
Cloned from:
https://github.com/tomaspinho/rtl8821ce

Signed-off-by: Thomas Backlund <tmb@mageia.org>

---
 3rdparty/rtl8821ce/Kconfig                                                     |    6 
 3rdparty/rtl8821ce/Makefile                                                    | 2313 ++++
 3rdparty/rtl8821ce/core/efuse/rtw_efuse.c                                      | 3302 ++++++
 3rdparty/rtl8821ce/core/mesh/rtw_mesh.c                                        | 4097 ++++++++
 3rdparty/rtl8821ce/core/mesh/rtw_mesh.h                                        |  534 +
 3rdparty/rtl8821ce/core/mesh/rtw_mesh_hwmp.c                                   | 1665 +++
 3rdparty/rtl8821ce/core/mesh/rtw_mesh_hwmp.h                                   |   60 
 3rdparty/rtl8821ce/core/mesh/rtw_mesh_pathtbl.c                                | 1185 ++
 3rdparty/rtl8821ce/core/mesh/rtw_mesh_pathtbl.h                                |  206 
 3rdparty/rtl8821ce/core/rtw_ap.c                                               | 5406 +++++++++++
 3rdparty/rtl8821ce/core/rtw_beamforming.c                                      | 3155 ++++++
 3rdparty/rtl8821ce/core/rtw_br_ext.c                                           | 1581 +++
 3rdparty/rtl8821ce/core/rtw_bt_mp.c                                            | 1575 +++
 3rdparty/rtl8821ce/core/rtw_btcoex.c                                           | 1763 +++
 3rdparty/rtl8821ce/core/rtw_btcoex_wifionly.c                                  |   47 
 3rdparty/rtl8821ce/core/rtw_chplan.c                                           | 1184 ++
 3rdparty/rtl8821ce/core/rtw_chplan.h                                           |  179 
 3rdparty/rtl8821ce/core/rtw_cmd.c                                              | 5354 +++++++++++
 3rdparty/rtl8821ce/core/rtw_debug.c                                            | 6721 +++++++++++++
 3rdparty/rtl8821ce/core/rtw_eeprom.c                                           |  369 
 3rdparty/rtl8821ce/core/rtw_ieee80211.c                                        | 2909 ++++++
 3rdparty/rtl8821ce/core/rtw_io.c                                               |  903 +
 3rdparty/rtl8821ce/core/rtw_ioctl_query.c                                      |  166 
 3rdparty/rtl8821ce/core/rtw_ioctl_rtl.c                                        |  901 +
 3rdparty/rtl8821ce/core/rtw_ioctl_set.c                                        |  919 +
 3rdparty/rtl8821ce/core/rtw_iol.c                                              |  394 
 3rdparty/rtl8821ce/core/rtw_mem.c                                              |  128 
 3rdparty/rtl8821ce/core/rtw_mi.c                                               | 1572 +++
 3rdparty/rtl8821ce/core/rtw_mlme.c                                             | 5319 ++++++++++
 3rdparty/rtl8821ce/core/rtw_mlme_ext.c                                         |16488 ++++++++++++++++++++++++++++++++++
 3rdparty/rtl8821ce/core/rtw_mp.c                                               | 3890 ++++++++
 3rdparty/rtl8821ce/core/rtw_mp_ioctl.c                                         | 2529 +++++
 3rdparty/rtl8821ce/core/rtw_odm.c                                              |  420 
 3rdparty/rtl8821ce/core/rtw_p2p.c                                              | 5455 +++++++++++
 3rdparty/rtl8821ce/core/rtw_pwrctrl.c                                          | 2780 +++++
 3rdparty/rtl8821ce/core/rtw_recv.c                                             | 5045 ++++++++++
 3rdparty/rtl8821ce/core/rtw_rf.c                                               | 1384 ++
 3rdparty/rtl8821ce/core/rtw_rm.c                                               | 2470 +++++
 3rdparty/rtl8821ce/core/rtw_rm_fsm.c                                           |  998 ++
 3rdparty/rtl8821ce/core/rtw_rson.c                                             |  595 +
 3rdparty/rtl8821ce/core/rtw_sdio.c                                             |  130 
 3rdparty/rtl8821ce/core/rtw_security.c                                         | 3408 +++++++
 3rdparty/rtl8821ce/core/rtw_sreset.c                                           |  314 
 3rdparty/rtl8821ce/core/rtw_sta_mgt.c                                          | 1330 ++
 3rdparty/rtl8821ce/core/rtw_tdls.c                                             | 3505 +++++++
 3rdparty/rtl8821ce/core/rtw_vht.c                                              | 1135 ++
 3rdparty/rtl8821ce/core/rtw_wapi.c                                             | 1312 ++
 3rdparty/rtl8821ce/core/rtw_wapi_sms4.c                                        |  922 +
 3rdparty/rtl8821ce/core/rtw_wlan_util.c                                        | 4941 ++++++++++
 3rdparty/rtl8821ce/core/rtw_xmit.c                                             | 5874 ++++++++++++
 3rdparty/rtl8821ce/hal/HalPwrSeqCmd.c                                          |  185 
 3rdparty/rtl8821ce/hal/btc/halbtc8192e1ant.c                                   | 3417 +++++++
 3rdparty/rtl8821ce/hal/btc/halbtc8192e1ant.h                                   |  226 
 3rdparty/rtl8821ce/hal/btc/halbtc8192e2ant.c                                   | 4252 ++++++++
 3rdparty/rtl8821ce/hal/btc/halbtc8192e2ant.h                                   |  216 
 3rdparty/rtl8821ce/hal/btc/halbtc8703b1ant.c                                   | 4263 ++++++++
 3rdparty/rtl8821ce/hal/btc/halbtc8703b1ant.h                                   |  399 
 3rdparty/rtl8821ce/hal/btc/halbtc8723b1ant.c                                   | 5113 ++++++++++
 3rdparty/rtl8821ce/hal/btc/halbtc8723b1ant.h                                   |  293 
 3rdparty/rtl8821ce/hal/btc/halbtc8723b2ant.c                                   | 4958 ++++++++++
 3rdparty/rtl8821ce/hal/btc/halbtc8723b2ant.h                                   |  217 
 3rdparty/rtl8821ce/hal/btc/halbtc8723bwifionly.c                               |   68 
 3rdparty/rtl8821ce/hal/btc/halbtc8723bwifionly.h                               |    8 
 3rdparty/rtl8821ce/hal/btc/halbtc8723d1ant.c                                   | 6293 +++++++++++++
 3rdparty/rtl8821ce/hal/btc/halbtc8723d1ant.h                                   |  413 
 3rdparty/rtl8821ce/hal/btc/halbtc8723d2ant.c                                   | 6838 ++++++++++++++
 3rdparty/rtl8821ce/hal/btc/halbtc8723d2ant.h                                   |  420 
 3rdparty/rtl8821ce/hal/btc/halbtc8812a1ant.c                                   | 3461 +++++++
 3rdparty/rtl8821ce/hal/btc/halbtc8812a1ant.h                                   |  230 
 3rdparty/rtl8821ce/hal/btc/halbtc8812a2ant.c                                   | 5624 +++++++++++
 3rdparty/rtl8821ce/hal/btc/halbtc8812a2ant.h                                   |  227 
 3rdparty/rtl8821ce/hal/btc/halbtc8821a1ant.c                                   | 3256 ++++++
 3rdparty/rtl8821ce/hal/btc/halbtc8821a1ant.h                                   |  214 
 3rdparty/rtl8821ce/hal/btc/halbtc8821a2ant.c                                   | 4584 +++++++++
 3rdparty/rtl8821ce/hal/btc/halbtc8821a2ant.h                                   |  211 
 3rdparty/rtl8821ce/hal/btc/halbtc8821c1ant.c                                   | 5492 +++++++++++
 3rdparty/rtl8821ce/hal/btc/halbtc8821c1ant.h                                   |  474 
 3rdparty/rtl8821ce/hal/btc/halbtc8821c2ant.c                                   | 6191 ++++++++++++
 3rdparty/rtl8821ce/hal/btc/halbtc8821c2ant.h                                   |  488 +
 3rdparty/rtl8821ce/hal/btc/halbtc8821cwifionly.c                               |  213 
 3rdparty/rtl8821ce/hal/btc/halbtc8821cwifionly.h                               |   89 
 3rdparty/rtl8821ce/hal/btc/halbtc8822b1ant.c                                   | 7002 ++++++++++++++
 3rdparty/rtl8821ce/hal/btc/halbtc8822b1ant.h                                   |  434 
 3rdparty/rtl8821ce/hal/btc/halbtc8822b2ant.c                                   | 5583 +++++++++++
 3rdparty/rtl8821ce/hal/btc/halbtc8822b2ant.h                                   |  493 +
 3rdparty/rtl8821ce/hal/btc/halbtc8822bwifionly.c                               |   54 
 3rdparty/rtl8821ce/hal/btc/halbtc8822bwifionly.h                               |   22 
 3rdparty/rtl8821ce/hal/btc/halbtcoutsrc.h                                      | 1276 ++
 3rdparty/rtl8821ce/hal/btc/mp_precomp.h                                        |  131 
 3rdparty/rtl8821ce/hal/efuse/efuse_mask.h                                      |  164 
 3rdparty/rtl8821ce/hal/efuse/rtl8821c/HalEfuseMask8821C_PCIE.c                 |   95 
 3rdparty/rtl8821ce/hal/efuse/rtl8821c/HalEfuseMask8821C_PCIE.h                 |   34 
 3rdparty/rtl8821ce/hal/efuse/rtl8821c/HalEfuseMask8821C_SDIO.c                 |   95 
 3rdparty/rtl8821ce/hal/efuse/rtl8821c/HalEfuseMask8821C_SDIO.h                 |   34 
 3rdparty/rtl8821ce/hal/efuse/rtl8821c/HalEfuseMask8821C_USB.c                  |   95 
 3rdparty/rtl8821ce/hal/efuse/rtl8821c/HalEfuseMask8821C_USB.h                  |   34 
 3rdparty/rtl8821ce/hal/hal_btcoex.c                                            | 5699 +++++++++++
 3rdparty/rtl8821ce/hal/hal_btcoex_wifionly.c                                   |  224 
 3rdparty/rtl8821ce/hal/hal_com.c                                               |14430 +++++++++++++++++++++++++++++
 3rdparty/rtl8821ce/hal/hal_com_c2h.h                                           |  123 
 3rdparty/rtl8821ce/hal/hal_com_phycfg.c                                        | 5407 +++++++++++
 3rdparty/rtl8821ce/hal/hal_dm.c                                                | 1470 +++
 3rdparty/rtl8821ce/hal/hal_dm.h                                                |  100 
 3rdparty/rtl8821ce/hal/hal_dm_acs.c                                            |  554 +
 3rdparty/rtl8821ce/hal/hal_dm_acs.h                                            |  167 
 3rdparty/rtl8821ce/hal/hal_halmac.c                                            | 5252 ++++++++++
 3rdparty/rtl8821ce/hal/hal_halmac.h                                            |  241 
 3rdparty/rtl8821ce/hal/hal_hci/hal_pci.c                                       |   18 
 3rdparty/rtl8821ce/hal/hal_intf.c                                              | 1705 +++
 3rdparty/rtl8821ce/hal/hal_mcc.c                                               | 3488 +++++++
 3rdparty/rtl8821ce/hal/hal_mp.c                                                | 2396 ++++
 3rdparty/rtl8821ce/hal/hal_phy.c                                               |  257 
 3rdparty/rtl8821ce/hal/halmac/halmac_2_platform.h                              |   87 
 3rdparty/rtl8821ce/hal/halmac/halmac_88xx/halmac_8821c/halmac_8821c_cfg.h      |   65 
 3rdparty/rtl8821ce/hal/halmac/halmac_88xx/halmac_8821c/halmac_8821c_phy.c      |   36 
 3rdparty/rtl8821ce/hal/halmac/halmac_88xx/halmac_8821c/halmac_8821c_pwr_seq.c  |  239 
 3rdparty/rtl8821ce/hal/halmac/halmac_88xx/halmac_8821c/halmac_8821c_pwr_seq.h  |   16 
 3rdparty/rtl8821ce/hal/halmac/halmac_88xx/halmac_8821c/halmac_api_8821c.c      |  287 
 3rdparty/rtl8821ce/hal/halmac/halmac_88xx/halmac_8821c/halmac_api_8821c.h      |   28 
 3rdparty/rtl8821ce/hal/halmac/halmac_88xx/halmac_8821c/halmac_api_8821c_pcie.c |  251 
 3rdparty/rtl8821ce/hal/halmac/halmac_88xx/halmac_8821c/halmac_api_8821c_pcie.h |   39 
 3rdparty/rtl8821ce/hal/halmac/halmac_88xx/halmac_8821c/halmac_api_8821c_sdio.c |  144 
 3rdparty/rtl8821ce/hal/halmac/halmac_88xx/halmac_8821c/halmac_api_8821c_sdio.h |   33 
 3rdparty/rtl8821ce/hal/halmac/halmac_88xx/halmac_8821c/halmac_api_8821c_usb.c  |  142 
 3rdparty/rtl8821ce/hal/halmac/halmac_88xx/halmac_8821c/halmac_api_8821c_usb.h  |   27 
 3rdparty/rtl8821ce/hal/halmac/halmac_88xx/halmac_8821c/halmac_cfg_wmac_8821c.c |  145 
 3rdparty/rtl8821ce/hal/halmac/halmac_88xx/halmac_8821c/halmac_cfg_wmac_8821c.h |   40 
 3rdparty/rtl8821ce/hal/halmac/halmac_88xx/halmac_8821c/halmac_common_8821c.c   |  182 
 3rdparty/rtl8821ce/hal/halmac/halmac_88xx/halmac_8821c/halmac_common_8821c.h   |   36 
 3rdparty/rtl8821ce/hal/halmac/halmac_88xx/halmac_8821c/halmac_func_8821c.c     |  311 
 3rdparty/rtl8821ce/hal/halmac/halmac_88xx/halmac_8821c/halmac_func_8821c.h     |   19 
 3rdparty/rtl8821ce/hal/halmac/halmac_88xx/halmac_8821c/halmac_gpio_8821c.c     |  846 +
 3rdparty/rtl8821ce/hal/halmac/halmac_88xx/halmac_8821c/halmac_gpio_8821c.h     |   37 
 3rdparty/rtl8821ce/hal/halmac/halmac_88xx/halmac_8821c/halmac_init_8821c.c     |  890 +
 3rdparty/rtl8821ce/hal/halmac/halmac_88xx/halmac_8821c/halmac_init_8821c.h     |   43 
 3rdparty/rtl8821ce/hal/halmac/halmac_88xx/halmac_8821c/halmac_pcie_8821c.c     |  356 
 3rdparty/rtl8821ce/hal/halmac/halmac_88xx/halmac_8821c/halmac_pcie_8821c.h     |   45 
 3rdparty/rtl8821ce/hal/halmac/halmac_88xx/halmac_8821c/halmac_phy_8821c.c      |   76 
 3rdparty/rtl8821ce/hal/halmac/halmac_88xx/halmac_8821c/halmac_pwr_seq_8821c.c  |  905 +
 3rdparty/rtl8821ce/hal/halmac/halmac_88xx/halmac_8821c/halmac_pwr_seq_8821c.h  |   37 
 3rdparty/rtl8821ce/hal/halmac/halmac_88xx/halmac_88xx_cfg.h                    |   44 
 3rdparty/rtl8821ce/hal/halmac/halmac_88xx/halmac_api_88xx.c                    | 5617 +++++++++++
 3rdparty/rtl8821ce/hal/halmac/halmac_88xx/halmac_api_88xx.h                    |  607 +
 3rdparty/rtl8821ce/hal/halmac/halmac_88xx/halmac_api_88xx_pcie.c               |  322 
 3rdparty/rtl8821ce/hal/halmac/halmac_88xx/halmac_api_88xx_pcie.h               |   76 
 3rdparty/rtl8821ce/hal/halmac/halmac_88xx/halmac_api_88xx_sdio.c               |  975 ++
 3rdparty/rtl8821ce/hal/halmac/halmac_88xx/halmac_api_88xx_sdio.h               |  118 
 3rdparty/rtl8821ce/hal/halmac/halmac_88xx/halmac_api_88xx_usb.c                |  563 +
 3rdparty/rtl8821ce/hal/halmac/halmac_88xx/halmac_api_88xx_usb.h                |   83 
 3rdparty/rtl8821ce/hal/halmac/halmac_88xx/halmac_bb_rf_88xx.c                  |  395 
 3rdparty/rtl8821ce/hal/halmac/halmac_88xx/halmac_bb_rf_88xx.h                  |   57 
 3rdparty/rtl8821ce/hal/halmac/halmac_88xx/halmac_cfg_wmac_88xx.c               | 1133 ++
 3rdparty/rtl8821ce/hal/halmac/halmac_88xx/halmac_cfg_wmac_88xx.h               |  126 
 3rdparty/rtl8821ce/hal/halmac/halmac_88xx/halmac_common_88xx.c                 | 2895 +++++
 3rdparty/rtl8821ce/hal/halmac/halmac_88xx/halmac_common_88xx.h                 |  155 
 3rdparty/rtl8821ce/hal/halmac/halmac_88xx/halmac_efuse_88xx.c                  | 1905 +++
 3rdparty/rtl8821ce/hal/halmac/halmac_88xx/halmac_efuse_88xx.h                  |  105 
 3rdparty/rtl8821ce/hal/halmac/halmac_88xx/halmac_flash_88xx.c                  |  316 
 3rdparty/rtl8821ce/hal/halmac/halmac_88xx/halmac_flash_88xx.h                  |   39 
 3rdparty/rtl8821ce/hal/halmac/halmac_88xx/halmac_func_88xx.c                   | 4323 ++++++++
 3rdparty/rtl8821ce/hal/halmac/halmac_88xx/halmac_func_88xx.h                   |  522 +
 3rdparty/rtl8821ce/hal/halmac/halmac_88xx/halmac_fw_88xx.c                     | 1167 ++
 3rdparty/rtl8821ce/hal/halmac/halmac_88xx/halmac_fw_88xx.h                     |   61 
 3rdparty/rtl8821ce/hal/halmac/halmac_88xx/halmac_gpio_88xx.c                   |  421 
 3rdparty/rtl8821ce/hal/halmac/halmac_88xx/halmac_gpio_88xx.h                   |   59 
 3rdparty/rtl8821ce/hal/halmac/halmac_88xx/halmac_init_88xx.c                   |  992 ++
 3rdparty/rtl8821ce/hal/halmac/halmac_88xx/halmac_init_88xx.h                   |   68 
 3rdparty/rtl8821ce/hal/halmac/halmac_88xx/halmac_mimo_88xx.c                   |  878 +
 3rdparty/rtl8821ce/hal/halmac/halmac_88xx/halmac_mimo_88xx.h                   |   83 
 3rdparty/rtl8821ce/hal/halmac/halmac_88xx/halmac_pcie_88xx.c                   |  537 +
 3rdparty/rtl8821ce/hal/halmac/halmac_88xx/halmac_pcie_88xx.h                   |  102 
 3rdparty/rtl8821ce/hal/halmac/halmac_api.c                                     |  622 +
 3rdparty/rtl8821ce/hal/halmac/halmac_api.h                                     |  120 
 3rdparty/rtl8821ce/hal/halmac/halmac_bit2.h                                    |73023 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
 3rdparty/rtl8821ce/hal/halmac/halmac_bit_8197f.h                               |17293 +++++++++++++++++++++++++++++++++++
 3rdparty/rtl8821ce/hal/halmac/halmac_bit_8814b.h                               |26515 ++++++++++++++++++++++++++++++++++++++++++++++++++++++
 3rdparty/rtl8821ce/hal/halmac/halmac_bit_8821c.h                               |19483 ++++++++++++++++++++++++++++++++++++++++
 3rdparty/rtl8821ce/hal/halmac/halmac_bit_8822b.h                               |17870 ++++++++++++++++++++++++++++++++++++
 3rdparty/rtl8821ce/hal/halmac/halmac_bit_8822c.h                               |21838 +++++++++++++++++++++++++++++++++++++++++++++
 3rdparty/rtl8821ce/hal/halmac/halmac_fw_info.h                                 |  119 
 3rdparty/rtl8821ce/hal/halmac/halmac_fw_offload_c2h_ap.h                       |  515 +
 3rdparty/rtl8821ce/hal/halmac/halmac_fw_offload_c2h_nic.h                      |  379 
 3rdparty/rtl8821ce/hal/halmac/halmac_fw_offload_h2c_ap.h                       |  989 ++
 3rdparty/rtl8821ce/hal/halmac/halmac_fw_offload_h2c_nic.h                      |  694 +
 3rdparty/rtl8821ce/hal/halmac/halmac_gpio_cmd.h                                |  101 
 3rdparty/rtl8821ce/hal/halmac/halmac_h2c_extra_info_ap.h                       |  220 
 3rdparty/rtl8821ce/hal/halmac/halmac_h2c_extra_info_nic.h                      |  171 
 3rdparty/rtl8821ce/hal/halmac/halmac_hw_cfg.h                                  |  200 
 3rdparty/rtl8821ce/hal/halmac/halmac_intf_phy_cmd.h                            |   45 
 3rdparty/rtl8821ce/hal/halmac/halmac_module.c                                  |  719 +
 3rdparty/rtl8821ce/hal/halmac/halmac_module.h                                  |  115 
 3rdparty/rtl8821ce/hal/halmac/halmac_original_c2h_ap.h                         |  650 +
 3rdparty/rtl8821ce/hal/halmac/halmac_original_c2h_nic.h                        |  434 
 3rdparty/rtl8821ce/hal/halmac/halmac_original_h2c_ap.h                         | 1661 +++
 3rdparty/rtl8821ce/hal/halmac/halmac_original_h2c_nic.h                        | 1143 ++
 3rdparty/rtl8821ce/hal/halmac/halmac_pcie_reg.h                                |   36 
 3rdparty/rtl8821ce/hal/halmac/halmac_pwr_seq_cmd.h                             |   98 
 3rdparty/rtl8821ce/hal/halmac/halmac_reg2.h                                    | 8184 ++++++++++++++++
 3rdparty/rtl8821ce/hal/halmac/halmac_reg_8197f.h                               |  700 +
 3rdparty/rtl8821ce/hal/halmac/halmac_reg_8814b.h                               | 1058 ++
 3rdparty/rtl8821ce/hal/halmac/halmac_reg_8821c.h                               |  803 +
 3rdparty/rtl8821ce/hal/halmac/halmac_reg_8822b.h                               |  733 +
 3rdparty/rtl8821ce/hal/halmac/halmac_reg_8822c.h                               |  877 +
 3rdparty/rtl8821ce/hal/halmac/halmac_rx_bd_ap.h                                |   25 
 3rdparty/rtl8821ce/hal/halmac/halmac_rx_bd_chip.h                              |  109 
 3rdparty/rtl8821ce/hal/halmac/halmac_rx_bd_nic.h                               |   41 
 3rdparty/rtl8821ce/hal/halmac/halmac_rx_desc_ap.h                              |  630 +
 3rdparty/rtl8821ce/hal/halmac/halmac_rx_desc_chip.h                            |  698 +
 3rdparty/rtl8821ce/hal/halmac/halmac_rx_desc_nic.h                             |  478 
 3rdparty/rtl8821ce/hal/halmac/halmac_sdio_reg.h                                |   55 
 3rdparty/rtl8821ce/hal/halmac/halmac_state_machine.h                           |  157 
 3rdparty/rtl8821ce/hal/halmac/halmac_tx_bd_ap.h                                |   95 
 3rdparty/rtl8821ce/hal/halmac/halmac_tx_bd_chip.h                              |  374 
 3rdparty/rtl8821ce/hal/halmac/halmac_tx_bd_nic.h                               |  111 
 3rdparty/rtl8821ce/hal/halmac/halmac_tx_desc_ap.h                              | 1942 ++++
 3rdparty/rtl8821ce/hal/halmac/halmac_tx_desc_buffer_ap.h                       | 1078 ++
 3rdparty/rtl8821ce/hal/halmac/halmac_tx_desc_buffer_chip.h                     |  509 +
 3rdparty/rtl8821ce/hal/halmac/halmac_tx_desc_buffer_nic.h                      |  491 +
 3rdparty/rtl8821ce/hal/halmac/halmac_tx_desc_chip.h                            | 2783 +++++
 3rdparty/rtl8821ce/hal/halmac/halmac_tx_desc_ie_ap.h                           | 1005 ++
 3rdparty/rtl8821ce/hal/halmac/halmac_tx_desc_ie_chip.h                         |  438 
 3rdparty/rtl8821ce/hal/halmac/halmac_tx_desc_ie_nic.h                          |  450 
 3rdparty/rtl8821ce/hal/halmac/halmac_tx_desc_nic.h                             | 1025 ++
 3rdparty/rtl8821ce/hal/halmac/halmac_type.h                                    | 2412 ++++
 3rdparty/rtl8821ce/hal/halmac/halmac_usb_reg.h                                 |   19 
 3rdparty/rtl8821ce/hal/led/hal_led.c                                           |  254 
 3rdparty/rtl8821ce/hal/led/hal_pci_led.c                                       | 2169 ++++
 3rdparty/rtl8821ce/hal/phydm/ap_makefile.mk                                    |  174 
 3rdparty/rtl8821ce/hal/phydm/halhwimg.h                                        |  137 
 3rdparty/rtl8821ce/hal/phydm/halphyrf_ap.c                                     | 2668 +++++
 3rdparty/rtl8821ce/hal/phydm/halphyrf_ap.h                                     |  178 
 3rdparty/rtl8821ce/hal/phydm/halphyrf_ce.c                                     |  837 +
 3rdparty/rtl8821ce/hal/phydm/halphyrf_ce.h                                     |  117 
 3rdparty/rtl8821ce/hal/phydm/halphyrf_win.c                                    |  821 +
 3rdparty/rtl8821ce/hal/phydm/halphyrf_win.h                                    |  119 
 3rdparty/rtl8821ce/hal/phydm/halrf/halphyrf_ap.c                               | 1340 ++
 3rdparty/rtl8821ce/hal/phydm/halrf/halphyrf_ap.h                               |  134 
 3rdparty/rtl8821ce/hal/phydm/halrf/halphyrf_ce.c                               |  918 +
 3rdparty/rtl8821ce/hal/phydm/halrf/halphyrf_ce.h                               |  110 
 3rdparty/rtl8821ce/hal/phydm/halrf/halphyrf_iot.c                              |  478 
 3rdparty/rtl8821ce/hal/phydm/halrf/halphyrf_iot.h                              |  124 
 3rdparty/rtl8821ce/hal/phydm/halrf/halphyrf_win.c                              |  836 +
 3rdparty/rtl8821ce/hal/phydm/halrf/halphyrf_win.h                              |  122 
 3rdparty/rtl8821ce/hal/phydm/halrf/halrf.c                                     | 1806 +++
 3rdparty/rtl8821ce/hal/phydm/halrf/halrf.h                                     |  471 
 3rdparty/rtl8821ce/hal/phydm/halrf/halrf_debug.c                               |  259 
 3rdparty/rtl8821ce/hal/phydm/halrf/halrf_debug.h                               |  123 
 3rdparty/rtl8821ce/hal/phydm/halrf/halrf_dpk.h                                 |   74 
 3rdparty/rtl8821ce/hal/phydm/halrf/halrf_features.h                            |   43 
 3rdparty/rtl8821ce/hal/phydm/halrf/halrf_iqk.h                                 |   92 
 3rdparty/rtl8821ce/hal/phydm/halrf/halrf_kfree.c                               | 1013 ++
 3rdparty/rtl8821ce/hal/phydm/halrf/halrf_kfree.h                               |  111 
 3rdparty/rtl8821ce/hal/phydm/halrf/halrf_powertracking.c                       |  152 
 3rdparty/rtl8821ce/hal/phydm/halrf/halrf_powertracking.h                       |   41 
 3rdparty/rtl8821ce/hal/phydm/halrf/halrf_powertracking_ap.c                    | 1219 ++
 3rdparty/rtl8821ce/hal/phydm/halrf/halrf_powertracking_ap.h                    |  397 
 3rdparty/rtl8821ce/hal/phydm/halrf/halrf_powertracking_ce.c                    |  840 +
 3rdparty/rtl8821ce/hal/phydm/halrf/halrf_powertracking_ce.h                    |  325 
 3rdparty/rtl8821ce/hal/phydm/halrf/halrf_powertracking_iot.c                   |  690 +
 3rdparty/rtl8821ce/hal/phydm/halrf/halrf_powertracking_iot.h                   |  347 
 3rdparty/rtl8821ce/hal/phydm/halrf/halrf_powertracking_win.c                   |  859 +
 3rdparty/rtl8821ce/hal/phydm/halrf/halrf_powertracking_win.h                   |  302 
 3rdparty/rtl8821ce/hal/phydm/halrf/halrf_psd.c                                 |  301 
 3rdparty/rtl8821ce/hal/phydm/halrf/halrf_psd.h                                 |   52 
 3rdparty/rtl8821ce/hal/phydm/halrf/halrf_txgapcal.c                            |  298 
 3rdparty/rtl8821ce/hal/phydm/halrf/halrf_txgapcal.h                            |   31 
 3rdparty/rtl8821ce/hal/phydm/halrf/rtl8821c/halrf_8821c.c                      |  469 
 3rdparty/rtl8821ce/hal/phydm/halrf/rtl8821c/halrf_8821c.h                      |   60 
 3rdparty/rtl8821ce/hal/phydm/halrf/rtl8821c/halrf_iqk_8821c.c                  | 3777 +++++++
 3rdparty/rtl8821ce/hal/phydm/halrf/rtl8821c/halrf_iqk_8821c.h                  |   62 
 3rdparty/rtl8821ce/hal/phydm/mp_precomp.h                                      |   24 
 3rdparty/rtl8821ce/hal/phydm/phydm.c                                           | 3168 ++++++
 3rdparty/rtl8821ce/hal/phydm/phydm.h                                           | 1340 ++
 3rdparty/rtl8821ce/hal/phydm/phydm.mk                                          |  217 
 3rdparty/rtl8821ce/hal/phydm/phydm_acs.c                                       | 1154 ++
 3rdparty/rtl8821ce/hal/phydm/phydm_acs.h                                       |  105 
 3rdparty/rtl8821ce/hal/phydm/phydm_adaptivity.c                                |  804 +
 3rdparty/rtl8821ce/hal/phydm/phydm_adaptivity.h                                |  134 
 3rdparty/rtl8821ce/hal/phydm/phydm_adc_sampling.c                              | 1076 ++
 3rdparty/rtl8821ce/hal/phydm/phydm_adc_sampling.h                              |  134 
 3rdparty/rtl8821ce/hal/phydm/phydm_antdect.c                                   |  891 +
 3rdparty/rtl8821ce/hal/phydm/phydm_antdect.h                                   |   78 
 3rdparty/rtl8821ce/hal/phydm/phydm_antdiv.c                                    | 5433 +++++++++++
 3rdparty/rtl8821ce/hal/phydm/phydm_antdiv.h                                    |  544 +
 3rdparty/rtl8821ce/hal/phydm/phydm_api.c                                       | 2410 ++++
 3rdparty/rtl8821ce/hal/phydm/phydm_api.h                                       |  168 
 3rdparty/rtl8821ce/hal/phydm/phydm_auto_dbg.c                                  |  671 +
 3rdparty/rtl8821ce/hal/phydm/phydm_auto_dbg.h                                  |  113 
 3rdparty/rtl8821ce/hal/phydm/phydm_beamforming.c                               | 2054 ++++
 3rdparty/rtl8821ce/hal/phydm/phydm_beamforming.h                               |  369 
 3rdparty/rtl8821ce/hal/phydm/phydm_cck_pd.c                                    | 1076 ++
 3rdparty/rtl8821ce/hal/phydm/phydm_cck_pd.h                                    |  154 
 3rdparty/rtl8821ce/hal/phydm/phydm_ccx.c                                       | 1839 +++
 3rdparty/rtl8821ce/hal/phydm/phydm_ccx.h                                       |  268 
 3rdparty/rtl8821ce/hal/phydm/phydm_cfotracking.c                               |  501 +
 3rdparty/rtl8821ce/hal/phydm/phydm_cfotracking.h                               |   67 
 3rdparty/rtl8821ce/hal/phydm/phydm_debug.c                                     | 4527 +++++++++
 3rdparty/rtl8821ce/hal/phydm/phydm_debug.h                                     |  444 
 3rdparty/rtl8821ce/hal/phydm/phydm_dfs.c                                       | 1700 +++
 3rdparty/rtl8821ce/hal/phydm/phydm_dfs.h                                       |  181 
 3rdparty/rtl8821ce/hal/phydm/phydm_dig.c                                       | 2729 +++++
 3rdparty/rtl8821ce/hal/phydm/phydm_dig.h                                       |  315 
 3rdparty/rtl8821ce/hal/phydm/phydm_dynamic_rx_path.c                           |  357 
 3rdparty/rtl8821ce/hal/phydm/phydm_dynamic_rx_path.h                           |  137 
 3rdparty/rtl8821ce/hal/phydm/phydm_dynamicbbpowersaving.c                      |  111 
 3rdparty/rtl8821ce/hal/phydm/phydm_dynamicbbpowersaving.h                      |   57 
 3rdparty/rtl8821ce/hal/phydm/phydm_dynamictxpower.c                            |  507 +
 3rdparty/rtl8821ce/hal/phydm/phydm_dynamictxpower.h                            |  103 
 3rdparty/rtl8821ce/hal/phydm/phydm_edcaturbocheck.c                            |  698 +
 3rdparty/rtl8821ce/hal/phydm/phydm_edcaturbocheck.h                            |  102 
 3rdparty/rtl8821ce/hal/phydm/phydm_features.h                                  |   58 
 3rdparty/rtl8821ce/hal/phydm/phydm_features_ap.h                               |  196 
 3rdparty/rtl8821ce/hal/phydm/phydm_features_ce.h                               |  205 
 3rdparty/rtl8821ce/hal/phydm/phydm_features_ce2_kernel.h                       |   84 
 3rdparty/rtl8821ce/hal/phydm/phydm_features_iot.h                              |  174 
 3rdparty/rtl8821ce/hal/phydm/phydm_features_win.h                              |  185 
 3rdparty/rtl8821ce/hal/phydm/phydm_hwconfig.c                                  | 1315 ++
 3rdparty/rtl8821ce/hal/phydm/phydm_hwconfig.h                                  |   79 
 3rdparty/rtl8821ce/hal/phydm/phydm_interface.c                                 | 1425 ++
 3rdparty/rtl8821ce/hal/phydm/phydm_interface.h                                 |  340 
 3rdparty/rtl8821ce/hal/phydm/phydm_iqk.h                                       |   65 
 3rdparty/rtl8821ce/hal/phydm/phydm_kfree.c                                     |  373 
 3rdparty/rtl8821ce/hal/phydm/phydm_kfree.h                                     |   87 
 3rdparty/rtl8821ce/hal/phydm/phydm_lna_sat.c                                   | 1354 ++
 3rdparty/rtl8821ce/hal/phydm/phydm_lna_sat.h                                   |  173 
 3rdparty/rtl8821ce/hal/phydm/phydm_math_lib.c                                  |  211 
 3rdparty/rtl8821ce/hal/phydm/phydm_math_lib.h                                  |  114 
 3rdparty/rtl8821ce/hal/phydm/phydm_mp.c                                        |  317 
 3rdparty/rtl8821ce/hal/phydm/phydm_mp.h                                        |   94 
 3rdparty/rtl8821ce/hal/phydm/phydm_noisemonitor.c                              |  457 
 3rdparty/rtl8821ce/hal/phydm/phydm_noisemonitor.h                              |   48 
 3rdparty/rtl8821ce/hal/phydm/phydm_pathdiv.c                                   |  628 +
 3rdparty/rtl8821ce/hal/phydm/phydm_pathdiv.h                                   |  117 
 3rdparty/rtl8821ce/hal/phydm/phydm_phystatus.c                                 | 3089 ++++++
 3rdparty/rtl8821ce/hal/phydm/phydm_phystatus.h                                 | 1137 ++
 3rdparty/rtl8821ce/hal/phydm/phydm_pmac_tx_setting.c                           |  522 +
 3rdparty/rtl8821ce/hal/phydm/phydm_pmac_tx_setting.h                           |  149 
 3rdparty/rtl8821ce/hal/phydm/phydm_pow_train.c                                 |  183 
 3rdparty/rtl8821ce/hal/phydm/phydm_pow_train.h                                 |   84 
 3rdparty/rtl8821ce/hal/phydm/phydm_powertracking_ap.c                          | 1249 ++
 3rdparty/rtl8821ce/hal/phydm/phydm_powertracking_ap.h                          |  355 
 3rdparty/rtl8821ce/hal/phydm/phydm_powertracking_ce.c                          |  824 +
 3rdparty/rtl8821ce/hal/phydm/phydm_powertracking_ce.h                          |  341 
 3rdparty/rtl8821ce/hal/phydm/phydm_powertracking_win.c                         |  854 +
 3rdparty/rtl8821ce/hal/phydm/phydm_powertracking_win.h                         |  308 
 3rdparty/rtl8821ce/hal/phydm/phydm_pre_define.h                                |  817 +
 3rdparty/rtl8821ce/hal/phydm/phydm_precomp.h                                   |  469 
 3rdparty/rtl8821ce/hal/phydm/phydm_primary_cca.c                               |  173 
 3rdparty/rtl8821ce/hal/phydm/phydm_primary_cca.h                               |   87 
 3rdparty/rtl8821ce/hal/phydm/phydm_psd.c                                       |  380 
 3rdparty/rtl8821ce/hal/phydm/phydm_psd.h                                       |   68 
 3rdparty/rtl8821ce/hal/phydm/phydm_rainfo.c                                    | 2134 ++++
 3rdparty/rtl8821ce/hal/phydm/phydm_rainfo.h                                    |  276 
 3rdparty/rtl8821ce/hal/phydm/phydm_reg.h                                       |  241 
 3rdparty/rtl8821ce/hal/phydm/phydm_regdefine11ac.h                             |  109 
 3rdparty/rtl8821ce/hal/phydm/phydm_regdefine11n.h                              |  219 
 3rdparty/rtl8821ce/hal/phydm/phydm_regtable.h                                  |  725 +
 3rdparty/rtl8821ce/hal/phydm/phydm_rssi_monitor.c                              |  170 
 3rdparty/rtl8821ce/hal/phydm/phydm_rssi_monitor.h                              |   55 
 3rdparty/rtl8821ce/hal/phydm/phydm_smt_ant.c                                   | 2253 ++++
 3rdparty/rtl8821ce/hal/phydm/phydm_smt_ant.h                                   |  210 
 3rdparty/rtl8821ce/hal/phydm/phydm_soml.c                                      |  963 +
 3rdparty/rtl8821ce/hal/phydm/phydm_soml.h                                      |  210 
 3rdparty/rtl8821ce/hal/phydm/phydm_types.h                                     |  316 
 3rdparty/rtl8821ce/hal/phydm/rtchnlplan.c                                      |  475 
 3rdparty/rtl8821ce/hal/phydm/rtchnlplan.h                                      |  682 +
 3rdparty/rtl8821ce/hal/phydm/rtl8821c/halhwimg8821c_bb.c                       | 4149 ++++++++
 3rdparty/rtl8821ce/hal/phydm/rtl8821c/halhwimg8821c_bb.h                       |   91 
 3rdparty/rtl8821ce/hal/phydm/rtl8821c/halhwimg8821c_fw.c                       |18444 ++++++++++++++++++++++++++++++++++++++
 3rdparty/rtl8821ce/hal/phydm/rtl8821c/halhwimg8821c_fw.h                       |   61 
 3rdparty/rtl8821ce/hal/phydm/rtl8821c/halhwimg8821c_mac.c                      |  316 
 3rdparty/rtl8821ce/hal/phydm/rtl8821c/halhwimg8821c_mac.h                      |   43 
 3rdparty/rtl8821ce/hal/phydm/rtl8821c/halhwimg8821c_rf.c                       | 4762 +++++++++
 3rdparty/rtl8821ce/hal/phydm/rtl8821c/halhwimg8821c_rf.h                       |   90 
 3rdparty/rtl8821ce/hal/phydm/rtl8821c/halhwimg8821c_testchip_bb.c              | 1925 +++
 3rdparty/rtl8821ce/hal/phydm/rtl8821c/halhwimg8821c_testchip_bb.h              |   58 
 3rdparty/rtl8821ce/hal/phydm/rtl8821c/halhwimg8821c_testchip_fw.c              |16138 +++++++++++++++++++++++++++++++++
 3rdparty/rtl8821ce/hal/phydm/rtl8821c/halhwimg8821c_testchip_fw.h              |   61 
 3rdparty/rtl8821ce/hal/phydm/rtl8821c/halhwimg8821c_testchip_mac.c             |  324 
 3rdparty/rtl8821ce/hal/phydm/rtl8821c/halhwimg8821c_testchip_mac.h             |   38 
 3rdparty/rtl8821ce/hal/phydm/rtl8821c/halhwimg8821c_testchip_rf.c              | 2304 ++++
 3rdparty/rtl8821ce/hal/phydm/rtl8821c/halhwimg8821c_testchip_rf.h              |   58 
 3rdparty/rtl8821ce/hal/phydm/rtl8821c/halphyrf_8821c.c                         |  486 +
 3rdparty/rtl8821ce/hal/phydm/rtl8821c/halphyrf_8821c.h                         |   83 
 3rdparty/rtl8821ce/hal/phydm/rtl8821c/mp_precomp.h                             |   14 
 3rdparty/rtl8821ce/hal/phydm/rtl8821c/phydm_hal_api8821c.c                     | 1370 ++
 3rdparty/rtl8821ce/hal/phydm/rtl8821c/phydm_hal_api8821c.h                     |  125 
 3rdparty/rtl8821ce/hal/phydm/rtl8821c/phydm_iqk_8821c.c                        | 2478 +++++
 3rdparty/rtl8821ce/hal/phydm/rtl8821c/phydm_iqk_8821c.h                        |   63 
 3rdparty/rtl8821ce/hal/phydm/rtl8821c/phydm_regconfig8821c.c                   |  248 
 3rdparty/rtl8821ce/hal/phydm/rtl8821c/phydm_regconfig8821c.h                   |   50 
 3rdparty/rtl8821ce/hal/phydm/rtl8821c/version_rtl8821c.h                       |   33 
 3rdparty/rtl8821ce/hal/phydm/sd4_phydm_2_kernel.mk                             |  188 
 3rdparty/rtl8821ce/hal/phydm/txbf/halcomtxbf.c                                 |  514 +
 3rdparty/rtl8821ce/hal/phydm/txbf/halcomtxbf.h                                 |  183 
 3rdparty/rtl8821ce/hal/phydm/txbf/haltxbf8192e.c                               |  382 
 3rdparty/rtl8821ce/hal/phydm/txbf/haltxbf8192e.h                               |   71 
 3rdparty/rtl8821ce/hal/phydm/txbf/haltxbf8814a.c                               |  675 +
 3rdparty/rtl8821ce/hal/phydm/txbf/haltxbf8814a.h                               |   77 
 3rdparty/rtl8821ce/hal/phydm/txbf/haltxbf8822b.c                               | 1087 ++
 3rdparty/rtl8821ce/hal/phydm/txbf/haltxbf8822b.h                               |   78 
 3rdparty/rtl8821ce/hal/phydm/txbf/haltxbfinterface.c                           | 1484 +++
 3rdparty/rtl8821ce/hal/phydm/txbf/haltxbfinterface.h                           |  167 
 3rdparty/rtl8821ce/hal/phydm/txbf/haltxbfjaguar.c                              |  508 +
 3rdparty/rtl8821ce/hal/phydm/txbf/haltxbfjaguar.h                              |   78 
 3rdparty/rtl8821ce/hal/phydm/txbf/phydm_hal_txbf_api.c                         |  183 
 3rdparty/rtl8821ce/hal/phydm/txbf/phydm_hal_txbf_api.h                         |   63 
 3rdparty/rtl8821ce/hal/rtl8821c/hal8821c_fw.c                                  |53340 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
 3rdparty/rtl8821ce/hal/rtl8821c/hal8821c_fw.h                                  |   42 
 3rdparty/rtl8821ce/hal/rtl8821c/pci/rtl8821ce.h                                |  127 
 3rdparty/rtl8821ce/hal/rtl8821c/pci/rtl8821ce_halinit.c                        |  381 
 3rdparty/rtl8821ce/hal/rtl8821c/pci/rtl8821ce_halmac.c                         |  382 
 3rdparty/rtl8821ce/hal/rtl8821c/pci/rtl8821ce_io.c                             |  348 
 3rdparty/rtl8821ce/hal/rtl8821c/pci/rtl8821ce_led.c                            |  161 
 3rdparty/rtl8821ce/hal/rtl8821c/pci/rtl8821ce_ops.c                            |  834 +
 3rdparty/rtl8821ce/hal/rtl8821c/pci/rtl8821ce_recv.c                           |  463 
 3rdparty/rtl8821ce/hal/rtl8821c/pci/rtl8821ce_xmit.c                           | 1671 +++
 3rdparty/rtl8821ce/hal/rtl8821c/rtl8821c.h                                     |  116 
 3rdparty/rtl8821ce/hal/rtl8821c/rtl8821c_cmd.c                                 |  460 
 3rdparty/rtl8821ce/hal/rtl8821c/rtl8821c_dm.c                                  |  264 
 3rdparty/rtl8821ce/hal/rtl8821c/rtl8821c_halinit.c                             |  354 
 3rdparty/rtl8821ce/hal/rtl8821c/rtl8821c_mac.c                                 |  182 
 3rdparty/rtl8821ce/hal/rtl8821c/rtl8821c_ops.c                                 | 3678 +++++++
 3rdparty/rtl8821ce/hal/rtl8821c/rtl8821c_phy.c                                 | 1457 +++
 3rdparty/rtl8821ce/halmac.mk                                                   |   68 
 3rdparty/rtl8821ce/include/Hal8188EPhyCfg.h                                    |  260 
 3rdparty/rtl8821ce/include/Hal8188EPhyReg.h                                    | 1100 ++
 3rdparty/rtl8821ce/include/Hal8188EPwrSeq.h                                    |  170 
 3rdparty/rtl8821ce/include/Hal8188FPhyCfg.h                                    |  134 
 3rdparty/rtl8821ce/include/Hal8188FPhyReg.h                                    | 1165 ++
 3rdparty/rtl8821ce/include/Hal8188FPwrSeq.h                                    |  212 
 3rdparty/rtl8821ce/include/Hal8192EPhyCfg.h                                    |  148 
 3rdparty/rtl8821ce/include/Hal8192EPhyReg.h                                    | 1146 ++
 3rdparty/rtl8821ce/include/Hal8192EPwrSeq.h                                    |  169 
 3rdparty/rtl8821ce/include/Hal8192FPhyCfg.h                                    |  131 
 3rdparty/rtl8821ce/include/Hal8192FPhyReg.h                                    | 1134 ++
 3rdparty/rtl8821ce/include/Hal8192FPwrSeq.h                                    |  221 
 3rdparty/rtl8821ce/include/Hal8703BPhyCfg.h                                    |  132 
 3rdparty/rtl8821ce/include/Hal8703BPhyReg.h                                    | 1133 ++
 3rdparty/rtl8821ce/include/Hal8703BPwrSeq.h                                    |  198 
 3rdparty/rtl8821ce/include/Hal8710BPhyCfg.h                                    |  127 
 3rdparty/rtl8821ce/include/Hal8710BPhyReg.h                                    | 1134 ++
 3rdparty/rtl8821ce/include/Hal8710BPwrSeq.h                                    |  167 
 3rdparty/rtl8821ce/include/Hal8723BPhyCfg.h                                    |  132 
 3rdparty/rtl8821ce/include/Hal8723BPhyReg.h                                    | 1131 ++
 3rdparty/rtl8821ce/include/Hal8723BPwrSeq.h                                    |  246 
 3rdparty/rtl8821ce/include/Hal8723DPhyCfg.h                                    |  131 
 3rdparty/rtl8821ce/include/Hal8723DPhyReg.h                                    | 1134 ++
 3rdparty/rtl8821ce/include/Hal8723DPwrSeq.h                                    |  206 
 3rdparty/rtl8821ce/include/Hal8723PwrSeq.h                                     |  183 
 3rdparty/rtl8821ce/include/Hal8812PhyCfg.h                                     |  143 
 3rdparty/rtl8821ce/include/Hal8812PhyReg.h                                     |  735 +
 3rdparty/rtl8821ce/include/Hal8812PwrSeq.h                                     |  208 
 3rdparty/rtl8821ce/include/Hal8814PhyCfg.h                                     |  264 
 3rdparty/rtl8821ce/include/Hal8814PhyReg.h                                     |  863 +
 3rdparty/rtl8821ce/include/Hal8814PwrSeq.h                                     |  231 
 3rdparty/rtl8821ce/include/Hal8821APwrSeq.h                                    |  200 
 3rdparty/rtl8821ce/include/HalPwrSeqCmd.h                                      |  130 
 3rdparty/rtl8821ce/include/HalVerDef.h                                         |  201 
 3rdparty/rtl8821ce/include/autoconf.h                                          |  305 
 3rdparty/rtl8821ce/include/basic_types.h                                       |  414 
 3rdparty/rtl8821ce/include/byteorder/big_endian.h                              |   82 
 3rdparty/rtl8821ce/include/byteorder/generic.h                                 |  207 
 3rdparty/rtl8821ce/include/byteorder/little_endian.h                           |   84 
 3rdparty/rtl8821ce/include/byteorder/swab.h                                    |  136 
 3rdparty/rtl8821ce/include/byteorder/swabb.h                                   |  151 
 3rdparty/rtl8821ce/include/circ_buf.h                                          |   23 
 3rdparty/rtl8821ce/include/cmd_osdep.h                                         |   26 
 3rdparty/rtl8821ce/include/cmn_info/rtw_sta_info.h                             |  250 
 3rdparty/rtl8821ce/include/custom_gpio.h                                       |   46 
 3rdparty/rtl8821ce/include/drv_conf.h                                          |  478 
 3rdparty/rtl8821ce/include/drv_types.h                                         | 1820 +++
 3rdparty/rtl8821ce/include/drv_types_ce.h                                      |   86 
 3rdparty/rtl8821ce/include/drv_types_gspi.h                                    |   49 
 3rdparty/rtl8821ce/include/drv_types_linux.h                                   |   19 
 3rdparty/rtl8821ce/include/drv_types_pci.h                                     |  266 
 3rdparty/rtl8821ce/include/drv_types_sdio.h                                    |   90 
 3rdparty/rtl8821ce/include/drv_types_xp.h                                      |   88 
 3rdparty/rtl8821ce/include/ethernet.h                                          |   36 
 3rdparty/rtl8821ce/include/gspi_hal.h                                          |   30 
 3rdparty/rtl8821ce/include/gspi_ops.h                                          |  180 
 3rdparty/rtl8821ce/include/gspi_ops_linux.h                                    |   18 
 3rdparty/rtl8821ce/include/gspi_osintf.h                                       |   25 
 3rdparty/rtl8821ce/include/h2clbk.h                                            |   26 
 3rdparty/rtl8821ce/include/hal_btcoex.h                                        |   97 
 3rdparty/rtl8821ce/include/hal_btcoex_wifionly.h                               |   81 
 3rdparty/rtl8821ce/include/hal_com.h                                           |  704 +
 3rdparty/rtl8821ce/include/hal_com_h2c.h                                       |  605 +
 3rdparty/rtl8821ce/include/hal_com_led.h                                       |  437 
 3rdparty/rtl8821ce/include/hal_com_phycfg.h                                    |  299 
 3rdparty/rtl8821ce/include/hal_com_reg.h                                       | 1873 +++
 3rdparty/rtl8821ce/include/hal_data.h                                          | 1061 ++
 3rdparty/rtl8821ce/include/hal_gspi.h                                          |   26 
 3rdparty/rtl8821ce/include/hal_ic_cfg.h                                        |  282 
 3rdparty/rtl8821ce/include/hal_intf.h                                          |  838 +
 3rdparty/rtl8821ce/include/hal_pg.h                                            |  880 +
 3rdparty/rtl8821ce/include/hal_phy.h                                           |  234 
 3rdparty/rtl8821ce/include/hal_phy_reg.h                                       |   25 
 3rdparty/rtl8821ce/include/hal_sdio.h                                          |   56 
 3rdparty/rtl8821ce/include/ieee80211.h                                         | 2172 ++++
 3rdparty/rtl8821ce/include/ieee80211_ext.h                                     |  471 
 3rdparty/rtl8821ce/include/if_ether.h                                          |  106 
 3rdparty/rtl8821ce/include/ip.h                                                |  135 
 3rdparty/rtl8821ce/include/linux/wireless.h                                    |   87 
 3rdparty/rtl8821ce/include/mlme_osdep.h                                        |   25 
 3rdparty/rtl8821ce/include/mp_custom_oid.h                                     |  348 
 3rdparty/rtl8821ce/include/nic_spec.h                                          |   41 
 3rdparty/rtl8821ce/include/osdep_intf.h                                        |  167 
 3rdparty/rtl8821ce/include/osdep_service.h                                     |  794 +
 3rdparty/rtl8821ce/include/osdep_service_bsd.h                                 |  756 +
 3rdparty/rtl8821ce/include/osdep_service_ce.h                                  |  200 
 3rdparty/rtl8821ce/include/osdep_service_linux.h                               |  539 +
 3rdparty/rtl8821ce/include/osdep_service_xp.h                                  |  210 
 3rdparty/rtl8821ce/include/pci_hal.h                                           |   52 
 3rdparty/rtl8821ce/include/pci_ops.h                                           |  102 
 3rdparty/rtl8821ce/include/pci_osintf.h                                        |   50 
 3rdparty/rtl8821ce/include/recv_osdep.h                                        |   67 
 3rdparty/rtl8821ce/include/rtl8188e_cmd.h                                      |  165 
 3rdparty/rtl8821ce/include/rtl8188e_dm.h                                       |   27 
 3rdparty/rtl8821ce/include/rtl8188e_hal.h                                      |  316 
 3rdparty/rtl8821ce/include/rtl8188e_led.h                                      |   37 
 3rdparty/rtl8821ce/include/rtl8188e_recv.h                                     |  161 
 3rdparty/rtl8821ce/include/rtl8188e_rf.h                                       |   27 
 3rdparty/rtl8821ce/include/rtl8188e_spec.h                                     |  159 
 3rdparty/rtl8821ce/include/rtl8188e_sreset.h                                   |   24 
 3rdparty/rtl8821ce/include/rtl8188e_xmit.h                                     |  295 
 3rdparty/rtl8821ce/include/rtl8188f_cmd.h                                      |  206 
 3rdparty/rtl8821ce/include/rtl8188f_dm.h                                       |   39 
 3rdparty/rtl8821ce/include/rtl8188f_hal.h                                      |  260 
 3rdparty/rtl8821ce/include/rtl8188f_led.h                                      |   45 
 3rdparty/rtl8821ce/include/rtl8188f_recv.h                                     |   68 
 3rdparty/rtl8821ce/include/rtl8188f_rf.h                                       |   25 
 3rdparty/rtl8821ce/include/rtl8188f_spec.h                                     |  275 
 3rdparty/rtl8821ce/include/rtl8188f_sreset.h                                   |   24 
 3rdparty/rtl8821ce/include/rtl8188f_xmit.h                                     |  336 
 3rdparty/rtl8821ce/include/rtl8192e_cmd.h                                      |  147 
 3rdparty/rtl8821ce/include/rtl8192e_dm.h                                       |   28 
 3rdparty/rtl8821ce/include/rtl8192e_hal.h                                      |  330 
 3rdparty/rtl8821ce/include/rtl8192e_led.h                                      |   36 
 3rdparty/rtl8821ce/include/rtl8192e_recv.h                                     |  179 
 3rdparty/rtl8821ce/include/rtl8192e_rf.h                                       |   28 
 3rdparty/rtl8821ce/include/rtl8192e_spec.h                                     |  313 
 3rdparty/rtl8821ce/include/rtl8192e_sreset.h                                   |   24 
 3rdparty/rtl8821ce/include/rtl8192e_xmit.h                                     |  450 
 3rdparty/rtl8821ce/include/rtl8192f_cmd.h                                      |  194 
 3rdparty/rtl8821ce/include/rtl8192f_dm.h                                       |   28 
 3rdparty/rtl8821ce/include/rtl8192f_hal.h                                      |  315 
 3rdparty/rtl8821ce/include/rtl8192f_led.h                                      |   42 
 3rdparty/rtl8821ce/include/rtl8192f_recv.h                                     |  111 
 3rdparty/rtl8821ce/include/rtl8192f_rf.h                                       |   22 
 3rdparty/rtl8821ce/include/rtl8192f_spec.h                                     |  534 +
 3rdparty/rtl8821ce/include/rtl8192f_sreset.h                                   |   24 
 3rdparty/rtl8821ce/include/rtl8192f_xmit.h                                     |  531 +
 3rdparty/rtl8821ce/include/rtl8703b_cmd.h                                      |  205 
 3rdparty/rtl8821ce/include/rtl8703b_dm.h                                       |   39 
 3rdparty/rtl8821ce/include/rtl8703b_hal.h                                      |  266 
 3rdparty/rtl8821ce/include/rtl8703b_led.h                                      |   44 
 3rdparty/rtl8821ce/include/rtl8703b_recv.h                                     |   86 
 3rdparty/rtl8821ce/include/rtl8703b_rf.h                                       |   25 
 3rdparty/rtl8821ce/include/rtl8703b_spec.h                                     |  464 
 3rdparty/rtl8821ce/include/rtl8703b_sreset.h                                   |   24 
 3rdparty/rtl8821ce/include/rtl8703b_xmit.h                                     |  335 
 3rdparty/rtl8821ce/include/rtl8710b_cmd.h                                      |  175 
 3rdparty/rtl8821ce/include/rtl8710b_dm.h                                       |   39 
 3rdparty/rtl8821ce/include/rtl8710b_hal.h                                      |  277 
 3rdparty/rtl8821ce/include/rtl8710b_led.h                                      |   44 
 3rdparty/rtl8821ce/include/rtl8710b_lps_poff.h                                 |   56 
 3rdparty/rtl8821ce/include/rtl8710b_recv.h                                     |   85 
 3rdparty/rtl8821ce/include/rtl8710b_rf.h                                       |   20 
 3rdparty/rtl8821ce/include/rtl8710b_spec.h                                     |  481 
 3rdparty/rtl8821ce/include/rtl8710b_sreset.h                                   |   24 
 3rdparty/rtl8821ce/include/rtl8710b_xmit.h                                     |  522 +
 3rdparty/rtl8821ce/include/rtl8723b_cmd.h                                      |  205 
 3rdparty/rtl8821ce/include/rtl8723b_dm.h                                       |   38 
 3rdparty/rtl8821ce/include/rtl8723b_hal.h                                      |  274 
 3rdparty/rtl8821ce/include/rtl8723b_led.h                                      |   44 
 3rdparty/rtl8821ce/include/rtl8723b_recv.h                                     |   86 
 3rdparty/rtl8821ce/include/rtl8723b_rf.h                                       |   25 
 3rdparty/rtl8821ce/include/rtl8723b_spec.h                                     |  280 
 3rdparty/rtl8821ce/include/rtl8723b_sreset.h                                   |   24 
 3rdparty/rtl8821ce/include/rtl8723b_xmit.h                                     |  335 
 3rdparty/rtl8821ce/include/rtl8723d_cmd.h                                      |  189 
 3rdparty/rtl8821ce/include/rtl8723d_dm.h                                       |   39 
 3rdparty/rtl8821ce/include/rtl8723d_hal.h                                      |  303 
 3rdparty/rtl8821ce/include/rtl8723d_led.h                                      |   44 
 3rdparty/rtl8821ce/include/rtl8723d_lps_poff.h                                 |   56 
 3rdparty/rtl8821ce/include/rtl8723d_recv.h                                     |  116 
 3rdparty/rtl8821ce/include/rtl8723d_rf.h                                       |   21 
 3rdparty/rtl8821ce/include/rtl8723d_spec.h                                     |  447 
 3rdparty/rtl8821ce/include/rtl8723d_sreset.h                                   |   24 
 3rdparty/rtl8821ce/include/rtl8723d_xmit.h                                     |  523 +
 3rdparty/rtl8821ce/include/rtl8812a_cmd.h                                      |  158 
 3rdparty/rtl8821ce/include/rtl8812a_dm.h                                       |   27 
 3rdparty/rtl8821ce/include/rtl8812a_hal.h                                      |  369 
 3rdparty/rtl8821ce/include/rtl8812a_led.h                                      |   41 
 3rdparty/rtl8821ce/include/rtl8812a_recv.h                                     |  153 
 3rdparty/rtl8821ce/include/rtl8812a_rf.h                                       |   28 
 3rdparty/rtl8821ce/include/rtl8812a_spec.h                                     |  263 
 3rdparty/rtl8821ce/include/rtl8812a_sreset.h                                   |   24 
 3rdparty/rtl8821ce/include/rtl8812a_xmit.h                                     |  367 
 3rdparty/rtl8821ce/include/rtl8814a_cmd.h                                      |  162 
 3rdparty/rtl8821ce/include/rtl8814a_dm.h                                       |   23 
 3rdparty/rtl8821ce/include/rtl8814a_hal.h                                      |  330 
 3rdparty/rtl8821ce/include/rtl8814a_led.h                                      |   36 
 3rdparty/rtl8821ce/include/rtl8814a_recv.h                                     |  186 
 3rdparty/rtl8821ce/include/rtl8814a_rf.h                                       |   28 
 3rdparty/rtl8821ce/include/rtl8814a_spec.h                                     |  648 +
 3rdparty/rtl8821ce/include/rtl8814a_sreset.h                                   |   24 
 3rdparty/rtl8821ce/include/rtl8814a_xmit.h                                     |  311 
 3rdparty/rtl8821ce/include/rtl8821a_spec.h                                     |   90 
 3rdparty/rtl8821ce/include/rtl8821a_xmit.h                                     |  173 
 3rdparty/rtl8821ce/include/rtl8821c_dm.h                                       |   23 
 3rdparty/rtl8821ce/include/rtl8821c_hal.h                                      |   84 
 3rdparty/rtl8821ce/include/rtl8821c_spec.h                                     |  202 
 3rdparty/rtl8821ce/include/rtl8821ce_hal.h                                     |   23 
 3rdparty/rtl8821ce/include/rtl8821cs_hal.h                                     |   23 
 3rdparty/rtl8821ce/include/rtl8821cu_hal.h                                     |   24 
 3rdparty/rtl8821ce/include/rtl8822b_hal.h                                      |  230 
 3rdparty/rtl8821ce/include/rtl8822be_hal.h                                     |   27 
 3rdparty/rtl8821ce/include/rtl8822bs_hal.h                                     |   31 
 3rdparty/rtl8821ce/include/rtl8822bu_hal.h                                     |   65 
 3rdparty/rtl8821ce/include/rtw_android.h                                       |  111 
 3rdparty/rtl8821ce/include/rtw_ap.h                                            |  112 
 3rdparty/rtl8821ce/include/rtw_beamforming.h                                   |  401 
 3rdparty/rtl8821ce/include/rtw_br_ext.h                                        |   69 
 3rdparty/rtl8821ce/include/rtw_bt_mp.h                                         |  288 
 3rdparty/rtl8821ce/include/rtw_btcoex.h                                        |  455 
 3rdparty/rtl8821ce/include/rtw_btcoex_wifionly.h                               |   24 
 3rdparty/rtl8821ce/include/rtw_byteorder.h                                     |   33 
 3rdparty/rtl8821ce/include/rtw_cmd.h                                           | 1328 ++
 3rdparty/rtl8821ce/include/rtw_debug.h                                         |  628 +
 3rdparty/rtl8821ce/include/rtw_eeprom.h                                        |  116 
 3rdparty/rtl8821ce/include/rtw_efuse.h                                         |  255 
 3rdparty/rtl8821ce/include/rtw_event.h                                         |  130 
 3rdparty/rtl8821ce/include/rtw_ht.h                                            |  217 
 3rdparty/rtl8821ce/include/rtw_io.h                                            |  569 +
 3rdparty/rtl8821ce/include/rtw_ioctl.h                                         |  319 
 3rdparty/rtl8821ce/include/rtw_ioctl_query.h                                   |   25 
 3rdparty/rtl8821ce/include/rtw_ioctl_rtl.h                                     |   75 
 3rdparty/rtl8821ce/include/rtw_ioctl_set.h                                     |   67 
 3rdparty/rtl8821ce/include/rtw_iol.h                                           |  131 
 3rdparty/rtl8821ce/include/rtw_mcc.h                                           |  271 
 3rdparty/rtl8821ce/include/rtw_mem.h                                           |   36 
 3rdparty/rtl8821ce/include/rtw_mi.h                                            |  306 
 3rdparty/rtl8821ce/include/rtw_mlme.h                                          | 1421 ++
 3rdparty/rtl8821ce/include/rtw_mlme_ext.h                                      | 1280 ++
 3rdparty/rtl8821ce/include/rtw_mp.h                                            |  938 +
 3rdparty/rtl8821ce/include/rtw_mp_ioctl.h                                      |  570 +
 3rdparty/rtl8821ce/include/rtw_mp_phy_regdef.h                                 | 1094 ++
 3rdparty/rtl8821ce/include/rtw_odm.h                                           |   97 
 3rdparty/rtl8821ce/include/rtw_p2p.h                                           |  169 
 3rdparty/rtl8821ce/include/rtw_pwrctrl.h                                       |  608 +
 3rdparty/rtl8821ce/include/rtw_qos.h                                           |   66 
 3rdparty/rtl8821ce/include/rtw_recv.h                                          |  878 +
 3rdparty/rtl8821ce/include/rtw_rf.h                                            |  238 
 3rdparty/rtl8821ce/include/rtw_rm.h                                            |   88 
 3rdparty/rtl8821ce/include/rtw_rm_fsm.h                                        |  389 
 3rdparty/rtl8821ce/include/rtw_rson.h                                          |   61 
 3rdparty/rtl8821ce/include/rtw_sdio.h                                          |   26 
 3rdparty/rtl8821ce/include/rtw_security.h                                      |  497 +
 3rdparty/rtl8821ce/include/rtw_sreset.h                                        |   66 
 3rdparty/rtl8821ce/include/rtw_tdls.h                                          |  185 
 3rdparty/rtl8821ce/include/rtw_version.h                                       |    2 
 3rdparty/rtl8821ce/include/rtw_vht.h                                           |  176 
 3rdparty/rtl8821ce/include/rtw_wapi.h                                          |  230 
 3rdparty/rtl8821ce/include/rtw_wifi_regd.h                                     |   34 
 3rdparty/rtl8821ce/include/rtw_xmit.h                                          | 1051 ++
 3rdparty/rtl8821ce/include/sdio_hal.h                                          |   57 
 3rdparty/rtl8821ce/include/sdio_ops.h                                          |  224 
 3rdparty/rtl8821ce/include/sdio_ops_ce.h                                       |   49 
 3rdparty/rtl8821ce/include/sdio_ops_linux.h                                    |   58 
 3rdparty/rtl8821ce/include/sdio_ops_xp.h                                       |   49 
 3rdparty/rtl8821ce/include/sdio_osintf.h                                       |   25 
 3rdparty/rtl8821ce/include/sta_info.h                                          |  741 +
 3rdparty/rtl8821ce/include/usb_hal.h                                           |   74 
 3rdparty/rtl8821ce/include/usb_ops.h                                           |  153 
 3rdparty/rtl8821ce/include/usb_ops_linux.h                                     |   98 
 3rdparty/rtl8821ce/include/usb_osintf.h                                        |   26 
 3rdparty/rtl8821ce/include/usb_vendor_req.h                                    |   56 
 3rdparty/rtl8821ce/include/wifi.h                                              | 1418 ++
 3rdparty/rtl8821ce/include/wlan_bssdef.h                                       |  705 +
 3rdparty/rtl8821ce/include/xmit_osdep.h                                        |   94 
 3rdparty/rtl8821ce/os_dep/linux/custom_gpio_linux.c                            |  340 
 3rdparty/rtl8821ce/os_dep/linux/ioctl_cfg80211.c                               | 9977 ++++++++++++++++++++
 3rdparty/rtl8821ce/os_dep/linux/ioctl_cfg80211.h                               |  409 
 3rdparty/rtl8821ce/os_dep/linux/ioctl_linux.c                                  |12868 ++++++++++++++++++++++++++
 3rdparty/rtl8821ce/os_dep/linux/ioctl_mp.c                                     | 2658 +++++
 3rdparty/rtl8821ce/os_dep/linux/mlme_linux.c                                   |  432 
 3rdparty/rtl8821ce/os_dep/linux/os_intfs.c                                     | 5181 ++++++++++
 3rdparty/rtl8821ce/os_dep/linux/pci_intf.c                                     | 2081 ++++
 3rdparty/rtl8821ce/os_dep/linux/pci_ops_linux.c                                |   17 
 3rdparty/rtl8821ce/os_dep/linux/recv_linux.c                                   |  734 +
 3rdparty/rtl8821ce/os_dep/linux/rhashtable.c                                   |  844 +
 3rdparty/rtl8821ce/os_dep/linux/rhashtable.h                                   |  827 +
 3rdparty/rtl8821ce/os_dep/linux/rtw_android.c                                  | 1325 ++
 3rdparty/rtl8821ce/os_dep/linux/rtw_cfgvendor.c                                | 2148 ++++
 3rdparty/rtl8821ce/os_dep/linux/rtw_cfgvendor.h                                |  633 +
 3rdparty/rtl8821ce/os_dep/linux/rtw_proc.c                                     | 4483 +++++++++
 3rdparty/rtl8821ce/os_dep/linux/rtw_proc.h                                     |   60 
 3rdparty/rtl8821ce/os_dep/linux/rtw_rhashtable.c                               |   74 
 3rdparty/rtl8821ce/os_dep/linux/rtw_rhashtable.h                               |   55 
 3rdparty/rtl8821ce/os_dep/linux/wifi_regd.c                                    |  424 
 3rdparty/rtl8821ce/os_dep/linux/xmit_linux.c                                   |  574 +
 3rdparty/rtl8821ce/os_dep/osdep_service.c                                      | 3136 ++++++
 3rdparty/rtl8821ce/platform/custom_country_chplan.h                            |   22 
 3rdparty/rtl8821ce/platform/platform_ARM_SUN50IW1P1_sdio.c                     |   86 
 3rdparty/rtl8821ce/platform/platform_ARM_SUNnI_sdio.c                          |  130 
 3rdparty/rtl8821ce/platform/platform_ARM_SUNxI_sdio.c                          |   90 
 3rdparty/rtl8821ce/platform/platform_ARM_SUNxI_usb.c                           |  136 
 3rdparty/rtl8821ce/platform/platform_ARM_WMT_sdio.c                            |   46 
 3rdparty/rtl8821ce/platform/platform_RTK_DMP_usb.c                             |   30 
 3rdparty/rtl8821ce/platform/platform_aml_s905_sdio.c                           |   54 
 3rdparty/rtl8821ce/platform/platform_aml_s905_sdio.h                           |   28 
 3rdparty/rtl8821ce/platform/platform_arm_act_sdio.c                            |   53 
 3rdparty/rtl8821ce/platform/platform_hisilicon_hi3798_sdio.c                   |  110 
 3rdparty/rtl8821ce/platform/platform_hisilicon_hi3798_sdio.h                   |   28 
 3rdparty/rtl8821ce/platform/platform_ops.c                                     |   32 
 3rdparty/rtl8821ce/platform/platform_ops.h                                     |   26 
 3rdparty/rtl8821ce/platform/platform_sprd_sdio.c                               |   84 
 3rdparty/rtl8821ce/platform/platform_zte_zx296716_sdio.c                       |   53 
 3rdparty/rtl8821ce/platform/platform_zte_zx296716_sdio.h                       |   25 
 3rdparty/rtl8821ce/rtl8821c.mk                                                 |   45 
 722 files changed, 821672 insertions(+)

diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/core/efuse/rtw_efuse.c linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/core/efuse/rtw_efuse.c
--- linux-5.6.3/3rdparty/rtl8821ce/core/efuse/rtw_efuse.c	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/core/efuse/rtw_efuse.c	2020-04-10 16:35:06.769657873 +0300
@@ -0,0 +1,3302 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#define _RTW_EFUSE_C_
+
+#include <drv_types.h>
+#include <hal_data.h>
+
+#include "../hal/efuse/efuse_mask.h"
+
+/*------------------------Define local variable------------------------------*/
+u8	fakeEfuseBank = {0};
+u32	fakeEfuseUsedBytes = {0};
+u8	fakeEfuseContent[EFUSE_MAX_HW_SIZE] = {0};
+u8	fakeEfuseInitMap[EFUSE_MAX_MAP_LEN] = {0};
+u8	fakeEfuseModifiedMap[EFUSE_MAX_MAP_LEN] = {0};
+
+u32	BTEfuseUsedBytes = {0};
+u8	BTEfuseContent[EFUSE_MAX_BT_BANK][EFUSE_MAX_HW_SIZE];
+u8	BTEfuseInitMap[EFUSE_BT_MAX_MAP_LEN] = {0};
+u8	BTEfuseModifiedMap[EFUSE_BT_MAX_MAP_LEN] = {0};
+
+u32	fakeBTEfuseUsedBytes = {0};
+u8	fakeBTEfuseContent[EFUSE_MAX_BT_BANK][EFUSE_MAX_HW_SIZE];
+u8	fakeBTEfuseInitMap[EFUSE_BT_MAX_MAP_LEN] = {0};
+u8	fakeBTEfuseModifiedMap[EFUSE_BT_MAX_MAP_LEN] = {0};
+
+u8	maskfileBuffer[64];
+/*------------------------Define local variable------------------------------*/
+BOOLEAN rtw_file_efuse_IsMasked(PADAPTER pAdapter, u16 Offset)
+{
+	int r = Offset / 16;
+	int c = (Offset % 16) / 2;
+	int result = 0;
+
+	if (pAdapter->registrypriv.boffefusemask)
+		return FALSE;
+
+	if (c < 4) /* Upper double word */
+		result = (maskfileBuffer[r] & (0x10 << c));
+	else
+		result = (maskfileBuffer[r] & (0x01 << (c - 4)));
+
+	return (result > 0) ? 0 : 1;
+}
+
+BOOLEAN efuse_IsMasked(PADAPTER pAdapter, u16 Offset)
+{
+	PHAL_DATA_TYPE pHalData = GET_HAL_DATA(pAdapter);
+
+	if (pAdapter->registrypriv.boffefusemask)
+		return FALSE;
+
+#ifdef CONFIG_USB_HCI
+#if defined(CONFIG_RTL8188E)
+	if (IS_HARDWARE_TYPE_8188E(pAdapter))
+		return (IS_MASKED(8188E, _MUSB, Offset)) ? TRUE : FALSE;
+#endif
+#if defined(CONFIG_RTL8812A)
+	if (IS_HARDWARE_TYPE_8812(pAdapter))
+		return (IS_MASKED(8812A, _MUSB, Offset)) ? TRUE : FALSE;
+#endif
+#if defined(CONFIG_RTL8821A)
+#if 0
+	if (IS_HARDWARE_TYPE_8811AU(pAdapter))
+		return (IS_MASKED(8811A, _MUSB, Offset)) ? TRUE : FALSE;
+#endif
+	if (IS_HARDWARE_TYPE_8821(pAdapter))
+		return (IS_MASKED(8821A, _MUSB, Offset)) ? TRUE : FALSE;
+#endif
+#if defined(CONFIG_RTL8192E)
+	if (IS_HARDWARE_TYPE_8192E(pAdapter))
+		return (IS_MASKED(8192E, _MUSB, Offset)) ? TRUE : FALSE;
+#endif
+#if defined(CONFIG_RTL8723B)
+	if (IS_HARDWARE_TYPE_8723B(pAdapter))
+		return (IS_MASKED(8723B, _MUSB, Offset)) ? TRUE : FALSE;
+#endif
+#if defined(CONFIG_RTL8703B)
+	if (IS_HARDWARE_TYPE_8703B(pAdapter))
+		return (IS_MASKED(8703B, _MUSB, Offset)) ? TRUE : FALSE;
+#endif
+#if defined(CONFIG_RTL8814A)
+	if (IS_HARDWARE_TYPE_8814A(pAdapter))
+		return (IS_MASKED(8814A, _MUSB, Offset)) ? TRUE : FALSE;
+#endif
+#if defined(CONFIG_RTL8188F)
+	if (IS_HARDWARE_TYPE_8188F(pAdapter))
+		return (IS_MASKED(8188F, _MUSB, Offset)) ? TRUE : FALSE;
+#endif
+#if defined(CONFIG_RTL8188GTV)
+	if (IS_HARDWARE_TYPE_8188GTV(pAdapter))
+		return (IS_MASKED(8188GTV, _MUSB, Offset)) ? TRUE : FALSE;
+#endif
+#if defined(CONFIG_RTL8822B)
+	if (IS_HARDWARE_TYPE_8822B(pAdapter))
+		return (IS_MASKED(8822B, _MUSB, Offset)) ? TRUE : FALSE;
+#endif
+#if defined(CONFIG_RTL8723D)
+	if (IS_HARDWARE_TYPE_8723D(pAdapter))
+		return (IS_MASKED(8723D, _MUSB, Offset)) ? TRUE : FALSE;
+#endif
+#if defined(CONFIG_RTL8710B)
+	if (IS_HARDWARE_TYPE_8710B(pAdapter))
+		return (IS_MASKED(8710B, _MUSB, Offset)) ? TRUE : FALSE;
+#endif
+#if defined(CONFIG_RTL8821C)
+	if (IS_HARDWARE_TYPE_8821CU(pAdapter))
+		return (IS_MASKED(8821C, _MUSB, Offset)) ? TRUE : FALSE;
+#endif
+
+#if defined(CONFIG_RTL8192F)
+	if (IS_HARDWARE_TYPE_8192FU(pAdapter))
+		return (IS_MASKED(8192F, _MUSB, Offset)) ? TRUE : FALSE;
+#endif
+#endif /*CONFIG_USB_HCI*/
+
+#ifdef CONFIG_PCI_HCI
+#if defined(CONFIG_RTL8188E)
+	if (IS_HARDWARE_TYPE_8188E(pAdapter))
+		return (IS_MASKED(8188E, _MPCIE, Offset)) ? TRUE : FALSE;
+#endif
+#if defined(CONFIG_RTL8192E)
+	if (IS_HARDWARE_TYPE_8192E(pAdapter))
+		return (IS_MASKED(8192E, _MPCIE, Offset)) ? TRUE : FALSE;
+#endif
+#if defined(CONFIG_RTL8812A)
+	if (IS_HARDWARE_TYPE_8812(pAdapter))
+		return (IS_MASKED(8812A, _MPCIE, Offset)) ? TRUE : FALSE;
+#endif
+#if defined(CONFIG_RTL8821A)
+	if (IS_HARDWARE_TYPE_8821(pAdapter))
+		return (IS_MASKED(8821A, _MPCIE, Offset)) ? TRUE : FALSE;
+#endif
+#if defined(CONFIG_RTL8723B)
+	if (IS_HARDWARE_TYPE_8723B(pAdapter))
+		return (IS_MASKED(8723B, _MPCIE, Offset)) ? TRUE : FALSE;
+#endif
+#if defined(CONFIG_RTL8814A)
+	if (IS_HARDWARE_TYPE_8814A(pAdapter))
+		return (IS_MASKED(8814A, _MPCIE, Offset)) ? TRUE : FALSE;
+#endif
+#if defined(CONFIG_RTL8822B)
+	if (IS_HARDWARE_TYPE_8822B(pAdapter))
+		return (IS_MASKED(8822B, _MPCIE, Offset)) ? TRUE : FALSE;
+#endif
+#if defined(CONFIG_RTL8821C)
+	if (IS_HARDWARE_TYPE_8821CE(pAdapter))
+		return (IS_MASKED(8821C, _MPCIE, Offset)) ? TRUE : FALSE;
+#endif
+
+#if defined(CONFIG_RTL8192F)
+	if (IS_HARDWARE_TYPE_8192FE(pAdapter))
+		return (IS_MASKED(8192F, _MPCIE, Offset)) ? TRUE : FALSE;
+#endif
+#endif /*CONFIG_PCI_HCI*/
+
+#ifdef CONFIG_SDIO_HCI
+#ifdef CONFIG_RTL8188E_SDIO
+	if (IS_HARDWARE_TYPE_8188E(pAdapter))
+		return (IS_MASKED(8188E, _MSDIO, Offset)) ? TRUE : FALSE;
+#endif
+#ifdef CONFIG_RTL8723B
+	if (IS_HARDWARE_TYPE_8723BS(pAdapter))
+		return (IS_MASKED(8723B, _MSDIO, Offset)) ? TRUE : FALSE;
+#endif
+#ifdef CONFIG_RTL8188F
+	if (IS_HARDWARE_TYPE_8188F(pAdapter))
+		return (IS_MASKED(8188F, _MSDIO, Offset)) ? TRUE : FALSE;
+#endif
+#ifdef CONFIG_RTL8188GTV
+	if (IS_HARDWARE_TYPE_8188GTV(pAdapter))
+		return (IS_MASKED(8188GTV, _MSDIO, Offset)) ? TRUE : FALSE;
+#endif
+#ifdef CONFIG_RTL8192E
+	if (IS_HARDWARE_TYPE_8192ES(pAdapter))
+		return (IS_MASKED(8192E, _MSDIO, Offset)) ? TRUE : FALSE;
+#endif
+#if defined(CONFIG_RTL8821A)
+	if (IS_HARDWARE_TYPE_8821S(pAdapter))
+		return (IS_MASKED(8821A, _MSDIO, Offset)) ? TRUE : FALSE;
+#endif
+#if defined(CONFIG_RTL8821C)
+	if (IS_HARDWARE_TYPE_8821CS(pAdapter))
+		return (IS_MASKED(8821C, _MSDIO, Offset)) ? TRUE : FALSE;
+#endif
+#if defined(CONFIG_RTL8822B)
+	if (IS_HARDWARE_TYPE_8822B(pAdapter))
+		return (IS_MASKED(8822B, _MSDIO, Offset)) ? TRUE : FALSE;
+#endif
+#if defined(CONFIG_RTL8192F)
+	if (IS_HARDWARE_TYPE_8192FS(pAdapter))
+		return (IS_MASKED(8192F, _MSDIO, Offset)) ? TRUE : FALSE;
+#endif
+#endif /*CONFIG_SDIO_HCI*/
+
+	return FALSE;
+}
+
+void rtw_efuse_mask_array(PADAPTER pAdapter, u8 *pArray)
+{
+	PHAL_DATA_TYPE pHalData = GET_HAL_DATA(pAdapter);
+
+#ifdef CONFIG_USB_HCI
+#if defined(CONFIG_RTL8188E)
+	if (IS_HARDWARE_TYPE_8188E(pAdapter))
+		GET_MASK_ARRAY(8188E, _MUSB, pArray);
+#endif
+#if defined(CONFIG_RTL8812A)
+	if (IS_HARDWARE_TYPE_8812(pAdapter))
+		GET_MASK_ARRAY(8812A, _MUSB, pArray);
+#endif
+#if defined(CONFIG_RTL8821A)
+	if (IS_HARDWARE_TYPE_8821(pAdapter))
+		GET_MASK_ARRAY(8821A, _MUSB, pArray);
+#endif
+#if defined(CONFIG_RTL8192E)
+	if (IS_HARDWARE_TYPE_8192E(pAdapter))
+		GET_MASK_ARRAY(8192E, _MUSB, pArray);
+#endif
+#if defined(CONFIG_RTL8723B)
+	if (IS_HARDWARE_TYPE_8723B(pAdapter))
+		GET_MASK_ARRAY(8723B, _MUSB, pArray);
+#endif
+#if defined(CONFIG_RTL8703B)
+	if (IS_HARDWARE_TYPE_8703B(pAdapter))
+		GET_MASK_ARRAY(8703B, _MUSB, pArray);
+#endif
+#if defined(CONFIG_RTL8188F)
+	if (IS_HARDWARE_TYPE_8188F(pAdapter))
+		GET_MASK_ARRAY(8188F, _MUSB, pArray);
+#endif
+#if defined(CONFIG_RTL8188GTV)
+	if (IS_HARDWARE_TYPE_8188GTV(pAdapter))
+		GET_MASK_ARRAY(8188GTV, _MUSB, pArray);
+#endif
+#if defined(CONFIG_RTL8814A)
+	if (IS_HARDWARE_TYPE_8814A(pAdapter))
+		GET_MASK_ARRAY(8814A, _MUSB, pArray);
+#endif
+#if defined(CONFIG_RTL8822B)
+	if (IS_HARDWARE_TYPE_8822B(pAdapter))
+		GET_MASK_ARRAY(8822B, _MUSB, pArray);
+#endif
+#if defined(CONFIG_RTL8821C)
+	if (IS_HARDWARE_TYPE_8821CU(pAdapter))
+		GET_MASK_ARRAY(8821C, _MUSB, pArray);
+#endif
+#if defined(CONFIG_RTL8192F)
+	if (IS_HARDWARE_TYPE_8192FU(pAdapter))
+		GET_MASK_ARRAY(8192F, _MUSB, pArray);
+#endif
+#endif /*CONFIG_USB_HCI*/
+
+#ifdef CONFIG_PCI_HCI
+#if defined(CONFIG_RTL8188E)
+	if (IS_HARDWARE_TYPE_8188E(pAdapter))
+		GET_MASK_ARRAY(8188E, _MPCIE, pArray);
+#endif
+#if defined(CONFIG_RTL8192E)
+	if (IS_HARDWARE_TYPE_8192E(pAdapter))
+		GET_MASK_ARRAY(8192E, _MPCIE, pArray);
+#endif
+#if defined(CONFIG_RTL8812A)
+	if (IS_HARDWARE_TYPE_8812(pAdapter))
+		GET_MASK_ARRAY(8812A, _MPCIE, pArray);
+#endif
+#if defined(CONFIG_RTL8821A)
+	if (IS_HARDWARE_TYPE_8821(pAdapter))
+		GET_MASK_ARRAY(8821A, _MPCIE, pArray);
+#endif
+#if defined(CONFIG_RTL8723B)
+	if (IS_HARDWARE_TYPE_8723B(pAdapter))
+		GET_MASK_ARRAY(8723B, _MPCIE, pArray);
+#endif
+#if defined(CONFIG_RTL8814A)
+	if (IS_HARDWARE_TYPE_8814A(pAdapter))
+		GET_MASK_ARRAY(8814A, _MPCIE, pArray);
+#endif
+#if defined(CONFIG_RTL8822B)
+	if (IS_HARDWARE_TYPE_8822B(pAdapter))
+		GET_MASK_ARRAY(8822B, _MPCIE, pArray);
+#endif
+#if defined(CONFIG_RTL8821C)
+	if (IS_HARDWARE_TYPE_8821CE(pAdapter))
+		GET_MASK_ARRAY(8821C, _MPCIE, pArray);
+#endif
+#if defined(CONFIG_RTL8192F)
+	if (IS_HARDWARE_TYPE_8192FE(pAdapter))
+		GET_MASK_ARRAY(8192F, _MPCIE, pArray);
+#endif
+#endif /*CONFIG_PCI_HCI*/
+
+#ifdef CONFIG_SDIO_HCI
+#if defined(CONFIG_RTL8188E)
+	if (IS_HARDWARE_TYPE_8188E(pAdapter))
+		GET_MASK_ARRAY(8188E, _MSDIO, pArray);
+#endif
+#if defined(CONFIG_RTL8723B)
+	if (IS_HARDWARE_TYPE_8723BS(pAdapter))
+		GET_MASK_ARRAY(8723B, _MSDIO, pArray);
+#endif
+#if defined(CONFIG_RTL8188F)
+	if (IS_HARDWARE_TYPE_8188F(pAdapter))
+		GET_MASK_ARRAY(8188F, _MSDIO, pArray);
+#endif
+#if defined(CONFIG_RTL8188GTV)
+	if (IS_HARDWARE_TYPE_8188GTV(pAdapter))
+		GET_MASK_ARRAY(8188GTV, _MSDIO, pArray);
+#endif
+#if defined(CONFIG_RTL8192E)
+	if (IS_HARDWARE_TYPE_8192ES(pAdapter))
+		GET_MASK_ARRAY(8192E, _MSDIO, pArray);
+#endif
+#if defined(CONFIG_RTL8821A)
+	if (IS_HARDWARE_TYPE_8821S(pAdapter))
+		GET_MASK_ARRAY(8821A, _MSDIO, pArray);
+#endif
+#if defined(CONFIG_RTL8821C)
+	if (IS_HARDWARE_TYPE_8821CS(pAdapter))
+		GET_MASK_ARRAY(8821C , _MSDIO, pArray);
+#endif
+#if defined(CONFIG_RTL8822B)
+	if (IS_HARDWARE_TYPE_8822B(pAdapter))
+		GET_MASK_ARRAY(8822B , _MSDIO, pArray);
+#endif
+#if defined(CONFIG_RTL8192F)
+	if (IS_HARDWARE_TYPE_8192FS(pAdapter))
+		GET_MASK_ARRAY(8192F, _MSDIO, pArray);
+#endif
+#endif /*CONFIG_SDIO_HCI*/
+}
+
+u16 rtw_get_efuse_mask_arraylen(PADAPTER pAdapter)
+{
+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(pAdapter);
+
+#ifdef CONFIG_USB_HCI
+#if defined(CONFIG_RTL8188E)
+	if (IS_HARDWARE_TYPE_8188E(pAdapter))
+		return GET_MASK_ARRAY_LEN(8188E, _MUSB);
+#endif
+#if defined(CONFIG_RTL8812A)
+	if (IS_HARDWARE_TYPE_8812(pAdapter))
+		return GET_MASK_ARRAY_LEN(8812A, _MUSB);
+#endif
+#if defined(CONFIG_RTL8821A)
+	if (IS_HARDWARE_TYPE_8821(pAdapter))
+		return GET_MASK_ARRAY_LEN(8821A, _MUSB);
+#endif
+#if defined(CONFIG_RTL8192E)
+	if (IS_HARDWARE_TYPE_8192E(pAdapter))
+		return GET_MASK_ARRAY_LEN(8192E, _MUSB);
+#endif
+#if defined(CONFIG_RTL8723B)
+	if (IS_HARDWARE_TYPE_8723B(pAdapter))
+		return GET_MASK_ARRAY_LEN(8723B, _MUSB);
+#endif
+#if defined(CONFIG_RTL8703B)
+	if (IS_HARDWARE_TYPE_8703B(pAdapter))
+		return GET_MASK_ARRAY_LEN(8703B, _MUSB);
+#endif
+#if defined(CONFIG_RTL8188F)
+	if (IS_HARDWARE_TYPE_8188F(pAdapter))
+		return GET_MASK_ARRAY_LEN(8188F, _MUSB);
+#endif
+#if defined(CONFIG_RTL8188GTV)
+	if (IS_HARDWARE_TYPE_8188GTV(pAdapter))
+		return GET_MASK_ARRAY_LEN(8188GTV, _MUSB);
+#endif
+#if defined(CONFIG_RTL8814A)
+	if (IS_HARDWARE_TYPE_8814A(pAdapter))
+		return GET_MASK_ARRAY_LEN(8814A, _MUSB);
+#endif
+#if defined(CONFIG_RTL8822B)
+	if (IS_HARDWARE_TYPE_8822B(pAdapter))
+		return GET_MASK_ARRAY_LEN(8822B, _MUSB);
+#endif
+#if defined(CONFIG_RTL8821C)
+	if (IS_HARDWARE_TYPE_8821CU(pAdapter))
+		return GET_MASK_ARRAY_LEN(8821C, _MUSB);
+#endif
+#if defined(CONFIG_RTL8192F)
+	if (IS_HARDWARE_TYPE_8192FU(pAdapter))
+		return GET_MASK_ARRAY_LEN(8192F, _MUSB);
+#endif
+#endif /*CONFIG_USB_HCI*/
+
+#ifdef CONFIG_PCI_HCI
+#if defined(CONFIG_RTL8188E)
+	if (IS_HARDWARE_TYPE_8188E(pAdapter))
+		return GET_MASK_ARRAY_LEN(8188E, _MPCIE);
+#endif
+#if defined(CONFIG_RTL8192E)
+	if (IS_HARDWARE_TYPE_8192E(pAdapter))
+		return GET_MASK_ARRAY_LEN(8192E, _MPCIE);
+#endif
+#if defined(CONFIG_RTL8812A)
+	if (IS_HARDWARE_TYPE_8812(pAdapter))
+		return GET_MASK_ARRAY_LEN(8812A, _MPCIE);
+#endif
+#if defined(CONFIG_RTL8821A)
+	if (IS_HARDWARE_TYPE_8821(pAdapter))
+		return GET_MASK_ARRAY_LEN(8821A, _MPCIE);
+#endif
+#if defined(CONFIG_RTL8723B)
+	if (IS_HARDWARE_TYPE_8723B(pAdapter))
+		return GET_MASK_ARRAY_LEN(8723B, _MPCIE);
+#endif
+#if defined(CONFIG_RTL8814A)
+	if (IS_HARDWARE_TYPE_8814A(pAdapter))
+		return GET_MASK_ARRAY_LEN(8814A, _MPCIE);
+#endif
+#if defined(CONFIG_RTL8822B)
+	if (IS_HARDWARE_TYPE_8822B(pAdapter))
+		return GET_MASK_ARRAY_LEN(8822B, _MPCIE);
+#endif
+#if defined(CONFIG_RTL8821C)
+	if (IS_HARDWARE_TYPE_8821CE(pAdapter))
+		return GET_MASK_ARRAY_LEN(8821C, _MPCIE);
+#endif
+#if defined(CONFIG_RTL8192F)
+	if (IS_HARDWARE_TYPE_8192FE(pAdapter))
+		return GET_MASK_ARRAY_LEN(8192F, _MPCIE);
+#endif
+#endif /*CONFIG_PCI_HCI*/
+
+#ifdef CONFIG_SDIO_HCI
+#if defined(CONFIG_RTL8188E)
+	if (IS_HARDWARE_TYPE_8188E(pAdapter))
+		return GET_MASK_ARRAY_LEN(8188E, _MSDIO);
+#endif
+#if defined(CONFIG_RTL8723B)
+	if (IS_HARDWARE_TYPE_8723BS(pAdapter))
+		return GET_MASK_ARRAY_LEN(8723B, _MSDIO);
+#endif
+#if defined(CONFIG_RTL8188F)
+	if (IS_HARDWARE_TYPE_8188F(pAdapter))
+		return GET_MASK_ARRAY_LEN(8188F, _MSDIO);
+#endif
+#if defined(CONFIG_RTL8188GTV)
+	if (IS_HARDWARE_TYPE_8188GTV(pAdapter))
+		return GET_MASK_ARRAY_LEN(8188GTV, _MSDIO);
+#endif
+#if defined(CONFIG_RTL8192E)
+	if (IS_HARDWARE_TYPE_8192ES(pAdapter))
+		return GET_MASK_ARRAY_LEN(8192E, _MSDIO);
+#endif
+#if defined(CONFIG_RTL8821A)
+	if (IS_HARDWARE_TYPE_8821S(pAdapter))
+		return GET_MASK_ARRAY_LEN(8821A, _MSDIO);
+#endif
+#if defined(CONFIG_RTL8821C)
+	if (IS_HARDWARE_TYPE_8821CS(pAdapter))
+		return GET_MASK_ARRAY_LEN(8821C, _MSDIO);
+#endif
+#if defined(CONFIG_RTL8822B)
+	if (IS_HARDWARE_TYPE_8822B(pAdapter))
+		return GET_MASK_ARRAY_LEN(8822B, _MSDIO);
+#endif
+#if defined(CONFIG_RTL8192F)
+	if (IS_HARDWARE_TYPE_8192FS(pAdapter))
+		return GET_MASK_ARRAY_LEN(8192F, _MSDIO);
+#endif
+#endif/*CONFIG_SDIO_HCI*/
+	return 0;
+}
+
+static void rtw_mask_map_read(PADAPTER padapter, u16 addr, u16 cnts, u8 *data)
+{
+	u16 i = 0;
+
+	if (padapter->registrypriv.boffefusemask == 0) {
+
+			for (i = 0; i < cnts; i++) {
+				if (padapter->registrypriv.bFileMaskEfuse == _TRUE) {
+					if (rtw_file_efuse_IsMasked(padapter, addr + i)) /*use file efuse mask.*/
+						data[i] = 0xff;
+				} else {
+					/*RTW_INFO(" %s , data[%d] = %x\n", __func__, i, data[i]);*/
+					if (efuse_IsMasked(padapter, addr + i)) {
+						data[i] = 0xff;
+						/*RTW_INFO(" %s ,mask data[%d] = %x\n", __func__, i, data[i]);*/
+					}
+				}
+			}
+
+	}
+}
+
+u8 rtw_efuse_mask_map_read(PADAPTER padapter, u16 addr, u16 cnts, u8 *data)
+{
+	u8	ret = _SUCCESS;
+	u16	mapLen = 0;
+
+	EFUSE_GetEfuseDefinition(padapter, EFUSE_WIFI, TYPE_EFUSE_MAP_LEN, (PVOID)&mapLen, _FALSE);
+
+	ret = rtw_efuse_map_read(padapter, addr, cnts , data);
+
+	rtw_mask_map_read(padapter, addr, cnts , data);
+
+	return ret;
+
+}
+
+/* ***********************************************************
+ *				Efuse related code
+ * *********************************************************** */
+static u8 hal_EfuseSwitchToBank(
+	PADAPTER	padapter,
+	u8			bank,
+	u8			bPseudoTest)
+{
+	u8 bRet = _FALSE;
+	u32 value32 = 0;
+#ifdef HAL_EFUSE_MEMORY
+	PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter);
+	PEFUSE_HAL pEfuseHal = &pHalData->EfuseHal;
+#endif
+
+
+	RTW_INFO("%s: Efuse switch bank to %d\n", __FUNCTION__, bank);
+	if (bPseudoTest) {
+#ifdef HAL_EFUSE_MEMORY
+		pEfuseHal->fakeEfuseBank = bank;
+#else
+		fakeEfuseBank = bank;
+#endif
+		bRet = _TRUE;
+	} else {
+		value32 = rtw_read32(padapter, 0x34);
+		bRet = _TRUE;
+		switch (bank) {
+		case 0:
+			value32 = (value32 & ~EFUSE_SEL_MASK) | EFUSE_SEL(EFUSE_WIFI_SEL_0);
+			break;
+		case 1:
+			value32 = (value32 & ~EFUSE_SEL_MASK) | EFUSE_SEL(EFUSE_BT_SEL_0);
+			break;
+		case 2:
+			value32 = (value32 & ~EFUSE_SEL_MASK) | EFUSE_SEL(EFUSE_BT_SEL_1);
+			break;
+		case 3:
+			value32 = (value32 & ~EFUSE_SEL_MASK) | EFUSE_SEL(EFUSE_BT_SEL_2);
+			break;
+		default:
+			value32 = (value32 & ~EFUSE_SEL_MASK) | EFUSE_SEL(EFUSE_WIFI_SEL_0);
+			bRet = _FALSE;
+			break;
+		}
+		rtw_write32(padapter, 0x34, value32);
+	}
+
+	return bRet;
+}
+
+void rtw_efuse_analyze(PADAPTER	padapter, u8 Type, u8 Fake)
+{
+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(padapter);
+	PEFUSE_HAL		pEfuseHal = &(pHalData->EfuseHal);
+	u16	eFuse_Addr = 0;
+	u8 offset, wden;
+	u16	 i, j;
+	u8	u1temp = 0;
+	u8	efuseHeader = 0, efuseExtHdr = 0, efuseData[EFUSE_MAX_WORD_UNIT*2] = {0}, dataCnt = 0;
+	u16	efuseHeader2Byte = 0;
+	u8	*eFuseWord = NULL;// [EFUSE_MAX_SECTION_NUM][EFUSE_MAX_WORD_UNIT];
+	u8	offset_2_0 = 0;
+	u8	pgSectionCnt = 0;
+	u8	wd_cnt = 0;
+	u8	max_section = 64;
+	u16	mapLen = 0, maprawlen = 0;
+	boolean	bExtHeader = _FALSE;
+	u8	efuseType = EFUSE_WIFI;
+	boolean	bPseudoTest = _FALSE;
+	u8	bank = 0, startBank = 0, endBank = 1-1;
+	boolean	bCheckNextBank = FALSE;
+	u8	protectBytesBank = 0;
+	u16	efuse_max = 0;
+	u8	ParseEfuseExtHdr, ParseEfuseHeader, ParseOffset, ParseWDEN, ParseOffset2_0;
+
+	eFuseWord = rtw_zmalloc(EFUSE_MAX_SECTION_NUM * (EFUSE_MAX_WORD_UNIT * 2));
+
+	RTW_INFO("\n");
+	if (Type == 0) {
+		if (Fake == 0) {
+			RTW_INFO("\n\tEFUSE_Analyze Wifi Content\n");
+			efuseType = EFUSE_WIFI;
+			bPseudoTest = FALSE;
+			startBank = 0;
+			endBank = 0;
+		} else {
+			RTW_INFO("\n\tEFUSE_Analyze Wifi Pseudo Content\n");
+			efuseType = EFUSE_WIFI;
+			bPseudoTest = TRUE;
+			startBank = 0;
+			endBank = 0;
+		}
+	} else {
+		if (Fake == 0) {
+			RTW_INFO("\n\tEFUSE_Analyze BT Content\n");
+			efuseType = EFUSE_BT;
+			bPseudoTest = FALSE;
+			startBank = 1;
+			endBank = EFUSE_MAX_BANK - 1;
+		} else {
+			RTW_INFO("\n\tEFUSE_Analyze BT Pseudo Content\n");
+			efuseType = EFUSE_BT;
+			bPseudoTest = TRUE;
+			startBank = 1;
+			endBank = EFUSE_MAX_BANK - 1;
+			if (IS_HARDWARE_TYPE_8821(padapter))
+				endBank = 3 - 1;/*EFUSE_MAX_BANK_8821A - 1;*/
+		}
+	}
+
+	RTW_INFO("\n\r 1Byte header, [7:4]=offset, [3:0]=word enable\n");
+	RTW_INFO("\n\r 2Byte header, header[7:5]=offset[2:0], header[4:0]=0x0F\n");
+	RTW_INFO("\n\r 2Byte header, extHeader[7:4]=offset[6:3], extHeader[3:0]=word enable\n");
+
+	EFUSE_GetEfuseDefinition(padapter, efuseType, TYPE_EFUSE_MAP_LEN, (PVOID)&mapLen, bPseudoTest);
+	EFUSE_GetEfuseDefinition(padapter, efuseType, TYPE_EFUSE_MAX_SECTION, (PVOID)&max_section, bPseudoTest);
+	EFUSE_GetEfuseDefinition(padapter, efuseType, TYPE_EFUSE_PROTECT_BYTES_BANK, (PVOID)&protectBytesBank, bPseudoTest);
+	EFUSE_GetEfuseDefinition(padapter, efuseType, TYPE_EFUSE_CONTENT_LEN_BANK, (PVOID)&efuse_max, bPseudoTest);
+	EFUSE_GetEfuseDefinition(padapter, EFUSE_WIFI, TYPE_EFUSE_REAL_CONTENT_LEN, (PVOID)&maprawlen, _FALSE);
+
+	_rtw_memset(eFuseWord, 0xff, EFUSE_MAX_SECTION_NUM * (EFUSE_MAX_WORD_UNIT * 2));
+	_rtw_memset(pEfuseHal->fakeEfuseInitMap, 0xff, EFUSE_MAX_MAP_LEN);
+
+	if (IS_HARDWARE_TYPE_8821(padapter))
+		endBank = 3 - 1;/*EFUSE_MAX_BANK_8821A - 1;*/
+
+	for (bank = startBank; bank <= endBank; bank++) {
+		if (!hal_EfuseSwitchToBank(padapter, bank, bPseudoTest)) {
+			RTW_INFO("EFUSE_SwitchToBank() Fail!!\n");
+			return;
+		}
+
+		eFuse_Addr = bank * EFUSE_MAX_BANK_SIZE;
+
+		efuse_OneByteRead(padapter, eFuse_Addr++, &efuseHeader, bPseudoTest);
+
+		if (efuseHeader == 0xFF && bank == startBank && Fake != TRUE) {
+			RTW_INFO("Non-PGed Efuse\n");
+			return;
+		}
+		RTW_INFO("EFUSE_REAL_CONTENT_LEN = %d\n", maprawlen);
+
+		while ((efuseHeader != 0xFF) && ((efuseType == EFUSE_WIFI && (eFuse_Addr < maprawlen)) || (efuseType == EFUSE_BT && (eFuse_Addr < (endBank + 1) * EFUSE_MAX_BANK_SIZE)))) {
+
+			RTW_INFO("Analyzing: Offset: 0x%X\n", eFuse_Addr);
+
+			/* Check PG header for section num.*/
+			if (EXT_HEADER(efuseHeader)) {
+				bExtHeader = TRUE;
+				offset_2_0 = GET_HDR_OFFSET_2_0(efuseHeader);
+				efuse_OneByteRead(padapter, eFuse_Addr++, &efuseExtHdr, bPseudoTest);
+
+				if (efuseExtHdr != 0xff) {
+					if (ALL_WORDS_DISABLED(efuseExtHdr)) {
+						/* Read next pg header*/
+						efuse_OneByteRead(padapter, eFuse_Addr++, &efuseHeader, bPseudoTest);
+						continue;
+					} else {
+						offset = ((efuseExtHdr & 0xF0) >> 1) | offset_2_0;
+						wden = (efuseExtHdr & 0x0F);
+						efuseHeader2Byte = (efuseExtHdr<<8)|efuseHeader;
+						RTW_INFO("Find efuseHeader2Byte = 0x%04X, offset=%d, wden=0x%x\n",
+										efuseHeader2Byte, offset, wden);
+					}
+				} else {
+					RTW_INFO("Error, efuse[%d]=0xff, efuseExtHdr=0xff\n", eFuse_Addr-1);
+					break;
+				}
+			} else {
+				offset = ((efuseHeader >> 4) & 0x0f);
+				wden = (efuseHeader & 0x0f);
+			}
+
+			_rtw_memset(efuseData, '\0', EFUSE_MAX_WORD_UNIT * 2);
+			dataCnt = 0;
+
+			if (offset < max_section) {
+				for (i = 0; i < EFUSE_MAX_WORD_UNIT; i++) {
+					/* Check word enable condition in the section	*/
+					if (!(wden & (0x01<<i))) {
+						if (!((efuseType == EFUSE_WIFI && (eFuse_Addr + 2 < maprawlen)) ||
+								(efuseType == EFUSE_BT && (eFuse_Addr + 2 < (endBank + 1) * EFUSE_MAX_BANK_SIZE)))) {
+							RTW_INFO("eFuse_Addr exceeds, break\n");
+							break;
+						}
+						efuse_OneByteRead(padapter, eFuse_Addr++, &efuseData[dataCnt++], bPseudoTest);
+						eFuseWord[(offset * 8) + (i * 2)] = (efuseData[dataCnt - 1]);
+						efuse_OneByteRead(padapter, eFuse_Addr++, &efuseData[dataCnt++], bPseudoTest);
+						eFuseWord[(offset * 8) + (i * 2 + 1)] = (efuseData[dataCnt - 1]);
+					}
+				}
+			}
+
+			if (bExtHeader) {
+				RTW_INFO("Efuse PG Section (%d) = ", pgSectionCnt);
+				RTW_INFO("[ %04X ], [", efuseHeader2Byte);
+
+			} else {
+				RTW_INFO("Efuse PG Section (%d) = ", pgSectionCnt);
+				RTW_INFO("[ %02X ], [", efuseHeader);
+			}
+
+			for (j = 0; j < dataCnt; j++)
+				RTW_INFO(" %02X ", efuseData[j]);
+
+			RTW_INFO("]\n");
+
+
+			if (bExtHeader) {
+				ParseEfuseExtHdr = (efuseHeader2Byte & 0xff00) >> 8;
+				ParseEfuseHeader = (efuseHeader2Byte & 0xff);
+				ParseOffset2_0 = GET_HDR_OFFSET_2_0(ParseEfuseHeader);
+				ParseOffset = ((ParseEfuseExtHdr & 0xF0) >> 1) | ParseOffset2_0;
+				ParseWDEN = (ParseEfuseExtHdr & 0x0F);
+				RTW_INFO("Header=0x%x, ExtHeader=0x%x, ", ParseEfuseHeader, ParseEfuseExtHdr);
+			} else {
+				ParseEfuseHeader = efuseHeader;
+				ParseOffset = ((ParseEfuseHeader >> 4) & 0x0f);
+				ParseWDEN = (ParseEfuseHeader & 0x0f);
+				RTW_INFO("Header=0x%x, ", ParseEfuseHeader);
+			}
+			RTW_INFO("offset=0x%x(%d), word enable=0x%x\n", ParseOffset, ParseOffset, ParseWDEN);
+
+			wd_cnt = 0;
+			for (i = 0; i < EFUSE_MAX_WORD_UNIT; i++) {
+				if (!(wden & (0x01 << i))) {
+					RTW_INFO("Map[ %02X ] = %02X %02X\n", ((offset * EFUSE_MAX_WORD_UNIT * 2) + (i * 2)), efuseData[wd_cnt * 2 + 0], efuseData[wd_cnt * 2 + 1]);
+					wd_cnt++;
+				}
+			}
+
+			pgSectionCnt++;
+			bExtHeader = FALSE;
+			efuse_OneByteRead(padapter, eFuse_Addr++, &efuseHeader, bPseudoTest);
+			if (efuseHeader == 0xFF) {
+				if ((eFuse_Addr + protectBytesBank) >= efuse_max)
+					bCheckNextBank = TRUE;
+				else
+					bCheckNextBank = FALSE;
+			}
+		}
+		if (!bCheckNextBank) {
+			RTW_INFO("Not need to check next bank, eFuse_Addr=%d, protectBytesBank=%d, efuse_max=%d\n",
+				eFuse_Addr, protectBytesBank, efuse_max);
+			break;
+		}
+	}
+	/* switch bank back to 0 for BT/wifi later use*/
+	hal_EfuseSwitchToBank(padapter, 0, bPseudoTest);
+
+	/* 3. Collect 16 sections and 4 word unit into Efuse map.*/
+	for (i = 0; i < max_section; i++) {
+		for (j = 0; j < EFUSE_MAX_WORD_UNIT; j++) {
+			pEfuseHal->fakeEfuseInitMap[(i*8)+(j*2)] = (eFuseWord[(i*8)+(j*2)]);
+			pEfuseHal->fakeEfuseInitMap[(i*8)+((j*2)+1)] =  (eFuseWord[(i*8)+((j*2)+1)]);
+		}
+	}
+
+	RTW_INFO("\n\tEFUSE Analyze Map\n");
+	i = 0;
+	j = 0;
+
+	for (i = 0; i < mapLen; i++) {
+		if (i % 16 == 0)
+			RTW_PRINT_SEL(RTW_DBGDUMP, "0x%03x: ", i);
+			_RTW_PRINT_SEL(RTW_DBGDUMP, "%02X%s"
+				, pEfuseHal->fakeEfuseInitMap[i]
+				, ((i + 1) % 16 == 0) ? "\n" : (((i + 1) % 8 == 0) ? "	  " : " ")
+			);
+		}
+	_RTW_PRINT_SEL(RTW_DBGDUMP, "\n");
+	if (eFuseWord)
+		rtw_mfree((u8 *)eFuseWord, EFUSE_MAX_SECTION_NUM * (EFUSE_MAX_WORD_UNIT * 2));
+}
+
+VOID efuse_PreUpdateAction(
+	PADAPTER	pAdapter,
+	pu4Byte	BackupRegs)
+{
+	if (IS_HARDWARE_TYPE_8812AU(pAdapter) || IS_HARDWARE_TYPE_8822BU(pAdapter)) {
+		/* <20131115, Kordan> Turn off Rx to prevent from being busy when writing the EFUSE. (Asked by Chunchu.)*/
+		BackupRegs[0] = phy_query_mac_reg(pAdapter, REG_RCR, bMaskDWord);
+		BackupRegs[1] = phy_query_mac_reg(pAdapter, REG_RXFLTMAP0, bMaskDWord);
+		BackupRegs[2] = phy_query_mac_reg(pAdapter, REG_RXFLTMAP0+4, bMaskDWord);
+#ifdef CONFIG_RTL8812A
+		BackupRegs[3] = phy_query_mac_reg(pAdapter, REG_AFE_MISC, bMaskDWord);
+#endif
+		PlatformEFIOWrite4Byte(pAdapter, REG_RCR, 0x1);
+		PlatformEFIOWrite1Byte(pAdapter, REG_RXFLTMAP0, 0);
+		PlatformEFIOWrite1Byte(pAdapter, REG_RXFLTMAP0+1, 0);
+		PlatformEFIOWrite1Byte(pAdapter, REG_RXFLTMAP0+2, 0);
+		PlatformEFIOWrite1Byte(pAdapter, REG_RXFLTMAP0+3, 0);
+		PlatformEFIOWrite1Byte(pAdapter, REG_RXFLTMAP0+4, 0);
+		PlatformEFIOWrite1Byte(pAdapter, REG_RXFLTMAP0+5, 0);
+#ifdef CONFIG_RTL8812A
+		/* <20140410, Kordan> 0x11 = 0x4E, lower down LX_SPS0 voltage. (Asked by Chunchu)*/
+		phy_set_mac_reg(pAdapter, REG_AFE_MISC, bMaskByte1, 0x4E);
+#endif
+		RTW_INFO(" %s , done\n", __func__);
+
+		}
+}
+
+
+VOID efuse_PostUpdateAction(
+	PADAPTER	pAdapter,
+	pu4Byte	BackupRegs)
+{
+	if (IS_HARDWARE_TYPE_8812AU(pAdapter) || IS_HARDWARE_TYPE_8822BU(pAdapter)) {
+		/* <20131115, Kordan> Turn on Rx and restore the registers. (Asked by Chunchu.)*/
+		phy_set_mac_reg(pAdapter, REG_RCR, bMaskDWord, BackupRegs[0]);
+		phy_set_mac_reg(pAdapter, REG_RXFLTMAP0, bMaskDWord, BackupRegs[1]);
+		phy_set_mac_reg(pAdapter, REG_RXFLTMAP0+4, bMaskDWord, BackupRegs[2]);
+#ifdef CONFIG_RTL8812A
+		phy_set_mac_reg(pAdapter, REG_AFE_MISC, bMaskDWord, BackupRegs[3]);
+#endif
+	RTW_INFO(" %s , done\n", __func__);
+	}
+}
+
+
+#ifdef RTW_HALMAC
+#include "../../hal/hal_halmac.h"
+
+void Efuse_PowerSwitch(PADAPTER adapter, u8 write, u8 pwrstate)
+{
+}
+
+void BTEfuse_PowerSwitch(PADAPTER adapter, u8 write, u8 pwrstate)
+{
+}
+
+u8 efuse_GetCurrentSize(PADAPTER adapter, u16 *size)
+{
+	*size = 0;
+
+	return _FAIL;
+}
+
+u16 efuse_GetMaxSize(PADAPTER adapter)
+{
+	struct dvobj_priv *d;
+	u32 size = 0;
+	int err;
+
+	d = adapter_to_dvobj(adapter);
+	err = rtw_halmac_get_physical_efuse_size(d, &size);
+	if (err)
+		return 0;
+
+	return size;
+}
+
+u16 efuse_GetavailableSize(PADAPTER adapter)
+{
+	struct dvobj_priv *d;
+	u32 size = 0;
+	int err;
+
+	d = adapter_to_dvobj(adapter);
+	err = rtw_halmac_get_available_efuse_size(d, &size);
+	if (err)
+		return 0;
+
+	return size;
+}
+
+
+u8 efuse_bt_GetCurrentSize(PADAPTER adapter, u16 *usesize)
+{
+	u8 *efuse_map;
+
+	*usesize = 0;
+	efuse_map = rtw_malloc(EFUSE_BT_MAP_LEN);
+	if (efuse_map == NULL) {
+		RTW_DBG("%s: malloc FAIL\n", __FUNCTION__);
+		return _FAIL;
+	}
+
+	/* for get bt phy efuse last use byte */
+	hal_ReadEFuse_BT_logic_map(adapter, 0x00, EFUSE_BT_MAP_LEN, efuse_map);
+	*usesize = fakeBTEfuseUsedBytes;
+
+	if (efuse_map)
+		rtw_mfree(efuse_map, EFUSE_BT_MAP_LEN);
+
+	return _SUCCESS;
+}
+
+u16 efuse_bt_GetMaxSize(PADAPTER adapter)
+{
+	return EFUSE_BT_REAL_CONTENT_LEN;
+}
+
+void EFUSE_GetEfuseDefinition(PADAPTER adapter, u8 efusetype, u8 type, void *out, BOOLEAN test)
+{
+	struct dvobj_priv *d;
+	u32 v32 = 0;
+
+
+	d = adapter_to_dvobj(adapter);
+
+	if (adapter->hal_func.EFUSEGetEfuseDefinition) {
+		adapter->hal_func.EFUSEGetEfuseDefinition(adapter, efusetype, type, out, test);
+		return;
+	}
+
+	if (EFUSE_WIFI == efusetype) {
+		switch (type) {
+		case TYPE_EFUSE_MAP_LEN:
+			rtw_halmac_get_logical_efuse_size(d, &v32);
+			*(u16 *)out = (u16)v32;
+			return;
+
+		case TYPE_EFUSE_REAL_CONTENT_LEN:	
+			rtw_halmac_get_physical_efuse_size(d, &v32);
+			*(u16 *)out = (u16)v32;
+			return;
+		}
+	} else if (EFUSE_BT == efusetype) {
+		switch (type) {
+		case TYPE_EFUSE_MAP_LEN:
+			*(u16 *)out = EFUSE_BT_MAP_LEN;
+			return;
+
+		case TYPE_EFUSE_REAL_CONTENT_LEN:
+			*(u16 *)out = EFUSE_BT_REAL_CONTENT_LEN;
+			return;
+		}
+	}
+}
+
+/*
+ * read/write raw efuse data
+ */
+u8 rtw_efuse_access(PADAPTER adapter, u8 write, u16 addr, u16 cnts, u8 *data)
+{
+	struct dvobj_priv *d;
+	u8 *efuse = NULL;
+	u32 size, i;
+	int err;
+
+
+	d = adapter_to_dvobj(adapter);
+	err = rtw_halmac_get_physical_efuse_size(d, &size);
+	if (err)
+		size = EFUSE_MAX_SIZE;
+
+	if ((addr + cnts) > size)
+		return _FAIL;
+
+	if (_TRUE == write) {
+		err = rtw_halmac_write_physical_efuse(d, addr, cnts, data);
+		if (err)
+			return _FAIL;
+	} else {
+		if (cnts > 16)
+			efuse = rtw_zmalloc(size);
+
+		if (efuse) {
+			err = rtw_halmac_read_physical_efuse_map(d, efuse, size);
+			if (err) {
+				rtw_mfree(efuse, size);
+				return _FAIL;
+			}
+
+			_rtw_memcpy(data, efuse + addr, cnts);
+			rtw_mfree(efuse, size);
+		} else {
+			err = rtw_halmac_read_physical_efuse(d, addr, cnts, data);
+			if (err)
+				return _FAIL;
+		}
+	}
+
+	return _SUCCESS;
+}
+
+static inline void dump_buf(u8 *buf, u32 len)
+{
+	u32 i;
+
+	RTW_INFO("-----------------Len %d----------------\n", len);
+	for (i = 0; i < len; i++)
+		printk("%2.2x-", *(buf + i));
+	printk("\n");
+}
+
+/*
+ * read/write raw efuse data
+ */
+u8 rtw_efuse_bt_access(PADAPTER adapter, u8 write, u16 addr, u16 cnts, u8 *data)
+{
+	struct dvobj_priv *d;
+	u8 *efuse = NULL;
+	u32 size, i;
+	int err = _FAIL;
+
+
+	d = adapter_to_dvobj(adapter);
+
+	size = EFUSE_BT_REAL_CONTENT_LEN;
+
+	if ((addr + cnts) > size)
+		return _FAIL;
+
+	if (_TRUE == write) {
+		err = rtw_halmac_write_bt_physical_efuse(d, addr, cnts, data);
+		if (err == -1) {
+			RTW_ERR("%s: rtw_halmac_write_bt_physical_efuse fail!\n", __FUNCTION__);
+			return _FAIL;
+		}
+		RTW_INFO("%s: rtw_halmac_write_bt_physical_efuse OK! data 0x%x\n", __FUNCTION__, *data);
+	} else {
+		efuse = rtw_zmalloc(size);
+
+		if (efuse) {
+			err = rtw_halmac_read_bt_physical_efuse_map(d, efuse, size);
+			
+			if (err == -1) {
+				RTW_ERR("%s: rtw_halmac_read_bt_physical_efuse_map fail!\n", __FUNCTION__);
+				rtw_mfree(efuse, size);
+				return _FAIL;
+			}
+			dump_buf(efuse + addr, cnts);
+
+			_rtw_memcpy(data, efuse + addr, cnts);
+
+			RTW_INFO("%s: rtw_halmac_read_bt_physical_efuse_map ok! data 0x%x\n", __FUNCTION__, *data);
+			rtw_mfree(efuse, size);
+		}
+	}
+
+	return _SUCCESS;
+}
+
+u8 rtw_efuse_map_read(PADAPTER adapter, u16 addr, u16 cnts, u8 *data)
+{
+	struct dvobj_priv *d;
+	u8 *efuse = NULL;
+	u32 size, i;
+	int err;
+	u32	backupRegs[4] = {0};
+	u8 status = _SUCCESS;
+
+	efuse_PreUpdateAction(adapter, backupRegs);
+
+	d = adapter_to_dvobj(adapter);
+	err = rtw_halmac_get_logical_efuse_size(d, &size);
+	if (err) {
+		status = _FAIL;
+		goto exit;
+	}
+	/* size error handle */
+	if ((addr + cnts) > size) {
+		if (addr < size)
+			cnts = size - addr;
+		else {
+			status = _FAIL;
+			goto exit;
+		}
+	}
+
+	if (cnts > 16)
+		efuse = rtw_zmalloc(size);
+
+	if (efuse) {
+		err = rtw_halmac_read_logical_efuse_map(d, efuse, size, NULL, 0);
+		if (err) {
+			rtw_mfree(efuse, size);
+			status = _FAIL;
+			goto exit;
+		}
+
+		_rtw_memcpy(data, efuse + addr, cnts);
+		rtw_mfree(efuse, size);
+	} else {
+		err = rtw_halmac_read_logical_efuse(d, addr, cnts, data);
+		if (err) {
+			status = _FAIL;
+			goto exit;
+		}
+	}
+	status = _SUCCESS;
+exit:
+	efuse_PostUpdateAction(adapter, backupRegs);
+
+	return status;
+}
+
+u8 rtw_efuse_map_write(PADAPTER adapter, u16 addr, u16 cnts, u8 *data)
+{
+	struct dvobj_priv *d;
+	u8 *efuse = NULL;
+	u32 size, i;
+	int err;
+	u8 mask_buf[64] = "";
+	u16 mask_len = sizeof(u8) * rtw_get_efuse_mask_arraylen(adapter);
+	u32 backupRegs[4] = {0};
+	u8 status = _SUCCESS;;
+
+	efuse_PreUpdateAction(adapter, backupRegs);
+
+	d = adapter_to_dvobj(adapter);
+	err = rtw_halmac_get_logical_efuse_size(d, &size);
+	if (err) {
+		status = _FAIL;
+		goto exit;
+	}
+
+	if ((addr + cnts) > size) {
+		status = _FAIL;
+		goto exit;
+	}
+
+	efuse = rtw_zmalloc(size);
+	if (!efuse) {
+		status = _FAIL;
+		goto exit;
+	}
+
+	err = rtw_halmac_read_logical_efuse_map(d, efuse, size, NULL, 0);
+	if (err) {
+		rtw_mfree(efuse, size);
+		status = _FAIL;
+		goto exit;
+	}
+
+	_rtw_memcpy(efuse + addr, data, cnts);
+
+	if (adapter->registrypriv.boffefusemask == 0) {
+		RTW_INFO("Use mask Array Len: %d\n", mask_len);
+
+		if (mask_len != 0) {
+			if (adapter->registrypriv.bFileMaskEfuse == _TRUE)
+				_rtw_memcpy(mask_buf, maskfileBuffer, mask_len);
+			else
+				rtw_efuse_mask_array(adapter, mask_buf);
+
+			err = rtw_halmac_write_logical_efuse_map(d, efuse, size, mask_buf, mask_len);
+		} else
+			err = rtw_halmac_write_logical_efuse_map(d, efuse, size, NULL, 0);
+	} else {
+		_rtw_memset(mask_buf, 0xFF, sizeof(mask_buf));
+		RTW_INFO("Efuse mask off\n");
+		err = rtw_halmac_write_logical_efuse_map(d, efuse, size, mask_buf, size/16);
+	}
+
+	if (err) {
+		rtw_mfree(efuse, size);
+		status = _FAIL;
+		goto exit;
+	}
+
+	rtw_mfree(efuse, size);
+	status = _SUCCESS;
+exit :
+	efuse_PostUpdateAction(adapter, backupRegs);
+
+	return status;
+}
+
+int Efuse_PgPacketRead(PADAPTER adapter, u8 offset, u8 *data, BOOLEAN test)
+{
+	return _FALSE;
+}
+
+int Efuse_PgPacketWrite(PADAPTER adapter, u8 offset, u8 word_en, u8 *data, BOOLEAN test)
+{
+	return _FALSE;
+}
+
+u8 rtw_BT_efuse_map_read(PADAPTER adapter, u16 addr, u16 cnts, u8 *data)
+{
+	hal_ReadEFuse_BT_logic_map(adapter,addr, cnts, data);
+
+	return _SUCCESS;
+}
+
+u8 rtw_BT_efuse_map_write(PADAPTER adapter, u16 addr, u16 cnts, u8 *data)
+{
+#define RT_ASSERT_RET(expr)									\
+	if (!(expr)) {										\
+		printk("Assertion failed! %s at ......\n", #expr);				\
+		printk("	  ......%s,%s, line=%d\n",__FILE__, __FUNCTION__, __LINE__);	\
+		return _FAIL;	\
+	}
+
+	u8	offset, word_en;
+	u8	*map;
+	u8	newdata[PGPKT_DATA_SIZE];
+	s32 i = 0, j = 0, idx;
+	u8	ret = _SUCCESS;
+	u16 mapLen = 1024;
+
+	if ((addr + cnts) > mapLen)
+		return _FAIL;
+
+	RT_ASSERT_RET(PGPKT_DATA_SIZE == 8); /* have to be 8 byte alignment */
+	RT_ASSERT_RET((mapLen & 0x7) == 0); /* have to be PGPKT_DATA_SIZE alignment for memcpy */
+
+	map = rtw_zmalloc(mapLen);
+	if (map == NULL)
+		return _FAIL;
+
+	ret = rtw_BT_efuse_map_read(adapter, 0, mapLen, map);
+	if (ret == _FAIL)
+		goto exit;
+	RTW_INFO("OFFSET\tVALUE(hex)\n");
+	for (i = 0; i < mapLen; i += 16) { /* set 512 because the iwpriv's extra size have limit 0x7FF */
+		RTW_INFO("0x%03x\t", i);
+		for (j = 0; j < 8; j++)
+			RTW_INFO("%02X ", map[i + j]);
+		RTW_INFO("\t");
+		for (; j < 16; j++)
+			RTW_INFO("%02X ", map[i + j]);
+		RTW_INFO("\n");
+	}
+	RTW_INFO("\n");
+
+	idx = 0;
+	offset = (addr >> 3);
+	while (idx < cnts) {
+		word_en = 0xF;
+		j = (addr + idx) & 0x7;
+		_rtw_memcpy(newdata, &map[offset << 3], PGPKT_DATA_SIZE);
+		for (i = j; i < PGPKT_DATA_SIZE && idx < cnts; i++, idx++) {
+			if (data[idx] != map[addr + idx]) {
+				word_en &= ~BIT(i >> 1);
+				newdata[i] = data[idx];
+			}
+		}
+
+		if (word_en != 0xF) {
+			ret = EfusePgPacketWrite_BT(adapter, offset, word_en, newdata, _FALSE);
+			RTW_INFO("offset=%x\n", offset);
+			RTW_INFO("word_en=%x\n", word_en);
+			RTW_INFO("%s: data=", __FUNCTION__);
+			for (i = 0; i < PGPKT_DATA_SIZE; i++)
+				RTW_INFO("0x%02X ", newdata[i]);
+			RTW_INFO("\n");
+			if (ret == _FAIL)
+				break;
+		}
+		offset++;
+	}
+exit:
+	rtw_mfree(map, mapLen);
+	return _SUCCESS;
+}
+
+VOID hal_ReadEFuse_BT_logic_map(
+	PADAPTER	padapter,
+	u16			_offset,
+	u16			_size_byte,
+	u8			*pbuf
+)
+{
+
+	PHAL_DATA_TYPE	pHalData = GET_HAL_DATA(padapter);
+	PEFUSE_HAL		pEfuseHal = &pHalData->EfuseHal;
+
+	u8	*efuseTbl, *phyefuse;
+	u8	bank;
+	u16	eFuse_Addr = 0;
+	u8	efuseHeader, efuseExtHdr, efuseData;
+	u8	offset, wden;
+	u16	i, total, used;
+	u8	efuse_usage;
+
+
+	/* */
+	/* Do NOT excess total size of EFuse table. Added by Roger, 2008.11.10. */
+	/* */
+	if ((_offset + _size_byte) > EFUSE_BT_MAP_LEN) {
+		RTW_INFO("%s: Invalid offset(%#x) with read bytes(%#x)!!\n", __FUNCTION__, _offset, _size_byte);
+		return;
+	}
+
+	efuseTbl = rtw_malloc(EFUSE_BT_MAP_LEN);
+	phyefuse = rtw_malloc(EFUSE_BT_REAL_CONTENT_LEN);
+	if (efuseTbl == NULL || phyefuse == NULL) {
+		RTW_INFO("%s: efuseTbl or phyefuse malloc fail!\n", __FUNCTION__);
+		goto exit;
+	}
+
+	/* 0xff will be efuse default value instead of 0x00. */
+	_rtw_memset(efuseTbl, 0xFF, EFUSE_BT_MAP_LEN);
+	_rtw_memset(phyefuse, 0xFF, EFUSE_BT_REAL_CONTENT_LEN);
+
+	if (rtw_efuse_bt_access(padapter, _FALSE, 0, EFUSE_BT_REAL_CONTENT_LEN, phyefuse))
+		dump_buf(phyefuse, EFUSE_BT_REAL_BANK_CONTENT_LEN);
+	
+	total = BANK_NUM;
+	for (bank = 1; bank <= total; bank++) { /* 8723d Max bake 0~2 */
+		eFuse_Addr = 0;
+
+		while (AVAILABLE_EFUSE_ADDR(eFuse_Addr)) {
+			/* ReadEFuseByte(padapter, eFuse_Addr++, &efuseHeader, bPseudoTest); */
+			efuseHeader = phyefuse[eFuse_Addr++];
+
+			if (efuseHeader == 0xFF)
+				break;
+			RTW_INFO("%s: efuse[%#X]=0x%02x (header)\n", __FUNCTION__, (((bank - 1) * EFUSE_BT_REAL_CONTENT_LEN) + eFuse_Addr - 1), efuseHeader);
+
+			/* Check PG header for section num. */
+			if (EXT_HEADER(efuseHeader)) {	/* extended header */
+				offset = GET_HDR_OFFSET_2_0(efuseHeader);
+				RTW_INFO("%s: extended header offset_2_0=0x%X\n", __FUNCTION__, offset);
+
+				/* ReadEFuseByte(padapter, eFuse_Addr++, &efuseExtHdr, bPseudoTest); */
+				efuseExtHdr = phyefuse[eFuse_Addr++];
+
+				RTW_INFO("%s: efuse[%#X]=0x%02x (ext header)\n", __FUNCTION__, (((bank - 1) * EFUSE_BT_REAL_CONTENT_LEN) + eFuse_Addr - 1), efuseExtHdr);
+				if (ALL_WORDS_DISABLED(efuseExtHdr))
+					continue;
+
+				offset |= ((efuseExtHdr & 0xF0) >> 1);
+				wden = (efuseExtHdr & 0x0F);
+			} else {
+				offset = ((efuseHeader >> 4) & 0x0f);
+				wden = (efuseHeader & 0x0f);
+			}
+
+			if (offset < EFUSE_BT_MAX_SECTION) {
+				u16 addr;
+
+				/* Get word enable value from PG header */
+				RTW_INFO("%s: Offset=%d Worden=%#X\n", __FUNCTION__, offset, wden);
+
+				addr = offset * PGPKT_DATA_SIZE;
+				for (i = 0; i < EFUSE_MAX_WORD_UNIT; i++) {
+					/* Check word enable condition in the section */
+					if (!(wden & (0x01 << i))) {
+						efuseData = 0;
+						/* ReadEFuseByte(padapter, eFuse_Addr++, &efuseData, bPseudoTest); */
+						efuseData = phyefuse[eFuse_Addr++];
+
+						RTW_INFO("%s: efuse[%#X]=0x%02X\n", __FUNCTION__, eFuse_Addr - 1, efuseData);
+						efuseTbl[addr] = efuseData;
+
+						efuseData = 0;
+						/* ReadEFuseByte(padapter, eFuse_Addr++, &efuseData, bPseudoTest); */
+						efuseData = phyefuse[eFuse_Addr++];
+
+						RTW_INFO("%s: efuse[%#X]=0x%02X\n", __FUNCTION__, eFuse_Addr - 1, efuseData);
+						efuseTbl[addr + 1] = efuseData;
+					}
+					addr += 2;
+				}
+			} else {
+				RTW_INFO("%s: offset(%d) is illegal!!\n", __FUNCTION__, offset);
+				eFuse_Addr += Efuse_CalculateWordCnts(wden) * 2;
+			}
+		}
+
+		if ((eFuse_Addr - 1) < total) {
+			RTW_INFO("%s: bank(%d) data end at %#x\n", __FUNCTION__, bank, eFuse_Addr - 1);
+			break;
+		}
+	}
+
+	/* switch bank back to bank 0 for later BT and wifi use. */
+	//hal_EfuseSwitchToBank(padapter, 0, bPseudoTest);
+
+	/* Copy from Efuse map to output pointer memory!!! */
+	for (i = 0; i < _size_byte; i++)
+		pbuf[i] = efuseTbl[_offset + i];
+	/* Calculate Efuse utilization */
+	total = EFUSE_BT_REAL_BANK_CONTENT_LEN;
+
+	used = eFuse_Addr - 1;
+
+	if (total)
+		efuse_usage = (u8)((used * 100) / total);
+	else
+		efuse_usage = 100;
+
+	fakeBTEfuseUsedBytes = used;
+	RTW_INFO("%s: BTEfuseUsed last Bytes = %#x\n", __FUNCTION__, fakeBTEfuseUsedBytes);
+
+exit:
+	if (efuseTbl)
+		rtw_mfree(efuseTbl, EFUSE_BT_MAP_LEN);
+	if (phyefuse)
+		rtw_mfree(phyefuse, EFUSE_BT_REAL_BANK_CONTENT_LEN);
+}
+
+
+static u8 hal_EfusePartialWriteCheck(
+	PADAPTER		padapter,
+	u8				efuseType,
+	u16				*pAddr,
+	PPGPKT_STRUCT	pTargetPkt,
+	u8				bPseudoTest)
+{
+	PHAL_DATA_TYPE	pHalData = GET_HAL_DATA(padapter);
+	PEFUSE_HAL		pEfuseHal = &pHalData->EfuseHal;
+	u8	bRet = _FALSE;
+	u16	startAddr = 0, efuse_max_available_len = EFUSE_BT_REAL_BANK_CONTENT_LEN, efuse_max = EFUSE_BT_REAL_BANK_CONTENT_LEN;
+	u8	efuse_data = 0;
+
+	startAddr = (u16)fakeBTEfuseUsedBytes;
+
+	startAddr %= efuse_max;
+	RTW_INFO("%s: startAddr=%#X\n", __FUNCTION__, startAddr);
+
+	while (1) {
+		if (startAddr >= efuse_max_available_len) {
+			bRet = _FALSE;
+			RTW_INFO("%s: startAddr(%d) >= efuse_max_available_len(%d)\n",
+				__FUNCTION__, startAddr, efuse_max_available_len);
+			break;
+		}
+		if (rtw_efuse_bt_access(padapter, _FALSE, startAddr, 1, &efuse_data)&& (efuse_data != 0xFF)) {
+			bRet = _FALSE;
+			RTW_INFO("%s: Something Wrong! last bytes(%#X=0x%02X) is not 0xFF\n",
+				 __FUNCTION__, startAddr, efuse_data);
+			break;
+		} else {
+			/* not used header, 0xff */
+			*pAddr = startAddr;
+			/*			RTW_INFO("%s: Started from unused header offset=%d\n", __FUNCTION__, startAddr)); */
+			bRet = _TRUE;
+			break;
+		}
+	}
+
+	return bRet;
+}
+
+
+static u8 hal_EfusePgPacketWrite2ByteHeader(
+	PADAPTER		padapter,
+	u8				efuseType,
+	u16				*pAddr,
+	PPGPKT_STRUCT	pTargetPkt,
+	u8				bPseudoTest)
+{
+	u16	efuse_addr, efuse_max_available_len = EFUSE_BT_REAL_BANK_CONTENT_LEN;
+	u8	pg_header = 0, tmp_header = 0;
+	u8	repeatcnt = 0;
+
+	/*	RTW_INFO("%s\n", __FUNCTION__); */
+
+	efuse_addr = *pAddr;
+	if (efuse_addr >= efuse_max_available_len) {
+		RTW_INFO("%s: addr(%d) over avaliable(%d)!!\n", __FUNCTION__, efuse_addr, efuse_max_available_len);
+		return _FALSE;
+	}
+
+	pg_header = ((pTargetPkt->offset & 0x07) << 5) | 0x0F;
+	/*	RTW_INFO("%s: pg_header=0x%x\n", __FUNCTION__, pg_header); */
+
+	do {
+		
+		rtw_efuse_bt_access(padapter, _TRUE, efuse_addr, 1, &pg_header);
+		rtw_efuse_bt_access(padapter, _FALSE, efuse_addr, 1, &tmp_header);
+
+		if (tmp_header != 0xFF)
+			break;
+		if (repeatcnt++ > EFUSE_REPEAT_THRESHOLD_) {
+			RTW_INFO("%s: Repeat over limit for pg_header!!\n", __FUNCTION__);
+			return _FALSE;
+		}
+	} while (1);
+
+	if (tmp_header != pg_header) {
+		RTW_ERR("%s: PG Header Fail!!(pg=0x%02X read=0x%02X)\n", __FUNCTION__, pg_header, tmp_header);
+		return _FALSE;
+	}
+
+	/* to write ext_header */
+	efuse_addr++;
+	pg_header = ((pTargetPkt->offset & 0x78) << 1) | pTargetPkt->word_en;
+
+	do {
+		rtw_efuse_bt_access(padapter, _TRUE, efuse_addr, 1, &pg_header);
+		rtw_efuse_bt_access(padapter, _FALSE, efuse_addr, 1, &tmp_header);
+
+		if (tmp_header != 0xFF)
+			break;
+		if (repeatcnt++ > EFUSE_REPEAT_THRESHOLD_) {
+			RTW_INFO("%s: Repeat over limit for ext_header!!\n", __FUNCTION__);
+			return _FALSE;
+		}
+	} while (1);
+
+	if (tmp_header != pg_header) {	/* offset PG fail */
+		RTW_ERR("%s: PG EXT Header Fail!!(pg=0x%02X read=0x%02X)\n", __FUNCTION__, pg_header, tmp_header);
+		return _FALSE;
+	}
+
+	*pAddr = efuse_addr;
+
+	return _TRUE;
+}
+
+
+static u8 hal_EfusePgPacketWrite1ByteHeader(
+	PADAPTER		pAdapter,
+	u8				efuseType,
+	u16				*pAddr,
+	PPGPKT_STRUCT	pTargetPkt,
+	u8				bPseudoTest)
+{
+	u8	bRet = _FALSE;
+	u8	pg_header = 0, tmp_header = 0;
+	u16	efuse_addr = *pAddr;
+	u8	repeatcnt = 0;
+
+
+	/*	RTW_INFO("%s\n", __FUNCTION__); */
+	pg_header = ((pTargetPkt->offset << 4) & 0xf0) | pTargetPkt->word_en;
+
+	do {
+		rtw_efuse_bt_access(pAdapter, _TRUE, efuse_addr, 1, &pg_header);
+		rtw_efuse_bt_access(pAdapter, _FALSE, efuse_addr, 1, &tmp_header);
+
+		if (tmp_header != 0xFF)
+			break;
+		if (repeatcnt++ > EFUSE_REPEAT_THRESHOLD_) {
+			RTW_INFO("%s: Repeat over limit for pg_header!!\n", __FUNCTION__);
+			return _FALSE;
+		}
+	} while (1);
+
+	if (tmp_header != pg_header) {
+		RTW_ERR("%s: PG Header Fail!!(pg=0x%02X read=0x%02X)\n", __FUNCTION__, pg_header, tmp_header);
+		return _FALSE;
+	}
+
+	*pAddr = efuse_addr;
+
+	return _TRUE;
+}
+
+static u8 hal_EfusePgPacketWriteHeader(
+	PADAPTER		padapter,
+	u8				efuseType,
+	u16				*pAddr,
+	PPGPKT_STRUCT	pTargetPkt,
+	u8				bPseudoTest)
+{
+	u8 bRet = _FALSE;
+
+	if (pTargetPkt->offset >= EFUSE_MAX_SECTION_BASE)
+		bRet = hal_EfusePgPacketWrite2ByteHeader(padapter, efuseType, pAddr, pTargetPkt, bPseudoTest);
+	else
+		bRet = hal_EfusePgPacketWrite1ByteHeader(padapter, efuseType, pAddr, pTargetPkt, bPseudoTest);
+
+	return bRet;
+}
+
+
+static u8
+Hal_EfuseWordEnableDataWrite(
+	PADAPTER	padapter,
+	u16			efuse_addr,
+	u8			word_en,
+	u8			*data,
+	u8			bPseudoTest)
+{
+	u16	tmpaddr = 0;
+	u16	start_addr = efuse_addr;
+	u8	badworden = 0x0F;
+	u8	tmpdata[PGPKT_DATA_SIZE];
+
+
+	/*	RTW_INFO("%s: efuse_addr=%#x word_en=%#x\n", __FUNCTION__, efuse_addr, word_en); */
+	_rtw_memset(tmpdata, 0xFF, PGPKT_DATA_SIZE);
+
+	if (!(word_en & BIT(0))) {
+		tmpaddr = start_addr;
+		rtw_efuse_bt_access(padapter, _TRUE, start_addr++, 1, &data[0]);
+		rtw_efuse_bt_access(padapter, _TRUE, start_addr++, 1, &data[1]);
+		rtw_efuse_bt_access(padapter, _FALSE, tmpaddr, 1, &tmpdata[0]);
+		rtw_efuse_bt_access(padapter, _FALSE, tmpaddr + 1, 1, &tmpdata[1]);
+		if ((data[0] != tmpdata[0]) || (data[1] != tmpdata[1]))
+			badworden &= (~BIT(0));
+	}
+	if (!(word_en & BIT(1))) {
+		tmpaddr = start_addr;
+		rtw_efuse_bt_access(padapter, _TRUE, start_addr++, 1, &data[2]);
+		rtw_efuse_bt_access(padapter, _TRUE, start_addr++, 1, &data[3]);
+		rtw_efuse_bt_access(padapter, _FALSE, tmpaddr, 1, &tmpdata[2]);
+		rtw_efuse_bt_access(padapter, _FALSE, tmpaddr + 1, 1, &tmpdata[3]);
+		if ((data[2] != tmpdata[2]) || (data[3] != tmpdata[3]))
+			badworden &= (~BIT(1));
+	}
+	if (!(word_en & BIT(2))) {
+		tmpaddr = start_addr;
+		rtw_efuse_bt_access(padapter, _TRUE, start_addr++, 1, &data[4]);
+		rtw_efuse_bt_access(padapter, _TRUE, start_addr++, 1, &data[5]);
+		rtw_efuse_bt_access(padapter, _FALSE, tmpaddr, 1, &tmpdata[4]);
+		rtw_efuse_bt_access(padapter, _FALSE, tmpaddr + 1, 1, &tmpdata[5]);
+		if ((data[4] != tmpdata[4]) || (data[5] != tmpdata[5]))
+			badworden &= (~BIT(2));
+	}
+	if (!(word_en & BIT(3))) {
+		tmpaddr = start_addr;
+		rtw_efuse_bt_access(padapter, _TRUE, start_addr++, 1, &data[6]);
+		rtw_efuse_bt_access(padapter, _TRUE, start_addr++, 1, &data[7]);
+		rtw_efuse_bt_access(padapter, _FALSE, tmpaddr, 1, &tmpdata[6]);
+		rtw_efuse_bt_access(padapter, _FALSE, tmpaddr + 1, 1, &tmpdata[7]);
+
+		if ((data[6] != tmpdata[6]) || (data[7] != tmpdata[7]))
+			badworden &= (~BIT(3));
+	}
+
+	return badworden;
+}
+
+static void
+hal_EfuseConstructPGPkt(
+	u8				offset,
+	u8				word_en,
+	u8				*pData,
+	PPGPKT_STRUCT	pTargetPkt)
+{
+	_rtw_memset(pTargetPkt->data, 0xFF, PGPKT_DATA_SIZE);
+	pTargetPkt->offset = offset;
+	pTargetPkt->word_en = word_en;
+	efuse_WordEnableDataRead(word_en, pData, pTargetPkt->data);
+	pTargetPkt->word_cnts = Efuse_CalculateWordCnts(pTargetPkt->word_en);
+}
+
+static u8
+hal_EfusePgPacketWriteData(
+	PADAPTER		pAdapter,
+	u8				efuseType,
+	u16				*pAddr,
+	PPGPKT_STRUCT	pTargetPkt,
+	u8				bPseudoTest)
+{
+	u16	efuse_addr;
+	u8	badworden;
+
+	efuse_addr = *pAddr;
+	badworden = Hal_EfuseWordEnableDataWrite(pAdapter, efuse_addr + 1, pTargetPkt->word_en, pTargetPkt->data, bPseudoTest);
+	if (badworden != 0x0F) {
+		RTW_INFO("%s: Fail!!\n", __FUNCTION__);
+		return _FALSE;
+	} else
+		RTW_INFO("%s: OK!!\n", __FUNCTION__);
+
+	return _TRUE;
+}
+
+u8 efuse_OneByteRead(struct _ADAPTER *a, u16 addr, u8 *data, u8 bPseudoTest)
+{
+		struct dvobj_priv *d;
+		int err;
+		u8 ret = _TRUE;
+
+		d = adapter_to_dvobj(a);
+		err = rtw_halmac_read_physical_efuse(d, addr, 1, data);
+		if (err) {
+			RTW_ERR("%s: addr=0x%x FAIL!!!\n", __FUNCTION__, addr);
+			ret = _FALSE;
+		}
+
+		return ret;
+	
+}
+
+static u16
+hal_EfuseGetCurrentSize_BT(
+	PADAPTER	padapter,
+	u8			bPseudoTest)
+{
+#ifdef HAL_EFUSE_MEMORY
+	PHAL_DATA_TYPE	pHalData = GET_HAL_DATA(padapter);
+	PEFUSE_HAL		pEfuseHal = &pHalData->EfuseHal;
+#endif
+	u16 btusedbytes;
+	u16	efuse_addr;
+	u8	bank, startBank;
+	u8	hoffset = 0, hworden = 0;
+	u8	efuse_data, word_cnts = 0;
+	u16	retU2 = 0;
+	u8 bContinual = _TRUE;
+
+
+	btusedbytes = fakeBTEfuseUsedBytes;
+
+	efuse_addr = (u16)((btusedbytes % EFUSE_BT_REAL_BANK_CONTENT_LEN));
+	startBank = (u8)(1 + (btusedbytes / EFUSE_BT_REAL_BANK_CONTENT_LEN));
+
+	RTW_INFO("%s: start from bank=%d addr=0x%X\n", __FUNCTION__, startBank, efuse_addr);
+	retU2 = EFUSE_BT_REAL_CONTENT_LEN - EFUSE_PROTECT_BYTES_BANK;
+
+	for (bank = startBank; bank < 3; bank++) {
+		if (hal_EfuseSwitchToBank(padapter, bank, bPseudoTest) == _FALSE) {
+			RTW_ERR("%s: switch bank(%d) Fail!!\n", __FUNCTION__, bank);
+			/* bank = EFUSE_MAX_BANK; */
+			break;
+		}
+
+		/* only when bank is switched we have to reset the efuse_addr. */
+		if (bank != startBank)
+			efuse_addr = 0;
+
+
+		while (AVAILABLE_EFUSE_ADDR(efuse_addr)) {
+			if (rtw_efuse_bt_access(padapter, _FALSE, efuse_addr, 1, &efuse_data) == _FALSE) {
+				RTW_ERR("%s: efuse_OneByteRead Fail! addr=0x%X !!\n", __FUNCTION__, efuse_addr);
+				/* bank = EFUSE_MAX_BANK; */
+				break;
+			}
+			RTW_INFO("%s: efuse_OneByteRead ! addr=0x%X !efuse_data=0x%X! bank =%d\n", __FUNCTION__, efuse_addr, efuse_data, bank);
+
+			if (efuse_data == 0xFF)
+				break;
+
+			if (EXT_HEADER(efuse_data)) {
+				hoffset = GET_HDR_OFFSET_2_0(efuse_data);
+				efuse_addr++;
+				rtw_efuse_bt_access(padapter, _FALSE, efuse_addr, 1, &efuse_data);
+				RTW_INFO("%s: efuse_OneByteRead EXT_HEADER ! addr=0x%X !efuse_data=0x%X! bank =%d\n", __FUNCTION__, efuse_addr, efuse_data, bank);
+
+				if (ALL_WORDS_DISABLED(efuse_data)) {
+					efuse_addr++;
+					continue;
+				}
+
+				/*				hoffset = ((hoffset & 0xE0) >> 5) | ((efuse_data & 0xF0) >> 1); */
+				hoffset |= ((efuse_data & 0xF0) >> 1);
+				hworden = efuse_data & 0x0F;
+			} else {
+				hoffset = (efuse_data >> 4) & 0x0F;
+				hworden =  efuse_data & 0x0F;
+			}
+
+			RTW_INFO(FUNC_ADPT_FMT": Offset=%d Worden=%#X\n",
+				 FUNC_ADPT_ARG(padapter), hoffset, hworden);
+
+			word_cnts = Efuse_CalculateWordCnts(hworden);
+			/* read next header */
+			efuse_addr += (word_cnts * 2) + 1;
+		}
+		/* Check if we need to check next bank efuse */
+		if (efuse_addr < retU2)
+			break;/* don't need to check next bank. */
+	}
+	retU2 = ((bank - 1) * EFUSE_BT_REAL_BANK_CONTENT_LEN) + efuse_addr;
+
+	fakeBTEfuseUsedBytes = retU2;
+	RTW_INFO("%s: CurrentSize=%d\n", __FUNCTION__, retU2);
+	return retU2;
+}
+
+
+static u8
+hal_BT_EfusePgCheckAvailableAddr(
+	PADAPTER	pAdapter,
+	u8		bPseudoTest)
+{
+	u16	max_available = EFUSE_BT_REAL_CONTENT_LEN - EFUSE_PROTECT_BYTES_BANK;
+	u16	current_size = 0;
+
+	 RTW_INFO("%s: max_available=%d\n", __FUNCTION__, max_available);
+	current_size = hal_EfuseGetCurrentSize_BT(pAdapter, bPseudoTest);
+	if (current_size >= max_available) {
+		RTW_INFO("%s: Error!! current_size(%d)>max_available(%d)\n", __FUNCTION__, current_size, max_available);
+		return _FALSE;
+	}
+	return _TRUE;
+}
+
+u8 EfusePgPacketWrite_BT(
+	PADAPTER	pAdapter,
+	u8			offset,
+	u8			word_en,
+	u8			*pData,
+	u8			bPseudoTest)
+{
+	PGPKT_STRUCT targetPkt;
+	u16 startAddr = 0;
+	u8 efuseType = EFUSE_BT;
+
+	if (!hal_BT_EfusePgCheckAvailableAddr(pAdapter, bPseudoTest))
+		return _FALSE;
+
+	hal_EfuseConstructPGPkt(offset, word_en, pData, &targetPkt);
+
+	if (!hal_EfusePartialWriteCheck(pAdapter, efuseType, &startAddr, &targetPkt, bPseudoTest))
+		return _FALSE;
+
+	if (!hal_EfusePgPacketWriteHeader(pAdapter, efuseType, &startAddr, &targetPkt, bPseudoTest))
+		return _FALSE;
+
+	if (!hal_EfusePgPacketWriteData(pAdapter, efuseType, &startAddr, &targetPkt, bPseudoTest))
+		return _FALSE;
+
+	return _TRUE;
+}
+
+
+#else /* !RTW_HALMAC */
+/* ------------------------------------------------------------------------------ */
+#define REG_EFUSE_CTRL		0x0030
+#define EFUSE_CTRL			REG_EFUSE_CTRL		/* E-Fuse Control. */
+/* ------------------------------------------------------------------------------ */
+
+
+BOOLEAN
+Efuse_Read1ByteFromFakeContent(
+	IN		PADAPTER	pAdapter,
+	IN		u16		Offset,
+	IN OUT	u8		*Value);
+BOOLEAN
+Efuse_Read1ByteFromFakeContent(
+	IN		PADAPTER	pAdapter,
+	IN		u16		Offset,
+	IN OUT	u8		*Value)
+{
+	if (Offset >= EFUSE_MAX_HW_SIZE)
+		return _FALSE;
+	/* DbgPrint("Read fake content, offset = %d\n", Offset); */
+	if (fakeEfuseBank == 0)
+		*Value = fakeEfuseContent[Offset];
+	else
+		*Value = fakeBTEfuseContent[fakeEfuseBank - 1][Offset];
+	return _TRUE;
+}
+
+BOOLEAN
+Efuse_Write1ByteToFakeContent(
+	IN		PADAPTER	pAdapter,
+	IN		u16		Offset,
+	IN		u8		Value);
+BOOLEAN
+Efuse_Write1ByteToFakeContent(
+	IN		PADAPTER	pAdapter,
+	IN		u16		Offset,
+	IN		u8		Value)
+{
+	if (Offset >= EFUSE_MAX_HW_SIZE)
+		return _FALSE;
+	if (fakeEfuseBank == 0)
+		fakeEfuseContent[Offset] = Value;
+	else
+		fakeBTEfuseContent[fakeEfuseBank - 1][Offset] = Value;
+	return _TRUE;
+}
+
+/*-----------------------------------------------------------------------------
+ * Function:	Efuse_PowerSwitch
+ *
+ * Overview:	When we want to enable write operation, we should change to
+ *				pwr on state. When we stop write, we should switch to 500k mode
+ *				and disable LDO 2.5V.
+ *
+ * Input:       NONE
+ *
+ * Output:      NONE
+ *
+ * Return:      NONE
+ *
+ * Revised History:
+ * When			Who		Remark
+ * 11/17/2008	MHC		Create Version 0.
+ *
+ *---------------------------------------------------------------------------*/
+VOID
+Efuse_PowerSwitch(
+	IN	PADAPTER	pAdapter,
+	IN	u8		bWrite,
+	IN	u8		PwrState)
+{
+	pAdapter->hal_func.EfusePowerSwitch(pAdapter, bWrite, PwrState);
+}
+
+VOID
+BTEfuse_PowerSwitch(
+	IN	PADAPTER	pAdapter,
+	IN	u8		bWrite,
+	IN	u8		PwrState)
+{
+	if (pAdapter->hal_func.BTEfusePowerSwitch)
+		pAdapter->hal_func.BTEfusePowerSwitch(pAdapter, bWrite, PwrState);
+}
+
+/*-----------------------------------------------------------------------------
+ * Function:	efuse_GetCurrentSize
+ *
+ * Overview:	Get current efuse size!!!
+ *
+ * Input:       NONE
+ *
+ * Output:      NONE
+ *
+ * Return:      NONE
+ *
+ * Revised History:
+ * When			Who		Remark
+ * 11/16/2008	MHC		Create Version 0.
+ *
+ *---------------------------------------------------------------------------*/
+u16
+Efuse_GetCurrentSize(
+	IN PADAPTER		pAdapter,
+	IN u8			efuseType,
+	IN BOOLEAN		bPseudoTest)
+{
+	u16 ret = 0;
+
+	ret = pAdapter->hal_func.EfuseGetCurrentSize(pAdapter, efuseType, bPseudoTest);
+
+	return ret;
+}
+
+/*
+ *	Description:
+ *		Execute E-Fuse read byte operation.
+ *		Refered from SD1 Richard.
+ *
+ *	Assumption:
+ *		1. Boot from E-Fuse and successfully auto-load.
+ *		2. PASSIVE_LEVEL (USB interface)
+ *
+ *	Created by Roger, 2008.10.21.
+ *   */
+VOID
+ReadEFuseByte(
+	PADAPTER	Adapter,
+	u16			_offset,
+	u8			*pbuf,
+	IN BOOLEAN	bPseudoTest)
+{
+	u32	value32;
+	u8	readbyte;
+	u16	retry;
+	/* systime start=rtw_get_current_time(); */
+
+	if (bPseudoTest) {
+		Efuse_Read1ByteFromFakeContent(Adapter, _offset, pbuf);
+		return;
+	}
+	if (IS_HARDWARE_TYPE_8723B(Adapter)) {
+		/* <20130121, Kordan> For SMIC S55 EFUSE specificatoin. */
+		/* 0x34[11]: SW force PGMEN input of efuse to high. (for the bank selected by 0x34[9:8]) */
+		phy_set_mac_reg(Adapter, EFUSE_TEST, BIT11, 0);
+	}
+	/* Write Address */
+	rtw_write8(Adapter, EFUSE_CTRL + 1, (_offset & 0xff));
+	readbyte = rtw_read8(Adapter, EFUSE_CTRL + 2);
+	rtw_write8(Adapter, EFUSE_CTRL + 2, ((_offset >> 8) & 0x03) | (readbyte & 0xfc));
+
+	/* Write bit 32 0 */
+	readbyte = rtw_read8(Adapter, EFUSE_CTRL + 3);
+	rtw_write8(Adapter, EFUSE_CTRL + 3, (readbyte & 0x7f));
+
+	/* Check bit 32 read-ready */
+	retry = 0;
+	value32 = rtw_read32(Adapter, EFUSE_CTRL);
+	/* while(!(((value32 >> 24) & 0xff) & 0x80)  && (retry<10)) */
+	while (!(((value32 >> 24) & 0xff) & 0x80)  && (retry < 10000)) {
+		value32 = rtw_read32(Adapter, EFUSE_CTRL);
+		retry++;
+	}
+
+	/* 20100205 Joseph: Add delay suggested by SD1 Victor. */
+	/* This fix the problem that Efuse read error in high temperature condition. */
+	/* Designer says that there shall be some delay after ready bit is set, or the */
+	/* result will always stay on last data we read. */
+	rtw_udelay_os(50);
+	value32 = rtw_read32(Adapter, EFUSE_CTRL);
+
+	*pbuf = (u8)(value32 & 0xff);
+	/* RTW_INFO("ReadEFuseByte _offset:%08u, in %d ms\n",_offset ,rtw_get_passing_time_ms(start)); */
+
+}
+
+/*
+ *	Description:
+ *		1. Execute E-Fuse read byte operation according as map offset and
+ *		    save to E-Fuse table.
+ *		2. Refered from SD1 Richard.
+ *
+ *	Assumption:
+ *		1. Boot from E-Fuse and successfully auto-load.
+ *		2. PASSIVE_LEVEL (USB interface)
+ *
+ *	Created by Roger, 2008.10.21.
+ *
+ *	2008/12/12 MH	1. Reorganize code flow and reserve bytes. and add description.
+ *					2. Add efuse utilization collect.
+ *	2008/12/22 MH	Read Efuse must check if we write section 1 data again!!! Sec1
+ *					write addr must be after sec5.
+ *   */
+
+VOID
+efuse_ReadEFuse(
+	PADAPTER	Adapter,
+	u8		efuseType,
+	u16		_offset,
+	u16		_size_byte,
+	u8	*pbuf,
+	IN	BOOLEAN	bPseudoTest
+);
+VOID
+efuse_ReadEFuse(
+	PADAPTER	Adapter,
+	u8		efuseType,
+	u16		_offset,
+	u16		_size_byte,
+	u8	*pbuf,
+	IN	BOOLEAN	bPseudoTest
+)
+{
+	Adapter->hal_func.ReadEFuse(Adapter, efuseType, _offset, _size_byte, pbuf, bPseudoTest);
+}
+
+VOID
+EFUSE_GetEfuseDefinition(
+	IN		PADAPTER	pAdapter,
+	IN		u8		efuseType,
+	IN		u8		type,
+	OUT		void		*pOut,
+	IN		BOOLEAN		bPseudoTest
+)
+{
+	pAdapter->hal_func.EFUSEGetEfuseDefinition(pAdapter, efuseType, type, pOut, bPseudoTest);
+}
+
+
+/*  11/16/2008 MH Read one byte from real Efuse. */
+u8
+efuse_OneByteRead(
+	IN	PADAPTER	pAdapter,
+	IN	u16			addr,
+	IN	u8			*data,
+	IN	BOOLEAN		bPseudoTest)
+{
+	u32	tmpidx = 0;
+	u8	bResult;
+	u8	readbyte;
+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(pAdapter);
+
+	/* RTW_INFO("===> EFUSE_OneByteRead(), addr = %x\n", addr); */
+	/* RTW_INFO("===> EFUSE_OneByteRead() start, 0x34 = 0x%X\n", rtw_read32(pAdapter, EFUSE_TEST)); */
+
+	if (bPseudoTest) {
+		bResult = Efuse_Read1ByteFromFakeContent(pAdapter, addr, data);
+		return bResult;
+	}
+
+#ifdef CONFIG_RTL8710B
+	/* <20171208, Peter>, Dont do the following write16(0x34) */
+	if (IS_HARDWARE_TYPE_8710B(pAdapter)) {
+		bResult = pAdapter->hal_func.efuse_indirect_read4(pAdapter, addr, data);
+		return bResult;
+	}
+#endif
+
+	if (IS_HARDWARE_TYPE_8723B(pAdapter) ||
+	    (IS_HARDWARE_TYPE_8192E(pAdapter) && (!IS_A_CUT(pHalData->version_id))) ||
+	    (IS_VENDOR_8188E_I_CUT_SERIES(pAdapter)) || (IS_CHIP_VENDOR_SMIC(pHalData->version_id))
+	   ) {
+		/* <20130121, Kordan> For SMIC EFUSE specificatoin. */
+		/* 0x34[11]: SW force PGMEN input of efuse to high. (for the bank selected by 0x34[9:8])	 */
+		/* phy_set_mac_reg(pAdapter, 0x34, BIT11, 0); */
+		rtw_write16(pAdapter, 0x34, rtw_read16(pAdapter, 0x34) & (~BIT11));
+	}
+
+	/* -----------------e-fuse reg ctrl --------------------------------- */
+	/* address			 */
+	rtw_write8(pAdapter, EFUSE_CTRL + 1, (u8)(addr & 0xff));
+	rtw_write8(pAdapter, EFUSE_CTRL + 2, ((u8)((addr >> 8) & 0x03)) |
+		   (rtw_read8(pAdapter, EFUSE_CTRL + 2) & 0xFC));
+
+	/* rtw_write8(pAdapter, EFUSE_CTRL+3,  0x72); */ /* read cmd	 */
+	/* Write bit 32 0 */
+	readbyte = rtw_read8(pAdapter, EFUSE_CTRL + 3);
+	rtw_write8(pAdapter, EFUSE_CTRL + 3, (readbyte & 0x7f));
+
+	while (!(0x80 & rtw_read8(pAdapter, EFUSE_CTRL + 3)) && (tmpidx < 1000)) {
+		rtw_mdelay_os(1);
+		tmpidx++;
+	}
+	if (tmpidx < 100) {
+		*data = rtw_read8(pAdapter, EFUSE_CTRL);
+		bResult = _TRUE;
+	} else {
+		*data = 0xff;
+		bResult = _FALSE;
+		RTW_INFO("%s: [ERROR] addr=0x%x bResult=%d time out 1s !!!\n", __FUNCTION__, addr, bResult);
+		RTW_INFO("%s: [ERROR] EFUSE_CTRL =0x%08x !!!\n", __FUNCTION__, rtw_read32(pAdapter, EFUSE_CTRL));
+	}
+
+	return bResult;
+}
+
+/*  11/16/2008 MH Write one byte to reald Efuse. */
+u8
+efuse_OneByteWrite(
+	IN	PADAPTER	pAdapter,
+	IN	u16			addr,
+	IN	u8			data,
+	IN	BOOLEAN		bPseudoTest)
+{
+	u8	tmpidx = 0;
+	u8	bResult = _FALSE;
+	u32 efuseValue = 0;
+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(pAdapter);
+
+	/* RTW_INFO("===> EFUSE_OneByteWrite(), addr = %x data=%x\n", addr, data); */
+	/* RTW_INFO("===> EFUSE_OneByteWrite() start, 0x34 = 0x%X\n", rtw_read32(pAdapter, EFUSE_TEST)); */
+
+	if (bPseudoTest) {
+		bResult = Efuse_Write1ByteToFakeContent(pAdapter, addr, data);
+		return bResult;
+	}
+
+	Efuse_PowerSwitch(pAdapter, _TRUE, _TRUE);
+
+	/* -----------------e-fuse reg ctrl ---------------------------------	 */
+	/* address			 */
+
+
+	efuseValue = rtw_read32(pAdapter, EFUSE_CTRL);
+	efuseValue |= (BIT21 | BIT31);
+	efuseValue &= ~(0x3FFFF);
+	efuseValue |= ((addr << 8 | data) & 0x3FFFF);
+
+	/* <20130227, Kordan> 8192E MP chip A-cut had better not set 0x34[11] until B-Cut. */
+	if (IS_HARDWARE_TYPE_8723B(pAdapter) ||
+	    (IS_HARDWARE_TYPE_8192E(pAdapter) && (!IS_A_CUT(pHalData->version_id))) ||
+	    (IS_VENDOR_8188E_I_CUT_SERIES(pAdapter)) || (IS_CHIP_VENDOR_SMIC(pHalData->version_id))
+	   ) {
+		/* <20130121, Kordan> For SMIC EFUSE specificatoin. */
+		/* 0x34[11]: SW force PGMEN input of efuse to high. (for the bank selected by 0x34[9:8]) */
+		/* phy_set_mac_reg(pAdapter, 0x34, BIT11, 1); */
+		rtw_write16(pAdapter, 0x34, rtw_read16(pAdapter, 0x34) | (BIT11));
+		rtw_write32(pAdapter, EFUSE_CTRL, 0x90600000 | ((addr << 8 | data)));
+	} else
+		rtw_write32(pAdapter, EFUSE_CTRL, efuseValue);
+
+	rtw_mdelay_os(1);
+
+	while ((0x80 &  rtw_read8(pAdapter, EFUSE_CTRL + 3)) && (tmpidx < 100)) {
+		rtw_mdelay_os(1);
+		tmpidx++;
+	}
+
+	if (tmpidx < 100)
+		bResult = _TRUE;
+	else {
+		bResult = _FALSE;
+		RTW_INFO("%s: [ERROR] addr=0x%x ,efuseValue=0x%x ,bResult=%d time out 1s !!!\n",
+			 __FUNCTION__, addr, efuseValue, bResult);
+		RTW_INFO("%s: [ERROR] EFUSE_CTRL =0x%08x !!!\n", __FUNCTION__, rtw_read32(pAdapter, EFUSE_CTRL));
+	}
+
+	/* disable Efuse program enable */
+	if (IS_HARDWARE_TYPE_8723B(pAdapter) ||
+	    (IS_HARDWARE_TYPE_8192E(pAdapter) && (!IS_A_CUT(pHalData->version_id))) ||
+	    (IS_VENDOR_8188E_I_CUT_SERIES(pAdapter)) || (IS_CHIP_VENDOR_SMIC(pHalData->version_id))
+	   )
+		phy_set_mac_reg(pAdapter, EFUSE_TEST, BIT(11), 0);
+
+	Efuse_PowerSwitch(pAdapter, _TRUE, _FALSE);
+
+	return bResult;
+}
+
+int
+Efuse_PgPacketRead(IN	PADAPTER	pAdapter,
+		   IN	u8			offset,
+		   IN	u8			*data,
+		   IN	BOOLEAN		bPseudoTest)
+{
+	int	ret = 0;
+
+	ret =  pAdapter->hal_func.Efuse_PgPacketRead(pAdapter, offset, data, bPseudoTest);
+
+	return ret;
+}
+
+int
+Efuse_PgPacketWrite(IN	PADAPTER	pAdapter,
+		    IN	u8			offset,
+		    IN	u8			word_en,
+		    IN	u8			*data,
+		    IN	BOOLEAN		bPseudoTest)
+{
+	int ret;
+
+	ret =  pAdapter->hal_func.Efuse_PgPacketWrite(pAdapter, offset, word_en, data, bPseudoTest);
+
+	return ret;
+}
+
+
+int
+Efuse_PgPacketWrite_BT(IN	PADAPTER	pAdapter,
+		       IN	u8			offset,
+		       IN	u8			word_en,
+		       IN	u8			*data,
+		       IN	BOOLEAN		bPseudoTest)
+{
+	int ret;
+
+	ret =  pAdapter->hal_func.Efuse_PgPacketWrite_BT(pAdapter, offset, word_en, data, bPseudoTest);
+
+	return ret;
+}
+
+
+u8
+Efuse_WordEnableDataWrite(IN	PADAPTER	pAdapter,
+			  IN	u16		efuse_addr,
+			  IN	u8		word_en,
+			  IN	u8		*data,
+			  IN	BOOLEAN		bPseudoTest)
+{
+	u8	ret = 0;
+
+	ret =  pAdapter->hal_func.Efuse_WordEnableDataWrite(pAdapter, efuse_addr, word_en, data, bPseudoTest);
+
+	return ret;
+}
+
+static u8 efuse_read8(PADAPTER padapter, u16 address, u8 *value)
+{
+	return efuse_OneByteRead(padapter, address, value, _FALSE);
+}
+
+static u8 efuse_write8(PADAPTER padapter, u16 address, u8 *value)
+{
+	return efuse_OneByteWrite(padapter, address, *value, _FALSE);
+}
+
+/*
+ * read/wirte raw efuse data
+ */
+u8 rtw_efuse_access(PADAPTER padapter, u8 bWrite, u16 start_addr, u16 cnts, u8 *data)
+{
+	int i = 0;
+	u16	real_content_len = 0, max_available_size = 0;
+	u8 res = _FAIL ;
+	u8(*rw8)(PADAPTER, u16, u8 *);
+	u32	backupRegs[4] = {0};
+
+
+	EFUSE_GetEfuseDefinition(padapter, EFUSE_WIFI, TYPE_EFUSE_REAL_CONTENT_LEN, (PVOID)&real_content_len, _FALSE);
+	EFUSE_GetEfuseDefinition(padapter, EFUSE_WIFI, TYPE_AVAILABLE_EFUSE_BYTES_TOTAL, (PVOID)&max_available_size, _FALSE);
+
+	if (start_addr > real_content_len)
+		return _FAIL;
+
+	if (_TRUE == bWrite) {
+		if ((start_addr + cnts) > max_available_size)
+			return _FAIL;
+		rw8 = &efuse_write8;
+	} else
+		rw8 = &efuse_read8;
+
+	efuse_PreUpdateAction(padapter, backupRegs);
+
+	Efuse_PowerSwitch(padapter, bWrite, _TRUE);
+
+	/* e-fuse one byte read / write */
+	for (i = 0; i < cnts; i++) {
+		if (start_addr >= real_content_len) {
+			res = _FAIL;
+			break;
+		}
+
+		res = rw8(padapter, start_addr++, data++);
+		if (_FAIL == res)
+			break;
+	}
+
+	Efuse_PowerSwitch(padapter, bWrite, _FALSE);
+
+	efuse_PostUpdateAction(padapter, backupRegs);
+
+	return res;
+}
+/* ------------------------------------------------------------------------------ */
+u16 efuse_GetMaxSize(PADAPTER padapter)
+{
+	u16	max_size;
+
+	max_size = 0;
+	EFUSE_GetEfuseDefinition(padapter, EFUSE_WIFI , TYPE_AVAILABLE_EFUSE_BYTES_TOTAL, (PVOID)&max_size, _FALSE);
+	return max_size;
+}
+/* ------------------------------------------------------------------------------ */
+u8 efuse_GetCurrentSize(PADAPTER padapter, u16 *size)
+{
+	Efuse_PowerSwitch(padapter, _FALSE, _TRUE);
+	*size = Efuse_GetCurrentSize(padapter, EFUSE_WIFI, _FALSE);
+	Efuse_PowerSwitch(padapter, _FALSE, _FALSE);
+
+	return _SUCCESS;
+}
+/* ------------------------------------------------------------------------------ */
+u16 efuse_bt_GetMaxSize(PADAPTER padapter)
+{
+	u16	max_size;
+
+	max_size = 0;
+	EFUSE_GetEfuseDefinition(padapter, EFUSE_BT , TYPE_AVAILABLE_EFUSE_BYTES_TOTAL, (PVOID)&max_size, _FALSE);
+	return max_size;
+}
+
+u8 efuse_bt_GetCurrentSize(PADAPTER padapter, u16 *size)
+{
+	Efuse_PowerSwitch(padapter, _FALSE, _TRUE);
+	*size = Efuse_GetCurrentSize(padapter, EFUSE_BT, _FALSE);
+	Efuse_PowerSwitch(padapter, _FALSE, _FALSE);
+
+	return _SUCCESS;
+}
+
+u8 rtw_efuse_map_read(PADAPTER padapter, u16 addr, u16 cnts, u8 *data)
+{
+	u16	mapLen = 0;
+
+	EFUSE_GetEfuseDefinition(padapter, EFUSE_WIFI, TYPE_EFUSE_MAP_LEN, (PVOID)&mapLen, _FALSE);
+
+	if ((addr + cnts) > mapLen)
+		return _FAIL;
+
+	Efuse_PowerSwitch(padapter, _FALSE, _TRUE);
+
+	efuse_ReadEFuse(padapter, EFUSE_WIFI, addr, cnts, data, _FALSE);
+
+	Efuse_PowerSwitch(padapter, _FALSE, _FALSE);
+
+	return _SUCCESS;
+}
+
+u8 rtw_BT_efuse_map_read(PADAPTER padapter, u16 addr, u16 cnts, u8 *data)
+{
+	u16	mapLen = 0;
+
+	EFUSE_GetEfuseDefinition(padapter, EFUSE_BT, TYPE_EFUSE_MAP_LEN, (PVOID)&mapLen, _FALSE);
+
+	if ((addr + cnts) > mapLen)
+		return _FAIL;
+
+	Efuse_PowerSwitch(padapter, _FALSE, _TRUE);
+
+	efuse_ReadEFuse(padapter, EFUSE_BT, addr, cnts, data, _FALSE);
+
+	Efuse_PowerSwitch(padapter, _FALSE, _FALSE);
+
+	return _SUCCESS;
+}
+
+/* ------------------------------------------------------------------------------ */
+u8 rtw_efuse_map_write(PADAPTER padapter, u16 addr, u16 cnts, u8 *data)
+{
+#define RT_ASSERT_RET(expr)												\
+	if (!(expr)) {															\
+		printk("Assertion failed! %s at ......\n", #expr);							\
+		printk("      ......%s,%s, line=%d\n",__FILE__, __FUNCTION__, __LINE__);	\
+		return _FAIL;	\
+	}
+
+	u8 *efuse = NULL;
+	u8	offset, word_en;
+	u8	*map = NULL;
+	u8	newdata[PGPKT_DATA_SIZE];
+	s32	i, j, idx, chk_total_byte;
+	u8	ret = _SUCCESS;
+	u16	mapLen = 0, startAddr = 0, efuse_max_available_len = 0;
+	u32	backupRegs[4] = {0};
+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(padapter);
+	PEFUSE_HAL	pEfuseHal = &pHalData->EfuseHal;
+
+
+	EFUSE_GetEfuseDefinition(padapter, EFUSE_WIFI, TYPE_EFUSE_MAP_LEN, (PVOID)&mapLen, _FALSE);
+	EFUSE_GetEfuseDefinition(padapter, EFUSE_WIFI, TYPE_AVAILABLE_EFUSE_BYTES_TOTAL, &efuse_max_available_len, _FALSE);
+
+	if ((addr + cnts) > mapLen)
+		return _FAIL;
+
+	RT_ASSERT_RET(PGPKT_DATA_SIZE == 8); /* have to be 8 byte alignment */
+	RT_ASSERT_RET((mapLen & 0x7) == 0); /* have to be PGPKT_DATA_SIZE alignment for memcpy */
+
+	efuse = rtw_zmalloc(mapLen);
+	if (!efuse)
+		return _FAIL;
+
+	map = rtw_zmalloc(mapLen);
+	if (map == NULL) {
+		rtw_mfree(efuse, mapLen);
+		return _FAIL;
+	}
+
+	_rtw_memset(map, 0xFF, mapLen);
+
+	ret = rtw_efuse_map_read(padapter, 0, mapLen, map);
+
+	if (ret == _FAIL)
+		goto exit;
+
+	_rtw_memcpy(efuse , map, mapLen);
+	_rtw_memcpy(efuse + addr, data, cnts);
+
+	if (padapter->registrypriv.boffefusemask == 0) {
+		for (i = 0; i < cnts; i++) {
+			if (padapter->registrypriv.bFileMaskEfuse == _TRUE) {
+				if (rtw_file_efuse_IsMasked(padapter, addr + i))	/*use file efuse mask. */
+					efuse[addr + i] = map[addr + i];
+			} else {
+				if (efuse_IsMasked(padapter, addr + i))
+					efuse[addr + i] = map[addr + i];
+			}
+			RTW_INFO("%s ,Write data[%d] = %x, map[%d]= %x\n", __func__, addr + i, efuse[ addr + i], addr + i, map[addr + i]);
+		}
+	}
+	/*Efuse_PowerSwitch(padapter, _TRUE, _TRUE);*/
+
+	chk_total_byte = 0;
+	idx = 0;
+	offset = (addr >> 3);
+
+	while (idx < cnts) {
+		word_en = 0xF;
+		j = (addr + idx) & 0x7;
+		for (i = j; i < PGPKT_DATA_SIZE && idx < cnts; i++, idx++) {
+			if (efuse[addr + idx] != map[addr + idx])
+				word_en &= ~BIT(i >> 1);
+		}
+
+		if (word_en != 0xF) {
+			chk_total_byte += Efuse_CalculateWordCnts(word_en) * 2;
+
+			if (offset >= EFUSE_MAX_SECTION_BASE) /* Over EFUSE_MAX_SECTION 16 for 2 ByteHeader */
+				chk_total_byte += 2;
+			else
+				chk_total_byte += 1;
+		}
+
+		offset++;
+	}
+
+	RTW_INFO("Total PG bytes Count = %d\n", chk_total_byte);
+	rtw_hal_get_hwreg(padapter, HW_VAR_EFUSE_BYTES, (u8 *)&startAddr);
+
+	if (startAddr == 0) {
+		startAddr = Efuse_GetCurrentSize(padapter, EFUSE_WIFI, _FALSE);
+		RTW_INFO("%s: Efuse_GetCurrentSize startAddr=%#X\n", __func__, startAddr);
+	}
+	RTW_DBG("%s: startAddr=%#X\n", __func__, startAddr);
+
+	if ((startAddr + chk_total_byte) >= efuse_max_available_len) {
+		RTW_INFO("%s: startAddr(0x%X) + PG data len %d >= efuse_max_available_len(0x%X)\n",
+			 __func__, startAddr, chk_total_byte, efuse_max_available_len);
+		ret = _FAIL;
+		goto exit;
+	}
+
+	efuse_PreUpdateAction(padapter, backupRegs);
+
+	idx = 0;
+	offset = (addr >> 3);
+	while (idx < cnts) {
+		word_en = 0xF;
+		j = (addr + idx) & 0x7;
+		_rtw_memcpy(newdata, &map[offset << 3], PGPKT_DATA_SIZE);
+		for (i = j; i < PGPKT_DATA_SIZE && idx < cnts; i++, idx++) {
+			if (efuse[addr + idx] != map[addr + idx]) {
+				word_en &= ~BIT(i >> 1);
+				newdata[i] = efuse[addr + idx];
+#ifdef CONFIG_RTL8723B
+				if (addr + idx == 0x8) {
+					if (IS_C_CUT(pHalData->version_id) || IS_B_CUT(pHalData->version_id)) {
+						if (pHalData->adjuseVoltageVal == 6) {
+							newdata[i] = map[addr + idx];
+							RTW_INFO(" %s ,\n adjuseVoltageVal = %d ,newdata[%d] = %x\n", __func__, pHalData->adjuseVoltageVal, i, newdata[i]);
+						}
+					}
+				}
+#endif
+			}
+		}
+
+		if (word_en != 0xF) {
+			ret = Efuse_PgPacketWrite(padapter, offset, word_en, newdata, _FALSE);
+			RTW_INFO("offset=%x\n", offset);
+			RTW_INFO("word_en=%x\n", word_en);
+
+			for (i = 0; i < PGPKT_DATA_SIZE; i++)
+				RTW_INFO("data=%x \t", newdata[i]);
+			if (ret == _FAIL)
+				break;
+		}
+
+		offset++;
+	}
+
+	/*Efuse_PowerSwitch(padapter, _TRUE, _FALSE);*/
+
+	efuse_PostUpdateAction(padapter, backupRegs);
+
+exit:
+
+	rtw_mfree(map, mapLen);
+	rtw_mfree(efuse, mapLen);
+
+	return ret;
+}
+
+
+u8 rtw_BT_efuse_map_write(PADAPTER padapter, u16 addr, u16 cnts, u8 *data)
+{
+#define RT_ASSERT_RET(expr)												\
+	if (!(expr)) {															\
+		printk("Assertion failed! %s at ......\n", #expr);							\
+		printk("      ......%s,%s, line=%d\n",__FILE__, __FUNCTION__, __LINE__);	\
+		return _FAIL;	\
+	}
+
+	u8	offset, word_en;
+	u8	*map;
+	u8	newdata[PGPKT_DATA_SIZE];
+	s32	i = 0, j = 0, idx;
+	u8	ret = _SUCCESS;
+	u16	mapLen = 0;
+
+	EFUSE_GetEfuseDefinition(padapter, EFUSE_BT, TYPE_EFUSE_MAP_LEN, (PVOID)&mapLen, _FALSE);
+
+	if ((addr + cnts) > mapLen)
+		return _FAIL;
+
+	RT_ASSERT_RET(PGPKT_DATA_SIZE == 8); /* have to be 8 byte alignment */
+	RT_ASSERT_RET((mapLen & 0x7) == 0); /* have to be PGPKT_DATA_SIZE alignment for memcpy */
+
+	map = rtw_zmalloc(mapLen);
+	if (map == NULL)
+		return _FAIL;
+
+	ret = rtw_BT_efuse_map_read(padapter, 0, mapLen, map);
+	if (ret == _FAIL)
+		goto exit;
+	RTW_INFO("OFFSET\tVALUE(hex)\n");
+	for (i = 0; i < 1024; i += 16) { /* set 512 because the iwpriv's extra size have limit 0x7FF */
+		RTW_INFO("0x%03x\t", i);
+		for (j = 0; j < 8; j++)
+			RTW_INFO("%02X ", map[i + j]);
+		RTW_INFO("\t");
+		for (; j < 16; j++)
+			RTW_INFO("%02X ", map[i + j]);
+		RTW_INFO("\n");
+	}
+	RTW_INFO("\n");
+	Efuse_PowerSwitch(padapter, _TRUE, _TRUE);
+
+	idx = 0;
+	offset = (addr >> 3);
+	while (idx < cnts) {
+		word_en = 0xF;
+		j = (addr + idx) & 0x7;
+		_rtw_memcpy(newdata, &map[offset << 3], PGPKT_DATA_SIZE);
+		for (i = j; i < PGPKT_DATA_SIZE && idx < cnts; i++, idx++) {
+			if (data[idx] != map[addr + idx]) {
+				word_en &= ~BIT(i >> 1);
+				newdata[i] = data[idx];
+			}
+		}
+
+		if (word_en != 0xF) {
+			RTW_INFO("offset=%x\n", offset);
+			RTW_INFO("word_en=%x\n", word_en);
+			RTW_INFO("%s: data=", __FUNCTION__);
+			for (i = 0; i < PGPKT_DATA_SIZE; i++)
+				RTW_INFO("0x%02X ", newdata[i]);
+			RTW_INFO("\n");
+			ret = Efuse_PgPacketWrite_BT(padapter, offset, word_en, newdata, _FALSE);
+			if (ret == _FAIL)
+				break;
+		}
+
+		offset++;
+	}
+
+	Efuse_PowerSwitch(padapter, _TRUE, _FALSE);
+
+exit:
+
+	rtw_mfree(map, mapLen);
+
+	return ret;
+}
+
+/*-----------------------------------------------------------------------------
+ * Function:	Efuse_ReadAllMap
+ *
+ * Overview:	Read All Efuse content
+ *
+ * Input:       NONE
+ *
+ * Output:      NONE
+ *
+ * Return:      NONE
+ *
+ * Revised History:
+ * When			Who		Remark
+ * 11/11/2008	MHC		Create Version 0.
+ *
+ *---------------------------------------------------------------------------*/
+VOID
+Efuse_ReadAllMap(
+	IN		PADAPTER	pAdapter,
+	IN		u8		efuseType,
+	IN OUT	u8		*Efuse,
+	IN		BOOLEAN		bPseudoTest);
+VOID
+Efuse_ReadAllMap(
+	IN		PADAPTER	pAdapter,
+	IN		u8		efuseType,
+	IN OUT	u8		*Efuse,
+	IN		BOOLEAN		bPseudoTest)
+{
+	u16	mapLen = 0;
+
+	Efuse_PowerSwitch(pAdapter, _FALSE, _TRUE);
+
+	EFUSE_GetEfuseDefinition(pAdapter, efuseType, TYPE_EFUSE_MAP_LEN, (PVOID)&mapLen, bPseudoTest);
+
+	efuse_ReadEFuse(pAdapter, efuseType, 0, mapLen, Efuse, bPseudoTest);
+
+	Efuse_PowerSwitch(pAdapter, _FALSE, _FALSE);
+}
+
+/*-----------------------------------------------------------------------------
+ * Function:	efuse_ShadowWrite1Byte
+ *			efuse_ShadowWrite2Byte
+ *			efuse_ShadowWrite4Byte
+ *
+ * Overview:	Write efuse modify map by one/two/four byte.
+ *
+ * Input:       NONE
+ *
+ * Output:      NONE
+ *
+ * Return:      NONE
+ *
+ * Revised History:
+ * When			Who		Remark
+ * 11/12/2008	MHC		Create Version 0.
+ *
+ *---------------------------------------------------------------------------*/
+#ifdef PLATFORM
+static VOID
+efuse_ShadowWrite1Byte(
+	IN	PADAPTER	pAdapter,
+	IN	u16		Offset,
+	IN	u8		Value);
+#endif /* PLATFORM */
+static VOID
+efuse_ShadowWrite1Byte(
+	IN	PADAPTER	pAdapter,
+	IN	u16		Offset,
+	IN	u8		Value)
+{
+	PHAL_DATA_TYPE pHalData = GET_HAL_DATA(pAdapter);
+
+	pHalData->efuse_eeprom_data[Offset] = Value;
+
+}	/* efuse_ShadowWrite1Byte */
+
+/* ---------------Write Two Bytes */
+static VOID
+efuse_ShadowWrite2Byte(
+	IN	PADAPTER	pAdapter,
+	IN	u16		Offset,
+	IN	u16		Value)
+{
+
+	PHAL_DATA_TYPE pHalData = GET_HAL_DATA(pAdapter);
+
+
+	pHalData->efuse_eeprom_data[Offset] = Value & 0x00FF;
+	pHalData->efuse_eeprom_data[Offset + 1] = Value >> 8;
+
+}	/* efuse_ShadowWrite1Byte */
+
+/* ---------------Write Four Bytes */
+static VOID
+efuse_ShadowWrite4Byte(
+	IN	PADAPTER	pAdapter,
+	IN	u16		Offset,
+	IN	u32		Value)
+{
+	PHAL_DATA_TYPE pHalData = GET_HAL_DATA(pAdapter);
+
+	pHalData->efuse_eeprom_data[Offset] = (u8)(Value & 0x000000FF);
+	pHalData->efuse_eeprom_data[Offset + 1] = (u8)((Value >> 8) & 0x0000FF);
+	pHalData->efuse_eeprom_data[Offset + 2] = (u8)((Value >> 16) & 0x00FF);
+	pHalData->efuse_eeprom_data[Offset + 3] = (u8)((Value >> 24) & 0xFF);
+
+}	/* efuse_ShadowWrite1Byte */
+
+
+/*-----------------------------------------------------------------------------
+ * Function:	EFUSE_ShadowWrite
+ *
+ * Overview:	Write efuse modify map for later update operation to use!!!!!
+ *
+ * Input:       NONE
+ *
+ * Output:      NONE
+ *
+ * Return:      NONE
+ *
+ * Revised History:
+ * When			Who		Remark
+ * 11/12/2008	MHC		Create Version 0.
+ *
+ *---------------------------------------------------------------------------*/
+VOID
+EFUSE_ShadowWrite(
+	IN	PADAPTER	pAdapter,
+	IN	u8		Type,
+	IN	u16		Offset,
+	IN OUT	u32		Value);
+VOID
+EFUSE_ShadowWrite(
+	IN	PADAPTER	pAdapter,
+	IN	u8		Type,
+	IN	u16		Offset,
+	IN OUT	u32		Value)
+{
+#if (MP_DRIVER == 0)
+	return;
+#endif
+	if (pAdapter->registrypriv.mp_mode == 0)
+		return;
+
+
+	if (Type == 1)
+		efuse_ShadowWrite1Byte(pAdapter, Offset, (u8)Value);
+	else if (Type == 2)
+		efuse_ShadowWrite2Byte(pAdapter, Offset, (u16)Value);
+	else if (Type == 4)
+		efuse_ShadowWrite4Byte(pAdapter, Offset, (u32)Value);
+
+}	/* EFUSE_ShadowWrite */
+
+VOID
+Efuse_InitSomeVar(
+	IN		PADAPTER	pAdapter
+);
+VOID
+Efuse_InitSomeVar(
+	IN		PADAPTER	pAdapter
+)
+{
+	u8 i;
+
+	_rtw_memset((PVOID)&fakeEfuseContent[0], 0xff, EFUSE_MAX_HW_SIZE);
+	_rtw_memset((PVOID)&fakeEfuseInitMap[0], 0xff, EFUSE_MAX_MAP_LEN);
+	_rtw_memset((PVOID)&fakeEfuseModifiedMap[0], 0xff, EFUSE_MAX_MAP_LEN);
+
+	for (i = 0; i < EFUSE_MAX_BT_BANK; i++)
+		_rtw_memset((PVOID)&BTEfuseContent[i][0], EFUSE_MAX_HW_SIZE, 0xff);
+	_rtw_memset((PVOID)&BTEfuseInitMap[0], 0xff, EFUSE_BT_MAX_MAP_LEN);
+	_rtw_memset((PVOID)&BTEfuseModifiedMap[0], 0xff, EFUSE_BT_MAX_MAP_LEN);
+
+	for (i = 0; i < EFUSE_MAX_BT_BANK; i++)
+		_rtw_memset((PVOID)&fakeBTEfuseContent[i][0], 0xff, EFUSE_MAX_HW_SIZE);
+	_rtw_memset((PVOID)&fakeBTEfuseInitMap[0], 0xff, EFUSE_BT_MAX_MAP_LEN);
+	_rtw_memset((PVOID)&fakeBTEfuseModifiedMap[0], 0xff, EFUSE_BT_MAX_MAP_LEN);
+}
+#endif /* !RTW_HALMAC */
+/*-----------------------------------------------------------------------------
+ * Function:	efuse_ShadowRead1Byte
+ *			efuse_ShadowRead2Byte
+ *			efuse_ShadowRead4Byte
+ *
+ * Overview:	Read from efuse init map by one/two/four bytes !!!!!
+ *
+ * Input:       NONE
+ *
+ * Output:      NONE
+ *
+ * Return:      NONE
+ *
+ * Revised History:
+ * When			Who		Remark
+ * 11/12/2008	MHC		Create Version 0.
+ *
+ *---------------------------------------------------------------------------*/
+static VOID
+efuse_ShadowRead1Byte(
+	IN	PADAPTER	pAdapter,
+	IN	u16		Offset,
+	IN OUT	u8		*Value)
+{
+	PHAL_DATA_TYPE pHalData = GET_HAL_DATA(pAdapter);
+
+	*Value = pHalData->efuse_eeprom_data[Offset];
+
+}	/* EFUSE_ShadowRead1Byte */
+
+/* ---------------Read Two Bytes */
+static VOID
+efuse_ShadowRead2Byte(
+	IN	PADAPTER	pAdapter,
+	IN	u16		Offset,
+	IN OUT	u16		*Value)
+{
+	PHAL_DATA_TYPE pHalData = GET_HAL_DATA(pAdapter);
+
+	*Value = pHalData->efuse_eeprom_data[Offset];
+	*Value |= pHalData->efuse_eeprom_data[Offset + 1] << 8;
+
+}	/* EFUSE_ShadowRead2Byte */
+
+/* ---------------Read Four Bytes */
+static VOID
+efuse_ShadowRead4Byte(
+	IN	PADAPTER	pAdapter,
+	IN	u16		Offset,
+	IN OUT	u32		*Value)
+{
+	PHAL_DATA_TYPE pHalData = GET_HAL_DATA(pAdapter);
+
+	*Value = pHalData->efuse_eeprom_data[Offset];
+	*Value |= pHalData->efuse_eeprom_data[Offset + 1] << 8;
+	*Value |= pHalData->efuse_eeprom_data[Offset + 2] << 16;
+	*Value |= pHalData->efuse_eeprom_data[Offset + 3] << 24;
+
+}	/* efuse_ShadowRead4Byte */
+
+/*-----------------------------------------------------------------------------
+ * Function:	EFUSE_ShadowRead
+ *
+ * Overview:	Read from pHalData->efuse_eeprom_data
+ *---------------------------------------------------------------------------*/
+void
+EFUSE_ShadowRead(
+	IN		PADAPTER	pAdapter,
+	IN		u8		Type,
+	IN		u16		Offset,
+	IN OUT	u32		*Value)
+{
+	if (Type == 1)
+		efuse_ShadowRead1Byte(pAdapter, Offset, (u8 *)Value);
+	else if (Type == 2)
+		efuse_ShadowRead2Byte(pAdapter, Offset, (u16 *)Value);
+	else if (Type == 4)
+		efuse_ShadowRead4Byte(pAdapter, Offset, (u32 *)Value);
+
+}	/* EFUSE_ShadowRead */
+
+/*  11/16/2008 MH Add description. Get current efuse area enabled word!!. */
+u8
+Efuse_CalculateWordCnts(IN u8	word_en)
+{
+	u8 word_cnts = 0;
+	if (!(word_en & BIT(0)))
+		word_cnts++; /* 0 : write enable */
+	if (!(word_en & BIT(1)))
+		word_cnts++;
+	if (!(word_en & BIT(2)))
+		word_cnts++;
+	if (!(word_en & BIT(3)))
+		word_cnts++;
+	return word_cnts;
+}
+
+/*-----------------------------------------------------------------------------
+ * Function:	efuse_WordEnableDataRead
+ *
+ * Overview:	Read allowed word in current efuse section data.
+ *
+ * Input:       NONE
+ *
+ * Output:      NONE
+ *
+ * Return:      NONE
+ *
+ * Revised History:
+ * When			Who		Remark
+ * 11/16/2008	MHC		Create Version 0.
+ * 11/21/2008	MHC		Fix Write bug when we only enable late word.
+ *
+ *---------------------------------------------------------------------------*/
+void
+efuse_WordEnableDataRead(IN	u8	word_en,
+			 IN	u8	*sourdata,
+			 IN	u8	*targetdata)
+{
+	if (!(word_en & BIT(0))) {
+		targetdata[0] = sourdata[0];
+		targetdata[1] = sourdata[1];
+	}
+	if (!(word_en & BIT(1))) {
+		targetdata[2] = sourdata[2];
+		targetdata[3] = sourdata[3];
+	}
+	if (!(word_en & BIT(2))) {
+		targetdata[4] = sourdata[4];
+		targetdata[5] = sourdata[5];
+	}
+	if (!(word_en & BIT(3))) {
+		targetdata[6] = sourdata[6];
+		targetdata[7] = sourdata[7];
+	}
+}
+
+/*-----------------------------------------------------------------------------
+ * Function:	EFUSE_ShadowMapUpdate
+ *
+ * Overview:	Transfer current EFUSE content to shadow init and modify map.
+ *
+ * Input:       NONE
+ *
+ * Output:      NONE
+ *
+ * Return:      NONE
+ *
+ * Revised History:
+ * When			Who		Remark
+ * 11/13/2008	MHC		Create Version 0.
+ *
+ *---------------------------------------------------------------------------*/
+void EFUSE_ShadowMapUpdate(
+	IN PADAPTER	pAdapter,
+	IN u8		efuseType,
+	IN BOOLEAN	bPseudoTest)
+{
+	PHAL_DATA_TYPE pHalData = GET_HAL_DATA(pAdapter);
+	u16	mapLen = 0;
+#ifdef RTW_HALMAC
+	u8 *efuse_map = NULL;
+	int err;
+
+
+	mapLen = EEPROM_MAX_SIZE;
+	efuse_map = pHalData->efuse_eeprom_data;
+	/* efuse default content is 0xFF */
+	_rtw_memset(efuse_map, 0xFF, EEPROM_MAX_SIZE);
+
+	EFUSE_GetEfuseDefinition(pAdapter, efuseType, TYPE_EFUSE_MAP_LEN, (PVOID)&mapLen, bPseudoTest);
+	if (!mapLen) {
+		RTW_WARN("%s: <ERROR> fail to get efuse size!\n", __FUNCTION__);
+		mapLen = EEPROM_MAX_SIZE;
+	}
+	if (mapLen > EEPROM_MAX_SIZE) {
+		RTW_WARN("%s: <ERROR> size of efuse data(%d) is large than expected(%d)!\n",
+			 __FUNCTION__, mapLen, EEPROM_MAX_SIZE);
+		mapLen = EEPROM_MAX_SIZE;
+	}
+
+	if (pHalData->bautoload_fail_flag == _FALSE) {
+		err = rtw_halmac_read_logical_efuse_map(adapter_to_dvobj(pAdapter), efuse_map, mapLen, NULL, 0);
+		if (err)
+			RTW_ERR("%s: <ERROR> fail to get efuse map!\n", __FUNCTION__);
+	}
+#else /* !RTW_HALMAC */
+	EFUSE_GetEfuseDefinition(pAdapter, efuseType, TYPE_EFUSE_MAP_LEN, (PVOID)&mapLen, bPseudoTest);
+
+	if (pHalData->bautoload_fail_flag == _TRUE)
+		_rtw_memset(pHalData->efuse_eeprom_data, 0xFF, mapLen);
+	else {
+#ifdef CONFIG_ADAPTOR_INFO_CACHING_FILE
+		if (_SUCCESS != retriveAdaptorInfoFile(pAdapter->registrypriv.adaptor_info_caching_file_path, pHalData->efuse_eeprom_data)) {
+#endif
+
+			Efuse_ReadAllMap(pAdapter, efuseType, pHalData->efuse_eeprom_data, bPseudoTest);
+
+#ifdef CONFIG_ADAPTOR_INFO_CACHING_FILE
+			storeAdaptorInfoFile(pAdapter->registrypriv.adaptor_info_caching_file_path, pHalData->efuse_eeprom_data);
+		}
+#endif
+	}
+
+	/* PlatformMoveMemory((PVOID)&pHalData->EfuseMap[EFUSE_MODIFY_MAP][0], */
+	/* (PVOID)&pHalData->EfuseMap[EFUSE_INIT_MAP][0], mapLen); */
+#endif /* !RTW_HALMAC */
+
+	rtw_mask_map_read(pAdapter, 0x00, mapLen, pHalData->efuse_eeprom_data);
+
+	rtw_dump_cur_efuse(pAdapter);
+} /* EFUSE_ShadowMapUpdate */
+
+const u8 _mac_hidden_max_bw_to_hal_bw_cap[MAC_HIDDEN_MAX_BW_NUM] = {
+	0,
+	0,
+	(BW_CAP_160M | BW_CAP_80M | BW_CAP_40M | BW_CAP_20M | BW_CAP_10M | BW_CAP_5M),
+	(BW_CAP_5M),
+	(BW_CAP_10M | BW_CAP_5M),
+	(BW_CAP_20M | BW_CAP_10M | BW_CAP_5M),
+	(BW_CAP_40M | BW_CAP_20M | BW_CAP_10M | BW_CAP_5M),
+	(BW_CAP_80M | BW_CAP_40M | BW_CAP_20M | BW_CAP_10M | BW_CAP_5M),
+};
+
+const u8 _mac_hidden_proto_to_hal_proto_cap[MAC_HIDDEN_PROTOCOL_NUM] = {
+	0,
+	0,
+	(PROTO_CAP_11N | PROTO_CAP_11G | PROTO_CAP_11B),
+	(PROTO_CAP_11AC | PROTO_CAP_11N | PROTO_CAP_11G | PROTO_CAP_11B),
+};
+
+u8 mac_hidden_wl_func_to_hal_wl_func(u8 func)
+{
+	u8 wl_func = 0;
+
+	if (func & BIT0)
+		wl_func |= WL_FUNC_MIRACAST;
+	if (func & BIT1)
+		wl_func |= WL_FUNC_P2P;
+	if (func & BIT2)
+		wl_func |= WL_FUNC_TDLS;
+	if (func & BIT3)
+		wl_func |= WL_FUNC_FTM;
+
+	return wl_func;
+}
+
+#ifdef PLATFORM_LINUX
+#ifdef CONFIG_ADAPTOR_INFO_CACHING_FILE
+/* #include <rtw_eeprom.h> */
+
+int isAdaptorInfoFileValid(void)
+{
+	return _TRUE;
+}
+
+int storeAdaptorInfoFile(char *path, u8 *efuse_data)
+{
+	int ret = _SUCCESS;
+
+	if (path && efuse_data) {
+		ret = rtw_store_to_file(path, efuse_data, EEPROM_MAX_SIZE_512);
+		if (ret == EEPROM_MAX_SIZE)
+			ret = _SUCCESS;
+		else
+			ret = _FAIL;
+	} else {
+		RTW_INFO("%s NULL pointer\n", __FUNCTION__);
+		ret =  _FAIL;
+	}
+	return ret;
+}
+
+int retriveAdaptorInfoFile(char *path, u8 *efuse_data)
+{
+	int ret = _SUCCESS;
+	mm_segment_t oldfs;
+	struct file *fp;
+
+	if (path && efuse_data) {
+
+		ret = rtw_retrieve_from_file(path, efuse_data, EEPROM_MAX_SIZE);
+
+		if (ret == EEPROM_MAX_SIZE)
+			ret = _SUCCESS;
+		else
+			ret = _FAIL;
+
+#if 0
+		if (isAdaptorInfoFileValid())
+			return 0;
+		else
+			return _FAIL;
+#endif
+
+	} else {
+		RTW_INFO("%s NULL pointer\n", __FUNCTION__);
+		ret = _FAIL;
+	}
+	return ret;
+}
+#endif /* CONFIG_ADAPTOR_INFO_CACHING_FILE */
+
+u8 rtw_efuse_file_read(PADAPTER padapter, u8 *filepatch, u8 *buf, u32 len)
+{
+	char *ptmpbuf = NULL, *ptr;
+	u8 val8;
+	u32 count, i, j;
+	int err;
+	u32 bufsize = 4096;
+
+	ptmpbuf = rtw_zmalloc(bufsize);
+	if (ptmpbuf == NULL)
+		return _FALSE;
+
+	count = rtw_retrieve_from_file(filepatch, ptmpbuf, bufsize);
+	if (count <= 90) {
+		rtw_mfree(ptmpbuf, bufsize);
+		RTW_ERR("%s, filepatch %s, size=%d, FAIL!!\n", __FUNCTION__, filepatch, count);
+		return _FALSE;
+	}
+
+	i = 0;
+	j = 0;
+	ptr = ptmpbuf;
+	while ((j < len) && (i < count)) {
+		if (ptmpbuf[i] == '\0')
+			break;
+	
+		ptr = strpbrk(&ptmpbuf[i], " \t\n\r");
+		if (ptr) {
+			if (ptr == &ptmpbuf[i]) {
+				i++;
+				continue;
+			}
+
+			/* Add string terminating null */
+			*ptr = 0;
+		} else {
+			ptr = &ptmpbuf[count-1];
+		}
+
+		err = sscanf(&ptmpbuf[i], "%hhx", &val8);
+		if (err != 1) {
+			RTW_WARN("Something wrong to parse efuse file, string=%s\n", &ptmpbuf[i]);
+		} else {
+			buf[j] = val8;
+			RTW_DBG("i=%d, j=%d, 0x%02x\n", i, j, buf[j]);
+			j++;
+		}
+
+		i = ptr - ptmpbuf + 1;
+	}
+
+	rtw_mfree(ptmpbuf, bufsize);
+	RTW_INFO("%s, filepatch %s, size=%d, done\n", __FUNCTION__, filepatch, count);
+	return _TRUE;
+}
+
+#ifdef CONFIG_EFUSE_CONFIG_FILE
+u32 rtw_read_efuse_from_file(const char *path, u8 *buf, int map_size)
+{
+	u32 i;
+	u8 c;
+	u8 temp[3];
+	u8 temp_i;
+	u8 end = _FALSE;
+	u32 ret = _FAIL;
+
+	u8 *file_data = NULL;
+	u32 file_size, read_size, pos = 0;
+	u8 *map = NULL;
+
+	if (rtw_is_file_readable_with_size(path, &file_size) != _TRUE) {
+		RTW_PRINT("%s %s is not readable\n", __func__, path);
+		goto exit;
+	}
+
+	file_data = rtw_vmalloc(file_size);
+	if (!file_data) {
+		RTW_ERR("%s rtw_vmalloc(%d) fail\n", __func__, file_size);
+		goto exit;
+	}
+
+	read_size = rtw_retrieve_from_file(path, file_data, file_size);
+	if (read_size == 0) {
+		RTW_ERR("%s read from %s fail\n", __func__, path);
+		goto exit;
+	}
+
+	map = rtw_vmalloc(map_size);
+	if (!map) {
+		RTW_ERR("%s rtw_vmalloc(%d) fail\n", __func__, map_size);
+		goto exit;
+	}
+	_rtw_memset(map, 0xff, map_size);
+
+	temp[2] = 0; /* end of string '\0' */
+
+	for (i = 0 ; i < map_size ; i++) {
+		temp_i = 0;
+
+		while (1) {
+			if (pos >= read_size) {
+				end = _TRUE;
+				break;
+			}
+			c = file_data[pos++];
+
+			/* bypass spece or eol or null before first hex digit */
+			if (temp_i == 0 && (is_eol(c) == _TRUE || is_space(c) == _TRUE || is_null(c) == _TRUE))
+				continue;
+
+			if (IsHexDigit(c) == _FALSE) {
+				RTW_ERR("%s invalid 8-bit hex format for offset:0x%03x\n", __func__, i);
+				goto exit;
+			}
+
+			temp[temp_i++] = c;
+
+			if (temp_i == 2) {
+				/* parse value */
+				if (sscanf(temp, "%hhx", &map[i]) != 1) {
+					RTW_ERR("%s sscanf fail for offset:0x%03x\n", __func__, i);
+					goto exit;
+				}
+				break;
+			}
+		}
+
+		if (end == _TRUE) {
+			if (temp_i != 0) {
+				RTW_ERR("%s incomplete 8-bit hex format for offset:0x%03x\n", __func__, i);
+				goto exit;
+			}
+			break;
+		}
+	}
+
+	RTW_PRINT("efuse file:%s, 0x%03x byte content read\n", path, i);
+
+	_rtw_memcpy(buf, map, map_size);
+
+	ret = _SUCCESS;
+
+exit:
+	if (file_data)
+		rtw_vmfree(file_data, file_size);
+	if (map)
+		rtw_vmfree(map, map_size);
+
+	return ret;
+}
+
+u32 rtw_read_macaddr_from_file(const char *path, u8 *buf)
+{
+	u32 i;
+	u8 temp[3];
+	u32 ret = _FAIL;
+
+	u8 file_data[17];
+	u32 read_size, pos = 0;
+	u8 addr[ETH_ALEN];
+
+	if (rtw_is_file_readable(path) != _TRUE) {
+		RTW_PRINT("%s %s is not readable\n", __func__, path);
+		goto exit;
+	}
+
+	read_size = rtw_retrieve_from_file(path, file_data, 17);
+	if (read_size != 17) {
+		RTW_ERR("%s read from %s fail\n", __func__, path);
+		goto exit;
+	}
+
+	temp[2] = 0; /* end of string '\0' */
+
+	for (i = 0 ; i < ETH_ALEN ; i++) {
+		if (IsHexDigit(file_data[i * 3]) == _FALSE || IsHexDigit(file_data[i * 3 + 1]) == _FALSE) {
+			RTW_ERR("%s invalid 8-bit hex format for address offset:%u\n", __func__, i);
+			goto exit;
+		}
+
+		if (i < ETH_ALEN - 1 && file_data[i * 3 + 2] != ':') {
+			RTW_ERR("%s invalid separator after address offset:%u\n", __func__, i);
+			goto exit;
+		}
+
+		temp[0] = file_data[i * 3];
+		temp[1] = file_data[i * 3 + 1];
+		if (sscanf(temp, "%hhx", &addr[i]) != 1) {
+			RTW_ERR("%s sscanf fail for address offset:0x%03x\n", __func__, i);
+			goto exit;
+		}
+	}
+
+	_rtw_memcpy(buf, addr, ETH_ALEN);
+
+	RTW_PRINT("wifi_mac file: %s\n", path);
+#ifdef CONFIG_RTW_DEBUG
+	RTW_INFO(MAC_FMT"\n", MAC_ARG(buf));
+#endif
+
+	ret = _SUCCESS;
+
+exit:
+	return ret;
+}
+#endif /* CONFIG_EFUSE_CONFIG_FILE */
+
+#endif /* PLATFORM_LINUX */
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/core/mesh/rtw_mesh.c linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/core/mesh/rtw_mesh.c
--- linux-5.6.3/3rdparty/rtl8821ce/core/mesh/rtw_mesh.c	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/core/mesh/rtw_mesh.c	2020-04-10 16:35:06.769657873 +0300
@@ -0,0 +1,4097 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#define _RTW_MESH_C_
+
+#ifdef CONFIG_RTW_MESH
+#include <drv_types.h>
+
+const char *_rtw_mesh_plink_str[] = {
+	"UNKNOWN",
+	"LISTEN",
+	"OPN_SNT",
+	"OPN_RCVD",
+	"CNF_RCVD",
+	"ESTAB",
+	"HOLDING",
+	"BLOCKED",
+};
+
+const char *_rtw_mesh_ps_str[] = {
+	"UNKNOWN",
+	"ACTIVE",
+	"LSLEEP",
+	"DSLEEP",
+};
+
+const char *_action_self_protected_str[] = {
+	"ACT_SELF_PROTECTED_RSVD",
+	"MESH_OPEN",
+	"MESH_CONF",
+	"MESH_CLOSE",
+	"MESH_GK_INFORM",
+	"MESH_GK_ACK",
+};
+
+inline u8 *rtw_set_ie_mesh_id(u8 *buf, u32 *buf_len, const char *mesh_id, u8 id_len)
+{
+	return rtw_set_ie(buf, WLAN_EID_MESH_ID, id_len, mesh_id, buf_len);
+}
+
+inline u8 *rtw_set_ie_mesh_config(u8 *buf, u32 *buf_len
+	, u8 path_sel_proto, u8 path_sel_metric, u8 congest_ctl_mode, u8 sync_method, u8 auth_proto
+	, u8 num_of_peerings, bool cto_mgate, bool cto_as
+	, bool accept_peerings, bool mcca_sup, bool mcca_en, bool forwarding
+	, bool mbca_en, bool tbtt_adj, bool ps_level)
+{
+
+	u8 conf[7] = {0};
+
+	SET_MESH_CONF_ELE_PATH_SEL_PROTO_ID(conf, path_sel_proto);
+	SET_MESH_CONF_ELE_PATH_SEL_METRIC_ID(conf, path_sel_metric);
+	SET_MESH_CONF_ELE_CONGEST_CTRL_MODE_ID(conf, congest_ctl_mode);
+	SET_MESH_CONF_ELE_SYNC_METHOD_ID(conf, sync_method);
+	SET_MESH_CONF_ELE_AUTH_PROTO_ID(conf, auth_proto);
+
+	SET_MESH_CONF_ELE_CTO_MGATE(conf, cto_mgate);
+	SET_MESH_CONF_ELE_NUM_OF_PEERINGS(conf, num_of_peerings);
+	SET_MESH_CONF_ELE_CTO_AS(conf, cto_as);
+
+	SET_MESH_CONF_ELE_ACCEPT_PEERINGS(conf, accept_peerings);
+	SET_MESH_CONF_ELE_MCCA_SUP(conf, mcca_sup);
+	SET_MESH_CONF_ELE_MCCA_EN(conf, mcca_en);
+	SET_MESH_CONF_ELE_FORWARDING(conf, forwarding);
+	SET_MESH_CONF_ELE_MBCA_EN(conf, mbca_en);
+	SET_MESH_CONF_ELE_TBTT_ADJ(conf, tbtt_adj);
+	SET_MESH_CONF_ELE_PS_LEVEL(conf, ps_level);
+
+	return rtw_set_ie(buf, WLAN_EID_MESH_CONFIG, 7, conf, buf_len);
+}
+
+inline u8 *rtw_set_ie_mpm(u8 *buf, u32 *buf_len
+	, u8 proto_id, u16 llid, u16 *plid, u16 *reason, u8 *chosen_pmk)
+{
+	u8 data[24] = {0};
+	u8 *pos = data;
+
+	RTW_PUT_LE16(pos, proto_id);
+	pos += 2;
+
+	RTW_PUT_LE16(pos, llid);
+	pos += 2;
+
+	if (plid) {
+		RTW_PUT_LE16(pos, *plid);
+		pos += 2;
+	}
+
+	if (reason) {
+		RTW_PUT_LE16(pos, *reason);
+		pos += 2;
+	}
+
+	if (chosen_pmk) {
+		_rtw_memcpy(pos, chosen_pmk, 16);
+		pos += 16;
+	}
+
+	return rtw_set_ie(buf, WLAN_EID_MPM, pos - data, data, buf_len);
+}
+
+bool rtw_bss_is_forwarding(WLAN_BSSID_EX *bss)
+{
+	u8 *ie;
+	int ie_len;
+	bool ret = 0;
+
+	ie = rtw_get_ie(BSS_EX_TLV_IES(bss), WLAN_EID_MESH_CONFIG, &ie_len,
+			BSS_EX_TLV_IES_LEN(bss));
+	if (!ie || ie_len != 7)
+		goto exit;
+
+	ret = GET_MESH_CONF_ELE_FORWARDING(ie + 2);
+
+exit:
+	return ret;
+}
+
+bool rtw_bss_is_cto_mgate(WLAN_BSSID_EX *bss)
+{
+	u8 *ie;
+	int ie_len;
+	bool ret = 0;
+
+	ie = rtw_get_ie(BSS_EX_TLV_IES(bss), WLAN_EID_MESH_CONFIG, &ie_len,
+			BSS_EX_TLV_IES_LEN(bss));
+	if (!ie || ie_len != 7)
+		goto exit;
+
+	ret = GET_MESH_CONF_ELE_CTO_MGATE(ie + 2);
+
+exit:
+	return ret;
+}
+
+int rtw_bss_is_same_mbss(WLAN_BSSID_EX *a, WLAN_BSSID_EX *b)
+{
+	int ret = 0;
+	u8 *a_mconf_ie, *b_mconf_ie;
+	sint a_mconf_ie_len, b_mconf_ie_len;
+
+	if (a->InfrastructureMode != Ndis802_11_mesh)
+		goto exit;
+	a_mconf_ie = rtw_get_ie(BSS_EX_TLV_IES(a), WLAN_EID_MESH_CONFIG, &a_mconf_ie_len, BSS_EX_TLV_IES_LEN(a));
+	if (!a_mconf_ie || a_mconf_ie_len != 7)
+		goto exit;
+	if (b->InfrastructureMode != Ndis802_11_mesh)
+		goto exit;
+	b_mconf_ie = rtw_get_ie(BSS_EX_TLV_IES(b), WLAN_EID_MESH_CONFIG, &b_mconf_ie_len, BSS_EX_TLV_IES_LEN(b));
+	if (!b_mconf_ie || b_mconf_ie_len != 7)
+		goto exit;
+
+	if (a->mesh_id.SsidLength != b->mesh_id.SsidLength
+		|| _rtw_memcmp(a->mesh_id.Ssid, b->mesh_id.Ssid, a->mesh_id.SsidLength) == _FALSE)
+		goto exit;
+
+	if (_rtw_memcmp(a_mconf_ie + 2, b_mconf_ie + 2, 5) == _FALSE)
+		goto exit;
+
+	ret = 1;
+
+exit:
+	return ret;
+}
+
+int rtw_bss_is_candidate_mesh_peer(WLAN_BSSID_EX *self, WLAN_BSSID_EX *target, u8 ch, u8 add_peer)
+{
+	int ret = 0;
+	u8 *mconf_ie;
+	sint mconf_ie_len;
+	int i, j;
+
+	if (!rtw_bss_is_same_mbss(self, target))
+		goto exit;
+
+	if (ch && self->Configuration.DSConfig != target->Configuration.DSConfig)
+		goto exit;
+
+	if (add_peer) {
+		/* Accept additional mesh peerings */
+		mconf_ie = rtw_get_ie(BSS_EX_TLV_IES(target), WLAN_EID_MESH_CONFIG, &mconf_ie_len, BSS_EX_TLV_IES_LEN(target));
+		if (!mconf_ie || mconf_ie_len != 7)
+			goto exit;
+		if (GET_MESH_CONF_ELE_ACCEPT_PEERINGS(mconf_ie + 2) == 0)
+			goto exit;
+	}
+
+	/* BSSBasicRateSet */
+	for (i = 0; i < NDIS_802_11_LENGTH_RATES_EX; i++) {
+		if (target->SupportedRates[i] == 0)
+			break;	
+		if (target->SupportedRates[i] & 0x80) {
+			u8 match = 0;
+
+			if (!ch) {
+				/* off-channel, check target with our hardcode capability */
+				if (target->Configuration.DSConfig > 14)
+					match = rtw_is_basic_rate_ofdm(target->SupportedRates[i]);
+				else
+					match = rtw_is_basic_rate_mix(target->SupportedRates[i]);
+			} else { 
+				for (j = 0; j < NDIS_802_11_LENGTH_RATES_EX; j++) {
+					if (self->SupportedRates[j] == 0)
+						break;
+					if (self->SupportedRates[j] == target->SupportedRates[i]) {
+						match = 1;
+						break;
+					}
+				}
+			}
+			if (!match)
+				goto exit;
+		}
+	}
+
+
+	/* BSSBasicMCSSet */
+
+	/* 802.1X connected to AS ? */
+
+	ret = 1;
+
+exit:
+	return ret;
+}
+
+void rtw_mesh_bss_peering_status(WLAN_BSSID_EX *bss, u8 *nop, u8 *accept)
+{
+	u8 *ie;
+	int ie_len;
+
+	if (nop)
+		*nop = 0;
+	if (accept)
+		*accept = 0;
+
+	ie = rtw_get_ie(BSS_EX_TLV_IES(bss), WLAN_EID_MESH_CONFIG, &ie_len,
+			BSS_EX_TLV_IES_LEN(bss));
+	if (!ie || ie_len != 7)
+		goto exit;
+
+	if (nop)
+		*nop = GET_MESH_CONF_ELE_NUM_OF_PEERINGS(ie + 2);
+	if (accept)
+		*accept = GET_MESH_CONF_ELE_ACCEPT_PEERINGS(ie + 2);
+
+exit:
+	return;
+}
+
+#if CONFIG_RTW_MESH_ACNODE_PREVENT
+void rtw_mesh_update_scanned_acnode_status(_adapter *adapter, struct wlan_network *scanned)
+{
+	bool acnode;
+	u8 nop, accept;
+
+	rtw_mesh_bss_peering_status(&scanned->network, &nop, &accept);
+
+	acnode = !nop && accept;
+
+	if (acnode && scanned->acnode_stime == 0) {
+		scanned->acnode_stime = rtw_get_current_time();
+		if (scanned->acnode_stime == 0)
+			scanned->acnode_stime++;
+	} else if (!acnode) {
+		scanned->acnode_stime = 0;
+		scanned->acnode_notify_etime = 0;
+	}
+}
+
+bool rtw_mesh_scanned_is_acnode_confirmed(_adapter *adapter, struct wlan_network *scanned)
+{
+	return scanned->acnode_stime
+			&& rtw_get_passing_time_ms(scanned->acnode_stime)
+				> adapter->mesh_cfg.peer_sel_policy.acnode_conf_timeout_ms;
+}
+
+static bool rtw_mesh_scanned_is_acnode_allow_notify(_adapter *adapter, struct wlan_network *scanned)
+{
+	return scanned->acnode_notify_etime
+			&& rtw_time_after(scanned->acnode_notify_etime, rtw_get_current_time());
+}
+
+bool rtw_mesh_acnode_prevent_allow_sacrifice(_adapter *adapter)
+{
+	struct rtw_mesh_cfg *mcfg = &adapter->mesh_cfg;
+	struct sta_priv *stapriv = &adapter->stapriv;
+	bool allow = 0;
+
+	if (!mcfg->peer_sel_policy.acnode_prevent
+		|| mcfg->max_peer_links <= 1
+		|| stapriv->asoc_list_cnt < mcfg->max_peer_links)
+		goto exit;
+
+#if CONFIG_RTW_MESH_CTO_MGATE_BLACKLIST
+	if (rtw_mesh_cto_mgate_required(adapter))
+		goto exit;
+#endif
+
+	allow = 1;
+
+exit:
+	return allow;
+}
+
+static bool rtw_mesh_acnode_candidate_exist(_adapter *adapter)
+{
+	struct rtw_mesh_cfg *mcfg = &adapter->mesh_cfg;
+	struct sta_priv *stapriv = &adapter->stapriv;
+	struct mlme_priv *mlme = &adapter->mlmepriv;
+	_queue *queue = &(mlme->scanned_queue);
+	_list *head, *list;
+	_irqL irqL;
+	struct wlan_network *scanned = NULL;
+	struct sta_info *sta = NULL;
+	bool need = 0;
+
+	_enter_critical_bh(&(mlme->scanned_queue.lock), &irqL);
+
+	head = get_list_head(queue);
+	list = get_next(head);
+	while (!rtw_end_of_queue_search(head, list)) {
+		scanned = LIST_CONTAINOR(list, struct wlan_network, list);
+		list = get_next(list);
+
+		if (rtw_get_passing_time_ms(scanned->last_scanned) < mcfg->peer_sel_policy.scanr_exp_ms
+			&& rtw_mesh_scanned_is_acnode_confirmed(adapter, scanned)
+			&& (!mcfg->rssi_threshold || mcfg->rssi_threshold <= scanned->network.Rssi)
+			#if CONFIG_RTW_MACADDR_ACL
+			&& rtw_access_ctrl(adapter, scanned->network.MacAddress) == _TRUE
+			#endif
+			&& rtw_bss_is_candidate_mesh_peer(&mlme->cur_network.network, &scanned->network, 1, 1)
+			#if CONFIG_RTW_MESH_PEER_BLACKLIST
+			&& !rtw_mesh_peer_blacklist_search(adapter, scanned->network.MacAddress)
+			#endif
+			#if CONFIG_RTW_MESH_CTO_MGATE_BLACKLIST
+			&& rtw_mesh_cto_mgate_network_filter(adapter, scanned)
+			#endif
+		) {
+			need = 1;
+			break;
+		}
+	}
+
+	_exit_critical_bh(&(mlme->scanned_queue.lock), &irqL);
+
+exit:
+	return need;
+}
+
+static int rtw_mesh_acnode_prevent_sacrifice_chk(_adapter *adapter, struct sta_info **sac, struct sta_info *com)
+{
+	struct rtw_mesh_cfg *mcfg = &adapter->mesh_cfg;
+	int updated = 0;
+
+	/*
+	* TODO: compare next_hop reference cnt of forwarding info
+	* don't sacrifice working next_hop or choose sta with least cnt
+	*/
+
+	if (*sac == NULL) {
+		updated = 1;
+		goto exit;
+	}
+
+#if CONFIG_RTW_MESH_CTO_MGATE_BLACKLIST
+	if (mcfg->peer_sel_policy.cto_mgate_require
+		&& !mcfg->dot11MeshGateAnnouncementProtocol
+	) {
+		if (IS_CTO_MGATE_CONF_TIMEOUT(com->plink)) {
+			if (!IS_CTO_MGATE_CONF_TIMEOUT((*sac)->plink)) {
+				/* blacklist > not blacklist */
+				updated = 1;
+				goto exit;
+			}
+		} else if (!IS_CTO_MGATE_CONF_DISABLED(com->plink)) {
+			if (IS_CTO_MGATE_CONF_DISABLED((*sac)->plink)) {
+				/* confirming > disabled */
+				updated = 1;
+				goto exit;
+			}
+		}
+	}
+#endif
+
+exit:
+	if (updated)
+		*sac = com;
+
+	return updated;
+}
+
+struct sta_info *_rtw_mesh_acnode_prevent_pick_sacrifice(_adapter *adapter)
+{
+	struct sta_priv *stapriv = &adapter->stapriv;
+	_list *head, *list;
+	struct sta_info *sta, *sacrifice = NULL;
+	u8 nop;
+
+	head = &stapriv->asoc_list;
+	list = get_next(head);
+	while (rtw_end_of_queue_search(head, list) == _FALSE) {
+		sta = LIST_CONTAINOR(list, struct sta_info, asoc_list);
+		list = get_next(list);
+
+		if (!sta->plink || !sta->plink->scanned) {
+			rtw_warn_on(1);
+			continue;
+		}
+
+		rtw_mesh_bss_peering_status(&sta->plink->scanned->network, &nop, NULL);
+		if (nop < 2)
+			continue;
+
+		rtw_mesh_acnode_prevent_sacrifice_chk(adapter, &sacrifice, sta);
+	}
+
+	return sacrifice;
+}
+
+struct sta_info *rtw_mesh_acnode_prevent_pick_sacrifice(_adapter *adapter)
+{
+	struct sta_priv *stapriv = &adapter->stapriv;
+	struct sta_info *sacrifice = NULL;
+
+	enter_critical_bh(&stapriv->asoc_list_lock);
+
+	sacrifice = _rtw_mesh_acnode_prevent_pick_sacrifice(adapter);
+
+	exit_critical_bh(&stapriv->asoc_list_lock);
+
+	return sacrifice;
+}
+
+static void rtw_mesh_acnode_rsvd_chk(_adapter *adapter)
+{
+	struct rtw_mesh_info *minfo = &adapter->mesh_info;
+	struct mesh_plink_pool *plink_ctl = &minfo->plink_ctl;
+	u8 acnode_rsvd = 0;
+
+	if (rtw_mesh_acnode_prevent_allow_sacrifice(adapter)
+		&& rtw_mesh_acnode_prevent_pick_sacrifice(adapter)
+		&& rtw_mesh_acnode_candidate_exist(adapter))
+		acnode_rsvd = 1;
+
+	if (plink_ctl->acnode_rsvd != acnode_rsvd) {
+		plink_ctl->acnode_rsvd = acnode_rsvd;
+		RTW_INFO(FUNC_ADPT_FMT" acnode_rsvd = %d\n", FUNC_ADPT_ARG(adapter), plink_ctl->acnode_rsvd);
+		update_beacon(adapter, WLAN_EID_MESH_CONFIG, NULL, 1);
+	}
+}
+
+static void rtw_mesh_acnode_set_notify_etime(_adapter *adapter, u8 *rframe_whdr)
+{
+	if (adapter->mesh_info.plink_ctl.acnode_rsvd) {
+		struct wlan_network *scanned = rtw_find_network(&adapter->mlmepriv.scanned_queue, get_addr2_ptr(rframe_whdr));
+
+		if (rtw_mesh_scanned_is_acnode_confirmed(adapter, scanned)) {
+			scanned->acnode_notify_etime = rtw_get_current_time()
+				+ rtw_ms_to_systime(adapter->mesh_cfg.peer_sel_policy.acnode_notify_timeout_ms);
+			if (scanned->acnode_notify_etime == 0)
+				scanned->acnode_notify_etime++;
+		}
+	}
+}
+
+void dump_mesh_acnode_prevent_settings(void *sel, _adapter *adapter)
+{
+	struct mesh_peer_sel_policy *peer_sel_policy = &adapter->mesh_cfg.peer_sel_policy;
+
+	RTW_PRINT_SEL(sel, "%-6s %-12s %-14s\n"
+		, "enable", "conf_timeout", "nofity_timeout");
+	RTW_PRINT_SEL(sel, "%6u %12u %14u\n"
+		, peer_sel_policy->acnode_prevent
+		, peer_sel_policy->acnode_conf_timeout_ms
+		, peer_sel_policy->acnode_notify_timeout_ms);
+}
+#endif /* CONFIG_RTW_MESH_ACNODE_PREVENT */
+
+#if CONFIG_RTW_MESH_PEER_BLACKLIST
+int rtw_mesh_peer_blacklist_add(_adapter *adapter, const u8 *addr)
+{
+	struct rtw_mesh_cfg *mcfg = &adapter->mesh_cfg;
+	struct rtw_mesh_info *minfo = &adapter->mesh_info;
+	struct mesh_plink_pool *plink_ctl = &minfo->plink_ctl;
+
+	return rtw_blacklist_add(&plink_ctl->peer_blacklist, addr
+		, mcfg->peer_sel_policy.peer_blacklist_timeout_ms);
+}
+
+int rtw_mesh_peer_blacklist_del(_adapter *adapter, const u8 *addr)
+{
+	struct rtw_mesh_info *minfo = &adapter->mesh_info;
+	struct mesh_plink_pool *plink_ctl = &minfo->plink_ctl;
+
+	return rtw_blacklist_del(&plink_ctl->peer_blacklist, addr);
+}
+
+int rtw_mesh_peer_blacklist_search(_adapter *adapter, const u8 *addr)
+{
+	struct rtw_mesh_info *minfo = &adapter->mesh_info;
+	struct mesh_plink_pool *plink_ctl = &minfo->plink_ctl;
+
+	return rtw_blacklist_search(&plink_ctl->peer_blacklist, addr);
+}
+
+void rtw_mesh_peer_blacklist_flush(_adapter *adapter)
+{
+	struct rtw_mesh_info *minfo = &adapter->mesh_info;
+	struct mesh_plink_pool *plink_ctl = &minfo->plink_ctl;
+
+	rtw_blacklist_flush(&plink_ctl->peer_blacklist);
+}
+
+void dump_mesh_peer_blacklist(void *sel, _adapter *adapter)
+{
+	struct rtw_mesh_info *minfo = &adapter->mesh_info;
+	struct mesh_plink_pool *plink_ctl = &minfo->plink_ctl;
+
+	dump_blacklist(sel, &plink_ctl->peer_blacklist, "blacklist");
+}
+
+void dump_mesh_peer_blacklist_settings(void *sel, _adapter *adapter)
+{
+	struct mesh_peer_sel_policy *peer_sel_policy = &adapter->mesh_cfg.peer_sel_policy;
+
+	RTW_PRINT_SEL(sel, "%-12s %-17s\n"
+		, "conf_timeout", "blacklist_timeout");
+	RTW_PRINT_SEL(sel, "%12u %17u\n"
+		, peer_sel_policy->peer_conf_timeout_ms
+		, peer_sel_policy->peer_blacklist_timeout_ms);
+}
+#endif /* CONFIG_RTW_MESH_PEER_BLACKLIST */
+
+#if CONFIG_RTW_MESH_CTO_MGATE_BLACKLIST
+u8 rtw_mesh_cto_mgate_required(_adapter *adapter)
+{
+	struct rtw_mesh_cfg *mcfg = &adapter->mesh_cfg;
+	struct mlme_ext_priv *mlmeext = &adapter->mlmeextpriv;
+
+	return mcfg->peer_sel_policy.cto_mgate_require
+		&& !rtw_bss_is_cto_mgate(&(mlmeext->mlmext_info.network));
+}
+
+u8 rtw_mesh_cto_mgate_network_filter(_adapter *adapter, struct wlan_network *scanned)
+{
+	struct rtw_mesh_cfg *mcfg = &adapter->mesh_cfg;
+	struct mlme_ext_priv *mlmeext = &adapter->mlmeextpriv;
+
+	return !rtw_mesh_cto_mgate_required(adapter)
+			|| (rtw_bss_is_cto_mgate(&scanned->network)
+				&& !rtw_mesh_cto_mgate_blacklist_search(adapter, scanned->network.MacAddress));
+}
+
+int rtw_mesh_cto_mgate_blacklist_add(_adapter *adapter, const u8 *addr)
+{
+	struct rtw_mesh_cfg *mcfg = &adapter->mesh_cfg;
+	struct rtw_mesh_info *minfo = &adapter->mesh_info;
+	struct mesh_plink_pool *plink_ctl = &minfo->plink_ctl;
+
+	return rtw_blacklist_add(&plink_ctl->cto_mgate_blacklist, addr
+		, mcfg->peer_sel_policy.cto_mgate_blacklist_timeout_ms);
+}
+
+int rtw_mesh_cto_mgate_blacklist_del(_adapter *adapter, const u8 *addr)
+{
+	struct rtw_mesh_info *minfo = &adapter->mesh_info;
+	struct mesh_plink_pool *plink_ctl = &minfo->plink_ctl;
+
+	return rtw_blacklist_del(&plink_ctl->cto_mgate_blacklist, addr);
+}
+
+int rtw_mesh_cto_mgate_blacklist_search(_adapter *adapter, const u8 *addr)
+{
+	struct rtw_mesh_info *minfo = &adapter->mesh_info;
+	struct mesh_plink_pool *plink_ctl = &minfo->plink_ctl;
+
+	return rtw_blacklist_search(&plink_ctl->cto_mgate_blacklist, addr);
+}
+
+void rtw_mesh_cto_mgate_blacklist_flush(_adapter *adapter)
+{
+	struct rtw_mesh_info *minfo = &adapter->mesh_info;
+	struct mesh_plink_pool *plink_ctl = &minfo->plink_ctl;
+
+	rtw_blacklist_flush(&plink_ctl->cto_mgate_blacklist);
+}
+
+void dump_mesh_cto_mgate_blacklist(void *sel, _adapter *adapter)
+{
+	struct rtw_mesh_info *minfo = &adapter->mesh_info;
+	struct mesh_plink_pool *plink_ctl = &minfo->plink_ctl;
+
+	dump_blacklist(sel, &plink_ctl->cto_mgate_blacklist, "blacklist");
+}
+
+void dump_mesh_cto_mgate_blacklist_settings(void *sel, _adapter *adapter)
+{
+	struct mesh_peer_sel_policy *peer_sel_policy = &adapter->mesh_cfg.peer_sel_policy;
+
+	RTW_PRINT_SEL(sel, "%-12s %-17s\n"
+		, "conf_timeout", "blacklist_timeout");
+	RTW_PRINT_SEL(sel, "%12u %17u\n"
+		, peer_sel_policy->cto_mgate_conf_timeout_ms
+		, peer_sel_policy->cto_mgate_blacklist_timeout_ms);
+}
+
+static void rtw_mesh_cto_mgate_blacklist_chk(_adapter *adapter)
+{
+	struct rtw_mesh_info *minfo = &adapter->mesh_info;
+	struct mesh_plink_pool *plink_ctl = &minfo->plink_ctl;
+	_queue *blist = &plink_ctl->cto_mgate_blacklist;
+	_list *list, *head;
+	struct blacklist_ent *ent = NULL;
+	struct wlan_network *scanned = NULL;
+
+	enter_critical_bh(&blist->lock);
+	head = &blist->queue;
+	list = get_next(head);
+	while (rtw_end_of_queue_search(head, list) == _FALSE) {
+		ent = LIST_CONTAINOR(list, struct blacklist_ent, list);
+		list = get_next(list);
+
+		if (rtw_time_after(rtw_get_current_time(), ent->exp_time)) {
+			rtw_list_delete(&ent->list);
+			rtw_mfree(ent, sizeof(struct blacklist_ent));
+			continue;
+		}
+
+		scanned = rtw_find_network(&adapter->mlmepriv.scanned_queue, ent->addr);
+		if (!scanned)
+			continue;
+
+		if (rtw_bss_is_forwarding(&scanned->network)) {
+			rtw_list_delete(&ent->list);
+			rtw_mfree(ent, sizeof(struct blacklist_ent));
+		}
+	}
+
+	exit_critical_bh(&blist->lock);
+}
+#endif /* CONFIG_RTW_MESH_CTO_MGATE_BLACKLIST */
+
+void rtw_chk_candidate_peer_notify(_adapter *adapter, struct wlan_network *scanned)
+{
+	struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter);
+	struct mlme_priv *mlme = &adapter->mlmepriv;
+	struct rtw_mesh_info *minfo = &adapter->mesh_info;
+	struct rtw_mesh_cfg *mcfg = &adapter->mesh_cfg;
+	struct mesh_plink_pool *plink_ctl = &minfo->plink_ctl;
+	bool acnode = 0;
+
+	if (IS_CH_WAITING(rfctl) && !IS_UNDER_CAC(rfctl))
+		goto exit;
+
+	if (plink_ctl->num >= RTW_MESH_MAX_PEER_CANDIDATES)
+		goto exit;
+
+#if CONFIG_RTW_MESH_ACNODE_PREVENT
+	if (plink_ctl->acnode_rsvd) {
+		acnode = rtw_mesh_scanned_is_acnode_confirmed(adapter, scanned);
+		if (acnode && !rtw_mesh_scanned_is_acnode_allow_notify(adapter, scanned))
+			goto exit;
+	}
+#endif
+
+	/* wpa_supplicant's auto peer will initiate peering when candidate peer is reported without max_peer_links consideration */
+	if (plink_ctl->num >= mcfg->max_peer_links + acnode ? 1 : 0)
+		goto exit;
+
+	if (rtw_get_passing_time_ms(scanned->last_scanned) >= mcfg->peer_sel_policy.scanr_exp_ms
+		|| (mcfg->rssi_threshold && mcfg->rssi_threshold > scanned->network.Rssi)
+		|| !rtw_bss_is_candidate_mesh_peer(&mlme->cur_network.network, &scanned->network, 1, 1)
+		#if CONFIG_RTW_MACADDR_ACL
+		|| rtw_access_ctrl(adapter, scanned->network.MacAddress) == _FALSE
+		#endif
+		|| rtw_mesh_plink_get(adapter, scanned->network.MacAddress)
+		#if CONFIG_RTW_MESH_PEER_BLACKLIST
+		|| rtw_mesh_peer_blacklist_search(adapter, scanned->network.MacAddress)
+		#endif
+		#if CONFIG_RTW_MESH_CTO_MGATE_BLACKLIST
+		|| !rtw_mesh_cto_mgate_network_filter(adapter, scanned)
+		#endif
+	)
+		goto exit;
+
+#if CONFIG_RTW_MESH_ACNODE_PREVENT
+	if (acnode) {
+		scanned->acnode_notify_etime = 0;
+		RTW_INFO(FUNC_ADPT_FMT" acnode "MAC_FMT"\n"
+			, FUNC_ADPT_ARG(adapter), MAC_ARG(scanned->network.MacAddress));
+	}
+#endif
+
+#ifdef CONFIG_IOCTL_CFG80211
+	rtw_cfg80211_notify_new_peer_candidate(adapter->rtw_wdev
+		, scanned->network.MacAddress
+		, BSS_EX_TLV_IES(&scanned->network)
+		, BSS_EX_TLV_IES_LEN(&scanned->network)
+		, GFP_ATOMIC
+	);
+#endif
+
+exit:
+	return;
+}
+
+void rtw_mesh_peer_status_chk(_adapter *adapter)
+{
+	struct mlme_priv *mlme = &adapter->mlmepriv;
+	struct rtw_mesh_cfg *mcfg = &adapter->mesh_cfg;
+	struct rtw_mesh_info *minfo = &adapter->mesh_info;
+	struct mesh_plink_pool *plink_ctl = &minfo->plink_ctl;
+	struct mesh_plink_ent *plink;
+	_list *head, *list;
+	struct sta_info *sta = NULL;
+	struct sta_priv *stapriv = &adapter->stapriv;
+	int stainfo_offset;
+#if CONFIG_RTW_MESH_CTO_MGATE_BLACKLIST
+	u8 cto_mgate, forwarding, mgate;
+#endif
+	u8 flush;
+	s8 flush_list[NUM_STA];
+	u8 flush_num = 0;
+	int i;
+
+#if CONFIG_RTW_MESH_CTO_MGATE_BLACKLIST
+	if (rtw_mesh_cto_mgate_required(adapter)) {
+		/* active scan on operating channel */
+		issue_probereq_ex(adapter, &adapter->mlmepriv.cur_network.network.mesh_id, NULL, 0, 0, 0, 0);
+	}
+#endif
+
+	enter_critical_bh(&(plink_ctl->lock));
+
+	/* check established peers */
+	enter_critical_bh(&stapriv->asoc_list_lock);
+
+	head = &stapriv->asoc_list;
+	list = get_next(head);
+	while (rtw_end_of_queue_search(head, list) == _FALSE) {
+		sta = LIST_CONTAINOR(list, struct sta_info, asoc_list);
+		list = get_next(list);
+
+		if (!sta->plink || !sta->plink->scanned) {
+			rtw_warn_on(1);
+			continue;
+		}
+		plink = sta->plink;
+		flush = 0;
+
+		/* remove unsuitable peer */
+		if (!rtw_bss_is_candidate_mesh_peer(&mlme->cur_network.network, &plink->scanned->network, 1, 0)
+			#if CONFIG_RTW_MACADDR_ACL
+			|| rtw_access_ctrl(adapter, plink->addr) == _FALSE
+			#endif
+		) {
+			flush = 1;
+			goto flush_add;
+		}
+
+		#if CONFIG_RTW_MESH_CTO_MGATE_BLACKLIST
+		cto_mgate = rtw_bss_is_cto_mgate(&(plink->scanned->network));
+		forwarding = rtw_bss_is_forwarding(&(plink->scanned->network));
+		mgate = rtw_mesh_gate_search(minfo->mesh_paths, sta->cmn.mac_addr);
+
+		/* CTO_MGATE required, remove peer without CTO_MGATE */
+		if (rtw_mesh_cto_mgate_required(adapter) && !cto_mgate) {
+			flush = 1;
+			goto flush_add;
+		}
+
+		/* cto_mgate_conf status update */
+		if (IS_CTO_MGATE_CONF_DISABLED(plink)) {
+			if (cto_mgate && !forwarding && !mgate)
+				SET_CTO_MGATE_CONF_END_TIME(plink, mcfg->peer_sel_policy.cto_mgate_conf_timeout_ms);
+			else
+				rtw_mesh_cto_mgate_blacklist_del(adapter, sta->cmn.mac_addr);
+		} else {
+			/* cto_mgate_conf ongoing */
+			if (cto_mgate && !forwarding && !mgate) {
+				if (IS_CTO_MGATE_CONF_TIMEOUT(plink)) {
+					rtw_mesh_cto_mgate_blacklist_add(adapter, sta->cmn.mac_addr);
+
+					/* CTO_MGATE required, remove peering can't achieve CTO_MGATE */
+					if (rtw_mesh_cto_mgate_required(adapter)) {
+						flush = 1;
+						goto flush_add;
+					}	
+				}
+			} else {
+				SET_CTO_MGATE_CONF_DISABLED(plink);
+				rtw_mesh_cto_mgate_blacklist_del(adapter, sta->cmn.mac_addr);
+			}
+		}
+		#endif /* CONFIG_RTW_MESH_CTO_MGATE_BLACKLIST */
+
+flush_add:
+		if (flush) {
+			rtw_list_delete(&sta->asoc_list);
+			stapriv->asoc_list_cnt--;
+			STA_SET_MESH_PLINK(sta, NULL);
+
+			stainfo_offset = rtw_stainfo_offset(stapriv, sta);
+			if (stainfo_offset_valid(stainfo_offset))
+				flush_list[flush_num++] = stainfo_offset;
+			else
+				rtw_warn_on(1);
+		}
+	}
+
+	exit_critical_bh(&stapriv->asoc_list_lock);
+
+	/* check non-established peers */
+	for (i = 0; i < RTW_MESH_MAX_PEER_CANDIDATES; i++) {
+		plink = &plink_ctl->ent[i];
+		if (plink->valid != _TRUE || plink->plink_state == RTW_MESH_PLINK_ESTAB)
+			continue;
+
+		/* remove unsuitable peer */
+		if (!rtw_bss_is_candidate_mesh_peer(&mlme->cur_network.network, &plink->scanned->network, 1, 1)
+			#if CONFIG_RTW_MACADDR_ACL
+			|| rtw_access_ctrl(adapter, plink->addr) == _FALSE
+			#endif
+		) {
+			_rtw_mesh_expire_peer_ent(adapter, plink);
+			continue;
+		}
+
+		#if CONFIG_RTW_MESH_PEER_BLACKLIST
+		/* peer confirm check timeout, add to black list */
+		if (IS_PEER_CONF_TIMEOUT(plink)) {
+			rtw_mesh_peer_blacklist_add(adapter, plink->addr);
+			_rtw_mesh_expire_peer_ent(adapter, plink);
+		}
+		#endif
+	}
+
+	exit_critical_bh(&(plink_ctl->lock));
+
+	if (flush_num) {
+		u8 sta_addr[ETH_ALEN];
+		u8 updated = _FALSE;
+
+		for (i = 0; i < flush_num; i++) {
+			sta = rtw_get_stainfo_by_offset(stapriv, flush_list[i]);
+			_rtw_memcpy(sta_addr, sta->cmn.mac_addr, ETH_ALEN);
+
+			updated |= ap_free_sta(adapter, sta, _TRUE, WLAN_REASON_DEAUTH_LEAVING, _FALSE);
+			rtw_mesh_expire_peer(adapter, sta_addr);
+		}
+
+		associated_clients_update(adapter, updated, STA_INFO_UPDATE_ALL);
+	}
+
+#if CONFIG_RTW_MESH_CTO_MGATE_BLACKLIST
+	/* loop cto_mgate_blacklist to remove ent according to scan_r */
+	rtw_mesh_cto_mgate_blacklist_chk(adapter);
+#endif
+
+#if CONFIG_RTW_MESH_ACNODE_PREVENT
+	rtw_mesh_acnode_rsvd_chk(adapter);
+#endif
+
+	return;
+}
+
+#if CONFIG_RTW_MESH_OFFCH_CAND
+static u8 rtw_mesh_offch_cto_mgate_required(_adapter *adapter)
+{
+#if CONFIG_RTW_MESH_CTO_MGATE_BLACKLIST
+	struct rtw_mesh_cfg *mcfg = &adapter->mesh_cfg;
+	struct mlme_priv *mlme = &adapter->mlmepriv;
+	_queue *queue = &(mlme->scanned_queue);
+	_list *head, *pos;
+	struct wlan_network *scanned = NULL;
+	u8 ret = 0;
+
+	if (!rtw_mesh_cto_mgate_required(adapter))
+		goto exit;
+
+	enter_critical_bh(&(mlme->scanned_queue.lock));
+
+	head = get_list_head(queue);
+	pos = get_next(head);
+	while (!rtw_end_of_queue_search(head, pos)) {
+		scanned = LIST_CONTAINOR(pos, struct wlan_network, list);
+
+		if (rtw_get_passing_time_ms(scanned->last_scanned) < mcfg->peer_sel_policy.scanr_exp_ms
+			&& (!mcfg->rssi_threshold || mcfg->rssi_threshold <= scanned->network.Rssi)
+			#if CONFIG_RTW_MACADDR_ACL
+			&& rtw_access_ctrl(adapter, scanned->network.MacAddress) == _TRUE
+			#endif
+			&& rtw_bss_is_candidate_mesh_peer(&mlme->cur_network.network, &scanned->network, 1, 1)
+			&& rtw_bss_is_cto_mgate(&scanned->network)
+			#if CONFIG_RTW_MESH_PEER_BLACKLIST
+			&& !rtw_mesh_peer_blacklist_search(adapter, scanned->network.MacAddress)
+			#endif
+			&& !rtw_mesh_cto_mgate_blacklist_search(adapter, scanned->network.MacAddress)
+		)
+			break;
+
+		pos = get_next(pos);
+	}
+
+	if (rtw_end_of_queue_search(head, pos))
+		ret = 1;
+
+	exit_critical_bh(&(mlme->scanned_queue.lock));
+
+exit:
+	return ret;
+#else
+	return 0;
+#endif /* CONFIG_RTW_MESH_CTO_MGATE_BLACKLIST */
+}
+
+u8 rtw_mesh_offch_candidate_accepted(_adapter *adapter)
+{
+	struct rtw_mesh_info *minfo = &adapter->mesh_info;
+	struct mesh_plink_pool *plink_ctl = &minfo->plink_ctl;
+	u8 ret = 0;
+
+	if (!adapter->mesh_cfg.peer_sel_policy.offch_cand)
+		goto exit;
+
+	ret = MLME_IS_MESH(adapter) && MLME_IS_ASOC(adapter)
+		&& (!plink_ctl->num || rtw_mesh_offch_cto_mgate_required(adapter))
+		;
+
+#ifdef CONFIG_CONCURRENT_MODE
+	if (ret) {
+		struct mi_state mstate_no_self;
+
+		rtw_mi_status_no_self(adapter, &mstate_no_self);
+		if (MSTATE_STA_LD_NUM(&mstate_no_self))
+			ret = 0;
+	}
+#endif
+
+exit:
+	return ret;
+}
+
+/*
+ * this function is called under off channel candidate is required 
+ * the channel with maximum candidate count is selected
+*/
+u8 rtw_mesh_select_operating_ch(_adapter *adapter)
+{
+	struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter);
+	struct rtw_mesh_cfg *mcfg = &adapter->mesh_cfg;
+	struct mlme_priv *mlme = &adapter->mlmepriv;
+	_queue *queue = &(mlme->scanned_queue);
+	_list *head, *pos;
+	_irqL irqL;
+	struct wlan_network *scanned = NULL;
+	int i;
+	/* statistics for candidate accept peering */
+	u8 cand_ap_cnt[MAX_CHANNEL_NUM] = {0};
+	u8 max_cand_ap_ch = 0;
+	u8 max_cand_ap_cnt = 0;
+	/* statistics for candidate including not accept peering */
+	u8 cand_cnt[MAX_CHANNEL_NUM] = {0};
+	u8 max_cand_ch = 0;
+	u8 max_cand_cnt = 0;
+
+	_enter_critical_bh(&(mlme->scanned_queue.lock), &irqL);
+
+	head = get_list_head(queue);
+	pos = get_next(head);
+	while (!rtw_end_of_queue_search(head, pos)) {
+		scanned = LIST_CONTAINOR(pos, struct wlan_network, list);
+		pos = get_next(pos);
+
+		if (rtw_get_passing_time_ms(scanned->last_scanned) < mcfg->peer_sel_policy.scanr_exp_ms
+			&& (!mcfg->rssi_threshold || mcfg->rssi_threshold <= scanned->network.Rssi)
+			#if CONFIG_RTW_MACADDR_ACL
+			&& rtw_access_ctrl(adapter, scanned->network.MacAddress) == _TRUE
+			#endif
+			&& rtw_bss_is_candidate_mesh_peer(&mlme->cur_network.network, &scanned->network, 0, 0)
+			#if CONFIG_RTW_MESH_PEER_BLACKLIST
+			&& !rtw_mesh_peer_blacklist_search(adapter, scanned->network.MacAddress)
+			#endif
+			#if CONFIG_RTW_MESH_CTO_MGATE_BLACKLIST
+			&& rtw_mesh_cto_mgate_network_filter(adapter, scanned)
+			#endif
+		) {
+			int ch_set_idx = rtw_chset_search_ch(rfctl->channel_set, scanned->network.Configuration.DSConfig);
+
+			if (ch_set_idx >= 0
+				&& !CH_IS_NON_OCP(&rfctl->channel_set[ch_set_idx])
+			) {
+				u8 nop, accept;
+
+				rtw_mesh_bss_peering_status(&scanned->network, &nop, &accept);
+				cand_cnt[ch_set_idx]++;
+				if (max_cand_cnt < cand_cnt[ch_set_idx]) {
+					max_cand_cnt = cand_cnt[ch_set_idx];
+					max_cand_ch = rfctl->channel_set[ch_set_idx].ChannelNum;
+				}
+				if (accept) {
+					cand_ap_cnt[ch_set_idx]++;
+					if (max_cand_ap_cnt < cand_ap_cnt[ch_set_idx]) {
+						max_cand_ap_cnt = cand_ap_cnt[ch_set_idx];
+						max_cand_ap_ch = rfctl->channel_set[ch_set_idx].ChannelNum;
+					}
+				}
+			}
+		}
+	}
+
+	_exit_critical_bh(&(mlme->scanned_queue.lock), &irqL);
+
+	return max_cand_ap_ch ? max_cand_ap_ch : max_cand_ch;
+}
+
+void dump_mesh_offch_cand_settings(void *sel, _adapter *adapter)
+{
+	struct mesh_peer_sel_policy *peer_sel_policy = &adapter->mesh_cfg.peer_sel_policy;
+
+	RTW_PRINT_SEL(sel, "%-6s %-11s\n"
+		, "enable", "find_int_ms");
+	RTW_PRINT_SEL(sel, "%6u %11u\n"
+		, peer_sel_policy->offch_cand, peer_sel_policy->offch_find_int_ms);
+}
+#endif /* CONFIG_RTW_MESH_OFFCH_CAND */
+
+void dump_mesh_peer_sel_policy(void *sel, _adapter *adapter)
+{
+	struct mesh_peer_sel_policy *peer_sel_policy = &adapter->mesh_cfg.peer_sel_policy;
+
+	RTW_PRINT_SEL(sel, "%-12s\n", "scanr_exp_ms");
+	RTW_PRINT_SEL(sel, "%12u\n", peer_sel_policy->scanr_exp_ms);
+}
+
+void dump_mesh_networks(void *sel, _adapter *adapter)
+{
+#if CONFIG_RTW_MESH_ACNODE_PREVENT
+#define NSTATE_TITLE_FMT_ACN " %-5s"
+#define NSTATE_VALUE_FMT_ACN " %5d"
+#define NSTATE_TITLE_ARG_ACN , "acn"
+#define NSTATE_VALUE_ARG_ACN , (acn_ms < 99999 ? acn_ms : 99999)
+#else
+#define NSTATE_TITLE_FMT_ACN ""
+#define NSTATE_VALUE_FMT_ACN ""
+#define NSTATE_TITLE_ARG_ACN
+#define NSTATE_VALUE_ARG_ACN
+#endif
+
+	struct mlme_priv *mlme = &(adapter->mlmepriv);
+	_queue *queue = &(mlme->scanned_queue);
+	struct wlan_network	*network;
+	_list *list, *head;
+	u8 same_mbss;
+	u8 candidate;
+	struct mesh_plink_ent *plink;
+	u8 blocked;
+	u8 established;
+	s32 age_ms;
+#if CONFIG_RTW_MESH_ACNODE_PREVENT
+	s32 acn_ms;
+#endif
+	u8 *mesh_conf_ie;
+	sint mesh_conf_ie_len;
+	struct wlan_network **mesh_networks;
+	u8 mesh_network_cnt = 0;
+	int i;
+
+	mesh_networks = rtw_zvmalloc(mlme->max_bss_cnt * sizeof(struct wlan_network *));
+	if (!mesh_networks)
+		return;
+
+	enter_critical_bh(&queue->lock);
+	head = get_list_head(queue);
+	list = get_next(head);
+
+	while (rtw_end_of_queue_search(head, list) == _FALSE) {
+		network = LIST_CONTAINOR(list, struct wlan_network, list);
+		list = get_next(list);
+
+		if (network->network.InfrastructureMode != Ndis802_11_mesh)
+			continue;
+
+		mesh_conf_ie = rtw_get_ie(BSS_EX_TLV_IES(&network->network), WLAN_EID_MESH_CONFIG
+			, &mesh_conf_ie_len, BSS_EX_TLV_IES_LEN(&network->network));
+		if (!mesh_conf_ie || mesh_conf_ie_len != 7)
+			continue;
+
+		mesh_networks[mesh_network_cnt++] = network;
+	}
+
+	exit_critical_bh(&queue->lock);
+
+	RTW_PRINT_SEL(sel, "  %-17s %-3s %-4s %-5s %-32s %-3s %-3s %-3s"
+		NSTATE_TITLE_FMT_ACN
+		"\n"
+		, "bssid", "ch", "rssi", "age", "mesh_id", "nop", "fwd", "cto"
+		NSTATE_TITLE_ARG_ACN
+	);
+
+	for (i = 0; i < mesh_network_cnt; i++) {
+		network = mesh_networks[i];
+
+		if (network->network.InfrastructureMode != Ndis802_11_mesh)
+			continue;
+
+		mesh_conf_ie = rtw_get_ie(BSS_EX_TLV_IES(&network->network), WLAN_EID_MESH_CONFIG
+			, &mesh_conf_ie_len, BSS_EX_TLV_IES_LEN(&network->network));
+		if (!mesh_conf_ie || mesh_conf_ie_len != 7)
+			continue;
+
+		age_ms = rtw_get_passing_time_ms(network->last_scanned);
+		#if CONFIG_RTW_MESH_ACNODE_PREVENT
+		if (network->acnode_stime == 0)
+			acn_ms = 0;
+		else
+			acn_ms = rtw_get_passing_time_ms(network->acnode_stime);
+		#endif
+		same_mbss = 0;
+		candidate = 0;
+		plink = NULL;
+		blocked = 0;
+		established = 0;
+
+		if (MLME_IS_MESH(adapter) && MLME_IS_ASOC(adapter)) {
+			plink = rtw_mesh_plink_get(adapter, network->network.MacAddress);
+			if (plink && plink->plink_state == RTW_MESH_PLINK_ESTAB)
+				established = 1;
+			else if (plink && plink->plink_state == RTW_MESH_PLINK_BLOCKED)
+				blocked = 1;
+			else if (plink)
+				;
+			else if (rtw_bss_is_candidate_mesh_peer(&mlme->cur_network.network, &network->network, 0, 1))
+				candidate = 1;
+			else if (rtw_bss_is_same_mbss(&mlme->cur_network.network, &network->network))
+				same_mbss = 1;
+		}
+
+		RTW_PRINT_SEL(sel, "%c "MAC_FMT" %3d %4ld %5d %-32s %c%2u %3u %c%c "
+			NSTATE_VALUE_FMT_ACN
+			"\n"
+			, established ? 'E' : (blocked ? 'B' : (plink ? 'N' : (candidate ? 'C' : (same_mbss ? 'S' : ' '))))
+			, MAC_ARG(network->network.MacAddress)
+			, network->network.Configuration.DSConfig
+			, network->network.Rssi
+			, age_ms < 99999 ? age_ms : 99999
+			, network->network.mesh_id.Ssid
+			, GET_MESH_CONF_ELE_ACCEPT_PEERINGS(mesh_conf_ie + 2) ? '+' : ' '
+			, GET_MESH_CONF_ELE_NUM_OF_PEERINGS(mesh_conf_ie + 2)
+			, GET_MESH_CONF_ELE_FORWARDING(mesh_conf_ie + 2)
+			, GET_MESH_CONF_ELE_CTO_MGATE(mesh_conf_ie + 2) ? 'G' : ' '
+			, GET_MESH_CONF_ELE_CTO_AS(mesh_conf_ie + 2) ? 'A' : ' '
+			NSTATE_VALUE_ARG_ACN
+		);
+	}
+
+	rtw_vmfree(mesh_networks, mlme->max_bss_cnt * sizeof(struct wlan_network *));
+}
+
+void rtw_mesh_adjust_chbw(u8 req_ch, u8 *req_bw, u8 *req_offset)
+{
+	if (req_ch >= 5 && req_ch <= 9) {
+		/* prevent secondary channel offset mismatch */
+		if (*req_bw > CHANNEL_WIDTH_20) {
+			*req_bw = CHANNEL_WIDTH_20;
+			*req_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
+		}
+	}
+}
+
+int rtw_sae_check_frames(_adapter *adapter, const u8 *buf, u32 len, u8 tx)
+{
+	const u8 *frame_body = buf + sizeof(struct rtw_ieee80211_hdr_3addr);
+	u16 alg;
+	u16 seq;
+	u16 status;
+	int ret = 0;
+
+	alg = RTW_GET_LE16(frame_body);
+	if (alg != 3)
+		goto exit;
+
+	seq = RTW_GET_LE16(frame_body + 2);
+	status = RTW_GET_LE16(frame_body + 4);
+
+	RTW_INFO("RTW_%s:AUTH alg:0x%04x, seq:0x%04x, status:0x%04x\n"
+		, (tx == _TRUE) ? "Tx" : "Rx", alg, seq, status);
+
+	ret = 1;
+
+#if CONFIG_RTW_MESH_PEER_BLACKLIST
+	if (tx && seq == 1)
+		rtw_mesh_plink_set_peer_conf_timeout(adapter, GetAddr1Ptr(buf));
+#endif
+
+exit:
+	return ret;
+}
+
+#if CONFIG_RTW_MPM_TX_IES_SYNC_BSS
+#ifdef CONFIG_RTW_MESH_AEK
+static int rtw_mpm_ampe_dec(_adapter *adapter, struct mesh_plink_ent *plink
+	, u8 *fhead, size_t flen, u8* fbody, u8 *mic_ie, u8 *ampe_buf)
+{	
+	int ret = _FAIL, verify_ret;
+	const u8 *aad[] = {adapter_mac_addr(adapter), plink->addr, fbody};
+	const size_t aad_len[] = {ETH_ALEN, ETH_ALEN, mic_ie - fbody};
+	u8 *iv_crypt;
+	size_t iv_crypt_len = flen - (mic_ie + 2 - fhead);
+
+	iv_crypt = rtw_malloc(iv_crypt_len);
+	if (!iv_crypt)
+		goto exit;
+
+	_rtw_memcpy(iv_crypt, mic_ie + 2, iv_crypt_len);
+
+	verify_ret = aes_siv_decrypt(plink->aek, iv_crypt, iv_crypt_len
+		, 3, aad, aad_len, ampe_buf);
+
+	rtw_mfree(iv_crypt, iv_crypt_len);
+
+	if (verify_ret) {
+		RTW_WARN("verify error, aek_valid=%u\n", plink->aek_valid);
+		goto exit;
+	} else if (*ampe_buf != WLAN_EID_AMPE) {
+		RTW_WARN("plaintext is not AMPE IE\n");
+		goto exit;
+	} else if (AES_BLOCK_SIZE + 2 + *(ampe_buf + 1) > iv_crypt_len) {
+		RTW_WARN("plaintext AMPE IE length is not valid\n");
+		goto exit;
+	}
+
+	ret = _SUCCESS;
+
+exit:
+	return ret;
+}
+
+static int rtw_mpm_ampe_enc(_adapter *adapter, struct mesh_plink_ent *plink
+	, u8* fbody, u8 *mic_ie, u8 *ampe_buf, bool inverse)
+{
+	int ret = _FAIL, protect_ret;
+	const u8 *aad[3];
+	const size_t aad_len[3] = {ETH_ALEN, ETH_ALEN, mic_ie - fbody};
+	u8 *ampe_ie;
+	size_t ampe_ie_len = *(ampe_buf + 1) + 2; /* including id & len */
+
+	if (inverse) {
+		aad[0] = plink->addr;
+		aad[1] = adapter_mac_addr(adapter);
+	} else {
+		aad[0] = adapter_mac_addr(adapter);
+		aad[1] = plink->addr;
+	}
+	aad[2] = fbody;
+
+	ampe_ie = rtw_malloc(ampe_ie_len);
+	if (!ampe_ie)
+		goto exit;
+
+	_rtw_memcpy(ampe_ie, ampe_buf, ampe_ie_len);
+
+	protect_ret = aes_siv_encrypt(plink->aek, ampe_ie, ampe_ie_len
+		, 3, aad, aad_len, mic_ie + 2);
+
+	rtw_mfree(ampe_ie, ampe_ie_len);
+
+	if (protect_ret) {
+		RTW_WARN("protect error, aek_valid=%u\n", plink->aek_valid);
+		goto exit;
+	}
+
+	ret = _SUCCESS;
+
+exit:
+	return ret;
+}
+#endif /* CONFIG_RTW_MESH_AEK */
+
+static int rtw_mpm_tx_ies_sync_bss(_adapter *adapter, struct mesh_plink_ent *plink
+	, u8 *fhead, size_t flen, u8* fbody, u8 tlv_ies_offset, u8 *mpm_ie, u8 *mic_ie
+	, u8 **nbuf, size_t *nlen)
+{
+	int ret = _FAIL;
+	struct mlme_priv *mlme = &(adapter->mlmepriv);
+	struct mlme_ext_priv *mlmeext = &adapter->mlmeextpriv;
+	struct mlme_ext_info *mlmeinfo = &(mlmeext->mlmext_info);
+	WLAN_BSSID_EX *network = &(mlmeinfo->network);
+	uint left;
+	u8 *pos;
+
+	uint mpm_ielen = *(mpm_ie + 1);
+	u8 *fpos;
+	u8 *new_buf = NULL;
+	size_t new_len = 0;
+
+	u8 *new_fhead;
+	size_t new_flen;
+	u8 *new_fbody;
+	u8 *new_mic_ie;
+
+#ifdef CONFIG_RTW_MESH_AEK
+	u8 *ampe_buf = NULL;
+	size_t ampe_buf_len = 0;
+
+	/* decode */
+	if (mic_ie) {
+		ampe_buf_len = flen - (mic_ie + 2 + AES_BLOCK_SIZE - fhead);
+		ampe_buf = rtw_malloc(ampe_buf_len);
+		if (!ampe_buf)
+			goto exit;
+
+		if (rtw_mpm_ampe_dec(adapter, plink, fhead, flen, fbody, mic_ie, ampe_buf) != _SUCCESS)
+			goto exit;
+
+		if (*(ampe_buf + 1) >= 68) {
+			_rtw_memcpy(plink->sel_pcs, ampe_buf + 2, 4);
+			_rtw_memcpy(plink->l_nonce, ampe_buf + 6, 32);
+			_rtw_memcpy(plink->p_nonce, ampe_buf + 38, 32);
+		}
+	}
+#endif
+
+	/* count for new frame length  */
+	new_len = sizeof(struct rtw_ieee80211_hdr_3addr) + tlv_ies_offset;
+	left = BSS_EX_TLV_IES_LEN(network);
+	pos = BSS_EX_TLV_IES(network);
+	while (left >= 2) {
+		u8 id, elen;
+	
+		id = *pos++;
+		elen = *pos++;
+		left -= 2;
+
+		if (elen > left)
+			break;
+
+		switch (id) {
+		case WLAN_EID_SSID:
+		case WLAN_EID_DS_PARAMS:
+		case WLAN_EID_TIM:
+			break;
+		default:
+			new_len += 2 + elen;
+		}
+
+		left -= elen;
+		pos += elen;
+	}
+	new_len += mpm_ielen + 2;
+	if (mic_ie)
+		new_len += AES_BLOCK_SIZE + 2 + ampe_buf_len;
+
+	/* alloc new frame */
+	new_buf = rtw_malloc(new_len);
+	if (!new_buf) {
+		rtw_warn_on(1);
+		goto exit;
+	}
+
+	/* build new frame  */
+	_rtw_memcpy(new_buf, fhead, sizeof(struct rtw_ieee80211_hdr_3addr) + tlv_ies_offset);
+	new_fhead = new_buf;
+	new_flen = new_len;
+	new_fbody = new_fhead + sizeof(struct rtw_ieee80211_hdr_3addr);
+
+	fpos = new_fbody + tlv_ies_offset;
+	left = BSS_EX_TLV_IES_LEN(network);
+	pos = BSS_EX_TLV_IES(network);
+	while (left >= 2) {
+		u8 id, elen;
+	
+		id = *pos++;
+		elen = *pos++;
+		left -= 2;
+
+		if (elen > left)
+			break;
+
+		switch (id) {
+		case WLAN_EID_SSID:
+		case WLAN_EID_DS_PARAMS:
+		case WLAN_EID_TIM:
+			break;
+		default:
+			fpos = rtw_set_ie(fpos, id, elen, pos, NULL);
+			if (id == WLAN_EID_MESH_CONFIG)
+				fpos = rtw_set_ie(fpos, WLAN_EID_MPM, mpm_ielen, mpm_ie + 2, NULL);
+		}
+
+		left -= elen;
+		pos += elen;
+	}
+	if (mic_ie) {
+		new_mic_ie = fpos;
+		*fpos++ = WLAN_EID_MIC;
+		*fpos++ = AES_BLOCK_SIZE;
+	}
+
+#ifdef CONFIG_RTW_MESH_AEK
+	/* encode */
+	if (mic_ie) {
+		int enc_ret = rtw_mpm_ampe_enc(adapter, plink, new_fbody, new_mic_ie, ampe_buf, 0);
+		if (enc_ret != _SUCCESS)
+			goto exit;
+	}
+#endif
+
+	*nlen = new_len;
+	*nbuf = new_buf;
+
+	ret = _SUCCESS;
+
+exit:
+	if (ret != _SUCCESS && new_buf)
+		rtw_mfree(new_buf, new_len);
+
+#ifdef CONFIG_RTW_MESH_AEK
+	if (ampe_buf)
+		rtw_mfree(ampe_buf, ampe_buf_len);
+#endif
+
+	return ret;
+}
+#endif /* CONFIG_RTW_MPM_TX_IES_SYNC_BSS */
+
+struct mpm_frame_info {
+	u8 *aid;
+	u16 aid_v;
+	u8 *pid;
+	u16 pid_v;
+	u8 *llid;
+	u16 llid_v;
+	u8 *plid;
+	u16 plid_v;
+	u8 *reason;
+	u16 reason_v;
+	u8 *chosen_pmk;
+};
+
+/*
+* pid:00000 llid:00000 chosen_pmk:0x00000000000000000000000000000000
+* aid:00000 pid:00000 llid:00000 plid:00000 chosen_pmk:0x00000000000000000000000000000000
+* pid:00000 llid:00000 plid:00000 reason:00000 chosen_pmk:0x00000000000000000000000000000000
+*/
+#define MPM_LOG_BUF_LEN 92 /* this length is limited for legal combination */
+static void rtw_mpm_info_msg(struct mpm_frame_info *mpm_info, u8 *mpm_log_buf)
+{
+	int cnt = 0;
+
+	if (mpm_info->aid) {
+		cnt += snprintf(mpm_log_buf + cnt, MPM_LOG_BUF_LEN - cnt - 1, "aid:%u ", mpm_info->aid_v);
+		if (cnt >= MPM_LOG_BUF_LEN - 1)
+			goto exit;
+	}
+	if (mpm_info->pid) {
+		cnt += snprintf(mpm_log_buf + cnt, MPM_LOG_BUF_LEN - cnt - 1, "pid:%u ", mpm_info->pid_v);
+		if (cnt >= MPM_LOG_BUF_LEN - 1)
+			goto exit;
+	}
+	if (mpm_info->llid) {
+		cnt += snprintf(mpm_log_buf + cnt, MPM_LOG_BUF_LEN - cnt - 1, "llid:%u ", mpm_info->llid_v);
+		if (cnt >= MPM_LOG_BUF_LEN - 1)
+			goto exit;
+	}
+	if (mpm_info->plid) {
+		cnt += snprintf(mpm_log_buf + cnt, MPM_LOG_BUF_LEN - cnt - 1, "plid:%u ", mpm_info->plid_v);
+		if (cnt >= MPM_LOG_BUF_LEN - 1)
+			goto exit;
+	}
+	if (mpm_info->reason) {
+		cnt += snprintf(mpm_log_buf + cnt, MPM_LOG_BUF_LEN - cnt - 1, "reason:%u ", mpm_info->reason_v);
+		if (cnt >= MPM_LOG_BUF_LEN - 1)
+			goto exit;
+	}
+	if (mpm_info->chosen_pmk) {
+		cnt += snprintf(mpm_log_buf + cnt, MPM_LOG_BUF_LEN - cnt - 1, "chosen_pmk:0x"KEY_FMT, KEY_ARG(mpm_info->chosen_pmk));
+		if (cnt >= MPM_LOG_BUF_LEN - 1)
+			goto exit;
+	}
+
+exit:
+	return;
+}
+
+static int rtw_mpm_check_frames(_adapter *adapter, u8 action, const u8 **buf, size_t *len, u8 tx)
+{
+	struct rtw_mesh_info *minfo = &adapter->mesh_info;
+	struct mesh_plink_pool *plink_ctl = &minfo->plink_ctl;
+	struct mesh_plink_ent *plink = NULL;
+	u8 *nbuf = NULL;
+	size_t nlen = 0;
+	u8 *fhead = (u8 *)*buf;
+	size_t flen = *len;
+	u8 *peer_addr = tx ? GetAddr1Ptr(fhead) : get_addr2_ptr(fhead);
+	u8 *frame_body = fhead + sizeof(struct rtw_ieee80211_hdr_3addr);
+	struct mpm_frame_info mpm_info;
+	u8 tlv_ies_offset;
+	u8 *mpm_ie = NULL;
+	uint mpm_ielen = 0;
+	u8 *mic_ie = NULL;
+	uint mic_ielen = 0;
+	int ret = 0;
+	u8 mpm_log_buf[MPM_LOG_BUF_LEN] = {0};
+
+	if (action == RTW_ACT_SELF_PROTECTED_MESH_OPEN)
+		tlv_ies_offset = 4;
+	else if (action == RTW_ACT_SELF_PROTECTED_MESH_CONF)
+		tlv_ies_offset = 6;
+	else if (action == RTW_ACT_SELF_PROTECTED_MESH_CLOSE)
+		tlv_ies_offset = 2;
+	else {
+		rtw_warn_on(1);
+		goto exit;
+	}
+
+	plink = rtw_mesh_plink_get(adapter, peer_addr);
+	if (!plink && (tx == _TRUE || action == RTW_ACT_SELF_PROTECTED_MESH_CONF)) {
+		/* warning message if no plink when: 1.TX all MPM or 2.RX CONF */
+		RTW_WARN("RTW_%s:%s without plink of "MAC_FMT"\n"
+			, (tx == _TRUE) ? "Tx" : "Rx", action_self_protected_str(action), MAC_ARG(peer_addr));
+		goto exit;
+	}
+
+	_rtw_memset(&mpm_info, 0, sizeof(struct mpm_frame_info));
+
+	if (action == RTW_ACT_SELF_PROTECTED_MESH_CONF) {
+		mpm_info.aid = (u8 *)frame_body + 4;
+		mpm_info.aid_v = RTW_GET_LE16(mpm_info.aid);
+	}
+
+	mpm_ie = rtw_get_ie(fhead + sizeof(struct rtw_ieee80211_hdr_3addr) + tlv_ies_offset
+		, WLAN_EID_MPM, &mpm_ielen
+		, flen - sizeof(struct rtw_ieee80211_hdr_3addr) - tlv_ies_offset);
+	if (!mpm_ie || mpm_ielen < 2 + 2)
+		goto exit;
+
+	mpm_info.pid = mpm_ie + 2;
+	mpm_info.pid_v = RTW_GET_LE16(mpm_info.pid);
+	mpm_info.llid = mpm_info.pid + 2;
+	mpm_info.llid_v = RTW_GET_LE16(mpm_info.llid);
+
+	switch (action) {
+	case RTW_ACT_SELF_PROTECTED_MESH_OPEN:
+		/* pid:2, llid:2, (chosen_pmk:16) */
+		if (mpm_info.pid_v == 0 && mpm_ielen == 4)
+			;
+		else if (mpm_info.pid_v == 1 && mpm_ielen == 20)
+			mpm_info.chosen_pmk = mpm_info.llid + 2;
+		else
+			goto exit;
+		break;
+	case RTW_ACT_SELF_PROTECTED_MESH_CONF:
+		/* pid:2, llid:2, plid:2, (chosen_pmk:16) */
+		mpm_info.plid = mpm_info.llid + 2;
+		mpm_info.plid_v = RTW_GET_LE16(mpm_info.plid);
+		if (mpm_info.pid_v == 0 && mpm_ielen == 6)
+			;
+		else if (mpm_info.pid_v == 1 && mpm_ielen == 22)
+			mpm_info.chosen_pmk = mpm_info.plid + 2;
+		else
+			goto exit;
+		break;
+	case RTW_ACT_SELF_PROTECTED_MESH_CLOSE:
+		/* pid:2, llid:2, (plid:2), reason:2, (chosen_pmk:16) */
+		if (mpm_info.pid_v == 0 && mpm_ielen == 6) {
+			/* MPM, without plid */
+			mpm_info.reason = mpm_info.llid + 2;
+			mpm_info.reason_v = RTW_GET_LE16(mpm_info.reason);
+		} else if (mpm_info.pid_v == 0 && mpm_ielen == 8) {
+			/* MPM, with plid */
+			mpm_info.plid = mpm_info.llid + 2;
+			mpm_info.plid_v = RTW_GET_LE16(mpm_info.plid);
+			mpm_info.reason = mpm_info.plid + 2;
+			mpm_info.reason_v = RTW_GET_LE16(mpm_info.reason);
+		} else if (mpm_info.pid_v == 1 && mpm_ielen == 22) {
+			/* AMPE, without plid */
+			mpm_info.reason = mpm_info.llid + 2;
+			mpm_info.reason_v = RTW_GET_LE16(mpm_info.reason);
+			mpm_info.chosen_pmk = mpm_info.reason + 2;
+		} else if (mpm_info.pid_v == 1 && mpm_ielen == 24) {
+			/* AMPE, with plid */
+			mpm_info.plid = mpm_info.llid + 2;
+			mpm_info.plid_v = RTW_GET_LE16(mpm_info.plid);
+			mpm_info.reason = mpm_info.plid + 2;
+			mpm_info.reason_v = RTW_GET_LE16(mpm_info.reason);
+			mpm_info.chosen_pmk = mpm_info.reason + 2;
+		} else
+			goto exit;
+		break;
+	};
+
+	if (mpm_info.pid_v == 1) {
+		mic_ie = rtw_get_ie(fhead + sizeof(struct rtw_ieee80211_hdr_3addr) + tlv_ies_offset
+			, WLAN_EID_MIC, &mic_ielen
+			, flen - sizeof(struct rtw_ieee80211_hdr_3addr) - tlv_ies_offset);
+		if (!mic_ie || mic_ielen != AES_BLOCK_SIZE)
+			goto exit;
+	}
+
+#if CONFIG_RTW_MPM_TX_IES_SYNC_BSS
+	if ((action == RTW_ACT_SELF_PROTECTED_MESH_OPEN || action == RTW_ACT_SELF_PROTECTED_MESH_CONF)
+		&& tx == _TRUE
+	) {
+#define DBG_RTW_MPM_TX_IES_SYNC_BSS 0
+
+		if (mpm_info.pid_v == 1 && (!plink || !MESH_PLINK_AEK_VALID(plink))) {
+			RTW_WARN("AEK not ready, IEs can't sync with BSS\n");
+			goto bypass_sync_bss;
+		}
+
+		if (DBG_RTW_MPM_TX_IES_SYNC_BSS) {
+			RTW_INFO(FUNC_ADPT_FMT" before:\n", FUNC_ADPT_ARG(adapter));
+			dump_ies(RTW_DBGDUMP
+				, fhead + sizeof(struct rtw_ieee80211_hdr_3addr) + tlv_ies_offset
+				, flen - sizeof(struct rtw_ieee80211_hdr_3addr) - tlv_ies_offset);
+		}
+
+		rtw_mpm_tx_ies_sync_bss(adapter, plink
+			, fhead, flen, frame_body, tlv_ies_offset, mpm_ie, mic_ie
+			, &nbuf, &nlen);
+		if (!nbuf)
+			goto exit;
+
+		/* update pointer & len for new frame */
+		fhead = nbuf;
+		flen = nlen;
+		frame_body = fhead + sizeof(struct rtw_ieee80211_hdr_3addr);
+		if (mpm_info.pid_v == 1) {
+			mic_ie = rtw_get_ie(fhead + sizeof(struct rtw_ieee80211_hdr_3addr) + tlv_ies_offset
+				, WLAN_EID_MIC, &mic_ielen
+				, flen - sizeof(struct rtw_ieee80211_hdr_3addr) - tlv_ies_offset);
+		}
+
+		if (DBG_RTW_MPM_TX_IES_SYNC_BSS) {
+			RTW_INFO(FUNC_ADPT_FMT" after:\n", FUNC_ADPT_ARG(adapter));
+			dump_ies(RTW_DBGDUMP
+				, fhead + sizeof(struct rtw_ieee80211_hdr_3addr) + tlv_ies_offset
+				, flen - sizeof(struct rtw_ieee80211_hdr_3addr) - tlv_ies_offset);
+		}
+	}
+bypass_sync_bss:
+#endif /* CONFIG_RTW_MPM_TX_IES_SYNC_BSS */
+
+	if (!plink)
+		goto mpm_log;
+
+#if CONFIG_RTW_MESH_PEER_BLACKLIST
+	if (action == RTW_ACT_SELF_PROTECTED_MESH_OPEN) {
+		if (tx)
+			rtw_mesh_plink_set_peer_conf_timeout(adapter, peer_addr);
+
+	} else
+#endif
+#if CONFIG_RTW_MESH_ACNODE_PREVENT
+	if (action == RTW_ACT_SELF_PROTECTED_MESH_CLOSE) {
+		if (tx && mpm_info.reason && mpm_info.reason_v == WLAN_REASON_MESH_MAX_PEERS) {
+			if (rtw_mesh_scanned_is_acnode_confirmed(adapter, plink->scanned)
+				&& rtw_mesh_acnode_prevent_allow_sacrifice(adapter)
+			) {
+				struct sta_info *sac = rtw_mesh_acnode_prevent_pick_sacrifice(adapter);
+
+				if (sac) {
+					struct sta_priv *stapriv = &adapter->stapriv;
+					_irqL irqL;
+					u8 sta_addr[ETH_ALEN];
+					u8 updated = _FALSE;
+
+					_enter_critical_bh(&stapriv->asoc_list_lock, &irqL);
+					if (!rtw_is_list_empty(&sac->asoc_list)) {
+						rtw_list_delete(&sac->asoc_list);
+						stapriv->asoc_list_cnt--;
+						STA_SET_MESH_PLINK(sac, NULL);
+					}
+					_exit_critical_bh(&stapriv->asoc_list_lock, &irqL);
+					RTW_INFO(FUNC_ADPT_FMT" sacrifice "MAC_FMT" for acnode\n"
+						, FUNC_ADPT_ARG(adapter), MAC_ARG(sac->cmn.mac_addr));
+
+					_rtw_memcpy(sta_addr, sac->cmn.mac_addr, ETH_ALEN);
+					updated = ap_free_sta(adapter, sac, 0, 0, 1);
+					rtw_mesh_expire_peer(stapriv->padapter, sta_addr);
+
+					associated_clients_update(adapter, updated, STA_INFO_UPDATE_ALL);
+				}
+			}
+		}
+	} else
+#endif
+	if (action == RTW_ACT_SELF_PROTECTED_MESH_CONF) {
+		_irqL irqL;
+		u8 *ies = NULL;
+		u16 ies_len = 0;
+
+		_enter_critical_bh(&(plink_ctl->lock), &irqL);
+
+		plink = _rtw_mesh_plink_get(adapter, peer_addr);
+		if (!plink)
+			goto release_plink_ctl;
+
+		if (tx == _FALSE) {
+			ies = plink->rx_conf_ies;
+			ies_len = plink->rx_conf_ies_len;
+			plink->rx_conf_ies = NULL;
+			plink->rx_conf_ies_len = 0;
+
+			plink->llid = mpm_info.plid_v;
+			plink->plid = mpm_info.llid_v;
+			plink->peer_aid = mpm_info.aid_v;
+			if (mpm_info.pid_v == 1)
+				_rtw_memcpy(plink->chosen_pmk, mpm_info.chosen_pmk, 16);
+		}
+		#ifdef CONFIG_RTW_MESH_DRIVER_AID
+		else {
+			ies = plink->tx_conf_ies;
+			ies_len = plink->tx_conf_ies_len;
+			plink->tx_conf_ies = NULL;
+			plink->tx_conf_ies_len = 0;
+		}
+		#endif
+
+		if (ies && ies_len)
+			rtw_mfree(ies, ies_len);
+
+		#ifndef CONFIG_RTW_MESH_DRIVER_AID
+		if (tx == _TRUE)
+			goto release_plink_ctl; /* no need to copy tx conf ies */
+		#endif
+
+		/* copy mesh confirm IEs */
+		if (mpm_info.pid_v == 1) /* not include MIC & encrypted AMPE */
+			ies_len = (mic_ie - fhead) - sizeof(struct rtw_ieee80211_hdr_3addr) - 2;
+		else
+			ies_len = flen - sizeof(struct rtw_ieee80211_hdr_3addr) - 2;
+
+		ies = rtw_zmalloc(ies_len);
+		if (ies) {
+			_rtw_memcpy(ies, fhead + sizeof(struct rtw_ieee80211_hdr_3addr) + 2, ies_len);
+			if (tx == _FALSE) {
+				plink->rx_conf_ies = ies;
+				plink->rx_conf_ies_len = ies_len;
+			}
+			#ifdef CONFIG_RTW_MESH_DRIVER_AID	
+			else {
+				plink->tx_conf_ies = ies;
+				plink->tx_conf_ies_len = ies_len;
+			}
+			#endif
+		}
+
+release_plink_ctl:
+		_exit_critical_bh(&(plink_ctl->lock), &irqL);
+	}
+
+mpm_log:
+	rtw_mpm_info_msg(&mpm_info, mpm_log_buf);
+	RTW_INFO("RTW_%s:%s %s\n"
+		, (tx == _TRUE) ? "Tx" : "Rx"
+		, action_self_protected_str(action)
+		, mpm_log_buf
+	);
+
+	ret = 1;
+
+exit:
+	if (nbuf) {
+		if (ret == 1) {
+			*buf = nbuf;
+			*len = nlen;
+		} else
+			rtw_mfree(nbuf, nlen);
+	}
+
+	return ret;
+}
+
+static int rtw_mesh_check_frames(_adapter *adapter, const u8 **buf, size_t *len, u8 tx)
+{
+	int is_mesh_frame = -1;
+	const u8 *frame_body;
+	u8 category, action;
+
+	frame_body = *buf + sizeof(struct rtw_ieee80211_hdr_3addr);
+	category = frame_body[0];
+
+	if (category == RTW_WLAN_CATEGORY_SELF_PROTECTED) {
+		action = frame_body[1];
+		switch (action) {
+		case RTW_ACT_SELF_PROTECTED_MESH_OPEN:
+		case RTW_ACT_SELF_PROTECTED_MESH_CONF:
+		case RTW_ACT_SELF_PROTECTED_MESH_CLOSE:
+			rtw_mpm_check_frames(adapter, action, buf, len, tx);
+			is_mesh_frame = action;
+			break;
+		case RTW_ACT_SELF_PROTECTED_MESH_GK_INFORM:
+		case RTW_ACT_SELF_PROTECTED_MESH_GK_ACK:
+			RTW_INFO("RTW_%s:%s\n", (tx == _TRUE) ? "Tx" : "Rx", action_self_protected_str(action));
+			is_mesh_frame = action;
+			break;
+		default:
+			break;
+		};
+	}
+
+exit:
+	return is_mesh_frame;
+}
+
+int rtw_mesh_check_frames_tx(_adapter *adapter, const u8 **buf, size_t *len)
+{
+	return rtw_mesh_check_frames(adapter, buf, len, _TRUE);
+}
+
+int rtw_mesh_check_frames_rx(_adapter *adapter, const u8 *buf, size_t len)
+{
+	return rtw_mesh_check_frames(adapter, &buf, &len, _FALSE);
+}
+
+int rtw_mesh_on_auth(_adapter *adapter, union recv_frame *rframe)
+{
+	u8 *whdr = rframe->u.hdr.rx_data;
+
+#if CONFIG_RTW_MACADDR_ACL
+	if (rtw_access_ctrl(adapter, get_addr2_ptr(whdr)) == _FALSE)
+		return _SUCCESS;
+#endif
+
+	if (!rtw_mesh_plink_get(adapter, get_addr2_ptr(whdr))) {
+		#if CONFIG_RTW_MESH_ACNODE_PREVENT
+		rtw_mesh_acnode_set_notify_etime(adapter, whdr);
+		#endif
+
+		if (adapter_to_rfctl(adapter)->offch_state == OFFCHS_NONE)
+			issue_probereq(adapter, &adapter->mlmepriv.cur_network.network.mesh_id, get_addr2_ptr(whdr));
+
+		/* only peer being added (checked by notify conditions) is allowed */
+		return _SUCCESS;
+	}
+
+	rtw_cfg80211_rx_mframe(adapter, rframe, NULL);
+	return _SUCCESS;
+}
+
+unsigned int on_action_self_protected(_adapter *adapter, union recv_frame *rframe)
+{
+	unsigned int ret = _FAIL;
+	struct sta_info *sta = NULL;
+	u8 *pframe = rframe->u.hdr.rx_data;
+	uint frame_len = rframe->u.hdr.len;
+	u8 *frame_body = (u8 *)(pframe + sizeof(struct rtw_ieee80211_hdr_3addr));
+	u8 category;
+	u8 action;
+
+	/* check RA matches or not */
+	if (!_rtw_memcmp(adapter_mac_addr(adapter), GetAddr1Ptr(pframe), ETH_ALEN))
+		goto exit;
+
+	category = frame_body[0];
+	if (category != RTW_WLAN_CATEGORY_SELF_PROTECTED)
+		goto exit;
+
+	action = frame_body[1];
+	switch (action) {
+	case RTW_ACT_SELF_PROTECTED_MESH_OPEN:
+	case RTW_ACT_SELF_PROTECTED_MESH_CONF:
+	case RTW_ACT_SELF_PROTECTED_MESH_CLOSE:
+	case RTW_ACT_SELF_PROTECTED_MESH_GK_INFORM:
+	case RTW_ACT_SELF_PROTECTED_MESH_GK_ACK:
+		if (!(MLME_IS_MESH(adapter) && MLME_IS_ASOC(adapter)))
+			goto exit;
+#ifdef CONFIG_IOCTL_CFG80211
+		#if CONFIG_RTW_MACADDR_ACL
+		if (rtw_access_ctrl(adapter, get_addr2_ptr(pframe)) == _FALSE)
+			goto exit;
+		#endif
+		#if CONFIG_RTW_MESH_CTO_MGATE_BLACKLIST
+		if (rtw_mesh_cto_mgate_required(adapter)
+			/* only peer being added (checked by notify conditions) is allowed */
+			&& !rtw_mesh_plink_get(adapter, get_addr2_ptr(pframe)))
+			goto exit;
+		#endif
+		rtw_cfg80211_rx_action(adapter, rframe, NULL);
+		ret = _SUCCESS;
+#endif /* CONFIG_IOCTL_CFG80211 */
+		break;
+	default:
+		break;
+	}
+
+exit:
+	return ret;
+}
+
+const u8 ae_to_mesh_ctrl_len[] = {
+	6,
+	12, /* MESH_FLAGS_AE_A4 */
+	18, /* MESH_FLAGS_AE_A5_A6 */
+	0,
+};
+
+unsigned int on_action_mesh(_adapter *adapter, union recv_frame *rframe)
+{
+	unsigned int ret = _FAIL;
+	struct sta_info *sta = NULL;
+	struct sta_priv *stapriv = &adapter->stapriv;
+	u8 *pframe = rframe->u.hdr.rx_data;
+	uint frame_len = rframe->u.hdr.len;
+	u8 *frame_body = (u8 *)(pframe + sizeof(struct rtw_ieee80211_hdr_3addr));
+	u8 category;
+	u8 action;
+
+	if (!MLME_IS_MESH(adapter))
+		goto exit;
+
+	/* check stainfo exist? */
+
+	category = frame_body[0];
+	if (category != RTW_WLAN_CATEGORY_MESH)
+		goto exit;
+
+	action = frame_body[1];
+	switch (action) {
+	case RTW_ACT_MESH_HWMP_PATH_SELECTION:
+		rtw_mesh_rx_path_sel_frame(adapter, rframe);
+		ret = _SUCCESS;
+		break;
+	default:
+		break;
+	}
+
+exit:
+	return ret;
+}
+
+bool rtw_mesh_update_bss_peering_status(_adapter *adapter, WLAN_BSSID_EX *bss)
+{
+	struct sta_priv *stapriv = &adapter->stapriv;
+	struct rtw_mesh_cfg *mcfg = &adapter->mesh_cfg;
+	struct rtw_mesh_info *minfo = &adapter->mesh_info;
+	struct mesh_plink_pool *plink_ctl = &minfo->plink_ctl;
+	u8 num_of_peerings = stapriv->asoc_list_cnt;
+	bool accept_peerings = stapriv->asoc_list_cnt < mcfg->max_peer_links;
+	u8 *ie;
+	int ie_len;
+	bool updated = 0;
+
+#if CONFIG_RTW_MESH_ACNODE_PREVENT
+	accept_peerings |= plink_ctl->acnode_rsvd;
+#endif
+
+	ie = rtw_get_ie(BSS_EX_TLV_IES(bss), WLAN_EID_MESH_CONFIG, &ie_len, BSS_EX_TLV_IES_LEN(bss));
+	if (!ie || ie_len != 7) {
+		rtw_warn_on(1);
+		goto exit;
+	}
+
+	if (GET_MESH_CONF_ELE_NUM_OF_PEERINGS(ie + 2) != num_of_peerings) {
+		SET_MESH_CONF_ELE_NUM_OF_PEERINGS(ie + 2, num_of_peerings);
+		updated = 1;
+	}
+
+	if (GET_MESH_CONF_ELE_ACCEPT_PEERINGS(ie + 2) != accept_peerings) {
+		SET_MESH_CONF_ELE_ACCEPT_PEERINGS(ie + 2, accept_peerings);
+		updated = 1;
+	}
+
+exit:
+	return updated;
+}
+
+bool rtw_mesh_update_bss_formation_info(_adapter *adapter, WLAN_BSSID_EX *bss)
+{
+	struct rtw_mesh_cfg *mcfg = &adapter->mesh_cfg;
+	struct rtw_mesh_info *minfo = &adapter->mesh_info;
+	u8 cto_mgate = (minfo->num_gates || mcfg->dot11MeshGateAnnouncementProtocol);
+	u8 cto_as = 0;
+	u8 *ie;
+	int ie_len;
+	bool updated = 0;
+
+	ie = rtw_get_ie(BSS_EX_TLV_IES(bss), WLAN_EID_MESH_CONFIG, &ie_len,
+			BSS_EX_TLV_IES_LEN(bss));
+	if (!ie || ie_len != 7) {
+		rtw_warn_on(1);
+		goto exit;
+	}
+
+	if (GET_MESH_CONF_ELE_CTO_MGATE(ie + 2) != cto_mgate) {
+		SET_MESH_CONF_ELE_CTO_MGATE(ie + 2, cto_mgate);
+		updated = 1;
+	}
+
+	if (GET_MESH_CONF_ELE_CTO_AS(ie + 2) != cto_as) {
+		SET_MESH_CONF_ELE_CTO_AS(ie + 2, cto_as);
+		updated = 1;
+	}
+
+exit:
+	return updated;
+}
+
+bool rtw_mesh_update_bss_forwarding_state(_adapter *adapter, WLAN_BSSID_EX *bss)
+{
+	struct rtw_mesh_cfg *mcfg = &adapter->mesh_cfg;
+	u8 forward = mcfg->dot11MeshForwarding;
+	u8 *ie;
+	int ie_len;
+	bool updated = 0;
+
+	ie = rtw_get_ie(BSS_EX_TLV_IES(bss), WLAN_EID_MESH_CONFIG, &ie_len,
+			BSS_EX_TLV_IES_LEN(bss));
+	if (!ie || ie_len != 7) {
+		rtw_warn_on(1);
+		goto exit;
+	}
+
+	if (GET_MESH_CONF_ELE_FORWARDING(ie + 2) != forward) {
+		SET_MESH_CONF_ELE_FORWARDING(ie + 2, forward);
+		updated = 1;
+	}
+
+exit:
+	return updated;
+}
+
+struct mesh_plink_ent *_rtw_mesh_plink_get(_adapter *adapter, const u8 *hwaddr)
+{
+	struct rtw_mesh_info *minfo = &adapter->mesh_info;
+	struct mesh_plink_pool *plink_ctl = &minfo->plink_ctl;
+	struct mesh_plink_ent *ent = NULL;
+	int i;
+
+	for (i = 0; i < RTW_MESH_MAX_PEER_CANDIDATES; i++) {
+		if (plink_ctl->ent[i].valid == _TRUE
+			&& _rtw_memcmp(plink_ctl->ent[i].addr, hwaddr, ETH_ALEN) == _TRUE
+		) {
+			ent = &plink_ctl->ent[i];
+			break;
+		}
+	}
+
+exit:
+	return ent;
+}
+
+struct mesh_plink_ent *rtw_mesh_plink_get(_adapter *adapter, const u8 *hwaddr)
+{
+	struct rtw_mesh_info *minfo = &adapter->mesh_info;
+	struct mesh_plink_pool *plink_ctl = &minfo->plink_ctl;
+	struct mesh_plink_ent *ent = NULL;
+	_irqL irqL;
+
+	_enter_critical_bh(&(plink_ctl->lock), &irqL);
+	ent = _rtw_mesh_plink_get(adapter, hwaddr);
+	_exit_critical_bh(&(plink_ctl->lock), &irqL);
+
+exit:
+	return ent;
+}
+
+struct mesh_plink_ent *rtw_mesh_plink_get_no_estab_by_idx(_adapter *adapter, u8 idx)
+{
+	struct rtw_mesh_info *minfo = &adapter->mesh_info;
+	struct mesh_plink_pool *plink_ctl = &minfo->plink_ctl;
+	struct mesh_plink_ent *ent = NULL;
+	int i, j = 0;
+	_irqL irqL;
+
+	_enter_critical_bh(&(plink_ctl->lock), &irqL);
+	for (i = 0; i < RTW_MESH_MAX_PEER_CANDIDATES; i++) {
+		if (plink_ctl->ent[i].valid == _TRUE
+			&& plink_ctl->ent[i].plink_state != RTW_MESH_PLINK_ESTAB
+		) {
+			if (j == idx) {
+				ent = &plink_ctl->ent[i];
+				break;
+			}
+			j++;
+		}
+	}
+	_exit_critical_bh(&(plink_ctl->lock), &irqL);
+
+	return ent;
+}
+
+int _rtw_mesh_plink_add(_adapter *adapter, const u8 *hwaddr)
+{
+	struct rtw_mesh_info *minfo = &adapter->mesh_info;
+	struct mesh_plink_pool *plink_ctl = &minfo->plink_ctl;
+	struct mesh_plink_ent *ent = NULL;
+	u8 exist = _FALSE;
+	int i;
+
+	for (i = 0; i < RTW_MESH_MAX_PEER_CANDIDATES; i++) {
+		if (plink_ctl->ent[i].valid == _TRUE
+			&& _rtw_memcmp(plink_ctl->ent[i].addr, hwaddr, ETH_ALEN) == _TRUE
+		) {
+			ent = &plink_ctl->ent[i];
+			exist = _TRUE;
+			break;
+		}
+
+		if (ent == NULL && plink_ctl->ent[i].valid == _FALSE)
+			ent = &plink_ctl->ent[i];
+	}
+
+	if (exist == _FALSE && ent) {
+		_rtw_memcpy(ent->addr, hwaddr, ETH_ALEN);
+		ent->valid = _TRUE;
+		#ifdef CONFIG_RTW_MESH_AEK
+		ent->aek_valid = 0;
+		#endif
+		ent->llid = 0;
+		ent->plid = 0;
+		_rtw_memset(ent->chosen_pmk, 0, 16);
+		#ifdef CONFIG_RTW_MESH_AEK
+		_rtw_memset(ent->sel_pcs, 0, 4);
+		_rtw_memset(ent->l_nonce, 0, 32);
+		_rtw_memset(ent->p_nonce, 0, 32);
+		#endif
+		ent->plink_state = RTW_MESH_PLINK_LISTEN;
+		#ifndef CONFIG_RTW_MESH_DRIVER_AID
+		ent->aid = 0;
+		#endif
+		ent->peer_aid = 0;
+		SET_PEER_CONF_DISABLED(ent);
+		SET_CTO_MGATE_CONF_DISABLED(ent);
+		plink_ctl->num++;
+	}
+
+exit:
+	return exist == _TRUE ? RTW_ALREADY : (ent ? _SUCCESS : _FAIL);
+}
+
+int rtw_mesh_plink_add(_adapter *adapter, const u8 *hwaddr)
+{
+	struct rtw_mesh_info *minfo = &adapter->mesh_info;
+	struct mesh_plink_pool *plink_ctl = &minfo->plink_ctl;
+	_irqL irqL;
+	int ret;
+
+	_enter_critical_bh(&(plink_ctl->lock), &irqL);
+	ret = _rtw_mesh_plink_add(adapter, hwaddr);
+	_exit_critical_bh(&(plink_ctl->lock), &irqL);
+
+	return ret;
+}
+
+int rtw_mesh_plink_set_state(_adapter *adapter, const u8 *hwaddr, u8 state)
+{
+	struct rtw_mesh_info *minfo = &adapter->mesh_info;
+	struct mesh_plink_pool *plink_ctl = &minfo->plink_ctl;
+	struct mesh_plink_ent *ent = NULL;
+	_irqL irqL;
+
+	_enter_critical_bh(&(plink_ctl->lock), &irqL);
+	ent = _rtw_mesh_plink_get(adapter, hwaddr);
+	if (ent)
+		ent->plink_state = state;
+	_exit_critical_bh(&(plink_ctl->lock), &irqL);
+
+exit:
+	return ent ? _SUCCESS : _FAIL;
+}
+
+#ifdef CONFIG_RTW_MESH_AEK
+int rtw_mesh_plink_set_aek(_adapter *adapter, const u8 *hwaddr, const u8 *aek)
+{
+	struct rtw_mesh_info *minfo = &adapter->mesh_info;
+	struct mesh_plink_pool *plink_ctl = &minfo->plink_ctl;
+	struct mesh_plink_ent *ent = NULL;
+	_irqL irqL;
+
+	_enter_critical_bh(&(plink_ctl->lock), &irqL);
+	ent = _rtw_mesh_plink_get(adapter, hwaddr);
+	if (ent) {
+		_rtw_memcpy(ent->aek, aek, 32);
+		ent->aek_valid = 1;
+	}
+	_exit_critical_bh(&(plink_ctl->lock), &irqL);
+
+exit:
+	return ent ? _SUCCESS : _FAIL;
+}
+#endif
+
+#if CONFIG_RTW_MESH_PEER_BLACKLIST
+int rtw_mesh_plink_set_peer_conf_timeout(_adapter *adapter, const u8 *hwaddr)
+{
+	struct rtw_mesh_cfg *mcfg = &adapter->mesh_cfg;
+	struct rtw_mesh_info *minfo = &adapter->mesh_info;
+	struct mesh_plink_pool *plink_ctl = &minfo->plink_ctl;
+	struct mesh_plink_ent *ent = NULL;
+	_irqL irqL;
+
+	_enter_critical_bh(&(plink_ctl->lock), &irqL);
+	ent = _rtw_mesh_plink_get(adapter, hwaddr);
+	if (ent) {
+		if (IS_PEER_CONF_DISABLED(ent))
+			SET_PEER_CONF_END_TIME(ent, mcfg->peer_sel_policy.peer_conf_timeout_ms);
+	}
+	_exit_critical_bh(&(plink_ctl->lock), &irqL);
+
+exit:
+	return ent ? _SUCCESS : _FAIL;
+}
+#endif
+
+void _rtw_mesh_plink_del_ent(_adapter *adapter, struct mesh_plink_ent *ent)
+{
+	struct rtw_mesh_info *minfo = &adapter->mesh_info;
+	struct mesh_plink_pool *plink_ctl = &minfo->plink_ctl;
+
+	ent->valid = _FALSE;
+	#ifdef CONFIG_RTW_MESH_DRIVER_AID
+	if (ent->tx_conf_ies && ent->tx_conf_ies_len)
+		rtw_mfree(ent->tx_conf_ies, ent->tx_conf_ies_len);
+	ent->tx_conf_ies = NULL;
+	ent->tx_conf_ies_len = 0;
+	#endif
+	if (ent->rx_conf_ies && ent->rx_conf_ies_len)
+		rtw_mfree(ent->rx_conf_ies, ent->rx_conf_ies_len);
+	ent->rx_conf_ies = NULL;
+	ent->rx_conf_ies_len = 0;
+	if (ent->scanned)
+		ent->scanned = NULL;
+	plink_ctl->num--;
+}
+
+int rtw_mesh_plink_del(_adapter *adapter, const u8 *hwaddr)
+{
+	struct rtw_mesh_info *minfo = &adapter->mesh_info;
+	struct mesh_plink_pool *plink_ctl = &minfo->plink_ctl;
+	struct mesh_plink_ent *ent = NULL;
+	u8 exist = _FALSE;
+	int i;
+	_irqL irqL;
+
+	_enter_critical_bh(&(plink_ctl->lock), &irqL);
+	for (i = 0; i < RTW_MESH_MAX_PEER_CANDIDATES; i++) {
+		if (plink_ctl->ent[i].valid == _TRUE
+			&& _rtw_memcmp(plink_ctl->ent[i].addr, hwaddr, ETH_ALEN) == _TRUE
+		) {
+			ent = &plink_ctl->ent[i];
+			exist = _TRUE;
+			break;
+		}
+	}
+
+	if (exist == _TRUE)
+		_rtw_mesh_plink_del_ent(adapter, ent);
+
+	_exit_critical_bh(&(plink_ctl->lock), &irqL);
+
+exit:
+	return exist == _TRUE ? _SUCCESS : RTW_ALREADY;
+}
+
+void rtw_mesh_plink_ctl_init(_adapter *adapter)
+{
+	struct rtw_mesh_info *minfo = &adapter->mesh_info;
+	struct mesh_plink_pool *plink_ctl = &minfo->plink_ctl;
+	int i;
+
+	_rtw_spinlock_init(&plink_ctl->lock);
+	plink_ctl->num = 0;
+	for (i = 0; i < RTW_MESH_MAX_PEER_CANDIDATES; i++)
+		plink_ctl->ent[i].valid = _FALSE;
+
+#if CONFIG_RTW_MESH_PEER_BLACKLIST
+	_rtw_init_queue(&plink_ctl->peer_blacklist);
+#endif
+#if CONFIG_RTW_MESH_CTO_MGATE_BLACKLIST
+	_rtw_init_queue(&plink_ctl->cto_mgate_blacklist);
+#endif
+}
+
+void rtw_mesh_plink_ctl_deinit(_adapter *adapter)
+{
+	struct rtw_mesh_info *minfo = &adapter->mesh_info;
+	struct mesh_plink_pool *plink_ctl = &minfo->plink_ctl;
+	struct mesh_plink_ent *ent;
+	int i;
+	_irqL irqL;
+
+	_enter_critical_bh(&(plink_ctl->lock), &irqL);
+	for (i = 0; i < RTW_MESH_MAX_PEER_CANDIDATES; i++) {
+		ent = &plink_ctl->ent[i];
+		#ifdef CONFIG_RTW_MESH_DRIVER_AID
+		if (ent->tx_conf_ies && ent->tx_conf_ies_len)
+			rtw_mfree(ent->tx_conf_ies, ent->tx_conf_ies_len);
+		#endif
+		if (ent->rx_conf_ies && ent->rx_conf_ies_len)
+			rtw_mfree(ent->rx_conf_ies, ent->rx_conf_ies_len);
+	}
+	_exit_critical_bh(&(plink_ctl->lock), &irqL);
+
+	_rtw_spinlock_free(&plink_ctl->lock);
+
+#if CONFIG_RTW_MESH_PEER_BLACKLIST
+	rtw_mesh_peer_blacklist_flush(adapter);
+	_rtw_deinit_queue(&plink_ctl->peer_blacklist);
+#endif
+#if CONFIG_RTW_MESH_CTO_MGATE_BLACKLIST
+	rtw_mesh_cto_mgate_blacklist_flush(adapter);
+	_rtw_deinit_queue(&plink_ctl->cto_mgate_blacklist);
+#endif
+}
+
+void dump_mesh_plink_ctl(void *sel, _adapter *adapter)
+{
+	struct rtw_mesh_info *minfo = &adapter->mesh_info;
+	struct mesh_plink_pool *plink_ctl = &minfo->plink_ctl;
+	struct mesh_plink_ent *ent;
+	int i;
+
+	RTW_PRINT_SEL(sel, "num:%u\n", plink_ctl->num);
+	#if CONFIG_RTW_MESH_ACNODE_PREVENT
+	RTW_PRINT_SEL(sel, "acnode_rsvd:%u\n", plink_ctl->acnode_rsvd);
+	#endif
+
+	for (i = 0; i < RTW_MESH_MAX_PEER_CANDIDATES; i++)  {
+		ent = &plink_ctl->ent[i];
+		if (!ent->valid)
+			continue;
+
+		RTW_PRINT_SEL(sel, "\n");
+		RTW_PRINT_SEL(sel, "peer:"MAC_FMT"\n", MAC_ARG(ent->addr));
+		RTW_PRINT_SEL(sel, "plink_state:%s\n", rtw_mesh_plink_str(ent->plink_state));
+
+		#ifdef CONFIG_RTW_MESH_AEK
+		if (ent->aek_valid)
+			RTW_PRINT_SEL(sel, "aek:"KEY_FMT KEY_FMT"\n", KEY_ARG(ent->aek), KEY_ARG(ent->aek + 16));
+		#endif
+
+		RTW_PRINT_SEL(sel, "llid:%u, plid:%u\n", ent->llid, ent->plid);
+		#ifndef CONFIG_RTW_MESH_DRIVER_AID
+		RTW_PRINT_SEL(sel, "aid:%u\n", ent->aid);
+		#endif
+		RTW_PRINT_SEL(sel, "peer_aid:%u\n", ent->peer_aid);
+
+		RTW_PRINT_SEL(sel, "chosen_pmk:"KEY_FMT"\n", KEY_ARG(ent->chosen_pmk));
+
+		#ifdef CONFIG_RTW_MESH_AEK
+		RTW_PRINT_SEL(sel, "sel_pcs:%02x%02x%02x%02x\n"
+			, ent->sel_pcs[0], ent->sel_pcs[1], ent->sel_pcs[2], ent->sel_pcs[3]);
+		RTW_PRINT_SEL(sel, "l_nonce:"KEY_FMT KEY_FMT"\n", KEY_ARG(ent->l_nonce), KEY_ARG(ent->l_nonce + 16));
+		RTW_PRINT_SEL(sel, "p_nonce:"KEY_FMT KEY_FMT"\n", KEY_ARG(ent->p_nonce), KEY_ARG(ent->p_nonce + 16));
+		#endif
+
+		#ifdef CONFIG_RTW_MESH_DRIVER_AID
+		RTW_PRINT_SEL(sel, "tx_conf_ies:%p, len:%u\n", ent->tx_conf_ies, ent->tx_conf_ies_len);
+		#endif
+		RTW_PRINT_SEL(sel, "rx_conf_ies:%p, len:%u\n", ent->rx_conf_ies, ent->rx_conf_ies_len);
+		RTW_PRINT_SEL(sel, "scanned:%p\n", ent->scanned);
+
+		#if CONFIG_RTW_MESH_PEER_BLACKLIST
+		if (!IS_PEER_CONF_DISABLED(ent)) {
+			if (!IS_PEER_CONF_TIMEOUT(ent))
+				RTW_PRINT_SEL(sel, "peer_conf:%d\n", rtw_systime_to_ms(ent->peer_conf_end_time - rtw_get_current_time()));
+			else
+				RTW_PRINT_SEL(sel, "peer_conf:TIMEOUT\n");
+		}
+		#endif
+
+		#if CONFIG_RTW_MESH_CTO_MGATE_BLACKLIST
+		if (!IS_CTO_MGATE_CONF_DISABLED(ent)) {
+			if (!IS_CTO_MGATE_CONF_TIMEOUT(ent))
+				RTW_PRINT_SEL(sel, "cto_mgate_conf:%d\n", rtw_systime_to_ms(ent->cto_mgate_conf_end_time - rtw_get_current_time()));
+			else
+				RTW_PRINT_SEL(sel, "cto_mgate_conf:TIMEOUT\n");
+		}
+		#endif
+	}
+}
+
+/* this function is called with plink_ctl being locked */
+int rtw_mesh_peer_establish(_adapter *adapter, struct mesh_plink_ent *plink, struct sta_info *sta)
+{
+#ifndef DBG_RTW_MESH_PEER_ESTABLISH
+#define DBG_RTW_MESH_PEER_ESTABLISH 0
+#endif
+
+	struct sta_priv *stapriv = &adapter->stapriv;
+	struct rtw_mesh_cfg *mcfg = &adapter->mesh_cfg;
+	struct rtw_mesh_info *minfo = &adapter->mesh_info;
+	struct mesh_plink_pool *plink_ctl = &minfo->plink_ctl;
+	u8 *tlv_ies;
+	u16 tlv_ieslen;
+	struct rtw_ieee802_11_elems elems;
+	_irqL irqL;
+	int i;
+	int ret = _FAIL;
+
+	if (!plink->rx_conf_ies || !plink->rx_conf_ies_len) {
+		RTW_INFO(FUNC_ADPT_FMT" no rx confirm from sta "MAC_FMT"\n"
+			, FUNC_ADPT_ARG(adapter), MAC_ARG(sta->cmn.mac_addr));
+		goto exit;
+	}
+
+	if (plink->rx_conf_ies_len < 4) {
+		RTW_INFO(FUNC_ADPT_FMT" confirm from sta "MAC_FMT" too short\n"
+			, FUNC_ADPT_ARG(adapter), MAC_ARG(sta->cmn.mac_addr));
+		goto exit;
+	}
+
+#ifdef CONFIG_RTW_MESH_DRIVER_AID
+	if (!plink->tx_conf_ies || !plink->tx_conf_ies_len) {
+		RTW_INFO(FUNC_ADPT_FMT" no tx confirm to sta "MAC_FMT"\n"
+			, FUNC_ADPT_ARG(adapter), MAC_ARG(sta->cmn.mac_addr));
+		goto exit;
+	}
+
+	if (plink->tx_conf_ies_len < 4) {
+		RTW_INFO(FUNC_ADPT_FMT" confirm to sta "MAC_FMT" too short\n"
+			, FUNC_ADPT_ARG(adapter), MAC_ARG(sta->cmn.mac_addr));
+		goto exit;
+	}
+#endif
+
+	tlv_ies = plink->rx_conf_ies + 4;
+	tlv_ieslen = plink->rx_conf_ies_len - 4;
+
+	if (DBG_RTW_MESH_PEER_ESTABLISH)
+		dump_ies(RTW_DBGDUMP, tlv_ies, tlv_ieslen);
+
+	if (rtw_ieee802_11_parse_elems(tlv_ies, tlv_ieslen, &elems, 1) == ParseFailed) {
+		RTW_INFO(FUNC_ADPT_FMT" sta "MAC_FMT" sent invalid confirm\n"
+			, FUNC_ADPT_ARG(adapter), MAC_ARG(sta->cmn.mac_addr));
+		goto exit;
+	}
+
+	SET_PEER_CONF_DISABLED(plink);
+	if (rtw_bss_is_cto_mgate(&plink->scanned->network)
+		&& !rtw_bss_is_forwarding(&plink->scanned->network))
+		SET_CTO_MGATE_CONF_END_TIME(plink, mcfg->peer_sel_policy.cto_mgate_conf_timeout_ms);
+	else
+		SET_CTO_MGATE_CONF_DISABLED(plink);
+
+	sta->state &= (~WIFI_FW_AUTH_SUCCESS);
+	sta->state |= WIFI_FW_ASSOC_STATE;
+
+	rtw_ap_parse_sta_capability(adapter, sta, plink->rx_conf_ies);
+
+	if (rtw_ap_parse_sta_supported_rates(adapter, sta, tlv_ies, tlv_ieslen) != _STATS_SUCCESSFUL_)
+		goto exit;
+	
+	if (rtw_ap_parse_sta_security_ie(adapter, sta, &elems) != _STATS_SUCCESSFUL_)
+		goto exit;
+
+	rtw_ap_parse_sta_wmm_ie(adapter, sta, tlv_ies, tlv_ieslen);
+
+	rtw_ap_parse_sta_ht_ie(adapter, sta, &elems);
+	rtw_ap_parse_sta_vht_ie(adapter, sta, &elems);
+
+	/* AID */
+#ifdef CONFIG_RTW_MESH_DRIVER_AID
+	sta->cmn.aid = RTW_GET_LE16(plink->tx_conf_ies + 2);
+#else
+	sta->cmn.aid = plink->aid;
+#endif
+	stapriv->sta_aid[sta->cmn.aid - 1] = sta;
+	RTW_INFO(FUNC_ADPT_FMT" sta "MAC_FMT" aid:%u\n"
+		, FUNC_ADPT_ARG(adapter), MAC_ARG(sta->cmn.mac_addr), sta->cmn.aid);
+
+	sta->state &= (~WIFI_FW_ASSOC_STATE);
+	sta->state |= WIFI_FW_ASSOC_SUCCESS;
+
+	sta->local_mps = RTW_MESH_PS_ACTIVE;
+
+	rtw_ewma_err_rate_init(&sta->metrics.err_rate);
+	rtw_ewma_err_rate_add(&sta->metrics.err_rate, 1);
+	/* init data_rate to 1M */
+	sta->metrics.data_rate = 10;
+
+	_enter_critical_bh(&stapriv->asoc_list_lock, &irqL);
+	if (rtw_is_list_empty(&sta->asoc_list)) {
+		STA_SET_MESH_PLINK(sta, plink);
+		/* TBD: up layer timeout mechanism */
+		/* sta->expire_to = mcfg->plink_timeout / 2; */
+		rtw_list_insert_tail(&sta->asoc_list, &stapriv->asoc_list);
+		stapriv->asoc_list_cnt++;
+	}
+	_exit_critical_bh(&stapriv->asoc_list_lock, &irqL);
+
+	bss_cap_update_on_sta_join(adapter, sta);
+	sta_info_update(adapter, sta);
+	report_add_sta_event(adapter, sta->cmn.mac_addr);
+
+	ret = _SUCCESS;
+
+exit:
+	return ret;
+}
+
+void rtw_mesh_expire_peer_notify(_adapter *adapter, const u8 *peer_addr)
+{
+	u8 null_ssid[2] = {0, 0};
+
+#ifdef CONFIG_IOCTL_CFG80211
+	rtw_cfg80211_notify_new_peer_candidate(adapter->rtw_wdev
+		, peer_addr
+		, null_ssid
+		, 2
+		, GFP_ATOMIC
+	);
+#endif
+
+exit:
+	return;
+}
+
+static u8 *rtw_mesh_construct_peer_mesh_close(_adapter *adapter, struct mesh_plink_ent *plink, u16 reason, u32 *len)
+{
+	struct rtw_mesh_info *minfo = &adapter->mesh_info;
+	u8 *frame = NULL, *pos;
+	u32 flen;
+	struct rtw_ieee80211_hdr *whdr;
+
+	if (minfo->mesh_auth_id && !MESH_PLINK_AEK_VALID(plink))
+		goto exit;
+
+	flen = sizeof(struct rtw_ieee80211_hdr_3addr)
+		+ 2 /* category, action */
+		+ 2 + minfo->mesh_id_len /* mesh id */
+		+ 2 + 8 + (minfo->mesh_auth_id ? 16 : 0) /* mpm */
+		+ (minfo->mesh_auth_id ? 2 + AES_BLOCK_SIZE : 0) /* mic */
+		+ (minfo->mesh_auth_id ? 70 : 0) /* ampe */
+		;
+
+	pos = frame = rtw_zmalloc(flen);
+	if (!frame)
+		goto exit;
+
+	whdr = (struct rtw_ieee80211_hdr *)frame;
+	_rtw_memcpy(whdr->addr1, adapter_mac_addr(adapter), ETH_ALEN);
+	_rtw_memcpy(whdr->addr2, plink->addr, ETH_ALEN);
+	_rtw_memcpy(whdr->addr3, adapter_mac_addr(adapter), ETH_ALEN);
+
+	set_frame_sub_type(frame, WIFI_ACTION);
+
+	pos += sizeof(struct rtw_ieee80211_hdr_3addr);
+	*(pos++) = RTW_WLAN_CATEGORY_SELF_PROTECTED;
+	*(pos++) = RTW_ACT_SELF_PROTECTED_MESH_CLOSE;
+
+	pos = rtw_set_ie_mesh_id(pos, NULL, minfo->mesh_id, minfo->mesh_id_len);
+
+	pos = rtw_set_ie_mpm(pos, NULL
+		, minfo->mesh_auth_id ? 1 : 0
+		, plink->plid
+		, &plink->llid
+		, &reason
+		, minfo->mesh_auth_id ? plink->chosen_pmk : NULL);
+
+#ifdef CONFIG_RTW_MESH_AEK
+	if (minfo->mesh_auth_id) {
+		u8 ampe_buf[70];
+		int enc_ret;
+
+		*pos = WLAN_EID_MIC;
+		*(pos + 1) = AES_BLOCK_SIZE;
+
+		ampe_buf[0] = WLAN_EID_AMPE;
+		ampe_buf[1] = 68;
+		_rtw_memcpy(ampe_buf + 2, plink->sel_pcs, 4);
+		_rtw_memcpy(ampe_buf + 6, plink->p_nonce, 32);
+		_rtw_memcpy(ampe_buf + 38, plink->l_nonce, 32);
+
+		enc_ret = rtw_mpm_ampe_enc(adapter, plink
+			, frame + sizeof(struct rtw_ieee80211_hdr_3addr)
+			, pos, ampe_buf, 1);
+		if (enc_ret != _SUCCESS) {
+			rtw_mfree(frame, flen);
+			frame = NULL;
+			goto exit;
+		}
+	}
+#endif
+
+	*len = flen;
+
+exit:
+	return frame;
+}
+
+void _rtw_mesh_expire_peer_ent(_adapter *adapter, struct mesh_plink_ent *plink)
+{
+#if defined(CONFIG_RTW_MESH_STA_DEL_DISASOC)
+	_rtw_mesh_plink_del_ent(adapter, plink);
+	rtw_cfg80211_indicate_sta_disassoc(adapter, plink->addr, 0);
+#else
+	u8 *frame = NULL;
+	u32 flen;
+
+	if (plink->plink_state == RTW_MESH_PLINK_ESTAB)
+		frame = rtw_mesh_construct_peer_mesh_close(adapter, plink, WLAN_REASON_MESH_CLOSE, &flen);
+
+	if (frame) {
+		struct mlme_ext_priv *mlmeext = &adapter->mlmeextpriv;
+		struct wireless_dev *wdev = adapter->rtw_wdev;
+		s32 freq = rtw_ch2freq(mlmeext->cur_channel);
+
+		#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) || defined(COMPAT_KERNEL_RELEASE)
+		rtw_cfg80211_rx_mgmt(wdev, freq, 0, frame, flen, GFP_ATOMIC);
+		#else
+		cfg80211_rx_action(adapter->pnetdev, freq, frame, flen, GFP_ATOMIC);
+		#endif
+
+		rtw_mfree(frame, flen);
+	} else {
+		rtw_mesh_expire_peer_notify(adapter, plink->addr);
+		RTW_INFO(FUNC_ADPT_FMT" set "MAC_FMT" plink unknown\n"
+			, FUNC_ADPT_ARG(adapter), MAC_ARG(plink->addr));
+		plink->plink_state = RTW_MESH_PLINK_UNKNOWN;
+	}
+#endif
+}
+
+void rtw_mesh_expire_peer(_adapter *adapter, const u8 *peer_addr)
+{
+	struct rtw_mesh_info *minfo = &adapter->mesh_info;
+	struct mesh_plink_pool *plink_ctl = &minfo->plink_ctl;
+	struct mesh_plink_ent *plink;
+	_irqL irqL;
+
+	_enter_critical_bh(&(plink_ctl->lock), &irqL);
+
+	plink = _rtw_mesh_plink_get(adapter, peer_addr);
+	if (!plink)
+		goto exit;
+
+	_rtw_mesh_expire_peer_ent(adapter, plink);
+
+exit:
+	_exit_critical_bh(&(plink_ctl->lock), &irqL);
+}
+
+u8 rtw_mesh_ps_annc(_adapter *adapter, u8 ps)
+{
+	_irqL irqL;
+	_list *head, *list;
+	struct sta_info *sta;
+	struct sta_priv *stapriv = &adapter->stapriv;
+	u8 sta_alive_num = 0, i;
+	char sta_alive_list[NUM_STA];
+	u8 annc_cnt = 0;
+
+	if (rtw_linked_check(adapter) == _FALSE)
+		goto exit;
+
+	_enter_critical_bh(&stapriv->asoc_list_lock, &irqL);
+
+	head = &stapriv->asoc_list;
+	list = get_next(head);
+	while ((rtw_end_of_queue_search(head, list)) == _FALSE) {
+		int stainfo_offset;
+
+		sta = LIST_CONTAINOR(list, struct sta_info, asoc_list);
+		list = get_next(list);
+
+		stainfo_offset = rtw_stainfo_offset(stapriv, sta);
+		if (stainfo_offset_valid(stainfo_offset))
+			sta_alive_list[sta_alive_num++] = stainfo_offset;
+	}
+	_exit_critical_bh(&stapriv->asoc_list_lock, &irqL);
+
+	for (i = 0; i < sta_alive_num; i++) {
+		sta = rtw_get_stainfo_by_offset(stapriv, sta_alive_list[i]);
+		if (!sta)
+			continue;
+
+		issue_qos_nulldata(adapter, sta->cmn.mac_addr, 7, ps, 3, 500);
+		annc_cnt++;
+	}
+
+exit:
+	return annc_cnt;
+}
+
+static void mpath_tx_tasklet_hdl(void *priv)
+{
+	_adapter *adapter = (_adapter *)priv;
+	struct rtw_mesh_info *minfo = &adapter->mesh_info;
+	struct xmit_frame *xframe;
+	_list *list, *head;
+	_list tmp;
+	u32 tmp_len;
+	s32 res;
+
+	_rtw_init_listhead(&tmp);
+
+	while (1) {
+		tmp_len = 0;
+		enter_critical_bh(&minfo->mpath_tx_queue.lock);
+		if (minfo->mpath_tx_queue_len) {
+			rtw_list_splice_init(&minfo->mpath_tx_queue.queue, &tmp);
+			tmp_len = minfo->mpath_tx_queue_len;
+			minfo->mpath_tx_queue_len = 0;
+		}
+		exit_critical_bh(&minfo->mpath_tx_queue.lock);
+
+		if (!tmp_len)
+			break;
+
+		head = &tmp;
+		list = get_next(head);
+		while (rtw_end_of_queue_search(head, list) == _FALSE) {
+			xframe = LIST_CONTAINOR(list, struct xmit_frame, list);
+			list = get_next(list);
+			rtw_list_delete(&xframe->list);
+			res = rtw_xmit_posthandle(adapter, xframe, xframe->pkt);
+			if (res < 0) {
+				#ifdef DBG_TX_DROP_FRAME
+				RTW_INFO("DBG_TX_DROP_FRAME %s rtw_xmit fail\n", __FUNCTION__);
+				#endif
+				adapter->xmitpriv.tx_drop++;
+			}
+		}
+	}
+}
+
+static void rtw_mpath_tx_queue_flush(_adapter *adapter)
+{
+	struct rtw_mesh_info *minfo = &adapter->mesh_info;
+	struct xmit_frame *xframe;
+	_list *list, *head;
+	_list tmp;
+
+	_rtw_init_listhead(&tmp);
+
+	enter_critical_bh(&minfo->mpath_tx_queue.lock);
+	rtw_list_splice_init(&minfo->mpath_tx_queue.queue, &tmp);
+	minfo->mpath_tx_queue_len = 0;
+	exit_critical_bh(&minfo->mpath_tx_queue.lock);
+
+	head = &tmp;
+	list = get_next(head);
+	while (rtw_end_of_queue_search(head, list) == _FALSE) {
+		xframe = LIST_CONTAINOR(list, struct xmit_frame, list);
+		list = get_next(list);
+		rtw_list_delete(&xframe->list);
+		rtw_free_xmitframe(&adapter->xmitpriv, xframe);
+	}
+}
+
+#ifdef PLATFORM_LINUX /* 3.10 ~ 4.13 checked */
+#if defined(CONFIG_SLUB)
+#include <linux/slub_def.h>
+#elif defined(CONFIG_SLAB)
+#include <linux/slab_def.h>
+#endif
+typedef struct kmem_cache rtw_mcache;
+#endif
+
+rtw_mcache *rtw_mcache_create(const char *name, size_t size)
+{
+#ifdef PLATFORM_LINUX /* 3.10 ~ 4.13 checked */
+	return kmem_cache_create(name, size, 0, 0, NULL);
+#else
+	#error "TBD\n";
+#endif
+}
+
+void rtw_mcache_destroy(rtw_mcache *s)
+{
+#ifdef PLATFORM_LINUX /* 3.10 ~ 4.13 checked */
+	kmem_cache_destroy(s);
+#else
+	#error "TBD\n";
+#endif
+}
+
+void *_rtw_mcache_alloc(rtw_mcache *cachep)
+{
+#ifdef PLATFORM_LINUX /* 3.10 ~ 4.13 checked */
+	return kmem_cache_alloc(cachep, GFP_ATOMIC);
+#else
+	#error "TBD\n";
+#endif
+}
+
+void _rtw_mcache_free(rtw_mcache *cachep, void *objp)
+{
+#ifdef PLATFORM_LINUX /* 3.10 ~ 4.13 checked */
+	kmem_cache_free(cachep, objp);
+#else
+	#error "TBD\n";
+#endif
+}
+
+#ifdef DBG_MEM_ALLOC
+inline void *dbg_rtw_mcache_alloc(rtw_mcache *cachep, const enum mstat_f flags, const char *func, const int line)
+{
+	void *p;
+	u32 sz = cachep->size;
+
+	if (match_mstat_sniff_rules(flags, sz))
+		RTW_INFO("DBG_MEM_ALLOC %s:%d %s(%u)\n", func, line, __func__, sz);
+
+	p = _rtw_mcache_alloc(cachep);
+
+	rtw_mstat_update(
+		flags
+		, p ? MSTAT_ALLOC_SUCCESS : MSTAT_ALLOC_FAIL
+		, sz
+	);
+
+	return p;
+}
+
+inline void dbg_rtw_mcache_free(rtw_mcache *cachep, void *pbuf, const enum mstat_f flags, const char *func, const int line)
+{
+	u32 sz = cachep->size;
+
+	if (match_mstat_sniff_rules(flags, sz))
+		RTW_INFO("DBG_MEM_ALLOC %s:%d %s(%u)\n", func, line, __func__, sz);
+
+	_rtw_mcache_free(cachep, pbuf);
+
+	rtw_mstat_update(
+		flags
+		, MSTAT_FREE
+		, sz
+	);
+}
+
+#define rtw_mcache_alloc(cachep) dbg_rtw_mcache_alloc(cachep, MSTAT_TYPE_PHY, __FUNCTION__, __LINE__)
+#define rtw_mcache_free(cachep, objp) dbg_rtw_mcache_free(cachep, objp, MSTAT_TYPE_PHY, __FUNCTION__, __LINE__)
+#else
+#define rtw_mcache_alloc(cachep) _rtw_mcache_alloc(cachep)
+#define rtw_mcache_free(cachep, objp) _rtw_mcache_free(cachep, objp)
+#endif /* DBG_MEM_ALLOC */
+
+/* Mesh Received Cache */
+#define RTW_MRC_BUCKETS			256 /* must be a power of 2 */
+#define RTW_MRC_QUEUE_MAX_LEN	4
+#define RTW_MRC_TIMEOUT_MS		(3 * 1000)
+
+/**
+ * struct rtw_mrc_entry - entry in the Mesh Received Cache
+ *
+ * @seqnum: mesh sequence number of the frame
+ * @exp_time: expiration time of the entry
+ * @msa: mesh source address of the frame
+ * @list: hashtable list pointer
+ *
+ * The Mesh Received Cache keeps track of the latest received frames that
+ * have been received by a mesh interface and discards received frames
+ * that are found in the cache.
+ */
+struct rtw_mrc_entry {
+	rtw_hlist_node list;
+	systime exp_time;
+	u32 seqnum;
+	u8 msa[ETH_ALEN];
+};
+
+struct rtw_mrc {
+	rtw_hlist_head bucket[RTW_MRC_BUCKETS];
+	u32 idx_mask;
+	rtw_mcache *cache;
+};
+
+static int rtw_mrc_init(_adapter *adapter)
+{
+	struct rtw_mesh_info *minfo = &adapter->mesh_info;
+	char cache_name[IFNAMSIZ + 8 + 1];
+	int i;
+
+	minfo->mrc = rtw_malloc(sizeof(struct rtw_mrc));
+	if (!minfo->mrc)
+		return -ENOMEM;
+	minfo->mrc->idx_mask = RTW_MRC_BUCKETS - 1;
+	for (i = 0; i < RTW_MRC_BUCKETS; i++)
+		rtw_hlist_head_init(&minfo->mrc->bucket[i]);
+
+	sprintf(cache_name, "rtw_mrc_%s", ADPT_ARG(adapter));
+	minfo->mrc->cache = rtw_mcache_create(cache_name, sizeof(struct rtw_mrc_entry));
+
+	return 0;
+}
+
+static void rtw_mrc_free(_adapter *adapter)
+{
+	struct rtw_mesh_info *minfo = &adapter->mesh_info;
+	struct rtw_mrc *mrc = minfo->mrc;
+	struct rtw_mrc_entry *p;
+	rtw_hlist_node *np, *n;
+	int i;
+
+	if (!mrc)
+		return;
+
+	for (i = 0; i < RTW_MRC_BUCKETS; i++) {
+		rtw_hlist_for_each_entry_safe(p, np, n, &mrc->bucket[i], list) {
+			rtw_hlist_del(&p->list);
+			rtw_mcache_free(mrc->cache, p);
+		}
+	}
+
+	rtw_mcache_destroy(mrc->cache);
+
+	rtw_mfree(mrc, sizeof(struct rtw_mrc));
+	minfo->mrc = NULL;
+}
+
+/**
+ * rtw_mrc_check - Check frame in mesh received cache and add if absent.
+ *
+ * @adapter:	interface
+ * @msa:		mesh source address
+ * @seq:		mesh seq number
+ *
+ * Returns: 0 if the frame is not in the cache, nonzero otherwise.
+ *
+ * Checks using the mesh source address and the mesh sequence number if we have
+ * received this frame lately. If the frame is not in the cache, it is added to
+ * it.
+ */
+static int rtw_mrc_check(_adapter *adapter, const u8 *msa, u32 seq)
+{
+	struct rtw_mesh_info *minfo = &adapter->mesh_info;
+	struct rtw_mrc *mrc = minfo->mrc;
+	int entries = 0;
+	u8 idx;
+	struct rtw_mrc_entry *p;
+	rtw_hlist_node *np, *n;
+	u8 timeout;
+
+	if (!mrc)
+		return -1;
+
+	idx = seq & mrc->idx_mask;
+	rtw_hlist_for_each_entry_safe(p, np, n, &mrc->bucket[idx], list) {
+		++entries;
+		timeout = rtw_time_after(rtw_get_current_time(), p->exp_time);
+		if (timeout || entries == RTW_MRC_QUEUE_MAX_LEN) {
+			if (!timeout)
+				minfo->mshstats.mrc_del_qlen++;
+
+			rtw_hlist_del(&p->list);
+			rtw_mcache_free(mrc->cache, p);
+			--entries;
+		} else if ((seq == p->seqnum) && _rtw_memcmp(msa, p->msa, ETH_ALEN) == _TRUE)
+			return -1;
+	}
+
+	p = rtw_mcache_alloc(mrc->cache);
+	if (!p)
+		return 0;
+
+	p->seqnum = seq;
+	p->exp_time = rtw_get_current_time() + rtw_ms_to_systime(RTW_MRC_TIMEOUT_MS);
+	_rtw_memcpy(p->msa, msa, ETH_ALEN);
+	rtw_hlist_add_head(&p->list, &mrc->bucket[idx]);
+	return 0;
+}
+
+static int rtw_mesh_decache(_adapter *adapter, const u8 *msa, u32 seq)
+{
+	return rtw_mrc_check(adapter, msa, seq);
+}
+
+#ifndef RTW_MESH_SCAN_RESULT_EXP_MS
+#define RTW_MESH_SCAN_RESULT_EXP_MS (10 * 1000)
+#endif
+
+#ifndef RTW_MESH_ACNODE_PREVENT
+#define RTW_MESH_ACNODE_PREVENT 0
+#endif
+#ifndef RTW_MESH_ACNODE_CONF_TIMEOUT_MS
+#define RTW_MESH_ACNODE_CONF_TIMEOUT_MS (20 * 1000)
+#endif
+#ifndef RTW_MESH_ACNODE_NOTIFY_TIMEOUT_MS
+#define RTW_MESH_ACNODE_NOTIFY_TIMEOUT_MS (2 * 1000)
+#endif
+
+#ifndef RTW_MESH_OFFCH_CAND
+#define RTW_MESH_OFFCH_CAND 1
+#endif
+#ifndef RTW_MESH_OFFCH_CAND_FIND_INT_MS
+#define RTW_MESH_OFFCH_CAND_FIND_INT_MS (10 * 1000)
+#endif
+
+#ifndef RTW_MESH_PEER_CONF_TIMEOUT_MS
+#define RTW_MESH_PEER_CONF_TIMEOUT_MS (20 * 1000)
+#endif
+#ifndef RTW_MESH_PEER_BLACKLIST_TIMEOUT_MS
+#define RTW_MESH_PEER_BLACKLIST_TIMEOUT_MS (20 * 1000)
+#endif
+
+#ifndef RTW_MESH_CTO_MGATE_REQUIRE
+#define RTW_MESH_CTO_MGATE_REQUIRE 0
+#endif
+#ifndef RTW_MESH_CTO_MGATE_CONF_TIMEOUT_MS
+#define RTW_MESH_CTO_MGATE_CONF_TIMEOUT_MS (20 * 1000)
+#endif
+#ifndef RTW_MESH_CTO_MGATE_BLACKLIST_TIMEOUT_MS
+#define RTW_MESH_CTO_MGATE_BLACKLIST_TIMEOUT_MS (20 * 1000)
+#endif
+
+void rtw_mesh_cfg_init_peer_sel_policy(struct rtw_mesh_cfg *mcfg)
+{
+	struct mesh_peer_sel_policy *sel_policy = &mcfg->peer_sel_policy;
+
+	sel_policy->scanr_exp_ms = RTW_MESH_SCAN_RESULT_EXP_MS;
+
+#if CONFIG_RTW_MESH_ACNODE_PREVENT
+	sel_policy->acnode_prevent = RTW_MESH_ACNODE_PREVENT;
+	sel_policy->acnode_conf_timeout_ms = RTW_MESH_ACNODE_CONF_TIMEOUT_MS;
+	sel_policy->acnode_notify_timeout_ms = RTW_MESH_ACNODE_NOTIFY_TIMEOUT_MS;
+#endif
+
+#if CONFIG_RTW_MESH_OFFCH_CAND
+	sel_policy->offch_cand = RTW_MESH_OFFCH_CAND;
+	sel_policy->offch_find_int_ms = RTW_MESH_OFFCH_CAND_FIND_INT_MS;
+#endif
+
+#if CONFIG_RTW_MESH_PEER_BLACKLIST
+	sel_policy->peer_conf_timeout_ms = RTW_MESH_PEER_CONF_TIMEOUT_MS;
+	sel_policy->peer_blacklist_timeout_ms = RTW_MESH_PEER_BLACKLIST_TIMEOUT_MS;
+#endif
+
+#if CONFIG_RTW_MESH_CTO_MGATE_BLACKLIST
+	sel_policy->cto_mgate_require = RTW_MESH_CTO_MGATE_REQUIRE;
+	sel_policy->cto_mgate_conf_timeout_ms = RTW_MESH_CTO_MGATE_CONF_TIMEOUT_MS;
+	sel_policy->cto_mgate_blacklist_timeout_ms = RTW_MESH_CTO_MGATE_BLACKLIST_TIMEOUT_MS;
+#endif
+}
+
+void rtw_mesh_cfg_init(_adapter *adapter)
+{
+	struct rtw_mesh_cfg *mcfg = &adapter->mesh_cfg;
+
+	mcfg->max_peer_links = RTW_MESH_MAX_PEER_LINKS;
+	mcfg->plink_timeout = RTW_MESH_PEER_LINK_TIMEOUT;
+
+	mcfg->dot11MeshTTL = RTW_MESH_TTL;
+	mcfg->element_ttl = RTW_MESH_DEFAULT_ELEMENT_TTL;
+	mcfg->dot11MeshHWMPmaxPREQretries = RTW_MESH_MAX_PREQ_RETRIES;
+	mcfg->path_refresh_time = RTW_MESH_PATH_REFRESH_TIME;
+	mcfg->min_discovery_timeout = RTW_MESH_MIN_DISCOVERY_TIMEOUT;
+	mcfg->dot11MeshHWMPactivePathTimeout = RTW_MESH_PATH_TIMEOUT;
+	mcfg->dot11MeshHWMPpreqMinInterval = RTW_MESH_PREQ_MIN_INT;
+	mcfg->dot11MeshHWMPperrMinInterval = RTW_MESH_PERR_MIN_INT;
+	mcfg->dot11MeshHWMPnetDiameterTraversalTime = RTW_MESH_DIAM_TRAVERSAL_TIME;
+	mcfg->dot11MeshHWMPRootMode = RTW_IEEE80211_ROOTMODE_NO_ROOT;
+	mcfg->dot11MeshHWMPRannInterval = RTW_MESH_RANN_INTERVAL;
+	mcfg->dot11MeshGateAnnouncementProtocol = _FALSE;
+	mcfg->dot11MeshForwarding = _TRUE;
+	mcfg->rssi_threshold = 0;
+	mcfg->dot11MeshHWMPactivePathToRootTimeout = RTW_MESH_PATH_TO_ROOT_TIMEOUT;
+	mcfg->dot11MeshHWMProotInterval = RTW_MESH_ROOT_INTERVAL;
+	mcfg->dot11MeshHWMPconfirmationInterval = RTW_MESH_ROOT_CONFIRMATION_INTERVAL;
+	mcfg->path_gate_timeout_factor = 3;
+	rtw_mesh_cfg_init_peer_sel_policy(mcfg);
+#ifdef CONFIG_RTW_MESH_ADD_ROOT_CHK
+	mcfg->sane_metric_delta = RTW_MESH_SANE_METRIC_DELTA;
+	mcfg->max_root_add_chk_cnt = RTW_MESH_MAX_ROOT_ADD_CHK_CNT;
+#endif
+
+#if CONFIG_RTW_MESH_DATA_BMC_TO_UC
+	mcfg->b2u_flags_msrc = 0;
+	mcfg->b2u_flags_mfwd = RTW_MESH_B2U_GA_UCAST;
+#endif
+}
+
+void rtw_mesh_cfg_init_max_peer_links(_adapter *adapter, u8 stack_conf)
+{
+	struct rtw_mesh_cfg *mcfg = &adapter->mesh_cfg;
+
+	mcfg->max_peer_links = RTW_MESH_MAX_PEER_LINKS;
+
+	if (mcfg->max_peer_links > stack_conf)
+		mcfg->max_peer_links = stack_conf;
+}
+
+void rtw_mesh_cfg_init_plink_timeout(_adapter *adapter, u32 stack_conf)
+{
+	struct rtw_mesh_cfg *mcfg = &adapter->mesh_cfg;
+
+	mcfg->plink_timeout = stack_conf;
+}
+
+void rtw_mesh_init_mesh_info(_adapter *adapter)
+{
+	struct rtw_mesh_info *minfo = &adapter->mesh_info;
+
+	_rtw_memset(minfo, 0, sizeof(struct rtw_mesh_info));
+
+	rtw_mesh_plink_ctl_init(adapter);
+	
+	minfo->last_preq = rtw_get_current_time();
+	/* minfo->last_sn_update = rtw_get_current_time(); */
+	minfo->next_perr = rtw_get_current_time();
+	
+	ATOMIC_SET(&minfo->mpaths, 0);
+	rtw_mesh_pathtbl_init(adapter);
+
+	_rtw_init_queue(&minfo->mpath_tx_queue);
+	tasklet_init(&minfo->mpath_tx_tasklet
+		, (void(*)(unsigned long))mpath_tx_tasklet_hdl
+		, (unsigned long)adapter);
+
+	rtw_mrc_init(adapter);
+
+	_rtw_init_listhead(&minfo->preq_queue.list);
+	_rtw_spinlock_init(&minfo->mesh_preq_queue_lock);
+	
+	rtw_init_timer(&adapter->mesh_path_timer, adapter, rtw_ieee80211_mesh_path_timer, adapter);
+	rtw_init_timer(&adapter->mesh_path_root_timer, adapter, rtw_ieee80211_mesh_path_root_timer, adapter);
+	rtw_init_timer(&adapter->mesh_atlm_param_req_timer, adapter, rtw_mesh_atlm_param_req_timer, adapter);
+	_init_workitem(&adapter->mesh_work, rtw_mesh_work_hdl, NULL);
+}
+
+void rtw_mesh_deinit_mesh_info(_adapter *adapter)
+{
+	struct rtw_mesh_info *minfo = &adapter->mesh_info;
+
+	tasklet_kill(&minfo->mpath_tx_tasklet);
+	rtw_mpath_tx_queue_flush(adapter);
+	_rtw_deinit_queue(&adapter->mesh_info.mpath_tx_queue);
+
+	rtw_mrc_free(adapter);
+
+	rtw_mesh_pathtbl_unregister(adapter);
+
+	rtw_mesh_plink_ctl_deinit(adapter);
+
+	_cancel_workitem_sync(&adapter->mesh_work);
+	_cancel_timer_ex(&adapter->mesh_path_timer);
+	_cancel_timer_ex(&adapter->mesh_path_root_timer);
+	_cancel_timer_ex(&adapter->mesh_atlm_param_req_timer);
+}
+
+/**
+ * rtw_mesh_nexthop_resolve - lookup next hop; conditionally start path discovery
+ *
+ * @skb: 802.11 frame to be sent
+ * @sdata: network subif the frame will be sent through
+ *
+ * Lookup next hop for given skb and start path discovery if no
+ * forwarding information is found.
+ *
+ * Returns: 0 if the next hop was found and -ENOENT if the frame was queued.
+ * skb is freeed here if no mpath could be allocated.
+ */
+int rtw_mesh_nexthop_resolve(_adapter *adapter,
+			struct xmit_frame *xframe)
+{
+	struct pkt_attrib *attrib = &xframe->attrib;
+	struct rtw_mesh_path *mpath;
+	struct xmit_frame *xframe_to_free = NULL;
+	u8 *target_addr = attrib->mda;
+	int err = 0;
+	int ret = _SUCCESS;
+
+	rtw_rcu_read_lock();
+	err = rtw_mesh_nexthop_lookup(adapter, target_addr, attrib->msa, attrib->ra);
+	if (!err)
+		goto endlookup;
+
+	/* no nexthop found, start resolving */
+	mpath = rtw_mesh_path_lookup(adapter, target_addr);
+	if (!mpath) {
+		mpath = rtw_mesh_path_add(adapter, target_addr);
+		if (IS_ERR(mpath)) {
+			xframe->pkt = NULL; /* free pkt outside */
+			rtw_mesh_path_discard_frame(adapter, xframe);
+			err = PTR_ERR(mpath);
+			ret = _FAIL;
+			goto endlookup;
+		}
+	}
+
+	if (!(mpath->flags & RTW_MESH_PATH_RESOLVING))
+		rtw_mesh_queue_preq(mpath, RTW_PREQ_Q_F_START);
+
+	enter_critical_bh(&mpath->frame_queue.lock);
+
+	if (mpath->frame_queue_len >= RTW_MESH_FRAME_QUEUE_LEN) {
+		xframe_to_free = LIST_CONTAINOR(get_next(get_list_head(&mpath->frame_queue)), struct xmit_frame, list);
+		rtw_list_delete(&(xframe_to_free->list));
+		mpath->frame_queue_len--;
+	}
+
+	rtw_list_insert_tail(&xframe->list, get_list_head(&mpath->frame_queue));
+	mpath->frame_queue_len++;
+
+	exit_critical_bh(&mpath->frame_queue.lock);
+
+	ret = RTW_RA_RESOLVING;
+	if (xframe_to_free)
+		rtw_mesh_path_discard_frame(adapter, xframe_to_free);
+
+endlookup:
+	rtw_rcu_read_unlock();
+	return ret;
+}
+
+/**
+ * rtw_mesh_nexthop_lookup - put the appropriate next hop on a mesh frame. Calling
+ * this function is considered "using" the associated mpath, so preempt a path
+ * refresh if this mpath expires soon.
+ *
+ * @skb: 802.11 frame to be sent
+ * @sdata: network subif the frame will be sent through
+ *
+ * Returns: 0 if the next hop was found. Nonzero otherwise.
+ */
+int rtw_mesh_nexthop_lookup(_adapter *adapter,
+	const u8 *mda, const u8 *msa, u8 *ra)
+{
+	struct rtw_mesh_path *mpath;
+	struct sta_info *next_hop;
+	const u8 *target_addr = mda;
+	int err = -ENOENT;
+
+	rtw_rcu_read_lock();
+	mpath = rtw_mesh_path_lookup(adapter, target_addr);
+
+	if (!mpath || !(mpath->flags & RTW_MESH_PATH_ACTIVE))
+		goto endlookup;
+
+	if (rtw_time_after(rtw_get_current_time(),
+		       mpath->exp_time -
+		       rtw_ms_to_systime(adapter->mesh_cfg.path_refresh_time)) &&
+	    _rtw_memcmp(adapter_mac_addr(adapter), msa, ETH_ALEN) == _TRUE &&
+	    !(mpath->flags & RTW_MESH_PATH_RESOLVING) &&
+	    !(mpath->flags & RTW_MESH_PATH_FIXED)) {
+		rtw_mesh_queue_preq(mpath, RTW_PREQ_Q_F_START | RTW_PREQ_Q_F_REFRESH);
+	}
+
+	next_hop = rtw_rcu_dereference(mpath->next_hop);
+	if (next_hop) {
+		_rtw_memcpy(ra, next_hop->cmn.mac_addr, ETH_ALEN);
+		err = 0;
+	}
+
+endlookup:
+	rtw_rcu_read_unlock();
+	return err;
+}
+
+#if CONFIG_RTW_MESH_DATA_BMC_TO_UC
+static bool rtw_mesh_data_bmc_to_uc(_adapter *adapter
+	, const u8 *da, const u8 *sa, const u8 *mda, const u8 *msa
+	, u8 ae_need, const u8 *ori_ta, u8 mfwd_ttl
+	, _list *b2u_list, u8 *b2u_num, u32 *b2u_mseq)
+{
+	struct sta_priv *stapriv = &adapter->stapriv;
+	struct xmit_priv *xmitpriv = &adapter->xmitpriv;
+	_irqL irqL;
+	_list *head, *list;
+	struct sta_info *sta;
+	char b2u_sta_id[NUM_STA];
+	u8 b2u_sta_num = 0;
+	bool bmc_need = _FALSE;
+	int i;
+
+	_enter_critical_bh(&stapriv->asoc_list_lock, &irqL);
+	head = &stapriv->asoc_list;
+	list = get_next(head);
+
+	while ((rtw_end_of_queue_search(head, list)) == _FALSE) {
+		int stainfo_offset;
+
+		sta = LIST_CONTAINOR(list, struct sta_info, asoc_list);
+		list = get_next(list);
+	
+		stainfo_offset = rtw_stainfo_offset(stapriv, sta);
+		if (stainfo_offset_valid(stainfo_offset))
+			b2u_sta_id[b2u_sta_num++] = stainfo_offset;
+	}
+	_exit_critical_bh(&stapriv->asoc_list_lock, &irqL);
+
+	if (!b2u_sta_num)
+		goto exit;
+
+	for (i = 0; i < b2u_sta_num; i++) {
+		struct xmit_frame *b2uframe;
+		struct pkt_attrib *attrib;
+
+		sta = rtw_get_stainfo_by_offset(stapriv, b2u_sta_id[i]);
+		if (!(sta->state & _FW_LINKED)
+			|| _rtw_memcmp(sta->cmn.mac_addr, msa, ETH_ALEN) == _TRUE
+			|| (ori_ta && _rtw_memcmp(sta->cmn.mac_addr, ori_ta, ETH_ALEN) == _TRUE)
+			|| is_broadcast_mac_addr(sta->cmn.mac_addr)
+			|| is_zero_mac_addr(sta->cmn.mac_addr))
+			continue;
+
+		b2uframe = rtw_alloc_xmitframe(xmitpriv);
+		if (!b2uframe) {
+			bmc_need = _TRUE;
+			break;
+		}
+
+		if ((*b2u_num)++ == 0 && !ori_ta) {
+			*b2u_mseq = (cpu_to_le32(adapter->mesh_info.mesh_seqnum));
+			adapter->mesh_info.mesh_seqnum++;
+		}
+
+		attrib = &b2uframe->attrib;
+
+		attrib->mb2u = 1;
+		attrib->mseq = *b2u_mseq;
+		attrib->mfwd_ttl = ori_ta ? mfwd_ttl : 0;
+		_rtw_memcpy(attrib->ra, sta->cmn.mac_addr, ETH_ALEN);
+		_rtw_memcpy(attrib->ta, adapter_mac_addr(adapter), ETH_ALEN);
+		_rtw_memcpy(attrib->mda, mda, ETH_ALEN);
+		_rtw_memcpy(attrib->msa, msa, ETH_ALEN);
+		_rtw_memcpy(attrib->dst, da, ETH_ALEN);
+		_rtw_memcpy(attrib->src, sa, ETH_ALEN);
+		attrib->mesh_frame_mode = ae_need ? MESH_UCAST_PX_DATA : MESH_UCAST_DATA;
+
+		rtw_list_insert_tail(&b2uframe->list, b2u_list);
+	}
+
+exit:
+	return bmc_need;
+}
+
+void dump_mesh_b2u_flags(void *sel, _adapter *adapter)
+{
+	struct rtw_mesh_cfg *mcfg = &adapter->mesh_cfg;
+
+	RTW_PRINT_SEL(sel, "%4s %4s\n", "msrc", "mfwd");
+	RTW_PRINT_SEL(sel, "0x%02x 0x%02x\n", mcfg->b2u_flags_msrc, mcfg->b2u_flags_mfwd);
+}
+#endif /* CONFIG_RTW_MESH_DATA_BMC_TO_UC */
+
+int rtw_mesh_addr_resolve(_adapter *adapter, struct xmit_frame *xframe, _pkt *pkt, _list *b2u_list)
+{
+	struct pkt_file pktfile;
+	struct ethhdr etherhdr;
+	struct pkt_attrib *attrib;
+	struct rtw_mesh_path *mpath = NULL, *mppath = NULL;
+	u8 is_da_mcast;
+	u8 ae_need;
+#if CONFIG_RTW_MESH_DATA_BMC_TO_UC
+	bool bmc_need = _TRUE;
+	u8 b2u_num = 0;
+	u32 b2u_mseq = 0;
+#endif
+	int res = _SUCCESS;
+
+	_rtw_open_pktfile(pkt, &pktfile);
+	if (_rtw_pktfile_read(&pktfile, (u8 *)&etherhdr, ETH_HLEN) != ETH_HLEN) {
+		res = _FAIL;
+		goto exit;
+	}
+	
+	xframe->pkt = pkt;
+#if CONFIG_RTW_MESH_DATA_BMC_TO_UC
+	_rtw_init_listhead(b2u_list);
+#endif
+
+	is_da_mcast = IS_MCAST(etherhdr.h_dest);
+	if (!is_da_mcast) {
+		struct sta_info *next_hop; 
+		bool mpp_lookup = 1;
+	
+		mpath = rtw_mesh_path_lookup(adapter, etherhdr.h_dest);
+		if (mpath) {
+			mpp_lookup = 0;
+			next_hop = rtw_rcu_dereference(mpath->next_hop);
+			if (!next_hop
+				|| !(mpath->flags & (RTW_MESH_PATH_ACTIVE | RTW_MESH_PATH_RESOLVING))
+			) {
+				/* mpath is not valid, search mppath */
+				mpp_lookup = 1;
+			}
+		}
+
+		if (mpp_lookup) {
+			mppath = rtw_mpp_path_lookup(adapter, etherhdr.h_dest);
+			if (mppath)
+				mppath->exp_time = rtw_get_current_time();
+		}
+
+		if (mppath && mpath)
+			rtw_mesh_path_del(adapter, mpath->dst);
+
+		ae_need = _rtw_memcmp(adapter_mac_addr(adapter), etherhdr.h_source, ETH_ALEN) == _FALSE
+			|| (mppath && _rtw_memcmp(mppath->mpp, etherhdr.h_dest, ETH_ALEN) == _FALSE);
+	} else {
+		ae_need = _rtw_memcmp(adapter_mac_addr(adapter), etherhdr.h_source, ETH_ALEN) == _FALSE;
+
+		#if CONFIG_RTW_MESH_DATA_BMC_TO_UC
+		if (rtw_msrc_b2u_policy_chk(adapter->mesh_cfg.b2u_flags_msrc, etherhdr.h_dest)) {
+			bmc_need = rtw_mesh_data_bmc_to_uc(adapter
+				, etherhdr.h_dest, etherhdr.h_source
+				, etherhdr.h_dest, adapter_mac_addr(adapter), ae_need, NULL, 0
+				, b2u_list, &b2u_num, &b2u_mseq);
+			if (bmc_need == _FALSE) {
+				res = RTW_BMC_NO_NEED;
+				goto exit;
+			}
+		}
+		#endif
+	}
+
+	attrib = &xframe->attrib;
+
+#if CONFIG_RTW_MESH_DATA_BMC_TO_UC
+	if (b2u_num) {
+		attrib->mb2u = 1;
+		attrib->mseq = b2u_mseq;
+	} else
+		attrib->mb2u = 0;
+#endif
+
+	attrib->mfwd_ttl = 0;
+	_rtw_memcpy(attrib->dst, etherhdr.h_dest, ETH_ALEN);
+	_rtw_memcpy(attrib->src, etherhdr.h_source, ETH_ALEN);
+	_rtw_memcpy(attrib->ta, adapter_mac_addr(adapter), ETH_ALEN);
+
+	if (is_da_mcast) {
+		attrib->mesh_frame_mode = ae_need ? MESH_BMCAST_PX_DATA : MESH_BMCAST_DATA;
+		_rtw_memcpy(attrib->ra, attrib->dst, ETH_ALEN);
+		_rtw_memcpy(attrib->msa, adapter_mac_addr(adapter), ETH_ALEN);
+	} else {
+		attrib->mesh_frame_mode = ae_need ? MESH_UCAST_PX_DATA : MESH_UCAST_DATA;
+		_rtw_memcpy(attrib->mda, (mppath && ae_need) ? mppath->mpp : attrib->dst, ETH_ALEN);
+		_rtw_memcpy(attrib->msa, adapter_mac_addr(adapter), ETH_ALEN);
+		/* RA needs to be resolved */
+		res = rtw_mesh_nexthop_resolve(adapter, xframe);
+	}
+
+exit:
+	return res;
+}
+
+s8 rtw_mesh_tx_set_whdr_mctrl_len(u8 mesh_frame_mode, struct pkt_attrib *attrib)
+{
+	u8 ret = 0;
+	switch (mesh_frame_mode) {
+	case MESH_UCAST_DATA:
+		attrib->hdrlen = WLAN_HDR_A4_QOS_LEN;
+		/* mesh flag + mesh TTL + Mesh SN. no ext addr. */
+		attrib->meshctrl_len = 6;
+		break;
+	case MESH_BMCAST_DATA:
+		attrib->hdrlen = WLAN_HDR_A3_QOS_LEN;
+		/* mesh flag + mesh TTL + Mesh SN. no ext addr. */
+		attrib->meshctrl_len = 6;
+		break;
+	case MESH_UCAST_PX_DATA:
+		attrib->hdrlen = WLAN_HDR_A4_QOS_LEN;
+		/* mesh flag + mesh TTL + Mesh SN + extaddr1 + extaddr2. */
+		attrib->meshctrl_len = 18;
+		break;
+	case MESH_BMCAST_PX_DATA:
+		attrib->hdrlen = WLAN_HDR_A3_QOS_LEN;
+		/* mesh flag + mesh TTL + Mesh SN + extaddr1 */
+		attrib->meshctrl_len = 12;
+		break;
+	default:
+		RTW_WARN("Invalid mesh frame mode:%u\n", mesh_frame_mode);
+		ret = -1;
+		break;
+	}				
+
+	return ret;
+}
+
+void rtw_mesh_tx_build_mctrl(_adapter *adapter, struct pkt_attrib *attrib, u8 *buf)
+{
+	struct rtw_ieee80211s_hdr *mctrl = (struct rtw_ieee80211s_hdr *)buf;
+
+	_rtw_memset(mctrl, 0, XATTRIB_GET_MCTRL_LEN(attrib));
+
+	if (attrib->mfwd_ttl
+		#if CONFIG_RTW_MESH_DATA_BMC_TO_UC
+		|| attrib->mb2u
+		#endif
+	) {
+		#if CONFIG_RTW_MESH_DATA_BMC_TO_UC
+		if (!attrib->mfwd_ttl)
+			mctrl->ttl = adapter->mesh_cfg.dot11MeshTTL;
+		else
+		#endif
+			mctrl->ttl = attrib->mfwd_ttl;
+
+		mctrl->seqnum = (cpu_to_le32(attrib->mseq));
+	} else {
+		mctrl->ttl = adapter->mesh_cfg.dot11MeshTTL;
+		mctrl->seqnum = (cpu_to_le32(adapter->mesh_info.mesh_seqnum));
+		adapter->mesh_info.mesh_seqnum++;
+	}
+
+	switch (attrib->mesh_frame_mode){
+	case MESH_UCAST_DATA:
+	case MESH_BMCAST_DATA:
+		break;
+	case MESH_UCAST_PX_DATA:
+		mctrl->flags |= MESH_FLAGS_AE_A5_A6;
+		_rtw_memcpy(mctrl->eaddr1, attrib->dst, ETH_ALEN);
+		_rtw_memcpy(mctrl->eaddr2, attrib->src, ETH_ALEN);
+		break;
+	case MESH_BMCAST_PX_DATA:
+		mctrl->flags |= MESH_FLAGS_AE_A4;
+		_rtw_memcpy(mctrl->eaddr1, attrib->src, ETH_ALEN);
+		break;
+	case MESH_MHOP_UCAST_ACT:
+		/* TBD */
+		break;
+	case MESH_MHOP_BMCAST_ACT:
+		/* TBD */
+		break;
+	default:
+		break;
+	}
+}
+
+u8 rtw_mesh_tx_build_whdr(_adapter *adapter, struct pkt_attrib *attrib
+	, u16 *fctrl, struct rtw_ieee80211_hdr *whdr)
+{
+	switch (attrib->mesh_frame_mode) {
+	case MESH_UCAST_DATA:		/* 1, 1, RA, TA, mDA(=DA),	mSA(=SA) */
+	case MESH_UCAST_PX_DATA:	/* 1, 1, RA, TA, mDA,		mSA,		[DA, SA] */
+		SetToDs(fctrl);
+		SetFrDs(fctrl);
+		_rtw_memcpy(whdr->addr1, attrib->ra, ETH_ALEN);
+		_rtw_memcpy(whdr->addr2, attrib->ta, ETH_ALEN);
+		_rtw_memcpy(whdr->addr3, attrib->mda, ETH_ALEN);
+		_rtw_memcpy(whdr->addr4, attrib->msa, ETH_ALEN);
+		break;
+	case MESH_BMCAST_DATA:		/* 0, 1, RA(DA), TA, mSA(SA) */
+	case MESH_BMCAST_PX_DATA:	/* 0, 1, RA(DA), TA, mSA,		[SA] */
+		SetFrDs(fctrl);
+		_rtw_memcpy(whdr->addr1, attrib->ra, ETH_ALEN);
+		_rtw_memcpy(whdr->addr2, attrib->ta, ETH_ALEN);
+		_rtw_memcpy(whdr->addr3, attrib->msa, ETH_ALEN);
+		break;
+	case MESH_MHOP_UCAST_ACT:
+		/* TBD */
+		RTW_INFO("MESH_MHOP_UCAST_ACT\n");
+		break;
+	case MESH_MHOP_BMCAST_ACT:
+		/* TBD */
+		RTW_INFO("MESH_MHOP_BMCAST_ACT\n");
+		break;
+	default:
+		RTW_WARN("Invalid mesh frame mode\n");
+		break;
+	}
+	
+	return 0;
+}
+
+int rtw_mesh_rx_data_validate_hdr(_adapter *adapter, union recv_frame *rframe, struct sta_info **sta)
+{
+	struct sta_priv *stapriv = &adapter->stapriv;
+	struct rx_pkt_attrib *rattrib = &rframe->u.hdr.attrib;
+	u8 *whdr = get_recvframe_data(rframe);
+	u8 is_ra_bmc = 0;
+	u8 a4_shift = 0;
+	u8 ps;
+	u8 *qc;
+	u8 mps_mode = RTW_MESH_PS_UNKNOWN;
+	sint ret = _FAIL;
+
+	if (!(MLME_STATE(adapter) & WIFI_ASOC_STATE))
+		goto exit;
+
+	if (!rattrib->qos)
+		goto exit;
+
+	switch (rattrib->to_fr_ds) {
+	case 1:
+		if (!IS_MCAST(GetAddr1Ptr(whdr)))
+			goto exit;
+		*sta = rtw_get_stainfo(stapriv, get_addr2_ptr(whdr));
+		if (*sta == NULL) {
+			ret = _SUCCESS; /* return _SUCCESS to drop at sta checking */
+			goto exit;
+		}
+		_rtw_memcpy(rattrib->ra, GetAddr1Ptr(whdr), ETH_ALEN);
+		_rtw_memcpy(rattrib->ta, get_addr2_ptr(whdr), ETH_ALEN);
+		_rtw_memcpy(rattrib->mda, GetAddr1Ptr(whdr), ETH_ALEN);
+		_rtw_memcpy(rattrib->msa, GetAddr3Ptr(whdr), ETH_ALEN); /* may change after checking AMSDU subframe header */
+		_rtw_memcpy(rattrib->dst, GetAddr1Ptr(whdr), ETH_ALEN);
+		_rtw_memcpy(rattrib->src, GetAddr3Ptr(whdr), ETH_ALEN); /* may change after checking mesh ctrl field */
+		_rtw_memcpy(rattrib->bssid, get_addr2_ptr(whdr), ETH_ALEN);
+		is_ra_bmc = 1;
+		break;
+	case 3:
+		if (IS_MCAST(GetAddr1Ptr(whdr)))
+			goto exit;
+		*sta = rtw_get_stainfo(stapriv, get_addr2_ptr(whdr));
+		if (*sta == NULL) {
+			ret = _SUCCESS; /* return _SUCCESS to drop at sta checking */
+			goto exit;
+		}
+		_rtw_memcpy(rattrib->ra, GetAddr1Ptr(whdr), ETH_ALEN);
+		_rtw_memcpy(rattrib->ta, get_addr2_ptr(whdr), ETH_ALEN);
+		_rtw_memcpy(rattrib->mda, GetAddr3Ptr(whdr), ETH_ALEN); /* may change after checking AMSDU subframe header */
+		_rtw_memcpy(rattrib->msa, GetAddr4Ptr(whdr), ETH_ALEN); /* may change after checking AMSDU subframe header */
+		_rtw_memcpy(rattrib->dst, GetAddr3Ptr(whdr), ETH_ALEN); /* may change after checking mesh ctrl field */
+		_rtw_memcpy(rattrib->src, GetAddr4Ptr(whdr), ETH_ALEN); /* may change after checking mesh ctrl field */
+		_rtw_memcpy(rattrib->bssid, get_addr2_ptr(whdr), ETH_ALEN);
+		a4_shift = ETH_ALEN;
+		break;
+	default:
+		goto exit;
+	}
+
+	qc = whdr + WLAN_HDR_A3_LEN + a4_shift;
+	ps = GetPwrMgt(whdr);
+	mps_mode = ps ? (is_ra_bmc || (get_mps_lv(qc)) ? RTW_MESH_PS_DSLEEP : RTW_MESH_PS_LSLEEP) : RTW_MESH_PS_ACTIVE;
+
+	if (ps) {
+		if (!((*sta)->state & WIFI_SLEEP_STATE))
+			stop_sta_xmit(adapter, *sta);
+	} else {
+		if ((*sta)->state & WIFI_SLEEP_STATE)
+			wakeup_sta_to_xmit(adapter, *sta);
+	}
+
+	if (is_ra_bmc)
+		(*sta)->nonpeer_mps = mps_mode;
+	else {
+		(*sta)->peer_mps = mps_mode;
+		if (mps_mode != RTW_MESH_PS_ACTIVE && (*sta)->nonpeer_mps == RTW_MESH_PS_ACTIVE)
+			(*sta)->nonpeer_mps = RTW_MESH_PS_DSLEEP;
+	}
+
+	if (get_frame_sub_type(whdr) & BIT(6)) {
+		/* No data, will not indicate to upper layer, temporily count it here */
+		count_rx_stats(adapter, rframe, *sta);
+		ret = RTW_RX_HANDLED;
+		goto exit;
+	}
+
+	rattrib->mesh_ctrl_present = get_mctrl_present(qc) ? 1 : 0;
+	if (!rattrib->mesh_ctrl_present)
+		goto exit;
+
+	ret = _SUCCESS;
+
+exit:
+	return ret;
+}
+
+int rtw_mesh_rx_data_validate_mctrl(_adapter *adapter, union recv_frame *rframe
+	, const struct rtw_ieee80211s_hdr *mctrl, const u8 *mda, const u8 *msa
+	, u8 *mctrl_len
+	, const u8 **da, const u8 **sa)
+{
+	struct rx_pkt_attrib *rattrib = &rframe->u.hdr.attrib;
+	u8 mlen;
+	u8 ae;
+	int ret = _SUCCESS;
+
+	ae = mctrl->flags & MESH_FLAGS_AE;
+	mlen = ae_to_mesh_ctrl_len[ae];
+	switch (rattrib->to_fr_ds) {
+	case 1:
+		*da = mda;
+		if (ae == MESH_FLAGS_AE_A4)
+			*sa = mctrl->eaddr1;
+		else if (ae == 0)
+			*sa = msa;
+		else
+			ret = _FAIL;
+		break;
+	case 3:
+		if (ae == MESH_FLAGS_AE_A5_A6) {
+			*da = mctrl->eaddr1;
+			*sa = mctrl->eaddr2;
+		} else if (ae == 0) {
+			*da = mda;
+			*sa = msa;
+		} else
+			ret = _FAIL;
+		break;
+	default:
+		ret = _FAIL;
+	}
+
+	if (ret == _FAIL) {
+		#ifdef DBG_RX_DROP_FRAME
+		RTW_INFO("DBG_RX_DROP_FRAME "FUNC_ADPT_FMT" invalid tfDS:%u AE:%u combination ra="MAC_FMT" ta="MAC_FMT"\n"
+			, FUNC_ADPT_ARG(adapter), rattrib->to_fr_ds, ae, MAC_ARG(rattrib->ra), MAC_ARG(rattrib->ta));
+		#endif
+		*mctrl_len = 0;
+	} else
+		*mctrl_len = mlen;
+
+	return ret;	
+}
+
+inline int rtw_mesh_rx_validate_mctrl_non_amsdu(_adapter *adapter, union recv_frame *rframe)
+{
+	struct rx_pkt_attrib *rattrib = &rframe->u.hdr.attrib;
+	const u8 *da, *sa;
+	int ret;
+
+	ret = rtw_mesh_rx_data_validate_mctrl(adapter, rframe
+			, (struct rtw_ieee80211s_hdr *)(get_recvframe_data(rframe) + rattrib->hdrlen + rattrib->iv_len)
+			, rattrib->mda, rattrib->msa
+			, &rattrib->mesh_ctrl_len
+			, &da, &sa);
+
+	if (ret == _SUCCESS) {
+		_rtw_memcpy(rattrib->dst, da, ETH_ALEN);
+		_rtw_memcpy(rattrib->src, sa, ETH_ALEN);
+	}
+
+	return ret;
+}
+
+/**
+ * rtw_mesh_rx_nexthop_resolve - lookup next hop; conditionally start path discovery
+ *
+ * @skb: 802.11 frame to be sent
+ * @sdata: network subif the frame will be sent through
+ *
+ * Lookup next hop for given skb and start path discovery if no
+ * forwarding information is found.
+ *
+ * Returns: 0 if the next hop was found and -ENOENT if the frame was queued.
+ * skb is freeed here if no mpath could be allocated.
+ */
+static int rtw_mesh_rx_nexthop_resolve(_adapter *adapter,
+	const u8 *mda, const u8 *msa, u8 *ra)
+{
+	struct rtw_mesh_path *mpath;
+	struct xmit_frame *xframe_to_free = NULL;
+	int err = 0;
+	int ret = _SUCCESS;
+
+	rtw_rcu_read_lock();
+	err = rtw_mesh_nexthop_lookup(adapter, mda, msa, ra);
+	if (!err)
+		goto endlookup;
+
+	/* no nexthop found, start resolving */
+	mpath = rtw_mesh_path_lookup(adapter, mda);
+	if (!mpath) {
+		mpath = rtw_mesh_path_add(adapter, mda);
+		if (IS_ERR(mpath)) {
+			err = PTR_ERR(mpath);
+			ret = _FAIL;
+			goto endlookup;
+		}
+	}
+
+	if (!(mpath->flags & RTW_MESH_PATH_RESOLVING))
+		rtw_mesh_queue_preq(mpath, RTW_PREQ_Q_F_START);
+
+	ret = _FAIL;
+
+endlookup:
+	rtw_rcu_read_unlock();
+	return ret;
+}
+
+#define RTW_MESH_DECACHE_BMC 1
+#define RTW_MESH_DECACHE_UC 0
+
+#define RTW_MESH_FORWARD_MDA_SELF_COND 0
+#define DBG_RTW_MESH_FORWARD_MDA_SELF_COND 0
+int rtw_mesh_rx_msdu_act_check(union recv_frame *rframe
+	, const u8 *mda, const u8 *msa
+	, const u8 *da, const u8 *sa
+	, struct rtw_ieee80211s_hdr *mctrl
+	, struct xmit_frame **fwd_frame, _list *b2u_list)
+{
+	_adapter *adapter = rframe->u.hdr.adapter;
+	struct rtw_mesh_cfg *mcfg = &adapter->mesh_cfg;
+	struct rtw_mesh_info *minfo = &adapter->mesh_info;
+	struct rx_pkt_attrib *rattrib = &rframe->u.hdr.attrib;
+	struct rtw_mesh_path *mppath;
+	u8 is_mda_bmc = IS_MCAST(mda); 
+	u8 is_mda_self = !is_mda_bmc && _rtw_memcmp(mda, adapter_mac_addr(adapter), ETH_ALEN);
+	struct xmit_frame *xframe;
+	struct pkt_attrib *xattrib;
+	u8 fwd_ra[ETH_ALEN] = {0};
+	u8 fwd_mpp[ETH_ALEN] = {0}; /* forward to other gate */
+	u32 fwd_mseq;
+	int act = 0;
+	u8 ae_need;
+#if CONFIG_RTW_MESH_DATA_BMC_TO_UC
+	bool bmc_need = _TRUE;
+	u8 b2u_num = 0;
+#endif
+
+	/* fwd info lifetime update */
+	#if 0
+	if (!is_mda_self)
+		mDA(A3) fwinfo.lifetime
+	mSA(A4) fwinfo.lifetime
+	Precursor-to-mDA(A2) fwinfo.lifetime
+	#endif
+
+	/* update/create pxoxy info for SA, mSA */
+	if ((mctrl->flags & MESH_FLAGS_AE)
+		&& sa != msa && _rtw_memcmp(sa, msa, ETH_ALEN) == _FALSE
+	) {
+		const u8 *proxied_addr = sa;
+		const u8 *mpp_addr = msa;
+
+		rtw_rcu_read_lock();
+		mppath = rtw_mpp_path_lookup(adapter, proxied_addr);
+		if (!mppath)
+			rtw_mpp_path_add(adapter, proxied_addr, mpp_addr);
+		else {
+			enter_critical_bh(&mppath->state_lock);
+			if (_rtw_memcmp(mppath->mpp, mpp_addr, ETH_ALEN) == _FALSE)
+				_rtw_memcpy(mppath->mpp, mpp_addr, ETH_ALEN);
+			mppath->exp_time = rtw_get_current_time();
+			exit_critical_bh(&mppath->state_lock);
+		}
+		rtw_rcu_read_unlock();
+	}
+
+	/* mSA is self, need no further process */
+	if (_rtw_memcmp(msa, adapter_mac_addr(adapter), ETH_ALEN) == _TRUE)
+		goto exit;
+
+	fwd_mseq = le32_to_cpu(mctrl->seqnum);
+
+	/* check duplicate MSDU from mSA */
+	if (((RTW_MESH_DECACHE_BMC && is_mda_bmc)
+			|| (RTW_MESH_DECACHE_UC && !is_mda_bmc))
+		&& rtw_mesh_decache(adapter, msa, fwd_mseq)
+	) {
+		minfo->mshstats.dropped_frames_duplicate++;
+		goto exit;
+	}
+
+	if (is_mda_bmc) {
+		/* mDA is bmc addr */
+		act |= RTW_RX_MSDU_ACT_INDICATE;
+		if (!mcfg->dot11MeshForwarding)
+			goto exit;
+		goto fwd_chk;
+
+	} else if (!is_mda_self) {
+		/* mDA is unicast but not self */
+		if (!mcfg->dot11MeshForwarding) {
+			rtw_mesh_path_error_tx(adapter
+				, adapter->mesh_cfg.element_ttl
+				, mda, 0
+				, WLAN_REASON_MESH_PATH_NOFORWARD
+				, rattrib->ta
+			);
+			#ifdef DBG_RX_DROP_FRAME
+			RTW_INFO("DBG_RX_DROP_FRAME "FUNC_ADPT_FMT" mDA("MAC_FMT") not self, !dot11MeshForwarding\n"
+				, FUNC_ADPT_ARG(adapter), MAC_ARG(mda));
+			#endif
+			goto exit;
+		}
+
+		if (rtw_mesh_rx_nexthop_resolve(adapter, mda, msa, fwd_ra) != _SUCCESS) {
+			/* mDA is unknown */
+			rtw_mesh_path_error_tx(adapter
+				, adapter->mesh_cfg.element_ttl
+				, mda, 0
+				, WLAN_REASON_MESH_PATH_NOFORWARD
+				, rattrib->ta
+			);
+			#ifdef DBG_RX_DROP_FRAME
+			RTW_INFO("DBG_RX_DROP_FRAME "FUNC_ADPT_FMT" mDA("MAC_FMT") unknown\n"
+				, FUNC_ADPT_ARG(adapter), MAC_ARG(mda));
+			#endif
+			minfo->mshstats.dropped_frames_no_route++;
+			goto exit;
+
+		} else {
+			/* mDA is known in fwd info */
+			#if 0
+			if	(TA is not in precursors)
+				goto exit;
+			#endif
+			goto fwd_chk;
+		}
+
+	} else {
+		/* mDA is self */
+		#if RTW_MESH_FORWARD_MDA_SELF_COND
+		if (da == mda
+			|| _rtw_memcmp(da, adapter_mac_addr(adapter), ETH_ALEN)
+		) {
+			/* DA is self, indicate */
+			act |= RTW_RX_MSDU_ACT_INDICATE;
+			goto exit;
+		}
+
+		if (rtw_get_iface_by_macddr(adapter, da)) {
+			/* DA is buddy, indicate */
+			act |= RTW_RX_MSDU_ACT_INDICATE;
+			#if DBG_RTW_MESH_FORWARD_MDA_SELF_COND
+			RTW_INFO(FUNC_ADPT_FMT" DA("MAC_FMT") is buddy("ADPT_FMT")\n"
+				, FUNC_ADPT_ARG(adapter), MAC_ARG(da), ADPT_ARG(rtw_get_iface_by_macddr(adapter, da)));
+			#endif
+			goto exit;
+		}
+
+		/* DA is not self or buddy */
+		if (rtw_mesh_nexthop_lookup(adapter, da, msa, fwd_ra) == 0) {
+			/* DA is known in fwd info */
+			if (!mcfg->dot11MeshForwarding) {
+				/* path error to? */
+				#if defined(DBG_RX_DROP_FRAME) || DBG_RTW_MESH_FORWARD_MDA_SELF_COND
+				RTW_INFO("DBG_RX_DROP_FRAME "FUNC_ADPT_FMT" DA("MAC_FMT") not self, !dot11MeshForwarding\n"
+					, FUNC_ADPT_ARG(adapter), MAC_ARG(da));
+				#endif
+				goto exit;
+			}
+			mda = da;
+			#if DBG_RTW_MESH_FORWARD_MDA_SELF_COND
+			RTW_INFO(FUNC_ADPT_FMT" fwd to DA("MAC_FMT"), fwd_RA("MAC_FMT")\n"
+				, FUNC_ADPT_ARG(adapter), MAC_ARG(da), MAC_ARG(fwd_ra));
+			#endif
+			goto fwd_chk;
+		}
+
+		rtw_rcu_read_lock();
+		mppath = rtw_mpp_path_lookup(adapter, da);
+		if (mppath) {
+			if (_rtw_memcmp(mppath->mpp, adapter_mac_addr(adapter), ETH_ALEN) == _FALSE) {
+				/* DA is proxied by others */
+				if (!mcfg->dot11MeshForwarding) {
+					/* path error to? */
+					#if defined(DBG_RX_DROP_FRAME) || DBG_RTW_MESH_FORWARD_MDA_SELF_COND
+					RTW_INFO("DBG_RX_DROP_FRAME "FUNC_ADPT_FMT" DA("MAC_FMT") is proxied by ("MAC_FMT"), !dot11MeshForwarding\n"
+						, FUNC_ADPT_ARG(adapter), MAC_ARG(da), MAC_ARG(mppath->mpp));
+					#endif
+					rtw_rcu_read_unlock();
+					goto exit;
+				}
+				_rtw_memcpy(fwd_mpp, mppath->mpp, ETH_ALEN);
+				mda = fwd_mpp;
+				msa = adapter_mac_addr(adapter);
+				rtw_rcu_read_unlock();
+
+				/* resolve RA */
+				if (rtw_mesh_nexthop_lookup(adapter, mda, msa, fwd_ra) != 0) {
+					minfo->mshstats.dropped_frames_no_route++;
+					#if defined(DBG_RX_DROP_FRAME) || DBG_RTW_MESH_FORWARD_MDA_SELF_COND
+					RTW_INFO("DBG_RX_DROP_FRAME "FUNC_ADPT_FMT" DA("MAC_FMT") is proxied by ("MAC_FMT"), RA resolve fail\n"
+						, FUNC_ADPT_ARG(adapter), MAC_ARG(da), MAC_ARG(mppath->mpp));
+					#endif
+					goto exit;
+				}
+				#if DBG_RTW_MESH_FORWARD_MDA_SELF_COND
+				RTW_INFO(FUNC_ADPT_FMT" DA("MAC_FMT") is proxied by ("MAC_FMT"), fwd_RA("MAC_FMT")\n"
+					, FUNC_ADPT_ARG(adapter), MAC_ARG(da), MAC_ARG(mppath->mpp), MAC_ARG(fwd_ra));
+				#endif
+				goto fwd_chk; /*  forward to other gate */
+			} else {
+				#if DBG_RTW_MESH_FORWARD_MDA_SELF_COND
+				RTW_INFO(FUNC_ADPT_FMT" DA("MAC_FMT") is proxied by self\n"
+					, FUNC_ADPT_ARG(adapter), MAC_ARG(da));
+				#endif
+			}
+		}
+		rtw_rcu_read_unlock();
+
+		if (!mppath) {
+			#if DBG_RTW_MESH_FORWARD_MDA_SELF_COND
+			RTW_INFO(FUNC_ADPT_FMT" DA("MAC_FMT") unknown\n"
+				, FUNC_ADPT_ARG(adapter), MAC_ARG(da));
+			#endif
+			/* DA is unknown */
+			#if 0 /* TODO: flags with AE bit */
+			rtw_mesh_path_error_tx(adapter
+				, adapter->mesh_cfg.element_ttl
+				, mda, adapter->mesh_info.last_sn_update
+				, WLAN_REASON_MESH_PATH_NOPROXY
+				, msa
+			);
+			#endif
+		}
+
+		/*
+		* indicate to DS for both cases:
+		* 1.) DA is proxied by self
+		* 2.) DA is unknown
+		*/
+		#endif /* RTW_MESH_FORWARD_MDA_SELF_COND */
+		act |= RTW_RX_MSDU_ACT_INDICATE;
+		goto exit;
+	}
+
+fwd_chk:
+
+	if (adapter->stapriv.asoc_list_cnt <= 1)
+		goto exit;
+
+	if (mctrl->ttl == 1) {
+		minfo->mshstats.dropped_frames_ttl++;
+		if (!act) {
+			#ifdef DBG_RX_DROP_FRAME
+			RTW_INFO("DBG_RX_DROP_FRAME "FUNC_ADPT_FMT" ttl reaches 0, not forwarding\n"
+				, FUNC_ADPT_ARG(adapter));
+			#endif
+		}
+		goto exit;
+	}
+
+#if CONFIG_RTW_MESH_DATA_BMC_TO_UC
+	_rtw_init_listhead(b2u_list);
+#endif
+
+	ae_need = _rtw_memcmp(da , mda, ETH_ALEN) == _FALSE
+		|| _rtw_memcmp(sa , msa, ETH_ALEN) == _FALSE;
+
+#if CONFIG_RTW_MESH_DATA_BMC_TO_UC
+	if (is_mda_bmc
+		&& rtw_mfwd_b2u_policy_chk(mcfg->b2u_flags_mfwd, mda, rattrib->to_fr_ds == 3)
+	) {
+		bmc_need = rtw_mesh_data_bmc_to_uc(adapter
+			, da, sa, mda, msa, ae_need, rframe->u.hdr.psta->cmn.mac_addr, mctrl->ttl - 1
+			, b2u_list, &b2u_num, &fwd_mseq);
+	}
+
+	if (bmc_need == _TRUE)
+#endif
+	{
+		xframe = rtw_alloc_xmitframe(&adapter->xmitpriv);
+		if (!xframe) {
+			#ifdef DBG_TX_DROP_FRAME
+			RTW_INFO("DBG_TX_DROP_FRAME "FUNC_ADPT_FMT" rtw_alloc_xmitframe fail\n"
+				, FUNC_ADPT_ARG(adapter));
+			#endif
+			goto exit;
+		}
+
+		xattrib = &xframe->attrib;
+
+#if CONFIG_RTW_MESH_DATA_BMC_TO_UC
+		if (b2u_num)
+			xattrib->mb2u = 1;
+		else
+			xattrib->mb2u = 0;
+#endif
+		xattrib->mfwd_ttl = mctrl->ttl - 1;
+		xattrib->mseq = fwd_mseq;
+		_rtw_memcpy(xattrib->dst, da, ETH_ALEN);
+		_rtw_memcpy(xattrib->src, sa, ETH_ALEN);
+		_rtw_memcpy(xattrib->mda, mda, ETH_ALEN);
+		_rtw_memcpy(xattrib->msa, msa, ETH_ALEN);
+		_rtw_memcpy(xattrib->ta, adapter_mac_addr(adapter), ETH_ALEN);
+
+		if (is_mda_bmc) {
+			xattrib->mesh_frame_mode = ae_need ? MESH_BMCAST_PX_DATA : MESH_BMCAST_DATA;
+			_rtw_memcpy(xattrib->ra, mda, ETH_ALEN);
+		} else {
+			xattrib->mesh_frame_mode = ae_need ? MESH_UCAST_PX_DATA : MESH_UCAST_DATA;
+			_rtw_memcpy(xattrib->ra, fwd_ra, ETH_ALEN);
+		}
+
+		*fwd_frame = xframe;
+	}
+
+	act |= RTW_RX_MSDU_ACT_FORWARD;
+	if (is_mda_bmc)
+		minfo->mshstats.fwded_mcast++;
+	else
+		minfo->mshstats.fwded_unicast++;
+	minfo->mshstats.fwded_frames++;
+
+exit:
+	return act;
+}
+
+void dump_mesh_stats(void *sel, _adapter *adapter)
+{
+	struct rtw_mesh_info *minfo = &adapter->mesh_info;
+	struct rtw_mesh_stats *stats = &minfo->mshstats;
+
+	RTW_PRINT_SEL(sel, "fwd_bmc:%u\n", stats->fwded_mcast);
+	RTW_PRINT_SEL(sel, "fwd_uc:%u\n", stats->fwded_unicast);
+
+	RTW_PRINT_SEL(sel, "drop_ttl:%u\n", stats->dropped_frames_ttl);
+	RTW_PRINT_SEL(sel, "drop_no_route:%u\n", stats->dropped_frames_no_route);
+	RTW_PRINT_SEL(sel, "drop_congestion:%u\n", stats->dropped_frames_congestion);
+	RTW_PRINT_SEL(sel, "drop_dup:%u\n", stats->dropped_frames_duplicate);
+
+	RTW_PRINT_SEL(sel, "mrc_del_qlen:%u\n", stats->mrc_del_qlen);
+}
+#endif /* CONFIG_RTW_MESH */
+
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/core/mesh/rtw_mesh.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/core/mesh/rtw_mesh.h
--- linux-5.6.3/3rdparty/rtl8821ce/core/mesh/rtw_mesh.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/core/mesh/rtw_mesh.h	2020-04-10 16:35:06.769657873 +0300
@@ -0,0 +1,534 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#ifndef __RTW_MESH_H_
+#define __RTW_MESH_H_
+
+#ifndef CONFIG_AP_MODE
+	#error "CONFIG_RTW_MESH can't be enabled when CONFIG_AP_MODE is not defined\n"
+#endif
+
+#define RTW_MESH_TTL				31
+#define RTW_MESH_PERR_MIN_INT			100
+#define RTW_MESH_DEFAULT_ELEMENT_TTL		31
+#define RTW_MESH_RANN_INTERVAL			5000
+#define RTW_MESH_PATH_TO_ROOT_TIMEOUT		6000
+#define RTW_MESH_DIAM_TRAVERSAL_TIME		50
+#define RTW_MESH_PATH_TIMEOUT			5000
+#define RTW_MESH_PREQ_MIN_INT			10
+#define RTW_MESH_MAX_PREQ_RETRIES		4
+#define RTW_MESH_MIN_DISCOVERY_TIMEOUT 		(2 * RTW_MESH_DIAM_TRAVERSAL_TIME)
+#define RTW_MESH_ROOT_CONFIRMATION_INTERVAL	2000
+#define RTW_MESH_PATH_REFRESH_TIME		1000
+#define RTW_MESH_ROOT_INTERVAL			5000
+
+#define RTW_MESH_SANE_METRIC_DELTA		100
+#define RTW_MESH_MAX_ROOT_ADD_CHK_CNT		2
+
+#define RTW_MESH_PLINK_UNKNOWN	0
+#define RTW_MESH_PLINK_LISTEN	1
+#define RTW_MESH_PLINK_OPN_SNT	2
+#define RTW_MESH_PLINK_OPN_RCVD 3
+#define RTW_MESH_PLINK_CNF_RCVD 4
+#define RTW_MESH_PLINK_ESTAB	5
+#define RTW_MESH_PLINK_HOLDING	6
+#define RTW_MESH_PLINK_BLOCKED	7
+
+extern const char *_rtw_mesh_plink_str[];
+#define rtw_mesh_plink_str(s) ((s <= RTW_MESH_PLINK_BLOCKED) ? _rtw_mesh_plink_str[s] : _rtw_mesh_plink_str[RTW_MESH_PLINK_UNKNOWN])
+
+#define RTW_MESH_PS_UNKNOWN 0
+#define RTW_MESH_PS_ACTIVE 1
+#define RTW_MESH_PS_LSLEEP 2
+#define RTW_MESH_PS_DSLEEP 3
+
+extern const char *_rtw_mesh_ps_str[];
+#define rtw_mesh_ps_str(mps) ((mps <= RTW_MESH_PS_DSLEEP) ? _rtw_mesh_ps_str[mps] : _rtw_mesh_ps_str[RTW_MESH_PS_UNKNOWN])
+
+#define GET_MESH_CONF_ELE_PATH_SEL_PROTO_ID(_iec)		LE_BITS_TO_1BYTE(((u8 *)(_iec)) + 0, 0, 8)
+#define GET_MESH_CONF_ELE_PATH_SEL_METRIC_ID(_iec)		LE_BITS_TO_1BYTE(((u8 *)(_iec)) + 1, 0, 8)
+#define GET_MESH_CONF_ELE_CONGEST_CTRL_MODE_ID(_iec)	LE_BITS_TO_1BYTE(((u8 *)(_iec)) + 2, 0, 8)
+#define GET_MESH_CONF_ELE_SYNC_METHOD_ID(_iec)			LE_BITS_TO_1BYTE(((u8 *)(_iec)) + 3, 0, 8)
+#define GET_MESH_CONF_ELE_AUTH_PROTO_ID(_iec)			LE_BITS_TO_1BYTE(((u8 *)(_iec)) + 4, 0, 8)
+
+#define GET_MESH_CONF_ELE_MESH_FORMATION(_iec)			LE_BITS_TO_1BYTE(((u8 *)(_iec)) + 5, 0, 8)
+#define GET_MESH_CONF_ELE_CTO_MGATE(_iec)				LE_BITS_TO_1BYTE(((u8 *)(_iec)) + 5, 0, 1)
+#define GET_MESH_CONF_ELE_NUM_OF_PEERINGS(_iec)			LE_BITS_TO_1BYTE(((u8 *)(_iec)) + 5, 1, 6)
+#define GET_MESH_CONF_ELE_CTO_AS(_iec)					LE_BITS_TO_1BYTE(((u8 *)(_iec)) + 5, 7, 1)
+
+#define GET_MESH_CONF_ELE_MESH_CAP(_iec)				LE_BITS_TO_1BYTE(((u8 *)(_iec)) + 6, 0, 8)
+#define GET_MESH_CONF_ELE_ACCEPT_PEERINGS(_iec)			LE_BITS_TO_1BYTE(((u8 *)(_iec)) + 6, 0, 1)
+#define GET_MESH_CONF_ELE_MCCA_SUP(_iec)				LE_BITS_TO_1BYTE(((u8 *)(_iec)) + 6, 1, 1)
+#define GET_MESH_CONF_ELE_MCCA_EN(_iec)					LE_BITS_TO_1BYTE(((u8 *)(_iec)) + 6, 2, 1)
+#define GET_MESH_CONF_ELE_FORWARDING(_iec)				LE_BITS_TO_1BYTE(((u8 *)(_iec)) + 6, 3, 1)
+#define GET_MESH_CONF_ELE_MBCA_EN(_iec)					LE_BITS_TO_1BYTE(((u8 *)(_iec)) + 6, 4, 1)
+#define GET_MESH_CONF_ELE_TBTT_ADJ(_iec)				LE_BITS_TO_1BYTE(((u8 *)(_iec)) + 6, 5, 1)
+#define GET_MESH_CONF_ELE_PS_LEVEL(_iec)				LE_BITS_TO_1BYTE(((u8 *)(_iec)) + 6, 6, 1)
+
+#define SET_MESH_CONF_ELE_PATH_SEL_PROTO_ID(_iec, _val)		SET_BITS_TO_LE_1BYTE(((u8 *)(_iec)) + 0, 0, 8, _val)
+#define SET_MESH_CONF_ELE_PATH_SEL_METRIC_ID(_iec, _val)	SET_BITS_TO_LE_1BYTE(((u8 *)(_iec)) + 1, 0, 8, _val)
+#define SET_MESH_CONF_ELE_CONGEST_CTRL_MODE_ID(_iec, _val)	SET_BITS_TO_LE_1BYTE(((u8 *)(_iec)) + 2, 0, 8, _val)
+#define SET_MESH_CONF_ELE_SYNC_METHOD_ID(_iec, _val)		SET_BITS_TO_LE_1BYTE(((u8 *)(_iec)) + 3, 0, 8, _val)
+#define SET_MESH_CONF_ELE_AUTH_PROTO_ID(_iec, _val)			SET_BITS_TO_LE_1BYTE(((u8 *)(_iec)) + 4, 0, 8, _val)
+
+#define SET_MESH_CONF_ELE_CTO_MGATE(_iec, _val)				SET_BITS_TO_LE_1BYTE(((u8 *)(_iec)) + 5, 0, 1, _val)
+#define SET_MESH_CONF_ELE_NUM_OF_PEERINGS(_iec, _val)		SET_BITS_TO_LE_1BYTE(((u8 *)(_iec)) + 5, 1, 6, _val)
+#define SET_MESH_CONF_ELE_CTO_AS(_iec, _val)				SET_BITS_TO_LE_1BYTE(((u8 *)(_iec)) + 5, 7, 1, _val)
+
+#define SET_MESH_CONF_ELE_ACCEPT_PEERINGS(_iec, _val)		SET_BITS_TO_LE_1BYTE(((u8 *)(_iec)) + 6, 0, 1, _val)
+#define SET_MESH_CONF_ELE_MCCA_SUP(_iec, _val)				SET_BITS_TO_LE_1BYTE(((u8 *)(_iec)) + 6, 1, 1, _val)
+#define SET_MESH_CONF_ELE_MCCA_EN(_iec, _val)				SET_BITS_TO_LE_1BYTE(((u8 *)(_iec)) + 6, 2, 1, _val)
+#define SET_MESH_CONF_ELE_FORWARDING(_iec, _val)			SET_BITS_TO_LE_1BYTE(((u8 *)(_iec)) + 6, 3, 1, _val)
+#define SET_MESH_CONF_ELE_MBCA_EN(_iec, _val)				SET_BITS_TO_LE_1BYTE(((u8 *)(_iec)) + 6, 4, 1, _val)
+#define SET_MESH_CONF_ELE_TBTT_ADJ(_iec, _val)				SET_BITS_TO_LE_1BYTE(((u8 *)(_iec)) + 6, 5, 1, _val)
+#define SET_MESH_CONF_ELE_PS_LEVEL(_iec, _val)				SET_BITS_TO_LE_1BYTE(((u8 *)(_iec)) + 6, 6, 1, _val)
+
+/* Mesh flags */
+#define MESH_FLAGS_AE		0x3 /* mask */
+#define MESH_FLAGS_AE_A4 	0x1
+#define MESH_FLAGS_AE_A5_A6	0x2
+
+/* Max number of paths */
+#define RTW_MESH_MAX_PATHS 1024
+
+#define RTW_PREQ_Q_F_START	0x1
+#define RTW_PREQ_Q_F_REFRESH	0x2
+#define RTW_PREQ_Q_F_CHK	0x4
+#define RTW_PREQ_Q_F_PEER_AKA	0x8
+struct rtw_mesh_preq_queue {
+	_list list;
+	u8 dst[ETH_ALEN];
+	u8 flags;
+};
+
+extern const u8 ae_to_mesh_ctrl_len[];
+
+enum mesh_frame_type {
+	MESH_UCAST_DATA		= 0x0,
+	MESH_BMCAST_DATA	= 0x1,
+	MESH_UCAST_PX_DATA	= 0x2,
+	MESH_BMCAST_PX_DATA	= 0x3,
+	MESH_MHOP_UCAST_ACT	= 0x4,
+	MESH_MHOP_BMCAST_ACT	= 0x5,
+};
+
+enum mpath_sel_frame_type {
+	MPATH_PREQ = 0,
+	MPATH_PREP,
+	MPATH_PERR,
+	MPATH_RANN
+};
+
+/**
+ * enum rtw_mesh_deferred_task_flags - mesh deferred tasks
+ *
+ *
+ *
+ * @RTW_MESH_WORK_HOUSEKEEPING: run the periodic mesh housekeeping tasks
+ * @RTW_MESH_WORK_ROOT: the mesh root station needs to send a frame
+ * @RTW_MESH_WORK_DRIFT_ADJUST: time to compensate for clock drift relative to other
+ * mesh nodes
+ * @RTW_MESH_WORK_MBSS_CHANGED: rebuild beacon and notify driver of BSS changes
+ */
+enum rtw_mesh_deferred_task_flags {
+	RTW_MESH_WORK_HOUSEKEEPING,
+	RTW_MESH_WORK_ROOT,
+	RTW_MESH_WORK_DRIFT_ADJUST,
+	RTW_MESH_WORK_MBSS_CHANGED,
+};
+
+#define RTW_MESH_MAX_PEER_CANDIDATES 15 /* aid consideration */
+#define RTW_MESH_MAX_PEER_LINKS 8
+#define RTW_MESH_PEER_LINK_TIMEOUT 20
+
+#define RTW_MESH_PEER_CONF_DISABLED 0 /* special time value means no confirmation ongoing */
+#if CONFIG_RTW_MESH_PEER_BLACKLIST
+#define IS_PEER_CONF_DISABLED(plink) ((plink)->peer_conf_end_time == RTW_MESH_PEER_CONF_DISABLED)
+#define IS_PEER_CONF_TIMEOUT(plink)(!IS_PEER_CONF_DISABLED(plink) && rtw_time_after(rtw_get_current_time(), (plink)->peer_conf_end_time))
+#define SET_PEER_CONF_DISABLED(plink) (plink)->peer_conf_end_time = RTW_MESH_PEER_CONF_DISABLED
+#define SET_PEER_CONF_END_TIME(plink, timeout_ms) \
+	do { \
+		(plink)->peer_conf_end_time = rtw_get_current_time() + rtw_ms_to_systime(timeout_ms); \
+		if ((plink)->peer_conf_end_time == RTW_MESH_PEER_CONF_DISABLED) \
+			(plink)->peer_conf_end_time++; \
+	} while (0)
+#else
+#define IS_PEER_CONF_DISABLED(plink) 1
+#define IS_PEER_CONF_TIMEOUT(plink) 0
+#define SET_PEER_CONF_DISABLED(plink) do {} while (0)
+#define SET_PEER_CONF_END_TIME(plink, timeout_ms) do {} while (0)
+#endif /* CONFIG_RTW_MESH_PEER_BLACKLIST */
+
+#define RTW_MESH_CTO_MGATE_CONF_DISABLED 0 /* special time value means no confirmation ongoing */
+#if CONFIG_RTW_MESH_CTO_MGATE_BLACKLIST
+#define IS_CTO_MGATE_CONF_DISABLED(plink) ((plink)->cto_mgate_conf_end_time == RTW_MESH_CTO_MGATE_CONF_DISABLED)
+#define IS_CTO_MGATE_CONF_TIMEOUT(plink)(!IS_CTO_MGATE_CONF_DISABLED(plink) && rtw_time_after(rtw_get_current_time(), (plink)->cto_mgate_conf_end_time))
+#define SET_CTO_MGATE_CONF_DISABLED(plink) (plink)->cto_mgate_conf_end_time = RTW_MESH_CTO_MGATE_CONF_DISABLED
+#define SET_CTO_MGATE_CONF_END_TIME(plink, timeout_ms) \
+	do { \
+		(plink)->cto_mgate_conf_end_time = rtw_get_current_time() + rtw_ms_to_systime(timeout_ms); \
+		if ((plink)->cto_mgate_conf_end_time == RTW_MESH_CTO_MGATE_CONF_DISABLED) \
+			(plink)->cto_mgate_conf_end_time++; \
+	} while (0)
+#else
+#define IS_CTO_MGATE_CONF_DISABLED(plink) 1
+#define IS_CTO_MGATE_CONF_TIMEOUT(plink) 0
+#define SET_CTO_MGATE_CONF_DISABLED(plink) do {} while (0)
+#define SET_CTO_MGATE_CONF_END_TIME(plink, timeout_ms) do {} while (0)
+#endif /* CONFIG_RTW_MESH_CTO_MGATE_BLACKLIST */
+
+struct mesh_plink_ent {
+	u8 valid;
+	u8 addr[ETH_ALEN];
+	u8 plink_state;
+
+#ifdef CONFIG_RTW_MESH_AEK
+	u8 aek_valid;
+	u8 aek[32];
+#endif
+
+	u16 llid;
+	u16 plid;
+#ifndef CONFIG_RTW_MESH_DRIVER_AID
+	u16 aid; /* aid assigned from upper layer */
+#endif
+	u16 peer_aid; /* aid assigned from peer */
+
+	u8 chosen_pmk[16];
+
+#ifdef CONFIG_RTW_MESH_AEK
+	u8 sel_pcs[4];
+	u8 l_nonce[32];
+	u8 p_nonce[32];
+#endif
+
+#ifdef CONFIG_RTW_MESH_DRIVER_AID
+	u8 *tx_conf_ies;
+	u16 tx_conf_ies_len;
+#endif
+	u8 *rx_conf_ies;
+	u16 rx_conf_ies_len;
+
+	struct wlan_network *scanned;
+
+#if CONFIG_RTW_MESH_PEER_BLACKLIST
+	systime peer_conf_end_time;
+#endif
+#if CONFIG_RTW_MESH_CTO_MGATE_BLACKLIST
+	systime cto_mgate_conf_end_time;
+#endif
+};
+
+#ifdef CONFIG_RTW_MESH_AEK
+#define MESH_PLINK_AEK_VALID(ent) ent->aek_valid
+#else
+#define MESH_PLINK_AEK_VALID(ent) 0
+#endif
+
+struct mesh_plink_pool {
+	_lock lock;
+	u8 num; /* current ent being used */
+	struct mesh_plink_ent ent[RTW_MESH_MAX_PEER_CANDIDATES];
+
+#if CONFIG_RTW_MESH_ACNODE_PREVENT
+	u8 acnode_rsvd;
+#endif
+
+#if CONFIG_RTW_MESH_PEER_BLACKLIST
+	_queue peer_blacklist;
+#endif
+#if CONFIG_RTW_MESH_CTO_MGATE_BLACKLIST
+	_queue cto_mgate_blacklist;
+#endif
+};
+
+struct mesh_peer_sel_policy {
+	u32 scanr_exp_ms;
+
+#if CONFIG_RTW_MESH_ACNODE_PREVENT
+	u8 acnode_prevent;
+	u32 acnode_conf_timeout_ms;
+	u32 acnode_notify_timeout_ms;
+#endif
+
+#if CONFIG_RTW_MESH_OFFCH_CAND
+	u8 offch_cand;
+	u32 offch_find_int_ms; /* 0 means no offch find triggerred by driver self*/
+#endif
+
+#if CONFIG_RTW_MESH_PEER_BLACKLIST
+	u32 peer_conf_timeout_ms;
+	u32 peer_blacklist_timeout_ms;
+#endif
+
+#if CONFIG_RTW_MESH_CTO_MGATE_BLACKLIST
+	u8 cto_mgate_require;
+	u32 cto_mgate_conf_timeout_ms;
+	u32 cto_mgate_blacklist_timeout_ms;
+#endif
+};
+
+/* b2u flags */
+#define RTW_MESH_B2U_ALL		BIT0
+#define RTW_MESH_B2U_GA_UCAST	BIT1 /* Group addressed unicast frame, forward only */
+#define RTW_MESH_B2U_BCAST		BIT2
+#define RTW_MESH_B2U_IP_MCAST	BIT3
+
+#define rtw_msrc_b2u_policy_chk(flags, mda) ( \
+	(flags & RTW_MESH_B2U_ALL) \
+	|| ((flags & RTW_MESH_B2U_BCAST) && is_broadcast_mac_addr(mda)) \
+	|| ((flags & RTW_MESH_B2U_IP_MCAST) && (IP_MCAST_MAC(mda) || ICMPV6_MCAST_MAC(mda))) \
+	)
+
+#define rtw_mfwd_b2u_policy_chk(flags, mda, ucst) ( \
+	(flags & RTW_MESH_B2U_ALL) \
+	|| ((flags & RTW_MESH_B2U_GA_UCAST) && ucst) \
+	|| ((flags & RTW_MESH_B2U_BCAST) && is_broadcast_mac_addr(mda)) \
+	|| ((flags & RTW_MESH_B2U_IP_MCAST) && (IP_MCAST_MAC(mda) || ICMPV6_MCAST_MAC(mda))) \
+	)
+
+/**
+ * @sane_metric_delta: Controlling if trigger additional path check mechanism
+ * @max_root_add_chk_cnt: The retry cnt to send additional root confirmation
+ *	PREQ through old(last) path
+ */
+struct rtw_mesh_cfg {
+	u8 max_peer_links; /* peering limit */
+	u32 plink_timeout; /* seconds */
+
+	u8 dot11MeshTTL;
+	u8 element_ttl;
+	u32 path_refresh_time;
+	u16 dot11MeshHWMPpreqMinInterval;
+	u16 dot11MeshHWMPnetDiameterTraversalTime;
+	u32 dot11MeshHWMPactivePathTimeout;
+	u8 dot11MeshHWMPmaxPREQretries;
+	u16 min_discovery_timeout;
+	u16 dot11MeshHWMPconfirmationInterval;
+	u16 dot11MeshHWMPperrMinInterval;
+	u8 dot11MeshHWMPRootMode;
+	BOOLEAN dot11MeshForwarding;
+	s32 rssi_threshold; /* in dBm, 0: no specified */
+	u16 dot11MeshHWMPRannInterval;
+	BOOLEAN dot11MeshGateAnnouncementProtocol;
+	u32 dot11MeshHWMPactivePathToRootTimeout;
+	u16 dot11MeshHWMProotInterval;
+	u8 path_gate_timeout_factor;
+#ifdef CONFIG_RTW_MESH_ADD_ROOT_CHK
+	u16 sane_metric_delta;
+	u8 max_root_add_chk_cnt;
+#endif
+
+	struct mesh_peer_sel_policy peer_sel_policy;
+
+#if CONFIG_RTW_MESH_DATA_BMC_TO_UC
+	u8 b2u_flags_msrc;
+	u8 b2u_flags_mfwd;
+#endif
+};
+
+struct rtw_mesh_stats {
+	u32 fwded_mcast;		/* Mesh forwarded multicast frames */
+	u32 fwded_unicast;		/* Mesh forwarded unicast frames */
+	u32 fwded_frames;		/* Mesh total forwarded frames */
+	u32 dropped_frames_ttl;	/* Not transmitted since mesh_ttl == 0*/
+	u32 dropped_frames_no_route;	/* Not transmitted, no route found */
+	u32 dropped_frames_congestion;/* Not forwarded due to congestion */
+	u32 dropped_frames_duplicate;
+
+	u32 mrc_del_qlen; /* MRC entry deleted cause by queue length limit */
+};
+
+struct rtw_mrc;
+
+struct rtw_mesh_info {
+	u8 mesh_id[NDIS_802_11_LENGTH_SSID];
+	size_t mesh_id_len;
+	/* Active Path Selection Protocol Identifier */
+	u8 mesh_pp_id;
+	/* Active Path Selection Metric Identifier */
+	u8 mesh_pm_id;
+	/* Congestion Control Mode Identifier */
+	u8 mesh_cc_id;
+	/* Synchronization Protocol Identifier */
+	u8 mesh_sp_id;
+	/* Authentication Protocol Identifier */
+	u8 mesh_auth_id;
+
+	struct mesh_plink_pool plink_ctl;
+
+	u32 mesh_seqnum;
+	/* MSTA's own hwmp sequence number */
+	u32 sn;
+	systime last_preq;
+	systime last_sn_update;
+	systime next_perr;
+	/* Last used Path Discovery ID */
+	u32 preq_id;
+	
+	ATOMIC_T mpaths;
+	struct rtw_mesh_table *mesh_paths;
+	struct rtw_mesh_table *mpp_paths;
+	int mesh_paths_generation;
+	int mpp_paths_generation;
+
+	int num_gates;
+	struct rtw_mesh_path *max_addr_gate;
+	bool max_addr_gate_is_larger_than_self;
+
+	struct rtw_mesh_stats mshstats;
+
+	_queue mpath_tx_queue;
+	u32 mpath_tx_queue_len;
+	struct tasklet_struct mpath_tx_tasklet;
+
+	struct rtw_mrc *mrc;
+
+	_lock mesh_preq_queue_lock;
+	struct rtw_mesh_preq_queue preq_queue;
+	int preq_queue_len;
+};
+
+extern const char *_action_self_protected_str[];
+#define action_self_protected_str(action) ((action < RTW_ACT_SELF_PROTECTED_NUM) ? _action_self_protected_str[action] : _action_self_protected_str[0])
+
+u8 *rtw_set_ie_mesh_id(u8 *buf, u32 *buf_len, const char *mesh_id, u8 id_len);
+u8 *rtw_set_ie_mesh_config(u8 *buf, u32 *buf_len
+	, u8 path_sel_proto, u8 path_sel_metric, u8 congest_ctl_mode, u8 sync_method, u8 auth_proto
+	, u8 num_of_peerings, bool cto_mgate, bool cto_as
+	, bool accept_peerings, bool mcca_sup, bool mcca_en, bool forwarding
+	, bool mbca_en, bool tbtt_adj, bool ps_level);
+
+int rtw_bss_is_same_mbss(WLAN_BSSID_EX *a, WLAN_BSSID_EX *b);
+int rtw_bss_is_candidate_mesh_peer(WLAN_BSSID_EX *self, WLAN_BSSID_EX *target, u8 ch, u8 add_peer);
+
+void rtw_chk_candidate_peer_notify(_adapter *adapter, struct wlan_network *scanned);
+
+void rtw_mesh_peer_status_chk(_adapter *adapter);
+
+#if CONFIG_RTW_MESH_ACNODE_PREVENT
+void rtw_mesh_update_scanned_acnode_status(_adapter *adapter, struct wlan_network *scanned);
+bool rtw_mesh_scanned_is_acnode_confirmed(_adapter *adapter, struct wlan_network *scanned);
+bool rtw_mesh_acnode_prevent_allow_sacrifice(_adapter *adapter);
+struct sta_info *rtw_mesh_acnode_prevent_pick_sacrifice(_adapter *adapter);
+void dump_mesh_acnode_prevent_settings(void *sel, _adapter *adapter);
+#endif
+
+#if CONFIG_RTW_MESH_OFFCH_CAND
+u8 rtw_mesh_offch_candidate_accepted(_adapter *adapter);
+u8 rtw_mesh_select_operating_ch(_adapter *adapter);
+void dump_mesh_offch_cand_settings(void *sel, _adapter *adapter);
+#endif
+
+#if CONFIG_RTW_MESH_PEER_BLACKLIST
+int rtw_mesh_peer_blacklist_add(_adapter *adapter, const u8 *addr);
+int rtw_mesh_peer_blacklist_del(_adapter *adapter, const u8 *addr);
+int rtw_mesh_peer_blacklist_search(_adapter *adapter, const u8 *addr);
+void rtw_mesh_peer_blacklist_flush(_adapter *adapter);
+void dump_mesh_peer_blacklist(void *sel, _adapter *adapter);
+void dump_mesh_peer_blacklist_settings(void *sel, _adapter *adapter);
+#endif
+#if CONFIG_RTW_MESH_CTO_MGATE_BLACKLIST
+u8 rtw_mesh_cto_mgate_required(_adapter *adapter);
+u8 rtw_mesh_cto_mgate_network_filter(_adapter *adapter, struct wlan_network *scanned);
+int rtw_mesh_cto_mgate_blacklist_add(_adapter *adapter, const u8 *addr);
+int rtw_mesh_cto_mgate_blacklist_del(_adapter *adapter, const u8 *addr);
+int rtw_mesh_cto_mgate_blacklist_search(_adapter *adapter, const u8 *addr);
+void rtw_mesh_cto_mgate_blacklist_flush(_adapter *adapter);
+void dump_mesh_cto_mgate_blacklist(void *sel, _adapter *adapter);
+void dump_mesh_cto_mgate_blacklist_settings(void *sel, _adapter *adapter);
+#endif
+void dump_mesh_peer_sel_policy(void *sel, _adapter *adapter);
+void dump_mesh_networks(void *sel, _adapter *adapter);
+
+void rtw_mesh_adjust_chbw(u8 req_ch, u8 *req_bw, u8 *req_offset);
+
+int rtw_sae_check_frames(_adapter *adapter, const u8 *buf, u32 len, u8 tx);
+int rtw_mesh_check_frames_tx(_adapter *adapter, const u8 **buf, size_t *len);
+int rtw_mesh_check_frames_rx(_adapter *adapter, const u8 *buf, size_t len);
+
+int rtw_mesh_on_auth(_adapter *adapter, union recv_frame *rframe);
+unsigned int on_action_self_protected(_adapter *adapter, union recv_frame *rframe);
+
+bool rtw_mesh_update_bss_peering_status(_adapter *adapter, WLAN_BSSID_EX *bss);
+bool rtw_mesh_update_bss_formation_info(_adapter *adapter, WLAN_BSSID_EX *bss);
+bool rtw_mesh_update_bss_forwarding_state(_adapter *adapter, WLAN_BSSID_EX *bss);
+
+struct mesh_plink_ent *_rtw_mesh_plink_get(_adapter *adapter, const u8 *hwaddr);
+struct mesh_plink_ent *rtw_mesh_plink_get(_adapter *adapter, const u8 *hwaddr);
+struct mesh_plink_ent *rtw_mesh_plink_get_no_estab_by_idx(_adapter *adapter, u8 idx);
+int _rtw_mesh_plink_add(_adapter *adapter, const u8 *hwaddr);
+int rtw_mesh_plink_add(_adapter *adapter, const u8 *hwaddr);
+int rtw_mesh_plink_set_state(_adapter *adapter, const u8 *hwaddr, u8 state);
+#ifdef CONFIG_RTW_MESH_AEK
+int rtw_mesh_plink_set_aek(_adapter *adapter, const u8 *hwaddr, const u8 *aek);
+#endif
+#if CONFIG_RTW_MESH_PEER_BLACKLIST
+int rtw_mesh_plink_set_peer_conf_timeout(_adapter *adapter, const u8 *hwaddr);
+#endif
+void _rtw_mesh_plink_del_ent(_adapter *adapter, struct mesh_plink_ent *ent);
+int rtw_mesh_plink_del(_adapter *adapter, const u8 *hwaddr);
+void rtw_mesh_plink_ctl_init(_adapter *adapter);
+void rtw_mesh_plink_ctl_deinit(_adapter *adapter);
+void dump_mesh_plink_ctl(void *sel, _adapter *adapter);
+
+int rtw_mesh_peer_establish(_adapter *adapter, struct mesh_plink_ent *plink, struct sta_info *sta);
+void _rtw_mesh_expire_peer_ent(_adapter *adapter, struct mesh_plink_ent *plink);
+void rtw_mesh_expire_peer(_adapter *adapter, const u8 *peer_addr);
+u8 rtw_mesh_ps_annc(_adapter *adapter, u8 ps);
+
+unsigned int on_action_mesh(_adapter *adapter, union recv_frame *rframe);
+
+void rtw_mesh_cfg_init(_adapter *adapter);
+void rtw_mesh_cfg_init_max_peer_links(_adapter *adapter, u8 stack_conf);
+void rtw_mesh_cfg_init_plink_timeout(_adapter *adapter, u32 stack_conf);
+void rtw_mesh_init_mesh_info(_adapter *adapter);
+void rtw_mesh_deinit_mesh_info(_adapter *adapter);
+
+#if CONFIG_RTW_MESH_DATA_BMC_TO_UC
+void dump_mesh_b2u_flags(void *sel, _adapter *adapter);
+#endif
+
+int rtw_mesh_addr_resolve(_adapter *adapter, struct xmit_frame *xframe, _pkt *pkt, _list *b2u_list);
+
+s8 rtw_mesh_tx_set_whdr_mctrl_len(u8 mesh_frame_mode, struct pkt_attrib *attrib);
+void rtw_mesh_tx_build_mctrl(_adapter *adapter, struct pkt_attrib *attrib, u8 *buf);
+u8 rtw_mesh_tx_build_whdr(_adapter *adapter, struct pkt_attrib *attrib
+	, u16 *fctrl, struct rtw_ieee80211_hdr *whdr);
+
+int rtw_mesh_rx_data_validate_hdr(_adapter *adapter, union recv_frame *rframe, struct sta_info **sta);
+int rtw_mesh_rx_data_validate_mctrl(_adapter *adapter, union recv_frame *rframe
+	, const struct rtw_ieee80211s_hdr *mctrl, const u8 *mda, const u8 *msa
+	, u8 *mctrl_len, const u8 **da, const u8 **sa);
+int rtw_mesh_rx_validate_mctrl_non_amsdu(_adapter *adapter, union recv_frame *rframe);
+
+int rtw_mesh_rx_msdu_act_check(union recv_frame *rframe
+	, const u8 *mda, const u8 *msa
+	, const u8 *da, const u8 *sa
+	, struct rtw_ieee80211s_hdr *mctrl
+	, struct xmit_frame **fwd_frame, _list *b2u_list);
+
+void dump_mesh_stats(void *sel, _adapter *adapter);
+
+#if defined(PLATFORM_LINUX) && (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 32))
+#define rtw_lockdep_assert_held(l) lockdep_assert_held(l)
+#define rtw_lockdep_is_held(l) lockdep_is_held(l)
+#else
+#error "TBD\n"
+#endif
+
+#include "rtw_mesh_pathtbl.h"
+#include "rtw_mesh_hwmp.h"
+#endif /* __RTW_MESH_H_ */
+
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/core/mesh/rtw_mesh_hwmp.c linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/core/mesh/rtw_mesh_hwmp.c
--- linux-5.6.3/3rdparty/rtl8821ce/core/mesh/rtw_mesh_hwmp.c	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/core/mesh/rtw_mesh_hwmp.c	2020-04-10 16:35:06.769657873 +0300
@@ -0,0 +1,1665 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#define _RTW_HWMP_C_
+
+#ifdef CONFIG_RTW_MESH
+#include <drv_types.h>
+#include <hal_data.h>
+
+#define RTW_TEST_FRAME_LEN	8192
+#define RTW_MAX_METRIC	0xffffffff
+#define RTW_ARITH_SHIFT	8
+#define RTW_LINK_FAIL_THRESH 95
+#define RTW_MAX_PREQ_QUEUE_LEN	64
+#define RTW_ATLM_REQ_CYCLE 1000
+
+#define rtw_ilog2(n)			\
+(					\
+	(n) < 2 ? 0 :			\
+	(n) & (1ULL << 63) ? 63 :	\
+	(n) & (1ULL << 62) ? 62 :	\
+	(n) & (1ULL << 61) ? 61 :	\
+	(n) & (1ULL << 60) ? 60 :	\
+	(n) & (1ULL << 59) ? 59 :	\
+	(n) & (1ULL << 58) ? 58 :	\
+	(n) & (1ULL << 57) ? 57 :	\
+	(n) & (1ULL << 56) ? 56 :	\
+	(n) & (1ULL << 55) ? 55 :	\
+	(n) & (1ULL << 54) ? 54 :	\
+	(n) & (1ULL << 53) ? 53 :	\
+	(n) & (1ULL << 52) ? 52 :	\
+	(n) & (1ULL << 51) ? 51 :	\
+	(n) & (1ULL << 50) ? 50 :	\
+	(n) & (1ULL << 49) ? 49 :	\
+	(n) & (1ULL << 48) ? 48 :	\
+	(n) & (1ULL << 47) ? 47 :	\
+	(n) & (1ULL << 46) ? 46 :	\
+	(n) & (1ULL << 45) ? 45 :	\
+	(n) & (1ULL << 44) ? 44 :	\
+	(n) & (1ULL << 43) ? 43 :	\
+	(n) & (1ULL << 42) ? 42 :	\
+	(n) & (1ULL << 41) ? 41 :	\
+	(n) & (1ULL << 40) ? 40 :	\
+	(n) & (1ULL << 39) ? 39 :	\
+	(n) & (1ULL << 38) ? 38 :	\
+	(n) & (1ULL << 37) ? 37 :	\
+	(n) & (1ULL << 36) ? 36 :	\
+	(n) & (1ULL << 35) ? 35 :	\
+	(n) & (1ULL << 34) ? 34 :	\
+	(n) & (1ULL << 33) ? 33 :	\
+	(n) & (1ULL << 32) ? 32 :	\
+	(n) & (1ULL << 31) ? 31 :	\
+	(n) & (1ULL << 30) ? 30 :	\
+	(n) & (1ULL << 29) ? 29 :	\
+	(n) & (1ULL << 28) ? 28 :	\
+	(n) & (1ULL << 27) ? 27 :	\
+	(n) & (1ULL << 26) ? 26 :	\
+	(n) & (1ULL << 25) ? 25 :	\
+	(n) & (1ULL << 24) ? 24 :	\
+	(n) & (1ULL << 23) ? 23 :	\
+	(n) & (1ULL << 22) ? 22 :	\
+	(n) & (1ULL << 21) ? 21 :	\
+	(n) & (1ULL << 20) ? 20 :	\
+	(n) & (1ULL << 19) ? 19 :	\
+	(n) & (1ULL << 18) ? 18 :	\
+	(n) & (1ULL << 17) ? 17 :	\
+	(n) & (1ULL << 16) ? 16 :	\
+	(n) & (1ULL << 15) ? 15 :	\
+	(n) & (1ULL << 14) ? 14 :	\
+	(n) & (1ULL << 13) ? 13 :	\
+	(n) & (1ULL << 12) ? 12 :	\
+	(n) & (1ULL << 11) ? 11 :	\
+	(n) & (1ULL << 10) ? 10 :	\
+	(n) & (1ULL <<  9) ?  9 :	\
+	(n) & (1ULL <<  8) ?  8 :	\
+	(n) & (1ULL <<  7) ?  7 :	\
+	(n) & (1ULL <<  6) ?  6 :	\
+	(n) & (1ULL <<  5) ?  5 :	\
+	(n) & (1ULL <<  4) ?  4 :	\
+	(n) & (1ULL <<  3) ?  3 :	\
+	(n) & (1ULL <<  2) ?  2 :	\
+	1				\
+)
+
+enum rtw_mpath_frame_type {
+	RTW_MPATH_PREQ = 0,
+	RTW_MPATH_PREP,
+	RTW_MPATH_PERR,
+	RTW_MPATH_RANN
+};
+
+static inline u32 rtw_u32_field_get(const u8 *preq_elem, int shift, BOOLEAN ae)
+{
+	if (ae)
+		shift += 6;
+	return LE_BITS_TO_4BYTE(preq_elem + shift, 0, 32);
+}
+
+static inline u16 rtw_u16_field_get(const u8 *preq_elem, int shift, BOOLEAN ae)
+{
+	if (ae)
+		shift += 6;
+	return LE_BITS_TO_2BYTE(preq_elem + shift, 0, 16);
+}
+
+/* HWMP IE processing macros */
+#define RTW_AE_F			(1<<6)
+#define RTW_AE_F_SET(x)			(*x & RTW_AE_F)
+#define RTW_PREQ_IE_FLAGS(x)		(*(x))
+#define RTW_PREQ_IE_HOPCOUNT(x)		(*(x + 1))
+#define RTW_PREQ_IE_TTL(x)		(*(x + 2))
+#define RTW_PREQ_IE_PREQ_ID(x)		rtw_u32_field_get(x, 3, 0)
+#define RTW_PREQ_IE_ORIG_ADDR(x)	(x + 7)
+#define RTW_PREQ_IE_ORIG_SN(x)		rtw_u32_field_get(x, 13, 0)
+#define RTW_PREQ_IE_LIFETIME(x)		rtw_u32_field_get(x, 17, RTW_AE_F_SET(x))
+#define RTW_PREQ_IE_METRIC(x) 		rtw_u32_field_get(x, 21, RTW_AE_F_SET(x))
+#define RTW_PREQ_IE_TARGET_F(x)		(*(RTW_AE_F_SET(x) ? x + 32 : x + 26))
+#define RTW_PREQ_IE_TARGET_ADDR(x) 	(RTW_AE_F_SET(x) ? x + 33 : x + 27)
+#define RTW_PREQ_IE_TARGET_SN(x) 	rtw_u32_field_get(x, 33, RTW_AE_F_SET(x))
+
+#define RTW_PREP_IE_FLAGS(x)		RTW_PREQ_IE_FLAGS(x)
+#define RTW_PREP_IE_HOPCOUNT(x)		RTW_PREQ_IE_HOPCOUNT(x)
+#define RTW_PREP_IE_TTL(x)		RTW_PREQ_IE_TTL(x)
+#define RTW_PREP_IE_ORIG_ADDR(x)	(RTW_AE_F_SET(x) ? x + 27 : x + 21)
+#define RTW_PREP_IE_ORIG_SN(x)		rtw_u32_field_get(x, 27, RTW_AE_F_SET(x))
+#define RTW_PREP_IE_LIFETIME(x)		rtw_u32_field_get(x, 13, RTW_AE_F_SET(x))
+#define RTW_PREP_IE_METRIC(x)		rtw_u32_field_get(x, 17, RTW_AE_F_SET(x))
+#define RTW_PREP_IE_TARGET_ADDR(x)	(x + 3)
+#define RTW_PREP_IE_TARGET_SN(x)	rtw_u32_field_get(x, 9, 0)
+
+#define RTW_PERR_IE_TTL(x)		(*(x))
+#define RTW_PERR_IE_TARGET_FLAGS(x)	(*(x + 2))
+#define RTW_PERR_IE_TARGET_ADDR(x)	(x + 3)
+#define RTW_PERR_IE_TARGET_SN(x)	rtw_u32_field_get(x, 9, 0)
+#define RTW_PERR_IE_TARGET_RCODE(x)	rtw_u16_field_get(x, 13, 0)
+
+#define RTW_TU_TO_SYSTIME(x)	(rtw_us_to_systime((x) * 1024))
+#define RTW_TU_TO_EXP_TIME(x)	(rtw_get_current_time() + RTW_TU_TO_SYSTIME(x))
+#define RTW_MSEC_TO_TU(x) (x*1000/1024)
+#define RTW_SN_GT(x, y) ((s32)(y - x) < 0)
+#define RTW_SN_LT(x, y) ((s32)(x - y) < 0)
+#define RTW_MAX_SANE_SN_DELTA 32
+
+static inline u32 RTW_SN_DELTA(u32 x, u32 y)
+{
+	return x >= y ? x - y : y - x;
+}
+
+#define rtw_net_traversal_jiffies(adapter) \
+	rtw_ms_to_systime(adapter->mesh_cfg.dot11MeshHWMPnetDiameterTraversalTime)
+#define rtw_default_lifetime(adapter) \
+	RTW_MSEC_TO_TU(adapter->mesh_cfg.dot11MeshHWMPactivePathTimeout)
+#define rtw_min_preq_int_jiff(adapter) \
+	(rtw_ms_to_systime(adapter->mesh_cfg.dot11MeshHWMPpreqMinInterval))
+#define rtw_max_preq_retries(adapter) (adapter->mesh_cfg.dot11MeshHWMPmaxPREQretries)
+#define rtw_disc_timeout_jiff(adapter) \
+	rtw_ms_to_systime(adapter->mesh_cfg.min_discovery_timeout)
+#define rtw_root_path_confirmation_jiffies(adapter) \
+	rtw_ms_to_systime(adapter->mesh_cfg.dot11MeshHWMPconfirmationInterval)
+
+static inline BOOLEAN rtw_ether_addr_equal(const u8 *addr1, const u8 *addr2)
+{
+	return _rtw_memcmp(addr1, addr2, ETH_ALEN);
+}
+
+#ifdef PLATFORM_LINUX
+#define rtw_print_ratelimit()	printk_ratelimit()
+#define rtw_mod_timer(ptimer, expires) mod_timer(&(ptimer)->timer, expires)
+#else
+
+#endif
+
+#define RTW_MESH_EWMA_PRECISION 20
+#define RTW_MESH_EWMA_WEIGHT_RCP 8
+#define RTW_TOTAL_PKT_MIN_THRESHOLD 1
+inline void rtw_ewma_err_rate_init(struct rtw_ewma_err_rate *e)
+{
+	e->internal = 0;
+}
+inline unsigned long rtw_ewma_err_rate_read(struct rtw_ewma_err_rate *e)
+{
+	return e->internal >> (RTW_MESH_EWMA_PRECISION);
+}
+inline void rtw_ewma_err_rate_add(struct rtw_ewma_err_rate *e,
+				  unsigned long val)
+{
+	unsigned long internal = e->internal;
+	unsigned long weight_rcp = rtw_ilog2(RTW_MESH_EWMA_WEIGHT_RCP);
+	unsigned long precision = RTW_MESH_EWMA_PRECISION;
+
+	(e->internal) = internal ? (((internal << weight_rcp) - internal) +
+			(val << precision)) >> weight_rcp :
+			(val << precision);
+}
+
+static const u8 bcast_addr[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
+
+static int rtw_mesh_path_sel_frame_tx(enum rtw_mpath_frame_type mpath_action, u8 flags,
+				      const u8 *originator_addr, u32 originator_sn,
+				      u8 target_flags, const u8 *target,
+				      u32 target_sn, const u8 *da, u8 hopcount, u8 ttl,
+				      u32 lifetime, u32 metric, u32 preq_id, 
+				      _adapter *adapter)
+{
+	struct xmit_priv *pxmitpriv = &(adapter->xmitpriv);
+	struct mlme_ext_priv *pmlmeext = &(adapter->mlmeextpriv);
+	struct xmit_frame *pmgntframe = NULL;
+	struct rtw_ieee80211_hdr *pwlanhdr = NULL;
+	struct pkt_attrib *pattrib = NULL;
+	u8 category = RTW_WLAN_CATEGORY_MESH;
+	u8 action = RTW_ACT_MESH_HWMP_PATH_SELECTION;
+	u16 *fctrl = NULL;
+	u8 *pos, ie_len;
+
+
+	pmgntframe = alloc_mgtxmitframe(pxmitpriv);
+	if (pmgntframe == NULL)
+		return -1;
+
+	pattrib = &pmgntframe->attrib;
+	update_mgntframe_attrib(adapter, pattrib);
+	_rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET);
+
+	pos = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET;
+	pwlanhdr = (struct rtw_ieee80211_hdr *)pos;
+
+
+	fctrl = &(pwlanhdr->frame_ctl);
+	*(fctrl) = 0;
+
+	_rtw_memcpy(pwlanhdr->addr1, da, ETH_ALEN);
+	_rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(adapter), ETH_ALEN);
+	_rtw_memcpy(pwlanhdr->addr3, adapter_mac_addr(adapter), ETH_ALEN);
+
+	SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq);
+	pmlmeext->mgnt_seq++;
+	set_frame_sub_type(pos, WIFI_ACTION);
+
+	pos += sizeof(struct rtw_ieee80211_hdr_3addr);
+	pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr);
+
+	pos = rtw_set_fixed_ie(pos, 1, &(category), &(pattrib->pktlen));
+	pos = rtw_set_fixed_ie(pos, 1, &(action), &(pattrib->pktlen));
+
+	switch (mpath_action) {
+	case RTW_MPATH_PREQ:
+		RTW_HWMP_DBG("sending PREQ to "MAC_FMT"\n", MAC_ARG(target));
+		ie_len = 37;
+		pattrib->pktlen += (ie_len + 2);
+		*pos++ = WLAN_EID_PREQ;
+		break;
+	case RTW_MPATH_PREP:
+		RTW_HWMP_DBG("sending PREP to "MAC_FMT"\n", MAC_ARG(originator_addr));
+		ie_len = 31;
+		pattrib->pktlen += (ie_len + 2);
+		*pos++ = WLAN_EID_PREP;
+		break;
+	case RTW_MPATH_RANN:
+		RTW_HWMP_DBG("sending RANN from "MAC_FMT"\n", MAC_ARG(originator_addr));
+		ie_len = sizeof(struct rtw_ieee80211_rann_ie);
+		pattrib->pktlen += (ie_len + 2);
+		*pos++ = WLAN_EID_RANN;
+		break;
+	default:
+		rtw_free_xmitbuf(pxmitpriv, pmgntframe->pxmitbuf);
+		rtw_free_xmitframe(pxmitpriv, pmgntframe);
+		return _FAIL;
+	}
+	*pos++ = ie_len;
+	*pos++ = flags;
+	*pos++ = hopcount;
+	*pos++ = ttl;
+	if (mpath_action == RTW_MPATH_PREP) {
+		_rtw_memcpy(pos, target, ETH_ALEN);
+		pos += ETH_ALEN;
+		*(u32 *)pos = cpu_to_le32(target_sn);
+		pos += 4;
+	} else {
+		if (mpath_action == RTW_MPATH_PREQ) {
+			*(u32 *)pos = cpu_to_le32(preq_id);
+			pos += 4;
+		}
+		_rtw_memcpy(pos, originator_addr, ETH_ALEN);
+		pos += ETH_ALEN;
+		*(u32 *)pos = cpu_to_le32(originator_sn);
+		pos += 4;
+	}
+	*(u32 *)pos = cpu_to_le32(lifetime);
+	pos += 4;
+	*(u32 *)pos = cpu_to_le32(metric);
+	pos += 4;
+	if (mpath_action == RTW_MPATH_PREQ) {
+		*pos++ = 1; /* support only 1 destination now */
+		*pos++ = target_flags;
+		_rtw_memcpy(pos, target, ETH_ALEN);
+		pos += ETH_ALEN;
+		*(u32 *)pos = cpu_to_le32(target_sn);
+		pos += 4;
+	} else if (mpath_action == RTW_MPATH_PREP) {
+		_rtw_memcpy(pos, originator_addr, ETH_ALEN);
+		pos += ETH_ALEN;
+		*(u32 *)pos = cpu_to_le32(originator_sn);
+		pos += 4;
+	}
+
+	pattrib->last_txcmdsz = pattrib->pktlen;
+	dump_mgntframe(adapter, pmgntframe);
+	return 0;
+}
+
+int rtw_mesh_path_error_tx(_adapter *adapter,
+			   u8 ttl, const u8 *target, u32 target_sn,
+			   u16 perr_reason_code, const u8 *ra)
+{
+
+	struct xmit_priv *pxmitpriv = &(adapter->xmitpriv);
+	struct mlme_ext_priv *pmlmeext = &(adapter->mlmeextpriv);
+	struct xmit_frame *pmgntframe = NULL;
+	struct rtw_ieee80211_hdr *pwlanhdr = NULL;
+	struct pkt_attrib *pattrib = NULL;
+	struct rtw_mesh_info *minfo = &adapter->mesh_info;
+	u8 category = RTW_WLAN_CATEGORY_MESH;
+	u8 action = RTW_ACT_MESH_HWMP_PATH_SELECTION;
+	u8 *pos, ie_len;
+	u16 *fctrl = NULL;
+
+	if (rtw_time_before(rtw_get_current_time(), minfo->next_perr))
+		return -1;
+
+	pmgntframe = alloc_mgtxmitframe(pxmitpriv);
+	if (pmgntframe == NULL)
+		return -1;
+
+	pattrib = &pmgntframe->attrib;
+	update_mgntframe_attrib(adapter, pattrib);
+	_rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET);
+
+	pos = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET;
+	pwlanhdr = (struct rtw_ieee80211_hdr *)pos;
+
+	fctrl = &(pwlanhdr->frame_ctl);
+	*(fctrl) = 0;
+
+	_rtw_memcpy(pwlanhdr->addr1, ra, ETH_ALEN);
+	_rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(adapter), ETH_ALEN);
+	_rtw_memcpy(pwlanhdr->addr3, adapter_mac_addr(adapter), ETH_ALEN);
+
+	SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq);
+	pmlmeext->mgnt_seq++;
+	set_frame_sub_type(pos, WIFI_ACTION);
+
+	pos += sizeof(struct rtw_ieee80211_hdr_3addr);
+	pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr);
+
+	pos = rtw_set_fixed_ie(pos, 1, &(category), &(pattrib->pktlen));
+	pos = rtw_set_fixed_ie(pos, 1, &(action), &(pattrib->pktlen));
+
+	ie_len = 15;
+	pattrib->pktlen += (2 + ie_len);
+	*pos++ = WLAN_EID_PERR;
+	*pos++ = ie_len;
+	/* ttl */
+	*pos++ = ttl;
+	/* The Number of Destinations N */
+	*pos++ = 1;
+	/* Flags format | B7 | B6 | B5:B0 | = | rsvd | AE | rsvd | */
+	*pos = 0;
+	pos++;
+	_rtw_memcpy(pos, target, ETH_ALEN);
+	pos += ETH_ALEN;
+	*(u32 *)pos = cpu_to_le32(target_sn);
+	pos += 4;
+	*(u16 *)pos = cpu_to_le16(perr_reason_code);
+
+	adapter->mesh_info.next_perr = RTW_TU_TO_EXP_TIME(
+				adapter->mesh_cfg.dot11MeshHWMPperrMinInterval);
+	pattrib->last_txcmdsz = pattrib->pktlen;
+	/* Send directly. Rewrite it if deferred tx is needed */
+	dump_mgntframe(adapter, pmgntframe);
+
+	RTW_HWMP_DBG("TX PERR toward "MAC_FMT", ra = "MAC_FMT"\n", MAC_ARG(target), MAC_ARG(ra));
+	
+	return 0;
+}
+
+static u32 rtw_get_vht_bitrate(u8 mcs, u8 bw, u8 nss, u8 sgi)
+{
+	static const u32 base[4][10] = {
+		{   6500000,
+		   13000000,
+		   19500000,
+		   26000000,
+		   39000000,
+		   52000000,
+		   58500000,
+		   65000000,
+		   78000000,
+		/* not in the spec, but some devices use this: */
+		   86500000,
+		},
+		{  13500000,
+		   27000000,
+		   40500000,
+		   54000000,
+		   81000000,
+		  108000000,
+		  121500000,
+		  135000000,
+		  162000000,
+		  180000000,
+		},
+		{  29300000,
+		   58500000,
+		   87800000,
+		  117000000,
+		  175500000,
+		  234000000,
+		  263300000,
+		  292500000,
+		  351000000,
+		  390000000,
+		},
+		{  58500000,
+		  117000000,
+		  175500000,
+		  234000000,
+		  351000000,
+		  468000000,
+		  526500000,
+		  585000000,
+		  702000000,
+		  780000000,
+		},
+	};
+	u32 bitrate;
+	int bw_idx;
+
+	if (mcs > 9) {
+		RTW_HWMP_INFO("Invalid mcs = %d\n", mcs);
+		return 0;
+	}
+
+	if (nss > 4 || nss < 1) {
+		RTW_HWMP_INFO("Now only support nss = 1, 2, 3, 4\n");
+	}
+
+	switch (bw) {
+	case CHANNEL_WIDTH_160:
+		bw_idx = 3;
+		break;
+	case CHANNEL_WIDTH_80:
+		bw_idx = 2;
+		break;
+	case CHANNEL_WIDTH_40:
+		bw_idx = 1;
+		break;
+	case CHANNEL_WIDTH_20:
+		bw_idx = 0;
+		break;
+	default:
+		RTW_HWMP_INFO("bw = %d currently not supported\n", bw);
+		return 0;
+	}
+
+	bitrate = base[bw_idx][mcs];
+	bitrate *= nss;
+
+	if (sgi)
+		bitrate = (bitrate / 9) * 10;
+
+	/* do NOT round down here */
+	return (bitrate + 50000) / 100000;
+}
+
+static u32 rtw_get_ht_bitrate(u8 mcs, u8 bw, u8 sgi)
+{
+	int modulation, streams, bitrate;
+
+	/* the formula below does only work for MCS values smaller than 32 */
+	if (mcs >= 32) {
+		RTW_HWMP_INFO("Invalid mcs = %d\n", mcs);
+		return 0;
+	}
+
+	if (bw > 1) {
+		RTW_HWMP_INFO("Now HT only support bw = 0(20Mhz), 1(40Mhz)\n");
+		return 0;
+	}
+
+	modulation = mcs & 7;
+	streams = (mcs >> 3) + 1;
+
+	bitrate = (bw == 1) ? 13500000 : 6500000;
+
+	if (modulation < 4)
+		bitrate *= (modulation + 1);
+	else if (modulation == 4)
+		bitrate *= (modulation + 2);
+	else
+		bitrate *= (modulation + 3);
+
+	bitrate *= streams;
+
+	if (sgi)
+		bitrate = (bitrate / 9) * 10;
+
+	/* do NOT round down here */
+	return (bitrate + 50000) / 100000;
+}
+
+/**
+ * @bw: 0(20Mhz), 1(40Mhz), 2(80Mhz), 3(160Mhz)
+ * @rate_idx: DESC_RATEXXXX & 0x7f
+ * @sgi: DESC_RATEXXXX >> 7
+ * Returns: bitrate in 100kbps
+ */
+static u32 rtw_desc_rate_to_bitrate(u8 bw, u8 rate_idx, u8 sgi)
+{
+	u32 bitrate;
+
+	if (rate_idx <= DESC_RATE54M){
+		u16 ofdm_rate[12] = {10, 20, 55, 110,
+			60, 90, 120, 180, 240, 360, 480, 540};
+		bitrate = ofdm_rate[rate_idx];
+	} else if ((DESC_RATEMCS0 <= rate_idx) &&
+		   (rate_idx <= DESC_RATEMCS31)) {
+		u8 mcs = rate_idx - DESC_RATEMCS0;
+		bitrate = rtw_get_ht_bitrate(mcs, bw, sgi);
+	} else if ((DESC_RATEVHTSS1MCS0 <= rate_idx) &&
+		   (rate_idx <= DESC_RATEVHTSS4MCS9)) {
+		u8 mcs = (rate_idx - DESC_RATEVHTSS1MCS0) % 10;
+		u8 nss = ((rate_idx - DESC_RATEVHTSS1MCS0) / 10) + 1;
+		bitrate = rtw_get_vht_bitrate(mcs, bw, nss, sgi);
+	} else {
+		/* 60Ghz ??? */
+		bitrate = 1;
+	}
+
+	return bitrate;
+}
+
+static u32 rtw_airtime_link_metric_get(_adapter *adapter, struct sta_info *sta)
+{
+	struct dm_struct *dm = adapter_to_phydm(adapter);
+	int device_constant = phydm_get_plcp(dm, sta->cmn.mac_id) << RTW_ARITH_SHIFT;
+	u32 test_frame_len = RTW_TEST_FRAME_LEN << RTW_ARITH_SHIFT;
+	u32 s_unit = 1 << RTW_ARITH_SHIFT;
+	u32 err;
+	u16 rate;
+	u32 tx_time, estimated_retx;
+	u64 result;
+	/* The fail_avg should <= 100 here */
+	u32 fail_avg = (u32)rtw_ewma_err_rate_read(&sta->metrics.err_rate);
+
+	if (fail_avg > RTW_LINK_FAIL_THRESH)
+		return RTW_MAX_METRIC;
+
+	rate = sta->metrics.data_rate;
+	/* rate unit is 100Kbps, min rate = 10 */
+	if (rate < 10) {
+		RTW_HWMP_INFO("rate = %d\n", rate);
+		return RTW_MAX_METRIC;
+	}
+
+	err = (fail_avg << RTW_ARITH_SHIFT) / 100;
+
+	/* test_frame_len*10 to adjust the unit of rate(100kbps/unit) */
+	tx_time = (device_constant + 10 * test_frame_len / rate);
+	estimated_retx = ((1 << (2 * RTW_ARITH_SHIFT)) / (s_unit - err));
+	result = (tx_time * estimated_retx) >> (2 * RTW_ARITH_SHIFT);
+	/* Convert us to 0.01 TU(10.24us). x/10.24 = x*100/1024 */
+	result = (result * 100) >> 10;
+
+	return (u32)result;
+}
+
+void rtw_ieee80211s_update_metric(_adapter *adapter, u8 mac_id,
+				  u8 per, u8 rate,
+				  u8 bw, u8 total_pkt)
+{
+	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
+	struct macid_ctl_t *macid_ctl = dvobj_to_macidctl(dvobj);
+	struct sta_info *sta;
+	u8 rate_idx;
+	u8 sgi;
+
+	sta = macid_ctl->sta[mac_id];
+	if (!sta)
+		return;
+
+	/* if RA, use reported rate */
+	if (adapter->fix_rate == 0xff) {
+		rate_idx = rate & 0x7f;
+		sgi = rate >> 7;
+	} else {
+		rate_idx = adapter->fix_rate & 0x7f;
+		sgi = adapter->fix_rate >> 7;
+	}
+	sta->metrics.data_rate = rtw_desc_rate_to_bitrate(bw, rate_idx, sgi);
+
+	if (total_pkt < RTW_TOTAL_PKT_MIN_THRESHOLD)
+		return;
+
+	/* TBD: sta->metrics.overhead = phydm_get_plcp(void *dm_void, u16 macid); */
+	sta->metrics.total_pkt = total_pkt;
+
+	rtw_ewma_err_rate_add(&sta->metrics.err_rate, per);
+	if (rtw_ewma_err_rate_read(&sta->metrics.err_rate) > 
+			RTW_LINK_FAIL_THRESH)
+		rtw_mesh_plink_broken(sta);
+}
+
+static void rtw_hwmp_preq_frame_process(_adapter *adapter,
+					struct rtw_ieee80211_hdr_3addr *mgmt,
+					const u8 *preq_elem, u32 originator_metric)
+{
+	struct rtw_mesh_info *minfo = &adapter->mesh_info;
+	struct rtw_mesh_cfg *mshcfg = &adapter->mesh_cfg;
+	struct rtw_mesh_path *path = NULL;
+	const u8 *target_addr, *originator_addr;
+	const u8 *da;
+	u8 target_flags, ttl, flags, to_gate_ask = 0;
+	u32 originator_sn, target_sn, lifetime, target_metric = 0;
+	BOOLEAN reply = _FALSE;
+	BOOLEAN forward = _TRUE;
+	BOOLEAN preq_is_gate;
+
+	/* Update target SN, if present */
+	target_addr = RTW_PREQ_IE_TARGET_ADDR(preq_elem);
+	originator_addr = RTW_PREQ_IE_ORIG_ADDR(preq_elem);
+	target_sn = RTW_PREQ_IE_TARGET_SN(preq_elem);
+	originator_sn = RTW_PREQ_IE_ORIG_SN(preq_elem);
+	target_flags = RTW_PREQ_IE_TARGET_F(preq_elem);
+	/* PREQ gate announcements */
+	flags = RTW_PREQ_IE_FLAGS(preq_elem);
+	preq_is_gate = !!(flags & RTW_IEEE80211_PREQ_IS_GATE_FLAG);
+
+	RTW_HWMP_DBG("received PREQ from "MAC_FMT"\n", MAC_ARG(originator_addr));
+
+	if (rtw_ether_addr_equal(target_addr, adapter_mac_addr(adapter))) {
+		RTW_HWMP_DBG("PREQ is for us\n");
+#ifdef CONFIG_RTW_MESH_ON_DMD_GANN
+		rtw_rcu_read_lock();
+		path = rtw_mesh_path_lookup(adapter, originator_addr);
+		if (path) {
+			if (preq_is_gate)
+				rtw_mesh_path_add_gate(path);
+			else if (path->is_gate) {
+				enter_critical_bh(&path->state_lock);
+				rtw_mesh_gate_del(adapter->mesh_info.mesh_paths, path);
+				exit_critical_bh(&path->state_lock);
+			}
+		}
+		path = NULL;
+		rtw_rcu_read_unlock();
+#endif
+		forward = _FALSE;
+		reply = _TRUE;
+		to_gate_ask = 1;
+		target_metric = 0;
+		if (rtw_time_after(rtw_get_current_time(), minfo->last_sn_update +
+					rtw_net_traversal_jiffies(adapter)) ||
+		    rtw_time_before(rtw_get_current_time(), minfo->last_sn_update)) {
+			++minfo->sn;
+			minfo->last_sn_update = rtw_get_current_time();
+		}
+		target_sn = minfo->sn;
+	} else if (is_broadcast_mac_addr(target_addr) &&
+		   (target_flags & RTW_IEEE80211_PREQ_TO_FLAG)) {
+		rtw_rcu_read_lock();
+		path = rtw_mesh_path_lookup(adapter, originator_addr);
+		if (path) {
+			if (flags & RTW_IEEE80211_PREQ_PROACTIVE_PREP_FLAG) {
+				reply = _TRUE;
+				target_addr = adapter_mac_addr(adapter);
+				target_sn = ++minfo->sn;
+				target_metric = 0;
+				minfo->last_sn_update = rtw_get_current_time();
+			}
+
+			if (preq_is_gate) {
+				lifetime = RTW_PREQ_IE_LIFETIME(preq_elem);
+				path->gate_ann_int = lifetime;
+				path->gate_asked = false;
+				rtw_mesh_path_add_gate(path);
+			} else if (path->is_gate) {
+				enter_critical_bh(&path->state_lock);
+				rtw_mesh_gate_del(adapter->mesh_info.mesh_paths, path);
+				exit_critical_bh(&path->state_lock);
+			}
+		}
+		rtw_rcu_read_unlock();
+	} else {
+		rtw_rcu_read_lock();
+#ifdef CONFIG_RTW_MESH_ON_DMD_GANN
+		path = rtw_mesh_path_lookup(adapter, originator_addr);
+		if (path) {
+			if (preq_is_gate)
+				rtw_mesh_path_add_gate(path);
+			else if (path->is_gate) {
+				enter_critical_bh(&path->state_lock);
+				rtw_mesh_gate_del(adapter->mesh_info.mesh_paths, path);
+				exit_critical_bh(&path->state_lock);
+			}
+		}
+		path = NULL;
+#endif
+		path = rtw_mesh_path_lookup(adapter, target_addr);
+		if (path) {
+			if ((!(path->flags & RTW_MESH_PATH_SN_VALID)) ||
+					RTW_SN_LT(path->sn, target_sn)) {
+				path->sn = target_sn;
+				path->flags |= RTW_MESH_PATH_SN_VALID;
+			} else if ((!(target_flags & RTW_IEEE80211_PREQ_TO_FLAG)) &&
+					(path->flags & RTW_MESH_PATH_ACTIVE)) {
+				reply = _TRUE;
+				target_metric = path->metric;
+				target_sn = path->sn;
+				/* Case E2 of sec 13.10.9.3 IEEE 802.11-2012*/
+				target_flags |= RTW_IEEE80211_PREQ_TO_FLAG;
+			}
+		}
+		rtw_rcu_read_unlock();
+	}
+
+	if (reply) {
+		lifetime = RTW_PREQ_IE_LIFETIME(preq_elem);
+		ttl = mshcfg->element_ttl;
+		if (ttl != 0 && !to_gate_ask) {
+			RTW_HWMP_DBG("replying to the PREQ\n");
+			rtw_mesh_path_sel_frame_tx(RTW_MPATH_PREP, 0, originator_addr,
+						   originator_sn, 0, target_addr,
+						   target_sn, mgmt->addr2, 0, ttl,
+						   lifetime, target_metric, 0,
+						   adapter);
+		} else if (ttl != 0 && to_gate_ask) {
+			RTW_HWMP_DBG("replying to the PREQ (PREQ for us)\n");
+			if (mshcfg->dot11MeshGateAnnouncementProtocol) {
+				/* BIT 7 is used to identify the prep is from mesh gate */
+				to_gate_ask = RTW_IEEE80211_PREQ_IS_GATE_FLAG | BIT(7);
+			} else {
+				to_gate_ask = 0;
+			}
+
+			rtw_mesh_path_sel_frame_tx(RTW_MPATH_PREP, to_gate_ask, originator_addr,
+						   originator_sn, 0, target_addr,
+						   target_sn, mgmt->addr2, 0, ttl,
+						   lifetime, target_metric, 0,
+						   adapter);
+		} else {
+			minfo->mshstats.dropped_frames_ttl++;
+		}
+	}
+
+	if (forward && mshcfg->dot11MeshForwarding) {
+		u32 preq_id;
+		u8 hopcount;
+
+		ttl = RTW_PREQ_IE_TTL(preq_elem);
+		lifetime = RTW_PREQ_IE_LIFETIME(preq_elem);
+		if (ttl <= 1) {
+			minfo->mshstats.dropped_frames_ttl++;
+			return;
+		}
+		RTW_HWMP_DBG("forwarding the PREQ from "MAC_FMT"\n", MAC_ARG(originator_addr));
+		--ttl;
+		preq_id = RTW_PREQ_IE_PREQ_ID(preq_elem);
+		hopcount = RTW_PREQ_IE_HOPCOUNT(preq_elem) + 1;
+		da = (path && path->is_root) ?
+			path->rann_snd_addr : bcast_addr;
+
+		if (flags & RTW_IEEE80211_PREQ_PROACTIVE_PREP_FLAG) {
+			target_addr = RTW_PREQ_IE_TARGET_ADDR(preq_elem);
+			target_sn = RTW_PREQ_IE_TARGET_SN(preq_elem);
+		}
+
+		rtw_mesh_path_sel_frame_tx(RTW_MPATH_PREQ, flags, originator_addr,
+					   originator_sn, target_flags, target_addr,
+					   target_sn, da, hopcount, ttl, lifetime,
+					   originator_metric, preq_id, adapter);
+		if (!is_multicast_mac_addr(da))
+			minfo->mshstats.fwded_unicast++;
+		else
+			minfo->mshstats.fwded_mcast++;
+		minfo->mshstats.fwded_frames++;
+	}
+}
+
+static inline struct sta_info *
+rtw_next_hop_deref_protected(struct rtw_mesh_path *path)
+{
+	return rtw_rcu_dereference_protected(path->next_hop,
+					 rtw_lockdep_is_held(&path->state_lock));
+}
+
+static void rtw_hwmp_prep_frame_process(_adapter *adapter,
+					struct rtw_ieee80211_hdr_3addr *mgmt,
+					const u8 *prep_elem, u32 metric)
+{
+	struct rtw_mesh_cfg *mshcfg = &adapter->mesh_cfg;
+	struct rtw_mesh_stats *mshstats = &adapter->mesh_info.mshstats;
+	struct rtw_mesh_path *path;
+	const u8 *target_addr, *originator_addr;
+	u8 ttl, hopcount, flags;
+	u8 next_hop[ETH_ALEN];
+	u32 target_sn, originator_sn, lifetime;
+
+	RTW_HWMP_DBG("received PREP from "MAC_FMT"\n",
+		  MAC_ARG(RTW_PREP_IE_TARGET_ADDR(prep_elem)));
+
+	originator_addr = RTW_PREP_IE_ORIG_ADDR(prep_elem);
+	if (rtw_ether_addr_equal(originator_addr, adapter_mac_addr(adapter))) {
+		/* destination, no forwarding required */
+		rtw_rcu_read_lock();
+		target_addr = RTW_PREP_IE_TARGET_ADDR(prep_elem);
+		path = rtw_mesh_path_lookup(adapter, target_addr);
+		if (path && path->gate_asked) {
+			flags = RTW_PREP_IE_FLAGS(prep_elem);
+			if (flags & BIT(7)) {
+				enter_critical_bh(&path->state_lock);
+				path->gate_asked = false;
+				exit_critical_bh(&path->state_lock);
+				if (!(flags & RTW_IEEE80211_PREQ_IS_GATE_FLAG)) {
+					enter_critical_bh(&path->state_lock);
+					rtw_mesh_gate_del(adapter->mesh_info.mesh_paths, path);
+					exit_critical_bh(&path->state_lock);
+				}
+			}
+		}
+
+		rtw_rcu_read_unlock();
+		return;
+	}
+
+	if (!mshcfg->dot11MeshForwarding)
+		return;
+
+	ttl = RTW_PREP_IE_TTL(prep_elem);
+	if (ttl <= 1) {
+		mshstats->dropped_frames_ttl++;
+		return;
+	}
+
+	rtw_rcu_read_lock();
+	path = rtw_mesh_path_lookup(adapter, originator_addr);
+	if (path)
+		enter_critical_bh(&path->state_lock);
+	else
+		goto fail;
+	if (!(path->flags & RTW_MESH_PATH_ACTIVE)) {
+		exit_critical_bh(&path->state_lock);
+		goto fail;
+	}
+	_rtw_memcpy(next_hop, rtw_next_hop_deref_protected(path)->cmn.mac_addr, ETH_ALEN);
+	exit_critical_bh(&path->state_lock);
+	--ttl;
+	flags = RTW_PREP_IE_FLAGS(prep_elem);
+	lifetime = RTW_PREP_IE_LIFETIME(prep_elem);
+	hopcount = RTW_PREP_IE_HOPCOUNT(prep_elem) + 1;
+	target_addr = RTW_PREP_IE_TARGET_ADDR(prep_elem);
+	target_sn = RTW_PREP_IE_TARGET_SN(prep_elem);
+	originator_sn = RTW_PREP_IE_ORIG_SN(prep_elem);
+
+	rtw_mesh_path_sel_frame_tx(RTW_MPATH_PREP, flags, originator_addr, originator_sn, 0,
+				   target_addr, target_sn, next_hop, hopcount,
+				   ttl, lifetime, metric, 0, adapter);
+	rtw_rcu_read_unlock();
+
+	mshstats->fwded_unicast++;
+	mshstats->fwded_frames++;
+	return;
+
+fail:
+	rtw_rcu_read_unlock();
+	mshstats->dropped_frames_no_route++;
+}
+
+static void rtw_hwmp_perr_frame_process(_adapter *adapter,
+					struct rtw_ieee80211_hdr_3addr *mgmt,
+					const u8 *perr_elem)
+{
+	struct rtw_mesh_cfg *mshcfg = &adapter->mesh_cfg;
+	struct rtw_mesh_stats *mshstats = &adapter->mesh_info.mshstats;
+	struct rtw_mesh_path *path;
+	u8 ttl;
+	const u8 *ta, *target_addr;
+	u32 target_sn;
+	u16 perr_reason_code;
+
+	ta = mgmt->addr2;
+	ttl = RTW_PERR_IE_TTL(perr_elem);
+	if (ttl <= 1) {
+		mshstats->dropped_frames_ttl++;
+		return;
+	}
+	ttl--;
+	target_addr = RTW_PERR_IE_TARGET_ADDR(perr_elem);
+	target_sn = RTW_PERR_IE_TARGET_SN(perr_elem);
+	perr_reason_code = RTW_PERR_IE_TARGET_RCODE(perr_elem);
+
+	RTW_HWMP_DBG("received PERR toward target "MAC_FMT"\n", MAC_ARG(target_addr));
+
+	rtw_rcu_read_lock();
+	path = rtw_mesh_path_lookup(adapter, target_addr);
+	if (path) {
+		struct sta_info *sta;
+
+		enter_critical_bh(&path->state_lock);
+		sta = rtw_next_hop_deref_protected(path);
+		if (path->flags & RTW_MESH_PATH_ACTIVE &&
+		    rtw_ether_addr_equal(ta, sta->cmn.mac_addr) &&
+		    !(path->flags & RTW_MESH_PATH_FIXED) &&
+		    (!(path->flags & RTW_MESH_PATH_SN_VALID) ||
+		    RTW_SN_GT(target_sn, path->sn)  || target_sn == 0)) {
+			path->flags &= ~RTW_MESH_PATH_ACTIVE;
+			if (target_sn != 0)
+				path->sn = target_sn;
+			else
+				path->sn += 1;
+			exit_critical_bh(&path->state_lock);
+			if (!mshcfg->dot11MeshForwarding)
+				goto endperr;
+			rtw_mesh_path_error_tx(adapter, ttl, target_addr,
+					       target_sn, perr_reason_code,
+					       bcast_addr);
+		} else
+			exit_critical_bh(&path->state_lock);
+	}
+endperr:
+	rtw_rcu_read_unlock();
+}
+
+static void rtw_hwmp_rann_frame_process(_adapter *adapter,
+					struct rtw_ieee80211_hdr_3addr *mgmt,
+					const struct rtw_ieee80211_rann_ie *rann)
+{
+	struct sta_info *sta;
+	struct sta_priv *pstapriv = &adapter->stapriv;
+	struct rtw_mesh_cfg *mshcfg = &adapter->mesh_cfg;
+	struct rtw_mesh_stats *mshstats = &adapter->mesh_info.mshstats;
+	struct rtw_mesh_path *path;
+	u8 ttl, flags, hopcount;
+	const u8 *originator_addr;
+	u32 originator_sn, metric, metric_txsta, interval;
+	BOOLEAN root_is_gate;
+
+	ttl = rann->rann_ttl;
+	flags = rann->rann_flags;
+	root_is_gate = !!(flags & RTW_RANN_FLAG_IS_GATE);
+	originator_addr = rann->rann_addr;
+	originator_sn = le32_to_cpu(rann->rann_seq);
+	interval = le32_to_cpu(rann->rann_interval);
+	hopcount = rann->rann_hopcount;
+	hopcount++;
+	metric = le32_to_cpu(rann->rann_metric);
+
+	/*  Ignore our own RANNs */
+	if (rtw_ether_addr_equal(originator_addr, adapter_mac_addr(adapter)))
+		return;
+
+	RTW_HWMP_DBG("received RANN from "MAC_FMT" via neighbour "MAC_FMT" (is_gate=%d)\n",
+		  MAC_ARG(originator_addr), MAC_ARG(mgmt->addr2), root_is_gate);
+
+	rtw_rcu_read_lock();
+	sta = rtw_get_stainfo(pstapriv, mgmt->addr2);
+	if (!sta) {
+		rtw_rcu_read_unlock();
+		return;
+	}
+
+	metric_txsta = rtw_airtime_link_metric_get(adapter, sta);
+
+	path = rtw_mesh_path_lookup(adapter, originator_addr);
+	if (!path) {
+		path = rtw_mesh_path_add(adapter, originator_addr);
+		if (IS_ERR(path)) {
+			rtw_rcu_read_unlock();
+			mshstats->dropped_frames_no_route++;
+			return;
+		}
+	}
+
+	if (!(RTW_SN_LT(path->sn, originator_sn)) &&
+	    !(path->sn == originator_sn && metric < path->rann_metric)) {
+		rtw_rcu_read_unlock();
+		return;
+	}
+
+	if ((!(path->flags & (RTW_MESH_PATH_ACTIVE | RTW_MESH_PATH_RESOLVING)) ||
+	     (rtw_time_after(rtw_get_current_time(), path->last_preq_to_root +
+				  rtw_root_path_confirmation_jiffies(adapter)) ||
+	     rtw_time_before(rtw_get_current_time(), path->last_preq_to_root))) &&
+	     !(path->flags & RTW_MESH_PATH_FIXED) && (ttl != 0)) {
+		u8 preq_node_flag = RTW_PREQ_Q_F_START | RTW_PREQ_Q_F_REFRESH;
+
+		RTW_HWMP_DBG("time to refresh root path "MAC_FMT"\n",
+			  MAC_ARG(originator_addr));
+#ifdef CONFIG_RTW_MESH_ADD_ROOT_CHK
+		if (RTW_SN_LT(path->sn, originator_sn) &&
+		    (path->rann_metric + mshcfg->sane_metric_delta < metric) &&
+		    _rtw_memcmp(bcast_addr, path->rann_snd_addr, ETH_ALEN) == _FALSE) {
+			RTW_HWMP_DBG("Trigger additional check for root "
+				     "confirm PREQ. rann_snd_addr = "MAC_FMT
+				     "add_chk_rann_snd_addr= "MAC_FMT"\n",
+					MAC_ARG(mgmt->addr2),
+					MAC_ARG(path->rann_snd_addr));
+			_rtw_memcpy(path->add_chk_rann_snd_addr,
+				    path->rann_snd_addr, ETH_ALEN);
+			preq_node_flag |= RTW_PREQ_Q_F_CHK;
+			
+		}
+#endif
+		rtw_mesh_queue_preq(path, preq_node_flag);
+		path->last_preq_to_root = rtw_get_current_time();
+	}
+
+	path->sn = originator_sn;
+	path->rann_metric = metric + metric_txsta;
+	path->is_root = _TRUE;
+	/* Recording RANNs sender address to send individually
+	 * addressed PREQs destined for root mesh STA */
+	_rtw_memcpy(path->rann_snd_addr, mgmt->addr2, ETH_ALEN);
+
+	if (root_is_gate) {
+		path->gate_ann_int = interval;
+		path->gate_asked = false;
+		rtw_mesh_path_add_gate(path);
+	} else if (path->is_gate) {
+		enter_critical_bh(&path->state_lock);
+		rtw_mesh_gate_del(adapter->mesh_info.mesh_paths, path);
+		exit_critical_bh(&path->state_lock);
+	}
+
+	if (ttl <= 1) {
+		mshstats->dropped_frames_ttl++;
+		rtw_rcu_read_unlock();
+		return;
+	}
+	ttl--;
+
+	if (mshcfg->dot11MeshForwarding) {
+		rtw_mesh_path_sel_frame_tx(RTW_MPATH_RANN, flags, originator_addr,
+					   originator_sn, 0, NULL, 0, bcast_addr,
+					   hopcount, ttl, interval,
+					   metric + metric_txsta, 0, adapter);
+	}
+
+	rtw_rcu_read_unlock();
+}
+
+static u32 rtw_hwmp_route_info_get(_adapter *adapter,
+				   struct rtw_ieee80211_hdr_3addr *mgmt,
+				   const u8 *hwmp_ie, enum rtw_mpath_frame_type action)
+{
+	struct rtw_mesh_path *path;
+	struct sta_priv *pstapriv = &adapter->stapriv;
+	struct sta_info *sta;
+	BOOLEAN fresh_info;
+	const u8 *originator_addr, *ta;
+	u32 originator_sn, originator_metric;
+	unsigned long originator_lifetime, exp_time;
+	u32 last_hop_metric, new_metric;
+	BOOLEAN process = _TRUE;
+
+	rtw_rcu_read_lock();
+	sta = rtw_get_stainfo(pstapriv, mgmt->addr2);
+	if (!sta) {
+		rtw_rcu_read_unlock();
+		return 0;
+	}
+
+	last_hop_metric = rtw_airtime_link_metric_get(adapter, sta);
+	/* Update and check originator routing info */
+	fresh_info = _TRUE;
+
+	switch (action) {
+	case RTW_MPATH_PREQ:
+		originator_addr = RTW_PREQ_IE_ORIG_ADDR(hwmp_ie);
+		originator_sn = RTW_PREQ_IE_ORIG_SN(hwmp_ie);
+		originator_lifetime = RTW_PREQ_IE_LIFETIME(hwmp_ie);
+		originator_metric = RTW_PREQ_IE_METRIC(hwmp_ie);
+		break;
+	case RTW_MPATH_PREP:
+		/* Note: For coding, the naming is not consist with spec */
+		originator_addr = RTW_PREP_IE_TARGET_ADDR(hwmp_ie);
+		originator_sn = RTW_PREP_IE_TARGET_SN(hwmp_ie);
+		originator_lifetime = RTW_PREP_IE_LIFETIME(hwmp_ie);
+		originator_metric = RTW_PREP_IE_METRIC(hwmp_ie);
+		break;
+	default:
+		rtw_rcu_read_unlock();
+		return 0;
+	}
+	new_metric = originator_metric + last_hop_metric;
+	if (new_metric < originator_metric)
+		new_metric = RTW_MAX_METRIC;
+	exp_time = RTW_TU_TO_EXP_TIME(originator_lifetime);
+
+	if (rtw_ether_addr_equal(originator_addr, adapter_mac_addr(adapter))) {
+		process = _FALSE;
+		fresh_info = _FALSE;
+	} else {
+		path = rtw_mesh_path_lookup(adapter, originator_addr);
+		if (path) {
+			enter_critical_bh(&path->state_lock);
+			if (path->flags & RTW_MESH_PATH_FIXED)
+				fresh_info = _FALSE;
+			else if ((path->flags & RTW_MESH_PATH_ACTIVE) &&
+			    (path->flags & RTW_MESH_PATH_SN_VALID)) {
+				if (RTW_SN_GT(path->sn, originator_sn) ||
+				    (path->sn == originator_sn &&
+				     new_metric >= path->metric)) {
+					process = _FALSE;
+					fresh_info = _FALSE;
+				}
+			} else if (!(path->flags & RTW_MESH_PATH_ACTIVE)) {
+				BOOLEAN have_sn, newer_sn, bounced;
+
+				have_sn = path->flags & RTW_MESH_PATH_SN_VALID;
+				newer_sn = have_sn && RTW_SN_GT(originator_sn, path->sn);
+				bounced = have_sn &&
+					  (RTW_SN_DELTA(originator_sn, path->sn) >
+							RTW_MAX_SANE_SN_DELTA);
+
+				if (!have_sn || newer_sn) {
+				} else if (bounced) {
+				} else {
+					process = _FALSE;
+					fresh_info = _FALSE;
+				}
+			}
+		} else {
+			path = rtw_mesh_path_add(adapter, originator_addr);
+			if (IS_ERR(path)) {
+				rtw_rcu_read_unlock();
+				return 0;
+			}
+			enter_critical_bh(&path->state_lock);
+		}
+
+		if (fresh_info) {
+			rtw_mesh_path_assign_nexthop(path, sta);
+			path->flags |= RTW_MESH_PATH_SN_VALID;
+			path->metric = new_metric;
+			path->sn = originator_sn;
+			path->exp_time = rtw_time_after(path->exp_time, exp_time)
+					  ?  path->exp_time : exp_time;
+			rtw_mesh_path_activate(path);
+#ifdef CONFIG_RTW_MESH_ADD_ROOT_CHK
+			if (path->is_root && (action == RTW_MPATH_PREP)) {
+				_rtw_memcpy(path->rann_snd_addr, 
+				mgmt->addr2, ETH_ALEN);
+				path->rann_metric = new_metric;
+			}
+#endif
+			exit_critical_bh(&path->state_lock);
+			rtw_mesh_path_tx_pending(path);
+		} else
+			exit_critical_bh(&path->state_lock);
+	}
+
+	/* Update and check transmitter routing info */
+	ta = mgmt->addr2;
+	if (rtw_ether_addr_equal(originator_addr, ta))
+		fresh_info = _FALSE;
+	else {
+		fresh_info = _TRUE;
+
+		path = rtw_mesh_path_lookup(adapter, ta);
+		if (path) {
+			enter_critical_bh(&path->state_lock);
+			if ((path->flags & RTW_MESH_PATH_FIXED) ||
+				((path->flags & RTW_MESH_PATH_ACTIVE) &&
+					(last_hop_metric > path->metric)))
+				fresh_info = _FALSE;
+		} else {
+			path = rtw_mesh_path_add(adapter, ta);
+			if (IS_ERR(path)) {
+				rtw_rcu_read_unlock();
+				return 0;
+			}
+			enter_critical_bh(&path->state_lock);
+		}
+
+		if (fresh_info) {
+			rtw_mesh_path_assign_nexthop(path, sta);
+			path->metric = last_hop_metric;
+			path->exp_time = rtw_time_after(path->exp_time, exp_time)
+					  ?  path->exp_time : exp_time;
+			rtw_mesh_path_activate(path);
+			exit_critical_bh(&path->state_lock);
+			rtw_mesh_path_tx_pending(path);
+		} else
+			exit_critical_bh(&path->state_lock);
+	}
+
+	rtw_rcu_read_unlock();
+
+	return process ? new_metric : 0;
+}
+
+static void rtw_mesh_rx_hwmp_frame_cnts(_adapter *adapter, u8 *addr)
+{
+	struct sta_info *sta;
+
+	sta = rtw_get_stainfo(&adapter->stapriv, addr);
+	if (sta)
+		sta->sta_stats.rx_hwmp_pkts++;
+}
+
+void rtw_mesh_rx_path_sel_frame(_adapter *adapter, union recv_frame *rframe)
+{
+	struct mesh_plink_ent *plink = NULL;
+	struct rtw_ieee802_11_elems elems;
+	u32 path_metric;
+	struct rx_pkt_attrib *attrib = &rframe->u.hdr.attrib;
+	u8 *pframe = rframe->u.hdr.rx_data, *start;
+	uint frame_len = rframe->u.hdr.len, left;
+	struct rtw_ieee80211_hdr_3addr *frame_hdr = (struct rtw_ieee80211_hdr_3addr *)pframe;
+	u8 *frame_body = (u8 *)(pframe + sizeof(struct rtw_ieee80211_hdr_3addr));
+	ParseRes parse_res;
+
+	plink = rtw_mesh_plink_get(adapter, get_addr2_ptr(pframe));
+	if (!plink || plink->plink_state != RTW_MESH_PLINK_ESTAB)
+		return;
+
+	rtw_mesh_rx_hwmp_frame_cnts(adapter, get_addr2_ptr(pframe));
+
+	/* Mesh action frame IE offset = 2 */
+	attrib->hdrlen = sizeof(struct rtw_ieee80211_hdr_3addr);
+	left = frame_len - attrib->hdrlen - attrib->iv_len - attrib->icv_len - 2;
+	start = pframe + attrib->hdrlen + 2;
+
+	parse_res = rtw_ieee802_11_parse_elems(start, left, &elems, 1);
+	if (parse_res == ParseFailed)
+		RTW_HWMP_INFO(FUNC_ADPT_FMT" Path Select Frame ParseFailed\n"
+			, FUNC_ADPT_ARG(adapter));
+	else if (parse_res == ParseUnknown)
+		RTW_HWMP_INFO(FUNC_ADPT_FMT" Path Select Frame ParseUnknown\n"
+			, FUNC_ADPT_ARG(adapter));
+
+	if (elems.preq) {
+		if (elems.preq_len != 37)
+			/* Right now we support just 1 destination and no AE */
+			return;
+		path_metric = rtw_hwmp_route_info_get(adapter, frame_hdr, elems.preq,
+						  MPATH_PREQ);
+		if (path_metric)
+			rtw_hwmp_preq_frame_process(adapter, frame_hdr, elems.preq,
+						path_metric);
+	}
+	if (elems.prep) {
+		if (elems.prep_len != 31)
+			/* Right now we support no AE */
+			return;
+		path_metric = rtw_hwmp_route_info_get(adapter, frame_hdr, elems.prep,
+						  MPATH_PREP);
+		if (path_metric)
+			rtw_hwmp_prep_frame_process(adapter, frame_hdr, elems.prep,
+						path_metric);
+	}
+	if (elems.perr) {
+		if (elems.perr_len != 15)
+			/* Right now we support only one destination per PERR */
+			return;
+		rtw_hwmp_perr_frame_process(adapter, frame_hdr, elems.perr);
+	}
+	if (elems.rann)
+		rtw_hwmp_rann_frame_process(adapter, frame_hdr, (struct rtw_ieee80211_rann_ie *)elems.rann);
+}
+
+void rtw_mesh_queue_preq(struct rtw_mesh_path *path, u8 flags)
+{
+	_adapter *adapter = path->adapter;
+	struct rtw_mesh_info *minfo = &adapter->mesh_info;
+	struct rtw_mesh_preq_queue *preq_node;
+
+	preq_node = rtw_malloc(sizeof(struct rtw_mesh_preq_queue));
+	if (!preq_node) {
+		RTW_HWMP_INFO("could not allocate PREQ node\n");
+		return;
+	}
+
+	enter_critical_bh(&minfo->mesh_preq_queue_lock);
+	if (minfo->preq_queue_len == RTW_MAX_PREQ_QUEUE_LEN) {
+		exit_critical_bh(&minfo->mesh_preq_queue_lock);
+		rtw_mfree(preq_node, sizeof(struct rtw_mesh_preq_queue));
+		if (rtw_print_ratelimit())
+			RTW_HWMP_INFO("PREQ node queue full\n");
+		return;
+	}
+
+	_rtw_spinlock(&path->state_lock);
+	if (path->flags & RTW_MESH_PATH_REQ_QUEUED) {
+		_rtw_spinunlock(&path->state_lock);
+		exit_critical_bh(&minfo->mesh_preq_queue_lock);
+		rtw_mfree(preq_node, sizeof(struct rtw_mesh_preq_queue));
+		return;
+	}
+
+	_rtw_memcpy(preq_node->dst, path->dst, ETH_ALEN);
+	preq_node->flags = flags;
+
+	path->flags |= RTW_MESH_PATH_REQ_QUEUED;
+#ifdef CONFIG_RTW_MESH_ADD_ROOT_CHK
+	if (flags & RTW_PREQ_Q_F_CHK)
+		path->flags |= RTW_MESH_PATH_ROOT_ADD_CHK;
+#endif
+	if (flags & RTW_PREQ_Q_F_PEER_AKA)
+		path->flags |= RTW_MESH_PATH_PEER_AKA;
+	_rtw_spinunlock(&path->state_lock);
+
+	rtw_list_insert_tail(&preq_node->list, &minfo->preq_queue.list);
+	++minfo->preq_queue_len;
+	exit_critical_bh(&minfo->mesh_preq_queue_lock);
+
+	if (rtw_time_after(rtw_get_current_time(), minfo->last_preq + rtw_min_preq_int_jiff(adapter)))
+		rtw_mesh_work(&adapter->mesh_work);
+
+	else if (rtw_time_before(rtw_get_current_time(), minfo->last_preq)) {
+		/* systime wrapped around issue */
+		minfo->last_preq = rtw_get_current_time() - rtw_min_preq_int_jiff(adapter) - 1;
+		rtw_mesh_work(&adapter->mesh_work);
+	} else
+		rtw_mod_timer(&adapter->mesh_path_timer, minfo->last_preq +
+					rtw_min_preq_int_jiff(adapter) + 1);
+}
+
+static const u8 *rtw_hwmp_preq_da(struct rtw_mesh_path *path,
+			    BOOLEAN is_root_add_chk, BOOLEAN da_is_peer)
+{
+	const u8 *da;
+
+	if (da_is_peer)
+		da = path->dst;
+	else if (path->is_root)
+#ifdef CONFIG_RTW_MESH_ADD_ROOT_CHK
+		da = is_root_add_chk ? path->add_chk_rann_snd_addr:
+				       path->rann_snd_addr;
+#else
+		da = path->rann_snd_addr;
+#endif
+	else
+		da = bcast_addr;
+
+	return da;
+}
+
+void rtw_mesh_path_start_discovery(_adapter *adapter)
+{
+	struct rtw_mesh_info *minfo = &adapter->mesh_info;
+	struct rtw_mesh_cfg *mshcfg = &adapter->mesh_cfg;
+	struct rtw_mesh_preq_queue *preq_node;
+	struct rtw_mesh_path *path;
+	u8 ttl, target_flags = 0;
+	const u8 *da;
+	u32 lifetime;
+	u8 flags = 0;
+	BOOLEAN is_root_add_chk = _FALSE;
+	BOOLEAN da_is_peer;
+
+	enter_critical_bh(&minfo->mesh_preq_queue_lock);
+	if (!minfo->preq_queue_len ||
+		rtw_time_before(rtw_get_current_time(), minfo->last_preq +
+				rtw_min_preq_int_jiff(adapter))) {
+		exit_critical_bh(&minfo->mesh_preq_queue_lock);
+		return;
+	}
+
+	preq_node = rtw_list_first_entry(&minfo->preq_queue.list,
+			struct rtw_mesh_preq_queue, list);
+	rtw_list_delete(&preq_node->list); /* list_del_init(&preq_node->list); */
+	--minfo->preq_queue_len;
+	exit_critical_bh(&minfo->mesh_preq_queue_lock);
+
+	rtw_rcu_read_lock();
+	path = rtw_mesh_path_lookup(adapter, preq_node->dst);
+	if (!path)
+		goto enddiscovery;
+
+	enter_critical_bh(&path->state_lock);
+	if (path->flags & (RTW_MESH_PATH_DELETED | RTW_MESH_PATH_FIXED)) {
+		exit_critical_bh(&path->state_lock);
+		goto enddiscovery;
+	}
+	path->flags &= ~RTW_MESH_PATH_REQ_QUEUED;
+	if (preq_node->flags & RTW_PREQ_Q_F_START) {
+		if (path->flags & RTW_MESH_PATH_RESOLVING) {
+			exit_critical_bh(&path->state_lock);
+			goto enddiscovery;
+		} else {
+			path->flags &= ~RTW_MESH_PATH_RESOLVED;
+			path->flags |= RTW_MESH_PATH_RESOLVING;
+			path->discovery_retries = 0;
+			path->discovery_timeout = rtw_disc_timeout_jiff(adapter);
+		}
+	} else if (!(path->flags & RTW_MESH_PATH_RESOLVING) ||
+			path->flags & RTW_MESH_PATH_RESOLVED) {
+		path->flags &= ~RTW_MESH_PATH_RESOLVING;
+		exit_critical_bh(&path->state_lock);
+		goto enddiscovery;
+	}
+
+	minfo->last_preq = rtw_get_current_time();
+
+	if (rtw_time_after(rtw_get_current_time(), minfo->last_sn_update +
+				rtw_net_traversal_jiffies(adapter)) ||
+	    rtw_time_before(rtw_get_current_time(), minfo->last_sn_update)) {
+		++minfo->sn;
+		minfo->last_sn_update = rtw_get_current_time();
+	}
+	lifetime = rtw_default_lifetime(adapter);
+	ttl = mshcfg->element_ttl;
+	if (ttl == 0) {
+		minfo->mshstats.dropped_frames_ttl++;
+		exit_critical_bh(&path->state_lock);
+		goto enddiscovery;
+	}
+
+	if (preq_node->flags & RTW_PREQ_Q_F_REFRESH)
+		target_flags |= RTW_IEEE80211_PREQ_TO_FLAG;
+	else
+		target_flags &= ~RTW_IEEE80211_PREQ_TO_FLAG;
+
+#ifdef CONFIG_RTW_MESH_ADD_ROOT_CHK
+	is_root_add_chk = !!(path->flags & RTW_MESH_PATH_ROOT_ADD_CHK);
+#endif
+	da_is_peer = !!(path->flags & RTW_MESH_PATH_PEER_AKA);
+	exit_critical_bh(&path->state_lock);
+
+	da = rtw_hwmp_preq_da(path, is_root_add_chk, da_is_peer);
+
+#ifdef CONFIG_RTW_MESH_ON_DMD_GANN
+	flags = (mshcfg->dot11MeshGateAnnouncementProtocol)
+		? RTW_IEEE80211_PREQ_IS_GATE_FLAG : 0;
+#endif
+	rtw_mesh_path_sel_frame_tx(RTW_MPATH_PREQ, flags, adapter_mac_addr(adapter), minfo->sn,
+				   target_flags, path->dst, path->sn, da, 0,
+				   ttl, lifetime, 0, minfo->preq_id++, adapter);
+	rtw_mod_timer(&path->timer, rtw_get_current_time() + path->discovery_timeout);
+
+enddiscovery:
+	rtw_rcu_read_unlock();
+	rtw_mfree(preq_node, sizeof(struct rtw_mesh_preq_queue));
+}
+
+void rtw_mesh_path_timer(void *ctx)
+{
+	struct rtw_mesh_path *path = (void *) ctx;
+	_adapter *adapter = path->adapter;
+	int ret;
+	u8 retry = 0;
+#ifdef CONFIG_RTW_MESH_ADD_ROOT_CHK
+	struct rtw_mesh_cfg *mshcfg = &adapter->mesh_cfg;
+#endif
+	/* TBD: Proctect for suspend */
+#if 0
+	if (suspending)
+		return;
+#endif
+	enter_critical_bh(&path->state_lock);
+	if (path->flags & RTW_MESH_PATH_RESOLVED ||
+			(!(path->flags & RTW_MESH_PATH_RESOLVING))) {
+		path->flags &= ~(RTW_MESH_PATH_RESOLVING |
+				 RTW_MESH_PATH_RESOLVED |
+				 RTW_MESH_PATH_ROOT_ADD_CHK |
+				 RTW_MESH_PATH_PEER_AKA);
+		exit_critical_bh(&path->state_lock);
+	} else if (path->discovery_retries < rtw_max_preq_retries(adapter)) {
+		++path->discovery_retries;
+		path->discovery_timeout *= 2;
+		path->flags &= ~RTW_MESH_PATH_REQ_QUEUED;
+#ifdef CONFIG_RTW_MESH_ADD_ROOT_CHK
+		if (path->discovery_retries > mshcfg->max_root_add_chk_cnt)
+			path->flags &= ~RTW_MESH_PATH_ROOT_ADD_CHK;
+#endif
+		if (path->gate_asked)
+			retry |= RTW_PREQ_Q_F_REFRESH;
+
+		exit_critical_bh(&path->state_lock);
+		rtw_mesh_queue_preq(path, retry);
+	} else {
+		path->flags &= ~(RTW_MESH_PATH_RESOLVING |
+				  RTW_MESH_PATH_RESOLVED |
+				  RTW_MESH_PATH_REQ_QUEUED |
+				  RTW_MESH_PATH_ROOT_ADD_CHK |
+				  RTW_MESH_PATH_PEER_AKA);
+		path->exp_time = rtw_get_current_time();
+		exit_critical_bh(&path->state_lock);
+		if (!path->is_gate && rtw_mesh_gate_num(adapter) > 0) {
+			ret = rtw_mesh_path_send_to_gates(path);
+			if (ret)
+				RTW_HWMP_DBG("no gate was reachable\n");
+		} else
+			rtw_mesh_path_flush_pending(path);
+	}
+}
+
+
+void rtw_mesh_path_tx_root_frame(_adapter *adapter)
+{
+	struct rtw_mesh_cfg *mshcfg = &adapter->mesh_cfg;
+	struct rtw_mesh_info *minfo = &adapter->mesh_info;
+	u32 interval = mshcfg->dot11MeshHWMPRannInterval;
+	u8 flags, target_flags = 0;
+
+	flags = (mshcfg->dot11MeshGateAnnouncementProtocol)
+			? RTW_RANN_FLAG_IS_GATE : 0;
+
+	switch (mshcfg->dot11MeshHWMPRootMode) {
+	case RTW_IEEE80211_PROACTIVE_RANN:
+		rtw_mesh_path_sel_frame_tx(RTW_MPATH_RANN, flags, adapter_mac_addr(adapter),
+					   ++minfo->sn, 0, NULL, 0, bcast_addr,
+					   0, mshcfg->element_ttl,
+					   interval, 0, 0, adapter);
+		break;
+	case RTW_IEEE80211_PROACTIVE_PREQ_WITH_PREP:
+		flags |= RTW_IEEE80211_PREQ_PROACTIVE_PREP_FLAG;
+	case RTW_IEEE80211_PROACTIVE_PREQ_NO_PREP:
+		interval = mshcfg->dot11MeshHWMPactivePathToRootTimeout;
+		target_flags |= RTW_IEEE80211_PREQ_TO_FLAG |
+				RTW_IEEE80211_PREQ_USN_FLAG;
+		rtw_mesh_path_sel_frame_tx(RTW_MPATH_PREQ, flags, adapter_mac_addr(adapter),
+					   ++minfo->sn, target_flags,
+					   (u8 *) bcast_addr, 0, bcast_addr,
+					   0, mshcfg->element_ttl, interval,
+					   0, minfo->preq_id++, adapter);
+		break;
+	default:
+		RTW_HWMP_INFO("Proactive mechanism not supported\n");
+		return;
+	}
+}
+
+void rtw_mesh_work(_workitem *work)
+{
+	/* use kernel global workqueue */
+	_set_workitem(work);
+}
+
+void rtw_ieee80211_mesh_path_timer(void *ctx)
+{
+	_adapter *adapter = (_adapter *)ctx;
+	rtw_mesh_work(&adapter->mesh_work);
+}
+
+void rtw_ieee80211_mesh_path_root_timer(void *ctx)
+{
+	_adapter *adapter = (_adapter *)ctx;
+
+	rtw_set_bit(RTW_MESH_WORK_ROOT, &adapter->wrkq_flags);
+
+	rtw_mesh_work(&adapter->mesh_work);
+}
+
+static void rtw_ieee80211_mesh_rootpath(_adapter *adapter)
+{
+	u32 interval;
+
+	rtw_mesh_path_tx_root_frame(adapter);
+
+	if (adapter->mesh_cfg.dot11MeshHWMPRootMode == RTW_IEEE80211_PROACTIVE_RANN)
+		interval = adapter->mesh_cfg.dot11MeshHWMPRannInterval;
+	else
+		interval = adapter->mesh_cfg.dot11MeshHWMProotInterval;
+
+	rtw_mod_timer(&adapter->mesh_path_root_timer,
+		  RTW_TU_TO_EXP_TIME(interval));
+}
+
+BOOLEAN rtw_ieee80211_mesh_root_setup(_adapter *adapter)
+{
+	BOOLEAN root_enabled = _FALSE;
+
+	if (adapter->mesh_cfg.dot11MeshHWMPRootMode > RTW_IEEE80211_ROOTMODE_ROOT) {
+		rtw_set_bit(RTW_MESH_WORK_ROOT, &adapter->wrkq_flags);
+		root_enabled = _TRUE;
+	}
+	else {
+		rtw_clear_bit(RTW_MESH_WORK_ROOT, &adapter->wrkq_flags);
+		/* stop running timer */
+		_cancel_timer_ex(&adapter->mesh_path_root_timer);
+		root_enabled = _FALSE;
+	}
+
+	return root_enabled;
+}
+
+void rtw_mesh_work_hdl(_workitem *work)
+{
+	_adapter *adapter = container_of(work, _adapter, mesh_work);
+
+	while(adapter->mesh_info.preq_queue_len) {
+		if (rtw_time_after(rtw_get_current_time(),
+		       adapter->mesh_info.last_preq + rtw_min_preq_int_jiff(adapter)))
+		       /* It will consume preq_queue_len */
+		       rtw_mesh_path_start_discovery(adapter);
+		else {
+			struct rtw_mesh_info *minfo = &adapter->mesh_info;
+
+			rtw_mod_timer(&adapter->mesh_path_timer,
+				minfo->last_preq + rtw_min_preq_int_jiff(adapter) + 1);
+			break;
+		}
+	}
+
+	if (rtw_test_and_clear_bit(RTW_MESH_WORK_ROOT, &adapter->wrkq_flags))
+		rtw_ieee80211_mesh_rootpath(adapter);
+}
+
+#ifndef RTW_PER_CMD_SUPPORT_FW
+static void rtw_update_metric_directly(_adapter *adapter)
+{
+	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
+	struct macid_ctl_t *macid_ctl = dvobj_to_macidctl(dvobj);
+	u8 i;
+
+	for (i = 0; i < macid_ctl->num; i++) {
+		u8 role;
+		role = GET_H2CCMD_MSRRPT_PARM_ROLE(&macid_ctl->h2c_msr[i]);
+		if (role == H2C_MSR_ROLE_MESH) {
+			struct sta_info *sta = macid_ctl->sta[i];
+			u8 rate_idx, sgi, bw;
+			u32 rate;
+
+			if (!sta)
+				continue;
+			rate_idx = rtw_get_current_tx_rate(adapter, sta);
+			sgi = rtw_get_current_tx_sgi(adapter, sta);
+			bw = sta->cmn.bw_mode;
+			rate = rtw_desc_rate_to_bitrate(bw, rate_idx, sgi);
+			sta->metrics.data_rate = rate;
+		}
+	}
+}
+#endif
+
+void rtw_mesh_atlm_param_req_timer(void *ctx)
+{
+	_adapter *adapter = (_adapter *)ctx;
+	u8 ret = _FAIL;
+
+#ifdef RTW_PER_CMD_SUPPORT_FW
+	ret = rtw_req_per_cmd(adapter);
+	if (ret == _FAIL)
+		RTW_HWMP_INFO("rtw_req_per_cmd fail\n");
+#else
+	rtw_update_metric_directly(adapter);
+#endif
+	_set_timer(&adapter->mesh_atlm_param_req_timer, RTW_ATLM_REQ_CYCLE);
+}
+
+#endif /* CONFIG_RTW_MESH */
+
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/core/mesh/rtw_mesh_hwmp.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/core/mesh/rtw_mesh_hwmp.h
--- linux-5.6.3/3rdparty/rtl8821ce/core/mesh/rtw_mesh_hwmp.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/core/mesh/rtw_mesh_hwmp.h	2020-04-10 16:35:06.769657873 +0300
@@ -0,0 +1,60 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#ifndef __RTW_MESH_HWMP_H_
+#define __RTW_MESH_HWMP_H_
+
+#ifndef DBG_RTW_HWMP
+#define DBG_RTW_HWMP 0
+#endif
+#if DBG_RTW_HWMP
+#define RTW_HWMP_DBG(fmt, arg...) RTW_PRINT(fmt, ##arg)
+#else
+#define RTW_HWMP_DBG(fmt, arg...) RTW_DBG(fmt, ##arg)
+#endif
+
+#ifndef INFO_RTW_HWMP
+#define INFO_RTW_HWMP 0
+#endif
+#if INFO_RTW_HWMP
+#define RTW_HWMP_INFO(fmt, arg...) RTW_PRINT(fmt, ##arg)
+#else
+#define RTW_HWMP_INFO(fmt, arg...) RTW_INFO(fmt, ##arg)
+#endif
+
+
+void rtw_ewma_err_rate_init(struct rtw_ewma_err_rate *e);
+unsigned long rtw_ewma_err_rate_read(struct rtw_ewma_err_rate *e);
+void rtw_ewma_err_rate_add(struct rtw_ewma_err_rate *e, unsigned long val);
+int rtw_mesh_path_error_tx(_adapter *adapter,
+			   u8 ttl, const u8 *target, u32 target_sn,
+			   u16 target_rcode, const u8 *ra);
+void rtw_ieee80211s_update_metric(_adapter *adapter, u8 mac_id,
+				  u8 per, u8 rate,
+				  u8 bw, u8 total_pkt);
+void rtw_mesh_rx_path_sel_frame(_adapter *adapter, union recv_frame *rframe);
+void rtw_mesh_queue_preq(struct rtw_mesh_path *mpath, u8 flags);
+void rtw_mesh_path_start_discovery(_adapter *adapter);
+void rtw_mesh_path_timer(void *ctx);
+void rtw_mesh_path_tx_root_frame(_adapter *adapter);
+void rtw_mesh_work_hdl(_workitem *work);
+void rtw_ieee80211_mesh_path_timer(void *ctx);
+void rtw_ieee80211_mesh_path_root_timer(void *ctx);
+BOOLEAN rtw_ieee80211_mesh_root_setup(_adapter *adapter);
+void rtw_mesh_work(_workitem *work);
+void rtw_mesh_atlm_param_req_timer(void *ctx);
+
+#endif /* __RTW_MESH_HWMP_H_ */
+
+
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/core/mesh/rtw_mesh_pathtbl.c linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/core/mesh/rtw_mesh_pathtbl.c
--- linux-5.6.3/3rdparty/rtl8821ce/core/mesh/rtw_mesh_pathtbl.c	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/core/mesh/rtw_mesh_pathtbl.c	2020-04-10 16:35:06.770657920 +0300
@@ -0,0 +1,1185 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#define _RTW_MESH_PATHTBL_C_
+
+#ifdef CONFIG_RTW_MESH
+#include <drv_types.h>
+#include <linux/jhash.h>
+
+#ifdef PLATFORM_LINUX
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 0, 0))
+static void rtw_mpath_free_rcu(struct rtw_mesh_path *mpath)
+{
+	kfree_rcu(mpath, rcu);
+	rtw_mstat_update(MSTAT_TYPE_PHY, MSTAT_FREE, sizeof(struct rtw_mesh_path));
+}
+#else
+static void rtw_mpath_free_rcu_callback(rtw_rcu_head *head)
+{
+	struct rtw_mesh_path *mpath;
+
+	mpath = container_of(head, struct rtw_mesh_path, rcu);
+	rtw_mfree(mpath, sizeof(struct rtw_mesh_path));
+}
+
+static void rtw_mpath_free_rcu(struct rtw_mesh_path *mpath)
+{
+	call_rcu(&mpath->rcu, rtw_mpath_free_rcu_callback);
+}
+#endif
+#endif /* PLATFORM_LINUX */
+
+static void rtw_mesh_path_free_rcu(struct rtw_mesh_table *tbl, struct rtw_mesh_path *mpath);
+
+static u32 rtw_mesh_table_hash(const void *addr, u32 len, u32 seed)
+{
+	/* Use last four bytes of hw addr as hash index */
+	return jhash_1word(*(u32 *)(addr+2), seed);
+}
+
+static const rtw_rhashtable_params rtw_mesh_rht_params = {
+	.nelem_hint = 2,
+	.automatic_shrinking = true,
+	.key_len = ETH_ALEN,
+	.key_offset = offsetof(struct rtw_mesh_path, dst),
+	.head_offset = offsetof(struct rtw_mesh_path, rhash),
+	.hashfn = rtw_mesh_table_hash,
+};
+
+static inline bool rtw_mpath_expired(struct rtw_mesh_path *mpath)
+{
+	return (mpath->flags & RTW_MESH_PATH_ACTIVE) &&
+	       rtw_time_after(rtw_get_current_time(), mpath->exp_time) &&
+	       !(mpath->flags & RTW_MESH_PATH_FIXED);
+}
+
+static void rtw_mesh_path_rht_free(void *ptr, void *tblptr)
+{
+	struct rtw_mesh_path *mpath = ptr;
+	struct rtw_mesh_table *tbl = tblptr;
+
+	rtw_mesh_path_free_rcu(tbl, mpath);
+}
+
+static struct rtw_mesh_table *rtw_mesh_table_alloc(void)
+{
+	struct rtw_mesh_table *newtbl;
+
+	newtbl = rtw_malloc(sizeof(struct rtw_mesh_table));
+	if (!newtbl)
+		return NULL;
+
+	rtw_hlist_head_init(&newtbl->known_gates);
+	ATOMIC_SET(&newtbl->entries,  0);
+	_rtw_spinlock_init(&newtbl->gates_lock);
+
+	return newtbl;
+}
+
+static void rtw_mesh_table_free(struct rtw_mesh_table *tbl)
+{
+	rtw_rhashtable_free_and_destroy(&tbl->rhead,
+				    rtw_mesh_path_rht_free, tbl);
+	rtw_mfree(tbl, sizeof(struct rtw_mesh_table));
+}
+
+/**
+ *
+ * rtw_mesh_path_assign_nexthop - update mesh path next hop
+ *
+ * @mpath: mesh path to update
+ * @sta: next hop to assign
+ *
+ * Locking: mpath->state_lock must be held when calling this function
+ */
+void rtw_mesh_path_assign_nexthop(struct rtw_mesh_path *mpath, struct sta_info *sta)
+{
+	struct xmit_frame *xframe;
+	_list *list, *head;
+
+	rtw_rcu_assign_pointer(mpath->next_hop, sta);
+
+	enter_critical_bh(&mpath->frame_queue.lock);
+	head = &mpath->frame_queue.queue;
+	list = get_next(head);
+	while (rtw_end_of_queue_search(head, list) == _FALSE) {
+		xframe = LIST_CONTAINOR(list, struct xmit_frame, list);
+		list = get_next(list);
+		_rtw_memcpy(xframe->attrib.ra, sta->cmn.mac_addr, ETH_ALEN);
+	}
+
+	exit_critical_bh(&mpath->frame_queue.lock);
+}
+
+static void rtw_prepare_for_gate(struct xmit_frame *xframe, char *dst_addr,
+			     struct rtw_mesh_path *gate_mpath)
+{
+	struct pkt_attrib *attrib = &xframe->attrib;
+	char *next_hop;
+
+	if (attrib->mesh_frame_mode == MESH_UCAST_DATA)
+		attrib->mesh_frame_mode = MESH_UCAST_PX_DATA;
+
+	/* update next hop */
+	rtw_rcu_read_lock();
+	next_hop = rtw_rcu_dereference(gate_mpath->next_hop)->cmn.mac_addr;
+	_rtw_memcpy(attrib->ra, next_hop, ETH_ALEN);
+	rtw_rcu_read_unlock();
+	_rtw_memcpy(attrib->mda, dst_addr, ETH_ALEN);
+}
+
+/**
+ *
+ * rtw_mesh_path_move_to_queue - Move or copy frames from one mpath queue to another
+ *
+ * This function is used to transfer or copy frames from an unresolved mpath to
+ * a gate mpath.  The function also adds the Address Extension field and
+ * updates the next hop.
+ *
+ * If a frame already has an Address Extension field, only the next hop and
+ * destination addresses are updated.
+ *
+ * The gate mpath must be an active mpath with a valid mpath->next_hop.
+ *
+ * @mpath: An active mpath the frames will be sent to (i.e. the gate)
+ * @from_mpath: The failed mpath
+ * @copy: When true, copy all the frames to the new mpath queue.  When false,
+ * move them.
+ */
+static void rtw_mesh_path_move_to_queue(struct rtw_mesh_path *gate_mpath,
+				    struct rtw_mesh_path *from_mpath,
+				    bool copy)
+{
+	struct xmit_frame *fskb;
+	_list *list, *head;
+	_list failq;
+	u32 failq_len;
+	_irqL flags;
+
+	if (rtw_warn_on(gate_mpath == from_mpath))
+		return;
+	if (rtw_warn_on(!gate_mpath->next_hop))
+		return;
+
+	_rtw_init_listhead(&failq);
+
+	_enter_critical_bh(&from_mpath->frame_queue.lock, &flags);
+	rtw_list_splice_init(&from_mpath->frame_queue.queue, &failq);
+	failq_len = from_mpath->frame_queue_len;
+	from_mpath->frame_queue_len = 0;
+	_exit_critical_bh(&from_mpath->frame_queue.lock, &flags);
+
+	head = &failq;
+	list = get_next(head);
+	while (rtw_end_of_queue_search(head, list) == _FALSE) {
+		if (gate_mpath->frame_queue_len >= RTW_MESH_FRAME_QUEUE_LEN) {
+			RTW_MPATH_DBG(FUNC_ADPT_FMT" mpath queue for gate %pM is full!\n"
+				, FUNC_ADPT_ARG(gate_mpath->adapter), gate_mpath->dst);
+			break;
+		}
+
+		fskb = LIST_CONTAINOR(list, struct xmit_frame, list);
+		list = get_next(list);
+
+		rtw_list_delete(&fskb->list);
+		failq_len--;
+		rtw_prepare_for_gate(fskb, gate_mpath->dst, gate_mpath);
+		_enter_critical_bh(&gate_mpath->frame_queue.lock, &flags);
+		rtw_list_insert_tail(&fskb->list, get_list_head(&gate_mpath->frame_queue));
+		gate_mpath->frame_queue_len++;
+		_exit_critical_bh(&gate_mpath->frame_queue.lock, &flags);
+
+		#if 0 /* TODO: copy */
+		skb = rtw_skb_copy(fskb);
+		if (rtw_warn_on(!skb))
+			break;
+
+		rtw_prepare_for_gate(skb, gate_mpath->dst, gate_mpath);
+		skb_queue_tail(&gate_mpath->frame_queue, skb);
+
+		if (copy)
+			continue;
+
+		__skb_unlink(fskb, &failq);
+		rtw_skb_free(fskb);
+		#endif
+	}
+
+	RTW_MPATH_DBG(FUNC_ADPT_FMT" mpath queue for gate %pM has %d frames\n"
+		, FUNC_ADPT_ARG(gate_mpath->adapter), gate_mpath->dst, gate_mpath->frame_queue_len);
+
+	if (!copy)
+		return;
+
+	_enter_critical_bh(&from_mpath->frame_queue.lock, &flags);
+	rtw_list_splice(&failq, &from_mpath->frame_queue.queue);
+	from_mpath->frame_queue_len += failq_len;
+	_exit_critical_bh(&from_mpath->frame_queue.lock, &flags);
+}
+
+
+static struct rtw_mesh_path *rtw_mpath_lookup(struct rtw_mesh_table *tbl, const u8 *dst)
+{
+	struct rtw_mesh_path *mpath;
+
+	if (!tbl)
+		return NULL;
+
+	mpath = rtw_rhashtable_lookup_fast(&tbl->rhead, dst, rtw_mesh_rht_params);
+
+	if (mpath && rtw_mpath_expired(mpath)) {
+		enter_critical_bh(&mpath->state_lock);
+		mpath->flags &= ~RTW_MESH_PATH_ACTIVE;
+		exit_critical_bh(&mpath->state_lock);
+	}
+	return mpath;
+}
+
+/**
+ * rtw_mesh_path_lookup - look up a path in the mesh path table
+ * @sdata: local subif
+ * @dst: hardware address (ETH_ALEN length) of destination
+ *
+ * Returns: pointer to the mesh path structure, or NULL if not found
+ *
+ * Locking: must be called within a read rcu section.
+ */
+struct rtw_mesh_path *
+rtw_mesh_path_lookup(_adapter *adapter, const u8 *dst)
+{
+	return rtw_mpath_lookup(adapter->mesh_info.mesh_paths, dst);
+}
+
+struct rtw_mesh_path *
+rtw_mpp_path_lookup(_adapter *adapter, const u8 *dst)
+{
+	return rtw_mpath_lookup(adapter->mesh_info.mpp_paths, dst);
+}
+
+static struct rtw_mesh_path *
+__rtw_mesh_path_lookup_by_idx(struct rtw_mesh_table *tbl, int idx)
+{
+	int i = 0, ret;
+	struct rtw_mesh_path *mpath = NULL;
+	rtw_rhashtable_iter iter;
+
+	if (!tbl)
+		return NULL;
+
+	ret = rtw_rhashtable_walk_enter(&tbl->rhead, &iter);
+	if (ret)
+		return NULL;
+
+	ret = rtw_rhashtable_walk_start(&iter);
+	if (ret && ret != -EAGAIN)
+		goto err;
+
+	while ((mpath = rtw_rhashtable_walk_next(&iter))) {
+		if (IS_ERR(mpath) && PTR_ERR(mpath) == -EAGAIN)
+			continue;
+		if (IS_ERR(mpath))
+			break;
+		if (i++ == idx)
+			break;
+	}
+err:
+	rtw_rhashtable_walk_stop(&iter);
+	rtw_rhashtable_walk_exit(&iter);
+
+	if (IS_ERR(mpath) || !mpath)
+		return NULL;
+
+	if (rtw_mpath_expired(mpath)) {
+		enter_critical_bh(&mpath->state_lock);
+		mpath->flags &= ~RTW_MESH_PATH_ACTIVE;
+		exit_critical_bh(&mpath->state_lock);
+	}
+	return mpath;
+}
+
+/**
+ * rtw_mesh_path_lookup_by_idx - look up a path in the mesh path table by its index
+ * @idx: index
+ * @sdata: local subif, or NULL for all entries
+ *
+ * Returns: pointer to the mesh path structure, or NULL if not found.
+ *
+ * Locking: must be called within a read rcu section.
+ */
+struct rtw_mesh_path *
+rtw_mesh_path_lookup_by_idx(_adapter *adapter, int idx)
+{
+	return __rtw_mesh_path_lookup_by_idx(adapter->mesh_info.mesh_paths, idx);
+}
+
+/**
+ * rtw_mpp_path_lookup_by_idx - look up a path in the proxy path table by its index
+ * @idx: index
+ * @sdata: local subif, or NULL for all entries
+ *
+ * Returns: pointer to the proxy path structure, or NULL if not found.
+ *
+ * Locking: must be called within a read rcu section.
+ */
+struct rtw_mesh_path *
+rtw_mpp_path_lookup_by_idx(_adapter *adapter, int idx)
+{
+	return __rtw_mesh_path_lookup_by_idx(adapter->mesh_info.mpp_paths, idx);
+}
+
+/**
+ * rtw_mesh_path_add_gate - add the given mpath to a mesh gate to our path table
+ * @mpath: gate path to add to table
+ */
+int rtw_mesh_path_add_gate(struct rtw_mesh_path *mpath)
+{
+	struct rtw_mesh_cfg *mcfg;
+	struct rtw_mesh_info *minfo;
+	struct rtw_mesh_table *tbl;
+	int err, ori_num_gates;
+
+	rtw_rcu_read_lock();
+	tbl = mpath->adapter->mesh_info.mesh_paths;
+	if (!tbl) {
+		err = -ENOENT;
+		goto err_rcu;
+	}
+
+	enter_critical_bh(&mpath->state_lock);
+	mcfg = &mpath->adapter->mesh_cfg;
+	mpath->gate_timeout = rtw_get_current_time() +
+			      rtw_ms_to_systime(mcfg->path_gate_timeout_factor *
+					        mpath->gate_ann_int);
+	if (mpath->is_gate) {
+		err = -EEXIST;
+		exit_critical_bh(&mpath->state_lock);
+		goto err_rcu;
+	}
+
+	minfo = &mpath->adapter->mesh_info;
+	mpath->is_gate = true;
+	_rtw_spinlock(&tbl->gates_lock);
+	ori_num_gates = minfo->num_gates;
+	minfo->num_gates++;
+	rtw_hlist_add_head_rcu(&mpath->gate_list, &tbl->known_gates);
+
+	if (ori_num_gates == 0
+		|| rtw_macaddr_is_larger(mpath->dst, minfo->max_addr_gate->dst)
+	) {
+		minfo->max_addr_gate = mpath;
+		minfo->max_addr_gate_is_larger_than_self =
+			rtw_macaddr_is_larger(mpath->dst, adapter_mac_addr(mpath->adapter));
+	}
+
+	_rtw_spinunlock(&tbl->gates_lock);
+
+	exit_critical_bh(&mpath->state_lock);
+
+	if (ori_num_gates == 0) {
+		update_beacon(mpath->adapter, WLAN_EID_MESH_CONFIG, NULL, _TRUE);
+		#if CONFIG_RTW_MESH_CTO_MGATE_CARRIER
+		if (!rtw_mesh_cto_mgate_required(mpath->adapter))
+			rtw_netif_carrier_on(mpath->adapter->pnetdev);
+		#endif
+	}
+
+	RTW_MPATH_DBG(
+		  FUNC_ADPT_FMT" Mesh path: Recorded new gate: %pM. %d known gates\n",
+		  FUNC_ADPT_ARG(mpath->adapter),
+		  mpath->dst, mpath->adapter->mesh_info.num_gates);
+	err = 0;
+err_rcu:
+	rtw_rcu_read_unlock();
+	return err;
+}
+
+/**
+ * rtw_mesh_gate_del - remove a mesh gate from the list of known gates
+ * @tbl: table which holds our list of known gates
+ * @mpath: gate mpath
+ */
+void rtw_mesh_gate_del(struct rtw_mesh_table *tbl, struct rtw_mesh_path *mpath)
+{
+	struct rtw_mesh_cfg *mcfg;
+	struct rtw_mesh_info *minfo;
+	int ori_num_gates;
+
+	rtw_lockdep_assert_held(&mpath->state_lock);
+	if (!mpath->is_gate)
+		return;
+
+	mcfg = &mpath->adapter->mesh_cfg;
+	minfo = &mpath->adapter->mesh_info;
+
+	mpath->is_gate = false;
+	enter_critical_bh(&tbl->gates_lock);
+	rtw_hlist_del_rcu(&mpath->gate_list);
+	ori_num_gates = minfo->num_gates;
+	minfo->num_gates--;
+
+	if (ori_num_gates == 1) {
+		minfo->max_addr_gate = NULL;
+		minfo->max_addr_gate_is_larger_than_self = 0;
+	} else if (minfo->max_addr_gate == mpath) {
+		struct rtw_mesh_path *gate, *max_addr_gate = NULL;
+		rtw_hlist_node *node;
+
+		rtw_hlist_for_each_entry_rcu(gate, node, &tbl->known_gates, gate_list) {
+			if (!max_addr_gate || rtw_macaddr_is_larger(gate->dst, max_addr_gate->dst))
+				max_addr_gate = gate;
+		}
+		minfo->max_addr_gate = max_addr_gate;
+		minfo->max_addr_gate_is_larger_than_self =
+			rtw_macaddr_is_larger(max_addr_gate->dst, adapter_mac_addr(mpath->adapter));
+	}
+
+	exit_critical_bh(&tbl->gates_lock);
+
+	if (ori_num_gates == 1) {
+		update_beacon(mpath->adapter, WLAN_EID_MESH_CONFIG, NULL, _TRUE);
+		#if CONFIG_RTW_MESH_CTO_MGATE_CARRIER
+		if (rtw_mesh_cto_mgate_required(mpath->adapter))
+			rtw_netif_carrier_off(mpath->adapter->pnetdev);
+		#endif
+	}
+
+	RTW_MPATH_DBG(
+		  FUNC_ADPT_FMT" Mesh path: Deleted gate: %pM. %d known gates\n",
+		  FUNC_ADPT_ARG(mpath->adapter),
+		  mpath->dst, mpath->adapter->mesh_info.num_gates);
+}
+
+/**
+ * rtw_mesh_gate_search - search a mesh gate from the list of known gates
+ * @tbl: table which holds our list of known gates
+ * @addr: address of gate
+ */
+bool rtw_mesh_gate_search(struct rtw_mesh_table *tbl, const u8 *addr)
+{
+	struct rtw_mesh_path *gate;
+	rtw_hlist_node *node;
+	bool exist = 0;
+
+	rtw_rcu_read_lock();
+	rtw_hlist_for_each_entry_rcu(gate, node, &tbl->known_gates, gate_list) {
+		if (_rtw_memcmp(gate->dst, addr, ETH_ALEN) == _TRUE) {
+			exist = 1;
+			break;
+		}
+	}
+
+	rtw_rcu_read_unlock();
+
+	return exist;
+}
+
+/**
+ * rtw_mesh_gate_num - number of gates known to this interface
+ * @sdata: subif data
+ */
+int rtw_mesh_gate_num(_adapter *adapter)
+{
+	return adapter->mesh_info.num_gates;
+}
+
+bool rtw_mesh_is_primary_gate(_adapter *adapter)
+{
+	struct rtw_mesh_cfg *mcfg = &adapter->mesh_cfg;
+	struct rtw_mesh_info *minfo = &adapter->mesh_info;
+
+	return mcfg->dot11MeshGateAnnouncementProtocol
+		&& !minfo->max_addr_gate_is_larger_than_self;
+}
+
+void dump_known_gates(void *sel, _adapter *adapter)
+{
+	struct rtw_mesh_info *minfo = &adapter->mesh_info;
+	struct rtw_mesh_table *tbl;
+	struct rtw_mesh_path *gate;
+	rtw_hlist_node *node;
+
+	if (!rtw_mesh_gate_num(adapter))
+		goto exit;
+
+	rtw_rcu_read_lock();
+
+	tbl = minfo->mesh_paths;
+	if (!tbl)
+		goto unlock;
+
+	RTW_PRINT_SEL(sel, "num:%d\n", rtw_mesh_gate_num(adapter));
+
+	rtw_hlist_for_each_entry_rcu(gate, node, &tbl->known_gates, gate_list) {
+		RTW_PRINT_SEL(sel, "%c"MAC_FMT"\n"
+			, gate == minfo->max_addr_gate ? '*' : ' '
+			, MAC_ARG(gate->dst));
+	}
+
+unlock:
+	rtw_rcu_read_unlock();
+exit:
+	return;
+}
+
+static
+struct rtw_mesh_path *rtw_mesh_path_new(_adapter *adapter,
+				const u8 *dst)
+{
+	struct rtw_mesh_path *new_mpath;
+
+	new_mpath = rtw_zmalloc(sizeof(struct rtw_mesh_path));
+	if (!new_mpath)
+		return NULL;
+
+	_rtw_memcpy(new_mpath->dst, dst, ETH_ALEN);
+	_rtw_memset(new_mpath->rann_snd_addr, 0xFF, ETH_ALEN);
+	new_mpath->is_root = false;
+	new_mpath->adapter = adapter;
+	new_mpath->flags = 0;
+	new_mpath->gate_asked = false;
+	_rtw_init_queue(&new_mpath->frame_queue);
+	new_mpath->frame_queue_len = 0;
+	new_mpath->exp_time = rtw_get_current_time();
+	_rtw_spinlock_init(&new_mpath->state_lock);
+	rtw_init_timer(&new_mpath->timer, adapter, rtw_mesh_path_timer, new_mpath);
+
+	return new_mpath;
+}
+
+/**
+ * rtw_mesh_path_add - allocate and add a new path to the mesh path table
+ * @dst: destination address of the path (ETH_ALEN length)
+ * @sdata: local subif
+ *
+ * Returns: 0 on success
+ *
+ * State: the initial state of the new path is set to 0
+ */
+struct rtw_mesh_path *rtw_mesh_path_add(_adapter *adapter,
+				const u8 *dst)
+{
+	struct rtw_mesh_table *tbl = adapter->mesh_info.mesh_paths;
+	struct rtw_mesh_path *mpath, *new_mpath;
+	int ret;
+
+	if (!tbl)
+		return ERR_PTR(-ENOTSUPP);
+
+	if (_rtw_memcmp(dst, adapter_mac_addr(adapter), ETH_ALEN) == _TRUE)
+		/* never add ourselves as neighbours */
+		return ERR_PTR(-ENOTSUPP);
+
+	if (is_multicast_mac_addr(dst))
+		return ERR_PTR(-ENOTSUPP);
+
+	if (ATOMIC_INC_UNLESS(&adapter->mesh_info.mpaths, RTW_MESH_MAX_MPATHS) == 0)
+		return ERR_PTR(-ENOSPC);
+
+	new_mpath = rtw_mesh_path_new(adapter, dst);
+	if (!new_mpath)
+		return ERR_PTR(-ENOMEM);
+
+	do {
+		ret = rtw_rhashtable_lookup_insert_fast(&tbl->rhead,
+						    &new_mpath->rhash,
+						    rtw_mesh_rht_params);
+
+		if (ret == -EEXIST)
+			mpath = rtw_rhashtable_lookup_fast(&tbl->rhead,
+						       dst,
+						       rtw_mesh_rht_params);
+
+	} while (unlikely(ret == -EEXIST && !mpath));
+
+	if (ret && ret != -EEXIST)
+		return ERR_PTR(ret);
+
+	/* At this point either new_mpath was added, or we found a
+	 * matching entry already in the table; in the latter case
+	 * free the unnecessary new entry.
+	 */
+	if (ret == -EEXIST) {
+		rtw_mfree(new_mpath, sizeof(struct rtw_mesh_path));
+		new_mpath = mpath;
+	}
+	adapter->mesh_info.mesh_paths_generation++;
+	return new_mpath;
+}
+
+int rtw_mpp_path_add(_adapter *adapter,
+		 const u8 *dst, const u8 *mpp)
+{
+	struct rtw_mesh_table *tbl = adapter->mesh_info.mpp_paths;
+	struct rtw_mesh_path *new_mpath;
+	int ret;
+
+	if (!tbl)
+		return -ENOTSUPP;
+
+	if (_rtw_memcmp(dst, adapter_mac_addr(adapter), ETH_ALEN) == _TRUE)
+		/* never add ourselves as neighbours */
+		return -ENOTSUPP;
+
+	if (is_multicast_mac_addr(dst))
+		return -ENOTSUPP;
+
+	new_mpath = rtw_mesh_path_new(adapter, dst);
+
+	if (!new_mpath)
+		return -ENOMEM;
+
+	_rtw_memcpy(new_mpath->mpp, mpp, ETH_ALEN);
+	ret = rtw_rhashtable_lookup_insert_fast(&tbl->rhead,
+					    &new_mpath->rhash,
+					    rtw_mesh_rht_params);
+
+	adapter->mesh_info.mpp_paths_generation++;
+	return ret;
+}
+
+void dump_mpp(void *sel, _adapter *adapter)
+{
+	struct rtw_mesh_path *mpath;
+	int idx = 0;
+	char dst[ETH_ALEN];
+	char mpp[ETH_ALEN];
+
+	RTW_PRINT_SEL(sel, "%-17s %-17s\n", "dst", "mpp");
+
+	do {
+		rtw_rcu_read_lock();
+
+		mpath = rtw_mpp_path_lookup_by_idx(adapter, idx);
+		if (mpath) {
+			_rtw_memcpy(dst, mpath->dst, ETH_ALEN);
+			_rtw_memcpy(mpp, mpath->mpp, ETH_ALEN);
+		}
+
+		rtw_rcu_read_unlock();
+
+		if (mpath) {
+			RTW_PRINT_SEL(sel, MAC_FMT" "MAC_FMT"\n"
+				, MAC_ARG(dst), MAC_ARG(mpp));
+		}
+
+		idx++;
+	} while (mpath);
+}
+
+/**
+ * rtw_mesh_plink_broken - deactivates paths and sends perr when a link breaks
+ *
+ * @sta: broken peer link
+ *
+ * This function must be called from the rate control algorithm if enough
+ * delivery errors suggest that a peer link is no longer usable.
+ */
+void rtw_mesh_plink_broken(struct sta_info *sta)
+{
+	_adapter *adapter = sta->padapter;
+	struct rtw_mesh_table *tbl = adapter->mesh_info.mesh_paths;
+	static const u8 bcast[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
+	struct rtw_mesh_path *mpath;
+	rtw_rhashtable_iter iter;
+	int ret;
+
+	if (!tbl)
+		return;
+
+	ret = rtw_rhashtable_walk_enter(&tbl->rhead, &iter);
+	if (ret)
+		return;
+
+	ret = rtw_rhashtable_walk_start(&iter);
+	if (ret && ret != -EAGAIN)
+		goto out;
+
+	while ((mpath = rtw_rhashtable_walk_next(&iter))) {
+		if (IS_ERR(mpath) && PTR_ERR(mpath) == -EAGAIN)
+			continue;
+		if (IS_ERR(mpath))
+			break;
+		if (rtw_rcu_access_pointer(mpath->next_hop) == sta &&
+		    mpath->flags & RTW_MESH_PATH_ACTIVE &&
+		    !(mpath->flags & RTW_MESH_PATH_FIXED)) {
+			enter_critical_bh(&mpath->state_lock);
+			mpath->flags &= ~RTW_MESH_PATH_ACTIVE;
+			++mpath->sn;
+			exit_critical_bh(&mpath->state_lock);
+			rtw_mesh_path_error_tx(adapter,
+				adapter->mesh_cfg.element_ttl,
+				mpath->dst, mpath->sn,
+				WLAN_REASON_MESH_PATH_DEST_UNREACHABLE, bcast);
+		}
+	}
+out:
+	rtw_rhashtable_walk_stop(&iter);
+	rtw_rhashtable_walk_exit(&iter);
+}
+
+static void rtw_mesh_path_free_rcu(struct rtw_mesh_table *tbl,
+			       struct rtw_mesh_path *mpath)
+{
+	_adapter *adapter = mpath->adapter;
+
+	enter_critical_bh(&mpath->state_lock);
+	mpath->flags |= RTW_MESH_PATH_RESOLVING | RTW_MESH_PATH_DELETED;
+	rtw_mesh_gate_del(tbl, mpath);
+	exit_critical_bh(&mpath->state_lock);
+	_cancel_timer_ex(&mpath->timer);
+	ATOMIC_DEC(&adapter->mesh_info.mpaths);
+	ATOMIC_DEC(&tbl->entries);
+	_rtw_spinlock_free(&mpath->state_lock);
+
+	rtw_mesh_path_flush_pending(mpath);
+
+	rtw_mpath_free_rcu(mpath);
+}
+
+static void __rtw_mesh_path_del(struct rtw_mesh_table *tbl, struct rtw_mesh_path *mpath)
+{
+	rtw_rhashtable_remove_fast(&tbl->rhead, &mpath->rhash, rtw_mesh_rht_params);
+	rtw_mesh_path_free_rcu(tbl, mpath);
+}
+
+/**
+ * rtw_mesh_path_flush_by_nexthop - Deletes mesh paths if their next hop matches
+ *
+ * @sta: mesh peer to match
+ *
+ * RCU notes: this function is called when a mesh plink transitions from
+ * PLINK_ESTAB to any other state, since PLINK_ESTAB state is the only one that
+ * allows path creation. This will happen before the sta can be freed (because
+ * sta_info_destroy() calls this) so any reader in a rcu read block will be
+ * protected against the plink disappearing.
+ */
+void rtw_mesh_path_flush_by_nexthop(struct sta_info *sta)
+{
+	_adapter *adapter = sta->padapter;
+	struct rtw_mesh_table *tbl = adapter->mesh_info.mesh_paths;
+	struct rtw_mesh_path *mpath;
+	rtw_rhashtable_iter iter;
+	int ret;
+
+	if (!tbl)
+		return;
+
+	ret = rtw_rhashtable_walk_enter(&tbl->rhead, &iter);
+	if (ret)
+		return;
+
+	ret = rtw_rhashtable_walk_start(&iter);
+	if (ret && ret != -EAGAIN)
+		goto out;
+
+	while ((mpath = rtw_rhashtable_walk_next(&iter))) {
+		if (IS_ERR(mpath) && PTR_ERR(mpath) == -EAGAIN)
+			continue;
+		if (IS_ERR(mpath))
+			break;
+
+		if (rtw_rcu_access_pointer(mpath->next_hop) == sta)
+			__rtw_mesh_path_del(tbl, mpath);
+	}
+out:
+	rtw_rhashtable_walk_stop(&iter);
+	rtw_rhashtable_walk_exit(&iter);
+}
+
+static void rtw_mpp_flush_by_proxy(_adapter *adapter,
+			       const u8 *proxy)
+{
+	struct rtw_mesh_table *tbl = adapter->mesh_info.mpp_paths;
+	struct rtw_mesh_path *mpath;
+	rtw_rhashtable_iter iter;
+	int ret;
+
+	if (!tbl)
+		return;
+
+	ret = rtw_rhashtable_walk_enter(&tbl->rhead, &iter);
+	if (ret)
+		return;
+
+	ret = rtw_rhashtable_walk_start(&iter);
+	if (ret && ret != -EAGAIN)
+		goto out;
+
+	while ((mpath = rtw_rhashtable_walk_next(&iter))) {
+		if (IS_ERR(mpath) && PTR_ERR(mpath) == -EAGAIN)
+			continue;
+		if (IS_ERR(mpath))
+			break;
+
+		if (_rtw_memcmp(mpath->mpp, proxy, ETH_ALEN) == _TRUE)
+			__rtw_mesh_path_del(tbl, mpath);
+	}
+out:
+	rtw_rhashtable_walk_stop(&iter);
+	rtw_rhashtable_walk_exit(&iter);
+}
+
+static void rtw_table_flush_by_iface(struct rtw_mesh_table *tbl)
+{
+	struct rtw_mesh_path *mpath;
+	rtw_rhashtable_iter iter;
+	int ret;
+
+	if (!tbl)
+		return;
+	
+	ret = rtw_rhashtable_walk_enter(&tbl->rhead, &iter);
+	if (ret)
+		return;
+
+	ret = rtw_rhashtable_walk_start(&iter);
+	if (ret && ret != -EAGAIN)
+		goto out;
+
+	while ((mpath = rtw_rhashtable_walk_next(&iter))) {
+		if (IS_ERR(mpath) && PTR_ERR(mpath) == -EAGAIN)
+			continue;
+		if (IS_ERR(mpath))
+			break;
+		__rtw_mesh_path_del(tbl, mpath);
+	}
+out:
+	rtw_rhashtable_walk_stop(&iter);
+	rtw_rhashtable_walk_exit(&iter);
+}
+
+/**
+ * rtw_mesh_path_flush_by_iface - Deletes all mesh paths associated with a given iface
+ *
+ * This function deletes both mesh paths as well as mesh portal paths.
+ *
+ * @sdata: interface data to match
+ *
+ */
+void rtw_mesh_path_flush_by_iface(_adapter *adapter)
+{
+	rtw_table_flush_by_iface(adapter->mesh_info.mesh_paths);
+	rtw_table_flush_by_iface(adapter->mesh_info.mpp_paths);
+}
+
+/**
+ * rtw_table_path_del - delete a path from the mesh or mpp table
+ *
+ * @tbl: mesh or mpp path table
+ * @sdata: local subif
+ * @addr: dst address (ETH_ALEN length)
+ *
+ * Returns: 0 if successful
+ */
+static int rtw_table_path_del(struct rtw_mesh_table *tbl,
+			  const u8 *addr)
+{
+	struct rtw_mesh_path *mpath;
+
+	if (!tbl)
+		return -ENXIO;
+
+	rtw_rcu_read_lock();
+	mpath = rtw_rhashtable_lookup_fast(&tbl->rhead, addr, rtw_mesh_rht_params);
+	if (!mpath) {
+		rtw_rcu_read_unlock();
+		return -ENXIO;
+	}
+
+	__rtw_mesh_path_del(tbl, mpath);
+	rtw_rcu_read_unlock();
+	return 0;
+}
+
+
+/**
+ * rtw_mesh_path_del - delete a mesh path from the table
+ *
+ * @addr: dst address (ETH_ALEN length)
+ * @sdata: local subif
+ *
+ * Returns: 0 if successful
+ */
+int rtw_mesh_path_del(_adapter *adapter, const u8 *addr)
+{
+	int err;
+
+	/* flush relevant mpp entries first */
+	rtw_mpp_flush_by_proxy(adapter, addr);
+
+	err = rtw_table_path_del(adapter->mesh_info.mesh_paths, addr);
+	adapter->mesh_info.mesh_paths_generation++;
+	return err;
+}
+
+/**
+ * rtw_mesh_path_tx_pending - sends pending frames in a mesh path queue
+ *
+ * @mpath: mesh path to activate
+ *
+ * Locking: the state_lock of the mpath structure must NOT be held when calling
+ * this function.
+ */
+void rtw_mesh_path_tx_pending(struct rtw_mesh_path *mpath)
+{
+	if (mpath->flags & RTW_MESH_PATH_ACTIVE) {
+		struct rtw_mesh_info *minfo = &mpath->adapter->mesh_info;
+		_list q;
+		u32 q_len = 0;
+
+		_rtw_init_listhead(&q);
+
+		/* move to local queue */
+		enter_critical_bh(&mpath->frame_queue.lock);
+		if (mpath->frame_queue_len) {
+			rtw_list_splice_init(&mpath->frame_queue.queue, &q);
+			q_len = mpath->frame_queue_len;
+			mpath->frame_queue_len = 0;
+		}
+		exit_critical_bh(&mpath->frame_queue.lock);
+
+		if (q_len) {
+			/* move to mpath_tx_queue */
+			enter_critical_bh(&minfo->mpath_tx_queue.lock);
+			rtw_list_splice_tail(&q, &minfo->mpath_tx_queue.queue);
+			minfo->mpath_tx_queue_len += q_len;
+			exit_critical_bh(&minfo->mpath_tx_queue.lock);
+
+			/* schedule mpath_tx_tasklet */
+			tasklet_hi_schedule(&minfo->mpath_tx_tasklet);
+		}
+	}
+}
+
+/**
+ * rtw_mesh_path_send_to_gates - sends pending frames to all known mesh gates
+ *
+ * @mpath: mesh path whose queue will be emptied
+ *
+ * If there is only one gate, the frames are transferred from the failed mpath
+ * queue to that gate's queue.  If there are more than one gates, the frames
+ * are copied from each gate to the next.  After frames are copied, the
+ * mpath queues are emptied onto the transmission queue.
+ */
+int rtw_mesh_path_send_to_gates(struct rtw_mesh_path *mpath)
+{
+	_adapter *adapter = mpath->adapter;
+	struct rtw_mesh_table *tbl;
+	struct rtw_mesh_path *from_mpath = mpath;
+	struct rtw_mesh_path *gate;
+	bool copy = false;
+	rtw_hlist_node *node;
+
+	tbl = adapter->mesh_info.mesh_paths;
+	if (!tbl)
+		return 0;
+
+	rtw_rcu_read_lock();
+	rtw_hlist_for_each_entry_rcu(gate, node, &tbl->known_gates, gate_list) {
+		if (gate->flags & RTW_MESH_PATH_ACTIVE) {
+			RTW_MPATH_DBG(FUNC_ADPT_FMT" Forwarding to %pM\n",
+				FUNC_ADPT_ARG(adapter), gate->dst);
+			rtw_mesh_path_move_to_queue(gate, from_mpath, copy);
+			from_mpath = gate;
+			copy = true;
+		} else {
+			RTW_MPATH_DBG(
+				  FUNC_ADPT_FMT" Not forwarding to %pM (flags %#x)\n",
+				  FUNC_ADPT_ARG(adapter), gate->dst, gate->flags);
+		}
+	}
+
+	rtw_hlist_for_each_entry_rcu(gate, node, &tbl->known_gates, gate_list) {
+		RTW_MPATH_DBG(FUNC_ADPT_FMT" Sending to %pM\n",
+			FUNC_ADPT_ARG(adapter), gate->dst);
+		rtw_mesh_path_tx_pending(gate);
+	}
+	rtw_rcu_read_unlock();
+
+	return (from_mpath == mpath) ? -EHOSTUNREACH : 0;
+}
+
+/**
+ * rtw_mesh_path_discard_frame - discard a frame whose path could not be resolved
+ *
+ * @skb: frame to discard
+ * @sdata: network subif the frame was to be sent through
+ *
+ * Locking: the function must me called within a rcu_read_lock region
+ */
+void rtw_mesh_path_discard_frame(_adapter *adapter,
+			     struct xmit_frame *xframe)
+{
+	rtw_free_xmitframe(&adapter->xmitpriv, xframe);
+	adapter->mesh_info.mshstats.dropped_frames_no_route++;
+}
+
+/**
+ * rtw_mesh_path_flush_pending - free the pending queue of a mesh path
+ *
+ * @mpath: mesh path whose queue has to be freed
+ *
+ * Locking: the function must me called within a rcu_read_lock region
+ */
+void rtw_mesh_path_flush_pending(struct rtw_mesh_path *mpath)
+{
+	struct xmit_frame *xframe;
+	_list *list, *head;
+	_list tmp;
+
+	_rtw_init_listhead(&tmp);
+
+	enter_critical_bh(&mpath->frame_queue.lock);
+	rtw_list_splice_init(&mpath->frame_queue.queue, &tmp);
+	mpath->frame_queue_len = 0;
+	exit_critical_bh(&mpath->frame_queue.lock);
+
+	head = &tmp;
+	list = get_next(head);
+	while (rtw_end_of_queue_search(head, list) == _FALSE) {
+		xframe = LIST_CONTAINOR(list, struct xmit_frame, list);
+		list = get_next(list);
+		rtw_list_delete(&xframe->list);
+		rtw_mesh_path_discard_frame(mpath->adapter, xframe);
+	}
+}
+
+/**
+ * rtw_mesh_path_fix_nexthop - force a specific next hop for a mesh path
+ *
+ * @mpath: the mesh path to modify
+ * @next_hop: the next hop to force
+ *
+ * Locking: this function must be called holding mpath->state_lock
+ */
+void rtw_mesh_path_fix_nexthop(struct rtw_mesh_path *mpath, struct sta_info *next_hop)
+{
+	enter_critical_bh(&mpath->state_lock);
+	rtw_mesh_path_assign_nexthop(mpath, next_hop);
+	mpath->sn = 0xffff;
+	mpath->metric = 0;
+	mpath->hop_count = 0;
+	mpath->exp_time = 0;
+	mpath->flags = RTW_MESH_PATH_FIXED | RTW_MESH_PATH_SN_VALID;
+	rtw_mesh_path_activate(mpath);
+	exit_critical_bh(&mpath->state_lock);
+	rtw_ewma_err_rate_init(&next_hop->metrics.err_rate);
+	/* init it at a low value - 0 start is tricky */
+	rtw_ewma_err_rate_add(&next_hop->metrics.err_rate, 1);
+	rtw_mesh_path_tx_pending(mpath);
+}
+
+int rtw_mesh_pathtbl_init(_adapter *adapter)
+{
+	struct rtw_mesh_table *tbl_path, *tbl_mpp;
+	int ret;
+
+	tbl_path = rtw_mesh_table_alloc();
+	if (!tbl_path)
+		return -ENOMEM;
+
+	tbl_mpp = rtw_mesh_table_alloc();
+	if (!tbl_mpp) {
+		ret = -ENOMEM;
+		goto free_path;
+	}
+
+	rtw_rhashtable_init(&tbl_path->rhead, &rtw_mesh_rht_params);
+	rtw_rhashtable_init(&tbl_mpp->rhead, &rtw_mesh_rht_params);
+
+	adapter->mesh_info.mesh_paths = tbl_path;
+	adapter->mesh_info.mpp_paths = tbl_mpp;
+
+	return 0;
+
+free_path:
+	rtw_mesh_table_free(tbl_path);
+	return ret;
+}
+
+static
+void rtw_mesh_path_tbl_expire(_adapter *adapter,
+			  struct rtw_mesh_table *tbl)
+{
+	struct rtw_mesh_path *mpath;
+	rtw_rhashtable_iter iter;
+	int ret;
+
+	if (!tbl)
+		return;
+
+	ret = rtw_rhashtable_walk_enter(&tbl->rhead, &iter);
+	if (ret)
+		return;
+
+	ret = rtw_rhashtable_walk_start(&iter);
+	if (ret && ret != -EAGAIN)
+		goto out;
+
+	while ((mpath = rtw_rhashtable_walk_next(&iter))) {
+		if (IS_ERR(mpath) && PTR_ERR(mpath) == -EAGAIN)
+			continue;
+		if (IS_ERR(mpath))
+			break;
+		if ((!(mpath->flags & RTW_MESH_PATH_RESOLVING)) &&
+		    (!(mpath->flags & RTW_MESH_PATH_FIXED)) &&
+		     rtw_time_after(rtw_get_current_time(), mpath->exp_time + RTW_MESH_PATH_EXPIRE))
+			__rtw_mesh_path_del(tbl, mpath);
+
+		if (mpath->is_gate &&  /* need not to deal with non-gate case */
+		    rtw_time_after(rtw_get_current_time(), mpath->gate_timeout)) {
+			RTW_MPATH_DBG(FUNC_ADPT_FMT"mpath [%pM] expired systime is %lu systime is %lu\n",
+				      FUNC_ADPT_ARG(adapter), mpath->dst,
+				      mpath->gate_timeout, rtw_get_current_time());
+			enter_critical_bh(&mpath->state_lock);
+			if (mpath->gate_asked) { /* asked gate before */
+				rtw_mesh_gate_del(tbl, mpath);
+				exit_critical_bh(&mpath->state_lock);
+			} else {
+				mpath->gate_asked = true;
+				mpath->gate_timeout = rtw_get_current_time() + rtw_ms_to_systime(mpath->gate_ann_int);
+				exit_critical_bh(&mpath->state_lock);
+				rtw_mesh_queue_preq(mpath, RTW_PREQ_Q_F_START | RTW_PREQ_Q_F_REFRESH);
+				RTW_MPATH_DBG(FUNC_ADPT_FMT"mpath [%pM] ask mesh gate existence (is_root=%d)\n",
+				      FUNC_ADPT_ARG(adapter), mpath->dst, mpath->is_root);
+			}
+		}
+	}
+
+out:
+	rtw_rhashtable_walk_stop(&iter);
+	rtw_rhashtable_walk_exit(&iter);
+}
+
+void rtw_mesh_path_expire(_adapter *adapter)
+{
+	rtw_mesh_path_tbl_expire(adapter, adapter->mesh_info.mesh_paths);
+	rtw_mesh_path_tbl_expire(adapter, adapter->mesh_info.mpp_paths);
+}
+
+void rtw_mesh_pathtbl_unregister(_adapter *adapter)
+{
+	if (adapter->mesh_info.mesh_paths) {
+		rtw_mesh_table_free(adapter->mesh_info.mesh_paths);
+		adapter->mesh_info.mesh_paths = NULL;
+	}
+
+	if (adapter->mesh_info.mpp_paths) {
+		rtw_mesh_table_free(adapter->mesh_info.mpp_paths);
+		adapter->mesh_info.mpp_paths = NULL;
+	}
+}
+#endif /* CONFIG_RTW_MESH */
+
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/core/mesh/rtw_mesh_pathtbl.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/core/mesh/rtw_mesh_pathtbl.h
--- linux-5.6.3/3rdparty/rtl8821ce/core/mesh/rtw_mesh_pathtbl.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/core/mesh/rtw_mesh_pathtbl.h	2020-04-10 16:35:06.770657920 +0300
@@ -0,0 +1,206 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#ifndef __RTW_MESH_PATHTBL_H_
+#define __RTW_MESH_PATHTBL_H_
+
+#ifndef DBG_RTW_MPATH
+#define DBG_RTW_MPATH 1
+#endif
+#if DBG_RTW_MPATH
+#define RTW_MPATH_DBG(fmt, arg...) RTW_PRINT(fmt, ##arg)
+#else
+#define RTW_MPATH_DBG(fmt, arg...) do {} while (0)
+#endif
+
+/**
+ * enum rtw_mesh_path_flags - mesh path flags
+ *
+ * @RTW_MESH_PATH_ACTIVE: the mesh path can be used for forwarding
+ * @RTW_MESH_PATH_RESOLVING: the discovery process is running for this mesh path
+ * @RTW_MESH_PATH_SN_VALID: the mesh path contains a valid destination sequence
+ *	number
+ * @RTW_MESH_PATH_FIXED: the mesh path has been manually set and should not be
+ *	modified
+ * @RTW_MESH_PATH_RESOLVED: the mesh path can has been resolved
+ * @RTW_MESH_PATH_REQ_QUEUED: there is an unsent path request for this destination
+ *	already queued up, waiting for the discovery process to start.
+ * @RTW_MESH_PATH_DELETED: the mesh path has been deleted and should no longer
+ *	be used
+ * @RTW_MESH_PATH_ROOT_ADD_CHK: root additional check in root mode.
+ *	With this flag, It will try the last used rann_snd_addr
+ * @RTW_MESH_PATH_PEER_AKA: only used toward a peer, only used in active keep
+ *	alive mechanism. PREQ's da = path dst
+ * 
+ * RTW_MESH_PATH_RESOLVED is used by the mesh path timer to
+ * decide when to stop or cancel the mesh path discovery.
+ */
+enum rtw_mesh_path_flags {
+	RTW_MESH_PATH_ACTIVE =	BIT(0),
+	RTW_MESH_PATH_RESOLVING =	BIT(1),
+	RTW_MESH_PATH_SN_VALID =	BIT(2),
+	RTW_MESH_PATH_FIXED	=	BIT(3),
+	RTW_MESH_PATH_RESOLVED =	BIT(4),
+	RTW_MESH_PATH_REQ_QUEUED =	BIT(5),
+	RTW_MESH_PATH_DELETED =	BIT(6),
+	RTW_MESH_PATH_ROOT_ADD_CHK =	BIT(7),
+	RTW_MESH_PATH_PEER_AKA =	BIT(8),
+};
+
+/**
+ * struct rtw_mesh_path - mesh path structure
+ *
+ * @dst: mesh path destination mac address
+ * @mpp: mesh proxy mac address
+ * @rhash: rhashtable list pointer
+ * @gate_list: list pointer for known gates list
+ * @sdata: mesh subif
+ * @next_hop: mesh neighbor to which frames for this destination will be
+ *	forwarded
+ * @timer: mesh path discovery timer
+ * @frame_queue: pending queue for frames sent to this destination while the
+ *	path is unresolved
+ * @rcu: rcu head for freeing mesh path
+ * @sn: target sequence number
+ * @metric: current metric to this destination
+ * @hop_count: hops to destination
+ * @exp_time: in jiffies, when the path will expire or when it expired
+ * @discovery_timeout: timeout (lapse in jiffies) used for the last discovery
+ *	retry
+ * @discovery_retries: number of discovery retries
+ * @flags: mesh path flags, as specified on &enum rtw_mesh_path_flags
+ * @state_lock: mesh path state lock used to protect changes to the
+ * mpath itself.  No need to take this lock when adding or removing
+ * an mpath to a hash bucket on a path table.
+ * @rann_snd_addr: the RANN sender address
+ * @rann_metric: the aggregated path metric towards the root node
+ * @last_preq_to_root: Timestamp of last PREQ sent to root
+ * @is_root: the destination station of this path is a root node
+ * @is_gate: the destination station of this path is a mesh gate
+ *
+ *
+ * The dst address is unique in the mesh path table. Since the mesh_path is
+ * protected by RCU, deleting the next_hop STA must remove / substitute the
+ * mesh_path structure and wait until that is no longer reachable before
+ * destroying the STA completely.
+ */
+struct rtw_mesh_path {
+	u8 dst[ETH_ALEN];
+	u8 mpp[ETH_ALEN];	/* used for MPP or MAP */
+	rtw_rhash_head rhash;
+	rtw_hlist_node gate_list;
+	_adapter *adapter;
+	struct sta_info __rcu *next_hop;
+	_timer timer;
+	_queue frame_queue;
+	u32 frame_queue_len;
+	rtw_rcu_head rcu;
+	u32 sn;
+	u32 metric;
+	u8 hop_count;
+	systime exp_time;
+	systime discovery_timeout;
+	systime gate_timeout;
+	u32 gate_ann_int;    /* gate announce interval */
+	u8 discovery_retries;
+	enum rtw_mesh_path_flags flags;
+	_lock state_lock;
+	u8 rann_snd_addr[ETH_ALEN];
+#ifdef CONFIG_RTW_MESH_ADD_ROOT_CHK
+	u8 add_chk_rann_snd_addr[ETH_ALEN];
+#endif
+	u32 rann_metric;
+	unsigned long last_preq_to_root;
+	bool is_root;
+	bool is_gate;
+	bool gate_asked;
+};
+
+/**
+ * struct rtw_mesh_table
+ *
+ * @known_gates: list of known mesh gates and their mpaths by the station. The
+ * gate's mpath may or may not be resolved and active.
+ * @gates_lock: protects updates to known_gates
+ * @rhead: the rhashtable containing struct mesh_paths, keyed by dest addr
+ * @entries: number of entries in the table
+ */
+struct rtw_mesh_table {
+	rtw_hlist_head known_gates;
+	_lock gates_lock;
+	rtw_rhashtable rhead;
+	ATOMIC_T entries;
+};
+
+#define RTW_MESH_PATH_EXPIRE (600 * HZ)
+
+/* Maximum number of paths per interface */
+#define RTW_MESH_MAX_MPATHS		1024
+
+/* Number of frames buffered per destination for unresolved destinations */
+#define RTW_MESH_FRAME_QUEUE_LEN	10
+
+int rtw_mesh_nexthop_lookup(_adapter *adapter,
+	const u8 *mda, const u8 *msa, u8 *ra);
+int rtw_mesh_nexthop_resolve(_adapter *adapter,
+			 struct xmit_frame *xframe);
+
+struct rtw_mesh_path *rtw_mesh_path_lookup(_adapter *adapter,
+				   const u8 *dst);
+struct rtw_mesh_path *rtw_mpp_path_lookup(_adapter *adapter,
+				  const u8 *dst);
+int rtw_mpp_path_add(_adapter *adapter,
+		 const u8 *dst, const u8 *mpp);
+void dump_mpp(void *sel, _adapter *adapter);
+
+struct rtw_mesh_path *
+rtw_mesh_path_lookup_by_idx(_adapter *adapter, int idx);
+struct rtw_mesh_path *
+rtw_mpp_path_lookup_by_idx(_adapter *adapter, int idx);
+void rtw_mesh_path_fix_nexthop(struct rtw_mesh_path *mpath, struct sta_info *next_hop);
+void rtw_mesh_path_expire(_adapter *adapter);
+
+struct rtw_mesh_path *
+rtw_mesh_path_add(_adapter *adapter, const u8 *dst);
+
+int rtw_mesh_path_add_gate(struct rtw_mesh_path *mpath);
+void rtw_mesh_gate_del(struct rtw_mesh_table *tbl, struct rtw_mesh_path *mpath);
+bool rtw_mesh_gate_search(struct rtw_mesh_table *tbl, const u8 *addr);
+int rtw_mesh_path_send_to_gates(struct rtw_mesh_path *mpath);
+int rtw_mesh_gate_num(_adapter *adapter);
+bool rtw_mesh_is_primary_gate(_adapter *adapter);
+void dump_known_gates(void *sel, _adapter *adapter);
+
+void rtw_mesh_plink_broken(struct sta_info *sta);
+
+void rtw_mesh_path_assign_nexthop(struct rtw_mesh_path *mpath, struct sta_info *sta);
+void rtw_mesh_path_flush_pending(struct rtw_mesh_path *mpath);
+void rtw_mesh_path_tx_pending(struct rtw_mesh_path *mpath);
+int rtw_mesh_pathtbl_init(_adapter *adapter);
+void rtw_mesh_pathtbl_unregister(_adapter *adapter);
+int rtw_mesh_path_del(_adapter *adapter, const u8 *addr);
+
+void rtw_mesh_path_flush_by_nexthop(struct sta_info *sta);
+void rtw_mesh_path_discard_frame(_adapter *adapter,
+			     struct xmit_frame *xframe);
+
+static inline void rtw_mesh_path_activate(struct rtw_mesh_path *mpath)
+{
+	mpath->flags |= RTW_MESH_PATH_ACTIVE | RTW_MESH_PATH_RESOLVED;
+}
+
+void rtw_mesh_path_flush_by_iface(_adapter *adapter);
+
+#endif /* __RTW_MESH_PATHTBL_H_ */
+
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/core/rtw_ap.c linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/core/rtw_ap.c
--- linux-5.6.3/3rdparty/rtl8821ce/core/rtw_ap.c	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/core/rtw_ap.c	2020-04-10 16:35:06.771657967 +0300
@@ -0,0 +1,5406 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#define _RTW_AP_C_
+
+#include <drv_types.h>
+#include <hal_data.h>
+
+#ifdef CONFIG_AP_MODE
+
+extern unsigned char	RTW_WPA_OUI[];
+extern unsigned char	WMM_OUI[];
+extern unsigned char	WPS_OUI[];
+extern unsigned char	P2P_OUI[];
+extern unsigned char	WFD_OUI[];
+
+void init_mlme_ap_info(_adapter *padapter)
+{
+	struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
+
+	_rtw_spinlock_init(&pmlmepriv->bcn_update_lock);
+	/* pmlmeext->bstart_bss = _FALSE; */
+}
+
+void free_mlme_ap_info(_adapter *padapter)
+{
+	struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
+
+	stop_ap_mode(padapter);
+	_rtw_spinlock_free(&pmlmepriv->bcn_update_lock);
+
+}
+
+/*
+* Set TIM IE
+* return length of total TIM IE
+*/
+u8 rtw_set_tim_ie(u8 dtim_cnt, u8 dtim_period
+	, const u8 *tim_bmp, u8 tim_bmp_len, u8 *tim_ie)
+{
+	u8 *p = tim_ie;
+	u8 i, n1, n2;
+	u8 bmp_len;
+
+	if (rtw_bmp_not_empty(tim_bmp, tim_bmp_len)) {
+		/* find the first nonzero octet in tim_bitmap */
+		for (i = 0; i < tim_bmp_len; i++)
+			if (tim_bmp[i])
+				break;
+		n1 = i & 0xFE;
+	
+		/* find the last nonzero octet in tim_bitmap, except octet 0 */
+		for (i = tim_bmp_len - 1; i > 0; i--)
+			if (tim_bmp[i])
+				break;
+		n2 = i;
+		bmp_len = n2 - n1 + 1;
+	} else {
+		n1 = n2 = 0;
+		bmp_len = 1;
+	}
+
+	*p++ = WLAN_EID_TIM;
+	*p++ = 2 + 1 + bmp_len;
+	*p++ = dtim_cnt;
+	*p++ = dtim_period;
+	*p++ = (rtw_bmp_is_set(tim_bmp, tim_bmp_len, 0) ? BIT0 : 0) | n1;
+	_rtw_memcpy(p, tim_bmp + n1, bmp_len);
+
+#if 0
+	RTW_INFO("n1:%u, n2:%u, bmp_offset:%u, bmp_len:%u\n", n1, n2, n1 / 2, bmp_len);
+	RTW_INFO_DUMP("tim_ie: ", tim_ie + 2, 2 + 1 + bmp_len);
+#endif
+	return 2 + 2 + 1 + bmp_len;
+}
+
+static void update_BCNTIM(_adapter *padapter)
+{
+	struct sta_priv *pstapriv = &padapter->stapriv;
+	struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv);
+	struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
+	WLAN_BSSID_EX *pnetwork_mlmeext = &(pmlmeinfo->network);
+	unsigned char *pie = pnetwork_mlmeext->IEs;
+
+#if 0
+
+
+	/* update TIM IE */
+	/* if(rtw_tim_map_anyone_be_set(padapter, pstapriv->tim_bitmap)) */
+#endif
+	if (_TRUE) {
+		u8 *p, *dst_ie, *premainder_ie = NULL, *pbackup_remainder_ie = NULL;
+		uint offset, tmp_len, tim_ielen, tim_ie_offset, remainder_ielen;
+
+		p = rtw_get_ie(pie + _FIXED_IE_LENGTH_, _TIM_IE_, &tim_ielen, pnetwork_mlmeext->IELength - _FIXED_IE_LENGTH_);
+		if (p != NULL && tim_ielen > 0) {
+			tim_ielen += 2;
+
+			premainder_ie = p + tim_ielen;
+
+			tim_ie_offset = (sint)(p - pie);
+
+			remainder_ielen = pnetwork_mlmeext->IELength - tim_ie_offset - tim_ielen;
+
+			/*append TIM IE from dst_ie offset*/
+			dst_ie = p;
+		} else {
+			tim_ielen = 0;
+
+			/*calculate head_len*/
+			offset = _FIXED_IE_LENGTH_;
+
+			/* get ssid_ie len */
+			p = rtw_get_ie(pie + _BEACON_IE_OFFSET_, _SSID_IE_, &tmp_len, (pnetwork_mlmeext->IELength - _BEACON_IE_OFFSET_));
+			if (p != NULL)
+				offset += tmp_len + 2;
+
+			/*get supported rates len*/
+			p = rtw_get_ie(pie + _BEACON_IE_OFFSET_, _SUPPORTEDRATES_IE_, &tmp_len, (pnetwork_mlmeext->IELength - _BEACON_IE_OFFSET_));
+			if (p !=  NULL)
+				offset += tmp_len + 2;
+
+			/*DS Parameter Set IE, len=3*/
+			offset += 3;
+
+			premainder_ie = pie + offset;
+
+			remainder_ielen = pnetwork_mlmeext->IELength - offset - tim_ielen;
+
+			/*append TIM IE from offset*/
+			dst_ie = pie + offset;
+
+		}
+
+		if (remainder_ielen > 0) {
+			pbackup_remainder_ie = rtw_malloc(remainder_ielen);
+			if (pbackup_remainder_ie && premainder_ie)
+				_rtw_memcpy(pbackup_remainder_ie, premainder_ie, remainder_ielen);
+		}
+
+		/* append TIM IE */
+		dst_ie += rtw_set_tim_ie(0, 1, pstapriv->tim_bitmap, pstapriv->aid_bmp_len, dst_ie);
+
+		/*copy remainder IE*/
+		if (pbackup_remainder_ie) {
+			_rtw_memcpy(dst_ie, pbackup_remainder_ie, remainder_ielen);
+
+			rtw_mfree(pbackup_remainder_ie, remainder_ielen);
+		}
+
+		offset = (uint)(dst_ie - pie);
+		pnetwork_mlmeext->IELength = offset + remainder_ielen;
+
+	}
+}
+
+void rtw_add_bcn_ie(_adapter *padapter, WLAN_BSSID_EX *pnetwork, u8 index, u8 *data, u8 len)
+{
+	PNDIS_802_11_VARIABLE_IEs	pIE;
+	u8	bmatch = _FALSE;
+	u8	*pie = pnetwork->IEs;
+	u8	*p = NULL, *dst_ie = NULL, *premainder_ie = NULL, *pbackup_remainder_ie = NULL;
+	u32	i = 0, offset = 0, ielen = 0, ie_offset = 0, remainder_ielen = 0;
+
+	for (i = sizeof(NDIS_802_11_FIXED_IEs); i < pnetwork->IELength;) {
+		pIE = (PNDIS_802_11_VARIABLE_IEs)(pnetwork->IEs + i);
+
+		if (pIE->ElementID > index)
+			break;
+		else if (pIE->ElementID == index) { /* already exist the same IE */
+			p = (u8 *)pIE;
+			ielen = pIE->Length;
+			bmatch = _TRUE;
+			break;
+		}
+
+		p = (u8 *)pIE;
+		ielen = pIE->Length;
+		i += (pIE->Length + 2);
+	}
+
+	if (p != NULL && ielen > 0) {
+		ielen += 2;
+
+		premainder_ie = p + ielen;
+
+		ie_offset = (sint)(p - pie);
+
+		remainder_ielen = pnetwork->IELength - ie_offset - ielen;
+
+		if (bmatch)
+			dst_ie = p;
+		else
+			dst_ie = (p + ielen);
+	}
+
+	if (dst_ie == NULL)
+		return;
+
+	if (remainder_ielen > 0) {
+		pbackup_remainder_ie = rtw_malloc(remainder_ielen);
+		if (pbackup_remainder_ie && premainder_ie)
+			_rtw_memcpy(pbackup_remainder_ie, premainder_ie, remainder_ielen);
+	}
+
+	*dst_ie++ = index;
+	*dst_ie++ = len;
+
+	_rtw_memcpy(dst_ie, data, len);
+	dst_ie += len;
+
+	/* copy remainder IE */
+	if (pbackup_remainder_ie) {
+		_rtw_memcpy(dst_ie, pbackup_remainder_ie, remainder_ielen);
+
+		rtw_mfree(pbackup_remainder_ie, remainder_ielen);
+	}
+
+	offset = (uint)(dst_ie - pie);
+	pnetwork->IELength = offset + remainder_ielen;
+}
+
+void rtw_remove_bcn_ie(_adapter *padapter, WLAN_BSSID_EX *pnetwork, u8 index)
+{
+	u8 *p, *dst_ie = NULL, *premainder_ie = NULL, *pbackup_remainder_ie = NULL;
+	uint offset, ielen, ie_offset, remainder_ielen = 0;
+	u8	*pie = pnetwork->IEs;
+
+	p = rtw_get_ie(pie + _FIXED_IE_LENGTH_, index, &ielen, pnetwork->IELength - _FIXED_IE_LENGTH_);
+	if (p != NULL && ielen > 0) {
+		ielen += 2;
+
+		premainder_ie = p + ielen;
+
+		ie_offset = (sint)(p - pie);
+
+		remainder_ielen = pnetwork->IELength - ie_offset - ielen;
+
+		dst_ie = p;
+	} else
+		return;
+
+	if (remainder_ielen > 0) {
+		pbackup_remainder_ie = rtw_malloc(remainder_ielen);
+		if (pbackup_remainder_ie && premainder_ie)
+			_rtw_memcpy(pbackup_remainder_ie, premainder_ie, remainder_ielen);
+	}
+
+	/* copy remainder IE */
+	if (pbackup_remainder_ie) {
+		_rtw_memcpy(dst_ie, pbackup_remainder_ie, remainder_ielen);
+
+		rtw_mfree(pbackup_remainder_ie, remainder_ielen);
+	}
+
+	offset = (uint)(dst_ie - pie);
+	pnetwork->IELength = offset + remainder_ielen;
+}
+
+
+u8 chk_sta_is_alive(struct sta_info *psta);
+u8 chk_sta_is_alive(struct sta_info *psta)
+{
+	u8 ret = _FALSE;
+#ifdef DBG_EXPIRATION_CHK
+	RTW_INFO("sta:"MAC_FMT", rssi:%d, rx:"STA_PKTS_FMT", expire_to:%u, %s%ssq_len:%u\n"
+		 , MAC_ARG(psta->cmn.mac_addr)
+		 , psta->cmn.rssi_stat.rssi
+		 /* , STA_RX_PKTS_ARG(psta) */
+		 , STA_RX_PKTS_DIFF_ARG(psta)
+		 , psta->expire_to
+		 , psta->state & WIFI_SLEEP_STATE ? "PS, " : ""
+		 , psta->state & WIFI_STA_ALIVE_CHK_STATE ? "SAC, " : ""
+		 , psta->sleepq_len
+		);
+#endif
+
+	/* if(sta_last_rx_pkts(psta) == sta_rx_pkts(psta)) */
+	if ((psta->sta_stats.last_rx_data_pkts + psta->sta_stats.last_rx_ctrl_pkts) == (psta->sta_stats.rx_data_pkts + psta->sta_stats.rx_ctrl_pkts)) {
+#if 0
+		if (psta->state & WIFI_SLEEP_STATE)
+			ret = _TRUE;
+#endif
+#ifdef CONFIG_RTW_MESH
+		if (MLME_IS_MESH(psta->padapter) &&
+		    (psta->sta_stats.last_rx_hwmp_pkts !=
+		     psta->sta_stats.rx_hwmp_pkts))
+			ret = _TRUE;
+#endif
+	} else
+		ret = _TRUE;
+
+	sta_update_last_rx_pkts(psta);
+
+	return ret;
+}
+
+/**
+ * issue_aka_chk_frame - issue active keep alive check frame
+ *	aka = active keep alive
+ */
+static int issue_aka_chk_frame(_adapter *adapter, struct sta_info *psta)
+{
+	int ret = _FAIL;
+	u8 *target_addr = psta->cmn.mac_addr;
+
+	if (MLME_IS_AP(adapter)) {
+		/* issue null data to check sta alive */
+		if (psta->state & WIFI_SLEEP_STATE)
+			ret = issue_nulldata(adapter, target_addr, 0, 1, 50);
+		else
+			ret = issue_nulldata(adapter, target_addr, 0, 3, 50);
+	}
+
+#ifdef CONFIG_RTW_MESH
+	if (MLME_IS_MESH(adapter)) {
+		struct rtw_mesh_path *mpath;
+
+		rtw_rcu_read_lock();
+		mpath = rtw_mesh_path_lookup(adapter, target_addr);
+		if (!mpath) {
+			mpath = rtw_mesh_path_add(adapter, target_addr);
+			if (IS_ERR(mpath)) {
+				rtw_rcu_read_unlock();
+				RTW_ERR(FUNC_ADPT_FMT" rtw_mesh_path_add for "MAC_FMT" fail.\n",
+					FUNC_ADPT_ARG(adapter), MAC_ARG(target_addr));
+				return _FAIL;
+			}
+		}
+		if (mpath->flags & RTW_MESH_PATH_ACTIVE)
+			ret = _SUCCESS;
+		else {
+			u8 flags = RTW_PREQ_Q_F_START | RTW_PREQ_Q_F_PEER_AKA;
+			/* issue PREQ to check peer alive */
+			rtw_mesh_queue_preq(mpath, flags);
+			ret = _FALSE;
+		}
+		rtw_rcu_read_unlock();
+	}
+#endif
+	return ret;
+}
+
+void	expire_timeout_chk(_adapter *padapter)
+{
+	_irqL irqL;
+	_list	*phead, *plist;
+	u8 updated = _FALSE;
+	struct sta_info *psta = NULL;
+	struct sta_priv *pstapriv = &padapter->stapriv;
+	u8 chk_alive_num = 0;
+	char chk_alive_list[NUM_STA];
+	int i;
+
+#ifdef CONFIG_RTW_MESH
+	if (MLME_IS_MESH(padapter)
+		&& check_fwstate(&padapter->mlmepriv, WIFI_ASOC_STATE)
+	) {
+		struct rtw_mesh_cfg *mcfg = &padapter->mesh_cfg;
+
+		rtw_mesh_path_expire(padapter);
+
+		/* TBD: up layer timeout mechanism */
+		/* if (!mcfg->plink_timeout)
+			return; */
+#ifndef CONFIG_ACTIVE_KEEP_ALIVE_CHECK
+		return;
+#endif
+	}
+#endif
+
+#ifdef CONFIG_MCC_MODE
+	/*	then driver may check fail due to not recv client's frame under sitesurvey,
+	 *	don't expire timeout chk under MCC under sitesurvey */
+
+	if (rtw_hal_mcc_link_status_chk(padapter, __func__) == _FALSE)
+		return;
+#endif
+
+	_enter_critical_bh(&pstapriv->auth_list_lock, &irqL);
+
+	phead = &pstapriv->auth_list;
+	plist = get_next(phead);
+
+	/* check auth_queue */
+#ifdef DBG_EXPIRATION_CHK
+	if (rtw_end_of_queue_search(phead, plist) == _FALSE) {
+		RTW_INFO(FUNC_ADPT_FMT" auth_list, cnt:%u\n"
+			, FUNC_ADPT_ARG(padapter), pstapriv->auth_list_cnt);
+	}
+#endif
+	while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) {
+		psta = LIST_CONTAINOR(plist, struct sta_info, auth_list);
+
+		plist = get_next(plist);
+
+
+#ifdef CONFIG_ATMEL_RC_PATCH
+		if (_rtw_memcmp((void *)(pstapriv->atmel_rc_pattern), (void *)(psta->cmn.mac_addr), ETH_ALEN) == _TRUE)
+			continue;
+		if (psta->flag_atmel_rc)
+			continue;
+#endif
+		if (psta->expire_to > 0) {
+			psta->expire_to--;
+			if (psta->expire_to == 0) {
+				rtw_list_delete(&psta->auth_list);
+				pstapriv->auth_list_cnt--;
+
+				RTW_INFO(FUNC_ADPT_FMT" auth expire "MAC_FMT"\n"
+					, FUNC_ADPT_ARG(padapter), MAC_ARG(psta->cmn.mac_addr));
+
+				_exit_critical_bh(&pstapriv->auth_list_lock, &irqL);
+
+				/* _enter_critical_bh(&(pstapriv->sta_hash_lock), &irqL);	 */
+				rtw_free_stainfo(padapter, psta);
+				/* _exit_critical_bh(&(pstapriv->sta_hash_lock), &irqL);	 */
+
+				_enter_critical_bh(&pstapriv->auth_list_lock, &irqL);
+			}
+		}
+
+	}
+
+	_exit_critical_bh(&pstapriv->auth_list_lock, &irqL);
+	psta = NULL;
+
+
+	_enter_critical_bh(&pstapriv->asoc_list_lock, &irqL);
+
+	phead = &pstapriv->asoc_list;
+	plist = get_next(phead);
+
+	/* check asoc_queue */
+#ifdef DBG_EXPIRATION_CHK
+	if (rtw_end_of_queue_search(phead, plist) == _FALSE) {
+		RTW_INFO(FUNC_ADPT_FMT" asoc_list, cnt:%u\n"
+			, FUNC_ADPT_ARG(padapter), pstapriv->asoc_list_cnt);
+	}
+#endif
+	while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) {
+		psta = LIST_CONTAINOR(plist, struct sta_info, asoc_list);
+		plist = get_next(plist);
+#ifdef CONFIG_ATMEL_RC_PATCH
+		RTW_INFO("%s:%d  psta=%p, %02x,%02x||%02x,%02x  \n\n", __func__,  __LINE__,
+			psta, pstapriv->atmel_rc_pattern[0], pstapriv->atmel_rc_pattern[5], psta->cmn.mac_addr[0], psta->cmn.mac_addr[5]);
+		if (_rtw_memcmp((void *)pstapriv->atmel_rc_pattern, (void *)(psta->cmn.mac_addr), ETH_ALEN) == _TRUE)
+			continue;
+		if (psta->flag_atmel_rc)
+			continue;
+		RTW_INFO("%s: debug line:%d\n", __func__, __LINE__);
+#endif
+#ifdef CONFIG_AUTO_AP_MODE
+		if (psta->isrc)
+			continue;
+#endif
+		if (chk_sta_is_alive(psta) || !psta->expire_to) {
+			psta->expire_to = pstapriv->expire_to;
+			psta->keep_alive_trycnt = 0;
+#ifdef CONFIG_TX_MCAST2UNI
+			psta->under_exist_checking = 0;
+#endif	/* CONFIG_TX_MCAST2UNI */
+		} else
+			psta->expire_to--;
+
+#ifndef CONFIG_ACTIVE_KEEP_ALIVE_CHECK
+#ifdef CONFIG_80211N_HT
+#ifdef CONFIG_TX_MCAST2UNI
+		if ((psta->flags & WLAN_STA_HT) && (psta->htpriv.agg_enable_bitmap || psta->under_exist_checking)) {
+			/* check sta by delba(addba) for 11n STA */
+			/* ToDo: use CCX report to check for all STAs */
+			/* RTW_INFO("asoc check by DELBA/ADDBA! (pstapriv->expire_to=%d s)(psta->expire_to=%d s), [%02x, %d]\n", pstapriv->expire_to*2, psta->expire_to*2, psta->htpriv.agg_enable_bitmap, psta->under_exist_checking); */
+
+			if (psta->expire_to <= (pstapriv->expire_to - 50)) {
+				RTW_INFO("asoc expire by DELBA/ADDBA! (%d s)\n", (pstapriv->expire_to - psta->expire_to) * 2);
+				psta->under_exist_checking = 0;
+				psta->expire_to = 0;
+			} else if (psta->expire_to <= (pstapriv->expire_to - 3) && (psta->under_exist_checking == 0)) {
+				RTW_INFO("asoc check by DELBA/ADDBA! (%d s)\n", (pstapriv->expire_to - psta->expire_to) * 2);
+				psta->under_exist_checking = 1;
+				/* tear down TX AMPDU */
+				send_delba(padapter, 1, psta->cmn.mac_addr);/*  */ /* originator */
+				psta->htpriv.agg_enable_bitmap = 0x0;/* reset */
+				psta->htpriv.candidate_tid_bitmap = 0x0;/* reset */
+			}
+		}
+#endif /* CONFIG_TX_MCAST2UNI */
+#endif /* CONFIG_80211N_HT */
+#endif /* CONFIG_ACTIVE_KEEP_ALIVE_CHECK */
+
+		if (psta->expire_to <= 0) {
+			struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
+
+			if (padapter->registrypriv.wifi_spec == 1) {
+				psta->expire_to = pstapriv->expire_to;
+				continue;
+			}
+
+#ifndef CONFIG_ACTIVE_KEEP_ALIVE_CHECK
+#ifdef CONFIG_80211N_HT
+
+#define KEEP_ALIVE_TRYCNT (3)
+
+			if (psta->keep_alive_trycnt > 0 && psta->keep_alive_trycnt <= KEEP_ALIVE_TRYCNT) {
+				if (psta->state & WIFI_STA_ALIVE_CHK_STATE)
+					psta->state ^= WIFI_STA_ALIVE_CHK_STATE;
+				else
+					psta->keep_alive_trycnt = 0;
+
+			} else if ((psta->keep_alive_trycnt > KEEP_ALIVE_TRYCNT) && !(psta->state & WIFI_STA_ALIVE_CHK_STATE))
+				psta->keep_alive_trycnt = 0;
+			if ((psta->htpriv.ht_option == _TRUE) && (psta->htpriv.ampdu_enable == _TRUE)) {
+				uint priority = 1; /* test using BK */
+				u8 issued = 0;
+
+				/* issued = (psta->htpriv.agg_enable_bitmap>>priority)&0x1; */
+				issued |= (psta->htpriv.candidate_tid_bitmap >> priority) & 0x1;
+
+				if (0 == issued) {
+					if (!(psta->state & WIFI_STA_ALIVE_CHK_STATE)) {
+						psta->htpriv.candidate_tid_bitmap |= BIT((u8)priority);
+
+						if (psta->state & WIFI_SLEEP_STATE)
+							psta->expire_to = 2; /* 2x2=4 sec */
+						else
+							psta->expire_to = 1; /* 2 sec */
+
+						psta->state |= WIFI_STA_ALIVE_CHK_STATE;
+
+						/* add_ba_hdl(padapter, (u8*)paddbareq_parm); */
+
+						RTW_INFO("issue addba_req to check if sta alive, keep_alive_trycnt=%d\n", psta->keep_alive_trycnt);
+
+						issue_addba_req(padapter, psta->cmn.mac_addr, (u8)priority);
+
+						_set_timer(&psta->addba_retry_timer, ADDBA_TO);
+
+						psta->keep_alive_trycnt++;
+
+						continue;
+					}
+				}
+			}
+			if (psta->keep_alive_trycnt > 0 && psta->state & WIFI_STA_ALIVE_CHK_STATE) {
+				psta->keep_alive_trycnt = 0;
+				psta->state ^= WIFI_STA_ALIVE_CHK_STATE;
+				RTW_INFO("change to another methods to check alive if staion is at ps mode\n");
+			}
+
+#endif /* CONFIG_80211N_HT */
+#endif /* CONFIG_ACTIVE_KEEP_ALIVE_CHECK	 */
+			if (psta->state & WIFI_SLEEP_STATE) {
+				if (!(psta->state & WIFI_STA_ALIVE_CHK_STATE)) {
+					/* to check if alive by another methods if staion is at ps mode.					 */
+					psta->expire_to = pstapriv->expire_to;
+					psta->state |= WIFI_STA_ALIVE_CHK_STATE;
+
+					/* RTW_INFO("alive chk, sta:" MAC_FMT " is at ps mode!\n", MAC_ARG(psta->cmn.mac_addr)); */
+
+					/* to update bcn with tim_bitmap for this station */
+					rtw_tim_map_set(padapter, pstapriv->tim_bitmap, psta->cmn.aid);
+					update_beacon(padapter, _TIM_IE_, NULL, _TRUE);
+
+					if (!pmlmeext->active_keep_alive_check)
+						continue;
+				}
+			}
+
+			{
+				int stainfo_offset;
+
+				stainfo_offset = rtw_stainfo_offset(pstapriv, psta);
+				if (stainfo_offset_valid(stainfo_offset))
+					chk_alive_list[chk_alive_num++] = stainfo_offset;
+				continue;
+			}
+		} else {
+			/* TODO: Aging mechanism to digest frames in sleep_q to avoid running out of xmitframe */
+			if (psta->sleepq_len > (NR_XMITFRAME / pstapriv->asoc_list_cnt)
+			    && padapter->xmitpriv.free_xmitframe_cnt < ((NR_XMITFRAME / pstapriv->asoc_list_cnt) / 2)
+			   ) {
+				RTW_INFO(FUNC_ADPT_FMT" sta:"MAC_FMT", sleepq_len:%u, free_xmitframe_cnt:%u, asoc_list_cnt:%u, clear sleep_q\n"
+					, FUNC_ADPT_ARG(padapter), MAC_ARG(psta->cmn.mac_addr)
+					, psta->sleepq_len, padapter->xmitpriv.free_xmitframe_cnt, pstapriv->asoc_list_cnt);
+				wakeup_sta_to_xmit(padapter, psta);
+			}
+		}
+	}
+
+	_exit_critical_bh(&pstapriv->asoc_list_lock, &irqL);
+
+	if (chk_alive_num) {
+#if defined(CONFIG_ACTIVE_KEEP_ALIVE_CHECK)
+		u8 backup_ch = 0, backup_bw = 0, backup_offset = 0;
+		u8 union_ch = 0, union_bw = 0, union_offset = 0;
+		u8 switch_channel_by_drv = _TRUE;
+		struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
+#endif
+		char del_asoc_list[NUM_STA];
+
+		_rtw_memset(del_asoc_list, NUM_STA, NUM_STA);
+
+		#ifdef CONFIG_ACTIVE_KEEP_ALIVE_CHECK
+		if (pmlmeext->active_keep_alive_check) {
+			#ifdef CONFIG_MCC_MODE
+			if (MCC_EN(padapter)) {
+				/* driver doesn't switch channel under MCC */
+				if (rtw_hal_check_mcc_status(padapter, MCC_STATUS_DOING_MCC))
+					switch_channel_by_drv = _FALSE;
+			}
+			#endif
+
+			if (!rtw_mi_get_ch_setting_union(padapter, &union_ch, &union_bw, &union_offset)
+				|| pmlmeext->cur_channel != union_ch)
+				switch_channel_by_drv = _FALSE;
+
+			/* switch to correct channel of current network  before issue keep-alive frames */
+			if (switch_channel_by_drv == _TRUE && rtw_get_oper_ch(padapter) != pmlmeext->cur_channel) {
+				backup_ch = rtw_get_oper_ch(padapter);
+				backup_bw = rtw_get_oper_bw(padapter);
+				backup_offset = rtw_get_oper_choffset(padapter);
+				set_channel_bwmode(padapter, union_ch, union_offset, union_bw);
+			}
+		}
+		#endif /* CONFIG_ACTIVE_KEEP_ALIVE_CHECK */
+
+		/* check loop */
+		for (i = 0; i < chk_alive_num; i++) {
+			#ifdef CONFIG_ACTIVE_KEEP_ALIVE_CHECK
+			int ret = _FAIL;
+			#endif
+
+			psta = rtw_get_stainfo_by_offset(pstapriv, chk_alive_list[i]);
+
+			#ifdef CONFIG_ATMEL_RC_PATCH
+			if (_rtw_memcmp(pstapriv->atmel_rc_pattern, psta->cmn.mac_addr, ETH_ALEN) == _TRUE)
+				continue;
+			if (psta->flag_atmel_rc)
+				continue;
+			#endif
+
+			if (!(psta->state & _FW_LINKED))
+				continue;
+
+			#ifdef CONFIG_ACTIVE_KEEP_ALIVE_CHECK
+			if (pmlmeext->active_keep_alive_check) {
+				/* issue active keep alive frame to check */
+				ret = issue_aka_chk_frame(padapter, psta);
+
+				psta->keep_alive_trycnt++;
+				if (ret == _SUCCESS) {
+					RTW_INFO(FUNC_ADPT_FMT" asoc check, "MAC_FMT" is alive\n"
+						, FUNC_ADPT_ARG(padapter), MAC_ARG(psta->cmn.mac_addr));
+					psta->expire_to = pstapriv->expire_to;
+					psta->keep_alive_trycnt = 0;
+					continue;
+				} else if (psta->keep_alive_trycnt <= 3) {
+					RTW_INFO(FUNC_ADPT_FMT" asoc check, "MAC_FMT" keep_alive_trycnt=%d\n"
+						, FUNC_ADPT_ARG(padapter) , MAC_ARG(psta->cmn.mac_addr), psta->keep_alive_trycnt);
+					psta->expire_to = 1;
+					continue;
+				}
+			}
+			#endif /* CONFIG_ACTIVE_KEEP_ALIVE_CHECK */
+
+			psta->keep_alive_trycnt = 0;
+			del_asoc_list[i] = chk_alive_list[i];
+			_enter_critical_bh(&pstapriv->asoc_list_lock, &irqL);
+			if (rtw_is_list_empty(&psta->asoc_list) == _FALSE) {
+				rtw_list_delete(&psta->asoc_list);
+				pstapriv->asoc_list_cnt--;
+				STA_SET_MESH_PLINK(psta, NULL);
+			}
+			_exit_critical_bh(&pstapriv->asoc_list_lock, &irqL);
+		}
+
+		/* delete loop */
+		for (i = 0; i < chk_alive_num; i++) {
+			u8 sta_addr[ETH_ALEN];
+
+			if (del_asoc_list[i] >= NUM_STA)
+				continue;
+
+			psta = rtw_get_stainfo_by_offset(pstapriv, del_asoc_list[i]);
+			_rtw_memcpy(sta_addr, psta->cmn.mac_addr, ETH_ALEN);
+
+			RTW_INFO(FUNC_ADPT_FMT" asoc expire "MAC_FMT", state=0x%x\n"
+				, FUNC_ADPT_ARG(padapter), MAC_ARG(psta->cmn.mac_addr), psta->state);
+			updated |= ap_free_sta(padapter, psta, _FALSE, WLAN_REASON_DEAUTH_LEAVING, _FALSE);
+			#ifdef CONFIG_RTW_MESH
+			if (MLME_IS_MESH(padapter))
+				rtw_mesh_expire_peer(padapter, sta_addr);
+			#endif
+		}
+
+		#ifdef CONFIG_ACTIVE_KEEP_ALIVE_CHECK
+		if (pmlmeext->active_keep_alive_check) {
+			/* back to the original operation channel */
+			if (switch_channel_by_drv == _TRUE && backup_ch > 0)
+				set_channel_bwmode(padapter, backup_ch, backup_offset, backup_bw);
+		}
+		#endif
+	}
+
+	associated_clients_update(padapter, updated, STA_INFO_UPDATE_ALL);
+}
+
+void rtw_ap_update_sta_ra_info(_adapter *padapter, struct sta_info *psta)
+{
+	unsigned char sta_band = 0;
+	u64 tx_ra_bitmap = 0;
+	struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
+	WLAN_BSSID_EX *pcur_network = (WLAN_BSSID_EX *)&pmlmepriv->cur_network.network;
+
+	if (!psta)
+		return;
+
+	if (!(psta->state & _FW_LINKED))
+		return;
+
+	rtw_hal_update_sta_ra_info(padapter, psta);
+	tx_ra_bitmap = psta->cmn.ra_info.ramask;
+
+	if (pcur_network->Configuration.DSConfig > 14) {
+
+		if (tx_ra_bitmap & 0xffff000)
+			sta_band |= WIRELESS_11_5N;
+
+		if (tx_ra_bitmap & 0xff0)
+			sta_band |= WIRELESS_11A;
+
+		/* 5G band */
+#ifdef CONFIG_80211AC_VHT
+		if (psta->vhtpriv.vht_option)
+			sta_band = WIRELESS_11_5AC;
+#endif
+	} else {
+		if (tx_ra_bitmap & 0xffff000)
+			sta_band |= WIRELESS_11_24N;
+
+		if (tx_ra_bitmap & 0xff0)
+			sta_band |= WIRELESS_11G;
+
+		if (tx_ra_bitmap & 0x0f)
+			sta_band |= WIRELESS_11B;
+	}
+
+	psta->wireless_mode = sta_band;
+	rtw_hal_update_sta_wset(padapter, psta);
+	RTW_INFO("%s=> mac_id:%d , tx_ra_bitmap:0x%016llx, networkType:0x%02x\n",
+			__FUNCTION__, psta->cmn.mac_id, tx_ra_bitmap, psta->wireless_mode);
+}
+
+#ifdef CONFIG_BMC_TX_RATE_SELECT
+u8 rtw_ap_find_mini_tx_rate(_adapter *adapter)
+{
+	_irqL irqL;
+	_list	*phead, *plist;
+	u8 miini_tx_rate = ODM_RATEVHTSS4MCS9, sta_tx_rate;
+	struct sta_info *psta = NULL;
+	struct sta_priv *pstapriv = &adapter->stapriv;
+
+	_enter_critical_bh(&pstapriv->asoc_list_lock, &irqL);
+	phead = &pstapriv->asoc_list;
+	plist = get_next(phead);
+	while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) {
+		psta = LIST_CONTAINOR(plist, struct sta_info, asoc_list);
+		plist = get_next(plist);
+
+		sta_tx_rate = psta->cmn.ra_info.curr_tx_rate & 0x7F;
+		if (sta_tx_rate < miini_tx_rate)
+			miini_tx_rate = sta_tx_rate;
+	}
+	_exit_critical_bh(&pstapriv->asoc_list_lock, &irqL);
+
+	return miini_tx_rate;
+}
+
+u8 rtw_ap_find_bmc_rate(_adapter *adapter, u8 tx_rate)
+{
+	PHAL_DATA_TYPE	hal_data = GET_HAL_DATA(adapter);
+	u8 tx_ini_rate = ODM_RATE6M;
+
+	switch (tx_rate) {
+	case ODM_RATEVHTSS3MCS9:
+	case ODM_RATEVHTSS3MCS8:
+	case ODM_RATEVHTSS3MCS7:
+	case ODM_RATEVHTSS3MCS6:
+	case ODM_RATEVHTSS3MCS5:
+	case ODM_RATEVHTSS3MCS4:
+	case ODM_RATEVHTSS3MCS3:
+	case ODM_RATEVHTSS2MCS9:
+	case ODM_RATEVHTSS2MCS8:
+	case ODM_RATEVHTSS2MCS7:
+	case ODM_RATEVHTSS2MCS6:
+	case ODM_RATEVHTSS2MCS5:
+	case ODM_RATEVHTSS2MCS4:
+	case ODM_RATEVHTSS2MCS3:
+	case ODM_RATEVHTSS1MCS9:
+	case ODM_RATEVHTSS1MCS8:
+	case ODM_RATEVHTSS1MCS7:
+	case ODM_RATEVHTSS1MCS6:
+	case ODM_RATEVHTSS1MCS5:
+	case ODM_RATEVHTSS1MCS4:
+	case ODM_RATEVHTSS1MCS3:
+	case ODM_RATEMCS15:
+	case ODM_RATEMCS14:
+	case ODM_RATEMCS13:
+	case ODM_RATEMCS12:
+	case ODM_RATEMCS11:
+	case ODM_RATEMCS7:
+	case ODM_RATEMCS6:
+	case ODM_RATEMCS5:
+	case ODM_RATEMCS4:
+	case ODM_RATEMCS3:
+	case ODM_RATE54M:
+	case ODM_RATE48M:
+	case ODM_RATE36M:
+	case ODM_RATE24M:
+		tx_ini_rate = ODM_RATE24M;
+		break;
+	case ODM_RATEVHTSS3MCS2:
+	case ODM_RATEVHTSS3MCS1:
+	case ODM_RATEVHTSS2MCS2:
+	case ODM_RATEVHTSS2MCS1:
+	case ODM_RATEVHTSS1MCS2:
+	case ODM_RATEVHTSS1MCS1:
+	case ODM_RATEMCS10:
+	case ODM_RATEMCS9:
+	case ODM_RATEMCS2:
+	case ODM_RATEMCS1:
+	case ODM_RATE18M:
+	case ODM_RATE12M:
+		tx_ini_rate = ODM_RATE12M;
+		break;
+	case ODM_RATEVHTSS3MCS0:
+	case ODM_RATEVHTSS2MCS0:
+	case ODM_RATEVHTSS1MCS0:
+	case ODM_RATEMCS8:
+	case ODM_RATEMCS0:
+	case ODM_RATE9M:
+	case ODM_RATE6M:
+		tx_ini_rate = ODM_RATE6M;
+		break;
+	case ODM_RATE11M:
+	case ODM_RATE5_5M:
+	case ODM_RATE2M:
+	case ODM_RATE1M:
+		tx_ini_rate = ODM_RATE1M;
+		break;
+	default:
+		tx_ini_rate = ODM_RATE6M;
+		break;
+	}
+
+	if (hal_data->current_band_type == BAND_ON_5G)
+		if (tx_ini_rate < ODM_RATE6M)
+			tx_ini_rate = ODM_RATE6M;
+
+	return tx_ini_rate;
+}
+
+void rtw_update_bmc_sta_tx_rate(_adapter *adapter)
+{
+	struct sta_info *psta = NULL;
+	u8 tx_rate;
+
+	psta = rtw_get_bcmc_stainfo(adapter);
+	if (psta == NULL) {
+		RTW_ERR(ADPT_FMT "could not get bmc_sta !!\n", ADPT_ARG(adapter));
+		return;
+	}
+
+	if (adapter->bmc_tx_rate != MGN_UNKNOWN) {
+		psta->init_rate = adapter->bmc_tx_rate;
+		goto _exit;
+	}
+
+	if (adapter->stapriv.asoc_sta_count <= 2)
+		goto _exit;
+
+	tx_rate = rtw_ap_find_mini_tx_rate(adapter);
+	#ifdef CONFIG_BMC_TX_LOW_RATE
+	tx_rate = rtw_ap_find_bmc_rate(adapter, tx_rate);
+	#endif
+
+	psta->init_rate = hw_rate_to_m_rate(tx_rate);
+
+_exit:
+	RTW_INFO(ADPT_FMT" BMC Tx rate - %s\n", ADPT_ARG(adapter), MGN_RATE_STR(psta->init_rate));
+}
+#endif
+
+void rtw_init_bmc_sta_tx_rate(_adapter *padapter, struct sta_info *psta)
+{
+#ifdef CONFIG_BMC_TX_LOW_RATE
+	struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv);
+#endif
+	u8 rate_idx = 0;
+	u8 brate_table[] = {MGN_1M, MGN_2M, MGN_5_5M, MGN_11M,
+		MGN_6M, MGN_9M, MGN_12M, MGN_18M, MGN_24M, MGN_36M, MGN_48M, MGN_54M};
+
+	if (!MLME_IS_AP(padapter) && !MLME_IS_MESH(padapter))
+		return;
+
+	if (padapter->bmc_tx_rate != MGN_UNKNOWN)
+		psta->init_rate = padapter->bmc_tx_rate;
+	else {
+		#ifdef CONFIG_BMC_TX_LOW_RATE
+		if (IsEnableHWOFDM(pmlmeext->cur_wireless_mode) && (psta->cmn.ra_info.ramask && 0xFF0))
+			rate_idx = get_lowest_rate_idx_ex(psta->cmn.ra_info.ramask, 4); /*from basic rate*/
+		else
+			rate_idx = get_lowest_rate_idx(psta->cmn.ra_info.ramask); /*from basic rate*/
+		#else
+		rate_idx = get_highest_rate_idx(psta->cmn.ra_info.ramask); /*from basic rate*/
+		#endif
+		if (rate_idx < 12)
+			psta->init_rate = brate_table[rate_idx];
+		else
+			psta->init_rate = MGN_1M;
+	}
+
+	RTW_INFO(ADPT_FMT" BMC Init Tx rate - %s\n", ADPT_ARG(padapter), MGN_RATE_STR(psta->init_rate));
+}
+
+void update_bmc_sta(_adapter *padapter)
+{
+	_irqL	irqL;
+	unsigned char	network_type;
+	int supportRateNum = 0;
+	struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
+	WLAN_BSSID_EX *pcur_network = (WLAN_BSSID_EX *)&pmlmepriv->cur_network.network;
+	struct sta_info *psta = rtw_get_bcmc_stainfo(padapter);
+
+	if (psta) {
+		psta->cmn.aid = 0;/* default set to 0 */
+#ifdef CONFIG_RTW_MESH
+		if (MLME_IS_MESH(padapter))
+			psta->qos_option = 1;
+		else
+#endif
+			psta->qos_option = 0;
+#ifdef CONFIG_80211N_HT
+		psta->htpriv.ht_option = _FALSE;
+#endif /* CONFIG_80211N_HT */
+
+		psta->ieee8021x_blocked = 0;
+
+		_rtw_memset((void *)&psta->sta_stats, 0, sizeof(struct stainfo_stats));
+
+		/* psta->dot118021XPrivacy = _NO_PRIVACY_; */ /* !!! remove it, because it has been set before this. */
+
+		supportRateNum = rtw_get_rateset_len((u8 *)&pcur_network->SupportedRates);
+		network_type = rtw_check_network_type((u8 *)&pcur_network->SupportedRates, supportRateNum, pcur_network->Configuration.DSConfig);
+		if (IsSupportedTxCCK(network_type))
+			network_type = WIRELESS_11B;
+		else if (network_type == WIRELESS_INVALID) { /* error handling */
+			if (pcur_network->Configuration.DSConfig > 14)
+				network_type = WIRELESS_11A;
+			else
+				network_type = WIRELESS_11B;
+		}
+		update_sta_basic_rate(psta, network_type);
+		psta->wireless_mode = network_type;
+
+		rtw_hal_update_sta_ra_info(padapter, psta);
+
+		_enter_critical_bh(&psta->lock, &irqL);
+		psta->state = _FW_LINKED;
+		_exit_critical_bh(&psta->lock, &irqL);
+
+		rtw_sta_media_status_rpt(padapter, psta, 1);
+		rtw_init_bmc_sta_tx_rate(padapter, psta);
+
+	} else
+		RTW_INFO("add_RATid_bmc_sta error!\n");
+
+}
+
+#if defined(CONFIG_80211N_HT) && defined(CONFIG_BEAMFORMING)
+void update_sta_info_apmode_ht_bf_cap(_adapter *padapter, struct sta_info *psta)
+{
+	struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
+	struct ht_priv	*phtpriv_ap = &pmlmepriv->htpriv;
+	struct ht_priv	*phtpriv_sta = &psta->htpriv;
+
+	u8 cur_beamform_cap = 0;
+
+	/*Config Tx beamforming setting*/
+	if (TEST_FLAG(phtpriv_ap->beamform_cap, BEAMFORMING_HT_BEAMFORMEE_ENABLE) &&
+		GET_HT_CAP_TXBF_EXPLICIT_COMP_STEERING_CAP((u8 *)(&phtpriv_sta->ht_cap))) {
+		SET_FLAG(cur_beamform_cap, BEAMFORMING_HT_BEAMFORMER_ENABLE);
+		/*Shift to BEAMFORMING_HT_BEAMFORMEE_CHNL_EST_CAP*/
+		SET_FLAG(cur_beamform_cap, GET_HT_CAP_TXBF_CHNL_ESTIMATION_NUM_ANTENNAS((u8 *)(&phtpriv_sta->ht_cap)) << 6);
+	}
+
+	if (TEST_FLAG(phtpriv_ap->beamform_cap, BEAMFORMING_HT_BEAMFORMER_ENABLE) &&
+		GET_HT_CAP_TXBF_EXPLICIT_COMP_FEEDBACK_CAP((u8 *)(&phtpriv_sta->ht_cap))) {
+		SET_FLAG(cur_beamform_cap, BEAMFORMING_HT_BEAMFORMEE_ENABLE);
+		/*Shift to BEAMFORMING_HT_BEAMFORMER_STEER_NUM*/
+		SET_FLAG(cur_beamform_cap, GET_HT_CAP_TXBF_COMP_STEERING_NUM_ANTENNAS((u8 *)(&phtpriv_sta->ht_cap)) << 4);
+	}
+	if (cur_beamform_cap)
+		RTW_INFO("Client STA(%d) HT Beamforming Cap = 0x%02X\n", psta->cmn.aid, cur_beamform_cap);
+
+	phtpriv_sta->beamform_cap = cur_beamform_cap;
+	psta->cmn.bf_info.ht_beamform_cap = cur_beamform_cap;
+
+}
+#endif /*CONFIG_80211N_HT && CONFIG_BEAMFORMING*/
+
+/* notes:
+ * AID: 1~MAX for sta and 0 for bc/mc in ap/adhoc mode  */
+void update_sta_info_apmode(_adapter *padapter, struct sta_info *psta)
+{
+	_irqL	irqL;
+	struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
+	struct security_priv *psecuritypriv = &padapter->securitypriv;
+	struct mlme_ext_priv	*pmlmeext = &(padapter->mlmeextpriv);
+#ifdef CONFIG_80211N_HT
+	struct ht_priv	*phtpriv_ap = &pmlmepriv->htpriv;
+	struct ht_priv	*phtpriv_sta = &psta->htpriv;
+#endif /* CONFIG_80211N_HT */
+	u8	cur_ldpc_cap = 0, cur_stbc_cap = 0;
+	/* set intf_tag to if1 */
+	/* psta->intf_tag = 0; */
+
+	RTW_INFO("%s\n", __FUNCTION__);
+
+	/*alloc macid when call rtw_alloc_stainfo(),release macid when call rtw_free_stainfo()*/
+
+	if (!MLME_IS_MESH(padapter) && psecuritypriv->dot11AuthAlgrthm == dot11AuthAlgrthm_8021X)
+		psta->ieee8021x_blocked = _TRUE;
+	else
+		psta->ieee8021x_blocked = _FALSE;
+
+
+	/* update sta's cap */
+
+	/* ERP */
+	VCS_update(padapter, psta);
+#ifdef CONFIG_80211N_HT
+	/* HT related cap */
+	if (phtpriv_sta->ht_option) {
+		/* check if sta supports rx ampdu */
+		phtpriv_sta->ampdu_enable = phtpriv_ap->ampdu_enable;
+
+		phtpriv_sta->rx_ampdu_min_spacing = (phtpriv_sta->ht_cap.ampdu_params_info & IEEE80211_HT_CAP_AMPDU_DENSITY) >> 2;
+
+		/* bwmode */
+		if ((phtpriv_sta->ht_cap.cap_info & phtpriv_ap->ht_cap.cap_info) & cpu_to_le16(IEEE80211_HT_CAP_SUP_WIDTH))
+			psta->cmn.bw_mode = CHANNEL_WIDTH_40;
+		else
+			psta->cmn.bw_mode = CHANNEL_WIDTH_20;
+
+		if (phtpriv_sta->op_present
+			&& !GET_HT_OP_ELE_STA_CHL_WIDTH(phtpriv_sta->ht_op))
+			psta->cmn.bw_mode = CHANNEL_WIDTH_20;
+
+		if (psta->ht_40mhz_intolerant)
+			psta->cmn.bw_mode = CHANNEL_WIDTH_20;
+
+		if (pmlmeext->cur_bwmode < psta->cmn.bw_mode)
+			psta->cmn.bw_mode = pmlmeext->cur_bwmode;
+
+		phtpriv_sta->ch_offset = pmlmeext->cur_ch_offset;
+
+
+		/* check if sta support s Short GI 20M */
+		if ((phtpriv_sta->ht_cap.cap_info & phtpriv_ap->ht_cap.cap_info) & cpu_to_le16(IEEE80211_HT_CAP_SGI_20))
+			phtpriv_sta->sgi_20m = _TRUE;
+
+		/* check if sta support s Short GI 40M */
+		if ((phtpriv_sta->ht_cap.cap_info & phtpriv_ap->ht_cap.cap_info) & cpu_to_le16(IEEE80211_HT_CAP_SGI_40)) {
+			if (psta->cmn.bw_mode == CHANNEL_WIDTH_40) /* according to psta->bw_mode */
+				phtpriv_sta->sgi_40m = _TRUE;
+			else
+				phtpriv_sta->sgi_40m = _FALSE;
+		}
+
+		psta->qos_option = _TRUE;
+
+		/* B0 Config LDPC Coding Capability */
+		if (TEST_FLAG(phtpriv_ap->ldpc_cap, LDPC_HT_ENABLE_TX) &&
+		    GET_HT_CAP_ELE_LDPC_CAP((u8 *)(&phtpriv_sta->ht_cap))) {
+			SET_FLAG(cur_ldpc_cap, (LDPC_HT_ENABLE_TX | LDPC_HT_CAP_TX));
+			RTW_INFO("Enable HT Tx LDPC for STA(%d)\n", psta->cmn.aid);
+		}
+
+		/* B7 B8 B9 Config STBC setting */
+		if (TEST_FLAG(phtpriv_ap->stbc_cap, STBC_HT_ENABLE_TX) &&
+		    GET_HT_CAP_ELE_RX_STBC((u8 *)(&phtpriv_sta->ht_cap))) {
+			SET_FLAG(cur_stbc_cap, (STBC_HT_ENABLE_TX | STBC_HT_CAP_TX));
+			RTW_INFO("Enable HT Tx STBC for STA(%d)\n", psta->cmn.aid);
+		}
+
+		#ifdef CONFIG_BEAMFORMING
+		update_sta_info_apmode_ht_bf_cap(padapter, psta);
+		#endif
+	} else {
+		phtpriv_sta->ampdu_enable = _FALSE;
+
+		phtpriv_sta->sgi_20m = _FALSE;
+		phtpriv_sta->sgi_40m = _FALSE;
+		psta->cmn.bw_mode = CHANNEL_WIDTH_20;
+		phtpriv_sta->ch_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
+	}
+
+	phtpriv_sta->ldpc_cap = cur_ldpc_cap;
+	phtpriv_sta->stbc_cap = cur_stbc_cap;
+
+	/* Rx AMPDU */
+	send_delba(padapter, 0, psta->cmn.mac_addr);/* recipient */
+
+	/* TX AMPDU */
+	send_delba(padapter, 1, psta->cmn.mac_addr);/*  */ /* originator */
+	phtpriv_sta->agg_enable_bitmap = 0x0;/* reset */
+	phtpriv_sta->candidate_tid_bitmap = 0x0;/* reset */
+#endif /* CONFIG_80211N_HT */
+
+#ifdef CONFIG_80211AC_VHT
+	update_sta_vht_info_apmode(padapter, psta);
+#endif
+	psta->cmn.ra_info.is_support_sgi = query_ra_short_GI(psta, rtw_get_tx_bw_mode(padapter, psta));
+	update_ldpc_stbc_cap(psta);
+
+	/* todo: init other variables */
+
+	_rtw_memset((void *)&psta->sta_stats, 0, sizeof(struct stainfo_stats));
+
+
+	/* add ratid */
+	/* add_RATid(padapter, psta); */ /* move to ap_sta_info_defer_update() */
+
+	/* ap mode */
+	rtw_hal_set_odm_var(padapter, HAL_ODM_STA_INFO, psta, _TRUE);
+
+	_enter_critical_bh(&psta->lock, &irqL);
+
+	/* Check encryption */
+	if (!MLME_IS_MESH(padapter) && psecuritypriv->dot11AuthAlgrthm == dot11AuthAlgrthm_8021X)
+		psta->state |= WIFI_UNDER_KEY_HANDSHAKE;
+
+	psta->state |= _FW_LINKED;
+
+	_exit_critical_bh(&psta->lock, &irqL);
+}
+
+static void update_ap_info(_adapter *padapter, struct sta_info *psta)
+{
+	struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
+	WLAN_BSSID_EX *pnetwork = (WLAN_BSSID_EX *)&pmlmepriv->cur_network.network;
+	struct mlme_ext_priv	*pmlmeext = &(padapter->mlmeextpriv);
+#ifdef CONFIG_80211N_HT
+	struct ht_priv	*phtpriv_ap = &pmlmepriv->htpriv;
+#endif /* CONFIG_80211N_HT */
+
+	psta->wireless_mode = pmlmeext->cur_wireless_mode;
+
+	psta->bssratelen = rtw_get_rateset_len(pnetwork->SupportedRates);
+	_rtw_memcpy(psta->bssrateset, pnetwork->SupportedRates, psta->bssratelen);
+
+#ifdef CONFIG_80211N_HT
+	/* HT related cap */
+	if (phtpriv_ap->ht_option) {
+		/* check if sta supports rx ampdu */
+		/* phtpriv_ap->ampdu_enable = phtpriv_ap->ampdu_enable; */
+
+		/* check if sta support s Short GI 20M */
+		if ((phtpriv_ap->ht_cap.cap_info) & cpu_to_le16(IEEE80211_HT_CAP_SGI_20))
+			phtpriv_ap->sgi_20m = _TRUE;
+		/* check if sta support s Short GI 40M */
+		if ((phtpriv_ap->ht_cap.cap_info) & cpu_to_le16(IEEE80211_HT_CAP_SGI_40))
+			phtpriv_ap->sgi_40m = _TRUE;
+
+		psta->qos_option = _TRUE;
+	} else {
+		phtpriv_ap->ampdu_enable = _FALSE;
+
+		phtpriv_ap->sgi_20m = _FALSE;
+		phtpriv_ap->sgi_40m = _FALSE;
+	}
+
+	psta->cmn.bw_mode = pmlmeext->cur_bwmode;
+	phtpriv_ap->ch_offset = pmlmeext->cur_ch_offset;
+
+	phtpriv_ap->agg_enable_bitmap = 0x0;/* reset */
+	phtpriv_ap->candidate_tid_bitmap = 0x0;/* reset */
+
+	_rtw_memcpy(&psta->htpriv, &pmlmepriv->htpriv, sizeof(struct ht_priv));
+
+#ifdef CONFIG_80211AC_VHT
+	_rtw_memcpy(&psta->vhtpriv, &pmlmepriv->vhtpriv, sizeof(struct vht_priv));
+#endif /* CONFIG_80211AC_VHT */
+
+#endif /* CONFIG_80211N_HT */
+
+	psta->state |= WIFI_AP_STATE; /* Aries, add,fix bug of flush_cam_entry at STOP AP mode , 0724 */
+}
+
+static void rtw_set_hw_wmm_param(_adapter *padapter)
+{
+	u8	AIFS, ECWMin, ECWMax, aSifsTime;
+	u8	acm_mask;
+	u16	TXOP;
+	u32	acParm, i;
+	u32	edca[4], inx[4];
+	struct mlme_ext_priv	*pmlmeext = &padapter->mlmeextpriv;
+	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
+	struct xmit_priv		*pxmitpriv = &padapter->xmitpriv;
+	struct registry_priv	*pregpriv = &padapter->registrypriv;
+
+	acm_mask = 0;
+#ifdef CONFIG_80211N_HT
+	if (pregpriv->ht_enable &&
+		(is_supported_5g(pmlmeext->cur_wireless_mode) ||
+	    (pmlmeext->cur_wireless_mode & WIRELESS_11_24N)))
+		aSifsTime = 16;
+	else
+#endif /* CONFIG_80211N_HT */
+		aSifsTime = 10;
+
+	if (pmlmeinfo->WMM_enable == 0) {
+		padapter->mlmepriv.acm_mask = 0;
+
+		AIFS = aSifsTime + (2 * pmlmeinfo->slotTime);
+
+		if (pmlmeext->cur_wireless_mode & (WIRELESS_11G | WIRELESS_11A)) {
+			ECWMin = 4;
+			ECWMax = 10;
+		} else if (pmlmeext->cur_wireless_mode & WIRELESS_11B) {
+			ECWMin = 5;
+			ECWMax = 10;
+		} else {
+			ECWMin = 4;
+			ECWMax = 10;
+		}
+
+		TXOP = 0;
+		acParm = AIFS | (ECWMin << 8) | (ECWMax << 12) | (TXOP << 16);
+		rtw_hal_set_hwreg(padapter, HW_VAR_AC_PARAM_BE, (u8 *)(&acParm));
+		rtw_hal_set_hwreg(padapter, HW_VAR_AC_PARAM_BK, (u8 *)(&acParm));
+		rtw_hal_set_hwreg(padapter, HW_VAR_AC_PARAM_VI, (u8 *)(&acParm));
+
+		ECWMin = 2;
+		ECWMax = 3;
+		TXOP = 0x2f;
+		acParm = AIFS | (ECWMin << 8) | (ECWMax << 12) | (TXOP << 16);
+		rtw_hal_set_hwreg(padapter, HW_VAR_AC_PARAM_VO, (u8 *)(&acParm));
+
+	} else {
+		edca[0] = edca[1] = edca[2] = edca[3] = 0;
+
+		/*TODO:*/
+		acm_mask = 0;
+		padapter->mlmepriv.acm_mask = acm_mask;
+
+#if 0
+		/* BK */
+		/* AIFS = AIFSN * slot time + SIFS - r2t phy delay */
+#endif
+		AIFS = (7 * pmlmeinfo->slotTime) + aSifsTime;
+		ECWMin = 4;
+		ECWMax = 10;
+		TXOP = 0;
+		acParm = AIFS | (ECWMin << 8) | (ECWMax << 12) | (TXOP << 16);
+		rtw_hal_set_hwreg(padapter, HW_VAR_AC_PARAM_BK, (u8 *)(&acParm));
+		edca[XMIT_BK_QUEUE] = acParm;
+		RTW_INFO("WMM(BK): %x\n", acParm);
+
+		/* BE */
+		AIFS = (3 * pmlmeinfo->slotTime) + aSifsTime;
+		ECWMin = 4;
+		ECWMax = 6;
+		TXOP = 0;
+		acParm = AIFS | (ECWMin << 8) | (ECWMax << 12) | (TXOP << 16);
+		rtw_hal_set_hwreg(padapter, HW_VAR_AC_PARAM_BE, (u8 *)(&acParm));
+		edca[XMIT_BE_QUEUE] = acParm;
+		RTW_INFO("WMM(BE): %x\n", acParm);
+
+		/* VI */
+		AIFS = (1 * pmlmeinfo->slotTime) + aSifsTime;
+		ECWMin = 3;
+		ECWMax = 4;
+		TXOP = 94;
+		acParm = AIFS | (ECWMin << 8) | (ECWMax << 12) | (TXOP << 16);
+		rtw_hal_set_hwreg(padapter, HW_VAR_AC_PARAM_VI, (u8 *)(&acParm));
+		edca[XMIT_VI_QUEUE] = acParm;
+		RTW_INFO("WMM(VI): %x\n", acParm);
+
+		/* VO */
+		AIFS = (1 * pmlmeinfo->slotTime) + aSifsTime;
+		ECWMin = 2;
+		ECWMax = 3;
+		TXOP = 47;
+		acParm = AIFS | (ECWMin << 8) | (ECWMax << 12) | (TXOP << 16);
+		rtw_hal_set_hwreg(padapter, HW_VAR_AC_PARAM_VO, (u8 *)(&acParm));
+		edca[XMIT_VO_QUEUE] = acParm;
+		RTW_INFO("WMM(VO): %x\n", acParm);
+
+
+		if (padapter->registrypriv.acm_method == 1)
+			rtw_hal_set_hwreg(padapter, HW_VAR_ACM_CTRL, (u8 *)(&acm_mask));
+		else
+			padapter->mlmepriv.acm_mask = acm_mask;
+
+		inx[0] = 0;
+		inx[1] = 1;
+		inx[2] = 2;
+		inx[3] = 3;
+
+		if (pregpriv->wifi_spec == 1) {
+			u32	j, tmp, change_inx = _FALSE;
+
+			/* entry indx: 0->vo, 1->vi, 2->be, 3->bk. */
+			for (i = 0 ; i < 4 ; i++) {
+				for (j = i + 1 ; j < 4 ; j++) {
+					/* compare CW and AIFS */
+					if ((edca[j] & 0xFFFF) < (edca[i] & 0xFFFF))
+						change_inx = _TRUE;
+					else if ((edca[j] & 0xFFFF) == (edca[i] & 0xFFFF)) {
+						/* compare TXOP */
+						if ((edca[j] >> 16) > (edca[i] >> 16))
+							change_inx = _TRUE;
+					}
+
+					if (change_inx) {
+						tmp = edca[i];
+						edca[i] = edca[j];
+						edca[j] = tmp;
+
+						tmp = inx[i];
+						inx[i] = inx[j];
+						inx[j] = tmp;
+
+						change_inx = _FALSE;
+					}
+				}
+			}
+		}
+
+		for (i = 0 ; i < 4 ; i++) {
+			pxmitpriv->wmm_para_seq[i] = inx[i];
+			RTW_INFO("wmm_para_seq(%d): %d\n", i, pxmitpriv->wmm_para_seq[i]);
+		}
+
+	}
+
+}
+#ifdef CONFIG_80211N_HT
+static void update_hw_ht_param(_adapter *padapter)
+{
+	unsigned char		max_AMPDU_len;
+	unsigned char		min_MPDU_spacing;
+	struct mlme_ext_priv	*pmlmeext = &padapter->mlmeextpriv;
+	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
+
+	RTW_INFO("%s\n", __FUNCTION__);
+
+
+	/* handle A-MPDU parameter field */
+	/*
+		AMPDU_para [1:0]:Max AMPDU Len => 0:8k , 1:16k, 2:32k, 3:64k
+		AMPDU_para [4:2]:Min MPDU Start Spacing
+	*/
+	max_AMPDU_len = pmlmeinfo->HT_caps.u.HT_cap_element.AMPDU_para & 0x03;
+
+	min_MPDU_spacing = (pmlmeinfo->HT_caps.u.HT_cap_element.AMPDU_para & 0x1c) >> 2;
+
+	rtw_hal_set_hwreg(padapter, HW_VAR_AMPDU_MIN_SPACE, (u8 *)(&min_MPDU_spacing));
+
+	rtw_hal_set_hwreg(padapter, HW_VAR_AMPDU_FACTOR, (u8 *)(&max_AMPDU_len));
+
+	/*  */
+	/* Config SM Power Save setting */
+	/*  */
+	pmlmeinfo->SM_PS = (pmlmeinfo->HT_caps.u.HT_cap_element.HT_caps_info & 0x0C) >> 2;
+	if (pmlmeinfo->SM_PS == WLAN_HT_CAP_SM_PS_STATIC) {
+#if 0
+		u8 i;
+		/* update the MCS rates */
+		for (i = 0; i < 16; i++)
+			pmlmeinfo->HT_caps.HT_cap_element.MCS_rate[i] &= MCS_rate_1R[i];
+#endif
+		RTW_INFO("%s(): WLAN_HT_CAP_SM_PS_STATIC\n", __FUNCTION__);
+	}
+
+	/*  */
+	/* Config current HT Protection mode. */
+	/*  */
+	/* pmlmeinfo->HT_protection = pmlmeinfo->HT_info.infos[1] & 0x3; */
+
+}
+#endif /* CONFIG_80211N_HT */
+static void rtw_ap_check_scan(_adapter *padapter)
+{
+	_irqL	irqL;
+	_list		*plist, *phead;
+	u32	delta_time, lifetime;
+	struct	wlan_network	*pnetwork = NULL;
+	WLAN_BSSID_EX *pbss = NULL;
+	struct	mlme_priv	*pmlmepriv = &(padapter->mlmepriv);
+	_queue	*queue	= &(pmlmepriv->scanned_queue);
+	u8 do_scan = _FALSE;
+	u8 reason = RTW_AUTO_SCAN_REASON_UNSPECIFIED;
+
+	lifetime = SCANQUEUE_LIFETIME; /* 20 sec */
+
+	_enter_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);
+	phead = get_list_head(queue);
+	if (rtw_end_of_queue_search(phead, get_next(phead)) == _TRUE)
+		if (padapter->registrypriv.wifi_spec) {
+			do_scan = _TRUE;
+			reason |= RTW_AUTO_SCAN_REASON_2040_BSS;
+		}
+	_exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);
+
+#ifdef CONFIG_RTW_ACS
+	if (padapter->registrypriv.acs_auto_scan) {
+		do_scan = _TRUE;
+		reason |= RTW_AUTO_SCAN_REASON_ACS;
+		rtw_acs_start(padapter);
+	}
+#endif/*CONFIG_RTW_ACS*/
+
+	if (_TRUE == do_scan) {
+		RTW_INFO("%s : drv scans by itself and wait_completed\n", __func__);
+		rtw_drv_scan_by_self(padapter, reason);
+		rtw_scan_wait_completed(padapter);
+	}
+
+#ifdef CONFIG_RTW_ACS
+	if (padapter->registrypriv.acs_auto_scan)
+		rtw_acs_stop(padapter);
+#endif
+
+	_enter_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);
+
+	phead = get_list_head(queue);
+	plist = get_next(phead);
+
+	while (1) {
+
+		if (rtw_end_of_queue_search(phead, plist) == _TRUE)
+			break;
+
+		pnetwork = LIST_CONTAINOR(plist, struct wlan_network, list);
+
+		if (rtw_chset_search_ch(adapter_to_chset(padapter), pnetwork->network.Configuration.DSConfig) >= 0
+		    && rtw_mlme_band_check(padapter, pnetwork->network.Configuration.DSConfig) == _TRUE
+		    && _TRUE == rtw_validate_ssid(&(pnetwork->network.Ssid))) {
+			delta_time = (u32) rtw_get_passing_time_ms(pnetwork->last_scanned);
+
+			if (delta_time < lifetime) {
+
+				uint ie_len = 0;
+				u8 *pbuf = NULL;
+				u8 *ie = NULL;
+
+				pbss = &pnetwork->network;
+				ie = pbss->IEs;
+
+				/*check if HT CAP INFO IE exists or not*/
+				pbuf = rtw_get_ie(ie + _BEACON_IE_OFFSET_, _HT_CAPABILITY_IE_, &ie_len, (pbss->IELength - _BEACON_IE_OFFSET_));
+				if (pbuf == NULL) {
+					/* HT CAP INFO IE don't exist, it is b/g mode bss.*/
+
+					if (_FALSE == ATOMIC_READ(&pmlmepriv->olbc))
+						ATOMIC_SET(&pmlmepriv->olbc, _TRUE);
+
+					if (_FALSE == ATOMIC_READ(&pmlmepriv->olbc_ht))
+						ATOMIC_SET(&pmlmepriv->olbc_ht, _TRUE);
+					
+					if (padapter->registrypriv.wifi_spec)
+						RTW_INFO("%s: %s is a/b/g ap\n", __func__, pnetwork->network.Ssid.Ssid);
+				}
+			}
+		}
+
+		plist = get_next(plist);
+
+	}
+
+	_exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);
+#ifdef CONFIG_80211N_HT
+	pmlmepriv->num_sta_no_ht = 0; /* reset to 0 after ap do scanning*/
+#endif
+}
+
+void rtw_start_bss_hdl_after_chbw_decided(_adapter *adapter)
+{
+	WLAN_BSSID_EX *pnetwork = &(adapter->mlmepriv.cur_network.network);
+	struct sta_info *sta = NULL;
+
+	/* update cur_wireless_mode */
+	update_wireless_mode(adapter);
+
+	/* update RRSR and RTS_INIT_RATE register after set channel and bandwidth */
+	UpdateBrateTbl(adapter, pnetwork->SupportedRates);
+	rtw_hal_set_hwreg(adapter, HW_VAR_BASIC_RATE, pnetwork->SupportedRates);
+
+	/* update capability after cur_wireless_mode updated */
+	update_capinfo(adapter, rtw_get_capability(pnetwork));
+
+	/* update bc/mc sta_info */
+	update_bmc_sta(adapter);
+
+	/* update AP's sta info */
+	sta = rtw_get_stainfo(&adapter->stapriv, pnetwork->MacAddress);
+	if (!sta) {
+		RTW_INFO(FUNC_ADPT_FMT" !sta for macaddr="MAC_FMT"\n", FUNC_ADPT_ARG(adapter), MAC_ARG(pnetwork->MacAddress));
+		rtw_warn_on(1);
+		return;
+	}
+
+	update_ap_info(adapter, sta);
+}
+
+#ifdef CONFIG_FW_HANDLE_TXBCN
+bool rtw_ap_nums_check(_adapter *adapter)
+{
+	if (rtw_ap_get_nums(adapter) < CONFIG_LIMITED_AP_NUM)
+		return _TRUE;
+	return _FALSE;
+}
+u8 rtw_ap_allocate_vapid(struct dvobj_priv *dvobj)
+{
+	u8 vap_id;
+
+	for (vap_id = 0; vap_id < CONFIG_LIMITED_AP_NUM; vap_id++) {
+		if (!(dvobj->vap_map & BIT(vap_id)))
+			break;
+	}
+
+	if (vap_id < CONFIG_LIMITED_AP_NUM)
+		dvobj->vap_map |= BIT(vap_id);
+
+	return vap_id;
+}
+u8 rtw_ap_release_vapid(struct dvobj_priv *dvobj, u8 vap_id)
+{
+	if (vap_id >= CONFIG_LIMITED_AP_NUM) {
+		RTW_ERR("%s - vapid(%d) failed\n", __func__, vap_id);
+		rtw_warn_on(1);
+		return _FAIL;
+	}
+	dvobj->vap_map &= ~ BIT(vap_id);
+	return _SUCCESS;
+}
+#endif
+static void _rtw_iface_undersurvey_chk(const char *func, _adapter *adapter)
+{
+	int i;
+	_adapter *iface;
+	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
+	struct mlme_priv *pmlmepriv;
+
+	for (i = 0; i < dvobj->iface_nums; i++) {
+		iface = dvobj->padapters[i];
+		if ((iface) && rtw_is_adapter_up(iface)) {
+			pmlmepriv = &iface->mlmepriv;
+			if (check_fwstate(pmlmepriv, _FW_UNDER_SURVEY))
+				RTW_ERR("%s ("ADPT_FMT") under survey\n", func, ADPT_ARG(iface));
+		}
+	}
+}
+void start_bss_network(_adapter *padapter, struct createbss_parm *parm)
+{
+#define DUMP_ADAPTERS_STATUS 0
+	u8 mlme_act = MLME_ACTION_UNKNOWN;
+	u8 val8;
+	u16 bcn_interval;
+	u32	acparm;
+	struct registry_priv	*pregpriv = &padapter->registrypriv;
+	struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
+	struct security_priv *psecuritypriv = &(padapter->securitypriv);
+	WLAN_BSSID_EX *pnetwork = (WLAN_BSSID_EX *)&pmlmepriv->cur_network.network; /* used as input */
+	struct mlme_ext_priv	*pmlmeext = &(padapter->mlmeextpriv);
+	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
+	WLAN_BSSID_EX *pnetwork_mlmeext = &(pmlmeinfo->network);
+	struct dvobj_priv *pdvobj = padapter->dvobj;
+	s16 req_ch = REQ_CH_NONE, req_bw = REQ_BW_NONE, req_offset = REQ_OFFSET_NONE;
+	u8 ch_to_set = 0, bw_to_set, offset_to_set;
+	u8 doiqk = _FALSE;
+	/* use for check ch bw offset can be allowed or not */
+	u8 chbw_allow = _TRUE;
+	int i;
+	u8 ifbmp_ch_changed = 0;
+
+	if (parm->req_ch != 0) {
+		/* bypass other setting, go checking ch, bw, offset */
+		mlme_act = MLME_OPCH_SWITCH;
+		req_ch = parm->req_ch;
+		req_bw = parm->req_bw;
+		req_offset = parm->req_offset;
+		goto chbw_decision;
+	} else {
+		/* request comes from upper layer */
+		if (MLME_IS_AP(padapter))
+			mlme_act = MLME_AP_STARTED;
+		else if (MLME_IS_MESH(padapter))
+			mlme_act = MLME_MESH_STARTED;
+		else
+			rtw_warn_on(1);
+		req_ch = 0;
+		_rtw_memcpy(pnetwork_mlmeext, pnetwork, pnetwork->Length);
+	}
+
+	bcn_interval = (u16)pnetwork->Configuration.BeaconPeriod;
+
+	/* check if there is wps ie, */
+	/* if there is wpsie in beacon, the hostapd will update beacon twice when stating hostapd, */
+	/* and at first time the security ie ( RSN/WPA IE) will not include in beacon. */
+	if (NULL == rtw_get_wps_ie(pnetwork->IEs + _FIXED_IE_LENGTH_, pnetwork->IELength - _FIXED_IE_LENGTH_, NULL, NULL))
+		pmlmeext->bstart_bss = _TRUE;
+
+	/* todo: update wmm, ht cap */
+	/* pmlmeinfo->WMM_enable; */
+	/* pmlmeinfo->HT_enable; */
+	if (pmlmepriv->qospriv.qos_option)
+		pmlmeinfo->WMM_enable = _TRUE;
+#ifdef CONFIG_80211N_HT
+	if (pmlmepriv->htpriv.ht_option) {
+		pmlmeinfo->WMM_enable = _TRUE;
+		pmlmeinfo->HT_enable = _TRUE;
+		/* pmlmeinfo->HT_info_enable = _TRUE; */
+		/* pmlmeinfo->HT_caps_enable = _TRUE; */
+
+		update_hw_ht_param(padapter);
+	}
+#endif /* #CONFIG_80211N_HT */
+
+#ifdef CONFIG_80211AC_VHT
+	if (pmlmepriv->vhtpriv.vht_option) {
+		pmlmeinfo->VHT_enable = _TRUE;
+		update_hw_vht_param(padapter);
+	}
+#endif /* CONFIG_80211AC_VHT */
+
+	if (pmlmepriv->cur_network.join_res != _TRUE) { /* setting only at  first time */
+		/* WEP Key will be set before this function, do not clear CAM. */
+		if ((psecuritypriv->dot11PrivacyAlgrthm != _WEP40_) && (psecuritypriv->dot11PrivacyAlgrthm != _WEP104_)
+			&& !MLME_IS_MESH(padapter) /* mesh group key is set before this function */
+		)
+			flush_all_cam_entry(padapter);	/* clear CAM */
+	}
+
+	/* set MSR to AP_Mode		 */
+	Set_MSR(padapter, _HW_STATE_AP_);
+
+	/* Set BSSID REG */
+	rtw_hal_set_hwreg(padapter, HW_VAR_BSSID, pnetwork->MacAddress);
+
+	/* Set Security */
+	val8 = (psecuritypriv->dot11AuthAlgrthm == dot11AuthAlgrthm_8021X) ? 0xcc : 0xcf;
+	rtw_hal_set_hwreg(padapter, HW_VAR_SEC_CFG, (u8 *)(&val8));
+
+	/* Beacon Control related register */
+	rtw_hal_set_hwreg(padapter, HW_VAR_BEACON_INTERVAL, (u8 *)(&bcn_interval));
+
+	rtw_hal_rcr_set_chk_bssid(padapter, mlme_act);
+
+chbw_decision:
+	ifbmp_ch_changed = rtw_ap_chbw_decision(padapter, parm->ifbmp, parm->excl_ifbmp
+						, req_ch, req_bw, req_offset
+						, &ch_to_set, &bw_to_set, &offset_to_set, &chbw_allow);
+
+	for (i = 0; i < pdvobj->iface_nums; i++) {
+		if (!(parm->ifbmp & BIT(i)) || !pdvobj->padapters[i])
+			continue;
+
+		/* let pnetwork_mlme == pnetwork_mlmeext */
+		_rtw_memcpy(&(pdvobj->padapters[i]->mlmepriv.cur_network.network)
+			, &(pdvobj->padapters[i]->mlmeextpriv.mlmext_info.network)
+			, pdvobj->padapters[i]->mlmeextpriv.mlmext_info.network.Length);
+
+		rtw_start_bss_hdl_after_chbw_decided(pdvobj->padapters[i]);
+
+		/* Set EDCA param reg after update cur_wireless_mode & update_capinfo */
+		if (pregpriv->wifi_spec == 1)
+			rtw_set_hw_wmm_param(pdvobj->padapters[i]);
+	}
+
+#if defined(CONFIG_DFS_MASTER)
+	rtw_dfs_rd_en_decision(padapter, mlme_act, parm->excl_ifbmp);
+#endif
+
+#ifdef CONFIG_MCC_MODE
+	if (MCC_EN(padapter)) {
+		/* 
+		* due to check under rtw_ap_chbw_decision
+		* if under MCC mode, means req channel setting is the same as current channel setting
+		* if not under MCC mode, mean req channel setting is not the same as current channel setting
+		*/
+		if (rtw_hal_check_mcc_status(padapter, MCC_STATUS_DOING_MCC)) {
+				RTW_INFO(FUNC_ADPT_FMT": req channel setting is the same as current channel setting, go to update BCN\n"
+				, FUNC_ADPT_ARG(padapter));
+
+				goto update_beacon;
+
+		}
+	}
+
+	/* issue null data to AP for all interface connecting to AP before switch channel setting for softap */
+	rtw_hal_mcc_issue_null_data(padapter, chbw_allow, 1);
+#endif /* CONFIG_MCC_MODE */
+
+	if (!IS_CH_WAITING(adapter_to_rfctl(padapter))) {
+		doiqk = _TRUE;
+		rtw_hal_set_hwreg(padapter , HW_VAR_DO_IQK , &doiqk);
+	}
+
+	if (ch_to_set != 0) {
+		set_channel_bwmode(padapter, ch_to_set, offset_to_set, bw_to_set);
+		rtw_mi_update_union_chan_inf(padapter, ch_to_set, offset_to_set, bw_to_set);
+	}
+
+	doiqk = _FALSE;
+	rtw_hal_set_hwreg(padapter , HW_VAR_DO_IQK , &doiqk);
+
+#ifdef CONFIG_MCC_MODE
+	/* after set_channel_bwmode for backup IQK */
+	rtw_hal_set_mcc_setting_start_bss_network(padapter, chbw_allow);
+#endif
+
+#if defined(CONFIG_IOCTL_CFG80211) && (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 5, 0))
+	for (i = 0; i < pdvobj->iface_nums; i++) {
+		if (!(ifbmp_ch_changed & BIT(i)) || !pdvobj->padapters[i])
+			continue;
+
+		/* pure AP is not needed*/
+		if (MLME_IS_GO(pdvobj->padapters[i])
+			|| MLME_IS_MESH(pdvobj->padapters[i])
+		) {
+			u8 ht_option = 0;
+
+			#ifdef CONFIG_80211N_HT
+			ht_option = pdvobj->padapters[i]->mlmepriv.htpriv.ht_option;
+			#endif
+
+			rtw_cfg80211_ch_switch_notify(pdvobj->padapters[i]
+				, pdvobj->padapters[i]->mlmeextpriv.cur_channel
+				, pdvobj->padapters[i]->mlmeextpriv.cur_bwmode
+				, pdvobj->padapters[i]->mlmeextpriv.cur_ch_offset
+				, ht_option);
+		}
+	}
+#endif /* defined(CONFIG_IOCTL_CFG80211) && (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 5, 0)) */
+
+	if (DUMP_ADAPTERS_STATUS) {
+		RTW_INFO(FUNC_ADPT_FMT" done\n", FUNC_ADPT_ARG(padapter));
+		dump_adapters_status(RTW_DBGDUMP , adapter_to_dvobj(padapter));
+	}
+
+#ifdef CONFIG_MCC_MODE
+update_beacon:
+#endif
+
+	for (i = 0; i < pdvobj->iface_nums; i++) {
+		struct mlme_priv *mlme;
+
+		if (!(parm->ifbmp & BIT(i)) || !pdvobj->padapters[i])
+			continue;
+
+		/* update beacon content only if bstart_bss is _TRUE */
+		if (pdvobj->padapters[i]->mlmeextpriv.bstart_bss != _TRUE)
+			continue;
+
+		mlme = &(pdvobj->padapters[i]->mlmepriv);
+
+		#ifdef CONFIG_80211N_HT
+		if ((ATOMIC_READ(&mlme->olbc) == _TRUE) || (ATOMIC_READ(&mlme->olbc_ht) == _TRUE)) {
+			/* AP is not starting a 40 MHz BSS in presence of an 802.11g BSS. */
+			mlme->ht_op_mode &= (~HT_INFO_OPERATION_MODE_OP_MODE_MASK);
+			mlme->ht_op_mode |= OP_MODE_MAY_BE_LEGACY_STAS;
+			update_beacon(pdvobj->padapters[i], _HT_ADD_INFO_IE_, NULL, _FALSE);
+		}
+		#endif
+
+		update_beacon(pdvobj->padapters[i], _TIM_IE_, NULL, _FALSE);
+	}
+
+	if (mlme_act != MLME_OPCH_SWITCH
+		&& pmlmeext->bstart_bss == _TRUE
+	) {
+#ifdef CONFIG_SUPPORT_MULTI_BCN
+		_irqL irqL;
+
+		_enter_critical_bh(&pdvobj->ap_if_q.lock, &irqL);
+		if (rtw_is_list_empty(&padapter->list)) {
+			#ifdef CONFIG_FW_HANDLE_TXBCN
+			padapter->vap_id = rtw_ap_allocate_vapid(pdvobj);
+			#endif
+			rtw_list_insert_tail(&padapter->list, get_list_head(&pdvobj->ap_if_q));
+			pdvobj->nr_ap_if++;
+			pdvobj->inter_bcn_space = DEFAULT_BCN_INTERVAL / pdvobj->nr_ap_if;
+		}
+		_exit_critical_bh(&pdvobj->ap_if_q.lock, &irqL);
+
+		#ifdef CONFIG_SWTIMER_BASED_TXBCN
+		rtw_ap_set_mbid_num(padapter, pdvobj->nr_ap_if);
+		rtw_hal_set_hwreg(padapter, HW_VAR_BEACON_INTERVAL, (u8 *)(&pdvobj->inter_bcn_space));
+		#endif /*CONFIG_SWTIMER_BASED_TXBCN*/
+
+#endif /*CONFIG_SUPPORT_MULTI_BCN*/
+
+		#ifdef CONFIG_HW_P0_TSF_SYNC
+		correct_TSF(padapter, mlme_act);
+		#endif
+	}
+
+	rtw_scan_wait_completed(padapter);
+
+	_rtw_iface_undersurvey_chk(__func__, padapter);
+	/* send beacon */
+	ResumeTxBeacon(padapter);
+	{
+#if !defined(CONFIG_INTERRUPT_BASED_TXBCN)
+#if defined(CONFIG_USB_HCI) || defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
+#ifdef CONFIG_SWTIMER_BASED_TXBCN
+		if (pdvobj->nr_ap_if == 1
+			&& mlme_act != MLME_OPCH_SWITCH
+		) {
+			RTW_INFO("start SW BCN TIMER!\n");
+			_set_timer(&pdvobj->txbcn_timer, bcn_interval);
+		}
+#else
+		for (i = 0; i < pdvobj->iface_nums; i++) {
+			if (!(parm->ifbmp & BIT(i)) || !pdvobj->padapters[i])
+				continue;
+
+			if (send_beacon(pdvobj->padapters[i]) == _FAIL)
+				RTW_INFO(ADPT_FMT" issue_beacon, fail!\n", ADPT_ARG(pdvobj->padapters[i]));
+		}
+#endif
+#endif
+#endif /* !defined(CONFIG_INTERRUPT_BASED_TXBCN) */
+
+#ifdef CONFIG_FW_HANDLE_TXBCN
+		if (mlme_act != MLME_OPCH_SWITCH)
+			rtw_ap_mbid_bcn_en(padapter, padapter->vap_id);
+#endif
+	}
+}
+
+int rtw_check_beacon_data(_adapter *padapter, u8 *pbuf,  int len)
+{
+	int ret = _SUCCESS;
+	u8 *p;
+	u8 *pHT_caps_ie = NULL;
+	u8 *pHT_info_ie = NULL;
+	u16 cap, ht_cap = _FALSE;
+	uint ie_len = 0;
+	int group_cipher, pairwise_cipher;
+	u8 mfp_opt = MFP_NO;
+	u8	channel, network_type, supportRate[NDIS_802_11_LENGTH_RATES_EX];
+	int supportRateNum = 0;
+	u8 OUI1[] = {0x00, 0x50, 0xf2, 0x01};
+	u8 WMM_PARA_IE[] = {0x00, 0x50, 0xf2, 0x02, 0x01, 0x01};
+	HT_CAP_AMPDU_DENSITY best_ampdu_density;
+	struct registry_priv *pregistrypriv = &padapter->registrypriv;
+	struct security_priv *psecuritypriv = &padapter->securitypriv;
+	struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
+	WLAN_BSSID_EX *pbss_network = (WLAN_BSSID_EX *)&pmlmepriv->cur_network.network;
+	u8 *ie = pbss_network->IEs;
+	u8 vht_cap = _FALSE;
+	struct mlme_ext_priv	*pmlmeext = &(padapter->mlmeextpriv);
+	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
+	struct rf_ctl_t *rfctl = adapter_to_rfctl(padapter);
+	u8 rf_num = 0;
+	int ret_rm;
+	/* SSID */
+	/* Supported rates */
+	/* DS Params */
+	/* WLAN_EID_COUNTRY */
+	/* ERP Information element */
+	/* Extended supported rates */
+	/* WPA/WPA2 */
+	/* Wi-Fi Wireless Multimedia Extensions */
+	/* ht_capab, ht_oper */
+	/* WPS IE */
+
+	RTW_INFO("%s, len=%d\n", __FUNCTION__, len);
+
+	if (!MLME_IS_AP(padapter) && !MLME_IS_MESH(padapter))
+		return _FAIL;
+
+
+	if (len > MAX_IE_SZ)
+		return _FAIL;
+
+	pbss_network->IELength = len;
+
+	_rtw_memset(ie, 0, MAX_IE_SZ);
+
+	_rtw_memcpy(ie, pbuf, pbss_network->IELength);
+
+
+	if (pbss_network->InfrastructureMode != Ndis802_11APMode
+		&& pbss_network->InfrastructureMode != Ndis802_11_mesh
+	) {
+		rtw_warn_on(1);
+		return _FAIL;
+	}
+
+
+	rtw_ap_check_scan(padapter);
+
+
+	pbss_network->Rssi = 0;
+
+	_rtw_memcpy(pbss_network->MacAddress, adapter_mac_addr(padapter), ETH_ALEN);
+
+	/* beacon interval */
+	p = rtw_get_beacon_interval_from_ie(ie);/* ie + 8;	 */ /* 8: TimeStamp, 2: Beacon Interval 2:Capability */
+	/* pbss_network->Configuration.BeaconPeriod = le16_to_cpu(*(unsigned short*)p); */
+	pbss_network->Configuration.BeaconPeriod = RTW_GET_LE16(p);
+
+	/* capability */
+	/* cap = *(unsigned short *)rtw_get_capability_from_ie(ie); */
+	/* cap = le16_to_cpu(cap); */
+	cap = RTW_GET_LE16(ie);
+
+	/* SSID */
+	p = rtw_get_ie(ie + _BEACON_IE_OFFSET_, _SSID_IE_, &ie_len, (pbss_network->IELength - _BEACON_IE_OFFSET_));
+	if (p && ie_len > 0) {
+		_rtw_memset(&pbss_network->Ssid, 0, sizeof(NDIS_802_11_SSID));
+		_rtw_memcpy(pbss_network->Ssid.Ssid, (p + 2), ie_len);
+		pbss_network->Ssid.SsidLength = ie_len;
+#ifdef CONFIG_P2P
+		_rtw_memcpy(padapter->wdinfo.p2p_group_ssid, pbss_network->Ssid.Ssid, pbss_network->Ssid.SsidLength);
+		padapter->wdinfo.p2p_group_ssid_len = pbss_network->Ssid.SsidLength;
+#endif
+	}
+
+#ifdef CONFIG_RTW_MESH
+	/* Mesh ID */
+	if (MLME_IS_MESH(padapter)) {
+		p = rtw_get_ie(ie + _BEACON_IE_OFFSET_, WLAN_EID_MESH_ID, &ie_len, (pbss_network->IELength - _BEACON_IE_OFFSET_));
+		if (p && ie_len > 0) {
+			_rtw_memset(&pbss_network->mesh_id, 0, sizeof(NDIS_802_11_SSID));
+			_rtw_memcpy(pbss_network->mesh_id.Ssid, (p + 2), ie_len);
+			pbss_network->mesh_id.SsidLength = ie_len;
+		}
+	}
+#endif
+
+	/* chnnel */
+	channel = 0;
+	pbss_network->Configuration.Length = 0;
+	p = rtw_get_ie(ie + _BEACON_IE_OFFSET_, _DSSET_IE_, &ie_len, (pbss_network->IELength - _BEACON_IE_OFFSET_));
+	if (p && ie_len > 0)
+		channel = *(p + 2);
+
+	pbss_network->Configuration.DSConfig = channel;
+
+
+	_rtw_memset(supportRate, 0, NDIS_802_11_LENGTH_RATES_EX);
+	/* get supported rates */
+	p = rtw_get_ie(ie + _BEACON_IE_OFFSET_, _SUPPORTEDRATES_IE_, &ie_len, (pbss_network->IELength - _BEACON_IE_OFFSET_));
+	if (p !=  NULL) {
+		if (padapter->registrypriv.wireless_mode == WIRELESS_11B) {
+			ret_rm = rtw_remove_ie_g_rate(ie , &len, _BEACON_IE_OFFSET_, _SUPPORTEDRATES_IE_);
+			RTW_DBG("%s, rtw_remove_ie_g_rate=%d\n", __FUNCTION__,ret_rm);
+			ie_len = ie_len - ret_rm;
+			pbss_network->IELength=pbss_network->IELength - ret_rm;
+		}
+		RTW_DBG("%s, ie_len=%u\n", __FUNCTION__, ie_len);
+		_rtw_memcpy(supportRate, p + 2, ie_len);
+		supportRateNum = ie_len;
+	}
+
+	/* get ext_supported rates */
+	p = rtw_get_ie(ie + _BEACON_IE_OFFSET_, _EXT_SUPPORTEDRATES_IE_, &ie_len, pbss_network->IELength - _BEACON_IE_OFFSET_);
+	if (p !=  NULL) {
+		if (padapter->registrypriv.wireless_mode == WIRELESS_11B) {
+			pbss_network->IELength = pbss_network->IELength-*(p+1) -2;
+			ret_rm = rtw_ies_remove_ie(ie , &len,_BEACON_IE_OFFSET_,
+					_EXT_SUPPORTEDRATES_IE_,NULL,0);
+			RTW_DBG("%s, remove_ie of ext_supported rates =%d\n", __FUNCTION__, ret_rm);
+		} else {
+			_rtw_memcpy(supportRate + supportRateNum, p + 2, ie_len);
+			supportRateNum += ie_len;
+		}
+
+	}
+
+	network_type = rtw_check_network_type(supportRate, supportRateNum, channel);
+
+	rtw_set_supported_rate(pbss_network->SupportedRates, network_type);
+
+
+	/* parsing ERP_IE */
+	p = rtw_get_ie(ie + _BEACON_IE_OFFSET_, _ERPINFO_IE_, &ie_len, (pbss_network->IELength - _BEACON_IE_OFFSET_));
+	if (p && ie_len > 0)  {
+		if(padapter->registrypriv.wireless_mode == WIRELESS_11B ) {
+
+			pbss_network->IELength = pbss_network->IELength - *(p+1) - 2;
+			ret_rm = rtw_ies_remove_ie(ie , &len, _BEACON_IE_OFFSET_, _ERPINFO_IE_,NULL,0);
+			RTW_DBG("%s, remove_ie of ERP_IE=%d\n", __FUNCTION__, ret_rm);
+		} else 
+			ERP_IE_handler(padapter, (PNDIS_802_11_VARIABLE_IEs)p);
+
+	}
+
+	/* update privacy/security */
+	if (cap & BIT(4))
+		pbss_network->Privacy = 1;
+	else
+		pbss_network->Privacy = 0;
+
+	psecuritypriv->wpa_psk = 0;
+
+	/* wpa2 */
+	group_cipher = 0;
+	pairwise_cipher = 0;
+	psecuritypriv->wpa2_group_cipher = _NO_PRIVACY_;
+	psecuritypriv->wpa2_pairwise_cipher = _NO_PRIVACY_;
+	p = rtw_get_ie(ie + _BEACON_IE_OFFSET_, _RSN_IE_2_, &ie_len, (pbss_network->IELength - _BEACON_IE_OFFSET_));
+	if (p && ie_len > 0) {
+		if (rtw_parse_wpa2_ie(p, ie_len + 2, &group_cipher, &pairwise_cipher, NULL, &mfp_opt) == _SUCCESS) {
+			psecuritypriv->dot11AuthAlgrthm = dot11AuthAlgrthm_8021X;
+			psecuritypriv->ndisauthtype = Ndis802_11AuthModeWPA2PSK;
+			psecuritypriv->dot8021xalg = 1;/* psk,  todo:802.1x */
+			psecuritypriv->wpa_psk |= BIT(1);
+
+			psecuritypriv->wpa2_group_cipher = group_cipher;
+			psecuritypriv->wpa2_pairwise_cipher = pairwise_cipher;
+#if 0
+			switch (group_cipher) {
+			case WPA_CIPHER_NONE:
+				psecuritypriv->wpa2_group_cipher = _NO_PRIVACY_;
+				break;
+			case WPA_CIPHER_WEP40:
+				psecuritypriv->wpa2_group_cipher = _WEP40_;
+				break;
+			case WPA_CIPHER_TKIP:
+				psecuritypriv->wpa2_group_cipher = _TKIP_;
+				break;
+			case WPA_CIPHER_CCMP:
+				psecuritypriv->wpa2_group_cipher = _AES_;
+				break;
+			case WPA_CIPHER_WEP104:
+				psecuritypriv->wpa2_group_cipher = _WEP104_;
+				break;
+			}
+
+			switch (pairwise_cipher) {
+			case WPA_CIPHER_NONE:
+				psecuritypriv->wpa2_pairwise_cipher = _NO_PRIVACY_;
+				break;
+			case WPA_CIPHER_WEP40:
+				psecuritypriv->wpa2_pairwise_cipher = _WEP40_;
+				break;
+			case WPA_CIPHER_TKIP:
+				psecuritypriv->wpa2_pairwise_cipher = _TKIP_;
+				break;
+			case WPA_CIPHER_CCMP:
+				psecuritypriv->wpa2_pairwise_cipher = _AES_;
+				break;
+			case WPA_CIPHER_WEP104:
+				psecuritypriv->wpa2_pairwise_cipher = _WEP104_;
+				break;
+			}
+#endif
+		}
+
+	}
+
+	/* wpa */
+	ie_len = 0;
+	group_cipher = 0;
+	pairwise_cipher = 0;
+	psecuritypriv->wpa_group_cipher = _NO_PRIVACY_;
+	psecuritypriv->wpa_pairwise_cipher = _NO_PRIVACY_;
+	for (p = ie + _BEACON_IE_OFFSET_; ; p += (ie_len + 2)) {
+		p = rtw_get_ie(p, _SSN_IE_1_, &ie_len, (pbss_network->IELength - _BEACON_IE_OFFSET_ - (ie_len + 2)));
+		if ((p) && (_rtw_memcmp(p + 2, OUI1, 4))) {
+			if (rtw_parse_wpa_ie(p, ie_len + 2, &group_cipher, &pairwise_cipher, NULL) == _SUCCESS) {
+				psecuritypriv->dot11AuthAlgrthm = dot11AuthAlgrthm_8021X;
+				psecuritypriv->ndisauthtype = Ndis802_11AuthModeWPAPSK;
+				psecuritypriv->dot8021xalg = 1;/* psk,  todo:802.1x */
+
+				psecuritypriv->wpa_psk |= BIT(0);
+
+				psecuritypriv->wpa_group_cipher = group_cipher;
+				psecuritypriv->wpa_pairwise_cipher = pairwise_cipher;
+
+#if 0
+				switch (group_cipher) {
+				case WPA_CIPHER_NONE:
+					psecuritypriv->wpa_group_cipher = _NO_PRIVACY_;
+					break;
+				case WPA_CIPHER_WEP40:
+					psecuritypriv->wpa_group_cipher = _WEP40_;
+					break;
+				case WPA_CIPHER_TKIP:
+					psecuritypriv->wpa_group_cipher = _TKIP_;
+					break;
+				case WPA_CIPHER_CCMP:
+					psecuritypriv->wpa_group_cipher = _AES_;
+					break;
+				case WPA_CIPHER_WEP104:
+					psecuritypriv->wpa_group_cipher = _WEP104_;
+					break;
+				}
+
+				switch (pairwise_cipher) {
+				case WPA_CIPHER_NONE:
+					psecuritypriv->wpa_pairwise_cipher = _NO_PRIVACY_;
+					break;
+				case WPA_CIPHER_WEP40:
+					psecuritypriv->wpa_pairwise_cipher = _WEP40_;
+					break;
+				case WPA_CIPHER_TKIP:
+					psecuritypriv->wpa_pairwise_cipher = _TKIP_;
+					break;
+				case WPA_CIPHER_CCMP:
+					psecuritypriv->wpa_pairwise_cipher = _AES_;
+					break;
+				case WPA_CIPHER_WEP104:
+					psecuritypriv->wpa_pairwise_cipher = _WEP104_;
+					break;
+				}
+#endif
+			}
+
+			break;
+
+		}
+
+		if ((p == NULL) || (ie_len == 0))
+			break;
+
+	}
+
+#ifdef CONFIG_RTW_MESH
+	if (MLME_IS_MESH(padapter)) {
+		/* MFP is mandatory for secure mesh */
+		if (padapter->mesh_info.mesh_auth_id)
+			mfp_opt = MFP_REQUIRED;
+	} else
+#endif
+	if (mfp_opt == MFP_INVALID) {
+		RTW_INFO(FUNC_ADPT_FMT" invalid MFP setting\n", FUNC_ADPT_ARG(padapter));
+		return _FAIL;
+	}
+	psecuritypriv->mfp_opt = mfp_opt;
+
+	/* wmm */
+	ie_len = 0;
+	pmlmepriv->qospriv.qos_option = 0;
+#ifdef CONFIG_RTW_MESH
+	if (MLME_IS_MESH(padapter))
+		pmlmepriv->qospriv.qos_option = 1;
+#endif
+	if (pregistrypriv->wmm_enable) {
+		for (p = ie + _BEACON_IE_OFFSET_; ; p += (ie_len + 2)) {
+			p = rtw_get_ie(p, _VENDOR_SPECIFIC_IE_, &ie_len, (pbss_network->IELength - _BEACON_IE_OFFSET_ - (ie_len + 2)));
+			if ((p) && _rtw_memcmp(p + 2, WMM_PARA_IE, 6)) {
+				pmlmepriv->qospriv.qos_option = 1;
+
+				*(p + 8) |= BIT(7); /* QoS Info, support U-APSD */
+
+				/* disable all ACM bits since the WMM admission control is not supported */
+				*(p + 10) &= ~BIT(4); /* BE */
+				*(p + 14) &= ~BIT(4); /* BK */
+				*(p + 18) &= ~BIT(4); /* VI */
+				*(p + 22) &= ~BIT(4); /* VO */
+
+				WMM_param_handler(padapter, (PNDIS_802_11_VARIABLE_IEs)p);
+
+				break;
+			}
+
+			if ((p == NULL) || (ie_len == 0))
+				break;
+		}
+	}
+#ifdef CONFIG_80211N_HT
+	if(padapter->registrypriv.ht_enable &&
+		is_supported_ht(padapter->registrypriv.wireless_mode)) {
+		/* parsing HT_CAP_IE */
+		p = rtw_get_ie(ie + _BEACON_IE_OFFSET_, _HT_CAPABILITY_IE_, &ie_len, (pbss_network->IELength - _BEACON_IE_OFFSET_));
+		if (p && ie_len > 0) {
+			u8 rf_type = 0;
+			HT_CAP_AMPDU_FACTOR max_rx_ampdu_factor = MAX_AMPDU_FACTOR_64K;
+			struct rtw_ieee80211_ht_cap *pht_cap = (struct rtw_ieee80211_ht_cap *)(p + 2);
+
+			if (0) {
+				RTW_INFO(FUNC_ADPT_FMT" HT_CAP_IE from upper layer:\n", FUNC_ADPT_ARG(padapter));
+				dump_ht_cap_ie_content(RTW_DBGDUMP, p + 2, ie_len);
+			}
+
+			pHT_caps_ie = p;
+
+			ht_cap = _TRUE;
+			network_type |= WIRELESS_11_24N;
+
+			rtw_ht_use_default_setting(padapter);
+
+			/* Update HT Capabilities Info field */
+			if (pmlmepriv->htpriv.sgi_20m == _FALSE)
+				pht_cap->cap_info &= ~(IEEE80211_HT_CAP_SGI_20);
+
+			if (pmlmepriv->htpriv.sgi_40m == _FALSE)
+				pht_cap->cap_info &= ~(IEEE80211_HT_CAP_SGI_40);
+
+			if (!TEST_FLAG(pmlmepriv->htpriv.ldpc_cap, LDPC_HT_ENABLE_RX))
+				pht_cap->cap_info &= ~(IEEE80211_HT_CAP_LDPC_CODING);
+
+			if (!TEST_FLAG(pmlmepriv->htpriv.stbc_cap, STBC_HT_ENABLE_TX))
+				pht_cap->cap_info &= ~(IEEE80211_HT_CAP_TX_STBC);
+
+			if (!TEST_FLAG(pmlmepriv->htpriv.stbc_cap, STBC_HT_ENABLE_RX))
+				pht_cap->cap_info &= ~(IEEE80211_HT_CAP_RX_STBC_3R);
+
+			/* Update A-MPDU Parameters field */
+			pht_cap->ampdu_params_info &= ~(IEEE80211_HT_CAP_AMPDU_FACTOR | IEEE80211_HT_CAP_AMPDU_DENSITY);
+
+			if ((psecuritypriv->wpa_pairwise_cipher & WPA_CIPHER_CCMP) ||
+				(psecuritypriv->wpa2_pairwise_cipher & WPA_CIPHER_CCMP)) {
+				rtw_hal_get_def_var(padapter, HW_VAR_BEST_AMPDU_DENSITY, &best_ampdu_density);
+				pht_cap->ampdu_params_info |= (IEEE80211_HT_CAP_AMPDU_DENSITY & (best_ampdu_density << 2));
+			} else
+				pht_cap->ampdu_params_info |= (IEEE80211_HT_CAP_AMPDU_DENSITY & 0x00);
+
+			rtw_hal_get_def_var(padapter, HW_VAR_MAX_RX_AMPDU_FACTOR, &max_rx_ampdu_factor);
+			pht_cap->ampdu_params_info |= (IEEE80211_HT_CAP_AMPDU_FACTOR & max_rx_ampdu_factor); /* set  Max Rx AMPDU size  to 64K */
+
+			_rtw_memcpy(&(pmlmeinfo->HT_caps), pht_cap, sizeof(struct HT_caps_element));
+
+			/* Update Supported MCS Set field */
+			{
+				struct hal_spec_t *hal_spec = GET_HAL_SPEC(padapter);
+				u8 rx_nss = 0;
+				int i;
+
+				rtw_hal_get_hwreg(padapter, HW_VAR_RF_TYPE, (u8 *)(&rf_type));
+				rx_nss = rtw_min(rf_type_to_rf_rx_cnt(rf_type), hal_spec->rx_nss_num);
+
+				/* RX MCS Bitmask */
+				switch (rx_nss) {
+				case 1:
+					set_mcs_rate_by_mask(HT_CAP_ELE_RX_MCS_MAP(pht_cap), MCS_RATE_1R);
+					break;
+				case 2:
+					set_mcs_rate_by_mask(HT_CAP_ELE_RX_MCS_MAP(pht_cap), MCS_RATE_2R);
+					break;
+				case 3:
+					set_mcs_rate_by_mask(HT_CAP_ELE_RX_MCS_MAP(pht_cap), MCS_RATE_3R);
+					break;
+				case 4:
+					set_mcs_rate_by_mask(HT_CAP_ELE_RX_MCS_MAP(pht_cap), MCS_RATE_4R);
+					break;
+				default:
+					RTW_WARN("rf_type:%d or rx_nss:%u is not expected\n", rf_type, hal_spec->rx_nss_num);
+				}
+				for (i = 0; i < 10; i++)
+					*(HT_CAP_ELE_RX_MCS_MAP(pht_cap) + i) &= padapter->mlmeextpriv.default_supported_mcs_set[i];
+			}
+
+#ifdef CONFIG_BEAMFORMING
+			/* Use registry value to enable HT Beamforming. */
+			/* ToDo: use configure file to set these capability. */
+			pht_cap->tx_BF_cap_info = 0;
+
+			/* HT Beamformer */
+			if (TEST_FLAG(pmlmepriv->htpriv.beamform_cap, BEAMFORMING_HT_BEAMFORMER_ENABLE)) {
+				/* Transmit NDP Capable */
+				SET_HT_CAP_TXBF_TRANSMIT_NDP_CAP(pht_cap, 1);
+				/* Explicit Compressed Steering Capable */
+				SET_HT_CAP_TXBF_EXPLICIT_COMP_STEERING_CAP(pht_cap, 1);
+				/* Compressed Steering Number Antennas */
+				SET_HT_CAP_TXBF_COMP_STEERING_NUM_ANTENNAS(pht_cap, 1);
+				rtw_hal_get_def_var(padapter, HAL_DEF_BEAMFORMER_CAP, (u8 *)&rf_num);
+				SET_HT_CAP_TXBF_CHNL_ESTIMATION_NUM_ANTENNAS(pht_cap, rf_num);
+			}
+
+			/* HT Beamformee */
+			if (TEST_FLAG(pmlmepriv->htpriv.beamform_cap, BEAMFORMING_HT_BEAMFORMEE_ENABLE)) {
+				/* Receive NDP Capable */
+				SET_HT_CAP_TXBF_RECEIVE_NDP_CAP(pht_cap, 1);
+				/* Explicit Compressed Beamforming Feedback Capable */
+				SET_HT_CAP_TXBF_EXPLICIT_COMP_FEEDBACK_CAP(pht_cap, 2);
+				rtw_hal_get_def_var(padapter, HAL_DEF_BEAMFORMEE_CAP, (u8 *)&rf_num);
+				SET_HT_CAP_TXBF_COMP_STEERING_NUM_ANTENNAS(pht_cap, rf_num);
+			}
+#endif /* CONFIG_BEAMFORMING */
+
+			_rtw_memcpy(&pmlmepriv->htpriv.ht_cap, p + 2, ie_len);
+
+			if (0) {
+				RTW_INFO(FUNC_ADPT_FMT" HT_CAP_IE driver masked:\n", FUNC_ADPT_ARG(padapter));
+				dump_ht_cap_ie_content(RTW_DBGDUMP, p + 2, ie_len);
+			}
+		}
+
+		/* parsing HT_INFO_IE */
+		p = rtw_get_ie(ie + _BEACON_IE_OFFSET_, _HT_ADD_INFO_IE_, &ie_len, (pbss_network->IELength - _BEACON_IE_OFFSET_));
+		if (p && ie_len > 0) {
+			pHT_info_ie = p;
+			if (channel == 0)
+				pbss_network->Configuration.DSConfig = GET_HT_OP_ELE_PRI_CHL(pHT_info_ie + 2);
+			else if (channel != GET_HT_OP_ELE_PRI_CHL(pHT_info_ie + 2)) {
+				RTW_INFO(FUNC_ADPT_FMT" ch inconsistent, DSSS:%u, HT primary:%u\n"
+					, FUNC_ADPT_ARG(padapter), channel, GET_HT_OP_ELE_PRI_CHL(pHT_info_ie + 2));
+			}
+		}
+	}
+#endif /* CONFIG_80211N_HT */
+
+	switch (network_type) {
+	case WIRELESS_11B:
+		pbss_network->NetworkTypeInUse = Ndis802_11DS;
+		break;
+	case WIRELESS_11G:
+	case WIRELESS_11BG:
+	case WIRELESS_11G_24N:
+	case WIRELESS_11BG_24N:
+		pbss_network->NetworkTypeInUse = Ndis802_11OFDM24;
+		break;
+	case WIRELESS_11A:
+		pbss_network->NetworkTypeInUse = Ndis802_11OFDM5;
+		break;
+	default:
+		pbss_network->NetworkTypeInUse = Ndis802_11OFDM24;
+		break;
+	}
+
+	pmlmepriv->cur_network.network_type = network_type;
+
+#ifdef CONFIG_80211N_HT
+	pmlmepriv->htpriv.ht_option = _FALSE;
+
+	if ((psecuritypriv->wpa2_pairwise_cipher & WPA_CIPHER_TKIP) ||
+	    (psecuritypriv->wpa_pairwise_cipher & WPA_CIPHER_TKIP)) {
+		/* todo: */
+		/* ht_cap = _FALSE; */
+	}
+
+	/* ht_cap	 */
+	if (padapter->registrypriv.ht_enable &&
+		is_supported_ht(padapter->registrypriv.wireless_mode) && ht_cap == _TRUE) {
+
+		pmlmepriv->htpriv.ht_option = _TRUE;
+		pmlmepriv->qospriv.qos_option = 1;
+
+		pmlmepriv->htpriv.ampdu_enable = pregistrypriv->ampdu_enable ? _TRUE : _FALSE;
+
+		HT_caps_handler(padapter, (PNDIS_802_11_VARIABLE_IEs)pHT_caps_ie);
+
+		HT_info_handler(padapter, (PNDIS_802_11_VARIABLE_IEs)pHT_info_ie);
+	}
+#endif
+
+#ifdef CONFIG_80211AC_VHT
+	pmlmepriv->ori_vht_en = 0;
+	pmlmepriv->vhtpriv.vht_option = _FALSE;
+
+	if (pmlmepriv->htpriv.ht_option == _TRUE
+		&& pbss_network->Configuration.DSConfig > 14
+		&& REGSTY_IS_11AC_ENABLE(pregistrypriv)
+		&& is_supported_vht(pregistrypriv->wireless_mode)
+		&& (!rfctl->country_ent || COUNTRY_CHPLAN_EN_11AC(rfctl->country_ent))
+	) {
+		/* Parsing VHT CAP IE */
+		p = rtw_get_ie(ie + _BEACON_IE_OFFSET_, EID_VHTCapability, &ie_len, (pbss_network->IELength - _BEACON_IE_OFFSET_));
+		if (p && ie_len > 0)
+			vht_cap = _TRUE;
+
+		/* Parsing VHT OPERATION IE */
+
+		if (vht_cap == _TRUE
+			&& MLME_IS_MESH(padapter) /* allow only mesh temporarily before VHT IE checking is ready */
+		) {
+			rtw_check_for_vht20(padapter, ie + _BEACON_IE_OFFSET_, pbss_network->IELength - _BEACON_IE_OFFSET_);
+			pmlmepriv->ori_vht_en = 1;
+			pmlmepriv->vhtpriv.vht_option = _TRUE;
+		} else if (REGSTY_IS_11AC_AUTO(pregistrypriv)) {
+			rtw_vht_ies_detach(padapter, pbss_network);
+			rtw_vht_ies_attach(padapter, pbss_network);
+		}
+	}
+
+	if (pmlmepriv->vhtpriv.vht_option == _FALSE)
+		rtw_vht_ies_detach(padapter, pbss_network);
+#endif /* CONFIG_80211AC_VHT */
+
+#ifdef CONFIG_80211N_HT
+	if(padapter->registrypriv.ht_enable &&
+					is_supported_ht(padapter->registrypriv.wireless_mode) &&
+		pbss_network->Configuration.DSConfig <= 14 && padapter->registrypriv.wifi_spec == 1 &&
+		pbss_network->IELength + 10 <= MAX_IE_SZ) {
+		uint len = 0;
+
+		SET_EXT_CAPABILITY_ELE_BSS_COEXIST(pmlmepriv->ext_capab_ie_data, 1);
+		pmlmepriv->ext_capab_ie_len = 10;
+		rtw_set_ie(pbss_network->IEs + pbss_network->IELength, EID_EXTCapability, 8, pmlmepriv->ext_capab_ie_data, &len);
+		pbss_network->IELength += pmlmepriv->ext_capab_ie_len;
+	}
+#endif /* CONFIG_80211N_HT */
+
+	pbss_network->Length = get_WLAN_BSSID_EX_sz((WLAN_BSSID_EX *)pbss_network);
+
+	rtw_ies_get_chbw(pbss_network->IEs + _BEACON_IE_OFFSET_, pbss_network->IELength - _BEACON_IE_OFFSET_
+		, &pmlmepriv->ori_ch, &pmlmepriv->ori_bw, &pmlmepriv->ori_offset, 1, 1);
+	rtw_warn_on(pmlmepriv->ori_ch == 0);
+
+	{
+		/* alloc sta_info for ap itself */
+
+		struct sta_info *sta;
+
+		sta = rtw_get_stainfo(&padapter->stapriv, pbss_network->MacAddress);
+		if (!sta) {
+			sta = rtw_alloc_stainfo(&padapter->stapriv, pbss_network->MacAddress);
+			if (sta == NULL)
+				return _FAIL;
+		}
+	}
+
+	rtw_startbss_cmd(padapter, RTW_CMDF_WAIT_ACK);
+	{
+		int sk_band = RTW_GET_SCAN_BAND_SKIP(padapter);
+
+		if (sk_band)
+			RTW_CLR_SCAN_BAND_SKIP(padapter, sk_band);
+	}
+
+	rtw_indicate_connect(padapter);
+
+	pmlmepriv->cur_network.join_res = _TRUE;/* for check if already set beacon */
+
+	/* update bc/mc sta_info */
+	/* update_bmc_sta(padapter); */
+
+	return ret;
+
+}
+
+#if CONFIG_RTW_MACADDR_ACL
+void rtw_macaddr_acl_init(_adapter *adapter, u8 period)
+{
+	struct sta_priv *stapriv = &adapter->stapriv;
+	struct wlan_acl_pool *acl;
+	_queue *acl_node_q;
+	int i;
+	_irqL irqL;
+
+	if (period >= RTW_ACL_PERIOD_NUM) {
+		rtw_warn_on(1);
+		return;
+	}
+
+	acl = &stapriv->acl_list[period];
+	acl_node_q = &acl->acl_node_q;
+
+	_rtw_spinlock_init(&(acl_node_q->lock));
+
+	_enter_critical_bh(&(acl_node_q->lock), &irqL);
+	_rtw_init_listhead(&(acl_node_q->queue));
+	acl->num = 0;
+	acl->mode = RTW_ACL_MODE_DISABLED;
+	for (i = 0; i < NUM_ACL; i++) {
+		_rtw_init_listhead(&acl->aclnode[i].list);
+		acl->aclnode[i].valid = _FALSE;
+	}
+	_exit_critical_bh(&(acl_node_q->lock), &irqL);
+}
+
+static void _rtw_macaddr_acl_deinit(_adapter *adapter, u8 period, bool clear_only)
+{
+	struct sta_priv *stapriv = &adapter->stapriv;
+	struct wlan_acl_pool *acl;
+	_queue *acl_node_q;
+	_irqL irqL;
+	_list *head, *list;
+	struct rtw_wlan_acl_node *acl_node;
+
+	if (period >= RTW_ACL_PERIOD_NUM) {
+		rtw_warn_on(1);
+		return;
+	}
+
+	acl = &stapriv->acl_list[period];
+	acl_node_q = &acl->acl_node_q;
+
+	_enter_critical_bh(&(acl_node_q->lock), &irqL);
+	head = get_list_head(acl_node_q);
+	list = get_next(head);
+	while (rtw_end_of_queue_search(head, list) == _FALSE) {
+		acl_node = LIST_CONTAINOR(list, struct rtw_wlan_acl_node, list);
+		list = get_next(list);
+
+		if (acl_node->valid == _TRUE) {
+			acl_node->valid = _FALSE;
+			rtw_list_delete(&acl_node->list);
+			acl->num--;
+		}
+	}
+	_exit_critical_bh(&(acl_node_q->lock), &irqL);
+
+	if (!clear_only)
+		_rtw_spinlock_free(&(acl_node_q->lock));
+
+	rtw_warn_on(acl->num);
+	acl->mode = RTW_ACL_MODE_DISABLED;
+}
+
+void rtw_macaddr_acl_deinit(_adapter *adapter, u8 period)
+{
+	_rtw_macaddr_acl_deinit(adapter, period, 0);
+}
+
+void rtw_macaddr_acl_clear(_adapter *adapter, u8 period)
+{
+	_rtw_macaddr_acl_deinit(adapter, period, 1);
+}
+
+void rtw_set_macaddr_acl(_adapter *adapter, u8 period, int mode)
+{
+	struct sta_priv *stapriv = &adapter->stapriv;
+	struct wlan_acl_pool *acl;
+
+	if (period >= RTW_ACL_PERIOD_NUM) {
+		rtw_warn_on(1);
+		return;
+	}
+
+	acl = &stapriv->acl_list[period];
+
+	RTW_INFO(FUNC_ADPT_FMT" p=%u, mode=%d\n"
+		, FUNC_ADPT_ARG(adapter), period, mode);
+
+	acl->mode = mode;
+}
+
+int rtw_acl_add_sta(_adapter *adapter, u8 period, const u8 *addr)
+{
+	_irqL irqL;
+	_list *list, *head;
+	u8 existed = 0;
+	int i = -1, ret = 0;
+	struct rtw_wlan_acl_node *acl_node;
+	struct sta_priv *stapriv = &adapter->stapriv;
+	struct wlan_acl_pool *acl;
+	_queue *acl_node_q;
+
+	if (period >= RTW_ACL_PERIOD_NUM) {
+		rtw_warn_on(1);
+		ret = -1;
+		goto exit;
+	}
+
+	acl = &stapriv->acl_list[period];
+	acl_node_q = &acl->acl_node_q;
+
+	_enter_critical_bh(&(acl_node_q->lock), &irqL);
+
+	head = get_list_head(acl_node_q);
+	list = get_next(head);
+
+	/* search for existed entry */
+	while (rtw_end_of_queue_search(head, list) == _FALSE) {
+		acl_node = LIST_CONTAINOR(list, struct rtw_wlan_acl_node, list);
+		list = get_next(list);
+
+		if (_rtw_memcmp(acl_node->addr, addr, ETH_ALEN)) {
+			if (acl_node->valid == _TRUE) {
+				existed = 1;
+				break;
+			}
+		}
+	}
+	if (existed)
+		goto release_lock;
+
+	if (acl->num >= NUM_ACL)
+		goto release_lock;
+
+	/* find empty one and use */
+	for (i = 0; i < NUM_ACL; i++) {
+
+		acl_node = &acl->aclnode[i];
+		if (acl_node->valid == _FALSE) {
+
+			_rtw_init_listhead(&acl_node->list);
+			_rtw_memcpy(acl_node->addr, addr, ETH_ALEN);
+			acl_node->valid = _TRUE;
+
+			rtw_list_insert_tail(&acl_node->list, get_list_head(acl_node_q));
+			acl->num++;
+			break;
+		}
+	}
+
+release_lock:
+	_exit_critical_bh(&(acl_node_q->lock), &irqL);
+
+	if (!existed && (i < 0 || i >= NUM_ACL))
+		ret = -1;
+
+	RTW_INFO(FUNC_ADPT_FMT" p=%u "MAC_FMT" %s (acl_num=%d)\n"
+		 , FUNC_ADPT_ARG(adapter), period, MAC_ARG(addr)
+		, (existed ? "existed" : ((i < 0 || i >= NUM_ACL) ? "no room" : "added"))
+		 , acl->num);
+exit:
+	return ret;
+}
+
+int rtw_acl_remove_sta(_adapter *adapter, u8 period, const u8 *addr)
+{
+	_irqL irqL;
+	_list *list, *head;
+	int ret = 0;
+	struct rtw_wlan_acl_node *acl_node;
+	struct sta_priv *stapriv = &adapter->stapriv;
+	struct wlan_acl_pool *acl;
+	_queue	*acl_node_q;
+	u8 is_baddr = is_broadcast_mac_addr(addr);
+	u8 match = 0;
+
+	if (period >= RTW_ACL_PERIOD_NUM) {
+		rtw_warn_on(1);
+		goto exit;
+	}
+
+	acl = &stapriv->acl_list[period];
+	acl_node_q = &acl->acl_node_q;
+
+	_enter_critical_bh(&(acl_node_q->lock), &irqL);
+
+	head = get_list_head(acl_node_q);
+	list = get_next(head);
+
+	while (rtw_end_of_queue_search(head, list) == _FALSE) {
+		acl_node = LIST_CONTAINOR(list, struct rtw_wlan_acl_node, list);
+		list = get_next(list);
+
+		if (is_baddr || _rtw_memcmp(acl_node->addr, addr, ETH_ALEN)) {
+			if (acl_node->valid == _TRUE) {
+				acl_node->valid = _FALSE;
+				rtw_list_delete(&acl_node->list);
+				acl->num--;
+				match = 1;
+			}
+		}
+	}
+
+	_exit_critical_bh(&(acl_node_q->lock), &irqL);
+
+	RTW_INFO(FUNC_ADPT_FMT" p=%u "MAC_FMT" %s (acl_num=%d)\n"
+		 , FUNC_ADPT_ARG(adapter), period, MAC_ARG(addr)
+		 , is_baddr ? "clear all" : (match ? "match" : "no found")
+		 , acl->num);
+
+exit:
+	return ret;
+}
+#endif /* CONFIG_RTW_MACADDR_ACL */
+
+u8 rtw_ap_set_sta_key(_adapter *adapter, const u8 *addr, u8 alg, const u8 *key, u8 keyid, u8 gk)
+{
+	struct cmd_priv *cmdpriv = &adapter->cmdpriv;
+	struct cmd_obj *cmd;
+	struct set_stakey_parm *param;
+	u8	res = _SUCCESS;
+
+	cmd = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj));
+	if (cmd == NULL) {
+		res = _FAIL;
+		goto exit;
+	}
+
+	param = (struct set_stakey_parm *)rtw_zmalloc(sizeof(struct set_stakey_parm));
+	if (param == NULL) {
+		rtw_mfree((u8 *) cmd, sizeof(struct cmd_obj));
+		res = _FAIL;
+		goto exit;
+	}
+
+	init_h2fwcmd_w_parm_no_rsp(cmd, param, _SetStaKey_CMD_);
+
+	_rtw_memcpy(param->addr, addr, ETH_ALEN);
+	param->algorithm = alg;
+	param->keyid = keyid;
+	_rtw_memcpy(param->key, key, 16);
+	param->gk = gk;
+
+	res = rtw_enqueue_cmd(cmdpriv, cmd);
+
+exit:
+	return res;
+}
+
+u8 rtw_ap_set_pairwise_key(_adapter *padapter, struct sta_info *psta)
+{
+	return rtw_ap_set_sta_key(padapter
+		, psta->cmn.mac_addr
+		, psta->dot118021XPrivacy
+		, psta->dot118021x_UncstKey.skey
+		, 0
+		, 0
+	);
+}
+
+static int rtw_ap_set_key(_adapter *padapter, u8 *key, u8 alg, int keyid, u8 set_tx)
+{
+	u8 keylen;
+	struct cmd_obj *pcmd;
+	struct setkey_parm *psetkeyparm;
+	struct cmd_priv	*pcmdpriv = &(padapter->cmdpriv);
+	int res = _SUCCESS;
+
+	/* RTW_INFO("%s\n", __FUNCTION__); */
+
+	pcmd = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj));
+	if (pcmd == NULL) {
+		res = _FAIL;
+		goto exit;
+	}
+	psetkeyparm = (struct setkey_parm *)rtw_zmalloc(sizeof(struct setkey_parm));
+	if (psetkeyparm == NULL) {
+		rtw_mfree((unsigned char *)pcmd, sizeof(struct cmd_obj));
+		res = _FAIL;
+		goto exit;
+	}
+
+	_rtw_memset(psetkeyparm, 0, sizeof(struct setkey_parm));
+
+	psetkeyparm->keyid = (u8)keyid;
+	if (is_wep_enc(alg))
+		padapter->securitypriv.key_mask |= BIT(psetkeyparm->keyid);
+
+	psetkeyparm->algorithm = alg;
+
+	psetkeyparm->set_tx = set_tx;
+
+	switch (alg) {
+	case _WEP40_:
+		keylen = 5;
+		break;
+	case _WEP104_:
+		keylen = 13;
+		break;
+	case _TKIP_:
+	case _TKIP_WTMIC_:
+	case _AES_:
+	default:
+		keylen = 16;
+	}
+
+	_rtw_memcpy(&(psetkeyparm->key[0]), key, keylen);
+
+	pcmd->cmdcode = _SetKey_CMD_;
+	pcmd->parmbuf = (u8 *)psetkeyparm;
+	pcmd->cmdsz = (sizeof(struct setkey_parm));
+	pcmd->rsp = NULL;
+	pcmd->rspsz = 0;
+
+
+	_rtw_init_listhead(&pcmd->list);
+
+	res = rtw_enqueue_cmd(pcmdpriv, pcmd);
+
+exit:
+
+	return res;
+}
+
+int rtw_ap_set_group_key(_adapter *padapter, u8 *key, u8 alg, int keyid)
+{
+	RTW_INFO("%s\n", __FUNCTION__);
+
+	return rtw_ap_set_key(padapter, key, alg, keyid, 1);
+}
+
+int rtw_ap_set_wep_key(_adapter *padapter, u8 *key, u8 keylen, int keyid, u8 set_tx)
+{
+	u8 alg;
+
+	switch (keylen) {
+	case 5:
+		alg = _WEP40_;
+		break;
+	case 13:
+		alg = _WEP104_;
+		break;
+	default:
+		alg = _NO_PRIVACY_;
+	}
+
+	RTW_INFO("%s\n", __FUNCTION__);
+
+	return rtw_ap_set_key(padapter, key, alg, keyid, set_tx);
+}
+
+u8 rtw_ap_bmc_frames_hdl(_adapter *padapter)
+{
+#define HIQ_XMIT_COUNTS (6)
+	_irqL irqL;
+	struct sta_info *psta_bmc;
+	_list	*xmitframe_plist, *xmitframe_phead;
+	struct xmit_frame *pxmitframe = NULL;
+	struct xmit_priv *pxmitpriv = &padapter->xmitpriv;
+	struct sta_priv  *pstapriv = &padapter->stapriv;
+	bool update_tim = _FALSE;
+
+
+	if (padapter->registrypriv.wifi_spec != 1)
+		return H2C_SUCCESS;
+
+
+	psta_bmc = rtw_get_bcmc_stainfo(padapter);
+	if (!psta_bmc)
+		return H2C_SUCCESS;
+
+
+	_enter_critical_bh(&pxmitpriv->lock, &irqL);
+
+	if ((rtw_tim_map_is_set(padapter, pstapriv->tim_bitmap, 0)) && (psta_bmc->sleepq_len > 0)) {
+		int tx_counts = 0;
+
+		_update_beacon(padapter, _TIM_IE_, NULL, _FALSE, "update TIM with TIB=1");
+
+		RTW_INFO("sleepq_len of bmc_sta = %d\n", psta_bmc->sleepq_len);
+
+		xmitframe_phead = get_list_head(&psta_bmc->sleep_q);
+		xmitframe_plist = get_next(xmitframe_phead);
+
+		while ((rtw_end_of_queue_search(xmitframe_phead, xmitframe_plist)) == _FALSE) {
+			pxmitframe = LIST_CONTAINOR(xmitframe_plist, struct xmit_frame, list);
+
+			xmitframe_plist = get_next(xmitframe_plist);
+
+			rtw_list_delete(&pxmitframe->list);
+
+			psta_bmc->sleepq_len--;
+			tx_counts++;
+
+			if (psta_bmc->sleepq_len > 0)
+				pxmitframe->attrib.mdata = 1;
+			else
+				pxmitframe->attrib.mdata = 0;
+
+			if (tx_counts == HIQ_XMIT_COUNTS)
+				pxmitframe->attrib.mdata = 0;
+
+			pxmitframe->attrib.triggered = 1;
+
+			if (xmitframe_hiq_filter(pxmitframe) == _TRUE)
+				pxmitframe->attrib.qsel = QSLT_HIGH;/*HIQ*/
+
+			rtw_hal_xmitframe_enqueue(padapter, pxmitframe);
+
+			if (tx_counts == HIQ_XMIT_COUNTS)
+				break;
+
+		}
+
+	} else {
+		if (psta_bmc->sleepq_len == 0) {
+
+			/*RTW_INFO("sleepq_len of bmc_sta = %d\n", psta_bmc->sleepq_len);*/
+
+			if (rtw_tim_map_is_set(padapter, pstapriv->tim_bitmap, 0))
+				update_tim = _TRUE;
+
+			rtw_tim_map_clear(padapter, pstapriv->tim_bitmap, 0);
+			rtw_tim_map_clear(padapter, pstapriv->sta_dz_bitmap, 0);
+
+			if (update_tim == _TRUE) {
+				RTW_INFO("clear TIB\n");
+				_update_beacon(padapter, _TIM_IE_, NULL, _TRUE, "bmc sleepq and HIQ empty");
+			}
+		}
+	}
+
+	_exit_critical_bh(&pxmitpriv->lock, &irqL);
+
+#if 0
+	/* HIQ Check */
+	rtw_hal_get_hwreg(padapter, HW_VAR_CHK_HI_QUEUE_EMPTY, &empty);
+
+	while (_FALSE == empty && rtw_get_passing_time_ms(start) < 3000) {
+		rtw_msleep_os(100);
+		rtw_hal_get_hwreg(padapter, HW_VAR_CHK_HI_QUEUE_EMPTY, &empty);
+	}
+
+
+	printk("check if hiq empty=%d\n", empty);
+#endif
+
+	return H2C_SUCCESS;
+}
+
+#ifdef CONFIG_NATIVEAP_MLME
+
+static void associated_stainfo_update(_adapter *padapter, struct sta_info *psta, u32 sta_info_type)
+{
+	struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
+
+	RTW_INFO("%s: "MAC_FMT", updated_type=0x%x\n", __func__, MAC_ARG(psta->cmn.mac_addr), sta_info_type);
+#ifdef CONFIG_80211N_HT
+	if (sta_info_type & STA_INFO_UPDATE_BW) {
+
+		if ((psta->flags & WLAN_STA_HT) && !psta->ht_20mhz_set) {
+			if (pmlmepriv->sw_to_20mhz) {
+				psta->cmn.bw_mode = CHANNEL_WIDTH_20;
+				/*psta->htpriv.ch_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE;*/
+				psta->htpriv.sgi_40m = _FALSE;
+			} else {
+				/*TODO: Switch back to 40MHZ?80MHZ*/
+			}
+		}
+	}
+#endif /* CONFIG_80211N_HT */
+	/*
+		if (sta_info_type & STA_INFO_UPDATE_RATE) {
+
+		}
+	*/
+
+	if (sta_info_type & STA_INFO_UPDATE_PROTECTION_MODE)
+		VCS_update(padapter, psta);
+
+	/*
+		if (sta_info_type & STA_INFO_UPDATE_CAP) {
+
+		}
+
+		if (sta_info_type & STA_INFO_UPDATE_HT_CAP) {
+
+		}
+
+		if (sta_info_type & STA_INFO_UPDATE_VHT_CAP) {
+
+		}
+	*/
+
+}
+
+static void update_bcn_ext_capab_ie(_adapter *padapter)
+{
+	sint ie_len = 0;
+	unsigned char	*pbuf;
+	struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
+	struct mlme_ext_priv	*pmlmeext = &(padapter->mlmeextpriv);
+	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
+	WLAN_BSSID_EX *pnetwork = &(pmlmeinfo->network);
+	u8 *ie = pnetwork->IEs;
+	u8 null_extcap_data[8] = {0};
+
+	pbuf = rtw_get_ie(ie + _BEACON_IE_OFFSET_, _EXT_CAP_IE_, &ie_len, (pnetwork->IELength - _BEACON_IE_OFFSET_));
+	if (pbuf && ie_len > 0)
+		rtw_remove_bcn_ie(padapter, pnetwork, _EXT_CAP_IE_);
+
+	if ((pmlmepriv->ext_capab_ie_len > 0) &&
+	    (_rtw_memcmp(pmlmepriv->ext_capab_ie_data, null_extcap_data, sizeof(null_extcap_data)) == _FALSE))
+		rtw_add_bcn_ie(padapter, pnetwork, _EXT_CAP_IE_, pmlmepriv->ext_capab_ie_data, pmlmepriv->ext_capab_ie_len);
+
+}
+
+static void update_bcn_erpinfo_ie(_adapter *padapter)
+{
+	struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
+	struct mlme_ext_priv	*pmlmeext = &(padapter->mlmeextpriv);
+	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
+	WLAN_BSSID_EX *pnetwork = &(pmlmeinfo->network);
+	unsigned char *p, *ie = pnetwork->IEs;
+	u32 len = 0;
+
+	RTW_INFO("%s, ERP_enable=%d\n", __FUNCTION__, pmlmeinfo->ERP_enable);
+
+	if (!pmlmeinfo->ERP_enable)
+		return;
+
+	/* parsing ERP_IE */
+	p = rtw_get_ie(ie + _BEACON_IE_OFFSET_, _ERPINFO_IE_, &len, (pnetwork->IELength - _BEACON_IE_OFFSET_));
+	if (p && len > 0) {
+		PNDIS_802_11_VARIABLE_IEs pIE = (PNDIS_802_11_VARIABLE_IEs)p;
+
+		if (pmlmepriv->num_sta_non_erp == 1)
+			pIE->data[0] |= RTW_ERP_INFO_NON_ERP_PRESENT | RTW_ERP_INFO_USE_PROTECTION;
+		else
+			pIE->data[0] &= ~(RTW_ERP_INFO_NON_ERP_PRESENT | RTW_ERP_INFO_USE_PROTECTION);
+
+		if (pmlmepriv->num_sta_no_short_preamble > 0)
+			pIE->data[0] |= RTW_ERP_INFO_BARKER_PREAMBLE_MODE;
+		else
+			pIE->data[0] &= ~(RTW_ERP_INFO_BARKER_PREAMBLE_MODE);
+
+		ERP_IE_handler(padapter, pIE);
+	}
+
+}
+
+static void update_bcn_htcap_ie(_adapter *padapter)
+{
+	RTW_INFO("%s\n", __FUNCTION__);
+
+}
+
+static void update_bcn_htinfo_ie(_adapter *padapter)
+{
+#ifdef CONFIG_80211N_HT
+	/*
+	u8 beacon_updated = _FALSE;
+	u32 sta_info_update_type = STA_INFO_UPDATE_NONE;
+	*/
+	struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
+	struct mlme_ext_priv	*pmlmeext = &(padapter->mlmeextpriv);
+	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
+	WLAN_BSSID_EX *pnetwork = &(pmlmeinfo->network);
+	unsigned char *p, *ie = pnetwork->IEs;
+	u32 len = 0;
+
+	if (pmlmepriv->htpriv.ht_option == _FALSE)
+		return;
+
+	if (pmlmeinfo->HT_info_enable != 1)
+		return;
+
+
+	RTW_INFO("%s current operation mode=0x%X\n",
+		 __FUNCTION__, pmlmepriv->ht_op_mode);
+
+	RTW_INFO("num_sta_40mhz_intolerant(%d), 20mhz_width_req(%d), intolerant_ch_rpt(%d), olbc(%d)\n",
+		pmlmepriv->num_sta_40mhz_intolerant, pmlmepriv->ht_20mhz_width_req, pmlmepriv->ht_intolerant_ch_reported, ATOMIC_READ(&pmlmepriv->olbc));
+
+	/*parsing HT_INFO_IE, currently only update ht_op_mode - pht_info->infos[1] & pht_info->infos[2] for wifi logo test*/
+	p = rtw_get_ie(ie + _BEACON_IE_OFFSET_, _HT_ADD_INFO_IE_, &len, (pnetwork->IELength - _BEACON_IE_OFFSET_));
+	if (p && len > 0) {
+		struct HT_info_element *pht_info = NULL;
+
+		pht_info = (struct HT_info_element *)(p + 2);
+
+		/* for STA Channel Width/Secondary Channel Offset*/
+		if ((pmlmepriv->sw_to_20mhz == 0) && (pmlmeext->cur_channel <= 14)) {
+			if ((pmlmepriv->num_sta_40mhz_intolerant > 0) || (pmlmepriv->ht_20mhz_width_req == _TRUE)
+			    || (pmlmepriv->ht_intolerant_ch_reported == _TRUE) || (ATOMIC_READ(&pmlmepriv->olbc) == _TRUE)) {
+				SET_HT_OP_ELE_2ND_CHL_OFFSET(pht_info, 0);
+				SET_HT_OP_ELE_STA_CHL_WIDTH(pht_info, 0);
+
+				pmlmepriv->sw_to_20mhz = 1;
+				/*
+				sta_info_update_type |= STA_INFO_UPDATE_BW;
+				beacon_updated = _TRUE;
+				*/
+
+				RTW_INFO("%s:switching to 20Mhz\n", __FUNCTION__);
+
+				/*TODO : cur_bwmode/cur_ch_offset switches to 20Mhz*/
+			}
+		} else {
+
+			if ((pmlmepriv->num_sta_40mhz_intolerant == 0) && (pmlmepriv->ht_20mhz_width_req == _FALSE)
+			    && (pmlmepriv->ht_intolerant_ch_reported == _FALSE) && (ATOMIC_READ(&pmlmepriv->olbc) == _FALSE)) {
+
+				if (pmlmeext->cur_bwmode >= CHANNEL_WIDTH_40) {
+
+					SET_HT_OP_ELE_STA_CHL_WIDTH(pht_info, 1);
+
+					SET_HT_OP_ELE_2ND_CHL_OFFSET(pht_info,
+						(pmlmeext->cur_ch_offset == HAL_PRIME_CHNL_OFFSET_LOWER) ?
+						HT_INFO_HT_PARAM_SECONDARY_CHNL_ABOVE : HT_INFO_HT_PARAM_SECONDARY_CHNL_BELOW);
+
+					pmlmepriv->sw_to_20mhz = 0;
+					/*
+					sta_info_update_type |= STA_INFO_UPDATE_BW;
+					beacon_updated = _TRUE;
+					*/
+
+					RTW_INFO("%s:switching back to 40Mhz\n", __FUNCTION__);
+				}
+			}
+		}
+
+		/* to update  ht_op_mode*/
+		*(u16 *)(pht_info->infos + 1) = cpu_to_le16(pmlmepriv->ht_op_mode);
+
+	}
+
+	/*associated_clients_update(padapter, beacon_updated, sta_info_update_type);*/
+#endif /* CONFIG_80211N_HT */
+}
+
+static void update_bcn_rsn_ie(_adapter *padapter)
+{
+	RTW_INFO("%s\n", __FUNCTION__);
+
+}
+
+static void update_bcn_wpa_ie(_adapter *padapter)
+{
+	RTW_INFO("%s\n", __FUNCTION__);
+
+}
+
+static void update_bcn_wmm_ie(_adapter *padapter)
+{
+	RTW_INFO("%s\n", __FUNCTION__);
+
+}
+
+static void update_bcn_wps_ie(_adapter *padapter)
+{
+	u8 *pwps_ie = NULL, *pwps_ie_src, *premainder_ie, *pbackup_remainder_ie = NULL;
+	uint wps_ielen = 0, wps_offset, remainder_ielen;
+	struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
+	struct mlme_ext_priv	*pmlmeext = &(padapter->mlmeextpriv);
+	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
+	WLAN_BSSID_EX *pnetwork = &(pmlmeinfo->network);
+	unsigned char *ie = pnetwork->IEs;
+	u32 ielen = pnetwork->IELength;
+
+
+	RTW_INFO("%s\n", __FUNCTION__);
+
+	pwps_ie = rtw_get_wps_ie(ie + _FIXED_IE_LENGTH_, ielen - _FIXED_IE_LENGTH_, NULL, &wps_ielen);
+
+	if (pwps_ie == NULL || wps_ielen == 0)
+		return;
+
+	pwps_ie_src = pmlmepriv->wps_beacon_ie;
+	if (pwps_ie_src == NULL)
+		return;
+
+	wps_offset = (uint)(pwps_ie - ie);
+
+	premainder_ie = pwps_ie + wps_ielen;
+
+	remainder_ielen = ielen - wps_offset - wps_ielen;
+
+	if (remainder_ielen > 0) {
+		pbackup_remainder_ie = rtw_malloc(remainder_ielen);
+		if (pbackup_remainder_ie)
+			_rtw_memcpy(pbackup_remainder_ie, premainder_ie, remainder_ielen);
+	}
+
+	wps_ielen = (uint)pwps_ie_src[1];/* to get ie data len */
+	if ((wps_offset + wps_ielen + 2 + remainder_ielen) <= MAX_IE_SZ) {
+		_rtw_memcpy(pwps_ie, pwps_ie_src, wps_ielen + 2);
+		pwps_ie += (wps_ielen + 2);
+
+		if (pbackup_remainder_ie)
+			_rtw_memcpy(pwps_ie, pbackup_remainder_ie, remainder_ielen);
+
+		/* update IELength */
+		pnetwork->IELength = wps_offset + (wps_ielen + 2) + remainder_ielen;
+	}
+
+	if (pbackup_remainder_ie)
+		rtw_mfree(pbackup_remainder_ie, remainder_ielen);
+
+	/* deal with the case without set_tx_beacon_cmd() in update_beacon() */
+#if defined(CONFIG_INTERRUPT_BASED_TXBCN) || defined(CONFIG_PCI_HCI)
+	if ((pmlmeinfo->state & 0x03) == WIFI_FW_AP_STATE) {
+		u8 sr = 0;
+		rtw_get_wps_attr_content(pwps_ie_src,  wps_ielen, WPS_ATTR_SELECTED_REGISTRAR, (u8 *)(&sr), NULL);
+
+		if (sr) {
+			set_fwstate(pmlmepriv, WIFI_UNDER_WPS);
+			RTW_INFO("%s, set WIFI_UNDER_WPS\n", __func__);
+		} else {
+			clr_fwstate(pmlmepriv, WIFI_UNDER_WPS);
+			RTW_INFO("%s, clr WIFI_UNDER_WPS\n", __func__);
+		}
+	}
+#endif
+}
+
+static void update_bcn_p2p_ie(_adapter *padapter)
+{
+
+}
+
+static void update_bcn_vendor_spec_ie(_adapter *padapter, u8 *oui)
+{
+	RTW_INFO("%s\n", __FUNCTION__);
+
+	if (_rtw_memcmp(RTW_WPA_OUI, oui, 4))
+		update_bcn_wpa_ie(padapter);
+	else if (_rtw_memcmp(WMM_OUI, oui, 4))
+		update_bcn_wmm_ie(padapter);
+	else if (_rtw_memcmp(WPS_OUI, oui, 4))
+		update_bcn_wps_ie(padapter);
+	else if (_rtw_memcmp(P2P_OUI, oui, 4))
+		update_bcn_p2p_ie(padapter);
+	else
+		RTW_INFO("unknown OUI type!\n");
+
+
+}
+
+void _update_beacon(_adapter *padapter, u8 ie_id, u8 *oui, u8 tx, const char *tag)
+{
+	_irqL irqL;
+	struct mlme_priv *pmlmepriv;
+	struct mlme_ext_priv *pmlmeext;
+	bool updated = 1; /* treat as upadated by default */
+
+	if (!padapter)
+		return;
+
+	pmlmepriv = &(padapter->mlmepriv);
+	pmlmeext = &(padapter->mlmeextpriv);
+
+	if (pmlmeext->bstart_bss == _FALSE)
+		return;
+
+	_enter_critical_bh(&pmlmepriv->bcn_update_lock, &irqL);
+
+	switch (ie_id) {
+	case _TIM_IE_:
+		update_BCNTIM(padapter);
+		break;
+
+	case _ERPINFO_IE_:
+		update_bcn_erpinfo_ie(padapter);
+		break;
+
+	case _HT_CAPABILITY_IE_:
+		update_bcn_htcap_ie(padapter);
+		break;
+
+	case _RSN_IE_2_:
+		update_bcn_rsn_ie(padapter);
+		break;
+
+	case _HT_ADD_INFO_IE_:
+		update_bcn_htinfo_ie(padapter);
+		break;
+
+	case _EXT_CAP_IE_:
+		update_bcn_ext_capab_ie(padapter);
+		break;
+
+#ifdef CONFIG_RTW_MESH
+	case WLAN_EID_MESH_CONFIG:
+		updated = rtw_mesh_update_bss_peering_status(padapter, &(pmlmeext->mlmext_info.network));
+		updated |= rtw_mesh_update_bss_formation_info(padapter, &(pmlmeext->mlmext_info.network));
+		updated |= rtw_mesh_update_bss_forwarding_state(padapter, &(pmlmeext->mlmext_info.network));
+		break;
+#endif
+
+	case _VENDOR_SPECIFIC_IE_:
+		update_bcn_vendor_spec_ie(padapter, oui);
+		break;
+
+	case 0xFF:
+	default:
+		break;
+	}
+
+	if (updated)
+		pmlmepriv->update_bcn = _TRUE;
+
+	_exit_critical_bh(&pmlmepriv->bcn_update_lock, &irqL);
+
+#ifndef CONFIG_INTERRUPT_BASED_TXBCN
+#if defined(CONFIG_USB_HCI) || defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
+	if (tx && updated) {
+		/* send_beacon(padapter); */ /* send_beacon must execute on TSR level */
+		if (0)
+			RTW_INFO(FUNC_ADPT_FMT" ie_id:%u - %s\n", FUNC_ADPT_ARG(padapter), ie_id, tag);
+		set_tx_beacon_cmd(padapter);
+	}
+#else
+	{
+		/* PCI will issue beacon when BCN interrupt occurs.		 */
+	}
+#endif
+#endif /* !CONFIG_INTERRUPT_BASED_TXBCN */
+}
+
+#ifdef CONFIG_80211N_HT
+
+void rtw_process_public_act_bsscoex(_adapter *padapter, u8 *pframe, uint frame_len)
+{
+	struct sta_info *psta;
+	struct sta_priv *pstapriv = &padapter->stapriv;
+	u8 beacon_updated = _FALSE;
+	struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
+	u8 *frame_body = pframe + sizeof(struct rtw_ieee80211_hdr_3addr);
+	uint frame_body_len = frame_len - sizeof(struct rtw_ieee80211_hdr_3addr);
+	u8 category, action;
+
+	psta = rtw_get_stainfo(pstapriv, get_addr2_ptr(pframe));
+	if (psta == NULL)
+		return;
+
+
+	category = frame_body[0];
+	action = frame_body[1];
+
+	if (frame_body_len > 0) {
+		if ((frame_body[2] == EID_BSSCoexistence) && (frame_body[3] > 0)) {
+			u8 ie_data = frame_body[4];
+
+			if (ie_data & RTW_WLAN_20_40_BSS_COEX_40MHZ_INTOL) {
+				if (psta->ht_40mhz_intolerant == 0) {
+					psta->ht_40mhz_intolerant = 1;
+					pmlmepriv->num_sta_40mhz_intolerant++;
+					beacon_updated = _TRUE;
+				}
+			} else if (ie_data & RTW_WLAN_20_40_BSS_COEX_20MHZ_WIDTH_REQ)	{
+				if (pmlmepriv->ht_20mhz_width_req == _FALSE) {
+					pmlmepriv->ht_20mhz_width_req = _TRUE;
+					beacon_updated = _TRUE;
+				}
+			} else
+				beacon_updated = _FALSE;
+		}
+	}
+
+	if (frame_body_len > 8) {
+		/* if EID_BSSIntolerantChlReport ie exists */
+		if ((frame_body[5] == EID_BSSIntolerantChlReport) && (frame_body[6] > 0)) {
+			/*todo:*/
+			if (pmlmepriv->ht_intolerant_ch_reported == _FALSE) {
+				pmlmepriv->ht_intolerant_ch_reported = _TRUE;
+				beacon_updated = _TRUE;
+			}
+		}
+	}
+
+	if (beacon_updated) {
+
+		update_beacon(padapter, _HT_ADD_INFO_IE_, NULL, _TRUE);
+
+		associated_stainfo_update(padapter, psta, STA_INFO_UPDATE_BW);
+	}
+
+
+
+}
+
+void rtw_process_ht_action_smps(_adapter *padapter, u8 *ta, u8 ctrl_field)
+{
+	u8 e_field, m_field;
+	struct sta_info *psta;
+	struct sta_priv *pstapriv = &padapter->stapriv;
+
+	psta = rtw_get_stainfo(pstapriv, ta);
+	if (psta == NULL)
+		return;
+
+	e_field = (ctrl_field & BIT(0)) ? 1 : 0;
+	m_field = (ctrl_field & BIT(1)) ? 1 : 0;
+
+	if (e_field) {
+
+		/* enable */
+		/* 0:static SMPS, 1:dynamic SMPS, 3:SMPS disabled, 2:reserved*/
+
+		if (m_field) /*mode*/
+			psta->htpriv.smps_cap = 1;
+		else
+			psta->htpriv.smps_cap = 0;
+	} else {
+		/*disable*/
+		psta->htpriv.smps_cap = 3;
+	}
+
+	rtw_dm_ra_mask_wk_cmd(padapter, (u8 *)psta);
+
+}
+
+/*
+op_mode
+Set to 0 (HT pure) under the followign conditions
+	- all STAs in the BSS are 20/40 MHz HT in 20/40 MHz BSS or
+	- all STAs in the BSS are 20 MHz HT in 20 MHz BSS
+Set to 1 (HT non-member protection) if there may be non-HT STAs
+	in both the primary and the secondary channel
+Set to 2 if only HT STAs are associated in BSS,
+	however and at least one 20 MHz HT STA is associated
+Set to 3 (HT mixed mode) when one or more non-HT STAs are associated
+	(currently non-GF HT station is considered as non-HT STA also)
+*/
+int rtw_ht_operation_update(_adapter *padapter)
+{
+	u16 cur_op_mode, new_op_mode;
+	int op_mode_changes = 0;
+	struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
+	struct ht_priv	*phtpriv_ap = &pmlmepriv->htpriv;
+
+	if (pmlmepriv->htpriv.ht_option == _FALSE)
+		return 0;
+
+	/*if (!iface->conf->ieee80211n || iface->conf->ht_op_mode_fixed)
+		return 0;*/
+
+	RTW_INFO("%s current operation mode=0x%X\n",
+		 __FUNCTION__, pmlmepriv->ht_op_mode);
+
+	if (!(pmlmepriv->ht_op_mode & HT_INFO_OPERATION_MODE_NON_GF_DEVS_PRESENT)
+	    && pmlmepriv->num_sta_ht_no_gf) {
+		pmlmepriv->ht_op_mode |=
+			HT_INFO_OPERATION_MODE_NON_GF_DEVS_PRESENT;
+		op_mode_changes++;
+	} else if ((pmlmepriv->ht_op_mode &
+		    HT_INFO_OPERATION_MODE_NON_GF_DEVS_PRESENT) &&
+		   pmlmepriv->num_sta_ht_no_gf == 0) {
+		pmlmepriv->ht_op_mode &=
+			~HT_INFO_OPERATION_MODE_NON_GF_DEVS_PRESENT;
+		op_mode_changes++;
+	}
+
+	if (!(pmlmepriv->ht_op_mode & HT_INFO_OPERATION_MODE_NON_HT_STA_PRESENT) &&
+	    (pmlmepriv->num_sta_no_ht || ATOMIC_READ(&pmlmepriv->olbc_ht))) {
+		pmlmepriv->ht_op_mode |= HT_INFO_OPERATION_MODE_NON_HT_STA_PRESENT;
+		op_mode_changes++;
+	} else if ((pmlmepriv->ht_op_mode &
+		    HT_INFO_OPERATION_MODE_NON_HT_STA_PRESENT) &&
+		   (pmlmepriv->num_sta_no_ht == 0 && !ATOMIC_READ(&pmlmepriv->olbc_ht))) {
+		pmlmepriv->ht_op_mode &=
+			~HT_INFO_OPERATION_MODE_NON_HT_STA_PRESENT;
+		op_mode_changes++;
+	}
+
+	/* Note: currently we switch to the MIXED op mode if HT non-greenfield
+	 * station is associated. Probably it's a theoretical case, since
+	 * it looks like all known HT STAs support greenfield.
+	 */
+	new_op_mode = 0;
+	if (pmlmepriv->num_sta_no_ht /*||
+	    (pmlmepriv->ht_op_mode & HT_INFO_OPERATION_MODE_NON_GF_DEVS_PRESENT)*/)
+		new_op_mode = OP_MODE_MIXED;
+	else if ((phtpriv_ap->ht_cap.cap_info & IEEE80211_HT_CAP_SUP_WIDTH)
+		 && pmlmepriv->num_sta_ht_20mhz)
+		new_op_mode = OP_MODE_20MHZ_HT_STA_ASSOCED;
+	else if (ATOMIC_READ(&pmlmepriv->olbc_ht))
+		new_op_mode = OP_MODE_MAY_BE_LEGACY_STAS;
+	else
+		new_op_mode = OP_MODE_PURE;
+
+	cur_op_mode = pmlmepriv->ht_op_mode & HT_INFO_OPERATION_MODE_OP_MODE_MASK;
+	if (cur_op_mode != new_op_mode) {
+		pmlmepriv->ht_op_mode &= ~HT_INFO_OPERATION_MODE_OP_MODE_MASK;
+		pmlmepriv->ht_op_mode |= new_op_mode;
+		op_mode_changes++;
+	}
+
+	RTW_INFO("%s new operation mode=0x%X changes=%d\n",
+		 __FUNCTION__, pmlmepriv->ht_op_mode, op_mode_changes);
+
+	return op_mode_changes;
+
+}
+
+#endif /* CONFIG_80211N_HT */
+
+void associated_clients_update(_adapter *padapter, u8 updated, u32 sta_info_type)
+{
+	/* update associcated stations cap. */
+	if (updated == _TRUE) {
+		_irqL irqL;
+		_list	*phead, *plist;
+		struct sta_info *psta = NULL;
+		struct sta_priv *pstapriv = &padapter->stapriv;
+
+		_enter_critical_bh(&pstapriv->asoc_list_lock, &irqL);
+
+		phead = &pstapriv->asoc_list;
+		plist = get_next(phead);
+
+		/* check asoc_queue */
+		while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) {
+			psta = LIST_CONTAINOR(plist, struct sta_info, asoc_list);
+
+			plist = get_next(plist);
+
+			associated_stainfo_update(padapter, psta, sta_info_type);
+		}
+
+		_exit_critical_bh(&pstapriv->asoc_list_lock, &irqL);
+
+	}
+
+}
+
+/* called > TSR LEVEL for USB or SDIO Interface*/
+void bss_cap_update_on_sta_join(_adapter *padapter, struct sta_info *psta)
+{
+	u8 beacon_updated = _FALSE;
+	struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
+	struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv);
+
+
+#if 0
+	if (!(psta->capability & WLAN_CAPABILITY_SHORT_PREAMBLE) &&
+	    !psta->no_short_preamble_set) {
+		psta->no_short_preamble_set = 1;
+		pmlmepriv->num_sta_no_short_preamble++;
+		if ((pmlmeext->cur_wireless_mode > WIRELESS_11B) &&
+		    (pmlmepriv->num_sta_no_short_preamble == 1))
+			ieee802_11_set_beacons(hapd->iface);
+	}
+#endif
+
+
+	if (!(psta->flags & WLAN_STA_SHORT_PREAMBLE)) {
+		if (!psta->no_short_preamble_set) {
+			psta->no_short_preamble_set = 1;
+
+			pmlmepriv->num_sta_no_short_preamble++;
+
+			if ((pmlmeext->cur_wireless_mode > WIRELESS_11B) &&
+			    (pmlmepriv->num_sta_no_short_preamble == 1))
+				beacon_updated = _TRUE;
+		}
+	} else {
+		if (psta->no_short_preamble_set) {
+			psta->no_short_preamble_set = 0;
+
+			pmlmepriv->num_sta_no_short_preamble--;
+
+			if ((pmlmeext->cur_wireless_mode > WIRELESS_11B) &&
+			    (pmlmepriv->num_sta_no_short_preamble == 0))
+				beacon_updated = _TRUE;
+		}
+	}
+
+#if 0
+	if (psta->flags & WLAN_STA_NONERP && !psta->nonerp_set) {
+		psta->nonerp_set = 1;
+		pmlmepriv->num_sta_non_erp++;
+		if (pmlmepriv->num_sta_non_erp == 1)
+			ieee802_11_set_beacons(hapd->iface);
+	}
+#endif
+
+	if (psta->flags & WLAN_STA_NONERP) {
+		if (!psta->nonerp_set) {
+			psta->nonerp_set = 1;
+
+			pmlmepriv->num_sta_non_erp++;
+
+			if (pmlmepriv->num_sta_non_erp == 1) {
+				beacon_updated = _TRUE;
+				update_beacon(padapter, _ERPINFO_IE_, NULL, _FALSE);
+			}
+		}
+
+	} else {
+		if (psta->nonerp_set) {
+			psta->nonerp_set = 0;
+
+			pmlmepriv->num_sta_non_erp--;
+
+			if (pmlmepriv->num_sta_non_erp == 0) {
+				beacon_updated = _TRUE;
+				update_beacon(padapter, _ERPINFO_IE_, NULL, _FALSE);
+			}
+		}
+
+	}
+
+
+#if 0
+	if (!(psta->capability & WLAN_CAPABILITY_SHORT_SLOT) &&
+	    !psta->no_short_slot_time_set) {
+		psta->no_short_slot_time_set = 1;
+		pmlmepriv->num_sta_no_short_slot_time++;
+		if ((pmlmeext->cur_wireless_mode > WIRELESS_11B) &&
+		    (pmlmepriv->num_sta_no_short_slot_time == 1))
+			ieee802_11_set_beacons(hapd->iface);
+	}
+#endif
+
+	if (!(psta->capability & WLAN_CAPABILITY_SHORT_SLOT)) {
+		if (!psta->no_short_slot_time_set) {
+			psta->no_short_slot_time_set = 1;
+
+			pmlmepriv->num_sta_no_short_slot_time++;
+
+			if ((pmlmeext->cur_wireless_mode > WIRELESS_11B) &&
+			    (pmlmepriv->num_sta_no_short_slot_time == 1))
+				beacon_updated = _TRUE;
+		}
+	} else {
+		if (psta->no_short_slot_time_set) {
+			psta->no_short_slot_time_set = 0;
+
+			pmlmepriv->num_sta_no_short_slot_time--;
+
+			if ((pmlmeext->cur_wireless_mode > WIRELESS_11B) &&
+			    (pmlmepriv->num_sta_no_short_slot_time == 0))
+				beacon_updated = _TRUE;
+		}
+	}
+
+#ifdef CONFIG_80211N_HT
+	if(padapter->registrypriv.ht_enable &&
+		is_supported_ht(padapter->registrypriv.wireless_mode)) {
+		if (psta->flags & WLAN_STA_HT) {
+			u16 ht_capab = le16_to_cpu(psta->htpriv.ht_cap.cap_info);
+
+			RTW_INFO("HT: STA " MAC_FMT " HT Capabilities Info: 0x%04x\n",
+				MAC_ARG(psta->cmn.mac_addr), ht_capab);
+
+			if (psta->no_ht_set) {
+				psta->no_ht_set = 0;
+				pmlmepriv->num_sta_no_ht--;
+			}
+
+			if ((ht_capab & IEEE80211_HT_CAP_GRN_FLD) == 0) {
+				if (!psta->no_ht_gf_set) {
+					psta->no_ht_gf_set = 1;
+					pmlmepriv->num_sta_ht_no_gf++;
+				}
+				RTW_INFO("%s STA " MAC_FMT " - no "
+					 "greenfield, num of non-gf stations %d\n",
+					 __FUNCTION__, MAC_ARG(psta->cmn.mac_addr),
+					 pmlmepriv->num_sta_ht_no_gf);
+			}
+
+			if ((ht_capab & IEEE80211_HT_CAP_SUP_WIDTH) == 0) {
+				if (!psta->ht_20mhz_set) {
+					psta->ht_20mhz_set = 1;
+					pmlmepriv->num_sta_ht_20mhz++;
+				}
+				RTW_INFO("%s STA " MAC_FMT " - 20 MHz HT, "
+					 "num of 20MHz HT STAs %d\n",
+					 __FUNCTION__, MAC_ARG(psta->cmn.mac_addr),
+					 pmlmepriv->num_sta_ht_20mhz);
+			}
+
+			if (((ht_capab & RTW_IEEE80211_HT_CAP_40MHZ_INTOLERANT) != 0) &&
+				(psta->ht_40mhz_intolerant == 0)) {
+				psta->ht_40mhz_intolerant = 1;
+				pmlmepriv->num_sta_40mhz_intolerant++;
+				RTW_INFO("%s STA " MAC_FMT " - 40MHZ_INTOLERANT, ",
+					   __FUNCTION__, MAC_ARG(psta->cmn.mac_addr));
+			}
+
+		} else {
+			if (!psta->no_ht_set) {
+				psta->no_ht_set = 1;
+				pmlmepriv->num_sta_no_ht++;
+			}
+			if (pmlmepriv->htpriv.ht_option == _TRUE) {
+				RTW_INFO("%s STA " MAC_FMT
+					 " - no HT, num of non-HT stations %d\n",
+					 __FUNCTION__, MAC_ARG(psta->cmn.mac_addr),
+					 pmlmepriv->num_sta_no_ht);
+			}
+		}
+
+		if (rtw_ht_operation_update(padapter) > 0) {
+			update_beacon(padapter, _HT_CAPABILITY_IE_, NULL, _FALSE);
+			update_beacon(padapter, _HT_ADD_INFO_IE_, NULL, _FALSE);
+			beacon_updated = _TRUE;
+		}
+	}
+#endif /* CONFIG_80211N_HT */
+
+#ifdef CONFIG_RTW_MESH
+	if (MLME_IS_MESH(padapter)) {
+		struct sta_priv *pstapriv = &padapter->stapriv;
+
+		update_beacon(padapter, WLAN_EID_MESH_CONFIG, NULL, _FALSE);
+		if (pstapriv->asoc_list_cnt == 1)
+			_set_timer(&padapter->mesh_atlm_param_req_timer, 0);
+		beacon_updated = _TRUE;
+	}
+#endif
+
+	if (beacon_updated)
+		update_beacon(padapter, 0xFF, NULL, _TRUE);
+
+	/* update associcated stations cap. */
+	associated_clients_update(padapter,  beacon_updated, STA_INFO_UPDATE_ALL);
+
+	RTW_INFO("%s, updated=%d\n", __func__, beacon_updated);
+
+}
+
+u8 bss_cap_update_on_sta_leave(_adapter *padapter, struct sta_info *psta)
+{
+	u8 beacon_updated = _FALSE;
+	struct sta_priv *pstapriv = &padapter->stapriv;
+	struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
+	struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv);
+
+	if (!psta)
+		return beacon_updated;
+
+	if (rtw_tim_map_is_set(padapter, pstapriv->tim_bitmap, psta->cmn.aid)) {
+		rtw_tim_map_clear(padapter, pstapriv->tim_bitmap, psta->cmn.aid);
+		beacon_updated = _TRUE;
+		update_beacon(padapter, _TIM_IE_, NULL, _FALSE);
+	}
+
+	if (psta->no_short_preamble_set) {
+		psta->no_short_preamble_set = 0;
+		pmlmepriv->num_sta_no_short_preamble--;
+		if (pmlmeext->cur_wireless_mode > WIRELESS_11B
+		    && pmlmepriv->num_sta_no_short_preamble == 0)
+			beacon_updated = _TRUE;
+	}
+
+	if (psta->nonerp_set) {
+		psta->nonerp_set = 0;
+		pmlmepriv->num_sta_non_erp--;
+		if (pmlmepriv->num_sta_non_erp == 0) {
+			beacon_updated = _TRUE;
+			update_beacon(padapter, _ERPINFO_IE_, NULL, _FALSE);
+		}
+	}
+
+	if (psta->no_short_slot_time_set) {
+		psta->no_short_slot_time_set = 0;
+		pmlmepriv->num_sta_no_short_slot_time--;
+		if (pmlmeext->cur_wireless_mode > WIRELESS_11B
+		    && pmlmepriv->num_sta_no_short_slot_time == 0)
+			beacon_updated = _TRUE;
+	}
+
+#ifdef CONFIG_80211N_HT
+	if (psta->no_ht_gf_set) {
+		psta->no_ht_gf_set = 0;
+		pmlmepriv->num_sta_ht_no_gf--;
+	}
+
+	if (psta->no_ht_set) {
+		psta->no_ht_set = 0;
+		pmlmepriv->num_sta_no_ht--;
+	}
+
+	if (psta->ht_20mhz_set) {
+		psta->ht_20mhz_set = 0;
+		pmlmepriv->num_sta_ht_20mhz--;
+	}
+
+	if (psta->ht_40mhz_intolerant) {
+		psta->ht_40mhz_intolerant = 0;
+		if (pmlmepriv->num_sta_40mhz_intolerant > 0)
+			pmlmepriv->num_sta_40mhz_intolerant--;
+		else
+			rtw_warn_on(1);
+	}
+
+	if (rtw_ht_operation_update(padapter) > 0) {
+		update_beacon(padapter, _HT_CAPABILITY_IE_, NULL, _FALSE);
+		update_beacon(padapter, _HT_ADD_INFO_IE_, NULL, _FALSE);
+	}
+#endif /* CONFIG_80211N_HT */
+
+#ifdef CONFIG_RTW_MESH
+	if (MLME_IS_MESH(padapter)) {
+		update_beacon(padapter, WLAN_EID_MESH_CONFIG, NULL, _FALSE);
+		if (pstapriv->asoc_list_cnt == 0)
+			_cancel_timer_ex(&padapter->mesh_atlm_param_req_timer);
+		beacon_updated = _TRUE;
+	}
+#endif
+
+	if (beacon_updated == _TRUE)
+		update_beacon(padapter, 0xFF, NULL, _TRUE);
+
+#if 0
+	/* update associated stations cap. */
+	associated_clients_update(padapter,  beacon_updated, STA_INFO_UPDATE_ALL); /* move it to avoid deadlock */
+#endif
+
+	RTW_INFO("%s, updated=%d\n", __func__, beacon_updated);
+
+	return beacon_updated;
+
+}
+
+u8 ap_free_sta(_adapter *padapter, struct sta_info *psta, bool active, u16 reason, bool enqueue)
+{
+	_irqL irqL;
+	u8 beacon_updated = _FALSE;
+
+	if (!psta)
+		return beacon_updated;
+
+	if (active == _TRUE) {
+#ifdef CONFIG_80211N_HT
+		/* tear down Rx AMPDU */
+		send_delba(padapter, 0, psta->cmn.mac_addr);/* recipient */
+
+		/* tear down TX AMPDU */
+		send_delba(padapter, 1, psta->cmn.mac_addr);/*  */ /* originator */
+
+#endif /* CONFIG_80211N_HT */
+
+		if (!MLME_IS_MESH(padapter))
+			issue_deauth(padapter, psta->cmn.mac_addr, reason);
+	}
+
+#ifdef CONFIG_RTW_MESH
+	if (MLME_IS_MESH(padapter))
+		rtw_mesh_path_flush_by_nexthop(psta);
+#endif
+
+#ifdef CONFIG_BEAMFORMING
+	beamforming_wk_cmd(padapter, BEAMFORMING_CTRL_LEAVE, psta->cmn.mac_addr, ETH_ALEN, 1);
+#endif
+
+#ifdef CONFIG_80211N_HT
+	psta->htpriv.agg_enable_bitmap = 0x0;/* reset */
+	psta->htpriv.candidate_tid_bitmap = 0x0;/* reset */
+#endif
+
+	/* clear cam entry / key */
+	rtw_clearstakey_cmd(padapter, psta, enqueue);
+
+
+	_enter_critical_bh(&psta->lock, &irqL);
+	psta->state &= ~(_FW_LINKED | WIFI_UNDER_KEY_HANDSHAKE);
+	_exit_critical_bh(&psta->lock, &irqL);
+
+	if (!MLME_IS_MESH(padapter)) {
+#ifdef CONFIG_IOCTL_CFG80211
+		#ifdef COMPAT_KERNEL_RELEASE
+		rtw_cfg80211_indicate_sta_disassoc(padapter, psta->cmn.mac_addr, reason);
+		#elif (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) && !defined(CONFIG_CFG80211_FORCE_COMPATIBLE_2_6_37_UNDER)
+		rtw_cfg80211_indicate_sta_disassoc(padapter, psta->cmn.mac_addr, reason);
+		#else /* (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) && !defined(CONFIG_CFG80211_FORCE_COMPATIBLE_2_6_37_UNDER) */
+		/* will call rtw_cfg80211_indicate_sta_disassoc() in cmd_thread for old API context */
+		#endif /* (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) && !defined(CONFIG_CFG80211_FORCE_COMPATIBLE_2_6_37_UNDER) */
+#else
+		rtw_indicate_sta_disassoc_event(padapter, psta);
+#endif
+	}
+
+	beacon_updated = bss_cap_update_on_sta_leave(padapter, psta);
+
+	report_del_sta_event(padapter, psta->cmn.mac_addr, reason, enqueue, _FALSE);
+
+	return beacon_updated;
+
+}
+
+int rtw_ap_inform_ch_switch(_adapter *padapter, u8 new_ch, u8 ch_offset)
+{
+	_irqL irqL;
+	_list	*phead, *plist;
+	int ret = 0;
+	struct sta_info *psta = NULL;
+	struct sta_priv *pstapriv = &padapter->stapriv;
+	struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
+	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
+	u8 bc_addr[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
+
+	if ((pmlmeinfo->state & 0x03) != WIFI_FW_AP_STATE)
+		return ret;
+
+	RTW_INFO(FUNC_NDEV_FMT" with ch:%u, offset:%u\n",
+		 FUNC_NDEV_ARG(padapter->pnetdev), new_ch, ch_offset);
+
+	_enter_critical_bh(&pstapriv->asoc_list_lock, &irqL);
+	phead = &pstapriv->asoc_list;
+	plist = get_next(phead);
+
+	/* for each sta in asoc_queue */
+	while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) {
+		psta = LIST_CONTAINOR(plist, struct sta_info, asoc_list);
+		plist = get_next(plist);
+
+		issue_action_spct_ch_switch(padapter, psta->cmn.mac_addr, new_ch, ch_offset);
+		psta->expire_to = ((pstapriv->expire_to * 2) > 5) ? 5 : (pstapriv->expire_to * 2);
+	}
+	_exit_critical_bh(&pstapriv->asoc_list_lock, &irqL);
+
+	issue_action_spct_ch_switch(padapter, bc_addr, new_ch, ch_offset);
+
+	return ret;
+}
+
+int rtw_sta_flush(_adapter *padapter, bool enqueue)
+{
+	_irqL irqL;
+	_list	*phead, *plist;
+	int ret = 0;
+	struct sta_info *psta = NULL;
+	struct sta_priv *pstapriv = &padapter->stapriv;
+	u8 bc_addr[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
+	u8 flush_num = 0;
+	char flush_list[NUM_STA];
+	int i;
+
+	if (!MLME_IS_AP(padapter) && !MLME_IS_MESH(padapter))
+		return ret;
+
+	RTW_INFO(FUNC_NDEV_FMT"\n", FUNC_NDEV_ARG(padapter->pnetdev));
+
+	/* pick sta from sta asoc_queue */
+	_enter_critical_bh(&pstapriv->asoc_list_lock, &irqL);
+	phead = &pstapriv->asoc_list;
+	plist = get_next(phead);
+	while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) {
+		int stainfo_offset;
+
+		psta = LIST_CONTAINOR(plist, struct sta_info, asoc_list);
+		plist = get_next(plist);
+
+		rtw_list_delete(&psta->asoc_list);
+		pstapriv->asoc_list_cnt--;
+		STA_SET_MESH_PLINK(psta, NULL);
+
+		stainfo_offset = rtw_stainfo_offset(pstapriv, psta);
+		if (stainfo_offset_valid(stainfo_offset))
+			flush_list[flush_num++] = stainfo_offset;
+		else
+			rtw_warn_on(1);
+	}
+	_exit_critical_bh(&pstapriv->asoc_list_lock, &irqL);
+
+	/* call ap_free_sta() for each sta picked */
+	for (i = 0; i < flush_num; i++) {
+		u8 sta_addr[ETH_ALEN];
+
+		psta = rtw_get_stainfo_by_offset(pstapriv, flush_list[i]);
+		_rtw_memcpy(sta_addr, psta->cmn.mac_addr, ETH_ALEN);
+
+		ap_free_sta(padapter, psta, _TRUE, WLAN_REASON_DEAUTH_LEAVING, enqueue);
+		#ifdef CONFIG_RTW_MESH
+		if (MLME_IS_MESH(padapter))
+			rtw_mesh_expire_peer(padapter, sta_addr);
+		#endif
+	}
+
+	if (!MLME_IS_MESH(padapter))
+		issue_deauth(padapter, bc_addr, WLAN_REASON_DEAUTH_LEAVING);
+
+	associated_clients_update(padapter, _TRUE, STA_INFO_UPDATE_ALL);
+
+	return ret;
+}
+
+/* called > TSR LEVEL for USB or SDIO Interface*/
+void sta_info_update(_adapter *padapter, struct sta_info *psta)
+{
+	int flags = psta->flags;
+	struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
+
+
+	/* update wmm cap. */
+	if (WLAN_STA_WME & flags)
+		psta->qos_option = 1;
+	else
+		psta->qos_option = 0;
+
+	if (pmlmepriv->qospriv.qos_option == 0)
+		psta->qos_option = 0;
+
+
+#ifdef CONFIG_80211N_HT
+	/* update 802.11n ht cap. */
+	if (WLAN_STA_HT & flags) {
+		psta->htpriv.ht_option = _TRUE;
+		psta->qos_option = 1;
+
+		psta->htpriv.smps_cap = (psta->htpriv.ht_cap.cap_info & IEEE80211_HT_CAP_SM_PS) >> 2;
+	} else
+		psta->htpriv.ht_option = _FALSE;
+
+	if (pmlmepriv->htpriv.ht_option == _FALSE)
+		psta->htpriv.ht_option = _FALSE;
+#endif
+
+#ifdef CONFIG_80211AC_VHT
+	/* update 802.11AC vht cap. */
+	if (WLAN_STA_VHT & flags)
+		psta->vhtpriv.vht_option = _TRUE;
+	else
+		psta->vhtpriv.vht_option = _FALSE;
+
+	if (pmlmepriv->vhtpriv.vht_option == _FALSE)
+		psta->vhtpriv.vht_option = _FALSE;
+#endif
+
+	update_sta_info_apmode(padapter, psta);
+}
+
+/* called >= TSR LEVEL for USB or SDIO Interface*/
+void ap_sta_info_defer_update(_adapter *padapter, struct sta_info *psta)
+{
+	if (psta->state & _FW_LINKED)
+		rtw_hal_update_ra_mask(psta); /* DM_RATR_STA_INIT */
+}
+/* restore hw setting from sw data structures */
+void rtw_ap_restore_network(_adapter *padapter)
+{
+	struct mlme_ext_priv	*pmlmeext = &padapter->mlmeextpriv;
+	struct sta_priv *pstapriv = &padapter->stapriv;
+	struct sta_info *psta;
+	struct security_priv *psecuritypriv = &(padapter->securitypriv);
+	_irqL irqL;
+	_list	*phead, *plist;
+	u8 chk_alive_num = 0;
+	char chk_alive_list[NUM_STA];
+	int i;
+
+	rtw_setopmode_cmd(padapter
+		, MLME_IS_AP(padapter) ? Ndis802_11APMode : Ndis802_11_mesh
+		, RTW_CMDF_DIRECTLY
+	);
+
+	set_channel_bwmode(padapter, pmlmeext->cur_channel, pmlmeext->cur_ch_offset, pmlmeext->cur_bwmode);
+
+	rtw_startbss_cmd(padapter, RTW_CMDF_DIRECTLY);
+
+	if ((padapter->securitypriv.dot11PrivacyAlgrthm == _TKIP_) ||
+	    (padapter->securitypriv.dot11PrivacyAlgrthm == _AES_)) {
+		/* restore group key, WEP keys is restored in ips_leave() */
+		rtw_set_key(padapter, psecuritypriv, psecuritypriv->dot118021XGrpKeyid, 0, _FALSE);
+	}
+
+	_enter_critical_bh(&pstapriv->asoc_list_lock, &irqL);
+
+	phead = &pstapriv->asoc_list;
+	plist = get_next(phead);
+
+	while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) {
+		int stainfo_offset;
+
+		psta = LIST_CONTAINOR(plist, struct sta_info, asoc_list);
+		plist = get_next(plist);
+
+		stainfo_offset = rtw_stainfo_offset(pstapriv, psta);
+		if (stainfo_offset_valid(stainfo_offset))
+			chk_alive_list[chk_alive_num++] = stainfo_offset;
+	}
+
+	_exit_critical_bh(&pstapriv->asoc_list_lock, &irqL);
+
+	for (i = 0; i < chk_alive_num; i++) {
+		psta = rtw_get_stainfo_by_offset(pstapriv, chk_alive_list[i]);
+
+		if (psta == NULL)
+			RTW_INFO(FUNC_ADPT_FMT" sta_info is null\n", FUNC_ADPT_ARG(padapter));
+		else if (psta->state & _FW_LINKED) {
+			rtw_sta_media_status_rpt(padapter, psta, 1);
+			Update_RA_Entry(padapter, psta);
+			/* pairwise key */
+			/* per sta pairwise key and settings */
+			if ((padapter->securitypriv.dot11PrivacyAlgrthm == _TKIP_) ||
+			    (padapter->securitypriv.dot11PrivacyAlgrthm == _AES_))
+				rtw_setstakey_cmd(padapter, psta, UNICAST_KEY, _FALSE);
+		}
+	}
+
+}
+
+void start_ap_mode(_adapter *padapter)
+{
+	int i;
+	struct sta_info *psta = NULL;
+	struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
+	struct sta_priv *pstapriv = &padapter->stapriv;
+	struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
+	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
+#ifdef CONFIG_CONCURRENT_MODE
+	struct security_priv *psecuritypriv = &padapter->securitypriv;
+#endif
+
+	pmlmepriv->update_bcn = _FALSE;
+
+	/*init_mlme_ap_info(padapter);*/
+
+	pmlmeext->bstart_bss = _FALSE;
+
+	pmlmepriv->num_sta_non_erp = 0;
+
+	pmlmepriv->num_sta_no_short_slot_time = 0;
+
+	pmlmepriv->num_sta_no_short_preamble = 0;
+
+	pmlmepriv->num_sta_ht_no_gf = 0;
+#ifdef CONFIG_80211N_HT
+	pmlmepriv->num_sta_no_ht = 0;
+#endif /* CONFIG_80211N_HT */
+	pmlmeinfo->HT_info_enable = 0;
+	pmlmeinfo->HT_caps_enable = 0;
+	pmlmeinfo->HT_enable = 0;
+
+	pmlmepriv->num_sta_ht_20mhz = 0;
+	pmlmepriv->num_sta_40mhz_intolerant = 0;
+	ATOMIC_SET(&pmlmepriv->olbc, _FALSE);
+	ATOMIC_SET(&pmlmepriv->olbc_ht, _FALSE);
+
+#ifdef CONFIG_80211N_HT
+	pmlmepriv->ht_20mhz_width_req = _FALSE;
+	pmlmepriv->ht_intolerant_ch_reported = _FALSE;
+	pmlmepriv->ht_op_mode = 0;
+	pmlmepriv->sw_to_20mhz = 0;
+#endif
+
+	_rtw_memset(pmlmepriv->ext_capab_ie_data, 0, sizeof(pmlmepriv->ext_capab_ie_data));
+	pmlmepriv->ext_capab_ie_len = 0;
+
+#ifdef CONFIG_CONCURRENT_MODE
+	psecuritypriv->dot118021x_bmc_cam_id = INVALID_SEC_MAC_CAM_ID;
+#endif
+
+	for (i = 0 ;  i < pstapriv->max_aid; i++)
+		pstapriv->sta_aid[i] = NULL;
+
+	psta = rtw_get_bcmc_stainfo(padapter);
+	/*_enter_critical_bh(&(pstapriv->sta_hash_lock), &irqL);*/
+	if (psta)
+		rtw_free_stainfo(padapter, psta);
+	/*_exit_critical_bh(&(pstapriv->sta_hash_lock), &irqL);*/
+
+	rtw_init_bcmc_stainfo(padapter);
+
+	if (rtw_mi_get_ap_num(padapter))
+		RTW_SET_SCAN_BAND_SKIP(padapter, BAND_5G);
+
+}
+
+void rtw_ap_bcmc_sta_flush(_adapter *padapter)
+{
+#ifdef CONFIG_CONCURRENT_MODE
+	int cam_id = -1;
+	u8 *addr = adapter_mac_addr(padapter);
+
+	cam_id = rtw_iface_bcmc_id_get(padapter);
+	if (cam_id != INVALID_SEC_MAC_CAM_ID) {
+		RTW_PRINT("clear group key for "ADPT_FMT" addr:"MAC_FMT", camid:%d\n",
+			ADPT_ARG(padapter), MAC_ARG(addr), cam_id);
+		clear_cam_entry(padapter, cam_id);
+		rtw_camid_free(padapter, cam_id);
+		rtw_iface_bcmc_id_set(padapter, INVALID_SEC_MAC_CAM_ID);	/*init default value*/
+	}
+#else
+	invalidate_cam_all(padapter);
+#endif
+}
+
+void stop_ap_mode(_adapter *padapter)
+{
+	u8 self_action = MLME_ACTION_UNKNOWN;
+	struct sta_info *psta = NULL;
+	struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
+	struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
+#ifdef CONFIG_SUPPORT_MULTI_BCN
+	struct dvobj_priv *pdvobj = padapter->dvobj;
+	_irqL irqL;
+#endif
+
+	RTW_INFO("%s -"ADPT_FMT"\n", __func__, ADPT_ARG(padapter));
+
+	if (MLME_IS_AP(padapter))
+		self_action = MLME_AP_STOPPED;
+	else if (MLME_IS_MESH(padapter))
+		self_action = MLME_MESH_STOPPED;
+	else
+		rtw_warn_on(1);
+
+	pmlmepriv->update_bcn = _FALSE;
+	/*pmlmeext->bstart_bss = _FALSE;*/
+	padapter->netif_up = _FALSE;
+	/* _rtw_spinlock_free(&pmlmepriv->bcn_update_lock); */
+
+	/* reset and init security priv , this can refine with rtw_reset_securitypriv */
+	_rtw_memset((unsigned char *)&padapter->securitypriv, 0, sizeof(struct security_priv));
+	padapter->securitypriv.ndisauthtype = Ndis802_11AuthModeOpen;
+	padapter->securitypriv.ndisencryptstatus = Ndis802_11WEPDisabled;
+
+#ifdef CONFIG_DFS_MASTER
+	rtw_dfs_rd_en_decision(padapter, self_action, 0);
+#endif
+
+	/* free scan queue */
+	rtw_free_network_queue(padapter, _TRUE);
+
+#if CONFIG_RTW_MACADDR_ACL
+	rtw_macaddr_acl_clear(padapter, RTW_ACL_PERIOD_BSS);
+#endif
+
+	rtw_sta_flush(padapter, _TRUE);
+	rtw_ap_bcmc_sta_flush(padapter);
+
+	/* free_assoc_sta_resources	 */
+	rtw_free_all_stainfo(padapter);
+
+	psta = rtw_get_bcmc_stainfo(padapter);
+	if (psta) {
+		rtw_sta_mstatus_disc_rpt(padapter, psta->cmn.mac_id);
+		/* _enter_critical_bh(&(pstapriv->sta_hash_lock), &irqL);		 */
+		rtw_free_stainfo(padapter, psta);
+		/*_exit_critical_bh(&(pstapriv->sta_hash_lock), &irqL);*/
+	}
+
+	rtw_free_mlme_priv_ie_data(pmlmepriv);
+
+#ifdef CONFIG_SUPPORT_MULTI_BCN
+	if (pmlmeext->bstart_bss == _TRUE) {
+		#ifdef CONFIG_FW_HANDLE_TXBCN
+		u8 free_apid = CONFIG_LIMITED_AP_NUM;
+		#endif
+
+		_enter_critical_bh(&pdvobj->ap_if_q.lock, &irqL);
+		pdvobj->nr_ap_if--;
+		if (pdvobj->nr_ap_if > 0)
+			pdvobj->inter_bcn_space = DEFAULT_BCN_INTERVAL / pdvobj->nr_ap_if;
+		else
+			pdvobj->inter_bcn_space = DEFAULT_BCN_INTERVAL;
+		#ifdef CONFIG_FW_HANDLE_TXBCN
+		rtw_ap_release_vapid(pdvobj, padapter->vap_id);
+		free_apid = padapter->vap_id;
+		padapter->vap_id = CONFIG_LIMITED_AP_NUM;
+		#endif
+		rtw_list_delete(&padapter->list);
+		_exit_critical_bh(&pdvobj->ap_if_q.lock, &irqL);
+		#ifdef CONFIG_FW_HANDLE_TXBCN
+		rtw_ap_mbid_bcn_dis(padapter, free_apid);
+		#endif
+
+		#ifdef CONFIG_SWTIMER_BASED_TXBCN
+		rtw_hal_set_hwreg(padapter, HW_VAR_BEACON_INTERVAL, (u8 *)(&pdvobj->inter_bcn_space));
+
+		if (pdvobj->nr_ap_if == 0)
+			_cancel_timer_ex(&pdvobj->txbcn_timer);
+		#endif
+	}
+#endif
+
+	pmlmeext->bstart_bss = _FALSE;
+
+	rtw_hal_rcr_set_chk_bssid(padapter, self_action);
+
+#ifdef CONFIG_HW_P0_TSF_SYNC
+	correct_TSF(padapter, self_action);
+#endif
+
+#ifdef CONFIG_BT_COEXIST
+	rtw_btcoex_MediaStatusNotify(padapter, 0); /* disconnect */
+#endif
+
+}
+
+#endif /* CONFIG_NATIVEAP_MLME */
+
+void rtw_ap_update_bss_chbw(_adapter *adapter, WLAN_BSSID_EX *bss, u8 ch, u8 bw, u8 offset)
+{
+#define UPDATE_VHT_CAP 1
+#define UPDATE_HT_CAP 1
+#ifdef CONFIG_80211AC_VHT
+	struct vht_priv *vhtpriv = &adapter->mlmepriv.vhtpriv;
+#endif
+	{
+		u8 *p;
+		int ie_len;
+		u8 old_ch = bss->Configuration.DSConfig;
+		bool change_band = _FALSE;
+
+		if ((ch <= 14 && old_ch >= 36) || (ch >= 36 && old_ch <= 14))
+			change_band = _TRUE;
+
+		/* update channel in IE */
+		p = rtw_get_ie((bss->IEs + sizeof(NDIS_802_11_FIXED_IEs)), _DSSET_IE_, &ie_len, (bss->IELength - sizeof(NDIS_802_11_FIXED_IEs)));
+		if (p && ie_len > 0)
+			*(p + 2) = ch;
+
+		bss->Configuration.DSConfig = ch;
+
+		/* band is changed, update ERP, support rate, ext support rate IE */
+		if (change_band == _TRUE)
+			change_band_update_ie(adapter, bss, ch);
+	}
+
+#ifdef CONFIG_80211AC_VHT
+	if (vhtpriv->vht_option == _TRUE) {
+		u8 *vht_cap_ie, *vht_op_ie;
+		int vht_cap_ielen, vht_op_ielen;
+		u8	center_freq;
+
+		vht_cap_ie = rtw_get_ie((bss->IEs + sizeof(NDIS_802_11_FIXED_IEs)), EID_VHTCapability, &vht_cap_ielen, (bss->IELength - sizeof(NDIS_802_11_FIXED_IEs)));
+		vht_op_ie = rtw_get_ie((bss->IEs + sizeof(NDIS_802_11_FIXED_IEs)), EID_VHTOperation, &vht_op_ielen, (bss->IELength - sizeof(NDIS_802_11_FIXED_IEs)));
+		center_freq = rtw_get_center_ch(ch, bw, offset);
+
+		/* update vht cap ie */
+		if (vht_cap_ie && vht_cap_ielen) {
+			#if UPDATE_VHT_CAP
+			/* if ((bw == CHANNEL_WIDTH_160 || bw == CHANNEL_WIDTH_80_80) && pvhtpriv->sgi_160m)
+				SET_VHT_CAPABILITY_ELE_SHORT_GI160M(pvht_cap_ie + 2, 1);
+			else */
+				SET_VHT_CAPABILITY_ELE_SHORT_GI160M(vht_cap_ie + 2, 0);
+
+			if (bw >= CHANNEL_WIDTH_80 && vhtpriv->sgi_80m)
+				SET_VHT_CAPABILITY_ELE_SHORT_GI80M(vht_cap_ie + 2, 1);
+			else
+				SET_VHT_CAPABILITY_ELE_SHORT_GI80M(vht_cap_ie + 2, 0);
+			#endif
+		}
+
+		/* update vht op ie */
+		if (vht_op_ie && vht_op_ielen) {
+			if (bw < CHANNEL_WIDTH_80) {
+				SET_VHT_OPERATION_ELE_CHL_WIDTH(vht_op_ie + 2, 0);
+				SET_VHT_OPERATION_ELE_CHL_CENTER_FREQ1(vht_op_ie + 2, 0);
+				SET_VHT_OPERATION_ELE_CHL_CENTER_FREQ2(vht_op_ie + 2, 0);
+			} else if (bw == CHANNEL_WIDTH_80) {
+				SET_VHT_OPERATION_ELE_CHL_WIDTH(vht_op_ie + 2, 1);
+				SET_VHT_OPERATION_ELE_CHL_CENTER_FREQ1(vht_op_ie + 2, center_freq);
+				SET_VHT_OPERATION_ELE_CHL_CENTER_FREQ2(vht_op_ie + 2, 0);
+			} else {
+				RTW_ERR(FUNC_ADPT_FMT" unsupported BW:%u\n", FUNC_ADPT_ARG(adapter), bw);
+				rtw_warn_on(1);
+			}
+		}
+	}
+#endif /* CONFIG_80211AC_VHT */
+#ifdef CONFIG_80211N_HT
+	{
+		struct ht_priv	*htpriv = &adapter->mlmepriv.htpriv;
+		u8 *ht_cap_ie, *ht_op_ie;
+		int ht_cap_ielen, ht_op_ielen;
+
+		ht_cap_ie = rtw_get_ie((bss->IEs + sizeof(NDIS_802_11_FIXED_IEs)), EID_HTCapability, &ht_cap_ielen, (bss->IELength - sizeof(NDIS_802_11_FIXED_IEs)));
+		ht_op_ie = rtw_get_ie((bss->IEs + sizeof(NDIS_802_11_FIXED_IEs)), EID_HTInfo, &ht_op_ielen, (bss->IELength - sizeof(NDIS_802_11_FIXED_IEs)));
+
+		/* update ht cap ie */
+		if (ht_cap_ie && ht_cap_ielen) {
+			#if UPDATE_HT_CAP
+			if (bw >= CHANNEL_WIDTH_40)
+				SET_HT_CAP_ELE_CHL_WIDTH(ht_cap_ie + 2, 1);
+			else
+				SET_HT_CAP_ELE_CHL_WIDTH(ht_cap_ie + 2, 0);
+
+			if (bw >= CHANNEL_WIDTH_40 && htpriv->sgi_40m)
+				SET_HT_CAP_ELE_SHORT_GI40M(ht_cap_ie + 2, 1);
+			else
+				SET_HT_CAP_ELE_SHORT_GI40M(ht_cap_ie + 2, 0);
+
+			if (htpriv->sgi_20m)
+				SET_HT_CAP_ELE_SHORT_GI20M(ht_cap_ie + 2, 1);
+			else
+				SET_HT_CAP_ELE_SHORT_GI20M(ht_cap_ie + 2, 0);
+			#endif
+		}
+
+		/* update ht op ie */
+		if (ht_op_ie && ht_op_ielen) {
+			SET_HT_OP_ELE_PRI_CHL(ht_op_ie + 2, ch);
+			switch (offset) {
+			case HAL_PRIME_CHNL_OFFSET_LOWER:
+				SET_HT_OP_ELE_2ND_CHL_OFFSET(ht_op_ie + 2, SCA);
+				break;
+			case HAL_PRIME_CHNL_OFFSET_UPPER:
+				SET_HT_OP_ELE_2ND_CHL_OFFSET(ht_op_ie + 2, SCB);
+				break;
+			case HAL_PRIME_CHNL_OFFSET_DONT_CARE:
+			default:
+				SET_HT_OP_ELE_2ND_CHL_OFFSET(ht_op_ie + 2, SCN);
+				break;
+			}
+
+			if (bw >= CHANNEL_WIDTH_40)
+				SET_HT_OP_ELE_STA_CHL_WIDTH(ht_op_ie + 2, 1);
+			else
+				SET_HT_OP_ELE_STA_CHL_WIDTH(ht_op_ie + 2, 0);
+		}
+	}
+#endif /* CONFIG_80211N_HT */
+}
+
+static u8 rtw_ap_update_chbw_by_ifbmp(struct dvobj_priv *dvobj, u8 ifbmp
+	, u8 cur_ie_ch[], u8 cur_ie_bw[], u8 cur_ie_offset[]
+	, u8 dec_ch[], u8 dec_bw[], u8 dec_offset[]
+	, const char *caller)
+{
+	_adapter *iface;
+	struct mlme_ext_priv *mlmeext;
+	WLAN_BSSID_EX *network;
+	u8 ifbmp_ch_changed = 0;
+	int i;
+
+	for (i = 0; i < dvobj->iface_nums; i++) {
+		if (!(ifbmp & BIT(i)) || !dvobj->padapters)
+			continue;
+
+		iface = dvobj->padapters[i];
+		mlmeext = &(iface->mlmeextpriv);
+
+		if (MLME_IS_ASOC(iface)) {
+			RTW_INFO(FUNC_ADPT_FMT" %u,%u,%u => %u,%u,%u%s\n", caller, ADPT_ARG(iface)
+				, mlmeext->cur_channel, mlmeext->cur_bwmode, mlmeext->cur_ch_offset
+				, dec_ch[i], dec_bw[i], dec_offset[i]
+				, MLME_IS_OPCH_SW(iface) ? " OPCH_SW" : "");
+		} else {
+			RTW_INFO(FUNC_ADPT_FMT" %u,%u,%u => %u,%u,%u%s\n", caller, ADPT_ARG(iface)
+				, cur_ie_ch[i], cur_ie_bw[i], cur_ie_offset[i]
+				, dec_ch[i], dec_bw[i], dec_offset[i]
+				, MLME_IS_OPCH_SW(iface) ? " OPCH_SW" : "");
+		}
+	}
+
+	for (i = 0; i < dvobj->iface_nums; i++) {
+		if (!(ifbmp & BIT(i)) || !dvobj->padapters)
+			continue;
+
+		iface = dvobj->padapters[i];
+		mlmeext = &(iface->mlmeextpriv);
+		network = &(mlmeext->mlmext_info.network);
+
+		/* ch setting differs from mlmeext.network IE */
+		if (cur_ie_ch[i] != dec_ch[i]
+			|| cur_ie_bw[i] != dec_bw[i]
+			|| cur_ie_offset[i] != dec_offset[i])
+			ifbmp_ch_changed |= BIT(i);
+
+		/* ch setting differs from existing one */
+		if (MLME_IS_ASOC(iface)
+			&& (mlmeext->cur_channel != dec_ch[i]
+				|| mlmeext->cur_bwmode != dec_bw[i]
+				|| mlmeext->cur_ch_offset != dec_offset[i])
+		) {
+			if (rtw_linked_check(iface) == _TRUE) {
+				#ifdef CONFIG_SPCT_CH_SWITCH
+				if (1)
+					rtw_ap_inform_ch_switch(iface, dec_ch[i], dec_offset[i]);
+				else
+				#endif
+					rtw_sta_flush(iface, _FALSE);
+			}
+		}
+
+		mlmeext->cur_channel = dec_ch[i];
+		mlmeext->cur_bwmode = dec_bw[i];
+		mlmeext->cur_ch_offset = dec_offset[i];
+
+		rtw_ap_update_bss_chbw(iface, network, dec_ch[i], dec_bw[i], dec_offset[i]);
+	}
+
+	return ifbmp_ch_changed;
+}
+
+static u8 rtw_ap_ch_specific_chk(_adapter *adapter, u8 ch, u8 *bw, u8 *offset, const char *caller)
+{
+	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
+	RT_CHANNEL_INFO *chset = adapter_to_chset(adapter);
+	u8 ret = _SUCCESS;
+
+	if (rtw_chset_search_ch(chset, ch) < 0) {
+		RTW_WARN("%s ch:%u doesn't fit in chplan\n", caller, ch);
+		ret = _FAIL;
+		goto exit;
+	}
+
+	rtw_adjust_chbw(adapter, ch, bw, offset);
+
+	if (!rtw_get_offset_by_chbw(ch, *bw, offset)) {
+		RTW_WARN("%s %u,%u has no valid offset\n", caller, ch, *bw);
+		ret = _FAIL;
+		goto exit;
+	}
+
+	while (!rtw_chset_is_chbw_valid(chset, ch, *bw, *offset)
+		|| (rtw_odm_dfs_domain_unknown(dvobj) && rtw_is_dfs_chbw(ch, *bw, *offset))
+	) {
+		if (*bw > CHANNEL_WIDTH_20)
+			(*bw)--;
+		if (*bw == CHANNEL_WIDTH_20) {
+			*offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
+			break;
+		}
+	}
+
+	if (rtw_odm_dfs_domain_unknown(dvobj) && rtw_is_dfs_chbw(ch, *bw, *offset)) {
+		RTW_WARN("%s DFS channel %u can't be used\n", caller, ch);
+		ret = _FAIL;
+		goto exit;
+	}
+
+exit:
+	return ret;
+}
+
+static bool rtw_ap_choose_chbw(_adapter *adapter, u8 sel_ch, u8 max_bw, u8 cur_ch
+	, u8 *ch, u8 *bw, u8 *offset, u8 mesh_only, const char *caller)
+{
+	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
+	struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter);
+	bool ch_avail = _FALSE;
+
+#if defined(CONFIG_DFS_MASTER)
+	if (!rtw_odm_dfs_domain_unknown(dvobj)) {
+		if (rfctl->radar_detected
+			&& rfctl->dbg_dfs_choose_dfs_ch_first
+		) {
+			ch_avail = rtw_choose_shortest_waiting_ch(rfctl, sel_ch, max_bw
+						, ch, bw, offset
+						, RTW_CHF_2G | RTW_CHF_NON_DFS
+						, cur_ch
+						, rfctl->ch_sel_same_band_prefer, mesh_only);
+			if (ch_avail == _TRUE) {
+				RTW_INFO("%s choose 5G DFS channel for debug\n", caller);
+				goto exit;
+			}
+		}
+
+		if (rfctl->radar_detected
+			&& rfctl->dfs_ch_sel_d_flags
+		) {
+			ch_avail = rtw_choose_shortest_waiting_ch(rfctl, sel_ch, max_bw
+						, ch, bw, offset
+						, rfctl->dfs_ch_sel_d_flags
+						, cur_ch
+						, rfctl->ch_sel_same_band_prefer, mesh_only);
+			if (ch_avail == _TRUE) {
+				RTW_INFO("%s choose with dfs_ch_sel_d_flags:0x%02x for debug\n"
+					, caller, rfctl->dfs_ch_sel_d_flags);
+				goto exit;
+			}
+		}
+
+		ch_avail = rtw_choose_shortest_waiting_ch(rfctl, sel_ch, max_bw
+					, ch, bw, offset
+					, 0
+					, cur_ch
+					, rfctl->ch_sel_same_band_prefer, mesh_only);
+	} else
+#endif /* defined(CONFIG_DFS_MASTER) */
+	{
+		ch_avail = rtw_choose_shortest_waiting_ch(rfctl, sel_ch, max_bw
+					, ch, bw, offset
+					, RTW_CHF_DFS
+					, cur_ch
+					, rfctl->ch_sel_same_band_prefer, mesh_only);
+	}
+
+exit:
+	if (ch_avail == _FALSE)
+		RTW_WARN("%s no available channel\n", caller);
+
+	return ch_avail;
+}
+
+u8 rtw_ap_chbw_decision(_adapter *adapter, u8 ifbmp, u8 excl_ifbmp
+	, s16 req_ch, s8 req_bw, s8 req_offset
+	, u8 *ch, u8 *bw, u8 *offset, u8 *chbw_allow)
+{
+	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
+	RT_CHANNEL_INFO *chset = adapter_to_chset(adapter);
+	struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter);
+	bool ch_avail = _FALSE;
+	u8 cur_ie_ch[CONFIG_IFACE_NUMBER] = {0};
+	u8 cur_ie_bw[CONFIG_IFACE_NUMBER] = {0};
+	u8 cur_ie_offset[CONFIG_IFACE_NUMBER] = {0};
+	u8 dec_ch[CONFIG_IFACE_NUMBER] = {0};
+	u8 dec_bw[CONFIG_IFACE_NUMBER] = {0};
+	u8 dec_offset[CONFIG_IFACE_NUMBER] = {0};
+	u8 u_ch = 0, u_bw = 0, u_offset = 0;
+	struct mlme_ext_priv *mlmeext;
+	WLAN_BSSID_EX *network;
+	struct mi_state mstate;
+	struct mi_state mstate_others;
+	bool set_u_ch = _FALSE;
+	u8 ifbmp_others = 0xFF & ~ifbmp & ~excl_ifbmp;
+	u8 ifbmp_ch_changed = 0;
+	bool ifbmp_all_mesh = 0;
+	_adapter *iface;
+	int i;
+
+#ifdef CONFIG_RTW_MESH
+	for (i = 0; i < dvobj->iface_nums; i++)
+		if ((ifbmp & BIT(i)) && dvobj->padapters)
+			if (!MLME_IS_MESH(dvobj->padapters[i]))
+				break;
+	ifbmp_all_mesh = i >= dvobj->iface_nums ? 1 : 0;
+#endif
+
+	RTW_INFO("%s ifbmp:0x%02x excl_ifbmp:0x%02x req:%d,%d,%d\n", __func__
+		, ifbmp, excl_ifbmp, req_ch, req_bw, req_offset);
+	rtw_mi_status_by_ifbmp(dvobj, ifbmp, &mstate);
+	rtw_mi_status_by_ifbmp(dvobj, ifbmp_others, &mstate_others);
+	RTW_INFO("%s others ld_sta_num:%u, lg_sta_num:%u, ap_num:%u, mesh_num:%u\n"
+		, __func__, MSTATE_STA_LD_NUM(&mstate_others), MSTATE_STA_LG_NUM(&mstate_others)
+		, MSTATE_AP_NUM(&mstate_others), MSTATE_MESH_NUM(&mstate_others));
+
+	for (i = 0; i < dvobj->iface_nums; i++) {
+		if (!(ifbmp & BIT(i)) || !dvobj->padapters[i])
+			continue;
+		iface = dvobj->padapters[i];
+		mlmeext = &(iface->mlmeextpriv);
+		network = &(mlmeext->mlmext_info.network);
+
+		/* get current IE channel settings */
+		rtw_ies_get_chbw(BSS_EX_TLV_IES(network), BSS_EX_TLV_IES_LEN(network)
+			, &cur_ie_ch[i], &cur_ie_bw[i], &cur_ie_offset[i], 1, 1);
+
+		/* prepare temporary channel setting decision */
+		if (req_ch == 0) {
+			/* request comes from upper layer, use cur_ie values */
+			dec_ch[i] = cur_ie_ch[i];
+			dec_bw[i] = cur_ie_bw[i];
+			dec_offset[i] = cur_ie_offset[i];
+		} else {
+			/* use chbw of cur_ie updated with specifying req as temporary decision */
+			dec_ch[i] = (req_ch <= REQ_CH_NONE) ? cur_ie_ch[i] : req_ch;
+			if (req_bw <= REQ_BW_NONE) {
+				if (req_bw == REQ_BW_ORI)
+					dec_bw[i] = iface->mlmepriv.ori_bw;
+				else
+					dec_bw[i] = cur_ie_bw[i];
+			} else
+				dec_bw[i] = req_bw;
+			dec_offset[i] = (req_offset <= REQ_OFFSET_NONE) ? cur_ie_offset[i] : req_offset;
+		}
+	}
+
+	if (MSTATE_STA_LD_NUM(&mstate_others) || MSTATE_STA_LG_NUM(&mstate_others)
+		|| MSTATE_AP_NUM(&mstate_others) || MSTATE_MESH_NUM(&mstate_others)
+	) {
+		/* has linked/linking STA or has AP/Mesh mode */
+		rtw_warn_on(!rtw_mi_get_ch_setting_union_by_ifbmp(dvobj, ifbmp_others, &u_ch, &u_bw, &u_offset));
+		RTW_INFO("%s others union:%u,%u,%u\n", __func__, u_ch, u_bw, u_offset);
+	}
+
+#ifdef CONFIG_MCC_MODE
+	if (MCC_EN(adapter) && req_ch == 0) {
+		if (rtw_hal_check_mcc_status(adapter, MCC_STATUS_DOING_MCC)) {
+			u8 if_id = adapter->iface_id;
+
+			mlmeext = &(adapter->mlmeextpriv);
+
+			/* check channel settings are the same */
+			if (cur_ie_ch[if_id] == mlmeext->cur_channel
+				&& cur_ie_bw[if_id] == mlmeext->cur_bwmode
+				&& cur_ie_offset[if_id] == mlmeext->cur_ch_offset) {
+
+				RTW_INFO(FUNC_ADPT_FMT"req ch settings are the same as current ch setting, go to exit\n"
+					, FUNC_ADPT_ARG(adapter));
+
+				*chbw_allow = _FALSE;
+				goto exit;
+			} else {
+				RTW_INFO(FUNC_ADPT_FMT"request channel settings are not the same as current channel setting(%d,%d,%d,%d,%d,%d), restart MCC\n"
+					, FUNC_ADPT_ARG(adapter)
+					, cur_ie_ch[if_id], cur_ie_bw[if_id], cur_ie_offset[if_id]
+					, mlmeext->cur_channel, mlmeext->cur_bwmode, mlmeext->cur_ch_offset);
+
+				rtw_hal_set_mcc_setting_disconnect(adapter);
+			}
+		}	
+	}
+#endif /* CONFIG_MCC_MODE */
+
+	if (MSTATE_STA_LG_NUM(&mstate_others) && !MSTATE_STA_LD_NUM(&mstate_others)) {
+		/* has linking STA but no linked STA */
+
+		for (i = 0; i < dvobj->iface_nums; i++) {
+			if (!(ifbmp & BIT(i)) || !dvobj->padapters[i])
+				continue;
+			iface = dvobj->padapters[i];
+
+			rtw_adjust_chbw(iface, dec_ch[i], &dec_bw[i], &dec_offset[i]);
+			#ifdef CONFIG_RTW_MESH
+			if (MLME_IS_MESH(iface))
+				rtw_mesh_adjust_chbw(dec_ch[i], &dec_bw[i], &dec_offset[i]);
+			#endif
+
+			if (rtw_is_chbw_grouped(u_ch, u_bw, u_offset, dec_ch[i], dec_bw[i], dec_offset[i])) {
+				rtw_chset_sync_chbw(chset
+					, &dec_ch[i], &dec_bw[i], &dec_offset[i]
+					, &u_ch, &u_bw, &u_offset);
+				set_u_ch = _TRUE;
+
+				/* channel bw offset can be allowed, not need MCC */
+				*chbw_allow = _TRUE;
+			} else {
+				#ifdef CONFIG_MCC_MODE
+				if (MCC_EN(iface)) {
+					mlmeext = &(iface->mlmeextpriv);
+					mlmeext->cur_channel = *ch = dec_ch[i];
+					mlmeext->cur_bwmode = *bw = dec_bw[i];
+					mlmeext->cur_ch_offset = *offset = dec_offset[i];
+
+					/* channel bw offset can not be allowed, need MCC */
+					*chbw_allow = _FALSE;
+					RTW_INFO(FUNC_ADPT_FMT" enable mcc: %u,%u,%u\n", FUNC_ADPT_ARG(iface)
+						 , *ch, *bw, *offset);
+					goto exit;
+				}
+				#endif /* CONFIG_MCC_MODE */
+
+				/* set this for possible ch change when join down*/
+				set_fwstate(&iface->mlmepriv, WIFI_OP_CH_SWITCHING);
+			}
+		}
+
+	} else if (MSTATE_STA_LD_NUM(&mstate_others)
+		|| MSTATE_AP_NUM(&mstate_others) || MSTATE_MESH_NUM(&mstate_others)
+	) {
+		/* has linked STA mode or AP/Mesh mode */
+
+		for (i = 0; i < dvobj->iface_nums; i++) {
+			if (!(ifbmp & BIT(i)) || !dvobj->padapters[i])
+				continue;
+			iface = dvobj->padapters[i];
+
+			rtw_adjust_chbw(iface, u_ch, &dec_bw[i], &dec_offset[i]);
+			#ifdef CONFIG_RTW_MESH
+			if (MLME_IS_MESH(iface))
+				rtw_mesh_adjust_chbw(u_ch, &dec_bw[i], &dec_offset[i]);
+			#endif
+
+			#ifdef CONFIG_MCC_MODE
+			if (MCC_EN(iface)) {
+				if (!rtw_is_chbw_grouped(u_ch, u_bw, u_offset, dec_ch[i], dec_bw[i], dec_offset[i])) {
+					mlmeext = &(iface->mlmeextpriv);
+					mlmeext->cur_channel = *ch = dec_ch[i] = cur_ie_ch[i];
+					mlmeext->cur_bwmode = *bw = dec_bw[i] = cur_ie_bw[i];
+					mlmeext->cur_ch_offset = *offset = dec_offset[i] = cur_ie_offset[i];
+					/* channel bw offset can not be allowed, need MCC */
+					*chbw_allow = _FALSE;
+					RTW_INFO(FUNC_ADPT_FMT" enable mcc: %u,%u,%u\n", FUNC_ADPT_ARG(iface)
+						 , *ch, *bw, *offset);
+					goto exit;
+				} else
+					/* channel bw offset can be allowed, not need MCC */
+					*chbw_allow = _TRUE;
+			}
+			#endif /* CONFIG_MCC_MODE */
+
+			if (req_ch == 0 && dec_bw[i] > u_bw
+				&& rtw_is_dfs_chbw(u_ch, u_bw, u_offset)
+			) {
+				/* request comes from upper layer, prevent from additional channel waiting */
+				dec_bw[i] = u_bw;
+				if (dec_bw[i] == CHANNEL_WIDTH_20)
+					dec_offset[i] = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
+			}
+
+			/* follow */
+			rtw_chset_sync_chbw(chset
+				, &dec_ch[i], &dec_bw[i], &dec_offset[i]
+				, &u_ch, &u_bw, &u_offset);
+		}
+
+		set_u_ch = _TRUE;
+
+	} else {
+		/* autonomous decision */
+		u8 ori_ch = 0;
+		u8 max_bw;
+
+		/* autonomous decision, not need MCC */
+		*chbw_allow = _TRUE;
+
+		if (req_ch <= REQ_CH_NONE) /* channel is not specified */
+			goto choose_chbw;
+
+		/* get tmp dec union of ifbmp */
+		for (i = 0; i < dvobj->iface_nums; i++) {
+			if (!(ifbmp & BIT(i)) || !dvobj->padapters[i])
+				continue;
+			if (u_ch == 0) {
+				u_ch = dec_ch[i];
+				u_bw = dec_bw[i];
+				u_offset = dec_offset[i];
+				rtw_adjust_chbw(adapter, u_ch, &u_bw, &u_offset);
+				rtw_get_offset_by_chbw(u_ch, u_bw, &u_offset);
+			} else {
+				u8 tmp_ch = dec_ch[i];
+				u8 tmp_bw = dec_bw[i];
+				u8 tmp_offset = dec_offset[i];
+				
+				rtw_adjust_chbw(adapter, tmp_ch, &tmp_bw, &tmp_offset);
+				rtw_get_offset_by_chbw(tmp_ch, tmp_bw, &tmp_offset);
+
+				rtw_warn_on(!rtw_is_chbw_grouped(u_ch, u_bw, u_offset, tmp_ch, tmp_bw, tmp_offset));
+				rtw_sync_chbw(&tmp_ch, &tmp_bw, &tmp_offset, &u_ch, &u_bw, &u_offset);
+			}
+		}
+
+		#ifdef CONFIG_RTW_MESH
+		/* if ifbmp are all mesh, apply bw restriction */
+		if (ifbmp_all_mesh)
+			rtw_mesh_adjust_chbw(u_ch, &u_bw, &u_offset);
+		#endif
+
+		RTW_INFO("%s ifbmp:0x%02x tmp union:%u,%u,%u\n", __func__, ifbmp, u_ch, u_bw, u_offset);
+
+		/* check if tmp dec union is usable */
+		if (rtw_ap_ch_specific_chk(adapter, u_ch, &u_bw, &u_offset, __func__) == _FAIL) {
+			/* channel can't be used */
+			if (req_ch > 0) {
+				/* specific channel and not from IE => don't change channel setting */
+				goto exit;
+			}
+			goto choose_chbw;
+		} else if (rtw_chset_is_chbw_non_ocp(chset, u_ch, u_bw, u_offset)) {
+			RTW_WARN("%s DFS channel %u,%u under non ocp\n", __func__, u_ch, u_bw);
+			if (req_ch > 0 && req_bw > REQ_BW_NONE) {
+				/* change_chbw with specific channel and specific bw, goto update_bss_chbw directly */
+				goto update_bss_chbw;
+			}
+		} else
+			goto update_bss_chbw;
+
+choose_chbw:
+		req_ch = req_ch > 0 ? req_ch : 0;
+		max_bw = req_bw > REQ_BW_NONE ? req_bw : CHANNEL_WIDTH_20;
+		for (i = 0; i < dvobj->iface_nums; i++) {
+			if (!(ifbmp & BIT(i)) || !dvobj->padapters[i])
+				continue;
+			iface = dvobj->padapters[i];
+			mlmeext = &(iface->mlmeextpriv);
+
+			if (req_bw <= REQ_BW_NONE) {
+				if (req_bw == REQ_BW_ORI) {
+					if (max_bw < iface->mlmepriv.ori_bw)
+						max_bw = iface->mlmepriv.ori_bw;
+				} else {
+					if (max_bw < cur_ie_bw[i])
+						max_bw = cur_ie_bw[i];
+				}
+			}
+
+			if (MSTATE_AP_NUM(&mstate) || MSTATE_MESH_NUM(&mstate)) {
+				if (ori_ch == 0)
+					ori_ch = mlmeext->cur_channel;
+				else if (ori_ch != mlmeext->cur_channel)
+					rtw_warn_on(1);
+			} else {
+				if (ori_ch == 0)
+					ori_ch = cur_ie_ch[i];
+				else if (ori_ch != cur_ie_ch[i])
+					rtw_warn_on(1);
+			}
+		}
+
+		ch_avail = rtw_ap_choose_chbw(adapter, req_ch, max_bw
+			, ori_ch, &u_ch, &u_bw, &u_offset, ifbmp_all_mesh, __func__);
+		if (ch_avail == _FALSE)
+			goto exit;
+
+update_bss_chbw:
+		for (i = 0; i < dvobj->iface_nums; i++) {
+			if (!(ifbmp & BIT(i)) || !dvobj->padapters[i])
+				continue;
+			iface = dvobj->padapters[i];
+
+			dec_ch[i] = u_ch;
+			if (dec_bw[i] > u_bw)
+				dec_bw[i] = u_bw;
+			if (dec_bw[i] == CHANNEL_WIDTH_20)
+				dec_offset[i] = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
+			else
+				dec_offset[i] = u_offset;
+
+			#ifdef CONFIG_RTW_MESH
+			if (MLME_IS_MESH(iface))
+				rtw_mesh_adjust_chbw(dec_ch[i], &dec_bw[i], &dec_offset[i]);
+			#endif
+		}
+
+		set_u_ch = _TRUE;
+	}
+
+	ifbmp_ch_changed = rtw_ap_update_chbw_by_ifbmp(dvobj, ifbmp
+							, cur_ie_ch, cur_ie_bw, cur_ie_offset
+							, dec_ch, dec_bw, dec_offset
+							, __func__);
+
+	if (u_ch != 0)
+		RTW_INFO("%s union:%u,%u,%u\n", __func__, u_ch, u_bw, u_offset);
+
+	if (rtw_mi_check_fwstate(adapter, _FW_UNDER_SURVEY)) {
+		/* scanning, leave ch setting to scan state machine */
+		set_u_ch = _FALSE;
+	}
+
+	if (set_u_ch == _TRUE) {
+		*ch = u_ch;
+		*bw = u_bw;
+		*offset = u_offset;
+	}
+exit:
+	return ifbmp_ch_changed;
+}
+
+u8 rtw_ap_sta_states_check(_adapter *adapter)
+{
+	struct sta_info *psta;
+	struct sta_priv *pstapriv = &adapter->stapriv;
+	_list *plist, *phead;
+	_irqL irqL;
+	u8 rst = _FALSE;
+
+	if (!MLME_IS_AP(adapter) && !MLME_IS_MESH(adapter))
+		return _FALSE;
+
+	if (pstapriv->auth_list_cnt !=0)
+		return _TRUE;
+
+	_enter_critical_bh(&pstapriv->asoc_list_lock, &irqL);
+	phead = &pstapriv->asoc_list;
+	plist = get_next(phead);
+	while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) {
+
+		psta = LIST_CONTAINOR(plist, struct sta_info, asoc_list);
+		plist = get_next(plist);
+
+		if (!(psta->state & _FW_LINKED)) {
+			RTW_INFO(ADPT_FMT"- SoftAP/Mesh - sta under linking, its state = 0x%x\n", ADPT_ARG(adapter), psta->state);
+			rst = _TRUE;
+			break;
+		} else if (psta->state & WIFI_UNDER_KEY_HANDSHAKE) {
+			RTW_INFO(ADPT_FMT"- SoftAP/Mesh - sta under key handshaking, its state = 0x%x\n", ADPT_ARG(adapter), psta->state);
+			rst = _TRUE;
+			break;
+		}
+	}
+	_exit_critical_bh(&pstapriv->asoc_list_lock, &irqL);
+	return rst;
+}
+
+/*#define DBG_SWTIMER_BASED_TXBCN*/
+#ifdef CONFIG_SWTIMER_BASED_TXBCN
+void tx_beacon_handlder(struct dvobj_priv *pdvobj)
+{
+#define BEACON_EARLY_TIME		20	/* unit:TU*/
+	_irqL irqL;
+	_list	*plist, *phead;
+	u32 timestamp[2];
+	u32 bcn_interval_us; /* unit : usec */
+	u64 time;
+	u32 cur_tick, time_offset; /* unit : usec */
+	u32 inter_bcn_space_us; /* unit : usec */
+	u32 txbcn_timer_ms; /* unit : ms */
+	int nr_vap, idx, bcn_idx;
+	int i;
+	u8 val8, late = 0;
+	_adapter *padapter = NULL;
+
+	i = 0;
+
+	/* get first ap mode interface */
+	_enter_critical_bh(&pdvobj->ap_if_q.lock, &irqL);
+	if (rtw_is_list_empty(&pdvobj->ap_if_q.queue) || (pdvobj->nr_ap_if == 0)) {
+		RTW_INFO("[%s] ERROR: ap_if_q is empty!or nr_ap = %d\n", __func__, pdvobj->nr_ap_if);
+		_exit_critical_bh(&pdvobj->ap_if_q.lock, &irqL);
+		return;
+	} else
+		padapter = LIST_CONTAINOR(get_next(&(pdvobj->ap_if_q.queue)), struct _ADAPTER, list);
+	_exit_critical_bh(&pdvobj->ap_if_q.lock, &irqL);
+
+	if (NULL == padapter) {
+		RTW_INFO("[%s] ERROR: no any ap interface!\n", __func__);
+		return;
+	}
+
+
+	bcn_interval_us = DEFAULT_BCN_INTERVAL * NET80211_TU_TO_US;
+	if (0 == bcn_interval_us) {
+		RTW_INFO("[%s] ERROR: beacon interval = 0\n", __func__);
+		return;
+	}
+
+	/* read TSF */
+	timestamp[1] = rtw_read32(padapter, 0x560 + 4);
+	timestamp[0] = rtw_read32(padapter, 0x560);
+	while (timestamp[1]) {
+		time = (0xFFFFFFFF % bcn_interval_us + 1) * timestamp[1] + timestamp[0];
+		timestamp[0] = (u32)time;
+		timestamp[1] = (u32)(time >> 32);
+	}
+	cur_tick = timestamp[0] % bcn_interval_us;
+
+
+	_enter_critical_bh(&pdvobj->ap_if_q.lock, &irqL);
+
+	nr_vap = (pdvobj->nr_ap_if - 1);
+	if (nr_vap > 0) {
+		inter_bcn_space_us = pdvobj->inter_bcn_space * NET80211_TU_TO_US; /* beacon_interval / (nr_vap+1); */
+		idx = cur_tick / inter_bcn_space_us;
+		if (idx < nr_vap)	/* if (idx < (nr_vap+1))*/
+			bcn_idx = idx + 1;	/* bcn_idx = (idx + 1) % (nr_vap+1);*/
+		else
+			bcn_idx = 0;
+
+		/* to get padapter based on bcn_idx */
+		padapter = NULL;
+		phead = get_list_head(&pdvobj->ap_if_q);
+		plist = get_next(phead);
+		while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) {
+			padapter = LIST_CONTAINOR(plist, struct _ADAPTER, list);
+
+			plist = get_next(plist);
+
+			if (i == bcn_idx)
+				break;
+
+			i++;
+		}
+		if ((NULL == padapter) || (i > pdvobj->nr_ap_if)) {
+			RTW_INFO("[%s] ERROR: nr_ap_if = %d, padapter=%p, bcn_idx=%d, index=%d\n",
+				__func__, pdvobj->nr_ap_if, padapter, bcn_idx, i);
+			_exit_critical_bh(&pdvobj->ap_if_q.lock, &irqL);
+			return;
+		}
+#ifdef DBG_SWTIMER_BASED_TXBCN
+		RTW_INFO("BCN_IDX=%d, cur_tick=%d, padapter=%p\n", bcn_idx, cur_tick, padapter);
+#endif
+		if (((idx + 2 == nr_vap + 1) && (idx < nr_vap + 1)) || (0 == bcn_idx)) {
+			time_offset = bcn_interval_us - cur_tick - BEACON_EARLY_TIME * NET80211_TU_TO_US;
+			if ((s32)time_offset < 0)
+				time_offset += inter_bcn_space_us;
+
+		} else {
+			time_offset = (idx + 2) * inter_bcn_space_us - cur_tick - BEACON_EARLY_TIME * NET80211_TU_TO_US;
+			if (time_offset > (inter_bcn_space_us + (inter_bcn_space_us >> 1))) {
+				time_offset -= inter_bcn_space_us;
+				late = 1;
+			}
+		}
+	} else
+		/*#endif*/ { /* MBSSID */
+		time_offset = 2 * bcn_interval_us - cur_tick - BEACON_EARLY_TIME * NET80211_TU_TO_US;
+		if (time_offset > (bcn_interval_us + (bcn_interval_us >> 1))) {
+			time_offset -= bcn_interval_us;
+			late = 1;
+		}
+	}
+	_exit_critical_bh(&pdvobj->ap_if_q.lock, &irqL);
+
+#ifdef DBG_SWTIMER_BASED_TXBCN
+	RTW_INFO("set sw bcn timer %d us\n", time_offset);
+#endif
+	txbcn_timer_ms = time_offset / NET80211_TU_TO_US;
+	_set_timer(&pdvobj->txbcn_timer, txbcn_timer_ms);
+
+	if (padapter) {
+#ifdef CONFIG_BCN_RECOVERY
+		rtw_ap_bcn_recovery(padapter);
+#endif /*CONFIG_BCN_RECOVERY*/
+
+#ifdef CONFIG_BCN_XMIT_PROTECT
+		rtw_ap_bcn_queue_empty_check(padapter, txbcn_timer_ms);
+#endif /*CONFIG_BCN_XMIT_PROTECT*/
+
+#ifdef DBG_SWTIMER_BASED_TXBCN
+		RTW_INFO("padapter=%p, PORT=%d\n", padapter, padapter->hw_port);
+#endif
+		/* bypass TX BCN queue if op ch is switching/waiting */
+		if (!check_fwstate(&padapter->mlmepriv, WIFI_OP_CH_SWITCHING)
+			&& !IS_CH_WAITING(adapter_to_rfctl(padapter))
+		) {
+			/*update_beacon(padapter, _TIM_IE_, NULL, _FALSE);*/
+			/*issue_beacon(padapter, 0);*/
+			send_beacon(padapter);
+		}
+	}
+
+#if 0
+	/* handle any buffered BC/MC frames*/
+	/* Don't dynamically change DIS_ATIM due to HW will auto send ACQ after HIQ empty.*/
+	val8 = *((unsigned char *)priv->beaconbuf + priv->timoffset + 4);
+	if (val8 & 0x01) {
+		process_mcast_dzqueue(priv);
+		priv->pkt_in_dtimQ = 0;
+	}
+#endif
+
+}
+
+void tx_beacon_timer_handlder(void *ctx)
+{
+	struct dvobj_priv *pdvobj = (struct dvobj_priv *)ctx;
+	_adapter *padapter = pdvobj->padapters[0];
+
+	if (padapter)
+		set_tx_beacon_cmd(padapter);
+}
+#endif
+
+void rtw_ap_parse_sta_capability(_adapter *adapter, struct sta_info *sta, u8 *cap)
+{
+	sta->capability = RTW_GET_LE16(cap);
+	if (sta->capability & WLAN_CAPABILITY_SHORT_PREAMBLE)
+		sta->flags |= WLAN_STA_SHORT_PREAMBLE;
+	else
+		sta->flags &= ~WLAN_STA_SHORT_PREAMBLE;
+}
+
+u16 rtw_ap_parse_sta_supported_rates(_adapter *adapter, struct sta_info *sta, u8 *tlv_ies, u16 tlv_ies_len)
+{
+	u8 rate_set[12];
+	u8 rate_num;
+	int i;
+	u16 status = _STATS_SUCCESSFUL_;
+
+	rtw_ies_get_supported_rate(tlv_ies, tlv_ies_len, rate_set, &rate_num);
+	if (rate_num == 0) {
+		RTW_INFO(FUNC_ADPT_FMT" sta "MAC_FMT" with no supported rate\n"
+			, FUNC_ADPT_ARG(adapter), MAC_ARG(sta->cmn.mac_addr));
+		status = _STATS_FAILURE_;
+		goto exit;
+	}
+
+	_rtw_memcpy(sta->bssrateset, rate_set, rate_num);
+	sta->bssratelen = rate_num;
+
+	if (MLME_IS_AP(adapter)) {
+		/* this function force only CCK rates to be bassic rate... */
+		UpdateBrateTblForSoftAP(sta->bssrateset, sta->bssratelen);
+	}
+
+	/* if (hapd->iface->current_mode->mode == HOSTAPD_MODE_IEEE80211G) */ /* ? */
+	sta->flags |= WLAN_STA_NONERP;
+	for (i = 0; i < sta->bssratelen; i++) {
+		if ((sta->bssrateset[i] & 0x7f) > 22) {
+			sta->flags &= ~WLAN_STA_NONERP;
+			break;
+		}
+	}
+
+exit:
+	return status;
+}
+
+u16 rtw_ap_parse_sta_security_ie(_adapter *adapter, struct sta_info *sta, struct rtw_ieee802_11_elems *elems)
+{
+	struct security_priv *sec = &adapter->securitypriv;
+	u8 *wpa_ie;
+	int wpa_ie_len;
+	int group_cipher = 0, pairwise_cipher = 0;
+	u8 mfp_opt = MFP_NO;
+	u16 status = _STATS_SUCCESSFUL_;
+
+	sta->dot8021xalg = 0;
+	sta->wpa_psk = 0;
+	sta->wpa_group_cipher = 0;
+	sta->wpa2_group_cipher = 0;
+	sta->wpa_pairwise_cipher = 0;
+	sta->wpa2_pairwise_cipher = 0;
+	_rtw_memset(sta->wpa_ie, 0, sizeof(sta->wpa_ie));
+
+	if ((sec->wpa_psk & BIT(1)) && elems->rsn_ie) {
+		wpa_ie = elems->rsn_ie;
+		wpa_ie_len = elems->rsn_ie_len;
+
+		if (rtw_parse_wpa2_ie(wpa_ie - 2, wpa_ie_len + 2, &group_cipher, &pairwise_cipher, NULL, &mfp_opt) == _SUCCESS) {
+			sta->dot8021xalg = 1;/* psk, todo:802.1x */
+			sta->wpa_psk |= BIT(1);
+
+			sta->wpa2_group_cipher = group_cipher & sec->wpa2_group_cipher;
+			sta->wpa2_pairwise_cipher = pairwise_cipher & sec->wpa2_pairwise_cipher;
+
+			if (!sta->wpa2_group_cipher)
+				status = WLAN_STATUS_GROUP_CIPHER_NOT_VALID;
+
+			if (!sta->wpa2_pairwise_cipher)
+				status = WLAN_STATUS_PAIRWISE_CIPHER_NOT_VALID;
+		} else
+			status = WLAN_STATUS_INVALID_IE;
+
+	}
+	else if ((sec->wpa_psk & BIT(0)) && elems->wpa_ie) {
+		wpa_ie = elems->wpa_ie;
+		wpa_ie_len = elems->wpa_ie_len;
+
+		if (rtw_parse_wpa_ie(wpa_ie - 2, wpa_ie_len + 2, &group_cipher, &pairwise_cipher, NULL) == _SUCCESS) {
+			sta->dot8021xalg = 1;/* psk, todo:802.1x */
+			sta->wpa_psk |= BIT(0);
+
+			sta->wpa_group_cipher = group_cipher & sec->wpa_group_cipher;
+			sta->wpa_pairwise_cipher = pairwise_cipher & sec->wpa_pairwise_cipher;
+
+			if (!sta->wpa_group_cipher)
+				status = WLAN_STATUS_GROUP_CIPHER_NOT_VALID;
+
+			if (!sta->wpa_pairwise_cipher)
+				status = WLAN_STATUS_PAIRWISE_CIPHER_NOT_VALID;
+		} else
+			status = WLAN_STATUS_INVALID_IE;
+
+	} else {
+		wpa_ie = NULL;
+		wpa_ie_len = 0;
+	}
+
+#ifdef CONFIG_RTW_MESH
+	if (MLME_IS_MESH(adapter)) {
+		/* MFP is mandatory for secure mesh */
+		if (adapter->mesh_info.mesh_auth_id)
+			sta->flags |= WLAN_STA_MFP;
+	} else
+#endif
+	if ((sec->mfp_opt == MFP_REQUIRED && mfp_opt == MFP_NO) || mfp_opt == MFP_INVALID) 
+		status = WLAN_STATUS_ROBUST_MGMT_FRAME_POLICY_VIOLATION;
+	else if (sec->mfp_opt >= MFP_OPTIONAL && mfp_opt >= MFP_OPTIONAL)
+		sta->flags |= WLAN_STA_MFP;
+
+	if (status != _STATS_SUCCESSFUL_)
+		goto exit;
+
+	if (!MLME_IS_AP(adapter))
+		goto exit;
+
+	sta->flags &= ~(WLAN_STA_WPS | WLAN_STA_MAYBE_WPS);
+	/* if (hapd->conf->wps_state && wpa_ie == NULL) { */ /* todo: to check ap if supporting WPS */
+	if (wpa_ie == NULL) {
+		if (elems->wps_ie) {
+			RTW_INFO("STA included WPS IE in "
+				 "(Re)Association Request - assume WPS is "
+				 "used\n");
+			sta->flags |= WLAN_STA_WPS;
+			/* wpabuf_free(sta->wps_ie); */
+			/* sta->wps_ie = wpabuf_alloc_copy(elems.wps_ie + 4, */
+			/*				elems.wps_ie_len - 4); */
+		} else {
+			RTW_INFO("STA did not include WPA/RSN IE "
+				 "in (Re)Association Request - possible WPS "
+				 "use\n");
+			sta->flags |= WLAN_STA_MAYBE_WPS;
+		}
+
+		/* AP support WPA/RSN, and sta is going to do WPS, but AP is not ready */
+		/* that the selected registrar of AP is _FLASE */
+		if ((sec->wpa_psk > 0)
+			&& (sta->flags & (WLAN_STA_WPS | WLAN_STA_MAYBE_WPS))
+		) {
+			struct mlme_priv *mlme = &adapter->mlmepriv;
+
+			if (mlme->wps_beacon_ie) {
+				u8 selected_registrar = 0;
+
+				rtw_get_wps_attr_content(mlme->wps_beacon_ie, mlme->wps_beacon_ie_len, WPS_ATTR_SELECTED_REGISTRAR, &selected_registrar, NULL);
+
+				if (!selected_registrar) {
+					RTW_INFO("selected_registrar is _FALSE , or AP is not ready to do WPS\n");
+					status = _STATS_UNABLE_HANDLE_STA_;
+					goto exit;
+				}
+			}
+		}
+
+	} else {
+		int copy_len;
+
+		if (sec->wpa_psk == 0) {
+			RTW_INFO("STA " MAC_FMT
+				": WPA/RSN IE in association request, but AP don't support WPA/RSN\n",
+				MAC_ARG(sta->cmn.mac_addr));
+			status = WLAN_STATUS_INVALID_IE;
+			goto exit;
+		}
+
+		if (elems->wps_ie) {
+			RTW_INFO("STA included WPS IE in "
+				 "(Re)Association Request - WPS is "
+				 "used\n");
+			sta->flags |= WLAN_STA_WPS;
+			copy_len = 0;
+		} else
+			copy_len = ((wpa_ie_len + 2) > sizeof(sta->wpa_ie)) ? (sizeof(sta->wpa_ie)) : (wpa_ie_len + 2);
+
+		if (copy_len > 0)
+			_rtw_memcpy(sta->wpa_ie, wpa_ie - 2, copy_len);
+	}
+
+exit:
+	return status;
+}
+
+void rtw_ap_parse_sta_wmm_ie(_adapter *adapter, struct sta_info *sta, u8 *tlv_ies, u16 tlv_ies_len)
+{
+	struct mlme_priv *mlme = &adapter->mlmepriv;
+	unsigned char WMM_IE[] = {0x00, 0x50, 0xf2, 0x02, 0x00, 0x01};
+	u8 *p;
+
+	sta->flags &= ~WLAN_STA_WME;
+	sta->qos_option = 0;
+	sta->qos_info = 0;
+	sta->has_legacy_ac = _TRUE;
+	sta->uapsd_vo = 0;
+	sta->uapsd_vi = 0;
+	sta->uapsd_be = 0;
+	sta->uapsd_bk = 0;
+
+	if (!mlme->qospriv.qos_option)
+		goto exit;
+
+#ifdef CONFIG_RTW_MESH
+	if (MLME_IS_MESH(adapter)) {
+		/* QoS is mandatory in mesh */
+		sta->flags |= WLAN_STA_WME;
+	}
+#endif
+
+	p = rtw_get_ie_ex(tlv_ies, tlv_ies_len, WLAN_EID_VENDOR_SPECIFIC, WMM_IE, 6, NULL, NULL);
+	if (!p)
+		goto exit;
+
+	sta->flags |= WLAN_STA_WME;
+	sta->qos_option = 1;
+	sta->qos_info = *(p + 8);
+	sta->max_sp_len = (sta->qos_info >> 5) & 0x3;
+
+	if ((sta->qos_info & 0xf) != 0xf)
+		sta->has_legacy_ac = _TRUE;
+	else
+		sta->has_legacy_ac = _FALSE;
+
+	if (sta->qos_info & 0xf) {
+		if (sta->qos_info & BIT(0))
+			sta->uapsd_vo = BIT(0) | BIT(1);
+		else
+			sta->uapsd_vo = 0;
+
+		if (sta->qos_info & BIT(1))
+			sta->uapsd_vi = BIT(0) | BIT(1);
+		else
+			sta->uapsd_vi = 0;
+
+		if (sta->qos_info & BIT(2))
+			sta->uapsd_bk = BIT(0) | BIT(1);
+		else
+			sta->uapsd_bk = 0;
+
+		if (sta->qos_info & BIT(3))
+			sta->uapsd_be = BIT(0) | BIT(1);
+		else
+			sta->uapsd_be = 0;
+	}
+
+exit:
+	return;
+}
+
+void rtw_ap_parse_sta_ht_ie(_adapter *adapter, struct sta_info *sta, struct rtw_ieee802_11_elems *elems)
+{
+	struct mlme_priv *mlme = &adapter->mlmepriv;
+
+	sta->flags &= ~WLAN_STA_HT;
+
+#ifdef CONFIG_80211N_HT
+	if (mlme->htpriv.ht_option == _FALSE)
+		goto exit;
+
+	/* save HT capabilities in the sta object */
+	_rtw_memset(&sta->htpriv.ht_cap, 0, sizeof(struct rtw_ieee80211_ht_cap));
+	if (elems->ht_capabilities && elems->ht_capabilities_len >= sizeof(struct rtw_ieee80211_ht_cap)) {
+		sta->flags |= WLAN_STA_HT;
+		sta->flags |= WLAN_STA_WME;
+		_rtw_memcpy(&sta->htpriv.ht_cap, elems->ht_capabilities, sizeof(struct rtw_ieee80211_ht_cap));
+
+		if (elems->ht_operation && elems->ht_operation_len == HT_OP_IE_LEN) {
+			_rtw_memcpy(sta->htpriv.ht_op, elems->ht_operation, HT_OP_IE_LEN);
+			sta->htpriv.op_present = 1;
+		}
+	}
+exit:
+#endif
+
+	return;
+}
+
+void rtw_ap_parse_sta_vht_ie(_adapter *adapter, struct sta_info *sta, struct rtw_ieee802_11_elems *elems)
+{
+	struct mlme_priv *mlme = &adapter->mlmepriv;
+
+	sta->flags &= ~WLAN_STA_VHT;
+
+#ifdef CONFIG_80211AC_VHT
+	if (mlme->vhtpriv.vht_option == _FALSE)
+		goto exit;
+
+	_rtw_memset(&sta->vhtpriv, 0, sizeof(struct vht_priv));
+	if (elems->vht_capabilities && elems->vht_capabilities_len == VHT_CAP_IE_LEN) {
+		sta->flags |= WLAN_STA_VHT;
+		_rtw_memcpy(sta->vhtpriv.vht_cap, elems->vht_capabilities, VHT_CAP_IE_LEN);
+
+		if (elems->vht_operation && elems->vht_operation_len== VHT_OP_IE_LEN) {
+			_rtw_memcpy(sta->vhtpriv.vht_op, elems->vht_operation, VHT_OP_IE_LEN);
+			sta->vhtpriv.op_present = 1;
+		}
+
+		if (elems->vht_op_mode_notify && elems->vht_op_mode_notify_len == 1) {
+			_rtw_memcpy(&sta->vhtpriv.vht_op_mode_notify, elems->vht_op_mode_notify, 1);
+			sta->vhtpriv.notify_present = 1;
+		}
+	}
+exit:
+#endif
+
+	return;
+}
+#endif /* CONFIG_AP_MODE */
+
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/core/rtw_beamforming.c linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/core/rtw_beamforming.c
--- linux-5.6.3/3rdparty/rtl8821ce/core/rtw_beamforming.c	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/core/rtw_beamforming.c	2020-04-10 16:35:06.771657967 +0300
@@ -0,0 +1,3155 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#define _RTW_BEAMFORMING_C_
+
+#include <drv_types.h>
+#include <hal_data.h>
+
+#ifdef CONFIG_BEAMFORMING
+
+#ifdef RTW_BEAMFORMING_VERSION_2
+
+struct ndpa_sta_info {
+	u16 aid:12;
+	u16 feedback_type:1;
+	u16 nc_index:3;
+};
+
+static void _get_txvector_parameter(PADAPTER adapter, struct sta_info *sta, u8 *g_id, u16 *p_aid)
+{
+	struct mlme_priv *mlme;
+	u16 aid;
+	u8 *bssid;
+	u16 val16;
+	u8 i;
+
+
+	mlme = &adapter->mlmepriv;
+
+	if (check_fwstate(mlme, WIFI_AP_STATE)) {
+		/*
+		 * Sent by an AP and addressed to a STA associated with that AP
+		 * or sent by a DLS or TDLS STA in a direct path to
+		 * a DLS or TDLS peer STA
+		 */
+
+		aid = sta->cmn.aid;
+		bssid = adapter_mac_addr(adapter);
+		RTW_INFO("%s: AID=0x%x BSSID=" MAC_FMT "\n",
+			 __FUNCTION__, sta->cmn.aid, MAC_ARG(bssid));
+
+		/* AID[0:8] */
+		aid &= 0x1FF;
+		/* BSSID[44:47] xor BSSID[40:43] */
+		val16 = ((bssid[5] & 0xF0) >> 4) ^ (bssid[5] & 0xF);
+		/* (dec(AID[0:8]) + dec(BSSID)*2^5) mod 2^9 */
+		*p_aid = (aid + (val16 << 5)) & 0x1FF;
+		*g_id = 63;
+	} else if ((check_fwstate(mlme, WIFI_ADHOC_STATE) == _TRUE)
+		   || (check_fwstate(mlme, WIFI_ADHOC_MASTER_STATE) == _TRUE)) {
+		/*
+		 * Otherwise, includes
+		 * 1. Sent to an IBSS STA
+		 * 2. Sent by an AP to a non associated STA
+		 * 3. Sent to a STA for which it is not known
+		 *    which condition is applicable
+		 */
+		*p_aid = 0;
+		*g_id = 63;
+	} else {
+		/* Addressed to AP */
+		bssid = sta->cmn.mac_addr;
+		RTW_INFO("%s: BSSID=" MAC_FMT "\n", __FUNCTION__, MAC_ARG(bssid));
+
+		/* BSSID[39:47] */
+		*p_aid = (bssid[5] << 1) | (bssid[4] >> 7);
+		*g_id = 0;
+	}
+
+	RTW_INFO("%s: GROUP_ID=0x%02x PARTIAL_AID=0x%04x\n",
+		 __FUNCTION__, *g_id, *p_aid);
+}
+
+/*
+ * Parameters
+ *	adapter		struct _adapter*
+ *	sta		struct sta_info*
+ *	sta_bf_cap	beamforming capabe of sta
+ *	sounding_dim	Number of Sounding Dimensions
+ *	comp_steering	Compressed Steering Number of Beamformer Antennas Supported
+ */
+static void _get_sta_beamform_cap(PADAPTER adapter, struct sta_info *sta,
+	u8 *sta_bf_cap, u8 *sounding_dim, u8 *comp_steering)
+{
+	struct beamforming_info *info;
+	struct ht_priv *ht;
+#ifdef CONFIG_80211AC_VHT
+	struct vht_priv *vht;
+#endif /* CONFIG_80211AC_VHT */
+	u16 bf_cap;
+
+
+	*sta_bf_cap = 0;
+	*sounding_dim = 0;
+	*comp_steering = 0;
+
+	info = GET_BEAMFORM_INFO(adapter);
+	ht = &adapter->mlmepriv.htpriv;
+#ifdef CONFIG_80211AC_VHT
+	vht = &adapter->mlmepriv.vhtpriv;
+#endif /* CONFIG_80211AC_VHT */
+
+	if (is_supported_ht(sta->wireless_mode) == _TRUE) {
+		/* HT */
+		bf_cap = ht->beamform_cap;
+
+		if (TEST_FLAG(bf_cap, BEAMFORMING_HT_BEAMFORMEE_ENABLE)) {
+			info->beamforming_cap |= BEAMFORMEE_CAP_HT_EXPLICIT;
+			*sta_bf_cap |= BEAMFORMER_CAP_HT_EXPLICIT;
+			*sounding_dim = (bf_cap & BEAMFORMING_HT_BEAMFORMEE_CHNL_EST_CAP) >> 6;
+		}
+		if (TEST_FLAG(bf_cap, BEAMFORMING_HT_BEAMFORMER_ENABLE)) {
+			info->beamforming_cap |= BEAMFORMER_CAP_HT_EXPLICIT;
+			*sta_bf_cap |= BEAMFORMEE_CAP_HT_EXPLICIT;
+			*comp_steering = (bf_cap & BEAMFORMING_HT_BEAMFORMER_STEER_NUM) >> 4;
+		}
+	}
+
+#ifdef CONFIG_80211AC_VHT
+	if (is_supported_vht(sta->wireless_mode) == _TRUE) {
+		/* VHT */
+		bf_cap = vht->beamform_cap;
+
+		/* We are SU Beamformee because the STA is SU Beamformer */
+		if (TEST_FLAG(bf_cap, BEAMFORMING_VHT_BEAMFORMEE_ENABLE)) {
+			info->beamforming_cap |= BEAMFORMEE_CAP_VHT_SU;
+			*sta_bf_cap |= BEAMFORMER_CAP_VHT_SU;
+
+			/* We are MU Beamformee because the STA is MU Beamformer */
+			if (TEST_FLAG(bf_cap, BEAMFORMING_VHT_MU_MIMO_STA_ENABLE)) {
+				info->beamforming_cap |= BEAMFORMEE_CAP_VHT_MU;
+				*sta_bf_cap |= BEAMFORMER_CAP_VHT_MU;
+			}
+
+			*sounding_dim = (bf_cap & BEAMFORMING_VHT_BEAMFORMEE_SOUND_DIM) >> 12;
+		}
+		/* We are SU Beamformer because the STA is SU Beamformee */
+		if (TEST_FLAG(bf_cap, BEAMFORMING_VHT_BEAMFORMER_ENABLE)) {
+			info->beamforming_cap |= BEAMFORMER_CAP_VHT_SU;
+			*sta_bf_cap |= BEAMFORMEE_CAP_VHT_SU;
+
+			/* We are MU Beamformer because the STA is MU Beamformee */
+			if (TEST_FLAG(bf_cap, BEAMFORMING_VHT_MU_MIMO_AP_ENABLE)) {
+				info->beamforming_cap |= BEAMFORMER_CAP_VHT_MU;
+				*sta_bf_cap |= BEAMFORMEE_CAP_VHT_MU;
+			}
+
+			*comp_steering = (bf_cap & BEAMFORMING_VHT_BEAMFORMER_STS_CAP) >> 8;
+		}
+	}
+#endif /* CONFIG_80211AC_VHT */
+}
+
+static u8 _send_ht_ndpa_packet(PADAPTER adapter, u8 *ra, enum channel_width bw)
+{
+	/* General */
+	struct xmit_priv		*pxmitpriv;
+	struct mlme_ext_priv		*pmlmeext;
+	struct mlme_ext_info		*pmlmeinfo;
+	struct xmit_frame		*pmgntframe;
+	/* Beamforming */
+	struct beamforming_info		*info;
+	struct beamformee_entry		*bfee;
+	struct ndpa_sta_info		sta_info;
+	u8 ActionHdr[4] = {ACT_CAT_VENDOR, 0x00, 0xE0, 0x4C};
+	/* MISC */
+	struct pkt_attrib		*attrib;
+	struct rtw_ieee80211_hdr	*pwlanhdr;
+	enum MGN_RATE txrate;
+	u8 *pframe;
+	u16 duration = 0;
+	u8 aSifsTime = 0;
+
+
+	RTW_INFO("+%s: Send to " MAC_FMT "\n", __FUNCTION__, MAC_ARG(ra));
+
+	pxmitpriv = &adapter->xmitpriv;
+	pmlmeext = &adapter->mlmeextpriv;
+	pmlmeinfo = &pmlmeext->mlmext_info;
+	bfee = rtw_bf_bfee_get_entry_by_addr(adapter, ra);
+	if (!bfee) {
+		RTW_ERR("%s: Cann't find beamformee entry!\n", __FUNCTION__);
+		return _FALSE;
+	}
+
+	pmgntframe = alloc_mgtxmitframe(pxmitpriv);
+	if (!pmgntframe) {
+		RTW_ERR("%s: alloc mgnt frame fail!\n", __FUNCTION__);
+		return _FALSE;
+	}
+
+	txrate = beamforming_get_htndp_tx_rate(GET_PDM_ODM(adapter), bfee->comp_steering_num_of_bfer);
+
+	/* update attribute */
+	attrib = &pmgntframe->attrib;
+	update_mgntframe_attrib(adapter, attrib);
+	/*attrib->type = WIFI_MGT_TYPE;*/ /* set in update_mgntframe_attrib() */
+	attrib->subtype = WIFI_ACTION_NOACK;
+	attrib->bwmode = bw;
+	/*attrib->qsel = QSLT_MGNT;*/ /* set in update_mgntframe_attrib() */
+	attrib->order = 1;
+	attrib->rate = (u8)txrate;
+	attrib->bf_pkt_type = 0;
+
+	_rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET);
+	pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET;
+	pwlanhdr = (struct rtw_ieee80211_hdr *)pframe;
+
+	/* Frame control */
+	pwlanhdr->frame_ctl = 0;
+	set_frame_sub_type(pframe, attrib->subtype);
+	set_order_bit(pframe);
+
+	/* Duration */
+	if (pmlmeext->cur_wireless_mode == WIRELESS_11B)
+		aSifsTime = 10;
+	else
+		aSifsTime = 16;
+	duration = 2 * aSifsTime + 40;
+	if (bw == CHANNEL_WIDTH_40)
+		duration += 87;
+	else
+		duration += 180;
+	set_duration(pframe, duration);
+
+	/* DA */
+	_rtw_memcpy(pwlanhdr->addr1, ra, ETH_ALEN);
+	/* SA */
+	_rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(adapter), ETH_ALEN);
+	/* BSSID */
+	_rtw_memcpy(pwlanhdr->addr3, get_my_bssid(&pmlmeinfo->network), ETH_ALEN);
+
+	/* HT control field */
+	SET_HT_CTRL_CSI_STEERING(pframe + 24, 3);
+	SET_HT_CTRL_NDP_ANNOUNCEMENT(pframe + 24, 1);
+
+	/*
+	 * Frame Body
+	 * Category field: vender-specific value, 0x7F
+	 * OUI: 0x00E04C
+	 */
+	_rtw_memcpy(pframe + 28, ActionHdr, 4);
+
+	attrib->pktlen = 32;
+	attrib->last_txcmdsz = attrib->pktlen;
+
+	dump_mgntframe(adapter, pmgntframe);
+
+	return _TRUE;
+}
+
+static u8 _send_vht_ndpa_packet(PADAPTER adapter, u8 *ra, u16 aid, enum channel_width bw)
+{
+	/* General */
+	struct xmit_priv		*pxmitpriv;
+	struct mlme_ext_priv		*pmlmeext;
+	struct xmit_frame		*pmgntframe;
+	/* Beamforming */
+	struct beamforming_info		*info;
+	struct beamformee_entry		*bfee;
+	struct ndpa_sta_info		sta_info;
+	/* MISC */
+	struct pkt_attrib		*attrib;
+	struct rtw_ieee80211_hdr	*pwlanhdr;
+	u8 *pframe;
+	enum MGN_RATE txrate;
+	u16 duration = 0;
+	u8 sequence = 0, aSifsTime = 0;
+
+
+	RTW_INFO("+%s: Send to " MAC_FMT "\n", __FUNCTION__, MAC_ARG(ra));
+
+	pxmitpriv = &adapter->xmitpriv;
+	pmlmeext = &adapter->mlmeextpriv;
+	info = GET_BEAMFORM_INFO(adapter);
+	bfee = rtw_bf_bfee_get_entry_by_addr(adapter, ra);
+	if (!bfee) {
+		RTW_ERR("%s: Cann't find beamformee entry!\n", __FUNCTION__);
+		return _FALSE;
+	}
+
+	pmgntframe = alloc_mgtxmitframe(pxmitpriv);
+	if (!pmgntframe) {
+		RTW_ERR("%s: alloc mgnt frame fail!\n", __FUNCTION__);
+		return _FALSE;
+	}
+
+	txrate = beamforming_get_vht_ndp_tx_rate(GET_PDM_ODM(adapter), bfee->comp_steering_num_of_bfer);
+
+	/* update attribute */
+	attrib = &pmgntframe->attrib;
+	update_mgntframe_attrib(adapter, attrib);
+	/*pattrib->type = WIFI_MGT_TYPE;*/ /* set in update_mgntframe_attrib() */
+	attrib->subtype = WIFI_NDPA;
+	attrib->bwmode = bw;
+	/*attrib->qsel = QSLT_MGNT;*/ /* set in update_mgntframe_attrib() */
+	attrib->rate = (u8)txrate;
+	attrib->bf_pkt_type = 0;
+
+	_rtw_memset(pmgntframe->buf_addr, 0, TXDESC_OFFSET + WLANHDR_OFFSET);
+	pframe = pmgntframe->buf_addr + TXDESC_OFFSET;
+	pwlanhdr = (struct rtw_ieee80211_hdr *)pframe;
+
+	/* Frame control */
+	pwlanhdr->frame_ctl = 0;
+	set_frame_sub_type(pframe, attrib->subtype);
+
+	/* Duration */
+	if (is_supported_5g(pmlmeext->cur_wireless_mode) || is_supported_ht(pmlmeext->cur_wireless_mode))
+		aSifsTime = 16;
+	else
+		aSifsTime = 10;
+	duration = 2 * aSifsTime + 44;
+	if (bw == CHANNEL_WIDTH_80)
+		duration += 40;
+	else if (bw == CHANNEL_WIDTH_40)
+		duration += 87;
+	else
+		duration += 180;
+	set_duration(pframe, duration);
+
+	/* RA */
+	_rtw_memcpy(pwlanhdr->addr1, ra, ETH_ALEN);
+
+	/* TA */
+	_rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(adapter), ETH_ALEN);
+
+	/* Sounding Sequence, bit0~1 is reserved */
+	sequence = info->sounding_sequence << 2;
+	if (info->sounding_sequence >= 0x3f)
+		info->sounding_sequence = 0;
+	else
+		info->sounding_sequence++;
+	_rtw_memcpy(pframe + 16, &sequence, 1);
+
+	/* STA Info */
+	/*
+	 * "AID12" Equal to 0 if the STA is an AP, mesh STA or
+	 * STA that is a member of an IBSS
+	 */
+	if (check_fwstate(&adapter->mlmepriv, WIFI_AP_STATE) == _FALSE)
+		aid = 0;
+	sta_info.aid = aid;
+	/* "Feedback Type" set to 0 for SU */
+	sta_info.feedback_type = 0;
+	/* "Nc Index" reserved if the Feedback Type field indicates SU */
+	sta_info.nc_index = 0;
+	_rtw_memcpy(pframe + 17, (u8 *)&sta_info, 2);
+
+	attrib->pktlen = 19;
+	attrib->last_txcmdsz = attrib->pktlen;
+
+	dump_mgntframe(adapter, pmgntframe);
+
+	return _TRUE;
+}
+
+static u8 _send_vht_mu_ndpa_packet(PADAPTER adapter, enum channel_width bw)
+{
+	/* General */
+	struct xmit_priv		*pxmitpriv;
+	struct mlme_ext_priv		*pmlmeext;
+	struct xmit_frame		*pmgntframe;
+	/* Beamforming */
+	struct beamforming_info		*info;
+	struct sounding_info		*sounding;
+	struct beamformee_entry		*bfee;
+	struct ndpa_sta_info		sta_info;
+	/* MISC */
+	struct pkt_attrib		*attrib;
+	struct rtw_ieee80211_hdr	*pwlanhdr;
+	enum MGN_RATE txrate;
+	u8 *pframe;
+	u8 *ra = NULL;
+	u16 duration = 0;
+	u8 sequence = 0, aSifsTime = 0;
+	u8 i;
+
+
+	RTW_INFO("+%s\n", __FUNCTION__);
+
+	pxmitpriv = &adapter->xmitpriv;
+	pmlmeext = &adapter->mlmeextpriv;
+	info = GET_BEAMFORM_INFO(adapter);
+	sounding = &info->sounding_info;
+
+	txrate = MGN_VHT2SS_MCS0;
+
+	/*
+	 * Fill the first MU BFee entry (STA1) MAC addr to destination address then
+	 * HW will change A1 to broadcast addr.
+	 * 2015.05.28. Suggested by SD1 Chunchu.
+	 */
+	bfee = &info->bfee_entry[sounding->mu_sounding_list[0]];
+	ra = bfee->mac_addr;
+
+	pmgntframe = alloc_mgtxmitframe(pxmitpriv);
+	if (!pmgntframe) {
+		RTW_ERR("%s: alloc mgnt frame fail!\n", __FUNCTION__);
+		return _FALSE;
+	}
+
+	/* update attribute */
+	attrib = &pmgntframe->attrib;
+	update_mgntframe_attrib(adapter, attrib);
+	/*attrib->type = WIFI_MGT_TYPE;*/ /* set in update_mgntframe_attrib() */
+	attrib->subtype = WIFI_NDPA;
+	attrib->bwmode = bw;
+	/*attrib->qsel = QSLT_MGNT;*/ /* set in update_mgntframe_attrib() */
+	attrib->rate = (u8)txrate;
+	/* Set TxBFPktType of Tx desc to unicast type if there is only one MU STA for HW design */
+	if (info->sounding_info.candidate_mu_bfee_cnt > 1)
+		attrib->bf_pkt_type = 1;
+	else
+		attrib->bf_pkt_type = 0;
+
+	_rtw_memset(pmgntframe->buf_addr, 0, TXDESC_OFFSET + WLANHDR_OFFSET);
+	pframe = pmgntframe->buf_addr + TXDESC_OFFSET;
+	pwlanhdr = (struct rtw_ieee80211_hdr *)pframe;
+
+	/* Frame control */
+	pwlanhdr->frame_ctl = 0;
+	set_frame_sub_type(pframe, attrib->subtype);
+
+	/* Duration */
+	if (is_supported_5g(pmlmeext->cur_wireless_mode) || is_supported_ht(pmlmeext->cur_wireless_mode))
+		aSifsTime = 16;
+	else
+		aSifsTime = 10;
+	duration = 2 * aSifsTime + 44;
+	if (bw == CHANNEL_WIDTH_80)
+		duration += 40;
+	else if (bw == CHANNEL_WIDTH_40)
+		duration += 87;
+	else
+		duration += 180;
+	set_duration(pframe, duration);
+
+	/* RA */
+	_rtw_memcpy(pwlanhdr->addr1, ra, ETH_ALEN);
+
+	/* TA */
+	_rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(adapter), ETH_ALEN);
+
+	/* Sounding Sequence, bit0~1 is reserved */
+	sequence = info->sounding_sequence << 2;
+	if (info->sounding_sequence >= 0x3f)
+		info->sounding_sequence = 0;
+	else
+		info->sounding_sequence++;
+	_rtw_memcpy(pframe + 16, &sequence, 1);
+
+	attrib->pktlen = 17;
+
+	/*
+	 * Construct STA info. for multiple STAs
+	 * STA Info1, ..., STA Info n
+	 */
+	for (i = 0; i < sounding->candidate_mu_bfee_cnt; i++) {
+		bfee = &info->bfee_entry[sounding->mu_sounding_list[i]];
+		sta_info.aid = bfee->aid;
+		sta_info.feedback_type = 1; /* 1'b1: MU */
+		sta_info.nc_index = 0;
+		_rtw_memcpy(pframe + attrib->pktlen, (u8 *)&sta_info, 2);
+		attrib->pktlen += 2;
+	}
+
+	attrib->last_txcmdsz = attrib->pktlen;
+
+	dump_mgntframe(adapter, pmgntframe);
+
+	return _TRUE;
+}
+
+static u8 _send_bf_report_poll(PADAPTER adapter, u8 *ra, u8 bFinalPoll)
+{
+	/* General */
+	struct xmit_priv *pxmitpriv;
+	struct xmit_frame *pmgntframe;
+	/* MISC */
+	struct pkt_attrib *attrib;
+	struct rtw_ieee80211_hdr *pwlanhdr;
+	u8 *pframe;
+
+
+	RTW_INFO("+%s: Send to " MAC_FMT "\n", __FUNCTION__, MAC_ARG(ra));
+
+	pxmitpriv = &adapter->xmitpriv;
+
+	pmgntframe = alloc_mgtxmitframe(pxmitpriv);
+	if (!pmgntframe) {
+		RTW_ERR("%s: alloc mgnt frame fail!\n", __FUNCTION__);
+		return _FALSE;
+	}
+
+	/* update attribute */
+	attrib = &pmgntframe->attrib;
+	update_mgntframe_attrib(adapter, attrib);
+	/*attrib->type = WIFI_MGT_TYPE;*/ /* set in update_mgntframe_attrib() */
+	attrib->subtype = WIFI_BF_REPORT_POLL;
+	attrib->bwmode = CHANNEL_WIDTH_20;
+	/*attrib->qsel = QSLT_MGNT;*/ /* set in update_mgntframe_attrib() */
+	attrib->rate = MGN_6M;
+	if (bFinalPoll)
+		attrib->bf_pkt_type = 3;
+	else
+		attrib->bf_pkt_type = 2;
+
+	_rtw_memset(pmgntframe->buf_addr, 0, TXDESC_OFFSET + WLANHDR_OFFSET);
+	pframe = pmgntframe->buf_addr + TXDESC_OFFSET;
+	pwlanhdr = (struct rtw_ieee80211_hdr *)pframe;
+
+	/* Frame control */
+	pwlanhdr->frame_ctl = 0;
+	set_frame_sub_type(pframe, attrib->subtype);
+
+	/* Duration */
+	set_duration(pframe, 100);
+
+	/* RA */
+	_rtw_memcpy(pwlanhdr->addr1, ra, ETH_ALEN);
+
+	/* TA */
+	_rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(adapter), ETH_ALEN);
+
+	/* Feedback Segment Retransmission Bitmap */
+	pframe[16] = 0xFF;
+
+	attrib->pktlen = 17;
+	attrib->last_txcmdsz = attrib->pktlen;
+
+	dump_mgntframe(adapter, pmgntframe);
+
+	return _TRUE;
+}
+
+static void _sounding_update_min_period(PADAPTER adapter, u16 period, u8 leave)
+{
+	struct beamforming_info *info;
+	struct beamformee_entry *bfee;
+	u8 i = 0;
+	u16 min_val = 0xFFFF;
+
+
+	info = GET_BEAMFORM_INFO(adapter);
+
+	if (_TRUE == leave) {
+		/*
+		 * When a BFee left,
+		 * we need to find the latest min sounding period
+		 * from the remaining BFees
+		 */
+		for (i = 0; i < MAX_BEAMFORMEE_ENTRY_NUM; i++) {
+			bfee = &info->bfee_entry[i];
+			if ((bfee->used == _TRUE)
+			    && (bfee->sound_period < min_val))
+				min_val = bfee->sound_period;
+		}
+
+		if (min_val == 0xFFFF)
+			info->sounding_info.min_sounding_period = 0;
+		else
+			info->sounding_info.min_sounding_period = min_val;
+	} else {
+		if ((info->sounding_info.min_sounding_period == 0)
+		    || (period < info->sounding_info.min_sounding_period))
+			info->sounding_info.min_sounding_period = period;
+	}
+}
+
+static void _sounding_init(struct sounding_info *sounding)
+{
+	_rtw_memset(sounding->su_sounding_list, 0xFF, MAX_NUM_BEAMFORMEE_SU);
+	_rtw_memset(sounding->mu_sounding_list, 0xFF, MAX_NUM_BEAMFORMEE_MU);
+	sounding->state = SOUNDING_STATE_NONE;
+	sounding->su_bfee_curidx = 0xFF;
+	sounding->candidate_mu_bfee_cnt = 0;
+	sounding->min_sounding_period = 0;
+	sounding->sound_remain_cnt_per_period = 0;
+}
+
+static void _sounding_reset_vars(PADAPTER adapter)
+{
+	struct beamforming_info	*info;
+	struct sounding_info *sounding;
+	u8 idx;
+
+
+	info = GET_BEAMFORM_INFO(adapter);
+	sounding = &info->sounding_info;
+
+	_rtw_memset(sounding->su_sounding_list, 0xFF, MAX_NUM_BEAMFORMEE_SU);
+	_rtw_memset(sounding->mu_sounding_list, 0xFF, MAX_NUM_BEAMFORMEE_MU);
+	sounding->su_bfee_curidx = 0xFF;
+	sounding->candidate_mu_bfee_cnt = 0;
+
+	/* Clear bSound flag for the new period */
+	for (idx = 0; idx < MAX_BEAMFORMEE_ENTRY_NUM; idx++) {
+		if ((info->bfee_entry[idx].used == _TRUE)
+		    && (info->bfee_entry[idx].sounding == _TRUE)) {
+			info->bfee_entry[idx].sounding = _FALSE;
+			info->bfee_entry[idx].bCandidateSoundingPeer = _FALSE;
+		}
+	}
+}
+
+/*
+ * Return
+ *	0	Prepare sounding list OK
+ *	-1	Fail to prepare sounding list, because no beamformee need to souding
+ *	-2	Fail to prepare sounding list, because beamformee state not ready
+ *
+ */
+static int _sounding_get_list(PADAPTER adapter)
+{
+	struct beamforming_info	*info;
+	struct sounding_info *sounding;
+	struct beamformee_entry *bfee;
+	u8 i, mu_idx = 0, su_idx = 0, not_ready = 0;
+	int ret = 0;
+
+
+	info = GET_BEAMFORM_INFO(adapter);
+	sounding = &info->sounding_info;
+
+	/* Add MU BFee list first because MU priority is higher than SU */
+	for (i = 0; i < MAX_BEAMFORMEE_ENTRY_NUM; i++) {
+		bfee = &info->bfee_entry[i];
+		if (bfee->used == _FALSE)
+			continue;
+
+		if (bfee->state != BEAMFORM_ENTRY_HW_STATE_ADDED) {
+			RTW_ERR("%s: Invalid BFee idx(%d) Hw state=%d\n", __FUNCTION__, i, bfee->state);
+			not_ready++;
+			continue;
+		}
+
+		/*
+		 * Decrease BFee's SoundCnt per period
+		 * If the remain count is 0,
+		 * then it can be sounded at this time
+		 */
+		if (bfee->SoundCnt) {
+			bfee->SoundCnt--;
+			if (bfee->SoundCnt)
+				continue;
+		}
+
+		/*
+		 * <tynli_Note>
+		 *	If the STA supports MU BFee capability then we add it to MUSoundingList directly
+		 *	because we can only sound one STA by unicast NDPA with MU cap enabled to get correct channel info.
+		 *	Suggested by BB team Luke Lee. 2015.11.25.
+		 */
+		if (bfee->cap & BEAMFORMEE_CAP_VHT_MU) {
+			/* MU BFee */
+			if (mu_idx >= MAX_NUM_BEAMFORMEE_MU) {
+				RTW_ERR("%s: Too much MU bfee entry(Limit:%d)\n", __FUNCTION__, MAX_NUM_BEAMFORMEE_MU);
+				continue;
+			}
+
+			if (bfee->bApplySounding == _TRUE) {
+				bfee->bCandidateSoundingPeer = _TRUE;
+				bfee->SoundCnt = GetInitSoundCnt(bfee->sound_period, sounding->min_sounding_period);
+				sounding->mu_sounding_list[mu_idx] = i;
+				mu_idx++;
+			}
+		} else if (bfee->cap & (BEAMFORMEE_CAP_VHT_SU|BEAMFORMEE_CAP_HT_EXPLICIT)) {
+			/* SU BFee (HT/VHT) */
+			if (su_idx >= MAX_NUM_BEAMFORMEE_SU) {
+				RTW_ERR("%s: Too much SU bfee entry(Limit:%d)\n", __FUNCTION__, MAX_NUM_BEAMFORMEE_SU);
+				continue;
+			}
+
+			if (bfee->bDeleteSounding == _TRUE) {
+				sounding->su_sounding_list[su_idx] = i;
+				su_idx++;
+			} else if ((bfee->bApplySounding == _TRUE)
+			    && (bfee->bSuspendSUCap == _FALSE)) {
+				bfee->bCandidateSoundingPeer = _TRUE;
+				bfee->SoundCnt = GetInitSoundCnt(bfee->sound_period, sounding->min_sounding_period);
+				sounding->su_sounding_list[su_idx] = i;
+				su_idx++;
+			}
+		}
+	}
+
+	sounding->candidate_mu_bfee_cnt = mu_idx;
+
+	if (su_idx + mu_idx == 0) {
+		ret = -1;
+		if (not_ready)
+			ret = -2;
+	}
+
+	RTW_INFO("-%s: There are %d SU and %d MU BFees in this sounding period\n", __FUNCTION__, su_idx, mu_idx);
+
+	return ret;
+}
+
+static void _sounding_handler(PADAPTER adapter)
+{
+	struct beamforming_info	*info;
+	struct sounding_info *sounding;
+	struct beamformee_entry *bfee;
+	u8 su_idx, i;
+	u32 timeout_period = 0;
+	u8 set_timer = _FALSE;
+	int ret = 0;
+	static u16 wait_cnt = 0;
+
+
+	info = GET_BEAMFORM_INFO(adapter);
+	sounding = &info->sounding_info;
+
+	RTW_DBG("+%s: state=%d\n", __FUNCTION__, sounding->state);
+	if ((sounding->state != SOUNDING_STATE_INIT)
+	    && (sounding->state != SOUNDING_STATE_SU_SOUNDDOWN)
+	    && (sounding->state != SOUNDING_STATE_MU_SOUNDDOWN)
+	    && (sounding->state != SOUNDING_STATE_SOUNDING_TIMEOUT)) {
+		RTW_WARN("%s: Invalid State(%d) and return!\n", __FUNCTION__, sounding->state);
+		return;
+	}
+
+	if (sounding->state == SOUNDING_STATE_INIT) {
+		RTW_INFO("%s: Sounding start\n", __FUNCTION__);
+
+		/* Init Var */
+		_sounding_reset_vars(adapter);
+
+		/* Get the sounding list of this sounding period */
+		ret = _sounding_get_list(adapter);
+		if (ret == -1) {
+			wait_cnt = 0;
+			sounding->state = SOUNDING_STATE_NONE;
+			RTW_ERR("%s: No BFees found, set to SOUNDING_STATE_NONE\n", __FUNCTION__);
+			info->sounding_running--;
+			return;
+		}
+		if (ret == -2) {
+			RTW_WARN("%s: Temporarily cann't find BFee to sounding\n", __FUNCTION__);
+			if (wait_cnt < 5) {
+				wait_cnt++;
+			} else {
+				wait_cnt = 0;
+				sounding->state = SOUNDING_STATE_NONE;
+				RTW_ERR("%s: Wait changing state timeout!! Set to SOUNDING_STATE_NONE\n", __FUNCTION__);
+			}
+			info->sounding_running--;
+			return;
+		}
+		if (ret != 0) {
+			wait_cnt = 0;
+			RTW_ERR("%s: Unkown state(%d)!\n", __FUNCTION__, ret);
+			info->sounding_running--;
+			return;
+
+		}
+
+		wait_cnt = 0;
+
+		if (check_fwstate(&adapter->mlmepriv, WIFI_SITE_MONITOR) == _TRUE) {
+			RTW_INFO("%s: Sounding abort! scanning APs...\n", __FUNCTION__);
+			info->sounding_running--;
+			return;
+		}
+
+		rtw_ps_deny(adapter, PS_DENY_BEAMFORMING);
+		LeaveAllPowerSaveModeDirect(adapter);
+	}
+
+	/* Get non-sound SU BFee index */
+	for (i = 0; i < MAX_NUM_BEAMFORMEE_SU; i++) {
+		su_idx = sounding->su_sounding_list[i];
+		if (su_idx >= MAX_BEAMFORMEE_ENTRY_NUM)
+			continue;
+		bfee = &info->bfee_entry[su_idx];
+		if (_FALSE == bfee->sounding)
+			break;
+	}
+	if (i < MAX_NUM_BEAMFORMEE_SU) {
+		sounding->su_bfee_curidx = su_idx;
+		/* Set to sounding start state */
+		sounding->state = SOUNDING_STATE_SU_START;
+		RTW_DBG("%s: Set to SOUNDING_STATE_SU_START\n", __FUNCTION__);
+
+		bfee->sounding = _TRUE;
+		/* Reset sounding timeout flag for the new sounding */
+		bfee->bSoundingTimeout = _FALSE;
+
+		if (_TRUE == bfee->bDeleteSounding) {
+			u8 res = _FALSE;
+			rtw_bf_cmd(adapter, BEAMFORMING_CTRL_END_PERIOD, &res, 1, 0);
+			return;
+		}
+
+		/* Start SU sounding */
+		if (bfee->cap & BEAMFORMEE_CAP_VHT_SU)
+			_send_vht_ndpa_packet(adapter, bfee->mac_addr, bfee->aid, bfee->sound_bw);
+		else if (bfee->cap & BEAMFORMEE_CAP_HT_EXPLICIT)
+			_send_ht_ndpa_packet(adapter, bfee->mac_addr, bfee->sound_bw);
+
+		/* Set sounding timeout timer */
+		_set_timer(&info->sounding_timeout_timer, SU_SOUNDING_TIMEOUT);
+		return;
+	}
+
+	if (sounding->candidate_mu_bfee_cnt > 0) {
+		/*
+		 * If there is no SU BFee then find MU BFee and perform MU sounding
+		 *
+		 * <tynli_note> Need to check the MU starting condition. 2015.12.15.
+		 */
+		sounding->state = SOUNDING_STATE_MU_START;
+		RTW_DBG("%s: Set to SOUNDING_STATE_MU_START\n", __FUNCTION__);
+
+		/* Update MU BFee info */
+		for (i = 0; i < sounding->candidate_mu_bfee_cnt; i++) {
+			bfee = &info->bfee_entry[sounding->mu_sounding_list[i]];
+			bfee->sounding = _TRUE;
+		}
+
+		/* Send MU NDPA */
+		bfee = &info->bfee_entry[sounding->mu_sounding_list[0]];
+		_send_vht_mu_ndpa_packet(adapter, bfee->sound_bw);
+
+		/* Send BF report poll if more than 1 MU STA */
+		for (i = 1; i < sounding->candidate_mu_bfee_cnt; i++) {
+			bfee = &info->bfee_entry[sounding->mu_sounding_list[i]];
+
+			if (i == (sounding->candidate_mu_bfee_cnt - 1))/* The last STA*/
+				_send_bf_report_poll(adapter, bfee->mac_addr, _TRUE);
+			else
+				_send_bf_report_poll(adapter, bfee->mac_addr, _FALSE);
+		}
+
+		sounding->candidate_mu_bfee_cnt = 0;
+
+		/* Set sounding timeout timer */
+		_set_timer(&info->sounding_timeout_timer, MU_SOUNDING_TIMEOUT);
+		return;
+	}
+
+	info->sounding_running--;
+	sounding->state = SOUNDING_STATE_INIT;
+	RTW_INFO("%s: Sounding finished!\n", __FUNCTION__);
+	rtw_ps_deny_cancel(adapter, PS_DENY_BEAMFORMING);
+}
+
+static void _sounding_force_stop(PADAPTER adapter)
+{
+	struct beamforming_info	*info;
+	struct sounding_info *sounding;
+
+	info = GET_BEAMFORM_INFO(adapter);
+	sounding = &info->sounding_info;
+
+	if ((sounding->state == SOUNDING_STATE_SU_START)
+	    || (sounding->state == SOUNDING_STATE_MU_START)) {
+		u8 res = _FALSE;
+		_cancel_timer_ex(&info->sounding_timeout_timer);
+		rtw_bf_cmd(adapter, BEAMFORMING_CTRL_END_PERIOD, &res, 1, 1);
+		return;
+	}
+
+	info->sounding_running--;
+	sounding->state = SOUNDING_STATE_INIT;
+	RTW_INFO("%s: Sounding finished!\n", __FUNCTION__);
+	rtw_ps_deny_cancel(adapter, PS_DENY_BEAMFORMING);
+}
+
+static void _sounding_timer_handler(void *FunctionContext)
+{
+	PADAPTER adapter;
+	struct beamforming_info	*info;
+	struct sounding_info *sounding;
+	static u8 delay = 0;
+
+
+	RTW_DBG("+%s\n", __FUNCTION__);
+
+	adapter = (PADAPTER)FunctionContext;
+	info = GET_BEAMFORM_INFO(adapter);
+	sounding = &info->sounding_info;
+
+	if (SOUNDING_STATE_NONE == sounding->state) {
+		RTW_INFO("%s: Stop!\n", __FUNCTION__);
+		if (info->sounding_running)
+			RTW_WARN("%s: souding_running=%d when thread stop!\n",
+				 __FUNCTION__, info->sounding_running);
+		return;
+	}
+
+	_set_timer(&info->sounding_timer, sounding->min_sounding_period);
+
+	if (!info->sounding_running) {
+		if (SOUNDING_STATE_INIT != sounding->state) {
+			RTW_WARN("%s: state(%d) != SOUNDING_STATE_INIT!!\n", __FUNCTION__, sounding->state);
+			sounding->state = SOUNDING_STATE_INIT;
+		}
+		delay = 0;
+		info->sounding_running++;
+		rtw_bf_cmd(adapter, BEAMFORMING_CTRL_START_PERIOD, NULL, 0, 1);
+	} else {
+		if (delay != 0xFF)
+			delay++;
+		RTW_WARN("%s: souding is still processing...(state:%d, running:%d, delay:%d)\n",
+			 __FUNCTION__, sounding->state, info->sounding_running, delay);
+		if (delay > 3) {
+			RTW_WARN("%s: Stop sounding!!\n", __FUNCTION__);
+			_sounding_force_stop(adapter);
+		}
+	}
+}
+
+static void _sounding_timeout_timer_handler(void *FunctionContext)
+{
+	PADAPTER adapter;
+	struct beamforming_info	*info;
+	struct sounding_info *sounding;
+	struct beamformee_entry *bfee;
+
+
+	RTW_WARN("+%s\n", __FUNCTION__);
+
+	adapter = (PADAPTER)FunctionContext;
+	info = GET_BEAMFORM_INFO(adapter);
+	sounding = &info->sounding_info;
+
+	if (SOUNDING_STATE_SU_START == sounding->state) {
+		sounding->state = SOUNDING_STATE_SOUNDING_TIMEOUT;
+		RTW_ERR("%s: Set to SU SOUNDING_STATE_SOUNDING_TIMEOUT\n", __FUNCTION__);
+		/* SU BFee */
+		bfee = &info->bfee_entry[sounding->su_bfee_curidx];
+		bfee->bSoundingTimeout = _TRUE;
+		RTW_WARN("%s: The BFee entry[%d] is Sounding Timeout!\n", __FUNCTION__, sounding->su_bfee_curidx);
+	} else if (SOUNDING_STATE_MU_START == sounding->state) {
+		sounding->state = SOUNDING_STATE_SOUNDING_TIMEOUT;
+		RTW_ERR("%s: Set to MU SOUNDING_STATE_SOUNDING_TIMEOUT\n", __FUNCTION__);
+	} else {
+		RTW_WARN("%s: unexpected sounding state:0x%02x\n", __FUNCTION__, sounding->state);
+		return;
+	}
+
+	rtw_bf_cmd(adapter, BEAMFORMING_CTRL_START_PERIOD, NULL, 0, 1);
+}
+
+static struct beamformer_entry *_bfer_get_free_entry(PADAPTER adapter)
+{
+	u8 i = 0;
+	struct beamforming_info *info;
+	struct beamformer_entry *bfer;
+
+
+	info = GET_BEAMFORM_INFO(adapter);
+
+	for (i = 0; i < MAX_BEAMFORMER_ENTRY_NUM; i++) {
+		bfer = &info->bfer_entry[i];
+		if (bfer->used == _FALSE)
+			return bfer;
+	}
+
+	return NULL;
+}
+
+static struct beamformer_entry *_bfer_get_entry_by_addr(PADAPTER adapter, u8 *ra)
+{
+	u8 i = 0;
+	struct beamforming_info *info;
+	struct beamformer_entry *bfer;
+
+
+	info = GET_BEAMFORM_INFO(adapter);
+
+	for (i = 0; i < MAX_BEAMFORMER_ENTRY_NUM; i++) {
+		bfer = &info->bfer_entry[i];
+		if (bfer->used == _FALSE)
+			continue;
+		if (_rtw_memcmp(ra, bfer->mac_addr, ETH_ALEN) == _TRUE)
+			return bfer;
+	}
+
+	return NULL;
+}
+
+static struct beamformer_entry *_bfer_add_entry(PADAPTER adapter,
+	struct sta_info *sta, u8 bf_cap, u8 sounding_dim, u8 comp_steering)
+{
+	struct mlme_priv *mlme;
+	struct beamforming_info *info;
+	struct beamformer_entry *bfer;
+	u8 *bssid;
+	u16 val16;
+	u8 i;
+
+
+	mlme = &adapter->mlmepriv;
+	info = GET_BEAMFORM_INFO(adapter);
+
+	bfer = _bfer_get_entry_by_addr(adapter, sta->cmn.mac_addr);
+	if (!bfer) {
+		bfer = _bfer_get_free_entry(adapter);
+		if (!bfer)
+			return NULL;
+	}
+
+	bfer->used = _TRUE;
+	_get_txvector_parameter(adapter, sta, &bfer->g_id, &bfer->p_aid);
+	_rtw_memcpy(bfer->mac_addr, sta->cmn.mac_addr, ETH_ALEN);
+	bfer->cap = bf_cap;
+	bfer->state = BEAMFORM_ENTRY_HW_STATE_ADD_INIT;
+	bfer->NumofSoundingDim = sounding_dim;
+
+	if (TEST_FLAG(bf_cap, BEAMFORMER_CAP_VHT_MU)) {
+		info->beamformer_mu_cnt += 1;
+		bfer->aid = sta->cmn.aid;
+	} else if (TEST_FLAG(bf_cap, BEAMFORMER_CAP_VHT_SU|BEAMFORMER_CAP_HT_EXPLICIT)) {
+		info->beamformer_su_cnt += 1;
+
+		/* Record HW idx info */
+		for (i = 0; i < MAX_NUM_BEAMFORMER_SU; i++) {
+			if ((info->beamformer_su_reg_maping & BIT(i)) == 0) {
+				info->beamformer_su_reg_maping |= BIT(i);
+				bfer->su_reg_index = i;
+				break;
+			}
+		}
+		RTW_INFO("%s: Add BFer entry beamformer_su_reg_maping=%#x, su_reg_index=%d\n",
+			 __FUNCTION__, info->beamformer_su_reg_maping, bfer->su_reg_index);
+	}
+
+	return bfer;
+}
+
+static void _bfer_remove_entry(PADAPTER adapter, struct beamformer_entry *entry)
+{
+	struct beamforming_info *info;
+
+
+	info = GET_BEAMFORM_INFO(adapter);
+
+	entry->state = BEAMFORM_ENTRY_HW_STATE_DELETE_INIT;
+
+	if (TEST_FLAG(entry->cap, BEAMFORMER_CAP_VHT_MU)) {
+		info->beamformer_mu_cnt -= 1;
+		_rtw_memset(entry->gid_valid, 0, 8);
+		_rtw_memset(entry->user_position, 0, 16);
+	} else if (TEST_FLAG(entry->cap, BEAMFORMER_CAP_VHT_SU|BEAMFORMER_CAP_HT_EXPLICIT)) {
+		info->beamformer_su_cnt -= 1;
+	}
+
+	if (info->beamformer_mu_cnt == 0)
+		info->beamforming_cap &= ~BEAMFORMEE_CAP_VHT_MU;
+	if (info->beamformer_su_cnt == 0)
+		info->beamforming_cap &= ~(BEAMFORMEE_CAP_VHT_SU|BEAMFORMEE_CAP_HT_EXPLICIT);
+}
+
+static u8 _bfer_set_entry_gid(PADAPTER adapter, u8 *addr, u8 *gid, u8 *position)
+{
+	struct beamformer_entry bfer;
+
+	memset(&bfer, 0, sizeof(bfer));
+	memcpy(bfer.mac_addr, addr, ETH_ALEN);
+
+	/* Parsing Membership Status Array */
+	memcpy(bfer.gid_valid, gid, 8);
+
+	/* Parsing User Position Array */
+	memcpy(bfer.user_position, position, 16);
+
+	/* Config HW GID table */
+	rtw_bf_cmd(adapter, BEAMFORMING_CTRL_SET_GID_TABLE, (u8 *) &bfer,
+			sizeof(bfer), 1);
+
+	return _SUCCESS;
+}
+
+static struct beamformee_entry *_bfee_get_free_entry(PADAPTER adapter)
+{
+	u8 i = 0;
+	struct beamforming_info *info;
+	struct beamformee_entry *bfee;
+
+
+	info = GET_BEAMFORM_INFO(adapter);
+
+	for (i = 0; i < MAX_BEAMFORMEE_ENTRY_NUM; i++) {
+		bfee = &info->bfee_entry[i];
+		if (bfee->used == _FALSE)
+			return bfee;
+	}
+
+	return NULL;
+}
+
+static struct beamformee_entry *_bfee_get_entry_by_addr(PADAPTER adapter, u8 *ra)
+{
+	u8 i = 0;
+	struct beamforming_info *info;
+	struct beamformee_entry *bfee;
+
+
+	info = GET_BEAMFORM_INFO(adapter);
+
+	for (i = 0; i < MAX_BEAMFORMEE_ENTRY_NUM; i++) {
+		bfee = &info->bfee_entry[i];
+		if (bfee->used == _FALSE)
+			continue;
+		if (_rtw_memcmp(ra, bfee->mac_addr, ETH_ALEN) == _TRUE)
+			return bfee;
+	}
+
+	return NULL;
+}
+
+static u8 _bfee_get_first_su_entry_idx(PADAPTER adapter, struct beamformee_entry *ignore)
+{
+	struct beamforming_info *info;
+	struct beamformee_entry *bfee;
+	u8 i;
+
+
+	info = GET_BEAMFORM_INFO(adapter);
+
+	for (i = 0; i < MAX_BEAMFORMEE_ENTRY_NUM; i++) {
+		bfee = &info->bfee_entry[i];
+		if (ignore && (bfee == ignore))
+			continue;
+		if (bfee->used == _FALSE)
+			continue;
+		if ((!TEST_FLAG(bfee->cap, BEAMFORMEE_CAP_VHT_MU))
+		    && TEST_FLAG(bfee->cap, BEAMFORMEE_CAP_VHT_SU|BEAMFORMEE_CAP_HT_EXPLICIT))
+			return i;
+	}
+
+	return 0xFF;
+}
+
+/*
+ * Description:
+ *	Get the first entry index of MU Beamformee.
+ *
+ * Return Value:
+ *	Index of the first MU sta, or 0xFF for invalid index.
+ *
+ * 2015.05.25. Created by tynli.
+ *
+ */
+static u8 _bfee_get_first_mu_entry_idx(PADAPTER adapter, struct beamformee_entry *ignore)
+{
+	struct beamforming_info *info;
+	struct beamformee_entry *bfee;
+	u8 i;
+
+
+	info = GET_BEAMFORM_INFO(adapter);
+
+	for (i = 0; i < MAX_BEAMFORMEE_ENTRY_NUM; i++) {
+		bfee = &info->bfee_entry[i];
+		if (ignore && (bfee == ignore))
+			continue;
+		if (bfee->used == _FALSE)
+			continue;
+		if (TEST_FLAG(bfee->cap, BEAMFORMEE_CAP_VHT_MU))
+			return i;
+	}
+
+	return 0xFF;
+}
+
+static struct beamformee_entry *_bfee_add_entry(PADAPTER adapter,
+	struct sta_info *sta, u8 bf_cap, u8 sounding_dim, u8 comp_steering)
+{
+	struct mlme_priv *mlme;
+	struct beamforming_info *info;
+	struct beamformee_entry *bfee;
+	u8 *bssid;
+	u16 val16;
+	u8 i;
+
+
+	mlme = &adapter->mlmepriv;
+	info = GET_BEAMFORM_INFO(adapter);
+
+	bfee = _bfee_get_entry_by_addr(adapter, sta->cmn.mac_addr);
+	if (!bfee) {
+		bfee = _bfee_get_free_entry(adapter);
+		if (!bfee)
+			return NULL;
+	}
+
+	bfee->used = _TRUE;
+	bfee->aid = sta->cmn.aid;
+	bfee->mac_id = sta->cmn.mac_id;
+	bfee->sound_bw = sta->cmn.bw_mode;
+
+	_get_txvector_parameter(adapter, sta, &bfee->g_id, &bfee->p_aid);
+	sta->cmn.bf_info.g_id = bfee->g_id;
+	sta->cmn.bf_info.p_aid = bfee->p_aid;
+
+	_rtw_memcpy(bfee->mac_addr, sta->cmn.mac_addr, ETH_ALEN);
+	bfee->txbf = _FALSE;
+	bfee->sounding = _FALSE;
+	bfee->sound_period = 40;
+	_sounding_update_min_period(adapter, bfee->sound_period, _FALSE);
+	bfee->SoundCnt = GetInitSoundCnt(bfee->sound_period, info->sounding_info.min_sounding_period);
+	bfee->cap = bf_cap;
+	bfee->state = BEAMFORM_ENTRY_HW_STATE_ADD_INIT;
+
+	bfee->bCandidateSoundingPeer = _FALSE;
+	bfee->bSoundingTimeout = _FALSE;
+	bfee->bDeleteSounding = _FALSE;
+	bfee->bApplySounding = _TRUE;
+
+	bfee->tx_timestamp = 0;
+	bfee->tx_bytes = 0;
+
+	bfee->LogStatusFailCnt = 0;
+	bfee->NumofSoundingDim = sounding_dim;
+	bfee->comp_steering_num_of_bfer = comp_steering;
+	bfee->bSuspendSUCap = _FALSE;
+
+	if (TEST_FLAG(bf_cap, BEAMFORMEE_CAP_VHT_MU)) {
+		info->beamformee_mu_cnt += 1;
+		info->first_mu_bfee_index = _bfee_get_first_mu_entry_idx(adapter, NULL);
+
+		if (_TRUE == info->bEnableSUTxBFWorkAround) {
+			/* When the first MU BFee added, discard SU BFee bfee's capability */
+			if ((info->beamformee_mu_cnt == 1) && (info->beamformee_su_cnt > 0)) {
+				if (info->TargetSUBFee) {
+					info->TargetSUBFee->bSuspendSUCap = _TRUE;
+					info->TargetSUBFee->bDeleteSounding = _TRUE;
+				} else {
+					RTW_ERR("%s: UNEXPECTED!! info->TargetSUBFee is NULL!", __FUNCTION__);
+				}
+				info->TargetSUBFee = NULL;
+				_rtw_memset(&info->TargetCSIInfo, 0, sizeof(struct _RT_CSI_INFO));
+				rtw_bf_cmd(adapter, BEAMFORMING_CTRL_SET_CSI_REPORT, (u8*)&info->TargetCSIInfo, sizeof(struct _RT_CSI_INFO), 0);
+			}
+		}
+
+		/* Record HW idx info */
+		for (i = 0; i < MAX_NUM_BEAMFORMEE_MU; i++) {
+			if ((info->beamformee_mu_reg_maping & BIT(i)) == 0) {
+				info->beamformee_mu_reg_maping |= BIT(i);
+				bfee->mu_reg_index = i;
+				break;
+			}
+		}
+		RTW_INFO("%s: Add BFee entry beamformee_mu_reg_maping=%#x, mu_reg_index=%d\n",
+			 __FUNCTION__, info->beamformee_mu_reg_maping, bfee->mu_reg_index);
+
+	} else if (TEST_FLAG(bf_cap, BEAMFORMEE_CAP_VHT_SU|BEAMFORMEE_CAP_HT_EXPLICIT)) {
+		info->beamformee_su_cnt += 1;
+
+		if (_TRUE == info->bEnableSUTxBFWorkAround) {
+			/* Record the first SU BFee index. We only allow the first SU BFee to be sound */
+			if ((info->beamformee_su_cnt == 1) && (info->beamformee_mu_cnt == 0)) {
+				info->TargetSUBFee = bfee;
+				_rtw_memset(&info->TargetCSIInfo, 0, sizeof(struct _RT_CSI_INFO));
+				bfee->bSuspendSUCap = _FALSE;
+			} else {
+				bfee->bSuspendSUCap = _TRUE;
+			}
+		}
+
+		/* Record HW idx info */
+		for (i = 0; i < MAX_NUM_BEAMFORMEE_SU; i++) {
+			if ((info->beamformee_su_reg_maping & BIT(i)) == 0) {
+				info->beamformee_su_reg_maping |= BIT(i);
+				bfee->su_reg_index = i;
+				break;
+			}
+		}
+		RTW_INFO("%s: Add BFee entry beamformee_su_reg_maping=%#x, su_reg_index=%d\n",
+			 __FUNCTION__, info->beamformee_su_reg_maping, bfee->su_reg_index);
+	}
+
+	return bfee;
+}
+
+static void _bfee_remove_entry(PADAPTER adapter, struct beamformee_entry *entry)
+{
+	struct beamforming_info *info;
+	u8 idx;
+
+
+	info = GET_BEAMFORM_INFO(adapter);
+
+	entry->state = BEAMFORM_ENTRY_HW_STATE_DELETE_INIT;
+
+	if (TEST_FLAG(entry->cap, BEAMFORMEE_CAP_VHT_MU)) {
+		info->beamformee_mu_cnt -= 1;
+		info->first_mu_bfee_index = _bfee_get_first_mu_entry_idx(adapter, entry);
+
+		if (_TRUE == info->bEnableSUTxBFWorkAround) {
+			if ((info->beamformee_mu_cnt == 0) && (info->beamformee_su_cnt > 0)) {
+				idx = _bfee_get_first_su_entry_idx(adapter, NULL);
+				info->TargetSUBFee = &info->bfee_entry[idx];
+				_rtw_memset(&info->TargetCSIInfo, 0, sizeof(struct _RT_CSI_INFO));
+				info->TargetSUBFee->bSuspendSUCap = _FALSE;
+			}
+		}
+	} else if (TEST_FLAG(entry->cap, BEAMFORMEE_CAP_VHT_SU|BEAMFORMEE_CAP_HT_EXPLICIT)) {
+		info->beamformee_su_cnt -= 1;
+
+		/* When the target SU BFee leaves, disable workaround */
+		if ((_TRUE == info->bEnableSUTxBFWorkAround)
+		    && (entry == info->TargetSUBFee)) {
+			entry->bSuspendSUCap = _TRUE;
+			info->TargetSUBFee = NULL;
+			_rtw_memset(&info->TargetCSIInfo, 0, sizeof(struct _RT_CSI_INFO));
+			rtw_bf_cmd(adapter, BEAMFORMING_CTRL_SET_CSI_REPORT, (u8*)&info->TargetCSIInfo, sizeof(struct _RT_CSI_INFO), 0);
+		}
+	}
+
+	if (info->beamformee_mu_cnt == 0)
+		info->beamforming_cap &= ~BEAMFORMER_CAP_VHT_MU;
+	if (info->beamformee_su_cnt == 0)
+		info->beamforming_cap &= ~(BEAMFORMER_CAP_VHT_SU|BEAMFORMER_CAP_HT_EXPLICIT);
+
+	_sounding_update_min_period(adapter, 0, _TRUE);
+}
+
+static enum beamforming_cap _bfee_get_entry_cap_by_macid(PADAPTER adapter, u8 macid)
+{
+	struct beamforming_info *info;
+	struct beamformee_entry *bfee;
+	u8 i;
+
+
+	info = GET_BEAMFORM_INFO(adapter);
+
+	for (i = 0; i < MAX_BEAMFORMER_ENTRY_NUM; i++) {
+		bfee = &info->bfee_entry[i];
+		if (bfee->used == _FALSE)
+			continue;
+		if (bfee->mac_id == macid)
+			return bfee->cap;
+	}
+
+	return BEAMFORMING_CAP_NONE;
+}
+
+static void _beamforming_enter(PADAPTER adapter, void *p)
+{
+	struct mlme_priv *mlme;
+	struct ht_priv *htpriv;
+#ifdef CONFIG_80211AC_VHT
+	struct vht_priv *vhtpriv;
+#endif
+	struct mlme_ext_priv *mlme_ext;
+	struct sta_info *sta, *sta_copy;
+	struct beamforming_info *info;
+	struct beamformer_entry *bfer = NULL;
+	struct beamformee_entry *bfee = NULL;
+	u8 wireless_mode;
+	u8 sta_bf_cap;
+	u8 sounding_dim = 0; /* number of sounding dimensions */
+	u8 comp_steering_num = 0; /* compressed steering number */
+
+
+	mlme = &adapter->mlmepriv;
+	htpriv = &mlme->htpriv;
+#ifdef CONFIG_80211AC_VHT
+	vhtpriv = &mlme->vhtpriv;
+#endif
+	mlme_ext = &adapter->mlmeextpriv;
+	info = GET_BEAMFORM_INFO(adapter);
+
+	sta_copy = (struct sta_info *)p;
+	sta = rtw_get_stainfo(&adapter->stapriv, sta_copy->cmn.mac_addr);
+	if (!sta) {
+		RTW_ERR("%s: Cann't find STA info for " MAC_FMT "\n",
+			__FUNCTION__, MAC_ARG(sta_copy->cmn.mac_addr));
+		return;
+	}
+	if (sta != sta_copy) {
+		RTW_WARN("%s: Origin sta(fake)=%p realsta=%p for " MAC_FMT "\n",
+		__FUNCTION__, sta_copy, sta, MAC_ARG(sta_copy->cmn.mac_addr));
+	}
+
+	/* The current setting does not support Beaforming */
+	wireless_mode = sta->wireless_mode;
+	if ((is_supported_ht(wireless_mode) == _FALSE)
+	    && (is_supported_vht(wireless_mode) == _FALSE)) {
+		RTW_WARN("%s: Not support HT or VHT mode\n", __FUNCTION__);
+		return;
+	}
+
+	if ((0 == htpriv->beamform_cap)
+#ifdef CONFIG_80211AC_VHT
+	    && (0 == vhtpriv->beamform_cap)
+#endif
+	   ) {
+		RTW_INFO("The configuration disabled Beamforming! Skip...\n");
+		return;
+	}
+
+	_get_sta_beamform_cap(adapter, sta,
+			      &sta_bf_cap, &sounding_dim, &comp_steering_num);
+	RTW_INFO("STA Beamforming Capability=0x%02X\n", sta_bf_cap);
+	if (sta_bf_cap == BEAMFORMING_CAP_NONE)
+		return;
+	if ((sta_bf_cap & BEAMFORMEE_CAP_HT_EXPLICIT)
+	    || (sta_bf_cap & BEAMFORMEE_CAP_VHT_SU)
+	    || (sta_bf_cap & BEAMFORMEE_CAP_VHT_MU))
+		sta_bf_cap |= BEAMFORMEE_CAP;
+	if ((sta_bf_cap & BEAMFORMER_CAP_HT_EXPLICIT)
+	    || (sta_bf_cap & BEAMFORMER_CAP_VHT_SU)
+	    || (sta_bf_cap & BEAMFORMER_CAP_VHT_MU))
+		sta_bf_cap |= BEAMFORMER_CAP;
+
+	if (sta_bf_cap & BEAMFORMER_CAP) {
+		/* The other side is beamformer */
+		bfer = _bfer_add_entry(adapter, sta, sta_bf_cap, sounding_dim, comp_steering_num);
+		if (!bfer)
+			RTW_ERR("%s: Fail to allocate bfer entry!\n", __FUNCTION__);
+	}
+	if (sta_bf_cap & BEAMFORMEE_CAP) {
+		/* The other side is beamformee */
+		bfee = _bfee_add_entry(adapter, sta, sta_bf_cap, sounding_dim, comp_steering_num);
+		if (!bfee)
+			RTW_ERR("%s: Fail to allocate bfee entry!\n", __FUNCTION__);
+	}
+	if (!bfer && !bfee)
+		return;
+
+	rtw_hal_set_hwreg(adapter, HW_VAR_SOUNDING_ENTER, (u8*)sta);
+
+	/* Perform sounding if there is BFee */
+	if ((info->beamformee_su_cnt != 0)
+	    || (info->beamformee_mu_cnt != 0)) {
+		if (SOUNDING_STATE_NONE == info->sounding_info.state) {
+			info->sounding_info.state = SOUNDING_STATE_INIT;
+			/* Start sounding after 2 sec */
+			_set_timer(&info->sounding_timer, 2000);
+		}
+	}
+}
+
+static void _beamforming_reset(PADAPTER adapter)
+{
+	RTW_ERR("%s: Not ready!!\n", __FUNCTION__);
+}
+
+static void _beamforming_leave(PADAPTER adapter, u8 *ra)
+{
+	struct beamforming_info *info;
+	struct beamformer_entry *bfer = NULL;
+	struct beamformee_entry *bfee = NULL;
+	u8 bHwStateAddInit = _FALSE;
+
+
+	RTW_INFO("+%s\n", __FUNCTION__);
+
+	info = GET_BEAMFORM_INFO(adapter);
+	bfer = _bfer_get_entry_by_addr(adapter, ra);
+	bfee = _bfee_get_entry_by_addr(adapter, ra);
+
+	if (!bfer && !bfee) {
+		RTW_WARN("%s: " MAC_FMT " is neither beamforming ee or er!!\n",
+			__FUNCTION__, MAC_ARG(ra));
+		return;
+	}
+
+	if (bfer)
+		_bfer_remove_entry(adapter, bfer);
+
+	if (bfee)
+		_bfee_remove_entry(adapter, bfee);
+
+	rtw_hal_set_hwreg(adapter, HW_VAR_SOUNDING_LEAVE, ra);
+
+	/* Stop sounding if there is no any BFee */
+	if ((info->beamformee_su_cnt == 0)
+	    && (info->beamformee_mu_cnt == 0)) {
+		_cancel_timer_ex(&info->sounding_timer);
+		_sounding_init(&info->sounding_info);
+	}
+
+	RTW_INFO("-%s\n", __FUNCTION__);
+}
+
+static void _beamforming_sounding_down(PADAPTER adapter, u8 status)
+{
+	struct beamforming_info	*info;
+	struct sounding_info *sounding;
+	struct beamformee_entry *bfee;
+
+
+	info = GET_BEAMFORM_INFO(adapter);
+	sounding = &info->sounding_info;
+
+	RTW_INFO("+%s: sounding=%d, status=0x%02x\n", __FUNCTION__, sounding->state, status);
+
+	if (sounding->state == SOUNDING_STATE_MU_START) {
+		RTW_INFO("%s: MU sounding done\n", __FUNCTION__);
+		sounding->state = SOUNDING_STATE_MU_SOUNDDOWN;
+		RTW_INFO("%s: Set to SOUNDING_STATE_MU_SOUNDDOWN\n", __FUNCTION__);
+		info->SetHalSoundownOnDemandCnt++;
+		rtw_hal_set_hwreg(adapter, HW_VAR_SOUNDING_STATUS, &status);
+	} else if (sounding->state == SOUNDING_STATE_SU_START) {
+		RTW_INFO("%s: SU entry[%d] sounding down\n", __FUNCTION__, sounding->su_bfee_curidx);
+		bfee = &info->bfee_entry[sounding->su_bfee_curidx];
+		sounding->state = SOUNDING_STATE_SU_SOUNDDOWN;
+		RTW_INFO("%s: Set to SOUNDING_STATE_SU_SOUNDDOWN\n", __FUNCTION__);
+
+		/*
+		 * <tynli_note>
+		 *	bfee->bSoundingTimeout this flag still cannot avoid
+		 *	old sound down event happens in the new sounding period.
+		 *	2015.12.10
+		 */
+		if (_TRUE == bfee->bSoundingTimeout) {
+			RTW_WARN("%s: The entry[%d] is bSoundingTimeout!\n", __FUNCTION__, sounding->su_bfee_curidx);
+			bfee->bSoundingTimeout = _FALSE;
+			return;
+		}
+
+		if (_TRUE == status) {
+			/* success */
+			bfee->LogStatusFailCnt = 0;
+			info->SetHalSoundownOnDemandCnt++;
+			rtw_hal_set_hwreg(adapter, HW_VAR_SOUNDING_STATUS, &status);
+		} else if (_TRUE == bfee->bDeleteSounding) {
+			RTW_WARN("%s: Delete entry[%d] sounding info!\n", __FUNCTION__, sounding->su_bfee_curidx);
+			rtw_hal_set_hwreg(adapter, HW_VAR_SOUNDING_STATUS, &status);
+			bfee->bDeleteSounding = _FALSE;
+		} else {
+			bfee->LogStatusFailCnt++;
+			RTW_WARN("%s: LogStatusFailCnt=%d\n", __FUNCTION__, bfee->LogStatusFailCnt);
+			if (bfee->LogStatusFailCnt > 30) {
+				RTW_ERR("%s: LogStatusFailCnt > 30, Stop SOUNDING!!\n", __FUNCTION__);
+				rtw_bf_cmd(adapter, BEAMFORMING_CTRL_LEAVE, bfee->mac_addr, ETH_ALEN, 1);
+			}
+		}
+	} else {
+		RTW_WARN("%s: unexpected sounding state:0x%02x\n", __FUNCTION__, sounding->state);
+		return;
+	}
+
+	rtw_bf_cmd(adapter, BEAMFORMING_CTRL_START_PERIOD, NULL, 0, 0);
+}
+
+static void _c2h_snd_txbf(PADAPTER adapter, u8 *buf, u8 buf_len)
+{
+	struct beamforming_info	*info;
+	u8 res;
+
+	info = GET_BEAMFORM_INFO(adapter);
+
+	_cancel_timer_ex(&info->sounding_timeout_timer);
+
+	res = C2H_SND_TXBF_GET_SND_RESULT(buf) ? _TRUE : _FALSE;
+	RTW_INFO("+%s: %s\n", __FUNCTION__, res==_TRUE?"Success":"Fail!");
+
+	rtw_bf_cmd(adapter, BEAMFORMING_CTRL_END_PERIOD, &res, 1, 1);
+}
+
+/*
+ * Description:
+ *	This function is for phydm only
+ */
+enum beamforming_cap rtw_bf_bfee_get_entry_cap_by_macid(void *mlme, u8 macid)
+{
+	PADAPTER adapter;
+	enum beamforming_cap cap = BEAMFORMING_CAP_NONE;
+
+
+	adapter = mlme_to_adapter((struct mlme_priv *)mlme);
+	cap = _bfee_get_entry_cap_by_macid(adapter, macid);
+
+	return cap;
+}
+
+struct beamformer_entry *rtw_bf_bfer_get_entry_by_addr(PADAPTER adapter, u8 *ra)
+{
+	return _bfer_get_entry_by_addr(adapter, ra);
+}
+
+struct beamformee_entry *rtw_bf_bfee_get_entry_by_addr(PADAPTER adapter, u8 *ra)
+{
+	return _bfee_get_entry_by_addr(adapter, ra);
+}
+
+void rtw_bf_get_ndpa_packet(PADAPTER adapter, union recv_frame *precv_frame)
+{
+	RTW_DBG("+%s\n", __FUNCTION__);
+}
+
+u32 rtw_bf_get_report_packet(PADAPTER adapter, union recv_frame *precv_frame)
+{
+	u32 ret = _SUCCESS;
+	struct beamforming_info *info;
+	struct beamformee_entry *bfee = NULL;
+	u8 *pframe;
+	u32 frame_len;
+	u8 *ta;
+	u8 *frame_body;
+	u8 category, action;
+	u8 *pMIMOCtrlField, *pCSIMatrix;
+	u8 Nc = 0, Nr = 0, CH_W = 0, Ng = 0, CodeBook = 0;
+	u16 CSIMatrixLen = 0;
+
+
+	RTW_INFO("+%s\n", __FUNCTION__);
+
+	info = GET_BEAMFORM_INFO(adapter);
+	pframe = precv_frame->u.hdr.rx_data;
+	frame_len = precv_frame->u.hdr.len;
+
+	/* Memory comparison to see if CSI report is the same with previous one */
+	ta = get_addr2_ptr(pframe);
+	bfee = _bfee_get_entry_by_addr(adapter, ta);
+	if (!bfee)
+		return _FAIL;
+
+	frame_body = pframe + sizeof(struct rtw_ieee80211_hdr_3addr);
+	category = frame_body[0];
+	action = frame_body[1];
+
+	if ((category == RTW_WLAN_CATEGORY_VHT)
+	    && (action == RTW_WLAN_ACTION_VHT_COMPRESSED_BEAMFORMING)) {
+		pMIMOCtrlField = pframe + 26;
+		Nc = (*pMIMOCtrlField) & 0x7;
+		Nr = ((*pMIMOCtrlField) & 0x38) >> 3;
+		CH_W =  (((*pMIMOCtrlField) & 0xC0) >> 6);
+		Ng = (*(pMIMOCtrlField+1)) & 0x3;
+		CodeBook = ((*(pMIMOCtrlField+1)) & 0x4) >> 2;
+		/*
+		 * 24+(1+1+3)+2
+		 * ==> MAC header+(Category+ActionCode+MIMOControlField)+SNR(Nc=2)
+		 */
+		pCSIMatrix = pMIMOCtrlField + 3 + Nc;
+		CSIMatrixLen = frame_len - 26 - 3 - Nc;
+		info->TargetCSIInfo.bVHT = _TRUE;
+	} else if ((category == RTW_WLAN_CATEGORY_HT)
+		   && (action == RTW_WLAN_ACTION_HT_COMPRESS_BEAMFORMING)) {
+		pMIMOCtrlField = pframe + 26;
+		Nc = (*pMIMOCtrlField) & 0x3;
+		Nr = ((*pMIMOCtrlField) & 0xC) >> 2;
+		CH_W = ((*pMIMOCtrlField) & 0x10) >> 4;
+		Ng = ((*pMIMOCtrlField) & 0x60) >> 5;
+		CodeBook = ((*(pMIMOCtrlField+1)) & 0x6) >> 1;
+		/*
+		 * 24+(1+1+6)+2
+		 * ==> MAC header+(Category+ActionCode+MIMOControlField)+SNR(Nc=2)
+		 */
+		pCSIMatrix = pMIMOCtrlField + 6 + Nr;
+		CSIMatrixLen = frame_len  - 26 - 6 - Nr;
+		info->TargetCSIInfo.bVHT = _FALSE;
+	}
+
+	/* Update current CSI report info */
+	if ((_TRUE == info->bEnableSUTxBFWorkAround)
+	    && (info->TargetSUBFee == bfee)) {
+		if ((info->TargetCSIInfo.Nc != Nc) || (info->TargetCSIInfo.Nr != Nr) ||
+			(info->TargetCSIInfo.ChnlWidth != CH_W) || (info->TargetCSIInfo.Ng != Ng) ||
+			(info->TargetCSIInfo.CodeBook != CodeBook)) {
+			info->TargetCSIInfo.Nc = Nc;
+			info->TargetCSIInfo.Nr = Nr;
+			info->TargetCSIInfo.ChnlWidth = CH_W;
+			info->TargetCSIInfo.Ng = Ng;
+			info->TargetCSIInfo.CodeBook = CodeBook;
+
+			rtw_bf_cmd(adapter, BEAMFORMING_CTRL_SET_CSI_REPORT, (u8*)&info->TargetCSIInfo, sizeof(struct _RT_CSI_INFO), 1);
+		}
+	}
+
+	RTW_INFO("%s: pkt type=%d-%d, Nc=%d, Nr=%d, CH_W=%d, Ng=%d, CodeBook=%d\n",
+		 __FUNCTION__, category, action, Nc, Nr, CH_W, Ng, CodeBook);
+
+	return ret;
+}
+
+u8 rtw_bf_send_vht_gid_mgnt_packet(PADAPTER adapter, u8 *ra, u8 *gid, u8 *position)
+{
+	/* General */
+	struct xmit_priv *xmitpriv;
+	struct mlme_priv *mlmepriv;
+	struct xmit_frame *pmgntframe;
+	/* MISC */
+	struct pkt_attrib *attrib;
+	struct rtw_ieee80211_hdr *wlanhdr;
+	u8 *pframe, *ptr;
+
+
+	xmitpriv = &adapter->xmitpriv;
+	mlmepriv = &adapter->mlmepriv;
+
+	pmgntframe = alloc_mgtxmitframe(xmitpriv);
+	if (!pmgntframe)
+		return _FALSE;
+
+	/* update attribute */
+	attrib = &pmgntframe->attrib;
+	update_mgntframe_attrib(adapter, attrib);
+	attrib->rate = MGN_6M;
+	attrib->bwmode = CHANNEL_WIDTH_20;
+	attrib->subtype = WIFI_ACTION;
+
+	_rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET);
+
+	pframe = (u8 *)pmgntframe->buf_addr + TXDESC_OFFSET;
+	wlanhdr = (struct rtw_ieee80211_hdr *)pframe;
+
+	wlanhdr->frame_ctl = 0;
+	set_frame_sub_type(pframe, attrib->subtype);
+	set_duration(pframe, 0);
+	SetFragNum(pframe, 0);
+	SetSeqNum(pframe, 0);
+
+	_rtw_memcpy(wlanhdr->addr1, ra, ETH_ALEN);
+	_rtw_memcpy(wlanhdr->addr2, adapter_mac_addr(adapter), ETH_ALEN);
+	_rtw_memcpy(wlanhdr->addr3, get_bssid(mlmepriv), ETH_ALEN);
+
+	pframe[24] = RTW_WLAN_CATEGORY_VHT;
+	pframe[25] = RTW_WLAN_ACTION_VHT_GROUPID_MANAGEMENT;
+	/* Set Membership Status Array */
+	ptr = pframe + 26;
+	_rtw_memcpy(ptr, gid, 8);
+	/* Set User Position Array */
+	ptr = pframe + 34;
+	_rtw_memcpy(ptr, position, 16);
+
+	attrib->pktlen = 54;
+	attrib->last_txcmdsz = attrib->pktlen;
+
+	dump_mgntframe(adapter, pmgntframe);
+
+	return _TRUE;
+}
+
+/*
+ * Description:
+ *	On VHT GID management frame by an MU beamformee.
+ */
+void rtw_bf_get_vht_gid_mgnt_packet(PADAPTER adapter, union recv_frame *precv_frame)
+{
+	u8 *pframe;
+	u8 *ta, *gid, *position;
+
+
+	RTW_DBG("+%s\n", __FUNCTION__);
+
+	pframe = precv_frame->u.hdr.rx_data;
+
+	/* Get address by Addr2 */
+	ta = get_addr2_ptr(pframe);
+	/* Remove signaling TA */
+	ta[0] &= 0xFE;
+
+	/* Membership Status Array */
+	gid = pframe + 26;
+	/* User Position Array */
+	position= pframe + 34;
+
+	_bfer_set_entry_gid(adapter, ta, gid, position);
+}
+
+void rtw_bf_init(PADAPTER adapter)
+{
+	struct beamforming_info	*info;
+
+
+	info = GET_BEAMFORM_INFO(adapter);
+	info->beamforming_cap = BEAMFORMING_CAP_NONE;
+	info->beamforming_state = BEAMFORMING_STATE_IDLE;
+/*
+	info->bfee_entry[MAX_BEAMFORMEE_ENTRY_NUM];
+	info->bfer_entry[MAX_BEAMFORMER_ENTRY_NUM];
+*/
+	info->sounding_sequence = 0;
+	info->beamformee_su_cnt = 0;
+	info->beamformer_su_cnt = 0;
+	info->beamformee_su_reg_maping = 0;
+	info->beamformer_su_reg_maping = 0;
+	info->beamformee_mu_cnt = 0;
+	info->beamformer_mu_cnt = 0;
+	info->beamformee_mu_reg_maping = 0;
+	info->first_mu_bfee_index = 0xFF;
+	info->mu_bfer_curidx = 0xFF;
+	info->cur_csi_rpt_rate = HALMAC_OFDM24;
+
+	_sounding_init(&info->sounding_info);
+	rtw_init_timer(&info->sounding_timer, adapter, _sounding_timer_handler, adapter);
+	rtw_init_timer(&info->sounding_timeout_timer, adapter, _sounding_timeout_timer_handler, adapter);
+
+	info->SetHalBFEnterOnDemandCnt = 0;
+	info->SetHalBFLeaveOnDemandCnt = 0;
+	info->SetHalSoundownOnDemandCnt = 0;
+
+	info->bEnableSUTxBFWorkAround = _TRUE;
+	info->TargetSUBFee = NULL;
+
+	info->sounding_running = 0;
+}
+
+void rtw_bf_cmd_hdl(PADAPTER adapter, u8 type, u8 *pbuf)
+{
+	switch (type) {
+	case BEAMFORMING_CTRL_ENTER:
+		_beamforming_enter(adapter, pbuf);
+		break;
+
+	case BEAMFORMING_CTRL_LEAVE:
+		if (pbuf == NULL)
+			_beamforming_reset(adapter);
+		else
+			_beamforming_leave(adapter, pbuf);
+		break;
+
+	case BEAMFORMING_CTRL_START_PERIOD:
+		_sounding_handler(adapter);
+		break;
+
+	case BEAMFORMING_CTRL_END_PERIOD:
+		_beamforming_sounding_down(adapter, *pbuf);
+		break;
+
+	case BEAMFORMING_CTRL_SET_GID_TABLE:
+		rtw_hal_set_hwreg(adapter, HW_VAR_SOUNDING_SET_GID_TABLE, pbuf);
+		break;
+
+	case BEAMFORMING_CTRL_SET_CSI_REPORT:
+		rtw_hal_set_hwreg(adapter, HW_VAR_SOUNDING_CSI_REPORT, pbuf);
+		break;
+
+	default:
+		break;
+	}
+}
+
+u8 rtw_bf_cmd(PADAPTER adapter, s32 type, u8 *pbuf, s32 size, u8 enqueue)
+{
+	struct cmd_obj *ph2c;
+	struct drvextra_cmd_parm *pdrvextra_cmd_parm;
+	struct cmd_priv	*pcmdpriv = &adapter->cmdpriv;
+	u8 *wk_buf;
+	u8 res = _SUCCESS;
+
+
+	if (!enqueue) {
+		rtw_bf_cmd_hdl(adapter, type, pbuf);
+		goto exit;
+	}
+
+	ph2c = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj));
+	if (ph2c == NULL) {
+		res = _FAIL;
+		goto exit;
+	}
+
+	pdrvextra_cmd_parm = (struct drvextra_cmd_parm *)rtw_zmalloc(sizeof(struct drvextra_cmd_parm));
+	if (pdrvextra_cmd_parm == NULL) {
+		rtw_mfree((unsigned char *)ph2c, sizeof(struct cmd_obj));
+		res = _FAIL;
+		goto exit;
+	}
+
+	if (pbuf != NULL) {
+		wk_buf = rtw_zmalloc(size);
+		if (wk_buf == NULL) {
+			rtw_mfree((u8 *)ph2c, sizeof(struct cmd_obj));
+			rtw_mfree((u8 *)pdrvextra_cmd_parm, sizeof(struct drvextra_cmd_parm));
+			res = _FAIL;
+			goto exit;
+		}
+
+		_rtw_memcpy(wk_buf, pbuf, size);
+	} else {
+		wk_buf = NULL;
+		size = 0;
+	}
+
+	pdrvextra_cmd_parm->ec_id = BEAMFORMING_WK_CID;
+	pdrvextra_cmd_parm->type = type;
+	pdrvextra_cmd_parm->size = size;
+	pdrvextra_cmd_parm->pbuf = wk_buf;
+
+	init_h2fwcmd_w_parm_no_rsp(ph2c, pdrvextra_cmd_parm, GEN_CMD_CODE(_Set_Drv_Extra));
+
+	res = rtw_enqueue_cmd(pcmdpriv, ph2c);
+
+exit:
+	return res;
+}
+
+void rtw_bf_update_attrib(PADAPTER adapter, struct pkt_attrib *attrib, struct sta_info *sta)
+{
+	if (sta) {
+		attrib->txbf_g_id = sta->cmn.bf_info.g_id;
+		attrib->txbf_p_aid = sta->cmn.bf_info.p_aid;
+	}
+}
+
+void rtw_bf_c2h_handler(PADAPTER adapter, u8 id, u8 *buf, u8 buf_len)
+{
+	switch (id) {
+	case CMD_ID_C2H_SND_TXBF:
+		_c2h_snd_txbf(adapter, buf, buf_len);
+		break;
+	}
+}
+
+#define toMbps(bytes, secs)	(rtw_division64(bytes >> 17, secs))
+void rtw_bf_update_traffic(PADAPTER adapter)
+{
+	struct beamforming_info	*info;
+	struct sounding_info *sounding;
+	struct beamformee_entry *bfee;
+	struct sta_info *sta;
+	u8 bfee_cnt, sounding_idx, i;
+	u16 tp[MAX_BEAMFORMEE_ENTRY_NUM] = {0};
+	u8 tx_rate[MAX_BEAMFORMEE_ENTRY_NUM] = {0};
+	u64 tx_bytes, last_bytes;
+	u32 time;
+	systime last_timestamp;
+	u8 set_timer = _FALSE;
+
+
+	info = GET_BEAMFORM_INFO(adapter);
+	sounding = &info->sounding_info;
+
+	/* Check any bfee exist? */
+	bfee_cnt = info->beamformee_su_cnt + info->beamformee_mu_cnt;
+	if (bfee_cnt == 0)
+		return;
+
+	for (i = 0; i < MAX_BEAMFORMEE_ENTRY_NUM; i++) {
+		bfee = &info->bfee_entry[i];
+		if (_FALSE == bfee->used)
+			continue;
+
+		sta = rtw_get_stainfo(&adapter->stapriv, bfee->mac_addr);
+		if (!sta) {
+			RTW_ERR("%s: Cann't find sta_info for " MAC_FMT "!\n", __FUNCTION__, MAC_ARG(bfee->mac_addr));
+			continue;
+		}
+
+		last_timestamp = bfee->tx_timestamp;
+		last_bytes = bfee->tx_bytes;
+		bfee->tx_timestamp = rtw_get_current_time();
+		bfee->tx_bytes = sta->sta_stats.tx_bytes;
+		if (last_timestamp) {
+			if (bfee->tx_bytes >= last_bytes)
+				tx_bytes = bfee->tx_bytes - last_bytes;
+			else
+				tx_bytes = bfee->tx_bytes + (~last_bytes);
+			time = rtw_get_time_interval_ms(last_timestamp, bfee->tx_timestamp);
+			time = (time > 1000) ? time/1000 : 1;
+			tp[i] = toMbps(tx_bytes, time);
+			tx_rate[i] = rtw_get_current_tx_rate(adapter, sta);
+			RTW_INFO("%s: BFee idx(%d), MadId(%d), TxTP=%lld bytes (%d Mbps), txrate=%d\n",
+				 __FUNCTION__, i, bfee->mac_id, tx_bytes, tp[i], tx_rate[i]);
+		}
+	}
+
+	sounding_idx = phydm_get_beamforming_sounding_info(GET_PDM_ODM(adapter), tp, MAX_BEAMFORMEE_ENTRY_NUM, tx_rate);
+
+	for (i = 0; i < MAX_BEAMFORMEE_ENTRY_NUM; i++) {
+		bfee = &info->bfee_entry[i];
+		if (_FALSE == bfee->used) {
+			if (sounding_idx & BIT(i))
+				RTW_WARN("%s: bfee(%d) not in used but need sounding?!\n", __FUNCTION__, i);
+			continue;
+		}
+
+		if (sounding_idx & BIT(i)) {
+			if (_FALSE == bfee->bApplySounding) {
+				bfee->bApplySounding = _TRUE;
+				bfee->SoundCnt = 0;
+				set_timer = _TRUE;
+			}
+		} else {
+			if (_TRUE == bfee->bApplySounding) {
+				bfee->bApplySounding = _FALSE;
+				bfee->bDeleteSounding = _TRUE;
+				bfee->SoundCnt = 0;
+				set_timer = _TRUE;
+			}
+		}
+	}
+
+	if (_TRUE == set_timer) {
+		if (SOUNDING_STATE_NONE == info->sounding_info.state) {
+			info->sounding_info.state = SOUNDING_STATE_INIT;
+			_set_timer(&info->sounding_timer, 0);
+		}
+	}
+}
+
+#else /* !RTW_BEAMFORMING_VERSION_2 */
+
+#if (BEAMFORMING_SUPPORT == 0) /*for diver defined beamforming*/
+struct beamforming_entry	*beamforming_get_entry_by_addr(struct mlme_priv *pmlmepriv, u8 *ra, u8 *idx)
+{
+	u8	i = 0;
+	struct beamforming_info	*pBeamInfo = GET_BEAMFORM_INFO(pmlmepriv);
+
+	for (i = 0; i < BEAMFORMING_ENTRY_NUM; i++) {
+		if (pBeamInfo->beamforming_entry[i].bUsed &&
+		    (_rtw_memcmp(ra, pBeamInfo->beamforming_entry[i].mac_addr, ETH_ALEN))) {
+			*idx = i;
+			return &(pBeamInfo->beamforming_entry[i]);
+		}
+	}
+
+	return NULL;
+}
+
+BEAMFORMING_CAP beamforming_get_entry_beam_cap_by_mac_id(PVOID pmlmepriv , u8 mac_id)
+{
+	u8	i = 0;
+	struct beamforming_info	*pBeamInfo = GET_BEAMFORM_INFO((struct mlme_priv *)pmlmepriv);
+	BEAMFORMING_CAP		BeamformEntryCap = BEAMFORMING_CAP_NONE;
+
+	for (i = 0; i < BEAMFORMING_ENTRY_NUM; i++) {
+		if (pBeamInfo->beamforming_entry[i].bUsed &&
+		    (mac_id == pBeamInfo->beamforming_entry[i].mac_id)) {
+			BeamformEntryCap =  pBeamInfo->beamforming_entry[i].beamforming_entry_cap;
+			i = BEAMFORMING_ENTRY_NUM;
+		}
+	}
+
+	return BeamformEntryCap;
+}
+
+struct beamforming_entry	*beamforming_get_free_entry(struct mlme_priv *pmlmepriv, u8 *idx)
+{
+	u8	i = 0;
+	struct beamforming_info	*pBeamInfo = GET_BEAMFORM_INFO(pmlmepriv);
+
+	for (i = 0; i < BEAMFORMING_ENTRY_NUM; i++) {
+		if (pBeamInfo->beamforming_entry[i].bUsed == _FALSE) {
+			*idx = i;
+			return &(pBeamInfo->beamforming_entry[i]);
+		}
+	}
+	return NULL;
+}
+
+
+struct beamforming_entry	*beamforming_add_entry(PADAPTER adapter, u8 *ra, u16 aid,
+	u16 mac_id, enum channel_width bw, BEAMFORMING_CAP beamfrom_cap, u8 *idx)
+{
+	struct mlme_priv			*pmlmepriv = &(adapter->mlmepriv);
+	struct beamforming_entry	*pEntry = beamforming_get_free_entry(pmlmepriv, idx);
+
+	if (pEntry != NULL) {
+		pEntry->bUsed = _TRUE;
+		pEntry->aid = aid;
+		pEntry->mac_id = mac_id;
+		pEntry->sound_bw = bw;
+		if (check_fwstate(pmlmepriv, WIFI_AP_STATE)) {
+			u16	BSSID = ((*(adapter_mac_addr(adapter) + 5) & 0xf0) >> 4) ^
+				(*(adapter_mac_addr(adapter) + 5) & 0xf); /* BSSID[44:47] xor BSSID[40:43] */
+			pEntry->p_aid = (aid + BSSID * 32) & 0x1ff;		/* (dec(A) + dec(B)*32) mod 512 */
+			pEntry->g_id = 63;
+		} else if (check_fwstate(pmlmepriv, WIFI_ADHOC_STATE) || check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE)) {
+			pEntry->p_aid = 0;
+			pEntry->g_id = 63;
+		} else {
+			pEntry->p_aid =  ra[5];						/* BSSID[39:47] */
+			pEntry->p_aid = (pEntry->p_aid << 1) | (ra[4] >> 7);
+			pEntry->g_id = 0;
+		}
+		_rtw_memcpy(pEntry->mac_addr, ra, ETH_ALEN);
+		pEntry->bSound = _FALSE;
+
+		/* 3 TODO SW/FW sound period */
+		pEntry->sound_period = 200;
+		pEntry->beamforming_entry_cap = beamfrom_cap;
+		pEntry->beamforming_entry_state = BEAMFORMING_ENTRY_STATE_UNINITIALIZE;
+
+
+		pEntry->PreLogSeq = 0;	/*Modified by Jeffery @2015-04-13*/
+		pEntry->LogSeq = 0;		/*Modified by Jeffery @2014-10-29*/
+		pEntry->LogRetryCnt = 0;	/*Modified by Jeffery @2014-10-29*/
+		pEntry->LogSuccess = 0;	/*LogSuccess is NOT needed to be accumulated, so  LogSuccessCnt->LogSuccess, 2015-04-13, Jeffery*/
+		pEntry->ClockResetTimes = 0;	/*Modified by Jeffery @2015-04-13*/
+		pEntry->LogStatusFailCnt = 0;
+
+		return pEntry;
+	} else
+		return NULL;
+}
+
+BOOLEAN	beamforming_remove_entry(struct mlme_priv *pmlmepriv, u8 *ra, u8 *idx)
+{
+	struct beamforming_entry	*pEntry = beamforming_get_entry_by_addr(pmlmepriv, ra, idx);
+
+	if (pEntry != NULL) {
+		pEntry->bUsed = _FALSE;
+		pEntry->beamforming_entry_cap = BEAMFORMING_CAP_NONE;
+		pEntry->beamforming_entry_state = BEAMFORMING_ENTRY_STATE_UNINITIALIZE;
+		return _TRUE;
+	} else
+		return _FALSE;
+}
+
+/* Used for BeamformingStart_V1 */
+void	beamforming_dym_ndpa_rate(PADAPTER adapter)
+{
+	u16	NDPARate = MGN_6M;
+	PHAL_DATA_TYPE	pHalData = GET_HAL_DATA(adapter);
+	s8 min_rssi = 0;
+
+	min_rssi = rtw_phydm_get_min_rssi(adapter);
+	if (min_rssi > 30) /* link RSSI > 30% */
+		NDPARate = MGN_24M;
+	else
+		NDPARate = MGN_6M;
+
+	/* BW = CHANNEL_WIDTH_20; */
+	NDPARate = NDPARate << 8;
+	rtw_hal_set_hwreg(adapter, HW_VAR_SOUNDING_RATE, (u8 *)&NDPARate);
+}
+
+void beamforming_dym_period(PADAPTER Adapter)
+{
+	u8	Idx;
+	BOOLEAN	bChangePeriod = _FALSE;
+	u16	SoundPeriod_SW, SoundPeriod_FW;
+	PHAL_DATA_TYPE	pHalData = GET_HAL_DATA(Adapter);
+	struct dvobj_priv	*pdvobjpriv = adapter_to_dvobj(Adapter);
+	struct beamforming_entry	*pBeamformEntry;
+	struct beamforming_info	*pBeamInfo = GET_BEAMFORM_INFO((&Adapter->mlmepriv));
+	struct sounding_info		*pSoundInfo = &(pBeamInfo->sounding_info);
+
+	/* 3 TODO  per-client throughput caculation. */
+
+	if (pdvobjpriv->traffic_stat.cur_tx_tp + pdvobjpriv->traffic_stat.cur_rx_tp > 2) {
+		SoundPeriod_SW = 32 * 20;
+		SoundPeriod_FW = 2;
+	} else {
+		SoundPeriod_SW = 32 * 2000;
+		SoundPeriod_FW = 200;
+	}
+
+	for (Idx = 0; Idx < BEAMFORMING_ENTRY_NUM; Idx++) {
+		pBeamformEntry = pBeamInfo->beamforming_entry + Idx;
+		if (pBeamformEntry->bDefaultCSI) {
+			SoundPeriod_SW = 32 * 2000;
+			SoundPeriod_FW = 200;
+		}
+
+		if (pBeamformEntry->beamforming_entry_cap & (BEAMFORMER_CAP_HT_EXPLICIT | BEAMFORMER_CAP_VHT_SU)) {
+			if (pSoundInfo->sound_mode == SOUNDING_FW_VHT_TIMER || pSoundInfo->sound_mode == SOUNDING_FW_HT_TIMER) {
+				if (pBeamformEntry->sound_period != SoundPeriod_FW) {
+					pBeamformEntry->sound_period = SoundPeriod_FW;
+					bChangePeriod = _TRUE;	/* Only FW sounding need to send H2C packet to change sound period. */
+				}
+			} else if (pBeamformEntry->sound_period != SoundPeriod_SW)
+				pBeamformEntry->sound_period = SoundPeriod_SW;
+		}
+	}
+
+	if (bChangePeriod)
+		rtw_hal_set_hwreg(Adapter, HW_VAR_SOUNDING_FW_NDPA, (u8 *)&Idx);
+}
+
+BOOLEAN	issue_ht_sw_ndpa_packet(PADAPTER Adapter, u8 *ra, enum channel_width bw, u8 qidx)
+{
+	struct xmit_frame		*pmgntframe;
+	struct pkt_attrib		*pattrib;
+	struct rtw_ieee80211_hdr	*pwlanhdr;
+	struct xmit_priv		*pxmitpriv = &(Adapter->xmitpriv);
+	struct mlme_ext_priv	*pmlmeext = &Adapter->mlmeextpriv;
+	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
+	u8	ActionHdr[4] = {ACT_CAT_VENDOR, 0x00, 0xe0, 0x4c};
+	u8	*pframe;
+	u16	*fctrl;
+	u16	duration = 0;
+	u8	aSifsTime = 0;
+	u8	NDPTxRate = 0;
+
+	RTW_INFO("%s: issue_ht_sw_ndpa_packet!\n", __func__);
+
+	NDPTxRate = MGN_MCS8;
+	RTW_INFO("%s: NDPTxRate =%d\n", __func__, NDPTxRate);
+	pmgntframe = alloc_mgtxmitframe(pxmitpriv);
+
+	if (pmgntframe == NULL)
+		return _FALSE;
+
+	/*update attribute*/
+	pattrib = &pmgntframe->attrib;
+	update_mgntframe_attrib(Adapter, pattrib);
+	pattrib->qsel = QSLT_MGNT;
+	pattrib->rate = NDPTxRate;
+	pattrib->bwmode = bw;
+	pattrib->order = 1;
+	pattrib->subtype = WIFI_ACTION_NOACK;
+
+	_rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET);
+
+	pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET;
+
+	pwlanhdr = (struct rtw_ieee80211_hdr *)pframe;
+
+	fctrl = &pwlanhdr->frame_ctl;
+	*(fctrl) = 0;
+
+	set_order_bit(pframe);
+	set_frame_sub_type(pframe, WIFI_ACTION_NOACK);
+
+	_rtw_memcpy(pwlanhdr->addr1, ra, ETH_ALEN);
+	_rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(Adapter), ETH_ALEN);
+	_rtw_memcpy(pwlanhdr->addr3, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN);
+
+	if (pmlmeext->cur_wireless_mode == WIRELESS_11B)
+		aSifsTime = 10;
+	else
+		aSifsTime = 16;
+
+	duration = 2 * aSifsTime + 40;
+
+	if (bw == CHANNEL_WIDTH_40)
+		duration += 87;
+	else
+		duration += 180;
+
+	set_duration(pframe, duration);
+
+	/*HT control field*/
+	SET_HT_CTRL_CSI_STEERING(pframe + 24, 3);
+	SET_HT_CTRL_NDP_ANNOUNCEMENT(pframe + 24, 1);
+
+	_rtw_memcpy(pframe + 28, ActionHdr, 4);
+
+	pattrib->pktlen = 32;
+
+	pattrib->last_txcmdsz = pattrib->pktlen;
+
+	dump_mgntframe(Adapter, pmgntframe);
+
+	return _TRUE;
+
+
+}
+BOOLEAN	issue_ht_ndpa_packet(PADAPTER Adapter, u8 *ra, enum channel_width bw, u8 qidx)
+{
+	struct xmit_frame		*pmgntframe;
+	struct pkt_attrib		*pattrib;
+	struct rtw_ieee80211_hdr	*pwlanhdr;
+	struct xmit_priv		*pxmitpriv = &(Adapter->xmitpriv);
+	struct mlme_ext_priv	*pmlmeext = &Adapter->mlmeextpriv;
+	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
+	u8	ActionHdr[4] = {ACT_CAT_VENDOR, 0x00, 0xe0, 0x4c};
+	u8	*pframe;
+	u16	*fctrl;
+	u16	duration = 0;
+	u8	aSifsTime = 0;
+
+	pmgntframe = alloc_mgtxmitframe(pxmitpriv);
+
+	if (pmgntframe == NULL)
+		return _FALSE;
+
+	/*update attribute*/
+	pattrib = &pmgntframe->attrib;
+	update_mgntframe_attrib(Adapter, pattrib);
+
+	if (qidx == BCN_QUEUE_INX)
+		pattrib->qsel = QSLT_BEACON;
+	pattrib->rate = MGN_MCS8;
+	pattrib->bwmode = bw;
+	pattrib->order = 1;
+	pattrib->subtype = WIFI_ACTION_NOACK;
+
+	_rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET);
+
+	pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET;
+
+	pwlanhdr = (struct rtw_ieee80211_hdr *)pframe;
+
+	fctrl = &pwlanhdr->frame_ctl;
+	*(fctrl) = 0;
+
+	set_order_bit(pframe);
+	set_frame_sub_type(pframe, WIFI_ACTION_NOACK);
+
+	_rtw_memcpy(pwlanhdr->addr1, ra, ETH_ALEN);
+	_rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(Adapter), ETH_ALEN);
+	_rtw_memcpy(pwlanhdr->addr3, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN);
+
+	if (pmlmeext->cur_wireless_mode == WIRELESS_11B)
+		aSifsTime = 10;
+	else
+		aSifsTime = 16;
+
+	duration = 2 * aSifsTime + 40;
+
+	if (bw == CHANNEL_WIDTH_40)
+		duration += 87;
+	else
+		duration += 180;
+
+	set_duration(pframe, duration);
+
+	/* HT control field */
+	SET_HT_CTRL_CSI_STEERING(pframe + 24, 3);
+	SET_HT_CTRL_NDP_ANNOUNCEMENT(pframe + 24, 1);
+
+	_rtw_memcpy(pframe + 28, ActionHdr, 4);
+
+	pattrib->pktlen = 32;
+
+	pattrib->last_txcmdsz = pattrib->pktlen;
+
+	dump_mgntframe(Adapter, pmgntframe);
+
+	return _TRUE;
+}
+
+BOOLEAN	beamforming_send_ht_ndpa_packet(PADAPTER Adapter, u8 *ra, enum channel_width bw, u8 qidx)
+{
+	return issue_ht_ndpa_packet(Adapter, ra, bw, qidx);
+}
+BOOLEAN	issue_vht_sw_ndpa_packet(PADAPTER Adapter, u8 *ra, u16 aid, enum channel_width bw, u8 qidx)
+{
+	struct xmit_frame		*pmgntframe;
+	struct pkt_attrib		*pattrib;
+	struct rtw_ieee80211_hdr	*pwlanhdr;
+	struct xmit_priv		*pxmitpriv = &(Adapter->xmitpriv);
+	struct mlme_ext_priv	*pmlmeext = &Adapter->mlmeextpriv;
+	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
+	struct mlme_priv		*pmlmepriv = &(Adapter->mlmepriv);
+	struct beamforming_info	*pBeamInfo = GET_BEAMFORM_INFO(pmlmepriv);
+	struct rtw_ndpa_sta_info	sta_info;
+	u8		 NDPTxRate = 0;
+
+	u8	*pframe;
+	u16	*fctrl;
+	u16	duration = 0;
+	u8	sequence = 0, aSifsTime = 0;
+
+	RTW_INFO("%s: issue_vht_sw_ndpa_packet!\n", __func__);
+
+
+	NDPTxRate = MGN_VHT2SS_MCS0;
+	RTW_INFO("%s: NDPTxRate =%d\n", __func__, NDPTxRate);
+	pmgntframe = alloc_mgtxmitframe(pxmitpriv);
+
+	if (pmgntframe == NULL) {
+		RTW_INFO("%s, alloc mgnt frame fail\n", __func__);
+		return _FALSE;
+	}
+
+	/*update attribute*/
+	pattrib = &pmgntframe->attrib;
+	update_mgntframe_attrib(Adapter, pattrib);
+	pattrib->qsel = QSLT_MGNT;
+	pattrib->rate = NDPTxRate;
+	pattrib->bwmode = bw;
+	pattrib->subtype = WIFI_NDPA;
+
+	_rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET);
+
+	pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET;
+
+	pwlanhdr = (struct rtw_ieee80211_hdr *)pframe;
+
+	fctrl = &pwlanhdr->frame_ctl;
+	*(fctrl) = 0;
+
+	set_frame_sub_type(pframe, WIFI_NDPA);
+
+	_rtw_memcpy(pwlanhdr->addr1, ra, ETH_ALEN);
+	_rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(Adapter), ETH_ALEN);
+
+	if (is_supported_5g(pmlmeext->cur_wireless_mode) || is_supported_ht(pmlmeext->cur_wireless_mode))
+		aSifsTime = 16;
+	else
+		aSifsTime = 10;
+
+	duration = 2 * aSifsTime + 44;
+
+	if (bw == CHANNEL_WIDTH_80)
+		duration += 40;
+	else if (bw == CHANNEL_WIDTH_40)
+		duration += 87;
+	else
+		duration += 180;
+
+	set_duration(pframe, duration);
+
+	sequence = pBeamInfo->sounding_sequence << 2;
+	if (pBeamInfo->sounding_sequence >= 0x3f)
+		pBeamInfo->sounding_sequence = 0;
+	else
+		pBeamInfo->sounding_sequence++;
+
+	_rtw_memcpy(pframe + 16, &sequence, 1);
+	if (((pmlmeinfo->state & 0x03) == WIFI_FW_ADHOC_STATE) || ((pmlmeinfo->state & 0x03) == WIFI_FW_AP_STATE))
+		aid = 0;
+
+	sta_info.aid = aid;
+	sta_info.feedback_type = 0;
+	sta_info.nc_index = 0;
+
+	_rtw_memcpy(pframe + 17, (u8 *)&sta_info, 2);
+
+	pattrib->pktlen = 19;
+
+	pattrib->last_txcmdsz = pattrib->pktlen;
+
+	dump_mgntframe(Adapter, pmgntframe);
+
+
+	return _TRUE;
+
+}
+BOOLEAN	issue_vht_ndpa_packet(PADAPTER Adapter, u8 *ra, u16 aid, enum channel_width bw, u8 qidx)
+{
+	struct xmit_frame		*pmgntframe;
+	struct pkt_attrib		*pattrib;
+	struct rtw_ieee80211_hdr	*pwlanhdr;
+	struct xmit_priv		*pxmitpriv = &(Adapter->xmitpriv);
+	struct mlme_ext_priv	*pmlmeext = &Adapter->mlmeextpriv;
+	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
+	struct mlme_priv		*pmlmepriv = &(Adapter->mlmepriv);
+	struct beamforming_info	*pBeamInfo = GET_BEAMFORM_INFO(pmlmepriv);
+	struct rtw_ndpa_sta_info	sta_info;
+	u8	*pframe;
+	u16	*fctrl;
+	u16	duration = 0;
+	u8	sequence = 0, aSifsTime = 0;
+
+	pmgntframe = alloc_mgtxmitframe(pxmitpriv);
+	if (pmgntframe == NULL)
+		return _FALSE;
+
+	/*update attribute*/
+	pattrib = &pmgntframe->attrib;
+	update_mgntframe_attrib(Adapter, pattrib);
+
+	if (qidx == BCN_QUEUE_INX)
+		pattrib->qsel = QSLT_BEACON;
+	pattrib->rate = MGN_VHT2SS_MCS0;
+	pattrib->bwmode = bw;
+	pattrib->subtype = WIFI_NDPA;
+
+	_rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET);
+
+	pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET;
+
+	pwlanhdr = (struct rtw_ieee80211_hdr *)pframe;
+
+	fctrl = &pwlanhdr->frame_ctl;
+	*(fctrl) = 0;
+
+	set_frame_sub_type(pframe, WIFI_NDPA);
+
+	_rtw_memcpy(pwlanhdr->addr1, ra, ETH_ALEN);
+	_rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(Adapter), ETH_ALEN);
+
+	if (is_supported_5g(pmlmeext->cur_wireless_mode) || is_supported_ht(pmlmeext->cur_wireless_mode))
+		aSifsTime = 16;
+	else
+		aSifsTime = 10;
+
+	duration = 2 * aSifsTime + 44;
+
+	if (bw == CHANNEL_WIDTH_80)
+		duration += 40;
+	else if (bw == CHANNEL_WIDTH_40)
+		duration += 87;
+	else
+		duration += 180;
+
+	set_duration(pframe, duration);
+
+	sequence = pBeamInfo->sounding_sequence << 2;
+	if (pBeamInfo->sounding_sequence >= 0x3f)
+		pBeamInfo->sounding_sequence = 0;
+	else
+		pBeamInfo->sounding_sequence++;
+
+	_rtw_memcpy(pframe + 16, &sequence, 1);
+
+	if (((pmlmeinfo->state & 0x03) == WIFI_FW_ADHOC_STATE) || ((pmlmeinfo->state & 0x03) == WIFI_FW_AP_STATE))
+		aid = 0;
+
+	sta_info.aid = aid;
+	sta_info.feedback_type = 0;
+	sta_info.nc_index = 0;
+
+	_rtw_memcpy(pframe + 17, (u8 *)&sta_info, 2);
+
+	pattrib->pktlen = 19;
+
+	pattrib->last_txcmdsz = pattrib->pktlen;
+
+	dump_mgntframe(Adapter, pmgntframe);
+
+	return _TRUE;
+}
+
+BOOLEAN	beamforming_send_vht_ndpa_packet(PADAPTER Adapter, u8 *ra, u16 aid, enum channel_width bw, u8 qidx)
+{
+	return issue_vht_ndpa_packet(Adapter, ra, aid, bw, qidx);
+}
+
+BOOLEAN	beamfomring_bSounding(struct beamforming_info *pBeamInfo)
+{
+	BOOLEAN		bSounding = _FALSE;
+
+	if ((beamforming_get_beamform_cap(pBeamInfo) & BEAMFORMER_CAP) == 0)
+		bSounding = _FALSE;
+	else
+		bSounding = _TRUE;
+
+	return bSounding;
+}
+
+u8	beamforming_sounding_idx(struct beamforming_info *pBeamInfo)
+{
+	u8	idx = 0;
+	u8	i;
+
+	for (i = 0; i < BEAMFORMING_ENTRY_NUM; i++) {
+		if (pBeamInfo->beamforming_entry[i].bUsed &&
+		    (_FALSE == pBeamInfo->beamforming_entry[i].bSound)) {
+			idx = i;
+			break;
+		}
+	}
+
+	return idx;
+}
+
+SOUNDING_MODE	beamforming_sounding_mode(struct beamforming_info *pBeamInfo, u8 idx)
+{
+	struct beamforming_entry	BeamEntry = pBeamInfo->beamforming_entry[idx];
+	SOUNDING_MODE	mode;
+
+	if (BeamEntry.beamforming_entry_cap & BEAMFORMER_CAP_VHT_SU)
+		mode = SOUNDING_FW_VHT_TIMER;
+	else if (BeamEntry.beamforming_entry_cap & BEAMFORMER_CAP_HT_EXPLICIT)
+		mode = SOUNDING_FW_HT_TIMER;
+	else
+		mode = SOUNDING_STOP_All_TIMER;
+
+	return mode;
+}
+
+u16	beamforming_sounding_time(struct beamforming_info *pBeamInfo, SOUNDING_MODE mode, u8 idx)
+{
+	u16						sounding_time = 0xffff;
+	struct beamforming_entry	BeamEntry = pBeamInfo->beamforming_entry[idx];
+
+	sounding_time = BeamEntry.sound_period;
+
+	return sounding_time;
+}
+
+enum channel_width	beamforming_sounding_bw(struct beamforming_info *pBeamInfo, SOUNDING_MODE mode, u8 idx)
+{
+	enum channel_width				sounding_bw = CHANNEL_WIDTH_20;
+	struct beamforming_entry		BeamEntry = pBeamInfo->beamforming_entry[idx];
+
+	sounding_bw = BeamEntry.sound_bw;
+
+	return sounding_bw;
+}
+
+BOOLEAN	beamforming_select_beam_entry(struct beamforming_info *pBeamInfo)
+{
+	struct sounding_info		*pSoundInfo = &(pBeamInfo->sounding_info);
+
+	pSoundInfo->sound_idx = beamforming_sounding_idx(pBeamInfo);
+
+	if (pSoundInfo->sound_idx < BEAMFORMING_ENTRY_NUM)
+		pSoundInfo->sound_mode = beamforming_sounding_mode(pBeamInfo, pSoundInfo->sound_idx);
+	else
+		pSoundInfo->sound_mode = SOUNDING_STOP_All_TIMER;
+
+	if (SOUNDING_STOP_All_TIMER == pSoundInfo->sound_mode)
+		return _FALSE;
+	else {
+		pSoundInfo->sound_bw = beamforming_sounding_bw(pBeamInfo, pSoundInfo->sound_mode, pSoundInfo->sound_idx);
+		pSoundInfo->sound_period = beamforming_sounding_time(pBeamInfo, pSoundInfo->sound_mode, pSoundInfo->sound_idx);
+		return _TRUE;
+	}
+}
+
+BOOLEAN	beamforming_start_fw(PADAPTER adapter, u8 idx)
+{
+	u8						*RA = NULL;
+	struct beamforming_entry	*pEntry;
+	BOOLEAN					ret = _TRUE;
+	struct mlme_priv			*pmlmepriv = &(adapter->mlmepriv);
+	struct beamforming_info	*pBeamInfo = GET_BEAMFORM_INFO(pmlmepriv);
+
+	pEntry = &(pBeamInfo->beamforming_entry[idx]);
+	if (pEntry->bUsed == _FALSE) {
+		RTW_INFO("Skip Beamforming, no entry for Idx =%d\n", idx);
+		return _FALSE;
+	}
+
+	pEntry->beamforming_entry_state = BEAMFORMING_ENTRY_STATE_PROGRESSING;
+	pEntry->bSound = _TRUE;
+	rtw_hal_set_hwreg(adapter, HW_VAR_SOUNDING_FW_NDPA, (u8 *)&idx);
+
+	return _TRUE;
+}
+
+void	beamforming_end_fw(PADAPTER adapter)
+{
+	u8	idx = 0;
+
+	rtw_hal_set_hwreg(adapter, HW_VAR_SOUNDING_FW_NDPA, (u8 *)&idx);
+
+	RTW_INFO("%s\n", __FUNCTION__);
+}
+
+BOOLEAN	beamforming_start_period(PADAPTER adapter)
+{
+	BOOLEAN	ret = _TRUE;
+	struct mlme_priv			*pmlmepriv = &(adapter->mlmepriv);
+	struct beamforming_info	*pBeamInfo = GET_BEAMFORM_INFO(pmlmepriv);
+	struct sounding_info		*pSoundInfo = &(pBeamInfo->sounding_info);
+
+	beamforming_dym_ndpa_rate(adapter);
+
+	beamforming_select_beam_entry(pBeamInfo);
+
+	if (pSoundInfo->sound_mode == SOUNDING_FW_VHT_TIMER || pSoundInfo->sound_mode == SOUNDING_FW_HT_TIMER)
+		ret = beamforming_start_fw(adapter, pSoundInfo->sound_idx);
+	else
+		ret = _FALSE;
+
+	RTW_INFO("%s Idx %d Mode %d BW %d Period %d\n", __FUNCTION__,
+		pSoundInfo->sound_idx, pSoundInfo->sound_mode, pSoundInfo->sound_bw, pSoundInfo->sound_period);
+
+	return ret;
+}
+
+void	beamforming_end_period(PADAPTER adapter)
+{
+	u8						idx = 0;
+	struct beamforming_entry	*pBeamformEntry;
+	struct mlme_priv			*pmlmepriv = &(adapter->mlmepriv);
+	struct beamforming_info	*pBeamInfo = GET_BEAMFORM_INFO(pmlmepriv);
+	struct sounding_info		*pSoundInfo = &(pBeamInfo->sounding_info);
+
+
+	if (pSoundInfo->sound_mode == SOUNDING_FW_VHT_TIMER || pSoundInfo->sound_mode == SOUNDING_FW_HT_TIMER)
+		beamforming_end_fw(adapter);
+}
+
+void	beamforming_notify(PADAPTER adapter)
+{
+	BOOLEAN		bSounding = _FALSE;
+	struct beamforming_info	*pBeamInfo = GET_BEAMFORM_INFO(&(adapter->mlmepriv));
+
+	bSounding = beamfomring_bSounding(pBeamInfo);
+
+	if (pBeamInfo->beamforming_state == BEAMFORMING_STATE_IDLE) {
+		if (bSounding) {
+			if (beamforming_start_period(adapter) == _TRUE)
+				pBeamInfo->beamforming_state = BEAMFORMING_STATE_START;
+		}
+	} else if (pBeamInfo->beamforming_state == BEAMFORMING_STATE_START) {
+		if (bSounding) {
+			if (beamforming_start_period(adapter) == _FALSE)
+				pBeamInfo->beamforming_state = BEAMFORMING_STATE_END;
+		} else {
+			beamforming_end_period(adapter);
+			pBeamInfo->beamforming_state = BEAMFORMING_STATE_END;
+		}
+	} else if (pBeamInfo->beamforming_state == BEAMFORMING_STATE_END) {
+		if (bSounding) {
+			if (beamforming_start_period(adapter) == _TRUE)
+				pBeamInfo->beamforming_state = BEAMFORMING_STATE_START;
+		}
+	} else
+		RTW_INFO("%s BeamformState %d\n", __FUNCTION__, pBeamInfo->beamforming_state);
+
+	RTW_INFO("%s BeamformState %d bSounding %d\n", __FUNCTION__, pBeamInfo->beamforming_state, bSounding);
+}
+
+BOOLEAN	beamforming_init_entry(PADAPTER	adapter, struct sta_info *psta, u8 *idx)
+{
+	struct mlme_priv	*pmlmepriv = &(adapter->mlmepriv);
+	struct ht_priv		*phtpriv = &(pmlmepriv->htpriv);
+#ifdef CONFIG_80211AC_VHT
+	struct vht_priv		*pvhtpriv = &(pmlmepriv->vhtpriv);
+#endif
+	struct mlme_ext_priv	*pmlmeext = &(adapter->mlmeextpriv);
+	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
+	struct beamforming_entry	*pBeamformEntry = NULL;
+	u8	*ra;
+	u16	aid, mac_id;
+	u8	wireless_mode;
+	enum channel_width	bw = CHANNEL_WIDTH_20;
+	BEAMFORMING_CAP	beamform_cap = BEAMFORMING_CAP_NONE;
+
+	/* The current setting does not support Beaforming */
+	if (0 == phtpriv->beamform_cap
+#ifdef CONFIG_80211AC_VHT
+	    && 0 == pvhtpriv->beamform_cap
+#endif
+	   ) {
+		RTW_INFO("The configuration disabled Beamforming! Skip...\n");
+		return _FALSE;
+	}
+
+	aid = psta->cmn.aid;
+	ra = psta->cmn.mac_addr;
+	mac_id = psta->cmn.mac_id;
+	wireless_mode = psta->wireless_mode;
+	bw = psta->cmn.bw_mode;
+
+	if (is_supported_ht(wireless_mode) || is_supported_vht(wireless_mode)) {
+		/* 3 */ /* HT */
+		u8	cur_beamform;
+
+		cur_beamform = psta->htpriv.beamform_cap;
+
+		/* We are Beamformee because the STA is Beamformer */
+		if (TEST_FLAG(cur_beamform, BEAMFORMING_HT_BEAMFORMER_ENABLE))
+			beamform_cap = (BEAMFORMING_CAP)(beamform_cap | BEAMFORMEE_CAP_HT_EXPLICIT);
+
+		/* We are Beamformer because the STA is Beamformee */
+		if (TEST_FLAG(cur_beamform, BEAMFORMING_HT_BEAMFORMEE_ENABLE))
+			beamform_cap = (BEAMFORMING_CAP)(beamform_cap | BEAMFORMER_CAP_HT_EXPLICIT);
+#ifdef CONFIG_80211AC_VHT
+		if (is_supported_vht(wireless_mode)) {
+			/* 3 */ /* VHT */
+			cur_beamform = psta->vhtpriv.beamform_cap;
+
+			/* We are Beamformee because the STA is Beamformer */
+			if (TEST_FLAG(cur_beamform, BEAMFORMING_VHT_BEAMFORMER_ENABLE))
+				beamform_cap = (BEAMFORMING_CAP)(beamform_cap | BEAMFORMEE_CAP_VHT_SU);
+			/* We are Beamformer because the STA is Beamformee */
+			if (TEST_FLAG(cur_beamform, BEAMFORMING_VHT_BEAMFORMEE_ENABLE))
+				beamform_cap = (BEAMFORMING_CAP)(beamform_cap | BEAMFORMER_CAP_VHT_SU);
+		}
+#endif /* CONFIG_80211AC_VHT */
+
+		if (beamform_cap == BEAMFORMING_CAP_NONE)
+			return _FALSE;
+
+		RTW_INFO("Beamforming Config Capability = 0x%02X\n", beamform_cap);
+
+		pBeamformEntry = beamforming_get_entry_by_addr(pmlmepriv, ra, idx);
+		if (pBeamformEntry == NULL) {
+			pBeamformEntry = beamforming_add_entry(adapter, ra, aid, mac_id, bw, beamform_cap, idx);
+			if (pBeamformEntry == NULL)
+				return _FALSE;
+			else
+				pBeamformEntry->beamforming_entry_state = BEAMFORMING_ENTRY_STATE_INITIALIZEING;
+		} else {
+			/* Entry has been created. If entry is initialing or progressing then errors occur. */
+			if (pBeamformEntry->beamforming_entry_state != BEAMFORMING_ENTRY_STATE_INITIALIZED &&
+			    pBeamformEntry->beamforming_entry_state != BEAMFORMING_ENTRY_STATE_PROGRESSED) {
+				RTW_INFO("Error State of Beamforming");
+				return _FALSE;
+			} else
+				pBeamformEntry->beamforming_entry_state = BEAMFORMING_ENTRY_STATE_INITIALIZEING;
+		}
+
+		pBeamformEntry->beamforming_entry_state = BEAMFORMING_ENTRY_STATE_INITIALIZED;
+		psta->cmn.bf_info.p_aid = pBeamformEntry->p_aid;
+		psta->cmn.bf_info.g_id = pBeamformEntry->g_id;
+
+		RTW_INFO("%s Idx %d\n", __FUNCTION__, *idx);
+	} else
+		return _FALSE;
+
+	return _SUCCESS;
+}
+
+void	beamforming_deinit_entry(PADAPTER adapter, u8 *ra)
+{
+	u8	idx = 0;
+	struct mlme_priv *pmlmepriv = &(adapter->mlmepriv);
+
+	if (beamforming_remove_entry(pmlmepriv, ra, &idx) == _TRUE)
+		rtw_hal_set_hwreg(adapter, HW_VAR_SOUNDING_LEAVE, (u8 *)&idx);
+
+	RTW_INFO("%s Idx %d\n", __FUNCTION__, idx);
+}
+
+void	beamforming_reset(PADAPTER adapter)
+{
+	u8	idx = 0;
+	struct mlme_priv			*pmlmepriv = &(adapter->mlmepriv);
+	struct beamforming_info	*pBeamInfo = GET_BEAMFORM_INFO(pmlmepriv);
+
+	for (idx = 0; idx < BEAMFORMING_ENTRY_NUM; idx++) {
+		if (pBeamInfo->beamforming_entry[idx].bUsed == _TRUE) {
+			pBeamInfo->beamforming_entry[idx].bUsed = _FALSE;
+			pBeamInfo->beamforming_entry[idx].beamforming_entry_cap = BEAMFORMING_CAP_NONE;
+			pBeamInfo->beamforming_entry[idx].beamforming_entry_state = BEAMFORMING_ENTRY_STATE_UNINITIALIZE;
+			rtw_hal_set_hwreg(adapter, HW_VAR_SOUNDING_LEAVE, (u8 *)&idx);
+		}
+	}
+
+	RTW_INFO("%s\n", __FUNCTION__);
+}
+
+void beamforming_sounding_fail(PADAPTER Adapter)
+{
+	struct mlme_priv			*pmlmepriv = &(Adapter->mlmepriv);
+	struct beamforming_info	*pBeamInfo = GET_BEAMFORM_INFO(pmlmepriv);
+	struct beamforming_entry	*pEntry = &(pBeamInfo->beamforming_entry[pBeamInfo->beamforming_cur_idx]);
+
+	pEntry->bSound = _FALSE;
+	rtw_hal_set_hwreg(Adapter, HW_VAR_SOUNDING_FW_NDPA, (u8 *)&pBeamInfo->beamforming_cur_idx);
+	beamforming_deinit_entry(Adapter, pEntry->mac_addr);
+}
+
+void	beamforming_check_sounding_success(PADAPTER Adapter, BOOLEAN status)
+{
+	struct mlme_priv			*pmlmepriv = &(Adapter->mlmepriv);
+	struct beamforming_info	*pBeamInfo = GET_BEAMFORM_INFO(pmlmepriv);
+	struct beamforming_entry	*pEntry = &(pBeamInfo->beamforming_entry[pBeamInfo->beamforming_cur_idx]);
+
+	if (status == 1)
+		pEntry->LogStatusFailCnt = 0;
+	else {
+		pEntry->LogStatusFailCnt++;
+		RTW_INFO("%s LogStatusFailCnt %d\n", __FUNCTION__, pEntry->LogStatusFailCnt);
+	}
+	if (pEntry->LogStatusFailCnt > 20) {
+		RTW_INFO("%s LogStatusFailCnt > 20, Stop SOUNDING\n", __FUNCTION__);
+		/* pEntry->bSound = _FALSE; */
+		/* rtw_hal_set_hwreg(Adapter, HW_VAR_SOUNDING_FW_NDPA, (u8 *)&pBeamInfo->beamforming_cur_idx); */
+		/* beamforming_deinit_entry(Adapter, pEntry->mac_addr); */
+		beamforming_wk_cmd(Adapter, BEAMFORMING_CTRL_SOUNDING_FAIL, NULL, 0, 1);
+	}
+}
+
+void	beamforming_enter(PADAPTER adapter, PVOID psta)
+{
+	u8	idx = 0xff;
+
+	if (beamforming_init_entry(adapter, (struct sta_info *)psta, &idx))
+		rtw_hal_set_hwreg(adapter, HW_VAR_SOUNDING_ENTER, (u8 *)&idx);
+
+	/* RTW_INFO("%s Idx %d\n", __FUNCTION__, idx); */
+}
+
+void	beamforming_leave(PADAPTER adapter, u8 *ra)
+{
+	if (ra == NULL)
+		beamforming_reset(adapter);
+	else
+		beamforming_deinit_entry(adapter, ra);
+
+	beamforming_notify(adapter);
+}
+
+BEAMFORMING_CAP beamforming_get_beamform_cap(struct beamforming_info	*pBeamInfo)
+{
+	u8	i;
+	BOOLEAN				bSelfBeamformer = _FALSE;
+	BOOLEAN				bSelfBeamformee = _FALSE;
+	struct beamforming_entry	beamforming_entry;
+	BEAMFORMING_CAP		beamform_cap = BEAMFORMING_CAP_NONE;
+
+	for (i = 0; i < BEAMFORMING_ENTRY_NUM; i++) {
+		beamforming_entry = pBeamInfo->beamforming_entry[i];
+
+		if (beamforming_entry.bUsed) {
+			if ((beamforming_entry.beamforming_entry_cap & BEAMFORMEE_CAP_VHT_SU) ||
+			    (beamforming_entry.beamforming_entry_cap & BEAMFORMEE_CAP_HT_EXPLICIT))
+				bSelfBeamformee = _TRUE;
+			if ((beamforming_entry.beamforming_entry_cap & BEAMFORMER_CAP_VHT_SU) ||
+			    (beamforming_entry.beamforming_entry_cap & BEAMFORMER_CAP_HT_EXPLICIT))
+				bSelfBeamformer = _TRUE;
+		}
+
+		if (bSelfBeamformer && bSelfBeamformee)
+			i = BEAMFORMING_ENTRY_NUM;
+	}
+
+	if (bSelfBeamformer)
+		beamform_cap |= BEAMFORMER_CAP;
+	if (bSelfBeamformee)
+		beamform_cap |= BEAMFORMEE_CAP;
+
+	return beamform_cap;
+}
+
+void	beamforming_watchdog(PADAPTER Adapter)
+{
+	struct beamforming_info	*pBeamInfo = GET_BEAMFORM_INFO((&(Adapter->mlmepriv)));
+
+	if (pBeamInfo->beamforming_state != BEAMFORMING_STATE_START)
+		return;
+
+	beamforming_dym_period(Adapter);
+	beamforming_dym_ndpa_rate(Adapter);
+}
+#endif/* #if (BEAMFORMING_SUPPORT ==0) - for diver defined beamforming*/
+
+u32	rtw_beamforming_get_report_frame(PADAPTER	 Adapter, union recv_frame *precv_frame)
+{
+	u32	ret = _SUCCESS;
+#if (BEAMFORMING_SUPPORT == 1)
+	PHAL_DATA_TYPE	pHalData = GET_HAL_DATA(Adapter);
+	struct dm_struct		*pDM_Odm = &(pHalData->odmpriv);
+
+	ret = beamforming_get_report_frame(pDM_Odm, precv_frame);
+
+#else /*(BEAMFORMING_SUPPORT == 0)- for drv beamfoming*/
+	struct beamforming_entry	*pBeamformEntry = NULL;
+	struct mlme_priv			*pmlmepriv = &(Adapter->mlmepriv);
+	u8	*pframe = precv_frame->u.hdr.rx_data;
+	u32	frame_len = precv_frame->u.hdr.len;
+	u8	*ta;
+	u8	idx, offset;
+
+	/*RTW_INFO("rtw_beamforming_get_report_frame\n");*/
+
+	/*Memory comparison to see if CSI report is the same with previous one*/
+	ta = get_addr2_ptr(pframe);
+	pBeamformEntry = beamforming_get_entry_by_addr(pmlmepriv, ta, &idx);
+	if (pBeamformEntry->beamforming_entry_cap & BEAMFORMER_CAP_VHT_SU)
+		offset = 31;	/*24+(1+1+3)+2  MAC header+(Category+ActionCode+MIMOControlField)+SNR(Nc=2)*/
+	else if (pBeamformEntry->beamforming_entry_cap & BEAMFORMER_CAP_HT_EXPLICIT)
+		offset = 34;	/*24+(1+1+6)+2  MAC header+(Category+ActionCode+MIMOControlField)+SNR(Nc=2)*/
+	else
+		return ret;
+
+	/*RTW_INFO("%s MacId %d offset=%d\n", __FUNCTION__, pBeamformEntry->mac_id, offset);*/
+
+	if (_rtw_memcmp(pBeamformEntry->PreCsiReport + offset, pframe + offset, frame_len - offset) == _FALSE)
+		pBeamformEntry->DefaultCsiCnt = 0;
+	else
+		pBeamformEntry->DefaultCsiCnt++;
+
+	_rtw_memcpy(&pBeamformEntry->PreCsiReport, pframe, frame_len);
+
+	pBeamformEntry->bDefaultCSI = _FALSE;
+
+	if (pBeamformEntry->DefaultCsiCnt > 20)
+		pBeamformEntry->bDefaultCSI = _TRUE;
+	else
+		pBeamformEntry->bDefaultCSI = _FALSE;
+#endif
+	return ret;
+}
+
+void	rtw_beamforming_get_ndpa_frame(PADAPTER	 Adapter, union recv_frame *precv_frame)
+{
+#if (BEAMFORMING_SUPPORT == 1)
+	PHAL_DATA_TYPE	pHalData = GET_HAL_DATA(Adapter);
+	struct dm_struct		*pDM_Odm = &(pHalData->odmpriv);
+
+	beamforming_get_ndpa_frame(pDM_Odm, precv_frame);
+
+#else /*(BEAMFORMING_SUPPORT == 0)- for drv beamfoming*/
+	u8	*ta;
+	u8	idx, Sequence;
+	u8	*pframe = precv_frame->u.hdr.rx_data;
+	struct mlme_priv			*pmlmepriv = &(Adapter->mlmepriv);
+	struct beamforming_entry	*pBeamformEntry = NULL;
+
+	/*RTW_INFO("rtw_beamforming_get_ndpa_frame\n");*/
+
+	if (IS_HARDWARE_TYPE_8812(Adapter) == _FALSE)
+		return;
+	else if (get_frame_sub_type(pframe) != WIFI_NDPA)
+		return;
+
+	ta = get_addr2_ptr(pframe);
+	/*Remove signaling TA. */
+	ta[0] = ta[0] & 0xFE;
+
+	pBeamformEntry = beamforming_get_entry_by_addr(pmlmepriv, ta, &idx);
+
+	if (pBeamformEntry == NULL)
+		return;
+	else if (!(pBeamformEntry->beamforming_entry_cap & BEAMFORMEE_CAP_VHT_SU))
+		return;
+	/*LogSuccess: As long as 8812A receive NDPA and feedback CSI succeed once, clock reset is NO LONGER needed !2015-04-10, Jeffery*/
+	/*ClockResetTimes: While BFer entry always doesn't receive our CSI, clock will reset again and again.So ClockResetTimes is limited to 5 times.2015-04-13, Jeffery*/
+	else if ((pBeamformEntry->LogSuccess == 1) || (pBeamformEntry->ClockResetTimes == 5)) {
+		RTW_INFO("[%s] LogSeq=%d, PreLogSeq=%d\n", __func__, pBeamformEntry->LogSeq, pBeamformEntry->PreLogSeq);
+		return;
+	}
+
+	Sequence = (pframe[16]) >> 2;
+	RTW_INFO("[%s] Start, Sequence=%d, LogSeq=%d, PreLogSeq=%d, LogRetryCnt=%d, ClockResetTimes=%d, LogSuccess=%d\n",
+		__func__, Sequence, pBeamformEntry->LogSeq, pBeamformEntry->PreLogSeq, pBeamformEntry->LogRetryCnt, pBeamformEntry->ClockResetTimes, pBeamformEntry->LogSuccess);
+
+	if ((pBeamformEntry->LogSeq != 0) && (pBeamformEntry->PreLogSeq != 0)) {
+		/*Success condition*/
+		if ((pBeamformEntry->LogSeq != Sequence) && (pBeamformEntry->PreLogSeq != pBeamformEntry->LogSeq)) {
+			/* break option for clcok reset, 2015-03-30, Jeffery */
+			pBeamformEntry->LogRetryCnt = 0;
+			/*As long as 8812A receive NDPA and feedback CSI succeed once, clock reset is no longer needed.*/
+			/*That is, LogSuccess is NOT needed to be reset to zero, 2015-04-13, Jeffery*/
+			pBeamformEntry->LogSuccess = 1;
+
+		} else {/*Fail condition*/
+
+			if (pBeamformEntry->LogRetryCnt == 5) {
+				pBeamformEntry->ClockResetTimes++;
+				pBeamformEntry->LogRetryCnt = 0;
+
+				RTW_INFO("[%s] Clock Reset!!! ClockResetTimes=%d\n",  __func__, pBeamformEntry->ClockResetTimes);
+				beamforming_wk_cmd(Adapter, BEAMFORMING_CTRL_SOUNDING_CLK, NULL, 0, 1);
+
+			} else
+				pBeamformEntry->LogRetryCnt++;
+		}
+	}
+
+	/*Update LogSeq & PreLogSeq*/
+	pBeamformEntry->PreLogSeq = pBeamformEntry->LogSeq;
+	pBeamformEntry->LogSeq = Sequence;
+
+#endif
+
+}
+
+
+
+
+void	beamforming_wk_hdl(_adapter *padapter, u8 type, u8 *pbuf)
+{
+	PHAL_DATA_TYPE	pHalData = GET_HAL_DATA(padapter);
+	struct dm_struct		*pDM_Odm = &(pHalData->odmpriv);
+
+#if (BEAMFORMING_SUPPORT == 1) /*(BEAMFORMING_SUPPORT == 1)- for PHYDM beamfoming*/
+	switch (type) {
+	case BEAMFORMING_CTRL_ENTER: {
+		struct sta_info	*psta = (PVOID)pbuf;
+		u16			staIdx = psta->cmn.mac_id;
+
+		beamforming_enter(pDM_Odm, staIdx);
+		break;
+	}
+	case BEAMFORMING_CTRL_LEAVE:
+		beamforming_leave(pDM_Odm, pbuf);
+		break;
+	default:
+		break;
+
+	}
+#else /*(BEAMFORMING_SUPPORT == 0)- for drv beamfoming*/
+	switch (type) {
+	case BEAMFORMING_CTRL_ENTER:
+		beamforming_enter(padapter, (PVOID)pbuf);
+		break;
+
+	case BEAMFORMING_CTRL_LEAVE:
+		beamforming_leave(padapter, pbuf);
+		break;
+
+	case BEAMFORMING_CTRL_SOUNDING_FAIL:
+		beamforming_sounding_fail(padapter);
+		break;
+
+	case BEAMFORMING_CTRL_SOUNDING_CLK:
+		rtw_hal_set_hwreg(padapter, HW_VAR_SOUNDING_CLK, NULL);
+		break;
+
+	default:
+		break;
+	}
+#endif
+}
+
+u8	beamforming_wk_cmd(_adapter *padapter, s32 type, u8 *pbuf, s32 size, u8 enqueue)
+{
+	struct cmd_obj	*ph2c;
+	struct drvextra_cmd_parm	*pdrvextra_cmd_parm;
+	struct cmd_priv	*pcmdpriv = &padapter->cmdpriv;
+	struct mlme_ext_priv	*pmlmeext = &padapter->mlmeextpriv;
+	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
+	u8	res = _SUCCESS;
+
+	/*20170214 ad_hoc mode and mp_mode not support BF*/
+	if ((padapter->registrypriv.mp_mode == 1)
+		|| (pmlmeinfo->state == WIFI_FW_ADHOC_STATE))
+		return res;
+
+	if (enqueue) {
+		u8	*wk_buf;
+
+		ph2c = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj));
+		if (ph2c == NULL) {
+			res = _FAIL;
+			goto exit;
+		}
+
+		pdrvextra_cmd_parm = (struct drvextra_cmd_parm *)rtw_zmalloc(sizeof(struct drvextra_cmd_parm));
+		if (pdrvextra_cmd_parm == NULL) {
+			rtw_mfree((unsigned char *)ph2c, sizeof(struct cmd_obj));
+			res = _FAIL;
+			goto exit;
+		}
+
+		if (pbuf != NULL) {
+			wk_buf = rtw_zmalloc(size);
+			if (wk_buf == NULL) {
+				rtw_mfree((u8 *)ph2c, sizeof(struct cmd_obj));
+				rtw_mfree((u8 *)pdrvextra_cmd_parm, sizeof(struct drvextra_cmd_parm));
+				res = _FAIL;
+				goto exit;
+			}
+
+			_rtw_memcpy(wk_buf, pbuf, size);
+		} else {
+			wk_buf = NULL;
+			size = 0;
+		}
+
+		pdrvextra_cmd_parm->ec_id = BEAMFORMING_WK_CID;
+		pdrvextra_cmd_parm->type = type;
+		pdrvextra_cmd_parm->size = size;
+		pdrvextra_cmd_parm->pbuf = wk_buf;
+
+		init_h2fwcmd_w_parm_no_rsp(ph2c, pdrvextra_cmd_parm, GEN_CMD_CODE(_Set_Drv_Extra));
+
+		res = rtw_enqueue_cmd(pcmdpriv, ph2c);
+	} else
+		beamforming_wk_hdl(padapter, type, pbuf);
+
+exit:
+
+
+	return res;
+}
+
+void update_attrib_txbf_info(_adapter *padapter, struct pkt_attrib *pattrib, struct sta_info *psta)
+{
+	if (psta) {
+		pattrib->txbf_g_id = psta->cmn.bf_info.g_id;
+		pattrib->txbf_p_aid = psta->cmn.bf_info.p_aid;
+	}
+}
+#endif /* !RTW_BEAMFORMING_VERSION_2 */
+
+#endif /* CONFIG_BEAMFORMING */
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/core/rtw_br_ext.c linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/core/rtw_br_ext.c
--- linux-5.6.3/3rdparty/rtl8821ce/core/rtw_br_ext.c	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/core/rtw_br_ext.c	2020-04-10 16:35:06.771657967 +0300
@@ -0,0 +1,1581 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#define _RTW_BR_EXT_C_
+
+#ifdef __KERNEL__
+	#include <linux/if_arp.h>
+	#include <net/ip.h>
+	#include <net/ipx.h>
+	#include <linux/atalk.h>
+	#include <linux/udp.h>
+	#include <linux/if_pppox.h>
+#endif
+
+#if 1	/* rtw_wifi_driver */
+	#include <drv_types.h>
+#else	/* rtw_wifi_driver */
+	#include "./8192cd_cfg.h"
+
+	#ifndef __KERNEL__
+		#include "./sys-support.h"
+	#endif
+
+	#include "./8192cd.h"
+	#include "./8192cd_headers.h"
+	#include "./8192cd_br_ext.h"
+	#include "./8192cd_debug.h"
+#endif /* rtw_wifi_driver */
+
+#ifdef CL_IPV6_PASS
+	#ifdef __KERNEL__
+		#include <linux/ipv6.h>
+		#include <linux/icmpv6.h>
+		#include <net/ndisc.h>
+		#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 24))
+			#include <net/ip6_checksum.h>
+		#else
+			#include <net/checksum.h>
+		#endif
+	#endif
+#endif
+
+#ifdef CONFIG_BR_EXT
+
+/* #define BR_EXT_DEBUG */
+
+#define NAT25_IPV4		01
+#define NAT25_IPV6		02
+#define NAT25_IPX		03
+#define NAT25_APPLE		04
+#define NAT25_PPPOE		05
+
+#define RTL_RELAY_TAG_LEN (ETH_ALEN)
+#define TAG_HDR_LEN		4
+
+#define MAGIC_CODE		0x8186
+#define MAGIC_CODE_LEN	2
+#define WAIT_TIME_PPPOE	5	/* waiting time for pppoe server in sec */
+
+/*-----------------------------------------------------------------
+  How database records network address:
+           0    1    2    3    4    5    6    7    8    9   10
+        |----|----|----|----|----|----|----|----|----|----|----|
+  IPv4  |type|                             |      IP addr      |
+  IPX   |type|      Net addr     |          Node addr          |
+  IPX   |type|      Net addr     |Sckt addr|
+  Apple |type| Network |node|
+  PPPoE |type|   SID   |           AC MAC            |
+-----------------------------------------------------------------*/
+
+
+/* Find a tag in pppoe frame and return the pointer */
+static __inline__ unsigned char *__nat25_find_pppoe_tag(struct pppoe_hdr *ph, unsigned short type)
+{
+	unsigned char *cur_ptr, *start_ptr;
+	unsigned short tagLen, tagType;
+
+	start_ptr = cur_ptr = (unsigned char *)ph->tag;
+	while ((cur_ptr - start_ptr) < ntohs(ph->length)) {
+		/* prevent un-alignment access */
+		tagType = (unsigned short)((cur_ptr[0] << 8) + cur_ptr[1]);
+		tagLen  = (unsigned short)((cur_ptr[2] << 8) + cur_ptr[3]);
+		if (tagType == type)
+			return cur_ptr;
+		cur_ptr = cur_ptr + TAG_HDR_LEN + tagLen;
+	}
+	return 0;
+}
+
+
+static __inline__ int __nat25_add_pppoe_tag(struct sk_buff *skb, struct pppoe_tag *tag)
+{
+	struct pppoe_hdr *ph = (struct pppoe_hdr *)(skb->data + ETH_HLEN);
+	int data_len;
+
+	data_len = tag->tag_len + TAG_HDR_LEN;
+	if (skb_tailroom(skb) < data_len) {
+		_DEBUG_ERR("skb_tailroom() failed in add SID tag!\n");
+		return -1;
+	}
+
+	skb_put(skb, data_len);
+	/* have a room for new tag */
+	memmove(((unsigned char *)ph->tag + data_len), (unsigned char *)ph->tag, ntohs(ph->length));
+	ph->length = htons(ntohs(ph->length) + data_len);
+	memcpy((unsigned char *)ph->tag, tag, data_len);
+	return data_len;
+}
+
+static int skb_pull_and_merge(struct sk_buff *skb, unsigned char *src, int len)
+{
+	int tail_len;
+	unsigned long end, tail;
+
+	if ((src + len) > skb_tail_pointer(skb) || skb->len < len)
+		return -1;
+
+	tail = (unsigned long)skb_tail_pointer(skb);
+	end = (unsigned long)src + len;
+	if (tail < end)
+		return -1;
+
+	tail_len = (int)(tail - end);
+	if (tail_len > 0)
+		memmove(src, src + len, tail_len);
+
+	skb_trim(skb, skb->len - len);
+	return 0;
+}
+
+static __inline__ unsigned long __nat25_timeout(_adapter *priv)
+{
+	unsigned long timeout;
+
+	timeout = jiffies - NAT25_AGEING_TIME * HZ;
+
+	return timeout;
+}
+
+
+static __inline__ int  __nat25_has_expired(_adapter *priv,
+		struct nat25_network_db_entry *fdb)
+{
+	if (time_before_eq(fdb->ageing_timer, __nat25_timeout(priv)))
+		return 1;
+
+	return 0;
+}
+
+
+static __inline__ void __nat25_generate_ipv4_network_addr(unsigned char *networkAddr,
+		unsigned int *ipAddr)
+{
+	memset(networkAddr, 0, MAX_NETWORK_ADDR_LEN);
+
+	networkAddr[0] = NAT25_IPV4;
+	memcpy(networkAddr + 7, (unsigned char *)ipAddr, 4);
+}
+
+
+static __inline__ void __nat25_generate_ipx_network_addr_with_node(unsigned char *networkAddr,
+		unsigned int *ipxNetAddr, unsigned char *ipxNodeAddr)
+{
+	memset(networkAddr, 0, MAX_NETWORK_ADDR_LEN);
+
+	networkAddr[0] = NAT25_IPX;
+	memcpy(networkAddr + 1, (unsigned char *)ipxNetAddr, 4);
+	memcpy(networkAddr + 5, ipxNodeAddr, 6);
+}
+
+
+static __inline__ void __nat25_generate_ipx_network_addr_with_socket(unsigned char *networkAddr,
+		unsigned int *ipxNetAddr, unsigned short *ipxSocketAddr)
+{
+	memset(networkAddr, 0, MAX_NETWORK_ADDR_LEN);
+
+	networkAddr[0] = NAT25_IPX;
+	memcpy(networkAddr + 1, (unsigned char *)ipxNetAddr, 4);
+	memcpy(networkAddr + 5, (unsigned char *)ipxSocketAddr, 2);
+}
+
+
+static __inline__ void __nat25_generate_apple_network_addr(unsigned char *networkAddr,
+		unsigned short *network, unsigned char *node)
+{
+	memset(networkAddr, 0, MAX_NETWORK_ADDR_LEN);
+
+	networkAddr[0] = NAT25_APPLE;
+	memcpy(networkAddr + 1, (unsigned char *)network, 2);
+	networkAddr[3] = *node;
+}
+
+
+static __inline__ void __nat25_generate_pppoe_network_addr(unsigned char *networkAddr,
+		unsigned char *ac_mac, unsigned short *sid)
+{
+	memset(networkAddr, 0, MAX_NETWORK_ADDR_LEN);
+
+	networkAddr[0] = NAT25_PPPOE;
+	memcpy(networkAddr + 1, (unsigned char *)sid, 2);
+	memcpy(networkAddr + 3, (unsigned char *)ac_mac, 6);
+}
+
+
+#ifdef CL_IPV6_PASS
+static  void __nat25_generate_ipv6_network_addr(unsigned char *networkAddr,
+		unsigned int *ipAddr)
+{
+	memset(networkAddr, 0, MAX_NETWORK_ADDR_LEN);
+
+	networkAddr[0] = NAT25_IPV6;
+	memcpy(networkAddr + 1, (unsigned char *)ipAddr, 16);
+}
+
+
+static unsigned char *scan_tlv(unsigned char *data, int len, unsigned char tag, unsigned char len8b)
+{
+	while (len > 0) {
+		if (*data == tag && *(data + 1) == len8b && len >= len8b * 8)
+			return data + 2;
+
+		len -= (*(data + 1)) * 8;
+		data += (*(data + 1)) * 8;
+	}
+	return NULL;
+}
+
+
+static int update_nd_link_layer_addr(unsigned char *data, int len, unsigned char *replace_mac)
+{
+	struct icmp6hdr *icmphdr = (struct icmp6hdr *)data;
+	unsigned char *mac;
+
+	if (icmphdr->icmp6_type == NDISC_ROUTER_SOLICITATION) {
+		if (len >= 8) {
+			mac = scan_tlv(&data[8], len - 8, 1, 1);
+			if (mac) {
+				RTW_INFO("Router Solicitation, replace MAC From: %02x:%02x:%02x:%02x:%02x:%02x, To: %02x:%02x:%02x:%02x:%02x:%02x\n",
+					mac[0], mac[1], mac[2], mac[3], mac[4], mac[5],
+					replace_mac[0], replace_mac[1], replace_mac[2], replace_mac[3], replace_mac[4], replace_mac[5]);
+				memcpy(mac, replace_mac, 6);
+				return 1;
+			}
+		}
+	} else if (icmphdr->icmp6_type == NDISC_ROUTER_ADVERTISEMENT) {
+		if (len >= 16) {
+			mac = scan_tlv(&data[16], len - 16, 1, 1);
+			if (mac) {
+				RTW_INFO("Router Advertisement, replace MAC From: %02x:%02x:%02x:%02x:%02x:%02x, To: %02x:%02x:%02x:%02x:%02x:%02x\n",
+					mac[0], mac[1], mac[2], mac[3], mac[4], mac[5],
+					replace_mac[0], replace_mac[1], replace_mac[2], replace_mac[3], replace_mac[4], replace_mac[5]);
+				memcpy(mac, replace_mac, 6);
+				return 1;
+			}
+		}
+	} else if (icmphdr->icmp6_type == NDISC_NEIGHBOUR_SOLICITATION) {
+		if (len >= 24) {
+			mac = scan_tlv(&data[24], len - 24, 1, 1);
+			if (mac) {
+				RTW_INFO("Neighbor Solicitation, replace MAC From: %02x:%02x:%02x:%02x:%02x:%02x, To: %02x:%02x:%02x:%02x:%02x:%02x\n",
+					mac[0], mac[1], mac[2], mac[3], mac[4], mac[5],
+					replace_mac[0], replace_mac[1], replace_mac[2], replace_mac[3], replace_mac[4], replace_mac[5]);
+				memcpy(mac, replace_mac, 6);
+				return 1;
+			}
+		}
+	} else if (icmphdr->icmp6_type == NDISC_NEIGHBOUR_ADVERTISEMENT) {
+		if (len >= 24) {
+			mac = scan_tlv(&data[24], len - 24, 2, 1);
+			if (mac) {
+				RTW_INFO("Neighbor Advertisement, replace MAC From: %02x:%02x:%02x:%02x:%02x:%02x, To: %02x:%02x:%02x:%02x:%02x:%02x\n",
+					mac[0], mac[1], mac[2], mac[3], mac[4], mac[5],
+					replace_mac[0], replace_mac[1], replace_mac[2], replace_mac[3], replace_mac[4], replace_mac[5]);
+				memcpy(mac, replace_mac, 6);
+				return 1;
+			}
+		}
+	} else if (icmphdr->icmp6_type == NDISC_REDIRECT) {
+		if (len >= 40) {
+			mac = scan_tlv(&data[40], len - 40, 2, 1);
+			if (mac) {
+				RTW_INFO("Redirect,  replace MAC From: %02x:%02x:%02x:%02x:%02x:%02x, To: %02x:%02x:%02x:%02x:%02x:%02x\n",
+					mac[0], mac[1], mac[2], mac[3], mac[4], mac[5],
+					replace_mac[0], replace_mac[1], replace_mac[2], replace_mac[3], replace_mac[4], replace_mac[5]);
+				memcpy(mac, replace_mac, 6);
+				return 1;
+			}
+		}
+	}
+	return 0;
+}
+
+#ifdef SUPPORT_RX_UNI2MCAST
+static void convert_ipv6_mac_to_mc(struct sk_buff *skb)
+{
+	struct ipv6hdr *iph = (struct ipv6hdr *)(skb->data + ETH_HLEN);
+	unsigned char *dst_mac = skb->data;
+
+	/* dst_mac[0] = 0xff; */
+	/* dst_mac[1] = 0xff; */
+	/*modified by qinjunjie,ipv6 multicast address ix 0x33-33-xx-xx-xx-xx*/
+	dst_mac[0] = 0x33;
+	dst_mac[1] = 0x33;
+	memcpy(&dst_mac[2], &iph->daddr.s6_addr32[3], 4);
+#if defined(__LINUX_2_6__)
+	/*modified by qinjunjie,warning:should not remove next line*/
+	skb->pkt_type = PACKET_MULTICAST;
+#endif
+}
+#endif /* CL_IPV6_PASS */
+#endif /* SUPPORT_RX_UNI2MCAST */
+
+
+static __inline__ int __nat25_network_hash(unsigned char *networkAddr)
+{
+	if (networkAddr[0] == NAT25_IPV4) {
+		unsigned long x;
+
+		x = networkAddr[7] ^ networkAddr[8] ^ networkAddr[9] ^ networkAddr[10];
+
+		return x & (NAT25_HASH_SIZE - 1);
+	} else if (networkAddr[0] == NAT25_IPX) {
+		unsigned long x;
+
+		x = networkAddr[1] ^ networkAddr[2] ^ networkAddr[3] ^ networkAddr[4] ^ networkAddr[5] ^
+		    networkAddr[6] ^ networkAddr[7] ^ networkAddr[8] ^ networkAddr[9] ^ networkAddr[10];
+
+		return x & (NAT25_HASH_SIZE - 1);
+	} else if (networkAddr[0] == NAT25_APPLE) {
+		unsigned long x;
+
+		x = networkAddr[1] ^ networkAddr[2] ^ networkAddr[3];
+
+		return x & (NAT25_HASH_SIZE - 1);
+	} else if (networkAddr[0] == NAT25_PPPOE) {
+		unsigned long x;
+
+		x = networkAddr[0] ^ networkAddr[1] ^ networkAddr[2] ^ networkAddr[3] ^ networkAddr[4] ^ networkAddr[5] ^ networkAddr[6] ^ networkAddr[7] ^ networkAddr[8];
+
+		return x & (NAT25_HASH_SIZE - 1);
+	}
+#ifdef CL_IPV6_PASS
+	else if (networkAddr[0] == NAT25_IPV6) {
+		unsigned long x;
+
+		x = networkAddr[1] ^ networkAddr[2] ^ networkAddr[3] ^ networkAddr[4] ^ networkAddr[5] ^
+		    networkAddr[6] ^ networkAddr[7] ^ networkAddr[8] ^ networkAddr[9] ^ networkAddr[10] ^
+		    networkAddr[11] ^ networkAddr[12] ^ networkAddr[13] ^ networkAddr[14] ^ networkAddr[15] ^
+		    networkAddr[16];
+
+		return x & (NAT25_HASH_SIZE - 1);
+	}
+#endif
+	else {
+		unsigned long x = 0;
+		int i;
+
+		for (i = 0; i < MAX_NETWORK_ADDR_LEN; i++)
+			x ^= networkAddr[i];
+
+		return x & (NAT25_HASH_SIZE - 1);
+	}
+}
+
+
+static __inline__ void __network_hash_link(_adapter *priv,
+		struct nat25_network_db_entry *ent, int hash)
+{
+	/* Caller must _enter_critical_bh already! */
+	/* _irqL irqL; */
+	/* _enter_critical_bh(&priv->br_ext_lock, &irqL); */
+
+	ent->next_hash = priv->nethash[hash];
+	if (ent->next_hash != NULL)
+		ent->next_hash->pprev_hash = &ent->next_hash;
+	priv->nethash[hash] = ent;
+	ent->pprev_hash = &priv->nethash[hash];
+
+	/* _exit_critical_bh(&priv->br_ext_lock, &irqL); */
+}
+
+
+static __inline__ void __network_hash_unlink(struct nat25_network_db_entry *ent)
+{
+	/* Caller must _enter_critical_bh already! */
+	/* _irqL irqL; */
+	/* _enter_critical_bh(&priv->br_ext_lock, &irqL); */
+
+	*(ent->pprev_hash) = ent->next_hash;
+	if (ent->next_hash != NULL)
+		ent->next_hash->pprev_hash = ent->pprev_hash;
+	ent->next_hash = NULL;
+	ent->pprev_hash = NULL;
+
+	/* _exit_critical_bh(&priv->br_ext_lock, &irqL); */
+}
+
+
+static int __nat25_db_network_lookup_and_replace(_adapter *priv,
+		struct sk_buff *skb, unsigned char *networkAddr)
+{
+	struct nat25_network_db_entry *db;
+	_irqL irqL;
+	_enter_critical_bh(&priv->br_ext_lock, &irqL);
+
+	db = priv->nethash[__nat25_network_hash(networkAddr)];
+	while (db != NULL) {
+		if (!memcmp(db->networkAddr, networkAddr, MAX_NETWORK_ADDR_LEN)) {
+			if (!__nat25_has_expired(priv, db)) {
+				/* replace the destination mac address */
+				memcpy(skb->data, db->macAddr, ETH_ALEN);
+				atomic_inc(&db->use_count);
+
+#ifdef CL_IPV6_PASS
+				RTW_INFO("NAT25: Lookup M:%02x%02x%02x%02x%02x%02x N:%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x"
+					 "%02x%02x%02x%02x%02x%02x\n",
+					 db->macAddr[0],
+					 db->macAddr[1],
+					 db->macAddr[2],
+					 db->macAddr[3],
+					 db->macAddr[4],
+					 db->macAddr[5],
+					 db->networkAddr[0],
+					 db->networkAddr[1],
+					 db->networkAddr[2],
+					 db->networkAddr[3],
+					 db->networkAddr[4],
+					 db->networkAddr[5],
+					 db->networkAddr[6],
+					 db->networkAddr[7],
+					 db->networkAddr[8],
+					 db->networkAddr[9],
+					 db->networkAddr[10],
+					 db->networkAddr[11],
+					 db->networkAddr[12],
+					 db->networkAddr[13],
+					 db->networkAddr[14],
+					 db->networkAddr[15],
+					 db->networkAddr[16]);
+#else
+				RTW_INFO("NAT25: Lookup M:%02x%02x%02x%02x%02x%02x N:%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x\n",
+					 db->macAddr[0],
+					 db->macAddr[1],
+					 db->macAddr[2],
+					 db->macAddr[3],
+					 db->macAddr[4],
+					 db->macAddr[5],
+					 db->networkAddr[0],
+					 db->networkAddr[1],
+					 db->networkAddr[2],
+					 db->networkAddr[3],
+					 db->networkAddr[4],
+					 db->networkAddr[5],
+					 db->networkAddr[6],
+					 db->networkAddr[7],
+					 db->networkAddr[8],
+					 db->networkAddr[9],
+					 db->networkAddr[10]);
+#endif
+			}
+			_exit_critical_bh(&priv->br_ext_lock, &irqL);
+			return 1;
+		}
+
+		db = db->next_hash;
+	}
+
+	_exit_critical_bh(&priv->br_ext_lock, &irqL);
+	return 0;
+}
+
+
+static void __nat25_db_network_insert(_adapter *priv,
+		      unsigned char *macAddr, unsigned char *networkAddr)
+{
+	struct nat25_network_db_entry *db;
+	int hash;
+	_irqL irqL;
+	_enter_critical_bh(&priv->br_ext_lock, &irqL);
+
+	hash = __nat25_network_hash(networkAddr);
+	db = priv->nethash[hash];
+	while (db != NULL) {
+		if (!memcmp(db->networkAddr, networkAddr, MAX_NETWORK_ADDR_LEN)) {
+			memcpy(db->macAddr, macAddr, ETH_ALEN);
+			db->ageing_timer = jiffies;
+			_exit_critical_bh(&priv->br_ext_lock, &irqL);
+			return;
+		}
+
+		db = db->next_hash;
+	}
+
+	db = (struct nat25_network_db_entry *) rtw_malloc(sizeof(*db));
+	if (db == NULL) {
+		_exit_critical_bh(&priv->br_ext_lock, &irqL);
+		return;
+	}
+
+	memcpy(db->networkAddr, networkAddr, MAX_NETWORK_ADDR_LEN);
+	memcpy(db->macAddr, macAddr, ETH_ALEN);
+	atomic_set(&db->use_count, 1);
+	db->ageing_timer = jiffies;
+
+	__network_hash_link(priv, db, hash);
+
+	_exit_critical_bh(&priv->br_ext_lock, &irqL);
+}
+
+
+static void __nat25_db_print(_adapter *priv)
+{
+	_irqL irqL;
+	_enter_critical_bh(&priv->br_ext_lock, &irqL);
+
+#ifdef BR_EXT_DEBUG
+	static int counter = 0;
+	int i, j;
+	struct nat25_network_db_entry *db;
+
+	counter++;
+	if ((counter % 16) != 0)
+		return;
+
+	for (i = 0, j = 0; i < NAT25_HASH_SIZE; i++) {
+		db = priv->nethash[i];
+
+		while (db != NULL) {
+#ifdef CL_IPV6_PASS
+			panic_printk("NAT25: DB(%d) H(%02d) C(%d) M:%02x%02x%02x%02x%02x%02x N:%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x"
+				     "%02x%02x%02x%02x%02x%02x\n",
+				     j,
+				     i,
+				     atomic_read(&db->use_count),
+				     db->macAddr[0],
+				     db->macAddr[1],
+				     db->macAddr[2],
+				     db->macAddr[3],
+				     db->macAddr[4],
+				     db->macAddr[5],
+				     db->networkAddr[0],
+				     db->networkAddr[1],
+				     db->networkAddr[2],
+				     db->networkAddr[3],
+				     db->networkAddr[4],
+				     db->networkAddr[5],
+				     db->networkAddr[6],
+				     db->networkAddr[7],
+				     db->networkAddr[8],
+				     db->networkAddr[9],
+				     db->networkAddr[10],
+				     db->networkAddr[11],
+				     db->networkAddr[12],
+				     db->networkAddr[13],
+				     db->networkAddr[14],
+				     db->networkAddr[15],
+				     db->networkAddr[16]);
+#else
+			panic_printk("NAT25: DB(%d) H(%02d) C(%d) M:%02x%02x%02x%02x%02x%02x N:%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x\n",
+				     j,
+				     i,
+				     atomic_read(&db->use_count),
+				     db->macAddr[0],
+				     db->macAddr[1],
+				     db->macAddr[2],
+				     db->macAddr[3],
+				     db->macAddr[4],
+				     db->macAddr[5],
+				     db->networkAddr[0],
+				     db->networkAddr[1],
+				     db->networkAddr[2],
+				     db->networkAddr[3],
+				     db->networkAddr[4],
+				     db->networkAddr[5],
+				     db->networkAddr[6],
+				     db->networkAddr[7],
+				     db->networkAddr[8],
+				     db->networkAddr[9],
+				     db->networkAddr[10]);
+#endif
+			j++;
+
+			db = db->next_hash;
+		}
+	}
+#endif
+
+	_exit_critical_bh(&priv->br_ext_lock, &irqL);
+}
+
+
+
+
+/*
+ *	NAT2.5 interface
+ */
+
+void nat25_db_cleanup(_adapter *priv)
+{
+	int i;
+	_irqL irqL;
+	_enter_critical_bh(&priv->br_ext_lock, &irqL);
+
+	for (i = 0; i < NAT25_HASH_SIZE; i++) {
+		struct nat25_network_db_entry *f;
+		f = priv->nethash[i];
+		while (f != NULL) {
+			struct nat25_network_db_entry *g;
+
+			g = f->next_hash;
+			if (priv->scdb_entry == f) {
+				memset(priv->scdb_mac, 0, ETH_ALEN);
+				memset(priv->scdb_ip, 0, 4);
+				priv->scdb_entry = NULL;
+			}
+			__network_hash_unlink(f);
+			rtw_mfree((u8 *) f, sizeof(struct nat25_network_db_entry));
+
+			f = g;
+		}
+	}
+
+	_exit_critical_bh(&priv->br_ext_lock, &irqL);
+}
+
+
+void nat25_db_expire(_adapter *priv)
+{
+	int i;
+	_irqL irqL;
+	_enter_critical_bh(&priv->br_ext_lock, &irqL);
+
+	/* if(!priv->ethBrExtInfo.nat25_disable) */
+	{
+		for (i = 0; i < NAT25_HASH_SIZE; i++) {
+			struct nat25_network_db_entry *f;
+			f = priv->nethash[i];
+
+			while (f != NULL) {
+				struct nat25_network_db_entry *g;
+				g = f->next_hash;
+
+				if (__nat25_has_expired(priv, f)) {
+					if (atomic_dec_and_test(&f->use_count)) {
+#ifdef BR_EXT_DEBUG
+#ifdef CL_IPV6_PASS
+						panic_printk("NAT25 Expire H(%02d) M:%02x%02x%02x%02x%02x%02x N:%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x"
+							"%02x%02x%02x%02x%02x%02x\n",
+							     i,
+							     f->macAddr[0],
+							     f->macAddr[1],
+							     f->macAddr[2],
+							     f->macAddr[3],
+							     f->macAddr[4],
+							     f->macAddr[5],
+							     f->networkAddr[0],
+							     f->networkAddr[1],
+							     f->networkAddr[2],
+							     f->networkAddr[3],
+							     f->networkAddr[4],
+							     f->networkAddr[5],
+							     f->networkAddr[6],
+							     f->networkAddr[7],
+							     f->networkAddr[8],
+							     f->networkAddr[9],
+							     f->networkAddr[10],
+							     f->networkAddr[11],
+							     f->networkAddr[12],
+							     f->networkAddr[13],
+							     f->networkAddr[14],
+							     f->networkAddr[15],
+							f->networkAddr[16]);
+#else
+
+						panic_printk("NAT25 Expire H(%02d) M:%02x%02x%02x%02x%02x%02x N:%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x\n",
+							     i,
+							     f->macAddr[0],
+							     f->macAddr[1],
+							     f->macAddr[2],
+							     f->macAddr[3],
+							     f->macAddr[4],
+							     f->macAddr[5],
+							     f->networkAddr[0],
+							     f->networkAddr[1],
+							     f->networkAddr[2],
+							     f->networkAddr[3],
+							     f->networkAddr[4],
+							     f->networkAddr[5],
+							     f->networkAddr[6],
+							     f->networkAddr[7],
+							     f->networkAddr[8],
+							     f->networkAddr[9],
+							f->networkAddr[10]);
+#endif
+#endif
+						if (priv->scdb_entry == f) {
+							memset(priv->scdb_mac, 0, ETH_ALEN);
+							memset(priv->scdb_ip, 0, 4);
+							priv->scdb_entry = NULL;
+						}
+						__network_hash_unlink(f);
+						rtw_mfree((u8 *) f, sizeof(struct nat25_network_db_entry));
+					}
+				}
+
+				f = g;
+			}
+		}
+	}
+
+	_exit_critical_bh(&priv->br_ext_lock, &irqL);
+}
+
+
+#ifdef SUPPORT_TX_MCAST2UNI
+static int checkIPMcAndReplace(_adapter *priv, struct sk_buff *skb, unsigned int *dst_ip)
+{
+	struct stat_info	*pstat;
+	struct list_head	*phead, *plist;
+	int i;
+
+	phead = &priv->asoc_list;
+	plist = phead->next;
+
+	while (plist != phead) {
+		pstat = list_entry(plist, struct stat_info, asoc_list);
+		plist = plist->next;
+
+		if (pstat->ipmc_num == 0)
+			continue;
+
+		for (i = 0; i < MAX_IP_MC_ENTRY; i++) {
+			if (pstat->ipmc[i].used && !memcmp(&pstat->ipmc[i].mcmac[3], ((unsigned char *)dst_ip) + 1, 3)) {
+				memcpy(skb->data, pstat->ipmc[i].mcmac, ETH_ALEN);
+				return 1;
+			}
+		}
+	}
+	return 0;
+}
+#endif
+
+int nat25_db_handle(_adapter *priv, struct sk_buff *skb, int method)
+{
+	unsigned short protocol;
+	unsigned char networkAddr[MAX_NETWORK_ADDR_LEN];
+
+	if (skb == NULL)
+		return -1;
+
+	if ((method <= NAT25_MIN) || (method >= NAT25_MAX))
+		return -1;
+
+	protocol = *((unsigned short *)(skb->data + 2 * ETH_ALEN));
+
+	/*---------------------------------------------------*/
+	/*                 Handle IP frame                  */
+	/*---------------------------------------------------*/
+	if (protocol == __constant_htons(ETH_P_IP)) {
+		struct iphdr *iph = (struct iphdr *)(skb->data + ETH_HLEN);
+
+		if (((unsigned char *)(iph) + (iph->ihl << 2)) >= (skb->data + ETH_HLEN + skb->len)) {
+			DEBUG_WARN("NAT25: malformed IP packet !\n");
+			return -1;
+		}
+
+		switch (method) {
+		case NAT25_CHECK:
+			return -1;
+
+		case NAT25_INSERT: {
+			/* some muticast with source IP is all zero, maybe other case is illegal */
+			/* in class A, B, C, host address is all zero or all one is illegal */
+			if (iph->saddr == 0)
+				return 0;
+			RTW_INFO("NAT25: Insert IP, SA=%08x, DA=%08x\n", iph->saddr, iph->daddr);
+			__nat25_generate_ipv4_network_addr(networkAddr, &iph->saddr);
+			/* record source IP address and , source mac address into db */
+			__nat25_db_network_insert(priv, skb->data + ETH_ALEN, networkAddr);
+
+			__nat25_db_print(priv);
+		}
+		return 0;
+
+		case NAT25_LOOKUP: {
+			RTW_INFO("NAT25: Lookup IP, SA=%08x, DA=%08x\n", iph->saddr, iph->daddr);
+#ifdef SUPPORT_TX_MCAST2UNI
+			if (priv->pshare->rf_ft_var.mc2u_disable ||
+			    ((((OPMODE & (WIFI_STATION_STATE | WIFI_ASOC_STATE))
+			       == (WIFI_STATION_STATE | WIFI_ASOC_STATE)) &&
+			      !checkIPMcAndReplace(priv, skb, &iph->daddr)) ||
+			     (OPMODE & WIFI_ADHOC_STATE)))
+#endif
+			{
+				__nat25_generate_ipv4_network_addr(networkAddr, &iph->daddr);
+
+				if (!__nat25_db_network_lookup_and_replace(priv, skb, networkAddr)) {
+					if (*((unsigned char *)&iph->daddr + 3) == 0xff) {
+						/* L2 is unicast but L3 is broadcast, make L2 bacome broadcast */
+						RTW_INFO("NAT25: Set DA as boardcast\n");
+						memset(skb->data, 0xff, ETH_ALEN);
+					} else {
+						/* forward unknow IP packet to upper TCP/IP */
+						RTW_INFO("NAT25: Replace DA with BR's MAC\n");
+						if ((*(u32 *)priv->br_mac) == 0 && (*(u16 *)(priv->br_mac + 4)) == 0) {
+							void netdev_br_init(struct net_device *netdev);
+							printk("Re-init netdev_br_init() due to br_mac==0!\n");
+							netdev_br_init(priv->pnetdev);
+						}
+						memcpy(skb->data, priv->br_mac, ETH_ALEN);
+					}
+				}
+			}
+		}
+		return 0;
+
+		default:
+			return -1;
+		}
+	}
+
+	/*---------------------------------------------------*/
+	/*                 Handle ARP frame                 */
+	/*---------------------------------------------------*/
+	else if (protocol == __constant_htons(ETH_P_ARP)) {
+		struct arphdr *arp = (struct arphdr *)(skb->data + ETH_HLEN);
+		unsigned char *arp_ptr = (unsigned char *)(arp + 1);
+		unsigned int *sender, *target;
+
+		if (arp->ar_pro != __constant_htons(ETH_P_IP)) {
+			DEBUG_WARN("NAT25: arp protocol unknown (%4x)!\n", htons(arp->ar_pro));
+			return -1;
+		}
+
+		switch (method) {
+		case NAT25_CHECK:
+			return 0;	/* skb_copy for all ARP frame */
+
+		case NAT25_INSERT: {
+			RTW_INFO("NAT25: Insert ARP, MAC=%02x%02x%02x%02x%02x%02x\n", arp_ptr[0],
+				arp_ptr[1], arp_ptr[2], arp_ptr[3], arp_ptr[4], arp_ptr[5]);
+
+			/* change to ARP sender mac address to wlan STA address */
+			memcpy(arp_ptr, GET_MY_HWADDR(priv), ETH_ALEN);
+
+			arp_ptr += arp->ar_hln;
+			sender = (unsigned int *)arp_ptr;
+
+			__nat25_generate_ipv4_network_addr(networkAddr, sender);
+
+			__nat25_db_network_insert(priv, skb->data + ETH_ALEN, networkAddr);
+
+			__nat25_db_print(priv);
+		}
+		return 0;
+
+		case NAT25_LOOKUP: {
+			RTW_INFO("NAT25: Lookup ARP\n");
+
+			arp_ptr += arp->ar_hln;
+			sender = (unsigned int *)arp_ptr;
+			arp_ptr += (arp->ar_hln + arp->ar_pln);
+			target = (unsigned int *)arp_ptr;
+
+			__nat25_generate_ipv4_network_addr(networkAddr, target);
+
+			__nat25_db_network_lookup_and_replace(priv, skb, networkAddr);
+
+			/* change to ARP target mac address to Lookup result */
+			arp_ptr = (unsigned char *)(arp + 1);
+			arp_ptr += (arp->ar_hln + arp->ar_pln);
+			memcpy(arp_ptr, skb->data, ETH_ALEN);
+		}
+		return 0;
+
+		default:
+			return -1;
+		}
+	}
+
+	/*---------------------------------------------------*/
+	/*         Handle IPX and Apple Talk frame          */
+	/*---------------------------------------------------*/
+	else if ((protocol == __constant_htons(ETH_P_IPX)) ||
+		 (protocol == __constant_htons(ETH_P_ATALK)) ||
+		 (protocol == __constant_htons(ETH_P_AARP))) {
+		unsigned char ipx_header[2] = {0xFF, 0xFF};
+		struct ipxhdr	*ipx = NULL;
+		struct elapaarp	*ea = NULL;
+		struct ddpehdr	*ddp = NULL;
+		unsigned char *framePtr = skb->data + ETH_HLEN;
+
+		if (protocol == __constant_htons(ETH_P_IPX)) {
+			RTW_INFO("NAT25: Protocol=IPX (Ethernet II)\n");
+			ipx = (struct ipxhdr *)framePtr;
+		} else { /* if(protocol <= __constant_htons(ETH_FRAME_LEN)) */
+			if (!memcmp(ipx_header, framePtr, 2)) {
+				RTW_INFO("NAT25: Protocol=IPX (Ethernet 802.3)\n");
+				ipx = (struct ipxhdr *)framePtr;
+			} else {
+				unsigned char ipx_8022_type =  0xE0;
+				unsigned char snap_8022_type = 0xAA;
+
+				if (*framePtr == snap_8022_type) {
+					unsigned char ipx_snap_id[5] = {0x0, 0x0, 0x0, 0x81, 0x37};		/* IPX SNAP ID */
+					unsigned char aarp_snap_id[5] = {0x00, 0x00, 0x00, 0x80, 0xF3};	/* Apple Talk AARP SNAP ID */
+					unsigned char ddp_snap_id[5] = {0x08, 0x00, 0x07, 0x80, 0x9B};	/* Apple Talk DDP SNAP ID */
+
+					framePtr += 3;	/* eliminate the 802.2 header */
+
+					if (!memcmp(ipx_snap_id, framePtr, 5)) {
+						framePtr += 5;	/* eliminate the SNAP header */
+
+						RTW_INFO("NAT25: Protocol=IPX (Ethernet SNAP)\n");
+						ipx = (struct ipxhdr *)framePtr;
+					} else if (!memcmp(aarp_snap_id, framePtr, 5)) {
+						framePtr += 5;	/* eliminate the SNAP header */
+
+						ea = (struct elapaarp *)framePtr;
+					} else if (!memcmp(ddp_snap_id, framePtr, 5)) {
+						framePtr += 5;	/* eliminate the SNAP header */
+
+						ddp = (struct ddpehdr *)framePtr;
+					} else {
+						DEBUG_WARN("NAT25: Protocol=Ethernet SNAP %02x%02x%02x%02x%02x\n", framePtr[0],
+							framePtr[1], framePtr[2], framePtr[3], framePtr[4]);
+						return -1;
+					}
+				} else if (*framePtr == ipx_8022_type) {
+					framePtr += 3;	/* eliminate the 802.2 header */
+
+					if (!memcmp(ipx_header, framePtr, 2)) {
+						RTW_INFO("NAT25: Protocol=IPX (Ethernet 802.2)\n");
+						ipx = (struct ipxhdr *)framePtr;
+					} else
+						return -1;
+				}
+			}
+		}
+
+		/*   IPX  */
+		if (ipx != NULL) {
+			switch (method) {
+			case NAT25_CHECK:
+				if (!memcmp(skb->data + ETH_ALEN, ipx->ipx_source.node, ETH_ALEN)) {
+					RTW_INFO("NAT25: Check IPX skb_copy\n");
+					return 0;
+				}
+				return -1;
+
+			case NAT25_INSERT: {
+				RTW_INFO("NAT25: Insert IPX, Dest=%08x,%02x%02x%02x%02x%02x%02x,%04x Source=%08x,%02x%02x%02x%02x%02x%02x,%04x\n",
+					 ipx->ipx_dest.net,
+					 ipx->ipx_dest.node[0],
+					 ipx->ipx_dest.node[1],
+					 ipx->ipx_dest.node[2],
+					 ipx->ipx_dest.node[3],
+					 ipx->ipx_dest.node[4],
+					 ipx->ipx_dest.node[5],
+					 ipx->ipx_dest.sock,
+					 ipx->ipx_source.net,
+					 ipx->ipx_source.node[0],
+					 ipx->ipx_source.node[1],
+					 ipx->ipx_source.node[2],
+					 ipx->ipx_source.node[3],
+					 ipx->ipx_source.node[4],
+					 ipx->ipx_source.node[5],
+					 ipx->ipx_source.sock);
+
+				if (!memcmp(skb->data + ETH_ALEN, ipx->ipx_source.node, ETH_ALEN)) {
+					RTW_INFO("NAT25: Use IPX Net, and Socket as network addr\n");
+
+					__nat25_generate_ipx_network_addr_with_socket(networkAddr, &ipx->ipx_source.net, &ipx->ipx_source.sock);
+
+					/* change IPX source node addr to wlan STA address */
+					memcpy(ipx->ipx_source.node, GET_MY_HWADDR(priv), ETH_ALEN);
+				} else
+					__nat25_generate_ipx_network_addr_with_node(networkAddr, &ipx->ipx_source.net, ipx->ipx_source.node);
+
+				__nat25_db_network_insert(priv, skb->data + ETH_ALEN, networkAddr);
+
+				__nat25_db_print(priv);
+			}
+			return 0;
+
+			case NAT25_LOOKUP: {
+				if (!memcmp(GET_MY_HWADDR(priv), ipx->ipx_dest.node, ETH_ALEN)) {
+					RTW_INFO("NAT25: Lookup IPX, Modify Destination IPX Node addr\n");
+
+					__nat25_generate_ipx_network_addr_with_socket(networkAddr, &ipx->ipx_dest.net, &ipx->ipx_dest.sock);
+
+					__nat25_db_network_lookup_and_replace(priv, skb, networkAddr);
+
+					/* replace IPX destination node addr with Lookup destination MAC addr */
+					memcpy(ipx->ipx_dest.node, skb->data, ETH_ALEN);
+				} else {
+					__nat25_generate_ipx_network_addr_with_node(networkAddr, &ipx->ipx_dest.net, ipx->ipx_dest.node);
+
+					__nat25_db_network_lookup_and_replace(priv, skb, networkAddr);
+				}
+			}
+			return 0;
+
+			default:
+				return -1;
+			}
+		}
+
+		/*   AARP  */
+		else if (ea != NULL) {
+			/* Sanity check fields. */
+			if (ea->hw_len != ETH_ALEN || ea->pa_len != AARP_PA_ALEN) {
+				DEBUG_WARN("NAT25: Appletalk AARP Sanity check fail!\n");
+				return -1;
+			}
+
+			switch (method) {
+			case NAT25_CHECK:
+				return 0;
+
+			case NAT25_INSERT: {
+				/* change to AARP source mac address to wlan STA address */
+				memcpy(ea->hw_src, GET_MY_HWADDR(priv), ETH_ALEN);
+
+				RTW_INFO("NAT25: Insert AARP, Source=%d,%d Destination=%d,%d\n",
+					 ea->pa_src_net,
+					 ea->pa_src_node,
+					 ea->pa_dst_net,
+					 ea->pa_dst_node);
+
+				__nat25_generate_apple_network_addr(networkAddr, &ea->pa_src_net, &ea->pa_src_node);
+
+				__nat25_db_network_insert(priv, skb->data + ETH_ALEN, networkAddr);
+
+				__nat25_db_print(priv);
+			}
+			return 0;
+
+			case NAT25_LOOKUP: {
+				RTW_INFO("NAT25: Lookup AARP, Source=%d,%d Destination=%d,%d\n",
+					 ea->pa_src_net,
+					 ea->pa_src_node,
+					 ea->pa_dst_net,
+					 ea->pa_dst_node);
+
+				__nat25_generate_apple_network_addr(networkAddr, &ea->pa_dst_net, &ea->pa_dst_node);
+
+				__nat25_db_network_lookup_and_replace(priv, skb, networkAddr);
+
+				/* change to AARP destination mac address to Lookup result */
+				memcpy(ea->hw_dst, skb->data, ETH_ALEN);
+			}
+			return 0;
+
+			default:
+				return -1;
+			}
+		}
+
+		/*   DDP  */
+		else if (ddp != NULL) {
+			switch (method) {
+			case NAT25_CHECK:
+				return -1;
+
+			case NAT25_INSERT: {
+				RTW_INFO("NAT25: Insert DDP, Source=%d,%d Destination=%d,%d\n",
+					 ddp->deh_snet,
+					 ddp->deh_snode,
+					 ddp->deh_dnet,
+					 ddp->deh_dnode);
+
+				__nat25_generate_apple_network_addr(networkAddr, &ddp->deh_snet, &ddp->deh_snode);
+
+				__nat25_db_network_insert(priv, skb->data + ETH_ALEN, networkAddr);
+
+				__nat25_db_print(priv);
+			}
+			return 0;
+
+			case NAT25_LOOKUP: {
+				RTW_INFO("NAT25: Lookup DDP, Source=%d,%d Destination=%d,%d\n",
+					 ddp->deh_snet,
+					 ddp->deh_snode,
+					 ddp->deh_dnet,
+					 ddp->deh_dnode);
+
+				__nat25_generate_apple_network_addr(networkAddr, &ddp->deh_dnet, &ddp->deh_dnode);
+
+				__nat25_db_network_lookup_and_replace(priv, skb, networkAddr);
+			}
+			return 0;
+
+			default:
+				return -1;
+			}
+		}
+
+		return -1;
+	}
+
+	/*---------------------------------------------------*/
+	/*                Handle PPPoE frame                */
+	/*---------------------------------------------------*/
+	else if ((protocol == __constant_htons(ETH_P_PPP_DISC)) ||
+		 (protocol == __constant_htons(ETH_P_PPP_SES))) {
+		struct pppoe_hdr *ph = (struct pppoe_hdr *)(skb->data + ETH_HLEN);
+		unsigned short *pMagic;
+
+		switch (method) {
+		case NAT25_CHECK:
+			if (ph->sid == 0)
+				return 0;
+			return 1;
+
+		case NAT25_INSERT:
+			if (ph->sid == 0) {	/* Discovery phase according to tag */
+				if (ph->code == PADI_CODE || ph->code == PADR_CODE) {
+					if (priv->ethBrExtInfo.addPPPoETag) {
+						struct pppoe_tag *tag, *pOldTag;
+						unsigned char tag_buf[40];
+						int old_tag_len = 0;
+
+						tag = (struct pppoe_tag *)tag_buf;
+						pOldTag = (struct pppoe_tag *)__nat25_find_pppoe_tag(ph, ntohs(PTT_RELAY_SID));
+						if (pOldTag) { /* if SID existed, copy old value and delete it */
+							old_tag_len = ntohs(pOldTag->tag_len);
+							if (old_tag_len + TAG_HDR_LEN + MAGIC_CODE_LEN + RTL_RELAY_TAG_LEN > sizeof(tag_buf)) {
+								DEBUG_ERR("SID tag length too long!\n");
+								return -1;
+							}
+
+							memcpy(tag->tag_data + MAGIC_CODE_LEN + RTL_RELAY_TAG_LEN,
+							       pOldTag->tag_data, old_tag_len);
+
+							if (skb_pull_and_merge(skb, (unsigned char *)pOldTag, TAG_HDR_LEN + old_tag_len) < 0) {
+								DEBUG_ERR("call skb_pull_and_merge() failed in PADI/R packet!\n");
+								return -1;
+							}
+							ph->length = htons(ntohs(ph->length) - TAG_HDR_LEN - old_tag_len);
+						}
+
+						tag->tag_type = PTT_RELAY_SID;
+						tag->tag_len = htons(MAGIC_CODE_LEN + RTL_RELAY_TAG_LEN + old_tag_len);
+
+						/* insert the magic_code+client mac in relay tag */
+						pMagic = (unsigned short *)tag->tag_data;
+						*pMagic = htons(MAGIC_CODE);
+						memcpy(tag->tag_data + MAGIC_CODE_LEN, skb->data + ETH_ALEN, ETH_ALEN);
+
+						/* Add relay tag */
+						if (__nat25_add_pppoe_tag(skb, tag) < 0)
+							return -1;
+
+						RTW_INFO("NAT25: Insert PPPoE, forward %s packet\n",
+							(ph->code == PADI_CODE ? "PADI" : "PADR"));
+					} else { /* not add relay tag */
+						if (priv->pppoe_connection_in_progress &&
+						    memcmp(skb->data + ETH_ALEN, priv->pppoe_addr, ETH_ALEN))	 {
+							DEBUG_ERR("Discard PPPoE packet due to another PPPoE connection is in progress!\n");
+							return -2;
+						}
+
+						if (priv->pppoe_connection_in_progress == 0)
+							memcpy(priv->pppoe_addr, skb->data + ETH_ALEN, ETH_ALEN);
+
+						priv->pppoe_connection_in_progress = WAIT_TIME_PPPOE;
+					}
+				} else
+					return -1;
+			} else {	/* session phase */
+				RTW_INFO("NAT25: Insert PPPoE, insert session packet to %s\n", skb->dev->name);
+
+				__nat25_generate_pppoe_network_addr(networkAddr, skb->data, &(ph->sid));
+
+				__nat25_db_network_insert(priv, skb->data + ETH_ALEN, networkAddr);
+
+				__nat25_db_print(priv);
+
+				if (!priv->ethBrExtInfo.addPPPoETag &&
+				    priv->pppoe_connection_in_progress &&
+				    !memcmp(skb->data + ETH_ALEN, priv->pppoe_addr, ETH_ALEN))
+					priv->pppoe_connection_in_progress = 0;
+			}
+			return 0;
+
+		case NAT25_LOOKUP:
+			if (ph->code == PADO_CODE || ph->code == PADS_CODE) {
+				if (priv->ethBrExtInfo.addPPPoETag) {
+					struct pppoe_tag *tag;
+					unsigned char *ptr;
+					unsigned short tagType, tagLen;
+					int offset = 0;
+
+					ptr = __nat25_find_pppoe_tag(ph, ntohs(PTT_RELAY_SID));
+					if (ptr == 0) {
+						DEBUG_ERR("Fail to find PTT_RELAY_SID in FADO!\n");
+						return -1;
+					}
+
+					tag = (struct pppoe_tag *)ptr;
+					tagType = (unsigned short)((ptr[0] << 8) + ptr[1]);
+					tagLen = (unsigned short)((ptr[2] << 8) + ptr[3]);
+
+					if ((tagType != ntohs(PTT_RELAY_SID)) || (tagLen < (MAGIC_CODE_LEN + RTL_RELAY_TAG_LEN))) {
+						DEBUG_ERR("Invalid PTT_RELAY_SID tag length [%d]!\n", tagLen);
+						return -1;
+					}
+
+					pMagic = (unsigned short *)tag->tag_data;
+					if (ntohs(*pMagic) != MAGIC_CODE) {
+						DEBUG_ERR("Can't find MAGIC_CODE in %s packet!\n",
+							(ph->code == PADO_CODE ? "PADO" : "PADS"));
+						return -1;
+					}
+
+					memcpy(skb->data, tag->tag_data + MAGIC_CODE_LEN, ETH_ALEN);
+
+					if (tagLen > MAGIC_CODE_LEN + RTL_RELAY_TAG_LEN)
+						offset = TAG_HDR_LEN;
+
+					if (skb_pull_and_merge(skb, ptr + offset, TAG_HDR_LEN + MAGIC_CODE_LEN + RTL_RELAY_TAG_LEN - offset) < 0) {
+						DEBUG_ERR("call skb_pull_and_merge() failed in PADO packet!\n");
+						return -1;
+					}
+					ph->length = htons(ntohs(ph->length) - (TAG_HDR_LEN + MAGIC_CODE_LEN + RTL_RELAY_TAG_LEN - offset));
+					if (offset > 0)
+						tag->tag_len = htons(tagLen - MAGIC_CODE_LEN - RTL_RELAY_TAG_LEN);
+
+					RTW_INFO("NAT25: Lookup PPPoE, forward %s Packet from %s\n",
+						(ph->code == PADO_CODE ? "PADO" : "PADS"),	skb->dev->name);
+				} else { /* not add relay tag */
+					if (!priv->pppoe_connection_in_progress) {
+						DEBUG_ERR("Discard PPPoE packet due to no connection in progresss!\n");
+						return -1;
+					}
+					memcpy(skb->data, priv->pppoe_addr, ETH_ALEN);
+					priv->pppoe_connection_in_progress = WAIT_TIME_PPPOE;
+				}
+			} else {
+				if (ph->sid != 0) {
+					RTW_INFO("NAT25: Lookup PPPoE, lookup session packet from %s\n", skb->dev->name);
+					__nat25_generate_pppoe_network_addr(networkAddr, skb->data + ETH_ALEN, &(ph->sid));
+
+					__nat25_db_network_lookup_and_replace(priv, skb, networkAddr);
+
+					__nat25_db_print(priv);
+				} else
+					return -1;
+
+			}
+			return 0;
+
+		default:
+			return -1;
+		}
+	}
+
+	/*---------------------------------------------------*/
+	/*                 Handle EAP frame                 */
+	/*---------------------------------------------------*/
+	else if (protocol == __constant_htons(0x888e)) {
+		switch (method) {
+		case NAT25_CHECK:
+			return -1;
+
+		case NAT25_INSERT:
+			return 0;
+
+		case NAT25_LOOKUP:
+			return 0;
+
+		default:
+			return -1;
+		}
+	}
+
+	/*---------------------------------------------------*/
+	/*         Handle C-Media proprietary frame         */
+	/*---------------------------------------------------*/
+	else if ((protocol == __constant_htons(0xe2ae)) ||
+		 (protocol == __constant_htons(0xe2af))) {
+		switch (method) {
+		case NAT25_CHECK:
+			return -1;
+
+		case NAT25_INSERT:
+			return 0;
+
+		case NAT25_LOOKUP:
+			return 0;
+
+		default:
+			return -1;
+		}
+	}
+
+	/*---------------------------------------------------*/
+	/*         Handle IPV6 frame      							 */
+	/*---------------------------------------------------*/
+#ifdef CL_IPV6_PASS
+	else if (protocol == __constant_htons(ETH_P_IPV6)) {
+		struct ipv6hdr *iph = (struct ipv6hdr *)(skb->data + ETH_HLEN);
+
+		if (sizeof(*iph) >= (skb->len - ETH_HLEN)) {
+			DEBUG_WARN("NAT25: malformed IPv6 packet !\n");
+			return -1;
+		}
+
+		switch (method) {
+		case NAT25_CHECK:
+			if (skb->data[0] & 1)
+				return 0;
+			return -1;
+
+		case NAT25_INSERT: {
+			RTW_INFO("NAT25: Insert IP, SA=%4x:%4x:%4x:%4x:%4x:%4x:%4x:%4x,"
+				" DA=%4x:%4x:%4x:%4x:%4x:%4x:%4x:%4x\n",
+				iph->saddr.s6_addr16[0], iph->saddr.s6_addr16[1], iph->saddr.s6_addr16[2], iph->saddr.s6_addr16[3],
+				iph->saddr.s6_addr16[4], iph->saddr.s6_addr16[5], iph->saddr.s6_addr16[6], iph->saddr.s6_addr16[7],
+				iph->daddr.s6_addr16[0], iph->daddr.s6_addr16[1], iph->daddr.s6_addr16[2], iph->daddr.s6_addr16[3],
+				iph->daddr.s6_addr16[4], iph->daddr.s6_addr16[5], iph->daddr.s6_addr16[6], iph->daddr.s6_addr16[7]);
+
+			if (memcmp(&iph->saddr, "\x0\x0\x0\x0\x0\x0\x0\x0\x0\x0\x0\x0\x0\x0\x0\x0", 16)) {
+				__nat25_generate_ipv6_network_addr(networkAddr, (unsigned int *)&iph->saddr);
+				__nat25_db_network_insert(priv, skb->data + ETH_ALEN, networkAddr);
+				__nat25_db_print(priv);
+
+				if (iph->nexthdr == IPPROTO_ICMPV6 &&
+				    skb->len > (ETH_HLEN +  sizeof(*iph) + 4)) {
+					if (update_nd_link_layer_addr(skb->data + ETH_HLEN + sizeof(*iph),
+						skb->len - ETH_HLEN - sizeof(*iph), GET_MY_HWADDR(priv))) {
+						struct icmp6hdr  *hdr = (struct icmp6hdr *)(skb->data + ETH_HLEN + sizeof(*iph));
+						hdr->icmp6_cksum = 0;
+						hdr->icmp6_cksum = csum_ipv6_magic(&iph->saddr, &iph->daddr,
+							iph->payload_len,
+							IPPROTO_ICMPV6,
+							csum_partial((__u8 *)hdr, iph->payload_len, 0));
+					}
+				}
+			}
+		}
+		return 0;
+
+		case NAT25_LOOKUP:
+			RTW_INFO("NAT25: Lookup IP, SA=%4x:%4x:%4x:%4x:%4x:%4x:%4x:%4x,"
+				 " DA=%4x:%4x:%4x:%4x:%4x:%4x:%4x:%4x\n",
+				iph->saddr.s6_addr16[0], iph->saddr.s6_addr16[1], iph->saddr.s6_addr16[2], iph->saddr.s6_addr16[3],
+				iph->saddr.s6_addr16[4], iph->saddr.s6_addr16[5], iph->saddr.s6_addr16[6], iph->saddr.s6_addr16[7],
+				iph->daddr.s6_addr16[0], iph->daddr.s6_addr16[1], iph->daddr.s6_addr16[2], iph->daddr.s6_addr16[3],
+				iph->daddr.s6_addr16[4], iph->daddr.s6_addr16[5], iph->daddr.s6_addr16[6], iph->daddr.s6_addr16[7]);
+
+
+			__nat25_generate_ipv6_network_addr(networkAddr, (unsigned int *)&iph->daddr);
+			if (!__nat25_db_network_lookup_and_replace(priv, skb, networkAddr)) {
+#ifdef SUPPORT_RX_UNI2MCAST
+				if (iph->daddr.s6_addr[0] == 0xff)
+					convert_ipv6_mac_to_mc(skb);
+#endif
+			}
+			return 0;
+
+		default:
+			return -1;
+		}
+	}
+#endif /* CL_IPV6_PASS */
+
+	return -1;
+}
+
+
+int nat25_handle_frame(_adapter *priv, struct sk_buff *skb)
+{
+#ifdef BR_EXT_DEBUG
+	if ((!priv->ethBrExtInfo.nat25_disable) && (!(skb->data[0] & 1))) {
+		panic_printk("NAT25: Input Frame: DA=%02x%02x%02x%02x%02x%02x SA=%02x%02x%02x%02x%02x%02x\n",
+			     skb->data[0],
+			     skb->data[1],
+			     skb->data[2],
+			     skb->data[3],
+			     skb->data[4],
+			     skb->data[5],
+			     skb->data[6],
+			     skb->data[7],
+			     skb->data[8],
+			     skb->data[9],
+			     skb->data[10],
+			     skb->data[11]);
+	}
+#endif
+
+	if (!(skb->data[0] & 1)) {
+		int is_vlan_tag = 0, i, retval = 0;
+		unsigned short vlan_hdr = 0;
+
+		if (*((unsigned short *)(skb->data + ETH_ALEN * 2)) == __constant_htons(ETH_P_8021Q)) {
+			is_vlan_tag = 1;
+			vlan_hdr = *((unsigned short *)(skb->data + ETH_ALEN * 2 + 2));
+			for (i = 0; i < 6; i++)
+				*((unsigned short *)(skb->data + ETH_ALEN * 2 + 2 - i * 2)) = *((unsigned short *)(skb->data + ETH_ALEN * 2 - 2 - i * 2));
+			skb_pull(skb, 4);
+		}
+
+		if (!priv->ethBrExtInfo.nat25_disable) {
+			_irqL irqL;
+			_enter_critical_bh(&priv->br_ext_lock, &irqL);
+			/*
+			 *	This function look up the destination network address from
+			 *	the NAT2.5 database. Return value = -1 means that the
+			 *	corresponding network protocol is NOT support.
+			 */
+			if (!priv->ethBrExtInfo.nat25sc_disable &&
+			    (*((unsigned short *)(skb->data + ETH_ALEN * 2)) == __constant_htons(ETH_P_IP)) &&
+			    !memcmp(priv->scdb_ip, skb->data + ETH_HLEN + 16, 4)) {
+				memcpy(skb->data, priv->scdb_mac, ETH_ALEN);
+
+				_exit_critical_bh(&priv->br_ext_lock, &irqL);
+			} else {
+				_exit_critical_bh(&priv->br_ext_lock, &irqL);
+
+				retval = nat25_db_handle(priv, skb, NAT25_LOOKUP);
+			}
+		} else {
+			if (((*((unsigned short *)(skb->data + ETH_ALEN * 2)) == __constant_htons(ETH_P_IP)) &&
+			     !memcmp(priv->br_ip, skb->data + ETH_HLEN + 16, 4)) ||
+			    ((*((unsigned short *)(skb->data + ETH_ALEN * 2)) == __constant_htons(ETH_P_ARP)) &&
+			     !memcmp(priv->br_ip, skb->data + ETH_HLEN + 24, 4))) {
+				/* for traffic to upper TCP/IP */
+				retval = nat25_db_handle(priv, skb, NAT25_LOOKUP);
+			}
+		}
+
+		if (is_vlan_tag) {
+			skb_push(skb, 4);
+			for (i = 0; i < 6; i++)
+				*((unsigned short *)(skb->data + i * 2)) = *((unsigned short *)(skb->data + 4 + i * 2));
+			*((unsigned short *)(skb->data + ETH_ALEN * 2)) = __constant_htons(ETH_P_8021Q);
+			*((unsigned short *)(skb->data + ETH_ALEN * 2 + 2)) = vlan_hdr;
+		}
+
+		if (retval == -1) {
+			/* DEBUG_ERR("NAT25: Lookup fail!\n"); */
+			return -1;
+		}
+	}
+
+	return 0;
+}
+
+#if 0
+void mac_clone(_adapter *priv, unsigned char *addr)
+{
+	struct sockaddr sa;
+
+	memcpy(sa.sa_data, addr, ETH_ALEN);
+	RTW_INFO("MAC Clone: Addr=%02x%02x%02x%02x%02x%02x\n",
+		 addr[0], addr[1], addr[2], addr[3], addr[4], addr[5]);
+	rtl8192cd_set_hwaddr(priv->dev, &sa);
+}
+
+
+int mac_clone_handle_frame(_adapter *priv, struct sk_buff *skb)
+{
+	if (priv->ethBrExtInfo.macclone_enable && !priv->macclone_completed) {
+		if (!(skb->data[ETH_ALEN] & 1)) {	/* check any other particular MAC add */
+			if (memcmp(skb->data + ETH_ALEN, GET_MY_HWADDR(priv), ETH_ALEN) &&
+			    ((priv->dev->br_port) &&
+			     memcmp(skb->data + ETH_ALEN, priv->br_mac, ETH_ALEN))) {
+				mac_clone(priv, skb->data + ETH_ALEN);
+				priv->macclone_completed = 1;
+			}
+		}
+	}
+
+	return 0;
+}
+#endif /* 0 */
+
+#define SERVER_PORT			67
+#define CLIENT_PORT			68
+#define DHCP_MAGIC			0x63825363
+#define BROADCAST_FLAG		0x8000
+
+struct dhcpMessage {
+	u_int8_t op;
+	u_int8_t htype;
+	u_int8_t hlen;
+	u_int8_t hops;
+	u_int32_t xid;
+	u_int16_t secs;
+	u_int16_t flags;
+	u_int32_t ciaddr;
+	u_int32_t yiaddr;
+	u_int32_t siaddr;
+	u_int32_t giaddr;
+	u_int8_t chaddr[16];
+	u_int8_t sname[64];
+	u_int8_t file[128];
+	u_int32_t cookie;
+	u_int8_t options[308]; /* 312 - cookie */
+};
+
+void dhcp_flag_bcast(_adapter *priv, struct sk_buff *skb)
+{
+	if (skb == NULL)
+		return;
+
+	if (!priv->ethBrExtInfo.dhcp_bcst_disable) {
+		unsigned short protocol = *((unsigned short *)(skb->data + 2 * ETH_ALEN));
+
+		if (protocol == __constant_htons(ETH_P_IP)) { /* IP */
+			struct iphdr *iph = (struct iphdr *)(skb->data + ETH_HLEN);
+
+			if (iph->protocol == IPPROTO_UDP) { /* UDP */
+				struct udphdr *udph = (struct udphdr *)((SIZE_PTR)iph + (iph->ihl << 2));
+
+				if ((udph->source == __constant_htons(CLIENT_PORT))
+				    && (udph->dest == __constant_htons(SERVER_PORT))) { /* DHCP request */
+					struct dhcpMessage *dhcph =
+						(struct dhcpMessage *)((SIZE_PTR)udph + sizeof(struct udphdr));
+
+					if (dhcph->cookie == __constant_htonl(DHCP_MAGIC)) { /* match magic word */
+						if (!(dhcph->flags & htons(BROADCAST_FLAG))) { /* if not broadcast */
+							register int sum = 0;
+
+							RTW_INFO("DHCP: change flag of DHCP request to broadcast.\n");
+							/* or BROADCAST flag */
+							dhcph->flags |= htons(BROADCAST_FLAG);
+							/* recalculate checksum */
+							sum = ~(udph->check) & 0xffff;
+							sum += dhcph->flags;
+							while (sum >> 16)
+								sum = (sum & 0xffff) + (sum >> 16);
+							udph->check = ~sum;
+						}
+					}
+				}
+			}
+		}
+	}
+}
+
+
+void *scdb_findEntry(_adapter *priv, unsigned char *macAddr,
+		     unsigned char *ipAddr)
+{
+	unsigned char networkAddr[MAX_NETWORK_ADDR_LEN];
+	struct nat25_network_db_entry *db;
+	int hash;
+	/* _irqL irqL; */
+	/* _enter_critical_bh(&priv->br_ext_lock, &irqL); */
+
+	__nat25_generate_ipv4_network_addr(networkAddr, (unsigned int *)ipAddr);
+	hash = __nat25_network_hash(networkAddr);
+	db = priv->nethash[hash];
+	while (db != NULL) {
+		if (!memcmp(db->networkAddr, networkAddr, MAX_NETWORK_ADDR_LEN)) {
+			/* _exit_critical_bh(&priv->br_ext_lock, &irqL); */
+			return (void *)db;
+		}
+
+		db = db->next_hash;
+	}
+
+	/* _exit_critical_bh(&priv->br_ext_lock, &irqL); */
+	return NULL;
+}
+
+#endif /* CONFIG_BR_EXT */
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/core/rtw_btcoex.c linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/core/rtw_btcoex.c
--- linux-5.6.3/3rdparty/rtl8821ce/core/rtw_btcoex.c	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/core/rtw_btcoex.c	2020-04-10 16:35:06.771657967 +0300
@@ -0,0 +1,1763 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2013 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#include <drv_types.h>
+#include <hal_data.h>
+#ifdef CONFIG_BT_COEXIST
+#include <hal_btcoex.h>
+
+void rtw_btcoex_Initialize(PADAPTER padapter)
+{
+	hal_btcoex_Initialize(padapter);
+}
+
+void rtw_btcoex_PowerOnSetting(PADAPTER padapter)
+{
+	hal_btcoex_PowerOnSetting(padapter);
+}
+
+void rtw_btcoex_AntInfoSetting(PADAPTER padapter)
+{
+	hal_btcoex_AntInfoSetting(padapter);
+}
+
+void rtw_btcoex_PowerOffSetting(PADAPTER padapter)
+{
+	hal_btcoex_PowerOffSetting(padapter);
+}
+
+void rtw_btcoex_PreLoadFirmware(PADAPTER padapter)
+{
+	hal_btcoex_PreLoadFirmware(padapter);
+}
+
+void rtw_btcoex_HAL_Initialize(PADAPTER padapter, u8 bWifiOnly)
+{
+	hal_btcoex_InitHwConfig(padapter, bWifiOnly);
+}
+
+void rtw_btcoex_IpsNotify(PADAPTER padapter, u8 type)
+{
+	PHAL_DATA_TYPE	pHalData;
+
+	pHalData = GET_HAL_DATA(padapter);
+	if (_FALSE == pHalData->EEPROMBluetoothCoexist)
+		return;
+
+	hal_btcoex_IpsNotify(padapter, type);
+}
+
+void rtw_btcoex_LpsNotify(PADAPTER padapter, u8 type)
+{
+	PHAL_DATA_TYPE	pHalData;
+
+	pHalData = GET_HAL_DATA(padapter);
+	if (_FALSE == pHalData->EEPROMBluetoothCoexist)
+		return;
+
+	hal_btcoex_LpsNotify(padapter, type);
+}
+
+void rtw_btcoex_ScanNotify(PADAPTER padapter, u8 type)
+{
+	PHAL_DATA_TYPE	pHalData;
+#ifdef CONFIG_BT_COEXIST_SOCKET_TRX
+	struct bt_coex_info *pcoex_info = &padapter->coex_info;
+	PBT_MGNT	pBtMgnt = &pcoex_info->BtMgnt;
+#endif /* CONFIG_BT_COEXIST_SOCKET_TRX */
+
+	pHalData = GET_HAL_DATA(padapter);
+	if (_FALSE == pHalData->EEPROMBluetoothCoexist)
+		return;
+
+	if (_FALSE == type) {
+		#ifdef CONFIG_CONCURRENT_MODE
+		if (rtw_mi_buddy_check_fwstate(padapter, WIFI_SITE_MONITOR))
+			return;
+		#endif
+
+		if (DEV_MGMT_TX_NUM(adapter_to_dvobj(padapter))
+			|| DEV_ROCH_NUM(adapter_to_dvobj(padapter)))
+			return;
+	}
+
+#ifdef CONFIG_BT_COEXIST_SOCKET_TRX
+	if (pBtMgnt->ExtConfig.bEnableWifiScanNotify)
+		rtw_btcoex_SendScanNotify(padapter, type);
+#endif /* CONFIG_BT_COEXIST_SOCKET_TRX	 */
+
+	hal_btcoex_ScanNotify(padapter, type);
+}
+
+void rtw_btcoex_ConnectNotify(PADAPTER padapter, u8 action)
+{
+	PHAL_DATA_TYPE	pHalData;
+
+	pHalData = GET_HAL_DATA(padapter);
+	if (_FALSE == pHalData->EEPROMBluetoothCoexist)
+		return;
+
+#ifdef DBG_CONFIG_ERROR_RESET
+	if (_TRUE == rtw_hal_sreset_inprogress(padapter)) {
+		RTW_INFO(FUNC_ADPT_FMT ": [BTCoex] under reset, skip notify!\n",
+			 FUNC_ADPT_ARG(padapter));
+		return;
+	}
+#endif /* DBG_CONFIG_ERROR_RESET */
+
+#ifdef CONFIG_CONCURRENT_MODE
+	if (_FALSE == action) {
+		if (rtw_mi_buddy_check_fwstate(padapter, WIFI_UNDER_LINKING))
+			return;
+	}
+#endif
+
+	hal_btcoex_ConnectNotify(padapter, action);
+}
+
+void rtw_btcoex_MediaStatusNotify(PADAPTER padapter, u8 mediaStatus)
+{
+	PHAL_DATA_TYPE	pHalData;
+
+	pHalData = GET_HAL_DATA(padapter);
+	if (_FALSE == pHalData->EEPROMBluetoothCoexist)
+		return;
+
+#ifdef DBG_CONFIG_ERROR_RESET
+	if (_TRUE == rtw_hal_sreset_inprogress(padapter)) {
+		RTW_INFO(FUNC_ADPT_FMT ": [BTCoex] under reset, skip notify!\n",
+			 FUNC_ADPT_ARG(padapter));
+		return;
+	}
+#endif /* DBG_CONFIG_ERROR_RESET */
+
+#ifdef CONFIG_CONCURRENT_MODE
+	if (RT_MEDIA_DISCONNECT == mediaStatus) {
+		if (rtw_mi_buddy_check_fwstate(padapter, WIFI_ASOC_STATE))
+			return;
+	}
+#endif /* CONFIG_CONCURRENT_MODE */
+
+	if ((RT_MEDIA_CONNECT == mediaStatus)
+	    && (check_fwstate(&padapter->mlmepriv, WIFI_AP_STATE) == _TRUE))
+		rtw_hal_set_hwreg(padapter, HW_VAR_DL_RSVD_PAGE, NULL);
+
+	hal_btcoex_MediaStatusNotify(padapter, mediaStatus);
+}
+
+void rtw_btcoex_SpecialPacketNotify(PADAPTER padapter, u8 pktType)
+{
+	PHAL_DATA_TYPE	pHalData;
+
+	pHalData = GET_HAL_DATA(padapter);
+	if (_FALSE == pHalData->EEPROMBluetoothCoexist)
+		return;
+
+	hal_btcoex_SpecialPacketNotify(padapter, pktType);
+}
+
+void rtw_btcoex_IQKNotify(PADAPTER padapter, u8 state)
+{
+	PHAL_DATA_TYPE	pHalData;
+
+	pHalData = GET_HAL_DATA(padapter);
+	if (_FALSE == pHalData->EEPROMBluetoothCoexist)
+		return;
+
+	hal_btcoex_IQKNotify(padapter, state);
+}
+
+void rtw_btcoex_BtInfoNotify(PADAPTER padapter, u8 length, u8 *tmpBuf)
+{
+	PHAL_DATA_TYPE	pHalData;
+
+	pHalData = GET_HAL_DATA(padapter);
+	if (_FALSE == pHalData->EEPROMBluetoothCoexist)
+		return;
+
+	hal_btcoex_BtInfoNotify(padapter, length, tmpBuf);
+}
+
+void rtw_btcoex_BtMpRptNotify(PADAPTER padapter, u8 length, u8 *tmpBuf)
+{
+	PHAL_DATA_TYPE	pHalData;
+
+	pHalData = GET_HAL_DATA(padapter);
+	if (_FALSE == pHalData->EEPROMBluetoothCoexist)
+		return;
+
+	if (padapter->registrypriv.mp_mode == 1)
+		return;
+
+	hal_btcoex_BtMpRptNotify(padapter, length, tmpBuf);
+}
+
+void rtw_btcoex_SuspendNotify(PADAPTER padapter, u8 state)
+{
+	PHAL_DATA_TYPE	pHalData;
+
+	pHalData = GET_HAL_DATA(padapter);
+	if (_FALSE == pHalData->EEPROMBluetoothCoexist)
+		return;
+
+	hal_btcoex_SuspendNotify(padapter, state);
+}
+
+void rtw_btcoex_HaltNotify(PADAPTER padapter)
+{
+	PHAL_DATA_TYPE	pHalData;
+	u8 do_halt = 1;
+
+	pHalData = GET_HAL_DATA(padapter);
+	if (_FALSE == pHalData->EEPROMBluetoothCoexist)
+		do_halt = 0;
+
+	if (_FALSE == padapter->bup) {
+		RTW_INFO(FUNC_ADPT_FMT ": bup=%d Skip!\n",
+			 FUNC_ADPT_ARG(padapter), padapter->bup);
+		do_halt = 0;
+	}
+
+	if (rtw_is_surprise_removed(padapter)) {
+		RTW_INFO(FUNC_ADPT_FMT ": bSurpriseRemoved=%s Skip!\n",
+			FUNC_ADPT_ARG(padapter), rtw_is_surprise_removed(padapter) ? "True" : "False");
+		do_halt = 0;
+	}
+
+	hal_btcoex_HaltNotify(padapter, do_halt);
+}
+
+void rtw_btcoex_switchband_notify(u8 under_scan, u8 band_type)
+{
+	hal_btcoex_switchband_notify(under_scan, band_type);
+}
+
+void rtw_btcoex_WlFwDbgInfoNotify(PADAPTER padapter, u8* tmpBuf, u8 length)
+{
+	hal_btcoex_WlFwDbgInfoNotify(padapter, tmpBuf, length);
+}
+
+void rtw_btcoex_rx_rate_change_notify(PADAPTER padapter, u8 is_data_frame, u8 rate_id)
+{
+	hal_btcoex_rx_rate_change_notify(padapter, is_data_frame, rate_id);
+}
+
+void rtw_btcoex_SwitchBtTRxMask(PADAPTER padapter)
+{
+	hal_btcoex_SwitchBtTRxMask(padapter);
+}
+
+void rtw_btcoex_Switch(PADAPTER padapter, u8 enable)
+{
+	hal_btcoex_SetBTCoexist(padapter, enable);
+}
+
+u8 rtw_btcoex_IsBtDisabled(PADAPTER padapter)
+{
+	return hal_btcoex_IsBtDisabled(padapter);
+}
+
+void rtw_btcoex_Handler(PADAPTER padapter)
+{
+	PHAL_DATA_TYPE	pHalData;
+
+	pHalData = GET_HAL_DATA(padapter);
+
+	if (_FALSE == pHalData->EEPROMBluetoothCoexist)
+		return;
+
+	hal_btcoex_Hanlder(padapter);
+}
+
+s32 rtw_btcoex_IsBTCoexRejectAMPDU(PADAPTER padapter)
+{
+	s32 coexctrl;
+
+	coexctrl = hal_btcoex_IsBTCoexRejectAMPDU(padapter);
+
+	return coexctrl;
+}
+
+s32 rtw_btcoex_IsBTCoexCtrlAMPDUSize(PADAPTER padapter)
+{
+	s32 coexctrl;
+
+	coexctrl = hal_btcoex_IsBTCoexCtrlAMPDUSize(padapter);
+
+	return coexctrl;
+}
+
+u32 rtw_btcoex_GetAMPDUSize(PADAPTER padapter)
+{
+	u32 size;
+
+	size = hal_btcoex_GetAMPDUSize(padapter);
+
+	return size;
+}
+
+void rtw_btcoex_SetManualControl(PADAPTER padapter, u8 manual)
+{
+	if (_TRUE == manual)
+		hal_btcoex_SetManualControl(padapter, _TRUE);
+	else
+		hal_btcoex_SetManualControl(padapter, _FALSE);
+}
+
+u8 rtw_btcoex_1Ant(PADAPTER padapter)
+{
+	return hal_btcoex_1Ant(padapter);
+}
+
+u8 rtw_btcoex_IsBtControlLps(PADAPTER padapter)
+{
+	return hal_btcoex_IsBtControlLps(padapter);
+}
+
+u8 rtw_btcoex_IsLpsOn(PADAPTER padapter)
+{
+	return hal_btcoex_IsLpsOn(padapter);
+}
+
+u8 rtw_btcoex_RpwmVal(PADAPTER padapter)
+{
+	return hal_btcoex_RpwmVal(padapter);
+}
+
+u8 rtw_btcoex_LpsVal(PADAPTER padapter)
+{
+	return hal_btcoex_LpsVal(padapter);
+}
+
+u32 rtw_btcoex_GetRaMask(PADAPTER padapter)
+{
+	return hal_btcoex_GetRaMask(padapter);
+}
+
+void rtw_btcoex_RecordPwrMode(PADAPTER padapter, u8 *pCmdBuf, u8 cmdLen)
+{
+	hal_btcoex_RecordPwrMode(padapter, pCmdBuf, cmdLen);
+}
+
+void rtw_btcoex_DisplayBtCoexInfo(PADAPTER padapter, u8 *pbuf, u32 bufsize)
+{
+	hal_btcoex_DisplayBtCoexInfo(padapter, pbuf, bufsize);
+}
+
+void rtw_btcoex_SetDBG(PADAPTER padapter, u32 *pDbgModule)
+{
+	hal_btcoex_SetDBG(padapter, pDbgModule);
+}
+
+u32 rtw_btcoex_GetDBG(PADAPTER padapter, u8 *pStrBuf, u32 bufSize)
+{
+	return hal_btcoex_GetDBG(padapter, pStrBuf, bufSize);
+}
+
+u8 rtw_btcoex_IncreaseScanDeviceNum(PADAPTER padapter)
+{
+	return hal_btcoex_IncreaseScanDeviceNum(padapter);
+}
+
+u8 rtw_btcoex_IsBtLinkExist(PADAPTER padapter)
+{
+	return hal_btcoex_IsBtLinkExist(padapter);
+}
+
+void rtw_btcoex_SetBtPatchVersion(PADAPTER padapter, u16 btHciVer, u16 btPatchVer)
+{
+	hal_btcoex_SetBtPatchVersion(padapter, btHciVer, btPatchVer);
+}
+
+void rtw_btcoex_SetHciVersion(PADAPTER  padapter, u16 hciVersion)
+{
+	hal_btcoex_SetHciVersion(padapter, hciVersion);
+}
+
+void rtw_btcoex_StackUpdateProfileInfo(void)
+{
+	hal_btcoex_StackUpdateProfileInfo();
+}
+
+void rtw_btcoex_pta_off_on_notify(PADAPTER padapter, u8 bBTON)
+{
+	hal_btcoex_pta_off_on_notify(padapter, bBTON);
+}
+
+#ifdef CONFIG_RF4CE_COEXIST
+void rtw_btcoex_SetRf4ceLinkState(PADAPTER padapter, u8 state)
+{
+	hal_btcoex_set_rf4ce_link_state(state);
+}
+
+u8 rtw_btcoex_GetRf4ceLinkState(PADAPTER padapter)
+{
+	return hal_btcoex_get_rf4ce_link_state();
+}
+#endif
+
+/* ==================================================
+ * Below Functions are called by BT-Coex
+ * ================================================== */
+void rtw_btcoex_rx_ampdu_apply(PADAPTER padapter)
+{
+	rtw_rx_ampdu_apply(padapter);
+}
+
+void rtw_btcoex_LPS_Enter(PADAPTER padapter)
+{
+	struct pwrctrl_priv *pwrpriv;
+	u8 lpsVal;
+
+
+	pwrpriv = adapter_to_pwrctl(padapter);
+
+	pwrpriv->bpower_saving = _TRUE;
+	lpsVal = rtw_btcoex_LpsVal(padapter);
+	rtw_set_ps_mode(padapter, PS_MODE_MIN, 0, lpsVal, "BTCOEX");
+}
+
+u8 rtw_btcoex_LPS_Leave(PADAPTER padapter)
+{
+	struct pwrctrl_priv *pwrpriv;
+
+
+	pwrpriv = adapter_to_pwrctl(padapter);
+
+	if (pwrpriv->pwr_mode != PS_MODE_ACTIVE) {
+		rtw_set_ps_mode(padapter, PS_MODE_ACTIVE, 0, 0, "BTCOEX");
+		LPS_RF_ON_check(padapter, 100);
+		pwrpriv->bpower_saving = _FALSE;
+	}
+
+	return _TRUE;
+}
+
+u16 rtw_btcoex_btreg_read(PADAPTER padapter, u8 type, u16 addr, u32 *data)
+{
+	return hal_btcoex_btreg_read(padapter, type, addr, data);
+}
+
+u16 rtw_btcoex_btreg_write(PADAPTER padapter, u8 type, u16 addr, u16 val)
+{
+	return hal_btcoex_btreg_write(padapter, type, addr, val);
+}
+
+u8 rtw_btcoex_get_bt_coexist(PADAPTER padapter)
+{
+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(padapter);
+
+	return pHalData->EEPROMBluetoothCoexist;
+}
+
+u8 rtw_btcoex_get_chip_type(PADAPTER padapter)
+{
+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(padapter);
+
+	return pHalData->EEPROMBluetoothType;
+}
+
+u8 rtw_btcoex_get_pg_ant_num(PADAPTER padapter)
+{
+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(padapter);
+
+	return pHalData->EEPROMBluetoothAntNum == Ant_x2 ? 2 : 1;
+}
+
+u8 rtw_btcoex_get_pg_single_ant_path(PADAPTER padapter)
+{
+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(padapter);
+
+	return pHalData->ant_path;
+}
+
+u8 rtw_btcoex_get_pg_rfe_type(PADAPTER padapter)
+{
+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(padapter);
+
+	return pHalData->rfe_type;
+}
+
+u8 rtw_btcoex_is_tfbga_package_type(PADAPTER padapter)
+{
+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(padapter);
+
+#ifdef CONFIG_RTL8723B
+	if ((pHalData->PackageType == PACKAGE_TFBGA79) || (pHalData->PackageType == PACKAGE_TFBGA80)
+	    || (pHalData->PackageType == PACKAGE_TFBGA90))
+		return _TRUE;
+#endif
+
+	return _FALSE;
+}
+
+u8 rtw_btcoex_get_ant_div_cfg(PADAPTER padapter)
+{
+	PHAL_DATA_TYPE pHalData;
+
+	pHalData = GET_HAL_DATA(padapter);
+	
+	return (pHalData->AntDivCfg == 0) ? _FALSE : _TRUE;
+}
+
+/* ==================================================
+ * Below Functions are BT-Coex socket related function
+ * ================================================== */
+
+#ifdef CONFIG_BT_COEXIST_SOCKET_TRX
+_adapter *pbtcoexadapter; /* = NULL; */ /* do not initialise globals to 0 or NULL */
+u8 rtw_btcoex_btinfo_cmd(_adapter *adapter, u8 *buf, u16 len)
+{
+	struct cmd_obj *ph2c;
+	struct drvextra_cmd_parm *pdrvextra_cmd_parm;
+	u8 *btinfo;
+	struct cmd_priv *pcmdpriv = &adapter->cmdpriv;
+	u8	res = _SUCCESS;
+
+	ph2c = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj));
+	if (ph2c == NULL) {
+		res = _FAIL;
+		goto exit;
+	}
+
+	pdrvextra_cmd_parm = (struct drvextra_cmd_parm *)rtw_zmalloc(sizeof(struct drvextra_cmd_parm));
+	if (pdrvextra_cmd_parm == NULL) {
+		rtw_mfree((u8 *)ph2c, sizeof(struct cmd_obj));
+		res = _FAIL;
+		goto exit;
+	}
+
+	btinfo = rtw_zmalloc(len);
+	if (btinfo == NULL) {
+		rtw_mfree((u8 *)ph2c, sizeof(struct cmd_obj));
+		rtw_mfree((u8 *)pdrvextra_cmd_parm, sizeof(struct drvextra_cmd_parm));
+		res = _FAIL;
+		goto exit;
+	}
+
+	pdrvextra_cmd_parm->ec_id = BTINFO_WK_CID;
+	pdrvextra_cmd_parm->type = 0;
+	pdrvextra_cmd_parm->size = len;
+	pdrvextra_cmd_parm->pbuf = btinfo;
+
+	_rtw_memcpy(btinfo, buf, len);
+
+	init_h2fwcmd_w_parm_no_rsp(ph2c, pdrvextra_cmd_parm, GEN_CMD_CODE(_Set_Drv_Extra));
+
+	res = rtw_enqueue_cmd(pcmdpriv, ph2c);
+
+exit:
+	return res;
+}
+
+u8 rtw_btcoex_send_event_to_BT(_adapter *padapter, u8 status,  u8 event_code, u8 opcode_low, u8 opcode_high, u8 *dbg_msg)
+{
+	u8 localBuf[6] = "";
+	u8 *pRetPar;
+	u8	len = 0, tx_event_length = 0;
+	rtw_HCI_event *pEvent;
+
+	pEvent = (rtw_HCI_event *)(&localBuf[0]);
+
+	pEvent->EventCode = event_code;
+	pEvent->Data[0] = 0x1;	/* packet # */
+	pEvent->Data[1] = opcode_low;
+	pEvent->Data[2] = opcode_high;
+	len = len + 3;
+
+	/* Return parameters starts from here */
+	pRetPar = &pEvent->Data[len];
+	pRetPar[0] = status;		/* status */
+
+	len++;
+	pEvent->Length = len;
+
+	/* total tx event length + EventCode length + sizeof(length) */
+	tx_event_length = pEvent->Length + 2;
+#if 0
+	rtw_btcoex_dump_tx_msg((u8 *)pEvent, tx_event_length, dbg_msg);
+#endif
+	status = rtw_btcoex_sendmsgbysocket(padapter, (u8 *)pEvent, tx_event_length, _FALSE);
+
+	return status;
+}
+
+/*
+Ref:
+Realtek Wi-Fi Driver
+Host Controller Interface for
+Bluetooth 3.0 + HS V1.4 2013/02/07
+
+Window team code & BT team code
+ */
+
+
+u8 rtw_btcoex_parse_BT_info_notify_cmd(_adapter *padapter, u8 *pcmd, u16 cmdlen)
+{
+#define BT_INFO_LENGTH 8
+
+	u8 curPollEnable = pcmd[0];
+	u8 curPollTime = pcmd[1];
+	u8 btInfoReason = pcmd[2];
+	u8 btInfoLen = pcmd[3];
+	u8 btinfo[BT_INFO_LENGTH];
+
+	u8 localBuf[6] = "";
+	u8 *pRetPar;
+	u8	len = 0, tx_event_length = 0;
+	RTW_HCI_STATUS status = HCI_STATUS_SUCCESS;
+	rtw_HCI_event *pEvent;
+
+	/* RTW_INFO("%s\n",__func__);
+	RTW_INFO("current Poll Enable: %d, currrent Poll Time: %d\n",curPollEnable,curPollTime);
+	RTW_INFO("BT Info reason: %d, BT Info length: %d\n",btInfoReason,btInfoLen);
+	RTW_INFO("%02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x\n"
+		,pcmd[4],pcmd[5],pcmd[6],pcmd[7],pcmd[8],pcmd[9],pcmd[10],pcmd[11]);*/
+
+	_rtw_memset(btinfo, 0, BT_INFO_LENGTH);
+
+#if 1
+	if (BT_INFO_LENGTH != btInfoLen) {
+		status = HCI_STATUS_INVALID_HCI_CMD_PARA_VALUE;
+		RTW_INFO("Error BT Info Length: %d\n", btInfoLen);
+		/* return _FAIL; */
+	} else
+#endif
+	{
+		if (0x1 == btInfoReason || 0x2 == btInfoReason) {
+			_rtw_memcpy(btinfo, &pcmd[4], btInfoLen);
+			btinfo[0] = btInfoReason;
+			rtw_btcoex_btinfo_cmd(padapter, btinfo, btInfoLen);
+		} else
+			RTW_INFO("Other BT info reason\n");
+	}
+
+	/* send complete event to BT */
+	{
+
+		pEvent = (rtw_HCI_event *)(&localBuf[0]);
+
+		pEvent->EventCode = HCI_EVENT_COMMAND_COMPLETE;
+		pEvent->Data[0] = 0x1;	/* packet # */
+		pEvent->Data[1] = HCIOPCODELOW(HCI_BT_INFO_NOTIFY, OGF_EXTENSION);
+		pEvent->Data[2] = HCIOPCODEHIGHT(HCI_BT_INFO_NOTIFY, OGF_EXTENSION);
+		len = len + 3;
+
+		/* Return parameters starts from here */
+		pRetPar = &pEvent->Data[len];
+		pRetPar[0] = status;		/* status */
+
+		len++;
+		pEvent->Length = len;
+
+		/* total tx event length + EventCode length + sizeof(length) */
+		tx_event_length = pEvent->Length + 2;
+#if 0
+		rtw_btcoex_dump_tx_msg((u8 *)pEvent, tx_event_length, "BT_info_event");
+#endif
+		status = rtw_btcoex_sendmsgbysocket(padapter, (u8 *)pEvent, tx_event_length, _FALSE);
+
+		return status;
+		/* bthci_IndicateEvent(Adapter, PPacketIrpEvent, len+2); */
+	}
+}
+
+u8 rtw_btcoex_parse_BT_patch_ver_info_cmd(_adapter *padapter, u8 *pcmd, u16 cmdlen)
+{
+	RTW_HCI_STATUS status = HCI_STATUS_SUCCESS;
+	u16		btPatchVer = 0x0, btHciVer = 0x0;
+	/* u16		*pU2tmp; */
+
+	u8 localBuf[6] = "";
+	u8 *pRetPar;
+	u8	len = 0, tx_event_length = 0;
+	rtw_HCI_event *pEvent;
+
+	btHciVer = pcmd[0] | pcmd[1] << 8;
+	btPatchVer = pcmd[2] | pcmd[3] << 8;
+
+
+	RTW_INFO("%s, cmd:%02x %02x %02x %02x\n", __func__, pcmd[0] , pcmd[1] , pcmd[2] , pcmd[3]);
+	RTW_INFO("%s, HCI Ver:%d, Patch Ver:%d\n", __func__, btHciVer, btPatchVer);
+
+	rtw_btcoex_SetBtPatchVersion(padapter, btHciVer, btPatchVer);
+
+
+	/* send complete event to BT */
+	{
+		pEvent = (rtw_HCI_event *)(&localBuf[0]);
+
+
+		pEvent->EventCode = HCI_EVENT_COMMAND_COMPLETE;
+		pEvent->Data[0] = 0x1;	/* packet # */
+		pEvent->Data[1] = HCIOPCODELOW(HCI_BT_PATCH_VERSION_NOTIFY, OGF_EXTENSION);
+		pEvent->Data[2] = HCIOPCODEHIGHT(HCI_BT_PATCH_VERSION_NOTIFY, OGF_EXTENSION);
+		len = len + 3;
+
+		/* Return parameters starts from here */
+		pRetPar = &pEvent->Data[len];
+		pRetPar[0] = status;		/* status */
+
+		len++;
+		pEvent->Length = len;
+
+		/* total tx event length + EventCode length + sizeof(length) */
+		tx_event_length = pEvent->Length + 2;
+#if 0
+		rtw_btcoex_dump_tx_msg((u8 *)pEvent, tx_event_length, "BT_patch_event");
+#endif
+		status = rtw_btcoex_sendmsgbysocket(padapter, (u8 *)pEvent, tx_event_length, _FALSE);
+		return status;
+		/* bthci_IndicateEvent(Adapter, PPacketIrpEvent, len+2); */
+	}
+}
+
+u8 rtw_btcoex_parse_HCI_Ver_notify_cmd(_adapter *padapter, u8 *pcmd, u16 cmdlen)
+{
+	RTW_HCI_STATUS status = HCI_STATUS_SUCCESS;
+	u16 hciver = pcmd[0] | pcmd[1] << 8;
+
+	u8 localBuf[6] = "";
+	u8 *pRetPar;
+	u8	len = 0, tx_event_length = 0;
+	rtw_HCI_event *pEvent;
+
+	struct bt_coex_info *pcoex_info = &padapter->coex_info;
+	PBT_MGNT	pBtMgnt = &pcoex_info->BtMgnt;
+	pBtMgnt->ExtConfig.HCIExtensionVer = hciver;
+	RTW_INFO("%s, HCI Version: %d\n", __func__, pBtMgnt->ExtConfig.HCIExtensionVer);
+	if (pBtMgnt->ExtConfig.HCIExtensionVer  < 4) {
+		status = HCI_STATUS_INVALID_HCI_CMD_PARA_VALUE;
+		RTW_INFO("%s, Version = %d, HCI Version < 4\n", __func__, pBtMgnt->ExtConfig.HCIExtensionVer);
+	} else
+		rtw_btcoex_SetHciVersion(padapter, hciver);
+	/* send complete event to BT */
+	{
+		pEvent = (rtw_HCI_event *)(&localBuf[0]);
+
+
+		pEvent->EventCode = HCI_EVENT_COMMAND_COMPLETE;
+		pEvent->Data[0] = 0x1;	/* packet # */
+		pEvent->Data[1] = HCIOPCODELOW(HCI_EXTENSION_VERSION_NOTIFY, OGF_EXTENSION);
+		pEvent->Data[2] = HCIOPCODEHIGHT(HCI_EXTENSION_VERSION_NOTIFY, OGF_EXTENSION);
+		len = len + 3;
+
+		/* Return parameters starts from here */
+		pRetPar = &pEvent->Data[len];
+		pRetPar[0] = status;		/* status */
+
+		len++;
+		pEvent->Length = len;
+
+		/* total tx event length + EventCode length + sizeof(length) */
+		tx_event_length = pEvent->Length + 2;
+
+		status = rtw_btcoex_sendmsgbysocket(padapter, (u8 *)pEvent, tx_event_length, _FALSE);
+		return status;
+		/* bthci_IndicateEvent(Adapter, PPacketIrpEvent, len+2); */
+	}
+
+}
+
+u8 rtw_btcoex_parse_WIFI_scan_notify_cmd(_adapter *padapter, u8 *pcmd, u16 cmdlen)
+{
+	RTW_HCI_STATUS status = HCI_STATUS_SUCCESS;
+
+	u8 localBuf[6] = "";
+	u8 *pRetPar;
+	u8	len = 0, tx_event_length = 0;
+	rtw_HCI_event *pEvent;
+
+	struct bt_coex_info *pcoex_info = &padapter->coex_info;
+	PBT_MGNT	pBtMgnt = &pcoex_info->BtMgnt;
+	pBtMgnt->ExtConfig.bEnableWifiScanNotify = pcmd[0];
+	RTW_INFO("%s, bEnableWifiScanNotify: %d\n", __func__, pBtMgnt->ExtConfig.bEnableWifiScanNotify);
+
+	/* send complete event to BT */
+	{
+		pEvent = (rtw_HCI_event *)(&localBuf[0]);
+
+
+		pEvent->EventCode = HCI_EVENT_COMMAND_COMPLETE;
+		pEvent->Data[0] = 0x1;	/* packet # */
+		pEvent->Data[1] = HCIOPCODELOW(HCI_ENABLE_WIFI_SCAN_NOTIFY, OGF_EXTENSION);
+		pEvent->Data[2] = HCIOPCODEHIGHT(HCI_ENABLE_WIFI_SCAN_NOTIFY, OGF_EXTENSION);
+		len = len + 3;
+
+		/* Return parameters starts from here */
+		pRetPar = &pEvent->Data[len];
+		pRetPar[0] = status;		/* status */
+
+		len++;
+		pEvent->Length = len;
+
+		/* total tx event length + EventCode length + sizeof(length) */
+		tx_event_length = pEvent->Length + 2;
+
+		status = rtw_btcoex_sendmsgbysocket(padapter, (u8 *)pEvent, tx_event_length, _FALSE);
+		return status;
+		/* bthci_IndicateEvent(Adapter, PPacketIrpEvent, len+2); */
+	}
+}
+
+u8 rtw_btcoex_parse_HCI_link_status_notify_cmd(_adapter *padapter, u8 *pcmd, u16 cmdlen)
+{
+	RTW_HCI_STATUS	status = HCI_STATUS_SUCCESS;
+	struct bt_coex_info	*pcoex_info = &padapter->coex_info;
+	PBT_MGNT	pBtMgnt = &pcoex_info->BtMgnt;
+	/* PBT_DBG		pBtDbg=&padapter->MgntInfo.BtInfo.BtDbg; */
+	u8		i, numOfHandle = 0, numOfAcl = 0;
+	u16		conHandle;
+	u8		btProfile, btCoreSpec, linkRole;
+	u8		*pTriple;
+
+	u8 localBuf[6] = "";
+	u8 *pRetPar;
+	u8	len = 0, tx_event_length = 0;
+	rtw_HCI_event *pEvent;
+
+	/* pBtDbg->dbgHciInfo.hciCmdCntLinkStatusNotify++; */
+	/* RT_DISP_DATA(FIOCTL, IOCTL_BT_HCICMD_EXT, "LinkStatusNotify, Hex Data :\n",  */
+	/*		&pHciCmd->Data[0], pHciCmd->Length); */
+
+	RTW_INFO("BTLinkStatusNotify\n");
+
+	/* Current only RTL8723 support this command. */
+	/* pBtMgnt->bSupportProfile = TRUE; */
+	pBtMgnt->bSupportProfile = _FALSE;
+
+	pBtMgnt->ExtConfig.NumberOfACL = 0;
+	pBtMgnt->ExtConfig.NumberOfSCO = 0;
+
+	numOfHandle = pcmd[0];
+	/* RT_DISP(FIOCTL, IOCTL_BT_HCICMD_EXT, ("numOfHandle = 0x%x\n", numOfHandle)); */
+	/* RT_DISP(FIOCTL, IOCTL_BT_HCICMD_EXT, ("HCIExtensionVer = %d\n", pBtMgnt->ExtConfig.HCIExtensionVer)); */
+	RTW_INFO("numOfHandle = 0x%x\n", numOfHandle);
+	RTW_INFO("HCIExtensionVer = %d\n", pBtMgnt->ExtConfig.HCIExtensionVer);
+
+	pTriple = &pcmd[1];
+	for (i = 0; i < numOfHandle; i++) {
+		if (pBtMgnt->ExtConfig.HCIExtensionVer < 1) {
+			conHandle = *((u8 *)&pTriple[0]);
+			btProfile = pTriple[2];
+			btCoreSpec = pTriple[3];
+			if (BT_PROFILE_SCO == btProfile)
+				pBtMgnt->ExtConfig.NumberOfSCO++;
+			else {
+				pBtMgnt->ExtConfig.NumberOfACL++;
+				pBtMgnt->ExtConfig.aclLink[i].ConnectHandle = conHandle;
+				pBtMgnt->ExtConfig.aclLink[i].BTProfile = btProfile;
+				pBtMgnt->ExtConfig.aclLink[i].BTCoreSpec = btCoreSpec;
+			}
+			/* RT_DISP(FIOCTL, IOCTL_BT_HCICMD_EXT, */
+			/*	("Connection_Handle=0x%x, BTProfile=%d, BTSpec=%d\n", */
+			/*		conHandle, btProfile, btCoreSpec)); */
+			RTW_INFO("Connection_Handle=0x%x, BTProfile=%d, BTSpec=%d\n", conHandle, btProfile, btCoreSpec);
+			pTriple += 4;
+		} else if (pBtMgnt->ExtConfig.HCIExtensionVer >= 1) {
+			conHandle = *((pu2Byte)&pTriple[0]);
+			btProfile = pTriple[2];
+			btCoreSpec = pTriple[3];
+			linkRole = pTriple[4];
+			if (BT_PROFILE_SCO == btProfile)
+				pBtMgnt->ExtConfig.NumberOfSCO++;
+			else {
+				pBtMgnt->ExtConfig.NumberOfACL++;
+				pBtMgnt->ExtConfig.aclLink[i].ConnectHandle = conHandle;
+				pBtMgnt->ExtConfig.aclLink[i].BTProfile = btProfile;
+				pBtMgnt->ExtConfig.aclLink[i].BTCoreSpec = btCoreSpec;
+				pBtMgnt->ExtConfig.aclLink[i].linkRole = linkRole;
+			}
+			/* RT_DISP(FIOCTL, IOCTL_BT_HCICMD_EXT, */
+			RTW_INFO("Connection_Handle=0x%x, BTProfile=%d, BTSpec=%d, LinkRole=%d\n",
+				 conHandle, btProfile, btCoreSpec, linkRole);
+			pTriple += 5;
+		}
+	}
+	rtw_btcoex_StackUpdateProfileInfo();
+
+	/* send complete event to BT */
+	{
+		pEvent = (rtw_HCI_event *)(&localBuf[0]);
+
+
+		pEvent->EventCode = HCI_EVENT_COMMAND_COMPLETE;
+		pEvent->Data[0] = 0x1;	/* packet # */
+		pEvent->Data[1] = HCIOPCODELOW(HCI_LINK_STATUS_NOTIFY, OGF_EXTENSION);
+		pEvent->Data[2] = HCIOPCODEHIGHT(HCI_LINK_STATUS_NOTIFY, OGF_EXTENSION);
+		len = len + 3;
+
+		/* Return parameters starts from here */
+		pRetPar = &pEvent->Data[len];
+		pRetPar[0] = status;		/* status */
+
+		len++;
+		pEvent->Length = len;
+
+		/* total tx event length + EventCode length + sizeof(length) */
+		tx_event_length = pEvent->Length + 2;
+
+		status = rtw_btcoex_sendmsgbysocket(padapter, (u8 *)pEvent, tx_event_length, _FALSE);
+		return status;
+		/* bthci_IndicateEvent(Adapter, PPacketIrpEvent, len+2); */
+	}
+
+
+}
+
+u8 rtw_btcoex_parse_HCI_BT_coex_notify_cmd(_adapter *padapter, u8 *pcmd, u16 cmdlen)
+{
+	u8 localBuf[6] = "";
+	u8 *pRetPar;
+	u8	len = 0, tx_event_length = 0;
+	rtw_HCI_event *pEvent;
+	RTW_HCI_STATUS	status = HCI_STATUS_SUCCESS;
+
+	{
+		pEvent = (rtw_HCI_event *)(&localBuf[0]);
+
+
+		pEvent->EventCode = HCI_EVENT_COMMAND_COMPLETE;
+		pEvent->Data[0] = 0x1;	/* packet # */
+		pEvent->Data[1] = HCIOPCODELOW(HCI_BT_COEX_NOTIFY, OGF_EXTENSION);
+		pEvent->Data[2] = HCIOPCODEHIGHT(HCI_BT_COEX_NOTIFY, OGF_EXTENSION);
+		len = len + 3;
+
+		/* Return parameters starts from here */
+		pRetPar = &pEvent->Data[len];
+		pRetPar[0] = status;		/* status */
+
+		len++;
+		pEvent->Length = len;
+
+		/* total tx event length + EventCode length + sizeof(length) */
+		tx_event_length = pEvent->Length + 2;
+
+		status = rtw_btcoex_sendmsgbysocket(padapter, (u8 *)pEvent, tx_event_length, _FALSE);
+		return status;
+		/* bthci_IndicateEvent(Adapter, PPacketIrpEvent, len+2); */
+	}
+}
+
+u8 rtw_btcoex_parse_HCI_BT_operation_notify_cmd(_adapter *padapter, u8 *pcmd, u16 cmdlen)
+{
+	u8 localBuf[6] = "";
+	u8 *pRetPar;
+	u8	len = 0, tx_event_length = 0;
+	rtw_HCI_event *pEvent;
+	RTW_HCI_STATUS	status = HCI_STATUS_SUCCESS;
+
+	RTW_INFO("%s, OP code: %d\n", __func__, pcmd[0]);
+
+	switch (pcmd[0]) {
+	case HCI_BT_OP_NONE:
+		RTW_INFO("[bt operation] : Operation None!!\n");
+		break;
+	case HCI_BT_OP_INQUIRY_START:
+		RTW_INFO("[bt operation] : Inquiry start!!\n");
+		break;
+	case HCI_BT_OP_INQUIRY_FINISH:
+		RTW_INFO("[bt operation] : Inquiry finished!!\n");
+		break;
+	case HCI_BT_OP_PAGING_START:
+		RTW_INFO("[bt operation] : Paging is started!!\n");
+		break;
+	case HCI_BT_OP_PAGING_SUCCESS:
+		RTW_INFO("[bt operation] : Paging complete successfully!!\n");
+		break;
+	case HCI_BT_OP_PAGING_UNSUCCESS:
+		RTW_INFO("[bt operation] : Paging complete unsuccessfully!!\n");
+		break;
+	case HCI_BT_OP_PAIRING_START:
+		RTW_INFO("[bt operation] : Pairing start!!\n");
+		break;
+	case HCI_BT_OP_PAIRING_FINISH:
+		RTW_INFO("[bt operation] : Pairing finished!!\n");
+		break;
+	case HCI_BT_OP_BT_DEV_ENABLE:
+		RTW_INFO("[bt operation] : BT Device is enabled!!\n");
+		break;
+	case HCI_BT_OP_BT_DEV_DISABLE:
+		RTW_INFO("[bt operation] : BT Device is disabled!!\n");
+		break;
+	default:
+		RTW_INFO("[bt operation] : Unknown, error!!\n");
+		break;
+	}
+
+	/* send complete event to BT */
+	{
+		pEvent = (rtw_HCI_event *)(&localBuf[0]);
+
+
+		pEvent->EventCode = HCI_EVENT_COMMAND_COMPLETE;
+		pEvent->Data[0] = 0x1;	/* packet # */
+		pEvent->Data[1] = HCIOPCODELOW(HCI_BT_OPERATION_NOTIFY, OGF_EXTENSION);
+		pEvent->Data[2] = HCIOPCODEHIGHT(HCI_BT_OPERATION_NOTIFY, OGF_EXTENSION);
+		len = len + 3;
+
+		/* Return parameters starts from here */
+		pRetPar = &pEvent->Data[len];
+		pRetPar[0] = status;		/* status */
+
+		len++;
+		pEvent->Length = len;
+
+		/* total tx event length + EventCode length + sizeof(length) */
+		tx_event_length = pEvent->Length + 2;
+
+		status = rtw_btcoex_sendmsgbysocket(padapter, (u8 *)pEvent, tx_event_length, _FALSE);
+		return status;
+		/* bthci_IndicateEvent(Adapter, PPacketIrpEvent, len+2); */
+	}
+}
+
+u8 rtw_btcoex_parse_BT_AFH_MAP_notify_cmd(_adapter *padapter, u8 *pcmd, u16 cmdlen)
+{
+	u8 localBuf[6] = "";
+	u8 *pRetPar;
+	u8	len = 0, tx_event_length = 0;
+	rtw_HCI_event *pEvent;
+	RTW_HCI_STATUS	status = HCI_STATUS_SUCCESS;
+
+	{
+		pEvent = (rtw_HCI_event *)(&localBuf[0]);
+
+
+		pEvent->EventCode = HCI_EVENT_COMMAND_COMPLETE;
+		pEvent->Data[0] = 0x1;	/* packet # */
+		pEvent->Data[1] = HCIOPCODELOW(HCI_BT_AFH_MAP_NOTIFY, OGF_EXTENSION);
+		pEvent->Data[2] = HCIOPCODEHIGHT(HCI_BT_AFH_MAP_NOTIFY, OGF_EXTENSION);
+		len = len + 3;
+
+		/* Return parameters starts from here */
+		pRetPar = &pEvent->Data[len];
+		pRetPar[0] = status;		/* status */
+
+		len++;
+		pEvent->Length = len;
+
+		/* total tx event length + EventCode length + sizeof(length) */
+		tx_event_length = pEvent->Length + 2;
+
+		status = rtw_btcoex_sendmsgbysocket(padapter, (u8 *)pEvent, tx_event_length, _FALSE);
+		return status;
+		/* bthci_IndicateEvent(Adapter, PPacketIrpEvent, len+2); */
+	}
+}
+
+u8 rtw_btcoex_parse_BT_register_val_notify_cmd(_adapter *padapter, u8 *pcmd, u16 cmdlen)
+{
+
+	u8 localBuf[6] = "";
+	u8 *pRetPar;
+	u8	len = 0, tx_event_length = 0;
+	rtw_HCI_event *pEvent;
+	RTW_HCI_STATUS	status = HCI_STATUS_SUCCESS;
+
+	{
+		pEvent = (rtw_HCI_event *)(&localBuf[0]);
+
+
+		pEvent->EventCode = HCI_EVENT_COMMAND_COMPLETE;
+		pEvent->Data[0] = 0x1;	/* packet # */
+		pEvent->Data[1] = HCIOPCODELOW(HCI_BT_REGISTER_VALUE_NOTIFY, OGF_EXTENSION);
+		pEvent->Data[2] = HCIOPCODEHIGHT(HCI_BT_REGISTER_VALUE_NOTIFY, OGF_EXTENSION);
+		len = len + 3;
+
+		/* Return parameters starts from here */
+		pRetPar = &pEvent->Data[len];
+		pRetPar[0] = status;		/* status */
+
+		len++;
+		pEvent->Length = len;
+
+		/* total tx event length + EventCode length + sizeof(length) */
+		tx_event_length = pEvent->Length + 2;
+
+		status = rtw_btcoex_sendmsgbysocket(padapter, (u8 *)pEvent, tx_event_length, _FALSE);
+		return status;
+		/* bthci_IndicateEvent(Adapter, PPacketIrpEvent, len+2); */
+	}
+}
+
+u8 rtw_btcoex_parse_HCI_BT_abnormal_notify_cmd(_adapter *padapter, u8 *pcmd, u16 cmdlen)
+{
+	u8 localBuf[6] = "";
+	u8 *pRetPar;
+	u8	len = 0, tx_event_length = 0;
+	rtw_HCI_event *pEvent;
+	RTW_HCI_STATUS	status = HCI_STATUS_SUCCESS;
+
+	{
+		pEvent = (rtw_HCI_event *)(&localBuf[0]);
+
+
+		pEvent->EventCode = HCI_EVENT_COMMAND_COMPLETE;
+		pEvent->Data[0] = 0x1;	/* packet # */
+		pEvent->Data[1] = HCIOPCODELOW(HCI_BT_ABNORMAL_NOTIFY, OGF_EXTENSION);
+		pEvent->Data[2] = HCIOPCODEHIGHT(HCI_BT_ABNORMAL_NOTIFY, OGF_EXTENSION);
+		len = len + 3;
+
+		/* Return parameters starts from here */
+		pRetPar = &pEvent->Data[len];
+		pRetPar[0] = status;		/* status */
+
+		len++;
+		pEvent->Length = len;
+
+		/* total tx event length + EventCode length + sizeof(length) */
+		tx_event_length = pEvent->Length + 2;
+
+		status = rtw_btcoex_sendmsgbysocket(padapter, (u8 *)pEvent, tx_event_length, _FALSE);
+		return status;
+		/* bthci_IndicateEvent(Adapter, PPacketIrpEvent, len+2); */
+	}
+}
+
+u8 rtw_btcoex_parse_HCI_query_RF_status_cmd(_adapter *padapter, u8 *pcmd, u16 cmdlen)
+{
+	u8 localBuf[6] = "";
+	u8 *pRetPar;
+	u8	len = 0, tx_event_length = 0;
+	rtw_HCI_event *pEvent;
+	RTW_HCI_STATUS	status = HCI_STATUS_SUCCESS;
+
+	{
+		pEvent = (rtw_HCI_event *)(&localBuf[0]);
+
+
+		pEvent->EventCode = HCI_EVENT_COMMAND_COMPLETE;
+		pEvent->Data[0] = 0x1;	/* packet # */
+		pEvent->Data[1] = HCIOPCODELOW(HCI_QUERY_RF_STATUS, OGF_EXTENSION);
+		pEvent->Data[2] = HCIOPCODEHIGHT(HCI_QUERY_RF_STATUS, OGF_EXTENSION);
+		len = len + 3;
+
+		/* Return parameters starts from here */
+		pRetPar = &pEvent->Data[len];
+		pRetPar[0] = status;		/* status */
+
+		len++;
+		pEvent->Length = len;
+
+		/* total tx event length + EventCode length + sizeof(length) */
+		tx_event_length = pEvent->Length + 2;
+
+		status = rtw_btcoex_sendmsgbysocket(padapter, (u8 *)pEvent, tx_event_length, _FALSE);
+		return status;
+		/* bthci_IndicateEvent(Adapter, PPacketIrpEvent, len+2); */
+	}
+}
+
+/*****************************************
+* HCI cmd format :
+*| 15 - 0						|
+*| OPcode (OCF|OGF<<10)		|
+*| 15 - 8		|7 - 0			|
+*|Cmd para	|Cmd para Length	|
+*|Cmd para......				|
+******************************************/
+
+/* bit 0  1  2  3  4  5  6  7  8  9 10 11 12 13 14 15
+ *	 |	OCF			             |	   OGF       | */
+void rtw_btcoex_parse_hci_extend_cmd(_adapter *padapter, u8 *pcmd, u16 len, const u16 hci_OCF)
+{
+
+	RTW_INFO("%s: OCF: %x\n", __func__, hci_OCF);
+	switch (hci_OCF) {
+	case HCI_EXTENSION_VERSION_NOTIFY:
+		RTW_INFO("HCI_EXTENSION_VERSION_NOTIFY\n");
+		rtw_btcoex_parse_HCI_Ver_notify_cmd(padapter, pcmd, len);
+		break;
+	case HCI_LINK_STATUS_NOTIFY:
+		RTW_INFO("HCI_LINK_STATUS_NOTIFY\n");
+		rtw_btcoex_parse_HCI_link_status_notify_cmd(padapter, pcmd, len);
+		break;
+	case HCI_BT_OPERATION_NOTIFY:
+		/* only for 8723a 2ant */
+		RTW_INFO("HCI_BT_OPERATION_NOTIFY\n");
+		rtw_btcoex_parse_HCI_BT_operation_notify_cmd(padapter, pcmd, len);
+		/*  */
+		break;
+	case HCI_ENABLE_WIFI_SCAN_NOTIFY:
+		RTW_INFO("HCI_ENABLE_WIFI_SCAN_NOTIFY\n");
+		rtw_btcoex_parse_WIFI_scan_notify_cmd(padapter, pcmd, len);
+		break;
+	case HCI_QUERY_RF_STATUS:
+		/* only for 8723b 2ant */
+		RTW_INFO("HCI_QUERY_RF_STATUS\n");
+		rtw_btcoex_parse_HCI_query_RF_status_cmd(padapter, pcmd, len);
+		break;
+	case HCI_BT_ABNORMAL_NOTIFY:
+		RTW_INFO("HCI_BT_ABNORMAL_NOTIFY\n");
+		rtw_btcoex_parse_HCI_BT_abnormal_notify_cmd(padapter, pcmd, len);
+		break;
+	case HCI_BT_INFO_NOTIFY:
+		RTW_INFO("HCI_BT_INFO_NOTIFY\n");
+		rtw_btcoex_parse_BT_info_notify_cmd(padapter, pcmd, len);
+		break;
+	case HCI_BT_COEX_NOTIFY:
+		RTW_INFO("HCI_BT_COEX_NOTIFY\n");
+		rtw_btcoex_parse_HCI_BT_coex_notify_cmd(padapter, pcmd, len);
+		break;
+	case HCI_BT_PATCH_VERSION_NOTIFY:
+		RTW_INFO("HCI_BT_PATCH_VERSION_NOTIFY\n");
+		rtw_btcoex_parse_BT_patch_ver_info_cmd(padapter, pcmd, len);
+		break;
+	case HCI_BT_AFH_MAP_NOTIFY:
+		RTW_INFO("HCI_BT_AFH_MAP_NOTIFY\n");
+		rtw_btcoex_parse_BT_AFH_MAP_notify_cmd(padapter, pcmd, len);
+		break;
+	case HCI_BT_REGISTER_VALUE_NOTIFY:
+		RTW_INFO("HCI_BT_REGISTER_VALUE_NOTIFY\n");
+		rtw_btcoex_parse_BT_register_val_notify_cmd(padapter, pcmd, len);
+		break;
+	default:
+		RTW_INFO("ERROR!!! Unknown OCF: %x\n", hci_OCF);
+		break;
+
+	}
+}
+
+void rtw_btcoex_parse_hci_cmd(_adapter *padapter, u8 *pcmd, u16 len)
+{
+	u16 opcode = pcmd[0] | pcmd[1] << 8;
+	u16 hci_OGF = HCI_OGF(opcode);
+	u16 hci_OCF = HCI_OCF(opcode);
+	u8 cmdlen = len - 3;
+	u8 pare_len = pcmd[2];
+
+	RTW_INFO("%s OGF: %x,OCF: %x\n", __func__, hci_OGF, hci_OCF);
+	switch (hci_OGF) {
+	case OGF_EXTENSION:
+		RTW_INFO("HCI_EXTENSION_CMD_OGF\n");
+		rtw_btcoex_parse_hci_extend_cmd(padapter, &pcmd[3], cmdlen, hci_OCF);
+		break;
+	default:
+		RTW_INFO("Other OGF: %x\n", hci_OGF);
+		break;
+	}
+}
+
+u16 rtw_btcoex_parse_recv_data(u8 *msg, u8 msg_size)
+{
+	u8 cmp_msg1[32] = attend_ack;
+	u8 cmp_msg2[32] = leave_ack;
+	u8 cmp_msg3[32] = bt_leave;
+	u8 cmp_msg4[32] = invite_req;
+	u8 cmp_msg5[32] = attend_req;
+	u8 cmp_msg6[32] = invite_rsp;
+	u8 res = OTHER;
+
+	if (_rtw_memcmp(cmp_msg1, msg, msg_size) == _TRUE) {
+		/*RTW_INFO("%s, msg:%s\n",__func__,msg);*/
+		res = RX_ATTEND_ACK;
+	} else if (_rtw_memcmp(cmp_msg2, msg, msg_size) == _TRUE) {
+		/*RTW_INFO("%s, msg:%s\n",__func__,msg);*/
+		res = RX_LEAVE_ACK;
+	} else if (_rtw_memcmp(cmp_msg3, msg, msg_size) == _TRUE) {
+		/*RTW_INFO("%s, msg:%s\n",__func__,msg);*/
+		res = RX_BT_LEAVE;
+	} else if (_rtw_memcmp(cmp_msg4, msg, msg_size) == _TRUE) {
+		/*RTW_INFO("%s, msg:%s\n",__func__,msg);*/
+		res = RX_INVITE_REQ;
+	} else if (_rtw_memcmp(cmp_msg5, msg, msg_size) == _TRUE)
+		res = RX_ATTEND_REQ;
+	else if (_rtw_memcmp(cmp_msg6, msg, msg_size) == _TRUE)
+		res = RX_INVITE_RSP;
+	else {
+		/*RTW_INFO("%s, %s\n", __func__, msg);*/
+		res = OTHER;
+	}
+
+	/*RTW_INFO("%s, res:%d\n", __func__, res);*/
+
+	return res;
+}
+
+void rtw_btcoex_recvmsgbysocket(void *data)
+{
+	u8 recv_data[255];
+	u8 tx_msg[255] = leave_ack;
+	u32 len = 0;
+	u16 recv_length = 0;
+	u16 parse_res = 0;
+#if 0
+	u8 para_len = 0, polling_enable = 0, poling_interval = 0, reason = 0, btinfo_len = 0;
+	u8 btinfo[BT_INFO_LEN] = {0};
+#endif
+
+	struct bt_coex_info *pcoex_info = NULL;
+	struct sock *sk = NULL;
+	struct sk_buff *skb = NULL;
+
+	/*RTW_INFO("%s\n",__func__);*/
+
+	if (pbtcoexadapter == NULL) {
+		RTW_INFO("%s: btcoexadapter NULL!\n", __func__);
+		return;
+	}
+
+	pcoex_info = &pbtcoexadapter->coex_info;
+	sk = pcoex_info->sk_store;
+
+	if (sk == NULL) {
+		RTW_INFO("%s: critical error when receive socket data!\n", __func__);
+		return;
+	}
+
+	len = skb_queue_len(&sk->sk_receive_queue);
+	while (len > 0) {
+		skb = skb_dequeue(&sk->sk_receive_queue);
+
+		/*important: cut the udp header from skb->data! header length is 8 byte*/
+		recv_length = skb->len - 8;
+		_rtw_memset(recv_data, 0, sizeof(recv_data));
+		_rtw_memcpy(recv_data, skb->data + 8, recv_length);
+
+		parse_res = rtw_btcoex_parse_recv_data(recv_data, recv_length);
+#if 0
+		if (RX_ATTEND_ACK == parse_res) {
+			/* attend ack */
+			pcoex_info->BT_attend = _TRUE;
+			RTW_INFO("RX_ATTEND_ACK!,sock_open:%d, BT_attend:%d\n", pcoex_info->sock_open, pcoex_info->BT_attend);
+		} else if (RX_ATTEND_REQ == parse_res) {
+			/* attend req from BT */
+			pcoex_info->BT_attend = _TRUE;
+			RTW_INFO("RX_BT_ATTEND_REQ!,sock_open:%d, BT_attend:%d\n", pcoex_info->sock_open, pcoex_info->BT_attend);
+			rtw_btcoex_sendmsgbysocket(pbtcoexadapter, attend_ack, sizeof(attend_ack), _FALSE);
+		} else if (RX_INVITE_REQ == parse_res) {
+			/* invite req from BT */
+			pcoex_info->BT_attend = _TRUE;
+			RTW_INFO("RX_INVITE_REQ!,sock_open:%d, BT_attend:%d\n", pcoex_info->sock_open, pcoex_info->BT_attend);
+			rtw_btcoex_sendmsgbysocket(pbtcoexadapter, invite_rsp, sizeof(invite_rsp), _FALSE);
+		} else if (RX_INVITE_RSP == parse_res) {
+			/* invite rsp */
+			pcoex_info->BT_attend = _TRUE;
+			RTW_INFO("RX_INVITE_RSP!,sock_open:%d, BT_attend:%d\n", pcoex_info->sock_open, pcoex_info->BT_attend);
+		} else if (RX_LEAVE_ACK == parse_res) {
+			/* mean BT know wifi  will leave */
+			pcoex_info->BT_attend = _FALSE;
+			RTW_INFO("RX_LEAVE_ACK!,sock_open:%d, BT_attend:%d\n", pcoex_info->sock_open, pcoex_info->BT_attend);
+		} else if (RX_BT_LEAVE == parse_res) {
+			/* BT leave */
+			rtw_btcoex_sendmsgbysocket(pbtcoexadapter, leave_ack, sizeof(leave_ack), _FALSE); /*  no ack */
+			pcoex_info->BT_attend = _FALSE;
+			RTW_INFO("RX_BT_LEAVE!sock_open:%d, BT_attend:%d\n", pcoex_info->sock_open, pcoex_info->BT_attend);
+		} else {
+			/* todo: check if recv data are really hci cmds */
+			if (_TRUE == pcoex_info->BT_attend)
+				rtw_btcoex_parse_hci_cmd(pbtcoexadapter, recv_data, recv_length);
+		}
+#endif
+		switch (parse_res) {
+		case RX_ATTEND_ACK:
+			/* attend ack */
+			pcoex_info->BT_attend = _TRUE;
+			RTW_INFO("RX_ATTEND_ACK!,sock_open:%d, BT_attend:%d\n", pcoex_info->sock_open, pcoex_info->BT_attend);
+			rtw_btcoex_pta_off_on_notify(pbtcoexadapter, pcoex_info->BT_attend);
+			break;
+
+		case RX_ATTEND_REQ:
+			pcoex_info->BT_attend = _TRUE;
+			RTW_INFO("RX_BT_ATTEND_REQ!,sock_open:%d, BT_attend:%d\n", pcoex_info->sock_open, pcoex_info->BT_attend);
+			rtw_btcoex_sendmsgbysocket(pbtcoexadapter, attend_ack, sizeof(attend_ack), _FALSE);
+			rtw_btcoex_pta_off_on_notify(pbtcoexadapter, pcoex_info->BT_attend);
+			break;
+
+		case RX_INVITE_REQ:
+			/* invite req from BT */
+			pcoex_info->BT_attend = _TRUE;
+			RTW_INFO("RX_INVITE_REQ!,sock_open:%d, BT_attend:%d\n", pcoex_info->sock_open, pcoex_info->BT_attend);
+			rtw_btcoex_sendmsgbysocket(pbtcoexadapter, invite_rsp, sizeof(invite_rsp), _FALSE);
+			rtw_btcoex_pta_off_on_notify(pbtcoexadapter, pcoex_info->BT_attend);
+			break;
+
+		case RX_INVITE_RSP:
+			/*invite rsp*/
+			pcoex_info->BT_attend = _TRUE;
+			RTW_INFO("RX_INVITE_RSP!,sock_open:%d, BT_attend:%d\n", pcoex_info->sock_open, pcoex_info->BT_attend);
+			rtw_btcoex_pta_off_on_notify(pbtcoexadapter, pcoex_info->BT_attend);
+			break;
+
+		case RX_LEAVE_ACK:
+			/* mean BT know wifi  will leave */
+			pcoex_info->BT_attend = _FALSE;
+			RTW_INFO("RX_LEAVE_ACK!,sock_open:%d, BT_attend:%d\n", pcoex_info->sock_open, pcoex_info->BT_attend);
+			rtw_btcoex_pta_off_on_notify(pbtcoexadapter, pcoex_info->BT_attend);
+			break;
+
+		case RX_BT_LEAVE:
+			/* BT leave */
+			rtw_btcoex_sendmsgbysocket(pbtcoexadapter, leave_ack, sizeof(leave_ack), _FALSE); /* no ack */
+			pcoex_info->BT_attend = _FALSE;
+			RTW_INFO("RX_BT_LEAVE!sock_open:%d, BT_attend:%d\n", pcoex_info->sock_open, pcoex_info->BT_attend);
+			rtw_btcoex_pta_off_on_notify(pbtcoexadapter, pcoex_info->BT_attend);
+			break;
+
+		default:
+			if (_TRUE == pcoex_info->BT_attend)
+				rtw_btcoex_parse_hci_cmd(pbtcoexadapter, recv_data, recv_length);
+			else
+				RTW_INFO("ERROR!! BT is UP\n");
+			break;
+
+		}
+
+		len--;
+		kfree_skb(skb);
+	}
+}
+
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 15, 0))
+	void rtw_btcoex_recvmsg_init(struct sock *sk_in, s32 bytes)
+#else
+	void rtw_btcoex_recvmsg_init(struct sock *sk_in)
+#endif
+{
+	struct bt_coex_info *pcoex_info = NULL;
+
+	if (pbtcoexadapter == NULL) {
+		RTW_INFO("%s: btcoexadapter NULL\n", __func__);
+		return;
+	}
+	pcoex_info = &pbtcoexadapter->coex_info;
+	pcoex_info->sk_store = sk_in;
+	if (pcoex_info->btcoex_wq != NULL)
+		queue_delayed_work(pcoex_info->btcoex_wq, &pcoex_info->recvmsg_work, 0);
+	else
+		RTW_INFO("%s: BTCOEX workqueue NULL\n", __func__);
+}
+
+u8 rtw_btcoex_sendmsgbysocket(_adapter *padapter, u8 *msg, u8 msg_size, bool force)
+{
+	u8 error;
+	struct msghdr	udpmsg;
+	mm_segment_t	oldfs;
+	struct iovec	iov;
+	struct bt_coex_info *pcoex_info = &padapter->coex_info;
+
+	/* RTW_INFO("%s: msg:%s, force:%s\n", __func__, msg, force == _TRUE?"TRUE":"FALSE"); */
+	if (_FALSE == force) {
+		if (_FALSE == pcoex_info->BT_attend) {
+			RTW_INFO("TX Blocked: WiFi-BT disconnected\n");
+			return _FAIL;
+		}
+	}
+
+	iov.iov_base	 = (void *)msg;
+	iov.iov_len	 = msg_size;
+	udpmsg.msg_name	 = &pcoex_info->bt_sockaddr;
+	udpmsg.msg_namelen	= sizeof(struct sockaddr_in);
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 19, 0))
+	/* referece:sock_xmit in kernel code
+	 * WRITE for sock_sendmsg, READ for sock_recvmsg
+	 * third parameter for msg_iovlen
+	 * last parameter for iov_len
+	 */
+	iov_iter_init(&udpmsg.msg_iter, WRITE, &iov, 1, msg_size);
+#else
+	udpmsg.msg_iov	 = &iov;
+	udpmsg.msg_iovlen	= 1;
+#endif
+	udpmsg.msg_control	= NULL;
+	udpmsg.msg_controllen = 0;
+	udpmsg.msg_flags	= MSG_DONTWAIT | MSG_NOSIGNAL;
+	oldfs = get_fs();
+	set_fs(KERNEL_DS);
+
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 1, 0))
+	error = sock_sendmsg(pcoex_info->udpsock, &udpmsg);
+#else
+	error = sock_sendmsg(pcoex_info->udpsock, &udpmsg, msg_size);
+#endif
+	set_fs(oldfs);
+	if (error < 0) {
+		RTW_INFO("Error when sendimg msg, error:%d\n", error);
+		return _FAIL;
+	} else
+		return _SUCCESS;
+}
+
+u8 rtw_btcoex_create_kernel_socket(_adapter *padapter)
+{
+	s8 kernel_socket_err;
+	u8 tx_msg[255] = attend_req;
+	struct bt_coex_info *pcoex_info = &padapter->coex_info;
+	s32 sock_reuse = 1;
+	u8 status = _FAIL;
+
+	RTW_INFO("%s CONNECT_PORT %d\n", __func__, CONNECT_PORT);
+
+	if (NULL == pcoex_info) {
+		RTW_INFO("coex_info: NULL\n");
+		status =  _FAIL;
+	}
+
+	kernel_socket_err = sock_create(PF_INET, SOCK_DGRAM, 0, &pcoex_info->udpsock);
+
+	if (kernel_socket_err < 0) {
+		RTW_INFO("Error during creation of socket error:%d\n", kernel_socket_err);
+		status = _FAIL;
+	} else {
+		_rtw_memset(&(pcoex_info->wifi_sockaddr), 0, sizeof(pcoex_info->wifi_sockaddr));
+		pcoex_info->wifi_sockaddr.sin_family = AF_INET;
+		pcoex_info->wifi_sockaddr.sin_port = htons(CONNECT_PORT);
+		pcoex_info->wifi_sockaddr.sin_addr.s_addr = htonl(INADDR_LOOPBACK);
+
+		_rtw_memset(&(pcoex_info->bt_sockaddr), 0, sizeof(pcoex_info->bt_sockaddr));
+		pcoex_info->bt_sockaddr.sin_family = AF_INET;
+		pcoex_info->bt_sockaddr.sin_port = htons(CONNECT_PORT_BT);
+		pcoex_info->bt_sockaddr.sin_addr.s_addr = htonl(INADDR_LOOPBACK);
+
+		pcoex_info->sk_store = NULL;
+		kernel_socket_err = pcoex_info->udpsock->ops->bind(pcoex_info->udpsock, (struct sockaddr *)&pcoex_info->wifi_sockaddr,
+				    sizeof(pcoex_info->wifi_sockaddr));
+		if (kernel_socket_err == 0) {
+			RTW_INFO("binding socket success\n");
+			pcoex_info->udpsock->sk->sk_data_ready = rtw_btcoex_recvmsg_init;
+			pcoex_info->sock_open |=  KERNEL_SOCKET_OK;
+			pcoex_info->BT_attend = _FALSE;
+			RTW_INFO("WIFI sending attend_req\n");
+			rtw_btcoex_sendmsgbysocket(padapter, attend_req, sizeof(attend_req), _TRUE);
+			status = _SUCCESS;
+		} else {
+			pcoex_info->BT_attend = _FALSE;
+			sock_release(pcoex_info->udpsock); /* bind fail release socket */
+			RTW_INFO("Error binding socket: %d\n", kernel_socket_err);
+			status = _FAIL;
+		}
+
+	}
+
+	return status;
+}
+
+void rtw_btcoex_close_kernel_socket(_adapter *padapter)
+{
+	struct bt_coex_info *pcoex_info = &padapter->coex_info;
+	if (pcoex_info->sock_open & KERNEL_SOCKET_OK) {
+		RTW_INFO("release kernel socket\n");
+		sock_release(pcoex_info->udpsock);
+		pcoex_info->sock_open &= ~(KERNEL_SOCKET_OK);
+		if (_TRUE == pcoex_info->BT_attend)
+			pcoex_info->BT_attend = _FALSE;
+
+		RTW_INFO("sock_open:%d, BT_attend:%d\n", pcoex_info->sock_open, pcoex_info->BT_attend);
+	}
+}
+
+void rtw_btcoex_init_socket(_adapter *padapter)
+{
+
+	u8 is_invite = _FALSE;
+	struct bt_coex_info *pcoex_info = &padapter->coex_info;
+	RTW_INFO("%s\n", __func__);
+	if (_FALSE == pcoex_info->is_exist) {
+		_rtw_memset(pcoex_info, 0, sizeof(struct bt_coex_info));
+		pcoex_info->btcoex_wq = create_workqueue("BTCOEX");
+		INIT_DELAYED_WORK(&pcoex_info->recvmsg_work,
+				  (void *)rtw_btcoex_recvmsgbysocket);
+		pbtcoexadapter = padapter;
+		/* We expect BT is off if BT don't send ack to wifi */
+		RTW_INFO("We expect BT is off if BT send ack to wifi\n");
+		rtw_btcoex_pta_off_on_notify(pbtcoexadapter, _FALSE);
+		if (rtw_btcoex_create_kernel_socket(padapter) == _SUCCESS)
+			pcoex_info->is_exist = _TRUE;
+		else {
+			pcoex_info->is_exist = _FALSE;
+			pbtcoexadapter = NULL;
+		}
+
+		RTW_INFO("%s: pbtcoexadapter:%p, coex_info->is_exist: %s\n"
+			, __func__, pbtcoexadapter, pcoex_info->is_exist == _TRUE ? "TRUE" : "FALSE");
+	}
+}
+
+void rtw_btcoex_close_socket(_adapter *padapter)
+{
+	struct bt_coex_info *pcoex_info = &padapter->coex_info;
+
+	RTW_INFO("%s--coex_info->is_exist: %s, pcoex_info->BT_attend:%s\n"
+		, __func__, pcoex_info->is_exist == _TRUE ? "TRUE" : "FALSE", pcoex_info->BT_attend == _TRUE ? "TRUE" : "FALSE");
+
+	if (_TRUE == pcoex_info->is_exist) {
+		if (_TRUE == pcoex_info->BT_attend) {
+			/*inform BT wifi leave*/
+			rtw_btcoex_sendmsgbysocket(padapter, wifi_leave, sizeof(wifi_leave), _FALSE);
+			msleep(50);
+		}
+
+		if (pcoex_info->btcoex_wq != NULL) {
+			flush_workqueue(pcoex_info->btcoex_wq);
+			destroy_workqueue(pcoex_info->btcoex_wq);
+		}
+
+		rtw_btcoex_close_kernel_socket(padapter);
+		pbtcoexadapter = NULL;
+		pcoex_info->is_exist = _FALSE;
+	}
+}
+
+void rtw_btcoex_dump_tx_msg(u8 *tx_msg, u8 len, u8 *msg_name)
+{
+	u8	i = 0;
+	RTW_INFO("======> Msg name: %s\n", msg_name);
+	for (i = 0; i < len; i++)
+		printk("%02x ", tx_msg[i]);
+	printk("\n");
+	RTW_INFO("Msg name: %s <======\n", msg_name);
+}
+
+/* Porting from Windows team */
+void rtw_btcoex_SendEventExtBtCoexControl(PADAPTER padapter, u8 bNeedDbgRsp, u8 dataLen, void *pData)
+{
+	u8			len = 0, tx_event_length = 0;
+	u8 			localBuf[32] = "";
+	u8			*pRetPar;
+	u8			opCode = 0;
+	u8			*pInBuf = (pu1Byte)pData;
+	u8			*pOpCodeContent;
+	rtw_HCI_event *pEvent;
+
+	opCode = pInBuf[0];
+
+	RTW_INFO("%s, OPCode:%02x\n", __func__, opCode);
+
+	pEvent = (rtw_HCI_event *)(&localBuf[0]);
+
+	/* len += bthci_ExtensionEventHeaderRtk(&localBuf[0], */
+	/*	HCI_EVENT_EXT_BT_COEX_CONTROL); */
+	pEvent->EventCode = HCI_EVENT_EXTENSION_RTK;
+	pEvent->Data[0] = HCI_EVENT_EXT_BT_COEX_CONTROL;	/* extension event code */
+	len++;
+
+	/* Return parameters starts from here */
+	pRetPar = &pEvent->Data[len];
+	_rtw_memcpy(&pRetPar[0], pData, dataLen);
+
+	len += dataLen;
+
+	pEvent->Length = len;
+
+	/* total tx event length + EventCode length + sizeof(length) */
+	tx_event_length = pEvent->Length + 2;
+#if 0
+	rtw_btcoex_dump_tx_msg((u8 *)pEvent, tx_event_length, "BT COEX CONTROL", _FALSE);
+#endif
+	rtw_btcoex_sendmsgbysocket(padapter, (u8 *)pEvent, tx_event_length, _FALSE);
+
+}
+
+/* Porting from Windows team */
+void rtw_btcoex_SendEventExtBtInfoControl(PADAPTER padapter, u8 dataLen, void *pData)
+{
+	rtw_HCI_event *pEvent;
+	u8			*pRetPar;
+	u8			len = 0, tx_event_length = 0;
+	u8 			localBuf[32] = "";
+
+	struct bt_coex_info *pcoex_info = &padapter->coex_info;
+	PBT_MGNT		pBtMgnt = &pcoex_info->BtMgnt;
+
+	/* RTW_INFO("%s\n",__func__);*/
+	if (pBtMgnt->ExtConfig.HCIExtensionVer < 4) { /* not support */
+		RTW_INFO("ERROR: HCIExtensionVer = %d, HCIExtensionVer<4 !!!!\n", pBtMgnt->ExtConfig.HCIExtensionVer);
+		return;
+	}
+
+	pEvent = (rtw_HCI_event *)(&localBuf[0]);
+
+	/* len += bthci_ExtensionEventHeaderRtk(&localBuf[0], */
+	/*		HCI_EVENT_EXT_BT_INFO_CONTROL); */
+	pEvent->EventCode = HCI_EVENT_EXTENSION_RTK;
+	pEvent->Data[0] = HCI_EVENT_EXT_BT_INFO_CONTROL;		/* extension event code */
+	len++;
+
+	/* Return parameters starts from here */
+	pRetPar = &pEvent->Data[len];
+	_rtw_memcpy(&pRetPar[0], pData, dataLen);
+
+	len += dataLen;
+
+	pEvent->Length = len;
+
+	/* total tx event length + EventCode length + sizeof(length) */
+	tx_event_length = pEvent->Length + 2;
+#if 0
+	rtw_btcoex_dump_tx_msg((u8 *)pEvent, tx_event_length, "BT INFO CONTROL");
+#endif
+	rtw_btcoex_sendmsgbysocket(padapter, (u8 *)pEvent, tx_event_length, _FALSE);
+
+}
+
+void rtw_btcoex_SendScanNotify(PADAPTER padapter, u8 scanType)
+{
+	u8	len = 0, tx_event_length = 0;
+	u8 	localBuf[7] = "";
+	u8	*pRetPar;
+	u8	*pu1Temp;
+	rtw_HCI_event *pEvent;
+	struct bt_coex_info *pcoex_info = &padapter->coex_info;
+	PBT_MGNT		pBtMgnt = &pcoex_info->BtMgnt;
+
+	/*	if(!pBtMgnt->BtOperationOn)
+	 *		return; */
+
+	pEvent = (rtw_HCI_event *)(&localBuf[0]);
+
+	/*	len += bthci_ExtensionEventHeaderRtk(&localBuf[0],
+	 *			HCI_EVENT_EXT_WIFI_SCAN_NOTIFY); */
+
+	pEvent->EventCode = HCI_EVENT_EXTENSION_RTK;
+	pEvent->Data[0] = HCI_EVENT_EXT_WIFI_SCAN_NOTIFY;		/* extension event code */
+	len++;
+
+	/* Return parameters starts from here */
+	/* pRetPar = &PPacketIrpEvent->Data[len]; */
+	/* pu1Temp = (u8 *)&pRetPar[0]; */
+	/* *pu1Temp = scanType; */
+	pEvent->Data[len] = scanType;
+	len += 1;
+
+	pEvent->Length = len;
+
+	/* total tx event length + EventCode length + sizeof(length) */
+	tx_event_length = pEvent->Length + 2;
+#if 0
+	rtw_btcoex_dump_tx_msg((u8 *)pEvent, tx_event_length, "WIFI SCAN OPERATION");
+#endif
+	rtw_btcoex_sendmsgbysocket(padapter, (u8 *)pEvent, tx_event_length, _FALSE);
+}
+#endif /* CONFIG_BT_COEXIST_SOCKET_TRX */
+#endif /* CONFIG_BT_COEXIST */
+
+void rtw_btcoex_set_ant_info(PADAPTER padapter)
+{
+#ifdef CONFIG_BT_COEXIST
+	PHAL_DATA_TYPE hal = GET_HAL_DATA(padapter);
+
+	if (hal->EEPROMBluetoothCoexist == _TRUE) {
+		u8 bMacPwrCtrlOn = _FALSE;
+
+		rtw_btcoex_AntInfoSetting(padapter);
+		rtw_hal_get_hwreg(padapter, HW_VAR_APFM_ON_MAC, &bMacPwrCtrlOn);
+		if (bMacPwrCtrlOn == _TRUE)
+			rtw_btcoex_PowerOnSetting(padapter);
+	}
+	else
+#endif
+		rtw_btcoex_wifionly_AntInfoSetting(padapter);
+}
+
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/core/rtw_btcoex_wifionly.c linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/core/rtw_btcoex_wifionly.c
--- linux-5.6.3/3rdparty/rtl8821ce/core/rtw_btcoex_wifionly.c	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/core/rtw_btcoex_wifionly.c	2020-04-10 16:35:06.771657967 +0300
@@ -0,0 +1,47 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2013 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#include <drv_types.h>
+#include <hal_btcoex_wifionly.h>
+#include <hal_data.h>
+
+void rtw_btcoex_wifionly_switchband_notify(PADAPTER padapter)
+{
+	hal_btcoex_wifionly_switchband_notify(padapter);
+}
+
+void rtw_btcoex_wifionly_scan_notify(PADAPTER padapter)
+{
+	hal_btcoex_wifionly_scan_notify(padapter);
+}
+
+void rtw_btcoex_wifionly_connect_notify(PADAPTER padapter)
+{
+	hal_btcoex_wifionly_connect_notify(padapter);
+}
+
+void rtw_btcoex_wifionly_hw_config(PADAPTER padapter)
+{
+	hal_btcoex_wifionly_hw_config(padapter);
+}
+
+void rtw_btcoex_wifionly_initialize(PADAPTER padapter)
+{
+	hal_btcoex_wifionly_initlizevariables(padapter);
+}
+
+void rtw_btcoex_wifionly_AntInfoSetting(PADAPTER padapter)
+{
+	hal_btcoex_wifionly_AntInfoSetting(padapter);
+}
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/core/rtw_bt_mp.c linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/core/rtw_bt_mp.c
--- linux-5.6.3/3rdparty/rtl8821ce/core/rtw_bt_mp.c	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/core/rtw_bt_mp.c	2020-04-10 16:35:06.771657967 +0300
@@ -0,0 +1,1575 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+
+
+#include <drv_types.h>
+#include <rtw_bt_mp.h>
+
+#if defined(CONFIG_RTL8723B)
+	#include <rtl8723b_hal.h>
+#endif
+
+#if defined(CONFIG_RTL8723B) || defined(CONFIG_RTL8821A)
+void MPh2c_timeout_handle(void *FunctionContext)
+{
+	PADAPTER pAdapter;
+	PMPT_CONTEXT pMptCtx;
+
+
+	RTW_INFO("[MPT], MPh2c_timeout_handle\n");
+
+	pAdapter = (PADAPTER)FunctionContext;
+	pMptCtx = &pAdapter->mppriv.mpt_ctx;
+
+	pMptCtx->bMPh2c_timeout = _TRUE;
+
+	if ((_FALSE == pMptCtx->MptH2cRspEvent)
+	    || ((_TRUE == pMptCtx->MptH2cRspEvent)
+		&& (_FALSE == pMptCtx->MptBtC2hEvent)))
+		_rtw_up_sema(&pMptCtx->MPh2c_Sema);
+}
+
+u32 WaitC2Hevent(PADAPTER pAdapter, u8 *C2H_event, u32 delay_time)
+{
+	PMPT_CONTEXT		pMptCtx = &(pAdapter->mppriv.mpt_ctx);
+	pMptCtx->bMPh2c_timeout = _FALSE;
+
+	if (pAdapter->registrypriv.mp_mode == 0) {
+		RTW_INFO("[MPT], Error!! WaitC2Hevent mp_mode == 0!!\n");
+		return _FALSE;
+	}
+
+	_set_timer(&pMptCtx->MPh2c_timeout_timer, delay_time);
+
+	_rtw_down_sema(&pMptCtx->MPh2c_Sema);
+
+	if (pMptCtx->bMPh2c_timeout == _TRUE) {
+		*C2H_event = _FALSE;
+
+		return _FALSE;
+	}
+
+	/* for safty, cancel timer here again */
+	_cancel_timer_ex(&pMptCtx->MPh2c_timeout_timer);
+
+	return _TRUE;
+}
+
+BT_CTRL_STATUS
+mptbt_CheckC2hFrame(
+	PADAPTER		Adapter,
+	PBT_H2C			pH2c,
+	PBT_EXT_C2H		pExtC2h
+)
+{
+	BT_CTRL_STATUS	c2hStatus = BT_STATUS_C2H_SUCCESS;
+
+	/* RTW_INFO("[MPT], MPT rsp C2H hex: %x %x %x  %x %x %x\n"), pExtC2h , pExtC2h+1 ,pExtC2h+2 ,pExtC2h+3 ,pExtC2h+4 ,pExtC2h+5); */
+
+	RTW_INFO("[MPT], statusCode = 0x%x\n", pExtC2h->statusCode);
+	RTW_INFO("[MPT], retLen = %d\n", pExtC2h->retLen);
+	RTW_INFO("[MPT], opCodeVer : req/rsp=%d/%d\n", pH2c->opCodeVer, pExtC2h->opCodeVer);
+	RTW_INFO("[MPT], reqNum : req/rsp=%d/%d\n", pH2c->reqNum, pExtC2h->reqNum);
+	if (pExtC2h->reqNum != pH2c->reqNum) {
+		c2hStatus = BT_STATUS_C2H_REQNUM_MISMATCH;
+		RTW_INFO("[MPT], Error!! C2H reqNum Mismatch!!\n");
+	} else if (pExtC2h->opCodeVer != pH2c->opCodeVer) {
+		c2hStatus = BT_STATUS_OPCODE_L_VERSION_MISMATCH;
+		RTW_INFO("[MPT], Error!! OPCode version L mismatch!!\n");
+	}
+
+	return c2hStatus;
+}
+
+BT_CTRL_STATUS
+mptbt_SendH2c(
+	PADAPTER	Adapter,
+	PBT_H2C	pH2c,
+	u2Byte		h2cCmdLen
+)
+{
+	/* KIRQL				OldIrql = KeGetCurrentIrql(); */
+	BT_CTRL_STATUS	h2cStatus = BT_STATUS_H2C_SUCCESS;
+	PMPT_CONTEXT		pMptCtx = &(Adapter->mppriv.mpt_ctx);
+	u1Byte				i;
+
+	RTW_INFO("[MPT], mptbt_SendH2c()=========>\n");
+
+	/* PlatformResetEvent(&pMptCtx->MptH2cRspEvent); */
+	/* PlatformResetEvent(&pMptCtx->MptBtC2hEvent); */
+
+	/*	if(OldIrql == PASSIVE_LEVEL)
+	 *	{ */
+	/* RTPRINT_DATA(FMPBT, FMPBT_H2C_CONTENT, ("[MPT], MPT H2C hex:\n"), pH2c, h2cCmdLen); */
+
+	for (i = 0; i < BT_H2C_MAX_RETRY; i++) {
+		RTW_INFO("[MPT], Send H2C command to wifi!!!\n");
+
+		pMptCtx->MptH2cRspEvent = _FALSE;
+		pMptCtx->MptBtC2hEvent = _FALSE;
+
+#if defined(CONFIG_RTL8723B)
+		rtl8723b_set_FwBtMpOper_cmd(Adapter, pH2c->opCode, pH2c->opCodeVer, pH2c->reqNum, pH2c->buf);
+#endif
+		pMptCtx->h2cReqNum++;
+		pMptCtx->h2cReqNum %= 16;
+
+		if (WaitC2Hevent(Adapter, &pMptCtx->MptH2cRspEvent, 100)) {
+			RTW_INFO("[MPT], Received WiFi MptH2cRspEvent!!!\n");
+			if (WaitC2Hevent(Adapter, &pMptCtx->MptBtC2hEvent, 400)) {
+				RTW_INFO("[MPT], Received MptBtC2hEvent!!!\n");
+				break;
+			} else {
+				RTW_INFO("[MPT], Error!!BT MptBtC2hEvent timeout!!\n");
+				h2cStatus = BT_STATUS_H2C_BT_NO_RSP;
+			}
+		} else {
+			RTW_INFO("[MPT], Error!!WiFi  MptH2cRspEvent timeout!!\n");
+			h2cStatus = BT_STATUS_H2C_TIMTOUT;
+		}
+	}
+	/*	}
+	 *	else
+	 *	{
+	 * 		RT_ASSERT(FALSE, ("[MPT],  mptbt_SendH2c() can only run under PASSIVE_LEVEL!!\n"));
+	 *		h2cStatus = BT_STATUS_WRONG_LEVEL;
+	 *	} */
+
+	RTW_INFO("[MPT], mptbt_SendH2c()<=========\n");
+	return h2cStatus;
+}
+
+
+
+BT_CTRL_STATUS
+mptbt_CheckBtRspStatus(
+	PADAPTER			Adapter,
+	PBT_EXT_C2H			pExtC2h
+)
+{
+	BT_CTRL_STATUS	retStatus = BT_OP_STATUS_SUCCESS;
+
+	switch (pExtC2h->statusCode) {
+	case BT_OP_STATUS_SUCCESS:
+		retStatus = BT_STATUS_BT_OP_SUCCESS;
+		RTW_INFO("[MPT], BT status : BT_STATUS_SUCCESS\n");
+		break;
+	case BT_OP_STATUS_VERSION_MISMATCH:
+		retStatus = BT_STATUS_OPCODE_L_VERSION_MISMATCH;
+		RTW_INFO("[MPT], BT status : BT_STATUS_OPCODE_L_VERSION_MISMATCH\n");
+		break;
+	case BT_OP_STATUS_UNKNOWN_OPCODE:
+		retStatus = BT_STATUS_UNKNOWN_OPCODE_L;
+		RTW_INFO("[MPT], BT status : BT_STATUS_UNKNOWN_OPCODE_L\n");
+		break;
+	case BT_OP_STATUS_ERROR_PARAMETER:
+		retStatus = BT_STATUS_PARAMETER_FORMAT_ERROR_L;
+		RTW_INFO("[MPT], BT status : BT_STATUS_PARAMETER_FORMAT_ERROR_L\n");
+		break;
+	default:
+		retStatus = BT_STATUS_UNKNOWN_STATUS_L;
+		RTW_INFO("[MPT], BT status : BT_STATUS_UNKNOWN_STATUS_L\n");
+		break;
+	}
+
+	return retStatus;
+}
+
+
+
+BT_CTRL_STATUS
+mptbt_BtFwOpCodeProcess(
+	PADAPTER		Adapter,
+	u1Byte			btFwOpCode,
+	u1Byte			opCodeVer,
+	pu1Byte			pH2cPar,
+	u1Byte			h2cParaLen
+)
+{
+	u1Byte				H2C_Parameter[6] = {0};
+	PBT_H2C				pH2c = (PBT_H2C)&H2C_Parameter[0];
+	PMPT_CONTEXT		pMptCtx = &(Adapter->mppriv.mpt_ctx);
+	PBT_EXT_C2H			pExtC2h = (PBT_EXT_C2H)&pMptCtx->c2hBuf[0];
+	u2Byte				paraLen = 0, i;
+	BT_CTRL_STATUS	h2cStatus = BT_STATUS_H2C_SUCCESS, c2hStatus = BT_STATUS_C2H_SUCCESS;
+	BT_CTRL_STATUS	retStatus = BT_STATUS_H2C_BT_NO_RSP;
+
+	if (Adapter->registrypriv.mp_mode == 0) {
+		RTW_INFO("[MPT], Error!! mptbt_BtFwOpCodeProces mp_mode == 0!!\n");
+		return _FALSE;
+	}
+
+	pH2c->opCode = btFwOpCode;
+	pH2c->opCodeVer = opCodeVer;
+	pH2c->reqNum = pMptCtx->h2cReqNum;
+	/* PlatformMoveMemory(&pH2c->buf[0], pH2cPar, h2cParaLen); */
+	/* _rtw_memcpy(&pH2c->buf[0], pH2cPar, h2cParaLen); */
+	_rtw_memcpy(pH2c->buf, pH2cPar, h2cParaLen);
+
+	RTW_INFO("[MPT], pH2c->opCode=%d\n", pH2c->opCode);
+	RTW_INFO("[MPT], pH2c->opCodeVer=%d\n", pH2c->opCodeVer);
+	RTW_INFO("[MPT], pH2c->reqNum=%d\n", pH2c->reqNum);
+	RTW_INFO("[MPT], h2c parameter length=%d\n", h2cParaLen);
+	for (i = 0; i < h2cParaLen; i++)
+		RTW_INFO("[MPT], parameter[%d]=0x%02x\n", i, pH2c->buf[i]);
+
+	h2cStatus = mptbt_SendH2c(Adapter, pH2c, h2cParaLen + 2);
+	if (BT_STATUS_H2C_SUCCESS == h2cStatus) {
+		/* if reach here, it means H2C get the correct c2h response, */
+		c2hStatus = mptbt_CheckC2hFrame(Adapter, pH2c, pExtC2h);
+		if (BT_STATUS_C2H_SUCCESS == c2hStatus)
+			retStatus = mptbt_CheckBtRspStatus(Adapter, pExtC2h);
+		else {
+			RTW_INFO("[MPT], Error!! C2H failed for pH2c->opCode=%d\n", pH2c->opCode);
+			/* check c2h status error, return error status code to upper layer. */
+			retStatus = c2hStatus;
+		}
+	} else {
+		RTW_INFO("[MPT], Error!! H2C failed for pH2c->opCode=%d\n", pH2c->opCode);
+		/* check h2c status error, return error status code to upper layer. */
+		retStatus = h2cStatus;
+	}
+
+	return retStatus;
+}
+
+
+
+
+u2Byte
+mptbt_BtReady(
+	PADAPTER		Adapter,
+	PBT_REQ_CMD	pBtReq,
+	PBT_RSP_CMD	pBtRsp
+)
+{
+	u1Byte				h2cParaBuf[6] = {0};
+	u1Byte				h2cParaLen = 0;
+	u2Byte				paraLen = 0;
+	u1Byte				retStatus = BT_STATUS_BT_OP_SUCCESS;
+	u1Byte				btOpcode;
+	u1Byte				btOpcodeVer = 0;
+	PMPT_CONTEXT		pMptCtx = &(Adapter->mppriv.mpt_ctx);
+	PBT_EXT_C2H			pExtC2h = (PBT_EXT_C2H)&pMptCtx->c2hBuf[0];
+	u1Byte				i;
+	u1Byte				btFwVer = 0, bdAddr[6] = {0};
+	u2Byte				btRealFwVer = 0;
+	pu2Byte			pu2Tmp = NULL;
+
+	/*  */
+	/* check upper layer parameters */
+	/*  */
+
+	/* 1. check upper layer opcode version */
+	if (pBtReq->opCodeVer != 1) {
+		RTW_INFO("[MPT], Error!! Upper OP code version not match!!!\n");
+		pBtRsp->status = BT_STATUS_OPCODE_U_VERSION_MISMATCH;
+		return paraLen;
+	}
+
+	pBtRsp->pParamStart[0] = MP_BT_NOT_READY;
+	paraLen = 10;
+	/*  */
+	/* execute lower layer opcodes */
+	/*  */
+
+	/* Get BT FW version */
+	/* fill h2c parameters */
+	btOpcode = BT_LO_OP_GET_BT_VERSION;
+	/* execute h2c and check respond c2h from bt fw is correct or not */
+	retStatus = mptbt_BtFwOpCodeProcess(Adapter, btOpcode, btOpcodeVer, &h2cParaBuf[0], h2cParaLen);
+	/* ckeck bt return status. */
+	if (BT_STATUS_BT_OP_SUCCESS != retStatus) {
+		pBtRsp->status = ((btOpcode << 8) | retStatus);
+		RTW_INFO("[MPT], Error!! status code=0x%x\n", pBtRsp->status);
+		return paraLen;
+	} else {
+		pu2Tmp = (pu2Byte)&pExtC2h->buf[0];
+		btRealFwVer = *pu2Tmp;
+		btFwVer = pExtC2h->buf[1];
+		RTW_INFO("[MPT], btRealFwVer=0x%x, btFwVer=0x%x\n", btRealFwVer, btFwVer);
+	}
+
+	/* Get BD Address */
+	/* fill h2c parameters */
+	btOpcode = BT_LO_OP_GET_BD_ADDR_L;
+	/* execute h2c and check respond c2h from bt fw is correct or not */
+	retStatus = mptbt_BtFwOpCodeProcess(Adapter, btOpcode, btOpcodeVer, &h2cParaBuf[0], h2cParaLen);
+	/* ckeck bt return status. */
+	if (BT_STATUS_BT_OP_SUCCESS != retStatus) {
+		pBtRsp->status = ((btOpcode << 8) | retStatus);
+		RTW_INFO("[MPT], Error!! status code=0x%x\n", pBtRsp->status);
+		return paraLen;
+	} else {
+		bdAddr[5] = pExtC2h->buf[0];
+		bdAddr[4] = pExtC2h->buf[1];
+		bdAddr[3] = pExtC2h->buf[2];
+	}
+
+	/* fill h2c parameters */
+	btOpcode = BT_LO_OP_GET_BD_ADDR_H;
+	/* execute h2c and check respond c2h from bt fw is correct or not */
+	retStatus = mptbt_BtFwOpCodeProcess(Adapter, btOpcode, btOpcodeVer, &h2cParaBuf[0], h2cParaLen);
+	/* ckeck bt return status. */
+	if (BT_STATUS_BT_OP_SUCCESS != retStatus) {
+		pBtRsp->status = ((btOpcode << 8) | retStatus);
+		RTW_INFO("[MPT], Error!! status code=0x%x\n", pBtRsp->status);
+		return paraLen;
+	} else {
+		bdAddr[2] = pExtC2h->buf[0];
+		bdAddr[1] = pExtC2h->buf[1];
+		bdAddr[0] = pExtC2h->buf[2];
+	}
+	RTW_INFO("[MPT], Local BDAddr:");
+	for (i = 0; i < 6; i++)
+		RTW_INFO(" 0x%x ", bdAddr[i]);
+	pBtRsp->status = BT_STATUS_SUCCESS;
+	pBtRsp->pParamStart[0] = MP_BT_READY;
+	pu2Tmp = (pu2Byte)&pBtRsp->pParamStart[1];
+	*pu2Tmp = btRealFwVer;
+	pBtRsp->pParamStart[3] = btFwVer;
+	for (i = 0; i < 6; i++)
+		pBtRsp->pParamStart[4 + i] = bdAddr[5 - i];
+
+	return paraLen;
+}
+
+void mptbt_close_WiFiRF(PADAPTER Adapter)
+{
+	phy_set_bb_reg(Adapter, 0x824, 0xF, 0x0);
+	phy_set_bb_reg(Adapter, 0x824, 0x700000, 0x0);
+	phy_set_rf_reg(Adapter, RF_PATH_A, 0x0, 0xF0000, 0x0);
+}
+
+void mptbt_open_WiFiRF(PADAPTER	Adapter)
+{
+	phy_set_bb_reg(Adapter, 0x824, 0x700000, 0x3);
+	phy_set_bb_reg(Adapter, 0x824, 0xF, 0x2);
+	phy_set_rf_reg(Adapter, RF_PATH_A, 0x0, 0xF0000, 0x3);
+}
+
+u4Byte mptbt_switch_RF(PADAPTER	Adapter, u1Byte	Enter)
+{
+	u2Byte	tmp_2byte = 0;
+
+	/* Enter test mode */
+	if (Enter) {
+		/* 1>. close WiFi RF */
+		mptbt_close_WiFiRF(Adapter);
+
+		/* 2>. change ant switch to BT */
+		tmp_2byte = rtw_read16(Adapter, 0x860);
+		tmp_2byte = tmp_2byte | BIT(9);
+		tmp_2byte = tmp_2byte & (~BIT(8));
+		rtw_write16(Adapter, 0x860, tmp_2byte);
+		rtw_write16(Adapter, 0x870, 0x300);
+	} else {
+		/* 1>. Open WiFi RF */
+		mptbt_open_WiFiRF(Adapter);
+
+		/* 2>. change ant switch back */
+		tmp_2byte = rtw_read16(Adapter, 0x860);
+		tmp_2byte = tmp_2byte | BIT(8);
+		tmp_2byte = tmp_2byte & (~BIT(9));
+		rtw_write16(Adapter, 0x860, tmp_2byte);
+		rtw_write16(Adapter, 0x870, 0x300);
+	}
+
+	return 0;
+}
+
+u2Byte
+mptbt_BtSetMode(
+	PADAPTER		Adapter,
+	PBT_REQ_CMD	pBtReq,
+	PBT_RSP_CMD	pBtRsp
+)
+{
+	u1Byte				h2cParaBuf[6] = {0};
+	u1Byte				h2cParaLen = 0;
+	u2Byte				paraLen = 0;
+	u1Byte				retStatus = BT_STATUS_BT_OP_SUCCESS;
+	u1Byte				btOpcode;
+	u1Byte				btOpcodeVer = 0;
+	u1Byte				btModeToSet = 0;
+
+	/*  */
+	/* check upper layer parameters */
+	/*  */
+	/* 1. check upper layer opcode version */
+	if (pBtReq->opCodeVer != 1) {
+		RTW_INFO("[MPT], Error!! Upper OP code version not match!!!\n");
+		pBtRsp->status = BT_STATUS_OPCODE_U_VERSION_MISMATCH;
+		return paraLen;
+	}
+	/* 2. check upper layer parameter length */
+	if (1 == pBtReq->paraLength) {
+		btModeToSet = pBtReq->pParamStart[0];
+		RTW_INFO("[MPT], BtTestMode=%d\n", btModeToSet);
+	} else {
+		RTW_INFO("[MPT], Error!! wrong parameter length=%d (should be 1)\n", pBtReq->paraLength);
+		pBtRsp->status = BT_STATUS_PARAMETER_FORMAT_ERROR_U;
+		return paraLen;
+	}
+
+	/*  */
+	/* execute lower layer opcodes */
+	/*  */
+
+	/* 1. fill h2c parameters	 */
+	/* check bt mode */
+	btOpcode = BT_LO_OP_SET_BT_MODE;
+	if (btModeToSet >= MP_BT_MODE_MAX) {
+		pBtRsp->status = BT_STATUS_PARAMETER_OUT_OF_RANGE_U;
+		return paraLen;
+	} else {
+		mptbt_switch_RF(Adapter, 1);
+
+		h2cParaBuf[0] = btModeToSet;
+		h2cParaLen = 1;
+		/* 2. execute h2c and check respond c2h from bt fw is correct or not */
+		retStatus = mptbt_BtFwOpCodeProcess(Adapter, btOpcode, btOpcodeVer, &h2cParaBuf[0], h2cParaLen);
+	}
+
+	/* 3. construct respond status code and data. */
+	if (BT_STATUS_BT_OP_SUCCESS == retStatus)
+		pBtRsp->status = BT_STATUS_SUCCESS;
+	else {
+		pBtRsp->status = ((btOpcode << 8) | retStatus);
+		RTW_INFO("[MPT], Error!! status code=0x%x\n", pBtRsp->status);
+	}
+
+	return paraLen;
+}
+
+
+VOID
+MPTBT_FwC2hBtMpCtrl(
+	PADAPTER	Adapter,
+	pu1Byte	tmpBuf,
+	u1Byte		length
+)
+{
+	u32 i;
+	PMPT_CONTEXT	pMptCtx = &(Adapter->mppriv.mpt_ctx);
+	PBT_EXT_C2H pExtC2h = (PBT_EXT_C2H)tmpBuf;
+
+	if (GET_HAL_DATA(Adapter)->bBTFWReady == _FALSE || Adapter->registrypriv.mp_mode == 0) {
+		/* RTW_INFO("Ignore C2H BT MP Info since not in MP mode\n"); */
+		return;
+	}
+	if (length > 32 || length < 3) {
+		RTW_INFO("\n [MPT], pExtC2h->buf hex: length=%d > 32 || < 3\n", length);
+		return;
+	}
+
+	/* cancel_timeout for h2c handle */
+	_cancel_timer_ex(&pMptCtx->MPh2c_timeout_timer);
+
+	for (i = 0; i < length; i++)
+		RTW_INFO("[MPT], %s, buf[%d]=0x%02x ", __FUNCTION__, i, tmpBuf[i]);
+	RTW_INFO("[MPT], pExtC2h->extendId=0x%x\n", pExtC2h->extendId);
+
+	switch (pExtC2h->extendId) {
+	case EXT_C2H_WIFI_FW_ACTIVE_RSP:
+		RTW_INFO("[MPT], EXT_C2H_WIFI_FW_ACTIVE_RSP\n");
+#if 0
+		RTW_INFO("[MPT], pExtC2h->buf hex:\n");
+		for (i = 0; i < (length - 3); i++)
+			RTW_INFO(" 0x%x ", pExtC2h->buf[i]);
+#endif
+		if ((_FALSE == pMptCtx->bMPh2c_timeout)
+		    && (_FALSE == pMptCtx->MptH2cRspEvent)) {
+			pMptCtx->MptH2cRspEvent = _TRUE;
+			_rtw_up_sema(&pMptCtx->MPh2c_Sema);
+		}
+		break;
+
+	case EXT_C2H_TRIG_BY_BT_FW:
+		RTW_INFO("[MPT], EXT_C2H_TRIG_BY_BT_FW\n");
+		_rtw_memcpy(&pMptCtx->c2hBuf[0], tmpBuf, length);
+		RTW_INFO("[MPT], pExtC2h->statusCode=0x%x\n", pExtC2h->statusCode);
+		RTW_INFO("[MPT], pExtC2h->retLen=0x%x\n", pExtC2h->retLen);
+		RTW_INFO("[MPT], pExtC2h->opCodeVer=0x%x\n", pExtC2h->opCodeVer);
+		RTW_INFO("[MPT], pExtC2h->reqNum=0x%x\n", pExtC2h->reqNum);
+		for (i = 0; i < (length - 3); i++)
+			RTW_INFO("[MPT], pExtC2h->buf[%d]=0x%02x\n", i, pExtC2h->buf[i]);
+
+		if ((_FALSE == pMptCtx->bMPh2c_timeout)
+		    && (_TRUE == pMptCtx->MptH2cRspEvent)
+		    && (_FALSE == pMptCtx->MptBtC2hEvent)) {
+			pMptCtx->MptBtC2hEvent = _TRUE;
+			_rtw_up_sema(&pMptCtx->MPh2c_Sema);
+		}
+		break;
+
+	default:
+		RTW_INFO("[MPT], EXT_C2H Target not found,pExtC2h->extendId =%d ,pExtC2h->reqNum=%d\n", pExtC2h->extendId, pExtC2h->reqNum);
+		break;
+	}
+
+
+
+}
+
+
+u2Byte
+mptbt_BtGetGeneral(
+	IN	PADAPTER		Adapter,
+	IN	PBT_REQ_CMD	pBtReq,
+	IN	PBT_RSP_CMD	pBtRsp
+)
+{
+	PMPT_CONTEXT		pMptCtx = &(Adapter->mppriv.mpt_ctx);
+	PBT_EXT_C2H		pExtC2h = (PBT_EXT_C2H)&pMptCtx->c2hBuf[0];
+	u1Byte				h2cParaBuf[6] = {0};
+	u1Byte				h2cParaLen = 0;
+	u2Byte				paraLen = 0;
+	u1Byte				retStatus = BT_STATUS_BT_OP_SUCCESS;
+	u1Byte				btOpcode, bdAddr[6] = {0};
+	u1Byte				btOpcodeVer = 0;
+	u1Byte				getType = 0, i;
+	u2Byte				getParaLen = 0, validParaLen = 0;
+	u1Byte				regType = 0, reportType = 0;
+	u4Byte				regAddr = 0, regValue = 0;
+	pu4Byte			pu4Tmp;
+	pu2Byte			pu2Tmp;
+	pu1Byte			pu1Tmp;
+
+	/*  */
+	/* check upper layer parameters */
+	/*  */
+
+	/* check upper layer opcode version */
+	if (pBtReq->opCodeVer != 1) {
+		RTW_INFO("[MPT], Error!! Upper OP code version not match!!!\n");
+		pBtRsp->status = BT_STATUS_OPCODE_U_VERSION_MISMATCH;
+		return paraLen;
+	}
+	/* check upper layer parameter length */
+	if (pBtReq->paraLength < 1) {
+		RTW_INFO("[MPT], Error!! wrong parameter length=%d (should larger than 1)\n", pBtReq->paraLength);
+		pBtRsp->status = BT_STATUS_PARAMETER_FORMAT_ERROR_U;
+		return paraLen;
+	}
+	getParaLen = pBtReq->paraLength - 1;
+	getType = pBtReq->pParamStart[0];
+
+	RTW_INFO("[MPT], getType=%d, getParaLen=%d\n", getType, getParaLen);
+
+	/* check parameter first */
+	switch (getType) {
+	case BT_GGET_REG:
+		RTW_INFO("[MPT], [BT_GGET_REG]\n");
+		validParaLen = 5;
+		if (getParaLen == validParaLen) {
+			btOpcode = BT_LO_OP_READ_REG;
+			regType = pBtReq->pParamStart[1];
+			pu4Tmp = (pu4Byte)&pBtReq->pParamStart[2];
+			regAddr = *pu4Tmp;
+			RTW_INFO("[MPT], BT_GGET_REG regType=0x%02x, regAddr=0x%08x!!\n",
+				 regType, regAddr);
+			if (regType >= BT_REG_MAX) {
+				pBtRsp->status = (btOpcode << 8) | BT_STATUS_PARAMETER_OUT_OF_RANGE_U;
+				return paraLen;
+			} else {
+				if (((BT_REG_RF == regType) && (regAddr > 0x7f)) ||
+				    ((BT_REG_MODEM == regType) && (regAddr > 0x1ff)) ||
+				    ((BT_REG_BLUEWIZE == regType) && (regAddr > 0xfff)) ||
+				    ((BT_REG_VENDOR == regType) && (regAddr > 0xfff)) ||
+				    ((BT_REG_LE == regType) && (regAddr > 0xfff))) {
+					pBtRsp->status = (btOpcode << 8) | BT_STATUS_PARAMETER_OUT_OF_RANGE_U;
+					return paraLen;
+				}
+			}
+		}
+		break;
+	case BT_GGET_STATUS:
+		RTW_INFO("[MPT], [BT_GGET_STATUS]\n");
+		validParaLen = 0;
+		break;
+	case BT_GGET_REPORT:
+		RTW_INFO("[MPT], [BT_GGET_REPORT]\n");
+		validParaLen = 1;
+		if (getParaLen == validParaLen) {
+			reportType = pBtReq->pParamStart[1];
+			RTW_INFO("[MPT], BT_GGET_REPORT reportType=0x%x!!\n", reportType);
+			if (reportType >= BT_REPORT_MAX) {
+				pBtRsp->status = BT_STATUS_PARAMETER_OUT_OF_RANGE_U;
+				return paraLen;
+			}
+		}
+		break;
+	default: {
+		RTW_INFO("[MPT], Error!! getType=%d, out of range\n", getType);
+		pBtRsp->status = BT_STATUS_PARAMETER_OUT_OF_RANGE_U;
+		return paraLen;
+	}
+	break;
+	}
+	if (getParaLen != validParaLen) {
+		RTW_INFO("[MPT], Error!! wrong parameter length=%d for BT_GET_GEN_CMD cmd id=0x%x, paraLen should=0x%x\n",
+			 getParaLen, getType, validParaLen);
+		pBtRsp->status = BT_STATUS_PARAMETER_FORMAT_ERROR_U;
+		return paraLen;
+	}
+
+	/*  */
+	/* execute lower layer opcodes */
+	/*  */
+	if (BT_GGET_REG == getType) {
+		/* fill h2c parameters */
+		/* here we should write reg value first then write the address, adviced by Austin */
+		btOpcode = BT_LO_OP_READ_REG;
+		h2cParaBuf[0] = regType;
+		h2cParaBuf[1] = pBtReq->pParamStart[2];
+		h2cParaBuf[2] = pBtReq->pParamStart[3];
+		h2cParaLen = 3;
+		/* execute h2c and check respond c2h from bt fw is correct or not */
+		retStatus = mptbt_BtFwOpCodeProcess(Adapter, btOpcode, btOpcodeVer, &h2cParaBuf[0], h2cParaLen);
+		/* construct respond status code and data. */
+		if (BT_STATUS_BT_OP_SUCCESS != retStatus) {
+			pBtRsp->status = ((btOpcode << 8) | retStatus);
+			RTW_INFO("[MPT], Error!! status code=0x%x\n", pBtRsp->status);
+			return paraLen;
+		}
+
+		pu2Tmp = (pu2Byte)&pExtC2h->buf[0];
+		regValue = *pu2Tmp;
+		RTW_INFO("[MPT], read reg regType=0x%02x, regAddr=0x%08x, regValue=0x%04x\n",
+			 regType, regAddr, regValue);
+
+		pu4Tmp = (pu4Byte)&pBtRsp->pParamStart[0];
+		*pu4Tmp = regValue;
+		paraLen = 4;
+	} else if (BT_GGET_STATUS == getType) {
+		btOpcode = BT_LO_OP_GET_BT_STATUS;
+		h2cParaLen = 0;
+		/* execute h2c and check respond c2h from bt fw is correct or not */
+		retStatus = mptbt_BtFwOpCodeProcess(Adapter, btOpcode, btOpcodeVer, &h2cParaBuf[0], h2cParaLen);
+		/* construct respond status code and data. */
+		if (BT_STATUS_BT_OP_SUCCESS != retStatus) {
+			pBtRsp->status = ((btOpcode << 8) | retStatus);
+			RTW_INFO("[MPT], Error!! status code=0x%x\n", pBtRsp->status);
+			return paraLen;
+		}
+
+		pBtRsp->pParamStart[0] = pExtC2h->buf[0];
+		pBtRsp->pParamStart[1] = pExtC2h->buf[1];
+		RTW_INFO("[MPT], read bt status, testMode=0x%x, testStatus=0x%x\n",
+			 pBtRsp->pParamStart[0], pBtRsp->pParamStart[1]);
+		paraLen = 2;
+	} else if (BT_GGET_REPORT == getType) {
+		switch (reportType) {
+		case BT_REPORT_RX_PACKET_CNT: {
+			RTW_INFO("[MPT], [Rx Packet Counts]\n");
+			btOpcode = BT_LO_OP_GET_RX_PKT_CNT_L;
+			h2cParaLen = 0;
+			/* execute h2c and check respond c2h from bt fw is correct or not */
+			retStatus = mptbt_BtFwOpCodeProcess(Adapter, btOpcode, btOpcodeVer, &h2cParaBuf[0], h2cParaLen);
+			/* construct respond status code and data. */
+			if (BT_STATUS_BT_OP_SUCCESS != retStatus) {
+				pBtRsp->status = ((btOpcode << 8) | retStatus);
+				RTW_INFO("[MPT], Error!! status code=0x%x\n", pBtRsp->status);
+				return paraLen;
+			}
+			pBtRsp->pParamStart[0] = pExtC2h->buf[0];
+			pBtRsp->pParamStart[1] = pExtC2h->buf[1];
+
+			btOpcode = BT_LO_OP_GET_RX_PKT_CNT_H;
+			h2cParaLen = 0;
+			/* execute h2c and check respond c2h from bt fw is correct or not */
+			retStatus = mptbt_BtFwOpCodeProcess(Adapter, btOpcode, btOpcodeVer, &h2cParaBuf[0], h2cParaLen);
+			/* construct respond status code and data. */
+			if (BT_STATUS_BT_OP_SUCCESS != retStatus) {
+				pBtRsp->status = ((btOpcode << 8) | retStatus);
+				RTW_INFO("[MPT], Error!! status code=0x%x\n", pBtRsp->status);
+				return paraLen;
+			}
+			pBtRsp->pParamStart[2] = pExtC2h->buf[0];
+			pBtRsp->pParamStart[3] = pExtC2h->buf[1];
+			paraLen = 4;
+		}
+		break;
+		case BT_REPORT_RX_ERROR_BITS: {
+			RTW_INFO("[MPT], [Rx Error Bits]\n");
+			btOpcode = BT_LO_OP_GET_RX_ERROR_BITS_L;
+			h2cParaLen = 0;
+			/* execute h2c and check respond c2h from bt fw is correct or not */
+			retStatus = mptbt_BtFwOpCodeProcess(Adapter, btOpcode, btOpcodeVer, &h2cParaBuf[0], h2cParaLen);
+			/* construct respond status code and data. */
+			if (BT_STATUS_BT_OP_SUCCESS != retStatus) {
+				pBtRsp->status = ((btOpcode << 8) | retStatus);
+				RTW_INFO("[MPT], Error!! status code=0x%x\n", pBtRsp->status);
+				return paraLen;
+			}
+			pBtRsp->pParamStart[0] = pExtC2h->buf[0];
+			pBtRsp->pParamStart[1] = pExtC2h->buf[1];
+
+			btOpcode = BT_LO_OP_GET_RX_ERROR_BITS_H;
+			h2cParaLen = 0;
+			/* execute h2c and check respond c2h from bt fw is correct or not */
+			retStatus = mptbt_BtFwOpCodeProcess(Adapter, btOpcode, btOpcodeVer, &h2cParaBuf[0], h2cParaLen);
+			/* construct respond status code and data. */
+			if (BT_STATUS_BT_OP_SUCCESS != retStatus) {
+				pBtRsp->status = ((btOpcode << 8) | retStatus);
+				RTW_INFO("[MPT], Error!! status code=0x%x\n", pBtRsp->status);
+				return paraLen;
+			}
+			pBtRsp->pParamStart[2] = pExtC2h->buf[0];
+			pBtRsp->pParamStart[3] = pExtC2h->buf[1];
+			paraLen = 4;
+		}
+		break;
+		case BT_REPORT_RSSI: {
+			RTW_INFO("[MPT], [RSSI]\n");
+			btOpcode = BT_LO_OP_GET_RSSI;
+			h2cParaLen = 0;
+			/* execute h2c and check respond c2h from bt fw is correct or not */
+			retStatus = mptbt_BtFwOpCodeProcess(Adapter, btOpcode, btOpcodeVer, &h2cParaBuf[0], h2cParaLen);
+			/* construct respond status code and data. */
+			if (BT_STATUS_BT_OP_SUCCESS != retStatus) {
+				pBtRsp->status = ((btOpcode << 8) | retStatus);
+				RTW_INFO("[MPT], Error!! status code=0x%x\n", pBtRsp->status);
+				return paraLen;
+			}
+			pBtRsp->pParamStart[0] = pExtC2h->buf[0];
+			pBtRsp->pParamStart[1] = pExtC2h->buf[1];
+			paraLen = 2;
+		}
+		break;
+		case BT_REPORT_CFO_HDR_QUALITY: {
+			RTW_INFO("[MPT], [CFO & Header Quality]\n");
+			btOpcode = BT_LO_OP_GET_CFO_HDR_QUALITY_L;
+			h2cParaLen = 0;
+			/* execute h2c and check respond c2h from bt fw is correct or not */
+			retStatus = mptbt_BtFwOpCodeProcess(Adapter, btOpcode, btOpcodeVer, &h2cParaBuf[0], h2cParaLen);
+			/* construct respond status code and data. */
+			if (BT_STATUS_BT_OP_SUCCESS != retStatus) {
+				pBtRsp->status = ((btOpcode << 8) | retStatus);
+				RTW_INFO("[MPT], Error!! status code=0x%x\n", pBtRsp->status);
+				return paraLen;
+			}
+			pBtRsp->pParamStart[0] = pExtC2h->buf[0];
+			pBtRsp->pParamStart[1] = pExtC2h->buf[1];
+
+			btOpcode = BT_LO_OP_GET_CFO_HDR_QUALITY_H;
+			h2cParaLen = 0;
+			/* execute h2c and check respond c2h from bt fw is correct or not */
+			retStatus = mptbt_BtFwOpCodeProcess(Adapter, btOpcode, btOpcodeVer, &h2cParaBuf[0], h2cParaLen);
+			/* construct respond status code and data. */
+			if (BT_STATUS_BT_OP_SUCCESS != retStatus) {
+				pBtRsp->status = ((btOpcode << 8) | retStatus);
+				RTW_INFO("[MPT], Error!! status code=0x%x\n", pBtRsp->status);
+				return paraLen;
+			}
+			pBtRsp->pParamStart[2] = pExtC2h->buf[0];
+			pBtRsp->pParamStart[3] = pExtC2h->buf[1];
+			paraLen = 4;
+		}
+		break;
+		case BT_REPORT_CONNECT_TARGET_BD_ADDR: {
+			RTW_INFO("[MPT], [Connected Target BD ADDR]\n");
+			btOpcode = BT_LO_OP_GET_TARGET_BD_ADDR_L;
+			h2cParaLen = 0;
+			/* execute h2c and check respond c2h from bt fw is correct or not */
+			retStatus = mptbt_BtFwOpCodeProcess(Adapter, btOpcode, btOpcodeVer, &h2cParaBuf[0], h2cParaLen);
+			/* construct respond status code and data. */
+			if (BT_STATUS_BT_OP_SUCCESS != retStatus) {
+				pBtRsp->status = ((btOpcode << 8) | retStatus);
+				RTW_INFO("[MPT], Error!! status code=0x%x\n", pBtRsp->status);
+				return paraLen;
+			}
+			bdAddr[5] = pExtC2h->buf[0];
+			bdAddr[4] = pExtC2h->buf[1];
+			bdAddr[3] = pExtC2h->buf[2];
+
+			btOpcode = BT_LO_OP_GET_TARGET_BD_ADDR_H;
+			h2cParaLen = 0;
+			/* execute h2c and check respond c2h from bt fw is correct or not */
+			retStatus = mptbt_BtFwOpCodeProcess(Adapter, btOpcode, btOpcodeVer, &h2cParaBuf[0], h2cParaLen);
+			/* construct respond status code and data. */
+			if (BT_STATUS_BT_OP_SUCCESS != retStatus) {
+				pBtRsp->status = ((btOpcode << 8) | retStatus);
+				RTW_INFO("[MPT], Error!! status code=0x%x\n", pBtRsp->status);
+				return paraLen;
+			}
+			bdAddr[2] = pExtC2h->buf[0];
+			bdAddr[1] = pExtC2h->buf[1];
+			bdAddr[0] = pExtC2h->buf[2];
+
+			RTW_INFO("[MPT], Connected Target BDAddr:%s", bdAddr);
+			for (i = 0; i < 6; i++)
+				pBtRsp->pParamStart[i] = bdAddr[5 - i];
+			paraLen = 6;
+		}
+		break;
+		default:
+			pBtRsp->status = BT_STATUS_PARAMETER_OUT_OF_RANGE_U;
+			return paraLen;
+			break;
+		}
+	}
+
+	pBtRsp->status = BT_STATUS_SUCCESS;
+	return paraLen;
+}
+
+
+
+u2Byte
+mptbt_BtSetGeneral(
+	IN	PADAPTER		Adapter,
+	IN	PBT_REQ_CMD	pBtReq,
+	IN	PBT_RSP_CMD	pBtRsp
+)
+{
+	u1Byte				h2cParaBuf[6] = {0};
+	u1Byte				h2cParaLen = 0;
+	u2Byte				paraLen = 0;
+	u1Byte				retStatus = BT_STATUS_BT_OP_SUCCESS;
+	u1Byte				btOpcode;
+	u1Byte				btOpcodeVer = 0;
+	u1Byte				setType = 0;
+	u2Byte				setParaLen = 0, validParaLen = 0;
+	u1Byte				regType = 0, bdAddr[6] = {0}, calVal = 0;
+	u4Byte				regAddr = 0, regValue = 0;
+	pu4Byte			pu4Tmp;
+	pu2Byte			pu2Tmp;
+	pu1Byte			pu1Tmp;
+
+	/*  */
+	/* check upper layer parameters */
+	/*  */
+
+	/* check upper layer opcode version */
+	if (pBtReq->opCodeVer != 1) {
+		RTW_INFO("[MPT], Error!! Upper OP code version not match!!!\n");
+		pBtRsp->status = BT_STATUS_OPCODE_U_VERSION_MISMATCH;
+		return paraLen;
+	}
+	/* check upper layer parameter length */
+	if (pBtReq->paraLength < 1) {
+		RTW_INFO("[MPT], Error!! wrong parameter length=%d (should larger than 1)\n", pBtReq->paraLength);
+		pBtRsp->status = BT_STATUS_PARAMETER_FORMAT_ERROR_U;
+		return paraLen;
+	}
+	setParaLen = pBtReq->paraLength - 1;
+	setType = pBtReq->pParamStart[0];
+
+	RTW_INFO("[MPT], setType=%d, setParaLen=%d\n", setType, setParaLen);
+
+	/* check parameter first */
+	switch (setType) {
+	case BT_GSET_REG:
+		RTW_INFO("[MPT], [BT_GSET_REG]\n");
+		validParaLen = 9;
+		if (setParaLen == validParaLen) {
+			btOpcode = BT_LO_OP_WRITE_REG_VALUE;
+			regType = pBtReq->pParamStart[1];
+			pu4Tmp = (pu4Byte)&pBtReq->pParamStart[2];
+			regAddr = *pu4Tmp;
+			pu4Tmp = (pu4Byte)&pBtReq->pParamStart[6];
+			regValue = *pu4Tmp;
+			RTW_INFO("[MPT], BT_GSET_REG regType=0x%x, regAddr=0x%x, regValue=0x%x!!\n",
+				 regType, regAddr, regValue);
+			if (regType >= BT_REG_MAX) {
+				pBtRsp->status = (btOpcode << 8) | BT_STATUS_PARAMETER_OUT_OF_RANGE_U;
+				return paraLen;
+			} else {
+				if (((BT_REG_RF == regType) && (regAddr > 0x7f)) ||
+				    ((BT_REG_MODEM == regType) && (regAddr > 0x1ff)) ||
+				    ((BT_REG_BLUEWIZE == regType) && (regAddr > 0xfff)) ||
+				    ((BT_REG_VENDOR == regType) && (regAddr > 0xfff)) ||
+				    ((BT_REG_LE == regType) && (regAddr > 0xfff))) {
+					pBtRsp->status = (btOpcode << 8) | BT_STATUS_PARAMETER_OUT_OF_RANGE_U;
+					return paraLen;
+				}
+			}
+		}
+		break;
+	case BT_GSET_RESET:
+		RTW_INFO("[MPT], [BT_GSET_RESET]\n");
+		validParaLen = 0;
+		break;
+	case BT_GSET_TARGET_BD_ADDR:
+		RTW_INFO("[MPT], [BT_GSET_TARGET_BD_ADDR]\n");
+		validParaLen = 6;
+		if (setParaLen == validParaLen) {
+			btOpcode = BT_LO_OP_SET_TARGET_BD_ADDR_H;
+			if ((pBtReq->pParamStart[1] == 0) &&
+			    (pBtReq->pParamStart[2] == 0) &&
+			    (pBtReq->pParamStart[3] == 0) &&
+			    (pBtReq->pParamStart[4] == 0) &&
+			    (pBtReq->pParamStart[5] == 0) &&
+			    (pBtReq->pParamStart[6] == 0)) {
+				RTW_INFO("[MPT], Error!! targetBDAddr=all zero\n");
+				pBtRsp->status = (btOpcode << 8) | BT_STATUS_PARAMETER_OUT_OF_RANGE_U;
+				return paraLen;
+			}
+			if ((pBtReq->pParamStart[1] == 0xff) &&
+			    (pBtReq->pParamStart[2] == 0xff) &&
+			    (pBtReq->pParamStart[3] == 0xff) &&
+			    (pBtReq->pParamStart[4] == 0xff) &&
+			    (pBtReq->pParamStart[5] == 0xff) &&
+			    (pBtReq->pParamStart[6] == 0xff)) {
+				RTW_INFO("[MPT], Error!! targetBDAddr=all 0xf\n");
+				pBtRsp->status = (btOpcode << 8) | BT_STATUS_PARAMETER_OUT_OF_RANGE_U;
+				return paraLen;
+			}
+			bdAddr[0] = pBtReq->pParamStart[6];
+			bdAddr[1] = pBtReq->pParamStart[5];
+			bdAddr[2] = pBtReq->pParamStart[4];
+			bdAddr[3] = pBtReq->pParamStart[3];
+			bdAddr[4] = pBtReq->pParamStart[2];
+			bdAddr[5] = pBtReq->pParamStart[1];
+			RTW_INFO("[MPT], target BDAddr:%x,%x,%x,%x,%x,%x\n",
+				bdAddr[0], bdAddr[1], bdAddr[2], bdAddr[3], bdAddr[4], bdAddr[5]);
+		}
+		break;
+	case BT_GSET_TX_PWR_FINETUNE:
+		RTW_INFO("[MPT], [BT_GSET_TX_PWR_FINETUNE]\n");
+		validParaLen = 1;
+		if (setParaLen == validParaLen) {
+			btOpcode = BT_LO_OP_SET_TX_POWER_CALIBRATION;
+			calVal = pBtReq->pParamStart[1];
+			if ((calVal < 1) || (calVal > 9)) {
+				pBtRsp->status = (btOpcode << 8) | BT_STATUS_PARAMETER_OUT_OF_RANGE_U;
+				return paraLen;
+			}
+			RTW_INFO("[MPT], calVal=%d\n", calVal);
+		}
+		break;
+	case BT_SET_TRACKING_INTERVAL:
+		RTW_INFO("[MPT], [BT_SET_TRACKING_INTERVAL] setParaLen =%d\n", setParaLen);
+
+		validParaLen = 1;
+		if (setParaLen == validParaLen)
+			calVal = pBtReq->pParamStart[1];
+		break;
+	case BT_SET_THERMAL_METER:
+		RTW_INFO("[MPT], [BT_SET_THERMAL_METER] setParaLen =%d\n", setParaLen);
+		validParaLen = 1;
+		if (setParaLen == validParaLen)
+			calVal = pBtReq->pParamStart[1];
+		break;
+	case BT_ENABLE_CFO_TRACKING:
+		RTW_INFO("[MPT], [BT_ENABLE_CFO_TRACKING] setParaLen =%d\n", setParaLen);
+		validParaLen = 1;
+		if (setParaLen == validParaLen)
+			calVal = pBtReq->pParamStart[1];
+		break;
+	case BT_GSET_UPDATE_BT_PATCH:
+
+		break;
+	default: {
+		RTW_INFO("[MPT], Error!! setType=%d, out of range\n", setType);
+		pBtRsp->status = BT_STATUS_PARAMETER_OUT_OF_RANGE_U;
+		return paraLen;
+	}
+	break;
+	}
+	if (setParaLen != validParaLen) {
+		RTW_INFO("[MPT], Error!! wrong parameter length=%d for BT_SET_GEN_CMD cmd id=0x%x, paraLen should=0x%x\n",
+			 setParaLen, setType, validParaLen);
+		pBtRsp->status = BT_STATUS_PARAMETER_FORMAT_ERROR_U;
+		return paraLen;
+	}
+
+	/*  */
+	/* execute lower layer opcodes */
+	/*  */
+	if (BT_GSET_REG == setType) {
+		/* fill h2c parameters */
+		/* here we should write reg value first then write the address, adviced by Austin */
+		btOpcode = BT_LO_OP_WRITE_REG_VALUE;
+		h2cParaBuf[0] = pBtReq->pParamStart[6];
+		h2cParaBuf[1] = pBtReq->pParamStart[7];
+		h2cParaBuf[2] = pBtReq->pParamStart[8];
+		h2cParaLen = 3;
+		/* execute h2c and check respond c2h from bt fw is correct or not */
+		retStatus = mptbt_BtFwOpCodeProcess(Adapter, btOpcode, btOpcodeVer, &h2cParaBuf[0], h2cParaLen);
+		/* construct respond status code and data. */
+		if (BT_STATUS_BT_OP_SUCCESS != retStatus) {
+			pBtRsp->status = ((btOpcode << 8) | retStatus);
+			RTW_INFO("[MPT], Error!! status code=0x%x\n", pBtRsp->status);
+			return paraLen;
+		}
+
+		/* write reg address */
+		btOpcode = BT_LO_OP_WRITE_REG_ADDR;
+		h2cParaBuf[0] = regType;
+		h2cParaBuf[1] = pBtReq->pParamStart[2];
+		h2cParaBuf[2] = pBtReq->pParamStart[3];
+		h2cParaLen = 3;
+		/* execute h2c and check respond c2h from bt fw is correct or not */
+		retStatus = mptbt_BtFwOpCodeProcess(Adapter, btOpcode, btOpcodeVer, &h2cParaBuf[0], h2cParaLen);
+		/* construct respond status code and data. */
+		if (BT_STATUS_BT_OP_SUCCESS != retStatus) {
+			pBtRsp->status = ((btOpcode << 8) | retStatus);
+			RTW_INFO("[MPT], Error!! status code=0x%x\n", pBtRsp->status);
+			return paraLen;
+		}
+	} else if (BT_GSET_RESET == setType) {
+		btOpcode = BT_LO_OP_RESET;
+		h2cParaLen = 0;
+		/* execute h2c and check respond c2h from bt fw is correct or not */
+		retStatus = mptbt_BtFwOpCodeProcess(Adapter, btOpcode, btOpcodeVer, &h2cParaBuf[0], h2cParaLen);
+		/* construct respond status code and data. */
+		if (BT_STATUS_BT_OP_SUCCESS != retStatus) {
+			pBtRsp->status = ((btOpcode << 8) | retStatus);
+			RTW_INFO("[MPT], Error!! status code=0x%x\n", pBtRsp->status);
+			return paraLen;
+		}
+	} else if (BT_GSET_TARGET_BD_ADDR == setType) {
+		/* fill h2c parameters */
+		btOpcode = BT_LO_OP_SET_TARGET_BD_ADDR_L;
+		h2cParaBuf[0] = pBtReq->pParamStart[1];
+		h2cParaBuf[1] = pBtReq->pParamStart[2];
+		h2cParaBuf[2] = pBtReq->pParamStart[3];
+		h2cParaLen = 3;
+		retStatus = mptbt_BtFwOpCodeProcess(Adapter, btOpcode, btOpcodeVer, &h2cParaBuf[0], h2cParaLen);
+		/* ckeck bt return status. */
+		if (BT_STATUS_BT_OP_SUCCESS != retStatus) {
+			pBtRsp->status = ((btOpcode << 8) | retStatus);
+			RTW_INFO("[MPT], Error!! status code=0x%x\n", pBtRsp->status);
+			return paraLen;
+		}
+
+		btOpcode = BT_LO_OP_SET_TARGET_BD_ADDR_H;
+		h2cParaBuf[0] = pBtReq->pParamStart[4];
+		h2cParaBuf[1] = pBtReq->pParamStart[5];
+		h2cParaBuf[2] = pBtReq->pParamStart[6];
+		h2cParaLen = 3;
+		retStatus = mptbt_BtFwOpCodeProcess(Adapter, btOpcode, btOpcodeVer, &h2cParaBuf[0], h2cParaLen);
+		/* ckeck bt return status. */
+		if (BT_STATUS_BT_OP_SUCCESS != retStatus) {
+			pBtRsp->status = ((btOpcode << 8) | retStatus);
+			RTW_INFO("[MPT], Error!! status code=0x%x\n", pBtRsp->status);
+			return paraLen;
+		}
+	} else if (BT_GSET_TX_PWR_FINETUNE == setType) {
+		/* fill h2c parameters */
+		btOpcode = BT_LO_OP_SET_TX_POWER_CALIBRATION;
+		h2cParaBuf[0] = calVal;
+		h2cParaLen = 1;
+		retStatus = mptbt_BtFwOpCodeProcess(Adapter, btOpcode, btOpcodeVer, &h2cParaBuf[0], h2cParaLen);
+		/* ckeck bt return status. */
+		if (BT_STATUS_BT_OP_SUCCESS != retStatus) {
+			pBtRsp->status = ((btOpcode << 8) | retStatus);
+			RTW_INFO("[MPT], Error!! status code=0x%x\n", pBtRsp->status);
+			return paraLen;
+		}
+	} else if (BT_SET_TRACKING_INTERVAL == setType) {
+		/*	BT_LO_OP_SET_TRACKING_INTERVAL								= 0x22, */
+		/*	BT_LO_OP_SET_THERMAL_METER									= 0x23, */
+		/*	BT_LO_OP_ENABLE_CFO_TRACKING									= 0x24, */
+		btOpcode = BT_LO_OP_SET_TRACKING_INTERVAL;
+		h2cParaBuf[0] = calVal;
+		h2cParaLen = 1;
+		retStatus = mptbt_BtFwOpCodeProcess(Adapter, btOpcode, btOpcodeVer, &h2cParaBuf[0], h2cParaLen);
+		/* ckeck bt return status. */
+		if (BT_STATUS_BT_OP_SUCCESS != retStatus) {
+			pBtRsp->status = ((btOpcode << 8) | retStatus);
+			RTW_INFO("[MPT], Error!! status code=0x%x\n", pBtRsp->status);
+			return paraLen;
+		}
+	} else if (BT_SET_THERMAL_METER == setType) {
+		btOpcode = BT_LO_OP_SET_THERMAL_METER;
+		h2cParaBuf[0] = calVal;
+		h2cParaLen = 1;
+		retStatus = mptbt_BtFwOpCodeProcess(Adapter, btOpcode, btOpcodeVer, &h2cParaBuf[0], h2cParaLen);
+		/* ckeck bt return status. */
+		if (BT_STATUS_BT_OP_SUCCESS != retStatus) {
+			pBtRsp->status = ((btOpcode << 8) | retStatus);
+			RTW_INFO("[MPT], Error!! status code=0x%x\n", pBtRsp->status);
+			return paraLen;
+		}
+	} else if (BT_ENABLE_CFO_TRACKING == setType) {
+		btOpcode = BT_LO_OP_ENABLE_CFO_TRACKING;
+		h2cParaBuf[0] = calVal;
+		h2cParaLen = 1;
+		retStatus = mptbt_BtFwOpCodeProcess(Adapter, btOpcode, btOpcodeVer, &h2cParaBuf[0], h2cParaLen);
+		/* ckeck bt return status. */
+		if (BT_STATUS_BT_OP_SUCCESS != retStatus) {
+			pBtRsp->status = ((btOpcode << 8) | retStatus);
+			RTW_INFO("[MPT], Error!! status code=0x%x\n", pBtRsp->status);
+			return paraLen;
+		}
+	}
+
+	pBtRsp->status = BT_STATUS_SUCCESS;
+	return paraLen;
+}
+
+
+
+u2Byte
+mptbt_BtSetTxRxPars(
+	IN	PADAPTER		Adapter,
+	IN	PBT_REQ_CMD	pBtReq,
+	IN	PBT_RSP_CMD	pBtRsp
+)
+{
+	u1Byte				h2cParaBuf[6] = {0};
+	u1Byte				h2cParaLen = 0;
+	u2Byte				paraLen = 0;
+	u1Byte				retStatus = BT_STATUS_BT_OP_SUCCESS;
+	u1Byte				btOpcode;
+	u1Byte				btOpcodeVer = 0;
+	PBT_TXRX_PARAMETERS pTxRxPars = (PBT_TXRX_PARAMETERS)&pBtReq->pParamStart[0];
+	u2Byte				lenTxRx = sizeof(BT_TXRX_PARAMETERS);
+	u1Byte				i;
+	u1Byte				bdAddr[6] = {0};
+
+	/*  */
+	/* check upper layer parameters */
+	/*  */
+
+	/* 1. check upper layer opcode version */
+	if (pBtReq->opCodeVer != 1) {
+		RTW_INFO("[MPT], Error!! Upper OP code version not match!!!\n");
+		pBtRsp->status = BT_STATUS_OPCODE_U_VERSION_MISMATCH;
+		return paraLen;
+	}
+	/* 2. check upper layer parameter length */
+	if (pBtReq->paraLength == sizeof(BT_TXRX_PARAMETERS)) {
+		RTW_INFO("[MPT], pTxRxPars->txrxChannel=0x%x\n", pTxRxPars->txrxChannel);
+		RTW_INFO("[MPT], pTxRxPars->txrxTxPktCnt=0x%8x\n", pTxRxPars->txrxTxPktCnt);
+		RTW_INFO("[MPT], pTxRxPars->txrxTxPktInterval=0x%x\n", pTxRxPars->txrxTxPktInterval);
+		RTW_INFO("[MPT], pTxRxPars->txrxPayloadType=0x%x\n", pTxRxPars->txrxPayloadType);
+		RTW_INFO("[MPT], pTxRxPars->txrxPktType=0x%x\n", pTxRxPars->txrxPktType);
+		RTW_INFO("[MPT], pTxRxPars->txrxPayloadLen=0x%x\n", pTxRxPars->txrxPayloadLen);
+		RTW_INFO("[MPT], pTxRxPars->txrxPktHeader=0x%x\n", pTxRxPars->txrxPktHeader);
+		RTW_INFO("[MPT], pTxRxPars->txrxWhitenCoeff=0x%x\n", pTxRxPars->txrxWhitenCoeff);
+		bdAddr[0] = pTxRxPars->txrxBdaddr[5];
+		bdAddr[1] = pTxRxPars->txrxBdaddr[4];
+		bdAddr[2] = pTxRxPars->txrxBdaddr[3];
+		bdAddr[3] = pTxRxPars->txrxBdaddr[2];
+		bdAddr[4] = pTxRxPars->txrxBdaddr[1];
+		bdAddr[5] = pTxRxPars->txrxBdaddr[0];
+		RTW_INFO("[MPT], pTxRxPars->txrxBdaddr: %s", &bdAddr[0]);
+		RTW_INFO("[MPT], pTxRxPars->txrxTxGainIndex=0x%x\n", pTxRxPars->txrxTxGainIndex);
+	} else {
+		RTW_INFO("[MPT], Error!! pBtReq->paraLength=%d, correct Len=%d\n", pBtReq->paraLength, lenTxRx);
+		pBtRsp->status = BT_STATUS_PARAMETER_FORMAT_ERROR_U;
+		return paraLen;
+	}
+
+	/*  */
+	/* execute lower layer opcodes */
+	/*  */
+
+	/* fill h2c parameters */
+	btOpcode = BT_LO_OP_SET_PKT_HEADER;
+	if (pTxRxPars->txrxPktHeader > 0x3ffff) {
+		RTW_INFO("[MPT], Error!! pTxRxPars->txrxPktHeader=0x%x is out of range, (should be between 0x0~0x3ffff)\n", pTxRxPars->txrxPktHeader);
+		pBtRsp->status = (btOpcode << 8) | BT_STATUS_PARAMETER_OUT_OF_RANGE_U;
+		return paraLen;
+	} else {
+		h2cParaBuf[0] = (u1Byte)(pTxRxPars->txrxPktHeader & 0xff);
+		h2cParaBuf[1] = (u1Byte)((pTxRxPars->txrxPktHeader & 0xff00) >> 8);
+		h2cParaBuf[2] = (u1Byte)((pTxRxPars->txrxPktHeader & 0xff0000) >> 16);
+		h2cParaLen = 3;
+		retStatus = mptbt_BtFwOpCodeProcess(Adapter, btOpcode, btOpcodeVer, &h2cParaBuf[0], h2cParaLen);
+	}
+
+	/* ckeck bt return status. */
+	if (BT_STATUS_BT_OP_SUCCESS != retStatus) {
+		pBtRsp->status = ((btOpcode << 8) | retStatus);
+		RTW_INFO("[MPT], Error!! status code=0x%x\n", pBtRsp->status);
+		return paraLen;
+	}
+
+	/* fill h2c parameters */
+	btOpcode = BT_LO_OP_SET_PKT_TYPE_LEN;
+	{
+		u2Byte	payloadLenLimit = 0;
+		switch (pTxRxPars->txrxPktType) {
+		case MP_BT_PKT_DH1:
+			payloadLenLimit = 27 * 8;
+			break;
+		case MP_BT_PKT_DH3:
+			payloadLenLimit = 183 * 8;
+			break;
+		case MP_BT_PKT_DH5:
+			payloadLenLimit = 339 * 8;
+			break;
+		case MP_BT_PKT_2DH1:
+			payloadLenLimit = 54 * 8;
+			break;
+		case MP_BT_PKT_2DH3:
+			payloadLenLimit = 367 * 8;
+			break;
+		case MP_BT_PKT_2DH5:
+			payloadLenLimit = 679 * 8;
+			break;
+		case MP_BT_PKT_3DH1:
+			payloadLenLimit = 83 * 8;
+			break;
+		case MP_BT_PKT_3DH3:
+			payloadLenLimit = 552 * 8;
+			break;
+		case MP_BT_PKT_3DH5:
+			payloadLenLimit = 1021 * 8;
+			break;
+		case MP_BT_PKT_LE:
+			payloadLenLimit = 39 * 8;
+			break;
+		default: {
+			RTW_INFO("[MPT], Error!! Unknown pTxRxPars->txrxPktType=0x%x\n", pTxRxPars->txrxPktType);
+			pBtRsp->status = (btOpcode << 8) | BT_STATUS_PARAMETER_OUT_OF_RANGE_U;
+			return paraLen;
+		}
+		break;
+		}
+
+		if (pTxRxPars->txrxPayloadLen > payloadLenLimit) {
+			RTW_INFO("[MPT], Error!! pTxRxPars->txrxPayloadLen=0x%x, (should smaller than %d)\n",
+				 pTxRxPars->txrxPayloadLen, payloadLenLimit);
+			pBtRsp->status = (btOpcode << 8) | BT_STATUS_PARAMETER_OUT_OF_RANGE_U;
+			return paraLen;
+		}
+
+		h2cParaBuf[0] = pTxRxPars->txrxPktType;
+		h2cParaBuf[1] = (u1Byte)((pTxRxPars->txrxPayloadLen & 0xff));
+		h2cParaBuf[2] = (u1Byte)((pTxRxPars->txrxPayloadLen & 0xff00) >> 8);
+		h2cParaLen = 3;
+		retStatus = mptbt_BtFwOpCodeProcess(Adapter, btOpcode, btOpcodeVer, &h2cParaBuf[0], h2cParaLen);
+	}
+
+	/* ckeck bt return status. */
+	if (BT_STATUS_BT_OP_SUCCESS != retStatus) {
+		pBtRsp->status = ((btOpcode << 8) | retStatus);
+		RTW_INFO("[MPT], Error!! status code=0x%x\n", pBtRsp->status);
+		return paraLen;
+	}
+
+	/* fill h2c parameters */
+	btOpcode = BT_LO_OP_SET_PKT_CNT_L_PL_TYPE;
+	if (pTxRxPars->txrxPayloadType > MP_BT_PAYLOAD_MAX) {
+		RTW_INFO("[MPT], Error!! pTxRxPars->txrxPayloadType=0x%x, (should be between 0~4)\n", pTxRxPars->txrxPayloadType);
+		pBtRsp->status = (btOpcode << 8) | BT_STATUS_PARAMETER_OUT_OF_RANGE_U;
+		return paraLen;
+	} else {
+		h2cParaBuf[0] = (u1Byte)((pTxRxPars->txrxTxPktCnt & 0xff));
+		h2cParaBuf[1] = (u1Byte)((pTxRxPars->txrxTxPktCnt & 0xff00) >> 8);
+		h2cParaBuf[2] = pTxRxPars->txrxPayloadType;
+		h2cParaLen = 3;
+		retStatus = mptbt_BtFwOpCodeProcess(Adapter, btOpcode, btOpcodeVer, &h2cParaBuf[0], h2cParaLen);
+	}
+
+	/* ckeck bt return status. */
+	if (BT_STATUS_BT_OP_SUCCESS != retStatus) {
+		pBtRsp->status = ((btOpcode << 8) | retStatus);
+		RTW_INFO("[MPT], Error!! status code=0x%x\n", pBtRsp->status);
+		return paraLen;
+	}
+
+	/* fill h2c parameters */
+	btOpcode = BT_LO_OP_SET_PKT_CNT_H_PKT_INTV;
+	if (pTxRxPars->txrxTxPktInterval > 15) {
+		RTW_INFO("[MPT], Error!! pTxRxPars->txrxTxPktInterval=0x%x, (should be between 0~15)\n", pTxRxPars->txrxTxPktInterval);
+		pBtRsp->status = (btOpcode << 8) | BT_STATUS_PARAMETER_OUT_OF_RANGE_U;
+		return paraLen;
+	} else {
+		h2cParaBuf[0] = (u1Byte)((pTxRxPars->txrxTxPktCnt & 0xff0000) >> 16);
+		h2cParaBuf[1] = (u1Byte)((pTxRxPars->txrxTxPktCnt & 0xff000000) >> 24);
+		h2cParaBuf[2] = pTxRxPars->txrxTxPktInterval;
+		h2cParaLen = 3;
+		retStatus = mptbt_BtFwOpCodeProcess(Adapter, btOpcode, btOpcodeVer, &h2cParaBuf[0], h2cParaLen);
+	}
+
+	/* ckeck bt return status. */
+	if (BT_STATUS_BT_OP_SUCCESS != retStatus) {
+		pBtRsp->status = ((btOpcode << 8) | retStatus);
+		RTW_INFO("[MPT], Error!! status code=0x%x\n", pBtRsp->status);
+		return paraLen;
+	}
+
+	/* fill h2c parameters */
+	btOpcode = BT_LO_OP_SET_WHITENCOEFF;
+	{
+		h2cParaBuf[0] = pTxRxPars->txrxWhitenCoeff;
+		h2cParaLen = 1;
+		retStatus = mptbt_BtFwOpCodeProcess(Adapter, btOpcode, btOpcodeVer, &h2cParaBuf[0], h2cParaLen);
+	}
+
+	/* ckeck bt return status. */
+	if (BT_STATUS_BT_OP_SUCCESS != retStatus) {
+		pBtRsp->status = ((btOpcode << 8) | retStatus);
+		RTW_INFO("[MPT], Error!! status code=0x%x\n", pBtRsp->status);
+		return paraLen;
+	}
+
+
+	/* fill h2c parameters */
+	btOpcode = BT_LO_OP_SET_CHNL_TX_GAIN;
+	if ((pTxRxPars->txrxChannel > 78) ||
+	    (pTxRxPars->txrxTxGainIndex > 7)) {
+		RTW_INFO("[MPT], Error!! pTxRxPars->txrxChannel=0x%x, (should be between 0~78)\n", pTxRxPars->txrxChannel);
+		RTW_INFO("[MPT], Error!! pTxRxPars->txrxTxGainIndex=0x%x, (should be between 0~7)\n", pTxRxPars->txrxTxGainIndex);
+		pBtRsp->status = (btOpcode << 8) | BT_STATUS_PARAMETER_OUT_OF_RANGE_U;
+		return paraLen;
+	} else {
+		h2cParaBuf[0] = pTxRxPars->txrxChannel;
+		h2cParaBuf[1] = pTxRxPars->txrxTxGainIndex;
+		h2cParaLen = 2;
+		retStatus = mptbt_BtFwOpCodeProcess(Adapter, btOpcode, btOpcodeVer, &h2cParaBuf[0], h2cParaLen);
+	}
+
+	/* ckeck bt return status. */
+	if (BT_STATUS_BT_OP_SUCCESS != retStatus) {
+		pBtRsp->status = ((btOpcode << 8) | retStatus);
+		RTW_INFO("[MPT], Error!! status code=0x%x\n", pBtRsp->status);
+		return paraLen;
+	}
+
+	/* fill h2c parameters */
+	btOpcode = BT_LO_OP_SET_BD_ADDR_L;
+	if ((pTxRxPars->txrxBdaddr[0] == 0) &&
+	    (pTxRxPars->txrxBdaddr[1] == 0) &&
+	    (pTxRxPars->txrxBdaddr[2] == 0) &&
+	    (pTxRxPars->txrxBdaddr[3] == 0) &&
+	    (pTxRxPars->txrxBdaddr[4] == 0) &&
+	    (pTxRxPars->txrxBdaddr[5] == 0)) {
+		RTW_INFO("[MPT], Error!! pTxRxPars->txrxBdaddr=all zero\n");
+		pBtRsp->status = (btOpcode << 8) | BT_STATUS_PARAMETER_OUT_OF_RANGE_U;
+		return paraLen;
+	}
+	if ((pTxRxPars->txrxBdaddr[0] == 0xff) &&
+	    (pTxRxPars->txrxBdaddr[1] == 0xff) &&
+	    (pTxRxPars->txrxBdaddr[2] == 0xff) &&
+	    (pTxRxPars->txrxBdaddr[3] == 0xff) &&
+	    (pTxRxPars->txrxBdaddr[4] == 0xff) &&
+	    (pTxRxPars->txrxBdaddr[5] == 0xff)) {
+		RTW_INFO("[MPT], Error!! pTxRxPars->txrxBdaddr=all 0xf\n");
+		pBtRsp->status = (btOpcode << 8) | BT_STATUS_PARAMETER_OUT_OF_RANGE_U;
+		return paraLen;
+	}
+
+	{
+		h2cParaBuf[0] = pTxRxPars->txrxBdaddr[0];
+		h2cParaBuf[1] = pTxRxPars->txrxBdaddr[1];
+		h2cParaBuf[2] = pTxRxPars->txrxBdaddr[2];
+		h2cParaLen = 3;
+		retStatus = mptbt_BtFwOpCodeProcess(Adapter, btOpcode, btOpcodeVer, &h2cParaBuf[0], h2cParaLen);
+	}
+	/* ckeck bt return status. */
+	if (BT_STATUS_BT_OP_SUCCESS != retStatus) {
+		pBtRsp->status = ((btOpcode << 8) | retStatus);
+		RTW_INFO("[MPT], Error!! status code=0x%x\n", pBtRsp->status);
+		return paraLen;
+	}
+
+	btOpcode = BT_LO_OP_SET_BD_ADDR_H;
+	{
+		h2cParaBuf[0] = pTxRxPars->txrxBdaddr[3];
+		h2cParaBuf[1] = pTxRxPars->txrxBdaddr[4];
+		h2cParaBuf[2] = pTxRxPars->txrxBdaddr[5];
+		h2cParaLen = 3;
+		retStatus = mptbt_BtFwOpCodeProcess(Adapter, btOpcode, btOpcodeVer, &h2cParaBuf[0], h2cParaLen);
+	}
+	/* ckeck bt return status. */
+	if (BT_STATUS_BT_OP_SUCCESS != retStatus) {
+		pBtRsp->status = ((btOpcode << 8) | retStatus);
+		RTW_INFO("[MPT], Error!! status code=0x%x\n", pBtRsp->status);
+		return paraLen;
+	}
+
+	pBtRsp->status = BT_STATUS_SUCCESS;
+	return paraLen;
+}
+
+
+
+u2Byte
+mptbt_BtTestCtrl(
+	IN	PADAPTER		Adapter,
+	IN	PBT_REQ_CMD	pBtReq,
+	IN	PBT_RSP_CMD	pBtRsp
+)
+{
+	u1Byte				h2cParaBuf[6] = {0};
+	u1Byte				h2cParaLen = 0;
+	u2Byte				paraLen = 0;
+	u1Byte				retStatus = BT_STATUS_BT_OP_SUCCESS;
+	u1Byte				btOpcode;
+	u1Byte				btOpcodeVer = 0;
+	u1Byte				testCtrl = 0;
+
+	/*  */
+	/* check upper layer parameters */
+	/*  */
+
+	/* 1. check upper layer opcode version */
+	if (pBtReq->opCodeVer != 1) {
+		RTW_INFO("[MPT], Error!! Upper OP code version not match!!!\n");
+		pBtRsp->status = BT_STATUS_OPCODE_U_VERSION_MISMATCH;
+		return paraLen;
+	}
+	/* 2. check upper layer parameter length */
+	if (1 == pBtReq->paraLength) {
+		testCtrl = pBtReq->pParamStart[0];
+		RTW_INFO("[MPT], testCtrl=%d\n", testCtrl);
+	} else {
+		RTW_INFO("[MPT], Error!! wrong parameter length=%d (should be 1)\n", pBtReq->paraLength);
+		pBtRsp->status = BT_STATUS_PARAMETER_FORMAT_ERROR_U;
+		return paraLen;
+	}
+
+	/*  */
+	/* execute lower layer opcodes */
+	/*  */
+
+	/* 1. fill h2c parameters	 */
+	/* check bt mode */
+	btOpcode = BT_LO_OP_TEST_CTRL;
+	if (testCtrl >= MP_BT_TEST_MAX) {
+		RTW_INFO("[MPT], Error!! testCtrl=0x%x, (should be between smaller or equal to 0x%x)\n",
+			 testCtrl, MP_BT_TEST_MAX - 1);
+		pBtRsp->status = BT_STATUS_PARAMETER_OUT_OF_RANGE_U;
+		return paraLen;
+	} else {
+		h2cParaBuf[0] = testCtrl;
+		h2cParaLen = 1;
+		retStatus = mptbt_BtFwOpCodeProcess(Adapter, btOpcode, btOpcodeVer, &h2cParaBuf[0], h2cParaLen);
+	}
+
+	/* 3. construct respond status code and data. */
+	if (BT_STATUS_BT_OP_SUCCESS != retStatus) {
+		pBtRsp->status = ((btOpcode << 8) | retStatus);
+		RTW_INFO("[MPT], Error!! status code=0x%x\n", pBtRsp->status);
+		return paraLen;
+	}
+
+	pBtRsp->status = BT_STATUS_SUCCESS;
+	return paraLen;
+}
+
+
+u2Byte
+mptbt_TestBT(
+	IN	PADAPTER		Adapter,
+	IN	PBT_REQ_CMD	pBtReq,
+	IN	PBT_RSP_CMD	pBtRsp
+)
+{
+
+	u1Byte				h2cParaBuf[6] = {0};
+	u1Byte				h2cParaLen = 0;
+	u2Byte				paraLen = 0;
+	u1Byte				retStatus = BT_STATUS_BT_OP_SUCCESS;
+	u1Byte				btOpcode;
+	u1Byte				btOpcodeVer = 0;
+	u1Byte				testCtrl = 0;
+
+	/* 1. fill h2c parameters	 */
+	btOpcode =  0x11;
+	h2cParaBuf[0] = 0x11;
+	h2cParaBuf[1] = 0x0;
+	h2cParaBuf[2] = 0x0;
+	h2cParaBuf[3] = 0x0;
+	h2cParaBuf[4] = 0x0;
+	h2cParaLen = 1;
+	/*	retStatus = mptbt_BtFwOpCodeProcess(Adapter, btOpcode, btOpcodeVer, &h2cParaBuf[0], h2cParaLen); */
+	retStatus = mptbt_BtFwOpCodeProcess(Adapter, btOpcode, btOpcodeVer, h2cParaBuf, h2cParaLen);
+
+
+	/* 3. construct respond status code and data. */
+	if (BT_STATUS_BT_OP_SUCCESS != retStatus) {
+		pBtRsp->status = ((btOpcode << 8) | retStatus);
+		RTW_INFO("[MPT], Error!! status code=0x%x\n", pBtRsp->status);
+		return paraLen;
+	}
+
+	pBtRsp->status = BT_STATUS_SUCCESS;
+	return paraLen;
+}
+
+VOID
+mptbt_BtControlProcess(
+	PADAPTER	Adapter,
+	PVOID		pInBuf
+)
+{
+	u1Byte			H2C_Parameter[6] = {0};
+	PBT_H2C		pH2c = (PBT_H2C)&H2C_Parameter[0];
+	PMPT_CONTEXT	pMptCtx = &(Adapter->mppriv.mpt_ctx);
+	PBT_REQ_CMD	pBtReq = (PBT_REQ_CMD)pInBuf;
+	PBT_RSP_CMD	pBtRsp;
+	u1Byte			i;
+
+
+	RTW_INFO("[MPT], mptbt_BtControlProcess()=========>\n");
+
+	RTW_INFO("[MPT], input opCodeVer=%d\n", pBtReq->opCodeVer);
+	RTW_INFO("[MPT], input OpCode=%d\n", pBtReq->OpCode);
+	RTW_INFO("[MPT], paraLength=%d\n", pBtReq->paraLength);
+	if (pBtReq->paraLength) {
+		/* RTW_INFO("[MPT], parameters(hex):0x%x %d\n",&pBtReq->pParamStart[0], pBtReq->paraLength); */
+	}
+
+	_rtw_memset((void *)pMptCtx->mptOutBuf, 0, 100);
+	pMptCtx->mptOutLen = 4; /* length of (BT_RSP_CMD.status+BT_RSP_CMD.paraLength) */
+
+	pBtRsp = (PBT_RSP_CMD)pMptCtx->mptOutBuf;
+	pBtRsp->status = BT_STATUS_SUCCESS;
+	pBtRsp->paraLength = 0x0;
+
+	/* The following we should maintain the User OP codes sent by upper layer */
+	switch (pBtReq->OpCode) {
+	case BT_UP_OP_BT_READY:
+		RTW_INFO("[MPT], OPcode : [BT_READY]\n");
+		pBtRsp->paraLength = mptbt_BtReady(Adapter, pBtReq, pBtRsp);
+		break;
+	case BT_UP_OP_BT_SET_MODE:
+		RTW_INFO("[MPT], OPcode : [BT_SET_MODE]\n");
+		pBtRsp->paraLength = mptbt_BtSetMode(Adapter, pBtReq, pBtRsp);
+		break;
+	case BT_UP_OP_BT_SET_TX_RX_PARAMETER:
+		RTW_INFO("[MPT], OPcode : [BT_SET_TXRX_PARAMETER]\n");
+		pBtRsp->paraLength = mptbt_BtSetTxRxPars(Adapter, pBtReq, pBtRsp);
+		break;
+	case BT_UP_OP_BT_SET_GENERAL:
+		RTW_INFO("[MPT], OPcode : [BT_SET_GENERAL]\n");
+		pBtRsp->paraLength = mptbt_BtSetGeneral(Adapter, pBtReq, pBtRsp);
+		break;
+	case BT_UP_OP_BT_GET_GENERAL:
+		RTW_INFO("[MPT], OPcode : [BT_GET_GENERAL]\n");
+		pBtRsp->paraLength = mptbt_BtGetGeneral(Adapter, pBtReq, pBtRsp);
+		break;
+	case BT_UP_OP_BT_TEST_CTRL:
+		RTW_INFO("[MPT], OPcode : [BT_TEST_CTRL]\n");
+		pBtRsp->paraLength = mptbt_BtTestCtrl(Adapter, pBtReq, pBtRsp);
+		break;
+	case BT_UP_OP_TEST_BT:
+		RTW_INFO("[MPT], OPcode : [TEST_BT]\n");
+		pBtRsp->paraLength = mptbt_TestBT(Adapter, pBtReq, pBtRsp);
+		break;
+	default:
+		RTW_INFO("[MPT], Error!! OPcode : UNDEFINED!!!!\n");
+		pBtRsp->status = BT_STATUS_UNKNOWN_OPCODE_U;
+		pBtRsp->paraLength = 0x0;
+		break;
+	}
+
+	pMptCtx->mptOutLen += pBtRsp->paraLength;
+
+	RTW_INFO("[MPT], pMptCtx->mptOutLen=%d, pBtRsp->paraLength=%d\n", pMptCtx->mptOutLen, pBtRsp->paraLength);
+	RTW_INFO("[MPT], mptbt_BtControlProcess()<=========\n");
+}
+
+#endif
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/core/rtw_chplan.c linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/core/rtw_chplan.c
--- linux-5.6.3/3rdparty/rtl8821ce/core/rtw_chplan.c	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/core/rtw_chplan.c	2020-04-10 16:35:06.772658013 +0300
@@ -0,0 +1,1184 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2018 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#define _RTW_CHPLAN_C_
+
+#include <drv_types.h>
+
+#define RTW_DOMAIN_MAP_VER	"35e"
+#define RTW_COUNTRY_MAP_VER	"20"
+
+#ifdef LEGACY_CHANNEL_PLAN_REF
+/********************************************************
+ChannelPlan definitions
+*********************************************************/
+static RT_CHANNEL_PLAN legacy_channel_plan[] = {
+	/* 0x00, RTW_CHPLAN_FCC */						{{1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 132, 136, 140, 149, 153, 157, 161, 165}, 32},
+	/* 0x01, RTW_CHPLAN_IC */						{{1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 136, 140, 149, 153, 157, 161, 165}, 31},
+	/* 0x02, RTW_CHPLAN_ETSI */						{{1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140}, 32},
+	/* 0x03, RTW_CHPLAN_SPAIN */						{{1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13}, 13},
+	/* 0x04, RTW_CHPLAN_FRANCE */					{{1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13}, 13},
+	/* 0x05, RTW_CHPLAN_MKK */						{{1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13}, 13},
+	/* 0x06, RTW_CHPLAN_MKK1 */						{{1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13}, 13},
+	/* 0x07, RTW_CHPLAN_ISRAEL */					{{1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 36, 40, 44, 48, 52, 56, 60, 64}, 21},
+	/* 0x08, RTW_CHPLAN_TELEC */						{{1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 36, 40, 44, 48, 52, 56, 60, 64}, 22},
+	/* 0x09, RTW_CHPLAN_GLOBAL_DOAMIN */			{{1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14}, 14},
+	/* 0x0A, RTW_CHPLAN_WORLD_WIDE_13 */			{{1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13}, 13},
+	/* 0x0B, RTW_CHPLAN_TAIWAN */					{{1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 56, 60, 64, 100, 104, 108, 112, 116, 136, 140, 149, 153, 157, 161, 165}, 26},
+	/* 0x0C, RTW_CHPLAN_CHINA */					{{1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 149, 153, 157, 161, 165}, 18},
+	/* 0x0D, RTW_CHPLAN_SINGAPORE_INDIA_MEXICO */	{{1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 36, 40, 44, 48, 52, 56, 60, 64, 149, 153, 157, 161, 165}, 24},
+	/* 0x0E, RTW_CHPLAN_KOREA */					{{1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 149, 153, 157, 161, 165}, 31},
+	/* 0x0F, RTW_CHPLAN_TURKEY */					{{1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 36, 40, 44, 48, 52, 56, 60, 64}, 19},
+	/* 0x10, RTW_CHPLAN_JAPAN */						{{1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140}, 32},
+	/* 0x11, RTW_CHPLAN_FCC_NO_DFS */				{{1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 36, 40, 44, 48, 149, 153, 157, 161, 165}, 20},
+	/* 0x12, RTW_CHPLAN_JAPAN_NO_DFS */				{{1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 36, 40, 44, 48}, 17},
+	/* 0x13, RTW_CHPLAN_WORLD_WIDE_5G */			{{1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 149, 153, 157, 161, 165}, 37},
+	/* 0x14, RTW_CHPLAN_TAIWAN_NO_DFS */			{{1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 56, 60, 64, 149, 153, 157, 161, 165}, 19},
+};
+#endif
+
+enum rtw_rd_2g {
+	RTW_RD_2G_NULL = 0,
+	RTW_RD_2G_WORLD = 1,	/* Worldwird 13 */
+	RTW_RD_2G_ETSI1 = 2,	/* Europe */
+	RTW_RD_2G_FCC1 = 3,		/* US */
+	RTW_RD_2G_MKK1 = 4,		/* Japan */
+	RTW_RD_2G_ETSI2 = 5,	/* France */
+	RTW_RD_2G_GLOBAL = 6,	/* Global domain */
+	RTW_RD_2G_MKK2 = 7,		/* Japan */
+	RTW_RD_2G_FCC2 = 8,		/* US */
+	RTW_RD_2G_IC1 = 9,		/* Canada */
+	RTW_RD_2G_WORLD1 = 10,	/* Worldwide 11 */
+	RTW_RD_2G_KCC1 = 11,	/* Korea */
+
+	RTW_RD_2G_MAX,
+};
+
+enum rtw_rd_5g {
+	RTW_RD_5G_NULL = 0,		/*	*/
+	RTW_RD_5G_ETSI1 = 1,	/* Europe */
+	RTW_RD_5G_ETSI2 = 2,	/* Australia, New Zealand */
+	RTW_RD_5G_ETSI3 = 3,	/* Russia */
+	RTW_RD_5G_FCC1 = 4,		/* US */
+	RTW_RD_5G_FCC2 = 5,		/* FCC w/o DFS Channels */
+	RTW_RD_5G_FCC3 = 6,		/* Bolivia, Chile, El Salvador, Venezuela */
+	RTW_RD_5G_FCC4 = 7,		/* Venezuela */
+	RTW_RD_5G_FCC5 = 8,		/* China */
+	RTW_RD_5G_FCC6 = 9,		/*	*/
+	RTW_RD_5G_FCC7 = 10,	/* US(w/o Weather radar) */
+	RTW_RD_5G_IC1 = 11,		/* Canada(w/o Weather radar) */
+	RTW_RD_5G_KCC1 = 12,	/* Korea */
+	RTW_RD_5G_MKK1 = 13,	/* Japan */
+	RTW_RD_5G_MKK2 = 14,	/* Japan (W52, W53) */
+	RTW_RD_5G_MKK3 = 15,	/* Japan (W56) */
+	RTW_RD_5G_NCC1 = 16,	/* Taiwan, (w/o Weather radar) */
+	RTW_RD_5G_NCC2 = 17,	/* Taiwan, Band2, Band4 */
+	RTW_RD_5G_NCC3 = 18,	/* Taiwan w/o DFS, Band4 only */
+	RTW_RD_5G_ETSI4 = 19,	/* Europe w/o DFS, Band1 only */
+	RTW_RD_5G_ETSI5 = 20,	/* Australia, New Zealand(w/o Weather radar) */
+	RTW_RD_5G_FCC8 = 21,	/* Latin America */
+	RTW_RD_5G_ETSI6 = 22,	/* Israel, Bahrain, Egypt, India, China, Malaysia */
+	RTW_RD_5G_ETSI7 = 23,	/* China */
+	RTW_RD_5G_ETSI8 = 24,	/* Jordan */
+	RTW_RD_5G_ETSI9 = 25,	/* Lebanon */
+	RTW_RD_5G_ETSI10 = 26,	/* Qatar */
+	RTW_RD_5G_ETSI11 = 27,	/* Russia */
+	RTW_RD_5G_NCC4 = 28,	/* Taiwan, (w/o Weather radar) */
+	RTW_RD_5G_ETSI12 = 29,	/* Indonesia */
+	RTW_RD_5G_FCC9 = 30,	/* (w/o Weather radar) */
+	RTW_RD_5G_ETSI13 = 31,	/* (w/o Weather radar) */
+	RTW_RD_5G_FCC10 = 32,	/* Argentina(w/o Weather radar) */
+	RTW_RD_5G_MKK4 = 33,	/* Japan (W52) */
+	RTW_RD_5G_ETSI14 = 34,	/* Russia */
+	RTW_RD_5G_FCC11 = 35,	/* US(include CH144) */
+	RTW_RD_5G_ETSI15 = 36,	/* Malaysia */
+	RTW_RD_5G_MKK5 = 37,	/* Japan */
+	RTW_RD_5G_ETSI16 = 38,	/* Europe */
+	RTW_RD_5G_ETSI17 = 39,	/* Europe */
+	RTW_RD_5G_FCC12 = 40,	/* FCC */
+	RTW_RD_5G_FCC13 = 41,	/* FCC */
+	RTW_RD_5G_FCC14 = 42,	/* FCC w/o Weather radar(w/o 5600~5650MHz) */
+	RTW_RD_5G_FCC15 = 43,	/* FCC w/o Band3 */
+	RTW_RD_5G_FCC16 = 44,	/* FCC w/o Band3 */
+	RTW_RD_5G_ETSI18 = 45,	/* ETSI w/o DFS Band2&3 */
+	RTW_RD_5G_ETSI19 = 46,	/* Europe */
+	RTW_RD_5G_FCC17 = 47,	/* FCC w/o Weather radar(w/o 5600~5650MHz) */
+	RTW_RD_5G_ETSI20 = 48,	/* Europe */
+	RTW_RD_5G_IC2 = 49,		/* Canada(w/o Weather radar), include ch144 */
+	RTW_RD_5G_ETSI21 = 50,	/* Australia, New Zealand(w/o Weather radar) */
+	RTW_RD_5G_FCC18 = 51,	/*  */
+	RTW_RD_5G_WORLD = 52,	/* Worldwide */
+	RTW_RD_5G_CHILE1 = 53,	/* Chile */
+	RTW_RD_5G_ACMA1 = 54,	/* Australia, New Zealand (w/o Weather radar) (w/o Ch120~Ch128) */
+	RTW_RD_5G_WORLD1 = 55,	/* 5G Worldwide Band1&2 */
+	RTW_RD_5G_CHILE2 = 56,	/* Chile (Band2,Band3) */
+	RTW_RD_5G_KCC2 = 57,	/* Korea (New standard) */
+
+	/* === Below are driver defined for legacy channel plan compatible, DON'T assign index ==== */
+	RTW_RD_5G_OLD_FCC1,
+	RTW_RD_5G_OLD_NCC1,
+	RTW_RD_5G_OLD_KCC1,
+
+	RTW_RD_5G_MAX,
+};
+
+struct ch_list_t {
+	u8 *len_ch;
+};
+
+#define CH_LIST_ENT(_len, arg...) \
+	{.len_ch = (u8[_len + 1]) {_len, ##arg}, }
+
+#define CH_LIST_LEN(_ch_list) (_ch_list.len_ch[0])
+#define CH_LIST_CH(_ch_list, _i) (_ch_list.len_ch[_i + 1])
+
+struct chplan_ent_t {
+	u8 rd_2g;
+#ifdef CONFIG_IEEE80211_BAND_5GHZ
+	u8 rd_5g;
+#endif
+	u8 regd; /* value of REGULATION_TXPWR_LMT */
+};
+
+#ifdef CONFIG_IEEE80211_BAND_5GHZ
+#define CHPLAN_ENT(i2g, i5g, regd) {i2g, i5g, regd}
+#else
+#define CHPLAN_ENT(i2g, i5g, regd) {i2g, regd}
+#endif
+
+static struct ch_list_t RTW_ChannelPlan2G[] = {
+	/* 0, RTW_RD_2G_NULL */		CH_LIST_ENT(0),
+	/* 1, RTW_RD_2G_WORLD */	CH_LIST_ENT(13, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13),
+	/* 2, RTW_RD_2G_ETSI1 */		CH_LIST_ENT(13, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13),
+	/* 3, RTW_RD_2G_FCC1 */		CH_LIST_ENT(11, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11),
+	/* 4, RTW_RD_2G_MKK1 */		CH_LIST_ENT(14, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14),
+	/* 5, RTW_RD_2G_ETSI2 */		CH_LIST_ENT(4, 10, 11, 12, 13),
+	/* 6, RTW_RD_2G_GLOBAL */	CH_LIST_ENT(14, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14),
+	/* 7, RTW_RD_2G_MKK2 */		CH_LIST_ENT(13, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13),
+	/* 8, RTW_RD_2G_FCC2 */		CH_LIST_ENT(13, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13),
+	/* 9, RTW_RD_2G_IC1 */		CH_LIST_ENT(13, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13),
+	/* 10, RTW_RD_2G_WORLD1 */	CH_LIST_ENT(11, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11),
+	/* 11, RTW_RD_2G_KCC1 */	CH_LIST_ENT(13, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13),
+};
+
+#ifdef CONFIG_IEEE80211_BAND_5GHZ
+static struct ch_list_t RTW_ChannelPlan5G[] = {
+	/* 0, RTW_RD_5G_NULL */		CH_LIST_ENT(0),
+	/* 1, RTW_RD_5G_ETSI1 */		CH_LIST_ENT(19, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140),
+	/* 2, RTW_RD_5G_ETSI2 */		CH_LIST_ENT(24, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 149, 153, 157, 161, 165),
+	/* 3, RTW_RD_5G_ETSI3 */		CH_LIST_ENT(22, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 128, 132, 149, 153, 157, 161, 165),
+	/* 4, RTW_RD_5G_FCC1 */		CH_LIST_ENT(24, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 149, 153, 157, 161, 165),
+	/* 5, RTW_RD_5G_FCC2 */		CH_LIST_ENT(9, 36, 40, 44, 48, 149, 153, 157, 161, 165),
+	/* 6, RTW_RD_5G_FCC3 */		CH_LIST_ENT(13, 36, 40, 44, 48, 52, 56, 60, 64, 149, 153, 157, 161, 165),
+	/* 7, RTW_RD_5G_FCC4 */		CH_LIST_ENT(12, 36, 40, 44, 48, 52, 56, 60, 64, 149, 153, 157, 161),
+	/* 8, RTW_RD_5G_FCC5 */		CH_LIST_ENT(5, 149, 153, 157, 161, 165),
+	/* 9, RTW_RD_5G_FCC6 */		CH_LIST_ENT(8, 36, 40, 44, 48, 52, 56, 60, 64),
+	/* 10, RTW_RD_5G_FCC7 */	CH_LIST_ENT(21, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 132, 136, 140, 149, 153, 157, 161, 165),
+	/* 11, RTW_RD_5G_IC1 */		CH_LIST_ENT(21, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 132, 136, 140, 149, 153, 157, 161, 165),
+	/* 12, RTW_RD_5G_KCC1 */	CH_LIST_ENT(19, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 149, 153, 157, 161),
+	/* 13, RTW_RD_5G_MKK1 */	CH_LIST_ENT(19, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140),
+	/* 14, RTW_RD_5G_MKK2 */	CH_LIST_ENT(8, 36, 40, 44, 48, 52, 56, 60, 64),
+	/* 15, RTW_RD_5G_MKK3 */	CH_LIST_ENT(11, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140),
+	/* 16, RTW_RD_5G_NCC1 */	CH_LIST_ENT(16, 56, 60, 64, 100, 104, 108, 112, 116, 132, 136, 140, 149, 153, 157, 161, 165),
+	/* 17, RTW_RD_5G_NCC2 */	CH_LIST_ENT(8, 56, 60, 64, 149, 153, 157, 161, 165),
+	/* 18, RTW_RD_5G_NCC3 */	CH_LIST_ENT(5, 149, 153, 157, 161, 165),
+	/* 19, RTW_RD_5G_ETSI4 */	CH_LIST_ENT(4, 36, 40, 44, 48),
+	/* 20, RTW_RD_5G_ETSI5 */	CH_LIST_ENT(21, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 132, 136, 140, 149, 153, 157, 161, 165),
+	/* 21, RTW_RD_5G_FCC8 */	CH_LIST_ENT(4, 149, 153, 157, 161),
+	/* 22, RTW_RD_5G_ETSI6 */	CH_LIST_ENT(8, 36, 40, 44, 48, 52, 56, 60, 64),
+	/* 23, RTW_RD_5G_ETSI7 */	CH_LIST_ENT(13, 36, 40, 44, 48, 52, 56, 60, 64, 149, 153, 157, 161, 165),
+	/* 24, RTW_RD_5G_ETSI8 */	CH_LIST_ENT(9, 36, 40, 44, 48, 149, 153, 157, 161, 165),
+	/* 25, RTW_RD_5G_ETSI9 */	CH_LIST_ENT(11, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140),
+	/* 26, RTW_RD_5G_ETSI10 */	CH_LIST_ENT(5, 149, 153, 157, 161, 165),
+	/* 27, RTW_RD_5G_ETSI11 */	CH_LIST_ENT(16, 36, 40, 44, 48, 52, 56, 60, 64, 132, 136, 140, 149, 153, 157, 161, 165),
+	/* 28, RTW_RD_5G_NCC4 */	CH_LIST_ENT(17, 52, 56, 60, 64, 100, 104, 108, 112, 116, 132, 136, 140, 149, 153, 157, 161, 165),
+	/* 29, RTW_RD_5G_ETSI12 */	CH_LIST_ENT(4, 149, 153, 157, 161),
+	/* 30, RTW_RD_5G_FCC9 */	CH_LIST_ENT(21, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 132, 136, 140, 149, 153, 157, 161, 165),
+	/* 31, RTW_RD_5G_ETSI13 */	CH_LIST_ENT(16, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 132, 136, 140),
+	/* 32, RTW_RD_5G_FCC10 */	CH_LIST_ENT(20, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 132, 136, 140, 149, 153, 157, 161),
+	/* 33, RTW_RD_5G_MKK4 */	CH_LIST_ENT(4, 36, 40, 44, 48),
+	/* 34, RTW_RD_5G_ETSI14 */	CH_LIST_ENT(11, 36, 40, 44, 48, 52, 56, 60, 64, 132, 136, 140),
+	/* 35, RTW_RD_5G_FCC11 */	CH_LIST_ENT(25, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 144, 149, 153, 157, 161, 165),
+	/* 36, RTW_RD_5G_ETSI15 */	CH_LIST_ENT(21, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 128, 149, 153, 157, 161, 165),
+	/* 37, RTW_RD_5G_MKK5 */	CH_LIST_ENT(24, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 149, 153, 157, 161, 165),
+	/* 38, RTW_RD_5G_ETSI16 */	CH_LIST_ENT(24, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 149, 153, 157, 161, 165),
+	/* 39, RTW_RD_5G_ETSI17 */	CH_LIST_ENT(24, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 149, 153, 157, 161, 165),
+	/* 40, RTW_RD_5G_FCC12*/	CH_LIST_ENT(24, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 149, 153, 157, 161, 165),
+	/* 41, RTW_RD_5G_FCC13 */	CH_LIST_ENT(24, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 149, 153, 157, 161, 165),
+	/* 42, RTW_RD_5G_FCC14 */	CH_LIST_ENT(21, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 132, 136, 140, 149, 153, 157, 161, 165),
+	/* 43, RTW_RD_5G_FCC15 */	CH_LIST_ENT(13, 36, 40, 44, 48, 52, 56, 60, 64, 149, 153, 157, 161, 165),
+	/* 44, RTW_RD_5G_FCC16 */	CH_LIST_ENT(13, 36, 40, 44, 48, 52, 56, 60, 64, 149, 153, 157, 161, 165),
+	/* 45, RTW_RD_5G_ETSI18 */	CH_LIST_ENT(9, 36, 40, 44, 48, 149, 153, 157, 161, 165),
+	/* 46, RTW_RD_5G_ETSI19 */	CH_LIST_ENT(24, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 149, 153, 157, 161, 165),
+	/* 47, RTW_RD_5G_FCC17 */	CH_LIST_ENT(16, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 132, 136, 140),
+	/* 48, RTW_RD_5G_ETSI20 */	CH_LIST_ENT(9, 52, 56, 60, 64, 149, 153, 157, 161, 165),
+	/* 49, RTW_RD_5G_IC2 */		CH_LIST_ENT(22, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 132, 136, 140, 144, 149, 153, 157, 161, 165),
+	/* 50, RTW_RD_5G_ETSI21 */	CH_LIST_ENT(13, 100, 104, 108, 112, 116, 132, 136, 140, 149, 153, 157, 161, 165),
+	/* 51, RTW_RD_5G_FCC18 */	CH_LIST_ENT(8, 100, 104, 108, 112, 116, 132, 136, 140),
+	/* 52, RTW_RD_5G_WORLD */	CH_LIST_ENT(25, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 144, 149, 153, 157, 161, 165),
+	/* 53, RTW_RD_5G_CHILE1 */	CH_LIST_ENT(25, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 144, 149, 153, 157, 161, 165),
+	/* 54, RTW_RD_5G_ACMA1 */	CH_LIST_ENT(21, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 132, 136, 140, 149, 153, 157, 161, 165),
+	/* 55, RTW_RD_5G_WORLD1 */	CH_LIST_ENT(8, 36, 40, 44, 48, 52, 56, 60, 64),
+	/* 56, RTW_RD_5G_CHILE2 */	CH_LIST_ENT(16, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 144),
+	/* 57, RTW_RD_5G_KCC2 */	CH_LIST_ENT(24, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 149, 153, 157, 161, 165),
+
+	/* === Below are driver defined for legacy channel plan compatible, NO static index assigned ==== */
+	/* RTW_RD_5G_OLD_FCC1 */	CH_LIST_ENT(20, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 136, 140, 149, 153, 157, 161, 165),
+	/* RTW_RD_5G_OLD_NCC1 */	CH_LIST_ENT(15, 56, 60, 64, 100, 104, 108, 112, 116, 136, 140, 149, 153, 157, 161, 165),
+	/* RTW_RD_5G_OLD_KCC1 */	CH_LIST_ENT(20, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 149, 153, 157, 161, 165),
+};
+#endif /* CONFIG_IEEE80211_BAND_5GHZ */
+
+static struct chplan_ent_t RTW_ChannelPlanMap[RTW_CHPLAN_MAX] = {
+	/* ===== 0x00 ~ 0x1F, legacy channel plan ===== */
+	CHPLAN_ENT(RTW_RD_2G_FCC1,		RTW_RD_5G_KCC1,		TXPWR_LMT_FCC),		/* 0x00, RTW_CHPLAN_FCC */
+	CHPLAN_ENT(RTW_RD_2G_FCC1,		RTW_RD_5G_OLD_FCC1,	TXPWR_LMT_FCC),		/* 0x01, RTW_CHPLAN_IC */
+	CHPLAN_ENT(RTW_RD_2G_ETSI1,		RTW_RD_5G_ETSI1,	TXPWR_LMT_ETSI),	/* 0x02, RTW_CHPLAN_ETSI */
+	CHPLAN_ENT(RTW_RD_2G_ETSI1,		RTW_RD_5G_NULL,		TXPWR_LMT_ETSI),	/* 0x03, RTW_CHPLAN_SPAIN */
+	CHPLAN_ENT(RTW_RD_2G_ETSI1,		RTW_RD_5G_NULL,		TXPWR_LMT_ETSI),	/* 0x04, RTW_CHPLAN_FRANCE */
+	CHPLAN_ENT(RTW_RD_2G_MKK1,		RTW_RD_5G_NULL,		TXPWR_LMT_MKK),		/* 0x05, RTW_CHPLAN_MKK */
+	CHPLAN_ENT(RTW_RD_2G_MKK1,		RTW_RD_5G_NULL,		TXPWR_LMT_MKK),		/* 0x06, RTW_CHPLAN_MKK1 */
+	CHPLAN_ENT(RTW_RD_2G_ETSI1,		RTW_RD_5G_FCC6,		TXPWR_LMT_ETSI),	/* 0x07, RTW_CHPLAN_ISRAEL */
+	CHPLAN_ENT(RTW_RD_2G_MKK1,		RTW_RD_5G_FCC6,		TXPWR_LMT_MKK),		/* 0x08, RTW_CHPLAN_TELEC */
+	CHPLAN_ENT(RTW_RD_2G_MKK1,		RTW_RD_5G_NULL,		TXPWR_LMT_WW),		/* 0x09, RTW_CHPLAN_GLOBAL_DOAMIN */
+	CHPLAN_ENT(RTW_RD_2G_WORLD,		RTW_RD_5G_NULL,		TXPWR_LMT_WW),		/* 0x0A, RTW_CHPLAN_WORLD_WIDE_13 */
+	CHPLAN_ENT(RTW_RD_2G_FCC1,		RTW_RD_5G_OLD_NCC1,	TXPWR_LMT_FCC),		/* 0x0B, RTW_CHPLAN_TAIWAN */
+	CHPLAN_ENT(RTW_RD_2G_ETSI1,		RTW_RD_5G_FCC5,		TXPWR_LMT_ETSI),	/* 0x0C, RTW_CHPLAN_CHINA */
+	CHPLAN_ENT(RTW_RD_2G_FCC1,		RTW_RD_5G_FCC3,		TXPWR_LMT_WW),		/* 0x0D, RTW_CHPLAN_SINGAPORE_INDIA_MEXICO */ /* ETSI:Singapore, India. FCC:Mexico => WW */
+	CHPLAN_ENT(RTW_RD_2G_FCC1,		RTW_RD_5G_OLD_KCC1,	TXPWR_LMT_ETSI),	/* 0x0E, RTW_CHPLAN_KOREA */
+	CHPLAN_ENT(RTW_RD_2G_FCC1,		RTW_RD_5G_FCC6,		TXPWR_LMT_ETSI),	/* 0x0F, RTW_CHPLAN_TURKEY */
+	CHPLAN_ENT(RTW_RD_2G_ETSI1,		RTW_RD_5G_ETSI1,	TXPWR_LMT_MKK),		/* 0x10, RTW_CHPLAN_JAPAN */
+	CHPLAN_ENT(RTW_RD_2G_FCC1,		RTW_RD_5G_FCC2,		TXPWR_LMT_FCC),		/* 0x11, RTW_CHPLAN_FCC_NO_DFS */
+	CHPLAN_ENT(RTW_RD_2G_ETSI1,		RTW_RD_5G_FCC7,		TXPWR_LMT_MKK),		/* 0x12, RTW_CHPLAN_JAPAN_NO_DFS */
+	CHPLAN_ENT(RTW_RD_2G_WORLD,		RTW_RD_5G_FCC1,		TXPWR_LMT_WW),		/* 0x13, RTW_CHPLAN_WORLD_WIDE_5G */
+	CHPLAN_ENT(RTW_RD_2G_FCC1,		RTW_RD_5G_NCC2,		TXPWR_LMT_FCC),		/* 0x14, RTW_CHPLAN_TAIWAN_NO_DFS */
+	CHPLAN_ENT(RTW_RD_2G_WORLD,		RTW_RD_5G_FCC7,		TXPWR_LMT_ETSI),	/* 0x15, RTW_CHPLAN_ETSI_NO_DFS */
+	CHPLAN_ENT(RTW_RD_2G_WORLD,		RTW_RD_5G_NCC1,		TXPWR_LMT_ETSI),	/* 0x16, RTW_CHPLAN_KOREA_NO_DFS */
+	CHPLAN_ENT(RTW_RD_2G_MKK1,		RTW_RD_5G_FCC7,		TXPWR_LMT_MKK),		/* 0x17, RTW_CHPLAN_JAPAN_NO_DFS */
+	CHPLAN_ENT(RTW_RD_2G_NULL,		RTW_RD_5G_FCC5,		TXPWR_LMT_ETSI),	/* 0x18, RTW_CHPLAN_PAKISTAN_NO_DFS */
+	CHPLAN_ENT(RTW_RD_2G_FCC1,		RTW_RD_5G_FCC5,		TXPWR_LMT_FCC),		/* 0x19, RTW_CHPLAN_TAIWAN2_NO_DFS */
+	CHPLAN_ENT(RTW_RD_2G_NULL,		RTW_RD_5G_NULL,		TXPWR_LMT_WW),		/* 0x1A, */
+	CHPLAN_ENT(RTW_RD_2G_NULL,		RTW_RD_5G_NULL,		TXPWR_LMT_WW),		/* 0x1B, */
+	CHPLAN_ENT(RTW_RD_2G_NULL,		RTW_RD_5G_NULL,		TXPWR_LMT_WW),		/* 0x1C, */
+	CHPLAN_ENT(RTW_RD_2G_NULL,		RTW_RD_5G_NULL,		TXPWR_LMT_WW),		/* 0x1D, */
+	CHPLAN_ENT(RTW_RD_2G_NULL,		RTW_RD_5G_NULL,		TXPWR_LMT_WW),		/* 0x1E, */
+	CHPLAN_ENT(RTW_RD_2G_NULL,		RTW_RD_5G_FCC1,		TXPWR_LMT_WW),		/* 0x1F, RTW_CHPLAN_WORLD_WIDE_ONLY_5G */
+
+	/* ===== 0x20 ~ 0x7F, new channel plan ===== */
+	CHPLAN_ENT(RTW_RD_2G_WORLD,		RTW_RD_5G_NULL,		TXPWR_LMT_WW),		/* 0x20, RTW_CHPLAN_WORLD_NULL */
+	CHPLAN_ENT(RTW_RD_2G_ETSI1,		RTW_RD_5G_NULL,		TXPWR_LMT_ETSI),	/* 0x21, RTW_CHPLAN_ETSI1_NULL */
+	CHPLAN_ENT(RTW_RD_2G_FCC1,		RTW_RD_5G_NULL,		TXPWR_LMT_FCC),		/* 0x22, RTW_CHPLAN_FCC1_NULL */
+	CHPLAN_ENT(RTW_RD_2G_MKK1,		RTW_RD_5G_NULL,		TXPWR_LMT_MKK),		/* 0x23, RTW_CHPLAN_MKK1_NULL */
+	CHPLAN_ENT(RTW_RD_2G_ETSI2,		RTW_RD_5G_NULL,		TXPWR_LMT_ETSI),	/* 0x24, RTW_CHPLAN_ETSI2_NULL */
+	CHPLAN_ENT(RTW_RD_2G_FCC1,		RTW_RD_5G_FCC1,		TXPWR_LMT_FCC),		/* 0x25, RTW_CHPLAN_FCC1_FCC1 */
+	CHPLAN_ENT(RTW_RD_2G_WORLD,		RTW_RD_5G_ETSI1,	TXPWR_LMT_ETSI),	/* 0x26, RTW_CHPLAN_WORLD_ETSI1 */
+	CHPLAN_ENT(RTW_RD_2G_MKK1,		RTW_RD_5G_MKK1,		TXPWR_LMT_MKK),		/* 0x27, RTW_CHPLAN_MKK1_MKK1 */
+	CHPLAN_ENT(RTW_RD_2G_WORLD,		RTW_RD_5G_KCC1,		TXPWR_LMT_KCC),		/* 0x28, RTW_CHPLAN_WORLD_KCC1 */
+	CHPLAN_ENT(RTW_RD_2G_WORLD,		RTW_RD_5G_FCC2,		TXPWR_LMT_FCC),		/* 0x29, RTW_CHPLAN_WORLD_FCC2 */
+	CHPLAN_ENT(RTW_RD_2G_FCC2,		RTW_RD_5G_NULL,		TXPWR_LMT_FCC),		/* 0x2A, RTW_CHPLAN_FCC2_NULL */
+	CHPLAN_ENT(RTW_RD_2G_IC1,		RTW_RD_5G_IC2,		TXPWR_LMT_IC),		/* 0x2B, RTW_CHPLAN_IC1_IC2 */
+	CHPLAN_ENT(RTW_RD_2G_MKK2,		RTW_RD_5G_NULL,		TXPWR_LMT_MKK),		/* 0x2C, RTW_CHPLAN_MKK2_NULL */
+	CHPLAN_ENT(RTW_RD_2G_WORLD,		RTW_RD_5G_CHILE1,	TXPWR_LMT_CHILE),	/* 0x2D, RTW_CHPLAN_WORLD_CHILE1 */
+	CHPLAN_ENT(RTW_RD_2G_WORLD1,	RTW_RD_5G_WORLD1,	TXPWR_LMT_WW),		/* 0x2E, RTW_CHPLAN_WORLD1_WORLD1 */
+	CHPLAN_ENT(RTW_RD_2G_WORLD,		RTW_RD_5G_CHILE2,	TXPWR_LMT_CHILE),	/* 0x2F, RTW_CHPLAN_WORLD_CHILE2 */
+	CHPLAN_ENT(RTW_RD_2G_WORLD,		RTW_RD_5G_FCC3,		TXPWR_LMT_FCC),		/* 0x30, RTW_CHPLAN_WORLD_FCC3 */
+	CHPLAN_ENT(RTW_RD_2G_WORLD,		RTW_RD_5G_FCC4,		TXPWR_LMT_FCC),		/* 0x31, RTW_CHPLAN_WORLD_FCC4 */
+	CHPLAN_ENT(RTW_RD_2G_WORLD,		RTW_RD_5G_FCC5,		TXPWR_LMT_FCC),		/* 0x32, RTW_CHPLAN_WORLD_FCC5 */
+	CHPLAN_ENT(RTW_RD_2G_WORLD,		RTW_RD_5G_FCC6,		TXPWR_LMT_FCC),		/* 0x33, RTW_CHPLAN_WORLD_FCC6 */
+	CHPLAN_ENT(RTW_RD_2G_FCC1,		RTW_RD_5G_FCC7,		TXPWR_LMT_FCC),		/* 0x34, RTW_CHPLAN_FCC1_FCC7 */
+	CHPLAN_ENT(RTW_RD_2G_WORLD,		RTW_RD_5G_ETSI2,	TXPWR_LMT_ETSI),	/* 0x35, RTW_CHPLAN_WORLD_ETSI2 */
+	CHPLAN_ENT(RTW_RD_2G_WORLD,		RTW_RD_5G_ETSI3,	TXPWR_LMT_ETSI),	/* 0x36, RTW_CHPLAN_WORLD_ETSI3 */
+	CHPLAN_ENT(RTW_RD_2G_MKK1,		RTW_RD_5G_MKK2,		TXPWR_LMT_MKK),		/* 0x37, RTW_CHPLAN_MKK1_MKK2 */
+	CHPLAN_ENT(RTW_RD_2G_MKK1,		RTW_RD_5G_MKK3,		TXPWR_LMT_MKK),		/* 0x38, RTW_CHPLAN_MKK1_MKK3 */
+	CHPLAN_ENT(RTW_RD_2G_FCC1,		RTW_RD_5G_NCC1,		TXPWR_LMT_FCC),		/* 0x39, RTW_CHPLAN_FCC1_NCC1 */
+	CHPLAN_ENT(RTW_RD_2G_ETSI1,		RTW_RD_5G_ETSI1,	TXPWR_LMT_ETSI),	/* 0x3A, RTW_CHPLAN_ETSI1_ETSI1 */
+	CHPLAN_ENT(RTW_RD_2G_ETSI1,		RTW_RD_5G_ACMA1,	TXPWR_LMT_ACMA),	/* 0x3B, RTW_CHPLAN_ETSI1_ACMA1 */
+	CHPLAN_ENT(RTW_RD_2G_ETSI1,		RTW_RD_5G_ETSI6,	TXPWR_LMT_ETSI),	/* 0x3C, RTW_CHPLAN_ETSI1_ETSI6 */
+	CHPLAN_ENT(RTW_RD_2G_ETSI1,		RTW_RD_5G_ETSI12,	TXPWR_LMT_ETSI),	/* 0x3D, RTW_CHPLAN_ETSI1_ETSI12 */
+	CHPLAN_ENT(RTW_RD_2G_KCC1,		RTW_RD_5G_KCC2,		TXPWR_LMT_KCC),		/* 0x3E, RTW_CHPLAN_KCC1_KCC2 */
+	CHPLAN_ENT(RTW_RD_2G_NULL,		RTW_RD_5G_NULL,		TXPWR_LMT_WW),		/* 0x3F, */
+	CHPLAN_ENT(RTW_RD_2G_FCC1,		RTW_RD_5G_NCC2,		TXPWR_LMT_FCC),		/* 0x40, RTW_CHPLAN_FCC1_NCC2 */
+	CHPLAN_ENT(RTW_RD_2G_GLOBAL,	RTW_RD_5G_NULL,		TXPWR_LMT_WW),		/* 0x41, RTW_CHPLAN_GLOBAL_NULL */
+	CHPLAN_ENT(RTW_RD_2G_ETSI1,		RTW_RD_5G_ETSI4,	TXPWR_LMT_ETSI),	/* 0x42, RTW_CHPLAN_ETSI1_ETSI4 */
+	CHPLAN_ENT(RTW_RD_2G_FCC1,		RTW_RD_5G_FCC2,		TXPWR_LMT_FCC),		/* 0x43, RTW_CHPLAN_FCC1_FCC2 */
+	CHPLAN_ENT(RTW_RD_2G_FCC1,		RTW_RD_5G_NCC3,		TXPWR_LMT_FCC),		/* 0x44, RTW_CHPLAN_FCC1_NCC3 */
+	CHPLAN_ENT(RTW_RD_2G_WORLD,		RTW_RD_5G_ACMA1,	TXPWR_LMT_ACMA),	/* 0x45, RTW_CHPLAN_WORLD_ACMA1 */
+	CHPLAN_ENT(RTW_RD_2G_FCC1,		RTW_RD_5G_FCC8,		TXPWR_LMT_FCC),		/* 0x46, RTW_CHPLAN_FCC1_FCC8 */
+	CHPLAN_ENT(RTW_RD_2G_WORLD,		RTW_RD_5G_ETSI6,	TXPWR_LMT_ETSI),	/* 0x47, RTW_CHPLAN_WORLD_ETSI6 */
+	CHPLAN_ENT(RTW_RD_2G_WORLD,		RTW_RD_5G_ETSI7,	TXPWR_LMT_ETSI),	/* 0x48, RTW_CHPLAN_WORLD_ETSI7 */
+	CHPLAN_ENT(RTW_RD_2G_WORLD,		RTW_RD_5G_ETSI8,	TXPWR_LMT_ETSI),	/* 0x49, RTW_CHPLAN_WORLD_ETSI8 */
+	CHPLAN_ENT(RTW_RD_2G_NULL,		RTW_RD_5G_NULL,		TXPWR_LMT_WW),		/* 0x4A, */
+	CHPLAN_ENT(RTW_RD_2G_NULL,		RTW_RD_5G_NULL,		TXPWR_LMT_WW),		/* 0x4B, */
+	CHPLAN_ENT(RTW_RD_2G_NULL,		RTW_RD_5G_NULL,		TXPWR_LMT_WW),		/* 0x4C, */
+	CHPLAN_ENT(RTW_RD_2G_NULL,		RTW_RD_5G_NULL,		TXPWR_LMT_WW),		/* 0x4D, */
+	CHPLAN_ENT(RTW_RD_2G_NULL,		RTW_RD_5G_NULL,		TXPWR_LMT_WW),		/* 0x4E, */
+	CHPLAN_ENT(RTW_RD_2G_NULL,		RTW_RD_5G_NULL,		TXPWR_LMT_WW),		/* 0x4F, */
+	CHPLAN_ENT(RTW_RD_2G_WORLD,		RTW_RD_5G_ETSI9,	TXPWR_LMT_ETSI),	/* 0x50, RTW_CHPLAN_WORLD_ETSI9 */
+	CHPLAN_ENT(RTW_RD_2G_WORLD,		RTW_RD_5G_ETSI10,	TXPWR_LMT_ETSI),	/* 0x51, RTW_CHPLAN_WORLD_ETSI10 */
+	CHPLAN_ENT(RTW_RD_2G_WORLD,		RTW_RD_5G_ETSI11,	TXPWR_LMT_ETSI),	/* 0x52, RTW_CHPLAN_WORLD_ETSI11 */
+	CHPLAN_ENT(RTW_RD_2G_FCC1,		RTW_RD_5G_NCC4,		TXPWR_LMT_FCC),		/* 0x53, RTW_CHPLAN_FCC1_NCC4 */
+	CHPLAN_ENT(RTW_RD_2G_WORLD,		RTW_RD_5G_ETSI12,	TXPWR_LMT_ETSI),	/* 0x54, RTW_CHPLAN_WORLD_ETSI12 */
+	CHPLAN_ENT(RTW_RD_2G_FCC1,		RTW_RD_5G_FCC9,		TXPWR_LMT_FCC),		/* 0x55, RTW_CHPLAN_FCC1_FCC9 */
+	CHPLAN_ENT(RTW_RD_2G_WORLD,		RTW_RD_5G_ETSI13,	TXPWR_LMT_ETSI),	/* 0x56, RTW_CHPLAN_WORLD_ETSI13 */
+	CHPLAN_ENT(RTW_RD_2G_FCC1,		RTW_RD_5G_FCC10,	TXPWR_LMT_FCC),		/* 0x57, RTW_CHPLAN_FCC1_FCC10 */
+	CHPLAN_ENT(RTW_RD_2G_MKK2,		RTW_RD_5G_MKK4,		TXPWR_LMT_MKK),		/* 0x58, RTW_CHPLAN_MKK2_MKK4 */
+	CHPLAN_ENT(RTW_RD_2G_WORLD,		RTW_RD_5G_ETSI14,	TXPWR_LMT_ETSI),	/* 0x59, RTW_CHPLAN_WORLD_ETSI14 */
+	CHPLAN_ENT(RTW_RD_2G_NULL,		RTW_RD_5G_NULL,		TXPWR_LMT_WW),		/* 0x5A, */
+	CHPLAN_ENT(RTW_RD_2G_NULL,		RTW_RD_5G_NULL,		TXPWR_LMT_WW),		/* 0x5B, */
+	CHPLAN_ENT(RTW_RD_2G_NULL,		RTW_RD_5G_NULL,		TXPWR_LMT_WW),		/* 0x5C, */
+	CHPLAN_ENT(RTW_RD_2G_NULL,		RTW_RD_5G_NULL,		TXPWR_LMT_WW),		/* 0x5D, */
+	CHPLAN_ENT(RTW_RD_2G_NULL,		RTW_RD_5G_NULL,		TXPWR_LMT_WW),		/* 0x5E, */
+	CHPLAN_ENT(RTW_RD_2G_NULL,		RTW_RD_5G_NULL,		TXPWR_LMT_WW),		/* 0x5F, */
+	CHPLAN_ENT(RTW_RD_2G_FCC1,		RTW_RD_5G_FCC5,		TXPWR_LMT_FCC),		/* 0x60, RTW_CHPLAN_FCC1_FCC5 */
+	CHPLAN_ENT(RTW_RD_2G_FCC2,		RTW_RD_5G_FCC7,		TXPWR_LMT_FCC),		/* 0x61, RTW_CHPLAN_FCC2_FCC7 */
+	CHPLAN_ENT(RTW_RD_2G_FCC2,		RTW_RD_5G_FCC1,		TXPWR_LMT_FCC),		/* 0x62, RTW_CHPLAN_FCC2_FCC1 */
+	CHPLAN_ENT(RTW_RD_2G_WORLD,		RTW_RD_5G_ETSI15,	TXPWR_LMT_ETSI),	/* 0x63, RTW_CHPLAN_WORLD_ETSI15 */
+	CHPLAN_ENT(RTW_RD_2G_MKK2,		RTW_RD_5G_MKK5,		TXPWR_LMT_MKK),		/* 0x64, RTW_CHPLAN_MKK2_MKK5 */
+	CHPLAN_ENT(RTW_RD_2G_ETSI1,		RTW_RD_5G_ETSI16,	TXPWR_LMT_ETSI),	/* 0x65, RTW_CHPLAN_ETSI1_ETSI16 */
+	CHPLAN_ENT(RTW_RD_2G_FCC1,		RTW_RD_5G_FCC14,	TXPWR_LMT_FCC),		/* 0x66, RTW_CHPLAN_FCC1_FCC14 */
+	CHPLAN_ENT(RTW_RD_2G_FCC1,		RTW_RD_5G_FCC12,	TXPWR_LMT_FCC),		/* 0x67, RTW_CHPLAN_FCC1_FCC12 */
+	CHPLAN_ENT(RTW_RD_2G_FCC2,		RTW_RD_5G_FCC14,	TXPWR_LMT_FCC),		/* 0x68, RTW_CHPLAN_FCC2_FCC14 */
+	CHPLAN_ENT(RTW_RD_2G_FCC2,		RTW_RD_5G_FCC12,	TXPWR_LMT_FCC),		/* 0x69, RTW_CHPLAN_FCC2_FCC12 */
+	CHPLAN_ENT(RTW_RD_2G_ETSI1,		RTW_RD_5G_ETSI17,	TXPWR_LMT_ETSI),	/* 0x6A, RTW_CHPLAN_ETSI1_ETSI17 */
+	CHPLAN_ENT(RTW_RD_2G_WORLD,		RTW_RD_5G_FCC16,	TXPWR_LMT_FCC),		/* 0x6B, RTW_CHPLAN_WORLD_FCC16 */
+	CHPLAN_ENT(RTW_RD_2G_WORLD,		RTW_RD_5G_FCC13,	TXPWR_LMT_FCC),		/* 0x6C, RTW_CHPLAN_WORLD_FCC13 */
+	CHPLAN_ENT(RTW_RD_2G_FCC2,		RTW_RD_5G_FCC15,	TXPWR_LMT_FCC),		/* 0x6D, RTW_CHPLAN_FCC2_FCC15 */
+	CHPLAN_ENT(RTW_RD_2G_WORLD,		RTW_RD_5G_FCC12,	TXPWR_LMT_FCC),		/* 0x6E, RTW_CHPLAN_WORLD_FCC12 */
+	CHPLAN_ENT(RTW_RD_2G_NULL,		RTW_RD_5G_ETSI8,	TXPWR_LMT_ETSI),	/* 0x6F, RTW_CHPLAN_NULL_ETSI8 */
+	CHPLAN_ENT(RTW_RD_2G_NULL,		RTW_RD_5G_ETSI18,	TXPWR_LMT_ETSI),	/* 0x70, RTW_CHPLAN_NULL_ETSI18 */
+	CHPLAN_ENT(RTW_RD_2G_NULL,		RTW_RD_5G_ETSI17,	TXPWR_LMT_ETSI),	/* 0x71, RTW_CHPLAN_NULL_ETSI17 */
+	CHPLAN_ENT(RTW_RD_2G_NULL,		RTW_RD_5G_ETSI19,	TXPWR_LMT_ETSI),	/* 0x72, RTW_CHPLAN_NULL_ETSI19 */
+	CHPLAN_ENT(RTW_RD_2G_WORLD,		RTW_RD_5G_FCC7,		TXPWR_LMT_FCC),		/* 0x73, RTW_CHPLAN_WORLD_FCC7 */
+	CHPLAN_ENT(RTW_RD_2G_FCC2,		RTW_RD_5G_FCC17,	TXPWR_LMT_FCC),		/* 0x74, RTW_CHPLAN_FCC2_FCC17 */
+	CHPLAN_ENT(RTW_RD_2G_WORLD,		RTW_RD_5G_ETSI20,	TXPWR_LMT_ETSI),	/* 0x75, RTW_CHPLAN_WORLD_ETSI20 */
+	CHPLAN_ENT(RTW_RD_2G_FCC2,		RTW_RD_5G_FCC11,	TXPWR_LMT_FCC),		/* 0x76, RTW_CHPLAN_FCC2_FCC11 */
+	CHPLAN_ENT(RTW_RD_2G_WORLD,		RTW_RD_5G_ETSI21,	TXPWR_LMT_ETSI),	/* 0x77, RTW_CHPLAN_WORLD_ETSI21 */
+	CHPLAN_ENT(RTW_RD_2G_FCC1,		RTW_RD_5G_FCC18,	TXPWR_LMT_FCC),		/* 0x78, RTW_CHPLAN_FCC1_FCC18 */
+	CHPLAN_ENT(RTW_RD_2G_MKK2,		RTW_RD_5G_MKK1,		TXPWR_LMT_MKK),		/* 0x79, RTW_CHPLAN_MKK2_MKK1 */
+};
+
+static struct chplan_ent_t RTW_CHANNEL_PLAN_MAP_REALTEK_DEFINE =
+	CHPLAN_ENT(RTW_RD_2G_WORLD,		RTW_RD_5G_FCC1,		TXPWR_LMT_FCC);		/* 0x7F, Realtek Define */
+
+u8 rtw_chplan_get_default_regd(u8 id)
+{
+	u8 regd;
+
+	if (id == RTW_CHPLAN_REALTEK_DEFINE)
+		regd = RTW_CHANNEL_PLAN_MAP_REALTEK_DEFINE.regd;
+	else
+		regd = RTW_ChannelPlanMap[id].regd;
+
+	return regd;
+}
+
+bool rtw_chplan_is_empty(u8 id)
+{
+	struct chplan_ent_t *chplan_map;
+
+	if (id == RTW_CHPLAN_REALTEK_DEFINE)
+		chplan_map = &RTW_CHANNEL_PLAN_MAP_REALTEK_DEFINE;
+	else
+		chplan_map = &RTW_ChannelPlanMap[id];
+
+	if (chplan_map->rd_2g == RTW_RD_2G_NULL
+		#ifdef CONFIG_IEEE80211_BAND_5GHZ
+		&& chplan_map->rd_5g == RTW_RD_5G_NULL
+		#endif
+	)
+		return _TRUE;
+
+	return _FALSE;
+}
+
+bool rtw_regsty_is_excl_chs(struct registry_priv *regsty, u8 ch)
+{
+	int i;
+
+	for (i = 0; i < MAX_CHANNEL_NUM; i++) {
+		if (regsty->excl_chs[i] == 0)
+			break;
+		if (regsty->excl_chs[i] == ch)
+			return _TRUE;
+	}
+	return _FALSE;
+}
+
+inline static u8 rtw_rd_5g_band1_passive(u8 rtw_rd_5g)
+{
+	u8 passive = 0;
+
+	switch (rtw_rd_5g) {
+	case RTW_RD_5G_FCC13:
+	case RTW_RD_5G_FCC16:
+	case RTW_RD_5G_ETSI18:
+	case RTW_RD_5G_ETSI19:
+	case RTW_RD_5G_WORLD:
+	case RTW_RD_5G_WORLD1:
+		passive = 1;
+	};
+
+	return passive;
+}
+
+inline static u8 rtw_rd_5g_band4_passive(u8 rtw_rd_5g)
+{
+	u8 passive = 0;
+
+	switch (rtw_rd_5g) {
+	case RTW_RD_5G_MKK5:
+	case RTW_RD_5G_ETSI16:
+	case RTW_RD_5G_ETSI18:
+	case RTW_RD_5G_ETSI19:
+	case RTW_RD_5G_WORLD:
+		passive = 1;
+	};
+
+	return passive;
+}
+
+u8 init_channel_set(_adapter *padapter, u8 ChannelPlan, RT_CHANNEL_INFO *channel_set)
+{
+	struct registry_priv *regsty = adapter_to_regsty(padapter);
+	u8	index, chanset_size = 0;
+	u8	b5GBand = _FALSE, b2_4GBand = _FALSE;
+	u8	rd_2g = 0, rd_5g = 0;
+#ifdef CONFIG_DFS_MASTER
+	int i;
+#endif
+
+	if (!rtw_is_channel_plan_valid(ChannelPlan)) {
+		RTW_ERR("ChannelPlan ID 0x%02X error !!!!!\n", ChannelPlan);
+		return chanset_size;
+	}
+
+	_rtw_memset(channel_set, 0, sizeof(RT_CHANNEL_INFO) * MAX_CHANNEL_NUM);
+
+	if (IsSupported24G(regsty->wireless_mode) && hal_chk_band_cap(padapter, BAND_CAP_2G))
+		b2_4GBand = _TRUE;
+
+	if (is_supported_5g(regsty->wireless_mode) && hal_chk_band_cap(padapter, BAND_CAP_5G))
+		b5GBand = _TRUE;
+
+	if (b2_4GBand == _FALSE && b5GBand == _FALSE) {
+		RTW_WARN("HW band_cap has no intersection with SW wireless_mode setting\n");
+		return chanset_size;
+	}
+
+	if (b2_4GBand) {
+		if (ChannelPlan == RTW_CHPLAN_REALTEK_DEFINE)
+			rd_2g = RTW_CHANNEL_PLAN_MAP_REALTEK_DEFINE.rd_2g;
+		else
+			rd_2g = RTW_ChannelPlanMap[ChannelPlan].rd_2g;
+
+		for (index = 0; index < CH_LIST_LEN(RTW_ChannelPlan2G[rd_2g]); index++) {
+			if (rtw_regsty_is_excl_chs(regsty, CH_LIST_CH(RTW_ChannelPlan2G[rd_2g], index)) == _TRUE)
+				continue;
+
+			if (chanset_size >= MAX_CHANNEL_NUM) {
+				RTW_WARN("chset size can't exceed MAX_CHANNEL_NUM(%u)\n", MAX_CHANNEL_NUM);
+				break;
+			}
+
+			channel_set[chanset_size].ChannelNum = CH_LIST_CH(RTW_ChannelPlan2G[rd_2g], index);
+
+			if (ChannelPlan == RTW_CHPLAN_GLOBAL_DOAMIN
+				|| rd_2g == RTW_RD_2G_GLOBAL
+			) {
+				/* Channel 1~11 is active, and 12~14 is passive */
+				if (channel_set[chanset_size].ChannelNum >= 1 && channel_set[chanset_size].ChannelNum <= 11)
+					channel_set[chanset_size].ScanType = SCAN_ACTIVE;
+				else if ((channel_set[chanset_size].ChannelNum  >= 12 && channel_set[chanset_size].ChannelNum  <= 14))
+					channel_set[chanset_size].ScanType  = SCAN_PASSIVE;
+			} else if (ChannelPlan == RTW_CHPLAN_WORLD_WIDE_13
+				|| ChannelPlan == RTW_CHPLAN_WORLD_WIDE_5G
+				|| rd_2g == RTW_RD_2G_WORLD
+			) {
+				/* channel 12~13, passive scan */
+				if (channel_set[chanset_size].ChannelNum <= 11)
+					channel_set[chanset_size].ScanType = SCAN_ACTIVE;
+				else
+					channel_set[chanset_size].ScanType = SCAN_PASSIVE;
+			} else
+				channel_set[chanset_size].ScanType = SCAN_ACTIVE;
+
+			chanset_size++;
+		}
+	}
+
+#ifdef CONFIG_IEEE80211_BAND_5GHZ
+	if (b5GBand) {
+		if (ChannelPlan == RTW_CHPLAN_REALTEK_DEFINE)
+			rd_5g = RTW_CHANNEL_PLAN_MAP_REALTEK_DEFINE.rd_5g;
+		else
+			rd_5g = RTW_ChannelPlanMap[ChannelPlan].rd_5g;
+
+		for (index = 0; index < CH_LIST_LEN(RTW_ChannelPlan5G[rd_5g]); index++) {
+			if (rtw_regsty_is_excl_chs(regsty, CH_LIST_CH(RTW_ChannelPlan5G[rd_5g], index)) == _TRUE)
+				continue;
+			#ifndef CONFIG_DFS
+			if (rtw_is_dfs_ch(CH_LIST_CH(RTW_ChannelPlan5G[rd_5g], index)))
+				continue;
+			#endif
+
+			if (chanset_size >= MAX_CHANNEL_NUM) {
+				RTW_WARN("chset size can't exceed MAX_CHANNEL_NUM(%u)\n", MAX_CHANNEL_NUM);
+				break;
+			}
+
+			channel_set[chanset_size].ChannelNum = CH_LIST_CH(RTW_ChannelPlan5G[rd_5g], index);
+
+			if ((ChannelPlan == RTW_CHPLAN_WORLD_WIDE_5G) /* all channels passive */
+				|| (rtw_is_5g_band1(channel_set[chanset_size].ChannelNum)
+					&& rtw_rd_5g_band1_passive(rd_5g)) /* band1 passive */
+				|| (rtw_is_5g_band4(channel_set[chanset_size].ChannelNum)
+					&& rtw_rd_5g_band4_passive(rd_5g)) /* band4 passive */
+				|| (rtw_is_dfs_ch(channel_set[chanset_size].ChannelNum)) /* DFS channel(band2, 3) passive */
+			)
+				channel_set[chanset_size].ScanType = SCAN_PASSIVE;
+			else
+				channel_set[chanset_size].ScanType = SCAN_ACTIVE;
+
+			chanset_size++;
+		}
+	}
+
+	#ifdef CONFIG_DFS_MASTER
+	for (i = 0; i < chanset_size; i++)
+		channel_set[i].non_ocp_end_time = rtw_get_current_time();
+	#endif
+#endif /* CONFIG_IEEE80211_BAND_5GHZ */
+
+	if (chanset_size)
+		RTW_INFO(FUNC_ADPT_FMT" ChannelPlan ID:0x%02x, ch num:%d\n"
+			, FUNC_ADPT_ARG(padapter), ChannelPlan, chanset_size);
+	else
+		RTW_WARN(FUNC_ADPT_FMT" ChannelPlan ID:0x%02x, final chset has no channel\n"
+			, FUNC_ADPT_ARG(padapter), ChannelPlan);
+
+	return chanset_size;
+}
+
+#ifdef CONFIG_80211AC_VHT
+#define COUNTRY_CHPLAN_ASSIGN_EN_11AC(_val) , .en_11ac = (_val)
+#else
+#define COUNTRY_CHPLAN_ASSIGN_EN_11AC(_val)
+#endif
+
+#if RTW_DEF_MODULE_REGULATORY_CERT
+#define COUNTRY_CHPLAN_ASSIGN_DEF_MODULE_FLAGS(_val) , .def_module_flags = (_val)
+#else
+#define COUNTRY_CHPLAN_ASSIGN_DEF_MODULE_FLAGS(_val)
+#endif
+
+/* has def_module_flags specified, used by common map and HAL dfference map */
+#define COUNTRY_CHPLAN_ENT(_alpha2, _chplan, _en_11ac, _def_module_flags) \
+	{.alpha2 = (_alpha2), .chplan = (_chplan) \
+		COUNTRY_CHPLAN_ASSIGN_EN_11AC(_en_11ac) \
+		COUNTRY_CHPLAN_ASSIGN_DEF_MODULE_FLAGS(_def_module_flags) \
+	}
+
+#ifdef CONFIG_CUSTOMIZED_COUNTRY_CHPLAN_MAP
+
+#include "../platform/custom_country_chplan.h"
+
+#elif RTW_DEF_MODULE_REGULATORY_CERT
+
+/* leave def_module_flags empty, def_module_flags check is done on country_chplan_map */
+#if (RTW_DEF_MODULE_REGULATORY_CERT & RTW_MODULE_RTL8821AE_HMC_M2) /* 2013 certify */
+static const struct country_chplan RTL8821AE_HMC_M2_country_chplan_exc_map[] = {
+	COUNTRY_CHPLAN_ENT("CA", 0x34, 1, 0), /* Canada */
+	COUNTRY_CHPLAN_ENT("CL", 0x30, 1, 0), /* Chile */
+	COUNTRY_CHPLAN_ENT("CN", 0x51, 1, 0), /* China */
+	COUNTRY_CHPLAN_ENT("CO", 0x34, 1, 0), /* Colombia */
+	COUNTRY_CHPLAN_ENT("CR", 0x34, 1, 0), /* Costa Rica */
+	COUNTRY_CHPLAN_ENT("DO", 0x34, 1, 0), /* Dominican Republic */
+	COUNTRY_CHPLAN_ENT("EC", 0x34, 1, 0), /* Ecuador */
+	COUNTRY_CHPLAN_ENT("GT", 0x34, 1, 0), /* Guatemala */
+	COUNTRY_CHPLAN_ENT("KR", 0x28, 1, 0), /* South Korea */
+	COUNTRY_CHPLAN_ENT("MX", 0x34, 1, 0), /* Mexico */
+	COUNTRY_CHPLAN_ENT("MY", 0x47, 1, 0), /* Malaysia */
+	COUNTRY_CHPLAN_ENT("NI", 0x34, 1, 0), /* Nicaragua */
+	COUNTRY_CHPLAN_ENT("PA", 0x34, 1, 0), /* Panama */
+	COUNTRY_CHPLAN_ENT("PE", 0x34, 1, 0), /* Peru */
+	COUNTRY_CHPLAN_ENT("PR", 0x34, 1, 0), /* Puerto Rico */
+	COUNTRY_CHPLAN_ENT("PY", 0x34, 1, 0), /* Paraguay */
+	COUNTRY_CHPLAN_ENT("TW", 0x39, 1, 0), /* Taiwan */
+	COUNTRY_CHPLAN_ENT("UA", 0x36, 0, 0), /* Ukraine */
+	COUNTRY_CHPLAN_ENT("US", 0x34, 1, 0), /* United States of America (USA) */
+};
+#endif
+
+#if (RTW_DEF_MODULE_REGULATORY_CERT & RTW_MODULE_RTL8821AU) /* 2014 certify */
+static const struct country_chplan RTL8821AU_country_chplan_exc_map[] = {
+	COUNTRY_CHPLAN_ENT("CA", 0x34, 1, 0), /* Canada */
+	COUNTRY_CHPLAN_ENT("KR", 0x28, 1, 0), /* South Korea */
+	COUNTRY_CHPLAN_ENT("RU", 0x59, 0, 0), /* Russia(fac/gost), Kaliningrad */
+	COUNTRY_CHPLAN_ENT("TW", 0x39, 1, 0), /* Taiwan */
+	COUNTRY_CHPLAN_ENT("UA", 0x36, 0, 0), /* Ukraine */
+	COUNTRY_CHPLAN_ENT("US", 0x34, 1, 0), /* United States of America (USA) */
+};
+#endif
+
+#if (RTW_DEF_MODULE_REGULATORY_CERT & RTW_MODULE_RTL8812AENF_NGFF) /* 2014 certify */
+static const struct country_chplan RTL8812AENF_NGFF_country_chplan_exc_map[] = {
+	COUNTRY_CHPLAN_ENT("TW", 0x39, 1, 0), /* Taiwan */
+	COUNTRY_CHPLAN_ENT("US", 0x34, 1, 0), /* United States of America (USA) */
+};
+#endif
+
+#if (RTW_DEF_MODULE_REGULATORY_CERT & RTW_MODULE_RTL8812AEBT_HMC) /* 2013 certify */
+static const struct country_chplan RTL8812AEBT_HMC_country_chplan_exc_map[] = {
+	COUNTRY_CHPLAN_ENT("CA", 0x34, 1, 0), /* Canada */
+	COUNTRY_CHPLAN_ENT("KR", 0x28, 1, 0), /* South Korea */
+	COUNTRY_CHPLAN_ENT("RU", 0x59, 0, 0), /* Russia(fac/gost), Kaliningrad */
+	COUNTRY_CHPLAN_ENT("TW", 0x39, 1, 0), /* Taiwan */
+	COUNTRY_CHPLAN_ENT("UA", 0x36, 0, 0), /* Ukraine */
+	COUNTRY_CHPLAN_ENT("US", 0x34, 1, 0), /* United States of America (USA) */
+};
+#endif
+
+#if (RTW_DEF_MODULE_REGULATORY_CERT & RTW_MODULE_RTL8188EE_HMC_M2) /* 2012 certify */
+static const struct country_chplan RTL8188EE_HMC_M2_country_chplan_exc_map[] = {
+	COUNTRY_CHPLAN_ENT("AW", 0x34, 1, 0), /* Aruba */
+	COUNTRY_CHPLAN_ENT("BB", 0x34, 1, 0), /* Barbados */
+	COUNTRY_CHPLAN_ENT("CA", 0x20, 1, 0), /* Canada */
+	COUNTRY_CHPLAN_ENT("CO", 0x34, 1, 0), /* Colombia */
+	COUNTRY_CHPLAN_ENT("CR", 0x34, 1, 0), /* Costa Rica */
+	COUNTRY_CHPLAN_ENT("DO", 0x34, 1, 0), /* Dominican Republic */
+	COUNTRY_CHPLAN_ENT("EC", 0x34, 1, 0), /* Ecuador */
+	COUNTRY_CHPLAN_ENT("GT", 0x34, 1, 0), /* Guatemala */
+	COUNTRY_CHPLAN_ENT("HT", 0x34, 1, 0), /* Haiti */
+	COUNTRY_CHPLAN_ENT("KR", 0x28, 1, 0), /* South Korea */
+	COUNTRY_CHPLAN_ENT("MX", 0x34, 1, 0), /* Mexico */
+	COUNTRY_CHPLAN_ENT("NI", 0x34, 1, 0), /* Nicaragua */
+	COUNTRY_CHPLAN_ENT("PA", 0x34, 1, 0), /* Panama */
+	COUNTRY_CHPLAN_ENT("PE", 0x34, 1, 0), /* Peru */
+	COUNTRY_CHPLAN_ENT("PR", 0x34, 1, 0), /* Puerto Rico */
+	COUNTRY_CHPLAN_ENT("PY", 0x34, 1, 0), /* Paraguay */
+	COUNTRY_CHPLAN_ENT("SC", 0x34, 1, 0), /* Seychelles */
+	COUNTRY_CHPLAN_ENT("TW", 0x39, 1, 0), /* Taiwan */
+	COUNTRY_CHPLAN_ENT("US", 0x34, 1, 0), /* United States of America (USA) */
+	COUNTRY_CHPLAN_ENT("VC", 0x34, 1, 0), /* Saint Vincent and the Grenadines */
+};
+#endif
+
+#if (RTW_DEF_MODULE_REGULATORY_CERT & RTW_MODULE_RTL8723BE_HMC_M2) /* 2013 certify */
+static const struct country_chplan RTL8723BE_HMC_M2_country_chplan_exc_map[] = {
+	COUNTRY_CHPLAN_ENT("AW", 0x34, 1, 0), /* Aruba */
+	COUNTRY_CHPLAN_ENT("BS", 0x34, 1, 0), /* Bahamas */
+	COUNTRY_CHPLAN_ENT("CA", 0x20, 1, 0), /* Canada */
+	COUNTRY_CHPLAN_ENT("CO", 0x34, 1, 0), /* Colombia */
+	COUNTRY_CHPLAN_ENT("CR", 0x34, 1, 0), /* Costa Rica */
+	COUNTRY_CHPLAN_ENT("DO", 0x34, 1, 0), /* Dominican Republic */
+	COUNTRY_CHPLAN_ENT("EC", 0x34, 1, 0), /* Ecuador */
+	COUNTRY_CHPLAN_ENT("GT", 0x34, 1, 0), /* Guatemala */
+	COUNTRY_CHPLAN_ENT("KR", 0x28, 1, 0), /* South Korea */
+	COUNTRY_CHPLAN_ENT("MX", 0x34, 1, 0), /* Mexico */
+	COUNTRY_CHPLAN_ENT("NI", 0x34, 1, 0), /* Nicaragua */
+	COUNTRY_CHPLAN_ENT("PA", 0x34, 1, 0), /* Panama */
+	COUNTRY_CHPLAN_ENT("PE", 0x34, 1, 0), /* Peru */
+	COUNTRY_CHPLAN_ENT("PR", 0x34, 1, 0), /* Puerto Rico */
+	COUNTRY_CHPLAN_ENT("PY", 0x34, 1, 0), /* Paraguay */
+	COUNTRY_CHPLAN_ENT("TW", 0x39, 1, 0), /* Taiwan */
+	COUNTRY_CHPLAN_ENT("US", 0x34, 1, 0), /* United States of America (USA) */
+};
+#endif
+
+#if (RTW_DEF_MODULE_REGULATORY_CERT & RTW_MODULE_RTL8723BS_NGFF1216) /* 2014 certify */
+static const struct country_chplan RTL8723BS_NGFF1216_country_chplan_exc_map[] = {
+	COUNTRY_CHPLAN_ENT("BB", 0x34, 1, 0), /* Barbados */
+	COUNTRY_CHPLAN_ENT("CA", 0x20, 1, 0), /* Canada */
+	COUNTRY_CHPLAN_ENT("CO", 0x34, 1, 0), /* Colombia */
+	COUNTRY_CHPLAN_ENT("CR", 0x34, 1, 0), /* Costa Rica */
+	COUNTRY_CHPLAN_ENT("DO", 0x34, 1, 0), /* Dominican Republic */
+	COUNTRY_CHPLAN_ENT("EC", 0x34, 1, 0), /* Ecuador */
+	COUNTRY_CHPLAN_ENT("GT", 0x34, 1, 0), /* Guatemala */
+	COUNTRY_CHPLAN_ENT("HT", 0x34, 1, 0), /* Haiti */
+	COUNTRY_CHPLAN_ENT("KR", 0x28, 1, 0), /* South Korea */
+	COUNTRY_CHPLAN_ENT("MX", 0x34, 1, 0), /* Mexico */
+	COUNTRY_CHPLAN_ENT("NI", 0x34, 1, 0), /* Nicaragua */
+	COUNTRY_CHPLAN_ENT("PA", 0x34, 1, 0), /* Panama */
+	COUNTRY_CHPLAN_ENT("PE", 0x34, 1, 0), /* Peru */
+	COUNTRY_CHPLAN_ENT("PR", 0x34, 1, 0), /* Puerto Rico */
+	COUNTRY_CHPLAN_ENT("PY", 0x34, 1, 0), /* Paraguay */
+	COUNTRY_CHPLAN_ENT("TW", 0x39, 1, 0), /* Taiwan */
+	COUNTRY_CHPLAN_ENT("US", 0x34, 1, 0), /* United States of America (USA) */
+};
+#endif
+
+#if (RTW_DEF_MODULE_REGULATORY_CERT & RTW_MODULE_RTL8192EEBT_HMC_M2) /* 2013 certify */
+static const struct country_chplan RTL8192EEBT_HMC_M2_country_chplan_exc_map[] = {
+	COUNTRY_CHPLAN_ENT("AW", 0x34, 1, 0), /* Aruba */
+	COUNTRY_CHPLAN_ENT("CA", 0x20, 1, 0), /* Canada */
+	COUNTRY_CHPLAN_ENT("CO", 0x34, 1, 0), /* Colombia */
+	COUNTRY_CHPLAN_ENT("CR", 0x34, 1, 0), /* Costa Rica */
+	COUNTRY_CHPLAN_ENT("DO", 0x34, 1, 0), /* Dominican Republic */
+	COUNTRY_CHPLAN_ENT("EC", 0x34, 1, 0), /* Ecuador */
+	COUNTRY_CHPLAN_ENT("GT", 0x34, 1, 0), /* Guatemala */
+	COUNTRY_CHPLAN_ENT("KR", 0x28, 1, 0), /* South Korea */
+	COUNTRY_CHPLAN_ENT("MX", 0x34, 1, 0), /* Mexico */
+	COUNTRY_CHPLAN_ENT("NI", 0x34, 1, 0), /* Nicaragua */
+	COUNTRY_CHPLAN_ENT("PA", 0x34, 1, 0), /* Panama */
+	COUNTRY_CHPLAN_ENT("PE", 0x34, 1, 0), /* Peru */
+	COUNTRY_CHPLAN_ENT("PR", 0x34, 1, 0), /* Puerto Rico */
+	COUNTRY_CHPLAN_ENT("PY", 0x34, 1, 0), /* Paraguay */
+	COUNTRY_CHPLAN_ENT("SC", 0x34, 1, 0), /* Seychelles */
+	COUNTRY_CHPLAN_ENT("ST", 0x34, 1, 0), /* Sao Tome and Principe */
+	COUNTRY_CHPLAN_ENT("TW", 0x39, 1, 0), /* Taiwan */
+	COUNTRY_CHPLAN_ENT("US", 0x34, 1, 0), /* United States of America (USA) */
+};
+#endif
+
+#if (RTW_DEF_MODULE_REGULATORY_CERT & RTW_MODULE_RTL8723DE_NGFF1630) /* 2016 certify */
+static const struct country_chplan RTL8723DE_NGFF1630_country_chplan_exc_map[] = {
+	COUNTRY_CHPLAN_ENT("CA", 0x2A, 1, 0), /* Canada */
+	COUNTRY_CHPLAN_ENT("KR", 0x28, 1, 0), /* South Korea */
+	COUNTRY_CHPLAN_ENT("MX", 0x34, 1, 0), /* Mexico */
+};
+#endif
+
+#if (RTW_DEF_MODULE_REGULATORY_CERT & RTW_MODULE_RTL8822BE) /* 2016 certify */
+static const struct country_chplan RTL8822BE_country_chplan_exc_map[] = {
+	COUNTRY_CHPLAN_ENT("KR", 0x28, 1, 0), /* South Korea */
+};
+#endif
+
+#if (RTW_DEF_MODULE_REGULATORY_CERT & RTW_MODULE_RTL8821CE) /* 2016 certify */
+static const struct country_chplan RTL8821CE_country_chplan_exc_map[] = {
+	COUNTRY_CHPLAN_ENT("KR", 0x28, 1, 0), /* South Korea */
+};
+#endif
+
+/**
+ * rtw_def_module_get_chplan_from_country -
+ * @country_code: string of country code
+ * @return:
+ * Return NULL for case referring to common map
+ */
+static const struct country_chplan *rtw_def_module_get_chplan_from_country(const char *country_code)
+{
+	const struct country_chplan *ent = NULL;
+	const struct country_chplan *hal_map = NULL;
+	u16 hal_map_sz = 0;
+	int i;
+
+	/* TODO: runtime selection for multi driver */
+#if (RTW_DEF_MODULE_REGULATORY_CERT == RTW_MODULE_RTL8821AE_HMC_M2)
+	hal_map = RTL8821AE_HMC_M2_country_chplan_exc_map;
+	hal_map_sz = sizeof(RTL8821AE_HMC_M2_country_chplan_exc_map) / sizeof(struct country_chplan);
+#elif (RTW_DEF_MODULE_REGULATORY_CERT == RTW_MODULE_RTL8821AU)
+	hal_map = RTL8821AU_country_chplan_exc_map;
+	hal_map_sz = sizeof(RTL8821AU_country_chplan_exc_map) / sizeof(struct country_chplan);
+#elif (RTW_DEF_MODULE_REGULATORY_CERT == RTW_MODULE_RTL8812AENF_NGFF)
+	hal_map = RTL8812AENF_NGFF_country_chplan_exc_map;
+	hal_map_sz = sizeof(RTL8812AENF_NGFF_country_chplan_exc_map) / sizeof(struct country_chplan);
+#elif (RTW_DEF_MODULE_REGULATORY_CERT == RTW_MODULE_RTL8812AEBT_HMC)
+	hal_map = RTL8812AEBT_HMC_country_chplan_exc_map;
+	hal_map_sz = sizeof(RTL8812AEBT_HMC_country_chplan_exc_map) / sizeof(struct country_chplan);
+#elif (RTW_DEF_MODULE_REGULATORY_CERT == RTW_MODULE_RTL8188EE_HMC_M2)
+	hal_map = RTL8188EE_HMC_M2_country_chplan_exc_map;
+	hal_map_sz = sizeof(RTL8188EE_HMC_M2_country_chplan_exc_map) / sizeof(struct country_chplan);
+#elif (RTW_DEF_MODULE_REGULATORY_CERT == RTW_MODULE_RTL8723BE_HMC_M2)
+	hal_map = RTL8723BE_HMC_M2_country_chplan_exc_map;
+	hal_map_sz = sizeof(RTL8723BE_HMC_M2_country_chplan_exc_map) / sizeof(struct country_chplan);
+#elif (RTW_DEF_MODULE_REGULATORY_CERT == RTW_MODULE_RTL8723BS_NGFF1216)
+	hal_map = RTL8723BS_NGFF1216_country_chplan_exc_map;
+	hal_map_sz = sizeof(RTL8723BS_NGFF1216_country_chplan_exc_map) / sizeof(struct country_chplan);
+#elif (RTW_DEF_MODULE_REGULATORY_CERT == RTW_MODULE_RTL8192EEBT_HMC_M2)
+	hal_map = RTL8192EEBT_HMC_M2_country_chplan_exc_map;
+	hal_map_sz = sizeof(RTL8192EEBT_HMC_M2_country_chplan_exc_map) / sizeof(struct country_chplan);
+#elif (RTW_DEF_MODULE_REGULATORY_CERT == RTW_MODULE_RTL8723DE_NGFF1630)
+	hal_map = RTL8723DE_NGFF1630_country_chplan_exc_map;
+	hal_map_sz = sizeof(RTL8723DE_NGFF1630_country_chplan_exc_map) / sizeof(struct country_chplan);
+#elif (RTW_DEF_MODULE_REGULATORY_CERT == RTW_MODULE_RTL8822BE)
+	hal_map = RTL8822BE_country_chplan_exc_map;
+	hal_map_sz = sizeof(RTL8822BE_country_chplan_exc_map) / sizeof(struct country_chplan);
+#elif (RTW_DEF_MODULE_REGULATORY_CERT == RTW_MODULE_RTL8821CE)
+	hal_map = RTL8821CE_country_chplan_exc_map;
+	hal_map_sz = sizeof(RTL8821CE_country_chplan_exc_map) / sizeof(struct country_chplan);
+#endif
+
+	if (hal_map == NULL || hal_map_sz == 0)
+		goto exit;
+
+	for (i = 0; i < hal_map_sz; i++) {
+		if (strncmp(country_code, hal_map[i].alpha2, 2) == 0) {
+			ent = &hal_map[i];
+			break;
+		}
+	}
+
+exit:
+	return ent;
+}
+#endif /* CONFIG_CUSTOMIZED_COUNTRY_CHPLAN_MAP or RTW_DEF_MODULE_REGULATORY_CERT */
+
+static const struct country_chplan country_chplan_map[] = {
+	COUNTRY_CHPLAN_ENT("AD", 0x26, 1, 0x000), /* Andorra */
+	COUNTRY_CHPLAN_ENT("AE", 0x26, 1, 0x7FB), /* United Arab Emirates */
+	COUNTRY_CHPLAN_ENT("AF", 0x42, 1, 0x000), /* Afghanistan */
+	COUNTRY_CHPLAN_ENT("AG", 0x26, 1, 0x000), /* Antigua & Barbuda */
+	COUNTRY_CHPLAN_ENT("AI", 0x26, 1, 0x000), /* Anguilla(UK) */
+	COUNTRY_CHPLAN_ENT("AL", 0x26, 1, 0x7F1), /* Albania */
+	COUNTRY_CHPLAN_ENT("AM", 0x26, 1, 0x6B0), /* Armenia */
+	COUNTRY_CHPLAN_ENT("AN", 0x26, 1, 0x7F1), /* Netherlands Antilles */
+	COUNTRY_CHPLAN_ENT("AO", 0x47, 1, 0x6E0), /* Angola */
+	COUNTRY_CHPLAN_ENT("AQ", 0x26, 1, 0x000), /* Antarctica */
+	COUNTRY_CHPLAN_ENT("AR", 0x61, 1, 0x7F3), /* Argentina */
+	COUNTRY_CHPLAN_ENT("AS", 0x76, 1, 0x000), /* American Samoa */
+	COUNTRY_CHPLAN_ENT("AT", 0x26, 1, 0x7FB), /* Austria */
+	COUNTRY_CHPLAN_ENT("AU", 0x45, 1, 0x7FB), /* Australia */
+	COUNTRY_CHPLAN_ENT("AW", 0x76, 1, 0x0B0), /* Aruba */
+	COUNTRY_CHPLAN_ENT("AZ", 0x26, 1, 0x7F1), /* Azerbaijan */
+	COUNTRY_CHPLAN_ENT("BA", 0x26, 1, 0x7F1), /* Bosnia & Herzegovina */
+	COUNTRY_CHPLAN_ENT("BB", 0x76, 1, 0x650), /* Barbados */
+	COUNTRY_CHPLAN_ENT("BD", 0x26, 1, 0x7F1), /* Bangladesh */
+	COUNTRY_CHPLAN_ENT("BE", 0x26, 1, 0x7FB), /* Belgium */
+	COUNTRY_CHPLAN_ENT("BF", 0x26, 1, 0x6B0), /* Burkina Faso */
+	COUNTRY_CHPLAN_ENT("BG", 0x26, 1, 0x7F1), /* Bulgaria */
+	COUNTRY_CHPLAN_ENT("BH", 0x47, 1, 0x7F1), /* Bahrain */
+	COUNTRY_CHPLAN_ENT("BI", 0x26, 1, 0x6B0), /* Burundi */
+	COUNTRY_CHPLAN_ENT("BJ", 0x26, 1, 0x6B0), /* Benin */
+	COUNTRY_CHPLAN_ENT("BN", 0x47, 1, 0x610), /* Brunei */
+	COUNTRY_CHPLAN_ENT("BO", 0x73, 1, 0x7F1), /* Bolivia */
+	COUNTRY_CHPLAN_ENT("BR", 0x62, 1, 0x7F1), /* Brazil */
+	COUNTRY_CHPLAN_ENT("BS", 0x76, 1, 0x620), /* Bahamas */
+	COUNTRY_CHPLAN_ENT("BW", 0x26, 1, 0x6F1), /* Botswana */
+	COUNTRY_CHPLAN_ENT("BY", 0x26, 1, 0x7F1), /* Belarus */
+	COUNTRY_CHPLAN_ENT("BZ", 0x76, 1, 0x000), /* Belize */
+	COUNTRY_CHPLAN_ENT("CA", 0x2B, 1, 0x7FB), /* Canada */
+	COUNTRY_CHPLAN_ENT("CC", 0x26, 1, 0x000), /* Cocos (Keeling) Islands (Australia) */
+	COUNTRY_CHPLAN_ENT("CD", 0x26, 1, 0x6B0), /* Congo, Republic of the */
+	COUNTRY_CHPLAN_ENT("CF", 0x26, 1, 0x6B0), /* Central African Republic */
+	COUNTRY_CHPLAN_ENT("CG", 0x26, 1, 0x6B0), /* Congo, Democratic Republic of the. Zaire */
+	COUNTRY_CHPLAN_ENT("CH", 0x26, 1, 0x7FB), /* Switzerland */
+	COUNTRY_CHPLAN_ENT("CI", 0x26, 1, 0x7F1), /* Cote d'Ivoire */
+	COUNTRY_CHPLAN_ENT("CK", 0x26, 1, 0x000), /* Cook Islands */
+	COUNTRY_CHPLAN_ENT("CL", 0x2D, 1, 0x7F1), /* Chile */
+	COUNTRY_CHPLAN_ENT("CM", 0x26, 1, 0x6B0), /* Cameroon */
+	COUNTRY_CHPLAN_ENT("CN", 0x48, 1, 0x7FB), /* China */
+	COUNTRY_CHPLAN_ENT("CO", 0x76, 1, 0x7F1), /* Colombia */
+	COUNTRY_CHPLAN_ENT("CR", 0x76, 1, 0x7F1), /* Costa Rica */
+	COUNTRY_CHPLAN_ENT("CV", 0x26, 1, 0x6B0), /* Cape Verde */
+	COUNTRY_CHPLAN_ENT("CX", 0x45, 1, 0x000), /* Christmas Island (Australia) */
+	COUNTRY_CHPLAN_ENT("CY", 0x26, 1, 0x7FB), /* Cyprus */
+	COUNTRY_CHPLAN_ENT("CZ", 0x26, 1, 0x7FB), /* Czech Republic */
+	COUNTRY_CHPLAN_ENT("DE", 0x26, 1, 0x7FB), /* Germany */
+	COUNTRY_CHPLAN_ENT("DJ", 0x26, 1, 0x680), /* Djibouti */
+	COUNTRY_CHPLAN_ENT("DK", 0x26, 1, 0x7FB), /* Denmark */
+	COUNTRY_CHPLAN_ENT("DM", 0x76, 1, 0x000), /* Dominica */
+	COUNTRY_CHPLAN_ENT("DO", 0x76, 1, 0x7F1), /* Dominican Republic */
+	COUNTRY_CHPLAN_ENT("DZ", 0x26, 1, 0x7F1), /* Algeria */
+	COUNTRY_CHPLAN_ENT("EC", 0x76, 1, 0x7F1), /* Ecuador */
+	COUNTRY_CHPLAN_ENT("EE", 0x26, 1, 0x7FB), /* Estonia */
+	COUNTRY_CHPLAN_ENT("EG", 0x47, 1, 0x7F1), /* Egypt */
+	COUNTRY_CHPLAN_ENT("EH", 0x47, 1, 0x680), /* Western Sahara */
+	COUNTRY_CHPLAN_ENT("ER", 0x26, 1, 0x000), /* Eritrea */
+	COUNTRY_CHPLAN_ENT("ES", 0x26, 1, 0x7FB), /* Spain, Canary Islands, Ceuta, Melilla */
+	COUNTRY_CHPLAN_ENT("ET", 0x26, 1, 0x4B0), /* Ethiopia */
+	COUNTRY_CHPLAN_ENT("FI", 0x26, 1, 0x7FB), /* Finland */
+	COUNTRY_CHPLAN_ENT("FJ", 0x76, 1, 0x600), /* Fiji */
+	COUNTRY_CHPLAN_ENT("FK", 0x26, 1, 0x000), /* Falkland Islands (Islas Malvinas) (UK) */
+	COUNTRY_CHPLAN_ENT("FM", 0x76, 1, 0x000), /* Micronesia, Federated States of (USA) */
+	COUNTRY_CHPLAN_ENT("FO", 0x26, 1, 0x000), /* Faroe Islands (Denmark) */
+	COUNTRY_CHPLAN_ENT("FR", 0x26, 1, 0x7FB), /* France */
+	COUNTRY_CHPLAN_ENT("GA", 0x26, 1, 0x6B0), /* Gabon */
+	COUNTRY_CHPLAN_ENT("GB", 0x26, 1, 0x7FB), /* Great Britain (United Kingdom; England) */
+	COUNTRY_CHPLAN_ENT("GD", 0x34, 1, 0x0B0), /* Grenada */
+	COUNTRY_CHPLAN_ENT("GE", 0x26, 1, 0x600), /* Georgia */
+	COUNTRY_CHPLAN_ENT("GF", 0x26, 1, 0x080), /* French Guiana */
+	COUNTRY_CHPLAN_ENT("GG", 0x26, 1, 0x000), /* Guernsey (UK) */
+	COUNTRY_CHPLAN_ENT("GH", 0x26, 1, 0x7F1), /* Ghana */
+	COUNTRY_CHPLAN_ENT("GI", 0x26, 1, 0x600), /* Gibraltar (UK) */
+	COUNTRY_CHPLAN_ENT("GL", 0x26, 1, 0x600), /* Greenland (Denmark) */
+	COUNTRY_CHPLAN_ENT("GM", 0x26, 1, 0x6B0), /* Gambia */
+	COUNTRY_CHPLAN_ENT("GN", 0x26, 1, 0x610), /* Guinea */
+	COUNTRY_CHPLAN_ENT("GP", 0x26, 1, 0x600), /* Guadeloupe (France) */
+	COUNTRY_CHPLAN_ENT("GQ", 0x26, 1, 0x6B0), /* Equatorial Guinea */
+	COUNTRY_CHPLAN_ENT("GR", 0x26, 1, 0x7FB), /* Greece */
+	COUNTRY_CHPLAN_ENT("GS", 0x26, 1, 0x000), /* South Georgia and the Sandwich Islands (UK) */
+	COUNTRY_CHPLAN_ENT("GT", 0x61, 1, 0x7F1), /* Guatemala */
+	COUNTRY_CHPLAN_ENT("GU", 0x76, 1, 0x600), /* Guam (USA) */
+	COUNTRY_CHPLAN_ENT("GW", 0x26, 1, 0x6B0), /* Guinea-Bissau */
+	COUNTRY_CHPLAN_ENT("GY", 0x44, 1, 0x000), /* Guyana */
+	COUNTRY_CHPLAN_ENT("HK", 0x26, 1, 0x7FB), /* Hong Kong */
+	COUNTRY_CHPLAN_ENT("HM", 0x45, 1, 0x000), /* Heard and McDonald Islands (Australia) */
+	COUNTRY_CHPLAN_ENT("HN", 0x32, 1, 0x7F1), /* Honduras */
+	COUNTRY_CHPLAN_ENT("HR", 0x26, 1, 0x7F9), /* Croatia */
+	COUNTRY_CHPLAN_ENT("HT", 0x76, 1, 0x650), /* Haiti */
+	COUNTRY_CHPLAN_ENT("HU", 0x26, 1, 0x7FB), /* Hungary */
+	COUNTRY_CHPLAN_ENT("ID", 0x3D, 0, 0x7F3), /* Indonesia */
+	COUNTRY_CHPLAN_ENT("IE", 0x26, 1, 0x7FB), /* Ireland */
+	COUNTRY_CHPLAN_ENT("IL", 0x47, 1, 0x7F1), /* Israel */
+	COUNTRY_CHPLAN_ENT("IM", 0x26, 1, 0x000), /* Isle of Man (UK) */
+	COUNTRY_CHPLAN_ENT("IN", 0x48, 1, 0x7F1), /* India */
+	COUNTRY_CHPLAN_ENT("IQ", 0x26, 1, 0x000), /* Iraq */
+	COUNTRY_CHPLAN_ENT("IR", 0x26, 0, 0x000), /* Iran */
+	COUNTRY_CHPLAN_ENT("IS", 0x26, 1, 0x7FB), /* Iceland */
+	COUNTRY_CHPLAN_ENT("IT", 0x26, 1, 0x7FB), /* Italy */
+	COUNTRY_CHPLAN_ENT("JE", 0x26, 1, 0x000), /* Jersey (UK) */
+	COUNTRY_CHPLAN_ENT("JM", 0x51, 1, 0x7F1), /* Jamaica */
+	COUNTRY_CHPLAN_ENT("JO", 0x49, 1, 0x7FB), /* Jordan */
+	COUNTRY_CHPLAN_ENT("JP", 0x27, 1, 0x7FF), /* Japan- Telec */
+	COUNTRY_CHPLAN_ENT("KE", 0x47, 1, 0x7F9), /* Kenya */
+	COUNTRY_CHPLAN_ENT("KG", 0x26, 1, 0x7F1), /* Kyrgyzstan */
+	COUNTRY_CHPLAN_ENT("KH", 0x26, 1, 0x7F1), /* Cambodia */
+	COUNTRY_CHPLAN_ENT("KI", 0x26, 1, 0x000), /* Kiribati */
+	COUNTRY_CHPLAN_ENT("KN", 0x76, 1, 0x000), /* Saint Kitts and Nevis */
+	COUNTRY_CHPLAN_ENT("KR", 0x3E, 1, 0x7FB), /* South Korea */
+	COUNTRY_CHPLAN_ENT("KW", 0x47, 1, 0x7FB), /* Kuwait */
+	COUNTRY_CHPLAN_ENT("KY", 0x76, 1, 0x000), /* Cayman Islands (UK) */
+	COUNTRY_CHPLAN_ENT("KZ", 0x26, 1, 0x700), /* Kazakhstan */
+	COUNTRY_CHPLAN_ENT("LA", 0x26, 1, 0x000), /* Laos */
+	COUNTRY_CHPLAN_ENT("LB", 0x26, 1, 0x7F1), /* Lebanon */
+	COUNTRY_CHPLAN_ENT("LC", 0x76, 1, 0x000), /* Saint Lucia */
+	COUNTRY_CHPLAN_ENT("LI", 0x26, 1, 0x7FB), /* Liechtenstein */
+	COUNTRY_CHPLAN_ENT("LK", 0x26, 1, 0x7F1), /* Sri Lanka */
+	COUNTRY_CHPLAN_ENT("LR", 0x26, 1, 0x6B0), /* Liberia */
+	COUNTRY_CHPLAN_ENT("LS", 0x26, 1, 0x7F1), /* Lesotho */
+	COUNTRY_CHPLAN_ENT("LT", 0x26, 1, 0x7FB), /* Lithuania */
+	COUNTRY_CHPLAN_ENT("LU", 0x26, 1, 0x7FB), /* Luxembourg */
+	COUNTRY_CHPLAN_ENT("LV", 0x26, 1, 0x7FB), /* Latvia */
+	COUNTRY_CHPLAN_ENT("LY", 0x26, 1, 0x000), /* Libya */
+	COUNTRY_CHPLAN_ENT("MA", 0x47, 1, 0x7F1), /* Morocco */
+	COUNTRY_CHPLAN_ENT("MC", 0x26, 1, 0x7FB), /* Monaco */
+	COUNTRY_CHPLAN_ENT("MD", 0x26, 1, 0x7F1), /* Moldova */
+	COUNTRY_CHPLAN_ENT("ME", 0x26, 1, 0x7F1), /* Montenegro */
+	COUNTRY_CHPLAN_ENT("MF", 0x76, 1, 0x000), /* Saint Martin */
+	COUNTRY_CHPLAN_ENT("MG", 0x26, 1, 0x620), /* Madagascar */
+	COUNTRY_CHPLAN_ENT("MH", 0x76, 1, 0x000), /* Marshall Islands (USA) */
+	COUNTRY_CHPLAN_ENT("MK", 0x26, 1, 0x7F1), /* Republic of Macedonia (FYROM) */
+	COUNTRY_CHPLAN_ENT("ML", 0x26, 1, 0x6B0), /* Mali */
+	COUNTRY_CHPLAN_ENT("MM", 0x26, 1, 0x000), /* Burma (Myanmar) */
+	COUNTRY_CHPLAN_ENT("MN", 0x26, 1, 0x000), /* Mongolia */
+	COUNTRY_CHPLAN_ENT("MO", 0x26, 1, 0x600), /* Macau */
+	COUNTRY_CHPLAN_ENT("MP", 0x76, 1, 0x000), /* Northern Mariana Islands (USA) */
+	COUNTRY_CHPLAN_ENT("MQ", 0x26, 1, 0x640), /* Martinique (France) */
+	COUNTRY_CHPLAN_ENT("MR", 0x26, 1, 0x6A0), /* Mauritania */
+	COUNTRY_CHPLAN_ENT("MS", 0x26, 1, 0x000), /* Montserrat (UK) */
+	COUNTRY_CHPLAN_ENT("MT", 0x26, 1, 0x7FB), /* Malta */
+	COUNTRY_CHPLAN_ENT("MU", 0x26, 1, 0x6B0), /* Mauritius */
+	COUNTRY_CHPLAN_ENT("MV", 0x47, 1, 0x000), /* Maldives */
+	COUNTRY_CHPLAN_ENT("MW", 0x26, 1, 0x6B0), /* Malawi */
+	COUNTRY_CHPLAN_ENT("MX", 0x61, 1, 0x7F1), /* Mexico */
+	COUNTRY_CHPLAN_ENT("MY", 0x63, 1, 0x7F1), /* Malaysia */
+	COUNTRY_CHPLAN_ENT("MZ", 0x26, 1, 0x7F1), /* Mozambique */
+	COUNTRY_CHPLAN_ENT("NA", 0x26, 1, 0x700), /* Namibia */
+	COUNTRY_CHPLAN_ENT("NC", 0x26, 1, 0x000), /* New Caledonia */
+	COUNTRY_CHPLAN_ENT("NE", 0x26, 1, 0x6B0), /* Niger */
+	COUNTRY_CHPLAN_ENT("NF", 0x45, 1, 0x000), /* Norfolk Island (Australia) */
+	COUNTRY_CHPLAN_ENT("NG", 0x75, 1, 0x7F9), /* Nigeria */
+	COUNTRY_CHPLAN_ENT("NI", 0x76, 1, 0x7F1), /* Nicaragua */
+	COUNTRY_CHPLAN_ENT("NL", 0x26, 1, 0x7FB), /* Netherlands */
+	COUNTRY_CHPLAN_ENT("NO", 0x26, 1, 0x7FB), /* Norway */
+	COUNTRY_CHPLAN_ENT("NP", 0x47, 1, 0x6F0), /* Nepal */
+	COUNTRY_CHPLAN_ENT("NR", 0x26, 1, 0x000), /* Nauru */
+	COUNTRY_CHPLAN_ENT("NU", 0x45, 1, 0x000), /* Niue */
+	COUNTRY_CHPLAN_ENT("NZ", 0x45, 1, 0x7FB), /* New Zealand */
+	COUNTRY_CHPLAN_ENT("OM", 0x26, 1, 0x7F9), /* Oman */
+	COUNTRY_CHPLAN_ENT("PA", 0x76, 1, 0x7F1), /* Panama */
+	COUNTRY_CHPLAN_ENT("PE", 0x76, 1, 0x7F1), /* Peru */
+	COUNTRY_CHPLAN_ENT("PF", 0x26, 1, 0x000), /* French Polynesia (France) */
+	COUNTRY_CHPLAN_ENT("PG", 0x26, 1, 0x7F1), /* Papua New Guinea */
+	COUNTRY_CHPLAN_ENT("PH", 0x26, 1, 0x7F1), /* Philippines */
+	COUNTRY_CHPLAN_ENT("PK", 0x51, 1, 0x7F1), /* Pakistan */
+	COUNTRY_CHPLAN_ENT("PL", 0x26, 1, 0x7FB), /* Poland */
+	COUNTRY_CHPLAN_ENT("PM", 0x26, 1, 0x000), /* Saint Pierre and Miquelon (France) */
+	COUNTRY_CHPLAN_ENT("PR", 0x76, 1, 0x7F1), /* Puerto Rico */
+	COUNTRY_CHPLAN_ENT("PT", 0x26, 1, 0x7FB), /* Portugal */
+	COUNTRY_CHPLAN_ENT("PW", 0x76, 1, 0x000), /* Palau */
+	COUNTRY_CHPLAN_ENT("PY", 0x76, 1, 0x7F1), /* Paraguay */
+	COUNTRY_CHPLAN_ENT("QA", 0x51, 1, 0x7F9), /* Qatar */
+	COUNTRY_CHPLAN_ENT("RE", 0x26, 1, 0x000), /* Reunion (France) */
+	COUNTRY_CHPLAN_ENT("RO", 0x26, 1, 0x7F1), /* Romania */
+	COUNTRY_CHPLAN_ENT("RS", 0x26, 1, 0x7F1), /* Serbia, Kosovo */
+	COUNTRY_CHPLAN_ENT("RU", 0x59, 1, 0x7FB), /* Russia(fac/gost), Kaliningrad */
+	COUNTRY_CHPLAN_ENT("RW", 0x26, 1, 0x0B0), /* Rwanda */
+	COUNTRY_CHPLAN_ENT("SA", 0x26, 1, 0x7FB), /* Saudi Arabia */
+	COUNTRY_CHPLAN_ENT("SB", 0x26, 1, 0x000), /* Solomon Islands */
+	COUNTRY_CHPLAN_ENT("SC", 0x76, 1, 0x690), /* Seychelles */
+	COUNTRY_CHPLAN_ENT("SE", 0x26, 1, 0x7FB), /* Sweden */
+	COUNTRY_CHPLAN_ENT("SG", 0x35, 1, 0x7FB), /* Singapore */
+	COUNTRY_CHPLAN_ENT("SH", 0x26, 1, 0x000), /* Saint Helena (UK) */
+	COUNTRY_CHPLAN_ENT("SI", 0x26, 1, 0x7FB), /* Slovenia */
+	COUNTRY_CHPLAN_ENT("SJ", 0x26, 1, 0x000), /* Svalbard (Norway) */
+	COUNTRY_CHPLAN_ENT("SK", 0x26, 1, 0x7FB), /* Slovakia */
+	COUNTRY_CHPLAN_ENT("SL", 0x26, 1, 0x6B0), /* Sierra Leone */
+	COUNTRY_CHPLAN_ENT("SM", 0x26, 1, 0x000), /* San Marino */
+	COUNTRY_CHPLAN_ENT("SN", 0x26, 1, 0x7F1), /* Senegal */
+	COUNTRY_CHPLAN_ENT("SO", 0x26, 1, 0x000), /* Somalia */
+	COUNTRY_CHPLAN_ENT("SR", 0x74, 1, 0x000), /* Suriname */
+	COUNTRY_CHPLAN_ENT("ST", 0x76, 1, 0x680), /* Sao Tome and Principe */
+	COUNTRY_CHPLAN_ENT("SV", 0x30, 1, 0x7F1), /* El Salvador */
+	COUNTRY_CHPLAN_ENT("SX", 0x76, 1, 0x000), /* Sint Marteen */
+	COUNTRY_CHPLAN_ENT("SZ", 0x26, 1, 0x020), /* Swaziland */
+	COUNTRY_CHPLAN_ENT("TC", 0x26, 1, 0x000), /* Turks and Caicos Islands (UK) */
+	COUNTRY_CHPLAN_ENT("TD", 0x26, 1, 0x6B0), /* Chad */
+	COUNTRY_CHPLAN_ENT("TF", 0x26, 1, 0x680), /* French Southern and Antarctic Lands (FR Southern Territories) */
+	COUNTRY_CHPLAN_ENT("TG", 0x26, 1, 0x6B0), /* Togo */
+	COUNTRY_CHPLAN_ENT("TH", 0x26, 1, 0x7F1), /* Thailand */
+	COUNTRY_CHPLAN_ENT("TJ", 0x26, 1, 0x640), /* Tajikistan */
+	COUNTRY_CHPLAN_ENT("TK", 0x45, 1, 0x000), /* Tokelau */
+	COUNTRY_CHPLAN_ENT("TM", 0x26, 1, 0x000), /* Turkmenistan */
+	COUNTRY_CHPLAN_ENT("TN", 0x47, 1, 0x7F1), /* Tunisia */
+	COUNTRY_CHPLAN_ENT("TO", 0x26, 1, 0x000), /* Tonga */
+	COUNTRY_CHPLAN_ENT("TR", 0x26, 1, 0x7F1), /* Turkey, Northern Cyprus */
+	COUNTRY_CHPLAN_ENT("TT", 0x42, 1, 0x3F1), /* Trinidad & Tobago */
+	COUNTRY_CHPLAN_ENT("TW", 0x76, 1, 0x7FF), /* Taiwan */
+	COUNTRY_CHPLAN_ENT("TZ", 0x26, 1, 0x6F0), /* Tanzania */
+	COUNTRY_CHPLAN_ENT("UA", 0x36, 1, 0x7FB), /* Ukraine */
+	COUNTRY_CHPLAN_ENT("UG", 0x26, 1, 0x6F1), /* Uganda */
+	COUNTRY_CHPLAN_ENT("US", 0x76, 1, 0x7FF), /* United States of America (USA) */
+	COUNTRY_CHPLAN_ENT("UY", 0x30, 1, 0x7F1), /* Uruguay */
+	COUNTRY_CHPLAN_ENT("UZ", 0x47, 1, 0x6F0), /* Uzbekistan */
+	COUNTRY_CHPLAN_ENT("VA", 0x26, 1, 0x000), /* Holy See (Vatican City) */
+	COUNTRY_CHPLAN_ENT("VC", 0x76, 1, 0x010), /* Saint Vincent and the Grenadines */
+	COUNTRY_CHPLAN_ENT("VE", 0x30, 1, 0x7F1), /* Venezuela */
+	COUNTRY_CHPLAN_ENT("VI", 0x76, 1, 0x000), /* United States Virgin Islands (USA) */
+	COUNTRY_CHPLAN_ENT("VN", 0x26, 1, 0x7F1), /* Vietnam */
+	COUNTRY_CHPLAN_ENT("VU", 0x26, 1, 0x000), /* Vanuatu */
+	COUNTRY_CHPLAN_ENT("WF", 0x26, 1, 0x000), /* Wallis and Futuna (France) */
+	COUNTRY_CHPLAN_ENT("WS", 0x76, 1, 0x000), /* Samoa */
+	COUNTRY_CHPLAN_ENT("YE", 0x26, 1, 0x040), /* Yemen */
+	COUNTRY_CHPLAN_ENT("YT", 0x26, 1, 0x680), /* Mayotte (France) */
+	COUNTRY_CHPLAN_ENT("ZA", 0x26, 1, 0x7F1), /* South Africa */
+	COUNTRY_CHPLAN_ENT("ZM", 0x26, 1, 0x6B0), /* Zambia */
+	COUNTRY_CHPLAN_ENT("ZW", 0x26, 1, 0x7F1), /* Zimbabwe */
+};
+
+/*
+* rtw_get_chplan_from_country -
+* @country_code: string of country code
+*
+* Return pointer of struct country_chplan entry or NULL when unsupported country_code is given
+*/
+const struct country_chplan *rtw_get_chplan_from_country(const char *country_code)
+{
+#if RTW_DEF_MODULE_REGULATORY_CERT
+	const struct country_chplan *exc_ent = NULL;
+#endif
+	const struct country_chplan *ent = NULL;
+	const struct country_chplan *map = NULL;
+	u16 map_sz = 0;
+	char code[2];
+	int i;
+
+	code[0] = alpha_to_upper(country_code[0]);
+	code[1] = alpha_to_upper(country_code[1]);
+
+#ifdef CONFIG_CUSTOMIZED_COUNTRY_CHPLAN_MAP
+	map = CUSTOMIZED_country_chplan_map;
+	map_sz = sizeof(CUSTOMIZED_country_chplan_map) / sizeof(struct country_chplan);
+#else
+	#if RTW_DEF_MODULE_REGULATORY_CERT
+	exc_ent = rtw_def_module_get_chplan_from_country(code);
+	#endif
+	map = country_chplan_map;
+	map_sz = sizeof(country_chplan_map) / sizeof(struct country_chplan);
+#endif
+
+	for (i = 0; i < map_sz; i++) {
+		if (strncmp(code, map[i].alpha2, 2) == 0) {
+			ent = &map[i];
+			break;
+		}
+	}
+
+	#if RTW_DEF_MODULE_REGULATORY_CERT
+	if (!ent || !(COUNTRY_CHPLAN_DEF_MODULE_FALGS(ent) & RTW_DEF_MODULE_REGULATORY_CERT))
+		exc_ent = ent = NULL;
+	if (exc_ent)
+		ent = exc_ent;
+	#endif
+
+	return ent;
+}
+
+void dump_country_chplan(void *sel, const struct country_chplan *ent)
+{
+	RTW_PRINT_SEL(sel, "\"%c%c\", 0x%02X%s\n"
+		, ent->alpha2[0], ent->alpha2[1], ent->chplan
+		, COUNTRY_CHPLAN_EN_11AC(ent) ? " ac" : ""
+	);
+}
+
+void dump_country_chplan_map(void *sel)
+{
+	const struct country_chplan *ent;
+	u8 code[2];
+
+#if RTW_DEF_MODULE_REGULATORY_CERT
+	RTW_PRINT_SEL(sel, "RTW_DEF_MODULE_REGULATORY_CERT:0x%x\n", RTW_DEF_MODULE_REGULATORY_CERT);
+#endif
+#ifdef CONFIG_CUSTOMIZED_COUNTRY_CHPLAN_MAP
+	RTW_PRINT_SEL(sel, "CONFIG_CUSTOMIZED_COUNTRY_CHPLAN_MAP\n");
+#endif
+
+	for (code[0] = 'A'; code[0] <= 'Z'; code[0]++) {
+		for (code[1] = 'A'; code[1] <= 'Z'; code[1]++) {
+			ent = rtw_get_chplan_from_country(code);
+			if (!ent)
+				continue;
+
+			dump_country_chplan(sel, ent);
+		}
+	}
+}
+
+void dump_chplan_id_list(void *sel)
+{
+	u8 first = 1;
+	int i;
+
+	for (i = 0; i < RTW_CHPLAN_MAX; i++) {
+		if (!rtw_is_channel_plan_valid(i))
+			continue;
+
+		if (first) {
+			RTW_PRINT_SEL(sel, "0x%02X ", i);
+			first = 0;
+		} else
+			_RTW_PRINT_SEL(sel, "0x%02X ", i);
+	}
+
+	_RTW_PRINT_SEL(sel, "0x7F\n");
+}
+
+void dump_chplan_test(void *sel)
+{
+	int i, j;
+
+	/* check invalid channel */
+	for (i = 0; i < RTW_RD_2G_MAX; i++) {
+		for (j = 0; j < CH_LIST_LEN(RTW_ChannelPlan2G[i]); j++) {
+			if (rtw_ch2freq(CH_LIST_CH(RTW_ChannelPlan2G[i], j)) == 0)
+				RTW_PRINT_SEL(sel, "invalid ch:%u at (%d,%d)\n", CH_LIST_CH(RTW_ChannelPlan2G[i], j), i, j);
+		}
+	}
+
+#ifdef CONFIG_IEEE80211_BAND_5GHZ
+	for (i = 0; i < RTW_RD_5G_MAX; i++) {
+		for (j = 0; j < CH_LIST_LEN(RTW_ChannelPlan5G[i]); j++) {
+			if (rtw_ch2freq(CH_LIST_CH(RTW_ChannelPlan5G[i], j)) == 0)
+				RTW_PRINT_SEL(sel, "invalid ch:%u at (%d,%d)\n", CH_LIST_CH(RTW_ChannelPlan5G[i], j), i, j);
+		}
+	}
+#endif
+}
+
+void dump_chplan_ver(void *sel)
+{
+	RTW_PRINT_SEL(sel, "%s-%s\n", RTW_DOMAIN_MAP_VER, RTW_COUNTRY_MAP_VER);
+}
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/core/rtw_chplan.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/core/rtw_chplan.h
--- linux-5.6.3/3rdparty/rtl8821ce/core/rtw_chplan.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/core/rtw_chplan.h	2020-04-10 16:35:06.772658013 +0300
@@ -0,0 +1,179 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2018 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#ifndef __RTW_CHPLAN_H__
+#define __RTW_CHPLAN_H__
+
+enum rtw_chplan_id {
+	/* ===== 0x00 ~ 0x1F, legacy channel plan ===== */
+	RTW_CHPLAN_FCC = 0x00,
+	RTW_CHPLAN_IC = 0x01,
+	RTW_CHPLAN_ETSI = 0x02,
+	RTW_CHPLAN_SPAIN = 0x03,
+	RTW_CHPLAN_FRANCE = 0x04,
+	RTW_CHPLAN_MKK = 0x05,
+	RTW_CHPLAN_MKK1 = 0x06,
+	RTW_CHPLAN_ISRAEL = 0x07,
+	RTW_CHPLAN_TELEC = 0x08,
+	RTW_CHPLAN_GLOBAL_DOAMIN = 0x09,
+	RTW_CHPLAN_WORLD_WIDE_13 = 0x0A,
+	RTW_CHPLAN_TAIWAN = 0x0B,
+	RTW_CHPLAN_CHINA = 0x0C,
+	RTW_CHPLAN_SINGAPORE_INDIA_MEXICO = 0x0D,
+	RTW_CHPLAN_KOREA = 0x0E,
+	RTW_CHPLAN_TURKEY = 0x0F,
+	RTW_CHPLAN_JAPAN = 0x10,
+	RTW_CHPLAN_FCC_NO_DFS = 0x11,
+	RTW_CHPLAN_JAPAN_NO_DFS = 0x12,
+	RTW_CHPLAN_WORLD_WIDE_5G = 0x13,
+	RTW_CHPLAN_TAIWAN_NO_DFS = 0x14,
+
+	/* ===== 0x20 ~ 0x7F, new channel plan ===== */
+	RTW_CHPLAN_WORLD_NULL = 0x20,
+	RTW_CHPLAN_ETSI1_NULL = 0x21,
+	RTW_CHPLAN_FCC1_NULL = 0x22,
+	RTW_CHPLAN_MKK1_NULL = 0x23,
+	RTW_CHPLAN_ETSI2_NULL = 0x24,
+	RTW_CHPLAN_FCC1_FCC1 = 0x25,
+	RTW_CHPLAN_WORLD_ETSI1 = 0x26,
+	RTW_CHPLAN_MKK1_MKK1 = 0x27,
+	RTW_CHPLAN_WORLD_KCC1 = 0x28,
+	RTW_CHPLAN_WORLD_FCC2 = 0x29,
+	RTW_CHPLAN_FCC2_NULL = 0x2A,
+	RTW_CHPLAN_IC1_IC2 = 0x2B,
+	RTW_CHPLAN_MKK2_NULL = 0x2C,
+	RTW_CHPLAN_WORLD_CHILE1= 0x2D,
+	RTW_CHPLAN_WORLD1_WORLD1 = 0x2E,
+	RTW_CHPLAN_WORLD_CHILE2 = 0x2F,
+	RTW_CHPLAN_WORLD_FCC3 = 0x30,
+	RTW_CHPLAN_WORLD_FCC4 = 0x31,
+	RTW_CHPLAN_WORLD_FCC5 = 0x32,
+	RTW_CHPLAN_WORLD_FCC6 = 0x33,
+	RTW_CHPLAN_FCC1_FCC7 = 0x34,
+	RTW_CHPLAN_WORLD_ETSI2 = 0x35,
+	RTW_CHPLAN_WORLD_ETSI3 = 0x36,
+	RTW_CHPLAN_MKK1_MKK2 = 0x37,
+	RTW_CHPLAN_MKK1_MKK3 = 0x38,
+	RTW_CHPLAN_FCC1_NCC1 = 0x39,
+	RTW_CHPLAN_ETSI1_ETSI1 = 0x3A,
+	RTW_CHPLAN_ETSI1_ACMA1 = 0x3B,
+	RTW_CHPLAN_ETSI1_ETSI6 = 0x3C,
+	RTW_CHPLAN_ETSI1_ETSI12 = 0x3D,
+	RTW_CHPLAN_KCC1_KCC2 = 0x3E,
+	RTW_CHPLAN_FCC1_NCC2 = 0x40,
+	RTW_CHPLAN_GLOBAL_NULL = 0x41,
+	RTW_CHPLAN_ETSI1_ETSI4 = 0x42,
+	RTW_CHPLAN_FCC1_FCC2 = 0x43,
+	RTW_CHPLAN_FCC1_NCC3 = 0x44,
+	RTW_CHPLAN_WORLD_ACMA1 = 0x45,
+	RTW_CHPLAN_FCC1_FCC8 = 0x46,
+	RTW_CHPLAN_WORLD_ETSI6 = 0x47,
+	RTW_CHPLAN_WORLD_ETSI7 = 0x48,
+	RTW_CHPLAN_WORLD_ETSI8 = 0x49,
+	RTW_CHPLAN_WORLD_ETSI9 = 0x50,
+	RTW_CHPLAN_WORLD_ETSI10 = 0x51,
+	RTW_CHPLAN_WORLD_ETSI11 = 0x52,
+	RTW_CHPLAN_FCC1_NCC4 = 0x53,
+	RTW_CHPLAN_WORLD_ETSI12 = 0x54,
+	RTW_CHPLAN_FCC1_FCC9 = 0x55,
+	RTW_CHPLAN_WORLD_ETSI13 = 0x56,
+	RTW_CHPLAN_FCC1_FCC10 = 0x57,
+	RTW_CHPLAN_MKK2_MKK4 = 0x58,
+	RTW_CHPLAN_WORLD_ETSI14 = 0x59,
+	RTW_CHPLAN_FCC1_FCC5 = 0x60,
+	RTW_CHPLAN_FCC2_FCC7 = 0x61,
+	RTW_CHPLAN_FCC2_FCC1 = 0x62,
+	RTW_CHPLAN_WORLD_ETSI15 = 0x63,
+	RTW_CHPLAN_MKK2_MKK5 = 0x64,
+	RTW_CHPLAN_ETSI1_ETSI16 = 0x65,
+	RTW_CHPLAN_FCC1_FCC14 = 0x66,
+	RTW_CHPLAN_FCC1_FCC12 = 0x67,
+	RTW_CHPLAN_FCC2_FCC14 = 0x68,
+	RTW_CHPLAN_FCC2_FCC12 = 0x69,
+	RTW_CHPLAN_ETSI1_ETSI17 = 0x6A,
+	RTW_CHPLAN_WORLD_FCC16 = 0x6B,
+	RTW_CHPLAN_WORLD_FCC13 = 0x6C,
+	RTW_CHPLAN_FCC2_FCC15 = 0x6D,
+	RTW_CHPLAN_WORLD_FCC12 = 0x6E,
+	RTW_CHPLAN_NULL_ETSI8 = 0x6F,
+	RTW_CHPLAN_NULL_ETSI18 = 0x70,
+	RTW_CHPLAN_NULL_ETSI17 = 0x71,
+	RTW_CHPLAN_NULL_ETSI19 = 0x72,
+	RTW_CHPLAN_WORLD_FCC7 = 0x73,
+	RTW_CHPLAN_FCC2_FCC17 = 0x74,
+	RTW_CHPLAN_WORLD_ETSI20 = 0x75,
+	RTW_CHPLAN_FCC2_FCC11 = 0x76,
+	RTW_CHPLAN_WORLD_ETSI21 = 0x77,
+	RTW_CHPLAN_FCC1_FCC18 = 0x78,
+	RTW_CHPLAN_MKK2_MKK1 = 0x79,
+
+	RTW_CHPLAN_MAX,
+	RTW_CHPLAN_REALTEK_DEFINE = 0x7F,
+	RTW_CHPLAN_UNSPECIFIED = 0xFF,
+};
+
+u8 rtw_chplan_get_default_regd(u8 id);
+bool rtw_chplan_is_empty(u8 id);
+#define rtw_is_channel_plan_valid(chplan) (((chplan) < RTW_CHPLAN_MAX || (chplan) == RTW_CHPLAN_REALTEK_DEFINE) && !rtw_chplan_is_empty(chplan))
+#define rtw_is_legacy_channel_plan(chplan) ((chplan) < 0x20)
+
+struct _RT_CHANNEL_INFO;
+u8 init_channel_set(_adapter *padapter, u8 ChannelPlan, struct _RT_CHANNEL_INFO *channel_set);
+
+#define IS_ALPHA2_NO_SPECIFIED(_alpha2) ((*((u16 *)(_alpha2))) == 0xFFFF)
+
+#define RTW_MODULE_RTL8821AE_HMC_M2		BIT0	/* RTL8821AE(HMC + M.2) */
+#define RTW_MODULE_RTL8821AU			BIT1	/* RTL8821AU */
+#define RTW_MODULE_RTL8812AENF_NGFF		BIT2	/* RTL8812AENF(8812AE+8761)_NGFF */
+#define RTW_MODULE_RTL8812AEBT_HMC		BIT3	/* RTL8812AEBT(8812AE+8761)_HMC */
+#define RTW_MODULE_RTL8188EE_HMC_M2		BIT4	/* RTL8188EE(HMC + M.2) */
+#define RTW_MODULE_RTL8723BE_HMC_M2		BIT5	/* RTL8723BE(HMC + M.2) */
+#define RTW_MODULE_RTL8723BS_NGFF1216	BIT6	/* RTL8723BS(NGFF1216) */
+#define RTW_MODULE_RTL8192EEBT_HMC_M2	BIT7	/* RTL8192EEBT(8192EE+8761AU)_(HMC + M.2) */
+#define RTW_MODULE_RTL8723DE_NGFF1630	BIT8	/* RTL8723DE(NGFF1630) */
+#define RTW_MODULE_RTL8822BE			BIT9	/* RTL8822BE */
+#define RTW_MODULE_RTL8821CE			BIT10	/* RTL8821CE */
+
+struct country_chplan {
+	char alpha2[2];
+	u8 chplan;
+#ifdef CONFIG_80211AC_VHT
+	u8 en_11ac;
+#endif
+#if RTW_DEF_MODULE_REGULATORY_CERT
+	u16 def_module_flags; /* RTW_MODULE_RTLXXX */
+#endif
+};
+
+#ifdef CONFIG_80211AC_VHT
+#define COUNTRY_CHPLAN_EN_11AC(_ent) ((_ent)->en_11ac)
+#else
+#define COUNTRY_CHPLAN_EN_11AC(_ent) 0
+#endif
+
+#if RTW_DEF_MODULE_REGULATORY_CERT
+#define COUNTRY_CHPLAN_DEF_MODULE_FALGS(_ent) ((_ent)->def_module_flags)
+#else
+#define COUNTRY_CHPLAN_DEF_MODULE_FALGS(_ent) 0
+#endif
+
+const struct country_chplan *rtw_get_chplan_from_country(const char *country_code);
+
+void dump_country_chplan(void *sel, const struct country_chplan *ent);
+void dump_country_chplan_map(void *sel);
+void dump_chplan_id_list(void *sel);
+void dump_chplan_test(void *sel);
+void dump_chplan_ver(void *sel);
+
+#endif /* __RTW_CHPLAN_H__ */
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/core/rtw_cmd.c linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/core/rtw_cmd.c
--- linux-5.6.3/3rdparty/rtl8821ce/core/rtw_cmd.c	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/core/rtw_cmd.c	2020-04-10 16:35:06.772658013 +0300
@@ -0,0 +1,5354 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#define _RTW_CMD_C_
+
+#include <drv_types.h>
+#include <hal_data.h>
+
+#ifndef DBG_CMD_EXECUTE
+	#define DBG_CMD_EXECUTE 0
+#endif
+
+/*
+Caller and the rtw_cmd_thread can protect cmd_q by spin_lock.
+No irqsave is necessary.
+*/
+
+sint	_rtw_init_cmd_priv(struct	cmd_priv *pcmdpriv)
+{
+	sint res = _SUCCESS;
+
+
+	_rtw_init_sema(&(pcmdpriv->cmd_queue_sema), 0);
+	/* _rtw_init_sema(&(pcmdpriv->cmd_done_sema), 0); */
+	_rtw_init_sema(&(pcmdpriv->start_cmdthread_sema), 0);
+
+	_rtw_init_queue(&(pcmdpriv->cmd_queue));
+
+	/* allocate DMA-able/Non-Page memory for cmd_buf and rsp_buf */
+
+	pcmdpriv->cmd_seq = 1;
+
+	pcmdpriv->cmd_allocated_buf = rtw_zmalloc(MAX_CMDSZ + CMDBUFF_ALIGN_SZ);
+
+	if (pcmdpriv->cmd_allocated_buf == NULL) {
+		res = _FAIL;
+		goto exit;
+	}
+
+	pcmdpriv->cmd_buf = pcmdpriv->cmd_allocated_buf  +  CMDBUFF_ALIGN_SZ - ((SIZE_PTR)(pcmdpriv->cmd_allocated_buf) & (CMDBUFF_ALIGN_SZ - 1));
+
+	pcmdpriv->rsp_allocated_buf = rtw_zmalloc(MAX_RSPSZ + 4);
+
+	if (pcmdpriv->rsp_allocated_buf == NULL) {
+		res = _FAIL;
+		goto exit;
+	}
+
+	pcmdpriv->rsp_buf = pcmdpriv->rsp_allocated_buf  +  4 - ((SIZE_PTR)(pcmdpriv->rsp_allocated_buf) & 3);
+
+	pcmdpriv->cmd_issued_cnt = pcmdpriv->cmd_done_cnt = pcmdpriv->rsp_cnt = 0;
+
+	_rtw_mutex_init(&pcmdpriv->sctx_mutex);
+exit:
+
+
+	return res;
+
+}
+
+#ifdef CONFIG_C2H_WK
+static void c2h_wk_callback(_workitem *work)
+{
+	struct evt_priv *evtpriv = container_of(work, struct evt_priv, c2h_wk);
+	_adapter *adapter = container_of(evtpriv, _adapter, evtpriv);
+	u8 *c2h_evt;
+	c2h_id_filter direct_hdl_filter = rtw_hal_c2h_id_handle_directly;
+	u8 id, seq, plen;
+	u8 *payload;
+
+	evtpriv->c2h_wk_alive = _TRUE;
+
+	while (!rtw_cbuf_empty(evtpriv->c2h_queue)) {
+		c2h_evt = (u8 *)rtw_cbuf_pop(evtpriv->c2h_queue);
+		if (c2h_evt != NULL) {
+			/* This C2H event is read, clear it */
+			c2h_evt_clear(adapter);
+		} else {
+			c2h_evt = (u8 *)rtw_malloc(C2H_REG_LEN);
+			if (c2h_evt == NULL) {
+				rtw_warn_on(1);
+				continue;
+			}
+
+			/* This C2H event is not read, read & clear now */
+			if (rtw_hal_c2h_evt_read(adapter, c2h_evt) != _SUCCESS) {
+				rtw_mfree(c2h_evt, C2H_REG_LEN);
+				continue;
+			}
+		}
+
+		/* Special pointer to trigger c2h_evt_clear only */
+		if ((void *)c2h_evt == (void *)evtpriv)
+			continue;
+
+		if (!rtw_hal_c2h_valid(adapter, c2h_evt)
+			|| rtw_hal_c2h_reg_hdr_parse(adapter, c2h_evt, &id, &seq, &plen, &payload) != _SUCCESS
+		) {
+			rtw_mfree(c2h_evt, C2H_REG_LEN);
+			continue;
+		}
+
+		if (direct_hdl_filter(adapter, id, seq, plen, payload) == _TRUE) {
+			/* Handle directly */
+			rtw_hal_c2h_handler(adapter, id, seq, plen, payload);
+			rtw_mfree(c2h_evt, C2H_REG_LEN);
+		} else {
+			/* Enqueue into cmd_thread for others */
+			rtw_c2h_reg_wk_cmd(adapter, c2h_evt);
+			rtw_mfree(c2h_evt, C2H_REG_LEN);
+		}
+	}
+
+	evtpriv->c2h_wk_alive = _FALSE;
+}
+#endif /* CONFIG_C2H_WK */
+
+sint _rtw_init_evt_priv(struct evt_priv *pevtpriv)
+{
+	sint res = _SUCCESS;
+
+
+#ifdef CONFIG_H2CLBK
+	_rtw_init_sema(&(pevtpriv->lbkevt_done), 0);
+	pevtpriv->lbkevt_limit = 0;
+	pevtpriv->lbkevt_num = 0;
+	pevtpriv->cmdevt_parm = NULL;
+#endif
+
+	/* allocate DMA-able/Non-Page memory for cmd_buf and rsp_buf */
+	ATOMIC_SET(&pevtpriv->event_seq, 0);
+	pevtpriv->evt_done_cnt = 0;
+
+#ifdef CONFIG_EVENT_THREAD_MODE
+
+	_rtw_init_sema(&(pevtpriv->evt_notify), 0);
+
+	pevtpriv->evt_allocated_buf = rtw_zmalloc(MAX_EVTSZ + 4);
+	if (pevtpriv->evt_allocated_buf == NULL) {
+		res = _FAIL;
+		goto exit;
+	}
+	pevtpriv->evt_buf = pevtpriv->evt_allocated_buf  +  4 - ((unsigned int)(pevtpriv->evt_allocated_buf) & 3);
+
+
+#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
+	pevtpriv->allocated_c2h_mem = rtw_zmalloc(C2H_MEM_SZ + 4);
+
+	if (pevtpriv->allocated_c2h_mem == NULL) {
+		res = _FAIL;
+		goto exit;
+	}
+
+	pevtpriv->c2h_mem = pevtpriv->allocated_c2h_mem +  4\
+			    - ((u32)(pevtpriv->allocated_c2h_mem) & 3);
+#ifdef PLATFORM_OS_XP
+	pevtpriv->pc2h_mdl = IoAllocateMdl((u8 *)pevtpriv->c2h_mem, C2H_MEM_SZ , FALSE, FALSE, NULL);
+
+	if (pevtpriv->pc2h_mdl == NULL) {
+		res = _FAIL;
+		goto exit;
+	}
+	MmBuildMdlForNonPagedPool(pevtpriv->pc2h_mdl);
+#endif
+#endif /* end of CONFIG_SDIO_HCI */
+
+	_rtw_init_queue(&(pevtpriv->evt_queue));
+
+exit:
+
+#endif /* end of CONFIG_EVENT_THREAD_MODE */
+
+#ifdef CONFIG_C2H_WK
+	_init_workitem(&pevtpriv->c2h_wk, c2h_wk_callback, NULL);
+	pevtpriv->c2h_wk_alive = _FALSE;
+	pevtpriv->c2h_queue = rtw_cbuf_alloc(C2H_QUEUE_MAX_LEN + 1);
+#endif
+
+
+	return res;
+}
+
+void _rtw_free_evt_priv(struct	evt_priv *pevtpriv)
+{
+
+
+#ifdef CONFIG_EVENT_THREAD_MODE
+	_rtw_free_sema(&(pevtpriv->evt_notify));
+
+	if (pevtpriv->evt_allocated_buf)
+		rtw_mfree(pevtpriv->evt_allocated_buf, MAX_EVTSZ + 4);
+#endif
+
+#ifdef CONFIG_C2H_WK
+	_cancel_workitem_sync(&pevtpriv->c2h_wk);
+	while (pevtpriv->c2h_wk_alive)
+		rtw_msleep_os(10);
+
+	while (!rtw_cbuf_empty(pevtpriv->c2h_queue)) {
+		void *c2h;
+		c2h = rtw_cbuf_pop(pevtpriv->c2h_queue);
+		if (c2h != NULL && c2h != (void *)pevtpriv)
+			rtw_mfree(c2h, 16);
+	}
+	rtw_cbuf_free(pevtpriv->c2h_queue);
+#endif
+
+
+
+}
+
+void _rtw_free_cmd_priv(struct	cmd_priv *pcmdpriv)
+{
+
+	if (pcmdpriv) {
+		_rtw_spinlock_free(&(pcmdpriv->cmd_queue.lock));
+		_rtw_free_sema(&(pcmdpriv->cmd_queue_sema));
+		/* _rtw_free_sema(&(pcmdpriv->cmd_done_sema)); */
+		_rtw_free_sema(&(pcmdpriv->start_cmdthread_sema));
+
+		if (pcmdpriv->cmd_allocated_buf)
+			rtw_mfree(pcmdpriv->cmd_allocated_buf, MAX_CMDSZ + CMDBUFF_ALIGN_SZ);
+
+		if (pcmdpriv->rsp_allocated_buf)
+			rtw_mfree(pcmdpriv->rsp_allocated_buf, MAX_RSPSZ + 4);
+
+		_rtw_mutex_free(&pcmdpriv->sctx_mutex);
+	}
+}
+
+/*
+Calling Context:
+
+rtw_enqueue_cmd can only be called between kernel thread,
+since only spin_lock is used.
+
+ISR/Call-Back functions can't call this sub-function.
+
+*/
+#ifdef DBG_CMD_QUEUE
+extern u8 dump_cmd_id;
+#endif
+
+sint _rtw_enqueue_cmd(_queue *queue, struct cmd_obj *obj, bool to_head)
+{
+	_irqL irqL;
+
+
+	if (obj == NULL)
+		goto exit;
+
+	/* _enter_critical_bh(&queue->lock, &irqL); */
+	_enter_critical(&queue->lock, &irqL);
+
+	if (to_head)
+		rtw_list_insert_head(&obj->list, &queue->queue);
+	else
+		rtw_list_insert_tail(&obj->list, &queue->queue);
+
+#ifdef DBG_CMD_QUEUE
+	if (dump_cmd_id) {
+		printk("%s===> cmdcode:0x%02x\n", __FUNCTION__, obj->cmdcode);
+		if (obj->cmdcode == GEN_CMD_CODE(_Set_MLME_EVT)) {
+			if (obj->parmbuf) {
+				struct C2HEvent_Header *pc2h_evt_hdr = (struct C2HEvent_Header *)(obj->parmbuf);
+				printk("pc2h_evt_hdr->ID:0x%02x(%d)\n", pc2h_evt_hdr->ID, pc2h_evt_hdr->ID);
+			}
+		}
+		if (obj->cmdcode == GEN_CMD_CODE(_Set_Drv_Extra)) {
+			if (obj->parmbuf) {
+				struct drvextra_cmd_parm *pdrvextra_cmd_parm = (struct drvextra_cmd_parm *)(obj->parmbuf);
+				printk("pdrvextra_cmd_parm->ec_id:0x%02x\n", pdrvextra_cmd_parm->ec_id);
+			}
+		}
+	}
+
+	if (queue->queue.prev->next != &queue->queue) {
+		RTW_INFO("[%d] head %p, tail %p, tail->prev->next %p[tail], tail->next %p[head]\n", __LINE__,
+			&queue->queue, queue->queue.prev, queue->queue.prev->prev->next, queue->queue.prev->next);
+
+		RTW_INFO("==========%s============\n", __FUNCTION__);
+		RTW_INFO("head:%p,obj_addr:%p\n", &queue->queue, obj);
+		RTW_INFO("padapter: %p\n", obj->padapter);
+		RTW_INFO("cmdcode: 0x%02x\n", obj->cmdcode);
+		RTW_INFO("res: %d\n", obj->res);
+		RTW_INFO("parmbuf: %p\n", obj->parmbuf);
+		RTW_INFO("cmdsz: %d\n", obj->cmdsz);
+		RTW_INFO("rsp: %p\n", obj->rsp);
+		RTW_INFO("rspsz: %d\n", obj->rspsz);
+		RTW_INFO("sctx: %p\n", obj->sctx);
+		RTW_INFO("list->next: %p\n", obj->list.next);
+		RTW_INFO("list->prev: %p\n", obj->list.prev);
+	}
+#endif /* DBG_CMD_QUEUE */
+
+	/* _exit_critical_bh(&queue->lock, &irqL);	 */
+	_exit_critical(&queue->lock, &irqL);
+
+exit:
+
+
+	return _SUCCESS;
+}
+
+struct	cmd_obj	*_rtw_dequeue_cmd(_queue *queue)
+{
+	_irqL irqL;
+	struct cmd_obj *obj;
+
+
+	/* _enter_critical_bh(&(queue->lock), &irqL); */
+	_enter_critical(&queue->lock, &irqL);
+
+#ifdef DBG_CMD_QUEUE
+	if (queue->queue.prev->next != &queue->queue) {
+		RTW_INFO("[%d] head %p, tail %p, tail->prev->next %p[tail], tail->next %p[head]\n", __LINE__,
+			&queue->queue, queue->queue.prev, queue->queue.prev->prev->next, queue->queue.prev->next);
+	}
+#endif /* DBG_CMD_QUEUE */
+
+
+	if (rtw_is_list_empty(&(queue->queue)))
+		obj = NULL;
+	else {
+		obj = LIST_CONTAINOR(get_next(&(queue->queue)), struct cmd_obj, list);
+
+#ifdef DBG_CMD_QUEUE
+		if (queue->queue.prev->next != &queue->queue) {
+			RTW_INFO("==========%s============\n", __FUNCTION__);
+			RTW_INFO("head:%p,obj_addr:%p\n", &queue->queue, obj);
+			RTW_INFO("padapter: %p\n", obj->padapter);
+			RTW_INFO("cmdcode: 0x%02x\n", obj->cmdcode);
+			RTW_INFO("res: %d\n", obj->res);
+			RTW_INFO("parmbuf: %p\n", obj->parmbuf);
+			RTW_INFO("cmdsz: %d\n", obj->cmdsz);
+			RTW_INFO("rsp: %p\n", obj->rsp);
+			RTW_INFO("rspsz: %d\n", obj->rspsz);
+			RTW_INFO("sctx: %p\n", obj->sctx);
+			RTW_INFO("list->next: %p\n", obj->list.next);
+			RTW_INFO("list->prev: %p\n", obj->list.prev);
+		}
+
+		if (dump_cmd_id) {
+			RTW_INFO("%s===> cmdcode:0x%02x\n", __FUNCTION__, obj->cmdcode);
+			if (obj->cmdcode == GEN_CMD_CODE(_Set_Drv_Extra)) {
+				if (obj->parmbuf) {
+					struct drvextra_cmd_parm *pdrvextra_cmd_parm = (struct drvextra_cmd_parm *)(obj->parmbuf);
+					printk("pdrvextra_cmd_parm->ec_id:0x%02x\n", pdrvextra_cmd_parm->ec_id);
+				}
+			}
+
+		}
+#endif /* DBG_CMD_QUEUE */
+
+		rtw_list_delete(&obj->list);
+	}
+
+	/* _exit_critical_bh(&(queue->lock), &irqL); */
+	_exit_critical(&queue->lock, &irqL);
+
+
+	return obj;
+}
+
+u32	rtw_init_cmd_priv(struct cmd_priv *pcmdpriv)
+{
+	u32	res;
+	res = _rtw_init_cmd_priv(pcmdpriv);
+	return res;
+}
+
+u32	rtw_init_evt_priv(struct	evt_priv *pevtpriv)
+{
+	int	res;
+	res = _rtw_init_evt_priv(pevtpriv);
+	return res;
+}
+
+void rtw_free_evt_priv(struct	evt_priv *pevtpriv)
+{
+	_rtw_free_evt_priv(pevtpriv);
+}
+
+void rtw_free_cmd_priv(struct	cmd_priv *pcmdpriv)
+{
+	_rtw_free_cmd_priv(pcmdpriv);
+}
+
+int rtw_cmd_filter(struct cmd_priv *pcmdpriv, struct cmd_obj *cmd_obj);
+int rtw_cmd_filter(struct cmd_priv *pcmdpriv, struct cmd_obj *cmd_obj)
+{
+	u8 bAllow = _FALSE; /* set to _TRUE to allow enqueuing cmd when hw_init_completed is _FALSE */
+
+#ifdef SUPPORT_HW_RFOFF_DETECTED
+	/* To decide allow or not */
+	if ((adapter_to_pwrctl(pcmdpriv->padapter)->bHWPwrPindetect)
+	    && (!pcmdpriv->padapter->registrypriv.usbss_enable)
+	   ) {
+		if (cmd_obj->cmdcode == GEN_CMD_CODE(_Set_Drv_Extra)) {
+			struct drvextra_cmd_parm	*pdrvextra_cmd_parm = (struct drvextra_cmd_parm *)cmd_obj->parmbuf;
+			if (pdrvextra_cmd_parm->ec_id == POWER_SAVING_CTRL_WK_CID) {
+				/* RTW_INFO("==>enqueue POWER_SAVING_CTRL_WK_CID\n"); */
+				bAllow = _TRUE;
+			}
+		}
+	}
+#endif
+
+	if (cmd_obj->cmdcode == GEN_CMD_CODE(_SetChannelPlan))
+		bAllow = _TRUE;
+
+	if (cmd_obj->no_io)
+		bAllow = _TRUE;
+
+	if ((!rtw_is_hw_init_completed(pcmdpriv->padapter) && (bAllow == _FALSE))
+	    || ATOMIC_READ(&(pcmdpriv->cmdthd_running)) == _FALSE	/* com_thread not running */
+	   ) {
+		if (DBG_CMD_EXECUTE)
+			RTW_INFO(ADPT_FMT" drop "CMD_FMT" hw_init_completed:%u, cmdthd_running:%u\n", ADPT_ARG(cmd_obj->padapter)
+				, CMD_ARG(cmd_obj), rtw_get_hw_init_completed(cmd_obj->padapter), ATOMIC_READ(&pcmdpriv->cmdthd_running));
+		if (0)
+			rtw_warn_on(1);
+
+		return _FAIL;
+	}
+	return _SUCCESS;
+}
+
+
+
+u32 rtw_enqueue_cmd(struct cmd_priv *pcmdpriv, struct cmd_obj *cmd_obj)
+{
+	int res = _FAIL;
+	PADAPTER padapter = pcmdpriv->padapter;
+
+
+	if (cmd_obj == NULL)
+		goto exit;
+
+	cmd_obj->padapter = padapter;
+
+#ifdef CONFIG_CONCURRENT_MODE
+	/* change pcmdpriv to primary's pcmdpriv */
+	if (!is_primary_adapter(padapter))
+		pcmdpriv = &(GET_PRIMARY_ADAPTER(padapter)->cmdpriv);
+#endif
+
+	res = rtw_cmd_filter(pcmdpriv, cmd_obj);
+	if ((_FAIL == res) || (cmd_obj->cmdsz > MAX_CMDSZ)) {
+		if (cmd_obj->cmdsz > MAX_CMDSZ) {
+			RTW_INFO("%s failed due to obj->cmdsz(%d) > MAX_CMDSZ(%d)\n", __func__, cmd_obj->cmdsz, MAX_CMDSZ);
+			rtw_warn_on(1);
+		}
+
+		if (cmd_obj->cmdcode == GEN_CMD_CODE(_Set_Drv_Extra)) {
+			struct drvextra_cmd_parm *extra_parm = (struct drvextra_cmd_parm *)cmd_obj->parmbuf;
+
+			if (extra_parm->pbuf && extra_parm->size > 0)
+				rtw_mfree(extra_parm->pbuf, extra_parm->size);
+		}
+		rtw_free_cmd_obj(cmd_obj);
+		goto exit;
+	}
+
+	res = _rtw_enqueue_cmd(&pcmdpriv->cmd_queue, cmd_obj, 0);
+
+	if (res == _SUCCESS)
+		_rtw_up_sema(&pcmdpriv->cmd_queue_sema);
+
+exit:
+
+
+	return res;
+}
+
+struct	cmd_obj	*rtw_dequeue_cmd(struct cmd_priv *pcmdpriv)
+{
+	struct cmd_obj *cmd_obj;
+
+
+	cmd_obj = _rtw_dequeue_cmd(&pcmdpriv->cmd_queue);
+
+	return cmd_obj;
+}
+
+void rtw_cmd_clr_isr(struct	cmd_priv *pcmdpriv)
+{
+	pcmdpriv->cmd_done_cnt++;
+	/* _rtw_up_sema(&(pcmdpriv->cmd_done_sema)); */
+}
+
+void rtw_free_cmd_obj(struct cmd_obj *pcmd)
+{
+	if (pcmd->parmbuf != NULL) {
+		/* free parmbuf in cmd_obj */
+		rtw_mfree((unsigned char *)pcmd->parmbuf, pcmd->cmdsz);
+	}
+	if (pcmd->rsp != NULL) {
+		if (pcmd->rspsz != 0) {
+			/* free rsp in cmd_obj */
+			rtw_mfree((unsigned char *)pcmd->rsp, pcmd->rspsz);
+		}
+	}
+
+	/* free cmd_obj */
+	rtw_mfree((unsigned char *)pcmd, sizeof(struct cmd_obj));
+}
+
+
+void rtw_stop_cmd_thread(_adapter *adapter)
+{
+	if (adapter->cmdThread) {
+		_rtw_up_sema(&adapter->cmdpriv.cmd_queue_sema);
+		rtw_thread_stop(adapter->cmdThread);
+		adapter->cmdThread = NULL;
+	}
+}
+
+thread_return rtw_cmd_thread(thread_context context)
+{
+	u8 ret;
+	struct cmd_obj *pcmd;
+	u8 *pcmdbuf, *prspbuf;
+	systime cmd_start_time;
+	u32 cmd_process_time;
+	u8(*cmd_hdl)(_adapter *padapter, u8 *pbuf);
+	void (*pcmd_callback)(_adapter *dev, struct cmd_obj *pcmd);
+	PADAPTER padapter = (PADAPTER)context;
+	struct cmd_priv *pcmdpriv = &(padapter->cmdpriv);
+	struct drvextra_cmd_parm *extra_parm = NULL;
+	_irqL irqL;
+
+	thread_enter("RTW_CMD_THREAD");
+
+	pcmdbuf = pcmdpriv->cmd_buf;
+	prspbuf = pcmdpriv->rsp_buf;
+	ATOMIC_SET(&(pcmdpriv->cmdthd_running), _TRUE);
+	_rtw_up_sema(&pcmdpriv->start_cmdthread_sema);
+
+
+	while (1) {
+		if (_rtw_down_sema(&pcmdpriv->cmd_queue_sema) == _FAIL) {
+			RTW_PRINT(FUNC_ADPT_FMT" _rtw_down_sema(&pcmdpriv->cmd_queue_sema) return _FAIL, break\n", FUNC_ADPT_ARG(padapter));
+			break;
+		}
+
+		if (RTW_CANNOT_RUN(padapter)) {
+			RTW_DBG(FUNC_ADPT_FMT "- bDriverStopped(%s) bSurpriseRemoved(%s)\n",
+				FUNC_ADPT_ARG(padapter),
+				rtw_is_drv_stopped(padapter) ? "True" : "False",
+				rtw_is_surprise_removed(padapter) ? "True" : "False");
+			break;
+		}
+
+		_enter_critical(&pcmdpriv->cmd_queue.lock, &irqL);
+		if (rtw_is_list_empty(&(pcmdpriv->cmd_queue.queue))) {
+			/* RTW_INFO("%s: cmd queue is empty!\n", __func__); */
+			_exit_critical(&pcmdpriv->cmd_queue.lock, &irqL);
+			continue;
+		}
+		_exit_critical(&pcmdpriv->cmd_queue.lock, &irqL);
+
+_next:
+		if (RTW_CANNOT_RUN(padapter)) {
+			RTW_PRINT("%s: DriverStopped(%s) SurpriseRemoved(%s) break at line %d\n",
+				  __func__
+				, rtw_is_drv_stopped(padapter) ? "True" : "False"
+				, rtw_is_surprise_removed(padapter) ? "True" : "False"
+				  , __LINE__);
+			break;
+		}
+
+		pcmd = rtw_dequeue_cmd(pcmdpriv);
+		if (!pcmd) {
+#ifdef CONFIG_LPS_LCLK
+			rtw_unregister_cmd_alive(padapter);
+#endif
+			continue;
+		}
+
+		cmd_start_time = rtw_get_current_time();
+		pcmdpriv->cmd_issued_cnt++;
+
+		if (pcmd->cmdsz > MAX_CMDSZ) {
+			RTW_ERR("%s cmdsz:%d > MAX_CMDSZ:%d\n", __func__, pcmd->cmdsz, MAX_CMDSZ);
+			pcmd->res = H2C_PARAMETERS_ERROR;
+			goto post_process;
+		}
+
+		if (pcmd->cmdcode >= (sizeof(wlancmds) / sizeof(struct cmd_hdl))) {
+			RTW_ERR("%s undefined cmdcode:%d\n", __func__, pcmd->cmdcode);
+			pcmd->res = H2C_PARAMETERS_ERROR;
+			goto post_process;
+		}
+
+		cmd_hdl = wlancmds[pcmd->cmdcode].h2cfuns;
+		if (!cmd_hdl) {
+			RTW_ERR("%s no cmd_hdl for cmdcode:%d\n", __func__, pcmd->cmdcode);
+			pcmd->res = H2C_PARAMETERS_ERROR;
+			goto post_process;
+		}
+
+		if (_FAIL == rtw_cmd_filter(pcmdpriv, pcmd)) {
+			pcmd->res = H2C_DROPPED;
+			if (pcmd->cmdcode == GEN_CMD_CODE(_Set_Drv_Extra)) {
+				extra_parm = (struct drvextra_cmd_parm *)pcmd->parmbuf;
+				if (extra_parm && extra_parm->pbuf && extra_parm->size > 0)
+					rtw_mfree(extra_parm->pbuf, extra_parm->size);
+			}
+			#ifdef CONFIG_DFS
+			else if (pcmd->cmdcode == GEN_CMD_CODE(_SetChannelSwitch))
+				adapter_to_rfctl(padapter)->csa_ch = 0;
+			#endif
+			goto post_process;
+		}
+
+#ifdef CONFIG_LPS_LCLK
+		if (pcmd->no_io)
+			rtw_unregister_cmd_alive(padapter);
+		else {
+			if (rtw_register_cmd_alive(padapter) != _SUCCESS) {
+				if (DBG_CMD_EXECUTE)
+					RTW_PRINT("%s: wait to leave LPS_LCLK\n", __func__);
+
+				pcmd->res = H2C_ENQ_HEAD;
+				ret = _rtw_enqueue_cmd(&pcmdpriv->cmd_queue, pcmd, 1);
+				if (ret == _SUCCESS) {
+					if (DBG_CMD_EXECUTE)
+						RTW_INFO(ADPT_FMT" "CMD_FMT" ENQ_HEAD\n", ADPT_ARG(pcmd->padapter), CMD_ARG(pcmd));
+					continue;
+				}
+
+				RTW_INFO(ADPT_FMT" "CMD_FMT" ENQ_HEAD_FAIL\n", ADPT_ARG(pcmd->padapter), CMD_ARG(pcmd));
+				pcmd->res = H2C_ENQ_HEAD_FAIL;
+				rtw_warn_on(1);
+			}
+		}
+#endif /* CONFIG_LPS_LCLK */
+
+		if (DBG_CMD_EXECUTE)
+			RTW_INFO(ADPT_FMT" "CMD_FMT" %sexecute\n", ADPT_ARG(pcmd->padapter), CMD_ARG(pcmd)
+				, pcmd->res == H2C_ENQ_HEAD ? "ENQ_HEAD " : (pcmd->res == H2C_ENQ_HEAD_FAIL ? "ENQ_HEAD_FAIL " : ""));
+
+		_rtw_memcpy(pcmdbuf, pcmd->parmbuf, pcmd->cmdsz);
+		ret = cmd_hdl(pcmd->padapter, pcmdbuf);
+		pcmd->res = ret;
+
+		pcmdpriv->cmd_seq++;
+
+post_process:
+
+		_enter_critical_mutex(&(pcmd->padapter->cmdpriv.sctx_mutex), NULL);
+		if (pcmd->sctx) {
+			if (0)
+				RTW_PRINT(FUNC_ADPT_FMT" pcmd->sctx\n", FUNC_ADPT_ARG(pcmd->padapter));
+			if (pcmd->res == H2C_SUCCESS)
+				rtw_sctx_done(&pcmd->sctx);
+			else
+				rtw_sctx_done_err(&pcmd->sctx, RTW_SCTX_DONE_CMD_ERROR);
+		}
+		_exit_critical_mutex(&(pcmd->padapter->cmdpriv.sctx_mutex), NULL);
+
+		cmd_process_time = rtw_get_passing_time_ms(cmd_start_time);
+		if (cmd_process_time > 1000) {
+			RTW_INFO(ADPT_FMT" "CMD_FMT" process_time=%d\n", ADPT_ARG(pcmd->padapter), CMD_ARG(pcmd), cmd_process_time);
+			if (0)
+				rtw_warn_on(1);
+		}
+
+		/* call callback function for post-processed */
+		if (pcmd->cmdcode < (sizeof(rtw_cmd_callback) / sizeof(struct _cmd_callback))) {
+			pcmd_callback = rtw_cmd_callback[pcmd->cmdcode].callback;
+			if (pcmd_callback == NULL) {
+				rtw_free_cmd_obj(pcmd);
+			} else {
+				/* todo: !!! fill rsp_buf to pcmd->rsp if (pcmd->rsp!=NULL) */
+				pcmd_callback(pcmd->padapter, pcmd);/* need conider that free cmd_obj in rtw_cmd_callback */
+			}
+		} else {
+			rtw_free_cmd_obj(pcmd);
+		}
+
+		flush_signals_thread();
+
+		goto _next;
+
+	}
+
+#ifdef CONFIG_LPS_LCLK
+	rtw_unregister_cmd_alive(padapter);
+#endif
+
+	/* to avoid enqueue cmd after free all cmd_obj */
+	ATOMIC_SET(&(pcmdpriv->cmdthd_running), _FALSE);
+
+	/* free all cmd_obj resources */
+	do {
+		pcmd = rtw_dequeue_cmd(pcmdpriv);
+		if (pcmd == NULL)
+			break;
+
+		if (0)
+			RTW_INFO("%s: leaving... drop "CMD_FMT"\n", __func__, CMD_ARG(pcmd));
+
+		if (pcmd->cmdcode == GEN_CMD_CODE(_Set_Drv_Extra)) {
+			extra_parm = (struct drvextra_cmd_parm *)pcmd->parmbuf;
+			if (extra_parm->pbuf && extra_parm->size > 0)
+				rtw_mfree(extra_parm->pbuf, extra_parm->size);
+		}
+		#ifdef CONFIG_DFS
+		else if (pcmd->cmdcode == GEN_CMD_CODE(_SetChannelSwitch))
+			adapter_to_rfctl(padapter)->csa_ch = 0;
+		#endif
+
+		_enter_critical_mutex(&(pcmd->padapter->cmdpriv.sctx_mutex), NULL);
+		if (pcmd->sctx) {
+			if (0)
+				RTW_PRINT(FUNC_ADPT_FMT" pcmd->sctx\n", FUNC_ADPT_ARG(pcmd->padapter));
+			rtw_sctx_done_err(&pcmd->sctx, RTW_SCTX_DONE_CMD_DROP);
+		}
+		_exit_critical_mutex(&(pcmd->padapter->cmdpriv.sctx_mutex), NULL);
+
+		rtw_free_cmd_obj(pcmd);
+	} while (1);
+
+	RTW_INFO(FUNC_ADPT_FMT " Exit\n", FUNC_ADPT_ARG(padapter));
+
+	rtw_thread_wait_stop();
+
+	return 0;
+}
+
+
+#ifdef CONFIG_EVENT_THREAD_MODE
+u32 rtw_enqueue_evt(struct evt_priv *pevtpriv, struct evt_obj *obj)
+{
+	_irqL irqL;
+	int	res;
+	_queue *queue = &pevtpriv->evt_queue;
+
+
+	res = _SUCCESS;
+
+	if (obj == NULL) {
+		res = _FAIL;
+		goto exit;
+	}
+
+	_enter_critical_bh(&queue->lock, &irqL);
+
+	rtw_list_insert_tail(&obj->list, &queue->queue);
+
+	_exit_critical_bh(&queue->lock, &irqL);
+
+	/* rtw_evt_notify_isr(pevtpriv); */
+
+exit:
+
+
+	return res;
+}
+
+struct evt_obj *rtw_dequeue_evt(_queue *queue)
+{
+	_irqL irqL;
+	struct	evt_obj	*pevtobj;
+
+
+	_enter_critical_bh(&queue->lock, &irqL);
+
+	if (rtw_is_list_empty(&(queue->queue)))
+		pevtobj = NULL;
+	else {
+		pevtobj = LIST_CONTAINOR(get_next(&(queue->queue)), struct evt_obj, list);
+		rtw_list_delete(&pevtobj->list);
+	}
+
+	_exit_critical_bh(&queue->lock, &irqL);
+
+
+	return pevtobj;
+}
+
+void rtw_free_evt_obj(struct evt_obj *pevtobj)
+{
+
+	if (pevtobj->parmbuf)
+		rtw_mfree((unsigned char *)pevtobj->parmbuf, pevtobj->evtsz);
+
+	rtw_mfree((unsigned char *)pevtobj, sizeof(struct evt_obj));
+
+}
+
+void rtw_evt_notify_isr(struct evt_priv *pevtpriv)
+{
+	pevtpriv->evt_done_cnt++;
+	_rtw_up_sema(&(pevtpriv->evt_notify));
+}
+#endif
+
+
+/*
+u8 rtw_setstandby_cmd(unsigned char  *adapter)
+*/
+u8 rtw_setstandby_cmd(_adapter *padapter, uint action)
+{
+	struct cmd_obj			*ph2c;
+	struct usb_suspend_parm	*psetusbsuspend;
+	struct cmd_priv			*pcmdpriv = &padapter->cmdpriv;
+
+	u8 ret = _SUCCESS;
+
+
+	ph2c = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj));
+	if (ph2c == NULL) {
+		ret = _FAIL;
+		goto exit;
+	}
+
+	psetusbsuspend = (struct usb_suspend_parm *)rtw_zmalloc(sizeof(struct usb_suspend_parm));
+	if (psetusbsuspend == NULL) {
+		rtw_mfree((u8 *) ph2c, sizeof(struct	cmd_obj));
+		ret = _FAIL;
+		goto exit;
+	}
+
+	psetusbsuspend->action = action;
+
+	init_h2fwcmd_w_parm_no_rsp(ph2c, psetusbsuspend, GEN_CMD_CODE(_SetUsbSuspend));
+
+	ret = rtw_enqueue_cmd(pcmdpriv, ph2c);
+
+exit:
+
+
+	return ret;
+}
+
+void rtw_init_sitesurvey_parm(_adapter *padapter, struct sitesurvey_parm *pparm)
+{
+	struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
+
+
+	_rtw_memset(pparm, 0, sizeof(struct sitesurvey_parm));
+	pparm->scan_mode = pmlmepriv->scan_mode;
+}
+
+/*
+rtw_sitesurvey_cmd(~)
+	### NOTE:#### (!!!!)
+	MUST TAKE CARE THAT BEFORE CALLING THIS FUNC, YOU SHOULD HAVE LOCKED pmlmepriv->lock
+*/
+u8 rtw_sitesurvey_cmd(_adapter *padapter, struct sitesurvey_parm *pparm)
+{
+	u8 res = _FAIL;
+	struct cmd_obj		*ph2c;
+	struct sitesurvey_parm	*psurveyPara;
+	struct cmd_priv	*pcmdpriv = &padapter->cmdpriv;
+	struct mlme_priv	*pmlmepriv = &padapter->mlmepriv;
+
+#ifdef CONFIG_LPS
+	if (check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE)
+		rtw_lps_ctrl_wk_cmd(padapter, LPS_CTRL_SCAN, 1);
+#endif
+
+#ifdef CONFIG_P2P_PS
+	if (check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE)
+		p2p_ps_wk_cmd(padapter, P2P_PS_SCAN, 1);
+#endif /* CONFIG_P2P_PS */
+
+	ph2c = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj));
+	if (ph2c == NULL)
+		return _FAIL;
+
+	psurveyPara = (struct sitesurvey_parm *)rtw_zmalloc(sizeof(struct sitesurvey_parm));
+	if (psurveyPara == NULL) {
+		rtw_mfree((unsigned char *) ph2c, sizeof(struct cmd_obj));
+		return _FAIL;
+	}
+
+	if (pparm)
+		_rtw_memcpy(psurveyPara, pparm, sizeof(struct sitesurvey_parm));
+	else
+		psurveyPara->scan_mode = pmlmepriv->scan_mode;
+
+	rtw_free_network_queue(padapter, _FALSE);
+
+	init_h2fwcmd_w_parm_no_rsp(ph2c, psurveyPara, GEN_CMD_CODE(_SiteSurvey));
+
+	set_fwstate(pmlmepriv, _FW_UNDER_SURVEY);
+
+	res = rtw_enqueue_cmd(pcmdpriv, ph2c);
+
+	if (res == _SUCCESS) {
+		u32 scan_timeout_ms;
+
+		pmlmepriv->scan_start_time = rtw_get_current_time();
+		scan_timeout_ms = rtw_scan_timeout_decision(padapter);
+		mlme_set_scan_to_timer(pmlmepriv,scan_timeout_ms);
+
+		rtw_led_control(padapter, LED_CTL_SITE_SURVEY);
+	} else
+		_clr_fwstate_(pmlmepriv, _FW_UNDER_SURVEY);
+
+
+	return res;
+}
+
+u8 rtw_setdatarate_cmd(_adapter *padapter, u8 *rateset)
+{
+	struct cmd_obj			*ph2c;
+	struct setdatarate_parm	*pbsetdataratepara;
+	struct cmd_priv		*pcmdpriv = &padapter->cmdpriv;
+	u8	res = _SUCCESS;
+
+
+	ph2c = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj));
+	if (ph2c == NULL) {
+		res = _FAIL;
+		goto exit;
+	}
+
+	pbsetdataratepara = (struct setdatarate_parm *)rtw_zmalloc(sizeof(struct setdatarate_parm));
+	if (pbsetdataratepara == NULL) {
+		rtw_mfree((u8 *) ph2c, sizeof(struct cmd_obj));
+		res = _FAIL;
+		goto exit;
+	}
+
+	init_h2fwcmd_w_parm_no_rsp(ph2c, pbsetdataratepara, GEN_CMD_CODE(_SetDataRate));
+#ifdef MP_FIRMWARE_OFFLOAD
+	pbsetdataratepara->curr_rateidx = *(u32 *)rateset;
+	/*	_rtw_memcpy(pbsetdataratepara, rateset, sizeof(u32)); */
+#else
+	pbsetdataratepara->mac_id = 5;
+	_rtw_memcpy(pbsetdataratepara->datarates, rateset, NumRates);
+#endif
+	res = rtw_enqueue_cmd(pcmdpriv, ph2c);
+exit:
+
+
+	return res;
+}
+
+u8 rtw_setbasicrate_cmd(_adapter *padapter, u8 *rateset)
+{
+	struct cmd_obj			*ph2c;
+	struct setbasicrate_parm	*pssetbasicratepara;
+	struct cmd_priv		*pcmdpriv = &padapter->cmdpriv;
+	u8	res = _SUCCESS;
+
+
+	ph2c = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj));
+	if (ph2c == NULL) {
+		res = _FAIL;
+		goto exit;
+	}
+	pssetbasicratepara = (struct setbasicrate_parm *)rtw_zmalloc(sizeof(struct setbasicrate_parm));
+
+	if (pssetbasicratepara == NULL) {
+		rtw_mfree((u8 *) ph2c, sizeof(struct cmd_obj));
+		res = _FAIL;
+		goto exit;
+	}
+
+	init_h2fwcmd_w_parm_no_rsp(ph2c, pssetbasicratepara, _SetBasicRate_CMD_);
+
+	_rtw_memcpy(pssetbasicratepara->basicrates, rateset, NumRates);
+
+	res = rtw_enqueue_cmd(pcmdpriv, ph2c);
+exit:
+
+
+	return res;
+}
+
+
+/*
+unsigned char rtw_setphy_cmd(unsigned char  *adapter)
+
+1.  be called only after rtw_update_registrypriv_dev_network( ~) or mp testing program
+2.  for AdHoc/Ap mode or mp mode?
+
+*/
+u8 rtw_setphy_cmd(_adapter *padapter, u8 modem, u8 ch)
+{
+	struct cmd_obj			*ph2c;
+	struct setphy_parm		*psetphypara;
+	struct cmd_priv			*pcmdpriv = &padapter->cmdpriv;
+	/*	struct mlme_priv			*pmlmepriv = &padapter->mlmepriv;
+	 *	struct registry_priv*		pregistry_priv = &padapter->registrypriv; */
+	u8	res = _SUCCESS;
+
+
+	ph2c = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj));
+	if (ph2c == NULL) {
+		res = _FAIL;
+		goto exit;
+	}
+	psetphypara = (struct setphy_parm *)rtw_zmalloc(sizeof(struct setphy_parm));
+
+	if (psetphypara == NULL) {
+		rtw_mfree((u8 *) ph2c, sizeof(struct	cmd_obj));
+		res = _FAIL;
+		goto exit;
+	}
+
+	init_h2fwcmd_w_parm_no_rsp(ph2c, psetphypara, _SetPhy_CMD_);
+
+
+	psetphypara->modem = modem;
+	psetphypara->rfchannel = ch;
+
+	res = rtw_enqueue_cmd(pcmdpriv, ph2c);
+exit:
+	return res;
+}
+
+u8 rtw_getmacreg_cmd(_adapter *padapter, u8 len, u32 addr)
+{
+	struct cmd_obj *ph2c;
+	struct readMAC_parm *preadmacparm;
+	struct cmd_priv *pcmdpriv = &padapter->cmdpriv;
+	u8	res = _SUCCESS;
+
+	ph2c = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj));
+	if (ph2c == NULL) {
+		res = _FAIL;
+		goto exit;
+	}
+	preadmacparm = (struct readMAC_parm *)rtw_zmalloc(sizeof(struct readMAC_parm));
+
+	if (preadmacparm == NULL) {
+		rtw_mfree((u8 *) ph2c, sizeof(struct	cmd_obj));
+		res = _FAIL;
+		goto exit;
+	}
+
+	init_h2fwcmd_w_parm_no_rsp(ph2c, preadmacparm, GEN_CMD_CODE(_GetMACReg));
+
+	preadmacparm->len = len;
+	preadmacparm->addr = addr;
+
+	res = rtw_enqueue_cmd(pcmdpriv, ph2c);
+
+exit:
+	return res;
+}
+
+void rtw_usb_catc_trigger_cmd(_adapter *padapter, const char *caller)
+{
+	RTW_INFO("%s caller:%s\n", __func__, caller);
+	rtw_getmacreg_cmd(padapter, 1, 0x1c4);
+}
+
+u8 rtw_setbbreg_cmd(_adapter *padapter, u8 offset, u8 val)
+{
+	struct cmd_obj			*ph2c;
+	struct writeBB_parm		*pwritebbparm;
+	struct cmd_priv			*pcmdpriv = &padapter->cmdpriv;
+	u8	res = _SUCCESS;
+	ph2c = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj));
+	if (ph2c == NULL) {
+		res = _FAIL;
+		goto exit;
+	}
+	pwritebbparm = (struct writeBB_parm *)rtw_zmalloc(sizeof(struct writeBB_parm));
+
+	if (pwritebbparm == NULL) {
+		rtw_mfree((u8 *) ph2c, sizeof(struct	cmd_obj));
+		res = _FAIL;
+		goto exit;
+	}
+
+	init_h2fwcmd_w_parm_no_rsp(ph2c, pwritebbparm, GEN_CMD_CODE(_SetBBReg));
+
+	pwritebbparm->offset = offset;
+	pwritebbparm->value = val;
+
+	res = rtw_enqueue_cmd(pcmdpriv, ph2c);
+exit:
+	return res;
+}
+
+u8 rtw_getbbreg_cmd(_adapter  *padapter, u8 offset, u8 *pval)
+{
+	struct cmd_obj			*ph2c;
+	struct readBB_parm		*prdbbparm;
+	struct cmd_priv			*pcmdpriv = &padapter->cmdpriv;
+	u8	res = _SUCCESS;
+
+	ph2c = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj));
+	if (ph2c == NULL) {
+		res = _FAIL;
+		goto exit;
+	}
+	prdbbparm = (struct readBB_parm *)rtw_zmalloc(sizeof(struct readBB_parm));
+
+	if (prdbbparm == NULL) {
+		rtw_mfree((unsigned char *) ph2c, sizeof(struct	cmd_obj));
+		return _FAIL;
+	}
+
+	_rtw_init_listhead(&ph2c->list);
+	ph2c->cmdcode = GEN_CMD_CODE(_GetBBReg);
+	ph2c->parmbuf = (unsigned char *)prdbbparm;
+	ph2c->cmdsz =  sizeof(struct readBB_parm);
+	ph2c->rsp = pval;
+	ph2c->rspsz = sizeof(struct readBB_rsp);
+
+	prdbbparm->offset = offset;
+
+	res = rtw_enqueue_cmd(pcmdpriv, ph2c);
+exit:
+	return res;
+}
+
+u8 rtw_setrfreg_cmd(_adapter  *padapter, u8 offset, u32 val)
+{
+	struct cmd_obj			*ph2c;
+	struct writeRF_parm		*pwriterfparm;
+	struct cmd_priv			*pcmdpriv = &padapter->cmdpriv;
+	u8	res = _SUCCESS;
+	ph2c = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj));
+	if (ph2c == NULL) {
+		res = _FAIL;
+		goto exit;
+	}
+	pwriterfparm = (struct writeRF_parm *)rtw_zmalloc(sizeof(struct writeRF_parm));
+
+	if (pwriterfparm == NULL) {
+		rtw_mfree((u8 *) ph2c, sizeof(struct	cmd_obj));
+		res = _FAIL;
+		goto exit;
+	}
+
+	init_h2fwcmd_w_parm_no_rsp(ph2c, pwriterfparm, GEN_CMD_CODE(_SetRFReg));
+
+	pwriterfparm->offset = offset;
+	pwriterfparm->value = val;
+
+	res = rtw_enqueue_cmd(pcmdpriv, ph2c);
+exit:
+	return res;
+}
+
+u8 rtw_getrfreg_cmd(_adapter  *padapter, u8 offset, u8 *pval)
+{
+	struct cmd_obj			*ph2c;
+	struct readRF_parm		*prdrfparm;
+	struct cmd_priv			*pcmdpriv = &padapter->cmdpriv;
+	u8	res = _SUCCESS;
+
+
+	ph2c = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj));
+	if (ph2c == NULL) {
+		res = _FAIL;
+		goto exit;
+	}
+
+	prdrfparm = (struct readRF_parm *)rtw_zmalloc(sizeof(struct readRF_parm));
+	if (prdrfparm == NULL) {
+		rtw_mfree((u8 *) ph2c, sizeof(struct	cmd_obj));
+		res = _FAIL;
+		goto exit;
+	}
+
+	_rtw_init_listhead(&ph2c->list);
+	ph2c->cmdcode = GEN_CMD_CODE(_GetRFReg);
+	ph2c->parmbuf = (unsigned char *)prdrfparm;
+	ph2c->cmdsz =  sizeof(struct readRF_parm);
+	ph2c->rsp = pval;
+	ph2c->rspsz = sizeof(struct readRF_rsp);
+
+	prdrfparm->offset = offset;
+
+	res = rtw_enqueue_cmd(pcmdpriv, ph2c);
+
+exit:
+
+
+	return res;
+}
+
+void rtw_getbbrfreg_cmdrsp_callback(_adapter	*padapter,  struct cmd_obj *pcmd)
+{
+
+	/* rtw_free_cmd_obj(pcmd); */
+	rtw_mfree((unsigned char *) pcmd->parmbuf, pcmd->cmdsz);
+	rtw_mfree((unsigned char *) pcmd, sizeof(struct cmd_obj));
+
+#ifdef CONFIG_MP_INCLUDED
+	if (padapter->registrypriv.mp_mode == 1)
+		padapter->mppriv.workparam.bcompleted = _TRUE;
+#endif
+}
+
+void rtw_readtssi_cmdrsp_callback(_adapter	*padapter,  struct cmd_obj *pcmd)
+{
+
+	rtw_mfree((unsigned char *) pcmd->parmbuf, pcmd->cmdsz);
+	rtw_mfree((unsigned char *) pcmd, sizeof(struct cmd_obj));
+
+#ifdef CONFIG_MP_INCLUDED
+	if (padapter->registrypriv.mp_mode == 1)
+		padapter->mppriv.workparam.bcompleted = _TRUE;
+#endif
+
+}
+
+static u8 rtw_createbss_cmd(_adapter  *adapter, int flags, bool adhoc
+	, u8 ifbmp, u8 excl_ifbmp, s16 req_ch, s8 req_bw, s8 req_offset)
+{
+	struct cmd_obj *cmdobj;
+	struct createbss_parm *parm;
+	struct cmd_priv *pcmdpriv = &adapter->cmdpriv;
+	struct submit_ctx sctx;
+	u8 res = _SUCCESS;
+
+	if (req_ch > 0 && req_bw >= 0 && req_offset >= 0) {
+		if (!rtw_chset_is_chbw_valid(adapter_to_chset(adapter), req_ch, req_bw, req_offset)) {
+			res = _FAIL;
+			goto exit;
+		}
+	}
+
+	/* prepare cmd parameter */
+	parm = (struct createbss_parm *)rtw_zmalloc(sizeof(*parm));
+	if (parm == NULL) {
+		res = _FAIL;
+		goto exit;
+	}
+
+	if (adhoc) {
+		/* for now, adhoc doesn't support ch,bw,offset request */
+		parm->adhoc = 1;
+	} else {
+		parm->adhoc = 0;
+		parm->ifbmp = ifbmp;
+		parm->excl_ifbmp = excl_ifbmp;
+		parm->req_ch = req_ch;
+		parm->req_bw = req_bw;
+		parm->req_offset = req_offset;
+	}
+
+	if (flags & RTW_CMDF_DIRECTLY) {
+		/* no need to enqueue, do the cmd hdl directly and free cmd parameter */
+		if (H2C_SUCCESS != createbss_hdl(adapter, (u8 *)parm))
+			res = _FAIL;
+		rtw_mfree((u8 *)parm, sizeof(*parm));
+	} else {
+		/* need enqueue, prepare cmd_obj and enqueue */
+		cmdobj = (struct cmd_obj *)rtw_zmalloc(sizeof(*cmdobj));
+		if (cmdobj == NULL) {
+			res = _FAIL;
+			rtw_mfree((u8 *)parm, sizeof(*parm));
+			goto exit;
+		}
+
+		init_h2fwcmd_w_parm_no_rsp(cmdobj, parm, GEN_CMD_CODE(_CreateBss));
+
+		if (flags & RTW_CMDF_WAIT_ACK) {
+			cmdobj->sctx = &sctx;
+			rtw_sctx_init(&sctx, 2000);
+		}
+
+		res = rtw_enqueue_cmd(pcmdpriv, cmdobj);
+
+		if (res == _SUCCESS && (flags & RTW_CMDF_WAIT_ACK)) {
+			rtw_sctx_wait(&sctx, __func__);
+			_enter_critical_mutex(&pcmdpriv->sctx_mutex, NULL);
+			if (sctx.status == RTW_SCTX_SUBMITTED)
+				cmdobj->sctx = NULL;
+			_exit_critical_mutex(&pcmdpriv->sctx_mutex, NULL);
+		}
+	}
+
+exit:
+	return res;
+}
+
+inline u8 rtw_create_ibss_cmd(_adapter *adapter, int flags)
+{
+	return rtw_createbss_cmd(adapter, flags
+		, 1
+		, 0, 0
+		, 0, REQ_BW_NONE, REQ_OFFSET_NONE /* for now, adhoc doesn't support ch,bw,offset request */
+	);
+}
+
+inline u8 rtw_startbss_cmd(_adapter *adapter, int flags)
+{
+	return rtw_createbss_cmd(adapter, flags
+		, 0
+		, BIT(adapter->iface_id), 0
+		, 0, REQ_BW_NONE, REQ_OFFSET_NONE /* excute entire AP setup cmd */
+	);
+}
+
+inline u8 rtw_change_bss_chbw_cmd(_adapter *adapter, int flags
+	, u8 ifbmp, u8 excl_ifbmp, s16 req_ch, s8 req_bw, s8 req_offset)
+{
+	return rtw_createbss_cmd(adapter, flags
+		, 0
+		, ifbmp, excl_ifbmp
+		, req_ch, req_bw, req_offset
+	);
+}
+
+#ifdef CONFIG_RTW_80211R
+static void rtw_ft_validate_akm_type(_adapter  *padapter,
+	struct wlan_network *pnetwork)
+{
+	struct security_priv *psecuritypriv = &(padapter->securitypriv);
+	struct ft_roam_info *pft_roam = &(padapter->mlmepriv.ft_roam);
+	u32 tmp_len;
+	u8 *ptmp;
+
+	/*IEEE802.11-2012 Std. Table 8-101-AKM suite selectors*/
+	if (rtw_ft_valid_akm(padapter, psecuritypriv->rsn_akm_suite_type)) {
+		ptmp = rtw_get_ie(&pnetwork->network.IEs[12], 
+				_MDIE_, &tmp_len, (pnetwork->network.IELength-12));
+		if (ptmp) {
+			pft_roam->mdid = *(u16 *)(ptmp+2);
+			pft_roam->ft_cap = *(ptmp+4);
+
+			RTW_INFO("FT: target " MAC_FMT " mdid=(0x%2x), capacity=(0x%2x)\n", 
+				MAC_ARG(pnetwork->network.MacAddress), pft_roam->mdid, pft_roam->ft_cap);
+			rtw_ft_set_flags(padapter, RTW_FT_PEER_EN);
+
+			if (rtw_ft_otd_roam_en(padapter))
+				rtw_ft_set_flags(padapter, RTW_FT_PEER_OTD_EN);
+		} else {
+			/* Don't use FT roaming if target AP cannot support FT */
+			rtw_ft_clr_flags(padapter, (RTW_FT_PEER_EN|RTW_FT_PEER_OTD_EN));
+			rtw_ft_reset_status(padapter);
+		}
+	} else {
+		/* It could be a non-FT connection */
+		rtw_ft_clr_flags(padapter, (RTW_FT_PEER_EN|RTW_FT_PEER_OTD_EN));
+		rtw_ft_reset_status(padapter);
+	}	
+}
+#endif
+
+u8 rtw_joinbss_cmd(_adapter  *padapter, struct wlan_network *pnetwork)
+{
+	u8	*auth, res = _SUCCESS;
+	uint	t_len = 0;
+	WLAN_BSSID_EX		*psecnetwork;
+	struct cmd_obj		*pcmd;
+	struct cmd_priv		*pcmdpriv = &padapter->cmdpriv;
+	struct mlme_priv		*pmlmepriv = &padapter->mlmepriv;
+	struct qos_priv		*pqospriv = &pmlmepriv->qospriv;
+	struct security_priv	*psecuritypriv = &padapter->securitypriv;
+	struct registry_priv	*pregistrypriv = &padapter->registrypriv;
+#ifdef CONFIG_80211N_HT
+	struct ht_priv			*phtpriv = &pmlmepriv->htpriv;
+#endif /* CONFIG_80211N_HT */
+#ifdef CONFIG_80211AC_VHT
+	struct vht_priv		*pvhtpriv = &pmlmepriv->vhtpriv;
+#endif /* CONFIG_80211AC_VHT */
+	NDIS_802_11_NETWORK_INFRASTRUCTURE ndis_network_mode = pnetwork->network.InfrastructureMode;
+	struct mlme_ext_priv	*pmlmeext = &padapter->mlmeextpriv;
+	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
+	struct rf_ctl_t *rfctl = adapter_to_rfctl(padapter);
+	u32 tmp_len;
+	u8 *ptmp = NULL;
+
+	rtw_led_control(padapter, LED_CTL_START_TO_LINK);
+
+	pcmd = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj));
+	if (pcmd == NULL) {
+		res = _FAIL;
+		goto exit;
+	}
+#if 0
+	/*  for IEs is pointer */
+	t_len = sizeof(ULONG) + sizeof(NDIS_802_11_MAC_ADDRESS) + 2 +
+		sizeof(NDIS_802_11_SSID) + sizeof(ULONG) +
+		sizeof(NDIS_802_11_RSSI) + sizeof(NDIS_802_11_NETWORK_TYPE) +
+		sizeof(NDIS_802_11_CONFIGURATION) +
+		sizeof(NDIS_802_11_NETWORK_INFRASTRUCTURE) +
+		sizeof(NDIS_802_11_RATES_EX) + sizeof(WLAN_PHY_INFO) + sizeof(ULONG) + MAX_IE_SZ;
+#endif
+	/* for IEs is fix buf size */
+	t_len = sizeof(WLAN_BSSID_EX);
+
+
+	/* for hidden ap to set fw_state here */
+	if (check_fwstate(pmlmepriv, WIFI_STATION_STATE | WIFI_ADHOC_STATE) != _TRUE) {
+		switch (ndis_network_mode) {
+		case Ndis802_11IBSS:
+			set_fwstate(pmlmepriv, WIFI_ADHOC_STATE);
+			break;
+
+		case Ndis802_11Infrastructure:
+			set_fwstate(pmlmepriv, WIFI_STATION_STATE);
+			break;
+
+		default:
+			rtw_warn_on(1);
+			break;
+		}
+	}
+
+	pmlmeinfo->assoc_AP_vendor = check_assoc_AP(pnetwork->network.IEs, pnetwork->network.IELength);
+
+#ifdef CONFIG_80211AC_VHT
+	/* save AP beamform_cap info for BCM IOT issue */
+	if (pmlmeinfo->assoc_AP_vendor == HT_IOT_PEER_BROADCOM)
+		pvhtpriv->ap_is_mu_bfer =
+			get_vht_mu_bfer_cap(pnetwork->network.IEs,
+				pnetwork->network.IELength);
+#endif
+	/*
+		Modified by Arvin 2015/05/13
+		Solution for allocating a new WLAN_BSSID_EX to avoid race condition issue between disconnect and joinbss
+	*/
+	psecnetwork = (WLAN_BSSID_EX *)rtw_zmalloc(sizeof(WLAN_BSSID_EX));
+	if (psecnetwork == NULL) {
+		if (pcmd != NULL)
+			rtw_mfree((unsigned char *)pcmd, sizeof(struct	cmd_obj));
+
+		res = _FAIL;
+
+
+		goto exit;
+	}
+
+	_rtw_memset(psecnetwork, 0, t_len);
+
+	_rtw_memcpy(psecnetwork, &pnetwork->network, get_WLAN_BSSID_EX_sz(&pnetwork->network));
+
+	auth = &psecuritypriv->authenticator_ie[0];
+	psecuritypriv->authenticator_ie[0] = (unsigned char)psecnetwork->IELength;
+
+	if ((psecnetwork->IELength - 12) < (256 - 1))
+		_rtw_memcpy(&psecuritypriv->authenticator_ie[1], &psecnetwork->IEs[12], psecnetwork->IELength - 12);
+	else
+		_rtw_memcpy(&psecuritypriv->authenticator_ie[1], &psecnetwork->IEs[12], (256 - 1));
+
+	psecnetwork->IELength = 0;
+	/* Added by Albert 2009/02/18 */
+	/* If the the driver wants to use the bssid to create the connection. */
+	/* If not,  we have to copy the connecting AP's MAC address to it so that */
+	/* the driver just has the bssid information for PMKIDList searching. */
+
+	if (pmlmepriv->assoc_by_bssid == _FALSE)
+		_rtw_memcpy(&pmlmepriv->assoc_bssid[0], &pnetwork->network.MacAddress[0], ETH_ALEN);
+
+	/* copy fixed ie */
+	_rtw_memcpy(psecnetwork->IEs, pnetwork->network.IEs, 12);
+	psecnetwork->IELength = 12;
+
+	psecnetwork->IELength += rtw_restruct_sec_ie(padapter, psecnetwork->IEs + psecnetwork->IELength);
+
+
+	pqospriv->qos_option = 0;
+
+	if (pregistrypriv->wmm_enable) {
+#ifdef CONFIG_WMMPS_STA	
+		rtw_uapsd_use_default_setting(padapter);
+#endif /* CONFIG_WMMPS_STA */		
+		tmp_len = rtw_restruct_wmm_ie(padapter, &pnetwork->network.IEs[0], &psecnetwork->IEs[0], pnetwork->network.IELength, psecnetwork->IELength);
+
+		if (psecnetwork->IELength != tmp_len) {
+			psecnetwork->IELength = tmp_len;
+			pqospriv->qos_option = 1; /* There is WMM IE in this corresp. beacon */
+		} else {
+			pqospriv->qos_option = 0;/* There is no WMM IE in this corresp. beacon */
+		}
+	}
+
+#ifdef CONFIG_80211N_HT
+	phtpriv->ht_option = _FALSE;
+	if (pregistrypriv->ht_enable && is_supported_ht(pregistrypriv->wireless_mode)) {
+		ptmp = rtw_get_ie(&pnetwork->network.IEs[12], _HT_CAPABILITY_IE_, &tmp_len, pnetwork->network.IELength - 12);
+		if (ptmp && tmp_len > 0) {
+			/*	Added by Albert 2010/06/23 */
+			/*	For the WEP mode, we will use the bg mode to do the connection to avoid some IOT issue. */
+			/*	Especially for Realtek 8192u SoftAP. */
+			if ((padapter->securitypriv.dot11PrivacyAlgrthm != _WEP40_) &&
+			    (padapter->securitypriv.dot11PrivacyAlgrthm != _WEP104_) &&
+			    (padapter->securitypriv.dot11PrivacyAlgrthm != _TKIP_)) {
+				rtw_ht_use_default_setting(padapter);
+
+				/* rtw_restructure_ht_ie */
+				rtw_restructure_ht_ie(padapter, &pnetwork->network.IEs[12], &psecnetwork->IEs[0],
+					pnetwork->network.IELength - 12, &psecnetwork->IELength,
+					pnetwork->network.Configuration.DSConfig);
+			}
+		}
+	}
+
+#ifdef CONFIG_80211AC_VHT
+	pvhtpriv->vht_option = _FALSE;
+	if (phtpriv->ht_option
+		&& REGSTY_IS_11AC_ENABLE(pregistrypriv)
+		&& is_supported_vht(pregistrypriv->wireless_mode)
+		&& (!rfctl->country_ent || COUNTRY_CHPLAN_EN_11AC(rfctl->country_ent))
+	) {
+		rtw_restructure_vht_ie(padapter, &pnetwork->network.IEs[0], &psecnetwork->IEs[0],
+			pnetwork->network.IELength, &psecnetwork->IELength);
+	}
+#endif
+#endif /* CONFIG_80211N_HT */
+
+	rtw_append_exented_cap(padapter, &psecnetwork->IEs[0], &psecnetwork->IELength);
+
+#ifdef CONFIG_RTW_80211R
+	rtw_ft_validate_akm_type(padapter, pnetwork);
+#endif
+
+#if 0
+	psecuritypriv->supplicant_ie[0] = (u8)psecnetwork->IELength;
+
+	if (psecnetwork->IELength < (256 - 1))
+		_rtw_memcpy(&psecuritypriv->supplicant_ie[1], &psecnetwork->IEs[0], psecnetwork->IELength);
+	else
+		_rtw_memcpy(&psecuritypriv->supplicant_ie[1], &psecnetwork->IEs[0], (256 - 1));
+#endif
+
+	pcmd->cmdsz = sizeof(WLAN_BSSID_EX);
+
+#ifdef CONFIG_RTL8712
+	/* wlan_network endian conversion	 */
+	psecnetwork->Length = cpu_to_le32(psecnetwork->Length);
+	psecnetwork->Ssid.SsidLength = cpu_to_le32(psecnetwork->Ssid.SsidLength);
+	psecnetwork->Privacy = cpu_to_le32(psecnetwork->Privacy);
+	psecnetwork->Rssi = cpu_to_le32(psecnetwork->Rssi);
+	psecnetwork->NetworkTypeInUse = cpu_to_le32(psecnetwork->NetworkTypeInUse);
+	psecnetwork->Configuration.ATIMWindow = cpu_to_le32(psecnetwork->Configuration.ATIMWindow);
+	psecnetwork->Configuration.BeaconPeriod = cpu_to_le32(psecnetwork->Configuration.BeaconPeriod);
+	psecnetwork->Configuration.DSConfig = cpu_to_le32(psecnetwork->Configuration.DSConfig);
+	psecnetwork->Configuration.FHConfig.DwellTime = cpu_to_le32(psecnetwork->Configuration.FHConfig.DwellTime);
+	psecnetwork->Configuration.FHConfig.HopPattern = cpu_to_le32(psecnetwork->Configuration.FHConfig.HopPattern);
+	psecnetwork->Configuration.FHConfig.HopSet = cpu_to_le32(psecnetwork->Configuration.FHConfig.HopSet);
+	psecnetwork->Configuration.FHConfig.Length = cpu_to_le32(psecnetwork->Configuration.FHConfig.Length);
+	psecnetwork->Configuration.Length = cpu_to_le32(psecnetwork->Configuration.Length);
+	psecnetwork->InfrastructureMode = cpu_to_le32(psecnetwork->InfrastructureMode);
+	psecnetwork->IELength = cpu_to_le32(psecnetwork->IELength);
+#endif
+
+	_rtw_init_listhead(&pcmd->list);
+	pcmd->cmdcode = _JoinBss_CMD_;/* GEN_CMD_CODE(_JoinBss) */
+	pcmd->parmbuf = (unsigned char *)psecnetwork;
+	pcmd->rsp = NULL;
+	pcmd->rspsz = 0;
+
+	res = rtw_enqueue_cmd(pcmdpriv, pcmd);
+
+exit:
+
+
+	return res;
+}
+
+u8 rtw_disassoc_cmd(_adapter *padapter, u32 deauth_timeout_ms, int flags) /* for sta_mode */
+{
+	struct cmd_obj *cmdobj = NULL;
+	struct disconnect_parm *param = NULL;
+	struct cmd_priv *cmdpriv = &padapter->cmdpriv;
+	struct cmd_priv *pcmdpriv = &padapter->cmdpriv;
+	struct submit_ctx sctx;
+	u8 res = _SUCCESS;
+
+	/* prepare cmd parameter */
+	param = (struct disconnect_parm *)rtw_zmalloc(sizeof(*param));
+	if (param == NULL) {
+		res = _FAIL;
+		goto exit;
+	}
+	param->deauth_timeout_ms = deauth_timeout_ms;
+
+	if (flags & RTW_CMDF_DIRECTLY) {
+		/* no need to enqueue, do the cmd hdl directly and free cmd parameter */
+		if (disconnect_hdl(padapter, (u8 *)param) != H2C_SUCCESS)
+			res = _FAIL;
+		rtw_mfree((u8 *)param, sizeof(*param));
+
+	} else {
+		cmdobj = (struct cmd_obj *)rtw_zmalloc(sizeof(*cmdobj));
+		if (cmdobj == NULL) {
+			res = _FAIL;
+			rtw_mfree((u8 *)param, sizeof(*param));
+			goto exit;
+		}
+		init_h2fwcmd_w_parm_no_rsp(cmdobj, param, _DisConnect_CMD_);
+		if (flags & RTW_CMDF_WAIT_ACK) {
+			cmdobj->sctx = &sctx;
+			rtw_sctx_init(&sctx, 2000);
+		}
+		res = rtw_enqueue_cmd(cmdpriv, cmdobj);
+		if (res == _SUCCESS && (flags & RTW_CMDF_WAIT_ACK)) {
+			rtw_sctx_wait(&sctx, __func__);
+			_enter_critical_mutex(&pcmdpriv->sctx_mutex, NULL);
+			if (sctx.status == RTW_SCTX_SUBMITTED)
+				cmdobj->sctx = NULL;
+			_exit_critical_mutex(&pcmdpriv->sctx_mutex, NULL);
+		}
+	}
+
+exit:
+
+
+	return res;
+}
+
+u8 rtw_setopmode_cmd(_adapter  *adapter, NDIS_802_11_NETWORK_INFRASTRUCTURE networktype, u8 flags)
+{
+	struct cmd_obj *cmdobj;
+	struct setopmode_parm *parm;
+	struct cmd_priv *pcmdpriv = &adapter->cmdpriv;
+	struct submit_ctx sctx;
+	u8 res = _SUCCESS;
+
+	/* prepare cmd parameter */
+	parm = (struct setopmode_parm *)rtw_zmalloc(sizeof(*parm));
+	if (parm == NULL) {
+		res = _FAIL;
+		goto exit;
+	}
+	parm->mode = (u8)networktype;
+
+	if (flags & RTW_CMDF_DIRECTLY) {
+		/* no need to enqueue, do the cmd hdl directly and free cmd parameter */
+		if (H2C_SUCCESS != setopmode_hdl(adapter, (u8 *)parm))
+			res = _FAIL;
+		rtw_mfree((u8 *)parm, sizeof(*parm));
+	} else {
+		/* need enqueue, prepare cmd_obj and enqueue */
+		cmdobj = (struct cmd_obj *)rtw_zmalloc(sizeof(*cmdobj));
+		if (cmdobj == NULL) {
+			res = _FAIL;
+			rtw_mfree((u8 *)parm, sizeof(*parm));
+			goto exit;
+		}
+
+		init_h2fwcmd_w_parm_no_rsp(cmdobj, parm, _SetOpMode_CMD_);
+
+		if (flags & RTW_CMDF_WAIT_ACK) {
+			cmdobj->sctx = &sctx;
+			rtw_sctx_init(&sctx, 2000);
+		}
+
+		res = rtw_enqueue_cmd(pcmdpriv, cmdobj);
+
+		if (res == _SUCCESS && (flags & RTW_CMDF_WAIT_ACK)) {
+			rtw_sctx_wait(&sctx, __func__);
+			_enter_critical_mutex(&pcmdpriv->sctx_mutex, NULL);
+			if (sctx.status == RTW_SCTX_SUBMITTED)
+				cmdobj->sctx = NULL;
+			_exit_critical_mutex(&pcmdpriv->sctx_mutex, NULL);
+		}
+	}
+
+exit:
+	return res;
+}
+
+u8 rtw_setstakey_cmd(_adapter *padapter, struct sta_info *sta, u8 key_type, bool enqueue)
+{
+	struct cmd_obj			*ph2c;
+	struct set_stakey_parm	*psetstakey_para;
+	struct cmd_priv			*pcmdpriv = &padapter->cmdpriv;
+	struct set_stakey_rsp		*psetstakey_rsp = NULL;
+
+	struct mlme_priv			*pmlmepriv = &padapter->mlmepriv;
+	struct security_priv		*psecuritypriv = &padapter->securitypriv;
+	u8	res = _SUCCESS;
+
+
+	psetstakey_para = (struct set_stakey_parm *)rtw_zmalloc(sizeof(struct set_stakey_parm));
+	if (psetstakey_para == NULL) {
+		res = _FAIL;
+		goto exit;
+	}
+
+	_rtw_memcpy(psetstakey_para->addr, sta->cmn.mac_addr, ETH_ALEN);
+
+	if (check_fwstate(pmlmepriv, WIFI_STATION_STATE))
+		psetstakey_para->algorithm = (unsigned char) psecuritypriv->dot11PrivacyAlgrthm;
+	else
+		GET_ENCRY_ALGO(psecuritypriv, sta, psetstakey_para->algorithm, _FALSE);
+
+	if (key_type == GROUP_KEY) {
+		_rtw_memcpy(&psetstakey_para->key, &psecuritypriv->dot118021XGrpKey[psecuritypriv->dot118021XGrpKeyid].skey, 16);
+		psetstakey_para->gk = 1;
+	} else if (key_type == UNICAST_KEY)
+		_rtw_memcpy(&psetstakey_para->key, &sta->dot118021x_UncstKey, 16);
+#ifdef CONFIG_TDLS
+	else if (key_type == TDLS_KEY) {
+		_rtw_memcpy(&psetstakey_para->key, sta->tpk.tk, 16);
+		psetstakey_para->algorithm = (u8)sta->dot118021XPrivacy;
+	}
+#endif /* CONFIG_TDLS */
+
+	/* jeff: set this becasue at least sw key is ready */
+	padapter->securitypriv.busetkipkey = _TRUE;
+
+	if (enqueue) {
+		ph2c = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj));
+		if (ph2c == NULL) {
+			rtw_mfree((u8 *) psetstakey_para, sizeof(struct set_stakey_parm));
+			res = _FAIL;
+			goto exit;
+		}
+
+		psetstakey_rsp = (struct set_stakey_rsp *)rtw_zmalloc(sizeof(struct set_stakey_rsp));
+		if (psetstakey_rsp == NULL) {
+			rtw_mfree((u8 *) ph2c, sizeof(struct cmd_obj));
+			rtw_mfree((u8 *) psetstakey_para, sizeof(struct set_stakey_parm));
+			res = _FAIL;
+			goto exit;
+		}
+
+		init_h2fwcmd_w_parm_no_rsp(ph2c, psetstakey_para, _SetStaKey_CMD_);
+		ph2c->rsp = (u8 *) psetstakey_rsp;
+		ph2c->rspsz = sizeof(struct set_stakey_rsp);
+		res = rtw_enqueue_cmd(pcmdpriv, ph2c);
+	} else {
+		set_stakey_hdl(padapter, (u8 *)psetstakey_para);
+		rtw_mfree((u8 *) psetstakey_para, sizeof(struct set_stakey_parm));
+	}
+exit:
+
+
+	return res;
+}
+
+u8 rtw_clearstakey_cmd(_adapter *padapter, struct sta_info *sta, u8 enqueue)
+{
+	struct cmd_obj			*ph2c;
+	struct set_stakey_parm	*psetstakey_para;
+	struct cmd_priv			*pcmdpriv = &padapter->cmdpriv;
+	struct set_stakey_rsp		*psetstakey_rsp = NULL;
+	s16 cam_id = 0;
+	u8	res = _SUCCESS;
+
+	if (!sta) {
+		RTW_ERR("%s sta == NULL\n", __func__);
+		goto exit;
+	}
+
+	if (!enqueue) {
+		while ((cam_id = rtw_camid_search(padapter, sta->cmn.mac_addr, -1, -1)) >= 0) {
+			RTW_PRINT("clear key for addr:"MAC_FMT", camid:%d\n", MAC_ARG(sta->cmn.mac_addr), cam_id);
+			clear_cam_entry(padapter, cam_id);
+			rtw_camid_free(padapter, cam_id);
+		}
+	} else {
+		ph2c = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj));
+		if (ph2c == NULL) {
+			res = _FAIL;
+			goto exit;
+		}
+
+		psetstakey_para = (struct set_stakey_parm *)rtw_zmalloc(sizeof(struct set_stakey_parm));
+		if (psetstakey_para == NULL) {
+			rtw_mfree((u8 *) ph2c, sizeof(struct	cmd_obj));
+			res = _FAIL;
+			goto exit;
+		}
+
+		psetstakey_rsp = (struct set_stakey_rsp *)rtw_zmalloc(sizeof(struct set_stakey_rsp));
+		if (psetstakey_rsp == NULL) {
+			rtw_mfree((u8 *) ph2c, sizeof(struct	cmd_obj));
+			rtw_mfree((u8 *) psetstakey_para, sizeof(struct set_stakey_parm));
+			res = _FAIL;
+			goto exit;
+		}
+
+		init_h2fwcmd_w_parm_no_rsp(ph2c, psetstakey_para, _SetStaKey_CMD_);
+		ph2c->rsp = (u8 *) psetstakey_rsp;
+		ph2c->rspsz = sizeof(struct set_stakey_rsp);
+
+		_rtw_memcpy(psetstakey_para->addr, sta->cmn.mac_addr, ETH_ALEN);
+
+		psetstakey_para->algorithm = _NO_PRIVACY_;
+
+		res = rtw_enqueue_cmd(pcmdpriv, ph2c);
+
+	}
+
+exit:
+
+
+	return res;
+}
+
+u8 rtw_setrttbl_cmd(_adapter  *padapter, struct setratable_parm *prate_table)
+{
+	struct cmd_obj			*ph2c;
+	struct setratable_parm	*psetrttblparm;
+	struct cmd_priv			*pcmdpriv = &padapter->cmdpriv;
+	u8	res = _SUCCESS;
+
+	ph2c = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj));
+	if (ph2c == NULL) {
+		res = _FAIL;
+		goto exit;
+	}
+	psetrttblparm = (struct setratable_parm *)rtw_zmalloc(sizeof(struct setratable_parm));
+
+	if (psetrttblparm == NULL) {
+		rtw_mfree((unsigned char *) ph2c, sizeof(struct	cmd_obj));
+		res = _FAIL;
+		goto exit;
+	}
+
+	init_h2fwcmd_w_parm_no_rsp(ph2c, psetrttblparm, GEN_CMD_CODE(_SetRaTable));
+
+	_rtw_memcpy(psetrttblparm, prate_table, sizeof(struct setratable_parm));
+
+	res = rtw_enqueue_cmd(pcmdpriv, ph2c);
+exit:
+	return res;
+
+}
+
+u8 rtw_getrttbl_cmd(_adapter  *padapter, struct getratable_rsp *pval)
+{
+	struct cmd_obj			*ph2c;
+	struct getratable_parm	*pgetrttblparm;
+	struct cmd_priv			*pcmdpriv = &padapter->cmdpriv;
+	u8	res = _SUCCESS;
+
+	ph2c = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj));
+	if (ph2c == NULL) {
+		res = _FAIL;
+		goto exit;
+	}
+	pgetrttblparm = (struct getratable_parm *)rtw_zmalloc(sizeof(struct getratable_parm));
+
+	if (pgetrttblparm == NULL) {
+		rtw_mfree((unsigned char *) ph2c, sizeof(struct	cmd_obj));
+		res = _FAIL;
+		goto exit;
+	}
+
+	/*	init_h2fwcmd_w_parm_no_rsp(ph2c, psetrttblparm, GEN_CMD_CODE(_SetRaTable)); */
+
+	_rtw_init_listhead(&ph2c->list);
+	ph2c->cmdcode = GEN_CMD_CODE(_GetRaTable);
+	ph2c->parmbuf = (unsigned char *)pgetrttblparm;
+	ph2c->cmdsz =  sizeof(struct getratable_parm);
+	ph2c->rsp = (u8 *)pval;
+	ph2c->rspsz = sizeof(struct getratable_rsp);
+
+	pgetrttblparm->rsvd = 0x0;
+
+	res = rtw_enqueue_cmd(pcmdpriv, ph2c);
+exit:
+	return res;
+
+}
+
+u8 rtw_setassocsta_cmd(_adapter  *padapter, u8 *mac_addr)
+{
+	struct cmd_priv		*pcmdpriv = &padapter->cmdpriv;
+	struct cmd_obj			*ph2c;
+	struct set_assocsta_parm	*psetassocsta_para;
+	struct set_stakey_rsp		*psetassocsta_rsp = NULL;
+
+	u8	res = _SUCCESS;
+
+
+	ph2c = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj));
+	if (ph2c == NULL) {
+		res = _FAIL;
+		goto exit;
+	}
+
+	psetassocsta_para = (struct set_assocsta_parm *)rtw_zmalloc(sizeof(struct set_assocsta_parm));
+	if (psetassocsta_para == NULL) {
+		rtw_mfree((u8 *) ph2c, sizeof(struct	cmd_obj));
+		res = _FAIL;
+		goto exit;
+	}
+
+	psetassocsta_rsp = (struct set_stakey_rsp *)rtw_zmalloc(sizeof(struct set_assocsta_rsp));
+	if (psetassocsta_rsp == NULL) {
+		rtw_mfree((u8 *) ph2c, sizeof(struct	cmd_obj));
+		rtw_mfree((u8 *) psetassocsta_para, sizeof(struct set_assocsta_parm));
+		return _FAIL;
+	}
+
+	init_h2fwcmd_w_parm_no_rsp(ph2c, psetassocsta_para, _SetAssocSta_CMD_);
+	ph2c->rsp = (u8 *) psetassocsta_rsp;
+	ph2c->rspsz = sizeof(struct set_assocsta_rsp);
+
+	_rtw_memcpy(psetassocsta_para->addr, mac_addr, ETH_ALEN);
+
+	res = rtw_enqueue_cmd(pcmdpriv, ph2c);
+
+exit:
+
+
+	return res;
+}
+
+u8 rtw_addbareq_cmd(_adapter *padapter, u8 tid, u8 *addr)
+{
+	struct cmd_priv		*pcmdpriv = &padapter->cmdpriv;
+	struct cmd_obj		*ph2c;
+	struct addBaReq_parm	*paddbareq_parm;
+
+	u8	res = _SUCCESS;
+
+
+	ph2c = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj));
+	if (ph2c == NULL) {
+		res = _FAIL;
+		goto exit;
+	}
+
+	paddbareq_parm = (struct addBaReq_parm *)rtw_zmalloc(sizeof(struct addBaReq_parm));
+	if (paddbareq_parm == NULL) {
+		rtw_mfree((unsigned char *)ph2c, sizeof(struct	cmd_obj));
+		res = _FAIL;
+		goto exit;
+	}
+
+	paddbareq_parm->tid = tid;
+	_rtw_memcpy(paddbareq_parm->addr, addr, ETH_ALEN);
+
+	init_h2fwcmd_w_parm_no_rsp(ph2c, paddbareq_parm, GEN_CMD_CODE(_AddBAReq));
+
+	/* RTW_INFO("rtw_addbareq_cmd, tid=%d\n", tid); */
+
+	/* rtw_enqueue_cmd(pcmdpriv, ph2c);	 */
+	res = rtw_enqueue_cmd(pcmdpriv, ph2c);
+
+exit:
+
+
+	return res;
+}
+
+u8 rtw_addbarsp_cmd(_adapter *padapter, u8 *addr, u16 tid, u8 status, u8 size, u16 start_seq)
+{
+	struct cmd_priv *pcmdpriv = &padapter->cmdpriv;
+	struct cmd_obj *ph2c;
+	struct addBaRsp_parm *paddBaRsp_parm;
+	u8 res = _SUCCESS;
+
+
+	ph2c = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj));
+	if (ph2c == NULL) {
+		res = _FAIL;
+		goto exit;
+	}
+
+	paddBaRsp_parm = (struct addBaRsp_parm *)rtw_zmalloc(sizeof(struct addBaRsp_parm));
+
+	if (paddBaRsp_parm == NULL) {
+		rtw_mfree((unsigned char *)ph2c, sizeof(struct cmd_obj));
+		res = _FAIL;
+		goto exit;
+	}
+
+	_rtw_memcpy(paddBaRsp_parm->addr, addr, ETH_ALEN);
+	paddBaRsp_parm->tid = tid;
+	paddBaRsp_parm->status = status;
+	paddBaRsp_parm->size = size;
+	paddBaRsp_parm->start_seq = start_seq;
+
+	init_h2fwcmd_w_parm_no_rsp(ph2c, paddBaRsp_parm, GEN_CMD_CODE(_AddBARsp));
+
+	res = rtw_enqueue_cmd(pcmdpriv, ph2c);
+
+exit:
+
+
+	return res;
+}
+/* add for CONFIG_IEEE80211W, none 11w can use it */
+u8 rtw_reset_securitypriv_cmd(_adapter *padapter)
+{
+	struct cmd_obj		*ph2c;
+	struct drvextra_cmd_parm  *pdrvextra_cmd_parm;
+	struct cmd_priv	*pcmdpriv = &padapter->cmdpriv;
+	u8	res = _SUCCESS;
+
+
+	ph2c = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj));
+	if (ph2c == NULL) {
+		res = _FAIL;
+		goto exit;
+	}
+
+	pdrvextra_cmd_parm = (struct drvextra_cmd_parm *)rtw_zmalloc(sizeof(struct drvextra_cmd_parm));
+	if (pdrvextra_cmd_parm == NULL) {
+		rtw_mfree((unsigned char *)ph2c, sizeof(struct cmd_obj));
+		res = _FAIL;
+		goto exit;
+	}
+
+	pdrvextra_cmd_parm->ec_id = RESET_SECURITYPRIV;
+	pdrvextra_cmd_parm->type = 0;
+	pdrvextra_cmd_parm->size = 0;
+	pdrvextra_cmd_parm->pbuf = NULL;
+
+	init_h2fwcmd_w_parm_no_rsp(ph2c, pdrvextra_cmd_parm, GEN_CMD_CODE(_Set_Drv_Extra));
+
+
+	/* rtw_enqueue_cmd(pcmdpriv, ph2c);	 */
+	res = rtw_enqueue_cmd(pcmdpriv, ph2c);
+
+exit:
+
+
+	return res;
+
+}
+
+void free_assoc_resources_hdl(_adapter *padapter, u8 lock_scanned_queue)
+{
+	rtw_free_assoc_resources(padapter, lock_scanned_queue);
+}
+
+u8 rtw_free_assoc_resources_cmd(_adapter *padapter, u8 lock_scanned_queue, int flags)
+{
+	struct cmd_obj *cmd;
+	struct drvextra_cmd_parm  *pdrvextra_cmd_parm;
+	struct cmd_priv	*pcmdpriv = &padapter->cmdpriv;
+	struct submit_ctx sctx;
+	u8	res = _SUCCESS;
+
+	if (flags & RTW_CMDF_DIRECTLY) {
+		free_assoc_resources_hdl(padapter, lock_scanned_queue);
+	}
+	else {
+		cmd = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj));
+		if (cmd == NULL) {
+			res = _FAIL;
+			goto exit;
+		}
+
+		pdrvextra_cmd_parm = (struct drvextra_cmd_parm *)rtw_zmalloc(sizeof(struct drvextra_cmd_parm));
+		if (pdrvextra_cmd_parm == NULL) {
+			rtw_mfree((unsigned char *)cmd, sizeof(struct cmd_obj));
+			res = _FAIL;
+			goto exit;
+		}
+
+		pdrvextra_cmd_parm->ec_id = FREE_ASSOC_RESOURCES;
+		pdrvextra_cmd_parm->type = lock_scanned_queue;
+		pdrvextra_cmd_parm->size = 0;
+		pdrvextra_cmd_parm->pbuf = NULL;
+
+		init_h2fwcmd_w_parm_no_rsp(cmd, pdrvextra_cmd_parm, GEN_CMD_CODE(_Set_Drv_Extra));
+		if (flags & RTW_CMDF_WAIT_ACK) {
+			cmd->sctx = &sctx;
+			rtw_sctx_init(&sctx, 2000);
+		}
+
+		res = rtw_enqueue_cmd(pcmdpriv, cmd);
+
+		if (res == _SUCCESS && (flags & RTW_CMDF_WAIT_ACK)) {
+			rtw_sctx_wait(&sctx, __func__);
+			_enter_critical_mutex(&pcmdpriv->sctx_mutex, NULL);
+			if (sctx.status == RTW_SCTX_SUBMITTED)
+				cmd->sctx = NULL;
+			_exit_critical_mutex(&pcmdpriv->sctx_mutex, NULL);
+		}
+	}
+exit:
+	return res;
+
+}
+
+u8 rtw_dynamic_chk_wk_cmd(_adapter *padapter)
+{
+	struct cmd_obj		*ph2c;
+	struct drvextra_cmd_parm  *pdrvextra_cmd_parm;
+	struct cmd_priv	*pcmdpriv = &padapter->cmdpriv;
+	u8	res = _SUCCESS;
+
+
+	/* only  primary padapter does this cmd */
+
+	ph2c = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj));
+	if (ph2c == NULL) {
+		res = _FAIL;
+		goto exit;
+	}
+
+	pdrvextra_cmd_parm = (struct drvextra_cmd_parm *)rtw_zmalloc(sizeof(struct drvextra_cmd_parm));
+	if (pdrvextra_cmd_parm == NULL) {
+		rtw_mfree((unsigned char *)ph2c, sizeof(struct cmd_obj));
+		res = _FAIL;
+		goto exit;
+	}
+
+	pdrvextra_cmd_parm->ec_id = DYNAMIC_CHK_WK_CID;
+	pdrvextra_cmd_parm->type = 0;
+	pdrvextra_cmd_parm->size = 0;
+	pdrvextra_cmd_parm->pbuf = NULL;
+	init_h2fwcmd_w_parm_no_rsp(ph2c, pdrvextra_cmd_parm, GEN_CMD_CODE(_Set_Drv_Extra));
+
+
+	/* rtw_enqueue_cmd(pcmdpriv, ph2c);	 */
+	res = rtw_enqueue_cmd(pcmdpriv, ph2c);
+
+exit:
+
+
+	return res;
+
+}
+
+u8 rtw_set_chbw_cmd(_adapter *padapter, u8 ch, u8 bw, u8 ch_offset, u8 flags)
+{
+	struct cmd_obj *pcmdobj;
+	struct set_ch_parm *set_ch_parm;
+	struct cmd_priv *pcmdpriv = &padapter->cmdpriv;
+	struct submit_ctx sctx;
+	u8 res = _SUCCESS;
+
+
+	RTW_INFO(FUNC_NDEV_FMT" ch:%u, bw:%u, ch_offset:%u\n",
+		 FUNC_NDEV_ARG(padapter->pnetdev), ch, bw, ch_offset);
+
+	/* check input parameter */
+
+	/* prepare cmd parameter */
+	set_ch_parm = (struct set_ch_parm *)rtw_zmalloc(sizeof(*set_ch_parm));
+	if (set_ch_parm == NULL) {
+		res = _FAIL;
+		goto exit;
+	}
+	set_ch_parm->ch = ch;
+	set_ch_parm->bw = bw;
+	set_ch_parm->ch_offset = ch_offset;
+
+	if (flags & RTW_CMDF_DIRECTLY) {
+		/* no need to enqueue, do the cmd hdl directly and free cmd parameter */
+		if (H2C_SUCCESS != rtw_set_chbw_hdl(padapter, (u8 *)set_ch_parm))
+			res = _FAIL;
+
+		rtw_mfree((u8 *)set_ch_parm, sizeof(*set_ch_parm));
+	} else {
+		/* need enqueue, prepare cmd_obj and enqueue */
+		pcmdobj = (struct cmd_obj *)rtw_zmalloc(sizeof(struct	cmd_obj));
+		if (pcmdobj == NULL) {
+			rtw_mfree((u8 *)set_ch_parm, sizeof(*set_ch_parm));
+			res = _FAIL;
+			goto exit;
+		}
+
+		init_h2fwcmd_w_parm_no_rsp(pcmdobj, set_ch_parm, GEN_CMD_CODE(_SetChannel));
+
+		if (flags & RTW_CMDF_WAIT_ACK) {
+			pcmdobj->sctx = &sctx;
+			rtw_sctx_init(&sctx, 10 * 1000);
+		}
+
+		res = rtw_enqueue_cmd(pcmdpriv, pcmdobj);
+
+		if (res == _SUCCESS && (flags & RTW_CMDF_WAIT_ACK)) {
+			rtw_sctx_wait(&sctx, __func__);
+			_enter_critical_mutex(&pcmdpriv->sctx_mutex, NULL);
+			if (sctx.status == RTW_SCTX_SUBMITTED)
+				pcmdobj->sctx = NULL;
+			_exit_critical_mutex(&pcmdpriv->sctx_mutex, NULL);
+		}
+	}
+
+	/* do something based on res... */
+
+exit:
+
+	RTW_INFO(FUNC_NDEV_FMT" res:%u\n", FUNC_NDEV_ARG(padapter->pnetdev), res);
+
+
+	return res;
+}
+
+u8 _rtw_set_chplan_cmd(_adapter *adapter, int flags, u8 chplan, const struct country_chplan *country_ent, u8 swconfig)
+{
+	struct cmd_obj *cmdobj;
+	struct	SetChannelPlan_param *parm;
+	struct cmd_priv *pcmdpriv = &adapter->cmdpriv;
+	struct submit_ctx sctx;
+	u8 res = _SUCCESS;
+
+
+	/* check if allow software config */
+	if (swconfig && rtw_hal_is_disable_sw_channel_plan(adapter) == _TRUE) {
+		res = _FAIL;
+		goto exit;
+	}
+
+	/* if country_entry is provided, replace chplan */
+	if (country_ent)
+		chplan = country_ent->chplan;
+
+	/* check input parameter */
+	if (!rtw_is_channel_plan_valid(chplan)) {
+		res = _FAIL;
+		goto exit;
+	}
+
+	/* prepare cmd parameter */
+	parm = (struct SetChannelPlan_param *)rtw_zmalloc(sizeof(*parm));
+	if (parm == NULL) {
+		res = _FAIL;
+		goto exit;
+	}
+	parm->country_ent = country_ent;
+	parm->channel_plan = chplan;
+
+	if (flags & RTW_CMDF_DIRECTLY) {
+		/* no need to enqueue, do the cmd hdl directly and free cmd parameter */
+		if (H2C_SUCCESS != set_chplan_hdl(adapter, (u8 *)parm))
+			res = _FAIL;
+		rtw_mfree((u8 *)parm, sizeof(*parm));
+	} else {
+		/* need enqueue, prepare cmd_obj and enqueue */
+		cmdobj = (struct cmd_obj *)rtw_zmalloc(sizeof(*cmdobj));
+		if (cmdobj == NULL) {
+			res = _FAIL;
+			rtw_mfree((u8 *)parm, sizeof(*parm));
+			goto exit;
+		}
+
+		init_h2fwcmd_w_parm_no_rsp(cmdobj, parm, GEN_CMD_CODE(_SetChannelPlan));
+
+		if (flags & RTW_CMDF_WAIT_ACK) {
+			cmdobj->sctx = &sctx;
+			rtw_sctx_init(&sctx, 2000);
+		}
+
+		res = rtw_enqueue_cmd(pcmdpriv, cmdobj);
+
+		if (res == _SUCCESS && (flags & RTW_CMDF_WAIT_ACK)) {
+			rtw_sctx_wait(&sctx, __func__);
+			_enter_critical_mutex(&pcmdpriv->sctx_mutex, NULL);
+			if (sctx.status == RTW_SCTX_SUBMITTED)
+				cmdobj->sctx = NULL;
+			_exit_critical_mutex(&pcmdpriv->sctx_mutex, NULL);
+			if (sctx.status != RTW_SCTX_DONE_SUCCESS)
+				res = _FAIL;
+		}
+
+		/* allow set channel plan when cmd_thread is not running */
+		if (res != _SUCCESS && (flags & RTW_CMDF_WAIT_ACK)) {
+			parm = (struct SetChannelPlan_param *)rtw_zmalloc(sizeof(*parm));
+			if (parm == NULL) {
+				res = _FAIL;
+				goto exit;
+			}
+			parm->country_ent = country_ent;
+			parm->channel_plan = chplan;
+
+			if (H2C_SUCCESS != set_chplan_hdl(adapter, (u8 *)parm))
+				res = _FAIL;
+			else
+				res = _SUCCESS;
+			rtw_mfree((u8 *)parm, sizeof(*parm));
+		}
+	}
+
+exit:
+	return res;
+}
+
+inline u8 rtw_set_chplan_cmd(_adapter *adapter, int flags, u8 chplan, u8 swconfig)
+{
+	return _rtw_set_chplan_cmd(adapter, flags, chplan, NULL, swconfig);
+}
+
+inline u8 rtw_set_country_cmd(_adapter *adapter, int flags, const char *country_code, u8 swconfig)
+{
+	const struct country_chplan *ent;
+
+	if (is_alpha(country_code[0]) == _FALSE
+	    || is_alpha(country_code[1]) == _FALSE
+	   ) {
+		RTW_PRINT("%s input country_code is not alpha2\n", __func__);
+		return _FAIL;
+	}
+
+	ent = rtw_get_chplan_from_country(country_code);
+
+	if (ent == NULL) {
+		RTW_PRINT("%s unsupported country_code:\"%c%c\"\n", __func__, country_code[0], country_code[1]);
+		return _FAIL;
+	}
+
+	RTW_PRINT("%s country_code:\"%c%c\" mapping to chplan:0x%02x\n", __func__, country_code[0], country_code[1], ent->chplan);
+
+	return _rtw_set_chplan_cmd(adapter, flags, RTW_CHPLAN_UNSPECIFIED, ent, swconfig);
+}
+
+u8 rtw_led_blink_cmd(_adapter *padapter, PVOID pLed)
+{
+	struct	cmd_obj	*pcmdobj;
+	struct	LedBlink_param *ledBlink_param;
+	struct	cmd_priv   *pcmdpriv = &padapter->cmdpriv;
+
+	u8	res = _SUCCESS;
+
+
+
+	pcmdobj = (struct	cmd_obj *)rtw_zmalloc(sizeof(struct	cmd_obj));
+	if (pcmdobj == NULL) {
+		res = _FAIL;
+		goto exit;
+	}
+
+	ledBlink_param = (struct	LedBlink_param *)rtw_zmalloc(sizeof(struct	LedBlink_param));
+	if (ledBlink_param == NULL) {
+		rtw_mfree((u8 *)pcmdobj, sizeof(struct cmd_obj));
+		res = _FAIL;
+		goto exit;
+	}
+
+	ledBlink_param->pLed = pLed;
+
+	init_h2fwcmd_w_parm_no_rsp(pcmdobj, ledBlink_param, GEN_CMD_CODE(_LedBlink));
+	res = rtw_enqueue_cmd(pcmdpriv, pcmdobj);
+
+exit:
+
+
+	return res;
+}
+
+u8 rtw_set_csa_cmd(_adapter *adapter)
+{
+	struct cmd_obj *cmdobj;
+	struct cmd_priv *cmdpriv = &adapter->cmdpriv;
+	u8	res = _SUCCESS;
+
+	cmdobj = rtw_zmalloc(sizeof(struct cmd_obj));
+	if (cmdobj == NULL) {
+		res = _FAIL;
+		goto exit;
+	}
+
+	init_h2fwcmd_w_parm_no_parm_rsp(cmdobj, GEN_CMD_CODE(_SetChannelSwitch));
+	res = rtw_enqueue_cmd(cmdpriv, cmdobj);
+
+exit:
+	return res;
+}
+
+u8 rtw_tdls_cmd(_adapter *padapter, u8 *addr, u8 option)
+{
+	u8 res = _SUCCESS;
+#ifdef CONFIG_TDLS
+	struct	cmd_obj	*pcmdobj;
+	struct	TDLSoption_param	*TDLSoption;
+	struct	mlme_priv *pmlmepriv = &padapter->mlmepriv;
+	struct	cmd_priv   *pcmdpriv = &padapter->cmdpriv;
+
+	pcmdobj = (struct	cmd_obj *)rtw_zmalloc(sizeof(struct	cmd_obj));
+	if (pcmdobj == NULL) {
+		res = _FAIL;
+		goto exit;
+	}
+
+	TDLSoption = (struct TDLSoption_param *)rtw_zmalloc(sizeof(struct TDLSoption_param));
+	if (TDLSoption == NULL) {
+		rtw_mfree((u8 *)pcmdobj, sizeof(struct cmd_obj));
+		res = _FAIL;
+		goto exit;
+	}
+
+	_rtw_spinlock(&(padapter->tdlsinfo.cmd_lock));
+	if (addr != NULL)
+		_rtw_memcpy(TDLSoption->addr, addr, 6);
+	TDLSoption->option = option;
+	_rtw_spinunlock(&(padapter->tdlsinfo.cmd_lock));
+	init_h2fwcmd_w_parm_no_rsp(pcmdobj, TDLSoption, GEN_CMD_CODE(_TDLS));
+	res = rtw_enqueue_cmd(pcmdpriv, pcmdobj);
+
+exit:
+#endif /* CONFIG_TDLS */
+
+	return res;
+}
+
+u8 rtw_enable_hw_update_tsf_cmd(_adapter *padapter)
+{
+	struct cmd_obj *ph2c;
+	struct drvextra_cmd_parm	*pdrvextra_cmd_parm;
+	struct cmd_priv *pcmdpriv = &padapter->cmdpriv;
+	u8	res = _SUCCESS;
+
+
+	ph2c = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj));
+	if (ph2c == NULL) {
+		res = _FAIL;
+		goto exit;
+	}
+
+	pdrvextra_cmd_parm = (struct drvextra_cmd_parm *)rtw_zmalloc(sizeof(struct drvextra_cmd_parm));
+	if (pdrvextra_cmd_parm == NULL) {
+		rtw_mfree((unsigned char *)ph2c, sizeof(struct cmd_obj));
+		res = _FAIL;
+		goto exit;
+	}
+
+	pdrvextra_cmd_parm->ec_id = EN_HW_UPDATE_TSF_WK_CID;
+	pdrvextra_cmd_parm->type = 0;
+	pdrvextra_cmd_parm->size = 0;
+	pdrvextra_cmd_parm->pbuf = NULL;
+
+	init_h2fwcmd_w_parm_no_rsp(ph2c, pdrvextra_cmd_parm, GEN_CMD_CODE(_Set_Drv_Extra));
+
+	res = rtw_enqueue_cmd(pcmdpriv, ph2c);
+
+exit:
+	return res;
+}
+
+u8 rtw_periodic_tsf_update_end_cmd(_adapter *adapter)
+{
+	struct cmd_obj *cmdobj;
+	struct drvextra_cmd_parm *parm;
+	struct cmd_priv *cmdpriv = &adapter->cmdpriv;
+	u8 res = _SUCCESS;
+
+	cmdobj = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj));
+	if (cmdobj == NULL) {
+		res = _FAIL;
+		goto exit;
+	}
+
+	parm = (struct drvextra_cmd_parm *)rtw_zmalloc(sizeof(struct drvextra_cmd_parm));
+	if (parm == NULL) {
+		rtw_mfree((unsigned char *)cmdobj, sizeof(struct cmd_obj));
+		res = _FAIL;
+		goto exit;
+	}
+
+	parm->ec_id = PERIOD_TSF_UPDATE_END_WK_CID;
+	parm->type = 0;
+	parm->size = 0;
+	parm->pbuf = NULL;
+
+	init_h2fwcmd_w_parm_no_rsp(cmdobj, parm, GEN_CMD_CODE(_Set_Drv_Extra));
+
+	res = rtw_enqueue_cmd(cmdpriv, cmdobj);
+
+exit:
+	return res;
+}
+#ifdef CONFIG_LPS
+#ifdef CONFIG_LPS_CHK_BY_TP
+u8 _lps_chk_by_tp(_adapter *adapter, u8 from_timer)
+{
+	u8 enter_ps = _FALSE;
+	struct mlme_priv *pmlmepriv = &adapter->mlmepriv;
+	struct sta_priv *pstapriv = &adapter->stapriv;
+	struct sta_info *psta;
+	struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(adapter);
+	u32 tx_tp_mbits, rx_tp_mbits, bi_tp_mbits;
+
+	psta = rtw_get_stainfo(pstapriv, get_bssid(pmlmepriv));
+	if (psta == NULL) {
+		RTW_ERR(ADPT_FMT" sta == NULL\n", ADPT_ARG(adapter));
+		rtw_warn_on(1);
+		return enter_ps;
+	}
+
+	psta->sta_stats.acc_tx_bytes = psta->sta_stats.tx_bytes;
+	psta->sta_stats.acc_rx_bytes = psta->sta_stats.rx_bytes;
+
+#if 1
+	tx_tp_mbits = psta->sta_stats.tx_tp_kbits >> 10;
+	rx_tp_mbits = psta->sta_stats.rx_tp_kbits >> 10;
+	bi_tp_mbits = tx_tp_mbits + rx_tp_mbits;
+#else
+	tx_tp_mbits = psta->sta_stats.smooth_tx_tp_kbits >> 10;
+	rx_tp_mbits = psta->sta_stats.smooth_rx_tp_kbits >> 10;
+	bi_tp_mbits = tx_tp_mbits + rx_tp_mbits;
+#endif
+
+	if ((bi_tp_mbits >= pwrpriv->lps_bi_tp_th) ||
+		(tx_tp_mbits >= pwrpriv->lps_tx_tp_th) ||
+		(rx_tp_mbits >= pwrpriv->lps_rx_tp_th)) {
+		enter_ps = _FALSE;
+		pwrpriv->lps_chk_cnt = pwrpriv->lps_chk_cnt_th;
+	}
+	else {
+		if (pwrpriv->lps_chk_cnt && --pwrpriv->lps_chk_cnt)
+			enter_ps = _FALSE;
+		else
+			enter_ps = _TRUE;
+	}
+
+	if (1) {
+		RTW_INFO(FUNC_ADPT_FMT" tx_tp:%d [%d], rx_tp:%d [%d], bi_tp:%d [%d], enter_ps(%d):%s\n",
+			FUNC_ADPT_ARG(adapter),
+			tx_tp_mbits, pwrpriv->lps_tx_tp_th,
+			rx_tp_mbits, pwrpriv->lps_rx_tp_th,
+			bi_tp_mbits, pwrpriv->lps_bi_tp_th,
+			pwrpriv->lps_chk_cnt,
+			(enter_ps == _TRUE) ? "True" : "False");
+		RTW_INFO(FUNC_ADPT_FMT" tx_pkt_cnt :%d [%d], rx_pkt_cnt :%d [%d]\n",
+			FUNC_ADPT_ARG(adapter),
+			pmlmepriv->LinkDetectInfo.NumTxOkInPeriod,
+			pwrpriv->lps_tx_pkts,
+			pmlmepriv->LinkDetectInfo.NumRxUnicastOkInPeriod,
+			pwrpriv->lps_rx_pkts);
+		if (!adapter->bsta_tp_dump)
+			RTW_INFO(FUNC_ADPT_FMT" bcn_cnt:%d (per-%d second)\n",
+			FUNC_ADPT_ARG(adapter),
+			rtw_get_bcn_cnt(psta->padapter),
+			2);
+	}
+
+	if (enter_ps) {
+		if (!from_timer)
+			LPS_Enter(adapter, "TRAFFIC_IDLE");
+	} else {
+		if (!from_timer)
+			LPS_Leave(adapter, "TRAFFIC_BUSY");
+		else {
+			#ifdef CONFIG_CONCURRENT_MODE
+			#ifndef CONFIG_FW_MULTI_PORT_SUPPORT
+			if (adapter->hw_port == HW_PORT0)
+			#endif
+			#endif
+				rtw_lps_ctrl_wk_cmd(adapter, LPS_CTRL_TRAFFIC_BUSY, 1);
+		}
+	}
+
+	return enter_ps;
+}
+#endif
+
+static u8 _lps_chk_by_pkt_cnts(_adapter *padapter, u8 from_timer, u8 bBusyTraffic)
+{		
+	struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
+	u8	bEnterPS = _FALSE;
+
+	/* check traffic for  powersaving. */
+	if (((pmlmepriv->LinkDetectInfo.NumRxUnicastOkInPeriod + pmlmepriv->LinkDetectInfo.NumTxOkInPeriod) > 8) ||
+		#ifdef CONFIG_LPS_SLOW_TRANSITION
+		(pmlmepriv->LinkDetectInfo.NumRxUnicastOkInPeriod > 2)
+		#else /* CONFIG_LPS_SLOW_TRANSITION */
+		(pmlmepriv->LinkDetectInfo.NumRxUnicastOkInPeriod > 4)
+		#endif /* CONFIG_LPS_SLOW_TRANSITION */
+	) {
+		#ifdef DBG_RX_COUNTER_DUMP
+		if (padapter->dump_rx_cnt_mode & DUMP_DRV_TRX_COUNTER_DATA)
+			RTW_INFO("(-)Tx = %d, Rx = %d\n", pmlmepriv->LinkDetectInfo.NumTxOkInPeriod, pmlmepriv->LinkDetectInfo.NumRxUnicastOkInPeriod);
+		#endif
+
+		bEnterPS = _FALSE;
+		#ifdef CONFIG_LPS_SLOW_TRANSITION
+		if (bBusyTraffic == _TRUE) {
+			if (pmlmepriv->LinkDetectInfo.TrafficTransitionCount <= 4)
+				pmlmepriv->LinkDetectInfo.TrafficTransitionCount = 4;
+
+			pmlmepriv->LinkDetectInfo.TrafficTransitionCount++;
+
+			/* RTW_INFO("Set TrafficTransitionCount to %d\n", pmlmepriv->LinkDetectInfo.TrafficTransitionCount); */
+
+			if (pmlmepriv->LinkDetectInfo.TrafficTransitionCount > 30/*TrafficTransitionLevel*/)
+				pmlmepriv->LinkDetectInfo.TrafficTransitionCount = 30;
+		}
+		#endif /* CONFIG_LPS_SLOW_TRANSITION */
+	} else {
+		#ifdef DBG_RX_COUNTER_DUMP
+		if (padapter->dump_rx_cnt_mode & DUMP_DRV_TRX_COUNTER_DATA)
+			RTW_INFO("(+)Tx = %d, Rx = %d\n", pmlmepriv->LinkDetectInfo.NumTxOkInPeriod, pmlmepriv->LinkDetectInfo.NumRxUnicastOkInPeriod);
+		#endif
+
+		#ifdef CONFIG_LPS_SLOW_TRANSITION
+		if (pmlmepriv->LinkDetectInfo.TrafficTransitionCount >= 2)
+			pmlmepriv->LinkDetectInfo.TrafficTransitionCount -= 2;
+		else
+			pmlmepriv->LinkDetectInfo.TrafficTransitionCount = 0;
+
+		if (pmlmepriv->LinkDetectInfo.TrafficTransitionCount == 0)
+			bEnterPS = _TRUE;
+		#else /* CONFIG_LPS_SLOW_TRANSITION */
+			bEnterPS = _TRUE;
+		#endif /* CONFIG_LPS_SLOW_TRANSITION */
+	}
+
+	#ifdef CONFIG_DYNAMIC_DTIM
+	if (pmlmepriv->LinkDetectInfo.LowPowerTransitionCount == 8)
+		bEnterPS = _FALSE;
+
+	RTW_INFO("LowPowerTransitionCount=%d\n", pmlmepriv->LinkDetectInfo.LowPowerTransitionCount);
+	#endif /* CONFIG_DYNAMIC_DTIM */
+
+	/* LeisurePS only work in infra mode. */
+	if (bEnterPS) {
+		if (!from_timer) {
+			#ifdef CONFIG_DYNAMIC_DTIM
+			if (pmlmepriv->LinkDetectInfo.LowPowerTransitionCount < 8)
+				adapter_to_pwrctl(padapter)->dtim = 1;
+			else
+				adapter_to_pwrctl(padapter)->dtim = 3;
+			#endif /* CONFIG_DYNAMIC_DTIM */
+			LPS_Enter(padapter, "TRAFFIC_IDLE");
+		} else {
+			/* do this at caller */
+			/* rtw_lps_ctrl_wk_cmd(adapter, LPS_CTRL_ENTER, 1); */
+			/* rtw_hal_dm_watchdog_in_lps(padapter); */
+		}
+
+		#ifdef CONFIG_DYNAMIC_DTIM
+		if (adapter_to_pwrctl(padapter)->bFwCurrentInPSMode == _TRUE)
+			pmlmepriv->LinkDetectInfo.LowPowerTransitionCount++;
+		#endif /* CONFIG_DYNAMIC_DTIM */
+	} else {
+		#ifdef CONFIG_DYNAMIC_DTIM
+		if (pmlmepriv->LinkDetectInfo.LowPowerTransitionCount != 8)
+			pmlmepriv->LinkDetectInfo.LowPowerTransitionCount = 0;
+		else
+			pmlmepriv->LinkDetectInfo.LowPowerTransitionCount++;
+		#endif /* CONFIG_DYNAMIC_DTIM */
+
+		if (!from_timer)
+			LPS_Leave(padapter, "TRAFFIC_BUSY");
+		else {
+			#ifdef CONFIG_CONCURRENT_MODE
+			#ifndef CONFIG_FW_MULTI_PORT_SUPPORT
+			if (padapter->hw_port == HW_PORT0)
+			#endif
+			#endif
+				rtw_lps_ctrl_wk_cmd(padapter, LPS_CTRL_TRAFFIC_BUSY, 1);
+		}
+	}
+
+	return bEnterPS;
+}
+#endif /* CONFIG_LPS */
+
+/* from_timer == 1 means driver is in LPS */
+u8 traffic_status_watchdog(_adapter *padapter, u8 from_timer)
+{
+	u8	bEnterPS = _FALSE;
+	u16 BusyThresholdHigh;
+	u16	BusyThresholdLow;
+	u16	BusyThreshold;
+	u8	bBusyTraffic = _FALSE, bTxBusyTraffic = _FALSE, bRxBusyTraffic = _FALSE;
+	u8	bHigherBusyTraffic = _FALSE, bHigherBusyRxTraffic = _FALSE, bHigherBusyTxTraffic = _FALSE;
+
+	struct mlme_priv		*pmlmepriv = &(padapter->mlmepriv);
+#ifdef CONFIG_TDLS
+	struct tdls_info *ptdlsinfo = &(padapter->tdlsinfo);
+	struct tdls_txmgmt txmgmt;
+	u8 baddr[ETH_ALEN] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
+#endif /* CONFIG_TDLS */
+#ifdef CONFIG_TRAFFIC_PROTECT
+	RT_LINK_DETECT_T *link_detect = &pmlmepriv->LinkDetectInfo;
+#endif
+
+#ifdef CONFIG_BT_COEXIST
+	if (padapter->registrypriv.wifi_spec != 1) {
+		BusyThresholdHigh = 25;
+		BusyThresholdLow = 10;
+	} else
+#endif /* CONFIG_BT_COEXIST */
+	{
+		BusyThresholdHigh = 100;
+		BusyThresholdLow = 75;
+	}
+	BusyThreshold = BusyThresholdHigh;
+
+
+	/*  */
+	/* Determine if our traffic is busy now */
+	/*  */
+	if ((check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE)
+	    /*&& !MgntInitAdapterInProgress(pMgntInfo)*/) {
+		/* if we raise bBusyTraffic in last watchdog, using lower threshold. */
+		if (pmlmepriv->LinkDetectInfo.bBusyTraffic)
+			BusyThreshold = BusyThresholdLow;
+
+		if (pmlmepriv->LinkDetectInfo.NumRxOkInPeriod > BusyThreshold ||
+		    pmlmepriv->LinkDetectInfo.NumTxOkInPeriod > BusyThreshold) {
+			bBusyTraffic = _TRUE;
+
+			if (pmlmepriv->LinkDetectInfo.NumRxOkInPeriod > pmlmepriv->LinkDetectInfo.NumTxOkInPeriod)
+				bRxBusyTraffic = _TRUE;
+			else
+				bTxBusyTraffic = _TRUE;
+		}
+
+		/* Higher Tx/Rx data. */
+		if (pmlmepriv->LinkDetectInfo.NumRxOkInPeriod > 4000 ||
+		    pmlmepriv->LinkDetectInfo.NumTxOkInPeriod > 4000) {
+			bHigherBusyTraffic = _TRUE;
+
+			if (pmlmepriv->LinkDetectInfo.NumRxOkInPeriod > pmlmepriv->LinkDetectInfo.NumTxOkInPeriod)
+				bHigherBusyRxTraffic = _TRUE;
+			else
+				bHigherBusyTxTraffic = _TRUE;
+		}
+
+#ifdef CONFIG_TRAFFIC_PROTECT
+#define TX_ACTIVE_TH 10
+#define RX_ACTIVE_TH 20
+#define TRAFFIC_PROTECT_PERIOD_MS 4500
+
+		if (link_detect->NumTxOkInPeriod > TX_ACTIVE_TH
+		    || link_detect->NumRxUnicastOkInPeriod > RX_ACTIVE_TH) {
+
+			RTW_INFO(FUNC_ADPT_FMT" acqiure wake_lock for %u ms(tx:%d,rx_unicast:%d)\n",
+				 FUNC_ADPT_ARG(padapter),
+				 TRAFFIC_PROTECT_PERIOD_MS,
+				 link_detect->NumTxOkInPeriod,
+				 link_detect->NumRxUnicastOkInPeriod);
+
+			rtw_lock_traffic_suspend_timeout(TRAFFIC_PROTECT_PERIOD_MS);
+		}
+#endif
+
+#ifdef CONFIG_TDLS
+#ifdef CONFIG_TDLS_AUTOSETUP
+		/* TDLS_WATCHDOG_PERIOD * 2sec, periodically send */
+		if (hal_chk_wl_func(padapter, WL_FUNC_TDLS) == _TRUE) {
+			if ((ptdlsinfo->watchdog_count % TDLS_WATCHDOG_PERIOD) == 0) {
+				_rtw_memcpy(txmgmt.peer, baddr, ETH_ALEN);
+				issue_tdls_dis_req(padapter, &txmgmt);
+			}
+			ptdlsinfo->watchdog_count++;
+		}
+#endif /* CONFIG_TDLS_AUTOSETUP */
+#endif /* CONFIG_TDLS */
+#ifdef CONFIG_LPS
+		if (adapter_to_pwrctl(padapter)->bLeisurePs && MLME_IS_STA(padapter)) {
+			#ifdef CONFIG_LPS_CHK_BY_TP
+			if (adapter_to_pwrctl(padapter)->lps_chk_by_tp)
+				bEnterPS = _lps_chk_by_tp(padapter, from_timer);
+			else
+			#endif /*CONFIG_LPS_CHK_BY_TP*/
+				bEnterPS = _lps_chk_by_pkt_cnts(padapter, from_timer, bBusyTraffic);
+		}
+#endif /* CONFIG_LPS */
+
+	} else {
+#ifdef CONFIG_LPS
+		if (!from_timer && rtw_mi_get_assoc_if_num(padapter) == 0)
+			LPS_Leave(padapter, "NON_LINKED");
+#endif
+	}
+
+	session_tracker_chk_cmd(padapter, NULL);
+
+#ifdef CONFIG_BEAMFORMING
+#ifdef RTW_BEAMFORMING_VERSION_2
+	rtw_bf_update_traffic(padapter);
+#endif /* RTW_BEAMFORMING_VERSION_2 */
+#endif /* CONFIG_BEAMFORMING */
+
+	pmlmepriv->LinkDetectInfo.NumRxOkInPeriod = 0;
+	pmlmepriv->LinkDetectInfo.NumTxOkInPeriod = 0;
+	pmlmepriv->LinkDetectInfo.NumRxUnicastOkInPeriod = 0;
+	pmlmepriv->LinkDetectInfo.bBusyTraffic = bBusyTraffic;
+	pmlmepriv->LinkDetectInfo.bTxBusyTraffic = bTxBusyTraffic;
+	pmlmepriv->LinkDetectInfo.bRxBusyTraffic = bRxBusyTraffic;
+	pmlmepriv->LinkDetectInfo.bHigherBusyTraffic = bHigherBusyTraffic;
+	pmlmepriv->LinkDetectInfo.bHigherBusyRxTraffic = bHigherBusyRxTraffic;
+	pmlmepriv->LinkDetectInfo.bHigherBusyTxTraffic = bHigherBusyTxTraffic;
+
+	return bEnterPS;
+
+}
+
+
+/* for 11n Logo 4.2.31/4.2.32 */
+static void dynamic_update_bcn_check(_adapter *padapter)
+{
+	struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
+	struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
+
+	if (!padapter->registrypriv.wifi_spec)
+		return;
+
+	if (!padapter->registrypriv.ht_enable || !is_supported_ht(padapter->registrypriv.wireless_mode))
+		return;
+
+	if (!MLME_IS_AP(padapter))
+		return;
+
+	if (pmlmeext->bstart_bss) {
+		/* In 10 * 2 = 20s, there are no legacy AP, update HT info  */
+		static u8 count = 1;
+
+		if (count % 10 == 0) {
+			count = 1;
+#ifdef CONFIG_80211N_HT
+			if (_FALSE == ATOMIC_READ(&pmlmepriv->olbc)
+				&& _FALSE == ATOMIC_READ(&pmlmepriv->olbc_ht)) {
+
+				if (rtw_ht_operation_update(padapter) > 0) {
+					update_beacon(padapter, _HT_CAPABILITY_IE_, NULL, _FALSE);
+					update_beacon(padapter, _HT_ADD_INFO_IE_, NULL, _TRUE);
+				}
+			}
+#endif /* CONFIG_80211N_HT */
+		}
+
+#ifdef CONFIG_80211N_HT
+		/* In 2s, there are any legacy AP, update HT info, and then reset count  */
+
+		if (_FALSE != ATOMIC_READ(&pmlmepriv->olbc)
+			&& _FALSE != ATOMIC_READ(&pmlmepriv->olbc_ht)) {
+					
+			if (rtw_ht_operation_update(padapter) > 0) {
+				update_beacon(padapter, _HT_CAPABILITY_IE_, NULL, _FALSE);
+				update_beacon(padapter, _HT_ADD_INFO_IE_, NULL, _TRUE);
+
+			}
+			ATOMIC_SET(&pmlmepriv->olbc, _FALSE);
+			ATOMIC_SET(&pmlmepriv->olbc_ht, _FALSE);
+			count = 0;
+		}
+#endif /* CONFIG_80211N_HT */
+		count ++;
+	}
+}
+void rtw_iface_dynamic_chk_wk_hdl(_adapter *padapter)
+{
+	#ifdef CONFIG_ACTIVE_KEEP_ALIVE_CHECK
+	#ifdef CONFIG_AP_MODE
+	if (MLME_IS_AP(padapter) || MLME_IS_MESH(padapter)) {
+		expire_timeout_chk(padapter);
+		#ifdef CONFIG_RTW_MESH
+		if (MLME_IS_MESH(padapter) && MLME_IS_ASOC(padapter))
+			rtw_mesh_peer_status_chk(padapter);
+		#endif
+	}
+	#endif
+	#endif /* CONFIG_ACTIVE_KEEP_ALIVE_CHECK */
+	dynamic_update_bcn_check(padapter);
+
+	linked_status_chk(padapter, 0);
+	traffic_status_watchdog(padapter, 0);
+
+	/* for debug purpose */
+	_linked_info_dump(padapter);
+
+	#ifdef CONFIG_BEAMFORMING
+	#ifndef RTW_BEAMFORMING_VERSION_2
+	#if (BEAMFORMING_SUPPORT == 0) /*for diver defined beamforming*/
+	beamforming_watchdog(padapter);
+	#endif
+	#endif /* !RTW_BEAMFORMING_VERSION_2 */
+	#endif
+
+#ifdef CONFIG_RTW_CFGVEDNOR_RSSIMONITOR
+        rtw_cfgvendor_rssi_monitor_evt(padapter);
+#endif
+
+
+}
+void rtw_dynamic_chk_wk_hdl(_adapter *padapter)
+{
+	rtw_mi_dynamic_chk_wk_hdl(padapter);
+
+#ifdef DBG_CONFIG_ERROR_DETECT
+	rtw_hal_sreset_xmit_status_check(padapter);
+	rtw_hal_sreset_linked_status_check(padapter);
+#endif
+
+	/* if(check_fwstate(pmlmepriv, _FW_UNDER_LINKING|_FW_UNDER_SURVEY)==_FALSE) */
+	{
+#ifdef DBG_RX_COUNTER_DUMP
+		rtw_dump_rx_counters(padapter);
+#endif
+		dm_DynamicUsbTxAgg(padapter, 0);
+	}
+	rtw_hal_dm_watchdog(padapter);
+
+	/* check_hw_pbc(padapter, pdrvextra_cmd->pbuf, pdrvextra_cmd->type); */
+
+#ifdef CONFIG_BT_COEXIST
+	/* BT-Coexist */
+	rtw_btcoex_Handler(padapter);
+#endif
+
+#ifdef CONFIG_IPS_CHECK_IN_WD
+	/* always call rtw_ps_processor() at last one. */
+	rtw_ps_processor(padapter);
+#endif
+
+#ifdef CONFIG_MCC_MODE
+	rtw_hal_mcc_sw_status_check(padapter);
+#endif /* CONFIG_MCC_MODE */
+
+	rtw_hal_periodic_tsf_update_chk(padapter);
+}
+
+#ifdef CONFIG_LPS
+
+void lps_ctrl_wk_hdl(_adapter *padapter, u8 lps_ctrl_type);
+void lps_ctrl_wk_hdl(_adapter *padapter, u8 lps_ctrl_type)
+{
+	struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter);
+	struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
+	u8	mstatus;
+
+
+	if ((check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE) == _TRUE)
+	    || (check_fwstate(pmlmepriv, WIFI_ADHOC_STATE) == _TRUE))
+		return;
+
+	switch (lps_ctrl_type) {
+	case LPS_CTRL_SCAN:
+		/* RTW_INFO("LPS_CTRL_SCAN\n"); */
+#ifdef CONFIG_BT_COEXIST
+		rtw_btcoex_ScanNotify(padapter, _TRUE);
+#endif /* CONFIG_BT_COEXIST */
+		if (check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE) {
+			/* connect */
+			LPS_Leave(padapter, "LPS_CTRL_SCAN");
+		}
+		break;
+	case LPS_CTRL_JOINBSS:
+		/* RTW_INFO("LPS_CTRL_JOINBSS\n"); */
+		LPS_Leave(padapter, "LPS_CTRL_JOINBSS");
+		break;
+	case LPS_CTRL_CONNECT:
+		/* RTW_INFO("LPS_CTRL_CONNECT\n"); */
+		mstatus = 1;/* connect */
+		/* Reset LPS Setting */
+		pwrpriv->LpsIdleCount = 0;
+		rtw_hal_set_hwreg(padapter, HW_VAR_H2C_FW_JOINBSSRPT, (u8 *)(&mstatus));
+#ifdef CONFIG_BT_COEXIST
+		rtw_btcoex_MediaStatusNotify(padapter, mstatus);
+#endif /* CONFIG_BT_COEXIST */
+		break;
+	case LPS_CTRL_DISCONNECT:
+		/* RTW_INFO("LPS_CTRL_DISCONNECT\n"); */
+		mstatus = 0;/* disconnect */
+#ifdef CONFIG_BT_COEXIST
+		rtw_btcoex_MediaStatusNotify(padapter, mstatus);
+#endif /* CONFIG_BT_COEXIST */
+		LPS_Leave(padapter, "LPS_CTRL_DISCONNECT");
+		rtw_hal_set_hwreg(padapter, HW_VAR_H2C_FW_JOINBSSRPT, (u8 *)(&mstatus));
+		break;
+	case LPS_CTRL_SPECIAL_PACKET:
+		/* RTW_INFO("LPS_CTRL_SPECIAL_PACKET\n"); */
+		pwrpriv->DelayLPSLastTimeStamp = rtw_get_current_time();
+#ifdef CONFIG_BT_COEXIST
+		rtw_btcoex_SpecialPacketNotify(padapter, PACKET_DHCP);
+#endif /* CONFIG_BT_COEXIST */
+		LPS_Leave(padapter, "LPS_CTRL_SPECIAL_PACKET");
+		break;
+	case LPS_CTRL_LEAVE:
+		LPS_Leave(padapter, "LPS_CTRL_LEAVE");
+		break;
+	case LPS_CTRL_LEAVE_CFG80211_PWRMGMT:
+		LPS_Leave(padapter, "CFG80211_PWRMGMT");
+		break;
+	case LPS_CTRL_TRAFFIC_BUSY:
+		LPS_Leave(padapter, "LPS_CTRL_TRAFFIC_BUSY");
+		break;
+	case LPS_CTRL_TX_TRAFFIC_LEAVE:
+		LPS_Leave(padapter, "LPS_CTRL_TX_TRAFFIC_LEAVE");
+		break;
+	case LPS_CTRL_RX_TRAFFIC_LEAVE:
+		LPS_Leave(padapter, "LPS_CTRL_RX_TRAFFIC_LEAVE");
+		break;
+	case LPS_CTRL_ENTER:
+		LPS_Enter(padapter, "TRAFFIC_IDLE_1");
+		break;
+	default:
+		break;
+	}
+
+}
+
+u8 rtw_lps_ctrl_wk_cmd(_adapter *padapter, u8 lps_ctrl_type, u8 enqueue)
+{
+	struct cmd_obj	*ph2c;
+	struct drvextra_cmd_parm	*pdrvextra_cmd_parm;
+	struct cmd_priv	*pcmdpriv = &padapter->cmdpriv;
+	/* struct pwrctrl_priv *pwrctrlpriv = adapter_to_pwrctl(padapter); */
+	u8	res = _SUCCESS;
+
+
+	/* if(!pwrctrlpriv->bLeisurePs) */
+	/*	return res; */
+
+	if (enqueue) {
+		ph2c = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj));
+		if (ph2c == NULL) {
+			res = _FAIL;
+			goto exit;
+		}
+
+		pdrvextra_cmd_parm = (struct drvextra_cmd_parm *)rtw_zmalloc(sizeof(struct drvextra_cmd_parm));
+		if (pdrvextra_cmd_parm == NULL) {
+			rtw_mfree((unsigned char *)ph2c, sizeof(struct cmd_obj));
+			res = _FAIL;
+			goto exit;
+		}
+
+		pdrvextra_cmd_parm->ec_id = LPS_CTRL_WK_CID;
+		pdrvextra_cmd_parm->type = lps_ctrl_type;
+		pdrvextra_cmd_parm->size = 0;
+		pdrvextra_cmd_parm->pbuf = NULL;
+
+		init_h2fwcmd_w_parm_no_rsp(ph2c, pdrvextra_cmd_parm, GEN_CMD_CODE(_Set_Drv_Extra));
+
+		res = rtw_enqueue_cmd(pcmdpriv, ph2c);
+	} else
+		lps_ctrl_wk_hdl(padapter, lps_ctrl_type);
+
+exit:
+
+
+	return res;
+
+}
+
+void rtw_dm_in_lps_hdl(_adapter *padapter)
+{
+	rtw_hal_set_hwreg(padapter, HW_VAR_DM_IN_LPS_LCLK, NULL);
+}
+
+u8 rtw_dm_in_lps_wk_cmd(_adapter *padapter)
+{
+	struct cmd_obj	*ph2c;
+	struct drvextra_cmd_parm	*pdrvextra_cmd_parm;
+	struct cmd_priv	*pcmdpriv = &padapter->cmdpriv;
+	u8	res = _SUCCESS;
+
+
+	ph2c = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj));
+	if (ph2c == NULL) {
+		res = _FAIL;
+		goto exit;
+	}
+
+	pdrvextra_cmd_parm = (struct drvextra_cmd_parm *)rtw_zmalloc(sizeof(struct drvextra_cmd_parm));
+	if (pdrvextra_cmd_parm == NULL) {
+		rtw_mfree((unsigned char *)ph2c, sizeof(struct cmd_obj));
+		res = _FAIL;
+		goto exit;
+	}
+
+	pdrvextra_cmd_parm->ec_id = DM_IN_LPS_WK_CID;
+	pdrvextra_cmd_parm->type = 0;
+	pdrvextra_cmd_parm->size = 0;
+	pdrvextra_cmd_parm->pbuf = NULL;
+
+	init_h2fwcmd_w_parm_no_rsp(ph2c, pdrvextra_cmd_parm, GEN_CMD_CODE(_Set_Drv_Extra));
+
+	res = rtw_enqueue_cmd(pcmdpriv, ph2c);
+
+exit:
+
+	return res;
+
+}
+
+void rtw_lps_change_dtim_hdl(_adapter *padapter, u8 dtim)
+{
+	struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter);
+
+	if (dtim <= 0 || dtim > 16)
+		return;
+
+#ifdef CONFIG_BT_COEXIST
+	if (rtw_btcoex_IsBtControlLps(padapter) == _TRUE)
+		return;
+#endif
+
+#ifdef CONFIG_LPS_LCLK
+	_enter_pwrlock(&pwrpriv->lock);
+#endif
+
+	if (pwrpriv->dtim != dtim) {
+		RTW_INFO("change DTIM from %d to %d, bFwCurrentInPSMode=%d, ps_mode=%d\n", pwrpriv->dtim, dtim,
+			 pwrpriv->bFwCurrentInPSMode, pwrpriv->pwr_mode);
+
+		pwrpriv->dtim = dtim;
+	}
+
+	if ((pwrpriv->bFwCurrentInPSMode == _TRUE) && (pwrpriv->pwr_mode > PS_MODE_ACTIVE)) {
+		u8 ps_mode = pwrpriv->pwr_mode;
+
+		/* RTW_INFO("change DTIM from %d to %d, ps_mode=%d\n", pwrpriv->dtim, dtim, ps_mode); */
+
+		rtw_hal_set_hwreg(padapter, HW_VAR_H2C_FW_PWRMODE, (u8 *)(&ps_mode));
+	}
+
+#ifdef CONFIG_LPS_LCLK
+	_exit_pwrlock(&pwrpriv->lock);
+#endif
+
+}
+
+#endif
+
+u8 rtw_lps_change_dtim_cmd(_adapter *padapter, u8 dtim)
+{
+	struct cmd_obj	*ph2c;
+	struct drvextra_cmd_parm	*pdrvextra_cmd_parm;
+	struct cmd_priv	*pcmdpriv = &padapter->cmdpriv;
+	u8	res = _SUCCESS;
+	/*
+	#ifdef CONFIG_CONCURRENT_MODE
+		if (padapter->hw_port != HW_PORT0)
+			return res;
+	#endif
+	*/
+	{
+		ph2c = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj));
+		if (ph2c == NULL) {
+			res = _FAIL;
+			goto exit;
+		}
+
+		pdrvextra_cmd_parm = (struct drvextra_cmd_parm *)rtw_zmalloc(sizeof(struct drvextra_cmd_parm));
+		if (pdrvextra_cmd_parm == NULL) {
+			rtw_mfree((unsigned char *)ph2c, sizeof(struct cmd_obj));
+			res = _FAIL;
+			goto exit;
+		}
+
+		pdrvextra_cmd_parm->ec_id = LPS_CHANGE_DTIM_CID;
+		pdrvextra_cmd_parm->type = dtim;
+		pdrvextra_cmd_parm->size = 0;
+		pdrvextra_cmd_parm->pbuf = NULL;
+
+		init_h2fwcmd_w_parm_no_rsp(ph2c, pdrvextra_cmd_parm, GEN_CMD_CODE(_Set_Drv_Extra));
+
+		res = rtw_enqueue_cmd(pcmdpriv, ph2c);
+	}
+
+exit:
+
+	return res;
+
+}
+
+#if (RATE_ADAPTIVE_SUPPORT == 1)
+void rpt_timer_setting_wk_hdl(_adapter *padapter, u16 minRptTime)
+{
+	rtw_hal_set_hwreg(padapter, HW_VAR_RPT_TIMER_SETTING, (u8 *)(&minRptTime));
+}
+
+u8 rtw_rpt_timer_cfg_cmd(_adapter *padapter, u16 minRptTime)
+{
+	struct cmd_obj		*ph2c;
+	struct drvextra_cmd_parm	*pdrvextra_cmd_parm;
+	struct cmd_priv	*pcmdpriv = &padapter->cmdpriv;
+
+	u8	res = _SUCCESS;
+
+	ph2c = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj));
+	if (ph2c == NULL) {
+		res = _FAIL;
+		goto exit;
+	}
+
+	pdrvextra_cmd_parm = (struct drvextra_cmd_parm *)rtw_zmalloc(sizeof(struct drvextra_cmd_parm));
+	if (pdrvextra_cmd_parm == NULL) {
+		rtw_mfree((unsigned char *)ph2c, sizeof(struct cmd_obj));
+		res = _FAIL;
+		goto exit;
+	}
+
+	pdrvextra_cmd_parm->ec_id = RTP_TIMER_CFG_WK_CID;
+	pdrvextra_cmd_parm->type = minRptTime;
+	pdrvextra_cmd_parm->size = 0;
+	pdrvextra_cmd_parm->pbuf = NULL;
+	init_h2fwcmd_w_parm_no_rsp(ph2c, pdrvextra_cmd_parm, GEN_CMD_CODE(_Set_Drv_Extra));
+	res = rtw_enqueue_cmd(pcmdpriv, ph2c);
+exit:
+
+
+	return res;
+
+}
+
+#endif
+
+#ifdef CONFIG_ANTENNA_DIVERSITY
+void antenna_select_wk_hdl(_adapter *padapter, u8 antenna)
+{
+	rtw_hal_set_odm_var(padapter, HAL_ODM_ANTDIV_SELECT, &antenna, _TRUE);
+}
+
+u8 rtw_antenna_select_cmd(_adapter *padapter, u8 antenna, u8 enqueue)
+{
+	struct cmd_obj		*ph2c;
+	struct drvextra_cmd_parm	*pdrvextra_cmd_parm;
+	struct cmd_priv	*pcmdpriv = &padapter->cmdpriv;
+	struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
+	u8	bSupportAntDiv = _FALSE;
+	u8	res = _SUCCESS;
+	int	i;
+
+	rtw_hal_get_def_var(padapter, HAL_DEF_IS_SUPPORT_ANT_DIV, &(bSupportAntDiv));
+	if (_FALSE == bSupportAntDiv)
+		return _FAIL;
+
+	for (i = 0; i < dvobj->iface_nums; i++) {
+		if (rtw_linked_check(dvobj->padapters[i]))
+			return _FAIL;
+	}
+
+	if (_TRUE == enqueue) {
+		ph2c = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj));
+		if (ph2c == NULL) {
+			res = _FAIL;
+			goto exit;
+		}
+
+		pdrvextra_cmd_parm = (struct drvextra_cmd_parm *)rtw_zmalloc(sizeof(struct drvextra_cmd_parm));
+		if (pdrvextra_cmd_parm == NULL) {
+			rtw_mfree((unsigned char *)ph2c, sizeof(struct cmd_obj));
+			res = _FAIL;
+			goto exit;
+		}
+
+		pdrvextra_cmd_parm->ec_id = ANT_SELECT_WK_CID;
+		pdrvextra_cmd_parm->type = antenna;
+		pdrvextra_cmd_parm->size = 0;
+		pdrvextra_cmd_parm->pbuf = NULL;
+		init_h2fwcmd_w_parm_no_rsp(ph2c, pdrvextra_cmd_parm, GEN_CMD_CODE(_Set_Drv_Extra));
+
+		res = rtw_enqueue_cmd(pcmdpriv, ph2c);
+	} else
+		antenna_select_wk_hdl(padapter, antenna);
+exit:
+
+
+	return res;
+
+}
+#endif
+
+void rtw_dm_ra_mask_hdl(_adapter *padapter, struct sta_info *psta)
+{
+	if (psta)
+		set_sta_rate(padapter, psta);
+}
+
+u8 rtw_dm_ra_mask_wk_cmd(_adapter *padapter, u8 *psta)
+{
+	struct cmd_obj	*ph2c;
+	struct drvextra_cmd_parm	*pdrvextra_cmd_parm;
+	struct cmd_priv	*pcmdpriv = &padapter->cmdpriv;
+	u8	res = _SUCCESS;
+
+
+	ph2c = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj));
+	if (ph2c == NULL) {
+		res = _FAIL;
+		goto exit;
+	}
+
+	pdrvextra_cmd_parm = (struct drvextra_cmd_parm *)rtw_zmalloc(sizeof(struct drvextra_cmd_parm));
+	if (pdrvextra_cmd_parm == NULL) {
+		rtw_mfree((unsigned char *)ph2c, sizeof(struct cmd_obj));
+		res = _FAIL;
+		goto exit;
+	}
+
+	pdrvextra_cmd_parm->ec_id = DM_RA_MSK_WK_CID;
+	pdrvextra_cmd_parm->type = 0;
+	pdrvextra_cmd_parm->size = 0;
+	pdrvextra_cmd_parm->pbuf = psta;
+
+	init_h2fwcmd_w_parm_no_rsp(ph2c, pdrvextra_cmd_parm, GEN_CMD_CODE(_Set_Drv_Extra));
+
+	res = rtw_enqueue_cmd(pcmdpriv, ph2c);
+
+exit:
+
+	return res;
+
+}
+
+void power_saving_wk_hdl(_adapter *padapter)
+{
+	rtw_ps_processor(padapter);
+}
+
+/* add for CONFIG_IEEE80211W, none 11w can use it */
+void reset_securitypriv_hdl(_adapter *padapter)
+{
+	rtw_reset_securitypriv(padapter);
+}
+
+#ifdef CONFIG_P2P
+u8 p2p_protocol_wk_cmd(_adapter *padapter, int intCmdType)
+{
+	struct cmd_obj	*ph2c;
+	struct drvextra_cmd_parm	*pdrvextra_cmd_parm;
+	struct wifidirect_info	*pwdinfo = &(padapter->wdinfo);
+	struct cmd_priv	*pcmdpriv = &padapter->cmdpriv;
+	u8	res = _SUCCESS;
+
+
+	if (rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE))
+		return res;
+
+	ph2c = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj));
+	if (ph2c == NULL) {
+		res = _FAIL;
+		goto exit;
+	}
+
+	pdrvextra_cmd_parm = (struct drvextra_cmd_parm *)rtw_zmalloc(sizeof(struct drvextra_cmd_parm));
+	if (pdrvextra_cmd_parm == NULL) {
+		rtw_mfree((unsigned char *)ph2c, sizeof(struct cmd_obj));
+		res = _FAIL;
+		goto exit;
+	}
+
+	pdrvextra_cmd_parm->ec_id = P2P_PROTO_WK_CID;
+	pdrvextra_cmd_parm->type = intCmdType;	/*	As the command tppe. */
+	pdrvextra_cmd_parm->size = 0;
+	pdrvextra_cmd_parm->pbuf = NULL;		/*	Must be NULL here */
+
+	init_h2fwcmd_w_parm_no_rsp(ph2c, pdrvextra_cmd_parm, GEN_CMD_CODE(_Set_Drv_Extra));
+
+	res = rtw_enqueue_cmd(pcmdpriv, ph2c);
+
+exit:
+
+
+	return res;
+
+}
+
+#ifdef CONFIG_IOCTL_CFG80211
+static u8 _p2p_roch_cmd(_adapter *adapter
+	, u64 cookie, struct wireless_dev *wdev
+	, struct ieee80211_channel *ch, enum nl80211_channel_type ch_type
+	, unsigned int duration
+	, u8 flags
+)
+{
+	struct cmd_obj *cmdobj;
+	struct drvextra_cmd_parm *parm;
+	struct p2p_roch_parm *roch_parm;
+	struct cmd_priv *pcmdpriv = &adapter->cmdpriv;
+	struct submit_ctx sctx;
+	u8 cancel = duration ? 0 : 1;
+	u8	res = _SUCCESS;
+
+	roch_parm = (struct p2p_roch_parm *)rtw_zmalloc(sizeof(struct p2p_roch_parm));
+	if (roch_parm == NULL) {
+		res = _FAIL;
+		goto exit;
+	}
+
+	roch_parm->cookie = cookie;
+	roch_parm->wdev = wdev;
+	if (!cancel) {
+		_rtw_memcpy(&roch_parm->ch, ch, sizeof(struct ieee80211_channel));
+		roch_parm->ch_type = ch_type;
+		roch_parm->duration = duration;
+	}
+
+	if (flags & RTW_CMDF_DIRECTLY) {
+		/* no need to enqueue, do the cmd hdl directly and free cmd parameter */
+		if (H2C_SUCCESS != p2p_protocol_wk_hdl(adapter, cancel ? P2P_CANCEL_RO_CH_WK : P2P_RO_CH_WK, (u8 *)roch_parm))
+			res = _FAIL;
+		rtw_mfree((u8 *)roch_parm, sizeof(*roch_parm));
+	} else {
+		/* need enqueue, prepare cmd_obj and enqueue */
+		parm = (struct drvextra_cmd_parm *)rtw_zmalloc(sizeof(struct drvextra_cmd_parm));
+		if (parm == NULL) {
+			rtw_mfree((u8 *)roch_parm, sizeof(*roch_parm));
+			res = _FAIL;
+			goto exit;
+		}
+
+		parm->ec_id = P2P_PROTO_WK_CID;
+		parm->type = cancel ? P2P_CANCEL_RO_CH_WK : P2P_RO_CH_WK;
+		parm->size = sizeof(*roch_parm);
+		parm->pbuf = (u8 *)roch_parm;
+
+		cmdobj = (struct cmd_obj *)rtw_zmalloc(sizeof(*cmdobj));
+		if (cmdobj == NULL) {
+			res = _FAIL;
+			rtw_mfree((u8 *)roch_parm, sizeof(*roch_parm));
+			rtw_mfree((u8 *)parm, sizeof(*parm));
+			goto exit;
+		}
+
+		init_h2fwcmd_w_parm_no_rsp(cmdobj, parm, GEN_CMD_CODE(_Set_Drv_Extra));
+
+		if (flags & RTW_CMDF_WAIT_ACK) {
+			cmdobj->sctx = &sctx;
+			rtw_sctx_init(&sctx, 10 * 1000);
+		}
+
+		res = rtw_enqueue_cmd(pcmdpriv, cmdobj);
+
+		if (res == _SUCCESS && (flags & RTW_CMDF_WAIT_ACK)) {
+			rtw_sctx_wait(&sctx, __func__);
+			_enter_critical_mutex(&pcmdpriv->sctx_mutex, NULL);
+			if (sctx.status == RTW_SCTX_SUBMITTED)
+				cmdobj->sctx = NULL;
+			_exit_critical_mutex(&pcmdpriv->sctx_mutex, NULL);
+			if (sctx.status != RTW_SCTX_DONE_SUCCESS)
+				res = _FAIL;
+		}
+	}
+
+exit:
+	return res;
+}
+
+inline u8 p2p_roch_cmd(_adapter *adapter
+	, u64 cookie, struct wireless_dev *wdev
+	, struct ieee80211_channel *ch, enum nl80211_channel_type ch_type
+	, unsigned int duration
+	, u8 flags
+)
+{
+	return _p2p_roch_cmd(adapter, cookie, wdev, ch, ch_type, duration, flags);
+}
+
+inline u8 p2p_cancel_roch_cmd(_adapter *adapter, u64 cookie, struct wireless_dev *wdev, u8 flags)
+{
+	return _p2p_roch_cmd(adapter, cookie, wdev, NULL, 0, 0, flags);
+}
+
+#endif /* CONFIG_IOCTL_CFG80211 */
+#endif /* CONFIG_P2P */
+
+#ifdef CONFIG_IOCTL_CFG80211 
+inline u8 rtw_mgnt_tx_cmd(_adapter *adapter, u8 tx_ch, u8 no_cck, const u8 *buf, size_t len, int wait_ack, u8 flags)
+{
+	struct cmd_obj *cmdobj;
+	struct drvextra_cmd_parm *parm;
+	struct mgnt_tx_parm *mgnt_parm;
+	struct cmd_priv *pcmdpriv = &adapter->cmdpriv;
+	struct submit_ctx sctx;
+	u8	res = _SUCCESS;
+
+	mgnt_parm = (struct mgnt_tx_parm *)rtw_zmalloc(sizeof(struct mgnt_tx_parm));
+	if (mgnt_parm == NULL) {
+		res = _FAIL;
+			goto exit;
+	}
+
+	mgnt_parm->tx_ch = tx_ch;
+	mgnt_parm->no_cck = no_cck;
+	mgnt_parm->buf = buf;
+	mgnt_parm->len = len;
+	mgnt_parm->wait_ack = wait_ack;
+
+	if (flags & RTW_CMDF_DIRECTLY) {
+		/* no need to enqueue, do the cmd hdl directly and free cmd parameter */
+		if (H2C_SUCCESS != rtw_mgnt_tx_handler(adapter, (u8 *)mgnt_parm))
+			res = _FAIL;
+		rtw_mfree((u8 *)mgnt_parm, sizeof(*mgnt_parm));
+	} else {
+		/* need enqueue, prepare cmd_obj and enqueue */
+		parm = (struct drvextra_cmd_parm *)rtw_zmalloc(sizeof(struct drvextra_cmd_parm));
+		if (parm == NULL) {
+			rtw_mfree((u8 *)mgnt_parm, sizeof(*mgnt_parm));
+			res = _FAIL;
+			goto exit;
+		}
+
+		parm->ec_id = MGNT_TX_WK_CID;
+		parm->type = 0;
+		parm->size = sizeof(*mgnt_parm);
+		parm->pbuf = (u8 *)mgnt_parm;
+
+		cmdobj = (struct cmd_obj *)rtw_zmalloc(sizeof(*cmdobj));
+		if (cmdobj == NULL) {
+			res = _FAIL;
+			rtw_mfree((u8 *)mgnt_parm, sizeof(*mgnt_parm));
+			rtw_mfree((u8 *)parm, sizeof(*parm));
+			goto exit;
+		}
+
+		init_h2fwcmd_w_parm_no_rsp(cmdobj, parm, GEN_CMD_CODE(_Set_Drv_Extra));
+
+		if (flags & RTW_CMDF_WAIT_ACK) {
+			cmdobj->sctx = &sctx;
+			rtw_sctx_init(&sctx, 10 * 1000);
+		}
+
+		res = rtw_enqueue_cmd(pcmdpriv, cmdobj);
+
+		if (res == _SUCCESS && (flags & RTW_CMDF_WAIT_ACK)) {
+			rtw_sctx_wait(&sctx, __func__);
+			_enter_critical_mutex(&pcmdpriv->sctx_mutex, NULL);
+			if (sctx.status == RTW_SCTX_SUBMITTED)
+				cmdobj->sctx = NULL;
+			_exit_critical_mutex(&pcmdpriv->sctx_mutex, NULL);
+			if (sctx.status != RTW_SCTX_DONE_SUCCESS)
+				res = _FAIL;
+		}
+	}
+
+exit:
+	return res;
+}
+#endif
+
+u8 rtw_ps_cmd(_adapter *padapter)
+{
+	struct cmd_obj		*ppscmd;
+	struct drvextra_cmd_parm	*pdrvextra_cmd_parm;
+	struct cmd_priv	*pcmdpriv = &padapter->cmdpriv;
+
+	u8	res = _SUCCESS;
+
+#ifdef CONFIG_CONCURRENT_MODE
+	if (!is_primary_adapter(padapter))
+		goto exit;
+#endif
+
+	ppscmd = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj));
+	if (ppscmd == NULL) {
+		res = _FAIL;
+		goto exit;
+	}
+
+	pdrvextra_cmd_parm = (struct drvextra_cmd_parm *)rtw_zmalloc(sizeof(struct drvextra_cmd_parm));
+	if (pdrvextra_cmd_parm == NULL) {
+		rtw_mfree((unsigned char *)ppscmd, sizeof(struct cmd_obj));
+		res = _FAIL;
+		goto exit;
+	}
+
+	pdrvextra_cmd_parm->ec_id = POWER_SAVING_CTRL_WK_CID;
+	pdrvextra_cmd_parm->type = 0;
+	pdrvextra_cmd_parm->size = 0;
+	pdrvextra_cmd_parm->pbuf = NULL;
+	init_h2fwcmd_w_parm_no_rsp(ppscmd, pdrvextra_cmd_parm, GEN_CMD_CODE(_Set_Drv_Extra));
+
+	res = rtw_enqueue_cmd(pcmdpriv, ppscmd);
+
+exit:
+
+
+	return res;
+
+}
+
+#ifdef CONFIG_DFS
+void rtw_dfs_ch_switch_hdl(struct dvobj_priv *dvobj)
+{
+	struct rf_ctl_t *rfctl = dvobj_to_rfctl(dvobj);
+	_adapter *pri_adapter = dvobj_get_primary_adapter(dvobj);
+	u8 ifbmp_m = rtw_mi_get_ap_mesh_ifbmp(pri_adapter);
+	u8 ifbmp_s = rtw_mi_get_ld_sta_ifbmp(pri_adapter);
+	s16 req_ch;
+
+	rtw_hal_macid_sleep_all_used(pri_adapter);
+
+	if (rtw_chset_search_ch(rfctl->channel_set, rfctl->csa_ch) >= 0
+		&& !rtw_chset_is_ch_non_ocp(rfctl->channel_set, rfctl->csa_ch)
+	) {
+		/* CSA channel available and valid */
+		req_ch = rfctl->csa_ch;
+		RTW_INFO("%s valid CSA ch%u\n", __func__, rfctl->csa_ch);
+	} else if (ifbmp_m) {
+		/* no available or valid CSA channel, having AP/MESH ifaces */
+		req_ch = REQ_CH_NONE;
+		RTW_INFO("%s ch sel by AP/MESH ifaces\n", __func__);
+	} else {
+		/* no available or valid CSA channel and no AP/MESH ifaces */
+		if (!IsSupported24G(dvobj_to_regsty(dvobj)->wireless_mode)
+			#ifdef CONFIG_DFS_MASTER
+			|| rfctl->radar_detected
+			#endif
+		)
+			req_ch = 36;
+		else
+			req_ch = 1;
+		RTW_INFO("%s switch to ch%d\n", __func__, req_ch);
+	}
+
+	/*  issue deauth for all asoc STA ifaces */
+	if (ifbmp_s) {
+		_adapter *iface;
+		int i;
+
+		for (i = 0; i < dvobj->iface_nums; i++) {
+			iface = dvobj->padapters[i];
+			if (!iface || !(ifbmp_s & BIT(iface->iface_id)))
+				continue;
+			set_fwstate(&iface->mlmepriv, WIFI_OP_CH_SWITCHING);
+
+			/* TODO: true op ch switching */
+			issue_deauth(iface, get_bssid(&iface->mlmepriv), WLAN_REASON_DEAUTH_LEAVING);
+		}
+	}
+
+#ifdef CONFIG_AP_MODE
+	if (ifbmp_m) {
+		/* trigger channel selection without consideraton of asoc STA ifaces */
+		rtw_change_bss_chbw_cmd(dvobj_get_primary_adapter(dvobj), RTW_CMDF_DIRECTLY
+			, ifbmp_m, ifbmp_s, req_ch, REQ_BW_ORI, REQ_OFFSET_NONE);
+	} else
+#endif
+	{
+		/* no AP/MESH iface, switch DFS status and channel directly */
+		rtw_warn_on(req_ch <= 0);
+		#ifdef CONFIG_DFS_MASTER
+		rtw_dfs_rd_en_decision(pri_adapter, MLME_OPCH_SWITCH, ifbmp_s);
+		#endif
+		set_channel_bwmode(pri_adapter, req_ch, HAL_PRIME_CHNL_OFFSET_DONT_CARE, CHANNEL_WIDTH_20);
+	}
+
+	/* make asoc STA ifaces disconnect */
+	/* TODO: true op ch switching */
+	if (ifbmp_s) {
+		_adapter *iface;
+		int i;
+	
+		for (i = 0; i < dvobj->iface_nums; i++) {
+			iface = dvobj->padapters[i];
+			if (!iface || !(ifbmp_s & BIT(iface->iface_id)))
+				continue;
+			rtw_disassoc_cmd(iface, 0, RTW_CMDF_DIRECTLY);
+			rtw_indicate_disconnect(iface, 0, _FALSE);
+			rtw_free_assoc_resources(iface, _TRUE);
+			rtw_free_network_queue(iface, _TRUE);
+		}
+	}
+
+	rfctl->csa_ch = 0;
+
+	rtw_hal_macid_wakeup_all_used(pri_adapter);
+	rtw_mi_os_xmit_schedule(pri_adapter);
+}
+#endif /* CONFIG_DFS */
+
+#ifdef CONFIG_AP_MODE
+
+static void rtw_chk_hi_queue_hdl(_adapter *padapter)
+{
+	struct sta_info *psta_bmc;
+	struct sta_priv *pstapriv = &padapter->stapriv;
+	systime start = rtw_get_current_time();
+	u8 empty = _FALSE;
+
+	psta_bmc = rtw_get_bcmc_stainfo(padapter);
+	if (!psta_bmc)
+		return;
+
+	rtw_hal_get_hwreg(padapter, HW_VAR_CHK_HI_QUEUE_EMPTY, &empty);
+
+	while (_FALSE == empty && rtw_get_passing_time_ms(start) < rtw_get_wait_hiq_empty_ms()) {
+		rtw_msleep_os(100);
+		rtw_hal_get_hwreg(padapter, HW_VAR_CHK_HI_QUEUE_EMPTY, &empty);
+	}
+
+	if (psta_bmc->sleepq_len == 0) {
+		if (empty == _SUCCESS) {
+			bool update_tim = _FALSE;
+
+			if (rtw_tim_map_is_set(padapter, pstapriv->tim_bitmap, 0))
+				update_tim = _TRUE;
+
+			rtw_tim_map_clear(padapter, pstapriv->tim_bitmap, 0);
+			rtw_tim_map_clear(padapter, pstapriv->sta_dz_bitmap, 0);
+
+			if (update_tim == _TRUE)
+				_update_beacon(padapter, _TIM_IE_, NULL, _TRUE, "bmc sleepq and HIQ empty");
+		} else /* re check again */
+			rtw_chk_hi_queue_cmd(padapter);
+
+	}
+
+}
+
+u8 rtw_chk_hi_queue_cmd(_adapter *padapter)
+{
+	struct cmd_obj	*ph2c;
+	struct drvextra_cmd_parm	*pdrvextra_cmd_parm;
+	struct cmd_priv	*pcmdpriv = &padapter->cmdpriv;
+	u8	res = _SUCCESS;
+
+	ph2c = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj));
+	if (ph2c == NULL) {
+		res = _FAIL;
+		goto exit;
+	}
+
+	pdrvextra_cmd_parm = (struct drvextra_cmd_parm *)rtw_zmalloc(sizeof(struct drvextra_cmd_parm));
+	if (pdrvextra_cmd_parm == NULL) {
+		rtw_mfree((unsigned char *)ph2c, sizeof(struct cmd_obj));
+		res = _FAIL;
+		goto exit;
+	}
+
+	pdrvextra_cmd_parm->ec_id = CHECK_HIQ_WK_CID;
+	pdrvextra_cmd_parm->type = 0;
+	pdrvextra_cmd_parm->size = 0;
+	pdrvextra_cmd_parm->pbuf = NULL;
+
+	init_h2fwcmd_w_parm_no_rsp(ph2c, pdrvextra_cmd_parm, GEN_CMD_CODE(_Set_Drv_Extra));
+
+	res = rtw_enqueue_cmd(pcmdpriv, ph2c);
+
+exit:
+
+	return res;
+
+}
+
+#ifdef CONFIG_DFS_MASTER
+u8 rtw_dfs_rd_hdl(_adapter *adapter)
+{
+	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
+	struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter);
+
+	if (!rfctl->radar_detect_enabled)
+		goto exit;
+
+	if (dvobj->oper_channel != rfctl->radar_detect_ch
+		|| rtw_get_passing_time_ms(rtw_get_on_oper_ch_time(adapter)) < 300
+	) {
+		/* offchannel, bypass radar detect */
+		goto cac_status_chk;
+	}
+
+	if (IS_CH_WAITING(rfctl) && !IS_UNDER_CAC(rfctl)) {
+		/* non_ocp, bypass radar detect */
+		goto cac_status_chk;
+	}
+
+	if (!rfctl->dbg_dfs_fake_radar_detect_cnt
+		&& rtw_odm_radar_detect(adapter) != _TRUE)
+		goto cac_status_chk;
+
+	if (!rfctl->dbg_dfs_fake_radar_detect_cnt
+		&& rfctl->dbg_dfs_radar_detect_trigger_non
+	) {
+		/* radar detect debug mode, trigger no mlme flow */
+		RTW_INFO("%s radar detected on test mode, trigger no mlme flow\n", __func__);
+		goto cac_status_chk;
+	}
+
+	if (rfctl->dbg_dfs_fake_radar_detect_cnt != 0) {
+		RTW_INFO("%s fake radar detected, cnt:%d\n", __func__
+			, rfctl->dbg_dfs_fake_radar_detect_cnt);
+		rfctl->dbg_dfs_fake_radar_detect_cnt--;
+	} else
+		RTW_INFO("%s radar detected\n", __func__);
+
+	rfctl->radar_detected = 1;
+
+	rtw_chset_update_non_ocp(rfctl->channel_set
+		, rfctl->radar_detect_ch, rfctl->radar_detect_bw, rfctl->radar_detect_offset);
+
+	rtw_dfs_ch_switch_hdl(dvobj);
+
+	if (rfctl->radar_detect_enabled)
+		goto set_timer;
+	goto exit;
+
+cac_status_chk:
+
+	if (!IS_CAC_STOPPED(rfctl)
+		&& ((IS_UNDER_CAC(rfctl) && rfctl->cac_force_stop)
+			|| !IS_CH_WAITING(rfctl)
+			)
+	) {
+		u8 pause = 0x00;
+
+		rtw_hal_set_hwreg(adapter, HW_VAR_TXPAUSE, &pause);
+		rfctl->cac_start_time = rfctl->cac_end_time = RTW_CAC_STOPPED;
+
+		if (rtw_mi_check_fwstate(adapter, WIFI_UNDER_LINKING|WIFI_SITE_MONITOR) == _FALSE) {
+			u8 doiqk = _TRUE;
+			u8 u_ch, u_bw, u_offset;
+
+			rtw_hal_set_hwreg(adapter , HW_VAR_DO_IQK , &doiqk);
+
+			if (rtw_mi_get_ch_setting_union(adapter, &u_ch, &u_bw, &u_offset))
+				set_channel_bwmode(adapter, u_ch, u_offset, u_bw);
+			else
+				rtw_warn_on(1);
+
+			doiqk = _FALSE;
+			rtw_hal_set_hwreg(adapter , HW_VAR_DO_IQK , &doiqk);
+
+			ResumeTxBeacon(adapter);
+			rtw_mi_tx_beacon_hdl(adapter);
+		}
+	}
+
+set_timer:
+	_set_timer(&rfctl->radar_detect_timer
+		, rtw_odm_radar_detect_polling_int_ms(dvobj));
+
+exit:
+	return H2C_SUCCESS;
+}
+
+u8 rtw_dfs_rd_cmd(_adapter *adapter, bool enqueue)
+{
+	struct cmd_obj *cmdobj;
+	struct drvextra_cmd_parm *parm;
+	struct cmd_priv *cmdpriv = &adapter->cmdpriv;
+	u8 res = _FAIL;
+
+	if (enqueue) {
+		cmdobj = rtw_zmalloc(sizeof(struct cmd_obj));
+		if (cmdobj == NULL)
+			goto exit;
+
+		parm = rtw_zmalloc(sizeof(struct drvextra_cmd_parm));
+		if (parm == NULL) {
+			rtw_mfree(cmdobj, sizeof(struct cmd_obj));
+			goto exit;
+		}
+
+		parm->ec_id = DFS_RADAR_DETECT_WK_CID;
+		parm->type = 0;
+		parm->size = 0;
+		parm->pbuf = NULL;
+
+		init_h2fwcmd_w_parm_no_rsp(cmdobj, parm, GEN_CMD_CODE(_Set_Drv_Extra));
+		res = rtw_enqueue_cmd(cmdpriv, cmdobj);
+	} else {
+		rtw_dfs_rd_hdl(adapter);
+		res = _SUCCESS;
+	}
+
+exit:
+	return res;
+}
+
+void rtw_dfs_rd_timer_hdl(void *ctx)
+{
+	struct rf_ctl_t *rfctl = (struct rf_ctl_t *)ctx;
+	struct dvobj_priv *dvobj = rfctl_to_dvobj(rfctl);
+
+	rtw_dfs_rd_cmd(dvobj_get_primary_adapter(dvobj), _TRUE);
+}
+
+static void rtw_dfs_rd_enable(struct rf_ctl_t *rfctl, u8 ch, u8 bw, u8 offset, bool bypass_cac)
+{
+	struct dvobj_priv *dvobj = rfctl_to_dvobj(rfctl);
+	_adapter *adapter = dvobj_get_primary_adapter(dvobj);
+
+	RTW_INFO("%s on %u,%u,%u\n", __func__, ch, bw, offset);
+
+	if (bypass_cac)
+		rfctl->cac_start_time = rfctl->cac_end_time = RTW_CAC_STOPPED;
+	else if (rtw_is_cac_reset_needed(rfctl, ch, bw, offset) == _TRUE)
+		rtw_reset_cac(rfctl, ch, bw, offset);
+
+	rfctl->radar_detect_by_others = _FALSE;
+	rfctl->radar_detect_ch = ch;
+	rfctl->radar_detect_bw = bw;
+	rfctl->radar_detect_offset = offset;
+
+	rfctl->radar_detected = 0;
+
+	if (IS_CH_WAITING(rfctl))
+		StopTxBeacon(adapter);
+
+	if (!rfctl->radar_detect_enabled) {
+		RTW_INFO("%s set radar_detect_enabled\n", __func__);
+		rfctl->radar_detect_enabled = 1;
+		#ifdef CONFIG_LPS
+		LPS_Leave(adapter, "RADAR_DETECT_EN");
+		#endif
+		_set_timer(&rfctl->radar_detect_timer
+			, rtw_odm_radar_detect_polling_int_ms(dvobj));
+
+		if (rtw_rfctl_overlap_radar_detect_ch(rfctl)) {
+			if (IS_CH_WAITING(rfctl)) {
+				u8 pause = 0xFF;
+
+				rtw_hal_set_hwreg(adapter, HW_VAR_TXPAUSE, &pause);
+			}
+			rtw_odm_radar_detect_enable(adapter);
+		}
+	}
+}
+
+static void rtw_dfs_rd_disable(struct rf_ctl_t *rfctl, u8 ch, u8 bw, u8 offset, bool by_others)
+{
+	_adapter *adapter = dvobj_get_primary_adapter(rfctl_to_dvobj(rfctl));
+
+	rfctl->radar_detect_by_others = by_others;
+
+	if (rfctl->radar_detect_enabled) {
+		bool overlap_radar_detect_ch = rtw_rfctl_overlap_radar_detect_ch(rfctl);
+
+		RTW_INFO("%s clear radar_detect_enabled\n", __func__);
+
+		rfctl->radar_detect_enabled = 0;
+		rfctl->radar_detected = 0;
+		rfctl->radar_detect_ch = 0;
+		rfctl->radar_detect_bw = 0;
+		rfctl->radar_detect_offset = 0;
+		rfctl->cac_start_time = rfctl->cac_end_time = RTW_CAC_STOPPED;
+		_cancel_timer_ex(&rfctl->radar_detect_timer);
+
+		if (rtw_mi_check_fwstate(adapter, WIFI_UNDER_LINKING|WIFI_SITE_MONITOR) == _FALSE) {
+			ResumeTxBeacon(adapter);
+			rtw_mi_tx_beacon_hdl(adapter);
+		}
+
+		if (overlap_radar_detect_ch) {
+			u8 pause = 0x00;
+
+			rtw_hal_set_hwreg(adapter, HW_VAR_TXPAUSE, &pause);
+			rtw_odm_radar_detect_disable(adapter);
+		}
+	}
+
+	if (by_others) {
+		rfctl->radar_detect_ch = ch;
+		rfctl->radar_detect_bw = bw;
+		rfctl->radar_detect_offset = offset;
+	}
+}
+
+void rtw_dfs_rd_en_decision(_adapter *adapter, u8 mlme_act, u8 excl_ifbmp)
+{
+	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
+	struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter);
+	struct mlme_ext_priv *mlmeext = &adapter->mlmeextpriv;
+	struct mi_state mstate;
+	u8 ifbmp;
+	u8 u_ch, u_bw, u_offset;
+	bool ld_sta_in_dfs = _FALSE;
+	bool sync_ch = _FALSE; /* _FALSE: asign channel directly */
+	bool needed = _FALSE;
+
+	if (mlme_act == MLME_OPCH_SWITCH
+		|| mlme_act == MLME_ACTION_NONE
+	) {
+		ifbmp = ~excl_ifbmp;
+		rtw_mi_status_by_ifbmp(dvobj, ifbmp, &mstate);
+		rtw_mi_get_ch_setting_union_by_ifbmp(dvobj, ifbmp, &u_ch, &u_bw, &u_offset);
+	} else {
+		ifbmp = ~excl_ifbmp & ~BIT(adapter->iface_id);
+		rtw_mi_status_by_ifbmp(dvobj, ifbmp, &mstate);
+		rtw_mi_get_ch_setting_union_by_ifbmp(dvobj, ifbmp, &u_ch, &u_bw, &u_offset);
+		if (u_ch != 0)
+			sync_ch = _TRUE;
+
+		switch (mlme_act) {
+		case MLME_STA_CONNECTING:
+			MSTATE_STA_LG_NUM(&mstate)++;
+			break;
+		case MLME_STA_CONNECTED:
+			MSTATE_STA_LD_NUM(&mstate)++;
+			break;
+		case MLME_STA_DISCONNECTED:
+			break;
+#ifdef CONFIG_AP_MODE
+		case MLME_AP_STARTED:
+			MSTATE_AP_NUM(&mstate)++;
+			break;
+		case MLME_AP_STOPPED:
+			break;
+#endif
+#ifdef CONFIG_RTW_MESH
+		case MLME_MESH_STARTED:
+			MSTATE_MESH_NUM(&mstate)++;
+			break;
+		case MLME_MESH_STOPPED:
+			break;
+#endif
+		default:
+			rtw_warn_on(1);
+			break;
+		}
+
+		if (sync_ch == _TRUE) {
+			if (!MLME_IS_OPCH_SW(adapter)) {
+				if (!rtw_is_chbw_grouped(mlmeext->cur_channel, mlmeext->cur_bwmode, mlmeext->cur_ch_offset, u_ch, u_bw, u_offset)) {
+					RTW_INFO(FUNC_ADPT_FMT" can't sync %u,%u,%u with %u,%u,%u\n", FUNC_ADPT_ARG(adapter)
+						, mlmeext->cur_channel, mlmeext->cur_bwmode, mlmeext->cur_ch_offset, u_ch, u_bw, u_offset);
+					goto apply;
+				}
+
+				rtw_sync_chbw(&mlmeext->cur_channel, &mlmeext->cur_bwmode, &mlmeext->cur_ch_offset
+					, &u_ch, &u_bw, &u_offset);
+			}
+		} else {
+			u_ch = mlmeext->cur_channel;
+			u_bw = mlmeext->cur_bwmode;
+			u_offset = mlmeext->cur_ch_offset;
+		}
+	}
+
+	if (MSTATE_STA_LG_NUM(&mstate) > 0) {
+		/* STA mode is linking */
+		goto apply;
+	}
+
+	if (MSTATE_STA_LD_NUM(&mstate) > 0) {
+		if (rtw_is_dfs_chbw(u_ch, u_bw, u_offset)) {
+			/*
+			* if operate as slave w/o radar detect,
+			* rely on AP on which STA mode connects
+			*/
+			if (IS_DFS_SLAVE_WITH_RD(rfctl) && !rtw_odm_dfs_domain_unknown(dvobj))
+				needed = _TRUE;
+			ld_sta_in_dfs = _TRUE;
+		}
+		goto apply;
+	}
+
+	if (!MSTATE_AP_NUM(&mstate) && !MSTATE_MESH_NUM(&mstate)) {
+		/* No working AP/Mesh mode */
+		goto apply;
+	}
+
+	if (rtw_is_dfs_chbw(u_ch, u_bw, u_offset))
+		needed = _TRUE;
+
+apply:
+
+	RTW_INFO(FUNC_ADPT_FMT" needed:%d, mlme_act:%u, excl_ifbmp:0x%02x\n"
+		, FUNC_ADPT_ARG(adapter), needed, mlme_act, excl_ifbmp);
+	RTW_INFO(FUNC_ADPT_FMT" ld_sta_num:%u, lg_sta_num:%u, ap_num:%u, mesh_num:%u, %u,%u,%u\n"
+		, FUNC_ADPT_ARG(adapter), MSTATE_STA_LD_NUM(&mstate), MSTATE_STA_LG_NUM(&mstate)
+		, MSTATE_AP_NUM(&mstate), MSTATE_MESH_NUM(&mstate)
+		, u_ch, u_bw, u_offset);
+
+	if (needed == _TRUE)
+		rtw_dfs_rd_enable(rfctl, u_ch, u_bw, u_offset, ld_sta_in_dfs);
+	else
+		rtw_dfs_rd_disable(rfctl, u_ch, u_bw, u_offset, ld_sta_in_dfs);
+}
+
+u8 rtw_dfs_rd_en_decision_cmd(_adapter *adapter)
+{
+	struct cmd_obj *cmdobj;
+	struct drvextra_cmd_parm *parm;
+	struct cmd_priv *cmdpriv = &adapter->cmdpriv;
+	u8 res = _FAIL;
+
+	cmdobj = rtw_zmalloc(sizeof(struct cmd_obj));
+	if (cmdobj == NULL)
+		goto exit;
+
+	parm = rtw_zmalloc(sizeof(struct drvextra_cmd_parm));
+	if (parm == NULL) {
+		rtw_mfree(cmdobj, sizeof(struct cmd_obj));
+		goto exit;
+	}
+
+	parm->ec_id = DFS_RADAR_DETECT_EN_DEC_WK_CID;
+	parm->type = 0;
+	parm->size = 0;
+	parm->pbuf = NULL;
+
+	init_h2fwcmd_w_parm_no_rsp(cmdobj, parm, GEN_CMD_CODE(_Set_Drv_Extra));
+	res = rtw_enqueue_cmd(cmdpriv, cmdobj);
+
+exit:
+	return res;
+}
+#endif /* CONFIG_DFS_MASTER */
+
+#endif /* CONFIG_AP_MODE */
+
+#ifdef CONFIG_BT_COEXIST
+struct btinfo {
+	u8 cid;
+	u8 len;
+
+	u8 bConnection:1;
+	u8 bSCOeSCO:1;
+	u8 bInQPage:1;
+	u8 bACLBusy:1;
+	u8 bSCOBusy:1;
+	u8 bHID:1;
+	u8 bA2DP:1;
+	u8 bFTP:1;
+
+	u8 retry_cnt:4;
+	u8 rsvd_34:1;
+	u8 rsvd_35:1;
+	u8 rsvd_36:1;
+	u8 rsvd_37:1;
+
+	u8 rssi;
+
+	u8 rsvd_50:1;
+	u8 rsvd_51:1;
+	u8 rsvd_52:1;
+	u8 rsvd_53:1;
+	u8 rsvd_54:1;
+	u8 rsvd_55:1;
+	u8 eSCO_SCO:1;
+	u8 Master_Slave:1;
+
+	u8 rsvd_6;
+	u8 rsvd_7;
+};
+
+void btinfo_evt_dump(void *sel, void *buf)
+{
+	struct btinfo *info = (struct btinfo *)buf;
+
+	RTW_PRINT_SEL(sel, "cid:0x%02x, len:%u\n", info->cid, info->len);
+
+	if (info->len > 2)
+		RTW_PRINT_SEL(sel, "byte2:%s%s%s%s%s%s%s%s\n"
+			      , info->bConnection ? "bConnection " : ""
+			      , info->bSCOeSCO ? "bSCOeSCO " : ""
+			      , info->bInQPage ? "bInQPage " : ""
+			      , info->bACLBusy ? "bACLBusy " : ""
+			      , info->bSCOBusy ? "bSCOBusy " : ""
+			      , info->bHID ? "bHID " : ""
+			      , info->bA2DP ? "bA2DP " : ""
+			      , info->bFTP ? "bFTP" : ""
+			     );
+
+	if (info->len > 3)
+		RTW_PRINT_SEL(sel, "retry_cnt:%u\n", info->retry_cnt);
+
+	if (info->len > 4)
+		RTW_PRINT_SEL(sel, "rssi:%u\n", info->rssi);
+
+	if (info->len > 5)
+		RTW_PRINT_SEL(sel, "byte5:%s%s\n"
+			      , info->eSCO_SCO ? "eSCO_SCO " : ""
+			      , info->Master_Slave ? "Master_Slave " : ""
+			     );
+}
+
+static void rtw_btinfo_hdl(_adapter *adapter, u8 *buf, u16 buf_len)
+{
+#define BTINFO_WIFI_FETCH 0x23
+#define BTINFO_BT_AUTO_RPT 0x27
+#ifdef CONFIG_BT_COEXIST_SOCKET_TRX
+	struct btinfo_8761ATV *info = (struct btinfo_8761ATV *)buf;
+#else /* !CONFIG_BT_COEXIST_SOCKET_TRX */
+	struct btinfo *info = (struct btinfo *)buf;
+#endif /* CONFIG_BT_COEXIST_SOCKET_TRX */
+	u8 cmd_idx;
+	u8 len;
+
+	cmd_idx = info->cid;
+
+	if (info->len > buf_len - 2) {
+		rtw_warn_on(1);
+		len = buf_len - 2;
+	} else
+		len = info->len;
+
+	/* #define DBG_PROC_SET_BTINFO_EVT */
+#ifdef DBG_PROC_SET_BTINFO_EVT
+#ifdef CONFIG_BT_COEXIST_SOCKET_TRX
+	RTW_INFO("%s: btinfo[0]=%x,btinfo[1]=%x,btinfo[2]=%x,btinfo[3]=%x btinfo[4]=%x,btinfo[5]=%x,btinfo[6]=%x,btinfo[7]=%x\n"
+		, __func__, buf[0], buf[1], buf[2], buf[3], buf[4], buf[5], buf[6], buf[7]);
+#else/* !CONFIG_BT_COEXIST_SOCKET_TRX */
+	btinfo_evt_dump(RTW_DBGDUMP, info);
+#endif /* CONFIG_BT_COEXIST_SOCKET_TRX */
+#endif /* DBG_PROC_SET_BTINFO_EVT */
+
+	/* transform BT-FW btinfo to WiFI-FW C2H format and notify */
+	if (cmd_idx == BTINFO_WIFI_FETCH)
+		buf[1] = 0;
+	else if (cmd_idx == BTINFO_BT_AUTO_RPT)
+		buf[1] = 2;
+#ifdef CONFIG_BT_COEXIST_SOCKET_TRX
+	else if (0x01 == cmd_idx || 0x02 == cmd_idx)
+		buf[1] = buf[0];
+#endif /* CONFIG_BT_COEXIST_SOCKET_TRX */
+	rtw_btcoex_BtInfoNotify(adapter , len + 1, &buf[1]);
+}
+
+u8 rtw_btinfo_cmd(_adapter *adapter, u8 *buf, u16 len)
+{
+	struct cmd_obj *ph2c;
+	struct drvextra_cmd_parm *pdrvextra_cmd_parm;
+	u8 *btinfo;
+	struct cmd_priv *pcmdpriv = &adapter->cmdpriv;
+	u8	res = _SUCCESS;
+
+	ph2c = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj));
+	if (ph2c == NULL) {
+		res = _FAIL;
+		goto exit;
+	}
+
+	pdrvextra_cmd_parm = (struct drvextra_cmd_parm *)rtw_zmalloc(sizeof(struct drvextra_cmd_parm));
+	if (pdrvextra_cmd_parm == NULL) {
+		rtw_mfree((u8 *)ph2c, sizeof(struct cmd_obj));
+		res = _FAIL;
+		goto exit;
+	}
+
+	btinfo = rtw_zmalloc(len);
+	if (btinfo == NULL) {
+		rtw_mfree((u8 *)ph2c, sizeof(struct cmd_obj));
+		rtw_mfree((u8 *)pdrvextra_cmd_parm, sizeof(struct drvextra_cmd_parm));
+		res = _FAIL;
+		goto exit;
+	}
+
+	pdrvextra_cmd_parm->ec_id = BTINFO_WK_CID;
+	pdrvextra_cmd_parm->type = 0;
+	pdrvextra_cmd_parm->size = len;
+	pdrvextra_cmd_parm->pbuf = btinfo;
+
+	_rtw_memcpy(btinfo, buf, len);
+
+	init_h2fwcmd_w_parm_no_rsp(ph2c, pdrvextra_cmd_parm, GEN_CMD_CODE(_Set_Drv_Extra));
+
+	res = rtw_enqueue_cmd(pcmdpriv, ph2c);
+
+exit:
+	return res;
+}
+#endif /* CONFIG_BT_COEXIST */
+
+u8 rtw_test_h2c_cmd(_adapter *adapter, u8 *buf, u8 len)
+{
+	struct cmd_obj *pcmdobj;
+	struct drvextra_cmd_parm *pdrvextra_cmd_parm;
+	u8 *ph2c_content;
+	struct cmd_priv *pcmdpriv = &adapter->cmdpriv;
+	u8	res = _SUCCESS;
+
+	pcmdobj = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj));
+	if (pcmdobj == NULL) {
+		res = _FAIL;
+		goto exit;
+	}
+
+	pdrvextra_cmd_parm = (struct drvextra_cmd_parm *)rtw_zmalloc(sizeof(struct drvextra_cmd_parm));
+	if (pdrvextra_cmd_parm == NULL) {
+		rtw_mfree((u8 *)pcmdobj, sizeof(struct cmd_obj));
+		res = _FAIL;
+		goto exit;
+	}
+
+	ph2c_content = rtw_zmalloc(len);
+	if (ph2c_content == NULL) {
+		rtw_mfree((u8 *)pcmdobj, sizeof(struct cmd_obj));
+		rtw_mfree((u8 *)pdrvextra_cmd_parm, sizeof(struct drvextra_cmd_parm));
+		res = _FAIL;
+		goto exit;
+	}
+
+	pdrvextra_cmd_parm->ec_id = TEST_H2C_CID;
+	pdrvextra_cmd_parm->type = 0;
+	pdrvextra_cmd_parm->size = len;
+	pdrvextra_cmd_parm->pbuf = ph2c_content;
+
+	_rtw_memcpy(ph2c_content, buf, len);
+
+	init_h2fwcmd_w_parm_no_rsp(pcmdobj, pdrvextra_cmd_parm, GEN_CMD_CODE(_Set_Drv_Extra));
+
+	res = rtw_enqueue_cmd(pcmdpriv, pcmdobj);
+
+exit:
+	return res;
+}
+
+#ifdef CONFIG_MP_INCLUDED
+static s32 rtw_mp_cmd_hdl(_adapter *padapter, u8 mp_cmd_id)
+{
+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(padapter);
+	int ret = H2C_SUCCESS;
+	uint status = _SUCCESS;
+
+	if (mp_cmd_id == MP_START) {
+		if (padapter->registrypriv.mp_mode == 0) {
+			rtw_intf_stop(padapter);
+			rtw_hal_deinit(padapter);
+			padapter->registrypriv.mp_mode = 1;
+#if (CONFIG_BTCOEX_SUPPORT_WIFI_ONLY_CFG == 1)
+		padapter->mppriv.CureFuseBTCoex = pHalData->EEPROMBluetoothCoexist;
+		pHalData->EEPROMBluetoothCoexist = _FALSE;
+#endif
+#ifdef CONFIG_RF_POWER_TRIM
+			if (!IS_HARDWARE_TYPE_8814A(padapter) && !IS_HARDWARE_TYPE_8822B(padapter)) {
+				padapter->registrypriv.RegPwrTrimEnable = 1;
+				rtw_hal_read_chip_info(padapter);
+			}
+#endif /*CONFIG_RF_POWER_TRIM*/
+			rtw_reset_drv_sw(padapter);
+#ifdef CONFIG_NEW_NETDEV_HDL
+			if (!rtw_is_hw_init_completed(padapter)) {
+				status = rtw_hal_init(padapter);
+				if (status == _FAIL) {
+					ret = H2C_REJECTED;
+					goto exit;
+				}
+				rtw_hal_iface_init(padapter);
+			}
+#else
+			status = rtw_hal_init(padapter);
+			if (status == _FAIL) {
+				ret = H2C_REJECTED;
+				goto exit;
+			}
+#endif /*CONFIG_NEW_NETDEV_HDL*/
+#ifndef RTW_HALMAC
+			rtw_intf_start(padapter);
+#endif /* !RTW_HALMAC */
+#ifdef RTW_HALMAC /*for New IC*/
+			MPT_InitializeAdapter(padapter, 1);
+#endif /* CONFIG_MP_INCLUDED */
+		}
+
+		if (padapter->registrypriv.mp_mode == 0) {
+			ret = H2C_REJECTED;
+			goto exit;
+		}
+
+		if (padapter->mppriv.mode == MP_OFF) {
+			if (mp_start_test(padapter) == _FAIL) {
+				ret = H2C_REJECTED;
+				goto exit;
+			}
+			padapter->mppriv.mode = MP_ON;
+			MPT_PwrCtlDM(padapter, 0);
+		}
+		padapter->mppriv.bmac_filter = _FALSE;
+#ifdef CONFIG_RTL8723B
+#ifdef CONFIG_USB_HCI
+		rtw_write32(padapter, 0x765, 0x0000);
+		rtw_write32(padapter, 0x948, 0x0280);
+#else
+		rtw_write32(padapter, 0x765, 0x0000);
+		rtw_write32(padapter, 0x948, 0x0000);
+#endif
+#ifdef CONFIG_FOR_RTL8723BS_VQ0
+		rtw_write32(padapter, 0x765, 0x0000);
+		rtw_write32(padapter, 0x948, 0x0280);
+#endif
+		rtw_write8(padapter, 0x66, 0x27); /*Open BT uart Log*/
+		rtw_write8(padapter, 0xc50, 0x20); /*for RX init Gain*/
+#endif
+		odm_write_dig(&pHalData->odmpriv, 0x20);
+
+	} else if (mp_cmd_id == MP_STOP) {
+		if (padapter->registrypriv.mp_mode == 1) {
+			MPT_DeInitAdapter(padapter);
+			rtw_intf_stop(padapter);
+			rtw_hal_deinit(padapter);
+			padapter->registrypriv.mp_mode = 0;
+#if (CONFIG_BTCOEX_SUPPORT_WIFI_ONLY_CFG == 1)
+			pHalData->EEPROMBluetoothCoexist = padapter->mppriv.CureFuseBTCoex;
+#endif
+			rtw_reset_drv_sw(padapter);
+#ifdef CONFIG_NEW_NETDEV_HDL
+			if (!rtw_is_hw_init_completed(padapter)) {
+				status = rtw_hal_init(padapter);
+				if (status == _FAIL) {
+					ret = H2C_REJECTED;
+					goto exit;
+				}
+				rtw_hal_iface_init(padapter);
+			}
+#else
+			status = rtw_hal_init(padapter);
+			if (status == _FAIL) {
+				ret = H2C_REJECTED;
+				goto exit;
+			}
+#endif /*CONFIG_NEW_NETDEV_HDL*/
+#ifndef RTW_HALMAC
+			rtw_intf_start(padapter);
+#endif /* !RTW_HALMAC */
+		}
+
+		if (padapter->mppriv.mode != MP_OFF) {
+			mp_stop_test(padapter);
+			padapter->mppriv.mode = MP_OFF;
+		}
+
+	} else {
+		RTW_INFO(FUNC_ADPT_FMT"invalid id:%d\n", FUNC_ADPT_ARG(padapter), mp_cmd_id);
+		ret = H2C_PARAMETERS_ERROR;
+		rtw_warn_on(1);
+	}
+
+exit:
+	return ret;
+}
+
+u8 rtw_mp_cmd(_adapter *adapter, u8 mp_cmd_id, u8 flags)
+{
+	struct cmd_obj *cmdobj;
+	struct drvextra_cmd_parm *parm;
+	struct cmd_priv *pcmdpriv = &adapter->cmdpriv;
+	struct submit_ctx sctx;
+	u8	res = _SUCCESS;
+
+	parm = (struct drvextra_cmd_parm *)rtw_zmalloc(sizeof(struct drvextra_cmd_parm));
+	if (parm == NULL) {
+		res = _FAIL;
+		goto exit;
+	}
+
+	parm->ec_id = MP_CMD_WK_CID;
+	parm->type = mp_cmd_id;
+	parm->size = 0;
+	parm->pbuf = NULL;
+
+	if (flags & RTW_CMDF_DIRECTLY) {
+		/* no need to enqueue, do the cmd hdl directly and free cmd parameter */
+		if (H2C_SUCCESS != rtw_mp_cmd_hdl(adapter, mp_cmd_id))
+			res = _FAIL;
+		rtw_mfree((u8 *)parm, sizeof(*parm));
+	} else {
+		/* need enqueue, prepare cmd_obj and enqueue */
+		cmdobj = (struct cmd_obj *)rtw_zmalloc(sizeof(*cmdobj));
+		if (cmdobj == NULL) {
+			res = _FAIL;
+			rtw_mfree((u8 *)parm, sizeof(*parm));
+			goto exit;
+		}
+
+		init_h2fwcmd_w_parm_no_rsp(cmdobj, parm, GEN_CMD_CODE(_Set_Drv_Extra));
+
+		if (flags & RTW_CMDF_WAIT_ACK) {
+			cmdobj->sctx = &sctx;
+			rtw_sctx_init(&sctx, 10 * 1000);
+		}
+
+		res = rtw_enqueue_cmd(pcmdpriv, cmdobj);
+
+		if (res == _SUCCESS && (flags & RTW_CMDF_WAIT_ACK)) {
+			rtw_sctx_wait(&sctx, __func__);
+			_enter_critical_mutex(&pcmdpriv->sctx_mutex, NULL);
+			if (sctx.status == RTW_SCTX_SUBMITTED)
+				cmdobj->sctx = NULL;
+			_exit_critical_mutex(&pcmdpriv->sctx_mutex, NULL);
+			if (sctx.status != RTW_SCTX_DONE_SUCCESS)
+				res = _FAIL;
+		}
+	}
+
+exit:
+	return res;
+}
+#endif	/*CONFIG_MP_INCLUDED*/
+
+#ifdef CONFIG_RTW_CUSTOMER_STR
+static s32 rtw_customer_str_cmd_hdl(_adapter *adapter, u8 write, const u8 *cstr)
+{
+	int ret = H2C_SUCCESS;
+
+	if (write)
+		ret = rtw_hal_h2c_customer_str_write(adapter, cstr);
+	else
+		ret = rtw_hal_h2c_customer_str_req(adapter);
+
+	return ret == _SUCCESS ? H2C_SUCCESS : H2C_REJECTED;
+}
+
+static u8 rtw_customer_str_cmd(_adapter *adapter, u8 write, const u8 *cstr)
+{
+	struct cmd_obj *cmdobj;
+	struct drvextra_cmd_parm *parm;
+	u8 *str = NULL;
+	struct cmd_priv *pcmdpriv = &adapter->cmdpriv;
+	struct submit_ctx sctx;
+	u8 res = _SUCCESS;
+
+	parm = (struct drvextra_cmd_parm *)rtw_zmalloc(sizeof(struct drvextra_cmd_parm));
+	if (parm == NULL) {
+		res = _FAIL;
+		goto exit;
+	}
+
+	if (write) {
+		str = rtw_zmalloc(RTW_CUSTOMER_STR_LEN);
+		if (str == NULL) {
+			rtw_mfree((u8 *)parm, sizeof(struct drvextra_cmd_parm));
+			res = _FAIL;
+			goto exit;
+		}
+	}
+
+	parm->ec_id = CUSTOMER_STR_WK_CID;
+	parm->type = write;
+	parm->size = write ? RTW_CUSTOMER_STR_LEN : 0;
+	parm->pbuf = write ? str : NULL;
+
+	if (write)
+		_rtw_memcpy(str, cstr, RTW_CUSTOMER_STR_LEN);
+
+	/* need enqueue, prepare cmd_obj and enqueue */
+	cmdobj = (struct cmd_obj *)rtw_zmalloc(sizeof(*cmdobj));
+	if (cmdobj == NULL) {
+		res = _FAIL;
+		rtw_mfree((u8 *)parm, sizeof(*parm));
+		if (write)
+			rtw_mfree(str, RTW_CUSTOMER_STR_LEN);
+		goto exit;
+	}
+
+	init_h2fwcmd_w_parm_no_rsp(cmdobj, parm, GEN_CMD_CODE(_Set_Drv_Extra));
+
+	cmdobj->sctx = &sctx;
+	rtw_sctx_init(&sctx, 2 * 1000);
+
+	res = rtw_enqueue_cmd(pcmdpriv, cmdobj);
+
+	if (res == _SUCCESS) {
+		rtw_sctx_wait(&sctx, __func__);
+		_enter_critical_mutex(&pcmdpriv->sctx_mutex, NULL);
+		if (sctx.status == RTW_SCTX_SUBMITTED)
+			cmdobj->sctx = NULL;
+		_exit_critical_mutex(&pcmdpriv->sctx_mutex, NULL);
+		if (sctx.status != RTW_SCTX_DONE_SUCCESS)
+			res = _FAIL;
+	}
+
+exit:
+	return res;
+}
+
+inline u8 rtw_customer_str_req_cmd(_adapter *adapter)
+{
+	return rtw_customer_str_cmd(adapter, 0, NULL);
+}
+
+inline u8 rtw_customer_str_write_cmd(_adapter *adapter, const u8 *cstr)
+{
+	return rtw_customer_str_cmd(adapter, 1, cstr);
+}
+#endif /* CONFIG_RTW_CUSTOMER_STR */
+
+u8 rtw_c2h_wk_cmd(PADAPTER padapter, u8 *pbuf, u16 length, u8 type)
+{
+	struct cmd_obj *ph2c;
+	struct drvextra_cmd_parm *pdrvextra_cmd_parm;
+	struct cmd_priv *pcmdpriv = &padapter->cmdpriv;
+	u8 *extra_cmd_buf;
+	u8 res = _SUCCESS;
+
+	ph2c = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj));
+	if (ph2c == NULL) {
+		res = _FAIL;
+		goto exit;
+	}
+
+	pdrvextra_cmd_parm = (struct drvextra_cmd_parm *)rtw_zmalloc(sizeof(struct drvextra_cmd_parm));
+	if (pdrvextra_cmd_parm == NULL) {
+		rtw_mfree((u8 *)ph2c, sizeof(struct cmd_obj));
+		res = _FAIL;
+		goto exit;
+	}
+
+	extra_cmd_buf = rtw_zmalloc(length);
+	if (extra_cmd_buf == NULL) {
+		rtw_mfree((u8 *)ph2c, sizeof(struct cmd_obj));
+		rtw_mfree((u8 *)pdrvextra_cmd_parm, sizeof(struct drvextra_cmd_parm));
+		res = _FAIL;
+		goto exit;
+	}
+
+	_rtw_memcpy(extra_cmd_buf, pbuf, length);
+	pdrvextra_cmd_parm->ec_id = C2H_WK_CID;
+	pdrvextra_cmd_parm->type = type;
+	pdrvextra_cmd_parm->size = length;
+	pdrvextra_cmd_parm->pbuf = extra_cmd_buf;
+
+	init_h2fwcmd_w_parm_no_rsp(ph2c, pdrvextra_cmd_parm, GEN_CMD_CODE(_Set_Drv_Extra));
+
+	res = rtw_enqueue_cmd(pcmdpriv, ph2c);
+
+exit:
+	return res;
+}
+
+#ifdef CONFIG_FW_C2H_REG
+inline u8 rtw_c2h_reg_wk_cmd(_adapter *adapter, u8 *c2h_evt)
+{
+	return rtw_c2h_wk_cmd(adapter, c2h_evt, c2h_evt ? C2H_REG_LEN : 0, C2H_TYPE_REG);
+}
+#endif
+
+#ifdef CONFIG_FW_C2H_PKT
+inline u8 rtw_c2h_packet_wk_cmd(_adapter *adapter, u8 *c2h_evt, u16 length)
+{
+	return rtw_c2h_wk_cmd(adapter, c2h_evt, length, C2H_TYPE_PKT);
+}
+#endif
+
+u8 rtw_run_in_thread_cmd(PADAPTER padapter, void (*func)(void *), void *context)
+{
+	struct cmd_priv *pcmdpriv;
+	struct cmd_obj *ph2c;
+	struct RunInThread_param *parm;
+	s32 res = _SUCCESS;
+
+
+	pcmdpriv = &padapter->cmdpriv;
+
+	ph2c = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj));
+	if (NULL == ph2c) {
+		res = _FAIL;
+		goto exit;
+	}
+
+	parm = (struct RunInThread_param *)rtw_zmalloc(sizeof(struct RunInThread_param));
+	if (NULL == parm) {
+		rtw_mfree((u8 *)ph2c, sizeof(struct cmd_obj));
+		res = _FAIL;
+		goto exit;
+	}
+
+	parm->func = func;
+	parm->context = context;
+	init_h2fwcmd_w_parm_no_rsp(ph2c, parm, GEN_CMD_CODE(_RunInThreadCMD));
+
+	res = rtw_enqueue_cmd(pcmdpriv, ph2c);
+exit:
+
+
+	return res;
+}
+
+#ifdef CONFIG_FW_C2H_REG
+s32 c2h_evt_hdl(_adapter *adapter, u8 *c2h_evt, c2h_id_filter filter)
+{
+	s32 ret = _FAIL;
+	u8 buf[C2H_REG_LEN] = {0};
+	u8 id, seq, plen;
+	u8 *payload;
+
+	if (!c2h_evt) {
+		/* No c2h event in cmd_obj, read c2h event before handling*/
+		if (rtw_hal_c2h_evt_read(adapter, buf) != _SUCCESS)
+			goto exit;
+		c2h_evt = buf;
+	}
+
+	rtw_hal_c2h_reg_hdr_parse(adapter, c2h_evt, &id, &seq, &plen, &payload);
+
+	if (filter && filter(adapter, id, seq, plen, payload) == _FALSE)
+		goto exit;
+
+	ret = rtw_hal_c2h_handler(adapter, id, seq, plen, payload);
+
+exit:
+	return ret;
+}
+#endif /* CONFIG_FW_C2H_REG */
+
+u8 session_tracker_cmd(_adapter *adapter, u8 cmd, struct sta_info *sta, u8 *local_naddr, u8 *local_port, u8 *remote_naddr, u8 *remote_port)
+{
+	struct cmd_priv	*cmdpriv = &adapter->cmdpriv;
+	struct cmd_obj *cmdobj;
+	struct drvextra_cmd_parm *cmd_parm;
+	struct st_cmd_parm *st_parm;
+	u8	res = _SUCCESS;
+
+	cmdobj = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj));
+	if (cmdobj == NULL) {
+		res = _FAIL;
+		goto exit;
+	}
+
+	cmd_parm = (struct drvextra_cmd_parm *)rtw_zmalloc(sizeof(struct drvextra_cmd_parm));
+	if (cmd_parm == NULL) {
+		rtw_mfree((u8 *)cmdobj, sizeof(struct cmd_obj));
+		res = _FAIL;
+		goto exit;
+	}
+
+	st_parm = (struct st_cmd_parm *)rtw_zmalloc(sizeof(struct st_cmd_parm));
+	if (st_parm == NULL) {
+		rtw_mfree((u8 *)cmdobj, sizeof(struct cmd_obj));
+		rtw_mfree((u8 *)cmd_parm, sizeof(struct drvextra_cmd_parm));
+		res = _FAIL;
+		goto exit;
+	}
+
+	st_parm->cmd = cmd;
+	st_parm->sta = sta;
+	if (cmd != ST_CMD_CHK) {
+		_rtw_memcpy(&st_parm->local_naddr, local_naddr, 4);
+		_rtw_memcpy(&st_parm->local_port, local_port, 2);
+		_rtw_memcpy(&st_parm->remote_naddr, remote_naddr, 4);
+		_rtw_memcpy(&st_parm->remote_port, remote_port, 2);
+	}
+
+	cmd_parm->ec_id = SESSION_TRACKER_WK_CID;
+	cmd_parm->type = 0;
+	cmd_parm->size = sizeof(struct st_cmd_parm);
+	cmd_parm->pbuf = (u8 *)st_parm;
+	init_h2fwcmd_w_parm_no_rsp(cmdobj, cmd_parm, GEN_CMD_CODE(_Set_Drv_Extra));
+	cmdobj->no_io = 1;
+
+	res = rtw_enqueue_cmd(cmdpriv, cmdobj);
+
+exit:
+	return res;
+}
+
+inline u8 session_tracker_chk_cmd(_adapter *adapter, struct sta_info *sta)
+{
+	return session_tracker_cmd(adapter, ST_CMD_CHK, sta, NULL, NULL, NULL, NULL);
+}
+
+inline u8 session_tracker_add_cmd(_adapter *adapter, struct sta_info *sta, u8 *local_naddr, u8 *local_port, u8 *remote_naddr, u8 *remote_port)
+{
+	return session_tracker_cmd(adapter, ST_CMD_ADD, sta, local_naddr, local_port, remote_naddr, remote_port);
+}
+
+inline u8 session_tracker_del_cmd(_adapter *adapter, struct sta_info *sta, u8 *local_naddr, u8 *local_port, u8 *remote_naddr, u8 *remote_port)
+{
+	return session_tracker_cmd(adapter, ST_CMD_DEL, sta, local_naddr, local_port, remote_naddr, remote_port);
+}
+
+void session_tracker_chk_for_sta(_adapter *adapter, struct sta_info *sta)
+{
+	struct st_ctl_t *st_ctl = &sta->st_ctl;
+	int i;
+	_irqL irqL;
+	_list *plist, *phead, *pnext;
+	_list dlist;
+	struct session_tracker *st = NULL;
+	u8 op_wfd_mode = MIRACAST_DISABLED;
+
+	if (DBG_SESSION_TRACKER)
+		RTW_INFO(FUNC_ADPT_FMT" sta:%p\n", FUNC_ADPT_ARG(adapter), sta);
+
+	if (!(sta->state & _FW_LINKED))
+		goto exit;
+
+	for (i = 0; i < SESSION_TRACKER_REG_ID_NUM; i++) {
+		if (st_ctl->reg[i].s_proto != 0)
+			break;
+	}
+	if (i >= SESSION_TRACKER_REG_ID_NUM)
+		goto chk_sta;
+
+	_rtw_init_listhead(&dlist);
+
+	_enter_critical_bh(&st_ctl->tracker_q.lock, &irqL);
+
+	phead = &st_ctl->tracker_q.queue;
+	plist = get_next(phead);
+	pnext = get_next(plist);
+	while (rtw_end_of_queue_search(phead, plist) == _FALSE) {
+		st = LIST_CONTAINOR(plist, struct session_tracker, list);
+		plist = pnext;
+		pnext = get_next(pnext);
+
+		if (st->status != ST_STATUS_ESTABLISH
+			&& rtw_get_passing_time_ms(st->set_time) > ST_EXPIRE_MS
+		) {
+			rtw_list_delete(&st->list);
+			rtw_list_insert_tail(&st->list, &dlist);
+		}
+
+		/* TODO: check OS for status update */
+		if (st->status == ST_STATUS_CHECK)
+			st->status = ST_STATUS_ESTABLISH;
+
+		if (st->status != ST_STATUS_ESTABLISH)
+			continue;
+
+		#ifdef CONFIG_WFD
+		if (0)
+			RTW_INFO(FUNC_ADPT_FMT" local:%u, remote:%u, rtsp:%u, %u, %u\n", FUNC_ADPT_ARG(adapter)
+				, ntohs(st->local_port), ntohs(st->remote_port), adapter->wfd_info.rtsp_ctrlport, adapter->wfd_info.tdls_rtsp_ctrlport
+				, adapter->wfd_info.peer_rtsp_ctrlport);
+		if (ntohs(st->local_port) == adapter->wfd_info.rtsp_ctrlport)
+			op_wfd_mode |= MIRACAST_SINK;
+		if (ntohs(st->local_port) == adapter->wfd_info.tdls_rtsp_ctrlport)
+			op_wfd_mode |= MIRACAST_SINK;
+		if (ntohs(st->remote_port) == adapter->wfd_info.peer_rtsp_ctrlport)
+			op_wfd_mode |= MIRACAST_SOURCE;
+		#endif
+	}
+
+	_exit_critical_bh(&st_ctl->tracker_q.lock, &irqL);
+
+	plist = get_next(&dlist);
+	while (rtw_end_of_queue_search(&dlist, plist) == _FALSE) {
+		st = LIST_CONTAINOR(plist, struct session_tracker, list);
+		plist = get_next(plist);
+		rtw_mfree((u8 *)st, sizeof(struct session_tracker));
+	}
+
+chk_sta:
+	if (STA_OP_WFD_MODE(sta) != op_wfd_mode) {
+		STA_SET_OP_WFD_MODE(sta, op_wfd_mode);
+		rtw_sta_media_status_rpt_cmd(adapter, sta, 1);
+	}
+
+exit:
+	return;
+}
+
+void session_tracker_chk_for_adapter(_adapter *adapter)
+{
+	struct sta_priv *stapriv = &adapter->stapriv;
+	struct sta_info *sta;
+	int i;
+	_irqL irqL;
+	_list *plist, *phead;
+	u8 op_wfd_mode = MIRACAST_DISABLED;
+
+	_enter_critical_bh(&stapriv->sta_hash_lock, &irqL);
+
+	for (i = 0; i < NUM_STA; i++) {
+		phead = &(stapriv->sta_hash[i]);
+		plist = get_next(phead);
+
+		while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) {
+			sta = LIST_CONTAINOR(plist, struct sta_info, hash_list);
+			plist = get_next(plist);
+
+			session_tracker_chk_for_sta(adapter, sta);
+
+			op_wfd_mode |= STA_OP_WFD_MODE(sta);
+		}
+	}
+
+	_exit_critical_bh(&stapriv->sta_hash_lock, &irqL);
+
+#ifdef CONFIG_WFD
+	adapter->wfd_info.op_wfd_mode = MIRACAST_MODE_REVERSE(op_wfd_mode);
+#endif
+}
+
+void session_tracker_cmd_hdl(_adapter *adapter, struct st_cmd_parm *parm)
+{
+	u8 cmd = parm->cmd;
+	struct sta_info *sta = parm->sta;
+
+	if (cmd == ST_CMD_CHK) {
+		if (sta)
+			session_tracker_chk_for_sta(adapter, sta);
+		else
+			session_tracker_chk_for_adapter(adapter);
+
+		goto exit;
+
+	} else if (cmd == ST_CMD_ADD || cmd == ST_CMD_DEL) {
+		struct st_ctl_t *st_ctl;
+		u32 local_naddr = parm->local_naddr;
+		u16 local_port = parm->local_port;
+		u32 remote_naddr = parm->remote_naddr;
+		u16 remote_port = parm->remote_port;
+		struct session_tracker *st = NULL;
+		_irqL irqL;
+		_list *plist, *phead;
+		u8 free_st = 0;
+		u8 alloc_st = 0;
+
+		if (DBG_SESSION_TRACKER)
+			RTW_INFO(FUNC_ADPT_FMT" cmd:%u, sta:%p, local:"IP_FMT":"PORT_FMT", remote:"IP_FMT":"PORT_FMT"\n"
+				, FUNC_ADPT_ARG(adapter), cmd, sta
+				, IP_ARG(&local_naddr), PORT_ARG(&local_port)
+				, IP_ARG(&remote_naddr), PORT_ARG(&remote_port)
+			);
+
+		if (!(sta->state & _FW_LINKED))
+			goto exit;
+
+		st_ctl = &sta->st_ctl;
+
+		_enter_critical_bh(&st_ctl->tracker_q.lock, &irqL);
+
+		phead = &st_ctl->tracker_q.queue;
+		plist = get_next(phead);
+		while (rtw_end_of_queue_search(phead, plist) == _FALSE) {
+			st = LIST_CONTAINOR(plist, struct session_tracker, list);
+
+			if (st->local_naddr == local_naddr
+				&& st->local_port == local_port
+				&& st->remote_naddr == remote_naddr
+				&& st->remote_port == remote_port)
+				break;
+
+			plist = get_next(plist);
+		}
+
+		if (rtw_end_of_queue_search(phead, plist) == _TRUE)
+			st = NULL;
+
+		switch (cmd) {
+		case ST_CMD_DEL:
+			if (st) {
+				rtw_list_delete(plist);
+				free_st = 1;
+			}
+			goto unlock;
+		case ST_CMD_ADD:
+			if (!st)
+				alloc_st = 1;
+		}
+
+unlock:
+		_exit_critical_bh(&st_ctl->tracker_q.lock, &irqL);
+
+		if (free_st) {
+			rtw_mfree((u8 *)st, sizeof(struct session_tracker));
+			goto exit;
+		}
+
+		if (alloc_st) {
+			st = (struct session_tracker *)rtw_zmalloc(sizeof(struct session_tracker));
+			if (!st)
+				goto exit;
+
+			st->local_naddr = local_naddr;
+			st->local_port = local_port;
+			st->remote_naddr = remote_naddr;
+			st->remote_port = remote_port;
+			st->set_time = rtw_get_current_time();
+			st->status = ST_STATUS_CHECK;
+
+			_enter_critical_bh(&st_ctl->tracker_q.lock, &irqL);
+			rtw_list_insert_tail(&st->list, phead);
+			_exit_critical_bh(&st_ctl->tracker_q.lock, &irqL);
+		}
+	}
+
+exit:
+	return;
+}
+
+#if defined(CONFIG_RTW_MESH) && defined(RTW_PER_CMD_SUPPORT_FW)
+static s32 rtw_req_per_cmd_hdl(_adapter *adapter)
+{
+	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
+	struct macid_ctl_t *macid_ctl = dvobj_to_macidctl(dvobj);
+	struct macid_bmp req_macid_bmp, *macid_bmp;
+	u8 i, ret = _FAIL;
+
+	macid_bmp = &macid_ctl->if_g[adapter->iface_id];
+	_rtw_memcpy(&req_macid_bmp, macid_bmp, sizeof(struct macid_bmp));
+
+	/* Clear none mesh's macid */
+	for (i = 0; i < macid_ctl->num; i++) {
+		u8 role;
+		role = GET_H2CCMD_MSRRPT_PARM_ROLE(&macid_ctl->h2c_msr[i]);
+		if (role != H2C_MSR_ROLE_MESH)
+			rtw_macid_map_clr(&req_macid_bmp, i);
+	}
+
+	/* group_macid: always be 0 in NIC, so only pass macid_bitmap.m0
+	 * rpt_type: 0 includes all info in 1, use 0 for now 
+	 * macid_bitmap: pass m0 only for NIC
+	 */
+	ret = rtw_hal_set_req_per_rpt_cmd(adapter, 0, 0, req_macid_bmp.m0);
+
+	return ret;
+}
+
+u8 rtw_req_per_cmd(_adapter *adapter)
+{
+	struct cmd_obj *cmdobj;
+	struct drvextra_cmd_parm *parm;
+	struct cmd_priv *pcmdpriv = &adapter->cmdpriv;
+	struct submit_ctx sctx;
+	u8 res = _SUCCESS;
+
+	parm = (struct drvextra_cmd_parm *)rtw_zmalloc(sizeof(struct drvextra_cmd_parm));
+	if (parm == NULL) {
+		res = _FAIL;
+		goto exit;
+	}
+
+	parm->ec_id = REQ_PER_CMD_WK_CID;
+	parm->type = 0;
+	parm->size = 0;
+	parm->pbuf = NULL;
+
+	cmdobj = (struct cmd_obj *)rtw_zmalloc(sizeof(*cmdobj));
+	if (cmdobj == NULL) {
+		res = _FAIL;
+		rtw_mfree((u8 *)parm, sizeof(*parm));
+		goto exit;
+	}
+
+	init_h2fwcmd_w_parm_no_rsp(cmdobj, parm, GEN_CMD_CODE(_Set_Drv_Extra));
+
+	res = rtw_enqueue_cmd(pcmdpriv, cmdobj);
+
+exit:
+	return res;
+}
+#endif
+
+u8 rtw_drvextra_cmd_hdl(_adapter *padapter, unsigned char *pbuf)
+{
+	int ret = H2C_SUCCESS;
+	struct drvextra_cmd_parm *pdrvextra_cmd;
+
+	if (!pbuf)
+		return H2C_PARAMETERS_ERROR;
+
+	pdrvextra_cmd = (struct drvextra_cmd_parm *)pbuf;
+
+	switch (pdrvextra_cmd->ec_id) {
+	case STA_MSTATUS_RPT_WK_CID:
+		rtw_sta_media_status_rpt_cmd_hdl(padapter, (struct sta_media_status_rpt_cmd_parm *)pdrvextra_cmd->pbuf);
+		break;
+
+	case DYNAMIC_CHK_WK_CID:/*only  primary padapter go to this cmd, but execute dynamic_chk_wk_hdl() for two interfaces */
+		rtw_dynamic_chk_wk_hdl(padapter);
+		break;
+	case POWER_SAVING_CTRL_WK_CID:
+		power_saving_wk_hdl(padapter);
+		break;
+#ifdef CONFIG_LPS
+	case LPS_CTRL_WK_CID:
+		lps_ctrl_wk_hdl(padapter, (u8)pdrvextra_cmd->type);
+		break;
+	case DM_IN_LPS_WK_CID:
+		rtw_dm_in_lps_hdl(padapter);
+		break;
+	case LPS_CHANGE_DTIM_CID:
+		rtw_lps_change_dtim_hdl(padapter, (u8)pdrvextra_cmd->type);
+		break;
+#endif
+#if (RATE_ADAPTIVE_SUPPORT == 1)
+	case RTP_TIMER_CFG_WK_CID:
+		rpt_timer_setting_wk_hdl(padapter, pdrvextra_cmd->type);
+		break;
+#endif
+#ifdef CONFIG_ANTENNA_DIVERSITY
+	case ANT_SELECT_WK_CID:
+		antenna_select_wk_hdl(padapter, pdrvextra_cmd->type);
+		break;
+#endif
+#ifdef CONFIG_P2P_PS
+	case P2P_PS_WK_CID:
+		p2p_ps_wk_hdl(padapter, pdrvextra_cmd->type);
+		break;
+#endif
+#ifdef CONFIG_P2P
+	case P2P_PROTO_WK_CID:
+		/*
+		* Commented by Albert 2011/07/01
+		* I used the type_size as the type command
+		*/
+		ret = p2p_protocol_wk_hdl(padapter, pdrvextra_cmd->type, pdrvextra_cmd->pbuf);
+		break;
+#endif
+#ifdef CONFIG_AP_MODE
+	case CHECK_HIQ_WK_CID:
+		rtw_chk_hi_queue_hdl(padapter);
+		break;
+#endif
+#ifdef CONFIG_INTEL_WIDI
+	case INTEl_WIDI_WK_CID:
+		intel_widi_wk_hdl(padapter, pdrvextra_cmd->type, pdrvextra_cmd->pbuf);
+		break;
+#endif
+	/* add for CONFIG_IEEE80211W, none 11w can use it */
+	case RESET_SECURITYPRIV:
+		reset_securitypriv_hdl(padapter);
+		break;
+	case FREE_ASSOC_RESOURCES:
+		free_assoc_resources_hdl(padapter, (u8)pdrvextra_cmd->type);
+		break;
+	case C2H_WK_CID:
+		switch (pdrvextra_cmd->type) {
+		#ifdef CONFIG_FW_C2H_REG
+		case C2H_TYPE_REG:
+			c2h_evt_hdl(padapter, pdrvextra_cmd->pbuf, NULL);
+			break;
+		#endif
+		#ifdef CONFIG_FW_C2H_PKT
+		case C2H_TYPE_PKT:
+			rtw_hal_c2h_pkt_hdl(padapter, pdrvextra_cmd->pbuf, pdrvextra_cmd->size);
+			break;
+		#endif
+		default:
+			RTW_ERR("unknown C2H type:%d\n", pdrvextra_cmd->type);
+			rtw_warn_on(1);
+			break;
+		}
+		break;
+#ifdef CONFIG_BEAMFORMING
+	case BEAMFORMING_WK_CID:
+		beamforming_wk_hdl(padapter, pdrvextra_cmd->type, pdrvextra_cmd->pbuf);
+		break;
+#endif
+	case DM_RA_MSK_WK_CID:
+		rtw_dm_ra_mask_hdl(padapter, (struct sta_info *)pdrvextra_cmd->pbuf);
+		break;
+#ifdef CONFIG_BT_COEXIST
+	case BTINFO_WK_CID:
+		rtw_btinfo_hdl(padapter, pdrvextra_cmd->pbuf, pdrvextra_cmd->size);
+		break;
+#endif
+#ifdef CONFIG_DFS_MASTER
+	case DFS_RADAR_DETECT_WK_CID:
+		rtw_dfs_rd_hdl(padapter);
+		break;
+	case DFS_RADAR_DETECT_EN_DEC_WK_CID:
+		rtw_dfs_rd_en_decision(padapter, MLME_ACTION_NONE, 0);
+		break;
+#endif
+	case SESSION_TRACKER_WK_CID:
+		session_tracker_cmd_hdl(padapter, (struct st_cmd_parm *)pdrvextra_cmd->pbuf);
+		break;
+	case EN_HW_UPDATE_TSF_WK_CID:
+		rtw_hal_set_hwreg(padapter, HW_VAR_EN_HW_UPDATE_TSF, NULL);
+		break;
+	case PERIOD_TSF_UPDATE_END_WK_CID:
+		rtw_hal_periodic_tsf_update_chk(padapter);
+		break;
+	case TEST_H2C_CID:
+		rtw_hal_fill_h2c_cmd(padapter, pdrvextra_cmd->pbuf[0], pdrvextra_cmd->size - 1, &pdrvextra_cmd->pbuf[1]);
+		break;
+	case MP_CMD_WK_CID:
+#ifdef CONFIG_MP_INCLUDED
+		ret = rtw_mp_cmd_hdl(padapter, pdrvextra_cmd->type);
+#endif
+		break;
+#ifdef CONFIG_RTW_CUSTOMER_STR
+	case CUSTOMER_STR_WK_CID:
+		ret = rtw_customer_str_cmd_hdl(padapter, pdrvextra_cmd->type, pdrvextra_cmd->pbuf);
+		break;
+#endif
+
+#ifdef CONFIG_RTW_REPEATER_SON
+	case RSON_SCAN_WK_CID:
+		rtw_rson_scan_cmd_hdl(padapter, pdrvextra_cmd->type);
+		break;
+#endif
+
+#ifdef CONFIG_IOCTL_CFG80211
+	case MGNT_TX_WK_CID:
+		ret = rtw_mgnt_tx_handler(padapter, pdrvextra_cmd->pbuf);
+		break;
+#endif /* CONFIG_IOCTL_CFG80211 */
+#ifdef CONFIG_MCC_MODE
+	case MCC_SET_DURATION_WK_CID:
+		ret = rtw_set_mcc_duration_hdl(padapter, pdrvextra_cmd->type, pdrvextra_cmd->pbuf);
+		break;
+#endif /* CONFIG_MCC_MODE */
+#if defined(CONFIG_RTW_MESH) && defined(RTW_PER_CMD_SUPPORT_FW)
+	case REQ_PER_CMD_WK_CID:
+		ret = rtw_req_per_cmd_hdl(padapter);
+		break;
+#endif
+	default:
+		break;
+	}
+
+	if (pdrvextra_cmd->pbuf && pdrvextra_cmd->size > 0)
+		rtw_mfree(pdrvextra_cmd->pbuf, pdrvextra_cmd->size);
+
+	return ret;
+}
+
+void rtw_survey_cmd_callback(_adapter	*padapter ,  struct cmd_obj *pcmd)
+{
+	struct	mlme_priv *pmlmepriv = &padapter->mlmepriv;
+
+
+	if (pcmd->res == H2C_DROPPED) {
+		/* TODO: cancel timer and do timeout handler directly... */
+		/* need to make timeout handlerOS independent */
+		mlme_set_scan_to_timer(pmlmepriv, 1);
+	} else if (pcmd->res != H2C_SUCCESS) {
+		mlme_set_scan_to_timer(pmlmepriv, 1);
+	}
+
+	/* free cmd */
+	rtw_free_cmd_obj(pcmd);
+
+}
+void rtw_disassoc_cmd_callback(_adapter	*padapter,  struct cmd_obj *pcmd)
+{
+	_irqL	irqL;
+	struct	mlme_priv *pmlmepriv = &padapter->mlmepriv;
+
+
+	if (pcmd->res != H2C_SUCCESS) {
+		_enter_critical_bh(&pmlmepriv->lock, &irqL);
+		set_fwstate(pmlmepriv, _FW_LINKED);
+		_exit_critical_bh(&pmlmepriv->lock, &irqL);
+		goto exit;
+	}
+#ifdef CONFIG_BR_EXT
+	else /* clear bridge database */
+		nat25_db_cleanup(padapter);
+#endif /* CONFIG_BR_EXT */
+
+	/* free cmd */
+	rtw_free_cmd_obj(pcmd);
+
+exit:
+	return;
+}
+
+
+void rtw_getmacreg_cmdrsp_callback(_adapter *padapter,  struct cmd_obj *pcmd)
+{
+
+
+	rtw_free_cmd_obj(pcmd);
+
+}
+
+void rtw_joinbss_cmd_callback(_adapter	*padapter,  struct cmd_obj *pcmd)
+{
+	struct	mlme_priv *pmlmepriv = &padapter->mlmepriv;
+
+
+	if (pcmd->res == H2C_DROPPED) {
+		/* TODO: cancel timer and do timeout handler directly... */
+		/* need to make timeout handlerOS independent */
+		_set_timer(&pmlmepriv->assoc_timer, 1);
+	} else if (pcmd->res != H2C_SUCCESS)
+		_set_timer(&pmlmepriv->assoc_timer, 1);
+
+	rtw_free_cmd_obj(pcmd);
+
+}
+
+void rtw_create_ibss_post_hdl(_adapter *padapter, int status)
+{
+	_irqL irqL;
+	struct wlan_network *pwlan = NULL;
+	struct	mlme_priv *pmlmepriv = &padapter->mlmepriv;
+	WLAN_BSSID_EX *pdev_network = &padapter->registrypriv.dev_network;
+	struct wlan_network *mlme_cur_network = &(pmlmepriv->cur_network);
+
+	if (status != H2C_SUCCESS)
+		_set_timer(&pmlmepriv->assoc_timer, 1);
+
+	_cancel_timer_ex(&pmlmepriv->assoc_timer);
+
+	_enter_critical_bh(&pmlmepriv->lock, &irqL);
+
+	{
+		_irqL irqL;
+
+		pwlan = _rtw_alloc_network(pmlmepriv);
+		_enter_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);
+		if (pwlan == NULL) {
+			pwlan = rtw_get_oldest_wlan_network(&pmlmepriv->scanned_queue);
+			if (pwlan == NULL) {
+				_exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);
+				goto createbss_cmd_fail;
+			}
+			pwlan->last_scanned = rtw_get_current_time();
+		} else
+			rtw_list_insert_tail(&(pwlan->list), &pmlmepriv->scanned_queue.queue);
+
+		pdev_network->Length = get_WLAN_BSSID_EX_sz(pdev_network);
+		_rtw_memcpy(&(pwlan->network), pdev_network, pdev_network->Length);
+		/* pwlan->fixed = _TRUE; */
+
+		/* copy pdev_network information to pmlmepriv->cur_network */
+		_rtw_memcpy(&mlme_cur_network->network, pdev_network, (get_WLAN_BSSID_EX_sz(pdev_network)));
+
+#if 0
+		/* reset DSConfig */
+		mlme_cur_network->network.Configuration.DSConfig = (u32)rtw_ch2freq(pdev_network->Configuration.DSConfig);
+#endif
+
+		_clr_fwstate_(pmlmepriv, _FW_UNDER_LINKING);
+		_exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);
+		/* we will set _FW_LINKED when there is one more sat to join us (rtw_stassoc_event_callback) */
+	}
+
+createbss_cmd_fail:
+	_exit_critical_bh(&pmlmepriv->lock, &irqL);
+	return;
+}
+
+
+
+void rtw_setstaKey_cmdrsp_callback(_adapter	*padapter ,  struct cmd_obj *pcmd)
+{
+
+	struct sta_priv *pstapriv = &padapter->stapriv;
+	struct set_stakey_rsp *psetstakey_rsp = (struct set_stakey_rsp *)(pcmd->rsp);
+	struct sta_info	*psta = rtw_get_stainfo(pstapriv, psetstakey_rsp->addr);
+
+
+	if (psta == NULL) {
+		goto exit;
+	}
+
+	/* psta->cmn.aid = psta->cmn.mac_id = psetstakey_rsp->keyid; */ /* CAM_ID(CAM_ENTRY) */
+
+exit:
+
+	rtw_free_cmd_obj(pcmd);
+
+
+}
+void rtw_setassocsta_cmdrsp_callback(_adapter	*padapter,  struct cmd_obj *pcmd)
+{
+	_irqL	irqL;
+	struct sta_priv *pstapriv = &padapter->stapriv;
+	struct mlme_priv	*pmlmepriv = &padapter->mlmepriv;
+	struct set_assocsta_parm *passocsta_parm = (struct set_assocsta_parm *)(pcmd->parmbuf);
+	struct set_assocsta_rsp *passocsta_rsp = (struct set_assocsta_rsp *)(pcmd->rsp);
+	struct sta_info	*psta = rtw_get_stainfo(pstapriv, passocsta_parm->addr);
+
+
+	if (psta == NULL) {
+		goto exit;
+	}
+
+	psta->cmn.aid = psta->cmn.mac_id = passocsta_rsp->cam_id;
+
+	_enter_critical_bh(&pmlmepriv->lock, &irqL);
+
+	if ((check_fwstate(pmlmepriv, WIFI_MP_STATE) == _TRUE) && (check_fwstate(pmlmepriv, _FW_UNDER_LINKING) == _TRUE))
+		_clr_fwstate_(pmlmepriv, _FW_UNDER_LINKING);
+
+	set_fwstate(pmlmepriv, _FW_LINKED);
+	_exit_critical_bh(&pmlmepriv->lock, &irqL);
+
+exit:
+	rtw_free_cmd_obj(pcmd);
+
+}
+
+void rtw_getrttbl_cmd_cmdrsp_callback(_adapter	*padapter,  struct cmd_obj *pcmd);
+void rtw_getrttbl_cmd_cmdrsp_callback(_adapter	*padapter,  struct cmd_obj *pcmd)
+{
+
+	rtw_free_cmd_obj(pcmd);
+#ifdef CONFIG_MP_INCLUDED
+	if (padapter->registrypriv.mp_mode == 1)
+		padapter->mppriv.workparam.bcompleted = _TRUE;
+#endif
+
+
+}
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/core/rtw_debug.c linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/core/rtw_debug.c
--- linux-5.6.3/3rdparty/rtl8821ce/core/rtw_debug.c	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/core/rtw_debug.c	2020-04-10 16:35:06.773658060 +0300
@@ -0,0 +1,6721 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#define _RTW_DEBUG_C_
+
+#include <drv_types.h>
+#include <hal_data.h>
+
+#ifdef CONFIG_RTW_DEBUG
+const char *rtw_log_level_str[] = {
+	"_DRV_NONE_ = 0",
+	"_DRV_ALWAYS_ = 1",
+	"_DRV_ERR_ = 2",
+	"_DRV_WARNING_ = 3",
+	"_DRV_INFO_ = 4",
+	"_DRV_DEBUG_ = 5",
+	"_DRV_MAX_ = 6",
+};
+#endif
+
+#ifdef CONFIG_DEBUG_RTL871X
+	u64 GlobalDebugComponents = 0;
+#endif /* CONFIG_DEBUG_RTL871X */
+
+#include <rtw_version.h>
+
+#ifdef CONFIG_TDLS
+	#define TDLS_DBG_INFO_SPACE_BTWN_ITEM_AND_VALUE	41
+#endif
+
+void dump_drv_version(void *sel)
+{
+	RTW_PRINT_SEL(sel, "%s %s\n", DRV_NAME, DRIVERVERSION);
+	RTW_PRINT_SEL(sel, "build time: %s %s\n", __DATE__, __TIME__);
+}
+
+void dump_drv_cfg(void *sel)
+{
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 24))
+	char *kernel_version = utsname()->release;
+
+	RTW_PRINT_SEL(sel, "\nKernel Version: %s\n", kernel_version);
+#endif
+
+	RTW_PRINT_SEL(sel, "Driver Version: %s\n", DRIVERVERSION);
+	RTW_PRINT_SEL(sel, "------------------------------------------------\n");
+#ifdef CONFIG_IOCTL_CFG80211
+	RTW_PRINT_SEL(sel, "CFG80211\n");
+#ifdef RTW_USE_CFG80211_STA_EVENT
+	RTW_PRINT_SEL(sel, "RTW_USE_CFG80211_STA_EVENT\n");
+#endif
+	#ifdef CONFIG_RADIO_WORK
+	RTW_PRINT_SEL(sel, "CONFIG_RADIO_WORK\n");
+	#endif
+#else
+	RTW_PRINT_SEL(sel, "WEXT\n");
+#endif
+
+	RTW_PRINT_SEL(sel, "DBG:%d\n", DBG);
+#ifdef CONFIG_RTW_DEBUG
+	RTW_PRINT_SEL(sel, "CONFIG_RTW_DEBUG\n");
+#endif
+
+#ifdef CONFIG_CONCURRENT_MODE
+	RTW_PRINT_SEL(sel, "CONFIG_CONCURRENT_MODE\n");
+#endif
+
+#ifdef CONFIG_POWER_SAVING
+	RTW_PRINT_SEL(sel, "CONFIG_POWER_SAVING\n");
+#endif
+
+#ifdef CONFIG_LOAD_PHY_PARA_FROM_FILE
+	RTW_PRINT_SEL(sel, "LOAD_PHY_PARA_FROM_FILE - REALTEK_CONFIG_PATH=%s\n", REALTEK_CONFIG_PATH);
+	#if defined(CONFIG_MULTIDRV) || defined(REALTEK_CONFIG_PATH_WITH_IC_NAME_FOLDER)
+	RTW_PRINT_SEL(sel, "LOAD_PHY_PARA_FROM_FILE - REALTEK_CONFIG_PATH_WITH_IC_NAME_FOLDER\n");
+	#endif
+
+/* configurations about TX power */
+#ifdef CONFIG_CALIBRATE_TX_POWER_BY_REGULATORY
+	RTW_PRINT_SEL(sel, "CONFIG_CALIBRATE_TX_POWER_BY_REGULATORY\n");
+#endif
+#ifdef CONFIG_CALIBRATE_TX_POWER_TO_MAX
+	RTW_PRINT_SEL(sel, "CONFIG_CALIBRATE_TX_POWER_TO_MAX\n");
+#endif
+#endif
+	RTW_PRINT_SEL(sel, "RTW_DEF_MODULE_REGULATORY_CERT=0x%02x\n", RTW_DEF_MODULE_REGULATORY_CERT);
+
+	RTW_PRINT_SEL(sel, "CONFIG_TXPWR_BY_RATE_EN=%d\n", CONFIG_TXPWR_BY_RATE_EN);
+	RTW_PRINT_SEL(sel, "CONFIG_TXPWR_LIMIT_EN=%d\n", CONFIG_TXPWR_LIMIT_EN);
+
+
+#ifdef CONFIG_DISABLE_ODM
+	RTW_PRINT_SEL(sel, "CONFIG_DISABLE_ODM\n");
+#endif
+
+#ifdef CONFIG_MINIMAL_MEMORY_USAGE
+	RTW_PRINT_SEL(sel, "CONFIG_MINIMAL_MEMORY_USAGE\n");
+#endif
+
+	RTW_PRINT_SEL(sel, "CONFIG_RTW_ADAPTIVITY_EN = %d\n", CONFIG_RTW_ADAPTIVITY_EN);
+#if (CONFIG_RTW_ADAPTIVITY_EN)
+	RTW_PRINT_SEL(sel, "ADAPTIVITY_MODE = %s\n", (CONFIG_RTW_ADAPTIVITY_MODE) ? "carrier_sense" : "normal");
+#endif
+
+#ifdef CONFIG_WOWLAN
+	RTW_PRINT_SEL(sel, "CONFIG_WOWLAN - ");
+
+#ifdef CONFIG_GPIO_WAKEUP
+	RTW_PRINT_SEL(sel, "CONFIG_GPIO_WAKEUP - WAKEUP_GPIO_IDX:%d\n", WAKEUP_GPIO_IDX);
+#endif
+#endif
+
+#ifdef CONFIG_TDLS
+	RTW_PRINT_SEL(sel, "CONFIG_TDLS\n");
+#endif
+
+#ifdef CONFIG_RTW_80211R
+	RTW_PRINT_SEL(sel, "CONFIG_RTW_80211R\n");
+#endif
+
+#ifdef CONFIG_RTW_NETIF_SG
+	RTW_PRINT_SEL(sel, "CONFIG_RTW_NETIF_SG\n");
+#endif
+
+#ifdef CONFIG_RTW_WIFI_HAL
+	RTW_PRINT_SEL(sel, "CONFIG_RTW_WIFI_HAL\n");
+#endif
+
+#ifdef CONFIG_USB_HCI
+#ifdef CONFIG_SUPPORT_USB_INT
+	RTW_PRINT_SEL(sel, "CONFIG_SUPPORT_USB_INT\n");
+#endif
+#ifdef CONFIG_USB_INTERRUPT_IN_PIPE
+	RTW_PRINT_SEL(sel, "CONFIG_USB_INTERRUPT_IN_PIPE\n");
+#endif
+#ifdef CONFIG_USB_TX_AGGREGATION
+	RTW_PRINT_SEL(sel, "CONFIG_USB_TX_AGGREGATION\n");
+#endif
+#ifdef CONFIG_USB_RX_AGGREGATION
+	RTW_PRINT_SEL(sel, "CONFIG_USB_RX_AGGREGATION\n");
+#endif
+#ifdef CONFIG_USE_USB_BUFFER_ALLOC_TX
+	RTW_PRINT_SEL(sel, "CONFIG_USE_USB_BUFFER_ALLOC_TX\n");
+#endif
+#ifdef CONFIG_USE_USB_BUFFER_ALLOC_RX
+	RTW_PRINT_SEL(sel, "CONFIG_USE_USB_BUFFER_ALLOC_RX\n");
+#endif
+#ifdef CONFIG_PREALLOC_RECV_SKB
+	RTW_PRINT_SEL(sel, "CONFIG_PREALLOC_RECV_SKB\n");
+#endif
+#ifdef CONFIG_FIX_NR_BULKIN_BUFFER
+	RTW_PRINT_SEL(sel, "CONFIG_FIX_NR_BULKIN_BUFFER\n");
+#endif
+#endif /*CONFIG_USB_HCI*/
+
+#ifdef CONFIG_SDIO_HCI
+#ifdef CONFIG_TX_AGGREGATION
+	RTW_PRINT_SEL(sel, "CONFIG_TX_AGGREGATION\n");
+#endif
+#ifdef CONFIG_RX_AGGREGATION
+	RTW_PRINT_SEL(sel, "CONFIG_RX_AGGREGATION\n");
+#endif
+#endif /*CONFIG_SDIO_HCI*/
+
+#ifdef CONFIG_PCI_HCI
+#endif
+
+	RTW_PRINT_SEL(sel, "CONFIG_IFACE_NUMBER = %d\n", CONFIG_IFACE_NUMBER);
+#ifdef CONFIG_MI_WITH_MBSSID_CAM
+	RTW_PRINT_SEL(sel, "CONFIG_MI_WITH_MBSSID_CAM\n");
+#endif
+#ifdef CONFIG_SWTIMER_BASED_TXBCN
+	RTW_PRINT_SEL(sel, "CONFIG_SWTIMER_BASED_TXBCN\n");
+#endif
+#ifdef CONFIG_FW_HANDLE_TXBCN
+	RTW_PRINT_SEL(sel, "CONFIG_FW_HANDLE_TXBCN\n");
+	RTW_PRINT_SEL(sel, "CONFIG_LIMITED_AP_NUM = %d\n", CONFIG_LIMITED_AP_NUM);
+#endif
+#ifdef CONFIG_CLIENT_PORT_CFG
+	RTW_PRINT_SEL(sel, "CONFIG_CLIENT_PORT_CFG\n");
+#endif
+
+	RTW_PRINT_SEL(sel, "\n=== XMIT-INFO ===\n");
+	RTW_PRINT_SEL(sel, "NR_XMITFRAME = %d\n", NR_XMITFRAME);
+	RTW_PRINT_SEL(sel, "NR_XMITBUFF = %d\n", NR_XMITBUFF);
+	RTW_PRINT_SEL(sel, "MAX_XMITBUF_SZ = %d\n", MAX_XMITBUF_SZ);
+	RTW_PRINT_SEL(sel, "NR_XMIT_EXTBUFF = %d\n", NR_XMIT_EXTBUFF);
+	RTW_PRINT_SEL(sel, "MAX_XMIT_EXTBUF_SZ = %d\n", MAX_XMIT_EXTBUF_SZ);
+	RTW_PRINT_SEL(sel, "MAX_CMDBUF_SZ = %d\n", MAX_CMDBUF_SZ);
+
+	RTW_PRINT_SEL(sel, "\n=== RECV-INFO ===\n");
+	RTW_PRINT_SEL(sel, "NR_RECVFRAME = %d\n", NR_RECVFRAME);
+	RTW_PRINT_SEL(sel, "NR_RECVBUFF = %d\n", NR_RECVBUFF);
+	RTW_PRINT_SEL(sel, "MAX_RECVBUF_SZ = %d\n", MAX_RECVBUF_SZ);
+
+}
+
+void dump_log_level(void *sel)
+{
+#ifdef CONFIG_RTW_DEBUG
+	int i;
+
+	RTW_PRINT_SEL(sel, "drv_log_level:%d\n", rtw_drv_log_level);
+	for (i = 0; i <= _DRV_MAX_; i++) {
+		if (rtw_log_level_str[i])
+			RTW_PRINT_SEL(sel, "%c %s = %d\n",
+				(rtw_drv_log_level == i) ? '+' : ' ', rtw_log_level_str[i], i);
+	}
+#else
+	RTW_PRINT_SEL(sel, "CONFIG_RTW_DEBUG is disabled\n");
+#endif
+}
+
+#ifdef CONFIG_SDIO_HCI
+void sd_f0_reg_dump(void *sel, _adapter *adapter)
+{
+	int i;
+
+	for (i = 0x0; i <= 0xff; i++) {
+		if (i % 16 == 0)
+			RTW_PRINT_SEL(sel, "0x%02x ", i);
+
+		_RTW_PRINT_SEL(sel, "%02x ", rtw_sd_f0_read8(adapter, i));
+
+		if (i % 16 == 15)
+			_RTW_PRINT_SEL(sel, "\n");
+		else if (i % 8 == 7)
+			_RTW_PRINT_SEL(sel, "\t");
+	}
+}
+
+void sdio_local_reg_dump(void *sel, _adapter *adapter)
+{
+	int i, j = 1;
+
+	for (i = 0x0; i < 0x100; i += 4) {
+		if (j % 4 == 1)
+			RTW_PRINT_SEL(sel, "0x%02x", i);
+		_RTW_PRINT_SEL(sel, " 0x%08x ", rtw_read32(adapter, (0x1025 << 16) | i));
+		if ((j++) % 4 == 0)
+			_RTW_PRINT_SEL(sel, "\n");
+	}
+}
+#endif /* CONFIG_SDIO_HCI */
+
+void mac_reg_dump(void *sel, _adapter *adapter)
+{
+	int i, j = 1;
+
+	RTW_PRINT_SEL(sel, "======= MAC REG =======\n");
+
+	for (i = 0x0; i < 0x800; i += 4) {
+		if (j % 4 == 1)
+			RTW_PRINT_SEL(sel, "0x%04x", i);
+		_RTW_PRINT_SEL(sel, " 0x%08x ", rtw_read32(adapter, i));
+		if ((j++) % 4 == 0)
+			_RTW_PRINT_SEL(sel, "\n");
+	}
+
+#ifdef CONFIG_RTL8814A
+	{
+		for (i = 0x1000; i < 0x1650; i += 4) {
+			if (j % 4 == 1)
+				RTW_PRINT_SEL(sel, "0x%04x", i);
+			_RTW_PRINT_SEL(sel, " 0x%08x ", rtw_read32(adapter, i));
+			if ((j++) % 4 == 0)
+				_RTW_PRINT_SEL(sel, "\n");
+		}
+	}
+#endif /* CONFIG_RTL8814A */
+
+
+#if defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C) ||defined(CONFIG_RTL8192F)
+	for (i = 0x1000; i < 0x1800; i += 4) {
+		if (j % 4 == 1)
+			RTW_PRINT_SEL(sel, "0x%04x", i);
+		_RTW_PRINT_SEL(sel, " 0x%08x ", rtw_read32(adapter, i));
+		if ((j++) % 4 == 0)
+			_RTW_PRINT_SEL(sel, "\n");
+	}
+#endif /* CONFIG_RTL8822B  or 8821c or 8192f*/
+
+}
+
+void bb_reg_dump(void *sel, _adapter *adapter)
+{
+	int i, j = 1;
+
+	RTW_PRINT_SEL(sel, "======= BB REG =======\n");
+	for (i = 0x800; i < 0x1000; i += 4) {
+		if (j % 4 == 1)
+			RTW_PRINT_SEL(sel, "0x%04x", i);
+		_RTW_PRINT_SEL(sel, " 0x%08x ", rtw_read32(adapter, i));
+		if ((j++) % 4 == 0)
+			_RTW_PRINT_SEL(sel, "\n");
+	}
+
+#if defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C)
+	for (i = 0x1800; i < 0x2000; i += 4) {
+		if (j % 4 == 1)
+			RTW_PRINT_SEL(sel, "0x%04x", i);
+		_RTW_PRINT_SEL(sel, " 0x%08x ", rtw_read32(adapter, i));
+		if ((j++) % 4 == 0)
+			_RTW_PRINT_SEL(sel, "\n");
+	}
+#endif /* CONFIG_RTL8822B */
+}
+
+void bb_reg_dump_ex(void *sel, _adapter *adapter)
+{
+	int i;
+
+	RTW_PRINT_SEL(sel, "======= BB REG =======\n");
+	for (i = 0x800; i < 0x1000; i += 4) {
+		RTW_PRINT_SEL(sel, "0x%04x", i);
+		_RTW_PRINT_SEL(sel, " 0x%08x ", rtw_read32(adapter, i));
+		_RTW_PRINT_SEL(sel, "\n");
+	}
+
+#if defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C)
+	for (i = 0x1800; i < 0x2000; i += 4) {
+		RTW_PRINT_SEL(sel, "0x%04x", i);
+		_RTW_PRINT_SEL(sel, " 0x%08x ", rtw_read32(adapter, i));
+		_RTW_PRINT_SEL(sel, "\n");
+	}
+#endif /* CONFIG_RTL8822B */
+}
+
+void rf_reg_dump(void *sel, _adapter *adapter)
+{
+	int i, j = 1, path;
+	u32 value;
+	u8 rf_type = 0;
+	u8 path_nums = 0;
+
+	rtw_hal_get_hwreg(adapter, HW_VAR_RF_TYPE, (u8 *)(&rf_type));
+	if ((RF_1T2R == rf_type) || (RF_1T1R == rf_type))
+		path_nums = 1;
+	else
+		path_nums = 2;
+
+	RTW_PRINT_SEL(sel, "======= RF REG =======\n");
+
+	for (path = 0; path < path_nums; path++) {
+		RTW_PRINT_SEL(sel, "RF_Path(%x)\n", path);
+		for (i = 0; i < 0x100; i++) {
+			value = rtw_hal_read_rfreg(adapter, path, i, 0xffffffff);
+			if (j % 4 == 1)
+				RTW_PRINT_SEL(sel, "0x%02x ", i);
+			_RTW_PRINT_SEL(sel, " 0x%08x ", value);
+			if ((j++) % 4 == 0)
+				_RTW_PRINT_SEL(sel, "\n");
+		}
+	}
+}
+
+void rtw_sink_rtp_seq_dbg(_adapter *adapter, u8 *ehdr_pos)
+{
+	struct recv_priv *precvpriv = &(adapter->recvpriv);
+	if (precvpriv->sink_udpport > 0) {
+		if (*((u16 *)(ehdr_pos + 0x24)) == cpu_to_be16(precvpriv->sink_udpport)) {
+			precvpriv->pre_rtp_rxseq = precvpriv->cur_rtp_rxseq;
+			precvpriv->cur_rtp_rxseq = be16_to_cpu(*((u16 *)(ehdr_pos + 0x2C)));
+			if (precvpriv->pre_rtp_rxseq + 1 != precvpriv->cur_rtp_rxseq)
+				RTW_INFO("%s : RTP Seq num from %d to %d\n", __FUNCTION__, precvpriv->pre_rtp_rxseq, precvpriv->cur_rtp_rxseq);
+		}
+	}
+}
+
+void sta_rx_reorder_ctl_dump(void *sel, struct sta_info *sta)
+{
+	struct recv_reorder_ctrl *reorder_ctl;
+	int i;
+
+	for (i = 0; i < 16; i++) {
+		reorder_ctl = &sta->recvreorder_ctrl[i];
+		if (reorder_ctl->ampdu_size != RX_AMPDU_SIZE_INVALID || reorder_ctl->indicate_seq != 0xFFFF) {
+			RTW_PRINT_SEL(sel, "tid=%d, enable=%d, ampdu_size=%u, indicate_seq=%u\n"
+				, i, reorder_ctl->enable, reorder_ctl->ampdu_size, reorder_ctl->indicate_seq
+				     );
+		}
+	}
+}
+
+void dump_tx_rate_bmp(void *sel, struct dvobj_priv *dvobj)
+{
+	_adapter *adapter = dvobj_get_primary_adapter(dvobj);
+	struct rf_ctl_t *rfctl = dvobj_to_rfctl(dvobj);
+	u8 bw;
+
+	RTW_PRINT_SEL(sel, "%-6s", "bw");
+	if (hal_chk_proto_cap(adapter, PROTO_CAP_11AC))
+		_RTW_PRINT_SEL(sel, " %-11s", "vht");
+
+	_RTW_PRINT_SEL(sel, " %-11s %-4s %-3s\n", "ht", "ofdm", "cck");
+
+	for (bw = CHANNEL_WIDTH_20; bw <= CHANNEL_WIDTH_160; bw++) {
+		if (!hal_is_bw_support(adapter, bw))
+			continue;
+
+		RTW_PRINT_SEL(sel, "%6s", ch_width_str(bw));
+		if (hal_chk_proto_cap(adapter, PROTO_CAP_11AC)) {
+			_RTW_PRINT_SEL(sel, " %03x %03x %03x"
+				, RATE_BMP_GET_VHT_3SS(rfctl->rate_bmp_vht_by_bw[bw])
+				, RATE_BMP_GET_VHT_2SS(rfctl->rate_bmp_vht_by_bw[bw])
+				, RATE_BMP_GET_VHT_1SS(rfctl->rate_bmp_vht_by_bw[bw])
+			);
+		}
+
+		_RTW_PRINT_SEL(sel, " %02x %02x %02x %02x"
+			, bw <= CHANNEL_WIDTH_40 ? RATE_BMP_GET_HT_4SS(rfctl->rate_bmp_ht_by_bw[bw]) : 0
+			, bw <= CHANNEL_WIDTH_40 ? RATE_BMP_GET_HT_3SS(rfctl->rate_bmp_ht_by_bw[bw]) : 0
+			, bw <= CHANNEL_WIDTH_40 ? RATE_BMP_GET_HT_2SS(rfctl->rate_bmp_ht_by_bw[bw]) : 0
+			, bw <= CHANNEL_WIDTH_40 ? RATE_BMP_GET_HT_1SS(rfctl->rate_bmp_ht_by_bw[bw]) : 0
+		);
+
+		_RTW_PRINT_SEL(sel, "  %03x   %01x\n"
+			, bw <= CHANNEL_WIDTH_20 ? RATE_BMP_GET_OFDM(rfctl->rate_bmp_cck_ofdm) : 0
+			, bw <= CHANNEL_WIDTH_20 ? RATE_BMP_GET_CCK(rfctl->rate_bmp_cck_ofdm) : 0
+		);
+	}
+}
+
+void dump_adapters_status(void *sel, struct dvobj_priv *dvobj)
+{
+	struct rf_ctl_t *rfctl = dvobj_to_rfctl(dvobj);
+	int i;
+	_adapter *iface;
+	u8 u_ch, u_bw, u_offset;
+#if (defined(CONFIG_SUPPORT_MULTI_BCN) && defined(CONFIG_FW_HANDLE_TXBCN)) || defined(CONFIG_CLIENT_PORT_CFG)
+	char str_val[64] = {'\0'};
+#endif
+	dump_mi_status(sel, dvobj);
+
+#if defined(CONFIG_SUPPORT_MULTI_BCN) && defined(CONFIG_FW_HANDLE_TXBCN)
+	RTW_PRINT_SEL(sel, "[AP] LIMITED_AP_NUM:%d\n", CONFIG_LIMITED_AP_NUM);
+	RTW_PRINT_SEL(sel, "[AP] vap_map:0x%02x\n", dvobj->vap_map);
+#endif
+#ifdef CONFIG_HW_P0_TSF_SYNC
+	RTW_PRINT_SEL(sel, "[AP] p0 tsf sync port = %d\n", dvobj->p0_tsf.sync_port);
+	RTW_PRINT_SEL(sel, "[AP] p0 tsf timer offset = %d\n", dvobj->p0_tsf.offset);
+#endif
+#ifdef CONFIG_CLIENT_PORT_CFG
+	RTW_PRINT_SEL(sel, "[CLT] clt_num = %d\n", dvobj->clt_port.num);
+	RTW_PRINT_SEL(sel, "[CLT] clt_map = 0x%02x\n", dvobj->clt_port.bmp);
+#endif
+#ifdef CONFIG_FW_MULTI_PORT_SUPPORT
+	RTW_PRINT_SEL(sel, "[MI] default port id:%d\n\n", dvobj->dft.port_id);
+#endif /* CONFIG_FW_MULTI_PORT_SUPPORT */
+
+	RTW_PRINT_SEL(sel, "dev status:%s%s\n\n"
+		, dev_is_surprise_removed(dvobj) ? " SR" : ""
+		, dev_is_drv_stopped(dvobj) ? " DS" : ""
+	);
+
+#ifdef CONFIG_P2P
+#define P2P_INFO_TITLE_FMT	" %-3s %-4s"
+#define P2P_INFO_TITLE_ARG	, "lch", "p2ps"
+#ifdef CONFIG_IOCTL_CFG80211
+#define P2P_INFO_VALUE_FMT	" %3u %c%3u"
+#define P2P_INFO_VALUE_ARG	, iface->wdinfo.listen_channel, iface->wdev_data.p2p_enabled ? 'e' : ' ', rtw_p2p_state(&iface->wdinfo)
+#else
+#define P2P_INFO_VALUE_FMT	" %3u %4u"
+#define P2P_INFO_VALUE_ARG	, iface->wdinfo.listen_channel, rtw_p2p_state(&iface->wdinfo)
+#endif
+#define P2P_INFO_DASH		"---------"
+#else
+#define P2P_INFO_TITLE_FMT	""
+#define P2P_INFO_TITLE_ARG
+#define P2P_INFO_VALUE_FMT	""
+#define P2P_INFO_VALUE_ARG
+#define P2P_INFO_DASH
+#endif
+
+#ifdef DBG_TSF_UPDATE
+#define TSF_PAUSE_TIME_TITLE_FMT " %-5s"
+#define TSF_PAUSE_TIME_TITLE_ARG , "tsfup"
+#define TSF_PAUSE_TIME_VALUE_FMT " %5d"
+#define TSF_PAUSE_TIME_VALUE_ARG , ((iface->mlmeextpriv.tsf_update_required && iface->mlmeextpriv.tsf_update_pause_stime) ? (rtw_get_passing_time_ms(iface->mlmeextpriv.tsf_update_pause_stime) > 99999 ? 99999 : rtw_get_passing_time_ms(iface->mlmeextpriv.tsf_update_pause_stime)) : 0)
+#else
+#define TSF_PAUSE_TIME_TITLE_FMT ""
+#define TSF_PAUSE_TIME_TITLE_ARG
+#define TSF_PAUSE_TIME_VALUE_FMT ""
+#define TSF_PAUSE_TIME_VALUE_ARG
+#endif
+
+#if (defined(CONFIG_SUPPORT_MULTI_BCN) && defined(CONFIG_FW_HANDLE_TXBCN)) || defined(CONFIG_CLIENT_PORT_CFG)
+#define INFO_FMT	" %-4s"
+#define INFO_ARG	, "info"
+#define INFO_CNT_FMT	" %-20s"
+#define INFO_CNT_ARG	, str_val
+#else
+#define INFO_FMT	""
+#define INFO_ARG
+#define INFO_CNT_FMT	""
+#define INFO_CNT_ARG
+#endif
+
+	RTW_PRINT_SEL(sel, "%-2s %-15s %c %-3s %-3s %-3s %-17s %-4s %-7s"
+		P2P_INFO_TITLE_FMT
+		TSF_PAUSE_TIME_TITLE_FMT
+		" %s"INFO_FMT"\n"
+		, "id", "ifname", ' ', "bup", "nup", "ncd", "macaddr", "port", "ch"
+		P2P_INFO_TITLE_ARG
+		TSF_PAUSE_TIME_TITLE_ARG
+		, "status"INFO_ARG);
+
+	RTW_PRINT_SEL(sel, "---------------------------------------------------------------"
+		P2P_INFO_DASH
+		"-------\n");
+
+	for (i = 0; i < dvobj->iface_nums; i++) {
+		iface = dvobj->padapters[i];
+		if (iface) {
+			#if (defined(CONFIG_SUPPORT_MULTI_BCN) && defined(CONFIG_FW_HANDLE_TXBCN)) || defined(CONFIG_CLIENT_PORT_CFG)
+			_rtw_memset(&str_val, '\0', sizeof(str_val));
+			#endif
+			#if defined(CONFIG_SUPPORT_MULTI_BCN) && defined(CONFIG_FW_HANDLE_TXBCN)
+			if (MLME_IS_AP(iface) || MLME_IS_MESH(iface)) {
+				u8 len;
+				char *p = str_val;
+				char tmp_str[10] = {'\0'};
+
+				len = snprintf(tmp_str, sizeof(tmp_str), "%s", "ap_id:");
+				strncpy(p, tmp_str, len);
+				p += len;
+				_rtw_memset(&tmp_str, '\0', sizeof(tmp_str));
+				#ifdef DBG_HW_PORT
+				len = snprintf(tmp_str, sizeof(tmp_str), "%d (%d,%d)", iface->vap_id, iface->hw_port, iface->client_port);
+				#else
+				len = snprintf(tmp_str, sizeof(tmp_str), "%d", iface->vap_id);
+				#endif
+				strncpy(p, tmp_str, len);
+			}
+			#endif
+			#ifdef CONFIG_CLIENT_PORT_CFG
+			if (MLME_IS_STA(iface)) {
+				u8 len;
+				char *p = str_val;
+				char tmp_str[10] = {'\0'};
+
+				len = snprintf(tmp_str, sizeof(tmp_str), "%s", "c_pid:");
+				strncpy(p, tmp_str, len);
+				p += len;
+				_rtw_memset(&tmp_str, '\0', sizeof(tmp_str));
+				#ifdef DBG_HW_PORT
+				len = snprintf(tmp_str, sizeof(tmp_str), "%d (%d,%d)", iface->client_port, iface->hw_port, iface->client_port);
+				#else
+				len = snprintf(tmp_str, sizeof(tmp_str), "%d", iface->client_port);
+				#endif
+				strncpy(p, tmp_str, len);
+			}
+			#endif
+
+			RTW_PRINT_SEL(sel, "%2d %-15s %c %3u %3u %3u "MAC_FMT" %4hhu %3u,%u,%u"
+				P2P_INFO_VALUE_FMT
+				TSF_PAUSE_TIME_VALUE_FMT
+				" "MLME_STATE_FMT" " INFO_CNT_FMT"\n"
+				, i, iface->registered ? ADPT_ARG(iface) : NULL
+				, iface->registered ? 'R' : ' '
+				, iface->bup
+				, iface->netif_up
+				, iface->net_closed
+				, MAC_ARG(adapter_mac_addr(iface))
+				, rtw_hal_get_port(iface)
+				, iface->mlmeextpriv.cur_channel
+				, iface->mlmeextpriv.cur_bwmode
+				, iface->mlmeextpriv.cur_ch_offset
+				P2P_INFO_VALUE_ARG
+				TSF_PAUSE_TIME_VALUE_ARG
+				, MLME_STATE_ARG(iface)
+				INFO_CNT_ARG
+			);
+		}
+	}
+
+	RTW_PRINT_SEL(sel, "---------------------------------------------------------------"
+		P2P_INFO_DASH
+		"-------\n");
+
+	rtw_mi_get_ch_setting_union(dvobj_get_primary_adapter(dvobj), &u_ch, &u_bw, &u_offset);
+	RTW_PRINT_SEL(sel, "%55s %3u,%u,%u\n"
+		, "union:"
+		, u_ch, u_bw, u_offset
+	);
+
+	RTW_PRINT_SEL(sel, "%55s %3u,%u,%u offch_state:%d\n"
+		, "oper:"
+		, dvobj->oper_channel
+		, dvobj->oper_bwmode
+		, dvobj->oper_ch_offset
+		, rfctl->offch_state
+	);
+
+#ifdef CONFIG_DFS_MASTER
+	if (rfctl->radar_detect_ch != 0) {
+		RTW_PRINT_SEL(sel, "%55s %3u,%u,%u"
+			, "radar_detect:"
+			, rfctl->radar_detect_ch
+			, rfctl->radar_detect_bw
+			, rfctl->radar_detect_offset
+		);
+
+		if (rfctl->radar_detect_by_others)
+			_RTW_PRINT_SEL(sel, ", by AP of STA link");
+		else {
+			u32 non_ocp_ms;
+			u32 cac_ms;
+			u8 dfs_domain = rtw_odm_get_dfs_domain(dvobj);
+
+			_RTW_PRINT_SEL(sel, ", domain:%u", dfs_domain);
+
+			rtw_get_ch_waiting_ms(rfctl
+				, rfctl->radar_detect_ch
+				, rfctl->radar_detect_bw
+				, rfctl->radar_detect_offset
+				, &non_ocp_ms
+				, &cac_ms
+			);
+
+			if (non_ocp_ms)
+				_RTW_PRINT_SEL(sel, ", non_ocp:%d", non_ocp_ms);
+			if (cac_ms)
+				_RTW_PRINT_SEL(sel, ", cac:%d", cac_ms);
+		}
+
+end_dfs_master:
+		_RTW_PRINT_SEL(sel, "\n");
+	}
+#endif /* CONFIG_DFS_MASTER */
+}
+
+#define SEC_CAM_ENT_ID_TITLE_FMT "%-2s"
+#define SEC_CAM_ENT_ID_TITLE_ARG "id"
+#define SEC_CAM_ENT_ID_VALUE_FMT "%2u"
+#define SEC_CAM_ENT_ID_VALUE_ARG(id) (id)
+
+#define SEC_CAM_ENT_TITLE_FMT "%-6s %-17s %-32s %-3s %-7s %-2s %-2s %-5s"
+#define SEC_CAM_ENT_TITLE_ARG "ctrl", "addr", "key", "kid", "type", "MK", "GK", "valid"
+#define SEC_CAM_ENT_VALUE_FMT "0x%04x "MAC_FMT" "KEY_FMT" %3u %-7s %2u %2u %5u"
+#define SEC_CAM_ENT_VALUE_ARG(ent) \
+	(ent)->ctrl \
+	, MAC_ARG((ent)->mac) \
+	, KEY_ARG((ent)->key) \
+	, ((ent)->ctrl) & 0x03 \
+	, security_type_str((((ent)->ctrl) >> 2) & 0x07) \
+	, (((ent)->ctrl) >> 5) & 0x01 \
+	, (((ent)->ctrl) >> 6) & 0x01 \
+	, (((ent)->ctrl) >> 15) & 0x01
+
+void dump_sec_cam_ent(void *sel, struct sec_cam_ent *ent, int id)
+{
+	if (id >= 0) {
+		RTW_PRINT_SEL(sel, SEC_CAM_ENT_ID_VALUE_FMT " " SEC_CAM_ENT_VALUE_FMT"\n"
+			, SEC_CAM_ENT_ID_VALUE_ARG(id), SEC_CAM_ENT_VALUE_ARG(ent));
+	} else
+		RTW_PRINT_SEL(sel, SEC_CAM_ENT_VALUE_FMT"\n", SEC_CAM_ENT_VALUE_ARG(ent));
+}
+
+void dump_sec_cam_ent_title(void *sel, u8 has_id)
+{
+	if (has_id) {
+		RTW_PRINT_SEL(sel, SEC_CAM_ENT_ID_TITLE_FMT " " SEC_CAM_ENT_TITLE_FMT"\n"
+			, SEC_CAM_ENT_ID_TITLE_ARG, SEC_CAM_ENT_TITLE_ARG);
+	} else
+		RTW_PRINT_SEL(sel, SEC_CAM_ENT_TITLE_FMT"\n", SEC_CAM_ENT_TITLE_ARG);
+}
+
+void dump_sec_cam(void *sel, _adapter *adapter)
+{
+	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
+	struct cam_ctl_t *cam_ctl = &dvobj->cam_ctl;
+	struct sec_cam_ent ent;
+	int i;
+
+	RTW_PRINT_SEL(sel, "HW sec cam:\n");
+	dump_sec_cam_ent_title(sel, 1);
+	for (i = 0; i < cam_ctl->num; i++) {
+		rtw_sec_read_cam_ent(adapter, i, (u8 *)(&ent.ctrl), ent.mac, ent.key);
+		dump_sec_cam_ent(sel , &ent, i);
+	}
+}
+
+void dump_sec_cam_cache(void *sel, _adapter *adapter)
+{
+	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
+	struct cam_ctl_t *cam_ctl = &dvobj->cam_ctl;
+	int i;
+
+	RTW_PRINT_SEL(sel, "SW sec cam cache:\n");
+	dump_sec_cam_ent_title(sel, 1);
+	for (i = 0; i < cam_ctl->num; i++) {
+		if (dvobj->cam_cache[i].ctrl != 0)
+			dump_sec_cam_ent(sel, &dvobj->cam_cache[i], i);
+	}
+
+}
+
+#ifdef CONFIG_PROC_DEBUG
+ssize_t proc_set_write_reg(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
+{
+	struct net_device *dev = data;
+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
+	char tmp[32];
+	u32 addr, val, len;
+
+	if (count < 3) {
+		RTW_INFO("argument size is less than 3\n");
+		return -EFAULT;
+	}
+
+	if (count > sizeof(tmp)) {
+		rtw_warn_on(1);
+		return -EFAULT;
+	}
+
+	if (buffer && !copy_from_user(tmp, buffer, count)) {
+
+		int num = sscanf(tmp, "%x %x %x", &addr, &val, &len);
+
+		if (num !=  3) {
+			RTW_INFO("invalid write_reg parameter!\n");
+			return count;
+		}
+
+		switch (len) {
+		case 1:
+			rtw_write8(padapter, addr, (u8)val);
+			break;
+		case 2:
+			rtw_write16(padapter, addr, (u16)val);
+			break;
+		case 4:
+			rtw_write32(padapter, addr, val);
+			break;
+		default:
+			RTW_INFO("error write length=%d", len);
+			break;
+		}
+
+	}
+
+	return count;
+
+}
+
+static u32 proc_get_read_addr = 0xeeeeeeee;
+static u32 proc_get_read_len = 0x4;
+
+int proc_get_read_reg(struct seq_file *m, void *v)
+{
+	struct net_device *dev = m->private;
+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
+
+	if (proc_get_read_addr == 0xeeeeeeee) {
+		RTW_PRINT_SEL(m, "address not initialized\n");
+		return 0;
+	}
+
+	switch (proc_get_read_len) {
+	case 1:
+		RTW_PRINT_SEL(m, "rtw_read8(0x%x)=0x%x\n", proc_get_read_addr, rtw_read8(padapter, proc_get_read_addr));
+		break;
+	case 2:
+		RTW_PRINT_SEL(m, "rtw_read16(0x%x)=0x%x\n", proc_get_read_addr, rtw_read16(padapter, proc_get_read_addr));
+		break;
+	case 4:
+		RTW_PRINT_SEL(m, "rtw_read32(0x%x)=0x%x\n", proc_get_read_addr, rtw_read32(padapter, proc_get_read_addr));
+		break;
+	default:
+		RTW_PRINT_SEL(m, "error read length=%d\n", proc_get_read_len);
+		break;
+	}
+
+	return 0;
+}
+
+ssize_t proc_set_read_reg(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
+{
+	char tmp[16];
+	u32 addr, len;
+
+	if (count < 2) {
+		RTW_INFO("argument size is less than 2\n");
+		return -EFAULT;
+	}
+
+	if (count > sizeof(tmp)) {
+		rtw_warn_on(1);
+		return -EFAULT;
+	}
+
+	if (buffer && !copy_from_user(tmp, buffer, count)) {
+
+		int num = sscanf(tmp, "%x %x", &addr, &len);
+
+		if (num !=  2) {
+			RTW_INFO("invalid read_reg parameter!\n");
+			return count;
+		}
+
+		proc_get_read_addr = addr;
+
+		proc_get_read_len = len;
+	}
+
+	return count;
+
+}
+
+int proc_get_rx_stat(struct seq_file *m, void *v)
+{
+	_irqL	 irqL;
+	_list	*plist, *phead;
+	struct net_device *dev = m->private;
+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
+	struct sta_info *psta = NULL;
+	struct stainfo_stats	*pstats = NULL;
+	struct sta_priv		*pstapriv = &(adapter->stapriv);
+	u32 i, j;
+	u8 bc_addr[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
+	u8 null_addr[ETH_ALEN] = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00};
+
+	_enter_critical_bh(&pstapriv->sta_hash_lock, &irqL);
+	for (i = 0; i < NUM_STA; i++) {
+		phead = &(pstapriv->sta_hash[i]);
+		plist = get_next(phead);
+		while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) {
+			psta = LIST_CONTAINOR(plist, struct sta_info, hash_list);
+			plist = get_next(plist);
+			pstats = &psta->sta_stats;
+
+			if (pstats == NULL)
+				continue;
+			if ((_rtw_memcmp(psta->cmn.mac_addr, bc_addr, ETH_ALEN) !=  _TRUE)
+				&& (_rtw_memcmp(psta->cmn.mac_addr, null_addr, ETH_ALEN) != _TRUE)
+				&& (_rtw_memcmp(psta->cmn.mac_addr, adapter_mac_addr(adapter), ETH_ALEN) != _TRUE)) {
+				RTW_PRINT_SEL(m, "MAC :\t\t"MAC_FMT "\n", MAC_ARG(psta->cmn.mac_addr));
+				RTW_PRINT_SEL(m, "data_rx_cnt :\t%llu\n", sta_rx_data_uc_pkts(psta) - pstats->last_rx_data_uc_pkts);
+				pstats->last_rx_data_uc_pkts = sta_rx_data_uc_pkts(psta);
+				RTW_PRINT_SEL(m, "duplicate_cnt :\t%u\n", pstats->duplicate_cnt);
+				pstats->duplicate_cnt = 0;
+				RTW_PRINT_SEL(m, "rx_per_rate_cnt :\n");
+
+				for (j = 0; j < 0x60; j++) {
+					RTW_PRINT_SEL(m, "%08u  ", pstats->rxratecnt[j]);
+					pstats->rxratecnt[j] = 0;
+					if ((j%8) == 7)
+						RTW_PRINT_SEL(m, "\n");
+				}
+				RTW_PRINT_SEL(m, "\n");
+			}
+		}
+	}
+	_exit_critical_bh(&pstapriv->sta_hash_lock, &irqL);
+	return 0;
+}
+
+int proc_get_tx_stat(struct seq_file *m, void *v)
+{
+	_irqL	irqL;
+	_list	*plist, *phead;
+	struct net_device *dev = m->private;
+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
+	struct sta_info *psta = NULL;
+	u8 sta_mac[NUM_STA][ETH_ALEN] = {{0}};
+	uint mac_id[NUM_STA];
+	struct stainfo_stats	*pstats = NULL;
+	struct sta_priv	*pstapriv = &(adapter->stapriv);
+	struct sta_priv	*pstapriv_primary = &(GET_PRIMARY_ADAPTER(adapter))->stapriv;
+	u32 i, macid_rec_idx = 0;
+	u8 bc_addr[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
+	u8 null_addr[ETH_ALEN] = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00};
+	struct submit_ctx gotc2h;
+
+	_enter_critical_bh(&pstapriv->sta_hash_lock, &irqL);
+	for (i = 0; i < NUM_STA; i++) {
+		phead = &(pstapriv->sta_hash[i]);
+		plist = get_next(phead);
+		while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) {
+			psta = LIST_CONTAINOR(plist, struct sta_info, hash_list);
+			plist = get_next(plist);
+			if ((_rtw_memcmp(psta->cmn.mac_addr, bc_addr, ETH_ALEN) !=  _TRUE)
+				&& (_rtw_memcmp(psta->cmn.mac_addr, null_addr, ETH_ALEN) != _TRUE)
+				&& (_rtw_memcmp(psta->cmn.mac_addr, adapter_mac_addr(adapter), ETH_ALEN) != _TRUE)) {
+				_rtw_memcpy(&sta_mac[macid_rec_idx][0], psta->cmn.mac_addr, ETH_ALEN);
+				mac_id[macid_rec_idx] = psta->cmn.mac_id;
+				macid_rec_idx++;
+			}
+		}
+	}
+	_exit_critical_bh(&pstapriv->sta_hash_lock, &irqL);
+	for (i = 0; i < macid_rec_idx; i++) {
+		_rtw_memcpy(pstapriv_primary->c2h_sta_mac, &sta_mac[i][0], ETH_ALEN);
+		pstapriv_primary->c2h_adapter_id = adapter->iface_id;
+		rtw_sctx_init(&gotc2h, 60);
+		pstapriv_primary->gotc2h = &gotc2h;
+		rtw_hal_reqtxrpt(adapter, mac_id[i]);
+		if (rtw_sctx_wait(&gotc2h, __func__)) {
+			psta = rtw_get_stainfo(pstapriv, &sta_mac[i][0]);
+			if(psta) {
+				pstats = &psta->sta_stats;
+#ifndef ROKU_PRIVATE
+				RTW_PRINT_SEL(m, "data_sent_cnt :\t%u\n", pstats->tx_ok_cnt + pstats->tx_fail_cnt);
+				RTW_PRINT_SEL(m, "success_cnt :\t%u\n", pstats->tx_ok_cnt);
+				RTW_PRINT_SEL(m, "failure_cnt :\t%u\n", pstats->tx_fail_cnt);
+				RTW_PRINT_SEL(m, "retry_cnt :\t%u\n\n", pstats->tx_retry_cnt);
+#else
+				RTW_PRINT_SEL(m, "MAC: " MAC_FMT " sent: %u fail: %u retry: %u\n",
+				MAC_ARG(&sta_mac[i][0]), pstats->tx_ok_cnt, pstats->tx_fail_cnt, pstats->tx_retry_cnt);
+#endif /* ROKU_PRIVATE */
+
+			} else
+				RTW_PRINT_SEL(m, "STA is gone\n");
+		} else {
+			//to avoid c2h modify counters
+			pstapriv_primary->gotc2h = NULL;
+			_rtw_memset(pstapriv_primary->c2h_sta_mac, 0, ETH_ALEN);
+			pstapriv_primary->c2h_adapter_id = CONFIG_IFACE_NUMBER;
+			RTW_PRINT_SEL(m, "Warming : Query timeout, operation abort!!\n");
+			break;
+		}
+		pstapriv_primary->gotc2h = NULL;
+		_rtw_memset(pstapriv_primary->c2h_sta_mac, 0, ETH_ALEN);
+		pstapriv_primary->c2h_adapter_id = CONFIG_IFACE_NUMBER;
+	}
+	return 0;
+}
+
+int proc_get_fwstate(struct seq_file *m, void *v)
+{
+	struct net_device *dev = m->private;
+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
+	struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
+
+	RTW_PRINT_SEL(m, "fwstate=0x%x\n", get_fwstate(pmlmepriv));
+
+	return 0;
+}
+
+int proc_get_sec_info(struct seq_file *m, void *v)
+{
+	struct net_device *dev = m->private;
+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
+	struct security_priv *sec = &padapter->securitypriv;
+
+	RTW_PRINT_SEL(m, "auth_alg=0x%x, enc_alg=0x%x, auth_type=0x%x, enc_type=0x%x\n",
+		sec->dot11AuthAlgrthm, sec->dot11PrivacyAlgrthm,
+		sec->ndisauthtype, sec->ndisencryptstatus);
+
+	RTW_PRINT_SEL(m, "hw_decrypted=%d\n", sec->hw_decrypted);
+
+#ifdef DBG_SW_SEC_CNT
+	RTW_PRINT_SEL(m, "wep_sw_enc_cnt=%llu, %llu, %llu\n"
+		, sec->wep_sw_enc_cnt_bc , sec->wep_sw_enc_cnt_mc, sec->wep_sw_enc_cnt_uc);
+	RTW_PRINT_SEL(m, "wep_sw_dec_cnt=%llu, %llu, %llu\n"
+		, sec->wep_sw_dec_cnt_bc , sec->wep_sw_dec_cnt_mc, sec->wep_sw_dec_cnt_uc);
+
+	RTW_PRINT_SEL(m, "tkip_sw_enc_cnt=%llu, %llu, %llu\n"
+		, sec->tkip_sw_enc_cnt_bc , sec->tkip_sw_enc_cnt_mc, sec->tkip_sw_enc_cnt_uc);
+	RTW_PRINT_SEL(m, "tkip_sw_dec_cnt=%llu, %llu, %llu\n"
+		, sec->tkip_sw_dec_cnt_bc , sec->tkip_sw_dec_cnt_mc, sec->tkip_sw_dec_cnt_uc);
+
+	RTW_PRINT_SEL(m, "aes_sw_enc_cnt=%llu, %llu, %llu\n"
+		, sec->aes_sw_enc_cnt_bc , sec->aes_sw_enc_cnt_mc, sec->aes_sw_enc_cnt_uc);
+	RTW_PRINT_SEL(m, "aes_sw_dec_cnt=%llu, %llu, %llu\n"
+		, sec->aes_sw_dec_cnt_bc , sec->aes_sw_dec_cnt_mc, sec->aes_sw_dec_cnt_uc);
+#endif /* DBG_SW_SEC_CNT */
+
+	return 0;
+}
+
+int proc_get_mlmext_state(struct seq_file *m, void *v)
+{
+	struct net_device *dev = m->private;
+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
+	struct mlme_ext_priv	*pmlmeext = &padapter->mlmeextpriv;
+	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
+
+	RTW_PRINT_SEL(m, "pmlmeinfo->state=0x%x\n", pmlmeinfo->state);
+
+	return 0;
+}
+
+#ifdef CONFIG_LAYER2_ROAMING
+int proc_get_roam_flags(struct seq_file *m, void *v)
+{
+	struct net_device *dev = m->private;
+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
+
+	RTW_PRINT_SEL(m, "0x%02x\n", rtw_roam_flags(adapter));
+
+	return 0;
+}
+
+ssize_t proc_set_roam_flags(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
+{
+	struct net_device *dev = data;
+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
+
+	char tmp[32];
+	u8 flags;
+
+	if (count < 1)
+		return -EFAULT;
+
+	if (count > sizeof(tmp)) {
+		rtw_warn_on(1);
+		return -EFAULT;
+	}
+
+	if (buffer && !copy_from_user(tmp, buffer, count)) {
+
+		int num = sscanf(tmp, "%hhx", &flags);
+
+		if (num == 1)
+			rtw_assign_roam_flags(adapter, flags);
+	}
+
+	return count;
+
+}
+
+int proc_get_roam_param(struct seq_file *m, void *v)
+{
+	struct net_device *dev = m->private;
+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
+	struct mlme_priv *mlme = &adapter->mlmepriv;
+
+	RTW_PRINT_SEL(m, "%12s %15s %26s %16s\n", "rssi_diff_th", "scanr_exp_ms", "scan_interval(unit:2 sec)", "rssi_threshold");
+	RTW_PRINT_SEL(m, "%-15u %-13u %-27u %-11u\n"
+		, mlme->roam_rssi_diff_th
+		, mlme->roam_scanr_exp_ms
+		, mlme->roam_scan_int
+		, mlme->roam_rssi_threshold
+	);
+
+	return 0;
+}
+
+ssize_t proc_set_roam_param(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
+{
+	struct net_device *dev = data;
+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
+	struct mlme_priv *mlme = &adapter->mlmepriv;
+
+	char tmp[32];
+	u8 rssi_diff_th;
+	u32 scanr_exp_ms;
+	u32 scan_int;
+	u8 rssi_threshold;
+
+	if (count < 1)
+		return -EFAULT;
+
+	if (count > sizeof(tmp)) {
+		rtw_warn_on(1);
+		return -EFAULT;
+	}
+
+	if (buffer && !copy_from_user(tmp, buffer, count)) {
+
+		int num = sscanf(tmp, "%hhu %u %u %hhu", &rssi_diff_th, &scanr_exp_ms, &scan_int, &rssi_threshold);
+
+		if (num >= 1)
+			mlme->roam_rssi_diff_th = rssi_diff_th;
+		if (num >= 2)
+			mlme->roam_scanr_exp_ms = scanr_exp_ms;
+		if (num >= 3)
+			mlme->roam_scan_int = scan_int;
+		if (num >= 4)
+			mlme->roam_rssi_threshold = rssi_threshold;
+	}
+
+	return count;
+
+}
+
+ssize_t proc_set_roam_tgt_addr(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
+{
+	struct net_device *dev = data;
+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
+
+	char tmp[32];
+	u8 addr[ETH_ALEN];
+
+	if (count < 1)
+		return -EFAULT;
+
+	if (count > sizeof(tmp)) {
+		rtw_warn_on(1);
+		return -EFAULT;
+	}
+
+	if (buffer && !copy_from_user(tmp, buffer, count)) {
+
+		int num = sscanf(tmp, "%hhx:%hhx:%hhx:%hhx:%hhx:%hhx", addr, addr + 1, addr + 2, addr + 3, addr + 4, addr + 5);
+		if (num == 6)
+			_rtw_memcpy(adapter->mlmepriv.roam_tgt_addr, addr, ETH_ALEN);
+
+		RTW_INFO("set roam_tgt_addr to "MAC_FMT"\n", MAC_ARG(adapter->mlmepriv.roam_tgt_addr));
+	}
+
+	return count;
+}
+#endif /* CONFIG_LAYER2_ROAMING */
+
+#ifdef CONFIG_RTW_80211R
+ssize_t proc_set_ft_flags(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
+{
+	struct net_device *dev = data;
+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
+
+	char tmp[32];
+	u8 flags;
+
+	if (count < 1)
+		return -EFAULT;
+
+	if (count > sizeof(tmp)) {
+		rtw_warn_on(1);
+		return -EFAULT;
+	}
+
+	if (buffer && !copy_from_user(tmp, buffer, count)) {
+		int num = sscanf(tmp, "%hhx", &flags);
+
+		if (num == 1)
+			adapter->mlmepriv.ft_roam.ft_flags = flags;
+	}
+
+	return count;
+
+}
+
+int proc_get_ft_flags(struct seq_file *m, void *v)
+{
+	struct net_device *dev = m->private;
+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
+
+	RTW_PRINT_SEL(m, "0x%02x\n", adapter->mlmepriv.ft_roam.ft_flags);
+
+	return 0;
+}
+#endif
+
+int proc_get_qos_option(struct seq_file *m, void *v)
+{
+	struct net_device *dev = m->private;
+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
+	struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
+
+	RTW_PRINT_SEL(m, "qos_option=%d\n", pmlmepriv->qospriv.qos_option);
+
+	return 0;
+}
+
+int proc_get_ht_option(struct seq_file *m, void *v)
+{
+	struct net_device *dev = m->private;
+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
+	struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
+
+#ifdef CONFIG_80211N_HT
+	RTW_PRINT_SEL(m, "ht_option=%d\n", pmlmepriv->htpriv.ht_option);
+#endif /* CONFIG_80211N_HT */
+
+	return 0;
+}
+
+int proc_get_rf_info(struct seq_file *m, void *v)
+{
+	struct net_device *dev = m->private;
+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
+	struct mlme_ext_priv	*pmlmeext = &padapter->mlmeextpriv;
+
+	RTW_PRINT_SEL(m, "cur_ch=%d, cur_bw=%d, cur_ch_offet=%d\n",
+		pmlmeext->cur_channel, pmlmeext->cur_bwmode, pmlmeext->cur_ch_offset);
+
+	RTW_PRINT_SEL(m, "oper_ch=%d, oper_bw=%d, oper_ch_offet=%d\n",
+		rtw_get_oper_ch(padapter), rtw_get_oper_bw(padapter),  rtw_get_oper_choffset(padapter));
+
+	return 0;
+}
+
+int proc_get_scan_param(struct seq_file *m, void *v)
+{
+	struct net_device *dev = m->private;
+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
+	struct mlme_ext_priv *mlmeext = &adapter->mlmeextpriv;
+	struct ss_res *ss = &mlmeext->sitesurvey_res;
+
+#define SCAN_PARAM_TITLE_FMT "%10s"
+#define SCAN_PARAM_VALUE_FMT "%-10u"
+#define SCAN_PARAM_TITLE_ARG , "scan_ch_ms"
+#define SCAN_PARAM_VALUE_ARG , ss->scan_ch_ms
+#ifdef CONFIG_80211N_HT
+#define SCAN_PARAM_TITLE_FMT_HT " %15s %13s"
+#define SCAN_PARAM_VALUE_FMT_HT " %-15u %-13u"
+#define SCAN_PARAM_TITLE_ARG_HT , "rx_ampdu_accept", "rx_ampdu_size"
+#define SCAN_PARAM_VALUE_ARG_HT , ss->rx_ampdu_accept, ss->rx_ampdu_size
+#else
+#define SCAN_PARAM_TITLE_FMT_HT ""
+#define SCAN_PARAM_VALUE_FMT_HT ""
+#define SCAN_PARAM_TITLE_ARG_HT
+#define SCAN_PARAM_VALUE_ARG_HT
+#endif
+#ifdef CONFIG_SCAN_BACKOP
+#define SCAN_PARAM_TITLE_FMT_BACKOP " %9s %12s"
+#define SCAN_PARAM_VALUE_FMT_BACKOP " %-9u %-12u"
+#define SCAN_PARAM_TITLE_ARG_BACKOP , "backop_ms", "scan_cnt_max"
+#define SCAN_PARAM_VALUE_ARG_BACKOP , ss->backop_ms, ss->scan_cnt_max
+#else
+#define SCAN_PARAM_TITLE_FMT_BACKOP ""
+#define SCAN_PARAM_VALUE_FMT_BACKOP ""
+#define SCAN_PARAM_TITLE_ARG_BACKOP
+#define SCAN_PARAM_VALUE_ARG_BACKOP
+#endif
+
+	RTW_PRINT_SEL(m,
+		SCAN_PARAM_TITLE_FMT
+		SCAN_PARAM_TITLE_FMT_HT
+		SCAN_PARAM_TITLE_FMT_BACKOP
+		"\n"
+		SCAN_PARAM_TITLE_ARG
+		SCAN_PARAM_TITLE_ARG_HT
+		SCAN_PARAM_TITLE_ARG_BACKOP
+	);
+
+	RTW_PRINT_SEL(m,
+		SCAN_PARAM_VALUE_FMT
+		SCAN_PARAM_VALUE_FMT_HT
+		SCAN_PARAM_VALUE_FMT_BACKOP
+		"\n"
+		SCAN_PARAM_VALUE_ARG
+		SCAN_PARAM_VALUE_ARG_HT
+		SCAN_PARAM_VALUE_ARG_BACKOP
+	);
+
+	return 0;
+}
+
+ssize_t proc_set_scan_param(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
+{
+	struct net_device *dev = data;
+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
+	struct mlme_ext_priv *mlmeext = &adapter->mlmeextpriv;
+	struct ss_res *ss = &mlmeext->sitesurvey_res;
+
+	char tmp[32] = {0};
+
+	u16 scan_ch_ms;
+#define SCAN_PARAM_INPUT_FMT "%hu"
+#define SCAN_PARAM_INPUT_ARG , &scan_ch_ms
+#ifdef CONFIG_80211N_HT
+	u8 rx_ampdu_accept;
+	u8 rx_ampdu_size;
+#define SCAN_PARAM_INPUT_FMT_HT " %hhu %hhu"
+#define SCAN_PARAM_INPUT_ARG_HT , &rx_ampdu_accept, &rx_ampdu_size
+#else
+#define SCAN_PARAM_INPUT_FMT_HT ""
+#define SCAN_PARAM_INPUT_ARG_HT
+#endif
+#ifdef CONFIG_SCAN_BACKOP
+	u16 backop_ms;
+	u8 scan_cnt_max;
+#define SCAN_PARAM_INPUT_FMT_BACKOP " %hu %hhu"
+#define SCAN_PARAM_INPUT_ARG_BACKOP , &backop_ms, &scan_cnt_max
+#else
+#define SCAN_PARAM_INPUT_FMT_BACKOP ""
+#define SCAN_PARAM_INPUT_ARG_BACKOP
+#endif
+
+	if (count < 1)
+		return -EFAULT;
+
+	if (count > sizeof(tmp)) {
+		rtw_warn_on(1);
+		return -EFAULT;
+	}
+
+	if (buffer && !copy_from_user(tmp, buffer, count)) {
+
+		int num = sscanf(tmp,
+			SCAN_PARAM_INPUT_FMT
+			SCAN_PARAM_INPUT_FMT_HT
+			SCAN_PARAM_INPUT_FMT_BACKOP
+			SCAN_PARAM_INPUT_ARG
+			SCAN_PARAM_INPUT_ARG_HT
+			SCAN_PARAM_INPUT_ARG_BACKOP
+		);
+
+		if (num-- > 0)
+			ss->scan_ch_ms = scan_ch_ms;
+#ifdef CONFIG_80211N_HT
+		if (num-- > 0)
+			ss->rx_ampdu_accept = rx_ampdu_accept;
+		if (num-- > 0)
+			ss->rx_ampdu_size = rx_ampdu_size;
+#endif
+#ifdef CONFIG_SCAN_BACKOP
+		if (num-- > 0)
+			ss->backop_ms = backop_ms;
+		if (num-- > 0)
+			ss->scan_cnt_max = scan_cnt_max;
+#endif
+	}
+
+	return count;
+}
+
+int proc_get_scan_abort(struct seq_file *m, void *v)
+{
+	struct net_device *dev = m->private;
+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
+	u32 pass_ms;
+
+	pass_ms = rtw_scan_abort_timeout(adapter, 10000);
+
+	RTW_PRINT_SEL(m, "%u\n", pass_ms);
+
+	return 0;
+}
+
+#ifdef CONFIG_RTW_REPEATER_SON
+int proc_get_rson_data(struct seq_file *m, void *v)
+{
+	struct net_device *dev = m->private;
+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
+	char rson_data_str[256];
+
+	rtw_rson_get_property_str(padapter, rson_data_str);
+	RTW_PRINT_SEL(m, "%s\n", rson_data_str);
+	return 0;
+}
+
+ssize_t proc_set_rson_data(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
+{
+	struct net_device *dev = data;
+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
+	struct dvobj_priv *pdvobj = adapter_to_dvobj(padapter);
+	char tmp[64] = {0};
+	int num;
+	u8 field[10], value[64];
+
+	if (count < 1)
+		return -EFAULT;
+
+	if (count > sizeof(tmp)) {
+		rtw_warn_on(1);
+		return -EFAULT;
+	}
+
+	if (buffer && !copy_from_user(tmp, buffer, count)) {
+		num = sscanf(tmp, "%s %s", field, value);
+		if (num != 2) {
+			RTW_INFO("Invalid format : echo <field> <value> > son_data\n");
+			return count;
+		}
+		RTW_INFO("field=%s  value=%s\n", field, value);
+		num = rtw_rson_set_property(padapter, field, value);
+		if (num != 1) {
+			RTW_INFO("Invalid field(%s) or value(%s)\n", field, value);
+			return count;
+		}
+	}
+	return count;
+}
+#endif /*CONFIG_RTW_REPEATER_SON*/
+
+int proc_get_survey_info(struct seq_file *m, void *v)
+{
+	_irqL irqL;
+	struct net_device *dev = m->private;
+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
+	struct mlme_priv	*pmlmepriv = &(padapter->mlmepriv);
+	_queue	*queue	= &(pmlmepriv->scanned_queue);
+	struct wlan_network	*pnetwork = NULL;
+	_list	*plist, *phead;
+	s32 notify_signal;
+	s16 notify_noise = 0;
+	u16  index = 0, ie_cap = 0;
+	unsigned char *ie_wpa = NULL, *ie_wpa2 = NULL, *ie_wps = NULL;
+	unsigned char *ie_p2p = NULL, *ssid = NULL;
+	char flag_str[64];
+	int ielen = 0;
+	u32 wpsielen = 0;
+#ifdef CONFIG_RTW_MESH
+	const char *ssid_title_str = "ssid/mesh_id";
+#else
+	const char *ssid_title_str = "ssid";
+#endif
+
+	_enter_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);
+	phead = get_list_head(queue);
+	if (!phead)
+		goto _exit;
+	plist = get_next(phead);
+	if (!plist)
+		goto _exit;
+
+#ifdef CONFIG_RTW_REPEATER_SON
+	rtw_rson_show_survey_info(m, plist, phead);
+#else
+
+	RTW_PRINT_SEL(m, "%5s  %-17s  %3s  %-3s  %-4s  %-4s  %5s  %32s  %32s\n", "index", "bssid", "ch", "RSSI", "SdBm", "Noise", "age", "flag", ssid_title_str);
+	while (1) {
+		if (rtw_end_of_queue_search(phead, plist) == _TRUE)
+			break;
+
+		pnetwork = LIST_CONTAINOR(plist, struct wlan_network, list);
+		if (!pnetwork)
+			break;
+
+		if (check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE &&
+		    is_same_network(&pmlmepriv->cur_network.network, &pnetwork->network, 0)) {
+			notify_signal = translate_percentage_to_dbm(padapter->recvpriv.signal_strength);/* dbm */
+		} else {
+			notify_signal = translate_percentage_to_dbm(pnetwork->network.PhyInfo.SignalStrength);/* dbm */
+		}
+
+#ifdef CONFIG_BACKGROUND_NOISE_MONITOR
+		if (IS_NM_ENABLE(padapter))
+			notify_noise = rtw_noise_query_by_chan_num(padapter, pnetwork->network.Configuration.DSConfig);
+#endif
+
+		ie_wpa = rtw_get_wpa_ie(&pnetwork->network.IEs[12], &ielen, pnetwork->network.IELength - 12);
+		ie_wpa2 = rtw_get_wpa2_ie(&pnetwork->network.IEs[12], &ielen, pnetwork->network.IELength - 12);
+		ie_cap = rtw_get_capability(&pnetwork->network);
+		ie_wps = rtw_get_wps_ie(&pnetwork->network.IEs[12], pnetwork->network.IELength - 12, NULL, &wpsielen);
+		ie_p2p = rtw_get_p2p_ie(&pnetwork->network.IEs[12], pnetwork->network.IELength - 12, NULL, &ielen);
+		ssid = pnetwork->network.Ssid.Ssid;
+		sprintf(flag_str, "%s%s%s%s%s%s%s",
+			(ie_wpa) ? "[WPA]" : "",
+			(ie_wpa2) ? "[WPA2]" : "",
+			(!ie_wpa && !ie_wpa && ie_cap & BIT(4)) ? "[WEP]" : "",
+			(ie_wps) ? "[WPS]" : "",
+			(pnetwork->network.InfrastructureMode == Ndis802_11IBSS) ? "[IBSS]" :
+				(pnetwork->network.InfrastructureMode == Ndis802_11_mesh) ? "[MESH]" : "",
+			(ie_cap & BIT(0)) ? "[ESS]" : "",
+			(ie_p2p) ? "[P2P]" : "");
+		RTW_PRINT_SEL(m, "%5d  "MAC_FMT"  %3d  %3d  %4d  %4d    %5d  %32s  %32s\n",
+			++index,
+			MAC_ARG(pnetwork->network.MacAddress),
+			pnetwork->network.Configuration.DSConfig,
+			(int)pnetwork->network.Rssi,
+			notify_signal,
+			notify_noise,
+			rtw_get_passing_time_ms(pnetwork->last_scanned),
+			flag_str,
+			pnetwork->network.InfrastructureMode == Ndis802_11_mesh ? pnetwork->network.mesh_id.Ssid : pnetwork->network.Ssid.Ssid
+		);
+		plist = get_next(plist);
+	}
+#endif
+_exit:
+	_exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);
+
+	return 0;
+}
+
+ssize_t proc_set_survey_info(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
+{
+	struct net_device *dev = data;
+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
+	u8 _status = _FALSE;
+	u8 ssc_chk;
+	if (count < 1)
+		return -EFAULT;
+
+#if 1
+	ssc_chk = rtw_sitesurvey_condition_check(padapter, _FALSE);
+	if (ssc_chk != SS_ALLOW)
+		goto exit;
+
+	rtw_ps_deny(padapter, PS_DENY_SCAN);
+	if (_FAIL == rtw_pwr_wakeup(padapter))
+		goto cancel_ps_deny;
+	if (!rtw_is_adapter_up(padapter)) {
+		RTW_INFO("scan abort!! adapter cannot use\n");
+		goto cancel_ps_deny;
+	}
+#else
+#ifdef CONFIG_MP_INCLUDED
+	if (rtw_mp_mode_check(padapter)) {
+		RTW_INFO("MP mode block Scan request\n");
+		goto exit;
+	}
+#endif
+	if (rtw_is_scan_deny(padapter)) {
+		RTW_INFO(FUNC_ADPT_FMT  ": scan deny\n", FUNC_ADPT_ARG(padapter));
+		goto exit;
+	}
+
+	rtw_ps_deny(padapter, PS_DENY_SCAN);
+	if (_FAIL == rtw_pwr_wakeup(padapter))
+		goto cancel_ps_deny;
+
+	if (!rtw_is_adapter_up(padapter)) {
+		RTW_INFO("scan abort!! adapter cannot use\n");
+		goto cancel_ps_deny;
+	}
+
+	if (rtw_mi_busy_traffic_check(padapter, _FALSE)) {
+		RTW_INFO("scan abort!! BusyTraffic == _TRUE\n");
+		goto cancel_ps_deny;
+	}
+
+	if (check_fwstate(pmlmepriv, WIFI_AP_STATE) && check_fwstate(pmlmepriv, WIFI_UNDER_WPS)) {
+		RTW_INFO("scan abort!! AP mode process WPS\n");
+		goto cancel_ps_deny;
+	}
+	if (check_fwstate(pmlmepriv, _FW_UNDER_SURVEY | _FW_UNDER_LINKING) == _TRUE) {
+		RTW_INFO("scan abort!! fwstate=0x%x\n", pmlmepriv->fw_state);
+		goto cancel_ps_deny;
+	}
+
+#ifdef CONFIG_CONCURRENT_MODE
+	if (rtw_mi_buddy_check_fwstate(padapter,
+		       _FW_UNDER_SURVEY | _FW_UNDER_LINKING | WIFI_UNDER_WPS)) {
+		RTW_INFO("scan abort!! buddy_fwstate check failed\n");
+		goto cancel_ps_deny;
+	}
+#endif
+#endif
+	_status = rtw_set_802_11_bssid_list_scan(padapter, NULL);
+
+cancel_ps_deny:
+	rtw_ps_deny_cancel(padapter, PS_DENY_SCAN);
+exit:
+	return count;
+}
+#ifdef ROKU_PRIVATE
+int proc_get_infra_ap(struct seq_file *m, void *v)
+{
+	struct net_device *dev = m->private;
+	struct sta_info *psta;
+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
+	struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
+	struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
+	struct ht_priv_infra_ap *phtpriv = &pmlmepriv->htpriv_infra_ap;
+#ifdef CONFIG_80211AC_VHT
+	struct vht_priv_infra_ap *pvhtpriv = &pmlmepriv->vhtpriv_infra_ap;
+#endif
+	struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
+	struct wlan_network *cur_network = &(pmlmepriv->cur_network);
+	struct sta_priv *pstapriv = &padapter->stapriv;
+
+	if (check_fwstate(pmlmepriv, WIFI_STATION_STATE)) {
+		psta = rtw_get_stainfo(pstapriv, cur_network->network.MacAddress);
+		if (psta) {
+			unsigned int i, j;
+			unsigned int Rx_ss = 0, Tx_ss = 0;
+			struct recv_reorder_ctrl *preorder_ctrl;
+
+			RTW_PRINT_SEL(m, "SSID=%s\n", pmlmeinfo->network.Ssid.Ssid);
+			RTW_PRINT_SEL(m, "sta's macaddr:" MAC_FMT "\n", MAC_ARG(psta->cmn.mac_addr));
+			RTW_PRINT_SEL(m, "Supported rate=");
+			for (i = 0; i < NDIS_802_11_LENGTH_RATES_EX; i++) {
+				if (pmlmeinfo->SupportedRates_infra_ap[i] == 0)
+					break;
+				RTW_PRINT_SEL(m, " 0x%x", pmlmeinfo->SupportedRates_infra_ap[i]);
+			}
+			RTW_PRINT_SEL(m, "\n");
+#ifdef CONFIG_80211N_HT
+			if (pmlmeinfo->ht_vht_received & BIT(0)) {
+				RTW_PRINT_SEL(m, "Supported MCS set=");
+				for (i = 0; i < 16 ; i++)
+					RTW_PRINT_SEL(m, " 0x%02x",  phtpriv->MCS_set_infra_ap[i]);
+				RTW_PRINT_SEL(m, "\n");
+				RTW_PRINT_SEL(m, "highest supported data rate=0x%x\n", phtpriv->rx_highest_data_rate_infra_ap);
+				RTW_PRINT_SEL(m, "HT_supported_channel_width_set=0x%x\n", phtpriv->channel_width_infra_ap);
+				RTW_PRINT_SEL(m, "sgi_20m=%d, sgi_40m=%d\n", phtpriv->sgi_20m_infra_ap, phtpriv->sgi_40m_infra_ap);
+				RTW_PRINT_SEL(m, "ldpc_cap=0x%x, stbc_cap=0x%x\n", phtpriv->ldpc_cap_infra_ap, phtpriv->stbc_cap_infra_ap);
+				RTW_PRINT_SEL(m, "HT_number_of_stream=%d\n", phtpriv->Rx_ss_infra_ap);
+			}
+#endif
+
+#ifdef CONFIG_80211AC_VHT
+			if (pmlmeinfo->ht_vht_received & BIT(1)) {
+				RTW_PRINT_SEL(m, "VHT_supported_channel_width_set=0x%x\n", pvhtpriv->channel_width_infra_ap);
+				RTW_PRINT_SEL(m, "vht_ldpc_cap=0x%x, vht_stbc_cap=0x%x, vht_beamform_cap=0x%x\n", pvhtpriv->ldpc_cap_infra_ap, pvhtpriv->stbc_cap_infra_ap, pvhtpriv->beamform_cap_infra_ap);
+				RTW_PRINT_SEL(m, "Rx_vht_mcs_map=0x%x, Tx_vht_mcs_map=0x%x\n", *(u16 *)pvhtpriv->vht_mcs_map_infra_ap, *(u16 *)pvhtpriv->vht_mcs_map_tx_infra_ap);
+				RTW_PRINT_SEL(m, "VHT_number_of_stream=%d\n", pvhtpriv->number_of_streams_infra_ap);
+			}
+#endif
+		} else
+			RTW_PRINT_SEL(m, "can't get sta's macaddr, cur_network's macaddr:" MAC_FMT "\n", MAC_ARG(cur_network->network.MacAddress));
+	} else
+		RTW_PRINT_SEL(m, "this only applies to STA mode\n");
+	return 0;
+}
+
+#endif /* ROKU_PRIVATE */
+
+int proc_get_ap_info(struct seq_file *m, void *v)
+{
+	struct net_device *dev = m->private;
+	struct sta_info *psta;
+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
+	struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
+	struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
+	struct wlan_network *cur_network = &(pmlmepriv->cur_network);
+	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
+	struct sta_priv *pstapriv = &padapter->stapriv;
+
+	/* ap vendor */
+	char vendor[VENDOR_NAME_LEN] = {0};
+	get_assoc_AP_Vendor(vendor,pmlmeinfo->assoc_AP_vendor);
+	RTW_PRINT_SEL(m,"AP Vendor %s\n", vendor);
+
+	psta = rtw_get_stainfo(pstapriv, cur_network->network.MacAddress);
+	if (psta) {
+		RTW_PRINT_SEL(m, "SSID=%s\n", cur_network->network.Ssid.Ssid);
+		RTW_PRINT_SEL(m, "sta's macaddr:" MAC_FMT "\n", MAC_ARG(psta->cmn.mac_addr));
+		RTW_PRINT_SEL(m, "cur_channel=%d, cur_bwmode=%d, cur_ch_offset=%d\n", pmlmeext->cur_channel, pmlmeext->cur_bwmode, pmlmeext->cur_ch_offset);
+		RTW_PRINT_SEL(m, "wireless_mode=0x%x, rtsen=%d, cts2slef=%d\n", psta->wireless_mode, psta->rtsen, psta->cts2self);
+		RTW_PRINT_SEL(m, "state=0x%x, aid=%d, macid=%d, raid=%d\n",
+			psta->state, psta->cmn.aid, psta->cmn.mac_id, psta->cmn.ra_info.rate_id);
+#ifdef CONFIG_80211N_HT
+		RTW_PRINT_SEL(m, "qos_en=%d, ht_en=%d, init_rate=%d\n", psta->qos_option, psta->htpriv.ht_option, psta->init_rate);
+		RTW_PRINT_SEL(m, "bwmode=%d, ch_offset=%d, sgi_20m=%d,sgi_40m=%d\n"
+			, psta->cmn.bw_mode, psta->htpriv.ch_offset, psta->htpriv.sgi_20m, psta->htpriv.sgi_40m);
+		RTW_PRINT_SEL(m, "ampdu_enable = %d\n", psta->htpriv.ampdu_enable);
+		RTW_PRINT_SEL(m, "agg_enable_bitmap=%x, candidate_tid_bitmap=%x\n", psta->htpriv.agg_enable_bitmap, psta->htpriv.candidate_tid_bitmap);
+		RTW_PRINT_SEL(m, "ldpc_cap=0x%x, stbc_cap=0x%x, beamform_cap=0x%x\n", psta->htpriv.ldpc_cap, psta->htpriv.stbc_cap, psta->htpriv.beamform_cap);
+#endif /* CONFIG_80211N_HT */
+#ifdef CONFIG_80211AC_VHT
+		RTW_PRINT_SEL(m, "vht_en=%d, vht_sgi_80m=%d\n", psta->vhtpriv.vht_option, psta->vhtpriv.sgi_80m);
+		RTW_PRINT_SEL(m, "vht_ldpc_cap=0x%x, vht_stbc_cap=0x%x, vht_beamform_cap=0x%x\n", psta->vhtpriv.ldpc_cap, psta->vhtpriv.stbc_cap, psta->vhtpriv.beamform_cap);
+		RTW_PRINT_SEL(m, "vht_mcs_map=0x%x, vht_highest_rate=0x%x, vht_ampdu_len=%d\n", *(u16 *)psta->vhtpriv.vht_mcs_map, psta->vhtpriv.vht_highest_rate, psta->vhtpriv.ampdu_len);
+#endif
+		sta_rx_reorder_ctl_dump(m, psta);
+	} else
+		RTW_PRINT_SEL(m, "can't get sta's macaddr, cur_network's macaddr:" MAC_FMT "\n", MAC_ARG(cur_network->network.MacAddress));
+
+	return 0;
+}
+
+ssize_t proc_reset_trx_info(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
+{
+	struct net_device *dev = data;
+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
+	struct recv_priv  *precvpriv = &padapter->recvpriv;
+	char cmd[32] = {0};
+	u8 cnt = 0;
+
+	if (count > sizeof(cmd)) {
+		rtw_warn_on(1);
+		return -EFAULT;
+	}
+
+	if (buffer && !copy_from_user(cmd, buffer, count)) {
+		int num = sscanf(cmd, "%hhx", &cnt);
+
+		if (num == 1 && cnt == 0) {
+			precvpriv->dbg_rx_ampdu_drop_count = 0;
+			precvpriv->dbg_rx_ampdu_forced_indicate_count = 0;
+			precvpriv->dbg_rx_ampdu_loss_count = 0;
+			precvpriv->dbg_rx_dup_mgt_frame_drop_count = 0;
+			precvpriv->dbg_rx_ampdu_window_shift_cnt = 0;
+			precvpriv->dbg_rx_conflic_mac_addr_cnt = 0;
+			precvpriv->dbg_rx_drop_count = 0;
+		}
+	}
+
+	return count;
+}
+
+int proc_get_trx_info(struct seq_file *m, void *v)
+{
+	struct net_device *dev = m->private;
+	int i;
+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
+	struct xmit_priv *pxmitpriv = &padapter->xmitpriv;
+	struct recv_priv  *precvpriv = &padapter->recvpriv;
+	struct hw_xmit *phwxmit;
+	u16 vo_params[4], vi_params[4], be_params[4], bk_params[4];
+
+	padapter->hal_func.read_wmmedca_reg(padapter, vo_params, vi_params, be_params, bk_params);
+
+	RTW_PRINT_SEL(m, "wmm_edca_vo, aifs = %u us, cw_min = %u, cw_max = %u, txop_limit = %u us\n", vo_params[0], vo_params[1], vo_params[2], vo_params[3]);
+	RTW_PRINT_SEL(m, "wmm_edca_vi, aifs = %u us, cw_min = %u, cw_max = %u, txop_limit = %u us\n", vi_params[0], vi_params[1], vi_params[2], vi_params[3]);
+	RTW_PRINT_SEL(m, "wmm_edca_be, aifs = %u us, cw_min = %u, cw_max = %u, txop_limit = %u us\n", be_params[0], be_params[1], be_params[2], be_params[3]);
+	RTW_PRINT_SEL(m, "wmm_edca_bk, aifs = %u us, cw_min = %u, cw_max = %u, txop_limit = %u us\n", bk_params[0], bk_params[1], bk_params[2], bk_params[3]);
+
+	dump_os_queue(m, padapter);
+
+	RTW_PRINT_SEL(m, "free_xmitbuf_cnt=%d, free_xmitframe_cnt=%d\n"
+		, pxmitpriv->free_xmitbuf_cnt, pxmitpriv->free_xmitframe_cnt);
+	RTW_PRINT_SEL(m, "free_ext_xmitbuf_cnt=%d, free_xframe_ext_cnt=%d\n"
+		, pxmitpriv->free_xmit_extbuf_cnt, pxmitpriv->free_xframe_ext_cnt);
+	RTW_PRINT_SEL(m, "free_recvframe_cnt=%d\n"
+		      , precvpriv->free_recvframe_cnt);
+
+	for (i = 0; i < 4; i++) {
+		phwxmit = pxmitpriv->hwxmits + i;
+		RTW_PRINT_SEL(m, "%d, hwq.accnt=%d\n", i, phwxmit->accnt);
+	}
+
+	rtw_hal_get_hwreg(padapter, HW_VAR_DUMP_MAC_TXFIFO, (u8 *)m);
+
+#ifdef CONFIG_USB_HCI
+	RTW_PRINT_SEL(m, "rx_urb_pending_cn=%d\n", ATOMIC_READ(&(precvpriv->rx_pending_cnt)));
+#endif
+
+	dump_rx_bh_tk(m, &GET_PRIMARY_ADAPTER(padapter)->recvpriv);
+
+	/* Folowing are RX info */
+	RTW_PRINT_SEL(m, "RX: Count of Packets dropped by Driver: %llu\n", (unsigned long long)precvpriv->dbg_rx_drop_count);
+	/* Counts of packets whose seq_num is less than preorder_ctrl->indicate_seq, Ex delay, retransmission, redundant packets and so on */
+	RTW_PRINT_SEL(m, "Rx: Counts of Packets Whose Seq_Num Less Than Reorder Control Seq_Num: %llu\n", (unsigned long long)precvpriv->dbg_rx_ampdu_drop_count);
+	/* How many times the Rx Reorder Timer is triggered. */
+	RTW_PRINT_SEL(m, "Rx: Reorder Time-out Trigger Counts: %llu\n", (unsigned long long)precvpriv->dbg_rx_ampdu_forced_indicate_count);
+	/* Total counts of packets loss */
+	RTW_PRINT_SEL(m, "Rx: Packet Loss Counts: %llu\n", (unsigned long long)precvpriv->dbg_rx_ampdu_loss_count);
+	RTW_PRINT_SEL(m, "Rx: Duplicate Management Frame Drop Count: %llu\n", (unsigned long long)precvpriv->dbg_rx_dup_mgt_frame_drop_count);
+	RTW_PRINT_SEL(m, "Rx: AMPDU BA window shift Count: %llu\n", (unsigned long long)precvpriv->dbg_rx_ampdu_window_shift_cnt);
+	/*The same mac addr counts*/
+	RTW_PRINT_SEL(m, "Rx: Conflict MAC Address Frames Count: %llu\n", (unsigned long long)precvpriv->dbg_rx_conflic_mac_addr_cnt);
+	return 0;
+}
+
+int proc_get_rate_ctl(struct seq_file *m, void *v)
+{
+	struct net_device *dev = m->private;
+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
+	u8 data_rate = 0, sgi = 0, data_fb = 0;
+
+	if (adapter->fix_rate != 0xff) {
+		data_rate = adapter->fix_rate & 0x7F;
+		sgi = adapter->fix_rate >> 7;
+		data_fb = adapter->data_fb ? 1 : 0;
+		RTW_PRINT_SEL(m, "FIXED %s%s%s\n"
+			, HDATA_RATE(data_rate)
+			, data_rate > DESC_RATE54M ? (sgi ? " SGI" : " LGI") : ""
+			, data_fb ? " FB" : ""
+		);
+		RTW_PRINT_SEL(m, "0x%02x %u\n", adapter->fix_rate, adapter->data_fb);
+	} else
+		RTW_PRINT_SEL(m, "RA\n");
+
+	return 0;
+}
+
+#ifdef 	CONFIG_PHDYM_FW_FIXRATE
+void phydm_fw_fix_rate(void *dm_void, u8 en, u8	macid, u8 bw, u8 rate);
+#endif
+ssize_t proc_set_rate_ctl(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
+{
+	struct net_device *dev = data;
+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
+	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
+	char tmp[32];
+	u8 fix_rate = 0xFF;
+#ifdef 	CONFIG_PHDYM_FW_FIXRATE
+	u8 bw = 0;
+#else
+	u8 data_fb = 0;
+#endif
+
+	if (count < 1)
+		return -EFAULT;
+
+	if (count > sizeof(tmp)) {
+		rtw_warn_on(1);
+		return -EFAULT;
+	}
+
+	if (buffer && !copy_from_user(tmp, buffer, count)) {
+#ifdef 	CONFIG_PHDYM_FW_FIXRATE
+		struct dm_struct *dm = adapter_to_phydm(adapter);
+		u8 en = 1, macid = 255;
+		_irqL	irqL;
+		_list	*plist, *phead;
+		struct sta_info *psta = NULL;
+		struct sta_priv	*pstapriv = &(adapter->stapriv);
+		u8 bc_addr[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
+		u8 null_addr[ETH_ALEN] = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00};
+		uint mac_id[NUM_STA];
+		int i, macid_rec_idx = 0;
+		int num = sscanf(tmp, "%hhx %hhu %hhu", &fix_rate, &bw, &macid);
+
+		if (num < 1) {
+			RTW_INFO("Invalid input!! \"ex: echo <rate> <bw> <macid> > /proc/.../rate_ctl\"\n");
+			return count;
+		}
+
+		if ((fix_rate == 0) || (fix_rate == 0xFF))
+			en = 0;
+			
+		if (macid != 255) {
+			RTW_INFO("Call phydm_fw_fix_rate()--en[%d] mac_id[%d] bw[%d] fix_rate[%d]\n", en, macid, bw, fix_rate);
+			phydm_fw_fix_rate(dm, en, macid, bw, fix_rate);
+			return count;
+		}
+
+		/*	no specific macid, apply to all macids except bc/mc macid */
+		_enter_critical_bh(&pstapriv->sta_hash_lock, &irqL);
+		for (i = 0; i < NUM_STA; i++) {
+			phead = &(pstapriv->sta_hash[i]);
+			plist = get_next(phead);
+			while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) {
+				psta = LIST_CONTAINOR(plist, struct sta_info, hash_list);
+				plist = get_next(plist);
+				if ((_rtw_memcmp(psta->cmn.mac_addr, bc_addr, ETH_ALEN) !=  _TRUE)
+					&& (_rtw_memcmp(psta->cmn.mac_addr, null_addr, ETH_ALEN) != _TRUE)
+					&& (_rtw_memcmp(psta->cmn.mac_addr, adapter_mac_addr(adapter), ETH_ALEN) != _TRUE)) {
+						mac_id[macid_rec_idx] = psta->cmn.mac_id;
+						macid_rec_idx++;
+				}
+			}
+		}
+		_exit_critical_bh(&pstapriv->sta_hash_lock, &irqL);
+
+		for (i = 0; i < macid_rec_idx; i++) {
+			RTW_INFO("Call phydm_fw_fix_rate()--en[%d] mac_id[%d] bw[%d] fix_rate[%d]\n", en, mac_id[i], bw, fix_rate);
+			phydm_fw_fix_rate(dm, en, mac_id[i], bw, fix_rate);
+		}
+#else
+		int num = sscanf(tmp, "%hhx %hhu", &fix_rate, &data_fb);
+
+		if (num >= 1) {
+			u8 fix_rate_ori = adapter->fix_rate;
+
+			adapter->fix_rate = fix_rate;
+			if (fix_rate == 0xFF)
+				hal_data->ForcedDataRate = 0;
+			else
+				hal_data->ForcedDataRate = hw_rate_to_m_rate(fix_rate & 0x7F);
+
+			if (adapter->fix_bw != 0xFF && fix_rate_ori != fix_rate)
+				rtw_update_tx_rate_bmp(adapter_to_dvobj(adapter));
+		}
+		if (num >= 2)
+			adapter->data_fb = data_fb ? 1 : 0;
+#endif
+	}
+
+	return count;
+}
+
+#ifdef CONFIG_AP_MODE
+int proc_get_bmc_tx_rate(struct seq_file *m, void *v)
+{
+	struct net_device *dev = m->private;
+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
+
+	if (!MLME_IS_AP(adapter) && !MLME_IS_MESH(adapter)) {
+		RTW_PRINT_SEL(m, "[ERROR] Not in SoftAP/Mesh mode !!\n");
+		return 0;
+	}
+
+	RTW_PRINT_SEL(m, " BMC Tx rate - %s\n", MGN_RATE_STR(adapter->bmc_tx_rate));
+	return 0;
+}
+
+ssize_t proc_set_bmc_tx_rate(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
+{
+	struct net_device *dev = data;
+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
+	char tmp[32];
+	u8 bmc_tx_rate;
+
+	if (count < 1)
+		return -EFAULT;
+
+	if (count > sizeof(tmp)) {
+		rtw_warn_on(1);
+		return -EFAULT;
+	}
+
+	if (buffer && !copy_from_user(tmp, buffer, count)) {
+
+		int num = sscanf(tmp, "%hhx", &bmc_tx_rate);
+
+		if (num >= 1)
+			/*adapter->bmc_tx_rate = hw_rate_to_m_rate(bmc_tx_rate);*/
+			adapter->bmc_tx_rate = bmc_tx_rate;
+	}
+
+	return count;
+}
+#endif /*CONFIG_AP_MODE*/
+
+
+int proc_get_tx_power_offset(struct seq_file *m, void *v)
+{
+	struct net_device *dev = m->private;
+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
+
+	RTW_PRINT_SEL(m, "Tx power offset - %u\n", adapter->power_offset);
+	return 0;
+}
+
+ssize_t proc_set_tx_power_offset(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
+{
+	struct net_device *dev = data;
+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
+	char tmp[32];
+	u8 power_offset = 0;
+
+	if (count < 1)
+		return -EFAULT;
+
+	if (count > sizeof(tmp)) {
+		rtw_warn_on(1);
+		return -EFAULT;
+	}
+
+	if (buffer && !copy_from_user(tmp, buffer, count)) {
+
+		int num = sscanf(tmp, "%hhu", &power_offset);
+
+		if (num >= 1) {
+			if (power_offset > 5)
+				power_offset = 0;
+
+			adapter->power_offset = power_offset;
+		}
+	}
+
+	return count;
+}
+
+int proc_get_bw_ctl(struct seq_file *m, void *v)
+{
+	struct net_device *dev = m->private;
+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
+	u8 data_bw = 0;
+
+	if (adapter->fix_bw != 0xff) {
+		data_bw = adapter->fix_bw;
+		RTW_PRINT_SEL(m, "FIXED %s\n", ch_width_str(data_bw));
+	} else
+		RTW_PRINT_SEL(m, "Auto\n");
+
+	return 0;
+}
+
+ssize_t proc_set_bw_ctl(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
+{
+	struct net_device *dev = data;
+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
+	char tmp[32];
+	u8 fix_bw;
+
+	if (count < 1)
+		return -EFAULT;
+
+	if (count > sizeof(tmp)) {
+		rtw_warn_on(1);
+		return -EFAULT;
+	}
+
+	if (buffer && !copy_from_user(tmp, buffer, count)) {
+		int num = sscanf(tmp, "%hhu", &fix_bw);
+
+		if (num >= 1) {
+			u8 fix_bw_ori = adapter->fix_bw;
+
+			adapter->fix_bw = fix_bw;
+
+			if (adapter->fix_rate != 0xFF && fix_bw_ori != fix_bw)
+				rtw_update_tx_rate_bmp(adapter_to_dvobj(adapter));
+		}
+	}
+
+	return count;
+}
+
+#ifdef DBG_RX_COUNTER_DUMP
+int proc_get_rx_cnt_dump(struct seq_file *m, void *v)
+{
+	struct net_device *dev = m->private;
+	int i;
+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
+
+	RTW_PRINT_SEL(m, "BIT0- Dump RX counters of DRV\n");
+	RTW_PRINT_SEL(m, "BIT1- Dump RX counters of MAC\n");
+	RTW_PRINT_SEL(m, "BIT2- Dump RX counters of PHY\n");
+	RTW_PRINT_SEL(m, "BIT3- Dump TRX data frame of DRV\n");
+	RTW_PRINT_SEL(m, "dump_rx_cnt_mode = 0x%02x\n", adapter->dump_rx_cnt_mode);
+
+	return 0;
+}
+ssize_t proc_set_rx_cnt_dump(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
+{
+	struct net_device *dev = data;
+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
+	char tmp[32];
+	u8 dump_rx_cnt_mode;
+
+	if (count < 1)
+		return -EFAULT;
+
+	if (count > sizeof(tmp)) {
+		rtw_warn_on(1);
+		return -EFAULT;
+	}
+
+	if (buffer && !copy_from_user(tmp, buffer, count)) {
+
+		int num = sscanf(tmp, "%hhx", &dump_rx_cnt_mode);
+
+		if (num == 1) {
+			rtw_dump_phy_rxcnts_preprocess(adapter, dump_rx_cnt_mode);
+			adapter->dump_rx_cnt_mode = dump_rx_cnt_mode;
+		}
+	}
+
+	return count;
+}
+#endif
+
+static u8 fwdl_test_chksum_fail = 0;
+static u8 fwdl_test_wintint_rdy_fail = 0;
+
+bool rtw_fwdl_test_trigger_chksum_fail(void)
+{
+	if (fwdl_test_chksum_fail) {
+		RTW_PRINT("fwdl test case: trigger chksum_fail\n");
+		fwdl_test_chksum_fail--;
+		return _TRUE;
+	}
+	return _FALSE;
+}
+
+bool rtw_fwdl_test_trigger_wintint_rdy_fail(void)
+{
+	if (fwdl_test_wintint_rdy_fail) {
+		RTW_PRINT("fwdl test case: trigger wintint_rdy_fail\n");
+		fwdl_test_wintint_rdy_fail--;
+		return _TRUE;
+	}
+	return _FALSE;
+}
+
+ssize_t proc_set_fwdl_test_case(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
+{
+	char tmp[32];
+
+	if (count < 1)
+		return -EFAULT;
+
+	if (count > sizeof(tmp)) {
+		rtw_warn_on(1);
+		return -EFAULT;
+	}
+
+	if (buffer && !copy_from_user(tmp, buffer, count))
+		sscanf(tmp, "%hhu %hhu", &fwdl_test_chksum_fail, &fwdl_test_wintint_rdy_fail);
+
+	return count;
+}
+
+static u8 del_rx_ampdu_test_no_tx_fail = 0;
+
+bool rtw_del_rx_ampdu_test_trigger_no_tx_fail(void)
+{
+	if (del_rx_ampdu_test_no_tx_fail) {
+		RTW_PRINT("del_rx_ampdu test case: trigger no_tx_fail\n");
+		del_rx_ampdu_test_no_tx_fail--;
+		return _TRUE;
+	}
+	return _FALSE;
+}
+
+ssize_t proc_set_del_rx_ampdu_test_case(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
+{
+	char tmp[32];
+
+	if (count < 1)
+		return -EFAULT;
+
+	if (count > sizeof(tmp)) {
+		rtw_warn_on(1);
+		return -EFAULT;
+	}
+
+	if (buffer && !copy_from_user(tmp, buffer, count))
+		sscanf(tmp, "%hhu", &del_rx_ampdu_test_no_tx_fail);
+
+	return count;
+}
+
+static u32 g_wait_hiq_empty_ms = 0;
+
+u32 rtw_get_wait_hiq_empty_ms(void)
+{
+	return g_wait_hiq_empty_ms;
+}
+
+ssize_t proc_set_wait_hiq_empty(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
+{
+	char tmp[32];
+
+	if (count < 1)
+		return -EFAULT;
+
+	if (count > sizeof(tmp)) {
+		rtw_warn_on(1);
+		return -EFAULT;
+	}
+
+	if (buffer && !copy_from_user(tmp, buffer, count))
+		sscanf(tmp, "%u", &g_wait_hiq_empty_ms);
+
+	return count;
+}
+
+static systime sta_linking_test_start_time = 0;
+static u32 sta_linking_test_wait_ms = 0;
+static u8 sta_linking_test_force_fail = 0;
+
+void rtw_sta_linking_test_set_start(void)
+{
+	sta_linking_test_start_time = rtw_get_current_time();
+}
+
+bool rtw_sta_linking_test_wait_done(void)
+{
+	return rtw_get_passing_time_ms(sta_linking_test_start_time) >= sta_linking_test_wait_ms;
+}
+
+bool rtw_sta_linking_test_force_fail(void)
+{
+	return sta_linking_test_force_fail;
+}
+
+ssize_t proc_set_sta_linking_test(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
+{
+	char tmp[32];
+
+	if (count < 1)
+		return -EFAULT;
+
+	if (count > sizeof(tmp)) {
+		rtw_warn_on(1);
+		return -EFAULT;
+	}
+
+	if (buffer && !copy_from_user(tmp, buffer, count)) {
+		u32 wait_ms = 0;
+		u8 force_fail = 0;
+		int num = sscanf(tmp, "%u %hhu", &wait_ms, &force_fail);
+
+		if (num >= 1)
+			sta_linking_test_wait_ms = wait_ms;
+		if (num >= 2)
+			sta_linking_test_force_fail = force_fail;
+	}
+
+	return count;
+}
+
+#ifdef CONFIG_AP_MODE
+static u16 ap_linking_test_force_auth_fail = 0;
+static u16 ap_linking_test_force_asoc_fail = 0;
+
+u16 rtw_ap_linking_test_force_auth_fail(void)
+{
+	return ap_linking_test_force_auth_fail;
+}
+
+u16 rtw_ap_linking_test_force_asoc_fail(void)
+{
+	return ap_linking_test_force_asoc_fail;
+}
+
+ssize_t proc_set_ap_linking_test(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
+{
+	char tmp[32];
+
+	if (count < 1)
+		return -EFAULT;
+
+	if (count > sizeof(tmp)) {
+		rtw_warn_on(1);
+		return -EFAULT;
+	}
+
+	if (buffer && !copy_from_user(tmp, buffer, count)) {
+		u16 force_auth_fail = 0;
+		u16 force_asoc_fail = 0;
+		int num = sscanf(tmp, "%hu %hu", &force_auth_fail, &force_asoc_fail);
+
+		if (num >= 1)
+			ap_linking_test_force_auth_fail = force_auth_fail;
+		if (num >= 2)
+			ap_linking_test_force_asoc_fail = force_asoc_fail;
+	}
+
+	return count;
+}
+#endif /* CONFIG_AP_MODE */
+
+int proc_get_ps_dbg_info(struct seq_file *m, void *v)
+{
+	struct net_device *dev = m->private;
+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
+	struct dvobj_priv *dvobj = padapter->dvobj;
+	struct debug_priv *pdbgpriv = &dvobj->drv_dbg;
+
+	RTW_PRINT_SEL(m, "dbg_sdio_alloc_irq_cnt=%d\n", pdbgpriv->dbg_sdio_alloc_irq_cnt);
+	RTW_PRINT_SEL(m, "dbg_sdio_free_irq_cnt=%d\n", pdbgpriv->dbg_sdio_free_irq_cnt);
+	RTW_PRINT_SEL(m, "dbg_sdio_alloc_irq_error_cnt=%d\n", pdbgpriv->dbg_sdio_alloc_irq_error_cnt);
+	RTW_PRINT_SEL(m, "dbg_sdio_free_irq_error_cnt=%d\n", pdbgpriv->dbg_sdio_free_irq_error_cnt);
+	RTW_PRINT_SEL(m, "dbg_sdio_init_error_cnt=%d\n", pdbgpriv->dbg_sdio_init_error_cnt);
+	RTW_PRINT_SEL(m, "dbg_sdio_deinit_error_cnt=%d\n", pdbgpriv->dbg_sdio_deinit_error_cnt);
+	RTW_PRINT_SEL(m, "dbg_suspend_error_cnt=%d\n", pdbgpriv->dbg_suspend_error_cnt);
+	RTW_PRINT_SEL(m, "dbg_suspend_cnt=%d\n", pdbgpriv->dbg_suspend_cnt);
+	RTW_PRINT_SEL(m, "dbg_resume_cnt=%d\n", pdbgpriv->dbg_resume_cnt);
+	RTW_PRINT_SEL(m, "dbg_resume_error_cnt=%d\n", pdbgpriv->dbg_resume_error_cnt);
+	RTW_PRINT_SEL(m, "dbg_deinit_fail_cnt=%d\n", pdbgpriv->dbg_deinit_fail_cnt);
+	RTW_PRINT_SEL(m, "dbg_carddisable_cnt=%d\n", pdbgpriv->dbg_carddisable_cnt);
+	RTW_PRINT_SEL(m, "dbg_ps_insuspend_cnt=%d\n", pdbgpriv->dbg_ps_insuspend_cnt);
+	RTW_PRINT_SEL(m, "dbg_dev_unload_inIPS_cnt=%d\n", pdbgpriv->dbg_dev_unload_inIPS_cnt);
+	RTW_PRINT_SEL(m, "dbg_scan_pwr_state_cnt=%d\n", pdbgpriv->dbg_scan_pwr_state_cnt);
+	RTW_PRINT_SEL(m, "dbg_downloadfw_pwr_state_cnt=%d\n", pdbgpriv->dbg_downloadfw_pwr_state_cnt);
+	RTW_PRINT_SEL(m, "dbg_carddisable_error_cnt=%d\n", pdbgpriv->dbg_carddisable_error_cnt);
+	RTW_PRINT_SEL(m, "dbg_fw_read_ps_state_fail_cnt=%d\n", pdbgpriv->dbg_fw_read_ps_state_fail_cnt);
+	RTW_PRINT_SEL(m, "dbg_leave_ips_fail_cnt=%d\n", pdbgpriv->dbg_leave_ips_fail_cnt);
+	RTW_PRINT_SEL(m, "dbg_leave_lps_fail_cnt=%d\n", pdbgpriv->dbg_leave_lps_fail_cnt);
+	RTW_PRINT_SEL(m, "dbg_h2c_leave32k_fail_cnt=%d\n", pdbgpriv->dbg_h2c_leave32k_fail_cnt);
+	RTW_PRINT_SEL(m, "dbg_diswow_dload_fw_fail_cnt=%d\n", pdbgpriv->dbg_diswow_dload_fw_fail_cnt);
+	RTW_PRINT_SEL(m, "dbg_enwow_dload_fw_fail_cnt=%d\n", pdbgpriv->dbg_enwow_dload_fw_fail_cnt);
+	RTW_PRINT_SEL(m, "dbg_ips_drvopen_fail_cnt=%d\n", pdbgpriv->dbg_ips_drvopen_fail_cnt);
+	RTW_PRINT_SEL(m, "dbg_poll_fail_cnt=%d\n", pdbgpriv->dbg_poll_fail_cnt);
+	RTW_PRINT_SEL(m, "dbg_rpwm_toogle_cnt=%d\n", pdbgpriv->dbg_rpwm_toogle_cnt);
+	RTW_PRINT_SEL(m, "dbg_rpwm_timeout_fail_cnt=%d\n", pdbgpriv->dbg_rpwm_timeout_fail_cnt);
+	RTW_PRINT_SEL(m, "dbg_sreset_cnt=%d\n", pdbgpriv->dbg_sreset_cnt);
+	RTW_PRINT_SEL(m, "dbg_fw_mem_dl_error_cnt=%d\n", pdbgpriv->dbg_fw_mem_dl_error_cnt);
+
+	return 0;
+}
+ssize_t proc_set_ps_dbg_info(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
+{
+	struct net_device *dev = data;
+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
+	struct dvobj_priv *dvobj = adapter->dvobj;
+	struct debug_priv *pdbgpriv = &dvobj->drv_dbg;
+	char tmp[32];
+	u8 ps_dbg_cmd_id;
+
+	if (count < 1)
+		return -EFAULT;
+
+	if (count > sizeof(tmp)) {
+		rtw_warn_on(1);
+		return -EFAULT;
+	}
+
+	if (buffer && !copy_from_user(tmp, buffer, count)) {
+
+		int num = sscanf(tmp, "%hhx", &ps_dbg_cmd_id);
+
+		if (num == 1 && ps_dbg_cmd_id == 1) /*Clean all*/
+			_rtw_memset(pdbgpriv, 0, sizeof(struct debug_priv));
+
+	}
+
+	return count;
+}
+
+
+#ifdef CONFIG_DBG_COUNTER
+
+int proc_get_rx_logs(struct seq_file *m, void *v)
+{
+	struct net_device *dev = m->private;
+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
+	struct rx_logs *rx_logs = &padapter->rx_logs;
+
+	RTW_PRINT_SEL(m,
+		      "intf_rx=%d\n"
+		      "intf_rx_err_recvframe=%d\n"
+		      "intf_rx_err_skb=%d\n"
+		      "intf_rx_report=%d\n"
+		      "core_rx=%d\n"
+		      "core_rx_pre=%d\n"
+		      "core_rx_pre_ver_err=%d\n"
+		      "core_rx_pre_mgmt=%d\n"
+		      "core_rx_pre_mgmt_err_80211w=%d\n"
+		      "core_rx_pre_mgmt_err=%d\n"
+		      "core_rx_pre_ctrl=%d\n"
+		      "core_rx_pre_ctrl_err=%d\n"
+		      "core_rx_pre_data=%d\n"
+		      "core_rx_pre_data_wapi_seq_err=%d\n"
+		      "core_rx_pre_data_wapi_key_err=%d\n"
+		      "core_rx_pre_data_handled=%d\n"
+		      "core_rx_pre_data_err=%d\n"
+		      "core_rx_pre_data_unknown=%d\n"
+		      "core_rx_pre_unknown=%d\n"
+		      "core_rx_enqueue=%d\n"
+		      "core_rx_dequeue=%d\n"
+		      "core_rx_post=%d\n"
+		      "core_rx_post_decrypt=%d\n"
+		      "core_rx_post_decrypt_wep=%d\n"
+		      "core_rx_post_decrypt_tkip=%d\n"
+		      "core_rx_post_decrypt_aes=%d\n"
+		      "core_rx_post_decrypt_wapi=%d\n"
+		      "core_rx_post_decrypt_hw=%d\n"
+		      "core_rx_post_decrypt_unknown=%d\n"
+		      "core_rx_post_decrypt_err=%d\n"
+		      "core_rx_post_defrag_err=%d\n"
+		      "core_rx_post_portctrl_err=%d\n"
+		      "core_rx_post_indicate=%d\n"
+		      "core_rx_post_indicate_in_oder=%d\n"
+		      "core_rx_post_indicate_reoder=%d\n"
+		      "core_rx_post_indicate_err=%d\n"
+		      "os_indicate=%d\n"
+		      "os_indicate_ap_mcast=%d\n"
+		      "os_indicate_ap_forward=%d\n"
+		      "os_indicate_ap_self=%d\n"
+		      "os_indicate_err=%d\n"
+		      "os_netif_ok=%d\n"
+		      "os_netif_err=%d\n",
+		      rx_logs->intf_rx,
+		      rx_logs->intf_rx_err_recvframe,
+		      rx_logs->intf_rx_err_skb,
+		      rx_logs->intf_rx_report,
+		      rx_logs->core_rx,
+		      rx_logs->core_rx_pre,
+		      rx_logs->core_rx_pre_ver_err,
+		      rx_logs->core_rx_pre_mgmt,
+		      rx_logs->core_rx_pre_mgmt_err_80211w,
+		      rx_logs->core_rx_pre_mgmt_err,
+		      rx_logs->core_rx_pre_ctrl,
+		      rx_logs->core_rx_pre_ctrl_err,
+		      rx_logs->core_rx_pre_data,
+		      rx_logs->core_rx_pre_data_wapi_seq_err,
+		      rx_logs->core_rx_pre_data_wapi_key_err,
+		      rx_logs->core_rx_pre_data_handled,
+		      rx_logs->core_rx_pre_data_err,
+		      rx_logs->core_rx_pre_data_unknown,
+		      rx_logs->core_rx_pre_unknown,
+		      rx_logs->core_rx_enqueue,
+		      rx_logs->core_rx_dequeue,
+		      rx_logs->core_rx_post,
+		      rx_logs->core_rx_post_decrypt,
+		      rx_logs->core_rx_post_decrypt_wep,
+		      rx_logs->core_rx_post_decrypt_tkip,
+		      rx_logs->core_rx_post_decrypt_aes,
+		      rx_logs->core_rx_post_decrypt_wapi,
+		      rx_logs->core_rx_post_decrypt_hw,
+		      rx_logs->core_rx_post_decrypt_unknown,
+		      rx_logs->core_rx_post_decrypt_err,
+		      rx_logs->core_rx_post_defrag_err,
+		      rx_logs->core_rx_post_portctrl_err,
+		      rx_logs->core_rx_post_indicate,
+		      rx_logs->core_rx_post_indicate_in_oder,
+		      rx_logs->core_rx_post_indicate_reoder,
+		      rx_logs->core_rx_post_indicate_err,
+		      rx_logs->os_indicate,
+		      rx_logs->os_indicate_ap_mcast,
+		      rx_logs->os_indicate_ap_forward,
+		      rx_logs->os_indicate_ap_self,
+		      rx_logs->os_indicate_err,
+		      rx_logs->os_netif_ok,
+		      rx_logs->os_netif_err
+		     );
+
+	return 0;
+}
+
+int proc_get_tx_logs(struct seq_file *m, void *v)
+{
+	struct net_device *dev = m->private;
+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
+	struct tx_logs *tx_logs = &padapter->tx_logs;
+
+	RTW_PRINT_SEL(m,
+		      "os_tx=%d\n"
+		      "os_tx_err_up=%d\n"
+		      "os_tx_err_xmit=%d\n"
+		      "os_tx_m2u=%d\n"
+		      "os_tx_m2u_ignore_fw_linked=%d\n"
+		      "os_tx_m2u_ignore_self=%d\n"
+		      "os_tx_m2u_entry=%d\n"
+		      "os_tx_m2u_entry_err_xmit=%d\n"
+		      "os_tx_m2u_entry_err_skb=%d\n"
+		      "os_tx_m2u_stop=%d\n"
+		      "core_tx=%d\n"
+		      "core_tx_err_pxmitframe=%d\n"
+		      "core_tx_err_brtx=%d\n"
+		      "core_tx_upd_attrib=%d\n"
+		      "core_tx_upd_attrib_adhoc=%d\n"
+		      "core_tx_upd_attrib_sta=%d\n"
+		      "core_tx_upd_attrib_ap=%d\n"
+		      "core_tx_upd_attrib_unknown=%d\n"
+		      "core_tx_upd_attrib_dhcp=%d\n"
+		      "core_tx_upd_attrib_icmp=%d\n"
+		      "core_tx_upd_attrib_active=%d\n"
+		      "core_tx_upd_attrib_err_ucast_sta=%d\n"
+		      "core_tx_upd_attrib_err_ucast_ap_link=%d\n"
+		      "core_tx_upd_attrib_err_sta=%d\n"
+		      "core_tx_upd_attrib_err_link=%d\n"
+		      "core_tx_upd_attrib_err_sec=%d\n"
+		      "core_tx_ap_enqueue_warn_fwstate=%d\n"
+		      "core_tx_ap_enqueue_warn_sta=%d\n"
+		      "core_tx_ap_enqueue_warn_nosta=%d\n"
+		      "core_tx_ap_enqueue_warn_link=%d\n"
+		      "core_tx_ap_enqueue_warn_trigger=%d\n"
+		      "core_tx_ap_enqueue_mcast=%d\n"
+		      "core_tx_ap_enqueue_ucast=%d\n"
+		      "core_tx_ap_enqueue=%d\n"
+		      "intf_tx=%d\n"
+		      "intf_tx_pending_ac=%d\n"
+		      "intf_tx_pending_fw_under_survey=%d\n"
+		      "intf_tx_pending_fw_under_linking=%d\n"
+		      "intf_tx_pending_xmitbuf=%d\n"
+		      "intf_tx_enqueue=%d\n"
+		      "core_tx_enqueue=%d\n"
+		      "core_tx_enqueue_class=%d\n"
+		      "core_tx_enqueue_class_err_sta=%d\n"
+		      "core_tx_enqueue_class_err_nosta=%d\n"
+		      "core_tx_enqueue_class_err_fwlink=%d\n"
+		      "intf_tx_direct=%d\n"
+		      "intf_tx_direct_err_coalesce=%d\n"
+		      "intf_tx_dequeue=%d\n"
+		      "intf_tx_dequeue_err_coalesce=%d\n"
+		      "intf_tx_dump_xframe=%d\n"
+		      "intf_tx_dump_xframe_err_txdesc=%d\n"
+		      "intf_tx_dump_xframe_err_port=%d\n",
+		      tx_logs->os_tx,
+		      tx_logs->os_tx_err_up,
+		      tx_logs->os_tx_err_xmit,
+		      tx_logs->os_tx_m2u,
+		      tx_logs->os_tx_m2u_ignore_fw_linked,
+		      tx_logs->os_tx_m2u_ignore_self,
+		      tx_logs->os_tx_m2u_entry,
+		      tx_logs->os_tx_m2u_entry_err_xmit,
+		      tx_logs->os_tx_m2u_entry_err_skb,
+		      tx_logs->os_tx_m2u_stop,
+		      tx_logs->core_tx,
+		      tx_logs->core_tx_err_pxmitframe,
+		      tx_logs->core_tx_err_brtx,
+		      tx_logs->core_tx_upd_attrib,
+		      tx_logs->core_tx_upd_attrib_adhoc,
+		      tx_logs->core_tx_upd_attrib_sta,
+		      tx_logs->core_tx_upd_attrib_ap,
+		      tx_logs->core_tx_upd_attrib_unknown,
+		      tx_logs->core_tx_upd_attrib_dhcp,
+		      tx_logs->core_tx_upd_attrib_icmp,
+		      tx_logs->core_tx_upd_attrib_active,
+		      tx_logs->core_tx_upd_attrib_err_ucast_sta,
+		      tx_logs->core_tx_upd_attrib_err_ucast_ap_link,
+		      tx_logs->core_tx_upd_attrib_err_sta,
+		      tx_logs->core_tx_upd_attrib_err_link,
+		      tx_logs->core_tx_upd_attrib_err_sec,
+		      tx_logs->core_tx_ap_enqueue_warn_fwstate,
+		      tx_logs->core_tx_ap_enqueue_warn_sta,
+		      tx_logs->core_tx_ap_enqueue_warn_nosta,
+		      tx_logs->core_tx_ap_enqueue_warn_link,
+		      tx_logs->core_tx_ap_enqueue_warn_trigger,
+		      tx_logs->core_tx_ap_enqueue_mcast,
+		      tx_logs->core_tx_ap_enqueue_ucast,
+		      tx_logs->core_tx_ap_enqueue,
+		      tx_logs->intf_tx,
+		      tx_logs->intf_tx_pending_ac,
+		      tx_logs->intf_tx_pending_fw_under_survey,
+		      tx_logs->intf_tx_pending_fw_under_linking,
+		      tx_logs->intf_tx_pending_xmitbuf,
+		      tx_logs->intf_tx_enqueue,
+		      tx_logs->core_tx_enqueue,
+		      tx_logs->core_tx_enqueue_class,
+		      tx_logs->core_tx_enqueue_class_err_sta,
+		      tx_logs->core_tx_enqueue_class_err_nosta,
+		      tx_logs->core_tx_enqueue_class_err_fwlink,
+		      tx_logs->intf_tx_direct,
+		      tx_logs->intf_tx_direct_err_coalesce,
+		      tx_logs->intf_tx_dequeue,
+		      tx_logs->intf_tx_dequeue_err_coalesce,
+		      tx_logs->intf_tx_dump_xframe,
+		      tx_logs->intf_tx_dump_xframe_err_txdesc,
+		      tx_logs->intf_tx_dump_xframe_err_port
+		     );
+
+	return 0;
+}
+
+int proc_get_int_logs(struct seq_file *m, void *v)
+{
+	struct net_device *dev = m->private;
+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
+
+	RTW_PRINT_SEL(m,
+		      "all=%d\n"
+		      "err=%d\n"
+		      "tbdok=%d\n"
+		      "tbder=%d\n"
+		      "bcnderr=%d\n"
+		      "bcndma=%d\n"
+		      "bcndma_e=%d\n"
+		      "rx=%d\n"
+		      "rx_rdu=%d\n"
+		      "rx_fovw=%d\n"
+		      "txfovw=%d\n"
+		      "mgntok=%d\n"
+		      "highdok=%d\n"
+		      "bkdok=%d\n"
+		      "bedok=%d\n"
+		      "vidok=%d\n"
+		      "vodok=%d\n",
+		      padapter->int_logs.all,
+		      padapter->int_logs.err,
+		      padapter->int_logs.tbdok,
+		      padapter->int_logs.tbder,
+		      padapter->int_logs.bcnderr,
+		      padapter->int_logs.bcndma,
+		      padapter->int_logs.bcndma_e,
+		      padapter->int_logs.rx,
+		      padapter->int_logs.rx_rdu,
+		      padapter->int_logs.rx_fovw,
+		      padapter->int_logs.txfovw,
+		      padapter->int_logs.mgntok,
+		      padapter->int_logs.highdok,
+		      padapter->int_logs.bkdok,
+		      padapter->int_logs.bedok,
+		      padapter->int_logs.vidok,
+		      padapter->int_logs.vodok
+		     );
+
+	return 0;
+}
+
+#endif /* CONFIG_DBG_COUNTER */
+
+int proc_get_hw_status(struct seq_file *m, void *v)
+{
+	struct net_device *dev = m->private;
+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
+	struct dvobj_priv *dvobj = padapter->dvobj;
+	struct debug_priv *pdbgpriv = &dvobj->drv_dbg;
+	struct registry_priv *regsty = dvobj_to_regsty(dvobj);
+
+	if (regsty->check_hw_status == 0)
+		RTW_PRINT_SEL(m, "RX FIFO full count: not check in watch dog\n");
+	else if (pdbgpriv->dbg_rx_fifo_last_overflow == 1
+	    && pdbgpriv->dbg_rx_fifo_curr_overflow == 1
+	    && pdbgpriv->dbg_rx_fifo_diff_overflow == 1
+	   )
+		RTW_PRINT_SEL(m, "RX FIFO full count: no implementation\n");
+	else {
+		RTW_PRINT_SEL(m, "RX FIFO full count: last_time=%llu, current_time=%llu, differential=%llu\n"
+			, pdbgpriv->dbg_rx_fifo_last_overflow, pdbgpriv->dbg_rx_fifo_curr_overflow, pdbgpriv->dbg_rx_fifo_diff_overflow);
+	}
+
+	return 0;
+}
+
+ssize_t proc_set_hw_status(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
+{
+	struct net_device *dev = data;
+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
+	struct dvobj_priv *dvobj = padapter->dvobj;
+	struct registry_priv *regsty = dvobj_to_regsty(dvobj);
+	char tmp[32];
+	u32 enable;
+
+	if (count < 1)
+		return -EFAULT;
+
+	if (count > sizeof(tmp)) {
+		rtw_warn_on(1);
+		return -EFAULT;
+	}
+
+	if (buffer && !copy_from_user(tmp, buffer, count)) {
+
+		int num = sscanf(tmp, "%d ", &enable);
+
+		if (num == 1 && regsty && enable <= 1) {
+			regsty->check_hw_status = enable;
+			RTW_INFO("check_hw_status=%d\n", regsty->check_hw_status);
+		}
+	}
+
+	return count;
+}
+
+#ifdef CONFIG_HUAWEI_PROC
+int proc_get_huawei_trx_info(struct seq_file *sel, void *v)
+{
+	struct net_device *dev = sel->private;
+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
+	struct dm_struct *dm = adapter_to_phydm(padapter);
+	struct sta_info *psta;
+	struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
+	struct macid_ctl_t *macid_ctl = dvobj_to_macidctl(dvobj);
+	struct ra_sta_info *ra_info;
+	u8 curr_tx_sgi = _FALSE;
+	u8 curr_tx_rate = 0;
+	u8 mac_id;
+#ifdef DBG_RX_SIGNAL_DISPLAY_RAW_DATA
+	u8 isCCKrate, rf_path;
+	PHAL_DATA_TYPE	pHalData =  GET_HAL_DATA(padapter);
+	struct rx_raw_rssi *psample_pkt_rssi = &padapter->recvpriv.raw_rssi_info;
+#endif
+
+	if (!dm->is_linked) {
+		RTW_PRINT_SEL(sel, "NO link\n\n");
+		return 0;
+	}
+
+	/*============  tx info ============	*/
+	for (mac_id = 0; mac_id < macid_ctl->num; mac_id++) {
+		if (rtw_macid_is_used(macid_ctl, mac_id) && !rtw_macid_is_bmc(macid_ctl, mac_id)) {
+			psta = macid_ctl->sta[mac_id];
+			if (!psta)
+				continue;
+
+			RTW_PRINT_SEL(sel, "STA [" MAC_FMT "]\n", MAC_ARG(psta->cmn.mac_addr));
+
+			ra_info = &psta->cmn.ra_info;
+			curr_tx_sgi = rtw_get_current_tx_sgi(padapter, psta);
+			curr_tx_rate = rtw_get_current_tx_rate(padapter, psta);
+			RTW_PRINT_SEL(sel, "curr_tx_rate : %s (%s)\n",
+					HDATA_RATE(curr_tx_rate), (curr_tx_sgi) ? "S" : "L");
+			RTW_PRINT_SEL(sel, "curr_tx_bw : %s\n", ch_width_str(ra_info->curr_tx_bw));
+		}
+	}
+
+	/*============  rx info ============	*/
+	RTW_PRINT_SEL(sel, "rx_rate : %s\n", HDATA_RATE(dm->rx_rate));
+#ifdef DBG_RX_SIGNAL_DISPLAY_RAW_DATA
+	isCCKrate = (psample_pkt_rssi->data_rate <= DESC_RATE11M) ? TRUE : FALSE;
+
+	for (rf_path = 0; rf_path < pHalData->NumTotalRFPath; rf_path++) {
+		if (!isCCKrate)
+			_RTW_PRINT_SEL(sel , "RF_PATH_%d : rx_ofdm_pwr:%d(dBm), rx_ofdm_snr:%d(dB)\n",
+				rf_path, psample_pkt_rssi->ofdm_pwr[rf_path], psample_pkt_rssi->ofdm_snr[rf_path]);
+	}
+#endif
+	RTW_PRINT_SEL(sel, "\n");
+	return 0;
+}
+#endif /* CONFIG_HUAWEI_PROC */
+
+int proc_get_trx_info_debug(struct seq_file *m, void *v)
+{
+	struct net_device *dev = m->private;
+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
+
+	/*============  tx info ============	*/
+	rtw_hal_get_def_var(padapter, HW_DEF_RA_INFO_DUMP, m);
+
+	/*============  rx info ============	*/
+	rtw_hal_set_odm_var(padapter, HAL_ODM_RX_INFO_DUMP, m, _FALSE);
+
+	return 0;
+}
+
+int proc_get_rx_signal(struct seq_file *m, void *v)
+{
+	struct net_device *dev = m->private;
+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
+
+	RTW_PRINT_SEL(m, "rssi:%d\n", padapter->recvpriv.rssi);
+#ifdef CONFIG_MP_INCLUDED
+	if (padapter->registrypriv.mp_mode == 1) {
+		struct dm_struct *odm = adapter_to_phydm(padapter);
+		if (padapter->mppriv.antenna_rx == ANTENNA_A)
+			RTW_PRINT_SEL(m, "Antenna: A\n");
+		else if (padapter->mppriv.antenna_rx == ANTENNA_B)
+			RTW_PRINT_SEL(m, "Antenna: B\n");
+		else if (padapter->mppriv.antenna_rx == ANTENNA_C)
+			RTW_PRINT_SEL(m, "Antenna: C\n");
+		else if (padapter->mppriv.antenna_rx == ANTENNA_D)
+			RTW_PRINT_SEL(m, "Antenna: D\n");
+		else if (padapter->mppriv.antenna_rx == ANTENNA_AB)
+			RTW_PRINT_SEL(m, "Antenna: AB\n");
+		else if (padapter->mppriv.antenna_rx == ANTENNA_BC)
+			RTW_PRINT_SEL(m, "Antenna: BC\n");
+		else if (padapter->mppriv.antenna_rx == ANTENNA_CD)
+			RTW_PRINT_SEL(m, "Antenna: CD\n");
+		else
+			RTW_PRINT_SEL(m, "Antenna: __\n");
+
+		RTW_PRINT_SEL(m, "rx_rate = %s\n", HDATA_RATE(odm->rx_rate));
+		return 0;
+	} else 
+#endif
+	{
+		/* RTW_PRINT_SEL(m, "rxpwdb:%d\n", padapter->recvpriv.rxpwdb); */
+		RTW_PRINT_SEL(m, "signal_strength:%u\n", padapter->recvpriv.signal_strength);
+		RTW_PRINT_SEL(m, "signal_qual:%u\n", padapter->recvpriv.signal_qual);
+	}
+#ifdef DBG_RX_SIGNAL_DISPLAY_RAW_DATA
+	rtw_odm_get_perpkt_rssi(m, padapter);
+	rtw_get_raw_rssi_info(m, padapter);
+#endif
+	return 0;
+}
+
+ssize_t proc_set_rx_signal(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
+{
+	struct net_device *dev = data;
+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
+	char tmp[32];
+	u32 is_signal_dbg, signal_strength;
+
+	if (count < 1)
+		return -EFAULT;
+
+	if (count > sizeof(tmp)) {
+		rtw_warn_on(1);
+		return -EFAULT;
+	}
+
+	if (buffer && !copy_from_user(tmp, buffer, count)) {
+
+		int num = sscanf(tmp, "%u %u", &is_signal_dbg, &signal_strength);
+
+		if (num < 1)
+			return count;
+
+		is_signal_dbg = is_signal_dbg == 0 ? 0 : 1;
+
+		if (is_signal_dbg && num < 2)
+			return count;
+
+		signal_strength = signal_strength > 100 ? 100 : signal_strength;
+
+		padapter->recvpriv.is_signal_dbg = is_signal_dbg;
+		padapter->recvpriv.signal_strength_dbg = signal_strength;
+
+		if (is_signal_dbg)
+			RTW_INFO("set %s %u\n", "DBG_SIGNAL_STRENGTH", signal_strength);
+		else
+			RTW_INFO("set %s\n", "HW_SIGNAL_STRENGTH");
+
+	}
+
+	return count;
+
+}
+
+int proc_get_mac_rptbuf(struct seq_file *m, void *v)
+{
+	struct net_device *dev = m->private;
+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
+	u16 i;
+	u16 mac_id;
+	u32 shcut_addr = 0;
+	u32 read_addr = 0;
+#ifdef CONFIG_RTL8814A
+	RTW_PRINT_SEL(m, "TX ShortCut:\n");
+	for (mac_id = 0; mac_id < 64; mac_id++) {
+		rtw_write16(padapter, 0x140, 0x662 | ((mac_id & BIT5) >> 5));
+		shcut_addr = 0x8000;
+		shcut_addr = shcut_addr | ((mac_id & 0x1f) << 7);
+		RTW_PRINT_SEL(m, "mac_id=%d, 0x140=%x =>\n", mac_id, 0x662 | ((mac_id & BIT5) >> 5));
+		for (i = 0; i < 30; i++) {
+			read_addr = 0;
+			read_addr = shcut_addr | (i << 2);
+			RTW_PRINT_SEL(m, "i=%02d: MAC_%04x= %08x ", i, read_addr, rtw_read32(padapter, read_addr));
+			if (!((i + 1) % 4))
+				RTW_PRINT_SEL(m, "\n");
+			if (i == 29)
+				RTW_PRINT_SEL(m, "\n");
+		}
+	}
+#endif /* CONFIG_RTL8814A */
+	return 0;
+}
+
+#ifdef CONFIG_80211N_HT
+
+int proc_get_ht_enable(struct seq_file *m, void *v)
+{
+	struct net_device *dev = m->private;
+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
+	struct registry_priv	*pregpriv = &padapter->registrypriv;
+
+	if (pregpriv)
+		RTW_PRINT_SEL(m, "%d\n", pregpriv->ht_enable);
+
+	return 0;
+}
+
+ssize_t proc_set_ht_enable(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
+{
+	struct net_device *dev = data;
+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
+	struct registry_priv	*pregpriv = &padapter->registrypriv;
+	char tmp[32];
+	u32 mode;
+
+	if (count < 1)
+		return -EFAULT;
+
+	if (count > sizeof(tmp)) {
+		rtw_warn_on(1);
+		return -EFAULT;
+	}
+
+	if (buffer && !copy_from_user(tmp, buffer, count)) {
+
+		int num = sscanf(tmp, "%d ", &mode);
+
+		if ( num == 1 && pregpriv && mode < 2) {
+			pregpriv->ht_enable = mode;
+			RTW_INFO("ht_enable=%d\n", pregpriv->ht_enable);
+		}
+	}
+
+	return count;
+
+}
+
+int proc_get_bw_mode(struct seq_file *m, void *v)
+{
+	struct net_device *dev = m->private;
+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
+	struct registry_priv	*pregpriv = &padapter->registrypriv;
+
+	if (pregpriv)
+		RTW_PRINT_SEL(m, "0x%02x\n", pregpriv->bw_mode);
+
+	return 0;
+}
+
+ssize_t proc_set_bw_mode(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
+{
+	struct net_device *dev = data;
+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
+	struct registry_priv	*pregpriv = &padapter->registrypriv;
+	char tmp[32];
+	u32 mode;
+	u8 bw_2g;
+	u8 bw_5g;
+
+	if (count < 1)
+		return -EFAULT;
+
+	if (count > sizeof(tmp)) {
+		rtw_warn_on(1);
+		return -EFAULT;
+	}
+
+	if (buffer && !copy_from_user(tmp, buffer, count)) {
+
+		int num = sscanf(tmp, "%x ", &mode);
+		bw_5g = mode >> 4;
+		bw_2g = mode & 0x0f;
+
+		if (num == 1 && pregpriv && bw_2g <= 4 && bw_5g <= 4) {
+			pregpriv->bw_mode = mode;
+			printk("bw_mode=0x%x\n", mode);
+		}
+	}
+
+	return count;
+
+}
+
+int proc_get_ampdu_enable(struct seq_file *m, void *v)
+{
+	struct net_device *dev = m->private;
+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
+	struct registry_priv	*pregpriv = &padapter->registrypriv;
+
+	if (pregpriv)
+		RTW_PRINT_SEL(m, "%d\n", pregpriv->ampdu_enable);
+
+	return 0;
+}
+
+ssize_t proc_set_ampdu_enable(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
+{
+	struct net_device *dev = data;
+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
+	struct registry_priv	*pregpriv = &padapter->registrypriv;
+	char tmp[32];
+	u32 mode;
+
+	if (count < 1)
+		return -EFAULT;
+
+	if (count > sizeof(tmp)) {
+		rtw_warn_on(1);
+		return -EFAULT;
+	}
+
+	if (buffer && !copy_from_user(tmp, buffer, count)) {
+
+		int num = sscanf(tmp, "%d ", &mode);
+
+		if (num == 1 && pregpriv && mode < 2) {
+			pregpriv->ampdu_enable = mode;
+			printk("ampdu_enable=%d\n", mode);
+		}
+
+	}
+
+	return count;
+
+}
+
+
+void dump_regsty_rx_ampdu_size_limit(void *sel, _adapter *adapter)
+{
+	struct registry_priv *regsty = adapter_to_regsty(adapter);
+	int i;
+
+	RTW_PRINT_SEL(sel, "%-3s %-3s %-3s %-3s %-4s\n"
+		, "", "20M", "40M", "80M", "160M");
+	for (i = 0; i < 4; i++)
+		RTW_PRINT_SEL(sel, "%dSS %3u %3u %3u %4u\n", i + 1
+			, regsty->rx_ampdu_sz_limit_by_nss_bw[i][0]
+			, regsty->rx_ampdu_sz_limit_by_nss_bw[i][1]
+			, regsty->rx_ampdu_sz_limit_by_nss_bw[i][2]
+			, regsty->rx_ampdu_sz_limit_by_nss_bw[i][3]);
+}
+
+int proc_get_rx_ampdu(struct seq_file *m, void *v)
+{
+	struct net_device *dev = m->private;
+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
+
+	_RTW_PRINT_SEL(m, "accept: ");
+	if (padapter->fix_rx_ampdu_accept == RX_AMPDU_ACCEPT_INVALID)
+		RTW_PRINT_SEL(m, "%u%s\n", rtw_rx_ampdu_is_accept(padapter), "(auto)");
+	else
+		RTW_PRINT_SEL(m, "%u%s\n", padapter->fix_rx_ampdu_accept, "(fixed)");
+
+	_RTW_PRINT_SEL(m, "size: ");
+	if (padapter->fix_rx_ampdu_size == RX_AMPDU_SIZE_INVALID) {
+		RTW_PRINT_SEL(m, "%u%s\n", rtw_rx_ampdu_size(padapter), "(auto) with conditional limit:");
+		dump_regsty_rx_ampdu_size_limit(m, padapter);
+	} else
+		RTW_PRINT_SEL(m, "%u%s\n", padapter->fix_rx_ampdu_size, "(fixed)");
+	RTW_PRINT_SEL(m, "\n");
+
+	RTW_PRINT_SEL(m, "%19s %17s\n", "fix_rx_ampdu_accept", "fix_rx_ampdu_size");
+
+	_RTW_PRINT_SEL(m, "%-19d %-17u\n"
+		, padapter->fix_rx_ampdu_accept
+		, padapter->fix_rx_ampdu_size);
+
+	return 0;
+}
+
+ssize_t proc_set_rx_ampdu(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
+{
+	struct net_device *dev = data;
+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
+	char tmp[32];
+	u8 accept;
+	u8 size;
+
+	if (count < 1)
+		return -EFAULT;
+
+	if (count > sizeof(tmp)) {
+		rtw_warn_on(1);
+		return -EFAULT;
+	}
+
+	if (buffer && !copy_from_user(tmp, buffer, count)) {
+
+		int num = sscanf(tmp, "%hhu %hhu", &accept, &size);
+
+		if (num >= 1)
+			rtw_rx_ampdu_set_accept(padapter, accept, RX_AMPDU_DRV_FIXED);
+		if (num >= 2)
+			rtw_rx_ampdu_set_size(padapter, size, RX_AMPDU_DRV_FIXED);
+
+		rtw_rx_ampdu_apply(padapter);
+	}
+
+	return count;
+}
+
+int proc_get_rx_ampdu_factor(struct seq_file *m, void *v)
+{
+	struct net_device *dev = m->private;
+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
+
+
+	if (padapter)
+		RTW_PRINT_SEL(m, "rx ampdu factor = %x\n", padapter->driver_rx_ampdu_factor);
+
+	return 0;
+}
+
+ssize_t proc_set_rx_ampdu_factor(struct file *file, const char __user *buffer
+				 , size_t count, loff_t *pos, void *data)
+{
+	struct net_device *dev = data;
+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
+	char tmp[32];
+	u32 factor;
+
+	if (count < 1)
+		return -EFAULT;
+
+	if (count > sizeof(tmp)) {
+		rtw_warn_on(1);
+		return -EFAULT;
+	}
+
+	if (buffer && !copy_from_user(tmp, buffer, count)) {
+
+		int num = sscanf(tmp, "%d ", &factor);
+
+		if (padapter && (num == 1)) {
+			RTW_INFO("padapter->driver_rx_ampdu_factor = %x\n", factor);
+
+			if (factor  > 0x03)
+				padapter->driver_rx_ampdu_factor = 0xFF;
+			else
+				padapter->driver_rx_ampdu_factor = factor;
+		}
+	}
+
+	return count;
+}
+
+int proc_get_tx_max_agg_num(struct seq_file *m, void *v)
+{
+	struct net_device *dev = m->private;
+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
+
+
+	if (padapter)
+		RTW_PRINT_SEL(m, "tx max AMPDU num = 0x%02x\n", padapter->driver_tx_max_agg_num);
+
+	return 0;
+}
+
+ssize_t proc_set_tx_max_agg_num(struct file *file, const char __user *buffer
+				 , size_t count, loff_t *pos, void *data)
+{
+	struct net_device *dev = data;
+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
+	char tmp[32];
+	u8 agg_num;
+
+	if (count < 1)
+		return -EFAULT;
+
+	if (count > sizeof(tmp)) {
+		rtw_warn_on(1);
+		return -EFAULT;
+	}
+
+	if (buffer && !copy_from_user(tmp, buffer, count)) {
+
+		int num = sscanf(tmp, "%hhx ", &agg_num);
+
+		if (padapter && (num == 1)) {
+			RTW_INFO("padapter->driver_tx_max_agg_num = 0x%02x\n", agg_num);
+
+			padapter->driver_tx_max_agg_num = agg_num;
+		}
+	}
+
+	return count;
+}
+
+int proc_get_rx_ampdu_density(struct seq_file *m, void *v)
+{
+	struct net_device *dev = m->private;
+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
+
+
+	if (padapter)
+		RTW_PRINT_SEL(m, "rx ampdu densityg = %x\n", padapter->driver_rx_ampdu_spacing);
+
+	return 0;
+}
+
+ssize_t proc_set_rx_ampdu_density(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
+{
+	struct net_device *dev = data;
+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
+	char tmp[32];
+	u32 density;
+
+	if (count < 1)
+		return -EFAULT;
+
+	if (count > sizeof(tmp)) {
+		rtw_warn_on(1);
+		return -EFAULT;
+	}
+
+	if (buffer && !copy_from_user(tmp, buffer, count)) {
+
+		int num = sscanf(tmp, "%d ", &density);
+
+		if (padapter && (num == 1)) {
+			RTW_INFO("padapter->driver_rx_ampdu_spacing = %x\n", density);
+
+			if (density > 0x07)
+				padapter->driver_rx_ampdu_spacing = 0xFF;
+			else
+				padapter->driver_rx_ampdu_spacing = density;
+		}
+	}
+
+	return count;
+}
+
+int proc_get_tx_ampdu_density(struct seq_file *m, void *v)
+{
+	struct net_device *dev = m->private;
+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
+
+
+	if (padapter)
+		RTW_PRINT_SEL(m, "tx ampdu density = %x\n", padapter->driver_ampdu_spacing);
+
+	return 0;
+}
+
+ssize_t proc_set_tx_ampdu_density(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
+{
+	struct net_device *dev = data;
+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
+	char tmp[32];
+	u32 density;
+
+	if (count < 1)
+		return -EFAULT;
+
+	if (count > sizeof(tmp)) {
+		rtw_warn_on(1);
+		return -EFAULT;
+	}
+
+	if (buffer && !copy_from_user(tmp, buffer, count)) {
+
+		int num = sscanf(tmp, "%d ", &density);
+
+		if (padapter && (num == 1)) {
+			RTW_INFO("padapter->driver_ampdu_spacing = %x\n", density);
+
+			if (density > 0x07)
+				padapter->driver_ampdu_spacing = 0xFF;
+			else
+				padapter->driver_ampdu_spacing = density;
+		}
+	}
+
+	return count;
+}
+
+#ifdef CONFIG_TX_AMSDU
+int proc_get_tx_amsdu(struct seq_file *m, void *v)
+{
+	struct net_device *dev = m->private;
+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
+	struct xmit_priv *pxmitpriv = &padapter->xmitpriv;
+
+	if (padapter)
+	{
+		RTW_PRINT_SEL(m, "tx amsdu = %d\n", padapter->tx_amsdu);
+		RTW_PRINT_SEL(m, "amsdu set timer conut = %u\n", pxmitpriv->amsdu_debug_set_timer);
+		RTW_PRINT_SEL(m, "amsdu  time out count = %u\n", pxmitpriv->amsdu_debug_timeout);
+		RTW_PRINT_SEL(m, "amsdu coalesce one count = %u\n", pxmitpriv->amsdu_debug_coalesce_one);
+		RTW_PRINT_SEL(m, "amsdu coalesce two count = %u\n", pxmitpriv->amsdu_debug_coalesce_two);
+	}
+
+	return 0;
+}
+
+ssize_t proc_set_tx_amsdu(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
+{
+	struct net_device *dev = data;
+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
+	struct xmit_priv *pxmitpriv = &padapter->xmitpriv;
+	char tmp[32];
+	u32 amsdu;
+
+	if (count < 1)
+		return -EFAULT;
+
+	if (count > sizeof(tmp)) {
+		rtw_warn_on(1);
+		return -EFAULT;
+	}
+
+	if (buffer && !copy_from_user(tmp, buffer, count)) {
+
+		int num = sscanf(tmp, "%d ", &amsdu);
+
+		if (padapter && (num == 1)) {
+			RTW_INFO("padapter->tx_amsdu = %x\n", amsdu);
+
+			if (amsdu > 3)
+				padapter->tx_amsdu = 0;
+			else if(amsdu == 3)
+			{
+				pxmitpriv->amsdu_debug_set_timer = 0;
+				pxmitpriv->amsdu_debug_timeout = 0;
+				pxmitpriv->amsdu_debug_coalesce_one = 0;
+				pxmitpriv->amsdu_debug_coalesce_two = 0;
+			}
+			else
+				padapter->tx_amsdu = amsdu;
+		}
+	}
+
+	return count;
+}
+
+int proc_get_tx_amsdu_rate(struct seq_file *m, void *v)
+{
+	struct net_device *dev = m->private;
+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
+
+	if (padapter)
+		RTW_PRINT_SEL(m, "tx amsdu rate = %d Mbps\n", padapter->tx_amsdu_rate);
+
+	return 0;
+}
+
+ssize_t proc_set_tx_amsdu_rate(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
+{
+	struct net_device *dev = data;
+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
+	char tmp[32];
+	u32 amsdu_rate;
+
+	if (count < 1)
+		return -EFAULT;
+
+	if (count > sizeof(tmp)) {
+		rtw_warn_on(1);
+		return -EFAULT;
+	}
+
+	if (buffer && !copy_from_user(tmp, buffer, count)) {
+
+		int num = sscanf(tmp, "%d ", &amsdu_rate);
+
+		if (padapter && (num == 1)) {
+			RTW_INFO("padapter->tx_amsdu_rate = %x\n", amsdu_rate);
+			padapter->tx_amsdu_rate = amsdu_rate;
+		}
+	}
+
+	return count;
+}
+#endif /* CONFIG_TX_AMSDU */
+#endif /* CONFIG_80211N_HT */
+
+int proc_get_en_fwps(struct seq_file *m, void *v)
+{
+	struct net_device *dev = m->private;
+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
+	struct registry_priv	*pregpriv = &padapter->registrypriv;
+
+	if (pregpriv)
+		RTW_PRINT_SEL(m, "check_fw_ps = %d , 1:enable get FW PS state , 0: disable get FW PS state\n"
+			      , pregpriv->check_fw_ps);
+
+	return 0;
+}
+
+ssize_t proc_set_en_fwps(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
+{
+	struct net_device *dev = data;
+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
+	struct registry_priv	*pregpriv = &padapter->registrypriv;
+	char tmp[32];
+	u32 mode;
+
+	if (count < 1)
+		return -EFAULT;
+
+	if (count > sizeof(tmp)) {
+		rtw_warn_on(1);
+		return -EFAULT;
+	}
+
+	if (buffer && !copy_from_user(tmp, buffer, count)) {
+
+		int num = sscanf(tmp, "%d ", &mode);
+
+		if (num == 1 && pregpriv &&  mode < 2) {
+			pregpriv->check_fw_ps = mode;
+			RTW_INFO("pregpriv->check_fw_ps=%d\n", pregpriv->check_fw_ps);
+		}
+
+	}
+
+	return count;
+}
+
+/*
+int proc_get_two_path_rssi(struct seq_file *m, void *v)
+{
+	struct net_device *dev = m->private;
+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
+
+	if(padapter)
+		RTW_PRINT_SEL(m, "%d %d\n",
+			padapter->recvpriv.RxRssi[0], padapter->recvpriv.RxRssi[1]);
+
+	return 0;
+}
+*/
+#ifdef CONFIG_80211N_HT
+void rtw_dump_dft_phy_cap(void *sel, _adapter *adapter)
+{
+	struct mlme_priv *pmlmepriv = &adapter->mlmepriv;
+	struct ht_priv	*phtpriv = &pmlmepriv->htpriv;
+	#ifdef CONFIG_80211AC_VHT
+	struct vht_priv *pvhtpriv = &pmlmepriv->vhtpriv;
+	#endif
+
+	#ifdef CONFIG_80211AC_VHT
+	RTW_PRINT_SEL(sel, "[DFT CAP] VHT STBC Tx : %s\n", (TEST_FLAG(pvhtpriv->stbc_cap, STBC_VHT_ENABLE_TX)) ? "V" : "X");
+	RTW_PRINT_SEL(sel, "[DFT CAP] VHT STBC Rx : %s\n", (TEST_FLAG(pvhtpriv->stbc_cap, STBC_VHT_ENABLE_RX)) ? "V" : "X");
+	#endif
+	RTW_PRINT_SEL(sel, "[DFT CAP] HT STBC Tx : %s\n", (TEST_FLAG(phtpriv->stbc_cap, STBC_HT_ENABLE_TX)) ? "V" : "X");
+	RTW_PRINT_SEL(sel, "[DFT CAP] HT STBC Rx : %s\n\n", (TEST_FLAG(phtpriv->stbc_cap, STBC_HT_ENABLE_RX)) ? "V" : "X");
+
+	#ifdef CONFIG_80211AC_VHT
+	RTW_PRINT_SEL(sel, "[DFT CAP] VHT LDPC Tx : %s\n", (TEST_FLAG(pvhtpriv->ldpc_cap, LDPC_VHT_ENABLE_TX)) ? "V" : "X");
+	RTW_PRINT_SEL(sel, "[DFT CAP] VHT LDPC Rx : %s\n", (TEST_FLAG(pvhtpriv->ldpc_cap, LDPC_VHT_ENABLE_RX)) ? "V" : "X");
+	#endif
+	RTW_PRINT_SEL(sel, "[DFT CAP] HT LDPC Tx : %s\n", (TEST_FLAG(phtpriv->ldpc_cap, LDPC_HT_ENABLE_TX)) ? "V" : "X");
+	RTW_PRINT_SEL(sel, "[DFT CAP] HT LDPC Rx : %s\n\n", (TEST_FLAG(phtpriv->ldpc_cap, LDPC_HT_ENABLE_RX)) ? "V" : "X");
+
+	#ifdef CONFIG_BEAMFORMING
+	#ifdef CONFIG_80211AC_VHT
+	RTW_PRINT_SEL(sel, "[DFT CAP] VHT MU Bfer : %s\n", (TEST_FLAG(pvhtpriv->beamform_cap, BEAMFORMING_VHT_MU_MIMO_AP_ENABLE)) ? "V" : "X");
+	RTW_PRINT_SEL(sel, "[DFT CAP] VHT MU Bfee : %s\n", (TEST_FLAG(pvhtpriv->beamform_cap, BEAMFORMING_VHT_MU_MIMO_STA_ENABLE)) ? "V" : "X");
+	RTW_PRINT_SEL(sel, "[DFT CAP] VHT SU Bfer : %s\n", (TEST_FLAG(pvhtpriv->beamform_cap, BEAMFORMING_VHT_BEAMFORMER_ENABLE)) ? "V" : "X");
+	RTW_PRINT_SEL(sel, "[DFT CAP] VHT SU Bfee : %s\n", (TEST_FLAG(pvhtpriv->beamform_cap, BEAMFORMING_VHT_BEAMFORMEE_ENABLE)) ? "V" : "X");
+	#endif
+	RTW_PRINT_SEL(sel, "[DFT CAP] HT Bfer : %s\n", (TEST_FLAG(phtpriv->beamform_cap, BEAMFORMING_HT_BEAMFORMER_ENABLE))  ? "V" : "X");
+	RTW_PRINT_SEL(sel, "[DFT CAP] HT Bfee : %s\n", (TEST_FLAG(phtpriv->beamform_cap, BEAMFORMING_HT_BEAMFORMEE_ENABLE)) ? "V" : "X");
+	#endif
+}
+
+void rtw_get_dft_phy_cap(void *sel, _adapter *adapter)
+{
+	RTW_PRINT_SEL(sel, "\n ======== PHY CAP protocol ========\n");
+	rtw_ht_use_default_setting(adapter);
+	#ifdef CONFIG_80211AC_VHT
+	rtw_vht_use_default_setting(adapter);
+	#endif
+	#ifdef CONFIG_80211N_HT
+	rtw_dump_dft_phy_cap(sel, adapter);
+	#endif
+}
+
+void rtw_dump_drv_phy_cap(void *sel, _adapter *adapter)
+{
+	struct registry_priv	*pregistry_priv = &adapter->registrypriv;
+
+	RTW_PRINT_SEL(sel, "\n ======== DRV's configuration ========\n");
+	#if 0
+	RTW_PRINT_SEL(sel, "[DRV CAP] TRx Capability : 0x%08x\n", phy_spec->trx_cap);
+	RTW_PRINT_SEL(sel, "[DRV CAP] Tx Stream Num Index : %d\n", (phy_spec->trx_cap >> 24) & 0xFF); /*Tx Stream Num Index [31:24]*/
+	RTW_PRINT_SEL(sel, "[DRV CAP] Rx Stream Num Index : %d\n", (phy_spec->trx_cap >> 16) & 0xFF); /*Rx Stream Num Index [23:16]*/
+	RTW_PRINT_SEL(sel, "[DRV CAP] Tx Path Num Index : %d\n", (phy_spec->trx_cap >> 8) & 0xFF);/*Tx Path Num Index	[15:8]*/
+	RTW_PRINT_SEL(sel, "[DRV CAP] Rx Path Num Index : %d\n", (phy_spec->trx_cap & 0xFF));/*Rx Path Num Index	[7:0]*/
+	#endif
+	#ifdef CONFIG_80211N_HT
+	RTW_PRINT_SEL(sel, "[DRV CAP] STBC Capability : 0x%02x\n", pregistry_priv->stbc_cap);
+	RTW_PRINT_SEL(sel, "[DRV CAP] VHT STBC Tx : %s\n", (TEST_FLAG(pregistry_priv->stbc_cap, BIT1)) ? "V" : "X"); /*BIT1: Enable VHT STBC Tx*/
+	RTW_PRINT_SEL(sel, "[DRV CAP] VHT STBC Rx : %s\n", (TEST_FLAG(pregistry_priv->stbc_cap, BIT0)) ? "V" : "X"); /*BIT0: Enable VHT STBC Rx*/
+	RTW_PRINT_SEL(sel, "[DRV CAP] HT STBC Tx : %s\n", (TEST_FLAG(pregistry_priv->stbc_cap, BIT5)) ? "V" : "X"); /*BIT5: Enable HT STBC Tx*/
+	RTW_PRINT_SEL(sel, "[DRV CAP] HT STBC Rx : %s\n\n", (TEST_FLAG(pregistry_priv->stbc_cap, BIT4)) ? "V" : "X"); /*BIT4: Enable HT STBC Rx*/
+
+	RTW_PRINT_SEL(sel, "[DRV CAP] LDPC Capability : 0x%02x\n", pregistry_priv->ldpc_cap);
+	RTW_PRINT_SEL(sel, "[DRV CAP] VHT LDPC Tx : %s\n", (TEST_FLAG(pregistry_priv->ldpc_cap, BIT1)) ? "V" : "X"); /*BIT1: Enable VHT LDPC Tx*/
+	RTW_PRINT_SEL(sel, "[DRV CAP] VHT LDPC Rx : %s\n", (TEST_FLAG(pregistry_priv->ldpc_cap, BIT0)) ? "V" : "X"); /*BIT0: Enable VHT LDPC Rx*/
+	RTW_PRINT_SEL(sel, "[DRV CAP] HT LDPC Tx : %s\n", (TEST_FLAG(pregistry_priv->ldpc_cap, BIT5)) ? "V" : "X"); /*BIT5: Enable HT LDPC Tx*/
+	RTW_PRINT_SEL(sel, "[DRV CAP] HT LDPC Rx : %s\n\n", (TEST_FLAG(pregistry_priv->ldpc_cap, BIT4)) ? "V" : "X"); /*BIT4: Enable HT LDPC Rx*/
+	#endif /* CONFIG_80211N_HT */
+	#ifdef CONFIG_BEAMFORMING
+	#if 0
+	RTW_PRINT_SEL(sel, "[DRV CAP] TxBF parameter : 0x%08x\n", phy_spec->txbf_param);
+	RTW_PRINT_SEL(sel, "[DRV CAP] VHT Sounding Dim : %d\n", (phy_spec->txbf_param >> 24) & 0xFF); /*VHT Sounding Dim [31:24]*/
+	RTW_PRINT_SEL(sel, "[DRV CAP] VHT Steering Ant : %d\n", (phy_spec->txbf_param >> 16) & 0xFF); /*VHT Steering Ant [23:16]*/
+	RTW_PRINT_SEL(sel, "[DRV CAP] HT Sounding Dim : %d\n", (phy_spec->txbf_param >> 8) & 0xFF); /*HT Sounding Dim [15:8]*/
+	RTW_PRINT_SEL(sel, "[DRV CAP] HT Steering Ant : %d\n", phy_spec->txbf_param & 0xFF); /*HT Steering Ant [7:0]*/
+	#endif
+
+	/*
+	 * BIT0: Enable VHT SU Beamformer
+	 * BIT1: Enable VHT SU Beamformee
+	 * BIT2: Enable VHT MU Beamformer, depend on VHT SU Beamformer
+	 * BIT3: Enable VHT MU Beamformee, depend on VHT SU Beamformee
+	 * BIT4: Enable HT Beamformer
+	 * BIT5: Enable HT Beamformee
+	 */
+	RTW_PRINT_SEL(sel, "[DRV CAP] TxBF Capability : 0x%02x\n", pregistry_priv->beamform_cap);
+	RTW_PRINT_SEL(sel, "[DRV CAP] VHT MU Bfer : %s\n", (TEST_FLAG(pregistry_priv->beamform_cap, BIT2)) ? "V" : "X");
+	RTW_PRINT_SEL(sel, "[DRV CAP] VHT MU Bfee : %s\n", (TEST_FLAG(pregistry_priv->beamform_cap, BIT3)) ? "V" : "X");
+	RTW_PRINT_SEL(sel, "[DRV CAP] VHT SU Bfer : %s\n", (TEST_FLAG(pregistry_priv->beamform_cap, BIT0)) ? "V" : "X");
+	RTW_PRINT_SEL(sel, "[DRV CAP] VHT SU Bfee : %s\n", (TEST_FLAG(pregistry_priv->beamform_cap, BIT1)) ? "V" : "X");
+	RTW_PRINT_SEL(sel, "[DRV CAP] HT Bfer : %s\n", (TEST_FLAG(pregistry_priv->beamform_cap, BIT4))  ? "V" : "X");
+	RTW_PRINT_SEL(sel, "[DRV CAP] HT Bfee : %s\n", (TEST_FLAG(pregistry_priv->beamform_cap, BIT5)) ? "V" : "X");
+
+	RTW_PRINT_SEL(sel, "[DRV CAP] Tx Bfer rf_num : %d\n", pregistry_priv->beamformer_rf_num);
+	RTW_PRINT_SEL(sel, "[DRV CAP] Tx Bfee rf_num : %d\n", pregistry_priv->beamformee_rf_num);
+	#endif
+}
+
+int proc_get_stbc_cap(struct seq_file *m, void *v)
+{
+	struct net_device *dev = m->private;
+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
+	struct registry_priv	*pregpriv = &padapter->registrypriv;
+
+	if (pregpriv)
+		RTW_PRINT_SEL(m, "0x%02x\n", pregpriv->stbc_cap);
+
+	return 0;
+}
+
+ssize_t proc_set_stbc_cap(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
+{
+	struct net_device *dev = data;
+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
+	struct registry_priv	*pregpriv = &padapter->registrypriv;
+	char tmp[32];
+	u32 mode;
+
+	if (count < 1)
+		return -EFAULT;
+
+	if (count > sizeof(tmp)) {
+		rtw_warn_on(1);
+		return -EFAULT;
+	}
+
+	if (buffer && !copy_from_user(tmp, buffer, count)) {
+
+		int num = sscanf(tmp, "%d ", &mode);
+
+		if (num == 1 && pregpriv) {
+			pregpriv->stbc_cap = mode;
+			RTW_INFO("stbc_cap = 0x%02x\n", mode);
+		}
+	}
+
+	return count;
+}
+int proc_get_rx_stbc(struct seq_file *m, void *v)
+{
+	struct net_device *dev = m->private;
+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
+	struct registry_priv	*pregpriv = &padapter->registrypriv;
+
+	if (pregpriv)
+		RTW_PRINT_SEL(m, "%d\n", pregpriv->rx_stbc);
+
+	return 0;
+}
+
+ssize_t proc_set_rx_stbc(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
+{
+	struct net_device *dev = data;
+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
+	struct registry_priv	*pregpriv = &padapter->registrypriv;
+	char tmp[32];
+	u32 mode;
+
+	if (count < 1)
+		return -EFAULT;
+
+	if (count > sizeof(tmp)) {
+		rtw_warn_on(1);
+		return -EFAULT;
+	}
+
+	if (buffer && !copy_from_user(tmp, buffer, count)) {
+
+		int num = sscanf(tmp, "%d ", &mode);
+
+		if (num == 1 && pregpriv && (mode == 0 || mode == 1 || mode == 2 || mode == 3)) {
+			pregpriv->rx_stbc = mode;
+			printk("rx_stbc=%d\n", mode);
+		}
+	}
+
+	return count;
+
+}
+int proc_get_ldpc_cap(struct seq_file *m, void *v)
+{
+	struct net_device *dev = m->private;
+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
+	struct registry_priv	*pregpriv = &padapter->registrypriv;
+
+	if (pregpriv)
+		RTW_PRINT_SEL(m, "0x%02x\n", pregpriv->ldpc_cap);
+
+	return 0;
+}
+
+ssize_t proc_set_ldpc_cap(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
+{
+	struct net_device *dev = data;
+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
+	struct registry_priv	*pregpriv = &padapter->registrypriv;
+	char tmp[32];
+	u32 mode;
+
+	if (count < 1)
+		return -EFAULT;
+
+	if (count > sizeof(tmp)) {
+		rtw_warn_on(1);
+		return -EFAULT;
+	}
+
+	if (buffer && !copy_from_user(tmp, buffer, count)) {
+
+		int num = sscanf(tmp, "%d ", &mode);
+
+		if (num == 1 && pregpriv) {
+			pregpriv->ldpc_cap = mode;
+			RTW_INFO("ldpc_cap = 0x%02x\n", mode);
+		}
+	}
+
+	return count;
+}
+#ifdef CONFIG_BEAMFORMING
+int proc_get_txbf_cap(struct seq_file *m, void *v)
+{
+	struct net_device *dev = m->private;
+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
+	struct registry_priv	*pregpriv = &padapter->registrypriv;
+
+	if (pregpriv)
+		RTW_PRINT_SEL(m, "0x%02x\n", pregpriv->beamform_cap);
+
+	return 0;
+}
+
+ssize_t proc_set_txbf_cap(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
+{
+	struct net_device *dev = data;
+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
+	struct registry_priv	*pregpriv = &padapter->registrypriv;
+	char tmp[32];
+	u32 mode;
+
+	if (count < 1)
+		return -EFAULT;
+
+	if (count > sizeof(tmp)) {
+		rtw_warn_on(1);
+		return -EFAULT;
+	}
+
+	if (buffer && !copy_from_user(tmp, buffer, count)) {
+
+		int num = sscanf(tmp, "%d ", &mode);
+
+		if (num == 1 && pregpriv) {
+			pregpriv->beamform_cap = mode;
+			RTW_INFO("beamform_cap = 0x%02x\n", mode);
+		}
+	}
+
+	return count;
+}
+#endif
+#endif /* CONFIG_80211N_HT */
+
+/*int proc_get_rssi_disp(struct seq_file *m, void *v)
+{
+	struct net_device *dev = m->private;
+	return 0;
+}
+*/
+
+/*ssize_t proc_set_rssi_disp(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
+{
+	struct net_device *dev = data;
+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
+	char tmp[32];
+	u32 enable=0;
+
+	if (count < 1)
+	{
+		RTW_INFO("argument size is less than 1\n");
+		return -EFAULT;
+	}
+
+	if (count > sizeof(tmp)) {
+		rtw_warn_on(1);
+		return -EFAULT;
+	}
+
+	if (buffer && !copy_from_user(tmp, buffer, count)) {
+
+		int num = sscanf(tmp, "%x", &enable);
+
+		if (num !=  1) {
+			RTW_INFO("invalid set_rssi_disp parameter!\n");
+			return count;
+		}
+
+		if(enable)
+		{
+			RTW_INFO("Linked info Function Enable\n");
+			padapter->bLinkInfoDump = enable ;
+		}
+		else
+		{
+			RTW_INFO("Linked info Function Disable\n");
+			padapter->bLinkInfoDump = 0 ;
+		}
+
+	}
+
+	return count;
+
+}
+
+*/
+#ifdef CONFIG_AP_MODE
+
+int proc_get_all_sta_info(struct seq_file *m, void *v)
+{
+	struct net_device *dev = m->private;
+	_irqL irqL;
+	struct sta_info *psta;
+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
+	struct sta_priv *pstapriv = &padapter->stapriv;
+	int i;
+	_list	*plist, *phead;
+
+	RTW_MAP_DUMP_SEL(m, "sta_dz_bitmap=", pstapriv->sta_dz_bitmap, pstapriv->aid_bmp_len);
+	RTW_MAP_DUMP_SEL(m, "tim_bitmap=", pstapriv->tim_bitmap, pstapriv->aid_bmp_len);
+
+	_enter_critical_bh(&pstapriv->sta_hash_lock, &irqL);
+
+	for (i = 0; i < NUM_STA; i++) {
+		phead = &(pstapriv->sta_hash[i]);
+		plist = get_next(phead);
+
+		while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) {
+			psta = LIST_CONTAINOR(plist, struct sta_info, hash_list);
+
+			plist = get_next(plist);
+
+			/* if(extra_arg == psta->cmn.aid) */
+			{
+				RTW_PRINT_SEL(m, "==============================\n");
+				RTW_PRINT_SEL(m, "sta's macaddr:" MAC_FMT "\n", MAC_ARG(psta->cmn.mac_addr));
+				RTW_PRINT_SEL(m, "rtsen=%d, cts2slef=%d\n", psta->rtsen, psta->cts2self);
+				RTW_PRINT_SEL(m, "state=0x%x, aid=%d, macid=%d, raid=%d\n",
+					psta->state, psta->cmn.aid, psta->cmn.mac_id, psta->cmn.ra_info.rate_id);
+#ifdef CONFIG_80211N_HT
+				RTW_PRINT_SEL(m, "qos_en=%d, ht_en=%d, init_rate=%d\n", psta->qos_option, psta->htpriv.ht_option, psta->init_rate);
+				RTW_PRINT_SEL(m, "bwmode=%d, ch_offset=%d, sgi_20m=%d,sgi_40m=%d\n"
+					, psta->cmn.bw_mode, psta->htpriv.ch_offset, psta->htpriv.sgi_20m, psta->htpriv.sgi_40m);
+				RTW_PRINT_SEL(m, "ampdu_enable = %d\n", psta->htpriv.ampdu_enable);
+				RTW_PRINT_SEL(m, "tx_amsdu_enable = %d\n", psta->htpriv.tx_amsdu_enable);
+				RTW_PRINT_SEL(m, "agg_enable_bitmap=%x, candidate_tid_bitmap=%x\n", psta->htpriv.agg_enable_bitmap, psta->htpriv.candidate_tid_bitmap);
+#endif /* CONFIG_80211N_HT */
+#ifdef CONFIG_80211AC_VHT
+				RTW_PRINT_SEL(m, "vht_en=%d, vht_sgi_80m=%d\n", psta->vhtpriv.vht_option, psta->vhtpriv.sgi_80m);
+				RTW_PRINT_SEL(m, "vht_ldpc_cap=0x%x, vht_stbc_cap=0x%x, vht_beamform_cap=0x%x\n", psta->vhtpriv.ldpc_cap, psta->vhtpriv.stbc_cap, psta->vhtpriv.beamform_cap);
+				RTW_PRINT_SEL(m, "vht_mcs_map=0x%x, vht_highest_rate=0x%x, vht_ampdu_len=%d\n", *(u16 *)psta->vhtpriv.vht_mcs_map, psta->vhtpriv.vht_highest_rate, psta->vhtpriv.ampdu_len);
+#endif
+				RTW_PRINT_SEL(m, "sleepq_len=%d\n", psta->sleepq_len);
+				RTW_PRINT_SEL(m, "sta_xmitpriv.vo_q_qcnt=%d\n", psta->sta_xmitpriv.vo_q.qcnt);
+				RTW_PRINT_SEL(m, "sta_xmitpriv.vi_q_qcnt=%d\n", psta->sta_xmitpriv.vi_q.qcnt);
+				RTW_PRINT_SEL(m, "sta_xmitpriv.be_q_qcnt=%d\n", psta->sta_xmitpriv.be_q.qcnt);
+				RTW_PRINT_SEL(m, "sta_xmitpriv.bk_q_qcnt=%d\n", psta->sta_xmitpriv.bk_q.qcnt);
+
+				RTW_PRINT_SEL(m, "capability=0x%x\n", psta->capability);
+				RTW_PRINT_SEL(m, "flags=0x%x\n", psta->flags);
+				RTW_PRINT_SEL(m, "wpa_psk=0x%x\n", psta->wpa_psk);
+				RTW_PRINT_SEL(m, "wpa2_group_cipher=0x%x\n", psta->wpa2_group_cipher);
+				RTW_PRINT_SEL(m, "wpa2_pairwise_cipher=0x%x\n", psta->wpa2_pairwise_cipher);
+				RTW_PRINT_SEL(m, "qos_info=0x%x\n", psta->qos_info);
+				RTW_PRINT_SEL(m, "dot118021XPrivacy=0x%x\n", psta->dot118021XPrivacy);
+
+				sta_rx_reorder_ctl_dump(m, psta);
+
+#ifdef CONFIG_TDLS
+				RTW_PRINT_SEL(m, "tdls_sta_state=0x%08x\n", psta->tdls_sta_state);
+				RTW_PRINT_SEL(m, "PeerKey_Lifetime=%d\n", psta->TDLS_PeerKey_Lifetime);
+#endif /* CONFIG_TDLS */
+				RTW_PRINT_SEL(m, "rx_data_uc_pkts=%llu\n", sta_rx_data_uc_pkts(psta));
+				RTW_PRINT_SEL(m, "rx_data_mc_pkts=%llu\n", psta->sta_stats.rx_data_mc_pkts);
+				RTW_PRINT_SEL(m, "rx_data_bc_pkts=%llu\n", psta->sta_stats.rx_data_bc_pkts);
+				RTW_PRINT_SEL(m, "rx_uc_bytes=%llu\n", sta_rx_uc_bytes(psta));
+				RTW_PRINT_SEL(m, "rx_mc_bytes=%llu\n", psta->sta_stats.rx_mc_bytes);
+				RTW_PRINT_SEL(m, "rx_bc_bytes=%llu\n", psta->sta_stats.rx_bc_bytes);
+				RTW_PRINT_SEL(m, "rx_avg_tp =%d (Bps)\n", psta->cmn.rx_moving_average_tp);
+
+				RTW_PRINT_SEL(m, "tx_data_pkts=%llu\n", psta->sta_stats.tx_pkts);
+				RTW_PRINT_SEL(m, "tx_bytes=%llu\n", psta->sta_stats.tx_bytes);
+				RTW_PRINT_SEL(m, "tx_avg_tp =%d (MBps)\n", psta->cmn.tx_moving_average_tp);
+#ifdef CONFIG_RTW_80211K
+				RTW_PRINT_SEL(m, "rm_en_cap="RM_CAP_FMT"\n", RM_CAP_ARG(psta->rm_en_cap));
+#endif
+				dump_st_ctl(m, &psta->st_ctl);
+
+				if (STA_OP_WFD_MODE(psta))
+					RTW_PRINT_SEL(m, "op_wfd_mode:0x%02x\n", STA_OP_WFD_MODE(psta));
+
+				RTW_PRINT_SEL(m, "==============================\n");
+			}
+
+		}
+
+	}
+
+	_exit_critical_bh(&pstapriv->sta_hash_lock, &irqL);
+
+	return 0;
+}
+
+#endif
+
+#ifdef CONFIG_PREALLOC_RX_SKB_BUFFER
+int proc_get_rtkm_info(struct seq_file *m, void *v)
+{
+	struct net_device *dev = m->private;
+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
+	struct recv_priv	*precvpriv = &padapter->recvpriv;
+	struct recv_buf *precvbuf;
+
+	precvbuf = (struct recv_buf *)precvpriv->precv_buf;
+
+	RTW_PRINT_SEL(m, "============[RTKM Info]============\n");
+	RTW_PRINT_SEL(m, "MAX_RTKM_NR_PREALLOC_RECV_SKB: %d\n", rtw_rtkm_get_nr_recv_skb());
+	RTW_PRINT_SEL(m, "MAX_RTKM_RECVBUF_SZ: %d\n", rtw_rtkm_get_buff_size());
+
+	RTW_PRINT_SEL(m, "============[Driver Info]============\n");
+	RTW_PRINT_SEL(m, "NR_PREALLOC_RECV_SKB: %d\n", NR_PREALLOC_RECV_SKB);
+	RTW_PRINT_SEL(m, "MAX_RECVBUF_SZ: %d\n", precvbuf->alloc_sz);
+
+	return 0;
+}
+#endif /* CONFIG_PREALLOC_RX_SKB_BUFFER */
+
+#ifdef DBG_MEMORY_LEAK
+#include <asm/atomic.h>
+extern atomic_t _malloc_cnt;;
+extern atomic_t _malloc_size;;
+
+int proc_get_malloc_cnt(struct seq_file *m, void *v)
+{
+	RTW_PRINT_SEL(m, "_malloc_cnt=%d\n", atomic_read(&_malloc_cnt));
+	RTW_PRINT_SEL(m, "_malloc_size=%d\n", atomic_read(&_malloc_size));
+
+	return 0;
+}
+#endif /* DBG_MEMORY_LEAK */
+
+#ifdef CONFIG_FIND_BEST_CHANNEL
+int proc_get_best_channel(struct seq_file *m, void *v)
+{
+	struct net_device *dev = m->private;
+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
+	struct rf_ctl_t *rfctl = adapter_to_rfctl(padapter);
+	u32 i, best_channel_24G = 1, best_channel_5G = 36, index_24G = 0, index_5G = 0;
+
+	for (i = 0; i < rfctl->max_chan_nums && rfctl->channel_set[i].ChannelNum != 0; i++) {
+		if (rfctl->channel_set[i].ChannelNum == 1)
+			index_24G = i;
+		if (rfctl->channel_set[i].ChannelNum == 36)
+			index_5G = i;
+	}
+
+	for (i = 0; i < rfctl->max_chan_nums && rfctl->channel_set[i].ChannelNum != 0; i++) {
+		/* 2.4G */
+		if (rfctl->channel_set[i].ChannelNum == 6) {
+			if (rfctl->channel_set[i].rx_count < rfctl->channel_set[index_24G].rx_count) {
+				index_24G = i;
+				best_channel_24G = rfctl->channel_set[i].ChannelNum;
+			}
+		}
+
+		/* 5G */
+		if (rfctl->channel_set[i].ChannelNum >= 36
+		    && rfctl->channel_set[i].ChannelNum < 140) {
+			/* Find primary channel */
+			if (((rfctl->channel_set[i].ChannelNum - 36) % 8 == 0)
+			    && (rfctl->channel_set[i].rx_count < rfctl->channel_set[index_5G].rx_count)) {
+				index_5G = i;
+				best_channel_5G = rfctl->channel_set[i].ChannelNum;
+			}
+		}
+
+		if (rfctl->channel_set[i].ChannelNum >= 149
+		    && rfctl->channel_set[i].ChannelNum < 165) {
+			/* find primary channel */
+			if (((rfctl->channel_set[i].ChannelNum - 149) % 8 == 0)
+			    && (rfctl->channel_set[i].rx_count < rfctl->channel_set[index_5G].rx_count)) {
+				index_5G = i;
+				best_channel_5G = rfctl->channel_set[i].ChannelNum;
+			}
+		}
+#if 1 /* debug */
+		RTW_PRINT_SEL(m, "The rx cnt of channel %3d = %d\n",
+			rfctl->channel_set[i].ChannelNum, rfctl->channel_set[i].rx_count);
+#endif
+	}
+
+	RTW_PRINT_SEL(m, "best_channel_5G = %d\n", best_channel_5G);
+	RTW_PRINT_SEL(m, "best_channel_24G = %d\n", best_channel_24G);
+
+	return 0;
+}
+
+ssize_t proc_set_best_channel(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
+{
+	struct net_device *dev = data;
+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
+	struct rf_ctl_t *rfctl = adapter_to_rfctl(padapter);
+	char tmp[32];
+
+	if (count < 1)
+		return -EFAULT;
+
+	if (count > sizeof(tmp)) {
+		rtw_warn_on(1);
+		return -EFAULT;
+	}
+
+	if (buffer && !copy_from_user(tmp, buffer, count)) {
+		int i;
+		for (i = 0; i < rfctl->max_chan_nums && rfctl->channel_set[i].ChannelNum != 0; i++)
+			rfctl->channel_set[i].rx_count = 0;
+
+		RTW_INFO("set %s\n", "Clean Best Channel Count");
+	}
+
+	return count;
+}
+#endif /* CONFIG_FIND_BEST_CHANNEL */
+
+#ifdef CONFIG_BT_COEXIST
+int proc_get_btcoex_dbg(struct seq_file *m, void *v)
+{
+	struct net_device *dev = m->private;
+	PADAPTER padapter;
+	char buf[512] = {0};
+	padapter = (PADAPTER)rtw_netdev_priv(dev);
+
+	rtw_btcoex_GetDBG(padapter, buf, 512);
+
+	_RTW_PRINT_SEL(m, "%s", buf);
+
+	return 0;
+}
+
+ssize_t proc_set_btcoex_dbg(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
+{
+	struct net_device *dev = data;
+	PADAPTER padapter;
+	u8 tmp[80] = {0};
+	u32 module[2] = {0};
+	u32 num;
+
+	padapter = (PADAPTER)rtw_netdev_priv(dev);
+
+	/*	RTW_INFO("+" FUNC_ADPT_FMT "\n", FUNC_ADPT_ARG(padapter)); */
+
+	if (NULL == buffer) {
+		RTW_INFO(FUNC_ADPT_FMT ": input buffer is NULL!\n",
+			 FUNC_ADPT_ARG(padapter));
+
+		return -EFAULT;
+	}
+
+	if (count < 1) {
+		RTW_INFO(FUNC_ADPT_FMT ": input length is 0!\n",
+			 FUNC_ADPT_ARG(padapter));
+
+		return -EFAULT;
+	}
+
+	num = count;
+	if (num > (sizeof(tmp) - 1))
+		num = (sizeof(tmp) - 1);
+
+	if (copy_from_user(tmp, buffer, num)) {
+		RTW_INFO(FUNC_ADPT_FMT ": copy buffer from user space FAIL!\n",
+			 FUNC_ADPT_ARG(padapter));
+
+		return -EFAULT;
+	}
+
+	num = sscanf(tmp, "%x %x", module, module + 1);
+	if (1 == num) {
+		if (0 == module[0])
+			_rtw_memset(module, 0, sizeof(module));
+		else
+			_rtw_memset(module, 0xFF, sizeof(module));
+	} else if (2 != num) {
+		RTW_INFO(FUNC_ADPT_FMT ": input(\"%s\") format incorrect!\n",
+			 FUNC_ADPT_ARG(padapter), tmp);
+
+		if (0 == num)
+			return -EFAULT;
+	}
+
+	RTW_INFO(FUNC_ADPT_FMT ": input 0x%08X 0x%08X\n",
+		 FUNC_ADPT_ARG(padapter), module[0], module[1]);
+	rtw_btcoex_SetDBG(padapter, module);
+
+	return count;
+}
+
+int proc_get_btcoex_info(struct seq_file *m, void *v)
+{
+	struct net_device *dev = m->private;
+	PADAPTER padapter;
+	const u32 bufsize = 30 * 100;
+	u8 *pbuf = NULL;
+
+	padapter = (PADAPTER)rtw_netdev_priv(dev);
+
+	pbuf = rtw_zmalloc(bufsize);
+	if (NULL == pbuf)
+		return -ENOMEM;
+
+	rtw_btcoex_DisplayBtCoexInfo(padapter, pbuf, bufsize);
+
+	_RTW_PRINT_SEL(m, "%s\n", pbuf);
+
+	rtw_mfree(pbuf, bufsize);
+
+	return 0;
+}
+
+#ifdef CONFIG_RF4CE_COEXIST
+int proc_get_rf4ce_state(struct seq_file *m, void *v)
+{
+	struct net_device *dev = m->private;
+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
+	u8 state = 0, voice = 0;
+
+	state = rtw_btcoex_GetRf4ceLinkState(adapter);
+
+	RTW_PRINT_SEL(m, "RF4CE %s\n", state?"Connected":"Disconnect");
+
+	return 0;
+}
+
+/* This interface is designed for user space application to inform RF4CE state
+ * Initial define for DHC 1295 E387 project
+ *
+ * echo state voice > rf4ce_state
+ * state
+ *	0: RF4CE disconnected
+ *	1: RF4CE connected
+ */
+ssize_t proc_set_rf4ce_state(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
+{
+	struct net_device *dev = data;
+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
+	char tmp[32];
+	u8 state;
+
+	if (count < 1)
+		return -EFAULT;
+
+	if (count > sizeof(tmp)) {
+		rtw_warn_on(1);
+		return -EFAULT;
+	}
+
+	if (buffer && !copy_from_user(tmp, buffer, count)) {
+
+		int num = sscanf(tmp, "%hhx", &state);
+
+		if (num >= 1)
+			rtw_btcoex_SetRf4ceLinkState(adapter, state);
+	}
+
+	return count;
+}
+#endif /* CONFIG_RF4CE_COEXIST */
+#endif /* CONFIG_BT_COEXIST */
+
+#if defined(DBG_CONFIG_ERROR_DETECT)
+int proc_get_sreset(struct seq_file *m, void *v)
+{
+	struct net_device *dev = m->private;
+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
+	struct dvobj_priv *psdpriv = padapter->dvobj;
+	struct debug_priv *pdbgpriv = &psdpriv->drv_dbg;
+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(padapter);
+	struct sreset_priv *psrtpriv = &pHalData->srestpriv;
+
+	if (psrtpriv->dbg_sreset_ctrl == _TRUE) {
+		RTW_PRINT_SEL(m, "self_dect_tx_cnt:%llu\n", psrtpriv->self_dect_tx_cnt);
+		RTW_PRINT_SEL(m, "self_dect_rx_cnt:%llu\n", psrtpriv->self_dect_rx_cnt);
+		RTW_PRINT_SEL(m, "self_dect_fw_cnt:%llu\n", psrtpriv->self_dect_fw_cnt);
+		RTW_PRINT_SEL(m, "tx_dma_status_cnt:%llu\n", psrtpriv->tx_dma_status_cnt);
+		RTW_PRINT_SEL(m, "rx_dma_status_cnt:%llu\n", psrtpriv->rx_dma_status_cnt);
+		RTW_PRINT_SEL(m, "self_dect_case:%d\n", psrtpriv->self_dect_case);
+		RTW_PRINT_SEL(m, "dbg_sreset_cnt:%d\n", pdbgpriv->dbg_sreset_cnt);
+	}
+	return 0;
+}
+
+ssize_t proc_set_sreset(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
+{
+	struct net_device *dev = data;
+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(padapter);
+	struct sreset_priv *psrtpriv = &pHalData->srestpriv;
+	char tmp[32];
+	s32 trigger_point;
+
+	if (count < 1)
+		return -EFAULT;
+
+	if (count > sizeof(tmp)) {
+		rtw_warn_on(1);
+		return -EFAULT;
+	}
+
+	if (buffer && !copy_from_user(tmp, buffer, count)) {
+
+		int num = sscanf(tmp, "%d", &trigger_point);
+
+		if (num < 1)
+			return count;
+
+		if (trigger_point == SRESET_TGP_NULL)
+			rtw_hal_sreset_reset(padapter);
+		else if (trigger_point == SRESET_TGP_INFO)
+			psrtpriv->dbg_sreset_ctrl = _TRUE;
+		else
+			sreset_set_trigger_point(padapter, trigger_point);
+	}
+
+	return count;
+
+}
+#endif /* DBG_CONFIG_ERROR_DETECT */
+
+#ifdef CONFIG_PCI_HCI
+
+ssize_t proc_set_pci_bridge_conf_space(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
+{
+	struct net_device *dev = data;
+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
+	struct dvobj_priv       *pdvobjpriv = adapter_to_dvobj(padapter);
+	struct pci_dev  *pdev = pdvobjpriv->ppcidev;
+	struct pci_dev  *bridge_pdev = pdev->bus->self;
+
+	char tmp[32] = { 0 };
+	int num;
+
+	u32 reg = 0, value = 0;
+
+	if (count < 1)
+		return -EFAULT;
+
+	if (count > sizeof(tmp)) {
+		rtw_warn_on(1);
+		return -EFAULT;
+	}
+
+	if (buffer && !copy_from_user(tmp, buffer, count)) {
+
+		num = sscanf(tmp, "%x %x", &reg, &value);
+		if (num != 2) {
+			RTW_INFO("invalid parameter!\n");
+			return count;
+		}
+
+		if (reg >= 0x1000) {
+			RTW_INFO("invalid register!\n");
+			return count;
+		}
+
+		if (value > 0xFF) {
+			RTW_INFO("invalid value! Only one byte\n");
+			return count;
+		}
+
+		RTW_INFO(FUNC_ADPT_FMT ": register 0x%x value 0x%x\n",
+			FUNC_ADPT_ARG(padapter), reg, value);
+
+		pci_write_config_byte(bridge_pdev, reg, value);
+	}
+	return count;
+}
+
+
+int proc_get_pci_bridge_conf_space(struct seq_file *m, void *v)
+{
+	struct net_device *dev = m->private;
+	_adapter *padapter = (_adapter *) rtw_netdev_priv(dev);
+	struct dvobj_priv       *pdvobjpriv = adapter_to_dvobj(padapter);
+	struct pci_dev  *pdev = pdvobjpriv->ppcidev;
+	struct pci_dev  *bridge_pdev = pdev->bus->self;
+
+	u32 tmp[4] = { 0 };
+	u32 i, j;
+
+	RTW_PRINT_SEL(m, "\n*****  PCI Host Device Configuration Space*****\n\n");
+
+	for (i = 0; i < 0x1000; i += 0x10) {
+		for (j = 0 ; j < 4 ; j++)
+			pci_read_config_dword(bridge_pdev, i + j * 4, tmp+j);
+
+		RTW_PRINT_SEL(m, "%03x: %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x\n",
+			i, tmp[0] & 0xFF, (tmp[0] >> 8) & 0xFF, (tmp[0] >> 16) & 0xFF, (tmp[0] >> 24) & 0xFF,
+			tmp[1] & 0xFF, (tmp[1] >> 8) & 0xFF, (tmp[1] >> 16) & 0xFF, (tmp[1] >> 24) & 0xFF,
+			tmp[2] & 0xFF, (tmp[2] >> 8) & 0xFF, (tmp[2] >> 16) & 0xFF, (tmp[2] >> 24) & 0xFF,
+			tmp[3] & 0xFF, (tmp[3] >> 8) & 0xFF, (tmp[3] >> 16) & 0xFF, (tmp[3] >> 24) & 0xFF);
+	}
+	return 0;
+}
+
+
+ssize_t proc_set_pci_conf_space(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
+{
+	struct net_device *dev = data;
+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
+	struct dvobj_priv       *pdvobjpriv = adapter_to_dvobj(padapter);
+	struct pci_dev  *pdev = pdvobjpriv->ppcidev;
+
+	char tmp[32] = { 0 };
+	int num;
+
+	u32 reg = 0, value = 0;
+
+	if (count < 1)
+		return -EFAULT;
+
+	if (count > sizeof(tmp)) {
+		rtw_warn_on(1);
+		return -EFAULT;
+	}
+
+	if (buffer && !copy_from_user(tmp, buffer, count)) {
+
+		num = sscanf(tmp, "%x %x", &reg, &value);
+
+		if (num != 2) {
+			RTW_INFO("invalid parameter!\n");
+			return count;
+		}
+
+
+		if (reg >= 0x1000) {
+			RTW_INFO("invalid register!\n");
+			return count;
+		}
+
+		if (value > 0xFF) {
+			RTW_INFO("invalid value! Only one byte\n");
+			return count;
+		}
+
+		RTW_INFO(FUNC_ADPT_FMT ": register 0x%x value 0x%x\n",
+			FUNC_ADPT_ARG(padapter), reg, value);
+
+		pci_write_config_byte(pdev, reg, value);
+
+
+	}
+	return count;
+}
+
+
+int proc_get_pci_conf_space(struct seq_file *m, void *v)
+{
+	struct net_device *dev = m->private;
+	_adapter *padapter = (_adapter *) rtw_netdev_priv(dev);
+	struct dvobj_priv       *pdvobjpriv = adapter_to_dvobj(padapter);
+	struct pci_dev  *pdev = pdvobjpriv->ppcidev;
+	struct pci_dev  *bridge_pdev = pdev->bus->self;
+
+	u32 tmp[4] = { 0 };
+	u32 i, j;
+
+	RTW_PRINT_SEL(m, "\n*****  PCI Device Configuration Space *****\n\n");
+
+	for (i = 0; i < 0x1000; i += 0x10) {
+		for (j = 0 ; j < 4 ; j++)
+			pci_read_config_dword(pdev, i + j * 4, tmp+j);
+
+		RTW_PRINT_SEL(m, "%03x: %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x\n",
+			i, tmp[0] & 0xFF, (tmp[0] >> 8) & 0xFF, (tmp[0] >> 16) & 0xFF, (tmp[0] >> 24) & 0xFF,
+			tmp[1] & 0xFF, (tmp[1] >> 8) & 0xFF, (tmp[1] >> 16) & 0xFF, (tmp[1] >> 24) & 0xFF,
+			tmp[2] & 0xFF, (tmp[2] >> 8) & 0xFF, (tmp[2] >> 16) & 0xFF, (tmp[2] >> 24) & 0xFF,
+			tmp[3] & 0xFF, (tmp[3] >> 8) & 0xFF, (tmp[3] >> 16) & 0xFF, (tmp[3] >> 24) & 0xFF);
+	}
+
+	return 0;
+}
+
+
+int proc_get_pci_aspm(struct seq_file *m, void *v)
+{
+	struct net_device *dev = m->private;
+	_adapter *padapter = (_adapter *) rtw_netdev_priv(dev);
+	struct dvobj_priv	*pdvobjpriv = adapter_to_dvobj(padapter);
+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(padapter);
+	struct pci_priv	*pcipriv = &(pdvobjpriv->pcipriv);
+	u8 tmp8 = 0;
+	u16 tmp16 = 0;
+	u32 tmp32 = 0;
+	u8 l1_idle = 0;
+
+
+	RTW_PRINT_SEL(m, "***** ASPM Capability *****\n");
+
+	pci_read_config_dword(pdvobjpriv->ppcidev, pcipriv->pciehdr_offset + PCI_EXP_LNKCAP, &tmp32);
+
+	RTW_PRINT_SEL(m, "CLK REQ:	%s\n", (tmp32&PCI_EXP_LNKCAP_CLKPM) ? "Enable" : "Disable");
+	RTW_PRINT_SEL(m, "ASPM L0s:	%s\n", (tmp32&BIT10) ? "Enable" : "Disable");
+	RTW_PRINT_SEL(m, "ASPM L1:	%s\n", (tmp32&BIT11) ? "Enable" : "Disable");
+
+	tmp8 = rtw_hal_pci_l1off_capability(padapter);
+	RTW_PRINT_SEL(m, "ASPM L1OFF:	%s\n", tmp8 ? "Enable" : "Disable");
+
+	RTW_PRINT_SEL(m, "***** ASPM CTRL Reg *****\n");
+
+	pci_read_config_word(pdvobjpriv->ppcidev, pcipriv->pciehdr_offset + PCI_EXP_LNKCTL, &tmp16);
+
+	RTW_PRINT_SEL(m, "CLK REQ:	%s\n", (tmp16&PCI_EXP_LNKCTL_CLKREQ_EN) ? "Enable" : "Disable");
+	RTW_PRINT_SEL(m, "ASPM L0s:	%s\n", (tmp16&BIT0) ? "Enable" : "Disable");
+	RTW_PRINT_SEL(m, "ASPM L1:	%s\n", (tmp16&BIT1) ? "Enable" : "Disable");
+
+	tmp8 = rtw_hal_pci_l1off_nic_support(padapter);
+	RTW_PRINT_SEL(m, "ASPM L1OFF:	%s\n", tmp8 ? "Enable" : "Disable");
+
+	RTW_PRINT_SEL(m, "***** ASPM Backdoor *****\n");
+
+	tmp8 = rtw_hal_pci_dbi_read(padapter, 0x719);
+	RTW_PRINT_SEL(m, "CLK REQ:	%s\n", (tmp8 & BIT4) ? "Enable" : "Disable");
+
+	tmp8 = rtw_hal_pci_dbi_read(padapter, 0x70f);
+	l1_idle = tmp8 & 0x38;
+	RTW_PRINT_SEL(m, "ASPM L0s:	%s\n", (tmp8&BIT7) ? "Enable" : "Disable");
+
+	tmp8 = rtw_hal_pci_dbi_read(padapter, 0x719);
+	RTW_PRINT_SEL(m, "ASPM L1:	%s\n", (tmp8 & BIT3) ? "Enable" : "Disable");
+
+	tmp8 = rtw_hal_pci_dbi_read(padapter, 0x718);
+	RTW_PRINT_SEL(m, "ASPM L1OFF:	%s\n", (tmp8 & BIT5) ? "Enable" : "Disable");
+
+	RTW_PRINT_SEL(m, "********* MISC **********\n");
+	RTW_PRINT_SEL(m, "ASPM L1 Idel Time: 0x%x\n", l1_idle>>3);
+	RTW_PRINT_SEL(m, "*************************\n");
+
+	return 0;
+}
+
+int proc_get_rx_ring(struct seq_file *m, void *v)
+{
+	_irqL irqL;
+	struct net_device *dev = m->private;
+	_adapter *padapter = (_adapter *) rtw_netdev_priv(dev);
+	struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(padapter);
+	struct recv_priv *precvpriv = &padapter->recvpriv;
+	struct rtw_rx_ring *rx_ring = &precvpriv->rx_ring[RX_MPDU_QUEUE];
+	int i, j;
+
+	RTW_PRINT_SEL(m, "rx ring (%p)\n", rx_ring);
+	RTW_PRINT_SEL(m, "  dma: 0x%08x\n", (int) rx_ring->dma);
+	RTW_PRINT_SEL(m, "  idx: %d\n", rx_ring->idx);
+
+	_enter_critical(&pdvobjpriv->irq_th_lock, &irqL);
+	for (i = 0; i < precvpriv->rxringcount; i++) {
+#ifdef CONFIG_TRX_BD_ARCH
+		struct rx_buf_desc *entry = &rx_ring->buf_desc[i];
+#else
+		struct recv_stat *entry = &rx_ring->desc[i];
+#endif
+		struct sk_buff *skb = rx_ring->rx_buf[i];
+
+		RTW_PRINT_SEL(m, "  desc[%03d]: %p, rx_buf[%03d]: 0x%08x\n",
+			i, entry, i, cpu_to_le32(*((dma_addr_t *)skb->cb)));
+
+		for (j = 0; j < sizeof(*entry) / 4; j++) {
+			if ((j % 4) == 0)
+				RTW_PRINT_SEL(m, "  0x%03x", j);
+
+			RTW_PRINT_SEL(m, " 0x%08x ", ((int *) entry)[j]);
+
+			if ((j % 4) == 3)
+				RTW_PRINT_SEL(m, "\n");
+		}
+	}
+	_exit_critical(&pdvobjpriv->irq_th_lock, &irqL);
+
+	return 0;
+}
+
+int proc_get_tx_ring(struct seq_file *m, void *v)
+{
+	_irqL irqL;
+	struct net_device *dev = m->private;
+	_adapter *padapter = (_adapter *) rtw_netdev_priv(dev);
+	struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(padapter);
+	struct xmit_priv *pxmitpriv = &padapter->xmitpriv;
+	int i, j, k;
+
+	_enter_critical(&pdvobjpriv->irq_th_lock, &irqL);
+	for (i = 0; i < PCI_MAX_TX_QUEUE_COUNT; i++) {
+		struct rtw_tx_ring *tx_ring = &pxmitpriv->tx_ring[i];
+
+		RTW_PRINT_SEL(m, "tx ring[%d] (%p)\n", i, tx_ring);
+		RTW_PRINT_SEL(m, "  dma: 0x%08x\n", (int) tx_ring->dma);
+		RTW_PRINT_SEL(m, "  idx: %d\n", tx_ring->idx);
+		RTW_PRINT_SEL(m, "  entries: %d\n", tx_ring->entries);
+		/*		RTW_PRINT_SEL(m, "  queue: %d\n", tx_ring->queue); */
+		RTW_PRINT_SEL(m, "  qlen: %d\n", tx_ring->qlen);
+
+		for (j = 0; j < pxmitpriv->txringcount[i]; j++) {
+#ifdef CONFIG_TRX_BD_ARCH
+			struct tx_buf_desc *entry = &tx_ring->buf_desc[j];
+			RTW_PRINT_SEL(m, "  buf_desc[%03d]: %p\n", j, entry);
+#else
+			struct tx_desc *entry = &tx_ring->desc[j];
+			RTW_PRINT_SEL(m, "  desc[%03d]: %p\n", j, entry);
+#endif
+
+			for (k = 0; k < sizeof(*entry) / 4; k++) {
+				if ((k % 4) == 0)
+					RTW_PRINT_SEL(m, "  0x%03x", k);
+
+				RTW_PRINT_SEL(m, " 0x%08x ", ((int *) entry)[k]);
+
+				if ((k % 4) == 3)
+					RTW_PRINT_SEL(m, "\n");
+			}
+		}
+	}
+	_exit_critical(&pdvobjpriv->irq_th_lock, &irqL);
+
+	return 0;
+}
+
+#ifdef DBG_TXBD_DESC_DUMP
+int proc_get_tx_ring_ext(struct seq_file *m, void *v)
+{
+	_irqL irqL;
+	struct net_device *dev = m->private;
+	_adapter *padapter = (_adapter *) rtw_netdev_priv(dev);
+	struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(padapter);
+	struct xmit_priv *pxmitpriv = &padapter->xmitpriv;
+	struct rtw_tx_desc_backup *pbuf;
+	int i, j, k, idx;
+
+	RTW_PRINT_SEL(m, "<<<< tx ring ext dump settings >>>>\n");
+	RTW_PRINT_SEL(m, " - backup frame num: %d\n", TX_BAK_FRMAE_CNT);
+	RTW_PRINT_SEL(m, " - backup max. desc size: %d bytes\n", TX_BAK_DESC_LEN);
+	RTW_PRINT_SEL(m, " - backup data size: %d bytes\n\n", TX_BAK_DATA_LEN);
+
+	if (!pxmitpriv->dump_txbd_desc) {
+		RTW_PRINT_SEL(m, "Dump function is disabled.\n");
+		return 0;
+	}
+
+	_enter_critical(&pdvobjpriv->irq_th_lock, &irqL);
+	for (i = 0; i < HW_QUEUE_ENTRY; i++) {
+		struct rtw_tx_ring *tx_ring = &pxmitpriv->tx_ring[i];
+
+		idx = rtw_get_tx_desc_backup(padapter, i, &pbuf);
+
+		RTW_PRINT_SEL(m, "Tx ring[%d]", i);
+		switch (i) {
+		case 0:
+			RTW_PRINT_SEL(m, " (VO)\n");
+			break;
+		case 1:
+			RTW_PRINT_SEL(m, " (VI)\n");
+			break;
+		case 2:
+			RTW_PRINT_SEL(m, " (BE)\n");
+			break;
+		case 3:
+			RTW_PRINT_SEL(m, " (BK)\n");
+			break;
+		case 4:
+			RTW_PRINT_SEL(m, " (BCN)\n");
+			break;
+		case 5:
+			RTW_PRINT_SEL(m, " (MGT)\n");
+			break;
+		case 6:
+			RTW_PRINT_SEL(m, " (HIGH)\n");
+			break;
+		case 7:
+			RTW_PRINT_SEL(m, " (TXCMD)\n");
+			break;
+		default:
+			RTW_PRINT_SEL(m, " (?)\n");
+			break;
+		}
+
+		RTW_PRINT_SEL(m, "  Entries: %d\n", TX_BAK_FRMAE_CNT);
+		RTW_PRINT_SEL(m, "  Last idx: %d\n", idx);
+
+		for (j = 0; j < TX_BAK_FRMAE_CNT; j++) {
+			RTW_PRINT_SEL(m, "  desc[%03d]:\n", j);
+
+			for (k = 0; k < (pbuf->tx_desc_size) / 4; k++) {
+				if ((k % 4) == 0)
+					RTW_PRINT_SEL(m, "  0x%03x", k);
+
+				RTW_PRINT_SEL(m, " 0x%08x ", ((int *)pbuf->tx_bak_desc)[k]);
+
+				if ((k % 4) == 3)
+					RTW_PRINT_SEL(m, "\n");
+			}
+
+#if 1 /* data dump */
+			if (pbuf->tx_desc_size) {
+				RTW_PRINT_SEL(m, "  data[%03d]:\n", j);
+
+				for (k = 0; k < (TX_BAK_DATA_LEN) / 4; k++) {
+					if ((k % 4) == 0)
+						RTW_PRINT_SEL(m, "  0x%03x", k);
+
+					RTW_PRINT_SEL(m, " 0x%08x ", ((int *)pbuf->tx_bak_data_hdr)[k]);
+
+					if ((k % 4) == 3)
+						RTW_PRINT_SEL(m, "\n");
+				}
+				RTW_PRINT_SEL(m, "\n");
+			}
+#endif
+
+			RTW_PRINT_SEL(m, "  R/W pointer: %d/%d\n", pbuf->tx_bak_rp, pbuf->tx_bak_wp);
+
+			pbuf = pbuf + 1;
+		}
+		RTW_PRINT_SEL(m, "\n");
+	}
+	_exit_critical(&pdvobjpriv->irq_th_lock, &irqL);
+
+	return 0;
+}
+
+ssize_t proc_set_tx_ring_ext(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
+{
+	_irqL irqL;
+	struct net_device *dev = data;
+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
+	struct xmit_priv *pxmitpriv = &padapter->xmitpriv;
+	struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(padapter);
+	char tmp[32];
+	u32 reset = 0;
+	u32 dump = 0;
+
+	if (count < 1)
+		return -EFAULT;
+
+	if (count > sizeof(tmp)) {
+		rtw_warn_on(1);
+		return -EFAULT;
+	}
+
+	if (buffer && !copy_from_user(tmp, buffer, count)) {
+
+		int num = sscanf(tmp, "%u %u", &dump, &reset);
+
+		if (num != 2) {
+			RTW_INFO("invalid parameter!\n");
+			return count;
+		}
+
+		_enter_critical(&pdvobjpriv->irq_th_lock, &irqL);
+		pxmitpriv->dump_txbd_desc = (BOOLEAN) dump;
+
+		if (reset == 1)
+			rtw_tx_desc_backup_reset();
+
+		_exit_critical(&pdvobjpriv->irq_th_lock, &irqL);
+
+	}
+
+	return count;
+}
+
+#endif
+
+#endif
+
+#ifdef CONFIG_WOWLAN
+int proc_get_pattern_info(struct seq_file *m, void *v)
+{
+	struct net_device *dev = m->private;
+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
+	struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter);
+	struct registry_priv *pregistrypriv = &padapter->registrypriv;
+	u8 pattern_num = 0, val8;
+	char str_1[128];
+	char *p_str;
+	int i = 0 , j = 0, k = 0;
+	int len = 0, max_len = 0, total = 0;
+
+	p_str = str_1;
+	max_len = sizeof(str_1);
+
+	total = pwrpriv->wowlan_pattern_idx;
+
+	rtw_set_default_pattern(padapter);
+
+	/*show pattern*/
+	RTW_PRINT_SEL(m, "\n======[Pattern Info.]======\n");
+	RTW_PRINT_SEL(m, "pattern number: %d\n", total);
+	RTW_PRINT_SEL(m, "support default patterns: %c\n",
+		      (pwrpriv->default_patterns_en) ? 'Y' : 'N');
+
+	for (k = 0; k < total ; k++) {
+		RTW_PRINT_SEL(m, "\npattern idx: %d\n", k);
+		RTW_PRINT_SEL(m, "pattern content:\n");
+
+		p_str = str_1;
+		max_len = sizeof(str_1);
+		for (i = 0 ; i < MAX_WKFM_PATTERN_SIZE / 8 ; i++) {
+			_rtw_memset(p_str, 0, max_len);
+			len = 0;
+			for (j = 0 ; j < 8 ; j++) {
+				val8 = pwrpriv->patterns[k].content[i * 8 + j];
+				len += snprintf(p_str + len, max_len - len,
+						"%02x ", val8);
+			}
+			RTW_PRINT_SEL(m, "%s\n", p_str);
+		}
+		RTW_PRINT_SEL(m, "\npattern mask:\n");
+		for (i = 0 ; i < MAX_WKFM_SIZE / 8 ; i++) {
+			_rtw_memset(p_str, 0, max_len);
+			len = 0;
+			for (j = 0 ; j < 8 ; j++) {
+				val8 = pwrpriv->patterns[k].mask[i * 8 + j];
+				len += snprintf(p_str + len, max_len - len,
+						"%02x ", val8);
+			}
+			RTW_PRINT_SEL(m, "%s\n", p_str);
+		}
+
+		RTW_PRINT_SEL(m, "\npriv_pattern_len:\n");
+		RTW_PRINT_SEL(m, "pattern_len: %d\n", pwrpriv->patterns[k].len);
+		RTW_PRINT_SEL(m, "*****************\n");
+	}
+
+	return 0;
+}
+
+ssize_t proc_set_pattern_info(struct file *file, const char __user *buffer,
+			      size_t count, loff_t *pos, void *data)
+{
+	struct net_device *dev = data;
+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
+	struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter);
+	struct wowlan_ioctl_param poidparam;
+	u8 tmp[MAX_WKFM_PATTERN_SIZE] = {0};
+	int ret = 0, num = 0;
+	u8 index = 0;
+
+	poidparam.subcode = 0;
+
+	if (count < 1)
+		return -EFAULT;
+
+	if (count > sizeof(tmp)) {
+		rtw_warn_on(1);
+		return -EFAULT;
+	}
+
+	if (pwrpriv->wowlan_pattern_idx >= MAX_WKFM_CAM_NUM) {
+		RTW_INFO("WARNING: priv-pattern is full(idx: %d)\n",
+			 pwrpriv->wowlan_pattern_idx);
+		RTW_INFO("WARNING: please clean priv-pattern first\n");
+		return -ENOMEM;
+	}
+
+	if (buffer && !copy_from_user(tmp, buffer, count)) {
+		if (strncmp(tmp, "clean", 5) == 0) {
+			poidparam.subcode = WOWLAN_PATTERN_CLEAN;
+			rtw_hal_set_hwreg(padapter,
+					  HW_VAR_WOWLAN, (u8 *)&poidparam);
+		} else {
+			index = pwrpriv->wowlan_pattern_idx;
+			ret = rtw_wowlan_parser_pattern_cmd(tmp,
+					    pwrpriv->patterns[index].content,
+					    &pwrpriv->patterns[index].len,
+					    pwrpriv->patterns[index].mask);
+			if (ret == _TRUE)
+				pwrpriv->wowlan_pattern_idx++;
+		}
+	}
+
+	return count;
+}
+
+int proc_get_wakeup_event(struct seq_file *m, void *v)
+{
+	struct net_device *dev = m->private;
+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
+	struct registry_priv  *registry_par = &padapter->registrypriv;
+
+	RTW_PRINT_SEL(m, "wakeup event: %#02x\n", registry_par->wakeup_event);
+	return 0;
+}
+
+ssize_t proc_set_wakeup_event(struct file *file, const char __user *buffer,
+			      size_t count, loff_t *pos, void *data)
+{
+	struct net_device *dev = data;
+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
+	struct pwrctrl_priv *pwrctrlpriv = adapter_to_pwrctl(padapter);
+	struct registry_priv  *registry_par = &padapter->registrypriv;
+	u32 wakeup_event = 0;
+
+	u8 tmp[8] = {0};
+	int ret = 0, num = 0;
+	u8 index = 0;
+
+	if (count < 1)
+		return -EFAULT;
+
+	if (count > sizeof(tmp)) {
+		rtw_warn_on(1);
+		return -EFAULT;
+	}
+
+	if (buffer && !copy_from_user(tmp, buffer, count))
+		num = sscanf(tmp, "%u", &wakeup_event);
+	else
+		return -EFAULT;
+
+	if (num == 1 && wakeup_event <= 0x07) {
+		registry_par->wakeup_event = wakeup_event;
+
+		if (wakeup_event & BIT(1))
+			pwrctrlpriv->default_patterns_en = _TRUE;
+		else
+			pwrctrlpriv->default_patterns_en = _FALSE;
+
+		rtw_wow_pattern_sw_reset(padapter);
+
+		RTW_INFO("%s: wakeup_event: %#2x, default pattern: %d\n",
+			 __func__, registry_par->wakeup_event,
+			 pwrctrlpriv->default_patterns_en);
+	} else {
+		return -EINVAL;
+	}
+
+	return count;
+}
+
+int proc_get_wakeup_reason(struct seq_file *m, void *v)
+{
+	struct net_device *dev = m->private;
+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
+	struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter);
+	u8 val = pwrpriv->wowlan_last_wake_reason;
+
+	RTW_PRINT_SEL(m, "last wake reason: %#02x\n", val);
+	return 0;
+}
+#endif /*CONFIG_WOWLAN*/
+
+#ifdef CONFIG_GPIO_WAKEUP
+int proc_get_wowlan_gpio_info(struct seq_file *m, void *v)
+{
+	struct net_device *dev = m->private;
+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
+	struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter);
+	u8 val = pwrpriv->is_high_active;
+
+	RTW_PRINT_SEL(m, "wakeup_gpio_idx: %d\n", WAKEUP_GPIO_IDX);
+	RTW_PRINT_SEL(m, "high_active: %d\n", val);
+
+	return 0;
+}
+
+ssize_t proc_set_wowlan_gpio_info(struct file *file, const char __user *buffer,
+				  size_t count, loff_t *pos, void *data)
+{
+	struct net_device *dev = data;
+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
+	struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter);
+	char tmp[32] = {0};
+	int num = 0;
+	u32 is_high_active = 0;
+	u8 val8 = 0;
+
+	if (count < 1)
+		return -EFAULT;
+
+	if (count > sizeof(tmp)) {
+		rtw_warn_on(1);
+		return -EFAULT;
+	}
+
+	if (buffer && !copy_from_user(tmp, buffer, count)) {
+
+		num = sscanf(tmp, "%u", &is_high_active);
+
+		if (num != 1) {
+			RTW_INFO("Invalid format\n");
+			return count;
+		}
+
+		is_high_active = is_high_active == 0 ? 0 : 1;
+
+		pwrpriv->is_high_active = is_high_active;
+
+		rtw_ps_deny(padapter, PS_DENY_IOCTL);
+		LeaveAllPowerSaveModeDirect(padapter);
+
+		#ifdef CONFIG_WAKEUP_GPIO_INPUT_MODE
+		if (pwrpriv->is_high_active == 0)
+			rtw_hal_set_input_gpio(padapter, WAKEUP_GPIO_IDX);
+		else
+			rtw_hal_set_output_gpio(padapter, WAKEUP_GPIO_IDX, 0);
+		#else
+		val8 = (pwrpriv->is_high_active == 0) ? 1 : 0;
+		rtw_hal_switch_gpio_wl_ctrl(padapter, WAKEUP_GPIO_IDX, _TRUE);
+		rtw_hal_set_output_gpio(padapter, WAKEUP_GPIO_IDX, val8);
+		#endif
+		rtw_ps_deny_cancel(padapter, PS_DENY_IOCTL);
+
+		RTW_INFO("set %s %d\n", "gpio_high_active",
+			 pwrpriv->is_high_active);
+		RTW_INFO("%s: set GPIO_%d %d as default.\n",
+			 __func__, WAKEUP_GPIO_IDX, val8);
+	}
+
+	return count;
+}
+#endif /* CONFIG_GPIO_WAKEUP */
+
+#ifdef CONFIG_P2P_WOWLAN
+int proc_get_p2p_wowlan_info(struct seq_file *m, void *v)
+{
+	struct net_device *dev = m->private;
+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
+	struct wifidirect_info	*pwdinfo = &(padapter->wdinfo);
+	struct p2p_wowlan_info	 peerinfo = pwdinfo->p2p_wow_info;
+	if (_TRUE == peerinfo.is_trigger) {
+		RTW_PRINT_SEL(m, "is_trigger: TRUE\n");
+		switch (peerinfo.wowlan_recv_frame_type) {
+		case P2P_WOWLAN_RECV_NEGO_REQ:
+			RTW_PRINT_SEL(m, "Frame Type: Nego Request\n");
+			break;
+		case P2P_WOWLAN_RECV_INVITE_REQ:
+			RTW_PRINT_SEL(m, "Frame Type: Invitation Request\n");
+			break;
+		case P2P_WOWLAN_RECV_PROVISION_REQ:
+			RTW_PRINT_SEL(m, "Frame Type: Provision Request\n");
+			break;
+		default:
+			break;
+		}
+		RTW_PRINT_SEL(m, "Peer Addr: "MAC_FMT"\n", MAC_ARG(peerinfo.wowlan_peer_addr));
+		RTW_PRINT_SEL(m, "Peer WPS Config: %x\n", peerinfo.wowlan_peer_wpsconfig);
+		RTW_PRINT_SEL(m, "Persistent Group: %d\n", peerinfo.wowlan_peer_is_persistent);
+		RTW_PRINT_SEL(m, "Intivation Type: %d\n", peerinfo.wowlan_peer_invitation_type);
+	} else
+		RTW_PRINT_SEL(m, "is_trigger: False\n");
+	return 0;
+}
+#endif /* CONFIG_P2P_WOWLAN */
+#ifdef CONFIG_BCN_CNT_CONFIRM_HDL
+int proc_get_new_bcn_max(struct seq_file *m, void *v)
+{
+	extern int new_bcn_max;
+
+	RTW_PRINT_SEL(m, "%d", new_bcn_max);
+	return 0;
+}
+
+ssize_t proc_set_new_bcn_max(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
+{
+	char tmp[32];
+	extern int new_bcn_max;
+
+	if (count < 1)
+		return -EFAULT;
+
+	if (count > sizeof(tmp)) {
+		rtw_warn_on(1);
+		return -EFAULT;
+	}
+
+	if (buffer && !copy_from_user(tmp, buffer, count))
+		sscanf(tmp, "%d ", &new_bcn_max);
+
+	return count;
+}
+#endif
+#ifdef CONFIG_POWER_SAVING
+int proc_get_ps_info(struct seq_file *m, void *v)
+{
+	struct net_device *dev = m->private;
+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
+	struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter);
+	u8 ips_mode = pwrpriv->ips_mode;
+	u8 lps_mode = pwrpriv->power_mgnt;
+	u8 lps_level = pwrpriv->lps_level;
+	char *str = "";
+
+	RTW_PRINT_SEL(m, "======Power Saving Info:======\n");
+	RTW_PRINT_SEL(m, "*IPS:\n");
+
+	if (ips_mode == IPS_NORMAL) {
+#ifdef CONFIG_FWLPS_IN_IPS
+		str = "FW_LPS_IN_IPS";
+#else
+		str = "Card Disable";
+#endif
+	} else if (ips_mode == IPS_NONE)
+		str = "NO IPS";
+	else if (ips_mode == IPS_LEVEL_2)
+		str = "IPS_LEVEL_2";
+	else
+		str = "invalid ips_mode";
+
+	RTW_PRINT_SEL(m, " IPS mode: %s\n", str);
+	RTW_PRINT_SEL(m, " IPS enter count:%d, IPS leave count:%d\n",
+		      pwrpriv->ips_enter_cnts, pwrpriv->ips_leave_cnts);
+	RTW_PRINT_SEL(m, "------------------------------\n");
+	RTW_PRINT_SEL(m, "*LPS:\n");
+
+	if (lps_mode == PS_MODE_ACTIVE)
+		str = "NO LPS";
+	else if (lps_mode == PS_MODE_MIN)
+		str = "MIN";
+	else if (lps_mode == PS_MODE_MAX)
+		str = "MAX";
+	else if (lps_mode == PS_MODE_DTIM)
+		str = "DTIM";
+	else
+		sprintf(str, "%d", lps_mode);
+
+	RTW_PRINT_SEL(m, " LPS mode: %s\n", str);
+
+	if (pwrpriv->dtim != 0)
+		RTW_PRINT_SEL(m, " DTIM: %d\n", pwrpriv->dtim);
+	RTW_PRINT_SEL(m, " LPS enter count:%d, LPS leave count:%d\n",
+		      pwrpriv->lps_enter_cnts, pwrpriv->lps_leave_cnts);
+
+	if (lps_level == LPS_LCLK)
+		str = "LPS_LCLK";
+	else if  (lps_level == LPS_PG)
+		str = "LPS_PG";
+	else
+		str = "LPS_NORMAL";
+	RTW_PRINT_SEL(m, " LPS level: %s\n", str);
+
+	RTW_PRINT_SEL(m, "=============================\n");
+	return 0;
+}
+
+#ifdef CONFIG_WMMPS_STA
+int proc_get_wmmps_info(struct seq_file *m, void *v)
+{
+	struct net_device *dev = m->private;
+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
+	struct registry_priv	*pregpriv = &padapter->registrypriv;
+	char *uapsd_max_sp_str="";
+
+	if (pregpriv){
+		switch(pregpriv->uapsd_max_sp_len) {
+			case 0:
+				uapsd_max_sp_str = "NO_LIMIT";
+				break;
+			case 1:
+				uapsd_max_sp_str = "TWO_MSDU";
+				break;
+			case 2:
+				uapsd_max_sp_str = "FOUR_MSDU";
+				break;
+			case 3:
+				uapsd_max_sp_str = "SIX_MSDU";
+				break;
+			default:
+				uapsd_max_sp_str = "UNSPECIFIED";
+				break;
+		}
+
+		RTW_PRINT_SEL(m, "====== WMMPS_STA Info:======\n");
+		RTW_PRINT_SEL(m, "uapsd_max_sp_len=0x%02x (%s)\n", pregpriv->uapsd_max_sp_len, uapsd_max_sp_str);
+		RTW_PRINT_SEL(m, "uapsd_ac_enable=0x%02x\n", pregpriv->uapsd_ac_enable);
+		RTW_PRINT_SEL(m, "BIT0 - AC_VO UAPSD: %s\n", (pregpriv->uapsd_ac_enable & DRV_CFG_UAPSD_VO) ? "Enabled" : "Disabled");
+		RTW_PRINT_SEL(m, "BIT1 - AC_VI UAPSD: %s\n", (pregpriv->uapsd_ac_enable & DRV_CFG_UAPSD_VI) ? "Enabled" : "Disabled");
+		RTW_PRINT_SEL(m, "BIT2 - AC_BK UAPSD: %s\n", (pregpriv->uapsd_ac_enable & DRV_CFG_UAPSD_BK) ? "Enabled" : "Disabled");
+		RTW_PRINT_SEL(m, "BIT3 - AC_BE UAPSD: %s\n", (pregpriv->uapsd_ac_enable & DRV_CFG_UAPSD_BE) ? "Enabled" : "Disabled");
+		RTW_PRINT_SEL(m, "============================\n");
+	}
+
+	return 0;
+}
+
+ssize_t proc_set_wmmps_info(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
+{
+	struct net_device *dev = data;
+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
+	struct registry_priv	*pregpriv = &padapter->registrypriv;
+	char tmp[32];
+	u8 uapsd_ac_setting;
+	u8 uapsd_max_sp_len_setting;
+
+	if (count < 1)
+		return -EFAULT;
+
+	if (count > sizeof(tmp)) {
+		rtw_warn_on(1);
+		return -EFAULT;
+	}
+
+	if (buffer && !copy_from_user(tmp, buffer, count)) {
+
+		int num = sscanf(tmp, "%hhu %hhx", &uapsd_max_sp_len_setting, &uapsd_ac_setting);
+
+		if (pregpriv) {
+			if (num >= 1) {
+				pregpriv->uapsd_max_sp_len = uapsd_max_sp_len_setting;
+				RTW_INFO("uapsd_max_sp_len = %d\n", pregpriv->uapsd_max_sp_len);
+			}
+
+			if (num >= 2) {
+				pregpriv->uapsd_ac_enable = uapsd_ac_setting;
+				RTW_INFO("uapsd_ac_enable = 0x%02x\n", pregpriv->uapsd_ac_enable);
+			}
+		}
+	}
+
+	return count;
+}
+#endif /* CONFIG_WMMPS_STA */
+#endif /* CONFIG_POWER_SAVING */
+
+#ifdef CONFIG_TDLS
+int proc_get_tdls_enable(struct seq_file *m, void *v)
+{
+	struct net_device *dev = m->private;
+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
+	struct registry_priv *pregpriv = &padapter->registrypriv;
+
+	if (pregpriv)
+		RTW_PRINT_SEL(m, "TDLS is %s !\n", (rtw_is_tdls_enabled(padapter) == _TRUE) ? "enabled" : "disabled");
+
+	return 0;
+}
+
+ssize_t proc_set_tdls_enable(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
+{
+	struct net_device *dev = data;
+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
+	struct registry_priv	*pregpriv = &padapter->registrypriv;
+	char tmp[32];
+	u32 en_tdls = 0;
+
+	if (count < 1)
+		return -EFAULT;
+
+	if (count > sizeof(tmp)) {
+		rtw_warn_on(1);
+		return -EFAULT;
+	}
+
+	if (buffer && !copy_from_user(tmp, buffer, count)) {
+
+		int num = sscanf(tmp, "%d ", &en_tdls);
+
+		if (num == 1 && pregpriv) {
+			if (en_tdls > 0)
+				rtw_enable_tdls_func(padapter);
+			else
+				rtw_disable_tdls_func(padapter, _TRUE);
+		}
+	}
+
+	return count;
+}
+
+static int proc_tdls_display_tdls_function_info(struct seq_file *m)
+{
+	struct net_device *dev = m->private;
+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
+	struct tdls_info *ptdlsinfo = &padapter->tdlsinfo;
+	u8 SpaceBtwnItemAndValue = TDLS_DBG_INFO_SPACE_BTWN_ITEM_AND_VALUE;
+	u8 SpaceBtwnItemAndValueTmp = 0;
+	BOOLEAN FirstMatchFound = _FALSE;
+	int j = 0;
+
+	RTW_PRINT_SEL(m, "============[TDLS Function Info]============\n");
+	RTW_PRINT_SEL(m, "%-*s = %s\n", SpaceBtwnItemAndValue, "TDLS Enable", (rtw_is_tdls_enabled(padapter) == _TRUE) ? "_TRUE" : "_FALSE");
+	RTW_PRINT_SEL(m, "%-*s = %s\n", SpaceBtwnItemAndValue, "TDLS Driver Setup", (ptdlsinfo->driver_setup == _TRUE) ? "_TRUE" : "_FALSE");
+	RTW_PRINT_SEL(m, "%-*s = %s\n", SpaceBtwnItemAndValue, "TDLS Prohibited", (ptdlsinfo->ap_prohibited == _TRUE) ? "_TRUE" : "_FALSE");
+	RTW_PRINT_SEL(m, "%-*s = %s\n", SpaceBtwnItemAndValue, "TDLS Channel Switch Prohibited", (ptdlsinfo->ch_switch_prohibited == _TRUE) ? "_TRUE" : "_FALSE");
+	RTW_PRINT_SEL(m, "%-*s = %s\n", SpaceBtwnItemAndValue, "TDLS Link Established", (ptdlsinfo->link_established == _TRUE) ? "_TRUE" : "_FALSE");
+	RTW_PRINT_SEL(m, "%-*s = %d/%d\n", SpaceBtwnItemAndValue, "TDLS STA Num (Linked/Allowed)", ptdlsinfo->sta_cnt, MAX_ALLOWED_TDLS_STA_NUM);
+	RTW_PRINT_SEL(m, "%-*s = %s\n", SpaceBtwnItemAndValue, "TDLS Allowed STA Num Reached", (ptdlsinfo->sta_maximum == _TRUE) ? "_TRUE" : "_FALSE");
+
+#ifdef CONFIG_TDLS_CH_SW
+	RTW_PRINT_SEL(m, "%-*s =", SpaceBtwnItemAndValue, "TDLS CH SW State");
+	if (ptdlsinfo->chsw_info.ch_sw_state == TDLS_STATE_NONE)
+		RTW_PRINT_SEL(m, "%-*s%s\n", SpaceBtwnItemAndValueTmp, " ", "TDLS_STATE_NONE");
+	else {
+		for (j = 0; j < 32; j++) {
+			if (ptdlsinfo->chsw_info.ch_sw_state & BIT(j)) {
+				if (FirstMatchFound ==  _FALSE) {
+					SpaceBtwnItemAndValueTmp = 1;
+					FirstMatchFound = _TRUE;
+				} else
+					SpaceBtwnItemAndValueTmp = SpaceBtwnItemAndValue + 3;
+				switch (BIT(j)) {
+				case TDLS_INITIATOR_STATE:
+					RTW_PRINT_SEL(m, "%-*s%s\n", SpaceBtwnItemAndValueTmp, " ", "TDLS_INITIATOR_STATE");
+					break;
+				case TDLS_RESPONDER_STATE:
+					RTW_PRINT_SEL(m, "%-*s%s\n", SpaceBtwnItemAndValueTmp, " ", "TDLS_RESPONDER_STATE");
+					break;
+				case TDLS_LINKED_STATE:
+					RTW_PRINT_SEL(m, "%-*s%s\n", SpaceBtwnItemAndValueTmp, " ", "TDLS_LINKED_STATE");
+					break;
+				case TDLS_WAIT_PTR_STATE:
+					RTW_PRINT_SEL(m, "%-*s%s\n", SpaceBtwnItemAndValueTmp, " ", "TDLS_WAIT_PTR_STATE");
+					break;
+				case TDLS_ALIVE_STATE:
+					RTW_PRINT_SEL(m, "%-*s%s\n", SpaceBtwnItemAndValueTmp, " ", "TDLS_ALIVE_STATE");
+					break;
+				case TDLS_CH_SWITCH_ON_STATE:
+					RTW_PRINT_SEL(m, "%-*s%s\n", SpaceBtwnItemAndValueTmp, " ", "TDLS_CH_SWITCH_ON_STATE");
+					break;
+				case TDLS_PEER_AT_OFF_STATE:
+					RTW_PRINT_SEL(m, "%-*s%s\n", SpaceBtwnItemAndValueTmp, " ", "TDLS_PEER_AT_OFF_STATE");
+					break;
+				case TDLS_CH_SW_INITIATOR_STATE:
+					RTW_PRINT_SEL(m, "%-*s%s\n", SpaceBtwnItemAndValueTmp, " ", "TDLS_CH_SW_INITIATOR_STATE");
+					break;
+				case TDLS_WAIT_CH_RSP_STATE:
+					RTW_PRINT_SEL(m, "%-*s%s\n", SpaceBtwnItemAndValue, " ", "TDLS_WAIT_CH_RSP_STATE");
+					break;
+				default:
+					RTW_PRINT_SEL(m, "%-*sBIT(%d)\n", SpaceBtwnItemAndValueTmp, " ", j);
+					break;
+				}
+			}
+		}
+	}
+
+	RTW_PRINT_SEL(m, "%-*s = %s\n", SpaceBtwnItemAndValue, "TDLS CH SW On", (ATOMIC_READ(&ptdlsinfo->chsw_info.chsw_on) == _TRUE) ? "_TRUE" : "_FALSE");
+	RTW_PRINT_SEL(m, "%-*s = %d\n", SpaceBtwnItemAndValue, "TDLS CH SW Off-Channel Num", ptdlsinfo->chsw_info.off_ch_num);
+	RTW_PRINT_SEL(m, "%-*s = %d\n", SpaceBtwnItemAndValue, "TDLS CH SW Channel Offset", ptdlsinfo->chsw_info.ch_offset);
+	RTW_PRINT_SEL(m, "%-*s = %d\n", SpaceBtwnItemAndValue, "TDLS CH SW Current Time", ptdlsinfo->chsw_info.cur_time);
+	RTW_PRINT_SEL(m, "%-*s = %s\n", SpaceBtwnItemAndValue, "TDLS CH SW Delay Switch Back", (ptdlsinfo->chsw_info.delay_switch_back == _TRUE) ? "_TRUE" : "_FALSE");
+	RTW_PRINT_SEL(m, "%-*s = %d\n", SpaceBtwnItemAndValue, "TDLS CH SW Dump Back", ptdlsinfo->chsw_info.dump_stack);
+#endif
+
+	RTW_PRINT_SEL(m, "%-*s = %s\n", SpaceBtwnItemAndValue, "TDLS Device Discovered", (ptdlsinfo->dev_discovered == _TRUE) ? "_TRUE" : "_FALSE");
+
+	return 0;
+}
+
+static int proc_tdls_display_network_info(struct seq_file *m)
+{
+	struct net_device *dev = m->private;
+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
+	struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
+	struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
+	struct wlan_network *cur_network = &(pmlmepriv->cur_network);
+	int i = 0;
+	u8 SpaceBtwnItemAndValue = TDLS_DBG_INFO_SPACE_BTWN_ITEM_AND_VALUE;
+
+	/* Display the linked AP/GO info */
+	RTW_PRINT_SEL(m, "============[Associated AP/GO Info]============\n");
+
+	if ((pmlmepriv->fw_state & WIFI_STATION_STATE) && (pmlmepriv->fw_state & _FW_LINKED)) {
+		RTW_PRINT_SEL(m, "%-*s = %s\n", SpaceBtwnItemAndValue, "BSSID", cur_network->network.Ssid.Ssid);
+		RTW_PRINT_SEL(m, "%-*s = "MAC_FMT"\n", SpaceBtwnItemAndValue, "Mac Address", MAC_ARG(cur_network->network.MacAddress));
+
+		RTW_PRINT_SEL(m, "%-*s = ", SpaceBtwnItemAndValue, "Wireless Mode");
+		for (i = 0; i < 8; i++) {
+			if (pmlmeext->cur_wireless_mode & BIT(i)) {
+				switch (BIT(i)) {
+				case WIRELESS_11B:
+					RTW_PRINT_SEL(m, "%4s", "11B ");
+					break;
+				case WIRELESS_11G:
+					RTW_PRINT_SEL(m, "%4s", "11G ");
+					break;
+				case WIRELESS_11A:
+					RTW_PRINT_SEL(m, "%4s", "11A ");
+					break;
+				case WIRELESS_11_24N:
+					RTW_PRINT_SEL(m, "%7s", "11_24N ");
+					break;
+				case WIRELESS_11_5N:
+					RTW_PRINT_SEL(m, "%6s", "11_5N ");
+					break;
+				case WIRELESS_AUTO:
+					RTW_PRINT_SEL(m, "%5s", "AUTO ");
+					break;
+				case WIRELESS_11AC:
+					RTW_PRINT_SEL(m, "%5s", "11AC ");
+					break;
+				}
+			}
+		}
+		RTW_PRINT_SEL(m, "\n");
+
+		RTW_PRINT_SEL(m, "%-*s = ", SpaceBtwnItemAndValue, "Privacy");
+		switch (padapter->securitypriv.dot11PrivacyAlgrthm) {
+		case _NO_PRIVACY_:
+			RTW_PRINT_SEL(m, "%s\n", "NO PRIVACY");
+			break;
+		case _WEP40_:
+			RTW_PRINT_SEL(m, "%s\n", "WEP 40");
+			break;
+		case _TKIP_:
+			RTW_PRINT_SEL(m, "%s\n", "TKIP");
+			break;
+		case _TKIP_WTMIC_:
+			RTW_PRINT_SEL(m, "%s\n", "TKIP WTMIC");
+			break;
+		case _AES_:
+			RTW_PRINT_SEL(m, "%s\n", "AES");
+			break;
+		case _WEP104_:
+			RTW_PRINT_SEL(m, "%s\n", "WEP 104");
+			break;
+		case _WEP_WPA_MIXED_:
+			RTW_PRINT_SEL(m, "%s\n", "WEP/WPA Mixed");
+			break;
+		case _SMS4_:
+			RTW_PRINT_SEL(m, "%s\n", "SMS4");
+			break;
+#ifdef CONFIG_IEEE80211W
+		case _BIP_:
+			RTW_PRINT_SEL(m, "%s\n", "BIP");
+			break;
+#endif /* CONFIG_IEEE80211W */
+		}
+
+		RTW_PRINT_SEL(m, "%-*s = %d\n", SpaceBtwnItemAndValue, "Channel", pmlmeext->cur_channel);
+		RTW_PRINT_SEL(m, "%-*s = ", SpaceBtwnItemAndValue, "Channel Offset");
+		switch (pmlmeext->cur_ch_offset) {
+		case HAL_PRIME_CHNL_OFFSET_DONT_CARE:
+			RTW_PRINT_SEL(m, "%s\n", "N/A");
+			break;
+		case HAL_PRIME_CHNL_OFFSET_LOWER:
+			RTW_PRINT_SEL(m, "%s\n", "Lower");
+			break;
+		case HAL_PRIME_CHNL_OFFSET_UPPER:
+			RTW_PRINT_SEL(m, "%s\n", "Upper");
+			break;
+		}
+
+		RTW_PRINT_SEL(m, "%-*s = ", SpaceBtwnItemAndValue, "Bandwidth Mode");
+		switch (pmlmeext->cur_bwmode) {
+		case CHANNEL_WIDTH_20:
+			RTW_PRINT_SEL(m, "%s\n", "20MHz");
+			break;
+		case CHANNEL_WIDTH_40:
+			RTW_PRINT_SEL(m, "%s\n", "40MHz");
+			break;
+		case CHANNEL_WIDTH_80:
+			RTW_PRINT_SEL(m, "%s\n", "80MHz");
+			break;
+		case CHANNEL_WIDTH_160:
+			RTW_PRINT_SEL(m, "%s\n", "160MHz");
+			break;
+		case CHANNEL_WIDTH_80_80:
+			RTW_PRINT_SEL(m, "%s\n", "80MHz + 80MHz");
+			break;
+		}
+	} else
+		RTW_PRINT_SEL(m, "No association with AP/GO exists!\n");
+
+	return 0;
+}
+
+static int proc_tdls_display_tdls_sta_info(struct seq_file *m)
+{
+	struct net_device *dev = m->private;
+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
+	struct sta_priv *pstapriv = &padapter->stapriv;
+	struct tdls_info *ptdlsinfo = &padapter->tdlsinfo;
+	struct sta_info *psta;
+	int i = 0, j = 0;
+	_irqL irqL;
+	_list	*plist, *phead;
+	u8 SpaceBtwnItemAndValue = TDLS_DBG_INFO_SPACE_BTWN_ITEM_AND_VALUE;
+	u8 SpaceBtwnItemAndValueTmp = 0;
+	u8 NumOfTdlsStaToShow = 0;
+	BOOLEAN FirstMatchFound = _FALSE;
+
+	/* Search for TDLS sta info to display */
+	_enter_critical_bh(&pstapriv->sta_hash_lock, &irqL);
+	for (i = 0; i < NUM_STA; i++) {
+		phead = &(pstapriv->sta_hash[i]);
+		plist = get_next(phead);
+		while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) {
+			psta = LIST_CONTAINOR(plist, struct sta_info, hash_list);
+			plist = get_next(plist);
+			if (psta->tdls_sta_state != TDLS_STATE_NONE) {
+				/* We got one TDLS sta info to show */
+				RTW_PRINT_SEL(m, "============[TDLS Peer STA Info: STA %d]============\n", ++NumOfTdlsStaToShow);
+				RTW_PRINT_SEL(m, "%-*s = "MAC_FMT"\n", SpaceBtwnItemAndValue, "Mac Address", MAC_ARG(psta->cmn.mac_addr));
+				RTW_PRINT_SEL(m, "%-*s =", SpaceBtwnItemAndValue, "TDLS STA State");
+				SpaceBtwnItemAndValueTmp = 0;
+				FirstMatchFound = _FALSE;
+				for (j = 0; j < 32; j++) {
+					if (psta->tdls_sta_state & BIT(j)) {
+						if (FirstMatchFound ==  _FALSE) {
+							SpaceBtwnItemAndValueTmp = 1;
+							FirstMatchFound = _TRUE;
+						} else
+							SpaceBtwnItemAndValueTmp = SpaceBtwnItemAndValue + 3;
+						switch (BIT(j)) {
+						case TDLS_INITIATOR_STATE:
+							RTW_PRINT_SEL(m, "%-*s%s\n", SpaceBtwnItemAndValueTmp, " ", "TDLS_INITIATOR_STATE");
+							break;
+						case TDLS_RESPONDER_STATE:
+							RTW_PRINT_SEL(m, "%-*s%s\n", SpaceBtwnItemAndValueTmp, " ", "TDLS_RESPONDER_STATE");
+							break;
+						case TDLS_LINKED_STATE:
+							RTW_PRINT_SEL(m, "%-*s%s\n", SpaceBtwnItemAndValueTmp, " ", "TDLS_LINKED_STATE");
+							break;
+						case TDLS_WAIT_PTR_STATE:
+							RTW_PRINT_SEL(m, "%-*s%s\n", SpaceBtwnItemAndValueTmp, " ", "TDLS_WAIT_PTR_STATE");
+							break;
+						case TDLS_ALIVE_STATE:
+							RTW_PRINT_SEL(m, "%-*s%s\n", SpaceBtwnItemAndValueTmp, " ", "TDLS_ALIVE_STATE");
+							break;
+						case TDLS_CH_SWITCH_ON_STATE:
+							RTW_PRINT_SEL(m, "%-*s%s\n", SpaceBtwnItemAndValueTmp, " ", "TDLS_CH_SWITCH_ON_STATE");
+							break;
+						case TDLS_PEER_AT_OFF_STATE:
+							RTW_PRINT_SEL(m, "%-*s%s\n", SpaceBtwnItemAndValueTmp, " ", "TDLS_PEER_AT_OFF_STATE");
+							break;
+						case TDLS_CH_SW_INITIATOR_STATE:
+							RTW_PRINT_SEL(m, "%-*s%s\n", SpaceBtwnItemAndValueTmp, " ", "TDLS_CH_SW_INITIATOR_STATE");
+							break;
+						case TDLS_WAIT_CH_RSP_STATE:
+							RTW_PRINT_SEL(m, "%-*s%s\n", SpaceBtwnItemAndValue, " ", "TDLS_WAIT_CH_RSP_STATE");
+							break;
+						default:
+							RTW_PRINT_SEL(m, "%-*sBIT(%d)\n", SpaceBtwnItemAndValueTmp, " ", j);
+							break;
+						}
+					}
+				}
+
+				RTW_PRINT_SEL(m, "%-*s = ", SpaceBtwnItemAndValue, "Wireless Mode");
+				for (j = 0; j < 8; j++) {
+					if (psta->wireless_mode & BIT(j)) {
+						switch (BIT(j)) {
+						case WIRELESS_11B:
+							RTW_PRINT_SEL(m, "%4s", "11B ");
+							break;
+						case WIRELESS_11G:
+							RTW_PRINT_SEL(m, "%4s", "11G ");
+							break;
+						case WIRELESS_11A:
+							RTW_PRINT_SEL(m, "%4s", "11A ");
+							break;
+						case WIRELESS_11_24N:
+							RTW_PRINT_SEL(m, "%7s", "11_24N ");
+							break;
+						case WIRELESS_11_5N:
+							RTW_PRINT_SEL(m, "%6s", "11_5N ");
+							break;
+						case WIRELESS_AUTO:
+							RTW_PRINT_SEL(m, "%5s", "AUTO ");
+							break;
+						case WIRELESS_11AC:
+							RTW_PRINT_SEL(m, "%5s", "11AC ");
+							break;
+						}
+					}
+				}
+				RTW_PRINT_SEL(m, "\n");
+
+				RTW_PRINT_SEL(m, "%-*s = ", SpaceBtwnItemAndValue, "Bandwidth Mode");
+				switch (psta->cmn.bw_mode) {
+				case CHANNEL_WIDTH_20:
+					RTW_PRINT_SEL(m, "%s\n", "20MHz");
+					break;
+				case CHANNEL_WIDTH_40:
+					RTW_PRINT_SEL(m, "%s\n", "40MHz");
+					break;
+				case CHANNEL_WIDTH_80:
+					RTW_PRINT_SEL(m, "%s\n", "80MHz");
+					break;
+				case CHANNEL_WIDTH_160:
+					RTW_PRINT_SEL(m, "%s\n", "160MHz");
+					break;
+				case CHANNEL_WIDTH_80_80:
+					RTW_PRINT_SEL(m, "%s\n", "80MHz + 80MHz");
+					break;
+				case CHANNEL_WIDTH_5:
+					RTW_PRINT_SEL(m, "%s\n", "5MHz");
+					break;
+				case CHANNEL_WIDTH_10:
+					RTW_PRINT_SEL(m, "%s\n", "10MHz");
+					break;
+				default:
+					RTW_PRINT_SEL(m, "(%d)%s\n", psta->cmn.bw_mode, "invalid");
+					break;
+				}
+
+				RTW_PRINT_SEL(m, "%-*s = ", SpaceBtwnItemAndValue, "Privacy");
+				switch (psta->dot118021XPrivacy) {
+				case _NO_PRIVACY_:
+					RTW_PRINT_SEL(m, "%s\n", "NO PRIVACY");
+					break;
+				case _WEP40_:
+					RTW_PRINT_SEL(m, "%s\n", "WEP 40");
+					break;
+				case _TKIP_:
+					RTW_PRINT_SEL(m, "%s\n", "TKIP");
+					break;
+				case _TKIP_WTMIC_:
+					RTW_PRINT_SEL(m, "%s\n", "TKIP WTMIC");
+					break;
+				case _AES_:
+					RTW_PRINT_SEL(m, "%s\n", "AES");
+					break;
+				case _WEP104_:
+					RTW_PRINT_SEL(m, "%s\n", "WEP 104");
+					break;
+				case _WEP_WPA_MIXED_:
+					RTW_PRINT_SEL(m, "%s\n", "WEP/WPA Mixed");
+					break;
+				case _SMS4_:
+					RTW_PRINT_SEL(m, "%s\n", "SMS4");
+					break;
+#ifdef CONFIG_IEEE80211W
+				case _BIP_:
+					RTW_PRINT_SEL(m, "%s\n", "BIP");
+					break;
+#endif /* CONFIG_IEEE80211W */
+				}
+
+				RTW_PRINT_SEL(m, "%-*s = %d sec/%d sec\n", SpaceBtwnItemAndValue, "TPK Lifetime (Current/Expire)", psta->TPK_count, psta->TDLS_PeerKey_Lifetime);
+				RTW_PRINT_SEL(m, "%-*s = %llu\n", SpaceBtwnItemAndValue, "Tx Packets Over Direct Link", psta->sta_stats.tx_pkts);
+				RTW_PRINT_SEL(m, "%-*s = %llu\n", SpaceBtwnItemAndValue, "Rx Packets Over Direct Link", psta->sta_stats.rx_data_pkts);
+			}
+		}
+	}
+	_exit_critical_bh(&pstapriv->sta_hash_lock, &irqL);
+	if (NumOfTdlsStaToShow == 0) {
+		RTW_PRINT_SEL(m, "============[TDLS Peer STA Info]============\n");
+		RTW_PRINT_SEL(m, "No TDLS direct link exists!\n");
+	}
+
+	return 0;
+}
+
+int proc_get_tdls_info(struct seq_file *m, void *v)
+{
+	struct net_device *dev = m->private;
+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
+	struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
+	struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
+	struct wlan_network *cur_network = &(pmlmepriv->cur_network);
+	struct sta_priv *pstapriv = &padapter->stapriv;
+	struct tdls_info *ptdlsinfo = &padapter->tdlsinfo;
+	struct sta_info *psta;
+	int i = 0, j = 0;
+	_irqL irqL;
+	_list	*plist, *phead;
+	u8 SpaceBtwnItemAndValue = 41;
+	u8 SpaceBtwnItemAndValueTmp = 0;
+	u8 NumOfTdlsStaToShow = 0;
+	BOOLEAN FirstMatchFound = _FALSE;
+
+	if (hal_chk_wl_func(padapter, WL_FUNC_TDLS) == _FALSE) {
+		RTW_PRINT_SEL(m, "No tdls info can be shown since hal doesn't support tdls\n");
+		return 0;
+	}
+
+	proc_tdls_display_tdls_function_info(m);
+	proc_tdls_display_network_info(m);
+	proc_tdls_display_tdls_sta_info(m);
+
+	return 0;
+}
+#endif
+
+int proc_get_monitor(struct seq_file *m, void *v)
+{
+	struct net_device *dev = m->private;
+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
+	struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
+
+	if (WIFI_MONITOR_STATE == get_fwstate(pmlmepriv)) {
+		RTW_PRINT_SEL(m, "Monitor mode : Enable\n");
+
+		RTW_PRINT_SEL(m, "ch=%d, ch_offset=%d, bw=%d\n",
+			rtw_get_oper_ch(padapter), rtw_get_oper_choffset(padapter), rtw_get_oper_bw(padapter));
+	} else
+		RTW_PRINT_SEL(m, "Monitor mode : Disable\n");
+
+	return 0;
+}
+
+ssize_t proc_set_monitor(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
+{
+	char tmp[32];
+	struct net_device *dev = data;
+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
+	u8 target_chan, target_offset, target_bw;
+
+	if (count < 3) {
+		RTW_INFO("argument size is less than 3\n");
+		return -EFAULT;
+	}
+
+	if (count > sizeof(tmp)) {
+		rtw_warn_on(1);
+		return -EFAULT;
+	}
+
+	if (buffer && !copy_from_user(tmp, buffer, count)) {
+		int num = sscanf(tmp, "%hhu %hhu %hhu", &target_chan, &target_offset, &target_bw);
+
+		if (num != 3) {
+			RTW_INFO("invalid write_reg parameter!\n");
+			return count;
+		}
+
+		padapter->mlmeextpriv.cur_channel  = target_chan;
+		set_channel_bwmode(padapter, target_chan, target_offset, target_bw);
+	}
+
+	return count;
+}
+#ifdef DBG_XMIT_BLOCK
+int proc_get_xmit_block(struct seq_file *m, void *v)
+{
+	struct net_device *dev = m->private;
+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
+
+	dump_xmit_block(m, padapter);
+
+	return 0;
+}
+
+ssize_t proc_set_xmit_block(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
+{
+	struct net_device *dev = data;
+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
+	char tmp[32];
+	u8 xb_mode, xb_reason;
+
+	if (count < 1)
+		return -EFAULT;
+
+	if (count > sizeof(tmp)) {
+		rtw_warn_on(1);
+		return -EFAULT;
+	}
+
+	if (buffer && !copy_from_user(tmp, buffer, count)) {
+
+		int num = sscanf(tmp, "%hhx %hhx", &xb_mode, &xb_reason);
+
+		if (num != 2) {
+			RTW_INFO("invalid parameter!\n");
+			return count;
+		}
+
+		if (xb_mode == 0)/*set*/
+			rtw_set_xmit_block(padapter, xb_reason);
+		else if (xb_mode == 1)/*clear*/
+			rtw_clr_xmit_block(padapter, xb_reason);
+		else
+			RTW_INFO("invalid parameter!\n");
+	}
+
+	return count;
+}
+#endif
+
+#include <hal_data.h>
+int proc_get_efuse_map(struct seq_file *m, void *v)
+{
+	struct net_device *dev = m->private;
+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
+	PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter);
+	struct pwrctrl_priv *pwrctrlpriv  = adapter_to_pwrctl(padapter);
+	PEFUSE_HAL pEfuseHal = &pHalData->EfuseHal;
+	int i, j;
+	u8 ips_mode = IPS_NUM;
+	u16 mapLen;
+
+	EFUSE_GetEfuseDefinition(padapter, EFUSE_WIFI, TYPE_EFUSE_MAP_LEN, (void *)&mapLen, _FALSE);
+	if (mapLen > EFUSE_MAX_MAP_LEN)
+		mapLen = EFUSE_MAX_MAP_LEN;
+
+	ips_mode = pwrctrlpriv->ips_mode;
+	rtw_pm_set_ips(padapter, IPS_NONE);
+
+	if (pHalData->efuse_file_status == EFUSE_FILE_LOADED) {
+		RTW_PRINT_SEL(m, "File eFuse Map loaded! file path:%s\nDriver eFuse Map From File\n", EFUSE_MAP_PATH);
+		if (pHalData->bautoload_fail_flag)
+			RTW_PRINT_SEL(m, "File Autoload fail!!!\n");
+	} else if (pHalData->efuse_file_status ==  EFUSE_FILE_FAILED) {
+		RTW_PRINT_SEL(m, "Open File eFuse Map Fail ! file path:%s\nDriver eFuse Map From Default\n", EFUSE_MAP_PATH);
+		if (pHalData->bautoload_fail_flag)
+			RTW_PRINT_SEL(m, "HW Autoload fail!!!\n");
+	} else {
+		RTW_PRINT_SEL(m, "Driver eFuse Map From HW\n");
+		if (pHalData->bautoload_fail_flag)
+			RTW_PRINT_SEL(m, "HW Autoload fail!!!\n");
+	}
+	for (i = 0; i < mapLen; i += 16) {
+		RTW_PRINT_SEL(m, "0x%02x\t", i);
+		for (j = 0; j < 8; j++)
+			RTW_PRINT_SEL(m, "%02X ", pHalData->efuse_eeprom_data[i + j]);
+		RTW_PRINT_SEL(m, "\t");
+		for (; j < 16; j++)
+			RTW_PRINT_SEL(m, "%02X ", pHalData->efuse_eeprom_data[i + j]);
+		RTW_PRINT_SEL(m, "\n");
+	}
+
+	if (rtw_efuse_map_read(padapter, 0, mapLen, pEfuseHal->fakeEfuseInitMap) == _FAIL) {
+		RTW_PRINT_SEL(m, "WARN - Read Realmap Failed\n");
+		return 0;
+	}
+
+	RTW_PRINT_SEL(m, "\n");
+	RTW_PRINT_SEL(m, "HW eFuse Map\n");
+	for (i = 0; i < mapLen; i += 16) {
+		RTW_PRINT_SEL(m, "0x%02x\t", i);
+		for (j = 0; j < 8; j++)
+			RTW_PRINT_SEL(m, "%02X ", pEfuseHal->fakeEfuseInitMap[i + j]);
+		RTW_PRINT_SEL(m, "\t");
+		for (; j < 16; j++)
+			RTW_PRINT_SEL(m, "%02X ", pEfuseHal->fakeEfuseInitMap[i + j]);
+		RTW_PRINT_SEL(m, "\n");
+	}
+
+	rtw_pm_set_ips(padapter, ips_mode);
+
+	return 0;
+}
+
+ssize_t proc_set_efuse_map(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
+{
+#if 0
+	char tmp[256] = {0};
+	u32 addr, cnts;
+	u8 efuse_data;
+
+	int jj, kk;
+
+	struct net_device *dev = data;
+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
+	struct pwrctrl_priv *pwrctrlpriv  = adapter_to_pwrctl(padapter);
+	u8 ips_mode = IPS_NUM;
+
+	if (count < 3) {
+		RTW_INFO("argument size is less than 3\n");
+		return -EFAULT;
+	}
+
+	if (count > sizeof(tmp)) {
+		rtw_warn_on(1);
+		return -EFAULT;
+	}
+
+	if (buffer && !copy_from_user(tmp, buffer, count)) {
+
+		int num = sscanf(tmp, "%x %d %x", &addr, &cnts, &efuse_data);
+
+		if (num != 3) {
+			RTW_INFO("invalid write_reg parameter!\n");
+			return count;
+		}
+	}
+	ips_mode = pwrctrlpriv->ips_mode;
+	rtw_pm_set_ips(padapter, IPS_NONE);
+	if (rtw_efuse_map_write(padapter, addr, cnts, &efuse_data) == _FAIL)
+		RTW_INFO("WARN - rtw_efuse_map_write error!!\n");
+	rtw_pm_set_ips(padapter, ips_mode);
+#endif
+	return count;
+}
+
+#ifdef CONFIG_IEEE80211W
+ssize_t proc_set_tx_sa_query(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
+{
+	struct net_device *dev = data;
+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
+	struct mlme_ext_priv	*pmlmeext = &padapter->mlmeextpriv;
+	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
+	struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
+	struct	sta_priv *pstapriv = &padapter->stapriv;
+	struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
+	struct macid_ctl_t *macid_ctl = dvobj_to_macidctl(dvobj);
+	struct sta_info *psta;
+	_list	*plist, *phead;
+	_irqL	 irqL;
+	char tmp[16];
+	u8	mac_addr[NUM_STA][ETH_ALEN];
+	u32 key_type;
+	u8 index;
+
+	if (count > 2) {
+		RTW_INFO("argument size is more than 2\n");
+		return -EFAULT;
+	}
+
+	if (buffer && !copy_from_user(tmp, buffer, sizeof(tmp))) {
+
+		int num = sscanf(tmp, "%x", &key_type);
+
+		if (num !=  1) {
+			RTW_INFO("invalid read_reg parameter!\n");
+			return count;
+		}
+		RTW_INFO("0: set sa query request , key_type=%d\n", key_type);
+	}
+
+	if ((check_fwstate(pmlmepriv, WIFI_STATION_STATE) == _TRUE)
+	    && (check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE) && SEC_IS_BIP_KEY_INSTALLED(&padapter->securitypriv) == _TRUE) {
+		RTW_INFO("STA:"MAC_FMT"\n", MAC_ARG(get_my_bssid(&(pmlmeinfo->network))));
+		/* TX unicast sa_query to AP */
+		issue_action_SA_Query(padapter, get_my_bssid(&(pmlmeinfo->network)), 0, 0, (u8)key_type);
+	} else if (check_fwstate(pmlmepriv, WIFI_AP_STATE) == _TRUE && SEC_IS_BIP_KEY_INSTALLED(&padapter->securitypriv) == _TRUE) {
+		/* TX unicast sa_query to every client STA */
+		_enter_critical_bh(&pstapriv->sta_hash_lock, &irqL);
+		for (index = 0; index < NUM_STA; index++) {
+			psta = NULL;
+
+			phead = &(pstapriv->sta_hash[index]);
+			plist = get_next(phead);
+
+			while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) {
+				psta = LIST_CONTAINOR(plist, struct sta_info, hash_list);
+				plist = get_next(plist);
+				_rtw_memcpy(&mac_addr[psta->cmn.mac_id][0], psta->cmn.mac_addr, ETH_ALEN);
+			}
+		}
+		_exit_critical_bh(&pstapriv->sta_hash_lock, &irqL);
+
+		for (index = 0; index < macid_ctl->num && index < NUM_STA; index++) {
+			if (rtw_macid_is_used(macid_ctl, index) && !rtw_macid_is_bmc(macid_ctl, index)) {
+				if (!_rtw_memcmp(get_my_bssid(&(pmlmeinfo->network)), &mac_addr[index][0], ETH_ALEN)
+				    && !IS_MCAST(&mac_addr[index][0])) {
+					issue_action_SA_Query(padapter, &mac_addr[index][0], 0, 0, (u8)key_type);
+					RTW_INFO("STA[%u]:"MAC_FMT"\n", index , MAC_ARG(&mac_addr[index][0]));
+				}
+			}
+		}
+	}
+
+	return count;
+}
+
+int proc_get_tx_sa_query(struct seq_file *m, void *v)
+{
+	struct net_device *dev = m->private;
+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
+
+	RTW_PRINT_SEL(m, "%s\n", __func__);
+	return 0;
+}
+
+ssize_t proc_set_tx_deauth(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
+{
+	struct net_device *dev = data;
+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
+	struct mlme_ext_priv	*pmlmeext = &padapter->mlmeextpriv;
+	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
+	struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
+	struct	sta_priv *pstapriv = &padapter->stapriv;
+	struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
+	struct macid_ctl_t *macid_ctl = dvobj_to_macidctl(dvobj);
+	struct sta_info *psta;
+	_list	*plist, *phead;
+	_irqL	 irqL;
+	char tmp[16];
+	u8	mac_addr[NUM_STA][ETH_ALEN];
+	u8 bc_addr[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
+	u32 key_type;
+	u8 index;
+
+
+	if (count > 2) {
+		RTW_INFO("argument size is more than 2\n");
+		return -EFAULT;
+	}
+
+	if (buffer && !copy_from_user(tmp, buffer, sizeof(tmp))) {
+
+		int num = sscanf(tmp, "%x", &key_type);
+
+		if (num !=  1) {
+			RTW_INFO("invalid read_reg parameter!\n");
+			return count;
+		}
+		RTW_INFO("key_type=%d\n", key_type);
+	}
+	if (key_type < 0 || key_type > 4)
+		return count;
+
+	if ((check_fwstate(pmlmepriv, WIFI_STATION_STATE) == _TRUE)
+	    && (check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE)) {
+		if (key_type == 3) /* key_type 3 only for AP mode */
+			return count;
+		/* TX unicast deauth to AP */
+		issue_deauth_11w(padapter, get_my_bssid(&(pmlmeinfo->network)), 0, (u8)key_type);
+	} else if (check_fwstate(pmlmepriv, WIFI_AP_STATE) == _TRUE) {
+		u8 updated = _FALSE;
+
+		if (key_type == 3)
+			issue_deauth_11w(padapter, bc_addr, 0, IEEE80211W_RIGHT_KEY);
+
+		/* TX unicast deauth to every client STA */
+		_enter_critical_bh(&pstapriv->sta_hash_lock, &irqL);
+		for (index = 0; index < NUM_STA; index++) {
+			psta = NULL;
+
+			phead = &(pstapriv->sta_hash[index]);
+			plist = get_next(phead);
+
+			while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) {
+				psta = LIST_CONTAINOR(plist, struct sta_info, hash_list);
+				plist = get_next(plist);
+				_rtw_memcpy(&mac_addr[psta->cmn.mac_id][0], psta->cmn.mac_addr, ETH_ALEN);
+			}
+		}
+		_exit_critical_bh(&pstapriv->sta_hash_lock, &irqL);
+
+		for (index = 0; index < macid_ctl->num && index < NUM_STA; index++) {
+			if (rtw_macid_is_used(macid_ctl, index) && !rtw_macid_is_bmc(macid_ctl, index)) {
+				if (!_rtw_memcmp(get_my_bssid(&(pmlmeinfo->network)), &mac_addr[index][0], ETH_ALEN)) {
+					if (key_type != 3)
+						issue_deauth_11w(padapter, &mac_addr[index][0], 0, (u8)key_type);
+
+					psta = rtw_get_stainfo(pstapriv, &mac_addr[index][0]);
+					if (psta && key_type != IEEE80211W_WRONG_KEY && key_type != IEEE80211W_NO_KEY) {
+						_enter_critical_bh(&pstapriv->asoc_list_lock, &irqL);
+						if (rtw_is_list_empty(&psta->asoc_list) == _FALSE) {
+							rtw_list_delete(&psta->asoc_list);
+							pstapriv->asoc_list_cnt--;
+							updated |= ap_free_sta(padapter, psta, _FALSE, WLAN_REASON_PREV_AUTH_NOT_VALID, _TRUE);
+
+						}
+						_exit_critical_bh(&pstapriv->asoc_list_lock, &irqL);
+					}
+
+					RTW_INFO("STA[%u]:"MAC_FMT"\n", index , MAC_ARG(&mac_addr[index][0]));
+				}
+			}
+		}
+
+		associated_clients_update(padapter, updated, STA_INFO_UPDATE_ALL);
+	}
+
+	return count;
+}
+
+int proc_get_tx_deauth(struct seq_file *m, void *v)
+{
+	struct net_device *dev = m->private;
+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
+
+	RTW_PRINT_SEL(m, "%s\n", __func__);
+	return 0;
+}
+
+ssize_t proc_set_tx_auth(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
+{
+	struct net_device *dev = data;
+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
+	struct mlme_ext_priv	*pmlmeext = &padapter->mlmeextpriv;
+	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
+	struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
+	struct	sta_priv *pstapriv = &padapter->stapriv;
+	struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
+	struct macid_ctl_t *macid_ctl = dvobj_to_macidctl(dvobj);
+	struct sta_info *psta;
+	_list	*plist, *phead;
+	_irqL	 irqL;
+	char tmp[16];
+	u8	mac_addr[NUM_STA][ETH_ALEN];
+	u8 bc_addr[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
+	u32 tx_auth;
+	u8 index;
+
+
+	if (count > 2) {
+		RTW_INFO("argument size is more than 2\n");
+		return -EFAULT;
+	}
+
+	if (buffer && !copy_from_user(tmp, buffer, sizeof(tmp))) {
+
+		int num = sscanf(tmp, "%x", &tx_auth);
+
+		if (num !=  1) {
+			RTW_INFO("invalid read_reg parameter!\n");
+			return count;
+		}
+		RTW_INFO("1: setnd auth, 2: send assoc request. tx_auth=%d\n", tx_auth);
+	}
+
+	if ((check_fwstate(pmlmepriv, WIFI_STATION_STATE) == _TRUE)
+	    && (check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE)) {
+		if (tx_auth == 1) {
+			/* TX unicast auth to AP */
+			issue_auth(padapter, NULL, 0);
+		} else if (tx_auth == 2) {
+			/* TX unicast auth to AP */
+			issue_assocreq(padapter);
+		}
+	}
+
+	return count;
+}
+
+int proc_get_tx_auth(struct seq_file *m, void *v)
+{
+	struct net_device *dev = m->private;
+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
+
+	RTW_PRINT_SEL(m, "%s\n", __func__);
+	return 0;
+}
+#endif /* CONFIG_IEEE80211W */
+
+#ifdef CONFIG_MCC_MODE
+int proc_get_mcc_info(struct seq_file *m, void *v)
+{
+	struct net_device *dev = m->private;
+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
+
+	dump_adapters_status(m, adapter_to_dvobj(adapter));
+	rtw_hal_dump_mcc_info(m, adapter_to_dvobj(adapter));
+	return 0;
+}
+
+int proc_get_mcc_policy_table(struct seq_file *m, void *v)
+{
+	struct net_device *dev = m->private;
+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
+
+	rtw_hal_dump_mcc_policy_table(m);
+	return 0;
+}
+
+ssize_t proc_set_mcc_enable(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
+{
+	struct net_device *dev = data;
+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
+	char tmp[255];
+	u32 en_mcc = 0;
+
+	if (NULL == buffer) {
+		RTW_INFO(FUNC_ADPT_FMT ": input buffer is NULL!\n", FUNC_ADPT_ARG(padapter));
+		return -EFAULT;
+	}
+
+	if (count < 1) {
+		RTW_INFO(FUNC_ADPT_FMT ": input length is 0!\n", FUNC_ADPT_ARG(padapter));
+		return -EFAULT;
+	}
+
+	if (count > sizeof(tmp)) {
+		RTW_INFO(FUNC_ADPT_FMT ": input length is too large\n", FUNC_ADPT_ARG(padapter));
+		rtw_warn_on(1);
+		return -EFAULT;
+	}
+
+	if (buffer && !copy_from_user(tmp, buffer, count)) {
+		struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
+		_adapter *iface = NULL;
+		u8 i = 0;
+		int num = sscanf(tmp, "%u", &en_mcc);
+
+		if (num < 1) {
+			RTW_INFO(FUNC_ADPT_FMT ": input parameters < 1\n", FUNC_ADPT_ARG(padapter));
+			return -EINVAL;
+		}
+
+		RTW_INFO("%s: en_mcc = %d\n", __func__, en_mcc);
+
+		for (i = 0; i < dvobj->iface_nums; i++) {
+			iface = dvobj->padapters[i];
+			if (!iface)
+				continue;
+			iface->registrypriv.en_mcc = en_mcc;
+		}
+	}
+
+	return count;
+}
+
+ssize_t proc_set_mcc_duration(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
+{
+	struct net_device *dev = data;
+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
+	char tmp[255];
+	u32 enable_runtime_duration = 0, mcc_duration = 0;
+
+	if (NULL == buffer) {
+		RTW_INFO(FUNC_ADPT_FMT ": input buffer is NULL!\n", FUNC_ADPT_ARG(padapter));
+		return -EFAULT;
+	}
+
+	if (count < 1) {
+		RTW_INFO(FUNC_ADPT_FMT ": input length is 0!\n", FUNC_ADPT_ARG(padapter));
+		return -EFAULT;
+	}
+
+	if (count > sizeof(tmp)) {
+		RTW_INFO(FUNC_ADPT_FMT ": input length is too large\n", FUNC_ADPT_ARG(padapter));
+		rtw_warn_on(1);
+		return -EFAULT;
+	}
+
+	if (buffer && !copy_from_user(tmp, buffer, count)) {
+		int num = sscanf(tmp, "%u %u", &enable_runtime_duration, &mcc_duration);
+
+		if (num < 1) {
+			RTW_INFO(FUNC_ADPT_FMT ": input parameters < 1\n", FUNC_ADPT_ARG(padapter));
+			return -EINVAL;
+		}
+
+		if (num > 2) {
+			RTW_INFO(FUNC_ADPT_FMT ": input parameters > 2\n", FUNC_ADPT_ARG(padapter));
+			return -EINVAL;
+		}
+
+		if (num >= 1) {
+			SET_MCC_RUNTIME_DURATION(padapter, enable_runtime_duration);
+			RTW_INFO("runtime duration:%s\n", enable_runtime_duration ? "enable":"disable");
+		}
+
+		if (num == 2) {
+			RTW_INFO("mcc duration:%d\n", mcc_duration);
+			rtw_set_mcc_duration_cmd(padapter, MCC_DURATION_DIRECET, mcc_duration);
+		}
+	}
+
+	return count;
+}
+
+ssize_t proc_set_mcc_single_tx_criteria(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
+{
+	struct net_device *dev = data;
+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
+	char tmp[255];
+	u32 mcc_single_tx_criteria = 0;
+
+	if (NULL == buffer) {
+		RTW_INFO(FUNC_ADPT_FMT ": input buffer is NULL!\n", FUNC_ADPT_ARG(padapter));
+		return -EFAULT;
+	}
+
+	if (count < 1) {
+		RTW_INFO(FUNC_ADPT_FMT ": input length is 0!\n", FUNC_ADPT_ARG(padapter));
+		return -EFAULT;
+	}
+
+	if (count > sizeof(tmp)) {
+		RTW_INFO(FUNC_ADPT_FMT ": input length is too large\n", FUNC_ADPT_ARG(padapter));
+		rtw_warn_on(1);
+		return -EFAULT;
+	}
+
+	if (buffer && !copy_from_user(tmp, buffer, count)) {
+		struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
+		_adapter *iface = NULL;
+		u8 i = 0;
+		int num = sscanf(tmp, "%u", &mcc_single_tx_criteria);
+
+		if (num < 1) {
+			RTW_INFO(FUNC_ADPT_FMT ": input parameters < 1\n", FUNC_ADPT_ARG(padapter));
+			return -EINVAL;
+		}
+
+		RTW_INFO("%s: mcc_single_tx_criteria = %d\n", __func__, mcc_single_tx_criteria);
+
+		for (i = 0; i < dvobj->iface_nums; i++) {
+			iface = dvobj->padapters[i];
+			if (!iface)
+				continue;
+			iface->registrypriv.rtw_mcc_single_tx_cri = mcc_single_tx_criteria;
+		}
+
+
+	}
+
+	return count;
+}
+
+
+ssize_t proc_set_mcc_ap_bw20_target_tp(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
+{
+	struct net_device *dev = data;
+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
+	char tmp[255];
+	u32 mcc_ap_bw20_target_tp = 0;
+
+	if (NULL == buffer) {
+		RTW_INFO(FUNC_ADPT_FMT ": input buffer is NULL!\n", FUNC_ADPT_ARG(padapter));
+		return -EFAULT;
+	}
+
+	if (count < 1) {
+		RTW_INFO(FUNC_ADPT_FMT ": input length is 0!\n", FUNC_ADPT_ARG(padapter));
+		return -EFAULT;
+	}
+
+	if (count > sizeof(tmp)) {
+		RTW_INFO(FUNC_ADPT_FMT ": input length is too large\n", FUNC_ADPT_ARG(padapter));
+		rtw_warn_on(1);
+		return -EFAULT;
+	}
+
+	if (buffer && !copy_from_user(tmp, buffer, count)) {
+		int num = sscanf(tmp, "%u", &mcc_ap_bw20_target_tp);
+
+		if (num < 1) {
+			RTW_INFO(FUNC_ADPT_FMT ": input parameters < 1\n", FUNC_ADPT_ARG(padapter));
+			return -EINVAL;
+		}
+
+		RTW_INFO("%s: mcc_ap_bw20_target_tp = %d\n", __func__, mcc_ap_bw20_target_tp);
+
+		padapter->registrypriv.rtw_mcc_ap_bw20_target_tx_tp = mcc_ap_bw20_target_tp;
+
+
+	}
+
+	return count;
+}
+
+ssize_t proc_set_mcc_ap_bw40_target_tp(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
+{
+	struct net_device *dev = data;
+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
+	char tmp[255];
+	u32 mcc_ap_bw40_target_tp = 0;
+
+	if (NULL == buffer) {
+		RTW_INFO(FUNC_ADPT_FMT ": input buffer is NULL!\n", FUNC_ADPT_ARG(padapter));
+		return -EFAULT;
+	}
+
+	if (count < 1) {
+		RTW_INFO(FUNC_ADPT_FMT ": input length is 0!\n", FUNC_ADPT_ARG(padapter));
+		return -EFAULT;
+	}
+
+	if (count > sizeof(tmp)) {
+		RTW_INFO(FUNC_ADPT_FMT ": input length is too large\n", FUNC_ADPT_ARG(padapter));
+		rtw_warn_on(1);
+		return -EFAULT;
+	}
+
+	if (buffer && !copy_from_user(tmp, buffer, count)) {
+		int num = sscanf(tmp, "%u", &mcc_ap_bw40_target_tp);
+
+		if (num < 1) {
+			RTW_INFO(FUNC_ADPT_FMT ": input parameters < 1\n", FUNC_ADPT_ARG(padapter));
+			return -EINVAL;
+		}
+
+		RTW_INFO("%s: mcc_ap_bw40_target_tp = %d\n", __func__, mcc_ap_bw40_target_tp);
+
+		padapter->registrypriv.rtw_mcc_ap_bw40_target_tx_tp = mcc_ap_bw40_target_tp;
+
+
+	}
+
+	return count;
+}
+
+ssize_t proc_set_mcc_ap_bw80_target_tp(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
+{
+	struct net_device *dev = data;
+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
+	char tmp[255];
+	u32 mcc_ap_bw80_target_tp = 0;
+
+	if (NULL == buffer) {
+		RTW_INFO(FUNC_ADPT_FMT ": input buffer is NULL!\n", FUNC_ADPT_ARG(padapter));
+		return -EFAULT;
+	}
+
+	if (count < 1) {
+		RTW_INFO(FUNC_ADPT_FMT ": input length is 0!\n", FUNC_ADPT_ARG(padapter));
+		return -EFAULT;
+	}
+
+	if (count > sizeof(tmp)) {
+		RTW_INFO(FUNC_ADPT_FMT ": input length is too large\n", FUNC_ADPT_ARG(padapter));
+		rtw_warn_on(1);
+		return -EFAULT;
+	}
+
+	if (buffer && !copy_from_user(tmp, buffer, count)) {
+		int num = sscanf(tmp, "%u", &mcc_ap_bw80_target_tp);
+
+		if (num < 1) {
+			RTW_INFO(FUNC_ADPT_FMT ": input parameters < 1\n", FUNC_ADPT_ARG(padapter));
+			return -EINVAL;
+		}
+
+		RTW_INFO("%s: mcc_ap_bw80_target_tp = %d\n", __func__, mcc_ap_bw80_target_tp);
+
+		padapter->registrypriv.rtw_mcc_ap_bw80_target_tx_tp = mcc_ap_bw80_target_tp;
+
+
+	}
+
+	return count;
+}
+
+ssize_t proc_set_mcc_sta_bw20_target_tp(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
+{
+	struct net_device *dev = data;
+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
+	char tmp[255];
+	u32 mcc_sta_bw20_target_tp = 0;
+
+	if (NULL == buffer) {
+		RTW_INFO(FUNC_ADPT_FMT ": input buffer is NULL!\n", FUNC_ADPT_ARG(padapter));
+		return -EFAULT;
+	}
+
+	if (count < 1) {
+		RTW_INFO(FUNC_ADPT_FMT ": input length is 0!\n", FUNC_ADPT_ARG(padapter));
+		return -EFAULT;
+	}
+
+	if (count > sizeof(tmp)) {
+		RTW_INFO(FUNC_ADPT_FMT ": input length is too large\n", FUNC_ADPT_ARG(padapter));
+		rtw_warn_on(1);
+		return -EFAULT;
+	}
+
+	if (buffer && !copy_from_user(tmp, buffer, count)) {
+		int num = sscanf(tmp, "%u", &mcc_sta_bw20_target_tp);
+
+		if (num < 1) {
+			RTW_INFO(FUNC_ADPT_FMT ": input parameters < 1\n", FUNC_ADPT_ARG(padapter));
+			return -EINVAL;
+		}
+
+		RTW_INFO("%s: mcc_sta_bw20_target_tp = %d\n", __func__, mcc_sta_bw20_target_tp);
+
+		padapter->registrypriv.rtw_mcc_sta_bw20_target_tx_tp = mcc_sta_bw20_target_tp;
+
+
+	}
+
+	return count;
+}
+
+ssize_t proc_set_mcc_sta_bw40_target_tp(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
+{
+	struct net_device *dev = data;
+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
+	char tmp[255];
+	u32 mcc_sta_bw40_target_tp = 0;
+
+	if (NULL == buffer) {
+		RTW_INFO(FUNC_ADPT_FMT ": input buffer is NULL!\n", FUNC_ADPT_ARG(padapter));
+		return -EFAULT;
+	}
+
+	if (count < 1) {
+		RTW_INFO(FUNC_ADPT_FMT ": input length is 0!\n", FUNC_ADPT_ARG(padapter));
+		return -EFAULT;
+	}
+
+	if (count > sizeof(tmp)) {
+		RTW_INFO(FUNC_ADPT_FMT ": input length is too large\n", FUNC_ADPT_ARG(padapter));
+		rtw_warn_on(1);
+		return -EFAULT;
+	}
+
+	if (buffer && !copy_from_user(tmp, buffer, count)) {
+		int num = sscanf(tmp, "%u", &mcc_sta_bw40_target_tp);
+
+		if (num < 1) {
+			RTW_INFO(FUNC_ADPT_FMT ": input parameters < 1\n", FUNC_ADPT_ARG(padapter));
+			return -EINVAL;
+		}
+
+		RTW_INFO("%s: mcc_sta_bw40_target_tp = %d\n", __func__, mcc_sta_bw40_target_tp);
+
+		padapter->registrypriv.rtw_mcc_sta_bw40_target_tx_tp = mcc_sta_bw40_target_tp;
+
+
+	}
+
+	return count;
+}
+
+ssize_t proc_set_mcc_sta_bw80_target_tp(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
+{
+	struct net_device *dev = data;
+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
+	char tmp[255];
+	u32 mcc_sta_bw80_target_tp = 0;
+
+	if (NULL == buffer) {
+		RTW_INFO(FUNC_ADPT_FMT ": input buffer is NULL!\n", FUNC_ADPT_ARG(padapter));
+		return -EFAULT;
+	}
+
+	if (count < 1) {
+		RTW_INFO(FUNC_ADPT_FMT ": input length is 0!\n", FUNC_ADPT_ARG(padapter));
+		return -EFAULT;
+	}
+
+	if (count > sizeof(tmp)) {
+		RTW_INFO(FUNC_ADPT_FMT ": input length is too large\n", FUNC_ADPT_ARG(padapter));
+		rtw_warn_on(1);
+		return -EFAULT;
+	}
+
+	if (buffer && !copy_from_user(tmp, buffer, count)) {
+		int num = sscanf(tmp, "%u", &mcc_sta_bw80_target_tp);
+
+		if (num < 1) {
+			RTW_INFO(FUNC_ADPT_FMT ": input parameters < 1\n", FUNC_ADPT_ARG(padapter));
+			return -EINVAL;
+		}
+
+		RTW_INFO("%s: mcc_sta_bw80_target_tp = %d\n", __func__, mcc_sta_bw80_target_tp);
+
+		padapter->registrypriv.rtw_mcc_sta_bw80_target_tx_tp = mcc_sta_bw80_target_tp;
+
+
+	}
+
+	return count;
+}
+#endif /* CONFIG_MCC_MODE */
+
+int proc_get_ack_timeout(struct seq_file *m, void *v)
+{
+	struct net_device *dev = m->private;
+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
+	u8 ack_timeout_val;
+#ifdef CONFIG_RTL8821C
+	u8 ack_timeout_val_cck;
+#endif
+
+	ack_timeout_val = rtw_read8(padapter, REG_ACKTO);
+
+#ifdef CONFIG_RTL8821C
+	ack_timeout_val_cck = rtw_read8(padapter, REG_ACKTO_CCK_8821C);
+	RTW_PRINT_SEL(m, "Current CCK packet ACK Timeout = %d us (0x%x).\n", ack_timeout_val_cck, ack_timeout_val_cck);
+	RTW_PRINT_SEL(m, "Current non-CCK packet ACK Timeout = %d us (0x%x).\n", ack_timeout_val, ack_timeout_val);
+#else
+	RTW_PRINT_SEL(m, "Current ACK Timeout = %d us (0x%x).\n", ack_timeout_val, ack_timeout_val);
+#endif
+
+	return 0;
+}
+
+ssize_t proc_set_ack_timeout(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
+{
+	struct net_device *dev = data;
+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
+	char tmp[32];
+	u32 ack_timeout_ms, ack_timeout_ms_cck;
+
+	if (count > sizeof(tmp)) {
+		rtw_warn_on(1);
+		return -EFAULT;
+	}
+
+	if (buffer && !copy_from_user(tmp, buffer, count)) {
+		int num = sscanf(tmp, "%u %u", &ack_timeout_ms, &ack_timeout_ms_cck);
+
+#ifdef CONFIG_RTL8821C
+		if (num < 2) {
+			RTW_INFO(FUNC_ADPT_FMT ": input parameters < 2\n", FUNC_ADPT_ARG(padapter));
+			return -EINVAL;
+		}
+#else
+		if (num < 1) {
+			RTW_INFO(FUNC_ADPT_FMT ": input parameters < 1\n", FUNC_ADPT_ARG(padapter));
+			return -EINVAL;
+		}
+#endif
+		/* This register sets the Ack time out value after Tx unicast packet. It is in units of us. */
+		rtw_write8(padapter, REG_ACKTO, (u8)ack_timeout_ms);
+
+#ifdef CONFIG_RTL8821C
+		/* This register sets the Ack time out value after Tx unicast CCK packet. It is in units of us. */
+		rtw_write8(padapter, REG_ACKTO_CCK_8821C, (u8)ack_timeout_ms_cck);
+		RTW_INFO("Set CCK packet ACK Timeout to %d us.\n", ack_timeout_ms_cck);
+		RTW_INFO("Set non-CCK packet ACK Timeout to %d us.\n", ack_timeout_ms);
+#else
+		RTW_INFO("Set ACK Timeout to %d us.\n", ack_timeout_ms);
+#endif
+	}
+
+	return count;
+}
+
+ssize_t proc_set_fw_offload(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
+{
+	struct net_device *dev = data;
+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
+	_adapter *pri_adapter = GET_PRIMARY_ADAPTER(adapter);
+	HAL_DATA_TYPE *hal = GET_HAL_DATA(adapter);
+	char tmp[32];
+	u32 iqk_offload_enable = 0, ch_switch_offload_enable = 0;
+
+	if (buffer == NULL) {
+		RTW_INFO("input buffer is NULL!\n");
+		return -EFAULT;
+	}
+
+	if (count < 1) {
+		RTW_INFO("input length is 0!\n");
+		return -EFAULT;
+	}
+
+	if (count > sizeof(tmp)) {
+		RTW_INFO("input length is too large\n");
+		rtw_warn_on(1);
+		return -EFAULT;
+	}
+
+	if (buffer && !copy_from_user(tmp, buffer, count)) {
+		int num = sscanf(tmp, "%d %d", &iqk_offload_enable, &ch_switch_offload_enable);
+
+		if (num < 2) {
+			RTW_INFO("input parameters < 1\n");
+			return -EINVAL;
+		}
+
+		if (hal->RegIQKFWOffload != iqk_offload_enable) {
+			hal->RegIQKFWOffload = iqk_offload_enable;
+			rtw_hal_update_iqk_fw_offload_cap(pri_adapter);
+		}
+
+		if (hal->ch_switch_offload != ch_switch_offload_enable)
+			hal->ch_switch_offload = ch_switch_offload_enable;
+	}
+
+	return count;
+}
+
+int proc_get_fw_offload(struct seq_file *m, void *v)
+{
+	struct net_device *dev = m->private;
+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
+	HAL_DATA_TYPE *hal = GET_HAL_DATA(adapter);
+
+
+	RTW_PRINT_SEL(m, "IQK FW offload:%s\n", hal->RegIQKFWOffload?"enable":"disable");
+	RTW_PRINT_SEL(m, "Channel switch FW offload:%s\n", hal->ch_switch_offload?"enable":"disable");
+	return 0;
+}
+#ifdef CONFIG_FW_HANDLE_TXBCN
+extern void rtw_hal_set_fw_ap_bcn_offload_cmd(_adapter *adapter, bool fw_bcn_en, u8 tbtt_rpt_map);
+ssize_t proc_set_fw_tbtt_rpt(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
+{
+	struct net_device *dev = data;
+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
+	char tmp[32];
+	u32 fw_tbtt_rpt, fw_bcn_offload;
+
+
+	if (buffer == NULL) {
+		RTW_INFO("input buffer is NULL!\n");
+		return -EFAULT;
+	}
+
+	if (count < 1) {
+		RTW_INFO("input length is 0!\n");
+		return -EFAULT;
+	}
+
+	if (count > sizeof(tmp)) {
+		RTW_INFO("input length is too large\n");
+		rtw_warn_on(1);
+		return -EFAULT;
+	}
+
+	if (buffer && !copy_from_user(tmp, buffer, count)) {
+		int num = sscanf(tmp, "%d %x",&fw_bcn_offload, &fw_tbtt_rpt);
+
+		if (num < 2) {
+			RTW_INFO("input parameters < 2\n");
+			return -EINVAL;
+		}
+		rtw_hal_set_fw_ap_bcn_offload_cmd(adapter, fw_bcn_offload, fw_tbtt_rpt);
+	}
+
+	return count;
+}
+
+int proc_get_fw_tbtt_rpt(struct seq_file *m, void *v)
+{
+	struct net_device *dev = m->private;
+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
+	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
+
+	RTW_PRINT_SEL(m, "FW BCN offload:%s\n", dvobj->fw_bcn_offload ? "enable" : "disable");
+	RTW_PRINT_SEL(m, "FW TBTT RPT:%x\n", dvobj->vap_tbtt_rpt_map);
+	return 0;
+}
+
+#endif
+
+#ifdef CONFIG_DBG_RF_CAL
+int proc_get_iqk_info(struct seq_file *m, void *v)
+{
+	struct net_device *dev = m->private;
+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
+
+	return 0;
+}
+
+ssize_t proc_set_iqk(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
+{
+	struct net_device *dev = data;
+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
+	char tmp[32];
+	u32 recovery, clear, segment;
+
+	if (count < 1)
+		return -EFAULT;
+
+	if (count > sizeof(tmp)) {
+		rtw_warn_on(1);
+		return -EFAULT;
+	}
+
+	if (buffer && !copy_from_user(tmp, buffer, count)) {
+
+		int num = sscanf(tmp, "%d %d %d", &recovery, &clear, &segment);
+
+		if (num != 3) {
+			RTW_INFO("Invalid format\n");
+			return count;
+		}
+
+		rtw_hal_iqk_test(padapter, recovery, clear, segment);
+	}
+
+	return count;
+
+}
+
+int proc_get_lck_info(struct seq_file *m, void *v)
+{
+	struct net_device *dev = m->private;
+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
+
+	return 0;
+}
+
+ssize_t proc_set_lck(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
+{
+	struct net_device *dev = data;
+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
+	char tmp[32];
+	u32 trigger;
+
+	if (count < 1)
+		return -EFAULT;
+
+	if (count > sizeof(tmp)) {
+		rtw_warn_on(1);
+		return -EFAULT;
+	}
+
+	if (buffer && !copy_from_user(tmp, buffer, count)) {
+
+		int num = sscanf(tmp, "%d", &trigger);
+
+		if (num != 1) {
+			RTW_INFO("Invalid format\n");
+			return count;
+		}
+
+		rtw_hal_lck_test(padapter);
+	}
+
+	return count;
+}
+#endif /* CONFIG_DBG_RF_CAL */
+
+#ifdef CONFIG_LPS_CHK_BY_TP
+ssize_t proc_set_lps_chk_tp(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
+{
+	struct net_device *dev = data;
+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
+	struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(adapter);
+	char tmp[32];
+	u32 enable = 0;
+	u32 lps_tx_tp = 0, lps_rx_tp = 0, lps_bi_tp = 0;
+	int lps_chk_cnt_th = 0;
+	u32 lps_tx_pkts = 0, lps_rx_pkts = 0;
+
+	if (buffer == NULL) {
+		RTW_INFO("input buffer is NULL!\n");
+		return -EFAULT;
+	}
+
+	if (count < 1) {
+		RTW_INFO("input length is 0!\n");
+		return -EFAULT;
+	}
+
+	if (count > sizeof(tmp)) {
+		RTW_INFO("input length is too large\n");
+		rtw_warn_on(1);
+		return -EFAULT;
+	}
+
+	if (buffer && !copy_from_user(tmp, buffer, count)) {
+		int num = sscanf(tmp, "%u %u %u %u %d %u %u",
+			&enable, &lps_tx_tp, &lps_rx_tp, &lps_bi_tp,
+			&lps_chk_cnt_th, &lps_tx_pkts, &lps_rx_pkts);
+
+		if (num < 1) {
+			RTW_INFO("input parameters < 1\n");
+			return -EINVAL;
+		}
+		pwrpriv->lps_chk_by_tp = enable;
+
+		if (lps_tx_tp) {
+			pwrpriv->lps_tx_tp_th = lps_tx_tp;
+			pwrpriv->lps_rx_tp_th = lps_tx_tp;
+			pwrpriv->lps_bi_tp_th = lps_tx_tp;
+		}
+		if (lps_rx_tp)
+			pwrpriv->lps_rx_tp_th = lps_rx_tp;
+		if (lps_bi_tp)
+			pwrpriv->lps_bi_tp_th = lps_bi_tp;
+
+		if (lps_chk_cnt_th)
+			pwrpriv->lps_chk_cnt_th = lps_chk_cnt_th;
+
+		if (lps_tx_pkts)
+			pwrpriv->lps_tx_pkts = lps_tx_pkts;
+
+		if (lps_rx_pkts)
+			pwrpriv->lps_rx_pkts = lps_rx_pkts;
+
+		RTW_INFO("%s lps_chk_by_tp:%s , lps_tx_tp_th:%d, lps_tx_tp_th:%d, lps_bi_tp:%d\n",
+			__func__, pwrpriv->lps_chk_by_tp ? "Y" : "N",
+			pwrpriv->lps_tx_tp_th, pwrpriv->lps_tx_tp_th, pwrpriv->lps_bi_tp_th);
+		RTW_INFO("%s lps_chk_cnt_th:%d , lps_tx_pkts:%d, lps_rx_pkts:%d\n",
+			__func__, pwrpriv->lps_chk_cnt_th, pwrpriv->lps_tx_pkts, pwrpriv->lps_rx_pkts);
+	}
+
+	return count;
+}
+
+int proc_get_lps_chk_tp(struct seq_file *m, void *v)
+{
+	struct net_device *dev = m->private;
+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
+	struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(adapter);
+
+	RTW_PRINT_SEL(m, "LPS chk by tp - %s\n", pwrpriv->lps_chk_by_tp ? "enable" : "disable");
+	RTW_PRINT_SEL(m, "LPS Tx TP TH - %d(Mbps)\n", pwrpriv->lps_tx_tp_th);
+	RTW_PRINT_SEL(m, "LPS Rx TP TH - %d(Mbps)\n", pwrpriv->lps_rx_tp_th);
+	RTW_PRINT_SEL(m, "LPS BI TP TH - %d(Mbps)\n", pwrpriv->lps_bi_tp_th);
+
+	RTW_PRINT_SEL(m, "LPS CHK CNT - %d\n", pwrpriv->lps_chk_cnt_th);
+	RTW_PRINT_SEL(m, "LPS Tx PKTs - %d\n", pwrpriv->lps_tx_pkts);
+	RTW_PRINT_SEL(m, "LPS Rx PKTs - %d\n", pwrpriv->lps_rx_pkts);
+	return 0;
+}
+#endif
+
+#endif /* CONFIG_PROC_DEBUG */
+#define RTW_BUFDUMP_BSIZE		16
+#if 1
+inline void RTW_BUF_DUMP_SEL(uint _loglevel, void *sel, u8 *_titlestring,
+					bool _idx_show, const u8 *_hexdata, int _hexdatalen)
+{
+#ifdef CONFIG_RTW_DEBUG
+	int __i;
+	u8 *ptr = (u8 *)_hexdata;
+
+	if (_loglevel <= rtw_drv_log_level) {
+		if (_titlestring) {
+			if (sel == RTW_DBGDUMP)
+				RTW_PRINT("");
+			_RTW_PRINT_SEL(sel, "%s", _titlestring);
+			if (_hexdatalen >= RTW_BUFDUMP_BSIZE)
+				_RTW_PRINT_SEL(sel, "\n");
+		}
+
+		for (__i = 0; __i < _hexdatalen; __i++) {
+			if (((__i % RTW_BUFDUMP_BSIZE) == 0) && (_hexdatalen >= RTW_BUFDUMP_BSIZE)) {
+				if (sel == RTW_DBGDUMP)
+					RTW_PRINT("");
+				if (_idx_show)
+					_RTW_PRINT_SEL(sel, "0x%03X: ", __i);
+			}
+			_RTW_PRINT_SEL(sel, "%02X%s", ptr[__i], (((__i + 1) % 4) == 0) ? "  " : " ");
+			if ((__i + 1 < _hexdatalen) && ((__i + 1) % RTW_BUFDUMP_BSIZE) == 0)
+				_RTW_PRINT_SEL(sel, "\n");
+		}
+		_RTW_PRINT_SEL(sel, "\n");
+	}
+#endif
+}
+#else
+inline void _RTW_STR_DUMP_SEL(void *sel, char *str_out)
+{
+	if (sel == RTW_DBGDUMP)
+		_dbgdump("%s\n", str_out);
+	#if defined(_seqdump)
+	else
+		_seqdump(sel, "%s\n", str_out);
+	#endif /*_seqdump*/
+}
+inline void RTW_BUF_DUMP_SEL(uint _loglevel, void *sel, u8 *_titlestring,
+					bool _idx_show, u8 *_hexdata, int _hexdatalen)
+{
+	int __i, len;
+	int __j, idx;
+	int block_num, remain_byte;
+	char str_out[128] = {'\0'};
+	char str_val[32] = {'\0'};
+	char *p = NULL;
+	u8 *ptr = (u8 *)_hexdata;
+
+	if (_loglevel <= rtw_drv_log_level) {
+		/*dump title*/
+		p = &str_out[0];
+		if (_titlestring) {
+			if (sel == RTW_DBGDUMP) {
+				len = snprintf(str_val, sizeof(str_val), "%s", DRIVER_PREFIX);
+				strncpy(p, str_val, len);
+				p += len;
+			}
+			len = snprintf(str_val, sizeof(str_val), "%s", _titlestring);
+			strncpy(p, str_val, len);
+			p += len;
+		}
+		if (p != &str_out[0]) {
+			_RTW_STR_DUMP_SEL(sel, str_out);
+			_rtw_memset(&str_out, '\0', sizeof(str_out));
+		}
+
+		/*dump buffer*/
+		block_num = _hexdatalen / RTW_BUFDUMP_BSIZE;
+		remain_byte = _hexdatalen % RTW_BUFDUMP_BSIZE;
+		for (__i = 0; __i < block_num; __i++) {
+			p = &str_out[0];
+			if (sel == RTW_DBGDUMP) {
+				len = snprintf(str_val, sizeof(str_val), "%s", DRIVER_PREFIX);
+				strncpy(p, str_val, len);
+				p += len;
+			}
+			if (_idx_show) {
+				len = snprintf(str_val, sizeof(str_val), "0x%03X: ", __i * RTW_BUFDUMP_BSIZE);
+				strncpy(p, str_val, len);
+				p += len;
+			}
+			for (__j =0; __j < RTW_BUFDUMP_BSIZE; __j++) {
+				idx = __i * RTW_BUFDUMP_BSIZE + __j;
+				len = snprintf(str_val, sizeof(str_val), "%02X%s", ptr[idx], (((__j + 1) % 4) == 0) ? "  " : " ");
+				strncpy(p, str_val, len);
+				p += len;
+			}
+			_RTW_STR_DUMP_SEL(sel, str_out);
+			_rtw_memset(&str_out, '\0', sizeof(str_out));
+		}
+
+		p = &str_out[0];
+		if ((sel == RTW_DBGDUMP) && remain_byte) {
+			len = snprintf(str_val, sizeof(str_val), "%s", DRIVER_PREFIX);
+			strncpy(p, str_val, len);
+			p += len;
+		}
+		if (_idx_show && remain_byte) {
+			len = snprintf(str_val, sizeof(str_val), "0x%03X: ", block_num * RTW_BUFDUMP_BSIZE);
+			strncpy(p, str_val, len);
+			p += len;
+		}
+		for (__i = 0; __i < remain_byte; __i++) {
+			idx = block_num * RTW_BUFDUMP_BSIZE + __i;
+			len = snprintf(str_val, sizeof(str_val), "%02X%s", ptr[idx], (((__i + 1) % 4) == 0) ? "  " : " ");
+			strncpy(p, str_val, len);
+			p += len;
+		}
+		_RTW_STR_DUMP_SEL(sel, str_out);
+	}
+}
+
+#endif
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/core/rtw_eeprom.c linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/core/rtw_eeprom.c
--- linux-5.6.3/3rdparty/rtl8821ce/core/rtw_eeprom.c	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/core/rtw_eeprom.c	2020-04-10 16:35:06.773658060 +0300
@@ -0,0 +1,369 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#define _RTW_EEPROM_C_
+
+#include <drv_conf.h>
+#include <osdep_service.h>
+#include <drv_types.h>
+
+void up_clk(_adapter	*padapter,	 u16 *x)
+{
+	*x = *x | _EESK;
+	rtw_write8(padapter, EE_9346CR, (u8)*x);
+	rtw_udelay_os(CLOCK_RATE);
+
+
+}
+
+void down_clk(_adapter	*padapter, u16 *x)
+{
+	*x = *x & ~_EESK;
+	rtw_write8(padapter, EE_9346CR, (u8)*x);
+	rtw_udelay_os(CLOCK_RATE);
+}
+
+void shift_out_bits(_adapter *padapter, u16 data, u16 count)
+{
+	u16 x, mask;
+
+	if (rtw_is_surprise_removed(padapter)) {
+		goto out;
+	}
+	mask = 0x01 << (count - 1);
+	x = rtw_read8(padapter, EE_9346CR);
+
+	x &= ~(_EEDO | _EEDI);
+
+	do {
+		x &= ~_EEDI;
+		if (data & mask)
+			x |= _EEDI;
+		if (rtw_is_surprise_removed(padapter)) {
+			goto out;
+		}
+		rtw_write8(padapter, EE_9346CR, (u8)x);
+		rtw_udelay_os(CLOCK_RATE);
+		up_clk(padapter, &x);
+		down_clk(padapter, &x);
+		mask = mask >> 1;
+	} while (mask);
+	if (rtw_is_surprise_removed(padapter)) {
+		goto out;
+	}
+	x &= ~_EEDI;
+	rtw_write8(padapter, EE_9346CR, (u8)x);
+out:
+	return;
+}
+
+u16 shift_in_bits(_adapter *padapter)
+{
+	u16 x, d = 0, i;
+	if (rtw_is_surprise_removed(padapter)) {
+		goto out;
+	}
+	x = rtw_read8(padapter, EE_9346CR);
+
+	x &= ~(_EEDO | _EEDI);
+	d = 0;
+
+	for (i = 0; i < 16; i++) {
+		d = d << 1;
+		up_clk(padapter, &x);
+		if (rtw_is_surprise_removed(padapter)) {
+			goto out;
+		}
+		x = rtw_read8(padapter, EE_9346CR);
+
+		x &= ~(_EEDI);
+		if (x & _EEDO)
+			d |= 1;
+
+		down_clk(padapter, &x);
+	}
+out:
+
+	return d;
+}
+
+void standby(_adapter	*padapter)
+{
+	u8   x;
+	x = rtw_read8(padapter, EE_9346CR);
+
+	x &= ~(_EECS | _EESK);
+	rtw_write8(padapter, EE_9346CR, x);
+
+	rtw_udelay_os(CLOCK_RATE);
+	x |= _EECS;
+	rtw_write8(padapter, EE_9346CR, x);
+	rtw_udelay_os(CLOCK_RATE);
+}
+
+u16 wait_eeprom_cmd_done(_adapter *padapter)
+{
+	u8	x;
+	u16	i, res = _FALSE;
+	standby(padapter);
+	for (i = 0; i < 200; i++) {
+		x = rtw_read8(padapter, EE_9346CR);
+		if (x & _EEDO) {
+			res = _TRUE;
+			goto exit;
+		}
+		rtw_udelay_os(CLOCK_RATE);
+	}
+exit:
+	return res;
+}
+
+void eeprom_clean(_adapter *padapter)
+{
+	u16 x;
+	if (rtw_is_surprise_removed(padapter)) {
+		goto out;
+	}
+	x = rtw_read8(padapter, EE_9346CR);
+	if (rtw_is_surprise_removed(padapter)) {
+		goto out;
+	}
+	x &= ~(_EECS | _EEDI);
+	rtw_write8(padapter, EE_9346CR, (u8)x);
+	if (rtw_is_surprise_removed(padapter)) {
+		goto out;
+	}
+	up_clk(padapter, &x);
+	if (rtw_is_surprise_removed(padapter)) {
+		goto out;
+	}
+	down_clk(padapter, &x);
+out:
+	return;
+}
+
+void eeprom_write16(_adapter *padapter, u16 reg, u16 data)
+{
+	u8 x;
+#ifdef CONFIG_RTL8712
+	u8	tmp8_ori, tmp8_new, tmp8_clk_ori, tmp8_clk_new;
+	tmp8_ori = rtw_read8(padapter, 0x102502f1);
+	tmp8_new = tmp8_ori & 0xf7;
+	if (tmp8_ori != tmp8_new) {
+		rtw_write8(padapter, 0x102502f1, tmp8_new);
+	}
+	tmp8_clk_ori = rtw_read8(padapter, 0x10250003);
+	tmp8_clk_new = tmp8_clk_ori | 0x20;
+	if (tmp8_clk_new != tmp8_clk_ori) {
+		rtw_write8(padapter, 0x10250003, tmp8_clk_new);
+	}
+#endif
+
+	x = rtw_read8(padapter, EE_9346CR);
+
+	x &= ~(_EEDI | _EEDO | _EESK | _EEM0);
+	x |= _EEM1 | _EECS;
+	rtw_write8(padapter, EE_9346CR, x);
+
+	shift_out_bits(padapter, EEPROM_EWEN_OPCODE, 5);
+
+	if (padapter->EepromAddressSize == 8)	/* CF+ and SDIO */
+		shift_out_bits(padapter, 0, 6);
+	else									/* USB */
+		shift_out_bits(padapter, 0, 4);
+
+	standby(padapter);
+
+	/* Commented out by rcnjko, 2004.0
+	 * 	  Erase this particular word.  Write the erase opcode and register
+	 *    number in that order. The opcode is 3bits in length; reg is 6 bits long. */
+/*	shift_out_bits(Adapter, EEPROM_ERASE_OPCODE, 3);
+ *	shift_out_bits(Adapter, reg, Adapter->EepromAddressSize);
+ *
+ *	if (wait_eeprom_cmd_done(Adapter ) == FALSE)
+ *	{
+ *		return;
+ *	} */
+
+
+	standby(padapter);
+
+	/* write the new word to the EEPROM */
+
+	/* send the write opcode the EEPORM */
+	shift_out_bits(padapter, EEPROM_WRITE_OPCODE, 3);
+
+	/* select which word in the EEPROM that we are writing to. */
+	shift_out_bits(padapter, reg, padapter->EepromAddressSize);
+
+	/* write the data to the selected EEPROM word. */
+	shift_out_bits(padapter, data, 16);
+
+	if (wait_eeprom_cmd_done(padapter) == _FALSE)
+
+		goto exit;
+
+	standby(padapter);
+
+	shift_out_bits(padapter, EEPROM_EWDS_OPCODE, 5);
+	shift_out_bits(padapter, reg, 4);
+
+	eeprom_clean(padapter);
+exit:
+#ifdef CONFIG_RTL8712
+	if (tmp8_clk_new != tmp8_clk_ori)
+		rtw_write8(padapter, 0x10250003, tmp8_clk_ori);
+	if (tmp8_new != tmp8_ori)
+		rtw_write8(padapter, 0x102502f1, tmp8_ori);
+
+#endif
+	return;
+}
+
+u16 eeprom_read16(_adapter *padapter, u16 reg)  /* ReadEEprom */
+{
+
+	u16 x;
+	u16 data = 0;
+#ifdef CONFIG_RTL8712
+	u8	tmp8_ori, tmp8_new, tmp8_clk_ori, tmp8_clk_new;
+	tmp8_ori = rtw_read8(padapter, 0x102502f1);
+	tmp8_new = tmp8_ori & 0xf7;
+	if (tmp8_ori != tmp8_new) {
+		rtw_write8(padapter, 0x102502f1, tmp8_new);
+	}
+	tmp8_clk_ori = rtw_read8(padapter, 0x10250003);
+	tmp8_clk_new = tmp8_clk_ori | 0x20;
+	if (tmp8_clk_new != tmp8_clk_ori) {
+		rtw_write8(padapter, 0x10250003, tmp8_clk_new);
+	}
+#endif
+
+	if (rtw_is_surprise_removed(padapter)) {
+		goto out;
+	}
+	/* select EEPROM, reset bits, set _EECS */
+	x = rtw_read8(padapter, EE_9346CR);
+
+	if (rtw_is_surprise_removed(padapter)) {
+		goto out;
+	}
+
+	x &= ~(_EEDI | _EEDO | _EESK | _EEM0);
+	x |= _EEM1 | _EECS;
+	rtw_write8(padapter, EE_9346CR, (unsigned char)x);
+
+	/* write the read opcode and register number in that order */
+	/* The opcode is 3bits in length, reg is 6 bits long */
+	shift_out_bits(padapter, EEPROM_READ_OPCODE, 3);
+	shift_out_bits(padapter, reg, padapter->EepromAddressSize);
+
+	/* Now read the data (16 bits) in from the selected EEPROM word */
+	data = shift_in_bits(padapter);
+
+	eeprom_clean(padapter);
+out:
+#ifdef CONFIG_RTL8712
+	if (tmp8_clk_new != tmp8_clk_ori)
+		rtw_write8(padapter, 0x10250003, tmp8_clk_ori);
+	if (tmp8_new != tmp8_ori)
+		rtw_write8(padapter, 0x102502f1, tmp8_ori);
+
+#endif
+	return data;
+
+
+}
+
+
+
+
+/* From even offset */
+void eeprom_read_sz(_adapter *padapter, u16 reg, u8 *data, u32 sz)
+{
+
+	u16 x, data16;
+	u32 i;
+	if (rtw_is_surprise_removed(padapter)) {
+		goto out;
+	}
+	/* select EEPROM, reset bits, set _EECS */
+	x = rtw_read8(padapter, EE_9346CR);
+
+	if (rtw_is_surprise_removed(padapter)) {
+		goto out;
+	}
+
+	x &= ~(_EEDI | _EEDO | _EESK | _EEM0);
+	x |= _EEM1 | _EECS;
+	rtw_write8(padapter, EE_9346CR, (unsigned char)x);
+
+	/* write the read opcode and register number in that order */
+	/* The opcode is 3bits in length, reg is 6 bits long */
+	shift_out_bits(padapter, EEPROM_READ_OPCODE, 3);
+	shift_out_bits(padapter, reg, padapter->EepromAddressSize);
+
+
+	for (i = 0; i < sz; i += 2) {
+		data16 = shift_in_bits(padapter);
+		data[i] = data16 & 0xff;
+		data[i + 1] = data16 >> 8;
+	}
+
+	eeprom_clean(padapter);
+out:
+	return;
+}
+
+
+/* addr_off : address offset of the entry in eeprom (not the tuple number of eeprom (reg); that is addr_off !=reg) */
+u8 eeprom_read(_adapter *padapter, u32 addr_off, u8 sz, u8 *rbuf)
+{
+	u8 quotient, remainder, addr_2align_odd;
+	u16 reg, stmp , i = 0, idx = 0;
+	reg = (u16)(addr_off >> 1);
+	addr_2align_odd = (u8)(addr_off & 0x1);
+
+	if (addr_2align_odd) { /* read that start at high part: e.g  1,3,5,7,9,... */
+		stmp = eeprom_read16(padapter, reg);
+		rbuf[idx++] = (u8)((stmp >> 8) & 0xff); /* return hogh-part of the short */
+		reg++;
+		sz--;
+	}
+
+	quotient = sz >> 1;
+	remainder = sz & 0x1;
+
+	for (i = 0 ; i < quotient; i++) {
+		stmp = eeprom_read16(padapter, reg + i);
+		rbuf[idx++] = (u8)(stmp & 0xff);
+		rbuf[idx++] = (u8)((stmp >> 8) & 0xff);
+	}
+
+	reg = reg + i;
+	if (remainder) { /* end of read at lower part of short : 0,2,4,6,... */
+		stmp = eeprom_read16(padapter, reg);
+		rbuf[idx] = (u8)(stmp & 0xff);
+	}
+	return _TRUE;
+}
+
+
+
+VOID read_eeprom_content(_adapter	*padapter)
+{
+
+
+
+}
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/core/rtw_ieee80211.c linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/core/rtw_ieee80211.c
--- linux-5.6.3/3rdparty/rtl8821ce/core/rtw_ieee80211.c	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/core/rtw_ieee80211.c	2020-04-10 16:35:06.773658060 +0300
@@ -0,0 +1,2909 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#define _IEEE80211_C
+
+#ifdef CONFIG_PLATFORM_INTEL_BYT
+	#include <linux/fs.h>
+#endif
+#include <drv_types.h>
+
+
+u8 RTW_WPA_OUI_TYPE[] = { 0x00, 0x50, 0xf2, 1 };
+u16 RTW_WPA_VERSION = 1;
+u8 WPA_AUTH_KEY_MGMT_NONE[] = { 0x00, 0x50, 0xf2, 0 };
+u8 WPA_AUTH_KEY_MGMT_UNSPEC_802_1X[] = { 0x00, 0x50, 0xf2, 1 };
+u8 WPA_AUTH_KEY_MGMT_PSK_OVER_802_1X[] = { 0x00, 0x50, 0xf2, 2 };
+u8 WPA_CIPHER_SUITE_NONE[] = { 0x00, 0x50, 0xf2, 0 };
+u8 WPA_CIPHER_SUITE_WEP40[] = { 0x00, 0x50, 0xf2, 1 };
+u8 WPA_CIPHER_SUITE_TKIP[] = { 0x00, 0x50, 0xf2, 2 };
+u8 WPA_CIPHER_SUITE_WRAP[] = { 0x00, 0x50, 0xf2, 3 };
+u8 WPA_CIPHER_SUITE_CCMP[] = { 0x00, 0x50, 0xf2, 4 };
+u8 WPA_CIPHER_SUITE_WEP104[] = { 0x00, 0x50, 0xf2, 5 };
+
+u16 RSN_VERSION_BSD = 1;
+u8 RSN_AUTH_KEY_MGMT_UNSPEC_802_1X[] = { 0x00, 0x0f, 0xac, 1 };
+u8 RSN_AUTH_KEY_MGMT_PSK_OVER_802_1X[] = { 0x00, 0x0f, 0xac, 2 };
+u8 RSN_CIPHER_SUITE_NONE[] = { 0x00, 0x0f, 0xac, 0 };
+u8 RSN_CIPHER_SUITE_WEP40[] = { 0x00, 0x0f, 0xac, 1 };
+u8 RSN_CIPHER_SUITE_TKIP[] = { 0x00, 0x0f, 0xac, 2 };
+u8 RSN_CIPHER_SUITE_WRAP[] = { 0x00, 0x0f, 0xac, 3 };
+u8 RSN_CIPHER_SUITE_CCMP[] = { 0x00, 0x0f, 0xac, 4 };
+u8 RSN_CIPHER_SUITE_WEP104[] = { 0x00, 0x0f, 0xac, 5 };
+/* -----------------------------------------------------------
+ * for adhoc-master to generate ie and provide supported-rate to fw
+ * ----------------------------------------------------------- */
+
+static u8	WIFI_CCKRATES[] = {
+	(IEEE80211_CCK_RATE_1MB | IEEE80211_BASIC_RATE_MASK),
+	(IEEE80211_CCK_RATE_2MB | IEEE80211_BASIC_RATE_MASK),
+	(IEEE80211_CCK_RATE_5MB | IEEE80211_BASIC_RATE_MASK),
+	(IEEE80211_CCK_RATE_11MB | IEEE80211_BASIC_RATE_MASK)
+};
+
+static u8	WIFI_OFDMRATES[] = {
+	(IEEE80211_OFDM_RATE_6MB),
+	(IEEE80211_OFDM_RATE_9MB),
+	(IEEE80211_OFDM_RATE_12MB),
+	(IEEE80211_OFDM_RATE_18MB),
+	(IEEE80211_OFDM_RATE_24MB),
+	IEEE80211_OFDM_RATE_36MB,
+	IEEE80211_OFDM_RATE_48MB,
+	IEEE80211_OFDM_RATE_54MB
+};
+
+u8 mgn_rates_cck[4] = {MGN_1M, MGN_2M, MGN_5_5M, MGN_11M};
+u8 mgn_rates_ofdm[8] = {MGN_6M, MGN_9M, MGN_12M, MGN_18M, MGN_24M, MGN_36M, MGN_48M, MGN_54M};
+u8 mgn_rates_mcs0_7[8] = {MGN_MCS0, MGN_MCS1, MGN_MCS2, MGN_MCS3, MGN_MCS4, MGN_MCS5, MGN_MCS6, MGN_MCS7};
+u8 mgn_rates_mcs8_15[8] = {MGN_MCS8, MGN_MCS9, MGN_MCS10, MGN_MCS11, MGN_MCS12, MGN_MCS13, MGN_MCS14, MGN_MCS15};
+u8 mgn_rates_mcs16_23[8] = {MGN_MCS16, MGN_MCS17, MGN_MCS18, MGN_MCS19, MGN_MCS20, MGN_MCS21, MGN_MCS22, MGN_MCS23};
+u8 mgn_rates_mcs24_31[8] = {MGN_MCS24, MGN_MCS25, MGN_MCS26, MGN_MCS27, MGN_MCS28, MGN_MCS29, MGN_MCS30, MGN_MCS31};
+u8 mgn_rates_vht1ss[10] = {MGN_VHT1SS_MCS0, MGN_VHT1SS_MCS1, MGN_VHT1SS_MCS2, MGN_VHT1SS_MCS3, MGN_VHT1SS_MCS4
+	, MGN_VHT1SS_MCS5, MGN_VHT1SS_MCS6, MGN_VHT1SS_MCS7, MGN_VHT1SS_MCS8, MGN_VHT1SS_MCS9
+			  };
+u8 mgn_rates_vht2ss[10] = {MGN_VHT2SS_MCS0, MGN_VHT2SS_MCS1, MGN_VHT2SS_MCS2, MGN_VHT2SS_MCS3, MGN_VHT2SS_MCS4
+	, MGN_VHT2SS_MCS5, MGN_VHT2SS_MCS6, MGN_VHT2SS_MCS7, MGN_VHT2SS_MCS8, MGN_VHT2SS_MCS9
+			  };
+u8 mgn_rates_vht3ss[10] = {MGN_VHT3SS_MCS0, MGN_VHT3SS_MCS1, MGN_VHT3SS_MCS2, MGN_VHT3SS_MCS3, MGN_VHT3SS_MCS4
+	, MGN_VHT3SS_MCS5, MGN_VHT3SS_MCS6, MGN_VHT3SS_MCS7, MGN_VHT3SS_MCS8, MGN_VHT3SS_MCS9
+			  };
+u8 mgn_rates_vht4ss[10] = {MGN_VHT4SS_MCS0, MGN_VHT4SS_MCS1, MGN_VHT4SS_MCS2, MGN_VHT4SS_MCS3, MGN_VHT4SS_MCS4
+	, MGN_VHT4SS_MCS5, MGN_VHT4SS_MCS6, MGN_VHT4SS_MCS7, MGN_VHT4SS_MCS8, MGN_VHT4SS_MCS9
+			  };
+
+static const char *const _rate_section_str[] = {
+	"CCK",
+	"OFDM",
+	"HT_1SS",
+	"HT_2SS",
+	"HT_3SS",
+	"HT_4SS",
+	"VHT_1SS",
+	"VHT_2SS",
+	"VHT_3SS",
+	"VHT_4SS",
+	"RATE_SECTION_UNKNOWN",
+};
+
+const char *rate_section_str(u8 section)
+{
+	section = (section >= RATE_SECTION_NUM) ? RATE_SECTION_NUM : section;
+	return _rate_section_str[section];
+}
+
+struct rate_section_ent rates_by_sections[RATE_SECTION_NUM] = {
+	{RF_1TX, 4, mgn_rates_cck},
+	{RF_1TX, 8, mgn_rates_ofdm},
+	{RF_1TX, 8, mgn_rates_mcs0_7},
+	{RF_2TX, 8, mgn_rates_mcs8_15},
+	{RF_3TX, 8, mgn_rates_mcs16_23},
+	{RF_4TX, 8, mgn_rates_mcs24_31},
+	{RF_1TX, 10, mgn_rates_vht1ss},
+	{RF_2TX, 10, mgn_rates_vht2ss},
+	{RF_3TX, 10, mgn_rates_vht3ss},
+	{RF_4TX, 10, mgn_rates_vht4ss},
+};
+
+int rtw_get_bit_value_from_ieee_value(u8 val)
+{
+	unsigned char dot11_rate_table[] = {2, 4, 11, 22, 12, 18, 24, 36, 48, 72, 96, 108, 0}; /* last element must be zero!! */
+
+	int i = 0;
+	while (dot11_rate_table[i] != 0) {
+		if (dot11_rate_table[i] == val)
+			return BIT(i);
+		i++;
+	}
+	return 0;
+}
+uint rtw_get_cckrate_size(u8 *rate, u32 rate_length)
+{
+	int i = 0;
+	while(i < rate_length){
+		RTW_DBG("%s, rate[%d]=%u\n", __FUNCTION__, i, rate[i]);
+		if (((rate[i] & 0x7f) == 2) || ((rate[i] & 0x7f) == 4) ||
+			((rate[i] & 0x7f) == 11)  || ((rate[i] & 0x7f) == 22))
+			i++;
+		else
+			break;
+	}
+	return i;
+}
+
+uint	rtw_is_cckrates_included(u8 *rate)
+{
+	u32	i = 0;
+
+	while (rate[i] != 0) {
+		if ((((rate[i]) & 0x7f) == 2)	|| (((rate[i]) & 0x7f) == 4) ||
+		    (((rate[i]) & 0x7f) == 11)  || (((rate[i]) & 0x7f) == 22))
+			return _TRUE;
+		i++;
+	}
+
+	return _FALSE;
+}
+
+uint	rtw_is_cckratesonly_included(u8 *rate)
+{
+	u32 i = 0;
+
+
+	while (rate[i] != 0) {
+		if ((((rate[i]) & 0x7f) != 2) && (((rate[i]) & 0x7f) != 4) &&
+		    (((rate[i]) & 0x7f) != 11)  && (((rate[i]) & 0x7f) != 22))
+			return _FALSE;
+
+		i++;
+	}
+
+	return _TRUE;
+
+}
+
+int rtw_check_network_type(unsigned char *rate, int ratelen, int channel)
+{
+	if (channel > 14) {
+		if ((rtw_is_cckrates_included(rate)) == _TRUE)
+			return WIRELESS_INVALID;
+		else
+			return WIRELESS_11A;
+	} else { /* could be pure B, pure G, or B/G */
+		if ((rtw_is_cckratesonly_included(rate)) == _TRUE)
+			return WIRELESS_11B;
+		else if ((rtw_is_cckrates_included(rate)) == _TRUE)
+			return	WIRELESS_11BG;
+		else
+			return WIRELESS_11G;
+	}
+
+}
+
+u8 *rtw_set_fixed_ie(unsigned char *pbuf, unsigned int len, unsigned char *source,
+		     unsigned int *frlen)
+{
+	_rtw_memcpy((void *)pbuf, (void *)source, len);
+	*frlen = *frlen + len;
+	return pbuf + len;
+}
+
+/* rtw_set_ie will update frame length */
+u8 *rtw_set_ie
+(
+	u8 *pbuf,
+	sint index,
+	uint len,
+	const u8 *source,
+	uint *frlen /* frame length */
+)
+{
+	*pbuf = (u8)index;
+
+	*(pbuf + 1) = (u8)len;
+
+	if (len > 0)
+		_rtw_memcpy((void *)(pbuf + 2), (void *)source, len);
+
+	if (frlen)
+		*frlen = *frlen + (len + 2);
+
+	return pbuf + len + 2;
+}
+
+inline u8 *rtw_set_ie_ch_switch(u8 *buf, u32 *buf_len, u8 ch_switch_mode,
+				u8 new_ch, u8 ch_switch_cnt)
+{
+	u8 ie_data[3];
+
+	ie_data[0] = ch_switch_mode;
+	ie_data[1] = new_ch;
+	ie_data[2] = ch_switch_cnt;
+	return rtw_set_ie(buf, WLAN_EID_CHANNEL_SWITCH,  3, ie_data, buf_len);
+}
+
+inline u8 secondary_ch_offset_to_hal_ch_offset(u8 ch_offset)
+{
+	if (ch_offset == SCN)
+		return HAL_PRIME_CHNL_OFFSET_DONT_CARE;
+	else if (ch_offset == SCA)
+		return HAL_PRIME_CHNL_OFFSET_LOWER;
+	else if (ch_offset == SCB)
+		return HAL_PRIME_CHNL_OFFSET_UPPER;
+
+	return HAL_PRIME_CHNL_OFFSET_DONT_CARE;
+}
+
+inline u8 hal_ch_offset_to_secondary_ch_offset(u8 ch_offset)
+{
+	if (ch_offset == HAL_PRIME_CHNL_OFFSET_DONT_CARE)
+		return SCN;
+	else if (ch_offset == HAL_PRIME_CHNL_OFFSET_LOWER)
+		return SCA;
+	else if (ch_offset == HAL_PRIME_CHNL_OFFSET_UPPER)
+		return SCB;
+
+	return SCN;
+}
+
+inline u8 *rtw_set_ie_secondary_ch_offset(u8 *buf, u32 *buf_len, u8 secondary_ch_offset)
+{
+	return rtw_set_ie(buf, WLAN_EID_SECONDARY_CHANNEL_OFFSET,  1, &secondary_ch_offset, buf_len);
+}
+
+inline u8 *rtw_set_ie_mesh_ch_switch_parm(u8 *buf, u32 *buf_len, u8 ttl,
+		u8 flags, u16 reason, u16 precedence)
+{
+	u8 ie_data[6];
+
+	ie_data[0] = ttl;
+	ie_data[1] = flags;
+	RTW_PUT_LE16((u8 *)&ie_data[2], reason);
+	RTW_PUT_LE16((u8 *)&ie_data[4], precedence);
+
+	return rtw_set_ie(buf, 0x118,  6, ie_data, buf_len);
+}
+
+/*----------------------------------------------------------------------------
+index: the information element id index, limit is the limit for search
+-----------------------------------------------------------------------------*/
+u8 *rtw_get_ie(const u8 *pbuf, sint index, sint *len, sint limit)
+{
+	sint tmp, i;
+	const u8 *p;
+	if (limit < 1) {
+		return NULL;
+	}
+
+	p = pbuf;
+	i = 0;
+	*len = 0;
+	while (1) {
+		if (*p == index) {
+			*len = *(p + 1);
+			return (u8 *)p;
+		} else {
+			tmp = *(p + 1);
+			p += (tmp + 2);
+			i += (tmp + 2);
+		}
+		if (i >= limit)
+			break;
+	}
+	return NULL;
+}
+
+/**
+ * rtw_get_ie_ex - Search specific IE from a series of IEs
+ * @in_ie: Address of IEs to search
+ * @in_len: Length limit from in_ie
+ * @eid: Element ID to match
+ * @oui: OUI to match
+ * @oui_len: OUI length
+ * @ie: If not NULL and the specific IE is found, the IE will be copied to the buf starting from the specific IE
+ * @ielen: If not NULL and the specific IE is found, will set to the length of the entire IE
+ *
+ * Returns: The address of the specific IE found, or NULL
+ */
+u8 *rtw_get_ie_ex(const u8 *in_ie, uint in_len, u8 eid, const u8 *oui, u8 oui_len, u8 *ie, uint *ielen)
+{
+	uint cnt;
+	const u8 *target_ie = NULL;
+
+
+	if (ielen)
+		*ielen = 0;
+
+	if (!in_ie || in_len <= 0)
+		return (u8 *)target_ie;
+
+	cnt = 0;
+
+	while (cnt < in_len) {
+		if (eid == in_ie[cnt]
+		    && (!oui || _rtw_memcmp(&in_ie[cnt + 2], oui, oui_len) == _TRUE)) {
+			target_ie = &in_ie[cnt];
+
+			if (ie)
+				_rtw_memcpy(ie, &in_ie[cnt], in_ie[cnt + 1] + 2);
+
+			if (ielen)
+				*ielen = in_ie[cnt + 1] + 2;
+
+			break;
+		} else {
+			cnt += in_ie[cnt + 1] + 2; /* goto next	 */
+		}
+
+	}
+
+	return (u8 *)target_ie;
+}
+
+/**
+ * rtw_ies_remove_ie - Find matching IEs and remove
+ * @ies: Address of IEs to search
+ * @ies_len: Pointer of length of ies, will update to new length
+ * @offset: The offset to start scarch
+ * @eid: Element ID to match
+ * @oui: OUI to match
+ * @oui_len: OUI length
+ *
+ * Returns: _SUCCESS: ies is updated, _FAIL: not updated
+ */
+int rtw_ies_remove_ie(u8 *ies, uint *ies_len, uint offset, u8 eid, u8 *oui, u8 oui_len)
+{
+	int ret = _FAIL;
+	u8 *target_ie;
+	u32 target_ielen;
+	u8 *start;
+	uint search_len;
+
+	if (!ies || !ies_len || *ies_len <= offset)
+		goto exit;
+
+	start = ies + offset;
+	search_len = *ies_len - offset;
+
+	while (1) {
+		target_ie = rtw_get_ie_ex(start, search_len, eid, oui, oui_len, NULL, &target_ielen);
+		if (target_ie && target_ielen) {
+			u8 *remain_ies = target_ie + target_ielen;
+			uint remain_len = search_len - (remain_ies - start);
+
+			_rtw_memmove(target_ie, remain_ies, remain_len);
+			*ies_len = *ies_len - target_ielen;
+			ret = _SUCCESS;
+
+			start = target_ie;
+			search_len = remain_len;
+		} else
+			break;
+	}
+exit:
+	return ret;
+}
+
+ /* Returns:  remove size OR  _FAIL: not updated*/
+int rtw_remove_ie_g_rate(u8 *ie, uint *ie_len, uint offset, u8 eid)
+{
+	int ret = _FAIL;
+	u8 *tem_target_ie;
+	u8 *target_ie;
+	u32 target_ielen,temp_target_ielen,cck_rate_size,rm_size;
+	u8 *start;
+	uint search_len;
+	u8 *remain_ies;
+	uint remain_len;
+	if (!ie || !ie_len || *ie_len <= offset)
+		goto exit;
+
+	start = ie + offset;
+	search_len = *ie_len - offset;
+
+	while (1) {
+		tem_target_ie=rtw_get_ie(start,eid,&temp_target_ielen,search_len);
+		
+		/*if(tem_target_ie)
+			RTW_INFO("%s, tem_target_ie=%u\n", __FUNCTION__,*tem_target_ie);*/
+		if (tem_target_ie && temp_target_ielen) {
+			cck_rate_size = rtw_get_cckrate_size((tem_target_ie+2), temp_target_ielen);
+			rm_size = temp_target_ielen - cck_rate_size;
+			RTW_DBG("%s,cck_rate_size=%u rm_size=%u\n", __FUNCTION__, cck_rate_size, rm_size);
+			temp_target_ielen=temp_target_ielen + 2;/*org size of  Supposrted Rates(include id + length)*/
+			/*RTW_INFO("%s, temp_target_ielen=%u\n", __FUNCTION__,temp_target_ielen);*/
+			remain_ies = tem_target_ie + temp_target_ielen;
+			remain_len = search_len - (remain_ies - start);
+			target_ielen=cck_rate_size;/*discount g mode rate 6, 9 12,18Mbps,id , length*/
+			*(tem_target_ie+1)=target_ielen;/*set new length to Supposrted Rates*/
+			target_ie=tem_target_ie+target_ielen + 2;/*set target ie to address of rate 6Mbps */
+	
+			_rtw_memmove(target_ie, remain_ies, remain_len);
+			*ie_len = *ie_len - rm_size;
+			ret = rm_size;
+
+			start = target_ie;
+			search_len = remain_len;
+		} else
+			break;
+	}
+exit:
+	return ret;
+}
+void rtw_set_supported_rate(u8 *SupportedRates, uint mode)
+{
+
+	_rtw_memset(SupportedRates, 0, NDIS_802_11_LENGTH_RATES_EX);
+
+	switch (mode) {
+	case WIRELESS_11B:
+		_rtw_memcpy(SupportedRates, WIFI_CCKRATES, IEEE80211_CCK_RATE_LEN);
+		break;
+
+	case WIRELESS_11G:
+	case WIRELESS_11A:
+	case WIRELESS_11_5N:
+	case WIRELESS_11A_5N: /* Todo: no basic rate for ofdm ? */
+	case WIRELESS_11_5AC:
+		_rtw_memcpy(SupportedRates, WIFI_OFDMRATES, IEEE80211_NUM_OFDM_RATESLEN);
+		break;
+
+	case WIRELESS_11BG:
+	case WIRELESS_11G_24N:
+	case WIRELESS_11_24N:
+	case WIRELESS_11BG_24N:
+		_rtw_memcpy(SupportedRates, WIFI_CCKRATES, IEEE80211_CCK_RATE_LEN);
+		_rtw_memcpy(SupportedRates + IEEE80211_CCK_RATE_LEN, WIFI_OFDMRATES, IEEE80211_NUM_OFDM_RATESLEN);
+		break;
+
+	}
+}
+
+uint	rtw_get_rateset_len(u8	*rateset)
+{
+	uint i = 0;
+	while (1) {
+		if ((rateset[i]) == 0)
+			break;
+
+		if (i > 12)
+			break;
+
+		i++;
+	}
+	return i;
+}
+
+int rtw_generate_ie(struct registry_priv *pregistrypriv)
+{
+	u8	wireless_mode;
+	int	sz = 0, rateLen;
+	WLAN_BSSID_EX	*pdev_network = &pregistrypriv->dev_network;
+	u8	*ie = pdev_network->IEs;
+
+
+	/* timestamp will be inserted by hardware */
+	sz += 8;
+	ie += sz;
+
+	/* beacon interval : 2bytes */
+	*(u16 *)ie = cpu_to_le16((u16)pdev_network->Configuration.BeaconPeriod); /* BCN_INTERVAL; */
+	sz += 2;
+	ie += 2;
+
+	/* capability info */
+	*(u16 *)ie = 0;
+
+	*(u16 *)ie |= cpu_to_le16(cap_IBSS);
+
+	if (pregistrypriv->preamble == PREAMBLE_SHORT)
+		*(u16 *)ie |= cpu_to_le16(cap_ShortPremble);
+
+	if (pdev_network->Privacy)
+		*(u16 *)ie |= cpu_to_le16(cap_Privacy);
+
+	sz += 2;
+	ie += 2;
+
+	/* SSID */
+	ie = rtw_set_ie(ie, _SSID_IE_, pdev_network->Ssid.SsidLength, pdev_network->Ssid.Ssid, &sz);
+
+	/* supported rates */
+	if (pregistrypriv->wireless_mode == WIRELESS_11ABGN) {
+		if (pdev_network->Configuration.DSConfig > 14)
+			wireless_mode = WIRELESS_11A_5N;
+		else
+			wireless_mode = WIRELESS_11BG_24N;
+	} else if (pregistrypriv->wireless_mode == WIRELESS_MODE_MAX) { /* WIRELESS_11ABGN | WIRELESS_11AC */
+		if (pdev_network->Configuration.DSConfig > 14)
+			wireless_mode = WIRELESS_11_5AC;
+		else
+			wireless_mode = WIRELESS_11BG_24N;
+	} else
+		wireless_mode = pregistrypriv->wireless_mode;
+
+	rtw_set_supported_rate(pdev_network->SupportedRates, wireless_mode) ;
+
+	rateLen = rtw_get_rateset_len(pdev_network->SupportedRates);
+
+	if (rateLen > 8) {
+		ie = rtw_set_ie(ie, _SUPPORTEDRATES_IE_, 8, pdev_network->SupportedRates, &sz);
+		/* ie = rtw_set_ie(ie, _EXT_SUPPORTEDRATES_IE_, (rateLen - 8), (pdev_network->SupportedRates + 8), &sz); */
+	} else
+		ie = rtw_set_ie(ie, _SUPPORTEDRATES_IE_, rateLen, pdev_network->SupportedRates, &sz);
+
+	/* DS parameter set */
+	ie = rtw_set_ie(ie, _DSSET_IE_, 1, (u8 *)&(pdev_network->Configuration.DSConfig), &sz);
+
+
+	/* IBSS Parameter Set */
+
+	ie = rtw_set_ie(ie, _IBSS_PARA_IE_, 2, (u8 *)&(pdev_network->Configuration.ATIMWindow), &sz);
+
+	if (rateLen > 8)
+		ie = rtw_set_ie(ie, _EXT_SUPPORTEDRATES_IE_, (rateLen - 8), (pdev_network->SupportedRates + 8), &sz);
+
+#ifdef CONFIG_80211N_HT
+	/* HT Cap. */
+	if (is_supported_ht(pregistrypriv->wireless_mode)
+	    && (pregistrypriv->ht_enable == _TRUE)) {
+		/* todo: */
+	}
+#endif /* CONFIG_80211N_HT */
+
+	/* pdev_network->IELength =  sz; */ /* update IELength */
+
+
+	/* return _SUCCESS; */
+
+	return sz;
+
+}
+
+unsigned char *rtw_get_wpa_ie(unsigned char *pie, int *wpa_ie_len, int limit)
+{
+	int len;
+	u16 val16;
+	unsigned char wpa_oui_type[] = {0x00, 0x50, 0xf2, 0x01};
+	u8 *pbuf = pie;
+	int limit_new = limit;
+
+	while (1) {
+		pbuf = rtw_get_ie(pbuf, _WPA_IE_ID_, &len, limit_new);
+
+		if (pbuf) {
+
+			/* check if oui matches... */
+			if (_rtw_memcmp((pbuf + 2), wpa_oui_type, sizeof(wpa_oui_type)) == _FALSE)
+
+				goto check_next_ie;
+
+			/* check version... */
+			_rtw_memcpy((u8 *)&val16, (pbuf + 6), sizeof(val16));
+
+			val16 = le16_to_cpu(val16);
+			if (val16 != 0x0001)
+				goto check_next_ie;
+
+			*wpa_ie_len = *(pbuf + 1);
+
+			return pbuf;
+
+		} else {
+
+			*wpa_ie_len = 0;
+			return NULL;
+		}
+
+check_next_ie:
+
+		limit_new = limit - (pbuf - pie) - 2 - len;
+
+		if (limit_new <= 0)
+			break;
+
+		pbuf += (2 + len);
+
+	}
+
+	*wpa_ie_len = 0;
+
+	return NULL;
+
+}
+
+unsigned char *rtw_get_wpa2_ie(unsigned char *pie, int *rsn_ie_len, int limit)
+{
+
+	return rtw_get_ie(pie, _WPA2_IE_ID_, rsn_ie_len, limit);
+
+}
+
+int rtw_get_wpa_cipher_suite(u8 *s)
+{
+	if (_rtw_memcmp(s, WPA_CIPHER_SUITE_NONE, WPA_SELECTOR_LEN) == _TRUE)
+		return WPA_CIPHER_NONE;
+	if (_rtw_memcmp(s, WPA_CIPHER_SUITE_WEP40, WPA_SELECTOR_LEN) == _TRUE)
+		return WPA_CIPHER_WEP40;
+	if (_rtw_memcmp(s, WPA_CIPHER_SUITE_TKIP, WPA_SELECTOR_LEN) == _TRUE)
+		return WPA_CIPHER_TKIP;
+	if (_rtw_memcmp(s, WPA_CIPHER_SUITE_CCMP, WPA_SELECTOR_LEN) == _TRUE)
+		return WPA_CIPHER_CCMP;
+	if (_rtw_memcmp(s, WPA_CIPHER_SUITE_WEP104, WPA_SELECTOR_LEN) == _TRUE)
+		return WPA_CIPHER_WEP104;
+
+	return 0;
+}
+
+int rtw_get_wpa2_cipher_suite(u8 *s)
+{
+	if (_rtw_memcmp(s, RSN_CIPHER_SUITE_NONE, RSN_SELECTOR_LEN) == _TRUE)
+		return WPA_CIPHER_NONE;
+	if (_rtw_memcmp(s, RSN_CIPHER_SUITE_WEP40, RSN_SELECTOR_LEN) == _TRUE)
+		return WPA_CIPHER_WEP40;
+	if (_rtw_memcmp(s, RSN_CIPHER_SUITE_TKIP, RSN_SELECTOR_LEN) == _TRUE)
+		return WPA_CIPHER_TKIP;
+	if (_rtw_memcmp(s, RSN_CIPHER_SUITE_CCMP, RSN_SELECTOR_LEN) == _TRUE)
+		return WPA_CIPHER_CCMP;
+	if (_rtw_memcmp(s, RSN_CIPHER_SUITE_WEP104, RSN_SELECTOR_LEN) == _TRUE)
+		return WPA_CIPHER_WEP104;
+
+	return 0;
+}
+
+
+int rtw_parse_wpa_ie(u8 *wpa_ie, int wpa_ie_len, int *group_cipher, int *pairwise_cipher, int *is_8021x)
+{
+	int i, ret = _SUCCESS;
+	int left, count;
+	u8 *pos;
+	u8 SUITE_1X[4] = {0x00, 0x50, 0xf2, 1};
+
+	if (wpa_ie_len <= 0) {
+		/* No WPA IE - fail silently */
+		return _FAIL;
+	}
+
+
+	if ((*wpa_ie != _WPA_IE_ID_) || (*(wpa_ie + 1) != (u8)(wpa_ie_len - 2)) ||
+	    (_rtw_memcmp(wpa_ie + 2, RTW_WPA_OUI_TYPE, WPA_SELECTOR_LEN) != _TRUE))
+		return _FAIL;
+
+	pos = wpa_ie;
+
+	pos += 8;
+	left = wpa_ie_len - 8;
+
+
+	/* group_cipher */
+	if (left >= WPA_SELECTOR_LEN) {
+
+		*group_cipher = rtw_get_wpa_cipher_suite(pos);
+
+		pos += WPA_SELECTOR_LEN;
+		left -= WPA_SELECTOR_LEN;
+
+	} else if (left > 0) {
+
+		return _FAIL;
+	}
+
+
+	/* pairwise_cipher */
+	if (left >= 2) {
+		/* count = le16_to_cpu(*(u16*)pos);	 */
+		count = RTW_GET_LE16(pos);
+		pos += 2;
+		left -= 2;
+
+		if (count == 0 || left < count * WPA_SELECTOR_LEN) {
+			return _FAIL;
+		}
+
+		for (i = 0; i < count; i++) {
+			*pairwise_cipher |= rtw_get_wpa_cipher_suite(pos);
+
+			pos += WPA_SELECTOR_LEN;
+			left -= WPA_SELECTOR_LEN;
+		}
+
+	} else if (left == 1) {
+		return _FAIL;
+	}
+
+	if (is_8021x) {
+		if (left >= 6) {
+			pos += 2;
+			if (_rtw_memcmp(pos, SUITE_1X, 4) == 1) {
+				*is_8021x = 1;
+			}
+		}
+	}
+
+	return ret;
+
+}
+
+int rtw_rsne_info_parse(const u8 *ie, uint ie_len, struct rsne_info *info)
+{
+	const u8 *pos = ie;
+	u16 cnt;
+
+	_rtw_memset(info, 0, sizeof(struct rsne_info));
+
+	if (ie + ie_len < pos + 4)
+		goto err;
+
+	if (*ie != WLAN_EID_RSN || *(ie + 1) != ie_len - 2)
+		goto err;
+	pos += 2 + 2;
+
+	/* Group CS */
+	if (ie + ie_len < pos + 4) {
+		if (ie + ie_len != pos)
+			goto err;
+		goto exit;
+	}
+	info->gcs = (u8 *)pos;
+	pos += 4;
+
+	/* Pairwise CS */
+	if (ie + ie_len < pos + 2) {
+		if (ie + ie_len != pos)
+			goto err;
+		goto exit;
+	}
+	cnt = RTW_GET_LE16(pos);
+	pos += 2;
+	if (ie + ie_len < pos + 4 * cnt) {
+		if (ie + ie_len != pos)
+			goto err;
+		goto exit;
+	}
+	info->pcs_cnt = cnt;
+	info->pcs_list = (u8 *)pos;
+	pos += 4 * cnt;
+
+	/* AKM */
+	if (ie + ie_len < pos + 2) {
+		if (ie + ie_len != pos)
+			goto err;
+		goto exit;
+	}
+	cnt = RTW_GET_LE16(pos);
+	pos += 2;
+	if (ie + ie_len < pos + 4 * cnt) {
+		if (ie + ie_len != pos)
+			goto err;
+		goto exit;
+	}
+	info->akm_cnt = cnt;
+	info->akm_list = (u8 *)pos;
+	pos += 4 * cnt;
+
+	/* RSN cap */
+	if (ie + ie_len < pos + 2) {
+		if (ie + ie_len != pos)
+			goto err;
+		goto exit;
+	}
+	info->cap = (u8 *)pos;
+	pos += 2;
+
+	/* PMKID */
+	if (ie + ie_len < pos + 2) {
+		if (ie + ie_len != pos)
+			goto err;
+		goto exit;
+	}
+	cnt = RTW_GET_LE16(pos);
+	pos += 2;
+	if (ie + ie_len < pos + 16 * cnt) {
+		if (ie + ie_len != pos)
+			goto err;
+		goto exit;
+	}
+	info->pmkid_cnt = cnt;
+	info->pmkid_list = (u8 *)pos;
+	pos += 16 * cnt;
+
+	/* Group Mgmt CS */
+	if (ie + ie_len < pos + 4) {
+		if (ie + ie_len != pos)
+			goto err;
+		goto exit;
+	}
+	info->gmcs = (u8 *)pos;
+
+exit:
+	return _SUCCESS;
+
+err:
+	info->err = 1;
+	return _FAIL;
+}
+
+int rtw_parse_wpa2_ie(u8 *rsn_ie, int rsn_ie_len, int *group_cipher, int *pairwise_cipher, int *is_8021x, u8 *mfp_opt)
+{
+	struct rsne_info info;
+	int i, ret = _SUCCESS;
+	u8 SUITE_1X[4] = {0x00, 0x0f, 0xac, 0x01};
+
+	ret = rtw_rsne_info_parse(rsn_ie, rsn_ie_len, &info);
+	if (ret != _SUCCESS)
+		goto exit;
+
+	if (group_cipher) {
+		if (info.gcs)
+			*group_cipher = rtw_get_wpa2_cipher_suite(info.gcs);
+		else
+			*group_cipher = 0;
+	}
+
+	if (pairwise_cipher) {
+		*pairwise_cipher = 0;
+		for (i = 0; i < info.pcs_cnt; i++)
+			*pairwise_cipher |= rtw_get_wpa2_cipher_suite(info.pcs_list + 4 * i);
+	}
+
+	if (is_8021x) {
+		*is_8021x = 0;
+		/* here only check the first AKM suite */
+		if (info.akm_cnt && _rtw_memcmp(SUITE_1X, info.akm_list, 4) == _TRUE)
+			*is_8021x = 1;
+	}
+
+	if (mfp_opt) {
+		*mfp_opt = MFP_NO;
+		if (info.cap)
+			*mfp_opt = GET_RSN_CAP_MFP_OPTION(info.cap);
+	}
+
+exit:
+	return ret;
+}
+
+/* #ifdef CONFIG_WAPI_SUPPORT */
+int rtw_get_wapi_ie(u8 *in_ie, uint in_len, u8 *wapi_ie, u16 *wapi_len)
+{
+	int len = 0;
+	u8 authmode;
+	uint	cnt;
+	u8 wapi_oui1[4] = {0x0, 0x14, 0x72, 0x01};
+	u8 wapi_oui2[4] = {0x0, 0x14, 0x72, 0x02};
+
+
+	if (wapi_len)
+		*wapi_len = 0;
+
+	if (!in_ie || in_len <= 0)
+		return len;
+
+	cnt = (_TIMESTAMP_ + _BEACON_ITERVAL_ + _CAPABILITY_);
+
+	while (cnt < in_len) {
+		authmode = in_ie[cnt];
+
+		/* if(authmode==_WAPI_IE_) */
+		if (authmode == _WAPI_IE_ && (_rtw_memcmp(&in_ie[cnt + 6], wapi_oui1, 4) == _TRUE ||
+			_rtw_memcmp(&in_ie[cnt + 6], wapi_oui2, 4) == _TRUE)) {
+			if (wapi_ie)
+				_rtw_memcpy(wapi_ie, &in_ie[cnt], in_ie[cnt + 1] + 2);
+
+			if (wapi_len)
+				*wapi_len = in_ie[cnt + 1] + 2;
+
+			cnt += in_ie[cnt + 1] + 2; /* get next */
+		} else {
+			cnt += in_ie[cnt + 1] + 2; /* get next */
+		}
+	}
+
+	if (wapi_len)
+		len = *wapi_len;
+
+
+	return len;
+
+}
+/* #endif */
+
+int rtw_get_sec_ie(u8 *in_ie, uint in_len, u8 *rsn_ie, u16 *rsn_len, u8 *wpa_ie, u16 *wpa_len)
+{
+	u8 authmode, sec_idx;
+	u8 wpa_oui[4] = {0x0, 0x50, 0xf2, 0x01};
+	uint	cnt;
+
+
+	/* Search required WPA or WPA2 IE and copy to sec_ie[ ] */
+
+	cnt = (_TIMESTAMP_ + _BEACON_ITERVAL_ + _CAPABILITY_);
+
+	sec_idx = 0;
+
+	while (cnt < in_len) {
+		authmode = in_ie[cnt];
+
+		if ((authmode == _WPA_IE_ID_) && (_rtw_memcmp(&in_ie[cnt + 2], &wpa_oui[0], 4) == _TRUE)) {
+
+			if (wpa_ie)
+				_rtw_memcpy(wpa_ie, &in_ie[cnt], in_ie[cnt + 1] + 2);
+
+			*wpa_len = in_ie[cnt + 1] + 2;
+			cnt += in_ie[cnt + 1] + 2; /* get next */
+		} else {
+			if (authmode == _WPA2_IE_ID_) {
+
+				if (rsn_ie)
+					_rtw_memcpy(rsn_ie, &in_ie[cnt], in_ie[cnt + 1] + 2);
+
+				*rsn_len = in_ie[cnt + 1] + 2;
+				cnt += in_ie[cnt + 1] + 2; /* get next */
+			} else {
+				cnt += in_ie[cnt + 1] + 2; /* get next */
+			}
+		}
+
+	}
+
+
+	return *rsn_len + *wpa_len;
+
+}
+
+u8 rtw_is_wps_ie(u8 *ie_ptr, uint *wps_ielen)
+{
+	u8 match = _FALSE;
+	u8 eid, wps_oui[4] = {0x0, 0x50, 0xf2, 0x04};
+
+	if (ie_ptr == NULL)
+		return match;
+
+	eid = ie_ptr[0];
+
+	if ((eid == _WPA_IE_ID_) && (_rtw_memcmp(&ie_ptr[2], wps_oui, 4) == _TRUE)) {
+		/* RTW_INFO("==> found WPS_IE.....\n"); */
+		*wps_ielen = ie_ptr[1] + 2;
+		match = _TRUE;
+	}
+	return match;
+}
+
+u8 *rtw_get_wps_ie_from_scan_queue(u8 *in_ie, uint in_len, u8 *wps_ie, uint *wps_ielen, enum bss_type frame_type)
+{
+	u8	*wps = NULL;
+
+	RTW_INFO("[%s] frame_type = %d\n", __FUNCTION__, frame_type);
+	switch (frame_type) {
+	case BSS_TYPE_BCN:
+	case BSS_TYPE_PROB_RSP: {
+		/*	Beacon or Probe Response */
+		wps = rtw_get_wps_ie(in_ie + _PROBERSP_IE_OFFSET_, in_len - _PROBERSP_IE_OFFSET_, wps_ie, wps_ielen);
+		break;
+	}
+	case BSS_TYPE_PROB_REQ: {
+		/*	Probe Request */
+		wps = rtw_get_wps_ie(in_ie + _PROBEREQ_IE_OFFSET_ , in_len - _PROBEREQ_IE_OFFSET_ , wps_ie, wps_ielen);
+		break;
+	}
+	default:
+	case BSS_TYPE_UNDEF:
+		break;
+	}
+	return wps;
+}
+
+/**
+ * rtw_get_wps_ie - Search WPS IE from a series of IEs
+ * @in_ie: Address of IEs to search
+ * @in_len: Length limit from in_ie
+ * @wps_ie: If not NULL and WPS IE is found, WPS IE will be copied to the buf starting from wps_ie
+ * @wps_ielen: If not NULL and WPS IE is found, will set to the length of the entire WPS IE
+ *
+ * Returns: The address of the WPS IE found, or NULL
+ */
+u8 *rtw_get_wps_ie(const u8 *in_ie, uint in_len, u8 *wps_ie, uint *wps_ielen)
+{
+	uint cnt;
+	const u8 *wpsie_ptr = NULL;
+	u8 eid, wps_oui[4] = {0x00, 0x50, 0xf2, 0x04};
+
+	if (wps_ielen)
+		*wps_ielen = 0;
+
+	if (!in_ie) {
+		rtw_warn_on(1);
+		return (u8 *)wpsie_ptr;
+	}
+
+	if (in_len <= 0)
+		return (u8 *)wpsie_ptr;
+
+	cnt = 0;
+
+	while (cnt + 1 + 4 < in_len) {
+		eid = in_ie[cnt];
+
+		if (cnt + 1 + 4 >= MAX_IE_SZ) {
+			rtw_warn_on(1);
+			return NULL;
+		}
+
+		if (eid == WLAN_EID_VENDOR_SPECIFIC && _rtw_memcmp(&in_ie[cnt + 2], wps_oui, 4) == _TRUE) {
+			wpsie_ptr = in_ie + cnt;
+
+			if (wps_ie)
+				_rtw_memcpy(wps_ie, &in_ie[cnt], in_ie[cnt + 1] + 2);
+
+			if (wps_ielen)
+				*wps_ielen = in_ie[cnt + 1] + 2;
+
+			break;
+		} else
+			cnt += in_ie[cnt + 1] + 2;
+
+	}
+
+	return (u8 *)wpsie_ptr;
+}
+
+/**
+ * rtw_get_wps_attr - Search a specific WPS attribute from a given WPS IE
+ * @wps_ie: Address of WPS IE to search
+ * @wps_ielen: Length limit from wps_ie
+ * @target_attr_id: The attribute ID of WPS attribute to search
+ * @buf_attr: If not NULL and the WPS attribute is found, WPS attribute will be copied to the buf starting from buf_attr
+ * @len_attr: If not NULL and the WPS attribute is found, will set to the length of the entire WPS attribute
+ *
+ * Returns: the address of the specific WPS attribute found, or NULL
+ */
+u8 *rtw_get_wps_attr(u8 *wps_ie, uint wps_ielen, u16 target_attr_id , u8 *buf_attr, u32 *len_attr)
+{
+	u8 *attr_ptr = NULL;
+	u8 *target_attr_ptr = NULL;
+	u8 wps_oui[4] = {0x00, 0x50, 0xF2, 0x04};
+
+	if (len_attr)
+		*len_attr = 0;
+
+	if ((wps_ie[0] != _VENDOR_SPECIFIC_IE_) ||
+	    (_rtw_memcmp(wps_ie + 2, wps_oui , 4) != _TRUE))
+		return attr_ptr;
+
+	/* 6 = 1(Element ID) + 1(Length) + 4(WPS OUI) */
+	attr_ptr = wps_ie + 6; /* goto first attr */
+
+	while (attr_ptr - wps_ie < wps_ielen) {
+		/* 4 = 2(Attribute ID) + 2(Length) */
+		u16 attr_id = RTW_GET_BE16(attr_ptr);
+		u16 attr_data_len = RTW_GET_BE16(attr_ptr + 2);
+		u16 attr_len = attr_data_len + 4;
+
+		/* RTW_INFO("%s attr_ptr:%p, id:%u, length:%u\n", __FUNCTION__, attr_ptr, attr_id, attr_data_len); */
+		if (attr_id == target_attr_id) {
+			target_attr_ptr = attr_ptr;
+
+			if (buf_attr)
+				_rtw_memcpy(buf_attr, attr_ptr, attr_len);
+
+			if (len_attr)
+				*len_attr = attr_len;
+
+			break;
+		} else {
+			attr_ptr += attr_len; /* goto next */
+		}
+
+	}
+
+	return target_attr_ptr;
+}
+
+/**
+ * rtw_get_wps_attr_content - Search a specific WPS attribute content from a given WPS IE
+ * @wps_ie: Address of WPS IE to search
+ * @wps_ielen: Length limit from wps_ie
+ * @target_attr_id: The attribute ID of WPS attribute to search
+ * @buf_content: If not NULL and the WPS attribute is found, WPS attribute content will be copied to the buf starting from buf_content
+ * @len_content: If not NULL and the WPS attribute is found, will set to the length of the WPS attribute content
+ *
+ * Returns: the address of the specific WPS attribute content found, or NULL
+ */
+u8 *rtw_get_wps_attr_content(u8 *wps_ie, uint wps_ielen, u16 target_attr_id , u8 *buf_content, uint *len_content)
+{
+	u8 *attr_ptr;
+	u32 attr_len;
+
+	if (len_content)
+		*len_content = 0;
+
+	attr_ptr = rtw_get_wps_attr(wps_ie, wps_ielen, target_attr_id, NULL, &attr_len);
+
+	if (attr_ptr && attr_len) {
+		if (buf_content)
+			_rtw_memcpy(buf_content, attr_ptr + 4, attr_len - 4);
+
+		if (len_content)
+			*len_content = attr_len - 4;
+
+		return attr_ptr + 4;
+	}
+
+	return NULL;
+}
+
+static int rtw_ieee802_11_parse_vendor_specific(u8 *pos, uint elen,
+		struct rtw_ieee802_11_elems *elems,
+		int show_errors)
+{
+	unsigned int oui;
+
+	/* first 3 bytes in vendor specific information element are the IEEE
+	 * OUI of the vendor. The following byte is used a vendor specific
+	 * sub-type. */
+	if (elen < 4) {
+		if (show_errors) {
+			RTW_INFO("short vendor specific "
+				 "information element ignored (len=%lu)\n",
+				 (unsigned long) elen);
+		}
+		return -1;
+	}
+
+	oui = RTW_GET_BE24(pos);
+	switch (oui) {
+	case OUI_MICROSOFT:
+		/* Microsoft/Wi-Fi information elements are further typed and
+		 * subtyped */
+		switch (pos[3]) {
+		case 1:
+			/* Microsoft OUI (00:50:F2) with OUI Type 1:
+			 * real WPA information element */
+			elems->wpa_ie = pos;
+			elems->wpa_ie_len = elen;
+			break;
+		case WME_OUI_TYPE: /* this is a Wi-Fi WME info. element */
+			if (elen < 5) {
+				RTW_DBG("short WME "
+					"information element ignored "
+					"(len=%lu)\n",
+					(unsigned long) elen);
+				return -1;
+			}
+			switch (pos[4]) {
+			case WME_OUI_SUBTYPE_INFORMATION_ELEMENT:
+			case WME_OUI_SUBTYPE_PARAMETER_ELEMENT:
+				elems->wme = pos;
+				elems->wme_len = elen;
+				break;
+			case WME_OUI_SUBTYPE_TSPEC_ELEMENT:
+				elems->wme_tspec = pos;
+				elems->wme_tspec_len = elen;
+				break;
+			default:
+				RTW_DBG("unknown WME "
+					"information element ignored "
+					"(subtype=%d len=%lu)\n",
+					pos[4], (unsigned long) elen);
+				return -1;
+			}
+			break;
+		case 4:
+			/* Wi-Fi Protected Setup (WPS) IE */
+			elems->wps_ie = pos;
+			elems->wps_ie_len = elen;
+			break;
+		default:
+			RTW_DBG("Unknown Microsoft "
+				"information element ignored "
+				"(type=%d len=%lu)\n",
+				pos[3], (unsigned long) elen);
+			return -1;
+		}
+		break;
+
+	case OUI_BROADCOM:
+		switch (pos[3]) {
+		case VENDOR_HT_CAPAB_OUI_TYPE:
+			elems->vendor_ht_cap = pos;
+			elems->vendor_ht_cap_len = elen;
+			break;
+		default:
+			RTW_DBG("Unknown Broadcom "
+				"information element ignored "
+				"(type=%d len=%lu)\n",
+				pos[3], (unsigned long) elen);
+			return -1;
+		}
+		break;
+
+	default:
+		RTW_DBG("unknown vendor specific information "
+			"element ignored (vendor OUI %02x:%02x:%02x "
+			"len=%lu)\n",
+			pos[0], pos[1], pos[2], (unsigned long) elen);
+		return -1;
+	}
+
+	return 0;
+
+}
+
+/**
+ * ieee802_11_parse_elems - Parse information elements in management frames
+ * @start: Pointer to the start of IEs
+ * @len: Length of IE buffer in octets
+ * @elems: Data structure for parsed elements
+ * @show_errors: Whether to show parsing errors in debug log
+ * Returns: Parsing result
+ */
+ParseRes rtw_ieee802_11_parse_elems(u8 *start, uint len,
+				    struct rtw_ieee802_11_elems *elems,
+				    int show_errors)
+{
+	uint left = len;
+	u8 *pos = start;
+	int unknown = 0;
+
+	_rtw_memset(elems, 0, sizeof(*elems));
+
+	while (left >= 2) {
+		u8 id, elen;
+
+		id = *pos++;
+		elen = *pos++;
+		left -= 2;
+
+		if (elen > left) {
+			if (show_errors) {
+				RTW_INFO("IEEE 802.11 element "
+					 "parse failed (id=%d elen=%d "
+					 "left=%lu)\n",
+					 id, elen, (unsigned long) left);
+			}
+			return ParseFailed;
+		}
+
+		switch (id) {
+		case WLAN_EID_SSID:
+			elems->ssid = pos;
+			elems->ssid_len = elen;
+			break;
+		case WLAN_EID_SUPP_RATES:
+			elems->supp_rates = pos;
+			elems->supp_rates_len = elen;
+			break;
+		case WLAN_EID_FH_PARAMS:
+			elems->fh_params = pos;
+			elems->fh_params_len = elen;
+			break;
+		case WLAN_EID_DS_PARAMS:
+			elems->ds_params = pos;
+			elems->ds_params_len = elen;
+			break;
+		case WLAN_EID_CF_PARAMS:
+			elems->cf_params = pos;
+			elems->cf_params_len = elen;
+			break;
+		case WLAN_EID_TIM:
+			elems->tim = pos;
+			elems->tim_len = elen;
+			break;
+		case WLAN_EID_IBSS_PARAMS:
+			elems->ibss_params = pos;
+			elems->ibss_params_len = elen;
+			break;
+		case WLAN_EID_CHALLENGE:
+			elems->challenge = pos;
+			elems->challenge_len = elen;
+			break;
+		case WLAN_EID_ERP_INFO:
+			elems->erp_info = pos;
+			elems->erp_info_len = elen;
+			break;
+		case WLAN_EID_EXT_SUPP_RATES:
+			elems->ext_supp_rates = pos;
+			elems->ext_supp_rates_len = elen;
+			break;
+		case WLAN_EID_VENDOR_SPECIFIC:
+			if (rtw_ieee802_11_parse_vendor_specific(pos, elen,
+					elems,
+					show_errors))
+				unknown++;
+			break;
+		case WLAN_EID_RSN:
+			elems->rsn_ie = pos;
+			elems->rsn_ie_len = elen;
+			break;
+		case WLAN_EID_PWR_CAPABILITY:
+			elems->power_cap = pos;
+			elems->power_cap_len = elen;
+			break;
+		case WLAN_EID_SUPPORTED_CHANNELS:
+			elems->supp_channels = pos;
+			elems->supp_channels_len = elen;
+			break;
+		case WLAN_EID_MOBILITY_DOMAIN:
+			elems->mdie = pos;
+			elems->mdie_len = elen;
+			break;
+		case WLAN_EID_FAST_BSS_TRANSITION:
+			elems->ftie = pos;
+			elems->ftie_len = elen;
+			break;
+		case WLAN_EID_TIMEOUT_INTERVAL:
+			elems->timeout_int = pos;
+			elems->timeout_int_len = elen;
+			break;
+		case WLAN_EID_HT_CAP:
+			elems->ht_capabilities = pos;
+			elems->ht_capabilities_len = elen;
+			break;
+		case WLAN_EID_HT_OPERATION:
+			elems->ht_operation = pos;
+			elems->ht_operation_len = elen;
+			break;
+		case WLAN_EID_VHT_CAPABILITY:
+			elems->vht_capabilities = pos;
+			elems->vht_capabilities_len = elen;
+			break;
+		case WLAN_EID_VHT_OPERATION:
+			elems->vht_operation = pos;
+			elems->vht_operation_len = elen;
+			break;
+		case WLAN_EID_VHT_OP_MODE_NOTIFY:
+			elems->vht_op_mode_notify = pos;
+			elems->vht_op_mode_notify_len = elen;
+			break;
+		case _EID_RRM_EN_CAP_IE_:
+			elems->rm_en_cap = pos;
+			elems->rm_en_cap_len = elen;
+			break;
+#ifdef CONFIG_RTW_MESH
+		case WLAN_EID_PREQ:
+			elems->preq = pos;
+			elems->preq_len = elen;
+			break;
+		case WLAN_EID_PREP:
+			elems->prep = pos;
+			elems->prep_len = elen;
+			break;
+		case WLAN_EID_PERR:
+			elems->perr = pos;
+			elems->perr_len = elen;
+			break;
+		case WLAN_EID_RANN:
+			elems->rann = pos;
+			elems->rann_len = elen;
+			break;
+#endif
+		default:
+			unknown++;
+			if (!show_errors)
+				break;
+			RTW_DBG("IEEE 802.11 element parse "
+				"ignored unknown element (id=%d elen=%d)\n",
+				id, elen);
+			break;
+		}
+
+		left -= elen;
+		pos += elen;
+	}
+
+	if (left)
+		return ParseFailed;
+
+	return unknown ? ParseUnknown : ParseOK;
+
+}
+
+static u8 key_char2num(u8 ch);
+static u8 key_char2num(u8 ch)
+{
+	if ((ch >= '0') && (ch <= '9'))
+		return ch - '0';
+	else if ((ch >= 'a') && (ch <= 'f'))
+		return ch - 'a' + 10;
+	else if ((ch >= 'A') && (ch <= 'F'))
+		return ch - 'A' + 10;
+	else
+		return 0xff;
+}
+
+u8 str_2char2num(u8 hch, u8 lch);
+u8 str_2char2num(u8 hch, u8 lch)
+{
+	return (key_char2num(hch) * 10) + key_char2num(lch);
+}
+
+u8 key_2char2num(u8 hch, u8 lch);
+u8 key_2char2num(u8 hch, u8 lch)
+{
+	return (key_char2num(hch) << 4) | key_char2num(lch);
+}
+
+void macstr2num(u8 *dst, u8 *src);
+void macstr2num(u8 *dst, u8 *src)
+{
+	int	jj, kk;
+	for (jj = 0, kk = 0; jj < ETH_ALEN; jj++, kk += 3)
+		dst[jj] = key_2char2num(src[kk], src[kk + 1]);
+}
+
+u8 convert_ip_addr(u8 hch, u8 mch, u8 lch)
+{
+	return (key_char2num(hch) * 100) + (key_char2num(mch) * 10) + key_char2num(lch);
+}
+
+#ifdef CONFIG_PLATFORM_INTEL_BYT
+#define MAC_ADDRESS_LEN 12
+
+int rtw_get_mac_addr_intel(unsigned char *buf)
+{
+	int ret = 0;
+	int i;
+	struct file *fp = NULL;
+	mm_segment_t oldfs;
+	unsigned char c_mac[MAC_ADDRESS_LEN];
+	char fname[] = "/config/wifi/mac.txt";
+	int jj, kk;
+
+	RTW_INFO("%s Enter\n", __FUNCTION__);
+
+	ret = rtw_retrieve_from_file(fname, c_mac, MAC_ADDRESS_LEN);
+	if (ret < MAC_ADDRESS_LEN)
+		return -1;
+
+	for (jj = 0, kk = 0; jj < ETH_ALEN; jj++, kk += 2)
+		buf[jj] = key_2char2num(c_mac[kk], c_mac[kk + 1]);
+
+	RTW_INFO("%s: read from file mac address: "MAC_FMT"\n",
+		 __FUNCTION__, MAC_ARG(buf));
+
+	return 0;
+}
+#endif /* CONFIG_PLATFORM_INTEL_BYT */
+
+/*
+ * Description:
+ * rtw_check_invalid_mac_address:
+ * This is only used for checking mac address valid or not.
+ *
+ * Input:
+ * adapter: mac_address pointer.
+ * check_local_bit: check locally bit or not.
+ *
+ * Output:
+ * _TRUE: The mac address is invalid.
+ * _FALSE: The mac address is valid.
+ *
+ * Auther: Isaac.Li
+ */
+u8 rtw_check_invalid_mac_address(u8 *mac_addr, u8 check_local_bit)
+{
+	u8 null_mac_addr[ETH_ALEN] = {0, 0, 0, 0, 0, 0};
+	u8 multi_mac_addr[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
+	u8 res = _FALSE;
+
+	if (_rtw_memcmp(mac_addr, null_mac_addr, ETH_ALEN)) {
+		res = _TRUE;
+		goto func_exit;
+	}
+
+	if (_rtw_memcmp(mac_addr, multi_mac_addr, ETH_ALEN)) {
+		res = _TRUE;
+		goto func_exit;
+	}
+
+	if (mac_addr[0] & BIT0) {
+		res = _TRUE;
+		goto func_exit;
+	}
+
+	if (check_local_bit == _TRUE) {
+		if (mac_addr[0] & BIT1) {
+			res = _TRUE;
+			goto func_exit;
+		}
+	}
+
+func_exit:
+	return res;
+}
+
+extern char *rtw_initmac;
+/**
+ * rtw_macaddr_cfg - Decide the mac address used
+ * @out: buf to store mac address decided
+ * @hw_mac_addr: mac address from efuse/epprom
+ */
+void rtw_macaddr_cfg(u8 *out, const u8 *hw_mac_addr)
+{
+#define DEFAULT_RANDOM_MACADDR 1
+	u8 mac[ETH_ALEN];
+
+	if (out == NULL) {
+		rtw_warn_on(1);
+		return;
+	}
+
+	/* Users specify the mac address */
+	if (rtw_initmac) {
+		int jj, kk;
+
+		for (jj = 0, kk = 0; jj < ETH_ALEN; jj++, kk += 3)
+			mac[jj] = key_2char2num(rtw_initmac[kk], rtw_initmac[kk + 1]);
+
+		goto err_chk;
+	}
+
+	/* platform specified */
+#ifdef CONFIG_PLATFORM_INTEL_BYT
+	if (rtw_get_mac_addr_intel(mac) == 0)
+		goto err_chk;
+#endif
+
+	/* Use the mac address stored in the Efuse */
+	if (hw_mac_addr) {
+		_rtw_memcpy(mac, hw_mac_addr, ETH_ALEN);
+		goto err_chk;
+	}
+
+err_chk:
+	if (rtw_check_invalid_mac_address(mac, _TRUE) == _TRUE) {
+#if DEFAULT_RANDOM_MACADDR
+		RTW_ERR("invalid mac addr:"MAC_FMT", assign random MAC\n", MAC_ARG(mac));
+		*((u32 *)(&mac[2])) = rtw_random32();
+		mac[0] = 0x00;
+		mac[1] = 0xe0;
+		mac[2] = 0x4c;
+#else
+		RTW_ERR("invalid mac addr:"MAC_FMT", assign default one\n", MAC_ARG(mac));
+		mac[0] = 0x00;
+		mac[1] = 0xe0;
+		mac[2] = 0x4c;
+		mac[3] = 0x87;
+		mac[4] = 0x00;
+		mac[5] = 0x00;
+#endif
+	}
+
+	_rtw_memcpy(out, mac, ETH_ALEN);
+	RTW_INFO("%s mac addr:"MAC_FMT"\n", __func__, MAC_ARG(out));
+}
+
+#ifdef CONFIG_80211N_HT
+void dump_ht_cap_ie_content(void *sel, const u8 *buf, u32 buf_len)
+{
+	if (buf_len != HT_CAP_IE_LEN) {
+		RTW_PRINT_SEL(sel, "Invalid HT capability IE len:%d != %d\n", buf_len, HT_CAP_IE_LEN);
+		return;
+	}
+
+	RTW_PRINT_SEL(sel, "cap_info:%02x%02x:%s\n", *(buf), *(buf + 1)
+		, GET_HT_CAP_ELE_CHL_WIDTH(buf) ? " 40MHz" : " 20MHz");
+	RTW_PRINT_SEL(sel, "A-MPDU Parameters:"HT_AMPDU_PARA_FMT"\n"
+		      , HT_AMPDU_PARA_ARG(HT_CAP_ELE_AMPDU_PARA(buf)));
+	RTW_PRINT_SEL(sel, "Supported MCS Set:"HT_SUP_MCS_SET_FMT"\n"
+		      , HT_SUP_MCS_SET_ARG(HT_CAP_ELE_SUP_MCS_SET(buf)));
+}
+
+void dump_ht_cap_ie(void *sel, const u8 *ie, u32 ie_len)
+{
+	const u8 *ht_cap_ie;
+	sint ht_cap_ielen;
+
+	ht_cap_ie = rtw_get_ie(ie, WLAN_EID_HT_CAP, &ht_cap_ielen, ie_len);
+	if (!ie || ht_cap_ie != ie)
+		return;
+
+	dump_ht_cap_ie_content(sel, ht_cap_ie + 2, ht_cap_ielen);
+}
+
+const char *const _ht_sc_offset_str[] = {
+	"SCN",
+	"SCA",
+	"SC-RSVD",
+	"SCB",
+};
+
+void dump_ht_op_ie_content(void *sel, const u8 *buf, u32 buf_len)
+{
+	if (buf_len != HT_OP_IE_LEN) {
+		RTW_PRINT_SEL(sel, "Invalid HT operation IE len:%d != %d\n", buf_len, HT_OP_IE_LEN);
+		return;
+	}
+
+	RTW_PRINT_SEL(sel, "ch:%u%s %s\n"
+		, GET_HT_OP_ELE_PRI_CHL(buf)
+		, GET_HT_OP_ELE_STA_CHL_WIDTH(buf) ? "" : " 20MHz only"
+		, ht_sc_offset_str(GET_HT_OP_ELE_2ND_CHL_OFFSET(buf))
+	);
+}
+
+void dump_ht_op_ie(void *sel, const u8 *ie, u32 ie_len)
+{
+	const u8 *ht_op_ie;
+	sint ht_op_ielen;
+
+	ht_op_ie = rtw_get_ie(ie, WLAN_EID_HT_OPERATION, &ht_op_ielen, ie_len);
+	if (!ie || ht_op_ie != ie)
+		return;
+
+	dump_ht_op_ie_content(sel, ht_op_ie + 2, ht_op_ielen);
+}
+#endif /* CONFIG_80211N_HT */
+
+void dump_ies(void *sel, const u8 *buf, u32 buf_len)
+{
+	const u8 *pos = buf;
+	u8 id, len;
+
+	while (pos - buf + 1 < buf_len) {
+		id = *pos;
+		len = *(pos + 1);
+
+		RTW_PRINT_SEL(sel, "%s ID:%u, LEN:%u\n", __FUNCTION__, id, len);
+#ifdef CONFIG_80211N_HT
+		dump_ht_cap_ie(sel, pos, len + 2);
+		dump_ht_op_ie(sel, pos, len + 2);
+#endif
+#ifdef CONFIG_80211AC_VHT
+		dump_vht_cap_ie(sel, pos, len + 2);
+		dump_vht_op_ie(sel, pos, len + 2);
+#endif
+		dump_wps_ie(sel, pos, len + 2);
+#ifdef CONFIG_P2P
+		dump_p2p_ie(sel, pos, len + 2);
+#ifdef CONFIG_WFD
+		dump_wfd_ie(sel, pos, len + 2);
+#endif
+#endif
+
+		pos += (2 + len);
+	}
+}
+
+void dump_wps_ie(void *sel, const u8 *ie, u32 ie_len)
+{
+	const u8 *pos = ie;
+	u16 id;
+	u16 len;
+
+	const u8 *wps_ie;
+	uint wps_ielen;
+
+	wps_ie = rtw_get_wps_ie(ie, ie_len, NULL, &wps_ielen);
+	if (wps_ie != ie || wps_ielen == 0)
+		return;
+
+	pos += 6;
+	while (pos - ie + 4 <= ie_len) {
+		id = RTW_GET_BE16(pos);
+		len = RTW_GET_BE16(pos + 2);
+
+		RTW_PRINT_SEL(sel, "%s ID:0x%04x, LEN:%u%s\n", __func__, id, len
+			, ((pos - ie + 4 + len) <= ie_len) ? "" : "(exceed ie_len)");
+
+		pos += (4 + len);
+	}
+}
+
+/**
+ * rtw_ies_get_chbw - get operation ch, bw, offset from IEs of BSS.
+ * @ies: pointer of the first tlv IE
+ * @ies_len: length of @ies
+ * @ch: pointer of ch, used as output
+ * @bw: pointer of bw, used as output
+ * @offset: pointer of offset, used as output
+ * @ht: check HT IEs
+ * @vht: check VHT IEs, if true imply ht is true
+ */
+void rtw_ies_get_chbw(u8 *ies, int ies_len, u8 *ch, u8 *bw, u8 *offset, u8 ht, u8 vht)
+{
+	u8 *p;
+	int	ie_len;
+
+	*ch = 0;
+	*bw = CHANNEL_WIDTH_20;
+	*offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
+
+	p = rtw_get_ie(ies, _DSSET_IE_, &ie_len, ies_len);
+	if (p && ie_len > 0)
+		*ch = *(p + 2);
+
+#ifdef CONFIG_80211N_HT
+	if (ht || vht) {
+		u8 *ht_cap_ie, *ht_op_ie;
+		int ht_cap_ielen, ht_op_ielen;
+
+		ht_cap_ie = rtw_get_ie(ies, EID_HTCapability, &ht_cap_ielen, ies_len);
+		if (ht_cap_ie && ht_cap_ielen) {
+			if (GET_HT_CAP_ELE_CHL_WIDTH(ht_cap_ie + 2))
+				*bw = CHANNEL_WIDTH_40;
+		}
+
+		ht_op_ie = rtw_get_ie(ies, EID_HTInfo, &ht_op_ielen, ies_len);
+		if (ht_op_ie && ht_op_ielen) {
+			if (*ch == 0)
+				*ch = GET_HT_OP_ELE_PRI_CHL(ht_op_ie + 2);
+			else if (*ch != 0 && *ch != GET_HT_OP_ELE_PRI_CHL(ht_op_ie + 2)) {
+				RTW_INFO("%s ch inconsistent, DSSS:%u, HT primary:%u\n"
+					, __func__, *ch, GET_HT_OP_ELE_PRI_CHL(ht_op_ie + 2));
+			}
+
+			if (!GET_HT_OP_ELE_STA_CHL_WIDTH(ht_op_ie + 2))
+				*bw = CHANNEL_WIDTH_20;
+
+			if (*bw == CHANNEL_WIDTH_40) {
+				switch (GET_HT_OP_ELE_2ND_CHL_OFFSET(ht_op_ie + 2)) {
+				case SCA:
+					*offset = HAL_PRIME_CHNL_OFFSET_LOWER;
+					break;
+				case SCB:
+					*offset = HAL_PRIME_CHNL_OFFSET_UPPER;
+					break;
+				}
+			}
+		}
+
+#ifdef CONFIG_80211AC_VHT
+		if (vht) {
+			u8 *vht_op_ie;
+			int vht_op_ielen;
+
+			vht_op_ie = rtw_get_ie(ies, EID_VHTOperation, &vht_op_ielen, ies_len);
+			if (vht_op_ie && vht_op_ielen) {
+				if (GET_VHT_OPERATION_ELE_CHL_WIDTH(vht_op_ie + 2) >= 1)
+					*bw = CHANNEL_WIDTH_80;
+			}
+		}
+#endif /* CONFIG_80211AC_VHT */
+
+	}
+#endif /* CONFIG_80211N_HT */
+}
+
+void rtw_bss_get_chbw(WLAN_BSSID_EX *bss, u8 *ch, u8 *bw, u8 *offset, u8 ht, u8 vht)
+{
+	rtw_ies_get_chbw(bss->IEs + sizeof(NDIS_802_11_FIXED_IEs)
+		, bss->IELength - sizeof(NDIS_802_11_FIXED_IEs)
+		, ch, bw, offset, ht, vht);
+
+	if (*ch == 0)
+		*ch = bss->Configuration.DSConfig;
+	else if (*ch != bss->Configuration.DSConfig) {
+		RTW_INFO("inconsistent ch - ies:%u bss->Configuration.DSConfig:%u\n"
+			 , *ch, bss->Configuration.DSConfig);
+		*ch = bss->Configuration.DSConfig;
+		rtw_warn_on(1);
+	}
+}
+
+/**
+ * rtw_is_chbw_grouped - test if the two ch settings can be grouped together
+ * @ch_a: ch of set a
+ * @bw_a: bw of set a
+ * @offset_a: offset of set a
+ * @ch_b: ch of set b
+ * @bw_b: bw of set b
+ * @offset_b: offset of set b
+ */
+bool rtw_is_chbw_grouped(u8 ch_a, u8 bw_a, u8 offset_a
+			 , u8 ch_b, u8 bw_b, u8 offset_b)
+{
+	bool is_grouped = _FALSE;
+
+	if (ch_a != ch_b) {
+		/* ch is different */
+		goto exit;
+	} else if ((bw_a == CHANNEL_WIDTH_40 || bw_a == CHANNEL_WIDTH_80)
+		   && (bw_b == CHANNEL_WIDTH_40 || bw_b == CHANNEL_WIDTH_80)
+		  ) {
+		if (offset_a != offset_b)
+			goto exit;
+	}
+
+	is_grouped = _TRUE;
+
+exit:
+	return is_grouped;
+}
+
+/**
+ * rtw_sync_chbw - obey g_ch, adjust g_bw, g_offset, bw, offset
+ * @req_ch: pointer of the request ch, may be modified further
+ * @req_bw: pointer of the request bw, may be modified further
+ * @req_offset: pointer of the request offset, may be modified further
+ * @g_ch: pointer of the ongoing group ch
+ * @g_bw: pointer of the ongoing group bw, may be modified further
+ * @g_offset: pointer of the ongoing group offset, may be modified further
+ */
+void rtw_sync_chbw(u8 *req_ch, u8 *req_bw, u8 *req_offset
+		   , u8 *g_ch, u8 *g_bw, u8 *g_offset)
+{
+
+	*req_ch = *g_ch;
+
+	if (*req_bw == CHANNEL_WIDTH_80 && *g_ch <= 14) {
+		/*2.4G ch, downgrade to 40Mhz */
+		*req_bw = CHANNEL_WIDTH_40;
+	}
+
+	switch (*req_bw) {
+	case CHANNEL_WIDTH_80:
+		if (*g_bw == CHANNEL_WIDTH_40 || *g_bw == CHANNEL_WIDTH_80)
+			*req_offset = *g_offset;
+		else if (*g_bw == CHANNEL_WIDTH_20)
+			rtw_get_offset_by_chbw(*req_ch, *req_bw, req_offset);
+
+		if (*req_offset == HAL_PRIME_CHNL_OFFSET_DONT_CARE) {
+			RTW_ERR("%s req 80MHz BW without offset, down to 20MHz\n", __func__);
+			rtw_warn_on(1);
+			*req_bw = CHANNEL_WIDTH_20;
+		}
+		break;
+	case CHANNEL_WIDTH_40:
+		if (*g_bw == CHANNEL_WIDTH_40 || *g_bw == CHANNEL_WIDTH_80)
+			*req_offset = *g_offset;
+		else if (*g_bw == CHANNEL_WIDTH_20)
+			rtw_get_offset_by_chbw(*req_ch, *req_bw, req_offset);
+
+		if (*req_offset == HAL_PRIME_CHNL_OFFSET_DONT_CARE) {
+			RTW_ERR("%s req 40MHz BW without offset, down to 20MHz\n", __func__);
+			rtw_warn_on(1);
+			*req_bw = CHANNEL_WIDTH_20;
+		}
+		break;
+	case CHANNEL_WIDTH_20:
+		*req_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
+		break;
+	default:
+		RTW_ERR("%s req unsupported BW:%u\n", __func__, *req_bw);
+		rtw_warn_on(1);
+	}
+
+	if (*req_bw > *g_bw) {
+		*g_bw = *req_bw;
+		*g_offset = *req_offset;
+	}
+}
+
+/**
+ * rtw_get_p2p_merged_len - Get merged ie length from muitiple p2p ies.
+ * @in_ie: Pointer of the first p2p ie
+ * @in_len: Total len of muiltiple p2p ies
+ * Returns: Length of merged p2p ie length
+ */
+u32 rtw_get_p2p_merged_ies_len(u8 *in_ie, u32 in_len)
+{
+	PNDIS_802_11_VARIABLE_IEs	pIE;
+	u8 OUI[4] = { 0x50, 0x6f, 0x9a, 0x09 };
+	int i = 0;
+	int len = 0;
+
+	while (i < in_len) {
+		pIE = (PNDIS_802_11_VARIABLE_IEs)(in_ie + i);
+
+		if (pIE->ElementID == _VENDOR_SPECIFIC_IE_ && _rtw_memcmp(pIE->data, OUI, 4)) {
+			len += pIE->Length - 4; /* 4 is P2P OUI length, don't count it in this loop */
+		}
+
+		i += (pIE->Length + 2);
+	}
+
+	return len + 4;	/* Append P2P OUI length at last. */
+}
+
+/**
+ * rtw_p2p_merge_ies - Merge muitiple p2p ies into one
+ * @in_ie: Pointer of the first p2p ie
+ * @in_len: Total len of muiltiple p2p ies
+ * @merge_ie: Pointer of merged ie
+ * Returns: Length of merged p2p ie
+ */
+int rtw_p2p_merge_ies(u8 *in_ie, u32 in_len, u8 *merge_ie)
+{
+	PNDIS_802_11_VARIABLE_IEs	pIE;
+	u8 len = 0;
+	u8 OUI[4] = { 0x50, 0x6f, 0x9a, 0x09 };
+	u8 ELOUI[6] = { 0xDD, 0x00, 0x50, 0x6f, 0x9a, 0x09 };	/* EID;Len;OUI, Len would copy at the end of function */
+	int i = 0;
+
+	if (merge_ie != NULL) {
+		/* Set first P2P OUI */
+		_rtw_memcpy(merge_ie, ELOUI, 6);
+		merge_ie += 6;
+
+		while (i < in_len) {
+			pIE = (PNDIS_802_11_VARIABLE_IEs)(in_ie + i);
+
+			/* Take out the rest of P2P OUIs */
+			if (pIE->ElementID == _VENDOR_SPECIFIC_IE_ && _rtw_memcmp(pIE->data, OUI, 4)) {
+				_rtw_memcpy(merge_ie, pIE->data + 4, pIE->Length - 4);
+				len += pIE->Length - 4;
+				merge_ie += pIE->Length - 4;
+			}
+
+			i += (pIE->Length + 2);
+		}
+
+		return len + 4;	/* 4 is for P2P OUI */
+
+	}
+
+	return 0;
+}
+
+void dump_p2p_ie(void *sel, const u8 *ie, u32 ie_len)
+{
+	const u8 *pos = ie;
+	u8 id;
+	u16 len;
+
+	const u8 *p2p_ie;
+	uint p2p_ielen;
+
+	p2p_ie = rtw_get_p2p_ie(ie, ie_len, NULL, &p2p_ielen);
+	if (p2p_ie != ie || p2p_ielen == 0)
+		return;
+
+	pos += 6;
+	while (pos - ie + 3 <= ie_len) {
+		id = *pos;
+		len = RTW_GET_LE16(pos + 1);
+
+		RTW_PRINT_SEL(sel, "%s ID:%u, LEN:%u%s\n", __func__, id, len
+			, ((pos - ie + 3 + len) <= ie_len) ? "" : "(exceed ie_len)");
+
+		pos += (3 + len);
+	}
+}
+
+/**
+ * rtw_get_p2p_ie - Search P2P IE from a series of IEs
+ * @in_ie: Address of IEs to search
+ * @in_len: Length limit from in_ie
+ * @p2p_ie: If not NULL and P2P IE is found, P2P IE will be copied to the buf starting from p2p_ie
+ * @p2p_ielen: If not NULL and P2P IE is found, will set to the length of the entire P2P IE
+ *
+ * Returns: The address of the P2P IE found, or NULL
+ */
+u8 *rtw_get_p2p_ie(const u8 *in_ie, int in_len, u8 *p2p_ie, uint *p2p_ielen)
+{
+	uint cnt;
+	const u8 *p2p_ie_ptr = NULL;
+	u8 eid, p2p_oui[4] = {0x50, 0x6F, 0x9A, 0x09};
+
+	if (p2p_ielen)
+		*p2p_ielen = 0;
+
+	if (!in_ie || in_len < 0) {
+		rtw_warn_on(1);
+		return (u8 *)p2p_ie_ptr;
+	}
+
+	if (in_len <= 0)
+		return (u8 *)p2p_ie_ptr;
+
+	cnt = 0;
+
+	while (cnt + 1 + 4 < in_len) {
+		eid = in_ie[cnt];
+
+		if (cnt + 1 + 4 >= MAX_IE_SZ) {
+			rtw_warn_on(1);
+			return NULL;
+		}
+
+		if (eid == WLAN_EID_VENDOR_SPECIFIC && _rtw_memcmp(&in_ie[cnt + 2], p2p_oui, 4) == _TRUE) {
+			p2p_ie_ptr = in_ie + cnt;
+
+			if (p2p_ie)
+				_rtw_memcpy(p2p_ie, &in_ie[cnt], in_ie[cnt + 1] + 2);
+
+			if (p2p_ielen)
+				*p2p_ielen = in_ie[cnt + 1] + 2;
+
+			break;
+		} else
+			cnt += in_ie[cnt + 1] + 2;
+
+	}
+
+	return (u8 *)p2p_ie_ptr;
+}
+
+/**
+ * rtw_get_p2p_attr - Search a specific P2P attribute from a given P2P IE
+ * @p2p_ie: Address of P2P IE to search
+ * @p2p_ielen: Length limit from p2p_ie
+ * @target_attr_id: The attribute ID of P2P attribute to search
+ * @buf_attr: If not NULL and the P2P attribute is found, P2P attribute will be copied to the buf starting from buf_attr
+ * @len_attr: If not NULL and the P2P attribute is found, will set to the length of the entire P2P attribute
+ *
+ * Returns: the address of the specific WPS attribute found, or NULL
+ */
+u8 *rtw_get_p2p_attr(u8 *p2p_ie, uint p2p_ielen, u8 target_attr_id , u8 *buf_attr, u32 *len_attr)
+{
+	u8 *attr_ptr = NULL;
+	u8 *target_attr_ptr = NULL;
+	u8 p2p_oui[4] = {0x50, 0x6F, 0x9A, 0x09};
+
+	if (len_attr)
+		*len_attr = 0;
+
+	if (!p2p_ie
+	    || p2p_ielen <= 6
+	    || (p2p_ie[0] != WLAN_EID_VENDOR_SPECIFIC)
+	    || (_rtw_memcmp(p2p_ie + 2, p2p_oui, 4) != _TRUE))
+		return attr_ptr;
+
+	/* 6 = 1(Element ID) + 1(Length) + 3 (OUI) + 1(OUI Type) */
+	attr_ptr = p2p_ie + 6; /* goto first attr */
+
+	while ((attr_ptr - p2p_ie + 3) <= p2p_ielen) {
+		/* 3 = 1(Attribute ID) + 2(Length) */
+		u8 attr_id = *attr_ptr;
+		u16 attr_data_len = RTW_GET_LE16(attr_ptr + 1);
+		u16 attr_len = attr_data_len + 3;
+
+		if (0)
+			RTW_INFO("%s attr_ptr:%p, id:%u, length:%u\n", __func__, attr_ptr, attr_id, attr_data_len);
+
+		if ((attr_ptr - p2p_ie + attr_len) > p2p_ielen)
+			break;
+
+		if (attr_id == target_attr_id) {
+			target_attr_ptr = attr_ptr;
+
+			if (buf_attr)
+				_rtw_memcpy(buf_attr, attr_ptr, attr_len);
+
+			if (len_attr)
+				*len_attr = attr_len;
+
+			break;
+		} else
+			attr_ptr += attr_len;
+	}
+
+	return target_attr_ptr;
+}
+
+/**
+ * rtw_get_p2p_attr_content - Search a specific P2P attribute content from a given P2P IE
+ * @p2p_ie: Address of P2P IE to search
+ * @p2p_ielen: Length limit from p2p_ie
+ * @target_attr_id: The attribute ID of P2P attribute to search
+ * @buf_content: If not NULL and the P2P attribute is found, P2P attribute content will be copied to the buf starting from buf_content
+ * @len_content: If not NULL and the P2P attribute is found, will set to the length of the P2P attribute content
+ *
+ * Returns: the address of the specific P2P attribute content found, or NULL
+ */
+u8 *rtw_get_p2p_attr_content(u8 *p2p_ie, uint p2p_ielen, u8 target_attr_id , u8 *buf_content, uint *len_content)
+{
+	u8 *attr_ptr;
+	u32 attr_len;
+
+	if (len_content)
+		*len_content = 0;
+
+	attr_ptr = rtw_get_p2p_attr(p2p_ie, p2p_ielen, target_attr_id, NULL, &attr_len);
+
+	if (attr_ptr && attr_len) {
+		if (buf_content)
+			_rtw_memcpy(buf_content, attr_ptr + 3, attr_len - 3);
+
+		if (len_content)
+			*len_content = attr_len - 3;
+
+		return attr_ptr + 3;
+	}
+
+	return NULL;
+}
+
+u32 rtw_set_p2p_attr_content(u8 *pbuf, u8 attr_id, u16 attr_len, u8 *pdata_attr)
+{
+	u32 a_len;
+
+	*pbuf = attr_id;
+
+	/* *(u16*)(pbuf + 1) = cpu_to_le16(attr_len); */
+	RTW_PUT_LE16(pbuf + 1, attr_len);
+
+	if (pdata_attr)
+		_rtw_memcpy(pbuf + 3, pdata_attr, attr_len);
+
+	a_len = attr_len + 3;
+
+	return a_len;
+}
+
+uint rtw_del_p2p_ie(u8 *ies, uint ies_len_ori, const char *msg)
+{
+#define DBG_DEL_P2P_IE 0
+
+	u8 *target_ie;
+	u32 target_ie_len;
+	uint ies_len = ies_len_ori;
+	int index = 0;
+
+	while (1) {
+		target_ie = rtw_get_p2p_ie(ies, ies_len, NULL, &target_ie_len);
+		if (target_ie && target_ie_len) {
+			u8 *next_ie = target_ie + target_ie_len;
+			uint remain_len = ies_len - (next_ie - ies);
+
+			if (DBG_DEL_P2P_IE && msg) {
+				RTW_INFO("%s %d before\n", __func__, index);
+				dump_ies(RTW_DBGDUMP, ies, ies_len);
+
+				RTW_INFO("ies:%p, ies_len:%u\n", ies, ies_len);
+				RTW_INFO("target_ie:%p, target_ie_len:%u\n", target_ie, target_ie_len);
+				RTW_INFO("next_ie:%p, remain_len:%u\n", next_ie, remain_len);
+			}
+
+			_rtw_memmove(target_ie, next_ie, remain_len);
+			_rtw_memset(target_ie + remain_len, 0, target_ie_len);
+			ies_len -= target_ie_len;
+
+			if (DBG_DEL_P2P_IE && msg) {
+				RTW_INFO("%s %d after\n", __func__, index);
+				dump_ies(RTW_DBGDUMP, ies, ies_len);
+			}
+
+			index++;
+		} else
+			break;
+	}
+
+	return ies_len;
+}
+
+uint rtw_del_p2p_attr(u8 *ie, uint ielen_ori, u8 attr_id)
+{
+#define DBG_DEL_P2P_ATTR 0
+
+	u8 *target_attr;
+	u32 target_attr_len;
+	uint ielen = ielen_ori;
+	int index = 0;
+
+	while (1) {
+		target_attr = rtw_get_p2p_attr(ie, ielen, attr_id, NULL, &target_attr_len);
+		if (target_attr && target_attr_len) {
+			u8 *next_attr = target_attr + target_attr_len;
+			uint remain_len = ielen - (next_attr - ie);
+
+			if (DBG_DEL_P2P_ATTR) {
+				RTW_INFO("%s %d before\n", __func__, index);
+				dump_ies(RTW_DBGDUMP, ie, ielen);
+
+				RTW_INFO("ie:%p, ielen:%u\n", ie, ielen);
+				RTW_INFO("target_attr:%p, target_attr_len:%u\n", target_attr, target_attr_len);
+				RTW_INFO("next_attr:%p, remain_len:%u\n", next_attr, remain_len);
+			}
+
+			_rtw_memmove(target_attr, next_attr, remain_len);
+			_rtw_memset(target_attr + remain_len, 0, target_attr_len);
+			*(ie + 1) -= target_attr_len;
+			ielen -= target_attr_len;
+
+			if (DBG_DEL_P2P_ATTR) {
+				RTW_INFO("%s %d after\n", __func__, index);
+				dump_ies(RTW_DBGDUMP, ie, ielen);
+			}
+
+			index++;
+		} else
+			break;
+	}
+
+	return ielen;
+}
+
+inline u8 *rtw_bss_ex_get_p2p_ie(WLAN_BSSID_EX *bss_ex, u8 *p2p_ie, uint *p2p_ielen)
+{
+	return rtw_get_p2p_ie(BSS_EX_TLV_IES(bss_ex), BSS_EX_TLV_IES_LEN(bss_ex), p2p_ie, p2p_ielen);
+}
+
+void rtw_bss_ex_del_p2p_ie(WLAN_BSSID_EX *bss_ex)
+{
+#define DBG_BSS_EX_DEL_P2P_IE 0
+
+	u8 *ies = BSS_EX_TLV_IES(bss_ex);
+	uint ies_len_ori = BSS_EX_TLV_IES_LEN(bss_ex);
+	uint ies_len;
+
+	ies_len = rtw_del_p2p_ie(ies, ies_len_ori, DBG_BSS_EX_DEL_P2P_IE ? __func__ : NULL);
+	bss_ex->IELength -= ies_len_ori - ies_len;
+}
+
+void rtw_bss_ex_del_p2p_attr(WLAN_BSSID_EX *bss_ex, u8 attr_id)
+{
+#define DBG_BSS_EX_DEL_P2P_ATTR 0
+
+	u8 *ies = BSS_EX_TLV_IES(bss_ex);
+	uint ies_len = BSS_EX_TLV_IES_LEN(bss_ex);
+
+	u8 *ie;
+	uint ie_len, ie_len_ori;
+
+	int index = 0;
+
+	while (1) {
+		ie = rtw_get_p2p_ie(ies, ies_len, NULL, &ie_len_ori);
+		if (ie) {
+			u8 *next_ie_ori = ie + ie_len_ori;
+			uint remain_len = bss_ex->IELength - (next_ie_ori - bss_ex->IEs);
+			u8 has_target_attr = 0;
+
+			if (DBG_BSS_EX_DEL_P2P_ATTR) {
+				if (rtw_get_p2p_attr(ie, ie_len_ori, attr_id, NULL, NULL)) {
+					RTW_INFO("%s %d before\n", __func__, index);
+					dump_ies(RTW_DBGDUMP, BSS_EX_TLV_IES(bss_ex), BSS_EX_TLV_IES_LEN(bss_ex));
+
+					RTW_INFO("ies:%p, ies_len:%u\n", ies, ies_len);
+					RTW_INFO("ie:%p, ie_len_ori:%u\n", ie, ie_len_ori);
+					RTW_INFO("next_ie_ori:%p, remain_len:%u\n", next_ie_ori, remain_len);
+					has_target_attr = 1;
+				}
+			}
+
+			ie_len = rtw_del_p2p_attr(ie, ie_len_ori, attr_id);
+			if (ie_len != ie_len_ori) {
+				u8 *next_ie = ie + ie_len;
+
+				_rtw_memmove(next_ie, next_ie_ori, remain_len);
+				_rtw_memset(next_ie + remain_len, 0, ie_len_ori - ie_len);
+				bss_ex->IELength -= ie_len_ori - ie_len;
+
+				ies = next_ie;
+			} else
+				ies = next_ie_ori;
+
+			if (DBG_BSS_EX_DEL_P2P_ATTR) {
+				if (has_target_attr) {
+					RTW_INFO("%s %d after\n", __func__, index);
+					dump_ies(RTW_DBGDUMP, BSS_EX_TLV_IES(bss_ex), BSS_EX_TLV_IES_LEN(bss_ex));
+				}
+			}
+
+			ies_len = remain_len;
+
+			index++;
+		} else
+			break;
+	}
+}
+
+void dump_wfd_ie(void *sel, const u8 *ie, u32 ie_len)
+{
+	const u8 *pos = ie;
+	u8 id;
+	u16 len;
+
+	const u8 *wfd_ie;
+	uint wfd_ielen;
+
+	wfd_ie = rtw_get_wfd_ie(ie, ie_len, NULL, &wfd_ielen);
+	if (wfd_ie != ie || wfd_ielen == 0)
+		return;
+
+	pos += 6;
+	while (pos - ie + 3 <= ie_len) {
+		id = *pos;
+		len = RTW_GET_BE16(pos + 1);
+
+		RTW_PRINT_SEL(sel, "%s ID:%u, LEN:%u%s\n", __func__, id, len
+			, ((pos - ie + 3 + len) <= ie_len) ? "" : "(exceed ie_len)");
+
+		pos += (3 + len);
+	}
+}
+
+/**
+ * rtw_get_wfd_ie - Search WFD IE from a series of IEs
+ * @in_ie: Address of IEs to search
+ * @in_len: Length limit from in_ie
+ * @wfd_ie: If not NULL and WFD IE is found, WFD IE will be copied to the buf starting from wfd_ie
+ * @wfd_ielen: If not NULL and WFD IE is found, will set to the length of the entire WFD IE
+ *
+ * Returns: The address of the P2P IE found, or NULL
+ */
+u8 *rtw_get_wfd_ie(const u8 *in_ie, int in_len, u8 *wfd_ie, uint *wfd_ielen)
+{
+	uint cnt;
+	const u8 *wfd_ie_ptr = NULL;
+	u8 eid, wfd_oui[4] = {0x50, 0x6F, 0x9A, 0x0A};
+
+	if (wfd_ielen)
+		*wfd_ielen = 0;
+
+	if (!in_ie || in_len < 0) {
+		rtw_warn_on(1);
+		return (u8 *)wfd_ie_ptr;
+	}
+
+	if (in_len <= 0)
+		return (u8 *)wfd_ie_ptr;
+
+	cnt = 0;
+
+	while (cnt + 1 + 4 < in_len) {
+		eid = in_ie[cnt];
+
+		if (cnt + 1 + 4 >= MAX_IE_SZ) {
+			rtw_warn_on(1);
+			return NULL;
+		}
+
+		if (eid == WLAN_EID_VENDOR_SPECIFIC && _rtw_memcmp(&in_ie[cnt + 2], wfd_oui, 4) == _TRUE) {
+			wfd_ie_ptr = in_ie + cnt;
+
+			if (wfd_ie)
+				_rtw_memcpy(wfd_ie, &in_ie[cnt], in_ie[cnt + 1] + 2);
+
+			if (wfd_ielen)
+				*wfd_ielen = in_ie[cnt + 1] + 2;
+
+			break;
+		} else
+			cnt += in_ie[cnt + 1] + 2;
+
+	}
+
+	return (u8 *)wfd_ie_ptr;
+}
+
+/**
+ * rtw_get_wfd_attr - Search a specific WFD attribute from a given WFD IE
+ * @wfd_ie: Address of WFD IE to search
+ * @wfd_ielen: Length limit from wfd_ie
+ * @target_attr_id: The attribute ID of WFD attribute to search
+ * @buf_attr: If not NULL and the WFD attribute is found, WFD attribute will be copied to the buf starting from buf_attr
+ * @len_attr: If not NULL and the WFD attribute is found, will set to the length of the entire WFD attribute
+ *
+ * Returns: the address of the specific WPS attribute found, or NULL
+ */
+u8 *rtw_get_wfd_attr(u8 *wfd_ie, uint wfd_ielen, u8 target_attr_id, u8 *buf_attr, u32 *len_attr)
+{
+	u8 *attr_ptr = NULL;
+	u8 *target_attr_ptr = NULL;
+	u8 wfd_oui[4] = {0x50, 0x6F, 0x9A, 0x0A};
+
+	if (len_attr)
+		*len_attr = 0;
+
+	if (!wfd_ie
+	    || wfd_ielen <= 6
+	    || (wfd_ie[0] != WLAN_EID_VENDOR_SPECIFIC)
+	    || (_rtw_memcmp(wfd_ie + 2, wfd_oui, 4) != _TRUE))
+		return attr_ptr;
+
+	/* 6 = 1(Element ID) + 1(Length) + 3 (OUI) + 1(OUI Type) */
+	attr_ptr = wfd_ie + 6; /* goto first attr */
+
+	while ((attr_ptr - wfd_ie + 3) <= wfd_ielen) {
+		/* 3 = 1(Attribute ID) + 2(Length) */
+		u8 attr_id = *attr_ptr;
+		u16 attr_data_len = RTW_GET_BE16(attr_ptr + 1);
+		u16 attr_len = attr_data_len + 3;
+
+		if (0)
+			RTW_INFO("%s attr_ptr:%p, id:%u, length:%u\n", __func__, attr_ptr, attr_id, attr_data_len);
+
+		if ((attr_ptr - wfd_ie + attr_len) > wfd_ielen)
+			break;
+
+		if (attr_id == target_attr_id) {
+			target_attr_ptr = attr_ptr;
+
+			if (buf_attr)
+				_rtw_memcpy(buf_attr, attr_ptr, attr_len);
+
+			if (len_attr)
+				*len_attr = attr_len;
+
+			break;
+		} else
+			attr_ptr += attr_len;
+	}
+
+	return target_attr_ptr;
+}
+
+/**
+ * rtw_get_wfd_attr_content - Search a specific WFD attribute content from a given WFD IE
+ * @wfd_ie: Address of WFD IE to search
+ * @wfd_ielen: Length limit from wfd_ie
+ * @target_attr_id: The attribute ID of WFD attribute to search
+ * @buf_content: If not NULL and the WFD attribute is found, WFD attribute content will be copied to the buf starting from buf_content
+ * @len_content: If not NULL and the WFD attribute is found, will set to the length of the WFD attribute content
+ *
+ * Returns: the address of the specific WFD attribute content found, or NULL
+ */
+u8 *rtw_get_wfd_attr_content(u8 *wfd_ie, uint wfd_ielen, u8 target_attr_id, u8 *buf_content, uint *len_content)
+{
+	u8 *attr_ptr;
+	u32 attr_len;
+
+	if (len_content)
+		*len_content = 0;
+
+	attr_ptr = rtw_get_wfd_attr(wfd_ie, wfd_ielen, target_attr_id, NULL, &attr_len);
+
+	if (attr_ptr && attr_len) {
+		if (buf_content)
+			_rtw_memcpy(buf_content, attr_ptr + 3, attr_len - 3);
+
+		if (len_content)
+			*len_content = attr_len - 3;
+
+		return attr_ptr + 3;
+	}
+
+	return NULL;
+}
+
+uint rtw_del_wfd_ie(u8 *ies, uint ies_len_ori, const char *msg)
+{
+#define DBG_DEL_WFD_IE 0
+
+	u8 *target_ie;
+	u32 target_ie_len;
+	uint ies_len = ies_len_ori;
+	int index = 0;
+
+	while (1) {
+		target_ie = rtw_get_wfd_ie(ies, ies_len, NULL, &target_ie_len);
+		if (target_ie && target_ie_len) {
+			u8 *next_ie = target_ie + target_ie_len;
+			uint remain_len = ies_len - (next_ie - ies);
+
+			if (DBG_DEL_WFD_IE && msg) {
+				RTW_INFO("%s %d before\n", __func__, index);
+				dump_ies(RTW_DBGDUMP, ies, ies_len);
+
+				RTW_INFO("ies:%p, ies_len:%u\n", ies, ies_len);
+				RTW_INFO("target_ie:%p, target_ie_len:%u\n", target_ie, target_ie_len);
+				RTW_INFO("next_ie:%p, remain_len:%u\n", next_ie, remain_len);
+			}
+
+			_rtw_memmove(target_ie, next_ie, remain_len);
+			_rtw_memset(target_ie + remain_len, 0, target_ie_len);
+			ies_len -= target_ie_len;
+
+			if (DBG_DEL_WFD_IE && msg) {
+				RTW_INFO("%s %d after\n", __func__, index);
+				dump_ies(RTW_DBGDUMP, ies, ies_len);
+			}
+
+			index++;
+		} else
+			break;
+	}
+
+	return ies_len;
+}
+
+uint rtw_del_wfd_attr(u8 *ie, uint ielen_ori, u8 attr_id)
+{
+#define DBG_DEL_WFD_ATTR 0
+
+	u8 *target_attr;
+	u32 target_attr_len;
+	uint ielen = ielen_ori;
+	int index = 0;
+
+	while (1) {
+		target_attr = rtw_get_wfd_attr(ie, ielen, attr_id, NULL, &target_attr_len);
+		if (target_attr && target_attr_len) {
+			u8 *next_attr = target_attr + target_attr_len;
+			uint remain_len = ielen - (next_attr - ie);
+
+			if (DBG_DEL_WFD_ATTR) {
+				RTW_INFO("%s %d before\n", __func__, index);
+				dump_ies(RTW_DBGDUMP, ie, ielen);
+
+				RTW_INFO("ie:%p, ielen:%u\n", ie, ielen);
+				RTW_INFO("target_attr:%p, target_attr_len:%u\n", target_attr, target_attr_len);
+				RTW_INFO("next_attr:%p, remain_len:%u\n", next_attr, remain_len);
+			}
+
+			_rtw_memmove(target_attr, next_attr, remain_len);
+			_rtw_memset(target_attr + remain_len, 0, target_attr_len);
+			*(ie + 1) -= target_attr_len;
+			ielen -= target_attr_len;
+
+			if (DBG_DEL_WFD_ATTR) {
+				RTW_INFO("%s %d after\n", __func__, index);
+				dump_ies(RTW_DBGDUMP, ie, ielen);
+			}
+
+			index++;
+		} else
+			break;
+	}
+
+	return ielen;
+}
+
+inline u8 *rtw_bss_ex_get_wfd_ie(WLAN_BSSID_EX *bss_ex, u8 *wfd_ie, uint *wfd_ielen)
+{
+	return rtw_get_wfd_ie(BSS_EX_TLV_IES(bss_ex), BSS_EX_TLV_IES_LEN(bss_ex), wfd_ie, wfd_ielen);
+}
+
+void rtw_bss_ex_del_wfd_ie(WLAN_BSSID_EX *bss_ex)
+{
+#define DBG_BSS_EX_DEL_WFD_IE 0
+	u8 *ies = BSS_EX_TLV_IES(bss_ex);
+	uint ies_len_ori = BSS_EX_TLV_IES_LEN(bss_ex);
+	uint ies_len;
+
+	ies_len = rtw_del_wfd_ie(ies, ies_len_ori, DBG_BSS_EX_DEL_WFD_IE ? __func__ : NULL);
+	bss_ex->IELength -= ies_len_ori - ies_len;
+}
+
+void rtw_bss_ex_del_wfd_attr(WLAN_BSSID_EX *bss_ex, u8 attr_id)
+{
+#define DBG_BSS_EX_DEL_WFD_ATTR 0
+
+	u8 *ies = BSS_EX_TLV_IES(bss_ex);
+	uint ies_len = BSS_EX_TLV_IES_LEN(bss_ex);
+
+	u8 *ie;
+	uint ie_len, ie_len_ori;
+
+	int index = 0;
+
+	while (1) {
+		ie = rtw_get_wfd_ie(ies, ies_len, NULL, &ie_len_ori);
+		if (ie) {
+			u8 *next_ie_ori = ie + ie_len_ori;
+			uint remain_len = bss_ex->IELength - (next_ie_ori - bss_ex->IEs);
+			u8 has_target_attr = 0;
+
+			if (DBG_BSS_EX_DEL_WFD_ATTR) {
+				if (rtw_get_wfd_attr(ie, ie_len_ori, attr_id, NULL, NULL)) {
+					RTW_INFO("%s %d before\n", __func__, index);
+					dump_ies(RTW_DBGDUMP, BSS_EX_TLV_IES(bss_ex), BSS_EX_TLV_IES_LEN(bss_ex));
+
+					RTW_INFO("ies:%p, ies_len:%u\n", ies, ies_len);
+					RTW_INFO("ie:%p, ie_len_ori:%u\n", ie, ie_len_ori);
+					RTW_INFO("next_ie_ori:%p, remain_len:%u\n", next_ie_ori, remain_len);
+					has_target_attr = 1;
+				}
+			}
+
+			ie_len = rtw_del_wfd_attr(ie, ie_len_ori, attr_id);
+			if (ie_len != ie_len_ori) {
+				u8 *next_ie = ie + ie_len;
+
+				_rtw_memmove(next_ie, next_ie_ori, remain_len);
+				_rtw_memset(next_ie + remain_len, 0, ie_len_ori - ie_len);
+				bss_ex->IELength -= ie_len_ori - ie_len;
+
+				ies = next_ie;
+			} else
+				ies = next_ie_ori;
+
+			if (DBG_BSS_EX_DEL_WFD_ATTR) {
+				if (has_target_attr) {
+					RTW_INFO("%s %d after\n", __func__, index);
+					dump_ies(RTW_DBGDUMP, BSS_EX_TLV_IES(bss_ex), BSS_EX_TLV_IES_LEN(bss_ex));
+				}
+			}
+
+			ies_len = remain_len;
+
+			index++;
+		} else
+			break;
+	}
+}
+
+/* Baron adds to avoid FreeBSD warning */
+int ieee80211_is_empty_essid(const char *essid, int essid_len)
+{
+	/* Single white space is for Linksys APs */
+	if (essid_len == 1 && essid[0] == ' ')
+		return 1;
+
+	/* Otherwise, if the entire essid is 0, we assume it is hidden */
+	while (essid_len) {
+		essid_len--;
+		if (essid[essid_len] != '\0')
+			return 0;
+	}
+
+	return 1;
+}
+
+int ieee80211_get_hdrlen(u16 fc)
+{
+	int hdrlen = 24;
+
+	switch (WLAN_FC_GET_TYPE(fc)) {
+	case RTW_IEEE80211_FTYPE_DATA:
+		if (fc & RTW_IEEE80211_STYPE_QOS_DATA)
+			hdrlen += 2;
+		if ((fc & RTW_IEEE80211_FCTL_FROMDS) && (fc & RTW_IEEE80211_FCTL_TODS))
+			hdrlen += 6; /* Addr4 */
+		break;
+	case RTW_IEEE80211_FTYPE_CTL:
+		switch (WLAN_FC_GET_STYPE(fc)) {
+		case RTW_IEEE80211_STYPE_CTS:
+		case RTW_IEEE80211_STYPE_ACK:
+			hdrlen = 10;
+			break;
+		default:
+			hdrlen = 16;
+			break;
+		}
+		break;
+	}
+
+	return hdrlen;
+}
+
+int rtw_get_cipher_info(struct wlan_network *pnetwork)
+{
+	u32 wpa_ielen;
+	unsigned char *pbuf;
+	int group_cipher = 0, pairwise_cipher = 0, is8021x = 0;
+	int ret = _FAIL;
+	pbuf = rtw_get_wpa_ie(&pnetwork->network.IEs[12], &wpa_ielen, pnetwork->network.IELength - 12);
+
+	if (pbuf && (wpa_ielen > 0)) {
+		if (_SUCCESS == rtw_parse_wpa_ie(pbuf, wpa_ielen + 2, &group_cipher, &pairwise_cipher, &is8021x)) {
+
+			pnetwork->BcnInfo.pairwise_cipher = pairwise_cipher;
+			pnetwork->BcnInfo.group_cipher = group_cipher;
+			pnetwork->BcnInfo.is_8021x = is8021x;
+			ret = _SUCCESS;
+		}
+	} else {
+
+		pbuf = rtw_get_wpa2_ie(&pnetwork->network.IEs[12], &wpa_ielen, pnetwork->network.IELength - 12);
+
+		if (pbuf && (wpa_ielen > 0)) {
+			if (_SUCCESS == rtw_parse_wpa2_ie(pbuf, wpa_ielen + 2, &group_cipher, &pairwise_cipher, &is8021x, NULL)) {
+				pnetwork->BcnInfo.pairwise_cipher = pairwise_cipher;
+				pnetwork->BcnInfo.group_cipher = group_cipher;
+				pnetwork->BcnInfo.is_8021x = is8021x;
+				ret = _SUCCESS;
+			}
+		}
+	}
+
+	return ret;
+}
+
+void rtw_get_bcn_info(struct wlan_network *pnetwork)
+{
+	unsigned short cap = 0;
+	u8 bencrypt = 0;
+	/* u8 wpa_ie[255],rsn_ie[255]; */
+	u16 wpa_len = 0, rsn_len = 0;
+	struct HT_info_element *pht_info = NULL;
+	struct rtw_ieee80211_ht_cap *pht_cap = NULL;
+	unsigned int		len;
+	unsigned char		*p;
+
+	_rtw_memcpy((u8 *)&cap, rtw_get_capability_from_ie(pnetwork->network.IEs), 2);
+	cap = le16_to_cpu(cap);
+	if (cap & WLAN_CAPABILITY_PRIVACY) {
+		bencrypt = 1;
+		pnetwork->network.Privacy = 1;
+	} else
+		pnetwork->BcnInfo.encryp_protocol = ENCRYP_PROTOCOL_OPENSYS;
+	rtw_get_sec_ie(pnetwork->network.IEs , pnetwork->network.IELength, NULL, &rsn_len, NULL, &wpa_len);
+
+	if (rsn_len > 0)
+		pnetwork->BcnInfo.encryp_protocol = ENCRYP_PROTOCOL_WPA2;
+	else if (wpa_len > 0)
+		pnetwork->BcnInfo.encryp_protocol = ENCRYP_PROTOCOL_WPA;
+	else {
+		if (bencrypt)
+			pnetwork->BcnInfo.encryp_protocol = ENCRYP_PROTOCOL_WEP;
+	}
+	rtw_get_cipher_info(pnetwork);
+
+	/* get bwmode and ch_offset */
+	/* parsing HT_CAP_IE */
+	p = rtw_get_ie(pnetwork->network.IEs + _FIXED_IE_LENGTH_, _HT_CAPABILITY_IE_, &len, pnetwork->network.IELength - _FIXED_IE_LENGTH_);
+	if (p && len > 0) {
+		pht_cap = (struct rtw_ieee80211_ht_cap *)(p + 2);
+		pnetwork->BcnInfo.ht_cap_info = pht_cap->cap_info;
+	} else
+		pnetwork->BcnInfo.ht_cap_info = 0;
+	/* parsing HT_INFO_IE */
+	p = rtw_get_ie(pnetwork->network.IEs + _FIXED_IE_LENGTH_, _HT_ADD_INFO_IE_, &len, pnetwork->network.IELength - _FIXED_IE_LENGTH_);
+	if (p && len > 0) {
+		pht_info = (struct HT_info_element *)(p + 2);
+		pnetwork->BcnInfo.ht_info_infos_0 = pht_info->infos[0];
+	} else
+		pnetwork->BcnInfo.ht_info_infos_0 = 0;
+}
+
+u8	rtw_ht_mcsset_to_nss(u8 *supp_mcs_set)
+{
+	u8 nss = 1;
+
+	if (supp_mcs_set[3])
+		nss = 4;
+	else if (supp_mcs_set[2])
+		nss = 3;
+	else if (supp_mcs_set[1])
+		nss = 2;
+	else if (supp_mcs_set[0])
+		nss = 1;
+	else
+		RTW_INFO("%s,%d, warning! supp_mcs_set is zero\n", __func__, __LINE__);
+	/* RTW_INFO("%s HT: %dSS\n", __FUNCTION__, nss); */
+	return nss;
+}
+
+u32	rtw_ht_mcs_set_to_bitmap(u8 *mcs_set, u8 nss)
+{
+	u8 i;
+	u32 bitmap = 0;
+
+	for (i = 0; i < nss; i++)
+		bitmap |= mcs_set[i] << (i * 8);
+
+	RTW_INFO("ht_mcs_set=%02x %02x %02x %02x, nss=%u, bitmap=%08x\n"
+		, mcs_set[0], mcs_set[1], mcs_set[2], mcs_set[3], nss, bitmap);
+
+	return bitmap;
+}
+
+/* show MCS rate, unit: 100Kbps */
+u16 rtw_mcs_rate(u8 rf_type, u8 bw_40MHz, u8 short_GI, unsigned char *MCS_rate)
+{
+	u16 max_rate = 0;
+
+	if (MCS_rate[3]) {
+		if (MCS_rate[3] & BIT(7))
+			max_rate = (bw_40MHz) ? ((short_GI) ? 6000 : 5400) : ((short_GI) ? 2889 : 2600);
+		else if (MCS_rate[3] & BIT(6))
+			max_rate = (bw_40MHz) ? ((short_GI) ? 5400 : 4860) : ((short_GI) ? 2600 : 2340);
+		else if (MCS_rate[3] & BIT(5))
+			max_rate = (bw_40MHz) ? ((short_GI) ? 4800 : 4320) : ((short_GI) ? 2311 : 2080);
+		else if (MCS_rate[3] & BIT(4))
+			max_rate = (bw_40MHz) ? ((short_GI) ? 3600 : 3240) : ((short_GI) ? 1733 : 1560);
+		else if (MCS_rate[3] & BIT(3))
+			max_rate = (bw_40MHz) ? ((short_GI) ? 2400 : 2160) : ((short_GI) ? 1156 : 1040);
+		else if (MCS_rate[3] & BIT(2))
+			max_rate = (bw_40MHz) ? ((short_GI) ? 1800 : 1620) : ((short_GI) ? 867 : 780);
+		else if (MCS_rate[3] & BIT(1))
+			max_rate = (bw_40MHz) ? ((short_GI) ? 1200 : 1080) : ((short_GI) ? 578 : 520);
+		else if (MCS_rate[3] & BIT(0))
+			max_rate = (bw_40MHz) ? ((short_GI) ? 600 : 540) : ((short_GI) ? 289 : 260);
+	} else if (MCS_rate[2]) {
+		if (MCS_rate[2] & BIT(7))
+			max_rate = (bw_40MHz) ? ((short_GI) ? 4500 : 4050) : ((short_GI) ? 2167 : 1950);
+		else if (MCS_rate[2] & BIT(6))
+			max_rate = (bw_40MHz) ? ((short_GI) ? 4050 : 3645) : ((short_GI) ? 1950 : 1750);
+		else if (MCS_rate[2] & BIT(5))
+			max_rate = (bw_40MHz) ? ((short_GI) ? 3600 : 3240) : ((short_GI) ? 1733 : 1560);
+		else if (MCS_rate[2] & BIT(4))
+			max_rate = (bw_40MHz) ? ((short_GI) ? 2700 : 2430) : ((short_GI) ? 1300 : 1170);
+		else if (MCS_rate[2] & BIT(3))
+			max_rate = (bw_40MHz) ? ((short_GI) ? 1800 : 1620) : ((short_GI) ? 867 : 780);
+		else if (MCS_rate[2] & BIT(2))
+			max_rate = (bw_40MHz) ? ((short_GI) ? 1350 : 1215) : ((short_GI) ? 650 : 585);
+		else if (MCS_rate[2] & BIT(1))
+			max_rate = (bw_40MHz) ? ((short_GI) ? 900 : 810) : ((short_GI) ? 433 : 390);
+		else if (MCS_rate[2] & BIT(0))
+			max_rate = (bw_40MHz) ? ((short_GI) ? 450 : 405) : ((short_GI) ? 217 : 195);
+	} else if (MCS_rate[1]) {
+		if (MCS_rate[1] & BIT(7))
+			max_rate = (bw_40MHz) ? ((short_GI) ? 3000 : 2700) : ((short_GI) ? 1444 : 1300);
+		else if (MCS_rate[1] & BIT(6))
+			max_rate = (bw_40MHz) ? ((short_GI) ? 2700 : 2430) : ((short_GI) ? 1300 : 1170);
+		else if (MCS_rate[1] & BIT(5))
+			max_rate = (bw_40MHz) ? ((short_GI) ? 2400 : 2160) : ((short_GI) ? 1156 : 1040);
+		else if (MCS_rate[1] & BIT(4))
+			max_rate = (bw_40MHz) ? ((short_GI) ? 1800 : 1620) : ((short_GI) ? 867 : 780);
+		else if (MCS_rate[1] & BIT(3))
+			max_rate = (bw_40MHz) ? ((short_GI) ? 1200 : 1080) : ((short_GI) ? 578 : 520);
+		else if (MCS_rate[1] & BIT(2))
+			max_rate = (bw_40MHz) ? ((short_GI) ? 900 : 810) : ((short_GI) ? 433 : 390);
+		else if (MCS_rate[1] & BIT(1))
+			max_rate = (bw_40MHz) ? ((short_GI) ? 600 : 540) : ((short_GI) ? 289 : 260);
+		else if (MCS_rate[1] & BIT(0))
+			max_rate = (bw_40MHz) ? ((short_GI) ? 300 : 270) : ((short_GI) ? 144 : 130);
+	} else {
+		if (MCS_rate[0] & BIT(7))
+			max_rate = (bw_40MHz) ? ((short_GI) ? 1500 : 1350) : ((short_GI) ? 722 : 650);
+		else if (MCS_rate[0] & BIT(6))
+			max_rate = (bw_40MHz) ? ((short_GI) ? 1350 : 1215) : ((short_GI) ? 650 : 585);
+		else if (MCS_rate[0] & BIT(5))
+			max_rate = (bw_40MHz) ? ((short_GI) ? 1200 : 1080) : ((short_GI) ? 578 : 520);
+		else if (MCS_rate[0] & BIT(4))
+			max_rate = (bw_40MHz) ? ((short_GI) ? 900 : 810) : ((short_GI) ? 433 : 390);
+		else if (MCS_rate[0] & BIT(3))
+			max_rate = (bw_40MHz) ? ((short_GI) ? 600 : 540) : ((short_GI) ? 289 : 260);
+		else if (MCS_rate[0] & BIT(2))
+			max_rate = (bw_40MHz) ? ((short_GI) ? 450 : 405) : ((short_GI) ? 217 : 195);
+		else if (MCS_rate[0] & BIT(1))
+			max_rate = (bw_40MHz) ? ((short_GI) ? 300 : 270) : ((short_GI) ? 144 : 130);
+		else if (MCS_rate[0] & BIT(0))
+			max_rate = (bw_40MHz) ? ((short_GI) ? 150 : 135) : ((short_GI) ? 72 : 65);
+	}
+
+	return max_rate;
+}
+
+int rtw_action_frame_parse(const u8 *frame, u32 frame_len, u8 *category, u8 *action)
+{
+	const u8 *frame_body = frame + sizeof(struct rtw_ieee80211_hdr_3addr);
+	u16 fc;
+	u8 c;
+	u8 a = ACT_PUBLIC_MAX;
+
+	fc = le16_to_cpu(((struct rtw_ieee80211_hdr_3addr *)frame)->frame_ctl);
+
+	if ((fc & (RTW_IEEE80211_FCTL_FTYPE | RTW_IEEE80211_FCTL_STYPE))
+	    != (RTW_IEEE80211_FTYPE_MGMT | RTW_IEEE80211_STYPE_ACTION)
+	   )
+		return _FALSE;
+
+	c = frame_body[0];
+
+	switch (c) {
+	case RTW_WLAN_CATEGORY_P2P: /* vendor-specific */
+		break;
+	default:
+		a = frame_body[1];
+	}
+
+	if (category)
+		*category = c;
+	if (action)
+		*action = a;
+
+	return _TRUE;
+}
+
+static const char *_action_public_str[] = {
+	"ACT_PUB_BSSCOEXIST",
+	"ACT_PUB_DSE_ENABLE",
+	"ACT_PUB_DSE_DEENABLE",
+	"ACT_PUB_DSE_REG_LOCATION",
+	"ACT_PUB_EXT_CHL_SWITCH",
+	"ACT_PUB_DSE_MSR_REQ",
+	"ACT_PUB_DSE_MSR_RPRT",
+	"ACT_PUB_MP",
+	"ACT_PUB_DSE_PWR_CONSTRAINT",
+	"ACT_PUB_VENDOR",
+	"ACT_PUB_GAS_INITIAL_REQ",
+	"ACT_PUB_GAS_INITIAL_RSP",
+	"ACT_PUB_GAS_COMEBACK_REQ",
+	"ACT_PUB_GAS_COMEBACK_RSP",
+	"ACT_PUB_TDLS_DISCOVERY_RSP",
+	"ACT_PUB_LOCATION_TRACK",
+	"ACT_PUB_RSVD",
+};
+
+const char *action_public_str(u8 action)
+{
+	action = (action >= ACT_PUBLIC_MAX) ? ACT_PUBLIC_MAX : action;
+	return _action_public_str[action];
+}
+
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/core/rtw_io.c linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/core/rtw_io.c
--- linux-5.6.3/3rdparty/rtl8821ce/core/rtw_io.c	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/core/rtw_io.c	2020-04-10 16:35:06.773658060 +0300
@@ -0,0 +1,903 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+/*
+
+The purpose of rtw_io.c
+
+a. provides the API
+
+b. provides the protocol engine
+
+c. provides the software interface between caller and the hardware interface
+
+
+Compiler Flag Option:
+
+1. CONFIG_SDIO_HCI:
+    a. USE_SYNC_IRP:  Only sync operations are provided.
+    b. USE_ASYNC_IRP:Both sync/async operations are provided.
+
+2. CONFIG_USB_HCI:
+   a. USE_ASYNC_IRP: Both sync/async operations are provided.
+
+3. CONFIG_CFIO_HCI:
+   b. USE_SYNC_IRP: Only sync operations are provided.
+
+
+Only sync read/rtw_write_mem operations are provided.
+
+jackson@realtek.com.tw
+
+*/
+
+#define _RTW_IO_C_
+
+#include <drv_types.h>
+#include <hal_data.h>
+
+#if defined(PLATFORM_LINUX) && defined (PLATFORM_WINDOWS)
+	#error "Shall be Linux or Windows, but not both!\n"
+#endif
+
+#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_PLATFORM_RTL8197D)
+	#define rtw_le16_to_cpu(val)		val
+	#define rtw_le32_to_cpu(val)		val
+	#define rtw_cpu_to_le16(val)		val
+	#define rtw_cpu_to_le32(val)		val
+#else
+	#define rtw_le16_to_cpu(val)		le16_to_cpu(val)
+	#define rtw_le32_to_cpu(val)		le32_to_cpu(val)
+	#define rtw_cpu_to_le16(val)		cpu_to_le16(val)
+	#define rtw_cpu_to_le32(val)		cpu_to_le32(val)
+#endif
+
+
+u8 _rtw_read8(_adapter *adapter, u32 addr)
+{
+	u8 r_val;
+	/* struct	io_queue  	*pio_queue = (struct io_queue *)adapter->pio_queue; */
+	struct io_priv *pio_priv = &adapter->iopriv;
+	struct	intf_hdl		*pintfhdl = &(pio_priv->intf);
+	u8(*_read8)(struct intf_hdl *pintfhdl, u32 addr);
+	_read8 = pintfhdl->io_ops._read8;
+
+	r_val = _read8(pintfhdl, addr);
+	return r_val;
+}
+
+u16 _rtw_read16(_adapter *adapter, u32 addr)
+{
+	u16 r_val;
+	/* struct	io_queue  	*pio_queue = (struct io_queue *)adapter->pio_queue; */
+	struct io_priv *pio_priv = &adapter->iopriv;
+	struct	intf_hdl		*pintfhdl = &(pio_priv->intf);
+	u16(*_read16)(struct intf_hdl *pintfhdl, u32 addr);
+	_read16 = pintfhdl->io_ops._read16;
+
+	r_val = _read16(pintfhdl, addr);
+	return rtw_le16_to_cpu(r_val);
+}
+
+u32 _rtw_read32(_adapter *adapter, u32 addr)
+{
+	u32 r_val;
+	/* struct	io_queue  	*pio_queue = (struct io_queue *)adapter->pio_queue; */
+	struct io_priv *pio_priv = &adapter->iopriv;
+	struct	intf_hdl		*pintfhdl = &(pio_priv->intf);
+	u32(*_read32)(struct intf_hdl *pintfhdl, u32 addr);
+	_read32 = pintfhdl->io_ops._read32;
+
+	r_val = _read32(pintfhdl, addr);
+	return rtw_le32_to_cpu(r_val);
+
+}
+
+int _rtw_write8(_adapter *adapter, u32 addr, u8 val)
+{
+	/* struct	io_queue  	*pio_queue = (struct io_queue *)adapter->pio_queue; */
+	struct io_priv *pio_priv = &adapter->iopriv;
+	struct	intf_hdl		*pintfhdl = &(pio_priv->intf);
+	int (*_write8)(struct intf_hdl *pintfhdl, u32 addr, u8 val);
+	int ret;
+	_write8 = pintfhdl->io_ops._write8;
+
+	ret = _write8(pintfhdl, addr, val);
+
+	return RTW_STATUS_CODE(ret);
+}
+int _rtw_write16(_adapter *adapter, u32 addr, u16 val)
+{
+	/* struct	io_queue  	*pio_queue = (struct io_queue *)adapter->pio_queue; */
+	struct io_priv *pio_priv = &adapter->iopriv;
+	struct	intf_hdl		*pintfhdl = &(pio_priv->intf);
+	int (*_write16)(struct intf_hdl *pintfhdl, u32 addr, u16 val);
+	int ret;
+	_write16 = pintfhdl->io_ops._write16;
+
+	val = rtw_cpu_to_le16(val);
+	ret = _write16(pintfhdl, addr, val);
+
+	return RTW_STATUS_CODE(ret);
+}
+int _rtw_write32(_adapter *adapter, u32 addr, u32 val)
+{
+	/* struct	io_queue  	*pio_queue = (struct io_queue *)adapter->pio_queue; */
+	struct io_priv *pio_priv = &adapter->iopriv;
+	struct	intf_hdl		*pintfhdl = &(pio_priv->intf);
+	int (*_write32)(struct intf_hdl *pintfhdl, u32 addr, u32 val);
+	int ret;
+	_write32 = pintfhdl->io_ops._write32;
+
+	val = rtw_cpu_to_le32(val);
+	ret = _write32(pintfhdl, addr, val);
+
+	return RTW_STATUS_CODE(ret);
+}
+
+int _rtw_writeN(_adapter *adapter, u32 addr , u32 length , u8 *pdata)
+{
+	/* struct	io_queue  	*pio_queue = (struct io_queue *)adapter->pio_queue; */
+	struct io_priv *pio_priv = &adapter->iopriv;
+	struct	intf_hdl	*pintfhdl = (struct intf_hdl *)(&(pio_priv->intf));
+	int (*_writeN)(struct intf_hdl *pintfhdl, u32 addr, u32 length, u8 *pdata);
+	int ret;
+	_writeN = pintfhdl->io_ops._writeN;
+
+	ret = _writeN(pintfhdl, addr, length, pdata);
+
+	return RTW_STATUS_CODE(ret);
+}
+
+#ifdef CONFIG_SDIO_HCI
+u8 _rtw_sd_f0_read8(_adapter *adapter, u32 addr)
+{
+	u8 r_val = 0x00;
+	struct io_priv *pio_priv = &adapter->iopriv;
+	struct intf_hdl *pintfhdl = &(pio_priv->intf);
+	u8(*_sd_f0_read8)(struct intf_hdl *pintfhdl, u32 addr);
+
+	_sd_f0_read8 = pintfhdl->io_ops._sd_f0_read8;
+
+	if (_sd_f0_read8)
+		r_val = _sd_f0_read8(pintfhdl, addr);
+	else
+		RTW_WARN(FUNC_ADPT_FMT" _sd_f0_read8 callback is NULL\n", FUNC_ADPT_ARG(adapter));
+
+	return r_val;
+}
+
+#ifdef CONFIG_SDIO_INDIRECT_ACCESS
+u8 _rtw_sd_iread8(_adapter *adapter, u32 addr)
+{
+	u8 r_val = 0x00;
+	struct io_priv *pio_priv = &adapter->iopriv;
+	struct intf_hdl *pintfhdl = &(pio_priv->intf);
+	u8(*_sd_iread8)(struct intf_hdl *pintfhdl, u32 addr);
+
+	_sd_iread8 = pintfhdl->io_ops._sd_iread8;
+
+	if (_sd_iread8)
+		r_val = _sd_iread8(pintfhdl, addr);
+	else
+		RTW_ERR(FUNC_ADPT_FMT" _sd_iread8 callback is NULL\n", FUNC_ADPT_ARG(adapter));
+
+	return r_val;
+}
+
+u16 _rtw_sd_iread16(_adapter *adapter, u32 addr)
+{
+	u16 r_val = 0x00;
+	struct io_priv *pio_priv = &adapter->iopriv;
+	struct intf_hdl *pintfhdl = &(pio_priv->intf);
+	u16(*_sd_iread16)(struct intf_hdl *pintfhdl, u32 addr);
+
+	_sd_iread16 = pintfhdl->io_ops._sd_iread16;
+
+	if (_sd_iread16)
+		r_val = _sd_iread16(pintfhdl, addr);
+	else
+		RTW_ERR(FUNC_ADPT_FMT" _sd_iread16 callback is NULL\n", FUNC_ADPT_ARG(adapter));
+
+	return r_val;
+}
+
+u32 _rtw_sd_iread32(_adapter *adapter, u32 addr)
+{
+	u32 r_val = 0x00;
+	struct io_priv *pio_priv = &adapter->iopriv;
+	struct intf_hdl *pintfhdl = &(pio_priv->intf);
+	u32(*_sd_iread32)(struct intf_hdl *pintfhdl, u32 addr);
+
+	_sd_iread32 = pintfhdl->io_ops._sd_iread32;
+
+	if (_sd_iread32)
+		r_val = _sd_iread32(pintfhdl, addr);
+	else
+		RTW_ERR(FUNC_ADPT_FMT" _sd_iread32 callback is NULL\n", FUNC_ADPT_ARG(adapter));
+
+	return r_val;
+}
+
+int _rtw_sd_iwrite8(_adapter *adapter, u32 addr, u8 val)
+{
+	struct io_priv *pio_priv = &adapter->iopriv;
+	struct intf_hdl *pintfhdl = &(pio_priv->intf);
+	int (*_sd_iwrite8)(struct intf_hdl *pintfhdl, u32 addr, u8 val);
+	int ret = -1;
+
+	_sd_iwrite8 = pintfhdl->io_ops._sd_iwrite8;
+
+	if (_sd_iwrite8)
+		ret = _sd_iwrite8(pintfhdl, addr, val);
+	else
+		RTW_ERR(FUNC_ADPT_FMT" _sd_iwrite8 callback is NULL\n", FUNC_ADPT_ARG(adapter));
+
+	return RTW_STATUS_CODE(ret);
+}
+
+int _rtw_sd_iwrite16(_adapter *adapter, u32 addr, u16 val)
+{
+	struct io_priv *pio_priv = &adapter->iopriv;
+	struct intf_hdl *pintfhdl = &(pio_priv->intf);
+	int (*_sd_iwrite16)(struct intf_hdl *pintfhdl, u32 addr, u16 val);
+	int ret = -1;
+
+	_sd_iwrite16 = pintfhdl->io_ops._sd_iwrite16;
+
+	if (_sd_iwrite16)
+		ret = _sd_iwrite16(pintfhdl, addr, val);
+	else
+		RTW_ERR(FUNC_ADPT_FMT" _sd_iwrite16 callback is NULL\n", FUNC_ADPT_ARG(adapter));
+
+	return RTW_STATUS_CODE(ret);
+}
+int _rtw_sd_iwrite32(_adapter *adapter, u32 addr, u32 val)
+{
+	struct io_priv *pio_priv = &adapter->iopriv;
+	struct intf_hdl *pintfhdl = &(pio_priv->intf);
+	int (*_sd_iwrite32)(struct intf_hdl *pintfhdl, u32 addr, u32 val);
+	int ret = -1;
+
+	_sd_iwrite32 = pintfhdl->io_ops._sd_iwrite32;
+
+	if (_sd_iwrite32)
+		ret = _sd_iwrite32(pintfhdl, addr, val);
+	else
+		RTW_ERR(FUNC_ADPT_FMT" _sd_iwrite32 callback is NULL\n", FUNC_ADPT_ARG(adapter));
+
+	return RTW_STATUS_CODE(ret);
+}
+
+#endif /* CONFIG_SDIO_INDIRECT_ACCESS */
+
+#endif /* CONFIG_SDIO_HCI */
+
+int _rtw_write8_async(_adapter *adapter, u32 addr, u8 val)
+{
+	/* struct	io_queue  	*pio_queue = (struct io_queue *)adapter->pio_queue; */
+	struct io_priv *pio_priv = &adapter->iopriv;
+	struct	intf_hdl		*pintfhdl = &(pio_priv->intf);
+	int (*_write8_async)(struct intf_hdl *pintfhdl, u32 addr, u8 val);
+	int ret;
+	_write8_async = pintfhdl->io_ops._write8_async;
+
+	ret = _write8_async(pintfhdl, addr, val);
+
+	return RTW_STATUS_CODE(ret);
+}
+int _rtw_write16_async(_adapter *adapter, u32 addr, u16 val)
+{
+	/* struct	io_queue  	*pio_queue = (struct io_queue *)adapter->pio_queue; */
+	struct io_priv *pio_priv = &adapter->iopriv;
+	struct	intf_hdl		*pintfhdl = &(pio_priv->intf);
+	int (*_write16_async)(struct intf_hdl *pintfhdl, u32 addr, u16 val);
+	int ret;
+	_write16_async = pintfhdl->io_ops._write16_async;
+	val = rtw_cpu_to_le16(val);
+	ret = _write16_async(pintfhdl, addr, val);
+
+	return RTW_STATUS_CODE(ret);
+}
+int _rtw_write32_async(_adapter *adapter, u32 addr, u32 val)
+{
+	/* struct	io_queue  	*pio_queue = (struct io_queue *)adapter->pio_queue; */
+	struct io_priv *pio_priv = &adapter->iopriv;
+	struct	intf_hdl		*pintfhdl = &(pio_priv->intf);
+	int (*_write32_async)(struct intf_hdl *pintfhdl, u32 addr, u32 val);
+	int ret;
+	_write32_async = pintfhdl->io_ops._write32_async;
+	val = rtw_cpu_to_le32(val);
+	ret = _write32_async(pintfhdl, addr, val);
+
+	return RTW_STATUS_CODE(ret);
+}
+
+void _rtw_read_mem(_adapter *adapter, u32 addr, u32 cnt, u8 *pmem)
+{
+	void (*_read_mem)(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *pmem);
+	/* struct	io_queue  	*pio_queue = (struct io_queue *)adapter->pio_queue; */
+	struct io_priv *pio_priv = &adapter->iopriv;
+	struct	intf_hdl		*pintfhdl = &(pio_priv->intf);
+
+
+	if (RTW_CANNOT_RUN(adapter)) {
+		return;
+	}
+
+	_read_mem = pintfhdl->io_ops._read_mem;
+
+	_read_mem(pintfhdl, addr, cnt, pmem);
+
+
+}
+
+void _rtw_write_mem(_adapter *adapter, u32 addr, u32 cnt, u8 *pmem)
+{
+	void (*_write_mem)(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *pmem);
+	/* struct	io_queue  	*pio_queue = (struct io_queue *)adapter->pio_queue; */
+	struct io_priv *pio_priv = &adapter->iopriv;
+	struct	intf_hdl		*pintfhdl = &(pio_priv->intf);
+
+
+	_write_mem = pintfhdl->io_ops._write_mem;
+
+	_write_mem(pintfhdl, addr, cnt, pmem);
+
+
+}
+
+void _rtw_read_port(_adapter *adapter, u32 addr, u32 cnt, u8 *pmem)
+{
+	u32(*_read_port)(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *pmem);
+	/* struct	io_queue  	*pio_queue = (struct io_queue *)adapter->pio_queue; */
+	struct io_priv *pio_priv = &adapter->iopriv;
+	struct	intf_hdl		*pintfhdl = &(pio_priv->intf);
+
+
+	if (RTW_CANNOT_RUN(adapter)) {
+		return;
+	}
+
+	_read_port = pintfhdl->io_ops._read_port;
+
+	_read_port(pintfhdl, addr, cnt, pmem);
+
+
+}
+
+void _rtw_read_port_cancel(_adapter *adapter)
+{
+	void (*_read_port_cancel)(struct intf_hdl *pintfhdl);
+	struct io_priv *pio_priv = &adapter->iopriv;
+	struct intf_hdl *pintfhdl = &(pio_priv->intf);
+
+	_read_port_cancel = pintfhdl->io_ops._read_port_cancel;
+
+	RTW_DISABLE_FUNC(adapter, DF_RX_BIT);
+
+	if (_read_port_cancel)
+		_read_port_cancel(pintfhdl);
+}
+
+u32 _rtw_write_port(_adapter *adapter, u32 addr, u32 cnt, u8 *pmem)
+{
+	u32(*_write_port)(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *pmem);
+	/* struct	io_queue  	*pio_queue = (struct io_queue *)adapter->pio_queue; */
+	struct io_priv *pio_priv = &adapter->iopriv;
+	struct	intf_hdl		*pintfhdl = &(pio_priv->intf);
+	u32 ret = _SUCCESS;
+
+
+	_write_port = pintfhdl->io_ops._write_port;
+
+	ret = _write_port(pintfhdl, addr, cnt, pmem);
+
+
+	return ret;
+}
+
+u32 _rtw_write_port_and_wait(_adapter *adapter, u32 addr, u32 cnt, u8 *pmem, int timeout_ms)
+{
+	int ret = _SUCCESS;
+	struct xmit_buf *pxmitbuf = (struct xmit_buf *)pmem;
+	struct submit_ctx sctx;
+
+	rtw_sctx_init(&sctx, timeout_ms);
+	pxmitbuf->sctx = &sctx;
+
+	ret = _rtw_write_port(adapter, addr, cnt, pmem);
+
+	if (ret == _SUCCESS) {
+		ret = rtw_sctx_wait(&sctx, __func__);
+
+		if (ret != _SUCCESS)
+			pxmitbuf->sctx = NULL;
+	}
+
+	return ret;
+}
+
+void _rtw_write_port_cancel(_adapter *adapter)
+{
+	void (*_write_port_cancel)(struct intf_hdl *pintfhdl);
+	struct io_priv *pio_priv = &adapter->iopriv;
+	struct intf_hdl *pintfhdl = &(pio_priv->intf);
+
+	_write_port_cancel = pintfhdl->io_ops._write_port_cancel;
+
+	RTW_DISABLE_FUNC(adapter, DF_TX_BIT);
+
+	if (_write_port_cancel)
+		_write_port_cancel(pintfhdl);
+}
+int rtw_init_io_priv(_adapter *padapter, void (*set_intf_ops)(_adapter *padapter, struct _io_ops *pops))
+{
+	struct io_priv	*piopriv = &padapter->iopriv;
+	struct intf_hdl *pintf = &piopriv->intf;
+
+	if (set_intf_ops == NULL)
+		return _FAIL;
+
+	piopriv->padapter = padapter;
+	pintf->padapter = padapter;
+	pintf->pintf_dev = adapter_to_dvobj(padapter);
+
+	set_intf_ops(padapter, &pintf->io_ops);
+
+	return _SUCCESS;
+}
+
+/*
+* Increase and check if the continual_io_error of this @param dvobjprive is larger than MAX_CONTINUAL_IO_ERR
+* @return _TRUE:
+* @return _FALSE:
+*/
+int rtw_inc_and_chk_continual_io_error(struct dvobj_priv *dvobj)
+{
+	int ret = _FALSE;
+	int value;
+
+	value = ATOMIC_INC_RETURN(&dvobj->continual_io_error);
+	if (value > MAX_CONTINUAL_IO_ERR) {
+		RTW_INFO("[dvobj:%p][ERROR] continual_io_error:%d > %d\n", dvobj, value, MAX_CONTINUAL_IO_ERR);
+		ret = _TRUE;
+	} else {
+		/* RTW_INFO("[dvobj:%p] continual_io_error:%d\n", dvobj, value); */
+	}
+	return ret;
+}
+
+/*
+* Set the continual_io_error of this @param dvobjprive to 0
+*/
+void rtw_reset_continual_io_error(struct dvobj_priv *dvobj)
+{
+	ATOMIC_SET(&dvobj->continual_io_error, 0);
+}
+
+#ifdef DBG_IO
+#define RTW_IO_SNIFF_TYPE_RANGE	0 /* specific address range is accessed */
+#define RTW_IO_SNIFF_TYPE_EN	1 /* part or all sniffed range is enabled */
+#define RTW_IO_SNIFF_TYPE_DIS	2 /* part or all sniffed range is disabled */
+
+struct rtw_io_sniff_ent {
+	u8 chip;
+	u8 hci;
+	u32 addr;
+	u8 type;
+	union {
+		u32 end_addr;
+		u32 mask;
+	} u;
+	char *tag;
+};
+
+const char *rtw_io_sniff_ent_get_tag(const struct rtw_io_sniff_ent *ent)
+{
+	return ent->tag;
+}
+
+#define RTW_IO_SNIFF_RANGE_ENT(_chip, _hci, _addr, _end_addr, _tag) \
+	{.chip = _chip, .hci = _hci, .addr = _addr, .u.end_addr = _end_addr, .tag = _tag, .type = RTW_IO_SNIFF_TYPE_RANGE,}
+
+#define RTW_IO_SNIFF_EN_ENT(_chip, _hci, _addr, _mask, _tag) \
+	{.chip = _chip, .hci = _hci, .addr = _addr, .u.mask = _mask, .tag = _tag, .type = RTW_IO_SNIFF_TYPE_EN,}
+
+#define RTW_IO_SNIFF_DIS_ENT(_chip, _hci, _addr, _mask, _tag) \
+	{.chip = _chip, .hci = _hci, .addr = _addr, .u.mask = _mask, .tag = _tag, .type = RTW_IO_SNIFF_TYPE_DIS,}
+
+const struct rtw_io_sniff_ent read_sniff[] = {
+#ifdef DBG_IO_HCI_EN_CHK
+	RTW_IO_SNIFF_EN_ENT(MAX_CHIP_TYPE, RTW_SDIO, 0x02, 0x1FC, "SDIO 0x02[8:2] not all 0"),
+	RTW_IO_SNIFF_EN_ENT(MAX_CHIP_TYPE, RTW_USB, 0x02, 0x1E0, "USB 0x02[8:5] not all 0"),
+	RTW_IO_SNIFF_EN_ENT(MAX_CHIP_TYPE, RTW_PCIE, 0x02, 0x01C, "PCI 0x02[4:2] not all 0"),
+#endif
+#ifdef DBG_IO_SNIFF_EXAMPLE
+	RTW_IO_SNIFF_RANGE_ENT(MAX_CHIP_TYPE, 0, 0x522, 0x522, "read TXPAUSE"),
+	RTW_IO_SNIFF_DIS_ENT(MAX_CHIP_TYPE, 0, 0x02, 0x3, "0x02[1:0] not all 1"),
+#endif
+};
+
+const int read_sniff_num = sizeof(read_sniff) / sizeof(struct rtw_io_sniff_ent);
+
+const struct rtw_io_sniff_ent write_sniff[] = {
+#ifdef DBG_IO_HCI_EN_CHK
+	RTW_IO_SNIFF_EN_ENT(MAX_CHIP_TYPE, RTW_SDIO, 0x02, 0x1FC, "SDIO 0x02[8:2] not all 0"),
+	RTW_IO_SNIFF_EN_ENT(MAX_CHIP_TYPE, RTW_USB, 0x02, 0x1E0, "USB 0x02[8:5] not all 0"),
+	RTW_IO_SNIFF_EN_ENT(MAX_CHIP_TYPE, RTW_PCIE, 0x02, 0x01C, "PCI 0x02[4:2] not all 0"),
+#endif
+#ifdef DBG_IO_SNIFF_EXAMPLE
+	RTW_IO_SNIFF_RANGE_ENT(MAX_CHIP_TYPE, 0, 0x522, 0x522, "write TXPAUSE"),
+	RTW_IO_SNIFF_DIS_ENT(MAX_CHIP_TYPE, 0, 0x02, 0x3, "0x02[1:0] not all 1"),
+#endif
+};
+
+const int write_sniff_num = sizeof(write_sniff) / sizeof(struct rtw_io_sniff_ent);
+
+static bool match_io_sniff_ranges(_adapter *adapter
+	, const struct rtw_io_sniff_ent *sniff, int i, u32 addr, u16 len)
+{
+
+	/* check if IO range after sniff end address */
+	if (addr > sniff->u.end_addr)
+		return 0;
+
+	return 1;
+}
+
+static bool match_io_sniff_en(_adapter *adapter
+	, const struct rtw_io_sniff_ent *sniff, int i, u32 addr, u8 len, u32 val)
+{
+	u8 sniff_len;
+	u8 shift;
+	u32 mask;
+	bool ret = 0;
+
+	/* check if IO range after sniff end address */
+	sniff_len = 4;
+	while (!(sniff->u.mask & (0xFF << ((sniff_len - 1) * 8)))) {
+		sniff_len--;
+		if (sniff_len == 0)
+			goto exit;
+	}
+	if (sniff->addr + sniff_len <= addr)
+		goto exit;
+
+	if (sniff->addr > addr) {
+		shift = (sniff->addr - addr) * 8;
+		mask = sniff->u.mask << shift;
+	} else if (sniff->addr < addr) {
+		shift = (addr - sniff->addr) * 8;
+		mask = sniff->u.mask >> shift;
+	} else {
+		shift = 0;
+		mask = sniff->u.mask;
+	}
+
+	if (sniff->type == RTW_IO_SNIFF_TYPE_DIS) {
+		if (len == 4)
+			mask &= 0xFFFFFFFF;
+		else if (len == 3)
+			mask &= 0x00FFFFFF;
+		else if (len == 2)
+			mask &= 0x0000FFFF;
+		else if (len == 1)
+			mask &= 0x000000FF;
+		else
+			mask &= 0x00000000;
+	}
+	
+	if ((sniff->type == RTW_IO_SNIFF_TYPE_EN && (mask & val))
+		|| (sniff->type == RTW_IO_SNIFF_TYPE_DIS && (mask & val) != mask)
+	) {
+		ret = 1;
+		if (0)
+			RTW_INFO(FUNC_ADPT_FMT" addr:0x%x len:%u val:0x%x i:%d sniff_len:%u shift:%u mask:0x%x\n"
+				, FUNC_ADPT_ARG(adapter), addr, len, val, i, sniff_len, shift, mask);
+	}
+
+exit:
+	return ret;
+}
+
+static bool match_io_sniff(_adapter *adapter
+	, const struct rtw_io_sniff_ent *sniff, int i, u32 addr, u8 len, u32 val)
+{
+	bool ret = 0;
+
+	if (sniff->chip != MAX_CHIP_TYPE
+		&& sniff->chip != rtw_get_chip_type(adapter))
+		goto exit;
+	if (sniff->hci
+		&& !(sniff->hci & rtw_get_intf_type(adapter)))
+		goto exit;
+	if (sniff->addr >= addr + len) /* IO range below sniff start address */
+		goto exit;
+
+	switch (sniff->type) {
+	case RTW_IO_SNIFF_TYPE_RANGE:
+		ret = match_io_sniff_ranges(adapter, sniff, i, addr, len);
+		break;
+	case RTW_IO_SNIFF_TYPE_EN:
+	case RTW_IO_SNIFF_TYPE_DIS:
+		if (len == 1 || len == 2 || len == 4)
+			ret = match_io_sniff_en(adapter, sniff, i, addr, len, val);
+		break;
+	default:
+		rtw_warn_on(1);
+		break;
+	}
+
+exit:
+	return ret;
+}
+
+const struct rtw_io_sniff_ent *match_read_sniff(_adapter *adapter
+	, u32 addr, u16 len, u32 val)
+{
+	int i;
+	bool ret = 0;
+
+	for (i = 0; i < read_sniff_num; i++) {
+		ret = match_io_sniff(adapter, &read_sniff[i], i, addr, len, val);
+		if (ret)
+			goto exit;
+	}
+
+exit:
+	return ret ? &read_sniff[i] : NULL;
+}
+
+const struct rtw_io_sniff_ent *match_write_sniff(_adapter *adapter
+	, u32 addr, u16 len, u32 val)
+{
+	int i;
+	bool ret = 0;
+
+	for (i = 0; i < write_sniff_num; i++) {
+		ret = match_io_sniff(adapter, &write_sniff[i], i, addr, len, val);
+		if (ret)
+			goto exit;
+	}
+
+exit:
+	return ret ? &write_sniff[i] : NULL;
+}
+
+struct rf_sniff_ent {
+	u8 path;
+	u16 reg;
+	u32 mask;
+};
+
+struct rf_sniff_ent rf_read_sniff_ranges[] = {
+	/* example for all path addr 0x55 with all RF Reg mask */
+	/* {MAX_RF_PATH, 0x55, bRFRegOffsetMask}, */
+};
+
+struct rf_sniff_ent rf_write_sniff_ranges[] = {
+	/* example for all path addr 0x55 with all RF Reg mask */
+	/* {MAX_RF_PATH, 0x55, bRFRegOffsetMask}, */
+};
+
+int rf_read_sniff_num = sizeof(rf_read_sniff_ranges) / sizeof(struct rf_sniff_ent);
+int rf_write_sniff_num = sizeof(rf_write_sniff_ranges) / sizeof(struct rf_sniff_ent);
+
+bool match_rf_read_sniff_ranges(_adapter *adapter, u8 path, u32 addr, u32 mask)
+{
+	int i;
+
+	for (i = 0; i < rf_read_sniff_num; i++) {
+		if (rf_read_sniff_ranges[i].path == MAX_RF_PATH || rf_read_sniff_ranges[i].path == path)
+			if (addr == rf_read_sniff_ranges[i].reg && (mask & rf_read_sniff_ranges[i].mask))
+				return _TRUE;
+	}
+
+	return _FALSE;
+}
+
+bool match_rf_write_sniff_ranges(_adapter *adapter, u8 path, u32 addr, u32 mask)
+{
+	int i;
+
+	for (i = 0; i < rf_write_sniff_num; i++) {
+		if (rf_write_sniff_ranges[i].path == MAX_RF_PATH || rf_write_sniff_ranges[i].path == path)
+			if (addr == rf_write_sniff_ranges[i].reg && (mask & rf_write_sniff_ranges[i].mask))
+				return _TRUE;
+	}
+
+	return _FALSE;
+}
+
+u8 dbg_rtw_read8(_adapter *adapter, u32 addr, const char *caller, const int line)
+{
+	u8 val = _rtw_read8(adapter, addr);
+	const struct rtw_io_sniff_ent *ent = match_read_sniff(adapter, addr, 1, val);
+
+	if (ent) {
+		RTW_INFO("DBG_IO %s:%d rtw_read8(0x%04x) return 0x%02x %s\n"
+			, caller, line, addr, val, rtw_io_sniff_ent_get_tag(ent));
+	}
+
+	return val;
+}
+
+u16 dbg_rtw_read16(_adapter *adapter, u32 addr, const char *caller, const int line)
+{
+	u16 val = _rtw_read16(adapter, addr);
+	const struct rtw_io_sniff_ent *ent = match_read_sniff(adapter, addr, 2, val);
+
+	if (ent) {
+		RTW_INFO("DBG_IO %s:%d rtw_read16(0x%04x) return 0x%04x %s\n"
+			, caller, line, addr, val, rtw_io_sniff_ent_get_tag(ent));
+	}
+
+	return val;
+}
+
+u32 dbg_rtw_read32(_adapter *adapter, u32 addr, const char *caller, const int line)
+{
+	u32 val = _rtw_read32(adapter, addr);
+	const struct rtw_io_sniff_ent *ent = match_read_sniff(adapter, addr, 4, val);
+
+	if (ent) {
+		RTW_INFO("DBG_IO %s:%d rtw_read32(0x%04x) return 0x%08x %s\n"
+			, caller, line, addr, val, rtw_io_sniff_ent_get_tag(ent));
+	}
+
+	return val;
+}
+
+int dbg_rtw_write8(_adapter *adapter, u32 addr, u8 val, const char *caller, const int line)
+{
+	const struct rtw_io_sniff_ent *ent = match_write_sniff(adapter, addr, 1, val);
+
+	if (ent) {
+		RTW_INFO("DBG_IO %s:%d rtw_write8(0x%04x, 0x%02x) %s\n"
+			, caller, line, addr, val, rtw_io_sniff_ent_get_tag(ent));
+	}
+
+	return _rtw_write8(adapter, addr, val);
+}
+int dbg_rtw_write16(_adapter *adapter, u32 addr, u16 val, const char *caller, const int line)
+{
+	const struct rtw_io_sniff_ent *ent = match_write_sniff(adapter, addr, 2, val);
+
+	if (ent) {
+		RTW_INFO("DBG_IO %s:%d rtw_write16(0x%04x, 0x%04x) %s\n"
+			, caller, line, addr, val, rtw_io_sniff_ent_get_tag(ent));
+	}
+
+	return _rtw_write16(adapter, addr, val);
+}
+int dbg_rtw_write32(_adapter *adapter, u32 addr, u32 val, const char *caller, const int line)
+{
+	const struct rtw_io_sniff_ent *ent = match_write_sniff(adapter, addr, 4, val);
+
+	if (ent) {
+		RTW_INFO("DBG_IO %s:%d rtw_write32(0x%04x, 0x%08x) %s\n"
+			, caller, line, addr, val, rtw_io_sniff_ent_get_tag(ent));
+	}
+
+	return _rtw_write32(adapter, addr, val);
+}
+int dbg_rtw_writeN(_adapter *adapter, u32 addr , u32 length , u8 *data, const char *caller, const int line)
+{
+	const struct rtw_io_sniff_ent *ent = match_write_sniff(adapter, addr, length, 0);
+
+	if (ent) {
+		RTW_INFO("DBG_IO %s:%d rtw_writeN(0x%04x, %u) %s\n"
+			, caller, line, addr, length, rtw_io_sniff_ent_get_tag(ent));
+	}
+
+	return _rtw_writeN(adapter, addr, length, data);
+}
+
+#ifdef CONFIG_SDIO_HCI
+u8 dbg_rtw_sd_f0_read8(_adapter *adapter, u32 addr, const char *caller, const int line)
+{
+	u8 val = _rtw_sd_f0_read8(adapter, addr);
+
+#if 0
+	const struct rtw_io_sniff_ent *ent = match_read_sniff(adapter, addr, 1, val);
+
+	if (ent) {
+		RTW_INFO("DBG_IO %s:%d rtw_sd_f0_read8(0x%04x) return 0x%02x %s\n"
+			, caller, line, addr, val, rtw_io_sniff_ent_get_tag(ent));
+	}
+#endif
+
+	return val;
+}
+
+#ifdef CONFIG_SDIO_INDIRECT_ACCESS
+u8 dbg_rtw_sd_iread8(_adapter *adapter, u32 addr, const char *caller, const int line)
+{
+	u8 val = rtw_sd_iread8(adapter, addr);
+	const struct rtw_io_sniff_ent *ent = match_read_sniff(adapter, addr, 1, val);
+
+	if (ent) {
+		RTW_INFO("DBG_IO %s:%d rtw_sd_iread8(0x%04x) return 0x%02x %s\n"
+			, caller, line, addr, val, rtw_io_sniff_ent_get_tag(ent));
+	}
+
+	return val;
+}
+
+u16 dbg_rtw_sd_iread16(_adapter *adapter, u32 addr, const char *caller, const int line)
+{
+	u16 val = _rtw_sd_iread16(adapter, addr);
+	const struct rtw_io_sniff_ent *ent = match_read_sniff(adapter, addr, 2, val);
+
+	if (ent) {
+		RTW_INFO("DBG_IO %s:%d rtw_sd_iread16(0x%04x) return 0x%04x %s\n"
+			, caller, line, addr, val, rtw_io_sniff_ent_get_tag(ent));
+	}
+
+	return val;
+}
+
+u32 dbg_rtw_sd_iread32(_adapter *adapter, u32 addr, const char *caller, const int line)
+{
+	u32 val = _rtw_sd_iread32(adapter, addr);
+	const struct rtw_io_sniff_ent *ent = match_read_sniff(adapter, addr, 4, val);
+
+	if (ent) {
+		RTW_INFO("DBG_IO %s:%d rtw_sd_iread32(0x%04x) return 0x%08x %s\n"
+			, caller, line, addr, val, rtw_io_sniff_ent_get_tag(ent));
+	}
+
+	return val;
+}
+
+int dbg_rtw_sd_iwrite8(_adapter *adapter, u32 addr, u8 val, const char *caller, const int line)
+{
+	const struct rtw_io_sniff_ent *ent = match_write_sniff(adapter, addr, 1, val);
+
+	if (ent) {
+		RTW_INFO("DBG_IO %s:%d rtw_sd_iwrite8(0x%04x, 0x%02x) %s\n"
+			, caller, line, addr, val, rtw_io_sniff_ent_get_tag(ent));
+	}
+
+	return _rtw_sd_iwrite8(adapter, addr, val);
+}
+int dbg_rtw_sd_iwrite16(_adapter *adapter, u32 addr, u16 val, const char *caller, const int line)
+{
+	const struct rtw_io_sniff_ent *ent = match_write_sniff(adapter, addr, 2, val);
+
+	if (ent) {
+		RTW_INFO("DBG_IO %s:%d rtw_sd_iwrite16(0x%04x, 0x%04x) %s\n"
+			, caller, line, addr, val, rtw_io_sniff_ent_get_tag(ent));
+	}
+
+	return _rtw_sd_iwrite16(adapter, addr, val);
+}
+int dbg_rtw_sd_iwrite32(_adapter *adapter, u32 addr, u32 val, const char *caller, const int line)
+{
+	const struct rtw_io_sniff_ent *ent = match_write_sniff(adapter, addr, 4, val);
+
+	if (ent) {
+		RTW_INFO("DBG_IO %s:%d rtw_sd_iwrite32(0x%04x, 0x%08x) %s\n"
+			, caller, line, addr, val, rtw_io_sniff_ent_get_tag(ent));
+	}
+
+	return _rtw_sd_iwrite32(adapter, addr, val);
+}
+
+#endif /* CONFIG_SDIO_INDIRECT_ACCESS */
+
+#endif /* CONFIG_SDIO_HCI */
+
+#endif
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/core/rtw_ioctl_query.c linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/core/rtw_ioctl_query.c
--- linux-5.6.3/3rdparty/rtl8821ce/core/rtw_ioctl_query.c	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/core/rtw_ioctl_query.c	2020-04-10 16:35:06.773658060 +0300
@@ -0,0 +1,166 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#define _RTW_IOCTL_QUERY_C_
+
+#include <drv_types.h>
+
+
+#ifdef PLATFORM_WINDOWS
+/*
+ * Added for WPA2-PSK, by Annie, 2005-09-20.
+ *   */
+u8
+query_802_11_capability(
+	_adapter		*Adapter,
+	u8			*pucBuf,
+	u32		*pulOutLen
+)
+{
+	static NDIS_802_11_AUTHENTICATION_ENCRYPTION szAuthEnc[] = {
+		{Ndis802_11AuthModeOpen, Ndis802_11EncryptionDisabled},
+		{Ndis802_11AuthModeOpen, Ndis802_11Encryption1Enabled},
+		{Ndis802_11AuthModeShared, Ndis802_11EncryptionDisabled},
+		{Ndis802_11AuthModeShared, Ndis802_11Encryption1Enabled},
+		{Ndis802_11AuthModeWPA, Ndis802_11Encryption2Enabled},
+		{Ndis802_11AuthModeWPA, Ndis802_11Encryption3Enabled},
+		{Ndis802_11AuthModeWPAPSK, Ndis802_11Encryption2Enabled},
+		{Ndis802_11AuthModeWPAPSK, Ndis802_11Encryption3Enabled},
+		{Ndis802_11AuthModeWPANone, Ndis802_11Encryption2Enabled},
+		{Ndis802_11AuthModeWPANone, Ndis802_11Encryption3Enabled},
+		{Ndis802_11AuthModeWPA2, Ndis802_11Encryption2Enabled},
+		{Ndis802_11AuthModeWPA2, Ndis802_11Encryption3Enabled},
+		{Ndis802_11AuthModeWPA2PSK, Ndis802_11Encryption2Enabled},
+		{Ndis802_11AuthModeWPA2PSK, Ndis802_11Encryption3Enabled}
+	};
+	static ULONG	ulNumOfPairSupported = sizeof(szAuthEnc) / sizeof(NDIS_802_11_AUTHENTICATION_ENCRYPTION);
+	NDIS_802_11_CAPABILITY *pCap = (NDIS_802_11_CAPABILITY *)pucBuf;
+	u8	*pucAuthEncryptionSupported = (u8 *) pCap->AuthenticationEncryptionSupported;
+
+
+	pCap->Length = sizeof(NDIS_802_11_CAPABILITY);
+	if (ulNumOfPairSupported > 1)
+		pCap->Length +=	(ulNumOfPairSupported - 1) * sizeof(NDIS_802_11_AUTHENTICATION_ENCRYPTION);
+
+	pCap->Version = 2;
+	pCap->NoOfPMKIDs = NUM_PMKID_CACHE;
+	pCap->NoOfAuthEncryptPairsSupported = ulNumOfPairSupported;
+
+	if (sizeof(szAuthEnc) <= 240)		/* 240 = 256 - 4*4	 */ { /* SecurityInfo.szCapability: only 256 bytes in size. */
+		_rtw_memcpy(pucAuthEncryptionSupported, (u8 *)szAuthEnc,  sizeof(szAuthEnc));
+		*pulOutLen = pCap->Length;
+		return _TRUE;
+	} else {
+		*pulOutLen = 0;
+		return _FALSE;
+	}
+}
+
+u8 query_802_11_association_information(_adapter *padapter, PNDIS_802_11_ASSOCIATION_INFORMATION	pAssocInfo)
+{
+	struct wlan_network *tgt_network;
+	struct	mlme_priv	*pmlmepriv = &(padapter->mlmepriv);
+	struct	security_priv  *psecuritypriv = &(padapter->securitypriv);
+	WLAN_BSSID_EX	*psecnetwork = (WLAN_BSSID_EX *)&pmlmepriv->cur_network.network;
+	u8	*pDest = (u8 *)pAssocInfo + sizeof(NDIS_802_11_ASSOCIATION_INFORMATION);
+	unsigned char i, *auth_ie, *supp_ie;
+
+	/* NdisZeroMemory(pAssocInfo, sizeof(NDIS_802_11_ASSOCIATION_INFORMATION)); */
+	_rtw_memset(pAssocInfo, 0, sizeof(NDIS_802_11_ASSOCIATION_INFORMATION));
+	/* pAssocInfo->Length = sizeof(NDIS_802_11_ASSOCIATION_INFORMATION); */
+
+	/* ------------------------------------------------------ */
+	/* Association Request related information */
+	/* ------------------------------------------------------ */
+	/* Req_1. AvailableRequestFixedIEs */
+	if (psecnetwork != NULL) {
+
+		pAssocInfo->AvailableRequestFixedIEs |= NDIS_802_11_AI_REQFI_CAPABILITIES | NDIS_802_11_AI_REQFI_CURRENTAPADDRESS;
+		pAssocInfo->RequestFixedIEs.Capabilities = (unsigned short) *&psecnetwork->IEs[10];
+		_rtw_memcpy(pAssocInfo->RequestFixedIEs.CurrentAPAddress,
+			    &psecnetwork->MacAddress, 6);
+
+		pAssocInfo->OffsetRequestIEs = sizeof(NDIS_802_11_ASSOCIATION_INFORMATION);
+
+		if (check_fwstate(pmlmepriv, _FW_UNDER_LINKING | _FW_LINKED) == _TRUE) {
+
+			if (psecuritypriv->ndisauthtype >= Ndis802_11AuthModeWPA2)
+				pDest[0] = 48;		/* RSN Information Element */
+			else
+				pDest[0] = 221;	/* WPA(SSN) Information Element */
+
+			supp_ie = &psecuritypriv->supplicant_ie[0];
+
+			i = 13;	/* 0~11 is fixed information element		 */
+			while ((i < supp_ie[0]) && (i < 256)) {
+				if ((unsigned char)supp_ie[i] == pDest[0]) {
+					_rtw_memcpy((u8 *)(pDest),
+						    &supp_ie[i],
+						    supp_ie[1 + i] + 2);
+
+					break;
+				}
+
+				i = i + supp_ie[i + 1] + 2;
+				if (supp_ie[1 + i] == 0)
+					i = i + 1;
+
+			}
+
+
+			pAssocInfo->RequestIELength += (2 + supp_ie[1 + i]); /* (2 + psecnetwork->IEs[1+i]+4); */
+
+		}
+
+
+
+	}
+
+
+	/* ------------------------------------------------------ */
+	/* Association Response related information */
+	/* ------------------------------------------------------ */
+
+	if (check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE) {
+		tgt_network = &(pmlmepriv->cur_network);
+		if (tgt_network != NULL) {
+			pAssocInfo->AvailableResponseFixedIEs =
+				NDIS_802_11_AI_RESFI_CAPABILITIES
+				| NDIS_802_11_AI_RESFI_ASSOCIATIONID
+				;
+
+			pAssocInfo->ResponseFixedIEs.Capabilities = (unsigned short) *&tgt_network->network.IEs[10];
+			pAssocInfo->ResponseFixedIEs.StatusCode = 0;
+			pAssocInfo->ResponseFixedIEs.AssociationId = (unsigned short) tgt_network->aid;
+
+			pDest = (u8 *)pAssocInfo + sizeof(NDIS_802_11_ASSOCIATION_INFORMATION) + pAssocInfo->RequestIELength;
+			auth_ie = &psecuritypriv->authenticator_ie[0];
+
+
+			i = auth_ie[0] - 12;
+			if (i > 0) {
+				_rtw_memcpy((u8 *)&pDest[0], &auth_ie[1], i);
+				pAssocInfo->ResponseIELength = i;
+			}
+
+
+			pAssocInfo->OffsetResponseIEs = sizeof(NDIS_802_11_ASSOCIATION_INFORMATION) + pAssocInfo->RequestIELength;
+
+
+		}
+	}
+
+	return _TRUE;
+}
+#endif
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/core/rtw_ioctl_rtl.c linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/core/rtw_ioctl_rtl.c
--- linux-5.6.3/3rdparty/rtl8821ce/core/rtw_ioctl_rtl.c	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/core/rtw_ioctl_rtl.c	2020-04-10 16:35:06.773658060 +0300
@@ -0,0 +1,901 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#define  _RTW_IOCTL_RTL_C_
+
+#include <drv_types.h>
+
+#ifdef CONFIG_MP_INCLUDED
+	#include <rtw_mp_ioctl.h>
+#endif
+
+struct oid_obj_priv oid_rtl_seg_01_01[] = {
+	{1, &oid_null_function},										/* 0x80 */
+	{1, &oid_null_function},										/* 0x81 */
+	{1, &oid_null_function},										/* 0x82 */
+	{1, &oid_null_function},										/* 0x83 */ /* OID_RT_SET_SNIFFER_MODE */
+	{1, &oid_rt_get_signal_quality_hdl},							/* 0x84 */
+	{1, &oid_rt_get_small_packet_crc_hdl},						/* 0x85 */
+	{1, &oid_rt_get_middle_packet_crc_hdl},						/* 0x86 */
+	{1, &oid_rt_get_large_packet_crc_hdl},						/* 0x87 */
+	{1, &oid_rt_get_tx_retry_hdl},								/* 0x88 */
+	{1, &oid_rt_get_rx_retry_hdl},								/* 0x89 */
+	{1, &oid_rt_pro_set_fw_dig_state_hdl},						/* 0x8A */
+	{1, &oid_rt_pro_set_fw_ra_state_hdl}	,						/* 0x8B */
+	{1, &oid_null_function},										/* 0x8C */
+	{1, &oid_null_function},										/* 0x8D */
+	{1, &oid_null_function},										/* 0x8E */
+	{1, &oid_null_function},										/* 0x8F */
+	{1, &oid_rt_get_rx_total_packet_hdl},							/* 0x90 */
+	{1, &oid_rt_get_tx_beacon_ok_hdl},							/* 0x91 */
+	{1, &oid_rt_get_tx_beacon_err_hdl},							/* 0x92 */
+	{1, &oid_rt_get_rx_icv_err_hdl},								/* 0x93 */
+	{1, &oid_rt_set_encryption_algorithm_hdl},					/* 0x94 */
+	{1, &oid_null_function},										/* 0x95 */
+	{1, &oid_rt_get_preamble_mode_hdl},							/* 0x96 */
+	{1, &oid_null_function},										/* 0x97 */
+	{1, &oid_rt_get_ap_ip_hdl},									/* 0x98 */
+	{1, &oid_rt_get_channelplan_hdl},							/* 0x99	 */
+	{1, &oid_rt_set_preamble_mode_hdl},	 						/* 0x9A */
+	{1, &oid_rt_set_bcn_intvl_hdl},								/* 0x9B */
+	{1, &oid_null_function},										/* 0x9C */
+	{1, &oid_rt_dedicate_probe_hdl},								/* 0x9D */
+	{1, &oid_null_function},										/* 0x9E */
+	{1, &oid_null_function},										/* 0x9F */
+	{1, &oid_null_function},										/* 0xA0 */
+	{1, &oid_null_function},										/* 0xA1 */
+	{1, &oid_null_function},										/* 0xA2 */
+	{1, &oid_null_function},										/* 0xA3 */
+	{1, &oid_null_function},										/* 0xA4 */
+	{1, &oid_null_function},										/* 0xA5 */
+	{1, &oid_null_function},										/* 0xA6 */
+	{1, &oid_rt_get_total_tx_bytes_hdl},							/* 0xA7 */
+	{1, &oid_rt_get_total_rx_bytes_hdl},							/* 0xA8 */
+	{1, &oid_rt_current_tx_power_level_hdl},						/* 0xA9	 */
+	{1, &oid_rt_get_enc_key_mismatch_count_hdl},	 			/* 0xAA */
+	{1, &oid_rt_get_enc_key_match_count_hdl},					/* 0xAB */
+	{1, &oid_rt_get_channel_hdl},								/* 0xAC */
+	{1, &oid_rt_set_channelplan_hdl},								/* 0xAD */
+	{1, &oid_rt_get_hardware_radio_off_hdl},						/* 0xAE */
+	{1, &oid_null_function},										/* 0xAF */
+	{1, &oid_null_function},										/* 0xB0 */
+	{1, &oid_null_function},										/* 0xB1 */
+	{1, &oid_null_function},										/* 0xB2 */
+	{1, &oid_null_function},										/* 0xB3 */
+	{1, &oid_rt_get_key_mismatch_hdl},							/* 0xB4 */
+	{1, &oid_null_function},										/* 0xB5 */
+	{1, &oid_null_function},										/* 0xB6 */
+	{1, &oid_null_function},										/* 0xB7 */
+	{1, &oid_null_function},										/* 0xB8 */
+	{1, &oid_null_function},										/* 0xB9	 */
+	{1, &oid_null_function},	 									/* 0xBA */
+	{1, &oid_rt_supported_wireless_mode_hdl},					/* 0xBB */
+	{1, &oid_rt_get_channel_list_hdl},							/* 0xBC */
+	{1, &oid_rt_get_scan_in_progress_hdl},						/* 0xBD */
+	{1, &oid_null_function},										/* 0xBE */
+	{1, &oid_null_function},										/* 0xBF */
+	{1, &oid_null_function},										/* 0xC0 */
+	{1, &oid_rt_forced_data_rate_hdl},							/* 0xC1 */
+	{1, &oid_rt_wireless_mode_for_scan_list_hdl},					/* 0xC2 */
+	{1, &oid_rt_get_bss_wireless_mode_hdl},						/* 0xC3 */
+	{1, &oid_rt_scan_with_magic_packet_hdl},					/* 0xC4 */
+	{1, &oid_null_function},										/* 0xC5 */
+	{1, &oid_null_function},										/* 0xC6 */
+	{1, &oid_null_function},										/* 0xC7 */
+	{1, &oid_null_function},										/* 0xC8 */
+	{1, &oid_null_function},										/* 0xC9	 */
+	{1, &oid_null_function},	 									/* 0xCA */
+	{1, &oid_null_function},										/* 0xCB */
+	{1, &oid_null_function},										/* 0xCC */
+	{1, &oid_null_function},										/* 0xCD */
+	{1, &oid_null_function},										/* 0xCE */
+	{1, &oid_null_function},										/* 0xCF */
+
+};
+
+struct oid_obj_priv oid_rtl_seg_01_03[] = {
+	{1, &oid_rt_ap_get_associated_station_list_hdl},				/* 0x00 */
+	{1, &oid_null_function},										/* 0x01 */
+	{1, &oid_rt_ap_switch_into_ap_mode_hdl},					/* 0x02 */
+	{1, &oid_null_function},										/* 0x03 */
+	{1, &oid_rt_ap_supported_hdl},								/* 0x04 */
+	{1, &oid_rt_ap_set_passphrase_hdl},							/* 0x05 */
+
+};
+
+struct oid_obj_priv oid_rtl_seg_01_11[] = {
+	{1, &oid_null_function},					/* 0xC0	OID_RT_PRO_RX_FILTER	 */
+	{1, &oid_null_function},					/* 0xC1	OID_CE_USB_WRITE_REGISTRY */
+	{1, &oid_null_function},					/* 0xC2	OID_CE_USB_READ_REGISTRY */
+	{1, &oid_null_function},					/* 0xC3	OID_RT_PRO_SET_INITIAL_GAIN */
+	{1, &oid_null_function},					/* 0xC4	OID_RT_PRO_SET_BB_RF_STANDBY_MODE */
+	{1, &oid_null_function},					/* 0xC5	OID_RT_PRO_SET_BB_RF_SHUTDOWN_MODE */
+	{1, &oid_null_function},					/* 0xC6	OID_RT_PRO_SET_TX_CHARGE_PUMP */
+	{1, &oid_null_function},					/* 0xC7	OID_RT_PRO_SET_RX_CHARGE_PUMP */
+	{1, &oid_rt_pro_rf_write_registry_hdl},	/* 0xC8	 */
+	{1, &oid_rt_pro_rf_read_registry_hdl},	/* 0xC9	 */
+	{1, &oid_null_function}					/* 0xCA	OID_RT_PRO_QUERY_RF_TYPE */
+
+};
+
+struct oid_obj_priv oid_rtl_seg_03_00[] = {
+	{1, &oid_null_function},										/* 0x00 */
+	{1, &oid_rt_get_connect_state_hdl},							/* 0x01 */
+	{1, &oid_null_function},										/* 0x02 */
+	{1, &oid_null_function},										/* 0x03 */
+	{1, &oid_rt_set_default_key_id_hdl},							/* 0x04 */
+
+
+};
+
+
+/* **************  oid_rtl_seg_01_01 section start ************** */
+
+NDIS_STATUS oid_rt_pro_set_fw_dig_state_hdl(struct oid_par_priv *poid_par_priv)
+{
+	NDIS_STATUS		status = NDIS_STATUS_SUCCESS;
+#if 0
+	PADAPTER		Adapter = (PADAPTER)(poid_par_priv->adapter_context);
+	_irqL			oldirql;
+
+
+	if (poid_par_priv->type_of_oid != SET_OID) {
+		status = NDIS_STATUS_NOT_ACCEPTED;
+		return status;
+	}
+
+	_irqlevel_changed_(&oldirql, LOWER);
+	if (poid_par_priv->information_buf_len >= sizeof(struct setdig_parm)) {
+		/* DEBUG_ERR(("===> oid_rt_pro_set_fw_dig_state_hdl. type:0x%02x.\n",*((unsigned char*)poid_par_priv->information_buf )));	 */
+		if (!rtw_setfwdig_cmd(Adapter, *((unsigned char *)poid_par_priv->information_buf)))
+			status = NDIS_STATUS_NOT_ACCEPTED;
+
+	} else
+		status = NDIS_STATUS_NOT_ACCEPTED;
+	_irqlevel_changed_(&oldirql, RAISE);
+#endif
+	return status;
+}
+/* ----------------------------------------------------------------------------- */
+NDIS_STATUS oid_rt_pro_set_fw_ra_state_hdl(struct oid_par_priv *poid_par_priv)
+{
+
+	NDIS_STATUS		status = NDIS_STATUS_SUCCESS;
+#if 0
+	PADAPTER		Adapter = (PADAPTER)(poid_par_priv->adapter_context);
+	_irqL			oldirql;
+
+	if (poid_par_priv->type_of_oid != SET_OID) {
+		status = NDIS_STATUS_NOT_ACCEPTED;
+		return status;
+	}
+
+
+	_irqlevel_changed_(&oldirql, LOWER);
+
+	if (poid_par_priv->information_buf_len >= sizeof(struct setra_parm)) {
+		/* DEBUG_ERR(("===> oid_rt_pro_set_fw_ra_state_hdl. type:0x%02x.\n",*((unsigned char*)poid_par_priv->information_buf )));	 */
+		if (!rtw_setfwra_cmd(Adapter, *((unsigned char *)poid_par_priv->information_buf)))
+			status = NDIS_STATUS_NOT_ACCEPTED;
+
+	} else
+		status = NDIS_STATUS_NOT_ACCEPTED;
+	_irqlevel_changed_(&oldirql, RAISE);
+#endif
+	return status;
+}
+/* ----------------------------------------------------------------------------- */
+NDIS_STATUS oid_rt_get_signal_quality_hdl(struct oid_par_priv *poid_par_priv)
+{
+	NDIS_STATUS		status = NDIS_STATUS_SUCCESS;
+	PADAPTER		padapter = (PADAPTER)(poid_par_priv->adapter_context);
+
+	/* DEBUG_ERR(("<**********************oid_rt_get_signal_quality_hdl\n")); */
+	if (poid_par_priv->type_of_oid != QUERY_OID) {
+		status = NDIS_STATUS_NOT_ACCEPTED;
+		return status;
+	}
+
+#if 0
+	if (pMgntInfo->mAssoc || pMgntInfo->mIbss) {
+		ulInfo = pAdapter->RxStats.SignalQuality;
+		*poid_par_priv->bytes_rw = poid_par_priv->information_buf_len;
+	} else {
+		ulInfo = 0xffffffff; /* It stands for -1 in 4-byte integer. */
+	}
+	break;
+#endif
+
+	return status;
+}
+
+/* ------------------------------------------------------------------------------ */
+
+NDIS_STATUS oid_rt_get_small_packet_crc_hdl(struct oid_par_priv *poid_par_priv)
+{
+	NDIS_STATUS		status = NDIS_STATUS_SUCCESS;
+	PADAPTER		padapter = (PADAPTER)(poid_par_priv->adapter_context);
+
+	if (poid_par_priv->type_of_oid != QUERY_OID) {
+		status = NDIS_STATUS_NOT_ACCEPTED;
+		return status;
+	}
+
+	if (poid_par_priv->information_buf_len >=  sizeof(ULONG)) {
+		*(ULONG *)poid_par_priv->information_buf = padapter->recvpriv.rx_smallpacket_crcerr;
+		*poid_par_priv->bytes_rw = poid_par_priv->information_buf_len;
+	} else
+		status = NDIS_STATUS_INVALID_LENGTH;
+
+	return status;
+}
+/* ------------------------------------------------------------------------------ */
+NDIS_STATUS oid_rt_get_middle_packet_crc_hdl(struct oid_par_priv *poid_par_priv)
+{
+	NDIS_STATUS		status = NDIS_STATUS_SUCCESS;
+	PADAPTER		padapter = (PADAPTER)(poid_par_priv->adapter_context);
+
+	if (poid_par_priv->type_of_oid != QUERY_OID) {
+		status = NDIS_STATUS_NOT_ACCEPTED;
+		return status;
+	}
+
+	if (poid_par_priv->information_buf_len >=  sizeof(ULONG)) {
+		*(ULONG *)poid_par_priv->information_buf = padapter->recvpriv.rx_middlepacket_crcerr;
+		*poid_par_priv->bytes_rw = poid_par_priv->information_buf_len;
+	} else
+		status = NDIS_STATUS_INVALID_LENGTH;
+
+
+	return status;
+}
+/* ------------------------------------------------------------------------------ */
+NDIS_STATUS oid_rt_get_large_packet_crc_hdl(struct oid_par_priv *poid_par_priv)
+{
+	NDIS_STATUS		status = NDIS_STATUS_SUCCESS;
+	PADAPTER		padapter = (PADAPTER)(poid_par_priv->adapter_context);
+
+	if (poid_par_priv->type_of_oid != QUERY_OID) {
+		status = NDIS_STATUS_NOT_ACCEPTED;
+		return status;
+	}
+
+	if (poid_par_priv->information_buf_len >=  sizeof(ULONG)) {
+		*(ULONG *)poid_par_priv->information_buf = padapter->recvpriv.rx_largepacket_crcerr;
+		*poid_par_priv->bytes_rw = poid_par_priv->information_buf_len;
+	} else
+		status = NDIS_STATUS_INVALID_LENGTH;
+
+
+	return status;
+}
+
+/* ------------------------------------------------------------------------------ */
+NDIS_STATUS oid_rt_get_tx_retry_hdl(struct oid_par_priv *poid_par_priv)
+{
+	NDIS_STATUS		status = NDIS_STATUS_SUCCESS;
+	PADAPTER		padapter = (PADAPTER)(poid_par_priv->adapter_context);
+
+	if (poid_par_priv->type_of_oid != QUERY_OID) {
+		status = NDIS_STATUS_NOT_ACCEPTED;
+		return status;
+	}
+
+	return status;
+}
+NDIS_STATUS oid_rt_get_rx_retry_hdl(struct oid_par_priv *poid_par_priv)
+{
+	NDIS_STATUS		status = NDIS_STATUS_SUCCESS;
+	PADAPTER		padapter = (PADAPTER)(poid_par_priv->adapter_context);
+
+	if (poid_par_priv->type_of_oid != QUERY_OID) {
+		status = NDIS_STATUS_NOT_ACCEPTED;
+		return status;
+	}
+	*poid_par_priv->bytes_rw = poid_par_priv->information_buf_len;
+	return status;
+}
+/* ------------------------------------------------------------------------------ */
+NDIS_STATUS oid_rt_get_rx_total_packet_hdl(struct oid_par_priv *poid_par_priv)
+{
+	NDIS_STATUS		status = NDIS_STATUS_SUCCESS;
+	PADAPTER		padapter = (PADAPTER)(poid_par_priv->adapter_context);
+
+	if (poid_par_priv->type_of_oid != QUERY_OID) {
+		status = NDIS_STATUS_NOT_ACCEPTED;
+		return status;
+	}
+	if (poid_par_priv->information_buf_len >=  sizeof(ULONG)) {
+		*(u64 *)poid_par_priv->information_buf = padapter->recvpriv.rx_pkts + padapter->recvpriv.rx_drop;
+		*poid_par_priv->bytes_rw = poid_par_priv->information_buf_len;
+	} else
+		status = NDIS_STATUS_INVALID_LENGTH;
+
+
+	return status;
+}
+/* ------------------------------------------------------------------------------ */
+NDIS_STATUS oid_rt_get_tx_beacon_ok_hdl(struct oid_par_priv *poid_par_priv)
+{
+	NDIS_STATUS		status = NDIS_STATUS_SUCCESS;
+	PADAPTER		padapter = (PADAPTER)(poid_par_priv->adapter_context);
+
+	if (poid_par_priv->type_of_oid != QUERY_OID) {
+		status = NDIS_STATUS_NOT_ACCEPTED;
+		return status;
+	}
+
+	return status;
+}
+NDIS_STATUS oid_rt_get_tx_beacon_err_hdl(struct oid_par_priv *poid_par_priv)
+{
+	NDIS_STATUS		status = NDIS_STATUS_SUCCESS;
+	PADAPTER		padapter = (PADAPTER)(poid_par_priv->adapter_context);
+
+	if (poid_par_priv->type_of_oid != QUERY_OID) {
+		status = NDIS_STATUS_NOT_ACCEPTED;
+		return status;
+	}
+
+	return status;
+}
+/* ------------------------------------------------------------------------------ */
+NDIS_STATUS oid_rt_get_rx_icv_err_hdl(struct oid_par_priv *poid_par_priv)
+{
+	NDIS_STATUS		status = NDIS_STATUS_SUCCESS;
+	PADAPTER		padapter = (PADAPTER)(poid_par_priv->adapter_context);
+
+	if (poid_par_priv->type_of_oid != QUERY_OID) {
+		status = NDIS_STATUS_NOT_ACCEPTED;
+		return status;
+	}
+	if (poid_par_priv->information_buf_len >= sizeof(u32)) {
+		/* _rtw_memcpy(*(uint *)poid_par_priv->information_buf,padapter->recvpriv.rx_icv_err,sizeof(u32)); */
+		*(uint *)poid_par_priv->information_buf = padapter->recvpriv.rx_icv_err;
+		*poid_par_priv->bytes_rw = poid_par_priv->information_buf_len;
+	} else
+		status = NDIS_STATUS_INVALID_LENGTH ;
+
+
+	return status;
+}
+/* ------------------------------------------------------------------------------ */
+NDIS_STATUS oid_rt_set_encryption_algorithm_hdl(struct oid_par_priv *poid_par_priv)
+{
+	NDIS_STATUS		status = NDIS_STATUS_SUCCESS;
+	PADAPTER		padapter = (PADAPTER)(poid_par_priv->adapter_context);
+
+	if (poid_par_priv->type_of_oid != SET_OID) {
+		status = NDIS_STATUS_NOT_ACCEPTED;
+		return status;
+	}
+
+	return status;
+}
+/* ------------------------------------------------------------------------------ */
+NDIS_STATUS oid_rt_get_preamble_mode_hdl(struct oid_par_priv *poid_par_priv)
+{
+	NDIS_STATUS		status = NDIS_STATUS_SUCCESS;
+	PADAPTER		padapter = (PADAPTER)(poid_par_priv->adapter_context);
+	ULONG			preamblemode = 0 ;
+
+	if (poid_par_priv->type_of_oid != QUERY_OID) {
+		status = NDIS_STATUS_NOT_ACCEPTED;
+		return status;
+	}
+	if (poid_par_priv->information_buf_len >= sizeof(ULONG)) {
+		if (padapter->registrypriv.preamble == PREAMBLE_LONG)
+			preamblemode = 0;
+		else if (padapter->registrypriv.preamble == PREAMBLE_AUTO)
+			preamblemode = 1;
+		else if (padapter->registrypriv.preamble == PREAMBLE_SHORT)
+			preamblemode = 2;
+
+
+		*(ULONG *)poid_par_priv->information_buf = preamblemode ;
+		*poid_par_priv->bytes_rw = poid_par_priv->information_buf_len;
+	} else
+		status = NDIS_STATUS_INVALID_LENGTH ;
+	return status;
+}
+/* ------------------------------------------------------------------------------ */
+NDIS_STATUS oid_rt_get_ap_ip_hdl(struct oid_par_priv *poid_par_priv)
+{
+	NDIS_STATUS		status = NDIS_STATUS_SUCCESS;
+	PADAPTER		padapter = (PADAPTER)(poid_par_priv->adapter_context);
+
+	if (poid_par_priv->type_of_oid != QUERY_OID) {
+		status = NDIS_STATUS_NOT_ACCEPTED;
+		return status;
+	}
+
+	return status;
+}
+
+NDIS_STATUS oid_rt_get_channelplan_hdl(struct oid_par_priv *poid_par_priv)
+{
+	NDIS_STATUS		status = NDIS_STATUS_SUCCESS;
+	PADAPTER		padapter = (PADAPTER)(poid_par_priv->adapter_context);
+	struct rf_ctl_t *rfctl = adapter_to_rfctl(padapter);
+
+	if (poid_par_priv->type_of_oid != QUERY_OID) {
+		status = NDIS_STATUS_NOT_ACCEPTED;
+		return status;
+	}
+	*poid_par_priv->bytes_rw = poid_par_priv->information_buf_len;
+	*(u16 *)poid_par_priv->information_buf = rfctl->ChannelPlan;
+
+	return status;
+}
+NDIS_STATUS oid_rt_set_channelplan_hdl(struct oid_par_priv *poid_par_priv)
+{
+	NDIS_STATUS		status = NDIS_STATUS_SUCCESS;
+	PADAPTER		padapter = (PADAPTER)(poid_par_priv->adapter_context);
+	struct rf_ctl_t *rfctl = adapter_to_rfctl(padapter);
+
+	if (poid_par_priv->type_of_oid != SET_OID) {
+		status = NDIS_STATUS_NOT_ACCEPTED;
+		return status;
+	}
+
+	rfctl->ChannelPlan  = *(u16 *)poid_par_priv->information_buf;
+
+	return status;
+}
+/* ------------------------------------------------------------------------------ */
+NDIS_STATUS oid_rt_set_preamble_mode_hdl(struct oid_par_priv *poid_par_priv)
+{
+	NDIS_STATUS		status = NDIS_STATUS_SUCCESS;
+	PADAPTER		padapter = (PADAPTER)(poid_par_priv->adapter_context);
+	ULONG			preamblemode = 0;
+	if (poid_par_priv->type_of_oid != SET_OID) {
+		status = NDIS_STATUS_NOT_ACCEPTED;
+		return status;
+	}
+
+	if (poid_par_priv->information_buf_len >= sizeof(ULONG)) {
+		preamblemode = *(ULONG *)poid_par_priv->information_buf ;
+		if (preamblemode == 0)
+			padapter->registrypriv.preamble = PREAMBLE_LONG;
+		else if (preamblemode == 1)
+			padapter->registrypriv.preamble = PREAMBLE_AUTO;
+		else if (preamblemode == 2)
+			padapter->registrypriv.preamble = PREAMBLE_SHORT;
+
+		*(ULONG *)poid_par_priv->information_buf = preamblemode ;
+		*poid_par_priv->bytes_rw = poid_par_priv->information_buf_len;
+	} else
+		status = NDIS_STATUS_INVALID_LENGTH ;
+
+	return status;
+}
+/* ------------------------------------------------------------------------------ */
+NDIS_STATUS oid_rt_set_bcn_intvl_hdl(struct oid_par_priv *poid_par_priv)
+{
+	NDIS_STATUS		status = NDIS_STATUS_SUCCESS;
+	PADAPTER		padapter = (PADAPTER)(poid_par_priv->adapter_context);
+
+	if (poid_par_priv->type_of_oid != SET_OID) {
+		status = NDIS_STATUS_NOT_ACCEPTED;
+		return status;
+	}
+
+	return status;
+}
+NDIS_STATUS oid_rt_dedicate_probe_hdl(struct oid_par_priv *poid_par_priv)
+{
+	NDIS_STATUS		status = NDIS_STATUS_SUCCESS;
+	PADAPTER		padapter = (PADAPTER)(poid_par_priv->adapter_context);
+
+	return status;
+}
+/* ------------------------------------------------------------------------------ */
+NDIS_STATUS oid_rt_get_total_tx_bytes_hdl(struct oid_par_priv *poid_par_priv)
+{
+	NDIS_STATUS		status = NDIS_STATUS_SUCCESS;
+	PADAPTER		padapter = (PADAPTER)(poid_par_priv->adapter_context);
+
+	if (poid_par_priv->type_of_oid != QUERY_OID) {
+		status = NDIS_STATUS_NOT_ACCEPTED;
+		return status;
+	}
+	if (poid_par_priv->information_buf_len >= sizeof(ULONG)) {
+		*(u64 *)poid_par_priv->information_buf = padapter->xmitpriv.tx_bytes;
+		*poid_par_priv->bytes_rw = poid_par_priv->information_buf_len;
+	} else
+		status = NDIS_STATUS_INVALID_LENGTH ;
+
+
+	return status;
+}
+/* ------------------------------------------------------------------------------ */
+NDIS_STATUS oid_rt_get_total_rx_bytes_hdl(struct oid_par_priv *poid_par_priv)
+{
+	NDIS_STATUS		status = NDIS_STATUS_SUCCESS;
+	PADAPTER		padapter = (PADAPTER)(poid_par_priv->adapter_context);
+
+	if (poid_par_priv->type_of_oid != QUERY_OID) {
+		status = NDIS_STATUS_NOT_ACCEPTED;
+		return status;
+	}
+	if (poid_par_priv->information_buf_len >= sizeof(ULONG)) {
+		/* _rtw_memcpy(*(uint *)poid_par_priv->information_buf,padapter->recvpriv.rx_icv_err,sizeof(u32)); */
+		*(u64 *)poid_par_priv->information_buf = padapter->recvpriv.rx_bytes;
+		*poid_par_priv->bytes_rw = poid_par_priv->information_buf_len;
+	} else
+		status = NDIS_STATUS_INVALID_LENGTH ;
+	return status;
+}
+/* ------------------------------------------------------------------------------ */
+NDIS_STATUS oid_rt_current_tx_power_level_hdl(struct oid_par_priv *poid_par_priv)
+{
+	NDIS_STATUS		status = NDIS_STATUS_SUCCESS;
+	PADAPTER		padapter = (PADAPTER)(poid_par_priv->adapter_context);
+
+	return status;
+}
+NDIS_STATUS oid_rt_get_enc_key_mismatch_count_hdl(struct oid_par_priv *poid_par_priv)
+{
+	NDIS_STATUS		status = NDIS_STATUS_SUCCESS;
+	PADAPTER		padapter = (PADAPTER)(poid_par_priv->adapter_context);
+
+	if (poid_par_priv->type_of_oid != QUERY_OID) {
+		status = NDIS_STATUS_NOT_ACCEPTED;
+		return status;
+	}
+
+	return status;
+}
+NDIS_STATUS oid_rt_get_enc_key_match_count_hdl(struct oid_par_priv *poid_par_priv)
+{
+	NDIS_STATUS		status = NDIS_STATUS_SUCCESS;
+	PADAPTER		padapter = (PADAPTER)(poid_par_priv->adapter_context);
+
+	if (poid_par_priv->type_of_oid != QUERY_OID) {
+		status = NDIS_STATUS_NOT_ACCEPTED;
+		return status;
+	}
+
+	return status;
+}
+NDIS_STATUS oid_rt_get_channel_hdl(struct oid_par_priv *poid_par_priv)
+{
+	NDIS_STATUS		status = NDIS_STATUS_SUCCESS;
+	PADAPTER		padapter = (PADAPTER)(poid_par_priv->adapter_context);
+	struct	mlme_priv	*pmlmepriv = &padapter->mlmepriv;
+	NDIS_802_11_CONFIGURATION		*pnic_Config;
+
+	ULONG   channelnum;
+
+	if (poid_par_priv->type_of_oid != QUERY_OID) {
+		status = NDIS_STATUS_NOT_ACCEPTED;
+		return status;
+	}
+
+	if ((check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE) ||
+	    (check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE) == _TRUE))
+		pnic_Config = &pmlmepriv->cur_network.network.Configuration;
+	else
+		pnic_Config = &padapter->registrypriv.dev_network.Configuration;
+
+	channelnum = pnic_Config->DSConfig;
+	*(ULONG *)poid_par_priv->information_buf = channelnum;
+
+	*poid_par_priv->bytes_rw = poid_par_priv->information_buf_len;
+
+
+
+
+	return status;
+}
+NDIS_STATUS oid_rt_get_hardware_radio_off_hdl(struct oid_par_priv *poid_par_priv)
+{
+	NDIS_STATUS		status = NDIS_STATUS_SUCCESS;
+	PADAPTER		padapter = (PADAPTER)(poid_par_priv->adapter_context);
+
+	if (poid_par_priv->type_of_oid != QUERY_OID) {
+		status = NDIS_STATUS_NOT_ACCEPTED;
+		return status;
+	}
+
+	return status;
+}
+NDIS_STATUS oid_rt_get_key_mismatch_hdl(struct oid_par_priv *poid_par_priv)
+{
+	NDIS_STATUS		status = NDIS_STATUS_SUCCESS;
+	PADAPTER		padapter = (PADAPTER)(poid_par_priv->adapter_context);
+
+	if (poid_par_priv->type_of_oid != QUERY_OID) {
+		status = NDIS_STATUS_NOT_ACCEPTED;
+		return status;
+	}
+
+	return status;
+}
+NDIS_STATUS oid_rt_supported_wireless_mode_hdl(struct oid_par_priv *poid_par_priv)
+{
+	NDIS_STATUS		status = NDIS_STATUS_SUCCESS;
+	PADAPTER		padapter = (PADAPTER)(poid_par_priv->adapter_context);
+	ULONG			ulInfo = 0 ;
+	/* DEBUG_ERR(("<**********************oid_rt_supported_wireless_mode_hdl\n"));	 */
+	if (poid_par_priv->type_of_oid != QUERY_OID) {
+		status = NDIS_STATUS_NOT_ACCEPTED;
+		return status;
+	}
+	if (poid_par_priv->information_buf_len >= sizeof(ULONG)) {
+		ulInfo |= 0x0100; /* WIRELESS_MODE_B */
+		ulInfo |= 0x0200; /* WIRELESS_MODE_G */
+		ulInfo |= 0x0400; /* WIRELESS_MODE_A */
+
+		*(ULONG *) poid_par_priv->information_buf = ulInfo;
+		/* DEBUG_ERR(("<===oid_rt_supported_wireless_mode %x\n",ulInfo));	 */
+		*poid_par_priv->bytes_rw = poid_par_priv->information_buf_len;
+	} else
+		status = NDIS_STATUS_INVALID_LENGTH;
+
+	return status;
+}
+NDIS_STATUS oid_rt_get_channel_list_hdl(struct oid_par_priv *poid_par_priv)
+{
+	NDIS_STATUS		status = NDIS_STATUS_SUCCESS;
+	PADAPTER		padapter = (PADAPTER)(poid_par_priv->adapter_context);
+
+	if (poid_par_priv->type_of_oid != QUERY_OID) {
+		status = NDIS_STATUS_NOT_ACCEPTED;
+		return status;
+	}
+
+	return status;
+}
+NDIS_STATUS oid_rt_get_scan_in_progress_hdl(struct oid_par_priv *poid_par_priv)
+{
+	NDIS_STATUS		status = NDIS_STATUS_SUCCESS;
+	PADAPTER		padapter = (PADAPTER)(poid_par_priv->adapter_context);
+
+	if (poid_par_priv->type_of_oid != QUERY_OID) {
+		status = NDIS_STATUS_NOT_ACCEPTED;
+		return status;
+	}
+
+	return status;
+}
+
+
+NDIS_STATUS oid_rt_forced_data_rate_hdl(struct oid_par_priv *poid_par_priv)
+{
+	NDIS_STATUS		status = NDIS_STATUS_SUCCESS;
+	PADAPTER		padapter = (PADAPTER)(poid_par_priv->adapter_context);
+
+	return status;
+}
+NDIS_STATUS oid_rt_wireless_mode_for_scan_list_hdl(struct oid_par_priv *poid_par_priv)
+{
+	NDIS_STATUS		status = NDIS_STATUS_SUCCESS;
+	PADAPTER		padapter = (PADAPTER)(poid_par_priv->adapter_context);
+
+	return status;
+}
+NDIS_STATUS oid_rt_get_bss_wireless_mode_hdl(struct oid_par_priv *poid_par_priv)
+{
+	NDIS_STATUS		status = NDIS_STATUS_SUCCESS;
+	PADAPTER		padapter = (PADAPTER)(poid_par_priv->adapter_context);
+
+	if (poid_par_priv->type_of_oid != QUERY_OID) {
+		status = NDIS_STATUS_NOT_ACCEPTED;
+		return status;
+	}
+
+	return status;
+}
+
+NDIS_STATUS oid_rt_scan_with_magic_packet_hdl(struct oid_par_priv *poid_par_priv)
+{
+	NDIS_STATUS		status = NDIS_STATUS_SUCCESS;
+	PADAPTER		padapter = (PADAPTER)(poid_par_priv->adapter_context);
+
+	return status;
+}
+/* **************  oid_rtl_seg_01_01 section end ************** */
+
+/* **************  oid_rtl_seg_01_03 section start ************** */
+NDIS_STATUS oid_rt_ap_get_associated_station_list_hdl(struct oid_par_priv *poid_par_priv)
+{
+	NDIS_STATUS		status = NDIS_STATUS_SUCCESS;
+	PADAPTER		padapter = (PADAPTER)(poid_par_priv->adapter_context);
+
+	if (poid_par_priv->type_of_oid != QUERY_OID) {
+		status = NDIS_STATUS_NOT_ACCEPTED;
+		return status;
+	}
+
+	return status;
+}
+NDIS_STATUS oid_rt_ap_switch_into_ap_mode_hdl(struct oid_par_priv *poid_par_priv)
+{
+	NDIS_STATUS		status = NDIS_STATUS_SUCCESS;
+	PADAPTER		padapter = (PADAPTER)(poid_par_priv->adapter_context);
+
+	return status;
+}
+NDIS_STATUS oid_rt_ap_supported_hdl(struct oid_par_priv *poid_par_priv)
+{
+	NDIS_STATUS		status = NDIS_STATUS_SUCCESS;
+	PADAPTER		padapter = (PADAPTER)(poid_par_priv->adapter_context);
+
+	return status;
+}
+NDIS_STATUS oid_rt_ap_set_passphrase_hdl(struct oid_par_priv *poid_par_priv)
+{
+	NDIS_STATUS		status = NDIS_STATUS_SUCCESS;
+	PADAPTER		padapter = (PADAPTER)(poid_par_priv->adapter_context);
+
+	if (poid_par_priv->type_of_oid != SET_OID) {
+		status = NDIS_STATUS_NOT_ACCEPTED;
+		return status;
+	}
+
+	return status;
+}
+
+/* **************  oid_rtl_seg_01_03 section end ************** */
+
+/* ****************  oid_rtl_seg_01_11   section start **************** */
+NDIS_STATUS oid_rt_pro_rf_write_registry_hdl(struct oid_par_priv *poid_par_priv)
+{
+	NDIS_STATUS		status = NDIS_STATUS_SUCCESS;
+	PADAPTER		Adapter = (PADAPTER)(poid_par_priv->adapter_context);
+	_irqL			oldirql;
+	/* DEBUG_ERR(("<**********************oid_rt_pro_rf_write_registry_hdl\n")); */
+	if (poid_par_priv->type_of_oid != SET_OID) { /* QUERY_OID */
+		status = NDIS_STATUS_NOT_ACCEPTED;
+		return status;
+	}
+
+	_irqlevel_changed_(&oldirql, LOWER);
+	if (poid_par_priv->information_buf_len == (sizeof(unsigned long) * 3)) {
+		/* RegOffsetValue	- The offset of RF register to write. */
+		/* RegDataWidth	- The data width of RF register to write. */
+		/* RegDataValue	- The value to write. */
+		/* RegOffsetValue = *((unsigned long*)InformationBuffer); */
+		/* RegDataWidth = *((unsigned long*)InformationBuffer+1);	   */
+		/* RegDataValue =  *((unsigned long*)InformationBuffer+2);	 */
+		if (!rtw_setrfreg_cmd(Adapter,
+			      *(unsigned char *)poid_par_priv->information_buf,
+			(unsigned long)(*((unsigned long *)poid_par_priv->information_buf + 2))))
+			status = NDIS_STATUS_NOT_ACCEPTED;
+
+	} else
+		status = NDIS_STATUS_INVALID_LENGTH;
+	_irqlevel_changed_(&oldirql, RAISE);
+
+	return status;
+}
+
+/* ------------------------------------------------------------------------------ */
+NDIS_STATUS oid_rt_pro_rf_read_registry_hdl(struct oid_par_priv *poid_par_priv)
+{
+	NDIS_STATUS		status = NDIS_STATUS_SUCCESS;
+#if 0
+	PADAPTER		Adapter = (PADAPTER)(poid_par_priv->adapter_context);
+	_irqL	oldirql;
+
+	/* DEBUG_ERR(("<**********************oid_rt_pro_rf_read_registry_hdl\n")); */
+	if (poid_par_priv->type_of_oid != SET_OID) { /* QUERY_OID */
+		status = NDIS_STATUS_NOT_ACCEPTED;
+		return status;
+	}
+
+	_irqlevel_changed_(&oldirql, LOWER);
+	if (poid_par_priv->information_buf_len == (sizeof(unsigned long) * 3)) {
+		if (Adapter->mppriv.act_in_progress == _TRUE)
+			status = NDIS_STATUS_NOT_ACCEPTED;
+		else {
+			/* init workparam */
+			Adapter->mppriv.act_in_progress = _TRUE;
+			Adapter->mppriv.workparam.bcompleted = _FALSE;
+			Adapter->mppriv.workparam.act_type = MPT_READ_RF;
+			Adapter->mppriv.workparam.io_offset = *(unsigned long *)poid_par_priv->information_buf;
+			Adapter->mppriv.workparam.io_value = 0xcccccccc;
+
+			/* RegOffsetValue	- The offset of RF register to read. */
+			/* RegDataWidth	- The data width of RF register to read. */
+			/* RegDataValue	- The value to read. */
+			/* RegOffsetValue = *((unsigned long*)InformationBuffer); */
+			/* RegDataWidth = *((unsigned long*)InformationBuffer+1);	   */
+			/* RegDataValue =  *((unsigned long*)InformationBuffer+2);	   	 	                   */
+			if (!rtw_getrfreg_cmd(Adapter,
+				*(unsigned char *)poid_par_priv->information_buf,
+				(unsigned char *)&Adapter->mppriv.workparam.io_value))
+				status = NDIS_STATUS_NOT_ACCEPTED;
+		}
+
+
+	} else
+		status = NDIS_STATUS_INVALID_LENGTH;
+	_irqlevel_changed_(&oldirql, RAISE);
+#endif
+	return status;
+}
+
+/* ****************  oid_rtl_seg_01_11   section end****************	 */
+
+
+/* **************  oid_rtl_seg_03_00 section start **************  */
+enum _CONNECT_STATE_ {
+	CHECKINGSTATUS,
+	ASSOCIATED,
+	ADHOCMODE,
+	NOTASSOCIATED
+};
+
+NDIS_STATUS oid_rt_get_connect_state_hdl(struct oid_par_priv *poid_par_priv)
+{
+	NDIS_STATUS		status = NDIS_STATUS_SUCCESS;
+	PADAPTER		padapter = (PADAPTER)(poid_par_priv->adapter_context);
+
+	struct mlme_priv	*pmlmepriv = &(padapter->mlmepriv);
+
+	ULONG ulInfo;
+
+	if (poid_par_priv->type_of_oid != QUERY_OID) {
+		status = NDIS_STATUS_NOT_ACCEPTED;
+		return status;
+	}
+
+	/* nStatus==0	CheckingStatus */
+	/* nStatus==1	Associated */
+	/* nStatus==2	AdHocMode */
+	/* nStatus==3	NotAssociated */
+
+	if (check_fwstate(pmlmepriv, _FW_UNDER_LINKING) == _TRUE)
+		ulInfo = CHECKINGSTATUS;
+	else if (check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE)
+		ulInfo = ASSOCIATED;
+	else if (check_fwstate(pmlmepriv, WIFI_ADHOC_STATE) == _TRUE)
+		ulInfo = ADHOCMODE;
+	else
+		ulInfo = NOTASSOCIATED ;
+
+	*(ULONG *)poid_par_priv->information_buf = ulInfo;
+	*poid_par_priv->bytes_rw =  poid_par_priv->information_buf_len;
+
+#if 0
+	/* Rearrange the order to let the UI still shows connection when scan is in progress */
+	if (pMgntInfo->mAssoc)
+		ulInfo = 1;
+	else if (pMgntInfo->mIbss)
+		ulInfo = 2;
+	else if (pMgntInfo->bScanInProgress)
+		ulInfo = 0;
+	else
+		ulInfo = 3;
+	ulInfoLen = sizeof(ULONG);
+#endif
+
+	return status;
+}
+
+NDIS_STATUS oid_rt_set_default_key_id_hdl(struct oid_par_priv *poid_par_priv)
+{
+	NDIS_STATUS		status = NDIS_STATUS_SUCCESS;
+	PADAPTER		padapter = (PADAPTER)(poid_par_priv->adapter_context);
+
+	if (poid_par_priv->type_of_oid != SET_OID) {
+		status = NDIS_STATUS_NOT_ACCEPTED;
+		return status;
+	}
+
+	return status;
+}
+/* **************  oid_rtl_seg_03_00 section end **************  */
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/core/rtw_ioctl_set.c linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/core/rtw_ioctl_set.c
--- linux-5.6.3/3rdparty/rtl8821ce/core/rtw_ioctl_set.c	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/core/rtw_ioctl_set.c	2020-04-10 16:35:06.773658060 +0300
@@ -0,0 +1,919 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#define _RTW_IOCTL_SET_C_
+
+#include <drv_types.h>
+#include <hal_data.h>
+
+
+extern void indicate_wx_scan_complete_event(_adapter *padapter);
+
+#define IS_MAC_ADDRESS_BROADCAST(addr) \
+	(\
+	 ((addr[0] == 0xff) && (addr[1] == 0xff) && \
+	  (addr[2] == 0xff) && (addr[3] == 0xff) && \
+	  (addr[4] == 0xff) && (addr[5] == 0xff)) ? _TRUE : _FALSE \
+	)
+
+u8 rtw_validate_bssid(u8 *bssid)
+{
+	u8 ret = _TRUE;
+
+	if (is_zero_mac_addr(bssid)
+	    || is_broadcast_mac_addr(bssid)
+	    || is_multicast_mac_addr(bssid)
+	   )
+		ret = _FALSE;
+
+	return ret;
+}
+
+u8 rtw_validate_ssid(NDIS_802_11_SSID *ssid)
+{
+#ifdef CONFIG_VALIDATE_SSID
+	u8	 i;
+#endif
+	u8	ret = _TRUE;
+
+
+	if (ssid->SsidLength > 32) {
+		ret = _FALSE;
+		goto exit;
+	}
+
+#ifdef CONFIG_VALIDATE_SSID
+	for (i = 0; i < ssid->SsidLength; i++) {
+		/* wifi, printable ascii code must be supported */
+		if (!((ssid->Ssid[i] >= 0x20) && (ssid->Ssid[i] <= 0x7e))) {
+			ret = _FALSE;
+			break;
+		}
+	}
+#endif /* CONFIG_VALIDATE_SSID */
+
+exit:
+
+
+	return ret;
+}
+
+u8 rtw_do_join(_adapter *padapter);
+u8 rtw_do_join(_adapter *padapter)
+{
+	_irqL	irqL;
+	_list	*plist, *phead;
+	u8 *pibss = NULL;
+	struct	mlme_priv	*pmlmepriv = &(padapter->mlmepriv);
+	struct sitesurvey_parm parm;
+	_queue	*queue	= &(pmlmepriv->scanned_queue);
+	u8 ret = _SUCCESS;
+
+
+	_enter_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);
+	phead = get_list_head(queue);
+	plist = get_next(phead);
+
+
+	pmlmepriv->cur_network.join_res = -2;
+
+	set_fwstate(pmlmepriv, _FW_UNDER_LINKING);
+
+	pmlmepriv->pscanned = plist;
+
+	pmlmepriv->to_join = _TRUE;
+
+	rtw_init_sitesurvey_parm(padapter, &parm);
+	_rtw_memcpy(&parm.ssid[0], &pmlmepriv->assoc_ssid, sizeof(NDIS_802_11_SSID));
+	parm.ssid_num = 1;
+
+	if (_rtw_queue_empty(queue) == _TRUE) {
+		_exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);
+		_clr_fwstate_(pmlmepriv, _FW_UNDER_LINKING);
+
+		/* when set_ssid/set_bssid for rtw_do_join(), but scanning queue is empty */
+		/* we try to issue sitesurvey firstly	 */
+
+		if (pmlmepriv->LinkDetectInfo.bBusyTraffic == _FALSE
+		    || rtw_to_roam(padapter) > 0
+		   ) {
+			u8 ssc_chk = rtw_sitesurvey_condition_check(padapter, _FALSE);
+
+			if ((ssc_chk == SS_ALLOW) || (ssc_chk == SS_DENY_BUSY_TRAFFIC) ){
+				/* submit site_survey_cmd */
+				ret = rtw_sitesurvey_cmd(padapter, &parm);
+				if (_SUCCESS != ret)
+					pmlmepriv->to_join = _FALSE;
+			} else {
+				/*if (ssc_chk == SS_DENY_BUDDY_UNDER_SURVEY)*/
+				pmlmepriv->to_join = _FALSE;
+				ret = _FAIL;
+			}
+		} else {
+			pmlmepriv->to_join = _FALSE;
+			ret = _FAIL;
+		}
+
+		goto exit;
+	} else {
+		int select_ret;
+		_exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);
+		select_ret = rtw_select_and_join_from_scanned_queue(pmlmepriv);
+		if (select_ret == _SUCCESS) {
+			pmlmepriv->to_join = _FALSE;
+			_set_timer(&pmlmepriv->assoc_timer, MAX_JOIN_TIMEOUT);
+		} else {
+			if (check_fwstate(pmlmepriv, WIFI_ADHOC_STATE) == _TRUE) {
+				/* submit createbss_cmd to change to a ADHOC_MASTER */
+
+				/* pmlmepriv->lock has been acquired by caller... */
+				WLAN_BSSID_EX    *pdev_network = &(padapter->registrypriv.dev_network);
+
+				/*pmlmepriv->fw_state = WIFI_ADHOC_MASTER_STATE;*/
+				init_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE);
+
+				pibss = padapter->registrypriv.dev_network.MacAddress;
+
+				_rtw_memset(&pdev_network->Ssid, 0, sizeof(NDIS_802_11_SSID));
+				_rtw_memcpy(&pdev_network->Ssid, &pmlmepriv->assoc_ssid, sizeof(NDIS_802_11_SSID));
+
+				rtw_update_registrypriv_dev_network(padapter);
+
+				rtw_generate_random_ibss(pibss);
+
+				if (rtw_create_ibss_cmd(padapter, 0) != _SUCCESS) {
+					ret =  _FALSE;
+					goto exit;
+				}
+
+				pmlmepriv->to_join = _FALSE;
+
+
+			} else {
+				/* can't associate ; reset under-linking			 */
+				_clr_fwstate_(pmlmepriv, _FW_UNDER_LINKING);
+
+				/* when set_ssid/set_bssid for rtw_do_join(), but there are no desired bss in scanning queue */
+				/* we try to issue sitesurvey firstly			 */
+				if (pmlmepriv->LinkDetectInfo.bBusyTraffic == _FALSE
+				    || rtw_to_roam(padapter) > 0
+				   ) {
+					u8 ssc_chk = rtw_sitesurvey_condition_check(padapter, _FALSE);
+
+					if ((ssc_chk == SS_ALLOW) || (ssc_chk == SS_DENY_BUSY_TRAFFIC)){
+						/* RTW_INFO(("rtw_do_join() when   no desired bss in scanning queue\n"); */
+						ret = rtw_sitesurvey_cmd(padapter, &parm);
+						if (_SUCCESS != ret)
+							pmlmepriv->to_join = _FALSE;
+					} else {
+						/*if (ssc_chk == SS_DENY_BUDDY_UNDER_SURVEY) {
+						} else {*/
+						ret = _FAIL;
+						pmlmepriv->to_join = _FALSE;
+					}
+				} else {
+					ret = _FAIL;
+					pmlmepriv->to_join = _FALSE;
+				}
+			}
+
+		}
+
+	}
+
+exit:
+
+	return ret;
+}
+
+#ifdef PLATFORM_WINDOWS
+u8 rtw_pnp_set_power_wakeup(_adapter *padapter)
+{
+	u8 res = _SUCCESS;
+
+
+
+	res = rtw_setstandby_cmd(padapter, 0);
+
+
+
+	return res;
+}
+
+u8 rtw_pnp_set_power_sleep(_adapter *padapter)
+{
+	u8 res = _SUCCESS;
+
+
+	/* DbgPrint("+rtw_pnp_set_power_sleep\n"); */
+
+	res = rtw_setstandby_cmd(padapter, 1);
+
+
+
+	return res;
+}
+
+u8 rtw_set_802_11_reload_defaults(_adapter *padapter, NDIS_802_11_RELOAD_DEFAULTS reloadDefaults)
+{
+
+
+
+	/* SecClearAllKeys(Adapter); */
+	/* 8711 CAM was not for En/Decrypt only */
+	/* so, we can't clear all keys. */
+	/* should we disable WPAcfg (ox0088) bit 1-2, instead of clear all CAM */
+
+	/* TO DO... */
+
+
+	return _TRUE;
+}
+
+u8 set_802_11_test(_adapter *padapter, NDIS_802_11_TEST *test)
+{
+	u8 ret = _TRUE;
+
+
+	switch (test->Type) {
+	case 1:
+		NdisMIndicateStatus(padapter->hndis_adapter, NDIS_STATUS_MEDIA_SPECIFIC_INDICATION, (PVOID)&test->AuthenticationEvent, test->Length - 8);
+		NdisMIndicateStatusComplete(padapter->hndis_adapter);
+		break;
+
+	case 2:
+		NdisMIndicateStatus(padapter->hndis_adapter, NDIS_STATUS_MEDIA_SPECIFIC_INDICATION, (PVOID)&test->RssiTrigger, sizeof(NDIS_802_11_RSSI));
+		NdisMIndicateStatusComplete(padapter->hndis_adapter);
+		break;
+
+	default:
+		ret = _FALSE;
+		break;
+	}
+
+
+	return ret;
+}
+
+u8	rtw_set_802_11_pmkid(_adapter	*padapter, NDIS_802_11_PMKID *pmkid)
+{
+	u8	ret = _SUCCESS;
+
+	return ret;
+}
+
+#endif
+
+u8 rtw_set_802_11_bssid(_adapter *padapter, u8 *bssid)
+{
+	_irqL irqL;
+	u8 status = _SUCCESS;
+
+	struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
+
+
+	RTW_PRINT("set bssid:%pM\n", bssid);
+
+	if ((bssid[0] == 0x00 && bssid[1] == 0x00 && bssid[2] == 0x00 && bssid[3] == 0x00 && bssid[4] == 0x00 && bssid[5] == 0x00) ||
+	    (bssid[0] == 0xFF && bssid[1] == 0xFF && bssid[2] == 0xFF && bssid[3] == 0xFF && bssid[4] == 0xFF && bssid[5] == 0xFF)) {
+		status = _FAIL;
+		goto exit;
+	}
+
+	_enter_critical_bh(&pmlmepriv->lock, &irqL);
+
+
+	RTW_INFO("Set BSSID under fw_state=0x%08x\n", get_fwstate(pmlmepriv));
+	if (check_fwstate(pmlmepriv, _FW_UNDER_SURVEY) == _TRUE)
+		goto handle_tkip_countermeasure;
+	else if (check_fwstate(pmlmepriv, _FW_UNDER_LINKING) == _TRUE)
+		goto release_mlme_lock;
+
+	if (check_fwstate(pmlmepriv, _FW_LINKED | WIFI_ADHOC_MASTER_STATE) == _TRUE) {
+
+		if (_rtw_memcmp(&pmlmepriv->cur_network.network.MacAddress, bssid, ETH_ALEN) == _TRUE) {
+			if (check_fwstate(pmlmepriv, WIFI_STATION_STATE) == _FALSE)
+				goto release_mlme_lock;/* it means driver is in WIFI_ADHOC_MASTER_STATE, we needn't create bss again. */
+		} else {
+
+			rtw_disassoc_cmd(padapter, 0, 0);
+
+			if (check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE)
+				rtw_indicate_disconnect(padapter, 0, _FALSE);
+
+			rtw_free_assoc_resources_cmd(padapter, _TRUE, 0);
+
+			if ((check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE) == _TRUE)) {
+				_clr_fwstate_(pmlmepriv, WIFI_ADHOC_MASTER_STATE);
+				set_fwstate(pmlmepriv, WIFI_ADHOC_STATE);
+			}
+		}
+	}
+
+handle_tkip_countermeasure:
+	if (rtw_handle_tkip_countermeasure(padapter, __func__) == _FAIL) {
+		status = _FAIL;
+		goto release_mlme_lock;
+	}
+
+	_rtw_memset(&pmlmepriv->assoc_ssid, 0, sizeof(NDIS_802_11_SSID));
+	_rtw_memcpy(&pmlmepriv->assoc_bssid, bssid, ETH_ALEN);
+	pmlmepriv->assoc_by_bssid = _TRUE;
+
+	if (check_fwstate(pmlmepriv, _FW_UNDER_SURVEY) == _TRUE)
+		pmlmepriv->to_join = _TRUE;
+	else
+		status = rtw_do_join(padapter);
+
+release_mlme_lock:
+	_exit_critical_bh(&pmlmepriv->lock, &irqL);
+
+exit:
+
+
+	return status;
+}
+
+u8 rtw_set_802_11_ssid(_adapter *padapter, NDIS_802_11_SSID *ssid)
+{
+	_irqL irqL;
+	u8 status = _SUCCESS;
+
+	struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
+	struct wlan_network *pnetwork = &pmlmepriv->cur_network;
+
+
+	RTW_PRINT("set ssid [%s] fw_state=0x%08x\n",
+		  ssid->Ssid, get_fwstate(pmlmepriv));
+
+	if (!rtw_is_hw_init_completed(padapter)) {
+		status = _FAIL;
+		goto exit;
+	}
+
+	_enter_critical_bh(&pmlmepriv->lock, &irqL);
+
+	RTW_INFO("Set SSID under fw_state=0x%08x\n", get_fwstate(pmlmepriv));
+	if (check_fwstate(pmlmepriv, _FW_UNDER_SURVEY) == _TRUE)
+		goto handle_tkip_countermeasure;
+	else if (check_fwstate(pmlmepriv, _FW_UNDER_LINKING) == _TRUE)
+		goto release_mlme_lock;
+
+	if (check_fwstate(pmlmepriv, _FW_LINKED | WIFI_ADHOC_MASTER_STATE) == _TRUE) {
+
+		if ((pmlmepriv->assoc_ssid.SsidLength == ssid->SsidLength) &&
+		    (_rtw_memcmp(&pmlmepriv->assoc_ssid.Ssid, ssid->Ssid, ssid->SsidLength) == _TRUE)) {
+			if ((check_fwstate(pmlmepriv, WIFI_STATION_STATE) == _FALSE)) {
+
+				if (rtw_is_same_ibss(padapter, pnetwork) == _FALSE) {
+					/* if in WIFI_ADHOC_MASTER_STATE | WIFI_ADHOC_STATE, create bss or rejoin again */
+					rtw_disassoc_cmd(padapter, 0, 0);
+
+					if (check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE)
+						rtw_indicate_disconnect(padapter, 0, _FALSE);
+
+					rtw_free_assoc_resources_cmd(padapter, _TRUE, 0);
+
+					if (check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE) == _TRUE) {
+						_clr_fwstate_(pmlmepriv, WIFI_ADHOC_MASTER_STATE);
+						set_fwstate(pmlmepriv, WIFI_ADHOC_STATE);
+					}
+				} else {
+					goto release_mlme_lock;/* it means driver is in WIFI_ADHOC_MASTER_STATE, we needn't create bss again. */
+				}
+			}
+#ifdef CONFIG_LPS
+			else
+				rtw_lps_ctrl_wk_cmd(padapter, LPS_CTRL_JOINBSS, 1);
+#endif
+		} else {
+
+			rtw_disassoc_cmd(padapter, 0, 0);
+
+			if (check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE)
+				rtw_indicate_disconnect(padapter, 0, _FALSE);
+
+			rtw_free_assoc_resources_cmd(padapter, _TRUE, 0);
+
+			if (check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE) == _TRUE) {
+				_clr_fwstate_(pmlmepriv, WIFI_ADHOC_MASTER_STATE);
+				set_fwstate(pmlmepriv, WIFI_ADHOC_STATE);
+			}
+		}
+	}
+
+handle_tkip_countermeasure:
+	if (rtw_handle_tkip_countermeasure(padapter, __func__) == _FAIL) {
+		status = _FAIL;
+		goto release_mlme_lock;
+	}
+
+	if (rtw_validate_ssid(ssid) == _FALSE) {
+		status = _FAIL;
+		goto release_mlme_lock;
+	}
+
+	_rtw_memcpy(&pmlmepriv->assoc_ssid, ssid, sizeof(NDIS_802_11_SSID));
+	pmlmepriv->assoc_by_bssid = _FALSE;
+
+	if (check_fwstate(pmlmepriv, _FW_UNDER_SURVEY) == _TRUE)
+		pmlmepriv->to_join = _TRUE;
+	else
+		status = rtw_do_join(padapter);
+
+release_mlme_lock:
+	_exit_critical_bh(&pmlmepriv->lock, &irqL);
+
+exit:
+
+
+	return status;
+
+}
+
+u8 rtw_set_802_11_connect(_adapter *padapter, u8 *bssid, NDIS_802_11_SSID *ssid)
+{
+	_irqL irqL;
+	u8 status = _SUCCESS;
+	bool bssid_valid = _TRUE;
+	bool ssid_valid = _TRUE;
+	struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
+
+
+	if (!ssid || rtw_validate_ssid(ssid) == _FALSE)
+		ssid_valid = _FALSE;
+
+	if (!bssid || rtw_validate_bssid(bssid) == _FALSE)
+		bssid_valid = _FALSE;
+
+	if (ssid_valid == _FALSE && bssid_valid == _FALSE) {
+		RTW_INFO(FUNC_ADPT_FMT" ssid:%p, ssid_valid:%d, bssid:%p, bssid_valid:%d\n",
+			FUNC_ADPT_ARG(padapter), ssid, ssid_valid, bssid, bssid_valid);
+		status = _FAIL;
+		goto exit;
+	}
+
+	if (!rtw_is_hw_init_completed(padapter)) {
+		status = _FAIL;
+		goto exit;
+	}
+
+	_enter_critical_bh(&pmlmepriv->lock, &irqL);
+
+	RTW_PRINT(FUNC_ADPT_FMT"  fw_state=0x%08x\n",
+		  FUNC_ADPT_ARG(padapter), get_fwstate(pmlmepriv));
+
+	if (check_fwstate(pmlmepriv, _FW_UNDER_SURVEY) == _TRUE)
+		goto handle_tkip_countermeasure;
+	else if (check_fwstate(pmlmepriv, _FW_UNDER_LINKING) == _TRUE)
+		goto release_mlme_lock;
+
+handle_tkip_countermeasure:
+	if (rtw_handle_tkip_countermeasure(padapter, __func__) == _FAIL) {
+		status = _FAIL;
+		goto release_mlme_lock;
+	}
+
+	if (ssid && ssid_valid)
+		_rtw_memcpy(&pmlmepriv->assoc_ssid, ssid, sizeof(NDIS_802_11_SSID));
+	else
+		_rtw_memset(&pmlmepriv->assoc_ssid, 0, sizeof(NDIS_802_11_SSID));
+
+	if (bssid && bssid_valid) {
+		_rtw_memcpy(&pmlmepriv->assoc_bssid, bssid, ETH_ALEN);
+		pmlmepriv->assoc_by_bssid = _TRUE;
+	} else
+		pmlmepriv->assoc_by_bssid = _FALSE;
+
+	if (check_fwstate(pmlmepriv, _FW_UNDER_SURVEY) == _TRUE)
+		pmlmepriv->to_join = _TRUE;
+	else
+		status = rtw_do_join(padapter);
+
+release_mlme_lock:
+	_exit_critical_bh(&pmlmepriv->lock, &irqL);
+
+exit:
+
+
+	return status;
+}
+
+u8 rtw_set_802_11_infrastructure_mode(_adapter *padapter,
+			      NDIS_802_11_NETWORK_INFRASTRUCTURE networktype)
+{
+	_irqL irqL;
+	struct	mlme_priv	*pmlmepriv = &padapter->mlmepriv;
+	struct	wlan_network	*cur_network = &pmlmepriv->cur_network;
+	NDIS_802_11_NETWORK_INFRASTRUCTURE *pold_state = &(cur_network->network.InfrastructureMode);
+	u8 ap2sta_mode = _FALSE;
+	u8 ret = _TRUE;
+
+	if (*pold_state != networktype) {
+		/* RTW_INFO("change mode, old_mode=%d, new_mode=%d, fw_state=0x%x\n", *pold_state, networktype, get_fwstate(pmlmepriv)); */
+
+		if (*pold_state == Ndis802_11APMode
+			|| *pold_state == Ndis802_11_mesh
+		) {
+			/* change to other mode from Ndis802_11APMode/Ndis802_11_mesh */
+			cur_network->join_res = -1;
+			ap2sta_mode = _TRUE;
+#ifdef CONFIG_NATIVEAP_MLME
+			stop_ap_mode(padapter);
+#endif
+		}
+
+		_enter_critical_bh(&pmlmepriv->lock, &irqL);
+
+		if ((check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE) || (*pold_state == Ndis802_11IBSS))
+			rtw_disassoc_cmd(padapter, 0, 0);
+
+		if ((check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE) ||
+		    (check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE) == _TRUE))
+			rtw_free_assoc_resources_cmd(padapter, _TRUE, 0);
+
+		if ((*pold_state == Ndis802_11Infrastructure) || (*pold_state == Ndis802_11IBSS)) {
+			if (check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE) {
+				rtw_indicate_disconnect(padapter, 0, _FALSE); /*will clr Linked_state; before this function, we must have checked whether issue dis-assoc_cmd or not*/
+			}
+		}
+
+		*pold_state = networktype;
+
+		_clr_fwstate_(pmlmepriv, ~WIFI_NULL_STATE);
+
+		switch (networktype) {
+		case Ndis802_11IBSS:
+			set_fwstate(pmlmepriv, WIFI_ADHOC_STATE);
+			break;
+
+		case Ndis802_11Infrastructure:
+			set_fwstate(pmlmepriv, WIFI_STATION_STATE);
+
+			if (ap2sta_mode)
+				rtw_init_bcmc_stainfo(padapter);
+			break;
+
+		case Ndis802_11APMode:
+			set_fwstate(pmlmepriv, WIFI_AP_STATE);
+#ifdef CONFIG_NATIVEAP_MLME
+			start_ap_mode(padapter);
+			/* rtw_indicate_connect(padapter); */
+#endif
+
+			break;
+
+#ifdef CONFIG_RTW_MESH
+		case Ndis802_11_mesh:
+			set_fwstate(pmlmepriv, WIFI_MESH_STATE);
+			start_ap_mode(padapter);
+			break;
+#endif
+
+		case Ndis802_11AutoUnknown:
+		case Ndis802_11InfrastructureMax:
+			break;
+		case Ndis802_11Monitor:
+			set_fwstate(pmlmepriv, WIFI_MONITOR_STATE);
+			break;
+		default:
+			ret = _FALSE;
+			rtw_warn_on(1);
+		}
+
+		/* SecClearAllKeys(adapter); */
+
+
+		_exit_critical_bh(&pmlmepriv->lock, &irqL);
+	}
+
+	return ret;
+}
+
+
+u8 rtw_set_802_11_disassociate(_adapter *padapter)
+{
+	_irqL irqL;
+	struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
+
+
+	_enter_critical_bh(&pmlmepriv->lock, &irqL);
+
+	if (check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE) {
+
+		rtw_disassoc_cmd(padapter, 0, 0);
+		rtw_indicate_disconnect(padapter, 0, _FALSE);
+		/* modify for CONFIG_IEEE80211W, none 11w can use it */
+		rtw_free_assoc_resources_cmd(padapter, _TRUE, 0);
+		if (_FAIL == rtw_pwr_wakeup(padapter))
+			RTW_INFO("%s(): rtw_pwr_wakeup fail !!!\n", __FUNCTION__);
+	}
+
+	_exit_critical_bh(&pmlmepriv->lock, &irqL);
+
+
+	return _TRUE;
+}
+
+#if 1
+u8 rtw_set_802_11_bssid_list_scan(_adapter *padapter, struct sitesurvey_parm *pparm)
+{
+	_irqL	irqL;
+	struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
+	u8	res = _TRUE;
+
+	_enter_critical_bh(&pmlmepriv->lock, &irqL);
+	res = rtw_sitesurvey_cmd(padapter, pparm);
+	_exit_critical_bh(&pmlmepriv->lock, &irqL);
+
+	return res;
+}
+
+#else
+u8 rtw_set_802_11_bssid_list_scan(_adapter *padapter, struct sitesurvey_parm *pparm)
+{
+	_irqL	irqL;
+	struct	mlme_priv		*pmlmepriv = &padapter->mlmepriv;
+	u8	res = _TRUE;
+
+
+
+	if (padapter == NULL) {
+		res = _FALSE;
+		goto exit;
+	}
+	if (!rtw_is_hw_init_completed(padapter)) {
+		res = _FALSE;
+		goto exit;
+	}
+
+	if ((check_fwstate(pmlmepriv, _FW_UNDER_SURVEY | _FW_UNDER_LINKING) == _TRUE) ||
+	    (pmlmepriv->LinkDetectInfo.bBusyTraffic == _TRUE)) {
+		/* Scan or linking is in progress, do nothing. */
+		res = _TRUE;
+
+
+	} else {
+		if (rtw_is_scan_deny(padapter)) {
+			RTW_INFO(FUNC_ADPT_FMT": scan deny\n", FUNC_ADPT_ARG(padapter));
+			indicate_wx_scan_complete_event(padapter);
+			return _SUCCESS;
+		}
+
+		_enter_critical_bh(&pmlmepriv->lock, &irqL);
+
+		res = rtw_sitesurvey_cmd(padapter, pparm);
+
+		_exit_critical_bh(&pmlmepriv->lock, &irqL);
+	}
+exit:
+
+
+	return res;
+}
+#endif
+u8 rtw_set_802_11_authentication_mode(_adapter *padapter, NDIS_802_11_AUTHENTICATION_MODE authmode)
+{
+	struct security_priv *psecuritypriv = &padapter->securitypriv;
+	int res;
+	u8 ret;
+
+
+
+	psecuritypriv->ndisauthtype = authmode;
+
+
+	if (psecuritypriv->ndisauthtype > 3)
+		psecuritypriv->dot11AuthAlgrthm = dot11AuthAlgrthm_8021X;
+
+#ifdef CONFIG_WAPI_SUPPORT
+	if (psecuritypriv->ndisauthtype == 6)
+		psecuritypriv->dot11AuthAlgrthm = dot11AuthAlgrthm_WAPI;
+#endif
+
+	res = rtw_set_auth(padapter, psecuritypriv);
+
+	if (res == _SUCCESS)
+		ret = _TRUE;
+	else
+		ret = _FALSE;
+
+
+	return ret;
+}
+
+u8 rtw_set_802_11_add_wep(_adapter *padapter, NDIS_802_11_WEP *wep)
+{
+
+	u8		bdefaultkey;
+	u8		btransmitkey;
+	sint		keyid, res;
+	struct security_priv *psecuritypriv = &(padapter->securitypriv);
+	u8		ret = _SUCCESS;
+
+
+	bdefaultkey = (wep->KeyIndex & 0x40000000) > 0 ? _FALSE : _TRUE; /* for ??? */
+	btransmitkey = (wep->KeyIndex & 0x80000000) > 0 ? _TRUE  : _FALSE;	/* for ??? */
+	keyid = wep->KeyIndex & 0x3fffffff;
+
+	if (keyid >= 4) {
+		ret = _FALSE;
+		goto exit;
+	}
+
+	switch (wep->KeyLength) {
+	case 5:
+		psecuritypriv->dot11PrivacyAlgrthm = _WEP40_;
+		break;
+	case 13:
+		psecuritypriv->dot11PrivacyAlgrthm = _WEP104_;
+		break;
+	default:
+		psecuritypriv->dot11PrivacyAlgrthm = _NO_PRIVACY_;
+		break;
+	}
+
+
+	_rtw_memcpy(&(psecuritypriv->dot11DefKey[keyid].skey[0]), &(wep->KeyMaterial), wep->KeyLength);
+
+	psecuritypriv->dot11DefKeylen[keyid] = wep->KeyLength;
+
+	psecuritypriv->dot11PrivacyKeyIndex = keyid;
+
+
+	res = rtw_set_key(padapter, psecuritypriv, keyid, 1, _TRUE);
+
+	if (res == _FAIL)
+		ret = _FALSE;
+exit:
+
+
+	return ret;
+
+}
+
+/*
+* rtw_get_cur_max_rate -
+* @adapter: pointer to _adapter structure
+*
+* Return 0 or 100Kbps
+*/
+u16 rtw_get_cur_max_rate(_adapter *adapter)
+{
+	int j;
+	int	i = 0;
+	u16	rate = 0, max_rate = 0;
+	struct mlme_priv	*pmlmepriv = &adapter->mlmepriv;
+	WLAN_BSSID_EX	*pcur_bss = &pmlmepriv->cur_network.network;
+	int	sta_bssrate_len = 0;
+	unsigned char	sta_bssrate[NumRates];
+	struct sta_info *psta = NULL;
+	u8	short_GI = 0;
+#ifdef CONFIG_80211N_HT
+	u8	rf_type = 0;
+#endif
+
+#ifdef CONFIG_MP_INCLUDED
+	if (adapter->registrypriv.mp_mode == 1) {
+		if (check_fwstate(pmlmepriv, WIFI_MP_STATE) == _TRUE)
+			return 0;
+	}
+#endif
+
+	if ((check_fwstate(pmlmepriv, _FW_LINKED) != _TRUE)
+	    && (check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE) != _TRUE))
+		return 0;
+
+	psta = rtw_get_stainfo(&adapter->stapriv, get_bssid(pmlmepriv));
+	if (psta == NULL)
+		return 0;
+
+	short_GI = query_ra_short_GI(psta, rtw_get_tx_bw_mode(adapter, psta));
+
+#ifdef CONFIG_80211N_HT
+	if (is_supported_ht(psta->wireless_mode)) {
+		rtw_hal_get_hwreg(adapter, HW_VAR_RF_TYPE, (u8 *)(&rf_type));
+		max_rate = rtw_mcs_rate(rf_type
+			, (psta->cmn.bw_mode == CHANNEL_WIDTH_40) ? 1 : 0
+			, short_GI
+			, psta->htpriv.ht_cap.supp_mcs_set
+		);
+	}
+#ifdef CONFIG_80211AC_VHT
+	else if (is_supported_vht(psta->wireless_mode))
+		max_rate = ((rtw_vht_mcs_to_data_rate(psta->cmn.bw_mode, short_GI, pmlmepriv->vhtpriv.vht_highest_rate) + 1) >> 1) * 10;
+#endif /* CONFIG_80211AC_VHT */
+	else
+#endif /* CONFIG_80211N_HT */
+	{
+		/*station mode show :station && ap support rate; softap :show ap support rate*/	
+		if (check_fwstate(pmlmepriv, WIFI_STATION_STATE) == _TRUE)
+			get_rate_set(adapter, sta_bssrate, &sta_bssrate_len);/*get sta rate and length*/
+
+
+		while ((pcur_bss->SupportedRates[i] != 0) && (pcur_bss->SupportedRates[i] != 0xFF)) {
+			rate = pcur_bss->SupportedRates[i] & 0x7F;/*AP support rates*/
+			/*RTW_INFO("%s rate=%02X \n", __func__, rate);*/
+
+			/*check STA  support rate or not */
+			if (check_fwstate(pmlmepriv, WIFI_STATION_STATE) == _TRUE) {
+				for (j = 0; j < sta_bssrate_len; j++) {
+					/* Avoid the proprietary data rate (22Mbps) of Handlink WSG-4000 AP */
+					if ((rate | IEEE80211_BASIC_RATE_MASK)
+					    == (sta_bssrate[j] | IEEE80211_BASIC_RATE_MASK)) {
+						if (rate > max_rate) {
+							max_rate = rate;
+						}
+						break;
+					}
+				}
+			} else {
+			
+				if (rate > max_rate)
+					max_rate = rate;
+
+			}
+			i++;
+		}
+
+		max_rate = max_rate * 10 / 2;
+	}
+	return max_rate;
+}
+
+/*
+* rtw_set_scan_mode -
+* @adapter: pointer to _adapter structure
+* @scan_mode:
+*
+* Return _SUCCESS or _FAIL
+*/
+int rtw_set_scan_mode(_adapter *adapter, RT_SCAN_TYPE scan_mode)
+{
+	if (scan_mode != SCAN_ACTIVE && scan_mode != SCAN_PASSIVE)
+		return _FAIL;
+
+	adapter->mlmepriv.scan_mode = scan_mode;
+
+	return _SUCCESS;
+}
+
+/*
+* rtw_set_channel_plan -
+* @adapter: pointer to _adapter structure
+* @channel_plan:
+*
+* Return _SUCCESS or _FAIL
+*/
+int rtw_set_channel_plan(_adapter *adapter, u8 channel_plan)
+{
+	/* handle by cmd_thread to sync with scan operation */
+	return rtw_set_chplan_cmd(adapter, RTW_CMDF_WAIT_ACK, channel_plan, 1);
+}
+
+/*
+* rtw_set_country -
+* @adapter: pointer to _adapter structure
+* @country_code: string of country code
+*
+* Return _SUCCESS or _FAIL
+*/
+int rtw_set_country(_adapter *adapter, const char *country_code)
+{
+#ifdef CONFIG_RTW_IOCTL_SET_COUNTRY
+	return rtw_set_country_cmd(adapter, RTW_CMDF_WAIT_ACK, country_code, 1);
+#else
+	RTW_INFO("%s(): not applied\n", __func__);
+	return _SUCCESS;
+#endif
+}
+
+/*
+* rtw_set_band -
+* @adapter: pointer to _adapter structure
+* @band: band to set
+*
+* Return _SUCCESS or _FAIL
+*/
+int rtw_set_band(_adapter *adapter, u8 band)
+{
+	if (rtw_band_valid(band)) {
+		RTW_INFO(FUNC_ADPT_FMT" band:%d\n", FUNC_ADPT_ARG(adapter), band);
+		adapter->setband = band;
+		return _SUCCESS;
+	}
+
+	RTW_PRINT(FUNC_ADPT_FMT" band:%d fail\n", FUNC_ADPT_ARG(adapter), band);
+	return _FAIL;
+}
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/core/rtw_iol.c linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/core/rtw_iol.c
--- linux-5.6.3/3rdparty/rtl8821ce/core/rtw_iol.c	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/core/rtw_iol.c	2020-04-10 16:35:06.773658060 +0300
@@ -0,0 +1,394 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+
+#include <drv_types.h>
+
+#ifdef CONFIG_IOL
+struct xmit_frame	*rtw_IOL_accquire_xmit_frame(ADAPTER *adapter)
+{
+	struct xmit_frame	*xmit_frame;
+	struct xmit_buf	*xmitbuf;
+	struct pkt_attrib	*pattrib;
+	struct xmit_priv	*pxmitpriv = &(adapter->xmitpriv);
+
+#if 1
+	xmit_frame = rtw_alloc_xmitframe(pxmitpriv);
+	if (xmit_frame == NULL) {
+		RTW_INFO("%s rtw_alloc_xmitframe return null\n", __FUNCTION__);
+		goto exit;
+	}
+
+	xmitbuf = rtw_alloc_xmitbuf(pxmitpriv);
+	if (xmitbuf == NULL) {
+		RTW_INFO("%s rtw_alloc_xmitbuf return null\n", __FUNCTION__);
+		rtw_free_xmitframe(pxmitpriv, xmit_frame);
+		xmit_frame = NULL;
+		goto exit;
+	}
+
+	xmit_frame->frame_tag = MGNT_FRAMETAG;
+	xmit_frame->pxmitbuf = xmitbuf;
+	xmit_frame->buf_addr = xmitbuf->pbuf;
+	xmitbuf->priv_data = xmit_frame;
+
+	pattrib = &xmit_frame->attrib;
+	update_mgntframe_attrib(adapter, pattrib);
+	pattrib->qsel = QSLT_BEACON;/* Beacon	 */
+	pattrib->subtype = WIFI_BEACON;
+	pattrib->pktlen = pattrib->last_txcmdsz = 0;
+
+#else
+	xmit_frame = alloc_mgtxmitframe(pxmitpriv);
+	if (xmit_frame == NULL)
+		RTW_INFO("%s alloc_mgtxmitframe return null\n", __FUNCTION__);
+	else {
+		pattrib = &xmit_frame->attrib;
+		update_mgntframe_attrib(adapter, pattrib);
+		pattrib->qsel = QSLT_BEACON;
+		pattrib->pktlen = pattrib->last_txcmdsz = 0;
+	}
+#endif
+
+exit:
+	return xmit_frame;
+}
+
+
+int rtw_IOL_append_cmds(struct xmit_frame *xmit_frame, u8 *IOL_cmds, u32 cmd_len)
+{
+	struct pkt_attrib	*pattrib = &xmit_frame->attrib;
+	u16 buf_offset;
+	u32 ori_len;
+
+	buf_offset = TXDESC_OFFSET;
+	ori_len = buf_offset + pattrib->pktlen;
+
+	/* check if the io_buf can accommodate new cmds */
+	if (ori_len + cmd_len + 8 > MAX_XMITBUF_SZ) {
+		RTW_INFO("%s %u is large than MAX_XMITBUF_SZ:%u, can't accommodate new cmds\n", __FUNCTION__
+			 , ori_len + cmd_len + 8, MAX_XMITBUF_SZ);
+		return _FAIL;
+	}
+
+	_rtw_memcpy(xmit_frame->buf_addr + buf_offset + pattrib->pktlen, IOL_cmds, cmd_len);
+	pattrib->pktlen += cmd_len;
+	pattrib->last_txcmdsz += cmd_len;
+
+	/* RTW_INFO("%s ori:%u + cmd_len:%u = %u\n", __FUNCTION__, ori_len, cmd_len, buf_offset+pattrib->pktlen); */
+
+	return _SUCCESS;
+}
+
+bool rtw_IOL_applied(ADAPTER *adapter)
+{
+	if (1 == adapter->registrypriv.fw_iol)
+		return _TRUE;
+
+#ifdef CONFIG_USB_HCI
+	if ((2 == adapter->registrypriv.fw_iol) && (IS_FULL_SPEED_USB(adapter)))
+		return _TRUE;
+#endif
+
+	return _FALSE;
+}
+
+int rtw_IOL_exec_cmds_sync(ADAPTER *adapter, struct xmit_frame *xmit_frame, u32 max_wating_ms, u32 bndy_cnt)
+{
+	return rtw_hal_iol_cmd(adapter, xmit_frame, max_wating_ms, bndy_cnt);
+}
+
+#ifdef CONFIG_IOL_NEW_GENERATION
+int rtw_IOL_append_LLT_cmd(struct xmit_frame *xmit_frame, u8 page_boundary)
+{
+	return _SUCCESS;
+}
+int _rtw_IOL_append_WB_cmd(struct xmit_frame *xmit_frame, u16 addr, u8 value, u8 mask)
+{
+	struct ioreg_cfg cmd = {8, IOREG_CMD_WB_REG, 0x0, 0x0, 0x0};
+
+	/* RTW_PUT_LE16((u8*)&cmd.address, addr);	 */
+	/* RTW_PUT_LE32((u8*)&cmd.value, (u32)value);	 */
+	cmd.address = cpu_to_le16(addr);
+	cmd.data = cpu_to_le32(value);
+
+	if (mask != 0xFF) {
+		cmd.length = 12;
+		/* RTW_PUT_LE32((u8*)&cmd.mask, (u32)mask);	 */
+		cmd.mask = cpu_to_le32(mask);
+	}
+
+	/* RTW_INFO("%s addr:0x%04x,value:0x%08x,mask:0x%08x\n", __FUNCTION__, addr,value,mask); */
+
+	return rtw_IOL_append_cmds(xmit_frame, (u8 *)&cmd, cmd.length);
+
+}
+int _rtw_IOL_append_WW_cmd(struct xmit_frame *xmit_frame, u16 addr, u16 value, u16 mask)
+{
+	struct ioreg_cfg cmd = {8, IOREG_CMD_WW_REG, 0x0, 0x0, 0x0};
+
+	/* RTW_PUT_LE16((u8*)&cmd.address, addr);	 */
+	/* RTW_PUT_LE32((u8*)&cmd.value, (u32)value);	 */
+	cmd.address = cpu_to_le16(addr);
+	cmd.data = cpu_to_le32(value);
+
+	if (mask != 0xFFFF) {
+		cmd.length = 12;
+		/* RTW_PUT_LE32((u8*)&cmd.mask, (u32)mask);	 */
+		cmd.mask =  cpu_to_le32(mask);
+	}
+
+	/* RTW_INFO("%s addr:0x%04x,value:0x%08x,mask:0x%08x\n", __FUNCTION__, addr,value,mask); */
+
+	return rtw_IOL_append_cmds(xmit_frame, (u8 *)&cmd, cmd.length);
+
+}
+int _rtw_IOL_append_WD_cmd(struct xmit_frame *xmit_frame, u16 addr, u32 value, u32 mask)
+{
+	struct ioreg_cfg cmd = {8, IOREG_CMD_WD_REG, 0x0, 0x0, 0x0};
+
+	/* RTW_PUT_LE16((u8*)&cmd.address, addr);	 */
+	/* RTW_PUT_LE32((u8*)&cmd.value, (u32)value);	 */
+	cmd.address = cpu_to_le16(addr);
+	cmd.data = cpu_to_le32(value);
+
+	if (mask != 0xFFFFFFFF) {
+		cmd.length = 12;
+		/* RTW_PUT_LE32((u8*)&cmd.mask, (u32)mask);	 */
+		cmd.mask =  cpu_to_le32(mask);
+	}
+
+	/* RTW_INFO("%s addr:0x%04x,value:0x%08x,mask:0x%08x\n", __FU2NCTION__, addr,value,mask); */
+
+	return rtw_IOL_append_cmds(xmit_frame, (u8 *)&cmd, cmd.length);
+
+}
+
+int _rtw_IOL_append_WRF_cmd(struct xmit_frame *xmit_frame, u8 rf_path, u16 addr, u32 value, u32 mask)
+{
+	struct ioreg_cfg cmd = {8, IOREG_CMD_W_RF, 0x0, 0x0, 0x0};
+
+	/* RTW_PUT_LE16((u8*)&cmd.address, addr);	 */
+	/* RTW_PUT_LE32((u8*)&cmd.value, (u32)value);	 */
+	cmd.address = (rf_path << 8) | ((addr) & 0xFF);
+	cmd.data = cpu_to_le32(value);
+
+	if (mask != 0x000FFFFF) {
+		cmd.length = 12;
+		/* RTW_PUT_LE32((u8*)&cmd.mask, (u32)mask);	 */
+		cmd.mask =  cpu_to_le32(mask);
+	}
+
+	/* RTW_INFO("%s rf_path:0x%02x addr:0x%04x,value:0x%08x,mask:0x%08x\n", __FU2NCTION__,rf_path, addr,value,mask); */
+
+	return rtw_IOL_append_cmds(xmit_frame, (u8 *)&cmd, cmd.length);
+
+}
+
+
+
+int rtw_IOL_append_DELAY_US_cmd(struct xmit_frame *xmit_frame, u16 us)
+{
+	struct ioreg_cfg cmd = {4, IOREG_CMD_DELAY_US, 0x0, 0x0, 0x0};
+	/* RTW_PUT_LE16((u8*)&cmd.address, us);	 */
+	cmd.address = cpu_to_le16(us);
+
+	/* RTW_INFO("%s %u\n", __FUNCTION__, us); */
+	return rtw_IOL_append_cmds(xmit_frame, (u8 *)&cmd, 4);
+}
+
+int rtw_IOL_append_DELAY_MS_cmd(struct xmit_frame *xmit_frame, u16 ms)
+{
+	struct ioreg_cfg cmd = {4, IOREG_CMD_DELAY_US, 0x0, 0x0, 0x0};
+
+	/* RTW_PUT_LE16((u8*)&cmd.address, ms);	 */
+	cmd.address = cpu_to_le16(ms);
+
+	/* RTW_INFO("%s %u\n", __FUNCTION__, ms); */
+	return rtw_IOL_append_cmds(xmit_frame, (u8 *)&cmd, 4);
+}
+int rtw_IOL_append_END_cmd(struct xmit_frame *xmit_frame)
+{
+	struct ioreg_cfg cmd = {4, IOREG_CMD_END, 0xFFFF, 0xFF, 0x0};
+	return rtw_IOL_append_cmds(xmit_frame, (u8 *)&cmd, 4);
+
+}
+
+u8 rtw_IOL_cmd_boundary_handle(struct xmit_frame *pxmit_frame)
+{
+	u8 is_cmd_bndy = _FALSE;
+	if (((pxmit_frame->attrib.pktlen + 32) % 256) + 8 >= 256) {
+		rtw_IOL_append_END_cmd(pxmit_frame);
+		pxmit_frame->attrib.pktlen = ((((pxmit_frame->attrib.pktlen + 32) / 256) + 1) * 256);
+
+		/* printk("==> %s, pktlen(%d)\n",__FUNCTION__,pxmit_frame->attrib.pktlen); */
+		pxmit_frame->attrib.last_txcmdsz = pxmit_frame->attrib.pktlen;
+		is_cmd_bndy = _TRUE;
+	}
+	return is_cmd_bndy;
+}
+
+void rtw_IOL_cmd_buf_dump(ADAPTER *Adapter, int buf_len, u8 *pbuf)
+{
+	int i;
+	int j = 1;
+
+	printk("###### %s ######\n", __FUNCTION__);
+	for (i = 0; i < buf_len; i++) {
+		printk("%02x-", *(pbuf + i));
+
+		if (j % 32 == 0)
+			printk("\n");
+		j++;
+	}
+	printk("\n");
+	printk("============= ioreg_cmd len = %d ===============\n", buf_len);
+}
+
+
+#else /* CONFIG_IOL_NEW_GENERATION */
+int rtw_IOL_append_LLT_cmd(struct xmit_frame *xmit_frame, u8 page_boundary)
+{
+	IOL_CMD cmd = {0x0, IOL_CMD_LLT, 0x0, 0x0};
+
+	RTW_PUT_BE32((u8 *)&cmd.value, (u32)page_boundary);
+
+	return rtw_IOL_append_cmds(xmit_frame, (u8 *)&cmd, 8);
+}
+
+int _rtw_IOL_append_WB_cmd(struct xmit_frame *xmit_frame, u16 addr, u8 value)
+{
+	IOL_CMD cmd = {0x0, IOL_CMD_WB_REG, 0x0, 0x0};
+
+	RTW_PUT_BE16((u8 *)&cmd.address, (u16)addr);
+	RTW_PUT_BE32((u8 *)&cmd.value, (u32)value);
+
+	return rtw_IOL_append_cmds(xmit_frame, (u8 *)&cmd, 8);
+}
+
+int _rtw_IOL_append_WW_cmd(struct xmit_frame *xmit_frame, u16 addr, u16 value)
+{
+	IOL_CMD cmd = {0x0, IOL_CMD_WW_REG, 0x0, 0x0};
+
+	RTW_PUT_BE16((u8 *)&cmd.address, (u16)addr);
+	RTW_PUT_BE32((u8 *)&cmd.value, (u32)value);
+
+	return rtw_IOL_append_cmds(xmit_frame, (u8 *)&cmd, 8);
+}
+
+int _rtw_IOL_append_WD_cmd(struct xmit_frame *xmit_frame, u16 addr, u32 value)
+{
+	IOL_CMD cmd = {0x0, IOL_CMD_WD_REG, 0x0, 0x0};
+	u8 *pos = (u8 *)&cmd;
+
+	RTW_PUT_BE16((u8 *)&cmd.address, (u16)addr);
+	RTW_PUT_BE32((u8 *)&cmd.value, (u32)value);
+
+	return rtw_IOL_append_cmds(xmit_frame, (u8 *)&cmd, 8);
+}
+
+#ifdef DBG_IO
+int dbg_rtw_IOL_append_WB_cmd(struct xmit_frame *xmit_frame, u16 addr, u8 value, const char *caller, const int line)
+{
+	const struct rtw_io_sniff_ent *ent = match_write_sniff(xmit_frame->padapter, addr, 1, value);
+
+	if (ent) {
+		RTW_INFO("DBG_IO %s:%d IOL_WB(0x%04x, 0x%02x) %s\n"
+			, caller, line, addr, value, rtw_io_sniff_ent_get_tag(ent));
+	}
+
+	return _rtw_IOL_append_WB_cmd(xmit_frame, addr, value);
+}
+
+int dbg_rtw_IOL_append_WW_cmd(struct xmit_frame *xmit_frame, u16 addr, u16 value, const char *caller, const int line)
+{
+	const struct rtw_io_sniff_ent *ent = match_write_sniff(xmit_frame->padapter, addr, 2, value);
+
+	if (ent) {
+		RTW_INFO("DBG_IO %s:%d IOL_WW(0x%04x, 0x%04x) %s\n"
+			, caller, line, addr, value, rtw_io_sniff_ent_get_tag(ent));
+	}
+
+	return _rtw_IOL_append_WW_cmd(xmit_frame, addr, value);
+}
+
+int dbg_rtw_IOL_append_WD_cmd(struct xmit_frame *xmit_frame, u16 addr, u32 value, const char *caller, const int line)
+{
+	const struct rtw_io_sniff_ent *ent = match_write_sniff(xmit_frame->padapter, addr, 4, value);
+
+	if (ent) {
+		RTW_INFO("DBG_IO %s:%d IOL_WD(0x%04x, 0x%08x) %s\n"
+			, caller, line, addr, value, rtw_io_sniff_ent_get_tag(ent));
+	}
+
+	return _rtw_IOL_append_WD_cmd(xmit_frame, addr, value);
+}
+#endif
+
+int rtw_IOL_append_DELAY_US_cmd(struct xmit_frame *xmit_frame, u16 us)
+{
+	IOL_CMD cmd = {0x0, IOL_CMD_DELAY_US, 0x0, 0x0};
+
+	RTW_PUT_BE32((u8 *)&cmd.value, (u32)us);
+
+	/* RTW_INFO("%s %u\n", __FUNCTION__, us); */
+
+	return rtw_IOL_append_cmds(xmit_frame, (u8 *)&cmd, 8);
+}
+
+int rtw_IOL_append_DELAY_MS_cmd(struct xmit_frame *xmit_frame, u16 ms)
+{
+	IOL_CMD cmd = {0x0, IOL_CMD_DELAY_MS, 0x0, 0x0};
+
+	RTW_PUT_BE32((u8 *)&cmd.value, (u32)ms);
+
+	/* RTW_INFO("%s %u\n", __FUNCTION__, ms); */
+
+	return rtw_IOL_append_cmds(xmit_frame, (u8 *)&cmd, 8);
+}
+
+int rtw_IOL_append_END_cmd(struct xmit_frame *xmit_frame)
+{
+	IOL_CMD end_cmd = {0x0, IOL_CMD_END, 0x0, 0x0};
+
+
+	return rtw_IOL_append_cmds(xmit_frame, (u8 *)&end_cmd, 8);
+
+}
+
+int rtw_IOL_exec_cmd_array_sync(PADAPTER adapter, u8 *IOL_cmds, u32 cmd_num, u32 max_wating_ms)
+{
+	struct xmit_frame	*xmit_frame;
+
+	xmit_frame = rtw_IOL_accquire_xmit_frame(adapter);
+	if (xmit_frame == NULL)
+		return _FAIL;
+
+	if (rtw_IOL_append_cmds(xmit_frame, IOL_cmds, cmd_num << 3) == _FAIL)
+		return _FAIL;
+
+	return rtw_IOL_exec_cmds_sync(adapter, xmit_frame, max_wating_ms, 0);
+}
+
+int rtw_IOL_exec_empty_cmds_sync(ADAPTER *adapter, u32 max_wating_ms)
+{
+	IOL_CMD end_cmd = {0x0, IOL_CMD_END, 0x0, 0x0};
+	return rtw_IOL_exec_cmd_array_sync(adapter, (u8 *)&end_cmd, 1, max_wating_ms);
+}
+#endif /* CONFIG_IOL_NEW_GENERATION */
+
+
+
+
+#endif /* CONFIG_IOL */
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/core/rtw_mem.c linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/core/rtw_mem.c
--- linux-5.6.3/3rdparty/rtl8821ce/core/rtw_mem.c	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/core/rtw_mem.c	2020-04-10 16:35:06.773658060 +0300
@@ -0,0 +1,128 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2016 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+
+#include <drv_types.h>
+#include <rtw_mem.h>
+
+MODULE_LICENSE("GPL");
+MODULE_DESCRIPTION("Realtek Wireless Lan Driver");
+MODULE_AUTHOR("Realtek Semiconductor Corp.");
+MODULE_VERSION("DRIVERVERSION");
+
+struct sk_buff_head rtk_skb_mem_q;
+struct u8 *rtk_buf_mem[NR_RECVBUFF];
+
+struct u8	*rtw_get_buf_premem(int index)
+{
+	printk("%s, rtk_buf_mem index : %d\n", __func__, index);
+	return rtk_buf_mem[index];
+}
+
+u16 rtw_rtkm_get_buff_size(void)
+{
+	return MAX_RTKM_RECVBUF_SZ;
+}
+EXPORT_SYMBOL(rtw_rtkm_get_buff_size);
+
+u8 rtw_rtkm_get_nr_recv_skb(void)
+{
+	return MAX_RTKM_NR_PREALLOC_RECV_SKB;
+}
+EXPORT_SYMBOL(rtw_rtkm_get_nr_recv_skb);
+
+struct sk_buff *rtw_alloc_skb_premem(u16 in_size)
+{
+	struct sk_buff *skb = NULL;
+
+	if (in_size > MAX_RTKM_RECVBUF_SZ) {
+		pr_info("warning %s: driver buffer size(%d) > rtkm buffer size(%d)\n", __func__, in_size, MAX_RTKM_RECVBUF_SZ);
+		WARN_ON(1);
+		return skb;
+	}
+
+	skb = skb_dequeue(&rtk_skb_mem_q);
+
+	printk("%s, rtk_skb_mem_q len : %d\n", __func__, skb_queue_len(&rtk_skb_mem_q));
+
+	return skb;
+}
+EXPORT_SYMBOL(rtw_alloc_skb_premem);
+
+int rtw_free_skb_premem(struct sk_buff *pskb)
+{
+	if (!pskb)
+		return -1;
+
+	if (skb_queue_len(&rtk_skb_mem_q) >= MAX_RTKM_NR_PREALLOC_RECV_SKB)
+		return -1;
+
+	skb_queue_tail(&rtk_skb_mem_q, pskb);
+
+	printk("%s, rtk_skb_mem_q len : %d\n", __func__, skb_queue_len(&rtk_skb_mem_q));
+
+	return 0;
+}
+EXPORT_SYMBOL(rtw_free_skb_premem);
+
+static int __init rtw_mem_init(void)
+{
+	int i;
+	SIZE_PTR tmpaddr = 0;
+	SIZE_PTR alignment = 0;
+	struct sk_buff *pskb = NULL;
+
+	printk("%s\n", __func__);
+	pr_info("MAX_RTKM_NR_PREALLOC_RECV_SKB: %d\n", MAX_RTKM_NR_PREALLOC_RECV_SKB);
+	pr_info("MAX_RTKM_RECVBUF_SZ: %d\n", MAX_RTKM_RECVBUF_SZ);
+
+#ifdef CONFIG_USE_USB_BUFFER_ALLOC_RX
+	for (i = 0; i < NR_RECVBUFF; i++)
+		rtk_buf_mem[i] = usb_buffer_alloc(dev, size, (in_interrupt() ? GFP_ATOMIC : GFP_KERNEL), dma);
+#endif /* CONFIG_USE_USB_BUFFER_ALLOC_RX */
+
+	skb_queue_head_init(&rtk_skb_mem_q);
+
+	for (i = 0; i < MAX_RTKM_NR_PREALLOC_RECV_SKB; i++) {
+		pskb = __dev_alloc_skb(MAX_RTKM_RECVBUF_SZ + RECVBUFF_ALIGN_SZ, in_interrupt() ? GFP_ATOMIC : GFP_KERNEL);
+		if (pskb) {
+			tmpaddr = (SIZE_PTR)pskb->data;
+			alignment = tmpaddr & (RECVBUFF_ALIGN_SZ - 1);
+			skb_reserve(pskb, (RECVBUFF_ALIGN_SZ - alignment));
+
+			skb_queue_tail(&rtk_skb_mem_q, pskb);
+		} else
+			printk("%s, alloc skb memory fail!\n", __func__);
+
+		pskb = NULL;
+	}
+
+	printk("%s, rtk_skb_mem_q len : %d\n", __func__, skb_queue_len(&rtk_skb_mem_q));
+
+	return 0;
+
+}
+
+static void __exit rtw_mem_exit(void)
+{
+	if (skb_queue_len(&rtk_skb_mem_q))
+		printk("%s, rtk_skb_mem_q len : %d\n", __func__, skb_queue_len(&rtk_skb_mem_q));
+
+	skb_queue_purge(&rtk_skb_mem_q);
+
+	printk("%s\n", __func__);
+}
+
+module_init(rtw_mem_init);
+module_exit(rtw_mem_exit);
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/core/rtw_mi.c linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/core/rtw_mi.c
--- linux-5.6.3/3rdparty/rtl8821ce/core/rtw_mi.c	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/core/rtw_mi.c	2020-04-10 16:35:06.774658107 +0300
@@ -0,0 +1,1572 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#define _RTW_MI_C_
+
+#include <drv_types.h>
+#include <hal_data.h>
+
+void rtw_mi_update_union_chan_inf(_adapter *adapter, u8 ch, u8 offset , u8 bw)
+{
+	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
+	struct mi_state *iface_state = &dvobj->iface_state;
+
+	iface_state->union_ch = ch;
+	iface_state->union_bw = bw;
+	iface_state->union_offset = offset;
+}
+
+#ifdef DBG_IFACE_STATUS
+#ifdef CONFIG_P2P
+static u8 _rtw_mi_p2p_listen_scan_chk(_adapter *adapter)
+{
+	int i;
+	_adapter *iface;
+	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
+	u8 p2p_listen_scan_state = _FALSE;
+
+	for (i = 0; i < dvobj->iface_nums; i++) {
+		iface = dvobj->padapters[i];
+		if (rtw_p2p_chk_state(&iface->wdinfo, P2P_STATE_LISTEN) ||
+			rtw_p2p_chk_state(&iface->wdinfo, P2P_STATE_SCAN)) {
+			p2p_listen_scan_state = _TRUE;
+			break;
+		}
+	}
+	return p2p_listen_scan_state;
+}
+#endif
+#endif
+
+u8 rtw_mi_stayin_union_ch_chk(_adapter *adapter)
+{
+	u8 rst = _TRUE;
+	u8 u_ch, u_bw, u_offset;
+	u8 o_ch, o_bw, o_offset;
+
+	u_ch = rtw_mi_get_union_chan(adapter);
+	u_bw = rtw_mi_get_union_bw(adapter);
+	u_offset = rtw_mi_get_union_offset(adapter);
+
+	o_ch = rtw_get_oper_ch(adapter);
+	o_bw = rtw_get_oper_bw(adapter);
+	o_offset = rtw_get_oper_choffset(adapter);
+
+	if ((u_ch != o_ch) || (u_bw != o_bw) || (u_offset != o_offset))
+		rst = _FALSE;
+
+	#ifdef DBG_IFACE_STATUS
+	if (rst == _FALSE) {
+		RTW_ERR("%s Not stay in union channel\n", __func__);
+		if (GET_HAL_DATA(adapter)->bScanInProcess == _TRUE)
+			RTW_ERR("ScanInProcess\n");
+		#ifdef CONFIG_P2P
+		if (_rtw_mi_p2p_listen_scan_chk(adapter))
+			RTW_ERR("P2P in listen or scan state\n");
+		#endif
+		RTW_ERR("union ch, bw, offset: %u,%u,%u\n", u_ch, u_bw, u_offset);
+		RTW_ERR("oper ch, bw, offset: %u,%u,%u\n", o_ch, o_bw, o_offset);
+		RTW_ERR("=========================\n");
+	}
+	#endif
+	return rst;
+}
+
+u8 rtw_mi_stayin_union_band_chk(_adapter *adapter)
+{
+	u8 rst = _TRUE;
+	u8 u_ch, o_ch;
+	u8 u_band, o_band;
+
+	u_ch = rtw_mi_get_union_chan(adapter);
+	o_ch = rtw_get_oper_ch(adapter);
+	u_band = (u_ch > 14) ? BAND_ON_5G : BAND_ON_2_4G;
+	o_band = (o_ch > 14) ? BAND_ON_5G : BAND_ON_2_4G;
+
+	if (u_ch != o_ch)
+		if(u_band != o_band)
+			rst = _FALSE;
+
+	#ifdef DBG_IFACE_STATUS
+	if (rst == _FALSE)
+		RTW_ERR("%s Not stay in union band\n", __func__);
+	#endif
+
+	return rst;
+}
+
+/* Find union about ch, bw, ch_offset of all linked/linking interfaces */
+int rtw_mi_get_ch_setting_union_by_ifbmp(struct dvobj_priv *dvobj, u8 ifbmp, u8 *ch, u8 *bw, u8 *offset)
+{
+	_adapter *iface;
+	struct mlme_ext_priv *mlmeext;
+	int i;
+	u8 ch_ret = 0;
+	u8 bw_ret = CHANNEL_WIDTH_20;
+	u8 offset_ret = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
+	int num = 0;
+
+	if (ch)
+		*ch = 0;
+	if (bw)
+		*bw = CHANNEL_WIDTH_20;
+	if (offset)
+		*offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
+
+	for (i = 0; i < dvobj->iface_nums; i++) {
+		iface = dvobj->padapters[i];
+		if (!iface || !(ifbmp & BIT(iface->iface_id)))
+			continue;
+
+		mlmeext = &iface->mlmeextpriv;
+
+		if (!check_fwstate(&iface->mlmepriv, _FW_LINKED | _FW_UNDER_LINKING))
+			continue;
+
+		if (check_fwstate(&iface->mlmepriv, WIFI_OP_CH_SWITCHING))
+			continue;
+
+		if (num == 0) {
+			ch_ret = mlmeext->cur_channel;
+			bw_ret = mlmeext->cur_bwmode;
+			offset_ret = mlmeext->cur_ch_offset;
+			num++;
+			continue;
+		}
+
+		if (ch_ret != mlmeext->cur_channel) {
+			num = 0;
+			break;
+		}
+
+		if (bw_ret < mlmeext->cur_bwmode) {
+			bw_ret = mlmeext->cur_bwmode;
+			offset_ret = mlmeext->cur_ch_offset;
+		} else if (bw_ret == mlmeext->cur_bwmode && offset_ret != mlmeext->cur_ch_offset) {
+			num = 0;
+			break;
+		}
+
+		num++;
+	}
+
+	if (num) {
+		if (ch)
+			*ch = ch_ret;
+		if (bw)
+			*bw = bw_ret;
+		if (offset)
+			*offset = offset_ret;
+	}
+
+	return num;
+}
+
+inline int rtw_mi_get_ch_setting_union(_adapter *adapter, u8 *ch, u8 *bw, u8 *offset)
+{
+	return rtw_mi_get_ch_setting_union_by_ifbmp(adapter_to_dvobj(adapter), 0xFF, ch, bw, offset);
+}
+
+inline int rtw_mi_get_ch_setting_union_no_self(_adapter *adapter, u8 *ch, u8 *bw, u8 *offset)
+{
+	return rtw_mi_get_ch_setting_union_by_ifbmp(adapter_to_dvobj(adapter), 0xFF & ~BIT(adapter->iface_id), ch, bw, offset);
+}
+
+/* For now, not return union_ch/bw/offset */
+void rtw_mi_status_by_ifbmp(struct dvobj_priv *dvobj, u8 ifbmp, struct mi_state *mstate)
+{
+	_adapter *iface;
+	int i;
+
+	_rtw_memset(mstate, 0, sizeof(struct mi_state));
+
+	for (i = 0; i < dvobj->iface_nums; i++) {
+		iface = dvobj->padapters[i];
+		if (!iface || !(ifbmp & BIT(iface->iface_id)))
+			continue;
+
+		if (check_fwstate(&iface->mlmepriv, WIFI_STATION_STATE) == _TRUE) {
+			MSTATE_STA_NUM(mstate)++;
+			if (check_fwstate(&iface->mlmepriv, _FW_LINKED) == _TRUE) {
+				MSTATE_STA_LD_NUM(mstate)++;
+
+				#ifdef CONFIG_TDLS
+				if (iface->tdlsinfo.link_established == _TRUE)
+					MSTATE_TDLS_LD_NUM(mstate)++;
+				#endif
+				#ifdef CONFIG_P2P
+				if (MLME_IS_GC(iface))
+					MSTATE_P2P_GC_NUM(mstate)++;
+				#endif
+			}
+			if (check_fwstate(&iface->mlmepriv, _FW_UNDER_LINKING) == _TRUE)
+				MSTATE_STA_LG_NUM(mstate)++;
+
+#ifdef CONFIG_AP_MODE
+		} else if (check_fwstate(&iface->mlmepriv, WIFI_AP_STATE) == _TRUE ) {
+			if (check_fwstate(&iface->mlmepriv, _FW_LINKED) == _TRUE) {
+				MSTATE_AP_NUM(mstate)++;
+				if (iface->stapriv.asoc_sta_count > 2)
+					MSTATE_AP_LD_NUM(mstate)++;
+				#ifdef CONFIG_P2P
+				if (MLME_IS_GO(iface))
+					MSTATE_P2P_GO_NUM(mstate)++;
+				#endif
+			} else
+				MSTATE_AP_STARTING_NUM(mstate)++;
+#endif
+
+		} else if (check_fwstate(&iface->mlmepriv, WIFI_ADHOC_STATE | WIFI_ADHOC_MASTER_STATE) == _TRUE
+			&& check_fwstate(&iface->mlmepriv, _FW_LINKED) == _TRUE
+		) {
+			MSTATE_ADHOC_NUM(mstate)++;
+			if (iface->stapriv.asoc_sta_count > 2)
+				MSTATE_ADHOC_LD_NUM(mstate)++;
+
+#ifdef CONFIG_RTW_MESH
+		} else if (check_fwstate(&iface->mlmepriv, WIFI_MESH_STATE) == _TRUE
+			&& check_fwstate(&iface->mlmepriv, _FW_LINKED) == _TRUE
+		) {
+			MSTATE_MESH_NUM(mstate)++;
+			if (iface->stapriv.asoc_sta_count > 2)
+				MSTATE_MESH_LD_NUM(mstate)++;
+#endif
+
+		}
+
+		if (check_fwstate(&iface->mlmepriv, WIFI_UNDER_WPS) == _TRUE)
+			MSTATE_WPS_NUM(mstate)++;
+
+		if (check_fwstate(&iface->mlmepriv, WIFI_SITE_MONITOR) == _TRUE) {
+			MSTATE_SCAN_NUM(mstate)++;
+
+			if (mlmeext_scan_state(&iface->mlmeextpriv) != SCAN_DISABLE
+				&& mlmeext_scan_state(&iface->mlmeextpriv) != SCAN_BACK_OP)
+				MSTATE_SCAN_ENTER_NUM(mstate)++;
+		}
+
+#ifdef CONFIG_IOCTL_CFG80211
+		if (rtw_cfg80211_get_is_mgmt_tx(iface))
+			MSTATE_MGMT_TX_NUM(mstate)++;
+		#ifdef CONFIG_P2P
+		if (rtw_cfg80211_get_is_roch(iface) == _TRUE)
+			MSTATE_ROCH_NUM(mstate)++;
+		#endif
+#endif /* CONFIG_IOCTL_CFG80211 */
+#ifdef CONFIG_P2P
+		if (MLME_IS_PD(iface))
+			MSTATE_P2P_DV_NUM(mstate)++;
+#endif
+	}
+}
+
+inline void rtw_mi_status(_adapter *adapter, struct mi_state *mstate)
+{
+	return rtw_mi_status_by_ifbmp(adapter_to_dvobj(adapter), 0xFF, mstate);
+}
+
+inline void rtw_mi_status_no_self(_adapter *adapter, struct mi_state *mstate)
+{
+	return rtw_mi_status_by_ifbmp(adapter_to_dvobj(adapter), 0xFF & ~BIT(adapter->iface_id), mstate);
+}
+
+inline void rtw_mi_status_no_others(_adapter *adapter, struct mi_state *mstate)
+{
+	return rtw_mi_status_by_ifbmp(adapter_to_dvobj(adapter), BIT(adapter->iface_id), mstate);
+}
+
+/* For now, not handle union_ch/bw/offset */
+inline void rtw_mi_status_merge(struct mi_state *d, struct mi_state *a)
+{
+	d->sta_num += a->sta_num;
+	d->ld_sta_num += a->ld_sta_num;
+	d->lg_sta_num += a->lg_sta_num;
+#ifdef CONFIG_TDLS
+	d->ld_tdls_num += a->ld_tdls_num;
+#endif
+#ifdef CONFIG_AP_MODE
+	d->ap_num += a->ap_num;
+	d->ld_ap_num += a->ld_ap_num;
+#endif
+	d->adhoc_num += a->adhoc_num;
+	d->ld_adhoc_num += a->ld_adhoc_num;
+#ifdef CONFIG_RTW_MESH
+	d->mesh_num += a->mesh_num;
+	d->ld_mesh_num += a->ld_mesh_num;
+#endif
+	d->scan_num += a->scan_num;
+	d->scan_enter_num += a->scan_enter_num;
+	d->uwps_num += a->uwps_num;
+#ifdef CONFIG_IOCTL_CFG80211
+	#ifdef CONFIG_P2P
+	d->roch_num += a->roch_num;
+	#endif
+	d->mgmt_tx_num += a->mgmt_tx_num;
+#endif
+}
+
+void dump_mi_status(void *sel, struct dvobj_priv *dvobj)
+{
+	RTW_PRINT_SEL(sel, "== dvobj-iface_state ==\n");
+	RTW_PRINT_SEL(sel, "sta_num:%d\n", DEV_STA_NUM(dvobj));
+	RTW_PRINT_SEL(sel, "linking_sta_num:%d\n", DEV_STA_LG_NUM(dvobj));
+	RTW_PRINT_SEL(sel, "linked_sta_num:%d\n", DEV_STA_LD_NUM(dvobj));
+#ifdef CONFIG_TDLS
+	RTW_PRINT_SEL(sel, "linked_tdls_num:%d\n", DEV_TDLS_LD_NUM(dvobj));
+#endif
+#ifdef CONFIG_AP_MODE
+	RTW_PRINT_SEL(sel, "ap_num:%d\n", DEV_AP_NUM(dvobj));
+	RTW_PRINT_SEL(sel, "starting_ap_num:%d\n", DEV_AP_STARTING_NUM(dvobj));
+	RTW_PRINT_SEL(sel, "linked_ap_num:%d\n", DEV_AP_LD_NUM(dvobj));
+#endif
+	RTW_PRINT_SEL(sel, "adhoc_num:%d\n", DEV_ADHOC_NUM(dvobj));
+	RTW_PRINT_SEL(sel, "linked_adhoc_num:%d\n", DEV_ADHOC_LD_NUM(dvobj));
+#ifdef CONFIG_RTW_MESH
+	RTW_PRINT_SEL(sel, "mesh_num:%d\n", DEV_MESH_NUM(dvobj));
+	RTW_PRINT_SEL(sel, "linked_mesh_num:%d\n", DEV_MESH_LD_NUM(dvobj));
+#endif
+#ifdef CONFIG_P2P
+	RTW_PRINT_SEL(sel, "p2p_device_num:%d\n", DEV_P2P_DV_NUM(dvobj));
+	RTW_PRINT_SEL(sel, "p2p_gc_num:%d\n", DEV_P2P_GC_NUM(dvobj));
+	RTW_PRINT_SEL(sel, "p2p_go_num:%d\n", DEV_P2P_GO_NUM(dvobj));
+#endif
+	RTW_PRINT_SEL(sel, "scan_num:%d\n", DEV_SCAN_NUM(dvobj));
+	RTW_PRINT_SEL(sel, "under_wps_num:%d\n", DEV_WPS_NUM(dvobj));
+#if defined(CONFIG_IOCTL_CFG80211)
+	#if defined(CONFIG_P2P)
+	RTW_PRINT_SEL(sel, "roch_num:%d\n", DEV_ROCH_NUM(dvobj));
+	#endif
+	RTW_PRINT_SEL(sel, "mgmt_tx_num:%d\n", DEV_MGMT_TX_NUM(dvobj));
+#endif
+	RTW_PRINT_SEL(sel, "union_ch:%d\n", DEV_U_CH(dvobj));
+	RTW_PRINT_SEL(sel, "union_bw:%d\n", DEV_U_BW(dvobj));
+	RTW_PRINT_SEL(sel, "union_offset:%d\n", DEV_U_OFFSET(dvobj));
+	RTW_PRINT_SEL(sel, "================\n\n");
+}
+
+void dump_dvobj_mi_status(void *sel, const char *fun_name, _adapter *adapter)
+{
+	RTW_INFO("\n[ %s ] call %s\n", fun_name, __func__);
+	dump_mi_status(sel, adapter_to_dvobj(adapter));
+}
+
+inline void rtw_mi_update_iface_status(struct mlme_priv *pmlmepriv, sint state)
+{
+	_adapter *adapter = container_of(pmlmepriv, _adapter, mlmepriv);
+	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
+	struct mi_state *iface_state = &dvobj->iface_state;
+	struct mi_state tmp_mstate;
+	u8 u_ch, u_offset, u_bw;
+
+	if (state == WIFI_MONITOR_STATE
+		|| state == 0xFFFFFFFF
+	)
+		return;
+
+	if (0)
+		RTW_INFO("%s => will change or clean state to 0x%08x\n", __func__, state);
+
+	rtw_mi_status(adapter, &tmp_mstate);
+	_rtw_memcpy(iface_state, &tmp_mstate, sizeof(struct mi_state));
+
+	if (rtw_mi_get_ch_setting_union(adapter, &u_ch, &u_bw, &u_offset))
+		rtw_mi_update_union_chan_inf(adapter , u_ch, u_offset , u_bw);
+	else {
+		if (0) {
+			dump_adapters_status(RTW_DBGDUMP , dvobj);
+			RTW_INFO("%s-[ERROR] cannot get union channel\n", __func__);
+			rtw_warn_on(1);
+		}
+	}
+
+#ifdef DBG_IFACE_STATUS
+	DBG_IFACE_STATUS_DUMP(adapter);
+#endif
+}
+u8 rtw_mi_check_status(_adapter *adapter, u8 type)
+{
+	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
+	struct mi_state *iface_state = &dvobj->iface_state;
+	u8 ret = _FALSE;
+
+#ifdef DBG_IFACE_STATUS
+	DBG_IFACE_STATUS_DUMP(adapter);
+	RTW_INFO("%s-"ADPT_FMT" check type:%d\n", __func__, ADPT_ARG(adapter), type);
+#endif
+
+	switch (type) {
+	case MI_LINKED:
+		if (MSTATE_STA_LD_NUM(iface_state) || MSTATE_AP_NUM(iface_state) || MSTATE_ADHOC_NUM(iface_state) || MSTATE_MESH_NUM(iface_state)) /*check_fwstate(&iface->mlmepriv, _FW_LINKED)*/
+			ret = _TRUE;
+		break;
+	case MI_ASSOC:
+		if (MSTATE_STA_LD_NUM(iface_state) || MSTATE_AP_LD_NUM(iface_state) || MSTATE_ADHOC_LD_NUM(iface_state) || MSTATE_MESH_LD_NUM(iface_state))
+			ret = _TRUE;
+		break;
+	case MI_UNDER_WPS:
+		if (MSTATE_WPS_NUM(iface_state))
+			ret = _TRUE;
+		break;
+
+	case MI_AP_MODE:
+		if (MSTATE_AP_NUM(iface_state))
+			ret = _TRUE;
+		break;
+	case MI_AP_ASSOC:
+		if (MSTATE_AP_LD_NUM(iface_state))
+			ret = _TRUE;
+		break;
+
+	case MI_ADHOC:
+		if (MSTATE_ADHOC_NUM(iface_state))
+			ret = _TRUE;
+		break;
+	case MI_ADHOC_ASSOC:
+		if (MSTATE_ADHOC_LD_NUM(iface_state))
+			ret = _TRUE;
+		break;
+
+#ifdef CONFIG_RTW_MESH
+	case MI_MESH:
+		if (MSTATE_MESH_NUM(iface_state))
+			ret = _TRUE;
+		break;
+	case MI_MESH_ASSOC:
+		if (MSTATE_MESH_LD_NUM(iface_state))
+			ret = _TRUE;
+		break;
+#endif
+
+	case MI_STA_NOLINK: /* this is misleading, but not used now */
+		if (MSTATE_STA_NUM(iface_state) && (!(MSTATE_STA_LD_NUM(iface_state) || MSTATE_STA_LG_NUM(iface_state))))
+			ret = _TRUE;
+		break;
+	case MI_STA_LINKED:
+		if (MSTATE_STA_LD_NUM(iface_state))
+			ret = _TRUE;
+		break;
+	case MI_STA_LINKING:
+		if (MSTATE_STA_LG_NUM(iface_state))
+			ret = _TRUE;
+		break;
+
+	default:
+		break;
+	}
+	return ret;
+}
+
+/*
+* return value : 0 is failed or have not interface meet condition
+* return value : !0 is success or interface numbers which meet condition
+* return value of ops_func must be _TRUE or _FALSE
+*/
+static u8 _rtw_mi_process(_adapter *padapter, bool exclude_self,
+		  void *data, u8(*ops_func)(_adapter *padapter, void *data))
+{
+	int i;
+	_adapter *iface;
+	struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
+
+	u8 ret = 0;
+
+	for (i = 0; i < dvobj->iface_nums; i++) {
+		iface = dvobj->padapters[i];
+		if ((iface) && rtw_is_adapter_up(iface)) {
+
+			if ((exclude_self) && (iface == padapter))
+				continue;
+
+			if (ops_func)
+				if (_TRUE == ops_func(iface, data))
+					ret++;
+		}
+	}
+	return ret;
+}
+static u8 _rtw_mi_process_without_schk(_adapter *padapter, bool exclude_self,
+		  void *data, u8(*ops_func)(_adapter *padapter, void *data))
+{
+	int i;
+	_adapter *iface;
+	struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
+
+	u8 ret = 0;
+
+	for (i = 0; i < dvobj->iface_nums; i++) {
+		iface = dvobj->padapters[i];
+		if (iface) {
+			if ((exclude_self) && (iface == padapter))
+				continue;
+
+			if (ops_func)
+				if (ops_func(iface, data) == _TRUE)
+					ret++;
+		}
+	}
+	return ret;
+}
+
+static u8 _rtw_mi_netif_caroff_qstop(_adapter *padapter, void *data)
+{
+	struct net_device *pnetdev = padapter->pnetdev;
+
+	rtw_netif_carrier_off(pnetdev);
+	rtw_netif_stop_queue(pnetdev);
+	return _TRUE;
+}
+u8 rtw_mi_netif_caroff_qstop(_adapter *padapter)
+{
+	return _rtw_mi_process(padapter, _FALSE, NULL, _rtw_mi_netif_caroff_qstop);
+}
+u8 rtw_mi_buddy_netif_caroff_qstop(_adapter *padapter)
+{
+	return _rtw_mi_process(padapter, _TRUE, NULL, _rtw_mi_netif_caroff_qstop);
+}
+
+static u8 _rtw_mi_netif_caron_qstart(_adapter *padapter, void *data)
+{
+	struct net_device *pnetdev = padapter->pnetdev;
+
+	rtw_netif_carrier_on(pnetdev);
+	rtw_netif_start_queue(pnetdev);
+	return _TRUE;
+}
+u8 rtw_mi_netif_caron_qstart(_adapter *padapter)
+{
+	return _rtw_mi_process(padapter, _FALSE, NULL, _rtw_mi_netif_caron_qstart);
+}
+u8 rtw_mi_buddy_netif_caron_qstart(_adapter *padapter)
+{
+	return _rtw_mi_process(padapter, _TRUE, NULL, _rtw_mi_netif_caron_qstart);
+}
+
+static u8 _rtw_mi_netif_stop_queue(_adapter *padapter, void *data)
+{
+	struct net_device *pnetdev = padapter->pnetdev;
+
+	rtw_netif_stop_queue(pnetdev);
+	return _TRUE;
+}
+u8 rtw_mi_netif_stop_queue(_adapter *padapter)
+{
+	return _rtw_mi_process(padapter, _FALSE, NULL, _rtw_mi_netif_stop_queue);
+}
+u8 rtw_mi_buddy_netif_stop_queue(_adapter *padapter)
+{
+	return _rtw_mi_process(padapter, _TRUE, NULL, _rtw_mi_netif_stop_queue);
+}
+
+static u8 _rtw_mi_netif_wake_queue(_adapter *padapter, void *data)
+{
+	struct net_device *pnetdev = padapter->pnetdev;
+
+	if (pnetdev)
+		rtw_netif_wake_queue(pnetdev);
+	return _TRUE;
+}
+u8 rtw_mi_netif_wake_queue(_adapter *padapter)
+{
+	return _rtw_mi_process(padapter, _FALSE, NULL, _rtw_mi_netif_wake_queue);
+}
+u8 rtw_mi_buddy_netif_wake_queue(_adapter *padapter)
+{
+	return _rtw_mi_process(padapter, _TRUE, NULL, _rtw_mi_netif_wake_queue);
+}
+
+static u8 _rtw_mi_netif_carrier_on(_adapter *padapter, void *data)
+{
+	struct net_device *pnetdev = padapter->pnetdev;
+
+	if (pnetdev)
+		rtw_netif_carrier_on(pnetdev);
+	return _TRUE;
+}
+u8 rtw_mi_netif_carrier_on(_adapter *padapter)
+{
+	return _rtw_mi_process(padapter, _FALSE, NULL, _rtw_mi_netif_carrier_on);
+}
+u8 rtw_mi_buddy_netif_carrier_on(_adapter *padapter)
+{
+	return _rtw_mi_process(padapter, _TRUE, NULL, _rtw_mi_netif_carrier_on);
+}
+
+static u8 _rtw_mi_netif_carrier_off(_adapter *padapter, void *data)
+{
+	struct net_device *pnetdev = padapter->pnetdev;
+
+	if (pnetdev)
+		rtw_netif_carrier_off(pnetdev);
+	return _TRUE;
+}
+u8 rtw_mi_netif_carrier_off(_adapter *padapter)
+{
+	return _rtw_mi_process(padapter, _FALSE, NULL, _rtw_mi_netif_carrier_off);
+}
+u8 rtw_mi_buddy_netif_carrier_off(_adapter *padapter)
+{
+	return _rtw_mi_process(padapter, _TRUE, NULL, _rtw_mi_netif_carrier_off);
+}
+
+static u8 _rtw_mi_scan_abort(_adapter *adapter, void *data)
+{
+	bool bwait = *(bool *)data;
+
+	if (bwait)
+		rtw_scan_abort(adapter);
+	else
+		rtw_scan_abort_no_wait(adapter);
+
+	return _TRUE;
+}
+void rtw_mi_scan_abort(_adapter *adapter, bool bwait)
+{
+	bool in_data = bwait;
+
+	_rtw_mi_process(adapter, _FALSE, &in_data, _rtw_mi_scan_abort);
+
+}
+void rtw_mi_buddy_scan_abort(_adapter *adapter, bool bwait)
+{
+	bool in_data = bwait;
+
+	_rtw_mi_process(adapter, _TRUE, &in_data, _rtw_mi_scan_abort);
+}
+
+static u32 _rtw_mi_start_drv_threads(_adapter *adapter, bool exclude_self)
+{
+	int i;
+	_adapter *iface = NULL;
+	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
+	u32 _status = _SUCCESS;
+
+	for (i = 0; i < dvobj->iface_nums; i++) {
+		iface = dvobj->padapters[i];
+		if (iface) {
+			if ((exclude_self) && (iface == adapter))
+				continue;
+			if (rtw_start_drv_threads(iface) == _FAIL) {
+				_status = _FAIL;
+				break;
+			}
+		}
+	}
+	return _status;
+}
+u32 rtw_mi_start_drv_threads(_adapter *adapter)
+{
+	return _rtw_mi_start_drv_threads(adapter, _FALSE);
+}
+u32 rtw_mi_buddy_start_drv_threads(_adapter *adapter)
+{
+	return _rtw_mi_start_drv_threads(adapter, _TRUE);
+}
+
+static void _rtw_mi_stop_drv_threads(_adapter *adapter, bool exclude_self)
+{
+	int i;
+	_adapter *iface = NULL;
+	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
+
+	for (i = 0; i < dvobj->iface_nums; i++) {
+		iface = dvobj->padapters[i];
+		if (iface) {
+			if ((exclude_self) && (iface == adapter))
+				continue;
+			rtw_stop_drv_threads(iface);
+		}
+	}
+}
+void rtw_mi_stop_drv_threads(_adapter *adapter)
+{
+	_rtw_mi_stop_drv_threads(adapter, _FALSE);
+}
+void rtw_mi_buddy_stop_drv_threads(_adapter *adapter)
+{
+	_rtw_mi_stop_drv_threads(adapter, _TRUE);
+}
+
+static u8 _rtw_mi_cancel_all_timer(_adapter *adapter, void *data)
+{
+	rtw_cancel_all_timer(adapter);
+	return _TRUE;
+}
+void rtw_mi_cancel_all_timer(_adapter *adapter)
+{
+	_rtw_mi_process(adapter, _FALSE, NULL, _rtw_mi_cancel_all_timer);
+}
+void rtw_mi_buddy_cancel_all_timer(_adapter *adapter)
+{
+	_rtw_mi_process(adapter, _TRUE, NULL, _rtw_mi_cancel_all_timer);
+}
+
+static u8 _rtw_mi_reset_drv_sw(_adapter *adapter, void *data)
+{
+	rtw_reset_drv_sw(adapter);
+	return _TRUE;
+}
+void rtw_mi_reset_drv_sw(_adapter *adapter)
+{
+	_rtw_mi_process_without_schk(adapter, _FALSE, NULL, _rtw_mi_reset_drv_sw);
+}
+void rtw_mi_buddy_reset_drv_sw(_adapter *adapter)
+{
+	_rtw_mi_process_without_schk(adapter, _TRUE, NULL, _rtw_mi_reset_drv_sw);
+}
+
+static u8 _rtw_mi_intf_start(_adapter *adapter, void *data)
+{
+	rtw_intf_start(adapter);
+	return _TRUE;
+}
+void rtw_mi_intf_start(_adapter *adapter)
+{
+	_rtw_mi_process(adapter, _FALSE, NULL, _rtw_mi_intf_start);
+}
+void rtw_mi_buddy_intf_start(_adapter *adapter)
+{
+	_rtw_mi_process(adapter, _TRUE, NULL, _rtw_mi_intf_start);
+}
+
+static u8 _rtw_mi_intf_stop(_adapter *adapter, void *data)
+{
+	rtw_intf_stop(adapter);
+	return _TRUE;
+}
+void rtw_mi_intf_stop(_adapter *adapter)
+{
+	_rtw_mi_process(adapter, _FALSE, NULL, _rtw_mi_intf_stop);
+}
+void rtw_mi_buddy_intf_stop(_adapter *adapter)
+{
+	_rtw_mi_process(adapter, _TRUE, NULL, _rtw_mi_intf_stop);
+}
+
+#ifdef CONFIG_NEW_NETDEV_HDL
+static u8 _rtw_mi_hal_iface_init(_adapter *padapter, void *data)
+{
+	if (rtw_hal_iface_init(padapter) == _SUCCESS)
+		return _TRUE;
+	return _FALSE;
+}
+u8 rtw_mi_hal_iface_init(_adapter *padapter)
+{
+	int i;
+	_adapter *iface;
+	struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
+
+	u8 ret = _TRUE;
+
+	for (i = 0; i < dvobj->iface_nums; i++) {
+		iface = dvobj->padapters[i];
+		if (iface && iface->netif_up)
+			rtw_hal_iface_init(padapter);
+	}
+	return ret;
+}
+#endif
+
+static u8 _rtw_mi_suspend_free_assoc_resource(_adapter *padapter, void *data)
+{
+	return rtw_suspend_free_assoc_resource(padapter);
+}
+void rtw_mi_suspend_free_assoc_resource(_adapter *adapter)
+{
+	_rtw_mi_process(adapter, _FALSE, NULL, _rtw_mi_suspend_free_assoc_resource);
+}
+void rtw_mi_buddy_suspend_free_assoc_resource(_adapter *adapter)
+{
+	_rtw_mi_process(adapter, _TRUE, NULL, _rtw_mi_suspend_free_assoc_resource);
+}
+
+static u8 _rtw_mi_is_scan_deny(_adapter *adapter, void *data)
+{
+	return rtw_is_scan_deny(adapter);
+}
+
+u8 rtw_mi_is_scan_deny(_adapter *adapter)
+{
+	return _rtw_mi_process(adapter, _FALSE, NULL, _rtw_mi_is_scan_deny);
+
+}
+u8 rtw_mi_buddy_is_scan_deny(_adapter *adapter)
+{
+	return _rtw_mi_process(adapter, _TRUE, NULL, _rtw_mi_is_scan_deny);
+}
+
+#ifdef CONFIG_SET_SCAN_DENY_TIMER
+static u8 _rtw_mi_set_scan_deny(_adapter *adapter, void *data)
+{
+	u32 ms = *(u32 *)data;
+
+	rtw_set_scan_deny(adapter, ms);
+	return _TRUE;
+}
+void rtw_mi_set_scan_deny(_adapter *adapter, u32 ms)
+{
+	u32 in_data = ms;
+
+	_rtw_mi_process(adapter, _FALSE, &in_data, _rtw_mi_set_scan_deny);
+}
+void rtw_mi_buddy_set_scan_deny(_adapter *adapter, u32 ms)
+{
+	u32 in_data = ms;
+
+	_rtw_mi_process(adapter, _TRUE, &in_data, _rtw_mi_set_scan_deny);
+}
+#endif /*CONFIG_SET_SCAN_DENY_TIMER*/
+
+static u8 _rtw_mi_beacon_update(_adapter *padapter, void *data)
+{
+	if (!MLME_IS_STA(padapter)
+	    && check_fwstate(&padapter->mlmepriv, _FW_LINKED) == _TRUE) {
+		RTW_INFO(ADPT_FMT" - update_beacon\n", ADPT_ARG(padapter));
+		update_beacon(padapter, 0xFF, NULL, _TRUE);
+	}
+	return _TRUE;
+}
+
+void rtw_mi_beacon_update(_adapter *padapter)
+{
+	_rtw_mi_process(padapter, _FALSE, NULL, _rtw_mi_beacon_update);
+}
+
+void rtw_mi_buddy_beacon_update(_adapter *padapter)
+{
+	_rtw_mi_process(padapter, _TRUE, NULL, _rtw_mi_beacon_update);
+}
+
+static u8 _rtw_mi_hal_dump_macaddr(_adapter *padapter, void *data)
+{
+	u8 mac_addr[ETH_ALEN] = {0};
+
+	rtw_hal_get_hwreg(padapter, HW_VAR_MAC_ADDR, mac_addr);
+	RTW_INFO(ADPT_FMT"MAC Address ="MAC_FMT"\n", ADPT_ARG(padapter), MAC_ARG(mac_addr));
+	return _TRUE;
+}
+void rtw_mi_hal_dump_macaddr(_adapter *padapter)
+{
+	_rtw_mi_process(padapter, _FALSE, NULL, _rtw_mi_hal_dump_macaddr);
+}
+void rtw_mi_buddy_hal_dump_macaddr(_adapter *padapter)
+{
+	_rtw_mi_process(padapter, _TRUE, NULL, _rtw_mi_hal_dump_macaddr);
+}
+
+#ifdef CONFIG_PCI_HCI
+static u8 _rtw_mi_xmit_tasklet_schedule(_adapter *padapter, void *data)
+{
+	if (rtw_txframes_pending(padapter)) {
+		/* try to deal with the pending packets */
+		tasklet_hi_schedule(&(padapter->xmitpriv.xmit_tasklet));
+	}
+	return _TRUE;
+}
+void rtw_mi_xmit_tasklet_schedule(_adapter *padapter)
+{
+	_rtw_mi_process(padapter, _FALSE, NULL, _rtw_mi_xmit_tasklet_schedule);
+}
+void rtw_mi_buddy_xmit_tasklet_schedule(_adapter *padapter)
+{
+	_rtw_mi_process(padapter, _TRUE, NULL, _rtw_mi_xmit_tasklet_schedule);
+}
+#endif
+
+u8 _rtw_mi_busy_traffic_check(_adapter *padapter, void *data)
+{
+	u32 passtime;
+	struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
+	bool check_sc_interval = *(bool *)data;
+
+	if (pmlmepriv->LinkDetectInfo.bBusyTraffic == _TRUE) {
+		if (check_sc_interval) {
+			/* Miracast can't do AP scan*/
+			passtime = rtw_get_passing_time_ms(pmlmepriv->lastscantime);
+			pmlmepriv->lastscantime = rtw_get_current_time();
+			if (passtime > BUSY_TRAFFIC_SCAN_DENY_PERIOD) {
+				RTW_INFO(ADPT_FMT" bBusyTraffic == _TRUE\n", ADPT_ARG(padapter));
+				return _TRUE;
+			}
+		} else
+			return _TRUE;
+	}
+
+	return _FALSE;
+}
+
+u8 rtw_mi_busy_traffic_check(_adapter *padapter, bool check_sc_interval)
+{
+	bool in_data = check_sc_interval;
+
+	return _rtw_mi_process(padapter, _FALSE, &in_data, _rtw_mi_busy_traffic_check);
+}
+u8 rtw_mi_buddy_busy_traffic_check(_adapter *padapter, bool check_sc_interval)
+{
+	bool in_data = check_sc_interval;
+
+	return _rtw_mi_process(padapter, _TRUE, &in_data, _rtw_mi_busy_traffic_check);
+}
+static u8 _rtw_mi_check_mlmeinfo_state(_adapter *padapter, void *data)
+{
+	u32 state = *(u32 *)data;
+	struct mlme_ext_priv *mlmeext = &padapter->mlmeextpriv;
+
+	/*if (mlmeext_msr(mlmeext) == state)*/
+	if (check_mlmeinfo_state(mlmeext, state))
+		return _TRUE;
+	else
+		return _FALSE;
+}
+
+u8 rtw_mi_check_mlmeinfo_state(_adapter *padapter, u32 state)
+{
+	u32 in_data = state;
+
+	return _rtw_mi_process(padapter, _FALSE, &in_data, _rtw_mi_check_mlmeinfo_state);
+}
+
+u8 rtw_mi_buddy_check_mlmeinfo_state(_adapter *padapter, u32 state)
+{
+	u32 in_data = state;
+
+	return _rtw_mi_process(padapter, _TRUE, &in_data, _rtw_mi_check_mlmeinfo_state);
+}
+
+/*#define DBG_DUMP_FW_STATE*/
+#ifdef DBG_DUMP_FW_STATE
+static void rtw_dbg_dump_fwstate(_adapter *padapter, sint state)
+{
+	u8 buf[32] = {0};
+
+	if (state & WIFI_FW_NULL_STATE) {
+		_rtw_memset(buf, 0, 32);
+		sprintf(buf, "WIFI_FW_NULL_STATE");
+		RTW_INFO(FUNC_ADPT_FMT"fwstate-%s\n", FUNC_ADPT_ARG(padapter), buf);
+	}
+
+	if (state & _FW_LINKED) {
+		_rtw_memset(buf, 0, 32);
+		sprintf(buf, "_FW_LINKED");
+		RTW_INFO(FUNC_ADPT_FMT"fwstate-%s\n", FUNC_ADPT_ARG(padapter), buf);
+	}
+
+	if (state & _FW_UNDER_LINKING) {
+		_rtw_memset(buf, 0, 32);
+		sprintf(buf, "_FW_UNDER_LINKING");
+		RTW_INFO(FUNC_ADPT_FMT"fwstate-%s\n", FUNC_ADPT_ARG(padapter), buf);
+	}
+
+	if (state & _FW_UNDER_SURVEY) {
+		_rtw_memset(buf, 0, 32);
+		sprintf(buf, "_FW_UNDER_SURVEY");
+		RTW_INFO(FUNC_ADPT_FMT"fwstate-%s\n", FUNC_ADPT_ARG(padapter), buf);
+	}
+}
+#endif
+
+static u8 _rtw_mi_check_fwstate(_adapter *padapter, void *data)
+{
+	u8 ret = _FALSE;
+
+	sint state = *(sint *)data;
+
+	if ((state == WIFI_FW_NULL_STATE) &&
+	    (padapter->mlmepriv.fw_state == WIFI_FW_NULL_STATE))
+		ret = _TRUE;
+	else if (_TRUE == check_fwstate(&padapter->mlmepriv, state))
+		ret = _TRUE;
+#ifdef DBG_DUMP_FW_STATE
+	if (ret)
+		rtw_dbg_dump_fwstate(padapter, state);
+#endif
+	return ret;
+}
+u8 rtw_mi_check_fwstate(_adapter *padapter, sint state)
+{
+	sint in_data = state;
+
+	return _rtw_mi_process(padapter, _FALSE, &in_data, _rtw_mi_check_fwstate);
+}
+u8 rtw_mi_buddy_check_fwstate(_adapter *padapter, sint state)
+{
+	sint in_data = state;
+
+	return _rtw_mi_process(padapter, _TRUE, &in_data, _rtw_mi_check_fwstate);
+}
+
+static u8 _rtw_mi_traffic_statistics(_adapter *padapter , void *data)
+{
+	struct dvobj_priv	*pdvobjpriv = adapter_to_dvobj(padapter);
+
+	/* Tx */
+	pdvobjpriv->traffic_stat.tx_bytes += padapter->xmitpriv.tx_bytes;
+	pdvobjpriv->traffic_stat.tx_pkts += padapter->xmitpriv.tx_pkts;
+	pdvobjpriv->traffic_stat.tx_drop += padapter->xmitpriv.tx_drop;
+
+	/* Rx */
+	pdvobjpriv->traffic_stat.rx_bytes += padapter->recvpriv.rx_bytes;
+	pdvobjpriv->traffic_stat.rx_pkts += padapter->recvpriv.rx_pkts;
+	pdvobjpriv->traffic_stat.rx_drop += padapter->recvpriv.rx_drop;
+	return _TRUE;
+}
+u8 rtw_mi_traffic_statistics(_adapter *padapter)
+{
+	return _rtw_mi_process(padapter, _FALSE, NULL, _rtw_mi_traffic_statistics);
+}
+
+static u8 _rtw_mi_check_miracast_enabled(_adapter *padapter , void *data)
+{
+	return is_miracast_enabled(padapter);
+}
+u8 rtw_mi_check_miracast_enabled(_adapter *padapter)
+{
+	return _rtw_mi_process(padapter, _FALSE, NULL, _rtw_mi_check_miracast_enabled);
+}
+
+#ifdef CONFIG_XMIT_THREAD_MODE
+static u8 _rtw_mi_check_pending_xmitbuf(_adapter *padapter , void *data)
+{
+	struct xmit_priv *pxmitpriv = &padapter->xmitpriv;
+
+	return check_pending_xmitbuf(pxmitpriv);
+}
+u8 rtw_mi_check_pending_xmitbuf(_adapter *padapter)
+{
+	return _rtw_mi_process(padapter, _FALSE, NULL, _rtw_mi_check_pending_xmitbuf);
+}
+u8 rtw_mi_buddy_check_pending_xmitbuf(_adapter *padapter)
+{
+	return _rtw_mi_process(padapter, _TRUE, NULL, _rtw_mi_check_pending_xmitbuf);
+}
+#endif
+
+#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
+static u8 _rtw_mi_dequeue_writeport(_adapter *padapter , bool exclude_self)
+{
+	int i;
+	u8	queue_empty = _TRUE;
+	_adapter *iface;
+	struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
+
+	for (i = 0; i < dvobj->iface_nums; i++) {
+		iface = dvobj->padapters[i];
+		if ((iface) && rtw_is_adapter_up(iface)) {
+
+			if ((exclude_self) && (iface == padapter))
+				continue;
+
+			queue_empty &= _dequeue_writeport(iface);
+		}
+	}
+	return queue_empty;
+}
+u8 rtw_mi_dequeue_writeport(_adapter *padapter)
+{
+	return _rtw_mi_dequeue_writeport(padapter, _FALSE);
+}
+u8 rtw_mi_buddy_dequeue_writeport(_adapter *padapter)
+{
+	return _rtw_mi_dequeue_writeport(padapter, _TRUE);
+}
+#endif
+static void _rtw_mi_adapter_reset(_adapter *padapter , u8 exclude_self)
+{
+	int i;
+	struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
+
+	for (i = 0; i < dvobj->iface_nums; i++) {
+		if (dvobj->padapters[i]) {
+			if ((exclude_self) && (dvobj->padapters[i] == padapter))
+				continue;
+			dvobj->padapters[i] = NULL;
+		}
+	}
+}
+
+void rtw_mi_adapter_reset(_adapter *padapter)
+{
+	_rtw_mi_adapter_reset(padapter, _FALSE);
+}
+
+void rtw_mi_buddy_adapter_reset(_adapter *padapter)
+{
+	_rtw_mi_adapter_reset(padapter, _TRUE);
+}
+
+static u8 _rtw_mi_dynamic_check_timer_handlder(_adapter *adapter, void *data)
+{
+	rtw_iface_dynamic_check_timer_handlder(adapter);
+	return _TRUE;
+}
+u8 rtw_mi_dynamic_check_timer_handlder(_adapter *padapter)
+{
+	return _rtw_mi_process(padapter, _FALSE, NULL, _rtw_mi_dynamic_check_timer_handlder);
+}
+u8 rtw_mi_buddy_dynamic_check_timer_handlder(_adapter *padapter)
+{
+	return _rtw_mi_process(padapter, _TRUE, NULL, _rtw_mi_dynamic_check_timer_handlder);
+}
+
+static u8 _rtw_mi_dynamic_chk_wk_hdl(_adapter *adapter, void *data)
+{
+	rtw_iface_dynamic_chk_wk_hdl(adapter);
+	return _TRUE;
+}
+u8 rtw_mi_dynamic_chk_wk_hdl(_adapter *padapter)
+{
+	return _rtw_mi_process(padapter, _FALSE, NULL, _rtw_mi_dynamic_chk_wk_hdl);
+}
+u8 rtw_mi_buddy_dynamic_chk_wk_hdl(_adapter *padapter)
+{
+	return _rtw_mi_process(padapter, _TRUE, NULL, _rtw_mi_dynamic_chk_wk_hdl);
+}
+
+static u8 _rtw_mi_os_xmit_schedule(_adapter *adapter, void *data)
+{
+	rtw_os_xmit_schedule(adapter);
+	return _TRUE;
+}
+u8 rtw_mi_os_xmit_schedule(_adapter *padapter)
+{
+	return _rtw_mi_process(padapter, _FALSE, NULL, _rtw_mi_os_xmit_schedule);
+}
+u8 rtw_mi_buddy_os_xmit_schedule(_adapter *padapter)
+{
+	return _rtw_mi_process(padapter, _TRUE, NULL, _rtw_mi_os_xmit_schedule);
+}
+
+static u8 _rtw_mi_report_survey_event(_adapter *adapter, void *data)
+{
+	union recv_frame *precv_frame = (union recv_frame *)data;
+
+	report_survey_event(adapter, precv_frame);
+	return _TRUE;
+}
+u8 rtw_mi_report_survey_event(_adapter *padapter, union recv_frame *precv_frame)
+{
+	return _rtw_mi_process(padapter, _FALSE, precv_frame, _rtw_mi_report_survey_event);
+}
+u8 rtw_mi_buddy_report_survey_event(_adapter *padapter, union recv_frame *precv_frame)
+{
+	return _rtw_mi_process(padapter, _TRUE, precv_frame, _rtw_mi_report_survey_event);
+}
+
+static u8 _rtw_mi_sreset_adapter_hdl(_adapter *adapter, void *data)
+{
+	u8 bstart = *(u8 *)data;
+
+	if (bstart)
+		sreset_start_adapter(adapter);
+	else
+		sreset_stop_adapter(adapter);
+	return _TRUE;
+}
+u8 rtw_mi_sreset_adapter_hdl(_adapter *padapter, u8 bstart)
+{
+	u8 in_data = bstart;
+
+	return _rtw_mi_process(padapter, _FALSE, &in_data, _rtw_mi_sreset_adapter_hdl);
+}
+
+#if defined(DBG_CONFIG_ERROR_RESET) && defined(CONFIG_CONCURRENT_MODE)
+void rtw_mi_ap_info_restore(_adapter *adapter)
+{
+	int i;
+	_adapter *iface;
+	struct mlme_priv *pmlmepriv;
+	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
+
+	for (i = 0; i < dvobj->iface_nums; i++) {
+		iface = dvobj->padapters[i];
+		if (iface) {
+			pmlmepriv = &iface->mlmepriv;
+
+			if (MLME_IS_AP(iface) || MLME_IS_MESH(iface)) {
+				RTW_INFO(FUNC_ADPT_FMT" %s\n", FUNC_ADPT_ARG(iface), MLME_IS_AP(iface) ? "AP" : "MESH");
+				rtw_iface_bcmc_sec_cam_map_restore(iface);
+			}
+		}
+	}
+}
+#endif /*#if defined(DBG_CONFIG_ERROR_RESET) && defined(CONFIG_CONCURRENT_MODE)*/
+
+u8 rtw_mi_buddy_sreset_adapter_hdl(_adapter *padapter, u8 bstart)
+{
+	u8 in_data = bstart;
+
+	return _rtw_mi_process(padapter, _TRUE, &in_data, _rtw_mi_sreset_adapter_hdl);
+}
+static u8 _rtw_mi_tx_beacon_hdl(_adapter *adapter, void *data)
+{
+	if ((MLME_IS_AP(adapter) || MLME_IS_MESH(adapter))
+		&& check_fwstate(&adapter->mlmepriv, WIFI_ASOC_STATE) == _TRUE
+	) {
+		adapter->mlmepriv.update_bcn = _TRUE;
+#ifndef CONFIG_INTERRUPT_BASED_TXBCN
+#if defined(CONFIG_USB_HCI) || defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
+		tx_beacon_hdl(adapter, NULL);
+#endif
+#endif
+	}
+	return _TRUE;
+}
+u8 rtw_mi_tx_beacon_hdl(_adapter *padapter)
+{
+	return _rtw_mi_process(padapter, _FALSE, NULL, _rtw_mi_tx_beacon_hdl);
+}
+u8 rtw_mi_buddy_tx_beacon_hdl(_adapter *padapter)
+{
+	return _rtw_mi_process(padapter, _TRUE, NULL, _rtw_mi_sreset_adapter_hdl);
+}
+
+static u8 _rtw_mi_set_tx_beacon_cmd(_adapter *adapter, void *data)
+{
+	struct mlme_priv *pmlmepriv = &adapter->mlmepriv;
+
+	if (MLME_IS_AP(adapter) || MLME_IS_MESH(adapter)) {
+		if (pmlmepriv->update_bcn == _TRUE)
+			set_tx_beacon_cmd(adapter);
+	}
+	return _TRUE;
+}
+u8 rtw_mi_set_tx_beacon_cmd(_adapter *padapter)
+{
+	return _rtw_mi_process(padapter, _FALSE, NULL, _rtw_mi_set_tx_beacon_cmd);
+}
+u8 rtw_mi_buddy_set_tx_beacon_cmd(_adapter *padapter)
+{
+	return _rtw_mi_process(padapter, _TRUE, NULL, _rtw_mi_set_tx_beacon_cmd);
+}
+
+#ifdef CONFIG_P2P
+static u8 _rtw_mi_p2p_chk_state(_adapter *adapter, void *data)
+{
+	struct wifidirect_info *pwdinfo = &(adapter->wdinfo);
+	enum P2P_STATE state = *(enum P2P_STATE *)data;
+
+	return rtw_p2p_chk_state(pwdinfo, state);
+}
+u8 rtw_mi_p2p_chk_state(_adapter *padapter, enum P2P_STATE p2p_state)
+{
+	u8 in_data = p2p_state;
+
+	return _rtw_mi_process(padapter, _FALSE, &in_data, _rtw_mi_p2p_chk_state);
+}
+u8 rtw_mi_buddy_p2p_chk_state(_adapter *padapter, enum P2P_STATE p2p_state)
+{
+	u8 in_data  = p2p_state;
+
+	return _rtw_mi_process(padapter, _TRUE, &in_data, _rtw_mi_p2p_chk_state);
+}
+static u8 _rtw_mi_stay_in_p2p_mode(_adapter *adapter, void *data)
+{
+	struct wifidirect_info *pwdinfo = &(adapter->wdinfo);
+
+	if (rtw_p2p_role(pwdinfo) != P2P_ROLE_DISABLE)
+		return _TRUE;
+	return _FALSE;
+}
+u8 rtw_mi_stay_in_p2p_mode(_adapter *padapter)
+{
+	return _rtw_mi_process(padapter, _FALSE, NULL, _rtw_mi_stay_in_p2p_mode);
+}
+u8 rtw_mi_buddy_stay_in_p2p_mode(_adapter *padapter)
+{
+	return _rtw_mi_process(padapter, _TRUE, NULL, _rtw_mi_stay_in_p2p_mode);
+}
+#endif /*CONFIG_P2P*/
+
+_adapter *rtw_get_iface_by_id(_adapter *padapter, u8 iface_id)
+{
+	_adapter *iface = NULL;
+	struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
+
+	if ((padapter == NULL) || (iface_id >= CONFIG_IFACE_NUMBER)) {
+		rtw_warn_on(1);
+		return iface;
+	}
+
+	return  dvobj->padapters[iface_id];
+}
+
+_adapter *rtw_get_iface_by_macddr(_adapter *padapter, const u8 *mac_addr)
+{
+	int i;
+	_adapter *iface = NULL;
+	u8 bmatch = _FALSE;
+	struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
+
+	for (i = 0; i < dvobj->iface_nums; i++) {
+		iface = dvobj->padapters[i];
+		if ((iface) && (_rtw_memcmp(mac_addr, adapter_mac_addr(iface), ETH_ALEN))) {
+			bmatch = _TRUE;
+			break;
+		}
+	}
+	if (bmatch)
+		return iface;
+	else
+		return NULL;
+}
+
+_adapter *rtw_get_iface_by_hwport(_adapter *padapter, u8 hw_port)
+{
+	int i;
+	_adapter *iface = NULL;
+	u8 bmatch = _FALSE;
+	struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
+
+	for (i = 0; i < dvobj->iface_nums; i++) {
+		iface = dvobj->padapters[i];
+		if ((iface) && (hw_port == iface->hw_port)) {
+			bmatch = _TRUE;
+			break;
+		}
+	}
+	if (bmatch)
+		return iface;
+	else
+		return NULL;
+}
+
+/*#define CONFIG_SKB_ALLOCATED*/
+#define DBG_SKB_PROCESS
+#ifdef DBG_SKB_PROCESS
+void rtw_dbg_skb_process(_adapter *padapter, union recv_frame *precvframe, union recv_frame *pcloneframe)
+{
+	_pkt *pkt_copy, *pkt_org;
+
+	pkt_org = precvframe->u.hdr.pkt;
+	pkt_copy = pcloneframe->u.hdr.pkt;
+	/*
+		RTW_INFO("%s ===== ORG SKB =====\n", __func__);
+		RTW_INFO(" SKB head(%p)\n", pkt_org->head);
+		RTW_INFO(" SKB data(%p)\n", pkt_org->data);
+		RTW_INFO(" SKB tail(%p)\n", pkt_org->tail);
+		RTW_INFO(" SKB end(%p)\n", pkt_org->end);
+
+		RTW_INFO(" recv frame head(%p)\n", precvframe->u.hdr.rx_head);
+		RTW_INFO(" recv frame data(%p)\n", precvframe->u.hdr.rx_data);
+		RTW_INFO(" recv frame tail(%p)\n", precvframe->u.hdr.rx_tail);
+		RTW_INFO(" recv frame end(%p)\n", precvframe->u.hdr.rx_end);
+
+		RTW_INFO("%s ===== COPY SKB =====\n", __func__);
+		RTW_INFO(" SKB head(%p)\n", pkt_copy->head);
+		RTW_INFO(" SKB data(%p)\n", pkt_copy->data);
+		RTW_INFO(" SKB tail(%p)\n", pkt_copy->tail);
+		RTW_INFO(" SKB end(%p)\n", pkt_copy->end);
+
+		RTW_INFO(" recv frame head(%p)\n", pcloneframe->u.hdr.rx_head);
+		RTW_INFO(" recv frame data(%p)\n", pcloneframe->u.hdr.rx_data);
+		RTW_INFO(" recv frame tail(%p)\n", pcloneframe->u.hdr.rx_tail);
+		RTW_INFO(" recv frame end(%p)\n", pcloneframe->u.hdr.rx_end);
+	*/
+	/*
+		RTW_INFO("%s => recv_frame adapter(%p,%p)\n", __func__, precvframe->u.hdr.adapter, pcloneframe->u.hdr.adapter);
+		RTW_INFO("%s => recv_frame dev(%p,%p)\n", __func__, pkt_org->dev , pkt_copy->dev);
+		RTW_INFO("%s => recv_frame len(%d,%d)\n", __func__, precvframe->u.hdr.len, pcloneframe->u.hdr.len);
+	*/
+	if (precvframe->u.hdr.len != pcloneframe->u.hdr.len)
+		RTW_INFO("%s [WARN]  recv_frame length(%d:%d) compare failed\n", __func__, precvframe->u.hdr.len, pcloneframe->u.hdr.len);
+
+	if (_rtw_memcmp(&precvframe->u.hdr.attrib, &pcloneframe->u.hdr.attrib, sizeof(struct rx_pkt_attrib)) == _FALSE)
+		RTW_INFO("%s [WARN]  recv_frame attrib compare failed\n", __func__);
+
+	if (_rtw_memcmp(precvframe->u.hdr.rx_data, pcloneframe->u.hdr.rx_data, precvframe->u.hdr.len) == _FALSE)
+		RTW_INFO("%s [WARN]  recv_frame rx_data compare failed\n", __func__);
+
+}
+#endif
+
+static s32 _rtw_mi_buddy_clone_bcmc_packet(_adapter *adapter, union recv_frame *precvframe, u8 *pphy_status, union recv_frame *pcloneframe)
+{
+	s32 ret = _SUCCESS;
+#ifdef CONFIG_SKB_ALLOCATED
+	u8 *pbuf = precvframe->u.hdr.rx_data;
+#endif
+	struct rx_pkt_attrib *pattrib = NULL;
+
+	if (pcloneframe) {
+		pcloneframe->u.hdr.adapter = adapter;
+
+		_rtw_init_listhead(&pcloneframe->u.hdr.list);
+		pcloneframe->u.hdr.precvbuf = NULL;	/*can't access the precvbuf for new arch.*/
+		pcloneframe->u.hdr.len = 0;
+
+		_rtw_memcpy(&pcloneframe->u.hdr.attrib, &precvframe->u.hdr.attrib, sizeof(struct rx_pkt_attrib));
+
+		pattrib = &pcloneframe->u.hdr.attrib;
+#ifdef CONFIG_SKB_ALLOCATED
+		if (rtw_os_alloc_recvframe(adapter, pcloneframe, pbuf, NULL) == _SUCCESS)
+#else
+		if (rtw_os_recvframe_duplicate_skb(adapter, pcloneframe, precvframe->u.hdr.pkt) == _SUCCESS)
+#endif
+		{
+#ifdef CONFIG_SKB_ALLOCATED
+			recvframe_put(pcloneframe, pattrib->pkt_len);
+#endif
+
+#ifdef DBG_SKB_PROCESS
+			rtw_dbg_skb_process(adapter, precvframe, pcloneframe);
+#endif
+
+			if (pphy_status)
+				rx_query_phy_status(pcloneframe, pphy_status);
+
+			ret = rtw_recv_entry(pcloneframe);
+		} else {
+			ret = -1;
+			RTW_INFO("%s()-%d: rtw_os_alloc_recvframe() failed!\n", __func__, __LINE__);
+		}
+
+	}
+	return ret;
+}
+
+void rtw_mi_buddy_clone_bcmc_packet(_adapter *padapter, union recv_frame *precvframe, u8 *pphy_status)
+{
+	int i;
+	s32 ret = _SUCCESS;
+	_adapter *iface = NULL;
+	union recv_frame *pcloneframe = NULL;
+	struct recv_priv *precvpriv = &padapter->recvpriv;/*primary_padapter*/
+	_queue *pfree_recv_queue = &precvpriv->free_recv_queue;
+	struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
+	u8 *fhead = get_recvframe_data(precvframe);
+	u8 type = GetFrameType(fhead);
+
+	for (i = 0; i < dvobj->iface_nums; i++) {
+		iface = dvobj->padapters[i];
+		if (!iface || iface == padapter)
+			continue;
+		if (rtw_is_adapter_up(iface) == _FALSE || iface->registered == 0)
+			continue;
+		if (type == WIFI_DATA_TYPE && !adapter_allow_bmc_data_rx(iface))
+			continue;
+
+		pcloneframe = rtw_alloc_recvframe(pfree_recv_queue);
+		if (pcloneframe) {
+			ret = _rtw_mi_buddy_clone_bcmc_packet(iface, precvframe, pphy_status, pcloneframe);
+			if (_SUCCESS != ret) {
+				if (ret == -1)
+					rtw_free_recvframe(pcloneframe, pfree_recv_queue);
+				/*RTW_INFO(ADPT_FMT"-clone BC/MC frame failed\n", ADPT_ARG(iface));*/
+			}
+		}
+	}
+
+}
+
+#ifdef CONFIG_PCI_HCI
+/*API be created temporary for MI, caller is interrupt-handler, PCIE's interrupt handler cannot apply to multi-AP*/
+_adapter *rtw_mi_get_ap_adapter(_adapter *padapter)
+{
+	struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
+	int i;
+	_adapter *iface = NULL;
+
+	for (i = 0; i < dvobj->iface_nums; i++) {
+		iface = dvobj->padapters[i];
+		if (!iface)
+			continue;
+
+		if (check_fwstate(&iface->mlmepriv, WIFI_AP_STATE) == _TRUE
+		    && check_fwstate(&iface->mlmepriv, WIFI_ASOC_STATE) == _TRUE)
+			break;
+
+	}
+	return iface;
+}
+#endif
+
+u8 rtw_mi_get_ld_sta_ifbmp(_adapter *adapter)
+{
+	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
+	int i;
+	_adapter *iface = NULL;
+	u8 ifbmp = 0;
+
+	for (i = 0; i < dvobj->iface_nums; i++) {
+		iface = dvobj->padapters[i];
+		if (!iface)
+			continue;
+
+		if (MLME_IS_STA(iface) && MLME_IS_ASOC(iface))
+			ifbmp |= BIT(i);
+	}
+
+	return ifbmp;
+}
+
+u8 rtw_mi_get_ap_mesh_ifbmp(_adapter *adapter)
+{
+	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
+	int i;
+	_adapter *iface = NULL;
+	u8 ifbmp = 0;
+
+	for (i = 0; i < dvobj->iface_nums; i++) {
+		iface = dvobj->padapters[i];
+		if (!iface)
+			continue;
+
+		if (CHK_MLME_STATE(iface, WIFI_AP_STATE | WIFI_MESH_STATE)
+			&& MLME_IS_ASOC(iface))
+			ifbmp |= BIT(i);
+	}
+
+	return ifbmp;
+}
+
+void rtw_mi_update_ap_bmc_camid(_adapter *padapter, u8 camid_a, u8 camid_b)
+{
+#ifdef CONFIG_CONCURRENT_MODE
+	struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
+	struct macid_ctl_t *macid_ctl = dvobj_to_macidctl(dvobj);
+
+	int i;
+	_adapter *iface = NULL;
+
+	for (i = 0; i < dvobj->iface_nums; i++) {
+		iface = dvobj->padapters[i];
+		if (!iface)
+			continue;
+
+		if (macid_ctl->iface_bmc[iface->iface_id] != INVALID_SEC_MAC_CAM_ID) {
+			if (macid_ctl->iface_bmc[iface->iface_id] == camid_a)
+				macid_ctl->iface_bmc[iface->iface_id] = camid_b;
+			else if (macid_ctl->iface_bmc[iface->iface_id] == camid_b)
+				macid_ctl->iface_bmc[iface->iface_id] = camid_a;
+			iface->securitypriv.dot118021x_bmc_cam_id  = macid_ctl->iface_bmc[iface->iface_id];
+		}
+	}
+#endif
+}
+
+u8 rtw_mi_get_assoc_if_num(_adapter *adapter)
+{
+	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
+	u8 n_assoc_iface = 0;
+#if 1
+	u8 i;
+
+	for (i = 0; i < dvobj->iface_nums; i++) {
+		if (check_fwstate(&(dvobj->padapters[i]->mlmepriv), WIFI_ASOC_STATE))
+			n_assoc_iface++;
+	}
+#else
+	n_assoc_iface = DEV_STA_LD_NUM(dvobj) + DEV_AP_NUM(dvobj) + DEV_ADHOC_NUM(dvobj) + DEV_MESH_NUM(dvobj);
+#endif
+	return n_assoc_iface;
+}
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/core/rtw_mlme.c linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/core/rtw_mlme.c
--- linux-5.6.3/3rdparty/rtl8821ce/core/rtw_mlme.c	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/core/rtw_mlme.c	2020-04-10 16:35:06.774658107 +0300
@@ -0,0 +1,5319 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#define _RTW_MLME_C_
+
+#include <hal_data.h>
+
+extern void indicate_wx_scan_complete_event(_adapter *padapter);
+extern u8 rtw_do_join(_adapter *padapter);
+
+
+void rtw_init_mlme_timer(_adapter *padapter)
+{
+	struct	mlme_priv *pmlmepriv = &padapter->mlmepriv;
+
+	rtw_init_timer(&(pmlmepriv->assoc_timer), padapter, rtw_join_timeout_handler, padapter);
+	rtw_init_timer(&(pmlmepriv->scan_to_timer), padapter, rtw_scan_timeout_handler, padapter);
+
+#ifdef CONFIG_SET_SCAN_DENY_TIMER
+	rtw_init_timer(&(pmlmepriv->set_scan_deny_timer), padapter, rtw_set_scan_deny_timer_hdl, padapter);
+#endif
+
+#ifdef RTK_DMP_PLATFORM
+	_init_workitem(&(pmlmepriv->Linkup_workitem), Linkup_workitem_callback, padapter);
+	_init_workitem(&(pmlmepriv->Linkdown_workitem), Linkdown_workitem_callback, padapter);
+#endif
+}
+
+sint	_rtw_init_mlme_priv(_adapter *padapter)
+{
+	sint	i;
+	u8	*pbuf;
+	struct wlan_network	*pnetwork;
+	struct mlme_priv		*pmlmepriv = &padapter->mlmepriv;
+	struct rf_ctl_t *rfctl = adapter_to_rfctl(padapter);
+	sint	res = _SUCCESS;
+
+
+	/* We don't need to memset padapter->XXX to zero, because adapter is allocated by rtw_zvmalloc(). */
+	/* _rtw_memset((u8 *)pmlmepriv, 0, sizeof(struct mlme_priv)); */
+
+
+	/*qos_priv*/
+	/*pmlmepriv->qospriv.qos_option = pregistrypriv->wmm_enable;*/
+
+	/*ht_priv*/
+#ifdef CONFIG_80211N_HT
+	pmlmepriv->htpriv.ampdu_enable = _FALSE;/*set to disabled*/
+#endif
+
+	pmlmepriv->nic_hdl = (u8 *)padapter;
+
+	pmlmepriv->pscanned = NULL;
+	init_fwstate(pmlmepriv, WIFI_STATION_STATE);
+	pmlmepriv->cur_network.network.InfrastructureMode = Ndis802_11AutoUnknown;
+	pmlmepriv->scan_mode = SCAN_ACTIVE; /* 1: active, 0: pasive. Maybe someday we should rename this varable to "active_mode" (Jeff) */
+
+	_rtw_spinlock_init(&(pmlmepriv->lock));
+	_rtw_init_queue(&(pmlmepriv->free_bss_pool));
+	_rtw_init_queue(&(pmlmepriv->scanned_queue));
+
+	set_scanned_network_val(pmlmepriv, 0);
+
+	_rtw_memset(&pmlmepriv->assoc_ssid, 0, sizeof(NDIS_802_11_SSID));
+
+	if (padapter->registrypriv.max_bss_cnt != 0)
+		pmlmepriv->max_bss_cnt = padapter->registrypriv.max_bss_cnt;
+	else if (rfctl->max_chan_nums <= MAX_CHANNEL_NUM_2G)
+		pmlmepriv->max_bss_cnt = MAX_BSS_CNT;
+	else
+		pmlmepriv->max_bss_cnt = MAX_BSS_CNT + MAX_BSS_CNT;
+
+
+	pbuf = rtw_zvmalloc(pmlmepriv->max_bss_cnt * (sizeof(struct wlan_network)));
+
+	if (pbuf == NULL) {
+		res = _FAIL;
+		goto exit;
+	}
+	pmlmepriv->free_bss_buf = pbuf;
+
+	pnetwork = (struct wlan_network *)pbuf;
+
+	for (i = 0; i < pmlmepriv->max_bss_cnt; i++) {
+		_rtw_init_listhead(&(pnetwork->list));
+
+		rtw_list_insert_tail(&(pnetwork->list), &(pmlmepriv->free_bss_pool.queue));
+
+		pnetwork++;
+	}
+
+	/* allocate DMA-able/Non-Page memory for cmd_buf and rsp_buf */
+
+	rtw_clear_scan_deny(padapter);
+#ifdef CONFIG_ARP_KEEP_ALIVE
+	pmlmepriv->bGetGateway = 0;
+	pmlmepriv->GetGatewayTryCnt = 0;
+#endif
+
+#ifdef CONFIG_LAYER2_ROAMING
+#define RTW_ROAM_SCAN_RESULT_EXP_MS (5*1000)
+#define RTW_ROAM_RSSI_DIFF_TH 10
+#define RTW_ROAM_SCAN_INTERVAL (5)    /* 5*(2 second)*/
+#define RTW_ROAM_RSSI_THRESHOLD 70
+
+	pmlmepriv->roam_flags = 0
+				| RTW_ROAM_ON_EXPIRED
+#ifdef CONFIG_LAYER2_ROAMING_RESUME
+				| RTW_ROAM_ON_RESUME
+#endif
+#ifdef CONFIG_LAYER2_ROAMING_ACTIVE
+				| RTW_ROAM_ACTIVE
+#endif
+				;
+
+	pmlmepriv->roam_scanr_exp_ms = RTW_ROAM_SCAN_RESULT_EXP_MS;
+	pmlmepriv->roam_rssi_diff_th = RTW_ROAM_RSSI_DIFF_TH;
+	pmlmepriv->roam_scan_int 	 = RTW_ROAM_SCAN_INTERVAL;
+	pmlmepriv->roam_rssi_threshold = RTW_ROAM_RSSI_THRESHOLD;
+	pmlmepriv->need_to_roam = _FALSE;
+	pmlmepriv->last_roaming = rtw_get_current_time();
+#endif /* CONFIG_LAYER2_ROAMING */
+
+#ifdef CONFIG_RTW_80211R
+	rtw_ft_info_init(&pmlmepriv->ft_roam);
+#endif
+#ifdef CONFIG_LAYER2_ROAMING
+#if defined(CONFIG_RTW_WNM) || defined(CONFIG_RTW_80211K)
+	rtw_roam_nb_info_init(padapter);
+	pmlmepriv->ch_cnt = 0;
+#endif	
+#endif
+	rtw_init_mlme_timer(padapter);
+
+exit:
+
+
+	return res;
+}
+
+void rtw_mfree_mlme_priv_lock(struct mlme_priv *pmlmepriv);
+void rtw_mfree_mlme_priv_lock(struct mlme_priv *pmlmepriv)
+{
+	_rtw_spinlock_free(&pmlmepriv->lock);
+	_rtw_spinlock_free(&(pmlmepriv->free_bss_pool.lock));
+	_rtw_spinlock_free(&(pmlmepriv->scanned_queue.lock));
+}
+
+static void rtw_free_mlme_ie_data(u8 **ppie, u32 *plen)
+{
+	if (*ppie) {
+		rtw_mfree(*ppie, *plen);
+		*plen = 0;
+		*ppie = NULL;
+	}
+}
+
+void rtw_free_mlme_priv_ie_data(struct mlme_priv *pmlmepriv)
+{
+#if defined(CONFIG_AP_MODE) && defined (CONFIG_NATIVEAP_MLME)
+	rtw_buf_free(&pmlmepriv->assoc_req, &pmlmepriv->assoc_req_len);
+	rtw_buf_free(&pmlmepriv->assoc_rsp, &pmlmepriv->assoc_rsp_len);
+	rtw_free_mlme_ie_data(&pmlmepriv->wps_beacon_ie, &pmlmepriv->wps_beacon_ie_len);
+	rtw_free_mlme_ie_data(&pmlmepriv->wps_probe_req_ie, &pmlmepriv->wps_probe_req_ie_len);
+	rtw_free_mlme_ie_data(&pmlmepriv->wps_probe_resp_ie, &pmlmepriv->wps_probe_resp_ie_len);
+	rtw_free_mlme_ie_data(&pmlmepriv->wps_assoc_resp_ie, &pmlmepriv->wps_assoc_resp_ie_len);
+
+	rtw_free_mlme_ie_data(&pmlmepriv->p2p_beacon_ie, &pmlmepriv->p2p_beacon_ie_len);
+	rtw_free_mlme_ie_data(&pmlmepriv->p2p_probe_req_ie, &pmlmepriv->p2p_probe_req_ie_len);
+	rtw_free_mlme_ie_data(&pmlmepriv->p2p_probe_resp_ie, &pmlmepriv->p2p_probe_resp_ie_len);
+	rtw_free_mlme_ie_data(&pmlmepriv->p2p_go_probe_resp_ie, &pmlmepriv->p2p_go_probe_resp_ie_len);
+	rtw_free_mlme_ie_data(&pmlmepriv->p2p_assoc_req_ie, &pmlmepriv->p2p_assoc_req_ie_len);
+	rtw_free_mlme_ie_data(&pmlmepriv->p2p_assoc_resp_ie, &pmlmepriv->p2p_assoc_resp_ie_len);
+#endif
+
+#if defined(CONFIG_WFD) && defined(CONFIG_IOCTL_CFG80211)
+	rtw_free_mlme_ie_data(&pmlmepriv->wfd_beacon_ie, &pmlmepriv->wfd_beacon_ie_len);
+	rtw_free_mlme_ie_data(&pmlmepriv->wfd_probe_req_ie, &pmlmepriv->wfd_probe_req_ie_len);
+	rtw_free_mlme_ie_data(&pmlmepriv->wfd_probe_resp_ie, &pmlmepriv->wfd_probe_resp_ie_len);
+	rtw_free_mlme_ie_data(&pmlmepriv->wfd_go_probe_resp_ie, &pmlmepriv->wfd_go_probe_resp_ie_len);
+	rtw_free_mlme_ie_data(&pmlmepriv->wfd_assoc_req_ie, &pmlmepriv->wfd_assoc_req_ie_len);
+	rtw_free_mlme_ie_data(&pmlmepriv->wfd_assoc_resp_ie, &pmlmepriv->wfd_assoc_resp_ie_len);
+#endif
+
+#ifdef CONFIG_RTW_80211R
+	rtw_free_mlme_ie_data(&pmlmepriv->auth_rsp, &pmlmepriv->auth_rsp_len);
+#endif
+}
+
+#if defined(CONFIG_WFD) && defined(CONFIG_IOCTL_CFG80211)
+int rtw_mlme_update_wfd_ie_data(struct mlme_priv *mlme, u8 type, u8 *ie, u32 ie_len)
+{
+	_adapter *adapter = mlme_to_adapter(mlme);
+	struct wifi_display_info *wfd_info = &adapter->wfd_info;
+	u8 clear = 0;
+	u8 **t_ie = NULL;
+	u32 *t_ie_len = NULL;
+	int ret = _FAIL;
+
+	if (!hal_chk_wl_func(adapter, WL_FUNC_MIRACAST))
+		goto success;
+
+	if (wfd_info->wfd_enable == _TRUE)
+		goto success; /* WFD IE is build by self */
+
+	if (!ie && !ie_len)
+		clear = 1;
+	else if (!ie || !ie_len) {
+		RTW_PRINT(FUNC_ADPT_FMT" type:%u, ie:%p, ie_len:%u"
+			  , FUNC_ADPT_ARG(adapter), type, ie, ie_len);
+		rtw_warn_on(1);
+		goto exit;
+	}
+
+	switch (type) {
+	case MLME_BEACON_IE:
+		t_ie = &mlme->wfd_beacon_ie;
+		t_ie_len = &mlme->wfd_beacon_ie_len;
+		break;
+	case MLME_PROBE_REQ_IE:
+		t_ie = &mlme->wfd_probe_req_ie;
+		t_ie_len = &mlme->wfd_probe_req_ie_len;
+		break;
+	case MLME_PROBE_RESP_IE:
+		t_ie = &mlme->wfd_probe_resp_ie;
+		t_ie_len = &mlme->wfd_probe_resp_ie_len;
+		break;
+	case MLME_GO_PROBE_RESP_IE:
+		t_ie = &mlme->wfd_go_probe_resp_ie;
+		t_ie_len = &mlme->wfd_go_probe_resp_ie_len;
+		break;
+	case MLME_ASSOC_REQ_IE:
+		t_ie = &mlme->wfd_assoc_req_ie;
+		t_ie_len = &mlme->wfd_assoc_req_ie_len;
+		break;
+	case MLME_ASSOC_RESP_IE:
+		t_ie = &mlme->wfd_assoc_resp_ie;
+		t_ie_len = &mlme->wfd_assoc_resp_ie_len;
+		break;
+	default:
+		RTW_PRINT(FUNC_ADPT_FMT" unsupported type:%u"
+			  , FUNC_ADPT_ARG(adapter), type);
+		rtw_warn_on(1);
+		goto exit;
+	}
+
+	if (*t_ie) {
+		u32 free_len = *t_ie_len;
+		*t_ie_len = 0;
+		rtw_mfree(*t_ie, free_len);
+		*t_ie = NULL;
+	}
+
+	if (!clear) {
+		*t_ie = rtw_malloc(ie_len);
+		if (*t_ie == NULL) {
+			RTW_ERR(FUNC_ADPT_FMT" type:%u, rtw_malloc() fail\n"
+				, FUNC_ADPT_ARG(adapter), type);
+			goto exit;
+		}
+		_rtw_memcpy(*t_ie, ie, ie_len);
+		*t_ie_len = ie_len;
+	}
+
+	if (*t_ie && *t_ie_len) {
+		u8 *attr_content;
+		u32 attr_contentlen = 0;
+
+		attr_content = rtw_get_wfd_attr_content(*t_ie, *t_ie_len, WFD_ATTR_DEVICE_INFO, NULL, &attr_contentlen);
+		if (attr_content && attr_contentlen) {
+			if (RTW_GET_BE16(attr_content + 2) != wfd_info->rtsp_ctrlport) {
+				wfd_info->rtsp_ctrlport = RTW_GET_BE16(attr_content + 2);
+				RTW_INFO(FUNC_ADPT_FMT" type:%u, RTSP CTRL port = %u\n"
+					, FUNC_ADPT_ARG(adapter), type, wfd_info->rtsp_ctrlport);
+			}
+		}
+	}
+
+success:
+	ret = _SUCCESS;
+
+exit:
+	return ret;
+}
+#endif /* defined(CONFIG_WFD) && defined(CONFIG_IOCTL_CFG80211) */
+
+void _rtw_free_mlme_priv(struct mlme_priv *pmlmepriv)
+{
+	_adapter *adapter = mlme_to_adapter(pmlmepriv);
+	if (NULL == pmlmepriv) {
+		rtw_warn_on(1);
+		goto exit;
+	}
+	rtw_free_mlme_priv_ie_data(pmlmepriv);
+
+	if (pmlmepriv) {
+		rtw_mfree_mlme_priv_lock(pmlmepriv);
+
+		if (pmlmepriv->free_bss_buf)
+			rtw_vmfree(pmlmepriv->free_bss_buf, pmlmepriv->max_bss_cnt * sizeof(struct wlan_network));
+	}
+exit:
+	return;
+}
+
+sint	_rtw_enqueue_network(_queue *queue, struct wlan_network *pnetwork)
+{
+	_irqL irqL;
+
+
+	if (pnetwork == NULL)
+		goto exit;
+
+	_enter_critical_bh(&queue->lock, &irqL);
+
+	rtw_list_insert_tail(&pnetwork->list, &queue->queue);
+
+	_exit_critical_bh(&queue->lock, &irqL);
+
+exit:
+
+
+	return _SUCCESS;
+}
+
+/*
+struct	wlan_network *_rtw_dequeue_network(_queue *queue)
+{
+	_irqL irqL;
+
+	struct wlan_network *pnetwork;
+
+
+	_enter_critical_bh(&queue->lock, &irqL);
+
+	if (_rtw_queue_empty(queue) == _TRUE)
+
+		pnetwork = NULL;
+
+	else
+	{
+		pnetwork = LIST_CONTAINOR(get_next(&queue->queue), struct wlan_network, list);
+
+		rtw_list_delete(&(pnetwork->list));
+	}
+
+	_exit_critical_bh(&queue->lock, &irqL);
+
+
+	return pnetwork;
+}
+*/
+
+struct	wlan_network *_rtw_alloc_network(struct	mlme_priv *pmlmepriv) /* (_queue *free_queue) */
+{
+	_irqL	irqL;
+	struct	wlan_network	*pnetwork;
+	_queue *free_queue = &pmlmepriv->free_bss_pool;
+	_list *plist = NULL;
+
+
+	_enter_critical_bh(&free_queue->lock, &irqL);
+
+	if (_rtw_queue_empty(free_queue) == _TRUE) {
+		pnetwork = NULL;
+		goto exit;
+	}
+	plist = get_next(&(free_queue->queue));
+
+	pnetwork = LIST_CONTAINOR(plist , struct wlan_network, list);
+
+	rtw_list_delete(&pnetwork->list);
+
+	pnetwork->network_type = 0;
+	pnetwork->fixed = _FALSE;
+	pnetwork->last_scanned = rtw_get_current_time();
+#if defined(CONFIG_RTW_MESH) && CONFIG_RTW_MESH_ACNODE_PREVENT
+	pnetwork->acnode_stime = 0;
+	pnetwork->acnode_notify_etime = 0;
+#endif
+
+	pnetwork->aid = 0;
+	pnetwork->join_res = 0;
+
+	pmlmepriv->num_of_scanned++;
+
+exit:
+	_exit_critical_bh(&free_queue->lock, &irqL);
+
+
+	return pnetwork;
+}
+
+void _rtw_free_network(struct	mlme_priv *pmlmepriv , struct wlan_network *pnetwork, u8 isfreeall)
+{
+	u32 delta_time;
+	u32 lifetime = SCANQUEUE_LIFETIME;
+	_irqL irqL;
+	_queue *free_queue = &(pmlmepriv->free_bss_pool);
+
+
+	if (pnetwork == NULL)
+		goto exit;
+
+	if (pnetwork->fixed == _TRUE)
+		goto exit;
+
+	if ((check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE) == _TRUE) ||
+	    (check_fwstate(pmlmepriv, WIFI_ADHOC_STATE) == _TRUE))
+		lifetime = 1;
+
+	if (!isfreeall) {
+		delta_time = (u32) rtw_get_passing_time_ms(pnetwork->last_scanned);
+		if (delta_time < lifetime) /* unit:msec */
+			goto exit;
+	}
+
+	_enter_critical_bh(&free_queue->lock, &irqL);
+
+	rtw_list_delete(&(pnetwork->list));
+
+	rtw_list_insert_tail(&(pnetwork->list), &(free_queue->queue));
+
+	pmlmepriv->num_of_scanned--;
+
+
+	/* RTW_INFO("_rtw_free_network:SSID=%s\n", pnetwork->network.Ssid.Ssid); */
+
+	_exit_critical_bh(&free_queue->lock, &irqL);
+
+exit:
+	return;
+}
+
+void _rtw_free_network_nolock(struct	mlme_priv *pmlmepriv, struct wlan_network *pnetwork)
+{
+
+	_queue *free_queue = &(pmlmepriv->free_bss_pool);
+
+
+	if (pnetwork == NULL)
+		goto exit;
+
+	if (pnetwork->fixed == _TRUE)
+		goto exit;
+
+	/* _enter_critical(&free_queue->lock, &irqL); */
+
+	rtw_list_delete(&(pnetwork->list));
+
+	rtw_list_insert_tail(&(pnetwork->list), get_list_head(free_queue));
+
+	pmlmepriv->num_of_scanned--;
+
+	/* _exit_critical(&free_queue->lock, &irqL); */
+
+exit:
+	return;
+}
+
+void _rtw_free_network_queue(_adapter *padapter, u8 isfreeall)
+{
+	_irqL irqL;
+	_list *phead, *plist;
+	struct wlan_network *pnetwork;
+	struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
+	_queue *scanned_queue = &pmlmepriv->scanned_queue;
+
+
+
+	_enter_critical_bh(&scanned_queue->lock, &irqL);
+
+	phead = get_list_head(scanned_queue);
+	plist = get_next(phead);
+
+	while (rtw_end_of_queue_search(phead, plist) == _FALSE) {
+
+		pnetwork = LIST_CONTAINOR(plist, struct wlan_network, list);
+
+		plist = get_next(plist);
+
+		_rtw_free_network(pmlmepriv, pnetwork, isfreeall);
+
+	}
+
+	_exit_critical_bh(&scanned_queue->lock, &irqL);
+
+
+}
+
+
+
+
+sint rtw_if_up(_adapter *padapter)
+{
+
+	sint res;
+
+	if (RTW_CANNOT_RUN(padapter) ||
+	    (check_fwstate(&padapter->mlmepriv, _FW_LINKED) == _FALSE)) {
+		res = _FALSE;
+	} else
+		res =  _TRUE;
+
+	return res;
+}
+
+
+void rtw_generate_random_ibss(u8 *pibss)
+{
+	*((u32 *)(&pibss[2])) = rtw_random32();
+	pibss[0] = 0x02; /* in ad-hoc mode local bit must set to 1 */
+	pibss[1] = 0x11;
+	pibss[2] = 0x87;
+}
+
+u8 *rtw_get_capability_from_ie(u8 *ie)
+{
+	return ie + 8 + 2;
+}
+
+
+u16 rtw_get_capability(WLAN_BSSID_EX *bss)
+{
+	u16	val;
+
+	_rtw_memcpy((u8 *)&val, rtw_get_capability_from_ie(bss->IEs), 2);
+
+	return le16_to_cpu(val);
+}
+
+u8 *rtw_get_timestampe_from_ie(u8 *ie)
+{
+	return ie + 0;
+}
+
+u8 *rtw_get_beacon_interval_from_ie(u8 *ie)
+{
+	return ie + 8;
+}
+
+
+int	rtw_init_mlme_priv(_adapter *padapter) /* (struct	mlme_priv *pmlmepriv) */
+{
+	int	res;
+	res = _rtw_init_mlme_priv(padapter);/* (pmlmepriv); */
+	return res;
+}
+
+void rtw_free_mlme_priv(struct mlme_priv *pmlmepriv)
+{
+	_rtw_free_mlme_priv(pmlmepriv);
+}
+
+int	rtw_enqueue_network(_queue *queue, struct wlan_network *pnetwork);
+int	rtw_enqueue_network(_queue *queue, struct wlan_network *pnetwork)
+{
+	int	res;
+	res = _rtw_enqueue_network(queue, pnetwork);
+	return res;
+}
+
+/*
+static struct	wlan_network *rtw_dequeue_network(_queue *queue)
+{
+	struct wlan_network *pnetwork;
+	pnetwork = _rtw_dequeue_network(queue);
+	return pnetwork;
+}
+*/
+
+struct	wlan_network *rtw_alloc_network(struct	mlme_priv *pmlmepriv);
+struct	wlan_network *rtw_alloc_network(struct	mlme_priv *pmlmepriv) /* (_queue	*free_queue) */
+{
+	struct	wlan_network	*pnetwork;
+	pnetwork = _rtw_alloc_network(pmlmepriv);
+	return pnetwork;
+}
+
+void rtw_free_network(struct mlme_priv *pmlmepriv, struct	wlan_network *pnetwork, u8 is_freeall);
+void rtw_free_network(struct mlme_priv *pmlmepriv, struct	wlan_network *pnetwork, u8 is_freeall)/* (struct	wlan_network *pnetwork, _queue	*free_queue) */
+{
+	_rtw_free_network(pmlmepriv, pnetwork, is_freeall);
+}
+
+void rtw_free_network_nolock(_adapter *padapter, struct wlan_network *pnetwork);
+void rtw_free_network_nolock(_adapter *padapter, struct wlan_network *pnetwork)
+{
+	_rtw_free_network_nolock(&(padapter->mlmepriv), pnetwork);
+#ifdef CONFIG_IOCTL_CFG80211
+	rtw_cfg80211_unlink_bss(padapter, pnetwork);
+#endif /* CONFIG_IOCTL_CFG80211 */
+}
+
+
+void rtw_free_network_queue(_adapter *dev, u8 isfreeall)
+{
+	_rtw_free_network_queue(dev, isfreeall);
+}
+
+struct wlan_network *_rtw_find_network(_queue *scanned_queue, const u8 *addr)
+{
+	_list	*phead, *plist;
+	struct	wlan_network *pnetwork = NULL;
+	u8 zero_addr[ETH_ALEN] = {0, 0, 0, 0, 0, 0};
+
+	if (_rtw_memcmp(zero_addr, addr, ETH_ALEN)) {
+		pnetwork = NULL;
+		goto exit;
+	}
+
+	phead = get_list_head(scanned_queue);
+	plist = get_next(phead);
+
+	while (plist != phead) {
+		pnetwork = LIST_CONTAINOR(plist, struct wlan_network , list);
+
+		if (_rtw_memcmp(addr, pnetwork->network.MacAddress, ETH_ALEN) == _TRUE)
+			break;
+
+		plist = get_next(plist);
+	}
+
+	if (plist == phead)
+		pnetwork = NULL;
+
+exit:
+	return pnetwork;
+}
+
+struct wlan_network *rtw_find_network(_queue *scanned_queue, const u8 *addr)
+{
+	struct	wlan_network *pnetwork;
+	_irqL irqL;
+
+	 _enter_critical_bh(&scanned_queue->lock, &irqL);
+	pnetwork = _rtw_find_network(scanned_queue, addr);
+	_exit_critical_bh(&scanned_queue->lock, &irqL);
+
+	return pnetwork;
+}
+
+int rtw_is_same_ibss(_adapter *adapter, struct wlan_network *pnetwork)
+{
+	int ret = _TRUE;
+	struct security_priv *psecuritypriv = &adapter->securitypriv;
+
+	if ((psecuritypriv->dot11PrivacyAlgrthm != _NO_PRIVACY_) &&
+	    (pnetwork->network.Privacy == 0))
+		ret = _FALSE;
+	else if ((psecuritypriv->dot11PrivacyAlgrthm == _NO_PRIVACY_) &&
+		 (pnetwork->network.Privacy == 1))
+		ret = _FALSE;
+	else
+		ret = _TRUE;
+
+	return ret;
+
+}
+
+inline int is_same_ess(WLAN_BSSID_EX *a, WLAN_BSSID_EX *b)
+{
+	return (a->Ssid.SsidLength == b->Ssid.SsidLength)
+	       &&  _rtw_memcmp(a->Ssid.Ssid, b->Ssid.Ssid, a->Ssid.SsidLength) == _TRUE;
+}
+
+int is_same_network(WLAN_BSSID_EX *src, WLAN_BSSID_EX *dst, u8 feature)
+{
+	u16 s_cap, d_cap;
+
+
+	if (rtw_bug_check(dst, src, &s_cap, &d_cap) == _FALSE)
+		return _FALSE;
+
+	_rtw_memcpy((u8 *)&s_cap, rtw_get_capability_from_ie(src->IEs), 2);
+	_rtw_memcpy((u8 *)&d_cap, rtw_get_capability_from_ie(dst->IEs), 2);
+
+
+	s_cap = le16_to_cpu(s_cap);
+	d_cap = le16_to_cpu(d_cap);
+
+
+#ifdef CONFIG_P2P
+	if ((feature == 1) && /* 1: P2P supported */
+	    (_rtw_memcmp(src->MacAddress, dst->MacAddress, ETH_ALEN) == _TRUE)
+	   )
+		return _TRUE;
+#endif
+
+	/* Wi-Fi driver doesn't consider the situation of BCN and ProbRsp sent from the same hidden AP, 
+	  * it considers these two packets are sent from different AP. 
+	  * Therefore, the scan queue may store two scan results of the same hidden AP, likes below.
+	  *
+	  *  index            bssid              ch    RSSI   SdBm  Noise   age          flag             ssid
+	  *    1    00:e0:4c:55:50:01    153   -73     -73        0     7044   [WPS][ESS]     RTK5G
+	  *    3    00:e0:4c:55:50:01    153   -73     -73        0     7044   [WPS][ESS]
+	  *
+	  * Original rules will compare Ssid, SsidLength, MacAddress, s_cap, d_cap at the same time.
+	  * Wi-Fi driver will assume that the BCN and ProbRsp sent from the same hidden AP are the same network
+	  * after we add an additional rule to compare SsidLength and Ssid.
+	  * It means the scan queue will not store two scan results of the same hidden AP, it only store ProbRsp.
+	  * For customer request.
+	  */
+	  
+	if (((_rtw_memcmp(src->MacAddress, dst->MacAddress, ETH_ALEN)) == _TRUE) &&
+		((s_cap & WLAN_CAPABILITY_IBSS) == (d_cap & WLAN_CAPABILITY_IBSS)) &&
+		((s_cap & WLAN_CAPABILITY_BSS) == (d_cap & WLAN_CAPABILITY_BSS))) {
+		if ((src->Ssid.SsidLength == dst->Ssid.SsidLength) && 
+			(((_rtw_memcmp(src->Ssid.Ssid, dst->Ssid.Ssid, src->Ssid.SsidLength)) == _TRUE) || //Case of normal AP
+			(is_all_null(src->Ssid.Ssid, src->Ssid.SsidLength) == _TRUE || is_all_null(dst->Ssid.Ssid, dst->Ssid.SsidLength) == _TRUE))) //Case of hidden AP
+			return _TRUE;
+		else if ((src->Ssid.SsidLength == 0 || dst->Ssid.SsidLength == 0)) //Case of hidden AP
+			return _TRUE;
+		else
+			return _FALSE;
+	} else {
+		return _FALSE;
+	}
+}
+
+struct wlan_network *_rtw_find_same_network(_queue *scanned_queue, struct wlan_network *network)
+{
+	_list *phead, *plist;
+	struct wlan_network *found = NULL;
+
+	phead = get_list_head(scanned_queue);
+	plist = get_next(phead);
+
+	while (plist != phead) {
+		found = LIST_CONTAINOR(plist, struct wlan_network , list);
+
+		if (is_same_network(&network->network, &found->network, 0))
+			break;
+
+		plist = get_next(plist);
+	}
+
+	if (plist == phead)
+		found = NULL;
+
+	return found;
+}
+
+struct wlan_network *rtw_find_same_network(_queue *scanned_queue, struct wlan_network *network)
+{
+	_irqL irqL;
+	struct wlan_network *found = NULL;
+
+	if (scanned_queue == NULL || network == NULL)
+		goto exit;
+
+	_enter_critical_bh(&scanned_queue->lock, &irqL);
+	found = _rtw_find_same_network(scanned_queue, network);
+	_exit_critical_bh(&scanned_queue->lock, &irqL);
+
+exit:
+	return found;
+}
+
+struct	wlan_network	*rtw_get_oldest_wlan_network(_queue *scanned_queue)
+{
+	_list	*plist, *phead;
+
+
+	struct	wlan_network	*pwlan = NULL;
+	struct	wlan_network	*oldest = NULL;
+	phead = get_list_head(scanned_queue);
+
+	plist = get_next(phead);
+
+	while (1) {
+
+		if (rtw_end_of_queue_search(phead, plist) == _TRUE)
+			break;
+
+		pwlan = LIST_CONTAINOR(plist, struct wlan_network, list);
+
+		if (pwlan->fixed != _TRUE) {
+			if (oldest == NULL || rtw_time_after(oldest->last_scanned, pwlan->last_scanned))
+				oldest = pwlan;
+		}
+
+		plist = get_next(plist);
+	}
+	return oldest;
+
+}
+
+void update_network(WLAN_BSSID_EX *dst, WLAN_BSSID_EX *src,
+		    _adapter *padapter, bool update_ie)
+{
+#if defined(DBG_RX_SIGNAL_DISPLAY_SSID_MONITORED) && 1
+	u8 ss_ori = dst->PhyInfo.SignalStrength;
+	u8 sq_ori = dst->PhyInfo.SignalQuality;
+	u8 ss_smp = src->PhyInfo.SignalStrength;
+	long rssi_smp = src->Rssi;
+#endif
+	long rssi_ori = dst->Rssi;
+
+	u8 sq_smp = src->PhyInfo.SignalQuality;
+	u8 ss_final;
+	u8 sq_final;
+	long rssi_final;
+
+
+#ifdef CONFIG_ANTENNA_DIVERSITY
+	rtw_hal_antdiv_rssi_compared(padapter, dst, src); /* this will update src.Rssi, need consider again */
+#endif
+
+#if defined(DBG_RX_SIGNAL_DISPLAY_SSID_MONITORED) && 1
+	if (strcmp(dst->Ssid.Ssid, DBG_RX_SIGNAL_DISPLAY_SSID_MONITORED) == 0) {
+		RTW_INFO(FUNC_ADPT_FMT" %s("MAC_FMT", ch%u) ss_ori:%3u, sq_ori:%3u, rssi_ori:%3ld, ss_smp:%3u, sq_smp:%3u, rssi_smp:%3ld\n"
+			 , FUNC_ADPT_ARG(padapter)
+			, src->Ssid.Ssid, MAC_ARG(src->MacAddress), src->Configuration.DSConfig
+			 , ss_ori, sq_ori, rssi_ori
+			 , ss_smp, sq_smp, rssi_smp
+			);
+	}
+#endif
+
+	/* The rule below is 1/5 for sample value, 4/5 for history value */
+	if (check_fwstate(&padapter->mlmepriv, _FW_LINKED) && is_same_network(&(padapter->mlmepriv.cur_network.network), src, 0)) {
+		/* Take the recvpriv's value for the connected AP*/
+		ss_final = padapter->recvpriv.signal_strength;
+		sq_final = padapter->recvpriv.signal_qual;
+		/* the rssi value here is undecorated, and will be used for antenna diversity */
+		if (sq_smp != 101) /* from the right channel */
+			rssi_final = (src->Rssi + dst->Rssi * 4) / 5;
+		else
+			rssi_final = rssi_ori;
+	} else {
+		if (sq_smp != 101) { /* from the right channel */
+			ss_final = ((u32)(src->PhyInfo.SignalStrength) + (u32)(dst->PhyInfo.SignalStrength) * 4) / 5;
+			sq_final = ((u32)(src->PhyInfo.SignalQuality) + (u32)(dst->PhyInfo.SignalQuality) * 4) / 5;
+			rssi_final = (src->Rssi + dst->Rssi * 4) / 5;
+		} else {
+			/* bss info not receving from the right channel, use the original RX signal infos */
+			ss_final = dst->PhyInfo.SignalStrength;
+			sq_final = dst->PhyInfo.SignalQuality;
+			rssi_final = dst->Rssi;
+		}
+
+	}
+
+	if (update_ie) {
+		dst->Reserved[0] = src->Reserved[0];
+		dst->Reserved[1] = src->Reserved[1];
+		_rtw_memcpy((u8 *)dst, (u8 *)src, get_WLAN_BSSID_EX_sz(src));
+	}
+
+	dst->PhyInfo.SignalStrength = ss_final;
+	dst->PhyInfo.SignalQuality = sq_final;
+	dst->Rssi = rssi_final;
+
+#if defined(DBG_RX_SIGNAL_DISPLAY_SSID_MONITORED) && 1
+	if (strcmp(dst->Ssid.Ssid, DBG_RX_SIGNAL_DISPLAY_SSID_MONITORED) == 0) {
+		RTW_INFO(FUNC_ADPT_FMT" %s("MAC_FMT"), SignalStrength:%u, SignalQuality:%u, RawRSSI:%ld\n"
+			 , FUNC_ADPT_ARG(padapter)
+			, dst->Ssid.Ssid, MAC_ARG(dst->MacAddress), dst->PhyInfo.SignalStrength, dst->PhyInfo.SignalQuality, dst->Rssi);
+	}
+#endif
+
+#if 0 /* old codes, may be useful one day...
+ * 	RTW_INFO("update_network: rssi=0x%lx dst->Rssi=%d ,dst->Rssi=0x%lx , src->Rssi=0x%lx",(dst->Rssi+src->Rssi)/2,dst->Rssi,dst->Rssi,src->Rssi); */
+	if (check_fwstate(&padapter->mlmepriv, _FW_LINKED) && is_same_network(&(padapter->mlmepriv.cur_network.network), src)) {
+
+		/* RTW_INFO("b:ssid=%s update_network: src->rssi=0x%d padapter->recvpriv.ui_rssi=%d\n",src->Ssid.Ssid,src->Rssi,padapter->recvpriv.signal); */
+		if (padapter->recvpriv.signal_qual_data.total_num++ >= PHY_LINKQUALITY_SLID_WIN_MAX) {
+			padapter->recvpriv.signal_qual_data.total_num = PHY_LINKQUALITY_SLID_WIN_MAX;
+			last_evm = padapter->recvpriv.signal_qual_data.elements[padapter->recvpriv.signal_qual_data.index];
+			padapter->recvpriv.signal_qual_data.total_val -= last_evm;
+		}
+		padapter->recvpriv.signal_qual_data.total_val += query_rx_pwr_percentage(src->Rssi);
+
+		padapter->recvpriv.signal_qual_data.elements[padapter->recvpriv.signal_qual_data.index++] = query_rx_pwr_percentage(src->Rssi);
+		if (padapter->recvpriv.signal_qual_data.index >= PHY_LINKQUALITY_SLID_WIN_MAX)
+			padapter->recvpriv.signal_qual_data.index = 0;
+
+		/* RTW_INFO("Total SQ=%d  pattrib->signal_qual= %d\n", padapter->recvpriv.signal_qual_data.total_val, src->Rssi); */
+
+		/* <1> Showed on UI for user,in percentage. */
+		tmpVal = padapter->recvpriv.signal_qual_data.total_val / padapter->recvpriv.signal_qual_data.total_num;
+		padapter->recvpriv.signal = (u8)tmpVal; /* Link quality */
+
+		src->Rssi = translate_percentage_to_dbm(padapter->recvpriv.signal) ;
+	} else {
+		/*	RTW_INFO("ELSE:ssid=%s update_network: src->rssi=0x%d dst->rssi=%d\n",src->Ssid.Ssid,src->Rssi,dst->Rssi); */
+		src->Rssi = (src->Rssi + dst->Rssi) / 2; /* dBM */
+	}
+
+	/*	RTW_INFO("a:update_network: src->rssi=0x%d padapter->recvpriv.ui_rssi=%d\n",src->Rssi,padapter->recvpriv.signal); */
+
+#endif
+
+}
+
+static void update_current_network(_adapter *adapter, WLAN_BSSID_EX *pnetwork)
+{
+	struct	mlme_priv	*pmlmepriv = &(adapter->mlmepriv);
+
+
+	rtw_bug_check(&(pmlmepriv->cur_network.network),
+		      &(pmlmepriv->cur_network.network),
+		      &(pmlmepriv->cur_network.network),
+		      &(pmlmepriv->cur_network.network));
+
+	if ((check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE) && (is_same_network(&(pmlmepriv->cur_network.network), pnetwork, 0))) {
+
+		/* if(pmlmepriv->cur_network.network.IELength<= pnetwork->IELength) */
+		{
+			update_network(&(pmlmepriv->cur_network.network), pnetwork, adapter, _TRUE);
+			rtw_update_protection(adapter, (pmlmepriv->cur_network.network.IEs) + sizeof(NDIS_802_11_FIXED_IEs),
+				      pmlmepriv->cur_network.network.IELength);
+		}
+	}
+
+
+}
+
+
+/*
+
+Caller must hold pmlmepriv->lock first.
+
+
+*/
+bool rtw_update_scanned_network(_adapter *adapter, WLAN_BSSID_EX *target)
+{
+	_irqL irqL;
+	_list	*plist, *phead;
+	ULONG	bssid_ex_sz;
+	struct mlme_priv	*pmlmepriv = &(adapter->mlmepriv);
+#ifdef CONFIG_P2P
+	struct wifidirect_info *pwdinfo = &(adapter->wdinfo);
+#endif /* CONFIG_P2P */
+	_queue	*queue	= &(pmlmepriv->scanned_queue);
+	struct wlan_network	*pnetwork = NULL;
+	struct wlan_network	*choice = NULL;
+	int target_find = 0;
+	u8 feature = 0;
+	bool update_ie = _FALSE;
+
+	_enter_critical_bh(&queue->lock, &irqL);
+	phead = get_list_head(queue);
+	plist = get_next(phead);
+
+#if 0
+	RTW_INFO("%s => ssid:%s , rssi:%ld , ss:%d\n",
+		__func__, target->Ssid.Ssid, target->Rssi, target->PhyInfo.SignalStrength);
+#endif
+
+#ifdef CONFIG_P2P
+	if (!rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE))
+		feature = 1; /* p2p enable */
+#endif
+
+	while (1) {
+		if (rtw_end_of_queue_search(phead, plist) == _TRUE)
+			break;
+
+		pnetwork = LIST_CONTAINOR(plist, struct wlan_network, list);
+
+		rtw_bug_check(pnetwork, pnetwork, pnetwork, pnetwork);
+
+#ifdef CONFIG_P2P
+		if (!rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE) &&
+		    (_rtw_memcmp(pnetwork->network.MacAddress, target->MacAddress, ETH_ALEN) == _TRUE)) {
+			target_find = 1;
+			break;
+		}
+#endif
+
+		if (is_same_network(&(pnetwork->network), target, feature)) {
+			target_find = 1;
+			break;
+		}
+
+		if (rtw_roam_flags(adapter)) {
+			/* TODO: don't  select netowrk in the same ess as choice if it's new enough*/
+		}
+		if (pnetwork->fixed) {
+			plist = get_next(plist);
+			continue;
+		}
+			
+#ifdef CONFIG_RSSI_PRIORITY
+		if ((choice == NULL) || (pnetwork->network.PhyInfo.SignalStrength < choice->network.PhyInfo.SignalStrength))
+			#ifdef CONFIG_RTW_MESH
+			if (!MLME_IS_MESH(adapter) || !MLME_IS_ASOC(adapter)
+				|| !rtw_bss_is_same_mbss(&pmlmepriv->cur_network.network, &pnetwork->network))
+			#endif
+				choice = pnetwork;
+#else
+		if (choice == NULL || rtw_time_after(choice->last_scanned, pnetwork->last_scanned))
+			#ifdef CONFIG_RTW_MESH
+			if (!MLME_IS_MESH(adapter) || !MLME_IS_ASOC(adapter)
+				|| !rtw_bss_is_same_mbss(&pmlmepriv->cur_network.network, &pnetwork->network))
+			#endif
+				choice = pnetwork;
+#endif
+		plist = get_next(plist);
+
+	}
+
+
+	/* If we didn't find a match, then get a new network slot to initialize
+	 * with this beacon's information */
+	/* if (rtw_end_of_queue_search(phead,plist)== _TRUE) { */
+	if (!target_find) {
+		if (_rtw_queue_empty(&(pmlmepriv->free_bss_pool)) == _TRUE) {
+			/* If there are no more slots, expire the choice */
+			/* list_del_init(&choice->list); */
+			pnetwork = choice;
+			if (pnetwork == NULL)
+				goto unlock_scan_queue;
+
+#ifdef CONFIG_RSSI_PRIORITY
+		RTW_DBG("%s => ssid:%s ,bssid:"MAC_FMT"  will be deleted from scanned_queue (rssi:%ld , ss:%d)\n",
+			__func__, pnetwork->network.Ssid.Ssid, MAC_ARG(pnetwork->network.MacAddress), pnetwork->network.Rssi, pnetwork->network.PhyInfo.SignalStrength);
+#else
+		RTW_DBG("%s => ssid:%s ,bssid:"MAC_FMT" will be deleted from scanned_queue\n",
+			__func__, pnetwork->network.Ssid.Ssid, MAC_ARG(pnetwork->network.MacAddress));
+#endif
+
+#ifdef CONFIG_ANTENNA_DIVERSITY
+			rtw_hal_get_odm_var(adapter, HAL_ODM_ANTDIV_SELECT, &(target->PhyInfo.Optimum_antenna), NULL);
+#endif
+			_rtw_memcpy(&(pnetwork->network), target,  get_WLAN_BSSID_EX_sz(target));
+			/* pnetwork->last_scanned = rtw_get_current_time(); */
+			/* variable initialize */
+			pnetwork->fixed = _FALSE;
+			pnetwork->last_scanned = rtw_get_current_time();
+			#if defined(CONFIG_RTW_MESH) && CONFIG_RTW_MESH_ACNODE_PREVENT
+			pnetwork->acnode_stime = 0;
+			pnetwork->acnode_notify_etime = 0;
+			#endif
+
+			pnetwork->network_type = 0;
+			pnetwork->aid = 0;
+			pnetwork->join_res = 0;
+
+			/* bss info not receving from the right channel */
+			if (pnetwork->network.PhyInfo.SignalQuality == 101)
+				pnetwork->network.PhyInfo.SignalQuality = 0;
+		} else {
+			/* Otherwise just pull from the free list */
+
+			pnetwork = rtw_alloc_network(pmlmepriv); /* will update scan_time */
+			if (pnetwork == NULL)
+				goto unlock_scan_queue;
+
+			bssid_ex_sz = get_WLAN_BSSID_EX_sz(target);
+			target->Length = bssid_ex_sz;
+#ifdef CONFIG_ANTENNA_DIVERSITY
+			rtw_hal_get_odm_var(adapter, HAL_ODM_ANTDIV_SELECT, &(target->PhyInfo.Optimum_antenna), NULL);
+#endif
+			_rtw_memcpy(&(pnetwork->network), target, bssid_ex_sz);
+
+			pnetwork->last_scanned = rtw_get_current_time();
+
+			/* bss info not receving from the right channel */
+			if (pnetwork->network.PhyInfo.SignalQuality == 101)
+				pnetwork->network.PhyInfo.SignalQuality = 0;
+
+			rtw_list_insert_tail(&(pnetwork->list), &(queue->queue));
+
+		}
+	} else {
+		/* we have an entry and we are going to update it. But this entry may
+		 * be already expired. In this case we do the same as we found a new
+		 * net and call the new_net handler
+		 */
+		#if defined(CONFIG_RTW_MESH) && CONFIG_RTW_MESH_ACNODE_PREVENT
+		systime last_scanned = pnetwork->last_scanned;
+		#endif
+
+		pnetwork->last_scanned = rtw_get_current_time();
+
+		/* target.Reserved[0]==BSS_TYPE_BCN, means that scanned network is a bcn frame. */
+		if ((pnetwork->network.IELength > target->IELength) && (target->Reserved[0] == BSS_TYPE_BCN))
+			update_ie = _FALSE;
+
+		if (MLME_IS_MESH(adapter)
+			/* probe resp(3) > beacon(1) > probe req(2) */
+			|| (target->Reserved[0] != BSS_TYPE_PROB_REQ
+				&& target->Reserved[0] >= pnetwork->network.Reserved[0])
+		)
+			update_ie = _TRUE;
+		else
+			update_ie = _FALSE;
+
+		#if defined(CONFIG_RTW_MESH) && CONFIG_RTW_MESH_ACNODE_PREVENT
+		if (!MLME_IS_MESH(adapter) || !MLME_IS_ASOC(adapter)
+			|| pnetwork->network.Configuration.DSConfig != target->Configuration.DSConfig
+			|| rtw_get_passing_time_ms(last_scanned) > adapter->mesh_cfg.peer_sel_policy.scanr_exp_ms
+			|| !rtw_bss_is_same_mbss(&pnetwork->network, target)
+		) {
+			pnetwork->acnode_stime = 0;
+			pnetwork->acnode_notify_etime = 0;
+		}
+		#endif
+		update_network(&(pnetwork->network), target, adapter, update_ie);
+	}
+
+	#if defined(CONFIG_RTW_MESH) && CONFIG_RTW_MESH_ACNODE_PREVENT
+	if (MLME_IS_MESH(adapter) && MLME_IS_ASOC(adapter))
+		rtw_mesh_update_scanned_acnode_status(adapter, pnetwork);
+	#endif
+
+unlock_scan_queue:
+	_exit_critical_bh(&queue->lock, &irqL);
+
+#ifdef CONFIG_RTW_MESH
+	if (pnetwork && MLME_IS_MESH(adapter)
+		&& check_fwstate(pmlmepriv, WIFI_ASOC_STATE)
+		&& !check_fwstate(pmlmepriv, WIFI_SITE_MONITOR)
+	)
+		rtw_chk_candidate_peer_notify(adapter, pnetwork);
+#endif
+
+	return update_ie;
+}
+
+void rtw_add_network(_adapter *adapter, WLAN_BSSID_EX *pnetwork);
+void rtw_add_network(_adapter *adapter, WLAN_BSSID_EX *pnetwork)
+{
+	bool update_ie;
+	/* _queue	*queue	= &(pmlmepriv->scanned_queue); */
+
+	/* _enter_critical_bh(&queue->lock, &irqL); */
+
+#if defined(CONFIG_P2P) && defined(CONFIG_P2P_REMOVE_GROUP_INFO)
+	if (adapter->registrypriv.wifi_spec == 0)
+		rtw_bss_ex_del_p2p_attr(pnetwork, P2P_ATTR_GROUP_INFO);
+#endif
+
+	if (!hal_chk_wl_func(adapter, WL_FUNC_MIRACAST))
+		rtw_bss_ex_del_wfd_ie(pnetwork);
+
+	/* Wi-Fi driver will update the current network if the scan result of the connected AP be updated by scan. */
+	update_ie = rtw_update_scanned_network(adapter, pnetwork);
+
+	if (update_ie)
+		update_current_network(adapter, pnetwork);
+
+	/* _exit_critical_bh(&queue->lock, &irqL); */
+
+}
+
+/* select the desired network based on the capability of the (i)bss.
+ * check items: (1) security
+ *			   (2) network_type
+ *			   (3) WMM
+ *			   (4) HT
+ * (5) others */
+int rtw_is_desired_network(_adapter *adapter, struct wlan_network *pnetwork);
+int rtw_is_desired_network(_adapter *adapter, struct wlan_network *pnetwork)
+{
+	struct security_priv *psecuritypriv = &adapter->securitypriv;
+	struct mlme_priv *pmlmepriv = &adapter->mlmepriv;
+	u32 desired_encmode;
+	u32 privacy;
+
+	/* u8 wps_ie[512]; */
+	uint wps_ielen;
+
+	int bselected = _TRUE;
+
+	desired_encmode = psecuritypriv->ndisencryptstatus;
+	privacy = pnetwork->network.Privacy;
+
+	if (check_fwstate(pmlmepriv, WIFI_UNDER_WPS)) {
+		if (rtw_get_wps_ie(pnetwork->network.IEs + _FIXED_IE_LENGTH_, pnetwork->network.IELength - _FIXED_IE_LENGTH_, NULL, &wps_ielen) != NULL)
+			return _TRUE;
+		else
+			return _FALSE;
+	}
+	if (adapter->registrypriv.wifi_spec == 1) { /* for  correct flow of 8021X  to do.... */
+		u8 *p = NULL;
+		uint ie_len = 0;
+
+		if ((desired_encmode == Ndis802_11EncryptionDisabled) && (privacy != 0))
+			bselected = _FALSE;
+
+		if (psecuritypriv->ndisauthtype == Ndis802_11AuthModeWPA2PSK) {
+			p = rtw_get_ie(pnetwork->network.IEs + _BEACON_IE_OFFSET_, _RSN_IE_2_, &ie_len, (pnetwork->network.IELength - _BEACON_IE_OFFSET_));
+			if (p && ie_len > 0)
+				bselected = _TRUE;
+			else
+				bselected = _FALSE;
+		}
+	}
+
+
+	if ((desired_encmode != Ndis802_11EncryptionDisabled) && (privacy == 0)) {
+		RTW_INFO("desired_encmode: %d, privacy: %d\n", desired_encmode, privacy);
+		bselected = _FALSE;
+	}
+
+	if (check_fwstate(pmlmepriv, WIFI_ADHOC_STATE) == _TRUE) {
+		if (pnetwork->network.InfrastructureMode != pmlmepriv->cur_network.network.InfrastructureMode)
+			bselected = _FALSE;
+	}
+
+
+	return bselected;
+}
+
+/* TODO: Perry : For Power Management */
+void rtw_atimdone_event_callback(_adapter	*adapter , u8 *pbuf)
+{
+
+	return;
+}
+
+
+void rtw_survey_event_callback(_adapter	*adapter, u8 *pbuf)
+{
+	_irqL  irqL;
+	u32 len;
+	WLAN_BSSID_EX *pnetwork;
+	struct	mlme_priv	*pmlmepriv = &(adapter->mlmepriv);
+
+
+	pnetwork = (WLAN_BSSID_EX *)pbuf;
+
+
+#ifdef CONFIG_RTL8712
+	/* endian_convert */
+	pnetwork->Length = le32_to_cpu(pnetwork->Length);
+	pnetwork->Ssid.SsidLength = le32_to_cpu(pnetwork->Ssid.SsidLength);
+	pnetwork->Privacy = le32_to_cpu(pnetwork->Privacy);
+	pnetwork->Rssi = le32_to_cpu(pnetwork->Rssi);
+	pnetwork->NetworkTypeInUse = le32_to_cpu(pnetwork->NetworkTypeInUse);
+	pnetwork->Configuration.ATIMWindow = le32_to_cpu(pnetwork->Configuration.ATIMWindow);
+	pnetwork->Configuration.BeaconPeriod = le32_to_cpu(pnetwork->Configuration.BeaconPeriod);
+	pnetwork->Configuration.DSConfig = le32_to_cpu(pnetwork->Configuration.DSConfig);
+	pnetwork->Configuration.FHConfig.DwellTime = le32_to_cpu(pnetwork->Configuration.FHConfig.DwellTime);
+	pnetwork->Configuration.FHConfig.HopPattern = le32_to_cpu(pnetwork->Configuration.FHConfig.HopPattern);
+	pnetwork->Configuration.FHConfig.HopSet = le32_to_cpu(pnetwork->Configuration.FHConfig.HopSet);
+	pnetwork->Configuration.FHConfig.Length = le32_to_cpu(pnetwork->Configuration.FHConfig.Length);
+	pnetwork->Configuration.Length = le32_to_cpu(pnetwork->Configuration.Length);
+	pnetwork->InfrastructureMode = le32_to_cpu(pnetwork->InfrastructureMode);
+	pnetwork->IELength = le32_to_cpu(pnetwork->IELength);
+#endif
+
+	len = get_WLAN_BSSID_EX_sz(pnetwork);
+	if (len > (sizeof(WLAN_BSSID_EX))) {
+		return;
+	}
+
+
+	_enter_critical_bh(&pmlmepriv->lock, &irqL);
+
+	/* update IBSS_network 's timestamp */
+	if ((check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE)) == _TRUE) {
+		if (_rtw_memcmp(&(pmlmepriv->cur_network.network.MacAddress), pnetwork->MacAddress, ETH_ALEN)) {
+			struct wlan_network *ibss_wlan = NULL;
+			_irqL	irqL;
+
+			_rtw_memcpy(pmlmepriv->cur_network.network.IEs, pnetwork->IEs, 8);
+			_enter_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);
+			ibss_wlan = _rtw_find_network(&pmlmepriv->scanned_queue,  pnetwork->MacAddress);
+			if (ibss_wlan) {
+				_rtw_memcpy(ibss_wlan->network.IEs , pnetwork->IEs, 8);
+				_exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);
+				goto exit;
+			}
+			_exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);
+		}
+	}
+
+	/* lock pmlmepriv->lock when you accessing network_q */
+	if ((check_fwstate(pmlmepriv, _FW_UNDER_LINKING)) == _FALSE) {
+		if (pnetwork->Ssid.Ssid[0] == 0)
+			pnetwork->Ssid.SsidLength = 0;
+		rtw_add_network(adapter, pnetwork);
+	}
+
+exit:
+
+	_exit_critical_bh(&pmlmepriv->lock, &irqL);
+
+
+	return;
+}
+
+void rtw_surveydone_event_callback(_adapter	*adapter, u8 *pbuf)
+{
+	_irqL  irqL;
+	struct sitesurvey_parm parm;
+	struct	mlme_priv	*pmlmepriv = &(adapter->mlmepriv);
+#ifdef CONFIG_RTW_80211R
+	struct mlme_ext_priv	*pmlmeext = &adapter->mlmeextpriv;
+#endif
+
+#ifdef CONFIG_MLME_EXT
+	mlmeext_surveydone_event_callback(adapter);
+#endif
+
+
+	_enter_critical_bh(&pmlmepriv->lock, &irqL);
+	if (pmlmepriv->wps_probe_req_ie) {
+		u32 free_len = pmlmepriv->wps_probe_req_ie_len;
+		pmlmepriv->wps_probe_req_ie_len = 0;
+		rtw_mfree(pmlmepriv->wps_probe_req_ie, free_len);
+		pmlmepriv->wps_probe_req_ie = NULL;
+	}
+
+
+	if (check_fwstate(pmlmepriv, _FW_UNDER_SURVEY) == _FALSE) {
+		RTW_INFO(FUNC_ADPT_FMT" fw_state:0x%x\n", FUNC_ADPT_ARG(adapter), get_fwstate(pmlmepriv));
+		/* rtw_warn_on(1); */
+	}
+
+	_clr_fwstate_(pmlmepriv, _FW_UNDER_SURVEY);
+	_exit_critical_bh(&pmlmepriv->lock, &irqL);
+
+	_cancel_timer_ex(&pmlmepriv->scan_to_timer);
+
+	_enter_critical_bh(&pmlmepriv->lock, &irqL);
+
+#ifdef CONFIG_NEW_SIGNAL_STAT_PROCESS
+	rtw_set_signal_stat_timer(&adapter->recvpriv);
+#endif
+
+	if (pmlmepriv->to_join == _TRUE) {
+		if ((check_fwstate(pmlmepriv, WIFI_ADHOC_STATE) == _TRUE)) {
+			if (check_fwstate(pmlmepriv, _FW_LINKED) == _FALSE) {
+				set_fwstate(pmlmepriv, _FW_UNDER_LINKING);
+
+				if (rtw_select_and_join_from_scanned_queue(pmlmepriv) == _SUCCESS)
+					_set_timer(&pmlmepriv->assoc_timer, MAX_JOIN_TIMEOUT);
+				else {
+					WLAN_BSSID_EX    *pdev_network = &(adapter->registrypriv.dev_network);
+					u8 *pibss = adapter->registrypriv.dev_network.MacAddress;
+
+					/* pmlmepriv->fw_state ^= _FW_UNDER_SURVEY; */ /* because don't set assoc_timer */
+					_clr_fwstate_(pmlmepriv, _FW_UNDER_SURVEY);
+
+
+					_rtw_memset(&pdev_network->Ssid, 0, sizeof(NDIS_802_11_SSID));
+					_rtw_memcpy(&pdev_network->Ssid, &pmlmepriv->assoc_ssid, sizeof(NDIS_802_11_SSID));
+
+					rtw_update_registrypriv_dev_network(adapter);
+					rtw_generate_random_ibss(pibss);
+
+					/*pmlmepriv->fw_state = WIFI_ADHOC_MASTER_STATE;*/
+					init_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE);
+
+					if (rtw_create_ibss_cmd(adapter, 0) != _SUCCESS)
+						RTW_ERR("rtw_create_ibss_cmd FAIL\n");
+
+					pmlmepriv->to_join = _FALSE;
+				}
+			}
+		} else {
+			int s_ret;
+			set_fwstate(pmlmepriv, _FW_UNDER_LINKING);
+			pmlmepriv->to_join = _FALSE;
+			s_ret = rtw_select_and_join_from_scanned_queue(pmlmepriv);
+			if (_SUCCESS == s_ret)
+				_set_timer(&pmlmepriv->assoc_timer, MAX_JOIN_TIMEOUT);
+			else if (s_ret == 2) { /* there is no need to wait for join */
+				_clr_fwstate_(pmlmepriv, _FW_UNDER_LINKING);
+				rtw_indicate_connect(adapter);
+			} else {
+				RTW_INFO("try_to_join, but select scanning queue fail, to_roam:%d\n", rtw_to_roam(adapter));
+
+				if (rtw_to_roam(adapter) != 0) {
+					u8 ssc_chk = rtw_sitesurvey_condition_check(adapter, _FALSE);
+
+					rtw_init_sitesurvey_parm(adapter, &parm);
+					_rtw_memcpy(&parm.ssid[0], &pmlmepriv->assoc_ssid, sizeof(NDIS_802_11_SSID));
+					parm.ssid_num = 1;
+
+					if (rtw_dec_to_roam(adapter) == 0
+						|| (ssc_chk != SS_ALLOW && ssc_chk != SS_DENY_BUSY_TRAFFIC)
+						|| _SUCCESS != rtw_sitesurvey_cmd(adapter, &parm)
+					   ) {
+						rtw_set_to_roam(adapter, 0);
+#ifdef CONFIG_INTEL_WIDI
+						if (adapter->mlmepriv.widi_state == INTEL_WIDI_STATE_ROAMING) {
+							_rtw_memset(pmlmepriv->sa_ext, 0x00, L2SDTA_SERVICE_VE_LEN);
+							intel_widi_wk_cmd(adapter, INTEL_WIDI_LISTEN_WK, NULL, 0);
+							RTW_INFO("change to widi listen\n");
+						}
+#endif /* CONFIG_INTEL_WIDI */
+						rtw_free_assoc_resources(adapter, _TRUE);
+						rtw_indicate_disconnect(adapter, 0, _FALSE);
+					} else
+						pmlmepriv->to_join = _TRUE;
+				} else
+					rtw_indicate_disconnect(adapter, 0, _FALSE);
+				_clr_fwstate_(pmlmepriv, _FW_UNDER_LINKING);
+			}
+		}
+	} else {
+		if (rtw_chk_roam_flags(adapter, RTW_ROAM_ACTIVE)) {
+			if (check_fwstate(pmlmepriv, WIFI_STATION_STATE)
+			    && check_fwstate(pmlmepriv, _FW_LINKED)) {
+				if (rtw_select_roaming_candidate(pmlmepriv) == _SUCCESS) {
+#ifdef CONFIG_RTW_80211R
+					rtw_ft_start_roam(adapter,
+						(u8 *)pmlmepriv->roam_network->network.MacAddress);
+#else
+					receive_disconnect(adapter, pmlmepriv->cur_network.network.MacAddress
+						, WLAN_REASON_ACTIVE_ROAM, _FALSE);
+#endif
+				}
+			}
+		}
+	}
+
+	/* RTW_INFO("scan complete in %dms\n",rtw_get_passing_time_ms(pmlmepriv->scan_start_time)); */
+
+	_exit_critical_bh(&pmlmepriv->lock, &irqL);
+
+#ifdef CONFIG_P2P_PS
+	if (check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE)
+		p2p_ps_wk_cmd(adapter, P2P_PS_SCAN_DONE, 0);
+#endif /* CONFIG_P2P_PS */
+
+	rtw_mi_os_xmit_schedule(adapter);
+
+#ifdef CONFIG_DRVEXT_MODULE_WSC
+	drvext_surveydone_callback(&adapter->drvextpriv);
+#endif
+
+#ifdef DBG_CONFIG_ERROR_DETECT
+	{
+		struct mlme_ext_priv *pmlmeext = &adapter->mlmeextpriv;
+		if (pmlmeext->sitesurvey_res.bss_cnt == 0) {
+			/* rtw_hal_sreset_reset(adapter); */
+		}
+	}
+#endif
+
+#ifdef CONFIG_IOCTL_CFG80211
+	rtw_cfg80211_surveydone_event_callback(adapter);
+#endif /* CONFIG_IOCTL_CFG80211 */
+
+	rtw_indicate_scan_done(adapter, _FALSE);
+
+#if defined(CONFIG_CONCURRENT_MODE) && defined(CONFIG_IOCTL_CFG80211)
+	rtw_cfg80211_indicate_scan_done_for_buddy(adapter, _FALSE);
+#endif
+
+#ifdef CONFIG_RTW_MESH
+	#if CONFIG_RTW_MESH_OFFCH_CAND
+	if (rtw_mesh_offch_candidate_accepted(adapter)) {
+		u8 ch;
+
+		ch = rtw_mesh_select_operating_ch(adapter);
+		if (ch && pmlmepriv->cur_network.network.Configuration.DSConfig != ch) {
+			u8 ifbmp = rtw_mi_get_ap_mesh_ifbmp(adapter);
+
+			if (ifbmp) {
+				/* switch to selected channel */
+				rtw_change_bss_chbw_cmd(adapter, RTW_CMDF_DIRECTLY, ifbmp, 0, ch, REQ_BW_ORI, REQ_OFFSET_NONE);
+				issue_probereq_ex(adapter, &pmlmepriv->cur_network.network.mesh_id, NULL, 0, 0, 0, 0);
+			} else
+				rtw_warn_on(1);
+		}
+	}
+	#endif
+#endif /* CONFIG_RTW_MESH */
+}
+
+u8 _rtw_sitesurvey_condition_check(const char *caller, _adapter *adapter, bool check_sc_interval)
+{
+	u8 ss_condition = SS_ALLOW;
+	struct mlme_priv *pmlmepriv = &adapter->mlmepriv;
+#ifdef DBG_LA_MODE
+	struct registry_priv *registry_par = &adapter->registrypriv;
+#endif
+
+#ifdef CONFIG_MP_INCLUDED
+	if (rtw_mp_mode_check(adapter)) {
+		RTW_INFO("%s ("ADPT_FMT") MP mode block Scan request\n", caller, ADPT_ARG(adapter));
+		ss_condition = SS_DENY_MP_MODE;
+		goto _exit;
+	}
+#endif
+
+#ifdef DBG_LA_MODE
+	if(registry_par->la_mode_en == 1 && MLME_IS_ASOC(adapter)) {
+		RTW_INFO("%s ("ADPT_FMT") LA debug mode block Scan request\n", caller, ADPT_ARG(adapter));
+		ss_condition = SS_DENY_LA_MODE;
+		goto _exit;
+	}
+#endif
+
+#ifdef CONFIG_RTW_REPEATER_SON
+	if (adapter->rtw_rson_scanstage == RSON_SCAN_PROCESS) {
+		RTW_INFO("%s ("ADPT_FMT") blocking scan for under rson scanning process\n", caller, ADPT_ARG(adapter));
+		ss_condition = SS_DENY_RSON_SCANING;
+		goto _exit;
+	}
+#endif
+#ifdef CONFIG_IOCTL_CFG80211
+	if (adapter_wdev_data(adapter)->block_scan == _TRUE) {
+		RTW_INFO("%s ("ADPT_FMT") wdev_priv.block_scan is set\n", caller, ADPT_ARG(adapter));
+		ss_condition = SS_DENY_BLOCK_SCAN;
+		goto _exit;
+	}
+#endif
+	if (rtw_is_scan_deny(adapter)) {
+		RTW_INFO("%s ("ADPT_FMT") : scan deny\n", caller, ADPT_ARG(adapter));
+		ss_condition = SS_DENY_BY_DRV;
+		goto _exit;
+	}
+
+	if (check_fwstate(pmlmepriv, WIFI_AP_STATE)){
+		if(check_fwstate(pmlmepriv, WIFI_UNDER_WPS)) {
+			RTW_INFO("%s ("ADPT_FMT") : scan abort!! AP mode process WPS\n", caller, ADPT_ARG(adapter));
+			ss_condition = SS_DENY_SELF_AP_UNDER_WPS;
+			goto _exit;
+		} else if (check_fwstate(pmlmepriv, _FW_UNDER_LINKING) == _TRUE) {
+			RTW_INFO("%s ("ADPT_FMT") : scan abort!!AP mode under linking (fwstate=0x%x)\n",
+				caller, ADPT_ARG(adapter), pmlmepriv->fw_state);
+			ss_condition = SS_DENY_SELF_AP_UNDER_LINKING;
+			goto _exit;
+		} else if (check_fwstate(pmlmepriv, _FW_UNDER_SURVEY) == _TRUE) {
+			RTW_INFO("%s ("ADPT_FMT") : scan abort!!AP mode under survey (fwstate=0x%x)\n",
+				caller, ADPT_ARG(adapter), pmlmepriv->fw_state);
+			ss_condition = SS_DENY_SELF_AP_UNDER_SURVEY;
+			goto _exit;
+		}
+	} else {
+		if (check_fwstate(pmlmepriv, _FW_UNDER_LINKING) == _TRUE) {
+			RTW_INFO("%s ("ADPT_FMT") : scan abort!!STA mode under linking (fwstate=0x%x)\n",
+				caller, ADPT_ARG(adapter), pmlmepriv->fw_state);
+			ss_condition = SS_DENY_SELF_STA_UNDER_LINKING;
+			goto _exit;
+		} else if (check_fwstate(pmlmepriv, _FW_UNDER_SURVEY) == _TRUE) {
+			RTW_INFO("%s ("ADPT_FMT") : scan abort!!STA mode under survey (fwstate=0x%x)\n",
+				caller, ADPT_ARG(adapter), pmlmepriv->fw_state);
+			ss_condition = SS_DENY_SELF_STA_UNDER_SURVEY;
+			goto _exit;
+		}
+	}
+
+#ifdef CONFIG_CONCURRENT_MODE
+	if (rtw_mi_buddy_check_fwstate(adapter, _FW_UNDER_LINKING | WIFI_UNDER_WPS)) {
+		RTW_INFO("%s ("ADPT_FMT") : scan abort!! buddy_intf under linking or wps\n", caller, ADPT_ARG(adapter));
+		ss_condition = SS_DENY_BUDDY_UNDER_LINK_WPS;
+		goto _exit;
+
+	} else if (rtw_mi_buddy_check_fwstate(adapter, _FW_UNDER_SURVEY)) {
+		RTW_INFO("%s ("ADPT_FMT") : scan abort!! buddy_intf under survey\n", caller, ADPT_ARG(adapter));
+		ss_condition = SS_DENY_BUDDY_UNDER_SURVEY;
+		goto _exit;
+	}
+#endif /* CONFIG_CONCURRENT_MODE */
+
+	if (rtw_mi_busy_traffic_check(adapter, check_sc_interval)) {
+		RTW_INFO("%s ("ADPT_FMT") : scan abort!! ifs BusyTraffic == _TRUE\n", caller, ADPT_ARG(adapter));
+		ss_condition = SS_DENY_BUSY_TRAFFIC;
+		goto _exit;
+	}
+
+_exit :
+	return ss_condition;
+}
+
+void rtw_dummy_event_callback(_adapter *adapter , u8 *pbuf)
+{
+
+}
+
+void rtw_fwdbg_event_callback(_adapter *adapter , u8 *pbuf)
+{
+
+}
+
+static void free_scanqueue(struct	mlme_priv *pmlmepriv)
+{
+	_irqL irqL, irqL0;
+	_queue *free_queue = &pmlmepriv->free_bss_pool;
+	_queue *scan_queue = &pmlmepriv->scanned_queue;
+	_list	*plist, *phead, *ptemp;
+
+
+	_enter_critical_bh(&scan_queue->lock, &irqL0);
+	_enter_critical_bh(&free_queue->lock, &irqL);
+
+	phead = get_list_head(scan_queue);
+	plist = get_next(phead);
+
+	while (plist != phead) {
+		ptemp = get_next(plist);
+		rtw_list_delete(plist);
+		rtw_list_insert_tail(plist, &free_queue->queue);
+		plist = ptemp;
+		pmlmepriv->num_of_scanned--;
+	}
+
+	_exit_critical_bh(&free_queue->lock, &irqL);
+	_exit_critical_bh(&scan_queue->lock, &irqL0);
+
+}
+
+void rtw_reset_rx_info(_adapter *adapter)
+{
+	struct recv_priv  *precvpriv = &adapter->recvpriv;
+
+	precvpriv->dbg_rx_ampdu_drop_count = 0;
+	precvpriv->dbg_rx_ampdu_forced_indicate_count = 0;
+	precvpriv->dbg_rx_ampdu_loss_count = 0;
+	precvpriv->dbg_rx_dup_mgt_frame_drop_count = 0;
+	precvpriv->dbg_rx_ampdu_window_shift_cnt = 0;
+	precvpriv->dbg_rx_drop_count = 0;
+	precvpriv->dbg_rx_conflic_mac_addr_cnt = 0;
+}
+
+/*
+*rtw_free_assoc_resources: the caller has to lock pmlmepriv->lock
+*/
+void rtw_free_assoc_resources(_adapter *adapter, u8 lock_scanned_queue)
+{
+	_irqL irqL;
+	struct wlan_network *pwlan = NULL;
+	struct	mlme_priv *pmlmepriv = &adapter->mlmepriv;
+	struct wlan_network *tgt_network = &pmlmepriv->cur_network;
+
+
+#ifdef CONFIG_TDLS
+	struct tdls_info *ptdlsinfo = &adapter->tdlsinfo;
+#endif /* CONFIG_TDLS */
+
+
+	RTW_INFO("%s-"ADPT_FMT" tgt_network MacAddress=" MAC_FMT" ssid=%s\n",
+		__func__, ADPT_ARG(adapter), MAC_ARG(tgt_network->network.MacAddress), tgt_network->network.Ssid.Ssid);
+
+	if (check_fwstate(pmlmepriv, WIFI_STATION_STATE)) {
+		struct sta_info *psta;
+
+		psta = rtw_get_stainfo(&adapter->stapriv, tgt_network->network.MacAddress);
+
+#ifdef CONFIG_TDLS
+		rtw_free_all_tdls_sta(adapter, _TRUE);
+		rtw_reset_tdls_info(adapter);
+
+		if (ptdlsinfo->link_established == _TRUE)
+			rtw_tdls_cmd(adapter, NULL, TDLS_RS_RCR);
+#endif /* CONFIG_TDLS */
+
+		/* _enter_critical_bh(&(pstapriv->sta_hash_lock), &irqL); */
+		rtw_free_stainfo(adapter, psta);
+		/* _exit_critical_bh(&(pstapriv->sta_hash_lock), &irqL); */
+
+	}
+
+	if (check_fwstate(pmlmepriv, WIFI_ADHOC_STATE | WIFI_ADHOC_MASTER_STATE)) {
+		struct sta_info *psta;
+
+		rtw_free_all_stainfo(adapter);
+
+		psta = rtw_get_bcmc_stainfo(adapter);
+		/* _enter_critical_bh(&(pstapriv->sta_hash_lock), &irqL);		 */
+		rtw_free_stainfo(adapter, psta);
+		/* _exit_critical_bh(&(pstapriv->sta_hash_lock), &irqL);		 */
+
+		rtw_init_bcmc_stainfo(adapter);
+	}
+
+	if (lock_scanned_queue)
+		_enter_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);
+
+	if (check_fwstate(pmlmepriv, WIFI_UNDER_WPS) || (pmlmepriv->wpa_phase == _TRUE)){
+		RTW_INFO("Dont free disconnecting network of scanned_queue due to uner %s %s phase\n\n",
+			check_fwstate(pmlmepriv, WIFI_UNDER_WPS) ? "WPS" : "",
+			(pmlmepriv->wpa_phase == _TRUE) ? "WPA" : "");
+	} else {
+		pwlan = _rtw_find_same_network(&pmlmepriv->scanned_queue, tgt_network);
+		if (pwlan) {
+			pwlan->fixed = _FALSE;
+
+			RTW_INFO("Free disconnecting network of scanned_queue\n");
+			rtw_free_network_nolock(adapter, pwlan);
+#ifdef CONFIG_P2P
+			if (!rtw_p2p_chk_state(&adapter->wdinfo, P2P_STATE_NONE)) {
+				rtw_set_scan_deny(adapter, 2000);
+				/* rtw_clear_scan_deny(adapter); */
+			}
+#endif /* CONFIG_P2P */
+		} else
+			RTW_ERR("Free disconnecting network of scanned_queue failed due to pwlan == NULL\n\n");
+	}
+
+	if ((check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE) && (adapter->stapriv.asoc_sta_count == 1))
+	    /*||check_fwstate(pmlmepriv, WIFI_STATION_STATE)*/) {
+		if (pwlan)
+			rtw_free_network_nolock(adapter, pwlan);
+	}
+
+	if (lock_scanned_queue)
+		_exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);
+
+	adapter->securitypriv.key_mask = 0;
+
+	rtw_reset_rx_info(adapter);
+
+
+}
+
+/*
+*rtw_indicate_connect: the caller has to lock pmlmepriv->lock
+*/
+void rtw_indicate_connect(_adapter *padapter)
+{
+	struct mlme_priv	*pmlmepriv = &padapter->mlmepriv;
+
+	pmlmepriv->to_join = _FALSE;
+
+	if (!check_fwstate(&padapter->mlmepriv, _FW_LINKED)) {
+
+		set_fwstate(pmlmepriv, _FW_LINKED);
+
+		rtw_led_control(padapter, LED_CTL_LINK);
+
+		rtw_os_indicate_connect(padapter);
+	}
+
+	rtw_set_to_roam(padapter, 0);
+#ifdef CONFIG_INTEL_WIDI
+	if (padapter->mlmepriv.widi_state == INTEL_WIDI_STATE_ROAMING) {
+		_rtw_memset(pmlmepriv->sa_ext, 0x00, L2SDTA_SERVICE_VE_LEN);
+		intel_widi_wk_cmd(padapter, INTEL_WIDI_LISTEN_WK, NULL, 0);
+		RTW_INFO("change to widi listen\n");
+	}
+#endif /* CONFIG_INTEL_WIDI */
+	if (!MLME_IS_AP(padapter) && !MLME_IS_MESH(padapter))
+		rtw_mi_set_scan_deny(padapter, 3000);
+
+
+}
+
+
+/*
+*rtw_indicate_disconnect: the caller has to lock pmlmepriv->lock
+*/
+void rtw_indicate_disconnect(_adapter *padapter, u16 reason, u8 locally_generated)
+{
+	struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
+	struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv);
+	struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
+	WLAN_BSSID_EX	*cur_network = &(pmlmeinfo->network);
+#ifdef CONFIG_WAPI_SUPPORT
+	struct sta_info *psta;
+	struct sta_priv *pstapriv = &padapter->stapriv;
+#endif
+	u8 *wps_ie = NULL;
+	uint wpsie_len = 0;
+
+	if (check_fwstate(pmlmepriv, WIFI_UNDER_WPS))
+		pmlmepriv->wpa_phase = _TRUE;
+
+	_clr_fwstate_(pmlmepriv, _FW_UNDER_LINKING | WIFI_UNDER_WPS | WIFI_OP_CH_SWITCHING | WIFI_UNDER_KEY_HANDSHAKE);
+
+	/* force to clear cur_network_scanned's SELECTED REGISTRAR */
+	if (pmlmepriv->cur_network_scanned) {
+		WLAN_BSSID_EX	*current_joined_bss = &(pmlmepriv->cur_network_scanned->network);
+		if (current_joined_bss) {
+			wps_ie = rtw_get_wps_ie(current_joined_bss->IEs + _FIXED_IE_LENGTH_,
+				current_joined_bss->IELength - _FIXED_IE_LENGTH_, NULL, &wpsie_len);
+			if (wps_ie && wpsie_len > 0) {
+				u8 *attr = NULL;
+				u32 attr_len;
+				attr = rtw_get_wps_attr(wps_ie, wpsie_len, WPS_ATTR_SELECTED_REGISTRAR,
+							NULL, &attr_len);
+				if (attr)
+					*(attr + 4) = 0;
+			}
+		}
+	}
+	/* RTW_INFO("clear wps when %s\n", __func__); */
+
+	if (rtw_to_roam(padapter) > 0)
+		_clr_fwstate_(pmlmepriv, _FW_LINKED);
+
+#ifdef CONFIG_WAPI_SUPPORT
+	psta = rtw_get_stainfo(pstapriv, cur_network->MacAddress);
+	if (check_fwstate(pmlmepriv, WIFI_STATION_STATE))
+		rtw_wapi_return_one_sta_info(padapter, psta->cmn.mac_addr);
+	else if (check_fwstate(pmlmepriv, WIFI_ADHOC_STATE) ||
+		 check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE))
+		rtw_wapi_return_all_sta_info(padapter);
+#endif
+
+	if (check_fwstate(&padapter->mlmepriv, _FW_LINKED)
+	    || (rtw_to_roam(padapter) <= 0)
+	   ) {
+
+		rtw_os_indicate_disconnect(padapter, reason, locally_generated);
+
+		/* set ips_deny_time to avoid enter IPS before LPS leave */
+		rtw_set_ips_deny(padapter, 3000);
+
+		_clr_fwstate_(pmlmepriv, _FW_LINKED);
+
+		rtw_led_control(padapter, LED_CTL_NO_LINK);
+
+		rtw_clear_scan_deny(padapter);
+	}
+
+#ifdef CONFIG_P2P_PS
+	p2p_ps_wk_cmd(padapter, P2P_PS_DISABLE, 1);
+#endif /* CONFIG_P2P_PS */
+
+#ifdef CONFIG_LPS
+	rtw_lps_ctrl_wk_cmd(padapter, LPS_CTRL_DISCONNECT, 1);
+#endif
+
+#ifdef CONFIG_BEAMFORMING
+	beamforming_wk_cmd(padapter, BEAMFORMING_CTRL_LEAVE, cur_network->MacAddress, ETH_ALEN, 1);
+#endif /*CONFIG_BEAMFORMING*/
+
+}
+
+inline void rtw_indicate_scan_done(_adapter *padapter, bool aborted)
+{
+	RTW_INFO(FUNC_ADPT_FMT"\n", FUNC_ADPT_ARG(padapter));
+
+	rtw_os_indicate_scan_done(padapter, aborted);
+
+#ifdef CONFIG_IPS
+	if (is_primary_adapter(padapter)
+	    && (_FALSE == adapter_to_pwrctl(padapter)->bInSuspend)
+	    && (check_fwstate(&padapter->mlmepriv, WIFI_ASOC_STATE | WIFI_UNDER_LINKING) == _FALSE)) {
+		struct pwrctrl_priv *pwrpriv;
+
+		pwrpriv = adapter_to_pwrctl(padapter);
+		rtw_set_ips_deny(padapter, 0);
+#ifdef CONFIG_IPS_CHECK_IN_WD
+		_set_timer(&adapter_to_dvobj(padapter)->dynamic_chk_timer, 1);
+#else /* !CONFIG_IPS_CHECK_IN_WD */
+		_rtw_set_pwr_state_check_timer(pwrpriv, 1);
+#endif /* !CONFIG_IPS_CHECK_IN_WD */
+	}
+#endif /* CONFIG_IPS */
+}
+
+static u32 _rtw_wait_scan_done(_adapter *adapter, u8 abort, u32 timeout_ms)
+{
+	systime start;
+	u32 pass_ms;
+	struct mlme_priv *pmlmepriv = &(adapter->mlmepriv);
+	struct mlme_ext_priv *pmlmeext = &(adapter->mlmeextpriv);
+
+	start = rtw_get_current_time();
+
+	pmlmeext->scan_abort = abort;
+
+	while (check_fwstate(pmlmepriv, _FW_UNDER_SURVEY)
+	       && rtw_get_passing_time_ms(start) <= timeout_ms) {
+
+		if (RTW_CANNOT_RUN(adapter))
+			break;
+
+		RTW_INFO(FUNC_NDEV_FMT"fw_state=_FW_UNDER_SURVEY!\n", FUNC_NDEV_ARG(adapter->pnetdev));
+		rtw_msleep_os(20);
+	}
+
+	if (_TRUE == abort) {
+		if (check_fwstate(pmlmepriv, _FW_UNDER_SURVEY)) {
+			if (!RTW_CANNOT_RUN(adapter))
+				RTW_INFO(FUNC_NDEV_FMT"waiting for scan_abort time out!\n", FUNC_NDEV_ARG(adapter->pnetdev));
+#ifdef CONFIG_PLATFORM_MSTAR
+			/*_clr_fwstate_(pmlmepriv, _FW_UNDER_SURVEY);*/
+			set_survey_timer(pmlmeext, 0);
+			mlme_set_scan_to_timer(pmlmepriv, 50);
+#endif
+			rtw_indicate_scan_done(adapter, _TRUE);
+		}
+	}
+
+	pmlmeext->scan_abort = _FALSE;
+	pass_ms = rtw_get_passing_time_ms(start);
+
+	return pass_ms;
+
+}
+
+void rtw_scan_wait_completed(_adapter *adapter)
+{
+	struct mlme_ext_priv *pmlmeext = &adapter->mlmeextpriv;
+	struct ss_res *ss = &pmlmeext->sitesurvey_res;
+
+	_rtw_wait_scan_done(adapter, _FALSE, ss->scan_timeout_ms);
+}
+
+u32 rtw_scan_abort_timeout(_adapter *adapter, u32 timeout_ms)
+{
+	return _rtw_wait_scan_done(adapter, _TRUE, timeout_ms);
+}
+
+void rtw_scan_abort_no_wait(_adapter *adapter)
+{
+	struct mlme_priv *pmlmepriv = &(adapter->mlmepriv);
+	struct mlme_ext_priv *pmlmeext = &(adapter->mlmeextpriv);
+
+	if (check_fwstate(pmlmepriv, _FW_UNDER_SURVEY))
+		pmlmeext->scan_abort = _TRUE;
+}
+
+void rtw_scan_abort(_adapter *adapter)
+{
+	rtw_scan_abort_timeout(adapter, 200);
+}
+
+static u32 _rtw_wait_join_done(_adapter *adapter, u8 abort, u32 timeout_ms)
+{
+	systime start;
+	u32 pass_ms;
+	struct mlme_priv *pmlmepriv = &(adapter->mlmepriv);
+	struct mlme_ext_priv *pmlmeext = &(adapter->mlmeextpriv);
+
+	start = rtw_get_current_time();
+
+	pmlmeext->join_abort = abort;
+	if (abort)
+		set_link_timer(pmlmeext, 1);
+
+	while (rtw_get_passing_time_ms(start) <= timeout_ms
+		&& (check_fwstate(pmlmepriv, _FW_UNDER_LINKING)
+			#ifdef CONFIG_IOCTL_CFG80211
+			|| rtw_cfg80211_is_connect_requested(adapter)
+			#endif
+			)
+	) {
+		if (RTW_CANNOT_RUN(adapter))
+			break;
+
+		RTW_INFO(FUNC_ADPT_FMT" linking...\n", FUNC_ADPT_ARG(adapter));
+		rtw_msleep_os(20);
+	}
+
+	if (abort) {
+		if (check_fwstate(pmlmepriv, _FW_UNDER_LINKING)
+			#ifdef CONFIG_IOCTL_CFG80211
+			|| rtw_cfg80211_is_connect_requested(adapter)
+			#endif
+		) {
+			if (!RTW_CANNOT_RUN(adapter))
+				RTW_INFO(FUNC_ADPT_FMT" waiting for join_abort time out!\n", FUNC_ADPT_ARG(adapter));
+		}
+	}
+
+	pmlmeext->join_abort = 0;
+	pass_ms = rtw_get_passing_time_ms(start);
+
+	return pass_ms;
+}
+
+u32 rtw_join_abort_timeout(_adapter *adapter, u32 timeout_ms)
+{
+	return _rtw_wait_join_done(adapter, _TRUE, timeout_ms);
+}
+
+static struct sta_info *rtw_joinbss_update_stainfo(_adapter *padapter, struct wlan_network *pnetwork)
+{
+	int i;
+	struct sta_info *psta = NULL;
+	struct recv_reorder_ctrl *preorder_ctrl;
+	struct sta_priv *pstapriv = &padapter->stapriv;
+	struct mlme_ext_priv	*pmlmeext = &padapter->mlmeextpriv;
+
+	psta = rtw_get_stainfo(pstapriv, pnetwork->network.MacAddress);
+	if (psta == NULL)
+		psta = rtw_alloc_stainfo(pstapriv, pnetwork->network.MacAddress);
+
+	if (psta) { /* update ptarget_sta */
+		RTW_INFO("%s\n", __FUNCTION__);
+
+		psta->cmn.aid  = pnetwork->join_res;
+
+		update_sta_info(padapter, psta);
+
+		/* update station supportRate */
+		psta->bssratelen = rtw_get_rateset_len(pnetwork->network.SupportedRates);
+		_rtw_memcpy(psta->bssrateset, pnetwork->network.SupportedRates, psta->bssratelen);
+		rtw_hal_update_sta_ra_info(padapter, psta);
+
+		psta->wireless_mode = pmlmeext->cur_wireless_mode;
+		rtw_hal_update_sta_wset(padapter, psta);
+
+		/* sta mode */
+		rtw_hal_set_odm_var(padapter, HAL_ODM_STA_INFO, psta, _TRUE);
+
+		/* security related */
+#ifdef CONFIG_RTW_80211R
+		if ((padapter->securitypriv.dot11AuthAlgrthm == dot11AuthAlgrthm_8021X)
+			&& (psta->ft_pairwise_key_installed == _FALSE)) {
+#else
+		if (padapter->securitypriv.dot11AuthAlgrthm == dot11AuthAlgrthm_8021X) {
+#endif
+			u8 *ie;
+			sint ie_len;
+			u8 mfp_opt = MFP_NO;
+
+			padapter->securitypriv.binstallGrpkey = _FALSE;
+			padapter->securitypriv.busetkipkey = _FALSE;
+			padapter->securitypriv.bgrpkey_handshake = _FALSE;
+
+			ie = rtw_get_ie(pnetwork->network.IEs + _BEACON_IE_OFFSET_, WLAN_EID_RSN
+				, &ie_len, (pnetwork->network.IELength - _BEACON_IE_OFFSET_));
+			if (ie && ie_len > 0
+				&& rtw_parse_wpa2_ie(ie, ie_len + 2, NULL, NULL, NULL, &mfp_opt) == _SUCCESS
+			) {
+				if (padapter->securitypriv.mfp_opt >= MFP_OPTIONAL && mfp_opt >= MFP_OPTIONAL)
+					psta->flags |= WLAN_STA_MFP;
+			}
+
+			psta->ieee8021x_blocked = _TRUE;
+			psta->dot118021XPrivacy = padapter->securitypriv.dot11PrivacyAlgrthm;
+
+			_rtw_memset((u8 *)&psta->dot118021x_UncstKey, 0, sizeof(union Keytype));
+			_rtw_memset((u8 *)&psta->dot11tkiprxmickey, 0, sizeof(union Keytype));
+			_rtw_memset((u8 *)&psta->dot11tkiptxmickey, 0, sizeof(union Keytype));
+		}
+
+		/*	Commented by Albert 2012/07/21 */
+		/*	When doing the WPS, the wps_ie_len won't equal to 0 */
+		/*	And the Wi-Fi driver shouldn't allow the data packet to be tramsmitted. */
+		if (padapter->securitypriv.wps_ie_len != 0) {
+			psta->ieee8021x_blocked = _TRUE;
+			padapter->securitypriv.wps_ie_len = 0;
+		}
+
+
+		/* for A-MPDU Rx reordering buffer control for sta_info */
+		/* if A-MPDU Rx is enabled, reseting  rx_ordering_ctrl wstart_b(indicate_seq) to default value=0xffff */
+		/* todo: check if AP can send A-MPDU packets */
+		for (i = 0; i < 16 ; i++) {
+			/* preorder_ctrl = &precvpriv->recvreorder_ctrl[i]; */
+			preorder_ctrl = &psta->recvreorder_ctrl[i];
+			preorder_ctrl->enable = _FALSE;
+			preorder_ctrl->indicate_seq = 0xffff;
+			#ifdef DBG_RX_SEQ
+			RTW_INFO("DBG_RX_SEQ "FUNC_ADPT_FMT" tid:%u SN_CLEAR indicate_seq:%u\n"
+				, FUNC_ADPT_ARG(padapter), i, preorder_ctrl->indicate_seq);
+			#endif
+			preorder_ctrl->wend_b = 0xffff;
+			preorder_ctrl->wsize_b = 64;/* max_ampdu_sz; */ /* ex. 32(kbytes) -> wsize_b=32 */
+			preorder_ctrl->ampdu_size = RX_AMPDU_SIZE_INVALID;
+		}
+	}
+
+#ifdef	CONFIG_RTW_80211K
+	_rtw_memcpy(&psta->rm_en_cap, pnetwork->network.PhyInfo.rm_en_cap, 5);
+#endif
+
+	return psta;
+
+}
+
+/* pnetwork : returns from rtw_joinbss_event_callback
+ * ptarget_wlan: found from scanned_queue */
+static void rtw_joinbss_update_network(_adapter *padapter, struct wlan_network *ptarget_wlan, struct wlan_network  *pnetwork)
+{
+	struct mlme_priv	*pmlmepriv = &(padapter->mlmepriv);
+	struct security_priv *psecuritypriv = &padapter->securitypriv;
+	struct wlan_network  *cur_network = &(pmlmepriv->cur_network);
+	sint tmp_fw_state = 0x0;
+
+	RTW_INFO("%s\n", __FUNCTION__);
+
+	/* why not use ptarget_wlan?? */
+	_rtw_memcpy(&cur_network->network, &pnetwork->network, pnetwork->network.Length);
+	/* some IEs in pnetwork is wrong, so we should use ptarget_wlan IEs */
+	cur_network->network.IELength = ptarget_wlan->network.IELength;
+	_rtw_memcpy(&cur_network->network.IEs[0], &ptarget_wlan->network.IEs[0], MAX_IE_SZ);
+
+	cur_network->aid = pnetwork->join_res;
+
+
+#ifdef CONFIG_NEW_SIGNAL_STAT_PROCESS
+	rtw_set_signal_stat_timer(&padapter->recvpriv);
+#endif
+	padapter->recvpriv.signal_strength = ptarget_wlan->network.PhyInfo.SignalStrength;
+	padapter->recvpriv.signal_qual = ptarget_wlan->network.PhyInfo.SignalQuality;
+	/* the ptarget_wlan->network.Rssi is raw data, we use ptarget_wlan->network.PhyInfo.SignalStrength instead (has scaled) */
+	padapter->recvpriv.rssi = translate_percentage_to_dbm(ptarget_wlan->network.PhyInfo.SignalStrength);
+#if defined(DBG_RX_SIGNAL_DISPLAY_PROCESSING) && 1
+	RTW_INFO(FUNC_ADPT_FMT" signal_strength:%3u, rssi:%3d, signal_qual:%3u"
+		 "\n"
+		 , FUNC_ADPT_ARG(padapter)
+		 , padapter->recvpriv.signal_strength
+		 , padapter->recvpriv.rssi
+		 , padapter->recvpriv.signal_qual
+		);
+#endif
+#ifdef CONFIG_NEW_SIGNAL_STAT_PROCESS
+	rtw_set_signal_stat_timer(&padapter->recvpriv);
+#endif
+
+	/* update fw_state */ /* will clr _FW_UNDER_LINKING here indirectly */
+
+	switch (pnetwork->network.InfrastructureMode) {
+	case Ndis802_11Infrastructure:
+		/* Check encryption */
+		if (psecuritypriv->dot11AuthAlgrthm == dot11AuthAlgrthm_8021X)
+			tmp_fw_state = tmp_fw_state | WIFI_UNDER_KEY_HANDSHAKE;
+
+		if (check_fwstate(pmlmepriv, WIFI_UNDER_WPS))
+			tmp_fw_state = tmp_fw_state | WIFI_UNDER_WPS;
+
+		init_fwstate(pmlmepriv, WIFI_STATION_STATE | tmp_fw_state);
+
+		break;
+	case Ndis802_11IBSS:
+		/*pmlmepriv->fw_state = WIFI_ADHOC_STATE;*/
+		init_fwstate(pmlmepriv, WIFI_ADHOC_STATE);
+		break;
+	default:
+		/*pmlmepriv->fw_state = WIFI_NULL_STATE;*/
+		init_fwstate(pmlmepriv, WIFI_NULL_STATE);
+		break;
+	}
+
+	rtw_update_protection(padapter, (cur_network->network.IEs) + sizeof(NDIS_802_11_FIXED_IEs),
+			      (cur_network->network.IELength));
+
+#ifdef CONFIG_80211N_HT
+	rtw_update_ht_cap(padapter, cur_network->network.IEs, cur_network->network.IELength, (u8) cur_network->network.Configuration.DSConfig);
+#endif
+}
+
+/* Notes: the fucntion could be > passive_level (the same context as Rx tasklet)
+ * pnetwork : returns from rtw_joinbss_event_callback
+ * ptarget_wlan: found from scanned_queue
+ * if join_res > 0, for (fw_state==WIFI_STATION_STATE), we check if  "ptarget_sta" & "ptarget_wlan" exist.
+ * if join_res > 0, for (fw_state==WIFI_ADHOC_STATE), we only check if "ptarget_wlan" exist.
+ * if join_res > 0, update "cur_network->network" from "pnetwork->network" if (ptarget_wlan !=NULL).
+ */
+/* #define REJOIN */
+void rtw_joinbss_event_prehandle(_adapter *adapter, u8 *pbuf, u16 status)
+{
+	_irqL irqL;
+	static u8 retry = 0;
+	struct sta_info *ptarget_sta = NULL, *pcur_sta = NULL;
+	struct	sta_priv *pstapriv = &adapter->stapriv;
+	struct	mlme_priv	*pmlmepriv = &(adapter->mlmepriv);
+	struct wlan_network	*pnetwork	= (struct wlan_network *)pbuf;
+	struct wlan_network	*cur_network = &(pmlmepriv->cur_network);
+	struct wlan_network	*pcur_wlan = NULL, *ptarget_wlan = NULL;
+	unsigned int		the_same_macaddr = _FALSE;
+
+
+#ifdef CONFIG_RTL8712
+	/* endian_convert */
+	pnetwork->join_res = le32_to_cpu(pnetwork->join_res);
+	pnetwork->network_type = le32_to_cpu(pnetwork->network_type);
+	pnetwork->network.Length = le32_to_cpu(pnetwork->network.Length);
+	pnetwork->network.Ssid.SsidLength = le32_to_cpu(pnetwork->network.Ssid.SsidLength);
+	pnetwork->network.Privacy = le32_to_cpu(pnetwork->network.Privacy);
+	pnetwork->network.Rssi = le32_to_cpu(pnetwork->network.Rssi);
+	pnetwork->network.NetworkTypeInUse = le32_to_cpu(pnetwork->network.NetworkTypeInUse) ;
+	pnetwork->network.Configuration.ATIMWindow = le32_to_cpu(pnetwork->network.Configuration.ATIMWindow);
+	pnetwork->network.Configuration.BeaconPeriod = le32_to_cpu(pnetwork->network.Configuration.BeaconPeriod);
+	pnetwork->network.Configuration.DSConfig = le32_to_cpu(pnetwork->network.Configuration.DSConfig);
+	pnetwork->network.Configuration.FHConfig.DwellTime = le32_to_cpu(pnetwork->network.Configuration.FHConfig.DwellTime);
+	pnetwork->network.Configuration.FHConfig.HopPattern = le32_to_cpu(pnetwork->network.Configuration.FHConfig.HopPattern);
+	pnetwork->network.Configuration.FHConfig.HopSet = le32_to_cpu(pnetwork->network.Configuration.FHConfig.HopSet);
+	pnetwork->network.Configuration.FHConfig.Length = le32_to_cpu(pnetwork->network.Configuration.FHConfig.Length);
+	pnetwork->network.Configuration.Length = le32_to_cpu(pnetwork->network.Configuration.Length);
+	pnetwork->network.InfrastructureMode = le32_to_cpu(pnetwork->network.InfrastructureMode);
+	pnetwork->network.IELength = le32_to_cpu(pnetwork->network.IELength);
+#endif
+
+
+	rtw_get_encrypt_decrypt_from_registrypriv(adapter);
+
+
+
+	the_same_macaddr = _rtw_memcmp(pnetwork->network.MacAddress, cur_network->network.MacAddress, ETH_ALEN);
+
+	pnetwork->network.Length = get_WLAN_BSSID_EX_sz(&pnetwork->network);
+	if (pnetwork->network.Length > sizeof(WLAN_BSSID_EX)) {
+		goto ignore_joinbss_callback;
+	}
+
+	_enter_critical_bh(&pmlmepriv->lock, &irqL);
+
+	pmlmepriv->LinkDetectInfo.TrafficTransitionCount = 0;
+	pmlmepriv->LinkDetectInfo.LowPowerTransitionCount = 0;
+
+
+	if (pnetwork->join_res > 0) {
+		_enter_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);
+		retry = 0;
+		if (check_fwstate(pmlmepriv, _FW_UNDER_LINKING)) {
+			/* s1. find ptarget_wlan */
+			if (check_fwstate(pmlmepriv, _FW_LINKED)) {
+				if (the_same_macaddr == _TRUE)
+					ptarget_wlan = _rtw_find_network(&pmlmepriv->scanned_queue, cur_network->network.MacAddress);
+				else {
+					pcur_wlan = _rtw_find_network(&pmlmepriv->scanned_queue, cur_network->network.MacAddress);
+					if (pcur_wlan)
+						pcur_wlan->fixed = _FALSE;
+
+					pcur_sta = rtw_get_stainfo(pstapriv, cur_network->network.MacAddress);
+					if (pcur_sta) {
+						/* _enter_critical_bh(&(pstapriv->sta_hash_lock), &irqL2); */
+						rtw_free_stainfo(adapter,  pcur_sta);
+						/* _exit_critical_bh(&(pstapriv->sta_hash_lock), &irqL2); */
+					}
+
+					ptarget_wlan = _rtw_find_network(&pmlmepriv->scanned_queue, pnetwork->network.MacAddress);
+					if (check_fwstate(pmlmepriv, WIFI_STATION_STATE) == _TRUE) {
+						if (ptarget_wlan)
+							ptarget_wlan->fixed = _TRUE;
+					}
+				}
+
+			} else {
+				ptarget_wlan = _rtw_find_same_network(&pmlmepriv->scanned_queue, pnetwork);
+				if (check_fwstate(pmlmepriv, WIFI_STATION_STATE) == _TRUE) {
+					if (ptarget_wlan)
+						ptarget_wlan->fixed = _TRUE;
+				}
+			}
+
+			/* s2. update cur_network */
+			if (ptarget_wlan)
+				rtw_joinbss_update_network(adapter, ptarget_wlan, pnetwork);
+			else {
+				RTW_PRINT("Can't find ptarget_wlan when joinbss_event callback\n");
+				_exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);
+				goto ignore_joinbss_callback;
+			}
+
+
+			/* s3. find ptarget_sta & update ptarget_sta after update cur_network only for station mode */
+			if (check_fwstate(pmlmepriv, WIFI_STATION_STATE) == _TRUE) {
+				ptarget_sta = rtw_joinbss_update_stainfo(adapter, pnetwork);
+				if (ptarget_sta == NULL) {
+					RTW_ERR("Can't update stainfo when joinbss_event callback\n");
+					_exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);
+					goto ignore_joinbss_callback;
+				}
+			}
+
+			/* s4. indicate connect			 */
+			if (MLME_IS_STA(adapter) || MLME_IS_ADHOC(adapter)) {
+				pmlmepriv->cur_network_scanned = ptarget_wlan;
+				rtw_indicate_connect(adapter);
+			}
+
+			/* s5. Cancle assoc_timer					 */
+			_cancel_timer_ex(&pmlmepriv->assoc_timer);
+
+
+		} else {
+			_exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);
+			goto ignore_joinbss_callback;
+		}
+
+		_exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);
+
+	} else if (pnetwork->join_res == -4) {
+		rtw_reset_securitypriv(adapter);
+		pmlmepriv->join_status = status;
+		_set_timer(&pmlmepriv->assoc_timer, 1);
+
+		/* rtw_free_assoc_resources(adapter, _TRUE); */
+
+		if ((check_fwstate(pmlmepriv, _FW_UNDER_LINKING)) == _TRUE) {
+			_clr_fwstate_(pmlmepriv, _FW_UNDER_LINKING);
+		}
+
+	} else { /* if join_res < 0 (join fails), then try again */
+
+#ifdef REJOIN
+		res = _FAIL;
+		if (retry < 2) {
+			res = rtw_select_and_join_from_scanned_queue(pmlmepriv);
+		}
+
+		if (res == _SUCCESS) {
+			/* extend time of assoc_timer */
+			_set_timer(&pmlmepriv->assoc_timer, MAX_JOIN_TIMEOUT);
+			retry++;
+		} else if (res == 2) { /* there is no need to wait for join */
+			_clr_fwstate_(pmlmepriv, _FW_UNDER_LINKING);
+			rtw_indicate_connect(adapter);
+		} else {
+#endif
+			pmlmepriv->join_status = status;
+			_set_timer(&pmlmepriv->assoc_timer, 1);
+			/* rtw_free_assoc_resources(adapter, _TRUE); */
+			_clr_fwstate_(pmlmepriv, _FW_UNDER_LINKING);
+
+#ifdef REJOIN
+			retry = 0;
+		}
+#endif
+	}
+
+ignore_joinbss_callback:
+	_exit_critical_bh(&pmlmepriv->lock, &irqL);
+}
+
+void rtw_joinbss_event_callback(_adapter *adapter, u8 *pbuf)
+{
+	struct wlan_network	*pnetwork	= (struct wlan_network *)pbuf;
+
+
+	mlmeext_joinbss_event_callback(adapter, pnetwork->join_res);
+
+	rtw_mi_os_xmit_schedule(adapter);
+
+}
+
+void rtw_sta_media_status_rpt(_adapter *adapter, struct sta_info *sta, bool connected)
+{
+	struct macid_ctl_t *macid_ctl = &adapter->dvobj->macid_ctl;
+	bool miracast_enabled = 0;
+	bool miracast_sink = 0;
+	u8 role = H2C_MSR_ROLE_RSVD;
+
+	if (sta == NULL) {
+		RTW_PRINT(FUNC_ADPT_FMT" sta is NULL\n"
+			  , FUNC_ADPT_ARG(adapter));
+		rtw_warn_on(1);
+		return;
+	}
+
+	if (sta->cmn.mac_id >= macid_ctl->num) {
+		RTW_PRINT(FUNC_ADPT_FMT" invalid macid:%u\n"
+			  , FUNC_ADPT_ARG(adapter), sta->cmn.mac_id);
+		rtw_warn_on(1);
+		return;
+	}
+
+	if (!rtw_macid_is_used(macid_ctl, sta->cmn.mac_id)) {
+		RTW_PRINT(FUNC_ADPT_FMT" macid:%u not is used, set connected to 0\n"
+			  , FUNC_ADPT_ARG(adapter), sta->cmn.mac_id);
+		connected = 0;
+		rtw_warn_on(1);
+	}
+
+	if (connected && !rtw_macid_is_bmc(macid_ctl, sta->cmn.mac_id)) {
+		miracast_enabled = STA_OP_WFD_MODE(sta) != 0 && is_miracast_enabled(adapter);
+		miracast_sink = miracast_enabled && (STA_OP_WFD_MODE(sta) & MIRACAST_SINK);
+
+#ifdef CONFIG_TDLS
+		if (sta->tdls_sta_state & TDLS_LINKED_STATE)
+			role = H2C_MSR_ROLE_TDLS;
+		else
+#endif
+		if (MLME_IS_STA(adapter)) {
+			if (MLME_IS_GC(adapter))
+				role = H2C_MSR_ROLE_GO;
+			else
+				role = H2C_MSR_ROLE_AP;
+		} else if (MLME_IS_AP(adapter)) {
+			if (MLME_IS_GO(adapter))
+				role = H2C_MSR_ROLE_GC;
+			else
+				role = H2C_MSR_ROLE_STA;
+		} else if (MLME_IS_ADHOC(adapter) || MLME_IS_ADHOC_MASTER(adapter))
+			role = H2C_MSR_ROLE_ADHOC;
+		else if (MLME_IS_MESH(adapter))
+			role = H2C_MSR_ROLE_MESH;
+
+#ifdef CONFIG_WFD
+		if (role == H2C_MSR_ROLE_GC
+			|| role == H2C_MSR_ROLE_GO
+			|| role == H2C_MSR_ROLE_TDLS
+		) {
+			if (adapter->wfd_info.rtsp_ctrlport
+				|| adapter->wfd_info.tdls_rtsp_ctrlport
+				|| adapter->wfd_info.peer_rtsp_ctrlport)
+				rtw_wfd_st_switch(sta, 1);
+		}
+#endif
+	}
+
+	rtw_hal_set_FwMediaStatusRpt_single_cmd(adapter
+		, connected
+		, miracast_enabled
+		, miracast_sink
+		, role
+		, sta->cmn.mac_id
+	);
+}
+
+u8 rtw_sta_media_status_rpt_cmd(_adapter *adapter, struct sta_info *sta, bool connected)
+{
+	struct cmd_priv	*cmdpriv = &adapter->cmdpriv;
+	struct cmd_obj *cmdobj;
+	struct drvextra_cmd_parm *cmd_parm;
+	struct sta_media_status_rpt_cmd_parm *rpt_parm;
+	u8	res = _SUCCESS;
+
+	cmdobj = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj));
+	if (cmdobj == NULL) {
+		res = _FAIL;
+		goto exit;
+	}
+
+	cmd_parm = (struct drvextra_cmd_parm *)rtw_zmalloc(sizeof(struct drvextra_cmd_parm));
+	if (cmd_parm == NULL) {
+		rtw_mfree((u8 *)cmdobj, sizeof(struct cmd_obj));
+		res = _FAIL;
+		goto exit;
+	}
+
+	rpt_parm = (struct sta_media_status_rpt_cmd_parm *)rtw_zmalloc(sizeof(struct sta_media_status_rpt_cmd_parm));
+	if (rpt_parm == NULL) {
+		rtw_mfree((u8 *)cmdobj, sizeof(struct cmd_obj));
+		rtw_mfree((u8 *)cmd_parm, sizeof(struct drvextra_cmd_parm));
+		res = _FAIL;
+		goto exit;
+	}
+
+	rpt_parm->sta = sta;
+	rpt_parm->connected = connected;
+
+	cmd_parm->ec_id = STA_MSTATUS_RPT_WK_CID;
+	cmd_parm->type = 0;
+	cmd_parm->size = sizeof(struct sta_media_status_rpt_cmd_parm);
+	cmd_parm->pbuf = (u8 *)rpt_parm;
+	init_h2fwcmd_w_parm_no_rsp(cmdobj, cmd_parm, GEN_CMD_CODE(_Set_Drv_Extra));
+
+	res = rtw_enqueue_cmd(cmdpriv, cmdobj);
+
+exit:
+	return res;
+}
+
+inline void rtw_sta_media_status_rpt_cmd_hdl(_adapter *adapter, struct sta_media_status_rpt_cmd_parm *parm)
+{
+	rtw_sta_media_status_rpt(adapter, parm->sta, parm->connected);
+}
+
+void rtw_stassoc_event_callback(_adapter *adapter, u8 *pbuf)
+{
+	_irqL irqL;
+	struct sta_info *psta;
+	struct mlme_priv *pmlmepriv = &(adapter->mlmepriv);
+	struct stassoc_event	*pstassoc	= (struct stassoc_event *)pbuf;
+	struct wlan_network	*cur_network = &(pmlmepriv->cur_network);
+	struct wlan_network	*ptarget_wlan = NULL;
+
+
+#if CONFIG_RTW_MACADDR_ACL
+	if (rtw_access_ctrl(adapter, pstassoc->macaddr) == _FALSE)
+		return;
+#endif
+
+#if defined(CONFIG_AP_MODE) && defined (CONFIG_NATIVEAP_MLME)
+	if (MLME_IS_AP(adapter) || MLME_IS_MESH(adapter)) {
+		psta = rtw_get_stainfo(&adapter->stapriv, pstassoc->macaddr);
+		if (psta) {
+			u8 *passoc_req = NULL;
+			u32 assoc_req_len = 0;
+
+			rtw_sta_media_status_rpt(adapter, psta, 1);
+
+#ifdef CONFIG_MCC_MODE
+			rtw_hal_mcc_update_macid_bitmap(adapter, psta->cmn.mac_id, _TRUE);
+#endif /* CONFIG_MCC_MODE */
+
+#ifndef CONFIG_AUTO_AP_MODE
+			ap_sta_info_defer_update(adapter, psta);
+
+			if (!MLME_IS_MESH(adapter)) {
+				/* report to upper layer */
+				RTW_INFO("indicate_sta_assoc_event to upper layer - hostapd\n");
+				#ifdef CONFIG_IOCTL_CFG80211
+				_enter_critical_bh(&psta->lock, &irqL);
+				if (psta->passoc_req && psta->assoc_req_len > 0) {
+					passoc_req = rtw_zmalloc(psta->assoc_req_len);
+					if (passoc_req) {
+						assoc_req_len = psta->assoc_req_len;
+						_rtw_memcpy(passoc_req, psta->passoc_req, assoc_req_len);
+
+						rtw_mfree(psta->passoc_req , psta->assoc_req_len);
+						psta->passoc_req = NULL;
+						psta->assoc_req_len = 0;
+					}
+				}
+				_exit_critical_bh(&psta->lock, &irqL);
+
+				if (passoc_req && assoc_req_len > 0) {
+					rtw_cfg80211_indicate_sta_assoc(adapter, passoc_req, assoc_req_len);
+					rtw_mfree(passoc_req, assoc_req_len);
+				}
+				#else /* !CONFIG_IOCTL_CFG80211	 */
+				rtw_indicate_sta_assoc_event(adapter, psta);
+				#endif /* !CONFIG_IOCTL_CFG80211 */
+			}
+#endif /* !CONFIG_AUTO_AP_MODE */
+
+#ifdef CONFIG_BEAMFORMING
+			beamforming_wk_cmd(adapter, BEAMFORMING_CTRL_ENTER, (u8 *)psta, sizeof(struct sta_info), 0);
+#endif/*CONFIG_BEAMFORMING*/
+			if (is_wep_enc(adapter->securitypriv.dot11PrivacyAlgrthm))
+				rtw_ap_wep_pk_setting(adapter, psta);
+		}
+		goto exit;
+	}
+#endif /* defined (CONFIG_AP_MODE) && defined (CONFIG_NATIVEAP_MLME) */
+
+	/* for AD-HOC mode */
+	psta = rtw_get_stainfo(&adapter->stapriv, pstassoc->macaddr);
+	if (psta == NULL) {
+		RTW_ERR(FUNC_ADPT_FMT" get no sta_info with "MAC_FMT"\n"
+			, FUNC_ADPT_ARG(adapter), MAC_ARG(pstassoc->macaddr));
+		rtw_warn_on(1);
+		goto exit;
+	}
+
+	rtw_sta_media_status_rpt(adapter, psta, 1);
+
+	if (adapter->securitypriv.dot11AuthAlgrthm == dot11AuthAlgrthm_8021X)
+		psta->dot118021XPrivacy = adapter->securitypriv.dot11PrivacyAlgrthm;
+
+
+	psta->ieee8021x_blocked = _FALSE;
+
+	_enter_critical_bh(&pmlmepriv->lock, &irqL);
+
+	if ((check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE) == _TRUE) ||
+	    (check_fwstate(pmlmepriv, WIFI_ADHOC_STATE) == _TRUE)) {
+		if (adapter->stapriv.asoc_sta_count == 2) {
+			_enter_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);
+			ptarget_wlan = _rtw_find_network(&pmlmepriv->scanned_queue, cur_network->network.MacAddress);
+			pmlmepriv->cur_network_scanned = ptarget_wlan;
+			if (ptarget_wlan)
+				ptarget_wlan->fixed = _TRUE;
+			_exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);
+			/* a sta + bc/mc_stainfo (not Ibss_stainfo) */
+			rtw_indicate_connect(adapter);
+		}
+	}
+
+	_exit_critical_bh(&pmlmepriv->lock, &irqL);
+
+
+	mlmeext_sta_add_event_callback(adapter, psta);
+
+#ifdef CONFIG_RTL8711
+	/* submit SetStaKey_cmd to tell fw, fw will allocate an CAM entry for this sta	 */
+	rtw_setstakey_cmd(adapter, psta, GROUP_KEY, _TRUE);
+#endif
+
+exit:
+	return;
+}
+
+#ifdef CONFIG_IEEE80211W
+void rtw_sta_timeout_event_callback(_adapter *adapter, u8 *pbuf)
+{
+	_irqL irqL;
+	struct sta_info *psta;
+	struct stadel_event *pstadel = (struct stadel_event *)pbuf;
+	struct sta_priv *pstapriv = &adapter->stapriv;
+
+
+	psta = rtw_get_stainfo(&adapter->stapriv, pstadel->macaddr);
+
+	if (psta) {
+		u8 updated = _FALSE;
+
+		_enter_critical_bh(&pstapriv->asoc_list_lock, &irqL);
+		if (rtw_is_list_empty(&psta->asoc_list) == _FALSE) {
+			rtw_list_delete(&psta->asoc_list);
+			pstapriv->asoc_list_cnt--;
+			updated = ap_free_sta(adapter, psta, _TRUE, WLAN_REASON_PREV_AUTH_NOT_VALID, _TRUE);
+		}
+		_exit_critical_bh(&pstapriv->asoc_list_lock, &irqL);
+
+		associated_clients_update(adapter, updated, STA_INFO_UPDATE_ALL);
+	}
+
+
+
+}
+#endif /* CONFIG_IEEE80211W */
+
+#ifdef CONFIG_RTW_80211R
+void rtw_ft_info_init(struct ft_roam_info *pft)
+{
+	_rtw_memset(pft, 0, sizeof(struct ft_roam_info));
+	pft->ft_flags = 0
+		| RTW_FT_EN
+		| RTW_FT_OTD_EN
+#ifdef CONFIG_RTW_BTM_ROAM
+		| RTW_FT_BTM_ROAM
+#endif
+		;
+	pft->ft_updated_bcn = _FALSE;
+}
+
+u8 rtw_ft_chk_roaming_candidate(
+	_adapter *padapter, struct wlan_network *competitor)
+{
+	u8 *pmdie;
+	u32 mdie_len = 0;
+	struct ft_roam_info *pft_roam = &(padapter->mlmepriv.ft_roam);
+
+	if (!(pmdie = rtw_get_ie(&competitor->network.IEs[12],
+			_MDIE_, &mdie_len, competitor->network.IELength-12)))
+		return _FALSE;
+
+	if (!_rtw_memcmp(&pft_roam->mdid, (pmdie+2), 2))
+		return _FALSE;
+
+	/*The candidate don't support over-the-DS*/
+	if (rtw_ft_valid_otd_candidate(padapter, pmdie)) {
+		RTW_INFO("FT: ignore the candidate("
+			MAC_FMT ") for over-the-DS\n", 
+			MAC_ARG(competitor->network.MacAddress));
+			rtw_ft_clr_flags(padapter, RTW_FT_PEER_OTD_EN);
+		return _FALSE;	
+	}
+
+	return _TRUE;
+}
+
+void rtw_ft_update_stainfo(_adapter *padapter, WLAN_BSSID_EX *pnetwork)
+{
+	struct sta_priv		*pstapriv = &padapter->stapriv;
+	struct sta_info		*psta = NULL;
+
+	psta = rtw_get_stainfo(pstapriv, pnetwork->MacAddress);
+	if (psta == NULL)
+		psta = rtw_alloc_stainfo(pstapriv, pnetwork->MacAddress);
+
+	if (padapter->securitypriv.dot11AuthAlgrthm == dot11AuthAlgrthm_8021X) {
+
+		padapter->securitypriv.binstallGrpkey = _FALSE;
+		padapter->securitypriv.busetkipkey = _FALSE;
+		padapter->securitypriv.bgrpkey_handshake = _FALSE;
+
+		psta->ieee8021x_blocked = _TRUE;
+		psta->dot118021XPrivacy = padapter->securitypriv.dot11PrivacyAlgrthm;
+
+		_rtw_memset((u8 *)&psta->dot118021x_UncstKey, 0, sizeof(union Keytype));
+		_rtw_memset((u8 *)&psta->dot11tkiprxmickey, 0, sizeof(union Keytype));
+		_rtw_memset((u8 *)&psta->dot11tkiptxmickey, 0, sizeof(union Keytype));
+	}
+
+}
+
+void rtw_ft_reassoc_event_callback(_adapter *padapter, u8 *pbuf)
+{
+	struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
+	struct stassoc_event *pstassoc = (struct stassoc_event *)pbuf;
+	struct ft_roam_info *pft_roam = &(pmlmepriv->ft_roam);
+	struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv);
+	struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
+	WLAN_BSSID_EX *pnetwork = (WLAN_BSSID_EX *)&(pmlmeinfo->network);
+	struct cfg80211_ft_event_params ft_evt_parms;
+	_irqL irqL;
+
+	_rtw_memset(&ft_evt_parms, 0, sizeof(ft_evt_parms));
+	rtw_ft_update_stainfo(padapter, pnetwork);
+	ft_evt_parms.ies_len = pft_roam->ft_event.ies_len;
+	ft_evt_parms.ies =  rtw_zmalloc(ft_evt_parms.ies_len);
+	if (ft_evt_parms.ies)
+		_rtw_memcpy((void *)ft_evt_parms.ies, pft_roam->ft_event.ies, ft_evt_parms.ies_len);
+	 else
+		goto err_2;
+
+	ft_evt_parms.target_ap = rtw_zmalloc(ETH_ALEN);
+	if (ft_evt_parms.target_ap)
+		_rtw_memcpy((void *)ft_evt_parms.target_ap, pstassoc->macaddr, ETH_ALEN);
+	else
+		goto err_1;
+
+	ft_evt_parms.ric_ies = pft_roam->ft_event.ric_ies;
+	ft_evt_parms.ric_ies_len = pft_roam->ft_event.ric_ies_len;
+
+	rtw_ft_lock_set_status(padapter, RTW_FT_AUTHENTICATED_STA, &irqL);
+	rtw_cfg80211_ft_event(padapter, &ft_evt_parms);
+	RTW_INFO("%s: to "MAC_FMT"\n", __func__, MAC_ARG(ft_evt_parms.target_ap));
+
+	rtw_mfree((u8 *)pft_roam->ft_event.target_ap, ETH_ALEN);
+err_1:
+	rtw_mfree((u8 *)ft_evt_parms.ies, ft_evt_parms.ies_len);
+err_2:
+	return;
+}
+#endif
+
+#if defined(CONFIG_RTW_WNM) || defined(CONFIG_RTW_80211K)
+void rtw_roam_nb_info_init(_adapter *padapter)
+{
+	struct roam_nb_info *pnb = &(padapter->mlmepriv.nb_info);
+	
+	_rtw_memset(&pnb->nb_rpt, 0, sizeof(pnb->nb_rpt));
+	_rtw_memset(&pnb->nb_rpt_ch_list, 0, sizeof(pnb->nb_rpt_ch_list));
+	_rtw_memset(&pnb->roam_target_addr, 0, ETH_ALEN);
+	pnb->nb_rpt_valid = _FALSE;
+	pnb->nb_rpt_ch_list_num = 0;
+	pnb->preference_en = _FALSE;
+	pnb->nb_rpt_is_same = _TRUE;
+	pnb->last_nb_rpt_entries = 0;
+#ifdef CONFIG_RTW_WNM
+	rtw_init_timer(&pnb->roam_scan_timer, 
+		padapter, rtw_wnm_roam_scan_hdl, 
+		padapter);
+#endif
+}
+
+u8 rtw_roam_nb_scan_list_set(
+	_adapter *padapter, struct sitesurvey_parm *pparm)
+{
+	u8 ret = _FALSE;
+	u32 i;
+	struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
+	struct roam_nb_info *pnb = &(pmlmepriv->nb_info);
+
+	if (!rtw_chk_roam_flags(padapter, RTW_ROAM_ACTIVE))
+		return ret;
+
+	if (!pmlmepriv->need_to_roam)
+		return ret;
+
+	if ((!pmlmepriv->nb_info.nb_rpt_valid) || (!pnb->nb_rpt_ch_list_num))
+		return ret;
+
+	if (!pparm)
+		return ret;
+
+	rtw_init_sitesurvey_parm(padapter, pparm);
+	if (rtw_roam_busy_scan(padapter, pnb)) {
+		pparm->ch_num = 1;
+		pparm->ch[pmlmepriv->ch_cnt].hw_value = 
+			pnb->nb_rpt_ch_list[pmlmepriv->ch_cnt].hw_value;
+		pmlmepriv->ch_cnt++;
+		ret = _TRUE;
+		if (pmlmepriv->ch_cnt == pnb->nb_rpt_ch_list_num) {
+			pmlmepriv->nb_info.nb_rpt_valid = _FALSE;
+			pmlmepriv->ch_cnt = 0;
+		}
+		goto set_bssid_list;
+	}
+
+	pparm->ch_num = (pnb->nb_rpt_ch_list_num > RTW_CHANNEL_SCAN_AMOUNT)?
+		(RTW_CHANNEL_SCAN_AMOUNT):(pnb->nb_rpt_ch_list_num);
+	for (i=0; i<pparm->ch_num; i++) {
+		pparm->ch[i].hw_value = pnb->nb_rpt_ch_list[i].hw_value;
+		pparm->ch[i].flags = RTW_IEEE80211_CHAN_PASSIVE_SCAN;
+	}
+
+	pmlmepriv->nb_info.nb_rpt_valid = _FALSE;
+	pmlmepriv->ch_cnt = 0;		
+	ret = _TRUE;
+
+set_bssid_list:
+	rtw_set_802_11_bssid_list_scan(padapter, pparm);
+	return ret;
+}
+#endif
+
+void rtw_sta_mstatus_disc_rpt(_adapter *adapter, u8 mac_id)
+{
+	struct macid_ctl_t *macid_ctl = &adapter->dvobj->macid_ctl;
+
+	if (mac_id >= 0 && mac_id < macid_ctl->num) {
+		u8 id_is_shared = mac_id == RTW_DEFAULT_MGMT_MACID; /* TODO: real shared macid judgment */
+
+		RTW_INFO(FUNC_ADPT_FMT" - mac_id=%d%s\n", FUNC_ADPT_ARG(adapter)
+			, mac_id, id_is_shared ? " shared" : "");
+
+		if (!id_is_shared) {
+			rtw_hal_set_FwMediaStatusRpt_single_cmd(adapter, 0, 0, 0, 0, mac_id);
+			/*
+			 * For safety, prevent from keeping macid sleep.
+			 * If we can sure all power mode enter/leave are paired,
+			 * this check can be removed.
+			 * Lucas@20131113
+			 */
+			/* wakeup macid after disconnect. */
+			/*if (MLME_IS_STA(adapter))*/
+			rtw_hal_macid_wakeup(adapter, mac_id);
+		}
+	} else {
+		RTW_PRINT(FUNC_ADPT_FMT" invalid macid:%u\n"
+			  , FUNC_ADPT_ARG(adapter), mac_id);
+		rtw_warn_on(1);
+	}
+}
+void rtw_sta_mstatus_report(_adapter *adapter)
+{
+	struct mlme_priv *pmlmepriv = &adapter->mlmepriv;
+	struct wlan_network *tgt_network = &pmlmepriv->cur_network;
+	struct sta_info *psta = NULL;
+
+	if (check_fwstate(pmlmepriv, WIFI_STATION_STATE) && check_fwstate(pmlmepriv, WIFI_ASOC_STATE)) {
+		psta = rtw_get_stainfo(&adapter->stapriv, tgt_network->network.MacAddress);
+		if (psta)
+			rtw_sta_mstatus_disc_rpt(adapter, psta->cmn.mac_id);
+		else {
+			RTW_INFO("%s "ADPT_FMT" - mac_addr: "MAC_FMT" psta == NULL\n", __func__, ADPT_ARG(adapter), MAC_ARG(tgt_network->network.MacAddress));
+			rtw_warn_on(1);
+		}
+	}
+}
+
+void rtw_stadel_event_callback(_adapter *adapter, u8 *pbuf)
+{
+	_irqL irqL, irqL2;
+
+	struct sta_info *psta;
+	struct wlan_network *pwlan = NULL;
+	WLAN_BSSID_EX    *pdev_network = NULL;
+	u8 *pibss = NULL;
+	struct	mlme_priv	*pmlmepriv = &(adapter->mlmepriv);
+	struct	stadel_event *pstadel	= (struct stadel_event *)pbuf;
+	struct wlan_network *tgt_network = &(pmlmepriv->cur_network);
+
+	RTW_INFO("%s(mac_id=%d)=" MAC_FMT "\n", __func__, pstadel->mac_id, MAC_ARG(pstadel->macaddr));
+	rtw_sta_mstatus_disc_rpt(adapter, pstadel->mac_id);
+
+#ifdef CONFIG_MCC_MODE
+	rtw_hal_mcc_update_macid_bitmap(adapter, pstadel->mac_id, _FALSE);
+#endif /* CONFIG_MCC_MODE */
+
+	psta = rtw_get_stainfo(&adapter->stapriv, pstadel->macaddr);
+
+	if (psta == NULL) {
+		RTW_INFO("%s(mac_id=%d)=" MAC_FMT " psta == NULL\n", __func__, pstadel->mac_id, MAC_ARG(pstadel->macaddr));
+		/*rtw_warn_on(1);*/
+	}
+
+	if (psta)
+		rtw_wfd_st_switch(psta, 0);
+
+	if (MLME_IS_MESH(adapter)) {
+		rtw_free_stainfo(adapter, psta);
+		return;
+	}
+
+	if (MLME_IS_AP(adapter)) {
+#ifdef CONFIG_IOCTL_CFG80211
+#ifdef COMPAT_KERNEL_RELEASE
+
+#elif (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 37)) || defined(CONFIG_CFG80211_FORCE_COMPATIBLE_2_6_37_UNDER)
+		rtw_cfg80211_indicate_sta_disassoc(adapter, pstadel->macaddr, *(u16 *)pstadel->rsvd);
+#endif /* (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 37)) || defined(CONFIG_CFG80211_FORCE_COMPATIBLE_2_6_37_UNDER) */
+#endif /* CONFIG_IOCTL_CFG80211 */
+
+		rtw_free_stainfo(adapter, psta);
+
+		return;
+	}
+
+	mlmeext_sta_del_event_callback(adapter);
+
+	_enter_critical_bh(&pmlmepriv->lock, &irqL2);
+
+	if (check_fwstate(pmlmepriv, WIFI_STATION_STATE)) {
+		u16 reason = *((unsigned short *)(pstadel->rsvd));
+		bool roam = _FALSE;
+		struct wlan_network *roam_target = NULL;
+
+#ifdef CONFIG_LAYER2_ROAMING
+#ifdef CONFIG_RTW_80211R
+		if (rtw_ft_roam_expired(adapter, reason))
+			pmlmepriv->ft_roam.ft_roam_on_expired = _TRUE;
+		else
+			pmlmepriv->ft_roam.ft_roam_on_expired = _FALSE;
+#endif
+		if (adapter->registrypriv.wifi_spec == 1)
+			roam = _FALSE;
+		else if (reason == WLAN_REASON_EXPIRATION_CHK && rtw_chk_roam_flags(adapter, RTW_ROAM_ON_EXPIRED))
+			roam = _TRUE;
+		else if (reason == WLAN_REASON_ACTIVE_ROAM && rtw_chk_roam_flags(adapter, RTW_ROAM_ACTIVE)) {
+			roam = _TRUE;
+			roam_target = pmlmepriv->roam_network;
+		}
+#ifdef CONFIG_INTEL_WIDI
+		else if (adapter->mlmepriv.widi_state == INTEL_WIDI_STATE_CONNECTED)
+			roam = _TRUE;
+#endif /* CONFIG_INTEL_WIDI */
+
+		if (roam == _TRUE) {
+			if (rtw_to_roam(adapter) > 0)
+				rtw_dec_to_roam(adapter); /* this stadel_event is caused by roaming, decrease to_roam */
+			else if (rtw_to_roam(adapter) == 0)
+				rtw_set_to_roam(adapter, adapter->registrypriv.max_roaming_times);
+		} else
+			rtw_set_to_roam(adapter, 0);
+#endif /* CONFIG_LAYER2_ROAMING */
+
+		rtw_free_uc_swdec_pending_queue(adapter);
+
+		rtw_free_assoc_resources(adapter, _TRUE);
+		rtw_free_mlme_priv_ie_data(pmlmepriv);
+
+		rtw_indicate_disconnect(adapter, *(u16 *)pstadel->rsvd, pstadel->locally_generated);
+#ifdef CONFIG_INTEL_WIDI
+		if (!rtw_to_roam(adapter))
+			process_intel_widi_disconnect(adapter, 1);
+#endif /* CONFIG_INTEL_WIDI */
+
+		_rtw_roaming(adapter, roam_target);
+	}
+
+	if (check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE) ||
+	    check_fwstate(pmlmepriv, WIFI_ADHOC_STATE)) {
+
+		/* _enter_critical_bh(&(pstapriv->sta_hash_lock), &irqL); */
+		rtw_free_stainfo(adapter,  psta);
+		/* _exit_critical_bh(&(pstapriv->sta_hash_lock), &irqL); */
+
+		if (adapter->stapriv.asoc_sta_count == 1) { /* a sta + bc/mc_stainfo (not Ibss_stainfo) */
+			/* rtw_indicate_disconnect(adapter); */ /* removed@20091105 */
+			_enter_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);
+			/* free old ibss network */
+			/* pwlan = _rtw_find_network(&pmlmepriv->scanned_queue, pstadel->macaddr); */
+			pwlan = _rtw_find_network(&pmlmepriv->scanned_queue, tgt_network->network.MacAddress);
+			if (pwlan) {
+				pwlan->fixed = _FALSE;
+				rtw_free_network_nolock(adapter, pwlan);
+			}
+			_exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);
+			/* re-create ibss */
+			pdev_network = &(adapter->registrypriv.dev_network);
+			pibss = adapter->registrypriv.dev_network.MacAddress;
+
+			_rtw_memcpy(pdev_network, &tgt_network->network, get_WLAN_BSSID_EX_sz(&tgt_network->network));
+
+			_rtw_memset(&pdev_network->Ssid, 0, sizeof(NDIS_802_11_SSID));
+			_rtw_memcpy(&pdev_network->Ssid, &pmlmepriv->assoc_ssid, sizeof(NDIS_802_11_SSID));
+
+			rtw_update_registrypriv_dev_network(adapter);
+
+			rtw_generate_random_ibss(pibss);
+
+			if (check_fwstate(pmlmepriv, WIFI_ADHOC_STATE)) {
+				set_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE);
+				_clr_fwstate_(pmlmepriv, WIFI_ADHOC_STATE);
+			}
+
+			if (rtw_create_ibss_cmd(adapter, 0) != _SUCCESS)
+				RTW_ERR("rtw_create_ibss_cmd FAIL\n");
+
+		}
+
+	}
+
+	_exit_critical_bh(&pmlmepriv->lock, &irqL2);
+
+
+}
+
+
+void rtw_cpwm_event_callback(PADAPTER padapter, u8 *pbuf)
+{
+#ifdef CONFIG_LPS_LCLK
+	struct reportpwrstate_parm *preportpwrstate;
+#endif
+
+
+#ifdef CONFIG_LPS_LCLK
+	preportpwrstate = (struct reportpwrstate_parm *)pbuf;
+	preportpwrstate->state |= (u8)(adapter_to_pwrctl(padapter)->cpwm_tog + 0x80);
+	cpwm_int_hdl(padapter, preportpwrstate);
+#endif
+
+
+}
+
+
+void rtw_wmm_event_callback(PADAPTER padapter, u8 *pbuf)
+{
+
+	WMMOnAssocRsp(padapter);
+
+
+}
+
+/*
+* rtw_join_timeout_handler - Timeout/failure handler for CMD JoinBss
+*/
+void rtw_join_timeout_handler(void *ctx)
+{
+	_adapter *adapter = (_adapter *)ctx;
+	_irqL irqL;
+	struct	mlme_priv *pmlmepriv = &adapter->mlmepriv;
+
+#if 0
+	if (rtw_is_drv_stopped(adapter)) {
+		_rtw_up_sema(&pmlmepriv->assoc_terminate);
+		return;
+	}
+#endif
+
+
+
+	RTW_INFO("%s, fw_state=%x\n", __FUNCTION__, get_fwstate(pmlmepriv));
+
+	if (RTW_CANNOT_RUN(adapter))
+		return;
+
+
+	_enter_critical_bh(&pmlmepriv->lock, &irqL);
+
+#ifdef CONFIG_LAYER2_ROAMING
+	if (rtw_to_roam(adapter) > 0) { /* join timeout caused by roaming */
+		while (1) {
+			rtw_dec_to_roam(adapter);
+			if (rtw_to_roam(adapter) != 0) { /* try another */
+				int do_join_r;
+				RTW_INFO("%s try another roaming\n", __FUNCTION__);
+				do_join_r = rtw_do_join(adapter);
+				if (_SUCCESS != do_join_r) {
+					RTW_INFO("%s roaming do_join return %d\n", __FUNCTION__ , do_join_r);
+					continue;
+				}
+				break;
+			} else {
+#ifdef CONFIG_INTEL_WIDI
+				if (adapter->mlmepriv.widi_state == INTEL_WIDI_STATE_ROAMING) {
+					_rtw_memset(pmlmepriv->sa_ext, 0x00, L2SDTA_SERVICE_VE_LEN);
+					intel_widi_wk_cmd(adapter, INTEL_WIDI_LISTEN_WK, NULL, 0);
+					RTW_INFO("change to widi listen\n");
+				}
+#endif /* CONFIG_INTEL_WIDI */
+				RTW_INFO("%s We've try roaming but fail\n", __FUNCTION__);
+#ifdef CONFIG_RTW_80211R
+				rtw_ft_clr_flags(adapter, RTW_FT_PEER_EN|RTW_FT_PEER_OTD_EN);
+				rtw_ft_reset_status(adapter);
+#endif
+				rtw_indicate_disconnect(adapter, pmlmepriv->join_status, _FALSE);
+				break;
+			}
+		}
+
+	} else
+#endif
+	{
+		rtw_indicate_disconnect(adapter, pmlmepriv->join_status, _FALSE);
+		free_scanqueue(pmlmepriv);/* ??? */
+
+#ifdef CONFIG_IOCTL_CFG80211
+		/* indicate disconnect for the case that join_timeout and check_fwstate != FW_LINKED */
+		rtw_cfg80211_indicate_disconnect(adapter, pmlmepriv->join_status, _FALSE);
+#endif /* CONFIG_IOCTL_CFG80211 */
+
+	}
+
+	pmlmepriv->join_status = 0; /* reset */
+
+	_exit_critical_bh(&pmlmepriv->lock, &irqL);
+
+
+#ifdef CONFIG_DRVEXT_MODULE_WSC
+	drvext_assoc_fail_indicate(&adapter->drvextpriv);
+#endif
+
+
+
+}
+
+/*
+* rtw_scan_timeout_handler - Timeout/Faliure handler for CMD SiteSurvey
+* @adapter: pointer to _adapter structure
+*/
+void rtw_scan_timeout_handler(void *ctx)
+{
+	_adapter *adapter = (_adapter *)ctx;
+	_irqL irqL;
+	struct mlme_priv *pmlmepriv = &adapter->mlmepriv;
+	RTW_INFO(FUNC_ADPT_FMT" fw_state=%x\n", FUNC_ADPT_ARG(adapter), get_fwstate(pmlmepriv));
+
+	_enter_critical_bh(&pmlmepriv->lock, &irqL);
+
+	_clr_fwstate_(pmlmepriv, _FW_UNDER_SURVEY);
+
+	_exit_critical_bh(&pmlmepriv->lock, &irqL);
+
+#ifdef CONFIG_IOCTL_CFG80211
+	rtw_cfg80211_surveydone_event_callback(adapter);
+#endif /* CONFIG_IOCTL_CFG80211 */
+
+	rtw_indicate_scan_done(adapter, _TRUE);
+
+#if defined(CONFIG_CONCURRENT_MODE) && defined(CONFIG_IOCTL_CFG80211)
+	rtw_cfg80211_indicate_scan_done_for_buddy(adapter, _TRUE);
+#endif
+}
+
+void rtw_mlme_reset_auto_scan_int(_adapter *adapter, u8 *reason)
+{
+#if defined(CONFIG_RTW_MESH) && defined(CONFIG_DFS_MASTER)
+#if CONFIG_RTW_MESH_OFFCH_CAND 
+	struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter);
+#endif
+#endif
+	u8 u_ch;
+	u32 interval_ms = 0xffffffff; /* 0xffffffff: special value to make min() works well, also means no auto scan */
+
+	*reason = RTW_AUTO_SCAN_REASON_UNSPECIFIED;
+	rtw_mi_get_ch_setting_union(adapter, &u_ch, NULL, NULL);
+
+	if (hal_chk_bw_cap(adapter, BW_CAP_40M)
+		&& is_client_associated_to_ap(adapter) == _TRUE
+		&& u_ch >= 1 && u_ch <= 14
+		&& adapter->registrypriv.wifi_spec
+		/* TODO: AP Connected is 40MHz capability? */
+	) {
+		interval_ms = rtw_min(interval_ms, 60 * 1000);
+		*reason |= RTW_AUTO_SCAN_REASON_2040_BSS;
+	}
+
+#ifdef CONFIG_RTW_MESH
+	#if CONFIG_RTW_MESH_OFFCH_CAND
+	if (adapter->mesh_cfg.peer_sel_policy.offch_find_int_ms
+		&& rtw_mesh_offch_candidate_accepted(adapter)
+		#ifdef CONFIG_DFS_MASTER
+		&& (!rfctl->radar_detect_ch || (IS_CH_WAITING(rfctl) && !IS_UNDER_CAC(rfctl)))
+		#endif
+	) {
+		interval_ms = rtw_min(interval_ms, adapter->mesh_cfg.peer_sel_policy.offch_find_int_ms);
+		*reason |= RTW_AUTO_SCAN_REASON_MESH_OFFCH_CAND;
+	}
+	#endif
+#endif /* CONFIG_RTW_MESH */
+
+	if (interval_ms == 0xffffffff)
+		interval_ms = 0;
+
+	rtw_mlme_set_auto_scan_int(adapter, interval_ms);
+	return;
+}
+
+void rtw_drv_scan_by_self(_adapter *padapter, u8 reason)
+{
+	struct sitesurvey_parm parm;
+	struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
+	int i;
+#if 1
+	u8 ssc_chk;
+
+	ssc_chk = rtw_sitesurvey_condition_check(padapter, _FALSE);
+	if( ssc_chk == SS_DENY_BUSY_TRAFFIC) {
+		#ifdef CONFIG_LAYER2_ROAMING
+		if (rtw_chk_roam_flags(padapter, RTW_ROAM_ACTIVE) && pmlmepriv->need_to_roam == _TRUE)
+			RTW_INFO(FUNC_ADPT_FMT" need to roam, don't care BusyTraffic\n", FUNC_ADPT_ARG(padapter));
+		else
+		#endif
+			RTW_INFO(FUNC_ADPT_FMT" exit BusyTraffic\n", FUNC_ADPT_ARG(padapter));
+			goto exit;
+	}
+	else if (ssc_chk != SS_ALLOW)
+		goto exit;
+
+	if (!rtw_is_adapter_up(padapter))
+		goto exit;
+#else
+	if (rtw_is_scan_deny(padapter))
+		goto exit;
+
+	if (!rtw_is_adapter_up(padapter))
+		goto exit;
+
+	if (rtw_mi_busy_traffic_check(padapter, _FALSE)) {
+#ifdef CONFIG_LAYER2_ROAMING
+		if (rtw_chk_roam_flags(padapter, RTW_ROAM_ACTIVE) && pmlmepriv->need_to_roam == _TRUE) {
+			RTW_INFO("need to roam, don't care BusyTraffic\n");
+		} else
+#endif
+		{
+			RTW_INFO(FUNC_ADPT_FMT" exit BusyTraffic\n", FUNC_ADPT_ARG(padapter));
+			goto exit;
+		}
+	}
+	if (check_fwstate(pmlmepriv, WIFI_AP_STATE) && check_fwstate(pmlmepriv, WIFI_UNDER_WPS)) {
+		RTW_INFO(FUNC_ADPT_FMT" WIFI_AP_STATE && WIFI_UNDER_WPS\n", FUNC_ADPT_ARG(padapter));
+		goto exit;
+	}
+	if (check_fwstate(pmlmepriv, (_FW_UNDER_SURVEY | _FW_UNDER_LINKING)) == _TRUE) {
+		RTW_INFO(FUNC_ADPT_FMT" _FW_UNDER_SURVEY|_FW_UNDER_LINKING\n", FUNC_ADPT_ARG(padapter));
+		goto exit;
+	}
+
+#ifdef CONFIG_CONCURRENT_MODE
+	if (rtw_mi_buddy_check_fwstate(padapter, (_FW_UNDER_SURVEY | _FW_UNDER_LINKING | WIFI_UNDER_WPS))) {
+		RTW_INFO(FUNC_ADPT_FMT", but buddy_intf is under scanning or linking or wps_phase\n", FUNC_ADPT_ARG(padapter));
+		goto exit;
+	}
+#endif
+#endif
+
+	RTW_INFO(FUNC_ADPT_FMT" reason:0x%02x\n", FUNC_ADPT_ARG(padapter), reason);
+
+	/* only for 20/40 BSS */
+	if (reason == RTW_AUTO_SCAN_REASON_2040_BSS) {
+		rtw_init_sitesurvey_parm(padapter, &parm);
+		for (i=0;i<14;i++) {
+			parm.ch[i].hw_value = i + 1;
+			parm.ch[i].flags = RTW_IEEE80211_CHAN_PASSIVE_SCAN;
+		}
+		parm.ch_num = 14;
+		rtw_set_802_11_bssid_list_scan(padapter, &parm);
+		goto exit;
+	}
+
+#if defined(CONFIG_RTW_WNM) || defined(CONFIG_RTW_80211K)
+	if ((reason == RTW_AUTO_SCAN_REASON_ROAM) 
+		&& (rtw_roam_nb_scan_list_set(padapter, &parm)))
+		goto exit;
+#endif
+
+	rtw_set_802_11_bssid_list_scan(padapter, NULL);
+exit:
+	return;
+}
+
+static void rtw_auto_scan_handler(_adapter *padapter)
+{
+	struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
+	u8 reason = RTW_AUTO_SCAN_REASON_UNSPECIFIED;
+
+	rtw_mlme_reset_auto_scan_int(padapter, &reason);
+
+#ifdef CONFIG_P2P
+	if (!rtw_p2p_chk_state(&padapter->wdinfo, P2P_STATE_NONE))
+		goto exit;
+#endif
+
+#ifdef CONFIG_TDLS
+	if (padapter->tdlsinfo.link_established == _TRUE)
+		goto exit;
+#endif
+
+	if (pmlmepriv->auto_scan_int_ms == 0
+	    || rtw_get_passing_time_ms(pmlmepriv->scan_start_time) < pmlmepriv->auto_scan_int_ms)
+		goto exit;
+
+	rtw_drv_scan_by_self(padapter, reason);
+
+exit:
+	return;
+}
+static u8 is_drv_in_lps(_adapter *adapter)
+{
+	u8 is_in_lps = _FALSE;
+
+	#ifdef CONFIG_LPS_LCLK_WD_TIMER /* to avoid leaving lps 32k frequently*/
+	if ((adapter_to_pwrctl(adapter)->bFwCurrentInPSMode == _TRUE)
+	#ifdef CONFIG_BT_COEXIST
+		&& (rtw_btcoex_IsBtControlLps(adapter) == _FALSE)
+	#endif
+		)
+		is_in_lps = _TRUE;
+	#endif /* CONFIG_LPS_LCLK_WD_TIMER*/
+	return is_in_lps;
+}
+void rtw_iface_dynamic_check_timer_handlder(_adapter *adapter)
+{
+#ifdef CONFIG_AP_MODE
+	struct mlme_priv *pmlmepriv = &adapter->mlmepriv;
+#endif /* CONFIG_AP_MODE */
+
+	if (adapter->net_closed == _TRUE)
+		return;
+	#ifdef CONFIG_LPS_LCLK_WD_TIMER /* to avoid leaving lps 32k frequently*/
+	if (is_drv_in_lps(adapter)) {
+		u8 bEnterPS;
+
+		linked_status_chk(adapter, 1);
+
+		bEnterPS = traffic_status_watchdog(adapter, 1);
+		if (bEnterPS) {
+			/* rtw_lps_ctrl_wk_cmd(adapter, LPS_CTRL_ENTER, 1); */
+			rtw_hal_dm_watchdog_in_lps(adapter);
+		} else {
+			/* call rtw_lps_ctrl_wk_cmd(padapter, LPS_CTRL_LEAVE, 1) in traffic_status_watchdog() */
+		}
+	}
+	#endif /* CONFIG_LPS_LCLK_WD_TIMER	*/
+
+	/* auto site survey */
+	rtw_auto_scan_handler(adapter);
+
+#ifdef CONFIG_AP_MODE
+	if (MLME_IS_AP(adapter)|| MLME_IS_MESH(adapter)) {
+		#ifndef CONFIG_ACTIVE_KEEP_ALIVE_CHECK
+		expire_timeout_chk(adapter);
+		#endif /* !CONFIG_ACTIVE_KEEP_ALIVE_CHECK */
+
+		#ifdef CONFIG_BMC_TX_RATE_SELECT
+		rtw_update_bmc_sta_tx_rate(adapter);
+		#endif /*CONFIG_BMC_TX_RATE_SELECT*/
+	}
+#endif /*CONFIG_AP_MODE*/
+
+
+#ifdef CONFIG_BR_EXT
+
+#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 35))
+	rcu_read_lock();
+#endif /* (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 35)) */
+
+#if (LINUX_VERSION_CODE <= KERNEL_VERSION(2, 6, 35))
+	if (adapter->pnetdev->br_port
+#else	/* (LINUX_VERSION_CODE <= KERNEL_VERSION(2, 6, 35)) */
+	if (rcu_dereference(adapter->pnetdev->rx_handler_data)
+#endif /* (LINUX_VERSION_CODE <= KERNEL_VERSION(2, 6, 35)) */
+		&& (check_fwstate(pmlmepriv, WIFI_STATION_STATE | WIFI_ADHOC_STATE) == _TRUE)) {
+		/* expire NAT2.5 entry */
+		void nat25_db_expire(_adapter *priv);
+		nat25_db_expire(adapter);
+
+		if (adapter->pppoe_connection_in_progress > 0)
+			adapter->pppoe_connection_in_progress--;
+		/* due to rtw_dynamic_check_timer_handlder() is called every 2 seconds */
+		if (adapter->pppoe_connection_in_progress > 0)
+			adapter->pppoe_connection_in_progress--;
+	}
+
+#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 35))
+	rcu_read_unlock();
+#endif /* (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 35)) */
+
+#endif /* CONFIG_BR_EXT */
+
+}
+
+/*TP_avg(t) = (1/10) * TP_avg(t-1) + (9/10) * TP(t) MBps*/
+static void collect_sta_traffic_statistics(_adapter *adapter)
+{
+	struct macid_ctl_t *macid_ctl = &adapter->dvobj->macid_ctl;
+	struct sta_info *sta;
+	u64 curr_tx_bytes = 0, curr_rx_bytes = 0;
+	u32 curr_tx_mbytes = 0, curr_rx_mbytes = 0;
+	int i;
+
+	for (i = 0; i < MACID_NUM_SW_LIMIT; i++) {
+		sta = macid_ctl->sta[i];
+		if (sta && !is_broadcast_mac_addr(sta->cmn.mac_addr)) {
+			if (sta->sta_stats.last_tx_bytes > sta->sta_stats.tx_bytes)
+				sta->sta_stats.last_tx_bytes =  sta->sta_stats.tx_bytes;
+			if (sta->sta_stats.last_rx_bytes > sta->sta_stats.rx_bytes)
+				sta->sta_stats.last_rx_bytes = sta->sta_stats.rx_bytes;
+			if (sta->sta_stats.last_rx_bc_bytes > sta->sta_stats.rx_bc_bytes)
+				sta->sta_stats.last_rx_bc_bytes = sta->sta_stats.rx_bc_bytes;
+			if (sta->sta_stats.last_rx_mc_bytes > sta->sta_stats.rx_mc_bytes)
+				sta->sta_stats.last_rx_mc_bytes = sta->sta_stats.rx_mc_bytes;
+
+			curr_tx_bytes = sta->sta_stats.tx_bytes - sta->sta_stats.last_tx_bytes;
+			curr_rx_bytes = sta->sta_stats.rx_bytes - sta->sta_stats.last_rx_bytes;
+			sta->sta_stats.tx_tp_kbits = (curr_tx_bytes * 8 / 2) >> 10;/*Kbps*/
+			sta->sta_stats.rx_tp_kbits = (curr_rx_bytes * 8 / 2) >> 10;/*Kbps*/
+
+			sta->sta_stats.smooth_tx_tp_kbits = (sta->sta_stats.smooth_tx_tp_kbits * 6 / 10) + (sta->sta_stats.tx_tp_kbits * 4 / 10);/*Kbps*/
+			sta->sta_stats.smooth_rx_tp_kbits = (sta->sta_stats.smooth_rx_tp_kbits * 6 / 10) + (sta->sta_stats.rx_tp_kbits * 4 / 10);/*Kbps*/
+
+			curr_tx_mbytes = (curr_tx_bytes / 2) >> 20;/*MBps*/
+			curr_rx_mbytes = (curr_rx_bytes / 2) >> 20;/*MBps*/
+
+			sta->cmn.tx_moving_average_tp =
+				(sta->cmn.tx_moving_average_tp / 10) + (curr_tx_mbytes * 9 / 10); /*MBps*/
+
+			sta->cmn.rx_moving_average_tp =
+				(sta->cmn.rx_moving_average_tp / 10) + (curr_rx_mbytes * 9 /10); /*MBps*/
+
+			rtw_collect_bcn_info(sta->padapter);
+
+			if (adapter->bsta_tp_dump)
+				dump_sta_traffic(RTW_DBGDUMP, adapter, sta);
+
+			sta->sta_stats.last_tx_bytes = sta->sta_stats.tx_bytes;
+			sta->sta_stats.last_rx_bytes = sta->sta_stats.rx_bytes;
+			sta->sta_stats.last_rx_bc_bytes = sta->sta_stats.rx_bc_bytes;
+			sta->sta_stats.last_rx_mc_bytes = sta->sta_stats.rx_mc_bytes;
+		}
+	}
+}
+
+void rtw_sta_traffic_info(void *sel, _adapter *adapter)
+{
+	struct macid_ctl_t *macid_ctl = &adapter->dvobj->macid_ctl;
+	struct sta_info *sta;
+	int i;
+
+	for (i = 0; i < MACID_NUM_SW_LIMIT; i++) {
+		sta = macid_ctl->sta[i];
+		if (sta && !is_broadcast_mac_addr(sta->cmn.mac_addr))
+			dump_sta_traffic(sel, adapter, sta);
+	}
+}
+
+/*#define DBG_TRAFFIC_STATISTIC*/
+static void collect_traffic_statistics(_adapter *padapter)
+{
+	struct dvobj_priv	*pdvobjpriv = adapter_to_dvobj(padapter);
+
+	/*_rtw_memset(&pdvobjpriv->traffic_stat, 0, sizeof(struct rtw_traffic_statistics));*/
+
+	/* Tx bytes reset*/
+	pdvobjpriv->traffic_stat.tx_bytes = 0;
+	pdvobjpriv->traffic_stat.tx_pkts = 0;
+	pdvobjpriv->traffic_stat.tx_drop = 0;
+
+	/* Rx bytes reset*/
+	pdvobjpriv->traffic_stat.rx_bytes = 0;
+	pdvobjpriv->traffic_stat.rx_pkts = 0;
+	pdvobjpriv->traffic_stat.rx_drop = 0;
+
+	rtw_mi_traffic_statistics(padapter);
+
+	/* Calculate throughput in last interval */
+	pdvobjpriv->traffic_stat.cur_tx_bytes = pdvobjpriv->traffic_stat.tx_bytes - pdvobjpriv->traffic_stat.last_tx_bytes;
+	pdvobjpriv->traffic_stat.cur_rx_bytes = pdvobjpriv->traffic_stat.rx_bytes - pdvobjpriv->traffic_stat.last_rx_bytes;
+	pdvobjpriv->traffic_stat.last_tx_bytes = pdvobjpriv->traffic_stat.tx_bytes;
+	pdvobjpriv->traffic_stat.last_rx_bytes = pdvobjpriv->traffic_stat.rx_bytes;
+
+	pdvobjpriv->traffic_stat.cur_tx_tp = (u32)(pdvobjpriv->traffic_stat.cur_tx_bytes * 8 / 2 / 1024 / 1024);/*Mbps*/
+	pdvobjpriv->traffic_stat.cur_rx_tp = (u32)(pdvobjpriv->traffic_stat.cur_rx_bytes * 8 / 2 / 1024 / 1024);/*Mbps*/
+
+	#ifdef DBG_TRAFFIC_STATISTIC
+	RTW_INFO("\n========================\n");
+	RTW_INFO("cur_tx_bytes:%lld\n", pdvobjpriv->traffic_stat.cur_tx_bytes);
+	RTW_INFO("cur_rx_bytes:%lld\n", pdvobjpriv->traffic_stat.cur_rx_bytes);
+
+	RTW_INFO("last_tx_bytes:%lld\n", pdvobjpriv->traffic_stat.last_tx_bytes);
+	RTW_INFO("last_rx_bytes:%lld\n", pdvobjpriv->traffic_stat.last_rx_bytes);
+
+	RTW_INFO("cur_tx_tp:%d (Mbps)\n", pdvobjpriv->traffic_stat.cur_tx_tp);
+	RTW_INFO("cur_rx_tp:%d (Mbps)\n", pdvobjpriv->traffic_stat.cur_rx_tp);
+	#endif
+
+#ifdef CONFIG_RTW_NAPI
+#ifdef CONFIG_RTW_NAPI_DYNAMIC
+	dynamic_napi_th_chk (padapter);
+#endif /* CONFIG_RTW_NAPI_DYNAMIC */
+#endif
+	
+}
+
+void rtw_dynamic_check_timer_handlder(void *ctx)
+{
+	struct dvobj_priv *pdvobj = (struct dvobj_priv *)ctx;
+	_adapter *adapter = dvobj_get_primary_adapter(pdvobj);
+
+#if (MP_DRIVER == 1)
+	if (adapter->registrypriv.mp_mode == 1 && adapter->mppriv.mp_dm == 0) { /* for MP ODM dynamic Tx power tracking */
+		/* RTW_INFO("%s mp_dm =0 return\n", __func__); */
+		goto exit;
+	}
+#endif
+
+	if (!adapter)
+		goto exit;
+
+	if (!rtw_is_hw_init_completed(adapter))
+		goto exit;
+
+	if (RTW_CANNOT_RUN(adapter))
+		goto exit;
+
+	collect_traffic_statistics(adapter);
+	collect_sta_traffic_statistics(adapter);
+	rtw_mi_dynamic_check_timer_handlder(adapter);
+
+	if (!is_drv_in_lps(adapter))
+		rtw_dynamic_chk_wk_cmd(adapter);
+
+exit:
+	_set_timer(&pdvobj->dynamic_chk_timer, 2000);
+}
+
+
+#ifdef CONFIG_SET_SCAN_DENY_TIMER
+inline bool rtw_is_scan_deny(_adapter *adapter)
+{
+	struct mlme_priv *mlmepriv = &adapter->mlmepriv;
+	return (ATOMIC_READ(&mlmepriv->set_scan_deny) != 0) ? _TRUE : _FALSE;
+}
+
+inline void rtw_clear_scan_deny(_adapter *adapter)
+{
+	struct mlme_priv *mlmepriv = &adapter->mlmepriv;
+	ATOMIC_SET(&mlmepriv->set_scan_deny, 0);
+	if (0)
+		RTW_INFO(FUNC_ADPT_FMT"\n", FUNC_ADPT_ARG(adapter));
+}
+
+void rtw_set_scan_deny_timer_hdl(void *ctx)
+{
+	_adapter *adapter = (_adapter *)ctx;
+
+	rtw_clear_scan_deny(adapter);
+}
+void rtw_set_scan_deny(_adapter *adapter, u32 ms)
+{
+	struct mlme_priv *mlmepriv = &adapter->mlmepriv;
+	if (0)
+		RTW_INFO(FUNC_ADPT_FMT"\n", FUNC_ADPT_ARG(adapter));
+	ATOMIC_SET(&mlmepriv->set_scan_deny, 1);
+	_set_timer(&mlmepriv->set_scan_deny_timer, ms);
+}
+#endif
+
+#ifdef CONFIG_LAYER2_ROAMING
+/*
+* Select a new roaming candidate from the original @param candidate and @param competitor
+* @return _TRUE: candidate is updated
+* @return _FALSE: candidate is not updated
+*/
+static int rtw_check_roaming_candidate(struct mlme_priv *mlme
+	, struct wlan_network **candidate, struct wlan_network *competitor)
+{
+	int updated = _FALSE;
+	_adapter *adapter = container_of(mlme, _adapter, mlmepriv);
+	struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter);
+	RT_CHANNEL_INFO *chset = rfctl->channel_set;
+	u8 ch = competitor->network.Configuration.DSConfig;
+
+	if (rtw_chset_search_ch(chset, ch) < 0)
+		goto exit;
+	if (IS_DFS_SLAVE_WITH_RD(rfctl)
+		&& !rtw_odm_dfs_domain_unknown(rfctl_to_dvobj(rfctl))
+		&& rtw_chset_is_ch_non_ocp(chset, ch))
+		goto exit;
+
+#if defined(CONFIG_RTW_REPEATER_SON) &&  (!defined(CONFIG_RTW_REPEATER_SON_ROOT))
+	if (rtw_rson_isupdate_roamcan(mlme, candidate, competitor))
+		goto  update;
+	goto exit;
+#endif
+
+	if (is_same_ess(&competitor->network, &mlme->cur_network.network) == _FALSE)
+		goto exit;
+
+	if (rtw_is_desired_network(adapter, competitor) == _FALSE)
+		goto exit;
+
+#ifdef CONFIG_LAYER2_ROAMING
+	if (mlme->need_to_roam == _FALSE)
+		goto exit;
+#endif
+
+#ifdef CONFIG_RTW_80211R
+	if (rtw_ft_chk_flags(adapter, RTW_FT_PEER_EN)) {
+		if (rtw_ft_chk_roaming_candidate(adapter, competitor) == _FALSE)
+		goto exit;
+	}
+#endif
+
+	RTW_INFO("roam candidate:%s %s("MAC_FMT", ch%3u) rssi:%d, age:%5d\n",
+		 (competitor == mlme->cur_network_scanned) ? "*" : " " ,
+		 competitor->network.Ssid.Ssid,
+		 MAC_ARG(competitor->network.MacAddress),
+		 competitor->network.Configuration.DSConfig,
+		 (int)competitor->network.Rssi,
+		 rtw_get_passing_time_ms(competitor->last_scanned)
+		);
+
+	/* got specific addr to roam */
+	if (!is_zero_mac_addr(mlme->roam_tgt_addr)) {
+		if (_rtw_memcmp(mlme->roam_tgt_addr, competitor->network.MacAddress, ETH_ALEN) == _TRUE)
+			goto update;
+		else
+			goto exit;
+	}
+#if 1
+	if (rtw_get_passing_time_ms(competitor->last_scanned) >= mlme->roam_scanr_exp_ms)
+		goto exit;
+
+#if defined(CONFIG_RTW_80211R) && defined(CONFIG_RTW_WNM)
+	if (rtw_wnm_btm_diff_bss(adapter) && 
+		rtw_wnm_btm_roam_candidate(adapter, competitor)) {
+		goto update;
+	}	
+#endif
+
+	if (competitor->network.Rssi - mlme->cur_network_scanned->network.Rssi < mlme->roam_rssi_diff_th)
+		goto exit;
+
+	if (*candidate != NULL && (*candidate)->network.Rssi >= competitor->network.Rssi)
+		goto exit;
+#else
+	goto exit;
+#endif
+
+update:
+	*candidate = competitor;
+	updated = _TRUE;
+
+exit:
+	return updated;
+}
+
+int rtw_select_roaming_candidate(struct mlme_priv *mlme)
+{
+	_irqL	irqL;
+	int ret = _FAIL;
+	_list	*phead;
+	_adapter *adapter;
+	_queue	*queue	= &(mlme->scanned_queue);
+	struct	wlan_network	*pnetwork = NULL;
+	struct	wlan_network	*candidate = NULL;
+
+	if (mlme->cur_network_scanned == NULL) {
+		rtw_warn_on(1);
+		goto exit;
+	}
+
+	_enter_critical_bh(&(mlme->scanned_queue.lock), &irqL);
+	phead = get_list_head(queue);
+	adapter = (_adapter *)mlme->nic_hdl;
+
+	mlme->pscanned = get_next(phead);
+
+	while (!rtw_end_of_queue_search(phead, mlme->pscanned)) {
+
+		pnetwork = LIST_CONTAINOR(mlme->pscanned, struct wlan_network, list);
+		if (pnetwork == NULL) {
+			ret = _FAIL;
+			goto exit;
+		}
+
+		mlme->pscanned = get_next(mlme->pscanned);
+
+		if (0)
+			RTW_INFO("%s("MAC_FMT", ch%u) rssi:%d\n"
+				 , pnetwork->network.Ssid.Ssid
+				 , MAC_ARG(pnetwork->network.MacAddress)
+				 , pnetwork->network.Configuration.DSConfig
+				 , (int)pnetwork->network.Rssi);
+
+		rtw_check_roaming_candidate(mlme, &candidate, pnetwork);
+
+	}
+
+	if (candidate == NULL) {
+	/*	if parent note lost the path to root and there is no other cadidate, report disconnection	*/
+#if defined(CONFIG_RTW_REPEATER_SON) &&  (!defined(CONFIG_RTW_REPEATER_SON_ROOT))
+		struct rtw_rson_struct  rson_curr;
+		u8 rson_score;
+
+		rtw_get_rson_struct(&(mlme->cur_network_scanned->network), &rson_curr);
+		rson_score = rtw_cal_rson_score(&rson_curr, mlme->cur_network_scanned->network.Rssi);
+		if (check_fwstate(mlme, _FW_LINKED)
+			&& ((rson_score == RTW_RSON_SCORE_NOTCNNT)
+			|| (rson_score == RTW_RSON_SCORE_NOTSUP)))
+			receive_disconnect(adapter, mlme->cur_network_scanned->network.MacAddress
+								, WLAN_REASON_EXPIRATION_CHK, _FALSE);
+#endif
+		RTW_INFO("%s: return _FAIL(candidate == NULL)\n", __FUNCTION__);
+		ret = _FAIL;
+		goto exit;
+	} else {
+#if defined(CONFIG_RTW_REPEATER_SON) &&  (!defined(CONFIG_RTW_REPEATER_SON_ROOT))
+		struct rtw_rson_struct  rson_curr;
+		u8 rson_score;
+
+		rtw_get_rson_struct(&(candidate->network), &rson_curr);
+		rson_score = rtw_cal_rson_score(&rson_curr, candidate->network.Rssi);
+		RTW_INFO("%s: candidate: %s("MAC_FMT", ch:%u) rson_score:%d\n", __FUNCTION__,
+			candidate->network.Ssid.Ssid, MAC_ARG(candidate->network.MacAddress),
+			 candidate->network.Configuration.DSConfig, rson_score);
+#else
+		RTW_INFO("%s: candidate: %s("MAC_FMT", ch:%u)\n", __FUNCTION__,
+			candidate->network.Ssid.Ssid, MAC_ARG(candidate->network.MacAddress),
+			 candidate->network.Configuration.DSConfig);
+#endif
+		mlme->roam_network = candidate;
+
+		if (_rtw_memcmp(candidate->network.MacAddress, mlme->roam_tgt_addr, ETH_ALEN) == _TRUE)
+			_rtw_memset(mlme->roam_tgt_addr, 0, ETH_ALEN);
+	}
+
+	ret = _SUCCESS;
+exit:
+	_exit_critical_bh(&(mlme->scanned_queue.lock), &irqL);
+
+	return ret;
+}
+#endif /* CONFIG_LAYER2_ROAMING */
+
+/*
+* Select a new join candidate from the original @param candidate and @param competitor
+* @return _TRUE: candidate is updated
+* @return _FALSE: candidate is not updated
+*/
+static int rtw_check_join_candidate(struct mlme_priv *mlme
+	    , struct wlan_network **candidate, struct wlan_network *competitor)
+{
+	int updated = _FALSE;
+	_adapter *adapter = container_of(mlme, _adapter, mlmepriv);
+	struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter);
+	RT_CHANNEL_INFO *chset = rfctl->channel_set;
+	u8 ch = competitor->network.Configuration.DSConfig;
+
+	if (rtw_chset_search_ch(chset, ch) < 0)
+		goto exit;
+	if (IS_DFS_SLAVE_WITH_RD(rfctl)
+		&& !rtw_odm_dfs_domain_unknown(rfctl_to_dvobj(rfctl))
+		&& rtw_chset_is_ch_non_ocp(chset, ch))
+		goto exit;
+
+#if defined(CONFIG_RTW_REPEATER_SON) &&  (!defined(CONFIG_RTW_REPEATER_SON_ROOT))
+	s16 rson_score;
+	struct rtw_rson_struct  rson_data;
+
+	if (rtw_rson_choose(candidate, competitor)) {
+		*candidate = competitor;
+		rtw_get_rson_struct(&((*candidate)->network), &rson_data);
+		rson_score = rtw_cal_rson_score(&rson_data, (*candidate)->network.Rssi);
+		RTW_INFO("[assoc_ssid:%s] new candidate: %s("MAC_FMT", ch%u) rson_score:%d\n",
+			 mlme->assoc_ssid.Ssid,
+			 (*candidate)->network.Ssid.Ssid,
+			 MAC_ARG((*candidate)->network.MacAddress),
+			 (*candidate)->network.Configuration.DSConfig,
+			 rson_score);
+		return _TRUE;
+	}
+	return _FALSE;
+#endif
+
+	/* check bssid, if needed */
+	if (mlme->assoc_by_bssid == _TRUE) {
+		if (_rtw_memcmp(competitor->network.MacAddress, mlme->assoc_bssid, ETH_ALEN) == _FALSE)
+			goto exit;
+	}
+
+	/* check ssid, if needed */
+	if (mlme->assoc_ssid.Ssid[0] && mlme->assoc_ssid.SsidLength) {
+		if (competitor->network.Ssid.SsidLength != mlme->assoc_ssid.SsidLength
+		    || _rtw_memcmp(competitor->network.Ssid.Ssid, mlme->assoc_ssid.Ssid, mlme->assoc_ssid.SsidLength) == _FALSE
+		   )
+			goto exit;
+	}
+
+	if (rtw_is_desired_network(adapter, competitor)  == _FALSE)
+		goto exit;
+
+#ifdef CONFIG_LAYER2_ROAMING
+	if (rtw_to_roam(adapter) > 0) {
+		if (rtw_get_passing_time_ms(competitor->last_scanned) >= mlme->roam_scanr_exp_ms
+		    || is_same_ess(&competitor->network, &mlme->cur_network.network) == _FALSE
+		   )
+			goto exit;
+	}
+#endif
+
+	if (*candidate == NULL || (*candidate)->network.Rssi < competitor->network.Rssi) {
+		*candidate = competitor;
+		updated = _TRUE;
+	}
+
+	if (updated) {
+		RTW_INFO("[by_bssid:%u][assoc_ssid:%s][to_roam:%u] "
+			 "new candidate: %s("MAC_FMT", ch%u) rssi:%d\n",
+			 mlme->assoc_by_bssid,
+			 mlme->assoc_ssid.Ssid,
+			 rtw_to_roam(adapter),
+			 (*candidate)->network.Ssid.Ssid,
+			 MAC_ARG((*candidate)->network.MacAddress),
+			 (*candidate)->network.Configuration.DSConfig,
+			 (int)(*candidate)->network.Rssi
+			);
+	}
+
+exit:
+	return updated;
+}
+
+/*
+Calling context:
+The caller of the sub-routine will be in critical section...
+
+The caller must hold the following spinlock
+
+pmlmepriv->lock
+
+
+*/
+
+int rtw_select_and_join_from_scanned_queue(struct mlme_priv *pmlmepriv)
+{
+	_irqL	irqL;
+	int ret;
+	_list	*phead;
+	_adapter *adapter;
+	_queue	*queue	= &(pmlmepriv->scanned_queue);
+	struct	wlan_network	*pnetwork = NULL;
+	struct	wlan_network	*candidate = NULL;
+#ifdef CONFIG_ANTENNA_DIVERSITY
+	u8		bSupportAntDiv = _FALSE;
+#endif
+
+	adapter = (_adapter *)pmlmepriv->nic_hdl;
+
+	_enter_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);
+
+#ifdef CONFIG_LAYER2_ROAMING
+	if (pmlmepriv->roam_network) {
+		candidate = pmlmepriv->roam_network;
+		pmlmepriv->roam_network = NULL;
+		goto candidate_exist;
+	}
+#endif
+
+	phead = get_list_head(queue);
+	pmlmepriv->pscanned = get_next(phead);
+
+	while (!rtw_end_of_queue_search(phead, pmlmepriv->pscanned)) {
+
+		pnetwork = LIST_CONTAINOR(pmlmepriv->pscanned, struct wlan_network, list);
+		if (pnetwork == NULL) {
+			ret = _FAIL;
+			goto exit;
+		}
+
+		pmlmepriv->pscanned = get_next(pmlmepriv->pscanned);
+
+		if (0)
+			RTW_INFO("%s("MAC_FMT", ch%u) rssi:%d\n"
+				 , pnetwork->network.Ssid.Ssid
+				 , MAC_ARG(pnetwork->network.MacAddress)
+				 , pnetwork->network.Configuration.DSConfig
+				 , (int)pnetwork->network.Rssi);
+
+		rtw_check_join_candidate(pmlmepriv, &candidate, pnetwork);
+
+	}
+
+	if (candidate == NULL) {
+		RTW_INFO("%s: return _FAIL(candidate == NULL)\n", __FUNCTION__);
+#ifdef CONFIG_WOWLAN
+		_clr_fwstate_(pmlmepriv, _FW_LINKED | _FW_UNDER_LINKING);
+#endif
+		ret = _FAIL;
+		goto exit;
+	} else {
+		RTW_INFO("%s: candidate: %s("MAC_FMT", ch:%u)\n", __FUNCTION__,
+			candidate->network.Ssid.Ssid, MAC_ARG(candidate->network.MacAddress),
+			 candidate->network.Configuration.DSConfig);
+		goto candidate_exist;
+	}
+
+candidate_exist:
+
+	/* check for situation of  _FW_LINKED */
+	if (check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE) {
+		RTW_INFO("%s: _FW_LINKED while ask_for_joinbss!!!\n", __FUNCTION__);
+
+#if 0 /* for WPA/WPA2 authentication, wpa_supplicant will expect authentication from AP, it is needed to reconnect AP... */
+		if (is_same_network(&pmlmepriv->cur_network.network, &candidate->network)) {
+			RTW_INFO("%s: _FW_LINKED and is same network, it needn't join again\n", __FUNCTION__);
+
+			rtw_indicate_connect(adapter);/* rtw_indicate_connect again */
+
+			ret = 2;
+			goto exit;
+		} else
+#endif
+		{
+			rtw_disassoc_cmd(adapter, 0, 0);
+			rtw_indicate_disconnect(adapter, 0, _FALSE);
+			rtw_free_assoc_resources_cmd(adapter, _TRUE, 0);
+		}
+	}
+
+#ifdef CONFIG_ANTENNA_DIVERSITY
+	rtw_hal_get_def_var(adapter, HAL_DEF_IS_SUPPORT_ANT_DIV, &(bSupportAntDiv));
+	if (_TRUE == bSupportAntDiv) {
+		u8 CurrentAntenna;
+		rtw_hal_get_odm_var(adapter, HAL_ODM_ANTDIV_SELECT, &(CurrentAntenna), NULL);
+		RTW_INFO("#### Opt_Ant_(%s) , cur_Ant(%s)\n",
+			(MAIN_ANT == candidate->network.PhyInfo.Optimum_antenna) ? "MAIN_ANT" : "AUX_ANT",
+			 (MAIN_ANT == CurrentAntenna) ? "MAIN_ANT" : "AUX_ANT"
+			);
+	}
+#endif
+	set_fwstate(pmlmepriv, _FW_UNDER_LINKING);
+	ret = rtw_joinbss_cmd(adapter, candidate);
+
+exit:
+	_exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);
+
+
+	return ret;
+}
+
+sint rtw_set_auth(_adapter *adapter, struct security_priv *psecuritypriv)
+{
+	struct	cmd_obj *pcmd;
+	struct	setauth_parm *psetauthparm;
+	struct	cmd_priv	*pcmdpriv = &(adapter->cmdpriv);
+	sint		res = _SUCCESS;
+
+
+	pcmd = (struct	cmd_obj *)rtw_zmalloc(sizeof(struct	cmd_obj));
+	if (pcmd == NULL) {
+		res = _FAIL; /* try again */
+		goto exit;
+	}
+
+	psetauthparm = (struct setauth_parm *)rtw_zmalloc(sizeof(struct setauth_parm));
+	if (psetauthparm == NULL) {
+		rtw_mfree((unsigned char *)pcmd, sizeof(struct	cmd_obj));
+		res = _FAIL;
+		goto exit;
+	}
+
+	_rtw_memset(psetauthparm, 0, sizeof(struct setauth_parm));
+	psetauthparm->mode = (unsigned char)psecuritypriv->dot11AuthAlgrthm;
+
+	pcmd->cmdcode = _SetAuth_CMD_;
+	pcmd->parmbuf = (unsigned char *)psetauthparm;
+	pcmd->cmdsz = (sizeof(struct setauth_parm));
+	pcmd->rsp = NULL;
+	pcmd->rspsz = 0;
+
+
+	_rtw_init_listhead(&pcmd->list);
+
+
+	res = rtw_enqueue_cmd(pcmdpriv, pcmd);
+
+exit:
+
+
+	return res;
+
+}
+
+
+sint rtw_set_key(_adapter *adapter, struct security_priv *psecuritypriv, sint keyid, u8 set_tx, bool enqueue)
+{
+	u8	keylen;
+	struct cmd_obj		*pcmd;
+	struct setkey_parm	*psetkeyparm;
+	struct cmd_priv		*pcmdpriv = &(adapter->cmdpriv);
+	sint	res = _SUCCESS;
+
+
+	psetkeyparm = (struct setkey_parm *)rtw_zmalloc(sizeof(struct setkey_parm));
+	if (psetkeyparm == NULL) {
+		res = _FAIL;
+		goto exit;
+	}
+	_rtw_memset(psetkeyparm, 0, sizeof(struct setkey_parm));
+
+	if (psecuritypriv->dot11AuthAlgrthm == dot11AuthAlgrthm_8021X) {
+		psetkeyparm->algorithm = (unsigned char)psecuritypriv->dot118021XGrpPrivacy;
+	} else {
+		psetkeyparm->algorithm = (u8)psecuritypriv->dot11PrivacyAlgrthm;
+
+	}
+	psetkeyparm->keyid = (u8)keyid;/* 0~3 */
+	psetkeyparm->set_tx = set_tx;
+	if (is_wep_enc(psetkeyparm->algorithm))
+		adapter->securitypriv.key_mask |= BIT(psetkeyparm->keyid);
+
+	RTW_INFO("==> rtw_set_key algorithm(%x),keyid(%x),key_mask(%x)\n", psetkeyparm->algorithm, psetkeyparm->keyid, adapter->securitypriv.key_mask);
+
+	switch (psetkeyparm->algorithm) {
+
+	case _WEP40_:
+		keylen = 5;
+		_rtw_memcpy(&(psetkeyparm->key[0]), &(psecuritypriv->dot11DefKey[keyid].skey[0]), keylen);
+		break;
+	case _WEP104_:
+		keylen = 13;
+		_rtw_memcpy(&(psetkeyparm->key[0]), &(psecuritypriv->dot11DefKey[keyid].skey[0]), keylen);
+		break;
+	case _TKIP_:
+		keylen = 16;
+		_rtw_memcpy(&psetkeyparm->key, &psecuritypriv->dot118021XGrpKey[keyid], keylen);
+		break;
+	case _AES_:
+		keylen = 16;
+		_rtw_memcpy(&psetkeyparm->key, &psecuritypriv->dot118021XGrpKey[keyid], keylen);
+		break;
+	default:
+		res = _FAIL;
+		rtw_mfree((unsigned char *)psetkeyparm, sizeof(struct setkey_parm));
+		goto exit;
+	}
+
+
+	if (enqueue) {
+		pcmd = (struct	cmd_obj *)rtw_zmalloc(sizeof(struct	cmd_obj));
+		if (pcmd == NULL) {
+			rtw_mfree((unsigned char *)psetkeyparm, sizeof(struct setkey_parm));
+			res = _FAIL; /* try again */
+			goto exit;
+		}
+
+		pcmd->cmdcode = _SetKey_CMD_;
+		pcmd->parmbuf = (u8 *)psetkeyparm;
+		pcmd->cmdsz = (sizeof(struct setkey_parm));
+		pcmd->rsp = NULL;
+		pcmd->rspsz = 0;
+
+		_rtw_init_listhead(&pcmd->list);
+
+		/* _rtw_init_sema(&(pcmd->cmd_sem), 0); */
+
+		res = rtw_enqueue_cmd(pcmdpriv, pcmd);
+	} else {
+		setkey_hdl(adapter, (u8 *)psetkeyparm);
+		rtw_mfree((u8 *) psetkeyparm, sizeof(struct setkey_parm));
+	}
+exit:
+	return res;
+
+}
+
+#ifdef CONFIG_WMMPS_STA
+/*
+ * rtw_uapsd_use_default_setting
+ * This function is used for setting default uapsd max sp length to uapsd_max_sp_len
+ * in qos_priv data structure from registry. In additional, it will also map default uapsd 
+ * ac to each uapsd TID, delivery-enabled and trigger-enabled of corresponding TID. 
+ * 
+ * Arguments:
+ * @padapter: _adapter pointer.
+ *
+ * Auther: Arvin Liu
+ * Date: 2017/05/03
+ */
+void	rtw_uapsd_use_default_setting(_adapter *padapter)
+{
+	struct mlme_priv		*pmlmepriv = &padapter->mlmepriv;
+	struct qos_priv		*pqospriv = &pmlmepriv->qospriv;
+	struct registry_priv		*pregistrypriv = &padapter->registrypriv;
+
+	if (pregistrypriv->uapsd_ac_enable != 0) {
+		pqospriv->uapsd_max_sp_len = pregistrypriv->uapsd_max_sp_len;
+		
+		CLEAR_FLAGS(pqospriv->uapsd_tid);
+		CLEAR_FLAGS(pqospriv->uapsd_tid_delivery_enabled);
+		CLEAR_FLAGS(pqospriv->uapsd_tid_trigger_enabled);
+
+		/* check the uapsd setting of AC_VO from registry then map these setting to each TID if necessary  */
+		if(TEST_FLAG(pregistrypriv->uapsd_ac_enable, DRV_CFG_UAPSD_VO)) {
+			SET_FLAG(pqospriv->uapsd_tid, WMM_TID7);
+			SET_FLAG(pqospriv->uapsd_tid_delivery_enabled, WMM_TID7);
+			SET_FLAG(pqospriv->uapsd_tid_trigger_enabled, WMM_TID7);
+			SET_FLAG(pqospriv->uapsd_tid, WMM_TID6);
+			SET_FLAG(pqospriv->uapsd_tid_delivery_enabled, WMM_TID6);
+			SET_FLAG(pqospriv->uapsd_tid_trigger_enabled, WMM_TID6);
+		}
+
+		/* check the uapsd setting of AC_VI from registry then map these setting to each TID if necessary  */
+		if(TEST_FLAG(pregistrypriv->uapsd_ac_enable, DRV_CFG_UAPSD_VI)) {	
+			SET_FLAG(pqospriv->uapsd_tid, WMM_TID5);
+			SET_FLAG(pqospriv->uapsd_tid_delivery_enabled, WMM_TID5);
+			SET_FLAG(pqospriv->uapsd_tid_trigger_enabled, WMM_TID5);
+			SET_FLAG(pqospriv->uapsd_tid, WMM_TID4);
+			SET_FLAG(pqospriv->uapsd_tid_delivery_enabled, WMM_TID4);
+			SET_FLAG(pqospriv->uapsd_tid_trigger_enabled, WMM_TID4);
+		}
+
+		/* check the uapsd setting of AC_BK from registry then map these setting to each TID if necessary  */
+		if(TEST_FLAG(pregistrypriv->uapsd_ac_enable, DRV_CFG_UAPSD_BK)) {
+			SET_FLAG(pqospriv->uapsd_tid, WMM_TID2);
+			SET_FLAG(pqospriv->uapsd_tid_delivery_enabled, WMM_TID2);
+			SET_FLAG(pqospriv->uapsd_tid_trigger_enabled, WMM_TID2);
+			SET_FLAG(pqospriv->uapsd_tid, WMM_TID1);
+			SET_FLAG(pqospriv->uapsd_tid_delivery_enabled, WMM_TID1);
+			SET_FLAG(pqospriv->uapsd_tid_trigger_enabled, WMM_TID1);
+		}
+
+		/* check the uapsd setting of AC_BE from registry then map these setting to each TID if necessary  */
+		if(TEST_FLAG(pregistrypriv->uapsd_ac_enable, DRV_CFG_UAPSD_BE)) {
+			SET_FLAG(pqospriv->uapsd_tid, WMM_TID3);
+			SET_FLAG(pqospriv->uapsd_tid_delivery_enabled, WMM_TID3);
+			SET_FLAG(pqospriv->uapsd_tid_trigger_enabled, WMM_TID3);
+			SET_FLAG(pqospriv->uapsd_tid, WMM_TID0);
+			SET_FLAG(pqospriv->uapsd_tid_delivery_enabled, WMM_TID0);
+			SET_FLAG(pqospriv->uapsd_tid_trigger_enabled, WMM_TID0);
+		}
+
+		RTW_INFO("[WMMPS] UAPSD MAX SP Len = 0x%02x, UAPSD TID enabled = 0x%02x\n", 
+			pqospriv->uapsd_max_sp_len, (u8)pqospriv->uapsd_tid);
+	}
+
+}
+
+/*
+ * rtw_is_wmmps_mode
+ * This function is used for checking whether Driver and an AP support uapsd function or not.
+ * If both of them support uapsd function, it will return true. Otherwise returns false.
+ * 
+ * Arguments:
+ * @padapter: _adapter pointer.
+ *
+ * Auther: Arvin Liu
+ * Date: 2017/06/12
+ */
+bool rtw_is_wmmps_mode(_adapter *padapter) 
+{
+	struct mlme_priv	*pmlmepriv = &(padapter->mlmepriv);
+	struct qos_priv	*pqospriv = &pmlmepriv->qospriv;
+		
+	if ((pqospriv->uapsd_ap_supported) && ((pqospriv->uapsd_tid & BIT_MASK_TID_TC)  != 0))
+		return _TRUE;
+
+	return _FALSE;
+}
+#endif /* CONFIG_WMMPS_STA */
+
+/* adjust IEs for rtw_joinbss_cmd in WMM */
+int rtw_restruct_wmm_ie(_adapter *adapter, u8 *in_ie, u8 *out_ie, uint in_len, uint initial_out_len)
+{
+#ifdef CONFIG_WMMPS_STA
+	struct mlme_priv		*pmlmepriv = &adapter->mlmepriv;
+	struct qos_priv		*pqospriv = &pmlmepriv->qospriv;
+#endif /* CONFIG_WMMPS_STA */
+	unsigned	int ielength = 0;
+	unsigned int i, j;
+	u8 qos_info = 0;
+
+	i = 12; /* after the fixed IE */
+	while (i < in_len) {
+		ielength = initial_out_len;
+
+		if (in_ie[i] == 0xDD && in_ie[i + 2] == 0x00 && in_ie[i + 3] == 0x50  && in_ie[i + 4] == 0xF2 && in_ie[i + 5] == 0x02 && i + 5 < in_len) { /* WMM element ID and OUI */
+
+			/* Append WMM IE to the last index of out_ie */
+#if 0
+			for (j = i; j < i + (in_ie[i + 1] + 2); j++) {
+				out_ie[ielength] = in_ie[j];
+				ielength++;
+			}
+			out_ie[initial_out_len + 8] = 0x00; /* force the QoS Info Field to be zero */
+#endif
+
+			for (j = i; j < i + 9; j++) {
+				out_ie[ielength] = in_ie[j];
+				ielength++;
+			}
+			out_ie[initial_out_len + 1] = 0x07;
+			out_ie[initial_out_len + 6] = 0x00;
+
+#ifdef CONFIG_WMMPS_STA
+			switch(pqospriv->uapsd_max_sp_len) {
+				case NO_LIMIT: 
+					/* do nothing */
+					break;
+				case TWO_MSDU: 
+					SET_FLAG(qos_info, BIT5);
+					break;
+				case FOUR_MSDU: 
+					SET_FLAG(qos_info, BIT6);
+					break;	
+				case SIX_MSDU: 
+					SET_FLAG(qos_info, BIT5);
+					SET_FLAG(qos_info, BIT6);
+					break;
+				default:
+					/* do nothing */
+					break;
+			};
+
+			/* check TID7 and TID6 for AC_VO to set corresponding Qos_info bit in WMM IE  */
+			if((TEST_FLAG(pqospriv->uapsd_tid, WMM_TID7)) && (TEST_FLAG(pqospriv->uapsd_tid, WMM_TID6)))
+				SET_FLAG(qos_info, WMM_IE_UAPSD_VO);
+			/* check TID5 and TID4 for AC_VI to set corresponding Qos_info bit in WMM IE  */
+			if((TEST_FLAG(pqospriv->uapsd_tid, WMM_TID5)) && (TEST_FLAG(pqospriv->uapsd_tid, WMM_TID4)))
+				SET_FLAG(qos_info, WMM_IE_UAPSD_VI);
+			/* check TID2 and TID1 for AC_BK to set corresponding Qos_info bit in WMM IE  */
+			if((TEST_FLAG(pqospriv->uapsd_tid, WMM_TID2)) && (TEST_FLAG(pqospriv->uapsd_tid, WMM_TID1)))
+				SET_FLAG(qos_info, WMM_IE_UAPSD_BK);
+			/* check TID3 and TID0 for AC_BE to set corresponding Qos_info bit in WMM IE  */
+			if((TEST_FLAG(pqospriv->uapsd_tid, WMM_TID3)) && (TEST_FLAG(pqospriv->uapsd_tid, WMM_TID0)))
+				SET_FLAG(qos_info, WMM_IE_UAPSD_BE);
+#endif /* CONFIG_WMMPS_STA */
+			
+			out_ie[initial_out_len + 8] = qos_info;
+
+			break;
+		}
+
+		i += (in_ie[i + 1] + 2); /* to the next IE element */
+	}
+
+	return ielength;
+
+}
+
+
+/*
+ * Ported from 8185: IsInPreAuthKeyList(). (Renamed from SecIsInPreAuthKeyList(), 2006-10-13.)
+ * Added by Annie, 2006-05-07.
+ *
+ * Search by BSSID,
+ * Return Value:
+ *		-1		:if there is no pre-auth key in the  table
+ *		>=0		:if there is pre-auth key, and   return the entry id
+ *
+ *   */
+
+static int SecIsInPMKIDList(_adapter *Adapter, u8 *bssid)
+{
+	struct security_priv *psecuritypriv = &Adapter->securitypriv;
+	int i = 0;
+
+	do {
+		if ((psecuritypriv->PMKIDList[i].bUsed) &&
+		    (_rtw_memcmp(psecuritypriv->PMKIDList[i].Bssid, bssid, ETH_ALEN) == _TRUE))
+			break;
+		else {
+			i++;
+			/* continue; */
+		}
+
+	} while (i < NUM_PMKID_CACHE);
+
+	if (i == NUM_PMKID_CACHE) {
+		i = -1;/* Could not find. */
+	} else {
+		/* There is one Pre-Authentication Key for the specific BSSID. */
+	}
+
+	return i;
+
+}
+
+static int rtw_rsn_sync_pmkid(_adapter *adapter, u8 *ie, uint ie_len, int i_ent)
+{
+	struct security_priv *sec = &adapter->securitypriv;
+	struct rsne_info info;
+	u8 gm_cs[4];
+	int i;
+
+	rtw_rsne_info_parse(ie, ie_len, &info);
+
+	if (info.err) {
+		RTW_WARN(FUNC_ADPT_FMT" rtw_rsne_info_parse error\n"
+			, FUNC_ADPT_ARG(adapter));
+		return 0;
+	}
+
+	if (i_ent < 0 && info.pmkid_cnt == 0)
+		goto exit;
+
+	if (i_ent >= 0 && info.pmkid_cnt == 1 && _rtw_memcmp(info.pmkid_list, sec->PMKIDList[i_ent].PMKID, 16)) {
+		RTW_INFO(FUNC_ADPT_FMT" has carried the same PMKID:"KEY_FMT"\n"
+			, FUNC_ADPT_ARG(adapter), KEY_ARG(&sec->PMKIDList[i_ent].PMKID));
+		goto exit;
+	}
+
+	/* bakcup group mgmt cs */
+	if (info.gmcs)
+		_rtw_memcpy(gm_cs, info.gmcs, 4);
+
+	if (info.pmkid_cnt) {
+		RTW_INFO(FUNC_ADPT_FMT" remove original PMKID, count:%u\n"
+			 , FUNC_ADPT_ARG(adapter), info.pmkid_cnt);
+		for (i = 0; i < info.pmkid_cnt; i++)
+			RTW_INFO("    "KEY_FMT"\n", KEY_ARG(info.pmkid_list + i * 16));
+	}
+
+	if (i_ent >= 0) {
+		RTW_INFO(FUNC_ADPT_FMT" append PMKID:"KEY_FMT"\n"
+			, FUNC_ADPT_ARG(adapter), KEY_ARG(sec->PMKIDList[i_ent].PMKID));
+        if (!info.pmkid_list) {
+            /* prevent nullptr dereference when trying to insert a PMKID into 
+             * a frame that did not previously contain one. In order to be minimally
+             * invasive, we just discard requests like these, which might impact
+             * the ability to connect to certain access points, but will at least
+             * prevent the kernel panics */
+            return 0;
+        }
+
+		info.pmkid_cnt = 1; /* update new pmkid_cnt */
+		_rtw_memcpy(info.pmkid_list, sec->PMKIDList[i_ent].PMKID, 16);
+	} else
+		info.pmkid_cnt = 0; /* update new pmkid_cnt */
+
+	RTW_PUT_LE16(info.pmkid_list - 2, info.pmkid_cnt);
+	if (info.gmcs)
+		_rtw_memcpy(info.pmkid_list + 16 * info.pmkid_cnt, gm_cs, 4);
+
+	ie_len = 1 + 1 + 2 + 4
+		+ 2 + 4 * info.pcs_cnt
+		+ 2 + 4 * info.akm_cnt
+		+ 2
+		+ 2 + 16 * info.pmkid_cnt
+		+ (info.gmcs ? 4 : 0)
+		;
+	
+	ie[1] = (u8)(ie_len - 2);
+
+exit:
+	return ie_len;
+}
+
+sint rtw_restruct_sec_ie(_adapter *adapter, u8 *out_ie)
+{
+	u8 authmode = 0x0;
+	uint	ielength = 0;
+	int iEntry;
+
+	struct mlme_priv *pmlmepriv = &adapter->mlmepriv;
+	struct security_priv *psecuritypriv = &adapter->securitypriv;
+	uint	ndisauthmode = psecuritypriv->ndisauthtype;
+
+	if ((ndisauthmode == Ndis802_11AuthModeWPA) || (ndisauthmode == Ndis802_11AuthModeWPAPSK))
+		authmode = _WPA_IE_ID_;
+	if ((ndisauthmode == Ndis802_11AuthModeWPA2) || (ndisauthmode == Ndis802_11AuthModeWPA2PSK))
+		authmode = _WPA2_IE_ID_;
+
+	if (check_fwstate(pmlmepriv, WIFI_UNDER_WPS)) {
+		_rtw_memcpy(out_ie, psecuritypriv->wps_ie, psecuritypriv->wps_ie_len);
+		ielength = psecuritypriv->wps_ie_len;
+
+	} else if ((authmode == _WPA_IE_ID_) || (authmode == _WPA2_IE_ID_)) {
+		/* copy RSN or SSN		 */
+		_rtw_memcpy(out_ie, psecuritypriv->supplicant_ie, psecuritypriv->supplicant_ie[1] + 2);
+		/* debug for CONFIG_IEEE80211W
+		{
+			int jj;
+			printk("supplicant_ie_length=%d &&&&&&&&&&&&&&&&&&&\n", psecuritypriv->supplicant_ie[1]+2);
+			for(jj=0; jj < psecuritypriv->supplicant_ie[1]+2; jj++)
+				printk(" %02x ", psecuritypriv->supplicant_ie[jj]);
+			printk("\n");
+		}*/
+		ielength = psecuritypriv->supplicant_ie[1] + 2;
+		rtw_report_sec_ie(adapter, authmode, psecuritypriv->supplicant_ie);
+	}
+
+	if (authmode == WLAN_EID_RSN) {
+		iEntry = SecIsInPMKIDList(adapter, pmlmepriv->assoc_bssid);
+		ielength = rtw_rsn_sync_pmkid(adapter, out_ie, ielength, iEntry);
+	}
+
+	return ielength;
+}
+
+void rtw_init_registrypriv_dev_network(_adapter *adapter)
+{
+	struct registry_priv *pregistrypriv = &adapter->registrypriv;
+	WLAN_BSSID_EX    *pdev_network = &pregistrypriv->dev_network;
+	u8 *myhwaddr = adapter_mac_addr(adapter);
+
+
+	_rtw_memcpy(pdev_network->MacAddress, myhwaddr, ETH_ALEN);
+
+	_rtw_memcpy(&pdev_network->Ssid, &pregistrypriv->ssid, sizeof(NDIS_802_11_SSID));
+
+	pdev_network->Configuration.Length = sizeof(NDIS_802_11_CONFIGURATION);
+	pdev_network->Configuration.BeaconPeriod = 100;
+	pdev_network->Configuration.FHConfig.Length = 0;
+	pdev_network->Configuration.FHConfig.HopPattern = 0;
+	pdev_network->Configuration.FHConfig.HopSet = 0;
+	pdev_network->Configuration.FHConfig.DwellTime = 0;
+
+
+
+}
+
+void rtw_update_registrypriv_dev_network(_adapter *adapter)
+{
+	int sz = 0;
+	struct registry_priv *pregistrypriv = &adapter->registrypriv;
+	WLAN_BSSID_EX    *pdev_network = &pregistrypriv->dev_network;
+	struct	security_priv	*psecuritypriv = &adapter->securitypriv;
+	struct	wlan_network	*cur_network = &adapter->mlmepriv.cur_network;
+	/* struct	xmit_priv	*pxmitpriv = &adapter->xmitpriv; */
+	struct mlme_ext_priv	*pmlmeext = &adapter->mlmeextpriv;
+
+
+#if 0
+	pxmitpriv->vcs_setting = pregistrypriv->vrtl_carrier_sense;
+	pxmitpriv->vcs = pregistrypriv->vcs_type;
+	pxmitpriv->vcs_type = pregistrypriv->vcs_type;
+	/* pxmitpriv->rts_thresh = pregistrypriv->rts_thresh; */
+	pxmitpriv->frag_len = pregistrypriv->frag_thresh;
+
+	adapter->qospriv.qos_option = pregistrypriv->wmm_enable;
+#endif
+
+	pdev_network->Privacy = (psecuritypriv->dot11PrivacyAlgrthm > 0 ? 1 : 0) ; /* adhoc no 802.1x */
+
+	pdev_network->Rssi = 0;
+
+	switch (pregistrypriv->wireless_mode) {
+	case WIRELESS_11B:
+		pdev_network->NetworkTypeInUse = (Ndis802_11DS);
+		break;
+	case WIRELESS_11G:
+	case WIRELESS_11BG:
+	case WIRELESS_11_24N:
+	case WIRELESS_11G_24N:
+	case WIRELESS_11BG_24N:
+		pdev_network->NetworkTypeInUse = (Ndis802_11OFDM24);
+		break;
+	case WIRELESS_11A:
+	case WIRELESS_11A_5N:
+		pdev_network->NetworkTypeInUse = (Ndis802_11OFDM5);
+		break;
+	case WIRELESS_11ABGN:
+		if (pregistrypriv->channel > 14)
+			pdev_network->NetworkTypeInUse = (Ndis802_11OFDM5);
+		else
+			pdev_network->NetworkTypeInUse = (Ndis802_11OFDM24);
+		break;
+	default:
+		/* TODO */
+		break;
+	}
+
+	pdev_network->Configuration.DSConfig = (pregistrypriv->channel);
+
+	if (cur_network->network.InfrastructureMode == Ndis802_11IBSS) {
+		pdev_network->Configuration.ATIMWindow = (0);
+
+		if (pmlmeext->cur_channel != 0)
+			pdev_network->Configuration.DSConfig = pmlmeext->cur_channel;
+		else
+			pdev_network->Configuration.DSConfig = 1;
+	}
+
+	pdev_network->InfrastructureMode = (cur_network->network.InfrastructureMode);
+
+	/* 1. Supported rates */
+	/* 2. IE */
+
+	/* rtw_set_supported_rate(pdev_network->SupportedRates, pregistrypriv->wireless_mode) ; */ /* will be called in rtw_generate_ie */
+	sz = rtw_generate_ie(pregistrypriv);
+
+	pdev_network->IELength = sz;
+
+	pdev_network->Length = get_WLAN_BSSID_EX_sz((WLAN_BSSID_EX *)pdev_network);
+
+	/* notes: translate IELength & Length after assign the Length to cmdsz in createbss_cmd(); */
+	/* pdev_network->IELength = cpu_to_le32(sz); */
+
+
+}
+
+void rtw_get_encrypt_decrypt_from_registrypriv(_adapter *adapter)
+{
+
+
+
+}
+
+/* the fucntion is at passive_level */
+void rtw_joinbss_reset(_adapter *padapter)
+{
+	u8	threshold;
+	struct mlme_priv	*pmlmepriv = &padapter->mlmepriv;
+	/* todo: if you want to do something io/reg/hw setting before join_bss, please add code here */
+
+#ifdef CONFIG_80211N_HT
+	struct ht_priv		*phtpriv = &pmlmepriv->htpriv;
+
+	pmlmepriv->num_FortyMHzIntolerant = 0;
+
+	pmlmepriv->num_sta_no_ht = 0;
+
+	phtpriv->ampdu_enable = _FALSE;/* reset to disabled */
+
+#if defined(CONFIG_USB_HCI) || defined(CONFIG_SDIO_HCI)
+	/* TH=1 => means that invalidate usb rx aggregation */
+	/* TH=0 => means that validate usb rx aggregation, use init value. */
+	if (phtpriv->ht_option) {
+		if (padapter->registrypriv.wifi_spec == 1)
+			threshold = 1;
+		else
+			threshold = 0;
+		rtw_hal_set_hwreg(padapter, HW_VAR_RXDMA_AGG_PG_TH, (u8 *)(&threshold));
+	} else {
+		threshold = 1;
+		rtw_hal_set_hwreg(padapter, HW_VAR_RXDMA_AGG_PG_TH, (u8 *)(&threshold));
+	}
+#endif/* #if defined( CONFIG_USB_HCI) || defined (CONFIG_SDIO_HCI) */
+
+#endif/* #ifdef CONFIG_80211N_HT */
+
+}
+
+
+#ifdef CONFIG_80211N_HT
+void	rtw_ht_use_default_setting(_adapter *padapter)
+{
+	struct mlme_priv		*pmlmepriv = &padapter->mlmepriv;
+	struct ht_priv		*phtpriv = &pmlmepriv->htpriv;
+	struct registry_priv	*pregistrypriv = &padapter->registrypriv;
+	BOOLEAN		bHwLDPCSupport = _FALSE, bHwSTBCSupport = _FALSE;
+#ifdef CONFIG_BEAMFORMING
+	BOOLEAN		bHwSupportBeamformer = _FALSE, bHwSupportBeamformee = _FALSE;
+#endif /* CONFIG_BEAMFORMING */
+
+	if (pregistrypriv->wifi_spec)
+		phtpriv->bss_coexist = 1;
+	else
+		phtpriv->bss_coexist = 0;
+
+	phtpriv->sgi_40m = TEST_FLAG(pregistrypriv->short_gi, BIT1) ? _TRUE : _FALSE;
+	phtpriv->sgi_20m = TEST_FLAG(pregistrypriv->short_gi, BIT0) ? _TRUE : _FALSE;
+
+	/* LDPC support */
+	rtw_hal_get_def_var(padapter, HAL_DEF_RX_LDPC, (u8 *)&bHwLDPCSupport);
+	CLEAR_FLAGS(phtpriv->ldpc_cap);
+	if (bHwLDPCSupport) {
+		if (TEST_FLAG(pregistrypriv->ldpc_cap, BIT4))
+			SET_FLAG(phtpriv->ldpc_cap, LDPC_HT_ENABLE_RX);
+	}
+	rtw_hal_get_def_var(padapter, HAL_DEF_TX_LDPC, (u8 *)&bHwLDPCSupport);
+	if (bHwLDPCSupport) {
+		if (TEST_FLAG(pregistrypriv->ldpc_cap, BIT5))
+			SET_FLAG(phtpriv->ldpc_cap, LDPC_HT_ENABLE_TX);
+	}
+	if (phtpriv->ldpc_cap)
+		RTW_INFO("[HT] HAL Support LDPC = 0x%02X\n", phtpriv->ldpc_cap);
+
+	/* STBC */
+	rtw_hal_get_def_var(padapter, HAL_DEF_TX_STBC, (u8 *)&bHwSTBCSupport);
+	CLEAR_FLAGS(phtpriv->stbc_cap);
+	if (bHwSTBCSupport) {
+		if (TEST_FLAG(pregistrypriv->stbc_cap, BIT5))
+			SET_FLAG(phtpriv->stbc_cap, STBC_HT_ENABLE_TX);
+	}
+	rtw_hal_get_def_var(padapter, HAL_DEF_RX_STBC, (u8 *)&bHwSTBCSupport);
+	if (bHwSTBCSupport) {
+		if (TEST_FLAG(pregistrypriv->stbc_cap, BIT4))
+			SET_FLAG(phtpriv->stbc_cap, STBC_HT_ENABLE_RX);
+	}
+	if (phtpriv->stbc_cap)
+		RTW_INFO("[HT] HAL Support STBC = 0x%02X\n", phtpriv->stbc_cap);
+
+	/* Beamforming setting */
+	CLEAR_FLAGS(phtpriv->beamform_cap);
+#ifdef CONFIG_BEAMFORMING
+#ifdef RTW_BEAMFORMING_VERSION_2
+	/* only enable beamforming in STA client mode */
+	if (MLME_IS_STA(padapter) && !MLME_IS_GC(padapter)
+				  && !MLME_IS_ADHOC(padapter)
+				  && !MLME_IS_MESH(padapter))
+#endif
+	{
+		rtw_hal_get_def_var(padapter, HAL_DEF_EXPLICIT_BEAMFORMER, (u8 *)&bHwSupportBeamformer);
+		rtw_hal_get_def_var(padapter, HAL_DEF_EXPLICIT_BEAMFORMEE, (u8 *)&bHwSupportBeamformee);
+		if (TEST_FLAG(pregistrypriv->beamform_cap, BIT4) && bHwSupportBeamformer) {
+			SET_FLAG(phtpriv->beamform_cap, BEAMFORMING_HT_BEAMFORMER_ENABLE);
+			RTW_INFO("[HT] HAL Support Beamformer\n");
+		}
+		if (TEST_FLAG(pregistrypriv->beamform_cap, BIT5) && bHwSupportBeamformee) {
+			SET_FLAG(phtpriv->beamform_cap, BEAMFORMING_HT_BEAMFORMEE_ENABLE);
+			RTW_INFO("[HT] HAL Support Beamformee\n");
+		}
+	}
+#endif /* CONFIG_BEAMFORMING */
+}
+void rtw_build_wmm_ie_ht(_adapter *padapter, u8 *out_ie, uint *pout_len)
+{
+	unsigned char WMM_IE[] = {0x00, 0x50, 0xf2, 0x02, 0x00, 0x01, 0x00};
+	int out_len;
+	u8 *pframe;
+
+	if (padapter->mlmepriv.qospriv.qos_option == 0) {
+		out_len = *pout_len;
+		pframe = rtw_set_ie(out_ie + out_len, _VENDOR_SPECIFIC_IE_,
+				    _WMM_IE_Length_, WMM_IE, pout_len);
+
+		padapter->mlmepriv.qospriv.qos_option = 1;
+	}
+}
+#if defined(CONFIG_80211N_HT)
+/* the fucntion is >= passive_level */
+unsigned int rtw_restructure_ht_ie(_adapter *padapter, u8 *in_ie, u8 *out_ie, uint in_len, uint *pout_len, u8 channel)
+{
+	u32 ielen, out_len;
+	u32 rx_packet_offset, max_recvbuf_sz;
+	HT_CAP_AMPDU_FACTOR max_rx_ampdu_factor;
+	HT_CAP_AMPDU_DENSITY best_ampdu_density;
+	unsigned char *p, *pframe;
+	struct rtw_ieee80211_ht_cap ht_capie;
+	u8	cbw40_enable = 0, rf_type = 0, rf_num = 0, rx_stbc_nss = 0, rx_nss = 0;
+	struct registry_priv *pregistrypriv = &padapter->registrypriv;
+	struct mlme_priv	*pmlmepriv = &padapter->mlmepriv;
+	struct ht_priv		*phtpriv = &pmlmepriv->htpriv;
+	struct mlme_ext_priv	*pmlmeext = &padapter->mlmeextpriv;
+	struct hal_spec_t *hal_spec = GET_HAL_SPEC(padapter);
+#ifdef CONFIG_80211AC_VHT
+	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
+	struct vht_priv	*pvhtpriv = &pmlmepriv->vhtpriv;
+#endif /* CONFIG_80211AC_VHT */
+
+	phtpriv->ht_option = _FALSE;
+
+	out_len = *pout_len;
+
+	_rtw_memset(&ht_capie, 0, sizeof(struct rtw_ieee80211_ht_cap));
+
+	ht_capie.cap_info = IEEE80211_HT_CAP_DSSSCCK40;
+
+	if (phtpriv->sgi_20m)
+		ht_capie.cap_info |= IEEE80211_HT_CAP_SGI_20;
+
+	/* check if 40MHz is allowed according to hal cap and registry */
+	if (hal_chk_bw_cap(padapter, BW_CAP_40M)) {
+		if (channel > 14) {
+			if (REGSTY_IS_BW_5G_SUPPORT(pregistrypriv, CHANNEL_WIDTH_40))
+				cbw40_enable = 1;
+		} else {
+			if (REGSTY_IS_BW_2G_SUPPORT(pregistrypriv, CHANNEL_WIDTH_40))
+				cbw40_enable = 1;
+		}
+	}
+
+	if (cbw40_enable) {
+		struct rf_ctl_t *rfctl = adapter_to_rfctl(padapter);
+		RT_CHANNEL_INFO *chset = rfctl->channel_set;
+		u8 oper_bw = CHANNEL_WIDTH_20, oper_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
+
+		if (in_ie == NULL) {
+			/* TDLS: TODO 20/40 issue */
+			if (check_fwstate(pmlmepriv, WIFI_STATION_STATE)) {
+				oper_bw = padapter->mlmeextpriv.cur_bwmode;
+				if (oper_bw > CHANNEL_WIDTH_40)
+					oper_bw = CHANNEL_WIDTH_40;
+			} else
+				/* TDLS: TODO 40? */
+				oper_bw = CHANNEL_WIDTH_40;
+		} else {
+			p = rtw_get_ie(in_ie, WLAN_EID_HT_OPERATION, &ielen, in_len);
+			if (p && ielen == HT_OP_IE_LEN) {
+				if (GET_HT_OP_ELE_STA_CHL_WIDTH(p + 2)) {
+					switch (GET_HT_OP_ELE_2ND_CHL_OFFSET(p + 2)) {
+					case SCA:
+						oper_bw = CHANNEL_WIDTH_40;
+						oper_offset = HAL_PRIME_CHNL_OFFSET_LOWER;
+						break;
+					case SCB:
+						oper_bw = CHANNEL_WIDTH_40;
+						oper_offset = HAL_PRIME_CHNL_OFFSET_UPPER;
+						break;
+					}
+				}
+			}
+		}
+
+		/* adjust bw to fit in channel plan setting */
+		if (oper_bw == CHANNEL_WIDTH_40
+			&& oper_offset != HAL_PRIME_CHNL_OFFSET_DONT_CARE /* check this because TDLS has no info to set offset */
+			&& (!rtw_chset_is_chbw_valid(chset, channel, oper_bw, oper_offset)
+				|| (IS_DFS_SLAVE_WITH_RD(rfctl)
+					&& !rtw_odm_dfs_domain_unknown(rfctl_to_dvobj(rfctl))
+					&& rtw_chset_is_chbw_non_ocp(chset, channel, oper_bw, oper_offset))
+				)
+		) {
+			oper_bw = CHANNEL_WIDTH_20;
+			oper_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
+			rtw_warn_on(!rtw_chset_is_chbw_valid(chset, channel, oper_bw, oper_offset));
+			if (IS_DFS_SLAVE_WITH_RD(rfctl) && !rtw_odm_dfs_domain_unknown(rfctl_to_dvobj(rfctl)))
+				rtw_warn_on(rtw_chset_is_chbw_non_ocp(chset, channel, oper_bw, oper_offset));
+		}
+
+		if (oper_bw == CHANNEL_WIDTH_40) {
+			ht_capie.cap_info |= IEEE80211_HT_CAP_SUP_WIDTH;
+			if (phtpriv->sgi_40m)
+				ht_capie.cap_info |= IEEE80211_HT_CAP_SGI_40;
+		}
+
+		cbw40_enable = oper_bw == CHANNEL_WIDTH_40 ? 1 : 0;
+	}
+
+	/* todo: disable SM power save mode */
+	ht_capie.cap_info |= IEEE80211_HT_CAP_SM_PS;
+
+	/* RX LDPC */
+	if (TEST_FLAG(phtpriv->ldpc_cap, LDPC_HT_ENABLE_RX)) {
+		ht_capie.cap_info |= IEEE80211_HT_CAP_LDPC_CODING;
+		RTW_INFO("[HT] Declare supporting RX LDPC\n");
+	}
+
+	/* TX STBC */
+	if (TEST_FLAG(phtpriv->stbc_cap, STBC_HT_ENABLE_TX)) {
+		ht_capie.cap_info |= IEEE80211_HT_CAP_TX_STBC;
+		RTW_INFO("[HT] Declare supporting TX STBC\n");
+	}
+
+	/* RX STBC */
+	if (TEST_FLAG(phtpriv->stbc_cap, STBC_HT_ENABLE_RX)) {
+		if ((pregistrypriv->rx_stbc == 0x3) ||							/* enable for 2.4/5 GHz */
+		    ((channel <= 14) && (pregistrypriv->rx_stbc == 0x1)) ||		/* enable for 2.4GHz */
+		    ((channel > 14) && (pregistrypriv->rx_stbc == 0x2)) ||		/* enable for 5GHz */
+		    (pregistrypriv->wifi_spec == 1)) {
+			/* HAL_DEF_RX_STBC means STBC RX spatial stream, todo: VHT 4 streams */
+			rtw_hal_get_def_var(padapter, HAL_DEF_RX_STBC, (u8 *)(&rx_stbc_nss));
+			SET_HT_CAP_ELE_RX_STBC(&ht_capie, rx_stbc_nss);
+			RTW_INFO("[HT] Declare supporting RX STBC = %d\n", rx_stbc_nss);
+		}
+	}
+
+	/* fill default supported_mcs_set */
+	_rtw_memcpy(ht_capie.supp_mcs_set, pmlmeext->default_supported_mcs_set, 16);
+
+	/* update default supported_mcs_set */
+	rtw_hal_get_hwreg(padapter, HW_VAR_RF_TYPE, (u8 *)(&rf_type));
+	rx_nss = rtw_min(rf_type_to_rf_rx_cnt(rf_type), hal_spec->rx_nss_num);
+
+	switch (rx_nss) {
+	case 1:
+		set_mcs_rate_by_mask(ht_capie.supp_mcs_set, MCS_RATE_1R);
+		break;
+	case 2:
+		#ifdef CONFIG_DISABLE_MCS13TO15
+		if (cbw40_enable && pregistrypriv->wifi_spec != 1)
+			set_mcs_rate_by_mask(ht_capie.supp_mcs_set, MCS_RATE_2R_13TO15_OFF);
+		else
+		#endif
+			set_mcs_rate_by_mask(ht_capie.supp_mcs_set, MCS_RATE_2R);
+		break;
+	case 3:
+		set_mcs_rate_by_mask(ht_capie.supp_mcs_set, MCS_RATE_3R);
+		break;
+	case 4:
+		set_mcs_rate_by_mask(ht_capie.supp_mcs_set, MCS_RATE_4R);
+		break;
+	default:
+		RTW_WARN("rf_type:%d or rx_nss:%u is not expected\n", rf_type, hal_spec->rx_nss_num);
+	}
+
+	{
+		rtw_hal_get_def_var(padapter, HAL_DEF_RX_PACKET_OFFSET, &rx_packet_offset);
+		rtw_hal_get_def_var(padapter, HAL_DEF_MAX_RECVBUF_SZ, &max_recvbuf_sz);
+		if (max_recvbuf_sz - rx_packet_offset >= (8191 - 256)) {
+			RTW_INFO("%s IEEE80211_HT_CAP_MAX_AMSDU is set\n", __FUNCTION__);
+			ht_capie.cap_info = ht_capie.cap_info | IEEE80211_HT_CAP_MAX_AMSDU;
+		}
+	}
+	/*
+	AMPDU_para [1:0]:Max AMPDU Len => 0:8k , 1:16k, 2:32k, 3:64k
+	AMPDU_para [4:2]:Min MPDU Start Spacing
+	*/
+
+	/*
+	#if defined(CONFIG_RTL8188E) && defined(CONFIG_SDIO_HCI)
+	ht_capie.ampdu_params_info = 2;
+	#else
+	ht_capie.ampdu_params_info = (IEEE80211_HT_CAP_AMPDU_FACTOR&0x03);
+	#endif
+	*/
+
+	if (padapter->driver_rx_ampdu_factor != 0xFF)
+		max_rx_ampdu_factor = (HT_CAP_AMPDU_FACTOR)padapter->driver_rx_ampdu_factor;
+	else
+		rtw_hal_get_def_var(padapter, HW_VAR_MAX_RX_AMPDU_FACTOR, &max_rx_ampdu_factor);
+
+	/* rtw_hal_get_def_var(padapter, HW_VAR_MAX_RX_AMPDU_FACTOR, &max_rx_ampdu_factor); */
+	ht_capie.ampdu_params_info = (max_rx_ampdu_factor & 0x03);
+
+	if (padapter->driver_rx_ampdu_spacing != 0xFF)
+		ht_capie.ampdu_params_info |= ((padapter->driver_rx_ampdu_spacing & 0x07) << 2);
+	else {
+		if (padapter->securitypriv.dot11PrivacyAlgrthm == _AES_) {
+			/*
+			*	Todo : Each chip must to ask DD , this chip best ampdu_density setting
+			*	By yiwei.sun
+			*/
+			rtw_hal_get_def_var(padapter, HW_VAR_BEST_AMPDU_DENSITY, &best_ampdu_density);
+
+			ht_capie.ampdu_params_info |= (IEEE80211_HT_CAP_AMPDU_DENSITY & (best_ampdu_density << 2));
+
+		} else
+			ht_capie.ampdu_params_info |= (IEEE80211_HT_CAP_AMPDU_DENSITY & 0x00);
+	}
+#ifdef CONFIG_BEAMFORMING
+	ht_capie.tx_BF_cap_info = 0;
+
+	/* HT Beamformer*/
+	if (TEST_FLAG(phtpriv->beamform_cap, BEAMFORMING_HT_BEAMFORMER_ENABLE)) {
+		/* Transmit NDP Capable */
+		SET_HT_CAP_TXBF_TRANSMIT_NDP_CAP(&ht_capie, 1);
+		/* Explicit Compressed Steering Capable */
+		SET_HT_CAP_TXBF_EXPLICIT_COMP_STEERING_CAP(&ht_capie, 1);
+		/* Compressed Steering Number Antennas */
+		SET_HT_CAP_TXBF_COMP_STEERING_NUM_ANTENNAS(&ht_capie, 1);
+		rtw_hal_get_def_var(padapter, HAL_DEF_BEAMFORMER_CAP, (u8 *)&rf_num);
+		SET_HT_CAP_TXBF_CHNL_ESTIMATION_NUM_ANTENNAS(&ht_capie, rf_num);
+	}
+
+	/* HT Beamformee */
+	if (TEST_FLAG(phtpriv->beamform_cap, BEAMFORMING_HT_BEAMFORMEE_ENABLE)) {
+		/* Receive NDP Capable */
+		SET_HT_CAP_TXBF_RECEIVE_NDP_CAP(&ht_capie, 1);
+		/* Explicit Compressed Beamforming Feedback Capable */
+		SET_HT_CAP_TXBF_EXPLICIT_COMP_FEEDBACK_CAP(&ht_capie, 2);
+
+		rtw_hal_get_def_var(padapter, HAL_DEF_BEAMFORMEE_CAP, (u8 *)&rf_num);
+#ifdef CONFIG_80211AC_VHT
+		/* IOT action suggested by Yu Chen 2017/3/3 */
+		if ((pmlmeinfo->assoc_AP_vendor == HT_IOT_PEER_BROADCOM) &&
+			!pvhtpriv->ap_is_mu_bfer)
+			rf_num = (rf_num >= 2 ? 2 : rf_num);
+#endif
+		SET_HT_CAP_TXBF_COMP_STEERING_NUM_ANTENNAS(&ht_capie, rf_num);
+	}
+#endif/*CONFIG_BEAMFORMING*/
+
+	pframe = rtw_set_ie(out_ie + out_len, _HT_CAPABILITY_IE_,
+		sizeof(struct rtw_ieee80211_ht_cap), (unsigned char *)&ht_capie, pout_len);
+
+	phtpriv->ht_option = _TRUE;
+
+	if (in_ie != NULL) {
+		p = rtw_get_ie(in_ie, _HT_ADD_INFO_IE_, &ielen, in_len);
+		if (p && (ielen == sizeof(struct ieee80211_ht_addt_info))) {
+			out_len = *pout_len;
+			pframe = rtw_set_ie(out_ie + out_len, _HT_ADD_INFO_IE_, ielen, p + 2 , pout_len);
+		}
+	}
+
+	return phtpriv->ht_option;
+
+}
+
+/* the fucntion is > passive_level (in critical_section) */
+void rtw_update_ht_cap(_adapter *padapter, u8 *pie, uint ie_len, u8 channel)
+{
+	u8 *p, max_ampdu_sz;
+	int len;
+	/* struct sta_info *bmc_sta, *psta; */
+	struct rtw_ieee80211_ht_cap *pht_capie;
+	struct ieee80211_ht_addt_info *pht_addtinfo;
+	/* struct recv_reorder_ctrl *preorder_ctrl; */
+	struct mlme_priv	*pmlmepriv = &padapter->mlmepriv;
+	struct ht_priv		*phtpriv = &pmlmepriv->htpriv;
+	/* struct recv_priv *precvpriv = &padapter->recvpriv; */
+	struct registry_priv *pregistrypriv = &padapter->registrypriv;
+	/* struct wlan_network *pcur_network = &(pmlmepriv->cur_network);; */
+	struct mlme_ext_priv	*pmlmeext = &padapter->mlmeextpriv;
+	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
+	u8 cbw40_enable = 0;
+
+
+	if (!phtpriv->ht_option)
+		return;
+
+	if ((!pmlmeinfo->HT_info_enable) || (!pmlmeinfo->HT_caps_enable))
+		return;
+
+	RTW_INFO("+rtw_update_ht_cap()\n");
+
+	/* maybe needs check if ap supports rx ampdu. */
+	if ((phtpriv->ampdu_enable == _FALSE) && (pregistrypriv->ampdu_enable == 1)) {
+		if (pregistrypriv->wifi_spec == 1) {
+			/* remove this part because testbed AP should disable RX AMPDU */
+			/* phtpriv->ampdu_enable = _FALSE; */
+			phtpriv->ampdu_enable = _TRUE;
+		} else
+			phtpriv->ampdu_enable = _TRUE;
+	} 
+
+
+	/* check Max Rx A-MPDU Size */
+	len = 0;
+	p = rtw_get_ie(pie + sizeof(NDIS_802_11_FIXED_IEs), _HT_CAPABILITY_IE_, &len, ie_len - sizeof(NDIS_802_11_FIXED_IEs));
+	if (p && len > 0) {
+		pht_capie = (struct rtw_ieee80211_ht_cap *)(p + 2);
+		max_ampdu_sz = (pht_capie->ampdu_params_info & IEEE80211_HT_CAP_AMPDU_FACTOR);
+		max_ampdu_sz = 1 << (max_ampdu_sz + 3); /* max_ampdu_sz (kbytes); */
+
+		/* RTW_INFO("rtw_update_ht_cap(): max_ampdu_sz=%d\n", max_ampdu_sz); */
+		phtpriv->rx_ampdu_maxlen = max_ampdu_sz;
+
+	}
+
+
+	len = 0;
+	p = rtw_get_ie(pie + sizeof(NDIS_802_11_FIXED_IEs), _HT_ADD_INFO_IE_, &len, ie_len - sizeof(NDIS_802_11_FIXED_IEs));
+	if (p && len > 0) {
+		pht_addtinfo = (struct ieee80211_ht_addt_info *)(p + 2);
+		/* todo: */
+	}
+
+	if (hal_chk_bw_cap(padapter, BW_CAP_40M)) {
+		if (channel > 14) {
+			if (REGSTY_IS_BW_5G_SUPPORT(pregistrypriv, CHANNEL_WIDTH_40))
+				cbw40_enable = 1;
+		} else {
+			if (REGSTY_IS_BW_2G_SUPPORT(pregistrypriv, CHANNEL_WIDTH_40))
+				cbw40_enable = 1;
+		}
+	}
+
+	/* update cur_bwmode & cur_ch_offset */
+	if ((cbw40_enable) &&
+	    (pmlmeinfo->HT_caps.u.HT_cap_element.HT_caps_info & BIT(1)) &&
+	    (pmlmeinfo->HT_info.infos[0] & BIT(2))) {
+		struct hal_spec_t *hal_spec = GET_HAL_SPEC(padapter);
+		int i;
+		u8	rf_type = RF_1T1R;
+		u8 tx_nss = 0;
+
+		rtw_hal_get_hwreg(padapter, HW_VAR_RF_TYPE, (u8 *)(&rf_type));
+		tx_nss = rtw_min(rf_type_to_rf_tx_cnt(rf_type), hal_spec->tx_nss_num);
+
+		/* update the MCS set */
+		for (i = 0; i < 16; i++)
+			pmlmeinfo->HT_caps.u.HT_cap_element.MCS_rate[i] &= pmlmeext->default_supported_mcs_set[i];
+
+		/* update the MCS rates */
+		switch (tx_nss) {
+		case 1:
+			set_mcs_rate_by_mask(pmlmeinfo->HT_caps.u.HT_cap_element.MCS_rate, MCS_RATE_1R);
+			break;
+		case 2:
+			#ifdef CONFIG_DISABLE_MCS13TO15
+			if (pmlmeext->cur_bwmode == CHANNEL_WIDTH_40 && pregistrypriv->wifi_spec != 1)
+				set_mcs_rate_by_mask(pmlmeinfo->HT_caps.u.HT_cap_element.MCS_rate, MCS_RATE_2R_13TO15_OFF);
+			else
+			#endif
+				set_mcs_rate_by_mask(pmlmeinfo->HT_caps.u.HT_cap_element.MCS_rate, MCS_RATE_2R);
+			break;
+		case 3:
+			set_mcs_rate_by_mask(pmlmeinfo->HT_caps.u.HT_cap_element.MCS_rate, MCS_RATE_3R);
+			break;
+		case 4:
+			set_mcs_rate_by_mask(pmlmeinfo->HT_caps.u.HT_cap_element.MCS_rate, MCS_RATE_4R);
+			break;
+		default:
+			RTW_WARN("rf_type:%d or tx_nss_num:%u is not expected\n", rf_type, hal_spec->tx_nss_num);
+		}
+
+		/* switch to the 40M Hz mode accoring to the AP */
+		/* pmlmeext->cur_bwmode = CHANNEL_WIDTH_40; */
+		switch ((pmlmeinfo->HT_info.infos[0] & 0x3)) {
+		case EXTCHNL_OFFSET_UPPER:
+			pmlmeext->cur_ch_offset = HAL_PRIME_CHNL_OFFSET_LOWER;
+			break;
+
+		case EXTCHNL_OFFSET_LOWER:
+			pmlmeext->cur_ch_offset = HAL_PRIME_CHNL_OFFSET_UPPER;
+			break;
+
+		default:
+			pmlmeext->cur_ch_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
+			break;
+		}
+	}
+
+	/*  */
+	/* Config SM Power Save setting */
+	/*  */
+	pmlmeinfo->SM_PS = (pmlmeinfo->HT_caps.u.HT_cap_element.HT_caps_info & 0x0C) >> 2;
+	if (pmlmeinfo->SM_PS == WLAN_HT_CAP_SM_PS_STATIC) {
+#if 0
+		u8 i;
+		/* update the MCS rates */
+		for (i = 0; i < 16; i++)
+			pmlmeinfo->HT_caps.HT_cap_element.MCS_rate[i] &= MCS_rate_1R[i];
+#endif
+		RTW_INFO("%s(): WLAN_HT_CAP_SM_PS_STATIC\n", __FUNCTION__);
+	}
+
+	/*  */
+	/* Config current HT Protection mode. */
+	/*  */
+	pmlmeinfo->HT_protection = pmlmeinfo->HT_info.infos[1] & 0x3;
+}
+#endif
+
+#ifdef CONFIG_TDLS
+void rtw_issue_addbareq_cmd_tdls(_adapter *padapter, struct xmit_frame *pxmitframe)
+{
+	struct pkt_attrib *pattrib = &pxmitframe->attrib;
+	struct sta_info *ptdls_sta = NULL;
+	u8 issued;
+	int priority;
+	struct ht_priv	*phtpriv;
+
+	priority = pattrib->priority;
+
+	if (pattrib->direct_link == _TRUE) {
+		ptdls_sta = rtw_get_stainfo(&padapter->stapriv, pattrib->dst);
+		if ((ptdls_sta != NULL) && (ptdls_sta->tdls_sta_state & TDLS_LINKED_STATE)) {
+			phtpriv = &ptdls_sta->htpriv;
+
+			if ((phtpriv->ht_option == _TRUE) && (phtpriv->ampdu_enable == _TRUE)) {
+				issued = (phtpriv->agg_enable_bitmap >> priority) & 0x1;
+				issued |= (phtpriv->candidate_tid_bitmap >> priority) & 0x1;
+
+				if (0 == issued) {
+					RTW_INFO("[%s], p=%d\n", __FUNCTION__, priority);
+					ptdls_sta->htpriv.candidate_tid_bitmap |= BIT((u8)priority);
+					rtw_addbareq_cmd(padapter, (u8)priority, pattrib->dst);
+				}
+			}
+		}
+	}
+}
+#endif /* CONFIG_TDLS */
+
+#ifdef CONFIG_80211N_HT
+void rtw_issue_addbareq_cmd(_adapter *padapter, struct xmit_frame *pxmitframe)
+{
+	u8 issued;
+	int priority;
+	struct sta_info *psta = NULL;
+	struct ht_priv	*phtpriv;
+	struct pkt_attrib *pattrib = &pxmitframe->attrib;
+	s32 bmcst = IS_MCAST(pattrib->ra);
+
+	/* if(bmcst || (padapter->mlmepriv.LinkDetectInfo.bTxBusyTraffic == _FALSE)) */
+	if (bmcst || (padapter->mlmepriv.LinkDetectInfo.NumTxOkInPeriod < 100))
+		return;
+
+	priority = pattrib->priority;
+
+#ifdef CONFIG_TDLS
+	rtw_issue_addbareq_cmd_tdls(padapter, pxmitframe);
+#endif /* CONFIG_TDLS */
+
+	psta = rtw_get_stainfo(&padapter->stapriv, pattrib->ra);
+	if (pattrib->psta != psta) {
+		RTW_INFO("%s, pattrib->psta(%p) != psta(%p)\n", __func__, pattrib->psta, psta);
+		return;
+	}
+
+	if (psta == NULL) {
+		RTW_INFO("%s, psta==NUL\n", __func__);
+		return;
+	}
+
+	if (!(psta->state & _FW_LINKED)) {
+		RTW_INFO("%s, psta->state(0x%x) != _FW_LINKED\n", __func__, psta->state);
+		return;
+	}
+
+
+	phtpriv = &psta->htpriv;
+
+	if ((phtpriv->ht_option == _TRUE) && (phtpriv->ampdu_enable == _TRUE)) {
+		issued = (phtpriv->agg_enable_bitmap >> priority) & 0x1;
+		issued |= (phtpriv->candidate_tid_bitmap >> priority) & 0x1;
+
+		if (0 == issued) {
+			RTW_INFO("rtw_issue_addbareq_cmd, p=%d\n", priority);
+			psta->htpriv.candidate_tid_bitmap |= BIT((u8)priority);
+			rtw_addbareq_cmd(padapter, (u8) priority, pattrib->ra);
+		}
+	}
+
+}
+#endif /* CONFIG_80211N_HT */
+void rtw_append_exented_cap(_adapter *padapter, u8 *out_ie, uint *pout_len)
+{
+	struct mlme_priv	*pmlmepriv = &padapter->mlmepriv;
+	struct ht_priv		*phtpriv = &pmlmepriv->htpriv;
+#ifdef CONFIG_80211AC_VHT
+	struct vht_priv	*pvhtpriv = &pmlmepriv->vhtpriv;
+#endif /* CONFIG_80211AC_VHT */
+	u8	cap_content[8] = { 0 };
+	u8	*pframe;
+	u8   null_content[8] = {0};
+
+	if (phtpriv->bss_coexist)
+		SET_EXT_CAPABILITY_ELE_BSS_COEXIST(cap_content, 1);
+
+#ifdef CONFIG_80211AC_VHT
+	if (pvhtpriv->vht_option)
+		SET_EXT_CAPABILITY_ELE_OP_MODE_NOTIF(cap_content, 1);
+#endif /* CONFIG_80211AC_VHT */
+#ifdef CONFIG_RTW_WNM
+	rtw_wnm_set_ext_cap_btm(cap_content, 1);
+#endif
+	/*
+		From 802.11 specification,if a STA does not support any of capabilities defined
+		in the Extended Capabilities element, then the STA is not required to
+		transmit the Extended Capabilities element.
+	*/
+	if (_FALSE == _rtw_memcmp(cap_content, null_content, 8))
+		pframe = rtw_set_ie(out_ie + *pout_len, EID_EXTCapability, 8, cap_content , pout_len);
+}
+#endif
+
+#ifdef CONFIG_LAYER2_ROAMING
+inline void rtw_set_to_roam(_adapter *adapter, u8 to_roam)
+{
+	if (to_roam == 0)
+		adapter->mlmepriv.to_join = _FALSE;
+	adapter->mlmepriv.to_roam = to_roam;
+}
+
+inline u8 rtw_dec_to_roam(_adapter *adapter)
+{
+	adapter->mlmepriv.to_roam--;
+	return adapter->mlmepriv.to_roam;
+}
+
+inline u8 rtw_to_roam(_adapter *adapter)
+{
+	return adapter->mlmepriv.to_roam;
+}
+
+void rtw_roaming(_adapter *padapter, struct wlan_network *tgt_network)
+{
+	_irqL irqL;
+	struct mlme_priv	*pmlmepriv = &padapter->mlmepriv;
+
+	_enter_critical_bh(&pmlmepriv->lock, &irqL);
+	_rtw_roaming(padapter, tgt_network);
+	_exit_critical_bh(&pmlmepriv->lock, &irqL);
+}
+void _rtw_roaming(_adapter *padapter, struct wlan_network *tgt_network)
+{
+	struct mlme_priv	*pmlmepriv = &padapter->mlmepriv;
+	struct wlan_network *cur_network = &pmlmepriv->cur_network;
+	int do_join_r;
+
+	if (0 < rtw_to_roam(padapter)) {
+		RTW_INFO("roaming from %s("MAC_FMT"), length:%d\n",
+			cur_network->network.Ssid.Ssid, MAC_ARG(cur_network->network.MacAddress),
+			 cur_network->network.Ssid.SsidLength);
+		_rtw_memcpy(&pmlmepriv->assoc_ssid, &cur_network->network.Ssid, sizeof(NDIS_802_11_SSID));
+
+		pmlmepriv->assoc_by_bssid = _FALSE;
+
+#ifdef CONFIG_WAPI_SUPPORT
+		rtw_wapi_return_all_sta_info(padapter);
+#endif
+
+		while (1) {
+			do_join_r = rtw_do_join(padapter);
+			if (_SUCCESS == do_join_r)
+				break;
+			else {
+				RTW_INFO("roaming do_join return %d\n", do_join_r);
+				rtw_dec_to_roam(padapter);
+
+				if (rtw_to_roam(padapter) > 0)
+					continue;
+				else {
+					RTW_INFO("%s(%d) -to roaming fail, indicate_disconnect\n", __FUNCTION__, __LINE__);
+#ifdef CONFIG_RTW_80211R
+					rtw_ft_clr_flags(padapter, RTW_FT_PEER_EN|RTW_FT_PEER_OTD_EN);
+					rtw_ft_reset_status(padapter);
+#endif
+					rtw_indicate_disconnect(padapter, 0, _FALSE);
+					break;
+				}
+			}
+		}
+	}
+
+}
+#endif /* CONFIG_LAYER2_ROAMING */
+
+bool rtw_adjust_chbw(_adapter *adapter, u8 req_ch, u8 *req_bw, u8 *req_offset)
+{
+	struct registry_priv *regsty = adapter_to_regsty(adapter);
+	u8 allowed_bw;
+
+	if (req_ch < 14)
+		allowed_bw = REGSTY_BW_2G(regsty);
+	else if (req_ch == 14)
+		allowed_bw = CHANNEL_WIDTH_20;
+	else
+		allowed_bw = REGSTY_BW_5G(regsty);
+
+	allowed_bw = hal_largest_bw(adapter, allowed_bw);
+
+	if (allowed_bw == CHANNEL_WIDTH_80 && *req_bw > CHANNEL_WIDTH_80)
+		*req_bw = CHANNEL_WIDTH_80;
+	else if (allowed_bw == CHANNEL_WIDTH_40 && *req_bw > CHANNEL_WIDTH_40)
+		*req_bw = CHANNEL_WIDTH_40;
+	else if (allowed_bw == CHANNEL_WIDTH_20 && *req_bw > CHANNEL_WIDTH_20) {
+		*req_bw = CHANNEL_WIDTH_20;
+		*req_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
+	} else
+		return _FALSE;
+
+	return _TRUE;
+}
+
+sint rtw_linked_check(_adapter *padapter)
+{
+	if (MLME_IS_AP(padapter) || MLME_IS_MESH(padapter)
+		|| MLME_IS_ADHOC(padapter) || MLME_IS_ADHOC_MASTER(padapter)
+	) {
+		if (padapter->stapriv.asoc_sta_count > 2)
+			return _TRUE;
+	} else {
+		/* Station mode */
+		if (check_fwstate(&padapter->mlmepriv, _FW_LINKED) == _TRUE)
+			return _TRUE;
+	}
+	return _FALSE;
+}
+/*#define DBG_ADAPTER_STATE_CHK*/
+u8 rtw_is_adapter_up(_adapter *padapter)
+{
+	if (padapter == NULL)
+		return _FALSE;
+
+	if (RTW_CANNOT_RUN(padapter)) {
+		#ifdef DBG_ADAPTER_STATE_CHK
+		RTW_INFO(FUNC_ADPT_FMT " FALSE -bDriverStopped(%s) bSurpriseRemoved(%s)\n"
+			, FUNC_ADPT_ARG(padapter)
+			, rtw_is_drv_stopped(padapter) ? "True" : "False"
+			, rtw_is_surprise_removed(padapter) ? "True" : "False");
+		#endif
+		return _FALSE;
+	}
+
+	if (!rtw_is_hw_init_completed(padapter)) {
+		#ifdef DBG_ADAPTER_STATE_CHK
+		RTW_INFO(FUNC_ADPT_FMT " FALSE -(hw_init_completed == _FALSE)\n", FUNC_ADPT_ARG(padapter));
+		#endif
+		return _FALSE;
+	}
+
+	if (padapter->bup == _FALSE) {
+		#ifdef DBG_ADAPTER_STATE_CHK
+		RTW_INFO(FUNC_ADPT_FMT " FALSE -(bup == _FALSE)\n", FUNC_ADPT_ARG(padapter));
+		#endif
+		return _FALSE;
+	}
+
+	return _TRUE;
+}
+
+bool is_miracast_enabled(_adapter *adapter)
+{
+	bool enabled = 0;
+#ifdef CONFIG_WFD
+	struct wifi_display_info *wfdinfo = &adapter->wfd_info;
+
+	enabled = (wfdinfo->stack_wfd_mode & (MIRACAST_SOURCE | MIRACAST_SINK))
+		  || (wfdinfo->op_wfd_mode & (MIRACAST_SOURCE | MIRACAST_SINK));
+#endif
+
+	return enabled;
+}
+
+bool rtw_chk_miracast_mode(_adapter *adapter, u8 mode)
+{
+	bool ret = 0;
+#ifdef CONFIG_WFD
+	struct wifi_display_info *wfdinfo = &adapter->wfd_info;
+
+	ret = (wfdinfo->stack_wfd_mode & mode) || (wfdinfo->op_wfd_mode & mode);
+#endif
+
+	return ret;
+}
+
+const char *get_miracast_mode_str(int mode)
+{
+	if (mode == MIRACAST_SOURCE)
+		return "SOURCE";
+	else if (mode == MIRACAST_SINK)
+		return "SINK";
+	else if (mode == (MIRACAST_SOURCE | MIRACAST_SINK))
+		return "SOURCE&SINK";
+	else if (mode == MIRACAST_DISABLED)
+		return "DISABLED";
+	else
+		return "INVALID";
+}
+
+#ifdef CONFIG_WFD
+static bool wfd_st_match_rule(_adapter *adapter, u8 *local_naddr, u8 *local_port, u8 *remote_naddr, u8 *remote_port)
+{
+	struct wifi_display_info *wfdinfo = &adapter->wfd_info;
+
+	if (ntohs(*((u16 *)local_port)) == wfdinfo->rtsp_ctrlport
+	    || ntohs(*((u16 *)local_port)) == wfdinfo->tdls_rtsp_ctrlport
+	    || ntohs(*((u16 *)remote_port)) == wfdinfo->peer_rtsp_ctrlport)
+		return _TRUE;
+	return _FALSE;
+}
+
+static struct st_register wfd_st_reg = {
+	.s_proto = 0x06,
+	.rule = wfd_st_match_rule,
+};
+#endif /* CONFIG_WFD */
+
+inline void rtw_wfd_st_switch(struct sta_info *sta, bool on)
+{
+#ifdef CONFIG_WFD
+	if (on)
+		rtw_st_ctl_register(&sta->st_ctl, SESSION_TRACKER_REG_ID_WFD, &wfd_st_reg);
+	else
+		rtw_st_ctl_unregister(&sta->st_ctl, SESSION_TRACKER_REG_ID_WFD);
+#endif
+}
+
+void dump_arp_pkt(void *sel, u8 *da, u8 *sa, u8 *arp, bool tx)
+{
+	RTW_PRINT_SEL(sel, "%s ARP da="MAC_FMT", sa="MAC_FMT"\n"
+		, tx ? "send" : "recv", MAC_ARG(da), MAC_ARG(sa));
+	RTW_PRINT_SEL(sel, "htype=%u, ptype=0x%04x, hlen=%u, plen=%u, oper=%u\n"
+		, GET_ARP_HTYPE(arp), GET_ARP_PTYPE(arp), GET_ARP_HLEN(arp)
+		, GET_ARP_PLEN(arp), GET_ARP_OPER(arp));
+	RTW_PRINT_SEL(sel, "sha="MAC_FMT", spa="IP_FMT"\n"
+		, MAC_ARG(ARP_SENDER_MAC_ADDR(arp)), IP_ARG(ARP_SENDER_IP_ADDR(arp)));
+	RTW_PRINT_SEL(sel, "tha="MAC_FMT", tpa="IP_FMT"\n"
+		, MAC_ARG(ARP_TARGET_MAC_ADDR(arp)), IP_ARG(ARP_TARGET_IP_ADDR(arp)));
+}
+
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/core/rtw_mlme_ext.c linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/core/rtw_mlme_ext.c
--- linux-5.6.3/3rdparty/rtl8821ce/core/rtw_mlme_ext.c	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/core/rtw_mlme_ext.c	2020-04-10 16:35:06.776658200 +0300
@@ -0,0 +1,16488 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#define _RTW_MLME_EXT_C_
+
+#include <drv_types.h>
+#ifdef CONFIG_IOCTL_CFG80211
+	#include <rtw_wifi_regd.h>
+#endif /* CONFIG_IOCTL_CFG80211 */
+#include <hal_data.h>
+
+
+struct mlme_handler mlme_sta_tbl[] = {
+	{WIFI_ASSOCREQ,		"OnAssocReq",	&OnAssocReq},
+	{WIFI_ASSOCRSP,		"OnAssocRsp",	&OnAssocRsp},
+	{WIFI_REASSOCREQ,	"OnReAssocReq",	&OnAssocReq},
+	{WIFI_REASSOCRSP,	"OnReAssocRsp",	&OnAssocRsp},
+	{WIFI_PROBEREQ,		"OnProbeReq",	&OnProbeReq},
+	{WIFI_PROBERSP,		"OnProbeRsp",		&OnProbeRsp},
+
+	/*----------------------------------------------------------
+					below 2 are reserved
+	-----------------------------------------------------------*/
+	{0,					"DoReserved",		&DoReserved},
+	{0,					"DoReserved",		&DoReserved},
+	{WIFI_BEACON,		"OnBeacon",		&OnBeacon},
+	{WIFI_ATIM,			"OnATIM",		&OnAtim},
+	{WIFI_DISASSOC,		"OnDisassoc",		&OnDisassoc},
+	{WIFI_AUTH,			"OnAuth",		&OnAuthClient},
+	{WIFI_DEAUTH,		"OnDeAuth",		&OnDeAuth},
+	{WIFI_ACTION,		"OnAction",		&OnAction},
+	{WIFI_ACTION_NOACK, "OnActionNoAck",	&OnAction},
+};
+
+#ifdef _CONFIG_NATIVEAP_MLME_
+struct mlme_handler mlme_ap_tbl[] = {
+	{WIFI_ASSOCREQ,		"OnAssocReq",	&OnAssocReq},
+	{WIFI_ASSOCRSP,		"OnAssocRsp",	&OnAssocRsp},
+	{WIFI_REASSOCREQ,	"OnReAssocReq",	&OnAssocReq},
+	{WIFI_REASSOCRSP,	"OnReAssocRsp",	&OnAssocRsp},
+	{WIFI_PROBEREQ,		"OnProbeReq",	&OnProbeReq},
+	{WIFI_PROBERSP,		"OnProbeRsp",		&OnProbeRsp},
+
+	/*----------------------------------------------------------
+					below 2 are reserved
+	-----------------------------------------------------------*/
+	{0,					"DoReserved",		&DoReserved},
+	{0,					"DoReserved",		&DoReserved},
+	{WIFI_BEACON,		"OnBeacon",		&OnBeacon},
+	{WIFI_ATIM,			"OnATIM",		&OnAtim},
+	{WIFI_DISASSOC,		"OnDisassoc",		&OnDisassoc},
+	{WIFI_AUTH,			"OnAuth",		&OnAuth},
+	{WIFI_DEAUTH,		"OnDeAuth",		&OnDeAuth},
+	{WIFI_ACTION,		"OnAction",		&OnAction},
+	{WIFI_ACTION_NOACK, "OnActionNoAck",	&OnAction},
+};
+#endif
+
+struct action_handler OnAction_tbl[] = {
+	{RTW_WLAN_CATEGORY_SPECTRUM_MGMT,	 "ACTION_SPECTRUM_MGMT", on_action_spct},
+	{RTW_WLAN_CATEGORY_QOS, "ACTION_QOS", &OnAction_qos},
+	{RTW_WLAN_CATEGORY_DLS, "ACTION_DLS", &OnAction_dls},
+	{RTW_WLAN_CATEGORY_BACK, "ACTION_BACK", &OnAction_back},
+	{RTW_WLAN_CATEGORY_PUBLIC, "ACTION_PUBLIC", on_action_public},
+	{RTW_WLAN_CATEGORY_RADIO_MEAS, "ACTION_RADIO_MEAS", &on_action_rm},
+	{RTW_WLAN_CATEGORY_FT, "ACTION_FT",	&OnAction_ft},
+	{RTW_WLAN_CATEGORY_HT,	"ACTION_HT",	&OnAction_ht},
+#ifdef CONFIG_IEEE80211W
+	{RTW_WLAN_CATEGORY_SA_QUERY, "ACTION_SA_QUERY", &OnAction_sa_query},
+#else
+	{RTW_WLAN_CATEGORY_SA_QUERY, "ACTION_SA_QUERY", &DoReserved},
+#endif /* CONFIG_IEEE80211W */
+#ifdef CONFIG_RTW_WNM
+	{RTW_WLAN_CATEGORY_WNM, "ACTION_WNM", &on_action_wnm},
+#endif
+	{RTW_WLAN_CATEGORY_UNPROTECTED_WNM, "ACTION_UNPROTECTED_WNM", &DoReserved},
+#ifdef CONFIG_RTW_MESH
+	{RTW_WLAN_CATEGORY_MESH, "ACTION_MESH", &on_action_mesh},
+	{RTW_WLAN_CATEGORY_SELF_PROTECTED, "ACTION_SELF_PROTECTED", &on_action_self_protected},
+#endif
+	{RTW_WLAN_CATEGORY_WMM, "ACTION_WMM", &OnAction_wmm},
+	{RTW_WLAN_CATEGORY_VHT, "ACTION_VHT", &OnAction_vht},
+	{RTW_WLAN_CATEGORY_P2P, "ACTION_P2P", &OnAction_p2p},
+};
+
+
+u8	null_addr[ETH_ALEN] = {0, 0, 0, 0, 0, 0};
+
+/**************************************************
+OUI definitions for the vendor specific IE
+***************************************************/
+unsigned char	RTW_WPA_OUI[] = {0x00, 0x50, 0xf2, 0x01};
+unsigned char WMM_OUI[] = {0x00, 0x50, 0xf2, 0x02};
+unsigned char	WPS_OUI[] = {0x00, 0x50, 0xf2, 0x04};
+unsigned char	P2P_OUI[] = {0x50, 0x6F, 0x9A, 0x09};
+unsigned char	WFD_OUI[] = {0x50, 0x6F, 0x9A, 0x0A};
+
+unsigned char	WMM_INFO_OUI[] = {0x00, 0x50, 0xf2, 0x02, 0x00, 0x01};
+unsigned char	WMM_PARA_OUI[] = {0x00, 0x50, 0xf2, 0x02, 0x01, 0x01};
+
+unsigned char WPA_TKIP_CIPHER[4] = {0x00, 0x50, 0xf2, 0x02};
+unsigned char RSN_TKIP_CIPHER[4] = {0x00, 0x0f, 0xac, 0x02};
+
+extern unsigned char REALTEK_96B_IE[];
+
+static void init_channel_list(_adapter *padapter, RT_CHANNEL_INFO *channel_set
+	, struct p2p_channels *channel_list)
+{
+	struct registry_priv *regsty = adapter_to_regsty(padapter);
+
+	struct p2p_oper_class_map op_class[] = {
+		{ IEEE80211G,  81,   1,  13,  1, BW20 },
+		{ IEEE80211G,  82,  14,  14,  1, BW20 },
+#if 0 /* Do not enable HT40 on 2 GHz */
+		{ IEEE80211G,  83,   1,   9,  1, BW40PLUS },
+		{ IEEE80211G,  84,   5,  13,  1, BW40MINUS },
+#endif
+		{ IEEE80211A, 115,  36,  48,  4, BW20 },
+		{ IEEE80211A, 116,  36,  44,  8, BW40PLUS },
+		{ IEEE80211A, 117,  40,  48,  8, BW40MINUS },
+		{ IEEE80211A, 124, 149, 161,  4, BW20 },
+		{ IEEE80211A, 125, 149, 169,  4, BW20 },
+		{ IEEE80211A, 126, 149, 157,  8, BW40PLUS },
+		{ IEEE80211A, 127, 153, 161,  8, BW40MINUS },
+		{ -1, 0, 0, 0, 0, BW20 }
+	};
+
+	int cla, op;
+
+	cla = 0;
+
+	for (op = 0; op_class[op].op_class; op++) {
+		u8 ch;
+		struct p2p_oper_class_map *o = &op_class[op];
+		struct p2p_reg_class *reg = NULL;
+
+		for (ch = o->min_chan; ch <= o->max_chan; ch += o->inc) {
+			if (rtw_chset_search_ch(channel_set, ch) == -1)
+				continue;
+#if defined(CONFIG_80211N_HT) || defined(CONFIG_80211AC_VHT)
+			if ((padapter->registrypriv.ht_enable == 0) && (o->inc == 8))
+				continue;
+
+			if ((REGSTY_IS_BW_5G_SUPPORT(regsty, CHANNEL_WIDTH_40)) &&
+			    ((o->bw == BW40MINUS) || (o->bw == BW40PLUS)))
+				continue;
+#endif
+			if (reg == NULL) {
+				reg = &channel_list->reg_class[cla];
+				cla++;
+				reg->reg_class = o->op_class;
+				reg->channels = 0;
+			}
+			reg->channel[reg->channels] = ch;
+			reg->channels++;
+		}
+	}
+	channel_list->reg_classes = cla;
+
+}
+
+#ifdef CONFIG_TXPWR_LIMIT
+void rtw_txpwr_init_regd(struct rf_ctl_t *rfctl)
+{
+	u8 regd;
+	struct regd_exc_ent *exc;
+	struct txpwr_lmt_ent *ent;
+	_irqL irqL;
+
+	_enter_critical_mutex(&rfctl->txpwr_lmt_mutex, &irqL);
+
+	rfctl->regd_name = NULL;
+
+	if (rfctl->txpwr_regd_num == 0) {
+		RTW_PRINT("there is no any txpwr_regd\n");
+		goto release_lock;
+	}
+
+	/* search from exception mapping */
+	exc = _rtw_regd_exc_search(rfctl
+		, rfctl->country_ent ? rfctl->country_ent->alpha2 : NULL
+		, rfctl->ChannelPlan);
+	if (exc) {
+		u8 has_country = (exc->country[0] == '\0' && exc->country[1] == '\0') ? 0 : 1;
+
+		if (strcmp(exc->regd_name, regd_str(TXPWR_LMT_NONE)) == 0)
+			rfctl->regd_name = regd_str(TXPWR_LMT_NONE);
+		else if (strcmp(exc->regd_name, regd_str(TXPWR_LMT_WW)) == 0)
+			rfctl->regd_name = regd_str(TXPWR_LMT_WW);
+		else {
+			ent = _rtw_txpwr_lmt_get_by_name(rfctl, exc->regd_name);
+			if (ent)
+				rfctl->regd_name = ent->regd_name;
+		}
+
+		RTW_PRINT("exception mapping country:%c%c domain:0x%02x to%s regd_name:%s\n"
+			, has_country ? exc->country[0] : '0'
+			, has_country ? exc->country[1] : '0'
+			, exc->domain
+			, rfctl->regd_name ? "" : " unknown"
+			, exc->regd_name
+		);
+		if (rfctl->regd_name)
+			goto release_lock;
+	}
+
+	/* follow default channel plan mapping */
+	regd = rtw_chplan_get_default_regd(rfctl->ChannelPlan);
+	if (regd == TXPWR_LMT_NONE)
+		rfctl->regd_name = regd_str(TXPWR_LMT_NONE);
+	else if (regd == TXPWR_LMT_WW)
+		rfctl->regd_name = regd_str(TXPWR_LMT_WW);
+	else {
+		ent = _rtw_txpwr_lmt_get_by_name(rfctl, regd_str(regd));
+		if (ent)
+			rfctl->regd_name = ent->regd_name;
+	}
+
+	RTW_PRINT("default mapping domain:0x%02x to%s regd_name:%s\n"
+		, rfctl->ChannelPlan
+		, rfctl->regd_name ? "" : " unknown"
+		, regd_str(regd)
+	);
+	if (rfctl->regd_name)
+		goto release_lock;
+
+	switch (regd) {
+	/*
+	* To support older chips without new predefined regd:
+	* - use FCC if IC or CHILE not found
+	* - use ETSI if KCC or ACMA not found
+	*/
+	case TXPWR_LMT_IC:
+	case TXPWR_LMT_KCC:
+	case TXPWR_LMT_ACMA:
+	case TXPWR_LMT_CHILE:
+		if (regd == TXPWR_LMT_IC || regd == TXPWR_LMT_CHILE)
+			regd = TXPWR_LMT_FCC;
+		else if (regd == TXPWR_LMT_KCC || regd == TXPWR_LMT_ACMA)
+			regd = TXPWR_LMT_ETSI;
+		ent = _rtw_txpwr_lmt_get_by_name(rfctl, regd_str(regd));
+		if (ent)
+			rfctl->regd_name = ent->regd_name;
+		RTW_PRINT("alternate regd_name:%s %s\n"
+			, regd_str(regd)
+			, rfctl->regd_name ? "is used" : "not found"
+		);
+		if (rfctl->regd_name)
+			break;
+		__attribute__((__fallthrough__));
+	default:
+		rfctl->regd_name = regd_str(TXPWR_LMT_WW);
+		RTW_PRINT("assign %s for default case\n", regd_str(TXPWR_LMT_WW));
+		break;
+	};
+
+release_lock:
+	_exit_critical_mutex(&rfctl->txpwr_lmt_mutex, &irqL);
+}
+#endif /* CONFIG_TXPWR_LIMIT */
+
+void rtw_rfctl_init(_adapter *adapter)
+{
+	struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter);
+
+	rfctl->max_chan_nums = init_channel_set(adapter, rfctl->ChannelPlan, rfctl->channel_set);
+	init_channel_list(adapter, rfctl->channel_set, &rfctl->channel_list);
+
+	_rtw_mutex_init(&rfctl->offch_mutex);
+
+#ifdef CONFIG_TXPWR_LIMIT
+	_rtw_mutex_init(&rfctl->txpwr_lmt_mutex);
+	_rtw_init_listhead(&rfctl->reg_exc_list);
+	_rtw_init_listhead(&rfctl->txpwr_lmt_list);
+#endif
+
+	rfctl->ch_sel_same_band_prefer = 1;
+
+#ifdef CONFIG_DFS_MASTER
+	rfctl->cac_start_time = rfctl->cac_end_time = RTW_CAC_STOPPED;
+	rtw_init_timer(&(rfctl->radar_detect_timer), adapter, rtw_dfs_rd_timer_hdl, rfctl);
+#endif
+#ifdef CONFIG_DFS_SLAVE_WITH_RADAR_DETECT
+	rfctl->dfs_slave_with_rd = 1;
+#endif
+}
+
+void rtw_rfctl_deinit(_adapter *adapter)
+{
+	struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter);
+
+	_rtw_mutex_free(&rfctl->offch_mutex);
+
+#ifdef CONFIG_TXPWR_LIMIT
+	rtw_regd_exc_list_free(rfctl);
+	rtw_txpwr_lmt_list_free(rfctl);
+	_rtw_mutex_free(&rfctl->txpwr_lmt_mutex);
+#endif
+}
+
+#ifdef CONFIG_DFS_MASTER
+/*
+* called in rtw_dfs_rd_enable()
+* assume the request channel coverage is DFS range
+* base on the current status and the request channel coverage to check if need to reset complete CAC time
+*/
+bool rtw_is_cac_reset_needed(struct rf_ctl_t *rfctl, u8 ch, u8 bw, u8 offset)
+{
+	bool needed = _FALSE;
+	u32 cur_hi, cur_lo, hi, lo;
+
+	if (rfctl->radar_detected == 1) {
+		needed = _TRUE;
+		goto exit;
+	}
+
+	if (rfctl->radar_detect_ch == 0) {
+		needed = _TRUE;
+		goto exit;
+	}
+
+	if (rtw_chbw_to_freq_range(ch, bw, offset, &hi, &lo) == _FALSE) {
+		RTW_ERR("request detection range ch:%u, bw:%u, offset:%u\n", ch, bw, offset);
+		rtw_warn_on(1);
+	}
+
+	if (rtw_chbw_to_freq_range(rfctl->radar_detect_ch, rfctl->radar_detect_bw, rfctl->radar_detect_offset, &cur_hi, &cur_lo) == _FALSE) {
+		RTW_ERR("cur detection range ch:%u, bw:%u, offset:%u\n", rfctl->radar_detect_ch, rfctl->radar_detect_bw, rfctl->radar_detect_offset);
+		rtw_warn_on(1);
+	}
+
+	if (hi <= lo || cur_hi <= cur_lo) {
+		RTW_ERR("hi:%u, lo:%u, cur_hi:%u, cur_lo:%u\n", hi, lo, cur_hi, cur_lo);
+		rtw_warn_on(1);
+	}
+
+	if (rtw_is_range_a_in_b(hi, lo, cur_hi, cur_lo)) {
+		/* request is in current detect range */
+		goto exit;
+	}
+
+	/* check if request channel coverage has new range and the new range is in DFS range */
+	if (!rtw_is_range_overlap(hi, lo, cur_hi, cur_lo)) {
+		/* request has no overlap with current */
+		needed = _TRUE;
+	} else if (rtw_is_range_a_in_b(cur_hi, cur_lo, hi, lo)) {
+		/* request is supper set of current */
+		if ((hi != cur_hi && rtw_is_dfs_range(hi, cur_hi)) || (lo != cur_lo && rtw_is_dfs_range(cur_lo, lo)))
+			needed = _TRUE;
+	} else {
+		/* request is not supper set of current, but has overlap */
+		if ((lo < cur_lo && rtw_is_dfs_range(cur_lo, lo)) || (hi > cur_hi && rtw_is_dfs_range(hi, cur_hi)))
+			needed = _TRUE;
+	}
+
+exit:
+	return needed;
+}
+
+bool _rtw_rfctl_overlap_radar_detect_ch(struct rf_ctl_t *rfctl, u8 ch, u8 bw, u8 offset)
+{
+	bool ret = _FALSE;
+	u32 hi = 0, lo = 0;
+	u32 r_hi = 0, r_lo = 0;
+	int i;
+
+	if (rfctl->radar_detect_by_others)
+		goto exit;
+
+	if (rfctl->radar_detect_ch == 0)
+		goto exit;
+
+	if (rtw_chbw_to_freq_range(ch, bw, offset, &hi, &lo) == _FALSE) {
+		rtw_warn_on(1);
+		goto exit;
+	}
+
+	if (rtw_chbw_to_freq_range(rfctl->radar_detect_ch
+			, rfctl->radar_detect_bw, rfctl->radar_detect_offset
+			, &r_hi, &r_lo) == _FALSE) {
+		rtw_warn_on(1);
+		goto exit;
+	}
+
+	if (rtw_is_range_overlap(hi, lo, r_hi, r_lo))
+		ret = _TRUE;
+
+exit:
+	return ret;
+}
+
+bool rtw_rfctl_overlap_radar_detect_ch(struct rf_ctl_t *rfctl)
+{
+	return _rtw_rfctl_overlap_radar_detect_ch(rfctl
+				, rfctl_to_dvobj(rfctl)->oper_channel
+				, rfctl_to_dvobj(rfctl)->oper_bwmode
+				, rfctl_to_dvobj(rfctl)->oper_ch_offset);
+}
+
+bool rtw_rfctl_is_tx_blocked_by_ch_waiting(struct rf_ctl_t *rfctl)
+{
+	return rtw_rfctl_overlap_radar_detect_ch(rfctl) && IS_CH_WAITING(rfctl);
+}
+
+bool rtw_chset_is_chbw_non_ocp(RT_CHANNEL_INFO *ch_set, u8 ch, u8 bw, u8 offset)
+{
+	bool ret = _FALSE;
+	u32 hi = 0, lo = 0;
+	int i;
+
+	if (rtw_chbw_to_freq_range(ch, bw, offset, &hi, &lo) == _FALSE)
+		goto exit;
+
+	for (i = 0; i < MAX_CHANNEL_NUM && ch_set[i].ChannelNum != 0; i++) {
+		if (!rtw_ch2freq(ch_set[i].ChannelNum)) {
+			rtw_warn_on(1);
+			continue;
+		}
+
+		if (!CH_IS_NON_OCP(&ch_set[i]))
+			continue;
+
+		if (lo <= rtw_ch2freq(ch_set[i].ChannelNum)
+			&& rtw_ch2freq(ch_set[i].ChannelNum) <= hi
+		) {
+			ret = _TRUE;
+			break;
+		}
+	}
+
+exit:
+	return ret;
+}
+
+bool rtw_chset_is_ch_non_ocp(RT_CHANNEL_INFO *ch_set, u8 ch)
+{
+	return rtw_chset_is_chbw_non_ocp(ch_set, ch, CHANNEL_WIDTH_20, HAL_PRIME_CHNL_OFFSET_DONT_CARE);
+}
+
+u32 rtw_chset_get_ch_non_ocp_ms(RT_CHANNEL_INFO *ch_set, u8 ch, u8 bw, u8 offset)
+{
+	int ms = 0;
+	systime current_time;
+	u32 hi = 0, lo = 0;
+	int i;
+
+	if (rtw_chbw_to_freq_range(ch, bw, offset, &hi, &lo) == _FALSE)
+		goto exit;
+
+	current_time = rtw_get_current_time();
+
+	for (i = 0; i < MAX_CHANNEL_NUM && ch_set[i].ChannelNum != 0; i++) {
+		if (!rtw_ch2freq(ch_set[i].ChannelNum)) {
+			rtw_warn_on(1);
+			continue;
+		}
+
+		if (!CH_IS_NON_OCP(&ch_set[i]))
+			continue;
+
+		if (lo <= rtw_ch2freq(ch_set[i].ChannelNum)
+			&& rtw_ch2freq(ch_set[i].ChannelNum) <= hi
+		) {
+			if (rtw_systime_to_ms(ch_set[i].non_ocp_end_time - current_time) > ms)
+				ms = rtw_systime_to_ms(ch_set[i].non_ocp_end_time - current_time);
+		}
+	}
+
+exit:
+	return ms;
+}
+
+/**
+ * rtw_chset_update_non_ocp - update non_ocp_end_time according to the given @ch, @bw, @offset into @ch_set
+ * @ch_set: the given channel set
+ * @ch: channel number on which radar is detected
+ * @bw: bandwidth on which radar is detected
+ * @offset: bandwidth offset on which radar is detected
+ * @ms: ms to add from now to update non_ocp_end_time, ms < 0 means use NON_OCP_TIME_MS
+ */
+static void _rtw_chset_update_non_ocp(RT_CHANNEL_INFO *ch_set, u8 ch, u8 bw, u8 offset, int ms)
+{
+	u32 hi = 0, lo = 0;
+	int i;
+
+	if (rtw_chbw_to_freq_range(ch, bw, offset, &hi, &lo) == _FALSE)
+		goto exit;
+
+	for (i = 0; i < MAX_CHANNEL_NUM && ch_set[i].ChannelNum != 0; i++) {
+		if (!rtw_ch2freq(ch_set[i].ChannelNum)) {
+			rtw_warn_on(1);
+			continue;
+		}
+
+		if (lo <= rtw_ch2freq(ch_set[i].ChannelNum)
+			&& rtw_ch2freq(ch_set[i].ChannelNum) <= hi
+		) {
+			if (ms >= 0)
+				ch_set[i].non_ocp_end_time = rtw_get_current_time() + rtw_ms_to_systime(ms);
+			else
+				ch_set[i].non_ocp_end_time = rtw_get_current_time() + rtw_ms_to_systime(NON_OCP_TIME_MS);
+		}
+	}
+
+exit:
+	return;
+}
+
+inline void rtw_chset_update_non_ocp(RT_CHANNEL_INFO *ch_set, u8 ch, u8 bw, u8 offset)
+{
+	_rtw_chset_update_non_ocp(ch_set, ch, bw, offset, -1);
+}
+
+inline void rtw_chset_update_non_ocp_ms(RT_CHANNEL_INFO *ch_set, u8 ch, u8 bw, u8 offset, int ms)
+{
+	_rtw_chset_update_non_ocp(ch_set, ch, bw, offset, ms);
+}
+
+u32 rtw_get_ch_waiting_ms(struct rf_ctl_t *rfctl, u8 ch, u8 bw, u8 offset, u32 *r_non_ocp_ms, u32 *r_cac_ms)
+{
+	struct dvobj_priv *dvobj = rfctl_to_dvobj(rfctl);
+	u32 non_ocp_ms;
+	u32 cac_ms;
+	u8 in_rd_range = 0; /* if in current radar detection range*/
+
+	if (rtw_chset_is_chbw_non_ocp(rfctl->channel_set, ch, bw, offset))
+		non_ocp_ms = rtw_chset_get_ch_non_ocp_ms(rfctl->channel_set, ch, bw, offset);
+	else
+		non_ocp_ms = 0;
+
+	if (rfctl->radar_detect_enabled) {
+		u32 cur_hi, cur_lo, hi, lo;
+
+		if (rtw_chbw_to_freq_range(ch, bw, offset, &hi, &lo) == _FALSE) {
+			RTW_ERR("input range ch:%u, bw:%u, offset:%u\n", ch, bw, offset);
+			rtw_warn_on(1);
+		}
+
+		if (rtw_chbw_to_freq_range(rfctl->radar_detect_ch, rfctl->radar_detect_bw, rfctl->radar_detect_offset, &cur_hi, &cur_lo) == _FALSE) {
+			RTW_ERR("cur detection range ch:%u, bw:%u, offset:%u\n", rfctl->radar_detect_ch, rfctl->radar_detect_bw, rfctl->radar_detect_offset);
+			rtw_warn_on(1);
+		}
+
+		if (rtw_is_range_a_in_b(hi, lo, cur_hi, cur_lo))
+			in_rd_range = 1;
+	}
+
+	if (!rtw_is_dfs_chbw(ch, bw, offset))
+		cac_ms = 0;
+	else if (in_rd_range && !non_ocp_ms) {
+		if (IS_CH_WAITING(rfctl))
+			cac_ms = rtw_systime_to_ms(rfctl->cac_end_time - rtw_get_current_time());
+		else
+			cac_ms = 0;
+	} else if (rtw_is_long_cac_ch(ch, bw, offset, rtw_odm_get_dfs_domain(dvobj)))
+		cac_ms = CAC_TIME_CE_MS;
+	else
+		cac_ms = CAC_TIME_MS;
+
+	if (r_non_ocp_ms)
+		*r_non_ocp_ms = non_ocp_ms;
+	if (r_cac_ms)
+		*r_cac_ms = cac_ms;
+
+	return non_ocp_ms + cac_ms;
+}
+
+void rtw_reset_cac(struct rf_ctl_t *rfctl, u8 ch, u8 bw, u8 offset)
+{
+	u32 non_ocp_ms;
+	u32 cac_ms;
+
+	rtw_get_ch_waiting_ms(rfctl
+		, ch
+		, bw
+		, offset
+		, &non_ocp_ms
+		, &cac_ms
+	);
+
+	rfctl->cac_start_time = rtw_get_current_time() + rtw_ms_to_systime(non_ocp_ms);
+	rfctl->cac_end_time = rfctl->cac_start_time + rtw_ms_to_systime(cac_ms);
+
+	/* skip special value */
+	if (rfctl->cac_start_time == RTW_CAC_STOPPED) {
+		rfctl->cac_start_time++;
+		rfctl->cac_end_time++;
+	}
+	if (rfctl->cac_end_time == RTW_CAC_STOPPED)
+		rfctl->cac_end_time++;
+}
+
+u32 rtw_force_stop_cac(struct rf_ctl_t *rfctl, u32 timeout_ms)
+{
+	struct dvobj_priv *dvobj = rfctl_to_dvobj(rfctl);
+	systime start;
+	u32 pass_ms;
+
+	start = rtw_get_current_time();
+
+	rfctl->cac_force_stop = 1;
+
+	while (rtw_get_passing_time_ms(start) <= timeout_ms
+		&& IS_UNDER_CAC(rfctl)
+	) {
+		if (dev_is_surprise_removed(dvobj) || dev_is_drv_stopped(dvobj))
+			break;
+		rtw_msleep_os(20);
+	}
+
+	if (IS_UNDER_CAC(rfctl)) {
+		if (!dev_is_surprise_removed(dvobj) && !dev_is_drv_stopped(dvobj))
+			RTW_INFO("%s waiting for cac stop timeout!\n", __func__);
+	}
+
+	rfctl->cac_force_stop = 0;
+
+	pass_ms = rtw_get_passing_time_ms(start);
+
+	return pass_ms;
+}
+#endif /* CONFIG_DFS_MASTER */
+
+/* choose channel with shortest waiting (non ocp + cac) time */
+bool rtw_choose_shortest_waiting_ch(struct rf_ctl_t *rfctl, u8 sel_ch, u8 max_bw
+	, u8 *dec_ch, u8 *dec_bw, u8 *dec_offset
+	, u8 d_flags, u8 cur_ch, u8 same_band_prefer, u8 mesh_only)
+{
+#ifndef DBG_CHOOSE_SHORTEST_WAITING_CH
+#define DBG_CHOOSE_SHORTEST_WAITING_CH 0
+#endif
+	struct dvobj_priv *dvobj = rfctl_to_dvobj(rfctl);
+	struct registry_priv *regsty = dvobj_to_regsty(dvobj);
+	u8 ch, bw, offset;
+	u8 ch_c = 0, bw_c = 0, offset_c = 0;
+	int i;
+	u32 min_waiting_ms = 0;
+
+	if (!dec_ch || !dec_bw || !dec_offset) {
+		rtw_warn_on(1);
+		return _FALSE;
+	}
+
+	/* full search and narrow bw judegement first to avoid potetial judegement timing issue */
+	for (bw = CHANNEL_WIDTH_20; bw <= max_bw; bw++) {
+		if (!hal_is_bw_support(dvobj_get_primary_adapter(dvobj), bw))
+			continue;
+
+		for (i = 0; i < rfctl->max_chan_nums; i++) {
+			u32 non_ocp_ms = 0;
+			u32 cac_ms = 0;
+			u32 waiting_ms = 0;
+
+			ch = rfctl->channel_set[i].ChannelNum;
+			if (sel_ch > 0 && ch != sel_ch)
+				continue;
+
+			if ((d_flags & RTW_CHF_2G) && ch <= 14)
+				continue;
+
+			if ((d_flags & RTW_CHF_5G) && ch > 14)
+				continue;
+
+			if (ch > 14) {
+				if (bw > REGSTY_BW_5G(regsty))
+					continue;
+			} else {
+				if (bw > REGSTY_BW_2G(regsty))
+					continue;
+			}
+
+			if (mesh_only && ch >= 5 && ch <= 9 && bw > CHANNEL_WIDTH_20)
+				continue;
+
+			if (!rtw_get_offset_by_chbw(ch, bw, &offset))
+				continue;
+
+			if (!rtw_chset_is_chbw_valid(rfctl->channel_set, ch, bw, offset))
+				continue;
+
+			if ((d_flags & RTW_CHF_NON_OCP) && rtw_chset_is_chbw_non_ocp(rfctl->channel_set, ch, bw, offset))
+				continue;
+
+			if ((d_flags & RTW_CHF_DFS) && rtw_is_dfs_chbw(ch, bw, offset))
+				continue;
+
+			if ((d_flags & RTW_CHF_LONG_CAC) && rtw_is_long_cac_ch(ch, bw, offset, rtw_odm_get_dfs_domain(dvobj)))
+				continue;
+
+			if ((d_flags & RTW_CHF_NON_DFS) && !rtw_is_dfs_chbw(ch, bw, offset))
+				continue;
+
+			if ((d_flags & RTW_CHF_NON_LONG_CAC) && !rtw_is_long_cac_ch(ch, bw, offset, rtw_odm_get_dfs_domain(dvobj)))
+				continue;
+
+			#ifdef CONFIG_DFS_MASTER
+			waiting_ms = rtw_get_ch_waiting_ms(rfctl, ch, bw, offset, &non_ocp_ms, &cac_ms);
+			#endif
+
+			if (DBG_CHOOSE_SHORTEST_WAITING_CH)
+				RTW_INFO("%s:%u,%u,%u %u(non_ocp:%u, cac:%u)\n"
+					, __func__, ch, bw, offset, waiting_ms, non_ocp_ms, cac_ms);
+
+			if (ch_c == 0
+				/* first: smaller wating time */
+				|| min_waiting_ms > waiting_ms
+				/* then: wider bw */
+				|| (min_waiting_ms == waiting_ms && bw > bw_c)
+				/* then: same band if requested */
+				|| (same_band_prefer && min_waiting_ms == waiting_ms && bw == bw_c
+					&& !rtw_is_same_band(cur_ch, ch_c) && rtw_is_same_band(cur_ch, ch))
+			) {
+				ch_c = ch;
+				bw_c = bw;
+				offset_c = offset;
+				min_waiting_ms = waiting_ms;
+			}
+		}
+	}
+
+	if (ch_c != 0) {
+		RTW_INFO("%s: d_flags:0x%02x cur_ch:%u sb_prefer:%u%s %u,%u,%u waiting_ms:%u\n"
+			, __func__, d_flags, cur_ch, same_band_prefer
+			, mesh_only ? " mesh_only" : ""
+			, ch_c, bw_c, offset_c, min_waiting_ms);
+
+		*dec_ch = ch_c;
+		*dec_bw = bw_c;
+		*dec_offset = offset_c;
+		return _TRUE;
+	}
+
+	if (d_flags == 0) {
+		RTW_INFO("%s: sel_ch:%u max_bw:%u d_flags:0x%02x cur_ch:%u sb_prefer:%u%s\n"
+			, __func__, sel_ch, max_bw, d_flags, cur_ch, same_band_prefer
+			, mesh_only ? " mesh_only" : "");
+		rtw_warn_on(1);
+	}
+
+	return _FALSE;
+}
+
+void dump_chset(void *sel, RT_CHANNEL_INFO *ch_set)
+{
+	u8	i;
+
+	for (i = 0; i < MAX_CHANNEL_NUM && ch_set[i].ChannelNum != 0; i++) {
+		RTW_PRINT_SEL(sel, "ch:%3u, freq:%u, scan_type:%d"
+			, ch_set[i].ChannelNum, rtw_ch2freq(ch_set[i].ChannelNum), ch_set[i].ScanType);
+
+#ifdef CONFIG_FIND_BEST_CHANNEL
+		_RTW_PRINT_SEL(sel, ", rx_count:%u", ch_set[i].rx_count);
+#endif
+
+#ifdef CONFIG_DFS_MASTER
+		if (rtw_is_dfs_ch(ch_set[i].ChannelNum)) {
+			if (CH_IS_NON_OCP(&ch_set[i]))
+				_RTW_PRINT_SEL(sel, ", non_ocp:%d"
+					, rtw_systime_to_ms(ch_set[i].non_ocp_end_time - rtw_get_current_time()));
+			else
+				_RTW_PRINT_SEL(sel, ", non_ocp:N/A");
+		}
+#endif
+
+		_RTW_PRINT_SEL(sel, "\n");
+	}
+
+	RTW_PRINT_SEL(sel, "total ch number:%d\n", i);
+}
+
+void dump_cur_chset(void *sel, struct rf_ctl_t *rfctl)
+{
+	struct dvobj_priv *dvobj = rfctl_to_dvobj(rfctl);
+	struct registry_priv *regsty = dvobj_to_regsty(dvobj);
+	int i;
+
+	if (rfctl->country_ent)
+		dump_country_chplan(sel, rfctl->country_ent);
+	else
+		RTW_PRINT_SEL(sel, "chplan:0x%02X\n", rfctl->ChannelPlan);
+
+#ifdef CONFIG_TXPWR_LIMIT
+	RTW_PRINT_SEL(sel, "PLS regd:%s\n", rfctl->regd_name);
+#endif
+
+#ifdef CONFIG_DFS_MASTER
+	RTW_PRINT_SEL(sel, "dfs_domain:%u\n", rtw_odm_get_dfs_domain(dvobj));
+#endif
+
+	for (i = 0; i < MAX_CHANNEL_NUM; i++)
+		if (regsty->excl_chs[i] != 0)
+			break;
+
+	if (i < MAX_CHANNEL_NUM) {
+		RTW_PRINT_SEL(sel, "excl_chs:");
+		for (i = 0; i < MAX_CHANNEL_NUM; i++) {
+			if (regsty->excl_chs[i] == 0)
+				break;
+			_RTW_PRINT_SEL(sel, "%u ", regsty->excl_chs[i]);
+		}
+		_RTW_PRINT_SEL(sel, "\n");
+	}
+
+	dump_chset(sel, rfctl->channel_set);
+}
+
+/*
+ * Search the @param ch in given @param ch_set
+ * @ch_set: the given channel set
+ * @ch: the given channel number
+ *
+ * return the index of channel_num in channel_set, -1 if not found
+ */
+int rtw_chset_search_ch(RT_CHANNEL_INFO *ch_set, const u32 ch)
+{
+	int i;
+
+	if (ch == 0)
+		return -1;
+
+	for (i = 0; i < MAX_CHANNEL_NUM && ch_set[i].ChannelNum != 0; i++) {
+		if (ch == ch_set[i].ChannelNum)
+			return i;
+	}
+
+	return -1;
+}
+
+/*
+ * Check if the @param ch, bw, offset is valid for the given @param ch_set
+ * @ch_set: the given channel set
+ * @ch: the given channel number
+ * @bw: the given bandwidth
+ * @offset: the given channel offset
+ *
+ * return valid (1) or not (0)
+ */
+u8 rtw_chset_is_chbw_valid(RT_CHANNEL_INFO *ch_set, u8 ch, u8 bw, u8 offset)
+{
+	u8 cch;
+	u8 *op_chs;
+	u8 op_ch_num;
+	u8 valid = 0;
+	int i;
+
+	cch = rtw_get_center_ch(ch, bw, offset);
+
+	if (!rtw_get_op_chs_by_cch_bw(cch, bw, &op_chs, &op_ch_num))
+		goto exit;
+
+	for (i = 0; i < op_ch_num; i++) {
+		if (0)
+			RTW_INFO("%u,%u,%u - cch:%u, bw:%u, op_ch:%u\n", ch, bw, offset, cch, bw, *(op_chs + i));
+		if (rtw_chset_search_ch(ch_set, *(op_chs + i)) == -1)
+			break;
+	}
+
+	if (op_ch_num != 0 && i == op_ch_num)
+		valid = 1;
+
+exit:
+	return valid;
+}
+
+/**
+ * rtw_chset_sync_chbw - obey g_ch, adjust g_bw, g_offset, bw, offset to fit in channel plan
+ * @ch_set: channel plan to check
+ * @req_ch: pointer of the request ch, may be modified further
+ * @req_bw: pointer of the request bw, may be modified further
+ * @req_offset: pointer of the request offset, may be modified further
+ * @g_ch: pointer of the ongoing group ch
+ * @g_bw: pointer of the ongoing group bw, may be modified further
+ * @g_offset: pointer of the ongoing group offset, may be modified further
+ */
+void rtw_chset_sync_chbw(RT_CHANNEL_INFO *ch_set, u8 *req_ch, u8 *req_bw, u8 *req_offset
+	, u8 *g_ch, u8 *g_bw, u8 *g_offset)
+{
+	u8 r_ch, r_bw, r_offset;
+	u8 u_ch, u_bw, u_offset;
+	u8 cur_bw = *req_bw;
+
+	while (1) {
+		r_ch = *req_ch;
+		r_bw = cur_bw;
+		r_offset = *req_offset;
+		u_ch = *g_ch;
+		u_bw = *g_bw;
+		u_offset = *g_offset;
+
+		rtw_sync_chbw(&r_ch, &r_bw, &r_offset, &u_ch, &u_bw, &u_offset);
+
+		if (rtw_chset_is_chbw_valid(ch_set, r_ch, r_bw, r_offset))
+			break;
+		if (cur_bw == CHANNEL_WIDTH_20) {
+			rtw_warn_on(1);
+			break;
+		}
+		cur_bw--;
+	};
+
+	*req_ch = r_ch;
+	*req_bw = r_bw;
+	*req_offset = r_offset;
+	*g_ch = u_ch;
+	*g_bw = u_bw;
+	*g_offset = u_offset;
+}
+
+/*
+ * Check the @param ch is fit with setband setting of @param adapter
+ * @adapter: the given adapter
+ * @ch: the given channel number
+ *
+ * return _TRUE when check valid, _FALSE not valid
+ */
+bool rtw_mlme_band_check(_adapter *adapter, const u32 ch)
+{
+	if (adapter->setband == WIFI_FREQUENCY_BAND_AUTO /* 2.4G and 5G */
+		|| (adapter->setband == WIFI_FREQUENCY_BAND_2GHZ && ch < 35) /* 2.4G only */
+		|| (adapter->setband == WIFI_FREQUENCY_BAND_5GHZ && ch > 35) /* 5G only */
+	)
+		return _TRUE;
+	return _FALSE;
+}
+inline void RTW_SET_SCAN_BAND_SKIP(_adapter *padapter, int skip_band)
+{
+	int bs = ATOMIC_READ(&padapter->bandskip);
+
+	bs |= skip_band;
+	ATOMIC_SET(&padapter->bandskip, bs);
+}
+
+inline void RTW_CLR_SCAN_BAND_SKIP(_adapter *padapter, int skip_band)
+{
+	int bs = ATOMIC_READ(&padapter->bandskip);
+
+	bs &= ~(skip_band);
+	ATOMIC_SET(&padapter->bandskip, bs);
+}
+inline int RTW_GET_SCAN_BAND_SKIP(_adapter *padapter)
+{
+	return ATOMIC_READ(&padapter->bandskip);
+}
+
+#define RTW_IS_SCAN_BAND_SKIP(padapter, skip_band) (ATOMIC_READ(&padapter->bandskip) & (skip_band))
+
+bool rtw_mlme_ignore_chan(_adapter *adapter, const u32 ch)
+{
+	if (RTW_IS_SCAN_BAND_SKIP(adapter, BAND_24G) && ch < 35) /* SKIP 2.4G Band channel */
+		return _TRUE;
+	if (RTW_IS_SCAN_BAND_SKIP(adapter, BAND_5G)  && ch > 35) /* SKIP 5G Band channel */
+		return _TRUE;
+
+	return _FALSE;
+}
+
+
+/****************************************************************************
+
+Following are the initialization functions for WiFi MLME
+
+*****************************************************************************/
+
+int init_hw_mlme_ext(_adapter *padapter)
+{
+	struct	mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
+	HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
+	u8 rx_bar_enble = _TRUE;
+
+	/*
+	 * Sync driver status and hardware setting
+	 */
+
+	/* Modify to make sure first time change channel(band) would be done properly */
+	pHalData->current_channel = 0;
+	pHalData->current_channel_bw = CHANNEL_WIDTH_MAX;
+	pHalData->current_band_type = BAND_MAX;
+
+	/* set_opmode_cmd(padapter, infra_client_with_mlme); */ /* removed */
+	rtw_hal_set_hwreg(padapter, HW_VAR_ENABLE_RX_BAR, &rx_bar_enble);
+	set_channel_bwmode(padapter, pmlmeext->cur_channel, pmlmeext->cur_ch_offset, pmlmeext->cur_bwmode);
+
+	return _SUCCESS;
+}
+
+void init_mlme_default_rate_set(_adapter *padapter)
+{
+	struct	mlme_ext_priv	*pmlmeext = &padapter->mlmeextpriv;
+	unsigned	char end_set[1] = {0xff};
+	u8	offset_datarate = 0;
+	u8	offset_basicrate = 0;
+#ifdef CONFIG_80211N_HT
+	unsigned char	supported_mcs_set[16] = {0xff, 0xff, 0xff, 0x00, 0x00, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0};
+#endif
+
+	if (IsSupportedTxCCK(padapter->registrypriv.wireless_mode)) {
+
+		unsigned char	datarate_b[B_MODE_RATE_NUM] ={_1M_RATE_, _2M_RATE_, _5M_RATE_, _11M_RATE_};
+		_rtw_memcpy(pmlmeext->datarate, datarate_b, B_MODE_RATE_NUM);
+		_rtw_memcpy(pmlmeext->basicrate, datarate_b, B_MODE_RATE_NUM);
+		offset_datarate += B_MODE_RATE_NUM;
+		offset_basicrate += B_MODE_RATE_NUM;
+		RTW_INFO("%s: support CCK\n", __func__);
+	}
+	if(IsSupportedTxOFDM(padapter->registrypriv.wireless_mode)) {
+		unsigned char	datarate_g[G_MODE_RATE_NUM] ={_6M_RATE_, _9M_RATE_, _12M_RATE_, _18M_RATE_,_24M_RATE_, _36M_RATE_, _48M_RATE_, _54M_RATE_};
+		unsigned char	basicrate_g[G_MODE_BASIC_RATE_NUM] = {_6M_RATE_, _12M_RATE_, _24M_RATE_};
+		_rtw_memcpy(pmlmeext->datarate + offset_datarate, datarate_g, G_MODE_RATE_NUM);
+		_rtw_memcpy(pmlmeext->basicrate + offset_basicrate,basicrate_g, G_MODE_BASIC_RATE_NUM);
+		offset_datarate += G_MODE_RATE_NUM;
+		offset_basicrate += G_MODE_BASIC_RATE_NUM;
+		RTW_INFO("%s: support OFDM\n", __func__);
+
+	}
+	_rtw_memcpy(pmlmeext->datarate + offset_datarate, end_set, 1);
+	_rtw_memcpy(pmlmeext->basicrate + offset_basicrate, end_set, 1);
+
+#ifdef CONFIG_80211N_HT
+	if( padapter->registrypriv.ht_enable && is_supported_ht(padapter->registrypriv.wireless_mode))
+		_rtw_memcpy(pmlmeext->default_supported_mcs_set, supported_mcs_set, sizeof(pmlmeext->default_supported_mcs_set));
+#endif
+}
+
+static void init_mlme_ext_priv_value(_adapter *padapter)
+{
+	struct mlme_ext_priv	*pmlmeext = &padapter->mlmeextpriv;
+	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
+
+	ATOMIC_SET(&pmlmeext->event_seq, 0);
+	pmlmeext->mgnt_seq = 0;/* reset to zero when disconnect at client mode */
+#ifdef CONFIG_IEEE80211W
+	pmlmeext->sa_query_seq = 0;
+#endif
+	pmlmeext->cur_channel = padapter->registrypriv.channel;
+	pmlmeext->cur_bwmode = CHANNEL_WIDTH_20;
+	pmlmeext->cur_ch_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
+
+	pmlmeext->retry = 0;
+
+	pmlmeext->cur_wireless_mode = padapter->registrypriv.wireless_mode;
+	init_mlme_default_rate_set(padapter);
+
+	if (pmlmeext->cur_channel > 14)
+		pmlmeext->tx_rate = IEEE80211_OFDM_RATE_6MB;
+	else
+		pmlmeext->tx_rate = IEEE80211_CCK_RATE_1MB;
+
+	mlmeext_set_scan_state(pmlmeext, SCAN_DISABLE);
+	pmlmeext->sitesurvey_res.channel_idx = 0;
+	pmlmeext->sitesurvey_res.bss_cnt = 0;
+	pmlmeext->sitesurvey_res.scan_ch_ms = SURVEY_TO;
+	pmlmeext->sitesurvey_res.rx_ampdu_accept = RX_AMPDU_ACCEPT_INVALID;
+	pmlmeext->sitesurvey_res.rx_ampdu_size = RX_AMPDU_SIZE_INVALID;
+#ifdef CONFIG_SCAN_BACKOP
+	mlmeext_assign_scan_backop_flags_sta(pmlmeext, /*SS_BACKOP_EN|*/SS_BACKOP_PS_ANNC | SS_BACKOP_TX_RESUME);
+	#ifdef CONFIG_AP_MODE
+	mlmeext_assign_scan_backop_flags_ap(pmlmeext, SS_BACKOP_EN | SS_BACKOP_PS_ANNC | SS_BACKOP_TX_RESUME);
+	#endif
+	#ifdef CONFIG_RTW_MESH
+	mlmeext_assign_scan_backop_flags_mesh(pmlmeext, /*SS_BACKOP_EN | */SS_BACKOP_PS_ANNC | SS_BACKOP_TX_RESUME);
+	#endif
+	pmlmeext->sitesurvey_res.scan_cnt = 0;
+	pmlmeext->sitesurvey_res.scan_cnt_max = RTW_SCAN_NUM_OF_CH;
+	pmlmeext->sitesurvey_res.backop_ms = RTW_BACK_OP_CH_MS;
+#endif
+#if defined(CONFIG_ANTENNA_DIVERSITY) || defined(DBG_SCAN_SW_ANTDIV_BL)
+	pmlmeext->sitesurvey_res.is_sw_antdiv_bl_scan = 0;
+#endif
+	pmlmeext->scan_abort = _FALSE;
+
+	pmlmeinfo->state = WIFI_FW_NULL_STATE;
+	pmlmeinfo->reauth_count = 0;
+	pmlmeinfo->reassoc_count = 0;
+	pmlmeinfo->link_count = 0;
+	pmlmeinfo->auth_seq = 0;
+	pmlmeinfo->auth_algo = dot11AuthAlgrthm_Open;
+	pmlmeinfo->key_index = 0;
+	pmlmeinfo->iv = 0;
+
+	pmlmeinfo->enc_algo = _NO_PRIVACY_;
+	pmlmeinfo->authModeToggle = 0;
+
+	_rtw_memset(pmlmeinfo->chg_txt, 0, 128);
+
+	pmlmeinfo->slotTime = SHORT_SLOT_TIME;
+	pmlmeinfo->preamble_mode = PREAMBLE_AUTO;
+
+	pmlmeinfo->dialogToken = 0;
+
+	pmlmeext->action_public_rxseq = 0xffff;
+	pmlmeext->action_public_dialog_token = 0xff;
+#ifdef ROKU_PRIVATE
+/*infra mode, used to store AP's info*/
+	_rtw_memset(pmlmeinfo->SupportedRates_infra_ap, 0, NDIS_802_11_LENGTH_RATES_EX);
+	pmlmeinfo->ht_vht_received = 0;
+#endif /* ROKU_PRIVATE */
+}
+
+void init_mlme_ext_timer(_adapter *padapter)
+{
+	struct	mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
+
+	rtw_init_timer(&pmlmeext->survey_timer, padapter, survey_timer_hdl, padapter);
+	rtw_init_timer(&pmlmeext->link_timer, padapter, link_timer_hdl, padapter);
+#ifdef CONFIG_RTW_80211R
+	rtw_init_timer(&pmlmeext->ft_link_timer, padapter, rtw_ft_link_timer_hdl, padapter);
+	rtw_init_timer(&pmlmeext->ft_roam_timer, padapter, rtw_ft_roam_timer_hdl, padapter);
+#endif
+
+#ifdef CONFIG_RTW_REPEATER_SON
+	rtw_init_timer(&pmlmeext->rson_scan_timer, padapter, rson_timer_hdl, padapter);
+#endif
+}
+
+int	init_mlme_ext_priv(_adapter *padapter)
+{
+	int	res = _SUCCESS;
+	struct registry_priv *pregistrypriv = &padapter->registrypriv;
+	struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
+	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
+
+	/* We don't need to memset padapter->XXX to zero, because adapter is allocated by rtw_zvmalloc(). */
+	/* _rtw_memset((u8 *)pmlmeext, 0, sizeof(struct mlme_ext_priv)); */
+
+	pmlmeext->padapter = padapter;
+
+	/* fill_fwpriv(padapter, &(pmlmeext->fwpriv)); */
+
+	init_mlme_ext_priv_value(padapter);
+	pmlmeinfo->bAcceptAddbaReq = pregistrypriv->bAcceptAddbaReq;
+
+	init_mlme_ext_timer(padapter);
+
+#ifdef CONFIG_AP_MODE
+	init_mlme_ap_info(padapter);
+#endif
+
+	pmlmeext->last_scan_time = 0;
+	pmlmeext->mlmeext_init = _TRUE;
+
+
+#ifdef CONFIG_ACTIVE_KEEP_ALIVE_CHECK
+	pmlmeext->active_keep_alive_check = _TRUE;
+#else
+	pmlmeext->active_keep_alive_check = _FALSE;
+#endif
+
+#ifdef DBG_FIXED_CHAN
+	pmlmeext->fixed_chan = 0xFF;
+#endif
+
+	pmlmeext->tsf_update_pause_factor = pregistrypriv->tsf_update_pause_factor;
+	pmlmeext->tsf_update_restore_factor = pregistrypriv->tsf_update_restore_factor;
+
+	return res;
+
+}
+
+void free_mlme_ext_priv(struct mlme_ext_priv *pmlmeext)
+{
+	_adapter *padapter = pmlmeext->padapter;
+
+	if (!padapter)
+		return;
+
+	if (rtw_is_drv_stopped(padapter)) {
+		_cancel_timer_ex(&pmlmeext->survey_timer);
+		_cancel_timer_ex(&pmlmeext->link_timer);
+	}
+}
+
+#ifdef CONFIG_PATCH_JOIN_WRONG_CHANNEL
+static u8 cmp_pkt_chnl_diff(_adapter *padapter, u8 *pframe, uint packet_len)
+{
+	/* if the channel is same, return 0. else return channel differential	 */
+	uint len;
+	u8 channel;
+	u8 *p;
+
+	p = rtw_get_ie(pframe + WLAN_HDR_A3_LEN + _BEACON_IE_OFFSET_, _DSSET_IE_, &len, packet_len - _BEACON_IE_OFFSET_);
+	if (p) {
+		channel = *(p + 2);
+		if (padapter->mlmeextpriv.cur_channel >= channel)
+			return padapter->mlmeextpriv.cur_channel - channel;
+		else
+			return channel - padapter->mlmeextpriv.cur_channel;
+	} else
+		return 0;
+}
+#endif /* CONFIG_PATCH_JOIN_WRONG_CHANNEL */
+
+static void _mgt_dispatcher(_adapter *padapter, struct mlme_handler *ptable, union recv_frame *precv_frame)
+{
+	u8 bc_addr[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
+	u8 *pframe = precv_frame->u.hdr.rx_data;
+
+	if (ptable->func) {
+		/* receive the frames that ra(a1) is my address or ra(a1) is bc address. */
+		if (!_rtw_memcmp(GetAddr1Ptr(pframe), adapter_mac_addr(padapter), ETH_ALEN) &&
+		    !_rtw_memcmp(GetAddr1Ptr(pframe), bc_addr, ETH_ALEN))
+#ifdef CONFIG_RTW_CFGVENDOR_RANDOM_MAC_OUI
+		{		
+			struct rtw_wdev_priv *pwdev_priv = adapter_wdev_data(padapter);
+
+			if (check_fwstate(&padapter->mlmepriv, WIFI_STATION_STATE) != _TRUE)
+				return;
+
+		    if (check_fwstate(&padapter->mlmepriv, _FW_LINKED) == _TRUE)
+				return;
+
+		    if ( pwdev_priv->pno_mac_addr[0] == 0xFF)
+				return;
+
+		    if (!_rtw_memcmp(GetAddr1Ptr(pframe), adapter_pno_mac_addr(padapter), ETH_ALEN))
+				return;
+		}
+#else
+			return;
+#endif
+
+		ptable->func(padapter, precv_frame);
+	}
+
+}
+
+void mgt_dispatcher(_adapter *padapter, union recv_frame *precv_frame)
+{
+	int index;
+	struct mlme_handler *ptable;
+	u8 bc_addr[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
+	u8 *pframe = precv_frame->u.hdr.rx_data;
+	struct sta_info *psta = rtw_get_stainfo(&padapter->stapriv, get_addr2_ptr(pframe));
+	struct recv_priv  *precvpriv = &padapter->recvpriv;
+
+
+#if 0
+	{
+		u8 *pbuf;
+		pbuf = GetAddr1Ptr(pframe);
+		RTW_INFO("A1-%x:%x:%x:%x:%x:%x\n", *pbuf, *(pbuf + 1), *(pbuf + 2), *(pbuf + 3), *(pbuf + 4), *(pbuf + 5));
+		pbuf = get_addr2_ptr(pframe);
+		RTW_INFO("A2-%x:%x:%x:%x:%x:%x\n", *pbuf, *(pbuf + 1), *(pbuf + 2), *(pbuf + 3), *(pbuf + 4), *(pbuf + 5));
+		pbuf = GetAddr3Ptr(pframe);
+		RTW_INFO("A3-%x:%x:%x:%x:%x:%x\n", *pbuf, *(pbuf + 1), *(pbuf + 2), *(pbuf + 3), *(pbuf + 4), *(pbuf + 5));
+	}
+#endif
+
+	if (GetFrameType(pframe) != WIFI_MGT_TYPE) {
+		return;
+	}
+
+	/* receive the frames that ra(a1) is my address or ra(a1) is bc address. */
+	if (!_rtw_memcmp(GetAddr1Ptr(pframe), adapter_mac_addr(padapter), ETH_ALEN) &&
+	    !_rtw_memcmp(GetAddr1Ptr(pframe), bc_addr, ETH_ALEN))
+#ifdef CONFIG_RTW_CFGVENDOR_RANDOM_MAC_OUI
+		{		
+			struct rtw_wdev_priv *pwdev_priv = adapter_wdev_data(padapter);
+
+			if (check_fwstate(&padapter->mlmepriv, WIFI_STATION_STATE) != _TRUE)
+				return;
+
+			if (check_fwstate(&padapter->mlmepriv, _FW_LINKED) == _TRUE)
+				return;
+
+		if ( pwdev_priv->pno_mac_addr[0] == 0xFF)
+				return;
+
+			if (!_rtw_memcmp(GetAddr1Ptr(pframe), adapter_pno_mac_addr(padapter), ETH_ALEN))
+				return;
+		}
+#else
+		return;
+#endif
+
+	ptable = mlme_sta_tbl;
+
+	index = get_frame_sub_type(pframe) >> 4;
+
+#ifdef CONFIG_TDLS
+	if ((index << 4) == WIFI_ACTION) {
+		/* category==public (4), action==TDLS_DISCOVERY_RESPONSE */
+		if (*(pframe + 24) == RTW_WLAN_CATEGORY_PUBLIC && *(pframe + 25) == TDLS_DISCOVERY_RESPONSE) {
+			RTW_INFO("[TDLS] Recv %s from "MAC_FMT"\n", rtw_tdls_action_txt(TDLS_DISCOVERY_RESPONSE), MAC_ARG(get_addr2_ptr(pframe)));
+			On_TDLS_Dis_Rsp(padapter, precv_frame);
+		}
+	}
+#endif /* CONFIG_TDLS */
+
+	if (index >= (sizeof(mlme_sta_tbl) / sizeof(struct mlme_handler))) {
+		return;
+	}
+	ptable += index;
+
+#if 1
+	if (psta != NULL) {
+		if (GetRetry(pframe)) {
+			if (precv_frame->u.hdr.attrib.seq_num == psta->RxMgmtFrameSeqNum) {
+				/* drop the duplicate management frame */
+				precvpriv->dbg_rx_dup_mgt_frame_drop_count++;
+				RTW_INFO("Drop duplicate management frame with seq_num = %d.\n", precv_frame->u.hdr.attrib.seq_num);
+				return;
+			}
+		}
+		psta->RxMgmtFrameSeqNum = precv_frame->u.hdr.attrib.seq_num;
+	}
+#else
+
+	if (GetRetry(pframe)) {
+		/* return; */
+	}
+#endif
+
+#ifdef CONFIG_AP_MODE
+	switch (get_frame_sub_type(pframe)) {
+	case WIFI_AUTH:
+		if (MLME_IS_AP(padapter) || MLME_IS_MESH(padapter))
+			ptable->func = &OnAuth;
+		else
+			ptable->func = &OnAuthClient;
+		__attribute__((__fallthrough__));
+	case WIFI_ASSOCREQ:
+	case WIFI_REASSOCREQ:
+		_mgt_dispatcher(padapter, ptable, precv_frame);
+		#ifdef CONFIG_HOSTAPD_MLME
+		if (MLME_IS_AP(padapter))
+			rtw_hostapd_mlme_rx(padapter, precv_frame);
+		#endif
+		break;
+	case WIFI_PROBEREQ:
+		_mgt_dispatcher(padapter, ptable, precv_frame);
+		#ifdef CONFIG_HOSTAPD_MLME
+		if (MLME_IS_AP(padapter))
+			rtw_hostapd_mlme_rx(padapter, precv_frame);
+		#endif
+		break;
+	case WIFI_BEACON:
+		_mgt_dispatcher(padapter, ptable, precv_frame);
+		break;
+	case WIFI_ACTION:
+		_mgt_dispatcher(padapter, ptable, precv_frame);
+		break;
+	default:
+		_mgt_dispatcher(padapter, ptable, precv_frame);
+		#ifdef CONFIG_HOSTAPD_MLME
+		if (MLME_IS_AP(padapter))
+			rtw_hostapd_mlme_rx(padapter, precv_frame);
+		#endif
+		break;
+	}
+#else
+
+	_mgt_dispatcher(padapter, ptable, precv_frame);
+
+#endif
+
+}
+
+#ifdef CONFIG_P2P
+u32 p2p_listen_state_process(_adapter *padapter, unsigned char *da)
+{
+	bool response = _TRUE;
+
+#ifdef CONFIG_IOCTL_CFG80211
+	if (padapter->wdinfo.driver_interface == DRIVER_CFG80211) {
+		if (rtw_cfg80211_get_is_roch(padapter) == _FALSE
+			|| rtw_get_oper_ch(padapter) != padapter->wdinfo.listen_channel
+			|| adapter_wdev_data(padapter)->p2p_enabled == _FALSE
+			|| padapter->mlmepriv.wps_probe_resp_ie == NULL
+			|| padapter->mlmepriv.p2p_probe_resp_ie == NULL
+		) {
+#ifdef CONFIG_DEBUG_CFG80211
+			RTW_INFO(ADPT_FMT" DON'T issue_probersp_p2p: p2p_enabled:%d, wps_probe_resp_ie:%p, p2p_probe_resp_ie:%p\n"
+				, ADPT_ARG(padapter)
+				, adapter_wdev_data(padapter)->p2p_enabled
+				, padapter->mlmepriv.wps_probe_resp_ie
+				, padapter->mlmepriv.p2p_probe_resp_ie);
+			RTW_INFO(ADPT_FMT" DON'T issue_probersp_p2p: is_ro_ch:%d, op_ch:%d, p2p_listen_channel:%d\n"
+				, ADPT_ARG(padapter)
+				, rtw_cfg80211_get_is_roch(padapter)
+				, rtw_get_oper_ch(padapter)
+				, padapter->wdinfo.listen_channel);
+#endif
+			response = _FALSE;
+		}
+	} else
+#endif /* CONFIG_IOCTL_CFG80211 */
+		if (padapter->wdinfo.driver_interface == DRIVER_WEXT) {
+			/*	do nothing if the device name is empty */
+			if (!padapter->wdinfo.device_name_len)
+				response	= _FALSE;
+		}
+
+	if (response == _TRUE)
+		issue_probersp_p2p(padapter, da);
+
+	return _SUCCESS;
+}
+#endif /* CONFIG_P2P */
+
+
+/****************************************************************************
+
+Following are the callback functions for each subtype of the management frames
+
+*****************************************************************************/
+
+unsigned int OnProbeReq(_adapter *padapter, union recv_frame *precv_frame)
+{
+	unsigned int	ielen;
+	unsigned char	*p;
+	struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
+	struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
+	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
+	WLAN_BSSID_EX	*cur = &(pmlmeinfo->network);
+	u8 *pframe = precv_frame->u.hdr.rx_data;
+	uint len = precv_frame->u.hdr.len;
+	u8 is_valid_p2p_probereq = _FALSE;
+
+#ifdef CONFIG_ATMEL_RC_PATCH
+	u8 *target_ie = NULL, *wps_ie = NULL;
+	u8 *start;
+	uint search_len = 0, wps_ielen = 0, target_ielen = 0;
+	struct sta_info	*psta;
+	struct sta_priv *pstapriv = &padapter->stapriv;
+#endif
+
+
+#ifdef CONFIG_P2P
+	struct wifidirect_info	*pwdinfo = &(padapter->wdinfo);
+	struct rx_pkt_attrib	*pattrib = &precv_frame->u.hdr.attrib;
+	u8 wifi_test_chk_rate = 1;
+
+#ifdef CONFIG_IOCTL_CFG80211
+	if ((pwdinfo->driver_interface == DRIVER_CFG80211)
+	    && !rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE)
+	    && (GET_CFG80211_REPORT_MGMT(adapter_wdev_data(padapter), IEEE80211_STYPE_PROBE_REQ) == _TRUE)
+	) {
+		rtw_cfg80211_rx_probe_request(padapter, precv_frame);
+		return _SUCCESS;
+	}
+#endif /* CONFIG_IOCTL_CFG80211 */
+
+	if (!rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE) &&
+	    !rtw_p2p_chk_state(pwdinfo, P2P_STATE_IDLE) &&
+	    !rtw_p2p_chk_role(pwdinfo, P2P_ROLE_CLIENT) &&
+	    !rtw_p2p_chk_state(pwdinfo, P2P_STATE_FIND_PHASE_SEARCH) &&
+	    !rtw_p2p_chk_state(pwdinfo, P2P_STATE_SCAN)
+	   ) {
+		/*	Commented by Albert 2011/03/17 */
+		/*	mcs_rate = 0->CCK 1M rate */
+		/*	mcs_rate = 1->CCK 2M rate */
+		/*	mcs_rate = 2->CCK 5.5M rate */
+		/*	mcs_rate = 3->CCK 11M rate */
+		/*	In the P2P mode, the driver should not support the CCK rate */
+
+		/*	Commented by Kurt 2012/10/16 */
+		/*	IOT issue: Google Nexus7 use 1M rate to send p2p_probe_req after GO nego completed and Nexus7 is client */
+		if (padapter->registrypriv.wifi_spec == 1) {
+			if (pattrib->data_rate <= DESC_RATE11M)
+				wifi_test_chk_rate = 0;
+		}
+
+		if (wifi_test_chk_rate == 1) {
+			is_valid_p2p_probereq = process_probe_req_p2p_ie(pwdinfo, pframe, len);
+			if (is_valid_p2p_probereq == _TRUE) {
+				if (rtw_p2p_chk_role(pwdinfo, P2P_ROLE_DEVICE)) {
+					/* FIXME */
+					if (padapter->wdinfo.driver_interface == DRIVER_WEXT)
+						report_survey_event(padapter, precv_frame);
+
+					p2p_listen_state_process(padapter,  get_sa(pframe));
+
+					return _SUCCESS;
+				}
+
+				if (rtw_p2p_chk_role(pwdinfo, P2P_ROLE_GO))
+					goto _continue;
+			}
+		}
+	}
+
+_continue:
+#endif /* CONFIG_P2P */
+
+	if (check_fwstate(pmlmepriv, WIFI_STATION_STATE))
+		return _SUCCESS;
+
+	if (check_fwstate(pmlmepriv, _FW_LINKED) == _FALSE &&
+	    check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE | WIFI_AP_STATE | WIFI_MESH_STATE) == _FALSE)
+		return _SUCCESS;
+
+
+	/* RTW_INFO("+OnProbeReq\n"); */
+
+
+#ifdef CONFIG_ATMEL_RC_PATCH
+	wps_ie = rtw_get_wps_ie(
+			      pframe + WLAN_HDR_A3_LEN + _PROBEREQ_IE_OFFSET_,
+			      len - WLAN_HDR_A3_LEN - _PROBEREQ_IE_OFFSET_,
+			      NULL, &wps_ielen);
+	if (wps_ie)
+		target_ie = rtw_get_wps_attr_content(wps_ie, wps_ielen, WPS_ATTR_MANUFACTURER, NULL, &target_ielen);
+	if ((target_ie && (target_ielen == 4)) && (_TRUE == _rtw_memcmp((void *)target_ie, "Ozmo", 4))) {
+		/* psta->flag_atmel_rc = 1; */
+		unsigned char *sa_addr = get_sa(pframe);
+		printk("%s: Find Ozmo RC -- %02x:%02x:%02x:%02x:%02x:%02x  \n\n",
+		       __func__, *sa_addr, *(sa_addr + 1), *(sa_addr + 2), *(sa_addr + 3), *(sa_addr + 4), *(sa_addr + 5));
+		_rtw_memcpy(pstapriv->atmel_rc_pattern, get_sa(pframe), ETH_ALEN);
+	}
+#endif
+
+
+#ifdef CONFIG_AUTO_AP_MODE
+	if (check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE &&
+	    pmlmepriv->cur_network.join_res == _TRUE) {
+		_irqL	irqL;
+		struct sta_info	*psta;
+		u8 *mac_addr, *peer_addr;
+		struct sta_priv *pstapriv = &padapter->stapriv;
+		u8 RC_OUI[4] = {0x00, 0xE0, 0x4C, 0x0A};
+		/* EID[1] + EID_LEN[1] + RC_OUI[4] + MAC[6] + PairingID[2] + ChannelNum[2] */
+
+		p = rtw_get_ie(pframe + WLAN_HDR_A3_LEN + _PROBEREQ_IE_OFFSET_, _VENDOR_SPECIFIC_IE_, (int *)&ielen,
+			       len - WLAN_HDR_A3_LEN - _PROBEREQ_IE_OFFSET_);
+
+		if (!p || ielen != 14)
+			goto _non_rc_device;
+
+		if (!_rtw_memcmp(p + 2, RC_OUI, sizeof(RC_OUI)))
+			goto _non_rc_device;
+
+		if (!_rtw_memcmp(p + 6, get_sa(pframe), ETH_ALEN)) {
+			RTW_INFO("%s, do rc pairing ("MAC_FMT"), but mac addr mismatch!("MAC_FMT")\n", __FUNCTION__,
+				 MAC_ARG(get_sa(pframe)), MAC_ARG(p + 6));
+
+			goto _non_rc_device;
+		}
+
+		RTW_INFO("%s, got the pairing device("MAC_FMT")\n", __FUNCTION__,  MAC_ARG(get_sa(pframe)));
+
+		/* new a station */
+		psta = rtw_get_stainfo(pstapriv, get_sa(pframe));
+		if (psta == NULL) {
+			/* allocate a new one */
+			RTW_INFO("going to alloc stainfo for rc="MAC_FMT"\n",  MAC_ARG(get_sa(pframe)));
+			psta = rtw_alloc_stainfo(pstapriv, get_sa(pframe));
+			if (psta == NULL) {
+				/* TODO: */
+				RTW_INFO(" Exceed the upper limit of supported clients...\n");
+				return _SUCCESS;
+			}
+
+			_enter_critical_bh(&pstapriv->asoc_list_lock, &irqL);
+			if (rtw_is_list_empty(&psta->asoc_list)) {
+				psta->expire_to = pstapriv->expire_to;
+				rtw_list_insert_tail(&psta->asoc_list, &pstapriv->asoc_list);
+				pstapriv->asoc_list_cnt++;
+			}
+			_exit_critical_bh(&pstapriv->asoc_list_lock, &irqL);
+
+			/* generate pairing ID */
+			mac_addr = adapter_mac_addr(padapter);
+			peer_addr = psta->cmn.mac_addr;
+			psta->pid = (u16)(((mac_addr[4] << 8) + mac_addr[5]) + ((peer_addr[4] << 8) + peer_addr[5]));
+
+			/* update peer stainfo */
+			psta->isrc = _TRUE;
+
+			/* AID assignment */
+			if (psta->cmn.aid > 0)
+				RTW_INFO(FUNC_ADPT_FMT" old AID=%d\n", FUNC_ADPT_ARG(padapter), psta->cmn.aid);
+			else {
+				if (!rtw_aid_alloc(padapter, psta)) {
+					RTW_INFO(FUNC_ADPT_FMT" no room for more AIDs\n", FUNC_ADPT_ARG(padapter));
+					return _SUCCESS;
+				}
+				RTW_INFO(FUNC_ADPT_FMT" allocate new AID=%d\n", FUNC_ADPT_ARG(padapter), psta->cmn.aid);
+			}
+
+			psta->qos_option = 1;
+			psta->cmn.bw_mode = CHANNEL_WIDTH_20;
+			psta->ieee8021x_blocked = _FALSE;
+#ifdef CONFIG_80211N_HT
+			if(padapter->registrypriv.ht_enable &&
+				is_supported_ht(padapter->registrypriv.wireless_mode)) {
+				psta->htpriv.ht_option = _TRUE;
+				psta->htpriv.ampdu_enable = _FALSE;
+				psta->htpriv.sgi_20m = _FALSE;
+				psta->htpriv.sgi_40m = _FALSE;
+				psta->htpriv.ch_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
+				psta->htpriv.agg_enable_bitmap = 0x0;/* reset */
+				psta->htpriv.candidate_tid_bitmap = 0x0;/* reset */
+			}
+#endif
+
+			rtw_hal_set_odm_var(padapter, HAL_ODM_STA_INFO, psta, _TRUE);
+
+			_rtw_memset((void *)&psta->sta_stats, 0, sizeof(struct stainfo_stats));
+
+			_enter_critical_bh(&psta->lock, &irqL);
+			psta->state |= _FW_LINKED;
+			_exit_critical_bh(&psta->lock, &irqL);
+
+			report_add_sta_event(padapter, psta->cmn.mac_addr);
+
+		}
+
+		issue_probersp(padapter, get_sa(pframe), _FALSE);
+
+		return _SUCCESS;
+
+	}
+
+_non_rc_device:
+
+	return _SUCCESS;
+
+#endif /* CONFIG_AUTO_AP_MODE */
+
+
+#ifdef CONFIG_CONCURRENT_MODE
+	if (((pmlmeinfo->state & 0x03) == WIFI_FW_AP_STATE) &&
+	    rtw_mi_buddy_check_fwstate(padapter, _FW_UNDER_LINKING | _FW_UNDER_SURVEY)) {
+		/* don't process probe req */
+		return _SUCCESS;
+	}
+#endif
+
+	p = rtw_get_ie(pframe + WLAN_HDR_A3_LEN + _PROBEREQ_IE_OFFSET_, _SSID_IE_, (int *)&ielen,
+		       len - WLAN_HDR_A3_LEN - _PROBEREQ_IE_OFFSET_);
+
+
+	/* check (wildcard) SSID */
+	if (p != NULL) {
+		if (is_valid_p2p_probereq == _TRUE)
+			goto _issue_probersp;
+
+		if ((ielen != 0 && _FALSE == _rtw_memcmp((void *)(p + 2), (void *)cur->Ssid.Ssid, cur->Ssid.SsidLength))
+			|| (ielen == 0 && pmlmeinfo->hidden_ssid_mode))
+			goto exit;
+
+		#ifdef CONFIG_RTW_MESH
+		if (MLME_IS_MESH(padapter)) {
+			p = rtw_get_ie(pframe + WLAN_HDR_A3_LEN + _PROBEREQ_IE_OFFSET_, WLAN_EID_MESH_ID, (int *)&ielen,
+					len - WLAN_HDR_A3_LEN - _PROBEREQ_IE_OFFSET_);
+
+			if (!p)
+				goto exit;
+			if (ielen != 0 && _rtw_memcmp((void *)(p + 2), (void *)cur->mesh_id.Ssid, cur->mesh_id.SsidLength) == _FALSE)
+				goto exit;
+		}
+		#endif
+
+_issue_probersp:
+		if (((check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE &&
+		      pmlmepriv->cur_network.join_res == _TRUE)) || check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE)) {
+			/* RTW_INFO("+issue_probersp during ap mode\n"); */
+			issue_probersp(padapter, get_sa(pframe), is_valid_p2p_probereq);
+		}
+
+	}
+
+exit:
+	return _SUCCESS;
+
+}
+
+unsigned int OnProbeRsp(_adapter *padapter, union recv_frame *precv_frame)
+{
+	struct mlme_ext_priv	*pmlmeext = &padapter->mlmeextpriv;
+	u8	*pframe = precv_frame->u.hdr.rx_data;
+#ifdef CONFIG_P2P
+	struct wifidirect_info	*pwdinfo = &padapter->wdinfo;
+#endif
+
+
+#ifdef CONFIG_P2P
+	if (rtw_p2p_chk_state(pwdinfo, P2P_STATE_TX_PROVISION_DIS_REQ)) {
+		if (_TRUE == pwdinfo->tx_prov_disc_info.benable) {
+			if (_rtw_memcmp(pwdinfo->tx_prov_disc_info.peerIFAddr, get_addr2_ptr(pframe), ETH_ALEN)) {
+				if (rtw_p2p_chk_role(pwdinfo, P2P_ROLE_CLIENT)) {
+					pwdinfo->tx_prov_disc_info.benable = _FALSE;
+					issue_p2p_provision_request(padapter,
+						pwdinfo->tx_prov_disc_info.ssid.Ssid,
+						pwdinfo->tx_prov_disc_info.ssid.SsidLength,
+						pwdinfo->tx_prov_disc_info.peerDevAddr);
+				} else if (rtw_p2p_chk_role(pwdinfo, P2P_ROLE_DEVICE) || rtw_p2p_chk_role(pwdinfo, P2P_ROLE_GO)) {
+					pwdinfo->tx_prov_disc_info.benable = _FALSE;
+					issue_p2p_provision_request(padapter,
+								    NULL,
+								    0,
+						pwdinfo->tx_prov_disc_info.peerDevAddr);
+				}
+			}
+		}
+		return _SUCCESS;
+	} else if (rtw_p2p_chk_state(pwdinfo, P2P_STATE_GONEGO_ING)) {
+		if (_TRUE == pwdinfo->nego_req_info.benable) {
+			RTW_INFO("[%s] P2P State is GONEGO ING!\n", __FUNCTION__);
+			if (_rtw_memcmp(pwdinfo->nego_req_info.peerDevAddr, get_addr2_ptr(pframe), ETH_ALEN)) {
+				pwdinfo->nego_req_info.benable = _FALSE;
+				issue_p2p_GO_request(padapter, pwdinfo->nego_req_info.peerDevAddr);
+			}
+		}
+	} else if (rtw_p2p_chk_state(pwdinfo, P2P_STATE_TX_INVITE_REQ)) {
+		if (_TRUE == pwdinfo->invitereq_info.benable) {
+			RTW_INFO("[%s] P2P_STATE_TX_INVITE_REQ!\n", __FUNCTION__);
+			if (_rtw_memcmp(pwdinfo->invitereq_info.peer_macaddr, get_addr2_ptr(pframe), ETH_ALEN)) {
+				pwdinfo->invitereq_info.benable = _FALSE;
+				issue_p2p_invitation_request(padapter, pwdinfo->invitereq_info.peer_macaddr);
+			}
+		}
+	}
+#endif
+
+
+	if ((mlmeext_chk_scan_state(pmlmeext, SCAN_PROCESS))
+		|| (MLME_IS_MESH(padapter) && check_fwstate(&padapter->mlmepriv, WIFI_ASOC_STATE))
+		#ifdef CONFIG_RTW_REPEATER_SON
+		|| (padapter->rtw_rson_scanstage == RSON_SCAN_PROCESS)
+		#endif
+	) {
+		rtw_mi_report_survey_event(padapter, precv_frame);
+		return _SUCCESS;
+	}
+
+#if 0 /* move to validate_recv_mgnt_frame */
+	if (_rtw_memcmp(GetAddr3Ptr(pframe), get_my_bssid(&pmlmeinfo->network), ETH_ALEN)) {
+		if (pmlmeinfo->state & WIFI_FW_ASSOC_SUCCESS) {
+			psta = rtw_get_stainfo(pstapriv, get_addr2_ptr(pframe));
+			if (psta != NULL)
+				psta->sta_stats.rx_mgnt_pkts++;
+		}
+	}
+#endif
+
+	return _SUCCESS;
+
+}
+
+/* for 11n Logo 4.2.31/4.2.32 */
+static void rtw_check_legacy_ap(_adapter *padapter, u8 *pframe, u32 len)
+{
+
+	struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
+	struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
+
+	if (!padapter->registrypriv.wifi_spec)
+		return;
+	
+	if(!MLME_IS_AP(padapter))
+		return;
+	
+
+	if (pmlmeext->bstart_bss == _TRUE) {
+		int left;
+		unsigned char *pos;
+		struct rtw_ieee802_11_elems elems;
+#ifdef CONFIG_80211N_HT
+		u16 cur_op_mode; 
+#endif
+		/* checking IEs */
+		left = len - sizeof(struct rtw_ieee80211_hdr_3addr) - _BEACON_IE_OFFSET_;
+		pos = pframe + sizeof(struct rtw_ieee80211_hdr_3addr) + _BEACON_IE_OFFSET_;
+		if (rtw_ieee802_11_parse_elems(pos, left, &elems, 1) == ParseFailed) {
+			RTW_INFO("%s: parse fail for "MAC_FMT"\n", __func__, MAC_ARG(GetAddr3Ptr(pframe)));
+			return;
+		}
+#ifdef CONFIG_80211N_HT
+		cur_op_mode = pmlmepriv->ht_op_mode & HT_INFO_OPERATION_MODE_OP_MODE_MASK;
+#endif
+		/* for legacy ap */
+		if (elems.ht_capabilities == NULL && elems.ht_capabilities_len == 0) {
+
+			if (0)
+				RTW_INFO("%s: "MAC_FMT" is legacy ap\n", __func__, MAC_ARG(GetAddr3Ptr(pframe)));
+
+			ATOMIC_SET(&pmlmepriv->olbc, _TRUE);
+			ATOMIC_SET(&pmlmepriv->olbc_ht, _TRUE);
+		}
+			
+	}
+}
+
+unsigned int OnBeacon(_adapter *padapter, union recv_frame *precv_frame)
+{
+	struct sta_info	*psta;
+	struct mlme_ext_priv	*pmlmeext = &padapter->mlmeextpriv;
+	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
+	struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
+	struct sta_priv	*pstapriv = &padapter->stapriv;
+	u8 *pframe = precv_frame->u.hdr.rx_data;
+	uint len = precv_frame->u.hdr.len;
+	WLAN_BSSID_EX *pbss;
+	int ret = _SUCCESS;
+#ifdef CONFIG_TDLS
+	struct sta_info *ptdls_sta;
+	struct tdls_info *ptdlsinfo = &padapter->tdlsinfo;
+#ifdef CONFIG_TDLS_CH_SW
+	struct tdls_ch_switch *pchsw_info = &padapter->tdlsinfo.chsw_info;
+#endif
+#endif /* CONFIG_TDLS */
+
+	if (validate_beacon_len(pframe, len) == _FALSE)
+		return _SUCCESS;
+
+	if (mlmeext_chk_scan_state(pmlmeext, SCAN_PROCESS)
+		|| (MLME_IS_MESH(padapter) && check_fwstate(pmlmepriv, WIFI_ASOC_STATE))
+	) {
+		rtw_mi_report_survey_event(padapter, precv_frame);
+		return _SUCCESS;
+	}
+#ifdef CONFIG_RTW_REPEATER_SON
+	if (padapter->rtw_rson_scanstage == RSON_SCAN_PROCESS)
+		rtw_mi_report_survey_event(padapter, precv_frame);
+#endif
+
+	rtw_check_legacy_ap(padapter, pframe, len);
+
+	if (_rtw_memcmp(GetAddr3Ptr(pframe), get_my_bssid(&pmlmeinfo->network), ETH_ALEN)) {
+		if ((pmlmeinfo->state & WIFI_FW_AUTH_NULL)
+			&& (rtw_sta_linking_test_wait_done() || pmlmeext->join_abort)
+		) {
+			if (rtw_sta_linking_test_force_fail() || pmlmeext->join_abort) {
+				set_link_timer(pmlmeext, 1);
+				return _SUCCESS;
+			}
+
+			/* we should update current network before auth, or some IE is wrong */
+			pbss = (WLAN_BSSID_EX *)rtw_malloc(sizeof(WLAN_BSSID_EX));
+			if (pbss) {
+				if (collect_bss_info(padapter, precv_frame, pbss) == _SUCCESS) {
+					struct beacon_keys recv_beacon;
+
+					update_network(&(pmlmepriv->cur_network.network), pbss, padapter, _TRUE);
+					rtw_get_bcn_info(&(pmlmepriv->cur_network));
+
+					/* update bcn keys */
+					if (rtw_get_bcn_keys(padapter, pframe, len, &recv_beacon) == _TRUE) {
+						RTW_INFO("%s: beacon keys ready\n", __func__);
+						_rtw_memcpy(&pmlmepriv->cur_beacon_keys,
+							&recv_beacon, sizeof(recv_beacon));
+					} else {
+						RTW_ERR("%s: get beacon keys failed\n", __func__);
+						_rtw_memset(&pmlmepriv->cur_beacon_keys, 0, sizeof(recv_beacon));
+					}
+					#ifdef CONFIG_BCN_CNT_CONFIRM_HDL
+					pmlmepriv->new_beacon_cnts = 0;
+					#endif
+				}
+				rtw_mfree((u8 *)pbss, sizeof(WLAN_BSSID_EX));
+			}
+
+			/* check the vendor of the assoc AP */
+			pmlmeinfo->assoc_AP_vendor = check_assoc_AP(pframe + sizeof(struct rtw_ieee80211_hdr_3addr), len - sizeof(struct rtw_ieee80211_hdr_3addr));
+
+			/* update TSF Value */
+			update_TSF(pmlmeext, pframe, len);
+			pmlmeext->bcn_cnt = 0;
+			pmlmeext->last_bcn_cnt = 0;
+
+#ifdef CONFIG_P2P_PS
+			/* Comment by YiWei , in wifi p2p spec the "3.3 P2P Power Management" , "These mechanisms are available in a P2P Group in which only P2P Devices are associated." */
+			/* process_p2p_ps_ie(padapter, (pframe + WLAN_HDR_A3_LEN), (len - WLAN_HDR_A3_LEN)); */
+#endif /* CONFIG_P2P_PS */
+
+#if defined(CONFIG_P2P) && defined(CONFIG_CONCURRENT_MODE)
+			if (padapter->registrypriv.wifi_spec) {
+				if (process_p2p_cross_connect_ie(padapter, (pframe + WLAN_HDR_A3_LEN), (len - WLAN_HDR_A3_LEN)) == _FALSE) {
+					if (rtw_mi_buddy_check_mlmeinfo_state(padapter, WIFI_FW_AP_STATE)) {
+						RTW_PRINT("no issue auth, P2P cross-connect does not permit\n ");
+						return _SUCCESS;
+					}
+				}
+			}
+#endif /* CONFIG_P2P CONFIG_P2P and CONFIG_CONCURRENT_MODE */
+
+			/* start auth */
+			start_clnt_auth(padapter);
+
+			return _SUCCESS;
+		}
+
+		if (((pmlmeinfo->state & 0x03) == WIFI_FW_STATION_STATE) && (pmlmeinfo->state & WIFI_FW_ASSOC_SUCCESS)) {
+			psta = rtw_get_stainfo(pstapriv, get_addr2_ptr(pframe));
+			if (psta != NULL) {
+#ifdef CONFIG_PATCH_JOIN_WRONG_CHANNEL
+				/* Merge from 8712 FW code */
+				if (cmp_pkt_chnl_diff(padapter, pframe, len) != 0) {
+					/* join wrong channel, deauth and reconnect           */
+					issue_deauth(padapter, (&(pmlmeinfo->network))->MacAddress, WLAN_REASON_DEAUTH_LEAVING);
+
+					report_del_sta_event(padapter, (&(pmlmeinfo->network))->MacAddress, WLAN_REASON_JOIN_WRONG_CHANNEL, _TRUE, _FALSE);
+					pmlmeinfo->state &= (~WIFI_FW_ASSOC_SUCCESS);
+					return _SUCCESS;
+				}
+#endif /* CONFIG_PATCH_JOIN_WRONG_CHANNEL */
+#ifdef CONFIG_RTW_80211R
+				rtw_ft_update_bcn(padapter, precv_frame);
+#endif
+				ret = rtw_check_bcn_info(padapter, pframe, len);
+				if (!ret) {
+					RTW_PRINT("ap has changed, disconnect now\n ");
+					receive_disconnect(padapter, pmlmeinfo->network.MacAddress , 0, _FALSE);
+					return _SUCCESS;
+				}
+				/* update WMM, ERP in the beacon */
+				/* todo: the timer is used instead of the number of the beacon received */
+				if ((sta_rx_pkts(psta) & 0xf) == 0) {
+					/* RTW_INFO("update_bcn_info\n"); */
+					update_beacon_info(padapter, pframe, len, psta);
+				}
+
+				pmlmepriv->cur_network_scanned->network.Rssi = precv_frame->u.hdr.attrib.phy_info.recv_signal_power;
+				pmlmeext->bcn_cnt++;
+#ifdef CONFIG_BCN_RECV_TIME
+				rtw_rx_bcn_time_update(padapter, len, precv_frame->u.hdr.attrib.data_rate);
+#endif
+#ifdef CONFIG_TDLS
+#ifdef CONFIG_TDLS_CH_SW
+				if (rtw_tdls_is_chsw_allowed(padapter) == _TRUE) {
+					/* Send TDLS Channel Switch Request when receiving Beacon */
+					if ((padapter->tdlsinfo.chsw_info.ch_sw_state & TDLS_CH_SW_INITIATOR_STATE) && (ATOMIC_READ(&pchsw_info->chsw_on) == _TRUE)
+					    && (pmlmeext->cur_channel == rtw_get_oper_ch(padapter))) {
+						ptdls_sta = rtw_get_stainfo(&padapter->stapriv, padapter->tdlsinfo.chsw_info.addr);
+						if (ptdls_sta != NULL) {
+							if (ptdls_sta->tdls_sta_state | TDLS_LINKED_STATE)
+								_set_timer(&ptdls_sta->stay_on_base_chnl_timer, TDLS_CH_SW_STAY_ON_BASE_CHNL_TIMEOUT);
+						}
+					}
+				}
+#endif
+#endif /* CONFIG_TDLS */
+
+				#ifdef CONFIG_DFS
+				process_csa_ie(padapter
+					, pframe + WLAN_HDR_A3_LEN + _BEACON_IE_OFFSET_
+					, len - (WLAN_HDR_A3_LEN + _BEACON_IE_OFFSET_));
+				#endif
+
+#ifdef CONFIG_P2P_PS
+				process_p2p_ps_ie(padapter, (pframe + WLAN_HDR_A3_LEN), (len - WLAN_HDR_A3_LEN));
+#endif /* CONFIG_P2P_PS */
+
+				if (pmlmeext->tsf_update_required && pmlmeext->en_hw_update_tsf)
+					rtw_enable_hw_update_tsf_cmd(padapter);
+
+#if 0 /* move to validate_recv_mgnt_frame */
+				psta->sta_stats.rx_mgnt_pkts++;
+#endif
+			}
+
+		} else if ((pmlmeinfo->state & 0x03) == WIFI_FW_ADHOC_STATE) {
+			u8 rate_set[16];
+			u8 rate_num = 0;
+
+			psta = rtw_get_stainfo(pstapriv, get_addr2_ptr(pframe));
+			if (psta != NULL) {
+				/*
+				* update WMM, ERP in the beacon
+				* todo: the timer is used instead of the number of the beacon received
+				*/
+				if ((sta_rx_pkts(psta) & 0xf) == 0)
+					update_beacon_info(padapter, pframe, len, psta);
+
+				if (pmlmeext->tsf_update_required && pmlmeext->en_hw_update_tsf)
+					rtw_enable_hw_update_tsf_cmd(padapter);
+			} else {
+				rtw_ies_get_supported_rate(pframe + WLAN_HDR_A3_LEN + _BEACON_IE_OFFSET_, len - WLAN_HDR_A3_LEN - _BEACON_IE_OFFSET_, rate_set, &rate_num);
+				if (rate_num == 0) {
+					RTW_INFO(FUNC_ADPT_FMT" RX beacon with no supported rate\n", FUNC_ADPT_ARG(padapter));
+					goto _END_ONBEACON_;
+				}
+
+				psta = rtw_alloc_stainfo(pstapriv, get_addr2_ptr(pframe));
+				if (psta == NULL) {
+					RTW_INFO(FUNC_ADPT_FMT" Exceed the upper limit of supported clients\n", FUNC_ADPT_ARG(padapter));
+					goto _END_ONBEACON_;
+				}
+
+				psta->expire_to = pstapriv->adhoc_expire_to;
+
+				_rtw_memcpy(psta->bssrateset, rate_set, rate_num);
+				psta->bssratelen = rate_num;
+
+				/* update TSF Value */
+				update_TSF(pmlmeext, pframe, len);
+
+				/* report sta add event */
+				report_add_sta_event(padapter, get_addr2_ptr(pframe));
+			}
+		}
+	}
+
+_END_ONBEACON_:
+
+	return _SUCCESS;
+
+}
+
+unsigned int OnAuth(_adapter *padapter, union recv_frame *precv_frame)
+{
+#ifdef CONFIG_AP_MODE
+	_irqL irqL;
+	unsigned int	auth_mode, seq, ie_len;
+	unsigned char	*sa, *p;
+	u16	algorithm;
+	int	status;
+	static struct sta_info stat;
+	struct	sta_info	*pstat = NULL;
+	struct	sta_priv *pstapriv = &padapter->stapriv;
+	struct security_priv *psecuritypriv = &padapter->securitypriv;
+	struct mlme_ext_priv	*pmlmeext = &padapter->mlmeextpriv;
+	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
+	u8 *pframe = precv_frame->u.hdr.rx_data;
+	uint len = precv_frame->u.hdr.len;
+	u8	offset = 0;
+
+
+#ifdef CONFIG_CONCURRENT_MODE
+	if (((pmlmeinfo->state & 0x03) == WIFI_FW_AP_STATE) &&
+	    rtw_mi_buddy_check_fwstate(padapter, _FW_UNDER_LINKING | _FW_UNDER_SURVEY)) {
+		/* don't process auth request; */
+		return _SUCCESS;
+	}
+#endif /* CONFIG_CONCURRENT_MODE */
+
+	if ((pmlmeinfo->state & 0x03) != WIFI_FW_AP_STATE)
+		return _FAIL;
+
+	if (!MLME_IS_ASOC(padapter))
+		return _SUCCESS;
+
+#if defined(CONFIG_IOCTL_CFG80211) && defined(CONFIG_RTW_MESH)
+	if (MLME_IS_MESH(padapter))
+		return rtw_mesh_on_auth(padapter, precv_frame);
+#endif
+
+	RTW_INFO("+OnAuth\n");
+
+	sa = get_addr2_ptr(pframe);
+
+	auth_mode = psecuritypriv->dot11AuthAlgrthm;
+
+	if (GetPrivacy(pframe)) {
+		u8	*iv;
+		struct rx_pkt_attrib	*prxattrib = &(precv_frame->u.hdr.attrib);
+
+		prxattrib->hdrlen = WLAN_HDR_A3_LEN;
+		prxattrib->encrypt = _WEP40_;
+
+		iv = pframe + prxattrib->hdrlen;
+		prxattrib->key_index = ((iv[3] >> 6) & 0x3);
+
+		prxattrib->iv_len = 4;
+		prxattrib->icv_len = 4;
+
+		rtw_wep_decrypt(padapter, (u8 *)precv_frame);
+
+		offset = 4;
+	}
+
+	algorithm = le16_to_cpu(*(u16 *)((SIZE_PTR)pframe + WLAN_HDR_A3_LEN + offset));
+	seq	= le16_to_cpu(*(u16 *)((SIZE_PTR)pframe + WLAN_HDR_A3_LEN + offset + 2));
+
+	RTW_INFO("auth alg=%x, seq=%X\n", algorithm, seq);
+
+	if (rtw_ap_linking_test_force_auth_fail()) {
+		status = rtw_ap_linking_test_force_auth_fail();
+		RTW_INFO(FUNC_ADPT_FMT" force auth fail with status:%u\n"
+			, FUNC_ADPT_ARG(padapter), status);
+		goto auth_fail;
+	}
+
+	if (auth_mode == 2 &&
+	    psecuritypriv->dot11PrivacyAlgrthm != _WEP40_ &&
+	    psecuritypriv->dot11PrivacyAlgrthm != _WEP104_)
+		auth_mode = 0;
+
+	if ((algorithm > 0 && auth_mode == 0) ||	/* rx a shared-key auth but shared not enabled */
+	    (algorithm == 0 && auth_mode == 1)) {	/* rx a open-system auth but shared-key is enabled */
+		RTW_INFO("auth rejected due to bad alg [alg=%d, auth_mib=%d] %02X%02X%02X%02X%02X%02X\n",
+			algorithm, auth_mode, sa[0], sa[1], sa[2], sa[3], sa[4], sa[5]);
+
+		status = _STATS_NO_SUPP_ALG_;
+
+		goto auth_fail;
+	}
+
+#if CONFIG_RTW_MACADDR_ACL
+	if (rtw_access_ctrl(padapter, sa) == _FALSE) {
+		status = _STATS_UNABLE_HANDLE_STA_;
+		goto auth_fail;
+	}
+#endif
+
+	pstat = rtw_get_stainfo(pstapriv, sa);
+	if (pstat == NULL) {
+
+		/* allocate a new one */
+		RTW_INFO("going to alloc stainfo for sa="MAC_FMT"\n",  MAC_ARG(sa));
+		pstat = rtw_alloc_stainfo(pstapriv, sa);
+		if (pstat == NULL) {
+			RTW_INFO(" Exceed the upper limit of supported clients...\n");
+			status = _STATS_UNABLE_HANDLE_STA_;
+			goto auth_fail;
+		}
+
+		pstat->state = WIFI_FW_AUTH_NULL;
+		pstat->auth_seq = 0;
+
+		/* pstat->flags = 0; */
+		/* pstat->capability = 0; */
+	} else {
+#ifdef CONFIG_IEEE80211W
+		if (pstat->bpairwise_key_installed != _TRUE && !(pstat->state & WIFI_FW_ASSOC_SUCCESS))
+#endif /* CONFIG_IEEE80211W */
+		{
+
+			_enter_critical_bh(&pstapriv->asoc_list_lock, &irqL);
+			if (rtw_is_list_empty(&pstat->asoc_list) == _FALSE) {
+				rtw_list_delete(&pstat->asoc_list);
+				pstapriv->asoc_list_cnt--;
+				if (pstat->expire_to > 0)
+					;/* TODO: STA re_auth within expire_to */
+			}
+			_exit_critical_bh(&pstapriv->asoc_list_lock, &irqL);
+
+			if (seq == 1)
+				; /* TODO: STA re_auth and auth timeout */
+
+		}
+	}
+
+#ifdef CONFIG_IEEE80211W
+	if (pstat->bpairwise_key_installed != _TRUE && !(pstat->state & WIFI_FW_ASSOC_SUCCESS))
+#endif /* CONFIG_IEEE80211W */
+	{
+		_enter_critical_bh(&pstapriv->auth_list_lock, &irqL);
+		if (rtw_is_list_empty(&pstat->auth_list)) {
+
+			rtw_list_insert_tail(&pstat->auth_list, &pstapriv->auth_list);
+			pstapriv->auth_list_cnt++;
+		}
+		_exit_critical_bh(&pstapriv->auth_list_lock, &irqL);
+	}
+
+	if (pstat->auth_seq == 0)
+		pstat->expire_to = pstapriv->auth_to;
+
+
+	if ((pstat->auth_seq + 1) != seq) {
+		RTW_INFO("(1)auth rejected because out of seq [rx_seq=%d, exp_seq=%d]!\n",
+			 seq, pstat->auth_seq + 1);
+		status = _STATS_OUT_OF_AUTH_SEQ_;
+		goto auth_fail;
+	}
+
+	if (algorithm == 0 && (auth_mode == 0 || auth_mode == 2 || auth_mode == 3)) {
+		if (seq == 1) {
+#ifdef CONFIG_IEEE80211W
+			if (pstat->bpairwise_key_installed != _TRUE && !(pstat->state & WIFI_FW_ASSOC_SUCCESS))
+#endif /* CONFIG_IEEE80211W */
+			{
+				pstat->state &= ~WIFI_FW_AUTH_NULL;
+				pstat->state |= WIFI_FW_AUTH_SUCCESS;
+				pstat->expire_to = pstapriv->assoc_to;
+			}
+			pstat->authalg = algorithm;
+		} else {
+			RTW_INFO("(2)auth rejected because out of seq [rx_seq=%d, exp_seq=%d]!\n",
+				 seq, pstat->auth_seq + 1);
+			status = _STATS_OUT_OF_AUTH_SEQ_;
+			goto auth_fail;
+		}
+	} else { /* shared system or auto authentication */
+		if (seq == 1) {
+			/* prepare for the challenging txt... */
+
+			/* get_random_bytes((void *)pstat->chg_txt, 128); */ /* TODO: */
+			_rtw_memset((void *)pstat->chg_txt, 78, 128);
+#ifdef CONFIG_IEEE80211W
+			if (pstat->bpairwise_key_installed != _TRUE && !(pstat->state & WIFI_FW_ASSOC_SUCCESS))
+#endif /* CONFIG_IEEE80211W */
+			{
+				pstat->state &= ~WIFI_FW_AUTH_NULL;
+				pstat->state |= WIFI_FW_AUTH_STATE;
+			}
+			pstat->authalg = algorithm;
+			pstat->auth_seq = 2;
+		} else if (seq == 3) {
+			/* checking for challenging txt... */
+			RTW_INFO("checking for challenging txt...\n");
+
+			p = rtw_get_ie(pframe + WLAN_HDR_A3_LEN + 4 + _AUTH_IE_OFFSET_ , _CHLGETXT_IE_, (int *)&ie_len,
+				len - WLAN_HDR_A3_LEN - _AUTH_IE_OFFSET_ - 4);
+
+			if ((p == NULL) || (ie_len <= 0)) {
+				RTW_INFO("auth rejected because challenge failure!(1)\n");
+				status = _STATS_CHALLENGE_FAIL_;
+				goto auth_fail;
+			}
+
+			if (_rtw_memcmp((void *)(p + 2), pstat->chg_txt, 128)) {
+#ifdef CONFIG_IEEE80211W
+				if (pstat->bpairwise_key_installed != _TRUE && !(pstat->state & WIFI_FW_ASSOC_SUCCESS))
+#endif /* CONFIG_IEEE80211W */
+				{
+					pstat->state &= (~WIFI_FW_AUTH_STATE);
+					pstat->state |= WIFI_FW_AUTH_SUCCESS;
+					/* challenging txt is correct... */
+					pstat->expire_to =  pstapriv->assoc_to;
+				}
+			} else {
+				RTW_INFO("auth rejected because challenge failure!\n");
+				status = _STATS_CHALLENGE_FAIL_;
+				goto auth_fail;
+			}
+		} else {
+			RTW_INFO("(3)auth rejected because out of seq [rx_seq=%d, exp_seq=%d]!\n",
+				 seq, pstat->auth_seq + 1);
+			status = _STATS_OUT_OF_AUTH_SEQ_;
+			goto auth_fail;
+		}
+	}
+
+
+	/* Now, we are going to issue_auth... */
+	pstat->auth_seq = seq + 1;
+
+#ifdef CONFIG_NATIVEAP_MLME
+	issue_auth(padapter, pstat, (unsigned short)(_STATS_SUCCESSFUL_));
+#endif
+
+	if ((pstat->state & WIFI_FW_AUTH_SUCCESS) || (pstat->state & WIFI_FW_ASSOC_SUCCESS))
+		pstat->auth_seq = 0;
+
+
+	return _SUCCESS;
+
+auth_fail:
+
+	if (pstat)
+		rtw_free_stainfo(padapter , pstat);
+
+	pstat = &stat;
+	_rtw_memset((char *)pstat, '\0', sizeof(stat));
+	pstat->auth_seq = 2;
+	_rtw_memcpy(pstat->cmn.mac_addr, sa, ETH_ALEN);
+
+#ifdef CONFIG_NATIVEAP_MLME
+	issue_auth(padapter, pstat, (unsigned short)status);
+#endif
+
+#endif
+	return _FAIL;
+
+}
+
+unsigned int OnAuthClient(_adapter *padapter, union recv_frame *precv_frame)
+{
+	unsigned int	seq, len, status, algthm, offset;
+	unsigned char	*p;
+	unsigned int	go2asoc = 0;
+	struct mlme_ext_priv	*pmlmeext = &padapter->mlmeextpriv;
+	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
+	u8 *pframe = precv_frame->u.hdr.rx_data;
+	uint pkt_len = precv_frame->u.hdr.len;
+
+	RTW_INFO("%s\n", __FUNCTION__);
+
+	/* check A1 matches or not */
+	if (!_rtw_memcmp(adapter_mac_addr(padapter), get_da(pframe), ETH_ALEN))
+		return _SUCCESS;
+
+	if (!(pmlmeinfo->state & WIFI_FW_AUTH_STATE) || pmlmeext->join_abort)
+		return _SUCCESS;
+
+	offset = (GetPrivacy(pframe)) ? 4 : 0;
+
+	algthm	= le16_to_cpu(*(unsigned short *)((SIZE_PTR)pframe + WLAN_HDR_A3_LEN + offset));
+	seq	= le16_to_cpu(*(unsigned short *)((SIZE_PTR)pframe + WLAN_HDR_A3_LEN + offset + 2));
+	status	= le16_to_cpu(*(unsigned short *)((SIZE_PTR)pframe + WLAN_HDR_A3_LEN + offset + 4));
+
+	if (status != 0) {
+		RTW_INFO("clnt auth fail, status: %d\n", status);
+		if (status == 13) { /* && pmlmeinfo->auth_algo == dot11AuthAlgrthm_Auto) */
+			if (pmlmeinfo->auth_algo == dot11AuthAlgrthm_Shared)
+				pmlmeinfo->auth_algo = dot11AuthAlgrthm_Open;
+			else
+				pmlmeinfo->auth_algo = dot11AuthAlgrthm_Shared;
+			/* pmlmeinfo->reauth_count = 0; */
+		}
+
+		pmlmeinfo->auth_status = status;
+		set_link_timer(pmlmeext, 1);
+		goto authclnt_fail;
+	}
+
+	if (seq == 2) {
+		if (pmlmeinfo->auth_algo == dot11AuthAlgrthm_Shared) {
+			/* legendary shared system */
+			p = rtw_get_ie(pframe + WLAN_HDR_A3_LEN + _AUTH_IE_OFFSET_, _CHLGETXT_IE_, (int *)&len,
+				pkt_len - WLAN_HDR_A3_LEN - _AUTH_IE_OFFSET_);
+
+			if (p == NULL) {
+				/* RTW_INFO("marc: no challenge text?\n"); */
+				goto authclnt_fail;
+			}
+
+			_rtw_memcpy((void *)(pmlmeinfo->chg_txt), (void *)(p + 2), len);
+			pmlmeinfo->auth_seq = 3;
+			issue_auth(padapter, NULL, 0);
+			set_link_timer(pmlmeext, REAUTH_TO);
+
+			return _SUCCESS;
+		} else {
+			/* open, or 802.11r FTAA system */
+			go2asoc = 1;
+		}
+	} else if (seq == 4) {
+		if (pmlmeinfo->auth_algo == dot11AuthAlgrthm_Shared)
+			go2asoc = 1;
+		else
+			goto authclnt_fail;
+	} else {
+		/* this is also illegal */
+		/* RTW_INFO("marc: clnt auth failed due to illegal seq=%x\n", seq); */
+		goto authclnt_fail;
+	}
+
+	if (go2asoc) {
+#ifdef CONFIG_RTW_80211R
+		if (rtw_ft_update_auth_rsp_ies(padapter, pframe, pkt_len))
+			return _SUCCESS;
+#endif
+		RTW_PRINT("auth success, start assoc\n");
+		start_clnt_assoc(padapter);
+		return _SUCCESS;
+	}
+
+authclnt_fail:
+
+	/* pmlmeinfo->state &= ~(WIFI_FW_AUTH_STATE); */
+
+	return _FAIL;
+
+}
+
+unsigned int OnAssocReq(_adapter *padapter, union recv_frame *precv_frame)
+{
+#ifdef CONFIG_AP_MODE
+	_irqL irqL;
+	u16 listen_interval;
+	struct rtw_ieee802_11_elems elems;
+	struct sta_info	*pstat;
+	unsigned char		reassoc, *pos;
+	int		left;
+	unsigned short		status = _STATS_SUCCESSFUL_;
+	unsigned short		frame_type, ie_offset = 0;
+	struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
+	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
+	WLAN_BSSID_EX	*cur = &(pmlmeinfo->network);
+	struct sta_priv *pstapriv = &padapter->stapriv;
+	u8 *pframe = precv_frame->u.hdr.rx_data;
+	uint pkt_len = precv_frame->u.hdr.len;
+#ifdef CONFIG_P2P
+	struct wifidirect_info	*pwdinfo = &(padapter->wdinfo);
+	u8 p2p_status_code = P2P_STATUS_SUCCESS;
+	u8 *p2pie;
+	u32 p2pielen = 0;
+#endif /* CONFIG_P2P */
+
+#ifdef CONFIG_CONCURRENT_MODE
+	if (((pmlmeinfo->state & 0x03) == WIFI_FW_AP_STATE) &&
+	    rtw_mi_buddy_check_fwstate(padapter, _FW_UNDER_LINKING | _FW_UNDER_SURVEY)) {
+		/* don't process assoc request; */
+		return _SUCCESS;
+	}
+#endif /* CONFIG_CONCURRENT_MODE */
+
+	if ((pmlmeinfo->state & 0x03) != WIFI_FW_AP_STATE)
+		return _FAIL;
+
+	frame_type = get_frame_sub_type(pframe);
+	if (frame_type == WIFI_ASSOCREQ) {
+		reassoc = 0;
+		ie_offset = _ASOCREQ_IE_OFFSET_;
+	} else { /* WIFI_REASSOCREQ */
+		reassoc = 1;
+		ie_offset = _REASOCREQ_IE_OFFSET_;
+	}
+
+
+	if (pkt_len < IEEE80211_3ADDR_LEN + ie_offset) {
+		RTW_INFO("handle_assoc(reassoc=%d) - too short payload (len=%lu)"
+			 "\n", reassoc, (unsigned long)pkt_len);
+		return _FAIL;
+	}
+
+	pstat = rtw_get_stainfo(pstapriv, get_addr2_ptr(pframe));
+	if (pstat == (struct sta_info *)NULL) {
+		status = _RSON_CLS2_;
+		goto asoc_class2_error;
+	}
+
+	RTW_INFO("%s\n", __FUNCTION__);
+
+	/* check if this stat has been successfully authenticated/assocated */
+	if (!((pstat->state) & WIFI_FW_AUTH_SUCCESS)) {
+		if (!((pstat->state) & WIFI_FW_ASSOC_SUCCESS)) {
+			status = _RSON_CLS2_;
+			goto asoc_class2_error;
+		} else {
+			pstat->state &= (~WIFI_FW_ASSOC_SUCCESS);
+			pstat->state |= WIFI_FW_ASSOC_STATE;
+		}
+	} else {
+		pstat->state &= (~WIFI_FW_AUTH_SUCCESS);
+		pstat->state |= WIFI_FW_ASSOC_STATE;
+	}
+
+#if 0/* todo:tkip_countermeasures */
+	if (hapd->tkip_countermeasures) {
+		resp = WLAN_REASON_MICHAEL_MIC_FAILURE;
+		goto fail;
+	}
+#endif
+
+	if (rtw_ap_linking_test_force_asoc_fail()) {
+		status = rtw_ap_linking_test_force_asoc_fail();
+		RTW_INFO(FUNC_ADPT_FMT" force asoc fail with status:%u\n"
+			, FUNC_ADPT_ARG(padapter), status);
+		goto OnAssocReqFail;
+	}
+
+	/* now parse all ieee802_11 ie to point to elems */
+	left = pkt_len - (IEEE80211_3ADDR_LEN + ie_offset);
+	pos = pframe + (IEEE80211_3ADDR_LEN + ie_offset);
+	if (rtw_ieee802_11_parse_elems(pos, left, &elems, 1) == ParseFailed) {
+		RTW_INFO("STA " MAC_FMT " sent invalid association request\n",
+			 MAC_ARG(pstat->cmn.mac_addr));
+		status = _STATS_FAILURE_;
+		goto OnAssocReqFail;
+	}
+
+	rtw_ap_parse_sta_capability(padapter, pstat, pframe + WLAN_HDR_A3_LEN);
+
+	listen_interval = RTW_GET_LE16(pframe + WLAN_HDR_A3_LEN + 2);
+#if 0/* todo: */
+	/* check listen_interval */
+	if (listen_interval > hapd->conf->max_listen_interval) {
+		hostapd_logger(hapd, mgmt->sa, HOSTAPD_MODULE_IEEE80211,
+			       HOSTAPD_LEVEL_DEBUG,
+			       "Too large Listen Interval (%d)",
+			       listen_interval);
+		resp = WLAN_STATUS_ASSOC_DENIED_LISTEN_INT_TOO_LARGE;
+		goto fail;
+	}
+
+	pstat->listen_interval = listen_interval;
+#endif
+
+	/* now we should check all the fields... */
+	/* checking SSID */
+	if (elems.ssid == NULL
+		|| elems.ssid_len == 0
+		|| elems.ssid_len != cur->Ssid.SsidLength
+		|| _rtw_memcmp(elems.ssid, cur->Ssid.Ssid, cur->Ssid.SsidLength) == _FALSE
+	) {
+		status = _STATS_FAILURE_;
+		goto OnAssocReqFail;
+	}
+
+	/* (Extended) Supported rates */
+	status = rtw_ap_parse_sta_supported_rates(padapter, pstat
+		, pframe + WLAN_HDR_A3_LEN + ie_offset, pkt_len - WLAN_HDR_A3_LEN - ie_offset);
+	if (status != _STATS_SUCCESSFUL_)
+		goto OnAssocReqFail;
+
+	/* check RSN/WPA/WPS */
+	status = rtw_ap_parse_sta_security_ie(padapter, pstat, &elems);
+	if (status != _STATS_SUCCESSFUL_)
+		goto OnAssocReqFail;
+
+	/* check if there is WMM IE & support WWM-PS */
+	rtw_ap_parse_sta_wmm_ie(padapter, pstat
+		, pframe + WLAN_HDR_A3_LEN + ie_offset, pkt_len - WLAN_HDR_A3_LEN - ie_offset);
+
+	rtw_ap_parse_sta_ht_ie(padapter, pstat, &elems);
+	rtw_ap_parse_sta_vht_ie(padapter, pstat, &elems);
+
+	if (((pstat->flags & WLAN_STA_HT) || (pstat->flags & WLAN_STA_VHT)) &&
+	    ((pstat->wpa2_pairwise_cipher & WPA_CIPHER_TKIP) ||
+	     (pstat->wpa_pairwise_cipher & WPA_CIPHER_TKIP))) {
+
+		RTW_INFO("(V)HT: " MAC_FMT " tried to use TKIP with (V)HT association\n", MAC_ARG(pstat->cmn.mac_addr));
+
+		pstat->flags &= ~WLAN_STA_HT;
+		pstat->flags &= ~WLAN_STA_VHT;
+		/*status = WLAN_STATUS_CIPHER_REJECTED_PER_POLICY;
+		  * goto OnAssocReqFail;
+		*/
+	}
+
+	if (status != _STATS_SUCCESSFUL_)
+		goto OnAssocReqFail;
+
+#ifdef CONFIG_P2P
+	pstat->is_p2p_device = _FALSE;
+	if (rtw_p2p_chk_role(pwdinfo, P2P_ROLE_GO)) {
+		p2pie = rtw_get_p2p_ie(pframe + WLAN_HDR_A3_LEN + ie_offset , pkt_len - WLAN_HDR_A3_LEN - ie_offset , NULL, &p2pielen);
+		if (p2pie) {
+			pstat->is_p2p_device = _TRUE;
+			p2p_status_code = (u8)process_assoc_req_p2p_ie(pwdinfo, pframe, pkt_len, pstat);
+			if (p2p_status_code > 0) {
+				pstat->p2p_status_code = p2p_status_code;
+				status = _STATS_CAP_FAIL_;
+				goto OnAssocReqFail;
+			}
+		}
+#ifdef CONFIG_WFD
+		rtw_process_wfd_ies(padapter, pframe + WLAN_HDR_A3_LEN + ie_offset, pkt_len - WLAN_HDR_A3_LEN - ie_offset, __func__);
+#endif
+	}
+	pstat->p2p_status_code = p2p_status_code;
+#endif /* CONFIG_P2P */
+
+#ifdef CONFIG_RTW_REPEATER_SON
+	if (rtw_rson_ap_check_sta(padapter, pframe, pkt_len, ie_offset))
+		goto OnAssocReqFail;
+#endif
+
+	/* TODO: identify_proprietary_vendor_ie(); */
+	/* Realtek proprietary IE */
+	/* identify if this is Broadcom sta */
+	/* identify if this is ralink sta */
+	/* Customer proprietary IE */
+
+#ifdef CONFIG_RTW_80211K
+	rtw_ap_parse_sta_rm_en_cap(padapter, pstat, &elems);
+#endif
+
+	/* AID assignment */
+	if (pstat->cmn.aid > 0)
+		RTW_INFO(FUNC_ADPT_FMT" old AID=%d\n", FUNC_ADPT_ARG(padapter), pstat->cmn.aid);
+	else {
+		if (!rtw_aid_alloc(padapter, pstat)) {
+			RTW_INFO(FUNC_ADPT_FMT" no room for more AIDs\n", FUNC_ADPT_ARG(padapter));
+			status = WLAN_STATUS_AP_UNABLE_TO_HANDLE_NEW_STA;
+			goto OnAssocReqFail;
+		}
+		RTW_INFO(FUNC_ADPT_FMT" allocate new AID=%d\n", FUNC_ADPT_ARG(padapter), pstat->cmn.aid);
+	}
+
+	pstat->state &= (~WIFI_FW_ASSOC_STATE);
+	pstat->state |= WIFI_FW_ASSOC_SUCCESS;
+	/* RTW_INFO("==================%s, %d,  (%x), bpairwise_key_installed=%d, MAC:"MAC_FMT"\n"
+	, __func__, __LINE__, pstat->state, pstat->bpairwise_key_installed, MAC_ARG(pstat->cmn.mac_addr)); */
+#ifdef CONFIG_IEEE80211W
+	if (pstat->bpairwise_key_installed != _TRUE)
+#endif /* CONFIG_IEEE80211W */
+	{
+		_enter_critical_bh(&pstapriv->auth_list_lock, &irqL);
+		if (!rtw_is_list_empty(&pstat->auth_list)) {
+			rtw_list_delete(&pstat->auth_list);
+			pstapriv->auth_list_cnt--;
+		}
+		_exit_critical_bh(&pstapriv->auth_list_lock, &irqL);
+
+		_enter_critical_bh(&pstapriv->asoc_list_lock, &irqL);
+		if (rtw_is_list_empty(&pstat->asoc_list)) {
+			pstat->expire_to = pstapriv->expire_to;
+			rtw_list_insert_tail(&pstat->asoc_list, &pstapriv->asoc_list);
+			pstapriv->asoc_list_cnt++;
+		}
+		_exit_critical_bh(&pstapriv->asoc_list_lock, &irqL);
+	}
+
+	/* now the station is qualified to join our BSS...	 */
+	if (pstat && (pstat->state & WIFI_FW_ASSOC_SUCCESS) && (_STATS_SUCCESSFUL_ == status)) {
+#ifdef CONFIG_NATIVEAP_MLME
+#ifdef CONFIG_IEEE80211W
+		if (pstat->bpairwise_key_installed != _TRUE)
+#endif /* CONFIG_IEEE80211W */
+		{
+			/* .1 bss_cap_update & sta_info_update */
+			bss_cap_update_on_sta_join(padapter, pstat);
+			sta_info_update(padapter, pstat);
+		}
+#ifdef CONFIG_IEEE80211W
+		if (pstat->bpairwise_key_installed == _TRUE)
+			status = _STATS_REFUSED_TEMPORARILY_;
+#endif /* CONFIG_IEEE80211W */
+		/* .2 issue assoc rsp before notify station join event. */
+		if (frame_type == WIFI_ASSOCREQ)
+			issue_asocrsp(padapter, status, pstat, WIFI_ASSOCRSP);
+		else
+			issue_asocrsp(padapter, status, pstat, WIFI_REASSOCRSP);
+
+#ifdef CONFIG_IOCTL_CFG80211
+		_enter_critical_bh(&pstat->lock, &irqL);
+		if (pstat->passoc_req) {
+			rtw_mfree(pstat->passoc_req, pstat->assoc_req_len);
+			pstat->passoc_req = NULL;
+			pstat->assoc_req_len = 0;
+		}
+
+		pstat->passoc_req =  rtw_zmalloc(pkt_len);
+		if (pstat->passoc_req) {
+			_rtw_memcpy(pstat->passoc_req, pframe, pkt_len);
+			pstat->assoc_req_len = pkt_len;
+		}
+		_exit_critical_bh(&pstat->lock, &irqL);
+#endif /* CONFIG_IOCTL_CFG80211 */
+#ifdef CONFIG_IEEE80211W
+		if (pstat->bpairwise_key_installed != _TRUE)
+#endif /* CONFIG_IEEE80211W */
+		{
+			/* .3-(1) report sta add event */
+			report_add_sta_event(padapter, pstat->cmn.mac_addr);
+		}
+#ifdef CONFIG_IEEE80211W
+		if (pstat->bpairwise_key_installed == _TRUE && SEC_IS_BIP_KEY_INSTALLED(&padapter->securitypriv) == _TRUE) {
+			RTW_INFO(MAC_FMT"\n", MAC_ARG(pstat->cmn.mac_addr));
+			issue_action_SA_Query(padapter, pstat->cmn.mac_addr, 0, 0, IEEE80211W_RIGHT_KEY);
+		}
+#endif /* CONFIG_IEEE80211W */
+#endif /* CONFIG_NATIVEAP_MLME */
+	}
+
+	return _SUCCESS;
+
+asoc_class2_error:
+
+#ifdef CONFIG_NATIVEAP_MLME
+	issue_deauth(padapter, (void *)get_addr2_ptr(pframe), status);
+#endif
+
+	return _FAIL;
+
+OnAssocReqFail:
+
+
+#ifdef CONFIG_NATIVEAP_MLME
+	pstat->cmn.aid = 0;
+	if (frame_type == WIFI_ASSOCREQ)
+		issue_asocrsp(padapter, status, pstat, WIFI_ASSOCRSP);
+	else
+		issue_asocrsp(padapter, status, pstat, WIFI_REASSOCRSP);
+#endif
+
+
+#endif /* CONFIG_AP_MODE */
+
+	return _FAIL;
+
+}
+
+#if defined(CONFIG_LAYER2_ROAMING) && defined(CONFIG_RTW_80211K)
+void rtw_roam_nb_discover(_adapter *padapter, u8 bfroce)
+{
+	struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
+	struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
+	struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);	
+	struct sta_priv *pstapriv = &padapter->stapriv;
+	struct sta_info *psta;
+	u8 nb_req_issue = _FALSE;
+
+	if (!check_fwstate(pmlmepriv, _FW_LINKED))
+		return;
+
+	if (!rtw_chk_roam_flags(padapter, RTW_ROAM_ACTIVE))
+		return;
+
+	psta = rtw_get_stainfo(pstapriv, pmlmeinfo->network.MacAddress);
+	if (!psta)
+		return;
+	
+	if (bfroce || (!pmlmepriv->nb_info.nb_rpt_is_same))
+		nb_req_issue = _TRUE;
+	
+	if (nb_req_issue && (psta->rm_en_cap[0] & RTW_RRM_NB_RPT_EN)) 
+		rm_add_nb_req(padapter, psta);
+}
+#endif
+
+unsigned int OnAssocRsp(_adapter *padapter, union recv_frame *precv_frame)
+{
+	uint i;
+	int res;
+	unsigned short	status;
+	PNDIS_802_11_VARIABLE_IEs	pIE;
+	struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
+	struct mlme_ext_priv	*pmlmeext = &padapter->mlmeextpriv;
+	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
+	/* WLAN_BSSID_EX 		*cur_network = &(pmlmeinfo->network); */
+	u8 *pframe = precv_frame->u.hdr.rx_data;
+	uint pkt_len = precv_frame->u.hdr.len;
+#ifdef CONFIG_WAPI_SUPPORT
+	PNDIS_802_11_VARIABLE_IEs	pWapiIE = NULL;
+#endif
+
+	RTW_INFO("%s\n", __FUNCTION__);
+
+	/* check A1 matches or not */
+	if (!_rtw_memcmp(adapter_mac_addr(padapter), get_da(pframe), ETH_ALEN))
+		return _SUCCESS;
+
+	if (!(pmlmeinfo->state & (WIFI_FW_AUTH_SUCCESS | WIFI_FW_ASSOC_STATE)) || pmlmeext->join_abort)
+		return _SUCCESS;
+
+	if (pmlmeinfo->state & WIFI_FW_ASSOC_SUCCESS)
+		return _SUCCESS;
+
+	_cancel_timer_ex(&pmlmeext->link_timer);
+
+	/* status */
+	status = le16_to_cpu(*(unsigned short *)(pframe + WLAN_HDR_A3_LEN + 2));
+	if (status > 0) {
+		RTW_INFO("assoc reject, status code: %d\n", status);
+		pmlmeinfo->state = WIFI_FW_NULL_STATE;
+		res = -4;
+		goto report_assoc_result;
+	}
+
+	/* get capabilities */
+	pmlmeinfo->capability = le16_to_cpu(*(unsigned short *)(pframe + WLAN_HDR_A3_LEN));
+
+	/* set slot time */
+	pmlmeinfo->slotTime = (pmlmeinfo->capability & BIT(10)) ? 9 : 20;
+
+	/* AID */
+	res = pmlmeinfo->aid = (int)(le16_to_cpu(*(unsigned short *)(pframe + WLAN_HDR_A3_LEN + 4)) & 0x3fff);
+
+	/* following are moved to join event callback function */
+	/* to handle HT, WMM, rate adaptive, update MAC reg */
+	/* for not to handle the synchronous IO in the tasklet */
+	for (i = (6 + WLAN_HDR_A3_LEN); i < pkt_len;) {
+		pIE = (PNDIS_802_11_VARIABLE_IEs)(pframe + i);
+
+		switch (pIE->ElementID) {
+		case _VENDOR_SPECIFIC_IE_:
+			if (_rtw_memcmp(pIE->data, WMM_PARA_OUI, 6))	/* WMM */
+				WMM_param_handler(padapter, pIE);
+#if defined(CONFIG_P2P) && defined(CONFIG_WFD)
+			else if (_rtw_memcmp(pIE->data, WFD_OUI, 4))		/* WFD */
+				rtw_process_wfd_ie(padapter, (u8 *)pIE, pIE->Length, __func__);
+#endif
+			break;
+
+#ifdef CONFIG_WAPI_SUPPORT
+		case _WAPI_IE_:
+			pWapiIE = pIE;
+			break;
+#endif
+
+		case _HT_CAPABILITY_IE_:	/* HT caps */
+			HT_caps_handler(padapter, pIE);
+#ifdef ROKU_PRIVATE
+			HT_caps_handler_infra_ap(padapter, pIE);
+#endif /* ROKU_PRIVATE */
+			break;
+
+		case _HT_EXTRA_INFO_IE_:	/* HT info */
+			HT_info_handler(padapter, pIE);
+			break;
+
+#ifdef CONFIG_80211AC_VHT
+		case EID_VHTCapability:
+			VHT_caps_handler(padapter, pIE);
+#ifdef ROKU_PRIVATE
+			VHT_caps_handler_infra_ap(padapter, pIE);
+#endif /* ROKU_PRIVATE */
+			break;
+
+		case EID_VHTOperation:
+			VHT_operation_handler(padapter, pIE);
+			break;
+#endif
+
+		case _ERPINFO_IE_:
+			ERP_IE_handler(padapter, pIE);
+			break;
+#ifdef CONFIG_TDLS
+		case _EXT_CAP_IE_:
+			if (check_ap_tdls_prohibited(pIE->data, pIE->Length) == _TRUE)
+				padapter->tdlsinfo.ap_prohibited = _TRUE;
+			if (check_ap_tdls_ch_switching_prohibited(pIE->data, pIE->Length) == _TRUE)
+				padapter->tdlsinfo.ch_switch_prohibited = _TRUE;
+			break;
+#endif /* CONFIG_TDLS */
+
+#ifdef CONFIG_RTW_80211K
+		case _EID_RRM_EN_CAP_IE_:
+			RM_IE_handler(padapter, pIE);
+			break;
+#endif
+
+#ifdef ROKU_PRIVATE
+		/* Infra mode, used to store AP's info , Parse the supported rates from AssocRsp */
+		case _SUPPORTEDRATES_IE_:
+			Supported_rate_infra_ap(padapter, pIE);
+			break;
+
+		case _EXT_SUPPORTEDRATES_IE_:
+			Extended_Supported_rate_infra_ap(padapter, pIE);
+			break;
+#endif /* ROKU_PRIVATE */
+		default:
+			break;
+		}
+
+		i += (pIE->Length + 2);
+	}
+
+#ifdef CONFIG_WAPI_SUPPORT
+	rtw_wapi_on_assoc_ok(padapter, pIE);
+#endif
+
+	pmlmeinfo->state &= (~WIFI_FW_ASSOC_STATE);
+	pmlmeinfo->state |= WIFI_FW_ASSOC_SUCCESS;
+
+	/* Update Basic Rate Table for spec, 2010-12-28 , by thomas */
+	UpdateBrateTbl(padapter, pmlmeinfo->network.SupportedRates);
+
+report_assoc_result:
+	if (res > 0)
+		rtw_buf_update(&pmlmepriv->assoc_rsp, &pmlmepriv->assoc_rsp_len, pframe, pkt_len);
+	else
+		rtw_buf_free(&pmlmepriv->assoc_rsp, &pmlmepriv->assoc_rsp_len);
+
+	report_join_res(padapter, res, status);
+
+#if defined(CONFIG_LAYER2_ROAMING) && defined(CONFIG_RTW_80211K)
+	rtw_roam_nb_discover(padapter, _TRUE);
+#endif
+	return _SUCCESS;
+}
+
+unsigned int OnDeAuth(_adapter *padapter, union recv_frame *precv_frame)
+{
+	unsigned short	reason;
+	struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
+	struct mlme_ext_priv	*pmlmeext = &padapter->mlmeextpriv;
+	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
+	u8 *pframe = precv_frame->u.hdr.rx_data;
+#ifdef CONFIG_P2P
+	struct wifidirect_info *pwdinfo = &(padapter->wdinfo);
+#endif /* CONFIG_P2P */
+
+	/* check A3 */
+	if (!(_rtw_memcmp(GetAddr3Ptr(pframe), get_my_bssid(&pmlmeinfo->network), ETH_ALEN)))
+		return _SUCCESS;
+
+	RTW_INFO(FUNC_ADPT_FMT" - Start to Disconnect\n", FUNC_ADPT_ARG(padapter));
+
+#ifdef CONFIG_P2P
+	if (pwdinfo->rx_invitereq_info.scan_op_ch_only) {
+		_cancel_timer_ex(&pwdinfo->reset_ch_sitesurvey);
+		_set_timer(&pwdinfo->reset_ch_sitesurvey, 10);
+	}
+#endif /* CONFIG_P2P */
+
+	reason = le16_to_cpu(*(unsigned short *)(pframe + WLAN_HDR_A3_LEN));
+
+#ifdef CONFIG_AP_MODE
+	if (MLME_IS_AP(padapter)) {
+		_irqL irqL;
+		struct sta_info *psta;
+		struct sta_priv *pstapriv = &padapter->stapriv;
+
+		/* _enter_critical_bh(&(pstapriv->sta_hash_lock), &irqL);		 */
+		/* rtw_free_stainfo(padapter, psta); */
+		/* _exit_critical_bh(&(pstapriv->sta_hash_lock), &irqL);		 */
+
+		RTW_PRINT(FUNC_ADPT_FMT" reason=%u, ta=%pM\n"
+			, FUNC_ADPT_ARG(padapter), reason, get_addr2_ptr(pframe));
+
+		psta = rtw_get_stainfo(pstapriv, get_addr2_ptr(pframe));
+		if (psta) {
+			u8 updated = _FALSE;
+
+			_enter_critical_bh(&pstapriv->asoc_list_lock, &irqL);
+			if (rtw_is_list_empty(&psta->asoc_list) == _FALSE) {
+				rtw_list_delete(&psta->asoc_list);
+				pstapriv->asoc_list_cnt--;
+				updated = ap_free_sta(padapter, psta, _FALSE, reason, _TRUE);
+
+			}
+			_exit_critical_bh(&pstapriv->asoc_list_lock, &irqL);
+
+			associated_clients_update(padapter, updated, STA_INFO_UPDATE_ALL);
+		}
+
+
+		return _SUCCESS;
+	} else
+#endif
+	if (!MLME_IS_MESH(padapter)) {
+		int	ignore_received_deauth = 0;
+
+		/*	Commented by Albert 20130604 */
+		/*	Before sending the auth frame to start the STA/GC mode connection with AP/GO,  */
+		/*	we will send the deauth first. */
+		/*	However, the Win8.1 with BRCM Wi-Fi will send the deauth with reason code 6 to us after receieving our deauth. */
+		/*	Added the following code to avoid this case. */
+		if ((pmlmeinfo->state & WIFI_FW_AUTH_STATE) ||
+		    (pmlmeinfo->state & WIFI_FW_ASSOC_STATE)) {
+			if (reason == WLAN_REASON_CLASS2_FRAME_FROM_NONAUTH_STA)
+				ignore_received_deauth = 1;
+			else if (WLAN_REASON_PREV_AUTH_NOT_VALID == reason) {
+				/* TODO: 802.11r */
+				ignore_received_deauth = 1;
+			}
+		}
+
+		RTW_PRINT(FUNC_ADPT_FMT" reason=%u, ta=%pM, ignore=%d\n"
+			, FUNC_ADPT_ARG(padapter), reason, get_addr2_ptr(pframe), ignore_received_deauth);
+
+		if (0 == ignore_received_deauth)
+			receive_disconnect(padapter, get_addr2_ptr(pframe), reason, _FALSE);
+	}
+	pmlmepriv->LinkDetectInfo.bBusyTraffic = _FALSE;
+	return _SUCCESS;
+
+}
+
+unsigned int OnDisassoc(_adapter *padapter, union recv_frame *precv_frame)
+{
+	unsigned short	reason;
+	struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
+	struct mlme_ext_priv	*pmlmeext = &padapter->mlmeextpriv;
+	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
+	u8 *pframe = precv_frame->u.hdr.rx_data;
+#ifdef CONFIG_P2P
+	struct wifidirect_info *pwdinfo = &(padapter->wdinfo);
+#endif /* CONFIG_P2P */
+
+	/* check A3 */
+	if (!(_rtw_memcmp(GetAddr3Ptr(pframe), get_my_bssid(&pmlmeinfo->network), ETH_ALEN)))
+		return _SUCCESS;
+
+	RTW_INFO(FUNC_ADPT_FMT" - Start to Disconnect\n", FUNC_ADPT_ARG(padapter));
+
+#ifdef CONFIG_P2P
+	if (pwdinfo->rx_invitereq_info.scan_op_ch_only) {
+		_cancel_timer_ex(&pwdinfo->reset_ch_sitesurvey);
+		_set_timer(&pwdinfo->reset_ch_sitesurvey, 10);
+	}
+#endif /* CONFIG_P2P */
+
+	reason = le16_to_cpu(*(unsigned short *)(pframe + WLAN_HDR_A3_LEN));
+
+#ifdef CONFIG_AP_MODE
+	if (MLME_IS_AP(padapter)) {
+		_irqL irqL;
+		struct sta_info *psta;
+		struct sta_priv *pstapriv = &padapter->stapriv;
+
+		/* _enter_critical_bh(&(pstapriv->sta_hash_lock), &irqL);	 */
+		/* rtw_free_stainfo(padapter, psta); */
+		/* _exit_critical_bh(&(pstapriv->sta_hash_lock), &irqL);		 */
+
+		RTW_PRINT(FUNC_ADPT_FMT" reason=%u, ta=%pM\n"
+			, FUNC_ADPT_ARG(padapter), reason, get_addr2_ptr(pframe));
+
+		psta = rtw_get_stainfo(pstapriv, get_addr2_ptr(pframe));
+		if (psta) {
+			u8 updated = _FALSE;
+
+			_enter_critical_bh(&pstapriv->asoc_list_lock, &irqL);
+			if (rtw_is_list_empty(&psta->asoc_list) == _FALSE) {
+				rtw_list_delete(&psta->asoc_list);
+				pstapriv->asoc_list_cnt--;
+				updated = ap_free_sta(padapter, psta, _FALSE, reason, _TRUE);
+
+			}
+			_exit_critical_bh(&pstapriv->asoc_list_lock, &irqL);
+
+			associated_clients_update(padapter, updated, STA_INFO_UPDATE_ALL);
+		}
+
+		return _SUCCESS;
+	} else
+#endif
+	if (!MLME_IS_MESH(padapter)) {
+		RTW_PRINT(FUNC_ADPT_FMT" reason=%u, ta=%pM\n"
+			, FUNC_ADPT_ARG(padapter), reason, get_addr2_ptr(pframe));
+
+		receive_disconnect(padapter, get_addr2_ptr(pframe), reason, _FALSE);
+	}
+	pmlmepriv->LinkDetectInfo.bBusyTraffic = _FALSE;
+	return _SUCCESS;
+
+}
+
+unsigned int OnAtim(_adapter *padapter, union recv_frame *precv_frame)
+{
+	RTW_INFO("%s\n", __FUNCTION__);
+	return _SUCCESS;
+}
+
+unsigned int on_action_spct_ch_switch(_adapter *padapter, struct sta_info *psta, u8 *ies, uint ies_len)
+{
+	unsigned int ret = _FAIL;
+	struct mlme_ext_priv *mlmeext = &padapter->mlmeextpriv;
+	struct mlme_ext_info	*pmlmeinfo = &(mlmeext->mlmext_info);
+
+	if (!(pmlmeinfo->state & WIFI_FW_ASSOC_SUCCESS)) {
+		ret = _SUCCESS;
+		goto exit;
+	}
+
+	if ((pmlmeinfo->state & 0x03) == WIFI_FW_STATION_STATE) {
+
+		int ch_switch_mode = -1, ch = -1, ch_switch_cnt = -1;
+		int ch_offset = -1;
+		u8 bwmode;
+		struct ieee80211_info_element *ie;
+
+		RTW_INFO(FUNC_NDEV_FMT" from "MAC_FMT"\n",
+			FUNC_NDEV_ARG(padapter->pnetdev), MAC_ARG(psta->cmn.mac_addr));
+
+		for_each_ie(ie, ies, ies_len) {
+			if (ie->id == WLAN_EID_CHANNEL_SWITCH) {
+				ch_switch_mode = ie->data[0];
+				ch = ie->data[1];
+				ch_switch_cnt = ie->data[2];
+				RTW_INFO("ch_switch_mode:%d, ch:%d, ch_switch_cnt:%d\n",
+					 ch_switch_mode, ch, ch_switch_cnt);
+			} else if (ie->id == WLAN_EID_SECONDARY_CHANNEL_OFFSET) {
+				ch_offset = secondary_ch_offset_to_hal_ch_offset(ie->data[0]);
+				RTW_INFO("ch_offset:%d\n", ch_offset);
+			}
+		}
+
+		if (ch == -1)
+			return _SUCCESS;
+
+		if (ch_offset == -1)
+			bwmode = mlmeext->cur_bwmode;
+		else
+			bwmode = (ch_offset == HAL_PRIME_CHNL_OFFSET_DONT_CARE) ?
+				 CHANNEL_WIDTH_20 : CHANNEL_WIDTH_40;
+
+		ch_offset = (ch_offset == -1) ? mlmeext->cur_ch_offset : ch_offset;
+
+		/* todo:
+		 * 1. the decision of channel switching
+		 * 2. things after channel switching
+		 */
+
+		ret = rtw_set_chbw_cmd(padapter, ch, bwmode, ch_offset, 0);
+	}
+
+exit:
+	return ret;
+}
+
+unsigned int on_action_spct(_adapter *padapter, union recv_frame *precv_frame)
+{
+	unsigned int ret = _FAIL;
+	struct sta_info *psta = NULL;
+	struct sta_priv *pstapriv = &padapter->stapriv;
+	u8 *pframe = precv_frame->u.hdr.rx_data;
+	uint frame_len = precv_frame->u.hdr.len;
+	u8 *frame_body = (u8 *)(pframe + sizeof(struct rtw_ieee80211_hdr_3addr));
+	u8 category;
+	u8 action;
+
+	psta = rtw_get_stainfo(pstapriv, get_addr2_ptr(pframe));
+
+	if (!psta)
+		goto exit;
+
+	category = frame_body[0];
+	if (category != RTW_WLAN_CATEGORY_SPECTRUM_MGMT)
+		goto exit;
+
+	action = frame_body[1];
+
+	RTW_INFO(FUNC_ADPT_FMT" action:%u\n", FUNC_ADPT_ARG(padapter), action);
+
+	switch (action) {
+	case RTW_WLAN_ACTION_SPCT_MSR_REQ:
+	case RTW_WLAN_ACTION_SPCT_MSR_RPRT:
+	case RTW_WLAN_ACTION_SPCT_TPC_REQ:
+	case RTW_WLAN_ACTION_SPCT_TPC_RPRT:
+		break;
+	case RTW_WLAN_ACTION_SPCT_CHL_SWITCH:
+#ifdef CONFIG_SPCT_CH_SWITCH
+		ret = on_action_spct_ch_switch(padapter, psta
+				, frame_body + 2, frame_len - (frame_body - pframe) - 2);
+#elif defined(CONFIG_DFS)
+		if (MLME_IS_STA(padapter) && MLME_IS_ASOC(padapter)) {
+			process_csa_ie(padapter
+				, frame_body + 2, frame_len - (frame_body - pframe) - 2);
+		}
+#endif
+		break;
+	default:
+		break;
+	}
+
+exit:
+	return ret;
+}
+
+unsigned int OnAction_qos(_adapter *padapter, union recv_frame *precv_frame)
+{
+	return _SUCCESS;
+}
+
+unsigned int OnAction_dls(_adapter *padapter, union recv_frame *precv_frame)
+{
+	return _SUCCESS;
+}
+
+#ifdef CONFIG_RTW_WNM
+unsigned int on_action_wnm(_adapter *adapter, union recv_frame *rframe)
+{
+	unsigned int ret = _FAIL;
+	struct sta_info *sta = NULL;
+	struct mlme_priv *pmlmepriv = &(adapter->mlmepriv);
+	struct sta_priv *stapriv = &(adapter->stapriv);
+	u8 *frame = rframe->u.hdr.rx_data;
+	u32 frame_len = rframe->u.hdr.len;
+	u8 *frame_body = (u8 *)(frame + sizeof(struct rtw_ieee80211_hdr_3addr));
+	u32 frame_body_len = frame_len - sizeof(struct rtw_ieee80211_hdr_3addr);	
+	u8 category, action;
+	int cnt = 0;
+	char msg[16];
+
+	sta = rtw_get_stainfo(stapriv, get_addr2_ptr(frame));
+	if (!sta)
+		goto exit;
+
+	category = frame_body[0];
+	if (category != RTW_WLAN_CATEGORY_WNM)
+		goto exit;
+
+	action = frame_body[1];
+
+	switch (action) {
+#ifdef CONFIG_RTW_80211R
+	case RTW_WLAN_ACTION_WNM_BTM_REQ:
+		if (check_fwstate(pmlmepriv, WIFI_STATION_STATE) == _TRUE) {
+			RTW_INFO("WNM: RTW_WLAN_ACTION_WNM_BTM_REQ recv.\n");
+			rtw_wnm_process_btm_req(adapter, frame_body, frame_body_len);
+		}
+		ret = _SUCCESS;
+		break;
+#endif		
+	default:
+		#ifdef CONFIG_IOCTL_CFG80211
+		cnt += sprintf((msg + cnt), "ACT_WNM %u", action);
+		rtw_cfg80211_rx_action(adapter, rframe, msg);
+		#endif
+		ret = _SUCCESS;
+		break;
+	}
+
+exit:
+	return ret;
+}
+#endif /* CONFIG_RTW_WNM */
+
+/**
+ * rtw_rx_ampdu_size - Get the target RX AMPDU buffer size for the specific @adapter
+ * @adapter: the adapter to get target RX AMPDU buffer size
+ *
+ * Returns: the target RX AMPDU buffer size
+ */
+u8 rtw_rx_ampdu_size(_adapter *adapter)
+{
+	u8 size;
+	HT_CAP_AMPDU_FACTOR max_rx_ampdu_factor;
+
+#ifdef CONFIG_BT_COEXIST
+	if (rtw_btcoex_IsBTCoexCtrlAMPDUSize(adapter) == _TRUE) {
+		size = rtw_btcoex_GetAMPDUSize(adapter);
+		goto exit;
+	}
+#endif
+
+	/* for scan */
+	if (!mlmeext_chk_scan_state(&adapter->mlmeextpriv, SCAN_DISABLE)
+	    && !mlmeext_chk_scan_state(&adapter->mlmeextpriv, SCAN_COMPLETE)
+	    && adapter->mlmeextpriv.sitesurvey_res.rx_ampdu_size != RX_AMPDU_SIZE_INVALID
+	   ) {
+		size = adapter->mlmeextpriv.sitesurvey_res.rx_ampdu_size;
+		goto exit;
+	}
+
+	/* default value based on max_rx_ampdu_factor */
+	if (adapter->driver_rx_ampdu_factor != 0xFF)
+		max_rx_ampdu_factor = (HT_CAP_AMPDU_FACTOR)adapter->driver_rx_ampdu_factor;
+	else
+		rtw_hal_get_def_var(adapter, HW_VAR_MAX_RX_AMPDU_FACTOR, &max_rx_ampdu_factor);
+	
+	/* In Maximum A-MPDU Length Exponent subfield of A-MPDU Parameters field of HT Capabilities element,
+		the unit of max_rx_ampdu_factor are octets. 8K, 16K, 32K, 64K is right.
+		But the buffer size subfield of Block Ack Parameter Set field in ADDBA action frame indicates
+		the number of buffers available for this particular TID. Each buffer is equal to max. size of 
+		MSDU or AMSDU. 
+		The size variable means how many MSDUs or AMSDUs, it's not Kbytes.
+	*/
+	if (MAX_AMPDU_FACTOR_64K == max_rx_ampdu_factor)
+		size = 64;
+	else if (MAX_AMPDU_FACTOR_32K == max_rx_ampdu_factor)
+		size = 32;
+	else if (MAX_AMPDU_FACTOR_16K == max_rx_ampdu_factor)
+		size = 16;
+	else if (MAX_AMPDU_FACTOR_8K == max_rx_ampdu_factor)
+		size = 8;
+	else
+		size = 64;
+
+exit:
+
+	if (size > 127)
+		size = 127;
+
+	return size;
+}
+
+/**
+ * rtw_rx_ampdu_is_accept - Get the permission if RX AMPDU should be set up for the specific @adapter
+ * @adapter: the adapter to get the permission if RX AMPDU should be set up
+ *
+ * Returns: accept or not
+ */
+bool rtw_rx_ampdu_is_accept(_adapter *adapter)
+{
+	bool accept;
+
+	if (adapter->fix_rx_ampdu_accept != RX_AMPDU_ACCEPT_INVALID) {
+		accept = adapter->fix_rx_ampdu_accept;
+		goto exit;
+	}
+
+#ifdef CONFIG_BT_COEXIST
+	if (rtw_btcoex_IsBTCoexRejectAMPDU(adapter) == _TRUE) {
+		accept = _FALSE;
+		goto exit;
+	}
+#endif
+
+	/* for scan */
+	if (!mlmeext_chk_scan_state(&adapter->mlmeextpriv, SCAN_DISABLE)
+	    && !mlmeext_chk_scan_state(&adapter->mlmeextpriv, SCAN_COMPLETE)
+	    && adapter->mlmeextpriv.sitesurvey_res.rx_ampdu_accept != RX_AMPDU_ACCEPT_INVALID
+	   ) {
+		accept = adapter->mlmeextpriv.sitesurvey_res.rx_ampdu_accept;
+		goto exit;
+	}
+
+	/* default value for other cases */
+	accept = adapter->mlmeextpriv.mlmext_info.bAcceptAddbaReq;
+
+exit:
+	return accept;
+}
+
+/**
+ * rtw_rx_ampdu_set_size - Set the target RX AMPDU buffer size for the specific @adapter and specific @reason
+ * @adapter: the adapter to set target RX AMPDU buffer size
+ * @size: the target RX AMPDU buffer size to set
+ * @reason: reason for the target RX AMPDU buffer size setting
+ *
+ * Returns: whether the target RX AMPDU buffer size is changed
+ */
+bool rtw_rx_ampdu_set_size(_adapter *adapter, u8 size, u8 reason)
+{
+	bool is_adj = _FALSE;
+	struct mlme_ext_priv *mlmeext;
+	struct mlme_ext_info *mlmeinfo;
+
+	mlmeext = &adapter->mlmeextpriv;
+	mlmeinfo = &mlmeext->mlmext_info;
+
+	if (reason == RX_AMPDU_DRV_FIXED) {
+		if (adapter->fix_rx_ampdu_size != size) {
+			adapter->fix_rx_ampdu_size = size;
+			is_adj = _TRUE;
+			RTW_INFO(FUNC_ADPT_FMT" fix_rx_ampdu_size:%u\n", FUNC_ADPT_ARG(adapter), size);
+		}
+	} else if (reason == RX_AMPDU_DRV_SCAN) {
+		struct ss_res *ss = &adapter->mlmeextpriv.sitesurvey_res;
+
+		if (ss->rx_ampdu_size != size) {
+			ss->rx_ampdu_size = size;
+			is_adj = _TRUE;
+			RTW_INFO(FUNC_ADPT_FMT" ss.rx_ampdu_size:%u\n", FUNC_ADPT_ARG(adapter), size);
+		}
+	}
+
+	return is_adj;
+}
+
+/**
+ * rtw_rx_ampdu_set_accept - Set the permission if RX AMPDU should be set up for the specific @adapter and specific @reason
+ * @adapter: the adapter to set if RX AMPDU should be set up
+ * @accept: if RX AMPDU should be set up
+ * @reason: reason for the permission if RX AMPDU should be set up
+ *
+ * Returns: whether the permission if RX AMPDU should be set up is changed
+ */
+bool rtw_rx_ampdu_set_accept(_adapter *adapter, u8 accept, u8 reason)
+{
+	bool is_adj = _FALSE;
+	struct mlme_ext_priv *mlmeext;
+	struct mlme_ext_info *mlmeinfo;
+
+	mlmeext = &adapter->mlmeextpriv;
+	mlmeinfo = &mlmeext->mlmext_info;
+
+	if (reason == RX_AMPDU_DRV_FIXED) {
+		if (adapter->fix_rx_ampdu_accept != accept) {
+			adapter->fix_rx_ampdu_accept = accept;
+			is_adj = _TRUE;
+			RTW_INFO(FUNC_ADPT_FMT" fix_rx_ampdu_accept:%u\n", FUNC_ADPT_ARG(adapter), accept);
+		}
+	} else if (reason == RX_AMPDU_DRV_SCAN) {
+		if (adapter->mlmeextpriv.sitesurvey_res.rx_ampdu_accept != accept) {
+			adapter->mlmeextpriv.sitesurvey_res.rx_ampdu_accept = accept;
+			is_adj = _TRUE;
+			RTW_INFO(FUNC_ADPT_FMT" ss.rx_ampdu_accept:%u\n", FUNC_ADPT_ARG(adapter), accept);
+		}
+	}
+
+	return is_adj;
+}
+
+/**
+ * rx_ampdu_apply_sta_tid - Apply RX AMPDU setting to the specific @sta and @tid
+ * @adapter: the adapter to which @sta belongs
+ * @sta: the sta to be checked
+ * @tid: the tid to be checked
+ * @accept: the target permission if RX AMPDU should be set up
+ * @size: the target RX AMPDU buffer size
+ *
+ * Returns:
+ * 0: no canceled
+ * 1: canceled by no permission
+ * 2: canceled by different buffer size
+ * 3: canceled by potential mismatched status
+ *
+ * Blocking function, may sleep
+ */
+u8 rx_ampdu_apply_sta_tid(_adapter *adapter, struct sta_info *sta, u8 tid, u8 accept, u8 size)
+{
+	u8 ret = 0;
+	struct recv_reorder_ctrl *reorder_ctl = &sta->recvreorder_ctrl[tid];
+
+	if (reorder_ctl->enable == _FALSE) {
+		if (reorder_ctl->ampdu_size != RX_AMPDU_SIZE_INVALID) {
+			send_delba_sta_tid_wait_ack(adapter, 0, sta, tid, 1);
+			ret = 3;
+		}
+		goto exit;
+	}
+
+	if (accept == _FALSE) {
+		send_delba_sta_tid_wait_ack(adapter, 0, sta, tid, 0);
+		ret = 1;
+	} else if (reorder_ctl->ampdu_size != size) {
+		send_delba_sta_tid_wait_ack(adapter, 0, sta, tid, 0);
+		ret = 2;
+	}
+
+exit:
+	return ret;
+}
+
+u8 rx_ampdu_size_sta_limit(_adapter *adapter, struct sta_info *sta)
+{
+	u8 sz_limit = 0xFF;
+
+#ifdef CONFIG_80211N_HT
+	struct registry_priv *regsty = adapter_to_regsty(adapter);
+	struct mlme_priv *mlme = &adapter->mlmepriv;
+	struct mlme_ext_info *mlmeinfo = &adapter->mlmeextpriv.mlmext_info;
+	s8 nss = -1;
+	u8 bw = rtw_min(sta->cmn.bw_mode, adapter->mlmeextpriv.cur_bwmode);
+
+	#ifdef CONFIG_80211AC_VHT
+	if (is_supported_vht(sta->wireless_mode)) {
+		nss = rtw_min(rtw_vht_mcsmap_to_nss(mlme->vhtpriv.vht_mcs_map)
+				, rtw_vht_mcsmap_to_nss(sta->vhtpriv.vht_mcs_map));
+	} else
+	#endif
+	if (is_supported_ht(sta->wireless_mode)) {
+		nss = rtw_min(rtw_ht_mcsset_to_nss(mlmeinfo->HT_caps.u.HT_cap_element.MCS_rate)
+				, rtw_ht_mcsset_to_nss(sta->htpriv.ht_cap.supp_mcs_set));
+	}
+
+	if (nss >= 1)
+		sz_limit = regsty->rx_ampdu_sz_limit_by_nss_bw[nss - 1][bw];
+#endif /* CONFIG_80211N_HT */
+
+	return sz_limit;
+}
+
+/**
+ * rx_ampdu_apply_sta - Apply RX AMPDU setting to the specific @sta
+ * @adapter: the adapter to which @sta belongs
+ * @sta: the sta to be checked
+ * @accept: the target permission if RX AMPDU should be set up
+ * @size: the target RX AMPDU buffer size
+ *
+ * Returns: number of the RX AMPDU assciation canceled for applying current target setting
+ *
+ * Blocking function, may sleep
+ */
+u8 rx_ampdu_apply_sta(_adapter *adapter, struct sta_info *sta, u8 accept, u8 size)
+{
+	u8 change_cnt = 0;
+	int i;
+
+	for (i = 0; i < TID_NUM; i++) {
+		if (rx_ampdu_apply_sta_tid(adapter, sta, i, accept, size) != 0)
+			change_cnt++;
+	}
+
+	return change_cnt;
+}
+
+/**
+ * rtw_rx_ampdu_apply - Apply the current target RX AMPDU setting for the specific @adapter
+ * @adapter: the adapter to be applied
+ *
+ * Returns: number of the RX AMPDU assciation canceled for applying current target setting
+ */
+u16 rtw_rx_ampdu_apply(_adapter *adapter)
+{
+	u16 adj_cnt = 0;
+	struct sta_info *sta;
+	u8 accept = rtw_rx_ampdu_is_accept(adapter);
+	u8 size;
+
+	if (adapter->fix_rx_ampdu_size != RX_AMPDU_SIZE_INVALID)
+		size = adapter->fix_rx_ampdu_size;
+	else
+		size = rtw_rx_ampdu_size(adapter);
+
+	if (MLME_IS_STA(adapter)) {
+		sta = rtw_get_stainfo(&adapter->stapriv, get_bssid(&adapter->mlmepriv));
+		if (sta) {
+			u8 sta_size = size;
+
+			if (adapter->fix_rx_ampdu_size == RX_AMPDU_SIZE_INVALID)
+				sta_size = rtw_min(size, rx_ampdu_size_sta_limit(adapter, sta));
+			adj_cnt += rx_ampdu_apply_sta(adapter, sta, accept, sta_size);
+		}
+		/* TODO: TDLS peer */
+
+	} else if (MLME_IS_AP(adapter) || MLME_IS_MESH(adapter)) {
+		_irqL irqL;
+		_list *phead, *plist;
+		u8 peer_num = 0;
+		char peers[NUM_STA];
+		struct sta_priv *pstapriv = &adapter->stapriv;
+		int i;
+
+		_enter_critical_bh(&pstapriv->asoc_list_lock, &irqL);
+
+		phead = &pstapriv->asoc_list;
+		plist = get_next(phead);
+
+		while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) {
+			int stainfo_offset;
+
+			sta = LIST_CONTAINOR(plist, struct sta_info, asoc_list);
+			plist = get_next(plist);
+
+			stainfo_offset = rtw_stainfo_offset(pstapriv, sta);
+			if (stainfo_offset_valid(stainfo_offset))
+				peers[peer_num++] = stainfo_offset;
+		}
+
+		_exit_critical_bh(&pstapriv->asoc_list_lock, &irqL);
+
+		for (i = 0; i < peer_num; i++) {
+			sta = rtw_get_stainfo_by_offset(pstapriv, peers[i]);
+			if (sta) {
+				u8 sta_size = size;
+
+				if (adapter->fix_rx_ampdu_size == RX_AMPDU_SIZE_INVALID)
+					sta_size = rtw_min(size, rx_ampdu_size_sta_limit(adapter, sta));
+				adj_cnt += rx_ampdu_apply_sta(adapter, sta, accept, sta_size);
+			}
+		}
+	}
+
+	/* TODO: ADHOC */
+
+	return adj_cnt;
+}
+
+unsigned int OnAction_back(_adapter *padapter, union recv_frame *precv_frame)
+{
+	u8 *addr;
+	struct sta_info *psta = NULL;
+	struct recv_reorder_ctrl *preorder_ctrl;
+	unsigned char		*frame_body;
+	unsigned char		category, action;
+	unsigned short	tid, status, reason_code = 0;
+	struct mlme_ext_priv	*pmlmeext = &padapter->mlmeextpriv;
+	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
+	u8 *pframe = precv_frame->u.hdr.rx_data;
+	struct sta_priv *pstapriv = &padapter->stapriv;
+	struct registry_priv *pregpriv = &padapter->registrypriv;
+
+#ifdef CONFIG_80211N_HT
+
+	RTW_INFO("%s\n", __FUNCTION__);
+
+	/* check RA matches or not	 */
+	if (!_rtw_memcmp(adapter_mac_addr(padapter), GetAddr1Ptr(pframe), ETH_ALEN))
+		return _SUCCESS;
+
+#if 0
+	/* check A1 matches or not */
+	if (!_rtw_memcmp(adapter_mac_addr(padapter), get_da(pframe), ETH_ALEN))
+		return _SUCCESS;
+#endif
+
+	if ((pmlmeinfo->state & 0x03) != WIFI_FW_AP_STATE)
+		if (!(pmlmeinfo->state & WIFI_FW_ASSOC_SUCCESS))
+			return _SUCCESS;
+
+	addr = get_addr2_ptr(pframe);
+	psta = rtw_get_stainfo(pstapriv, addr);
+
+	if (psta == NULL)
+		return _SUCCESS;
+
+	frame_body = (unsigned char *)(pframe + sizeof(struct rtw_ieee80211_hdr_3addr));
+
+	category = frame_body[0];
+	if (category == RTW_WLAN_CATEGORY_BACK) { /* representing Block Ack */
+#ifdef CONFIG_TDLS
+		if ((psta->tdls_sta_state & TDLS_LINKED_STATE) &&
+		    (psta->htpriv.ht_option == _TRUE) &&
+		    (psta->htpriv.ampdu_enable == _TRUE))
+			RTW_INFO("Recv [%s] from direc link\n", __FUNCTION__);
+		else
+#endif /* CONFIG_TDLS */
+			if (!pmlmeinfo->HT_enable)
+				return _SUCCESS;
+
+		action = frame_body[1];
+		RTW_INFO("%s, action=%d\n", __FUNCTION__, action);
+		switch (action) {
+		case RTW_WLAN_ACTION_ADDBA_REQ: /* ADDBA request */
+
+			_rtw_memcpy(&(pmlmeinfo->ADDBA_req), &(frame_body[2]), sizeof(struct ADDBA_request));
+			/* process_addba_req(padapter, (u8*)&(pmlmeinfo->ADDBA_req), GetAddr3Ptr(pframe)); */
+			process_addba_req(padapter, (u8 *)&(pmlmeinfo->ADDBA_req), addr);
+
+			break;
+
+		case RTW_WLAN_ACTION_ADDBA_RESP: /* ADDBA response */
+
+			/* status = frame_body[3] | (frame_body[4] << 8); */ /* endian issue */
+			status = RTW_GET_LE16(&frame_body[3]);
+			tid = ((frame_body[5] >> 2) & 0x7);
+			if (status == 0) {
+				/* successful					 */
+				RTW_INFO("agg_enable for TID=%d\n", tid);
+				psta->htpriv.agg_enable_bitmap |= 1 << tid;
+				psta->htpriv.candidate_tid_bitmap &= ~BIT(tid);
+				/* amsdu in ampdu */
+				if (pregpriv->tx_ampdu_amsdu == 0)
+					psta->htpriv.tx_amsdu_enable = _FALSE;
+				else if (pregpriv->tx_ampdu_amsdu == 1)
+					psta->htpriv.tx_amsdu_enable = _TRUE;
+				else {
+					if (frame_body[5] & 1)
+						psta->htpriv.tx_amsdu_enable = _TRUE;
+				}
+			} else
+				psta->htpriv.agg_enable_bitmap &= ~BIT(tid);
+
+			if (psta->state & WIFI_STA_ALIVE_CHK_STATE) {
+				RTW_INFO("%s alive check - rx ADDBA response\n", __func__);
+				psta->htpriv.agg_enable_bitmap &= ~BIT(tid);
+				psta->expire_to = pstapriv->expire_to;
+				psta->state ^= WIFI_STA_ALIVE_CHK_STATE;
+			}
+
+			/* RTW_INFO("marc: ADDBA RSP: %x\n", pmlmeinfo->agg_enable_bitmap); */
+			break;
+
+		case RTW_WLAN_ACTION_DELBA: /* DELBA */
+			if ((frame_body[3] & BIT(3)) == 0) {
+				psta->htpriv.agg_enable_bitmap &= ~(1 << ((frame_body[3] >> 4) & 0xf));
+				psta->htpriv.candidate_tid_bitmap &= ~(1 << ((frame_body[3] >> 4) & 0xf));
+
+				/* reason_code = frame_body[4] | (frame_body[5] << 8); */
+				reason_code = RTW_GET_LE16(&frame_body[4]);
+			} else if ((frame_body[3] & BIT(3)) == BIT(3)) {
+				tid = (frame_body[3] >> 4) & 0x0F;
+
+				preorder_ctrl = &psta->recvreorder_ctrl[tid];
+				preorder_ctrl->enable = _FALSE;
+				preorder_ctrl->ampdu_size = RX_AMPDU_SIZE_INVALID;
+			}
+
+			RTW_INFO("%s(): DELBA: %x(%x)\n", __FUNCTION__, pmlmeinfo->agg_enable_bitmap, reason_code);
+			/* todo: how to notify the host while receiving DELETE BA */
+			break;
+
+		default:
+			break;
+		}
+	}
+#endif /* CONFIG_80211N_HT */
+	return _SUCCESS;
+}
+
+#ifdef CONFIG_P2P
+int get_reg_classes_full_count(struct p2p_channels *channel_list)
+{
+	int cnt = 0;
+	int i;
+
+	for (i = 0; i < channel_list->reg_classes; i++)
+		cnt += channel_list->reg_class[i].channels;
+
+	return cnt;
+}
+
+void issue_p2p_GO_request(_adapter *padapter, u8 *raddr)
+{
+	struct p2p_channels *ch_list = &(adapter_to_rfctl(padapter)->channel_list);
+	unsigned char category = RTW_WLAN_CATEGORY_PUBLIC;
+	u8			action = P2P_PUB_ACTION_ACTION;
+	u32			p2poui = cpu_to_be32(P2POUI);
+	u8			oui_subtype = P2P_GO_NEGO_REQ;
+	u8			wpsie[255] = { 0x00 }, p2pie[255] = { 0x00 };
+	u8			wpsielen = 0, p2pielen = 0;
+	u16			len_channellist_attr = 0;
+#ifdef CONFIG_WFD
+	u32					wfdielen = 0;
+#endif
+
+	struct xmit_frame			*pmgntframe;
+	struct pkt_attrib			*pattrib;
+	unsigned char					*pframe;
+	struct rtw_ieee80211_hdr	*pwlanhdr;
+	unsigned short				*fctrl;
+	struct xmit_priv			*pxmitpriv = &(padapter->xmitpriv);
+	struct mlme_ext_priv	*pmlmeext = &(padapter->mlmeextpriv);
+	struct wifidirect_info	*pwdinfo = &(padapter->wdinfo);
+
+
+	pmgntframe = alloc_mgtxmitframe(pxmitpriv);
+	if (pmgntframe == NULL)
+		return;
+
+	RTW_INFO("[%s] In\n", __FUNCTION__);
+	/* update attribute */
+	pattrib = &pmgntframe->attrib;
+	update_mgntframe_attrib(padapter, pattrib);
+
+	_rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET);
+
+	pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET;
+	pwlanhdr = (struct rtw_ieee80211_hdr *)pframe;
+
+	fctrl = &(pwlanhdr->frame_ctl);
+	*(fctrl) = 0;
+
+	_rtw_memcpy(pwlanhdr->addr1, raddr, ETH_ALEN);
+	_rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN);
+	_rtw_memcpy(pwlanhdr->addr3, adapter_mac_addr(padapter), ETH_ALEN);
+
+	SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq);
+	pmlmeext->mgnt_seq++;
+	set_frame_sub_type(pframe, WIFI_ACTION);
+
+	pframe += sizeof(struct rtw_ieee80211_hdr_3addr);
+	pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr);
+
+	pframe = rtw_set_fixed_ie(pframe, 1, &(category), &(pattrib->pktlen));
+	pframe = rtw_set_fixed_ie(pframe, 1, &(action), &(pattrib->pktlen));
+	pframe = rtw_set_fixed_ie(pframe, 4, (unsigned char *) &(p2poui), &(pattrib->pktlen));
+	pframe = rtw_set_fixed_ie(pframe, 1, &(oui_subtype), &(pattrib->pktlen));
+	pwdinfo->negotiation_dialog_token = 1;	/*	Initialize the dialog value */
+	pframe = rtw_set_fixed_ie(pframe, 1, &pwdinfo->negotiation_dialog_token, &(pattrib->pktlen));
+
+
+
+	/*	WPS Section */
+	wpsielen = 0;
+	/*	WPS OUI */
+	*(u32 *)(wpsie) = cpu_to_be32(WPSOUI);
+	wpsielen += 4;
+
+	/*	WPS version */
+	/*	Type: */
+	*(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_ATTR_VER1);
+	wpsielen += 2;
+
+	/*	Length: */
+	*(u16 *)(wpsie + wpsielen) = cpu_to_be16(0x0001);
+	wpsielen += 2;
+
+	/*	Value: */
+	wpsie[wpsielen++] = WPS_VERSION_1;	/*	Version 1.0 */
+
+	/*	Device Password ID */
+	/*	Type: */
+	*(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_ATTR_DEVICE_PWID);
+	wpsielen += 2;
+
+	/*	Length: */
+	*(u16 *)(wpsie + wpsielen) = cpu_to_be16(0x0002);
+	wpsielen += 2;
+
+	/*	Value: */
+
+	if (pwdinfo->ui_got_wps_info == P2P_GOT_WPSINFO_PEER_DISPLAY_PIN)
+		*(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_DPID_USER_SPEC);
+	else if (pwdinfo->ui_got_wps_info == P2P_GOT_WPSINFO_SELF_DISPLAY_PIN)
+		*(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_DPID_REGISTRAR_SPEC);
+	else if (pwdinfo->ui_got_wps_info == P2P_GOT_WPSINFO_PBC)
+		*(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_DPID_PBC);
+
+	wpsielen += 2;
+
+	pframe = rtw_set_ie(pframe, _VENDOR_SPECIFIC_IE_, wpsielen, (unsigned char *) wpsie, &pattrib->pktlen);
+
+
+	/*	P2P IE Section. */
+
+	/*	P2P OUI */
+	p2pielen = 0;
+	p2pie[p2pielen++] = 0x50;
+	p2pie[p2pielen++] = 0x6F;
+	p2pie[p2pielen++] = 0x9A;
+	p2pie[p2pielen++] = 0x09;	/*	WFA P2P v1.0 */
+
+	/*	Commented by Albert 20110306 */
+	/*	According to the P2P Specification, the group negoitation request frame should contain 9 P2P attributes */
+	/*	1. P2P Capability */
+	/*	2. Group Owner Intent */
+	/*	3. Configuration Timeout */
+	/*	4. Listen Channel */
+	/*	5. Extended Listen Timing */
+	/*	6. Intended P2P Interface Address */
+	/*	7. Channel List */
+	/*	8. P2P Device Info */
+	/*	9. Operating Channel */
+
+
+	/*	P2P Capability */
+	/*	Type: */
+	p2pie[p2pielen++] = P2P_ATTR_CAPABILITY;
+
+	/*	Length: */
+	*(u16 *)(p2pie + p2pielen) = cpu_to_le16(0x0002);
+	p2pielen += 2;
+
+	/*	Value: */
+	/*	Device Capability Bitmap, 1 byte */
+	p2pie[p2pielen++] = DMP_P2P_DEVCAP_SUPPORT;
+
+	/*	Group Capability Bitmap, 1 byte */
+	if (pwdinfo->persistent_supported)
+		p2pie[p2pielen++] = P2P_GRPCAP_CROSS_CONN | P2P_GRPCAP_PERSISTENT_GROUP;
+	else
+		p2pie[p2pielen++] = P2P_GRPCAP_CROSS_CONN;
+
+
+	/*	Group Owner Intent */
+	/*	Type: */
+	p2pie[p2pielen++] = P2P_ATTR_GO_INTENT;
+
+	/*	Length: */
+	*(u16 *)(p2pie + p2pielen) = cpu_to_le16(0x0001);
+	p2pielen += 2;
+
+	/*	Value: */
+	/*	Todo the tie breaker bit. */
+	p2pie[p2pielen++] = ((pwdinfo->intent << 1) &  0xFE);
+
+	/*	Configuration Timeout */
+	/*	Type: */
+	p2pie[p2pielen++] = P2P_ATTR_CONF_TIMEOUT;
+
+	/*	Length: */
+	*(u16 *)(p2pie + p2pielen) = cpu_to_le16(0x0002);
+	p2pielen += 2;
+
+	/*	Value: */
+	p2pie[p2pielen++] = 200;	/*	2 seconds needed to be the P2P GO */
+	p2pie[p2pielen++] = 200;	/*	2 seconds needed to be the P2P Client */
+
+
+	/*	Listen Channel */
+	/*	Type: */
+	p2pie[p2pielen++] = P2P_ATTR_LISTEN_CH;
+
+	/*	Length: */
+	*(u16 *)(p2pie + p2pielen) = cpu_to_le16(0x0005);
+	p2pielen += 2;
+
+	/*	Value: */
+	/*	Country String */
+	p2pie[p2pielen++] = 'X';
+	p2pie[p2pielen++] = 'X';
+
+	/*	The third byte should be set to 0x04. */
+	/*	Described in the "Operating Channel Attribute" section. */
+	p2pie[p2pielen++] = 0x04;
+
+	/*	Operating Class */
+	p2pie[p2pielen++] = 0x51;	/*	Copy from SD7 */
+
+	/*	Channel Number */
+	p2pie[p2pielen++] = pwdinfo->listen_channel;	/*	listening channel number */
+
+
+	/*	Extended Listen Timing ATTR */
+	/*	Type: */
+	p2pie[p2pielen++] = P2P_ATTR_EX_LISTEN_TIMING;
+
+	/*	Length: */
+	*(u16 *)(p2pie + p2pielen) = cpu_to_le16(0x0004);
+	p2pielen += 2;
+
+	/*	Value: */
+	/*	Availability Period */
+	*(u16 *)(p2pie + p2pielen) = cpu_to_le16(0xFFFF);
+	p2pielen += 2;
+
+	/*	Availability Interval */
+	*(u16 *)(p2pie + p2pielen) = cpu_to_le16(0xFFFF);
+	p2pielen += 2;
+
+
+	/*	Intended P2P Interface Address */
+	/*	Type: */
+	p2pie[p2pielen++] = P2P_ATTR_INTENDED_IF_ADDR;
+
+	/*	Length: */
+	*(u16 *)(p2pie + p2pielen) = cpu_to_le16(ETH_ALEN);
+	p2pielen += 2;
+
+	/*	Value: */
+	_rtw_memcpy(p2pie + p2pielen, adapter_mac_addr(padapter), ETH_ALEN);
+	p2pielen += ETH_ALEN;
+
+
+	/*	Channel List */
+	/*	Type: */
+	p2pie[p2pielen++] = P2P_ATTR_CH_LIST;
+
+	/* Length: */
+	/* Country String(3) */
+	/* + ( Operating Class (1) + Number of Channels(1) ) * Operation Classes (?) */
+	/* + number of channels in all classes */
+	len_channellist_attr = 3
+		       + (1 + 1) * (u16)(ch_list->reg_classes)
+		       + get_reg_classes_full_count(ch_list);
+
+#ifdef CONFIG_CONCURRENT_MODE
+	if (rtw_mi_check_status(padapter, MI_LINKED) && padapter->registrypriv.full_ch_in_p2p_handshake == 0)
+		*(u16 *)(p2pie + p2pielen) = cpu_to_le16(5 + 1);
+	else
+		*(u16 *)(p2pie + p2pielen) = cpu_to_le16(len_channellist_attr);
+#else
+
+	*(u16 *)(p2pie + p2pielen) = cpu_to_le16(len_channellist_attr);
+
+#endif
+	p2pielen += 2;
+
+	/*	Value: */
+	/*	Country String */
+	p2pie[p2pielen++] = 'X';
+	p2pie[p2pielen++] = 'X';
+
+	/*	The third byte should be set to 0x04. */
+	/*	Described in the "Operating Channel Attribute" section. */
+	p2pie[p2pielen++] = 0x04;
+
+	/*	Channel Entry List */
+
+#ifdef CONFIG_CONCURRENT_MODE
+	if (rtw_mi_check_status(padapter, MI_LINKED) && padapter->registrypriv.full_ch_in_p2p_handshake == 0) {
+		u8 union_ch = rtw_mi_get_union_chan(padapter);
+
+		/*	Operating Class */
+		if (union_ch > 14) {
+			if (union_ch >= 149)
+				p2pie[p2pielen++] = 0x7c;
+			else
+				p2pie[p2pielen++] = 0x73;
+		} else
+			p2pie[p2pielen++] = 0x51;
+
+
+		/*	Number of Channels */
+		/*	Just support 1 channel and this channel is AP's channel */
+		p2pie[p2pielen++] = 1;
+
+		/*	Channel List */
+		p2pie[p2pielen++] = union_ch;
+	} else
+#endif /* CONFIG_CONCURRENT_MODE */
+	{
+		int i, j;
+		for (j = 0; j < ch_list->reg_classes; j++) {
+			/*	Operating Class */
+			p2pie[p2pielen++] = ch_list->reg_class[j].reg_class;
+
+			/*	Number of Channels */
+			p2pie[p2pielen++] = ch_list->reg_class[j].channels;
+
+			/*	Channel List */
+			for (i = 0; i < ch_list->reg_class[j].channels; i++)
+				p2pie[p2pielen++] = ch_list->reg_class[j].channel[i];
+		}
+	}
+
+	/*	Device Info */
+	/*	Type: */
+	p2pie[p2pielen++] = P2P_ATTR_DEVICE_INFO;
+
+	/*	Length: */
+	/*	21->P2P Device Address (6bytes) + Config Methods (2bytes) + Primary Device Type (8bytes)  */
+	/*	+ NumofSecondDevType (1byte) + WPS Device Name ID field (2bytes) + WPS Device Name Len field (2bytes) */
+	*(u16 *)(p2pie + p2pielen) = cpu_to_le16(21 + pwdinfo->device_name_len);
+	p2pielen += 2;
+
+	/*	Value: */
+	/*	P2P Device Address */
+	_rtw_memcpy(p2pie + p2pielen, adapter_mac_addr(padapter), ETH_ALEN);
+	p2pielen += ETH_ALEN;
+
+	/*	Config Method */
+	/*	This field should be big endian. Noted by P2P specification. */
+
+	*(u16 *)(p2pie + p2pielen) = cpu_to_be16(pwdinfo->supported_wps_cm);
+
+	p2pielen += 2;
+
+	/*	Primary Device Type */
+	/*	Category ID */
+	*(u16 *)(p2pie + p2pielen) = cpu_to_be16(WPS_PDT_CID_MULIT_MEDIA);
+	p2pielen += 2;
+
+	/*	OUI */
+	*(u32 *)(p2pie + p2pielen) = cpu_to_be32(WPSOUI);
+	p2pielen += 4;
+
+	/*	Sub Category ID */
+	*(u16 *)(p2pie + p2pielen) = cpu_to_be16(WPS_PDT_SCID_MEDIA_SERVER);
+	p2pielen += 2;
+
+	/*	Number of Secondary Device Types */
+	p2pie[p2pielen++] = 0x00;	/*	No Secondary Device Type List */
+
+	/*	Device Name */
+	/*	Type: */
+	*(u16 *)(p2pie + p2pielen) = cpu_to_be16(WPS_ATTR_DEVICE_NAME);
+	p2pielen += 2;
+
+	/*	Length: */
+	*(u16 *)(p2pie + p2pielen) = cpu_to_be16(pwdinfo->device_name_len);
+	p2pielen += 2;
+
+	/*	Value: */
+	_rtw_memcpy(p2pie + p2pielen, pwdinfo->device_name , pwdinfo->device_name_len);
+	p2pielen += pwdinfo->device_name_len;
+
+
+	/*	Operating Channel */
+	/*	Type: */
+	p2pie[p2pielen++] = P2P_ATTR_OPERATING_CH;
+
+	/*	Length: */
+	*(u16 *)(p2pie + p2pielen) = cpu_to_le16(0x0005);
+	p2pielen += 2;
+
+	/*	Value: */
+	/*	Country String */
+	p2pie[p2pielen++] = 'X';
+	p2pie[p2pielen++] = 'X';
+
+	/*	The third byte should be set to 0x04. */
+	/*	Described in the "Operating Channel Attribute" section. */
+	p2pie[p2pielen++] = 0x04;
+
+	/*	Operating Class */
+	if (pwdinfo->operating_channel <= 14) {
+		/*	Operating Class */
+		p2pie[p2pielen++] = 0x51;
+	} else if ((pwdinfo->operating_channel >= 36) && (pwdinfo->operating_channel <= 48)) {
+		/*	Operating Class */
+		p2pie[p2pielen++] = 0x73;
+	} else {
+		/*	Operating Class */
+		p2pie[p2pielen++] = 0x7c;
+	}
+
+	/*	Channel Number */
+	p2pie[p2pielen++] = pwdinfo->operating_channel;	/*	operating channel number */
+
+	pframe = rtw_set_ie(pframe, _VENDOR_SPECIFIC_IE_, p2pielen, (unsigned char *) p2pie, &pattrib->pktlen);
+
+#ifdef CONFIG_WFD
+	wfdielen = build_nego_req_wfd_ie(pwdinfo, pframe);
+	pframe += wfdielen;
+	pattrib->pktlen += wfdielen;
+#endif
+
+	pattrib->last_txcmdsz = pattrib->pktlen;
+
+	dump_mgntframe(padapter, pmgntframe);
+
+	return;
+
+}
+
+
+void issue_p2p_GO_response(_adapter *padapter, u8 *raddr, u8 *frame_body, uint len, u8 result)
+{
+	struct p2p_channels *ch_list = &(adapter_to_rfctl(padapter)->channel_list);
+	unsigned char category = RTW_WLAN_CATEGORY_PUBLIC;
+	u8			action = P2P_PUB_ACTION_ACTION;
+	u32			p2poui = cpu_to_be32(P2POUI);
+	u8			oui_subtype = P2P_GO_NEGO_RESP;
+	u8			wpsie[255] = { 0x00 }, p2pie[255] = { 0x00 };
+	u8			p2pielen = 0;
+	uint			wpsielen = 0;
+	u16			wps_devicepassword_id = 0x0000;
+	uint			wps_devicepassword_id_len = 0;
+	u16			len_channellist_attr = 0;
+
+	struct xmit_frame			*pmgntframe;
+	struct pkt_attrib			*pattrib;
+	unsigned char					*pframe;
+	struct rtw_ieee80211_hdr	*pwlanhdr;
+	unsigned short				*fctrl;
+	struct xmit_priv			*pxmitpriv = &(padapter->xmitpriv);
+	struct mlme_ext_priv	*pmlmeext = &(padapter->mlmeextpriv);
+	struct wifidirect_info	*pwdinfo = &(padapter->wdinfo);
+
+#ifdef CONFIG_WFD
+	u32					wfdielen = 0;
+#endif
+
+	pmgntframe = alloc_mgtxmitframe(pxmitpriv);
+	if (pmgntframe == NULL)
+		return;
+
+	RTW_INFO("[%s] In, result = %d\n", __FUNCTION__,  result);
+	/* update attribute */
+	pattrib = &pmgntframe->attrib;
+	update_mgntframe_attrib(padapter, pattrib);
+
+	_rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET);
+
+	pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET;
+	pwlanhdr = (struct rtw_ieee80211_hdr *)pframe;
+
+	fctrl = &(pwlanhdr->frame_ctl);
+	*(fctrl) = 0;
+
+	_rtw_memcpy(pwlanhdr->addr1, raddr, ETH_ALEN);
+	_rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN);
+	_rtw_memcpy(pwlanhdr->addr3, adapter_mac_addr(padapter), ETH_ALEN);
+
+	SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq);
+	pmlmeext->mgnt_seq++;
+	set_frame_sub_type(pframe, WIFI_ACTION);
+
+	pframe += sizeof(struct rtw_ieee80211_hdr_3addr);
+	pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr);
+
+	pframe = rtw_set_fixed_ie(pframe, 1, &(category), &(pattrib->pktlen));
+	pframe = rtw_set_fixed_ie(pframe, 1, &(action), &(pattrib->pktlen));
+	pframe = rtw_set_fixed_ie(pframe, 4, (unsigned char *) &(p2poui), &(pattrib->pktlen));
+	pframe = rtw_set_fixed_ie(pframe, 1, &(oui_subtype), &(pattrib->pktlen));
+	pwdinfo->negotiation_dialog_token = frame_body[7];	/*	The Dialog Token of provisioning discovery request frame. */
+	pframe = rtw_set_fixed_ie(pframe, 1, &(pwdinfo->negotiation_dialog_token), &(pattrib->pktlen));
+
+	/*	Commented by Albert 20110328 */
+	/*	Try to get the device password ID from the WPS IE of group negotiation request frame */
+	/*	WiFi Direct test plan 5.1.15 */
+	rtw_get_wps_ie(frame_body + _PUBLIC_ACTION_IE_OFFSET_, len - _PUBLIC_ACTION_IE_OFFSET_, wpsie, &wpsielen);
+	rtw_get_wps_attr_content(wpsie, wpsielen, WPS_ATTR_DEVICE_PWID, (u8 *) &wps_devicepassword_id, &wps_devicepassword_id_len);
+	wps_devicepassword_id = be16_to_cpu(wps_devicepassword_id);
+
+	_rtw_memset(wpsie, 0x00, 255);
+	wpsielen = 0;
+
+	/*	WPS Section */
+	wpsielen = 0;
+	/*	WPS OUI */
+	*(u32 *)(wpsie) = cpu_to_be32(WPSOUI);
+	wpsielen += 4;
+
+	/*	WPS version */
+	/*	Type: */
+	*(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_ATTR_VER1);
+	wpsielen += 2;
+
+	/*	Length: */
+	*(u16 *)(wpsie + wpsielen) = cpu_to_be16(0x0001);
+	wpsielen += 2;
+
+	/*	Value: */
+	wpsie[wpsielen++] = WPS_VERSION_1;	/*	Version 1.0 */
+
+	/*	Device Password ID */
+	/*	Type: */
+	*(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_ATTR_DEVICE_PWID);
+	wpsielen += 2;
+
+	/*	Length: */
+	*(u16 *)(wpsie + wpsielen) = cpu_to_be16(0x0002);
+	wpsielen += 2;
+
+	/*	Value: */
+	if (wps_devicepassword_id == WPS_DPID_USER_SPEC)
+		*(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_DPID_REGISTRAR_SPEC);
+	else if (wps_devicepassword_id == WPS_DPID_REGISTRAR_SPEC)
+		*(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_DPID_USER_SPEC);
+	else
+		*(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_DPID_PBC);
+	wpsielen += 2;
+
+	/*	Commented by Kurt 20120113 */
+	/*	If some device wants to do p2p handshake without sending prov_disc_req */
+	/*	We have to get peer_req_cm from here. */
+	if (_rtw_memcmp(pwdinfo->rx_prov_disc_info.strconfig_method_desc_of_prov_disc_req, "000", 3)) {
+		if (wps_devicepassword_id == WPS_DPID_USER_SPEC)
+			_rtw_memcpy(pwdinfo->rx_prov_disc_info.strconfig_method_desc_of_prov_disc_req, "dis", 3);
+		else if (wps_devicepassword_id == WPS_DPID_REGISTRAR_SPEC)
+			_rtw_memcpy(pwdinfo->rx_prov_disc_info.strconfig_method_desc_of_prov_disc_req, "pad", 3);
+		else
+			_rtw_memcpy(pwdinfo->rx_prov_disc_info.strconfig_method_desc_of_prov_disc_req, "pbc", 3);
+	}
+
+	pframe = rtw_set_ie(pframe, _VENDOR_SPECIFIC_IE_, wpsielen, (unsigned char *) wpsie, &pattrib->pktlen);
+
+
+	/*	P2P IE Section. */
+
+	/*	P2P OUI */
+	p2pielen = 0;
+	p2pie[p2pielen++] = 0x50;
+	p2pie[p2pielen++] = 0x6F;
+	p2pie[p2pielen++] = 0x9A;
+	p2pie[p2pielen++] = 0x09;	/*	WFA P2P v1.0 */
+
+	/*	Commented by Albert 20100908 */
+	/*	According to the P2P Specification, the group negoitation response frame should contain 9 P2P attributes */
+	/*	1. Status */
+	/*	2. P2P Capability */
+	/*	3. Group Owner Intent */
+	/*	4. Configuration Timeout */
+	/*	5. Operating Channel */
+	/*	6. Intended P2P Interface Address */
+	/*	7. Channel List */
+	/*	8. Device Info */
+	/*	9. Group ID	( Only GO ) */
+
+
+	/*	ToDo: */
+
+	/*	P2P Status */
+	/*	Type: */
+	p2pie[p2pielen++] = P2P_ATTR_STATUS;
+
+	/*	Length: */
+	*(u16 *)(p2pie + p2pielen) = cpu_to_le16(0x0001);
+	p2pielen += 2;
+
+	/*	Value: */
+	p2pie[p2pielen++] = result;
+
+	/*	P2P Capability */
+	/*	Type: */
+	p2pie[p2pielen++] = P2P_ATTR_CAPABILITY;
+
+	/*	Length: */
+	*(u16 *)(p2pie + p2pielen) = cpu_to_le16(0x0002);
+	p2pielen += 2;
+
+	/*	Value: */
+	/*	Device Capability Bitmap, 1 byte */
+
+	if (rtw_p2p_chk_role(pwdinfo, P2P_ROLE_CLIENT)) {
+		/*	Commented by Albert 2011/03/08 */
+		/*	According to the P2P specification */
+		/*	if the sending device will be client, the P2P Capability should be reserved of group negotation response frame */
+		p2pie[p2pielen++] = 0;
+	} else {
+		/*	Be group owner or meet the error case */
+		p2pie[p2pielen++] = DMP_P2P_DEVCAP_SUPPORT;
+	}
+
+	/*	Group Capability Bitmap, 1 byte */
+	if (pwdinfo->persistent_supported)
+		p2pie[p2pielen++] = P2P_GRPCAP_CROSS_CONN | P2P_GRPCAP_PERSISTENT_GROUP;
+	else
+		p2pie[p2pielen++] = P2P_GRPCAP_CROSS_CONN;
+
+	/*	Group Owner Intent */
+	/*	Type: */
+	p2pie[p2pielen++] = P2P_ATTR_GO_INTENT;
+
+	/*	Length: */
+	*(u16 *)(p2pie + p2pielen) = cpu_to_le16(0x0001);
+	p2pielen += 2;
+
+	/*	Value: */
+	if (pwdinfo->peer_intent & 0x01) {
+		/*	Peer's tie breaker bit is 1, our tie breaker bit should be 0 */
+		p2pie[p2pielen++] = (pwdinfo->intent << 1);
+	} else {
+		/*	Peer's tie breaker bit is 0, our tie breaker bit should be 1 */
+		p2pie[p2pielen++] = ((pwdinfo->intent << 1) | BIT(0));
+	}
+
+
+	/*	Configuration Timeout */
+	/*	Type: */
+	p2pie[p2pielen++] = P2P_ATTR_CONF_TIMEOUT;
+
+	/*	Length: */
+	*(u16 *)(p2pie + p2pielen) = cpu_to_le16(0x0002);
+	p2pielen += 2;
+
+	/*	Value: */
+	p2pie[p2pielen++] = 200;	/*	2 seconds needed to be the P2P GO */
+	p2pie[p2pielen++] = 200;	/*	2 seconds needed to be the P2P Client */
+
+	/*	Operating Channel */
+	/*	Type: */
+	p2pie[p2pielen++] = P2P_ATTR_OPERATING_CH;
+
+	/*	Length: */
+	*(u16 *)(p2pie + p2pielen) = cpu_to_le16(0x0005);
+	p2pielen += 2;
+
+	/*	Value: */
+	/*	Country String */
+	p2pie[p2pielen++] = 'X';
+	p2pie[p2pielen++] = 'X';
+
+	/*	The third byte should be set to 0x04. */
+	/*	Described in the "Operating Channel Attribute" section. */
+	p2pie[p2pielen++] = 0x04;
+
+	/*	Operating Class */
+	if (pwdinfo->operating_channel <= 14) {
+		/*	Operating Class */
+		p2pie[p2pielen++] = 0x51;
+	} else if ((pwdinfo->operating_channel >= 36) && (pwdinfo->operating_channel <= 48)) {
+		/*	Operating Class */
+		p2pie[p2pielen++] = 0x73;
+	} else {
+		/*	Operating Class */
+		p2pie[p2pielen++] = 0x7c;
+	}
+
+	/*	Channel Number */
+	p2pie[p2pielen++] = pwdinfo->operating_channel;	/*	operating channel number */
+
+	/*	Intended P2P Interface Address	 */
+	/*	Type: */
+	p2pie[p2pielen++] = P2P_ATTR_INTENDED_IF_ADDR;
+
+	/*	Length: */
+	*(u16 *)(p2pie + p2pielen) = cpu_to_le16(ETH_ALEN);
+	p2pielen += 2;
+
+	/*	Value: */
+	_rtw_memcpy(p2pie + p2pielen, adapter_mac_addr(padapter), ETH_ALEN);
+	p2pielen += ETH_ALEN;
+
+	/*	Channel List */
+	/*	Type: */
+	p2pie[p2pielen++] = P2P_ATTR_CH_LIST;
+
+	/* Country String(3) */
+	/* + ( Operating Class (1) + Number of Channels(1) ) * Operation Classes (?) */
+	/* + number of channels in all classes */
+	len_channellist_attr = 3
+		       + (1 + 1) * (u16)ch_list->reg_classes
+		       + get_reg_classes_full_count(ch_list);
+
+#ifdef CONFIG_CONCURRENT_MODE
+	if (rtw_mi_check_status(padapter, MI_LINKED) && padapter->registrypriv.full_ch_in_p2p_handshake == 0)
+		*(u16 *)(p2pie + p2pielen) = cpu_to_le16(5 + 1);
+	else
+		*(u16 *)(p2pie + p2pielen) = cpu_to_le16(len_channellist_attr);
+#else
+	*(u16 *)(p2pie + p2pielen) = cpu_to_le16(len_channellist_attr);
+
+#endif
+	p2pielen += 2;
+
+	/*	Value: */
+	/*	Country String */
+	p2pie[p2pielen++] = 'X';
+	p2pie[p2pielen++] = 'X';
+
+	/*	The third byte should be set to 0x04. */
+	/*	Described in the "Operating Channel Attribute" section. */
+	p2pie[p2pielen++] = 0x04;
+
+	/*	Channel Entry List */
+
+#ifdef CONFIG_CONCURRENT_MODE
+	if (rtw_mi_check_status(padapter, MI_LINKED) && padapter->registrypriv.full_ch_in_p2p_handshake == 0) {
+
+		u8 union_chan = rtw_mi_get_union_chan(padapter);
+
+		/*Operating Class*/
+		if (union_chan > 14) {
+			if (union_chan >= 149)
+				p2pie[p2pielen++] = 0x7c;
+			else
+				p2pie[p2pielen++] = 0x73;
+
+		} else
+			p2pie[p2pielen++] = 0x51;
+
+		/*	Number of Channels
+			Just support 1 channel and this channel is AP's channel*/
+		p2pie[p2pielen++] = 1;
+
+		/*Channel List*/
+		p2pie[p2pielen++] = union_chan;
+	} else
+#endif /* CONFIG_CONCURRENT_MODE */
+	{
+		int i, j;
+		for (j = 0; j < ch_list->reg_classes; j++) {
+			/*	Operating Class */
+			p2pie[p2pielen++] = ch_list->reg_class[j].reg_class;
+
+			/*	Number of Channels */
+			p2pie[p2pielen++] = ch_list->reg_class[j].channels;
+
+			/*	Channel List */
+			for (i = 0; i < ch_list->reg_class[j].channels; i++)
+				p2pie[p2pielen++] = ch_list->reg_class[j].channel[i];
+		}
+	}
+
+	/*	Device Info */
+	/*	Type: */
+	p2pie[p2pielen++] = P2P_ATTR_DEVICE_INFO;
+
+	/*	Length: */
+	/*	21->P2P Device Address (6bytes) + Config Methods (2bytes) + Primary Device Type (8bytes)  */
+	/*	+ NumofSecondDevType (1byte) + WPS Device Name ID field (2bytes) + WPS Device Name Len field (2bytes) */
+	*(u16 *)(p2pie + p2pielen) = cpu_to_le16(21 + pwdinfo->device_name_len);
+	p2pielen += 2;
+
+	/*	Value: */
+	/*	P2P Device Address */
+	_rtw_memcpy(p2pie + p2pielen, adapter_mac_addr(padapter), ETH_ALEN);
+	p2pielen += ETH_ALEN;
+
+	/*	Config Method */
+	/*	This field should be big endian. Noted by P2P specification. */
+
+	*(u16 *)(p2pie + p2pielen) = cpu_to_be16(pwdinfo->supported_wps_cm);
+
+	p2pielen += 2;
+
+	/*	Primary Device Type */
+	/*	Category ID */
+	*(u16 *)(p2pie + p2pielen) = cpu_to_be16(WPS_PDT_CID_MULIT_MEDIA);
+	p2pielen += 2;
+
+	/*	OUI */
+	*(u32 *)(p2pie + p2pielen) = cpu_to_be32(WPSOUI);
+	p2pielen += 4;
+
+	/*	Sub Category ID */
+	*(u16 *)(p2pie + p2pielen) = cpu_to_be16(WPS_PDT_SCID_MEDIA_SERVER);
+	p2pielen += 2;
+
+	/*	Number of Secondary Device Types */
+	p2pie[p2pielen++] = 0x00;	/*	No Secondary Device Type List */
+
+	/*	Device Name */
+	/*	Type: */
+	*(u16 *)(p2pie + p2pielen) = cpu_to_be16(WPS_ATTR_DEVICE_NAME);
+	p2pielen += 2;
+
+	/*	Length: */
+	*(u16 *)(p2pie + p2pielen) = cpu_to_be16(pwdinfo->device_name_len);
+	p2pielen += 2;
+
+	/*	Value: */
+	_rtw_memcpy(p2pie + p2pielen, pwdinfo->device_name , pwdinfo->device_name_len);
+	p2pielen += pwdinfo->device_name_len;
+
+	if (rtw_p2p_chk_role(pwdinfo, P2P_ROLE_GO)) {
+		/*	Group ID Attribute */
+		/*	Type: */
+		p2pie[p2pielen++] = P2P_ATTR_GROUP_ID;
+
+		/*	Length: */
+		*(u16 *)(p2pie + p2pielen) = cpu_to_le16(ETH_ALEN + pwdinfo->nego_ssidlen);
+		p2pielen += 2;
+
+		/*	Value: */
+		/*	p2P Device Address */
+		_rtw_memcpy(p2pie + p2pielen , pwdinfo->device_addr, ETH_ALEN);
+		p2pielen += ETH_ALEN;
+
+		/*	SSID */
+		_rtw_memcpy(p2pie + p2pielen, pwdinfo->nego_ssid, pwdinfo->nego_ssidlen);
+		p2pielen += pwdinfo->nego_ssidlen;
+
+	}
+
+	pframe = rtw_set_ie(pframe, _VENDOR_SPECIFIC_IE_, p2pielen, (unsigned char *) p2pie, &pattrib->pktlen);
+
+#ifdef CONFIG_WFD
+	wfdielen = build_nego_resp_wfd_ie(pwdinfo, pframe);
+	pframe += wfdielen;
+	pattrib->pktlen += wfdielen;
+#endif
+
+	pattrib->last_txcmdsz = pattrib->pktlen;
+
+	dump_mgntframe(padapter, pmgntframe);
+
+	return;
+
+}
+
+void issue_p2p_GO_confirm(_adapter *padapter, u8 *raddr, u8 result)
+{
+
+	unsigned char category = RTW_WLAN_CATEGORY_PUBLIC;
+	u8			action = P2P_PUB_ACTION_ACTION;
+	u32			p2poui = cpu_to_be32(P2POUI);
+	u8			oui_subtype = P2P_GO_NEGO_CONF;
+	u8			p2pie[255] = { 0x00 };
+	u8			p2pielen = 0;
+
+	struct xmit_frame			*pmgntframe;
+	struct pkt_attrib			*pattrib;
+	unsigned char					*pframe;
+	struct rtw_ieee80211_hdr	*pwlanhdr;
+	unsigned short				*fctrl;
+	struct xmit_priv			*pxmitpriv = &(padapter->xmitpriv);
+	struct mlme_ext_priv	*pmlmeext = &(padapter->mlmeextpriv);
+	struct wifidirect_info	*pwdinfo = &(padapter->wdinfo);
+#ifdef CONFIG_WFD
+	u32					wfdielen = 0;
+#endif
+
+	pmgntframe = alloc_mgtxmitframe(pxmitpriv);
+	if (pmgntframe == NULL)
+		return;
+
+	RTW_INFO("[%s] In\n", __FUNCTION__);
+	/* update attribute */
+	pattrib = &pmgntframe->attrib;
+	update_mgntframe_attrib(padapter, pattrib);
+
+	_rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET);
+
+	pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET;
+	pwlanhdr = (struct rtw_ieee80211_hdr *)pframe;
+
+	fctrl = &(pwlanhdr->frame_ctl);
+	*(fctrl) = 0;
+
+	_rtw_memcpy(pwlanhdr->addr1, raddr, ETH_ALEN);
+	_rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN);
+	_rtw_memcpy(pwlanhdr->addr3, adapter_mac_addr(padapter), ETH_ALEN);
+
+	SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq);
+	pmlmeext->mgnt_seq++;
+	set_frame_sub_type(pframe, WIFI_ACTION);
+
+	pframe += sizeof(struct rtw_ieee80211_hdr_3addr);
+	pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr);
+
+	pframe = rtw_set_fixed_ie(pframe, 1, &(category), &(pattrib->pktlen));
+	pframe = rtw_set_fixed_ie(pframe, 1, &(action), &(pattrib->pktlen));
+	pframe = rtw_set_fixed_ie(pframe, 4, (unsigned char *) &(p2poui), &(pattrib->pktlen));
+	pframe = rtw_set_fixed_ie(pframe, 1, &(oui_subtype), &(pattrib->pktlen));
+	pframe = rtw_set_fixed_ie(pframe, 1, &(pwdinfo->negotiation_dialog_token), &(pattrib->pktlen));
+
+
+
+	/*	P2P IE Section. */
+
+	/*	P2P OUI */
+	p2pielen = 0;
+	p2pie[p2pielen++] = 0x50;
+	p2pie[p2pielen++] = 0x6F;
+	p2pie[p2pielen++] = 0x9A;
+	p2pie[p2pielen++] = 0x09;	/*	WFA P2P v1.0 */
+
+	/*	Commented by Albert 20110306 */
+	/*	According to the P2P Specification, the group negoitation request frame should contain 5 P2P attributes */
+	/*	1. Status */
+	/*	2. P2P Capability */
+	/*	3. Operating Channel */
+	/*	4. Channel List */
+	/*	5. Group ID	( if this WiFi is GO ) */
+
+	/*	P2P Status */
+	/*	Type: */
+	p2pie[p2pielen++] = P2P_ATTR_STATUS;
+
+	/*	Length: */
+	*(u16 *)(p2pie + p2pielen) = cpu_to_le16(0x0001);
+	p2pielen += 2;
+
+	/*	Value: */
+	p2pie[p2pielen++] = result;
+
+	/*	P2P Capability */
+	/*	Type: */
+	p2pie[p2pielen++] = P2P_ATTR_CAPABILITY;
+
+	/*	Length: */
+	*(u16 *)(p2pie + p2pielen) = cpu_to_le16(0x0002);
+	p2pielen += 2;
+
+	/*	Value: */
+	/*	Device Capability Bitmap, 1 byte */
+	p2pie[p2pielen++] = DMP_P2P_DEVCAP_SUPPORT;
+
+	/*	Group Capability Bitmap, 1 byte */
+	if (pwdinfo->persistent_supported)
+		p2pie[p2pielen++] = P2P_GRPCAP_CROSS_CONN | P2P_GRPCAP_PERSISTENT_GROUP;
+	else
+		p2pie[p2pielen++] = P2P_GRPCAP_CROSS_CONN;
+
+
+	/*	Operating Channel */
+	/*	Type: */
+	p2pie[p2pielen++] = P2P_ATTR_OPERATING_CH;
+
+	/*	Length: */
+	*(u16 *)(p2pie + p2pielen) = cpu_to_le16(0x0005);
+	p2pielen += 2;
+
+	/*	Value: */
+	/*	Country String */
+	p2pie[p2pielen++] = 'X';
+	p2pie[p2pielen++] = 'X';
+
+	/*	The third byte should be set to 0x04. */
+	/*	Described in the "Operating Channel Attribute" section. */
+	p2pie[p2pielen++] = 0x04;
+
+
+	if (rtw_p2p_chk_role(pwdinfo, P2P_ROLE_CLIENT)) {
+		if (pwdinfo->peer_operating_ch <= 14) {
+			/*	Operating Class */
+			p2pie[p2pielen++] = 0x51;
+		} else if ((pwdinfo->peer_operating_ch >= 36) && (pwdinfo->peer_operating_ch <= 48)) {
+			/*	Operating Class */
+			p2pie[p2pielen++] = 0x73;
+		} else {
+			/*	Operating Class */
+			p2pie[p2pielen++] = 0x7c;
+		}
+
+		p2pie[p2pielen++] = pwdinfo->peer_operating_ch;
+	} else {
+		if (pwdinfo->operating_channel <= 14) {
+			/*	Operating Class */
+			p2pie[p2pielen++] = 0x51;
+		} else if ((pwdinfo->operating_channel >= 36) && (pwdinfo->operating_channel <= 48)) {
+			/*	Operating Class */
+			p2pie[p2pielen++] = 0x73;
+		} else {
+			/*	Operating Class */
+			p2pie[p2pielen++] = 0x7c;
+		}
+
+		/*	Channel Number */
+		p2pie[p2pielen++] = pwdinfo->operating_channel;		/*	Use the listen channel as the operating channel */
+	}
+
+
+	/*	Channel List */
+	/*	Type: */
+	p2pie[p2pielen++] = P2P_ATTR_CH_LIST;
+
+	*(u16 *)(p2pie + p2pielen) = 6;
+	p2pielen += 2;
+
+	/*	Country String */
+	p2pie[p2pielen++] = 'X';
+	p2pie[p2pielen++] = 'X';
+
+	/*	The third byte should be set to 0x04. */
+	/*	Described in the "Operating Channel Attribute" section. */
+	p2pie[p2pielen++] = 0x04;
+
+	/*	Value: */
+	if (rtw_p2p_chk_role(pwdinfo, P2P_ROLE_CLIENT)) {
+		if (pwdinfo->peer_operating_ch <= 14) {
+			/*	Operating Class */
+			p2pie[p2pielen++] = 0x51;
+		} else if ((pwdinfo->peer_operating_ch >= 36) && (pwdinfo->peer_operating_ch <= 48)) {
+			/*	Operating Class */
+			p2pie[p2pielen++] = 0x73;
+		} else {
+			/*	Operating Class */
+			p2pie[p2pielen++] = 0x7c;
+		}
+		p2pie[p2pielen++] = 1;
+		p2pie[p2pielen++] = pwdinfo->peer_operating_ch;
+	} else {
+		if (pwdinfo->operating_channel <= 14) {
+			/*	Operating Class */
+			p2pie[p2pielen++] = 0x51;
+		} else if ((pwdinfo->operating_channel >= 36) && (pwdinfo->operating_channel <= 48)) {
+			/*	Operating Class */
+			p2pie[p2pielen++] = 0x73;
+		} else {
+			/*	Operating Class */
+			p2pie[p2pielen++] = 0x7c;
+		}
+
+		/*	Channel Number */
+		p2pie[p2pielen++] = 1;
+		p2pie[p2pielen++] = pwdinfo->operating_channel;		/*	Use the listen channel as the operating channel */
+	}
+
+	if (rtw_p2p_chk_role(pwdinfo, P2P_ROLE_GO)) {
+		/*	Group ID Attribute */
+		/*	Type: */
+		p2pie[p2pielen++] = P2P_ATTR_GROUP_ID;
+
+		/*	Length: */
+		*(u16 *)(p2pie + p2pielen) = cpu_to_le16(ETH_ALEN + pwdinfo->nego_ssidlen);
+		p2pielen += 2;
+
+		/*	Value: */
+		/*	p2P Device Address */
+		_rtw_memcpy(p2pie + p2pielen , pwdinfo->device_addr, ETH_ALEN);
+		p2pielen += ETH_ALEN;
+
+		/*	SSID */
+		_rtw_memcpy(p2pie + p2pielen, pwdinfo->nego_ssid, pwdinfo->nego_ssidlen);
+		p2pielen += pwdinfo->nego_ssidlen;
+	}
+
+	pframe = rtw_set_ie(pframe, _VENDOR_SPECIFIC_IE_, p2pielen, (unsigned char *) p2pie, &pattrib->pktlen);
+
+#ifdef CONFIG_WFD
+	wfdielen = build_nego_confirm_wfd_ie(pwdinfo, pframe);
+	pframe += wfdielen;
+	pattrib->pktlen += wfdielen;
+#endif
+
+	pattrib->last_txcmdsz = pattrib->pktlen;
+
+	dump_mgntframe(padapter, pmgntframe);
+
+	return;
+
+}
+
+void issue_p2p_invitation_request(_adapter *padapter, u8 *raddr)
+{
+	struct p2p_channels *ch_list = &(adapter_to_rfctl(padapter)->channel_list);
+	unsigned char category = RTW_WLAN_CATEGORY_PUBLIC;
+	u8			action = P2P_PUB_ACTION_ACTION;
+	u32			p2poui = cpu_to_be32(P2POUI);
+	u8			oui_subtype = P2P_INVIT_REQ;
+	u8			p2pie[255] = { 0x00 };
+	u8			p2pielen = 0;
+	u8			dialogToken = 3;
+	u16			len_channellist_attr = 0;
+#ifdef CONFIG_WFD
+	u32					wfdielen = 0;
+#endif
+
+	struct xmit_frame			*pmgntframe;
+	struct pkt_attrib			*pattrib;
+	unsigned char					*pframe;
+	struct rtw_ieee80211_hdr	*pwlanhdr;
+	unsigned short				*fctrl;
+	struct xmit_priv			*pxmitpriv = &(padapter->xmitpriv);
+	struct mlme_ext_priv	*pmlmeext = &(padapter->mlmeextpriv);
+	struct wifidirect_info	*pwdinfo = &(padapter->wdinfo);
+
+
+	pmgntframe = alloc_mgtxmitframe(pxmitpriv);
+	if (pmgntframe == NULL)
+		return;
+
+	/* update attribute */
+	pattrib = &pmgntframe->attrib;
+	update_mgntframe_attrib(padapter, pattrib);
+
+	_rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET);
+
+	pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET;
+	pwlanhdr = (struct rtw_ieee80211_hdr *)pframe;
+
+	fctrl = &(pwlanhdr->frame_ctl);
+	*(fctrl) = 0;
+
+	_rtw_memcpy(pwlanhdr->addr1, raddr, ETH_ALEN);
+	_rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN);
+	_rtw_memcpy(pwlanhdr->addr3, raddr,  ETH_ALEN);
+
+	SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq);
+	pmlmeext->mgnt_seq++;
+	set_frame_sub_type(pframe, WIFI_ACTION);
+
+	pframe += sizeof(struct rtw_ieee80211_hdr_3addr);
+	pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr);
+
+	pframe = rtw_set_fixed_ie(pframe, 1, &(category), &(pattrib->pktlen));
+	pframe = rtw_set_fixed_ie(pframe, 1, &(action), &(pattrib->pktlen));
+	pframe = rtw_set_fixed_ie(pframe, 4, (unsigned char *) &(p2poui), &(pattrib->pktlen));
+	pframe = rtw_set_fixed_ie(pframe, 1, &(oui_subtype), &(pattrib->pktlen));
+	pframe = rtw_set_fixed_ie(pframe, 1, &(dialogToken), &(pattrib->pktlen));
+
+	/*	P2P IE Section. */
+
+	/*	P2P OUI */
+	p2pielen = 0;
+	p2pie[p2pielen++] = 0x50;
+	p2pie[p2pielen++] = 0x6F;
+	p2pie[p2pielen++] = 0x9A;
+	p2pie[p2pielen++] = 0x09;	/*	WFA P2P v1.0 */
+
+	/*	Commented by Albert 20101011 */
+	/*	According to the P2P Specification, the P2P Invitation request frame should contain 7 P2P attributes */
+	/*	1. Configuration Timeout */
+	/*	2. Invitation Flags */
+	/*	3. Operating Channel	( Only GO ) */
+	/*	4. P2P Group BSSID	( Should be included if I am the GO ) */
+	/*	5. Channel List */
+	/*	6. P2P Group ID */
+	/*	7. P2P Device Info */
+
+	/*	Configuration Timeout */
+	/*	Type: */
+	p2pie[p2pielen++] = P2P_ATTR_CONF_TIMEOUT;
+
+	/*	Length: */
+	*(u16 *)(p2pie + p2pielen) = cpu_to_le16(0x0002);
+	p2pielen += 2;
+
+	/*	Value: */
+	p2pie[p2pielen++] = 200;	/*	2 seconds needed to be the P2P GO */
+	p2pie[p2pielen++] = 200;	/*	2 seconds needed to be the P2P Client */
+
+	/*	Invitation Flags */
+	/*	Type: */
+	p2pie[p2pielen++] = P2P_ATTR_INVITATION_FLAGS;
+
+	/*	Length: */
+	*(u16 *)(p2pie + p2pielen) = cpu_to_le16(0x0001);
+	p2pielen += 2;
+
+	/*	Value: */
+	p2pie[p2pielen++] = P2P_INVITATION_FLAGS_PERSISTENT;
+
+
+	/*	Operating Channel */
+	/*	Type: */
+	p2pie[p2pielen++] = P2P_ATTR_OPERATING_CH;
+
+	/*	Length: */
+	*(u16 *)(p2pie + p2pielen) = cpu_to_le16(0x0005);
+	p2pielen += 2;
+
+	/*	Value: */
+	/*	Country String */
+	p2pie[p2pielen++] = 'X';
+	p2pie[p2pielen++] = 'X';
+
+	/*	The third byte should be set to 0x04. */
+	/*	Described in the "Operating Channel Attribute" section. */
+	p2pie[p2pielen++] = 0x04;
+
+	/*	Operating Class */
+	if (pwdinfo->invitereq_info.operating_ch <= 14)
+		p2pie[p2pielen++] = 0x51;
+	else if ((pwdinfo->invitereq_info.operating_ch >= 36) && (pwdinfo->invitereq_info.operating_ch <= 48))
+		p2pie[p2pielen++] = 0x73;
+	else
+		p2pie[p2pielen++] = 0x7c;
+
+	/*	Channel Number */
+	p2pie[p2pielen++] = pwdinfo->invitereq_info.operating_ch;	/*	operating channel number */
+
+	if (_rtw_memcmp(adapter_mac_addr(padapter), pwdinfo->invitereq_info.go_bssid, ETH_ALEN)) {
+		/*	P2P Group BSSID */
+		/*	Type: */
+		p2pie[p2pielen++] = P2P_ATTR_GROUP_BSSID;
+
+		/*	Length: */
+		*(u16 *)(p2pie + p2pielen) = cpu_to_le16(ETH_ALEN);
+		p2pielen += 2;
+
+		/*	Value: */
+		/*	P2P Device Address for GO */
+		_rtw_memcpy(p2pie + p2pielen, pwdinfo->invitereq_info.go_bssid, ETH_ALEN);
+		p2pielen += ETH_ALEN;
+	}
+
+	/*	Channel List */
+	/*	Type: */
+	p2pie[p2pielen++] = P2P_ATTR_CH_LIST;
+
+
+	/*	Length: */
+	/* Country String(3) */
+	/* + ( Operating Class (1) + Number of Channels(1) ) * Operation Classes (?) */
+	/* + number of channels in all classes */
+	len_channellist_attr = 3
+		       + (1 + 1) * (u16)ch_list->reg_classes
+		       + get_reg_classes_full_count(ch_list);
+
+#ifdef CONFIG_CONCURRENT_MODE
+	if (rtw_mi_check_status(padapter, MI_LINKED) && padapter->registrypriv.full_ch_in_p2p_handshake == 0)
+		*(u16 *)(p2pie + p2pielen) = cpu_to_le16(5 + 1);
+	else
+		*(u16 *)(p2pie + p2pielen) = cpu_to_le16(len_channellist_attr);
+#else
+	*(u16 *)(p2pie + p2pielen) = cpu_to_le16(len_channellist_attr);
+#endif
+	p2pielen += 2;
+
+	/*	Value: */
+	/*	Country String */
+	p2pie[p2pielen++] = 'X';
+	p2pie[p2pielen++] = 'X';
+
+	/*	The third byte should be set to 0x04. */
+	/*	Described in the "Operating Channel Attribute" section. */
+	p2pie[p2pielen++] = 0x04;
+
+	/*	Channel Entry List */
+#ifdef CONFIG_CONCURRENT_MODE
+	if (rtw_mi_check_status(padapter, MI_LINKED) && padapter->registrypriv.full_ch_in_p2p_handshake == 0) {
+		u8 union_ch =  rtw_mi_get_union_chan(padapter);
+
+		/*	Operating Class */
+		if (union_ch > 14) {
+			if (union_ch >= 149)
+				p2pie[p2pielen++] = 0x7c;
+			else
+				p2pie[p2pielen++] = 0x73;
+		} else
+			p2pie[p2pielen++] = 0x51;
+
+
+		/*	Number of Channels */
+		/*	Just support 1 channel and this channel is AP's channel */
+		p2pie[p2pielen++] = 1;
+
+		/*	Channel List */
+		p2pie[p2pielen++] = union_ch;
+	} else
+#endif /* CONFIG_CONCURRENT_MODE */
+	{
+		int i, j;
+		for (j = 0; j < ch_list->reg_classes; j++) {
+			/*	Operating Class */
+			p2pie[p2pielen++] = ch_list->reg_class[j].reg_class;
+
+			/*	Number of Channels */
+			p2pie[p2pielen++] = ch_list->reg_class[j].channels;
+
+			/*	Channel List */
+			for (i = 0; i < ch_list->reg_class[j].channels; i++)
+				p2pie[p2pielen++] = ch_list->reg_class[j].channel[i];
+		}
+	}
+
+
+	/*	P2P Group ID */
+	/*	Type: */
+	p2pie[p2pielen++] = P2P_ATTR_GROUP_ID;
+
+	/*	Length: */
+	*(u16 *)(p2pie + p2pielen) = cpu_to_le16(6 + pwdinfo->invitereq_info.ssidlen);
+	p2pielen += 2;
+
+	/*	Value: */
+	/*	P2P Device Address for GO */
+	_rtw_memcpy(p2pie + p2pielen, pwdinfo->invitereq_info.go_bssid, ETH_ALEN);
+	p2pielen += ETH_ALEN;
+
+	/*	SSID */
+	_rtw_memcpy(p2pie + p2pielen, pwdinfo->invitereq_info.go_ssid, pwdinfo->invitereq_info.ssidlen);
+	p2pielen += pwdinfo->invitereq_info.ssidlen;
+
+
+	/*	Device Info */
+	/*	Type: */
+	p2pie[p2pielen++] = P2P_ATTR_DEVICE_INFO;
+
+	/*	Length: */
+	/*	21->P2P Device Address (6bytes) + Config Methods (2bytes) + Primary Device Type (8bytes)  */
+	/*	+ NumofSecondDevType (1byte) + WPS Device Name ID field (2bytes) + WPS Device Name Len field (2bytes) */
+	*(u16 *)(p2pie + p2pielen) = cpu_to_le16(21 + pwdinfo->device_name_len);
+	p2pielen += 2;
+
+	/*	Value: */
+	/*	P2P Device Address */
+	_rtw_memcpy(p2pie + p2pielen, adapter_mac_addr(padapter), ETH_ALEN);
+	p2pielen += ETH_ALEN;
+
+	/*	Config Method */
+	/*	This field should be big endian. Noted by P2P specification. */
+	*(u16 *)(p2pie + p2pielen) = cpu_to_be16(WPS_CONFIG_METHOD_DISPLAY);
+	p2pielen += 2;
+
+	/*	Primary Device Type */
+	/*	Category ID */
+	*(u16 *)(p2pie + p2pielen) = cpu_to_be16(WPS_PDT_CID_MULIT_MEDIA);
+	p2pielen += 2;
+
+	/*	OUI */
+	*(u32 *)(p2pie + p2pielen) = cpu_to_be32(WPSOUI);
+	p2pielen += 4;
+
+	/*	Sub Category ID */
+	*(u16 *)(p2pie + p2pielen) = cpu_to_be16(WPS_PDT_SCID_MEDIA_SERVER);
+	p2pielen += 2;
+
+	/*	Number of Secondary Device Types */
+	p2pie[p2pielen++] = 0x00;	/*	No Secondary Device Type List */
+
+	/*	Device Name */
+	/*	Type: */
+	*(u16 *)(p2pie + p2pielen) = cpu_to_be16(WPS_ATTR_DEVICE_NAME);
+	p2pielen += 2;
+
+	/*	Length: */
+	*(u16 *)(p2pie + p2pielen) = cpu_to_be16(pwdinfo->device_name_len);
+	p2pielen += 2;
+
+	/*	Value: */
+	_rtw_memcpy(p2pie + p2pielen, pwdinfo->device_name, pwdinfo->device_name_len);
+	p2pielen += pwdinfo->device_name_len;
+
+	pframe = rtw_set_ie(pframe, _VENDOR_SPECIFIC_IE_, p2pielen, (unsigned char *) p2pie, &pattrib->pktlen);
+
+#ifdef CONFIG_WFD
+	wfdielen = build_invitation_req_wfd_ie(pwdinfo, pframe);
+	pframe += wfdielen;
+	pattrib->pktlen += wfdielen;
+#endif
+
+	pattrib->last_txcmdsz = pattrib->pktlen;
+
+	dump_mgntframe(padapter, pmgntframe);
+
+	return;
+
+}
+
+void issue_p2p_invitation_response(_adapter *padapter, u8 *raddr, u8 dialogToken, u8 status_code)
+{
+	struct p2p_channels *ch_list = &(adapter_to_rfctl(padapter)->channel_list);
+	unsigned char category = RTW_WLAN_CATEGORY_PUBLIC;
+	u8			action = P2P_PUB_ACTION_ACTION;
+	u32			p2poui = cpu_to_be32(P2POUI);
+	u8			oui_subtype = P2P_INVIT_RESP;
+	u8			p2pie[255] = { 0x00 };
+	u8			p2pielen = 0;
+	u16			len_channellist_attr = 0;
+#ifdef CONFIG_WFD
+	u32					wfdielen = 0;
+#endif
+
+	struct xmit_frame			*pmgntframe;
+	struct pkt_attrib			*pattrib;
+	unsigned char					*pframe;
+	struct rtw_ieee80211_hdr	*pwlanhdr;
+	unsigned short				*fctrl;
+	struct xmit_priv			*pxmitpriv = &(padapter->xmitpriv);
+	struct mlme_ext_priv	*pmlmeext = &(padapter->mlmeextpriv);
+	struct wifidirect_info	*pwdinfo = &(padapter->wdinfo);
+
+
+	pmgntframe = alloc_mgtxmitframe(pxmitpriv);
+	if (pmgntframe == NULL)
+		return;
+
+	/* update attribute */
+	pattrib = &pmgntframe->attrib;
+	update_mgntframe_attrib(padapter, pattrib);
+
+	_rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET);
+
+	pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET;
+	pwlanhdr = (struct rtw_ieee80211_hdr *)pframe;
+
+	fctrl = &(pwlanhdr->frame_ctl);
+	*(fctrl) = 0;
+
+	_rtw_memcpy(pwlanhdr->addr1, raddr, ETH_ALEN);
+	_rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN);
+	_rtw_memcpy(pwlanhdr->addr3, raddr,  ETH_ALEN);
+
+	SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq);
+	pmlmeext->mgnt_seq++;
+	set_frame_sub_type(pframe, WIFI_ACTION);
+
+	pframe += sizeof(struct rtw_ieee80211_hdr_3addr);
+	pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr);
+
+	pframe = rtw_set_fixed_ie(pframe, 1, &(category), &(pattrib->pktlen));
+	pframe = rtw_set_fixed_ie(pframe, 1, &(action), &(pattrib->pktlen));
+	pframe = rtw_set_fixed_ie(pframe, 4, (unsigned char *) &(p2poui), &(pattrib->pktlen));
+	pframe = rtw_set_fixed_ie(pframe, 1, &(oui_subtype), &(pattrib->pktlen));
+	pframe = rtw_set_fixed_ie(pframe, 1, &(dialogToken), &(pattrib->pktlen));
+
+	/*	P2P IE Section. */
+
+	/*	P2P OUI */
+	p2pielen = 0;
+	p2pie[p2pielen++] = 0x50;
+	p2pie[p2pielen++] = 0x6F;
+	p2pie[p2pielen++] = 0x9A;
+	p2pie[p2pielen++] = 0x09;	/*	WFA P2P v1.0 */
+
+	/*	Commented by Albert 20101005 */
+	/*	According to the P2P Specification, the P2P Invitation response frame should contain 5 P2P attributes */
+	/*	1. Status */
+	/*	2. Configuration Timeout */
+	/*	3. Operating Channel	( Only GO ) */
+	/*	4. P2P Group BSSID	( Only GO ) */
+	/*	5. Channel List */
+
+	/*	P2P Status */
+	/*	Type: */
+	p2pie[p2pielen++] = P2P_ATTR_STATUS;
+
+	/*	Length: */
+	*(u16 *)(p2pie + p2pielen) = cpu_to_le16(0x0001);
+	p2pielen += 2;
+
+	/*	Value: */
+	/*	When status code is P2P_STATUS_FAIL_INFO_UNAVAILABLE. */
+	/*	Sent the event receiving the P2P Invitation Req frame to DMP UI. */
+	/*	DMP had to compare the MAC address to find out the profile. */
+	/*	So, the WiFi driver will send the P2P_STATUS_FAIL_INFO_UNAVAILABLE to NB. */
+	/*	If the UI found the corresponding profile, the WiFi driver sends the P2P Invitation Req */
+	/*	to NB to rebuild the persistent group. */
+	p2pie[p2pielen++] = status_code;
+
+	/*	Configuration Timeout */
+	/*	Type: */
+	p2pie[p2pielen++] = P2P_ATTR_CONF_TIMEOUT;
+
+	/*	Length: */
+	*(u16 *)(p2pie + p2pielen) = cpu_to_le16(0x0002);
+	p2pielen += 2;
+
+	/*	Value: */
+	p2pie[p2pielen++] = 200;	/*	2 seconds needed to be the P2P GO */
+	p2pie[p2pielen++] = 200;	/*	2 seconds needed to be the P2P Client */
+
+	if (status_code == P2P_STATUS_SUCCESS) {
+		if (rtw_p2p_chk_role(pwdinfo, P2P_ROLE_GO)) {
+			/*	The P2P Invitation request frame asks this Wi-Fi device to be the P2P GO */
+			/*	In this case, the P2P Invitation response frame should carry the two more P2P attributes. */
+			/*	First one is operating channel attribute. */
+			/*	Second one is P2P Group BSSID attribute. */
+
+			/*	Operating Channel */
+			/*	Type: */
+			p2pie[p2pielen++] = P2P_ATTR_OPERATING_CH;
+
+			/*	Length: */
+			*(u16 *)(p2pie + p2pielen) = cpu_to_le16(0x0005);
+			p2pielen += 2;
+
+			/*	Value: */
+			/*	Country String */
+			p2pie[p2pielen++] = 'X';
+			p2pie[p2pielen++] = 'X';
+
+			/*	The third byte should be set to 0x04. */
+			/*	Described in the "Operating Channel Attribute" section. */
+			p2pie[p2pielen++] = 0x04;
+
+			/*	Operating Class */
+			p2pie[p2pielen++] = 0x51;	/*	Copy from SD7 */
+
+			/*	Channel Number */
+			p2pie[p2pielen++] = pwdinfo->operating_channel;	/*	operating channel number */
+
+
+			/*	P2P Group BSSID */
+			/*	Type: */
+			p2pie[p2pielen++] = P2P_ATTR_GROUP_BSSID;
+
+			/*	Length: */
+			*(u16 *)(p2pie + p2pielen) = cpu_to_le16(ETH_ALEN);
+			p2pielen += 2;
+
+			/*	Value: */
+			/*	P2P Device Address for GO */
+			_rtw_memcpy(p2pie + p2pielen, adapter_mac_addr(padapter), ETH_ALEN);
+			p2pielen += ETH_ALEN;
+
+		}
+
+		/*	Channel List */
+		/*	Type: */
+		p2pie[p2pielen++] = P2P_ATTR_CH_LIST;
+
+		/*	Length: */
+		/* Country String(3) */
+		/* + ( Operating Class (1) + Number of Channels(1) ) * Operation Classes (?) */
+		/* + number of channels in all classes */
+		len_channellist_attr = 3
+			+ (1 + 1) * (u16)ch_list->reg_classes
+			+ get_reg_classes_full_count(ch_list);
+
+#ifdef CONFIG_CONCURRENT_MODE
+		if (rtw_mi_check_status(padapter, MI_LINKED) && padapter->registrypriv.full_ch_in_p2p_handshake == 0)
+			*(u16 *)(p2pie + p2pielen) = cpu_to_le16(5 + 1);
+		else
+			*(u16 *)(p2pie + p2pielen) = cpu_to_le16(len_channellist_attr);
+#else
+		*(u16 *)(p2pie + p2pielen) = cpu_to_le16(len_channellist_attr);
+#endif
+		p2pielen += 2;
+
+		/*	Value: */
+		/*	Country String */
+		p2pie[p2pielen++] = 'X';
+		p2pie[p2pielen++] = 'X';
+
+		/*	The third byte should be set to 0x04. */
+		/*	Described in the "Operating Channel Attribute" section. */
+		p2pie[p2pielen++] = 0x04;
+
+		/*	Channel Entry List */
+#ifdef CONFIG_CONCURRENT_MODE
+		if (rtw_mi_check_status(padapter, MI_LINKED) && padapter->registrypriv.full_ch_in_p2p_handshake == 0) {
+			u8 union_ch = rtw_mi_get_union_chan(padapter);
+
+			/*	Operating Class */
+			if (union_ch > 14) {
+				if (union_ch >= 149)
+					p2pie[p2pielen++]  = 0x7c;
+				else
+					p2pie[p2pielen++] = 0x73;
+			} else
+				p2pie[p2pielen++] = 0x51;
+
+
+			/*	Number of Channels */
+			/*	Just support 1 channel and this channel is AP's channel */
+			p2pie[p2pielen++] = 1;
+
+			/*	Channel List */
+			p2pie[p2pielen++] = union_ch;
+		} else
+#endif /* CONFIG_CONCURRENT_MODE */
+		{
+			int i, j;
+			for (j = 0; j < ch_list->reg_classes; j++) {
+				/*	Operating Class */
+				p2pie[p2pielen++] = ch_list->reg_class[j].reg_class;
+
+				/*	Number of Channels */
+				p2pie[p2pielen++] = ch_list->reg_class[j].channels;
+
+				/*	Channel List */
+				for (i = 0; i < ch_list->reg_class[j].channels; i++)
+					p2pie[p2pielen++] = ch_list->reg_class[j].channel[i];
+			}
+		}
+	}
+
+	pframe = rtw_set_ie(pframe, _VENDOR_SPECIFIC_IE_, p2pielen, (unsigned char *) p2pie, &pattrib->pktlen);
+
+#ifdef CONFIG_WFD
+	wfdielen = build_invitation_resp_wfd_ie(pwdinfo, pframe);
+	pframe += wfdielen;
+	pattrib->pktlen += wfdielen;
+#endif
+
+	pattrib->last_txcmdsz = pattrib->pktlen;
+
+	dump_mgntframe(padapter, pmgntframe);
+
+	return;
+
+}
+
+void issue_p2p_provision_request(_adapter *padapter, u8 *pssid, u8 ussidlen, u8 *pdev_raddr)
+{
+	unsigned char category = RTW_WLAN_CATEGORY_PUBLIC;
+	u8			action = P2P_PUB_ACTION_ACTION;
+	u8			dialogToken = 1;
+	u32			p2poui = cpu_to_be32(P2POUI);
+	u8			oui_subtype = P2P_PROVISION_DISC_REQ;
+	u8			wpsie[100] = { 0x00 };
+	u8			wpsielen = 0;
+	u32			p2pielen = 0;
+#ifdef CONFIG_WFD
+	u32					wfdielen = 0;
+#endif
+
+	struct xmit_frame			*pmgntframe;
+	struct pkt_attrib			*pattrib;
+	unsigned char					*pframe;
+	struct rtw_ieee80211_hdr	*pwlanhdr;
+	unsigned short				*fctrl;
+	struct xmit_priv			*pxmitpriv = &(padapter->xmitpriv);
+	struct mlme_ext_priv	*pmlmeext = &(padapter->mlmeextpriv);
+	struct wifidirect_info	*pwdinfo = &(padapter->wdinfo);
+
+
+	pmgntframe = alloc_mgtxmitframe(pxmitpriv);
+	if (pmgntframe == NULL)
+		return;
+
+	RTW_INFO("[%s] In\n", __FUNCTION__);
+	/* update attribute */
+	pattrib = &pmgntframe->attrib;
+	update_mgntframe_attrib(padapter, pattrib);
+
+	_rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET);
+
+	pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET;
+	pwlanhdr = (struct rtw_ieee80211_hdr *)pframe;
+
+	fctrl = &(pwlanhdr->frame_ctl);
+	*(fctrl) = 0;
+
+	_rtw_memcpy(pwlanhdr->addr1, pdev_raddr, ETH_ALEN);
+	_rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN);
+	_rtw_memcpy(pwlanhdr->addr3, pdev_raddr, ETH_ALEN);
+
+	SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq);
+	pmlmeext->mgnt_seq++;
+	set_frame_sub_type(pframe, WIFI_ACTION);
+
+	pframe += sizeof(struct rtw_ieee80211_hdr_3addr);
+	pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr);
+
+	pframe = rtw_set_fixed_ie(pframe, 1, &(category), &(pattrib->pktlen));
+	pframe = rtw_set_fixed_ie(pframe, 1, &(action), &(pattrib->pktlen));
+	pframe = rtw_set_fixed_ie(pframe, 4, (unsigned char *) &(p2poui), &(pattrib->pktlen));
+	pframe = rtw_set_fixed_ie(pframe, 1, &(oui_subtype), &(pattrib->pktlen));
+	pframe = rtw_set_fixed_ie(pframe, 1, &(dialogToken), &(pattrib->pktlen));
+
+	p2pielen = build_prov_disc_request_p2p_ie(pwdinfo, pframe, pssid, ussidlen, pdev_raddr);
+
+	pframe += p2pielen;
+	pattrib->pktlen += p2pielen;
+
+	wpsielen = 0;
+	/*	WPS OUI */
+	*(u32 *)(wpsie) = cpu_to_be32(WPSOUI);
+	wpsielen += 4;
+
+	/*	WPS version */
+	/*	Type: */
+	*(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_ATTR_VER1);
+	wpsielen += 2;
+
+	/*	Length: */
+	*(u16 *)(wpsie + wpsielen) = cpu_to_be16(0x0001);
+	wpsielen += 2;
+
+	/*	Value: */
+	wpsie[wpsielen++] = WPS_VERSION_1;	/*	Version 1.0 */
+
+	/*	Config Method */
+	/*	Type: */
+	*(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_ATTR_CONF_METHOD);
+	wpsielen += 2;
+
+	/*	Length: */
+	*(u16 *)(wpsie + wpsielen) = cpu_to_be16(0x0002);
+	wpsielen += 2;
+
+	/*	Value: */
+	*(u16 *)(wpsie + wpsielen) = cpu_to_be16(pwdinfo->tx_prov_disc_info.wps_config_method_request);
+	wpsielen += 2;
+
+	pframe = rtw_set_ie(pframe, _VENDOR_SPECIFIC_IE_, wpsielen, (unsigned char *) wpsie, &pattrib->pktlen);
+
+
+#ifdef CONFIG_WFD
+	wfdielen = build_provdisc_req_wfd_ie(pwdinfo, pframe);
+	pframe += wfdielen;
+	pattrib->pktlen += wfdielen;
+#endif
+
+	pattrib->last_txcmdsz = pattrib->pktlen;
+
+	dump_mgntframe(padapter, pmgntframe);
+
+	return;
+
+}
+
+
+u8 is_matched_in_profilelist(u8 *peermacaddr, struct profile_info *profileinfo)
+{
+	u8 i, match_result = 0;
+
+	RTW_INFO("[%s] peermac = %.2X %.2X %.2X %.2X %.2X %.2X\n", __FUNCTION__,
+		peermacaddr[0], peermacaddr[1], peermacaddr[2], peermacaddr[3], peermacaddr[4], peermacaddr[5]);
+
+	for (i = 0; i < P2P_MAX_PERSISTENT_GROUP_NUM; i++, profileinfo++) {
+		RTW_INFO("[%s] profileinfo_mac = %.2X %.2X %.2X %.2X %.2X %.2X\n", __FUNCTION__,
+			profileinfo->peermac[0], profileinfo->peermac[1], profileinfo->peermac[2], profileinfo->peermac[3], profileinfo->peermac[4], profileinfo->peermac[5]);
+		if (_rtw_memcmp(peermacaddr, profileinfo->peermac, ETH_ALEN)) {
+			match_result = 1;
+			RTW_INFO("[%s] Match!\n", __FUNCTION__);
+			break;
+		}
+	}
+
+	return match_result ;
+}
+
+void issue_probersp_p2p(_adapter *padapter, unsigned char *da)
+{
+	struct xmit_frame			*pmgntframe;
+	struct pkt_attrib			*pattrib;
+	unsigned char					*pframe;
+	struct rtw_ieee80211_hdr	*pwlanhdr;
+	unsigned short				*fctrl;
+	unsigned char					*mac;
+	struct xmit_priv	*pxmitpriv = &(padapter->xmitpriv);
+	struct mlme_ext_priv	*pmlmeext = &(padapter->mlmeextpriv);
+	struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
+	/* WLAN_BSSID_EX 		*cur_network = &(pmlmeinfo->network); */
+	u16					beacon_interval = 100;
+	u16					capInfo = 0;
+	struct wifidirect_info	*pwdinfo = &(padapter->wdinfo);
+	u8					wpsie[255] = { 0x00 };
+	u32					wpsielen = 0, p2pielen = 0;
+#ifdef CONFIG_WFD
+	u32					wfdielen = 0;
+#endif
+#ifdef CONFIG_INTEL_WIDI
+	u8 zero_array_check[L2SDTA_SERVICE_VE_LEN] = { 0x00 };
+#endif /* CONFIG_INTEL_WIDI */
+
+	/* RTW_INFO("%s\n", __FUNCTION__); */
+
+	pmgntframe = alloc_mgtxmitframe(pxmitpriv);
+	if (pmgntframe == NULL)
+		return;
+
+	/* update attribute */
+	pattrib = &pmgntframe->attrib;
+	update_mgntframe_attrib(padapter, pattrib);
+
+	if (IS_CCK_RATE(pattrib->rate)) {
+		/* force OFDM 6M rate */
+		pattrib->rate = MGN_6M;
+		pattrib->raid = rtw_get_mgntframe_raid(padapter, WIRELESS_11G);
+	}
+
+	_rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET);
+
+	pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET;
+	pwlanhdr = (struct rtw_ieee80211_hdr *)pframe;
+
+	mac = adapter_mac_addr(padapter);
+
+	fctrl = &(pwlanhdr->frame_ctl);
+	*(fctrl) = 0;
+	_rtw_memcpy(pwlanhdr->addr1, da, ETH_ALEN);
+	_rtw_memcpy(pwlanhdr->addr2, mac, ETH_ALEN);
+
+	/*	Use the device address for BSSID field.	 */
+	_rtw_memcpy(pwlanhdr->addr3, mac, ETH_ALEN);
+
+	SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq);
+	pmlmeext->mgnt_seq++;
+	set_frame_sub_type(fctrl, WIFI_PROBERSP);
+
+	pattrib->hdrlen = sizeof(struct rtw_ieee80211_hdr_3addr);
+	pattrib->pktlen = pattrib->hdrlen;
+	pframe += pattrib->hdrlen;
+
+	/* timestamp will be inserted by hardware */
+	pframe += 8;
+	pattrib->pktlen += 8;
+
+	/* beacon interval: 2 bytes */
+	_rtw_memcpy(pframe, (unsigned char *) &beacon_interval, 2);
+	pframe += 2;
+	pattrib->pktlen += 2;
+
+	/*	capability info: 2 bytes */
+	/*	ESS and IBSS bits must be 0 (defined in the 3.1.2.1.1 of WiFi Direct Spec) */
+	capInfo |= cap_ShortPremble;
+	capInfo |= cap_ShortSlot;
+
+	_rtw_memcpy(pframe, (unsigned char *) &capInfo, 2);
+	pframe += 2;
+	pattrib->pktlen += 2;
+
+
+	/* SSID */
+	pframe = rtw_set_ie(pframe, _SSID_IE_, 7, pwdinfo->p2p_wildcard_ssid, &pattrib->pktlen);
+
+	/* supported rates... */
+	/*	Use the OFDM rate in the P2P probe response frame. ( 6(B), 9(B), 12, 18, 24, 36, 48, 54 ) */
+	pframe = rtw_set_ie(pframe, _SUPPORTEDRATES_IE_, 8, pwdinfo->support_rate, &pattrib->pktlen);
+
+	/* DS parameter set */
+	pframe = rtw_set_ie(pframe, _DSSET_IE_, 1, (unsigned char *)&pwdinfo->listen_channel, &pattrib->pktlen);
+
+#ifdef CONFIG_IOCTL_CFG80211
+	if (adapter_wdev_data(padapter)->p2p_enabled && pwdinfo->driver_interface == DRIVER_CFG80211) {
+		if (pmlmepriv->wps_probe_resp_ie != NULL && pmlmepriv->p2p_probe_resp_ie != NULL) {
+			/* WPS IE */
+			_rtw_memcpy(pframe, pmlmepriv->wps_probe_resp_ie, pmlmepriv->wps_probe_resp_ie_len);
+			pattrib->pktlen += pmlmepriv->wps_probe_resp_ie_len;
+			pframe += pmlmepriv->wps_probe_resp_ie_len;
+
+			/* P2P IE */
+			_rtw_memcpy(pframe, pmlmepriv->p2p_probe_resp_ie, pmlmepriv->p2p_probe_resp_ie_len);
+			pattrib->pktlen += pmlmepriv->p2p_probe_resp_ie_len;
+			pframe += pmlmepriv->p2p_probe_resp_ie_len;
+		}
+	} else
+#endif /* CONFIG_IOCTL_CFG80211		 */
+	{
+
+		/*	Todo: WPS IE */
+		/*	Noted by Albert 20100907 */
+		/*	According to the WPS specification, all the WPS attribute is presented by Big Endian. */
+
+		wpsielen = 0;
+		/*	WPS OUI */
+		*(u32 *)(wpsie) = cpu_to_be32(WPSOUI);
+		wpsielen += 4;
+
+		/*	WPS version */
+		/*	Type: */
+		*(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_ATTR_VER1);
+		wpsielen += 2;
+
+		/*	Length: */
+		*(u16 *)(wpsie + wpsielen) = cpu_to_be16(0x0001);
+		wpsielen += 2;
+
+		/*	Value: */
+		wpsie[wpsielen++] = WPS_VERSION_1;	/*	Version 1.0 */
+
+#ifdef CONFIG_INTEL_WIDI
+		/*	Commented by Kurt */
+		/*	Appended WiDi info. only if we did issued_probereq_widi(), and then we saved ven. ext. in pmlmepriv->sa_ext. */
+		if (_rtw_memcmp(pmlmepriv->sa_ext, zero_array_check, L2SDTA_SERVICE_VE_LEN) == _FALSE
+		    || pmlmepriv->num_p2p_sdt != 0) {
+			/* Sec dev type */
+			*(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_ATTR_SEC_DEV_TYPE_LIST);
+			wpsielen += 2;
+
+			/*	Length: */
+			*(u16 *)(wpsie + wpsielen) = cpu_to_be16(0x0008);
+			wpsielen += 2;
+
+			/*	Value: */
+			/*	Category ID */
+			*(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_PDT_CID_DISPLAYS);
+			wpsielen += 2;
+
+			/*	OUI */
+			*(u32 *)(wpsie + wpsielen) = cpu_to_be32(INTEL_DEV_TYPE_OUI);
+			wpsielen += 4;
+
+			*(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_PDT_SCID_WIDI_CONSUMER_SINK);
+			wpsielen += 2;
+
+			if (_rtw_memcmp(pmlmepriv->sa_ext, zero_array_check, L2SDTA_SERVICE_VE_LEN) == _FALSE) {
+				/*	Vendor Extension */
+				_rtw_memcpy(wpsie + wpsielen, pmlmepriv->sa_ext, L2SDTA_SERVICE_VE_LEN);
+				wpsielen += L2SDTA_SERVICE_VE_LEN;
+			}
+		}
+#endif /* CONFIG_INTEL_WIDI */
+
+		/*	WiFi Simple Config State */
+		/*	Type: */
+		*(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_ATTR_SIMPLE_CONF_STATE);
+		wpsielen += 2;
+
+		/*	Length: */
+		*(u16 *)(wpsie + wpsielen) = cpu_to_be16(0x0001);
+		wpsielen += 2;
+
+		/*	Value: */
+		wpsie[wpsielen++] = WPS_WSC_STATE_NOT_CONFIG;	/*	Not Configured. */
+
+		/*	Response Type */
+		/*	Type: */
+		*(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_ATTR_RESP_TYPE);
+		wpsielen += 2;
+
+		/*	Length: */
+		*(u16 *)(wpsie + wpsielen) = cpu_to_be16(0x0001);
+		wpsielen += 2;
+
+		/*	Value: */
+		wpsie[wpsielen++] = WPS_RESPONSE_TYPE_8021X;
+
+		/*	UUID-E */
+		/*	Type: */
+		*(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_ATTR_UUID_E);
+		wpsielen += 2;
+
+		/*	Length: */
+		*(u16 *)(wpsie + wpsielen) = cpu_to_be16(0x0010);
+		wpsielen += 2;
+
+		/*	Value: */
+		if (pwdinfo->external_uuid == 0) {
+			_rtw_memset(wpsie + wpsielen, 0x0, 16);
+			_rtw_memcpy(wpsie + wpsielen, mac, ETH_ALEN);
+		} else
+			_rtw_memcpy(wpsie + wpsielen, pwdinfo->uuid, 0x10);
+		wpsielen += 0x10;
+
+		/*	Manufacturer */
+		/*	Type: */
+		*(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_ATTR_MANUFACTURER);
+		wpsielen += 2;
+
+		/*	Length: */
+		*(u16 *)(wpsie + wpsielen) = cpu_to_be16(0x0007);
+		wpsielen += 2;
+
+		/*	Value: */
+		_rtw_memcpy(wpsie + wpsielen, "Realtek", 7);
+		wpsielen += 7;
+
+		/*	Model Name */
+		/*	Type: */
+		*(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_ATTR_MODEL_NAME);
+		wpsielen += 2;
+
+		/*	Length: */
+		*(u16 *)(wpsie + wpsielen) = cpu_to_be16(0x0006);
+		wpsielen += 2;
+
+		/*	Value: */
+		_rtw_memcpy(wpsie + wpsielen, "8192CU", 6);
+		wpsielen += 6;
+
+		/*	Model Number */
+		/*	Type: */
+		*(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_ATTR_MODEL_NUMBER);
+		wpsielen += 2;
+
+		/*	Length: */
+		*(u16 *)(wpsie + wpsielen) = cpu_to_be16(0x0001);
+		wpsielen += 2;
+
+		/*	Value: */
+		wpsie[wpsielen++] = 0x31;		/*	character 1 */
+
+		/*	Serial Number */
+		/*	Type: */
+		*(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_ATTR_SERIAL_NUMBER);
+		wpsielen += 2;
+
+		/*	Length: */
+		*(u16 *)(wpsie + wpsielen) = cpu_to_be16(ETH_ALEN);
+		wpsielen += 2;
+
+		/*	Value: */
+		_rtw_memcpy(wpsie + wpsielen, "123456" , ETH_ALEN);
+		wpsielen += ETH_ALEN;
+
+		/*	Primary Device Type */
+		/*	Type: */
+		*(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_ATTR_PRIMARY_DEV_TYPE);
+		wpsielen += 2;
+
+		/*	Length: */
+		*(u16 *)(wpsie + wpsielen) = cpu_to_be16(0x0008);
+		wpsielen += 2;
+
+		/*	Value: */
+		/*	Category ID */
+		*(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_PDT_CID_MULIT_MEDIA);
+		wpsielen += 2;
+
+		/*	OUI */
+		*(u32 *)(wpsie + wpsielen) = cpu_to_be32(WPSOUI);
+		wpsielen += 4;
+
+		/*	Sub Category ID */
+		*(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_PDT_SCID_MEDIA_SERVER);
+		wpsielen += 2;
+
+		/*	Device Name */
+		/*	Type: */
+		*(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_ATTR_DEVICE_NAME);
+		wpsielen += 2;
+
+		/*	Length: */
+		*(u16 *)(wpsie + wpsielen) = cpu_to_be16(pwdinfo->device_name_len);
+		wpsielen += 2;
+
+		/*	Value: */
+		_rtw_memcpy(wpsie + wpsielen, pwdinfo->device_name, pwdinfo->device_name_len);
+		wpsielen += pwdinfo->device_name_len;
+
+		/*	Config Method */
+		/*	Type: */
+		*(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_ATTR_CONF_METHOD);
+		wpsielen += 2;
+
+		/*	Length: */
+		*(u16 *)(wpsie + wpsielen) = cpu_to_be16(0x0002);
+		wpsielen += 2;
+
+		/*	Value: */
+		*(u16 *)(wpsie + wpsielen) = cpu_to_be16(pwdinfo->supported_wps_cm);
+		wpsielen += 2;
+
+
+		pframe = rtw_set_ie(pframe, _VENDOR_SPECIFIC_IE_, wpsielen, (unsigned char *) wpsie, &pattrib->pktlen);
+
+
+		p2pielen = build_probe_resp_p2p_ie(pwdinfo, pframe);
+		pframe += p2pielen;
+		pattrib->pktlen += p2pielen;
+	}
+
+#ifdef CONFIG_WFD
+	wfdielen = rtw_append_probe_resp_wfd_ie(padapter, pframe);
+	pframe += wfdielen;
+	pattrib->pktlen += wfdielen;
+#endif
+
+	pattrib->last_txcmdsz = pattrib->pktlen;
+
+
+	dump_mgntframe(padapter, pmgntframe);
+
+	return;
+
+}
+
+int _issue_probereq_p2p(_adapter *padapter, u8 *da, int wait_ack)
+{
+	int ret = _FAIL;
+	struct xmit_frame		*pmgntframe;
+	struct pkt_attrib		*pattrib;
+	unsigned char			*pframe;
+	struct rtw_ieee80211_hdr	*pwlanhdr;
+	unsigned short		*fctrl;
+	unsigned char			*mac;
+	struct xmit_priv		*pxmitpriv = &(padapter->xmitpriv);
+	struct mlme_ext_priv	*pmlmeext = &(padapter->mlmeextpriv);
+	u8	bc_addr[] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
+	struct wifidirect_info	*pwdinfo = &(padapter->wdinfo);
+	u8					wpsie[255] = { 0x00 }, p2pie[255] = { 0x00 };
+	u16					wpsielen = 0, p2pielen = 0;
+#ifdef CONFIG_WFD
+	u32					wfdielen = 0;
+#endif
+
+	struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
+
+
+	pmgntframe = alloc_mgtxmitframe(pxmitpriv);
+	if (pmgntframe == NULL)
+		goto exit;
+
+	/* update attribute */
+	pattrib = &pmgntframe->attrib;
+	update_mgntframe_attrib(padapter, pattrib);
+
+	if (IS_CCK_RATE(pattrib->rate)) {
+		/* force OFDM 6M rate */
+		pattrib->rate = MGN_6M;
+		pattrib->raid = rtw_get_mgntframe_raid(padapter, WIRELESS_11G);
+	}
+
+	_rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET);
+
+	pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET;
+	pwlanhdr = (struct rtw_ieee80211_hdr *)pframe;
+
+	mac = adapter_mac_addr(padapter);
+
+	fctrl = &(pwlanhdr->frame_ctl);
+	*(fctrl) = 0;
+
+	if (da) {
+		_rtw_memcpy(pwlanhdr->addr1, da, ETH_ALEN);
+		_rtw_memcpy(pwlanhdr->addr3, da, ETH_ALEN);
+	} else {
+		if ((pwdinfo->p2p_info.scan_op_ch_only) || (pwdinfo->rx_invitereq_info.scan_op_ch_only)) {
+			/*	This two flags will be set when this is only the P2P client mode. */
+			_rtw_memcpy(pwlanhdr->addr1, pwdinfo->p2p_peer_interface_addr, ETH_ALEN);
+			_rtw_memcpy(pwlanhdr->addr3, pwdinfo->p2p_peer_interface_addr, ETH_ALEN);
+		} else {
+			/*	broadcast probe request frame */
+			_rtw_memcpy(pwlanhdr->addr1, bc_addr, ETH_ALEN);
+			_rtw_memcpy(pwlanhdr->addr3, bc_addr, ETH_ALEN);
+		}
+	}
+	_rtw_memcpy(pwlanhdr->addr2, mac, ETH_ALEN);
+
+	SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq);
+	pmlmeext->mgnt_seq++;
+	set_frame_sub_type(pframe, WIFI_PROBEREQ);
+
+	pframe += sizeof(struct rtw_ieee80211_hdr_3addr);
+	pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr);
+
+	if (rtw_p2p_chk_state(pwdinfo, P2P_STATE_TX_PROVISION_DIS_REQ))
+		pframe = rtw_set_ie(pframe, _SSID_IE_, pwdinfo->tx_prov_disc_info.ssid.SsidLength, pwdinfo->tx_prov_disc_info.ssid.Ssid, &(pattrib->pktlen));
+	else
+		pframe = rtw_set_ie(pframe, _SSID_IE_, P2P_WILDCARD_SSID_LEN, pwdinfo->p2p_wildcard_ssid, &(pattrib->pktlen));
+	/*	Use the OFDM rate in the P2P probe request frame. ( 6(B), 9(B), 12(B), 24(B), 36, 48, 54 ) */
+	pframe = rtw_set_ie(pframe, _SUPPORTEDRATES_IE_, 8, pwdinfo->support_rate, &pattrib->pktlen);
+
+#ifdef CONFIG_IOCTL_CFG80211
+	if (adapter_wdev_data(padapter)->p2p_enabled && pwdinfo->driver_interface == DRIVER_CFG80211) {
+		if (pmlmepriv->wps_probe_req_ie != NULL && pmlmepriv->p2p_probe_req_ie != NULL) {
+			/* WPS IE */
+			_rtw_memcpy(pframe, pmlmepriv->wps_probe_req_ie, pmlmepriv->wps_probe_req_ie_len);
+			pattrib->pktlen += pmlmepriv->wps_probe_req_ie_len;
+			pframe += pmlmepriv->wps_probe_req_ie_len;
+
+			/* P2P IE */
+			_rtw_memcpy(pframe, pmlmepriv->p2p_probe_req_ie, pmlmepriv->p2p_probe_req_ie_len);
+			pattrib->pktlen += pmlmepriv->p2p_probe_req_ie_len;
+			pframe += pmlmepriv->p2p_probe_req_ie_len;
+		}
+	} else
+#endif /* CONFIG_IOCTL_CFG80211 */
+	{
+
+		/*	WPS IE */
+		/*	Noted by Albert 20110221 */
+		/*	According to the WPS specification, all the WPS attribute is presented by Big Endian. */
+
+		wpsielen = 0;
+		/*	WPS OUI */
+		*(u32 *)(wpsie) = cpu_to_be32(WPSOUI);
+		wpsielen += 4;
+
+		/*	WPS version */
+		/*	Type: */
+		*(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_ATTR_VER1);
+		wpsielen += 2;
+
+		/*	Length: */
+		*(u16 *)(wpsie + wpsielen) = cpu_to_be16(0x0001);
+		wpsielen += 2;
+
+		/*	Value: */
+		wpsie[wpsielen++] = WPS_VERSION_1;	/*	Version 1.0 */
+
+		if (pmlmepriv->wps_probe_req_ie == NULL) {
+			/*	UUID-E */
+			/*	Type: */
+			*(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_ATTR_UUID_E);
+			wpsielen += 2;
+
+			/*	Length: */
+			*(u16 *)(wpsie + wpsielen) = cpu_to_be16(0x0010);
+			wpsielen += 2;
+
+			/*	Value: */
+			if (pwdinfo->external_uuid == 0) {
+				_rtw_memset(wpsie + wpsielen, 0x0, 16);
+				_rtw_memcpy(wpsie + wpsielen, mac, ETH_ALEN);
+			} else
+				_rtw_memcpy(wpsie + wpsielen, pwdinfo->uuid, 0x10);
+			wpsielen += 0x10;
+
+			/*	Config Method */
+			/*	Type: */
+			*(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_ATTR_CONF_METHOD);
+			wpsielen += 2;
+
+			/*	Length: */
+			*(u16 *)(wpsie + wpsielen) = cpu_to_be16(0x0002);
+			wpsielen += 2;
+
+			/*	Value: */
+			*(u16 *)(wpsie + wpsielen) = cpu_to_be16(pwdinfo->supported_wps_cm);
+			wpsielen += 2;
+		}
+
+		/*	Device Name */
+		/*	Type: */
+		*(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_ATTR_DEVICE_NAME);
+		wpsielen += 2;
+
+		/*	Length: */
+		*(u16 *)(wpsie + wpsielen) = cpu_to_be16(pwdinfo->device_name_len);
+		wpsielen += 2;
+
+		/*	Value: */
+		_rtw_memcpy(wpsie + wpsielen, pwdinfo->device_name, pwdinfo->device_name_len);
+		wpsielen += pwdinfo->device_name_len;
+
+		/*	Primary Device Type */
+		/*	Type: */
+		*(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_ATTR_PRIMARY_DEV_TYPE);
+		wpsielen += 2;
+
+		/*	Length: */
+		*(u16 *)(wpsie + wpsielen) = cpu_to_be16(0x0008);
+		wpsielen += 2;
+
+		/*	Value: */
+		/*	Category ID */
+		*(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_PDT_CID_RTK_WIDI);
+		wpsielen += 2;
+
+		/*	OUI */
+		*(u32 *)(wpsie + wpsielen) = cpu_to_be32(WPSOUI);
+		wpsielen += 4;
+
+		/*	Sub Category ID */
+		*(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_PDT_SCID_RTK_DMP);
+		wpsielen += 2;
+
+		/*	Device Password ID */
+		/*	Type: */
+		*(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_ATTR_DEVICE_PWID);
+		wpsielen += 2;
+
+		/*	Length: */
+		*(u16 *)(wpsie + wpsielen) = cpu_to_be16(0x0002);
+		wpsielen += 2;
+
+		/*	Value: */
+		*(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_DPID_REGISTRAR_SPEC);	/*	Registrar-specified */
+		wpsielen += 2;
+
+		pframe = rtw_set_ie(pframe, _VENDOR_SPECIFIC_IE_, wpsielen, (unsigned char *) wpsie, &pattrib->pktlen);
+
+		/*	P2P OUI */
+		p2pielen = 0;
+		p2pie[p2pielen++] = 0x50;
+		p2pie[p2pielen++] = 0x6F;
+		p2pie[p2pielen++] = 0x9A;
+		p2pie[p2pielen++] = 0x09;	/*	WFA P2P v1.0 */
+
+		/*	Commented by Albert 20110221 */
+		/*	According to the P2P Specification, the probe request frame should contain 5 P2P attributes */
+		/*	1. P2P Capability */
+		/*	2. P2P Device ID if this probe request wants to find the specific P2P device */
+		/*	3. Listen Channel */
+		/*	4. Extended Listen Timing */
+		/*	5. Operating Channel if this WiFi is working as the group owner now */
+
+		/*	P2P Capability */
+		/*	Type: */
+		p2pie[p2pielen++] = P2P_ATTR_CAPABILITY;
+
+		/*	Length: */
+		*(u16 *)(p2pie + p2pielen) = cpu_to_le16(0x0002);
+		p2pielen += 2;
+
+		/*	Value: */
+		/*	Device Capability Bitmap, 1 byte */
+		p2pie[p2pielen++] = DMP_P2P_DEVCAP_SUPPORT;
+
+		/*	Group Capability Bitmap, 1 byte */
+		if (pwdinfo->persistent_supported)
+			p2pie[p2pielen++] = P2P_GRPCAP_PERSISTENT_GROUP | DMP_P2P_GRPCAP_SUPPORT;
+		else
+			p2pie[p2pielen++] = DMP_P2P_GRPCAP_SUPPORT;
+
+		/*	Listen Channel */
+		/*	Type: */
+		p2pie[p2pielen++] = P2P_ATTR_LISTEN_CH;
+
+		/*	Length: */
+		*(u16 *)(p2pie + p2pielen) = cpu_to_le16(0x0005);
+		p2pielen += 2;
+
+		/*	Value: */
+		/*	Country String */
+		p2pie[p2pielen++] = 'X';
+		p2pie[p2pielen++] = 'X';
+
+		/*	The third byte should be set to 0x04. */
+		/*	Described in the "Operating Channel Attribute" section. */
+		p2pie[p2pielen++] = 0x04;
+
+		/*	Operating Class */
+		p2pie[p2pielen++] = 0x51;	/*	Copy from SD7 */
+
+		/*	Channel Number */
+		p2pie[p2pielen++] = pwdinfo->listen_channel;	/*	listen channel */
+
+
+		/*	Extended Listen Timing */
+		/*	Type: */
+		p2pie[p2pielen++] = P2P_ATTR_EX_LISTEN_TIMING;
+
+		/*	Length: */
+		*(u16 *)(p2pie + p2pielen) = cpu_to_le16(0x0004);
+		p2pielen += 2;
+
+		/*	Value: */
+		/*	Availability Period */
+		*(u16 *)(p2pie + p2pielen) = cpu_to_le16(0xFFFF);
+		p2pielen += 2;
+
+		/*	Availability Interval */
+		*(u16 *)(p2pie + p2pielen) = cpu_to_le16(0xFFFF);
+		p2pielen += 2;
+
+		if (rtw_p2p_chk_role(pwdinfo, P2P_ROLE_GO)) {
+			/*	Operating Channel (if this WiFi is working as the group owner now) */
+			/*	Type: */
+			p2pie[p2pielen++] = P2P_ATTR_OPERATING_CH;
+
+			/*	Length: */
+			*(u16 *)(p2pie + p2pielen) = cpu_to_le16(0x0005);
+			p2pielen += 2;
+
+			/*	Value: */
+			/*	Country String */
+			p2pie[p2pielen++] = 'X';
+			p2pie[p2pielen++] = 'X';
+
+			/*	The third byte should be set to 0x04. */
+			/*	Described in the "Operating Channel Attribute" section. */
+			p2pie[p2pielen++] = 0x04;
+
+			/*	Operating Class */
+			p2pie[p2pielen++] = 0x51;	/*	Copy from SD7 */
+
+			/*	Channel Number */
+			p2pie[p2pielen++] = pwdinfo->operating_channel;	/*	operating channel number */
+
+		}
+
+		pframe = rtw_set_ie(pframe, _VENDOR_SPECIFIC_IE_, p2pielen, (unsigned char *) p2pie, &pattrib->pktlen);
+
+	}
+
+#ifdef CONFIG_WFD
+	wfdielen = rtw_append_probe_req_wfd_ie(padapter, pframe);
+	pframe += wfdielen;
+	pattrib->pktlen += wfdielen;
+#endif
+
+	pattrib->last_txcmdsz = pattrib->pktlen;
+
+
+	if (wait_ack)
+		ret = dump_mgntframe_and_wait_ack(padapter, pmgntframe);
+	else {
+		dump_mgntframe(padapter, pmgntframe);
+		ret = _SUCCESS;
+	}
+
+exit:
+	return ret;
+}
+
+inline void issue_probereq_p2p(_adapter *adapter, u8 *da)
+{
+	_issue_probereq_p2p(adapter, da, _FALSE);
+}
+
+/*
+ * wait_ms == 0 means that there is no need to wait ack through C2H_CCX_TX_RPT
+ * wait_ms > 0 means you want to wait ack through C2H_CCX_TX_RPT, and the value of wait_ms means the interval between each TX
+ * try_cnt means the maximal TX count to try
+ */
+int issue_probereq_p2p_ex(_adapter *adapter, u8 *da, int try_cnt, int wait_ms)
+{
+	int ret;
+	int i = 0;
+	systime start = rtw_get_current_time();
+
+	do {
+		ret = _issue_probereq_p2p(adapter, da, wait_ms > 0 ? _TRUE : _FALSE);
+
+		i++;
+
+		if (RTW_CANNOT_RUN(adapter))
+			break;
+
+		if (i < try_cnt && wait_ms > 0 && ret == _FAIL)
+			rtw_msleep_os(wait_ms);
+
+	} while ((i < try_cnt) && ((ret == _FAIL) || (wait_ms == 0)));
+
+	if (ret != _FAIL) {
+		ret = _SUCCESS;
+#ifndef DBG_XMIT_ACK
+		goto exit;
+#endif
+	}
+
+	if (try_cnt && wait_ms) {
+		if (da)
+			RTW_INFO(FUNC_ADPT_FMT" to "MAC_FMT", ch:%u%s, %d/%d in %u ms\n",
+				FUNC_ADPT_ARG(adapter), MAC_ARG(da), rtw_get_oper_ch(adapter),
+				ret == _SUCCESS ? ", acked" : "", i, try_cnt, rtw_get_passing_time_ms(start));
+		else
+			RTW_INFO(FUNC_ADPT_FMT", ch:%u%s, %d/%d in %u ms\n",
+				FUNC_ADPT_ARG(adapter), rtw_get_oper_ch(adapter),
+				ret == _SUCCESS ? ", acked" : "", i, try_cnt, rtw_get_passing_time_ms(start));
+	}
+exit:
+	return ret;
+}
+
+#endif /* CONFIG_P2P */
+
+s32 rtw_action_public_decache(union recv_frame *rframe, u8 token_offset)
+{
+	_adapter *adapter = rframe->u.hdr.adapter;
+	struct mlme_ext_priv *mlmeext = &(adapter->mlmeextpriv);
+	u8 *frame = rframe->u.hdr.rx_data;
+	u16 seq_ctrl = ((rframe->u.hdr.attrib.seq_num & 0xffff) << 4) | (rframe->u.hdr.attrib.frag_num & 0xf);
+	u8 token = *(rframe->u.hdr.rx_data + sizeof(struct rtw_ieee80211_hdr_3addr) + token_offset);
+
+	if (GetRetry(frame)) {
+		if ((seq_ctrl == mlmeext->action_public_rxseq)
+		    && (token == mlmeext->action_public_dialog_token)
+		   ) {
+			RTW_INFO(FUNC_ADPT_FMT" seq_ctrl=0x%x, rxseq=0x%x, token:%d\n",
+				FUNC_ADPT_ARG(adapter), seq_ctrl, mlmeext->action_public_rxseq, token);
+			return _FAIL;
+		}
+	}
+
+	/* TODO: per sta seq & token */
+	mlmeext->action_public_rxseq = seq_ctrl;
+	mlmeext->action_public_dialog_token = token;
+
+	return _SUCCESS;
+}
+
+unsigned int on_action_public_p2p(union recv_frame *precv_frame)
+{
+	_adapter *padapter = precv_frame->u.hdr.adapter;
+	u8 *pframe = precv_frame->u.hdr.rx_data;
+	uint len = precv_frame->u.hdr.len;
+	u8 *frame_body;
+#ifdef CONFIG_P2P
+	u8 *p2p_ie;
+	u32	p2p_ielen;
+	struct	wifidirect_info	*pwdinfo = &(padapter->wdinfo);
+	u8	result = P2P_STATUS_SUCCESS;
+	u8	empty_addr[ETH_ALEN] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 };
+	u8 *merged_p2pie = NULL;
+	u32 merged_p2p_ielen = 0;
+#endif /* CONFIG_P2P */
+
+	frame_body = (unsigned char *)(pframe + sizeof(struct rtw_ieee80211_hdr_3addr));
+
+#ifdef CONFIG_P2P
+	_cancel_timer_ex(&pwdinfo->reset_ch_sitesurvey);
+#ifdef CONFIG_IOCTL_CFG80211
+	if (adapter_wdev_data(padapter)->p2p_enabled && pwdinfo->driver_interface == DRIVER_CFG80211)
+		rtw_cfg80211_rx_p2p_action_public(padapter, precv_frame);
+	else
+#endif /* CONFIG_IOCTL_CFG80211 */
+	{
+		/*	Do nothing if the driver doesn't enable the P2P function. */
+		if (rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE) || rtw_p2p_chk_state(pwdinfo, P2P_STATE_IDLE))
+			return _SUCCESS;
+
+		len -= sizeof(struct rtw_ieee80211_hdr_3addr);
+
+		switch (frame_body[6]) { /* OUI Subtype */
+		case P2P_GO_NEGO_REQ: {
+			RTW_INFO("[%s] Got GO Nego Req Frame\n", __FUNCTION__);
+			_rtw_memset(&pwdinfo->groupid_info, 0x00, sizeof(struct group_id_info));
+
+			if (rtw_p2p_chk_state(pwdinfo, P2P_STATE_RX_PROVISION_DIS_REQ))
+				rtw_p2p_set_state(pwdinfo, rtw_p2p_pre_state(pwdinfo));
+
+			if (rtw_p2p_chk_state(pwdinfo, P2P_STATE_GONEGO_FAIL)) {
+				/*	Commented by Albert 20110526 */
+				/*	In this case, this means the previous nego fail doesn't be reset yet. */
+				_cancel_timer_ex(&pwdinfo->restore_p2p_state_timer);
+				/*	Restore the previous p2p state */
+				rtw_p2p_set_state(pwdinfo, rtw_p2p_pre_state(pwdinfo));
+				RTW_INFO("[%s] Restore the previous p2p state to %d\n", __FUNCTION__, rtw_p2p_state(pwdinfo));
+			}
+#ifdef CONFIG_CONCURRENT_MODE
+			if (rtw_mi_buddy_check_fwstate(padapter, _FW_LINKED))
+				_cancel_timer_ex(&pwdinfo->ap_p2p_switch_timer);
+#endif /* CONFIG_CONCURRENT_MODE */
+
+			/*	Commented by Kurt 20110902 */
+			/* Add if statement to avoid receiving duplicate prov disc req. such that pre_p2p_state would be covered. */
+			if (!rtw_p2p_chk_state(pwdinfo, P2P_STATE_GONEGO_ING))
+				rtw_p2p_set_pre_state(pwdinfo, rtw_p2p_state(pwdinfo));
+
+			/*	Commented by Kurt 20120113 */
+			/*	Get peer_dev_addr here if peer doesn't issue prov_disc frame. */
+			if (_rtw_memcmp(pwdinfo->rx_prov_disc_info.peerDevAddr, empty_addr, ETH_ALEN))
+				_rtw_memcpy(pwdinfo->rx_prov_disc_info.peerDevAddr, get_addr2_ptr(pframe), ETH_ALEN);
+
+			result = process_p2p_group_negotation_req(pwdinfo, frame_body, len);
+			issue_p2p_GO_response(padapter, get_addr2_ptr(pframe), frame_body, len, result);
+#ifdef CONFIG_INTEL_WIDI
+			if (padapter->mlmepriv.widi_state == INTEL_WIDI_STATE_LISTEN) {
+				padapter->mlmepriv.widi_state = INTEL_WIDI_STATE_WFD_CONNECTION;
+				_cancel_timer_ex(&(padapter->mlmepriv.listen_timer));
+				intel_widi_wk_cmd(padapter, INTEL_WIDI_LISTEN_STOP_WK, NULL, 0);
+			}
+#endif /* CONFIG_INTEL_WIDI */
+
+			/*	Commented by Albert 20110718 */
+			/*	No matter negotiating or negotiation failure, the driver should set up the restore P2P state timer. */
+#ifdef CONFIG_CONCURRENT_MODE
+			/*	Commented by Albert 20120107 */
+			_set_timer(&pwdinfo->restore_p2p_state_timer, 3000);
+#else /* CONFIG_CONCURRENT_MODE */
+			_set_timer(&pwdinfo->restore_p2p_state_timer, 5000);
+#endif /* CONFIG_CONCURRENT_MODE */
+			break;
+		}
+		case P2P_GO_NEGO_RESP: {
+			RTW_INFO("[%s] Got GO Nego Resp Frame\n", __FUNCTION__);
+
+			if (rtw_p2p_chk_state(pwdinfo, P2P_STATE_GONEGO_ING)) {
+				/*	Commented by Albert 20110425 */
+				/*	The restore timer is enabled when issuing the nego request frame of rtw_p2p_connect function. */
+				_cancel_timer_ex(&pwdinfo->restore_p2p_state_timer);
+				pwdinfo->nego_req_info.benable = _FALSE;
+				result = process_p2p_group_negotation_resp(pwdinfo, frame_body, len);
+				issue_p2p_GO_confirm(pwdinfo->padapter, get_addr2_ptr(pframe), result);
+				if (P2P_STATUS_SUCCESS == result) {
+					if (rtw_p2p_role(pwdinfo) == P2P_ROLE_CLIENT) {
+						pwdinfo->p2p_info.operation_ch[0] = pwdinfo->peer_operating_ch;
+#ifdef CONFIG_P2P_OP_CHK_SOCIAL_CH
+						pwdinfo->p2p_info.operation_ch[1] = 1;	/* Check whether GO is operating in channel 1; */
+						pwdinfo->p2p_info.operation_ch[2] = 6;	/* Check whether GO is operating in channel 6; */
+						pwdinfo->p2p_info.operation_ch[3] = 11;	/* Check whether GO is operating in channel 11; */
+#endif /* CONFIG_P2P_OP_CHK_SOCIAL_CH */
+						pwdinfo->p2p_info.scan_op_ch_only = 1;
+						_set_timer(&pwdinfo->reset_ch_sitesurvey2, P2P_RESET_SCAN_CH);
+					}
+				}
+
+				/*	Reset the dialog token for group negotiation frames. */
+				pwdinfo->negotiation_dialog_token = 1;
+
+				if (rtw_p2p_chk_state(pwdinfo, P2P_STATE_GONEGO_FAIL))
+					_set_timer(&pwdinfo->restore_p2p_state_timer, 5000);
+			} else
+				RTW_INFO("[%s] Skipped GO Nego Resp Frame (p2p_state != P2P_STATE_GONEGO_ING)\n", __FUNCTION__);
+
+			break;
+		}
+		case P2P_GO_NEGO_CONF: {
+			RTW_INFO("[%s] Got GO Nego Confirm Frame\n", __FUNCTION__);
+			result = process_p2p_group_negotation_confirm(pwdinfo, frame_body, len);
+			if (P2P_STATUS_SUCCESS == result) {
+				if (rtw_p2p_role(pwdinfo) == P2P_ROLE_CLIENT) {
+					pwdinfo->p2p_info.operation_ch[0] = pwdinfo->peer_operating_ch;
+#ifdef CONFIG_P2P_OP_CHK_SOCIAL_CH
+					pwdinfo->p2p_info.operation_ch[1] = 1;	/* Check whether GO is operating in channel 1; */
+					pwdinfo->p2p_info.operation_ch[2] = 6;	/* Check whether GO is operating in channel 6; */
+					pwdinfo->p2p_info.operation_ch[3] = 11;	/* Check whether GO is operating in channel 11; */
+#endif /* CONFIG_P2P_OP_CHK_SOCIAL_CH */
+					pwdinfo->p2p_info.scan_op_ch_only = 1;
+					_set_timer(&pwdinfo->reset_ch_sitesurvey2, P2P_RESET_SCAN_CH);
+				}
+			}
+			break;
+		}
+		case P2P_INVIT_REQ: {
+			/*	Added by Albert 2010/10/05 */
+			/*	Received the P2P Invite Request frame. */
+
+			RTW_INFO("[%s] Got invite request frame!\n", __FUNCTION__);
+			p2p_ie = rtw_get_p2p_ie(frame_body + _PUBLIC_ACTION_IE_OFFSET_, len - _PUBLIC_ACTION_IE_OFFSET_, NULL, &p2p_ielen);
+			if (p2p_ie) {
+				/*	Parse the necessary information from the P2P Invitation Request frame. */
+				/*	For example: The MAC address of sending this P2P Invitation Request frame. */
+				u32	attr_contentlen = 0;
+				u8	status_code = P2P_STATUS_FAIL_INFO_UNAVAILABLE;
+				struct group_id_info group_id;
+				u8	invitation_flag = 0;
+
+				merged_p2p_ielen = rtw_get_p2p_merged_ies_len(frame_body + _PUBLIC_ACTION_IE_OFFSET_, len - _PUBLIC_ACTION_IE_OFFSET_);
+
+				merged_p2pie = rtw_zmalloc(merged_p2p_ielen + 2);	/* 2 is for EID and Length */
+				if (merged_p2pie == NULL) {
+					RTW_INFO("[%s] Malloc p2p ie fail\n", __FUNCTION__);
+					goto exit;
+				}
+				_rtw_memset(merged_p2pie, 0x00, merged_p2p_ielen);
+
+				merged_p2p_ielen = rtw_p2p_merge_ies(frame_body + _PUBLIC_ACTION_IE_OFFSET_, len - _PUBLIC_ACTION_IE_OFFSET_, merged_p2pie);
+
+				rtw_get_p2p_attr_content(merged_p2pie, merged_p2p_ielen, P2P_ATTR_INVITATION_FLAGS, &invitation_flag, &attr_contentlen);
+				if (attr_contentlen) {
+
+					rtw_get_p2p_attr_content(merged_p2pie, merged_p2p_ielen, P2P_ATTR_GROUP_BSSID, pwdinfo->p2p_peer_interface_addr, &attr_contentlen);
+					/*	Commented by Albert 20120510 */
+					/*	Copy to the pwdinfo->p2p_peer_interface_addr. */
+					/*	So that the WFD UI ( or Sigma ) can get the peer interface address by using the following command. */
+					/*	#> iwpriv wlan0 p2p_get peer_ifa */
+					/*	After having the peer interface address, the sigma can find the correct conf file for wpa_supplicant. */
+
+					if (attr_contentlen) {
+						RTW_INFO("[%s] GO's BSSID = %.2X %.2X %.2X %.2X %.2X %.2X\n", __FUNCTION__,
+							pwdinfo->p2p_peer_interface_addr[0], pwdinfo->p2p_peer_interface_addr[1],
+							pwdinfo->p2p_peer_interface_addr[2], pwdinfo->p2p_peer_interface_addr[3],
+							pwdinfo->p2p_peer_interface_addr[4], pwdinfo->p2p_peer_interface_addr[5]);
+					}
+
+					if (invitation_flag & P2P_INVITATION_FLAGS_PERSISTENT) {
+						/*	Re-invoke the persistent group. */
+
+						_rtw_memset(&group_id, 0x00, sizeof(struct group_id_info));
+						rtw_get_p2p_attr_content(merged_p2pie, merged_p2p_ielen, P2P_ATTR_GROUP_ID, (u8 *) &group_id, &attr_contentlen);
+						if (attr_contentlen) {
+							if (_rtw_memcmp(group_id.go_device_addr, adapter_mac_addr(padapter), ETH_ALEN)) {
+								/*	The p2p device sending this p2p invitation request wants this Wi-Fi device to be the persistent GO. */
+								rtw_p2p_set_state(pwdinfo, P2P_STATE_RECV_INVITE_REQ_GO);
+								rtw_p2p_set_role(pwdinfo, P2P_ROLE_GO);
+								status_code = P2P_STATUS_SUCCESS;
+							} else {
+								/*	The p2p device sending this p2p invitation request wants to be the persistent GO. */
+								if (is_matched_in_profilelist(pwdinfo->p2p_peer_interface_addr, &pwdinfo->profileinfo[0])) {
+									u8 operatingch_info[5] = { 0x00 };
+									if (rtw_get_p2p_attr_content(merged_p2pie, merged_p2p_ielen, P2P_ATTR_OPERATING_CH, operatingch_info,
+										&attr_contentlen)) {
+										if (rtw_chset_search_ch(adapter_to_chset(padapter), (u32)operatingch_info[4]) >= 0) {
+											/*	The operating channel is acceptable for this device. */
+											pwdinfo->rx_invitereq_info.operation_ch[0] = operatingch_info[4];
+#ifdef CONFIG_P2P_OP_CHK_SOCIAL_CH
+											pwdinfo->rx_invitereq_info.operation_ch[1] = 1;		/* Check whether GO is operating in channel 1; */
+											pwdinfo->rx_invitereq_info.operation_ch[2] = 6;		/* Check whether GO is operating in channel 6; */
+											pwdinfo->rx_invitereq_info.operation_ch[3] = 11;		/* Check whether GO is operating in channel 11; */
+#endif /* CONFIG_P2P_OP_CHK_SOCIAL_CH */
+											pwdinfo->rx_invitereq_info.scan_op_ch_only = 1;
+											_set_timer(&pwdinfo->reset_ch_sitesurvey, P2P_RESET_SCAN_CH);
+											rtw_p2p_set_state(pwdinfo, P2P_STATE_RECV_INVITE_REQ_MATCH);
+											rtw_p2p_set_role(pwdinfo, P2P_ROLE_CLIENT);
+											status_code = P2P_STATUS_SUCCESS;
+										} else {
+											/*	The operating channel isn't supported by this device. */
+											rtw_p2p_set_state(pwdinfo, P2P_STATE_RECV_INVITE_REQ_DISMATCH);
+											rtw_p2p_set_role(pwdinfo, P2P_ROLE_DEVICE);
+											status_code = P2P_STATUS_FAIL_NO_COMMON_CH;
+											_set_timer(&pwdinfo->restore_p2p_state_timer, 3000);
+										}
+									} else {
+										/*	Commented by Albert 20121130 */
+										/*	Intel will use the different P2P IE to store the operating channel information */
+										/*	Workaround for Intel WiDi 3.5 */
+										rtw_p2p_set_state(pwdinfo, P2P_STATE_RECV_INVITE_REQ_MATCH);
+										rtw_p2p_set_role(pwdinfo, P2P_ROLE_CLIENT);
+										status_code = P2P_STATUS_SUCCESS;
+									}
+								} else {
+									rtw_p2p_set_state(pwdinfo, P2P_STATE_RECV_INVITE_REQ_DISMATCH);
+#ifdef CONFIG_INTEL_WIDI
+									_rtw_memcpy(pwdinfo->p2p_peer_device_addr, group_id.go_device_addr , ETH_ALEN);
+									rtw_p2p_set_role(pwdinfo, P2P_ROLE_CLIENT);
+#endif /* CONFIG_INTEL_WIDI */
+
+									status_code = P2P_STATUS_FAIL_UNKNOWN_P2PGROUP;
+								}
+							}
+						} else {
+							RTW_INFO("[%s] P2P Group ID Attribute NOT FOUND!\n", __FUNCTION__);
+							status_code = P2P_STATUS_FAIL_INFO_UNAVAILABLE;
+						}
+					} else {
+						/*	Received the invitation to join a P2P group. */
+
+						_rtw_memset(&group_id, 0x00, sizeof(struct group_id_info));
+						rtw_get_p2p_attr_content(merged_p2pie, merged_p2p_ielen, P2P_ATTR_GROUP_ID, (u8 *) &group_id, &attr_contentlen);
+						if (attr_contentlen) {
+							if (_rtw_memcmp(group_id.go_device_addr, adapter_mac_addr(padapter), ETH_ALEN)) {
+								/*	In this case, the GO can't be myself. */
+								rtw_p2p_set_state(pwdinfo, P2P_STATE_RECV_INVITE_REQ_DISMATCH);
+								status_code = P2P_STATUS_FAIL_INFO_UNAVAILABLE;
+							} else {
+								/*	The p2p device sending this p2p invitation request wants to join an existing P2P group */
+								/*	Commented by Albert 2012/06/28 */
+								/*	In this case, this Wi-Fi device should use the iwpriv command to get the peer device address. */
+								/*	The peer device address should be the destination address for the provisioning discovery request. */
+								/*	Then, this Wi-Fi device should use the iwpriv command to get the peer interface address. */
+								/*	The peer interface address should be the address for WPS mac address */
+								_rtw_memcpy(pwdinfo->p2p_peer_device_addr, group_id.go_device_addr , ETH_ALEN);
+								rtw_p2p_set_role(pwdinfo, P2P_ROLE_CLIENT);
+								rtw_p2p_set_state(pwdinfo, P2P_STATE_RECV_INVITE_REQ_JOIN);
+								status_code = P2P_STATUS_SUCCESS;
+							}
+						} else {
+							RTW_INFO("[%s] P2P Group ID Attribute NOT FOUND!\n", __FUNCTION__);
+							status_code = P2P_STATUS_FAIL_INFO_UNAVAILABLE;
+						}
+					}
+				} else {
+					RTW_INFO("[%s] P2P Invitation Flags Attribute NOT FOUND!\n", __FUNCTION__);
+					status_code = P2P_STATUS_FAIL_INFO_UNAVAILABLE;
+				}
+
+				RTW_INFO("[%s] status_code = %d\n", __FUNCTION__, status_code);
+
+				pwdinfo->inviteresp_info.token = frame_body[7];
+				issue_p2p_invitation_response(padapter, get_addr2_ptr(pframe), pwdinfo->inviteresp_info.token, status_code);
+				_set_timer(&pwdinfo->restore_p2p_state_timer, 3000);
+			}
+#ifdef CONFIG_INTEL_WIDI
+			if (padapter->mlmepriv.widi_state == INTEL_WIDI_STATE_LISTEN) {
+				padapter->mlmepriv.widi_state = INTEL_WIDI_STATE_WFD_CONNECTION;
+				_cancel_timer_ex(&(padapter->mlmepriv.listen_timer));
+				intel_widi_wk_cmd(padapter, INTEL_WIDI_LISTEN_STOP_WK, NULL, 0);
+			}
+#endif /* CONFIG_INTEL_WIDI */
+			break;
+		}
+		case P2P_INVIT_RESP: {
+			u8	attr_content = 0x00;
+			u32	attr_contentlen = 0;
+
+			RTW_INFO("[%s] Got invite response frame!\n", __FUNCTION__);
+			_cancel_timer_ex(&pwdinfo->restore_p2p_state_timer);
+			p2p_ie = rtw_get_p2p_ie(frame_body + _PUBLIC_ACTION_IE_OFFSET_, len - _PUBLIC_ACTION_IE_OFFSET_, NULL, &p2p_ielen);
+			if (p2p_ie) {
+				rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_STATUS, &attr_content, &attr_contentlen);
+
+				if (attr_contentlen == 1) {
+					RTW_INFO("[%s] Status = %d\n", __FUNCTION__, attr_content);
+					pwdinfo->invitereq_info.benable = _FALSE;
+
+					if (attr_content == P2P_STATUS_SUCCESS) {
+						if (_rtw_memcmp(pwdinfo->invitereq_info.go_bssid, adapter_mac_addr(padapter), ETH_ALEN))
+							rtw_p2p_set_role(pwdinfo, P2P_ROLE_GO);
+						else
+							rtw_p2p_set_role(pwdinfo, P2P_ROLE_CLIENT);
+
+						rtw_p2p_set_state(pwdinfo, P2P_STATE_RX_INVITE_RESP_OK);
+					} else {
+						rtw_p2p_set_role(pwdinfo, P2P_ROLE_DEVICE);
+						rtw_p2p_set_state(pwdinfo, P2P_STATE_RX_INVITE_RESP_FAIL);
+					}
+				} else {
+					rtw_p2p_set_role(pwdinfo, P2P_ROLE_DEVICE);
+					rtw_p2p_set_state(pwdinfo, P2P_STATE_RX_INVITE_RESP_FAIL);
+				}
+			} else {
+				rtw_p2p_set_role(pwdinfo, P2P_ROLE_DEVICE);
+				rtw_p2p_set_state(pwdinfo, P2P_STATE_RX_INVITE_RESP_FAIL);
+			}
+
+			if (rtw_p2p_chk_state(pwdinfo, P2P_STATE_RX_INVITE_RESP_FAIL))
+				_set_timer(&pwdinfo->restore_p2p_state_timer, 5000);
+			break;
+		}
+		case P2P_DEVDISC_REQ:
+
+			process_p2p_devdisc_req(pwdinfo, pframe, len);
+
+			break;
+
+		case P2P_DEVDISC_RESP:
+
+			process_p2p_devdisc_resp(pwdinfo, pframe, len);
+
+			break;
+
+		case P2P_PROVISION_DISC_REQ:
+			RTW_INFO("[%s] Got Provisioning Discovery Request Frame\n", __FUNCTION__);
+			process_p2p_provdisc_req(pwdinfo, pframe, len);
+			_rtw_memcpy(pwdinfo->rx_prov_disc_info.peerDevAddr, get_addr2_ptr(pframe), ETH_ALEN);
+
+			/* 20110902 Kurt */
+			/* Add the following statement to avoid receiving duplicate prov disc req. such that pre_p2p_state would be covered. */
+			if (!rtw_p2p_chk_state(pwdinfo, P2P_STATE_RX_PROVISION_DIS_REQ))
+				rtw_p2p_set_pre_state(pwdinfo, rtw_p2p_state(pwdinfo));
+
+			rtw_p2p_set_state(pwdinfo, P2P_STATE_RX_PROVISION_DIS_REQ);
+			_set_timer(&pwdinfo->restore_p2p_state_timer, P2P_PROVISION_TIMEOUT);
+#ifdef CONFIG_INTEL_WIDI
+			if (padapter->mlmepriv.widi_state == INTEL_WIDI_STATE_LISTEN) {
+				padapter->mlmepriv.widi_state = INTEL_WIDI_STATE_WFD_CONNECTION;
+				_cancel_timer_ex(&(padapter->mlmepriv.listen_timer));
+				intel_widi_wk_cmd(padapter, INTEL_WIDI_LISTEN_STOP_WK, NULL, 0);
+			}
+#endif /* CONFIG_INTEL_WIDI */
+			break;
+
+		case P2P_PROVISION_DISC_RESP:
+			/*	Commented by Albert 20110707 */
+			/*	Should we check the pwdinfo->tx_prov_disc_info.bsent flag here?? */
+			RTW_INFO("[%s] Got Provisioning Discovery Response Frame\n", __FUNCTION__);
+			/*	Commented by Albert 20110426 */
+			/*	The restore timer is enabled when issuing the provisioing request frame in rtw_p2p_prov_disc function. */
+			_cancel_timer_ex(&pwdinfo->restore_p2p_state_timer);
+			rtw_p2p_set_state(pwdinfo, P2P_STATE_RX_PROVISION_DIS_RSP);
+			process_p2p_provdisc_resp(pwdinfo, pframe);
+			_set_timer(&pwdinfo->restore_p2p_state_timer, P2P_PROVISION_TIMEOUT);
+			break;
+
+		}
+	}
+
+
+exit:
+
+	if (merged_p2pie)
+		rtw_mfree(merged_p2pie, merged_p2p_ielen + 2);
+#endif /* CONFIG_P2P */
+	return _SUCCESS;
+}
+
+unsigned int on_action_public_vendor(union recv_frame *precv_frame)
+{
+	unsigned int ret = _FAIL;
+	u8 *pframe = precv_frame->u.hdr.rx_data;
+	u8 *frame_body = pframe + sizeof(struct rtw_ieee80211_hdr_3addr);
+
+	if (_rtw_memcmp(frame_body + 2, P2P_OUI, 4) == _TRUE) {
+		if (rtw_action_public_decache(precv_frame, 7) == _FAIL)
+			goto exit;
+
+		if (!hal_chk_wl_func(precv_frame->u.hdr.adapter, WL_FUNC_MIRACAST))
+			rtw_rframe_del_wfd_ie(precv_frame, 8);
+
+		ret = on_action_public_p2p(precv_frame);
+	}
+
+exit:
+	return ret;
+}
+
+unsigned int on_action_public_default(union recv_frame *precv_frame, u8 action)
+{
+	unsigned int ret = _FAIL;
+	u8 *pframe = precv_frame->u.hdr.rx_data;
+	u8 *frame_body = pframe + sizeof(struct rtw_ieee80211_hdr_3addr);
+	u8 token;
+	_adapter *adapter = precv_frame->u.hdr.adapter;
+	int cnt = 0;
+	char msg[64];
+
+	token = frame_body[2];
+
+	if (rtw_action_public_decache(precv_frame, 2) == _FAIL)
+		goto exit;
+
+#ifdef CONFIG_IOCTL_CFG80211
+	cnt += sprintf((msg + cnt), "%s(token:%u)", action_public_str(action), token);
+	rtw_cfg80211_rx_action(adapter, precv_frame, msg);
+#endif
+
+	ret = _SUCCESS;
+
+exit:
+	return ret;
+}
+
+unsigned int on_action_public(_adapter *padapter, union recv_frame *precv_frame)
+{
+	unsigned int ret = _FAIL;
+	u8 *pframe = precv_frame->u.hdr.rx_data;
+	uint frame_len = precv_frame->u.hdr.len;
+	u8 *frame_body = pframe + sizeof(struct rtw_ieee80211_hdr_3addr);
+	u8 category, action;
+
+	/* check RA matches or not */
+	if (!_rtw_memcmp(adapter_mac_addr(padapter), GetAddr1Ptr(pframe), ETH_ALEN))
+		goto exit;
+
+	category = frame_body[0];
+	if (category != RTW_WLAN_CATEGORY_PUBLIC)
+		goto exit;
+
+	action = frame_body[1];
+	switch (action) {
+	case ACT_PUBLIC_BSSCOEXIST:
+#ifdef CONFIG_80211N_HT
+#ifdef CONFIG_AP_MODE
+		/*20/40 BSS Coexistence Management frame is a Public Action frame*/
+		if (check_fwstate(&padapter->mlmepriv, WIFI_AP_STATE) == _TRUE)
+			rtw_process_public_act_bsscoex(padapter, pframe, frame_len);
+#endif /*CONFIG_AP_MODE*/
+#endif /*CONFIG_80211N_HT*/
+		break;
+	case ACT_PUBLIC_VENDOR:
+		ret = on_action_public_vendor(precv_frame);
+		break;
+	default:
+		ret = on_action_public_default(precv_frame, action);
+		break;
+	}
+
+exit:
+	return ret;
+}
+
+#if defined(CONFIG_RTW_WNM) || defined(CONFIG_RTW_80211K)
+static u8 rtw_wnm_nb_elem_parsing(
+	u8* pdata, u32 data_len, u8 from_btm, 
+	u32 *nb_rpt_num, u8 *nb_rpt_is_same,
+	struct roam_nb_info *pnb, struct wnm_btm_cant *pcandidates)
+{
+	u8 bfound = _FALSE, ret = _SUCCESS;
+	u8 *ptr, *pend, *op;
+	u32 elem_len, subelem_len, op_len;
+	u32 i, nb_rpt_entries = 0;
+	struct nb_rpt_hdr *pie;
+	struct wnm_btm_cant *pcandidate;
+
+	if ((!pdata) || (!pnb))
+		return _FAIL;
+
+	if ((from_btm) && (!pcandidates))
+		return _FAIL;
+
+	ptr = pdata;
+	pend = ptr + data_len;
+	elem_len = data_len;
+	subelem_len = (u32)*(pdata+1);
+
+	for (i=0; i < RTW_MAX_NB_RPT_NUM; i++) {
+		if (((ptr + 7) > pend) || (elem_len < subelem_len)) 
+			break;
+
+		if (*ptr != 0x34) {
+			RTW_ERR("WNM: invalid data(0x%2x)!\n", *ptr);
+			ret = _FAIL;
+			break;
+		}
+
+		pie = (struct nb_rpt_hdr *)ptr;		
+		if (from_btm) {
+			op = rtw_get_ie((u8 *)(ptr+15), 
+				WNM_BTM_CAND_PREF_SUBEID, 
+				&op_len, (subelem_len - 15));
+		}
+
+		ptr = (u8 *)(ptr + subelem_len + 2);
+		elem_len -= (subelem_len +2);
+		subelem_len = *(ptr+1);
+		if (from_btm) {
+			pcandidate = (pcandidates + i);
+			_rtw_memcpy(&pcandidate->nb_rpt, pie, sizeof(struct nb_rpt_hdr));
+			if (op && (op_len !=0)) {
+				pcandidate->preference = *(op + 2);
+				bfound = _TRUE;
+			} else
+				pcandidate->preference = 0;
+
+			RTW_DBG("WNM: preference check bssid("MAC_FMT
+				") ,bss_info(0x%04X), reg_class(0x%02X), ch(%d),"
+				" phy_type(0x%02X), preference(0x%02X)\n",
+				MAC_ARG(pcandidate->nb_rpt.bssid), pcandidate->nb_rpt.bss_info, 
+				pcandidate->nb_rpt.reg_class, pcandidate->nb_rpt.ch_num, 
+				pcandidate->nb_rpt.phy_type, pcandidate->preference);
+		} else {
+			if (_rtw_memcmp(&pnb->nb_rpt[i], pie, sizeof(struct nb_rpt_hdr)) == _FALSE)
+				*nb_rpt_is_same = _FALSE;
+			_rtw_memcpy(&pnb->nb_rpt[i], pie, sizeof(struct nb_rpt_hdr));
+		}
+		nb_rpt_entries++;			
+	} 
+
+	if (from_btm) 
+		pnb->preference_en = (bfound)?_TRUE:_FALSE; 
+
+	*nb_rpt_num = nb_rpt_entries;
+	return ret;
+}	
+
+/* selection sorting based on preference value
+ * IN : 		nb_rpt_entries - candidate num
+ * IN/OUT :	pcandidates	- candidate list
+ * return : TRUE - means pcandidates is updated.  
+ */
+static u8 rtw_wnm_candidates_sorting(
+	u32 nb_rpt_entries, struct wnm_btm_cant *pcandidates)
+{
+	u8 updated = _FALSE;
+	u32 i, j, pos;
+	struct wnm_btm_cant swap;
+	struct wnm_btm_cant *pcant_1, *pcant_2;
+
+	if ((!nb_rpt_entries) || (!pcandidates))
+		return updated;
+
+	for (i=0; i < (nb_rpt_entries - 1); i++) {
+		pos = i;
+		for (j=(i + 1); j < nb_rpt_entries; j++) {
+			pcant_1 = pcandidates+pos;
+			pcant_2 = pcandidates+j;
+			if ((pcant_1->preference) < (pcant_2->preference))
+				pos = j;
+		}
+
+		if (pos != i) {
+			updated = _TRUE;
+			_rtw_memcpy(&swap, (pcandidates+i), sizeof(struct wnm_btm_cant));
+			_rtw_memcpy((pcandidates+i), (pcandidates+pos), sizeof(struct wnm_btm_cant));
+			_rtw_memcpy((pcandidates+pos), &swap, sizeof(struct wnm_btm_cant));
+		}
+	}	
+	return updated;
+}	
+
+static void rtw_wnm_nb_info_update(
+	u32 nb_rpt_entries, u8 from_btm, 
+	struct roam_nb_info *pnb, struct wnm_btm_cant *pcandidates, 
+	u8 *nb_rpt_is_same)
+{
+	u8 is_found;
+	u32 i, j;
+	struct wnm_btm_cant *pcand;
+
+	if (!pnb)
+		return;
+
+	pnb->nb_rpt_ch_list_num = 0;
+	for (i=0; i<nb_rpt_entries; i++) {
+		is_found = _FALSE;
+		if (from_btm) {
+			pcand = (pcandidates+i);
+			if (_rtw_memcmp(&pnb->nb_rpt[i], &pcand->nb_rpt,
+					sizeof(struct nb_rpt_hdr)) == _FALSE)
+				*nb_rpt_is_same = _FALSE;
+			_rtw_memcpy(&pnb->nb_rpt[i], &pcand->nb_rpt, sizeof(struct nb_rpt_hdr));
+		}
+
+		RTW_DBG("WNM: bssid(" MAC_FMT 
+			") , bss_info(0x%04X), reg_class(0x%02X), ch_num(%d), phy_type(0x%02X)\n",
+			MAC_ARG(pnb->nb_rpt[i].bssid), pnb->nb_rpt[i].bss_info, 
+			pnb->nb_rpt[i].reg_class, pnb->nb_rpt[i].ch_num, 
+			pnb->nb_rpt[i].phy_type);
+
+		if (pnb->nb_rpt[i].ch_num == 0)
+			continue;
+
+		for (j=0; j<nb_rpt_entries; j++) {
+			if (pnb->nb_rpt[i].ch_num == pnb->nb_rpt_ch_list[j].hw_value) {
+				is_found = _TRUE;
+				break;
+			}
+		}
+							
+		if (!is_found) {
+			pnb->nb_rpt_ch_list[pnb->nb_rpt_ch_list_num].hw_value = pnb->nb_rpt[i].ch_num;
+				pnb->nb_rpt_ch_list_num++;
+		}
+	}
+}
+
+static void rtw_wnm_btm_candidate_select(_adapter *padapter)
+{
+	struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
+	struct roam_nb_info *pnb = &(padapter->mlmepriv.nb_info);
+	struct wlan_network *pnetwork;
+	u8 bfound = _FALSE;
+	u32 i;
+
+	for (i = 0; i < pnb->last_nb_rpt_entries; i++) {
+		pnetwork = rtw_find_network(
+				&(pmlmepriv->scanned_queue), 
+				pnb->nb_rpt[i].bssid);
+
+		if (pnetwork) {
+			bfound = _TRUE;
+			break;
+		}
+	}
+
+	if (bfound) {
+		_rtw_memcpy(pnb->roam_target_addr, pnb->nb_rpt[i].bssid, ETH_ALEN);
+		RTW_INFO("WNM : select btm entry(%d) - %s("MAC_FMT", ch%u) rssi:%d\n"
+			, i
+			, pnetwork->network.Ssid.Ssid
+			, MAC_ARG(pnetwork->network.MacAddress)
+			, pnetwork->network.Configuration.DSConfig
+			, (int)pnetwork->network.Rssi);
+	} else 
+		_rtw_memset(pnb->roam_target_addr,0, ETH_ALEN);
+}
+
+u32 rtw_wnm_btm_candidates_survey(
+	_adapter *padapter, u8* pframe, u32 elem_len, u8 from_btm)
+{
+	struct roam_nb_info *pnb = &(padapter->mlmepriv.nb_info);
+	struct wnm_btm_cant *pcandidate_list = NULL;
+	u8 nb_rpt_is_same = _TRUE;
+	u32	ret = _FAIL;
+	u32 nb_rpt_entries = 0;	
+
+	if (from_btm) {
+		u32 mlen = sizeof(struct wnm_btm_cant) * RTW_MAX_NB_RPT_NUM;
+		pcandidate_list = (struct wnm_btm_cant *)rtw_malloc(mlen);
+		if (pcandidate_list == NULL) 
+			goto exit;				
+	}
+
+	/*clean the status set last time*/
+	_rtw_memset(&pnb->nb_rpt_ch_list, 0, sizeof(pnb->nb_rpt_ch_list));
+	pnb->nb_rpt_valid = _FALSE;
+	if (!rtw_wnm_nb_elem_parsing(
+			pframe, elem_len, from_btm, 
+			&nb_rpt_entries, &nb_rpt_is_same,
+			pnb, pcandidate_list))
+		goto exit;
+
+	if (nb_rpt_entries != 0) {
+		if ((from_btm) && (rtw_wnm_btm_preference_cap(padapter)))
+			rtw_wnm_candidates_sorting(nb_rpt_entries, pcandidate_list);
+
+		rtw_wnm_nb_info_update(
+			nb_rpt_entries, from_btm, 
+			pnb, pcandidate_list, &nb_rpt_is_same);
+	}
+
+	RTW_INFO("nb_rpt_is_same = %d, nb_rpt_entries = %d, last_nb_rpt_entries = %d\n", 
+		nb_rpt_is_same, nb_rpt_entries, pnb->last_nb_rpt_entries);
+	if ((nb_rpt_is_same == _TRUE) && (nb_rpt_entries == pnb->last_nb_rpt_entries))
+		pnb->nb_rpt_is_same = _TRUE;
+	else {
+		pnb->nb_rpt_is_same = _FALSE;
+		pnb->last_nb_rpt_entries = nb_rpt_entries;
+	}
+
+	if ((from_btm) && (nb_rpt_entries != 0))
+		rtw_wnm_btm_candidate_select(padapter);
+	
+	pnb->nb_rpt_valid = _TRUE;
+	ret = _SUCCESS;
+
+exit:
+	if (from_btm && pcandidate_list)
+		rtw_mfree((u8 *)pcandidate_list, sizeof(struct wnm_btm_cant) * RTW_MAX_NB_RPT_NUM);
+	
+	return ret;
+}
+#endif
+
+unsigned int OnAction_ft(_adapter *padapter, union recv_frame *precv_frame)
+{
+#ifdef CONFIG_RTW_80211R
+	u32	ret = _FAIL;
+	u32	frame_len = 0;
+	u8	action_code = 0;
+	u8	category = 0;
+	u8	*pframe = NULL;
+	u8	*pframe_body = NULL;
+	u8	sta_addr[ETH_ALEN] = {0};
+	u8	*pie = NULL;
+	u32	ft_ie_len = 0;
+	u32 status_code = 0;
+	struct mlme_ext_priv *pmlmeext = NULL;
+	struct mlme_ext_info *pmlmeinfo = NULL;
+	struct mlme_priv *pmlmepriv = NULL;
+	struct wlan_network *proam_target = NULL;
+	struct ft_roam_info *pft_roam = NULL;
+	_irqL  irqL;
+
+	pmlmeext = &(padapter->mlmeextpriv);
+	pmlmeinfo = &(pmlmeext->mlmext_info);
+	pmlmepriv = &(padapter->mlmepriv);
+	pft_roam = &(pmlmepriv->ft_roam);
+	pframe = precv_frame->u.hdr.rx_data;
+	frame_len = precv_frame->u.hdr.len;
+	pframe_body = pframe + sizeof(struct rtw_ieee80211_hdr_3addr);
+	category = pframe_body[0];
+
+	if (category != RTW_WLAN_CATEGORY_FT)
+		goto exit;
+
+	action_code = pframe_body[1];
+	switch (action_code) {
+	case RTW_WLAN_ACTION_FT_RSP:
+		RTW_INFO("FT: RTW_WLAN_ACTION_FT_RSP recv.\n");
+		if (!_rtw_memcmp(adapter_mac_addr(padapter), &pframe_body[2], ETH_ALEN)) {
+			RTW_ERR("FT: Unmatched STA MAC Address "MAC_FMT"\n", MAC_ARG(&pframe_body[2]));
+			goto exit;
+		}
+
+		status_code = le16_to_cpu(*(u16 *)((SIZE_PTR)pframe +  sizeof(struct rtw_ieee80211_hdr_3addr) + 14));
+		if (status_code != 0) {
+			RTW_ERR("FT: WLAN ACTION FT RESPONSE fail, status: %d\n", status_code);
+			goto exit;
+		}
+
+		if (is_zero_mac_addr(&pframe_body[8]) || is_broadcast_mac_addr(&pframe_body[8])) {
+			RTW_ERR("FT: Invalid Target MAC Address "MAC_FMT"\n", MAC_ARG(padapter->mlmepriv.roam_tgt_addr));
+			goto exit;
+		}
+
+		pie = rtw_get_ie(pframe_body, _MDIE_, &ft_ie_len, frame_len);
+		if (pie) {
+			if (!_rtw_memcmp(&pft_roam->mdid, pie+2, 2)) {
+				RTW_ERR("FT: Invalid MDID\n");
+				goto exit;
+			}
+		}
+
+		rtw_ft_set_status(padapter, RTW_FT_REQUESTED_STA);
+		_cancel_timer_ex(&pmlmeext->ft_link_timer);
+
+		/*Disconnect current AP*/
+		receive_disconnect(padapter, pmlmepriv->cur_network.network.MacAddress, WLAN_REASON_ACTIVE_ROAM, _FALSE);
+
+		pft_roam->ft_action_len = frame_len;
+		_rtw_memcpy(pft_roam->ft_action, pframe, rtw_min(frame_len, RTW_FT_MAX_IE_SZ));
+		ret = _SUCCESS;
+		break;
+	case RTW_WLAN_ACTION_FT_REQ:
+	case RTW_WLAN_ACTION_FT_CONF:
+	case RTW_WLAN_ACTION_FT_ACK:
+	default:
+		RTW_ERR("FT: Unsupported FT Action!\n");
+		break;
+	}
+
+exit:
+	return ret;
+#else
+	return _SUCCESS;
+#endif
+}
+
+#ifdef CONFIG_RTW_WNM
+u8 rtw_wmn_btm_rsp_reason_decision(_adapter *padapter, u8* req_mode)
+{
+	struct recv_priv *precvpriv = &padapter->recvpriv;
+	struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
+	u8 reason = 0;
+
+	if (!rtw_wnm_btm_diff_bss(padapter)) {
+		/* Reject - No suitable BSS transition candidates */
+		reason = 7;
+		goto candidate_remove;
+	}
+
+#ifdef CONFIG_RTW_80211R
+	if (rtw_ft_chk_flags(padapter, RTW_FT_BTM_ROAM)) {
+		/* Accept */
+		reason = 0;
+		goto under_survey;
+	}	
+#endif
+
+	if (((*req_mode) & DISASSOC_IMMINENT) == 0) {
+		/* Reject - Unspecified reject reason */
+		reason = 1;
+		goto candidate_remove;
+	}	
+
+	if (precvpriv->signal_strength_data.avg_val >= pmlmepriv->roam_rssi_threshold) {
+		reason = 1;
+		goto candidate_remove;
+	}
+
+under_survey:	
+	if (check_fwstate(pmlmepriv, _FW_UNDER_SURVEY)) {
+		RTW_INFO("%s reject due to _FW_UNDER_SURVEY\n", __func__);
+		reason = 1;
+	}
+
+candidate_remove:
+	if (reason !=0)
+		rtw_wnm_reset_btm_candidate(&padapter->mlmepriv.nb_info);
+
+	return reason;
+}
+
+static u32 rtw_wnm_btm_candidates_offset_get(u8* pframe)
+{
+	u8 *pos = pframe;
+	u32 offset = 0;
+
+	if (!pframe)
+		return 0;
+
+	offset += 7;
+	pos += offset;
+
+	/* BSS Termination Duration check */
+	if (wnm_btm_bss_term_inc(pframe)) {
+		offset += 12;
+		pos += offset;	
+	}	
+
+	/* Session Information URL check*/
+	if (wnm_btm_ess_disassoc_im(pframe)) {
+		/*URL length field + URL variable length*/
+		offset = 1 + *(pframe + offset);
+		pos += offset;	
+	}
+
+	offset = (pos - pframe);
+	return offset;
+}
+
+static void rtw_wnm_btm_req_hdr_parsing(u8* pframe, struct btm_req_hdr *phdr)
+{
+	u8 *pos = pframe;
+	u32 offset = 0;
+
+	if (!pframe || !phdr)
+		return;
+
+	_rtw_memset(phdr, 0, sizeof(struct btm_req_hdr));
+	phdr->req_mode  = wnm_btm_req_mode(pframe);
+	phdr->disassoc_timer = wnm_btm_disassoc_timer(pframe);
+	phdr->validity_interval = wnm_btm_valid_interval(pframe);
+	if (wnm_btm_bss_term_inc(pframe)) {
+		_rtw_memcpy(&phdr->term_duration, 
+			wnm_btm_term_duration_offset(pframe), 
+			sizeof(struct btm_term_duration));
+	}
+
+	RTW_DBG("WNM: req_mode(%1x), disassoc_timer(%02x), interval(%x)\n",
+		phdr->req_mode, phdr->disassoc_timer, phdr->validity_interval);
+	if (wnm_btm_bss_term_inc(pframe))
+		RTW_INFO("WNM: tsf(%llx), duration(%2x)\n",
+			phdr->term_duration.tsf, phdr->term_duration.duration);
+}
+
+void rtw_wnm_roam_scan_hdl(void *ctx)
+{
+	_adapter *padapter = (_adapter *)ctx;
+	struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
+
+	if (rtw_is_scan_deny(padapter)) 
+		RTW_INFO("WNM: roam scan would abort by scan_deny!\n");
+		
+	pmlmepriv->need_to_roam = _TRUE;
+	rtw_drv_scan_by_self(padapter, RTW_AUTO_SCAN_REASON_ROAM);
+}
+
+static void rtw_wnm_roam_scan(_adapter *padapter)
+{
+	struct roam_nb_info *pnb = &(padapter->mlmepriv.nb_info);
+
+	if (rtw_is_scan_deny(padapter)) {
+		_cancel_timer_ex(&pnb->roam_scan_timer);
+		_set_timer(&pnb->roam_scan_timer, 1000);
+	} else
+		rtw_wnm_roam_scan_hdl((void *)padapter);
+}
+
+void rtw_wnm_process_btm_req(_adapter *padapter, u8* pframe, u32 frame_len)
+{
+	struct roam_nb_info *pnb = &(padapter->mlmepriv.nb_info);
+	struct btm_req_hdr req_hdr;
+	u8 *ptr, reason;
+	u32 elem_len, offset;
+
+	rtw_wnm_btm_req_hdr_parsing(pframe, &req_hdr);
+	offset = rtw_wnm_btm_candidates_offset_get(pframe);
+	if ((offset == 0) || ((frame_len - offset) <= 15))
+		return;
+
+	ptr = (pframe + offset);
+	elem_len = (frame_len - offset);
+	rtw_wnm_btm_candidates_survey(padapter, ptr, elem_len, _TRUE);
+	reason = rtw_wmn_btm_rsp_reason_decision(padapter, &pframe[3]);
+	rtw_wnm_issue_action(padapter, 
+		RTW_WLAN_ACTION_WNM_BTM_RSP, reason);
+
+	if (reason == 0) 
+		rtw_wnm_roam_scan(padapter);
+}
+
+void rtw_wnm_reset_btm_candidate(struct roam_nb_info *pnb)
+{
+	pnb->preference_en = _FALSE;
+	_rtw_memset(pnb->roam_target_addr, 0, ETH_ALEN);
+}
+
+void rtw_wnm_reset_btm_state(_adapter *padapter)
+{
+	struct roam_nb_info *pnb = &(padapter->mlmepriv.nb_info);
+
+	pnb->last_nb_rpt_entries = 0;
+	pnb->nb_rpt_is_same = _TRUE;
+	pnb->nb_rpt_valid = _FALSE;
+	pnb->nb_rpt_ch_list_num = 0;
+	rtw_wnm_reset_btm_candidate(pnb);
+	_rtw_memset(&pnb->nb_rpt, 0, sizeof(pnb->nb_rpt));
+	_rtw_memset(&pnb->nb_rpt_ch_list, 0, sizeof(pnb->nb_rpt_ch_list));
+}
+
+void rtw_wnm_issue_action(_adapter *padapter, u8 action, u8 reason)
+{
+	struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
+	struct xmit_priv *pxmitpriv = &(padapter->xmitpriv);
+	struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv);
+	struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
+	struct xmit_frame *pmgntframe;
+	struct rtw_ieee80211_hdr *pwlanhdr;
+	struct pkt_attrib *pattrib;
+	u8 category, dialog_token, termination_delay, *pframe;
+	u16 *fctrl;
+
+	if ((pmgntframe = alloc_mgtxmitframe(pxmitpriv)) == NULL)
+		return ;
+	
+	pattrib = &(pmgntframe->attrib);
+	update_mgntframe_attrib(padapter, pattrib);
+	_rtw_memset(pmgntframe->buf_addr, 0, (WLANHDR_OFFSET + TXDESC_OFFSET));
+
+	pframe = (u8 *)(pmgntframe->buf_addr + TXDESC_OFFSET);
+	pwlanhdr = (struct rtw_ieee80211_hdr *)pframe;
+
+	fctrl = &(pwlanhdr->frame_ctl);
+	*(fctrl) = 0;
+
+	_rtw_memcpy(pwlanhdr->addr1, get_my_bssid(&pmlmeinfo->network), ETH_ALEN);
+	_rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN);
+	_rtw_memcpy(pwlanhdr->addr3, get_my_bssid(&pmlmeinfo->network), ETH_ALEN);
+
+	SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq);
+	pmlmeext->mgnt_seq++;
+	set_frame_sub_type(pframe, WIFI_ACTION);
+
+	pframe += sizeof(struct rtw_ieee80211_hdr_3addr);
+	pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr);
+
+	category = RTW_WLAN_CATEGORY_WNM;
+	pframe = rtw_set_fixed_ie(pframe, 1, &(category), &(pattrib->pktlen));
+	pframe = rtw_set_fixed_ie(pframe, 1, &(action), &(pattrib->pktlen));
+
+	switch (action) {
+		case RTW_WLAN_ACTION_WNM_BTM_QUERY:
+			pframe = rtw_set_fixed_ie(pframe, 1, &(dialog_token), &(pattrib->pktlen));
+			pframe = rtw_set_fixed_ie(pframe, 1, &(reason), &(pattrib->pktlen));
+			RTW_INFO("WNM: RTW_WLAN_ACTION_WNM_BTM_QUERY sent.\n");
+			break;
+		case RTW_WLAN_ACTION_WNM_BTM_RSP:
+			termination_delay = 0;
+			pframe = rtw_set_fixed_ie(pframe, 1, &(dialog_token), &(pattrib->pktlen));
+			pframe = rtw_set_fixed_ie(pframe, 1, &(reason), &(pattrib->pktlen));
+			pframe = rtw_set_fixed_ie(pframe, 1, &(termination_delay), &(pattrib->pktlen));
+			if (!is_zero_mac_addr(pmlmepriv->nb_info.roam_target_addr)) {
+				pframe = rtw_set_fixed_ie(pframe, 6, 
+					pmlmepriv->nb_info.roam_target_addr, &(pattrib->pktlen));
+			}
+			RTW_INFO("WNM: RTW_WLAN_ACTION_WNM_BTM_RSP sent. reason = %d\n", reason);			
+			break;		
+		default:
+			goto exit;
+	}	
+	
+	pattrib->last_txcmdsz = pattrib->pktlen;
+	dump_mgntframe(padapter, pmgntframe);
+
+exit:	
+	return;
+}
+#endif
+
+unsigned int OnAction_ht(_adapter *padapter, union recv_frame *precv_frame)
+{
+	u8 *pframe = precv_frame->u.hdr.rx_data;
+	u8 *frame_body = pframe + sizeof(struct rtw_ieee80211_hdr_3addr);
+	u8 category, action;
+
+	/* check RA matches or not */
+	if (!_rtw_memcmp(adapter_mac_addr(padapter), GetAddr1Ptr(pframe), ETH_ALEN))
+		goto exit;
+
+	category = frame_body[0];
+	if (category != RTW_WLAN_CATEGORY_HT)
+		goto exit;
+
+	action = frame_body[1];
+	switch (action) {
+	case RTW_WLAN_ACTION_HT_SM_PS:
+#ifdef CONFIG_80211N_HT
+#ifdef CONFIG_AP_MODE
+		if (check_fwstate(&padapter->mlmepriv, WIFI_AP_STATE) == _TRUE)
+			rtw_process_ht_action_smps(padapter, get_addr2_ptr(pframe), frame_body[2]);
+#endif /*CONFIG_AP_MODE*/
+#endif /*CONFIG_80211N_HT*/
+		break;
+	case RTW_WLAN_ACTION_HT_COMPRESS_BEAMFORMING:
+#ifdef CONFIG_BEAMFORMING
+		/*RTW_INFO("RTW_WLAN_ACTION_HT_COMPRESS_BEAMFORMING\n");*/
+		rtw_beamforming_get_report_frame(padapter, precv_frame);
+#endif /*CONFIG_BEAMFORMING*/
+		break;
+	default:
+		break;
+	}
+
+exit:
+
+	return _SUCCESS;
+}
+
+#ifdef CONFIG_IEEE80211W
+unsigned int OnAction_sa_query(_adapter *padapter, union recv_frame *precv_frame)
+{
+	u8 *pframe = precv_frame->u.hdr.rx_data;
+	struct rx_pkt_attrib *pattrib = &precv_frame->u.hdr.attrib;
+	struct mlme_ext_priv	*pmlmeext = &(padapter->mlmeextpriv);
+	struct sta_info		*psta;
+	struct sta_priv		*pstapriv = &padapter->stapriv;
+	struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
+	u16 tid;
+	/* Baron */
+
+	RTW_INFO("OnAction_sa_query\n");
+
+	switch (pframe[WLAN_HDR_A3_LEN + 1]) {
+	case 0: /* SA Query req */
+		_rtw_memcpy(&tid, &pframe[WLAN_HDR_A3_LEN + 2], sizeof(u16));
+		RTW_INFO("OnAction_sa_query request,action=%d, tid=%04x, pframe=%02x-%02x\n"
+			, pframe[WLAN_HDR_A3_LEN + 1], tid, pframe[WLAN_HDR_A3_LEN + 2], pframe[WLAN_HDR_A3_LEN + 3]);
+		issue_action_SA_Query(padapter, get_addr2_ptr(pframe), 1, tid, IEEE80211W_RIGHT_KEY);
+		break;
+
+	case 1: /* SA Query rsp */
+		psta = rtw_get_stainfo(pstapriv, get_addr2_ptr(pframe));
+		if (psta != NULL)
+			_cancel_timer_ex(&psta->dot11w_expire_timer);
+
+		_rtw_memcpy(&tid, &pframe[WLAN_HDR_A3_LEN + 2], sizeof(u16));
+		RTW_INFO("OnAction_sa_query response,action=%d, tid=%04x, cancel timer\n", pframe[WLAN_HDR_A3_LEN + 1], tid);
+		break;
+	default:
+		break;
+	}
+	if (0) {
+		int pp;
+		printk("pattrib->pktlen = %d =>", pattrib->pkt_len);
+		for (pp = 0; pp < pattrib->pkt_len; pp++)
+			printk(" %02x ", pframe[pp]);
+		printk("\n");
+	}
+
+	return _SUCCESS;
+}
+#endif /* CONFIG_IEEE80211W */
+
+unsigned int on_action_rm(_adapter *padapter, union recv_frame *precv_frame)
+{
+#ifdef CONFIG_RTW_80211K
+	return rm_on_action(padapter, precv_frame);
+#else
+	return _SUCCESS;
+#endif  /* CONFIG_RTW_80211K */
+}
+
+unsigned int OnAction_wmm(_adapter *padapter, union recv_frame *precv_frame)
+{
+	return _SUCCESS;
+}
+
+unsigned int OnAction_vht(_adapter *padapter, union recv_frame *precv_frame)
+{
+#ifdef CONFIG_80211AC_VHT
+	u8 *pframe = precv_frame->u.hdr.rx_data;
+	struct rtw_ieee80211_hdr_3addr *whdr = (struct rtw_ieee80211_hdr_3addr *)pframe;
+	u8 *frame_body = pframe + sizeof(struct rtw_ieee80211_hdr_3addr);
+	u8 category, action;
+	struct sta_info *psta = NULL;
+
+	/* check RA matches or not */
+	if (!_rtw_memcmp(adapter_mac_addr(padapter), GetAddr1Ptr(pframe), ETH_ALEN))
+		goto exit;
+
+	category = frame_body[0];
+	if (category != RTW_WLAN_CATEGORY_VHT)
+		goto exit;
+
+	action = frame_body[1];
+	switch (action) {
+	case RTW_WLAN_ACTION_VHT_COMPRESSED_BEAMFORMING:
+#ifdef CONFIG_BEAMFORMING
+		/*RTW_INFO("RTW_WLAN_ACTION_VHT_COMPRESSED_BEAMFORMING\n");*/
+		rtw_beamforming_get_report_frame(padapter, precv_frame);
+#endif /*CONFIG_BEAMFORMING*/
+		break;
+	case RTW_WLAN_ACTION_VHT_OPMODE_NOTIFICATION:
+		/* CategoryCode(1) + ActionCode(1) + OpModeNotification(1) */
+		/* RTW_INFO("RTW_WLAN_ACTION_VHT_OPMODE_NOTIFICATION\n"); */
+		psta = rtw_get_stainfo(&padapter->stapriv, whdr->addr2);
+		if (psta)
+			rtw_process_vht_op_mode_notify(padapter, &frame_body[2], psta);
+		break;
+	case RTW_WLAN_ACTION_VHT_GROUPID_MANAGEMENT:
+#ifdef CONFIG_BEAMFORMING
+#ifdef RTW_BEAMFORMING_VERSION_2
+		rtw_beamforming_get_vht_gid_mgnt_frame(padapter, precv_frame);
+#endif /* RTW_BEAMFORMING_VERSION_2 */
+#endif /* CONFIG_BEAMFORMING */
+		break;
+	default:
+		break;
+	}
+
+exit:
+#endif /* CONFIG_80211AC_VHT */
+
+	return _SUCCESS;
+}
+
+unsigned int OnAction_p2p(_adapter *padapter, union recv_frame *precv_frame)
+{
+#ifdef CONFIG_P2P
+	u8 *frame_body;
+	u8 category, OUI_Subtype, dialogToken = 0;
+	u8 *pframe = precv_frame->u.hdr.rx_data;
+	uint len = precv_frame->u.hdr.len;
+	struct	wifidirect_info	*pwdinfo = &(padapter->wdinfo);
+
+	/* check RA matches or not */
+	if (!_rtw_memcmp(adapter_mac_addr(padapter), GetAddr1Ptr(pframe), ETH_ALEN))
+		return _SUCCESS;
+
+	frame_body = (unsigned char *)(pframe + sizeof(struct rtw_ieee80211_hdr_3addr));
+
+	category = frame_body[0];
+	if (category != RTW_WLAN_CATEGORY_P2P)
+		return _SUCCESS;
+
+	if (cpu_to_be32(*((u32 *)(frame_body + 1))) != P2POUI)
+		return _SUCCESS;
+
+#ifdef CONFIG_IOCTL_CFG80211
+	if (adapter_wdev_data(padapter)->p2p_enabled
+		&& pwdinfo->driver_interface == DRIVER_CFG80211
+	) {
+		rtw_cfg80211_rx_action_p2p(padapter, precv_frame);
+		return _SUCCESS;
+	} else
+#endif /* CONFIG_IOCTL_CFG80211 */
+	{
+		len -= sizeof(struct rtw_ieee80211_hdr_3addr);
+		OUI_Subtype = frame_body[5];
+		dialogToken = frame_body[6];
+
+		switch (OUI_Subtype) {
+		case P2P_NOTICE_OF_ABSENCE:
+
+			break;
+
+		case P2P_PRESENCE_REQUEST:
+
+			process_p2p_presence_req(pwdinfo, pframe, len);
+
+			break;
+
+		case P2P_PRESENCE_RESPONSE:
+
+			break;
+
+		case P2P_GO_DISC_REQUEST:
+
+			break;
+
+		default:
+			break;
+
+		}
+	}
+#endif /* CONFIG_P2P */
+
+	return _SUCCESS;
+
+}
+
+unsigned int OnAction(_adapter *padapter, union recv_frame *precv_frame)
+{
+	int i;
+	unsigned char	category;
+	struct action_handler *ptable;
+	unsigned char	*frame_body;
+	u8 *pframe = precv_frame->u.hdr.rx_data;
+
+	frame_body = (unsigned char *)(pframe + sizeof(struct rtw_ieee80211_hdr_3addr));
+
+	category = frame_body[0];
+
+	for (i = 0; i < sizeof(OnAction_tbl) / sizeof(struct action_handler); i++) {
+		ptable = &OnAction_tbl[i];
+
+		if (category == ptable->num)
+			ptable->func(padapter, precv_frame);
+
+	}
+
+	return _SUCCESS;
+
+}
+
+unsigned int DoReserved(_adapter *padapter, union recv_frame *precv_frame)
+{
+
+	/* RTW_INFO("rcvd mgt frame(%x, %x)\n", (get_frame_sub_type(pframe) >> 4), *(unsigned int *)GetAddr1Ptr(pframe)); */
+	return _SUCCESS;
+}
+
+struct xmit_frame *_alloc_mgtxmitframe(struct xmit_priv *pxmitpriv, bool once)
+{
+	struct xmit_frame *pmgntframe;
+	struct xmit_buf *pxmitbuf;
+
+	if (once)
+		pmgntframe = rtw_alloc_xmitframe_once(pxmitpriv);
+	else
+		pmgntframe = rtw_alloc_xmitframe_ext(pxmitpriv);
+
+	if (pmgntframe == NULL) {
+		RTW_INFO(FUNC_ADPT_FMT" alloc xmitframe fail, once:%d\n", FUNC_ADPT_ARG(pxmitpriv->adapter), once);
+		goto exit;
+	}
+
+	pxmitbuf = rtw_alloc_xmitbuf_ext(pxmitpriv);
+	if (pxmitbuf == NULL) {
+		RTW_INFO(FUNC_ADPT_FMT" alloc xmitbuf fail\n", FUNC_ADPT_ARG(pxmitpriv->adapter));
+		rtw_free_xmitframe(pxmitpriv, pmgntframe);
+		pmgntframe = NULL;
+		goto exit;
+	}
+
+	pmgntframe->frame_tag = MGNT_FRAMETAG;
+	pmgntframe->pxmitbuf = pxmitbuf;
+	pmgntframe->buf_addr = pxmitbuf->pbuf;
+	pxmitbuf->priv_data = pmgntframe;
+
+exit:
+	return pmgntframe;
+
+}
+
+inline struct xmit_frame *alloc_mgtxmitframe(struct xmit_priv *pxmitpriv)
+{
+	return _alloc_mgtxmitframe(pxmitpriv, _FALSE);
+}
+
+inline struct xmit_frame *alloc_mgtxmitframe_once(struct xmit_priv *pxmitpriv)
+{
+	return _alloc_mgtxmitframe(pxmitpriv, _TRUE);
+}
+
+
+/****************************************************************************
+
+Following are some TX fuctions for WiFi MLME
+
+*****************************************************************************/
+
+void update_mgnt_tx_rate(_adapter *padapter, u8 rate)
+{
+	struct mlme_ext_priv	*pmlmeext = &(padapter->mlmeextpriv);
+
+	pmlmeext->tx_rate = rate;
+	/* RTW_INFO("%s(): rate = %x\n",__FUNCTION__, rate); */
+}
+
+
+void update_monitor_frame_attrib(_adapter *padapter, struct pkt_attrib *pattrib)
+{
+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(padapter);
+	u8	wireless_mode;
+	struct mlme_ext_priv	*pmlmeext = &(padapter->mlmeextpriv);
+	struct xmit_priv		*pxmitpriv = &padapter->xmitpriv;
+	struct sta_info		*psta = NULL;
+	struct sta_priv		*pstapriv = &padapter->stapriv;
+
+	psta = rtw_get_stainfo(pstapriv, pattrib->ra);
+
+	pattrib->hdrlen = 24;
+	pattrib->nr_frags = 1;
+	pattrib->priority = 7;
+	pattrib->mac_id = RTW_DEFAULT_MGMT_MACID;
+	pattrib->qsel = QSLT_MGNT;
+
+	pattrib->pktlen = 0;
+
+	if (pmlmeext->tx_rate == IEEE80211_CCK_RATE_1MB)
+		wireless_mode = WIRELESS_11B;
+	else
+		wireless_mode = WIRELESS_11G;
+
+	pattrib->raid = rtw_get_mgntframe_raid(padapter, wireless_mode);
+#ifdef CONFIG_80211AC_VHT
+	if (pHalData->rf_type == RF_1T1R)
+		pattrib->raid = RATEID_IDX_VHT_1SS;
+	else if (pHalData->rf_type == RF_2T2R || pHalData->rf_type == RF_2T4R)
+		pattrib->raid = RATEID_IDX_VHT_2SS;
+	else if (pHalData->rf_type == RF_3T3R)
+		pattrib->raid = RATEID_IDX_VHT_3SS;
+	else
+		pattrib->raid = RATEID_IDX_BGN_40M_1SS;
+#endif
+
+#ifdef CONFIG_80211AC_VHT
+	pattrib->rate = MGN_VHT1SS_MCS9;
+#else
+	pattrib->rate = MGN_MCS7;
+#endif
+
+	pattrib->encrypt = _NO_PRIVACY_;
+	pattrib->bswenc = _FALSE;
+
+	pattrib->qos_en = _FALSE;
+	pattrib->ht_en = 1;
+	pattrib->bwmode = CHANNEL_WIDTH_20;
+	pattrib->ch_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
+	pattrib->sgi = _FALSE;
+
+	pattrib->seqnum = pmlmeext->mgnt_seq;
+
+	pattrib->retry_ctrl = _TRUE;
+
+	pattrib->mbssid = 0;
+	pattrib->hw_ssn_sel = pxmitpriv->hw_ssn_seq_no;
+
+}
+
+
+void update_mgntframe_attrib(_adapter *padapter, struct pkt_attrib *pattrib)
+{
+	u8	wireless_mode;
+	struct mlme_ext_priv	*pmlmeext = &(padapter->mlmeextpriv);
+	struct xmit_priv		*pxmitpriv = &padapter->xmitpriv;
+	/* _rtw_memset((u8 *)(pattrib), 0, sizeof(struct pkt_attrib)); */
+
+	pattrib->hdrlen = 24;
+	pattrib->nr_frags = 1;
+	pattrib->priority = 7;
+	pattrib->mac_id = RTW_DEFAULT_MGMT_MACID;
+	pattrib->qsel = QSLT_MGNT;
+
+#ifdef CONFIG_MCC_MODE
+	update_mcc_mgntframe_attrib(padapter, pattrib);
+#endif
+
+	pattrib->pktlen = 0;
+
+	if (IS_CCK_RATE(pmlmeext->tx_rate))
+		wireless_mode = WIRELESS_11B;
+	else
+		wireless_mode = WIRELESS_11G;
+	pattrib->raid =  rtw_get_mgntframe_raid(padapter, wireless_mode);
+	pattrib->rate = pmlmeext->tx_rate;
+
+	pattrib->encrypt = _NO_PRIVACY_;
+	pattrib->bswenc = _FALSE;
+
+	pattrib->qos_en = _FALSE;
+	pattrib->ht_en = _FALSE;
+	pattrib->bwmode = CHANNEL_WIDTH_20;
+	pattrib->ch_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
+	pattrib->sgi = _FALSE;
+
+	pattrib->seqnum = pmlmeext->mgnt_seq;
+
+	pattrib->retry_ctrl = _TRUE;
+
+	pattrib->mbssid = 0;
+	pattrib->hw_ssn_sel = pxmitpriv->hw_ssn_seq_no;
+}
+
+void update_mgntframe_attrib_addr(_adapter *padapter, struct xmit_frame *pmgntframe)
+{
+	u8	*pframe;
+	struct pkt_attrib	*pattrib = &pmgntframe->attrib;
+#if defined(CONFIG_BEAMFORMING) || defined(CONFIG_ANTENNA_DIVERSITY)
+	struct sta_info		*sta = NULL;
+#endif
+
+	pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET;
+
+	_rtw_memcpy(pattrib->ra, GetAddr1Ptr(pframe), ETH_ALEN);
+	_rtw_memcpy(pattrib->ta, get_addr2_ptr(pframe), ETH_ALEN);
+
+#if defined(CONFIG_BEAMFORMING) || defined(CONFIG_ANTENNA_DIVERSITY)
+	sta = pattrib->psta;
+	if (!sta) {
+		sta = rtw_get_stainfo(&padapter->stapriv, pattrib->ra);
+		pattrib->psta = sta;
+	}
+	#ifdef CONFIG_BEAMFORMING
+	if (sta)
+		update_attrib_txbf_info(padapter, pattrib, sta);
+	#endif
+#endif /* defined(CONFIG_BEAMFORMING) || defined(CONFIG_ANTENNA_DIVERSITY) */
+}
+
+void dump_mgntframe(_adapter *padapter, struct xmit_frame *pmgntframe)
+{
+	if (RTW_CANNOT_RUN(padapter)) {
+		rtw_free_xmitbuf(&padapter->xmitpriv, pmgntframe->pxmitbuf);
+		rtw_free_xmitframe(&padapter->xmitpriv, pmgntframe);
+		return;
+	}
+
+	rtw_hal_mgnt_xmit(padapter, pmgntframe);
+}
+
+s32 dump_mgntframe_and_wait(_adapter *padapter, struct xmit_frame *pmgntframe, int timeout_ms)
+{
+	s32 ret = _FAIL;
+	_irqL irqL;
+	struct xmit_priv *pxmitpriv = &padapter->xmitpriv;
+	struct xmit_buf *pxmitbuf = pmgntframe->pxmitbuf;
+	struct submit_ctx sctx;
+
+	if (RTW_CANNOT_RUN(padapter)) {
+		rtw_free_xmitbuf(&padapter->xmitpriv, pmgntframe->pxmitbuf);
+		rtw_free_xmitframe(&padapter->xmitpriv, pmgntframe);
+		return ret;
+	}
+
+	rtw_sctx_init(&sctx, timeout_ms);
+	pxmitbuf->sctx = &sctx;
+
+	ret = rtw_hal_mgnt_xmit(padapter, pmgntframe);
+
+	if (ret == _SUCCESS)
+		ret = rtw_sctx_wait(&sctx, __func__);
+
+	_enter_critical(&pxmitpriv->lock_sctx, &irqL);
+	pxmitbuf->sctx = NULL;
+	_exit_critical(&pxmitpriv->lock_sctx, &irqL);
+
+	return ret;
+}
+
+s32 dump_mgntframe_and_wait_ack_timeout(_adapter *padapter, struct xmit_frame *pmgntframe, int timeout_ms)
+{
+#ifdef CONFIG_XMIT_ACK
+	static u8 seq_no = 0;
+	s32 ret = _FAIL;
+	struct xmit_priv	*pxmitpriv = &(GET_PRIMARY_ADAPTER(padapter))->xmitpriv;
+
+	if (RTW_CANNOT_RUN(padapter)) {
+		rtw_free_xmitbuf(&padapter->xmitpriv, pmgntframe->pxmitbuf);
+		rtw_free_xmitframe(&padapter->xmitpriv, pmgntframe);
+		return -1;
+	}
+
+	_enter_critical_mutex(&pxmitpriv->ack_tx_mutex, NULL);
+	pxmitpriv->ack_tx = _TRUE;
+	pxmitpriv->seq_no = seq_no++;
+	pmgntframe->ack_report = 1;
+	rtw_sctx_init(&(pxmitpriv->ack_tx_ops), timeout_ms);
+	if (rtw_hal_mgnt_xmit(padapter, pmgntframe) == _SUCCESS)
+		ret = rtw_sctx_wait(&(pxmitpriv->ack_tx_ops), __func__);
+
+	pxmitpriv->ack_tx = _FALSE;
+	_exit_critical_mutex(&pxmitpriv->ack_tx_mutex, NULL);
+
+	return ret;
+#else /* !CONFIG_XMIT_ACK */
+	dump_mgntframe(padapter, pmgntframe);
+	rtw_msleep_os(50);
+	return _SUCCESS;
+#endif /* !CONFIG_XMIT_ACK */
+}
+
+s32 dump_mgntframe_and_wait_ack(_adapter *padapter, struct xmit_frame *pmgntframe)
+{
+	/* In this case, use 500 ms as the default wait_ack timeout */
+	return dump_mgntframe_and_wait_ack_timeout(padapter, pmgntframe, 500);
+}
+
+
+int update_hidden_ssid(u8 *ies, u32 ies_len, u8 hidden_ssid_mode)
+{
+	u8 *ssid_ie;
+	sint ssid_len_ori;
+	int len_diff = 0;
+
+	ssid_ie = rtw_get_ie(ies,  WLAN_EID_SSID, &ssid_len_ori, ies_len);
+
+	/* RTW_INFO("%s hidden_ssid_mode:%u, ssid_ie:%p, ssid_len_ori:%d\n", __FUNCTION__, hidden_ssid_mode, ssid_ie, ssid_len_ori); */
+
+	if (ssid_ie && ssid_len_ori > 0) {
+		switch (hidden_ssid_mode) {
+		case 1: {
+			u8 *next_ie = ssid_ie + 2 + ssid_len_ori;
+			u32 remain_len = 0;
+
+			remain_len = ies_len - (next_ie - ies);
+
+			ssid_ie[1] = 0;
+			_rtw_memcpy(ssid_ie + 2, next_ie, remain_len);
+			len_diff -= ssid_len_ori;
+
+			break;
+		}
+		case 2:
+			_rtw_memset(&ssid_ie[2], 0, ssid_len_ori);
+			break;
+		default:
+			break;
+		}
+	}
+
+	return len_diff;
+}
+
+#ifdef CONFIG_APPEND_VENDOR_IE_ENABLE
+u32 rtw_build_vendor_ie(_adapter *padapter , unsigned char *pframe , u8 mgmt_frame_tyte)
+{
+	int vendor_ie_num = 0;
+	struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
+	u32 len = 0;
+
+	for (vendor_ie_num = 0 ; vendor_ie_num < WLAN_MAX_VENDOR_IE_NUM ; vendor_ie_num++) {
+		if (pmlmepriv->vendor_ielen[vendor_ie_num] > 0 && pmlmepriv->vendor_ie_mask[vendor_ie_num] & mgmt_frame_tyte) {
+			_rtw_memcpy(pframe , pmlmepriv->vendor_ie[vendor_ie_num] , pmlmepriv->vendor_ielen[vendor_ie_num]);
+			pframe +=  pmlmepriv->vendor_ielen[vendor_ie_num];
+			len += pmlmepriv->vendor_ielen[vendor_ie_num];
+		}
+	}
+
+	return len;
+}
+#endif
+
+void issue_beacon(_adapter *padapter, int timeout_ms)
+{
+	struct xmit_frame	*pmgntframe;
+	struct pkt_attrib	*pattrib;
+	unsigned char	*pframe;
+	struct rtw_ieee80211_hdr *pwlanhdr;
+	unsigned short *fctrl;
+	unsigned int	rate_len;
+	struct xmit_priv	*pxmitpriv = &(padapter->xmitpriv);
+#if defined(CONFIG_AP_MODE) && defined (CONFIG_NATIVEAP_MLME)
+	_irqL irqL;
+	struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
+#endif /* #if defined (CONFIG_AP_MODE) && defined (CONFIG_NATIVEAP_MLME) */
+	struct mlme_ext_priv	*pmlmeext = &(padapter->mlmeextpriv);
+	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
+	WLAN_BSSID_EX		*cur_network = &(pmlmeinfo->network);
+	u8	bc_addr[] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
+#ifdef CONFIG_P2P
+	struct wifidirect_info	*pwdinfo = &(padapter->wdinfo);
+#endif /* CONFIG_P2P */
+
+
+	/* RTW_INFO("%s\n", __FUNCTION__); */
+
+#ifdef CONFIG_BCN_ICF
+	pmgntframe = rtw_alloc_bcnxmitframe(pxmitpriv);
+	if (pmgntframe == NULL)
+#else
+	pmgntframe = alloc_mgtxmitframe(pxmitpriv);
+	if (pmgntframe == NULL)
+#endif
+	{
+		RTW_INFO("%s, alloc mgnt frame fail\n", __FUNCTION__);
+		return;
+	}
+#if defined(CONFIG_AP_MODE) && defined (CONFIG_NATIVEAP_MLME)
+	_enter_critical_bh(&pmlmepriv->bcn_update_lock, &irqL);
+#endif /* #if defined (CONFIG_AP_MODE) && defined (CONFIG_NATIVEAP_MLME) */
+
+	/* update attribute */
+	pattrib = &pmgntframe->attrib;
+	update_mgntframe_attrib(padapter, pattrib);
+	pattrib->qsel = QSLT_BEACON;
+
+#if defined(CONFIG_CONCURRENT_MODE) && (!defined(CONFIG_SWTIMER_BASED_TXBCN))
+	if (padapter->hw_port == HW_PORT1)
+		pattrib->mbssid = 1;
+#endif
+#ifdef CONFIG_FW_HANDLE_TXBCN
+	if (padapter->vap_id != CONFIG_LIMITED_AP_NUM)
+		pattrib->mbssid = padapter->vap_id;
+#endif
+
+	_rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET);
+
+	pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET;
+	pwlanhdr = (struct rtw_ieee80211_hdr *)pframe;
+
+
+	fctrl = &(pwlanhdr->frame_ctl);
+	*(fctrl) = 0;
+
+	_rtw_memcpy(pwlanhdr->addr1, bc_addr, ETH_ALEN);
+	_rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN);
+	_rtw_memcpy(pwlanhdr->addr3, get_my_bssid(cur_network), ETH_ALEN);
+
+	SetSeqNum(pwlanhdr, 0/*pmlmeext->mgnt_seq*/);
+	/* pmlmeext->mgnt_seq++; */
+	set_frame_sub_type(pframe, WIFI_BEACON);
+
+	pframe += sizeof(struct rtw_ieee80211_hdr_3addr);
+	pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr);
+
+	if (MLME_IS_AP(padapter) || MLME_IS_MESH(padapter)) {
+		/* RTW_INFO("ie len=%d\n", cur_network->IELength); */
+#ifdef CONFIG_P2P
+		/* for P2P : Primary Device Type & Device Name */
+		u32 wpsielen = 0, insert_len = 0;
+		u8 *wpsie = NULL;
+		wpsie = rtw_get_wps_ie(cur_network->IEs + _FIXED_IE_LENGTH_, cur_network->IELength - _FIXED_IE_LENGTH_, NULL, &wpsielen);
+
+		if (rtw_p2p_chk_role(pwdinfo, P2P_ROLE_GO) && wpsie && wpsielen > 0) {
+			uint wps_offset, remainder_ielen;
+			u8 *premainder_ie, *pframe_wscie;
+
+			wps_offset = (uint)(wpsie - cur_network->IEs);
+
+			premainder_ie = wpsie + wpsielen;
+
+			remainder_ielen = cur_network->IELength - wps_offset - wpsielen;
+
+#ifdef CONFIG_IOCTL_CFG80211
+			if (adapter_wdev_data(padapter)->p2p_enabled && pwdinfo->driver_interface == DRIVER_CFG80211) {
+				if (pmlmepriv->wps_beacon_ie && pmlmepriv->wps_beacon_ie_len > 0) {
+					_rtw_memcpy(pframe, cur_network->IEs, wps_offset);
+					pframe += wps_offset;
+					pattrib->pktlen += wps_offset;
+
+					_rtw_memcpy(pframe, pmlmepriv->wps_beacon_ie, pmlmepriv->wps_beacon_ie_len);
+					pframe += pmlmepriv->wps_beacon_ie_len;
+					pattrib->pktlen += pmlmepriv->wps_beacon_ie_len;
+
+					/* copy remainder_ie to pframe */
+					_rtw_memcpy(pframe, premainder_ie, remainder_ielen);
+					pframe += remainder_ielen;
+					pattrib->pktlen += remainder_ielen;
+				} else {
+					_rtw_memcpy(pframe, cur_network->IEs, cur_network->IELength);
+					pframe += cur_network->IELength;
+					pattrib->pktlen += cur_network->IELength;
+				}
+			} else
+#endif /* CONFIG_IOCTL_CFG80211 */
+			{
+				pframe_wscie = pframe + wps_offset;
+				_rtw_memcpy(pframe, cur_network->IEs, wps_offset + wpsielen);
+				pframe += (wps_offset + wpsielen);
+				pattrib->pktlen += (wps_offset + wpsielen);
+
+				/* now pframe is end of wsc ie, insert Primary Device Type & Device Name */
+				/*	Primary Device Type */
+				/*	Type: */
+				*(u16 *)(pframe + insert_len) = cpu_to_be16(WPS_ATTR_PRIMARY_DEV_TYPE);
+				insert_len += 2;
+
+				/*	Length: */
+				*(u16 *)(pframe + insert_len) = cpu_to_be16(0x0008);
+				insert_len += 2;
+
+				/*	Value: */
+				/*	Category ID */
+				*(u16 *)(pframe + insert_len) = cpu_to_be16(WPS_PDT_CID_MULIT_MEDIA);
+				insert_len += 2;
+
+				/*	OUI */
+				*(u32 *)(pframe + insert_len) = cpu_to_be32(WPSOUI);
+				insert_len += 4;
+
+				/*	Sub Category ID */
+				*(u16 *)(pframe + insert_len) = cpu_to_be16(WPS_PDT_SCID_MEDIA_SERVER);
+				insert_len += 2;
+
+
+				/*	Device Name */
+				/*	Type: */
+				*(u16 *)(pframe + insert_len) = cpu_to_be16(WPS_ATTR_DEVICE_NAME);
+				insert_len += 2;
+
+				/*	Length: */
+				*(u16 *)(pframe + insert_len) = cpu_to_be16(pwdinfo->device_name_len);
+				insert_len += 2;
+
+				/*	Value: */
+				_rtw_memcpy(pframe + insert_len, pwdinfo->device_name, pwdinfo->device_name_len);
+				insert_len += pwdinfo->device_name_len;
+
+
+				/* update wsc ie length */
+				*(pframe_wscie + 1) = (wpsielen - 2) + insert_len;
+
+				/* pframe move to end */
+				pframe += insert_len;
+				pattrib->pktlen += insert_len;
+
+				/* copy remainder_ie to pframe */
+				_rtw_memcpy(pframe, premainder_ie, remainder_ielen);
+				pframe += remainder_ielen;
+				pattrib->pktlen += remainder_ielen;
+			}
+		} else
+#endif /* CONFIG_P2P */
+		{
+			int len_diff;
+			_rtw_memcpy(pframe, cur_network->IEs, cur_network->IELength);
+			len_diff = update_hidden_ssid(
+					   pframe + _BEACON_IE_OFFSET_
+				   , cur_network->IELength - _BEACON_IE_OFFSET_
+					   , pmlmeinfo->hidden_ssid_mode
+				   );
+			pframe += (cur_network->IELength + len_diff);
+			pattrib->pktlen += (cur_network->IELength + len_diff);
+		}
+
+		{
+			u8 *wps_ie;
+			uint wps_ielen;
+			u8 sr = 0;
+			wps_ie = rtw_get_wps_ie(pmgntframe->buf_addr + TXDESC_OFFSET + sizeof(struct rtw_ieee80211_hdr_3addr) + _BEACON_IE_OFFSET_,
+				pattrib->pktlen - sizeof(struct rtw_ieee80211_hdr_3addr) - _BEACON_IE_OFFSET_, NULL, &wps_ielen);
+			if (wps_ie && wps_ielen > 0)
+				rtw_get_wps_attr_content(wps_ie,  wps_ielen, WPS_ATTR_SELECTED_REGISTRAR, (u8 *)(&sr), NULL);
+			if (sr != 0)
+				set_fwstate(pmlmepriv, WIFI_UNDER_WPS);
+			else
+				_clr_fwstate_(pmlmepriv, WIFI_UNDER_WPS);
+		}
+
+#ifdef CONFIG_RTW_80211K
+		pframe = rtw_set_ie(pframe, _EID_RRM_EN_CAP_IE_,
+			sizeof(padapter->rmpriv.rm_en_cap_def),
+			padapter->rmpriv.rm_en_cap_def, &pattrib->pktlen);
+#endif
+
+#ifdef CONFIG_P2P
+		if (rtw_p2p_chk_role(pwdinfo, P2P_ROLE_GO)) {
+			u32 len;
+#ifdef CONFIG_IOCTL_CFG80211
+			if (adapter_wdev_data(padapter)->p2p_enabled && pwdinfo->driver_interface == DRIVER_CFG80211) {
+				len = pmlmepriv->p2p_beacon_ie_len;
+				if (pmlmepriv->p2p_beacon_ie && len > 0)
+					_rtw_memcpy(pframe, pmlmepriv->p2p_beacon_ie, len);
+			} else
+#endif /* CONFIG_IOCTL_CFG80211 */
+			{
+				len = build_beacon_p2p_ie(pwdinfo, pframe);
+			}
+
+			pframe += len;
+			pattrib->pktlen += len;
+
+#ifdef CONFIG_MCC_MODE
+			pframe = rtw_hal_mcc_append_go_p2p_ie(padapter, pframe, &pattrib->pktlen);
+#endif /* CONFIG_MCC_MODE*/
+
+#ifdef CONFIG_WFD
+			len = rtw_append_beacon_wfd_ie(padapter, pframe);
+			pframe += len;
+			pattrib->pktlen += len;
+#endif
+		}
+#endif /* CONFIG_P2P */
+#ifdef CONFIG_RTW_REPEATER_SON
+		rtw_rson_append_ie(padapter, pframe, &pattrib->pktlen);
+#endif
+#ifdef CONFIG_APPEND_VENDOR_IE_ENABLE
+		pattrib->pktlen += rtw_build_vendor_ie(padapter , pframe , WIFI_BEACON_VENDOR_IE_BIT);
+#endif
+		goto _issue_bcn;
+
+	}
+
+	/* below for ad-hoc mode */
+
+	/* timestamp will be inserted by hardware */
+	pframe += 8;
+	pattrib->pktlen += 8;
+
+	/* beacon interval: 2 bytes */
+
+	_rtw_memcpy(pframe, (unsigned char *)(rtw_get_beacon_interval_from_ie(cur_network->IEs)), 2);
+
+	pframe += 2;
+	pattrib->pktlen += 2;
+
+	/* capability info: 2 bytes */
+
+	_rtw_memcpy(pframe, (unsigned char *)(rtw_get_capability_from_ie(cur_network->IEs)), 2);
+
+	pframe += 2;
+	pattrib->pktlen += 2;
+
+	/* SSID */
+	pframe = rtw_set_ie(pframe, _SSID_IE_, cur_network->Ssid.SsidLength, cur_network->Ssid.Ssid, &pattrib->pktlen);
+
+	/* supported rates... */
+	rate_len = rtw_get_rateset_len(cur_network->SupportedRates);
+	pframe = rtw_set_ie(pframe, _SUPPORTEDRATES_IE_, ((rate_len > 8) ? 8 : rate_len), cur_network->SupportedRates, &pattrib->pktlen);
+
+	/* DS parameter set */
+	pframe = rtw_set_ie(pframe, _DSSET_IE_, 1, (unsigned char *)&(cur_network->Configuration.DSConfig), &pattrib->pktlen);
+
+	/* if( (pmlmeinfo->state&0x03) == WIFI_FW_ADHOC_STATE) */
+	{
+		u8 erpinfo = 0;
+		u32 ATIMWindow;
+		/* IBSS Parameter Set... */
+		/* ATIMWindow = cur->Configuration.ATIMWindow; */
+		ATIMWindow = 0;
+		pframe = rtw_set_ie(pframe, _IBSS_PARA_IE_, 2, (unsigned char *)(&ATIMWindow), &pattrib->pktlen);
+
+		/* ERP IE */
+		pframe = rtw_set_ie(pframe, _ERPINFO_IE_, 1, &erpinfo, &pattrib->pktlen);
+	}
+
+
+	/* EXTERNDED SUPPORTED RATE */
+	if (rate_len > 8)
+		pframe = rtw_set_ie(pframe, _EXT_SUPPORTEDRATES_IE_, (rate_len - 8), (cur_network->SupportedRates + 8), &pattrib->pktlen);
+
+
+	/* todo:HT for adhoc */
+
+_issue_bcn:
+
+#if defined(CONFIG_AP_MODE) && defined (CONFIG_NATIVEAP_MLME)
+	pmlmepriv->update_bcn = _FALSE;
+
+	_exit_critical_bh(&pmlmepriv->bcn_update_lock, &irqL);
+#endif /* #if defined (CONFIG_AP_MODE) && defined (CONFIG_NATIVEAP_MLME) */
+
+	if ((pattrib->pktlen + TXDESC_SIZE) > MAX_BEACON_LEN) {
+		RTW_ERR("beacon frame too large ,len(%d,%d)\n",
+			(pattrib->pktlen + TXDESC_SIZE), MAX_BEACON_LEN);
+		rtw_warn_on(1);
+		return;
+	}
+
+	pattrib->last_txcmdsz = pattrib->pktlen;
+
+	/* RTW_INFO("issue bcn_sz=%d\n", pattrib->last_txcmdsz); */
+	if (timeout_ms > 0)
+		dump_mgntframe_and_wait(padapter, pmgntframe, timeout_ms);
+	else
+		dump_mgntframe(padapter, pmgntframe);
+
+}
+
+void issue_probersp(_adapter *padapter, unsigned char *da, u8 is_valid_p2p_probereq)
+{
+	struct xmit_frame			*pmgntframe;
+	struct pkt_attrib			*pattrib;
+	unsigned char					*pframe;
+	struct rtw_ieee80211_hdr	*pwlanhdr;
+	unsigned short				*fctrl;
+	unsigned char					*mac, *bssid;
+	struct xmit_priv	*pxmitpriv = &(padapter->xmitpriv);
+#if defined(CONFIG_AP_MODE) && defined (CONFIG_NATIVEAP_MLME)
+	u8 *pwps_ie;
+	uint wps_ielen;
+	struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
+#endif /* #if defined (CONFIG_AP_MODE) && defined (CONFIG_NATIVEAP_MLME) */
+	struct mlme_ext_priv	*pmlmeext = &(padapter->mlmeextpriv);
+	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
+	WLAN_BSSID_EX		*cur_network = &(pmlmeinfo->network);
+	unsigned int	rate_len;
+#ifdef CONFIG_P2P
+	struct wifidirect_info	*pwdinfo = &(padapter->wdinfo);
+#endif /* CONFIG_P2P */
+
+	/* RTW_INFO("%s\n", __FUNCTION__); */
+
+	if (da == NULL)
+		return;
+
+	if (rtw_rfctl_is_tx_blocked_by_ch_waiting(adapter_to_rfctl(padapter)))
+		return;
+
+	pmgntframe = alloc_mgtxmitframe(pxmitpriv);
+	if (pmgntframe == NULL) {
+		RTW_INFO("%s, alloc mgnt frame fail\n", __FUNCTION__);
+		return;
+	}
+
+
+	/* update attribute */
+	pattrib = &pmgntframe->attrib;
+	update_mgntframe_attrib(padapter, pattrib);
+
+	_rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET);
+
+	pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET;
+	pwlanhdr = (struct rtw_ieee80211_hdr *)pframe;
+
+	mac = adapter_mac_addr(padapter);
+	bssid = cur_network->MacAddress;
+
+	fctrl = &(pwlanhdr->frame_ctl);
+	*(fctrl) = 0;
+	_rtw_memcpy(pwlanhdr->addr1, da, ETH_ALEN);
+	_rtw_memcpy(pwlanhdr->addr2, mac, ETH_ALEN);
+	_rtw_memcpy(pwlanhdr->addr3, bssid, ETH_ALEN);
+
+	SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq);
+	pmlmeext->mgnt_seq++;
+	set_frame_sub_type(fctrl, WIFI_PROBERSP);
+
+	pattrib->hdrlen = sizeof(struct rtw_ieee80211_hdr_3addr);
+	pattrib->pktlen = pattrib->hdrlen;
+	pframe += pattrib->hdrlen;
+
+
+	if (cur_network->IELength > MAX_IE_SZ)
+		return;
+
+#if defined(CONFIG_AP_MODE) && defined (CONFIG_NATIVEAP_MLME)
+	if ((pmlmeinfo->state & 0x03) == WIFI_FW_AP_STATE) {
+		pwps_ie = rtw_get_wps_ie(cur_network->IEs + _FIXED_IE_LENGTH_, cur_network->IELength - _FIXED_IE_LENGTH_, NULL, &wps_ielen);
+
+		/* inerset & update wps_probe_resp_ie */
+		if ((pmlmepriv->wps_probe_resp_ie != NULL) && pwps_ie && (wps_ielen > 0)) {
+			uint wps_offset, remainder_ielen;
+			u8 *premainder_ie;
+
+			wps_offset = (uint)(pwps_ie - cur_network->IEs);
+
+			premainder_ie = pwps_ie + wps_ielen;
+
+			remainder_ielen = cur_network->IELength - wps_offset - wps_ielen;
+
+			_rtw_memcpy(pframe, cur_network->IEs, wps_offset);
+			pframe += wps_offset;
+			pattrib->pktlen += wps_offset;
+
+			wps_ielen = (uint)pmlmepriv->wps_probe_resp_ie[1];/* to get ie data len */
+			if ((wps_offset + wps_ielen + 2) <= MAX_IE_SZ) {
+				_rtw_memcpy(pframe, pmlmepriv->wps_probe_resp_ie, wps_ielen + 2);
+				pframe += wps_ielen + 2;
+				pattrib->pktlen += wps_ielen + 2;
+			}
+
+			if ((wps_offset + wps_ielen + 2 + remainder_ielen) <= MAX_IE_SZ) {
+				_rtw_memcpy(pframe, premainder_ie, remainder_ielen);
+				pframe += remainder_ielen;
+				pattrib->pktlen += remainder_ielen;
+			}
+		} else {
+			_rtw_memcpy(pframe, cur_network->IEs, cur_network->IELength);
+			pframe += cur_network->IELength;
+			pattrib->pktlen += cur_network->IELength;
+		}
+
+		/* retrieve SSID IE from cur_network->Ssid */
+		{
+			u8 *ssid_ie;
+			sint ssid_ielen;
+			sint ssid_ielen_diff;
+			u8 buf[MAX_IE_SZ];
+			u8 *ies = pmgntframe->buf_addr + TXDESC_OFFSET + sizeof(struct rtw_ieee80211_hdr_3addr);
+
+			ssid_ie = rtw_get_ie(ies + _FIXED_IE_LENGTH_, _SSID_IE_, &ssid_ielen,
+				     (pframe - ies) - _FIXED_IE_LENGTH_);
+
+			ssid_ielen_diff = cur_network->Ssid.SsidLength - ssid_ielen;
+
+			if (ssid_ie &&  cur_network->Ssid.SsidLength) {
+				uint remainder_ielen;
+				u8 *remainder_ie;
+				remainder_ie = ssid_ie + 2;
+				remainder_ielen = (pframe - remainder_ie);
+
+				if (remainder_ielen > MAX_IE_SZ) {
+					RTW_WARN(FUNC_ADPT_FMT" remainder_ielen > MAX_IE_SZ\n", FUNC_ADPT_ARG(padapter));
+					remainder_ielen = MAX_IE_SZ;
+				}
+
+				_rtw_memcpy(buf, remainder_ie, remainder_ielen);
+				_rtw_memcpy(remainder_ie + ssid_ielen_diff, buf, remainder_ielen);
+				*(ssid_ie + 1) = cur_network->Ssid.SsidLength;
+				_rtw_memcpy(ssid_ie + 2, cur_network->Ssid.Ssid, cur_network->Ssid.SsidLength);
+
+				pframe += ssid_ielen_diff;
+				pattrib->pktlen += ssid_ielen_diff;
+			}
+		}
+#ifdef CONFIG_RTW_REPEATER_SON
+		rtw_rson_append_ie(padapter, pframe, &pattrib->pktlen);
+#endif
+#ifdef CONFIG_APPEND_VENDOR_IE_ENABLE
+		pattrib->pktlen += rtw_build_vendor_ie(padapter , pframe , WIFI_PROBERESP_VENDOR_IE_BIT);
+#endif
+	} else
+#endif
+	{
+
+		/* timestamp will be inserted by hardware */
+		pframe += 8;
+		pattrib->pktlen += 8;
+
+		/* beacon interval: 2 bytes */
+
+		_rtw_memcpy(pframe, (unsigned char *)(rtw_get_beacon_interval_from_ie(cur_network->IEs)), 2);
+
+		pframe += 2;
+		pattrib->pktlen += 2;
+
+		/* capability info: 2 bytes */
+
+		_rtw_memcpy(pframe, (unsigned char *)(rtw_get_capability_from_ie(cur_network->IEs)), 2);
+
+		pframe += 2;
+		pattrib->pktlen += 2;
+
+		/* below for ad-hoc mode */
+
+		/* SSID */
+		pframe = rtw_set_ie(pframe, _SSID_IE_, cur_network->Ssid.SsidLength, cur_network->Ssid.Ssid, &pattrib->pktlen);
+
+		/* supported rates... */
+		rate_len = rtw_get_rateset_len(cur_network->SupportedRates);
+		pframe = rtw_set_ie(pframe, _SUPPORTEDRATES_IE_, ((rate_len > 8) ? 8 : rate_len), cur_network->SupportedRates, &pattrib->pktlen);
+
+		/* DS parameter set */
+		pframe = rtw_set_ie(pframe, _DSSET_IE_, 1, (unsigned char *)&(cur_network->Configuration.DSConfig), &pattrib->pktlen);
+
+		if ((pmlmeinfo->state & 0x03) == WIFI_FW_ADHOC_STATE) {
+			u8 erpinfo = 0;
+			u32 ATIMWindow;
+			/* IBSS Parameter Set... */
+			/* ATIMWindow = cur->Configuration.ATIMWindow; */
+			ATIMWindow = 0;
+			pframe = rtw_set_ie(pframe, _IBSS_PARA_IE_, 2, (unsigned char *)(&ATIMWindow), &pattrib->pktlen);
+
+			/* ERP IE */
+			pframe = rtw_set_ie(pframe, _ERPINFO_IE_, 1, &erpinfo, &pattrib->pktlen);
+		}
+
+
+		/* EXTERNDED SUPPORTED RATE */
+		if (rate_len > 8)
+			pframe = rtw_set_ie(pframe, _EXT_SUPPORTEDRATES_IE_, (rate_len - 8), (cur_network->SupportedRates + 8), &pattrib->pktlen);
+
+
+		/* todo:HT for adhoc */
+
+	}
+
+#ifdef CONFIG_RTW_80211K
+	pframe = rtw_set_ie(pframe, _EID_RRM_EN_CAP_IE_,
+		sizeof(padapter->rmpriv.rm_en_cap_def),
+		padapter->rmpriv.rm_en_cap_def, &pattrib->pktlen);
+#endif
+
+#ifdef CONFIG_P2P
+	if (rtw_p2p_chk_role(pwdinfo, P2P_ROLE_GO)
+	    /* IOT issue, When wifi_spec is not set, send probe_resp with P2P IE even if probe_req has no P2P IE */
+	    && (is_valid_p2p_probereq || !padapter->registrypriv.wifi_spec)) {
+		u32 len;
+#ifdef CONFIG_IOCTL_CFG80211
+		if (adapter_wdev_data(padapter)->p2p_enabled && pwdinfo->driver_interface == DRIVER_CFG80211) {
+			/* if pwdinfo->role == P2P_ROLE_DEVICE will call issue_probersp_p2p() */
+			len = pmlmepriv->p2p_go_probe_resp_ie_len;
+			if (pmlmepriv->p2p_go_probe_resp_ie && len > 0)
+				_rtw_memcpy(pframe, pmlmepriv->p2p_go_probe_resp_ie, len);
+		} else
+#endif /* CONFIG_IOCTL_CFG80211 */
+		{
+			len = build_probe_resp_p2p_ie(pwdinfo, pframe);
+		}
+
+		pframe += len;
+		pattrib->pktlen += len;
+
+#ifdef CONFIG_MCC_MODE
+		pframe = rtw_hal_mcc_append_go_p2p_ie(padapter, pframe, &pattrib->pktlen);
+#endif /* CONFIG_MCC_MODE*/
+
+#ifdef CONFIG_WFD
+		len = rtw_append_probe_resp_wfd_ie(padapter, pframe);
+		pframe += len;
+		pattrib->pktlen += len;
+#endif
+	}
+#endif /* CONFIG_P2P */
+
+
+#ifdef CONFIG_AUTO_AP_MODE
+	{
+		struct sta_info	*psta;
+		struct sta_priv *pstapriv = &padapter->stapriv;
+
+		RTW_INFO("(%s)\n", __FUNCTION__);
+
+		/* check rc station */
+		psta = rtw_get_stainfo(pstapriv, da);
+		if (psta && psta->isrc && psta->pid > 0) {
+			u8 RC_OUI[4] = {0x00, 0xE0, 0x4C, 0x0A};
+			u8 RC_INFO[14] = {0};
+			/* EID[1] + EID_LEN[1] + RC_OUI[4] + MAC[6] + PairingID[2] + ChannelNum[2] */
+			u16 cu_ch = (u16)cur_network->Configuration.DSConfig;
+
+			RTW_INFO("%s, reply rc(pid=0x%x) device "MAC_FMT" in ch=%d\n", __FUNCTION__,
+				 psta->pid, MAC_ARG(psta->cmn.mac_addr), cu_ch);
+
+			/* append vendor specific ie */
+			_rtw_memcpy(RC_INFO, RC_OUI, sizeof(RC_OUI));
+			_rtw_memcpy(&RC_INFO[4], mac, ETH_ALEN);
+			_rtw_memcpy(&RC_INFO[10], (u8 *)&psta->pid, 2);
+			_rtw_memcpy(&RC_INFO[12], (u8 *)&cu_ch, 2);
+
+			pframe = rtw_set_ie(pframe, _VENDOR_SPECIFIC_IE_, sizeof(RC_INFO), RC_INFO, &pattrib->pktlen);
+		}
+	}
+#endif /* CONFIG_AUTO_AP_MODE */
+
+
+	pattrib->last_txcmdsz = pattrib->pktlen;
+
+
+	dump_mgntframe(padapter, pmgntframe);
+
+	return;
+
+}
+
+int _issue_probereq(_adapter *padapter, const NDIS_802_11_SSID *pssid, const u8 *da, u8 ch, bool append_wps, int wait_ack)
+{
+	int ret = _FAIL;
+	struct xmit_frame		*pmgntframe;
+	struct pkt_attrib		*pattrib;
+	unsigned char			*pframe;
+	struct rtw_ieee80211_hdr	*pwlanhdr;
+	unsigned short		*fctrl;
+	unsigned char			*mac;
+	unsigned char			bssrate[NumRates];
+	struct xmit_priv		*pxmitpriv = &(padapter->xmitpriv);
+	struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
+	struct mlme_ext_priv	*pmlmeext = &(padapter->mlmeextpriv);
+	int	bssrate_len = 0;
+	u8	bc_addr[] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
+#ifdef CONFIG_RTW_CFGVENDOR_RANDOM_MAC_OUI
+	struct rtw_wdev_priv *pwdev_priv = adapter_wdev_data(padapter);
+#endif
+
+	if (rtw_rfctl_is_tx_blocked_by_ch_waiting(adapter_to_rfctl(padapter)))
+		goto exit;
+
+	pmgntframe = alloc_mgtxmitframe(pxmitpriv);
+	if (pmgntframe == NULL)
+		goto exit;
+
+	/* update attribute */
+	pattrib = &pmgntframe->attrib;
+	update_mgntframe_attrib(padapter, pattrib);
+
+
+	_rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET);
+
+	pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET;
+	pwlanhdr = (struct rtw_ieee80211_hdr *)pframe;
+
+#ifdef CONFIG_RTW_CFGVENDOR_RANDOM_MAC_OUI
+	if ((pwdev_priv->pno_mac_addr[0] != 0xFF)
+	    && (check_fwstate(&padapter->mlmepriv, WIFI_STATION_STATE) == _TRUE)
+	    && (check_fwstate(&padapter->mlmepriv, _FW_LINKED) == _FALSE))
+		mac = pwdev_priv->pno_mac_addr;
+	else
+#endif
+	mac = adapter_mac_addr(padapter);
+
+	fctrl = &(pwlanhdr->frame_ctl);
+	*(fctrl) = 0;
+
+	if (da) {
+		/*	unicast probe request frame */
+		_rtw_memcpy(pwlanhdr->addr1, da, ETH_ALEN);
+		_rtw_memcpy(pwlanhdr->addr3, da, ETH_ALEN);
+	} else {
+		/*	broadcast probe request frame */
+		_rtw_memcpy(pwlanhdr->addr1, bc_addr, ETH_ALEN);
+		_rtw_memcpy(pwlanhdr->addr3, bc_addr, ETH_ALEN);
+	}
+
+	_rtw_memcpy(pwlanhdr->addr2, mac, ETH_ALEN);
+
+#ifdef CONFIG_RTW_CFGVENDOR_RANDOM_MAC_OUI
+	if ((pwdev_priv->pno_mac_addr[0] != 0xFF)
+	    && (check_fwstate(&padapter->mlmepriv, WIFI_STATION_STATE) == _TRUE)
+	    && (check_fwstate(&padapter->mlmepriv, _FW_LINKED) == _FALSE)) {
+#ifdef CONFIG_RTW_DEBUG
+		RTW_DBG("%s pno_scan_seq_num: %d\n", __func__,
+			 pwdev_priv->pno_scan_seq_num);
+#endif
+		SetSeqNum(pwlanhdr, pwdev_priv->pno_scan_seq_num);
+		pattrib->seqnum = pwdev_priv->pno_scan_seq_num;
+		pattrib->qos_en = 1;
+		pwdev_priv->pno_scan_seq_num++;
+	} else
+#endif
+	{
+		SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq);
+		pmlmeext->mgnt_seq++;
+	}
+	set_frame_sub_type(pframe, WIFI_PROBEREQ);
+
+	pframe += sizeof(struct rtw_ieee80211_hdr_3addr);
+	pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr);
+
+	if (pssid && !MLME_IS_MESH(padapter))
+		pframe = rtw_set_ie(pframe, _SSID_IE_, pssid->SsidLength, pssid->Ssid, &(pattrib->pktlen));
+	else
+		pframe = rtw_set_ie(pframe, _SSID_IE_, 0, NULL, &(pattrib->pktlen));
+
+	get_rate_set(padapter, bssrate, &bssrate_len);
+
+	if (bssrate_len > 8) {
+		pframe = rtw_set_ie(pframe, _SUPPORTEDRATES_IE_ , 8, bssrate, &(pattrib->pktlen));
+		pframe = rtw_set_ie(pframe, _EXT_SUPPORTEDRATES_IE_ , (bssrate_len - 8), (bssrate + 8), &(pattrib->pktlen));
+	} else
+		pframe = rtw_set_ie(pframe, _SUPPORTEDRATES_IE_ , bssrate_len , bssrate, &(pattrib->pktlen));
+
+	if (ch)
+		pframe = rtw_set_ie(pframe, _DSSET_IE_, 1, &ch, &pattrib->pktlen);
+
+#ifdef CONFIG_RTW_MESH
+	if (MLME_IS_MESH(padapter)) {
+		if (pssid)
+			pframe = rtw_set_ie_mesh_id(pframe, &pattrib->pktlen, pssid->Ssid, pssid->SsidLength);
+		else
+			pframe = rtw_set_ie_mesh_id(pframe, &pattrib->pktlen, NULL, 0);
+	}
+#endif
+
+	if (append_wps) {
+		/* add wps_ie for wps2.0 */
+		if (pmlmepriv->wps_probe_req_ie_len > 0 && pmlmepriv->wps_probe_req_ie) {
+			_rtw_memcpy(pframe, pmlmepriv->wps_probe_req_ie, pmlmepriv->wps_probe_req_ie_len);
+			pframe += pmlmepriv->wps_probe_req_ie_len;
+			pattrib->pktlen += pmlmepriv->wps_probe_req_ie_len;
+			/* pmlmepriv->wps_probe_req_ie_len = 0 ; */ /* reset to zero */
+		}
+	}
+#ifdef CONFIG_APPEND_VENDOR_IE_ENABLE
+	pattrib->pktlen += rtw_build_vendor_ie(padapter , pframe , WIFI_PROBEREQ_VENDOR_IE_BIT);
+#endif
+
+	pattrib->last_txcmdsz = pattrib->pktlen;
+
+
+	if (wait_ack)
+		ret = dump_mgntframe_and_wait_ack(padapter, pmgntframe);
+	else {
+		dump_mgntframe(padapter, pmgntframe);
+		ret = _SUCCESS;
+	}
+
+exit:
+	return ret;
+}
+
+inline void issue_probereq(_adapter *padapter, const NDIS_802_11_SSID *pssid, const u8 *da)
+{
+	_issue_probereq(padapter, pssid, da, 0, 1, _FALSE);
+}
+
+/*
+ * wait_ms == 0 means that there is no need to wait ack through C2H_CCX_TX_RPT
+ * wait_ms > 0 means you want to wait ack through C2H_CCX_TX_RPT, and the value of wait_ms means the interval between each TX
+ * try_cnt means the maximal TX count to try
+ */
+int issue_probereq_ex(_adapter *padapter, const NDIS_802_11_SSID *pssid, const u8 *da, u8 ch, bool append_wps,
+		      int try_cnt, int wait_ms)
+{
+	int ret = _FAIL;
+	int i = 0;
+	systime start = rtw_get_current_time();
+
+	if (rtw_rfctl_is_tx_blocked_by_ch_waiting(adapter_to_rfctl(padapter)))
+		goto exit;
+
+	do {
+		ret = _issue_probereq(padapter, pssid, da, ch, append_wps, wait_ms > 0 ? _TRUE : _FALSE);
+
+		i++;
+
+		if (RTW_CANNOT_RUN(padapter))
+			break;
+
+		if (i < try_cnt && wait_ms > 0 && ret == _FAIL)
+			rtw_msleep_os(wait_ms);
+
+	} while ((i < try_cnt) && ((ret == _FAIL) || (wait_ms == 0)));
+
+	if (ret != _FAIL) {
+		ret = _SUCCESS;
+#ifndef DBG_XMIT_ACK
+		goto exit;
+#endif
+	}
+
+	if (try_cnt && wait_ms) {
+		if (da)
+			RTW_INFO(FUNC_ADPT_FMT" to "MAC_FMT", ch:%u%s, %d/%d in %u ms\n",
+				FUNC_ADPT_ARG(padapter), MAC_ARG(da), rtw_get_oper_ch(padapter),
+				ret == _SUCCESS ? ", acked" : "", i, try_cnt, rtw_get_passing_time_ms(start));
+		else
+			RTW_INFO(FUNC_ADPT_FMT", ch:%u%s, %d/%d in %u ms\n",
+				FUNC_ADPT_ARG(padapter), rtw_get_oper_ch(padapter),
+				ret == _SUCCESS ? ", acked" : "", i, try_cnt, rtw_get_passing_time_ms(start));
+	}
+exit:
+	return ret;
+}
+
+/* if psta == NULL, indiate we are station(client) now... */
+void issue_auth(_adapter *padapter, struct sta_info *psta, unsigned short status)
+{
+	struct xmit_frame			*pmgntframe;
+	struct pkt_attrib			*pattrib;
+	unsigned char					*pframe;
+	struct rtw_ieee80211_hdr	*pwlanhdr;
+	unsigned short				*fctrl;
+	unsigned int					val32;
+	unsigned short				val16;
+	int use_shared_key = 0;
+	struct xmit_priv			*pxmitpriv = &(padapter->xmitpriv);
+	struct mlme_ext_priv	*pmlmeext = &(padapter->mlmeextpriv);
+	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
+
+	if (rtw_rfctl_is_tx_blocked_by_ch_waiting(adapter_to_rfctl(padapter)))
+		return;
+
+	pmgntframe = alloc_mgtxmitframe(pxmitpriv);
+	if (pmgntframe == NULL)
+		return;
+
+	/* update attribute */
+	pattrib = &pmgntframe->attrib;
+	update_mgntframe_attrib(padapter, pattrib);
+
+	_rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET);
+
+	pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET;
+	pwlanhdr = (struct rtw_ieee80211_hdr *)pframe;
+
+	fctrl = &(pwlanhdr->frame_ctl);
+	*(fctrl) = 0;
+
+	SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq);
+	pmlmeext->mgnt_seq++;
+	set_frame_sub_type(pframe, WIFI_AUTH);
+
+	pframe += sizeof(struct rtw_ieee80211_hdr_3addr);
+	pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr);
+
+
+	if (psta) { /* for AP mode */
+#ifdef CONFIG_NATIVEAP_MLME
+
+		_rtw_memcpy(pwlanhdr->addr1, psta->cmn.mac_addr, ETH_ALEN);
+		_rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN);
+		_rtw_memcpy(pwlanhdr->addr3, adapter_mac_addr(padapter), ETH_ALEN);
+
+
+		/* setting auth algo number */
+		val16 = (u16)psta->authalg;
+
+		if (status != _STATS_SUCCESSFUL_)
+			val16 = 0;
+
+		if (val16)	{
+			val16 = cpu_to_le16(val16);
+			use_shared_key = 1;
+		}
+
+		pframe = rtw_set_fixed_ie(pframe, _AUTH_ALGM_NUM_, (unsigned char *)&val16, &(pattrib->pktlen));
+
+		/* setting auth seq number */
+		val16 = (u16)psta->auth_seq;
+		val16 = cpu_to_le16(val16);
+		pframe = rtw_set_fixed_ie(pframe, _AUTH_SEQ_NUM_, (unsigned char *)&val16, &(pattrib->pktlen));
+
+		/* setting status code... */
+		val16 = status;
+		val16 = cpu_to_le16(val16);
+		pframe = rtw_set_fixed_ie(pframe, _STATUS_CODE_, (unsigned char *)&val16, &(pattrib->pktlen));
+
+		/* added challenging text... */
+		if ((psta->auth_seq == 2) && (psta->state & WIFI_FW_AUTH_STATE) && (use_shared_key == 1))
+			pframe = rtw_set_ie(pframe, _CHLGETXT_IE_, 128, psta->chg_txt, &(pattrib->pktlen));
+#endif
+	} else {
+		_rtw_memcpy(pwlanhdr->addr1, get_my_bssid(&pmlmeinfo->network), ETH_ALEN);
+		_rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN);
+		_rtw_memcpy(pwlanhdr->addr3, get_my_bssid(&pmlmeinfo->network), ETH_ALEN);
+
+#ifdef CONFIG_RTW_80211R
+		if (rtw_ft_roam(padapter)) {
+			/* 2: 802.11R FTAA */
+			val16 = cpu_to_le16(2);
+		} else
+#endif
+		{
+			/* setting auth algo number */
+			val16 = (pmlmeinfo->auth_algo == dot11AuthAlgrthm_Shared) ? 1 : 0;	/* 0:OPEN System, 1:Shared key */
+			if (val16) {
+				val16 = cpu_to_le16(val16);
+				use_shared_key = 1;
+			}
+		}
+
+		/* RTW_INFO("%s auth_algo= %s auth_seq=%d\n",__FUNCTION__,(pmlmeinfo->auth_algo==0)?"OPEN":"SHARED",pmlmeinfo->auth_seq); */
+
+		/* setting IV for auth seq #3 */
+		if ((pmlmeinfo->auth_seq == 3) && (pmlmeinfo->state & WIFI_FW_AUTH_STATE) && (use_shared_key == 1)) {
+			/* RTW_INFO("==> iv(%d),key_index(%d)\n",pmlmeinfo->iv,pmlmeinfo->key_index); */
+			val32 = ((pmlmeinfo->iv++) | (pmlmeinfo->key_index << 30));
+			val32 = cpu_to_le32(val32);
+			pframe = rtw_set_fixed_ie(pframe, 4, (unsigned char *)&val32, &(pattrib->pktlen));
+
+			pattrib->iv_len = 4;
+		}
+
+		pframe = rtw_set_fixed_ie(pframe, _AUTH_ALGM_NUM_, (unsigned char *)&val16, &(pattrib->pktlen));
+
+		/* setting auth seq number */
+		val16 = pmlmeinfo->auth_seq;
+		val16 = cpu_to_le16(val16);
+		pframe = rtw_set_fixed_ie(pframe, _AUTH_SEQ_NUM_, (unsigned char *)&val16, &(pattrib->pktlen));
+
+
+		/* setting status code... */
+		val16 = status;
+		val16 = cpu_to_le16(val16);
+		pframe = rtw_set_fixed_ie(pframe, _STATUS_CODE_, (unsigned char *)&val16, &(pattrib->pktlen));
+
+#ifdef CONFIG_RTW_80211R
+		rtw_ft_build_auth_req_ies(padapter, pattrib, &pframe);
+#endif
+
+		/* then checking to see if sending challenging text... */
+		if ((pmlmeinfo->auth_seq == 3) && (pmlmeinfo->state & WIFI_FW_AUTH_STATE) && (use_shared_key == 1)) {
+			pframe = rtw_set_ie(pframe, _CHLGETXT_IE_, 128, pmlmeinfo->chg_txt, &(pattrib->pktlen));
+
+			SetPrivacy(fctrl);
+
+			pattrib->hdrlen = sizeof(struct rtw_ieee80211_hdr_3addr);
+
+			pattrib->encrypt = _WEP40_;
+
+			pattrib->icv_len = 4;
+
+			pattrib->pktlen += pattrib->icv_len;
+
+		}
+
+	}
+
+	pattrib->last_txcmdsz = pattrib->pktlen;
+
+	rtw_wep_encrypt(padapter, (u8 *)pmgntframe);
+	RTW_INFO("%s\n", __FUNCTION__);
+	dump_mgntframe(padapter, pmgntframe);
+
+	return;
+}
+
+
+void issue_asocrsp(_adapter *padapter, unsigned short status, struct sta_info *pstat, int pkt_type)
+{
+#ifdef CONFIG_AP_MODE
+	struct xmit_frame	*pmgntframe;
+	struct rtw_ieee80211_hdr	*pwlanhdr;
+	struct pkt_attrib *pattrib;
+	unsigned char	*pbuf, *pframe;
+	unsigned short val, ie_status;
+	unsigned short *fctrl;
+	struct xmit_priv *pxmitpriv = &(padapter->xmitpriv);
+	struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
+	struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
+	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
+	WLAN_BSSID_EX *pnetwork = &(pmlmeinfo->network);
+	u8 *ie = pnetwork->IEs;
+#ifdef CONFIG_P2P
+	struct wifidirect_info	*pwdinfo = &(padapter->wdinfo);
+#ifdef CONFIG_WFD
+	u32					wfdielen = 0;
+#endif
+
+#endif /* CONFIG_P2P */
+
+	if (rtw_rfctl_is_tx_blocked_by_ch_waiting(adapter_to_rfctl(padapter)))
+		return;
+
+	RTW_INFO("%s\n", __FUNCTION__);
+
+	pmgntframe = alloc_mgtxmitframe(pxmitpriv);
+	if (pmgntframe == NULL)
+		return;
+
+	/* update attribute */
+	pattrib = &pmgntframe->attrib;
+	update_mgntframe_attrib(padapter, pattrib);
+
+
+	_rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET);
+
+	pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET;
+	pwlanhdr = (struct rtw_ieee80211_hdr *)pframe;
+
+	fctrl = &(pwlanhdr->frame_ctl);
+	*(fctrl) = 0;
+
+	_rtw_memcpy((void *)GetAddr1Ptr(pwlanhdr), pstat->cmn.mac_addr, ETH_ALEN);
+	_rtw_memcpy((void *)get_addr2_ptr(pwlanhdr), adapter_mac_addr(padapter), ETH_ALEN);
+	_rtw_memcpy((void *)GetAddr3Ptr(pwlanhdr), get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN);
+
+
+	SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq);
+	pmlmeext->mgnt_seq++;
+	if ((pkt_type == WIFI_ASSOCRSP) || (pkt_type == WIFI_REASSOCRSP))
+		set_frame_sub_type(pwlanhdr, pkt_type);
+	else
+		return;
+
+	pattrib->hdrlen = sizeof(struct rtw_ieee80211_hdr_3addr);
+	pattrib->pktlen += pattrib->hdrlen;
+	pframe += pattrib->hdrlen;
+
+	/* capability */
+	val = *(unsigned short *)rtw_get_capability_from_ie(ie);
+
+	pframe = rtw_set_fixed_ie(pframe, _CAPABILITY_ , (unsigned char *)&val, &(pattrib->pktlen));
+
+	ie_status = cpu_to_le16(status);
+	pframe = rtw_set_fixed_ie(pframe , _STATUS_CODE_ , (unsigned char *)&ie_status, &(pattrib->pktlen));
+
+	val = cpu_to_le16(pstat->cmn.aid | BIT(14) | BIT(15));
+	pframe = rtw_set_fixed_ie(pframe, _ASOC_ID_ , (unsigned char *)&val, &(pattrib->pktlen));
+
+	if (pstat->bssratelen <= 8)
+		pframe = rtw_set_ie(pframe, _SUPPORTEDRATES_IE_, pstat->bssratelen, pstat->bssrateset, &(pattrib->pktlen));
+	else {
+		pframe = rtw_set_ie(pframe, _SUPPORTEDRATES_IE_, 8, pstat->bssrateset, &(pattrib->pktlen));
+		pframe = rtw_set_ie(pframe, _EXT_SUPPORTEDRATES_IE_, (pstat->bssratelen - 8), pstat->bssrateset + 8, &(pattrib->pktlen));
+	}
+
+#ifdef CONFIG_IEEE80211W
+	if (status == _STATS_REFUSED_TEMPORARILY_) {
+		u8 timeout_itvl[5];
+		u32 timeout_interval = 3000;
+		/* Association Comeback time */
+		timeout_itvl[0] = 0x03;
+		timeout_interval = cpu_to_le32(timeout_interval);
+		_rtw_memcpy(timeout_itvl + 1, &timeout_interval, 4);
+		pframe = rtw_set_ie(pframe, _TIMEOUT_ITVL_IE_, 5, timeout_itvl, &(pattrib->pktlen));
+	}
+#endif /* CONFIG_IEEE80211W */
+
+#ifdef CONFIG_80211N_HT
+	if ((pstat->flags & WLAN_STA_HT) && (pmlmepriv->htpriv.ht_option)) {
+		uint ie_len = 0;
+
+		/* FILL HT CAP INFO IE */
+		/* p = hostapd_eid_ht_capabilities_info(hapd, p); */
+		pbuf = rtw_get_ie(ie + _BEACON_IE_OFFSET_, _HT_CAPABILITY_IE_, &ie_len, (pnetwork->IELength - _BEACON_IE_OFFSET_));
+		if (pbuf && ie_len > 0) {
+			_rtw_memcpy(pframe, pbuf, ie_len + 2);
+			pframe += (ie_len + 2);
+			pattrib->pktlen += (ie_len + 2);
+		}
+
+		/* FILL HT ADD INFO IE */
+		/* p = hostapd_eid_ht_operation(hapd, p); */
+		pbuf = rtw_get_ie(ie + _BEACON_IE_OFFSET_, _HT_ADD_INFO_IE_, &ie_len, (pnetwork->IELength - _BEACON_IE_OFFSET_));
+		if (pbuf && ie_len > 0) {
+			_rtw_memcpy(pframe, pbuf, ie_len + 2);
+			pframe += (ie_len + 2);
+			pattrib->pktlen += (ie_len + 2);
+		}
+
+	}
+#endif
+
+	/*adding EXT_CAPAB_IE */
+	if (pmlmepriv->ext_capab_ie_len > 0) {
+		uint ie_len = 0;
+
+		pbuf = rtw_get_ie(ie + _BEACON_IE_OFFSET_, _EXT_CAP_IE_, &ie_len, (pnetwork->IELength - _BEACON_IE_OFFSET_));
+		if (pbuf && ie_len > 0) {
+			_rtw_memcpy(pframe, pbuf, ie_len + 2);
+			pframe += (ie_len + 2);
+			pattrib->pktlen += (ie_len + 2);
+		}
+	}
+
+#ifdef CONFIG_80211AC_VHT
+	if ((pstat->flags & WLAN_STA_VHT) && (pmlmepriv->vhtpriv.vht_option)
+	    && (pstat->wpa_pairwise_cipher != WPA_CIPHER_TKIP)
+	    && (pstat->wpa2_pairwise_cipher != WPA_CIPHER_TKIP)) {
+		u32 ie_len = 0;
+
+		/* FILL VHT CAP IE */
+		pbuf = rtw_get_ie(ie + _BEACON_IE_OFFSET_, EID_VHTCapability, &ie_len, (pnetwork->IELength - _BEACON_IE_OFFSET_));
+		if (pbuf && ie_len > 0) {
+			_rtw_memcpy(pframe, pbuf, ie_len + 2);
+			pframe += (ie_len + 2);
+			pattrib->pktlen += (ie_len + 2);
+		}
+
+		/* FILL VHT OPERATION IE */
+		pbuf = rtw_get_ie(ie + _BEACON_IE_OFFSET_, EID_VHTOperation, &ie_len, (pnetwork->IELength - _BEACON_IE_OFFSET_));
+		if (pbuf && ie_len > 0) {
+			_rtw_memcpy(pframe, pbuf, ie_len + 2);
+			pframe += (ie_len + 2);
+			pattrib->pktlen += (ie_len + 2);
+		}
+	}
+#endif /* CONFIG_80211AC_VHT */
+
+	/* FILL WMM IE */
+	if ((pstat->flags & WLAN_STA_WME) && (pmlmepriv->qospriv.qos_option)) {
+		uint ie_len = 0;
+		unsigned char WMM_PARA_IE[] = {0x00, 0x50, 0xf2, 0x02, 0x01, 0x01};
+
+		for (pbuf = ie + _BEACON_IE_OFFSET_; ; pbuf += (ie_len + 2)) {
+			pbuf = rtw_get_ie(pbuf, _VENDOR_SPECIFIC_IE_, &ie_len, (pnetwork->IELength - _BEACON_IE_OFFSET_ - (ie_len + 2)));
+			if (pbuf && _rtw_memcmp(pbuf + 2, WMM_PARA_IE, 6)) {
+				_rtw_memcpy(pframe, pbuf, ie_len + 2);
+				pframe += (ie_len + 2);
+				pattrib->pktlen += (ie_len + 2);
+
+				break;
+			}
+
+			if ((pbuf == NULL) || (ie_len == 0))
+				break;
+		}
+
+	}
+
+
+	if (pmlmeinfo->assoc_AP_vendor == HT_IOT_PEER_REALTEK)
+		pframe = rtw_set_ie(pframe, _VENDOR_SPECIFIC_IE_, 6 , REALTEK_96B_IE, &(pattrib->pktlen));
+
+	/* add WPS IE ie for wps 2.0 */
+	if (pmlmepriv->wps_assoc_resp_ie && pmlmepriv->wps_assoc_resp_ie_len > 0) {
+		_rtw_memcpy(pframe, pmlmepriv->wps_assoc_resp_ie, pmlmepriv->wps_assoc_resp_ie_len);
+
+		pframe += pmlmepriv->wps_assoc_resp_ie_len;
+		pattrib->pktlen += pmlmepriv->wps_assoc_resp_ie_len;
+	}
+
+#ifdef CONFIG_P2P
+	if (rtw_p2p_chk_role(pwdinfo, P2P_ROLE_GO) && (pstat->is_p2p_device == _TRUE)) {
+		u32 len;
+
+		if (padapter->wdinfo.driver_interface == DRIVER_CFG80211) {
+			len = 0;
+			if (pmlmepriv->p2p_assoc_resp_ie && pmlmepriv->p2p_assoc_resp_ie_len > 0) {
+				len = pmlmepriv->p2p_assoc_resp_ie_len;
+				_rtw_memcpy(pframe, pmlmepriv->p2p_assoc_resp_ie, len);
+			}
+		} else
+			len = build_assoc_resp_p2p_ie(pwdinfo, pframe, pstat->p2p_status_code);
+		pframe += len;
+		pattrib->pktlen += len;
+	}
+
+#ifdef CONFIG_WFD
+	if (rtw_p2p_chk_role(pwdinfo, P2P_ROLE_GO)) {
+		wfdielen = rtw_append_assoc_resp_wfd_ie(padapter, pframe);
+		pframe += wfdielen;
+		pattrib->pktlen += wfdielen;
+	}
+#endif
+
+#endif /* CONFIG_P2P */
+#ifdef CONFIG_APPEND_VENDOR_IE_ENABLE
+	pattrib->pktlen += rtw_build_vendor_ie(padapter , pframe , WIFI_ASSOCRESP_VENDOR_IE_BIT);
+#endif
+	pattrib->last_txcmdsz = pattrib->pktlen;
+
+	dump_mgntframe(padapter, pmgntframe);
+
+#endif
+}
+
+void _issue_assocreq(_adapter *padapter, u8 is_reassoc)
+{
+	int ret = _FAIL;
+	struct xmit_frame				*pmgntframe;
+	struct pkt_attrib				*pattrib;
+	unsigned char					*pframe;
+	struct rtw_ieee80211_hdr			*pwlanhdr;
+	unsigned short				*fctrl;
+	unsigned short				val16;
+	unsigned int					i, j, index = 0;
+	unsigned char					bssrate[NumRates], sta_bssrate[NumRates];
+	PNDIS_802_11_VARIABLE_IEs	pIE;
+	struct xmit_priv		*pxmitpriv = &(padapter->xmitpriv);
+	struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
+	struct mlme_ext_priv	*pmlmeext = &(padapter->mlmeextpriv);
+	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
+	int	bssrate_len = 0, sta_bssrate_len = 0;
+	u8	vs_ie_length = 0;
+#ifdef CONFIG_P2P
+	struct wifidirect_info	*pwdinfo = &(padapter->wdinfo);
+	u8					p2pie[255] = { 0x00 };
+	u16					p2pielen = 0;
+#ifdef CONFIG_WFD
+	u32					wfdielen = 0;
+#endif
+#endif /* CONFIG_P2P */
+
+#ifdef CONFIG_DFS
+	struct rf_ctl_t *rfctl = adapter_to_rfctl(padapter);
+	u16	cap;
+
+	/* Dot H */
+	u8 pow_cap_ele[2] = { 0x00 };
+	u8 sup_ch[30 * 2] = {0x00 }, sup_ch_idx = 0, idx_5g = 2;	/* For supported channel */
+#endif /* CONFIG_DFS */
+
+	if (rtw_rfctl_is_tx_blocked_by_ch_waiting(adapter_to_rfctl(padapter)))
+		goto exit;
+
+	pmgntframe = alloc_mgtxmitframe(pxmitpriv);
+	if (pmgntframe == NULL)
+		goto exit;
+
+	/* update attribute */
+	pattrib = &pmgntframe->attrib;
+	update_mgntframe_attrib(padapter, pattrib);
+
+
+	_rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET);
+
+	pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET;
+	pwlanhdr = (struct rtw_ieee80211_hdr *)pframe;
+
+	fctrl = &(pwlanhdr->frame_ctl);
+	*(fctrl) = 0;
+	_rtw_memcpy(pwlanhdr->addr1, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN);
+	_rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN);
+	_rtw_memcpy(pwlanhdr->addr3, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN);
+
+	SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq);
+	pmlmeext->mgnt_seq++;
+	if (is_reassoc == _TRUE)
+		set_frame_sub_type(pframe, WIFI_REASSOCREQ);
+	else
+		set_frame_sub_type(pframe, WIFI_ASSOCREQ);
+
+	pframe += sizeof(struct rtw_ieee80211_hdr_3addr);
+	pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr);
+
+	/* caps */
+
+#ifdef CONFIG_DFS
+	_rtw_memcpy(&cap, rtw_get_capability_from_ie(pmlmeinfo->network.IEs), 2);
+	cap |= cap_SpecMgmt;
+	_rtw_memcpy(pframe, &cap, 2);
+#else
+	_rtw_memcpy(pframe, rtw_get_capability_from_ie(pmlmeinfo->network.IEs), 2);
+#endif /* CONFIG_DFS */
+
+	pframe += 2;
+	pattrib->pktlen += 2;
+
+	/* listen interval */
+	/* todo: listen interval for power saving */
+	val16 = cpu_to_le16(3);
+	_rtw_memcpy(pframe , (unsigned char *)&val16, 2);
+	pframe += 2;
+	pattrib->pktlen += 2;
+
+	/*Construct Current AP Field for Reassoc-Req only*/
+	if (is_reassoc == _TRUE) {
+		_rtw_memcpy(pframe, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN);
+		pframe += ETH_ALEN;
+		pattrib->pktlen += ETH_ALEN;
+	}
+
+	/* SSID */
+	pframe = rtw_set_ie(pframe, _SSID_IE_,  pmlmeinfo->network.Ssid.SsidLength, pmlmeinfo->network.Ssid.Ssid, &(pattrib->pktlen));
+
+#ifdef CONFIG_DFS
+	/* Dot H */
+	if (pmlmeext->cur_channel > 14) {
+		pow_cap_ele[0] = 13;	/* Minimum transmit power capability */
+		pow_cap_ele[1] = 21;	/* Maximum transmit power capability */
+		pframe = rtw_set_ie(pframe, EID_PowerCap, 2, pow_cap_ele, &(pattrib->pktlen));
+
+		/* supported channels */
+		while (sup_ch_idx < rfctl->max_chan_nums && rfctl->channel_set[sup_ch_idx].ChannelNum != 0) {
+			if (rfctl->channel_set[sup_ch_idx].ChannelNum <= 14) {
+				/* TODO: fix 2.4G supported channel when channel doesn't start from 1 and continuous */
+				sup_ch[0] = 1;	/* First channel number */
+				sup_ch[1] = rfctl->channel_set[sup_ch_idx].ChannelNum;	/* Number of channel */
+			} else {
+				sup_ch[idx_5g++] = rfctl->channel_set[sup_ch_idx].ChannelNum;
+				sup_ch[idx_5g++] = 1;
+			}
+			sup_ch_idx++;
+		}
+		pframe = rtw_set_ie(pframe, EID_SupportedChannels, idx_5g, sup_ch, &(pattrib->pktlen));
+	}
+#endif /* CONFIG_DFS */
+
+	/* supported rate & extended supported rate */
+
+#if 1	/* Check if the AP's supported rates are also supported by STA. */
+	get_rate_set(padapter, sta_bssrate, &sta_bssrate_len);
+	/* RTW_INFO("sta_bssrate_len=%d\n", sta_bssrate_len); */
+
+	if (pmlmeext->cur_channel == 14) /* for JAPAN, channel 14 can only uses B Mode(CCK) */
+		sta_bssrate_len = 4;
+
+
+	/* for (i = 0; i < sta_bssrate_len; i++) { */
+	/*	RTW_INFO("sta_bssrate[%d]=%02X\n", i, sta_bssrate[i]); */
+	/* } */
+
+	for (i = 0; i < NDIS_802_11_LENGTH_RATES_EX; i++) {
+		if (pmlmeinfo->network.SupportedRates[i] == 0)
+			break;
+		RTW_INFO("network.SupportedRates[%d]=%02X\n", i, pmlmeinfo->network.SupportedRates[i]);
+	}
+
+
+	for (i = 0; i < NDIS_802_11_LENGTH_RATES_EX; i++) {
+		if (pmlmeinfo->network.SupportedRates[i] == 0)
+			break;
+
+
+		/* Check if the AP's supported rates are also supported by STA. */
+		for (j = 0; j < sta_bssrate_len; j++) {
+			/* Avoid the proprietary data rate (22Mbps) of Handlink WSG-4000 AP */
+			if ((pmlmeinfo->network.SupportedRates[i] | IEEE80211_BASIC_RATE_MASK)
+			    == (sta_bssrate[j] | IEEE80211_BASIC_RATE_MASK)) {
+				/* RTW_INFO("match i = %d, j=%d\n", i, j); */
+				break;
+			} else {
+				/* RTW_INFO("not match: %02X != %02X\n", (pmlmeinfo->network.SupportedRates[i]|IEEE80211_BASIC_RATE_MASK), (sta_bssrate[j]|IEEE80211_BASIC_RATE_MASK)); */
+			}
+		}
+
+		if (j == sta_bssrate_len) {
+			/* the rate is not supported by STA */
+			RTW_INFO("%s(): the rate[%d]=%02X is not supported by STA!\n", __FUNCTION__, i, pmlmeinfo->network.SupportedRates[i]);
+		} else {
+			/* the rate is supported by STA */
+			bssrate[index++] = pmlmeinfo->network.SupportedRates[i];
+		}
+	}
+
+	bssrate_len = index;
+	RTW_INFO("bssrate_len = %d\n", bssrate_len);
+
+#else	/* Check if the AP's supported rates are also supported by STA. */
+#if 0
+	get_rate_set(padapter, bssrate, &bssrate_len);
+#else
+	for (bssrate_len = 0; bssrate_len < NumRates; bssrate_len++) {
+		if (pmlmeinfo->network.SupportedRates[bssrate_len] == 0)
+			break;
+
+		if (pmlmeinfo->network.SupportedRates[bssrate_len] == 0x2C) /* Avoid the proprietary data rate (22Mbps) of Handlink WSG-4000 AP */
+			break;
+
+		bssrate[bssrate_len] = pmlmeinfo->network.SupportedRates[bssrate_len];
+	}
+#endif
+#endif /* Check if the AP's supported rates are also supported by STA. */
+
+	if ((bssrate_len == 0) && (pmlmeinfo->network.SupportedRates[0] != 0)) {
+		rtw_free_xmitbuf(pxmitpriv, pmgntframe->pxmitbuf);
+		rtw_free_xmitframe(pxmitpriv, pmgntframe);
+		goto exit; /* don't connect to AP if no joint supported rate */
+	}
+
+
+	if (bssrate_len > 8) {
+		pframe = rtw_set_ie(pframe, _SUPPORTEDRATES_IE_ , 8, bssrate, &(pattrib->pktlen));
+		pframe = rtw_set_ie(pframe, _EXT_SUPPORTEDRATES_IE_ , (bssrate_len - 8), (bssrate + 8), &(pattrib->pktlen));
+	} else if (bssrate_len > 0)
+		pframe = rtw_set_ie(pframe, _SUPPORTEDRATES_IE_ , bssrate_len , bssrate, &(pattrib->pktlen));
+	else
+		RTW_INFO("%s: Connect to AP without 11b and 11g data rate!\n", __FUNCTION__);
+
+#ifdef CONFIG_RTW_80211K
+	if (pmlmeinfo->network.PhyInfo.rm_en_cap[0] /* RM Enabled Capabilities */
+		| pmlmeinfo->network.PhyInfo.rm_en_cap[1]
+		| pmlmeinfo->network.PhyInfo.rm_en_cap[2]
+		| pmlmeinfo->network.PhyInfo.rm_en_cap[3]
+		| pmlmeinfo->network.PhyInfo.rm_en_cap[4])
+		pframe = rtw_set_ie(pframe, _EID_RRM_EN_CAP_IE_, 5,
+				(u8 *)padapter->rmpriv.rm_en_cap_def, &(pattrib->pktlen));
+#endif /* CONFIG_RTW_80211K */
+
+	/* vendor specific IE, such as WPA, WMM, WPS */
+	for (i = sizeof(NDIS_802_11_FIXED_IEs); i < pmlmeinfo->network.IELength;) {
+		pIE = (PNDIS_802_11_VARIABLE_IEs)(pmlmeinfo->network.IEs + i);
+
+		switch (pIE->ElementID) {
+		case _VENDOR_SPECIFIC_IE_:
+			if ((_rtw_memcmp(pIE->data, RTW_WPA_OUI, 4)) ||
+			    (_rtw_memcmp(pIE->data, WMM_OUI, 4)) ||
+			    (_rtw_memcmp(pIE->data, WPS_OUI, 4))) {
+				vs_ie_length = pIE->Length;
+				if ((!padapter->registrypriv.wifi_spec) && (_rtw_memcmp(pIE->data, WPS_OUI, 4))) {
+					/* Commented by Kurt 20110629 */
+					/* In some older APs, WPS handshake */
+					/* would be fail if we append vender extensions informations to AP */
+
+					vs_ie_length = 14;
+				}
+
+				pframe = rtw_set_ie(pframe, _VENDOR_SPECIFIC_IE_, vs_ie_length, pIE->data, &(pattrib->pktlen));
+			}
+			break;
+
+		case EID_WPA2:
+#ifdef CONFIG_RTW_80211R
+			if ((is_reassoc) && (rtw_ft_roam(padapter))) {
+				rtw_ft_update_rsnie(padapter, _TRUE, pattrib, &pframe);
+			} else
+#endif
+				pframe = rtw_set_ie(pframe, EID_WPA2, pIE->Length, pIE->data, &(pattrib->pktlen));
+			break;
+#ifdef CONFIG_80211N_HT
+		case EID_HTCapability:
+			if (padapter->mlmepriv.htpriv.ht_option == _TRUE) {
+				if (!(is_ap_in_tkip(padapter))) {
+					_rtw_memcpy(&(pmlmeinfo->HT_caps), pIE->data, sizeof(struct HT_caps_element));
+
+					pmlmeinfo->HT_caps.u.HT_cap_element.HT_caps_info = cpu_to_le16(pmlmeinfo->HT_caps.u.HT_cap_element.HT_caps_info);
+
+					pframe = rtw_set_ie(pframe, EID_HTCapability, pIE->Length , (u8 *)(&(pmlmeinfo->HT_caps)), &(pattrib->pktlen));
+				}
+			}
+			break;
+
+		case EID_EXTCapability:
+			if (padapter->mlmepriv.htpriv.ht_option == _TRUE)
+				pframe = rtw_set_ie(pframe, EID_EXTCapability, pIE->Length, pIE->data, &(pattrib->pktlen));
+			break;
+#endif /* CONFIG_80211N_HT */
+#ifdef CONFIG_80211AC_VHT
+		case EID_VHTCapability:
+			if (padapter->mlmepriv.vhtpriv.vht_option == _TRUE)
+				pframe = rtw_set_ie(pframe, EID_VHTCapability, pIE->Length, pIE->data, &(pattrib->pktlen));
+			break;
+
+		case EID_OpModeNotification:
+			if (padapter->mlmepriv.vhtpriv.vht_option == _TRUE)
+				pframe = rtw_set_ie(pframe, EID_OpModeNotification, pIE->Length, pIE->data, &(pattrib->pktlen));
+			break;
+#endif /* CONFIG_80211AC_VHT */
+		default:
+			break;
+		}
+
+		i += (pIE->Length + 2);
+	}
+
+	if (pmlmeinfo->assoc_AP_vendor == HT_IOT_PEER_REALTEK)
+		pframe = rtw_set_ie(pframe, _VENDOR_SPECIFIC_IE_, 6 , REALTEK_96B_IE, &(pattrib->pktlen));
+
+
+#ifdef CONFIG_WAPI_SUPPORT
+	rtw_build_assoc_req_wapi_ie(padapter, pframe, pattrib);
+#endif
+
+
+#ifdef CONFIG_P2P
+
+#ifdef CONFIG_IOCTL_CFG80211
+	if (adapter_wdev_data(padapter)->p2p_enabled && pwdinfo->driver_interface == DRIVER_CFG80211) {
+		if (pmlmepriv->p2p_assoc_req_ie && pmlmepriv->p2p_assoc_req_ie_len > 0) {
+			_rtw_memcpy(pframe, pmlmepriv->p2p_assoc_req_ie, pmlmepriv->p2p_assoc_req_ie_len);
+			pframe += pmlmepriv->p2p_assoc_req_ie_len;
+			pattrib->pktlen += pmlmepriv->p2p_assoc_req_ie_len;
+		}
+	} else
+#endif /* CONFIG_IOCTL_CFG80211 */
+	{
+		if (!rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE) && !rtw_p2p_chk_state(pwdinfo, P2P_STATE_IDLE)) {
+			/*	Should add the P2P IE in the association request frame.	 */
+			/*	P2P OUI */
+
+			p2pielen = 0;
+			p2pie[p2pielen++] = 0x50;
+			p2pie[p2pielen++] = 0x6F;
+			p2pie[p2pielen++] = 0x9A;
+			p2pie[p2pielen++] = 0x09;	/*	WFA P2P v1.0 */
+
+			/*	Commented by Albert 20101109 */
+			/*	According to the P2P Specification, the association request frame should contain 3 P2P attributes */
+			/*	1. P2P Capability */
+			/*	2. Extended Listen Timing */
+			/*	3. Device Info */
+			/*	Commented by Albert 20110516 */
+			/*	4. P2P Interface */
+
+			/*	P2P Capability */
+			/*	Type: */
+			p2pie[p2pielen++] = P2P_ATTR_CAPABILITY;
+
+			/*	Length: */
+			*(u16 *)(p2pie + p2pielen) = cpu_to_le16(0x0002);
+			p2pielen += 2;
+
+			/*	Value: */
+			/*	Device Capability Bitmap, 1 byte */
+			p2pie[p2pielen++] = DMP_P2P_DEVCAP_SUPPORT;
+
+			/*	Group Capability Bitmap, 1 byte */
+			if (pwdinfo->persistent_supported)
+				p2pie[p2pielen++] = P2P_GRPCAP_PERSISTENT_GROUP | DMP_P2P_GRPCAP_SUPPORT;
+			else
+				p2pie[p2pielen++] = DMP_P2P_GRPCAP_SUPPORT;
+
+			/*	Extended Listen Timing */
+			/*	Type: */
+			p2pie[p2pielen++] = P2P_ATTR_EX_LISTEN_TIMING;
+
+			/*	Length: */
+			*(u16 *)(p2pie + p2pielen) = cpu_to_le16(0x0004);
+			p2pielen += 2;
+
+			/*	Value: */
+			/*	Availability Period */
+			*(u16 *)(p2pie + p2pielen) = cpu_to_le16(0xFFFF);
+			p2pielen += 2;
+
+			/*	Availability Interval */
+			*(u16 *)(p2pie + p2pielen) = cpu_to_le16(0xFFFF);
+			p2pielen += 2;
+
+			/*	Device Info */
+			/*	Type: */
+			p2pie[p2pielen++] = P2P_ATTR_DEVICE_INFO;
+
+			/*	Length: */
+			/*	21->P2P Device Address (6bytes) + Config Methods (2bytes) + Primary Device Type (8bytes)  */
+			/*	+ NumofSecondDevType (1byte) + WPS Device Name ID field (2bytes) + WPS Device Name Len field (2bytes) */
+			*(u16 *)(p2pie + p2pielen) = cpu_to_le16(21 + pwdinfo->device_name_len);
+			p2pielen += 2;
+
+			/*	Value: */
+			/*	P2P Device Address */
+			_rtw_memcpy(p2pie + p2pielen, adapter_mac_addr(padapter), ETH_ALEN);
+			p2pielen += ETH_ALEN;
+
+			/*	Config Method */
+			/*	This field should be big endian. Noted by P2P specification. */
+			if ((pwdinfo->ui_got_wps_info == P2P_GOT_WPSINFO_PEER_DISPLAY_PIN) ||
+			    (pwdinfo->ui_got_wps_info == P2P_GOT_WPSINFO_SELF_DISPLAY_PIN))
+				*(u16 *)(p2pie + p2pielen) = cpu_to_be16(WPS_CONFIG_METHOD_DISPLAY);
+			else
+				*(u16 *)(p2pie + p2pielen) = cpu_to_be16(WPS_CONFIG_METHOD_PBC);
+
+			p2pielen += 2;
+
+			/*	Primary Device Type */
+			/*	Category ID */
+			*(u16 *)(p2pie + p2pielen) = cpu_to_be16(WPS_PDT_CID_MULIT_MEDIA);
+			p2pielen += 2;
+
+			/*	OUI */
+			*(u32 *)(p2pie + p2pielen) = cpu_to_be32(WPSOUI);
+			p2pielen += 4;
+
+			/*	Sub Category ID */
+			*(u16 *)(p2pie + p2pielen) = cpu_to_be16(WPS_PDT_SCID_MEDIA_SERVER);
+			p2pielen += 2;
+
+			/*	Number of Secondary Device Types */
+			p2pie[p2pielen++] = 0x00;	/*	No Secondary Device Type List */
+
+			/*	Device Name */
+			/*	Type: */
+			*(u16 *)(p2pie + p2pielen) = cpu_to_be16(WPS_ATTR_DEVICE_NAME);
+			p2pielen += 2;
+
+			/*	Length: */
+			*(u16 *)(p2pie + p2pielen) = cpu_to_be16(pwdinfo->device_name_len);
+			p2pielen += 2;
+
+			/*	Value: */
+			_rtw_memcpy(p2pie + p2pielen, pwdinfo->device_name, pwdinfo->device_name_len);
+			p2pielen += pwdinfo->device_name_len;
+
+			/*	P2P Interface */
+			/*	Type: */
+			p2pie[p2pielen++] = P2P_ATTR_INTERFACE;
+
+			/*	Length: */
+			*(u16 *)(p2pie + p2pielen) = cpu_to_le16(0x000D);
+			p2pielen += 2;
+
+			/*	Value: */
+			_rtw_memcpy(p2pie + p2pielen, pwdinfo->device_addr, ETH_ALEN);	/*	P2P Device Address */
+			p2pielen += ETH_ALEN;
+
+			p2pie[p2pielen++] = 1;	/*	P2P Interface Address Count */
+
+			_rtw_memcpy(p2pie + p2pielen, pwdinfo->device_addr, ETH_ALEN);	/*	P2P Interface Address List */
+			p2pielen += ETH_ALEN;
+
+			pframe = rtw_set_ie(pframe, _VENDOR_SPECIFIC_IE_, p2pielen, (unsigned char *) p2pie, &pattrib->pktlen);
+		}
+	}
+
+#endif /* CONFIG_P2P */
+
+#ifdef CONFIG_WFD
+	wfdielen = rtw_append_assoc_req_wfd_ie(padapter, pframe);
+	pframe += wfdielen;
+	pattrib->pktlen += wfdielen;
+#endif
+#ifdef CONFIG_RTW_REPEATER_SON
+	rtw_rson_append_ie(padapter, pframe, &pattrib->pktlen);
+#endif
+#ifdef CONFIG_APPEND_VENDOR_IE_ENABLE
+	pattrib->pktlen += rtw_build_vendor_ie(padapter , pframe , WIFI_ASSOCREQ_VENDOR_IE_BIT);
+#endif
+#ifdef CONFIG_RTW_80211R
+	rtw_ft_build_assoc_req_ies(padapter, is_reassoc, pattrib, &pframe);
+#endif
+
+	pattrib->last_txcmdsz = pattrib->pktlen;
+	dump_mgntframe(padapter, pmgntframe);
+
+	ret = _SUCCESS;
+
+exit:
+	if (ret == _SUCCESS)
+		rtw_buf_update(&pmlmepriv->assoc_req, &pmlmepriv->assoc_req_len, (u8 *)pwlanhdr, pattrib->pktlen);
+	else
+		rtw_buf_free(&pmlmepriv->assoc_req, &pmlmepriv->assoc_req_len);
+
+	return;
+}
+
+void issue_assocreq(_adapter *padapter)
+{
+	_issue_assocreq(padapter, _FALSE);
+}
+
+void issue_reassocreq(_adapter *padapter)
+{
+	_issue_assocreq(padapter, _TRUE);
+}
+
+/* when wait_ack is ture, this function shoule be called at process context */
+static int _issue_nulldata(_adapter *padapter, unsigned char *da, unsigned int power_mode, int wait_ack)
+{
+	int ret = _FAIL;
+	struct xmit_frame			*pmgntframe;
+	struct pkt_attrib			*pattrib;
+	unsigned char					*pframe;
+	struct rtw_ieee80211_hdr	*pwlanhdr;
+	unsigned short				*fctrl;
+	struct xmit_priv	*pxmitpriv;
+	struct mlme_ext_priv	*pmlmeext;
+	struct mlme_ext_info	*pmlmeinfo;
+	u8 a4_shift;
+
+	/* RTW_INFO("%s:%d\n", __FUNCTION__, power_mode); */
+
+	if (!padapter)
+		goto exit;
+
+	if (rtw_rfctl_is_tx_blocked_by_ch_waiting(adapter_to_rfctl(padapter)))
+		goto exit;
+
+	pxmitpriv = &(padapter->xmitpriv);
+	pmlmeext = &(padapter->mlmeextpriv);
+	pmlmeinfo = &(pmlmeext->mlmext_info);
+
+	pmgntframe = alloc_mgtxmitframe(pxmitpriv);
+	if (pmgntframe == NULL)
+		goto exit;
+
+	/* update attribute */
+	pattrib = &pmgntframe->attrib;
+	update_mgntframe_attrib(padapter, pattrib);
+	pattrib->retry_ctrl = _FALSE;
+
+	_rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET);
+
+	pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET;
+	pwlanhdr = (struct rtw_ieee80211_hdr *)pframe;
+
+	fctrl = &(pwlanhdr->frame_ctl);
+	*(fctrl) = 0;
+
+	if (MLME_IS_AP(padapter))
+		SetFrDs(fctrl);
+	else if (MLME_IS_STA(padapter))
+		SetToDs(fctrl);
+	else if (MLME_IS_MESH(padapter)) {
+		SetToDs(fctrl);
+		SetFrDs(fctrl);
+	}
+
+	if (power_mode)
+		SetPwrMgt(fctrl);
+
+	if (get_tofr_ds(fctrl) == 3) {
+		_rtw_memcpy(pwlanhdr->addr1, da, ETH_ALEN);
+		_rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN);
+		_rtw_memcpy(pwlanhdr->addr3, da, ETH_ALEN);
+		_rtw_memcpy(pwlanhdr->addr4, adapter_mac_addr(padapter), ETH_ALEN);
+		a4_shift = ETH_ALEN;
+		pattrib->hdrlen += ETH_ALEN;
+	} else {
+		_rtw_memcpy(pwlanhdr->addr1, da, ETH_ALEN);
+		_rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN);
+		_rtw_memcpy(pwlanhdr->addr3, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN);
+		a4_shift = 0;
+	}
+
+	SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq);
+	pmlmeext->mgnt_seq++;
+	set_frame_sub_type(pframe, WIFI_DATA_NULL);
+
+	pframe += sizeof(struct rtw_ieee80211_hdr_3addr) + a4_shift;
+	pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr) + a4_shift;
+
+	pattrib->last_txcmdsz = pattrib->pktlen;
+
+	if (wait_ack)
+		ret = dump_mgntframe_and_wait_ack(padapter, pmgntframe);
+	else {
+		dump_mgntframe(padapter, pmgntframe);
+		ret = _SUCCESS;
+	}
+
+exit:
+	return ret;
+}
+
+/*
+ * When wait_ms > 0, this function should be called at process context
+ * wait_ms == 0 means that there is no need to wait ack through C2H_CCX_TX_RPT
+ * wait_ms > 0 means you want to wait ack through C2H_CCX_TX_RPT, and the value of wait_ms means the interval between each TX
+ * try_cnt means the maximal TX count to try
+ * da == NULL for station mode
+ */
+int issue_nulldata(_adapter *padapter, unsigned char *da, unsigned int power_mode, int try_cnt, int wait_ms)
+{
+	int ret = _FAIL;
+	int i = 0;
+	systime start = rtw_get_current_time();
+	struct mlme_ext_priv	*pmlmeext = &(padapter->mlmeextpriv);
+	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
+
+	if (rtw_rfctl_is_tx_blocked_by_ch_waiting(adapter_to_rfctl(padapter)))
+		goto exit;
+
+	/* da == NULL, assum it's null data for sta to ap */
+	if (da == NULL)
+		da = get_my_bssid(&(pmlmeinfo->network));
+
+	do {
+		ret = _issue_nulldata(padapter, da, power_mode, wait_ms > 0 ? _TRUE : _FALSE);
+
+		i++;
+
+		if (RTW_CANNOT_RUN(padapter))
+			break;
+
+		if (i < try_cnt && wait_ms > 0 && ret == _FAIL)
+			rtw_msleep_os(wait_ms);
+
+	} while ((i < try_cnt) && ((ret == _FAIL) || (wait_ms == 0)));
+
+	if (ret != _FAIL) {
+		ret = _SUCCESS;
+#ifndef DBG_XMIT_ACK
+		goto exit;
+#endif
+	}
+
+	if (try_cnt && wait_ms) {
+		if (da)
+			RTW_INFO(FUNC_ADPT_FMT" to "MAC_FMT", ch:%u%s, %d/%d in %u ms\n",
+				FUNC_ADPT_ARG(padapter), MAC_ARG(da), rtw_get_oper_ch(padapter),
+				ret == _SUCCESS ? ", acked" : "", i, try_cnt, rtw_get_passing_time_ms(start));
+		else
+			RTW_INFO(FUNC_ADPT_FMT", ch:%u%s, %d/%d in %u ms\n",
+				FUNC_ADPT_ARG(padapter), rtw_get_oper_ch(padapter),
+				ret == _SUCCESS ? ", acked" : "", i, try_cnt, rtw_get_passing_time_ms(start));
+	}
+exit:
+	return ret;
+}
+
+/* when wait_ack is ture, this function shoule be called at process context */
+static int _issue_qos_nulldata(_adapter *padapter, unsigned char *da, u16 tid, u8 ps, int wait_ack)
+{
+	int ret = _FAIL;
+	struct xmit_frame			*pmgntframe;
+	struct pkt_attrib			*pattrib;
+	unsigned char					*pframe;
+	struct rtw_ieee80211_hdr	*pwlanhdr;
+	unsigned short				*fctrl, *qc;
+	struct xmit_priv			*pxmitpriv = &(padapter->xmitpriv);
+	struct mlme_ext_priv	*pmlmeext = &(padapter->mlmeextpriv);
+	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
+	u8 a4_shift;
+
+	if (rtw_rfctl_is_tx_blocked_by_ch_waiting(adapter_to_rfctl(padapter)))
+		goto exit;
+
+	/* RTW_INFO("%s\n", __FUNCTION__); */
+
+	pmgntframe = alloc_mgtxmitframe(pxmitpriv);
+	if (pmgntframe == NULL)
+		goto exit;
+
+	/* update attribute */
+	pattrib = &pmgntframe->attrib;
+	update_mgntframe_attrib(padapter, pattrib);
+
+	pattrib->hdrlen += 2;
+	pattrib->qos_en = _TRUE;
+	pattrib->eosp = 1;
+	pattrib->ack_policy = 0;
+	pattrib->mdata = 0;
+
+	_rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET);
+
+	pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET;
+	pwlanhdr = (struct rtw_ieee80211_hdr *)pframe;
+
+	fctrl = &(pwlanhdr->frame_ctl);
+	*(fctrl) = 0;
+
+	if (MLME_IS_AP(padapter))
+		SetFrDs(fctrl);
+	else if (MLME_IS_STA(padapter))
+		SetToDs(fctrl);
+	else if (MLME_IS_MESH(padapter)) {
+		SetToDs(fctrl);
+		SetFrDs(fctrl);
+	}
+
+	if (ps)
+		SetPwrMgt(fctrl);
+
+	if (pattrib->mdata)
+		SetMData(fctrl);
+
+	if (get_tofr_ds(fctrl) == 3) {
+		_rtw_memcpy(pwlanhdr->addr1, da, ETH_ALEN);
+		_rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN);
+		_rtw_memcpy(pwlanhdr->addr3, da, ETH_ALEN);
+		_rtw_memcpy(pwlanhdr->addr4, adapter_mac_addr(padapter), ETH_ALEN);
+		a4_shift = ETH_ALEN;
+		pattrib->hdrlen += ETH_ALEN;
+	} else {
+		_rtw_memcpy(pwlanhdr->addr1, da, ETH_ALEN);
+		_rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN);
+		_rtw_memcpy(pwlanhdr->addr3, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN);
+		a4_shift = 0;
+	}
+
+	qc = (unsigned short *)(pframe + pattrib->hdrlen - 2);
+
+	SetPriority(qc, tid);
+
+	SetEOSP(qc, pattrib->eosp);
+
+	SetAckpolicy(qc, pattrib->ack_policy);
+
+	SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq);
+	pmlmeext->mgnt_seq++;
+	set_frame_sub_type(pframe, WIFI_QOS_DATA_NULL);
+
+	pframe += sizeof(struct rtw_ieee80211_hdr_3addr_qos) + a4_shift;
+	pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr_qos) + a4_shift;
+
+	pattrib->last_txcmdsz = pattrib->pktlen;
+
+	if (wait_ack)
+		ret = dump_mgntframe_and_wait_ack(padapter, pmgntframe);
+	else {
+		dump_mgntframe(padapter, pmgntframe);
+		ret = _SUCCESS;
+	}
+
+exit:
+	return ret;
+}
+
+/*
+ * when wait_ms >0 , this function should be called at process context
+ * wait_ms == 0 means that there is no need to wait ack through C2H_CCX_TX_RPT
+ * wait_ms > 0 means you want to wait ack through C2H_CCX_TX_RPT, and the value of wait_ms means the interval between each TX
+ * try_cnt means the maximal TX count to try
+ * da == NULL for station mode
+ */
+int issue_qos_nulldata(_adapter *padapter, unsigned char *da, u16 tid, u8 ps, int try_cnt, int wait_ms)
+{
+	int ret = _FAIL;
+	int i = 0;
+	systime start = rtw_get_current_time();
+	struct mlme_ext_priv	*pmlmeext = &(padapter->mlmeextpriv);
+	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
+
+	if (rtw_rfctl_is_tx_blocked_by_ch_waiting(adapter_to_rfctl(padapter)))
+		goto exit;
+
+	/* da == NULL, assum it's null data for sta to ap*/
+	if (da == NULL)
+		da = get_my_bssid(&(pmlmeinfo->network));
+
+	do {
+		ret = _issue_qos_nulldata(padapter, da, tid, ps, wait_ms > 0 ? _TRUE : _FALSE);
+
+		i++;
+
+		if (RTW_CANNOT_RUN(padapter))
+			break;
+
+		if (i < try_cnt && wait_ms > 0 && ret == _FAIL)
+			rtw_msleep_os(wait_ms);
+
+	} while ((i < try_cnt) && ((ret == _FAIL) || (wait_ms == 0)));
+
+	if (ret != _FAIL) {
+		ret = _SUCCESS;
+#ifndef DBG_XMIT_ACK
+		goto exit;
+#endif
+	}
+
+	if (try_cnt && wait_ms) {
+		if (da)
+			RTW_INFO(FUNC_ADPT_FMT" to "MAC_FMT", ch:%u%s, %d/%d in %u ms\n",
+				FUNC_ADPT_ARG(padapter), MAC_ARG(da), rtw_get_oper_ch(padapter),
+				ret == _SUCCESS ? ", acked" : "", i, try_cnt, rtw_get_passing_time_ms(start));
+		else
+			RTW_INFO(FUNC_ADPT_FMT", ch:%u%s, %d/%d in %u ms\n",
+				FUNC_ADPT_ARG(padapter), rtw_get_oper_ch(padapter),
+				ret == _SUCCESS ? ", acked" : "", i, try_cnt, rtw_get_passing_time_ms(start));
+	}
+exit:
+	return ret;
+}
+
+static int _issue_deauth(_adapter *padapter, unsigned char *da, unsigned short reason, u8 wait_ack, u8 key_type)
+{
+	struct xmit_frame			*pmgntframe;
+	struct pkt_attrib			*pattrib;
+	unsigned char					*pframe;
+	struct rtw_ieee80211_hdr	*pwlanhdr;
+	unsigned short				*fctrl;
+	struct xmit_priv			*pxmitpriv = &(padapter->xmitpriv);
+	struct mlme_ext_priv	*pmlmeext = &(padapter->mlmeextpriv);
+	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
+	int ret = _FAIL;
+#ifdef CONFIG_P2P
+	struct wifidirect_info *pwdinfo = &(padapter->wdinfo);
+#endif /* CONFIG_P2P	 */
+
+	/* RTW_INFO("%s to "MAC_FMT"\n", __func__, MAC_ARG(da)); */
+
+#ifdef CONFIG_P2P
+	if (!(rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE)) && (pwdinfo->rx_invitereq_info.scan_op_ch_only)) {
+		_cancel_timer_ex(&pwdinfo->reset_ch_sitesurvey);
+		_set_timer(&pwdinfo->reset_ch_sitesurvey, 10);
+	}
+#endif /* CONFIG_P2P */
+
+	if (rtw_rfctl_is_tx_blocked_by_ch_waiting(adapter_to_rfctl(padapter)))
+		goto exit;
+
+	pmgntframe = alloc_mgtxmitframe(pxmitpriv);
+	if (pmgntframe == NULL)
+		goto exit;
+
+	/* update attribute */
+	pattrib = &pmgntframe->attrib;
+	update_mgntframe_attrib(padapter, pattrib);
+	pattrib->retry_ctrl = _FALSE;
+	pattrib->key_type = key_type;
+	_rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET);
+
+	pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET;
+	pwlanhdr = (struct rtw_ieee80211_hdr *)pframe;
+
+	fctrl = &(pwlanhdr->frame_ctl);
+	*(fctrl) = 0;
+
+	_rtw_memcpy(pwlanhdr->addr1, da, ETH_ALEN);
+	_rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN);
+	_rtw_memcpy(pwlanhdr->addr3, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN);
+
+	SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq);
+	pmlmeext->mgnt_seq++;
+	set_frame_sub_type(pframe, WIFI_DEAUTH);
+
+	pframe += sizeof(struct rtw_ieee80211_hdr_3addr);
+	pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr);
+
+	reason = cpu_to_le16(reason);
+	pframe = rtw_set_fixed_ie(pframe, _RSON_CODE_ , (unsigned char *)&reason, &(pattrib->pktlen));
+
+	pattrib->last_txcmdsz = pattrib->pktlen;
+
+
+	if (wait_ack)
+		ret = dump_mgntframe_and_wait_ack(padapter, pmgntframe);
+	else {
+		dump_mgntframe(padapter, pmgntframe);
+		ret = _SUCCESS;
+	}
+
+exit:
+	return ret;
+}
+
+int issue_deauth(_adapter *padapter, unsigned char *da, unsigned short reason)
+{
+	RTW_INFO("%s to "MAC_FMT"\n", __func__, MAC_ARG(da));
+	return _issue_deauth(padapter, da, reason, _FALSE, IEEE80211W_RIGHT_KEY);
+}
+
+#ifdef CONFIG_IEEE80211W
+int issue_deauth_11w(_adapter *padapter, unsigned char *da, unsigned short reason, u8 key_type)
+{
+	RTW_INFO("%s to "MAC_FMT"\n", __func__, MAC_ARG(da));
+	return _issue_deauth(padapter, da, reason, _FALSE, key_type);
+}
+#endif /* CONFIG_IEEE80211W */
+
+/*
+ * wait_ms == 0 means that there is no need to wait ack through C2H_CCX_TX_RPT
+ * wait_ms > 0 means you want to wait ack through C2H_CCX_TX_RPT, and the value of wait_ms means the interval between each TX
+ * try_cnt means the maximal TX count to try
+ */
+int issue_deauth_ex(_adapter *padapter, u8 *da, unsigned short reason, int try_cnt,
+		    int wait_ms)
+{
+	int ret = _FAIL;
+	int i = 0;
+	systime start = rtw_get_current_time();
+
+	if (rtw_rfctl_is_tx_blocked_by_ch_waiting(adapter_to_rfctl(padapter)))
+		goto exit;
+
+	do {
+		ret = _issue_deauth(padapter, da, reason, wait_ms > 0 ? _TRUE : _FALSE, IEEE80211W_RIGHT_KEY);
+
+		i++;
+
+		if (RTW_CANNOT_RUN(padapter))
+			break;
+
+		if (i < try_cnt && wait_ms > 0 && ret == _FAIL)
+			rtw_msleep_os(wait_ms);
+
+	} while ((i < try_cnt) && ((ret == _FAIL) || (wait_ms == 0)));
+
+	if (ret != _FAIL) {
+		ret = _SUCCESS;
+#ifndef DBG_XMIT_ACK
+		goto exit;
+#endif
+	}
+
+	if (try_cnt && wait_ms) {
+		if (da)
+			RTW_INFO(FUNC_ADPT_FMT" to "MAC_FMT", ch:%u%s, %d/%d in %u ms\n",
+				FUNC_ADPT_ARG(padapter), MAC_ARG(da), rtw_get_oper_ch(padapter),
+				ret == _SUCCESS ? ", acked" : "", i, try_cnt, rtw_get_passing_time_ms(start));
+		else
+			RTW_INFO(FUNC_ADPT_FMT", ch:%u%s, %d/%d in %u ms\n",
+				FUNC_ADPT_ARG(padapter), rtw_get_oper_ch(padapter),
+				ret == _SUCCESS ? ", acked" : "", i, try_cnt, rtw_get_passing_time_ms(start));
+	}
+exit:
+	return ret;
+}
+
+void issue_action_spct_ch_switch(_adapter *padapter, u8 *ra, u8 new_ch, u8 ch_offset)
+{
+	struct xmit_frame *pmgntframe;
+	struct pkt_attrib *pattrib;
+	unsigned char				*pframe;
+	struct rtw_ieee80211_hdr	*pwlanhdr;
+	unsigned short			*fctrl;
+	struct xmit_priv			*pxmitpriv = &(padapter->xmitpriv);
+	struct mlme_ext_priv	*pmlmeext = &(padapter->mlmeextpriv);
+
+	if (rtw_rfctl_is_tx_blocked_by_ch_waiting(adapter_to_rfctl(padapter)))
+		return;
+
+	RTW_INFO(FUNC_NDEV_FMT" ra="MAC_FMT", ch:%u, offset:%u\n",
+		FUNC_NDEV_ARG(padapter->pnetdev), MAC_ARG(ra), new_ch, ch_offset);
+
+	pmgntframe = alloc_mgtxmitframe(pxmitpriv);
+	if (pmgntframe == NULL)
+		return;
+
+	/* update attribute */
+	pattrib = &pmgntframe->attrib;
+	update_mgntframe_attrib(padapter, pattrib);
+
+	_rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET);
+
+	pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET;
+	pwlanhdr = (struct rtw_ieee80211_hdr *)pframe;
+
+	fctrl = &(pwlanhdr->frame_ctl);
+	*(fctrl) = 0;
+
+	_rtw_memcpy(pwlanhdr->addr1, ra, ETH_ALEN); /* RA */
+	_rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN); /* TA */
+	_rtw_memcpy(pwlanhdr->addr3, ra, ETH_ALEN); /* DA = RA */
+
+	SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq);
+	pmlmeext->mgnt_seq++;
+	set_frame_sub_type(pframe, WIFI_ACTION);
+
+	pframe += sizeof(struct rtw_ieee80211_hdr_3addr);
+	pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr);
+
+	/* category, action */
+	{
+		u8 category, action;
+		category = RTW_WLAN_CATEGORY_SPECTRUM_MGMT;
+		action = RTW_WLAN_ACTION_SPCT_CHL_SWITCH;
+
+		pframe = rtw_set_fixed_ie(pframe, 1, &(category), &(pattrib->pktlen));
+		pframe = rtw_set_fixed_ie(pframe, 1, &(action), &(pattrib->pktlen));
+	}
+
+	pframe = rtw_set_ie_ch_switch(pframe, &(pattrib->pktlen), 0, new_ch, 0);
+	pframe = rtw_set_ie_secondary_ch_offset(pframe, &(pattrib->pktlen),
+			hal_ch_offset_to_secondary_ch_offset(ch_offset));
+
+	pattrib->last_txcmdsz = pattrib->pktlen;
+
+	dump_mgntframe(padapter, pmgntframe);
+
+}
+
+#ifdef CONFIG_IEEE80211W
+void issue_action_SA_Query(_adapter *padapter, unsigned char *raddr, unsigned char action, unsigned short tid, u8 key_type)
+{
+	u8	category = RTW_WLAN_CATEGORY_SA_QUERY;
+	u16	reason_code;
+	struct xmit_frame		*pmgntframe;
+	struct pkt_attrib		*pattrib;
+	u8					*pframe;
+	struct rtw_ieee80211_hdr	*pwlanhdr;
+	u16					*fctrl;
+	struct xmit_priv		*pxmitpriv = &(padapter->xmitpriv);
+	struct mlme_ext_priv	*pmlmeext = &(padapter->mlmeextpriv);
+	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
+	struct sta_info		*psta;
+	struct sta_priv		*pstapriv = &padapter->stapriv;
+	struct registry_priv		*pregpriv = &padapter->registrypriv;
+	struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
+
+	if (rtw_rfctl_is_tx_blocked_by_ch_waiting(adapter_to_rfctl(padapter)))
+		return;
+
+	RTW_INFO("%s, %04x\n", __FUNCTION__, tid);
+
+	pmgntframe = alloc_mgtxmitframe(pxmitpriv);
+	if (pmgntframe == NULL) {
+		RTW_INFO("%s: alloc_mgtxmitframe fail\n", __FUNCTION__);
+		return;
+	}
+
+	/* update attribute */
+	pattrib = &pmgntframe->attrib;
+	update_mgntframe_attrib(padapter, pattrib);
+	pattrib->key_type = key_type;
+	_rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET);
+
+	pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET;
+	pwlanhdr = (struct rtw_ieee80211_hdr *)pframe;
+
+	fctrl = &(pwlanhdr->frame_ctl);
+	*(fctrl) = 0;
+
+	if (raddr)
+		_rtw_memcpy(pwlanhdr->addr1, raddr, ETH_ALEN);
+	else
+		_rtw_memcpy(pwlanhdr->addr1, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN);
+	_rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN);
+	_rtw_memcpy(pwlanhdr->addr3, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN);
+
+	SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq);
+	pmlmeext->mgnt_seq++;
+	set_frame_sub_type(pframe, WIFI_ACTION);
+
+	pframe += sizeof(struct rtw_ieee80211_hdr_3addr);
+	pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr);
+
+	pframe = rtw_set_fixed_ie(pframe, 1, &category, &pattrib->pktlen);
+	pframe = rtw_set_fixed_ie(pframe, 1, &action, &pattrib->pktlen);
+
+	switch (action) {
+	case 0: /* SA Query req */
+		pframe = rtw_set_fixed_ie(pframe, 2, (unsigned char *)&pmlmeext->sa_query_seq, &pattrib->pktlen);
+		pmlmeext->sa_query_seq++;
+		/* send sa query request to AP, AP should reply sa query response in 1 second */
+		if (pattrib->key_type == IEEE80211W_RIGHT_KEY) {
+			psta = rtw_get_stainfo(pstapriv, pwlanhdr->addr1);
+			if (psta != NULL) {
+				/* RTW_INFO("%s, %d, set dot11w_expire_timer\n", __func__, __LINE__); */
+				_set_timer(&psta->dot11w_expire_timer, 1000);
+			}
+		}
+		break;
+
+	case 1: /* SA Query rsp */
+		tid = cpu_to_le16(tid);
+		/* RTW_INFO("rtw_set_fixed_ie, %04x\n", tid); */
+		pframe = rtw_set_fixed_ie(pframe, 2, (unsigned char *)&tid, &pattrib->pktlen);
+		break;
+	default:
+		break;
+	}
+
+	pattrib->last_txcmdsz = pattrib->pktlen;
+
+	dump_mgntframe(padapter, pmgntframe);
+}
+#endif /* CONFIG_IEEE80211W */
+
+/**
+ * issue_action_ba - internal function to TX Block Ack action frame
+ * @padapter: the adapter to TX
+ * @raddr: receiver address
+ * @action: Block Ack Action
+ * @tid: tid
+ * @size: the announced AMPDU buffer size. used by ADDBA_RESP
+ * @status: status/reason code. used by ADDBA_RESP, DELBA
+ * @initiator: if we are the initiator of AMPDU association. used by DELBA
+ * @wait_ack: used xmit ack
+ *
+ * Returns:
+ * _SUCCESS: No xmit ack is used or acked
+ * _FAIL: not acked when using xmit ack
+ */
+static int issue_action_ba(_adapter *padapter, unsigned char *raddr, unsigned char action
+		   , u8 tid, u8 size, u16 status, u8 initiator, int wait_ack)
+{
+	int ret = _FAIL;
+	u8	category = RTW_WLAN_CATEGORY_BACK;
+	u16	start_seq;
+	u16	BA_para_set;
+	u16	BA_timeout_value;
+	u16	BA_starting_seqctrl;
+	struct xmit_frame		*pmgntframe;
+	struct pkt_attrib		*pattrib;
+	u8					*pframe;
+	struct rtw_ieee80211_hdr	*pwlanhdr;
+	u16					*fctrl;
+	struct xmit_priv		*pxmitpriv = &(padapter->xmitpriv);
+	struct mlme_ext_priv	*pmlmeext = &(padapter->mlmeextpriv);
+	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
+	struct sta_info		*psta;
+	struct sta_priv		*pstapriv = &padapter->stapriv;
+	struct registry_priv		*pregpriv = &padapter->registrypriv;
+
+#ifdef CONFIG_80211N_HT
+
+	if (rtw_rfctl_is_tx_blocked_by_ch_waiting(adapter_to_rfctl(padapter)))
+		goto exit;
+
+	pmgntframe = alloc_mgtxmitframe(pxmitpriv);
+	if (pmgntframe == NULL)
+		goto exit;
+
+	/* update attribute */
+	pattrib = &pmgntframe->attrib;
+	update_mgntframe_attrib(padapter, pattrib);
+
+	_rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET);
+
+	pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET;
+	pwlanhdr = (struct rtw_ieee80211_hdr *)pframe;
+
+	fctrl = &(pwlanhdr->frame_ctl);
+	*(fctrl) = 0;
+
+	/* _rtw_memcpy(pwlanhdr->addr1, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN); */
+	_rtw_memcpy(pwlanhdr->addr1, raddr, ETH_ALEN);
+	_rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN);
+	_rtw_memcpy(pwlanhdr->addr3, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN);
+
+	SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq);
+	pmlmeext->mgnt_seq++;
+	set_frame_sub_type(pframe, WIFI_ACTION);
+
+	pframe += sizeof(struct rtw_ieee80211_hdr_3addr);
+	pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr);
+
+	pframe = rtw_set_fixed_ie(pframe, 1, &(category), &(pattrib->pktlen));
+	pframe = rtw_set_fixed_ie(pframe, 1, &(action), &(pattrib->pktlen));
+
+	if (category == 3) {
+		switch (action) {
+		case RTW_WLAN_ACTION_ADDBA_REQ:
+			do {
+				pmlmeinfo->dialogToken++;
+			} while (pmlmeinfo->dialogToken == 0);
+			pframe = rtw_set_fixed_ie(pframe, 1, &(pmlmeinfo->dialogToken), &(pattrib->pktlen));
+
+#if defined(CONFIG_RTL8188E) && defined(CONFIG_SDIO_HCI)
+			BA_para_set = (0x0802 | ((tid & 0xf) << 2)); /* immediate ack & 16 buffer size */
+#else
+			BA_para_set = (0x1002 | ((tid & 0xf) << 2)); /* immediate ack & 64 buffer size */
+#endif
+
+#ifdef CONFIG_TX_AMSDU
+			if (padapter->tx_amsdu >= 1) /* TX AMSDU  enabled */
+				BA_para_set |= BIT(0);
+			else /* TX AMSDU disabled */
+				BA_para_set &= ~BIT(0);
+#endif
+			BA_para_set = cpu_to_le16(BA_para_set);
+			pframe = rtw_set_fixed_ie(pframe, 2, (unsigned char *)(&(BA_para_set)), &(pattrib->pktlen));
+
+			/* BA_timeout_value = 0xffff; */ /* max: 65535 TUs(~ 65 ms) */
+			BA_timeout_value = 5000;/* ~ 5ms */
+			BA_timeout_value = cpu_to_le16(BA_timeout_value);
+			pframe = rtw_set_fixed_ie(pframe, 2, (unsigned char *)(&(BA_timeout_value)), &(pattrib->pktlen));
+
+			/* if ((psta = rtw_get_stainfo(pstapriv, pmlmeinfo->network.MacAddress)) != NULL) */
+			psta = rtw_get_stainfo(pstapriv, raddr);
+			if (psta != NULL) {
+				start_seq = (psta->sta_xmitpriv.txseq_tid[tid & 0x07] & 0xfff) + 1;
+
+				RTW_INFO("BA_starting_seqctrl = %d for TID=%d\n", start_seq, tid & 0x07);
+
+				psta->BA_starting_seqctrl[tid & 0x07] = start_seq;
+
+				BA_starting_seqctrl = start_seq << 4;
+			}
+
+			BA_starting_seqctrl = cpu_to_le16(BA_starting_seqctrl);
+			pframe = rtw_set_fixed_ie(pframe, 2, (unsigned char *)(&(BA_starting_seqctrl)), &(pattrib->pktlen));
+			break;
+
+		case RTW_WLAN_ACTION_ADDBA_RESP:
+			pframe = rtw_set_fixed_ie(pframe, 1, &(pmlmeinfo->ADDBA_req.dialog_token), &(pattrib->pktlen));
+			status = cpu_to_le16(status);
+			pframe = rtw_set_fixed_ie(pframe, 2, (unsigned char *)(&status), &(pattrib->pktlen));
+
+			BA_para_set = le16_to_cpu(pmlmeinfo->ADDBA_req.BA_para_set);
+
+			BA_para_set &= ~IEEE80211_ADDBA_PARAM_TID_MASK;
+			BA_para_set |= (tid << 2) & IEEE80211_ADDBA_PARAM_TID_MASK;
+
+			BA_para_set &= ~RTW_IEEE80211_ADDBA_PARAM_BUF_SIZE_MASK;
+			BA_para_set |= (size << 6) & RTW_IEEE80211_ADDBA_PARAM_BUF_SIZE_MASK;
+
+			if (!padapter->registrypriv.wifi_spec) {
+				if (pregpriv->rx_ampdu_amsdu == 0) /* disabled */
+					BA_para_set &= ~BIT(0);
+				else if (pregpriv->rx_ampdu_amsdu == 1) /* enabled */
+					BA_para_set |= BIT(0);
+			}
+
+			BA_para_set = cpu_to_le16(BA_para_set);
+
+			pframe = rtw_set_fixed_ie(pframe, 2, (unsigned char *)(&(BA_para_set)), &(pattrib->pktlen));
+			pframe = rtw_set_fixed_ie(pframe, 2, (unsigned char *)(&(pmlmeinfo->ADDBA_req.BA_timeout_value)), &(pattrib->pktlen));
+			break;
+
+		case RTW_WLAN_ACTION_DELBA:
+			BA_para_set = 0;
+			BA_para_set |= (tid << 12) & IEEE80211_DELBA_PARAM_TID_MASK;
+			BA_para_set |= (initiator << 11) & IEEE80211_DELBA_PARAM_INITIATOR_MASK;
+
+			BA_para_set = cpu_to_le16(BA_para_set);
+			pframe = rtw_set_fixed_ie(pframe, 2, (unsigned char *)(&(BA_para_set)), &(pattrib->pktlen));
+			status = cpu_to_le16(status);
+			pframe = rtw_set_fixed_ie(pframe, 2, (unsigned char *)(&(status)), &(pattrib->pktlen));
+			break;
+		default:
+			break;
+		}
+	}
+
+	pattrib->last_txcmdsz = pattrib->pktlen;
+
+	if (wait_ack)
+		ret = dump_mgntframe_and_wait_ack(padapter, pmgntframe);
+	else {
+		dump_mgntframe(padapter, pmgntframe);
+		ret = _SUCCESS;
+	}
+
+exit:
+#endif /* CONFIG_80211N_HT */
+	return ret;
+}
+
+/**
+ * issue_addba_req - TX ADDBA_REQ
+ * @adapter: the adapter to TX
+ * @ra: receiver address
+ * @tid: tid
+ */
+inline void issue_addba_req(_adapter *adapter, unsigned char *ra, u8 tid)
+{
+	issue_action_ba(adapter, ra, RTW_WLAN_ACTION_ADDBA_REQ
+			, tid
+			, 0 /* unused */
+			, 0 /* unused */
+			, 0 /* unused */
+			, _FALSE
+		       );
+	RTW_INFO(FUNC_ADPT_FMT" ra="MAC_FMT" tid=%u\n"
+		 , FUNC_ADPT_ARG(adapter), MAC_ARG(ra), tid);
+
+}
+
+/**
+ * issue_addba_rsp - TX ADDBA_RESP
+ * @adapter: the adapter to TX
+ * @ra: receiver address
+ * @tid: tid
+ * @status: status code
+ * @size: the announced AMPDU buffer size
+ */
+inline void issue_addba_rsp(_adapter *adapter, unsigned char *ra, u8 tid, u16 status, u8 size)
+{
+	issue_action_ba(adapter, ra, RTW_WLAN_ACTION_ADDBA_RESP
+			, tid
+			, size
+			, status
+			, 0 /* unused */
+			, _FALSE
+		       );
+	RTW_INFO(FUNC_ADPT_FMT" ra="MAC_FMT" status=%u, tid=%u, size=%u\n"
+		 , FUNC_ADPT_ARG(adapter), MAC_ARG(ra), status, tid, size);
+}
+
+/**
+ * issue_addba_rsp_wait_ack - TX ADDBA_RESP and wait ack
+ * @adapter: the adapter to TX
+ * @ra: receiver address
+ * @tid: tid
+ * @status: status code
+ * @size: the announced AMPDU buffer size
+ * @try_cnt: the maximal TX count to try
+ * @wait_ms: == 0 means that there is no need to wait ack through C2H_CCX_TX_RPT
+ *           > 0 means you want to wait ack through C2H_CCX_TX_RPT, and the value of wait_ms means the interval between each TX
+ */
+inline u8 issue_addba_rsp_wait_ack(_adapter *adapter, unsigned char *ra, u8 tid, u16 status, u8 size, int try_cnt, int wait_ms)
+{
+	int ret = _FAIL;
+	int i = 0;
+	systime start = rtw_get_current_time();
+
+	if (rtw_rfctl_is_tx_blocked_by_ch_waiting(adapter_to_rfctl(adapter)))
+		goto exit;
+
+	do {
+		ret = issue_action_ba(adapter, ra, RTW_WLAN_ACTION_ADDBA_RESP
+				      , tid
+				      , size
+				      , status
+				      , 0 /* unused */
+				      , _TRUE
+				     );
+
+		i++;
+
+		if (RTW_CANNOT_RUN(adapter))
+			break;
+
+		if (i < try_cnt && wait_ms > 0 && ret == _FAIL)
+			rtw_msleep_os(wait_ms);
+
+	} while ((i < try_cnt) && ((ret == _FAIL) || (wait_ms == 0)));
+
+	if (ret != _FAIL) {
+		ret = _SUCCESS;
+#ifndef DBG_XMIT_ACK
+		/* goto exit; */
+#endif
+	}
+
+	if (try_cnt && wait_ms) {
+		RTW_INFO(FUNC_ADPT_FMT" ra="MAC_FMT" status:=%u tid=%u size:%u%s, %d/%d in %u ms\n"
+			, FUNC_ADPT_ARG(adapter), MAC_ARG(ra), status, tid, size
+			, ret == _SUCCESS ? ", acked" : "", i, try_cnt, rtw_get_passing_time_ms(start));
+	}
+
+exit:
+	return ret;
+}
+
+/**
+ * issue_del_ba - TX DELBA
+ * @adapter: the adapter to TX
+ * @ra: receiver address
+ * @tid: tid
+ * @reason: reason code
+ * @initiator: if we are the initiator of AMPDU association. used by DELBA
+ */
+inline void issue_del_ba(_adapter *adapter, unsigned char *ra, u8 tid, u16 reason, u8 initiator)
+{
+	issue_action_ba(adapter, ra, RTW_WLAN_ACTION_DELBA
+			, tid
+			, 0 /* unused */
+			, reason
+			, initiator
+			, _FALSE
+		       );
+	RTW_INFO(FUNC_ADPT_FMT" ra="MAC_FMT" reason=%u, tid=%u, initiator=%u\n"
+		 , FUNC_ADPT_ARG(adapter), MAC_ARG(ra), reason, tid, initiator);
+}
+
+/**
+ * issue_del_ba_ex - TX DELBA with xmit ack options
+ * @adapter: the adapter to TX
+ * @ra: receiver address
+ * @tid: tid
+ * @reason: reason code
+ * @initiator: if we are the initiator of AMPDU association. used by DELBA
+ * @try_cnt: the maximal TX count to try
+ * @wait_ms: == 0 means that there is no need to wait ack through C2H_CCX_TX_RPT
+ *           > 0 means you want to wait ack through C2H_CCX_TX_RPT, and the value of wait_ms means the interval between each TX
+ */
+int issue_del_ba_ex(_adapter *adapter, unsigned char *ra, u8 tid, u16 reason, u8 initiator
+		    , int try_cnt, int wait_ms)
+{
+	int ret = _FAIL;
+	int i = 0;
+	systime start = rtw_get_current_time();
+
+	if (rtw_rfctl_is_tx_blocked_by_ch_waiting(adapter_to_rfctl(adapter)))
+		goto exit;
+
+	do {
+		ret = issue_action_ba(adapter, ra, RTW_WLAN_ACTION_DELBA
+				      , tid
+				      , 0 /* unused */
+				      , reason
+				      , initiator
+				      , wait_ms > 0 ? _TRUE : _FALSE
+				     );
+
+		i++;
+
+		if (RTW_CANNOT_RUN(adapter))
+			break;
+
+		if (i < try_cnt && wait_ms > 0 && ret == _FAIL)
+			rtw_msleep_os(wait_ms);
+
+	} while ((i < try_cnt) && ((ret == _FAIL) || (wait_ms == 0)));
+
+	if (ret != _FAIL) {
+		ret = _SUCCESS;
+#ifndef DBG_XMIT_ACK
+		/* goto exit; */
+#endif
+	}
+
+	if (try_cnt && wait_ms) {
+		RTW_INFO(FUNC_ADPT_FMT" ra="MAC_FMT" reason=%u, tid=%u, initiator=%u%s, %d/%d in %u ms\n"
+			, FUNC_ADPT_ARG(adapter), MAC_ARG(ra), reason, tid, initiator
+			, ret == _SUCCESS ? ", acked" : "", i, try_cnt, rtw_get_passing_time_ms(start));
+	}
+exit:
+	return ret;
+}
+
+void issue_action_BSSCoexistPacket(_adapter *padapter)
+{
+	_irqL	irqL;
+	_list		*plist, *phead;
+	unsigned char category, action;
+	struct xmit_frame			*pmgntframe;
+	struct pkt_attrib			*pattrib;
+	unsigned char				*pframe;
+	struct rtw_ieee80211_hdr	*pwlanhdr;
+	unsigned short			*fctrl;
+	struct	wlan_network	*pnetwork = NULL;
+	struct xmit_priv			*pxmitpriv = &(padapter->xmitpriv);
+	struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
+	struct mlme_ext_priv	*pmlmeext = &(padapter->mlmeextpriv);
+	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
+	_queue		*queue	= &(pmlmepriv->scanned_queue);
+	u8 InfoContent[16] = {0};
+	u8 ICS[8][15];
+#ifdef CONFIG_80211N_HT
+	if ((pmlmepriv->num_FortyMHzIntolerant == 0) || (pmlmepriv->num_sta_no_ht == 0))
+		return;
+
+	if (_TRUE == pmlmeinfo->bwmode_updated)
+		return;
+
+	if (rtw_rfctl_is_tx_blocked_by_ch_waiting(adapter_to_rfctl(padapter)))
+		return;
+
+	RTW_INFO("%s\n", __FUNCTION__);
+
+
+	category = RTW_WLAN_CATEGORY_PUBLIC;
+	action = ACT_PUBLIC_BSSCOEXIST;
+
+	pmgntframe = alloc_mgtxmitframe(pxmitpriv);
+	if (pmgntframe == NULL)
+		return;
+
+	/* update attribute */
+	pattrib = &pmgntframe->attrib;
+	update_mgntframe_attrib(padapter, pattrib);
+
+	_rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET);
+
+	pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET;
+	pwlanhdr = (struct rtw_ieee80211_hdr *)pframe;
+
+	fctrl = &(pwlanhdr->frame_ctl);
+	*(fctrl) = 0;
+
+	_rtw_memcpy(pwlanhdr->addr1, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN);
+	_rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN);
+	_rtw_memcpy(pwlanhdr->addr3, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN);
+
+	SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq);
+	pmlmeext->mgnt_seq++;
+	set_frame_sub_type(pframe, WIFI_ACTION);
+
+	pframe += sizeof(struct rtw_ieee80211_hdr_3addr);
+	pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr);
+
+	pframe = rtw_set_fixed_ie(pframe, 1, &(category), &(pattrib->pktlen));
+	pframe = rtw_set_fixed_ie(pframe, 1, &(action), &(pattrib->pktlen));
+
+
+	/*  */
+	if (pmlmepriv->num_FortyMHzIntolerant > 0) {
+		u8 iedata = 0;
+
+		iedata |= BIT(2);/* 20 MHz BSS Width Request */
+
+		pframe = rtw_set_ie(pframe, EID_BSSCoexistence,  1, &iedata, &(pattrib->pktlen));
+
+	}
+
+
+	/*  */
+	_rtw_memset(ICS, 0, sizeof(ICS));
+	if (pmlmepriv->num_sta_no_ht > 0) {
+		int i;
+
+		_enter_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);
+
+		phead = get_list_head(queue);
+		plist = get_next(phead);
+
+		while (1) {
+			int len;
+			u8 *p;
+			WLAN_BSSID_EX *pbss_network;
+
+			if (rtw_end_of_queue_search(phead, plist) == _TRUE)
+				break;
+
+			pnetwork = LIST_CONTAINOR(plist, struct wlan_network, list);
+
+			plist = get_next(plist);
+
+			pbss_network = (WLAN_BSSID_EX *)&pnetwork->network;
+
+			p = rtw_get_ie(pbss_network->IEs + _FIXED_IE_LENGTH_, _HT_CAPABILITY_IE_, &len, pbss_network->IELength - _FIXED_IE_LENGTH_);
+			if ((p == NULL) || (len == 0)) { /* non-HT */
+				if ((pbss_network->Configuration.DSConfig <= 0) || (pbss_network->Configuration.DSConfig > 14))
+					continue;
+
+				ICS[0][pbss_network->Configuration.DSConfig] = 1;
+
+				if (ICS[0][0] == 0)
+					ICS[0][0] = 1;
+			}
+
+		}
+
+		_exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);
+
+
+		for (i = 0; i < 8; i++) {
+			if (ICS[i][0] == 1) {
+				int j, k = 0;
+
+				InfoContent[k] = i;
+				/* SET_BSS_INTOLERANT_ELE_REG_CLASS(InfoContent,i); */
+				k++;
+
+				for (j = 1; j <= 14; j++) {
+					if (ICS[i][j] == 1) {
+						if (k < 16) {
+							InfoContent[k] = j; /* channel number */
+							/* SET_BSS_INTOLERANT_ELE_CHANNEL(InfoContent+k, j); */
+							k++;
+						}
+					}
+				}
+
+				pframe = rtw_set_ie(pframe, EID_BSSIntolerantChlReport, k, InfoContent, &(pattrib->pktlen));
+
+			}
+
+		}
+
+
+	}
+
+
+	pattrib->last_txcmdsz = pattrib->pktlen;
+
+	dump_mgntframe(padapter, pmgntframe);
+#endif /* CONFIG_80211N_HT */
+}
+
+/* Spatial Multiplexing Powersave (SMPS) action frame */
+int _issue_action_SM_PS(_adapter *padapter ,  unsigned char *raddr , u8 NewMimoPsMode ,  u8 wait_ack)
+{
+
+	int ret = _FAIL;
+	unsigned char category = RTW_WLAN_CATEGORY_HT;
+	u8 action = RTW_WLAN_ACTION_HT_SM_PS;
+	u8 sm_power_control = 0;
+	struct xmit_frame			*pmgntframe;
+	struct pkt_attrib			*pattrib;
+	unsigned char					*pframe;
+	struct rtw_ieee80211_hdr	*pwlanhdr;
+	unsigned short				*fctrl;
+	struct xmit_priv			*pxmitpriv = &(padapter->xmitpriv);
+	struct mlme_ext_priv	*pmlmeext = &(padapter->mlmeextpriv);
+	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
+
+
+	if (NewMimoPsMode == WLAN_HT_CAP_SM_PS_DISABLED) {
+		sm_power_control = sm_power_control  & ~(BIT(0)); /* SM Power Save Enable = 0 SM Power Save Disable */
+	} else if (NewMimoPsMode == WLAN_HT_CAP_SM_PS_STATIC) {
+		sm_power_control = sm_power_control | BIT(0);    /* SM Power Save Enable = 1 SM Power Save Enable  */
+		sm_power_control = sm_power_control & ~(BIT(1)); /* SM Mode = 0 Static Mode */
+	} else if (NewMimoPsMode == WLAN_HT_CAP_SM_PS_DYNAMIC) {
+		sm_power_control = sm_power_control | BIT(0); /* SM Power Save Enable = 1 SM Power Save Enable  */
+		sm_power_control = sm_power_control | BIT(1); /* SM Mode = 1 Dynamic Mode */
+	} else
+		return ret;
+
+	if (rtw_rfctl_is_tx_blocked_by_ch_waiting(adapter_to_rfctl(padapter)))
+		return ret;
+
+	RTW_INFO("%s, sm_power_control=%u, NewMimoPsMode=%u\n", __FUNCTION__ , sm_power_control , NewMimoPsMode);
+
+	pmgntframe = alloc_mgtxmitframe(pxmitpriv);
+	if (pmgntframe == NULL)
+		return ret;
+
+	/* update attribute */
+	pattrib = &pmgntframe->attrib;
+	update_mgntframe_attrib(padapter, pattrib);
+
+	_rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET);
+
+	pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET;
+	pwlanhdr = (struct rtw_ieee80211_hdr *)pframe;
+
+	fctrl = &(pwlanhdr->frame_ctl);
+	*(fctrl) = 0;
+
+	_rtw_memcpy(pwlanhdr->addr1, raddr, ETH_ALEN); /* RA */
+	_rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN); /* TA */
+	_rtw_memcpy(pwlanhdr->addr3, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN); /* DA = RA */
+
+	SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq);
+	pmlmeext->mgnt_seq++;
+	set_frame_sub_type(pframe, WIFI_ACTION);
+
+	pframe += sizeof(struct rtw_ieee80211_hdr_3addr);
+	pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr);
+
+	/* category, action */
+	pframe = rtw_set_fixed_ie(pframe, 1, &(category), &(pattrib->pktlen));
+	pframe = rtw_set_fixed_ie(pframe, 1, &(action), &(pattrib->pktlen));
+
+	pframe = rtw_set_fixed_ie(pframe, 1, &(sm_power_control), &(pattrib->pktlen));
+
+	pattrib->last_txcmdsz = pattrib->pktlen;
+
+	if (wait_ack)
+		ret = dump_mgntframe_and_wait_ack(padapter, pmgntframe);
+	else {
+		dump_mgntframe(padapter, pmgntframe);
+		ret = _SUCCESS;
+	}
+
+	if (ret != _SUCCESS)
+		RTW_INFO("%s, ack to\n", __func__);
+
+	return ret;
+}
+
+/*
+ * wait_ms == 0 means that there is no need to wait ack through C2H_CCX_TX_RPT
+ * wait_ms > 0 means you want to wait ack through C2H_CCX_TX_RPT, and the value of wait_ms means the interval between each TX
+ * try_cnt means the maximal TX count to try
+ */
+int issue_action_SM_PS_wait_ack(_adapter *padapter, unsigned char *raddr, u8 NewMimoPsMode, int try_cnt, int wait_ms)
+{
+	int ret = _FAIL;
+	int i = 0;
+	systime start = rtw_get_current_time();
+
+	if (rtw_rfctl_is_tx_blocked_by_ch_waiting(adapter_to_rfctl(padapter)))
+		goto exit;
+
+	do {
+		ret = _issue_action_SM_PS(padapter, raddr, NewMimoPsMode , wait_ms > 0 ? _TRUE : _FALSE);
+
+		i++;
+
+		if (RTW_CANNOT_RUN(padapter))
+			break;
+
+		if (i < try_cnt && wait_ms > 0 && ret == _FAIL)
+			rtw_msleep_os(wait_ms);
+
+	} while ((i < try_cnt) && ((ret == _FAIL) || (wait_ms == 0)));
+
+	if (ret != _FAIL) {
+		ret = _SUCCESS;
+#ifndef DBG_XMIT_ACK
+		goto exit;
+#endif
+	}
+
+	if (try_cnt && wait_ms) {
+		if (raddr)
+			RTW_INFO(FUNC_ADPT_FMT" to "MAC_FMT", %s , %d/%d in %u ms\n",
+				 FUNC_ADPT_ARG(padapter), MAC_ARG(raddr),
+				ret == _SUCCESS ? ", acked" : "", i, try_cnt, rtw_get_passing_time_ms(start));
+		else
+			RTW_INFO(FUNC_ADPT_FMT", %s , %d/%d in %u ms\n",
+				 FUNC_ADPT_ARG(padapter),
+				ret == _SUCCESS ? ", acked" : "", i, try_cnt, rtw_get_passing_time_ms(start));
+	}
+exit:
+
+	return ret;
+}
+
+int issue_action_SM_PS(_adapter *padapter ,  unsigned char *raddr , u8 NewMimoPsMode)
+{
+	RTW_INFO("%s to "MAC_FMT"\n", __func__, MAC_ARG(raddr));
+	return _issue_action_SM_PS(padapter, raddr, NewMimoPsMode , _FALSE);
+}
+
+/**
+ * _send_delba_sta_tid - Cancel the AMPDU association for the specific @sta, @tid
+ * @adapter: the adapter to which @sta belongs
+ * @initiator: if we are the initiator of AMPDU association
+ * @sta: the sta to be checked
+ * @tid: the tid to be checked
+ * @force: cancel and send DELBA even when no AMPDU association is setup
+ * @wait_ack: send delba with xmit ack (valid when initiator == 0)
+ *
+ * Returns:
+ * _FAIL if sta is NULL
+ * when initiator is 1, always _SUCCESS
+ * when initiator is 0, _SUCCESS if DELBA is acked
+ */
+static unsigned int _send_delba_sta_tid(_adapter *adapter, u8 initiator, struct sta_info *sta, u8 tid
+					, u8 force, int wait_ack)
+{
+	int ret = _SUCCESS;
+
+	if (sta == NULL) {
+		ret = _FAIL;
+		goto exit;
+	}
+
+	if (initiator == 0) {
+		/* recipient */
+		if (force || sta->recvreorder_ctrl[tid].enable == _TRUE) {
+			u8 ampdu_size_bak = sta->recvreorder_ctrl[tid].ampdu_size;
+
+			sta->recvreorder_ctrl[tid].enable = _FALSE;
+			sta->recvreorder_ctrl[tid].ampdu_size = RX_AMPDU_SIZE_INVALID;
+
+			if (rtw_del_rx_ampdu_test_trigger_no_tx_fail())
+				ret = _FAIL;
+			else if (wait_ack)
+				ret = issue_del_ba_ex(adapter, sta->cmn.mac_addr, tid, 37, initiator, 3, 1);
+			else
+				issue_del_ba(adapter, sta->cmn.mac_addr, tid, 37, initiator);
+
+			if (ret == _FAIL && sta->recvreorder_ctrl[tid].enable == _FALSE)
+				sta->recvreorder_ctrl[tid].ampdu_size = ampdu_size_bak;
+		}
+	} else if (initiator == 1) {
+		/* originator */
+#ifdef CONFIG_80211N_HT
+		if (force || sta->htpriv.agg_enable_bitmap & BIT(tid)) {
+			sta->htpriv.agg_enable_bitmap &= ~BIT(tid);
+			sta->htpriv.candidate_tid_bitmap &= ~BIT(tid);
+			issue_del_ba(adapter, sta->cmn.mac_addr, tid, 37, initiator);
+		}
+#endif
+	}
+
+exit:
+	return ret;
+}
+
+inline unsigned int send_delba_sta_tid(_adapter *adapter, u8 initiator, struct sta_info *sta, u8 tid
+				       , u8 force)
+{
+	return _send_delba_sta_tid(adapter, initiator, sta, tid, force, 0);
+}
+
+inline unsigned int send_delba_sta_tid_wait_ack(_adapter *adapter, u8 initiator, struct sta_info *sta, u8 tid
+		, u8 force)
+{
+	return _send_delba_sta_tid(adapter, initiator, sta, tid, force, 1);
+}
+
+unsigned int send_delba(_adapter *padapter, u8 initiator, u8 *addr)
+{
+	struct sta_priv *pstapriv = &padapter->stapriv;
+	struct sta_info *psta = NULL;
+	struct mlme_ext_priv	*pmlmeext = &padapter->mlmeextpriv;
+	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
+	u16 tid;
+
+	if ((pmlmeinfo->state & 0x03) != WIFI_FW_AP_STATE)
+		if (!(pmlmeinfo->state & WIFI_FW_ASSOC_SUCCESS))
+			return _SUCCESS;
+
+	psta = rtw_get_stainfo(pstapriv, addr);
+	if (psta == NULL)
+		return _SUCCESS;
+
+#if 0
+	RTW_INFO("%s:%s\n", __func__, (initiator == 0) ? "RX_DIR" : "TX_DIR");
+	if (initiator == 1) /* originator */
+		RTW_INFO("tx agg_enable_bitmap(0x%08x)\n", psta->htpriv.agg_enable_bitmap);
+#endif
+
+	for (tid = 0; tid < TID_NUM; tid++)
+		send_delba_sta_tid(padapter, initiator, psta, tid, 0);
+
+	return _SUCCESS;
+}
+
+unsigned int send_beacon(_adapter *padapter)
+{
+#ifdef CONFIG_PCI_HCI
+	#ifdef CONFIG_FW_HANDLE_TXBCN
+	u8 vap_id = padapter->vap_id;
+
+	/* bypass TX BCN because vap_id is invalid*/
+	if (vap_id == CONFIG_LIMITED_AP_NUM)
+		return _SUCCESS;
+	#endif
+
+	/* bypass TX BCN queue because op ch is switching/waiting */
+	if (check_fwstate(&padapter->mlmepriv, WIFI_OP_CH_SWITCHING)
+		|| IS_CH_WAITING(adapter_to_rfctl(padapter))
+	)
+		return _SUCCESS;
+
+	/* RTW_INFO("%s\n", __FUNCTION__); */
+
+	rtw_hal_set_hwreg(padapter, HW_VAR_BCN_VALID, NULL);
+
+	/* 8192EE Port select for Beacon DL */
+	rtw_hal_set_hwreg(padapter, HW_VAR_DL_BCN_SEL, NULL);
+	#ifdef CONFIG_FW_HANDLE_TXBCN
+	rtw_hal_set_hwreg(padapter, HW_VAR_BCN_HEAD_SEL, &vap_id);
+	#endif
+
+	issue_beacon(padapter, 0);
+
+	#ifdef CONFIG_FW_HANDLE_TXBCN
+	vap_id = 0xFF;
+	rtw_hal_set_hwreg(padapter, HW_VAR_BCN_HEAD_SEL, &vap_id);
+	#endif
+
+	#ifdef RTL8814AE_SW_BCN
+	if (GET_HAL_DATA(padapter)->bCorrectBCN != 0)
+		RTW_INFO("%s, line%d, Warnning, pHalData->bCorrectBCN != 0\n", __func__, __LINE__);
+	GET_HAL_DATA(padapter)->bCorrectBCN = 1;
+	#endif
+
+	return _SUCCESS;
+#endif /*CONFIG_PCI_HCI*/
+
+#if defined(CONFIG_USB_HCI) || defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
+	u8 bxmitok = _FALSE;
+	int issue = 0;
+	int poll = 0;
+	systime start = rtw_get_current_time();
+	#ifdef CONFIG_FW_HANDLE_TXBCN
+	u8 vap_id = padapter->vap_id;
+
+	/* bypass TX BCN because vap_id is invalid*/
+	if (vap_id == CONFIG_LIMITED_AP_NUM)
+		return _SUCCESS;
+	#endif
+
+	/* bypass TX BCN queue because op ch is switching/waiting */
+	if (check_fwstate(&padapter->mlmepriv, WIFI_OP_CH_SWITCHING)
+		|| IS_CH_WAITING(adapter_to_rfctl(padapter))
+	)
+		return _SUCCESS;
+
+	#if defined(CONFIG_USB_HCI)
+	#if defined(CONFIG_RTL8812A)
+	if (IS_FULL_SPEED_USB(padapter)) {
+		issue_beacon(padapter, 300);
+		bxmitok = _TRUE;
+	} else
+	#endif
+	#endif
+	{
+		rtw_hal_set_hwreg(padapter, HW_VAR_BCN_VALID, NULL);
+		rtw_hal_set_hwreg(padapter, HW_VAR_DL_BCN_SEL, NULL);
+		#ifdef CONFIG_FW_HANDLE_TXBCN
+		rtw_hal_set_hwreg(padapter, HW_VAR_BCN_HEAD_SEL, &vap_id);
+		#endif
+		do {
+			issue_beacon(padapter, 100);
+			issue++;
+			do {
+				rtw_yield_os();
+				rtw_hal_get_hwreg(padapter, HW_VAR_BCN_VALID, (u8 *)(&bxmitok));
+				poll++;
+			} while ((poll % 10) != 0 && _FALSE == bxmitok && !RTW_CANNOT_RUN(padapter));
+
+		} while (bxmitok == _FALSE && (issue < 100) && !RTW_CANNOT_RUN(padapter));
+		#ifdef CONFIG_FW_HANDLE_TXBCN
+		vap_id = 0xFF;
+		rtw_hal_set_hwreg(padapter, HW_VAR_BCN_HEAD_SEL, &vap_id);
+		#endif
+	}
+	if (RTW_CANNOT_RUN(padapter))
+		return _FAIL;
+
+
+	if (_FALSE == bxmitok) {
+		RTW_INFO("%s fail! %u ms\n", __FUNCTION__, rtw_get_passing_time_ms(start));
+		#ifdef CONFIG_BCN_RECOVERY
+		GET_HAL_DATA(padapter)->issue_bcn_fail++;
+		#endif  /*CONFIG_BCN_RECOVERY*/
+		return _FAIL;
+	} else {
+		u32 passing_time = rtw_get_passing_time_ms(start);
+
+		if (passing_time > 100 || issue > 3)
+			RTW_INFO("%s success, issue:%d, poll:%d, %u ms\n", __FUNCTION__, issue, poll, rtw_get_passing_time_ms(start));
+		else if (0)
+			RTW_INFO("%s success, issue:%d, poll:%d, %u ms\n", __FUNCTION__, issue, poll, rtw_get_passing_time_ms(start));
+
+		#ifdef CONFIG_FW_CORRECT_BCN
+		rtw_hal_fw_correct_bcn(padapter);
+		#endif
+		return _SUCCESS;
+	}
+
+#endif /*defined(CONFIG_USB_HCI) || defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)*/
+
+}
+
+/****************************************************************************
+
+Following are some utitity fuctions for WiFi MLME
+
+*****************************************************************************/
+
+BOOLEAN IsLegal5GChannel(
+	IN PADAPTER			Adapter,
+	IN u8			channel)
+{
+
+	int i = 0;
+	u8 Channel_5G[45] = {36, 38, 40, 42, 44, 46, 48, 50, 52, 54, 56, 58,
+		60, 62, 64, 100, 102, 104, 106, 108, 110, 112, 114, 116, 118, 120, 122,
+		124, 126, 128, 130, 132, 134, 136, 138, 140, 149, 151, 153, 155, 157, 159,
+			     161, 163, 165
+			    };
+	for (i = 0; i < sizeof(Channel_5G); i++)
+		if (channel == Channel_5G[i])
+			return _TRUE;
+	return _FALSE;
+}
+
+/* collect bss info from Beacon and Probe request/response frames. */
+u8 collect_bss_info(_adapter *padapter, union recv_frame *precv_frame, WLAN_BSSID_EX *bssid)
+{
+	int	i;
+	sint len;
+	u8	*p;
+	u8	rf_path;
+	u16	val16, subtype;
+	u8	*pframe = precv_frame->u.hdr.rx_data;
+	u32	packet_len = precv_frame->u.hdr.len;
+	u8 ie_offset;
+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(padapter);
+	struct registry_priv	*pregistrypriv = &padapter->registrypriv;
+	struct mlme_ext_priv	*pmlmeext = &padapter->mlmeextpriv;
+	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
+
+
+	len = packet_len - sizeof(struct rtw_ieee80211_hdr_3addr);
+
+	if (len > MAX_IE_SZ) {
+		/* RTW_INFO("IE too long for survey event\n"); */
+		return _FAIL;
+	}
+
+	_rtw_memset(bssid, 0, sizeof(WLAN_BSSID_EX));
+
+	subtype = get_frame_sub_type(pframe);
+
+	if (subtype == WIFI_BEACON) {
+		bssid->Reserved[0] = BSS_TYPE_BCN;
+		ie_offset = _BEACON_IE_OFFSET_;
+	} else {
+		/* FIXME : more type */
+		if (subtype == WIFI_PROBERSP) {
+			ie_offset = _PROBERSP_IE_OFFSET_;
+			bssid->Reserved[0] = BSS_TYPE_PROB_RSP;
+		} else if (subtype == WIFI_PROBEREQ) {
+			ie_offset = _PROBEREQ_IE_OFFSET_;
+			bssid->Reserved[0] = BSS_TYPE_PROB_REQ;
+		} else {
+			bssid->Reserved[0] = BSS_TYPE_UNDEF;
+			ie_offset = _FIXED_IE_LENGTH_;
+		}
+	}
+
+	bssid->Length = sizeof(WLAN_BSSID_EX) - MAX_IE_SZ + len;
+
+	/* below is to copy the information element */
+	bssid->IELength = len;
+	_rtw_memcpy(bssid->IEs, (pframe + sizeof(struct rtw_ieee80211_hdr_3addr)), bssid->IELength);
+
+	/* get the signal strength */
+	/* bssid->Rssi = precv_frame->u.hdr.attrib.SignalStrength; */ /* 0-100 index. */
+	bssid->Rssi = precv_frame->u.hdr.attrib.phy_info.recv_signal_power; /* in dBM.raw data */
+	bssid->PhyInfo.SignalQuality = precv_frame->u.hdr.attrib.phy_info.signal_quality;/* in percentage */
+	bssid->PhyInfo.SignalStrength = precv_frame->u.hdr.attrib.phy_info.signal_strength;/* in percentage */
+
+	/* get rx_snr */
+	if (precv_frame->u.hdr.attrib.data_rate >= DESC_RATE11M) {
+		bssid->PhyInfo.is_cck_rate = 0;
+		for (rf_path = 0; rf_path < pHalData->NumTotalRFPath; rf_path++)
+			bssid->PhyInfo.rx_snr[rf_path] =
+				precv_frame->u.hdr.attrib.phy_info.rx_snr[rf_path];
+	} else
+		bssid->PhyInfo.is_cck_rate = 1;
+
+#ifdef CONFIG_ANTENNA_DIVERSITY
+	rtw_hal_get_odm_var(padapter, HAL_ODM_ANTDIV_SELECT, &(bssid->PhyInfo.Optimum_antenna), NULL);
+#endif
+
+	/* checking SSID */
+	p = rtw_get_ie(bssid->IEs + ie_offset, _SSID_IE_, &len, bssid->IELength - ie_offset);
+	if (p == NULL) {
+		RTW_INFO("marc: cannot find SSID for survey event\n");
+		return _FAIL;
+	}
+
+	if (*(p + 1)) {
+		if (len > NDIS_802_11_LENGTH_SSID) {
+			RTW_INFO("%s()-%d: IE too long (%d) for survey event\n", __FUNCTION__, __LINE__, len);
+			return _FAIL;
+		}
+		_rtw_memcpy(bssid->Ssid.Ssid, (p + 2), *(p + 1));
+		bssid->Ssid.SsidLength = *(p + 1);
+	} else
+		bssid->Ssid.SsidLength = 0;
+
+	_rtw_memset(bssid->SupportedRates, 0, NDIS_802_11_LENGTH_RATES_EX);
+
+	/* checking rate info... */
+	i = 0;
+	p = rtw_get_ie(bssid->IEs + ie_offset, _SUPPORTEDRATES_IE_, &len, bssid->IELength - ie_offset);
+	if (p != NULL) {
+		if (len > NDIS_802_11_LENGTH_RATES_EX) {
+			RTW_INFO("%s()-%d: IE too long (%d) for survey event\n", __FUNCTION__, __LINE__, len);
+			return _FAIL;
+		}
+		if (rtw_validate_value(_SUPPORTEDRATES_IE_, p+2, len) == _FALSE) {
+			rtw_absorb_ssid_ifneed(padapter, bssid, pframe);
+			RTW_DBG_DUMP("Invalidated Support Rate IE --", p, len+2);
+			return _FAIL;
+		}
+		_rtw_memcpy(bssid->SupportedRates, (p + 2), len);
+		i = len;
+	}
+
+	p = rtw_get_ie(bssid->IEs + ie_offset, _EXT_SUPPORTEDRATES_IE_, &len, bssid->IELength - ie_offset);
+	if (p != NULL) {
+		if (len > (NDIS_802_11_LENGTH_RATES_EX - i)) {
+			RTW_INFO("%s()-%d: IE too long (%d) for survey event\n", __FUNCTION__, __LINE__, len);
+			return _FAIL;
+		}
+		if (rtw_validate_value(_EXT_SUPPORTEDRATES_IE_, p+2, len) == _FALSE) {
+			rtw_absorb_ssid_ifneed(padapter, bssid, pframe);
+			RTW_DBG_DUMP("Invalidated EXT Support Rate IE --", p, len+2);
+			return _FAIL;
+		}
+		_rtw_memcpy(bssid->SupportedRates + i, (p + 2), len);
+	}
+
+	/* todo: */
+#if 0
+	if (judge_network_type(bssid->SupportedRates, (len + i)) == WIRELESS_11B)
+		bssid->NetworkTypeInUse = Ndis802_11DS;
+	else
+#endif
+	{
+		bssid->NetworkTypeInUse = Ndis802_11OFDM24;
+	}
+
+#ifdef CONFIG_P2P
+	if (subtype == WIFI_PROBEREQ) {
+		u8 *p2p_ie;
+		u32	p2p_ielen;
+		/* Set Listion Channel */
+		p2p_ie = rtw_get_p2p_ie(bssid->IEs, bssid->IELength, NULL, &p2p_ielen);
+		if (p2p_ie) {
+			u32	attr_contentlen = 0;
+			u8 listen_ch[5] = { 0x00 };
+
+			rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_LISTEN_CH, listen_ch, &attr_contentlen);
+			bssid->Configuration.DSConfig = listen_ch[4];
+		} else {
+			/* use current channel */
+			bssid->Configuration.DSConfig = padapter->mlmeextpriv.cur_channel;
+			RTW_INFO("%s()-%d: Cannot get p2p_ie. set DSconfig to op_ch(%d)\n", __FUNCTION__, __LINE__, bssid->Configuration.DSConfig);
+		}
+
+		/* FIXME */
+		bssid->InfrastructureMode = Ndis802_11Infrastructure;
+		_rtw_memcpy(bssid->MacAddress, get_addr2_ptr(pframe), ETH_ALEN);
+		bssid->Privacy = 1;
+		return _SUCCESS;
+	}
+#endif /* CONFIG_P2P */
+
+	if (bssid->IELength < 12)
+		return _FAIL;
+
+	/* Checking for DSConfig */
+	p = rtw_get_ie(bssid->IEs + ie_offset, _DSSET_IE_, &len, bssid->IELength - ie_offset);
+
+	bssid->Configuration.DSConfig = 0;
+	bssid->Configuration.Length = 0;
+
+	if (p)
+		bssid->Configuration.DSConfig = *(p + 2);
+	else {
+		/* In 5G, some ap do not have DSSET IE */
+		/* checking HT info for channel */
+		p = rtw_get_ie(bssid->IEs + ie_offset, _HT_ADD_INFO_IE_, &len, bssid->IELength - ie_offset);
+		if (p) {
+			struct HT_info_element *HT_info = (struct HT_info_element *)(p + 2);
+			bssid->Configuration.DSConfig = HT_info->primary_channel;
+		} else {
+			/* use current channel */
+			bssid->Configuration.DSConfig = rtw_get_oper_ch(padapter);
+		}
+	}
+
+	_rtw_memcpy(&bssid->Configuration.BeaconPeriod, rtw_get_beacon_interval_from_ie(bssid->IEs), 2);
+	bssid->Configuration.BeaconPeriod = le32_to_cpu(bssid->Configuration.BeaconPeriod);
+
+	val16 = rtw_get_capability((WLAN_BSSID_EX *)bssid);
+
+	if ((val16 & 0x03) == cap_ESS) {
+		bssid->InfrastructureMode = Ndis802_11Infrastructure;
+		_rtw_memcpy(bssid->MacAddress, get_addr2_ptr(pframe), ETH_ALEN);
+	} else if ((val16 & 0x03) == cap_IBSS){
+		bssid->InfrastructureMode = Ndis802_11IBSS;
+		_rtw_memcpy(bssid->MacAddress, GetAddr3Ptr(pframe), ETH_ALEN);
+	} else if ((val16 & 0x03) == 0x00){
+		u8 *mesh_id_ie, *mesh_conf_ie;
+		sint mesh_id_ie_len, mesh_conf_ie_len;
+
+		mesh_id_ie = rtw_get_ie(bssid->IEs + ie_offset, WLAN_EID_MESH_ID, &mesh_id_ie_len, bssid->IELength - ie_offset);
+		mesh_conf_ie = rtw_get_ie(bssid->IEs + ie_offset, WLAN_EID_MESH_CONFIG, &mesh_conf_ie_len, bssid->IELength - ie_offset);
+		if (mesh_id_ie || mesh_conf_ie) {
+			if (!mesh_id_ie) {
+				RTW_INFO("cannot find Mesh ID for survey event\n");
+				return _FAIL;
+			}
+			if (mesh_id_ie_len) {
+				if (mesh_id_ie_len > NDIS_802_11_LENGTH_SSID) {
+					RTW_INFO("Mesh ID too long (%d) for survey event\n", mesh_id_ie_len);
+					return _FAIL;
+				}
+				_rtw_memcpy(bssid->mesh_id.Ssid, (mesh_id_ie + 2), mesh_id_ie_len);
+				bssid->mesh_id.SsidLength = mesh_id_ie_len;
+			} else
+				bssid->mesh_id.SsidLength = 0;
+
+			if (!mesh_conf_ie) {
+				RTW_INFO("cannot find Mesh config for survey event\n");
+				return _FAIL;
+			}
+			if (mesh_conf_ie_len != 7) {
+				RTW_INFO("invalid Mesh conf IE len (%d) for survey event\n", mesh_conf_ie_len);
+				return _FAIL;
+			}
+
+			bssid->InfrastructureMode = Ndis802_11_mesh;
+			_rtw_memcpy(bssid->MacAddress, GetAddr3Ptr(pframe), ETH_ALEN);
+		} else {
+			/* default cases */
+			bssid->InfrastructureMode = Ndis802_11IBSS;
+			_rtw_memcpy(bssid->MacAddress, GetAddr3Ptr(pframe), ETH_ALEN);
+		}
+	}
+
+	if (val16 & BIT(4))
+		bssid->Privacy = 1;
+	else
+		bssid->Privacy = 0;
+
+	bssid->Configuration.ATIMWindow = 0;
+
+	/* 20/40 BSS Coexistence check */
+	if ((pregistrypriv->wifi_spec == 1) && (_FALSE == pmlmeinfo->bwmode_updated)) {
+		struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
+#ifdef CONFIG_80211N_HT
+		p = rtw_get_ie(bssid->IEs + ie_offset, _HT_CAPABILITY_IE_, &len, bssid->IELength - ie_offset);
+		if (p && len > 0) {
+			struct HT_caps_element	*pHT_caps;
+			pHT_caps = (struct HT_caps_element *)(p + 2);
+
+			if (pHT_caps->u.HT_cap_element.HT_caps_info & BIT(14))
+				pmlmepriv->num_FortyMHzIntolerant++;
+		} else
+			pmlmepriv->num_sta_no_ht++;
+#endif /* CONFIG_80211N_HT */
+
+	}
+
+#ifdef CONFIG_INTEL_WIDI
+	/* process_intel_widi_query_or_tigger(padapter, bssid); */
+	if (process_intel_widi_query_or_tigger(padapter, bssid))
+		return _FAIL;
+#endif /* CONFIG_INTEL_WIDI */
+
+#if defined(DBG_RX_SIGNAL_DISPLAY_SSID_MONITORED) & 1
+	if (strcmp(bssid->Ssid.Ssid, DBG_RX_SIGNAL_DISPLAY_SSID_MONITORED) == 0) {
+		RTW_INFO("Receiving %s("MAC_FMT", DSConfig:%u) from ch%u with ss:%3u, sq:%3u, RawRSSI:%3ld\n"
+			, bssid->Ssid.Ssid, MAC_ARG(bssid->MacAddress), bssid->Configuration.DSConfig
+			 , rtw_get_oper_ch(padapter)
+			, bssid->PhyInfo.SignalStrength, bssid->PhyInfo.SignalQuality, bssid->Rssi
+			);
+	}
+#endif
+
+	/* mark bss info receving from nearby channel as SignalQuality 101 */
+	if (bssid->Configuration.DSConfig != rtw_get_oper_ch(padapter))
+		bssid->PhyInfo.SignalQuality = 101;
+
+#ifdef CONFIG_RTW_80211K
+	p = rtw_get_ie(bssid->IEs + ie_offset, _EID_RRM_EN_CAP_IE_, &len, bssid->IELength - ie_offset);
+	if (p)
+		_rtw_memcpy(bssid->PhyInfo.rm_en_cap, (p + 2), *(p + 1));
+
+	/* save freerun counter */
+	bssid->PhyInfo.free_cnt = precv_frame->u.hdr.attrib.free_cnt;
+#endif
+	return _SUCCESS;
+}
+
+void start_create_ibss(_adapter *padapter)
+{
+	unsigned short	caps;
+	u8	val8;
+	u8	join_type;
+	struct mlme_ext_priv	*pmlmeext = &padapter->mlmeextpriv;
+	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
+	WLAN_BSSID_EX		*pnetwork = (WLAN_BSSID_EX *)(&(pmlmeinfo->network));
+	u8 doiqk = _FALSE;
+	pmlmeext->cur_channel = (u8)pnetwork->Configuration.DSConfig;
+	pmlmeinfo->bcn_interval = get_beacon_interval(pnetwork);
+
+	/* update wireless mode */
+	update_wireless_mode(padapter);
+
+	/* udpate capability */
+	caps = rtw_get_capability((WLAN_BSSID_EX *)pnetwork);
+	update_capinfo(padapter, caps);
+	if (caps & cap_IBSS) { /* adhoc master */
+		/* set_opmode_cmd(padapter, adhoc); */ /* removed */
+
+		val8 = 0xcf;
+		rtw_hal_set_hwreg(padapter, HW_VAR_SEC_CFG, (u8 *)(&val8));
+
+		doiqk = _TRUE;
+		rtw_hal_set_hwreg(padapter , HW_VAR_DO_IQK , &doiqk);
+
+		/* switch channel */
+		set_channel_bwmode(padapter, pmlmeext->cur_channel, HAL_PRIME_CHNL_OFFSET_DONT_CARE, CHANNEL_WIDTH_20);
+
+		doiqk = _FALSE;
+		rtw_hal_set_hwreg(padapter , HW_VAR_DO_IQK , &doiqk);
+
+		beacon_timing_control(padapter);
+
+		/* set msr to WIFI_FW_ADHOC_STATE */
+		pmlmeinfo->state = WIFI_FW_ADHOC_STATE;
+		Set_MSR(padapter, (pmlmeinfo->state & 0x3));
+
+		/* issue beacon */
+		if (send_beacon(padapter) == _FAIL) {
+
+			report_join_res(padapter, -1, WLAN_STATUS_UNSPECIFIED_FAILURE);
+			pmlmeinfo->state = WIFI_FW_NULL_STATE;
+		} else {
+			rtw_hal_set_hwreg(padapter, HW_VAR_BSSID, padapter->registrypriv.dev_network.MacAddress);
+			rtw_hal_rcr_set_chk_bssid(padapter, MLME_ADHOC_STARTED);
+			join_type = 0;
+			rtw_hal_set_hwreg(padapter, HW_VAR_MLME_JOIN, (u8 *)(&join_type));
+
+			report_join_res(padapter, 1, WLAN_STATUS_SUCCESS);
+			pmlmeinfo->state |= WIFI_FW_ASSOC_SUCCESS;
+			rtw_indicate_connect(padapter);
+		}
+	} else {
+		RTW_INFO("start_create_ibss, invalid cap:%x\n", caps);
+		return;
+	}
+	/* update bc/mc sta_info */
+	update_bmc_sta(padapter);
+
+}
+
+void start_clnt_join(_adapter *padapter)
+{
+	unsigned short	caps;
+	u8	val8;
+	struct mlme_ext_priv	*pmlmeext = &padapter->mlmeextpriv;
+	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
+	WLAN_BSSID_EX		*pnetwork = (WLAN_BSSID_EX *)(&(pmlmeinfo->network));
+	int beacon_timeout;
+	u8 ASIX_ID[] = {0x00, 0x0E, 0xC6};
+
+	/* update wireless mode */
+	update_wireless_mode(padapter);
+
+	/* udpate capability */
+	caps = rtw_get_capability((WLAN_BSSID_EX *)pnetwork);
+	update_capinfo(padapter, caps);
+
+	/* check if sta is ASIX peer and fix IOT issue if it is. */
+	if (_rtw_memcmp(get_my_bssid(&pmlmeinfo->network) , ASIX_ID , 3)) {
+		u8 iot_flag = _TRUE;
+		rtw_hal_set_hwreg(padapter, HW_VAR_ASIX_IOT, (u8 *)(&iot_flag));
+	}
+
+	if (caps & cap_ESS) {
+		Set_MSR(padapter, WIFI_FW_STATION_STATE);
+
+		val8 = (pmlmeinfo->auth_algo == dot11AuthAlgrthm_8021X) ? 0xcc : 0xcf;
+
+#ifdef CONFIG_WAPI_SUPPORT
+		if (padapter->wapiInfo.bWapiEnable && pmlmeinfo->auth_algo == dot11AuthAlgrthm_WAPI) {
+			/* Disable TxUseDefaultKey, RxUseDefaultKey, RxBroadcastUseDefaultKey. */
+			val8 = 0x4c;
+		}
+#endif
+		rtw_hal_set_hwreg(padapter, HW_VAR_SEC_CFG, (u8 *)(&val8));
+
+#ifdef CONFIG_DEAUTH_BEFORE_CONNECT
+		/* Because of AP's not receiving deauth before */
+		/* AP may: 1)not response auth or 2)deauth us after link is complete */
+		/* issue deauth before issuing auth to deal with the situation */
+
+		/*	Commented by Albert 2012/07/21 */
+		/*	For the Win8 P2P connection, it will be hard to have a successful connection if this Wi-Fi doesn't connect to it. */
+		{
+#ifdef CONFIG_P2P
+			_queue *queue = &(padapter->mlmepriv.scanned_queue);
+			_list	*head = get_list_head(queue);
+			_list *pos = get_next(head);
+			struct wlan_network *scanned = NULL;
+			u8 ie_offset = 0;
+			_irqL irqL;
+			bool has_p2p_ie = _FALSE;
+
+			_enter_critical_bh(&(padapter->mlmepriv.scanned_queue.lock), &irqL);
+
+			for (pos = get_next(head); !rtw_end_of_queue_search(head, pos); pos = get_next(pos)) {
+
+				scanned = LIST_CONTAINOR(pos, struct wlan_network, list);
+
+				if (_rtw_memcmp(&(scanned->network.Ssid), &(pnetwork->Ssid), sizeof(NDIS_802_11_SSID)) == _TRUE
+				    && _rtw_memcmp(scanned->network.MacAddress, pnetwork->MacAddress, sizeof(NDIS_802_11_MAC_ADDRESS)) == _TRUE
+				   ) {
+					ie_offset = (scanned->network.Reserved[0] == BSS_TYPE_PROB_REQ ? 0 : 12);
+					if (rtw_get_p2p_ie(scanned->network.IEs + ie_offset, scanned->network.IELength - ie_offset, NULL, NULL))
+						has_p2p_ie = _TRUE;
+					break;
+				}
+			}
+
+			_exit_critical_bh(&(padapter->mlmepriv.scanned_queue.lock), &irqL);
+
+			if (scanned == NULL || rtw_end_of_queue_search(head, pos) || has_p2p_ie == _FALSE)
+#endif /* CONFIG_P2P */
+				/* To avoid connecting to AP fail during resume process, change retry count from 5 to 1 */
+				issue_deauth_ex(padapter, pnetwork->MacAddress, WLAN_REASON_DEAUTH_LEAVING, 1, 100);
+		}
+#endif /* CONFIG_DEAUTH_BEFORE_CONNECT */
+
+		/* here wait for receiving the beacon to start auth */
+		/* and enable a timer */
+		beacon_timeout = decide_wait_for_beacon_timeout(pmlmeinfo->bcn_interval);
+		set_link_timer(pmlmeext, beacon_timeout);
+		_set_timer(&padapter->mlmepriv.assoc_timer,
+			(REAUTH_TO * REAUTH_LIMIT) + (REASSOC_TO * REASSOC_LIMIT) + beacon_timeout);
+
+#ifdef CONFIG_RTW_80211R
+		if (rtw_ft_roam(padapter)) {
+			rtw_ft_start_clnt_join(padapter);
+		} else
+#endif
+		{
+			rtw_sta_linking_test_set_start();
+			pmlmeinfo->state = WIFI_FW_AUTH_NULL | WIFI_FW_STATION_STATE;
+		}
+	} else if (caps & cap_IBSS) { /* adhoc client */
+		Set_MSR(padapter, WIFI_FW_ADHOC_STATE);
+
+		val8 = 0xcf;
+		rtw_hal_set_hwreg(padapter, HW_VAR_SEC_CFG, (u8 *)(&val8));
+
+		beacon_timing_control(padapter);
+
+		pmlmeinfo->state = WIFI_FW_ADHOC_STATE;
+
+		report_join_res(padapter, 1, WLAN_STATUS_SUCCESS);
+	} else {
+		/* RTW_INFO("marc: invalid cap:%x\n", caps); */
+		return;
+	}
+
+}
+
+void start_clnt_auth(_adapter *padapter)
+{
+	struct mlme_ext_priv	*pmlmeext = &padapter->mlmeextpriv;
+	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
+
+	_cancel_timer_ex(&pmlmeext->link_timer);
+
+	pmlmeinfo->state &= (~WIFI_FW_AUTH_NULL);
+	pmlmeinfo->state |= WIFI_FW_AUTH_STATE;
+
+	pmlmeinfo->auth_seq = 1;
+	pmlmeinfo->reauth_count = 0;
+	pmlmeinfo->reassoc_count = 0;
+	pmlmeinfo->link_count = 0;
+	pmlmeext->retry = 0;
+
+#ifdef CONFIG_RTW_80211R
+	if (rtw_ft_roam(padapter)) {
+		rtw_ft_set_status(padapter, RTW_FT_AUTHENTICATING_STA);
+		RTW_PRINT("start ft auth\n");
+	} else
+#endif
+		RTW_PRINT("start auth\n");
+	issue_auth(padapter, NULL, 0);
+
+	set_link_timer(pmlmeext, REAUTH_TO);
+
+}
+
+
+void start_clnt_assoc(_adapter *padapter)
+{
+	struct mlme_ext_priv	*pmlmeext = &padapter->mlmeextpriv;
+	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
+
+	_cancel_timer_ex(&pmlmeext->link_timer);
+
+	pmlmeinfo->state &= (~(WIFI_FW_AUTH_NULL | WIFI_FW_AUTH_STATE));
+	pmlmeinfo->state |= (WIFI_FW_AUTH_SUCCESS | WIFI_FW_ASSOC_STATE);
+
+#ifdef CONFIG_RTW_80211R
+	if (rtw_ft_roam(padapter))
+		issue_reassocreq(padapter);
+	else
+#endif
+		issue_assocreq(padapter);
+
+	set_link_timer(pmlmeext, REASSOC_TO);
+}
+
+unsigned int receive_disconnect(_adapter *padapter, unsigned char *MacAddr, unsigned short reason, u8 locally_generated)
+{
+	struct mlme_ext_priv	*pmlmeext = &padapter->mlmeextpriv;
+	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
+
+	if (!(_rtw_memcmp(MacAddr, get_my_bssid(&pmlmeinfo->network), ETH_ALEN)))
+		return _SUCCESS;
+
+	RTW_INFO("%s\n", __FUNCTION__);
+
+#ifdef CONFIG_RTW_REPEATER_SON
+	rtw_rson_do_disconnect(padapter);
+#endif
+	if ((pmlmeinfo->state & 0x03) == WIFI_FW_STATION_STATE) {
+		if (pmlmeinfo->state & WIFI_FW_ASSOC_SUCCESS) {
+			if (report_del_sta_event(padapter, MacAddr, reason, _TRUE, locally_generated) != _FAIL)
+				pmlmeinfo->state = WIFI_FW_NULL_STATE;
+		} else if (pmlmeinfo->state & WIFI_FW_LINKING_STATE) {
+			if (report_join_res(padapter, -2, reason) != _FAIL)
+				pmlmeinfo->state = WIFI_FW_NULL_STATE;
+		} else
+			RTW_INFO(FUNC_ADPT_FMT" - End to Disconnect\n", FUNC_ADPT_ARG(padapter));
+#ifdef CONFIG_RTW_80211R
+		rtw_ft_roam_status_reset(padapter);
+#endif
+#ifdef CONFIG_RTW_WNM
+		rtw_wnm_reset_btm_state(padapter);
+#endif
+	}
+
+	return _SUCCESS;
+}
+
+#ifdef CONFIG_80211D
+static void process_80211d(PADAPTER padapter, WLAN_BSSID_EX *bssid)
+{
+	struct rf_ctl_t *rfctl = adapter_to_rfctl(padapter);
+	struct registry_priv *pregistrypriv;
+	struct mlme_ext_priv *pmlmeext;
+	RT_CHANNEL_INFO *chplan_new;
+	u8 channel;
+	u8 i;
+
+
+	pregistrypriv = &padapter->registrypriv;
+	pmlmeext = &padapter->mlmeextpriv;
+
+	/* Adjust channel plan by AP Country IE */
+	if (pregistrypriv->enable80211d
+	    && (!pmlmeext->update_channel_plan_by_ap_done)) {
+		u8 *ie, *p;
+		u32 len;
+		RT_CHANNEL_PLAN chplan_ap;
+		RT_CHANNEL_INFO *chplan_sta = NULL;
+		u8 country[4];
+		u8 fcn; /* first channel number */
+		u8 noc; /* number of channel */
+		u8 j, k;
+
+		ie = rtw_get_ie(bssid->IEs + _FIXED_IE_LENGTH_, _COUNTRY_IE_, &len, bssid->IELength - _FIXED_IE_LENGTH_);
+		if (!ie)
+			return;
+		if (len < 6)
+			return;
+
+		ie += 2;
+		p = ie;
+		ie += len;
+
+		_rtw_memset(country, 0, 4);
+		_rtw_memcpy(country, p, 3);
+		p += 3;
+		RTW_INFO("%s: 802.11d country=%s\n", __FUNCTION__, country);
+
+		i = 0;
+		while ((ie - p) >= 3) {
+			fcn = *(p++);
+			noc = *(p++);
+			p++;
+
+			for (j = 0; j < noc; j++) {
+				if (fcn <= 14)
+					channel = fcn + j; /* 2.4 GHz */
+				else
+					channel = fcn + j * 4; /* 5 GHz */
+
+				chplan_ap.Channel[i++] = channel;
+			}
+		}
+		chplan_ap.Len = i;
+
+#ifdef CONFIG_RTW_DEBUG
+		i = 0;
+		RTW_INFO("%s: AP[%s] channel plan {", __FUNCTION__, bssid->Ssid.Ssid);
+		while ((i < chplan_ap.Len) && (chplan_ap.Channel[i] != 0)) {
+			_RTW_INFO("%02d,", chplan_ap.Channel[i]);
+			i++;
+		}
+		_RTW_INFO("}\n");
+#endif
+
+		chplan_sta = rtw_malloc(sizeof(RT_CHANNEL_INFO) * MAX_CHANNEL_NUM);
+		if (!chplan_sta)
+			goto done_update_chplan_from_ap;
+
+		_rtw_memcpy(chplan_sta, rfctl->channel_set, sizeof(RT_CHANNEL_INFO) * MAX_CHANNEL_NUM);
+#ifdef CONFIG_RTW_DEBUG
+		i = 0;
+		RTW_INFO("%s: STA channel plan {", __FUNCTION__);
+		while ((i < MAX_CHANNEL_NUM) && (chplan_sta[i].ChannelNum != 0)) {
+			_RTW_INFO("%02d(%c),", chplan_sta[i].ChannelNum, chplan_sta[i].ScanType == SCAN_PASSIVE ? 'p' : 'a');
+			i++;
+		}
+		_RTW_INFO("}\n");
+#endif
+
+		_rtw_memset(rfctl->channel_set, 0, sizeof(rfctl->channel_set));
+		chplan_new = rfctl->channel_set;
+
+		i = j = k = 0;
+		if (pregistrypriv->wireless_mode & WIRELESS_11G) {
+			do {
+				if ((i == MAX_CHANNEL_NUM)
+				    || (chplan_sta[i].ChannelNum == 0)
+				    || (chplan_sta[i].ChannelNum > 14))
+					break;
+
+				if ((j == chplan_ap.Len) || (chplan_ap.Channel[j] > 14))
+					break;
+
+				if (chplan_sta[i].ChannelNum == chplan_ap.Channel[j]) {
+					chplan_new[k].ChannelNum = chplan_ap.Channel[j];
+					chplan_new[k].ScanType = SCAN_ACTIVE;
+					i++;
+					j++;
+					k++;
+				} else if (chplan_sta[i].ChannelNum < chplan_ap.Channel[j]) {
+					chplan_new[k].ChannelNum = chplan_sta[i].ChannelNum;
+#if 0
+					chplan_new[k].ScanType = chplan_sta[i].ScanType;
+#else
+					chplan_new[k].ScanType = SCAN_PASSIVE;
+#endif
+					i++;
+					k++;
+				} else if (chplan_sta[i].ChannelNum > chplan_ap.Channel[j]) {
+					chplan_new[k].ChannelNum = chplan_ap.Channel[j];
+					chplan_new[k].ScanType = SCAN_ACTIVE;
+					j++;
+					k++;
+				}
+			} while (1);
+
+			/* change AP not support channel to Passive scan */
+			while ((i < MAX_CHANNEL_NUM)
+			       && (chplan_sta[i].ChannelNum != 0)
+			       && (chplan_sta[i].ChannelNum <= 14)) {
+				chplan_new[k].ChannelNum = chplan_sta[i].ChannelNum;
+#if 0
+				chplan_new[k].ScanType = chplan_sta[i].ScanType;
+#else
+				chplan_new[k].ScanType = SCAN_PASSIVE;
+#endif
+				i++;
+				k++;
+			}
+
+			/* add channel AP supported */
+			while ((j < chplan_ap.Len) && (chplan_ap.Channel[j] <= 14)) {
+				chplan_new[k].ChannelNum = chplan_ap.Channel[j];
+				chplan_new[k].ScanType = SCAN_ACTIVE;
+				j++;
+				k++;
+			}
+		} else {
+			/* keep original STA 2.4G channel plan */
+			while ((i < MAX_CHANNEL_NUM)
+			       && (chplan_sta[i].ChannelNum != 0)
+			       && (chplan_sta[i].ChannelNum <= 14)) {
+				chplan_new[k].ChannelNum = chplan_sta[i].ChannelNum;
+				chplan_new[k].ScanType = chplan_sta[i].ScanType;
+				i++;
+				k++;
+			}
+
+			/* skip AP 2.4G channel plan */
+			while ((j < chplan_ap.Len) && (chplan_ap.Channel[j] <= 14))
+				j++;
+		}
+
+		if (pregistrypriv->wireless_mode & WIRELESS_11A) {
+			do {
+				if ((i >= MAX_CHANNEL_NUM)
+				    || (chplan_sta[i].ChannelNum == 0))
+					break;
+
+				if ((j == chplan_ap.Len) || (chplan_ap.Channel[j] == 0))
+					break;
+
+				if (chplan_sta[i].ChannelNum == chplan_ap.Channel[j]) {
+					chplan_new[k].ChannelNum = chplan_ap.Channel[j];
+					chplan_new[k].ScanType = SCAN_ACTIVE;
+					i++;
+					j++;
+					k++;
+				} else if (chplan_sta[i].ChannelNum < chplan_ap.Channel[j]) {
+					chplan_new[k].ChannelNum = chplan_sta[i].ChannelNum;
+#if 0
+					chplan_new[k].ScanType = chplan_sta[i].ScanType;
+#else
+					chplan_new[k].ScanType = SCAN_PASSIVE;
+#endif
+					i++;
+					k++;
+				} else if (chplan_sta[i].ChannelNum > chplan_ap.Channel[j]) {
+					chplan_new[k].ChannelNum = chplan_ap.Channel[j];
+					chplan_new[k].ScanType = SCAN_ACTIVE;
+					j++;
+					k++;
+				}
+			} while (1);
+
+			/* change AP not support channel to Passive scan */
+			while ((i < MAX_CHANNEL_NUM) && (chplan_sta[i].ChannelNum != 0)) {
+				chplan_new[k].ChannelNum = chplan_sta[i].ChannelNum;
+#if 0
+				chplan_new[k].ScanType = chplan_sta[i].ScanType;
+#else
+				chplan_new[k].ScanType = SCAN_PASSIVE;
+#endif
+				i++;
+				k++;
+			}
+
+			/* add channel AP supported */
+			while ((j < chplan_ap.Len) && (chplan_ap.Channel[j] != 0)) {
+				chplan_new[k].ChannelNum = chplan_ap.Channel[j];
+				chplan_new[k].ScanType = SCAN_ACTIVE;
+				j++;
+				k++;
+			}
+		} else {
+			/* keep original STA 5G channel plan */
+			while ((i < MAX_CHANNEL_NUM) && (chplan_sta[i].ChannelNum != 0)) {
+				chplan_new[k].ChannelNum = chplan_sta[i].ChannelNum;
+				chplan_new[k].ScanType = chplan_sta[i].ScanType;
+				i++;
+				k++;
+			}
+		}
+
+		pmlmeext->update_channel_plan_by_ap_done = 1;
+
+#ifdef CONFIG_RTW_DEBUG
+		k = 0;
+		RTW_INFO("%s: new STA channel plan {", __FUNCTION__);
+		while ((k < MAX_CHANNEL_NUM) && (chplan_new[k].ChannelNum != 0)) {
+			_RTW_INFO("%02d(%c),", chplan_new[k].ChannelNum, chplan_new[k].ScanType == SCAN_PASSIVE ? 'p' : 'c');
+			k++;
+		}
+		_RTW_INFO("}\n");
+#endif
+
+#if 0
+		/* recover the right channel index */
+		channel = chplan_sta[pmlmeext->sitesurvey_res.channel_idx].ChannelNum;
+		k = 0;
+		while ((k < MAX_CHANNEL_NUM) && (chplan_new[k].ChannelNum != 0)) {
+			if (chplan_new[k].ChannelNum == channel) {
+				RTW_INFO("%s: change mlme_ext sitesurvey channel index from %d to %d\n",
+					__FUNCTION__, pmlmeext->sitesurvey_res.channel_idx, k);
+				pmlmeext->sitesurvey_res.channel_idx = k;
+				break;
+			}
+			k++;
+		}
+#endif
+
+done_update_chplan_from_ap:
+		if (chplan_sta)
+			rtw_mfree(chplan_sta, sizeof(RT_CHANNEL_INFO) * MAX_CHANNEL_NUM);
+	}
+}
+#endif
+
+/****************************************************************************
+
+Following are the functions to report events
+
+*****************************************************************************/
+
+void report_survey_event(_adapter *padapter, union recv_frame *precv_frame)
+{
+	struct cmd_obj *pcmd_obj;
+	u8	*pevtcmd;
+	u32 cmdsz;
+	struct survey_event	*psurvey_evt;
+	struct C2HEvent_Header *pc2h_evt_hdr;
+	struct mlme_ext_priv *pmlmeext;
+	struct cmd_priv *pcmdpriv;
+	/* u8 *pframe = precv_frame->u.hdr.rx_data; */
+	/* uint len = precv_frame->u.hdr.len; */
+	RT_CHANNEL_INFO *chset = adapter_to_chset(padapter);
+	int ch_set_idx = -1;
+
+	if (!padapter)
+		return;
+
+	pmlmeext = &padapter->mlmeextpriv;
+	pcmdpriv = &padapter->cmdpriv;
+
+
+	pcmd_obj = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj));
+	if (pcmd_obj == NULL)
+		return;
+
+	cmdsz = (sizeof(struct survey_event) + sizeof(struct C2HEvent_Header));
+	pevtcmd = (u8 *)rtw_zmalloc(cmdsz);
+	if (pevtcmd == NULL) {
+		rtw_mfree((u8 *)pcmd_obj, sizeof(struct cmd_obj));
+		return;
+	}
+
+	_rtw_init_listhead(&pcmd_obj->list);
+
+	pcmd_obj->cmdcode = GEN_CMD_CODE(_Set_MLME_EVT);
+	pcmd_obj->cmdsz = cmdsz;
+	pcmd_obj->parmbuf = pevtcmd;
+
+	pcmd_obj->rsp = NULL;
+	pcmd_obj->rspsz  = 0;
+
+	pc2h_evt_hdr = (struct C2HEvent_Header *)(pevtcmd);
+	pc2h_evt_hdr->len = sizeof(struct survey_event);
+	pc2h_evt_hdr->ID = GEN_EVT_CODE(_Survey);
+	pc2h_evt_hdr->seq = ATOMIC_INC_RETURN(&pmlmeext->event_seq);
+
+	psurvey_evt = (struct survey_event *)(pevtcmd + sizeof(struct C2HEvent_Header));
+
+	if (collect_bss_info(padapter, precv_frame, (WLAN_BSSID_EX *)&psurvey_evt->bss) == _FAIL) {
+		rtw_mfree((u8 *)pcmd_obj, sizeof(struct cmd_obj));
+		rtw_mfree((u8 *)pevtcmd, cmdsz);
+		return;
+	}
+
+#ifdef CONFIG_80211D
+	process_80211d(padapter, &psurvey_evt->bss);
+#endif
+
+	ch_set_idx = rtw_chset_search_ch(chset, psurvey_evt->bss.Configuration.DSConfig);
+	if (ch_set_idx >= 0) {
+		if (psurvey_evt->bss.InfrastructureMode == Ndis802_11Infrastructure) {
+			if (chset[ch_set_idx].ScanType == SCAN_PASSIVE
+				&& !rtw_is_dfs_ch(psurvey_evt->bss.Configuration.DSConfig)
+			) {
+				RTW_INFO("%s: change ch:%d to active\n", __func__, psurvey_evt->bss.Configuration.DSConfig);
+				chset[ch_set_idx].ScanType = SCAN_ACTIVE;
+			}
+			#ifdef CONFIG_DFS
+			if (hidden_ssid_ap(&psurvey_evt->bss))
+				chset[ch_set_idx].hidden_bss_cnt++;
+			#endif
+		}
+	}
+
+	rtw_enqueue_cmd(pcmdpriv, pcmd_obj);
+
+	pmlmeext->sitesurvey_res.bss_cnt++;
+
+	return;
+
+}
+
+void report_surveydone_event(_adapter *padapter)
+{
+	struct cmd_obj *pcmd_obj;
+	u8	*pevtcmd;
+	u32 cmdsz;
+	struct surveydone_event *psurveydone_evt;
+	struct C2HEvent_Header	*pc2h_evt_hdr;
+	struct mlme_ext_priv		*pmlmeext = &padapter->mlmeextpriv;
+	struct cmd_priv *pcmdpriv = &padapter->cmdpriv;
+
+	pcmd_obj = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj));
+	if (pcmd_obj == NULL)
+		return;
+
+	cmdsz = (sizeof(struct surveydone_event) + sizeof(struct C2HEvent_Header));
+	pevtcmd = (u8 *)rtw_zmalloc(cmdsz);
+	if (pevtcmd == NULL) {
+		rtw_mfree((u8 *)pcmd_obj, sizeof(struct cmd_obj));
+		return;
+	}
+
+	_rtw_init_listhead(&pcmd_obj->list);
+
+	pcmd_obj->cmdcode = GEN_CMD_CODE(_Set_MLME_EVT);
+	pcmd_obj->cmdsz = cmdsz;
+	pcmd_obj->parmbuf = pevtcmd;
+
+	pcmd_obj->rsp = NULL;
+	pcmd_obj->rspsz  = 0;
+
+	pc2h_evt_hdr = (struct C2HEvent_Header *)(pevtcmd);
+	pc2h_evt_hdr->len = sizeof(struct surveydone_event);
+	pc2h_evt_hdr->ID = GEN_EVT_CODE(_SurveyDone);
+	pc2h_evt_hdr->seq = ATOMIC_INC_RETURN(&pmlmeext->event_seq);
+
+	psurveydone_evt = (struct surveydone_event *)(pevtcmd + sizeof(struct C2HEvent_Header));
+	psurveydone_evt->bss_cnt = pmlmeext->sitesurvey_res.bss_cnt;
+
+	RTW_INFO("survey done event(%x) band:%d for "ADPT_FMT"\n", psurveydone_evt->bss_cnt, padapter->setband, ADPT_ARG(padapter));
+
+	rtw_enqueue_cmd(pcmdpriv, pcmd_obj);
+
+	return;
+
+}
+
+u32 report_join_res(_adapter *padapter, int aid_res, u16 status)
+{
+	struct cmd_obj *pcmd_obj;
+	u8	*pevtcmd;
+	u32 cmdsz;
+	struct joinbss_event		*pjoinbss_evt;
+	struct C2HEvent_Header	*pc2h_evt_hdr;
+	struct mlme_ext_priv		*pmlmeext = &padapter->mlmeextpriv;
+	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
+	struct cmd_priv *pcmdpriv = &padapter->cmdpriv;
+	u32 ret = _FAIL;
+
+	pcmd_obj = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj));
+	if (pcmd_obj == NULL)
+		goto exit;
+
+	cmdsz = (sizeof(struct joinbss_event) + sizeof(struct C2HEvent_Header));
+	pevtcmd = (u8 *)rtw_zmalloc(cmdsz);
+	if (pevtcmd == NULL) {
+		rtw_mfree((u8 *)pcmd_obj, sizeof(struct cmd_obj));
+		goto exit;
+	}
+
+	_rtw_init_listhead(&pcmd_obj->list);
+
+	pcmd_obj->cmdcode = GEN_CMD_CODE(_Set_MLME_EVT);
+	pcmd_obj->cmdsz = cmdsz;
+	pcmd_obj->parmbuf = pevtcmd;
+
+	pcmd_obj->rsp = NULL;
+	pcmd_obj->rspsz  = 0;
+
+	pc2h_evt_hdr = (struct C2HEvent_Header *)(pevtcmd);
+	pc2h_evt_hdr->len = sizeof(struct joinbss_event);
+	pc2h_evt_hdr->ID = GEN_EVT_CODE(_JoinBss);
+	pc2h_evt_hdr->seq = ATOMIC_INC_RETURN(&pmlmeext->event_seq);
+
+	pjoinbss_evt = (struct joinbss_event *)(pevtcmd + sizeof(struct C2HEvent_Header));
+	_rtw_memcpy((unsigned char *)(&(pjoinbss_evt->network.network)), &(pmlmeinfo->network), sizeof(WLAN_BSSID_EX));
+	pjoinbss_evt->network.join_res	= pjoinbss_evt->network.aid = aid_res;
+
+	RTW_INFO("report_join_res(%d, %u)\n", aid_res, status);
+
+
+	rtw_joinbss_event_prehandle(padapter, (u8 *)&pjoinbss_evt->network, status);
+
+
+	ret = rtw_enqueue_cmd(pcmdpriv, pcmd_obj);
+
+exit:
+	return ret;
+}
+
+void report_wmm_edca_update(_adapter *padapter)
+{
+	struct cmd_obj *pcmd_obj;
+	u8	*pevtcmd;
+	u32 cmdsz;
+	struct wmm_event		*pwmm_event;
+	struct C2HEvent_Header	*pc2h_evt_hdr;
+	struct mlme_ext_priv		*pmlmeext = &padapter->mlmeextpriv;
+	struct cmd_priv *pcmdpriv = &padapter->cmdpriv;
+
+	pcmd_obj = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj));
+	if (pcmd_obj == NULL)
+		return;
+
+	cmdsz = (sizeof(struct wmm_event) + sizeof(struct C2HEvent_Header));
+	pevtcmd = (u8 *)rtw_zmalloc(cmdsz);
+	if (pevtcmd == NULL) {
+		rtw_mfree((u8 *)pcmd_obj, sizeof(struct cmd_obj));
+		return;
+	}
+
+	_rtw_init_listhead(&pcmd_obj->list);
+
+	pcmd_obj->cmdcode = GEN_CMD_CODE(_Set_MLME_EVT);
+	pcmd_obj->cmdsz = cmdsz;
+	pcmd_obj->parmbuf = pevtcmd;
+
+	pcmd_obj->rsp = NULL;
+	pcmd_obj->rspsz  = 0;
+
+	pc2h_evt_hdr = (struct C2HEvent_Header *)(pevtcmd);
+	pc2h_evt_hdr->len = sizeof(struct wmm_event);
+	pc2h_evt_hdr->ID = GEN_EVT_CODE(_WMM);
+	pc2h_evt_hdr->seq = ATOMIC_INC_RETURN(&pmlmeext->event_seq);
+
+	pwmm_event = (struct wmm_event *)(pevtcmd + sizeof(struct C2HEvent_Header));
+	pwmm_event->wmm = 0;
+
+	rtw_enqueue_cmd(pcmdpriv, pcmd_obj);
+
+	return;
+
+}
+
+u32 report_del_sta_event(_adapter *padapter, unsigned char *MacAddr, unsigned short reason, bool enqueue, u8 locally_generated)
+{
+	struct cmd_obj *pcmd_obj;
+	u8	*pevtcmd;
+	u32 cmdsz;
+	struct sta_info *psta;
+	int	mac_id = -1;
+	struct stadel_event			*pdel_sta_evt;
+	struct C2HEvent_Header	*pc2h_evt_hdr;
+	struct mlme_ext_priv		*pmlmeext = &padapter->mlmeextpriv;
+	struct cmd_priv *pcmdpriv = &padapter->cmdpriv;
+	u8 res = _SUCCESS;
+
+	/* prepare cmd parameter */
+	cmdsz = (sizeof(struct stadel_event) + sizeof(struct C2HEvent_Header));
+	pevtcmd = (u8 *)rtw_zmalloc(cmdsz);
+	if (pevtcmd == NULL) {
+		res = _FAIL;
+		goto exit;
+	}
+
+	pc2h_evt_hdr = (struct C2HEvent_Header *)(pevtcmd);
+	pc2h_evt_hdr->len = sizeof(struct stadel_event);
+	pc2h_evt_hdr->ID = GEN_EVT_CODE(_DelSTA);
+	pc2h_evt_hdr->seq = ATOMIC_INC_RETURN(&pmlmeext->event_seq);
+
+	pdel_sta_evt = (struct stadel_event *)(pevtcmd + sizeof(struct C2HEvent_Header));
+	_rtw_memcpy((unsigned char *)(&(pdel_sta_evt->macaddr)), MacAddr, ETH_ALEN);
+	_rtw_memcpy((unsigned char *)(pdel_sta_evt->rsvd), (unsigned char *)(&reason), 2);
+	psta = rtw_get_stainfo(&padapter->stapriv, MacAddr);
+	if (psta)
+		mac_id = (int)psta->cmn.mac_id;
+	else
+		mac_id = (-1);
+	pdel_sta_evt->mac_id = mac_id;
+	pdel_sta_evt->locally_generated = locally_generated;
+
+	if (!enqueue) {
+		/* do directly */
+		rtw_stadel_event_callback(padapter, (u8 *)pdel_sta_evt);
+		rtw_mfree(pevtcmd, cmdsz);
+	} else {
+		pcmd_obj = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj));
+		if (pcmd_obj == NULL) {
+			rtw_mfree(pevtcmd, cmdsz);
+			res = _FAIL;
+			goto exit;
+		}
+
+		_rtw_init_listhead(&pcmd_obj->list);
+		pcmd_obj->cmdcode = GEN_CMD_CODE(_Set_MLME_EVT);
+		pcmd_obj->cmdsz = cmdsz;
+		pcmd_obj->parmbuf = pevtcmd;
+
+		pcmd_obj->rsp = NULL;
+		pcmd_obj->rspsz  = 0;
+
+		res = rtw_enqueue_cmd(pcmdpriv, pcmd_obj);
+	}
+
+exit:
+
+	RTW_INFO(FUNC_ADPT_FMT" "MAC_FMT" mac_id=%d, enqueue:%d, res:%u\n"
+		, FUNC_ADPT_ARG(padapter), MAC_ARG(MacAddr), mac_id, enqueue, res);
+
+	return res;
+}
+
+void report_add_sta_event(_adapter *padapter, unsigned char *MacAddr)
+{
+	struct cmd_obj *pcmd_obj;
+	u8	*pevtcmd;
+	u32 cmdsz;
+	struct stassoc_event		*padd_sta_evt;
+	struct C2HEvent_Header	*pc2h_evt_hdr;
+	struct mlme_ext_priv		*pmlmeext = &padapter->mlmeextpriv;
+	struct cmd_priv *pcmdpriv = &padapter->cmdpriv;
+
+	pcmd_obj = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj));
+	if (pcmd_obj == NULL)
+		return;
+
+	cmdsz = (sizeof(struct stassoc_event) + sizeof(struct C2HEvent_Header));
+	pevtcmd = (u8 *)rtw_zmalloc(cmdsz);
+	if (pevtcmd == NULL) {
+		rtw_mfree((u8 *)pcmd_obj, sizeof(struct cmd_obj));
+		return;
+	}
+
+	_rtw_init_listhead(&pcmd_obj->list);
+
+	pcmd_obj->cmdcode = GEN_CMD_CODE(_Set_MLME_EVT);
+	pcmd_obj->cmdsz = cmdsz;
+	pcmd_obj->parmbuf = pevtcmd;
+
+	pcmd_obj->rsp = NULL;
+	pcmd_obj->rspsz  = 0;
+
+	pc2h_evt_hdr = (struct C2HEvent_Header *)(pevtcmd);
+	pc2h_evt_hdr->len = sizeof(struct stassoc_event);
+	pc2h_evt_hdr->ID = GEN_EVT_CODE(_AddSTA);
+	pc2h_evt_hdr->seq = ATOMIC_INC_RETURN(&pmlmeext->event_seq);
+
+	padd_sta_evt = (struct stassoc_event *)(pevtcmd + sizeof(struct C2HEvent_Header));
+	_rtw_memcpy((unsigned char *)(&(padd_sta_evt->macaddr)), MacAddr, ETH_ALEN);
+
+	RTW_INFO("report_add_sta_event: add STA\n");
+
+	rtw_enqueue_cmd(pcmdpriv, pcmd_obj);
+
+	return;
+}
+
+
+bool rtw_port_switch_chk(_adapter *adapter)
+{
+	bool switch_needed = _FALSE;
+#ifdef CONFIG_CONCURRENT_MODE
+#ifdef CONFIG_RUNTIME_PORT_SWITCH
+	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
+	struct pwrctrl_priv *pwrctl = dvobj_to_pwrctl(dvobj);
+	_adapter *if_port0 = NULL;
+	_adapter *if_port1 = NULL;
+	struct mlme_ext_info *if_port0_mlmeinfo = NULL;
+	struct mlme_ext_info *if_port1_mlmeinfo = NULL;
+	int i;
+
+	for (i = 0; i < dvobj->iface_nums; i++) {
+		if (get_hw_port(dvobj->padapters[i]) == HW_PORT0) {
+			if_port0 = dvobj->padapters[i];
+			if_port0_mlmeinfo = &(if_port0->mlmeextpriv.mlmext_info);
+		} else if (get_hw_port(dvobj->padapters[i]) == HW_PORT1) {
+			if_port1 = dvobj->padapters[i];
+			if_port1_mlmeinfo = &(if_port1->mlmeextpriv.mlmext_info);
+		}
+	}
+
+	if (if_port0 == NULL) {
+		rtw_warn_on(1);
+		goto exit;
+	}
+
+	if (if_port1 == NULL) {
+		rtw_warn_on(1);
+		goto exit;
+	}
+
+#ifdef DBG_RUNTIME_PORT_SWITCH
+	RTW_INFO(FUNC_ADPT_FMT" wowlan_mode:%u\n"
+		 ADPT_FMT", port0, mlmeinfo->state:0x%08x, p2p_state:%d, %d\n"
+		 ADPT_FMT", port1, mlmeinfo->state:0x%08x, p2p_state:%d, %d\n",
+		 FUNC_ADPT_ARG(adapter), pwrctl->wowlan_mode,
+		ADPT_ARG(if_port0), if_port0_mlmeinfo->state, rtw_p2p_state(&if_port0->wdinfo), rtw_p2p_chk_state(&if_port0->wdinfo, P2P_STATE_NONE),
+		ADPT_ARG(if_port1), if_port1_mlmeinfo->state, rtw_p2p_state(&if_port1->wdinfo), rtw_p2p_chk_state(&if_port1->wdinfo, P2P_STATE_NONE));
+#endif /* DBG_RUNTIME_PORT_SWITCH */
+
+#ifdef CONFIG_WOWLAN
+	/* WOWLAN interface(primary, for now) should be port0 */
+	if (pwrctl->wowlan_mode == _TRUE) {
+		if (!is_primary_adapter(if_port0)) {
+			RTW_INFO("%s "ADPT_FMT" enable WOWLAN\n", __func__, ADPT_ARG(if_port1));
+			switch_needed = _TRUE;
+		}
+		goto exit;
+	}
+#endif /* CONFIG_WOWLAN */
+
+	/* AP/Mesh should use port0 for ctl frame's ack */
+	if ((if_port1_mlmeinfo->state & 0x03) == WIFI_FW_AP_STATE) {
+		RTW_INFO("%s "ADPT_FMT" is AP/GO/Mesh\n", __func__, ADPT_ARG(if_port1));
+		switch_needed = _TRUE;
+		goto exit;
+	}
+
+	/* GC should use port0 for p2p ps */
+	if (((if_port1_mlmeinfo->state & 0x03) == WIFI_FW_STATION_STATE)
+	    && (if_port1_mlmeinfo->state & WIFI_FW_ASSOC_SUCCESS)
+#ifdef CONFIG_P2P
+	    && !rtw_p2p_chk_state(&if_port1->wdinfo, P2P_STATE_NONE)
+#endif
+	    && !check_fwstate(&if_port1->mlmepriv, WIFI_UNDER_WPS)
+	   ) {
+		RTW_INFO("%s "ADPT_FMT" is GC\n", __func__, ADPT_ARG(if_port1));
+		switch_needed = _TRUE;
+		goto exit;
+	}
+
+	/* port1 linked, but port0 not linked */
+	if ((if_port1_mlmeinfo->state & WIFI_FW_ASSOC_SUCCESS)
+	    && !(if_port0_mlmeinfo->state & WIFI_FW_ASSOC_SUCCESS)
+	    && ((if_port0_mlmeinfo->state & 0x03) != WIFI_FW_AP_STATE)
+	   ) {
+		RTW_INFO("%s "ADPT_FMT" is SINGLE_LINK\n", __func__, ADPT_ARG(if_port1));
+		switch_needed = _TRUE;
+		goto exit;
+	}
+
+exit:
+#ifdef DBG_RUNTIME_PORT_SWITCH
+	RTW_INFO(FUNC_ADPT_FMT" ret:%d\n", FUNC_ADPT_ARG(adapter), switch_needed);
+#endif /* DBG_RUNTIME_PORT_SWITCH */
+#endif /* CONFIG_RUNTIME_PORT_SWITCH */
+#endif /* CONFIG_CONCURRENT_MODE */
+	return switch_needed;
+}
+
+/****************************************************************************
+
+Following are the event callback functions
+
+*****************************************************************************/
+
+/* for sta/adhoc mode */
+void update_sta_info(_adapter *padapter, struct sta_info *psta)
+{
+	_irqL	irqL;
+	struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
+	struct mlme_ext_priv	*pmlmeext = &padapter->mlmeextpriv;
+	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
+
+	/* ERP */
+	VCS_update(padapter, psta);
+
+#ifdef CONFIG_80211N_HT
+	/* HT */
+	if (pmlmepriv->htpriv.ht_option) {
+		psta->htpriv.ht_option = _TRUE;
+
+		psta->htpriv.ampdu_enable = pmlmepriv->htpriv.ampdu_enable;
+
+		psta->htpriv.rx_ampdu_min_spacing = (pmlmeinfo->HT_caps.u.HT_cap_element.AMPDU_para & IEEE80211_HT_CAP_AMPDU_DENSITY) >> 2;
+
+		if (support_short_GI(padapter, &(pmlmeinfo->HT_caps), CHANNEL_WIDTH_20))
+			psta->htpriv.sgi_20m = _TRUE;
+
+		if (support_short_GI(padapter, &(pmlmeinfo->HT_caps), CHANNEL_WIDTH_40))
+			psta->htpriv.sgi_40m = _TRUE;
+
+		psta->qos_option = _TRUE;
+
+		psta->htpriv.ldpc_cap = pmlmepriv->htpriv.ldpc_cap;
+		psta->htpriv.stbc_cap = pmlmepriv->htpriv.stbc_cap;
+		psta->htpriv.beamform_cap = pmlmepriv->htpriv.beamform_cap;
+
+		_rtw_memcpy(&psta->htpriv.ht_cap, &pmlmeinfo->HT_caps, sizeof(struct rtw_ieee80211_ht_cap));
+		#ifdef CONFIG_BEAMFORMING
+		psta->htpriv.beamform_cap = pmlmepriv->htpriv.beamform_cap;
+		psta->cmn.bf_info.ht_beamform_cap = pmlmepriv->htpriv.beamform_cap;
+		#endif
+	} else
+#endif /* CONFIG_80211N_HT */
+	{
+#ifdef CONFIG_80211N_HT
+		psta->htpriv.ht_option = _FALSE;
+		psta->htpriv.ampdu_enable = _FALSE;
+		psta->htpriv.tx_amsdu_enable = _FALSE;
+		psta->htpriv.sgi_20m = _FALSE;
+		psta->htpriv.sgi_40m = _FALSE;
+#endif /* CONFIG_80211N_HT */
+		psta->qos_option = _FALSE;
+
+	}
+
+#ifdef CONFIG_80211N_HT
+	psta->htpriv.ch_offset = pmlmeext->cur_ch_offset;
+
+	psta->htpriv.agg_enable_bitmap = 0x0;/* reset */
+	psta->htpriv.candidate_tid_bitmap = 0x0;/* reset */
+#endif /* CONFIG_80211N_HT */
+
+	psta->cmn.bw_mode = pmlmeext->cur_bwmode;
+
+	/* QoS */
+	if (pmlmepriv->qospriv.qos_option)
+		psta->qos_option = _TRUE;
+
+#ifdef CONFIG_80211AC_VHT
+	_rtw_memcpy(&psta->vhtpriv, &pmlmepriv->vhtpriv, sizeof(struct vht_priv));
+	if (psta->vhtpriv.vht_option) {
+		psta->cmn.ra_info.is_vht_enable = _TRUE;
+		#ifdef CONFIG_BEAMFORMING
+		psta->vhtpriv.beamform_cap = pmlmepriv->vhtpriv.beamform_cap;
+		psta->cmn.bf_info.vht_beamform_cap = pmlmepriv->vhtpriv.beamform_cap;
+		#endif /*CONFIG_BEAMFORMING*/
+	}
+#endif /* CONFIG_80211AC_VHT */
+	psta->cmn.ra_info.is_support_sgi = query_ra_short_GI(psta, rtw_get_tx_bw_mode(padapter, psta));
+	update_ldpc_stbc_cap(psta);
+
+	_enter_critical_bh(&psta->lock, &irqL);
+	psta->state = _FW_LINKED;
+	_exit_critical_bh(&psta->lock, &irqL);
+
+}
+
+static void rtw_mlmeext_disconnect(_adapter *padapter)
+{
+	struct mlme_priv		*pmlmepriv = &padapter->mlmepriv;
+	struct mlme_ext_priv	*pmlmeext = &padapter->mlmeextpriv;
+	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
+	u8 self_action = MLME_ACTION_UNKNOWN;
+	u8 state_backup = (pmlmeinfo->state & 0x03);
+	u8 ASIX_ID[] = {0x00, 0x0E, 0xC6};
+
+	if (MLME_IS_AP(padapter))
+		self_action = MLME_AP_STOPPED;
+	else if (MLME_IS_MESH(padapter))
+		self_action = MLME_MESH_STOPPED;
+	else if (MLME_IS_STA(padapter))
+		self_action = MLME_STA_DISCONNECTED;
+	else if (MLME_IS_ADHOC(padapter) || MLME_IS_ADHOC_MASTER(padapter))
+		self_action = MLME_ADHOC_STOPPED;
+	else {
+		RTW_INFO("state:0x%x\n", MLME_STATE(padapter));
+		rtw_warn_on(1);
+	}
+
+	/* set_opmode_cmd(padapter, infra_client_with_mlme); */
+#ifdef CONFIG_HW_P0_TSF_SYNC
+	if (self_action == MLME_STA_DISCONNECTED)
+		correct_TSF(padapter, self_action);
+#endif
+	rtw_hal_set_hwreg(padapter, HW_VAR_MLME_DISCONNECT, 0);
+	rtw_hal_set_hwreg(padapter, HW_VAR_BSSID, null_addr);
+	if (self_action == MLME_STA_DISCONNECTED)
+		rtw_hal_rcr_set_chk_bssid(padapter, self_action);
+
+	/* set MSR to no link state->infra. mode */
+	Set_MSR(padapter, _HW_STATE_STATION_);
+
+	/* check if sta is ASIX peer and fix IOT issue if it is. */
+	if (_rtw_memcmp(get_my_bssid(&pmlmeinfo->network) , ASIX_ID , 3)) {
+		u8 iot_flag = _FALSE;
+		rtw_hal_set_hwreg(padapter, HW_VAR_ASIX_IOT, (u8 *)(&iot_flag));
+	}
+	pmlmeinfo->state = WIFI_FW_NULL_STATE;
+
+#ifdef CONFIG_MCC_MODE
+	/* mcc disconnect setting before download LPS rsvd page */
+	rtw_hal_set_mcc_setting_disconnect(padapter);
+#endif /* CONFIG_MCC_MODE */
+
+	if (state_backup == WIFI_FW_STATION_STATE) {
+		if (rtw_port_switch_chk(padapter) == _TRUE) {
+			rtw_hal_set_hwreg(padapter, HW_VAR_PORT_SWITCH, NULL);
+#ifdef CONFIG_LPS
+			{
+				_adapter *port0_iface = dvobj_get_port0_adapter(adapter_to_dvobj(padapter));
+				if (port0_iface)
+					rtw_lps_ctrl_wk_cmd(port0_iface, LPS_CTRL_CONNECT, 0);
+			}
+#endif
+		}
+	}
+
+	/* switch to the 20M Hz mode after disconnect */
+	pmlmeext->cur_bwmode = CHANNEL_WIDTH_20;
+	pmlmeext->cur_ch_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
+
+#ifdef CONFIG_FCS_MODE
+	if (EN_FCS(padapter))
+		rtw_hal_set_hwreg(padapter, HW_VAR_STOP_FCS_MODE, NULL);
+#endif
+
+	if (!(MLME_IS_STA(padapter) && MLME_IS_OPCH_SW(padapter))) {
+		/* DFS and channel status no need to check here for STA under OPCH_SW */
+		u8 ch, bw, offset;
+
+		#ifdef CONFIG_DFS_MASTER
+		rtw_dfs_rd_en_decision(padapter, self_action, 0);
+		#endif
+
+		if (rtw_mi_get_ch_setting_union_no_self(padapter, &ch, &bw, &offset) != 0) {
+			set_channel_bwmode(padapter, ch, offset, bw);
+			rtw_mi_update_union_chan_inf(padapter, ch, offset, bw);
+		}
+	}
+
+	flush_all_cam_entry(padapter);
+
+	_cancel_timer_ex(&pmlmeext->link_timer);
+
+	/* pmlmepriv->LinkDetectInfo.TrafficBusyState = _FALSE; */
+	pmlmepriv->LinkDetectInfo.TrafficTransitionCount = 0;
+	pmlmepriv->LinkDetectInfo.LowPowerTransitionCount = 0;
+
+#ifdef CONFIG_TDLS
+	padapter->tdlsinfo.ap_prohibited = _FALSE;
+
+	/* For TDLS channel switch, currently we only allow it to work in wifi logo test mode */
+	if (padapter->registrypriv.wifi_spec == 1)
+		padapter->tdlsinfo.ch_switch_prohibited = _FALSE;
+#endif /* CONFIG_TDLS */
+
+#ifdef CONFIG_WMMPS_STA
+	 if (check_fwstate(pmlmepriv, WIFI_STATION_STATE)) {
+		/* reset currently related uapsd setting when the connection has broken */
+		pmlmepriv->qospriv.uapsd_max_sp_len = 0;
+		pmlmepriv->qospriv.uapsd_tid = 0;
+		pmlmepriv->qospriv.uapsd_tid_delivery_enabled = 0;
+		pmlmepriv->qospriv.uapsd_tid_trigger_enabled = 0;
+		pmlmepriv->qospriv.uapsd_ap_supported = 0;
+	}
+#endif /* CONFIG_WMMPS_STA */
+
+}
+
+void mlmeext_joinbss_event_callback(_adapter *padapter, int join_res)
+{
+	struct sta_info		*psta;
+	struct mlme_ext_priv	*pmlmeext = &padapter->mlmeextpriv;
+	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
+	WLAN_BSSID_EX		*cur_network = &(pmlmeinfo->network);
+	struct sta_priv		*pstapriv = &padapter->stapriv;
+	u8	join_type;
+	struct mlme_priv	*pmlmepriv = &padapter->mlmepriv;
+
+#ifndef CONFIG_IOCTL_CFG80211
+	struct security_priv *psecuritypriv = &padapter->securitypriv;
+#endif
+
+	if (pmlmepriv->wpa_phase == _TRUE)
+		pmlmepriv->wpa_phase = _FALSE;
+
+	if (join_res < 0) {
+		join_type = 1;
+		rtw_hal_set_hwreg(padapter, HW_VAR_MLME_JOIN, (u8 *)(&join_type));
+		rtw_hal_set_hwreg(padapter, HW_VAR_BSSID, null_addr);
+		if ((pmlmeinfo->state & 0x03) == WIFI_FW_STATION_STATE)
+			rtw_hal_rcr_set_chk_bssid(padapter, MLME_STA_DISCONNECTED);
+
+		goto exit_mlmeext_joinbss_event_callback;
+	}
+
+#ifdef CONFIG_ARP_KEEP_ALIVE
+	pmlmepriv->bGetGateway = 1;
+	pmlmepriv->GetGatewayTryCnt = 0;
+#endif
+
+	if ((pmlmeinfo->state & 0x03) == WIFI_FW_ADHOC_STATE) {
+		/* update bc/mc sta_info */
+		update_bmc_sta(padapter);
+	}
+
+
+	/* turn on dynamic functions */
+	/* Switch_DM_Func(padapter, DYNAMIC_ALL_FUNC_ENABLE, _TRUE); */
+
+	/* update IOT-releated issue */
+	update_IOT_info(padapter);
+
+	rtw_hal_set_hwreg(padapter, HW_VAR_BASIC_RATE, cur_network->SupportedRates);
+
+	/* BCN interval */
+	rtw_hal_set_hwreg(padapter, HW_VAR_BEACON_INTERVAL, (u8 *)(&pmlmeinfo->bcn_interval));
+
+	/* udpate capability */
+	update_capinfo(padapter, pmlmeinfo->capability);
+
+	/* WMM, Update EDCA param */
+	WMMOnAssocRsp(padapter);
+#ifdef CONFIG_80211N_HT
+	/* HT */
+	HTOnAssocRsp(padapter);
+#endif /* CONFIG_80211N_HT */
+#ifdef CONFIG_80211AC_VHT
+	/* VHT */
+	VHTOnAssocRsp(padapter);
+#endif
+
+	psta = rtw_get_stainfo(pstapriv, cur_network->MacAddress);
+	if (psta) { /* only for infra. mode */
+		psta->wireless_mode = pmlmeext->cur_wireless_mode;
+
+		/* set per sta rate after updating HT cap. */
+		set_sta_rate(padapter, psta);
+
+		rtw_sta_media_status_rpt(padapter, psta, 1);
+
+		/* wakeup macid after join bss successfully to ensure
+			the subsequent data frames can be sent out normally */
+		rtw_hal_macid_wakeup(padapter, psta->cmn.mac_id);
+	}
+
+#ifndef CONFIG_IOCTL_CFG80211
+	if (is_wep_enc(psecuritypriv->dot11PrivacyAlgrthm))
+		rtw_sec_restore_wep_key(padapter);
+#endif /* CONFIG_IOCTL_CFG80211 */
+
+	if (rtw_port_switch_chk(padapter) == _TRUE)
+		rtw_hal_set_hwreg(padapter, HW_VAR_PORT_SWITCH, NULL);
+
+	join_type = 2;
+	rtw_hal_set_hwreg(padapter, HW_VAR_MLME_JOIN, (u8 *)(&join_type));
+
+	if ((pmlmeinfo->state & 0x03) == WIFI_FW_STATION_STATE) {
+		rtw_hal_rcr_set_chk_bssid(padapter, MLME_STA_CONNECTED);
+
+		/* correcting TSF */
+		correct_TSF(padapter, MLME_STA_CONNECTED);
+
+		/* set_link_timer(pmlmeext, DISCONNECT_TO); */
+	}
+
+#ifdef CONFIG_LPS
+	#ifndef CONFIG_FW_MULTI_PORT_SUPPORT
+	if (get_hw_port(padapter) == HW_PORT0)
+	#endif
+		rtw_lps_ctrl_wk_cmd(padapter, LPS_CTRL_CONNECT, 0);
+#endif
+
+#ifdef CONFIG_BEAMFORMING
+	if (psta)
+		beamforming_wk_cmd(padapter, BEAMFORMING_CTRL_ENTER, (u8 *)psta, sizeof(struct sta_info), 0);
+#endif/*CONFIG_BEAMFORMING*/
+
+exit_mlmeext_joinbss_event_callback:
+
+	rtw_join_done_chk_ch(padapter, join_res);
+#ifdef CONFIG_RTW_REPEATER_SON
+	rtw_rson_join_done(padapter);
+#endif
+	RTW_INFO("=>%s - End to Connection without 4-way\n", __FUNCTION__);
+}
+
+/* currently only adhoc mode will go here */
+void mlmeext_sta_add_event_callback(_adapter *padapter, struct sta_info *psta)
+{
+	struct mlme_ext_priv	*pmlmeext = &(padapter->mlmeextpriv);
+	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
+	u8	join_type;
+
+	RTW_INFO("%s\n", __FUNCTION__);
+
+	if ((pmlmeinfo->state & 0x03) == WIFI_FW_ADHOC_STATE) {
+		if (pmlmeinfo->state & WIFI_FW_ASSOC_SUCCESS) { /* adhoc master or sta_count>1 */
+			/* nothing to do */
+		} else { /* adhoc client */
+			/* update TSF Value */
+			/* update_TSF(pmlmeext, pframe, len);			 */
+
+			/* correcting TSF */
+			correct_TSF(padapter, MLME_ADHOC_STARTED);
+
+			/* start beacon */
+			if (send_beacon(padapter) == _FAIL)
+				rtw_warn_on(1);
+
+			pmlmeinfo->state |= WIFI_FW_ASSOC_SUCCESS;
+		}
+
+		join_type = 2;
+		rtw_hal_set_hwreg(padapter, HW_VAR_MLME_JOIN, (u8 *)(&join_type));
+	}
+
+	/* update adhoc sta_info */
+	update_sta_info(padapter, psta);
+
+	rtw_hal_update_sta_ra_info(padapter, psta);
+
+	/* ToDo: HT for Ad-hoc */
+	psta->wireless_mode = rtw_check_network_type(psta->bssrateset, psta->bssratelen, pmlmeext->cur_channel);
+	rtw_hal_set_odm_var(padapter, HAL_ODM_STA_INFO, psta, _TRUE);
+
+	/* rate radaptive */
+	Update_RA_Entry(padapter, psta);
+}
+
+void mlmeext_sta_del_event_callback(_adapter *padapter)
+{
+	if (is_client_associated_to_ap(padapter) || is_IBSS_empty(padapter))
+		rtw_mlmeext_disconnect(padapter);
+}
+
+/****************************************************************************
+
+Following are the functions for the timer handlers
+
+*****************************************************************************/
+void _linked_info_dump(_adapter *padapter)
+{
+	if (padapter->bLinkInfoDump) {
+		rtw_hal_get_def_var(padapter, HW_DEF_RA_INFO_DUMP, RTW_DBGDUMP);
+		rtw_hal_set_odm_var(padapter, HAL_ODM_RX_INFO_DUMP, RTW_DBGDUMP, _FALSE);
+	}
+}
+/********************************************************************
+
+When station does not receive any packet in MAX_CONTINUAL_NORXPACKET_COUNT*2 seconds,
+recipient station will teardown the block ack by issuing DELBA frame.
+
+*********************************************************************/
+void rtw_delba_check(_adapter *padapter, struct sta_info *psta, u8 from_timer)
+{
+	int	i = 0;
+	int ret = _SUCCESS;
+	struct mlme_ext_priv	*pmlmeext = &padapter->mlmeextpriv;
+	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
+
+	/*
+		IOT issue,occur Broadcom ap(Buffalo WZR-D1800H,Netgear R6300).
+		AP is originator.AP does not transmit unicast packets when STA response its BAR.
+		This case probably occur ap issue BAR after AP builds BA.
+
+		Follow 802.11 spec, STA shall maintain an inactivity timer for every negotiated Block Ack setup.
+		The inactivity timer is not reset when MPDUs corresponding to other TIDs are received.
+	*/
+	if (pmlmeinfo->assoc_AP_vendor == HT_IOT_PEER_BROADCOM) {
+		for (i = 0; i < TID_NUM ; i++) {
+			if ((psta->recvreorder_ctrl[i].enable) && 
+                        (sta_rx_data_qos_pkts(psta, i) == sta_last_rx_data_qos_pkts(psta, i)) ) {			
+					if (_TRUE == rtw_inc_and_chk_continual_no_rx_packet(psta, i)) {					
+						/* send a DELBA frame to the peer STA with the Reason Code field set to TIMEOUT */
+						if (!from_timer)
+							ret = issue_del_ba_ex(padapter, psta->cmn.mac_addr, i, 39, 0, 3, 1);
+						else
+							issue_del_ba(padapter,  psta->cmn.mac_addr, i, 39, 0);
+						psta->recvreorder_ctrl[i].enable = _FALSE;
+						if (ret != _FAIL)
+							psta->recvreorder_ctrl[i].ampdu_size = RX_AMPDU_SIZE_INVALID;
+						rtw_reset_continual_no_rx_packet(psta, i);
+					}				
+			} else {
+				/* The inactivity timer is reset when MPDUs to the TID is received. */
+				rtw_reset_continual_no_rx_packet(psta, i);
+			}
+		}
+	}
+}
+
+u8 chk_ap_is_alive(_adapter *padapter, struct sta_info *psta)
+{
+	u8 ret = _FALSE;
+#ifdef DBG_EXPIRATION_CHK
+	struct mlme_ext_priv	*pmlmeext = &padapter->mlmeextpriv;
+	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
+
+	RTW_INFO(FUNC_ADPT_FMT" rx:"STA_PKTS_FMT", beacon:%llu, probersp_to_self:%llu"
+		/*", probersp_bm:%llu, probersp_uo:%llu, probereq:%llu, BI:%u"*/
+		 ", retry:%u\n"
+		 , FUNC_ADPT_ARG(padapter)
+		 , STA_RX_PKTS_DIFF_ARG(psta)
+		, psta->sta_stats.rx_beacon_pkts - psta->sta_stats.last_rx_beacon_pkts
+		, psta->sta_stats.rx_probersp_pkts - psta->sta_stats.last_rx_probersp_pkts
+		/*, psta->sta_stats.rx_probersp_bm_pkts - psta->sta_stats.last_rx_probersp_bm_pkts
+		, psta->sta_stats.rx_probersp_uo_pkts - psta->sta_stats.last_rx_probersp_uo_pkts
+		, psta->sta_stats.rx_probereq_pkts - psta->sta_stats.last_rx_probereq_pkts
+		 , pmlmeinfo->bcn_interval*/
+		 , pmlmeext->retry
+		);
+
+	RTW_INFO(FUNC_ADPT_FMT" tx_pkts:%llu, link_count:%u\n", FUNC_ADPT_ARG(padapter)
+		 , sta_tx_pkts(psta)
+		 , pmlmeinfo->link_count
+		);
+#endif
+
+	if ((sta_rx_data_pkts(psta) == sta_last_rx_data_pkts(psta))
+	    && sta_rx_beacon_pkts(psta) == sta_last_rx_beacon_pkts(psta)
+	    && sta_rx_probersp_pkts(psta) == sta_last_rx_probersp_pkts(psta)
+	   )
+		ret = _FALSE;
+	else
+		ret = _TRUE;
+
+	sta_update_last_rx_pkts(psta);
+
+	return ret;
+}
+
+u8 chk_adhoc_peer_is_alive(struct sta_info *psta)
+{
+	u8 ret = _TRUE;
+
+#ifdef DBG_EXPIRATION_CHK
+	RTW_INFO("sta:"MAC_FMT", rssi:%d, rx:"STA_PKTS_FMT", beacon:%llu, probersp_to_self:%llu"
+		/*", probersp_bm:%llu, probersp_uo:%llu, probereq:%llu, BI:%u"*/
+		 ", expire_to:%u\n"
+		 , MAC_ARG(psta->cmn.mac_addr)
+		 , psta->cmn.rssi_stat.rssi
+		 , STA_RX_PKTS_DIFF_ARG(psta)
+		, psta->sta_stats.rx_beacon_pkts - psta->sta_stats.last_rx_beacon_pkts
+		, psta->sta_stats.rx_probersp_pkts - psta->sta_stats.last_rx_probersp_pkts
+		/*, psta->sta_stats.rx_probersp_bm_pkts - psta->sta_stats.last_rx_probersp_bm_pkts
+		, psta->sta_stats.rx_probersp_uo_pkts - psta->sta_stats.last_rx_probersp_uo_pkts
+		, psta->sta_stats.rx_probereq_pkts - psta->sta_stats.last_rx_probereq_pkts
+		 , pmlmeinfo->bcn_interval*/
+		 , psta->expire_to
+		);
+#endif
+
+	if (sta_rx_data_pkts(psta) == sta_last_rx_data_pkts(psta)
+	    && sta_rx_beacon_pkts(psta) == sta_last_rx_beacon_pkts(psta)
+	    && sta_rx_probersp_pkts(psta) == sta_last_rx_probersp_pkts(psta))
+		ret = _FALSE;
+
+	sta_update_last_rx_pkts(psta);
+
+	return ret;
+}
+
+#ifdef CONFIG_TDLS
+u8 chk_tdls_peer_sta_is_alive(_adapter *padapter, struct sta_info *psta)
+{
+	if ((psta->sta_stats.rx_data_pkts == psta->sta_stats.last_rx_data_pkts)
+	    && (psta->sta_stats.rx_tdls_disc_rsp_pkts == psta->sta_stats.last_rx_tdls_disc_rsp_pkts))
+		return _FALSE;
+
+	return _TRUE;
+}
+
+void linked_status_chk_tdls(_adapter *padapter)
+{
+	struct candidate_pool {
+		struct sta_info *psta;
+		u8 addr[ETH_ALEN];
+	};
+	struct sta_priv *pstapriv = &padapter->stapriv;
+	_irqL irqL;
+	u8 ack_chk;
+	struct sta_info *psta;
+	int i, num_teardown = 0, num_checkalive = 0;
+	_list	*plist, *phead;
+	struct tdls_txmgmt txmgmt;
+	struct candidate_pool checkalive[MAX_ALLOWED_TDLS_STA_NUM];
+	struct candidate_pool teardown[MAX_ALLOWED_TDLS_STA_NUM];
+	u8 tdls_sta_max = _FALSE;
+
+#define ALIVE_MIN 2
+#define ALIVE_MAX 5
+
+	_rtw_memset(&txmgmt, 0x00, sizeof(struct tdls_txmgmt));
+	_rtw_memset(checkalive, 0x00, sizeof(checkalive));
+	_rtw_memset(teardown, 0x00, sizeof(teardown));
+
+	if ((padapter->tdlsinfo.link_established == _TRUE)) {
+		_enter_critical_bh(&pstapriv->sta_hash_lock, &irqL);
+		for (i = 0; i < NUM_STA; i++) {
+			phead = &(pstapriv->sta_hash[i]);
+			plist = get_next(phead);
+
+			while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) {
+				psta = LIST_CONTAINOR(plist, struct sta_info, hash_list);
+				plist = get_next(plist);
+
+				if (psta->tdls_sta_state & TDLS_LINKED_STATE) {
+					psta->alive_count++;
+					if (psta->alive_count >= ALIVE_MIN) {
+						if (chk_tdls_peer_sta_is_alive(padapter, psta) == _FALSE) {
+							if (psta->alive_count < ALIVE_MAX) {
+								_rtw_memcpy(checkalive[num_checkalive].addr, psta->cmn.mac_addr, ETH_ALEN);
+								checkalive[num_checkalive].psta = psta;
+								num_checkalive++;
+							} else {
+								_rtw_memcpy(teardown[num_teardown].addr, psta->cmn.mac_addr, ETH_ALEN);
+								teardown[num_teardown].psta = psta;
+								num_teardown++;
+							}
+						} else
+							psta->alive_count = 0;
+					}
+					psta->sta_stats.last_rx_data_pkts = psta->sta_stats.rx_data_pkts;
+					psta->sta_stats.last_rx_tdls_disc_rsp_pkts = psta->sta_stats.rx_tdls_disc_rsp_pkts;
+
+					if ((num_checkalive >= MAX_ALLOWED_TDLS_STA_NUM) || (num_teardown >= MAX_ALLOWED_TDLS_STA_NUM)) {
+						tdls_sta_max = _TRUE;
+						break;
+					}
+				}
+			}
+
+			if (tdls_sta_max == _TRUE)
+				break;
+		}
+		_exit_critical_bh(&pstapriv->sta_hash_lock, &irqL);
+
+		if (num_checkalive > 0) {
+			for (i = 0; i < num_checkalive; i++) {
+				_rtw_memcpy(txmgmt.peer, checkalive[i].addr, ETH_ALEN);
+				issue_tdls_dis_req(padapter, &txmgmt);
+				issue_tdls_dis_req(padapter, &txmgmt);
+				issue_tdls_dis_req(padapter, &txmgmt);
+			}
+		}
+
+		if (num_teardown > 0) {
+			for (i = 0; i < num_teardown; i++) {
+				RTW_INFO("[%s %d] Send teardown to "MAC_FMT"\n", __FUNCTION__, __LINE__, MAC_ARG(teardown[i].addr));
+				txmgmt.status_code = _RSON_TDLS_TEAR_TOOFAR_;
+				_rtw_memcpy(txmgmt.peer, teardown[i].addr, ETH_ALEN);
+				issue_tdls_teardown(padapter, &txmgmt, _FALSE);
+			}
+		}
+	}
+
+}
+#endif /* CONFIG_TDLS */
+
+/* from_timer == 1 means driver is in LPS */
+void linked_status_chk(_adapter *padapter, u8 from_timer)
+{
+	u32	i;
+	struct sta_info		*psta;
+	struct mlme_ext_priv	*pmlmeext = &padapter->mlmeextpriv;
+	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
+	struct sta_priv		*pstapriv = &padapter->stapriv;
+#if defined(CONFIG_ARP_KEEP_ALIVE) || defined(CONFIG_LAYER2_ROAMING)
+	struct mlme_priv	*pmlmepriv = &padapter->mlmepriv;
+#endif
+#ifdef CONFIG_LAYER2_ROAMING
+	struct recv_priv	*precvpriv = &padapter->recvpriv;
+#endif
+
+	if (padapter->registrypriv.mp_mode == _TRUE)
+		return;
+
+	if (is_client_associated_to_ap(padapter)) {
+		/* linked infrastructure client mode */
+
+		int tx_chk = _SUCCESS, rx_chk = _SUCCESS;
+		int rx_chk_limit;
+		int link_count_limit;
+
+#if defined(CONFIG_RTW_REPEATER_SON)
+	rtw_rson_scan_wk_cmd(padapter, RSON_SCAN_PROCESS);
+#elif defined(CONFIG_LAYER2_ROAMING)
+		if (rtw_chk_roam_flags(padapter, RTW_ROAM_ACTIVE)) {
+			RTW_INFO("signal_strength_data.avg_val = %d\n", precvpriv->signal_strength_data.avg_val);
+			if ((precvpriv->signal_strength_data.avg_val < pmlmepriv->roam_rssi_threshold)
+				&& (rtw_get_passing_time_ms(pmlmepriv->last_roaming) >= pmlmepriv->roam_scan_int*2000)) {
+#ifdef CONFIG_RTW_80211K
+				rtw_roam_nb_discover(padapter, _FALSE);
+#endif
+				pmlmepriv->need_to_roam = _TRUE;
+				rtw_drv_scan_by_self(padapter, RTW_AUTO_SCAN_REASON_ROAM);
+				pmlmepriv->last_roaming = rtw_get_current_time();
+			} else
+				pmlmepriv->need_to_roam = _FALSE;
+		}
+#endif
+#ifdef CONFIG_MCC_MODE
+		/*
+		 * due to tx ps null date to ao, so ap doest not tx pkt to driver
+		 * we may check chk_ap_is_alive fail, and may issue_probereq to wrong channel under sitesurvey
+		 * don't keep alive check under MCC
+		 */
+		if (rtw_hal_mcc_link_status_chk(padapter, __func__) == _FALSE)
+			return;
+#endif
+
+#if defined(DBG_ROAMING_TEST) || defined(CONFIG_RTW_REPEATER_SON)
+		rx_chk_limit = 1;
+#elif defined(CONFIG_ACTIVE_KEEP_ALIVE_CHECK) && !defined(CONFIG_LPS_LCLK_WD_TIMER)
+		rx_chk_limit = 4;
+#else
+		rx_chk_limit = 8;
+#endif
+#ifdef CONFIG_ARP_KEEP_ALIVE
+		if (!from_timer && pmlmepriv->bGetGateway == 1 && pmlmepriv->GetGatewayTryCnt < 3) {
+			RTW_INFO("do rtw_gw_addr_query() : %d\n", pmlmepriv->GetGatewayTryCnt);
+			pmlmepriv->GetGatewayTryCnt++;
+			if (rtw_gw_addr_query(padapter) == 0)
+				pmlmepriv->bGetGateway = 0;
+			else {
+				_rtw_memset(pmlmepriv->gw_ip, 0, 4);
+				_rtw_memset(pmlmepriv->gw_mac_addr, 0, ETH_ALEN);
+			}
+		}
+#endif
+#ifdef CONFIG_P2P
+		if (!rtw_p2p_chk_state(&padapter->wdinfo, P2P_STATE_NONE)) {
+			if (!from_timer)
+				link_count_limit = 3; /* 8 sec */
+			else
+				link_count_limit = 15; /* 32 sec */
+		} else
+#endif /* CONFIG_P2P */
+		{
+			if (!from_timer)
+				link_count_limit = 7; /* 16 sec */
+			else
+				link_count_limit = 29; /* 60 sec */
+		}
+
+#ifdef CONFIG_TDLS
+#ifdef CONFIG_TDLS_CH_SW
+		if (ATOMIC_READ(&padapter->tdlsinfo.chsw_info.chsw_on) == _TRUE)
+			return;
+#endif /* CONFIG_TDLS_CH_SW */
+
+#ifdef CONFIG_TDLS_AUTOCHECKALIVE
+		linked_status_chk_tdls(padapter);
+#endif /* CONFIG_TDLS_AUTOCHECKALIVE */
+#endif /* CONFIG_TDLS */
+
+		psta = rtw_get_stainfo(pstapriv, pmlmeinfo->network.MacAddress);
+		if (psta != NULL) {
+			bool is_p2p_enable = _FALSE;
+#ifdef CONFIG_P2P
+			is_p2p_enable = !rtw_p2p_chk_state(&padapter->wdinfo, P2P_STATE_NONE);
+#endif
+
+#ifdef CONFIG_ISSUE_DELBA_WHEN_NO_TRAFFIC 
+			/*issue delba when ap does not tx data packet that is Broadcom ap */
+			rtw_delba_check(padapter, psta, from_timer);
+#endif
+			if (chk_ap_is_alive(padapter, psta) == _FALSE)
+				rx_chk = _FAIL;
+
+			if (sta_last_tx_pkts(psta) == sta_tx_pkts(psta))
+				tx_chk = _FAIL;
+
+#ifdef CONFIG_ACTIVE_KEEP_ALIVE_CHECK
+			if (!from_timer && pmlmeext->active_keep_alive_check && (rx_chk == _FAIL || tx_chk == _FAIL)
+			) {
+				u8 backup_ch = 0, backup_bw = 0, backup_offset = 0;
+				u8 union_ch = 0, union_bw = 0, union_offset = 0;
+				u8 switch_channel_by_drv = _TRUE;
+
+				
+#ifdef CONFIG_MCC_MODE
+				if (MCC_EN(padapter)) {
+					/* driver doesn't switch channel under MCC */
+					if (rtw_hal_check_mcc_status(padapter, MCC_STATUS_DOING_MCC))
+						switch_channel_by_drv = _FALSE;
+				}
+#endif
+				if (switch_channel_by_drv) {
+					if (!rtw_mi_get_ch_setting_union(padapter, &union_ch, &union_bw, &union_offset)
+						|| pmlmeext->cur_channel != union_ch)
+							goto bypass_active_keep_alive;
+
+					/* switch to correct channel of current network  before issue keep-alive frames */
+					if (rtw_get_oper_ch(padapter) != pmlmeext->cur_channel) {
+						backup_ch = rtw_get_oper_ch(padapter);
+						backup_bw = rtw_get_oper_bw(padapter);
+						backup_offset = rtw_get_oper_choffset(padapter);
+						set_channel_bwmode(padapter, union_ch, union_offset, union_bw);
+					}
+				}
+
+				if (rx_chk != _SUCCESS)
+					issue_probereq_ex(padapter, &pmlmeinfo->network.Ssid, psta->cmn.mac_addr, 0, 0, 3, 1);
+
+				if ((tx_chk != _SUCCESS && pmlmeinfo->link_count++ == link_count_limit) || rx_chk != _SUCCESS) {
+					if (rtw_mi_check_fwstate(padapter, _FW_UNDER_SURVEY))
+						tx_chk = issue_nulldata(padapter, psta->cmn.mac_addr, 1, 3, 1);
+					else
+						tx_chk = issue_nulldata(padapter, psta->cmn.mac_addr, 0, 3, 1);
+					/* if tx acked and p2p disabled, set rx_chk _SUCCESS to reset retry count */
+					if (tx_chk == _SUCCESS && !is_p2p_enable)
+						rx_chk = _SUCCESS;
+				}
+
+				/* back to the original operation channel */
+				if (backup_ch > 0 && switch_channel_by_drv)
+					set_channel_bwmode(padapter, backup_ch, backup_offset, backup_bw);
+
+bypass_active_keep_alive:
+				;
+			} else
+#endif /* CONFIG_ACTIVE_KEEP_ALIVE_CHECK */
+			{
+				if (rx_chk != _SUCCESS) {
+					if (pmlmeext->retry == 0) {
+#ifdef DBG_EXPIRATION_CHK
+						RTW_INFO("issue_probereq to trigger probersp, retry=%d\n", pmlmeext->retry);
+#endif
+						issue_probereq_ex(padapter, &pmlmeinfo->network.Ssid, pmlmeinfo->network.MacAddress, 0, 0, 0, (from_timer ? 0 : 1));
+						issue_probereq_ex(padapter, &pmlmeinfo->network.Ssid, pmlmeinfo->network.MacAddress, 0, 0, 0, (from_timer ? 0 : 1));
+						issue_probereq_ex(padapter, &pmlmeinfo->network.Ssid, pmlmeinfo->network.MacAddress, 0, 0, 0, (from_timer ? 0 : 1));
+					}
+				}
+
+				if (tx_chk != _SUCCESS && pmlmeinfo->link_count++ == link_count_limit
+#ifdef CONFIG_MCC_MODE
+				    /* FW tx nulldata under MCC mode, we just check  ap is alive */
+				    && (!rtw_hal_check_mcc_status(padapter, MCC_STATUS_NEED_MCC))
+#endif /* CONFIG_MCC_MODE */
+				) {
+					#ifdef DBG_EXPIRATION_CHK
+					RTW_INFO("%s issue_nulldata(%d)\n", __FUNCTION__, from_timer ? 1 : 0);
+					#endif
+					if (from_timer || rtw_mi_check_fwstate(padapter, _FW_UNDER_SURVEY))
+						tx_chk = issue_nulldata(padapter, NULL, 1, 0, 0);
+					else
+						tx_chk = issue_nulldata(padapter, NULL, 0, 1, 1);
+				}
+			}
+
+			if (rx_chk == _FAIL) {
+				pmlmeext->retry++;
+				if (pmlmeext->retry > rx_chk_limit) {
+					RTW_PRINT(FUNC_ADPT_FMT" disconnect or roaming\n",
+						  FUNC_ADPT_ARG(padapter));
+					receive_disconnect(padapter, pmlmeinfo->network.MacAddress
+						, WLAN_REASON_EXPIRATION_CHK, _FALSE);
+					return;
+				}
+			} else
+				pmlmeext->retry = 0;
+
+			if (tx_chk == _FAIL)
+				pmlmeinfo->link_count %= (link_count_limit + 1);
+			else {
+				psta->sta_stats.last_tx_pkts = psta->sta_stats.tx_pkts;
+				pmlmeinfo->link_count = 0;
+			}
+
+		} /* end of if ((psta = rtw_get_stainfo(pstapriv, passoc_res->network.MacAddress)) != NULL) */
+
+	} else if (is_client_associated_to_ibss(padapter)) {
+		_irqL irqL;
+		_list *phead, *plist, dlist;
+
+		_rtw_init_listhead(&dlist);
+
+		_enter_critical_bh(&pstapriv->sta_hash_lock, &irqL);
+
+		for (i = 0; i < NUM_STA; i++) {
+
+			phead = &(pstapriv->sta_hash[i]);
+			plist = get_next(phead);
+			while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) {
+				psta = LIST_CONTAINOR(plist, struct sta_info, hash_list);
+				plist = get_next(plist);
+
+				if (is_broadcast_mac_addr(psta->cmn.mac_addr))
+					continue;
+
+				if (chk_adhoc_peer_is_alive(psta) || !psta->expire_to)
+					psta->expire_to = pstapriv->adhoc_expire_to;
+				else
+					psta->expire_to--;
+
+				if (psta->expire_to <= 0) {
+					rtw_list_delete(&psta->list);
+					rtw_list_insert_tail(&psta->list, &dlist);
+				}
+			}
+		}
+
+		_exit_critical_bh(&pstapriv->sta_hash_lock, &irqL);
+
+		plist = get_next(&dlist);
+		while (rtw_end_of_queue_search(&dlist, plist) == _FALSE) {
+			psta = LIST_CONTAINOR(plist, struct sta_info, list);
+			plist = get_next(plist);
+			rtw_list_delete(&psta->list);
+			RTW_INFO(FUNC_ADPT_FMT" ibss expire "MAC_FMT"\n"
+				, FUNC_ADPT_ARG(padapter), MAC_ARG(psta->cmn.mac_addr));
+			report_del_sta_event(padapter, psta->cmn.mac_addr, WLAN_REASON_EXPIRATION_CHK, from_timer ? _TRUE : _FALSE, _FALSE);
+		}
+	}
+
+}
+
+void survey_timer_hdl(void *ctx)
+{
+	_adapter *padapter = (_adapter *)ctx;
+	struct cmd_obj *cmd;
+	struct sitesurvey_parm *psurveyPara;
+	struct cmd_priv *pcmdpriv = &padapter->cmdpriv;
+	struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
+
+	if (mlmeext_scan_state(pmlmeext) > SCAN_DISABLE) {
+		cmd = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj));
+		if (cmd == NULL) {
+			rtw_warn_on(1);
+			goto exit;
+		}
+
+		psurveyPara = (struct sitesurvey_parm *)rtw_zmalloc(sizeof(struct sitesurvey_parm));
+		if (psurveyPara == NULL) {
+			rtw_warn_on(1);
+			rtw_mfree((unsigned char *)cmd, sizeof(struct cmd_obj));
+			goto exit;
+		}
+
+		init_h2fwcmd_w_parm_no_rsp(cmd, psurveyPara, GEN_CMD_CODE(_SiteSurvey));
+		rtw_enqueue_cmd(pcmdpriv, cmd);
+	}
+
+exit:
+	return;
+}
+
+#ifdef CONFIG_RTW_REPEATER_SON
+/*	 100ms pass, stop rson_scan	*/
+void rson_timer_hdl(void *ctx)
+{
+	_adapter *padapter = (_adapter *)ctx;
+
+	rtw_rson_scan_wk_cmd(padapter, RSON_SCAN_DISABLE);
+}
+
+#endif
+
+void link_timer_hdl(void *ctx)
+{
+	_adapter *padapter = (_adapter *)ctx;
+	/* static unsigned int		rx_pkt = 0; */
+	/* static u64				tx_cnt = 0; */
+	/* struct xmit_priv		*pxmitpriv = &(padapter->xmitpriv); */
+	struct mlme_ext_priv	*pmlmeext = &padapter->mlmeextpriv;
+	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
+	/* struct sta_priv		*pstapriv = &padapter->stapriv; */
+#ifdef CONFIG_RTW_80211R
+	struct	sta_priv		*pstapriv = &padapter->stapriv;
+	struct	sta_info		*psta = NULL;
+	WLAN_BSSID_EX		*pnetwork = (WLAN_BSSID_EX *)(&(pmlmeinfo->network));
+#endif
+
+	if (rtw_sta_linking_test_force_fail())
+		RTW_INFO("rtw_sta_linking_test_force_fail\n");
+
+	if (pmlmeext->join_abort && pmlmeinfo->state != WIFI_FW_NULL_STATE) {
+		RTW_INFO(FUNC_ADPT_FMT" join abort\n", FUNC_ADPT_ARG(padapter));
+		pmlmeinfo->state = WIFI_FW_NULL_STATE;
+		report_join_res(padapter, -4, WLAN_STATUS_UNSPECIFIED_FAILURE);
+		goto exit;
+	}
+
+	if (pmlmeinfo->state & WIFI_FW_AUTH_NULL) {
+		RTW_INFO("link_timer_hdl:no beacon while connecting\n");
+		pmlmeinfo->state = WIFI_FW_NULL_STATE;
+		report_join_res(padapter, -3, WLAN_STATUS_UNSPECIFIED_FAILURE);
+	} else if (pmlmeinfo->state & WIFI_FW_AUTH_STATE) {
+		/* re-auth timer */
+		if (++pmlmeinfo->reauth_count > REAUTH_LIMIT) {
+			/* if (pmlmeinfo->auth_algo != dot11AuthAlgrthm_Auto) */
+			/* { */
+			pmlmeinfo->state = 0;
+			if (pmlmeinfo->auth_status) {
+				report_join_res(padapter, -1, pmlmeinfo->auth_status);
+				pmlmeinfo->auth_status = 0; /* reset */
+			} else
+				report_join_res(padapter, -1, WLAN_STATUS_UNSPECIFIED_FAILURE);
+			return;
+			/* } */
+			/* else */
+			/* { */
+			/*	pmlmeinfo->auth_algo = dot11AuthAlgrthm_Shared; */
+			/*	pmlmeinfo->reauth_count = 0; */
+			/* } */
+		}
+
+		RTW_INFO("link_timer_hdl: auth timeout and try again\n");
+		pmlmeinfo->auth_seq = 1;
+		issue_auth(padapter, NULL, 0);
+		set_link_timer(pmlmeext, REAUTH_TO);
+	} else if (pmlmeinfo->state & WIFI_FW_ASSOC_STATE) {
+		/* re-assoc timer */
+		if (++pmlmeinfo->reassoc_count > REASSOC_LIMIT) {
+			pmlmeinfo->state = WIFI_FW_NULL_STATE;
+#ifdef CONFIG_RTW_80211R
+			if (rtw_ft_roam(padapter)) {
+				psta = rtw_get_stainfo(pstapriv, pmlmeinfo->network.MacAddress);
+				if (psta)
+					rtw_free_stainfo(padapter,  psta);
+			}
+#endif
+			report_join_res(padapter, -2, WLAN_STATUS_UNSPECIFIED_FAILURE);
+			return;
+		}
+
+#ifdef CONFIG_RTW_80211R
+		if (rtw_ft_roam(padapter)) {
+			RTW_INFO("link_timer_hdl: reassoc timeout and try again\n");
+			issue_reassocreq(padapter);
+		} else
+#endif
+		{
+			RTW_INFO("link_timer_hdl: assoc timeout and try again\n");
+			issue_assocreq(padapter);
+		}
+
+		set_link_timer(pmlmeext, REASSOC_TO);
+	}
+
+exit:
+	return;
+}
+
+void addba_timer_hdl(void *ctx)
+{
+	struct sta_info *psta = (struct sta_info *)ctx;
+
+#ifdef CONFIG_80211N_HT
+	struct ht_priv	*phtpriv;
+
+	if (!psta)
+		return;
+
+	phtpriv = &psta->htpriv;
+
+	if ((phtpriv->ht_option == _TRUE) && (phtpriv->ampdu_enable == _TRUE)) {
+		if (phtpriv->candidate_tid_bitmap)
+			phtpriv->candidate_tid_bitmap = 0x0;
+
+	}
+#endif /* CONFIG_80211N_HT */
+}
+
+#ifdef CONFIG_IEEE80211W
+void report_sta_timeout_event(_adapter *padapter, u8 *MacAddr, unsigned short reason)
+{
+	struct cmd_obj *pcmd_obj;
+	u8	*pevtcmd;
+	u32 cmdsz;
+	struct sta_info *psta;
+	int	mac_id;
+	struct stadel_event			*pdel_sta_evt;
+	struct C2HEvent_Header	*pc2h_evt_hdr;
+	struct mlme_ext_priv		*pmlmeext = &padapter->mlmeextpriv;
+	struct cmd_priv *pcmdpriv = &padapter->cmdpriv;
+
+	pcmd_obj = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj));
+	if (pcmd_obj == NULL)
+		return;
+
+	cmdsz = (sizeof(struct stadel_event) + sizeof(struct C2HEvent_Header));
+	pevtcmd = (u8 *)rtw_zmalloc(cmdsz);
+	if (pevtcmd == NULL) {
+		rtw_mfree((u8 *)pcmd_obj, sizeof(struct cmd_obj));
+		return;
+	}
+
+	_rtw_init_listhead(&pcmd_obj->list);
+
+	pcmd_obj->cmdcode = GEN_CMD_CODE(_Set_MLME_EVT);
+	pcmd_obj->cmdsz = cmdsz;
+	pcmd_obj->parmbuf = pevtcmd;
+
+	pcmd_obj->rsp = NULL;
+	pcmd_obj->rspsz  = 0;
+
+	pc2h_evt_hdr = (struct C2HEvent_Header *)(pevtcmd);
+	pc2h_evt_hdr->len = sizeof(struct stadel_event);
+	pc2h_evt_hdr->ID = GEN_EVT_CODE(_TimeoutSTA);
+	pc2h_evt_hdr->seq = ATOMIC_INC_RETURN(&pmlmeext->event_seq);
+
+	pdel_sta_evt = (struct stadel_event *)(pevtcmd + sizeof(struct C2HEvent_Header));
+	_rtw_memcpy((unsigned char *)(&(pdel_sta_evt->macaddr)), MacAddr, ETH_ALEN);
+	_rtw_memcpy((unsigned char *)(pdel_sta_evt->rsvd), (unsigned char *)(&reason), 2);
+
+
+	psta = rtw_get_stainfo(&padapter->stapriv, MacAddr);
+	if (psta)
+		mac_id = (int)psta->cmn.mac_id;
+	else
+		mac_id = (-1);
+
+	pdel_sta_evt->mac_id = mac_id;
+
+	RTW_INFO("report_del_sta_event: delete STA, mac_id=%d\n", mac_id);
+
+	rtw_enqueue_cmd(pcmdpriv, pcmd_obj);
+
+	return;
+}
+
+void clnt_sa_query_timeout(_adapter *padapter)
+{
+	struct mlme_ext_priv *mlmeext = &(padapter->mlmeextpriv);
+	struct mlme_ext_info *mlmeinfo = &(mlmeext->mlmext_info);
+
+	RTW_INFO(FUNC_ADPT_FMT"\n", FUNC_ADPT_ARG(padapter));
+	receive_disconnect(padapter, get_my_bssid(&(mlmeinfo->network)), WLAN_REASON_SA_QUERY_TIMEOUT, _FALSE);
+}
+
+void sa_query_timer_hdl(void *ctx)
+{
+	struct sta_info *psta = (struct sta_info *)ctx;
+	_adapter *padapter = psta->padapter;
+	_irqL irqL;
+	struct sta_priv *pstapriv = &padapter->stapriv;
+	struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
+
+	if (check_fwstate(pmlmepriv, WIFI_STATION_STATE) == _TRUE &&
+	    check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE)
+		clnt_sa_query_timeout(padapter);
+	else if (check_fwstate(pmlmepriv, WIFI_AP_STATE) == _TRUE)
+		report_sta_timeout_event(padapter, psta->cmn.mac_addr, WLAN_REASON_PREV_AUTH_NOT_VALID);
+}
+
+#endif /* CONFIG_IEEE80211W */
+
+#ifdef CONFIG_RTW_80211R
+void rtw_ft_update_bcn(_adapter *padapter, union recv_frame *precv_frame)
+{
+	struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
+	struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
+	struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
+	u8 *pframe = precv_frame->u.hdr.rx_data;
+	uint len = precv_frame->u.hdr.len;
+	WLAN_BSSID_EX *pbss;
+
+	if (rtw_ft_chk_status(padapter,RTW_FT_ASSOCIATED_STA) 
+		&& (pmlmepriv->ft_roam.ft_updated_bcn == _FALSE)) {
+		pbss = (WLAN_BSSID_EX*)rtw_malloc(sizeof(WLAN_BSSID_EX));
+		if (pbss) {
+			if (collect_bss_info(padapter, precv_frame, pbss) == _SUCCESS) {
+				struct beacon_keys recv_beacon;
+
+				update_network(&(pmlmepriv->cur_network.network), pbss, padapter, _TRUE);
+				rtw_get_bcn_info(&(pmlmepriv->cur_network));
+				
+				/* update bcn keys */
+				if (rtw_get_bcn_keys(padapter, pframe, len, &recv_beacon) == _TRUE) {
+					RTW_INFO("%s: beacon keys ready\n", __func__);
+					_rtw_memcpy(&pmlmepriv->cur_beacon_keys,
+						&recv_beacon, sizeof(recv_beacon));
+				} else {
+					RTW_ERR("%s: get beacon keys failed\n", __func__);
+					_rtw_memset(&pmlmepriv->cur_beacon_keys, 0, sizeof(recv_beacon));
+				}
+				#ifdef CONFIG_BCN_CNT_CONFIRM_HDL
+				pmlmepriv->new_beacon_cnts = 0;
+				#endif
+			}
+			rtw_mfree((u8*)pbss, sizeof(WLAN_BSSID_EX));
+		}
+
+		/* check the vendor of the assoc AP */
+		pmlmeinfo->assoc_AP_vendor = 	
+			check_assoc_AP(pframe+sizeof(struct rtw_ieee80211_hdr_3addr),
+				(len - sizeof(struct rtw_ieee80211_hdr_3addr)));
+
+		/* update TSF Value */
+		update_TSF(pmlmeext, pframe, len);
+		pmlmeext->bcn_cnt = 0;
+		pmlmeext->last_bcn_cnt = 0;
+		pmlmepriv->ft_roam.ft_updated_bcn = _TRUE;
+	}
+}
+
+void rtw_ft_start_clnt_join(_adapter *padapter)
+{
+	struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv);
+	struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
+	struct	mlme_priv *pmlmepriv = &(padapter->mlmepriv);
+	struct ft_roam_info *pft_roam = &(pmlmepriv->ft_roam);
+
+	if (rtw_ft_otd_roam(padapter)) {
+		pmlmeinfo->state = WIFI_FW_AUTH_SUCCESS | WIFI_FW_STATION_STATE;
+		pft_roam->ft_event.ies =
+			(pft_roam->ft_action + sizeof(struct rtw_ieee80211_hdr_3addr) + 16);
+		pft_roam->ft_event.ies_len =
+			(pft_roam->ft_action_len - sizeof(struct rtw_ieee80211_hdr_3addr));
+
+		/*Not support RIC*/
+		pft_roam->ft_event.ric_ies =  NULL;
+		pft_roam->ft_event.ric_ies_len = 0;
+		rtw_ft_report_evt(padapter);
+		return;
+	}
+
+	pmlmeinfo->state = WIFI_FW_AUTH_NULL | WIFI_FW_STATION_STATE;
+	start_clnt_auth(padapter);
+}
+
+u8 rtw_ft_update_rsnie(
+	_adapter *padapter, u8 bwrite, 
+	struct pkt_attrib *pattrib, u8 **pframe)
+{
+	struct ft_roam_info *pft_roam = &(padapter->mlmepriv.ft_roam);
+	u8 *pie;
+	u32 len;
+
+	pie = rtw_get_ie(pft_roam->updated_ft_ies, EID_WPA2, &len, 
+			pft_roam->updated_ft_ies_len);
+
+	if (!bwrite)
+		return (pie)?_SUCCESS:_FAIL;
+	
+	if (pie) {
+		*pframe = rtw_set_ie(((u8 *)*pframe), EID_WPA2, len, 
+						pie+2, &(pattrib->pktlen));
+	} else
+		return _FAIL;
+
+	return _SUCCESS;	
+}
+
+static u8 rtw_ft_update_mdie(
+	_adapter *padapter, struct pkt_attrib *pattrib, u8 **pframe)
+{
+	struct ft_roam_info *pft_roam = &(padapter->mlmepriv.ft_roam);
+	u8 *pie, mdie[3];
+	u32 len = 3;
+
+	if (rtw_ft_roam(padapter)) {
+		if ((pie = rtw_get_ie(pft_roam->updated_ft_ies, _MDIE_, 
+				&len, pft_roam->updated_ft_ies_len))) {
+			pie = (pie + 2); /* ignore md-id & length */
+		} else 
+			return _FAIL;
+	} else {
+		*((u16 *)&mdie[0]) = pft_roam->mdid;
+		mdie[2] = pft_roam->ft_cap;
+		pie = &mdie[0];
+	}
+
+	*pframe = rtw_set_ie(((u8 *)*pframe), _MDIE_, len , pie, &(pattrib->pktlen));
+	return _SUCCESS;	
+}
+
+static u8 rtw_ft_update_ftie(
+	_adapter *padapter, struct pkt_attrib *pattrib, u8 **pframe)
+{
+	struct ft_roam_info *pft_roam = &(padapter->mlmepriv.ft_roam);
+	u8 *pie;
+	u32 len;
+
+	if ((pie = rtw_get_ie(pft_roam->updated_ft_ies, _FTIE_, &len, 
+				pft_roam->updated_ft_ies_len)) != NULL) {
+		*pframe = rtw_set_ie(*pframe, _FTIE_, len , 
+					(pie+2), &(pattrib->pktlen));
+	} else
+		return _FAIL;
+
+	return _SUCCESS;	
+}
+
+void rtw_ft_build_auth_req_ies(_adapter *padapter, 
+	struct pkt_attrib *pattrib, u8 **pframe)
+{
+	u8 ftie_append = _TRUE;
+
+	if (!pattrib || !(*pframe))
+		return;
+
+	if (!rtw_ft_roam(padapter))
+		return;
+
+	ftie_append = rtw_ft_update_rsnie(padapter, _TRUE, pattrib, pframe);
+	rtw_ft_update_mdie(padapter, pattrib, pframe);
+	if (ftie_append)
+		rtw_ft_update_ftie(padapter, pattrib, pframe);
+}
+
+void rtw_ft_build_assoc_req_ies(_adapter *padapter, 
+	u8 is_reassoc, struct pkt_attrib *pattrib, u8 **pframe)
+{
+	if (!pattrib || !(*pframe))
+		return;
+
+	if (rtw_ft_chk_flags(padapter, RTW_FT_PEER_EN))
+		rtw_ft_update_mdie(padapter, pattrib, pframe);
+
+	if ((!is_reassoc) || (!rtw_ft_roam(padapter)))
+		return;
+
+	if (rtw_ft_update_rsnie(padapter, _FALSE, pattrib, pframe))
+		rtw_ft_update_ftie(padapter, pattrib, pframe);	
+}
+
+u8 rtw_ft_update_auth_rsp_ies(_adapter *padapter, u8 *pframe, u32 len)
+{
+	u8 ret = _SUCCESS;
+	u8 target_ap_addr[ETH_ALEN] = {0};
+	struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
+	struct ft_roam_info *pft_roam = &(pmlmepriv->ft_roam);
+
+	if (!rtw_ft_roam(padapter))
+		return _FAIL;
+
+	/*rtw_ft_report_reassoc_evt already,
+	 * and waiting for cfg80211_rtw_update_ft_ies */
+	if (rtw_ft_authed_sta(padapter))
+		return ret;
+
+	if (!pframe || !len)
+		return _FAIL;
+	
+	rtw_buf_update(&pmlmepriv->auth_rsp, 
+		&pmlmepriv->auth_rsp_len, pframe, len);
+	pft_roam->ft_event.ies =
+		(pmlmepriv->auth_rsp + sizeof(struct rtw_ieee80211_hdr_3addr) + 6);
+	pft_roam->ft_event.ies_len =
+		(pmlmepriv->auth_rsp_len - sizeof(struct rtw_ieee80211_hdr_3addr) - 6);
+
+	/*Not support RIC*/
+	pft_roam->ft_event.ric_ies =  NULL;
+	pft_roam->ft_event.ric_ies_len =  0;
+	_rtw_memcpy(target_ap_addr, pmlmepriv->assoc_bssid, ETH_ALEN);
+	rtw_ft_report_reassoc_evt(padapter, target_ap_addr);
+
+	return ret;	
+}
+
+static void rtw_ft_start_clnt_action(_adapter *padapter, u8 *pTargetAddr)
+{
+	struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
+
+	rtw_ft_set_status(padapter, RTW_FT_REQUESTING_STA);
+	rtw_ft_issue_action_req(padapter, pTargetAddr);
+	_set_timer(&pmlmeext->ft_link_timer, REASSOC_TO);
+}
+
+void rtw_ft_start_roam(_adapter *padapter, u8 *pTargetAddr)
+{
+	struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
+
+	if (rtw_ft_otd_roam(padapter)) {
+		rtw_ft_start_clnt_action(padapter, pTargetAddr);
+	} else {
+		/*wait a little time to retrieve packets buffered in the current ap while scan*/
+		_set_timer(&pmlmeext->ft_roam_timer, 30);
+	}
+}
+
+void rtw_ft_issue_action_req(_adapter *padapter, u8 *pTargetAddr)
+{
+	struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
+	struct xmit_priv *pxmitpriv = &(padapter->xmitpriv);
+	struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv);
+	struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
+	struct xmit_frame *pmgntframe;
+	struct rtw_ieee80211_hdr *pwlanhdr;
+	struct pkt_attrib *pattrib;
+	u8 *pframe;
+	u8 category = RTW_WLAN_CATEGORY_FT;
+	u8 action = RTW_WLAN_ACTION_FT_REQ;
+
+	pmgntframe = alloc_mgtxmitframe(pxmitpriv);
+	if (pmgntframe == NULL)
+		return;
+
+	pattrib = &pmgntframe->attrib;
+	update_mgntframe_attrib(padapter, pattrib);
+	_rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET);
+
+	pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET;
+	pwlanhdr = (struct rtw_ieee80211_hdr *)pframe;
+	pwlanhdr->frame_ctl = 0;
+
+	_rtw_memcpy(pwlanhdr->addr1, get_my_bssid(&pmlmeinfo->network), ETH_ALEN);
+	_rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN);
+	_rtw_memcpy(pwlanhdr->addr3, get_my_bssid(&pmlmeinfo->network), ETH_ALEN);
+
+	SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq);
+	pmlmeext->mgnt_seq++;
+	set_frame_sub_type(pframe, WIFI_ACTION);
+
+	pframe += sizeof(struct rtw_ieee80211_hdr_3addr);
+	pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr);
+
+	pframe = rtw_set_fixed_ie(pframe, 1, &(category), &(pattrib->pktlen));
+	pframe = rtw_set_fixed_ie(pframe, 1, &(action), &(pattrib->pktlen));
+
+	_rtw_memcpy(pframe, adapter_mac_addr(padapter), ETH_ALEN);
+	pframe += ETH_ALEN;
+	pattrib->pktlen += ETH_ALEN;
+
+	_rtw_memcpy(pframe, pTargetAddr, ETH_ALEN);
+	pframe += ETH_ALEN;
+	pattrib->pktlen += ETH_ALEN;
+
+	rtw_ft_update_mdie(padapter, pattrib, &pframe);
+	if (rtw_ft_update_rsnie(padapter, _TRUE, pattrib, &pframe))
+		rtw_ft_update_ftie(padapter, pattrib, &pframe);
+
+	pattrib->last_txcmdsz = pattrib->pktlen;
+	dump_mgntframe(padapter, pmgntframe);
+}
+
+void rtw_ft_report_evt(_adapter *padapter)
+{
+	struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
+	struct ft_roam_info *pft_roam = &(pmlmepriv->ft_roam);
+	struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv);
+	struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
+	WLAN_BSSID_EX *pnetwork = (WLAN_BSSID_EX *)&(pmlmeinfo->network);
+	struct cfg80211_ft_event_params ft_evt_parms;
+	_irqL irqL;
+
+	_rtw_memset(&ft_evt_parms, 0, sizeof(ft_evt_parms));
+	rtw_ft_update_stainfo(padapter, pnetwork);
+
+	if (!pnetwork)
+		goto err_2;
+
+	ft_evt_parms.ies_len = pft_roam->ft_event.ies_len;
+	ft_evt_parms.ies =  rtw_zmalloc(ft_evt_parms.ies_len);
+	if (ft_evt_parms.ies)
+		_rtw_memcpy((void *)ft_evt_parms.ies, pft_roam->ft_event.ies, ft_evt_parms.ies_len);
+	 else
+		goto err_2;
+
+	ft_evt_parms.target_ap = rtw_zmalloc(ETH_ALEN);
+	if (ft_evt_parms.target_ap)
+		_rtw_memcpy((void *)ft_evt_parms.target_ap, pnetwork->MacAddress, ETH_ALEN);
+	else
+		goto err_1;
+
+	ft_evt_parms.ric_ies = pft_roam->ft_event.ric_ies;
+	ft_evt_parms.ric_ies_len = pft_roam->ft_event.ric_ies_len;
+
+	rtw_ft_lock_set_status(padapter, RTW_FT_AUTHENTICATED_STA, &irqL);
+	rtw_cfg80211_ft_event(padapter, &ft_evt_parms);
+	RTW_INFO("FT: rtw_ft_report_evt\n");
+	rtw_mfree((u8 *)pft_roam->ft_event.target_ap, ETH_ALEN);
+err_1:
+	rtw_mfree((u8 *)ft_evt_parms.ies, ft_evt_parms.ies_len);
+err_2:
+	return;
+}
+
+void rtw_ft_report_reassoc_evt(_adapter *padapter, u8 *pMacAddr)
+{
+	struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv);
+	struct cmd_priv *pcmdpriv = &(padapter->cmdpriv);
+	struct cmd_obj *pcmd_obj = NULL;
+	struct stassoc_event *passoc_sta_evt = NULL;
+	struct C2HEvent_Header *pc2h_evt_hdr = NULL;
+	u8 *pevtcmd = NULL;
+	u32 cmdsz = 0;
+
+	pcmd_obj = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj));
+	if (pcmd_obj == NULL)
+		return;
+
+	cmdsz = (sizeof(struct stassoc_event) + sizeof(struct C2HEvent_Header));
+	pevtcmd = (u8 *)rtw_zmalloc(cmdsz);
+	if (pevtcmd == NULL) {
+		rtw_mfree((u8 *)pcmd_obj, sizeof(struct cmd_obj));
+		return;
+	}
+
+	_rtw_init_listhead(&pcmd_obj->list);
+	pcmd_obj->cmdcode = GEN_CMD_CODE(_Set_MLME_EVT);
+	pcmd_obj->cmdsz = cmdsz;
+	pcmd_obj->parmbuf = pevtcmd;
+	pcmd_obj->rsp = NULL;
+	pcmd_obj->rspsz  = 0;
+
+	pc2h_evt_hdr = (struct C2HEvent_Header *)(pevtcmd);
+	pc2h_evt_hdr->len = sizeof(struct stassoc_event);
+	pc2h_evt_hdr->ID = GEN_EVT_CODE(_FT_REASSOC);
+	pc2h_evt_hdr->seq = ATOMIC_INC_RETURN(&pmlmeext->event_seq);
+
+	passoc_sta_evt = (struct stassoc_event *)(pevtcmd + sizeof(struct C2HEvent_Header));
+	_rtw_memcpy((unsigned char *)(&(passoc_sta_evt->macaddr)), pMacAddr, ETH_ALEN);
+	rtw_enqueue_cmd(pcmdpriv, pcmd_obj);
+}
+
+void rtw_ft_link_timer_hdl(void *ctx)
+{
+	_adapter *padapter = (_adapter *)ctx;
+	struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv);
+	struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
+	struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
+	struct ft_roam_info *pft_roam = &(pmlmepriv->ft_roam);
+
+	if (rtw_ft_chk_status(padapter, RTW_FT_REQUESTING_STA)) {
+		if (pft_roam->ft_req_retry_cnt < RTW_FT_ACTION_REQ_LMT) {
+			pft_roam->ft_req_retry_cnt++;
+			rtw_ft_issue_action_req(padapter, (u8 *)pmlmepriv->roam_network->network.MacAddress);
+			_set_timer(&pmlmeext->ft_link_timer, REASSOC_TO);
+		} else {
+			pft_roam->ft_req_retry_cnt = 0;	
+			if (pmlmeinfo->state & WIFI_FW_ASSOC_SUCCESS)
+				rtw_ft_set_status(padapter, RTW_FT_ASSOCIATED_STA);
+			else
+				rtw_ft_reset_status(padapter);
+		}
+	}
+}
+
+void rtw_ft_roam_timer_hdl(void *ctx)
+{
+	_adapter *padapter = (_adapter *)ctx;
+	struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
+
+	receive_disconnect(padapter, pmlmepriv->cur_network.network.MacAddress
+				, WLAN_REASON_ACTIVE_ROAM, _FALSE);
+}
+
+void rtw_ft_roam_status_reset(_adapter *padapter)
+{
+	struct ft_roam_info *pft_roam = &(padapter->mlmepriv.ft_roam);
+
+	if ((rtw_to_roam(padapter) > 0) && 
+		(!rtw_ft_chk_status(padapter, RTW_FT_REQUESTED_STA))) {
+		rtw_ft_reset_status(padapter);
+	}	
+	
+	padapter->mlmepriv.ft_roam.ft_updated_bcn = _FALSE;
+}
+#endif
+
+u8 NULL_hdl(_adapter *padapter, u8 *pbuf)
+{
+	return H2C_SUCCESS;
+}
+
+#ifdef CONFIG_AUTO_AP_MODE
+void rtw_auto_ap_rx_msg_dump(_adapter *padapter, union recv_frame *precv_frame, u8 *ehdr_pos)
+{
+	struct rx_pkt_attrib *pattrib = &precv_frame->u.hdr.attrib;
+	struct sta_info *psta = precv_frame->u.hdr.psta;
+	struct ethhdr *ehdr = (struct ethhdr *)ehdr_pos;
+
+	RTW_INFO("eth rx: got eth_type=0x%x\n", ntohs(ehdr->h_proto));
+
+	if (psta && psta->isrc && psta->pid > 0) {
+		u16 rx_pid;
+
+		rx_pid = *(u16 *)(ehdr_pos + ETH_HLEN);
+
+		RTW_INFO("eth rx(pid=0x%x): sta("MAC_FMT") pid=0x%x\n",
+			 rx_pid, MAC_ARG(psta->cmn.mac_addr), psta->pid);
+
+		if (rx_pid == psta->pid) {
+			int i;
+			u16 len = *(u16 *)(ehdr_pos + ETH_HLEN + 2);
+			/* u16 ctrl_type = *(u16 *)(ehdr_pos + ETH_HLEN + 4); */
+
+			/* RTW_INFO("eth, RC: len=0x%x, ctrl_type=0x%x\n", len, ctrl_type);  */
+			RTW_INFO("eth, RC: len=0x%x\n", len);
+
+			for (i = 0; i < len; i++)
+				RTW_INFO("0x%x\n", *(ehdr_pos + ETH_HLEN + 4 + i));
+			/* RTW_INFO("0x%x\n", *(ehdr_pos + ETH_HLEN + 6 + i)); */
+
+			RTW_INFO("eth, RC-end\n");
+		}
+	}
+
+}
+
+void rtw_start_auto_ap(_adapter *adapter)
+{
+	RTW_INFO("%s\n", __FUNCTION__);
+
+	rtw_set_802_11_infrastructure_mode(adapter, Ndis802_11APMode);
+
+	rtw_setopmode_cmd(adapter, Ndis802_11APMode, RTW_CMDF_WAIT_ACK);
+}
+
+static int rtw_auto_ap_start_beacon(_adapter *adapter)
+{
+	int ret = 0;
+	u8 *pbuf = NULL;
+	uint len;
+	u8	supportRate[16];
+	int	sz = 0, rateLen;
+	u8	*ie;
+	u8	wireless_mode, oper_channel;
+	u8 ssid[3] = {0}; /* hidden ssid */
+	u32 ssid_len = sizeof(ssid);
+	struct mlme_priv *pmlmepriv = &(adapter->mlmepriv);
+
+
+	if (check_fwstate(pmlmepriv, WIFI_AP_STATE) != _TRUE)
+		return -EINVAL;
+
+
+	len = 128;
+	pbuf = rtw_zmalloc(len);
+	if (!pbuf)
+		return -ENOMEM;
+
+
+	/* generate beacon */
+	ie = pbuf;
+
+	/* timestamp will be inserted by hardware */
+	sz += 8;
+	ie += sz;
+
+	/* beacon interval : 2bytes */
+	*(u16 *)ie = cpu_to_le16((u16)100); /* BCN_INTERVAL=100; */
+	sz += 2;
+	ie += 2;
+
+	/* capability info */
+	*(u16 *)ie = 0;
+	*(u16 *)ie |= cpu_to_le16(cap_ESS);
+	*(u16 *)ie |= cpu_to_le16(cap_ShortPremble);
+	/* *(u16*)ie |= cpu_to_le16(cap_Privacy); */
+	sz += 2;
+	ie += 2;
+
+	/* SSID */
+	ie = rtw_set_ie(ie, _SSID_IE_, ssid_len, ssid, &sz);
+
+	/* supported rates */
+	wireless_mode = WIRELESS_11BG_24N;
+	rtw_set_supported_rate(supportRate, wireless_mode) ;
+	rateLen = rtw_get_rateset_len(supportRate);
+	if (rateLen > 8)
+		ie = rtw_set_ie(ie, _SUPPORTEDRATES_IE_, 8, supportRate, &sz);
+	else
+		ie = rtw_set_ie(ie, _SUPPORTEDRATES_IE_, rateLen, supportRate, &sz);
+
+
+	/* DS parameter set */
+	if (rtw_mi_check_status(adapter, MI_LINKED))
+		oper_channel = rtw_mi_get_union_chan(adapter);
+	else
+		oper_channel = adapter_to_dvobj(adapter)->oper_channel;
+
+	ie = rtw_set_ie(ie, _DSSET_IE_, 1, &oper_channel, &sz);
+
+	/* ext supported rates */
+	if (rateLen > 8)
+		ie = rtw_set_ie(ie, _EXT_SUPPORTEDRATES_IE_, (rateLen - 8), (supportRate + 8), &sz);
+
+	RTW_INFO("%s, start auto ap beacon sz=%d\n", __FUNCTION__, sz);
+
+	/* lunch ap mode & start to issue beacon */
+	if (rtw_check_beacon_data(adapter, pbuf,  sz) == _SUCCESS) {
+
+	} else
+		ret = -EINVAL;
+
+
+	rtw_mfree(pbuf, len);
+
+	return ret;
+
+}
+#endif/* CONFIG_AUTO_AP_MODE */
+
+u8 setopmode_hdl(_adapter *padapter, u8 *pbuf)
+{
+	u8	type;
+	struct mlme_ext_priv	*pmlmeext = &padapter->mlmeextpriv;
+	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
+	struct setopmode_parm *psetop = (struct setopmode_parm *)pbuf;
+
+	if (psetop->mode == Ndis802_11APMode
+		|| psetop->mode == Ndis802_11_mesh
+	) {
+		pmlmeinfo->state = WIFI_FW_AP_STATE;
+		type = _HW_STATE_AP_;
+	} else if (psetop->mode == Ndis802_11Infrastructure) {
+		pmlmeinfo->state &= ~(BIT(0) | BIT(1)); /* clear state */
+		pmlmeinfo->state |= WIFI_FW_STATION_STATE;/* set to 	STATION_STATE */
+		type = _HW_STATE_STATION_;
+	} else if (psetop->mode == Ndis802_11IBSS)
+		type = _HW_STATE_ADHOC_;
+	else if (psetop->mode == Ndis802_11Monitor)
+		type = _HW_STATE_MONITOR_;
+	else
+		type = _HW_STATE_NOLINK_;
+
+#ifdef CONFIG_AP_PORT_SWAP
+	rtw_hal_set_hwreg(padapter, HW_VAR_PORT_SWITCH, (u8 *)(&type));
+#endif
+
+	rtw_hal_set_hwreg(padapter, HW_VAR_SET_OPMODE, (u8 *)(&type));
+
+#ifdef CONFIG_AUTO_AP_MODE
+	if (psetop->mode == Ndis802_11APMode)
+		rtw_auto_ap_start_beacon(padapter);
+#endif
+
+	if (rtw_port_switch_chk(padapter) == _TRUE) {
+		rtw_hal_set_hwreg(padapter, HW_VAR_PORT_SWITCH, NULL);
+
+		if (psetop->mode == Ndis802_11APMode)
+			adapter_to_pwrctl(padapter)->fw_psmode_iface_id = 0xff; /* ap mode won't dowload rsvd pages */
+		else if (psetop->mode == Ndis802_11Infrastructure) {
+#ifdef CONFIG_LPS
+			_adapter *port0_iface = dvobj_get_port0_adapter(adapter_to_dvobj(padapter));
+			if (port0_iface)
+				rtw_lps_ctrl_wk_cmd(port0_iface, LPS_CTRL_CONNECT, 0);
+#endif
+		}
+	}
+
+#ifdef CONFIG_BT_COEXIST
+	if (psetop->mode == Ndis802_11APMode
+		|| psetop->mode == Ndis802_11_mesh
+		|| psetop->mode == Ndis802_11Monitor
+	) {
+		/* Do this after port switch to */
+		/* prevent from downloading rsvd page to wrong port */
+		rtw_btcoex_MediaStatusNotify(padapter, 1); /* connect */
+	}
+#endif /* CONFIG_BT_COEXIST */
+
+	return H2C_SUCCESS;
+
+}
+
+u8 createbss_hdl(_adapter *padapter, u8 *pbuf)
+{
+	struct mlme_ext_priv	*pmlmeext = &padapter->mlmeextpriv;
+	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
+	WLAN_BSSID_EX	*pnetwork = (WLAN_BSSID_EX *)(&(pmlmeinfo->network));
+	WLAN_BSSID_EX	*pdev_network = &padapter->registrypriv.dev_network;
+	struct createbss_parm *parm = (struct createbss_parm *)pbuf;
+	u8 ret = H2C_SUCCESS;
+	/* u8	initialgain; */
+
+#ifdef CONFIG_AP_MODE
+	if ((parm->req_ch == 0 && pmlmeinfo->state == WIFI_FW_AP_STATE)
+		|| parm->req_ch != 0
+	) {
+		start_bss_network(padapter, parm);
+		goto exit;
+	}
+#endif
+
+	/* below is for ad-hoc master */
+	if (parm->adhoc) {
+		rtw_warn_on(pdev_network->InfrastructureMode != Ndis802_11IBSS);
+		rtw_joinbss_reset(padapter);
+
+		pmlmeext->cur_bwmode = CHANNEL_WIDTH_20;
+		pmlmeext->cur_ch_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
+		pmlmeinfo->ERP_enable = 0;
+		pmlmeinfo->WMM_enable = 0;
+		pmlmeinfo->HT_enable = 0;
+		pmlmeinfo->HT_caps_enable = 0;
+		pmlmeinfo->HT_info_enable = 0;
+		pmlmeinfo->agg_enable_bitmap = 0;
+		pmlmeinfo->candidate_tid_bitmap = 0;
+
+		/* cancel link timer */
+		_cancel_timer_ex(&pmlmeext->link_timer);
+
+		/* clear CAM */
+		flush_all_cam_entry(padapter);
+
+		pdev_network->Length = get_WLAN_BSSID_EX_sz(pdev_network);
+		_rtw_memcpy(pnetwork, pdev_network, FIELD_OFFSET(WLAN_BSSID_EX, IELength));
+		pnetwork->IELength = pdev_network->IELength;
+
+		if (pnetwork->IELength > MAX_IE_SZ) {
+			ret = H2C_PARAMETERS_ERROR;
+			goto ibss_post_hdl;
+		}
+
+		_rtw_memcpy(pnetwork->IEs, pdev_network->IEs, pnetwork->IELength);
+		start_create_ibss(padapter);
+	} else {
+		rtw_warn_on(1);
+		ret = H2C_PARAMETERS_ERROR;
+	}
+
+ibss_post_hdl:
+	rtw_create_ibss_post_hdl(padapter, ret);
+
+exit:
+	return ret;
+}
+
+u8 join_cmd_hdl(_adapter *padapter, u8 *pbuf)
+{
+	u8	join_type;
+	PNDIS_802_11_VARIABLE_IEs	pIE;
+	struct mlme_ext_priv	*pmlmeext = &padapter->mlmeextpriv;
+	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
+	WLAN_BSSID_EX		*pnetwork = (WLAN_BSSID_EX *)(&(pmlmeinfo->network));
+#ifdef CONFIG_ANTENNA_DIVERSITY
+	struct joinbss_parm	*pparm = (struct joinbss_parm *)pbuf;
+#endif /* CONFIG_ANTENNA_DIVERSITY */
+	u32 i;
+	/* u8	initialgain; */
+	/* u32	acparm; */
+	u8 u_ch, u_bw, u_offset;
+	u8 doiqk = _FALSE;
+
+	/* check already connecting to AP or not */
+	if (pmlmeinfo->state & WIFI_FW_ASSOC_SUCCESS) {
+		if (pmlmeinfo->state & WIFI_FW_STATION_STATE)
+			issue_deauth_ex(padapter, pnetwork->MacAddress, WLAN_REASON_DEAUTH_LEAVING, 1, 100);
+		pmlmeinfo->state = WIFI_FW_NULL_STATE;
+
+		/* clear CAM */
+		flush_all_cam_entry(padapter);
+
+		_cancel_timer_ex(&pmlmeext->link_timer);
+
+		/* set MSR to nolink->infra. mode		 */
+		/* Set_MSR(padapter, _HW_STATE_NOLINK_); */
+		Set_MSR(padapter, _HW_STATE_STATION_);
+
+
+		rtw_hal_set_hwreg(padapter, HW_VAR_MLME_DISCONNECT, 0);
+		if (pmlmeinfo->state & WIFI_FW_STATION_STATE)
+			rtw_hal_rcr_set_chk_bssid(padapter, MLME_STA_DISCONNECTED);
+	}
+
+#ifdef CONFIG_ANTENNA_DIVERSITY
+	rtw_antenna_select_cmd(padapter, pparm->network.PhyInfo.Optimum_antenna, _FALSE);
+#endif
+
+#ifdef CONFIG_WAPI_SUPPORT
+	rtw_wapi_clear_all_cam_entry(padapter);
+#endif
+
+	rtw_joinbss_reset(padapter);
+
+	pmlmeinfo->ERP_enable = 0;
+	pmlmeinfo->WMM_enable = 0;
+	pmlmeinfo->HT_enable = 0;
+	pmlmeinfo->HT_caps_enable = 0;
+	pmlmeinfo->HT_info_enable = 0;
+	pmlmeinfo->agg_enable_bitmap = 0;
+	pmlmeinfo->candidate_tid_bitmap = 0;
+	pmlmeinfo->bwmode_updated = _FALSE;
+	/* pmlmeinfo->assoc_AP_vendor = HT_IOT_PEER_MAX; */
+	pmlmeinfo->VHT_enable = 0;
+#ifdef ROKU_PRIVATE
+	pmlmeinfo->ht_vht_received = 0;
+	_rtw_memset(pmlmeinfo->SupportedRates_infra_ap, 0, NDIS_802_11_LENGTH_RATES_EX);
+#endif /* ROKU_PRIVATE */
+	_rtw_memcpy(pnetwork, pbuf, FIELD_OFFSET(WLAN_BSSID_EX, IELength));
+	pnetwork->IELength = ((WLAN_BSSID_EX *)pbuf)->IELength;
+
+	if (pnetwork->IELength > MAX_IE_SZ) /* Check pbuf->IELength */
+		return H2C_PARAMETERS_ERROR;
+
+	if (pnetwork->IELength < 2) {
+		report_join_res(padapter, (-4), WLAN_STATUS_UNSPECIFIED_FAILURE);
+		return H2C_SUCCESS;
+	}
+	_rtw_memcpy(pnetwork->IEs, ((WLAN_BSSID_EX *)pbuf)->IEs, pnetwork->IELength);
+
+	pmlmeinfo->bcn_interval = get_beacon_interval(pnetwork);
+
+	/* Check AP vendor to move rtw_joinbss_cmd() */
+	/* pmlmeinfo->assoc_AP_vendor = check_assoc_AP(pnetwork->IEs, pnetwork->IELength); */
+
+	/* sizeof(NDIS_802_11_FIXED_IEs)	 */
+	for (i = _FIXED_IE_LENGTH_ ; i < pnetwork->IELength - 2 ;) {
+		pIE = (PNDIS_802_11_VARIABLE_IEs)(pnetwork->IEs + i);
+
+		switch (pIE->ElementID) {
+		case _VENDOR_SPECIFIC_IE_: /* Get WMM IE. */
+			if (_rtw_memcmp(pIE->data, WMM_OUI, 4))
+				WMM_param_handler(padapter, pIE);
+			break;
+
+#ifdef CONFIG_80211N_HT
+		case _HT_CAPABILITY_IE_:	/* Get HT Cap IE. */
+			pmlmeinfo->HT_caps_enable = 1;
+			break;
+
+		case _HT_EXTRA_INFO_IE_:	/* Get HT Info IE. */
+			pmlmeinfo->HT_info_enable = 1;
+			break;
+#endif /* CONFIG_80211N_HT */
+
+#ifdef CONFIG_80211AC_VHT
+		case EID_VHTCapability: /* Get VHT Cap IE. */
+			pmlmeinfo->VHT_enable = 1;
+			break;
+
+		case EID_VHTOperation: /* Get VHT Operation IE. */
+			break;
+#endif /* CONFIG_80211AC_VHT */
+		default:
+			break;
+		}
+
+		i += (pIE->Length + 2);
+	}
+
+	rtw_bss_get_chbw(pnetwork
+		, &pmlmeext->cur_channel, &pmlmeext->cur_bwmode, &pmlmeext->cur_ch_offset, 1, 1);
+
+	rtw_adjust_chbw(padapter, pmlmeext->cur_channel, &pmlmeext->cur_bwmode, &pmlmeext->cur_ch_offset);
+
+#if 0
+	if (padapter->registrypriv.wifi_spec) {
+		/* for WiFi test, follow WMM test plan spec */
+		acparm = 0x002F431C; /* VO */
+		rtw_hal_set_hwreg(padapter, HW_VAR_AC_PARAM_VO, (u8 *)(&acparm));
+		acparm = 0x005E541C; /* VI */
+		rtw_hal_set_hwreg(padapter, HW_VAR_AC_PARAM_VI, (u8 *)(&acparm));
+		acparm = 0x0000A525; /* BE */
+		rtw_hal_set_hwreg(padapter, HW_VAR_AC_PARAM_BE, (u8 *)(&acparm));
+		acparm = 0x0000A549; /* BK */
+		rtw_hal_set_hwreg(padapter, HW_VAR_AC_PARAM_BK, (u8 *)(&acparm));
+
+		/* for WiFi test, mixed mode with intel STA under bg mode throughput issue */
+		if (padapter->mlmepriv.htpriv.ht_option == _FALSE) {
+			acparm = 0x00004320;
+			rtw_hal_set_hwreg(padapter, HW_VAR_AC_PARAM_BE, (u8 *)(&acparm));
+		}
+	} else {
+		acparm = 0x002F3217; /* VO */
+		rtw_hal_set_hwreg(padapter, HW_VAR_AC_PARAM_VO, (u8 *)(&acparm));
+		acparm = 0x005E4317; /* VI */
+		rtw_hal_set_hwreg(padapter, HW_VAR_AC_PARAM_VI, (u8 *)(&acparm));
+		acparm = 0x00105320; /* BE */
+		rtw_hal_set_hwreg(padapter, HW_VAR_AC_PARAM_BE, (u8 *)(&acparm));
+		acparm = 0x0000A444; /* BK */
+		rtw_hal_set_hwreg(padapter, HW_VAR_AC_PARAM_BK, (u8 *)(&acparm));
+	}
+#endif
+
+	/* check channel, bandwidth, offset and switch */
+	if (rtw_chk_start_clnt_join(padapter, &u_ch, &u_bw, &u_offset) == _FAIL) {
+		report_join_res(padapter, (-4), WLAN_STATUS_UNSPECIFIED_FAILURE);
+		return H2C_SUCCESS;
+	}
+
+	/* disable dynamic functions, such as high power, DIG */
+	/*rtw_phydm_func_disable_all(padapter);*/
+
+	/* config the initial gain under linking, need to write the BB registers */
+	/* initialgain = 0x1E; */
+	/*rtw_hal_set_odm_var(padapter, HAL_ODM_INITIAL_GAIN, &initialgain, _FALSE);*/
+
+	rtw_hal_set_hwreg(padapter, HW_VAR_BSSID, pmlmeinfo->network.MacAddress);
+	if (MLME_IS_STA(padapter))
+		rtw_hal_rcr_set_chk_bssid(padapter, MLME_STA_CONNECTING);
+	else
+		rtw_hal_rcr_set_chk_bssid(padapter, MLME_ADHOC_STARTED);
+
+	join_type = 0;
+	rtw_hal_set_hwreg(padapter, HW_VAR_MLME_JOIN, (u8 *)(&join_type));
+
+	doiqk = _TRUE;
+	rtw_hal_set_hwreg(padapter , HW_VAR_DO_IQK , &doiqk);
+
+	set_channel_bwmode(padapter, u_ch, u_offset, u_bw);
+	rtw_mi_update_union_chan_inf(padapter, u_ch, u_offset, u_bw);
+
+	doiqk = _FALSE;
+	rtw_hal_set_hwreg(padapter , HW_VAR_DO_IQK , &doiqk);
+
+	/* cancel link timer */
+	_cancel_timer_ex(&pmlmeext->link_timer);
+
+	start_clnt_join(padapter);
+
+	return H2C_SUCCESS;
+
+}
+
+u8 disconnect_hdl(_adapter *padapter, unsigned char *pbuf)
+{
+#ifdef CONFIG_DFS
+	struct rf_ctl_t *rfctl = adapter_to_rfctl(padapter);
+#endif
+	struct disconnect_parm *param = (struct disconnect_parm *)pbuf;
+	struct mlme_ext_priv	*pmlmeext = &padapter->mlmeextpriv;
+	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
+	WLAN_BSSID_EX		*pnetwork = (WLAN_BSSID_EX *)(&(pmlmeinfo->network));
+	u8 val8;
+
+	if (is_client_associated_to_ap(padapter)
+		#ifdef CONFIG_DFS
+		&& !IS_RADAR_DETECTED(rfctl) && !rfctl->csa_ch
+		#endif
+	) {
+		#ifdef CONFIG_PLATFORM_ROCKCHIPS
+		/* To avoid connecting to AP fail during resume process, change retry count from 5 to 1 */
+		issue_deauth_ex(padapter, pnetwork->MacAddress, WLAN_REASON_DEAUTH_LEAVING, 1, 100);
+		#else
+		issue_deauth_ex(padapter, pnetwork->MacAddress, WLAN_REASON_DEAUTH_LEAVING, param->deauth_timeout_ms / 100, 100);
+		#endif /* CONFIG_PLATFORM_ROCKCHIPS */
+	}
+
+#ifndef CONFIG_SUPPORT_MULTI_BCN
+	if (((pmlmeinfo->state & 0x03) == WIFI_FW_ADHOC_STATE) || ((pmlmeinfo->state & 0x03) == WIFI_FW_AP_STATE)) {
+		/* Stop BCN */
+		val8 = 0;
+		rtw_hal_set_hwreg(padapter, HW_VAR_BCN_FUNC, (u8 *)(&val8));
+	}
+#endif
+
+	rtw_mlmeext_disconnect(padapter);
+
+	rtw_free_uc_swdec_pending_queue(padapter);
+
+	rtw_sta_mstatus_report(padapter);
+
+	return	H2C_SUCCESS;
+}
+
+static const char *const _scan_state_str[] = {
+	"SCAN_DISABLE",
+	"SCAN_START",
+	"SCAN_PS_ANNC_WAIT",
+	"SCAN_ENTER",
+	"SCAN_PROCESS",
+	"SCAN_BACKING_OP",
+	"SCAN_BACK_OP",
+	"SCAN_LEAVING_OP",
+	"SCAN_LEAVE_OP",
+	"SCAN_SW_ANTDIV_BL",
+	"SCAN_TO_P2P_LISTEN",
+	"SCAN_P2P_LISTEN",
+	"SCAN_COMPLETE",
+	"SCAN_STATE_MAX",
+};
+
+const char *scan_state_str(u8 state)
+{
+	state = (state >= SCAN_STATE_MAX) ? SCAN_STATE_MAX : state;
+	return _scan_state_str[state];
+}
+
+static bool scan_abort_hdl(_adapter *adapter)
+{
+	struct mlme_ext_priv *pmlmeext = &adapter->mlmeextpriv;
+	struct ss_res *ss = &pmlmeext->sitesurvey_res;
+#ifdef CONFIG_P2P
+	struct wifidirect_info *pwdinfo = &adapter->wdinfo;
+#endif
+	bool ret = _FALSE;
+
+	if (pmlmeext->scan_abort == _TRUE) {
+#ifdef CONFIG_P2P
+		if (!rtw_p2p_chk_state(&adapter->wdinfo, P2P_STATE_NONE)) {
+			rtw_p2p_findphase_ex_set(pwdinfo, P2P_FINDPHASE_EX_MAX);
+			ss->channel_idx = 3;
+			RTW_INFO("%s idx:%d, cnt:%u\n", __FUNCTION__
+				 , ss->channel_idx
+				 , pwdinfo->find_phase_state_exchange_cnt
+				);
+		} else
+#endif
+		{
+			ss->channel_idx = ss->ch_num;
+			RTW_INFO("%s idx:%d\n", __FUNCTION__
+				 , ss->channel_idx
+				);
+		}
+		pmlmeext->scan_abort = _FALSE;
+		ret = _TRUE;
+	}
+
+	return ret;
+}
+
+u8 rtw_scan_sparse(_adapter *adapter, struct rtw_ieee80211_channel *ch, u8 ch_num)
+{
+	/* interval larger than this is treated as backgroud scan */
+#ifndef RTW_SCAN_SPARSE_BG_INTERVAL_MS
+#define RTW_SCAN_SPARSE_BG_INTERVAL_MS 12000
+#endif
+
+#ifndef RTW_SCAN_SPARSE_CH_NUM_MIRACAST
+#define RTW_SCAN_SPARSE_CH_NUM_MIRACAST 1
+#endif
+#ifndef RTW_SCAN_SPARSE_CH_NUM_BG
+#define RTW_SCAN_SPARSE_CH_NUM_BG 4
+#endif
+#ifdef CONFIG_LAYER2_ROAMING
+#ifndef RTW_SCAN_SPARSE_CH_NUM_ROAMING_ACTIVE
+#define RTW_SCAN_SPARSE_CH_NUM_ROAMING_ACTIVE 1
+#endif
+#endif
+
+#define SCAN_SPARSE_CH_NUM_INVALID 255
+
+	static u8 token = 255;
+	u32 interval;
+	bool busy_traffic = _FALSE;
+	bool miracast_enabled = _FALSE;
+	bool bg_scan = _FALSE;
+	u8 max_allow_ch = SCAN_SPARSE_CH_NUM_INVALID;
+	u8 scan_division_num;
+	u8 ret_num = ch_num;
+	struct registry_priv *regsty = dvobj_to_regsty(adapter_to_dvobj(adapter));
+	struct mlme_ext_priv *mlmeext = &adapter->mlmeextpriv;
+
+	if (regsty->wifi_spec)
+		goto exit;
+
+	/* assume ch_num > 6 is normal scan */
+	if (ch_num <= 6)
+		goto exit;
+
+	if (mlmeext->last_scan_time == 0)
+		mlmeext->last_scan_time = rtw_get_current_time();
+
+	interval = rtw_get_passing_time_ms(mlmeext->last_scan_time);
+
+
+	if (rtw_mi_busy_traffic_check(adapter, _FALSE))
+		busy_traffic = _TRUE;
+
+	if (rtw_mi_check_miracast_enabled(adapter))
+		miracast_enabled = _TRUE;
+
+	if (interval > RTW_SCAN_SPARSE_BG_INTERVAL_MS)
+		bg_scan = _TRUE;
+
+	/* max_allow_ch by conditions*/
+
+#if RTW_SCAN_SPARSE_MIRACAST
+	if (miracast_enabled == _TRUE && busy_traffic == _TRUE)
+		max_allow_ch = rtw_min(max_allow_ch, RTW_SCAN_SPARSE_CH_NUM_MIRACAST);
+#endif
+
+#if RTW_SCAN_SPARSE_BG
+	if (bg_scan == _TRUE)
+		max_allow_ch = rtw_min(max_allow_ch, RTW_SCAN_SPARSE_CH_NUM_BG);
+#endif
+
+#if  defined(CONFIG_LAYER2_ROAMING) && defined(RTW_SCAN_SPARSE_ROAMING_ACTIVE)
+	if (rtw_chk_roam_flags(adapter, RTW_ROAM_ACTIVE)) {
+		if (busy_traffic == _TRUE && adapter->mlmepriv.need_to_roam == _TRUE)
+			max_allow_ch = rtw_min(max_allow_ch, RTW_SCAN_SPARSE_CH_NUM_ROAMING_ACTIVE);
+	}
+#endif
+
+
+	if (max_allow_ch != SCAN_SPARSE_CH_NUM_INVALID) {
+		int i;
+		int k = 0;
+
+		scan_division_num = (ch_num / max_allow_ch) + ((ch_num % max_allow_ch) ? 1 : 0);
+		token = (token + 1) % scan_division_num;
+
+		if (0)
+			RTW_INFO("scan_division_num:%u, token:%u\n", scan_division_num, token);
+
+		for (i = 0; i < ch_num; i++) {
+			if (ch[i].hw_value && (i % scan_division_num) == token
+			   ) {
+				if (i != k)
+					_rtw_memcpy(&ch[k], &ch[i], sizeof(struct rtw_ieee80211_channel));
+				k++;
+			}
+		}
+
+		_rtw_memset(&ch[k], 0, sizeof(struct rtw_ieee80211_channel));
+
+		ret_num = k;
+		mlmeext->last_scan_time = rtw_get_current_time();
+	}
+
+exit:
+	return ret_num;
+}
+
+#ifdef CONFIG_SCAN_BACKOP
+u8 rtw_scan_backop_decision(_adapter *adapter)
+{
+	struct mlme_ext_priv *mlmeext = &adapter->mlmeextpriv;
+	struct mi_state mstate;
+	u8 backop_flags = 0;
+
+	rtw_mi_status(adapter, &mstate);
+
+	if ((MSTATE_STA_LD_NUM(&mstate) && mlmeext_chk_scan_backop_flags_sta(mlmeext, SS_BACKOP_EN))
+		|| (MSTATE_STA_NUM(&mstate) && mlmeext_chk_scan_backop_flags_sta(mlmeext, SS_BACKOP_EN_NL)))
+		backop_flags |= mlmeext_scan_backop_flags_sta(mlmeext);
+
+#ifdef CONFIG_AP_MODE
+	if ((MSTATE_AP_LD_NUM(&mstate) && mlmeext_chk_scan_backop_flags_ap(mlmeext, SS_BACKOP_EN))
+		|| (MSTATE_AP_NUM(&mstate) && mlmeext_chk_scan_backop_flags_ap(mlmeext, SS_BACKOP_EN_NL)))
+		backop_flags |= mlmeext_scan_backop_flags_ap(mlmeext);
+#endif
+
+#ifdef CONFIG_RTW_MESH
+	if ((MSTATE_MESH_LD_NUM(&mstate) && mlmeext_chk_scan_backop_flags_mesh(mlmeext, SS_BACKOP_EN))
+		|| (MSTATE_MESH_NUM(&mstate) && mlmeext_chk_scan_backop_flags_mesh(mlmeext, SS_BACKOP_EN_NL)))
+		backop_flags |= mlmeext_scan_backop_flags_mesh(mlmeext);
+#endif
+
+	return backop_flags;
+}
+#endif
+
+#define SCANNING_TIMEOUT_EX	2000
+u32 rtw_scan_timeout_decision(_adapter *padapter)
+{
+	u32 back_op_times= 0;
+	u8 max_chan_num;
+	u16 scan_ms;
+	struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
+	struct ss_res *ss = &pmlmeext->sitesurvey_res;
+
+	if (is_supported_5g(padapter->registrypriv.wireless_mode)
+		&& IsSupported24G(padapter->registrypriv.wireless_mode)) 
+		max_chan_num = MAX_CHANNEL_NUM;/* dual band */
+	else
+		max_chan_num = MAX_CHANNEL_NUM_2G;/*single band*/
+
+	#ifdef CONFIG_SCAN_BACKOP
+	if (rtw_scan_backop_decision(padapter))
+		back_op_times = (max_chan_num / ss->scan_cnt_max) * ss->backop_ms;
+	#endif
+
+	if (ss->duration)
+		scan_ms = ss->duration;
+	else
+	#if defined(CONFIG_RTW_ACS) && defined(CONFIG_RTW_ACS_DBG)
+	if (IS_ACS_ENABLE(padapter) && rtw_is_acs_st_valid(padapter))
+		scan_ms = rtw_acs_get_adv_st(padapter);
+	else
+	#endif /*CONFIG_RTW_ACS*/
+		scan_ms = ss->scan_ch_ms;
+
+	ss->scan_timeout_ms = (scan_ms * max_chan_num) + back_op_times + SCANNING_TIMEOUT_EX;
+	#ifdef DBG_SITESURVEY
+	RTW_INFO("%s , scan_timeout_ms = %d (ms)\n", __func__, ss->scan_timeout_ms);
+	#endif /*DBG_SITESURVEY*/
+	return ss->scan_timeout_ms;
+}
+
+static int rtw_scan_ch_decision(_adapter *padapter, struct rtw_ieee80211_channel *out,
+		u32 out_num, struct rtw_ieee80211_channel *in, u32 in_num)
+{
+	int i, j;
+	int set_idx;
+	u8 chan;
+	struct rf_ctl_t *rfctl = adapter_to_rfctl(padapter);
+
+	/* clear first */
+	_rtw_memset(out, 0, sizeof(struct rtw_ieee80211_channel) * out_num);
+
+	/* acquire channels from in */
+	j = 0;
+	for (i = 0; i < in_num; i++) {
+
+		if (0)
+			RTW_INFO(FUNC_ADPT_FMT" "CHAN_FMT"\n", FUNC_ADPT_ARG(padapter), CHAN_ARG(&in[i]));
+
+		if (!in[i].hw_value || (in[i].flags & RTW_IEEE80211_CHAN_DISABLED))
+			continue;
+		if (rtw_mlme_band_check(padapter, in[i].hw_value) == _FALSE)
+			continue;
+
+		set_idx = rtw_chset_search_ch(rfctl->channel_set, in[i].hw_value);
+		if (set_idx >= 0) {
+			if (j >= out_num) {
+				RTW_PRINT(FUNC_ADPT_FMT" out_num:%u not enough\n",
+					  FUNC_ADPT_ARG(padapter), out_num);
+				break;
+			}
+
+			_rtw_memcpy(&out[j], &in[i], sizeof(struct rtw_ieee80211_channel));
+
+			if (rfctl->channel_set[set_idx].ScanType == SCAN_PASSIVE)
+				out[j].flags |= RTW_IEEE80211_CHAN_PASSIVE_SCAN;
+
+			j++;
+		}
+		if (j >= out_num)
+			break;
+	}
+
+	/* if out is empty, use channel_set as default */
+	if (j == 0) {
+		for (i = 0; i < rfctl->max_chan_nums; i++) {
+			chan = rfctl->channel_set[i].ChannelNum;
+			if (rtw_mlme_band_check(padapter, chan) == _TRUE) {
+				if (rtw_mlme_ignore_chan(padapter, chan) == _TRUE)
+					continue;
+
+				if (0)
+					RTW_INFO(FUNC_ADPT_FMT" ch:%u\n", FUNC_ADPT_ARG(padapter), chan);
+
+				if (j >= out_num) {
+					RTW_PRINT(FUNC_ADPT_FMT" out_num:%u not enough\n",
+						FUNC_ADPT_ARG(padapter), out_num);
+					break;
+				}
+
+				out[j].hw_value = chan;
+
+				if (rfctl->channel_set[i].ScanType == SCAN_PASSIVE)
+					out[j].flags |= RTW_IEEE80211_CHAN_PASSIVE_SCAN;
+
+				j++;
+			}
+		}
+	}
+
+	/* scan_sparse */
+	j = rtw_scan_sparse(padapter, out, j);
+
+	return j;
+}
+
+static void sitesurvey_res_reset(_adapter *adapter, struct sitesurvey_parm *parm)
+{
+	struct ss_res *ss = &adapter->mlmeextpriv.sitesurvey_res;
+	RT_CHANNEL_INFO *chset = adapter_to_chset(adapter);
+	int i;
+
+	ss->bss_cnt = 0;
+	ss->channel_idx = 0;
+#ifdef CONFIG_DFS
+	ss->dfs_ch_ssid_scan = 0;
+#endif
+	ss->igi_scan = 0;
+	ss->igi_before_scan = 0;
+#ifdef CONFIG_SCAN_BACKOP
+	ss->scan_cnt = 0;
+#endif
+#if defined(CONFIG_ANTENNA_DIVERSITY) || defined(DBG_SCAN_SW_ANTDIV_BL)
+	ss->is_sw_antdiv_bl_scan = 0;
+#endif
+	ss->ssid_num = 0;
+	for (i = 0; i < RTW_SSID_SCAN_AMOUNT; i++) {
+		if (parm->ssid[i].SsidLength) {
+			_rtw_memcpy(ss->ssid[i].Ssid, parm->ssid[i].Ssid, IW_ESSID_MAX_SIZE);
+			ss->ssid[i].SsidLength = parm->ssid[i].SsidLength;
+			ss->ssid_num++;
+		} else
+			ss->ssid[i].SsidLength = 0;
+	}
+
+	ss->ch_num = rtw_scan_ch_decision(adapter
+					  , ss->ch, RTW_CHANNEL_SCAN_AMOUNT
+					  , parm->ch, parm->ch_num
+					 );
+
+#ifdef CONFIG_DFS
+	for (i = 0; i < MAX_CHANNEL_NUM; i++)
+		chset[i].hidden_bss_cnt = 0;
+#endif
+
+	ss->bw = parm->bw;
+	ss->igi = parm->igi;
+	ss->token = parm->token;
+	ss->duration = parm->duration;
+	ss->scan_mode = parm->scan_mode;
+	ss->token = parm->token;
+}
+
+static u8 sitesurvey_pick_ch_behavior(_adapter *padapter, u8 *ch, RT_SCAN_TYPE *type)
+{
+	u8 next_state;
+	u8 scan_ch = 0;
+	RT_SCAN_TYPE scan_type = SCAN_PASSIVE;
+	struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
+	struct ss_res *ss = &pmlmeext->sitesurvey_res;
+	struct rf_ctl_t *rfctl = adapter_to_rfctl(padapter);
+	int ch_set_idx;
+#ifdef CONFIG_P2P
+	struct wifidirect_info *pwdinfo = &padapter->wdinfo;
+#endif
+#ifdef CONFIG_SCAN_BACKOP
+	u8 backop_flags = 0;
+#endif
+
+	/* handle scan abort request */
+	scan_abort_hdl(padapter);
+
+#ifdef CONFIG_P2P
+	if (pwdinfo->rx_invitereq_info.scan_op_ch_only || pwdinfo->p2p_info.scan_op_ch_only) {
+		if (pwdinfo->rx_invitereq_info.scan_op_ch_only)
+			scan_ch = pwdinfo->rx_invitereq_info.operation_ch[ss->channel_idx];
+		else
+			scan_ch = pwdinfo->p2p_info.operation_ch[ss->channel_idx];
+		scan_type = SCAN_ACTIVE;
+	} else if (rtw_p2p_findphase_ex_is_social(pwdinfo)) {
+		/*
+		* Commented by Albert 2011/06/03
+		* The driver is in the find phase, it should go through the social channel.
+		*/
+		scan_ch = pwdinfo->social_chan[ss->channel_idx];
+		ch_set_idx = rtw_chset_search_ch(rfctl->channel_set, scan_ch);
+		if (ch_set_idx >= 0)
+			scan_type = rfctl->channel_set[ch_set_idx].ScanType;
+		else
+			scan_type = SCAN_ACTIVE;
+	} else
+#endif /* CONFIG_P2P */
+	{
+		struct rtw_ieee80211_channel *ch;
+
+		#ifdef CONFIG_SCAN_BACKOP
+		backop_flags = rtw_scan_backop_decision(padapter);
+		#endif
+
+#ifdef CONFIG_DFS
+		#ifdef CONFIG_SCAN_BACKOP
+		if (!(backop_flags && ss->scan_cnt >= ss->scan_cnt_max))
+		#endif
+		{
+			#ifdef CONFIG_RTW_WIFI_HAL
+			if (adapter_to_dvobj(padapter)->nodfs) {
+				while ( ss->channel_idx < ss->ch_num && rtw_is_dfs_ch(ss->ch[ss->channel_idx].hw_value))
+					ss->channel_idx++;
+			} else
+			#endif
+			if (ss->channel_idx != 0 && ss->dfs_ch_ssid_scan == 0
+				&& pmlmeext->sitesurvey_res.ssid_num
+				&& rtw_is_dfs_ch(ss->ch[ss->channel_idx - 1].hw_value)
+			) {
+				ch_set_idx = rtw_chset_search_ch(rfctl->channel_set, ss->ch[ss->channel_idx - 1].hw_value);
+				if (ch_set_idx != -1 && rfctl->channel_set[ch_set_idx].hidden_bss_cnt
+					&& (!IS_DFS_SLAVE_WITH_RD(rfctl)
+						|| rtw_odm_dfs_domain_unknown(rfctl_to_dvobj(rfctl))
+						|| !CH_IS_NON_OCP(&rfctl->channel_set[ch_set_idx]))
+				) {
+					ss->channel_idx--;
+					ss->dfs_ch_ssid_scan = 1;
+				}
+			} else
+				ss->dfs_ch_ssid_scan = 0;
+		}
+#endif /* CONFIG_DFS */
+
+		if (ss->channel_idx < ss->ch_num) {
+			ch = &ss->ch[ss->channel_idx];
+			scan_ch = ch->hw_value;
+
+			#if defined(CONFIG_RTW_ACS) && defined(CONFIG_RTW_ACS_DBG)
+			if (IS_ACS_ENABLE(padapter) && rtw_is_acs_passiv_scan(padapter))
+				scan_type = SCAN_PASSIVE;
+			else
+			#endif /*CONFIG_RTW_ACS*/
+				scan_type = (ch->flags & RTW_IEEE80211_CHAN_PASSIVE_SCAN) ? SCAN_PASSIVE : SCAN_ACTIVE;
+		}
+	}
+
+	if (scan_ch != 0) {
+		next_state = SCAN_PROCESS;
+
+		#ifdef CONFIG_SCAN_BACKOP
+		if (backop_flags) {
+			if (ss->scan_cnt < ss->scan_cnt_max)
+				ss->scan_cnt++;
+			else {
+				mlmeext_assign_scan_backop_flags(pmlmeext, backop_flags);
+				next_state = SCAN_BACKING_OP;
+			}
+		}
+		#endif
+
+	} else if (rtw_p2p_findphase_ex_is_needed(pwdinfo)) {
+		/* go p2p listen */
+		next_state = SCAN_TO_P2P_LISTEN;
+
+#ifdef CONFIG_ANTENNA_DIVERSITY
+	} else if (rtw_hal_antdiv_before_linked(padapter)) {
+		/* go sw antdiv before link */
+		next_state = SCAN_SW_ANTDIV_BL;
+#endif
+	} else {
+		next_state = SCAN_COMPLETE;
+
+#if defined(DBG_SCAN_SW_ANTDIV_BL)
+		{
+			/* for SCAN_SW_ANTDIV_BL state testing */
+			struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
+			int i;
+			bool is_linked = _FALSE;
+
+			for (i = 0; i < dvobj->iface_nums; i++) {
+				if (rtw_linked_check(dvobj->padapters[i]))
+					is_linked = _TRUE;
+			}
+
+			if (!is_linked) {
+				static bool fake_sw_antdiv_bl_state = 0;
+
+				if (fake_sw_antdiv_bl_state == 0) {
+					next_state = SCAN_SW_ANTDIV_BL;
+					fake_sw_antdiv_bl_state = 1;
+				} else
+					fake_sw_antdiv_bl_state = 0;
+			}
+		}
+#endif /* defined(DBG_SCAN_SW_ANTDIV_BL) */
+	}
+
+#ifdef CONFIG_SCAN_BACKOP
+	if (next_state != SCAN_PROCESS)
+		ss->scan_cnt = 0;
+#endif
+
+
+#ifdef DBG_FIXED_CHAN
+	if (pmlmeext->fixed_chan != 0xff && next_state == SCAN_PROCESS)
+		scan_ch = pmlmeext->fixed_chan;
+#endif
+
+	if (ch)
+		*ch = scan_ch;
+	if (type)
+		*type = scan_type;
+
+	return next_state;
+}
+
+void site_survey(_adapter *padapter, u8 survey_channel, RT_SCAN_TYPE ScanType)
+{
+	struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
+	struct ss_res *ss = &pmlmeext->sitesurvey_res;
+	u8 ssid_scan = 0;
+
+#ifdef CONFIG_P2P
+#ifndef CONFIG_IOCTL_CFG80211
+	struct wifidirect_info *pwdinfo = &(padapter->wdinfo);
+#endif
+#endif
+
+	if (survey_channel != 0) {
+		set_channel_bwmode(padapter, survey_channel, HAL_PRIME_CHNL_OFFSET_DONT_CARE, CHANNEL_WIDTH_20);
+
+#ifdef CONFIG_DFS
+		if (ScanType == SCAN_PASSIVE && ss->dfs_ch_ssid_scan)
+			ssid_scan = 1;
+		else
+#endif
+		if (ScanType == SCAN_ACTIVE) {
+#ifdef CONFIG_P2P
+			#ifdef CONFIG_IOCTL_CFG80211
+			if (rtw_cfg80211_is_p2p_scan(padapter))
+			#else
+			if (rtw_p2p_chk_state(pwdinfo, P2P_STATE_SCAN)
+				|| rtw_p2p_chk_state(pwdinfo, P2P_STATE_FIND_PHASE_SEARCH))
+			#endif
+			{
+				issue_probereq_p2p(padapter, NULL);
+				issue_probereq_p2p(padapter, NULL);
+				issue_probereq_p2p(padapter, NULL);
+			} else
+#endif /* CONFIG_P2P */
+			{
+				if (pmlmeext->sitesurvey_res.scan_mode == SCAN_ACTIVE) {
+					/* IOT issue, When wifi_spec is not set, send one probe req without WPS IE. */
+					if (padapter->registrypriv.wifi_spec)
+						issue_probereq(padapter, NULL, NULL);
+					else
+						issue_probereq_ex(padapter, NULL, NULL, 0, 0, 0, 0);
+					issue_probereq(padapter, NULL, NULL);
+				}
+
+				ssid_scan = 1;
+			}
+		}
+
+		if (ssid_scan) {
+			int i;
+
+			for (i = 0; i < RTW_SSID_SCAN_AMOUNT; i++) {
+				if (pmlmeext->sitesurvey_res.ssid[i].SsidLength) {
+					/* IOT issue, When wifi_spec is not set, send one probe req without WPS IE. */
+					if (padapter->registrypriv.wifi_spec)
+						issue_probereq(padapter, &(pmlmeext->sitesurvey_res.ssid[i]), NULL);
+					else
+						issue_probereq_ex(padapter, &(pmlmeext->sitesurvey_res.ssid[i]), NULL, 0, 0, 0, 0);
+					issue_probereq(padapter, &(pmlmeext->sitesurvey_res.ssid[i]), NULL);
+				}
+			}
+		}
+	} else {
+		/* channel number is 0 or this channel is not valid. */
+		rtw_warn_on(1);
+	}
+
+	return;
+}
+
+void survey_done_set_ch_bw(_adapter *padapter)
+{
+	struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
+	u8 cur_channel = 0;
+	u8 cur_bwmode;
+	u8 cur_ch_offset;
+
+#ifdef CONFIG_MCC_MODE
+	if (!rtw_hal_mcc_change_scan_flag(padapter, &cur_channel, &cur_bwmode, &cur_ch_offset)) {
+		if (0)
+			RTW_INFO(FUNC_ADPT_FMT" back to AP channel - ch:%u, bw:%u, offset:%u\n",
+				FUNC_ADPT_ARG(padapter), cur_channel, cur_bwmode, cur_ch_offset);
+		goto exit;
+	}
+#endif
+
+	if (rtw_mi_get_ch_setting_union(padapter, &cur_channel, &cur_bwmode, &cur_ch_offset) != 0) {
+		if (0)
+			RTW_INFO(FUNC_ADPT_FMT" back to linked/linking union - ch:%u, bw:%u, offset:%u\n",
+				FUNC_ADPT_ARG(padapter), cur_channel, cur_bwmode, cur_ch_offset);
+	} else {
+#ifdef CONFIG_P2P
+		struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
+		_adapter *iface;
+		int i;
+
+		for (i = 0; i < dvobj->iface_nums; i++) {
+			iface = dvobj->padapters[i];
+			if (!iface)
+				continue;
+
+#ifdef CONFIG_IOCTL_CFG80211
+			if (iface->wdinfo.driver_interface == DRIVER_CFG80211 && !adapter_wdev_data(iface)->p2p_enabled)
+				continue;
+#endif
+
+			if (rtw_p2p_chk_state(&iface->wdinfo, P2P_STATE_LISTEN)) {
+				cur_channel = iface->wdinfo.listen_channel;
+				cur_bwmode = CHANNEL_WIDTH_20;
+				cur_ch_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
+				if (0)
+					RTW_INFO(FUNC_ADPT_FMT" back to "ADPT_FMT"'s listen ch - ch:%u, bw:%u, offset:%u\n",
+						FUNC_ADPT_ARG(padapter), ADPT_ARG(iface), cur_channel, cur_bwmode, cur_ch_offset);
+				break;
+			}
+		}
+#endif /* CONFIG_P2P */
+
+		if (cur_channel == 0) {
+			cur_channel = pmlmeext->cur_channel;
+			cur_bwmode = pmlmeext->cur_bwmode;
+			cur_ch_offset = pmlmeext->cur_ch_offset;
+			if (0)
+				RTW_INFO(FUNC_ADPT_FMT" back to ch:%u, bw:%u, offset:%u\n",
+					FUNC_ADPT_ARG(padapter), cur_channel, cur_bwmode, cur_ch_offset);
+		}
+	}
+#ifdef CONFIG_MCC_MODE
+exit:
+#endif
+	set_channel_bwmode(padapter, cur_channel, cur_ch_offset, cur_bwmode);
+}
+
+/**
+ * rtw_ps_annc - check and doing ps announcement for all the adapters
+ * @adapter: the requesting adapter
+ * @ps: power saving or not
+ *
+ * Returns: 0: no ps announcement is doing. 1: ps announcement is doing
+ */
+u8 rtw_ps_annc(_adapter *adapter, bool ps)
+{
+	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
+	_adapter *iface;
+	int i;
+	u8 ps_anc = 0;
+
+	for (i = 0; i < dvobj->iface_nums; i++) {
+		iface = dvobj->padapters[i];
+		if (!iface)
+			continue;
+
+		if (MLME_IS_STA(iface)) {
+			if (is_client_associated_to_ap(iface) == _TRUE) {
+				/* TODO: TDLS peers */
+				#ifdef CONFIG_MCC_MODE
+				/* for two station case */
+				if (MCC_EN(adapter) && rtw_hal_check_mcc_status(adapter, MCC_STATUS_NEED_MCC)) {
+					u8 ch = iface->mlmeextpriv.cur_channel;
+					u8 offset = iface->mlmeextpriv.cur_ch_offset;
+					u8 bw = iface->mlmeextpriv.cur_bwmode;
+
+					set_channel_bwmode(iface, ch, offset, bw);
+				}
+				#endif /* CONFIG_MCC_MODE */
+				issue_nulldata(iface, NULL, ps, 3, 500);
+				ps_anc = 1;
+			}
+		#ifdef CONFIG_RTW_MESH
+		} else if (MLME_IS_MESH(iface)) {
+			if (rtw_mesh_ps_annc(iface, ps))
+				ps_anc = 1;
+		#endif
+		}
+	}
+	return ps_anc;
+}
+
+void rtw_leave_opch(_adapter *adapter)
+{
+	struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter);
+
+#ifdef CONFIG_MCC_MODE
+	if (MCC_EN(adapter) && rtw_hal_check_mcc_status(adapter, MCC_STATUS_DOING_MCC))
+		return;
+#endif
+
+	_enter_critical_mutex(&rfctl->offch_mutex, NULL);
+
+	if (rfctl->offch_state == OFFCHS_NONE) {
+		/* prepare to leave operating channel */
+		rfctl->offch_state = OFFCHS_LEAVING_OP;
+
+		/* clear HW TX queue */
+		rtw_hal_set_hwreg(adapter, HW_VAR_CHECK_TXBUF, 0);
+
+		rtw_hal_macid_sleep_all_used(adapter);
+
+		rtw_ps_annc(adapter, 1);
+
+		rfctl->offch_state = OFFCHS_LEAVE_OP;
+	}
+
+	_exit_critical_mutex(&rfctl->offch_mutex, NULL);
+}
+
+void rtw_back_opch(_adapter *adapter)
+{
+	struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter);
+
+#ifdef CONFIG_MCC_MODE
+	if (MCC_EN(adapter) && rtw_hal_check_mcc_status(adapter, MCC_STATUS_DOING_MCC))
+		return;
+#endif
+
+	_enter_critical_mutex(&rfctl->offch_mutex, NULL);
+
+	if (rfctl->offch_state != OFFCHS_NONE) {
+		rfctl->offch_state = OFFCHS_BACKING_OP;
+		rtw_hal_macid_wakeup_all_used(adapter);
+		rtw_ps_annc(adapter, 0);
+
+		rfctl->offch_state = OFFCHS_NONE;
+		rtw_mi_os_xmit_schedule(adapter);
+	}
+
+	_exit_critical_mutex(&rfctl->offch_mutex, NULL);
+}
+
+void sitesurvey_set_igi(_adapter *adapter)
+{
+	struct mlme_ext_priv *mlmeext = &adapter->mlmeextpriv;
+	struct ss_res *ss = &mlmeext->sitesurvey_res;
+	u8 igi;
+#ifdef CONFIG_P2P
+	struct wifidirect_info *pwdinfo = &adapter->wdinfo;
+#endif
+
+	switch (mlmeext_scan_state(mlmeext)) {
+	case SCAN_ENTER:
+		#ifdef CONFIG_P2P
+		#ifdef CONFIG_IOCTL_CFG80211
+		if (pwdinfo->driver_interface == DRIVER_CFG80211 && rtw_cfg80211_is_p2p_scan(adapter))
+			igi = 0x30;
+		else
+		#endif /* CONFIG_IOCTL_CFG80211 */
+		if (!rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE))
+			igi = 0x28;
+		else
+		#endif /* CONFIG_P2P */
+
+		if (ss->igi)
+			igi = ss->igi;
+		else
+		#if defined(CONFIG_RTW_ACS) && defined(CONFIG_RTW_ACS_DBG)
+		if (IS_ACS_ENABLE(adapter) && rtw_is_acs_igi_valid(adapter))
+			igi = rtw_acs_get_adv_igi(adapter);
+		else
+		#endif /*CONFIG_RTW_ACS*/
+			igi = 0x1e;
+
+		/* record IGI status */
+		ss->igi_scan = igi;
+		rtw_hal_get_odm_var(adapter, HAL_ODM_INITIAL_GAIN, &ss->igi_before_scan, NULL);
+
+		/* disable DIG and set IGI for scan */
+		rtw_hal_set_odm_var(adapter, HAL_ODM_INITIAL_GAIN, &igi, _FALSE);
+		break;
+	case SCAN_COMPLETE:
+	case SCAN_TO_P2P_LISTEN:
+		/* enable DIG and restore IGI */
+		igi = 0xff;
+		rtw_hal_set_odm_var(adapter, HAL_ODM_INITIAL_GAIN, &igi, _FALSE);
+		break;
+#ifdef CONFIG_SCAN_BACKOP
+	case SCAN_BACKING_OP:
+		/* write IGI for op channel when DIG is not enabled */
+		odm_write_dig(adapter_to_phydm(adapter), ss->igi_before_scan);
+		break;
+	case SCAN_LEAVE_OP:
+		/* write IGI for scan when DIG is not enabled */
+		odm_write_dig(adapter_to_phydm(adapter), ss->igi_scan);
+		break;
+#endif /* CONFIG_SCAN_BACKOP */
+	default:
+		rtw_warn_on(1);
+		break;
+	}
+}
+void sitesurvey_set_msr(_adapter *adapter, bool enter)
+{
+	u8 network_type;
+	struct mlme_ext_priv *pmlmeext = &adapter->mlmeextpriv;
+	struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
+
+	if (enter) {
+#ifdef CONFIG_MI_WITH_MBSSID_CAM
+		rtw_hal_get_hwreg(adapter, HW_VAR_MEDIA_STATUS, (u8 *)(&pmlmeinfo->hw_media_state));
+#endif
+		/* set MSR to no link state */
+		network_type = _HW_STATE_NOLINK_;
+	} else {
+#ifdef CONFIG_MI_WITH_MBSSID_CAM
+		network_type = pmlmeinfo->hw_media_state;
+#else
+		network_type = pmlmeinfo->state & 0x3;
+#endif
+	}
+	Set_MSR(adapter, network_type);
+}
+
+void sitesurvey_set_offch_state(_adapter *adapter, u8 scan_state)
+{
+	struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter);
+
+	_enter_critical_mutex(&rfctl->offch_mutex, NULL);
+
+	switch (scan_state) {
+	case SCAN_DISABLE:
+	case SCAN_BACK_OP:
+		rfctl->offch_state = OFFCHS_NONE;
+		break;
+	case SCAN_START:
+	case SCAN_LEAVING_OP:
+		rfctl->offch_state = OFFCHS_LEAVING_OP;
+		break;
+	case SCAN_ENTER:
+	case SCAN_LEAVE_OP:
+		rfctl->offch_state = OFFCHS_LEAVE_OP;
+		break;
+	case SCAN_COMPLETE:
+	case SCAN_BACKING_OP:
+		rfctl->offch_state = OFFCHS_BACKING_OP;
+		break;
+	default:
+		break;
+	}
+
+	_exit_critical_mutex(&rfctl->offch_mutex, NULL);
+}
+
+u8 sitesurvey_cmd_hdl(_adapter *padapter, u8 *pbuf)
+{
+	struct sitesurvey_parm	*pparm = (struct sitesurvey_parm *)pbuf;
+#ifdef DBG_CHECK_FW_PS_STATE
+	struct dvobj_priv *dvobj = padapter->dvobj;
+	struct debug_priv *pdbgpriv = &dvobj->drv_dbg;
+#endif
+	struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
+	struct ss_res *ss = &pmlmeext->sitesurvey_res;
+#ifdef CONFIG_RTW_CFGVENDOR_RANDOM_MAC_OUI
+		struct rtw_wdev_priv *pwdev_priv = adapter_wdev_data(padapter);
+#endif
+	u8 val8;
+
+#ifdef CONFIG_P2P
+	struct wifidirect_info *pwdinfo = &padapter->wdinfo;
+#endif
+
+#ifdef DBG_CHECK_FW_PS_STATE
+	if (rtw_fw_ps_state(padapter) == _FAIL) {
+		RTW_INFO("scan without leave 32k\n");
+		pdbgpriv->dbg_scan_pwr_state_cnt++;
+	}
+#endif /* DBG_CHECK_FW_PS_STATE */
+
+	/* increase channel idx */
+	if (mlmeext_chk_scan_state(pmlmeext, SCAN_PROCESS))
+		ss->channel_idx++;
+
+	/* update scan state to next state (assigned by previous cmd hdl) */
+	if (mlmeext_scan_state(pmlmeext) != mlmeext_scan_next_state(pmlmeext))
+		mlmeext_set_scan_state(pmlmeext, mlmeext_scan_next_state(pmlmeext));
+
+operation_by_state:
+	switch (mlmeext_scan_state(pmlmeext)) {
+
+	case SCAN_DISABLE:
+		/*
+		* SW parameter initialization
+		*/
+
+		sitesurvey_res_reset(padapter, pparm);
+		mlmeext_set_scan_state(pmlmeext, SCAN_START);
+		goto operation_by_state;
+
+	case SCAN_START:
+#ifdef CONFIG_RTW_CFGVENDOR_RANDOM_MAC_OUI
+		if ((pwdev_priv->pno_mac_addr[0] != 0xFF)
+			    && (check_fwstate(&padapter->mlmepriv, WIFI_STATION_STATE) == _TRUE)
+	    	    && (check_fwstate(&padapter->mlmepriv, _FW_LINKED) == _FALSE)) {
+			u16 seq_num;
+
+			rtw_hal_pno_random_gen_mac_addr(padapter);
+			rtw_hal_set_hw_mac_addr(padapter, pwdev_priv->pno_mac_addr);
+			get_random_bytes(&seq_num, 2);
+			pwdev_priv->pno_scan_seq_num = seq_num & 0xFFF;
+			RTW_INFO("%s pno_scan_seq_num %d\n", __func__,
+				 pwdev_priv->pno_scan_seq_num);
+		}
+#endif
+
+		/*
+		* prepare to leave operating channel
+		*/
+
+#ifdef CONFIG_MCC_MODE
+		rtw_hal_set_mcc_setting_scan_start(padapter);
+#endif /* CONFIG_MCC_MODE */
+
+		/* apply rx ampdu setting */
+		if (ss->rx_ampdu_accept != RX_AMPDU_ACCEPT_INVALID
+			|| ss->rx_ampdu_size != RX_AMPDU_SIZE_INVALID)
+			rtw_rx_ampdu_apply(padapter);
+
+		/* clear HW TX queue before scan */
+		rtw_hal_set_hwreg(padapter, HW_VAR_CHECK_TXBUF, 0);
+
+		rtw_hal_macid_sleep_all_used(padapter);
+
+		/* power save state announcement */
+		if (rtw_ps_annc(padapter, 1)) {
+			mlmeext_set_scan_state(pmlmeext, SCAN_PS_ANNC_WAIT);
+			mlmeext_set_scan_next_state(pmlmeext, SCAN_ENTER);
+			set_survey_timer(pmlmeext, 50); /* delay 50ms to protect nulldata(1) */
+		} else {
+			mlmeext_set_scan_state(pmlmeext, SCAN_ENTER);
+			goto operation_by_state;
+		}
+
+		break;
+
+	case SCAN_ENTER:
+		/*
+		* HW register and DM setting for enter scan
+		*/
+
+		rtw_phydm_ability_backup(padapter);
+
+		sitesurvey_set_igi(padapter);
+
+		/* config dynamic functions for off channel */
+		rtw_phydm_func_for_offchannel(padapter);
+		/* set MSR to no link state */
+		sitesurvey_set_msr(padapter, _TRUE);
+
+		val8 = 1; /* under site survey */
+		rtw_hal_set_hwreg(padapter, HW_VAR_MLME_SITESURVEY, (u8 *)(&val8));
+
+		mlmeext_set_scan_state(pmlmeext, SCAN_PROCESS);
+		goto operation_by_state;
+
+	case SCAN_PROCESS: {
+		u8 scan_ch;
+		RT_SCAN_TYPE scan_type;
+		u8 next_state;
+		u32 scan_ms;
+
+#ifdef CONFIG_RTW_ACS
+		if (IS_ACS_ENABLE(padapter))
+			rtw_acs_get_rst(padapter);
+#endif
+
+		next_state = sitesurvey_pick_ch_behavior(padapter, &scan_ch, &scan_type);
+
+		if (next_state != SCAN_PROCESS) {
+			mlmeext_set_scan_state(pmlmeext, next_state);
+			goto operation_by_state;
+		}
+
+		/* still SCAN_PROCESS state */
+		#ifdef DBG_SITESURVEY
+			#ifdef CONFIG_P2P
+			RTW_INFO(FUNC_ADPT_FMT" %s ch:%u (cnt:%u,idx:%d) at %dms, %c%c%c%c\n"
+				, FUNC_ADPT_ARG(padapter)
+				, mlmeext_scan_state_str(pmlmeext)
+				, scan_ch
+				, pwdinfo->find_phase_state_exchange_cnt, ss->channel_idx
+				, rtw_get_passing_time_ms(padapter->mlmepriv.scan_start_time)
+				, scan_type ? 'A' : 'P', ss->scan_mode ? 'A' : 'P'
+				, ss->ssid[0].SsidLength ? 'S' : ' '
+				, ss->dfs_ch_ssid_scan ? 'D' : ' '
+			);
+			#else
+			RTW_INFO(FUNC_ADPT_FMT" %s ch:%u (idx:%d) at %dms, %c%c%c%c\n"
+				, FUNC_ADPT_ARG(padapter)
+				, mlmeext_scan_state_str(pmlmeext)
+				, scan_ch
+				, ss->channel_idx
+				, rtw_get_passing_time_ms(padapter->mlmepriv.scan_start_time)
+				, scan_type ? 'A' : 'P', ss->scan_mode ? 'A' : 'P'
+				, ss->ssid[0].SsidLength ? 'S' : ' '
+				, ss->dfs_ch_ssid_scan ? 'D' : ' '
+			);
+			#endif /* CONFIG_P2P */
+		#endif /*DBG_SITESURVEY*/
+#ifdef DBG_FIXED_CHAN
+		if (pmlmeext->fixed_chan != 0xff)
+			RTW_INFO(FUNC_ADPT_FMT" fixed_chan:%u\n", pmlmeext->fixed_chan);
+#endif
+
+		site_survey(padapter, scan_ch, scan_type);
+
+#if defined(CONFIG_ATMEL_RC_PATCH)
+		if (check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE)
+			scan_ms = 20;
+		else
+			scan_ms = 40;
+#else
+		#if defined(CONFIG_RTW_ACS) && defined(CONFIG_RTW_ACS_DBG)
+		if (IS_ACS_ENABLE(padapter) && rtw_is_acs_st_valid(padapter))
+			scan_ms = rtw_acs_get_adv_st(padapter);
+		else
+		#endif /*CONFIG_RTW_ACS*/
+			scan_ms = ss->scan_ch_ms;
+#endif
+
+#if defined(CONFIG_ANTENNA_DIVERSITY) || defined(DBG_SCAN_SW_ANTDIV_BL)
+		if (ss->is_sw_antdiv_bl_scan)
+			scan_ms = scan_ms / 2;
+#endif
+
+#ifdef CONFIG_RTW_ACS
+		if (IS_ACS_ENABLE(padapter)) {
+			if (pparm->token)
+				rtw_acs_trigger(padapter, scan_ms, scan_ch, NHM_PID_IEEE_11K_HIGH);
+			else
+				rtw_acs_trigger(padapter, scan_ms, scan_ch, NHM_PID_ACS);
+		}
+#endif
+
+#ifdef CONFIG_BACKGROUND_NOISE_MONITOR
+		if (IS_NM_ENABLE(padapter))
+			rtw_noise_measure(padapter, scan_ch, _FALSE, 0, scan_ms / 2);
+#endif
+		set_survey_timer(pmlmeext, scan_ms);
+		break;
+	}
+
+#ifdef CONFIG_SCAN_BACKOP
+	case SCAN_BACKING_OP: {
+		u8 back_ch, back_bw, back_ch_offset;
+		u8 need_ch_setting_union = _TRUE;
+
+#ifdef CONFIG_MCC_MODE
+		need_ch_setting_union = rtw_hal_mcc_change_scan_flag(padapter,
+				&back_ch, &back_bw, &back_ch_offset);
+#endif /* CONFIG_MCC_MODE */
+
+		if (need_ch_setting_union) {
+			if (rtw_mi_get_ch_setting_union(padapter, &back_ch, &back_bw, &back_ch_offset) == 0)
+				rtw_warn_on(1);
+		}
+
+		#ifdef DBG_SITESURVEY
+			RTW_INFO(FUNC_ADPT_FMT" %s ch:%u, bw:%u, offset:%u at %dms\n"
+				 , FUNC_ADPT_ARG(padapter)
+				 , mlmeext_scan_state_str(pmlmeext)
+				 , back_ch, back_bw, back_ch_offset
+				, rtw_get_passing_time_ms(padapter->mlmepriv.scan_start_time)
+				);
+		#endif /*DBG_SITESURVEY*/
+		set_channel_bwmode(padapter, back_ch, back_ch_offset, back_bw);
+
+		sitesurvey_set_msr(padapter, _FALSE);
+
+		val8 = 0; /* survey done */
+		rtw_hal_set_hwreg(padapter, HW_VAR_MLME_SITESURVEY, (u8 *)(&val8));
+
+		if (mlmeext_chk_scan_backop_flags(pmlmeext, SS_BACKOP_PS_ANNC)) {
+			sitesurvey_set_igi(padapter);
+			rtw_hal_macid_wakeup_all_used(padapter);
+			rtw_ps_annc(padapter, 0);
+		}
+
+		mlmeext_set_scan_state(pmlmeext, SCAN_BACK_OP);
+		ss->backop_time = rtw_get_current_time();
+
+		if (mlmeext_chk_scan_backop_flags(pmlmeext, SS_BACKOP_TX_RESUME))
+			rtw_mi_os_xmit_schedule(padapter);
+
+
+		goto operation_by_state;
+	}
+
+	case SCAN_BACK_OP:
+		if (rtw_get_passing_time_ms(ss->backop_time) >= ss->backop_ms
+		    || pmlmeext->scan_abort
+		   ) {
+			mlmeext_set_scan_state(pmlmeext, SCAN_LEAVING_OP);
+			goto operation_by_state;
+		}
+		set_survey_timer(pmlmeext, 50);
+		break;
+
+	case SCAN_LEAVING_OP:
+		/*
+		 * prepare to leave operating channel
+		 */
+
+		/* clear HW TX queue before scan */
+		rtw_hal_set_hwreg(padapter, HW_VAR_CHECK_TXBUF, 0);
+
+		rtw_hal_macid_sleep_all_used(padapter);
+		if (mlmeext_chk_scan_backop_flags(pmlmeext, SS_BACKOP_PS_ANNC)
+			&& rtw_ps_annc(padapter, 1)
+		) {
+			mlmeext_set_scan_state(pmlmeext, SCAN_PS_ANNC_WAIT);
+			mlmeext_set_scan_next_state(pmlmeext, SCAN_LEAVE_OP);
+			set_survey_timer(pmlmeext, 50); /* delay 50ms to protect nulldata(1) */
+		} else {
+			mlmeext_set_scan_state(pmlmeext, SCAN_LEAVE_OP);
+			goto operation_by_state;
+		}
+
+		break;
+
+	case SCAN_LEAVE_OP:
+		/*
+		* HW register and DM setting for enter scan
+		*/
+
+		if (mlmeext_chk_scan_backop_flags(pmlmeext, SS_BACKOP_PS_ANNC))
+			sitesurvey_set_igi(padapter);
+
+		sitesurvey_set_msr(padapter, _TRUE);
+
+		val8 = 1; /* under site survey */
+		rtw_hal_set_hwreg(padapter, HW_VAR_MLME_SITESURVEY, (u8 *)(&val8));
+
+		mlmeext_set_scan_state(pmlmeext, SCAN_PROCESS);
+		goto operation_by_state;
+
+#endif /* CONFIG_SCAN_BACKOP */
+
+#if defined(CONFIG_ANTENNA_DIVERSITY) || defined(DBG_SCAN_SW_ANTDIV_BL)
+	case SCAN_SW_ANTDIV_BL:
+		/*
+		* 20100721
+		* For SW antenna diversity before link, it needs to switch to another antenna and scan again.
+		* It compares the scan result and select better one to do connection.
+		*/
+		ss->bss_cnt = 0;
+		ss->channel_idx = 0;
+		ss->is_sw_antdiv_bl_scan = 1;
+
+		mlmeext_set_scan_next_state(pmlmeext, SCAN_PROCESS);
+		set_survey_timer(pmlmeext, ss->scan_ch_ms);
+		break;
+#endif
+
+#ifdef CONFIG_P2P
+	case SCAN_TO_P2P_LISTEN:
+		/*
+		* Set the P2P State to the listen state of find phase
+		* and set the current channel to the listen channel
+		*/
+		set_channel_bwmode(padapter, pwdinfo->listen_channel, HAL_PRIME_CHNL_OFFSET_DONT_CARE, CHANNEL_WIDTH_20);
+		rtw_p2p_set_state(pwdinfo, P2P_STATE_FIND_PHASE_LISTEN);
+
+		/* turn on phy-dynamic functions */
+		rtw_phydm_ability_restore(padapter);
+
+		sitesurvey_set_igi(padapter);
+
+		mlmeext_set_scan_state(pmlmeext, SCAN_P2P_LISTEN);
+		_set_timer(&pwdinfo->find_phase_timer, (u32)((u32)pwdinfo->listen_dwell * 100));
+		break;
+
+	case SCAN_P2P_LISTEN:
+		mlmeext_set_scan_state(pmlmeext, SCAN_PROCESS);
+		ss->channel_idx = 0;
+		goto operation_by_state;
+#endif /* CONFIG_P2P */
+
+	case SCAN_COMPLETE:
+#ifdef CONFIG_RTW_CFGVENDOR_RANDOM_MAC_OUI
+		rtw_hal_set_hw_mac_addr(padapter, adapter_mac_addr(padapter));
+#endif
+#ifdef CONFIG_P2P
+		if (rtw_p2p_chk_state(pwdinfo, P2P_STATE_SCAN)
+		    || rtw_p2p_chk_state(pwdinfo, P2P_STATE_FIND_PHASE_SEARCH)
+		   ) {
+#ifdef CONFIG_CONCURRENT_MODE
+			if (pwdinfo->driver_interface == DRIVER_WEXT) {
+				if (rtw_mi_check_status(padapter, MI_LINKED))
+					_set_timer(&pwdinfo->ap_p2p_switch_timer, 500);
+			}
+#endif
+
+			rtw_p2p_set_state(pwdinfo, rtw_p2p_pre_state(pwdinfo));
+		}
+		rtw_p2p_findphase_ex_set(pwdinfo, P2P_FINDPHASE_EX_NONE);
+#endif /* CONFIG_P2P */
+
+		/* switch channel */
+		survey_done_set_ch_bw(padapter);
+
+		sitesurvey_set_msr(padapter, _FALSE);
+
+		val8 = 0; /* survey done */
+		rtw_hal_set_hwreg(padapter, HW_VAR_MLME_SITESURVEY, (u8 *)(&val8));
+
+		/* turn on phy-dynamic functions */
+		rtw_phydm_ability_restore(padapter);
+
+		sitesurvey_set_igi(padapter);
+
+#ifdef CONFIG_MCC_MODE
+		/* start MCC fail, then tx null data */
+		if (!rtw_hal_set_mcc_setting_scan_complete(padapter))
+#endif
+		{
+			rtw_hal_macid_wakeup_all_used(padapter);
+			rtw_ps_annc(padapter, 0);
+		}
+
+		/* apply rx ampdu setting */
+		rtw_rx_ampdu_apply(padapter);
+
+		mlmeext_set_scan_state(pmlmeext, SCAN_DISABLE);
+
+		report_surveydone_event(padapter);
+#ifdef CONFIG_RTW_ACS
+		if (IS_ACS_ENABLE(padapter))
+			rtw_acs_select_best_chan(padapter);
+#endif
+
+#if defined(CONFIG_BACKGROUND_NOISE_MONITOR) && defined(DBG_NOISE_MONITOR)
+		if (IS_NM_ENABLE(padapter))
+			rtw_noise_info_dump(RTW_DBGDUMP, padapter);
+#endif
+		issue_action_BSSCoexistPacket(padapter);
+		issue_action_BSSCoexistPacket(padapter);
+		issue_action_BSSCoexistPacket(padapter);
+
+#ifdef CONFIG_RTW_80211K
+		if (ss->token)
+			rm_post_event(padapter, ss->token, RM_EV_survey_done);
+#endif /* CONFIG_RTW_80211K */
+
+		break;
+	}
+
+	return H2C_SUCCESS;
+}
+
+u8 setauth_hdl(_adapter *padapter, unsigned char *pbuf)
+{
+	struct setauth_parm		*pparm = (struct setauth_parm *)pbuf;
+	struct mlme_ext_priv	*pmlmeext = &padapter->mlmeextpriv;
+	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
+
+	if (pparm->mode < 4)
+		pmlmeinfo->auth_algo = pparm->mode;
+
+	return	H2C_SUCCESS;
+}
+
+/*
+SEC CAM Entry format (32 bytes)
+DW0 - MAC_ADDR[15:0] | Valid[15] | MFB[14:8] | RSVD[7]  | GK[6] | MIC_KEY[5] | SEC_TYPE[4:2] | KID[1:0]
+DW0 - MAC_ADDR[15:0] | Valid[15] |RSVD[14:9] | RPT_MODE[8] | SPP_MODE[7]  | GK[6] | MIC_KEY[5] | SEC_TYPE[4:2] | KID[1:0] (92E/8812A/8814A)
+DW1 - MAC_ADDR[47:16]
+DW2 - KEY[31:0]
+DW3 - KEY[63:32]
+DW4 - KEY[95:64]
+DW5 - KEY[127:96]
+DW6 - RSVD
+DW7 - RSVD
+*/
+
+/*Set WEP key or Group Key*/
+u8 setkey_hdl(_adapter *padapter, u8 *pbuf)
+{
+	u16	ctrl = 0;
+	s16 cam_id = 0;
+	struct setkey_parm		*pparm = (struct setkey_parm *)pbuf;
+	struct mlme_ext_priv	*pmlmeext = &padapter->mlmeextpriv;
+	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
+	unsigned char null_addr[] = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00};
+	u8 *addr;
+	bool used = _FALSE;
+
+	/* main tx key for wep. */
+	if (pparm->set_tx)
+		pmlmeinfo->key_index = pparm->keyid;
+
+#ifdef CONFIG_CONCURRENT_MODE
+	if (((pmlmeinfo->state & 0x03) == WIFI_FW_AP_STATE) || ((pmlmeinfo->state & 0x03) == WIFI_FW_ADHOC_STATE))
+		cam_id = rtw_iface_bcmc_id_get(padapter);
+	else
+#endif
+		cam_id = rtw_camid_alloc(padapter, NULL, pparm->keyid, 1, &used);
+
+	if (cam_id < 0)
+		goto enable_mc;
+
+#ifndef CONFIG_CONCURRENT_MODE
+	if (cam_id >= 0 && cam_id <= 3) {
+		/* default key camid */
+		addr = null_addr;
+	} else
+#endif
+	{
+		/* not default key camid */
+		if (((pmlmeinfo->state & 0x03) == WIFI_FW_AP_STATE) || ((pmlmeinfo->state & 0x03) == WIFI_FW_ADHOC_STATE)) {
+			/* group TX, force sec cam entry_id */
+			addr = adapter_mac_addr(padapter);
+		} else {
+			/* group RX, searched by A2 (TA) */
+			addr = get_bssid(&padapter->mlmepriv);
+		}
+	}
+
+	/* cam entry searched is pairwise key */
+	if (used == _TRUE && rtw_camid_is_gk(padapter, cam_id) == _FALSE) {
+		s16 camid_clr;
+
+		RTW_PRINT(FUNC_ADPT_FMT" group key with "MAC_FMT" id:%u the same key id as pairwise key\n"
+			, FUNC_ADPT_ARG(padapter), MAC_ARG(addr), pparm->keyid);
+
+		/* HW has problem to distinguish this group key with existing pairwise key, stop HW enc and dec for BMC */
+		rtw_camctl_set_flags(padapter, SEC_STATUS_STA_PK_GK_CONFLICT_DIS_BMC_SEARCH);
+		rtw_hal_set_hwreg(padapter, HW_VAR_SEC_CFG, NULL);
+
+		/* clear group key */
+		while ((camid_clr = rtw_camid_search(padapter, addr, -1, 1)) >= 0) {
+			RTW_PRINT("clear group key for addr:"MAC_FMT", camid:%d\n", MAC_ARG(addr), camid_clr);
+			clear_cam_entry(padapter, camid_clr);
+			rtw_camid_free(padapter, camid_clr);
+		}
+
+		goto enable_mc;
+	}
+
+	ctrl = BIT(15) | BIT(6) | ((pparm->algorithm) << 2) | pparm->keyid;
+
+	RTW_PRINT("set group key camid:%d, addr:"MAC_FMT", kid:%d, type:%s\n"
+		, cam_id, MAC_ARG(addr), pparm->keyid, security_type_str(pparm->algorithm));
+
+	write_cam(padapter, cam_id, ctrl, addr, pparm->key);
+
+	/* if ((cam_id > 3) && (((pmlmeinfo->state&0x03) == WIFI_FW_AP_STATE) || ((pmlmeinfo->state&0x03) == WIFI_FW_ADHOC_STATE)))*/
+#ifdef CONFIG_CONCURRENT_MODE
+	if (((pmlmeinfo->state & 0x03) == WIFI_FW_AP_STATE) || ((pmlmeinfo->state & 0x03) == WIFI_FW_ADHOC_STATE)) {
+		if (is_wep_enc(pparm->algorithm)) {
+			padapter->securitypriv.dot11Def_camid[pparm->keyid] = cam_id;
+			padapter->securitypriv.dot118021x_bmc_cam_id =
+				padapter->securitypriv.dot11Def_camid[padapter->securitypriv.dot11PrivacyKeyIndex];
+			RTW_PRINT("wep group key - force camid:%d\n", padapter->securitypriv.dot118021x_bmc_cam_id);
+		} else {
+			/*u8 org_cam_id = padapter->securitypriv.dot118021x_bmc_cam_id;*/
+
+			/*force GK's cam id*/
+			padapter->securitypriv.dot118021x_bmc_cam_id = cam_id;
+
+			/* for GTK rekey
+			if ((org_cam_id != INVALID_SEC_MAC_CAM_ID) &&
+				(org_cam_id != cam_id)) {
+				RTW_PRINT("clear group key for addr:"MAC_FMT", org_camid:%d new_camid:%d\n", MAC_ARG(addr), org_cam_id, cam_id);
+				clear_cam_entry(padapter, org_cam_id);
+				rtw_camid_free(padapter, org_cam_id);
+			}*/
+		}
+	}
+#endif
+
+
+#ifndef CONFIG_CONCURRENT_MODE
+	if (cam_id >= 0 && cam_id <= 3)
+		rtw_hal_set_hwreg(padapter, HW_VAR_SEC_DK_CFG, (u8 *)_TRUE);
+#endif
+
+	/* 8814au should set both broadcast and unicast CAM entry for WEP key in STA mode */
+	if (is_wep_enc(pparm->algorithm) && check_mlmeinfo_state(pmlmeext, WIFI_FW_STATION_STATE) &&
+	    _rtw_camctl_chk_cap(padapter, SEC_CAP_CHK_BMC)) {
+		struct set_stakey_parm	sta_pparm;
+
+		_rtw_memset(&sta_pparm, 0, sizeof(struct set_stakey_parm));
+		sta_pparm.algorithm = pparm->algorithm;
+		sta_pparm.keyid = pparm->keyid;
+		_rtw_memcpy(sta_pparm.key, pparm->key, 16);
+		_rtw_memcpy(sta_pparm.addr, get_bssid(&padapter->mlmepriv), ETH_ALEN);
+		set_stakey_hdl(padapter, (u8 *)&sta_pparm);
+	}
+
+enable_mc:
+	/* allow multicast packets to driver */
+	rtw_hal_set_hwreg(padapter, HW_VAR_ON_RCR_AM, null_addr);
+
+	return H2C_SUCCESS;
+}
+
+void rtw_ap_wep_pk_setting(_adapter *adapter, struct sta_info *psta)
+{
+	struct security_priv *psecuritypriv = &(adapter->securitypriv);
+	struct set_stakey_parm	sta_pparm;
+	sint keyid;
+
+	if (!is_wep_enc(psecuritypriv->dot11PrivacyAlgrthm))
+		return;
+
+	for (keyid = 0; keyid < 4; keyid++) {
+		if ((psecuritypriv->key_mask & BIT(keyid)) && (keyid == psecuritypriv->dot11PrivacyKeyIndex)) {
+			sta_pparm.algorithm = psecuritypriv->dot11PrivacyAlgrthm;
+			sta_pparm.keyid = keyid;
+			sta_pparm.gk = 0;
+			_rtw_memcpy(sta_pparm.key, &(psecuritypriv->dot11DefKey[keyid].skey[0]), 16);
+			_rtw_memcpy(sta_pparm.addr, psta->cmn.mac_addr, ETH_ALEN);
+
+			RTW_PRINT(FUNC_ADPT_FMT"set WEP - PK with "MAC_FMT" keyid:%u\n"
+				, FUNC_ADPT_ARG(adapter), MAC_ARG(psta->cmn.mac_addr), keyid);
+
+			set_stakey_hdl(adapter, (u8 *)&sta_pparm);
+		}
+	}
+}
+
+u8 set_stakey_hdl(_adapter *padapter, u8 *pbuf)
+{
+	u16 ctrl = 0;
+	s16 cam_id = 0;
+	bool used;
+	u8 ret = H2C_SUCCESS;
+	struct mlme_ext_priv	*pmlmeext = &padapter->mlmeextpriv;
+	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
+	struct set_stakey_parm	*pparm = (struct set_stakey_parm *)pbuf;
+	struct sta_priv *pstapriv = &padapter->stapriv;
+	struct sta_info *psta;
+
+	if (pparm->algorithm == _NO_PRIVACY_)
+		goto write_to_cam;
+
+	psta = rtw_get_stainfo(pstapriv, pparm->addr);
+	if (!psta) {
+		RTW_PRINT("%s sta:"MAC_FMT" not found\n", __func__, MAC_ARG(pparm->addr));
+		ret = H2C_REJECTED;
+		goto exit;
+	}
+
+	pmlmeinfo->enc_algo = pparm->algorithm;
+
+	cam_id = rtw_camid_alloc(padapter, psta, pparm->keyid, pparm->gk, &used);
+	if (cam_id < 0)
+		goto exit;
+
+	/* cam entry searched is group key when setting pariwise key */
+	if (!pparm->gk && used == _TRUE && rtw_camid_is_gk(padapter, cam_id) == _TRUE) {
+		s16 camid_clr;
+
+		RTW_PRINT(FUNC_ADPT_FMT" pairwise key with "MAC_FMT" id:%u the same key id as group key\n"
+			, FUNC_ADPT_ARG(padapter), MAC_ARG(pparm->addr), pparm->keyid);
+
+		/* HW has problem to distinguish this pairwise key with existing group key, stop HW enc and dec for BMC */
+		rtw_camctl_set_flags(padapter, SEC_STATUS_STA_PK_GK_CONFLICT_DIS_BMC_SEARCH);
+		rtw_hal_set_hwreg(padapter, HW_VAR_SEC_CFG, NULL);
+
+		/* clear group key */
+		while ((camid_clr = rtw_camid_search(padapter, pparm->addr, -1, 1)) >= 0) {
+			RTW_PRINT("clear group key for addr:"MAC_FMT", camid:%d\n", MAC_ARG(pparm->addr), camid_clr);
+			clear_cam_entry(padapter, camid_clr);
+			rtw_camid_free(padapter, camid_clr);
+		}
+	}
+
+write_to_cam:
+	if (pparm->algorithm == _NO_PRIVACY_) {
+		while ((cam_id = rtw_camid_search(padapter, pparm->addr, -1, -1)) >= 0) {
+			RTW_PRINT("clear key for addr:"MAC_FMT", camid:%d\n", MAC_ARG(pparm->addr), cam_id);
+			clear_cam_entry(padapter, cam_id);
+			rtw_camid_free(padapter, cam_id);
+		}
+	} else {
+		RTW_PRINT("set %s key camid:%d, addr:"MAC_FMT", kid:%d, type:%s\n"
+			, pparm->gk ? "group" : "pairwise"
+			, cam_id, MAC_ARG(pparm->addr), pparm->keyid, security_type_str(pparm->algorithm));
+		ctrl = BIT(15) | ((pparm->algorithm) << 2) | pparm->keyid;
+		if (pparm->gk)
+			ctrl |= BIT(6);
+		write_cam(padapter, cam_id, ctrl, pparm->addr, pparm->key);
+	}
+	ret = H2C_SUCCESS_RSP;
+
+exit:
+	return ret;
+}
+
+u8 add_ba_hdl(_adapter *padapter, unsigned char *pbuf)
+{
+	struct addBaReq_parm	*pparm = (struct addBaReq_parm *)pbuf;
+	struct mlme_ext_priv	*pmlmeext = &padapter->mlmeextpriv;
+	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
+
+	struct sta_info *psta = rtw_get_stainfo(&padapter->stapriv, pparm->addr);
+
+	if (!psta)
+		return	H2C_SUCCESS;
+
+#ifdef CONFIG_80211N_HT
+	if (((pmlmeinfo->state & WIFI_FW_ASSOC_SUCCESS) && (pmlmeinfo->HT_enable)) ||
+	    ((pmlmeinfo->state & 0x03) == WIFI_FW_AP_STATE)) {
+		/* pmlmeinfo->ADDBA_retry_count = 0; */
+		/* pmlmeinfo->candidate_tid_bitmap |= (0x1 << pparm->tid);		 */
+		/* psta->htpriv.candidate_tid_bitmap |= BIT(pparm->tid); */
+		issue_addba_req(padapter, pparm->addr, (u8)pparm->tid);
+		_set_timer(&psta->addba_retry_timer, ADDBA_TO);
+	}
+#ifdef CONFIG_TDLS
+	else if ((psta->tdls_sta_state & TDLS_LINKED_STATE) &&
+		 (psta->htpriv.ht_option == _TRUE) &&
+		 (psta->htpriv.ampdu_enable == _TRUE)) {
+		issue_addba_req(padapter, pparm->addr, (u8)pparm->tid);
+		_set_timer(&psta->addba_retry_timer, ADDBA_TO);
+	}
+#endif /* CONFIG */
+	else
+		psta->htpriv.candidate_tid_bitmap &= ~BIT(pparm->tid);
+#endif /* CONFIG_80211N_HT */
+	return	H2C_SUCCESS;
+}
+
+
+u8 add_ba_rsp_hdl(_adapter *padapter, unsigned char *pbuf)
+{
+	struct addBaRsp_parm *pparm = (struct addBaRsp_parm *)pbuf;
+	struct recv_reorder_ctrl *preorder_ctrl;
+	struct sta_priv *pstapriv = &padapter->stapriv;
+	struct sta_info *psta;
+	u8 ret = _TRUE;
+
+	psta = rtw_get_stainfo(pstapriv, pparm->addr);
+	if (!psta)
+		goto exit;
+
+	preorder_ctrl = &psta->recvreorder_ctrl[pparm->tid];
+	ret = issue_addba_rsp_wait_ack(padapter, pparm->addr, pparm->tid, pparm->status, pparm->size, 3, 50);
+
+#ifdef CONFIG_UPDATE_INDICATE_SEQ_WHILE_PROCESS_ADDBA_REQ
+	/* status = 0 means accept this addba req, so update indicate seq = start_seq under this compile flag */
+	if (pparm->status == 0) {
+		preorder_ctrl->indicate_seq = pparm->start_seq;
+		#ifdef DBG_RX_SEQ
+		RTW_INFO("DBG_RX_SEQ "FUNC_ADPT_FMT" tid:%u SN_UPDATE indicate_seq:%d, start_seq:%d\n"
+			, FUNC_ADPT_ARG(padapter), preorder_ctrl->tid, preorder_ctrl->indicate_seq, pparm->start_seq);
+		#endif
+	}
+#else
+	preorder_ctrl->indicate_seq = 0xffff;
+	#ifdef DBG_RX_SEQ
+	RTW_INFO("DBG_RX_SEQ "FUNC_ADPT_FMT" tid:%u SN_CLEAR indicate_seq:%d, start_seq:%d\n"
+		, FUNC_ADPT_ARG(padapter), preorder_ctrl->tid, preorder_ctrl->indicate_seq, pparm->start_seq);
+	#endif
+#endif
+
+	/*
+	  * status = 0 means accept this addba req
+	  * status = 37 means reject this addba req
+	  */
+	if (pparm->status == 0) {
+		preorder_ctrl->enable = _TRUE;
+		preorder_ctrl->ampdu_size = pparm->size;
+	} else if (pparm->status == 37)
+		preorder_ctrl->enable = _FALSE;
+
+exit:
+	return H2C_SUCCESS;
+}
+
+u8 chk_bmc_sleepq_cmd(_adapter *padapter)
+{
+	struct cmd_obj *ph2c;
+	struct cmd_priv *pcmdpriv = &(padapter->cmdpriv);
+	u8 res = _SUCCESS;
+
+
+	ph2c = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj));
+	if (ph2c == NULL) {
+		res = _FAIL;
+		goto exit;
+	}
+
+	init_h2fwcmd_w_parm_no_parm_rsp(ph2c, GEN_CMD_CODE(_ChkBMCSleepq));
+
+	res = rtw_enqueue_cmd(pcmdpriv, ph2c);
+
+exit:
+
+
+	return res;
+}
+
+u8 set_tx_beacon_cmd(_adapter *padapter)
+{
+	struct cmd_obj	*ph2c;
+	struct Tx_Beacon_param	*ptxBeacon_parm;
+	struct cmd_priv	*pcmdpriv = &(padapter->cmdpriv);
+	struct mlme_ext_priv	*pmlmeext = &padapter->mlmeextpriv;
+	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
+	u8	res = _SUCCESS;
+	int len_diff = 0;
+
+
+	ph2c = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj));
+	if (ph2c == NULL) {
+		res = _FAIL;
+		goto exit;
+	}
+
+	ptxBeacon_parm = (struct Tx_Beacon_param *)rtw_zmalloc(sizeof(struct Tx_Beacon_param));
+	if (ptxBeacon_parm == NULL) {
+		rtw_mfree((unsigned char *)ph2c, sizeof(struct	cmd_obj));
+		res = _FAIL;
+		goto exit;
+	}
+
+	_rtw_memcpy(&(ptxBeacon_parm->network), &(pmlmeinfo->network), sizeof(WLAN_BSSID_EX));
+
+	len_diff = update_hidden_ssid(
+			   ptxBeacon_parm->network.IEs + _BEACON_IE_OFFSET_
+		   , ptxBeacon_parm->network.IELength - _BEACON_IE_OFFSET_
+			   , pmlmeinfo->hidden_ssid_mode
+		   );
+	ptxBeacon_parm->network.IELength += len_diff;
+
+	init_h2fwcmd_w_parm_no_rsp(ph2c, ptxBeacon_parm, GEN_CMD_CODE(_TX_Beacon));
+
+	res = rtw_enqueue_cmd(pcmdpriv, ph2c);
+
+
+exit:
+
+
+	return res;
+}
+
+
+u8 mlme_evt_hdl(_adapter *padapter, unsigned char *pbuf)
+{
+	u8 evt_code, evt_seq;
+	u16 evt_sz;
+	uint	*peventbuf;
+	void (*event_callback)(_adapter *dev, u8 *pbuf);
+	struct evt_priv *pevt_priv = &(padapter->evtpriv);
+
+	if (pbuf == NULL)
+		goto _abort_event_;
+
+	peventbuf = (uint *)pbuf;
+	evt_sz = (u16)(*peventbuf & 0xffff);
+	evt_seq = (u8)((*peventbuf >> 24) & 0x7f);
+	evt_code = (u8)((*peventbuf >> 16) & 0xff);
+
+
+#ifdef CHECK_EVENT_SEQ
+	/* checking event sequence...		 */
+	if (evt_seq != (ATOMIC_READ(&pevt_priv->event_seq) & 0x7f)) {
+
+		pevt_priv->event_seq = (evt_seq + 1) & 0x7f;
+
+		goto _abort_event_;
+	}
+#endif
+
+	/* checking if event code is valid */
+	if (evt_code >= MAX_C2HEVT) {
+		goto _abort_event_;
+	}
+
+	/* checking if event size match the event parm size	 */
+	if ((wlanevents[evt_code].parmsize != 0) &&
+	    (wlanevents[evt_code].parmsize != evt_sz)) {
+
+		goto _abort_event_;
+
+	}
+
+	ATOMIC_INC(&pevt_priv->event_seq);
+
+	peventbuf += 2;
+
+	if (peventbuf) {
+		event_callback = wlanevents[evt_code].event_callback;
+		event_callback(padapter, (u8 *)peventbuf);
+
+		pevt_priv->evt_done_cnt++;
+	}
+
+
+_abort_event_:
+
+
+	return H2C_SUCCESS;
+
+}
+
+u8 h2c_msg_hdl(_adapter *padapter, unsigned char *pbuf)
+{
+	if (!pbuf)
+		return H2C_PARAMETERS_ERROR;
+
+	return H2C_SUCCESS;
+}
+
+u8 chk_bmc_sleepq_hdl(_adapter *padapter, unsigned char *pbuf)
+{
+#ifdef CONFIG_AP_MODE
+	_irqL irqL;
+	struct sta_info *psta_bmc;
+	_list	*xmitframe_plist, *xmitframe_phead;
+	struct xmit_frame *pxmitframe = NULL;
+	struct xmit_priv *pxmitpriv = &padapter->xmitpriv;
+	struct sta_priv  *pstapriv = &padapter->stapriv;
+
+	/* for BC/MC Frames */
+	psta_bmc = rtw_get_bcmc_stainfo(padapter);
+	if (!psta_bmc)
+		return H2C_SUCCESS;
+
+	if ((rtw_tim_map_is_set(padapter, pstapriv->tim_bitmap, 0)) && (psta_bmc->sleepq_len > 0)) {
+#ifndef CONFIG_PCI_HCI
+		rtw_msleep_os(10);/* 10ms, ATIM(HIQ) Windows */
+#endif
+		/* _enter_critical_bh(&psta_bmc->sleep_q.lock, &irqL); */
+		_enter_critical_bh(&pxmitpriv->lock, &irqL);
+
+		xmitframe_phead = get_list_head(&psta_bmc->sleep_q);
+		xmitframe_plist = get_next(xmitframe_phead);
+
+		while ((rtw_end_of_queue_search(xmitframe_phead, xmitframe_plist)) == _FALSE) {
+			pxmitframe = LIST_CONTAINOR(xmitframe_plist, struct xmit_frame, list);
+
+			xmitframe_plist = get_next(xmitframe_plist);
+
+			rtw_list_delete(&pxmitframe->list);
+
+			psta_bmc->sleepq_len--;
+			if (psta_bmc->sleepq_len > 0)
+				pxmitframe->attrib.mdata = 1;
+			else
+				pxmitframe->attrib.mdata = 0;
+
+			pxmitframe->attrib.triggered = 1;
+
+			if (xmitframe_hiq_filter(pxmitframe) == _TRUE)
+				pxmitframe->attrib.qsel = QSLT_HIGH;/* HIQ */
+
+#if 0
+			_exit_critical_bh(&psta_bmc->sleep_q.lock, &irqL);
+			if (rtw_hal_xmit(padapter, pxmitframe) == _TRUE)
+				rtw_os_xmit_complete(padapter, pxmitframe);
+			_enter_critical_bh(&psta_bmc->sleep_q.lock, &irqL);
+#endif
+			rtw_hal_xmitframe_enqueue(padapter, pxmitframe);
+		}
+
+		/* _exit_critical_bh(&psta_bmc->sleep_q.lock, &irqL); */
+		_exit_critical_bh(&pxmitpriv->lock, &irqL);
+
+		if (rtw_get_intf_type(padapter) != RTW_PCIE) {
+			/* check hi queue and bmc_sleepq */
+			rtw_chk_hi_queue_cmd(padapter);
+		}
+	}
+#endif
+
+	return H2C_SUCCESS;
+}
+
+u8 tx_beacon_hdl(_adapter *padapter, unsigned char *pbuf)
+{
+	/*RTW_INFO(FUNC_ADPT_FMT, FUNC_ADPT_ARG(padapter));*/
+#ifdef CONFIG_SWTIMER_BASED_TXBCN
+
+	tx_beacon_handlder(padapter->dvobj);
+
+#else
+
+	if (send_beacon(padapter) == _FAIL) {
+		RTW_INFO("issue_beacon, fail!\n");
+		return H2C_PARAMETERS_ERROR;
+	}
+
+	/* tx bc/mc frames after update TIM */
+	chk_bmc_sleepq_hdl(padapter, NULL);
+#endif
+
+	return H2C_SUCCESS;
+}
+
+/*
+* according to channel
+* add/remove WLAN_BSSID_EX.IEs's ERP ie
+* set WLAN_BSSID_EX.SupportedRates
+* update WLAN_BSSID_EX.IEs's Supported Rate and Extended Supported Rate ie
+*/
+void change_band_update_ie(_adapter *padapter, WLAN_BSSID_EX *pnetwork, u8 ch)
+{
+	u8	network_type, rate_len, total_rate_len, remainder_rate_len;
+	struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
+	struct rf_ctl_t *rfctl = adapter_to_rfctl(padapter);
+	u8	erpinfo = 0x4;
+
+	if (ch >= 36) {
+		network_type = WIRELESS_11A;
+		total_rate_len = IEEE80211_NUM_OFDM_RATESLEN;
+		rtw_remove_bcn_ie(padapter, pnetwork, _ERPINFO_IE_);
+		#ifdef CONFIG_80211AC_VHT
+		/* if channel in 5G band, then add vht ie . */
+		if ((pmlmepriv->htpriv.ht_option == _TRUE)
+			&& REGSTY_IS_11AC_ENABLE(&padapter->registrypriv)
+			&& is_supported_vht(padapter->registrypriv.wireless_mode)
+			&& (!rfctl->country_ent || COUNTRY_CHPLAN_EN_11AC(rfctl->country_ent))
+		) {
+			if (REGSTY_IS_11AC_AUTO(&padapter->registrypriv)
+				|| pmlmepriv->ori_vht_en)
+				rtw_vht_ies_attach(padapter, pnetwork);
+		}
+		#endif
+	} else {
+		network_type = WIRELESS_11BG;
+		total_rate_len = IEEE80211_CCK_RATE_LEN + IEEE80211_NUM_OFDM_RATESLEN;
+		rtw_add_bcn_ie(padapter, pnetwork, _ERPINFO_IE_, &erpinfo, 1);
+		#ifdef CONFIG_80211AC_VHT
+		rtw_vht_ies_detach(padapter, pnetwork);
+		#endif
+	}
+
+	rtw_set_supported_rate(pnetwork->SupportedRates, network_type);
+
+	UpdateBrateTbl(padapter, pnetwork->SupportedRates);
+
+	if (total_rate_len > 8) {
+		rate_len = 8;
+		remainder_rate_len = total_rate_len - 8;
+	} else {
+		rate_len = total_rate_len;
+		remainder_rate_len = 0;
+	}
+
+	rtw_add_bcn_ie(padapter, pnetwork, _SUPPORTEDRATES_IE_, pnetwork->SupportedRates, rate_len);
+
+	if (remainder_rate_len)
+		rtw_add_bcn_ie(padapter, pnetwork, _EXT_SUPPORTEDRATES_IE_, (pnetwork->SupportedRates + 8), remainder_rate_len);
+	else
+		rtw_remove_bcn_ie(padapter, pnetwork, _EXT_SUPPORTEDRATES_IE_);
+
+	pnetwork->Length = get_WLAN_BSSID_EX_sz(pnetwork);
+}
+
+void rtw_join_done_chk_ch(_adapter *adapter, int join_res)
+{
+#define DUMP_ADAPTERS_STATUS 0
+
+	struct dvobj_priv *dvobj;
+	_adapter *iface;
+	struct mlme_priv *mlme;
+	struct mlme_ext_priv *mlmeext;
+	u8 u_ch, u_offset, u_bw;
+	int i;
+
+	dvobj = adapter_to_dvobj(adapter);
+
+	if (DUMP_ADAPTERS_STATUS) {
+		RTW_INFO(FUNC_ADPT_FMT" enter\n", FUNC_ADPT_ARG(adapter));
+		dump_adapters_status(RTW_DBGDUMP , dvobj);
+	}
+
+	if (join_res >= 0) {
+
+#ifdef CONFIG_MCC_MODE
+		/* MCC setting success, don't go to ch union process */
+		if (rtw_hal_set_mcc_setting_join_done_chk_ch(adapter))
+			return;
+#endif /* CONFIG_MCC_MODE */
+
+		if (rtw_mi_get_ch_setting_union(adapter, &u_ch, &u_bw, &u_offset) <= 0) {
+			dump_adapters_status(RTW_DBGDUMP , dvobj);
+			rtw_warn_on(1);
+		}
+
+		for (i = 0; i < dvobj->iface_nums; i++) {
+			iface = dvobj->padapters[i];
+			mlme = &iface->mlmepriv;
+			mlmeext = &iface->mlmeextpriv;
+
+			if (!iface || iface == adapter)
+				continue;
+
+			if ((MLME_IS_AP(iface) || MLME_IS_MESH(iface))
+				&& check_fwstate(mlme, WIFI_ASOC_STATE)
+			) {
+				u8 ori_ch, ori_bw, ori_offset;
+				bool is_grouped = rtw_is_chbw_grouped(u_ch, u_bw, u_offset
+					, mlmeext->cur_channel, mlmeext->cur_bwmode, mlmeext->cur_ch_offset);
+
+				if (is_grouped == _FALSE) {
+					/* handle AP which need to switch ch setting */
+
+					ori_ch = mlmeext->cur_channel;
+					ori_bw = mlmeext->cur_bwmode;
+					ori_offset = mlmeext->cur_ch_offset;
+
+					/* restore original bw, adjust bw by registry setting on target ch */
+					mlmeext->cur_bwmode = mlme->ori_bw;
+					mlmeext->cur_channel = u_ch;
+					rtw_adjust_chbw(iface, mlmeext->cur_channel, &mlmeext->cur_bwmode, &mlmeext->cur_ch_offset);
+					#ifdef CONFIG_RTW_MESH
+					if (MLME_IS_MESH(iface))
+						rtw_mesh_adjust_chbw(mlmeext->cur_channel, &mlmeext->cur_bwmode, &mlmeext->cur_ch_offset);
+					#endif
+
+					rtw_chset_sync_chbw(adapter_to_chset(adapter)
+						, &mlmeext->cur_channel, &mlmeext->cur_bwmode, &mlmeext->cur_ch_offset
+						, &u_ch, &u_bw, &u_offset);
+
+					RTW_INFO(FUNC_ADPT_FMT" %u,%u,%u => %u,%u,%u\n", FUNC_ADPT_ARG(iface)
+						, ori_ch, ori_bw, ori_offset
+						, mlmeext->cur_channel, mlmeext->cur_bwmode, mlmeext->cur_ch_offset);
+
+					rtw_ap_update_bss_chbw(iface, &(mlmeext->mlmext_info.network)
+						, mlmeext->cur_channel, mlmeext->cur_bwmode, mlmeext->cur_ch_offset);
+
+					_rtw_memcpy(&(mlme->cur_network.network), &(mlmeext->mlmext_info.network), sizeof(WLAN_BSSID_EX));
+
+					rtw_start_bss_hdl_after_chbw_decided(iface);
+
+					if (MLME_IS_GO(iface) || MLME_IS_MESH(iface)) { /* pure AP is not needed*/
+						#if defined(CONFIG_IOCTL_CFG80211) && (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 5, 0))
+						u8 ht_option = 0;
+
+						#ifdef CONFIG_80211N_HT
+						ht_option = mlme->htpriv.ht_option;
+						#endif
+
+						rtw_cfg80211_ch_switch_notify(iface
+							, mlmeext->cur_channel, mlmeext->cur_bwmode, mlmeext->cur_ch_offset
+							, ht_option);
+						#endif
+					}
+				}
+
+				clr_fwstate(mlme, WIFI_OP_CH_SWITCHING);
+				update_beacon(iface, 0xFF, NULL, _TRUE);
+			}
+		}
+
+#ifdef CONFIG_DFS_MASTER
+		rtw_dfs_rd_en_decision(adapter, MLME_STA_CONNECTED, 0);
+#endif
+	} else {
+		for (i = 0; i < dvobj->iface_nums; i++) {
+			iface = dvobj->padapters[i];
+			mlme = &iface->mlmepriv;
+			mlmeext = &iface->mlmeextpriv;
+
+			if (!iface || iface == adapter)
+				continue;
+
+			if ((MLME_IS_AP(iface) || MLME_IS_MESH(iface))
+				&& check_fwstate(mlme, WIFI_ASOC_STATE)
+			) {
+				clr_fwstate(mlme, WIFI_OP_CH_SWITCHING);
+				update_beacon(iface, 0xFF, NULL, _TRUE);
+			}
+		}
+#ifdef CONFIG_DFS_MASTER
+		rtw_dfs_rd_en_decision(adapter, MLME_STA_DISCONNECTED, 0);
+#endif
+	}
+
+	if (rtw_mi_get_ch_setting_union(adapter, &u_ch, &u_bw, &u_offset)) {
+		RTW_INFO(FUNC_ADPT_FMT" union:%u,%u,%u\n", FUNC_ADPT_ARG(adapter), u_ch, u_bw, u_offset);
+		set_channel_bwmode(adapter, u_ch, u_offset, u_bw);
+		rtw_mi_update_union_chan_inf(adapter, u_ch, u_offset, u_bw);
+	}
+
+	if (DUMP_ADAPTERS_STATUS) {
+		RTW_INFO(FUNC_ADPT_FMT" exit\n", FUNC_ADPT_ARG(adapter));
+		dump_adapters_status(RTW_DBGDUMP , dvobj);
+	}
+}
+
+int rtw_chk_start_clnt_join(_adapter *adapter, u8 *ch, u8 *bw, u8 *offset)
+{
+#ifdef CONFIG_CONCURRENT_MODE
+	bool chbw_allow = _TRUE;
+#endif
+	bool connect_allow = _TRUE;
+	struct mlme_ext_priv	*pmlmeext = &adapter->mlmeextpriv;
+	u8 cur_ch, cur_bw, cur_ch_offset;
+	u8 u_ch, u_offset, u_bw;
+
+	u_ch = cur_ch = pmlmeext->cur_channel;
+	u_bw = cur_bw = pmlmeext->cur_bwmode;
+	u_offset = cur_ch_offset = pmlmeext->cur_ch_offset;
+
+	if (!ch || !bw || !offset) {
+		connect_allow = _FALSE;
+		rtw_warn_on(1);
+		goto exit;
+	}
+
+	if (cur_ch == 0) {
+		connect_allow = _FALSE;
+		RTW_ERR(FUNC_ADPT_FMT" cur_ch:%u\n"
+			, FUNC_ADPT_ARG(adapter), cur_ch);
+		rtw_warn_on(1);
+		goto exit;
+	}
+	RTW_INFO(FUNC_ADPT_FMT" req: %u,%u,%u\n", FUNC_ADPT_ARG(adapter), u_ch, u_bw, u_offset);
+
+#ifdef CONFIG_CONCURRENT_MODE
+	{
+		struct dvobj_priv *dvobj;
+		_adapter *iface;
+		struct mlme_priv *mlme;
+		struct mlme_ext_priv *mlmeext;
+		struct mi_state mstate;
+		int i;
+
+		dvobj = adapter_to_dvobj(adapter);
+
+		rtw_mi_status_no_self(adapter, &mstate);
+		RTW_INFO(FUNC_ADPT_FMT" others ld_sta_num:%u, ap_num:%u, mesh_num:%u\n"
+			, FUNC_ADPT_ARG(adapter), MSTATE_STA_LD_NUM(&mstate)
+			, MSTATE_AP_NUM(&mstate), MSTATE_MESH_NUM(&mstate));
+
+		if (!MSTATE_STA_LD_NUM(&mstate) && !MSTATE_AP_NUM(&mstate) && !MSTATE_MESH_NUM(&mstate)) {
+			/* consider linking STA? */
+			goto connect_allow_hdl;
+		}
+
+		if (rtw_mi_get_ch_setting_union_no_self(adapter, &u_ch, &u_bw, &u_offset) <= 0) {
+			dump_adapters_status(RTW_DBGDUMP , dvobj);
+			rtw_warn_on(1);
+		}
+		RTW_INFO(FUNC_ADPT_FMT" others union:%u,%u,%u\n"
+			 , FUNC_ADPT_ARG(adapter), u_ch, u_bw, u_offset);
+
+		/* chbw_allow? */
+		chbw_allow = rtw_is_chbw_grouped(pmlmeext->cur_channel, pmlmeext->cur_bwmode, pmlmeext->cur_ch_offset
+						 , u_ch, u_bw, u_offset);
+
+		RTW_INFO(FUNC_ADPT_FMT" chbw_allow:%d\n"
+			 , FUNC_ADPT_ARG(adapter), chbw_allow);
+
+#ifdef CONFIG_MCC_MODE
+		/* check setting success, don't go to ch union process */
+		if (rtw_hal_set_mcc_setting_chk_start_clnt_join(adapter, &u_ch, &u_bw, &u_offset, chbw_allow))
+			goto exit;
+#endif
+
+		if (chbw_allow == _TRUE) {
+			rtw_sync_chbw(&cur_ch, &cur_bw, &cur_ch_offset, &u_ch, &u_bw, &u_offset);
+			rtw_warn_on(cur_ch != pmlmeext->cur_channel);
+			rtw_warn_on(cur_bw != pmlmeext->cur_bwmode);
+			rtw_warn_on(cur_ch_offset != pmlmeext->cur_ch_offset);
+			goto connect_allow_hdl;
+		}
+
+#ifdef CONFIG_CFG80211_ONECHANNEL_UNDER_CONCURRENT
+		/* chbw_allow is _FALSE, connect allow? */
+		for (i = 0; i < dvobj->iface_nums; i++) {
+			iface = dvobj->padapters[i];
+			mlme = &iface->mlmepriv;
+			mlmeext = &iface->mlmeextpriv;
+
+			if (check_fwstate(mlme, WIFI_STATION_STATE)
+			    && check_fwstate(mlme, WIFI_ASOC_STATE)
+#if defined(CONFIG_P2P)
+			    && rtw_p2p_chk_state(&(iface->wdinfo), P2P_STATE_NONE)
+#endif
+			   ) {
+				connect_allow = _FALSE;
+				break;
+			}
+		}
+#endif /* CONFIG_CFG80211_ONECHANNEL_UNDER_CONCURRENT */
+
+		if (MSTATE_STA_LD_NUM(&mstate) + MSTATE_AP_LD_NUM(&mstate) + MSTATE_MESH_LD_NUM(&mstate) >= 4)
+			connect_allow = _FALSE;
+
+		RTW_INFO(FUNC_ADPT_FMT" connect_allow:%d\n"
+			 , FUNC_ADPT_ARG(adapter), connect_allow);
+
+		if (connect_allow == _FALSE)
+			goto exit;
+
+connect_allow_hdl:
+		/* connect_allow == _TRUE */
+
+		if (chbw_allow == _FALSE) {
+			u_ch = cur_ch;
+			u_bw = cur_bw;
+			u_offset = cur_ch_offset;
+
+			for (i = 0; i < dvobj->iface_nums; i++) {
+				iface = dvobj->padapters[i];
+				mlme = &iface->mlmepriv;
+				mlmeext = &iface->mlmeextpriv;
+
+				if (!iface || iface == adapter)
+					continue;
+
+				if ((MLME_IS_AP(iface) || MLME_IS_MESH(iface))
+					&& check_fwstate(mlme, WIFI_ASOC_STATE)
+				) {
+					#ifdef CONFIG_SPCT_CH_SWITCH
+					if (1)
+						rtw_ap_inform_ch_switch(iface, pmlmeext->cur_channel , pmlmeext->cur_ch_offset);
+					else
+					#endif
+						rtw_sta_flush(iface, _FALSE);
+
+					rtw_hal_set_hwreg(iface, HW_VAR_CHECK_TXBUF, 0);
+					set_fwstate(mlme, WIFI_OP_CH_SWITCHING);
+
+				} else if (check_fwstate(mlme, WIFI_STATION_STATE)
+					&& check_fwstate(mlme, WIFI_ASOC_STATE)
+				) {
+					rtw_disassoc_cmd(iface, 500, RTW_CMDF_DIRECTLY);
+					rtw_indicate_disconnect(iface, 0, _FALSE);
+					rtw_free_assoc_resources(iface, _TRUE);
+				}
+			}
+		}
+
+		#ifdef CONFIG_DFS_MASTER
+		rtw_dfs_rd_en_decision(adapter, MLME_STA_CONNECTING, 0);
+		#endif
+	}
+#endif /* CONFIG_CONCURRENT_MODE */
+
+exit:
+
+	if (connect_allow == _TRUE) {
+		RTW_INFO(FUNC_ADPT_FMT" union: %u,%u,%u\n", FUNC_ADPT_ARG(adapter), u_ch, u_bw, u_offset);
+		*ch = u_ch;
+		*bw = u_bw;
+		*offset = u_offset;
+	}
+
+	return connect_allow == _TRUE ? _SUCCESS : _FAIL;
+}
+
+
+u8 rtw_set_chbw_hdl(_adapter *padapter, u8 *pbuf)
+{
+	struct set_ch_parm *set_ch_parm;
+	struct mlme_ext_priv	*pmlmeext = &padapter->mlmeextpriv;
+
+	if (!pbuf)
+		return H2C_PARAMETERS_ERROR;
+
+	set_ch_parm = (struct set_ch_parm *)pbuf;
+
+	RTW_INFO(FUNC_NDEV_FMT" ch:%u, bw:%u, ch_offset:%u\n",
+		 FUNC_NDEV_ARG(padapter->pnetdev),
+		 set_ch_parm->ch, set_ch_parm->bw, set_ch_parm->ch_offset);
+
+	pmlmeext->cur_channel = set_ch_parm->ch;
+	pmlmeext->cur_ch_offset = set_ch_parm->ch_offset;
+	pmlmeext->cur_bwmode = set_ch_parm->bw;
+
+	set_channel_bwmode(padapter, set_ch_parm->ch, set_ch_parm->ch_offset, set_ch_parm->bw);
+
+	return	H2C_SUCCESS;
+}
+
+u8 set_chplan_hdl(_adapter *padapter, unsigned char *pbuf)
+{
+	struct SetChannelPlan_param *setChannelPlan_param;
+	struct rf_ctl_t *rfctl = adapter_to_rfctl(padapter);
+
+	if (!pbuf)
+		return H2C_PARAMETERS_ERROR;
+
+	setChannelPlan_param = (struct SetChannelPlan_param *)pbuf;
+
+	if (!rtw_is_channel_plan_valid(setChannelPlan_param->channel_plan))
+		return H2C_PARAMETERS_ERROR;
+
+	rfctl->country_ent = setChannelPlan_param->country_ent;
+	rfctl->ChannelPlan = setChannelPlan_param->channel_plan;
+
+	rfctl->max_chan_nums = init_channel_set(padapter, rfctl->ChannelPlan, rfctl->channel_set);
+	init_channel_list(padapter, rfctl->channel_set, &rfctl->channel_list);
+#ifdef CONFIG_TXPWR_LIMIT
+	rtw_txpwr_init_regd(rfctl);
+#endif
+
+	rtw_hal_set_odm_var(padapter, HAL_ODM_REGULATION, NULL, _TRUE);
+
+#ifdef CONFIG_IOCTL_CFG80211
+	rtw_regd_apply_flags(adapter_to_wiphy(padapter));
+#endif
+
+	return	H2C_SUCCESS;
+}
+
+u8 led_blink_hdl(_adapter *padapter, unsigned char *pbuf)
+{
+	struct LedBlink_param *ledBlink_param;
+
+	if (!pbuf)
+		return H2C_PARAMETERS_ERROR;
+
+	ledBlink_param = (struct LedBlink_param *)pbuf;
+
+#ifdef CONFIG_RTW_LED_HANDLED_BY_CMD_THREAD
+	BlinkHandler((PLED_DATA)ledBlink_param->pLed);
+#endif
+
+	return	H2C_SUCCESS;
+}
+
+u8 set_csa_hdl(_adapter *adapter, unsigned char *pbuf)
+{
+#ifdef CONFIG_DFS
+	struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter);
+
+	if (rfctl->csa_ch)
+		rtw_dfs_ch_switch_hdl(adapter_to_dvobj(adapter));
+#endif
+	return	H2C_SUCCESS;
+}
+
+u8 tdls_hdl(_adapter *padapter, unsigned char *pbuf)
+{
+#ifdef CONFIG_TDLS
+	_irqL irqL;
+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(padapter);
+	struct tdls_info *ptdlsinfo = &padapter->tdlsinfo;
+#ifdef CONFIG_TDLS_CH_SW
+	struct tdls_ch_switch *pchsw_info = &ptdlsinfo->chsw_info;
+#endif
+	struct TDLSoption_param *TDLSoption;
+	struct sta_info *ptdls_sta = NULL;
+	struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
+	struct mlme_ext_info *pmlmeinfo = &pmlmeext->mlmext_info;
+	struct sta_info *ap_sta = rtw_get_stainfo(&padapter->stapriv, get_my_bssid(&(pmlmeinfo->network)));
+	u8 survey_channel, i, min, option;
+	struct tdls_txmgmt txmgmt;
+	u32 setchtime, resp_sleep = 0, wait_time;
+	u8 zaddr[ETH_ALEN] = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00};
+	u8 ret;
+	u8 doiqk;
+	u64 tx_ra_bitmap = 0;
+
+	if (!pbuf)
+		return H2C_PARAMETERS_ERROR;
+
+	TDLSoption = (struct TDLSoption_param *)pbuf;
+	option = TDLSoption->option;
+
+	if (!_rtw_memcmp(TDLSoption->addr, zaddr, ETH_ALEN)) {
+		ptdls_sta = rtw_get_stainfo(&(padapter->stapriv), TDLSoption->addr);
+		if (ptdls_sta == NULL)
+			return H2C_REJECTED;
+	} else {
+		if (!(option == TDLS_RS_RCR))
+			return H2C_REJECTED;
+	}
+
+	/* _enter_critical_bh(&(ptdlsinfo->hdl_lock), &irqL); */
+	/* RTW_INFO("[%s] option:%d\n", __FUNCTION__, option); */
+
+	switch (option) {
+	case TDLS_ESTABLISHED: {
+		/* As long as TDLS handshake success, we should set RCR_CBSSID_DATA bit to 0 */
+		/* So we can receive all kinds of data frames. */
+		u8 sta_band = 0;
+
+		/* leave ALL PS when TDLS is established */
+		rtw_pwr_wakeup(padapter);
+
+		rtw_hal_rcr_set_chk_bssid(padapter, MLME_TDLS_LINKED);
+		RTW_INFO("Created Direct Link with "MAC_FMT"\n", MAC_ARG(ptdls_sta->cmn.mac_addr));
+
+		/* Set TDLS sta rate. */
+		/* Update station supportRate */
+		rtw_hal_update_sta_ra_info(padapter, ptdls_sta);
+		tx_ra_bitmap = ptdls_sta->cmn.ra_info.ramask;
+
+		if (pmlmeext->cur_channel > 14) {
+			if (tx_ra_bitmap & 0xffff000)
+				sta_band |= WIRELESS_11_5N ;
+
+			if (tx_ra_bitmap & 0xff0)
+				sta_band |= WIRELESS_11A;
+
+			/* 5G band */
+#ifdef CONFIG_80211AC_VHT
+			if (ptdls_sta->vhtpriv.vht_option)
+				sta_band = WIRELESS_11_5AC;
+#endif
+
+		} else {
+			if (tx_ra_bitmap & 0xffff000)
+				sta_band |= WIRELESS_11_24N;
+
+			if (tx_ra_bitmap & 0xff0)
+				sta_band |= WIRELESS_11G;
+
+			if (tx_ra_bitmap & 0x0f)
+				sta_band |= WIRELESS_11B;
+		}
+		ptdls_sta->wireless_mode = sta_band;
+		rtw_hal_update_sta_wset(padapter, ptdls_sta);
+		/* Sta mode */
+		rtw_hal_set_odm_var(padapter, HAL_ODM_STA_INFO, ptdls_sta, _TRUE);
+
+		set_sta_rate(padapter, ptdls_sta);
+		rtw_sta_media_status_rpt(padapter, ptdls_sta, 1);
+		break;
+	}
+	case TDLS_ISSUE_PTI:
+		ptdls_sta->tdls_sta_state |= TDLS_WAIT_PTR_STATE;
+		issue_tdls_peer_traffic_indication(padapter, ptdls_sta);
+		_set_timer(&ptdls_sta->pti_timer, TDLS_PTI_TIME);
+		break;
+#ifdef CONFIG_TDLS_CH_SW
+	case TDLS_CH_SW_RESP:
+		_rtw_memset(&txmgmt, 0x00, sizeof(struct tdls_txmgmt));
+		txmgmt.status_code = 0;
+		_rtw_memcpy(txmgmt.peer, ptdls_sta->cmn.mac_addr, ETH_ALEN);
+
+		if (ap_sta)
+			rtw_hal_macid_sleep(padapter, ap_sta->cmn.mac_id);
+		issue_nulldata(padapter, NULL, 1, 3, 3);
+
+		RTW_INFO("[TDLS ] issue tdls channel switch response\n");
+		ret = issue_tdls_ch_switch_rsp(padapter, &txmgmt, _TRUE);
+
+		/* If we receive TDLS_CH_SW_REQ at off channel which it's target is AP's channel */
+		/* then we just switch to AP's channel*/
+		if (padapter->mlmeextpriv.cur_channel == pchsw_info->off_ch_num) {
+			rtw_tdls_cmd(padapter, ptdls_sta->cmn.mac_addr, TDLS_CH_SW_END_TO_BASE_CHNL);
+			break;
+		}
+
+		if (ret == _SUCCESS)
+			rtw_tdls_cmd(padapter, ptdls_sta->cmn.mac_addr, TDLS_CH_SW_TO_OFF_CHNL);
+		else
+			RTW_INFO("[TDLS] issue_tdls_ch_switch_rsp wait ack fail !!!!!!!!!!\n");
+
+		break;
+	case TDLS_CH_SW_PREPARE:
+		pchsw_info->ch_sw_state |= TDLS_CH_SWITCH_PREPARE_STATE;
+
+		/* to collect IQK info of off-chnl */
+		doiqk = _TRUE;
+		rtw_hal_set_hwreg(padapter, HW_VAR_DO_IQK, &doiqk);
+		set_channel_bwmode(padapter, pchsw_info->off_ch_num, pchsw_info->ch_offset, (pchsw_info->ch_offset) ? CHANNEL_WIDTH_40 : CHANNEL_WIDTH_20);
+		doiqk = _FALSE;
+		rtw_hal_set_hwreg(padapter, HW_VAR_DO_IQK, &doiqk);
+
+		/* switch back to base-chnl */
+		set_channel_bwmode(padapter, pmlmeext->cur_channel, pmlmeext->cur_ch_offset, pmlmeext->cur_bwmode);
+
+		rtw_tdls_cmd(padapter, ptdls_sta->cmn.mac_addr, TDLS_CH_SW_START);
+
+		pchsw_info->ch_sw_state &= ~(TDLS_CH_SWITCH_PREPARE_STATE);
+
+		break;
+	case TDLS_CH_SW_START:
+		rtw_tdls_set_ch_sw_oper_control(padapter, _TRUE);
+		break;
+	case TDLS_CH_SW_TO_OFF_CHNL:
+		if (ap_sta)
+			rtw_hal_macid_sleep(padapter, ap_sta->cmn.mac_id);
+		issue_nulldata(padapter, NULL, 1, 3, 3);
+
+		if (padapter->registrypriv.wifi_spec == 0) {
+		if (!(pchsw_info->ch_sw_state & TDLS_CH_SW_INITIATOR_STATE))
+			_set_timer(&ptdls_sta->ch_sw_timer, (u32)(ptdls_sta->ch_switch_timeout) / 1000);
+		}
+
+		if (rtw_tdls_do_ch_sw(padapter, ptdls_sta, TDLS_CH_SW_OFF_CHNL, pchsw_info->off_ch_num,
+			pchsw_info->ch_offset, (pchsw_info->ch_offset) ? CHANNEL_WIDTH_40 : CHANNEL_WIDTH_20, ptdls_sta->ch_switch_time) == _SUCCESS) {
+			pchsw_info->ch_sw_state &= ~(TDLS_PEER_AT_OFF_STATE);
+			if (pchsw_info->ch_sw_state & TDLS_CH_SW_INITIATOR_STATE) {
+				if (issue_nulldata_to_TDLS_peer_STA(ptdls_sta->padapter, ptdls_sta->cmn.mac_addr, 0, 1, 
+					(padapter->registrypriv.wifi_spec == 0) ? 3 : 0) == _FAIL)
+					rtw_tdls_cmd(padapter, ptdls_sta->cmn.mac_addr, TDLS_CH_SW_TO_BASE_CHNL);
+			}
+		} else {
+			if (!(pchsw_info->ch_sw_state & TDLS_CH_SW_INITIATOR_STATE))
+				_cancel_timer_ex(&ptdls_sta->ch_sw_timer);
+		}
+
+
+		break;
+	case TDLS_CH_SW_END:
+	case TDLS_CH_SW_END_TO_BASE_CHNL:
+		rtw_tdls_set_ch_sw_oper_control(padapter, _FALSE);
+		_cancel_timer_ex(&ptdls_sta->ch_sw_timer);
+		_cancel_timer_ex(&ptdls_sta->stay_on_base_chnl_timer);
+		_cancel_timer_ex(&ptdls_sta->ch_sw_monitor_timer);
+#if 0
+		_rtw_memset(pHalData->tdls_ch_sw_iqk_info_base_chnl, 0x00, sizeof(pHalData->tdls_ch_sw_iqk_info_base_chnl));
+		_rtw_memset(pHalData->tdls_ch_sw_iqk_info_off_chnl, 0x00, sizeof(pHalData->tdls_ch_sw_iqk_info_off_chnl));
+#endif
+
+		if (option == TDLS_CH_SW_END_TO_BASE_CHNL)
+			rtw_tdls_cmd(padapter, ptdls_sta->cmn.mac_addr, TDLS_CH_SW_TO_BASE_CHNL);
+
+		break;
+	case TDLS_CH_SW_TO_BASE_CHNL_UNSOLICITED:
+	case TDLS_CH_SW_TO_BASE_CHNL:
+		pchsw_info->ch_sw_state &= ~(TDLS_PEER_AT_OFF_STATE | TDLS_WAIT_CH_RSP_STATE);
+
+		if (option == TDLS_CH_SW_TO_BASE_CHNL_UNSOLICITED) {
+			if (ptdls_sta != NULL) {
+				/* Send unsolicited channel switch rsp. to peer */
+				_rtw_memset(&txmgmt, 0x00, sizeof(struct tdls_txmgmt));
+				txmgmt.status_code = 0;
+				_rtw_memcpy(txmgmt.peer, ptdls_sta->cmn.mac_addr, ETH_ALEN);
+				issue_tdls_ch_switch_rsp(padapter, &txmgmt, _FALSE);
+			}
+		}
+
+		if (rtw_tdls_do_ch_sw(padapter, ptdls_sta, TDLS_CH_SW_BASE_CHNL, pmlmeext->cur_channel,
+			pmlmeext->cur_ch_offset, pmlmeext->cur_bwmode, ptdls_sta->ch_switch_time) == _SUCCESS) {
+			if (ap_sta)
+				rtw_hal_macid_wakeup(padapter, ap_sta->cmn.mac_id);
+			issue_nulldata(padapter, NULL, 0, 3, 3);
+			/* set ch sw monitor timer for responder */
+			if (!(pchsw_info->ch_sw_state & TDLS_CH_SW_INITIATOR_STATE))
+				_set_timer(&ptdls_sta->ch_sw_monitor_timer, TDLS_CH_SW_MONITOR_TIMEOUT);
+		}
+
+		break;
+#endif
+	case TDLS_RS_RCR:
+		rtw_hal_rcr_set_chk_bssid(padapter, MLME_TDLS_NOLINK);
+		break;
+	case TDLS_TEARDOWN_STA:
+	case TDLS_TEARDOWN_STA_NO_WAIT:
+		_rtw_memset(&txmgmt, 0x00, sizeof(struct tdls_txmgmt));
+		txmgmt.status_code = _RSON_TDLS_TEAR_UN_RSN_;
+		_rtw_memcpy(txmgmt.peer, ptdls_sta->cmn.mac_addr, ETH_ALEN);
+
+		issue_tdls_teardown(padapter, &txmgmt, (option == TDLS_TEARDOWN_STA) ? _TRUE : _FALSE);
+
+		break;
+	case TDLS_TEARDOWN_STA_LOCALLY:
+	case TDLS_TEARDOWN_STA_LOCALLY_POST:
+#ifdef CONFIG_TDLS_CH_SW
+		if (_rtw_memcmp(TDLSoption->addr, pchsw_info->addr, ETH_ALEN) == _TRUE) {
+			pchsw_info->ch_sw_state &= ~(TDLS_CH_SW_INITIATOR_STATE |
+						     TDLS_CH_SWITCH_ON_STATE |
+						     TDLS_PEER_AT_OFF_STATE);
+			rtw_tdls_set_ch_sw_oper_control(padapter, _FALSE);
+			_rtw_memset(pchsw_info->addr, 0x00, ETH_ALEN);
+		}
+#endif
+
+		if (option == TDLS_TEARDOWN_STA_LOCALLY)
+			rtw_tdls_teardown_pre_hdl(padapter, ptdls_sta);
+
+		rtw_tdls_teardown_post_hdl(padapter, ptdls_sta, _FALSE);
+
+		if (ptdlsinfo->tdls_sctx != NULL)
+			rtw_sctx_done(&(ptdlsinfo->tdls_sctx));
+
+		break;
+	}
+
+	/* _exit_critical_bh(&(ptdlsinfo->hdl_lock), &irqL); */
+
+	return H2C_SUCCESS;
+#else
+	return H2C_REJECTED;
+#endif /* CONFIG_TDLS */
+
+}
+
+u8 run_in_thread_hdl(_adapter *padapter, u8 *pbuf)
+{
+	struct RunInThread_param *p;
+
+
+	if (NULL == pbuf)
+		return H2C_PARAMETERS_ERROR;
+	p = (struct RunInThread_param *)pbuf;
+
+	if (p->func)
+		p->func(p->context);
+
+	return H2C_SUCCESS;
+}
+
+u8 rtw_getmacreg_hdl(_adapter *padapter, u8 *pbuf)
+{
+
+	struct readMAC_parm *preadmacparm = NULL;
+	u8 sz = 0;
+	u32	addr = 0;
+	u32	value = 0;
+
+	if (!pbuf)
+		return H2C_PARAMETERS_ERROR;
+
+	preadmacparm = (struct readMAC_parm *) pbuf;
+	sz = preadmacparm->len;
+	addr = preadmacparm->addr;
+	value = 0;
+
+	switch (sz) {
+	case 1:
+		value = rtw_read8(padapter, addr);
+		break;
+	case 2:
+		value = rtw_read16(padapter, addr);
+		break;
+	case 4:
+		value = rtw_read32(padapter, addr);
+		break;
+	default:
+		RTW_INFO("%s: Unknown size\n", __func__);
+		break;
+	}
+	RTW_INFO("%s: addr:0x%02x valeu:0x%02x\n", __func__, addr, value);
+
+	return H2C_SUCCESS;
+}
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/core/rtw_mp.c linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/core/rtw_mp.c
--- linux-5.6.3/3rdparty/rtl8821ce/core/rtw_mp.c	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/core/rtw_mp.c	2020-04-10 16:35:06.776658200 +0300
@@ -0,0 +1,3890 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#define _RTW_MP_C_
+#include <drv_types.h>
+#ifdef PLATFORM_FREEBSD
+	#include <sys/unistd.h>		/* for RFHIGHPID */
+#endif
+
+#include "../hal/phydm/phydm_precomp.h"
+#if defined(CONFIG_RTL8723B) || defined(CONFIG_RTL8821A)
+	#include <rtw_bt_mp.h>
+#endif
+
+#ifdef CONFIG_MP_VHT_HW_TX_MODE
+#define CEILING_POS(X) ((X - (int)(X)) > 0 ? (int)(X + 1) : (int)(X))
+#define CEILING_NEG(X) ((X - (int)(X)) < 0 ? (int)(X - 1) : (int)(X))
+#define ceil(X) (((X) > 0) ? CEILING_POS(X) : CEILING_NEG(X))
+
+int rtfloor(float x)
+{
+	int i = x - 2;
+	while
+	(++i <= x - 1)
+		;
+	return i;
+}
+#endif
+
+#ifdef CONFIG_MP_INCLUDED
+u32 read_macreg(_adapter *padapter, u32 addr, u32 sz)
+{
+	u32 val = 0;
+
+	switch (sz) {
+	case 1:
+		val = rtw_read8(padapter, addr);
+		break;
+	case 2:
+		val = rtw_read16(padapter, addr);
+		break;
+	case 4:
+		val = rtw_read32(padapter, addr);
+		break;
+	default:
+		val = 0xffffffff;
+		break;
+	}
+
+	return val;
+
+}
+
+void write_macreg(_adapter *padapter, u32 addr, u32 val, u32 sz)
+{
+	switch (sz) {
+	case 1:
+		rtw_write8(padapter, addr, (u8)val);
+		break;
+	case 2:
+		rtw_write16(padapter, addr, (u16)val);
+		break;
+	case 4:
+		rtw_write32(padapter, addr, val);
+		break;
+	default:
+		break;
+	}
+
+}
+
+u32 read_bbreg(_adapter *padapter, u32 addr, u32 bitmask)
+{
+	return rtw_hal_read_bbreg(padapter, addr, bitmask);
+}
+
+void write_bbreg(_adapter *padapter, u32 addr, u32 bitmask, u32 val)
+{
+	rtw_hal_write_bbreg(padapter, addr, bitmask, val);
+}
+
+u32 _read_rfreg(PADAPTER padapter, u8 rfpath, u32 addr, u32 bitmask)
+{
+	return rtw_hal_read_rfreg(padapter, rfpath, addr, bitmask);
+}
+
+void _write_rfreg(PADAPTER padapter, u8 rfpath, u32 addr, u32 bitmask, u32 val)
+{
+	rtw_hal_write_rfreg(padapter, rfpath, addr, bitmask, val);
+}
+
+u32 read_rfreg(PADAPTER padapter, u8 rfpath, u32 addr)
+{
+	return _read_rfreg(padapter, rfpath, addr, bRFRegOffsetMask);
+}
+
+void write_rfreg(PADAPTER padapter, u8 rfpath, u32 addr, u32 val)
+{
+	_write_rfreg(padapter, rfpath, addr, bRFRegOffsetMask, val);
+}
+
+static void _init_mp_priv_(struct mp_priv *pmp_priv)
+{
+	WLAN_BSSID_EX *pnetwork;
+
+	_rtw_memset(pmp_priv, 0, sizeof(struct mp_priv));
+
+	pmp_priv->mode = MP_OFF;
+
+	pmp_priv->channel = 1;
+	pmp_priv->bandwidth = CHANNEL_WIDTH_20;
+	pmp_priv->prime_channel_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
+	pmp_priv->rateidx = RATE_1M;
+	pmp_priv->txpoweridx = 0x2A;
+
+	pmp_priv->antenna_tx = ANTENNA_A;
+	pmp_priv->antenna_rx = ANTENNA_AB;
+
+	pmp_priv->check_mp_pkt = 0;
+
+	pmp_priv->tx_pktcount = 0;
+
+	pmp_priv->rx_bssidpktcount = 0;
+	pmp_priv->rx_pktcount = 0;
+	pmp_priv->rx_crcerrpktcount = 0;
+
+	pmp_priv->network_macaddr[0] = 0x00;
+	pmp_priv->network_macaddr[1] = 0xE0;
+	pmp_priv->network_macaddr[2] = 0x4C;
+	pmp_priv->network_macaddr[3] = 0x87;
+	pmp_priv->network_macaddr[4] = 0x66;
+	pmp_priv->network_macaddr[5] = 0x55;
+
+	pmp_priv->bSetRxBssid = _FALSE;
+	pmp_priv->bRTWSmbCfg = _FALSE;
+	pmp_priv->bloopback = _FALSE;
+
+	pmp_priv->bloadefusemap = _FALSE;
+	pmp_priv->brx_filter_beacon = _FALSE;
+
+	pnetwork = &pmp_priv->mp_network.network;
+	_rtw_memcpy(pnetwork->MacAddress, pmp_priv->network_macaddr, ETH_ALEN);
+
+	pnetwork->Ssid.SsidLength = 8;
+	_rtw_memcpy(pnetwork->Ssid.Ssid, "mp_871x", pnetwork->Ssid.SsidLength);
+
+	pmp_priv->tx.payload = 2;
+#ifdef CONFIG_80211N_HT
+	pmp_priv->tx.attrib.ht_en = 1;
+#endif
+
+	pmp_priv->mpt_ctx.mpt_rate_index = 1;
+
+}
+
+#ifdef PLATFORM_WINDOWS
+#if 0
+void mp_wi_callback(
+	IN NDIS_WORK_ITEM	*pwk_item,
+	IN PVOID			cntx
+)
+{
+	_adapter *padapter = (_adapter *)cntx;
+	struct mp_priv *pmppriv = &padapter->mppriv;
+	struct mp_wi_cntx	*pmp_wi_cntx = &pmppriv->wi_cntx;
+
+	/*  Execute specified action. */
+	if (pmp_wi_cntx->curractfunc != NULL) {
+		LARGE_INTEGER	cur_time;
+		ULONGLONG start_time, end_time;
+		NdisGetCurrentSystemTime(&cur_time);	/*  driver version */
+		start_time = cur_time.QuadPart / 10; /*  The return value is in microsecond */
+
+		pmp_wi_cntx->curractfunc(padapter);
+
+		NdisGetCurrentSystemTime(&cur_time);	/*  driver version */
+		end_time = cur_time.QuadPart / 10; /*  The return value is in microsecond */
+
+	}
+
+	NdisAcquireSpinLock(&(pmp_wi_cntx->mp_wi_lock));
+	pmp_wi_cntx->bmp_wi_progress = _FALSE;
+	NdisReleaseSpinLock(&(pmp_wi_cntx->mp_wi_lock));
+
+	if (pmp_wi_cntx->bmpdrv_unload)
+		NdisSetEvent(&(pmp_wi_cntx->mp_wi_evt));
+
+}
+#endif
+
+static int init_mp_priv_by_os(struct mp_priv *pmp_priv)
+{
+	struct mp_wi_cntx *pmp_wi_cntx;
+
+	if (pmp_priv == NULL)
+		return _FAIL;
+
+	pmp_priv->rx_testcnt = 0;
+	pmp_priv->rx_testcnt1 = 0;
+	pmp_priv->rx_testcnt2 = 0;
+
+	pmp_priv->tx_testcnt = 0;
+	pmp_priv->tx_testcnt1 = 0;
+
+	pmp_wi_cntx = &pmp_priv->wi_cntx
+		      pmp_wi_cntx->bmpdrv_unload = _FALSE;
+	pmp_wi_cntx->bmp_wi_progress = _FALSE;
+	pmp_wi_cntx->curractfunc = NULL;
+
+	return _SUCCESS;
+}
+#endif
+
+#ifdef PLATFORM_LINUX
+#if 0
+static int init_mp_priv_by_os(struct mp_priv *pmp_priv)
+{
+	int i, res;
+	struct mp_xmit_frame *pmp_xmitframe;
+
+	if (pmp_priv == NULL)
+		return _FAIL;
+
+	_rtw_init_queue(&pmp_priv->free_mp_xmitqueue);
+
+	pmp_priv->pallocated_mp_xmitframe_buf = NULL;
+	pmp_priv->pallocated_mp_xmitframe_buf = rtw_zmalloc(NR_MP_XMITFRAME * sizeof(struct mp_xmit_frame) + 4);
+	if (pmp_priv->pallocated_mp_xmitframe_buf == NULL) {
+		res = _FAIL;
+		goto _exit_init_mp_priv;
+	}
+
+	pmp_priv->pmp_xmtframe_buf = pmp_priv->pallocated_mp_xmitframe_buf + 4 - ((SIZE_PTR)(pmp_priv->pallocated_mp_xmitframe_buf) & 3);
+
+	pmp_xmitframe = (struct mp_xmit_frame *)pmp_priv->pmp_xmtframe_buf;
+
+	for (i = 0; i < NR_MP_XMITFRAME; i++) {
+		_rtw_init_listhead(&pmp_xmitframe->list);
+		rtw_list_insert_tail(&pmp_xmitframe->list, &pmp_priv->free_mp_xmitqueue.queue);
+
+		pmp_xmitframe->pkt = NULL;
+		pmp_xmitframe->frame_tag = MP_FRAMETAG;
+		pmp_xmitframe->padapter = pmp_priv->papdater;
+
+		pmp_xmitframe++;
+	}
+
+	pmp_priv->free_mp_xmitframe_cnt = NR_MP_XMITFRAME;
+
+	res = _SUCCESS;
+
+_exit_init_mp_priv:
+
+	return res;
+}
+#endif
+#endif
+
+static void mp_init_xmit_attrib(struct mp_tx *pmptx, PADAPTER padapter)
+{
+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(padapter);
+
+	struct pkt_attrib *pattrib;
+
+	/* init xmitframe attribute */
+	pattrib = &pmptx->attrib;
+	_rtw_memset(pattrib, 0, sizeof(struct pkt_attrib));
+	_rtw_memset(pmptx->desc, 0, TXDESC_SIZE);
+
+	pattrib->ether_type = 0x8712;
+#if 0
+	_rtw_memcpy(pattrib->src, adapter_mac_addr(padapter), ETH_ALEN);
+	_rtw_memcpy(pattrib->ta, pattrib->src, ETH_ALEN);
+#endif
+	_rtw_memset(pattrib->dst, 0xFF, ETH_ALEN);
+
+	/*	pattrib->dhcp_pkt = 0;
+	 *	pattrib->pktlen = 0; */
+	pattrib->ack_policy = 0;
+	/*	pattrib->pkt_hdrlen = ETH_HLEN; */
+	pattrib->hdrlen = WLAN_HDR_A3_LEN;
+	pattrib->subtype = WIFI_DATA;
+	pattrib->priority = 0;
+	pattrib->qsel = pattrib->priority;
+	/*	do_queue_select(padapter, pattrib); */
+	pattrib->nr_frags = 1;
+	pattrib->encrypt = 0;
+	pattrib->bswenc = _FALSE;
+	pattrib->qos_en = _FALSE;
+
+	pattrib->pktlen = 1500;
+
+	if (pHalData->rf_type == RF_2T2R)
+		pattrib->raid = RATEID_IDX_BGN_40M_2SS;
+	else
+		pattrib->raid = RATEID_IDX_BGN_40M_1SS;
+
+#ifdef CONFIG_80211AC_VHT
+	if (pHalData->rf_type == RF_1T1R)
+		pattrib->raid = RATEID_IDX_VHT_1SS;
+	else if (pHalData->rf_type == RF_2T2R || pHalData->rf_type == RF_2T4R)
+		pattrib->raid = RATEID_IDX_VHT_2SS;
+	else if (pHalData->rf_type == RF_3T3R)
+		pattrib->raid = RATEID_IDX_VHT_3SS;
+	else
+		pattrib->raid = RATEID_IDX_BGN_40M_1SS;
+#endif
+}
+
+s32 init_mp_priv(PADAPTER padapter)
+{
+	struct mp_priv *pmppriv = &padapter->mppriv;
+	PHAL_DATA_TYPE pHalData;
+
+	pHalData = GET_HAL_DATA(padapter);
+
+	_init_mp_priv_(pmppriv);
+	pmppriv->papdater = padapter;
+	pmppriv->mp_dm = 0;
+	pmppriv->tx.stop = 1;
+	pmppriv->bSetTxPower = 0;		/*for  manually set tx power*/
+	pmppriv->bTxBufCkFail = _FALSE;
+	pmppriv->pktInterval = 0;
+	pmppriv->pktLength = 1000;
+
+	mp_init_xmit_attrib(&pmppriv->tx, padapter);
+
+	switch (padapter->registrypriv.rf_config) {
+	case RF_1T1R:
+		pmppriv->antenna_tx = ANTENNA_A;
+		pmppriv->antenna_rx = ANTENNA_A;
+		break;
+	case RF_1T2R:
+	default:
+		pmppriv->antenna_tx = ANTENNA_A;
+		pmppriv->antenna_rx = ANTENNA_AB;
+		break;
+	case RF_2T2R:
+		pmppriv->antenna_tx = ANTENNA_AB;
+		pmppriv->antenna_rx = ANTENNA_AB;
+		break;
+	case RF_2T4R:
+		pmppriv->antenna_tx = ANTENNA_BC;
+		pmppriv->antenna_rx = ANTENNA_ABCD;
+		break;
+	}
+
+	pHalData->AntennaRxPath = pmppriv->antenna_rx;
+	pHalData->antenna_tx_path = pmppriv->antenna_tx;
+
+	return _SUCCESS;
+}
+
+void free_mp_priv(struct mp_priv *pmp_priv)
+{
+	if (pmp_priv->pallocated_mp_xmitframe_buf) {
+		rtw_mfree(pmp_priv->pallocated_mp_xmitframe_buf, 0);
+		pmp_priv->pallocated_mp_xmitframe_buf = NULL;
+	}
+	pmp_priv->pmp_xmtframe_buf = NULL;
+}
+
+#if 0
+static VOID PHY_IQCalibrate_default(
+	IN	PADAPTER	pAdapter,
+	IN	BOOLEAN	bReCovery
+)
+{
+	RTW_INFO("%s\n", __func__);
+}
+
+static VOID PHY_LCCalibrate_default(
+	IN	PADAPTER	pAdapter
+)
+{
+	RTW_INFO("%s\n", __func__);
+}
+
+static VOID PHY_SetRFPathSwitch_default(
+	IN	PADAPTER	pAdapter,
+	IN	BOOLEAN		bMain
+)
+{
+	RTW_INFO("%s\n", __func__);
+}
+#endif
+
+void mpt_InitHWConfig(PADAPTER Adapter)
+{
+	PHAL_DATA_TYPE hal;
+
+	hal = GET_HAL_DATA(Adapter);
+
+	if (IS_HARDWARE_TYPE_8723B(Adapter)) {
+		/* TODO: <20130114, Kordan> The following setting is only for DPDT and Fixed board type. */
+		/* TODO:  A better solution is configure it according EFUSE during the run-time. */
+
+		phy_set_mac_reg(Adapter, 0x64, BIT20, 0x0);		/* 0x66[4]=0		 */
+		phy_set_mac_reg(Adapter, 0x64, BIT24, 0x0);		/* 0x66[8]=0 */
+		phy_set_mac_reg(Adapter, 0x40, BIT4, 0x0);		/* 0x40[4]=0		 */
+		phy_set_mac_reg(Adapter, 0x40, BIT3, 0x1);		/* 0x40[3]=1		 */
+		phy_set_mac_reg(Adapter, 0x4C, BIT24, 0x1);		/* 0x4C[24:23]=10 */
+		phy_set_mac_reg(Adapter, 0x4C, BIT23, 0x0);		/* 0x4C[24:23]=10 */
+		phy_set_bb_reg(Adapter, 0x944, BIT1 | BIT0, 0x3);	/* 0x944[1:0]=11	 */
+		phy_set_bb_reg(Adapter, 0x930, bMaskByte0, 0x77);/* 0x930[7:0]=77	  */
+		phy_set_mac_reg(Adapter, 0x38, BIT11, 0x1);/* 0x38[11]=1 */
+
+		/* TODO: <20130206, Kordan> The default setting is wrong, hard-coded here. */
+		phy_set_mac_reg(Adapter, 0x778, 0x3, 0x3);					/* Turn off hardware PTA control (Asked by Scott) */
+		phy_set_mac_reg(Adapter, 0x64, bMaskDWord, 0x36000000);/* Fix BT S0/S1 */
+		phy_set_mac_reg(Adapter, 0x948, bMaskDWord, 0x0);		/* Fix BT can't Tx */
+
+		/* <20130522, Kordan> Turn off equalizer to improve Rx sensitivity. (Asked by EEChou) */
+		phy_set_bb_reg(Adapter, 0xA00, BIT8, 0x0);			/*0xA01[0] = 0*/
+	} else if (IS_HARDWARE_TYPE_8821(Adapter)) {
+		/* <20131121, VincentL> Add for 8821AU DPDT setting and fix switching antenna issue (Asked by Rock)
+		<20131122, VincentL> Enable for all 8821A/8811AU  (Asked by Alex)*/
+		phy_set_mac_reg(Adapter, 0x4C, BIT23, 0x0);		/*0x4C[23:22]=01*/
+		phy_set_mac_reg(Adapter, 0x4C, BIT22, 0x1);		/*0x4C[23:22]=01*/
+	} else if (IS_HARDWARE_TYPE_8188ES(Adapter))
+		phy_set_mac_reg(Adapter, 0x4C , BIT23, 0);		/*select DPDT_P and DPDT_N as output pin*/
+#ifdef CONFIG_RTL8814A
+	else if (IS_HARDWARE_TYPE_8814A(Adapter))
+		PlatformEFIOWrite2Byte(Adapter, REG_RXFLTMAP1_8814A, 0x2000);
+#endif
+
+#ifdef CONFIG_RTL8812A
+	else if (IS_HARDWARE_TYPE_8812(Adapter)) {
+		rtw_write32(Adapter, 0x520, rtw_read32(Adapter, 0x520) | 0x8000);
+		rtw_write32(Adapter, 0x524, rtw_read32(Adapter, 0x524) & (~0x800));
+	}
+#endif
+
+
+#ifdef CONFIG_RTL8822B
+	else if (IS_HARDWARE_TYPE_8822B(Adapter)) {
+		u32 tmp_reg = 0;
+
+		PlatformEFIOWrite2Byte(Adapter, REG_RXFLTMAP1_8822B, 0x2000);
+		/* fixed wifi can't 2.4g tx suggest by Szuyitasi 20160504 */
+		phy_set_bb_reg(Adapter, 0x70, bMaskByte3, 0x0e);
+		RTW_INFO(" 0x73 = 0x%x\n", phy_query_bb_reg(Adapter, 0x70, bMaskByte3));
+		phy_set_bb_reg(Adapter, 0x1704, bMaskDWord, 0x0000ff00);
+		RTW_INFO(" 0x1704 = 0x%x\n", phy_query_bb_reg(Adapter, 0x1704, bMaskDWord));
+		phy_set_bb_reg(Adapter, 0x1700, bMaskDWord, 0xc00f0038);
+		RTW_INFO(" 0x1700 = 0x%x\n", phy_query_bb_reg(Adapter, 0x1700, bMaskDWord));
+	}
+#endif /* CONFIG_RTL8822B */
+#ifdef CONFIG_RTL8821C
+	else if (IS_HARDWARE_TYPE_8821C(Adapter))
+		PlatformEFIOWrite2Byte(Adapter, REG_RXFLTMAP1_8821C, 0x2000);
+#endif /* CONFIG_RTL8821C */
+#if defined(CONFIG_RTL8188F) || defined(CONFIG_RTL8188GTV)
+	else if (IS_HARDWARE_TYPE_8188F(Adapter) || IS_HARDWARE_TYPE_8188GTV(Adapter)) {
+		if (IS_A_CUT(hal->version_id) || IS_B_CUT(hal->version_id)) {
+			RTW_INFO("%s() Active large power detection\n", __func__);
+			phy_active_large_power_detection_8188f(&(GET_HAL_DATA(Adapter)->odmpriv));
+		}
+	}
+#endif
+}
+
+static void PHY_IQCalibrate(PADAPTER padapter, u8 bReCovery)
+{
+	halrf_iqk_trigger(&(GET_HAL_DATA(padapter)->odmpriv), bReCovery);
+}
+
+static void PHY_LCCalibrate(PADAPTER padapter)
+{
+	halrf_lck_trigger(&(GET_HAL_DATA(padapter)->odmpriv));
+}
+
+static u8 PHY_QueryRFPathSwitch(PADAPTER padapter)
+{
+	u8 bmain = 0;
+/*
+	if (IS_HARDWARE_TYPE_8723B(padapter)) {
+#ifdef CONFIG_RTL8723B
+		bmain = PHY_QueryRFPathSwitch_8723B(padapter);
+#endif
+	} else if (IS_HARDWARE_TYPE_8188E(padapter)) {
+#ifdef CONFIG_RTL8188E
+		bmain = PHY_QueryRFPathSwitch_8188E(padapter);
+#endif
+	} else if (IS_HARDWARE_TYPE_8814A(padapter)) {
+#ifdef CONFIG_RTL8814A
+		bmain = PHY_QueryRFPathSwitch_8814A(padapter);
+#endif
+	} else if (IS_HARDWARE_TYPE_8812(padapter) || IS_HARDWARE_TYPE_8821(padapter)) {
+#if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A)
+		bmain = PHY_QueryRFPathSwitch_8812A(padapter);
+#endif
+	} else if (IS_HARDWARE_TYPE_8192E(padapter)) {
+#ifdef CONFIG_RTL8192E
+		bmain = PHY_QueryRFPathSwitch_8192E(padapter);
+#endif
+	} else if (IS_HARDWARE_TYPE_8703B(padapter)) {
+#ifdef CONFIG_RTL8703B
+		bmain = PHY_QueryRFPathSwitch_8703B(padapter);
+#endif
+	} else if (IS_HARDWARE_TYPE_8188F(padapter)) {
+#ifdef CONFIG_RTL8188F
+		bmain = PHY_QueryRFPathSwitch_8188F(padapter);
+#endif
+	} else if (IS_HARDWARE_TYPE_8188GTV(padapter)) {
+#ifdef CONFIG_RTL8188GTV
+		bmain = PHY_QueryRFPathSwitch_8188GTV(padapter);
+#endif
+	} else if (IS_HARDWARE_TYPE_8822B(padapter)) {
+#ifdef CONFIG_RTL8822B
+		bmain = PHY_QueryRFPathSwitch_8822B(padapter);
+#endif
+	} else if (IS_HARDWARE_TYPE_8723D(padapter)) {
+#ifdef CONFIG_RTL8723D
+		bmain = PHY_QueryRFPathSwitch_8723D(padapter);
+#endif
+	} else
+*/
+
+	if (IS_HARDWARE_TYPE_8821C(padapter)) {
+#ifdef CONFIG_RTL8821C
+		bmain = phy_query_rf_path_switch_8821c(padapter);
+#endif
+	}
+
+	return bmain;
+}
+
+static void  PHY_SetRFPathSwitch(PADAPTER padapter , BOOLEAN bMain) {
+
+	PHAL_DATA_TYPE hal = GET_HAL_DATA(padapter);
+	struct dm_struct *phydm = &hal->odmpriv;
+
+	if (IS_HARDWARE_TYPE_8723B(padapter)) {
+#ifdef CONFIG_RTL8723B
+		phy_set_rf_path_switch_8723b(phydm, bMain);
+#endif
+	} else if (IS_HARDWARE_TYPE_8188E(padapter)) {
+#ifdef CONFIG_RTL8188E
+		phy_set_rf_path_switch_8188e(phydm, bMain);
+#endif
+	} else if (IS_HARDWARE_TYPE_8814A(padapter)) {
+#ifdef CONFIG_RTL8814A
+		phy_set_rf_path_switch_8814a(phydm, bMain);
+#endif
+	} else if (IS_HARDWARE_TYPE_8812(padapter) || IS_HARDWARE_TYPE_8821(padapter)) {
+#if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A)
+		phy_set_rf_path_switch_8812a(phydm, bMain);
+#endif
+	} else if (IS_HARDWARE_TYPE_8192E(padapter)) {
+#ifdef CONFIG_RTL8192E
+		phy_set_rf_path_switch_8192e(phydm, bMain);
+#endif
+	} else if (IS_HARDWARE_TYPE_8703B(padapter)) {
+#ifdef CONFIG_RTL8703B
+		phy_set_rf_path_switch_8703b(phydm, bMain);
+#endif
+	} else if (IS_HARDWARE_TYPE_8188F(padapter) || IS_HARDWARE_TYPE_8188GTV(padapter)) {
+#if defined(CONFIG_RTL8188F) || defined(CONFIG_RTL8188GTV)
+		phy_set_rf_path_switch_8188f(phydm, bMain);
+#endif
+	} else if (IS_HARDWARE_TYPE_8192F(padapter)) {
+#ifdef CONFIG_RTL8192F
+		phy_set_rf_path_switch_8192f(padapter, bMain);
+#endif
+	} else if (IS_HARDWARE_TYPE_8822B(padapter)) {
+#ifdef CONFIG_RTL8822B
+		phy_set_rf_path_switch_8822b(phydm, bMain);
+#endif
+	} else if (IS_HARDWARE_TYPE_8723D(padapter)) {
+#ifdef CONFIG_RTL8723D
+		phy_set_rf_path_switch_8723d(phydm, bMain);
+#endif
+	} else if (IS_HARDWARE_TYPE_8821C(padapter)) {
+#ifdef CONFIG_RTL8821C
+		phy_set_rf_path_switch_8821c(phydm, bMain);
+#endif
+	}
+}
+
+
+static void phy_switch_rf_path_set(PADAPTER padapter , u8 *prf_set_State) {
+#ifdef CONFIG_RTL8821C
+	HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
+	struct dm_struct *p_dm = &pHalData->odmpriv;
+
+	if (IS_HARDWARE_TYPE_8821C(padapter)) {
+		config_phydm_set_ant_path(p_dm, *prf_set_State, p_dm->current_ant_num_8821c);
+		/* Do IQK when switching to BTG/WLG, requested by RF Binson */
+		if (*prf_set_State == SWITCH_TO_BTG || *prf_set_State == SWITCH_TO_WLG)
+			PHY_IQCalibrate(padapter, FALSE);
+	}
+#endif
+
+}
+
+
+#ifdef CONFIG_ANTENNA_DIVERSITY
+u8 rtw_mp_set_antdiv(PADAPTER padapter, BOOLEAN bMain)
+{
+	HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
+	u8 cur_ant, change_ant;
+
+	if (!pHalData->AntDivCfg)
+		return _FALSE;
+	/*rtw_hal_get_odm_var(padapter, HAL_ODM_ANTDIV_SELECT, &cur_ant, NULL);*/
+	change_ant = (bMain == MAIN_ANT) ? MAIN_ANT : AUX_ANT;
+
+	RTW_INFO("%s: config %s\n", __func__, (bMain == MAIN_ANT) ? "MAIN_ANT" : "AUX_ANT");
+	rtw_antenna_select_cmd(padapter, change_ant, _FALSE);
+
+	return _TRUE;
+}
+#endif
+
+s32
+MPT_InitializeAdapter(
+	IN	PADAPTER			pAdapter,
+	IN	u8				Channel
+)
+{
+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(pAdapter);
+	s32		rtStatus = _SUCCESS;
+	PMPT_CONTEXT	pMptCtx = &pAdapter->mppriv.mpt_ctx;
+	u32		ledsetting;
+
+	pMptCtx->bMptDrvUnload = _FALSE;
+	pMptCtx->bMassProdTest = _FALSE;
+	pMptCtx->bMptIndexEven = _TRUE;	/* default gain index is -6.0db */
+	pMptCtx->h2cReqNum = 0x0;
+	/* init for BT MP */
+#if defined(CONFIG_RTL8723B)
+	pMptCtx->bMPh2c_timeout = _FALSE;
+	pMptCtx->MptH2cRspEvent = _FALSE;
+	pMptCtx->MptBtC2hEvent = _FALSE;
+	_rtw_init_sema(&pMptCtx->MPh2c_Sema, 0);
+	rtw_init_timer(&pMptCtx->MPh2c_timeout_timer, pAdapter, MPh2c_timeout_handle, pAdapter);
+#endif
+
+	mpt_InitHWConfig(pAdapter);
+
+#ifdef CONFIG_RTL8723B
+	rtl8723b_InitAntenna_Selection(pAdapter);
+	if (IS_HARDWARE_TYPE_8723B(pAdapter)) {
+
+		/* <20130522, Kordan> Turn off equalizer to improve Rx sensitivity. (Asked by EEChou)*/
+		phy_set_bb_reg(pAdapter, 0xA00, BIT8, 0x0);
+		PHY_SetRFPathSwitch(pAdapter, 1/*pHalData->bDefaultAntenna*/); /*default use Main*/
+
+		if (pHalData->PackageType == PACKAGE_DEFAULT)
+			phy_set_rf_reg(pAdapter, RF_PATH_A, 0x51, bRFRegOffsetMask, 0x6B04E);
+		else
+			phy_set_rf_reg(pAdapter, RF_PATH_A, 0x51, bRFRegOffsetMask, 0x6F10E);
+
+	}
+	/*set ant to wifi side in mp mode*/
+	rtw_write16(pAdapter, 0x870, 0x300);
+	rtw_write16(pAdapter, 0x860, 0x110);
+#endif
+
+	pMptCtx->bMptWorkItemInProgress = _FALSE;
+	pMptCtx->CurrMptAct = NULL;
+	pMptCtx->mpt_rf_path = RF_PATH_A;
+	/* ------------------------------------------------------------------------- */
+	/* Don't accept any packets */
+	rtw_write32(pAdapter, REG_RCR, 0);
+
+	/* ledsetting = rtw_read32(pAdapter, REG_LEDCFG0); */
+	/* rtw_write32(pAdapter, REG_LEDCFG0, ledsetting & ~LED0DIS); */
+
+	/* rtw_write32(pAdapter, REG_LEDCFG0, 0x08080); */
+	ledsetting = rtw_read32(pAdapter, REG_LEDCFG0);
+
+
+	PHY_LCCalibrate(pAdapter);
+	PHY_IQCalibrate(pAdapter, _FALSE);
+	/* dm_check_txpowertracking(&pHalData->odmpriv);	*/ /* trigger thermal meter */
+
+	PHY_SetRFPathSwitch(pAdapter, 1/*pHalData->bDefaultAntenna*/); /* default use Main */
+
+	pMptCtx->backup0xc50 = (u1Byte)phy_query_bb_reg(pAdapter, rOFDM0_XAAGCCore1, bMaskByte0);
+	pMptCtx->backup0xc58 = (u1Byte)phy_query_bb_reg(pAdapter, rOFDM0_XBAGCCore1, bMaskByte0);
+	pMptCtx->backup0xc30 = (u1Byte)phy_query_bb_reg(pAdapter, rOFDM0_RxDetector1, bMaskByte0);
+	pMptCtx->backup0x52_RF_A = (u1Byte)phy_query_rf_reg(pAdapter, RF_PATH_A, RF_0x52, 0x000F0);
+	pMptCtx->backup0x52_RF_B = (u1Byte)phy_query_rf_reg(pAdapter, RF_PATH_B, RF_0x52, 0x000F0);
+#ifdef CONFIG_RTL8188E
+	rtw_write32(pAdapter, REG_MACID_NO_LINK_0, 0x0);
+	rtw_write32(pAdapter, REG_MACID_NO_LINK_1, 0x0);
+#endif
+#ifdef CONFIG_RTL8814A
+	if (IS_HARDWARE_TYPE_8814A(pAdapter)) {
+		pHalData->BackUp_IG_REG_4_Chnl_Section[0] = (u1Byte)phy_query_bb_reg(pAdapter, rA_IGI_Jaguar, bMaskByte0);
+		pHalData->BackUp_IG_REG_4_Chnl_Section[1] = (u1Byte)phy_query_bb_reg(pAdapter, rB_IGI_Jaguar, bMaskByte0);
+		pHalData->BackUp_IG_REG_4_Chnl_Section[2] = (u1Byte)phy_query_bb_reg(pAdapter, rC_IGI_Jaguar2, bMaskByte0);
+		pHalData->BackUp_IG_REG_4_Chnl_Section[3] = (u1Byte)phy_query_bb_reg(pAdapter, rD_IGI_Jaguar2, bMaskByte0);
+	}
+#endif
+	return	rtStatus;
+}
+
+/*-----------------------------------------------------------------------------
+ * Function:	MPT_DeInitAdapter()
+ *
+ * Overview:	Extra DeInitialization for Mass Production Test.
+ *
+ * Input:		PADAPTER	pAdapter
+ *
+ * Output:		NONE
+ *
+ * Return:		NONE
+ *
+ * Revised History:
+ *	When		Who		Remark
+ *	05/08/2007	MHC		Create Version 0.
+ *	05/18/2007	MHC		Add normal driver MPHalt code.
+ *
+ *---------------------------------------------------------------------------*/
+VOID
+MPT_DeInitAdapter(
+	IN	PADAPTER	pAdapter
+)
+{
+	PMPT_CONTEXT		pMptCtx = &pAdapter->mppriv.mpt_ctx;
+
+	pMptCtx->bMptDrvUnload = _TRUE;
+#if defined(CONFIG_RTL8723B)
+	_rtw_free_sema(&(pMptCtx->MPh2c_Sema));
+	_cancel_timer_ex(&pMptCtx->MPh2c_timeout_timer);
+#endif
+#if	defined(CONFIG_RTL8723B)
+	phy_set_bb_reg(pAdapter, 0xA01, BIT0, 1); /* /suggestion  by jerry for MP Rx. */
+#endif
+#if 0 /* for Windows */
+	PlatformFreeWorkItem(&(pMptCtx->MptWorkItem));
+
+	while (pMptCtx->bMptWorkItemInProgress) {
+		if (NdisWaitEvent(&(pMptCtx->MptWorkItemEvent), 50))
+			break;
+	}
+	NdisFreeSpinLock(&(pMptCtx->MptWorkItemSpinLock));
+#endif
+}
+
+static u8 mpt_ProStartTest(PADAPTER padapter)
+{
+	PMPT_CONTEXT pMptCtx = &padapter->mppriv.mpt_ctx;
+
+	pMptCtx->bMassProdTest = _TRUE;
+	pMptCtx->is_start_cont_tx = _FALSE;
+	pMptCtx->bCckContTx = _FALSE;
+	pMptCtx->bOfdmContTx = _FALSE;
+	pMptCtx->bSingleCarrier = _FALSE;
+	pMptCtx->is_carrier_suppression = _FALSE;
+	pMptCtx->is_single_tone = _FALSE;
+	pMptCtx->HWTxmode = PACKETS_TX;
+
+	return _SUCCESS;
+}
+
+/*
+ * General use
+ */
+s32 SetPowerTracking(PADAPTER padapter, u8 enable)
+{
+
+	hal_mpt_SetPowerTracking(padapter, enable);
+	return 0;
+}
+
+void GetPowerTracking(PADAPTER padapter, u8 *enable)
+{
+	hal_mpt_GetPowerTracking(padapter, enable);
+}
+
+void rtw_mp_trigger_iqk(PADAPTER padapter)
+{
+	PHY_IQCalibrate(padapter, _FALSE);
+}
+
+void rtw_mp_trigger_lck(PADAPTER padapter)
+{
+	PHY_LCCalibrate(padapter);
+}
+
+static void init_mp_data(PADAPTER padapter)
+{
+	u8 v8;
+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(padapter);
+	struct dm_struct		*pDM_Odm = &pHalData->odmpriv;
+
+	/*disable BCN*/
+	v8 = rtw_read8(padapter, REG_BCN_CTRL);
+	v8 &= ~EN_BCN_FUNCTION;
+	rtw_write8(padapter, REG_BCN_CTRL, v8);
+
+	pDM_Odm->rf_calibrate_info.txpowertrack_control = _FALSE;
+}
+
+void MPT_PwrCtlDM(PADAPTER padapter, u32 bstart)
+{
+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(padapter);
+	struct dm_struct		*pDM_Odm = &pHalData->odmpriv;
+	u32	rf_ability;
+
+	if (bstart == 1) {
+		RTW_INFO("in MPT_PwrCtlDM start\n");
+
+		rf_ability = ((u32)halrf_cmn_info_get(pDM_Odm, HALRF_CMNINFO_ABILITY)) | HAL_RF_TX_PWR_TRACK;
+		halrf_cmn_info_set(pDM_Odm, HALRF_CMNINFO_ABILITY, rf_ability);
+
+		pDM_Odm->rf_calibrate_info.txpowertrack_control = _TRUE;
+		padapter->mppriv.mp_dm = 1;
+
+	} else {
+		RTW_INFO("in MPT_PwrCtlDM stop\n");
+		rf_ability = ((u32)halrf_cmn_info_get(pDM_Odm, HALRF_CMNINFO_ABILITY)) & ~HAL_RF_TX_PWR_TRACK;
+		halrf_cmn_info_set(pDM_Odm, HALRF_CMNINFO_ABILITY, rf_ability);
+		pDM_Odm->rf_calibrate_info.txpowertrack_control = _FALSE;
+		padapter->mppriv.mp_dm = 0;
+		{
+			struct txpwrtrack_cfg c;
+			u1Byte	chnl = 0 ;
+			_rtw_memset(&c, 0, sizeof(struct txpwrtrack_cfg));
+			configure_txpower_track(pDM_Odm, &c);
+			odm_clear_txpowertracking_state(pDM_Odm);
+			if (*c.odm_tx_pwr_track_set_pwr) {
+				if (pDM_Odm->support_ic_type == ODM_RTL8188F)
+					(*c.odm_tx_pwr_track_set_pwr)(pDM_Odm, MIX_MODE, RF_PATH_A, chnl);
+				else if (pDM_Odm->support_ic_type == ODM_RTL8723D) {
+					(*c.odm_tx_pwr_track_set_pwr)(pDM_Odm, BBSWING, RF_PATH_A, chnl);
+					SetTxPower(padapter);
+				} else if (pDM_Odm->support_ic_type == ODM_RTL8192F) {
+					(*c.odm_tx_pwr_track_set_pwr)(pDM_Odm, MIX_MODE, RF_PATH_A, chnl);
+					(*c.odm_tx_pwr_track_set_pwr)(pDM_Odm, MIX_MODE, RF_PATH_B, chnl);
+				} else {
+					(*c.odm_tx_pwr_track_set_pwr)(pDM_Odm, BBSWING, RF_PATH_A, chnl);
+					(*c.odm_tx_pwr_track_set_pwr)(pDM_Odm, BBSWING, RF_PATH_B, chnl);
+				}
+			}
+		}
+	}
+
+}
+
+
+u32 mp_join(PADAPTER padapter, u8 mode)
+{
+	WLAN_BSSID_EX bssid;
+	struct sta_info *psta;
+	u32 length;
+	_irqL irqL;
+	s32 res = _SUCCESS;
+
+	struct mp_priv *pmppriv = &padapter->mppriv;
+	struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
+	struct wlan_network *tgt_network = &pmlmepriv->cur_network;
+	struct mlme_ext_priv	*pmlmeext = &padapter->mlmeextpriv;
+	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
+	WLAN_BSSID_EX		*pnetwork = (WLAN_BSSID_EX *)(&(pmlmeinfo->network));
+
+	/* 1. initialize a new WLAN_BSSID_EX */
+	_rtw_memset(&bssid, 0, sizeof(WLAN_BSSID_EX));
+	RTW_INFO("%s ,pmppriv->network_macaddr=%x %x %x %x %x %x\n", __func__,
+		pmppriv->network_macaddr[0], pmppriv->network_macaddr[1], pmppriv->network_macaddr[2], pmppriv->network_macaddr[3], pmppriv->network_macaddr[4],
+		 pmppriv->network_macaddr[5]);
+	_rtw_memcpy(bssid.MacAddress, pmppriv->network_macaddr, ETH_ALEN);
+
+	if (mode == WIFI_FW_ADHOC_STATE) {
+		bssid.Ssid.SsidLength = strlen("mp_pseudo_adhoc");
+		_rtw_memcpy(bssid.Ssid.Ssid, (u8 *)"mp_pseudo_adhoc", bssid.Ssid.SsidLength);
+		bssid.InfrastructureMode = Ndis802_11IBSS;
+		bssid.NetworkTypeInUse = Ndis802_11DS;
+		bssid.IELength = 0;
+		bssid.Configuration.DSConfig = pmppriv->channel;
+
+	} else if (mode == WIFI_FW_STATION_STATE) {
+		bssid.Ssid.SsidLength = strlen("mp_pseudo_STATION");
+		_rtw_memcpy(bssid.Ssid.Ssid, (u8 *)"mp_pseudo_STATION", bssid.Ssid.SsidLength);
+		bssid.InfrastructureMode = Ndis802_11Infrastructure;
+		bssid.NetworkTypeInUse = Ndis802_11DS;
+		bssid.IELength = 0;
+	}
+
+	length = get_WLAN_BSSID_EX_sz(&bssid);
+	if (length % 4)
+		bssid.Length = ((length >> 2) + 1) << 2; /* round up to multiple of 4 bytes. */
+	else
+		bssid.Length = length;
+
+	_enter_critical_bh(&pmlmepriv->lock, &irqL);
+
+	if (check_fwstate(pmlmepriv, WIFI_MP_STATE) == _TRUE)
+		goto end_of_mp_start_test;
+
+	/* init mp_start_test status */
+	if (check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE) {
+		rtw_disassoc_cmd(padapter, 500, 0);
+		rtw_indicate_disconnect(padapter, 0, _FALSE);
+		rtw_free_assoc_resources_cmd(padapter, _TRUE, 0);
+	}
+	pmppriv->prev_fw_state = get_fwstate(pmlmepriv);
+	/*pmlmepriv->fw_state = WIFI_MP_STATE;*/
+	init_fwstate(pmlmepriv, WIFI_MP_STATE);
+
+	set_fwstate(pmlmepriv, _FW_UNDER_LINKING);
+
+	/* 3 2. create a new psta for mp driver */
+	/* clear psta in the cur_network, if any */
+	psta = rtw_get_stainfo(&padapter->stapriv, tgt_network->network.MacAddress);
+	if (psta)
+		rtw_free_stainfo(padapter, psta);
+
+	psta = rtw_alloc_stainfo(&padapter->stapriv, bssid.MacAddress);
+	if (psta == NULL) {
+		/*pmlmepriv->fw_state = pmppriv->prev_fw_state;*/
+		init_fwstate(pmlmepriv, pmppriv->prev_fw_state);
+		res = _FAIL;
+		goto end_of_mp_start_test;
+	}
+	if (mode == WIFI_FW_ADHOC_STATE)
+	set_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE);
+	else
+		set_fwstate(pmlmepriv, WIFI_STATION_STATE);
+	/* 3 3. join psudo AdHoc */
+	tgt_network->join_res = 1;
+	tgt_network->aid = psta->cmn.aid = 1;
+
+	_rtw_memcpy(&padapter->registrypriv.dev_network, &bssid, length);
+	rtw_update_registrypriv_dev_network(padapter);
+	_rtw_memcpy(&tgt_network->network, &padapter->registrypriv.dev_network, padapter->registrypriv.dev_network.Length);
+	_rtw_memcpy(pnetwork, &padapter->registrypriv.dev_network, padapter->registrypriv.dev_network.Length);
+
+	rtw_indicate_connect(padapter);
+	_clr_fwstate_(pmlmepriv, _FW_UNDER_LINKING);
+	set_fwstate(pmlmepriv, _FW_LINKED);
+
+end_of_mp_start_test:
+
+	_exit_critical_bh(&pmlmepriv->lock, &irqL);
+
+	if (1) { /* (res == _SUCCESS) */
+		/* set MSR to WIFI_FW_ADHOC_STATE */
+		if (mode == WIFI_FW_ADHOC_STATE) {
+			/* set msr to WIFI_FW_ADHOC_STATE */
+			pmlmeinfo->state = WIFI_FW_ADHOC_STATE;
+			Set_MSR(padapter, (pmlmeinfo->state & 0x3));
+			rtw_hal_set_hwreg(padapter, HW_VAR_BSSID, padapter->registrypriv.dev_network.MacAddress);
+			rtw_hal_rcr_set_chk_bssid(padapter, MLME_ADHOC_STARTED);
+			pmlmeinfo->state |= WIFI_FW_ASSOC_SUCCESS;
+		} else {
+			Set_MSR(padapter, WIFI_FW_STATION_STATE);
+
+			RTW_INFO("%s , pmppriv->network_macaddr =%x %x %x %x %x %x\n", __func__,
+				pmppriv->network_macaddr[0], pmppriv->network_macaddr[1], pmppriv->network_macaddr[2], pmppriv->network_macaddr[3], pmppriv->network_macaddr[4],
+				 pmppriv->network_macaddr[5]);
+
+			rtw_hal_set_hwreg(padapter, HW_VAR_BSSID, pmppriv->network_macaddr);
+		}
+	}
+
+	return res;
+}
+/* This function initializes the DUT to the MP test mode */
+s32 mp_start_test(PADAPTER padapter)
+{
+	struct mp_priv *pmppriv = &padapter->mppriv;
+	s32 res = _SUCCESS;
+
+	padapter->registrypriv.mp_mode = 1;
+
+	init_mp_data(padapter);
+#ifdef CONFIG_RTL8814A
+	rtl8814_InitHalDm(padapter);
+#endif /* CONFIG_RTL8814A */
+#ifdef CONFIG_RTL8812A
+	rtl8812_InitHalDm(padapter);
+#endif /* CONFIG_RTL8812A */
+#ifdef CONFIG_RTL8723B
+	rtl8723b_InitHalDm(padapter);
+#endif /* CONFIG_RTL8723B */
+#ifdef CONFIG_RTL8703B
+	rtl8703b_InitHalDm(padapter);
+#endif /* CONFIG_RTL8703B */
+#ifdef CONFIG_RTL8192E
+	rtl8192e_InitHalDm(padapter);
+#endif
+#ifdef CONFIG_RTL8188F
+	rtl8188f_InitHalDm(padapter);
+#endif
+#ifdef CONFIG_RTL8188GTV
+	rtl8188gtv_InitHalDm(padapter);
+#endif
+#ifdef CONFIG_RTL8188E
+	rtl8188e_InitHalDm(padapter);
+#endif
+#ifdef CONFIG_RTL8723D
+	rtl8723d_InitHalDm(padapter);
+#endif /* CONFIG_RTL8723D */
+
+	/* 3 0. update mp_priv */
+
+	if (!RF_TYPE_VALID(padapter->registrypriv.rf_config)) {
+		/*		switch (phal->rf_type) { */
+		switch (GET_RF_TYPE(padapter)) {
+		case RF_1T1R:
+			pmppriv->antenna_tx = ANTENNA_A;
+			pmppriv->antenna_rx = ANTENNA_A;
+			break;
+		case RF_1T2R:
+		default:
+			pmppriv->antenna_tx = ANTENNA_A;
+			pmppriv->antenna_rx = ANTENNA_AB;
+			break;
+		case RF_2T2R:
+			pmppriv->antenna_tx = ANTENNA_AB;
+			pmppriv->antenna_rx = ANTENNA_AB;
+			break;
+		case RF_2T4R:
+			pmppriv->antenna_tx = ANTENNA_AB;
+			pmppriv->antenna_rx = ANTENNA_ABCD;
+			break;
+		}
+	}
+
+	mpt_ProStartTest(padapter);
+
+	mp_join(padapter, WIFI_FW_ADHOC_STATE);
+
+	return res;
+}
+/* ------------------------------------------------------------------------------
+ * This function change the DUT from the MP test mode into normal mode */
+void mp_stop_test(PADAPTER padapter)
+{
+	struct mp_priv *pmppriv = &padapter->mppriv;
+	struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
+	struct wlan_network *tgt_network = &pmlmepriv->cur_network;
+	struct sta_info *psta;
+
+	_irqL irqL;
+
+	if (pmppriv->mode == MP_ON) {
+		pmppriv->bSetTxPower = 0;
+		_enter_critical_bh(&pmlmepriv->lock, &irqL);
+		if (check_fwstate(pmlmepriv, WIFI_MP_STATE) == _FALSE)
+			goto end_of_mp_stop_test;
+
+		/* 3 1. disconnect psudo AdHoc */
+		rtw_indicate_disconnect(padapter, 0, _FALSE);
+
+		/* 3 2. clear psta used in mp test mode.
+		*	rtw_free_assoc_resources(padapter, _TRUE); */
+		psta = rtw_get_stainfo(&padapter->stapriv, tgt_network->network.MacAddress);
+		if (psta)
+			rtw_free_stainfo(padapter, psta);
+
+		/* 3 3. return to normal state (default:station mode) */
+		/*pmlmepriv->fw_state = pmppriv->prev_fw_state; */ /* WIFI_STATION_STATE;*/
+		init_fwstate(pmlmepriv, pmppriv->prev_fw_state);
+
+		/* flush the cur_network */
+		_rtw_memset(tgt_network, 0, sizeof(struct wlan_network));
+
+		_clr_fwstate_(pmlmepriv, WIFI_MP_STATE);
+
+end_of_mp_stop_test:
+
+		_exit_critical_bh(&pmlmepriv->lock, &irqL);
+
+#ifdef CONFIG_RTL8812A
+		rtl8812_InitHalDm(padapter);
+#endif
+#ifdef CONFIG_RTL8723B
+		rtl8723b_InitHalDm(padapter);
+#endif
+#ifdef CONFIG_RTL8703B
+		rtl8703b_InitHalDm(padapter);
+#endif
+#ifdef CONFIG_RTL8192E
+		rtl8192e_InitHalDm(padapter);
+#endif
+#ifdef CONFIG_RTL8188F
+		rtl8188f_InitHalDm(padapter);
+#endif
+#ifdef CONFIG_RTL8188GTV
+		rtl8188gtv_InitHalDm(padapter);
+#endif
+#ifdef CONFIG_RTL8723D
+		rtl8723d_InitHalDm(padapter);
+#endif
+	}
+}
+/*---------------------------hal\rtl8192c\MPT_Phy.c---------------------------*/
+#if 0
+/* #ifdef CONFIG_USB_HCI */
+static VOID mpt_AdjustRFRegByRateByChan92CU(PADAPTER pAdapter, u8 RateIdx, u8 Channel, u8 BandWidthID)
+{
+	u8		eRFPath;
+	u32		rfReg0x26;
+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(pAdapter);
+
+
+	if (RateIdx < MPT_RATE_6M) 	/* CCK rate,for 88cu */
+		rfReg0x26 = 0xf400;
+	else if ((RateIdx >= MPT_RATE_6M) && (RateIdx <= MPT_RATE_54M)) {/* OFDM rate,for 88cu */
+		if ((4 == Channel) || (8 == Channel) || (12 == Channel))
+			rfReg0x26 = 0xf000;
+		else if ((5 == Channel) || (7 == Channel) || (13 == Channel) || (14 == Channel))
+			rfReg0x26 = 0xf400;
+		else
+			rfReg0x26 = 0x4f200;
+	} else if ((RateIdx >= MPT_RATE_MCS0) && (RateIdx <= MPT_RATE_MCS15)) {
+		/* MCS 20M ,for 88cu */ /* MCS40M rate,for 88cu */
+
+		if (CHANNEL_WIDTH_20 == BandWidthID) {
+			if ((4 == Channel) || (8 == Channel))
+				rfReg0x26 = 0xf000;
+			else if ((5 == Channel) || (7 == Channel) || (13 == Channel) || (14 == Channel))
+				rfReg0x26 = 0xf400;
+			else
+				rfReg0x26 = 0x4f200;
+		} else {
+			if ((4 == Channel) || (8 == Channel))
+				rfReg0x26 = 0xf000;
+			else if ((5 == Channel) || (7 == Channel))
+				rfReg0x26 = 0xf400;
+			else
+				rfReg0x26 = 0x4f200;
+		}
+	}
+
+	for (eRFPath = 0; eRFPath < pHalData->NumTotalRFPath; eRFPath++)
+		write_rfreg(pAdapter, eRFPath, RF_SYN_G2, rfReg0x26);
+}
+#endif
+/*-----------------------------------------------------------------------------
+ * Function:	mpt_SwitchRfSetting
+ *
+ * Overview:	Change RF Setting when we siwthc channel/rate/BW for MP.
+ *
+ * Input:       IN	PADAPTER				pAdapter
+ *
+ * Output:      NONE
+ *
+ * Return:      NONE
+ *
+ * Revised History:
+ * When			Who		Remark
+ * 01/08/2009	MHC		Suggestion from SD3 Willis for 92S series.
+ * 01/09/2009	MHC		Add CCK modification for 40MHZ. Suggestion from SD3.
+ *
+ *---------------------------------------------------------------------------*/
+#if 0
+static void mpt_SwitchRfSetting(PADAPTER pAdapter)
+{
+	hal_mpt_SwitchRfSetting(pAdapter);
+}
+
+/*---------------------------hal\rtl8192c\MPT_Phy.c---------------------------*/
+/*---------------------------hal\rtl8192c\MPT_HelperFunc.c---------------------------*/
+static void MPT_CCKTxPowerAdjust(PADAPTER Adapter, BOOLEAN bInCH14)
+{
+	hal_mpt_CCKTxPowerAdjust(Adapter, bInCH14);
+}
+#endif
+
+/*---------------------------hal\rtl8192c\MPT_HelperFunc.c---------------------------*/
+
+/*
+ * SetChannel
+ * Description
+ *	Use H2C command to change channel,
+ *	not only modify rf register, but also other setting need to be done.
+ */
+void SetChannel(PADAPTER pAdapter)
+{
+	hal_mpt_SetChannel(pAdapter);
+}
+
+/*
+ * Notice
+ *	Switch bandwitdth may change center frequency(channel)
+ */
+void SetBandwidth(PADAPTER pAdapter)
+{
+	hal_mpt_SetBandwidth(pAdapter);
+
+}
+
+void SetAntenna(PADAPTER pAdapter)
+{
+	hal_mpt_SetAntenna(pAdapter);
+}
+
+int SetTxPower(PADAPTER pAdapter)
+{
+
+	hal_mpt_SetTxPower(pAdapter);
+	return _TRUE;
+}
+
+void SetTxAGCOffset(PADAPTER pAdapter, u32 ulTxAGCOffset)
+{
+	u32 TxAGCOffset_B, TxAGCOffset_C, TxAGCOffset_D, tmpAGC;
+
+	TxAGCOffset_B = (ulTxAGCOffset & 0x000000ff);
+	TxAGCOffset_C = ((ulTxAGCOffset & 0x0000ff00) >> 8);
+	TxAGCOffset_D = ((ulTxAGCOffset & 0x00ff0000) >> 16);
+
+	tmpAGC = (TxAGCOffset_D << 8 | TxAGCOffset_C << 4 | TxAGCOffset_B);
+	write_bbreg(pAdapter, rFPGA0_TxGainStage,
+		    (bXBTxAGC | bXCTxAGC | bXDTxAGC), tmpAGC);
+}
+
+void SetDataRate(PADAPTER pAdapter)
+{
+	hal_mpt_SetDataRate(pAdapter);
+}
+
+void MP_PHY_SetRFPathSwitch(PADAPTER pAdapter , BOOLEAN bMain)
+{
+
+	PHY_SetRFPathSwitch(pAdapter, bMain);
+
+}
+
+void mp_phy_switch_rf_path_set(PADAPTER pAdapter , u8 *pstate)
+{
+
+	phy_switch_rf_path_set(pAdapter, pstate);
+
+}
+
+u8 MP_PHY_QueryRFPathSwitch(PADAPTER pAdapter)
+{
+	return PHY_QueryRFPathSwitch(pAdapter);
+}
+
+s32 SetThermalMeter(PADAPTER pAdapter, u8 target_ther)
+{
+	return hal_mpt_SetThermalMeter(pAdapter, target_ther);
+}
+
+#if 0
+static void TriggerRFThermalMeter(PADAPTER pAdapter)
+{
+	hal_mpt_TriggerRFThermalMeter(pAdapter);
+}
+
+static u8 ReadRFThermalMeter(PADAPTER pAdapter)
+{
+	return hal_mpt_ReadRFThermalMeter(pAdapter);
+}
+#endif
+
+void GetThermalMeter(PADAPTER pAdapter, u8 *value)
+{
+	hal_mpt_GetThermalMeter(pAdapter, value);
+}
+
+void SetSingleCarrierTx(PADAPTER pAdapter, u8 bStart)
+{
+	PhySetTxPowerLevel(pAdapter);
+	hal_mpt_SetSingleCarrierTx(pAdapter, bStart);
+}
+
+void SetSingleToneTx(PADAPTER pAdapter, u8 bStart)
+{
+	PhySetTxPowerLevel(pAdapter);
+	hal_mpt_SetSingleToneTx(pAdapter, bStart);
+}
+
+void SetCarrierSuppressionTx(PADAPTER pAdapter, u8 bStart)
+{
+	PhySetTxPowerLevel(pAdapter);
+	hal_mpt_SetCarrierSuppressionTx(pAdapter, bStart);
+}
+
+void SetContinuousTx(PADAPTER pAdapter, u8 bStart)
+{
+	PhySetTxPowerLevel(pAdapter);
+	hal_mpt_SetContinuousTx(pAdapter, bStart);
+}
+
+
+void PhySetTxPowerLevel(PADAPTER pAdapter)
+{
+	struct mp_priv *pmp_priv = &pAdapter->mppriv;
+
+
+	if (pmp_priv->bSetTxPower == 0) /* for NO manually set power index */
+		rtw_hal_set_tx_power_level(pAdapter, pmp_priv->channel);
+}
+
+/* ------------------------------------------------------------------------------ */
+static void dump_mpframe(PADAPTER padapter, struct xmit_frame *pmpframe)
+{
+	rtw_hal_mgnt_xmit(padapter, pmpframe);
+}
+
+static struct xmit_frame *alloc_mp_xmitframe(struct xmit_priv *pxmitpriv)
+{
+	struct xmit_frame	*pmpframe;
+	struct xmit_buf	*pxmitbuf;
+
+	pmpframe = rtw_alloc_xmitframe(pxmitpriv);
+	if (pmpframe == NULL)
+		return NULL;
+
+	pxmitbuf = rtw_alloc_xmitbuf(pxmitpriv);
+	if (pxmitbuf == NULL) {
+		rtw_free_xmitframe(pxmitpriv, pmpframe);
+		return NULL;
+	}
+
+	pmpframe->frame_tag = MP_FRAMETAG;
+
+	pmpframe->pxmitbuf = pxmitbuf;
+
+	pmpframe->buf_addr = pxmitbuf->pbuf;
+
+	pxmitbuf->priv_data = pmpframe;
+
+	return pmpframe;
+
+}
+
+#ifdef CONFIG_PCI_HCI
+static u8 check_nic_enough_desc(_adapter *padapter, struct pkt_attrib *pattrib)
+{
+	u32 prio;
+	struct xmit_priv	*pxmitpriv = &padapter->xmitpriv;
+	struct rtw_tx_ring	*ring;
+
+	switch (pattrib->qsel) {
+	case 0:
+	case 3:
+		prio = BE_QUEUE_INX;
+		break;
+	case 1:
+	case 2:
+		prio = BK_QUEUE_INX;
+		break;
+	case 4:
+	case 5:
+		prio = VI_QUEUE_INX;
+		break;
+	case 6:
+	case 7:
+		prio = VO_QUEUE_INX;
+		break;
+	default:
+		prio = BE_QUEUE_INX;
+		break;
+	}
+
+	ring = &pxmitpriv->tx_ring[prio];
+
+	/*
+	 * for now we reserve two free descriptor as a safety boundary
+	 * between the tail and the head
+	 */
+	if ((ring->entries - ring->qlen) >= 2)
+		return _TRUE;
+	else
+		return _FALSE;
+}
+#endif
+
+static thread_return mp_xmit_packet_thread(thread_context context)
+{
+	struct xmit_frame	*pxmitframe;
+	struct mp_tx		*pmptx;
+	struct mp_priv	*pmp_priv;
+	struct xmit_priv	*pxmitpriv;
+	PADAPTER padapter;
+
+	pmp_priv = (struct mp_priv *)context;
+	pmptx = &pmp_priv->tx;
+	padapter = pmp_priv->papdater;
+	pxmitpriv = &(padapter->xmitpriv);
+
+	thread_enter("RTW_MP_THREAD");
+
+	RTW_INFO("%s:pkTx Start\n", __func__);
+	while (1) {
+		pxmitframe = alloc_mp_xmitframe(pxmitpriv);
+#ifdef CONFIG_PCI_HCI
+		if(check_nic_enough_desc(padapter, &pmptx->attrib) == _FALSE) {
+			rtw_usleep_os(1000);
+			continue;
+		}
+#endif
+		if (pxmitframe == NULL) {
+			if (pmptx->stop ||
+			    RTW_CANNOT_RUN(padapter))
+				goto exit;
+			else {
+				rtw_usleep_os(10);
+				continue;
+			}
+		}
+		_rtw_memcpy((u8 *)(pxmitframe->buf_addr + TXDESC_OFFSET), pmptx->buf, pmptx->write_size);
+		_rtw_memcpy(&(pxmitframe->attrib), &(pmptx->attrib), sizeof(struct pkt_attrib));
+
+
+		rtw_usleep_os(padapter->mppriv.pktInterval);
+		dump_mpframe(padapter, pxmitframe);
+
+		pmptx->sended++;
+		pmp_priv->tx_pktcount++;
+
+		if (pmptx->stop ||
+		    RTW_CANNOT_RUN(padapter))
+			goto exit;
+		if ((pmptx->count != 0) &&
+		    (pmptx->count == pmptx->sended))
+			goto exit;
+
+		flush_signals_thread();
+	}
+
+exit:
+	/* RTW_INFO("%s:pkTx Exit\n", __func__); */
+	rtw_mfree(pmptx->pallocated_buf, pmptx->buf_size);
+	pmptx->pallocated_buf = NULL;
+	pmptx->stop = 1;
+
+	thread_exit(NULL);
+	return 0;
+}
+
+void fill_txdesc_for_mp(PADAPTER padapter, u8 *ptxdesc)
+{
+	struct mp_priv *pmp_priv = &padapter->mppriv;
+	_rtw_memcpy(ptxdesc, pmp_priv->tx.desc, TXDESC_SIZE);
+}
+
+#if defined(CONFIG_RTL8188E)
+void fill_tx_desc_8188e(PADAPTER padapter)
+{
+	struct mp_priv *pmp_priv = &padapter->mppriv;
+	struct tx_desc *desc   = (struct tx_desc *)&(pmp_priv->tx.desc);
+	struct pkt_attrib *pattrib = &(pmp_priv->tx.attrib);
+	u32	pkt_size = pattrib->last_txcmdsz;
+	s32 bmcast = IS_MCAST(pattrib->ra);
+	/* offset 0 */
+#if !defined(CONFIG_RTL8188E_SDIO) && !defined(CONFIG_PCI_HCI)
+	desc->txdw0 |= cpu_to_le32(OWN | FSG | LSG);
+	desc->txdw0 |= cpu_to_le32(pkt_size & 0x0000FFFF); /* packet size */
+	desc->txdw0 |= cpu_to_le32(((TXDESC_SIZE + OFFSET_SZ) << OFFSET_SHT) & 0x00FF0000); /* 32 bytes for TX Desc */
+	if (bmcast)
+		desc->txdw0 |= cpu_to_le32(BMC); /* broadcast packet */
+
+	desc->txdw1 |= cpu_to_le32((0x01 << 26) & 0xff000000);
+#endif
+
+	desc->txdw1 |= cpu_to_le32((pattrib->mac_id) & 0x3F); /* CAM_ID(MAC_ID) */
+	desc->txdw1 |= cpu_to_le32((pattrib->qsel << QSEL_SHT) & 0x00001F00); /* Queue Select, TID */
+	desc->txdw1 |= cpu_to_le32((pattrib->raid << RATE_ID_SHT) & 0x000F0000); /* Rate Adaptive ID */
+	/* offset 8 */
+	/* desc->txdw2 |= cpu_to_le32(AGG_BK); */ /* AGG BK */
+
+	desc->txdw3 |= cpu_to_le32((pattrib->seqnum << 16) & 0x0fff0000);
+	desc->txdw4 |= cpu_to_le32(HW_SSN);
+
+	desc->txdw4 |= cpu_to_le32(USERATE);
+	desc->txdw4 |= cpu_to_le32(DISDATAFB);
+
+	if (pmp_priv->preamble) {
+		if (HwRateToMPTRate(pmp_priv->rateidx) <=  MPT_RATE_54M)
+			desc->txdw4 |= cpu_to_le32(DATA_SHORT); /* CCK Short Preamble */
+	}
+
+	if (pmp_priv->bandwidth == CHANNEL_WIDTH_40)
+		desc->txdw4 |= cpu_to_le32(DATA_BW);
+
+	/* offset 20 */
+	desc->txdw5 |= cpu_to_le32(pmp_priv->rateidx & 0x0000001F);
+
+	if (pmp_priv->preamble) {
+		if (HwRateToMPTRate(pmp_priv->rateidx) > MPT_RATE_54M)
+			desc->txdw5 |= cpu_to_le32(SGI); /* MCS Short Guard Interval */
+	}
+
+	desc->txdw5 |= cpu_to_le32(RTY_LMT_EN); /* retry limit enable */
+	desc->txdw5 |= cpu_to_le32(0x00180000); /* DATA/RTS Rate Fallback Limit	 */
+
+
+}
+#endif
+
+#if defined(CONFIG_RTL8814A)
+void fill_tx_desc_8814a(PADAPTER padapter)
+{
+	struct mp_priv *pmp_priv = &padapter->mppriv;
+	u8 *pDesc   = (u8 *)&(pmp_priv->tx.desc);
+	struct pkt_attrib *pattrib = &(pmp_priv->tx.attrib);
+
+	u32	pkt_size = pattrib->last_txcmdsz;
+	s32 bmcast = IS_MCAST(pattrib->ra);
+	u8 offset;
+
+	/* SET_TX_DESC_FIRST_SEG_8814A(pDesc, 1); */
+	SET_TX_DESC_LAST_SEG_8814A(pDesc, 1);
+	/* SET_TX_DESC_OWN_(pDesc, 1); */
+
+	SET_TX_DESC_PKT_SIZE_8814A(pDesc, pkt_size);
+
+	offset = TXDESC_SIZE + OFFSET_SZ;
+
+	SET_TX_DESC_OFFSET_8814A(pDesc, offset);
+#if defined(CONFIG_PCI_HCI)
+	SET_TX_DESC_PKT_OFFSET_8814A(pDesc, 0); /* 8814AE pkt_offset is 0 */
+#else
+	SET_TX_DESC_PKT_OFFSET_8814A(pDesc, 1);
+#endif
+
+	if (bmcast)
+		SET_TX_DESC_BMC_8814A(pDesc, 1);
+
+	SET_TX_DESC_MACID_8814A(pDesc, pattrib->mac_id);
+	SET_TX_DESC_RATE_ID_8814A(pDesc, pattrib->raid);
+
+	/* SET_TX_DESC_RATE_ID_8812(pDesc, RATEID_IDX_G); */
+	SET_TX_DESC_QUEUE_SEL_8814A(pDesc,  pattrib->qsel);
+	/* SET_TX_DESC_QUEUE_SEL_8812(pDesc,  QSLT_MGNT); */
+
+	if (pmp_priv->preamble)
+		SET_TX_DESC_DATA_SHORT_8814A(pDesc, 1);
+
+	if (!pattrib->qos_en) {
+		SET_TX_DESC_HWSEQ_EN_8814A(pDesc, 1); /* Hw set sequence number */
+	} else
+		SET_TX_DESC_SEQ_8814A(pDesc, pattrib->seqnum);
+
+	if (pmp_priv->bandwidth <= CHANNEL_WIDTH_160)
+		SET_TX_DESC_DATA_BW_8814A(pDesc, pmp_priv->bandwidth);
+	else {
+		RTW_INFO("%s:Err: unknown bandwidth %d, use 20M\n", __func__, pmp_priv->bandwidth);
+		SET_TX_DESC_DATA_BW_8814A(pDesc, CHANNEL_WIDTH_20);
+	}
+
+	SET_TX_DESC_DISABLE_FB_8814A(pDesc, 1);
+	SET_TX_DESC_USE_RATE_8814A(pDesc, 1);
+	SET_TX_DESC_TX_RATE_8814A(pDesc, pmp_priv->rateidx);
+
+}
+#endif
+
+#if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A)
+void fill_tx_desc_8812a(PADAPTER padapter)
+{
+	struct mp_priv *pmp_priv = &padapter->mppriv;
+	u8 *pDesc   = (u8 *)&(pmp_priv->tx.desc);
+	struct pkt_attrib *pattrib = &(pmp_priv->tx.attrib);
+
+	u32	pkt_size = pattrib->last_txcmdsz;
+	s32 bmcast = IS_MCAST(pattrib->ra);
+	u8 data_rate, pwr_status, offset;
+
+	SET_TX_DESC_FIRST_SEG_8812(pDesc, 1);
+	SET_TX_DESC_LAST_SEG_8812(pDesc, 1);
+	SET_TX_DESC_OWN_8812(pDesc, 1);
+
+	SET_TX_DESC_PKT_SIZE_8812(pDesc, pkt_size);
+
+	offset = TXDESC_SIZE + OFFSET_SZ;
+
+	SET_TX_DESC_OFFSET_8812(pDesc, offset);
+
+#if defined(CONFIG_PCI_HCI)
+	SET_TX_DESC_PKT_OFFSET_8812(pDesc, 0);
+#else
+	SET_TX_DESC_PKT_OFFSET_8812(pDesc, 1);
+#endif
+	if (bmcast)
+		SET_TX_DESC_BMC_8812(pDesc, 1);
+
+	SET_TX_DESC_MACID_8812(pDesc, pattrib->mac_id);
+	SET_TX_DESC_RATE_ID_8812(pDesc, pattrib->raid);
+
+	/* SET_TX_DESC_RATE_ID_8812(pDesc, RATEID_IDX_G); */
+	SET_TX_DESC_QUEUE_SEL_8812(pDesc,  pattrib->qsel);
+	/* SET_TX_DESC_QUEUE_SEL_8812(pDesc,  QSLT_MGNT); */
+
+	if (!pattrib->qos_en) {
+		SET_TX_DESC_HWSEQ_EN_8812(pDesc, 1); /* Hw set sequence number */
+	} else
+		SET_TX_DESC_SEQ_8812(pDesc, pattrib->seqnum);
+
+	if (pmp_priv->bandwidth <= CHANNEL_WIDTH_160)
+		SET_TX_DESC_DATA_BW_8812(pDesc, pmp_priv->bandwidth);
+	else {
+		RTW_INFO("%s:Err: unknown bandwidth %d, use 20M\n", __func__, pmp_priv->bandwidth);
+		SET_TX_DESC_DATA_BW_8812(pDesc, CHANNEL_WIDTH_20);
+	}
+
+	SET_TX_DESC_DISABLE_FB_8812(pDesc, 1);
+	SET_TX_DESC_USE_RATE_8812(pDesc, 1);
+	SET_TX_DESC_TX_RATE_8812(pDesc, pmp_priv->rateidx);
+
+}
+#endif
+#if defined(CONFIG_RTL8192E)
+void fill_tx_desc_8192e(PADAPTER padapter)
+{
+	struct mp_priv *pmp_priv = &padapter->mppriv;
+	u8 *pDesc	= (u8 *)&(pmp_priv->tx.desc);
+	struct pkt_attrib *pattrib = &(pmp_priv->tx.attrib);
+
+	u32 pkt_size = pattrib->last_txcmdsz;
+	s32 bmcast = IS_MCAST(pattrib->ra);
+	u8 data_rate, pwr_status, offset;
+
+
+	SET_TX_DESC_PKT_SIZE_92E(pDesc, pkt_size);
+
+	offset = TXDESC_SIZE + OFFSET_SZ;
+
+	SET_TX_DESC_OFFSET_92E(pDesc, offset);
+#if defined(CONFIG_PCI_HCI) /* 8192EE */
+
+	SET_TX_DESC_PKT_OFFSET_92E(pDesc, 0); /* 8192EE pkt_offset is 0 */
+#else /* 8192EU 8192ES */
+	SET_TX_DESC_PKT_OFFSET_92E(pDesc, 1);
+#endif
+
+	if (bmcast)
+		SET_TX_DESC_BMC_92E(pDesc, 1);
+
+	SET_TX_DESC_MACID_92E(pDesc, pattrib->mac_id);
+	SET_TX_DESC_RATE_ID_92E(pDesc, pattrib->raid);
+
+
+	SET_TX_DESC_QUEUE_SEL_92E(pDesc,  pattrib->qsel);
+	/* SET_TX_DESC_QUEUE_SEL_8812(pDesc,  QSLT_MGNT); */
+
+	if (!pattrib->qos_en) {
+		SET_TX_DESC_EN_HWSEQ_92E(pDesc, 1);/* Hw set sequence number */
+		SET_TX_DESC_HWSEQ_SEL_92E(pDesc, pattrib->hw_ssn_sel);
+	} else
+		SET_TX_DESC_SEQ_92E(pDesc, pattrib->seqnum);
+
+	if ((pmp_priv->bandwidth == CHANNEL_WIDTH_20) || (pmp_priv->bandwidth == CHANNEL_WIDTH_40))
+		SET_TX_DESC_DATA_BW_92E(pDesc, pmp_priv->bandwidth);
+	else {
+		RTW_INFO("%s:Err: unknown bandwidth %d, use 20M\n", __func__, pmp_priv->bandwidth);
+		SET_TX_DESC_DATA_BW_92E(pDesc, CHANNEL_WIDTH_20);
+	}
+
+	/* SET_TX_DESC_DATA_SC_92E(pDesc, SCMapping_92E(padapter,pattrib)); */
+
+	SET_TX_DESC_DISABLE_FB_92E(pDesc, 1);
+	SET_TX_DESC_USE_RATE_92E(pDesc, 1);
+	SET_TX_DESC_TX_RATE_92E(pDesc, pmp_priv->rateidx);
+
+}
+#endif
+
+#if defined(CONFIG_RTL8723B)
+void fill_tx_desc_8723b(PADAPTER padapter)
+{
+	struct mp_priv *pmp_priv = &padapter->mppriv;
+	struct pkt_attrib *pattrib = &(pmp_priv->tx.attrib);
+	u8 *ptxdesc = pmp_priv->tx.desc;
+
+	SET_TX_DESC_AGG_BREAK_8723B(ptxdesc, 1);
+	SET_TX_DESC_MACID_8723B(ptxdesc, pattrib->mac_id);
+	SET_TX_DESC_QUEUE_SEL_8723B(ptxdesc, pattrib->qsel);
+
+	SET_TX_DESC_RATE_ID_8723B(ptxdesc, pattrib->raid);
+	SET_TX_DESC_SEQ_8723B(ptxdesc, pattrib->seqnum);
+	SET_TX_DESC_HWSEQ_EN_8723B(ptxdesc, 1);
+	SET_TX_DESC_USE_RATE_8723B(ptxdesc, 1);
+	SET_TX_DESC_DISABLE_FB_8723B(ptxdesc, 1);
+
+	if (pmp_priv->preamble) {
+		if (HwRateToMPTRate(pmp_priv->rateidx) <=  MPT_RATE_54M)
+			SET_TX_DESC_DATA_SHORT_8723B(ptxdesc, 1);
+	}
+
+	if (pmp_priv->bandwidth == CHANNEL_WIDTH_40)
+		SET_TX_DESC_DATA_BW_8723B(ptxdesc, 1);
+
+	SET_TX_DESC_TX_RATE_8723B(ptxdesc, pmp_priv->rateidx);
+
+	SET_TX_DESC_DATA_RATE_FB_LIMIT_8723B(ptxdesc, 0x1F);
+	SET_TX_DESC_RTS_RATE_FB_LIMIT_8723B(ptxdesc, 0xF);
+}
+#endif
+
+#if defined(CONFIG_RTL8703B)
+void fill_tx_desc_8703b(PADAPTER padapter)
+{
+	struct mp_priv *pmp_priv = &padapter->mppriv;
+	struct pkt_attrib *pattrib = &(pmp_priv->tx.attrib);
+	u8 *ptxdesc = pmp_priv->tx.desc;
+
+	SET_TX_DESC_AGG_BREAK_8703B(ptxdesc, 1);
+	SET_TX_DESC_MACID_8703B(ptxdesc, pattrib->mac_id);
+	SET_TX_DESC_QUEUE_SEL_8703B(ptxdesc, pattrib->qsel);
+
+	SET_TX_DESC_RATE_ID_8703B(ptxdesc, pattrib->raid);
+	SET_TX_DESC_SEQ_8703B(ptxdesc, pattrib->seqnum);
+	SET_TX_DESC_HWSEQ_EN_8703B(ptxdesc, 1);
+	SET_TX_DESC_USE_RATE_8703B(ptxdesc, 1);
+	SET_TX_DESC_DISABLE_FB_8703B(ptxdesc, 1);
+
+	if (pmp_priv->preamble) {
+		if (HwRateToMPTRate(pmp_priv->rateidx) <=  MPT_RATE_54M)
+			SET_TX_DESC_DATA_SHORT_8703B(ptxdesc, 1);
+	}
+
+	if (pmp_priv->bandwidth == CHANNEL_WIDTH_40)
+		SET_TX_DESC_DATA_BW_8703B(ptxdesc, 1);
+
+	SET_TX_DESC_TX_RATE_8703B(ptxdesc, pmp_priv->rateidx);
+
+	SET_TX_DESC_DATA_RATE_FB_LIMIT_8703B(ptxdesc, 0x1F);
+	SET_TX_DESC_RTS_RATE_FB_LIMIT_8703B(ptxdesc, 0xF);
+}
+#endif
+
+#if defined(CONFIG_RTL8188F)
+void fill_tx_desc_8188f(PADAPTER padapter)
+{
+	struct mp_priv *pmp_priv = &padapter->mppriv;
+	struct pkt_attrib *pattrib = &(pmp_priv->tx.attrib);
+	u8 *ptxdesc = pmp_priv->tx.desc;
+
+	SET_TX_DESC_AGG_BREAK_8188F(ptxdesc, 1);
+	SET_TX_DESC_MACID_8188F(ptxdesc, pattrib->mac_id);
+	SET_TX_DESC_QUEUE_SEL_8188F(ptxdesc, pattrib->qsel);
+
+	SET_TX_DESC_RATE_ID_8188F(ptxdesc, pattrib->raid);
+	SET_TX_DESC_SEQ_8188F(ptxdesc, pattrib->seqnum);
+	SET_TX_DESC_HWSEQ_EN_8188F(ptxdesc, 1);
+	SET_TX_DESC_USE_RATE_8188F(ptxdesc, 1);
+	SET_TX_DESC_DISABLE_FB_8188F(ptxdesc, 1);
+
+	if (pmp_priv->preamble)
+		if (HwRateToMPTRate(pmp_priv->rateidx) <=  MPT_RATE_54M)
+			SET_TX_DESC_DATA_SHORT_8188F(ptxdesc, 1);
+
+	if (pmp_priv->bandwidth == CHANNEL_WIDTH_40)
+		SET_TX_DESC_DATA_BW_8188F(ptxdesc, 1);
+
+	SET_TX_DESC_TX_RATE_8188F(ptxdesc, pmp_priv->rateidx);
+
+	SET_TX_DESC_DATA_RATE_FB_LIMIT_8188F(ptxdesc, 0x1F);
+	SET_TX_DESC_RTS_RATE_FB_LIMIT_8188F(ptxdesc, 0xF);
+}
+#endif
+
+#if defined(CONFIG_RTL8188GTV)
+void fill_tx_desc_8188gtv(PADAPTER padapter)
+{
+	struct mp_priv *pmp_priv = &padapter->mppriv;
+	struct pkt_attrib *pattrib = &(pmp_priv->tx.attrib);
+	u8 *ptxdesc = pmp_priv->tx.desc;
+
+	SET_TX_DESC_AGG_BREAK_8188GTV(ptxdesc, 1);
+	SET_TX_DESC_MACID_8188GTV(ptxdesc, pattrib->mac_id);
+	SET_TX_DESC_QUEUE_SEL_8188GTV(ptxdesc, pattrib->qsel);
+
+	SET_TX_DESC_RATE_ID_8188GTV(ptxdesc, pattrib->raid);
+	SET_TX_DESC_SEQ_8188GTV(ptxdesc, pattrib->seqnum);
+	SET_TX_DESC_HWSEQ_EN_8188GTV(ptxdesc, 1);
+	SET_TX_DESC_USE_RATE_8188GTV(ptxdesc, 1);
+	SET_TX_DESC_DISABLE_FB_8188GTV(ptxdesc, 1);
+
+	if (pmp_priv->preamble)
+		if (HwRateToMPTRate(pmp_priv->rateidx) <=  MPT_RATE_54M)
+			SET_TX_DESC_DATA_SHORT_8188GTV(ptxdesc, 1);
+
+	if (pmp_priv->bandwidth == CHANNEL_WIDTH_40)
+		SET_TX_DESC_DATA_BW_8188GTV(ptxdesc, 1);
+
+	SET_TX_DESC_TX_RATE_8188GTV(ptxdesc, pmp_priv->rateidx);
+
+	SET_TX_DESC_DATA_RATE_FB_LIMIT_8188GTV(ptxdesc, 0x1F);
+	SET_TX_DESC_RTS_RATE_FB_LIMIT_8188GTV(ptxdesc, 0xF);
+}
+#endif
+
+#if defined(CONFIG_RTL8723D)
+void fill_tx_desc_8723d(PADAPTER padapter)
+{
+	struct mp_priv *pmp_priv = &padapter->mppriv;
+	struct pkt_attrib *pattrib = &(pmp_priv->tx.attrib);
+	u8 *ptxdesc = pmp_priv->tx.desc;
+
+	SET_TX_DESC_BK_8723D(ptxdesc, 1);
+	SET_TX_DESC_MACID_8723D(ptxdesc, pattrib->mac_id);
+	SET_TX_DESC_QUEUE_SEL_8723D(ptxdesc, pattrib->qsel);
+
+	SET_TX_DESC_RATE_ID_8723D(ptxdesc, pattrib->raid);
+	SET_TX_DESC_SEQ_8723D(ptxdesc, pattrib->seqnum);
+	SET_TX_DESC_HWSEQ_EN_8723D(ptxdesc, 1);
+	SET_TX_DESC_USE_RATE_8723D(ptxdesc, 1);
+	SET_TX_DESC_DISABLE_FB_8723D(ptxdesc, 1);
+
+	if (pmp_priv->preamble) {
+		if (HwRateToMPTRate(pmp_priv->rateidx) <=  MPT_RATE_54M)
+			SET_TX_DESC_DATA_SHORT_8723D(ptxdesc, 1);
+	}
+
+	if (pmp_priv->bandwidth == CHANNEL_WIDTH_40)
+		SET_TX_DESC_DATA_BW_8723D(ptxdesc, 1);
+
+	SET_TX_DESC_TX_RATE_8723D(ptxdesc, pmp_priv->rateidx);
+
+	SET_TX_DESC_DATA_RATE_FB_LIMIT_8723D(ptxdesc, 0x1F);
+	SET_TX_DESC_RTS_RATE_FB_LIMIT_8723D(ptxdesc, 0xF);
+}
+#endif
+
+#if defined(CONFIG_RTL8710B)
+void fill_tx_desc_8710b(PADAPTER padapter)
+{
+	struct mp_priv *pmp_priv = &padapter->mppriv;
+	struct pkt_attrib *pattrib = &(pmp_priv->tx.attrib);
+	u8 *ptxdesc = pmp_priv->tx.desc;
+
+	SET_TX_DESC_BK_8710B(ptxdesc, 1);
+	SET_TX_DESC_MACID_8710B(ptxdesc, pattrib->mac_id);
+	SET_TX_DESC_QUEUE_SEL_8710B(ptxdesc, pattrib->qsel);
+
+	SET_TX_DESC_RATE_ID_8710B(ptxdesc, pattrib->raid);
+	SET_TX_DESC_SEQ_8710B(ptxdesc, pattrib->seqnum);
+	SET_TX_DESC_HWSEQ_EN_8710B(ptxdesc, 1);
+	SET_TX_DESC_USE_RATE_8710B(ptxdesc, 1);
+	SET_TX_DESC_DISABLE_FB_8710B(ptxdesc, 1);
+
+	if (pmp_priv->preamble) {
+		if (HwRateToMPTRate(pmp_priv->rateidx) <=  MPT_RATE_54M)
+			SET_TX_DESC_DATA_SHORT_8710B(ptxdesc, 1);
+	}
+
+	if (pmp_priv->bandwidth == CHANNEL_WIDTH_40)
+		SET_TX_DESC_DATA_BW_8710B(ptxdesc, 1);
+
+	SET_TX_DESC_TX_RATE_8710B(ptxdesc, pmp_priv->rateidx);
+
+	SET_TX_DESC_DATA_RATE_FB_LIMIT_8710B(ptxdesc, 0x1F);
+	SET_TX_DESC_RTS_RATE_FB_LIMIT_8710B(ptxdesc, 0xF);
+}
+#endif
+
+#if defined(CONFIG_RTL8192F)
+void fill_tx_desc_8192f(PADAPTER padapter)
+{
+	struct mp_priv *pmp_priv = &padapter->mppriv;
+	struct pkt_attrib *pattrib = &(pmp_priv->tx.attrib);
+	u8 *ptxdesc = pmp_priv->tx.desc;
+
+	SET_TX_DESC_BK_8192F(ptxdesc, 1);
+	SET_TX_DESC_MACID_8192F(ptxdesc, pattrib->mac_id);
+	SET_TX_DESC_QUEUE_SEL_8192F(ptxdesc, pattrib->qsel);
+
+	SET_TX_DESC_RATE_ID_8192F(ptxdesc, pattrib->raid);
+	SET_TX_DESC_SEQ_8192F(ptxdesc, pattrib->seqnum);
+	SET_TX_DESC_HWSEQ_EN_8192F(ptxdesc, 1);
+	SET_TX_DESC_USE_RATE_8192F(ptxdesc, 1);
+	SET_TX_DESC_DISABLE_FB_8192F(ptxdesc, 1);
+
+	if (pmp_priv->preamble) {
+		if (HwRateToMPTRate(pmp_priv->rateidx) <=  MPT_RATE_54M)
+			SET_TX_DESC_DATA_SHORT_8192F(ptxdesc, 1);
+	}
+
+	if (pmp_priv->bandwidth == CHANNEL_WIDTH_40)
+		SET_TX_DESC_DATA_BW_8192F(ptxdesc, 1);
+
+	SET_TX_DESC_TX_RATE_8192F(ptxdesc, pmp_priv->rateidx);
+
+	SET_TX_DESC_DATA_RATE_FB_LIMIT_8192F(ptxdesc, 0x1F);
+	SET_TX_DESC_RTS_RATE_FB_LIMIT_8192F(ptxdesc, 0xF);
+}
+
+#endif
+static void Rtw_MPSetMacTxEDCA(PADAPTER padapter)
+{
+
+	rtw_write32(padapter, 0x508 , 0x00a422); /* Disable EDCA BE Txop for MP pkt tx adjust Packet interval */
+	/* RTW_INFO("%s:write 0x508~~~~~~ 0x%x\n", __func__,rtw_read32(padapter, 0x508)); */
+	phy_set_mac_reg(padapter, 0x458 , bMaskDWord , 0x0);
+	/*RTW_INFO("%s()!!!!! 0x460 = 0x%x\n" ,__func__, phy_query_bb_reg(padapter, 0x460, bMaskDWord));*/
+	phy_set_mac_reg(padapter, 0x460 , bMaskLWord , 0x0); /* fast EDCA queue packet interval & time out value*/
+	/*phy_set_mac_reg(padapter, ODM_EDCA_VO_PARAM ,bMaskLWord , 0x431C);*/
+	/*phy_set_mac_reg(padapter, ODM_EDCA_BE_PARAM ,bMaskLWord , 0x431C);*/
+	/*phy_set_mac_reg(padapter, ODM_EDCA_BK_PARAM ,bMaskLWord , 0x431C);*/
+	RTW_INFO("%s()!!!!! 0x460 = 0x%x\n" , __func__, phy_query_bb_reg(padapter, 0x460, bMaskDWord));
+
+}
+
+void SetPacketTx(PADAPTER padapter)
+{
+	u8 *ptr, *pkt_start, *pkt_end;
+	u32 pkt_size, i;
+	struct rtw_ieee80211_hdr *hdr;
+	u8 payload;
+	s32 bmcast;
+	struct pkt_attrib *pattrib;
+	struct mp_priv *pmp_priv;
+
+	pmp_priv = &padapter->mppriv;
+
+	if (pmp_priv->tx.stop)
+		return;
+	pmp_priv->tx.sended = 0;
+	pmp_priv->tx.stop = 0;
+	pmp_priv->tx_pktcount = 0;
+
+	/* 3 1. update_attrib() */
+	pattrib = &pmp_priv->tx.attrib;
+	_rtw_memcpy(pattrib->src, adapter_mac_addr(padapter), ETH_ALEN);
+	_rtw_memcpy(pattrib->ta, pattrib->src, ETH_ALEN);
+	_rtw_memcpy(pattrib->ra, pattrib->dst, ETH_ALEN);
+	bmcast = IS_MCAST(pattrib->ra);
+	if (bmcast)
+		pattrib->psta = rtw_get_bcmc_stainfo(padapter);
+	else
+		pattrib->psta = rtw_get_stainfo(&padapter->stapriv, get_bssid(&padapter->mlmepriv));
+
+	pattrib->mac_id = pattrib->psta->cmn.mac_id;
+	pattrib->mbssid = 0;
+
+	pattrib->last_txcmdsz = pattrib->hdrlen + pattrib->pktlen;
+
+	/* 3 2. allocate xmit buffer */
+	pkt_size = pattrib->last_txcmdsz;
+
+	if (pmp_priv->tx.pallocated_buf)
+		rtw_mfree(pmp_priv->tx.pallocated_buf, pmp_priv->tx.buf_size);
+	pmp_priv->tx.write_size = pkt_size;
+	pmp_priv->tx.buf_size = pkt_size + XMITBUF_ALIGN_SZ;
+	pmp_priv->tx.pallocated_buf = rtw_zmalloc(pmp_priv->tx.buf_size);
+	if (pmp_priv->tx.pallocated_buf == NULL) {
+		RTW_INFO("%s: malloc(%d) fail!!\n", __func__, pmp_priv->tx.buf_size);
+		return;
+	}
+	pmp_priv->tx.buf = (u8 *)N_BYTE_ALIGMENT((SIZE_PTR)(pmp_priv->tx.pallocated_buf), XMITBUF_ALIGN_SZ);
+	ptr = pmp_priv->tx.buf;
+
+	_rtw_memset(pmp_priv->tx.desc, 0, TXDESC_SIZE);
+	pkt_start = ptr;
+	pkt_end = pkt_start + pkt_size;
+
+	/* 3 3. init TX descriptor */
+#if defined(CONFIG_RTL8188E)
+	if (IS_HARDWARE_TYPE_8188E(padapter))
+		fill_tx_desc_8188e(padapter);
+#endif
+
+#if defined(CONFIG_RTL8814A)
+	if (IS_HARDWARE_TYPE_8814A(padapter))
+		fill_tx_desc_8814a(padapter);
+#endif /* defined(CONFIG_RTL8814A) */
+
+#if defined(CONFIG_RTL8822B)
+	if (IS_HARDWARE_TYPE_8822B(padapter))
+		rtl8822b_prepare_mp_txdesc(padapter, pmp_priv);
+#endif /* CONFIG_RTL8822B */
+
+#if defined(CONFIG_RTL8821C)
+	if (IS_HARDWARE_TYPE_8821C(padapter))
+		rtl8821c_prepare_mp_txdesc(padapter, pmp_priv);
+#endif /* CONFIG_RTL8821C */
+
+#if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A)
+	if (IS_HARDWARE_TYPE_8812(padapter) || IS_HARDWARE_TYPE_8821(padapter))
+		fill_tx_desc_8812a(padapter);
+#endif
+
+#if defined(CONFIG_RTL8192E)
+	if (IS_HARDWARE_TYPE_8192E(padapter))
+		fill_tx_desc_8192e(padapter);
+#endif
+#if defined(CONFIG_RTL8723B)
+	if (IS_HARDWARE_TYPE_8723B(padapter))
+		fill_tx_desc_8723b(padapter);
+#endif
+#if defined(CONFIG_RTL8703B)
+	if (IS_HARDWARE_TYPE_8703B(padapter))
+		fill_tx_desc_8703b(padapter);
+#endif
+
+#if defined(CONFIG_RTL8188F)
+	if (IS_HARDWARE_TYPE_8188F(padapter))
+		fill_tx_desc_8188f(padapter);
+#endif
+
+#if defined(CONFIG_RTL8188GTV)
+	if (IS_HARDWARE_TYPE_8188GTV(padapter))
+		fill_tx_desc_8188gtv(padapter);
+#endif
+
+#if defined(CONFIG_RTL8723D)
+	if (IS_HARDWARE_TYPE_8723D(padapter))
+		fill_tx_desc_8723d(padapter);
+#endif
+#if defined(CONFIG_RTL8192F)
+		if (IS_HARDWARE_TYPE_8192F(padapter))
+			fill_tx_desc_8192f(padapter);
+#endif
+
+#if defined(CONFIG_RTL8710B)
+	if (IS_HARDWARE_TYPE_8710B(padapter))
+		fill_tx_desc_8710b(padapter);
+#endif
+
+	/* 3 4. make wlan header, make_wlanhdr() */
+	hdr = (struct rtw_ieee80211_hdr *)pkt_start;
+	set_frame_sub_type(&hdr->frame_ctl, pattrib->subtype);
+
+	_rtw_memcpy(hdr->addr1, pattrib->dst, ETH_ALEN); /* DA */
+	_rtw_memcpy(hdr->addr2, pattrib->src, ETH_ALEN); /* SA */
+	_rtw_memcpy(hdr->addr3, get_bssid(&padapter->mlmepriv), ETH_ALEN); /* RA, BSSID */
+
+	/* 3 5. make payload */
+	ptr = pkt_start + pattrib->hdrlen;
+
+	switch (pmp_priv->tx.payload) {
+	case 0:
+		payload = 0x00;
+		break;
+	case 1:
+		payload = 0x5a;
+		break;
+	case 2:
+		payload = 0xa5;
+		break;
+	case 3:
+		payload = 0xff;
+		break;
+	default:
+		payload = 0x00;
+		break;
+	}
+	pmp_priv->TXradomBuffer = rtw_zmalloc(4096);
+	if (pmp_priv->TXradomBuffer == NULL) {
+		RTW_INFO("mp create random buffer fail!\n");
+		goto exit;
+	}
+
+
+	for (i = 0; i < 4096; i++)
+		pmp_priv->TXradomBuffer[i] = rtw_random32() % 0xFF;
+
+	/* startPlace = (u32)(rtw_random32() % 3450); */
+	_rtw_memcpy(ptr, pmp_priv->TXradomBuffer, pkt_end - ptr);
+	/* _rtw_memset(ptr, payload, pkt_end - ptr); */
+	rtw_mfree(pmp_priv->TXradomBuffer, 4096);
+
+	/* 3 6. start thread */
+#ifdef PLATFORM_LINUX
+	pmp_priv->tx.PktTxThread = kthread_run(mp_xmit_packet_thread, pmp_priv, "RTW_MP_THREAD");
+	if (IS_ERR(pmp_priv->tx.PktTxThread)) {
+		RTW_ERR("Create PktTx Thread Fail !!!!!\n");
+		pmp_priv->tx.PktTxThread = NULL;
+	}
+#endif
+#ifdef PLATFORM_FREEBSD
+	{
+		struct proc *p;
+		struct thread *td;
+		pmp_priv->tx.PktTxThread = kproc_kthread_add(mp_xmit_packet_thread, pmp_priv,
+			&p, &td, RFHIGHPID, 0, "MPXmitThread", "MPXmitThread");
+
+		if (pmp_priv->tx.PktTxThread < 0)
+			RTW_INFO("Create PktTx Thread Fail !!!!!\n");
+	}
+#endif
+
+	Rtw_MPSetMacTxEDCA(padapter);
+exit:
+	return;
+}
+
+void SetPacketRx(PADAPTER pAdapter, u8 bStartRx, u8 bAB)
+{
+	PHAL_DATA_TYPE pHalData = GET_HAL_DATA(pAdapter);
+	struct mp_priv *pmppriv = &pAdapter->mppriv;
+
+
+	if (bStartRx) {
+#ifdef CONFIG_RTL8723B
+		phy_set_mac_reg(pAdapter, 0xe70, BIT23 | BIT22, 0x3); /* Power on adc  (in RX_WAIT_CCA state) */
+		write_bbreg(pAdapter, 0xa01, BIT0, bDisable);/* improve Rx performance by jerry	 */
+#endif
+		pHalData->ReceiveConfig = RCR_AAP | RCR_APM | RCR_AM | RCR_AMF | RCR_HTC_LOC_CTRL;
+		pHalData->ReceiveConfig |= RCR_ACRC32;
+		pHalData->ReceiveConfig |= RCR_APP_PHYST_RXFF | RCR_APP_ICV | RCR_APP_MIC;
+
+		if (pmppriv->bSetRxBssid == _TRUE) {
+			RTW_INFO("%s: pmppriv->network_macaddr=" MAC_FMT "\n", __func__,
+				 MAC_ARG(pmppriv->network_macaddr));
+			pHalData->ReceiveConfig = 0;
+			pHalData->ReceiveConfig |= RCR_CBSSID_DATA | RCR_CBSSID_BCN |RCR_APM | RCR_AM | RCR_AB |RCR_AMF;
+			pHalData->ReceiveConfig |= RCR_APP_PHYST_RXFF;
+
+#if defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C)
+			write_bbreg(pAdapter, 0x550, BIT3, bEnable);
+#endif
+			rtw_write16(pAdapter, REG_RXFLTMAP0, 0xFFEF); /* REG_RXFLTMAP0 (RX Filter Map Group 0) */
+			pmppriv->brx_filter_beacon = _TRUE;
+
+		} else {
+			pHalData->ReceiveConfig |= RCR_ADF;
+			/* Accept all data frames */
+			rtw_write16(pAdapter, REG_RXFLTMAP2, 0xFFFF);
+		}
+
+		if (bAB)
+			pHalData->ReceiveConfig |= RCR_AB;
+	} else {
+#ifdef CONFIG_RTL8723B
+		phy_set_mac_reg(pAdapter, 0xe70, BIT23 | BIT22, 0x00); /* Power off adc  (in RX_WAIT_CCA state)*/
+		write_bbreg(pAdapter, 0xa01, BIT0, bEnable);/* improve Rx performance by jerry	 */
+#endif
+		pHalData->ReceiveConfig = 0;
+		rtw_write16(pAdapter, REG_RXFLTMAP0, 0xFFFF); /* REG_RXFLTMAP0 (RX Filter Map Group 0) */
+	}
+
+	rtw_write32(pAdapter, REG_RCR, pHalData->ReceiveConfig);
+}
+
+void ResetPhyRxPktCount(PADAPTER pAdapter)
+{
+	u32 i, phyrx_set = 0;
+
+	for (i = 0; i <= 0xF; i++) {
+		phyrx_set = 0;
+		phyrx_set |= _RXERR_RPT_SEL(i);	/* select */
+		phyrx_set |= RXERR_RPT_RST;	/* set counter to zero */
+		rtw_write32(pAdapter, REG_RXERR_RPT, phyrx_set);
+	}
+}
+
+static u32 GetPhyRxPktCounts(PADAPTER pAdapter, u32 selbit)
+{
+	/* selection */
+	u32 phyrx_set = 0, count = 0;
+
+	phyrx_set = _RXERR_RPT_SEL(selbit & 0xF);
+	rtw_write32(pAdapter, REG_RXERR_RPT, phyrx_set);
+
+	/* Read packet count */
+	count = rtw_read32(pAdapter, REG_RXERR_RPT) & RXERR_COUNTER_MASK;
+
+	return count;
+}
+
+u32 GetPhyRxPktReceived(PADAPTER pAdapter)
+{
+	u32 OFDM_cnt = 0, CCK_cnt = 0, HT_cnt = 0;
+
+	OFDM_cnt = GetPhyRxPktCounts(pAdapter, RXERR_TYPE_OFDM_MPDU_OK);
+	CCK_cnt = GetPhyRxPktCounts(pAdapter, RXERR_TYPE_CCK_MPDU_OK);
+	HT_cnt = GetPhyRxPktCounts(pAdapter, RXERR_TYPE_HT_MPDU_OK);
+
+	return OFDM_cnt + CCK_cnt + HT_cnt;
+}
+
+u32 GetPhyRxPktCRC32Error(PADAPTER pAdapter)
+{
+	u32 OFDM_cnt = 0, CCK_cnt = 0, HT_cnt = 0;
+
+	OFDM_cnt = GetPhyRxPktCounts(pAdapter, RXERR_TYPE_OFDM_MPDU_FAIL);
+	CCK_cnt = GetPhyRxPktCounts(pAdapter, RXERR_TYPE_CCK_MPDU_FAIL);
+	HT_cnt = GetPhyRxPktCounts(pAdapter, RXERR_TYPE_HT_MPDU_FAIL);
+
+	return OFDM_cnt + CCK_cnt + HT_cnt;
+}
+
+struct psd_init_regs {
+	/* 3 wire */
+	int reg_88c;
+	int reg_c00;
+	int reg_e00;
+	int reg_1800;
+	int reg_1a00;
+	/* cck */
+	int reg_800;
+	int reg_808;
+};
+
+static int rtw_mp_psd_init(PADAPTER padapter, struct psd_init_regs *regs)
+{
+	HAL_DATA_TYPE	*phal_data	= GET_HAL_DATA(padapter);
+
+	switch (phal_data->rf_type) {
+	/* 1R */
+	case RF_1T1R:
+		if (hal_chk_proto_cap(padapter, PROTO_CAP_11AC)) {
+			/* 11AC 1R PSD Setting 3wire & cck off */
+			regs->reg_c00 = rtw_read32(padapter, 0xC00);
+			phy_set_bb_reg(padapter, 0xC00, 0x3, 0x00);
+			regs->reg_808 = rtw_read32(padapter, 0x808);
+			phy_set_bb_reg(padapter, 0x808, 0x10000000, 0x0);
+		} else {
+			/* 11N 3-wire off 1 */
+			regs->reg_88c = rtw_read32(padapter, 0x88C);
+			phy_set_bb_reg(padapter, 0x88C, 0x300000, 0x3);
+			/* 11N CCK off */
+			regs->reg_800 = rtw_read32(padapter, 0x800);
+			phy_set_bb_reg(padapter, 0x800, 0x1000000, 0x0);
+		}
+	break;
+
+	/* 2R */
+	case RF_1T2R:
+	case RF_2T2R:
+		if (hal_chk_proto_cap(padapter, PROTO_CAP_11AC)) {
+			/* 11AC 2R PSD Setting 3wire & cck off */
+			regs->reg_c00 = rtw_read32(padapter, 0xC00);
+			regs->reg_e00 = rtw_read32(padapter, 0xE00);
+			phy_set_bb_reg(padapter, 0xC00, 0x3, 0x00);
+			phy_set_bb_reg(padapter, 0xE00, 0x3, 0x00);
+			regs->reg_808 = rtw_read32(padapter, 0x808);
+			phy_set_bb_reg(padapter, 0x808, 0x10000000, 0x0);
+		} else {
+			/* 11N 3-wire off 2 */
+			regs->reg_88c = rtw_read32(padapter, 0x88C);
+			phy_set_bb_reg(padapter, 0x88C, 0xF00000, 0xF);
+			/* 11N CCK off */
+			regs->reg_800 = rtw_read32(padapter, 0x800);
+			phy_set_bb_reg(padapter, 0x800, 0x1000000, 0x0);
+		}
+	break;
+
+	/* 3R */
+	case RF_2T3R:
+	case RF_3T3R:
+		if (hal_chk_proto_cap(padapter, PROTO_CAP_11AC)) {
+			/* 11AC 3R PSD Setting 3wire & cck off */
+			regs->reg_c00 = rtw_read32(padapter, 0xC00);
+			regs->reg_e00 = rtw_read32(padapter, 0xE00);
+			regs->reg_1800 = rtw_read32(padapter, 0x1800);
+			phy_set_bb_reg(padapter, 0xC00, 0x3, 0x00);
+			phy_set_bb_reg(padapter, 0xE00, 0x3, 0x00);
+			phy_set_bb_reg(padapter, 0x1800, 0x3, 0x00);
+			regs->reg_808 = rtw_read32(padapter, 0x808);
+			phy_set_bb_reg(padapter, 0x808, 0x10000000, 0x0);
+		} else {
+			RTW_ERR("%s: 11n don't support 3R\n", __func__);
+			return -1;
+		}
+		break;
+
+	/* 4R */
+	case RF_2T4R:
+	case RF_3T4R:
+	case RF_4T4R:
+		if (hal_chk_proto_cap(padapter, PROTO_CAP_11AC)) {
+			/* 11AC 4R PSD Setting 3wire & cck off */
+			regs->reg_c00 = rtw_read32(padapter, 0xC00);
+			regs->reg_e00 = rtw_read32(padapter, 0xE00);
+			regs->reg_1800 = rtw_read32(padapter, 0x1800);
+			regs->reg_1a00 = rtw_read32(padapter, 0x1A00);
+			phy_set_bb_reg(padapter, 0xC00, 0x3, 0x00);
+			phy_set_bb_reg(padapter, 0xE00, 0x3, 0x00);
+			phy_set_bb_reg(padapter, 0x1800, 0x3, 0x00);
+			phy_set_bb_reg(padapter, 0x1A00, 0x3, 0x00);
+			regs->reg_808 = rtw_read32(padapter, 0x808);
+			phy_set_bb_reg(padapter, 0x808, 0x10000000, 0x0);
+		} else {
+			RTW_ERR("%s: 11n don't support 4R\n", __func__);
+			return -1;
+		}
+		break;
+
+	default:
+		RTW_ERR("%s: unknown %d rf type\n", __func__, phal_data->rf_type);
+		return -1;
+	}
+
+	/* Set PSD points, 0=128, 1=256, 2=512, 3=1024 */
+	if (hal_chk_proto_cap(padapter, PROTO_CAP_11AC))
+		phy_set_bb_reg(padapter, 0x910, 0xC000, 3);
+	else
+		phy_set_bb_reg(padapter, 0x808, 0xC000, 3);
+
+	RTW_INFO("%s: set %d rf type done\n", __func__, phal_data->rf_type);
+	return 0;
+}
+
+static int rtw_mp_psd_close(PADAPTER padapter, struct psd_init_regs *regs)
+{
+	HAL_DATA_TYPE	*phal_data	= GET_HAL_DATA(padapter);
+
+
+	if (!hal_chk_proto_cap(padapter, PROTO_CAP_11AC)) {
+		/* 11n 3wire restore */
+		rtw_write32(padapter, 0x88C, regs->reg_88c);
+		/* 11n cck restore */
+		rtw_write32(padapter, 0x800, regs->reg_800);
+		RTW_INFO("%s: restore %d rf type\n", __func__, phal_data->rf_type);
+		return 0;
+	}
+
+	/* 11ac 3wire restore */
+	switch (phal_data->rf_type) {
+	case RF_1T1R:
+		rtw_write32(padapter, 0xC00, regs->reg_c00);
+		break;
+	case RF_1T2R:
+	case RF_2T2R:
+		rtw_write32(padapter, 0xC00, regs->reg_c00);
+		rtw_write32(padapter, 0xE00, regs->reg_e00);
+		break;
+	case RF_2T3R:
+	case RF_3T3R:
+		rtw_write32(padapter, 0xC00, regs->reg_c00);
+		rtw_write32(padapter, 0xE00, regs->reg_e00);
+		rtw_write32(padapter, 0x1800, regs->reg_1800);
+		break;
+	case RF_2T4R:
+	case RF_3T4R:
+	case RF_4T4R:
+		rtw_write32(padapter, 0xC00, regs->reg_c00);
+		rtw_write32(padapter, 0xE00, regs->reg_e00);
+		rtw_write32(padapter, 0x1800, regs->reg_1800);
+		rtw_write32(padapter, 0x1A00, regs->reg_1a00);
+		break;
+	default:
+		RTW_WARN("%s: unknown %d rf type\n", __func__, phal_data->rf_type);
+		break;
+	}
+
+	/* 11ac cck restore */
+	rtw_write32(padapter, 0x808, regs->reg_808);
+	RTW_INFO("%s: restore %d rf type done\n", __func__, phal_data->rf_type);
+	return 0;
+}
+
+/* reg 0x808[9:0]: FFT data x
+ * reg 0x808[22]:  0  -->  1  to get 1 FFT data y
+ * reg 0x8B4[15:0]: FFT data y report */
+static u32 rtw_GetPSDData(PADAPTER pAdapter, u32 point)
+{
+	u32 psd_val = 0;
+
+#if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A) || defined(CONFIG_RTL8814A) || defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C)
+	u16 psd_reg = 0x910;
+	u16 psd_regL = 0xF44;
+#else
+	u16 psd_reg = 0x808;
+	u16 psd_regL = 0x8B4;
+#endif
+
+	psd_val = rtw_read32(pAdapter, psd_reg);
+
+	psd_val &= 0xFFBFFC00;
+	psd_val |= point;
+
+	rtw_write32(pAdapter, psd_reg, psd_val);
+	rtw_mdelay_os(1);
+	psd_val |= 0x00400000;
+
+	rtw_write32(pAdapter, psd_reg, psd_val);
+	rtw_mdelay_os(1);
+
+	psd_val = rtw_read32(pAdapter, psd_regL);
+#if defined(CONFIG_RTL8821C)
+	psd_val = (psd_val & 0x00FFFFFF) / 32;
+#else
+	psd_val &= 0x0000FFFF;
+#endif
+
+	return psd_val;
+}
+
+/*
+ * pts	start_point_min		stop_point_max
+ * 128	64			64 + 128 = 192
+ * 256	128			128 + 256 = 384
+ * 512	256			256 + 512 = 768
+ * 1024	512			512 + 1024 = 1536
+ *
+ */
+u32 mp_query_psd(PADAPTER pAdapter, u8 *data)
+{
+	u32 i, psd_pts = 0, psd_start = 0, psd_stop = 0;
+	u32 psd_data = 0;
+	struct psd_init_regs regs = {};
+	int psd_analysis = 0;
+
+#ifdef PLATFORM_LINUX
+	if (!netif_running(pAdapter->pnetdev)) {
+		return 0;
+	}
+#endif
+
+	if (check_fwstate(&pAdapter->mlmepriv, WIFI_MP_STATE) == _FALSE) {
+		return 0;
+	}
+
+	if (strlen(data) == 0) { /* default value */
+		psd_pts = 128;
+		psd_start = 64;
+		psd_stop = 128;
+	} else if (strncmp(data, "analysis,", 9) == 0) {
+		if (rtw_mp_psd_init(pAdapter, &regs) != 0)
+			return 0;
+		psd_analysis = 1;
+		sscanf(data + 9, "pts=%d,start=%d,stop=%d", &psd_pts, &psd_start, &psd_stop);
+	} else
+		sscanf(data, "pts=%d,start=%d,stop=%d", &psd_pts, &psd_start, &psd_stop);
+
+	data[0] = '\0';
+
+	i = psd_start;
+	while (i < psd_stop) {
+		if (i >= psd_pts)
+			psd_data = rtw_GetPSDData(pAdapter, i - psd_pts);
+		else
+			psd_data = rtw_GetPSDData(pAdapter, i);
+		sprintf(data, "%s%x ", data, psd_data);
+		i++;
+	}
+
+#ifdef CONFIG_LONG_DELAY_ISSUE
+	rtw_msleep_os(100);
+#else
+	rtw_mdelay_os(100);
+#endif
+
+	if (psd_analysis)
+		rtw_mp_psd_close(pAdapter, &regs);
+
+	return strlen(data) + 1;
+}
+
+
+#if 0
+void _rtw_mp_xmit_priv(struct xmit_priv *pxmitpriv)
+{
+	int i, res;
+	_adapter *padapter = pxmitpriv->adapter;
+	struct xmit_frame	*pxmitframe = (struct xmit_frame *) pxmitpriv->pxmit_frame_buf;
+	struct xmit_buf *pxmitbuf = (struct xmit_buf *)pxmitpriv->pxmitbuf;
+
+	u32 max_xmit_extbuf_size = MAX_XMIT_EXTBUF_SZ;
+	u32 num_xmit_extbuf = NR_XMIT_EXTBUFF;
+	if (padapter->registrypriv.mp_mode == 0) {
+		max_xmit_extbuf_size = MAX_XMIT_EXTBUF_SZ;
+		num_xmit_extbuf = NR_XMIT_EXTBUFF;
+	} else {
+		max_xmit_extbuf_size = 6000;
+		num_xmit_extbuf = 8;
+	}
+
+	pxmitbuf = (struct xmit_buf *)pxmitpriv->pxmit_extbuf;
+	for (i = 0; i < num_xmit_extbuf; i++) {
+		rtw_os_xmit_resource_free(padapter, pxmitbuf, (max_xmit_extbuf_size + XMITBUF_ALIGN_SZ), _FALSE);
+
+		pxmitbuf++;
+	}
+
+	if (pxmitpriv->pallocated_xmit_extbuf)
+		rtw_vmfree(pxmitpriv->pallocated_xmit_extbuf, num_xmit_extbuf * sizeof(struct xmit_buf) + 4);
+
+	if (padapter->registrypriv.mp_mode == 0) {
+		max_xmit_extbuf_size = 6000;
+		num_xmit_extbuf = 8;
+	} else {
+		max_xmit_extbuf_size = MAX_XMIT_EXTBUF_SZ;
+		num_xmit_extbuf = NR_XMIT_EXTBUFF;
+	}
+
+	/* Init xmit extension buff */
+	_rtw_init_queue(&pxmitpriv->free_xmit_extbuf_queue);
+
+	pxmitpriv->pallocated_xmit_extbuf = rtw_zvmalloc(num_xmit_extbuf * sizeof(struct xmit_buf) + 4);
+
+	if (pxmitpriv->pallocated_xmit_extbuf  == NULL) {
+		res = _FAIL;
+		goto exit;
+	}
+
+	pxmitpriv->pxmit_extbuf = (u8 *)N_BYTE_ALIGMENT((SIZE_PTR)(pxmitpriv->pallocated_xmit_extbuf), 4);
+
+	pxmitbuf = (struct xmit_buf *)pxmitpriv->pxmit_extbuf;
+
+	for (i = 0; i < num_xmit_extbuf; i++) {
+		_rtw_init_listhead(&pxmitbuf->list);
+
+		pxmitbuf->priv_data = NULL;
+		pxmitbuf->padapter = padapter;
+		pxmitbuf->buf_tag = XMITBUF_MGNT;
+
+		res = rtw_os_xmit_resource_alloc(padapter, pxmitbuf, max_xmit_extbuf_size + XMITBUF_ALIGN_SZ, _TRUE);
+		if (res == _FAIL) {
+			res = _FAIL;
+			goto exit;
+		}
+
+#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
+		pxmitbuf->phead = pxmitbuf->pbuf;
+		pxmitbuf->pend = pxmitbuf->pbuf + max_xmit_extbuf_size;
+		pxmitbuf->len = 0;
+		pxmitbuf->pdata = pxmitbuf->ptail = pxmitbuf->phead;
+#endif
+
+		rtw_list_insert_tail(&pxmitbuf->list, &(pxmitpriv->free_xmit_extbuf_queue.queue));
+#ifdef DBG_XMIT_BUF_EXT
+		pxmitbuf->no = i;
+#endif
+		pxmitbuf++;
+
+	}
+
+	pxmitpriv->free_xmit_extbuf_cnt = num_xmit_extbuf;
+
+exit:
+	;
+}
+#endif
+
+u8
+mpt_to_mgnt_rate(
+	IN	ULONG	MptRateIdx
+)
+{
+	/* Mapped to MGN_XXX defined in MgntGen.h */
+	switch (MptRateIdx) {
+	/* CCK rate. */
+	case	MPT_RATE_1M:
+		return MGN_1M;
+	case	MPT_RATE_2M:
+		return MGN_2M;
+	case	MPT_RATE_55M:
+		return MGN_5_5M;
+	case	MPT_RATE_11M:
+		return MGN_11M;
+
+	/* OFDM rate. */
+	case	MPT_RATE_6M:
+		return MGN_6M;
+	case	MPT_RATE_9M:
+		return MGN_9M;
+	case	MPT_RATE_12M:
+		return MGN_12M;
+	case	MPT_RATE_18M:
+		return MGN_18M;
+	case	MPT_RATE_24M:
+		return MGN_24M;
+	case	MPT_RATE_36M:
+		return MGN_36M;
+	case	MPT_RATE_48M:
+		return MGN_48M;
+	case	MPT_RATE_54M:
+		return MGN_54M;
+
+	/* HT rate. */
+	case	MPT_RATE_MCS0:
+		return MGN_MCS0;
+	case	MPT_RATE_MCS1:
+		return MGN_MCS1;
+	case	MPT_RATE_MCS2:
+		return MGN_MCS2;
+	case	MPT_RATE_MCS3:
+		return MGN_MCS3;
+	case	MPT_RATE_MCS4:
+		return MGN_MCS4;
+	case	MPT_RATE_MCS5:
+		return MGN_MCS5;
+	case	MPT_RATE_MCS6:
+		return MGN_MCS6;
+	case	MPT_RATE_MCS7:
+		return MGN_MCS7;
+	case	MPT_RATE_MCS8:
+		return MGN_MCS8;
+	case	MPT_RATE_MCS9:
+		return MGN_MCS9;
+	case	MPT_RATE_MCS10:
+		return MGN_MCS10;
+	case	MPT_RATE_MCS11:
+		return MGN_MCS11;
+	case	MPT_RATE_MCS12:
+		return MGN_MCS12;
+	case	MPT_RATE_MCS13:
+		return MGN_MCS13;
+	case	MPT_RATE_MCS14:
+		return MGN_MCS14;
+	case	MPT_RATE_MCS15:
+		return MGN_MCS15;
+	case	MPT_RATE_MCS16:
+		return MGN_MCS16;
+	case	MPT_RATE_MCS17:
+		return MGN_MCS17;
+	case	MPT_RATE_MCS18:
+		return MGN_MCS18;
+	case	MPT_RATE_MCS19:
+		return MGN_MCS19;
+	case	MPT_RATE_MCS20:
+		return MGN_MCS20;
+	case	MPT_RATE_MCS21:
+		return MGN_MCS21;
+	case	MPT_RATE_MCS22:
+		return MGN_MCS22;
+	case	MPT_RATE_MCS23:
+		return MGN_MCS23;
+	case	MPT_RATE_MCS24:
+		return MGN_MCS24;
+	case	MPT_RATE_MCS25:
+		return MGN_MCS25;
+	case	MPT_RATE_MCS26:
+		return MGN_MCS26;
+	case	MPT_RATE_MCS27:
+		return MGN_MCS27;
+	case	MPT_RATE_MCS28:
+		return MGN_MCS28;
+	case	MPT_RATE_MCS29:
+		return MGN_MCS29;
+	case	MPT_RATE_MCS30:
+		return MGN_MCS30;
+	case	MPT_RATE_MCS31:
+		return MGN_MCS31;
+
+	/* VHT rate. */
+	case	MPT_RATE_VHT1SS_MCS0:
+		return MGN_VHT1SS_MCS0;
+	case	MPT_RATE_VHT1SS_MCS1:
+		return MGN_VHT1SS_MCS1;
+	case	MPT_RATE_VHT1SS_MCS2:
+		return MGN_VHT1SS_MCS2;
+	case	MPT_RATE_VHT1SS_MCS3:
+		return MGN_VHT1SS_MCS3;
+	case	MPT_RATE_VHT1SS_MCS4:
+		return MGN_VHT1SS_MCS4;
+	case	MPT_RATE_VHT1SS_MCS5:
+		return MGN_VHT1SS_MCS5;
+	case	MPT_RATE_VHT1SS_MCS6:
+		return MGN_VHT1SS_MCS6;
+	case	MPT_RATE_VHT1SS_MCS7:
+		return MGN_VHT1SS_MCS7;
+	case	MPT_RATE_VHT1SS_MCS8:
+		return MGN_VHT1SS_MCS8;
+	case	MPT_RATE_VHT1SS_MCS9:
+		return MGN_VHT1SS_MCS9;
+	case	MPT_RATE_VHT2SS_MCS0:
+		return MGN_VHT2SS_MCS0;
+	case	MPT_RATE_VHT2SS_MCS1:
+		return MGN_VHT2SS_MCS1;
+	case	MPT_RATE_VHT2SS_MCS2:
+		return MGN_VHT2SS_MCS2;
+	case	MPT_RATE_VHT2SS_MCS3:
+		return MGN_VHT2SS_MCS3;
+	case	MPT_RATE_VHT2SS_MCS4:
+		return MGN_VHT2SS_MCS4;
+	case	MPT_RATE_VHT2SS_MCS5:
+		return MGN_VHT2SS_MCS5;
+	case	MPT_RATE_VHT2SS_MCS6:
+		return MGN_VHT2SS_MCS6;
+	case	MPT_RATE_VHT2SS_MCS7:
+		return MGN_VHT2SS_MCS7;
+	case	MPT_RATE_VHT2SS_MCS8:
+		return MGN_VHT2SS_MCS8;
+	case	MPT_RATE_VHT2SS_MCS9:
+		return MGN_VHT2SS_MCS9;
+	case	MPT_RATE_VHT3SS_MCS0:
+		return MGN_VHT3SS_MCS0;
+	case	MPT_RATE_VHT3SS_MCS1:
+		return MGN_VHT3SS_MCS1;
+	case	MPT_RATE_VHT3SS_MCS2:
+		return MGN_VHT3SS_MCS2;
+	case	MPT_RATE_VHT3SS_MCS3:
+		return MGN_VHT3SS_MCS3;
+	case	MPT_RATE_VHT3SS_MCS4:
+		return MGN_VHT3SS_MCS4;
+	case	MPT_RATE_VHT3SS_MCS5:
+		return MGN_VHT3SS_MCS5;
+	case	MPT_RATE_VHT3SS_MCS6:
+		return MGN_VHT3SS_MCS6;
+	case	MPT_RATE_VHT3SS_MCS7:
+		return MGN_VHT3SS_MCS7;
+	case	MPT_RATE_VHT3SS_MCS8:
+		return MGN_VHT3SS_MCS8;
+	case	MPT_RATE_VHT3SS_MCS9:
+		return MGN_VHT3SS_MCS9;
+	case	MPT_RATE_VHT4SS_MCS0:
+		return MGN_VHT4SS_MCS0;
+	case	MPT_RATE_VHT4SS_MCS1:
+		return MGN_VHT4SS_MCS1;
+	case	MPT_RATE_VHT4SS_MCS2:
+		return MGN_VHT4SS_MCS2;
+	case	MPT_RATE_VHT4SS_MCS3:
+		return MGN_VHT4SS_MCS3;
+	case	MPT_RATE_VHT4SS_MCS4:
+		return MGN_VHT4SS_MCS4;
+	case	MPT_RATE_VHT4SS_MCS5:
+		return MGN_VHT4SS_MCS5;
+	case	MPT_RATE_VHT4SS_MCS6:
+		return MGN_VHT4SS_MCS6;
+	case	MPT_RATE_VHT4SS_MCS7:
+		return MGN_VHT4SS_MCS7;
+	case	MPT_RATE_VHT4SS_MCS8:
+		return MGN_VHT4SS_MCS8;
+	case	MPT_RATE_VHT4SS_MCS9:
+		return MGN_VHT4SS_MCS9;
+
+	case	MPT_RATE_LAST:	/* fully automatiMGN_VHT2SS_MCS1;	 */
+	default:
+		RTW_INFO("<===mpt_to_mgnt_rate(), Invalid Rate: %d!!\n", MptRateIdx);
+		return 0x0;
+	}
+}
+
+
+u8 HwRateToMPTRate(u8 rate)
+{
+	u8	ret_rate = MGN_1M;
+
+	switch (rate) {
+	case DESC_RATE1M:
+		ret_rate = MPT_RATE_1M;
+		break;
+	case DESC_RATE2M:
+		ret_rate = MPT_RATE_2M;
+		break;
+	case DESC_RATE5_5M:
+		ret_rate = MPT_RATE_55M;
+		break;
+	case DESC_RATE11M:
+		ret_rate = MPT_RATE_11M;
+		break;
+	case DESC_RATE6M:
+		ret_rate = MPT_RATE_6M;
+		break;
+	case DESC_RATE9M:
+		ret_rate = MPT_RATE_9M;
+		break;
+	case DESC_RATE12M:
+		ret_rate = MPT_RATE_12M;
+		break;
+	case DESC_RATE18M:
+		ret_rate = MPT_RATE_18M;
+		break;
+	case DESC_RATE24M:
+		ret_rate = MPT_RATE_24M;
+		break;
+	case DESC_RATE36M:
+		ret_rate = MPT_RATE_36M;
+		break;
+	case DESC_RATE48M:
+		ret_rate = MPT_RATE_48M;
+		break;
+	case DESC_RATE54M:
+		ret_rate = MPT_RATE_54M;
+		break;
+	case DESC_RATEMCS0:
+		ret_rate = MPT_RATE_MCS0;
+		break;
+	case DESC_RATEMCS1:
+		ret_rate = MPT_RATE_MCS1;
+		break;
+	case DESC_RATEMCS2:
+		ret_rate = MPT_RATE_MCS2;
+		break;
+	case DESC_RATEMCS3:
+		ret_rate = MPT_RATE_MCS3;
+		break;
+	case DESC_RATEMCS4:
+		ret_rate = MPT_RATE_MCS4;
+		break;
+	case DESC_RATEMCS5:
+		ret_rate = MPT_RATE_MCS5;
+		break;
+	case DESC_RATEMCS6:
+		ret_rate = MPT_RATE_MCS6;
+		break;
+	case DESC_RATEMCS7:
+		ret_rate = MPT_RATE_MCS7;
+		break;
+	case DESC_RATEMCS8:
+		ret_rate = MPT_RATE_MCS8;
+		break;
+	case DESC_RATEMCS9:
+		ret_rate = MPT_RATE_MCS9;
+		break;
+	case DESC_RATEMCS10:
+		ret_rate = MPT_RATE_MCS10;
+		break;
+	case DESC_RATEMCS11:
+		ret_rate = MPT_RATE_MCS11;
+		break;
+	case DESC_RATEMCS12:
+		ret_rate = MPT_RATE_MCS12;
+		break;
+	case DESC_RATEMCS13:
+		ret_rate = MPT_RATE_MCS13;
+		break;
+	case DESC_RATEMCS14:
+		ret_rate = MPT_RATE_MCS14;
+		break;
+	case DESC_RATEMCS15:
+		ret_rate = MPT_RATE_MCS15;
+		break;
+	case DESC_RATEMCS16:
+		ret_rate = MPT_RATE_MCS16;
+		break;
+	case DESC_RATEMCS17:
+		ret_rate = MPT_RATE_MCS17;
+		break;
+	case DESC_RATEMCS18:
+		ret_rate = MPT_RATE_MCS18;
+		break;
+	case DESC_RATEMCS19:
+		ret_rate = MPT_RATE_MCS19;
+		break;
+	case DESC_RATEMCS20:
+		ret_rate = MPT_RATE_MCS20;
+		break;
+	case DESC_RATEMCS21:
+		ret_rate = MPT_RATE_MCS21;
+		break;
+	case DESC_RATEMCS22:
+		ret_rate = MPT_RATE_MCS22;
+		break;
+	case DESC_RATEMCS23:
+		ret_rate = MPT_RATE_MCS23;
+		break;
+	case DESC_RATEMCS24:
+		ret_rate = MPT_RATE_MCS24;
+		break;
+	case DESC_RATEMCS25:
+		ret_rate = MPT_RATE_MCS25;
+		break;
+	case DESC_RATEMCS26:
+		ret_rate = MPT_RATE_MCS26;
+		break;
+	case DESC_RATEMCS27:
+		ret_rate = MPT_RATE_MCS27;
+		break;
+	case DESC_RATEMCS28:
+		ret_rate = MPT_RATE_MCS28;
+		break;
+	case DESC_RATEMCS29:
+		ret_rate = MPT_RATE_MCS29;
+		break;
+	case DESC_RATEMCS30:
+		ret_rate = MPT_RATE_MCS30;
+		break;
+	case DESC_RATEMCS31:
+		ret_rate = MPT_RATE_MCS31;
+		break;
+	case DESC_RATEVHTSS1MCS0:
+		ret_rate = MPT_RATE_VHT1SS_MCS0;
+		break;
+	case DESC_RATEVHTSS1MCS1:
+		ret_rate = MPT_RATE_VHT1SS_MCS1;
+		break;
+	case DESC_RATEVHTSS1MCS2:
+		ret_rate = MPT_RATE_VHT1SS_MCS2;
+		break;
+	case DESC_RATEVHTSS1MCS3:
+		ret_rate = MPT_RATE_VHT1SS_MCS3;
+		break;
+	case DESC_RATEVHTSS1MCS4:
+		ret_rate = MPT_RATE_VHT1SS_MCS4;
+		break;
+	case DESC_RATEVHTSS1MCS5:
+		ret_rate = MPT_RATE_VHT1SS_MCS5;
+		break;
+	case DESC_RATEVHTSS1MCS6:
+		ret_rate = MPT_RATE_VHT1SS_MCS6;
+		break;
+	case DESC_RATEVHTSS1MCS7:
+		ret_rate = MPT_RATE_VHT1SS_MCS7;
+		break;
+	case DESC_RATEVHTSS1MCS8:
+		ret_rate = MPT_RATE_VHT1SS_MCS8;
+		break;
+	case DESC_RATEVHTSS1MCS9:
+		ret_rate = MPT_RATE_VHT1SS_MCS9;
+		break;
+	case DESC_RATEVHTSS2MCS0:
+		ret_rate = MPT_RATE_VHT2SS_MCS0;
+		break;
+	case DESC_RATEVHTSS2MCS1:
+		ret_rate = MPT_RATE_VHT2SS_MCS1;
+		break;
+	case DESC_RATEVHTSS2MCS2:
+		ret_rate = MPT_RATE_VHT2SS_MCS2;
+		break;
+	case DESC_RATEVHTSS2MCS3:
+		ret_rate = MPT_RATE_VHT2SS_MCS3;
+		break;
+	case DESC_RATEVHTSS2MCS4:
+		ret_rate = MPT_RATE_VHT2SS_MCS4;
+		break;
+	case DESC_RATEVHTSS2MCS5:
+		ret_rate = MPT_RATE_VHT2SS_MCS5;
+		break;
+	case DESC_RATEVHTSS2MCS6:
+		ret_rate = MPT_RATE_VHT2SS_MCS6;
+		break;
+	case DESC_RATEVHTSS2MCS7:
+		ret_rate = MPT_RATE_VHT2SS_MCS7;
+		break;
+	case DESC_RATEVHTSS2MCS8:
+		ret_rate = MPT_RATE_VHT2SS_MCS8;
+		break;
+	case DESC_RATEVHTSS2MCS9:
+		ret_rate = MPT_RATE_VHT2SS_MCS9;
+		break;
+	case DESC_RATEVHTSS3MCS0:
+		ret_rate = MPT_RATE_VHT3SS_MCS0;
+		break;
+	case DESC_RATEVHTSS3MCS1:
+		ret_rate = MPT_RATE_VHT3SS_MCS1;
+		break;
+	case DESC_RATEVHTSS3MCS2:
+		ret_rate = MPT_RATE_VHT3SS_MCS2;
+		break;
+	case DESC_RATEVHTSS3MCS3:
+		ret_rate = MPT_RATE_VHT3SS_MCS3;
+		break;
+	case DESC_RATEVHTSS3MCS4:
+		ret_rate = MPT_RATE_VHT3SS_MCS4;
+		break;
+	case DESC_RATEVHTSS3MCS5:
+		ret_rate = MPT_RATE_VHT3SS_MCS5;
+		break;
+	case DESC_RATEVHTSS3MCS6:
+		ret_rate = MPT_RATE_VHT3SS_MCS6;
+		break;
+	case DESC_RATEVHTSS3MCS7:
+		ret_rate = MPT_RATE_VHT3SS_MCS7;
+		break;
+	case DESC_RATEVHTSS3MCS8:
+		ret_rate = MPT_RATE_VHT3SS_MCS8;
+		break;
+	case DESC_RATEVHTSS3MCS9:
+		ret_rate = MPT_RATE_VHT3SS_MCS9;
+		break;
+	case DESC_RATEVHTSS4MCS0:
+		ret_rate = MPT_RATE_VHT4SS_MCS0;
+		break;
+	case DESC_RATEVHTSS4MCS1:
+		ret_rate = MPT_RATE_VHT4SS_MCS1;
+		break;
+	case DESC_RATEVHTSS4MCS2:
+		ret_rate = MPT_RATE_VHT4SS_MCS2;
+		break;
+	case DESC_RATEVHTSS4MCS3:
+		ret_rate = MPT_RATE_VHT4SS_MCS3;
+		break;
+	case DESC_RATEVHTSS4MCS4:
+		ret_rate = MPT_RATE_VHT4SS_MCS4;
+		break;
+	case DESC_RATEVHTSS4MCS5:
+		ret_rate = MPT_RATE_VHT4SS_MCS5;
+		break;
+	case DESC_RATEVHTSS4MCS6:
+		ret_rate = MPT_RATE_VHT4SS_MCS6;
+		break;
+	case DESC_RATEVHTSS4MCS7:
+		ret_rate = MPT_RATE_VHT4SS_MCS7;
+		break;
+	case DESC_RATEVHTSS4MCS8:
+		ret_rate = MPT_RATE_VHT4SS_MCS8;
+		break;
+	case DESC_RATEVHTSS4MCS9:
+		ret_rate = MPT_RATE_VHT4SS_MCS9;
+		break;
+
+	default:
+		RTW_INFO("hw_rate_to_m_rate(): Non supported Rate [%x]!!!\n", rate);
+		break;
+	}
+	return ret_rate;
+}
+
+u8 rtw_mpRateParseFunc(PADAPTER pAdapter, u8 *targetStr)
+{
+	u16 i = 0;
+	u8 *rateindex_Array[] = { "1M", "2M", "5.5M", "11M", "6M", "9M", "12M", "18M", "24M", "36M", "48M", "54M",
+		"HTMCS0", "HTMCS1", "HTMCS2", "HTMCS3", "HTMCS4", "HTMCS5", "HTMCS6", "HTMCS7",
+		"HTMCS8", "HTMCS9", "HTMCS10", "HTMCS11", "HTMCS12", "HTMCS13", "HTMCS14", "HTMCS15",
+		"HTMCS16", "HTMCS17", "HTMCS18", "HTMCS19", "HTMCS20", "HTMCS21", "HTMCS22", "HTMCS23",
+		"HTMCS24", "HTMCS25", "HTMCS26", "HTMCS27", "HTMCS28", "HTMCS29", "HTMCS30", "HTMCS31",
+		"VHT1MCS0", "VHT1MCS1", "VHT1MCS2", "VHT1MCS3", "VHT1MCS4", "VHT1MCS5", "VHT1MCS6", "VHT1MCS7", "VHT1MCS8", "VHT1MCS9",
+		"VHT2MCS0", "VHT2MCS1", "VHT2MCS2", "VHT2MCS3", "VHT2MCS4", "VHT2MCS5", "VHT2MCS6", "VHT2MCS7", "VHT2MCS8", "VHT2MCS9",
+		"VHT3MCS0", "VHT3MCS1", "VHT3MCS2", "VHT3MCS3", "VHT3MCS4", "VHT3MCS5", "VHT3MCS6", "VHT3MCS7", "VHT3MCS8", "VHT3MCS9",
+		"VHT4MCS0", "VHT4MCS1", "VHT4MCS2", "VHT4MCS3", "VHT4MCS4", "VHT4MCS5", "VHT4MCS6", "VHT4MCS7", "VHT4MCS8", "VHT4MCS9"
+				};
+
+	for (i = 0; i <= 83; i++) {
+		if (strcmp(targetStr, rateindex_Array[i]) == 0) {
+			RTW_INFO("%s , index = %d\n", __func__ , i);
+			return i;
+		}
+	}
+
+	printk("%s ,please input a Data RATE String as:", __func__);
+	for (i = 0; i <= 83; i++) {
+		printk("%s ", rateindex_Array[i]);
+		if (i % 10 == 0)
+			printk("\n");
+	}
+	return _FAIL;
+}
+
+u8 rtw_mp_mode_check(PADAPTER pAdapter)
+{
+	PADAPTER primary_adapter = GET_PRIMARY_ADAPTER(pAdapter);
+
+	if (primary_adapter->registrypriv.mp_mode == 1)
+		return _TRUE;
+	else
+		return _FALSE;
+}
+
+
+ULONG mpt_ProQueryCalTxPower(
+	PADAPTER	pAdapter,
+	u8		RfPath
+)
+{
+
+	HAL_DATA_TYPE	*pHalData	= GET_HAL_DATA(pAdapter);
+	PMPT_CONTEXT		pMptCtx = &(pAdapter->mppriv.mpt_ctx);
+
+	ULONG			TxPower = 1;
+	struct txpwr_idx_comp tic;
+	u8 mgn_rate = mpt_to_mgnt_rate(pMptCtx->mpt_rate_index);
+
+	TxPower = rtw_hal_get_tx_power_index(pAdapter, RfPath, mgn_rate, pHalData->current_channel_bw, pHalData->current_channel, &tic);
+
+	RTW_INFO("bw=%d, ch=%d, rate=%d, txPower:%u = %u + (%d=%d:%d) + (%d) + (%d)\n",
+		pHalData->current_channel_bw, pHalData->current_channel, mgn_rate
+		, TxPower, tic.base, (tic.by_rate > tic.limit ? tic.limit : tic.by_rate), tic.by_rate, tic.limit, tic.tpt, tic.ebias);
+
+	pAdapter->mppriv.txpoweridx = (u8)TxPower;
+	if (RfPath == RF_PATH_A)
+		pMptCtx->TxPwrLevel[RF_PATH_A] = (u8)TxPower;
+	else if (RfPath == RF_PATH_B)
+		pMptCtx->TxPwrLevel[RF_PATH_B] = (u8)TxPower;
+	else if (RfPath == RF_PATH_C)
+		pMptCtx->TxPwrLevel[RF_PATH_C] = (u8)TxPower;
+	else if (RfPath == RF_PATH_D)
+		pMptCtx->TxPwrLevel[RF_PATH_D]    = (u8)TxPower;
+	hal_mpt_SetTxPower(pAdapter);
+
+	return TxPower;
+}
+
+#ifdef CONFIG_MP_VHT_HW_TX_MODE
+static inline void dump_buf(u8 *buf, u32 len)
+{
+	u32 i;
+
+	RTW_INFO("-----------------Len %d----------------\n", len);
+	for (i = 0; i < len; i++)
+		RTW_INFO("%2.2x-", *(buf + i));
+	RTW_INFO("\n");
+}
+
+void ByteToBit(
+	UCHAR	*out,
+	bool	*in,
+	UCHAR	in_size)
+{
+	UCHAR i = 0, j = 0;
+
+	for (i = 0; i < in_size; i++) {
+		for (j = 0; j < 8; j++) {
+			if (in[8 * i + j])
+				out[i] |= (1 << j);
+		}
+	}
+}
+
+
+void CRC16_generator(
+	bool *out,
+	bool *in,
+	UCHAR in_size
+)
+{
+	UCHAR i = 0;
+	bool temp = 0, reg[] = {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1};
+
+	for (i = 0; i < in_size; i++) {/* take one's complement and bit reverse*/
+		temp = in[i] ^ reg[15];
+		reg[15]	= reg[14];
+		reg[14]	= reg[13];
+		reg[13]	= reg[12];
+		reg[12]	= reg[11];
+		reg[11]	= reg[10];
+		reg[10]	= reg[9];
+		reg[9]	= reg[8];
+		reg[8]	= reg[7];
+
+		reg[7]	= reg[6];
+		reg[6]	= reg[5];
+		reg[5]	= reg[4];
+		reg[4]	= reg[3];
+		reg[3]	= reg[2];
+		reg[2]	= reg[1];
+		reg[1]	= reg[0];
+		reg[12]	= reg[12] ^ temp;
+		reg[5]	= reg[5] ^ temp;
+		reg[0]	= temp;
+	}
+	for (i = 0; i < 16; i++)	/* take one's complement and bit reverse*/
+		out[i] = 1 - reg[15 - i];
+}
+
+
+
+/*========================================
+	SFD		SIGNAL	SERVICE	LENGTH	CRC
+	16 bit	8 bit	8 bit	16 bit	16 bit
+========================================*/
+void CCK_generator(
+	PRT_PMAC_TX_INFO	pPMacTxInfo,
+	PRT_PMAC_PKT_INFO	pPMacPktInfo
+)
+{
+	double	ratio = 0;
+	bool	crc16_in[32] = {0}, crc16_out[16] = {0};
+	bool LengthExtBit;
+	double LengthExact;
+	double LengthPSDU;
+	UCHAR i;
+	UINT PacketLength = pPMacTxInfo->PacketLength;
+
+	if (pPMacTxInfo->bSPreamble)
+		pPMacTxInfo->SFD = 0x05CF;
+	else
+		pPMacTxInfo->SFD = 0xF3A0;
+
+	switch (pPMacPktInfo->MCS) {
+	case 0:
+		pPMacTxInfo->SignalField = 0xA;
+		ratio = 8;
+		/*CRC16_in(1,0:7)=[0 1 0 1 0 0 0 0]*/
+		crc16_in[1] = crc16_in[3] = 1;
+		break;
+	case 1:
+		pPMacTxInfo->SignalField = 0x14;
+		ratio = 4;
+		/*CRC16_in(1,0:7)=[0 0 1 0 1 0 0 0];*/
+		crc16_in[2] = crc16_in[4] = 1;
+		break;
+	case 2:
+		pPMacTxInfo->SignalField = 0x37;
+		ratio = 8.0 / 5.5;
+		/*CRC16_in(1,0:7)=[1 1 1 0 1 1 0 0];*/
+		crc16_in[0] = crc16_in[1] = crc16_in[2] = crc16_in[4] = crc16_in[5] = 1;
+		break;
+	case 3:
+		pPMacTxInfo->SignalField = 0x6E;
+		ratio = 8.0 / 11.0;
+		/*CRC16_in(1,0:7)=[0 1 1 1 0 1 1 0];*/
+		crc16_in[1] = crc16_in[2] = crc16_in[3] = crc16_in[5] = crc16_in[6] = 1;
+		break;
+	}
+
+	LengthExact = PacketLength * ratio;
+	LengthPSDU = ceil(LengthExact);
+
+	if ((pPMacPktInfo->MCS == 3) &&
+	    ((LengthPSDU - LengthExact) >= 0.727 || (LengthPSDU - LengthExact) <= -0.727))
+		LengthExtBit = 1;
+	else
+		LengthExtBit = 0;
+
+
+	pPMacTxInfo->LENGTH = (UINT)LengthPSDU;
+	/* CRC16_in(1,16:31) = LengthPSDU[0:15]*/
+	for (i = 0; i < 16; i++)
+		crc16_in[i + 16] = (pPMacTxInfo->LENGTH >> i) & 0x1;
+
+	if (LengthExtBit == 0) {
+		pPMacTxInfo->ServiceField = 0x0;
+		/* CRC16_in(1,8:15) = [0 0 0 0 0 0 0 0];*/
+	} else {
+		pPMacTxInfo->ServiceField = 0x80;
+		/*CRC16_in(1,8:15)=[0 0 0 0 0 0 0 1];*/
+		crc16_in[15] = 1;
+	}
+
+	CRC16_generator(crc16_out, crc16_in, 32);
+
+	_rtw_memset(pPMacTxInfo->CRC16, 0, 2);
+	ByteToBit(pPMacTxInfo->CRC16, crc16_out, 2);
+
+}
+
+
+void PMAC_Get_Pkt_Param(
+	PRT_PMAC_TX_INFO	pPMacTxInfo,
+	PRT_PMAC_PKT_INFO	pPMacPktInfo)
+{
+
+	UCHAR		TX_RATE_HEX = 0, MCS = 0;
+	UCHAR		TX_RATE = pPMacTxInfo->TX_RATE;
+
+	/*	TX_RATE & Nss	*/
+	if (MPT_IS_2SS_RATE(TX_RATE))
+		pPMacPktInfo->Nss = 2;
+	else if (MPT_IS_3SS_RATE(TX_RATE))
+		pPMacPktInfo->Nss = 3;
+	else if (MPT_IS_4SS_RATE(TX_RATE))
+		pPMacPktInfo->Nss = 4;
+	else
+		pPMacPktInfo->Nss = 1;
+
+	RTW_INFO("PMacTxInfo.Nss =%d\n", pPMacPktInfo->Nss);
+
+	/*	MCS & TX_RATE_HEX*/
+	if (MPT_IS_CCK_RATE(TX_RATE)) {
+		switch (TX_RATE) {
+		case MPT_RATE_1M:
+			TX_RATE_HEX = MCS = 0;
+			break;
+		case MPT_RATE_2M:
+			TX_RATE_HEX = MCS = 1;
+			break;
+		case MPT_RATE_55M:
+			TX_RATE_HEX = MCS = 2;
+			break;
+		case MPT_RATE_11M:
+			TX_RATE_HEX = MCS = 3;
+			break;
+		}
+	} else if (MPT_IS_OFDM_RATE(TX_RATE)) {
+		MCS = TX_RATE - MPT_RATE_6M;
+		TX_RATE_HEX = MCS + 4;
+	} else if (MPT_IS_HT_RATE(TX_RATE)) {
+		MCS = TX_RATE - MPT_RATE_MCS0;
+		TX_RATE_HEX = MCS + 12;
+	} else if (MPT_IS_VHT_RATE(TX_RATE)) {
+		TX_RATE_HEX = TX_RATE - MPT_RATE_VHT1SS_MCS0 + 44;
+
+		if (MPT_IS_VHT_2S_RATE(TX_RATE))
+			MCS = TX_RATE - MPT_RATE_VHT2SS_MCS0;
+		else if (MPT_IS_VHT_3S_RATE(TX_RATE))
+			MCS = TX_RATE - MPT_RATE_VHT3SS_MCS0;
+		else if (MPT_IS_VHT_4S_RATE(TX_RATE))
+			MCS = TX_RATE - MPT_RATE_VHT4SS_MCS0;
+		else
+			MCS = TX_RATE - MPT_RATE_VHT1SS_MCS0;
+	}
+
+	pPMacPktInfo->MCS = MCS;
+	pPMacTxInfo->TX_RATE_HEX = TX_RATE_HEX;
+
+	RTW_INFO(" MCS=%d, TX_RATE_HEX =0x%x\n", MCS, pPMacTxInfo->TX_RATE_HEX);
+	/*	mSTBC & Nsts*/
+	pPMacPktInfo->Nsts = pPMacPktInfo->Nss;
+	if (pPMacTxInfo->bSTBC) {
+		if (pPMacPktInfo->Nss == 1) {
+			pPMacTxInfo->m_STBC = 2;
+			pPMacPktInfo->Nsts = pPMacPktInfo->Nss * 2;
+		} else
+			pPMacTxInfo->m_STBC = 1;
+	} else
+		pPMacTxInfo->m_STBC = 1;
+}
+
+
+UINT LDPC_parameter_generator(
+	UINT N_pld_int,
+	UINT N_CBPSS,
+	UINT N_SS,
+	UINT R,
+	UINT m_STBC,
+	UINT N_TCB_int
+)
+{
+	double	CR = 0.;
+	double	N_pld = (double)N_pld_int;
+	double	N_TCB = (double)N_TCB_int;
+	double	N_CW = 0., N_shrt = 0., N_spcw = 0., N_fshrt = 0.;
+	double	L_LDPC = 0., K_LDPC = 0., L_LDPC_info = 0.;
+	double	N_punc = 0., N_ppcw = 0., N_fpunc = 0., N_rep = 0., N_rpcw = 0., N_frep = 0.;
+	double	R_eff = 0.;
+	UINT	VHTSIGA2B3  = 0;/* extra symbol from VHT-SIG-A2 Bit 3*/
+
+	if (R == 0)
+		CR	= 0.5;
+	else if (R == 1)
+		CR = 2. / 3.;
+	else if (R == 2)
+		CR = 3. / 4.;
+	else if (R == 3)
+		CR = 5. / 6.;
+
+	if (N_TCB <= 648.) {
+		N_CW	= 1.;
+		if (N_TCB >= N_pld + 912.*(1. - CR))
+			L_LDPC	= 1296.;
+		else
+			L_LDPC	= 648.;
+	} else if (N_TCB <= 1296.) {
+		N_CW	= 1.;
+		if (N_TCB >= (double)N_pld + 1464.*(1. - CR))
+			L_LDPC	= 1944.;
+		else
+			L_LDPC	= 1296.;
+	} else if	(N_TCB <= 1944.) {
+		N_CW	= 1.;
+		L_LDPC	= 1944.;
+	} else if (N_TCB <= 2592.) {
+		N_CW	= 2.;
+		if (N_TCB >= N_pld + 2916.*(1. - CR))
+			L_LDPC	= 1944.;
+		else
+			L_LDPC	= 1296.;
+	} else {
+		N_CW = ceil(N_pld / 1944. / CR);
+		L_LDPC	= 1944.;
+	}
+	/*	Number of information bits per CW*/
+	K_LDPC = L_LDPC * CR;
+	/*	Number of shortening bits					max(0, (N_CW * L_LDPC * R) - N_pld)*/
+	N_shrt = (N_CW * K_LDPC - N_pld) > 0. ? (N_CW * K_LDPC - N_pld) : 0.;
+	/*	Number of shortening bits per CW			N_spcw = rtfloor(N_shrt/N_CW)*/
+	N_spcw = rtfloor(N_shrt / N_CW);
+	/*	The first N_fshrt CWs shorten 1 bit more*/
+	N_fshrt = (double)((int)N_shrt % (int)N_CW);
+	/*	Number of data bits for the last N_CW-N_fshrt CWs*/
+	L_LDPC_info = K_LDPC - N_spcw;
+	/*	Number of puncturing bits*/
+	N_punc = (N_CW * L_LDPC - N_TCB - N_shrt) > 0. ? (N_CW * L_LDPC - N_TCB - N_shrt) : 0.;
+	if (((N_punc > .1 * N_CW * L_LDPC * (1. - CR)) && (N_shrt < 1.2 * N_punc * CR / (1. - CR))) ||
+	    (N_punc > 0.3 * N_CW * L_LDPC * (1. - CR))) {
+		/*cout << "*** N_TCB and N_punc are Recomputed ***" << endl;*/
+		VHTSIGA2B3 = 1;
+		N_TCB += (double)N_CBPSS * N_SS * m_STBC;
+		N_punc = (N_CW * L_LDPC - N_TCB - N_shrt) > 0. ? (N_CW * L_LDPC - N_TCB - N_shrt) : 0.;
+	} else
+		VHTSIGA2B3 = 0;
+
+	return VHTSIGA2B3;
+}	/* function end of LDPC_parameter_generator */
+
+/*========================================
+	Data field of PPDU
+	Get N_sym and SIGA2BB3
+========================================*/
+void PMAC_Nsym_generator(
+	PRT_PMAC_TX_INFO	pPMacTxInfo,
+	PRT_PMAC_PKT_INFO	pPMacPktInfo)
+{
+	UINT	SIGA2B3 = 0;
+	UCHAR	TX_RATE = pPMacTxInfo->TX_RATE;
+
+	UINT R, R_list[10] = {0, 0, 2, 0, 2, 1, 2, 3, 2, 3};
+	double CR = 0;
+	UINT N_SD, N_BPSC_list[10] = {1, 2, 2, 4, 4, 6, 6, 6, 8, 8};
+	UINT N_BPSC = 0, N_CBPS = 0, N_DBPS = 0, N_ES = 0, N_SYM = 0, N_pld = 0, N_TCB = 0;
+	int D_R = 0;
+
+	RTW_INFO("TX_RATE = %d\n", TX_RATE);
+	/*	N_SD*/
+	if (pPMacTxInfo->BandWidth == 0)
+		N_SD = 52;
+	else if (pPMacTxInfo->BandWidth == 1)
+		N_SD = 108;
+	else
+		N_SD = 234;
+
+	if (MPT_IS_HT_RATE(TX_RATE)) {
+		UCHAR MCS_temp;
+
+		if (pPMacPktInfo->MCS > 23)
+			MCS_temp = pPMacPktInfo->MCS - 24;
+		else if (pPMacPktInfo->MCS > 15)
+			MCS_temp = pPMacPktInfo->MCS - 16;
+		else if (pPMacPktInfo->MCS > 7)
+			MCS_temp = pPMacPktInfo->MCS - 8;
+		else
+			MCS_temp = pPMacPktInfo->MCS;
+
+		R = R_list[MCS_temp];
+
+		switch (R) {
+		case 0:
+			CR = .5;
+			break;
+		case 1:
+			CR = 2. / 3.;
+			break;
+		case 2:
+			CR = 3. / 4.;
+			break;
+		case 3:
+			CR = 5. / 6.;
+			break;
+		}
+
+		N_BPSC = N_BPSC_list[MCS_temp];
+		N_CBPS = N_BPSC * N_SD * pPMacPktInfo->Nss;
+		N_DBPS = (UINT)((double)N_CBPS * CR);
+
+		if (pPMacTxInfo->bLDPC == FALSE) {
+			N_ES = (UINT)ceil((double)(N_DBPS * pPMacPktInfo->Nss) / 4. / 300.);
+			RTW_INFO("N_ES = %d\n", N_ES);
+
+			/*	N_SYM = m_STBC* (8*length+16+6*N_ES) / (m_STBC*N_DBPS)*/
+			N_SYM = pPMacTxInfo->m_STBC * (UINT)ceil((double)(pPMacTxInfo->PacketLength * 8 + 16 + N_ES * 6) /
+					(double)(N_DBPS * pPMacTxInfo->m_STBC));
+
+		} else {
+			N_ES = 1;
+			/*	N_pld = length * 8 + 16*/
+			N_pld = pPMacTxInfo->PacketLength * 8 + 16;
+			RTW_INFO("N_pld = %d\n", N_pld);
+			N_SYM = pPMacTxInfo->m_STBC * (UINT)ceil((double)(N_pld) /
+					(double)(N_DBPS * pPMacTxInfo->m_STBC));
+			RTW_INFO("N_SYM = %d\n", N_SYM);
+			/*	N_avbits = N_CBPS *m_STBC *(N_pld/N_CBPS*R*m_STBC)*/
+			N_TCB = N_CBPS * N_SYM;
+			RTW_INFO("N_TCB = %d\n", N_TCB);
+			SIGA2B3 = LDPC_parameter_generator(N_pld, N_CBPS, pPMacPktInfo->Nss, R, pPMacTxInfo->m_STBC, N_TCB);
+			RTW_INFO("SIGA2B3 = %d\n", SIGA2B3);
+			N_SYM = N_SYM + SIGA2B3 * pPMacTxInfo->m_STBC;
+			RTW_INFO("N_SYM = %d\n", N_SYM);
+		}
+	} else if (MPT_IS_VHT_RATE(TX_RATE)) {
+		R = R_list[pPMacPktInfo->MCS];
+
+		switch (R) {
+		case 0:
+			CR = .5;
+			break;
+		case 1:
+			CR = 2. / 3.;
+			break;
+		case 2:
+			CR = 3. / 4.;
+			break;
+		case 3:
+			CR = 5. / 6.;
+			break;
+		}
+		N_BPSC = N_BPSC_list[pPMacPktInfo->MCS];
+		N_CBPS = N_BPSC * N_SD * pPMacPktInfo->Nss;
+		N_DBPS = (UINT)((double)N_CBPS * CR);
+		if (pPMacTxInfo->bLDPC == FALSE) {
+			if (pPMacTxInfo->bSGI)
+				N_ES = (UINT)ceil((double)(N_DBPS) / 3.6 / 600.);
+			else
+				N_ES = (UINT)ceil((double)(N_DBPS) / 4. / 600.);
+			/*	N_SYM = m_STBC* (8*length+16+6*N_ES) / (m_STBC*N_DBPS)*/
+			N_SYM = pPMacTxInfo->m_STBC * (UINT)ceil((double)(pPMacTxInfo->PacketLength * 8 + 16 + N_ES * 6) / (double)(N_DBPS * pPMacTxInfo->m_STBC));
+			SIGA2B3 = 0;
+		} else {
+			N_ES = 1;
+			/*	N_SYM = m_STBC* (8*length+N_service) / (m_STBC*N_DBPS)*/
+			N_SYM = pPMacTxInfo->m_STBC * (UINT)ceil((double)(pPMacTxInfo->PacketLength * 8 + 16) / (double)(N_DBPS * pPMacTxInfo->m_STBC));
+			/*	N_avbits = N_sys_init * N_CBPS*/
+			N_TCB = N_CBPS * N_SYM;
+			/*	N_pld = N_sys_init * N_DBPS*/
+			N_pld = N_SYM * N_DBPS;
+			SIGA2B3 = LDPC_parameter_generator(N_pld, N_CBPS, pPMacPktInfo->Nss, R, pPMacTxInfo->m_STBC, N_TCB);
+			N_SYM = N_SYM + SIGA2B3 * pPMacTxInfo->m_STBC;
+		}
+
+		switch (R) {
+		case 0:
+			D_R = 2;
+			break;
+		case 1:
+			D_R = 3;
+			break;
+		case 2:
+			D_R = 4;
+			break;
+		case 3:
+			D_R = 6;
+			break;
+		}
+
+		if (((N_CBPS / N_ES) % D_R) != 0) {
+			RTW_INFO("MCS= %d is not supported when Nss=%d and BW= %d !!\n",  pPMacPktInfo->MCS, pPMacPktInfo->Nss, pPMacTxInfo->BandWidth);
+			return;
+		}
+
+		RTW_INFO("MCS= %d Nss=%d and BW= %d !!\n",  pPMacPktInfo->MCS, pPMacPktInfo->Nss, pPMacTxInfo->BandWidth);
+	}
+
+	pPMacPktInfo->N_sym = N_SYM;
+	pPMacPktInfo->SIGA2B3 = SIGA2B3;
+}
+
+/*========================================
+	L-SIG	Rate	R	Length	P	Tail
+			4b		1b	12b		1b	6b
+========================================*/
+
+void L_SIG_generator(
+	UINT	N_SYM,		/* Max: 750*/
+	PRT_PMAC_TX_INFO	pPMacTxInfo,
+	PRT_PMAC_PKT_INFO	pPMacPktInfo)
+{
+	u8	sig_bi[24] = {0};	/* 24 BIT*/
+	UINT	mode, LENGTH;
+	int i;
+
+	if (MPT_IS_OFDM_RATE(pPMacTxInfo->TX_RATE)) {
+		mode = pPMacPktInfo->MCS;
+		LENGTH = pPMacTxInfo->PacketLength;
+	} else {
+		UCHAR	N_LTF;
+		double	T_data;
+		UINT	OFDM_symbol;
+
+		mode = 0;
+
+		/*	Table 20-13 Num of HT-DLTFs request*/
+		if (pPMacPktInfo->Nsts <= 2)
+			N_LTF = pPMacPktInfo->Nsts;
+		else
+			N_LTF = 4;
+
+		if (pPMacTxInfo->bSGI)
+			T_data = 3.6;
+		else
+			T_data = 4.0;
+
+		/*(L-SIG, HT-SIG, HT-STF, HT-LTF....HT-LTF, Data)*/
+		if (MPT_IS_VHT_RATE(pPMacTxInfo->TX_RATE))
+			OFDM_symbol = (UINT)ceil((double)(8 + 4 + N_LTF * 4 + N_SYM * T_data + 4) / 4.);
+		else
+			OFDM_symbol = (UINT)ceil((double)(8 + 4 + N_LTF * 4 + N_SYM * T_data) / 4.);
+
+		RTW_INFO("%s , OFDM_symbol =%d\n", __func__, OFDM_symbol);
+		LENGTH = OFDM_symbol * 3 - 3;
+		RTW_INFO("%s , LENGTH =%d\n", __func__, LENGTH);
+
+	}
+	/*	Rate Field*/
+	switch (mode) {
+	case	0:
+		sig_bi[0] = 1;
+		sig_bi[1] = 1;
+		sig_bi[2] = 0;
+		sig_bi[3] = 1;
+		break;
+	case	1:
+		sig_bi[0] = 1;
+		sig_bi[1] = 1;
+		sig_bi[2] = 1;
+		sig_bi[3] = 1;
+		break;
+	case	2:
+		sig_bi[0] = 0;
+		sig_bi[1] = 1;
+		sig_bi[2] = 0;
+		sig_bi[3] = 1;
+		break;
+	case	3:
+		sig_bi[0] = 0;
+		sig_bi[1] = 1;
+		sig_bi[2] = 1;
+		sig_bi[3] = 1;
+		break;
+	case	4:
+		sig_bi[0] = 1;
+		sig_bi[1] = 0;
+		sig_bi[2] = 0;
+		sig_bi[3] = 1;
+		break;
+	case	5:
+		sig_bi[0] = 1;
+		sig_bi[1] = 0;
+		sig_bi[2] = 1;
+		sig_bi[3] = 1;
+		break;
+	case	6:
+		sig_bi[0] = 0;
+		sig_bi[1] = 0;
+		sig_bi[2] = 0;
+		sig_bi[3] = 1;
+		break;
+	case	7:
+		sig_bi[0] = 0;
+		sig_bi[1] = 0;
+		sig_bi[2] = 1;
+		sig_bi[3] = 1;
+		break;
+	}
+	/*Reserved bit*/
+	sig_bi[4] = 0;
+
+	/*	Length Field*/
+	for (i = 0; i < 12; i++)
+		sig_bi[i + 5] = (LENGTH >> i) & 1;
+
+	/* Parity Bit*/
+	sig_bi[17] = 0;
+	for (i = 0; i < 17; i++)
+		sig_bi[17] = sig_bi[17] + sig_bi[i];
+
+	sig_bi[17] %= 2;
+
+	/*	Tail Field*/
+	for (i = 18; i < 24; i++)
+		sig_bi[i] = 0;
+
+	/* dump_buf(sig_bi,24);*/
+	_rtw_memset(pPMacTxInfo->LSIG, 0, 3);
+	ByteToBit(pPMacTxInfo->LSIG, (bool *)sig_bi, 3);
+}
+
+
+void CRC8_generator(
+	bool	*out,
+	bool	*in,
+	UCHAR	in_size
+)
+{
+	UCHAR i = 0;
+	bool temp = 0, reg[] = {1, 1, 1, 1, 1, 1, 1, 1};
+
+	for (i = 0; i < in_size; i++) { /* take one's complement and bit reverse*/
+		temp = in[i] ^ reg[7];
+		reg[7]	= reg[6];
+		reg[6]	= reg[5];
+		reg[5]	= reg[4];
+		reg[4]	= reg[3];
+		reg[3]	= reg[2];
+		reg[2]	= reg[1] ^ temp;
+		reg[1]	= reg[0] ^ temp;
+		reg[0]	= temp;
+	}
+	for (i = 0; i < 8; i++)/* take one's complement and bit reverse*/
+		out[i] = reg[7 - i] ^ 1;
+}
+
+/*/================================================================================
+	HT-SIG1	MCS	CW	Length		24BIT + 24BIT
+			7b	1b	16b
+	HT-SIG2	Smoothing	Not sounding	Rsvd		AGG	STBC	FEC	SGI	N_ELTF	CRC	Tail
+			1b			1b			1b		1b	2b		1b	1b	2b		8b	6b
+================================================================================*/
+void HT_SIG_generator(
+	PRT_PMAC_TX_INFO	pPMacTxInfo,
+	PRT_PMAC_PKT_INFO	pPMacPktInfo
+)
+{
+	UINT i;
+	bool sig_bi[48] = {0}, crc8[8] = {0};
+	/*	MCS Field*/
+	for (i = 0; i < 7; i++)
+		sig_bi[i] = (pPMacPktInfo->MCS >> i) & 0x1;
+	/*	Packet BW Setting*/
+	sig_bi[7] = pPMacTxInfo->BandWidth;
+	/*	HT-Length Field*/
+	for (i = 0; i < 16; i++)
+		sig_bi[i + 8] = (pPMacTxInfo->PacketLength >> i) & 0x1;
+	/*	Smoothing;	1->allow smoothing*/
+	sig_bi[24] = 1;
+	/*Not Sounding*/
+	sig_bi[25] = 1 - pPMacTxInfo->NDP_sound;
+	/*Reserved bit*/
+	sig_bi[26] = 1;
+	/*/Aggregate*/
+	sig_bi[27] = 0;
+	/*STBC Field*/
+	if (pPMacTxInfo->bSTBC) {
+		sig_bi[28] = 1;
+		sig_bi[29] = 0;
+	} else {
+		sig_bi[28] = 0;
+		sig_bi[29] = 0;
+	}
+	/*Advance Coding,	0: BCC, 1: LDPC*/
+	sig_bi[30] = pPMacTxInfo->bLDPC;
+	/* Short GI*/
+	sig_bi[31] = pPMacTxInfo->bSGI;
+	/* N_ELTFs*/
+	if (pPMacTxInfo->NDP_sound == FALSE) {
+		sig_bi[32]	= 0;
+		sig_bi[33]	= 0;
+	} else {
+		int	N_ELTF = pPMacTxInfo->Ntx - pPMacPktInfo->Nss;
+
+		for (i = 0; i < 2; i++)
+			sig_bi[32 + i] = (N_ELTF >> i) % 2;
+	}
+	/*	CRC-8*/
+	CRC8_generator(crc8, sig_bi, 34);
+
+	for (i = 0; i < 8; i++)
+		sig_bi[34 + i] = crc8[i];
+
+	/*Tail*/
+	for (i = 42; i < 48; i++)
+		sig_bi[i] = 0;
+
+	_rtw_memset(pPMacTxInfo->HT_SIG, 0, 6);
+	ByteToBit(pPMacTxInfo->HT_SIG, sig_bi, 6);
+}
+
+
+/*======================================================================================
+	VHT-SIG-A1
+	BW	Reserved	STBC	G_ID	SU_Nsts	P_AID	TXOP_PS_NOT_ALLOW	Reserved
+	2b	1b			1b		6b	3b	9b		1b		2b					1b
+	VHT-SIG-A2
+	SGI	SGI_Nsym	SU/MU coding	LDPC_Extra	SU_NCS	Beamformed	Reserved	CRC	Tail
+	1b	1b			1b				1b			4b		1b			1b			8b	6b
+======================================================================================*/
+void VHT_SIG_A_generator(
+	PRT_PMAC_TX_INFO	pPMacTxInfo,
+	PRT_PMAC_PKT_INFO	pPMacPktInfo)
+{
+	UINT i;
+	bool sig_bi[48], crc8[8];
+
+	_rtw_memset(sig_bi, 0, 48);
+	_rtw_memset(crc8, 0, 8);
+
+	/*	BW Setting*/
+	for (i = 0; i < 2; i++)
+		sig_bi[i] = (pPMacTxInfo->BandWidth >> i) & 0x1;
+	/* Reserved Bit*/
+	sig_bi[2] = 1;
+	/*STBC Field*/
+	sig_bi[3] = pPMacTxInfo->bSTBC;
+	/*Group ID: Single User->A value of 0 or 63 indicates an SU PPDU. */
+	for (i = 0; i < 6; i++)
+		sig_bi[4 + i] = 0;
+	/*	N_STS/Partial AID*/
+	for (i = 0; i < 12; i++) {
+		if (i < 3)
+			sig_bi[10 + i] = ((pPMacPktInfo->Nsts - 1) >> i) & 0x1;
+		else
+			sig_bi[10 + i] = 0;
+	}
+	/*TXOP_PS_NOT_ALLPWED*/
+	sig_bi[22]	= 0;
+	/*Reserved Bits*/
+	sig_bi[23]	= 1;
+	/*Short GI*/
+	sig_bi[24] = pPMacTxInfo->bSGI;
+	if (pPMacTxInfo->bSGI > 0 && (pPMacPktInfo->N_sym % 10) == 9)
+		sig_bi[25] = 1;
+	else
+		sig_bi[25] = 0;
+	/* SU/MU[0] Coding*/
+	sig_bi[26] = pPMacTxInfo->bLDPC;	/*	0:BCC, 1:LDPC		*/
+	sig_bi[27] = pPMacPktInfo->SIGA2B3;	/*/	Record Extra OFDM Symols is added or not when LDPC is used*/
+	/*SU MCS/MU[1-3] Coding*/
+	for (i = 0; i < 4; i++)
+		sig_bi[28 + i] = (pPMacPktInfo->MCS >> i) & 0x1;
+	/*SU Beamform */
+	sig_bi[32] = 0;	/*packet.TXBF_en;*/
+	/*Reserved Bit*/
+	sig_bi[33] = 1;
+	/*CRC-8*/
+	CRC8_generator(crc8, sig_bi, 34);
+	for (i = 0; i < 8; i++)
+		sig_bi[34 + i]	= crc8[i];
+	/*Tail*/
+	for (i = 42; i < 48; i++)
+		sig_bi[i] = 0;
+
+	_rtw_memset(pPMacTxInfo->VHT_SIG_A, 0, 6);
+	ByteToBit(pPMacTxInfo->VHT_SIG_A, sig_bi, 6);
+}
+
+/*======================================================================================
+	VHT-SIG-B
+	Length				Resesrved	Trail
+	17/19/21 BIT		3/2/2 BIT	6b
+======================================================================================*/
+void VHT_SIG_B_generator(
+	PRT_PMAC_TX_INFO	pPMacTxInfo)
+{
+	bool sig_bi[32], crc8_bi[8];
+	UINT i, len, res, tail = 6, total_len, crc8_in_len;
+	UINT sigb_len;
+
+	_rtw_memset(sig_bi, 0, 32);
+	_rtw_memset(crc8_bi, 0, 8);
+
+	/*Sounding Packet*/
+	if (pPMacTxInfo->NDP_sound == 1) {
+		if (pPMacTxInfo->BandWidth == 0) {
+			bool sigb_temp[26] = {0, 0, 0, 0, 0, 1, 1, 1, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0};
+
+			_rtw_memcpy(sig_bi, sigb_temp, 26);
+		} else if (pPMacTxInfo->BandWidth == 1) {
+			bool sigb_temp[27] = {1, 0, 1, 0, 0, 1, 0, 1, 1, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0};
+
+			_rtw_memcpy(sig_bi, sigb_temp, 27);
+		} else if (pPMacTxInfo->BandWidth == 2) {
+			bool sigb_temp[29] = {0, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 1, 1, 1, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0};
+
+			_rtw_memcpy(sig_bi, sigb_temp, 29);
+		}
+	} else {	/* Not NDP Sounding*/
+		bool *sigb_temp[29] = {0};
+
+		if (pPMacTxInfo->BandWidth == 0) {
+			len = 17;
+			res = 3;
+		} else if (pPMacTxInfo->BandWidth == 1) {
+			len = 19;
+			res = 2;
+		} else if (pPMacTxInfo->BandWidth == 2) {
+			len	= 21;
+			res	= 2;
+		} else {
+			len	= 21;
+			res	= 2;
+		}
+		total_len = len + res + tail;
+		crc8_in_len = len + res;
+
+		/*Length Field*/
+		sigb_len = (pPMacTxInfo->PacketLength + 3) >> 2;
+
+		for (i = 0; i < len; i++)
+			sig_bi[i] = (sigb_len >> i) & 0x1;
+		/*Reserved Field*/
+		for (i = 0; i < res; i++)
+			sig_bi[len + i] = 1;
+		/* CRC-8*/
+		CRC8_generator(crc8_bi, sig_bi, crc8_in_len);
+
+		/* Tail */
+		for (i = 0; i < tail; i++)
+			sig_bi[len + res + i] = 0;
+	}
+
+	_rtw_memset(pPMacTxInfo->VHT_SIG_B, 0, 4);
+	ByteToBit(pPMacTxInfo->VHT_SIG_B, sig_bi, 4);
+
+	pPMacTxInfo->VHT_SIG_B_CRC = 0;
+	ByteToBit(&(pPMacTxInfo->VHT_SIG_B_CRC), crc8_bi, 1);
+}
+
+/*=======================
+ VHT Delimiter
+=======================*/
+void VHT_Delimiter_generator(
+	PRT_PMAC_TX_INFO	pPMacTxInfo
+)
+{
+	bool sig_bi[32] = {0}, crc8[8] = {0};
+	UINT crc8_in_len = 16;
+	UINT PacketLength = pPMacTxInfo->PacketLength;
+	int j;
+
+	/* Delimiter[0]: EOF*/
+	sig_bi[0] = 1;
+	/* Delimiter[1]: Reserved*/
+	sig_bi[1] = 0;
+	/* Delimiter[3:2]: MPDU Length High*/
+	sig_bi[2] = ((PacketLength - 4) >> 12) % 2;
+	sig_bi[3] = ((PacketLength - 4) >> 13) % 2;
+	/* Delimiter[15:4]: MPDU Length Low*/
+	for (j = 4; j < 16; j++)
+		sig_bi[j] = ((PacketLength - 4) >> (j - 4)) % 2;
+	CRC8_generator(crc8, sig_bi, crc8_in_len);
+	for (j = 16; j < 24; j++) /* Delimiter[23:16]: CRC 8*/
+		sig_bi[j] = crc8[j - 16];
+	for (j = 24; j < 32; j++) /* Delimiter[31:24]: Signature ('4E' in Hex, 78 in Dec)*/
+		sig_bi[j]	= (78 >> (j - 24)) % 2;
+
+	_rtw_memset(pPMacTxInfo->VHT_Delimiter, 0, 4);
+	ByteToBit(pPMacTxInfo->VHT_Delimiter, sig_bi, 4);
+}
+
+#endif
+#endif
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/core/rtw_mp_ioctl.c linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/core/rtw_mp_ioctl.c
--- linux-5.6.3/3rdparty/rtl8821ce/core/rtw_mp_ioctl.c	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/core/rtw_mp_ioctl.c	2020-04-10 16:35:06.776658200 +0300
@@ -0,0 +1,2529 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#define _RTW_MP_IOCTL_C_
+
+#include <drv_types.h>
+#include <rtw_mp_ioctl.h>
+#include "../hal/phydm/phydm_precomp.h"
+
+/* ****************  oid_rtl_seg_81_85   section start **************** */
+NDIS_STATUS oid_rt_wireless_mode_hdl(struct oid_par_priv *poid_par_priv)
+{
+	NDIS_STATUS status = NDIS_STATUS_SUCCESS;
+	PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context);
+
+
+	if (poid_par_priv->information_buf_len < sizeof(u8))
+		return NDIS_STATUS_INVALID_LENGTH;
+
+	if (poid_par_priv->type_of_oid == SET_OID)
+		Adapter->registrypriv.wireless_mode = *(u8 *)poid_par_priv->information_buf;
+	else if (poid_par_priv->type_of_oid == QUERY_OID) {
+		*(u8 *)poid_par_priv->information_buf = Adapter->registrypriv.wireless_mode;
+		*poid_par_priv->bytes_rw = poid_par_priv->information_buf_len;
+	} else
+		status = NDIS_STATUS_NOT_ACCEPTED;
+
+
+	return status;
+}
+/* ****************  oid_rtl_seg_81_87_80   section start **************** */
+NDIS_STATUS oid_rt_pro_write_bb_reg_hdl(struct oid_par_priv *poid_par_priv)
+{
+#ifdef PLATFORM_OS_XP
+	_irqL oldirql;
+#endif
+	struct bb_reg_param *pbbreg;
+	u16 offset;
+	u32 value;
+	NDIS_STATUS status = NDIS_STATUS_SUCCESS;
+	PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context);
+
+
+
+	if (poid_par_priv->type_of_oid != SET_OID)
+		return NDIS_STATUS_NOT_ACCEPTED;
+
+	if (poid_par_priv->information_buf_len < sizeof(struct bb_reg_param))
+		return NDIS_STATUS_INVALID_LENGTH;
+
+	pbbreg = (struct bb_reg_param *)(poid_par_priv->information_buf);
+
+	offset = (u16)(pbbreg->offset) & 0xFFF; /* 0ffset :0x800~0xfff */
+	if (offset < BB_REG_BASE_ADDR)
+		offset |= BB_REG_BASE_ADDR;
+
+	value = pbbreg->value;
+
+
+	_irqlevel_changed_(&oldirql, LOWER);
+	write_bbreg(Adapter, offset, 0xFFFFFFFF, value);
+	_irqlevel_changed_(&oldirql, RAISE);
+
+
+	return status;
+}
+/* ------------------------------------------------------------------------------ */
+NDIS_STATUS oid_rt_pro_read_bb_reg_hdl(struct oid_par_priv *poid_par_priv)
+{
+#ifdef PLATFORM_OS_XP
+	_irqL oldirql;
+#endif
+	struct bb_reg_param *pbbreg;
+	u16 offset;
+	u32 value;
+	NDIS_STATUS status = NDIS_STATUS_SUCCESS;
+	PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context);
+
+
+
+	if (poid_par_priv->type_of_oid != QUERY_OID)
+		return NDIS_STATUS_NOT_ACCEPTED;
+
+	if (poid_par_priv->information_buf_len < sizeof(struct bb_reg_param))
+		return NDIS_STATUS_INVALID_LENGTH;
+
+	pbbreg = (struct bb_reg_param *)(poid_par_priv->information_buf);
+
+	offset = (u16)(pbbreg->offset) & 0xFFF; /* 0ffset :0x800~0xfff */
+	if (offset < BB_REG_BASE_ADDR)
+		offset |= BB_REG_BASE_ADDR;
+
+	_irqlevel_changed_(&oldirql, LOWER);
+	value = read_bbreg(Adapter, offset, 0xFFFFFFFF);
+	_irqlevel_changed_(&oldirql, RAISE);
+
+	pbbreg->value = value;
+	*poid_par_priv->bytes_rw = poid_par_priv->information_buf_len;
+
+
+	return status;
+}
+/* ------------------------------------------------------------------------------ */
+NDIS_STATUS oid_rt_pro_write_rf_reg_hdl(struct oid_par_priv *poid_par_priv)
+{
+#ifdef PLATFORM_OS_XP
+	_irqL oldirql;
+#endif
+	struct rf_reg_param *pbbreg;
+	u8 path;
+	u8 offset;
+	u32 value;
+	NDIS_STATUS status = NDIS_STATUS_SUCCESS;
+	PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context);
+
+
+
+	if (poid_par_priv->type_of_oid != SET_OID)
+		return NDIS_STATUS_NOT_ACCEPTED;
+
+	if (poid_par_priv->information_buf_len < sizeof(struct rf_reg_param))
+		return NDIS_STATUS_INVALID_LENGTH;
+
+	pbbreg = (struct rf_reg_param *)(poid_par_priv->information_buf);
+
+	if (pbbreg->path >= MAX_RF_PATH_NUMS)
+		return NDIS_STATUS_NOT_ACCEPTED;
+	if (pbbreg->offset > 0xFF)
+		return NDIS_STATUS_NOT_ACCEPTED;
+	if (pbbreg->value > 0xFFFFF)
+		return NDIS_STATUS_NOT_ACCEPTED;
+
+	path = (u8)pbbreg->path;
+	offset = (u8)pbbreg->offset;
+	value = pbbreg->value;
+
+
+	_irqlevel_changed_(&oldirql, LOWER);
+	write_rfreg(Adapter, path, offset, value);
+	_irqlevel_changed_(&oldirql, RAISE);
+
+
+	return status;
+}
+/* ------------------------------------------------------------------------------ */
+NDIS_STATUS oid_rt_pro_read_rf_reg_hdl(struct oid_par_priv *poid_par_priv)
+{
+#ifdef PLATFORM_OS_XP
+	_irqL oldirql;
+#endif
+	struct rf_reg_param *pbbreg;
+	u8 path;
+	u8 offset;
+	u32 value;
+	PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context);
+	NDIS_STATUS status = NDIS_STATUS_SUCCESS;
+
+
+
+	if (poid_par_priv->type_of_oid != QUERY_OID)
+		return NDIS_STATUS_NOT_ACCEPTED;
+
+	if (poid_par_priv->information_buf_len < sizeof(struct rf_reg_param))
+		return NDIS_STATUS_INVALID_LENGTH;
+
+	pbbreg = (struct rf_reg_param *)(poid_par_priv->information_buf);
+
+	if (pbbreg->path >= MAX_RF_PATH_NUMS)
+		return NDIS_STATUS_NOT_ACCEPTED;
+	if (pbbreg->offset > 0xFF)
+		return NDIS_STATUS_NOT_ACCEPTED;
+
+	path = (u8)pbbreg->path;
+	offset = (u8)pbbreg->offset;
+
+	_irqlevel_changed_(&oldirql, LOWER);
+	value = read_rfreg(Adapter, path, offset);
+	_irqlevel_changed_(&oldirql, RAISE);
+
+	pbbreg->value = value;
+
+	*poid_par_priv->bytes_rw = poid_par_priv->information_buf_len;
+
+
+
+	return status;
+}
+/* ****************  oid_rtl_seg_81_87_00   section end****************
+ * ------------------------------------------------------------------------------ */
+
+/* ****************  oid_rtl_seg_81_80_00   section start ****************
+ * ------------------------------------------------------------------------------ */
+NDIS_STATUS oid_rt_pro_set_data_rate_hdl(struct oid_par_priv *poid_par_priv)
+{
+#ifdef PLATFORM_OS_XP
+	_irqL		oldirql;
+#endif
+	u32		ratevalue;/* 4 */
+	NDIS_STATUS	status = NDIS_STATUS_SUCCESS;
+	PADAPTER	Adapter = (PADAPTER)(poid_par_priv->adapter_context);
+
+
+
+	if (poid_par_priv->type_of_oid != SET_OID)
+		return NDIS_STATUS_NOT_ACCEPTED;
+
+	if (poid_par_priv->information_buf_len != sizeof(u32))
+		return NDIS_STATUS_INVALID_LENGTH;
+
+	ratevalue = *((u32 *)poid_par_priv->information_buf); /* 4 */
+	if (ratevalue >= MPT_RATE_LAST)
+		return NDIS_STATUS_INVALID_DATA;
+
+	Adapter->mppriv.rateidx = ratevalue;
+
+	_irqlevel_changed_(&oldirql, LOWER);
+	SetDataRate(Adapter);
+	_irqlevel_changed_(&oldirql, RAISE);
+
+
+	return status;
+}
+/* ------------------------------------------------------------------------------ */
+NDIS_STATUS oid_rt_pro_start_test_hdl(struct oid_par_priv *poid_par_priv)
+{
+#ifdef PLATFORM_OS_XP
+	_irqL		oldirql;
+#endif
+	u32		mode;
+	NDIS_STATUS	status = NDIS_STATUS_SUCCESS;
+	PADAPTER	Adapter = (PADAPTER)(poid_par_priv->adapter_context);
+
+
+
+	if (Adapter->registrypriv.mp_mode == 0)
+		return NDIS_STATUS_NOT_ACCEPTED;
+
+	if (poid_par_priv->type_of_oid != SET_OID)
+		return NDIS_STATUS_NOT_ACCEPTED;
+
+	_irqlevel_changed_(&oldirql, LOWER);
+
+	/* IQCalibrateBcut(Adapter); */
+
+	mode = *((u32 *)poid_par_priv->information_buf);
+	Adapter->mppriv.mode = mode;/* 1 for loopback */
+
+	if (mp_start_test(Adapter) == _FAIL) {
+		status = NDIS_STATUS_NOT_ACCEPTED;
+		goto exit;
+	}
+
+exit:
+	_irqlevel_changed_(&oldirql, RAISE);
+
+
+
+	return status;
+}
+/* ------------------------------------------------------------------------------ */
+NDIS_STATUS oid_rt_pro_stop_test_hdl(struct oid_par_priv *poid_par_priv)
+{
+#ifdef PLATFORM_OS_XP
+	_irqL		oldirql;
+#endif
+	NDIS_STATUS	status = NDIS_STATUS_SUCCESS;
+	PADAPTER	Adapter = (PADAPTER)(poid_par_priv->adapter_context);
+
+
+
+	if (poid_par_priv->type_of_oid != SET_OID)
+		return NDIS_STATUS_NOT_ACCEPTED;
+
+	_irqlevel_changed_(&oldirql, LOWER);
+	mp_stop_test(Adapter);
+	_irqlevel_changed_(&oldirql, RAISE);
+
+
+
+	return status;
+}
+/* ------------------------------------------------------------------------------ */
+NDIS_STATUS oid_rt_pro_set_channel_direct_call_hdl(struct oid_par_priv *poid_par_priv)
+{
+#ifdef PLATFORM_OS_XP
+	_irqL		oldirql;
+#endif
+	u32		Channel;
+	NDIS_STATUS	status = NDIS_STATUS_SUCCESS;
+	PADAPTER	Adapter = (PADAPTER)(poid_par_priv->adapter_context);
+
+
+
+	if (poid_par_priv->information_buf_len != sizeof(u32))
+		return NDIS_STATUS_INVALID_LENGTH;
+
+	if (poid_par_priv->type_of_oid == QUERY_OID) {
+		*((u32 *)poid_par_priv->information_buf) = Adapter->mppriv.channel;
+		return NDIS_STATUS_SUCCESS;
+	}
+
+	if (poid_par_priv->type_of_oid != SET_OID)
+		return NDIS_STATUS_NOT_ACCEPTED;
+
+	Channel = *((u32 *)poid_par_priv->information_buf);
+	if (Channel > 14)
+		return NDIS_STATUS_NOT_ACCEPTED;
+	Adapter->mppriv.channel = Channel;
+
+	_irqlevel_changed_(&oldirql, LOWER);
+	SetChannel(Adapter);
+	_irqlevel_changed_(&oldirql, RAISE);
+
+
+	return status;
+}
+/* ------------------------------------------------------------------------------ */
+NDIS_STATUS oid_rt_set_bandwidth_hdl(struct oid_par_priv *poid_par_priv)
+{
+#ifdef PLATFORM_OS_XP
+	_irqL		oldirql;
+#endif
+	u16		bandwidth;
+	u16		channel_offset;
+	NDIS_STATUS	status = NDIS_STATUS_SUCCESS;
+	PADAPTER	padapter = (PADAPTER)(poid_par_priv->adapter_context);
+
+
+
+	if (poid_par_priv->type_of_oid != SET_OID)
+		return NDIS_STATUS_NOT_ACCEPTED;
+
+	if (poid_par_priv->information_buf_len < sizeof(u32))
+		return NDIS_STATUS_INVALID_LENGTH;
+
+	bandwidth = *((u32 *)poid_par_priv->information_buf); /* 4 */
+	channel_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
+
+	if (bandwidth != CHANNEL_WIDTH_40)
+		bandwidth = CHANNEL_WIDTH_20;
+	padapter->mppriv.bandwidth = (u8)bandwidth;
+	padapter->mppriv.prime_channel_offset = (u8)channel_offset;
+
+	_irqlevel_changed_(&oldirql, LOWER);
+	SetBandwidth(padapter);
+	_irqlevel_changed_(&oldirql, RAISE);
+
+
+
+	return status;
+}
+/* ------------------------------------------------------------------------------ */
+NDIS_STATUS oid_rt_pro_set_antenna_bb_hdl(struct oid_par_priv *poid_par_priv)
+{
+#ifdef PLATFORM_OS_XP
+	_irqL		oldirql;
+#endif
+	u32		antenna;
+	NDIS_STATUS	status = NDIS_STATUS_SUCCESS;
+	PADAPTER	Adapter = (PADAPTER)(poid_par_priv->adapter_context);
+
+
+
+	if (poid_par_priv->information_buf_len != sizeof(u32))
+		return NDIS_STATUS_INVALID_LENGTH;
+
+	if (poid_par_priv->type_of_oid == SET_OID) {
+		antenna = *(u32 *)poid_par_priv->information_buf;
+
+		Adapter->mppriv.antenna_tx = (u16)((antenna & 0xFFFF0000) >> 16);
+		Adapter->mppriv.antenna_rx = (u16)(antenna & 0x0000FFFF);
+
+		_irqlevel_changed_(&oldirql, LOWER);
+		SetAntenna(Adapter);
+		_irqlevel_changed_(&oldirql, RAISE);
+	} else {
+		antenna = (Adapter->mppriv.antenna_tx << 16) | Adapter->mppriv.antenna_rx;
+		*(u32 *)poid_par_priv->information_buf = antenna;
+	}
+
+
+	return status;
+}
+
+NDIS_STATUS oid_rt_pro_set_tx_power_control_hdl(struct oid_par_priv *poid_par_priv)
+{
+#ifdef PLATFORM_OS_XP
+	_irqL		oldirql;
+#endif
+	u32		tx_pwr_idx;
+	NDIS_STATUS	status = NDIS_STATUS_SUCCESS;
+	PADAPTER	Adapter = (PADAPTER)(poid_par_priv->adapter_context);
+
+
+
+	if (poid_par_priv->type_of_oid != SET_OID)
+		return NDIS_STATUS_NOT_ACCEPTED;
+
+	if (poid_par_priv->information_buf_len != sizeof(u32))
+		return NDIS_STATUS_INVALID_LENGTH;
+
+	tx_pwr_idx = *((u32 *)poid_par_priv->information_buf);
+	if (tx_pwr_idx > MAX_TX_PWR_INDEX_N_MODE)
+		return NDIS_STATUS_NOT_ACCEPTED;
+
+	Adapter->mppriv.txpoweridx = (u8)tx_pwr_idx;
+
+
+	_irqlevel_changed_(&oldirql, LOWER);
+	SetTxPower(Adapter);
+	_irqlevel_changed_(&oldirql, RAISE);
+
+
+	return status;
+}
+
+/* ------------------------------------------------------------------------------
+ * ****************  oid_rtl_seg_81_80_20   section start ****************
+ * ------------------------------------------------------------------------------ */
+NDIS_STATUS oid_rt_pro_query_tx_packet_sent_hdl(struct oid_par_priv *poid_par_priv)
+{
+	NDIS_STATUS	status = NDIS_STATUS_SUCCESS;
+	PADAPTER	Adapter = (PADAPTER)(poid_par_priv->adapter_context);
+
+
+	if (poid_par_priv->type_of_oid != QUERY_OID) {
+		status = NDIS_STATUS_NOT_ACCEPTED;
+		return status;
+	}
+
+	if (poid_par_priv->information_buf_len == sizeof(ULONG)) {
+		*(ULONG *)poid_par_priv->information_buf =  Adapter->mppriv.tx_pktcount;
+		*poid_par_priv->bytes_rw = poid_par_priv->information_buf_len;
+	} else
+		status = NDIS_STATUS_INVALID_LENGTH;
+
+
+	return status;
+}
+/* ------------------------------------------------------------------------------ */
+NDIS_STATUS oid_rt_pro_query_rx_packet_received_hdl(struct oid_par_priv *poid_par_priv)
+{
+	NDIS_STATUS	status = NDIS_STATUS_SUCCESS;
+	PADAPTER	Adapter = (PADAPTER)(poid_par_priv->adapter_context);
+
+
+	if (poid_par_priv->type_of_oid != QUERY_OID) {
+		status = NDIS_STATUS_NOT_ACCEPTED;
+		return status;
+	}
+	if (poid_par_priv->information_buf_len == sizeof(ULONG)) {
+		*(ULONG *)poid_par_priv->information_buf =  Adapter->mppriv.rx_pktcount;
+		*poid_par_priv->bytes_rw = poid_par_priv->information_buf_len;
+	} else
+		status = NDIS_STATUS_INVALID_LENGTH;
+
+
+	return status;
+}
+/* ------------------------------------------------------------------------------ */
+NDIS_STATUS oid_rt_pro_query_rx_packet_crc32_error_hdl(struct oid_par_priv *poid_par_priv)
+{
+	NDIS_STATUS	status = NDIS_STATUS_SUCCESS;
+	PADAPTER	Adapter = (PADAPTER)(poid_par_priv->adapter_context);
+
+
+	if (poid_par_priv->type_of_oid != QUERY_OID) {
+		status = NDIS_STATUS_NOT_ACCEPTED;
+		return status;
+	}
+	if (poid_par_priv->information_buf_len == sizeof(ULONG)) {
+		*(ULONG *)poid_par_priv->information_buf =  Adapter->mppriv.rx_crcerrpktcount;
+		*poid_par_priv->bytes_rw = poid_par_priv->information_buf_len;
+	} else
+		status = NDIS_STATUS_INVALID_LENGTH;
+
+
+	return status;
+}
+/* ------------------------------------------------------------------------------ */
+
+NDIS_STATUS oid_rt_pro_reset_tx_packet_sent_hdl(struct oid_par_priv *poid_par_priv)
+{
+	NDIS_STATUS	status = NDIS_STATUS_SUCCESS;
+	PADAPTER	Adapter = (PADAPTER)(poid_par_priv->adapter_context);
+
+
+	if (poid_par_priv->type_of_oid != SET_OID) {
+		status = NDIS_STATUS_NOT_ACCEPTED;
+		return status;
+	}
+
+	Adapter->mppriv.tx_pktcount = 0;
+
+
+	return status;
+}
+/* ------------------------------------------------------------------------------ */
+NDIS_STATUS oid_rt_pro_reset_rx_packet_received_hdl(struct oid_par_priv *poid_par_priv)
+{
+	NDIS_STATUS	status = NDIS_STATUS_SUCCESS;
+	PADAPTER	Adapter = (PADAPTER)(poid_par_priv->adapter_context);
+
+
+	if (poid_par_priv->type_of_oid != SET_OID) {
+		status = NDIS_STATUS_NOT_ACCEPTED;
+		return status;
+	}
+
+	if (poid_par_priv->information_buf_len == sizeof(ULONG)) {
+		Adapter->mppriv.rx_pktcount = 0;
+		Adapter->mppriv.rx_crcerrpktcount = 0;
+	} else
+		status = NDIS_STATUS_INVALID_LENGTH;
+
+
+	return status;
+}
+/* ------------------------------------------------------------------------------ */
+NDIS_STATUS oid_rt_reset_phy_rx_packet_count_hdl(struct oid_par_priv *poid_par_priv)
+{
+#ifdef PLATFORM_OS_XP
+	_irqL		oldirql;
+#endif
+	NDIS_STATUS	status = NDIS_STATUS_SUCCESS;
+	PADAPTER	Adapter = (PADAPTER)(poid_par_priv->adapter_context);
+
+
+	if (poid_par_priv->type_of_oid != SET_OID) {
+		status = NDIS_STATUS_NOT_ACCEPTED;
+		return status;
+	}
+
+	_irqlevel_changed_(&oldirql, LOWER);
+	ResetPhyRxPktCount(Adapter);
+	_irqlevel_changed_(&oldirql, RAISE);
+
+
+	return status;
+}
+/* ------------------------------------------------------------------------------ */
+NDIS_STATUS oid_rt_get_phy_rx_packet_received_hdl(struct oid_par_priv *poid_par_priv)
+{
+#ifdef PLATFORM_OS_XP
+	_irqL		oldirql;
+#endif
+	NDIS_STATUS	status = NDIS_STATUS_SUCCESS;
+	PADAPTER	Adapter = (PADAPTER)(poid_par_priv->adapter_context);
+
+
+
+	if (poid_par_priv->type_of_oid != QUERY_OID)
+		return NDIS_STATUS_NOT_ACCEPTED;
+
+	if (poid_par_priv->information_buf_len != sizeof(ULONG))
+		return NDIS_STATUS_INVALID_LENGTH;
+
+	_irqlevel_changed_(&oldirql, LOWER);
+	*(ULONG *)poid_par_priv->information_buf = GetPhyRxPktReceived(Adapter);
+	_irqlevel_changed_(&oldirql, RAISE);
+
+	*poid_par_priv->bytes_rw = poid_par_priv->information_buf_len;
+
+
+
+	return status;
+}
+/* ------------------------------------------------------------------------------ */
+NDIS_STATUS oid_rt_get_phy_rx_packet_crc32_error_hdl(struct oid_par_priv *poid_par_priv)
+{
+#ifdef PLATFORM_OS_XP
+	_irqL		oldirql;
+#endif
+	NDIS_STATUS	status = NDIS_STATUS_SUCCESS;
+	PADAPTER	Adapter = (PADAPTER)(poid_par_priv->adapter_context);
+
+
+
+	if (poid_par_priv->type_of_oid != QUERY_OID)
+		return NDIS_STATUS_NOT_ACCEPTED;
+
+
+	if (poid_par_priv->information_buf_len != sizeof(ULONG))
+		return NDIS_STATUS_INVALID_LENGTH;
+
+	_irqlevel_changed_(&oldirql, LOWER);
+	*(ULONG *)poid_par_priv->information_buf = GetPhyRxPktCRC32Error(Adapter);
+	_irqlevel_changed_(&oldirql, RAISE);
+
+	*poid_par_priv->bytes_rw = poid_par_priv->information_buf_len;
+
+
+
+	return status;
+}
+/* ****************  oid_rtl_seg_81_80_20   section end **************** */
+NDIS_STATUS oid_rt_pro_set_continuous_tx_hdl(struct oid_par_priv *poid_par_priv)
+{
+#ifdef PLATFORM_OS_XP
+	_irqL		oldirql;
+#endif
+	u32		bStartTest;
+	NDIS_STATUS	status = NDIS_STATUS_SUCCESS;
+	PADAPTER	Adapter = (PADAPTER)(poid_par_priv->adapter_context);
+
+
+
+	if (poid_par_priv->type_of_oid != SET_OID)
+		return NDIS_STATUS_NOT_ACCEPTED;
+
+	bStartTest = *((u32 *)poid_par_priv->information_buf);
+
+	_irqlevel_changed_(&oldirql, LOWER);
+	SetContinuousTx(Adapter, (u8)bStartTest);
+	if (bStartTest) {
+		struct mp_priv *pmp_priv = &Adapter->mppriv;
+		if (pmp_priv->tx.stop == 0) {
+			pmp_priv->tx.stop = 1;
+			RTW_INFO("%s: pkt tx is running...\n", __func__);
+			rtw_msleep_os(5);
+		}
+		pmp_priv->tx.stop = 0;
+		pmp_priv->tx.count = 1;
+		SetPacketTx(Adapter);
+	}
+	_irqlevel_changed_(&oldirql, RAISE);
+
+
+	return status;
+}
+
+NDIS_STATUS oid_rt_pro_set_single_carrier_tx_hdl(struct oid_par_priv *poid_par_priv)
+{
+#ifdef PLATFORM_OS_XP
+	_irqL		oldirql;
+#endif
+	u32		bStartTest;
+	NDIS_STATUS	status = NDIS_STATUS_SUCCESS;
+	PADAPTER	Adapter = (PADAPTER)(poid_par_priv->adapter_context);
+
+
+
+	if (poid_par_priv->type_of_oid != SET_OID)
+		return NDIS_STATUS_NOT_ACCEPTED;
+
+	bStartTest = *((u32 *)poid_par_priv->information_buf);
+
+	_irqlevel_changed_(&oldirql, LOWER);
+	SetSingleCarrierTx(Adapter, (u8)bStartTest);
+	if (bStartTest) {
+		struct mp_priv *pmp_priv = &Adapter->mppriv;
+		if (pmp_priv->tx.stop == 0) {
+			pmp_priv->tx.stop = 1;
+			RTW_INFO("%s: pkt tx is running...\n", __func__);
+			rtw_msleep_os(5);
+		}
+		pmp_priv->tx.stop = 0;
+		pmp_priv->tx.count = 1;
+		SetPacketTx(Adapter);
+	}
+	_irqlevel_changed_(&oldirql, RAISE);
+
+
+	return status;
+}
+
+NDIS_STATUS oid_rt_pro_set_carrier_suppression_tx_hdl(struct oid_par_priv *poid_par_priv)
+{
+#ifdef PLATFORM_OS_XP
+	_irqL		oldirql;
+#endif
+	u32		bStartTest;
+	NDIS_STATUS	status = NDIS_STATUS_SUCCESS;
+	PADAPTER	Adapter = (PADAPTER)(poid_par_priv->adapter_context);
+
+
+
+	if (poid_par_priv->type_of_oid != SET_OID)
+		return NDIS_STATUS_NOT_ACCEPTED;
+
+	bStartTest = *((u32 *)poid_par_priv->information_buf);
+
+	_irqlevel_changed_(&oldirql, LOWER);
+	SetCarrierSuppressionTx(Adapter, (u8)bStartTest);
+	if (bStartTest) {
+		struct mp_priv *pmp_priv = &Adapter->mppriv;
+		if (pmp_priv->tx.stop == 0) {
+			pmp_priv->tx.stop = 1;
+			RTW_INFO("%s: pkt tx is running...\n", __func__);
+			rtw_msleep_os(5);
+		}
+		pmp_priv->tx.stop = 0;
+		pmp_priv->tx.count = 1;
+		SetPacketTx(Adapter);
+	}
+	_irqlevel_changed_(&oldirql, RAISE);
+
+
+	return status;
+}
+
+NDIS_STATUS oid_rt_pro_set_single_tone_tx_hdl(struct oid_par_priv *poid_par_priv)
+{
+#ifdef PLATFORM_OS_XP
+	_irqL		oldirql;
+#endif
+	u32		bStartTest;
+	NDIS_STATUS	status = NDIS_STATUS_SUCCESS;
+	PADAPTER	Adapter = (PADAPTER)(poid_par_priv->adapter_context);
+
+
+
+	if (poid_par_priv->type_of_oid != SET_OID)
+		return NDIS_STATUS_NOT_ACCEPTED;
+
+	bStartTest = *((u32 *)poid_par_priv->information_buf);
+
+	_irqlevel_changed_(&oldirql, LOWER);
+	SetSingleToneTx(Adapter, (u8)bStartTest);
+	_irqlevel_changed_(&oldirql, RAISE);
+
+
+	return status;
+}
+
+NDIS_STATUS oid_rt_pro_set_modulation_hdl(struct oid_par_priv *poid_par_priv)
+{
+	return 0;
+}
+
+NDIS_STATUS oid_rt_pro_trigger_gpio_hdl(struct oid_par_priv *poid_par_priv)
+{
+	PADAPTER	Adapter = (PADAPTER)(poid_par_priv->adapter_context);
+
+#ifdef PLATFORM_OS_XP
+	_irqL		oldirql;
+#endif
+	NDIS_STATUS	status = NDIS_STATUS_SUCCESS;
+
+	if (poid_par_priv->type_of_oid != SET_OID)
+		return NDIS_STATUS_NOT_ACCEPTED;
+
+	_irqlevel_changed_(&oldirql, LOWER);
+	rtw_hal_set_hwreg(Adapter, HW_VAR_TRIGGER_GPIO_0, 0);
+	_irqlevel_changed_(&oldirql, RAISE);
+
+
+	return status;
+}
+/* ****************  oid_rtl_seg_81_80_00   section end ****************
+ * ------------------------------------------------------------------------------ */
+NDIS_STATUS oid_rt_pro8711_join_bss_hdl(struct oid_par_priv *poid_par_priv)
+{
+#if 0
+	PADAPTER	Adapter = (PADAPTER)(poid_par_priv->adapter_context);
+
+#ifdef PLATFORM_OS_XP
+	_irqL		oldirql;
+#endif
+	NDIS_STATUS	status = NDIS_STATUS_SUCCESS;
+
+	PNDIS_802_11_SSID pssid;
+
+
+	if (poid_par_priv->type_of_oid != SET_OID)
+		return NDIS_STATUS_NOT_ACCEPTED;
+
+	*poid_par_priv->bytes_needed = (u32)sizeof(NDIS_802_11_SSID);
+	*poid_par_priv->bytes_rw = 0;
+	if (poid_par_priv->information_buf_len < *poid_par_priv->bytes_needed)
+		return NDIS_STATUS_INVALID_LENGTH;
+
+	pssid = (PNDIS_802_11_SSID)poid_par_priv->information_buf;
+
+	_irqlevel_changed_(&oldirql, LOWER);
+
+	if (mp_start_joinbss(Adapter, pssid) == _FAIL)
+		status = NDIS_STATUS_NOT_ACCEPTED;
+
+	_irqlevel_changed_(&oldirql, RAISE);
+
+	*poid_par_priv->bytes_rw = sizeof(NDIS_802_11_SSID);
+
+
+	return status;
+#else
+	return 0;
+#endif
+}
+/* ------------------------------------------------------------------------------ */
+NDIS_STATUS oid_rt_pro_read_register_hdl(struct oid_par_priv *poid_par_priv)
+{
+#ifdef PLATFORM_OS_XP
+	_irqL		oldirql;
+#endif
+	pRW_Reg	RegRWStruct;
+	u32		offset, width;
+	NDIS_STATUS	status = NDIS_STATUS_SUCCESS;
+	PADAPTER	Adapter = (PADAPTER)(poid_par_priv->adapter_context);
+
+
+
+	if (poid_par_priv->type_of_oid != QUERY_OID)
+		return NDIS_STATUS_NOT_ACCEPTED;
+
+	RegRWStruct = (pRW_Reg)poid_par_priv->information_buf;
+	offset = RegRWStruct->offset;
+	width = RegRWStruct->width;
+
+	if (offset > 0xFFF)
+		return NDIS_STATUS_NOT_ACCEPTED;
+
+	_irqlevel_changed_(&oldirql, LOWER);
+
+	switch (width) {
+	case 1:
+		RegRWStruct->value = rtw_read8(Adapter, offset);
+		break;
+	case 2:
+		RegRWStruct->value = rtw_read16(Adapter, offset);
+		break;
+	default:
+		width = 4;
+		RegRWStruct->value = rtw_read32(Adapter, offset);
+		break;
+	}
+
+	_irqlevel_changed_(&oldirql, RAISE);
+
+	*poid_par_priv->bytes_rw = width;
+
+
+	return status;
+}
+/* ------------------------------------------------------------------------------ */
+NDIS_STATUS oid_rt_pro_write_register_hdl(struct oid_par_priv *poid_par_priv)
+{
+#ifdef PLATFORM_OS_XP
+	_irqL		oldirql;
+#endif
+	pRW_Reg	RegRWStruct;
+	u32		offset, width, value;
+	NDIS_STATUS	status = NDIS_STATUS_SUCCESS;
+	PADAPTER	padapter = (PADAPTER)(poid_par_priv->adapter_context);
+
+
+
+	if (poid_par_priv->type_of_oid != SET_OID)
+		return NDIS_STATUS_NOT_ACCEPTED;
+
+	RegRWStruct = (pRW_Reg)poid_par_priv->information_buf;
+	offset = RegRWStruct->offset;
+	width = RegRWStruct->width;
+	value = RegRWStruct->value;
+
+	if (offset > 0xFFF)
+		return NDIS_STATUS_NOT_ACCEPTED;
+
+	_irqlevel_changed_(&oldirql, LOWER);
+
+	switch (RegRWStruct->width) {
+	case 1:
+		if (value > 0xFF) {
+			status = NDIS_STATUS_NOT_ACCEPTED;
+			break;
+		}
+		rtw_write8(padapter, offset, (u8)value);
+		break;
+	case 2:
+		if (value > 0xFFFF) {
+			status = NDIS_STATUS_NOT_ACCEPTED;
+			break;
+		}
+		rtw_write16(padapter, offset, (u16)value);
+		break;
+	case 4:
+		rtw_write32(padapter, offset, value);
+		break;
+	default:
+		status = NDIS_STATUS_NOT_ACCEPTED;
+		break;
+	}
+
+	_irqlevel_changed_(&oldirql, RAISE);
+
+
+
+	return status;
+}
+/* ------------------------------------------------------------------------------ */
+NDIS_STATUS oid_rt_pro_burst_read_register_hdl(struct oid_par_priv *poid_par_priv)
+{
+#if 0
+#ifdef PLATFORM_OS_XP
+	_irqL		oldirql;
+#endif
+	pBurst_RW_Reg	pBstRwReg;
+	NDIS_STATUS	status = NDIS_STATUS_SUCCESS;
+	PADAPTER	padapter = (PADAPTER)(poid_par_priv->adapter_context);
+
+
+
+	if (poid_par_priv->type_of_oid != QUERY_OID)
+		return NDIS_STATUS_NOT_ACCEPTED;
+
+	pBstRwReg = (pBurst_RW_Reg)poid_par_priv->information_buf;
+
+	_irqlevel_changed_(&oldirql, LOWER);
+	rtw_read_mem(padapter, pBstRwReg->offset, (u32)pBstRwReg->len, pBstRwReg->Data);
+	_irqlevel_changed_(&oldirql, RAISE);
+
+	*poid_par_priv->bytes_rw = poid_par_priv->information_buf_len;
+
+
+
+	return status;
+#else
+	return 0;
+#endif
+}
+/* ------------------------------------------------------------------------------ */
+NDIS_STATUS oid_rt_pro_burst_write_register_hdl(struct oid_par_priv *poid_par_priv)
+{
+#if 0
+#ifdef PLATFORM_OS_XP
+	_irqL		oldirql;
+#endif
+	pBurst_RW_Reg	pBstRwReg;
+	NDIS_STATUS	status = NDIS_STATUS_SUCCESS;
+	PADAPTER	padapter = (PADAPTER)(poid_par_priv->adapter_context);
+
+
+
+	if (poid_par_priv->type_of_oid != SET_OID)
+		return NDIS_STATUS_NOT_ACCEPTED;
+
+	pBstRwReg = (pBurst_RW_Reg)poid_par_priv->information_buf;
+
+	_irqlevel_changed_(&oldirql, LOWER);
+	rtw_write_mem(padapter, pBstRwReg->offset, (u32)pBstRwReg->len, pBstRwReg->Data);
+	_irqlevel_changed_(&oldirql, RAISE);
+
+
+
+	return status;
+#else
+	return 0;
+#endif
+}
+/* ------------------------------------------------------------------------------ */
+NDIS_STATUS oid_rt_pro_write_txcmd_hdl(struct oid_par_priv *poid_par_priv)
+{
+#if 0
+	NDIS_STATUS	status = NDIS_STATUS_SUCCESS;
+
+	PADAPTER	Adapter = (PADAPTER)(poid_par_priv->adapter_context);
+
+#ifdef PLATFORM_OS_XP
+	_irqL		oldirql;
+#endif
+
+	TX_CMD_Desc	*TxCmd_Info;
+
+
+	if (poid_par_priv->type_of_oid != SET_OID)
+		return NDIS_STATUS_NOT_ACCEPTED;
+
+
+	TxCmd_Info = (TX_CMD_Desc *)poid_par_priv->information_buf;
+
+
+		 _irqlevel_changed_(&oldirql, LOWER);
+
+		rtw_write32(Adapter, TxCmd_Info->offset + 0, (unsigned int)TxCmd_Info->TxCMD.value[0]);
+		rtw_write32(Adapter, TxCmd_Info->offset + 4, (unsigned int)TxCmd_Info->TxCMD.value[1]);
+
+		 _irqlevel_changed_(&oldirql, RAISE);
+
+
+
+		 return status;
+#else
+	return 0;
+#endif
+}
+
+/* ------------------------------------------------------------------------------ */
+NDIS_STATUS oid_rt_pro_read16_eeprom_hdl(struct oid_par_priv *poid_par_priv)
+{
+#if 0
+#ifdef PLATFORM_OS_XP
+	_irqL		oldirql;
+#endif
+	pEEPROM_RWParam pEEPROM;
+	NDIS_STATUS	status = NDIS_STATUS_SUCCESS;
+	PADAPTER	padapter = (PADAPTER)(poid_par_priv->adapter_context);
+
+
+
+	if (poid_par_priv->type_of_oid != QUERY_OID)
+		return NDIS_STATUS_NOT_ACCEPTED;
+
+	pEEPROM = (pEEPROM_RWParam)poid_par_priv->information_buf;
+
+	_irqlevel_changed_(&oldirql, LOWER);
+	pEEPROM->value = eeprom_read16(padapter, (u16)(pEEPROM->offset >> 1));
+	_irqlevel_changed_(&oldirql, RAISE);
+
+	*poid_par_priv->bytes_rw = poid_par_priv->information_buf_len;
+
+
+
+	return status;
+#else
+	return 0;
+#endif
+}
+
+/* ------------------------------------------------------------------------------ */
+NDIS_STATUS oid_rt_pro_write16_eeprom_hdl(struct oid_par_priv *poid_par_priv)
+{
+#if 0
+#ifdef PLATFORM_OS_XP
+	_irqL		oldirql;
+#endif
+	pEEPROM_RWParam pEEPROM;
+	NDIS_STATUS	status = NDIS_STATUS_SUCCESS;
+	PADAPTER	padapter = (PADAPTER)(poid_par_priv->adapter_context);
+
+
+
+	if (poid_par_priv->type_of_oid != SET_OID)
+		return NDIS_STATUS_NOT_ACCEPTED;
+
+	pEEPROM = (pEEPROM_RWParam)poid_par_priv->information_buf;
+
+	_irqlevel_changed_(&oldirql, LOWER);
+	eeprom_write16(padapter, (u16)(pEEPROM->offset >> 1), pEEPROM->value);
+	_irqlevel_changed_(&oldirql, RAISE);
+
+	*poid_par_priv->bytes_rw = poid_par_priv->information_buf_len;
+
+
+	return status;
+#else
+	return 0;
+#endif
+}
+/* ------------------------------------------------------------------------------ */
+NDIS_STATUS oid_rt_pro8711_wi_poll_hdl(struct oid_par_priv *poid_par_priv)
+{
+#if 0
+	PADAPTER	Adapter = (PADAPTER)(poid_par_priv->adapter_context);
+
+	NDIS_STATUS	status = NDIS_STATUS_SUCCESS;
+
+	struct mp_wiparam *pwi_param;
+
+
+	if (poid_par_priv->type_of_oid != QUERY_OID)
+		return NDIS_STATUS_NOT_ACCEPTED;
+
+	if (poid_par_priv->information_buf_len < sizeof(struct mp_wiparam))
+		return NDIS_STATUS_INVALID_LENGTH;
+
+	if (Adapter->mppriv.workparam.bcompleted == _FALSE)
+		return NDIS_STATUS_NOT_ACCEPTED;
+
+	pwi_param = (struct mp_wiparam *)poid_par_priv->information_buf;
+
+	_rtw_memcpy(pwi_param, &Adapter->mppriv.workparam, sizeof(struct mp_wiparam));
+	Adapter->mppriv.act_in_progress = _FALSE;
+	*poid_par_priv->bytes_rw = poid_par_priv->information_buf_len;
+
+
+	return status;
+#else
+	return 0;
+#endif
+}
+/* ------------------------------------------------------------------------------ */
+NDIS_STATUS oid_rt_pro8711_pkt_loss_hdl(struct oid_par_priv *poid_par_priv)
+{
+#if 0
+	PADAPTER	Adapter = (PADAPTER)(poid_par_priv->adapter_context);
+
+	NDIS_STATUS	status = NDIS_STATUS_SUCCESS;
+
+
+
+	if (poid_par_priv->type_of_oid != QUERY_OID)
+		return NDIS_STATUS_NOT_ACCEPTED;
+
+	if (poid_par_priv->information_buf_len < sizeof(uint) * 2) {
+		return NDIS_STATUS_INVALID_LENGTH;
+	}
+
+	if (*(uint *)poid_par_priv->information_buf == 1) /* init==1 */
+		Adapter->mppriv.rx_pktloss = 0;
+
+	*((uint *)poid_par_priv->information_buf + 1) = Adapter->mppriv.rx_pktloss;
+	*poid_par_priv->bytes_rw = poid_par_priv->information_buf_len;
+
+
+	return status;
+#else
+	return 0;
+#endif
+}
+/* ------------------------------------------------------------------------------ */
+NDIS_STATUS oid_rt_rd_attrib_mem_hdl(struct oid_par_priv *poid_par_priv)
+{
+#if 0
+	PADAPTER	Adapter = (PADAPTER)(poid_par_priv->adapter_context);
+	struct io_queue *pio_queue = (struct io_queue *)Adapter->pio_queue;
+	struct intf_hdl	*pintfhdl = &pio_queue->intf;
+
+#ifdef PLATFORM_OS_XP
+	_irqL		oldirql;
+#endif
+	NDIS_STATUS	status = NDIS_STATUS_SUCCESS;
+
+#ifdef CONFIG_SDIO_HCI
+	void (*_attrib_read)(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *pmem);
+#endif
+
+
+
+	if (poid_par_priv->type_of_oid != QUERY_OID)
+		return NDIS_STATUS_NOT_ACCEPTED;
+
+#ifdef CONFIG_SDIO_HCI
+	_irqlevel_changed_(&oldirql, LOWER);
+	{
+		u32 *plmem = (u32 *)poid_par_priv->information_buf + 2;
+		_attrib_read = pintfhdl->io_ops._attrib_read;
+		_attrib_read(pintfhdl, *((u32 *)poid_par_priv->information_buf),
+			*((u32 *)poid_par_priv->information_buf + 1), (u8 *)plmem);
+		*poid_par_priv->bytes_rw = poid_par_priv->information_buf_len;
+	}
+	_irqlevel_changed_(&oldirql, RAISE);
+#endif
+
+
+	return status;
+#else
+	return 0;
+#endif
+}
+/* ------------------------------------------------------------------------------ */
+NDIS_STATUS oid_rt_wr_attrib_mem_hdl(struct oid_par_priv *poid_par_priv)
+{
+#if 0
+	PADAPTER	Adapter = (PADAPTER)(poid_par_priv->adapter_context);
+	struct io_queue *pio_queue = (struct io_queue *)Adapter->pio_queue;
+	struct intf_hdl	*pintfhdl = &pio_queue->intf;
+
+#ifdef PLATFORM_OS_XP
+	_irqL		oldirql;
+#endif
+	NDIS_STATUS	status = NDIS_STATUS_SUCCESS;
+
+#ifdef CONFIG_SDIO_HCI
+	void (*_attrib_write)(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *pmem);
+#endif
+
+
+	if (poid_par_priv->type_of_oid != SET_OID)
+		return NDIS_STATUS_NOT_ACCEPTED;
+
+#ifdef CONFIG_SDIO_HCI
+	_irqlevel_changed_(&oldirql, LOWER);
+	{
+		u32 *plmem = (u32 *)poid_par_priv->information_buf + 2;
+		_attrib_write = pintfhdl->io_ops._attrib_write;
+		_attrib_write(pintfhdl, *(u32 *)poid_par_priv->information_buf,
+			*((u32 *)poid_par_priv->information_buf + 1), (u8 *)plmem);
+	}
+	_irqlevel_changed_(&oldirql, RAISE);
+#endif
+
+
+	return status;
+#else
+	return 0;
+#endif
+}
+/* ------------------------------------------------------------------------------ */
+NDIS_STATUS  oid_rt_pro_set_rf_intfs_hdl(struct oid_par_priv *poid_par_priv)
+{
+#if 0
+	PADAPTER	Adapter = (PADAPTER)(poid_par_priv->adapter_context);
+
+#ifdef PLATFORM_OS_XP
+	_irqL		oldirql;
+#endif
+	NDIS_STATUS	status = NDIS_STATUS_SUCCESS;
+
+
+
+	if (poid_par_priv->type_of_oid != SET_OID)
+		return NDIS_STATUS_NOT_ACCEPTED;
+
+	_irqlevel_changed_(&oldirql, LOWER);
+
+	if (rtw_setrfintfs_cmd(Adapter, *(unsigned char *)poid_par_priv->information_buf) == _FAIL)
+		status = NDIS_STATUS_NOT_ACCEPTED;
+
+	_irqlevel_changed_(&oldirql, RAISE);
+
+
+	return status;
+#else
+	return 0;
+#endif
+}
+/* ------------------------------------------------------------------------------ */
+NDIS_STATUS oid_rt_poll_rx_status_hdl(struct oid_par_priv *poid_par_priv)
+{
+#if 0
+	PADAPTER	Adapter = (PADAPTER)(poid_par_priv->adapter_context);
+
+	NDIS_STATUS	status = NDIS_STATUS_SUCCESS;
+
+
+	if (poid_par_priv->type_of_oid != QUERY_OID)
+		return NDIS_STATUS_NOT_ACCEPTED;
+
+	_rtw_memcpy(poid_par_priv->information_buf, (unsigned char *)&Adapter->mppriv.rxstat, sizeof(struct recv_stat));
+	*poid_par_priv->bytes_rw = poid_par_priv->information_buf_len;
+
+
+	return status;
+#else
+	return 0;
+#endif
+}
+/* ------------------------------------------------------------------------------ */
+NDIS_STATUS oid_rt_pro_cfg_debug_message_hdl(struct oid_par_priv *poid_par_priv)
+{
+#if 0
+	PADAPTER	Adapter = (PADAPTER)(poid_par_priv->adapter_context);
+
+	NDIS_STATUS	status = NDIS_STATUS_SUCCESS;
+
+	PCFG_DBG_MSG_STRUCT pdbg_msg;
+
+
+
+#if 0/*#ifdef CONFIG_DEBUG_RTL871X*/
+
+	pdbg_msg = (PCFG_DBG_MSG_STRUCT)(poid_par_priv->information_buf);
+
+	if (poid_par_priv->type_of_oid == SET_OID) {
+
+		GlobalDebugLevel = pdbg_msg->DebugLevel;
+		GlobalDebugComponents = (pdbg_msg->DebugComponent_H32 << 32) | pdbg_msg->DebugComponent_L32;
+	} else {
+		pdbg_msg->DebugLevel = GlobalDebugLevel;
+		pdbg_msg->DebugComponent_H32 = (u32)(GlobalDebugComponents >> 32);
+		pdbg_msg->DebugComponent_L32 = (u32)GlobalDebugComponents;
+		*poid_par_priv->bytes_rw = poid_par_priv->information_buf_len;
+
+	}
+
+#endif
+
+
+	return status;
+#else
+	return 0;
+#endif
+}
+/* ------------------------------------------------------------------------------ */
+NDIS_STATUS oid_rt_pro_set_data_rate_ex_hdl(struct oid_par_priv *poid_par_priv)
+{
+	PADAPTER	Adapter = (PADAPTER)(poid_par_priv->adapter_context);
+
+#ifdef PLATFORM_OS_XP
+	_irqL		oldirql;
+#endif
+	NDIS_STATUS	status = NDIS_STATUS_SUCCESS;
+
+
+
+	if (poid_par_priv->type_of_oid != SET_OID)
+		return NDIS_STATUS_NOT_ACCEPTED;
+
+	_irqlevel_changed_(&oldirql, LOWER);
+
+	if (rtw_setdatarate_cmd(Adapter, poid_par_priv->information_buf) != _SUCCESS)
+		status = NDIS_STATUS_NOT_ACCEPTED;
+
+	_irqlevel_changed_(&oldirql, RAISE);
+
+
+	return status;
+}
+/* ----------------------------------------------------------------------------- */
+NDIS_STATUS oid_rt_get_thermal_meter_hdl(struct oid_par_priv *poid_par_priv)
+{
+#ifdef PLATFORM_OS_XP
+	_irqL		oldirql;
+#endif
+	NDIS_STATUS	status = NDIS_STATUS_SUCCESS;
+	u8 thermal = 0;
+	PADAPTER	Adapter = (PADAPTER)(poid_par_priv->adapter_context);
+
+
+
+	if (poid_par_priv->type_of_oid != QUERY_OID)
+		return NDIS_STATUS_NOT_ACCEPTED;
+
+	if (poid_par_priv->information_buf_len < sizeof(u32))
+		return NDIS_STATUS_INVALID_LENGTH;
+
+	_irqlevel_changed_(&oldirql, LOWER);
+	GetThermalMeter(Adapter, &thermal);
+	_irqlevel_changed_(&oldirql, RAISE);
+
+	*(u32 *)poid_par_priv->information_buf = (u32)thermal;
+	*poid_par_priv->bytes_rw = sizeof(u32);
+
+
+	return status;
+}
+/* ----------------------------------------------------------------------------- */
+NDIS_STATUS oid_rt_pro_read_tssi_hdl(struct oid_par_priv *poid_par_priv)
+{
+#if 0
+	PADAPTER	Adapter = (PADAPTER)(poid_par_priv->adapter_context);
+
+#ifdef PLATFORM_OS_XP
+	_irqL		oldirql;
+#endif
+	NDIS_STATUS	status = NDIS_STATUS_SUCCESS;
+
+
+
+	if (poid_par_priv->type_of_oid != SET_OID)
+		return NDIS_STATUS_NOT_ACCEPTED;
+
+	if (Adapter->mppriv.act_in_progress == _TRUE)
+		return NDIS_STATUS_NOT_ACCEPTED;
+
+	if (poid_par_priv->information_buf_len < sizeof(u8))
+		return NDIS_STATUS_INVALID_LENGTH;
+
+	/* init workparam */
+	Adapter->mppriv.act_in_progress = _TRUE;
+	Adapter->mppriv.workparam.bcompleted = _FALSE;
+	Adapter->mppriv.workparam.act_type = MPT_READ_TSSI;
+	Adapter->mppriv.workparam.io_offset = 0;
+	Adapter->mppriv.workparam.io_value = 0xFFFFFFFF;
+
+	_irqlevel_changed_(&oldirql, LOWER);
+
+	if (!rtw_gettssi_cmd(Adapter, 0, (u8 *)&Adapter->mppriv.workparam.io_value))
+		status = NDIS_STATUS_NOT_ACCEPTED;
+
+	_irqlevel_changed_(&oldirql, RAISE);
+
+
+	return status;
+#else
+	return 0;
+#endif
+}
+/* ------------------------------------------------------------------------------ */
+NDIS_STATUS oid_rt_pro_set_power_tracking_hdl(struct oid_par_priv *poid_par_priv)
+{
+#ifdef PLATFORM_OS_XP
+	_irqL		oldirql;
+#endif
+	NDIS_STATUS	status = NDIS_STATUS_SUCCESS;
+	PADAPTER	Adapter = (PADAPTER)(poid_par_priv->adapter_context);
+
+
+
+	/*	if (poid_par_priv->type_of_oid != SET_OID)
+	 *		return NDIS_STATUS_NOT_ACCEPTED; */
+
+	if (poid_par_priv->information_buf_len < sizeof(u8))
+		return NDIS_STATUS_INVALID_LENGTH;
+
+	_irqlevel_changed_(&oldirql, LOWER);
+	if (poid_par_priv->type_of_oid == SET_OID) {
+		u8 enable;
+
+		enable = *(u8 *)poid_par_priv->information_buf;
+
+		SetPowerTracking(Adapter, enable);
+	} else
+		GetPowerTracking(Adapter, (u8 *)poid_par_priv->information_buf);
+	_irqlevel_changed_(&oldirql, RAISE);
+
+
+	return status;
+}
+/* ----------------------------------------------------------------------------- */
+NDIS_STATUS oid_rt_pro_set_basic_rate_hdl(struct oid_par_priv *poid_par_priv)
+{
+#if 0
+#ifdef PLATFORM_OS_XP
+	_irqL		oldirql;
+#endif
+	u32 ratevalue;
+	u8 datarates[NumRates];
+	int i;
+	NDIS_STATUS	status = NDIS_STATUS_SUCCESS;
+	PADAPTER	padapter = (PADAPTER)(poid_par_priv->adapter_context);
+
+
+
+	if (poid_par_priv->type_of_oid != SET_OID)
+		return NDIS_STATUS_NOT_ACCEPTED;
+#if 0
+	ratevalue = *((u32 *)poid_par_priv->information_buf);
+
+	for (i = 0; i < NumRates; i++) {
+		if (ratevalue == mpdatarate[i])
+			datarates[i] = mpdatarate[i];
+		else
+			datarates[i] = 0xff;
+	}
+
+	_irqlevel_changed_(&oldirql, LOWER);
+
+	if (rtw_setbasicrate_cmd(padapter, datarates) != _SUCCESS)
+		status = NDIS_STATUS_NOT_ACCEPTED;
+
+	_irqlevel_changed_(&oldirql, RAISE);
+#endif
+
+
+	return status;
+#else
+	return 0;
+#endif
+}
+/* ------------------------------------------------------------------------------ */
+NDIS_STATUS oid_rt_pro_qry_pwrstate_hdl(struct oid_par_priv *poid_par_priv)
+{
+#if 0
+	PADAPTER	Adapter = (PADAPTER)(poid_par_priv->adapter_context);
+
+	NDIS_STATUS	status = NDIS_STATUS_SUCCESS;
+
+
+	if (poid_par_priv->type_of_oid != QUERY_OID)
+		return NDIS_STATUS_NOT_ACCEPTED;
+
+	if (poid_par_priv->information_buf_len < 8)
+		return NDIS_STATUS_INVALID_LENGTH;
+
+	*poid_par_priv->bytes_rw = 8;
+	_rtw_memcpy(poid_par_priv->information_buf, &(adapter_to_pwrctl(Adapter)->pwr_mode), 8);
+	*poid_par_priv->bytes_rw = poid_par_priv->information_buf_len;
+
+
+
+	return status;
+#else
+	return 0;
+#endif
+}
+/* ------------------------------------------------------------------------------ */
+NDIS_STATUS oid_rt_pro_set_pwrstate_hdl(struct oid_par_priv *poid_par_priv)
+{
+#if 0
+	PADAPTER	Adapter = (PADAPTER)(poid_par_priv->adapter_context);
+
+	NDIS_STATUS	status = NDIS_STATUS_SUCCESS;
+
+	uint pwr_mode, smart_ps;
+
+
+
+	if (poid_par_priv->type_of_oid != SET_OID)
+		return NDIS_STATUS_NOT_ACCEPTED;
+
+	*poid_par_priv->bytes_rw = 0;
+	*poid_par_priv->bytes_needed = 8;
+
+	if (poid_par_priv->information_buf_len < 8)
+		return NDIS_STATUS_INVALID_LENGTH;
+
+	pwr_mode = *(uint *)(poid_par_priv->information_buf);
+	smart_ps = *(uint *)((int)poid_par_priv->information_buf + 4);
+
+	*poid_par_priv->bytes_rw = 8;
+
+
+	return status;
+#else
+	return 0;
+#endif
+}
+/* ------------------------------------------------------------------------------ */
+NDIS_STATUS oid_rt_pro_h2c_set_rate_table_hdl(struct oid_par_priv *poid_par_priv)
+{
+#if 0
+	PADAPTER	Adapter = (PADAPTER)(poid_par_priv->adapter_context);
+
+#ifdef PLATFORM_OS_XP
+	_irqL		oldirql;
+#endif
+	NDIS_STATUS	status = NDIS_STATUS_SUCCESS;
+
+	struct setratable_parm *prate_table;
+	u8		res;
+
+
+	if (poid_par_priv->type_of_oid != SET_OID)
+		return NDIS_STATUS_NOT_ACCEPTED;
+
+	*poid_par_priv->bytes_needed  = sizeof(struct setratable_parm);
+	if (poid_par_priv->information_buf_len < sizeof(struct setratable_parm))
+		return NDIS_STATUS_INVALID_LENGTH;
+
+	prate_table = (struct setratable_parm *)poid_par_priv->information_buf;
+
+	_irqlevel_changed_(&oldirql, LOWER);
+	res = rtw_setrttbl_cmd(Adapter, prate_table);
+	_irqlevel_changed_(&oldirql, RAISE);
+
+	if (res == _FAIL)
+		status = NDIS_STATUS_FAILURE;
+
+
+	return status;
+#else
+	return 0;
+#endif
+}
+/* ------------------------------------------------------------------------------ */
+NDIS_STATUS oid_rt_pro_h2c_get_rate_table_hdl(struct oid_par_priv *poid_par_priv)
+{
+#if 0
+	PADAPTER	Adapter = (PADAPTER)(poid_par_priv->adapter_context);
+
+	NDIS_STATUS	status = NDIS_STATUS_SUCCESS;
+
+
+	if (poid_par_priv->type_of_oid != QUERY_OID)
+		return NDIS_STATUS_NOT_ACCEPTED;
+
+#if 0
+	struct mp_wi_cntx *pmp_wi_cntx = &(Adapter->mppriv.wi_cntx);
+	u8 res = _SUCCESS;
+	DEBUG_INFO(("===> Set OID_RT_PRO_H2C_GET_RATE_TABLE.\n"));
+
+	if (pmp_wi_cntx->bmp_wi_progress == _TRUE) {
+		DEBUG_ERR(("\n mp workitem is progressing, not allow to set another workitem right now!!!\n"));
+		Status = NDIS_STATUS_NOT_ACCEPTED;
+		break;
+	} else {
+		pmp_wi_cntx->bmp_wi_progress = _TRUE;
+		pmp_wi_cntx->param.bcompleted = _FALSE;
+		pmp_wi_cntx->param.act_type = MPT_GET_RATE_TABLE;
+		pmp_wi_cntx->param.io_offset = 0x0;
+		pmp_wi_cntx->param.bytes_cnt = sizeof(struct getratable_rsp);
+		pmp_wi_cntx->param.io_value = 0xffffffff;
+
+		res = rtw_getrttbl_cmd(Adapter, (struct getratable_rsp *)pmp_wi_cntx->param.data);
+		*poid_par_priv->bytes_rw = poid_par_priv->information_buf_len;
+		if (res != _SUCCESS)
+			Status = NDIS_STATUS_NOT_ACCEPTED;
+	}
+	DEBUG_INFO(("\n <=== Set OID_RT_PRO_H2C_GET_RATE_TABLE.\n"));
+#endif
+
+
+	return status;
+#else
+	return 0;
+#endif
+}
+
+/* ****************  oid_rtl_seg_87_12_00   section start **************** */
+NDIS_STATUS oid_rt_pro_encryption_ctrl_hdl(struct oid_par_priv *poid_par_priv)
+{
+#if 0
+	PADAPTER	Adapter = (PADAPTER)(poid_par_priv->adapter_context);
+	struct security_priv *psecuritypriv = &Adapter->securitypriv;
+
+	NDIS_STATUS	status = NDIS_STATUS_SUCCESS;
+
+	ENCRY_CTRL_STATE encry_mode;
+
+
+	*poid_par_priv->bytes_needed = sizeof(u8);
+	if (poid_par_priv->information_buf_len < *poid_par_priv->bytes_needed)
+		return NDIS_STATUS_INVALID_LENGTH;
+
+	if (poid_par_priv->type_of_oid == SET_OID) {
+		encry_mode = *((u8 *)poid_par_priv->information_buf);
+		switch (encry_mode) {
+		case HW_CONTROL:
+#if 0
+			Adapter->registrypriv.software_decrypt = _FALSE;
+			Adapter->registrypriv.software_encrypt = _FALSE;
+#else
+			psecuritypriv->sw_decrypt = _FALSE;
+			psecuritypriv->sw_encrypt = _FALSE;
+#endif
+			break;
+		case SW_CONTROL:
+#if 0
+			Adapter->registrypriv.software_decrypt = _TRUE;
+			Adapter->registrypriv.software_encrypt = _TRUE;
+#else
+			psecuritypriv->sw_decrypt = _TRUE;
+			psecuritypriv->sw_encrypt = _TRUE;
+#endif
+			break;
+		case HW_ENCRY_SW_DECRY:
+#if 0
+			Adapter->registrypriv.software_decrypt = _TRUE;
+			Adapter->registrypriv.software_encrypt = _FALSE;
+#else
+			psecuritypriv->sw_decrypt = _TRUE;
+			psecuritypriv->sw_encrypt = _FALSE;
+#endif
+			break;
+		case SW_ENCRY_HW_DECRY:
+#if 0
+			Adapter->registrypriv.software_decrypt = _FALSE;
+			Adapter->registrypriv.software_encrypt = _TRUE;
+#else
+			psecuritypriv->sw_decrypt = _FALSE;
+			psecuritypriv->sw_encrypt = _TRUE;
+#endif
+			break;
+		}
+
+	} else {
+#if 0
+		if (Adapter->registrypriv.software_encrypt == _FALSE) {
+			if (Adapter->registrypriv.software_decrypt == _FALSE)
+				encry_mode = HW_CONTROL;
+			else
+				encry_mode = HW_ENCRY_SW_DECRY;
+		} else {
+			if (Adapter->registrypriv.software_decrypt == _FALSE)
+				encry_mode = SW_ENCRY_HW_DECRY;
+			else
+				encry_mode = SW_CONTROL;
+		}
+#else
+
+		if ((psecuritypriv->sw_encrypt == _FALSE) && (psecuritypriv->sw_decrypt == _FALSE))
+			encry_mode = HW_CONTROL;
+		else if ((psecuritypriv->sw_encrypt == _FALSE) && (psecuritypriv->sw_decrypt == _TRUE))
+			encry_mode = HW_ENCRY_SW_DECRY;
+		else if ((psecuritypriv->sw_encrypt == _TRUE) && (psecuritypriv->sw_decrypt == _FALSE))
+			encry_mode = SW_ENCRY_HW_DECRY;
+		else if ((psecuritypriv->sw_encrypt == _TRUE) && (psecuritypriv->sw_decrypt == _TRUE))
+			encry_mode = SW_CONTROL;
+
+#endif
+
+		*(u8 *)poid_par_priv->information_buf =  encry_mode;
+		*poid_par_priv->bytes_rw = poid_par_priv->information_buf_len;
+
+	}
+
+	return status;
+#else
+	return 0;
+#endif
+}
+/* ------------------------------------------------------------------------------ */
+NDIS_STATUS oid_rt_pro_add_sta_info_hdl(struct oid_par_priv *poid_par_priv)
+{
+#if 0
+	PADAPTER	Adapter = (PADAPTER)(poid_par_priv->adapter_context);
+
+#ifdef PLATFORM_OS_XP
+	_irqL		oldirql;
+#endif
+	NDIS_STATUS	status = NDIS_STATUS_SUCCESS;
+
+	struct sta_info *psta = NULL;
+	UCHAR		*macaddr;
+
+
+	if (poid_par_priv->type_of_oid != SET_OID)
+		return NDIS_STATUS_NOT_ACCEPTED;
+
+	*poid_par_priv->bytes_needed = ETH_ALEN;
+	if (poid_par_priv->information_buf_len < *poid_par_priv->bytes_needed)
+		return NDIS_STATUS_INVALID_LENGTH;
+
+	macaddr = (UCHAR *) poid_par_priv->information_buf ;
+
+
+	_irqlevel_changed_(&oldirql, LOWER);
+
+	psta = rtw_get_stainfo(&Adapter->stapriv, macaddr);
+
+	if (psta == NULL) { /* the sta have been in sta_info_queue => do nothing */
+		psta = rtw_alloc_stainfo(&Adapter->stapriv, macaddr);
+
+		if (psta == NULL) {
+			status = NDIS_STATUS_FAILURE;
+		}
+	}
+
+	_irqlevel_changed_(&oldirql, RAISE);
+
+	return status;
+#else
+	return 0;
+#endif
+}
+/* ------------------------------------------------------------------------------ */
+NDIS_STATUS oid_rt_pro_dele_sta_info_hdl(struct oid_par_priv *poid_par_priv)
+{
+#if 0
+	PADAPTER	Adapter = (PADAPTER)(poid_par_priv->adapter_context);
+
+#ifdef PLATFORM_OS_XP
+	_irqL		oldirql;
+#endif
+	NDIS_STATUS	status = NDIS_STATUS_SUCCESS;
+
+	struct sta_info *psta = NULL;
+	UCHAR		*macaddr;
+
+
+	if (poid_par_priv->type_of_oid != SET_OID)
+		return NDIS_STATUS_NOT_ACCEPTED;
+
+	*poid_par_priv->bytes_needed = ETH_ALEN;
+	if (poid_par_priv->information_buf_len < *poid_par_priv->bytes_needed)
+		return NDIS_STATUS_INVALID_LENGTH;
+
+	macaddr = (UCHAR *) poid_par_priv->information_buf ;
+
+	psta = rtw_get_stainfo(&Adapter->stapriv, macaddr);
+	if (psta != NULL) {
+		/* _enter_critical(&(Adapter->stapriv.sta_hash_lock), &irqL); */
+		rtw_free_stainfo(Adapter, psta);
+		/* _exit_critical(&(Adapter->stapriv.sta_hash_lock), &irqL); */
+	}
+
+	return status;
+#else
+	return 0;
+#endif
+}
+/* ------------------------------------------------------------------------------ */
+#if 0
+static u32 mp_query_drv_var(_adapter *padapter, u8 offset, u32 var)
+{
+#ifdef CONFIG_SDIO_HCI
+
+	if (offset == 1) {
+		u16 tmp_blk_num;
+		tmp_blk_num = rtw_read16(padapter, SDIO_RX0_RDYBLK_NUM);
+		if (adapter_to_dvobj(padapter)->rxblknum != tmp_blk_num) {
+			/*	sd_recv_rxfifo(padapter); */
+		}
+	}
+
+#if 0
+	if (offset <= 100) { /* For setting data rate and query data rate */
+		if (offset == 100) { /* For query data rate */
+			var = padapter->registrypriv.tx_rate;
+
+		} else if (offset < 0x1d) { /* For setting data rate */
+			padapter->registrypriv.tx_rate = offset;
+			var = padapter->registrypriv.tx_rate;
+			padapter->registrypriv.use_rate = _TRUE;
+		} else { /* not use the data rate */
+			padapter->registrypriv.use_rate = _FALSE;
+		}
+	} else if (offset <= 110) { /* for setting debug level */
+		if (offset == 110) { /* For query data rate */
+			padapter->registrypriv.dbg_level = GlobalDebugLevel;
+			var = padapter->registrypriv.dbg_level;
+		} else if (offset < 110 && offset > 100) {
+			padapter->registrypriv.dbg_level = GlobalDebugLevel = offset - 100;
+			var = padapter->registrypriv.dbg_level;
+
+		}
+	} else if (offset > 110 && offset < 116) {
+		if (115 == offset) {
+		} else {
+			switch (offset) {
+			case 111:
+				adapter_to_dvobj(padapter)->tx_block_mode = 1;
+				adapter_to_dvobj(padapter)->rx_block_mode = 1;
+				break;
+			case 112:
+				adapter_to_dvobj(padapter)->tx_block_mode = 1;
+				adapter_to_dvobj(padapter)->rx_block_mode = 0;
+				break;
+			case 113:
+				adapter_to_dvobj(padapter)->tx_block_mode = 0;
+				adapter_to_dvobj(padapter)->rx_block_mode = 1;
+				break;
+			case 114:
+				adapter_to_dvobj(padapter)->tx_block_mode = 0;
+				adapter_to_dvobj(padapter)->rx_block_mode = 0;
+				break;
+			default:
+				break;
+
+			}
+
+		}
+
+	} else if (offset >= 127) {
+		u64	prnt_dbg_comp;
+		u8   chg_idx;
+		u64	tmp_dbg_comp;
+		chg_idx = offset - 0x80;
+		tmp_dbg_comp = BIT(chg_idx);
+		prnt_dbg_comp = padapter->registrypriv.dbg_component = GlobalDebugComponents;
+		if (offset == 127) {
+			/*		prnt_dbg_comp=padapter->registrypriv.dbg_component= GlobalDebugComponents; */
+			var = (u32)(padapter->registrypriv.dbg_component);
+			prnt_dbg_comp = GlobalDebugComponents;
+			prnt_dbg_comp = GlobalDebugComponents = padapter->registrypriv.dbg_component;
+
+		} else {
+			prnt_dbg_comp = GlobalDebugComponents;
+			prnt_dbg_comp = GlobalDebugComponents = padapter->registrypriv.dbg_component;
+
+			if (GlobalDebugComponents & tmp_dbg_comp) {
+				/* this bit is already set, now clear it */
+				GlobalDebugComponents = GlobalDebugComponents & (~tmp_dbg_comp);
+			} else {
+				/* this bit is not set, now set it. */
+				GlobalDebugComponents = GlobalDebugComponents | tmp_dbg_comp;
+			}
+			prnt_dbg_comp = GlobalDebugComponents;
+
+			var = (u32)(GlobalDebugComponents);
+			/* GlobalDebugComponents=padapter->registrypriv.dbg_component; */
+
+		}
+	}
+#endif
+#endif
+
+	return var;
+}
+#endif
+
+NDIS_STATUS oid_rt_pro_query_dr_variable_hdl(struct oid_par_priv *poid_par_priv)
+{
+#if 0
+	PADAPTER		Adapter = (PADAPTER)(poid_par_priv->adapter_context);
+
+#ifdef PLATFORM_OS_XP
+	_irqL			oldirql;
+#endif
+	NDIS_STATUS		status = NDIS_STATUS_SUCCESS;
+
+	DR_VARIABLE_STRUCT	*pdrv_var;
+
+
+	if (poid_par_priv->type_of_oid != QUERY_OID)
+		return NDIS_STATUS_NOT_ACCEPTED;
+
+	*poid_par_priv->bytes_needed = sizeof(DR_VARIABLE_STRUCT);
+	if (poid_par_priv->information_buf_len < *poid_par_priv->bytes_needed)
+		return NDIS_STATUS_INVALID_LENGTH;
+
+
+	pdrv_var = (struct _DR_VARIABLE_STRUCT_ *)poid_par_priv->information_buf;
+
+	_irqlevel_changed_(&oldirql, LOWER);
+	pdrv_var->variable = mp_query_drv_var(Adapter, pdrv_var->offset, pdrv_var->variable);
+	_irqlevel_changed_(&oldirql, RAISE);
+
+	*poid_par_priv->bytes_rw = poid_par_priv->information_buf_len;
+
+
+	return status;
+#else
+	return 0;
+#endif
+}
+/* ------------------------------------------------------------------------------ */
+NDIS_STATUS oid_rt_pro_rx_packet_type_hdl(struct oid_par_priv *poid_par_priv)
+{
+#if 0
+	PADAPTER	Adapter = (PADAPTER)(poid_par_priv->adapter_context);
+
+	NDIS_STATUS	status = NDIS_STATUS_SUCCESS;
+
+
+	if (poid_par_priv->information_buf_len < sizeof(UCHAR)) {
+		status = NDIS_STATUS_INVALID_LENGTH;
+		*poid_par_priv->bytes_needed = sizeof(UCHAR);
+		return status;
+	}
+
+	if (poid_par_priv->type_of_oid == SET_OID) {
+		Adapter->mppriv.rx_with_status = *(UCHAR *) poid_par_priv->information_buf;
+
+
+	} else {
+		*(UCHAR *) poid_par_priv->information_buf = Adapter->mppriv.rx_with_status;
+		*poid_par_priv->bytes_rw = poid_par_priv->information_buf_len;
+
+
+		/* *(u32 *)&Adapter->eeprompriv.mac_addr[0]=rtw_read32(Adapter, 0x10250050); */
+		/* *(u16 *)&Adapter->eeprompriv.mac_addr[4]=rtw_read16(Adapter, 0x10250054); */
+	}
+#endif
+
+	return NDIS_STATUS_SUCCESS;
+}
+/* ------------------------------------------------------------------------------ */
+NDIS_STATUS oid_rt_pro_read_efuse_hdl(struct oid_par_priv *poid_par_priv)
+{
+#ifdef PLATFORM_OS_XP
+	_irqL oldirql;
+#endif
+	PEFUSE_ACCESS_STRUCT pefuse;
+	u8 *data;
+	u16 addr = 0, cnts = 0, max_available_size = 0;
+	NDIS_STATUS status = NDIS_STATUS_SUCCESS;
+	PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context);
+
+
+	if (poid_par_priv->type_of_oid != QUERY_OID)
+		return NDIS_STATUS_NOT_ACCEPTED;
+
+	if (poid_par_priv->information_buf_len < sizeof(EFUSE_ACCESS_STRUCT))
+		return NDIS_STATUS_INVALID_LENGTH;
+
+	pefuse = (PEFUSE_ACCESS_STRUCT)poid_par_priv->information_buf;
+	addr = pefuse->start_addr;
+	cnts = pefuse->cnts;
+	data = pefuse->data;
+
+
+	EFUSE_GetEfuseDefinition(Adapter, EFUSE_WIFI, TYPE_AVAILABLE_EFUSE_BYTES_TOTAL, (PVOID)&max_available_size, _FALSE);
+
+	if ((addr + cnts) > max_available_size) {
+		return NDIS_STATUS_NOT_ACCEPTED;
+	}
+
+	_irqlevel_changed_(&oldirql, LOWER);
+	if (rtw_efuse_access(Adapter, _FALSE, addr, cnts, data) == _FAIL) {
+		status = NDIS_STATUS_FAILURE;
+	} else
+		*poid_par_priv->bytes_rw = poid_par_priv->information_buf_len;
+	_irqlevel_changed_(&oldirql, RAISE);
+
+
+	return status;
+}
+/* ------------------------------------------------------------------------------ */
+NDIS_STATUS oid_rt_pro_write_efuse_hdl(struct oid_par_priv *poid_par_priv)
+{
+#ifdef PLATFORM_OS_XP
+	_irqL oldirql;
+#endif
+	PEFUSE_ACCESS_STRUCT pefuse;
+	u8 *data;
+	u16 addr = 0, cnts = 0, max_available_size = 0;
+	NDIS_STATUS status = NDIS_STATUS_SUCCESS;
+	PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context);
+
+
+
+	if (poid_par_priv->type_of_oid != SET_OID)
+		return NDIS_STATUS_NOT_ACCEPTED;
+
+	pefuse = (PEFUSE_ACCESS_STRUCT)poid_par_priv->information_buf;
+	addr = pefuse->start_addr;
+	cnts = pefuse->cnts;
+	data = pefuse->data;
+
+
+	EFUSE_GetEfuseDefinition(Adapter, EFUSE_WIFI, TYPE_AVAILABLE_EFUSE_BYTES_TOTAL, (PVOID)&max_available_size, _FALSE);
+
+	if ((addr + cnts) > max_available_size) {
+		return NDIS_STATUS_NOT_ACCEPTED;
+	}
+
+	_irqlevel_changed_(&oldirql, LOWER);
+	if (rtw_efuse_access(Adapter, _TRUE, addr, cnts, data) == _FAIL)
+		status = NDIS_STATUS_FAILURE;
+	_irqlevel_changed_(&oldirql, RAISE);
+
+
+	return status;
+}
+/* ------------------------------------------------------------------------------ */
+NDIS_STATUS oid_rt_pro_rw_efuse_pgpkt_hdl(struct oid_par_priv *poid_par_priv)
+{
+#ifdef PLATFORM_OS_XP
+	_irqL		oldirql;
+#endif
+	PPGPKT_STRUCT	ppgpkt;
+	NDIS_STATUS	status = NDIS_STATUS_SUCCESS;
+	PADAPTER	Adapter = (PADAPTER)(poid_par_priv->adapter_context);
+
+
+
+	*poid_par_priv->bytes_rw = 0;
+
+	if (poid_par_priv->information_buf_len < sizeof(PGPKT_STRUCT))
+		return NDIS_STATUS_INVALID_LENGTH;
+
+	ppgpkt = (PPGPKT_STRUCT)poid_par_priv->information_buf;
+
+	_irqlevel_changed_(&oldirql, LOWER);
+
+	if (poid_par_priv->type_of_oid == QUERY_OID) {
+
+		Efuse_PowerSwitch(Adapter, _FALSE, _TRUE);
+		if (Efuse_PgPacketRead(Adapter, ppgpkt->offset, ppgpkt->data, _FALSE) == _TRUE)
+			*poid_par_priv->bytes_rw = poid_par_priv->information_buf_len;
+		else
+			status = NDIS_STATUS_FAILURE;
+		Efuse_PowerSwitch(Adapter, _FALSE, _FALSE);
+	} else {
+
+		Efuse_PowerSwitch(Adapter, _TRUE, _TRUE);
+		if (Efuse_PgPacketWrite(Adapter, ppgpkt->offset, ppgpkt->word_en, ppgpkt->data, _FALSE) == _TRUE)
+			*poid_par_priv->bytes_rw = poid_par_priv->information_buf_len;
+		else
+			status = NDIS_STATUS_FAILURE;
+		Efuse_PowerSwitch(Adapter, _TRUE, _FALSE);
+	}
+
+	_irqlevel_changed_(&oldirql, RAISE);
+
+
+
+	return status;
+}
+/* ------------------------------------------------------------------------------ */
+NDIS_STATUS oid_rt_get_efuse_current_size_hdl(struct oid_par_priv *poid_par_priv)
+{
+#ifdef PLATFORM_OS_XP
+	_irqL		oldirql;
+#endif
+	u16 size;
+	u8 ret;
+	NDIS_STATUS	status = NDIS_STATUS_SUCCESS;
+	PADAPTER	Adapter = (PADAPTER)(poid_par_priv->adapter_context);
+
+
+	if (poid_par_priv->type_of_oid != QUERY_OID)
+		return NDIS_STATUS_NOT_ACCEPTED;
+
+	if (poid_par_priv->information_buf_len < sizeof(u32))
+		return NDIS_STATUS_INVALID_LENGTH;
+
+	_irqlevel_changed_(&oldirql, LOWER);
+	ret = efuse_GetCurrentSize(Adapter, &size);
+	_irqlevel_changed_(&oldirql, RAISE);
+	if (ret == _SUCCESS) {
+		*(u32 *)poid_par_priv->information_buf = size;
+		*poid_par_priv->bytes_rw = poid_par_priv->information_buf_len;
+	} else
+		status = NDIS_STATUS_FAILURE;
+
+
+	return status;
+}
+/* ------------------------------------------------------------------------------ */
+NDIS_STATUS oid_rt_get_efuse_max_size_hdl(struct oid_par_priv *poid_par_priv)
+{
+	NDIS_STATUS	status = NDIS_STATUS_SUCCESS;
+	PADAPTER	Adapter = (PADAPTER)(poid_par_priv->adapter_context);
+
+
+	if (poid_par_priv->type_of_oid != QUERY_OID)
+		return NDIS_STATUS_NOT_ACCEPTED;
+
+	if (poid_par_priv->information_buf_len < sizeof(u32))
+		return NDIS_STATUS_INVALID_LENGTH;
+
+	*(u32 *)poid_par_priv->information_buf = efuse_GetMaxSize(Adapter);
+	*poid_par_priv->bytes_rw = poid_par_priv->information_buf_len;
+
+
+
+	return status;
+}
+/* ------------------------------------------------------------------------------ */
+NDIS_STATUS oid_rt_pro_efuse_hdl(struct oid_par_priv *poid_par_priv)
+{
+	NDIS_STATUS	status;
+
+
+
+	if (poid_par_priv->type_of_oid == QUERY_OID)
+		status = oid_rt_pro_read_efuse_hdl(poid_par_priv);
+	else
+		status = oid_rt_pro_write_efuse_hdl(poid_par_priv);
+
+
+
+	return status;
+}
+/* ------------------------------------------------------------------------------ */
+NDIS_STATUS oid_rt_pro_efuse_map_hdl(struct oid_par_priv *poid_par_priv)
+{
+#ifdef PLATFORM_OS_XP
+	_irqL		oldirql;
+#endif
+	u8		*data;
+	NDIS_STATUS	status = NDIS_STATUS_SUCCESS;
+	PADAPTER	Adapter = (PADAPTER)(poid_par_priv->adapter_context);
+	u16	mapLen = 0;
+
+
+
+	EFUSE_GetEfuseDefinition(Adapter, EFUSE_WIFI, TYPE_EFUSE_MAP_LEN, (PVOID)&mapLen, _FALSE);
+
+	*poid_par_priv->bytes_rw = 0;
+
+	if (poid_par_priv->information_buf_len < mapLen)
+		return NDIS_STATUS_INVALID_LENGTH;
+
+	data = (u8 *)poid_par_priv->information_buf;
+
+	_irqlevel_changed_(&oldirql, LOWER);
+
+	if (poid_par_priv->type_of_oid == QUERY_OID) {
+
+		if (rtw_efuse_map_read(Adapter, 0, mapLen, data) == _SUCCESS)
+			*poid_par_priv->bytes_rw = mapLen;
+		else {
+			status = NDIS_STATUS_FAILURE;
+		}
+	} else {
+		/* SET_OID */
+
+		if (rtw_efuse_map_write(Adapter, 0, mapLen, data) == _SUCCESS)
+			*poid_par_priv->bytes_rw = mapLen;
+		else {
+			status = NDIS_STATUS_FAILURE;
+		}
+	}
+
+	_irqlevel_changed_(&oldirql, RAISE);
+
+
+
+	return status;
+}
+
+NDIS_STATUS oid_rt_set_crystal_cap_hdl(struct oid_par_priv *poid_par_priv)
+{
+	NDIS_STATUS	status = NDIS_STATUS_SUCCESS;
+#if 0
+	PADAPTER	Adapter = (PADAPTER)(poid_par_priv->adapter_context);
+
+#ifdef PLATFORM_OS_XP
+	_irqL		oldirql;
+#endif
+
+	u32		crystal_cap = 0;
+
+
+	if (poid_par_priv->type_of_oid != SET_OID)
+		return NDIS_STATUS_NOT_ACCEPTED;
+
+	if (poid_par_priv->information_buf_len < sizeof(u32))
+		return NDIS_STATUS_INVALID_LENGTH;
+
+	crystal_cap = *((u32 *)poid_par_priv->information_buf); /* 4 */
+	if (crystal_cap > 0xf)
+		return NDIS_STATUS_NOT_ACCEPTED;
+
+	Adapter->mppriv.curr_crystalcap = crystal_cap;
+
+	_irqlevel_changed_(&oldirql, LOWER);
+	SetCrystalCap(Adapter);
+	_irqlevel_changed_(&oldirql, RAISE);
+
+
+#endif
+	return status;
+}
+
+NDIS_STATUS oid_rt_set_rx_packet_type_hdl(struct oid_par_priv *poid_par_priv)
+{
+#ifdef PLATFORM_OS_XP
+	_irqL		oldirql;
+#endif
+	u8		rx_pkt_type;
+	/*	u32		rcr_val32; */
+	NDIS_STATUS	status = NDIS_STATUS_SUCCESS;
+	/*	PADAPTER	padapter = (PADAPTER)(poid_par_priv->adapter_context); */
+
+
+
+	if (poid_par_priv->type_of_oid != SET_OID)
+		return NDIS_STATUS_NOT_ACCEPTED;
+
+	if (poid_par_priv->information_buf_len < sizeof(u8))
+		return NDIS_STATUS_INVALID_LENGTH;
+
+	rx_pkt_type = *((u8 *)poid_par_priv->information_buf); /* 4 */
+
+#if 0
+	_irqlevel_changed_(&oldirql, LOWER);
+#if 0
+	rcr_val8 = rtw_read8(Adapter, 0x10250048);/* RCR */
+	rcr_val8 &= ~(RCR_AB | RCR_AM | RCR_APM | RCR_AAP);
+
+	if (rx_pkt_type == RX_PKT_BROADCAST)
+		rcr_val8 |= (RCR_AB | RCR_ACRC32);
+	else if (rx_pkt_type == RX_PKT_DEST_ADDR)
+		rcr_val8 |= (RCR_AAP | RCR_AM | RCR_ACRC32);
+	else if (rx_pkt_type == RX_PKT_PHY_MATCH)
+		rcr_val8 |= (RCR_APM | RCR_ACRC32);
+	else
+		rcr_val8 &= ~(RCR_AAP | RCR_APM | RCR_AM | RCR_AB | RCR_ACRC32);
+	rtw_write8(padapter, 0x10250048, rcr_val8);
+#else
+	rcr_val32 = rtw_read32(padapter, RCR);/* RCR = 0x10250048 */
+	rcr_val32 &= ~(RCR_CBSSID | RCR_AB | RCR_AM | RCR_APM | RCR_AAP);
+#if 0
+	if (rx_pkt_type == RX_PKT_BROADCAST)
+		rcr_val32 |= (RCR_AB | RCR_AM | RCR_APM | RCR_AAP | RCR_ACRC32);
+	else if (rx_pkt_type == RX_PKT_DEST_ADDR) {
+		/* rcr_val32 |= (RCR_CBSSID|RCR_AAP|RCR_AM|RCR_ACRC32); */
+		rcr_val32 |= (RCR_CBSSID | RCR_APM | RCR_ACRC32);
+	} else if (rx_pkt_type == RX_PKT_PHY_MATCH) {
+		rcr_val32 |= (RCR_APM | RCR_ACRC32);
+		/* rcr_val32 |= (RCR_AAP|RCR_ACRC32); */
+	} else
+		rcr_val32 &= ~(RCR_AAP | RCR_APM | RCR_AM | RCR_AB | RCR_ACRC32);
+#else
+	switch (rx_pkt_type) {
+	case RX_PKT_BROADCAST:
+		rcr_val32 |= (RCR_AB | RCR_AM | RCR_APM | RCR_AAP | RCR_ACRC32);
+		break;
+	case RX_PKT_DEST_ADDR:
+		rcr_val32 |= (RCR_AB | RCR_AM | RCR_APM | RCR_AAP | RCR_ACRC32);
+		break;
+	case RX_PKT_PHY_MATCH:
+		rcr_val32 |= (RCR_APM | RCR_ACRC32);
+		break;
+	default:
+		rcr_val32 &= ~(RCR_AAP | RCR_APM | RCR_AM | RCR_AB | RCR_ACRC32);
+		break;
+	}
+
+	if (rx_pkt_type == RX_PKT_DEST_ADDR)
+		padapter->mppriv.check_mp_pkt = 1;
+	else
+		padapter->mppriv.check_mp_pkt = 0;
+#endif
+	rtw_write32(padapter, RCR, rcr_val32);
+
+#endif
+	_irqlevel_changed_(&oldirql, RAISE);
+#endif
+
+	return status;
+}
+
+NDIS_STATUS oid_rt_pro_set_tx_agc_offset_hdl(struct oid_par_priv *poid_par_priv)
+{
+#if 0
+	PADAPTER	Adapter = (PADAPTER)(poid_par_priv->adapter_context);
+
+#ifdef PLATFORM_OS_XP
+	_irqL		oldirql;
+#endif
+	NDIS_STATUS	status = NDIS_STATUS_SUCCESS;
+
+	u32		txagc;
+
+
+	if (poid_par_priv->type_of_oid != SET_OID)
+		return NDIS_STATUS_NOT_ACCEPTED;
+
+	if (poid_par_priv->information_buf_len < sizeof(u32))
+		return NDIS_STATUS_INVALID_LENGTH;
+
+	txagc = *(u32 *)poid_par_priv->information_buf;
+
+	_irqlevel_changed_(&oldirql, LOWER);
+	SetTxAGCOffset(Adapter, txagc);
+	_irqlevel_changed_(&oldirql, RAISE);
+
+
+	return status;
+#else
+	return 0;
+#endif
+}
+
+NDIS_STATUS oid_rt_pro_set_pkt_test_mode_hdl(struct oid_par_priv *poid_par_priv)
+{
+#if 0
+	PADAPTER		Adapter = (PADAPTER)(poid_par_priv->adapter_context);
+
+	NDIS_STATUS		status = NDIS_STATUS_SUCCESS;
+
+	struct mlme_priv	*pmlmepriv = &Adapter->mlmepriv;
+	struct mp_priv		*pmppriv = &Adapter->mppriv;
+	u32			type;
+
+
+	if (poid_par_priv->type_of_oid != SET_OID)
+		return NDIS_STATUS_NOT_ACCEPTED;
+
+	if (poid_par_priv->information_buf_len < sizeof(u32))
+		return NDIS_STATUS_INVALID_LENGTH;
+
+	type = *(u32 *)poid_par_priv->information_buf;
+
+	if (_LOOPBOOK_MODE_ == type) {
+		pmppriv->mode = type;
+		set_fwstate(pmlmepriv, WIFI_MP_LPBK_STATE); /* append txdesc */
+	} else if (_2MAC_MODE_ == type) {
+		pmppriv->mode = type;
+		_clr_fwstate_(pmlmepriv, WIFI_MP_LPBK_STATE);
+	} else
+		status = NDIS_STATUS_NOT_ACCEPTED;
+
+
+	return status;
+#else
+	return 0;
+#endif
+}
+
+unsigned int mp_ioctl_xmit_packet_hdl(struct oid_par_priv *poid_par_priv)
+{
+	PMP_XMIT_PARM pparm;
+	PADAPTER padapter;
+	struct mp_priv *pmp_priv;
+	struct pkt_attrib *pattrib;
+
+
+	pparm = (PMP_XMIT_PARM)poid_par_priv->information_buf;
+	padapter = (PADAPTER)poid_par_priv->adapter_context;
+	pmp_priv = &padapter->mppriv;
+
+	if (poid_par_priv->type_of_oid == QUERY_OID) {
+		pparm->enable = !pmp_priv->tx.stop;
+		pparm->count = pmp_priv->tx.sended;
+	} else {
+		if (pparm->enable == 0)
+			pmp_priv->tx.stop = 1;
+		else if (pmp_priv->tx.stop == 1) {
+			pmp_priv->tx.stop = 0;
+			pmp_priv->tx.count = pparm->count;
+			pmp_priv->tx.payload = pparm->payload_type;
+			pattrib = &pmp_priv->tx.attrib;
+			pattrib->pktlen = pparm->length;
+			_rtw_memcpy(pattrib->dst, pparm->da, ETH_ALEN);
+			SetPacketTx(padapter);
+		} else
+			return NDIS_STATUS_FAILURE;
+	}
+
+	return NDIS_STATUS_SUCCESS;
+}
+
+#if 0
+unsigned int mp_ioctl_xmit_packet_hdl(struct oid_par_priv *poid_par_priv)
+{
+	unsigned char *pframe, *pmp_pkt;
+	struct ethhdr *pethhdr;
+	struct pkt_attrib *pattrib;
+	struct rtw_ieee80211_hdr *pwlanhdr;
+	unsigned short *fctrl;
+	int llc_sz, payload_len;
+	struct mp_xmit_frame *pxframe =  NULL;
+	struct mp_xmit_packet *pmp_xmitpkt = (struct mp_xmit_packet *)param;
+	u8 addr3[] = {0x02, 0xE0, 0x4C, 0x87, 0x66, 0x55};
+
+	/*	RTW_INFO("+mp_ioctl_xmit_packet_hdl\n"); */
+
+	pxframe = alloc_mp_xmitframe(&padapter->mppriv);
+	if (pxframe == NULL) {
+		DEBUG_ERR(("Can't alloc pmpframe %d:%s\n", __LINE__, __FILE__));
+		return -1;
+	}
+
+	/* mp_xmit_pkt */
+	payload_len = pmp_xmitpkt->len - 14;
+	pmp_pkt = (unsigned char *)pmp_xmitpkt->mem;
+	pethhdr = (struct ethhdr *)pmp_pkt;
+
+	/* RTW_INFO("payload_len=%d, pkt_mem=0x%x\n", pmp_xmitpkt->len, (void*)pmp_xmitpkt->mem); */
+
+	/* RTW_INFO("pxframe=0x%x\n", (void*)pxframe); */
+	/* RTW_INFO("pxframe->mem=0x%x\n", (void*)pxframe->mem); */
+
+	/* update attribute */
+	pattrib = &pxframe->attrib;
+	memset((u8 *)(pattrib), 0, sizeof(struct pkt_attrib));
+	pattrib->pktlen = pmp_xmitpkt->len;
+	pattrib->ether_type = ntohs(pethhdr->h_proto);
+	pattrib->hdrlen = 24;
+	pattrib->nr_frags = 1;
+	pattrib->priority = 0;
+#ifndef CONFIG_MP_LINUX
+	if (IS_MCAST(pethhdr->h_dest))
+		pattrib->mac_id = 4;
+	else
+		pattrib->mac_id = 5;
+#else
+	pattrib->mac_id = 5;
+#endif
+
+	/*  */
+	memset(pxframe->mem, 0 , WLANHDR_OFFSET);
+	pframe = (u8 *)(pxframe->mem) + WLANHDR_OFFSET;
+
+	pwlanhdr = (struct rtw_ieee80211_hdr *)pframe;
+
+	fctrl = &(pwlanhdr->frame_ctl);
+	*(fctrl) = 0;
+	set_frame_sub_type(pframe, WIFI_DATA);
+
+	_rtw_memcpy(pwlanhdr->addr1, pethhdr->h_dest, ETH_ALEN);
+	_rtw_memcpy(pwlanhdr->addr2, pethhdr->h_source, ETH_ALEN);
+
+	_rtw_memcpy(pwlanhdr->addr3, addr3, ETH_ALEN);
+
+	pwlanhdr->seq_ctl = 0;
+	pframe += pattrib->hdrlen;
+
+	llc_sz = rtw_put_snap(pframe, pattrib->ether_type);
+	pframe += llc_sz;
+
+	_rtw_memcpy(pframe, (void *)(pmp_pkt + 14),  payload_len);
+
+	pattrib->last_txcmdsz = pattrib->hdrlen + llc_sz + payload_len;
+
+	DEBUG_INFO(("issuing mp_xmit_frame, tx_len=%d, ether_type=0x%x\n", pattrib->last_txcmdsz, pattrib->ether_type));
+	xmit_mp_frame(padapter, pxframe);
+
+	return _SUCCESS;
+}
+#endif
+/* ------------------------------------------------------------------------------ */
+NDIS_STATUS oid_rt_set_power_down_hdl(struct oid_par_priv *poid_par_priv)
+{
+#ifdef PLATFORM_OS_XP
+	_irqL		oldirql;
+#endif
+	u8		bpwrup;
+	NDIS_STATUS	status = NDIS_STATUS_SUCCESS;
+#ifdef PLATFORM_LINUX
+#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
+	PADAPTER	padapter = (PADAPTER)(poid_par_priv->adapter_context);
+#endif
+#endif
+
+
+	if (poid_par_priv->type_of_oid != SET_OID) {
+		status = NDIS_STATUS_NOT_ACCEPTED;
+		return status;
+	}
+
+
+	_irqlevel_changed_(&oldirql, LOWER);
+
+	bpwrup = *(u8 *)poid_par_priv->information_buf;
+	/* CALL  the power_down function */
+#ifdef PLATFORM_LINUX
+#if defined(CONFIG_RTL8712) /* Linux MP insmod unknown symbol */
+	dev_power_down(padapter, bpwrup);
+#endif
+#endif
+	_irqlevel_changed_(&oldirql, RAISE);
+
+	/* DEBUG_ERR(("\n <=== Query OID_RT_PRO_READ_REGISTER. */
+	/*	Add:0x%08x Width:%d Value:0x%08x\n",RegRWStruct->offset,RegRWStruct->width,RegRWStruct->value)); */
+
+
+	return status;
+}
+/* ------------------------------------------------------------------------------ */
+NDIS_STATUS oid_rt_get_power_mode_hdl(struct oid_par_priv *poid_par_priv)
+{
+#if 0
+	NDIS_STATUS	status = NDIS_STATUS_SUCCESS;
+	PADAPTER	Adapter = (PADAPTER)(poid_par_priv->adapter_context);
+	/* #ifdef PLATFORM_OS_XP */
+	/*	_irqL		oldirql;
+	 * #endif */
+
+
+	if (poid_par_priv->type_of_oid != QUERY_OID) {
+		status = NDIS_STATUS_NOT_ACCEPTED;
+		return status;
+	}
+	if (poid_par_priv->information_buf_len < sizeof(u32)) {
+		status = NDIS_STATUS_INVALID_LENGTH;
+		return status;
+	}
+
+
+	/*	_irqlevel_changed_(&oldirql, LOWER); */
+	*(int *)poid_par_priv->information_buf = Adapter->registrypriv.low_power ? POWER_LOW : POWER_NORMAL;
+	*poid_par_priv->bytes_rw = poid_par_priv->information_buf_len;
+	/*	_irqlevel_changed_(&oldirql, RAISE); */
+
+
+	return status;
+#else
+	return 0;
+#endif
+}
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/core/rtw_odm.c linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/core/rtw_odm.c
--- linux-5.6.3/3rdparty/rtl8821ce/core/rtw_odm.c	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/core/rtw_odm.c	2020-04-10 16:35:06.776658200 +0300
@@ -0,0 +1,420 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2013 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+
+#include <rtw_odm.h>
+#include <hal_data.h>
+
+u32 rtw_phydm_ability_ops(_adapter *adapter, HAL_PHYDM_OPS ops, u32 ability)
+{
+	HAL_DATA_TYPE *pHalData = GET_HAL_DATA(adapter);
+	struct dm_struct *podmpriv = &pHalData->odmpriv;
+	u32 result = 0;
+
+	switch (ops) {
+	case HAL_PHYDM_DIS_ALL_FUNC:
+		podmpriv->support_ability = DYNAMIC_FUNC_DISABLE;
+		halrf_cmn_info_set(podmpriv, HALRF_CMNINFO_ABILITY, DYNAMIC_FUNC_DISABLE);
+		break;
+	case HAL_PHYDM_FUNC_SET:
+		podmpriv->support_ability |= ability;
+		break;
+	case HAL_PHYDM_FUNC_CLR:
+		podmpriv->support_ability &= ~(ability);
+		break;
+	case HAL_PHYDM_ABILITY_BK:
+		/* dm flag backup*/
+		podmpriv->bk_support_ability = podmpriv->support_ability;
+		pHalData->bk_rf_ability = halrf_cmn_info_get(podmpriv, HALRF_CMNINFO_ABILITY);
+		break;
+	case HAL_PHYDM_ABILITY_RESTORE:
+		/* restore dm flag */
+		podmpriv->support_ability = podmpriv->bk_support_ability;
+		halrf_cmn_info_set(podmpriv, HALRF_CMNINFO_ABILITY, pHalData->bk_rf_ability);
+		break;
+	case HAL_PHYDM_ABILITY_SET:
+		podmpriv->support_ability = ability;
+		break;
+	case HAL_PHYDM_ABILITY_GET:
+		result = podmpriv->support_ability;
+		break;
+	}
+	return result;
+}
+
+/* set ODM_CMNINFO_IC_TYPE based on chip_type */
+void rtw_odm_init_ic_type(_adapter *adapter)
+{
+	struct dm_struct *odm = adapter_to_phydm(adapter);
+	u4Byte ic_type = chip_type_to_odm_ic_type(rtw_get_chip_type(adapter));
+
+	rtw_warn_on(!ic_type);
+
+	odm_cmn_info_init(odm, ODM_CMNINFO_IC_TYPE, ic_type);
+}
+
+void rtw_odm_adaptivity_ver_msg(void *sel, _adapter *adapter)
+{
+	RTW_PRINT_SEL(sel, "ADAPTIVITY_VERSION "ADAPTIVITY_VERSION"\n");
+}
+
+#define RTW_ADAPTIVITY_EN_DISABLE 0
+#define RTW_ADAPTIVITY_EN_ENABLE 1
+
+void rtw_odm_adaptivity_en_msg(void *sel, _adapter *adapter)
+{
+	struct registry_priv *regsty = &adapter->registrypriv;
+
+	RTW_PRINT_SEL(sel, "RTW_ADAPTIVITY_EN_");
+
+	if (regsty->adaptivity_en == RTW_ADAPTIVITY_EN_DISABLE)
+		_RTW_PRINT_SEL(sel, "DISABLE\n");
+	else if (regsty->adaptivity_en == RTW_ADAPTIVITY_EN_ENABLE)
+		_RTW_PRINT_SEL(sel, "ENABLE\n");
+	else
+		_RTW_PRINT_SEL(sel, "INVALID\n");
+}
+
+#define RTW_ADAPTIVITY_MODE_NORMAL 0
+#define RTW_ADAPTIVITY_MODE_CARRIER_SENSE 1
+
+void rtw_odm_adaptivity_mode_msg(void *sel, _adapter *adapter)
+{
+	struct registry_priv *regsty = &adapter->registrypriv;
+
+	RTW_PRINT_SEL(sel, "RTW_ADAPTIVITY_MODE_");
+
+	if (regsty->adaptivity_mode == RTW_ADAPTIVITY_MODE_NORMAL)
+		_RTW_PRINT_SEL(sel, "NORMAL\n");
+	else if (regsty->adaptivity_mode == RTW_ADAPTIVITY_MODE_CARRIER_SENSE)
+		_RTW_PRINT_SEL(sel, "CARRIER_SENSE\n");
+	else
+		_RTW_PRINT_SEL(sel, "INVALID\n");
+}
+
+void rtw_odm_adaptivity_config_msg(void *sel, _adapter *adapter)
+{
+	rtw_odm_adaptivity_ver_msg(sel, adapter);
+	rtw_odm_adaptivity_en_msg(sel, adapter);
+	rtw_odm_adaptivity_mode_msg(sel, adapter);
+}
+
+bool rtw_odm_adaptivity_needed(_adapter *adapter)
+{
+	struct registry_priv *regsty = &adapter->registrypriv;
+	bool ret = _FALSE;
+
+	if (regsty->adaptivity_en == RTW_ADAPTIVITY_EN_ENABLE)
+		ret = _TRUE;
+
+	return ret;
+}
+
+void rtw_odm_adaptivity_parm_msg(void *sel, _adapter *adapter)
+{
+	struct dm_struct *odm = adapter_to_phydm(adapter);
+
+	rtw_odm_adaptivity_config_msg(sel, adapter);
+
+	RTW_PRINT_SEL(sel, "%10s %16s\n"
+		, "th_l2h_ini", "th_edcca_hl_diff");
+	RTW_PRINT_SEL(sel, "0x%-8x %-16d\n"
+		, (u8)odm->th_l2h_ini
+		, odm->th_edcca_hl_diff
+	);
+}
+
+void rtw_odm_adaptivity_parm_set(_adapter *adapter, s8 th_l2h_ini, s8 th_edcca_hl_diff)
+{
+	struct dm_struct *odm = adapter_to_phydm(adapter);
+
+	odm->th_l2h_ini = th_l2h_ini;
+	odm->th_edcca_hl_diff = th_edcca_hl_diff;
+}
+
+void rtw_odm_get_perpkt_rssi(void *sel, _adapter *adapter)
+{
+	struct dm_struct *odm = adapter_to_phydm(adapter);
+
+	RTW_PRINT_SEL(sel, "rx_rate = %s, rssi_a = %d(%%), rssi_b = %d(%%)\n",
+		      HDATA_RATE(odm->rx_rate), odm->rssi_a, odm->rssi_b);
+}
+
+
+void rtw_odm_acquirespinlock(_adapter *adapter,	enum rt_spinlock_type type)
+{
+	PHAL_DATA_TYPE	pHalData = GET_HAL_DATA(adapter);
+	_irqL irqL;
+
+	switch (type) {
+	case RT_IQK_SPINLOCK:
+		_enter_critical_bh(&pHalData->IQKSpinLock, &irqL);
+	default:
+		break;
+	}
+}
+
+void rtw_odm_releasespinlock(_adapter *adapter,	enum rt_spinlock_type type)
+{
+	PHAL_DATA_TYPE	pHalData = GET_HAL_DATA(adapter);
+	_irqL irqL;
+
+	switch (type) {
+	case RT_IQK_SPINLOCK:
+		_exit_critical_bh(&pHalData->IQKSpinLock, &irqL);
+	default:
+		break;
+	}
+}
+
+inline u8 rtw_odm_get_dfs_domain(struct dvobj_priv *dvobj)
+{
+#ifdef CONFIG_DFS_MASTER
+	struct dm_struct *pDM_Odm = dvobj_to_phydm(dvobj);
+
+	return pDM_Odm->dfs_region_domain;
+#else
+	return PHYDM_DFS_DOMAIN_UNKNOWN;
+#endif
+}
+
+inline u8 rtw_odm_dfs_domain_unknown(struct dvobj_priv *dvobj)
+{
+#ifdef CONFIG_DFS_MASTER
+	return rtw_odm_get_dfs_domain(dvobj) == PHYDM_DFS_DOMAIN_UNKNOWN;
+#else
+	return 1;
+#endif
+}
+
+#ifdef CONFIG_DFS_MASTER
+inline VOID rtw_odm_radar_detect_reset(_adapter *adapter)
+{
+	phydm_radar_detect_reset(adapter_to_phydm(adapter));
+}
+
+inline VOID rtw_odm_radar_detect_disable(_adapter *adapter)
+{
+	phydm_radar_detect_disable(adapter_to_phydm(adapter));
+}
+
+/* called after ch, bw is set */
+inline VOID rtw_odm_radar_detect_enable(_adapter *adapter)
+{
+	phydm_radar_detect_enable(adapter_to_phydm(adapter));
+}
+
+inline BOOLEAN rtw_odm_radar_detect(_adapter *adapter)
+{
+	return phydm_radar_detect(adapter_to_phydm(adapter));
+}
+
+inline u8 rtw_odm_radar_detect_polling_int_ms(struct dvobj_priv *dvobj)
+{
+	return phydm_dfs_polling_time(dvobj_to_phydm(dvobj));
+}
+#endif /* CONFIG_DFS_MASTER */
+
+void rtw_odm_parse_rx_phy_status_chinfo(union recv_frame *rframe, u8 *phys)
+{
+#ifndef DBG_RX_PHYSTATUS_CHINFO
+#define DBG_RX_PHYSTATUS_CHINFO 0
+#endif
+
+#if (ODM_PHY_STATUS_NEW_TYPE_SUPPORT == 1)
+	_adapter *adapter = rframe->u.hdr.adapter;
+	struct dm_struct *phydm = adapter_to_phydm(adapter);
+	struct rx_pkt_attrib *attrib = &rframe->u.hdr.attrib;
+	u8 *wlanhdr = get_recvframe_data(rframe);
+
+	if (phydm->support_ic_type & PHYSTS_2ND_TYPE_IC) {
+		/*
+		* 8723D:
+		* type_0(CCK)
+		*     l_rxsc
+		*         is filled with primary channel SC, not real rxsc.
+		*         0:LSC, 1:USC
+		* type_1(OFDM)
+		*     rf_mode
+		*         RF bandwidth when RX
+		*     l_rxsc(legacy), ht_rxsc
+		*         see below RXSC N-series
+		* type_2(Not used)
+		*/
+		/*
+		* 8821C, 8822B:
+		* type_0(CCK)
+		*     l_rxsc
+		*         is filled with primary channel SC, not real rxsc.
+		*         0:LSC, 1:USC
+		* type_1(OFDM)
+		*     rf_mode
+		*         RF bandwidth when RX
+		*     l_rxsc(legacy), ht_rxsc
+		*         see below RXSC AC-series
+		* type_2(Not used)
+		*/
+
+		if ((*phys & 0xf) == 0) {
+			struct phy_status_rpt_jaguar2_type0 *phys_t0 = (struct phy_status_rpt_jaguar2_type0 *)phys;
+
+			if (DBG_RX_PHYSTATUS_CHINFO) {
+				RTW_PRINT("phys_t%u ta="MAC_FMT" %s, %s(band:%u, ch:%u, l_rxsc:%u)\n"
+					, *phys & 0xf
+					, MAC_ARG(get_ta(wlanhdr))
+					, is_broadcast_mac_addr(get_ra(wlanhdr)) ? "BC" : is_multicast_mac_addr(get_ra(wlanhdr)) ? "MC" : "UC"
+					, HDATA_RATE(attrib->data_rate)
+					, phys_t0->band, phys_t0->channel, phys_t0->rxsc
+				);
+			}
+
+		} else if ((*phys & 0xf) == 1) {
+			struct phy_status_rpt_jaguar2_type1 *phys_t1 = (struct phy_status_rpt_jaguar2_type1 *)phys;
+			u8 rxsc = (attrib->data_rate > DESC_RATE11M && attrib->data_rate < DESC_RATEMCS0) ? phys_t1->l_rxsc : phys_t1->ht_rxsc;
+			u8 pkt_cch = 0;
+			u8 pkt_bw = CHANNEL_WIDTH_20;
+
+			#if	ODM_IC_11N_SERIES_SUPPORT
+			if (phydm->support_ic_type & ODM_IC_11N_SERIES) {
+				/* RXSC N-series */
+				#define RXSC_DUP	0
+				#define RXSC_LSC	1
+				#define RXSC_USC	2
+				#define RXSC_40M	3
+
+				static const s8 cch_offset_by_rxsc[4] = {0, -2, 2, 0};
+
+				if (phys_t1->rf_mode == 0) {
+					pkt_cch = phys_t1->channel;
+					pkt_bw = CHANNEL_WIDTH_20;
+				} else if (phys_t1->rf_mode == 1) {
+					if (rxsc == RXSC_LSC || rxsc == RXSC_USC) {
+						pkt_cch = phys_t1->channel + cch_offset_by_rxsc[rxsc];
+						pkt_bw = CHANNEL_WIDTH_20;
+					} else if (rxsc == RXSC_40M) {
+						pkt_cch = phys_t1->channel;
+						pkt_bw = CHANNEL_WIDTH_40;
+					}
+				} else
+					rtw_warn_on(1);
+
+				goto type1_end;
+			}
+			#endif /* ODM_IC_11N_SERIES_SUPPORT */
+
+			#if	ODM_IC_11AC_SERIES_SUPPORT
+			if (phydm->support_ic_type & ODM_IC_11AC_SERIES) {
+				/* RXSC AC-series */
+				#define RXSC_DUP			0 /* 0: RX from all SC of current rf_mode */
+
+				#define RXSC_LL20M_OF_160M	8 /* 1~8: RX from 20MHz SC */
+				#define RXSC_L20M_OF_160M	6
+				#define RXSC_L20M_OF_80M	4
+				#define RXSC_L20M_OF_40M	2
+				#define RXSC_U20M_OF_40M	1
+				#define RXSC_U20M_OF_80M	3
+				#define RXSC_U20M_OF_160M	5
+				#define RXSC_UU20M_OF_160M	7
+
+				#define RXSC_L40M_OF_160M	12 /* 9~12: RX from 40MHz SC */
+				#define RXSC_L40M_OF_80M	10
+				#define RXSC_U40M_OF_80M	9
+				#define RXSC_U40M_OF_160M	11
+
+				#define RXSC_L80M_OF_160M	14 /* 13~14: RX from 80MHz SC */
+				#define RXSC_U80M_OF_160M	13
+
+				static const s8 cch_offset_by_rxsc[15] = {0, 2, -2, 6, -6, 10, -10, 14, -14, 4, -4, 12, -12, 8, -8};
+
+				if (phys_t1->rf_mode > 3) {
+					/* invalid rf_mode */
+					rtw_warn_on(1);
+					goto type1_end;
+				}
+
+				if (phys_t1->rf_mode == 0) {
+					/* RF 20MHz */
+					pkt_cch = phys_t1->channel;
+					pkt_bw = CHANNEL_WIDTH_20;
+					goto type1_end;
+				}
+
+				if (rxsc == 0) {
+					/* RF and RX with same BW */
+					if (attrib->data_rate >= DESC_RATEMCS0) {
+						pkt_cch = phys_t1->channel;
+						pkt_bw = phys_t1->rf_mode;
+					}
+					goto type1_end;
+				}
+
+				if ((phys_t1->rf_mode == 1 && rxsc >= 1 && rxsc <= 2) /* RF 40MHz, RX 20MHz */
+					|| (phys_t1->rf_mode == 2 && rxsc >= 1 && rxsc <= 4) /* RF 80MHz, RX 20MHz */
+					|| (phys_t1->rf_mode == 3 && rxsc >= 1 && rxsc <= 8) /* RF 160MHz, RX 20MHz */
+				) {
+					pkt_cch = phys_t1->channel + cch_offset_by_rxsc[rxsc];
+					pkt_bw = CHANNEL_WIDTH_20;
+				} else if ((phys_t1->rf_mode == 2 && rxsc >= 9 && rxsc <= 10) /* RF 80MHz, RX 40MHz */
+					|| (phys_t1->rf_mode == 3 && rxsc >= 9 && rxsc <= 12) /* RF 160MHz, RX 40MHz */
+				) {
+					if (attrib->data_rate >= DESC_RATEMCS0) {
+						pkt_cch = phys_t1->channel + cch_offset_by_rxsc[rxsc];
+						pkt_bw = CHANNEL_WIDTH_40;
+					}
+				} else if ((phys_t1->rf_mode == 3 && rxsc >= 13 && rxsc <= 14) /* RF 160MHz, RX 80MHz */
+				) {
+					if (attrib->data_rate >= DESC_RATEMCS0) {
+						pkt_cch = phys_t1->channel + cch_offset_by_rxsc[rxsc];
+						pkt_bw = CHANNEL_WIDTH_80;
+					}
+				} else
+					rtw_warn_on(1);
+
+			}
+			#endif /* ODM_IC_11AC_SERIES_SUPPORT */
+
+type1_end:
+			if (DBG_RX_PHYSTATUS_CHINFO) {
+				RTW_PRINT("phys_t%u ta="MAC_FMT" %s, %s(band:%u, ch:%u, rf_mode:%u, l_rxsc:%u, ht_rxsc:%u) => %u,%u\n"
+					, *phys & 0xf
+					, MAC_ARG(get_ta(wlanhdr))
+					, is_broadcast_mac_addr(get_ra(wlanhdr)) ? "BC" : is_multicast_mac_addr(get_ra(wlanhdr)) ? "MC" : "UC"
+					, HDATA_RATE(attrib->data_rate)
+					, phys_t1->band, phys_t1->channel, phys_t1->rf_mode, phys_t1->l_rxsc, phys_t1->ht_rxsc
+					, pkt_cch, pkt_bw
+				);
+			}
+
+			/* for now, only return cneter channel of 20MHz packet */
+			if (pkt_cch && pkt_bw == CHANNEL_WIDTH_20)
+				attrib->ch = pkt_cch;
+
+		} else {
+			struct phy_status_rpt_jaguar2_type2 *phys_t2 = (struct phy_status_rpt_jaguar2_type2 *)phys;
+
+			if (DBG_RX_PHYSTATUS_CHINFO) {
+				RTW_PRINT("phys_t%u ta="MAC_FMT" %s, %s(band:%u, ch:%u, l_rxsc:%u, ht_rxsc:%u)\n"
+					, *phys & 0xf
+					, MAC_ARG(get_ta(wlanhdr))
+					, is_broadcast_mac_addr(get_ra(wlanhdr)) ? "BC" : is_multicast_mac_addr(get_ra(wlanhdr)) ? "MC" : "UC"
+					, HDATA_RATE(attrib->data_rate)
+					, phys_t2->band, phys_t2->channel, phys_t2->l_rxsc, phys_t2->ht_rxsc
+				);
+			}
+		}
+	}
+#endif /* (ODM_PHY_STATUS_NEW_TYPE_SUPPORT == 1) */
+
+}
+
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/core/rtw_p2p.c linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/core/rtw_p2p.c
--- linux-5.6.3/3rdparty/rtl8821ce/core/rtw_p2p.c	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/core/rtw_p2p.c	2020-04-10 16:35:06.777658247 +0300
@@ -0,0 +1,5455 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#define _RTW_P2P_C_
+
+#include <drv_types.h>
+
+#ifdef CONFIG_P2P
+
+int rtw_p2p_is_channel_list_ok(u8 desired_ch, u8 *ch_list, u8 ch_cnt)
+{
+	int found = 0, i = 0;
+
+	for (i = 0; i < ch_cnt; i++) {
+		if (ch_list[i] == desired_ch) {
+			found = 1;
+			break;
+		}
+	}
+	return found ;
+}
+
+int is_any_client_associated(_adapter *padapter)
+{
+	return padapter->stapriv.asoc_list_cnt ? _TRUE : _FALSE;
+}
+
+static u32 go_add_group_info_attr(struct wifidirect_info *pwdinfo, u8 *pbuf)
+{
+	_irqL irqL;
+	_list	*phead, *plist;
+	u32 len = 0;
+	u16 attr_len = 0;
+	u8 tmplen, *pdata_attr, *pstart, *pcur;
+	struct sta_info *psta = NULL;
+	_adapter *padapter = pwdinfo->padapter;
+	struct sta_priv *pstapriv = &padapter->stapriv;
+
+	RTW_INFO(FUNC_ADPT_FMT"\n", FUNC_ADPT_ARG(padapter));
+
+	pdata_attr = rtw_zmalloc(MAX_P2P_IE_LEN);
+
+	if (NULL == pdata_attr) {
+		RTW_INFO("%s pdata_attr malloc failed\n", __FUNCTION__);
+		goto _exit;
+	}
+
+	pstart = pdata_attr;
+	pcur = pdata_attr;
+
+	_enter_critical_bh(&pstapriv->asoc_list_lock, &irqL);
+	phead = &pstapriv->asoc_list;
+	plist = get_next(phead);
+
+	/* look up sta asoc_queue */
+	while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) {
+		psta = LIST_CONTAINOR(plist, struct sta_info, asoc_list);
+
+		plist = get_next(plist);
+
+
+		if (psta->is_p2p_device) {
+			tmplen = 0;
+
+			pcur++;
+
+			/* P2P device address */
+			_rtw_memcpy(pcur, psta->dev_addr, ETH_ALEN);
+			pcur += ETH_ALEN;
+
+			/* P2P interface address */
+			_rtw_memcpy(pcur, psta->cmn.mac_addr, ETH_ALEN);
+			pcur += ETH_ALEN;
+
+			*pcur = psta->dev_cap;
+			pcur++;
+
+			/* *(u16*)(pcur) = cpu_to_be16(psta->config_methods); */
+			RTW_PUT_BE16(pcur, psta->config_methods);
+			pcur += 2;
+
+			_rtw_memcpy(pcur, psta->primary_dev_type, 8);
+			pcur += 8;
+
+			*pcur = psta->num_of_secdev_type;
+			pcur++;
+
+			_rtw_memcpy(pcur, psta->secdev_types_list, psta->num_of_secdev_type * 8);
+			pcur += psta->num_of_secdev_type * 8;
+
+			if (psta->dev_name_len > 0) {
+				/* *(u16*)(pcur) = cpu_to_be16( WPS_ATTR_DEVICE_NAME ); */
+				RTW_PUT_BE16(pcur, WPS_ATTR_DEVICE_NAME);
+				pcur += 2;
+
+				/* *(u16*)(pcur) = cpu_to_be16( psta->dev_name_len ); */
+				RTW_PUT_BE16(pcur, psta->dev_name_len);
+				pcur += 2;
+
+				_rtw_memcpy(pcur, psta->dev_name, psta->dev_name_len);
+				pcur += psta->dev_name_len;
+			}
+
+
+			tmplen = (u8)(pcur - pstart);
+
+			*pstart = (tmplen - 1);
+
+			attr_len += tmplen;
+
+			/* pstart += tmplen; */
+			pstart = pcur;
+
+		}
+
+
+	}
+	_exit_critical_bh(&pstapriv->asoc_list_lock, &irqL);
+
+	if (attr_len > 0)
+		len = rtw_set_p2p_attr_content(pbuf, P2P_ATTR_GROUP_INFO, attr_len, pdata_attr);
+
+	rtw_mfree(pdata_attr, MAX_P2P_IE_LEN);
+
+_exit:
+	return len;
+
+}
+
+static void issue_group_disc_req(struct wifidirect_info *pwdinfo, u8 *da)
+{
+	struct xmit_frame			*pmgntframe;
+	struct pkt_attrib			*pattrib;
+	unsigned char					*pframe;
+	struct rtw_ieee80211_hdr	*pwlanhdr;
+	unsigned short				*fctrl;
+	_adapter *padapter = pwdinfo->padapter;
+	struct xmit_priv			*pxmitpriv = &(padapter->xmitpriv);
+	struct mlme_ext_priv	*pmlmeext = &(padapter->mlmeextpriv);
+	unsigned char category = RTW_WLAN_CATEGORY_P2P;/* P2P action frame	 */
+	u32	p2poui = cpu_to_be32(P2POUI);
+	u8	oui_subtype = P2P_GO_DISC_REQUEST;
+	u8	dialogToken = 0;
+
+	RTW_INFO("[%s]\n", __FUNCTION__);
+
+	pmgntframe = alloc_mgtxmitframe(pxmitpriv);
+	if (pmgntframe == NULL)
+		return;
+
+	/* update attribute */
+	pattrib = &pmgntframe->attrib;
+	update_mgntframe_attrib(padapter, pattrib);
+
+	_rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET);
+
+	pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET;
+	pwlanhdr = (struct rtw_ieee80211_hdr *)pframe;
+
+	fctrl = &(pwlanhdr->frame_ctl);
+	*(fctrl) = 0;
+
+	_rtw_memcpy(pwlanhdr->addr1, da, ETH_ALEN);
+	_rtw_memcpy(pwlanhdr->addr2, pwdinfo->interface_addr, ETH_ALEN);
+	_rtw_memcpy(pwlanhdr->addr3, pwdinfo->interface_addr, ETH_ALEN);
+
+	SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq);
+	pmlmeext->mgnt_seq++;
+	set_frame_sub_type(pframe, WIFI_ACTION);
+
+	pframe += sizeof(struct rtw_ieee80211_hdr_3addr);
+	pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr);
+
+	/* Build P2P action frame header */
+	pframe = rtw_set_fixed_ie(pframe, 1, &(category), &(pattrib->pktlen));
+	pframe = rtw_set_fixed_ie(pframe, 4, (unsigned char *) &(p2poui), &(pattrib->pktlen));
+	pframe = rtw_set_fixed_ie(pframe, 1, &(oui_subtype), &(pattrib->pktlen));
+	pframe = rtw_set_fixed_ie(pframe, 1, &(dialogToken), &(pattrib->pktlen));
+
+	/* there is no IE in this P2P action frame */
+
+	pattrib->last_txcmdsz = pattrib->pktlen;
+
+	dump_mgntframe(padapter, pmgntframe);
+
+}
+
+static void issue_p2p_devdisc_resp(struct wifidirect_info *pwdinfo, u8 *da, u8 status, u8 dialogToken)
+{
+	struct xmit_frame			*pmgntframe;
+	struct pkt_attrib			*pattrib;
+	unsigned char					*pframe;
+	struct rtw_ieee80211_hdr	*pwlanhdr;
+	unsigned short				*fctrl;
+	_adapter *padapter = pwdinfo->padapter;
+	struct xmit_priv			*pxmitpriv = &(padapter->xmitpriv);
+	struct mlme_ext_priv	*pmlmeext = &(padapter->mlmeextpriv);
+	unsigned char category = RTW_WLAN_CATEGORY_PUBLIC;
+	u8			action = P2P_PUB_ACTION_ACTION;
+	u32			p2poui = cpu_to_be32(P2POUI);
+	u8			oui_subtype = P2P_DEVDISC_RESP;
+	u8 p2pie[8] = { 0x00 };
+	u32 p2pielen = 0;
+
+	RTW_INFO("[%s]\n", __FUNCTION__);
+
+	pmgntframe = alloc_mgtxmitframe(pxmitpriv);
+	if (pmgntframe == NULL)
+		return;
+
+	/* update attribute */
+	pattrib = &pmgntframe->attrib;
+	update_mgntframe_attrib(padapter, pattrib);
+
+	_rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET);
+
+	pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET;
+	pwlanhdr = (struct rtw_ieee80211_hdr *)pframe;
+
+	fctrl = &(pwlanhdr->frame_ctl);
+	*(fctrl) = 0;
+
+	_rtw_memcpy(pwlanhdr->addr1, da, ETH_ALEN);
+	_rtw_memcpy(pwlanhdr->addr2, pwdinfo->device_addr, ETH_ALEN);
+	_rtw_memcpy(pwlanhdr->addr3, pwdinfo->device_addr, ETH_ALEN);
+
+	SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq);
+	pmlmeext->mgnt_seq++;
+	set_frame_sub_type(pframe, WIFI_ACTION);
+
+	pframe += sizeof(struct rtw_ieee80211_hdr_3addr);
+	pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr);
+
+	/* Build P2P public action frame header */
+	pframe = rtw_set_fixed_ie(pframe, 1, &(category), &(pattrib->pktlen));
+	pframe = rtw_set_fixed_ie(pframe, 1, &(action), &(pattrib->pktlen));
+	pframe = rtw_set_fixed_ie(pframe, 4, (unsigned char *) &(p2poui), &(pattrib->pktlen));
+	pframe = rtw_set_fixed_ie(pframe, 1, &(oui_subtype), &(pattrib->pktlen));
+	pframe = rtw_set_fixed_ie(pframe, 1, &(dialogToken), &(pattrib->pktlen));
+
+
+	/* Build P2P IE */
+	/*	P2P OUI */
+	p2pielen = 0;
+	p2pie[p2pielen++] = 0x50;
+	p2pie[p2pielen++] = 0x6F;
+	p2pie[p2pielen++] = 0x9A;
+	p2pie[p2pielen++] = 0x09;	/*	WFA P2P v1.0 */
+
+	/* P2P_ATTR_STATUS */
+	p2pielen += rtw_set_p2p_attr_content(&p2pie[p2pielen], P2P_ATTR_STATUS, 1, &status);
+
+	pframe = rtw_set_ie(pframe, _VENDOR_SPECIFIC_IE_, p2pielen, p2pie, &pattrib->pktlen);
+
+	pattrib->last_txcmdsz = pattrib->pktlen;
+
+	dump_mgntframe(padapter, pmgntframe);
+
+}
+
+static void issue_p2p_provision_resp(struct wifidirect_info *pwdinfo, u8 *raddr, u8 *frame_body, u16 config_method)
+{
+	_adapter *padapter = pwdinfo->padapter;
+	unsigned char category = RTW_WLAN_CATEGORY_PUBLIC;
+	u8			action = P2P_PUB_ACTION_ACTION;
+	u8			dialogToken = frame_body[7];	/*	The Dialog Token of provisioning discovery request frame. */
+	u32			p2poui = cpu_to_be32(P2POUI);
+	u8			oui_subtype = P2P_PROVISION_DISC_RESP;
+	u8			wpsie[100] = { 0x00 };
+	u8			wpsielen = 0;
+#ifdef CONFIG_WFD
+	u32					wfdielen = 0;
+#endif
+
+	struct xmit_frame			*pmgntframe;
+	struct pkt_attrib			*pattrib;
+	unsigned char					*pframe;
+	struct rtw_ieee80211_hdr	*pwlanhdr;
+	unsigned short				*fctrl;
+	struct xmit_priv			*pxmitpriv = &(padapter->xmitpriv);
+	struct mlme_ext_priv	*pmlmeext = &(padapter->mlmeextpriv);
+
+
+	pmgntframe = alloc_mgtxmitframe(pxmitpriv);
+	if (pmgntframe == NULL)
+		return;
+
+	/* update attribute */
+	pattrib = &pmgntframe->attrib;
+	update_mgntframe_attrib(padapter, pattrib);
+
+	_rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET);
+
+	pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET;
+	pwlanhdr = (struct rtw_ieee80211_hdr *)pframe;
+
+	fctrl = &(pwlanhdr->frame_ctl);
+	*(fctrl) = 0;
+
+	_rtw_memcpy(pwlanhdr->addr1, raddr, ETH_ALEN);
+	_rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN);
+	_rtw_memcpy(pwlanhdr->addr3, adapter_mac_addr(padapter), ETH_ALEN);
+
+	SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq);
+	pmlmeext->mgnt_seq++;
+	set_frame_sub_type(pframe, WIFI_ACTION);
+
+	pframe += sizeof(struct rtw_ieee80211_hdr_3addr);
+	pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr);
+
+	pframe = rtw_set_fixed_ie(pframe, 1, &(category), &(pattrib->pktlen));
+	pframe = rtw_set_fixed_ie(pframe, 1, &(action), &(pattrib->pktlen));
+	pframe = rtw_set_fixed_ie(pframe, 4, (unsigned char *) &(p2poui), &(pattrib->pktlen));
+	pframe = rtw_set_fixed_ie(pframe, 1, &(oui_subtype), &(pattrib->pktlen));
+	pframe = rtw_set_fixed_ie(pframe, 1, &(dialogToken), &(pattrib->pktlen));
+
+	wpsielen = 0;
+	/*	WPS OUI */
+	/* *(u32*) ( wpsie ) = cpu_to_be32( WPSOUI ); */
+	RTW_PUT_BE32(wpsie, WPSOUI);
+	wpsielen += 4;
+
+#if 0
+	/*	WPS version */
+	/*	Type: */
+	*(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_ATTR_VER1);
+	wpsielen += 2;
+
+	/*	Length: */
+	*(u16 *)(wpsie + wpsielen) = cpu_to_be16(0x0001);
+	wpsielen += 2;
+
+	/*	Value: */
+	wpsie[wpsielen++] = WPS_VERSION_1;	/*	Version 1.0 */
+#endif
+
+	/*	Config Method */
+	/*	Type: */
+	/* *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( WPS_ATTR_CONF_METHOD ); */
+	RTW_PUT_BE16(wpsie + wpsielen, WPS_ATTR_CONF_METHOD);
+	wpsielen += 2;
+
+	/*	Length: */
+	/* *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( 0x0002 ); */
+	RTW_PUT_BE16(wpsie + wpsielen, 0x0002);
+	wpsielen += 2;
+
+	/*	Value: */
+	/* *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( config_method ); */
+	RTW_PUT_BE16(wpsie + wpsielen, config_method);
+	wpsielen += 2;
+
+	pframe = rtw_set_ie(pframe, _VENDOR_SPECIFIC_IE_, wpsielen, (unsigned char *) wpsie, &pattrib->pktlen);
+
+#ifdef CONFIG_WFD
+	wfdielen = build_provdisc_resp_wfd_ie(pwdinfo, pframe);
+	pframe += wfdielen;
+	pattrib->pktlen += wfdielen;
+#endif
+
+	pattrib->last_txcmdsz = pattrib->pktlen;
+
+	dump_mgntframe(padapter, pmgntframe);
+
+	return;
+
+}
+
+static void issue_p2p_presence_resp(struct wifidirect_info *pwdinfo, u8 *da, u8 status, u8 dialogToken)
+{
+	struct xmit_frame			*pmgntframe;
+	struct pkt_attrib			*pattrib;
+	unsigned char					*pframe;
+	struct rtw_ieee80211_hdr	*pwlanhdr;
+	unsigned short				*fctrl;
+	_adapter *padapter = pwdinfo->padapter;
+	struct xmit_priv			*pxmitpriv = &(padapter->xmitpriv);
+	struct mlme_ext_priv	*pmlmeext = &(padapter->mlmeextpriv);
+	unsigned char category = RTW_WLAN_CATEGORY_P2P;/* P2P action frame	 */
+	u32	p2poui = cpu_to_be32(P2POUI);
+	u8	oui_subtype = P2P_PRESENCE_RESPONSE;
+	u8 p2pie[MAX_P2P_IE_LEN] = { 0x00 };
+	u8 noa_attr_content[32] = { 0x00 };
+	u32 p2pielen = 0;
+
+	RTW_INFO("[%s]\n", __FUNCTION__);
+
+	pmgntframe = alloc_mgtxmitframe(pxmitpriv);
+	if (pmgntframe == NULL)
+		return;
+
+	/* update attribute */
+	pattrib = &pmgntframe->attrib;
+	update_mgntframe_attrib(padapter, pattrib);
+
+	_rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET);
+
+	pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET;
+	pwlanhdr = (struct rtw_ieee80211_hdr *)pframe;
+
+	fctrl = &(pwlanhdr->frame_ctl);
+	*(fctrl) = 0;
+
+	_rtw_memcpy(pwlanhdr->addr1, da, ETH_ALEN);
+	_rtw_memcpy(pwlanhdr->addr2, pwdinfo->interface_addr, ETH_ALEN);
+	_rtw_memcpy(pwlanhdr->addr3, pwdinfo->interface_addr, ETH_ALEN);
+
+	SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq);
+	pmlmeext->mgnt_seq++;
+	set_frame_sub_type(pframe, WIFI_ACTION);
+
+	pframe += sizeof(struct rtw_ieee80211_hdr_3addr);
+	pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr);
+
+	/* Build P2P action frame header */
+	pframe = rtw_set_fixed_ie(pframe, 1, &(category), &(pattrib->pktlen));
+	pframe = rtw_set_fixed_ie(pframe, 4, (unsigned char *) &(p2poui), &(pattrib->pktlen));
+	pframe = rtw_set_fixed_ie(pframe, 1, &(oui_subtype), &(pattrib->pktlen));
+	pframe = rtw_set_fixed_ie(pframe, 1, &(dialogToken), &(pattrib->pktlen));
+
+
+	/* Add P2P IE header */
+	/*	P2P OUI */
+	p2pielen = 0;
+	p2pie[p2pielen++] = 0x50;
+	p2pie[p2pielen++] = 0x6F;
+	p2pie[p2pielen++] = 0x9A;
+	p2pie[p2pielen++] = 0x09;	/*	WFA P2P v1.0 */
+
+	/* Add Status attribute in P2P IE */
+	p2pielen += rtw_set_p2p_attr_content(&p2pie[p2pielen], P2P_ATTR_STATUS, 1, &status);
+
+	/* Add NoA attribute in P2P IE */
+	noa_attr_content[0] = 0x1;/* index */
+	noa_attr_content[1] = 0x0;/* CTWindow and OppPS Parameters */
+
+	/* todo: Notice of Absence Descriptor(s) */
+
+	p2pielen += rtw_set_p2p_attr_content(&p2pie[p2pielen], P2P_ATTR_NOA, 2, noa_attr_content);
+
+
+
+	pframe = rtw_set_ie(pframe, _VENDOR_SPECIFIC_IE_, p2pielen, p2pie, &(pattrib->pktlen));
+
+
+	pattrib->last_txcmdsz = pattrib->pktlen;
+
+	dump_mgntframe(padapter, pmgntframe);
+
+}
+
+u32 build_beacon_p2p_ie(struct wifidirect_info *pwdinfo, u8 *pbuf)
+{
+	u8 p2pie[MAX_P2P_IE_LEN] = { 0x00 };
+	u16 capability = 0;
+	u32 len = 0, p2pielen = 0;
+
+
+	/*	P2P OUI */
+	p2pielen = 0;
+	p2pie[p2pielen++] = 0x50;
+	p2pie[p2pielen++] = 0x6F;
+	p2pie[p2pielen++] = 0x9A;
+	p2pie[p2pielen++] = 0x09;	/*	WFA P2P v1.0 */
+
+
+	/*	According to the P2P Specification, the beacon frame should contain 3 P2P attributes */
+	/*	1. P2P Capability */
+	/*	2. P2P Device ID */
+	/*	3. Notice of Absence ( NOA )	 */
+
+	/*	P2P Capability ATTR */
+	/*	Type: */
+	/*	Length: */
+	/*	Value: */
+	/*	Device Capability Bitmap, 1 byte */
+	/*	Be able to participate in additional P2P Groups and */
+	/*	support the P2P Invitation Procedure	 */
+	/*	Group Capability Bitmap, 1 byte	 */
+	capability = P2P_DEVCAP_INVITATION_PROC | P2P_DEVCAP_CLIENT_DISCOVERABILITY;
+	capability |= ((P2P_GRPCAP_GO | P2P_GRPCAP_INTRABSS) << 8);
+	if (rtw_p2p_chk_state(pwdinfo, P2P_STATE_PROVISIONING_ING))
+		capability |= (P2P_GRPCAP_GROUP_FORMATION << 8);
+
+	capability = cpu_to_le16(capability);
+
+	p2pielen += rtw_set_p2p_attr_content(&p2pie[p2pielen], P2P_ATTR_CAPABILITY, 2, (u8 *)&capability);
+
+
+	/* P2P Device ID ATTR */
+	p2pielen += rtw_set_p2p_attr_content(&p2pie[p2pielen], P2P_ATTR_DEVICE_ID, ETH_ALEN, pwdinfo->device_addr);
+
+
+	/* Notice of Absence ATTR */
+	/*	Type:  */
+	/*	Length: */
+	/*	Value: */
+
+	/* go_add_noa_attr(pwdinfo); */
+
+
+	pbuf = rtw_set_ie(pbuf, _VENDOR_SPECIFIC_IE_, p2pielen, (unsigned char *) p2pie, &len);
+
+
+	return len;
+
+}
+
+#ifdef CONFIG_WFD
+u32 build_beacon_wfd_ie(struct wifidirect_info *pwdinfo, u8 *pbuf)
+{
+	u8 wfdie[MAX_WFD_IE_LEN] = { 0x00 };
+	u16 val16 = 0;
+	u32 len = 0, wfdielen = 0;
+	_adapter *padapter = pwdinfo->padapter;
+	struct mlme_priv		*pmlmepriv = &padapter->mlmepriv;
+	struct wifi_display_info	*pwfd_info = padapter->wdinfo.wfd_info;
+
+	if (!hal_chk_wl_func(padapter, WL_FUNC_MIRACAST))
+		goto exit;
+
+	/*	WFD OUI */
+	wfdielen = 0;
+	wfdie[wfdielen++] = 0x50;
+	wfdie[wfdielen++] = 0x6F;
+	wfdie[wfdielen++] = 0x9A;
+	wfdie[wfdielen++] = 0x0A;	/*	WFA WFD v1.0 */
+
+	/*	Commented by Albert 20110812 */
+	/*	According to the WFD Specification, the beacon frame should contain 4 WFD attributes */
+	/*	1. WFD Device Information */
+	/*	2. Associated BSSID */
+	/*	3. Coupled Sink Information */
+
+
+	/*	WFD Device Information ATTR */
+	/*	Type: */
+	wfdie[wfdielen++] = WFD_ATTR_DEVICE_INFO;
+
+	/*	Length: */
+	/*	Note: In the WFD specification, the size of length field is 2. */
+	RTW_PUT_BE16(wfdie + wfdielen, 0x0006);
+	wfdielen += 2;
+
+	/*	Value1: */
+	/*	WFD device information */
+
+	if (P2P_ROLE_GO == pwdinfo->role) {
+		if (is_any_client_associated(pwdinfo->padapter)) {
+			/*	WFD primary sink + WiFi Direct mode + WSD (WFD Service Discovery) */
+			val16 = pwfd_info->wfd_device_type | WFD_DEVINFO_WSD;
+			RTW_PUT_BE16(wfdie + wfdielen, val16);
+		} else {
+			/*	WFD primary sink + available for WFD session + WiFi Direct mode + WSD (WFD Service Discovery) */
+			val16 = pwfd_info->wfd_device_type | WFD_DEVINFO_SESSION_AVAIL | WFD_DEVINFO_WSD;
+			RTW_PUT_BE16(wfdie + wfdielen, val16);
+		}
+
+	} else {
+		/*	WFD primary sink + available for WFD session + WiFi Direct mode + WSD ( WFD Service Discovery ) */
+		val16 = pwfd_info->wfd_device_type | WFD_DEVINFO_SESSION_AVAIL | WFD_DEVINFO_WSD;
+		RTW_PUT_BE16(wfdie + wfdielen, val16);
+	}
+
+	wfdielen += 2;
+
+	/*	Value2: */
+	/*	Session Management Control Port */
+	/*	Default TCP port for RTSP messages is 554 */
+	RTW_PUT_BE16(wfdie + wfdielen, pwfd_info->rtsp_ctrlport);
+	wfdielen += 2;
+
+	/*	Value3: */
+	/*	WFD Device Maximum Throughput */
+	/*	300Mbps is the maximum throughput */
+	RTW_PUT_BE16(wfdie + wfdielen, 300);
+	wfdielen += 2;
+
+	/*	Associated BSSID ATTR */
+	/*	Type: */
+	wfdie[wfdielen++] = WFD_ATTR_ASSOC_BSSID;
+
+	/*	Length: */
+	/*	Note: In the WFD specification, the size of length field is 2. */
+	RTW_PUT_BE16(wfdie + wfdielen, 0x0006);
+	wfdielen += 2;
+
+	/*	Value: */
+	/*	Associated BSSID */
+	if (check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE)
+		_rtw_memcpy(wfdie + wfdielen, &pmlmepriv->assoc_bssid[0], ETH_ALEN);
+	else
+		_rtw_memset(wfdie + wfdielen, 0x00, ETH_ALEN);
+
+	wfdielen += ETH_ALEN;
+
+	/*	Coupled Sink Information ATTR */
+	/*	Type: */
+	wfdie[wfdielen++] = WFD_ATTR_COUPLED_SINK_INFO;
+
+	/*	Length: */
+	/*	Note: In the WFD specification, the size of length field is 2. */
+	RTW_PUT_BE16(wfdie + wfdielen, 0x0007);
+	wfdielen += 2;
+
+	/*	Value: */
+	/*	Coupled Sink Status bitmap */
+	/*	Not coupled/available for Coupling */
+	wfdie[wfdielen++] = 0;
+	/* MAC Addr. */
+	wfdie[wfdielen++] = 0;
+	wfdie[wfdielen++] = 0;
+	wfdie[wfdielen++] = 0;
+	wfdie[wfdielen++] = 0;
+	wfdie[wfdielen++] = 0;
+	wfdie[wfdielen++] = 0;
+
+	rtw_set_ie(pbuf, _VENDOR_SPECIFIC_IE_, wfdielen, (unsigned char *) wfdie, &len);
+
+exit:
+	return len;
+}
+
+u32 build_probe_req_wfd_ie(struct wifidirect_info *pwdinfo, u8 *pbuf)
+{
+	u8 wfdie[MAX_WFD_IE_LEN] = { 0x00 };
+	u16 val16 = 0;
+	u32 len = 0, wfdielen = 0;
+	_adapter *padapter = pwdinfo->padapter;
+	struct mlme_priv		*pmlmepriv = &padapter->mlmepriv;
+	struct wifi_display_info	*pwfd_info = padapter->wdinfo.wfd_info;
+
+	if (!hal_chk_wl_func(padapter, WL_FUNC_MIRACAST))
+		goto exit;
+
+	/*	WFD OUI */
+	wfdielen = 0;
+	wfdie[wfdielen++] = 0x50;
+	wfdie[wfdielen++] = 0x6F;
+	wfdie[wfdielen++] = 0x9A;
+	wfdie[wfdielen++] = 0x0A;	/*	WFA WFD v1.0 */
+
+	/*	Commented by Albert 20110812 */
+	/*	According to the WFD Specification, the probe request frame should contain 4 WFD attributes */
+	/*	1. WFD Device Information */
+	/*	2. Associated BSSID */
+	/*	3. Coupled Sink Information */
+
+
+	/*	WFD Device Information ATTR */
+	/*	Type: */
+	wfdie[wfdielen++] = WFD_ATTR_DEVICE_INFO;
+
+	/*	Length: */
+	/*	Note: In the WFD specification, the size of length field is 2. */
+	RTW_PUT_BE16(wfdie + wfdielen, 0x0006);
+	wfdielen += 2;
+
+	/*	Value1: */
+	/*	WFD device information */
+
+	if (1 == pwdinfo->wfd_tdls_enable) {
+		/*	WFD primary sink + available for WFD session + WiFi TDLS mode + WSC ( WFD Service Discovery )	 */
+		val16 = pwfd_info->wfd_device_type |
+			WFD_DEVINFO_SESSION_AVAIL |
+			WFD_DEVINFO_WSD |
+			WFD_DEVINFO_PC_TDLS;
+		RTW_PUT_BE16(wfdie + wfdielen, val16);
+	} else {
+		/*	WFD primary sink + available for WFD session + WiFi Direct mode + WSC ( WFD Service Discovery )	 */
+		val16 = pwfd_info->wfd_device_type |
+			WFD_DEVINFO_SESSION_AVAIL |
+			WFD_DEVINFO_WSD;
+		RTW_PUT_BE16(wfdie + wfdielen, val16);
+	}
+
+	wfdielen += 2;
+
+	/*	Value2: */
+	/*	Session Management Control Port */
+	/*	Default TCP port for RTSP messages is 554 */
+	RTW_PUT_BE16(wfdie + wfdielen, pwfd_info->rtsp_ctrlport);
+	wfdielen += 2;
+
+	/*	Value3: */
+	/*	WFD Device Maximum Throughput */
+	/*	300Mbps is the maximum throughput */
+	RTW_PUT_BE16(wfdie + wfdielen, 300);
+	wfdielen += 2;
+
+	/*	Associated BSSID ATTR */
+	/*	Type: */
+	wfdie[wfdielen++] = WFD_ATTR_ASSOC_BSSID;
+
+	/*	Length: */
+	/*	Note: In the WFD specification, the size of length field is 2. */
+	RTW_PUT_BE16(wfdie + wfdielen, 0x0006);
+	wfdielen += 2;
+
+	/*	Value: */
+	/*	Associated BSSID */
+	if (check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE)
+		_rtw_memcpy(wfdie + wfdielen, &pmlmepriv->assoc_bssid[0], ETH_ALEN);
+	else
+		_rtw_memset(wfdie + wfdielen, 0x00, ETH_ALEN);
+
+	wfdielen += ETH_ALEN;
+
+	/*	Coupled Sink Information ATTR */
+	/*	Type: */
+	wfdie[wfdielen++] = WFD_ATTR_COUPLED_SINK_INFO;
+
+	/*	Length: */
+	/*	Note: In the WFD specification, the size of length field is 2. */
+	RTW_PUT_BE16(wfdie + wfdielen, 0x0007);
+	wfdielen += 2;
+
+	/*	Value: */
+	/*	Coupled Sink Status bitmap */
+	/*	Not coupled/available for Coupling */
+	wfdie[wfdielen++] = 0;
+	/* MAC Addr. */
+	wfdie[wfdielen++] = 0;
+	wfdie[wfdielen++] = 0;
+	wfdie[wfdielen++] = 0;
+	wfdie[wfdielen++] = 0;
+	wfdie[wfdielen++] = 0;
+	wfdie[wfdielen++] = 0;
+
+	rtw_set_ie(pbuf, _VENDOR_SPECIFIC_IE_, wfdielen, (unsigned char *) wfdie, &len);
+
+exit:
+	return len;
+}
+
+u32 build_probe_resp_wfd_ie(struct wifidirect_info *pwdinfo, u8 *pbuf, u8 tunneled)
+{
+	u8 wfdie[MAX_WFD_IE_LEN] = { 0x00 };
+	u32 len = 0, wfdielen = 0;
+	_adapter *padapter = pwdinfo->padapter;
+	struct mlme_priv		*pmlmepriv = &padapter->mlmepriv;
+	struct wifi_display_info	*pwfd_info = padapter->wdinfo.wfd_info;
+	u16 v16 = 0;
+
+	if (!hal_chk_wl_func(padapter, WL_FUNC_MIRACAST))
+		goto exit;
+
+	/*	WFD OUI */
+	wfdielen = 0;
+	wfdie[wfdielen++] = 0x50;
+	wfdie[wfdielen++] = 0x6F;
+	wfdie[wfdielen++] = 0x9A;
+	wfdie[wfdielen++] = 0x0A;	/*	WFA WFD v1.0 */
+
+	/*	Commented by Albert 20110812 */
+	/*	According to the WFD Specification, the probe response frame should contain 4 WFD attributes */
+	/*	1. WFD Device Information */
+	/*	2. Associated BSSID */
+	/*	3. Coupled Sink Information */
+	/*	4. WFD Session Information */
+
+
+	/*	WFD Device Information ATTR */
+	/*	Type: */
+	wfdie[wfdielen++] = WFD_ATTR_DEVICE_INFO;
+
+	/*	Length: */
+	/*	Note: In the WFD specification, the size of length field is 2. */
+	RTW_PUT_BE16(wfdie + wfdielen, 0x0006);
+	wfdielen += 2;
+
+	/*	Value1: */
+	/*	WFD device information */
+	/*	WFD primary sink + available for WFD session + WiFi Direct mode */
+
+	if (_TRUE == pwdinfo->session_available) {
+		if (P2P_ROLE_GO == pwdinfo->role) {
+			if (is_any_client_associated(pwdinfo->padapter)) {
+				if (pwdinfo->wfd_tdls_enable) {
+					/*	TDLS mode + WSD ( WFD Service Discovery ) */
+					v16 = pwfd_info->wfd_device_type | WFD_DEVINFO_WSD | WFD_DEVINFO_PC_TDLS | WFD_DEVINFO_HDCP_SUPPORT;
+					RTW_PUT_BE16(wfdie + wfdielen, v16);
+				} else {
+					/*	WiFi Direct mode + WSD ( WFD Service Discovery ) */
+					v16 =  pwfd_info->wfd_device_type | WFD_DEVINFO_WSD | WFD_DEVINFO_HDCP_SUPPORT;
+					RTW_PUT_BE16(wfdie + wfdielen, v16);
+				}
+			} else {
+				if (pwdinfo->wfd_tdls_enable) {
+					/*	available for WFD session + TDLS mode + WSD ( WFD Service Discovery ) */
+					v16 = pwfd_info->wfd_device_type | WFD_DEVINFO_SESSION_AVAIL | WFD_DEVINFO_WSD | WFD_DEVINFO_PC_TDLS | WFD_DEVINFO_HDCP_SUPPORT;
+					RTW_PUT_BE16(wfdie + wfdielen, v16);
+				} else {
+					/*	available for WFD session + WiFi Direct mode + WSD ( WFD Service Discovery ) */
+					v16 = pwfd_info->wfd_device_type | WFD_DEVINFO_SESSION_AVAIL | WFD_DEVINFO_WSD | WFD_DEVINFO_HDCP_SUPPORT;
+					RTW_PUT_BE16(wfdie + wfdielen, v16);
+				}
+			}
+		} else {
+			if (pwdinfo->wfd_tdls_enable) {
+				/*	available for WFD session + WiFi Direct mode + WSD ( WFD Service Discovery ) */
+				v16 = pwfd_info->wfd_device_type | WFD_DEVINFO_SESSION_AVAIL | WFD_DEVINFO_WSD | WFD_DEVINFO_PC_TDLS | WFD_DEVINFO_HDCP_SUPPORT;
+				RTW_PUT_BE16(wfdie + wfdielen, v16);
+			} else {
+				/*	available for WFD session + WiFi Direct mode + WSD ( WFD Service Discovery ) */
+				v16 =  pwfd_info->wfd_device_type | WFD_DEVINFO_SESSION_AVAIL | WFD_DEVINFO_WSD | WFD_DEVINFO_HDCP_SUPPORT;
+				RTW_PUT_BE16(wfdie + wfdielen, v16);
+			}
+		}
+	} else {
+		if (pwdinfo->wfd_tdls_enable) {
+			v16 = pwfd_info->wfd_device_type | WFD_DEVINFO_WSD | WFD_DEVINFO_PC_TDLS | WFD_DEVINFO_HDCP_SUPPORT;
+			RTW_PUT_BE16(wfdie + wfdielen, v16);
+		} else {
+			v16 =  pwfd_info->wfd_device_type | WFD_DEVINFO_WSD | WFD_DEVINFO_HDCP_SUPPORT;
+			RTW_PUT_BE16(wfdie + wfdielen, v16);
+		}
+	}
+
+	wfdielen += 2;
+
+	/*	Value2: */
+	/*	Session Management Control Port */
+	/*	Default TCP port for RTSP messages is 554 */
+	RTW_PUT_BE16(wfdie + wfdielen, pwfd_info->rtsp_ctrlport);
+	wfdielen += 2;
+
+	/*	Value3: */
+	/*	WFD Device Maximum Throughput */
+	/*	300Mbps is the maximum throughput */
+	RTW_PUT_BE16(wfdie + wfdielen, 300);
+	wfdielen += 2;
+
+	/*	Associated BSSID ATTR */
+	/*	Type: */
+	wfdie[wfdielen++] = WFD_ATTR_ASSOC_BSSID;
+
+	/*	Length: */
+	/*	Note: In the WFD specification, the size of length field is 2. */
+	RTW_PUT_BE16(wfdie + wfdielen, 0x0006);
+	wfdielen += 2;
+
+	/*	Value: */
+	/*	Associated BSSID */
+	if (check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE)
+		_rtw_memcpy(wfdie + wfdielen, &pmlmepriv->assoc_bssid[0], ETH_ALEN);
+	else
+		_rtw_memset(wfdie + wfdielen, 0x00, ETH_ALEN);
+
+	wfdielen += ETH_ALEN;
+
+	/*	Coupled Sink Information ATTR */
+	/*	Type: */
+	wfdie[wfdielen++] = WFD_ATTR_COUPLED_SINK_INFO;
+
+	/*	Length: */
+	/*	Note: In the WFD specification, the size of length field is 2. */
+	RTW_PUT_BE16(wfdie + wfdielen, 0x0007);
+	wfdielen += 2;
+
+	/*	Value: */
+	/*	Coupled Sink Status bitmap */
+	/*	Not coupled/available for Coupling */
+	wfdie[wfdielen++] = 0;
+	/* MAC Addr. */
+	wfdie[wfdielen++] = 0;
+	wfdie[wfdielen++] = 0;
+	wfdie[wfdielen++] = 0;
+	wfdie[wfdielen++] = 0;
+	wfdie[wfdielen++] = 0;
+	wfdie[wfdielen++] = 0;
+
+	if (rtw_p2p_chk_role(pwdinfo, P2P_ROLE_GO)) {
+		/*	WFD Session Information ATTR */
+		/*	Type: */
+		wfdie[wfdielen++] = WFD_ATTR_SESSION_INFO;
+
+		/*	Length: */
+		/*	Note: In the WFD specification, the size of length field is 2. */
+		RTW_PUT_BE16(wfdie + wfdielen, 0x0000);
+		wfdielen += 2;
+
+		/*	Todo: to add the list of WFD device info descriptor in WFD group. */
+
+	}
+#ifdef CONFIG_CONCURRENT_MODE
+#ifdef CONFIG_TDLS
+	{
+		int i;
+		_adapter *iface = NULL;
+		struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
+
+		for (i = 0; i < dvobj->iface_nums; i++) {
+			iface = dvobj->padapters[i];
+			if ((iface) && rtw_is_adapter_up(iface)) {
+				if (iface == padapter)
+					continue;
+
+				if ((tunneled == 0) && (iface->wdinfo.wfd_tdls_enable == 1)) {
+					/*	Alternative MAC Address ATTR
+						Type:					*/
+					wfdie[wfdielen++] = WFD_ATTR_ALTER_MAC;
+
+					/*	Length:
+						Note: In the WFD specification, the size of length field is 2.*/
+					RTW_PUT_BE16(wfdie + wfdielen,  ETH_ALEN);
+					wfdielen += 2;
+
+					/*	Value:
+						Alternative MAC Address*/
+					_rtw_memcpy(wfdie + wfdielen, adapter_mac_addr(iface), ETH_ALEN);
+					wfdielen += ETH_ALEN;
+				}
+			}
+		}
+	}
+
+#endif /* CONFIG_TDLS*/
+#endif /* CONFIG_CONCURRENT_MODE */
+
+	pbuf = rtw_set_ie(pbuf, _VENDOR_SPECIFIC_IE_, wfdielen, (unsigned char *) wfdie, &len);
+
+exit:
+	return len;
+}
+
+u32 build_assoc_req_wfd_ie(struct wifidirect_info *pwdinfo, u8 *pbuf)
+{
+	u8 wfdie[MAX_WFD_IE_LEN] = { 0x00 };
+	u16 val16 = 0;
+	u32 len = 0, wfdielen = 0;
+	_adapter					*padapter = NULL;
+	struct mlme_priv			*pmlmepriv = NULL;
+	struct wifi_display_info		*pwfd_info = NULL;
+
+	padapter = pwdinfo->padapter;
+	pmlmepriv = &padapter->mlmepriv;
+	pwfd_info = padapter->wdinfo.wfd_info;
+
+	if (!hal_chk_wl_func(padapter, WL_FUNC_MIRACAST))
+		goto exit;
+
+	if (rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE) || rtw_p2p_chk_state(pwdinfo, P2P_STATE_IDLE))
+		goto exit;
+
+	/* WFD OUI */
+	wfdielen = 0;
+	wfdie[wfdielen++] = 0x50;
+	wfdie[wfdielen++] = 0x6F;
+	wfdie[wfdielen++] = 0x9A;
+	wfdie[wfdielen++] = 0x0A;	/*	WFA WFD v1.0 */
+
+	/*	Commented by Albert 20110812 */
+	/*	According to the WFD Specification, the probe request frame should contain 4 WFD attributes */
+	/*	1. WFD Device Information */
+	/*	2. Associated BSSID */
+	/*	3. Coupled Sink Information */
+
+
+	/*	WFD Device Information ATTR */
+	/*	Type: */
+	wfdie[wfdielen++] = WFD_ATTR_DEVICE_INFO;
+
+	/*	Length: */
+	/*	Note: In the WFD specification, the size of length field is 2. */
+	RTW_PUT_BE16(wfdie + wfdielen, 0x0006);
+	wfdielen += 2;
+
+	/*	Value1: */
+	/*	WFD device information */
+	/*	WFD primary sink + available for WFD session + WiFi Direct mode + WSD ( WFD Service Discovery ) */
+	val16 = pwfd_info->wfd_device_type | WFD_DEVINFO_SESSION_AVAIL | WFD_DEVINFO_WSD;
+	RTW_PUT_BE16(wfdie + wfdielen, val16);
+	wfdielen += 2;
+
+	/*	Value2: */
+	/*	Session Management Control Port */
+	/*	Default TCP port for RTSP messages is 554 */
+	RTW_PUT_BE16(wfdie + wfdielen, pwfd_info->rtsp_ctrlport);
+	wfdielen += 2;
+
+	/*	Value3: */
+	/*	WFD Device Maximum Throughput */
+	/*	300Mbps is the maximum throughput */
+	RTW_PUT_BE16(wfdie + wfdielen, 300);
+	wfdielen += 2;
+
+	/*	Associated BSSID ATTR */
+	/*	Type: */
+	wfdie[wfdielen++] = WFD_ATTR_ASSOC_BSSID;
+
+	/*	Length: */
+	/*	Note: In the WFD specification, the size of length field is 2. */
+	RTW_PUT_BE16(wfdie + wfdielen, 0x0006);
+	wfdielen += 2;
+
+	/*	Value: */
+	/*	Associated BSSID */
+	if (check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE)
+		_rtw_memcpy(wfdie + wfdielen, &pmlmepriv->assoc_bssid[0], ETH_ALEN);
+	else
+		_rtw_memset(wfdie + wfdielen, 0x00, ETH_ALEN);
+
+	wfdielen += ETH_ALEN;
+
+	/*	Coupled Sink Information ATTR */
+	/*	Type: */
+	wfdie[wfdielen++] = WFD_ATTR_COUPLED_SINK_INFO;
+
+	/*	Length: */
+	/*	Note: In the WFD specification, the size of length field is 2. */
+	RTW_PUT_BE16(wfdie + wfdielen, 0x0007);
+	wfdielen += 2;
+
+	/*	Value: */
+	/*	Coupled Sink Status bitmap */
+	/*	Not coupled/available for Coupling */
+	wfdie[wfdielen++] = 0;
+	/* MAC Addr. */
+	wfdie[wfdielen++] = 0;
+	wfdie[wfdielen++] = 0;
+	wfdie[wfdielen++] = 0;
+	wfdie[wfdielen++] = 0;
+	wfdie[wfdielen++] = 0;
+	wfdie[wfdielen++] = 0;
+
+	rtw_set_ie(pbuf, _VENDOR_SPECIFIC_IE_, wfdielen, (unsigned char *) wfdie, &len);
+
+exit:
+	return len;
+}
+
+u32 build_assoc_resp_wfd_ie(struct wifidirect_info *pwdinfo, u8 *pbuf)
+{
+	u8 wfdie[MAX_WFD_IE_LEN] = { 0x00 };
+	u32 len = 0, wfdielen = 0;
+	u16 val16 = 0;
+	_adapter *padapter = pwdinfo->padapter;
+	struct mlme_priv		*pmlmepriv = &padapter->mlmepriv;
+	struct wifi_display_info	*pwfd_info = padapter->wdinfo.wfd_info;
+
+	if (!hal_chk_wl_func(padapter, WL_FUNC_MIRACAST))
+		goto exit;
+
+	/*	WFD OUI */
+	wfdielen = 0;
+	wfdie[wfdielen++] = 0x50;
+	wfdie[wfdielen++] = 0x6F;
+	wfdie[wfdielen++] = 0x9A;
+	wfdie[wfdielen++] = 0x0A;	/*	WFA WFD v1.0 */
+
+	/*	Commented by Albert 20110812 */
+	/*	According to the WFD Specification, the probe request frame should contain 4 WFD attributes */
+	/*	1. WFD Device Information */
+	/*	2. Associated BSSID */
+	/*	3. Coupled Sink Information */
+
+
+	/*	WFD Device Information ATTR */
+	/*	Type: */
+	wfdie[wfdielen++] = WFD_ATTR_DEVICE_INFO;
+
+	/*	Length: */
+	/*	Note: In the WFD specification, the size of length field is 2. */
+	RTW_PUT_BE16(wfdie + wfdielen, 0x0006);
+	wfdielen += 2;
+
+	/*	Value1: */
+	/*	WFD device information */
+	/*	WFD primary sink + available for WFD session + WiFi Direct mode + WSD ( WFD Service Discovery ) */
+	val16 = pwfd_info->wfd_device_type | WFD_DEVINFO_SESSION_AVAIL | WFD_DEVINFO_WSD;
+	RTW_PUT_BE16(wfdie + wfdielen, val16);
+	wfdielen += 2;
+
+	/*	Value2: */
+	/*	Session Management Control Port */
+	/*	Default TCP port for RTSP messages is 554 */
+	RTW_PUT_BE16(wfdie + wfdielen, pwfd_info->rtsp_ctrlport);
+	wfdielen += 2;
+
+	/*	Value3: */
+	/*	WFD Device Maximum Throughput */
+	/*	300Mbps is the maximum throughput */
+	RTW_PUT_BE16(wfdie + wfdielen, 300);
+	wfdielen += 2;
+
+	/*	Associated BSSID ATTR */
+	/*	Type: */
+	wfdie[wfdielen++] = WFD_ATTR_ASSOC_BSSID;
+
+	/*	Length: */
+	/*	Note: In the WFD specification, the size of length field is 2. */
+	RTW_PUT_BE16(wfdie + wfdielen, 0x0006);
+	wfdielen += 2;
+
+	/*	Value: */
+	/*	Associated BSSID */
+	if (check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE)
+		_rtw_memcpy(wfdie + wfdielen, &pmlmepriv->assoc_bssid[0], ETH_ALEN);
+	else
+		_rtw_memset(wfdie + wfdielen, 0x00, ETH_ALEN);
+
+	wfdielen += ETH_ALEN;
+
+	/*	Coupled Sink Information ATTR */
+	/*	Type: */
+	wfdie[wfdielen++] = WFD_ATTR_COUPLED_SINK_INFO;
+
+	/*	Length: */
+	/*	Note: In the WFD specification, the size of length field is 2. */
+	RTW_PUT_BE16(wfdie + wfdielen, 0x0007);
+	wfdielen += 2;
+
+	/*	Value: */
+	/*	Coupled Sink Status bitmap */
+	/*	Not coupled/available for Coupling */
+	wfdie[wfdielen++] = 0;
+	/* MAC Addr. */
+	wfdie[wfdielen++] = 0;
+	wfdie[wfdielen++] = 0;
+	wfdie[wfdielen++] = 0;
+	wfdie[wfdielen++] = 0;
+	wfdie[wfdielen++] = 0;
+	wfdie[wfdielen++] = 0;
+
+	rtw_set_ie(pbuf, _VENDOR_SPECIFIC_IE_, wfdielen, (unsigned char *) wfdie, &len);
+
+exit:
+	return len;
+}
+
+u32 build_nego_req_wfd_ie(struct wifidirect_info *pwdinfo, u8 *pbuf)
+{
+	u8 wfdie[MAX_WFD_IE_LEN] = { 0x00 };
+	u32 len = 0, wfdielen = 0;
+	u16 val16 = 0;
+	_adapter *padapter = pwdinfo->padapter;
+	struct mlme_priv		*pmlmepriv = &padapter->mlmepriv;
+	struct wifi_display_info	*pwfd_info = padapter->wdinfo.wfd_info;
+
+	if (!hal_chk_wl_func(padapter, WL_FUNC_MIRACAST))
+		goto exit;
+
+	/*	WFD OUI */
+	wfdielen = 0;
+	wfdie[wfdielen++] = 0x50;
+	wfdie[wfdielen++] = 0x6F;
+	wfdie[wfdielen++] = 0x9A;
+	wfdie[wfdielen++] = 0x0A;	/*	WFA WFD v1.0 */
+
+	/*	Commented by Albert 20110825 */
+	/*	According to the WFD Specification, the negotiation request frame should contain 3 WFD attributes */
+	/*	1. WFD Device Information */
+	/*	2. Associated BSSID ( Optional ) */
+	/*	3. Local IP Adress ( Optional ) */
+
+
+	/*	WFD Device Information ATTR */
+	/*	Type: */
+	wfdie[wfdielen++] = WFD_ATTR_DEVICE_INFO;
+
+	/*	Length: */
+	/*	Note: In the WFD specification, the size of length field is 2. */
+	RTW_PUT_BE16(wfdie + wfdielen, 0x0006);
+	wfdielen += 2;
+
+	/*	Value1: */
+	/*	WFD device information */
+	/*	WFD primary sink + WiFi Direct mode + WSD ( WFD Service Discovery ) + WFD Session Available */
+	val16 = pwfd_info->wfd_device_type | WFD_DEVINFO_WSD | WFD_DEVINFO_SESSION_AVAIL;
+	RTW_PUT_BE16(wfdie + wfdielen, val16);
+	wfdielen += 2;
+
+	/*	Value2: */
+	/*	Session Management Control Port */
+	/*	Default TCP port for RTSP messages is 554 */
+	RTW_PUT_BE16(wfdie + wfdielen, pwfd_info->rtsp_ctrlport);
+	wfdielen += 2;
+
+	/*	Value3: */
+	/*	WFD Device Maximum Throughput */
+	/*	300Mbps is the maximum throughput */
+	RTW_PUT_BE16(wfdie + wfdielen, 300);
+	wfdielen += 2;
+
+	/*	Associated BSSID ATTR */
+	/*	Type: */
+	wfdie[wfdielen++] = WFD_ATTR_ASSOC_BSSID;
+
+	/*	Length: */
+	/*	Note: In the WFD specification, the size of length field is 2. */
+	RTW_PUT_BE16(wfdie + wfdielen, 0x0006);
+	wfdielen += 2;
+
+	/*	Value: */
+	/*	Associated BSSID */
+	if (check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE)
+		_rtw_memcpy(wfdie + wfdielen, &pmlmepriv->assoc_bssid[0], ETH_ALEN);
+	else
+		_rtw_memset(wfdie + wfdielen, 0x00, ETH_ALEN);
+
+	wfdielen += ETH_ALEN;
+
+	/*	Coupled Sink Information ATTR */
+	/*	Type: */
+	wfdie[wfdielen++] = WFD_ATTR_COUPLED_SINK_INFO;
+
+	/*	Length: */
+	/*	Note: In the WFD specification, the size of length field is 2. */
+	RTW_PUT_BE16(wfdie + wfdielen, 0x0007);
+	wfdielen += 2;
+
+	/*	Value: */
+	/*	Coupled Sink Status bitmap */
+	/*	Not coupled/available for Coupling */
+	wfdie[wfdielen++] = 0;
+	/* MAC Addr. */
+	wfdie[wfdielen++] = 0;
+	wfdie[wfdielen++] = 0;
+	wfdie[wfdielen++] = 0;
+	wfdie[wfdielen++] = 0;
+	wfdie[wfdielen++] = 0;
+	wfdie[wfdielen++] = 0;
+
+	rtw_set_ie(pbuf, _VENDOR_SPECIFIC_IE_, wfdielen, (unsigned char *) wfdie, &len);
+
+exit:
+	return len;
+}
+
+u32 build_nego_resp_wfd_ie(struct wifidirect_info *pwdinfo, u8 *pbuf)
+{
+	u8 wfdie[MAX_WFD_IE_LEN] = { 0x00 };
+	u32 len = 0, wfdielen = 0;
+	u16 val16 = 0;
+	_adapter *padapter = pwdinfo->padapter;
+	struct mlme_priv		*pmlmepriv = &padapter->mlmepriv;
+	struct wifi_display_info	*pwfd_info = padapter->wdinfo.wfd_info;
+
+	if (!hal_chk_wl_func(padapter, WL_FUNC_MIRACAST))
+		goto exit;
+
+	/*	WFD OUI */
+	wfdielen = 0;
+	wfdie[wfdielen++] = 0x50;
+	wfdie[wfdielen++] = 0x6F;
+	wfdie[wfdielen++] = 0x9A;
+	wfdie[wfdielen++] = 0x0A;	/*	WFA WFD v1.0 */
+
+	/*	Commented by Albert 20110825 */
+	/*	According to the WFD Specification, the negotiation request frame should contain 3 WFD attributes */
+	/*	1. WFD Device Information */
+	/*	2. Associated BSSID ( Optional ) */
+	/*	3. Local IP Adress ( Optional ) */
+
+
+	/*	WFD Device Information ATTR */
+	/*	Type: */
+	wfdie[wfdielen++] = WFD_ATTR_DEVICE_INFO;
+
+	/*	Length: */
+	/*	Note: In the WFD specification, the size of length field is 2. */
+	RTW_PUT_BE16(wfdie + wfdielen, 0x0006);
+	wfdielen += 2;
+
+	/*	Value1: */
+	/*	WFD device information */
+	/*	WFD primary sink + WiFi Direct mode + WSD ( WFD Service Discovery ) + WFD Session Available */
+	val16 = pwfd_info->wfd_device_type | WFD_DEVINFO_WSD | WFD_DEVINFO_SESSION_AVAIL;
+	RTW_PUT_BE16(wfdie + wfdielen, val16);
+	wfdielen += 2;
+
+	/*	Value2: */
+	/*	Session Management Control Port */
+	/*	Default TCP port for RTSP messages is 554 */
+	RTW_PUT_BE16(wfdie + wfdielen, pwfd_info->rtsp_ctrlport);
+	wfdielen += 2;
+
+	/*	Value3: */
+	/*	WFD Device Maximum Throughput */
+	/*	300Mbps is the maximum throughput */
+	RTW_PUT_BE16(wfdie + wfdielen, 300);
+	wfdielen += 2;
+
+	/*	Associated BSSID ATTR */
+	/*	Type: */
+	wfdie[wfdielen++] = WFD_ATTR_ASSOC_BSSID;
+
+	/*	Length: */
+	/*	Note: In the WFD specification, the size of length field is 2. */
+	RTW_PUT_BE16(wfdie + wfdielen, 0x0006);
+	wfdielen += 2;
+
+	/*	Value: */
+	/*	Associated BSSID */
+	if (check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE)
+		_rtw_memcpy(wfdie + wfdielen, &pmlmepriv->assoc_bssid[0], ETH_ALEN);
+	else
+		_rtw_memset(wfdie + wfdielen, 0x00, ETH_ALEN);
+
+	wfdielen += ETH_ALEN;
+
+	/*	Coupled Sink Information ATTR */
+	/*	Type: */
+	wfdie[wfdielen++] = WFD_ATTR_COUPLED_SINK_INFO;
+
+	/*	Length: */
+	/*	Note: In the WFD specification, the size of length field is 2. */
+	RTW_PUT_BE16(wfdie + wfdielen, 0x0007);
+	wfdielen += 2;
+
+	/*	Value: */
+	/*	Coupled Sink Status bitmap */
+	/*	Not coupled/available for Coupling */
+	wfdie[wfdielen++] = 0;
+	/* MAC Addr. */
+	wfdie[wfdielen++] = 0;
+	wfdie[wfdielen++] = 0;
+	wfdie[wfdielen++] = 0;
+	wfdie[wfdielen++] = 0;
+	wfdie[wfdielen++] = 0;
+	wfdie[wfdielen++] = 0;
+
+
+	rtw_set_ie(pbuf, _VENDOR_SPECIFIC_IE_, wfdielen, (unsigned char *) wfdie, &len);
+
+exit:
+	return len;
+}
+
+u32 build_nego_confirm_wfd_ie(struct wifidirect_info *pwdinfo, u8 *pbuf)
+{
+	u8 wfdie[MAX_WFD_IE_LEN] = { 0x00 };
+	u32 len = 0, wfdielen = 0;
+	u16 val16 = 0;
+	_adapter *padapter = pwdinfo->padapter;
+	struct mlme_priv		*pmlmepriv = &padapter->mlmepriv;
+	struct wifi_display_info	*pwfd_info = padapter->wdinfo.wfd_info;
+
+	if (!hal_chk_wl_func(padapter, WL_FUNC_MIRACAST))
+		goto exit;
+
+	/*	WFD OUI */
+	wfdielen = 0;
+	wfdie[wfdielen++] = 0x50;
+	wfdie[wfdielen++] = 0x6F;
+	wfdie[wfdielen++] = 0x9A;
+	wfdie[wfdielen++] = 0x0A;	/*	WFA WFD v1.0 */
+
+	/*	Commented by Albert 20110825 */
+	/*	According to the WFD Specification, the negotiation request frame should contain 3 WFD attributes */
+	/*	1. WFD Device Information */
+	/*	2. Associated BSSID ( Optional ) */
+	/*	3. Local IP Adress ( Optional ) */
+
+
+	/*	WFD Device Information ATTR */
+	/*	Type: */
+	wfdie[wfdielen++] = WFD_ATTR_DEVICE_INFO;
+
+	/*	Length: */
+	/*	Note: In the WFD specification, the size of length field is 2. */
+	RTW_PUT_BE16(wfdie + wfdielen, 0x0006);
+	wfdielen += 2;
+
+	/*	Value1: */
+	/*	WFD device information */
+	/*	WFD primary sink + WiFi Direct mode + WSD ( WFD Service Discovery ) + WFD Session Available */
+	val16 = pwfd_info->wfd_device_type | WFD_DEVINFO_WSD | WFD_DEVINFO_SESSION_AVAIL;
+	RTW_PUT_BE16(wfdie + wfdielen, val16);
+	wfdielen += 2;
+
+	/*	Value2: */
+	/*	Session Management Control Port */
+	/*	Default TCP port for RTSP messages is 554 */
+	RTW_PUT_BE16(wfdie + wfdielen, pwfd_info->rtsp_ctrlport);
+	wfdielen += 2;
+
+	/*	Value3: */
+	/*	WFD Device Maximum Throughput */
+	/*	300Mbps is the maximum throughput */
+	RTW_PUT_BE16(wfdie + wfdielen, 300);
+	wfdielen += 2;
+
+	/*	Associated BSSID ATTR */
+	/*	Type: */
+	wfdie[wfdielen++] = WFD_ATTR_ASSOC_BSSID;
+
+	/*	Length: */
+	/*	Note: In the WFD specification, the size of length field is 2. */
+	RTW_PUT_BE16(wfdie + wfdielen, 0x0006);
+	wfdielen += 2;
+
+	/*	Value: */
+	/*	Associated BSSID */
+	if (check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE)
+		_rtw_memcpy(wfdie + wfdielen, &pmlmepriv->assoc_bssid[0], ETH_ALEN);
+	else
+		_rtw_memset(wfdie + wfdielen, 0x00, ETH_ALEN);
+
+	wfdielen += ETH_ALEN;
+
+	/*	Coupled Sink Information ATTR */
+	/*	Type: */
+	wfdie[wfdielen++] = WFD_ATTR_COUPLED_SINK_INFO;
+
+	/*	Length: */
+	/*	Note: In the WFD specification, the size of length field is 2. */
+	RTW_PUT_BE16(wfdie + wfdielen, 0x0007);
+	wfdielen += 2;
+
+	/*	Value: */
+	/*	Coupled Sink Status bitmap */
+	/*	Not coupled/available for Coupling */
+	wfdie[wfdielen++] = 0;
+	/* MAC Addr. */
+	wfdie[wfdielen++] = 0;
+	wfdie[wfdielen++] = 0;
+	wfdie[wfdielen++] = 0;
+	wfdie[wfdielen++] = 0;
+	wfdie[wfdielen++] = 0;
+	wfdie[wfdielen++] = 0;
+
+
+	pbuf = rtw_set_ie(pbuf, _VENDOR_SPECIFIC_IE_, wfdielen, (unsigned char *) wfdie, &len);
+
+exit:
+	return len;
+}
+
+u32 build_invitation_req_wfd_ie(struct wifidirect_info *pwdinfo, u8 *pbuf)
+{
+	u8 wfdie[MAX_WFD_IE_LEN] = { 0x00 };
+	u32 len = 0, wfdielen = 0;
+	u16 val16 = 0;
+	_adapter *padapter = pwdinfo->padapter;
+	struct mlme_priv		*pmlmepriv = &padapter->mlmepriv;
+	struct wifi_display_info	*pwfd_info = padapter->wdinfo.wfd_info;
+
+	if (!hal_chk_wl_func(padapter, WL_FUNC_MIRACAST))
+		goto exit;
+
+	/*	WFD OUI */
+	wfdielen = 0;
+	wfdie[wfdielen++] = 0x50;
+	wfdie[wfdielen++] = 0x6F;
+	wfdie[wfdielen++] = 0x9A;
+	wfdie[wfdielen++] = 0x0A;	/*	WFA WFD v1.0 */
+
+	/*	Commented by Albert 20110825 */
+	/*	According to the WFD Specification, the provision discovery request frame should contain 3 WFD attributes */
+	/*	1. WFD Device Information */
+	/*	2. Associated BSSID ( Optional ) */
+	/*	3. Local IP Adress ( Optional ) */
+
+
+	/*	WFD Device Information ATTR */
+	/*	Type: */
+	wfdie[wfdielen++] = WFD_ATTR_DEVICE_INFO;
+
+	/*	Length: */
+	/*	Note: In the WFD specification, the size of length field is 2. */
+	RTW_PUT_BE16(wfdie + wfdielen, 0x0006);
+	wfdielen += 2;
+
+	/*	Value1: */
+	/*	WFD device information */
+	/*	WFD primary sink + available for WFD session + WiFi Direct mode + WSD ( WFD Service Discovery ) */
+	val16 = pwfd_info->wfd_device_type | WFD_DEVINFO_SESSION_AVAIL | WFD_DEVINFO_WSD;
+	RTW_PUT_BE16(wfdie + wfdielen, val16);
+	wfdielen += 2;
+
+	/*	Value2: */
+	/*	Session Management Control Port */
+	/*	Default TCP port for RTSP messages is 554 */
+	RTW_PUT_BE16(wfdie + wfdielen, pwfd_info->rtsp_ctrlport);
+	wfdielen += 2;
+
+	/*	Value3: */
+	/*	WFD Device Maximum Throughput */
+	/*	300Mbps is the maximum throughput */
+	RTW_PUT_BE16(wfdie + wfdielen, 300);
+	wfdielen += 2;
+
+	/*	Associated BSSID ATTR */
+	/*	Type: */
+	wfdie[wfdielen++] = WFD_ATTR_ASSOC_BSSID;
+
+	/*	Length: */
+	/*	Note: In the WFD specification, the size of length field is 2. */
+	RTW_PUT_BE16(wfdie + wfdielen, 0x0006);
+	wfdielen += 2;
+
+	/*	Value: */
+	/*	Associated BSSID */
+	if (check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE)
+		_rtw_memcpy(wfdie + wfdielen, &pmlmepriv->assoc_bssid[0], ETH_ALEN);
+	else
+		_rtw_memset(wfdie + wfdielen, 0x00, ETH_ALEN);
+
+	wfdielen += ETH_ALEN;
+
+	/*	Coupled Sink Information ATTR */
+	/*	Type: */
+	wfdie[wfdielen++] = WFD_ATTR_COUPLED_SINK_INFO;
+
+	/*	Length: */
+	/*	Note: In the WFD specification, the size of length field is 2. */
+	RTW_PUT_BE16(wfdie + wfdielen, 0x0007);
+	wfdielen += 2;
+
+	/*	Value: */
+	/*	Coupled Sink Status bitmap */
+	/*	Not coupled/available for Coupling */
+	wfdie[wfdielen++] = 0;
+	/* MAC Addr. */
+	wfdie[wfdielen++] = 0;
+	wfdie[wfdielen++] = 0;
+	wfdie[wfdielen++] = 0;
+	wfdie[wfdielen++] = 0;
+	wfdie[wfdielen++] = 0;
+	wfdie[wfdielen++] = 0;
+
+	if (P2P_ROLE_GO == pwdinfo->role) {
+		/*	WFD Session Information ATTR */
+		/*	Type: */
+		wfdie[wfdielen++] = WFD_ATTR_SESSION_INFO;
+
+		/*	Length: */
+		/*	Note: In the WFD specification, the size of length field is 2. */
+		RTW_PUT_BE16(wfdie + wfdielen, 0x0000);
+		wfdielen += 2;
+
+		/*	Todo: to add the list of WFD device info descriptor in WFD group. */
+
+	}
+
+	rtw_set_ie(pbuf, _VENDOR_SPECIFIC_IE_, wfdielen, (unsigned char *) wfdie, &len);
+
+exit:
+	return len;
+}
+
+u32 build_invitation_resp_wfd_ie(struct wifidirect_info *pwdinfo, u8 *pbuf)
+{
+	u8 wfdie[MAX_WFD_IE_LEN] = { 0x00 };
+	u16 val16 = 0;
+	u32 len = 0, wfdielen = 0;
+	_adapter *padapter = pwdinfo->padapter;
+	struct mlme_priv		*pmlmepriv = &padapter->mlmepriv;
+	struct wifi_display_info	*pwfd_info = padapter->wdinfo.wfd_info;
+
+	if (!hal_chk_wl_func(padapter, WL_FUNC_MIRACAST))
+		goto exit;
+
+	/*	WFD OUI */
+	wfdielen = 0;
+	wfdie[wfdielen++] = 0x50;
+	wfdie[wfdielen++] = 0x6F;
+	wfdie[wfdielen++] = 0x9A;
+	wfdie[wfdielen++] = 0x0A;	/*	WFA WFD v1.0 */
+
+	/*	Commented by Albert 20110825 */
+	/*	According to the WFD Specification, the provision discovery request frame should contain 3 WFD attributes */
+	/*	1. WFD Device Information */
+	/*	2. Associated BSSID ( Optional ) */
+	/*	3. Local IP Adress ( Optional ) */
+
+
+	/*	WFD Device Information ATTR */
+	/*	Type: */
+	wfdie[wfdielen++] = WFD_ATTR_DEVICE_INFO;
+
+	/*	Length: */
+	/*	Note: In the WFD specification, the size of length field is 2. */
+	RTW_PUT_BE16(wfdie + wfdielen, 0x0006);
+	wfdielen += 2;
+
+	/*	Value1: */
+	/*	WFD device information */
+	/*	WFD primary sink + available for WFD session + WiFi Direct mode + WSD ( WFD Service Discovery ) */
+	val16 = pwfd_info->wfd_device_type | WFD_DEVINFO_SESSION_AVAIL | WFD_DEVINFO_WSD;
+	RTW_PUT_BE16(wfdie + wfdielen, val16);
+	wfdielen += 2;
+
+	/*	Value2: */
+	/*	Session Management Control Port */
+	/*	Default TCP port for RTSP messages is 554 */
+	RTW_PUT_BE16(wfdie + wfdielen, pwfd_info->rtsp_ctrlport);
+	wfdielen += 2;
+
+	/*	Value3: */
+	/*	WFD Device Maximum Throughput */
+	/*	300Mbps is the maximum throughput */
+	RTW_PUT_BE16(wfdie + wfdielen, 300);
+	wfdielen += 2;
+
+	/*	Associated BSSID ATTR */
+	/*	Type: */
+	wfdie[wfdielen++] = WFD_ATTR_ASSOC_BSSID;
+
+	/*	Length: */
+	/*	Note: In the WFD specification, the size of length field is 2. */
+	RTW_PUT_BE16(wfdie + wfdielen, 0x0006);
+	wfdielen += 2;
+
+	/*	Value: */
+	/*	Associated BSSID */
+	if (check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE)
+		_rtw_memcpy(wfdie + wfdielen, &pmlmepriv->assoc_bssid[0], ETH_ALEN);
+	else
+		_rtw_memset(wfdie + wfdielen, 0x00, ETH_ALEN);
+
+	wfdielen += ETH_ALEN;
+
+	/*	Coupled Sink Information ATTR */
+	/*	Type: */
+	wfdie[wfdielen++] = WFD_ATTR_COUPLED_SINK_INFO;
+
+	/*	Length: */
+	/*	Note: In the WFD specification, the size of length field is 2. */
+	RTW_PUT_BE16(wfdie + wfdielen, 0x0007);
+	wfdielen += 2;
+
+	/*	Value: */
+	/*	Coupled Sink Status bitmap */
+	/*	Not coupled/available for Coupling */
+	wfdie[wfdielen++] = 0;
+	/* MAC Addr. */
+	wfdie[wfdielen++] = 0;
+	wfdie[wfdielen++] = 0;
+	wfdie[wfdielen++] = 0;
+	wfdie[wfdielen++] = 0;
+	wfdie[wfdielen++] = 0;
+	wfdie[wfdielen++] = 0;
+
+	if (P2P_ROLE_GO == pwdinfo->role) {
+		/*	WFD Session Information ATTR */
+		/*	Type: */
+		wfdie[wfdielen++] = WFD_ATTR_SESSION_INFO;
+
+		/*	Length: */
+		/*	Note: In the WFD specification, the size of length field is 2. */
+		RTW_PUT_BE16(wfdie + wfdielen, 0x0000);
+		wfdielen += 2;
+
+		/*	Todo: to add the list of WFD device info descriptor in WFD group. */
+
+	}
+
+	rtw_set_ie(pbuf, _VENDOR_SPECIFIC_IE_, wfdielen, (unsigned char *) wfdie, &len);
+
+exit:
+	return len;
+}
+
+u32 build_provdisc_req_wfd_ie(struct wifidirect_info *pwdinfo, u8 *pbuf)
+{
+	u8 wfdie[MAX_WFD_IE_LEN] = { 0x00 };
+	u32 len = 0, wfdielen = 0;
+	u16 val16 = 0;
+	_adapter *padapter = pwdinfo->padapter;
+	struct mlme_priv		*pmlmepriv = &padapter->mlmepriv;
+	struct wifi_display_info	*pwfd_info = padapter->wdinfo.wfd_info;
+
+	if (!hal_chk_wl_func(padapter, WL_FUNC_MIRACAST))
+		goto exit;
+
+	/*	WFD OUI */
+	wfdielen = 0;
+	wfdie[wfdielen++] = 0x50;
+	wfdie[wfdielen++] = 0x6F;
+	wfdie[wfdielen++] = 0x9A;
+	wfdie[wfdielen++] = 0x0A;	/*	WFA WFD v1.0 */
+
+	/*	Commented by Albert 20110825 */
+	/*	According to the WFD Specification, the provision discovery request frame should contain 3 WFD attributes */
+	/*	1. WFD Device Information */
+	/*	2. Associated BSSID ( Optional ) */
+	/*	3. Local IP Adress ( Optional ) */
+
+
+	/*	WFD Device Information ATTR */
+	/*	Type: */
+	wfdie[wfdielen++] = WFD_ATTR_DEVICE_INFO;
+
+	/*	Length: */
+	/*	Note: In the WFD specification, the size of length field is 2. */
+	RTW_PUT_BE16(wfdie + wfdielen, 0x0006);
+	wfdielen += 2;
+
+	/*	Value1: */
+	/*	WFD device information */
+	/*	WFD primary sink + available for WFD session + WiFi Direct mode + WSD ( WFD Service Discovery ) */
+	val16 = pwfd_info->wfd_device_type | WFD_DEVINFO_SESSION_AVAIL | WFD_DEVINFO_WSD;
+	RTW_PUT_BE16(wfdie + wfdielen, val16);
+	wfdielen += 2;
+
+	/*	Value2: */
+	/*	Session Management Control Port */
+	/*	Default TCP port for RTSP messages is 554 */
+	RTW_PUT_BE16(wfdie + wfdielen, pwfd_info->rtsp_ctrlport);
+	wfdielen += 2;
+
+	/*	Value3: */
+	/*	WFD Device Maximum Throughput */
+	/*	300Mbps is the maximum throughput */
+	RTW_PUT_BE16(wfdie + wfdielen, 300);
+	wfdielen += 2;
+
+	/*	Associated BSSID ATTR */
+	/*	Type: */
+	wfdie[wfdielen++] = WFD_ATTR_ASSOC_BSSID;
+
+	/*	Length: */
+	/*	Note: In the WFD specification, the size of length field is 2. */
+	RTW_PUT_BE16(wfdie + wfdielen, 0x0006);
+	wfdielen += 2;
+
+	/*	Value: */
+	/*	Associated BSSID */
+	if (check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE)
+		_rtw_memcpy(wfdie + wfdielen, &pmlmepriv->assoc_bssid[0], ETH_ALEN);
+	else
+		_rtw_memset(wfdie + wfdielen, 0x00, ETH_ALEN);
+
+	wfdielen += ETH_ALEN;
+
+	/*	Coupled Sink Information ATTR */
+	/*	Type: */
+	wfdie[wfdielen++] = WFD_ATTR_COUPLED_SINK_INFO;
+
+	/*	Length: */
+	/*	Note: In the WFD specification, the size of length field is 2. */
+	RTW_PUT_BE16(wfdie + wfdielen, 0x0007);
+	wfdielen += 2;
+
+	/*	Value: */
+	/*	Coupled Sink Status bitmap */
+	/*	Not coupled/available for Coupling */
+	wfdie[wfdielen++] = 0;
+	/* MAC Addr. */
+	wfdie[wfdielen++] = 0;
+	wfdie[wfdielen++] = 0;
+	wfdie[wfdielen++] = 0;
+	wfdie[wfdielen++] = 0;
+	wfdie[wfdielen++] = 0;
+	wfdie[wfdielen++] = 0;
+
+
+	rtw_set_ie(pbuf, _VENDOR_SPECIFIC_IE_, wfdielen, (unsigned char *) wfdie, &len);
+
+exit:
+	return len;
+}
+
+u32 build_provdisc_resp_wfd_ie(struct wifidirect_info *pwdinfo, u8 *pbuf)
+{
+	u8 wfdie[MAX_WFD_IE_LEN] = { 0x00 };
+	u32 len = 0, wfdielen = 0;
+	u16 val16 = 0;
+	_adapter *padapter = pwdinfo->padapter;
+	struct mlme_priv		*pmlmepriv = &padapter->mlmepriv;
+	struct wifi_display_info	*pwfd_info = padapter->wdinfo.wfd_info;
+
+	if (!hal_chk_wl_func(padapter, WL_FUNC_MIRACAST))
+		goto exit;
+
+	/*	WFD OUI */
+	wfdielen = 0;
+	wfdie[wfdielen++] = 0x50;
+	wfdie[wfdielen++] = 0x6F;
+	wfdie[wfdielen++] = 0x9A;
+	wfdie[wfdielen++] = 0x0A;	/*	WFA WFD v1.0 */
+
+	/*	Commented by Albert 20110825 */
+	/*	According to the WFD Specification, the provision discovery response frame should contain 3 WFD attributes */
+	/*	1. WFD Device Information */
+	/*	2. Associated BSSID ( Optional ) */
+	/*	3. Local IP Adress ( Optional ) */
+
+
+	/*	WFD Device Information ATTR */
+	/*	Type: */
+	wfdie[wfdielen++] = WFD_ATTR_DEVICE_INFO;
+
+	/*	Length: */
+	/*	Note: In the WFD specification, the size of length field is 2. */
+	RTW_PUT_BE16(wfdie + wfdielen, 0x0006);
+	wfdielen += 2;
+
+	/*	Value1: */
+	/*	WFD device information */
+	/*	WFD primary sink + available for WFD session + WiFi Direct mode + WSD ( WFD Service Discovery ) */
+	val16 = pwfd_info->wfd_device_type | WFD_DEVINFO_SESSION_AVAIL | WFD_DEVINFO_WSD;
+	RTW_PUT_BE16(wfdie + wfdielen, val16);
+	wfdielen += 2;
+
+	/*	Value2: */
+	/*	Session Management Control Port */
+	/*	Default TCP port for RTSP messages is 554 */
+	RTW_PUT_BE16(wfdie + wfdielen, pwfd_info->rtsp_ctrlport);
+	wfdielen += 2;
+
+	/*	Value3: */
+	/*	WFD Device Maximum Throughput */
+	/*	300Mbps is the maximum throughput */
+	RTW_PUT_BE16(wfdie + wfdielen, 300);
+	wfdielen += 2;
+
+	/*	Associated BSSID ATTR */
+	/*	Type: */
+	wfdie[wfdielen++] = WFD_ATTR_ASSOC_BSSID;
+
+	/*	Length: */
+	/*	Note: In the WFD specification, the size of length field is 2. */
+	RTW_PUT_BE16(wfdie + wfdielen, 0x0006);
+	wfdielen += 2;
+
+	/*	Value: */
+	/*	Associated BSSID */
+	if (check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE)
+		_rtw_memcpy(wfdie + wfdielen, &pmlmepriv->assoc_bssid[0], ETH_ALEN);
+	else
+		_rtw_memset(wfdie + wfdielen, 0x00, ETH_ALEN);
+
+	wfdielen += ETH_ALEN;
+
+	/*	Coupled Sink Information ATTR */
+	/*	Type: */
+	wfdie[wfdielen++] = WFD_ATTR_COUPLED_SINK_INFO;
+
+	/*	Length: */
+	/*	Note: In the WFD specification, the size of length field is 2. */
+	RTW_PUT_BE16(wfdie + wfdielen, 0x0007);
+	wfdielen += 2;
+
+	/*	Value: */
+	/*	Coupled Sink Status bitmap */
+	/*	Not coupled/available for Coupling */
+	wfdie[wfdielen++] = 0;
+	/* MAC Addr. */
+	wfdie[wfdielen++] = 0;
+	wfdie[wfdielen++] = 0;
+	wfdie[wfdielen++] = 0;
+	wfdie[wfdielen++] = 0;
+	wfdie[wfdielen++] = 0;
+	wfdie[wfdielen++] = 0;
+
+	rtw_set_ie(pbuf, _VENDOR_SPECIFIC_IE_, wfdielen, (unsigned char *) wfdie, &len);
+
+exit:
+	return len;
+}
+#endif /* CONFIG_WFD */
+
+u32 build_probe_resp_p2p_ie(struct wifidirect_info *pwdinfo, u8 *pbuf)
+{
+	u8 p2pie[MAX_P2P_IE_LEN] = { 0x00 };
+	u32 len = 0, p2pielen = 0;
+#ifdef CONFIG_INTEL_WIDI
+	struct mlme_priv *pmlmepriv = &(pwdinfo->padapter->mlmepriv);
+	u8 zero_array_check[L2SDTA_SERVICE_VE_LEN] = { 0x00 };
+	u8 widi_version = 0, i = 0;
+
+	if (_rtw_memcmp(pmlmepriv->sa_ext, zero_array_check, L2SDTA_SERVICE_VE_LEN) == _FALSE)
+		widi_version = 35;
+	else if (pmlmepriv->num_p2p_sdt != 0)
+		widi_version = 40;
+#endif /* CONFIG_INTEL_WIDI */
+
+	/*	P2P OUI */
+	p2pielen = 0;
+	p2pie[p2pielen++] = 0x50;
+	p2pie[p2pielen++] = 0x6F;
+	p2pie[p2pielen++] = 0x9A;
+	p2pie[p2pielen++] = 0x09;	/*	WFA P2P v1.0 */
+
+	/*	Commented by Albert 20100907 */
+	/*	According to the P2P Specification, the probe response frame should contain 5 P2P attributes */
+	/*	1. P2P Capability */
+	/*	2. Extended Listen Timing */
+	/*	3. Notice of Absence ( NOA )	( Only GO needs this ) */
+	/*	4. Device Info */
+	/*	5. Group Info	( Only GO need this ) */
+
+	/*	P2P Capability ATTR */
+	/*	Type: */
+	p2pie[p2pielen++] = P2P_ATTR_CAPABILITY;
+
+	/*	Length: */
+	/* *(u16*) ( p2pie + p2pielen ) = cpu_to_le16( 0x0002 ); */
+	RTW_PUT_LE16(p2pie + p2pielen, 0x0002);
+	p2pielen += 2;
+
+	/*	Value: */
+	/*	Device Capability Bitmap, 1 byte */
+	p2pie[p2pielen++] = DMP_P2P_DEVCAP_SUPPORT;
+
+	/*	Group Capability Bitmap, 1 byte */
+	if (rtw_p2p_chk_role(pwdinfo, P2P_ROLE_GO)) {
+		p2pie[p2pielen] = (P2P_GRPCAP_GO | P2P_GRPCAP_INTRABSS);
+
+		if (rtw_p2p_chk_state(pwdinfo, P2P_STATE_PROVISIONING_ING))
+			p2pie[p2pielen] |= P2P_GRPCAP_GROUP_FORMATION;
+
+		p2pielen++;
+	} else if (rtw_p2p_chk_role(pwdinfo, P2P_ROLE_DEVICE)) {
+		/*	Group Capability Bitmap, 1 byte */
+		if (pwdinfo->persistent_supported)
+			p2pie[p2pielen++] = P2P_GRPCAP_PERSISTENT_GROUP | DMP_P2P_GRPCAP_SUPPORT;
+		else
+			p2pie[p2pielen++] = DMP_P2P_GRPCAP_SUPPORT;
+	}
+
+	/*	Extended Listen Timing ATTR */
+	/*	Type: */
+	p2pie[p2pielen++] = P2P_ATTR_EX_LISTEN_TIMING;
+
+	/*	Length: */
+	/* *(u16*) ( p2pie + p2pielen ) = cpu_to_le16( 0x0004 ); */
+	RTW_PUT_LE16(p2pie + p2pielen, 0x0004);
+	p2pielen += 2;
+
+	/*	Value: */
+	/*	Availability Period */
+	/* *(u16*) ( p2pie + p2pielen ) = cpu_to_le16( 0xFFFF ); */
+	RTW_PUT_LE16(p2pie + p2pielen, 0xFFFF);
+	p2pielen += 2;
+
+	/*	Availability Interval */
+	/* *(u16*) ( p2pie + p2pielen ) = cpu_to_le16( 0xFFFF ); */
+	RTW_PUT_LE16(p2pie + p2pielen, 0xFFFF);
+	p2pielen += 2;
+
+
+	/* Notice of Absence ATTR */
+	/*	Type:  */
+	/*	Length: */
+	/*	Value: */
+	if (rtw_p2p_chk_role(pwdinfo, P2P_ROLE_GO)) {
+		/* go_add_noa_attr(pwdinfo); */
+	}
+
+	/*	Device Info ATTR */
+	/*	Type: */
+	p2pie[p2pielen++] = P2P_ATTR_DEVICE_INFO;
+
+	/*	Length: */
+	/*	21->P2P Device Address (6bytes) + Config Methods (2bytes) + Primary Device Type (8bytes)  */
+	/*	+ NumofSecondDevType (1byte) + WPS Device Name ID field (2bytes) + WPS Device Name Len field (2bytes) */
+	/* *(u16*) ( p2pie + p2pielen ) = cpu_to_le16( 21 + pwdinfo->device_name_len ); */
+#ifdef CONFIG_INTEL_WIDI
+	if (widi_version == 35)
+		RTW_PUT_LE16(p2pie + p2pielen, 21 + 8 + pwdinfo->device_name_len);
+	else if (widi_version == 40)
+		RTW_PUT_LE16(p2pie + p2pielen, 21 + 8 * pmlmepriv->num_p2p_sdt + pwdinfo->device_name_len);
+	else
+#endif /* CONFIG_INTEL_WIDI */
+		RTW_PUT_LE16(p2pie + p2pielen, 21 + pwdinfo->device_name_len);
+	p2pielen += 2;
+
+	/*	Value: */
+	/*	P2P Device Address */
+	_rtw_memcpy(p2pie + p2pielen, pwdinfo->device_addr, ETH_ALEN);
+	p2pielen += ETH_ALEN;
+
+	/*	Config Method */
+	/*	This field should be big endian. Noted by P2P specification. */
+	/* *(u16*) ( p2pie + p2pielen ) = cpu_to_be16( pwdinfo->supported_wps_cm ); */
+	RTW_PUT_BE16(p2pie + p2pielen, pwdinfo->supported_wps_cm);
+	p2pielen += 2;
+
+#ifdef CONFIG_INTEL_WIDI
+	if (widi_version == 40) {
+		/*	Primary Device Type */
+		/*	Category ID */
+		/* *(u16*) ( p2pie + p2pielen ) = cpu_to_be16( WPS_PDT_CID_MULIT_MEDIA ); */
+		RTW_PUT_BE16(p2pie + p2pielen, pmlmepriv->p2p_pdt_cid);
+		p2pielen += 2;
+
+		/*	OUI */
+		/* *(u32*) ( p2pie + p2pielen ) = cpu_to_be32( WPSOUI ); */
+		RTW_PUT_BE32(p2pie + p2pielen, WPSOUI);
+		p2pielen += 4;
+
+		/*	Sub Category ID */
+		/* *(u16*) ( p2pie + p2pielen ) = cpu_to_be16( WPS_PDT_SCID_MEDIA_SERVER ); */
+		RTW_PUT_BE16(p2pie + p2pielen, pmlmepriv->p2p_pdt_scid);
+		p2pielen += 2;
+	} else
+#endif /* CONFIG_INTEL_WIDI */
+	{
+		/*	Primary Device Type */
+		/*	Category ID */
+		/* *(u16*) ( p2pie + p2pielen ) = cpu_to_be16( WPS_PDT_CID_MULIT_MEDIA ); */
+		RTW_PUT_BE16(p2pie + p2pielen, WPS_PDT_CID_MULIT_MEDIA);
+		p2pielen += 2;
+
+		/*	OUI */
+		/* *(u32*) ( p2pie + p2pielen ) = cpu_to_be32( WPSOUI ); */
+		RTW_PUT_BE32(p2pie + p2pielen, WPSOUI);
+		p2pielen += 4;
+
+		/*	Sub Category ID */
+		/* *(u16*) ( p2pie + p2pielen ) = cpu_to_be16( WPS_PDT_SCID_MEDIA_SERVER ); */
+		RTW_PUT_BE16(p2pie + p2pielen, WPS_PDT_SCID_MEDIA_SERVER);
+		p2pielen += 2;
+	}
+
+	/*	Number of Secondary Device Types */
+#ifdef CONFIG_INTEL_WIDI
+	if (widi_version == 35) {
+		p2pie[p2pielen++] = 0x01;
+
+		RTW_PUT_BE16(p2pie + p2pielen, WPS_PDT_CID_DISPLAYS);
+		p2pielen += 2;
+
+		RTW_PUT_BE32(p2pie + p2pielen, INTEL_DEV_TYPE_OUI);
+		p2pielen += 4;
+
+		RTW_PUT_BE16(p2pie + p2pielen, P2P_SCID_WIDI_CONSUMER_SINK);
+		p2pielen += 2;
+	} else if (widi_version == 40) {
+		p2pie[p2pielen++] = pmlmepriv->num_p2p_sdt;
+		for (; i < pmlmepriv->num_p2p_sdt; i++) {
+			RTW_PUT_BE16(p2pie + p2pielen, pmlmepriv->p2p_sdt_cid[i]);
+			p2pielen += 2;
+
+			RTW_PUT_BE32(p2pie + p2pielen, INTEL_DEV_TYPE_OUI);
+			p2pielen += 4;
+
+			RTW_PUT_BE16(p2pie + p2pielen, pmlmepriv->p2p_sdt_scid[i]);
+			p2pielen += 2;
+		}
+	} else
+#endif /* CONFIG_INTEL_WIDI */
+		p2pie[p2pielen++] = 0x00;	/*	No Secondary Device Type List */
+
+	/*	Device Name */
+	/*	Type: */
+	/* *(u16*) ( p2pie + p2pielen ) = cpu_to_be16( WPS_ATTR_DEVICE_NAME ); */
+	RTW_PUT_BE16(p2pie + p2pielen, WPS_ATTR_DEVICE_NAME);
+	p2pielen += 2;
+
+	/*	Length: */
+	/* *(u16*) ( p2pie + p2pielen ) = cpu_to_be16( pwdinfo->device_name_len ); */
+	RTW_PUT_BE16(p2pie + p2pielen, pwdinfo->device_name_len);
+	p2pielen += 2;
+
+	/*	Value: */
+	_rtw_memcpy(p2pie + p2pielen, pwdinfo->device_name, pwdinfo->device_name_len);
+	p2pielen += pwdinfo->device_name_len;
+
+	/* Group Info ATTR */
+	/*	Type: */
+	/*	Length: */
+	/*	Value: */
+	if (rtw_p2p_chk_role(pwdinfo, P2P_ROLE_GO))
+		p2pielen += go_add_group_info_attr(pwdinfo, p2pie + p2pielen);
+
+
+	pbuf = rtw_set_ie(pbuf, _VENDOR_SPECIFIC_IE_, p2pielen, (unsigned char *) p2pie, &len);
+
+
+	return len;
+
+}
+
+u32 build_prov_disc_request_p2p_ie(struct wifidirect_info *pwdinfo, u8 *pbuf, u8 *pssid, u8 ussidlen, u8 *pdev_raddr)
+{
+	u8 p2pie[MAX_P2P_IE_LEN] = { 0x00 };
+	u32 len = 0, p2pielen = 0;
+
+	/*	P2P OUI */
+	p2pielen = 0;
+	p2pie[p2pielen++] = 0x50;
+	p2pie[p2pielen++] = 0x6F;
+	p2pie[p2pielen++] = 0x9A;
+	p2pie[p2pielen++] = 0x09;	/*	WFA P2P v1.0 */
+
+	/*	Commented by Albert 20110301 */
+	/*	According to the P2P Specification, the provision discovery request frame should contain 3 P2P attributes */
+	/*	1. P2P Capability */
+	/*	2. Device Info */
+	/*	3. Group ID ( When joining an operating P2P Group ) */
+
+	/*	P2P Capability ATTR */
+	/*	Type: */
+	p2pie[p2pielen++] = P2P_ATTR_CAPABILITY;
+
+	/*	Length: */
+	/* *(u16*) ( p2pie + p2pielen ) = cpu_to_le16( 0x0002 ); */
+	RTW_PUT_LE16(p2pie + p2pielen, 0x0002);
+	p2pielen += 2;
+
+	/*	Value: */
+	/*	Device Capability Bitmap, 1 byte */
+	p2pie[p2pielen++] = DMP_P2P_DEVCAP_SUPPORT;
+
+	/*	Group Capability Bitmap, 1 byte */
+	if (pwdinfo->persistent_supported)
+		p2pie[p2pielen++] = P2P_GRPCAP_PERSISTENT_GROUP | DMP_P2P_GRPCAP_SUPPORT;
+	else
+		p2pie[p2pielen++] = DMP_P2P_GRPCAP_SUPPORT;
+
+
+	/*	Device Info ATTR */
+	/*	Type: */
+	p2pie[p2pielen++] = P2P_ATTR_DEVICE_INFO;
+
+	/*	Length: */
+	/*	21->P2P Device Address (6bytes) + Config Methods (2bytes) + Primary Device Type (8bytes)  */
+	/*	+ NumofSecondDevType (1byte) + WPS Device Name ID field (2bytes) + WPS Device Name Len field (2bytes) */
+	/* *(u16*) ( p2pie + p2pielen ) = cpu_to_le16( 21 + pwdinfo->device_name_len ); */
+	RTW_PUT_LE16(p2pie + p2pielen, 21 + pwdinfo->device_name_len);
+	p2pielen += 2;
+
+	/*	Value: */
+	/*	P2P Device Address */
+	_rtw_memcpy(p2pie + p2pielen, pwdinfo->device_addr, ETH_ALEN);
+	p2pielen += ETH_ALEN;
+
+	/*	Config Method */
+	/*	This field should be big endian. Noted by P2P specification. */
+	if (pwdinfo->ui_got_wps_info == P2P_GOT_WPSINFO_PBC) {
+		/* *(u16*) ( p2pie + p2pielen ) = cpu_to_be16( WPS_CONFIG_METHOD_PBC ); */
+		RTW_PUT_BE16(p2pie + p2pielen, WPS_CONFIG_METHOD_PBC);
+	} else {
+		/* *(u16*) ( p2pie + p2pielen ) = cpu_to_be16( WPS_CONFIG_METHOD_DISPLAY ); */
+		RTW_PUT_BE16(p2pie + p2pielen, WPS_CONFIG_METHOD_DISPLAY);
+	}
+
+	p2pielen += 2;
+
+	/*	Primary Device Type */
+	/*	Category ID */
+	/* *(u16*) ( p2pie + p2pielen ) = cpu_to_be16( WPS_PDT_CID_MULIT_MEDIA ); */
+	RTW_PUT_BE16(p2pie + p2pielen, WPS_PDT_CID_MULIT_MEDIA);
+	p2pielen += 2;
+
+	/*	OUI */
+	/* *(u32*) ( p2pie + p2pielen ) = cpu_to_be32( WPSOUI ); */
+	RTW_PUT_BE32(p2pie + p2pielen, WPSOUI);
+	p2pielen += 4;
+
+	/*	Sub Category ID */
+	/* *(u16*) ( p2pie + p2pielen ) = cpu_to_be16( WPS_PDT_SCID_MEDIA_SERVER ); */
+	RTW_PUT_BE16(p2pie + p2pielen, WPS_PDT_SCID_MEDIA_SERVER);
+	p2pielen += 2;
+
+	/*	Number of Secondary Device Types */
+	p2pie[p2pielen++] = 0x00;	/*	No Secondary Device Type List */
+
+	/*	Device Name */
+	/*	Type: */
+	/* *(u16*) ( p2pie + p2pielen ) = cpu_to_be16( WPS_ATTR_DEVICE_NAME ); */
+	RTW_PUT_BE16(p2pie + p2pielen, WPS_ATTR_DEVICE_NAME);
+	p2pielen += 2;
+
+	/*	Length: */
+	/* *(u16*) ( p2pie + p2pielen ) = cpu_to_be16( pwdinfo->device_name_len ); */
+	RTW_PUT_BE16(p2pie + p2pielen, pwdinfo->device_name_len);
+	p2pielen += 2;
+
+	/*	Value: */
+	_rtw_memcpy(p2pie + p2pielen, pwdinfo->device_name, pwdinfo->device_name_len);
+	p2pielen += pwdinfo->device_name_len;
+
+	if (rtw_p2p_chk_role(pwdinfo, P2P_ROLE_CLIENT)) {
+		/*	Added by Albert 2011/05/19 */
+		/*	In this case, the pdev_raddr is the device address of the group owner. */
+
+		/*	P2P Group ID ATTR */
+		/*	Type: */
+		p2pie[p2pielen++] = P2P_ATTR_GROUP_ID;
+
+		/*	Length: */
+		/* *(u16*) ( p2pie + p2pielen ) = cpu_to_le16( ETH_ALEN + ussidlen ); */
+		RTW_PUT_LE16(p2pie + p2pielen, ETH_ALEN + ussidlen);
+		p2pielen += 2;
+
+		/*	Value: */
+		_rtw_memcpy(p2pie + p2pielen, pdev_raddr, ETH_ALEN);
+		p2pielen += ETH_ALEN;
+
+		_rtw_memcpy(p2pie + p2pielen, pssid, ussidlen);
+		p2pielen += ussidlen;
+
+	}
+
+	pbuf = rtw_set_ie(pbuf, _VENDOR_SPECIFIC_IE_, p2pielen, (unsigned char *) p2pie, &len);
+
+
+	return len;
+
+}
+
+
+u32 build_assoc_resp_p2p_ie(struct wifidirect_info *pwdinfo, u8 *pbuf, u8 status_code)
+{
+	u8 p2pie[MAX_P2P_IE_LEN] = { 0x00 };
+	u32 len = 0, p2pielen = 0;
+
+	/*	P2P OUI */
+	p2pielen = 0;
+	p2pie[p2pielen++] = 0x50;
+	p2pie[p2pielen++] = 0x6F;
+	p2pie[p2pielen++] = 0x9A;
+	p2pie[p2pielen++] = 0x09;	/*	WFA P2P v1.0 */
+
+	/* According to the P2P Specification, the Association response frame should contain 2 P2P attributes */
+	/*	1. Status */
+	/*	2. Extended Listen Timing (optional) */
+
+
+	/*	Status ATTR */
+	p2pielen += rtw_set_p2p_attr_content(&p2pie[p2pielen], P2P_ATTR_STATUS, 1, &status_code);
+
+
+	/* Extended Listen Timing ATTR */
+	/*	Type: */
+	/*	Length: */
+	/*	Value: */
+
+
+	pbuf = rtw_set_ie(pbuf, _VENDOR_SPECIFIC_IE_, p2pielen, (unsigned char *) p2pie, &len);
+
+	return len;
+
+}
+
+u32 build_deauth_p2p_ie(struct wifidirect_info *pwdinfo, u8 *pbuf)
+{
+	u32 len = 0;
+
+	return len;
+}
+
+u32 process_probe_req_p2p_ie(struct wifidirect_info *pwdinfo, u8 *pframe, uint len)
+{
+	u8 *p;
+	u32 ret = _FALSE;
+	u8 *p2pie;
+	u32	p2pielen = 0;
+	int ssid_len = 0, rate_cnt = 0;
+
+	p = rtw_get_ie(pframe + WLAN_HDR_A3_LEN + _PROBEREQ_IE_OFFSET_, _SUPPORTEDRATES_IE_, (int *)&rate_cnt,
+		       len - WLAN_HDR_A3_LEN - _PROBEREQ_IE_OFFSET_);
+
+	if (rate_cnt <= 4) {
+		int i, g_rate = 0;
+
+		for (i = 0; i < rate_cnt; i++) {
+			if (((*(p + 2 + i) & 0xff) != 0x02) &&
+			    ((*(p + 2 + i) & 0xff) != 0x04) &&
+			    ((*(p + 2 + i) & 0xff) != 0x0B) &&
+			    ((*(p + 2 + i) & 0xff) != 0x16))
+				g_rate = 1;
+		}
+
+		if (g_rate == 0) {
+			/*	There is no OFDM rate included in SupportedRates IE of this probe request frame */
+			/*	The driver should response this probe request. */
+			return ret;
+		}
+	} else {
+		/*	rate_cnt > 4 means the SupportRates IE contains the OFDM rate because the count of CCK rates are 4. */
+		/*	We should proceed the following check for this probe request. */
+	}
+
+	/*	Added comments by Albert 20100906 */
+	/*	There are several items we should check here. */
+	/*	1. This probe request frame must contain the P2P IE. (Done) */
+	/*	2. This probe request frame must contain the wildcard SSID. (Done) */
+	/*	3. Wildcard BSSID. (Todo) */
+	/*	4. Destination Address. ( Done in mgt_dispatcher function ) */
+	/*	5. Requested Device Type in WSC IE. (Todo) */
+	/*	6. Device ID attribute in P2P IE. (Todo) */
+
+	p = rtw_get_ie(pframe + WLAN_HDR_A3_LEN + _PROBEREQ_IE_OFFSET_, _SSID_IE_, (int *)&ssid_len,
+		       len - WLAN_HDR_A3_LEN - _PROBEREQ_IE_OFFSET_);
+
+	ssid_len &= 0xff;	/*	Just last 1 byte is valid for ssid len of the probe request */
+	if (rtw_p2p_chk_role(pwdinfo, P2P_ROLE_DEVICE) || rtw_p2p_chk_role(pwdinfo, P2P_ROLE_GO)) {
+		p2pie = rtw_get_p2p_ie(pframe + WLAN_HDR_A3_LEN + _PROBEREQ_IE_OFFSET_ , len - WLAN_HDR_A3_LEN - _PROBEREQ_IE_OFFSET_ , NULL, &p2pielen);
+		if (p2pie) {
+			if ((p != NULL) && _rtw_memcmp((void *)(p + 2), (void *) pwdinfo->p2p_wildcard_ssid , 7)) {
+				/* todo: */
+				/* Check Requested Device Type attributes in WSC IE. */
+				/* Check Device ID attribute in P2P IE */
+
+				ret = _TRUE;
+			} else if ((p != NULL) && (ssid_len == 0))
+				ret = _TRUE;
+		} else {
+			/* non -p2p device */
+		}
+
+	}
+
+
+	return ret;
+
+}
+
+u32 process_assoc_req_p2p_ie(struct wifidirect_info *pwdinfo, u8 *pframe, uint len, struct sta_info *psta)
+{
+	u8 status_code = P2P_STATUS_SUCCESS;
+	u8 *pbuf, *pattr_content = NULL;
+	u32 attr_contentlen = 0;
+	u16 cap_attr = 0;
+	unsigned short	frame_type, ie_offset = 0;
+	u8 *ies;
+	u32 ies_len;
+	u8 *p2p_ie;
+	u32	p2p_ielen = 0;
+
+	if (!rtw_p2p_chk_role(pwdinfo, P2P_ROLE_GO))
+		return P2P_STATUS_FAIL_REQUEST_UNABLE;
+
+	frame_type = get_frame_sub_type(pframe);
+	if (frame_type == WIFI_ASSOCREQ)
+		ie_offset = _ASOCREQ_IE_OFFSET_;
+	else /* WIFI_REASSOCREQ */
+		ie_offset = _REASOCREQ_IE_OFFSET_;
+
+	ies = pframe + WLAN_HDR_A3_LEN + ie_offset;
+	ies_len = len - WLAN_HDR_A3_LEN - ie_offset;
+
+	p2p_ie = rtw_get_p2p_ie(ies , ies_len , NULL, &p2p_ielen);
+
+	if (!p2p_ie) {
+		RTW_INFO("[%s] P2P IE not Found!!\n", __FUNCTION__);
+		status_code =  P2P_STATUS_FAIL_INVALID_PARAM;
+	} else
+		RTW_INFO("[%s] P2P IE Found!!\n", __FUNCTION__);
+
+	while (p2p_ie) {
+		/* Check P2P Capability ATTR */
+		if (rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_CAPABILITY, (u8 *)&cap_attr, (uint *) &attr_contentlen)) {
+			RTW_INFO("[%s] Got P2P Capability Attr!!\n", __FUNCTION__);
+			cap_attr = le16_to_cpu(cap_attr);
+			psta->dev_cap = cap_attr & 0xff;
+		}
+
+		/* Check Extended Listen Timing ATTR */
+
+
+		/* Check P2P Device Info ATTR */
+		if (rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_DEVICE_INFO, NULL, (uint *)&attr_contentlen)) {
+			RTW_INFO("[%s] Got P2P DEVICE INFO Attr!!\n", __FUNCTION__);
+			pattr_content = pbuf = rtw_zmalloc(attr_contentlen);
+			if (pattr_content) {
+				u8 num_of_secdev_type;
+				u16 dev_name_len;
+
+
+				rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_DEVICE_INFO , pattr_content, (uint *)&attr_contentlen);
+
+				_rtw_memcpy(psta->dev_addr, 	pattr_content, ETH_ALEN);/* P2P Device Address */
+
+				pattr_content += ETH_ALEN;
+
+				_rtw_memcpy(&psta->config_methods, pattr_content, 2);/* Config Methods */
+				psta->config_methods = be16_to_cpu(psta->config_methods);
+
+				pattr_content += 2;
+
+				_rtw_memcpy(psta->primary_dev_type, pattr_content, 8);
+
+				pattr_content += 8;
+
+				num_of_secdev_type = *pattr_content;
+				pattr_content += 1;
+
+				if (num_of_secdev_type == 0)
+					psta->num_of_secdev_type = 0;
+				else {
+					u32 len;
+
+					psta->num_of_secdev_type = num_of_secdev_type;
+
+					len = (sizeof(psta->secdev_types_list) < (num_of_secdev_type * 8)) ? (sizeof(psta->secdev_types_list)) : (num_of_secdev_type * 8);
+
+					_rtw_memcpy(psta->secdev_types_list, pattr_content, len);
+
+					pattr_content += (num_of_secdev_type * 8);
+				}
+
+
+				/* dev_name_len = attr_contentlen - ETH_ALEN - 2 - 8 - 1 - (num_of_secdev_type*8); */
+				psta->dev_name_len = 0;
+				if (WPS_ATTR_DEVICE_NAME == be16_to_cpu(*(u16 *)pattr_content)) {
+					dev_name_len = be16_to_cpu(*(u16 *)(pattr_content + 2));
+
+					psta->dev_name_len = (sizeof(psta->dev_name) < dev_name_len) ? sizeof(psta->dev_name) : dev_name_len;
+
+					_rtw_memcpy(psta->dev_name, pattr_content + 4, psta->dev_name_len);
+				}
+
+				rtw_mfree(pbuf, attr_contentlen);
+
+			}
+
+		}
+
+		/* Get the next P2P IE */
+		p2p_ie = rtw_get_p2p_ie(p2p_ie + p2p_ielen, ies_len - (p2p_ie - ies + p2p_ielen), NULL, &p2p_ielen);
+
+	}
+
+	return status_code;
+
+}
+
+u32 process_p2p_devdisc_req(struct wifidirect_info *pwdinfo, u8 *pframe, uint len)
+{
+	u8 *frame_body;
+	u8 status, dialogToken;
+	struct sta_info *psta = NULL;
+	_adapter *padapter = pwdinfo->padapter;
+	struct sta_priv *pstapriv = &padapter->stapriv;
+	u8 *p2p_ie;
+	u32	p2p_ielen = 0;
+
+	frame_body = (unsigned char *)(pframe + sizeof(struct rtw_ieee80211_hdr_3addr));
+
+	dialogToken = frame_body[7];
+	status = P2P_STATUS_FAIL_UNKNOWN_P2PGROUP;
+
+	p2p_ie = rtw_get_p2p_ie(frame_body + _PUBLIC_ACTION_IE_OFFSET_, len - _PUBLIC_ACTION_IE_OFFSET_, NULL, &p2p_ielen);
+	if (p2p_ie) {
+		u8 groupid[38] = { 0x00 };
+		u8 dev_addr[ETH_ALEN] = { 0x00 };
+		u32	attr_contentlen = 0;
+
+		if (rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_GROUP_ID, groupid, &attr_contentlen)) {
+			if (_rtw_memcmp(pwdinfo->device_addr, groupid, ETH_ALEN) &&
+			    _rtw_memcmp(pwdinfo->p2p_group_ssid, groupid + ETH_ALEN, pwdinfo->p2p_group_ssid_len)) {
+				attr_contentlen = 0;
+				if (rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_DEVICE_ID, dev_addr, &attr_contentlen)) {
+					_irqL irqL;
+					_list	*phead, *plist;
+
+					_enter_critical_bh(&pstapriv->asoc_list_lock, &irqL);
+					phead = &pstapriv->asoc_list;
+					plist = get_next(phead);
+
+					/* look up sta asoc_queue */
+					while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) {
+						psta = LIST_CONTAINOR(plist, struct sta_info, asoc_list);
+
+						plist = get_next(plist);
+
+						if (psta->is_p2p_device && (psta->dev_cap & P2P_DEVCAP_CLIENT_DISCOVERABILITY) &&
+						    _rtw_memcmp(psta->dev_addr, dev_addr, ETH_ALEN)) {
+
+							/* _exit_critical_bh(&pstapriv->asoc_list_lock, &irqL); */
+							/* issue GO Discoverability Request */
+							issue_group_disc_req(pwdinfo, psta->cmn.mac_addr);
+							/* _enter_critical_bh(&pstapriv->asoc_list_lock, &irqL); */
+
+							status = P2P_STATUS_SUCCESS;
+
+							break;
+						} else
+							status = P2P_STATUS_FAIL_INFO_UNAVAILABLE;
+
+					}
+					_exit_critical_bh(&pstapriv->asoc_list_lock, &irqL);
+
+				} else
+					status = P2P_STATUS_FAIL_INVALID_PARAM;
+
+			} else
+				status = P2P_STATUS_FAIL_INVALID_PARAM;
+
+		}
+
+	}
+
+
+	/* issue Device Discoverability Response */
+	issue_p2p_devdisc_resp(pwdinfo, get_addr2_ptr(pframe), status, dialogToken);
+
+
+	return (status == P2P_STATUS_SUCCESS) ? _TRUE : _FALSE;
+
+}
+
+u32 process_p2p_devdisc_resp(struct wifidirect_info *pwdinfo, u8 *pframe, uint len)
+{
+	return _TRUE;
+}
+
+u8 process_p2p_provdisc_req(struct wifidirect_info *pwdinfo,  u8 *pframe, uint len)
+{
+	u8 *frame_body;
+	u8 *wpsie;
+	uint	wps_ielen = 0, attr_contentlen = 0;
+	u16	uconfig_method = 0;
+
+
+	frame_body = (pframe + sizeof(struct rtw_ieee80211_hdr_3addr));
+
+	wpsie = rtw_get_wps_ie(frame_body + _PUBLIC_ACTION_IE_OFFSET_, len - _PUBLIC_ACTION_IE_OFFSET_, NULL, &wps_ielen);
+	if (wpsie) {
+		if (rtw_get_wps_attr_content(wpsie, wps_ielen, WPS_ATTR_CONF_METHOD , (u8 *) &uconfig_method, &attr_contentlen)) {
+			uconfig_method = be16_to_cpu(uconfig_method);
+			switch (uconfig_method) {
+			case WPS_CM_DISPLYA: {
+				_rtw_memcpy(pwdinfo->rx_prov_disc_info.strconfig_method_desc_of_prov_disc_req, "dis", 3);
+				break;
+			}
+			case WPS_CM_LABEL: {
+				_rtw_memcpy(pwdinfo->rx_prov_disc_info.strconfig_method_desc_of_prov_disc_req, "lab", 3);
+				break;
+			}
+			case WPS_CM_PUSH_BUTTON: {
+				_rtw_memcpy(pwdinfo->rx_prov_disc_info.strconfig_method_desc_of_prov_disc_req, "pbc", 3);
+				break;
+			}
+			case WPS_CM_KEYPAD: {
+				_rtw_memcpy(pwdinfo->rx_prov_disc_info.strconfig_method_desc_of_prov_disc_req, "pad", 3);
+				break;
+			}
+			}
+			issue_p2p_provision_resp(pwdinfo, get_addr2_ptr(pframe), frame_body, uconfig_method);
+		}
+	}
+	RTW_INFO("[%s] config method = %s\n", __FUNCTION__, pwdinfo->rx_prov_disc_info.strconfig_method_desc_of_prov_disc_req);
+	return _TRUE;
+
+}
+
+u8 process_p2p_provdisc_resp(struct wifidirect_info *pwdinfo,  u8 *pframe)
+{
+
+	return _TRUE;
+}
+
+u8 rtw_p2p_get_peer_ch_list(struct wifidirect_info *pwdinfo, u8 *ch_content, u8 ch_cnt, u8 *peer_ch_list)
+{
+	u8 i = 0, j = 0;
+	u8 temp = 0;
+	u8 ch_no = 0;
+	ch_content += 3;
+	ch_cnt -= 3;
+
+	while (ch_cnt > 0) {
+		ch_content += 1;
+		ch_cnt -= 1;
+		temp = *ch_content;
+		for (i = 0 ; i < temp ; i++, j++)
+			peer_ch_list[j] = *(ch_content + 1 + i);
+		ch_content += (temp + 1);
+		ch_cnt -= (temp + 1);
+		ch_no += temp ;
+	}
+
+	return ch_no;
+}
+
+u8 rtw_p2p_ch_inclusion(_adapter *adapter, u8 *peer_ch_list, u8 peer_ch_num, u8 *ch_list_inclusioned)
+{
+	struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter);
+	int	i = 0, j = 0, temp = 0;
+	u8 ch_no = 0;
+
+	for (i = 0; i < peer_ch_num; i++) {
+		for (j = temp; j < rfctl->max_chan_nums; j++) {
+			if (*(peer_ch_list + i) == rfctl->channel_set[j].ChannelNum) {
+				ch_list_inclusioned[ch_no++] = *(peer_ch_list + i);
+				temp = j;
+				break;
+			}
+		}
+	}
+
+	return ch_no;
+}
+
+u8 process_p2p_group_negotation_req(struct wifidirect_info *pwdinfo, u8 *pframe, uint len)
+{
+	_adapter *padapter = pwdinfo->padapter;
+	u8	result = P2P_STATUS_SUCCESS;
+	u32	p2p_ielen = 0, wps_ielen = 0;
+	u8 *ies;
+	u32 ies_len;
+	u8 *p2p_ie;
+	u8 *wpsie;
+	u16		wps_devicepassword_id = 0x0000;
+	uint	wps_devicepassword_id_len = 0;
+#ifdef CONFIG_WFD
+#ifdef CONFIG_TDLS
+	struct tdls_info *ptdlsinfo = &padapter->tdlsinfo;
+#endif /* CONFIG_TDLS	 */
+#endif /* CONFIG_WFD */
+	wpsie = rtw_get_wps_ie(pframe + _PUBLIC_ACTION_IE_OFFSET_, len - _PUBLIC_ACTION_IE_OFFSET_, NULL, &wps_ielen);
+	if (wpsie) {
+		/*	Commented by Kurt 20120113 */
+		/*	If some device wants to do p2p handshake without sending prov_disc_req */
+		/*	We have to get peer_req_cm from here. */
+		if (_rtw_memcmp(pwdinfo->rx_prov_disc_info.strconfig_method_desc_of_prov_disc_req, "000", 3)) {
+			rtw_get_wps_attr_content(wpsie, wps_ielen, WPS_ATTR_DEVICE_PWID, (u8 *) &wps_devicepassword_id, &wps_devicepassword_id_len);
+			wps_devicepassword_id = be16_to_cpu(wps_devicepassword_id);
+
+			if (wps_devicepassword_id == WPS_DPID_USER_SPEC)
+				_rtw_memcpy(pwdinfo->rx_prov_disc_info.strconfig_method_desc_of_prov_disc_req, "dis", 3);
+			else if (wps_devicepassword_id == WPS_DPID_REGISTRAR_SPEC)
+				_rtw_memcpy(pwdinfo->rx_prov_disc_info.strconfig_method_desc_of_prov_disc_req, "pad", 3);
+			else
+				_rtw_memcpy(pwdinfo->rx_prov_disc_info.strconfig_method_desc_of_prov_disc_req, "pbc", 3);
+		}
+	} else {
+		RTW_INFO("[%s] WPS IE not Found!!\n", __FUNCTION__);
+		result = P2P_STATUS_FAIL_INCOMPATIBLE_PARAM;
+		rtw_p2p_set_state(pwdinfo, P2P_STATE_GONEGO_FAIL);
+		return result ;
+	}
+
+	ies = pframe + _PUBLIC_ACTION_IE_OFFSET_;
+	ies_len = len - _PUBLIC_ACTION_IE_OFFSET_;
+
+	p2p_ie = rtw_get_p2p_ie(ies, ies_len, NULL, &p2p_ielen);
+
+	if (!p2p_ie) {
+		RTW_INFO("[%s] P2P IE not Found!!\n", __FUNCTION__);
+		result = P2P_STATUS_FAIL_INCOMPATIBLE_PARAM;
+		rtw_p2p_set_state(pwdinfo, P2P_STATE_GONEGO_FAIL);
+	}
+
+	while (p2p_ie) {
+		u8	attr_content = 0x00;
+		u32	attr_contentlen = 0;
+		u8	ch_content[100] = { 0x00 };
+		uint	ch_cnt = 0;
+		u8	peer_ch_list[100] = { 0x00 };
+		u8	peer_ch_num = 0;
+		u8	ch_list_inclusioned[100] = { 0x00 };
+		u8	ch_num_inclusioned = 0;
+		u16	cap_attr;
+		u8 listen_ch_attr[5] = { 0x00 };
+
+		rtw_p2p_set_state(pwdinfo, P2P_STATE_GONEGO_ING);
+
+		/* Check P2P Capability ATTR */
+		if (rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_CAPABILITY, (u8 *)&cap_attr, (uint *)&attr_contentlen)) {
+			cap_attr = le16_to_cpu(cap_attr);
+
+#if defined(CONFIG_WFD) && defined(CONFIG_TDLS)
+			if (!(cap_attr & P2P_GRPCAP_INTRABSS))
+				ptdlsinfo->ap_prohibited = _TRUE;
+#endif /* defined(CONFIG_WFD) && defined(CONFIG_TDLS) */
+		}
+
+		if (rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_GO_INTENT , &attr_content, &attr_contentlen)) {
+			RTW_INFO("[%s] GO Intent = %d, tie = %d\n", __FUNCTION__, attr_content >> 1, attr_content & 0x01);
+			pwdinfo->peer_intent = attr_content;	/*	include both intent and tie breaker values. */
+
+			if (pwdinfo->intent == (pwdinfo->peer_intent >> 1)) {
+				/*	Try to match the tie breaker value */
+				if (pwdinfo->intent == P2P_MAX_INTENT) {
+					rtw_p2p_set_role(pwdinfo, P2P_ROLE_DEVICE);
+					result = P2P_STATUS_FAIL_BOTH_GOINTENT_15;
+				} else {
+					if (attr_content & 0x01)
+						rtw_p2p_set_role(pwdinfo, P2P_ROLE_CLIENT);
+					else
+						rtw_p2p_set_role(pwdinfo, P2P_ROLE_GO);
+				}
+			} else if (pwdinfo->intent > (pwdinfo->peer_intent >> 1))
+				rtw_p2p_set_role(pwdinfo, P2P_ROLE_GO);
+			else
+				rtw_p2p_set_role(pwdinfo, P2P_ROLE_CLIENT);
+
+			if (rtw_p2p_chk_role(pwdinfo, P2P_ROLE_GO)) {
+				/*	Store the group id information. */
+				_rtw_memcpy(pwdinfo->groupid_info.go_device_addr, pwdinfo->device_addr, ETH_ALEN);
+				_rtw_memcpy(pwdinfo->groupid_info.ssid, pwdinfo->nego_ssid, pwdinfo->nego_ssidlen);
+			}
+		}
+
+		if (rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_LISTEN_CH, (u8 *)listen_ch_attr, (uint *) &attr_contentlen) && attr_contentlen == 5)
+			pwdinfo->nego_req_info.peer_ch = listen_ch_attr[4];
+
+		RTW_INFO(FUNC_ADPT_FMT" listen channel :%u\n", FUNC_ADPT_ARG(padapter), pwdinfo->nego_req_info.peer_ch);
+
+		attr_contentlen = 0;
+		if (rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_INTENDED_IF_ADDR, pwdinfo->p2p_peer_interface_addr, &attr_contentlen)) {
+			if (attr_contentlen != ETH_ALEN)
+				_rtw_memset(pwdinfo->p2p_peer_interface_addr, 0x00, ETH_ALEN);
+		}
+
+		if (rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_CH_LIST, ch_content, &ch_cnt)) {
+			peer_ch_num = rtw_p2p_get_peer_ch_list(pwdinfo, ch_content, ch_cnt, peer_ch_list);
+			ch_num_inclusioned = rtw_p2p_ch_inclusion(padapter, peer_ch_list, peer_ch_num, ch_list_inclusioned);
+
+			if (ch_num_inclusioned == 0) {
+				RTW_INFO("[%s] No common channel in channel list!\n", __FUNCTION__);
+				result = P2P_STATUS_FAIL_NO_COMMON_CH;
+				rtw_p2p_set_state(pwdinfo, P2P_STATE_GONEGO_FAIL);
+				break;
+			}
+
+			if (rtw_p2p_chk_role(pwdinfo, P2P_ROLE_GO)) {
+				if (!rtw_p2p_is_channel_list_ok(pwdinfo->operating_channel,
+					ch_list_inclusioned, ch_num_inclusioned)) {
+#ifdef CONFIG_CONCURRENT_MODE
+					if (rtw_mi_check_status(padapter, MI_LINKED)
+					    && padapter->registrypriv.full_ch_in_p2p_handshake == 0) {
+						RTW_INFO("[%s] desired channel NOT Found!\n", __FUNCTION__);
+						result = P2P_STATUS_FAIL_NO_COMMON_CH;
+						rtw_p2p_set_state(pwdinfo, P2P_STATE_GONEGO_FAIL);
+						break;
+					} else
+#endif /* CONFIG_CONCURRENT_MODE */
+					{
+						u8 operatingch_info[5] = { 0x00 }, peer_operating_ch = 0;
+						attr_contentlen = 0;
+
+						if (rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_OPERATING_CH, operatingch_info, &attr_contentlen))
+							peer_operating_ch = operatingch_info[4];
+
+						if (rtw_p2p_is_channel_list_ok(peer_operating_ch,
+							ch_list_inclusioned, ch_num_inclusioned)) {
+							/**
+							 *	Change our operating channel as peer's for compatibility.
+							 */
+							pwdinfo->operating_channel = peer_operating_ch;
+							RTW_INFO("[%s] Change op ch to %02x as peer's\n", __FUNCTION__, pwdinfo->operating_channel);
+						} else {
+							/* Take first channel of ch_list_inclusioned as operating channel */
+							pwdinfo->operating_channel = ch_list_inclusioned[0];
+							RTW_INFO("[%s] Change op ch to %02x\n", __FUNCTION__, pwdinfo->operating_channel);
+						}
+					}
+
+				}
+			}
+		}
+
+		/* Get the next P2P IE */
+		p2p_ie = rtw_get_p2p_ie(p2p_ie + p2p_ielen, ies_len - (p2p_ie - ies + p2p_ielen), NULL, &p2p_ielen);
+	}
+
+	if (pwdinfo->ui_got_wps_info == P2P_NO_WPSINFO) {
+		result = P2P_STATUS_FAIL_INFO_UNAVAILABLE;
+		rtw_p2p_set_state(pwdinfo, P2P_STATE_TX_INFOR_NOREADY);
+		return result;
+	}
+
+#ifdef CONFIG_WFD
+	rtw_process_wfd_ies(padapter, pframe + _PUBLIC_ACTION_IE_OFFSET_, len - _PUBLIC_ACTION_IE_OFFSET_, __func__);
+#endif
+
+	return result ;
+}
+
+u8 process_p2p_group_negotation_resp(struct wifidirect_info *pwdinfo, u8 *pframe, uint len)
+{
+	_adapter *padapter = pwdinfo->padapter;
+	u8	result = P2P_STATUS_SUCCESS;
+	u32	p2p_ielen, wps_ielen;
+	u8 *ies;
+	u32 ies_len;
+	u8 *p2p_ie;
+#ifdef CONFIG_WFD
+#ifdef CONFIG_TDLS
+	struct tdls_info *ptdlsinfo = &padapter->tdlsinfo;
+#endif /* CONFIG_TDLS	 */
+#endif /* CONFIG_WFD */
+
+	ies = pframe + _PUBLIC_ACTION_IE_OFFSET_;
+	ies_len = len - _PUBLIC_ACTION_IE_OFFSET_;
+
+	/*	Be able to know which one is the P2P GO and which one is P2P client. */
+
+	if (rtw_get_wps_ie(ies, ies_len, NULL, &wps_ielen)) {
+
+	} else {
+		RTW_INFO("[%s] WPS IE not Found!!\n", __FUNCTION__);
+		result = P2P_STATUS_FAIL_INCOMPATIBLE_PARAM;
+		rtw_p2p_set_state(pwdinfo, P2P_STATE_GONEGO_FAIL);
+	}
+
+	p2p_ie = rtw_get_p2p_ie(ies, ies_len, NULL, &p2p_ielen);
+	if (!p2p_ie) {
+		rtw_p2p_set_role(pwdinfo, P2P_ROLE_DEVICE);
+		rtw_p2p_set_state(pwdinfo, P2P_STATE_GONEGO_FAIL);
+		result = P2P_STATUS_FAIL_INCOMPATIBLE_PARAM;
+	} else {
+
+		u8	attr_content = 0x00;
+		u32	attr_contentlen = 0;
+		u8	operatingch_info[5] = { 0x00 };
+		u8	groupid[38];
+		u16	cap_attr;
+		u8	peer_ch_list[100] = { 0x00 };
+		u8	peer_ch_num = 0;
+		u8	ch_list_inclusioned[100] = { 0x00 };
+		u8	ch_num_inclusioned = 0;
+
+		while (p2p_ie) {	/*	Found the P2P IE. */
+
+			/* Check P2P Capability ATTR */
+			if (rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_CAPABILITY, (u8 *)&cap_attr, (uint *)&attr_contentlen)) {
+				cap_attr = le16_to_cpu(cap_attr);
+#ifdef CONFIG_TDLS
+				if (!(cap_attr & P2P_GRPCAP_INTRABSS))
+					ptdlsinfo->ap_prohibited = _TRUE;
+#endif /* CONFIG_TDLS */
+			}
+
+			rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_STATUS, &attr_content, &attr_contentlen);
+			if (attr_contentlen == 1) {
+				RTW_INFO("[%s] Status = %d\n", __FUNCTION__, attr_content);
+				if (attr_content == P2P_STATUS_SUCCESS) {
+					/*	Do nothing. */
+				} else {
+					if (P2P_STATUS_FAIL_INFO_UNAVAILABLE == attr_content)
+						rtw_p2p_set_state(pwdinfo, P2P_STATE_RX_INFOR_NOREADY);
+					else
+						rtw_p2p_set_state(pwdinfo, P2P_STATE_GONEGO_FAIL);
+					rtw_p2p_set_role(pwdinfo, P2P_ROLE_DEVICE);
+					result = attr_content;
+					break;
+				}
+			}
+
+			/*	Try to get the peer's interface address */
+			attr_contentlen = 0;
+			if (rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_INTENDED_IF_ADDR, pwdinfo->p2p_peer_interface_addr, &attr_contentlen)) {
+				if (attr_contentlen != ETH_ALEN)
+					_rtw_memset(pwdinfo->p2p_peer_interface_addr, 0x00, ETH_ALEN);
+			}
+
+			/*	Try to get the peer's intent and tie breaker value. */
+			attr_content = 0x00;
+			attr_contentlen = 0;
+			if (rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_GO_INTENT , &attr_content, &attr_contentlen)) {
+				RTW_INFO("[%s] GO Intent = %d, tie = %d\n", __FUNCTION__, attr_content >> 1, attr_content & 0x01);
+				pwdinfo->peer_intent = attr_content;	/*	include both intent and tie breaker values. */
+
+				if (pwdinfo->intent == (pwdinfo->peer_intent >> 1)) {
+					/*	Try to match the tie breaker value */
+					if (pwdinfo->intent == P2P_MAX_INTENT) {
+						rtw_p2p_set_role(pwdinfo, P2P_ROLE_DEVICE);
+						result = P2P_STATUS_FAIL_BOTH_GOINTENT_15;
+						rtw_p2p_set_state(pwdinfo, P2P_STATE_GONEGO_FAIL);
+					} else {
+						rtw_p2p_set_state(pwdinfo, P2P_STATE_GONEGO_OK);
+						rtw_p2p_set_pre_state(pwdinfo, P2P_STATE_GONEGO_OK);
+						if (attr_content & 0x01)
+							rtw_p2p_set_role(pwdinfo, P2P_ROLE_CLIENT);
+						else
+							rtw_p2p_set_role(pwdinfo, P2P_ROLE_GO);
+					}
+				} else if (pwdinfo->intent > (pwdinfo->peer_intent >> 1)) {
+					rtw_p2p_set_state(pwdinfo, P2P_STATE_GONEGO_OK);
+					rtw_p2p_set_pre_state(pwdinfo, P2P_STATE_GONEGO_OK);
+					rtw_p2p_set_role(pwdinfo, P2P_ROLE_GO);
+				} else {
+					rtw_p2p_set_state(pwdinfo, P2P_STATE_GONEGO_OK);
+					rtw_p2p_set_pre_state(pwdinfo, P2P_STATE_GONEGO_OK);
+					rtw_p2p_set_role(pwdinfo, P2P_ROLE_CLIENT);
+				}
+
+				if (rtw_p2p_chk_role(pwdinfo, P2P_ROLE_GO)) {
+					/*	Store the group id information. */
+					_rtw_memcpy(pwdinfo->groupid_info.go_device_addr, pwdinfo->device_addr, ETH_ALEN);
+					_rtw_memcpy(pwdinfo->groupid_info.ssid, pwdinfo->nego_ssid, pwdinfo->nego_ssidlen);
+
+				}
+			}
+
+			/*	Try to get the operation channel information */
+
+			attr_contentlen = 0;
+			if (rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_OPERATING_CH, operatingch_info, &attr_contentlen)) {
+				RTW_INFO("[%s] Peer's operating channel = %d\n", __FUNCTION__, operatingch_info[4]);
+				pwdinfo->peer_operating_ch = operatingch_info[4];
+			}
+
+			/*	Try to get the channel list information */
+			if (rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_CH_LIST, pwdinfo->channel_list_attr, &pwdinfo->channel_list_attr_len)) {
+				RTW_INFO("[%s] channel list attribute found, len = %d\n", __FUNCTION__,  pwdinfo->channel_list_attr_len);
+
+				peer_ch_num = rtw_p2p_get_peer_ch_list(pwdinfo, pwdinfo->channel_list_attr, pwdinfo->channel_list_attr_len, peer_ch_list);
+				ch_num_inclusioned = rtw_p2p_ch_inclusion(padapter, peer_ch_list, peer_ch_num, ch_list_inclusioned);
+
+				if (ch_num_inclusioned == 0) {
+					RTW_INFO("[%s] No common channel in channel list!\n", __FUNCTION__);
+					result = P2P_STATUS_FAIL_NO_COMMON_CH;
+					rtw_p2p_set_state(pwdinfo, P2P_STATE_GONEGO_FAIL);
+					break;
+				}
+
+				if (rtw_p2p_chk_role(pwdinfo, P2P_ROLE_GO)) {
+					if (!rtw_p2p_is_channel_list_ok(pwdinfo->operating_channel,
+						ch_list_inclusioned, ch_num_inclusioned)) {
+#ifdef CONFIG_CONCURRENT_MODE
+						if (rtw_mi_check_status(padapter, MI_LINKED)
+						    && padapter->registrypriv.full_ch_in_p2p_handshake == 0) {
+							RTW_INFO("[%s] desired channel NOT Found!\n", __FUNCTION__);
+							result = P2P_STATUS_FAIL_NO_COMMON_CH;
+							rtw_p2p_set_state(pwdinfo, P2P_STATE_GONEGO_FAIL);
+							break;
+						} else
+#endif /* CONFIG_CONCURRENT_MODE */
+						{
+							u8 operatingch_info[5] = { 0x00 }, peer_operating_ch = 0;
+							attr_contentlen = 0;
+
+							if (rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_OPERATING_CH, operatingch_info, &attr_contentlen))
+								peer_operating_ch = operatingch_info[4];
+
+							if (rtw_p2p_is_channel_list_ok(peer_operating_ch,
+								ch_list_inclusioned, ch_num_inclusioned)) {
+								/**
+								 *	Change our operating channel as peer's for compatibility.
+								 */
+								pwdinfo->operating_channel = peer_operating_ch;
+								RTW_INFO("[%s] Change op ch to %02x as peer's\n", __FUNCTION__, pwdinfo->operating_channel);
+							} else {
+								/* Take first channel of ch_list_inclusioned as operating channel */
+								pwdinfo->operating_channel = ch_list_inclusioned[0];
+								RTW_INFO("[%s] Change op ch to %02x\n", __FUNCTION__, pwdinfo->operating_channel);
+							}
+						}
+
+					}
+				}
+
+			} else
+				RTW_INFO("[%s] channel list attribute not found!\n", __FUNCTION__);
+
+			/*	Try to get the group id information if peer is GO */
+			attr_contentlen = 0;
+			_rtw_memset(groupid, 0x00, 38);
+			if (rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_GROUP_ID, groupid, &attr_contentlen)) {
+				_rtw_memcpy(pwdinfo->groupid_info.go_device_addr, &groupid[0], ETH_ALEN);
+				_rtw_memcpy(pwdinfo->groupid_info.ssid, &groupid[6], attr_contentlen - ETH_ALEN);
+			}
+
+			/* Get the next P2P IE */
+			p2p_ie = rtw_get_p2p_ie(p2p_ie + p2p_ielen, ies_len - (p2p_ie - ies + p2p_ielen), NULL, &p2p_ielen);
+		}
+
+	}
+
+#ifdef CONFIG_WFD
+	rtw_process_wfd_ies(padapter, pframe + _PUBLIC_ACTION_IE_OFFSET_, len - _PUBLIC_ACTION_IE_OFFSET_, __func__);
+#endif
+
+	return result ;
+
+}
+
+u8 process_p2p_group_negotation_confirm(struct wifidirect_info *pwdinfo, u8 *pframe, uint len)
+{
+#ifdef CONFIG_CONCURRENT_MODE
+	_adapter *padapter = pwdinfo->padapter;
+#endif
+	u8 *ies;
+	u32 ies_len;
+	u8 *p2p_ie;
+	u32	p2p_ielen = 0;
+	u8	result = P2P_STATUS_SUCCESS;
+	ies = pframe + _PUBLIC_ACTION_IE_OFFSET_;
+	ies_len = len - _PUBLIC_ACTION_IE_OFFSET_;
+
+	p2p_ie = rtw_get_p2p_ie(ies, ies_len, NULL, &p2p_ielen);
+	while (p2p_ie) {	/*	Found the P2P IE. */
+		u8	attr_content = 0x00, operatingch_info[5] = { 0x00 };
+		u8	groupid[38] = { 0x00 };
+		u32	attr_contentlen = 0;
+
+		pwdinfo->negotiation_dialog_token = 1;
+		rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_STATUS, &attr_content, &attr_contentlen);
+		if (attr_contentlen == 1) {
+			RTW_INFO("[%s] Status = %d\n", __FUNCTION__, attr_content);
+			result = attr_content;
+
+			if (attr_content == P2P_STATUS_SUCCESS) {
+
+				_cancel_timer_ex(&pwdinfo->restore_p2p_state_timer);
+
+				/*	Commented by Albert 20100911 */
+				/*	Todo: Need to handle the case which both Intents are the same. */
+				rtw_p2p_set_state(pwdinfo, P2P_STATE_GONEGO_OK);
+				rtw_p2p_set_pre_state(pwdinfo, P2P_STATE_GONEGO_OK);
+				if ((pwdinfo->intent) > (pwdinfo->peer_intent >> 1))
+					rtw_p2p_set_role(pwdinfo, P2P_ROLE_GO);
+				else if ((pwdinfo->intent) < (pwdinfo->peer_intent >> 1))
+					rtw_p2p_set_role(pwdinfo, P2P_ROLE_CLIENT);
+				else {
+					/*	Have to compare the Tie Breaker */
+					if (pwdinfo->peer_intent & 0x01)
+						rtw_p2p_set_role(pwdinfo, P2P_ROLE_CLIENT);
+					else
+						rtw_p2p_set_role(pwdinfo, P2P_ROLE_GO);
+				}
+
+#ifdef CONFIG_CONCURRENT_MODE
+				if (rtw_mi_check_status(padapter, MI_LINKED)
+				    && padapter->registrypriv.full_ch_in_p2p_handshake == 0) {
+					/*	Switch back to the AP channel soon. */
+					_set_timer(&pwdinfo->ap_p2p_switch_timer, 100);
+				}
+#endif
+			} else {
+				rtw_p2p_set_role(pwdinfo, P2P_ROLE_DEVICE);
+				rtw_p2p_set_state(pwdinfo, P2P_STATE_GONEGO_FAIL);
+				break;
+			}
+		}
+
+		/*	Try to get the group id information */
+		attr_contentlen = 0;
+		_rtw_memset(groupid, 0x00, 38);
+		if (rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_GROUP_ID, groupid, &attr_contentlen)) {
+			RTW_INFO("[%s] Ssid = %s, ssidlen = %zu\n", __FUNCTION__, &groupid[ETH_ALEN], strlen(&groupid[ETH_ALEN]));
+			_rtw_memcpy(pwdinfo->groupid_info.go_device_addr, &groupid[0], ETH_ALEN);
+			_rtw_memcpy(pwdinfo->groupid_info.ssid, &groupid[6], attr_contentlen - ETH_ALEN);
+		}
+
+		attr_contentlen = 0;
+		if (rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_OPERATING_CH, operatingch_info, &attr_contentlen)) {
+			RTW_INFO("[%s] Peer's operating channel = %d\n", __FUNCTION__, operatingch_info[4]);
+			pwdinfo->peer_operating_ch = operatingch_info[4];
+		}
+
+		/* Get the next P2P IE */
+		p2p_ie = rtw_get_p2p_ie(p2p_ie + p2p_ielen, ies_len - (p2p_ie - ies + p2p_ielen), NULL, &p2p_ielen);
+
+	}
+
+	return result ;
+}
+
+u8 process_p2p_presence_req(struct wifidirect_info *pwdinfo, u8 *pframe, uint len)
+{
+	u8 *frame_body;
+	u8 dialogToken = 0;
+	u8 status = P2P_STATUS_SUCCESS;
+
+	frame_body = (unsigned char *)(pframe + sizeof(struct rtw_ieee80211_hdr_3addr));
+
+	dialogToken = frame_body[6];
+
+	/* todo: check NoA attribute */
+
+	issue_p2p_presence_resp(pwdinfo, get_addr2_ptr(pframe), status, dialogToken);
+
+	return _TRUE;
+}
+
+void find_phase_handler(_adapter	*padapter)
+{
+	struct wifidirect_info  *pwdinfo = &padapter->wdinfo;
+	struct mlme_priv		*pmlmepriv = &padapter->mlmepriv;
+	struct sitesurvey_parm parm;
+	_irqL				irqL;
+	u8					_status = 0;
+
+
+	rtw_init_sitesurvey_parm(padapter, &parm);
+	_rtw_memcpy(&parm.ssid[0].Ssid, pwdinfo->p2p_wildcard_ssid, P2P_WILDCARD_SSID_LEN);
+	parm.ssid[0].SsidLength = P2P_WILDCARD_SSID_LEN;
+	parm.ssid_num = 1;
+
+	rtw_p2p_set_state(pwdinfo, P2P_STATE_FIND_PHASE_SEARCH);
+
+	_enter_critical_bh(&pmlmepriv->lock, &irqL);
+	_status = rtw_sitesurvey_cmd(padapter, &parm);
+	_exit_critical_bh(&pmlmepriv->lock, &irqL);
+
+
+}
+
+void p2p_concurrent_handler(_adapter *padapter);
+
+void restore_p2p_state_handler(_adapter	*padapter)
+{
+	struct wifidirect_info  *pwdinfo = &padapter->wdinfo;
+
+	if (rtw_p2p_chk_state(pwdinfo, P2P_STATE_GONEGO_ING) || rtw_p2p_chk_state(pwdinfo, P2P_STATE_GONEGO_FAIL))
+		rtw_p2p_set_role(pwdinfo, P2P_ROLE_DEVICE);
+
+#ifdef CONFIG_CONCURRENT_MODE
+	if (rtw_mi_check_status(padapter, MI_LINKED)) {
+		u8 union_ch = rtw_mi_get_union_chan(padapter);
+		u8 union_bw = rtw_mi_get_union_bw(padapter);
+		u8 union_offset = rtw_mi_get_union_offset(padapter);
+
+		if (rtw_p2p_chk_state(pwdinfo, P2P_STATE_TX_PROVISION_DIS_REQ) || rtw_p2p_chk_state(pwdinfo, P2P_STATE_RX_PROVISION_DIS_RSP)) {
+			set_channel_bwmode(padapter, union_ch, union_offset, union_bw);
+			rtw_back_opch(padapter);
+		}
+	}
+#endif
+
+	rtw_p2p_set_state(pwdinfo, rtw_p2p_pre_state(pwdinfo));
+
+	if (rtw_p2p_chk_role(pwdinfo, P2P_ROLE_DEVICE)) {
+#ifdef CONFIG_CONCURRENT_MODE
+		p2p_concurrent_handler(padapter);
+#else
+		/*	In the P2P client mode, the driver should not switch back to its listen channel */
+		/*	because this P2P client should stay at the operating channel of P2P GO. */
+		set_channel_bwmode(padapter, pwdinfo->listen_channel, HAL_PRIME_CHNL_OFFSET_DONT_CARE, CHANNEL_WIDTH_20);
+#endif
+	}
+}
+
+void pre_tx_invitereq_handler(_adapter	*padapter)
+{
+	struct wifidirect_info  *pwdinfo = &padapter->wdinfo;
+	u8	val8 = 1;
+
+	set_channel_bwmode(padapter, pwdinfo->invitereq_info.peer_ch, HAL_PRIME_CHNL_OFFSET_DONT_CARE, CHANNEL_WIDTH_20);
+	rtw_hal_set_hwreg(padapter, HW_VAR_MLME_SITESURVEY, (u8 *)(&val8));
+	issue_probereq_p2p(padapter, NULL);
+	_set_timer(&pwdinfo->pre_tx_scan_timer, P2P_TX_PRESCAN_TIMEOUT);
+
+}
+
+void pre_tx_provdisc_handler(_adapter	*padapter)
+{
+	struct wifidirect_info  *pwdinfo = &padapter->wdinfo;
+	u8	val8 = 1;
+
+	set_channel_bwmode(padapter, pwdinfo->tx_prov_disc_info.peer_channel_num[0], HAL_PRIME_CHNL_OFFSET_DONT_CARE, CHANNEL_WIDTH_20);
+	rtw_hal_set_hwreg(padapter, HW_VAR_MLME_SITESURVEY, (u8 *)(&val8));
+	issue_probereq_p2p(padapter, NULL);
+	_set_timer(&pwdinfo->pre_tx_scan_timer, P2P_TX_PRESCAN_TIMEOUT);
+
+}
+
+void pre_tx_negoreq_handler(_adapter	*padapter)
+{
+	struct wifidirect_info  *pwdinfo = &padapter->wdinfo;
+	u8	val8 = 1;
+
+	set_channel_bwmode(padapter, pwdinfo->nego_req_info.peer_channel_num[0], HAL_PRIME_CHNL_OFFSET_DONT_CARE, CHANNEL_WIDTH_20);
+	rtw_hal_set_hwreg(padapter, HW_VAR_MLME_SITESURVEY, (u8 *)(&val8));
+	issue_probereq_p2p(padapter , NULL);
+	/* WIN Phone only accept unicast probe request when nego back */
+	issue_probereq_p2p(padapter , pwdinfo->nego_req_info.peerDevAddr);
+	_set_timer(&pwdinfo->pre_tx_scan_timer, P2P_TX_PRESCAN_TIMEOUT);
+
+}
+
+#ifdef CONFIG_CONCURRENT_MODE
+void p2p_concurrent_handler(_adapter	*padapter)
+{
+	struct wifidirect_info	*pwdinfo = &padapter->wdinfo;
+	struct mlme_ext_priv	*pmlmeext = &(padapter->mlmeextpriv);
+	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
+	u8					val8;
+
+#ifdef CONFIG_IOCTL_CFG80211
+	if (pwdinfo->driver_interface == DRIVER_CFG80211
+		&& !rtw_cfg80211_get_is_roch(padapter))
+		return;
+#endif
+
+	if (rtw_mi_check_status(padapter, MI_LINKED)) {
+		u8 union_ch = rtw_mi_get_union_chan(padapter);
+		u8 union_bw = rtw_mi_get_union_bw(padapter);
+		u8 union_offset = rtw_mi_get_union_offset(padapter);
+
+		pwdinfo->operating_channel = union_ch;
+
+		if (pwdinfo->driver_interface == DRIVER_CFG80211) {
+			RTW_INFO("%s, switch ch back to union=%u,%u, %u\n"
+				, __func__, union_ch, union_bw, union_offset);
+			set_channel_bwmode(padapter, union_ch, union_offset, union_bw);
+			rtw_back_opch(padapter);
+
+		} else if (pwdinfo->driver_interface == DRIVER_WEXT) {
+			if (rtw_p2p_chk_state(pwdinfo, P2P_STATE_IDLE)) {
+				/*	Now, the driver stays on the AP's channel. */
+				/*	If the pwdinfo->ext_listen_period = 0, that means the P2P listen state is not available on listen channel. */
+				if (pwdinfo->ext_listen_period > 0) {
+					RTW_INFO("[%s] P2P_STATE_IDLE, ext_listen_period = %d\n", __FUNCTION__, pwdinfo->ext_listen_period);
+
+					if (union_ch != pwdinfo->listen_channel) {
+						rtw_leave_opch(padapter);
+						set_channel_bwmode(padapter, pwdinfo->listen_channel, HAL_PRIME_CHNL_OFFSET_DONT_CARE, CHANNEL_WIDTH_20);
+					}
+
+					rtw_p2p_set_state(pwdinfo, P2P_STATE_LISTEN);
+
+					if (!rtw_mi_check_mlmeinfo_state(padapter, WIFI_FW_AP_STATE)) {
+						val8 = 1;
+						rtw_hal_set_hwreg(padapter, HW_VAR_MLME_SITESURVEY, (u8 *)(&val8));
+					}
+					/*	Todo: To check the value of pwdinfo->ext_listen_period is equal to 0 or not. */
+					_set_timer(&pwdinfo->ap_p2p_switch_timer, pwdinfo->ext_listen_period);
+				}
+
+			} else if (rtw_p2p_chk_state(pwdinfo, P2P_STATE_LISTEN) ||
+				rtw_p2p_chk_state(pwdinfo, P2P_STATE_GONEGO_FAIL) ||
+				(rtw_p2p_chk_state(pwdinfo, P2P_STATE_GONEGO_ING) && pwdinfo->nego_req_info.benable == _FALSE) ||
+				rtw_p2p_chk_state(pwdinfo, P2P_STATE_RX_PROVISION_DIS_REQ)) {
+				/*	Now, the driver is in the listen state of P2P mode. */
+				RTW_INFO("[%s] P2P_STATE_IDLE, ext_listen_interval = %d\n", __FUNCTION__, pwdinfo->ext_listen_interval);
+
+				/*	Commented by Albert 2012/11/01 */
+				/*	If the AP's channel is the same as the listen channel, we should still be in the listen state */
+				/*	Other P2P device is still able to find this device out even this device is in the AP's channel. */
+				/*	So, configure this device to be able to receive the probe request frame and set it to listen state. */
+				if (union_ch != pwdinfo->listen_channel) {
+
+					set_channel_bwmode(padapter, union_ch, union_offset, union_bw);
+					if (!rtw_mi_check_status(padapter, MI_AP_MODE)) {
+						val8 = 0;
+						rtw_hal_set_hwreg(padapter, HW_VAR_MLME_SITESURVEY, (u8 *)(&val8));
+					}
+					rtw_p2p_set_state(pwdinfo, P2P_STATE_IDLE);
+					rtw_back_opch(padapter);
+				}
+
+				/*	Todo: To check the value of pwdinfo->ext_listen_interval is equal to 0 or not. */
+				_set_timer(&pwdinfo->ap_p2p_switch_timer, pwdinfo->ext_listen_interval);
+
+			} else if (rtw_p2p_chk_state(pwdinfo, P2P_STATE_GONEGO_OK)) {
+				/*	The driver had finished the P2P handshake successfully. */
+				val8 = 0;
+				rtw_hal_set_hwreg(padapter, HW_VAR_MLME_SITESURVEY, (u8 *)(&val8));
+				set_channel_bwmode(padapter, union_ch, union_offset, union_bw);
+				rtw_back_opch(padapter);
+
+			} else if (rtw_p2p_chk_state(pwdinfo, P2P_STATE_TX_PROVISION_DIS_REQ)) {
+				val8 = 1;
+				set_channel_bwmode(padapter, pwdinfo->tx_prov_disc_info.peer_channel_num[0], HAL_PRIME_CHNL_OFFSET_DONT_CARE, CHANNEL_WIDTH_20);
+				rtw_hal_set_hwreg(padapter, HW_VAR_MLME_SITESURVEY, (u8 *)(&val8));
+				issue_probereq_p2p(padapter, NULL);
+				_set_timer(&pwdinfo->pre_tx_scan_timer, P2P_TX_PRESCAN_TIMEOUT);
+			} else if (rtw_p2p_chk_state(pwdinfo, P2P_STATE_GONEGO_ING) && pwdinfo->nego_req_info.benable == _TRUE) {
+				val8 = 1;
+				set_channel_bwmode(padapter, pwdinfo->nego_req_info.peer_channel_num[0], HAL_PRIME_CHNL_OFFSET_DONT_CARE, CHANNEL_WIDTH_20);
+				rtw_hal_set_hwreg(padapter, HW_VAR_MLME_SITESURVEY, (u8 *)(&val8));
+				issue_probereq_p2p(padapter, NULL);
+				_set_timer(&pwdinfo->pre_tx_scan_timer, P2P_TX_PRESCAN_TIMEOUT);
+			} else if (rtw_p2p_chk_state(pwdinfo, P2P_STATE_TX_INVITE_REQ) && pwdinfo->invitereq_info.benable == _TRUE) {
+				/*
+				val8 = 1;
+				set_channel_bwmode(padapter, , HAL_PRIME_CHNL_OFFSET_DONT_CARE, CHANNEL_WIDTH_20);
+				rtw_hal_set_hwreg(padapter, HW_VAR_MLME_SITESURVEY, (u8 *)(&val8));
+				issue_probereq_p2p(padapter, NULL);
+				_set_timer( &pwdinfo->pre_tx_scan_timer, P2P_TX_PRESCAN_TIMEOUT );
+				*/
+			}
+		}
+	} else {
+		/* In p2p+softap. When in P2P_STATE_GONEGO_OK, not back to listen channel.*/
+		if (!rtw_p2p_chk_state(pwdinfo , P2P_STATE_GONEGO_OK) || padapter->registrypriv.full_ch_in_p2p_handshake == 0)
+			set_channel_bwmode(padapter, pwdinfo->listen_channel, HAL_PRIME_CHNL_OFFSET_DONT_CARE, CHANNEL_WIDTH_20);
+		else
+			RTW_INFO("%s, buddy not linked, go nego ok, not back to listen channel\n", __func__);
+	}
+
+}
+#endif
+
+#ifdef CONFIG_IOCTL_CFG80211
+u8 roch_stay_in_cur_chan(_adapter *padapter)
+{
+	int i;
+	_adapter *iface;
+	struct mlme_priv *pmlmepriv;
+	struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
+	u8 rst = _FALSE;
+
+	for (i = 0; i < dvobj->iface_nums; i++) {
+		iface = dvobj->padapters[i];
+		if (iface) {
+			pmlmepriv = &iface->mlmepriv;
+
+			if (check_fwstate(pmlmepriv, _FW_UNDER_LINKING | WIFI_UNDER_WPS | WIFI_UNDER_KEY_HANDSHAKE) == _TRUE) {
+				RTW_INFO(ADPT_FMT"- _FW_UNDER_LINKING |WIFI_UNDER_WPS | WIFI_UNDER_KEY_HANDSHAKE (mlme state:0x%x)\n",
+						ADPT_ARG(iface), get_fwstate(&iface->mlmepriv));
+				rst = _TRUE;
+				break;
+			}
+			#ifdef CONFIG_AP_MODE
+			if (MLME_IS_AP(iface) || MLME_IS_MESH(iface)) {
+				if (rtw_ap_sta_states_check(iface) == _TRUE) {
+					rst = _TRUE;
+					break;
+				}
+			}
+			#endif
+		}
+	}
+
+	return rst;
+}
+
+static int ro_ch_handler(_adapter *adapter, u8 *buf)
+{
+	int ret = H2C_SUCCESS;
+	struct p2p_roch_parm *roch_parm = (struct p2p_roch_parm *)buf;
+	struct rtw_wdev_priv *pwdev_priv = adapter_wdev_data(adapter);
+	struct cfg80211_wifidirect_info *pcfg80211_wdinfo = &adapter->cfg80211_wdinfo;
+#ifdef CONFIG_CONCURRENT_MODE
+	struct mlme_ext_priv *pmlmeext = &adapter->mlmeextpriv;
+#ifdef RTW_ROCH_BACK_OP
+	struct wifidirect_info *pwdinfo = &adapter->wdinfo;
+#endif
+#endif
+	u8 ready_on_channel = _FALSE;
+	u8 remain_ch;
+	unsigned int duration;
+
+	_enter_critical_mutex(&pwdev_priv->roch_mutex, NULL);
+
+	if (rtw_cfg80211_get_is_roch(adapter) != _TRUE)
+		goto exit;
+
+	remain_ch = (u8)ieee80211_frequency_to_channel(roch_parm->ch.center_freq);
+	duration = roch_parm->duration;
+
+	RTW_INFO(FUNC_ADPT_FMT" ch:%u duration:%d, cookie:0x%llx\n"
+		, FUNC_ADPT_ARG(adapter), remain_ch, roch_parm->duration, roch_parm->cookie);
+
+	if (roch_parm->wdev && roch_parm->cookie) {
+		if (pcfg80211_wdinfo->ro_ch_wdev != roch_parm->wdev) {
+			RTW_WARN(FUNC_ADPT_FMT" ongoing wdev:%p, wdev:%p\n"
+				, FUNC_ADPT_ARG(adapter), pcfg80211_wdinfo->ro_ch_wdev, roch_parm->wdev);
+			rtw_warn_on(1);
+		}
+
+		if (pcfg80211_wdinfo->remain_on_ch_cookie != roch_parm->cookie) {
+			RTW_WARN(FUNC_ADPT_FMT" ongoing cookie:0x%llx, cookie:0x%llx\n"
+				, FUNC_ADPT_ARG(adapter), pcfg80211_wdinfo->remain_on_ch_cookie, roch_parm->cookie);
+			rtw_warn_on(1);
+		}
+	}
+
+	if (roch_stay_in_cur_chan(adapter) == _TRUE) {
+		remain_ch = rtw_mi_get_union_chan(adapter);
+		RTW_INFO(FUNC_ADPT_FMT" stay in union ch:%d\n", FUNC_ADPT_ARG(adapter), remain_ch);
+	}
+
+	#ifdef CONFIG_CONCURRENT_MODE
+	if (rtw_mi_check_status(adapter, MI_LINKED) && (0 != rtw_mi_get_union_chan(adapter))) {
+		if ((remain_ch != rtw_mi_get_union_chan(adapter)) && !check_fwstate(&adapter->mlmepriv, _FW_LINKED)) {
+			if (remain_ch != pmlmeext->cur_channel
+				#ifdef RTW_ROCH_BACK_OP
+				|| ATOMIC_READ(&pwdev_priv->switch_ch_to) == 1
+				#endif
+			) {
+				rtw_leave_opch(adapter);
+
+				#ifdef RTW_ROCH_BACK_OP
+				RTW_INFO("%s, set switch ch timer, duration=%d\n", __func__, duration - pwdinfo->ext_listen_interval);
+				ATOMIC_SET(&pwdev_priv->switch_ch_to, 0);
+				_set_timer(&pwdinfo->ap_p2p_switch_timer, duration - pwdinfo->ext_listen_interval);
+				#endif
+			}
+		}
+		ready_on_channel = _TRUE;
+	} else
+	#endif /* CONFIG_CONCURRENT_MODE */
+	{
+		if (remain_ch != rtw_get_oper_ch(adapter))
+			ready_on_channel = _TRUE;
+	}
+
+	if (ready_on_channel == _TRUE) {
+		#ifndef RTW_SINGLE_WIPHY
+		if (!check_fwstate(&adapter->mlmepriv, _FW_LINKED))
+		#endif
+		{
+			#ifdef CONFIG_CONCURRENT_MODE
+			if (rtw_get_oper_ch(adapter) != remain_ch)
+			#endif
+			{
+				/* if (!padapter->mlmepriv.LinkDetectInfo.bBusyTraffic) */
+				set_channel_bwmode(adapter, remain_ch, HAL_PRIME_CHNL_OFFSET_DONT_CARE, CHANNEL_WIDTH_20);
+			}
+		}
+	}
+
+	#ifdef CONFIG_BT_COEXIST
+	rtw_btcoex_ScanNotify(adapter, _TRUE);
+	#endif
+
+	RTW_INFO("%s, set ro ch timer, duration=%d\n", __func__, duration);
+	_set_timer(&pcfg80211_wdinfo->remain_on_ch_timer, duration);
+
+exit:
+	_exit_critical_mutex(&pwdev_priv->roch_mutex, NULL);
+
+	return ret;
+}
+
+static int cancel_ro_ch_handler(_adapter *padapter, u8 *buf)
+{
+	int ret = H2C_SUCCESS;
+	struct p2p_roch_parm *roch_parm = (struct p2p_roch_parm *)buf;
+	struct rtw_wdev_priv *pwdev_priv = adapter_wdev_data(padapter);
+	struct cfg80211_wifidirect_info *pcfg80211_wdinfo = &padapter->cfg80211_wdinfo;
+	struct wireless_dev *wdev;
+	struct wifidirect_info *pwdinfo = &padapter->wdinfo;
+	u8 ch, bw, offset;
+
+	_enter_critical_mutex(&pwdev_priv->roch_mutex, NULL);
+
+	if (rtw_cfg80211_get_is_roch(padapter) != _TRUE)
+		goto exit;
+
+	if (roch_parm->wdev && roch_parm->cookie) {
+		if (pcfg80211_wdinfo->ro_ch_wdev != roch_parm->wdev) {
+			RTW_WARN(FUNC_ADPT_FMT" ongoing wdev:%p, wdev:%p\n"
+				, FUNC_ADPT_ARG(padapter), pcfg80211_wdinfo->ro_ch_wdev, roch_parm->wdev);
+			rtw_warn_on(1);
+		}
+
+		if (pcfg80211_wdinfo->remain_on_ch_cookie != roch_parm->cookie) {
+			RTW_WARN(FUNC_ADPT_FMT" ongoing cookie:0x%llx, cookie:0x%llx\n"
+				, FUNC_ADPT_ARG(padapter), pcfg80211_wdinfo->remain_on_ch_cookie, roch_parm->cookie);
+			rtw_warn_on(1);
+		}
+	}
+
+#if defined(RTW_ROCH_BACK_OP) && defined(CONFIG_CONCURRENT_MODE)
+	_cancel_timer_ex(&pwdinfo->ap_p2p_switch_timer);
+	ATOMIC_SET(&pwdev_priv->switch_ch_to, 1);
+#endif
+
+	if (rtw_mi_get_ch_setting_union(padapter, &ch, &bw, &offset) != 0) {
+		if (0)
+			RTW_INFO(FUNC_ADPT_FMT" back to linked/linking union - ch:%u, bw:%u, offset:%u\n",
+				 FUNC_ADPT_ARG(padapter), ch, bw, offset);
+	} else if (adapter_wdev_data(padapter)->p2p_enabled && pwdinfo->listen_channel) {
+		ch = pwdinfo->listen_channel;
+		bw = CHANNEL_WIDTH_20;
+		offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
+		if (0)
+			RTW_INFO(FUNC_ADPT_FMT" back to listen ch - ch:%u, bw:%u, offset:%u\n",
+				 FUNC_ADPT_ARG(padapter), ch, bw, offset);
+	} else {
+		ch = pcfg80211_wdinfo->restore_channel;
+		bw = CHANNEL_WIDTH_20;
+		offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
+		if (0)
+			RTW_INFO(FUNC_ADPT_FMT" back to restore ch - ch:%u, bw:%u, offset:%u\n",
+				 FUNC_ADPT_ARG(padapter), ch, bw, offset);
+	}
+
+	set_channel_bwmode(padapter, ch, offset, bw);
+	rtw_back_opch(padapter);
+
+	rtw_p2p_set_state(pwdinfo, rtw_p2p_pre_state(pwdinfo));
+#ifdef CONFIG_DEBUG_CFG80211
+	RTW_INFO("%s, role=%d, p2p_state=%d\n", __func__, rtw_p2p_role(pwdinfo), rtw_p2p_state(pwdinfo));
+#endif
+
+	wdev = pcfg80211_wdinfo->ro_ch_wdev;
+
+	rtw_cfg80211_set_is_roch(padapter, _FALSE);
+	pcfg80211_wdinfo->ro_ch_wdev = NULL;
+	rtw_cfg80211_set_last_ro_ch_time(padapter);
+
+	rtw_cfg80211_remain_on_channel_expired(wdev
+		, pcfg80211_wdinfo->remain_on_ch_cookie
+		, &pcfg80211_wdinfo->remain_on_ch_channel
+		, pcfg80211_wdinfo->remain_on_ch_type, GFP_KERNEL);
+
+	RTW_INFO("cfg80211_remain_on_channel_expired cookie:0x%llx\n"
+		, pcfg80211_wdinfo->remain_on_ch_cookie);
+
+#ifdef CONFIG_BT_COEXIST
+	rtw_btcoex_ScanNotify(padapter, _FALSE);
+#endif
+
+exit:
+	_exit_critical_mutex(&pwdev_priv->roch_mutex, NULL);
+
+	return ret;
+}
+
+static void ro_ch_timer_process(void *FunctionContext)
+{
+	_adapter *adapter = (_adapter *)FunctionContext;
+
+	p2p_cancel_roch_cmd(adapter, 0, NULL, 0);
+}
+
+#if 0
+static void rtw_change_p2pie_op_ch(_adapter *padapter, const u8 *frame_body, u32 len, u8 ch)
+{
+	u8 *ies, *p2p_ie;
+	u32 ies_len, p2p_ielen;
+
+#ifdef CONFIG_MCC_MODE
+	if (MCC_EN(padapter))
+		return;
+#endif /* CONFIG_MCC_MODE */
+
+	ies = (u8 *)(frame_body + _PUBLIC_ACTION_IE_OFFSET_);
+	ies_len = len - _PUBLIC_ACTION_IE_OFFSET_;
+
+	p2p_ie = rtw_get_p2p_ie(ies, ies_len, NULL, &p2p_ielen);
+
+	while (p2p_ie) {
+		u32	attr_contentlen = 0;
+		u8 *pattr = NULL;
+
+		/* Check P2P_ATTR_OPERATING_CH */
+		attr_contentlen = 0;
+		pattr = NULL;
+		pattr = rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_OPERATING_CH, NULL, (uint *)&attr_contentlen);
+		if (pattr != NULL)
+			*(pattr + 4) = ch;
+
+		/* Get the next P2P IE */
+		p2p_ie = rtw_get_p2p_ie(p2p_ie + p2p_ielen, ies_len - (p2p_ie - ies + p2p_ielen), NULL, &p2p_ielen);
+	}
+}
+#endif
+
+#if defined(CONFIG_CONCURRENT_MODE) && defined(CONFIG_CFG80211_ONECHANNEL_UNDER_CONCURRENT)
+static void rtw_change_p2pie_ch_list(_adapter *padapter, const u8 *frame_body, u32 len, u8 ch)
+{
+	u8 *ies, *p2p_ie;
+	u32 ies_len, p2p_ielen;
+
+#ifdef CONFIG_MCC_MODE
+	if (MCC_EN(padapter))
+		return;
+#endif /* CONFIG_MCC_MODE */
+
+	ies = (u8 *)(frame_body + _PUBLIC_ACTION_IE_OFFSET_);
+	ies_len = len - _PUBLIC_ACTION_IE_OFFSET_;
+
+	p2p_ie = rtw_get_p2p_ie(ies, ies_len, NULL, &p2p_ielen);
+
+	while (p2p_ie) {
+		u32	attr_contentlen = 0;
+		u8 *pattr = NULL;
+
+		/* Check P2P_ATTR_CH_LIST */
+		pattr = rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_CH_LIST, NULL, (uint *)&attr_contentlen);
+		if (pattr != NULL) {
+			int i;
+			u32 num_of_ch;
+			u8 *pattr_temp = pattr + 3 ;
+
+			attr_contentlen -= 3;
+
+			while (attr_contentlen > 0) {
+				num_of_ch = *(pattr_temp + 1);
+
+				for (i = 0; i < num_of_ch; i++)
+					*(pattr_temp + 2 + i) = ch;
+
+				pattr_temp += (2 + num_of_ch);
+				attr_contentlen -= (2 + num_of_ch);
+			}
+		}
+
+		/* Get the next P2P IE */
+		p2p_ie = rtw_get_p2p_ie(p2p_ie + p2p_ielen, ies_len - (p2p_ie - ies + p2p_ielen), NULL, &p2p_ielen);
+	}
+}
+#endif
+
+#if defined(CONFIG_CONCURRENT_MODE) && defined(CONFIG_CFG80211_ONECHANNEL_UNDER_CONCURRENT)
+static bool rtw_chk_p2pie_ch_list_with_buddy(_adapter *padapter, const u8 *frame_body, u32 len)
+{
+	bool fit = _FALSE;
+	u8 *ies, *p2p_ie;
+	u32 ies_len, p2p_ielen;
+	u8 union_ch = rtw_mi_get_union_chan(padapter);
+
+	ies = (u8 *)(frame_body + _PUBLIC_ACTION_IE_OFFSET_);
+	ies_len = len - _PUBLIC_ACTION_IE_OFFSET_;
+
+	p2p_ie = rtw_get_p2p_ie(ies, ies_len, NULL, &p2p_ielen);
+
+	while (p2p_ie) {
+		u32	attr_contentlen = 0;
+		u8 *pattr = NULL;
+
+		/* Check P2P_ATTR_CH_LIST */
+		pattr = rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_CH_LIST, NULL, (uint *)&attr_contentlen);
+		if (pattr != NULL) {
+			int i;
+			u32 num_of_ch;
+			u8 *pattr_temp = pattr + 3 ;
+
+			attr_contentlen -= 3;
+
+			while (attr_contentlen > 0) {
+				num_of_ch = *(pattr_temp + 1);
+
+				for (i = 0; i < num_of_ch; i++) {
+					if (*(pattr_temp + 2 + i) == union_ch) {
+						RTW_INFO(FUNC_ADPT_FMT" ch_list fit buddy_ch:%u\n", FUNC_ADPT_ARG(padapter), union_ch);
+						fit = _TRUE;
+						break;
+					}
+				}
+
+				pattr_temp += (2 + num_of_ch);
+				attr_contentlen -= (2 + num_of_ch);
+			}
+		}
+
+		/* Get the next P2P IE */
+		p2p_ie = rtw_get_p2p_ie(p2p_ie + p2p_ielen, ies_len - (p2p_ie - ies + p2p_ielen), NULL, &p2p_ielen);
+	}
+
+	return fit;
+}
+
+#if defined(CONFIG_P2P_INVITE_IOT)
+static bool rtw_chk_p2pie_op_ch_with_buddy(_adapter *padapter, const u8 *frame_body, u32 len)
+{
+	bool fit = _FALSE;
+	u8 *ies, *p2p_ie;
+	u32 ies_len, p2p_ielen;
+	u8 union_ch = rtw_mi_get_union_chan(padapter);
+
+	ies = (u8 *)(frame_body + _PUBLIC_ACTION_IE_OFFSET_);
+	ies_len = len - _PUBLIC_ACTION_IE_OFFSET_;
+
+	p2p_ie = rtw_get_p2p_ie(ies, ies_len, NULL, &p2p_ielen);
+
+	while (p2p_ie) {
+		u32	attr_contentlen = 0;
+		u8 *pattr = NULL;
+
+		/* Check P2P_ATTR_OPERATING_CH */
+		attr_contentlen = 0;
+		pattr = NULL;
+		pattr = rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_OPERATING_CH, NULL, (uint *)&attr_contentlen);
+		if (pattr != NULL) {
+			if (*(pattr + 4) == union_ch) {
+				RTW_INFO(FUNC_ADPT_FMT" op_ch fit buddy_ch:%u\n", FUNC_ADPT_ARG(padapter), union_ch);
+				fit = _TRUE;
+				break;
+			}
+		}
+
+		/* Get the next P2P IE */
+		p2p_ie = rtw_get_p2p_ie(p2p_ie + p2p_ielen, ies_len - (p2p_ie - ies + p2p_ielen), NULL, &p2p_ielen);
+	}
+
+	return fit;
+}
+#endif
+
+static void rtw_cfg80211_adjust_p2pie_channel(_adapter *padapter, const u8 *frame_body, u32 len)
+{
+	u8 *ies, *p2p_ie;
+	u32 ies_len, p2p_ielen;
+	u8 union_ch = rtw_mi_get_union_chan(padapter);
+
+#ifdef CONFIG_MCC_MODE
+	if (MCC_EN(padapter))
+		return;
+#endif /* CONFIG_MCC_MODE */
+
+	ies = (u8 *)(frame_body + _PUBLIC_ACTION_IE_OFFSET_);
+	ies_len = len - _PUBLIC_ACTION_IE_OFFSET_;
+
+	p2p_ie = rtw_get_p2p_ie(ies, ies_len, NULL, &p2p_ielen);
+
+	while (p2p_ie) {
+		u32	attr_contentlen = 0;
+		u8 *pattr = NULL;
+
+		/* Check P2P_ATTR_CH_LIST */
+		pattr = rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_CH_LIST, NULL, (uint *)&attr_contentlen);
+		if (pattr != NULL) {
+			int i;
+			u32 num_of_ch;
+			u8 *pattr_temp = pattr + 3 ;
+
+			attr_contentlen -= 3;
+
+			while (attr_contentlen > 0) {
+				num_of_ch = *(pattr_temp + 1);
+
+				for (i = 0; i < num_of_ch; i++) {
+					if (*(pattr_temp + 2 + i) && *(pattr_temp + 2 + i) != union_ch) {
+						#ifdef RTW_SINGLE_WIPHY
+						RTW_ERR("replace ch_list:%u with:%u\n", *(pattr_temp + 2 + i), union_ch);
+						#endif
+						*(pattr_temp + 2 + i) = union_ch; /*forcing to the same channel*/
+					}
+				}
+
+				pattr_temp += (2 + num_of_ch);
+				attr_contentlen -= (2 + num_of_ch);
+			}
+		}
+
+		/* Check P2P_ATTR_OPERATING_CH */
+		attr_contentlen = 0;
+		pattr = NULL;
+		pattr = rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_OPERATING_CH, NULL, (uint *)&attr_contentlen);
+		if (pattr != NULL) {
+			if (*(pattr + 4) && *(pattr + 4) != union_ch) {
+				#ifdef RTW_SINGLE_WIPHY
+				RTW_ERR("replace op_ch:%u with:%u\n", *(pattr + 4), union_ch);
+				#endif
+				*(pattr + 4) = union_ch; /*forcing to the same channel	*/
+			}
+		}
+
+		/* Get the next P2P IE */
+		p2p_ie = rtw_get_p2p_ie(p2p_ie + p2p_ielen, ies_len - (p2p_ie - ies + p2p_ielen), NULL, &p2p_ielen);
+
+	}
+
+}
+#endif
+
+#ifdef CONFIG_WFD
+u32 rtw_xframe_build_wfd_ie(struct xmit_frame *xframe)
+{
+	_adapter *adapter = xframe->padapter;
+	struct wifidirect_info *wdinfo = &adapter->wdinfo;
+	u8 *frame = xframe->buf_addr + TXDESC_OFFSET;
+	u8 *frame_body = frame + sizeof(struct rtw_ieee80211_hdr_3addr);
+	u8 *frame_tail = frame + xframe->attrib.pktlen;
+	u8 category, action, OUI_Subtype, dialogToken = 0;
+	u32	wfdielen = 0;
+
+	category = frame_body[0];
+	if (category == RTW_WLAN_CATEGORY_PUBLIC) {
+		action = frame_body[1];
+		if (action == ACT_PUBLIC_VENDOR
+		    && _rtw_memcmp(frame_body + 2, P2P_OUI, 4) == _TRUE
+		   ) {
+			OUI_Subtype = frame_body[6];
+			dialogToken = frame_body[7];
+
+			switch (OUI_Subtype) {
+			case P2P_GO_NEGO_REQ:
+				wfdielen = build_nego_req_wfd_ie(wdinfo, frame_tail);
+				break;
+			case P2P_GO_NEGO_RESP:
+				wfdielen = build_nego_resp_wfd_ie(wdinfo, frame_tail);
+				break;
+			case P2P_GO_NEGO_CONF:
+				wfdielen = build_nego_confirm_wfd_ie(wdinfo, frame_tail);
+				break;
+			case P2P_INVIT_REQ:
+				wfdielen = build_invitation_req_wfd_ie(wdinfo, frame_tail);
+				break;
+			case P2P_INVIT_RESP:
+				wfdielen = build_invitation_resp_wfd_ie(wdinfo, frame_tail);
+				break;
+			case P2P_PROVISION_DISC_REQ:
+				wfdielen = build_provdisc_req_wfd_ie(wdinfo, frame_tail);
+				break;
+			case P2P_PROVISION_DISC_RESP:
+				wfdielen = build_provdisc_resp_wfd_ie(wdinfo, frame_tail);
+				break;
+			case P2P_DEVDISC_REQ:
+			case P2P_DEVDISC_RESP:
+			default:
+				break;
+			}
+
+		}
+	} else if (category == RTW_WLAN_CATEGORY_P2P) {
+		OUI_Subtype = frame_body[5];
+		dialogToken = frame_body[6];
+
+#ifdef CONFIG_DEBUG_CFG80211
+		RTW_INFO("ACTION_CATEGORY_P2P: OUI=0x%x, OUI_Subtype=%d, dialogToken=%d\n"
+			, cpu_to_be32(*((u32 *)(frame_body + 1))), OUI_Subtype, dialogToken);
+#endif
+
+		switch (OUI_Subtype) {
+		case P2P_NOTICE_OF_ABSENCE:
+			break;
+		case P2P_PRESENCE_REQUEST:
+			break;
+		case P2P_PRESENCE_RESPONSE:
+			break;
+		case P2P_GO_DISC_REQUEST:
+			break;
+		default:
+			break;
+		}
+	} else
+		RTW_INFO("%s, action frame category=%d\n", __func__, category);
+
+	xframe->attrib.pktlen += wfdielen;
+
+	return wfdielen;
+}
+#endif /* CONFIG_WFD */
+
+bool rtw_xframe_del_wfd_ie(struct xmit_frame *xframe)
+{
+#define DBG_XFRAME_DEL_WFD_IE 0
+	u8 *frame = xframe->buf_addr + TXDESC_OFFSET;
+	u8 *frame_body = frame + sizeof(struct rtw_ieee80211_hdr_3addr);
+	u8 *frame_tail = frame + xframe->attrib.pktlen;
+	u8 category, action, OUI_Subtype;
+	u8 *ies = NULL;
+	uint ies_len_ori = 0;
+	uint ies_len = 0;
+
+	category = frame_body[0];
+	if (category == RTW_WLAN_CATEGORY_PUBLIC) {
+		action = frame_body[1];
+		if (action == ACT_PUBLIC_VENDOR
+		    && _rtw_memcmp(frame_body + 2, P2P_OUI, 4) == _TRUE
+		   ) {
+			OUI_Subtype = frame_body[6];
+
+			switch (OUI_Subtype) {
+			case P2P_GO_NEGO_REQ:
+			case P2P_GO_NEGO_RESP:
+			case P2P_GO_NEGO_CONF:
+			case P2P_INVIT_REQ:
+			case P2P_INVIT_RESP:
+			case P2P_PROVISION_DISC_REQ:
+			case P2P_PROVISION_DISC_RESP:
+				ies = frame_body + 8;
+				ies_len_ori = frame_tail - (frame_body + 8);
+				break;
+			}
+		}
+	}
+
+	if (ies && ies_len_ori) {
+		ies_len = rtw_del_wfd_ie(ies, ies_len_ori, DBG_XFRAME_DEL_WFD_IE ? __func__ : NULL);
+		xframe->attrib.pktlen -= (ies_len_ori - ies_len);
+	}
+
+	return ies_len_ori != ies_len;
+}
+
+/*
+* rtw_xframe_chk_wfd_ie -
+*
+*/
+void rtw_xframe_chk_wfd_ie(struct xmit_frame *xframe)
+{
+	_adapter *adapter = xframe->padapter;
+#ifdef CONFIG_IOCTL_CFG80211
+	struct wifidirect_info *wdinfo = &adapter->wdinfo;
+#endif
+	u8 build = 0;
+	u8 del = 0;
+
+	if (!hal_chk_wl_func(adapter, WL_FUNC_MIRACAST))
+		del = 1;
+
+#ifdef CONFIG_IOCTL_CFG80211
+	if (wdinfo->wfd_info->wfd_enable == _TRUE)
+#endif
+		del = build = 1;
+
+	if (del)
+		rtw_xframe_del_wfd_ie(xframe);
+
+#ifdef CONFIG_WFD
+	if (build)
+		rtw_xframe_build_wfd_ie(xframe);
+#endif
+}
+
+u8 *dump_p2p_attr_ch_list(u8 *p2p_ie, uint p2p_ielen, u8 *buf, u32 buf_len)
+{
+	uint attr_contentlen = 0;
+	u8 *pattr = NULL;
+	int w_sz = 0;
+	u8 ch_cnt = 0;
+	u8 ch_list[40];
+
+	pattr = rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_CH_LIST, NULL, &attr_contentlen);
+	if (pattr != NULL) {
+		int i, j;
+		u32 num_of_ch;
+		u8 *pattr_temp = pattr + 3 ;
+
+		attr_contentlen -= 3;
+
+		_rtw_memset(ch_list, 0, 40);
+
+		while (attr_contentlen > 0) {
+			num_of_ch = *(pattr_temp + 1);
+
+			for (i = 0; i < num_of_ch; i++) {
+				for (j = 0; j < ch_cnt; j++) {
+					if (ch_list[j] == *(pattr_temp + 2 + i))
+						break;
+				}
+				if (j >= ch_cnt)
+					ch_list[ch_cnt++] = *(pattr_temp + 2 + i);
+
+			}
+
+			pattr_temp += (2 + num_of_ch);
+			attr_contentlen -= (2 + num_of_ch);
+		}
+
+		for (j = 0; j < ch_cnt; j++) {
+			if (j == 0)
+				w_sz += snprintf(buf + w_sz, buf_len - w_sz, "%u", ch_list[j]);
+			else if (ch_list[j] - ch_list[j - 1] != 1)
+				w_sz += snprintf(buf + w_sz, buf_len - w_sz, ", %u", ch_list[j]);
+			else if (j != ch_cnt - 1 && ch_list[j + 1] - ch_list[j] == 1) {
+				/* empty */
+			} else
+				w_sz += snprintf(buf + w_sz, buf_len - w_sz, "-%u", ch_list[j]);
+		}
+	}
+	return buf;
+}
+
+/*
+ * return _TRUE if requester is GO, _FALSE if responder is GO
+ */
+bool rtw_p2p_nego_intent_compare(u8 req, u8 resp)
+{
+	if (req >> 1 == resp >> 1)
+		return  req & 0x01 ? _TRUE : _FALSE;
+	else if (req >> 1 > resp >> 1)
+		return _TRUE;
+	else
+		return _FALSE;
+}
+
+int rtw_p2p_check_frames(_adapter *padapter, const u8 *buf, u32 len, u8 tx)
+{
+	int is_p2p_frame = (-1);
+	unsigned char	*frame_body;
+	u8 category, action, OUI_Subtype, dialogToken = 0;
+	u8 *p2p_ie = NULL;
+	uint p2p_ielen = 0;
+	struct rtw_wdev_priv *pwdev_priv = adapter_wdev_data(padapter);
+	int status = -1;
+	u8 ch_list_buf[128] = {'\0'};
+	int op_ch = -1;
+	int listen_ch = -1;
+	u8 intent = 0;
+	u8 *iaddr = NULL;
+	u8 *gbssid = NULL;
+
+	frame_body = (unsigned char *)(buf + sizeof(struct rtw_ieee80211_hdr_3addr));
+	category = frame_body[0];
+	/* just for check */
+	if (category == RTW_WLAN_CATEGORY_PUBLIC) {
+		action = frame_body[1];
+		if (action == ACT_PUBLIC_VENDOR
+			&& _rtw_memcmp(frame_body + 2, P2P_OUI, 4) == _TRUE
+		) {
+			OUI_Subtype = frame_body[6];
+			dialogToken = frame_body[7];
+			is_p2p_frame = OUI_Subtype;
+
+			#ifdef CONFIG_DEBUG_CFG80211
+			RTW_INFO("ACTION_CATEGORY_PUBLIC: ACT_PUBLIC_VENDOR, OUI=0x%x, OUI_Subtype=%d, dialogToken=%d\n",
+				cpu_to_be32(*((u32 *)(frame_body + 2))), OUI_Subtype, dialogToken);
+			#endif
+
+			p2p_ie = rtw_get_p2p_ie(
+				(u8 *)buf + sizeof(struct rtw_ieee80211_hdr_3addr) + _PUBLIC_ACTION_IE_OFFSET_
+				, len - sizeof(struct rtw_ieee80211_hdr_3addr) - _PUBLIC_ACTION_IE_OFFSET_
+				, NULL, &p2p_ielen);
+
+			switch (OUI_Subtype) { /* OUI Subtype */
+				u8 *cont;
+				uint cont_len;
+			case P2P_GO_NEGO_REQ: {
+				struct rtw_wdev_nego_info *nego_info = &pwdev_priv->nego_info;
+
+				if (tx) {
+					#ifdef CONFIG_DRV_ISSUE_PROV_REQ /* IOT FOR S2 */
+					if (pwdev_priv->provdisc_req_issued == _FALSE)
+						rtw_cfg80211_issue_p2p_provision_request(padapter, buf, len);
+					#endif /* CONFIG_DRV_ISSUE_PROV_REQ */
+
+					/* pwdev_priv->provdisc_req_issued = _FALSE; */
+
+					#if defined(CONFIG_CONCURRENT_MODE) && defined(CONFIG_CFG80211_ONECHANNEL_UNDER_CONCURRENT)
+					if (rtw_mi_check_status(padapter, MI_LINKED) && padapter->registrypriv.full_ch_in_p2p_handshake == 0)
+						rtw_cfg80211_adjust_p2pie_channel(padapter, frame_body, len - sizeof(struct rtw_ieee80211_hdr_3addr));
+					#endif
+				}
+
+				cont = rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_OPERATING_CH, NULL, &cont_len);
+				if (cont)
+					op_ch = *(cont + 4);
+				cont = rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_LISTEN_CH, NULL, &cont_len);
+				if (cont)
+					listen_ch = *(cont + 4);
+				cont = rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_GO_INTENT, NULL, &cont_len);
+				if (cont)
+					intent = *cont;
+				cont = rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_INTENDED_IF_ADDR, NULL, &cont_len);
+				if (cont && cont_len == 6)
+					iaddr = cont;
+
+				if (nego_info->token != dialogToken)
+					rtw_wdev_nego_info_init(nego_info);
+
+				_rtw_memcpy(nego_info->peer_mac, tx ? GetAddr1Ptr(buf) : get_addr2_ptr(buf), ETH_ALEN);
+				if (iaddr)
+					_rtw_memcpy(tx ? nego_info->iface_addr : nego_info->peer_iface_addr, iaddr, ETH_ALEN);
+				nego_info->active = tx ? 1 : 0;
+				nego_info->token = dialogToken;
+				nego_info->req_op_ch = op_ch;
+				nego_info->req_listen_ch = listen_ch;
+				nego_info->req_intent = intent;
+				nego_info->state = 0;
+
+				dump_p2p_attr_ch_list(p2p_ie, p2p_ielen, ch_list_buf, 128);
+				RTW_INFO("RTW_%s:P2P_GO_NEGO_REQ, dialogToken=%d, intent:%u%s, listen_ch:%d, op_ch:%d, ch_list:%s"
+					, (tx == _TRUE) ? "Tx" : "Rx" , dialogToken , (intent >> 1) , intent & 0x1 ? "+" : "-" , listen_ch , op_ch , ch_list_buf);
+				if (iaddr)
+					_RTW_INFO(", iaddr:"MAC_FMT, MAC_ARG(iaddr));
+				_RTW_INFO("\n");
+
+				if (!tx) {
+					#if defined(CONFIG_CONCURRENT_MODE) && defined(CONFIG_CFG80211_ONECHANNEL_UNDER_CONCURRENT)
+					if (rtw_mi_check_status(padapter, MI_LINKED)
+					    && rtw_chk_p2pie_ch_list_with_buddy(padapter, frame_body, len - sizeof(struct rtw_ieee80211_hdr_3addr)) == _FALSE
+					    && padapter->registrypriv.full_ch_in_p2p_handshake == 0) {
+						RTW_INFO(FUNC_ADPT_FMT" ch_list has no intersect with buddy\n", FUNC_ADPT_ARG(padapter));
+						rtw_change_p2pie_ch_list(padapter, frame_body, len - sizeof(struct rtw_ieee80211_hdr_3addr), 0);
+					}
+					#endif
+				}
+
+				break;
+			}
+			case P2P_GO_NEGO_RESP: {
+				struct rtw_wdev_nego_info *nego_info = &pwdev_priv->nego_info;
+
+				if (tx) {
+					#if defined(CONFIG_CONCURRENT_MODE) && defined(CONFIG_CFG80211_ONECHANNEL_UNDER_CONCURRENT)
+					if (rtw_mi_check_status(padapter, MI_LINKED) && padapter->registrypriv.full_ch_in_p2p_handshake == 0)
+						rtw_cfg80211_adjust_p2pie_channel(padapter, frame_body, len - sizeof(struct rtw_ieee80211_hdr_3addr));
+					#endif
+				}
+
+				cont = rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_OPERATING_CH, NULL, &cont_len);
+				if (cont)
+					op_ch = *(cont + 4);
+				cont = rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_GO_INTENT, NULL, &cont_len);
+				if (cont)
+					intent = *cont;
+				cont = rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_STATUS, NULL, &cont_len);
+				if (cont)
+					status = *cont;
+				cont = rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_INTENDED_IF_ADDR, NULL, &cont_len);
+				if (cont && cont_len == 6)
+					iaddr = cont;
+
+				if (nego_info->token == dialogToken && nego_info->state == 0
+					&& _rtw_memcmp(nego_info->peer_mac, tx ? GetAddr1Ptr(buf) : get_addr2_ptr(buf), ETH_ALEN) == _TRUE
+				) {
+					if (iaddr)
+						_rtw_memcpy(tx ? nego_info->iface_addr : nego_info->peer_iface_addr, iaddr, ETH_ALEN);
+					nego_info->status = (status == -1) ? 0xff : status;
+					nego_info->rsp_op_ch = op_ch;
+					nego_info->rsp_intent = intent;
+					nego_info->state = 1;
+					if (status != 0)
+						nego_info->token = 0; /* init */
+				}
+
+				dump_p2p_attr_ch_list(p2p_ie, p2p_ielen, ch_list_buf, 128);
+				RTW_INFO("RTW_%s:P2P_GO_NEGO_RESP, dialogToken=%d, intent:%u%s, status:%d, op_ch:%d, ch_list:%s"
+					, (tx == _TRUE) ? "Tx" : "Rx", dialogToken, (intent >> 1), intent & 0x1 ? "+" : "-", status, op_ch, ch_list_buf);
+				if (iaddr)
+					_RTW_INFO(", iaddr:"MAC_FMT, MAC_ARG(iaddr));
+				_RTW_INFO("\n");
+
+				if (!tx) {
+					pwdev_priv->provdisc_req_issued = _FALSE;
+					#if defined(CONFIG_CONCURRENT_MODE) && defined(CONFIG_CFG80211_ONECHANNEL_UNDER_CONCURRENT)
+					if (rtw_mi_check_status(padapter, MI_LINKED)
+					    && rtw_chk_p2pie_ch_list_with_buddy(padapter, frame_body, len - sizeof(struct rtw_ieee80211_hdr_3addr)) == _FALSE
+					    && padapter->registrypriv.full_ch_in_p2p_handshake == 0) {
+						RTW_INFO(FUNC_ADPT_FMT" ch_list has no intersect with buddy\n", FUNC_ADPT_ARG(padapter));
+						rtw_change_p2pie_ch_list(padapter, frame_body, len - sizeof(struct rtw_ieee80211_hdr_3addr), 0);
+					}
+					#endif
+				}
+
+				break;
+			}
+			case P2P_GO_NEGO_CONF: {
+				struct rtw_wdev_nego_info *nego_info = &pwdev_priv->nego_info;
+				bool is_go = _FALSE;
+
+				if (tx) {
+					#if defined(CONFIG_CONCURRENT_MODE) && defined(CONFIG_CFG80211_ONECHANNEL_UNDER_CONCURRENT)
+					if (rtw_mi_check_status(padapter, MI_LINKED) && padapter->registrypriv.full_ch_in_p2p_handshake == 0)
+						rtw_cfg80211_adjust_p2pie_channel(padapter, frame_body, len - sizeof(struct rtw_ieee80211_hdr_3addr));
+					#endif
+				}
+
+				cont = rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_OPERATING_CH, NULL, &cont_len);
+				if (cont)
+					op_ch = *(cont + 4);
+				cont = rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_STATUS, NULL, &cont_len);
+				if (cont)
+					status = *cont;
+
+				if (nego_info->token == dialogToken && nego_info->state == 1
+				    && _rtw_memcmp(nego_info->peer_mac, tx ? GetAddr1Ptr(buf) : get_addr2_ptr(buf), ETH_ALEN) == _TRUE
+				   ) {
+					nego_info->status = (status == -1) ? 0xff : status;
+					nego_info->conf_op_ch = (op_ch == -1) ? 0 : op_ch;
+					nego_info->state = 2;
+
+					if (status == 0) {
+						if (rtw_p2p_nego_intent_compare(nego_info->req_intent, nego_info->rsp_intent) ^ !tx)
+							is_go = _TRUE;
+					}
+
+					nego_info->token = 0; /* init */
+				}
+
+				dump_p2p_attr_ch_list(p2p_ie, p2p_ielen, ch_list_buf, 128);
+				RTW_INFO("RTW_%s:P2P_GO_NEGO_CONF, dialogToken=%d, status:%d, op_ch:%d, ch_list:%s\n"
+					, (tx == _TRUE) ? "Tx" : "Rx", dialogToken, status, op_ch, ch_list_buf);
+
+				if (!tx) {
+				}
+
+				break;
+			}
+			case P2P_INVIT_REQ: {
+				struct rtw_wdev_invit_info *invit_info = &pwdev_priv->invit_info;
+				int flags = -1;
+
+				if (tx) {
+					#if defined(CONFIG_CONCURRENT_MODE) && defined(CONFIG_CFG80211_ONECHANNEL_UNDER_CONCURRENT)
+					if (rtw_mi_check_status(padapter, MI_LINKED)
+					    && padapter->registrypriv.full_ch_in_p2p_handshake == 0)
+						rtw_cfg80211_adjust_p2pie_channel(padapter, frame_body, len - sizeof(struct rtw_ieee80211_hdr_3addr));
+					#endif
+				}
+
+				cont = rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_INVITATION_FLAGS, NULL, &cont_len);
+				if (cont)
+					flags = *cont;
+				cont = rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_OPERATING_CH, NULL, &cont_len);
+				if (cont)
+					op_ch = *(cont + 4);
+				cont = rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_GROUP_BSSID, NULL, &cont_len);
+				if (cont && cont_len == 6)
+					gbssid = cont;
+
+				if (invit_info->token != dialogToken)
+					rtw_wdev_invit_info_init(invit_info);
+
+				_rtw_memcpy(invit_info->peer_mac, tx ? GetAddr1Ptr(buf) : get_addr2_ptr(buf), ETH_ALEN);
+				if (gbssid)
+					_rtw_memcpy(invit_info->group_bssid, gbssid, ETH_ALEN);
+				invit_info->active = tx ? 1 : 0;
+				invit_info->token = dialogToken;
+				invit_info->flags = (flags == -1) ? 0x0 : flags;
+				invit_info->req_op_ch = op_ch;
+				invit_info->state = 0;
+
+				dump_p2p_attr_ch_list(p2p_ie, p2p_ielen, ch_list_buf, 128);
+				RTW_INFO("RTW_%s:P2P_INVIT_REQ, dialogToken=%d, flags:0x%02x, op_ch:%d, ch_list:%s"
+					, (tx == _TRUE) ? "Tx" : "Rx", dialogToken, flags, op_ch, ch_list_buf);
+				if (gbssid)
+					_RTW_INFO(", gbssid:"MAC_FMT, MAC_ARG(gbssid));
+				_RTW_INFO("\n");
+
+				if (!tx) {
+					#if defined(CONFIG_CONCURRENT_MODE) && defined(CONFIG_CFG80211_ONECHANNEL_UNDER_CONCURRENT)
+					if (rtw_mi_check_status(padapter, MI_LINKED) && padapter->registrypriv.full_ch_in_p2p_handshake == 0) {
+						#if defined(CONFIG_P2P_INVITE_IOT)
+						if (op_ch != -1 && rtw_chk_p2pie_op_ch_with_buddy(padapter, frame_body, len - sizeof(struct rtw_ieee80211_hdr_3addr)) == _FALSE) {
+							RTW_INFO(FUNC_ADPT_FMT" op_ch:%u has no intersect with buddy\n", FUNC_ADPT_ARG(padapter), op_ch);
+							rtw_change_p2pie_ch_list(padapter, frame_body, len - sizeof(struct rtw_ieee80211_hdr_3addr), 0);
+						} else
+						#endif
+						if (rtw_chk_p2pie_ch_list_with_buddy(padapter, frame_body, len - sizeof(struct rtw_ieee80211_hdr_3addr)) == _FALSE) {
+							RTW_INFO(FUNC_ADPT_FMT" ch_list has no intersect with buddy\n", FUNC_ADPT_ARG(padapter));
+							rtw_change_p2pie_ch_list(padapter, frame_body, len - sizeof(struct rtw_ieee80211_hdr_3addr), 0);
+						}
+					}
+					#endif
+				}
+
+				break;
+			}
+			case P2P_INVIT_RESP: {
+				struct rtw_wdev_invit_info *invit_info = &pwdev_priv->invit_info;
+
+				if (tx) {
+					#if defined(CONFIG_CONCURRENT_MODE) && defined(CONFIG_CFG80211_ONECHANNEL_UNDER_CONCURRENT)
+					if (rtw_mi_check_status(padapter, MI_LINKED) && padapter->registrypriv.full_ch_in_p2p_handshake == 0)
+						rtw_cfg80211_adjust_p2pie_channel(padapter, frame_body, len - sizeof(struct rtw_ieee80211_hdr_3addr));
+					#endif
+				}
+
+				cont = rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_STATUS, NULL, &cont_len);
+				if (cont) {
+					#ifdef CONFIG_P2P_INVITE_IOT
+					if (tx && *cont == 7) {
+						RTW_INFO("TX_P2P_INVITE_RESP, status is no common channel, change to unknown group\n");
+						*cont = 8; /* unknow group status */
+					}
+					#endif /* CONFIG_P2P_INVITE_IOT */
+					status = *cont;
+				}
+				cont = rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_OPERATING_CH, NULL, &cont_len);
+				if (cont)
+					op_ch = *(cont + 4);
+				cont = rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_GROUP_BSSID, NULL, &cont_len);
+				if (cont && cont_len == 6)
+					gbssid = cont;
+
+				if (invit_info->token == dialogToken && invit_info->state == 0
+				    && _rtw_memcmp(invit_info->peer_mac, tx ? GetAddr1Ptr(buf) : get_addr2_ptr(buf), ETH_ALEN) == _TRUE
+				   ) {
+					invit_info->status = (status == -1) ? 0xff : status;
+					invit_info->rsp_op_ch = op_ch;
+					invit_info->state = 1;
+					invit_info->token = 0; /* init */
+				}
+
+				dump_p2p_attr_ch_list(p2p_ie, p2p_ielen, ch_list_buf, 128);
+				RTW_INFO("RTW_%s:P2P_INVIT_RESP, dialogToken=%d, status:%d, op_ch:%d, ch_list:%s"
+					, (tx == _TRUE) ? "Tx" : "Rx", dialogToken, status, op_ch, ch_list_buf);
+				if (gbssid)
+					_RTW_INFO(", gbssid:"MAC_FMT, MAC_ARG(gbssid));
+				_RTW_INFO("\n");
+
+				if (!tx) {
+				}
+
+				break;
+			}
+			case P2P_DEVDISC_REQ:
+				RTW_INFO("RTW_%s:P2P_DEVDISC_REQ, dialogToken=%d\n", (tx == _TRUE) ? "Tx" : "Rx", dialogToken);
+				break;
+			case P2P_DEVDISC_RESP:
+				cont = rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_STATUS, NULL, &cont_len);
+				RTW_INFO("RTW_%s:P2P_DEVDISC_RESP, dialogToken=%d, status:%d\n", (tx == _TRUE) ? "Tx" : "Rx", dialogToken, cont ? *cont : -1);
+				break;
+			case P2P_PROVISION_DISC_REQ: {
+				size_t frame_body_len = len - sizeof(struct rtw_ieee80211_hdr_3addr);
+				u8 *p2p_ie;
+				uint p2p_ielen = 0;
+				uint contentlen = 0;
+
+				RTW_INFO("RTW_%s:P2P_PROVISION_DISC_REQ, dialogToken=%d\n", (tx == _TRUE) ? "Tx" : "Rx", dialogToken);
+
+				/* if(tx) */
+				{
+					pwdev_priv->provdisc_req_issued = _FALSE;
+
+					p2p_ie = rtw_get_p2p_ie(frame_body + _PUBLIC_ACTION_IE_OFFSET_, frame_body_len - _PUBLIC_ACTION_IE_OFFSET_, NULL, &p2p_ielen);
+					if (p2p_ie) {
+
+						if (rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_GROUP_ID, NULL, &contentlen)) {
+							pwdev_priv->provdisc_req_issued = _FALSE;/* case: p2p_client join p2p GO */
+						} else {
+							#ifdef CONFIG_DEBUG_CFG80211
+							RTW_INFO("provdisc_req_issued is _TRUE\n");
+							#endif /*CONFIG_DEBUG_CFG80211*/
+							pwdev_priv->provdisc_req_issued = _TRUE;/* case: p2p_devices connection before Nego req. */
+						}
+
+					}
+				}
+			}
+			break;
+			case P2P_PROVISION_DISC_RESP:
+				RTW_INFO("RTW_%s:P2P_PROVISION_DISC_RESP, dialogToken=%d\n", (tx == _TRUE) ? "Tx" : "Rx", dialogToken);
+				break;
+			default:
+				RTW_INFO("RTW_%s:OUI_Subtype=%d, dialogToken=%d\n", (tx == _TRUE) ? "Tx" : "Rx", OUI_Subtype, dialogToken);
+				break;
+			}
+
+		}
+
+	} else if (category == RTW_WLAN_CATEGORY_P2P) {
+		OUI_Subtype = frame_body[5];
+		dialogToken = frame_body[6];
+
+		#ifdef CONFIG_DEBUG_CFG80211
+		RTW_INFO("ACTION_CATEGORY_P2P: OUI=0x%x, OUI_Subtype=%d, dialogToken=%d\n",
+			cpu_to_be32(*((u32 *)(frame_body + 1))), OUI_Subtype, dialogToken);
+		#endif
+
+		is_p2p_frame = OUI_Subtype;
+
+		switch (OUI_Subtype) {
+		case P2P_NOTICE_OF_ABSENCE:
+			RTW_INFO("RTW_%s:P2P_NOTICE_OF_ABSENCE, dialogToken=%d\n", (tx == _TRUE) ? "Tx" : "Rx", dialogToken);
+			break;
+		case P2P_PRESENCE_REQUEST:
+			RTW_INFO("RTW_%s:P2P_PRESENCE_REQUEST, dialogToken=%d\n", (tx == _TRUE) ? "Tx" : "Rx", dialogToken);
+			break;
+		case P2P_PRESENCE_RESPONSE:
+			RTW_INFO("RTW_%s:P2P_PRESENCE_RESPONSE, dialogToken=%d\n", (tx == _TRUE) ? "Tx" : "Rx", dialogToken);
+			break;
+		case P2P_GO_DISC_REQUEST:
+			RTW_INFO("RTW_%s:P2P_GO_DISC_REQUEST, dialogToken=%d\n", (tx == _TRUE) ? "Tx" : "Rx", dialogToken);
+			break;
+		default:
+			RTW_INFO("RTW_%s:OUI_Subtype=%d, dialogToken=%d\n", (tx == _TRUE) ? "Tx" : "Rx", OUI_Subtype, dialogToken);
+			break;
+		}
+
+	}
+
+	return is_p2p_frame;
+}
+
+void rtw_init_cfg80211_wifidirect_info(_adapter	*padapter)
+{
+	struct cfg80211_wifidirect_info *pcfg80211_wdinfo = &padapter->cfg80211_wdinfo;
+
+	_rtw_memset(pcfg80211_wdinfo, 0x00, sizeof(struct cfg80211_wifidirect_info));
+
+	rtw_init_timer(&pcfg80211_wdinfo->remain_on_ch_timer, padapter, ro_ch_timer_process, padapter);
+}
+#endif /* CONFIG_IOCTL_CFG80211	 */
+
+s32 p2p_protocol_wk_hdl(_adapter *padapter, int intCmdType, u8 *buf)
+{
+	int ret = H2C_SUCCESS;
+
+	switch (intCmdType) {
+	case P2P_FIND_PHASE_WK:
+		find_phase_handler(padapter);
+		break;
+
+	case P2P_RESTORE_STATE_WK:
+		restore_p2p_state_handler(padapter);
+		break;
+
+	case P2P_PRE_TX_PROVDISC_PROCESS_WK:
+#ifdef CONFIG_CONCURRENT_MODE
+		if (rtw_mi_check_status(padapter, MI_LINKED))
+			p2p_concurrent_handler(padapter);
+		else
+			pre_tx_provdisc_handler(padapter);
+#else
+		pre_tx_provdisc_handler(padapter);
+#endif
+		break;
+
+	case P2P_PRE_TX_INVITEREQ_PROCESS_WK:
+#ifdef CONFIG_CONCURRENT_MODE
+		if (rtw_mi_check_status(padapter, MI_LINKED))
+			p2p_concurrent_handler(padapter);
+		else
+			pre_tx_invitereq_handler(padapter);
+#else
+		pre_tx_invitereq_handler(padapter);
+#endif
+		break;
+
+	case P2P_PRE_TX_NEGOREQ_PROCESS_WK:
+#ifdef CONFIG_CONCURRENT_MODE
+		if (rtw_mi_check_status(padapter, MI_LINKED))
+			p2p_concurrent_handler(padapter);
+		else
+			pre_tx_negoreq_handler(padapter);
+#else
+		pre_tx_negoreq_handler(padapter);
+#endif
+		break;
+
+#ifdef CONFIG_CONCURRENT_MODE
+	case P2P_AP_P2P_CH_SWITCH_PROCESS_WK:
+		p2p_concurrent_handler(padapter);
+		break;
+#endif
+
+#ifdef CONFIG_IOCTL_CFG80211
+	case P2P_RO_CH_WK:
+		ret = ro_ch_handler(padapter, buf);
+		break;
+	case P2P_CANCEL_RO_CH_WK:
+		ret = cancel_ro_ch_handler(padapter, buf);
+		break;
+#endif
+
+	default:
+		rtw_warn_on(1);
+		break;
+	}
+
+	return ret;
+}
+
+int process_p2p_cross_connect_ie(PADAPTER padapter, u8 *IEs, u32 IELength)
+{
+	int ret = _TRUE;
+	u8 *ies;
+	u32 ies_len;
+	u8 *p2p_ie;
+	u32	p2p_ielen = 0;
+	u8	p2p_attr[MAX_P2P_IE_LEN] = { 0x00 };/* NoA length should be n*(13) + 2 */
+	u32	attr_contentlen = 0;
+
+
+
+	if (IELength <= _BEACON_IE_OFFSET_)
+		return ret;
+
+	ies = IEs + _BEACON_IE_OFFSET_;
+	ies_len = IELength - _BEACON_IE_OFFSET_;
+
+	p2p_ie = rtw_get_p2p_ie(ies, ies_len, NULL, &p2p_ielen);
+
+	while (p2p_ie) {
+		/* Get P2P Manageability IE. */
+		if (rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_MANAGEABILITY, p2p_attr, &attr_contentlen)) {
+			if ((p2p_attr[0] & (BIT(0) | BIT(1))) == 0x01)
+				ret = _FALSE;
+			break;
+		}
+		/* Get the next P2P IE */
+		p2p_ie = rtw_get_p2p_ie(p2p_ie + p2p_ielen, ies_len - (p2p_ie - ies + p2p_ielen), NULL, &p2p_ielen);
+	}
+
+	return ret;
+}
+
+#ifdef CONFIG_P2P_PS
+void process_p2p_ps_ie(PADAPTER padapter, u8 *IEs, u32 IELength)
+{
+	u8 *ies;
+	u32 ies_len;
+	u8 *p2p_ie;
+	u32	p2p_ielen = 0;
+	u8	noa_attr[MAX_P2P_IE_LEN] = { 0x00 };/* NoA length should be n*(13) + 2 */
+	u32	attr_contentlen = 0;
+
+	struct wifidirect_info	*pwdinfo = &(padapter->wdinfo);
+	u8	find_p2p = _FALSE, find_p2p_ps = _FALSE;
+	u8	noa_offset, noa_num, noa_index;
+
+
+	if (rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE))
+		return;
+#ifdef CONFIG_CONCURRENT_MODE
+#ifndef CONFIG_FW_MULTI_PORT_SUPPORT
+	if (padapter->hw_port != HW_PORT0)
+		return;
+#endif
+#endif
+	if (IELength <= _BEACON_IE_OFFSET_)
+		return;
+
+	ies = IEs + _BEACON_IE_OFFSET_;
+	ies_len = IELength - _BEACON_IE_OFFSET_;
+
+	p2p_ie = rtw_get_p2p_ie(ies, ies_len, NULL, &p2p_ielen);
+
+	while (p2p_ie) {
+		find_p2p = _TRUE;
+		/* Get Notice of Absence IE. */
+		if (rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_NOA, noa_attr, &attr_contentlen)) {
+			find_p2p_ps = _TRUE;
+			noa_index = noa_attr[0];
+
+			if ((pwdinfo->p2p_ps_mode == P2P_PS_NONE) ||
+			    (noa_index != pwdinfo->noa_index)) { /* if index change, driver should reconfigure related setting. */
+				pwdinfo->noa_index = noa_index;
+				pwdinfo->opp_ps = noa_attr[1] >> 7;
+				pwdinfo->ctwindow = noa_attr[1] & 0x7F;
+
+				noa_offset = 2;
+				noa_num = 0;
+				/* NoA length should be n*(13) + 2 */
+				if (attr_contentlen > 2) {
+					while (noa_offset < attr_contentlen) {
+						/* _rtw_memcpy(&wifidirect_info->noa_count[noa_num], &noa_attr[noa_offset], 1); */
+						pwdinfo->noa_count[noa_num] = noa_attr[noa_offset];
+						noa_offset += 1;
+
+						_rtw_memcpy(&pwdinfo->noa_duration[noa_num], &noa_attr[noa_offset], 4);
+						noa_offset += 4;
+
+						_rtw_memcpy(&pwdinfo->noa_interval[noa_num], &noa_attr[noa_offset], 4);
+						noa_offset += 4;
+
+						_rtw_memcpy(&pwdinfo->noa_start_time[noa_num], &noa_attr[noa_offset], 4);
+						noa_offset += 4;
+
+						noa_num++;
+					}
+				}
+				pwdinfo->noa_num = noa_num;
+
+				if (pwdinfo->opp_ps == 1) {
+					pwdinfo->p2p_ps_mode = P2P_PS_CTWINDOW;
+					/* driver should wait LPS for entering CTWindow */
+					if (adapter_to_pwrctl(padapter)->bFwCurrentInPSMode == _TRUE)
+						p2p_ps_wk_cmd(padapter, P2P_PS_ENABLE, 1);
+				} else if (pwdinfo->noa_num > 0) {
+					pwdinfo->p2p_ps_mode = P2P_PS_NOA;
+					p2p_ps_wk_cmd(padapter, P2P_PS_ENABLE, 1);
+				} else if (pwdinfo->p2p_ps_mode > P2P_PS_NONE)
+					p2p_ps_wk_cmd(padapter, P2P_PS_DISABLE, 1);
+			}
+
+			break; /* find target, just break. */
+		}
+
+		/* Get the next P2P IE */
+		p2p_ie = rtw_get_p2p_ie(p2p_ie + p2p_ielen, ies_len - (p2p_ie - ies + p2p_ielen), NULL, &p2p_ielen);
+
+	}
+
+	if (find_p2p == _TRUE) {
+		if ((pwdinfo->p2p_ps_mode > P2P_PS_NONE) && (find_p2p_ps == _FALSE))
+			p2p_ps_wk_cmd(padapter, P2P_PS_DISABLE, 1);
+	}
+
+}
+
+void p2p_ps_wk_hdl(_adapter *padapter, u8 p2p_ps_state)
+{
+	struct pwrctrl_priv		*pwrpriv = adapter_to_pwrctl(padapter);
+	struct wifidirect_info	*pwdinfo = &(padapter->wdinfo);
+	u32 ps_deny = 0;
+
+	/* Pre action for p2p state */
+	switch (p2p_ps_state) {
+	case P2P_PS_DISABLE:
+		pwdinfo->p2p_ps_state = p2p_ps_state;
+
+		rtw_hal_set_hwreg(padapter, HW_VAR_H2C_FW_P2P_PS_OFFLOAD, (u8 *)(&p2p_ps_state));
+
+		pwdinfo->noa_index = 0;
+		pwdinfo->ctwindow = 0;
+		pwdinfo->opp_ps = 0;
+		pwdinfo->noa_num = 0;
+		pwdinfo->p2p_ps_mode = P2P_PS_NONE;
+		if (pwrpriv->bFwCurrentInPSMode == _TRUE) {
+			if (pwrpriv->smart_ps == 0) {
+				pwrpriv->smart_ps = 2;
+				rtw_hal_set_hwreg(padapter, HW_VAR_H2C_FW_PWRMODE, (u8 *)(&(pwrpriv->pwr_mode)));
+			}
+		}
+		break;
+	case P2P_PS_ENABLE:
+		_enter_pwrlock(&adapter_to_pwrctl(padapter)->lock);
+		ps_deny = rtw_ps_deny_get(padapter);
+		_exit_pwrlock(&adapter_to_pwrctl(padapter)->lock);
+
+		if ((ps_deny & (PS_DENY_SCAN | PS_DENY_JOIN))
+			|| rtw_mi_check_fwstate(padapter, (_FW_UNDER_SURVEY | _FW_UNDER_LINKING))) {
+			pwdinfo->p2p_ps_mode = P2P_PS_NONE;
+			RTW_DBG(FUNC_ADPT_FMT" Block P2P PS under site survey or LINKING\n", FUNC_ADPT_ARG(padapter));
+			return;
+		}
+		if (pwdinfo->p2p_ps_mode > P2P_PS_NONE) {
+#ifdef CONFIG_MCC_MODE
+			if (MCC_EN(padapter)) {
+				if (rtw_hal_check_mcc_status(padapter, MCC_STATUS_DOING_MCC)) {
+					RTW_INFO("P2P PS enble under MCC\n");
+					rtw_warn_on(1);
+				}
+
+			}
+#endif /* CONFIG_MCC_MODE */
+			pwdinfo->p2p_ps_state = p2p_ps_state;
+
+			if (pwdinfo->ctwindow > 0) {
+				if (pwrpriv->smart_ps != 0) {
+					pwrpriv->smart_ps = 0;
+					RTW_INFO("%s(): Enter CTW, change SmartPS\n", __FUNCTION__);
+					rtw_hal_set_hwreg(padapter, HW_VAR_H2C_FW_PWRMODE, (u8 *)(&(pwrpriv->pwr_mode)));
+				}
+			}
+			rtw_hal_set_hwreg(padapter, HW_VAR_H2C_FW_P2P_PS_OFFLOAD, (u8 *)(&p2p_ps_state));
+		}
+		break;
+	case P2P_PS_SCAN:
+	case P2P_PS_SCAN_DONE:
+	case P2P_PS_ALLSTASLEEP:
+		if (pwdinfo->p2p_ps_mode > P2P_PS_NONE) {
+			pwdinfo->p2p_ps_state = p2p_ps_state;
+			rtw_hal_set_hwreg(padapter, HW_VAR_H2C_FW_P2P_PS_OFFLOAD, (u8 *)(&p2p_ps_state));
+		}
+		break;
+	default:
+		break;
+	}
+
+#ifdef CONFIG_MCC_MODE
+	rtw_hal_mcc_process_noa(padapter);
+#endif /* CONFIG_MCC_MODE */
+}
+
+u8 p2p_ps_wk_cmd(_adapter *padapter, u8 p2p_ps_state, u8 enqueue)
+{
+	struct cmd_obj	*ph2c;
+	struct drvextra_cmd_parm	*pdrvextra_cmd_parm;
+	struct wifidirect_info	*pwdinfo = &(padapter->wdinfo);
+	struct cmd_priv	*pcmdpriv = &padapter->cmdpriv;
+	u8	res = _SUCCESS;
+
+
+	if (rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE)
+#ifdef CONFIG_CONCURRENT_MODE
+#ifndef CONFIG_FW_MULTI_PORT_SUPPORT
+	    || (padapter->hw_port != HW_PORT0)
+#endif
+#endif
+	   )
+		return res;
+
+	if (enqueue) {
+		ph2c = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj));
+		if (ph2c == NULL) {
+			res = _FAIL;
+			goto exit;
+		}
+
+		pdrvextra_cmd_parm = (struct drvextra_cmd_parm *)rtw_zmalloc(sizeof(struct drvextra_cmd_parm));
+		if (pdrvextra_cmd_parm == NULL) {
+			rtw_mfree((unsigned char *)ph2c, sizeof(struct cmd_obj));
+			res = _FAIL;
+			goto exit;
+		}
+
+		pdrvextra_cmd_parm->ec_id = P2P_PS_WK_CID;
+		pdrvextra_cmd_parm->type = p2p_ps_state;
+		pdrvextra_cmd_parm->size = 0;
+		pdrvextra_cmd_parm->pbuf = NULL;
+
+		init_h2fwcmd_w_parm_no_rsp(ph2c, pdrvextra_cmd_parm, GEN_CMD_CODE(_Set_Drv_Extra));
+
+		res = rtw_enqueue_cmd(pcmdpriv, ph2c);
+	} else
+		p2p_ps_wk_hdl(padapter, p2p_ps_state);
+
+exit:
+
+
+	return res;
+
+}
+#endif /* CONFIG_P2P_PS */
+
+static void reset_ch_sitesurvey_timer_process(void *FunctionContext)
+{
+	_adapter *adapter = (_adapter *)FunctionContext;
+	struct	wifidirect_info		*pwdinfo = &adapter->wdinfo;
+
+	if (rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE))
+		return;
+
+	RTW_INFO("[%s] In\n", __FUNCTION__);
+	/*	Reset the operation channel information */
+	pwdinfo->rx_invitereq_info.operation_ch[0] = 0;
+#ifdef CONFIG_P2P_OP_CHK_SOCIAL_CH
+	pwdinfo->rx_invitereq_info.operation_ch[1] = 0;
+	pwdinfo->rx_invitereq_info.operation_ch[2] = 0;
+	pwdinfo->rx_invitereq_info.operation_ch[3] = 0;
+#endif /* CONFIG_P2P_OP_CHK_SOCIAL_CH */
+	pwdinfo->rx_invitereq_info.scan_op_ch_only = 0;
+}
+
+static void reset_ch_sitesurvey_timer_process2(void *FunctionContext)
+{
+	_adapter *adapter = (_adapter *)FunctionContext;
+	struct	wifidirect_info		*pwdinfo = &adapter->wdinfo;
+
+	if (rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE))
+		return;
+
+	RTW_INFO("[%s] In\n", __FUNCTION__);
+	/*	Reset the operation channel information */
+	pwdinfo->p2p_info.operation_ch[0] = 0;
+#ifdef CONFIG_P2P_OP_CHK_SOCIAL_CH
+	pwdinfo->p2p_info.operation_ch[1] = 0;
+	pwdinfo->p2p_info.operation_ch[2] = 0;
+	pwdinfo->p2p_info.operation_ch[3] = 0;
+#endif /* CONFIG_P2P_OP_CHK_SOCIAL_CH */
+	pwdinfo->p2p_info.scan_op_ch_only = 0;
+}
+
+static void restore_p2p_state_timer_process(void *FunctionContext)
+{
+	_adapter *adapter = (_adapter *)FunctionContext;
+	struct	wifidirect_info		*pwdinfo = &adapter->wdinfo;
+
+	if (rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE))
+		return;
+
+	p2p_protocol_wk_cmd(adapter, P2P_RESTORE_STATE_WK);
+}
+
+static void pre_tx_scan_timer_process(void *FunctionContext)
+{
+	_adapter							*adapter = (_adapter *) FunctionContext;
+	struct	wifidirect_info				*pwdinfo = &adapter->wdinfo;
+	_irqL							irqL;
+	struct mlme_priv					*pmlmepriv = &adapter->mlmepriv;
+
+	if (rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE))
+		return;
+
+	_enter_critical_bh(&pmlmepriv->lock, &irqL);
+
+
+	if (rtw_p2p_chk_state(pwdinfo, P2P_STATE_TX_PROVISION_DIS_REQ)) {
+		if (_TRUE == pwdinfo->tx_prov_disc_info.benable) {	/*	the provision discovery request frame is trigger to send or not */
+			p2p_protocol_wk_cmd(adapter, P2P_PRE_TX_PROVDISC_PROCESS_WK);
+			/* issue_probereq_p2p(adapter, NULL); */
+			/* _set_timer( &pwdinfo->pre_tx_scan_timer, P2P_TX_PRESCAN_TIMEOUT ); */
+		}
+	} else if (rtw_p2p_chk_state(pwdinfo, P2P_STATE_GONEGO_ING)) {
+		if (_TRUE == pwdinfo->nego_req_info.benable)
+			p2p_protocol_wk_cmd(adapter, P2P_PRE_TX_NEGOREQ_PROCESS_WK);
+	} else if (rtw_p2p_chk_state(pwdinfo, P2P_STATE_TX_INVITE_REQ)) {
+		if (_TRUE == pwdinfo->invitereq_info.benable)
+			p2p_protocol_wk_cmd(adapter, P2P_PRE_TX_INVITEREQ_PROCESS_WK);
+	} else
+		RTW_INFO("[%s] p2p_state is %d, ignore!!\n", __FUNCTION__, rtw_p2p_state(pwdinfo));
+
+	_exit_critical_bh(&pmlmepriv->lock, &irqL);
+}
+
+static void find_phase_timer_process(void *FunctionContext)
+{
+	_adapter *adapter = (_adapter *)FunctionContext;
+	struct	wifidirect_info		*pwdinfo = &adapter->wdinfo;
+
+	if (rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE))
+		return;
+
+	adapter->wdinfo.find_phase_state_exchange_cnt++;
+
+	p2p_protocol_wk_cmd(adapter, P2P_FIND_PHASE_WK);
+}
+
+#ifdef CONFIG_CONCURRENT_MODE
+void ap_p2p_switch_timer_process(void *FunctionContext)
+{
+	_adapter *adapter = (_adapter *)FunctionContext;
+	struct	wifidirect_info		*pwdinfo = &adapter->wdinfo;
+#ifdef CONFIG_IOCTL_CFG80211
+	struct rtw_wdev_priv *pwdev_priv = adapter_wdev_data(adapter);
+#endif
+
+	if (rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE))
+		return;
+
+#ifdef CONFIG_IOCTL_CFG80211
+	ATOMIC_SET(&pwdev_priv->switch_ch_to, 1);
+#endif
+
+	p2p_protocol_wk_cmd(adapter, P2P_AP_P2P_CH_SWITCH_PROCESS_WK);
+}
+#endif
+
+void reset_global_wifidirect_info(_adapter *padapter)
+{
+	struct wifidirect_info	*pwdinfo;
+
+	pwdinfo = &padapter->wdinfo;
+	pwdinfo->persistent_supported = 0;
+	pwdinfo->session_available = _TRUE;
+	rtw_tdls_wfd_enable(padapter, 0);
+	pwdinfo->wfd_tdls_weaksec = _TRUE;
+}
+
+#ifdef CONFIG_WFD
+int rtw_init_wifi_display_info(_adapter *padapter)
+{
+	int	res = _SUCCESS;
+	struct wifi_display_info *pwfd_info = &padapter->wfd_info;
+
+	/* Used in P2P and TDLS */
+	pwfd_info->init_rtsp_ctrlport = 554;
+#ifdef CONFIG_IOCTL_CFG80211
+	pwfd_info->rtsp_ctrlport = 0;
+#else
+	pwfd_info->rtsp_ctrlport = pwfd_info->init_rtsp_ctrlport; /* set non-zero value for legacy wfd */
+#endif
+	pwfd_info->tdls_rtsp_ctrlport = 0;
+	pwfd_info->peer_rtsp_ctrlport = 0;	/*	Reset to 0 */
+	pwfd_info->wfd_enable = _FALSE;
+	pwfd_info->wfd_device_type = WFD_DEVINFO_PSINK;
+	pwfd_info->scan_result_type = SCAN_RESULT_P2P_ONLY;
+
+	/* Used in P2P */
+	pwfd_info->peer_session_avail = _TRUE;
+	pwfd_info->wfd_pc = _FALSE;
+
+	/* Used in TDLS */
+	_rtw_memset(pwfd_info->ip_address, 0x00, 4);
+	_rtw_memset(pwfd_info->peer_ip_address, 0x00, 4);
+	return res;
+
+}
+
+inline void rtw_wfd_enable(_adapter *adapter, bool on)
+{
+	struct wifi_display_info *wfdinfo = &adapter->wfd_info;
+
+	if (on) {
+		wfdinfo->rtsp_ctrlport = wfdinfo->init_rtsp_ctrlport;
+		wfdinfo->wfd_enable = _TRUE;
+
+	} else {
+		wfdinfo->wfd_enable = _FALSE;
+		wfdinfo->rtsp_ctrlport = 0;
+	}
+}
+
+inline void rtw_wfd_set_ctrl_port(_adapter *adapter, u16 port)
+{
+	struct wifi_display_info *wfdinfo = &adapter->wfd_info;
+
+	wfdinfo->init_rtsp_ctrlport = port;
+	if (wfdinfo->wfd_enable == _TRUE)
+		wfdinfo->rtsp_ctrlport = port;
+	if (adapter->wdinfo.wfd_tdls_enable == 1)
+		wfdinfo->tdls_rtsp_ctrlport = port;
+}
+
+inline void rtw_tdls_wfd_enable(_adapter *adapter, bool on)
+{
+	struct wifi_display_info *wfdinfo = &adapter->wfd_info;
+
+	if (on) {
+		wfdinfo->tdls_rtsp_ctrlport = wfdinfo->init_rtsp_ctrlport;
+		adapter->wdinfo.wfd_tdls_enable = 1;
+
+	} else {
+		adapter->wdinfo.wfd_tdls_enable = 0;
+		wfdinfo->tdls_rtsp_ctrlport = 0;
+	}
+}
+
+u32 rtw_append_beacon_wfd_ie(_adapter *adapter, u8 *pbuf)
+{
+	struct wifidirect_info *wdinfo = &adapter->wdinfo;
+	struct mlme_priv *mlme = &adapter->mlmepriv;
+	u8 build_ie_by_self = 0;
+	u32 len = 0;
+
+	if (!hal_chk_wl_func(adapter, WL_FUNC_MIRACAST))
+		goto exit;
+
+#ifdef CONFIG_IOCTL_CFG80211
+	if (_TRUE == wdinfo->wfd_info->wfd_enable)
+#endif
+		build_ie_by_self = 1;
+
+	if (build_ie_by_self)
+		len = build_beacon_wfd_ie(wdinfo, pbuf);
+#ifdef CONFIG_IOCTL_CFG80211
+	else if (mlme->wfd_beacon_ie && mlme->wfd_beacon_ie_len > 0) {
+		len = mlme->wfd_beacon_ie_len;
+		_rtw_memcpy(pbuf, mlme->wfd_beacon_ie, len);
+	}
+#endif
+
+exit:
+	return len;
+}
+
+u32 rtw_append_probe_req_wfd_ie(_adapter *adapter, u8 *pbuf)
+{
+	struct wifidirect_info *wdinfo = &adapter->wdinfo;
+	struct mlme_priv *mlme = &adapter->mlmepriv;
+	u8 build_ie_by_self = 0;
+	u32 len = 0;
+
+	if (!hal_chk_wl_func(adapter, WL_FUNC_MIRACAST))
+		goto exit;
+
+#ifdef CONFIG_IOCTL_CFG80211
+	if (_TRUE == wdinfo->wfd_info->wfd_enable)
+#endif
+		build_ie_by_self = 1;
+
+	if (build_ie_by_self)
+		len = build_probe_req_wfd_ie(wdinfo, pbuf);
+#ifdef CONFIG_IOCTL_CFG80211
+	else if (mlme->wfd_probe_req_ie && mlme->wfd_probe_req_ie_len > 0) {
+		len = mlme->wfd_probe_req_ie_len;
+		_rtw_memcpy(pbuf, mlme->wfd_probe_req_ie, len);
+	}
+#endif
+
+exit:
+	return len;
+}
+
+u32 rtw_append_probe_resp_wfd_ie(_adapter *adapter, u8 *pbuf)
+{
+	struct wifidirect_info *wdinfo = &adapter->wdinfo;
+	struct mlme_priv *mlme = &adapter->mlmepriv;
+	u8 build_ie_by_self = 0;
+	u32 len = 0;
+
+	if (!hal_chk_wl_func(adapter, WL_FUNC_MIRACAST))
+		goto exit;
+
+#ifdef CONFIG_IOCTL_CFG80211
+	if (_TRUE == wdinfo->wfd_info->wfd_enable)
+#endif
+		build_ie_by_self = 1;
+
+	if (build_ie_by_self)
+		len = build_probe_resp_wfd_ie(wdinfo, pbuf, 0);
+#ifdef CONFIG_IOCTL_CFG80211
+	else if (mlme->wfd_probe_resp_ie && mlme->wfd_probe_resp_ie_len > 0) {
+		len = mlme->wfd_probe_resp_ie_len;
+		_rtw_memcpy(pbuf, mlme->wfd_probe_resp_ie, len);
+	}
+#endif
+
+exit:
+	return len;
+}
+
+u32 rtw_append_assoc_req_wfd_ie(_adapter *adapter, u8 *pbuf)
+{
+	struct wifidirect_info *wdinfo = &adapter->wdinfo;
+	struct mlme_priv *mlme = &adapter->mlmepriv;
+	u8 build_ie_by_self = 0;
+	u32 len = 0;
+
+	if (!hal_chk_wl_func(adapter, WL_FUNC_MIRACAST))
+		goto exit;
+
+#ifdef CONFIG_IOCTL_CFG80211
+	if (_TRUE == wdinfo->wfd_info->wfd_enable)
+#endif
+		build_ie_by_self = 1;
+
+	if (build_ie_by_self)
+		len = build_assoc_req_wfd_ie(wdinfo, pbuf);
+#ifdef CONFIG_IOCTL_CFG80211
+	else if (mlme->wfd_assoc_req_ie && mlme->wfd_assoc_req_ie_len > 0) {
+		len = mlme->wfd_assoc_req_ie_len;
+		_rtw_memcpy(pbuf, mlme->wfd_assoc_req_ie, len);
+	}
+#endif
+
+exit:
+	return len;
+}
+
+u32 rtw_append_assoc_resp_wfd_ie(_adapter *adapter, u8 *pbuf)
+{
+	struct wifidirect_info *wdinfo = &adapter->wdinfo;
+	struct mlme_priv *mlme = &adapter->mlmepriv;
+	u8 build_ie_by_self = 0;
+	u32 len = 0;
+
+	if (!hal_chk_wl_func(adapter, WL_FUNC_MIRACAST))
+		goto exit;
+
+#ifdef CONFIG_IOCTL_CFG80211
+	if (_TRUE == wdinfo->wfd_info->wfd_enable)
+#endif
+		build_ie_by_self = 1;
+
+	if (build_ie_by_self)
+		len = build_assoc_resp_wfd_ie(wdinfo, pbuf);
+#ifdef CONFIG_IOCTL_CFG80211
+	else if (mlme->wfd_assoc_resp_ie && mlme->wfd_assoc_resp_ie_len > 0) {
+		len = mlme->wfd_assoc_resp_ie_len;
+		_rtw_memcpy(pbuf, mlme->wfd_assoc_resp_ie, len);
+	}
+#endif
+
+exit:
+	return len;
+}
+
+#endif /* CONFIG_WFD */
+
+void rtw_init_wifidirect_timers(_adapter *padapter)
+{
+	struct wifidirect_info *pwdinfo = &padapter->wdinfo;
+
+	rtw_init_timer(&pwdinfo->find_phase_timer, padapter, find_phase_timer_process, padapter);
+	rtw_init_timer(&pwdinfo->restore_p2p_state_timer, padapter, restore_p2p_state_timer_process, padapter);
+	rtw_init_timer(&pwdinfo->pre_tx_scan_timer, padapter, pre_tx_scan_timer_process, padapter);
+	rtw_init_timer(&pwdinfo->reset_ch_sitesurvey, padapter, reset_ch_sitesurvey_timer_process, padapter);
+	rtw_init_timer(&pwdinfo->reset_ch_sitesurvey2, padapter, reset_ch_sitesurvey_timer_process2, padapter);
+#ifdef CONFIG_CONCURRENT_MODE
+	rtw_init_timer(&pwdinfo->ap_p2p_switch_timer, padapter, ap_p2p_switch_timer_process, padapter);
+#endif
+}
+
+void rtw_init_wifidirect_addrs(_adapter *padapter, u8 *dev_addr, u8 *iface_addr)
+{
+#ifdef CONFIG_P2P
+	struct wifidirect_info *pwdinfo = &padapter->wdinfo;
+
+	/*init device&interface address */
+	if (dev_addr)
+		_rtw_memcpy(pwdinfo->device_addr, dev_addr, ETH_ALEN);
+	if (iface_addr)
+		_rtw_memcpy(pwdinfo->interface_addr, iface_addr, ETH_ALEN);
+#endif
+}
+
+void init_wifidirect_info(_adapter *padapter, enum P2P_ROLE role)
+{
+	struct wifidirect_info	*pwdinfo;
+#ifdef CONFIG_WFD
+	struct wifi_display_info	*pwfd_info = &padapter->wfd_info;
+#endif
+	pwdinfo = &padapter->wdinfo;
+
+	pwdinfo->padapter = padapter;
+
+	/*	1, 6, 11 are the social channel defined in the WiFi Direct specification. */
+	pwdinfo->social_chan[0] = 1;
+	pwdinfo->social_chan[1] = 6;
+	pwdinfo->social_chan[2] = 11;
+	pwdinfo->social_chan[3] = 0;	/*	channel 0 for scanning ending in site survey function. */
+
+	if (role != P2P_ROLE_DISABLE
+		&& pwdinfo->driver_interface != DRIVER_CFG80211
+	) {
+		#ifdef CONFIG_CONCURRENT_MODE
+		u8 union_ch = 0;
+
+		if (rtw_mi_check_status(padapter, MI_LINKED))
+			union_ch = rtw_mi_get_union_chan(padapter);
+
+		if (union_ch != 0 &&
+			(union_ch == 1 || union_ch == 6 || union_ch == 11)
+		) {
+			/* Use the AP's channel as the listen channel */
+			/* This will avoid the channel switch between AP's channel and listen channel */
+			pwdinfo->listen_channel = union_ch;
+		} else
+		#endif /* CONFIG_CONCURRENT_MODE */
+		{
+			/* Use the channel 11 as the listen channel */
+			pwdinfo->listen_channel = 11;
+		}
+	}
+
+	if (role == P2P_ROLE_DEVICE) {
+		rtw_p2p_set_role(pwdinfo, P2P_ROLE_DEVICE);
+#ifdef CONFIG_CONCURRENT_MODE
+		if (rtw_mi_check_status(padapter, MI_LINKED))
+			rtw_p2p_set_state(pwdinfo, P2P_STATE_IDLE);
+		else
+#endif
+			rtw_p2p_set_state(pwdinfo, P2P_STATE_LISTEN);
+
+		pwdinfo->intent = 1;
+		rtw_p2p_set_pre_state(pwdinfo, P2P_STATE_LISTEN);
+	} else if (role == P2P_ROLE_CLIENT) {
+		rtw_p2p_set_role(pwdinfo, P2P_ROLE_CLIENT);
+		rtw_p2p_set_state(pwdinfo, P2P_STATE_GONEGO_OK);
+		pwdinfo->intent = 1;
+		rtw_p2p_set_pre_state(pwdinfo, P2P_STATE_GONEGO_OK);
+	} else if (role == P2P_ROLE_GO) {
+		rtw_p2p_set_role(pwdinfo, P2P_ROLE_GO);
+		rtw_p2p_set_state(pwdinfo, P2P_STATE_GONEGO_OK);
+		pwdinfo->intent = 15;
+		rtw_p2p_set_pre_state(pwdinfo, P2P_STATE_GONEGO_OK);
+	}
+
+	/*	Use the OFDM rate in the P2P probe response frame. ( 6(B), 9(B), 12, 18, 24, 36, 48, 54 )	 */
+	pwdinfo->support_rate[0] = 0x8c;	/*	6(B) */
+	pwdinfo->support_rate[1] = 0x92;	/*	9(B) */
+	pwdinfo->support_rate[2] = 0x18;	/*	12 */
+	pwdinfo->support_rate[3] = 0x24;	/*	18 */
+	pwdinfo->support_rate[4] = 0x30;	/*	24 */
+	pwdinfo->support_rate[5] = 0x48;	/*	36 */
+	pwdinfo->support_rate[6] = 0x60;	/*	48 */
+	pwdinfo->support_rate[7] = 0x6c;	/*	54 */
+
+	_rtw_memcpy((void *) pwdinfo->p2p_wildcard_ssid, "DIRECT-", 7);
+
+	_rtw_memset(pwdinfo->device_name, 0x00, WPS_MAX_DEVICE_NAME_LEN);
+	pwdinfo->device_name_len = 0;
+
+	_rtw_memset(&pwdinfo->invitereq_info, 0x00, sizeof(struct tx_invite_req_info));
+	pwdinfo->invitereq_info.token = 3;	/*	Token used for P2P invitation request frame. */
+
+	_rtw_memset(&pwdinfo->inviteresp_info, 0x00, sizeof(struct tx_invite_resp_info));
+	pwdinfo->inviteresp_info.token = 0;
+
+	pwdinfo->profileindex = 0;
+	_rtw_memset(&pwdinfo->profileinfo[0], 0x00, sizeof(struct profile_info) * P2P_MAX_PERSISTENT_GROUP_NUM);
+
+	rtw_p2p_findphase_ex_set(pwdinfo, P2P_FINDPHASE_EX_NONE);
+
+	pwdinfo->listen_dwell = (u8)((rtw_get_current_time() % 3) + 1);
+	/* RTW_INFO( "[%s] listen_dwell time is %d00ms\n", __FUNCTION__, pwdinfo->listen_dwell ); */
+
+	_rtw_memset(&pwdinfo->tx_prov_disc_info, 0x00, sizeof(struct tx_provdisc_req_info));
+	pwdinfo->tx_prov_disc_info.wps_config_method_request = WPS_CM_NONE;
+
+	_rtw_memset(&pwdinfo->nego_req_info, 0x00, sizeof(struct tx_nego_req_info));
+
+	pwdinfo->device_password_id_for_nego = WPS_DPID_PBC;
+	pwdinfo->negotiation_dialog_token = 1;
+
+	_rtw_memset(pwdinfo->nego_ssid, 0x00, WLAN_SSID_MAXLEN);
+	pwdinfo->nego_ssidlen = 0;
+
+	pwdinfo->ui_got_wps_info = P2P_NO_WPSINFO;
+#ifdef CONFIG_WFD
+	pwdinfo->supported_wps_cm = WPS_CONFIG_METHOD_DISPLAY  | WPS_CONFIG_METHOD_PBC;
+	pwdinfo->wfd_info = pwfd_info;
+#else
+	pwdinfo->supported_wps_cm = WPS_CONFIG_METHOD_DISPLAY | WPS_CONFIG_METHOD_PBC | WPS_CONFIG_METHOD_KEYPAD;
+#endif /* CONFIG_WFD */
+	pwdinfo->channel_list_attr_len = 0;
+	_rtw_memset(pwdinfo->channel_list_attr, 0x00, 100);
+
+	_rtw_memset(pwdinfo->rx_prov_disc_info.strconfig_method_desc_of_prov_disc_req, 0x00, 4);
+	_rtw_memset(pwdinfo->rx_prov_disc_info.strconfig_method_desc_of_prov_disc_req, '0', 3);
+	_rtw_memset(&pwdinfo->groupid_info, 0x00, sizeof(struct group_id_info));
+#ifdef CONFIG_CONCURRENT_MODE
+#ifdef CONFIG_IOCTL_CFG80211
+	pwdinfo->ext_listen_interval = 1000; /* The interval to be available with legacy AP during p2p0-find/scan */
+	pwdinfo->ext_listen_period = 3000; /* The time period to be available for P2P during nego */
+#else /* !CONFIG_IOCTL_CFG80211 */
+	/* pwdinfo->ext_listen_interval = 3000; */
+	/* pwdinfo->ext_listen_period = 400; */
+	pwdinfo->ext_listen_interval = 1000;
+	pwdinfo->ext_listen_period = 1000;
+#endif /* !CONFIG_IOCTL_CFG80211 */
+#endif
+
+	/* Commented by Kurt 20130319
+	 * For WiDi purpose: Use CFG80211 interface but controled WFD/RDS frame by driver itself. */
+#ifdef CONFIG_IOCTL_CFG80211
+	pwdinfo->driver_interface = DRIVER_CFG80211;
+#else
+	pwdinfo->driver_interface = DRIVER_WEXT;
+#endif /* CONFIG_IOCTL_CFG80211 */
+
+	pwdinfo->wfd_tdls_enable = 0;
+	_rtw_memset(pwdinfo->p2p_peer_interface_addr, 0x00, ETH_ALEN);
+	_rtw_memset(pwdinfo->p2p_peer_device_addr, 0x00, ETH_ALEN);
+
+	pwdinfo->rx_invitereq_info.operation_ch[0] = 0;
+	pwdinfo->rx_invitereq_info.operation_ch[1] = 0;	/*	Used to indicate the scan end in site survey function */
+#ifdef CONFIG_P2P_OP_CHK_SOCIAL_CH
+	pwdinfo->rx_invitereq_info.operation_ch[2] = 0;
+	pwdinfo->rx_invitereq_info.operation_ch[3] = 0;
+	pwdinfo->rx_invitereq_info.operation_ch[4] = 0;
+#endif /* CONFIG_P2P_OP_CHK_SOCIAL_CH */
+	pwdinfo->rx_invitereq_info.scan_op_ch_only = 0;
+	pwdinfo->p2p_info.operation_ch[0] = 0;
+	pwdinfo->p2p_info.operation_ch[1] = 0;			/*	Used to indicate the scan end in site survey function */
+#ifdef CONFIG_P2P_OP_CHK_SOCIAL_CH
+	pwdinfo->p2p_info.operation_ch[2] = 0;
+	pwdinfo->p2p_info.operation_ch[3] = 0;
+	pwdinfo->p2p_info.operation_ch[4] = 0;
+#endif /* CONFIG_P2P_OP_CHK_SOCIAL_CH */
+	pwdinfo->p2p_info.scan_op_ch_only = 0;
+}
+
+void _rtw_p2p_set_role(struct wifidirect_info *wdinfo, enum P2P_ROLE role)
+{
+	if (wdinfo->role != role) {
+		wdinfo->role = role;
+		rtw_mi_update_iface_status(&(wdinfo->padapter->mlmepriv), 0);
+	}
+}
+
+#ifdef CONFIG_DBG_P2P
+
+/**
+ * rtw_p2p_role_txt - Get the p2p role name as a text string
+ * @role: P2P role
+ * Returns: The state name as a printable text string
+ */
+const char *rtw_p2p_role_txt(enum P2P_ROLE role)
+{
+	switch (role) {
+	case P2P_ROLE_DISABLE:
+		return "P2P_ROLE_DISABLE";
+	case P2P_ROLE_DEVICE:
+		return "P2P_ROLE_DEVICE";
+	case P2P_ROLE_CLIENT:
+		return "P2P_ROLE_CLIENT";
+	case P2P_ROLE_GO:
+		return "P2P_ROLE_GO";
+	default:
+		return "UNKNOWN";
+	}
+}
+
+/**
+ * rtw_p2p_state_txt - Get the p2p state name as a text string
+ * @state: P2P state
+ * Returns: The state name as a printable text string
+ */
+const char *rtw_p2p_state_txt(enum P2P_STATE state)
+{
+	switch (state) {
+	case P2P_STATE_NONE:
+		return "P2P_STATE_NONE";
+	case P2P_STATE_IDLE:
+		return "P2P_STATE_IDLE";
+	case P2P_STATE_LISTEN:
+		return "P2P_STATE_LISTEN";
+	case P2P_STATE_SCAN:
+		return "P2P_STATE_SCAN";
+	case P2P_STATE_FIND_PHASE_LISTEN:
+		return "P2P_STATE_FIND_PHASE_LISTEN";
+	case P2P_STATE_FIND_PHASE_SEARCH:
+		return "P2P_STATE_FIND_PHASE_SEARCH";
+	case P2P_STATE_TX_PROVISION_DIS_REQ:
+		return "P2P_STATE_TX_PROVISION_DIS_REQ";
+	case P2P_STATE_RX_PROVISION_DIS_RSP:
+		return "P2P_STATE_RX_PROVISION_DIS_RSP";
+	case P2P_STATE_RX_PROVISION_DIS_REQ:
+		return "P2P_STATE_RX_PROVISION_DIS_REQ";
+	case P2P_STATE_GONEGO_ING:
+		return "P2P_STATE_GONEGO_ING";
+	case P2P_STATE_GONEGO_OK:
+		return "P2P_STATE_GONEGO_OK";
+	case P2P_STATE_GONEGO_FAIL:
+		return "P2P_STATE_GONEGO_FAIL";
+	case P2P_STATE_RECV_INVITE_REQ_MATCH:
+		return "P2P_STATE_RECV_INVITE_REQ_MATCH";
+	case P2P_STATE_PROVISIONING_ING:
+		return "P2P_STATE_PROVISIONING_ING";
+	case P2P_STATE_PROVISIONING_DONE:
+		return "P2P_STATE_PROVISIONING_DONE";
+	case P2P_STATE_TX_INVITE_REQ:
+		return "P2P_STATE_TX_INVITE_REQ";
+	case P2P_STATE_RX_INVITE_RESP_OK:
+		return "P2P_STATE_RX_INVITE_RESP_OK";
+	case P2P_STATE_RECV_INVITE_REQ_DISMATCH:
+		return "P2P_STATE_RECV_INVITE_REQ_DISMATCH";
+	case P2P_STATE_RECV_INVITE_REQ_GO:
+		return "P2P_STATE_RECV_INVITE_REQ_GO";
+	case P2P_STATE_RECV_INVITE_REQ_JOIN:
+		return "P2P_STATE_RECV_INVITE_REQ_JOIN";
+	case P2P_STATE_RX_INVITE_RESP_FAIL:
+		return "P2P_STATE_RX_INVITE_RESP_FAIL";
+	case P2P_STATE_RX_INFOR_NOREADY:
+		return "P2P_STATE_RX_INFOR_NOREADY";
+	case P2P_STATE_TX_INFOR_NOREADY:
+		return "P2P_STATE_TX_INFOR_NOREADY";
+	default:
+		return "UNKNOWN";
+	}
+}
+
+void dbg_rtw_p2p_set_state(struct wifidirect_info *wdinfo, enum P2P_STATE state, const char *caller, int line)
+{
+	if (!_rtw_p2p_chk_state(wdinfo, state)) {
+		enum P2P_STATE old_state = _rtw_p2p_state(wdinfo);
+		_rtw_p2p_set_state(wdinfo, state);
+		RTW_INFO("[CONFIG_DBG_P2P]%s:%d set_state from %s to %s\n", caller, line
+			, rtw_p2p_state_txt(old_state), rtw_p2p_state_txt(_rtw_p2p_state(wdinfo))
+			);
+	} else {
+		RTW_INFO("[CONFIG_DBG_P2P]%s:%d set_state to same state %s\n", caller, line
+			 , rtw_p2p_state_txt(_rtw_p2p_state(wdinfo))
+			);
+	}
+}
+void dbg_rtw_p2p_set_pre_state(struct wifidirect_info *wdinfo, enum P2P_STATE state, const char *caller, int line)
+{
+	if (_rtw_p2p_pre_state(wdinfo) != state) {
+		enum P2P_STATE old_state = _rtw_p2p_pre_state(wdinfo);
+		_rtw_p2p_set_pre_state(wdinfo, state);
+		RTW_INFO("[CONFIG_DBG_P2P]%s:%d set_pre_state from %s to %s\n", caller, line
+			, rtw_p2p_state_txt(old_state), rtw_p2p_state_txt(_rtw_p2p_pre_state(wdinfo))
+			);
+	} else {
+		RTW_INFO("[CONFIG_DBG_P2P]%s:%d set_pre_state to same state %s\n", caller, line
+			 , rtw_p2p_state_txt(_rtw_p2p_pre_state(wdinfo))
+			);
+	}
+}
+#if 0
+void dbg_rtw_p2p_restore_state(struct wifidirect_info *wdinfo, const char *caller, int line)
+{
+	if (wdinfo->pre_p2p_state != -1) {
+		RTW_INFO("[CONFIG_DBG_P2P]%s:%d restore from %s to %s\n", caller, line
+			, p2p_state_str[wdinfo->p2p_state], p2p_state_str[wdinfo->pre_p2p_state]
+			);
+		_rtw_p2p_restore_state(wdinfo);
+	} else {
+		RTW_INFO("[CONFIG_DBG_P2P]%s:%d restore no pre state, cur state %s\n", caller, line
+			 , p2p_state_str[wdinfo->p2p_state]
+			);
+	}
+}
+#endif
+void dbg_rtw_p2p_set_role(struct wifidirect_info *wdinfo, enum P2P_ROLE role, const char *caller, int line)
+{
+	if (wdinfo->role != role) {
+		enum P2P_ROLE old_role = wdinfo->role;
+		_rtw_p2p_set_role(wdinfo, role);
+		RTW_INFO("[CONFIG_DBG_P2P]%s:%d set_role from %s to %s\n", caller, line
+			, rtw_p2p_role_txt(old_role), rtw_p2p_role_txt(wdinfo->role)
+			);
+	} else {
+		RTW_INFO("[CONFIG_DBG_P2P]%s:%d set_role to same role %s\n", caller, line
+			 , rtw_p2p_role_txt(wdinfo->role)
+			);
+	}
+}
+#endif /* CONFIG_DBG_P2P */
+
+
+int rtw_p2p_enable(_adapter *padapter, enum P2P_ROLE role)
+{
+	int ret = _SUCCESS;
+	struct wifidirect_info *pwdinfo = &(padapter->wdinfo);
+
+	if (role == P2P_ROLE_DEVICE || role == P2P_ROLE_CLIENT || role == P2P_ROLE_GO) {
+#if defined(CONFIG_CONCURRENT_MODE) && (!defined(RTW_P2P_GROUP_INTERFACE) || !RTW_P2P_GROUP_INTERFACE)
+		/*	Commented by Albert 2011/12/30 */
+		/*	The driver just supports 1 P2P group operation. */
+		/*	So, this function will do nothing if the buddy adapter had enabled the P2P function. */
+		/*if(!rtw_p2p_chk_state(pbuddy_wdinfo, P2P_STATE_NONE))
+			return ret;*/
+		/*The buddy adapter had enabled the P2P function.*/
+		if (rtw_mi_buddy_stay_in_p2p_mode(padapter))
+			return ret;
+#endif /* CONFIG_CONCURRENT_MODE */
+
+		/* leave IPS/Autosuspend */
+		if (_FAIL == rtw_pwr_wakeup(padapter)) {
+			ret = _FAIL;
+			goto exit;
+		}
+
+		/*	Added by Albert 2011/03/22 */
+		/*	In the P2P mode, the driver should not support the b mode. */
+		/*	So, the Tx packet shouldn't use the CCK rate */
+		#ifdef CONFIG_IOCTL_CFG80211
+		if (rtw_cfg80211_iface_has_p2p_group_cap(padapter))
+		#endif
+			update_tx_basic_rate(padapter, WIRELESS_11AGN);
+
+		/* Enable P2P function */
+		init_wifidirect_info(padapter, role);
+
+		#ifdef CONFIG_IOCTL_CFG80211
+		if (padapter->wdinfo.driver_interface == DRIVER_CFG80211)
+			adapter_wdev_data(padapter)->p2p_enabled = _TRUE;
+		#endif
+
+		rtw_hal_set_odm_var(padapter, HAL_ODM_P2P_STATE, NULL, _TRUE);
+#ifdef CONFIG_WFD
+		if (hal_chk_wl_func(padapter, WL_FUNC_MIRACAST))
+			rtw_hal_set_odm_var(padapter, HAL_ODM_WIFI_DISPLAY_STATE, NULL, _TRUE);
+#endif
+
+	} else if (role == P2P_ROLE_DISABLE) {
+#ifdef CONFIG_INTEL_WIDI
+		if (padapter->mlmepriv.p2p_reject_disable == _TRUE)
+			return ret;
+#endif /* CONFIG_INTEL_WIDI */
+
+		#ifdef CONFIG_IOCTL_CFG80211
+		if (padapter->wdinfo.driver_interface == DRIVER_CFG80211)
+			adapter_wdev_data(padapter)->p2p_enabled = _FALSE;
+		#endif
+
+		pwdinfo->listen_channel = 0;
+
+		/* Disable P2P function */
+		if (!rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE)) {
+			_cancel_timer_ex(&pwdinfo->find_phase_timer);
+			_cancel_timer_ex(&pwdinfo->restore_p2p_state_timer);
+			_cancel_timer_ex(&pwdinfo->pre_tx_scan_timer);
+			_cancel_timer_ex(&pwdinfo->reset_ch_sitesurvey);
+			_cancel_timer_ex(&pwdinfo->reset_ch_sitesurvey2);
+			reset_ch_sitesurvey_timer_process(padapter);
+			reset_ch_sitesurvey_timer_process2(padapter);
+#ifdef CONFIG_CONCURRENT_MODE
+			_cancel_timer_ex(&pwdinfo->ap_p2p_switch_timer);
+#endif
+			rtw_p2p_set_state(pwdinfo, P2P_STATE_NONE);
+			rtw_p2p_set_pre_state(pwdinfo, P2P_STATE_NONE);
+			rtw_p2p_set_role(pwdinfo, P2P_ROLE_DISABLE);
+			_rtw_memset(&pwdinfo->rx_prov_disc_info, 0x00, sizeof(struct rx_provdisc_req_info));
+
+			/* Remove profiles in wifidirect_info structure. */
+			_rtw_memset(&pwdinfo->profileinfo[0], 0x00, sizeof(struct profile_info) * P2P_MAX_PERSISTENT_GROUP_NUM);
+			pwdinfo->profileindex = 0;
+		}
+
+		rtw_hal_set_odm_var(padapter, HAL_ODM_P2P_STATE, NULL, _FALSE);
+#ifdef CONFIG_WFD
+		if (hal_chk_wl_func(padapter, WL_FUNC_MIRACAST))
+			rtw_hal_set_odm_var(padapter, HAL_ODM_WIFI_DISPLAY_STATE, NULL, _FALSE);
+#endif
+
+		if (_FAIL == rtw_pwr_wakeup(padapter)) {
+			ret = _FAIL;
+			goto exit;
+		}
+
+		/* Restore to initial setting. */
+		update_tx_basic_rate(padapter, padapter->registrypriv.wireless_mode);
+
+#ifdef CONFIG_INTEL_WIDI
+		rtw_reset_widi_info(padapter);
+#endif /* CONFIG_INTEL_WIDI */
+
+		/* For WiDi purpose. */
+#ifdef CONFIG_IOCTL_CFG80211
+		pwdinfo->driver_interface = DRIVER_CFG80211;
+#else
+		pwdinfo->driver_interface = DRIVER_WEXT;
+#endif /* CONFIG_IOCTL_CFG80211 */
+
+	}
+
+exit:
+	return ret;
+}
+
+#endif /* CONFIG_P2P */
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/core/rtw_pwrctrl.c linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/core/rtw_pwrctrl.c
--- linux-5.6.3/3rdparty/rtl8821ce/core/rtw_pwrctrl.c	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/core/rtw_pwrctrl.c	2020-04-10 16:35:06.777658247 +0300
@@ -0,0 +1,2780 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#define _RTW_PWRCTRL_C_
+
+#include <drv_types.h>
+#include <hal_data.h>
+#include <hal_com_h2c.h>
+
+#ifdef DBG_CHECK_FW_PS_STATE
+int rtw_fw_ps_state(PADAPTER padapter)
+{
+	struct dvobj_priv *psdpriv = padapter->dvobj;
+	struct debug_priv *pdbgpriv = &psdpriv->drv_dbg;
+	int ret = _FAIL, dont_care = 0;
+	u16 fw_ps_state = 0;
+	struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter);
+	struct registry_priv  *registry_par = &padapter->registrypriv;
+
+	if (registry_par->check_fw_ps != 1)
+		return _SUCCESS;
+
+	_enter_pwrlock(&pwrpriv->check_32k_lock);
+
+	if (RTW_CANNOT_RUN(padapter)) {
+		RTW_INFO("%s: bSurpriseRemoved=%s , hw_init_completed=%d, bDriverStopped=%s\n", __func__
+			 , rtw_is_surprise_removed(padapter) ? "True" : "False"
+			 , rtw_get_hw_init_completed(padapter)
+			 , rtw_is_drv_stopped(padapter) ? "True" : "False");
+		goto exit_fw_ps_state;
+	}
+	#if defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C) || defined(CONFIG_RTL8822C)
+	rtw_hal_get_hwreg(padapter, HW_VAR_FW_PS_STATE, (u8 *)&fw_ps_state);
+	if ((fw_ps_state & BIT_LPS_STATUS) == 0)
+		ret = _SUCCESS;
+	else {
+		pdbgpriv->dbg_poll_fail_cnt++;
+		RTW_INFO("%s: fw_ps_state=%04x\n", __FUNCTION__, fw_ps_state);
+	}
+	#else
+	rtw_hal_set_hwreg(padapter, HW_VAR_SET_REQ_FW_PS, (u8 *)&dont_care);
+	{
+		/* 4. if 0x88[7]=1, driver set cmd to leave LPS/IPS. */
+		/* Else, hw will keep in active mode. */
+		/* debug info: */
+		/* 0x88[7] = 32kpermission, */
+		/* 0x88[6:0] = current_ps_state */
+		/* 0x89[7:0] = last_rpwm */
+
+		rtw_hal_get_hwreg(padapter, HW_VAR_FW_PS_STATE, (u8 *)&fw_ps_state);
+
+		if ((fw_ps_state & 0x80) == 0)
+			ret = _SUCCESS;
+		else {
+			pdbgpriv->dbg_poll_fail_cnt++;
+			RTW_INFO("%s: fw_ps_state=%04x\n", __FUNCTION__, fw_ps_state);
+		}
+	}
+	#endif
+
+exit_fw_ps_state:
+	_exit_pwrlock(&pwrpriv->check_32k_lock);
+	return ret;
+}
+#endif /*DBG_CHECK_FW_PS_STATE*/
+#ifdef CONFIG_IPS
+void _ips_enter(_adapter *padapter)
+{
+	struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter);
+
+	pwrpriv->bips_processing = _TRUE;
+
+	/* syn ips_mode with request */
+	pwrpriv->ips_mode = pwrpriv->ips_mode_req;
+
+	pwrpriv->ips_enter_cnts++;
+	RTW_INFO("==>ips_enter cnts:%d\n", pwrpriv->ips_enter_cnts);
+
+	if (rf_off == pwrpriv->change_rfpwrstate) {
+		pwrpriv->bpower_saving = _TRUE;
+		RTW_PRINT("nolinked power save enter\n");
+
+		if (pwrpriv->ips_mode == IPS_LEVEL_2)
+			pwrpriv->bkeepfwalive = _TRUE;
+
+#ifdef CONFIG_RTW_CFGVEDNOR_LLSTATS		
+		pwrpriv->pwr_saving_start_time = rtw_get_current_time();
+#endif /* CONFIG_RTW_CFGVEDNOR_LLSTATS */
+
+		rtw_ips_pwr_down(padapter);
+		pwrpriv->rf_pwrstate = rf_off;
+	}
+	pwrpriv->bips_processing = _FALSE;
+
+}
+
+void ips_enter(_adapter *padapter)
+{
+	struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter);
+
+
+#ifdef CONFIG_BT_COEXIST
+	rtw_btcoex_IpsNotify(padapter, pwrpriv->ips_mode_req);
+#endif /* CONFIG_BT_COEXIST */
+
+	_enter_pwrlock(&pwrpriv->lock);
+	_ips_enter(padapter);
+	_exit_pwrlock(&pwrpriv->lock);
+}
+
+int _ips_leave(_adapter *padapter)
+{
+	struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter);
+	int result = _SUCCESS;
+
+	if ((pwrpriv->rf_pwrstate == rf_off) && (!pwrpriv->bips_processing)) {
+		pwrpriv->bips_processing = _TRUE;
+		pwrpriv->change_rfpwrstate = rf_on;
+		pwrpriv->ips_leave_cnts++;
+		RTW_INFO("==>ips_leave cnts:%d\n", pwrpriv->ips_leave_cnts);
+
+		result = rtw_ips_pwr_up(padapter);
+		if (result == _SUCCESS)
+			pwrpriv->rf_pwrstate = rf_on;
+		
+#ifdef CONFIG_RTW_CFGVEDNOR_LLSTATS	
+		pwrpriv->pwr_saving_time += rtw_get_passing_time_ms(pwrpriv->pwr_saving_start_time);
+#endif /* CONFIG_RTW_CFGVEDNOR_LLSTATS */
+
+		RTW_PRINT("nolinked power save leave\n");
+
+		RTW_INFO("==> ips_leave.....LED(0x%08x)...\n", rtw_read32(padapter, 0x4c));
+		pwrpriv->bips_processing = _FALSE;
+
+		pwrpriv->bkeepfwalive = _FALSE;
+		pwrpriv->bpower_saving = _FALSE;
+	}
+
+	return result;
+}
+
+int ips_leave(_adapter *padapter)
+{
+	struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter);
+#ifdef DBG_CHECK_FW_PS_STATE
+	struct dvobj_priv *psdpriv = padapter->dvobj;
+	struct debug_priv *pdbgpriv = &psdpriv->drv_dbg;
+#endif
+	int ret;
+
+	if (!is_primary_adapter(padapter))
+		return _SUCCESS;
+
+	_enter_pwrlock(&pwrpriv->lock);
+	ret = _ips_leave(padapter);
+#ifdef DBG_CHECK_FW_PS_STATE
+	if (rtw_fw_ps_state(padapter) == _FAIL) {
+		RTW_INFO("ips leave doesn't leave 32k\n");
+		pdbgpriv->dbg_leave_ips_fail_cnt++;
+	}
+#endif /* DBG_CHECK_FW_PS_STATE */
+	_exit_pwrlock(&pwrpriv->lock);
+
+	if (_SUCCESS == ret)
+		odm_dm_reset(&GET_HAL_DATA(padapter)->odmpriv);
+
+#ifdef CONFIG_BT_COEXIST
+	if (_SUCCESS == ret)
+		rtw_btcoex_IpsNotify(padapter, IPS_NONE);
+#endif /* CONFIG_BT_COEXIST */
+
+	return ret;
+}
+#endif /* CONFIG_IPS */
+
+#ifdef CONFIG_AUTOSUSPEND
+	extern void autosuspend_enter(_adapter *padapter);
+	extern int autoresume_enter(_adapter *padapter);
+#endif
+
+#ifdef SUPPORT_HW_RFOFF_DETECTED
+	int rtw_hw_suspend(_adapter *padapter);
+	int rtw_hw_resume(_adapter *padapter);
+#endif
+
+bool rtw_pwr_unassociated_idle(_adapter *adapter)
+{
+	u8 i;
+	_adapter *iface;
+	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
+	struct xmit_priv *pxmit_priv = &adapter->xmitpriv;
+	struct mlme_priv *pmlmepriv;
+#ifdef CONFIG_P2P
+	struct wifidirect_info	*pwdinfo;
+#endif
+
+	bool ret = _FALSE;
+
+	if (adapter_to_pwrctl(adapter)->bpower_saving == _TRUE) {
+		/* RTW_INFO("%s: already in LPS or IPS mode\n", __func__); */
+		goto exit;
+	}
+
+	if (rtw_time_after(adapter_to_pwrctl(adapter)->ips_deny_time, rtw_get_current_time())) {
+		/* RTW_INFO("%s ips_deny_time\n", __func__); */
+		goto exit;
+	}
+
+	for (i = 0; i < dvobj->iface_nums; i++) {
+		iface = dvobj->padapters[i];
+		if ((iface) && rtw_is_adapter_up(iface)) {
+			pmlmepriv = &(iface->mlmepriv);
+#ifdef CONFIG_P2P
+			pwdinfo = &(iface->wdinfo);
+#endif
+			if (check_fwstate(pmlmepriv, WIFI_ASOC_STATE | WIFI_SITE_MONITOR)
+				|| check_fwstate(pmlmepriv, WIFI_UNDER_LINKING | WIFI_UNDER_WPS)
+				|| MLME_IS_AP(iface)
+				|| MLME_IS_MESH(iface)
+				|| check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE | WIFI_ADHOC_STATE)
+				#if defined(CONFIG_P2P) && defined(CONFIG_IOCTL_CFG80211)
+				|| rtw_cfg80211_get_is_roch(iface) == _TRUE
+				|| (rtw_cfg80211_is_ro_ch_once(adapter)
+					&& rtw_cfg80211_get_last_ro_ch_passing_ms(adapter) < 3000)
+				#elif defined(CONFIG_P2P)
+				|| rtw_p2p_chk_state(pwdinfo, P2P_STATE_IDLE)
+				|| rtw_p2p_chk_state(pwdinfo, P2P_STATE_LISTEN)
+				#endif
+			)
+				goto exit;
+
+		}
+	}
+
+#if (MP_DRIVER == 1)
+	if (adapter->registrypriv.mp_mode == 1)
+		goto exit;
+#endif
+
+#ifdef CONFIG_INTEL_PROXIM
+	if (adapter->proximity.proxim_on == _TRUE)
+		return;
+#endif
+
+	if (pxmit_priv->free_xmitbuf_cnt != NR_XMITBUFF ||
+	    pxmit_priv->free_xmit_extbuf_cnt != NR_XMIT_EXTBUFF) {
+		RTW_PRINT("There are some pkts to transmit\n");
+		RTW_PRINT("free_xmitbuf_cnt: %d, free_xmit_extbuf_cnt: %d\n",
+			pxmit_priv->free_xmitbuf_cnt, pxmit_priv->free_xmit_extbuf_cnt);
+		goto exit;
+	}
+
+	ret = _TRUE;
+
+exit:
+	return ret;
+}
+
+
+/*
+ * ATTENTION:
+ *	rtw_ps_processor() doesn't handle LPS.
+ */
+void rtw_ps_processor(_adapter *padapter)
+{
+	struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter);
+	struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
+	struct dvobj_priv *psdpriv = padapter->dvobj;
+	struct debug_priv *pdbgpriv = &psdpriv->drv_dbg;
+#ifdef SUPPORT_HW_RFOFF_DETECTED
+	rt_rf_power_state rfpwrstate;
+#endif /* SUPPORT_HW_RFOFF_DETECTED */
+	u32 ps_deny = 0;
+
+	_enter_pwrlock(&adapter_to_pwrctl(padapter)->lock);
+	ps_deny = rtw_ps_deny_get(padapter);
+	_exit_pwrlock(&adapter_to_pwrctl(padapter)->lock);
+	if (ps_deny != 0) {
+		RTW_INFO(FUNC_ADPT_FMT ": ps_deny=0x%08X, skip power save!\n",
+			 FUNC_ADPT_ARG(padapter), ps_deny);
+		goto exit;
+	}
+
+	if (pwrpriv->bInSuspend == _TRUE) { /* system suspend or autosuspend */
+		pdbgpriv->dbg_ps_insuspend_cnt++;
+		RTW_INFO("%s, pwrpriv->bInSuspend == _TRUE ignore this process\n", __FUNCTION__);
+		return;
+	}
+
+	pwrpriv->ps_processing = _TRUE;
+
+#ifdef SUPPORT_HW_RFOFF_DETECTED
+	if (pwrpriv->bips_processing == _TRUE)
+		goto exit;
+
+	/* RTW_INFO("==> fw report state(0x%x)\n",rtw_read8(padapter,0x1ca));	 */
+	if (pwrpriv->bHWPwrPindetect) {
+#ifdef CONFIG_AUTOSUSPEND
+		if (padapter->registrypriv.usbss_enable) {
+			if (pwrpriv->rf_pwrstate == rf_on) {
+				if (padapter->net_closed == _TRUE)
+					pwrpriv->ps_flag = _TRUE;
+
+				rfpwrstate = RfOnOffDetect(padapter);
+				RTW_INFO("@@@@- #1  %s==> rfstate:%s\n", __FUNCTION__, (rfpwrstate == rf_on) ? "rf_on" : "rf_off");
+				if (rfpwrstate != pwrpriv->rf_pwrstate) {
+					if (rfpwrstate == rf_off) {
+						pwrpriv->change_rfpwrstate = rf_off;
+
+						pwrpriv->bkeepfwalive = _TRUE;
+						pwrpriv->brfoffbyhw = _TRUE;
+
+						autosuspend_enter(padapter);
+					}
+				}
+			}
+		} else
+#endif /* CONFIG_AUTOSUSPEND */
+		{
+			rfpwrstate = RfOnOffDetect(padapter);
+			RTW_INFO("@@@@- #2  %s==> rfstate:%s\n", __FUNCTION__, (rfpwrstate == rf_on) ? "rf_on" : "rf_off");
+
+			if (rfpwrstate != pwrpriv->rf_pwrstate) {
+				if (rfpwrstate == rf_off) {
+					pwrpriv->change_rfpwrstate = rf_off;
+					pwrpriv->brfoffbyhw = _TRUE;
+					rtw_hw_suspend(padapter);
+				} else {
+					pwrpriv->change_rfpwrstate = rf_on;
+					rtw_hw_resume(padapter);
+				}
+				RTW_INFO("current rf_pwrstate(%s)\n", (pwrpriv->rf_pwrstate == rf_off) ? "rf_off" : "rf_on");
+			}
+		}
+		pwrpriv->pwr_state_check_cnts++;
+	}
+#endif /* SUPPORT_HW_RFOFF_DETECTED */
+
+	if (pwrpriv->ips_mode_req == IPS_NONE)
+		goto exit;
+
+	if (rtw_pwr_unassociated_idle(padapter) == _FALSE)
+		goto exit;
+
+	if ((pwrpriv->rf_pwrstate == rf_on) && ((pwrpriv->pwr_state_check_cnts % 4) == 0)) {
+		RTW_INFO("==>%s .fw_state(%x)\n", __FUNCTION__, get_fwstate(pmlmepriv));
+#if defined(CONFIG_BT_COEXIST) && defined (CONFIG_AUTOSUSPEND)
+#else
+		pwrpriv->change_rfpwrstate = rf_off;
+#endif
+#ifdef CONFIG_AUTOSUSPEND
+		if (padapter->registrypriv.usbss_enable) {
+			if (pwrpriv->bHWPwrPindetect)
+				pwrpriv->bkeepfwalive = _TRUE;
+
+			if (padapter->net_closed == _TRUE)
+				pwrpriv->ps_flag = _TRUE;
+
+#if defined(CONFIG_BT_COEXIST) && defined (CONFIG_AUTOSUSPEND)
+			if (_TRUE == pwrpriv->bInternalAutoSuspend)
+				RTW_INFO("<==%s .pwrpriv->bInternalAutoSuspend)(%x)\n", __FUNCTION__, pwrpriv->bInternalAutoSuspend);
+			else {
+				pwrpriv->change_rfpwrstate = rf_off;
+				RTW_INFO("<==%s .pwrpriv->bInternalAutoSuspend)(%x) call autosuspend_enter\n", __FUNCTION__, pwrpriv->bInternalAutoSuspend);
+				autosuspend_enter(padapter);
+			}
+#else
+			autosuspend_enter(padapter);
+#endif	/* if defined (CONFIG_BT_COEXIST)&& defined (CONFIG_AUTOSUSPEND) */
+		} else if (pwrpriv->bHWPwrPindetect) {
+		} else
+#endif /* CONFIG_AUTOSUSPEND */
+		{
+#if defined(CONFIG_BT_COEXIST) && defined (CONFIG_AUTOSUSPEND)
+			pwrpriv->change_rfpwrstate = rf_off;
+#endif	/* defined (CONFIG_BT_COEXIST)&& defined (CONFIG_AUTOSUSPEND) */
+
+#ifdef CONFIG_IPS
+			ips_enter(padapter);
+#endif
+		}
+	}
+exit:
+#ifndef CONFIG_IPS_CHECK_IN_WD
+	rtw_set_pwr_state_check_timer(pwrpriv);
+#endif
+	pwrpriv->ps_processing = _FALSE;
+	return;
+}
+
+void pwr_state_check_handler(void *ctx)
+{
+	_adapter *padapter = (_adapter *)ctx;
+	rtw_ps_cmd(padapter);
+}
+
+#ifdef CONFIG_LPS
+#ifdef CONFIG_CHECK_LEAVE_LPS
+#ifdef CONFIG_LPS_CHK_BY_TP
+void traffic_check_for_leave_lps_by_tp(PADAPTER padapter, u8 tx, struct sta_info *sta)
+{
+	struct stainfo_stats *pstats = &sta->sta_stats;
+	u64 cur_acc_tx_bytes = 0, cur_acc_rx_bytes = 0;
+	u32 tx_tp_kbyte = 0, rx_tp_kbyte = 0;
+	u32 tx_tp_th = 0, rx_tp_th = 0;
+	struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter);
+	u8	leave_lps = _FALSE;
+
+	if (tx) { /* from tx */
+		cur_acc_tx_bytes = pstats->tx_bytes - pstats->acc_tx_bytes;
+		tx_tp_kbyte = cur_acc_tx_bytes >> 10;
+		tx_tp_th = pwrpriv->lps_tx_tp_th * 1024 / 8 * 2; /*KBytes @2s*/
+
+		if (tx_tp_kbyte >= tx_tp_th ||
+			padapter->mlmepriv.LinkDetectInfo.NumTxOkInPeriod >= pwrpriv->lps_tx_pkts){
+			if (pwrpriv->bLeisurePs
+				&& (pwrpriv->pwr_mode != PS_MODE_ACTIVE)
+				#ifdef CONFIG_BT_COEXIST
+				&& (rtw_btcoex_IsBtControlLps(padapter) == _FALSE)
+				#endif
+			) {
+				leave_lps = _TRUE;
+			}
+		}
+
+	} else { /* from rx path */
+		cur_acc_rx_bytes = pstats->rx_bytes - pstats->acc_rx_bytes;
+		rx_tp_kbyte = cur_acc_rx_bytes >> 10;
+		rx_tp_th = pwrpriv->lps_rx_tp_th * 1024 / 8 * 2;
+
+		if (rx_tp_kbyte>= rx_tp_th ||
+			padapter->mlmepriv.LinkDetectInfo.NumRxUnicastOkInPeriod >= pwrpriv->lps_rx_pkts) {
+			if (pwrpriv->bLeisurePs
+				&& (pwrpriv->pwr_mode != PS_MODE_ACTIVE)
+				#ifdef CONFIG_BT_COEXIST
+				&& (rtw_btcoex_IsBtControlLps(padapter) == _FALSE)
+				#endif
+			) {
+				leave_lps = _TRUE;
+			}
+		}
+	}
+
+	if (leave_lps) {
+		#ifdef DBG_LPS_CHK_BY_TP
+		RTW_INFO("leave lps via %s, ", tx ? "Tx" : "Rx");
+		if (tx)
+			RTW_INFO("Tx = %d [%d] (KB)\n", tx_tp_kbyte, tx_tp_th);
+		else
+			RTW_INFO("Rx = %d [%d] (KB)\n", rx_tp_kbyte, rx_tp_th);
+		#endif
+		pwrpriv->lps_chk_cnt = pwrpriv->lps_chk_cnt_th;
+		/* rtw_lps_ctrl_wk_cmd(padapter, LPS_CTRL_LEAVE, 1); */
+		rtw_lps_ctrl_wk_cmd(padapter, tx ? LPS_CTRL_TX_TRAFFIC_LEAVE : LPS_CTRL_RX_TRAFFIC_LEAVE, 1);
+	}
+}
+#endif /*CONFIG_LPS_CHK_BY_TP*/
+
+void	traffic_check_for_leave_lps(PADAPTER padapter, u8 tx, u32 tx_packets)
+{
+	static systime start_time = 0;
+	static u32 xmit_cnt = 0;
+	u8	bLeaveLPS = _FALSE;
+	struct mlme_priv	*pmlmepriv = &padapter->mlmepriv;
+
+
+
+	if (tx) { /* from tx */
+		xmit_cnt += tx_packets;
+
+		if (start_time == 0)
+			start_time = rtw_get_current_time();
+
+		if (rtw_get_passing_time_ms(start_time) > 2000) { /* 2 sec == watch dog timer */
+			if (xmit_cnt > 8) {
+				if ((adapter_to_pwrctl(padapter)->bLeisurePs)
+				    && (adapter_to_pwrctl(padapter)->pwr_mode != PS_MODE_ACTIVE)
+#ifdef CONFIG_BT_COEXIST
+				    && (rtw_btcoex_IsBtControlLps(padapter) == _FALSE)
+#endif
+				   ) {
+					/* RTW_INFO("leave lps via Tx = %d\n", xmit_cnt);			 */
+					bLeaveLPS = _TRUE;
+				}
+			}
+
+			start_time = rtw_get_current_time();
+			xmit_cnt = 0;
+		}
+
+	} else { /* from rx path */
+		if (pmlmepriv->LinkDetectInfo.NumRxUnicastOkInPeriod > 4/*2*/) {
+			if ((adapter_to_pwrctl(padapter)->bLeisurePs)
+			    && (adapter_to_pwrctl(padapter)->pwr_mode != PS_MODE_ACTIVE)
+#ifdef CONFIG_BT_COEXIST
+			    && (rtw_btcoex_IsBtControlLps(padapter) == _FALSE)
+#endif
+			   ) {
+				/* RTW_INFO("leave lps via Rx = %d\n", pmlmepriv->LinkDetectInfo.NumRxUnicastOkInPeriod);	 */
+				bLeaveLPS = _TRUE;
+			}
+		}
+	}
+
+	if (bLeaveLPS) {
+		/* RTW_INFO("leave lps via %s, Tx = %d, Rx = %d\n", tx?"Tx":"Rx", pmlmepriv->LinkDetectInfo.NumTxOkInPeriod,pmlmepriv->LinkDetectInfo.NumRxUnicastOkInPeriod);	 */
+		/* rtw_lps_ctrl_wk_cmd(padapter, LPS_CTRL_LEAVE, 1); */
+		rtw_lps_ctrl_wk_cmd(padapter, tx ? LPS_CTRL_TX_TRAFFIC_LEAVE : LPS_CTRL_RX_TRAFFIC_LEAVE, tx ? 0 : 1);
+	}
+}
+#endif /* CONFIG_CHECK_LEAVE_LPS */
+
+#ifdef CONFIG_LPS_LCLK
+#define LPS_CPWM_TIMEOUT_MS	10 /*ms*/
+#define LPS_RPWM_RETRY_CNT		3
+
+u8 rtw_cpwm_polling(_adapter *adapter, u8 rpwm, u8 cpwm_orig)
+{
+	u8 rst = _FAIL;
+	u8 cpwm_now = 0;
+	systime start_time;
+	struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(adapter);
+	#ifdef DBG_CHECK_FW_PS_STATE
+	struct debug_priv *pdbgpriv = &(adapter_to_dvobj(adapter)->drv_dbg);
+	#endif
+
+	pwrpriv->rpwm_retry = 0;
+
+	do {
+		start_time = rtw_get_current_time();
+		do {
+			rtw_msleep_os(1);
+			rtw_hal_get_hwreg(adapter, HW_VAR_CPWM, &cpwm_now);
+
+			if ((cpwm_orig ^ cpwm_now) & 0x80) {
+				pwrpriv->cpwm = PS_STATE_S4;
+				pwrpriv->cpwm_tog = cpwm_now & PS_TOGGLE;
+				rst = _SUCCESS;
+				break;
+			}
+		} while (rtw_get_passing_time_ms(start_time) < LPS_CPWM_TIMEOUT_MS && !RTW_CANNOT_RUN(adapter));
+
+		if (rst == _SUCCESS)
+			break;
+		else {
+			/* rpwm retry */
+			cpwm_orig = cpwm_now;
+			rpwm &= ~PS_TOGGLE;
+			rpwm |= pwrpriv->tog;
+			rtw_hal_set_hwreg(adapter, HW_VAR_SET_RPWM, (u8 *)(&rpwm));
+			pwrpriv->tog += 0x80;
+		}
+	} while (pwrpriv->rpwm_retry++ < LPS_RPWM_RETRY_CNT && !RTW_CANNOT_RUN(adapter));
+
+	if (rst == _SUCCESS) {
+		#ifdef DBG_CHECK_FW_PS_STATE
+		RTW_INFO("%s: polling cpwm OK! rpwm_retry=%d, cpwm_orig=%02x, cpwm_now=%02x , 0x100=0x%x\n"
+			, __func__, pwrpriv->rpwm_retry, cpwm_orig, cpwm_now, rtw_read8(adapter, REG_CR));
+		if (rtw_fw_ps_state(adapter) == _FAIL) {
+			RTW_INFO("leave 32k but fw state in 32k\n");
+			pdbgpriv->dbg_rpwm_toogle_cnt++;
+		}
+		#endif /* DBG_CHECK_FW_PS_STATE */
+	} else {
+		RTW_ERR("%s: polling cpwm timeout! rpwm_retry=%d, cpwm_orig=%02x, cpwm_now=%02x\n"
+				, __func__, pwrpriv->rpwm_retry, cpwm_orig, cpwm_now);
+		#ifdef DBG_CHECK_FW_PS_STATE
+		if (rtw_fw_ps_state(adapter) == _FAIL) {
+			RTW_INFO("rpwm timeout and fw ps state in 32k\n");
+			pdbgpriv->dbg_rpwm_timeout_fail_cnt++;
+		}
+		#endif /* DBG_CHECK_FW_PS_STATE */
+
+		#ifdef CONFIG_LPS_RPWM_TIMER
+		_set_timer(&pwrpriv->pwr_rpwm_timer, 1);
+		#endif /* CONFIG_LPS_RPWM_TIMER */
+	}
+
+	return rst;
+}
+#endif
+/*
+ * Description:
+ *	This function MUST be called under power lock protect
+ *
+ * Parameters
+ *	padapter
+ *	pslv			power state level, only could be PS_STATE_S0 ~ PS_STATE_S4
+ *
+ */
+u8 rtw_set_rpwm(PADAPTER padapter, u8 pslv)
+{
+	u8	rpwm = 0xFF;
+	struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter);
+#ifdef CONFIG_LPS_LCLK
+	u8 cpwm_orig;
+#endif
+
+	pslv = PS_STATE(pslv);
+
+#ifdef CONFIG_LPS_RPWM_TIMER
+	if (pwrpriv->brpwmtimeout == _TRUE)
+		RTW_INFO("%s: RPWM timeout, force to set RPWM(0x%02X) again!\n", __FUNCTION__, pslv);
+	else
+#endif /* CONFIG_LPS_RPWM_TIMER */
+	{
+		if ((pwrpriv->rpwm == pslv)
+#ifdef CONFIG_LPS_LCLK
+		    || ((pwrpriv->rpwm >= PS_STATE_S2) && (pslv >= PS_STATE_S2))
+#endif
+			|| (pwrpriv->lps_level == LPS_NORMAL)
+		   ) {
+			return rpwm;
+		}
+	}
+
+	if (rtw_is_surprise_removed(padapter) ||
+	    (!rtw_is_hw_init_completed(padapter))) {
+
+		pwrpriv->cpwm = PS_STATE_S4;
+
+		return rpwm;
+	}
+
+	if (rtw_is_drv_stopped(padapter))
+		if (pslv < PS_STATE_S2)
+			return rpwm;
+
+	rpwm = pslv | pwrpriv->tog;
+#ifdef CONFIG_LPS_LCLK
+	/* only when from PS_STATE S0/S1 to S2 and higher needs ACK */
+	if ((pwrpriv->cpwm < PS_STATE_S2) && (pslv >= PS_STATE_S2))
+		rpwm |= PS_ACK;
+#endif
+
+	pwrpriv->rpwm = pslv;
+
+#ifdef CONFIG_LPS_LCLK
+	cpwm_orig = 0;
+	if (rpwm & PS_ACK)
+		rtw_hal_get_hwreg(padapter, HW_VAR_CPWM, &cpwm_orig);
+#endif
+
+#if defined(CONFIG_LPS_RPWM_TIMER) && !defined(CONFIG_DETECT_CPWM_BY_POLLING)
+	if (rpwm & PS_ACK) {
+		#if defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN) || defined(CONFIG_P2P_WOWLAN)
+		if (pwrpriv->wowlan_mode != _TRUE &&
+			pwrpriv->wowlan_ap_mode != _TRUE &&
+			pwrpriv->wowlan_p2p_mode != _TRUE)
+		#endif
+		_set_timer(&pwrpriv->pwr_rpwm_timer, LPS_CPWM_TIMEOUT_MS);
+	}
+#endif /* CONFIG_LPS_RPWM_TIMER & !CONFIG_DETECT_CPWM_BY_POLLING */
+
+	rtw_hal_set_hwreg(padapter, HW_VAR_SET_RPWM, (u8 *)(&rpwm));
+
+	pwrpriv->tog += 0x80;
+
+#ifdef CONFIG_LPS_LCLK
+	/* No LPS 32K, No Ack */
+	if (rpwm & PS_ACK) {
+		#ifdef CONFIG_DETECT_CPWM_BY_POLLING
+		rtw_cpwm_polling(padapter, rpwm, cpwm_orig);
+		#else
+		#if defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN) || defined(CONFIG_P2P_WOWLAN)
+		if (pwrpriv->wowlan_mode == _TRUE ||
+			pwrpriv->wowlan_ap_mode == _TRUE ||
+			pwrpriv->wowlan_p2p_mode == _TRUE)
+				rtw_cpwm_polling(padapter, rpwm, cpwm_orig);
+		#endif /*#if defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN) || defined(CONFIG_P2P_WOWLAN)*/
+		#endif /*#ifdef CONFIG_DETECT_CPWM_BY_POLLING*/
+	} else
+#endif /* CONFIG_LPS_LCLK */
+	{
+		pwrpriv->cpwm = pslv;
+	}
+
+	return rpwm;
+}
+
+u8 PS_RDY_CHECK(_adapter *padapter)
+{
+	u32 delta_ms;
+	struct pwrctrl_priv	*pwrpriv = adapter_to_pwrctl(padapter);
+	struct mlme_priv	*pmlmepriv = &(padapter->mlmepriv);
+
+#if defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN)
+	if (_TRUE == pwrpriv->bInSuspend && pwrpriv->wowlan_mode)
+		return _TRUE;
+	else if (_TRUE == pwrpriv->bInSuspend && pwrpriv->wowlan_ap_mode)
+		return _TRUE;
+	else if (_TRUE == pwrpriv->bInSuspend)
+		return _FALSE;
+#else
+	if (_TRUE == pwrpriv->bInSuspend)
+		return _FALSE;
+#endif
+
+	delta_ms = rtw_get_passing_time_ms(pwrpriv->DelayLPSLastTimeStamp);
+	if (delta_ms < LPS_DELAY_MS)
+		return _FALSE;
+
+	if (check_fwstate(pmlmepriv, WIFI_SITE_MONITOR)
+		|| check_fwstate(pmlmepriv, WIFI_UNDER_LINKING | WIFI_UNDER_WPS)
+		|| MLME_IS_AP(padapter)
+		|| MLME_IS_MESH(padapter)
+		|| check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE | WIFI_ADHOC_STATE)
+		#if defined(CONFIG_P2P) && defined(CONFIG_IOCTL_CFG80211)
+		|| rtw_cfg80211_get_is_roch(padapter) == _TRUE
+		#endif
+		|| rtw_is_scan_deny(padapter)
+		#ifdef CONFIG_TDLS
+		/* TDLS link is established. */
+		|| (padapter->tdlsinfo.link_established == _TRUE)
+		#endif /* CONFIG_TDLS		 */
+		#ifdef CONFIG_DFS_MASTER
+		|| adapter_to_rfctl(padapter)->radar_detect_enabled
+		#endif
+	)
+		return _FALSE;
+
+	if ((padapter->securitypriv.dot11AuthAlgrthm == dot11AuthAlgrthm_8021X) && (padapter->securitypriv.binstallGrpkey == _FALSE)) {
+		RTW_INFO("Group handshake still in progress !!!\n");
+		return _FALSE;
+	}
+
+#ifdef CONFIG_IOCTL_CFG80211
+	if (!rtw_cfg80211_pwr_mgmt(padapter))
+		return _FALSE;
+#endif
+
+	return _TRUE;
+}
+
+#if defined(CONFIG_FWLPS_IN_IPS)
+void rtw_set_fw_in_ips_mode(PADAPTER padapter, u8 enable)
+{
+	struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter);
+	int cnt = 0;
+	systime start_time;
+	u8 val8 = 0;
+	u8 cpwm_orig = 0, cpwm_now = 0;
+	u8 parm[H2C_INACTIVE_PS_LEN] = {0};
+
+	if (padapter->netif_up == _FALSE) {
+		RTW_INFO("%s: ERROR, netif is down\n", __func__);
+		return;
+	}
+
+	/* u8 cmd_param; */ /* BIT0:enable, BIT1:NoConnect32k */
+	if (enable) {
+#ifdef CONFIG_BT_COEXIST
+		rtw_btcoex_IpsNotify(padapter, pwrpriv->ips_mode_req);
+#endif
+		/* Enter IPS */
+		RTW_INFO("%s: issue H2C to FW when entering IPS\n", __func__);
+
+		parm[0] = 0x1;/* suggest by Isaac.Hsu*/
+#ifdef CONFIG_PNO_SUPPORT
+		if (pwrpriv->pno_inited) {
+			parm[1] = pwrpriv->pnlo_info->fast_scan_iterations;
+			parm[2] = pwrpriv->pnlo_info->slow_scan_period;
+		}
+#endif
+
+		rtw_hal_fill_h2c_cmd(padapter, /* H2C_FWLPS_IN_IPS_, */
+				     H2C_INACTIVE_PS_,
+				     H2C_INACTIVE_PS_LEN, parm);
+		/* poll 0x1cc to make sure H2C command already finished by FW; MAC_0x1cc=0 means H2C done by FW. */
+		do {
+			val8 = rtw_read8(padapter, REG_HMETFR);
+			cnt++;
+			RTW_INFO("%s  polling REG_HMETFR=0x%x, cnt=%d\n",
+				 __func__, val8, cnt);
+			rtw_mdelay_os(10);
+		} while (cnt < 100 && (val8 != 0));
+
+#ifdef CONFIG_LPS_LCLK
+		/* H2C done, enter 32k */
+		if (val8 == 0) {
+			/* ser rpwm to enter 32k */
+			rtw_hal_get_hwreg(padapter, HW_VAR_RPWM_TOG, &val8);
+			RTW_INFO("%s: read rpwm=%02x\n", __FUNCTION__, val8);
+			val8 += 0x80;
+			val8 |= BIT(0);
+			rtw_hal_set_hwreg(padapter, HW_VAR_SET_RPWM, (u8 *)(&val8));
+			RTW_INFO("%s: write rpwm=%02x\n", __FUNCTION__, val8);
+			adapter_to_pwrctl(padapter)->tog = (val8 + 0x80) & 0x80;
+			cnt = val8 = 0;
+			if (parm[1] == 0 || parm[2] == 0) {
+				do {
+					val8 = rtw_read8(padapter, REG_CR);
+					cnt++;
+					RTW_INFO("%s  polling 0x100=0x%x, cnt=%d\n",
+						 __func__, val8, cnt);
+					RTW_INFO("%s 0x08:%02x, 0x03:%02x\n",
+						 __func__,
+						 rtw_read8(padapter, 0x08),
+						 rtw_read8(padapter, 0x03));
+					rtw_mdelay_os(10);
+				} while (cnt < 20 && (val8 != 0xEA));
+			}
+		}
+#endif
+	} else {
+		/* Leave IPS */
+		RTW_INFO("%s: Leaving IPS in FWLPS state\n", __func__);
+
+#ifdef CONFIG_LPS_LCLK
+		/* for polling cpwm */
+		cpwm_orig = 0;
+		rtw_hal_get_hwreg(padapter, HW_VAR_CPWM, &cpwm_orig);
+
+		/* ser rpwm */
+		rtw_hal_get_hwreg(padapter, HW_VAR_RPWM_TOG, &val8);
+		val8 += 0x80;
+		val8 |= BIT(6);
+		rtw_hal_set_hwreg(padapter, HW_VAR_SET_RPWM, (u8 *)(&val8));
+		RTW_INFO("%s: write rpwm=%02x\n", __FUNCTION__, val8);
+		adapter_to_pwrctl(padapter)->tog = (val8 + 0x80) & 0x80;
+
+		/* do polling cpwm */
+		start_time = rtw_get_current_time();
+		do {
+
+			rtw_mdelay_os(1);
+
+			rtw_hal_get_hwreg(padapter, HW_VAR_CPWM, &cpwm_now);
+			if ((cpwm_orig ^ cpwm_now) & 0x80)
+				break;
+
+			if (rtw_get_passing_time_ms(start_time) > 100) {
+				RTW_INFO("%s: polling cpwm timeout when leaving IPS in FWLPS state\n", __FUNCTION__);
+				break;
+			}
+		} while (1);
+
+#endif
+		parm[0] = 0x0;
+		parm[1] = 0x0;
+		parm[2] = 0x0;
+		rtw_hal_fill_h2c_cmd(padapter, H2C_INACTIVE_PS_,
+				     H2C_INACTIVE_PS_LEN, parm);
+#ifdef CONFIG_BT_COEXIST
+		rtw_btcoex_IpsNotify(padapter, IPS_NONE);
+#endif
+	}
+}
+#endif /* CONFIG_PNO_SUPPORT */
+
+void rtw_set_ps_mode(PADAPTER padapter, u8 ps_mode, u8 smart_ps, u8 bcn_ant_mode, const char *msg)
+{
+	struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter);
+#if defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN) || defined(CONFIG_P2P_WOWLAN)
+	struct dvobj_priv *psdpriv = padapter->dvobj;
+	struct debug_priv *pdbgpriv = &psdpriv->drv_dbg;
+#endif
+#ifdef CONFIG_WMMPS_STA	
+	struct registry_priv *pregistrypriv = &padapter->registrypriv;
+#endif
+#ifdef CONFIG_P2P
+	struct wifidirect_info	*pwdinfo = &(padapter->wdinfo);
+#endif /* CONFIG_P2P */
+#ifdef CONFIG_TDLS
+	struct sta_priv *pstapriv = &padapter->stapriv;
+	_irqL irqL;
+	int i, j;
+	_list	*plist, *phead;
+	struct sta_info *ptdls_sta;
+#endif /* CONFIG_TDLS */
+#ifdef CONFIG_LPS_PG
+	u8 lps_pg_hdl_id = 0;
+#endif
+
+
+
+	if (ps_mode > PM_Card_Disable) {
+		return;
+	}
+
+	if (pwrpriv->pwr_mode == ps_mode) {
+		if (PS_MODE_ACTIVE == ps_mode)
+			return;
+
+#ifndef CONFIG_BT_COEXIST
+#ifdef CONFIG_WMMPS_STA	
+		if (!rtw_is_wmmps_mode(padapter))
+#endif /* CONFIG_WMMPS_STA */
+			if ((pwrpriv->smart_ps == smart_ps) &&
+			    (pwrpriv->bcn_ant_mode == bcn_ant_mode))
+				return;
+#endif /* !CONFIG_BT_COEXIST */
+	}
+
+#ifdef CONFIG_FW_MULTI_PORT_SUPPORT
+	if (PS_MODE_ACTIVE != ps_mode) {
+		rtw_set_ps_rsvd_page(padapter);
+		rtw_set_default_port_id(padapter);
+	}
+#endif
+
+#ifdef CONFIG_LPS_PG
+	if ((PS_MODE_ACTIVE != ps_mode) && (pwrpriv->blpspg_info_up)) {
+		/*rtw_hal_set_lps_pg_info(padapter);*/
+		lps_pg_hdl_id = LPS_PG_INFO_CFG;
+		rtw_hal_set_hwreg(padapter, HW_VAR_LPS_PG_HANDLE, (u8 *)(&lps_pg_hdl_id));
+	}
+#endif
+
+#ifdef CONFIG_LPS_LCLK
+	_enter_pwrlock(&pwrpriv->lock);
+#endif
+
+	/* if(pwrpriv->pwr_mode == PS_MODE_ACTIVE) */
+	if (ps_mode == PS_MODE_ACTIVE) {
+		if (1
+#ifdef CONFIG_BT_COEXIST
+		    && (((rtw_btcoex_IsBtControlLps(padapter) == _FALSE)
+#ifdef CONFIG_P2P_PS
+			 && (pwdinfo->opp_ps == 0)
+#endif /* CONFIG_P2P_PS */
+			)
+			|| ((rtw_btcoex_IsBtControlLps(padapter) == _TRUE)
+			    && (rtw_btcoex_IsLpsOn(padapter) == _FALSE))
+		       )
+#else /* !CONFIG_BT_COEXIST */
+#ifdef CONFIG_P2P_PS
+		    && (pwdinfo->opp_ps == 0)
+#endif /* CONFIG_P2P_PS */
+#endif /* !CONFIG_BT_COEXIST */
+		   ) {
+			RTW_INFO(FUNC_ADPT_FMT" Leave 802.11 power save - %s\n",
+				 FUNC_ADPT_ARG(padapter), msg);
+
+			if (pwrpriv->lps_leave_cnts < UINT_MAX)
+				pwrpriv->lps_leave_cnts++;
+			else
+				pwrpriv->lps_leave_cnts = 0;
+#ifdef CONFIG_TDLS
+			for (i = 0; i < NUM_STA; i++) {
+				phead = &(pstapriv->sta_hash[i]);
+				plist = get_next(phead);
+
+				while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) {
+					ptdls_sta = LIST_CONTAINOR(plist, struct sta_info, hash_list);
+
+					if (ptdls_sta->tdls_sta_state & TDLS_LINKED_STATE)
+						issue_nulldata_to_TDLS_peer_STA(padapter, ptdls_sta->cmn.mac_addr, 0, 0, 0);
+					plist = get_next(plist);
+				}
+			}
+#endif /* CONFIG_TDLS */
+
+			pwrpriv->pwr_mode = ps_mode;
+			rtw_set_rpwm(padapter, PS_STATE_S4);
+
+#if defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN) || defined(CONFIG_P2P_WOWLAN)
+			if (pwrpriv->wowlan_mode == _TRUE ||
+			    pwrpriv->wowlan_ap_mode == _TRUE ||
+			    pwrpriv->wowlan_p2p_mode == _TRUE) {
+				systime start_time;
+				u32 delay_ms;
+				u8 val8;
+				delay_ms = 20;
+				start_time = rtw_get_current_time();
+				do {
+					rtw_hal_get_hwreg(padapter, HW_VAR_SYS_CLKR, &val8);
+					if (!(val8 & BIT(4))) { /* 0x08 bit4 =1 --> in 32k, bit4 = 0 --> leave 32k */
+						pwrpriv->cpwm = PS_STATE_S4;
+						break;
+					}
+					if (rtw_get_passing_time_ms(start_time) > delay_ms) {
+						RTW_INFO("%s: Wait for FW 32K leave more than %u ms!!!\n",
+							__FUNCTION__, delay_ms);
+						pdbgpriv->dbg_wow_leave_ps_fail_cnt++;
+						break;
+					}
+					rtw_usleep_os(100);
+				} while (1);
+			}
+#endif
+#ifdef CONFIG_LPS_PG
+			if (pwrpriv->lps_level == LPS_PG) {
+				lps_pg_hdl_id = LPS_PG_REDLEMEM;
+				rtw_hal_set_hwreg(padapter, HW_VAR_LPS_PG_HANDLE, (u8 *)(&lps_pg_hdl_id));
+			}
+#endif
+			rtw_hal_set_hwreg(padapter, HW_VAR_H2C_FW_PWRMODE, (u8 *)(&ps_mode));
+			rtw_hal_set_hwreg(padapter, HW_VAR_LPS_STATE_CHK, (u8 *)(&ps_mode));
+
+#ifdef CONFIG_LPS_PG
+			if (pwrpriv->lps_level == LPS_PG) {
+				lps_pg_hdl_id = LPS_PG_PHYDM_EN;
+				rtw_hal_set_hwreg(padapter, HW_VAR_LPS_PG_HANDLE, (u8 *)(&lps_pg_hdl_id));
+			}
+#endif
+
+#ifdef CONFIG_LPS_POFF
+			rtw_hal_set_hwreg(padapter, HW_VAR_LPS_POFF_SET_MODE,
+					  (u8 *)(&ps_mode));
+#endif /*CONFIG_LPS_POFF*/
+
+			pwrpriv->bFwCurrentInPSMode = _FALSE;
+
+#ifdef CONFIG_BT_COEXIST
+			rtw_btcoex_LpsNotify(padapter, ps_mode);
+#endif /* CONFIG_BT_COEXIST */
+		}
+	} else {
+		if ((PS_RDY_CHECK(padapter) && check_fwstate(&padapter->mlmepriv, WIFI_ASOC_STATE))
+#ifdef CONFIG_BT_COEXIST
+		    || ((rtw_btcoex_IsBtControlLps(padapter) == _TRUE)
+			&& (rtw_btcoex_IsLpsOn(padapter) == _TRUE))
+#endif
+#ifdef CONFIG_P2P_WOWLAN
+		    || (_TRUE == pwrpriv->wowlan_p2p_mode)
+#endif /* CONFIG_P2P_WOWLAN */
+		   ) {
+			u8 pslv;
+
+			RTW_INFO(FUNC_ADPT_FMT" Enter 802.11 power save - %s\n",
+				 FUNC_ADPT_ARG(padapter), msg);
+
+			if (pwrpriv->lps_enter_cnts < UINT_MAX)
+				pwrpriv->lps_enter_cnts++;
+			else
+				pwrpriv->lps_enter_cnts = 0;
+#ifdef CONFIG_TDLS
+			for (i = 0; i < NUM_STA; i++) {
+				phead = &(pstapriv->sta_hash[i]);
+				plist = get_next(phead);
+
+				while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) {
+					ptdls_sta = LIST_CONTAINOR(plist, struct sta_info, hash_list);
+
+					if (ptdls_sta->tdls_sta_state & TDLS_LINKED_STATE)
+						issue_nulldata_to_TDLS_peer_STA(padapter, ptdls_sta->cmn.mac_addr, 1, 0, 0);
+					plist = get_next(plist);
+				}
+			}
+#endif /* CONFIG_TDLS */
+
+#ifdef CONFIG_BT_COEXIST
+			rtw_btcoex_LpsNotify(padapter, ps_mode);
+#endif /* CONFIG_BT_COEXIST */
+
+#ifdef CONFIG_LPS_POFF
+			rtw_hal_set_hwreg(padapter, HW_VAR_LPS_POFF_SET_MODE,
+					  (u8 *)(&ps_mode));
+#endif /*CONFIG_LPS_POFF*/
+
+			pwrpriv->bFwCurrentInPSMode = _TRUE;
+			pwrpriv->pwr_mode = ps_mode;
+			pwrpriv->smart_ps = smart_ps;
+			pwrpriv->bcn_ant_mode = bcn_ant_mode;
+#ifdef CONFIG_LPS_PG
+			if (pwrpriv->lps_level == LPS_PG) {
+				lps_pg_hdl_id = LPS_PG_PHYDM_DIS;
+				rtw_hal_set_hwreg(padapter, HW_VAR_LPS_PG_HANDLE, (u8 *)(&lps_pg_hdl_id));
+			}
+#endif
+
+#ifdef CONFIG_WMMPS_STA	
+			pwrpriv->wmm_smart_ps = pregistrypriv->wmm_smart_ps;
+#endif /* CONFIG_WMMPS_STA */
+			
+			rtw_hal_set_hwreg(padapter, HW_VAR_H2C_FW_PWRMODE, (u8 *)(&ps_mode));
+
+#ifdef CONFIG_P2P_PS
+			/* Set CTWindow after LPS */
+			if (pwdinfo->opp_ps == 1)
+				p2p_ps_wk_cmd(padapter, P2P_PS_ENABLE, 0);
+#endif /* CONFIG_P2P_PS */
+
+			pslv = PS_STATE_S2;
+#ifdef CONFIG_LPS_LCLK
+			if (pwrpriv->alives == 0)
+				pslv = PS_STATE_S0;
+#endif /* CONFIG_LPS_LCLK */
+
+#ifdef CONFIG_BT_COEXIST
+			if ((rtw_btcoex_IsBtDisabled(padapter) == _FALSE)
+			    && (rtw_btcoex_IsBtControlLps(padapter) == _TRUE)) {
+				u8 val8;
+
+				val8 = rtw_btcoex_LpsVal(padapter);
+				if (val8 & BIT(4))
+					pslv = PS_STATE_S2;
+
+			}
+#endif /* CONFIG_BT_COEXIST */
+
+			rtw_set_rpwm(padapter, pslv);
+		}
+	}
+
+#ifdef CONFIG_LPS_LCLK
+	_exit_pwrlock(&pwrpriv->lock);
+#endif
+
+}
+
+/*
+ * Return:
+ *	0:	Leave OK
+ *	-1:	Timeout
+ *	-2:	Other error
+ */
+s32 LPS_RF_ON_check(PADAPTER padapter, u32 delay_ms)
+{
+	systime start_time;
+	u8 bAwake = _FALSE;
+	s32 err = 0;
+
+
+	start_time = rtw_get_current_time();
+	while (1) {
+		rtw_hal_get_hwreg(padapter, HW_VAR_FWLPS_RF_ON, &bAwake);
+		if (_TRUE == bAwake)
+			break;
+
+		if (rtw_is_surprise_removed(padapter)) {
+			err = -2;
+			RTW_INFO("%s: device surprise removed!!\n", __FUNCTION__);
+			break;
+		}
+
+		if (rtw_get_passing_time_ms(start_time) > delay_ms) {
+			err = -1;
+			RTW_INFO("%s: Wait for FW LPS leave more than %u ms!!!\n", __FUNCTION__, delay_ms);
+			break;
+		}
+		rtw_usleep_os(100);
+	}
+
+	return err;
+}
+
+/*
+ *	Description:
+ *		Enter the leisure power save mode.
+ *   */
+void LPS_Enter(PADAPTER padapter, const char *msg)
+{
+	struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
+	struct pwrctrl_priv	*pwrpriv = dvobj_to_pwrctl(dvobj);
+	int i;
+	char buf[32] = {0};
+#ifdef DBG_LA_MODE
+	struct registry_priv *registry_par = &(padapter->registrypriv);
+#endif
+
+	/*	RTW_INFO("+LeisurePSEnter\n"); */
+	if (GET_HAL_DATA(padapter)->bFWReady == _FALSE)
+		return;
+
+#ifdef CONFIG_BT_COEXIST
+	if (rtw_btcoex_IsBtControlLps(padapter) == _TRUE)
+		return;
+#endif
+
+#ifdef DBG_LA_MODE
+	if(registry_par->la_mode_en == 1) {
+		RTW_INFO("%s LA debug mode lps_leave \n", __func__);
+		return;
+	}
+#endif
+	/* Skip lps enter request if number of assocated adapters is not 1 */
+	if (rtw_mi_get_assoc_if_num(padapter) != 1)
+		return;
+
+#ifndef CONFIG_FW_MULTI_PORT_SUPPORT
+	/* Skip lps enter request for adapter not port0 */
+	if (get_hw_port(padapter) != HW_PORT0)
+		return;
+#endif
+
+	for (i = 0; i < dvobj->iface_nums; i++) {
+		if (PS_RDY_CHECK(dvobj->padapters[i]) == _FALSE)
+			return;
+	}
+
+#ifdef CONFIG_CLIENT_PORT_CFG
+	if ((rtw_hal_get_port(padapter) == CLT_PORT_INVALID) ||
+		get_clt_num(padapter) > MAX_CLIENT_PORT_NUM){
+		RTW_ERR(ADPT_FMT" cannot get client port or clt num(%d) over than 4\n", ADPT_ARG(padapter), get_clt_num(padapter));
+		return;
+	}
+#endif
+
+#ifdef CONFIG_P2P_PS
+	if (padapter->wdinfo.p2p_ps_mode == P2P_PS_NOA) {
+		return;/* supporting p2p client ps NOA via H2C_8723B_P2P_PS_OFFLOAD */
+	}
+#endif /* CONFIG_P2P_PS */
+
+	if (pwrpriv->bLeisurePs) {
+		/* Idle for a while if we connect to AP a while ago. */
+		if (pwrpriv->LpsIdleCount >= 2) { /* 4 Sec */
+			if (pwrpriv->pwr_mode == PS_MODE_ACTIVE) {
+
+#ifdef CONFIG_WMMPS_STA
+				if (rtw_is_wmmps_mode(padapter))
+					msg = "WMMPS_IDLE";
+#endif /* CONFIG_WMMPS_STA */
+				
+				sprintf(buf, "WIFI-%s", msg);
+				pwrpriv->bpower_saving = _TRUE;
+				
+#ifdef CONFIG_RTW_CFGVEDNOR_LLSTATS
+				pwrpriv->pwr_saving_start_time = rtw_get_current_time();
+#endif /* CONFIG_RTW_CFGVEDNOR_LLSTATS */
+
+				rtw_set_ps_mode(padapter, pwrpriv->power_mgnt, padapter->registrypriv.smart_ps, 0, buf);
+			}
+		} else
+			pwrpriv->LpsIdleCount++;
+	}
+
+	/*	RTW_INFO("-LeisurePSEnter\n"); */
+
+}
+
+/*
+ *	Description:
+ *		Leave the leisure power save mode.
+ *   */
+void LPS_Leave(PADAPTER padapter, const char *msg)
+{
+#define LPS_LEAVE_TIMEOUT_MS 100
+
+	struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
+	struct pwrctrl_priv	*pwrpriv = dvobj_to_pwrctl(dvobj);
+	char buf[32] = {0};
+#ifdef DBG_CHECK_FW_PS_STATE
+	struct debug_priv *pdbgpriv = &dvobj->drv_dbg;
+#endif
+
+
+	/*	RTW_INFO("+LeisurePSLeave\n"); */
+
+#ifdef CONFIG_BT_COEXIST
+	if (rtw_btcoex_IsBtControlLps(padapter) == _TRUE)
+		return;
+#endif
+
+	if (pwrpriv->bLeisurePs) {
+		if (pwrpriv->pwr_mode != PS_MODE_ACTIVE) {
+
+#ifdef CONFIG_WMMPS_STA
+			if (rtw_is_wmmps_mode(padapter))
+				msg = "WMMPS_BUSY";
+#endif /* CONFIG_WMMPS_STA */
+			
+			sprintf(buf, "WIFI-%s", msg);
+			rtw_set_ps_mode(padapter, PS_MODE_ACTIVE, 0, 0, buf);
+
+#ifdef CONFIG_RTW_CFGVEDNOR_LLSTATS	
+			pwrpriv->pwr_saving_time += rtw_get_passing_time_ms(pwrpriv->pwr_saving_start_time);
+#endif /* CONFIG_RTW_CFGVEDNOR_LLSTATS */
+
+			if (pwrpriv->pwr_mode == PS_MODE_ACTIVE)
+				LPS_RF_ON_check(padapter, LPS_LEAVE_TIMEOUT_MS);
+		}
+	}
+
+	pwrpriv->bpower_saving = _FALSE;
+#ifdef DBG_CHECK_FW_PS_STATE
+	if (rtw_fw_ps_state(padapter) == _FAIL) {
+		RTW_INFO("leave lps, fw in 32k\n");
+		pdbgpriv->dbg_leave_lps_fail_cnt++;
+	}
+#endif /* DBG_CHECK_FW_PS_STATE
+ * 	RTW_INFO("-LeisurePSLeave\n"); */
+
+}
+
+void rtw_wow_lps_level_decide(_adapter *adapter, u8 wow_en)
+{
+#if defined(CONFIG_USB_HCI) && defined(CONFIG_LPS_LCLK)
+	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
+	struct pwrctrl_priv *pwrpriv = dvobj_to_pwrctl(dvobj);
+
+	if (wow_en) {
+		pwrpriv->lps_level_bk = pwrpriv->lps_level;
+		pwrpriv->lps_level = LPS_LCLK;
+	} else
+		pwrpriv->lps_level = pwrpriv->lps_level_bk;
+#endif
+}
+#endif
+
+void LeaveAllPowerSaveModeDirect(PADAPTER Adapter)
+{
+	PADAPTER pri_padapter = GET_PRIMARY_ADAPTER(Adapter);
+	struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(Adapter);
+#ifdef CONFIG_LPS_LCLK
+#ifndef CONFIG_DETECT_CPWM_BY_POLLING
+	u8 cpwm_orig;
+#endif /* CONFIG_DETECT_CPWM_BY_POLLING */
+	u8 rpwm;
+#endif
+
+	RTW_INFO("%s.....\n", __FUNCTION__);
+
+	if (rtw_is_surprise_removed(Adapter)) {
+		RTW_INFO(FUNC_ADPT_FMT ": bSurpriseRemoved=_TRUE Skip!\n", FUNC_ADPT_ARG(Adapter));
+		return;
+	}
+
+	if (rtw_mi_check_status(Adapter, MI_LINKED)) { /*connect*/
+
+		if (pwrpriv->pwr_mode == PS_MODE_ACTIVE) {
+			RTW_INFO("%s: Driver Already Leave LPS\n", __FUNCTION__);
+			return;
+		}
+
+#ifdef CONFIG_LPS_LCLK
+		_enter_pwrlock(&pwrpriv->lock);
+
+#ifndef CONFIG_DETECT_CPWM_BY_POLLING
+		cpwm_orig = 0;
+		rtw_hal_get_hwreg(Adapter, HW_VAR_CPWM, &cpwm_orig);
+#endif /* CONFIG_DETECT_CPWM_BY_POLLING */
+		rpwm = rtw_set_rpwm(Adapter, PS_STATE_S4);
+
+#ifndef CONFIG_DETECT_CPWM_BY_POLLING
+		if (rpwm != 0xFF && rpwm & PS_ACK)
+			rtw_cpwm_polling(Adapter, rpwm, cpwm_orig);
+#endif /* CONFIG_DETECT_CPWM_BY_POLLING */
+
+		_exit_pwrlock(&pwrpriv->lock);
+#endif/*CONFIG_LPS_LCLK*/
+
+#ifdef CONFIG_P2P_PS
+		p2p_ps_wk_cmd(pri_padapter, P2P_PS_DISABLE, 0);
+#endif /* CONFIG_P2P_PS */
+
+#ifdef CONFIG_LPS
+		rtw_lps_ctrl_wk_cmd(pri_padapter, LPS_CTRL_LEAVE, 0);
+#endif
+	} else {
+		if (pwrpriv->rf_pwrstate == rf_off) {
+#ifdef CONFIG_AUTOSUSPEND
+			if (Adapter->registrypriv.usbss_enable) {
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 35))
+				usb_disable_autosuspend(adapter_to_dvobj(Adapter)->pusbdev);
+#elif (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 22) && LINUX_VERSION_CODE <= KERNEL_VERSION(2, 6, 34))
+				adapter_to_dvobj(Adapter)->pusbdev->autosuspend_disabled = Adapter->bDisableAutosuspend;/* autosuspend disabled by the user */
+#endif
+			} else
+#endif
+			{
+#if defined(CONFIG_FWLPS_IN_IPS) || defined(CONFIG_SWLPS_IN_IPS) || defined(CONFIG_RTL8188E)
+#ifdef CONFIG_IPS
+				if (_FALSE == ips_leave(pri_padapter))
+					RTW_INFO("======> ips_leave fail.............\n");
+#endif
+#endif /* CONFIG_SWLPS_IN_IPS || (CONFIG_PLATFORM_SPRD && CONFIG_RTL8188E) */
+			}
+		}
+	}
+
+}
+
+/*
+ * Description: Leave all power save mode: LPS, FwLPS, IPS if needed.
+ * Move code to function by tynli. 2010.03.26.
+ *   */
+void LeaveAllPowerSaveMode(IN PADAPTER Adapter)
+{
+	struct dvobj_priv *dvobj = adapter_to_dvobj(Adapter);
+	u8	enqueue = 0;
+	int i;
+
+	#ifndef CONFIG_NEW_NETDEV_HDL
+	if (_FALSE == Adapter->bup) {
+		RTW_INFO(FUNC_ADPT_FMT ": bup=%d Skip!\n",
+			 FUNC_ADPT_ARG(Adapter), Adapter->bup);
+		return;
+	}
+	#endif
+
+/*	RTW_INFO(FUNC_ADPT_FMT "\n", FUNC_ADPT_ARG(Adapter));*/
+
+	if (rtw_is_surprise_removed(Adapter)) {
+		RTW_INFO(FUNC_ADPT_FMT ": bSurpriseRemoved=_TRUE Skip!\n", FUNC_ADPT_ARG(Adapter));
+		return;
+	}
+
+	if (rtw_mi_get_assoc_if_num(Adapter)) {
+		/* connect */
+#ifdef CONFIG_LPS_LCLK
+		enqueue = 1;
+#endif
+
+#ifdef CONFIG_P2P_PS
+		for (i = 0; i < dvobj->iface_nums; i++) {
+			_adapter *iface = dvobj->padapters[i];
+			struct wifidirect_info *pwdinfo = &(iface->wdinfo);
+
+			if (pwdinfo->p2p_ps_mode > P2P_PS_NONE)
+				p2p_ps_wk_cmd(iface, P2P_PS_DISABLE, enqueue);
+		}
+#endif /* CONFIG_P2P_PS */
+
+#ifdef CONFIG_LPS
+		rtw_lps_ctrl_wk_cmd(Adapter, LPS_CTRL_LEAVE, enqueue);
+#endif
+
+#ifdef CONFIG_LPS_LCLK
+		LPS_Leave_check(Adapter);
+#endif
+	} else {
+		if (adapter_to_pwrctl(Adapter)->rf_pwrstate == rf_off) {
+#ifdef CONFIG_AUTOSUSPEND
+			if (Adapter->registrypriv.usbss_enable) {
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 35))
+				usb_disable_autosuspend(adapter_to_dvobj(Adapter)->pusbdev);
+#elif (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 22) && LINUX_VERSION_CODE <= KERNEL_VERSION(2, 6, 34))
+				adapter_to_dvobj(Adapter)->pusbdev->autosuspend_disabled = Adapter->bDisableAutosuspend;/* autosuspend disabled by the user */
+#endif
+			} else
+#endif
+			{
+#if defined(CONFIG_FWLPS_IN_IPS) || defined(CONFIG_SWLPS_IN_IPS) || (defined(CONFIG_PLATFORM_SPRD) && defined(CONFIG_RTL8188E))
+#ifdef CONFIG_IPS
+				if (_FALSE == ips_leave(Adapter))
+					RTW_INFO("======> ips_leave fail.............\n");
+#endif
+#endif /* CONFIG_SWLPS_IN_IPS || (CONFIG_PLATFORM_SPRD && CONFIG_RTL8188E) */
+			}
+		}
+	}
+
+}
+
+#ifdef CONFIG_LPS_LCLK
+void LPS_Leave_check(
+	PADAPTER padapter)
+{
+	struct pwrctrl_priv *pwrpriv;
+	systime	start_time;
+	u8	bReady;
+
+
+	pwrpriv = adapter_to_pwrctl(padapter);
+
+	bReady = _FALSE;
+	start_time = rtw_get_current_time();
+
+	rtw_yield_os();
+
+	while (1) {
+		_enter_pwrlock(&pwrpriv->lock);
+
+		if (rtw_is_surprise_removed(padapter)
+		    || (!rtw_is_hw_init_completed(padapter))
+#ifdef CONFIG_USB_HCI
+		    || rtw_is_drv_stopped(padapter)
+#endif
+		    || (pwrpriv->pwr_mode == PS_MODE_ACTIVE)
+		   )
+			bReady = _TRUE;
+
+		_exit_pwrlock(&pwrpriv->lock);
+
+		if (_TRUE == bReady)
+			break;
+
+		if (rtw_get_passing_time_ms(start_time) > 100) {
+			RTW_ERR("Wait for cpwm event  than 100 ms!!!\n");
+			break;
+		}
+		rtw_msleep_os(1);
+	}
+
+}
+
+/*
+ * Caller:ISR handler...
+ *
+ * This will be called when CPWM interrupt is up.
+ *
+ * using to update cpwn of drv; and drv willl make a decision to up or down pwr level
+ */
+void cpwm_int_hdl(
+	PADAPTER padapter,
+	struct reportpwrstate_parm *preportpwrstate)
+{
+	struct pwrctrl_priv *pwrpriv;
+
+	if (!padapter)
+		goto exit;
+
+	if (RTW_CANNOT_RUN(padapter))
+		goto exit;
+
+	pwrpriv = adapter_to_pwrctl(padapter);
+#if 0
+	if (pwrpriv->cpwm_tog == (preportpwrstate->state & PS_TOGGLE)) {
+		goto exit;
+	}
+#endif
+
+	_enter_pwrlock(&pwrpriv->lock);
+
+#ifdef CONFIG_LPS_RPWM_TIMER
+	if (pwrpriv->rpwm < PS_STATE_S2) {
+		RTW_INFO("%s: Redundant CPWM Int. RPWM=0x%02X CPWM=0x%02x\n", __func__, pwrpriv->rpwm, pwrpriv->cpwm);
+		_exit_pwrlock(&pwrpriv->lock);
+		goto exit;
+	}
+#endif /* CONFIG_LPS_RPWM_TIMER */
+
+	pwrpriv->cpwm = PS_STATE(preportpwrstate->state);
+	pwrpriv->cpwm_tog = preportpwrstate->state & PS_TOGGLE;
+
+	if (pwrpriv->cpwm >= PS_STATE_S2) {
+		if (pwrpriv->alives & CMD_ALIVE)
+			_rtw_up_sema(&padapter->cmdpriv.cmd_queue_sema);
+
+		if (pwrpriv->alives & XMIT_ALIVE)
+			_rtw_up_sema(&padapter->xmitpriv.xmit_sema);
+	}
+
+	_exit_pwrlock(&pwrpriv->lock);
+
+exit:
+	return;
+}
+
+static void cpwm_event_callback(struct work_struct *work)
+{
+	struct pwrctrl_priv *pwrpriv = container_of(work, struct pwrctrl_priv, cpwm_event);
+	struct dvobj_priv *dvobj = pwrctl_to_dvobj(pwrpriv);
+	_adapter *adapter = dvobj_get_primary_adapter(dvobj);
+	struct reportpwrstate_parm report;
+
+	/* RTW_INFO("%s\n",__FUNCTION__); */
+
+	report.state = PS_STATE_S2;
+	cpwm_int_hdl(adapter, &report);
+}
+
+static void dma_event_callback(struct work_struct *work)
+{
+	struct pwrctrl_priv *pwrpriv = container_of(work, struct pwrctrl_priv, dma_event);
+	struct dvobj_priv *dvobj = pwrctl_to_dvobj(pwrpriv);
+	_adapter *adapter = dvobj_get_primary_adapter(dvobj);
+
+	rtw_unregister_tx_alive(adapter);
+}
+
+#ifdef CONFIG_LPS_RPWM_TIMER
+
+#define DBG_CPWM_CHK_FAIL
+#if defined(DBG_CPWM_CHK_FAIL) && (defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C))
+#define CPU_EXCEPTION_CODE 0xFAFAFAFA
+static void rtw_cpwm_chk_fail_debug(_adapter *padapter)
+{
+	u32 cpu_state;
+
+	cpu_state = rtw_read32(padapter, 0x10FC);
+
+	RTW_INFO("[PS-DBG] Reg_10FC =0x%08x\n", cpu_state);
+	RTW_INFO("[PS-DBG] Reg_10F8 =0x%08x\n", rtw_read32(padapter, 0x10F8));
+	RTW_INFO("[PS-DBG] Reg_11F8 =0x%08x\n", rtw_read32(padapter, 0x11F8));
+	RTW_INFO("[PS-DBG] Reg_4A4 =0x%08x\n", rtw_read32(padapter, 0x4A4));
+	RTW_INFO("[PS-DBG] Reg_4A8 =0x%08x\n", rtw_read32(padapter, 0x4A8));
+
+	if (cpu_state == CPU_EXCEPTION_CODE) {
+		RTW_INFO("[PS-DBG] Reg_48C =0x%08x\n", rtw_read32(padapter, 0x48C));
+		RTW_INFO("[PS-DBG] Reg_490 =0x%08x\n", rtw_read32(padapter, 0x490));
+		RTW_INFO("[PS-DBG] Reg_494 =0x%08x\n", rtw_read32(padapter, 0x494));
+		RTW_INFO("[PS-DBG] Reg_498 =0x%08x\n", rtw_read32(padapter, 0x498));
+		RTW_INFO("[PS-DBG] Reg_49C =0x%08x\n", rtw_read32(padapter, 0x49C));
+		RTW_INFO("[PS-DBG] Reg_4A0 =0x%08x\n", rtw_read32(padapter, 0x4A0));
+		RTW_INFO("[PS-DBG] Reg_1BC =0x%08x\n", rtw_read32(padapter, 0x1BC));
+
+		RTW_INFO("[PS-DBG] Reg_008 =0x%08x\n", rtw_read32(padapter, 0x08));
+		RTW_INFO("[PS-DBG] Reg_2F0 =0x%08x\n", rtw_read32(padapter, 0x2F0));
+		RTW_INFO("[PS-DBG] Reg_2F4 =0x%08x\n", rtw_read32(padapter, 0x2F4));
+		RTW_INFO("[PS-DBG] Reg_2F8 =0x%08x\n", rtw_read32(padapter, 0x2F8));
+		RTW_INFO("[PS-DBG] Reg_2FC =0x%08x\n", rtw_read32(padapter, 0x2FC));
+
+		rtw_dump_fifo(RTW_DBGDUMP, padapter, 5, 0, 3072);
+	}
+}
+#endif
+static void rpwmtimeout_workitem_callback(struct work_struct *work)
+{
+	PADAPTER padapter;
+	struct dvobj_priv *dvobj;
+	struct pwrctrl_priv *pwrpriv;
+
+
+	pwrpriv = container_of(work, struct pwrctrl_priv, rpwmtimeoutwi);
+	dvobj = pwrctl_to_dvobj(pwrpriv);
+	padapter = dvobj_get_primary_adapter(dvobj);
+
+	if (!padapter)
+		return;
+
+	if (RTW_CANNOT_RUN(padapter))
+		return;
+
+	_enter_pwrlock(&pwrpriv->lock);
+	if ((pwrpriv->rpwm == pwrpriv->cpwm) || (pwrpriv->cpwm >= PS_STATE_S2)) {
+		RTW_INFO("%s: rpwm=0x%02X cpwm=0x%02X CPWM done!\n", __func__, pwrpriv->rpwm, pwrpriv->cpwm);
+		goto exit;
+	}
+
+	if (pwrpriv->rpwm_retry++ < LPS_RPWM_RETRY_CNT) {
+		u8 rpwm = (pwrpriv->rpwm | pwrpriv->tog | PS_ACK);
+
+		rtw_hal_set_hwreg(padapter, HW_VAR_SET_RPWM, (u8 *)(&rpwm));
+
+		pwrpriv->tog += 0x80;
+		_set_timer(&pwrpriv->pwr_rpwm_timer, LPS_CPWM_TIMEOUT_MS);
+		goto exit;
+	}
+
+	pwrpriv->rpwm_retry = 0;
+	_exit_pwrlock(&pwrpriv->lock);
+
+#if defined(DBG_CPWM_CHK_FAIL) && (defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C))
+	RTW_INFO("+%s: rpwm=0x%02X cpwm=0x%02X\n", __func__, pwrpriv->rpwm, pwrpriv->cpwm);
+	rtw_cpwm_chk_fail_debug(padapter);
+#endif
+
+	if (rtw_read8(padapter, 0x100) != 0xEA) {
+#if 1
+		struct reportpwrstate_parm report;
+
+		report.state = PS_STATE_S2;
+		RTW_INFO("\n%s: FW already leave 32K!\n\n", __func__);
+		cpwm_int_hdl(padapter, &report);
+#else
+		RTW_INFO("\n%s: FW already leave 32K!\n\n", __func__);
+		cpwm_event_callback(&pwrpriv->cpwm_event);
+#endif
+		return;
+	}
+
+	_enter_pwrlock(&pwrpriv->lock);
+
+	if ((pwrpriv->rpwm == pwrpriv->cpwm) || (pwrpriv->cpwm >= PS_STATE_S2)) {
+		RTW_INFO("%s: cpwm=%d, nothing to do!\n", __func__, pwrpriv->cpwm);
+		goto exit;
+	}
+	pwrpriv->brpwmtimeout = _TRUE;
+	rtw_set_rpwm(padapter, pwrpriv->rpwm);
+	pwrpriv->brpwmtimeout = _FALSE;
+
+exit:
+	_exit_pwrlock(&pwrpriv->lock);
+}
+
+/*
+ * This function is a timer handler, can't do any IO in it.
+ */
+static void pwr_rpwm_timeout_handler(void *FunctionContext)
+{
+	PADAPTER padapter;
+	struct pwrctrl_priv *pwrpriv;
+
+
+	padapter = (PADAPTER)FunctionContext;
+	pwrpriv = adapter_to_pwrctl(padapter);
+	if (!padapter)
+		return;
+
+	if (RTW_CANNOT_RUN(padapter))
+		return;
+
+	RTW_INFO("+%s: rpwm=0x%02X cpwm=0x%02X\n", __func__, pwrpriv->rpwm, pwrpriv->cpwm);
+
+	if ((pwrpriv->rpwm == pwrpriv->cpwm) || (pwrpriv->cpwm >= PS_STATE_S2)) {
+		RTW_INFO("+%s: cpwm=%d, nothing to do!\n", __func__, pwrpriv->cpwm);
+		return;
+	}
+
+	_set_workitem(&pwrpriv->rpwmtimeoutwi);
+}
+#endif /* CONFIG_LPS_RPWM_TIMER */
+
+__inline static void register_task_alive(struct pwrctrl_priv *pwrctrl, u32 tag)
+{
+	pwrctrl->alives |= tag;
+}
+
+__inline static void unregister_task_alive(struct pwrctrl_priv *pwrctrl, u32 tag)
+{
+	pwrctrl->alives &= ~tag;
+}
+
+
+/*
+ * Description:
+ *	Check if the fw_pwrstate is okay for I/O.
+ *	If not (cpwm is less than S2), then the sub-routine
+ *	will raise the cpwm to be greater than or equal to S2.
+ *
+ *	Calling Context: Passive
+ *
+ *	Constraint:
+ *		1. this function will request pwrctrl->lock
+ *
+ * Return Value:
+ *	_SUCCESS	hardware is ready for I/O
+ *	_FAIL		can't I/O right now
+ */
+s32 rtw_register_task_alive(PADAPTER padapter, u32 task)
+{
+	s32 res;
+	struct pwrctrl_priv *pwrctrl;
+	u8 pslv;
+
+
+	res = _SUCCESS;
+	pwrctrl = adapter_to_pwrctl(padapter);
+	pslv = PS_STATE_S2;
+
+	_enter_pwrlock(&pwrctrl->lock);
+
+	register_task_alive(pwrctrl, task);
+
+	if (pwrctrl->bFwCurrentInPSMode == _TRUE) {
+
+		if (pwrctrl->cpwm < pslv) {
+			if (pwrctrl->cpwm < PS_STATE_S2)
+				res = _FAIL;
+			if (pwrctrl->rpwm < pslv)
+				rtw_set_rpwm(padapter, pslv);
+		}
+	}
+
+	_exit_pwrlock(&pwrctrl->lock);
+
+#ifdef CONFIG_DETECT_CPWM_BY_POLLING
+	if (_FAIL == res) {
+		if (pwrctrl->cpwm >= PS_STATE_S2)
+			res = _SUCCESS;
+	}
+#endif /* CONFIG_DETECT_CPWM_BY_POLLING */
+
+
+	return res;
+}
+
+/*
+ * Description:
+ *	If task is done, call this func. to power down firmware again.
+ *
+ *	Constraint:
+ *		1. this function will request pwrctrl->lock
+ *
+ * Return Value:
+ *	none
+ */
+void rtw_unregister_task_alive(PADAPTER padapter, u32 task)
+{
+	struct pwrctrl_priv *pwrctrl;
+	u8 pslv;
+
+
+	pwrctrl = adapter_to_pwrctl(padapter);
+	pslv = PS_STATE_S0;
+
+#ifdef CONFIG_BT_COEXIST
+	if ((rtw_btcoex_IsBtDisabled(padapter) == _FALSE)
+	    && (rtw_btcoex_IsBtControlLps(padapter) == _TRUE)) {
+		u8 val8;
+
+		val8 = rtw_btcoex_LpsVal(padapter);
+		if (val8 & BIT(4))
+			pslv = PS_STATE_S2;
+
+	}
+#endif /* CONFIG_BT_COEXIST */
+
+	_enter_pwrlock(&pwrctrl->lock);
+
+	unregister_task_alive(pwrctrl, task);
+
+	if ((pwrctrl->pwr_mode != PS_MODE_ACTIVE)
+	    && (pwrctrl->bFwCurrentInPSMode == _TRUE)) {
+
+		if (pwrctrl->cpwm > pslv) {
+			if ((pslv >= PS_STATE_S2) || (pwrctrl->alives == 0))
+				rtw_set_rpwm(padapter, pslv);
+		}
+	}
+
+	_exit_pwrlock(&pwrctrl->lock);
+
+}
+
+/*
+ * Caller: rtw_xmit_thread
+ *
+ * Check if the fw_pwrstate is okay for xmit.
+ * If not (cpwm is less than S3), then the sub-routine
+ * will raise the cpwm to be greater than or equal to S3.
+ *
+ * Calling Context: Passive
+ *
+ * Return Value:
+ *	 _SUCCESS	rtw_xmit_thread can write fifo/txcmd afterwards.
+ *	 _FAIL		rtw_xmit_thread can not do anything.
+ */
+s32 rtw_register_tx_alive(PADAPTER padapter)
+{
+	s32 res;
+	struct pwrctrl_priv *pwrctrl;
+	u8 pslv;
+
+
+	res = _SUCCESS;
+	pwrctrl = adapter_to_pwrctl(padapter);
+	pslv = PS_STATE_S2;
+
+	_enter_pwrlock(&pwrctrl->lock);
+
+	register_task_alive(pwrctrl, XMIT_ALIVE);
+
+	if (pwrctrl->bFwCurrentInPSMode == _TRUE) {
+
+		if (pwrctrl->cpwm < pslv) {
+			if (pwrctrl->cpwm < PS_STATE_S2)
+				res = _FAIL;
+			if (pwrctrl->rpwm < pslv)
+				rtw_set_rpwm(padapter, pslv);
+		}
+	}
+
+	_exit_pwrlock(&pwrctrl->lock);
+
+#ifdef CONFIG_DETECT_CPWM_BY_POLLING
+	if (_FAIL == res) {
+		if (pwrctrl->cpwm >= PS_STATE_S2)
+			res = _SUCCESS;
+	}
+#endif /* CONFIG_DETECT_CPWM_BY_POLLING */
+
+
+	return res;
+}
+
+/*
+ * Caller: rtw_cmd_thread
+ *
+ * Check if the fw_pwrstate is okay for issuing cmd.
+ * If not (cpwm should be is less than S2), then the sub-routine
+ * will raise the cpwm to be greater than or equal to S2.
+ *
+ * Calling Context: Passive
+ *
+ * Return Value:
+ *	_SUCCESS	rtw_cmd_thread can issue cmds to firmware afterwards.
+ *	_FAIL		rtw_cmd_thread can not do anything.
+ */
+s32 rtw_register_cmd_alive(PADAPTER padapter)
+{
+	s32 res;
+	struct pwrctrl_priv *pwrctrl;
+	u8 pslv;
+
+
+	res = _SUCCESS;
+	pwrctrl = adapter_to_pwrctl(padapter);
+	pslv = PS_STATE_S2;
+
+	_enter_pwrlock(&pwrctrl->lock);
+
+	register_task_alive(pwrctrl, CMD_ALIVE);
+
+	if (pwrctrl->bFwCurrentInPSMode == _TRUE) {
+
+		if (pwrctrl->cpwm < pslv) {
+			if (pwrctrl->cpwm < PS_STATE_S2)
+				res = _FAIL;
+			if (pwrctrl->rpwm < pslv)
+				rtw_set_rpwm(padapter, pslv);
+		}
+	}
+
+	_exit_pwrlock(&pwrctrl->lock);
+
+#ifdef CONFIG_DETECT_CPWM_BY_POLLING
+	if (_FAIL == res) {
+		if (pwrctrl->cpwm >= PS_STATE_S2)
+			res = _SUCCESS;
+	}
+#endif /* CONFIG_DETECT_CPWM_BY_POLLING */
+
+
+	return res;
+}
+
+/*
+ * Caller: rx_isr
+ *
+ * Calling Context: Dispatch/ISR
+ *
+ * Return Value:
+ *	_SUCCESS
+ *	_FAIL
+ */
+s32 rtw_register_rx_alive(PADAPTER padapter)
+{
+	struct pwrctrl_priv *pwrctrl;
+
+
+	pwrctrl = adapter_to_pwrctl(padapter);
+
+	_enter_pwrlock(&pwrctrl->lock);
+
+	register_task_alive(pwrctrl, RECV_ALIVE);
+
+	_exit_pwrlock(&pwrctrl->lock);
+
+
+	return _SUCCESS;
+}
+
+/*
+ * Caller: evt_isr or evt_thread
+ *
+ * Calling Context: Dispatch/ISR or Passive
+ *
+ * Return Value:
+ *	_SUCCESS
+ *	_FAIL
+ */
+s32 rtw_register_evt_alive(PADAPTER padapter)
+{
+	struct pwrctrl_priv *pwrctrl;
+
+
+	pwrctrl = adapter_to_pwrctl(padapter);
+
+	_enter_pwrlock(&pwrctrl->lock);
+
+	register_task_alive(pwrctrl, EVT_ALIVE);
+
+	_exit_pwrlock(&pwrctrl->lock);
+
+
+	return _SUCCESS;
+}
+
+/*
+ * Caller: ISR
+ *
+ * If ISR's txdone,
+ * No more pkts for TX,
+ * Then driver shall call this fun. to power down firmware again.
+ */
+void rtw_unregister_tx_alive(PADAPTER padapter)
+{
+	struct pwrctrl_priv *pwrctrl;
+	_adapter *iface;
+	struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
+	u8 pslv, i;
+
+
+	pwrctrl = adapter_to_pwrctl(padapter);
+	pslv = PS_STATE_S0;
+
+#ifdef CONFIG_BT_COEXIST
+	if ((rtw_btcoex_IsBtDisabled(padapter) == _FALSE)
+	    && (rtw_btcoex_IsBtControlLps(padapter) == _TRUE)) {
+		u8 val8;
+
+		val8 = rtw_btcoex_LpsVal(padapter);
+		if (val8 & BIT(4))
+			pslv = PS_STATE_S2;
+
+	}
+#endif /* CONFIG_BT_COEXIST */
+
+#ifdef CONFIG_P2P_PS
+	for (i = 0; i < dvobj->iface_nums; i++) {
+		iface = dvobj->padapters[i];
+		if ((iface) && rtw_is_adapter_up(iface)) {
+			if (iface->wdinfo.p2p_ps_mode > P2P_PS_NONE) {
+				pslv = PS_STATE_S2;
+				break;
+			}
+		}
+	}
+#endif
+	_enter_pwrlock(&pwrctrl->lock);
+
+	unregister_task_alive(pwrctrl, XMIT_ALIVE);
+
+	if ((pwrctrl->pwr_mode != PS_MODE_ACTIVE)
+	    && (pwrctrl->bFwCurrentInPSMode == _TRUE)) {
+
+		if (pwrctrl->cpwm > pslv) {
+			if ((pslv >= PS_STATE_S2) || (pwrctrl->alives == 0))
+				rtw_set_rpwm(padapter, pslv);
+		}
+	}
+
+	_exit_pwrlock(&pwrctrl->lock);
+
+}
+
+/*
+ * Caller: ISR
+ *
+ * If all commands have been done,
+ * and no more command to do,
+ * then driver shall call this fun. to power down firmware again.
+ */
+void rtw_unregister_cmd_alive(PADAPTER padapter)
+{
+	_adapter *iface;
+	struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
+	struct pwrctrl_priv *pwrctrl;
+	u8 pslv, i;
+
+
+	pwrctrl = adapter_to_pwrctl(padapter);
+	pslv = PS_STATE_S0;
+
+#ifdef CONFIG_BT_COEXIST
+	if ((rtw_btcoex_IsBtDisabled(padapter) == _FALSE)
+	    && (rtw_btcoex_IsBtControlLps(padapter) == _TRUE)) {
+		u8 val8;
+
+		val8 = rtw_btcoex_LpsVal(padapter);
+		if (val8 & BIT(4))
+			pslv = PS_STATE_S2;
+
+	}
+#endif /* CONFIG_BT_COEXIST */
+
+#ifdef CONFIG_P2P_PS
+	for (i = 0; i < dvobj->iface_nums; i++) {
+		iface = dvobj->padapters[i];
+		if ((iface) && rtw_is_adapter_up(iface)) {
+			if (iface->wdinfo.p2p_ps_mode > P2P_PS_NONE) {
+				pslv = PS_STATE_S2;
+				break;
+			}
+		}
+	}
+#endif
+
+	_enter_pwrlock(&pwrctrl->lock);
+
+	unregister_task_alive(pwrctrl, CMD_ALIVE);
+
+	if ((pwrctrl->pwr_mode != PS_MODE_ACTIVE)
+	    && (pwrctrl->bFwCurrentInPSMode == _TRUE)) {
+
+		if (pwrctrl->cpwm > pslv) {
+			if ((pslv >= PS_STATE_S2) || (pwrctrl->alives == 0))
+				rtw_set_rpwm(padapter, pslv);
+		}
+	}
+
+	_exit_pwrlock(&pwrctrl->lock);
+
+}
+
+/*
+ * Caller: ISR
+ */
+void rtw_unregister_rx_alive(PADAPTER padapter)
+{
+	struct pwrctrl_priv *pwrctrl;
+
+
+	pwrctrl = adapter_to_pwrctl(padapter);
+
+	_enter_pwrlock(&pwrctrl->lock);
+
+	unregister_task_alive(pwrctrl, RECV_ALIVE);
+
+
+	_exit_pwrlock(&pwrctrl->lock);
+
+}
+
+void rtw_unregister_evt_alive(PADAPTER padapter)
+{
+	struct pwrctrl_priv *pwrctrl;
+
+
+	pwrctrl = adapter_to_pwrctl(padapter);
+
+	unregister_task_alive(pwrctrl, EVT_ALIVE);
+
+
+	_exit_pwrlock(&pwrctrl->lock);
+
+}
+#endif	/* CONFIG_LPS_LCLK */
+
+#ifdef CONFIG_RESUME_IN_WORKQUEUE
+	static void resume_workitem_callback(struct work_struct *work);
+#endif /* CONFIG_RESUME_IN_WORKQUEUE */
+
+void rtw_init_pwrctrl_priv(PADAPTER padapter)
+{
+	struct pwrctrl_priv *pwrctrlpriv = adapter_to_pwrctl(padapter);
+#ifdef CONFIG_WOWLAN
+	struct registry_priv  *registry_par = &padapter->registrypriv;
+#endif
+#ifdef CONFIG_GPIO_WAKEUP
+	u8 val8 = 0;
+#endif
+
+#if defined(CONFIG_CONCURRENT_MODE)
+	if (!is_primary_adapter(padapter))
+		return;
+#endif
+
+
+#ifdef PLATFORM_WINDOWS
+	pwrctrlpriv->pnp_current_pwr_state = NdisDeviceStateD0;
+#endif
+
+	_init_pwrlock(&pwrctrlpriv->lock);
+	_init_pwrlock(&pwrctrlpriv->check_32k_lock);
+	pwrctrlpriv->rf_pwrstate = rf_on;
+	pwrctrlpriv->ips_enter_cnts = 0;
+	pwrctrlpriv->ips_leave_cnts = 0;
+	pwrctrlpriv->lps_enter_cnts = 0;
+	pwrctrlpriv->lps_leave_cnts = 0;
+	pwrctrlpriv->bips_processing = _FALSE;
+#ifdef CONFIG_LPS_CHK_BY_TP
+	pwrctrlpriv->lps_chk_by_tp = padapter->registrypriv.lps_chk_by_tp;
+	pwrctrlpriv->lps_tx_tp_th = LPS_TX_TP_TH;
+	pwrctrlpriv->lps_rx_tp_th = LPS_RX_TP_TH;
+	pwrctrlpriv->lps_bi_tp_th = LPS_BI_TP_TH;
+	pwrctrlpriv->lps_chk_cnt = pwrctrlpriv->lps_chk_cnt_th = LPS_TP_CHK_CNT;
+	pwrctrlpriv->lps_tx_pkts = LPS_CHK_PKTS_TX;
+	pwrctrlpriv->lps_rx_pkts = LPS_CHK_PKTS_RX;
+#endif
+
+	pwrctrlpriv->ips_mode = padapter->registrypriv.ips_mode;
+	pwrctrlpriv->ips_mode_req = padapter->registrypriv.ips_mode;
+	pwrctrlpriv->ips_deny_time = rtw_get_current_time();
+	pwrctrlpriv->lps_level = padapter->registrypriv.lps_level;
+
+	pwrctrlpriv->pwr_state_check_interval = RTW_PWR_STATE_CHK_INTERVAL;
+	pwrctrlpriv->pwr_state_check_cnts = 0;
+	#ifdef CONFIG_AUTOSUSPEND
+	pwrctrlpriv->bInternalAutoSuspend = _FALSE;
+	#endif
+	pwrctrlpriv->bInSuspend = _FALSE;
+	pwrctrlpriv->bkeepfwalive = _FALSE;
+
+#ifdef CONFIG_AUTOSUSPEND
+#ifdef SUPPORT_HW_RFOFF_DETECTED
+	pwrctrlpriv->pwr_state_check_interval = (pwrctrlpriv->bHWPwrPindetect) ? 1000 : 2000;
+#endif
+#endif
+
+	pwrctrlpriv->LpsIdleCount = 0;
+
+#ifdef CONFIG_LPS_PG
+	pwrctrlpriv->lpspg_rsvd_page_locate = 0;
+#endif
+
+	/* pwrctrlpriv->FWCtrlPSMode =padapter->registrypriv.power_mgnt; */ /* PS_MODE_MIN; */
+	if (padapter->registrypriv.mp_mode == 1)
+		pwrctrlpriv->power_mgnt = PS_MODE_ACTIVE ;
+	else
+		pwrctrlpriv->power_mgnt = padapter->registrypriv.power_mgnt; /* PS_MODE_MIN; */
+	pwrctrlpriv->bLeisurePs = (PS_MODE_ACTIVE != pwrctrlpriv->power_mgnt) ? _TRUE : _FALSE;
+
+	pwrctrlpriv->bFwCurrentInPSMode = _FALSE;
+
+	pwrctrlpriv->rpwm = 0;
+	pwrctrlpriv->cpwm = PS_STATE_S4;
+
+	pwrctrlpriv->pwr_mode = PS_MODE_ACTIVE;
+	pwrctrlpriv->smart_ps = padapter->registrypriv.smart_ps;
+	pwrctrlpriv->bcn_ant_mode = 0;
+	pwrctrlpriv->dtim = 0;
+
+	pwrctrlpriv->tog = 0x80;
+	pwrctrlpriv->rpwm_retry = 0;
+
+#ifdef CONFIG_LPS_LCLK
+	rtw_hal_set_hwreg(padapter, HW_VAR_SET_RPWM, (u8 *)(&pwrctrlpriv->rpwm));
+
+	_init_workitem(&pwrctrlpriv->cpwm_event, cpwm_event_callback, NULL);
+
+	_init_workitem(&pwrctrlpriv->dma_event, dma_event_callback, NULL);
+
+#ifdef CONFIG_LPS_RPWM_TIMER
+	pwrctrlpriv->brpwmtimeout = _FALSE;
+	_init_workitem(&pwrctrlpriv->rpwmtimeoutwi, rpwmtimeout_workitem_callback, NULL);
+	rtw_init_timer(&pwrctrlpriv->pwr_rpwm_timer, padapter, pwr_rpwm_timeout_handler, padapter);
+#endif /* CONFIG_LPS_RPWM_TIMER */
+#endif /* CONFIG_LPS_LCLK */
+
+	rtw_init_timer(&pwrctrlpriv->pwr_state_check_timer, padapter, pwr_state_check_handler, padapter);
+
+	pwrctrlpriv->wowlan_mode = _FALSE;
+	pwrctrlpriv->wowlan_ap_mode = _FALSE;
+	pwrctrlpriv->wowlan_p2p_mode = _FALSE;
+	pwrctrlpriv->wowlan_in_resume = _FALSE;
+	pwrctrlpriv->wowlan_last_wake_reason = 0;
+
+#ifdef CONFIG_RESUME_IN_WORKQUEUE
+	_init_workitem(&pwrctrlpriv->resume_work, resume_workitem_callback, NULL);
+	pwrctrlpriv->rtw_workqueue = create_singlethread_workqueue("rtw_workqueue");
+#endif /* CONFIG_RESUME_IN_WORKQUEUE */
+
+#if defined(CONFIG_HAS_EARLYSUSPEND) || defined(CONFIG_ANDROID_POWER)
+	pwrctrlpriv->early_suspend.suspend = NULL;
+	rtw_register_early_suspend(pwrctrlpriv);
+#endif /* CONFIG_HAS_EARLYSUSPEND || CONFIG_ANDROID_POWER */
+
+#ifdef CONFIG_GPIO_WAKEUP
+	/*default low active*/
+	pwrctrlpriv->is_high_active = HIGH_ACTIVE_DEV2HST;
+	pwrctrlpriv->hst2dev_high_active = HIGH_ACTIVE_HST2DEV;
+#ifdef CONFIG_RTW_ONE_PIN_GPIO
+	rtw_hal_switch_gpio_wl_ctrl(padapter, WAKEUP_GPIO_IDX, _TRUE);
+	rtw_hal_set_input_gpio(padapter, WAKEUP_GPIO_IDX);
+#else
+	#ifdef CONFIG_WAKEUP_GPIO_INPUT_MODE
+	if (pwrctrlpriv->is_high_active == 0)
+		rtw_hal_set_input_gpio(padapter, WAKEUP_GPIO_IDX);
+	else
+		rtw_hal_set_output_gpio(padapter, WAKEUP_GPIO_IDX, 0);
+	#else
+	val8 = (pwrctrlpriv->is_high_active == 0) ? 1 : 0;
+	rtw_hal_set_output_gpio(padapter, WAKEUP_GPIO_IDX, val8);
+	RTW_INFO("%s: set GPIO_%d %d as default.\n",
+		 __func__, WAKEUP_GPIO_IDX, val8);
+	#endif /*CONFIG_WAKEUP_GPIO_INPUT_MODE*/
+#endif /* CONFIG_RTW_ONE_PIN_GPIO */
+#endif /* CONFIG_GPIO_WAKEUP */
+
+#ifdef CONFIG_WOWLAN
+
+	if (registry_par->wakeup_event & BIT(1))
+		pwrctrlpriv->default_patterns_en = _TRUE;
+	else
+		pwrctrlpriv->default_patterns_en = _FALSE;
+
+	rtw_wow_pattern_sw_reset(padapter);
+#ifdef CONFIG_PNO_SUPPORT
+	pwrctrlpriv->pno_inited = _FALSE;
+	pwrctrlpriv->pnlo_info = NULL;
+	pwrctrlpriv->pscan_info = NULL;
+	pwrctrlpriv->pno_ssid_list = NULL;
+#endif /* CONFIG_PNO_SUPPORT */
+#ifdef CONFIG_WOW_PATTERN_HW_CAM
+	_rtw_mutex_init(&pwrctrlpriv->wowlan_pattern_cam_mutex);
+#endif
+	pwrctrlpriv->wowlan_aoac_rpt_loc = 0;
+#endif /* CONFIG_WOWLAN */
+
+#ifdef CONFIG_LPS_POFF
+	rtw_hal_set_hwreg(padapter, HW_VAR_LPS_POFF_INIT, 0);
+#endif
+
+
+}
+
+
+void rtw_free_pwrctrl_priv(PADAPTER adapter)
+{
+	struct pwrctrl_priv *pwrctrlpriv = adapter_to_pwrctl(adapter);
+
+#if defined(CONFIG_CONCURRENT_MODE)
+	if (!is_primary_adapter(adapter))
+		return;
+#endif
+
+
+	/* _rtw_memset((unsigned char *)pwrctrlpriv, 0, sizeof(struct pwrctrl_priv)); */
+
+
+#ifdef CONFIG_RESUME_IN_WORKQUEUE
+	if (pwrctrlpriv->rtw_workqueue) {
+		flush_workqueue(pwrctrlpriv->rtw_workqueue);
+		destroy_workqueue(pwrctrlpriv->rtw_workqueue);
+	}
+#endif
+
+#ifdef CONFIG_LPS_POFF
+	rtw_hal_set_hwreg(adapter, HW_VAR_LPS_POFF_DEINIT, 0);
+#endif
+
+#ifdef CONFIG_LPS_LCLK
+	_cancel_workitem_sync(&pwrctrlpriv->cpwm_event);
+	_cancel_workitem_sync(&pwrctrlpriv->dma_event);
+	#ifdef CONFIG_LPS_RPWM_TIMER
+	_cancel_workitem_sync(&pwrctrlpriv->rpwmtimeoutwi);
+	#endif
+#endif /* CONFIG_LPS_LCLK */
+
+#ifdef CONFIG_WOWLAN
+#ifdef CONFIG_PNO_SUPPORT
+	if (pwrctrlpriv->pnlo_info != NULL)
+		printk("****** pnlo_info memory leak********\n");
+
+	if (pwrctrlpriv->pscan_info != NULL)
+		printk("****** pscan_info memory leak********\n");
+
+	if (pwrctrlpriv->pno_ssid_list != NULL)
+		printk("****** pno_ssid_list memory leak********\n");
+#endif
+#ifdef CONFIG_WOW_PATTERN_HW_CAM
+	_rtw_mutex_free(&pwrctrlpriv->wowlan_pattern_cam_mutex);
+#endif
+
+#endif /* CONFIG_WOWLAN */
+
+#if defined(CONFIG_HAS_EARLYSUSPEND) || defined(CONFIG_ANDROID_POWER)
+	rtw_unregister_early_suspend(pwrctrlpriv);
+#endif /* CONFIG_HAS_EARLYSUSPEND || CONFIG_ANDROID_POWER */
+
+	_free_pwrlock(&pwrctrlpriv->lock);
+	_free_pwrlock(&pwrctrlpriv->check_32k_lock);
+
+}
+
+#ifdef CONFIG_RESUME_IN_WORKQUEUE
+extern int rtw_resume_process(_adapter *padapter);
+
+static void resume_workitem_callback(struct work_struct *work)
+{
+	struct pwrctrl_priv *pwrpriv = container_of(work, struct pwrctrl_priv, resume_work);
+	struct dvobj_priv *dvobj = pwrctl_to_dvobj(pwrpriv);
+	_adapter *adapter = dvobj_get_primary_adapter(dvobj);
+
+	RTW_INFO("%s\n", __FUNCTION__);
+
+	rtw_resume_process(adapter);
+
+	rtw_resume_unlock_suspend();
+}
+
+void rtw_resume_in_workqueue(struct pwrctrl_priv *pwrpriv)
+{
+	/* accquire system's suspend lock preventing from falliing asleep while resume in workqueue */
+	/* rtw_lock_suspend(); */
+
+	rtw_resume_lock_suspend();
+
+#if 1
+	queue_work(pwrpriv->rtw_workqueue, &pwrpriv->resume_work);
+#else
+	_set_workitem(&pwrpriv->resume_work);
+#endif
+}
+#endif /* CONFIG_RESUME_IN_WORKQUEUE */
+
+#if defined(CONFIG_HAS_EARLYSUSPEND) || defined(CONFIG_ANDROID_POWER)
+inline bool rtw_is_earlysuspend_registered(struct pwrctrl_priv *pwrpriv)
+{
+	return (pwrpriv->early_suspend.suspend) ? _TRUE : _FALSE;
+}
+
+inline bool rtw_is_do_late_resume(struct pwrctrl_priv *pwrpriv)
+{
+	return (pwrpriv->do_late_resume) ? _TRUE : _FALSE;
+}
+
+inline void rtw_set_do_late_resume(struct pwrctrl_priv *pwrpriv, bool enable)
+{
+	pwrpriv->do_late_resume = enable;
+}
+#endif
+
+#ifdef CONFIG_HAS_EARLYSUSPEND
+extern int rtw_resume_process(_adapter *padapter);
+static void rtw_early_suspend(struct early_suspend *h)
+{
+	struct pwrctrl_priv *pwrpriv = container_of(h, struct pwrctrl_priv, early_suspend);
+	RTW_INFO("%s\n", __FUNCTION__);
+
+	rtw_set_do_late_resume(pwrpriv, _FALSE);
+}
+
+static void rtw_late_resume(struct early_suspend *h)
+{
+	struct pwrctrl_priv *pwrpriv = container_of(h, struct pwrctrl_priv, early_suspend);
+	struct dvobj_priv *dvobj = pwrctl_to_dvobj(pwrpriv);
+	_adapter *adapter = dvobj_get_primary_adapter(dvobj);
+
+	RTW_INFO("%s\n", __FUNCTION__);
+
+	if (pwrpriv->do_late_resume) {
+		rtw_set_do_late_resume(pwrpriv, _FALSE);
+		rtw_resume_process(adapter);
+	}
+}
+
+void rtw_register_early_suspend(struct pwrctrl_priv *pwrpriv)
+{
+	RTW_INFO("%s\n", __FUNCTION__);
+
+	/* jeff: set the early suspend level before blank screen, so we wll do late resume after scree is lit */
+	pwrpriv->early_suspend.level = EARLY_SUSPEND_LEVEL_BLANK_SCREEN - 20;
+	pwrpriv->early_suspend.suspend = rtw_early_suspend;
+	pwrpriv->early_suspend.resume = rtw_late_resume;
+	register_early_suspend(&pwrpriv->early_suspend);
+
+
+}
+
+void rtw_unregister_early_suspend(struct pwrctrl_priv *pwrpriv)
+{
+	RTW_INFO("%s\n", __FUNCTION__);
+
+	rtw_set_do_late_resume(pwrpriv, _FALSE);
+
+	if (pwrpriv->early_suspend.suspend)
+		unregister_early_suspend(&pwrpriv->early_suspend);
+
+	pwrpriv->early_suspend.suspend = NULL;
+	pwrpriv->early_suspend.resume = NULL;
+}
+#endif /* CONFIG_HAS_EARLYSUSPEND */
+
+#ifdef CONFIG_ANDROID_POWER
+#if defined(CONFIG_USB_HCI) || defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
+	extern int rtw_resume_process(PADAPTER padapter);
+#endif
+static void rtw_early_suspend(android_early_suspend_t *h)
+{
+	struct pwrctrl_priv *pwrpriv = container_of(h, struct pwrctrl_priv, early_suspend);
+	RTW_INFO("%s\n", __FUNCTION__);
+
+	rtw_set_do_late_resume(pwrpriv, _FALSE);
+}
+
+static void rtw_late_resume(android_early_suspend_t *h)
+{
+	struct pwrctrl_priv *pwrpriv = container_of(h, struct pwrctrl_priv, early_suspend);
+	struct dvobj_priv *dvobj = pwrctl_to_dvobj(pwrpriv);
+	_adapter *adapter = dvobj_get_primary_adapter(dvobj);
+
+	RTW_INFO("%s\n", __FUNCTION__);
+	if (pwrpriv->do_late_resume) {
+#if defined(CONFIG_USB_HCI) || defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
+		rtw_set_do_late_resume(pwrpriv, _FALSE);
+		rtw_resume_process(adapter);
+#endif
+	}
+}
+
+void rtw_register_early_suspend(struct pwrctrl_priv *pwrpriv)
+{
+	RTW_INFO("%s\n", __FUNCTION__);
+
+	/* jeff: set the early suspend level before blank screen, so we wll do late resume after scree is lit */
+	pwrpriv->early_suspend.level = ANDROID_EARLY_SUSPEND_LEVEL_BLANK_SCREEN - 20;
+	pwrpriv->early_suspend.suspend = rtw_early_suspend;
+	pwrpriv->early_suspend.resume = rtw_late_resume;
+	android_register_early_suspend(&pwrpriv->early_suspend);
+}
+
+void rtw_unregister_early_suspend(struct pwrctrl_priv *pwrpriv)
+{
+	RTW_INFO("%s\n", __FUNCTION__);
+
+	rtw_set_do_late_resume(pwrpriv, _FALSE);
+
+	if (pwrpriv->early_suspend.suspend)
+		android_unregister_early_suspend(&pwrpriv->early_suspend);
+
+	pwrpriv->early_suspend.suspend = NULL;
+	pwrpriv->early_suspend.resume = NULL;
+}
+#endif /* CONFIG_ANDROID_POWER */
+
+u8 rtw_interface_ps_func(_adapter *padapter, HAL_INTF_PS_FUNC efunc_id, u8 *val)
+{
+	u8 bResult = _TRUE;
+	rtw_hal_intf_ps_func(padapter, efunc_id, val);
+
+	return bResult;
+}
+
+
+inline void rtw_set_ips_deny(_adapter *padapter, u32 ms)
+{
+	struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter);
+	pwrpriv->ips_deny_time = rtw_get_current_time() + rtw_ms_to_systime(ms);
+}
+
+/*
+* rtw_pwr_wakeup - Wake the NIC up from: 1)IPS. 2)USB autosuspend
+* @adapter: pointer to _adapter structure
+* @ips_deffer_ms: the ms wiil prevent from falling into IPS after wakeup
+* Return _SUCCESS or _FAIL
+*/
+
+int _rtw_pwr_wakeup(_adapter *padapter, u32 ips_deffer_ms, const char *caller)
+{
+	struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
+	struct pwrctrl_priv *pwrpriv = dvobj_to_pwrctl(dvobj);
+	struct mlme_priv *pmlmepriv;
+	int ret = _SUCCESS;
+	systime start = rtw_get_current_time();
+
+	/*RTW_INFO(FUNC_ADPT_FMT "===>\n", FUNC_ADPT_ARG(padapter));*/
+	/* for LPS */
+	LeaveAllPowerSaveMode(padapter);
+
+	/* IPS still bound with primary adapter */
+	padapter = GET_PRIMARY_ADAPTER(padapter);
+	pmlmepriv = &padapter->mlmepriv;
+
+	if (rtw_time_after(rtw_get_current_time() + rtw_ms_to_systime(ips_deffer_ms), pwrpriv->ips_deny_time))
+		pwrpriv->ips_deny_time = rtw_get_current_time() + rtw_ms_to_systime(ips_deffer_ms);
+
+
+	if (pwrpriv->ps_processing) {
+		RTW_INFO("%s wait ps_processing...\n", __func__);
+		while (pwrpriv->ps_processing && rtw_get_passing_time_ms(start) <= 3000)
+			rtw_msleep_os(10);
+		if (pwrpriv->ps_processing)
+			RTW_INFO("%s wait ps_processing timeout\n", __func__);
+		else
+			RTW_INFO("%s wait ps_processing done\n", __func__);
+	}
+
+#ifdef DBG_CONFIG_ERROR_DETECT
+	if (rtw_hal_sreset_inprogress(padapter)) {
+		RTW_INFO("%s wait sreset_inprogress...\n", __func__);
+		while (rtw_hal_sreset_inprogress(padapter) && rtw_get_passing_time_ms(start) <= 4000)
+			rtw_msleep_os(10);
+		if (rtw_hal_sreset_inprogress(padapter))
+			RTW_INFO("%s wait sreset_inprogress timeout\n", __func__);
+		else
+			RTW_INFO("%s wait sreset_inprogress done\n", __func__);
+	}
+#endif
+
+	if (pwrpriv->bInSuspend
+		#ifdef CONFIG_AUTOSUSPEND
+		&& pwrpriv->bInternalAutoSuspend == _FALSE
+		#endif
+		) {
+		RTW_INFO("%s wait bInSuspend...\n", __func__);
+		while (pwrpriv->bInSuspend
+		       && ((rtw_get_passing_time_ms(start) <= 3000 && !rtw_is_do_late_resume(pwrpriv))
+			|| (rtw_get_passing_time_ms(start) <= 500 && rtw_is_do_late_resume(pwrpriv)))
+		      )
+			rtw_msleep_os(10);
+		if (pwrpriv->bInSuspend)
+			RTW_INFO("%s wait bInSuspend timeout\n", __func__);
+		else
+			RTW_INFO("%s wait bInSuspend done\n", __func__);
+	}
+
+	/* System suspend is not allowed to wakeup */
+	if ((_TRUE == pwrpriv->bInSuspend)
+		#ifdef CONFIG_AUTOSUSPEND
+		&& (pwrpriv->bInternalAutoSuspend == _FALSE)
+		#endif
+	) {
+		ret = _FAIL;
+		goto exit;
+	}
+#ifdef CONFIG_AUTOSUSPEND
+	/* usb autosuspend block??? */
+	if ((pwrpriv->bInternalAutoSuspend == _TRUE)  && (padapter->net_closed == _TRUE)) {
+		ret = _FAIL;
+		goto exit;
+	}
+#endif
+	/* I think this should be check in IPS, LPS, autosuspend functions... */
+	if (check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE) {
+#if defined(CONFIG_BT_COEXIST) && defined (CONFIG_AUTOSUSPEND)
+		if (_TRUE == pwrpriv->bInternalAutoSuspend) {
+			if (0 == pwrpriv->autopm_cnt) {
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 33))
+				if (usb_autopm_get_interface(adapter_to_dvobj(padapter)->pusbintf) < 0)
+					RTW_INFO("can't get autopm:\n");
+#elif (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 20))
+				usb_autopm_disable(adapter_to_dvobj(padapter)->pusbintf);
+#else
+				usb_autoresume_device(adapter_to_dvobj(padapter)->pusbdev, 1);
+#endif
+				pwrpriv->autopm_cnt++;
+			}
+#endif	/* #if defined (CONFIG_BT_COEXIST) && defined (CONFIG_AUTOSUSPEND) */
+			ret = _SUCCESS;
+			goto exit;
+#if defined(CONFIG_BT_COEXIST) && defined (CONFIG_AUTOSUSPEND)
+		}
+#endif	/* #if defined (CONFIG_BT_COEXIST) && defined (CONFIG_AUTOSUSPEND) */
+	}
+
+	if (rf_off == pwrpriv->rf_pwrstate) {
+#ifdef CONFIG_USB_HCI
+#ifdef CONFIG_AUTOSUSPEND
+		if (pwrpriv->brfoffbyhw == _TRUE) {
+			RTW_INFO("hw still in rf_off state ...........\n");
+			ret = _FAIL;
+			goto exit;
+		} else if (padapter->registrypriv.usbss_enable) {
+			RTW_INFO("%s call autoresume_enter....\n", __FUNCTION__);
+			if (_FAIL ==  autoresume_enter(padapter)) {
+				RTW_INFO("======> autoresume fail.............\n");
+				ret = _FAIL;
+				goto exit;
+			}
+		} else
+#endif
+#endif
+		{
+#ifdef CONFIG_IPS
+			RTW_INFO("%s call ips_leave....\n", __FUNCTION__);
+			if (_FAIL ==  ips_leave(padapter)) {
+				RTW_INFO("======> ips_leave fail.............\n");
+				ret = _FAIL;
+				goto exit;
+			}
+#endif
+		}
+	}
+
+	/* TODO: the following checking need to be merged... */
+	if (rtw_is_drv_stopped(padapter)
+	    || !padapter->bup
+	    || !rtw_is_hw_init_completed(padapter)
+	   ) {
+		RTW_INFO("%s: bDriverStopped=%s, bup=%d, hw_init_completed=%u\n"
+			 , caller
+			 , rtw_is_drv_stopped(padapter) ? "True" : "False"
+			 , padapter->bup
+			 , rtw_get_hw_init_completed(padapter));
+		ret = _FALSE;
+		goto exit;
+	}
+
+exit:
+	if (rtw_time_after(rtw_get_current_time() + rtw_ms_to_systime(ips_deffer_ms), pwrpriv->ips_deny_time))
+		pwrpriv->ips_deny_time = rtw_get_current_time() + rtw_ms_to_systime(ips_deffer_ms);
+	/*RTW_INFO(FUNC_ADPT_FMT "<===\n", FUNC_ADPT_ARG(padapter));*/
+	return ret;
+
+}
+
+int rtw_pm_set_lps(_adapter *padapter, u8 mode)
+{
+	int	ret = 0;
+	struct pwrctrl_priv *pwrctrlpriv = adapter_to_pwrctl(padapter);
+
+	if (mode < PS_MODE_NUM) {
+		if (pwrctrlpriv->power_mgnt != mode) {
+			if (PS_MODE_ACTIVE == mode)
+				LeaveAllPowerSaveMode(padapter);
+			else
+				pwrctrlpriv->LpsIdleCount = 2;
+			pwrctrlpriv->power_mgnt = mode;
+			pwrctrlpriv->bLeisurePs = (PS_MODE_ACTIVE != pwrctrlpriv->power_mgnt) ? _TRUE : _FALSE;
+		}
+	} else
+		ret = -EINVAL;
+
+	return ret;
+}
+
+int rtw_pm_set_lps_level(_adapter *padapter, u8 level)
+{
+	int	ret = 0;
+	struct pwrctrl_priv *pwrctrlpriv = adapter_to_pwrctl(padapter);
+
+	if (level < LPS_LEVEL_MAX)
+		pwrctrlpriv->lps_level = level;
+	else
+		ret = -EINVAL;
+
+	return ret;
+}
+
+int rtw_pm_set_ips(_adapter *padapter, u8 mode)
+{
+	struct pwrctrl_priv *pwrctrlpriv = adapter_to_pwrctl(padapter);
+
+	if (mode == IPS_NORMAL || mode == IPS_LEVEL_2) {
+		rtw_ips_mode_req(pwrctrlpriv, mode);
+		RTW_INFO("%s %s\n", __FUNCTION__, mode == IPS_NORMAL ? "IPS_NORMAL" : "IPS_LEVEL_2");
+		return 0;
+	} else if (mode == IPS_NONE) {
+		rtw_ips_mode_req(pwrctrlpriv, mode);
+		RTW_INFO("%s %s\n", __FUNCTION__, "IPS_NONE");
+		if (!rtw_is_surprise_removed(padapter) && (_FAIL == rtw_pwr_wakeup(padapter)))
+			return -EFAULT;
+	} else
+		return -EINVAL;
+	return 0;
+}
+
+/*
+ * ATTENTION:
+ *	This function will request pwrctrl LOCK!
+ */
+void rtw_ps_deny(PADAPTER padapter, PS_DENY_REASON reason)
+{
+	struct pwrctrl_priv *pwrpriv;
+
+	/* 	RTW_INFO("+" FUNC_ADPT_FMT ": Request PS deny for %d (0x%08X)\n",
+	 *		FUNC_ADPT_ARG(padapter), reason, BIT(reason)); */
+
+	pwrpriv = adapter_to_pwrctl(padapter);
+
+	_enter_pwrlock(&pwrpriv->lock);
+	if (pwrpriv->ps_deny & BIT(reason)) {
+		RTW_INFO(FUNC_ADPT_FMT ": [WARNING] Reason %d had been set before!!\n",
+			 FUNC_ADPT_ARG(padapter), reason);
+	}
+	pwrpriv->ps_deny |= BIT(reason);
+	_exit_pwrlock(&pwrpriv->lock);
+
+	/* 	RTW_INFO("-" FUNC_ADPT_FMT ": Now PS deny for 0x%08X\n",
+	 *		FUNC_ADPT_ARG(padapter), pwrpriv->ps_deny); */
+}
+
+/*
+ * ATTENTION:
+ *	This function will request pwrctrl LOCK!
+ */
+void rtw_ps_deny_cancel(PADAPTER padapter, PS_DENY_REASON reason)
+{
+	struct pwrctrl_priv *pwrpriv;
+
+
+	/* 	RTW_INFO("+" FUNC_ADPT_FMT ": Cancel PS deny for %d(0x%08X)\n",
+	 *		FUNC_ADPT_ARG(padapter), reason, BIT(reason)); */
+
+	pwrpriv = adapter_to_pwrctl(padapter);
+
+	_enter_pwrlock(&pwrpriv->lock);
+	if ((pwrpriv->ps_deny & BIT(reason)) == 0) {
+		RTW_INFO(FUNC_ADPT_FMT ": [ERROR] Reason %d had been canceled before!!\n",
+			 FUNC_ADPT_ARG(padapter), reason);
+	}
+	pwrpriv->ps_deny &= ~BIT(reason);
+	_exit_pwrlock(&pwrpriv->lock);
+
+	/* 	RTW_INFO("-" FUNC_ADPT_FMT ": Now PS deny for 0x%08X\n",
+	 *		FUNC_ADPT_ARG(padapter), pwrpriv->ps_deny); */
+}
+
+/*
+ * ATTENTION:
+ *	Before calling this function pwrctrl lock should be occupied already,
+ *	otherwise it may return incorrect value.
+ */
+u32 rtw_ps_deny_get(PADAPTER padapter)
+{
+	u32 deny;
+
+
+	deny = adapter_to_pwrctl(padapter)->ps_deny;
+
+	return deny;
+}
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/core/rtw_recv.c linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/core/rtw_recv.c
--- linux-5.6.3/3rdparty/rtl8821ce/core/rtw_recv.c	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/core/rtw_recv.c	2020-04-10 16:35:06.777658247 +0300
@@ -0,0 +1,5045 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#define _RTW_RECV_C_
+
+#include <drv_types.h>
+#include <hal_data.h>
+
+#if defined(PLATFORM_LINUX) && defined (PLATFORM_WINDOWS)
+
+	#error "Shall be Linux or Windows, but not both!\n"
+
+#endif
+
+
+#ifdef CONFIG_NEW_SIGNAL_STAT_PROCESS
+static void rtw_signal_stat_timer_hdl(void *ctx);
+
+enum {
+	SIGNAL_STAT_CALC_PROFILE_0 = 0,
+	SIGNAL_STAT_CALC_PROFILE_1,
+	SIGNAL_STAT_CALC_PROFILE_MAX
+};
+
+u8 signal_stat_calc_profile[SIGNAL_STAT_CALC_PROFILE_MAX][2] = {
+	{4, 1},	/* Profile 0 => pre_stat : curr_stat = 4 : 1 */
+	{3, 7}	/* Profile 1 => pre_stat : curr_stat = 3 : 7 */
+};
+
+#ifndef RTW_SIGNAL_STATE_CALC_PROFILE
+	#define RTW_SIGNAL_STATE_CALC_PROFILE SIGNAL_STAT_CALC_PROFILE_1
+#endif
+
+#endif /* CONFIG_NEW_SIGNAL_STAT_PROCESS */
+
+u8 rtw_bridge_tunnel_header[] = { 0xaa, 0xaa, 0x03, 0x00, 0x00, 0xf8 };
+u8 rtw_rfc1042_header[] = { 0xaa, 0xaa, 0x03, 0x00, 0x00, 0x00 };
+static u8 SNAP_ETH_TYPE_IPX[2] = {0x81, 0x37};
+static u8 SNAP_ETH_TYPE_APPLETALK_AARP[2] = {0x80, 0xf3};
+#ifdef CONFIG_TDLS
+static u8 SNAP_ETH_TYPE_TDLS[2] = {0x89, 0x0d};
+#endif
+
+void _rtw_init_sta_recv_priv(struct sta_recv_priv *psta_recvpriv)
+{
+
+
+
+	_rtw_memset((u8 *)psta_recvpriv, 0, sizeof(struct sta_recv_priv));
+
+	_rtw_spinlock_init(&psta_recvpriv->lock);
+
+	/* for(i=0; i<MAX_RX_NUMBLKS; i++) */
+	/*	_rtw_init_queue(&psta_recvpriv->blk_strms[i]); */
+
+	_rtw_init_queue(&psta_recvpriv->defrag_q);
+
+
+}
+
+sint _rtw_init_recv_priv(struct recv_priv *precvpriv, _adapter *padapter)
+{
+	sint i;
+
+	union recv_frame *precvframe;
+	sint	res = _SUCCESS;
+
+
+	/* We don't need to memset padapter->XXX to zero, because adapter is allocated by rtw_zvmalloc(). */
+	/* _rtw_memset((unsigned char *)precvpriv, 0, sizeof (struct  recv_priv)); */
+
+	_rtw_spinlock_init(&precvpriv->lock);
+
+#ifdef CONFIG_RECV_THREAD_MODE
+	_rtw_init_sema(&precvpriv->recv_sema, 0);
+
+#endif
+
+	_rtw_init_queue(&precvpriv->free_recv_queue);
+	_rtw_init_queue(&precvpriv->recv_pending_queue);
+	_rtw_init_queue(&precvpriv->uc_swdec_pending_queue);
+
+	precvpriv->adapter = padapter;
+
+	precvpriv->free_recvframe_cnt = NR_RECVFRAME;
+
+	precvpriv->sink_udpport = 0;
+	precvpriv->pre_rtp_rxseq = 0;
+	precvpriv->cur_rtp_rxseq = 0;
+
+#ifdef DBG_RX_SIGNAL_DISPLAY_RAW_DATA
+	precvpriv->store_law_data_flag = 1;
+#else
+	precvpriv->store_law_data_flag = 0;
+#endif
+
+	rtw_os_recv_resource_init(precvpriv, padapter);
+
+	precvpriv->pallocated_frame_buf = rtw_zvmalloc(NR_RECVFRAME * sizeof(union recv_frame) + RXFRAME_ALIGN_SZ);
+
+	if (precvpriv->pallocated_frame_buf == NULL) {
+		res = _FAIL;
+		goto exit;
+	}
+	/* _rtw_memset(precvpriv->pallocated_frame_buf, 0, NR_RECVFRAME * sizeof(union recv_frame) + RXFRAME_ALIGN_SZ); */
+
+	precvpriv->precv_frame_buf = (u8 *)N_BYTE_ALIGMENT((SIZE_PTR)(precvpriv->pallocated_frame_buf), RXFRAME_ALIGN_SZ);
+	/* precvpriv->precv_frame_buf = precvpriv->pallocated_frame_buf + RXFRAME_ALIGN_SZ - */
+	/*						((SIZE_PTR) (precvpriv->pallocated_frame_buf) &(RXFRAME_ALIGN_SZ-1)); */
+
+	precvframe = (union recv_frame *) precvpriv->precv_frame_buf;
+
+
+	for (i = 0; i < NR_RECVFRAME ; i++) {
+		_rtw_init_listhead(&(precvframe->u.list));
+
+		rtw_list_insert_tail(&(precvframe->u.list), &(precvpriv->free_recv_queue.queue));
+
+		res = rtw_os_recv_resource_alloc(padapter, precvframe);
+
+		precvframe->u.hdr.len = 0;
+
+		precvframe->u.hdr.adapter = padapter;
+		precvframe++;
+
+	}
+
+#ifdef CONFIG_USB_HCI
+
+	ATOMIC_SET(&(precvpriv->rx_pending_cnt), 1);
+
+	_rtw_init_sema(&precvpriv->allrxreturnevt, 0);
+
+#endif
+
+	res = rtw_hal_init_recv_priv(padapter);
+
+#ifdef CONFIG_NEW_SIGNAL_STAT_PROCESS
+	rtw_init_timer(&precvpriv->signal_stat_timer, padapter, rtw_signal_stat_timer_hdl, padapter);
+
+	precvpriv->signal_stat_sampling_interval = 2000; /* ms */
+	/* precvpriv->signal_stat_converging_constant = 5000; */ /* ms */
+
+	rtw_set_signal_stat_timer(precvpriv);
+#endif /* CONFIG_NEW_SIGNAL_STAT_PROCESS */
+
+exit:
+
+
+	return res;
+
+}
+
+void rtw_mfree_recv_priv_lock(struct recv_priv *precvpriv);
+void rtw_mfree_recv_priv_lock(struct recv_priv *precvpriv)
+{
+	_rtw_spinlock_free(&precvpriv->lock);
+#ifdef CONFIG_RECV_THREAD_MODE
+	_rtw_free_sema(&precvpriv->recv_sema);
+#endif
+
+	_rtw_spinlock_free(&precvpriv->free_recv_queue.lock);
+	_rtw_spinlock_free(&precvpriv->recv_pending_queue.lock);
+
+	_rtw_spinlock_free(&precvpriv->free_recv_buf_queue.lock);
+
+#ifdef CONFIG_USE_USB_BUFFER_ALLOC_RX
+	_rtw_spinlock_free(&precvpriv->recv_buf_pending_queue.lock);
+#endif /* CONFIG_USE_USB_BUFFER_ALLOC_RX */
+}
+
+void _rtw_free_recv_priv(struct recv_priv *precvpriv)
+{
+	_adapter	*padapter = precvpriv->adapter;
+
+
+	rtw_free_uc_swdec_pending_queue(padapter);
+
+	rtw_mfree_recv_priv_lock(precvpriv);
+
+	rtw_os_recv_resource_free(precvpriv);
+
+	if (precvpriv->pallocated_frame_buf)
+		rtw_vmfree(precvpriv->pallocated_frame_buf, NR_RECVFRAME * sizeof(union recv_frame) + RXFRAME_ALIGN_SZ);
+
+	rtw_hal_free_recv_priv(padapter);
+
+
+}
+
+bool rtw_rframe_del_wfd_ie(union recv_frame *rframe, u8 ies_offset)
+{
+#define DBG_RFRAME_DEL_WFD_IE 0
+	u8 *ies = rframe->u.hdr.rx_data + sizeof(struct rtw_ieee80211_hdr_3addr) + ies_offset;
+	uint ies_len_ori = rframe->u.hdr.len - (ies - rframe->u.hdr.rx_data);
+	uint ies_len;
+
+	ies_len = rtw_del_wfd_ie(ies, ies_len_ori, DBG_RFRAME_DEL_WFD_IE ? __func__ : NULL);
+	rframe->u.hdr.len -= ies_len_ori - ies_len;
+
+	return ies_len_ori != ies_len;
+}
+
+union recv_frame *_rtw_alloc_recvframe(_queue *pfree_recv_queue)
+{
+
+	union recv_frame  *precvframe;
+	_list	*plist, *phead;
+	_adapter *padapter;
+	struct recv_priv *precvpriv;
+
+	if (_rtw_queue_empty(pfree_recv_queue) == _TRUE)
+		precvframe = NULL;
+	else {
+		phead = get_list_head(pfree_recv_queue);
+
+		plist = get_next(phead);
+
+		precvframe = LIST_CONTAINOR(plist, union recv_frame, u);
+
+		rtw_list_delete(&precvframe->u.hdr.list);
+		padapter = precvframe->u.hdr.adapter;
+		if (padapter != NULL) {
+			precvpriv = &padapter->recvpriv;
+			if (pfree_recv_queue == &precvpriv->free_recv_queue)
+				precvpriv->free_recvframe_cnt--;
+		}
+	}
+
+
+	return precvframe;
+
+}
+
+union recv_frame *rtw_alloc_recvframe(_queue *pfree_recv_queue)
+{
+	_irqL irqL;
+	union recv_frame  *precvframe;
+
+	_enter_critical_bh(&pfree_recv_queue->lock, &irqL);
+
+	precvframe = _rtw_alloc_recvframe(pfree_recv_queue);
+
+	_exit_critical_bh(&pfree_recv_queue->lock, &irqL);
+
+	return precvframe;
+}
+
+void rtw_init_recvframe(union recv_frame *precvframe, struct recv_priv *precvpriv)
+{
+	/* Perry: This can be removed */
+	_rtw_init_listhead(&precvframe->u.hdr.list);
+
+	precvframe->u.hdr.len = 0;
+}
+
+int rtw_free_recvframe(union recv_frame *precvframe, _queue *pfree_recv_queue)
+{
+	_irqL irqL;
+	_adapter *padapter = precvframe->u.hdr.adapter;
+	struct recv_priv *precvpriv = &padapter->recvpriv;
+
+
+#ifdef CONFIG_CONCURRENT_MODE
+	padapter = GET_PRIMARY_ADAPTER(padapter);
+	precvpriv = &padapter->recvpriv;
+	pfree_recv_queue = &precvpriv->free_recv_queue;
+	precvframe->u.hdr.adapter = padapter;
+#endif
+
+
+	rtw_os_free_recvframe(precvframe);
+
+
+	_enter_critical_bh(&pfree_recv_queue->lock, &irqL);
+
+	rtw_list_delete(&(precvframe->u.hdr.list));
+
+	precvframe->u.hdr.len = 0;
+
+	rtw_list_insert_tail(&(precvframe->u.hdr.list), get_list_head(pfree_recv_queue));
+
+	if (padapter != NULL) {
+		if (pfree_recv_queue == &precvpriv->free_recv_queue)
+			precvpriv->free_recvframe_cnt++;
+	}
+
+	_exit_critical_bh(&pfree_recv_queue->lock, &irqL);
+
+
+	return _SUCCESS;
+
+}
+
+
+
+
+sint _rtw_enqueue_recvframe(union recv_frame *precvframe, _queue *queue)
+{
+
+	_adapter *padapter = precvframe->u.hdr.adapter;
+	struct recv_priv *precvpriv = &padapter->recvpriv;
+
+
+	/* _rtw_init_listhead(&(precvframe->u.hdr.list)); */
+	rtw_list_delete(&(precvframe->u.hdr.list));
+
+
+	rtw_list_insert_tail(&(precvframe->u.hdr.list), get_list_head(queue));
+
+	if (padapter != NULL) {
+		if (queue == &precvpriv->free_recv_queue)
+			precvpriv->free_recvframe_cnt++;
+	}
+
+
+	return _SUCCESS;
+}
+
+sint rtw_enqueue_recvframe(union recv_frame *precvframe, _queue *queue)
+{
+	sint ret;
+	_irqL irqL;
+
+	/* _spinlock(&pfree_recv_queue->lock); */
+	_enter_critical_bh(&queue->lock, &irqL);
+	ret = _rtw_enqueue_recvframe(precvframe, queue);
+	/* _rtw_spinunlock(&pfree_recv_queue->lock); */
+	_exit_critical_bh(&queue->lock, &irqL);
+
+	return ret;
+}
+
+/*
+sint	rtw_enqueue_recvframe(union recv_frame *precvframe, _queue *queue)
+{
+	return rtw_free_recvframe(precvframe, queue);
+}
+*/
+
+
+
+
+/*
+caller : defrag ; recvframe_chk_defrag in recv_thread  (passive)
+pframequeue: defrag_queue : will be accessed in recv_thread  (passive)
+
+using spinlock to protect
+
+*/
+
+void rtw_free_recvframe_queue(_queue *pframequeue,  _queue *pfree_recv_queue)
+{
+	union	recv_frame	*precvframe;
+	_list	*plist, *phead;
+
+	_rtw_spinlock(&pframequeue->lock);
+
+	phead = get_list_head(pframequeue);
+	plist = get_next(phead);
+
+	while (rtw_end_of_queue_search(phead, plist) == _FALSE) {
+		precvframe = LIST_CONTAINOR(plist, union recv_frame, u);
+
+		plist = get_next(plist);
+
+		/* rtw_list_delete(&precvframe->u.hdr.list); */ /* will do this in rtw_free_recvframe() */
+
+		rtw_free_recvframe(precvframe, pfree_recv_queue);
+	}
+
+	_rtw_spinunlock(&pframequeue->lock);
+
+
+}
+
+u32 rtw_free_uc_swdec_pending_queue(_adapter *adapter)
+{
+	u32 cnt = 0;
+	union recv_frame *pending_frame;
+	while ((pending_frame = rtw_alloc_recvframe(&adapter->recvpriv.uc_swdec_pending_queue))) {
+		rtw_free_recvframe(pending_frame, &adapter->recvpriv.free_recv_queue);
+		cnt++;
+	}
+
+	if (cnt)
+		RTW_INFO(FUNC_ADPT_FMT" dequeue %d\n", FUNC_ADPT_ARG(adapter), cnt);
+
+	return cnt;
+}
+
+
+sint rtw_enqueue_recvbuf_to_head(struct recv_buf *precvbuf, _queue *queue)
+{
+	_irqL irqL;
+
+	_enter_critical_bh(&queue->lock, &irqL);
+
+	rtw_list_delete(&precvbuf->list);
+	rtw_list_insert_head(&precvbuf->list, get_list_head(queue));
+
+	_exit_critical_bh(&queue->lock, &irqL);
+
+	return _SUCCESS;
+}
+
+sint rtw_enqueue_recvbuf(struct recv_buf *precvbuf, _queue *queue)
+{
+	_irqL irqL;
+#ifdef CONFIG_SDIO_HCI
+	_enter_critical_bh(&queue->lock, &irqL);
+#else
+	_enter_critical_ex(&queue->lock, &irqL);
+#endif/*#ifdef CONFIG_SDIO_HCI*/
+
+	rtw_list_delete(&precvbuf->list);
+
+	rtw_list_insert_tail(&precvbuf->list, get_list_head(queue));
+#ifdef CONFIG_SDIO_HCI
+	_exit_critical_bh(&queue->lock, &irqL);
+#else
+	_exit_critical_ex(&queue->lock, &irqL);
+#endif/*#ifdef CONFIG_SDIO_HCI*/
+	return _SUCCESS;
+
+}
+
+struct recv_buf *rtw_dequeue_recvbuf(_queue *queue)
+{
+	_irqL irqL;
+	struct recv_buf *precvbuf;
+	_list	*plist, *phead;
+
+#ifdef CONFIG_SDIO_HCI
+	_enter_critical_bh(&queue->lock, &irqL);
+#else
+	_enter_critical_ex(&queue->lock, &irqL);
+#endif/*#ifdef CONFIG_SDIO_HCI*/
+
+	if (_rtw_queue_empty(queue) == _TRUE)
+		precvbuf = NULL;
+	else {
+		phead = get_list_head(queue);
+
+		plist = get_next(phead);
+
+		precvbuf = LIST_CONTAINOR(plist, struct recv_buf, list);
+
+		rtw_list_delete(&precvbuf->list);
+
+	}
+
+#ifdef CONFIG_SDIO_HCI
+	_exit_critical_bh(&queue->lock, &irqL);
+#else
+	_exit_critical_ex(&queue->lock, &irqL);
+#endif/*#ifdef CONFIG_SDIO_HCI*/
+
+	return precvbuf;
+
+}
+
+sint recvframe_chkmic(_adapter *adapter,  union recv_frame *precvframe);
+sint recvframe_chkmic(_adapter *adapter,  union recv_frame *precvframe)
+{
+
+	sint	i, res = _SUCCESS;
+	u32	datalen;
+	u8	miccode[8];
+	u8	bmic_err = _FALSE, brpt_micerror = _TRUE;
+	u8	*pframe, *payload, *pframemic;
+	u8	*mickey;
+	/* u8	*iv,rxdata_key_idx=0; */
+	struct	sta_info		*stainfo;
+	struct	rx_pkt_attrib	*prxattrib = &precvframe->u.hdr.attrib;
+	struct	security_priv	*psecuritypriv = &adapter->securitypriv;
+
+	struct mlme_ext_priv	*pmlmeext = &adapter->mlmeextpriv;
+	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
+
+	stainfo = rtw_get_stainfo(&adapter->stapriv , &prxattrib->ta[0]);
+
+	if (prxattrib->encrypt == _TKIP_) {
+
+		/* calculate mic code */
+		if (stainfo != NULL) {
+			if (IS_MCAST(prxattrib->ra)) {
+				/* mickey=&psecuritypriv->dot118021XGrprxmickey.skey[0]; */
+				/* iv = precvframe->u.hdr.rx_data+prxattrib->hdrlen; */
+				/* rxdata_key_idx =( ((iv[3])>>6)&0x3) ; */
+				mickey = &psecuritypriv->dot118021XGrprxmickey[prxattrib->key_index].skey[0];
+
+				/* RTW_INFO("\n recvframe_chkmic: bcmc key psecuritypriv->dot118021XGrpKeyid(%d),pmlmeinfo->key_index(%d) ,recv key_id(%d)\n", */
+				/*								psecuritypriv->dot118021XGrpKeyid,pmlmeinfo->key_index,rxdata_key_idx); */
+
+				if (psecuritypriv->binstallGrpkey == _FALSE) {
+					res = _FAIL;
+					RTW_INFO("\n recvframe_chkmic:didn't install group key!!!!!!!!!!\n");
+					goto exit;
+				}
+			} else {
+				mickey = &stainfo->dot11tkiprxmickey.skey[0];
+			}
+
+			datalen = precvframe->u.hdr.len - prxattrib->hdrlen - prxattrib->iv_len - prxattrib->icv_len - 8; /* icv_len included the mic code */
+			pframe = precvframe->u.hdr.rx_data;
+			payload = pframe + prxattrib->hdrlen + prxattrib->iv_len;
+
+
+			/* rtw_seccalctkipmic(&stainfo->dot11tkiprxmickey.skey[0],pframe,payload, datalen ,&miccode[0],(unsigned char)prxattrib->priority); */ /* care the length of the data */
+
+			rtw_seccalctkipmic(mickey, pframe, payload, datalen , &miccode[0], (unsigned char)prxattrib->priority); /* care the length of the data */
+
+			pframemic = payload + datalen;
+
+			bmic_err = _FALSE;
+
+			for (i = 0; i < 8; i++) {
+				if (miccode[i] != *(pframemic + i)) {
+					bmic_err = _TRUE;
+				}
+			}
+
+
+			if (bmic_err == _TRUE) {
+
+
+
+				/* double check key_index for some timing issue , */
+				/* cannot compare with psecuritypriv->dot118021XGrpKeyid also cause timing issue */
+				if ((IS_MCAST(prxattrib->ra) == _TRUE)  && (prxattrib->key_index != pmlmeinfo->key_index))
+					brpt_micerror = _FALSE;
+
+				if ((prxattrib->bdecrypted == _TRUE) && (brpt_micerror == _TRUE)) {
+					rtw_handle_tkip_mic_err(adapter, stainfo, (u8)IS_MCAST(prxattrib->ra));
+					RTW_INFO(" mic error :prxattrib->bdecrypted=%d\n", prxattrib->bdecrypted);
+				} else {
+					RTW_INFO(" mic error :prxattrib->bdecrypted=%d\n", prxattrib->bdecrypted);
+				}
+
+				res = _FAIL;
+
+			} else {
+				/* mic checked ok */
+				if ((psecuritypriv->bcheck_grpkey == _FALSE) && (IS_MCAST(prxattrib->ra) == _TRUE)) {
+					psecuritypriv->bcheck_grpkey = _TRUE;
+				}
+			}
+
+		}
+
+		recvframe_pull_tail(precvframe, 8);
+
+	}
+
+exit:
+
+
+	return res;
+
+}
+
+/*#define DBG_RX_SW_DECRYPTOR*/
+
+/* decrypt and set the ivlen,icvlen of the recv_frame */
+union recv_frame *decryptor(_adapter *padapter, union recv_frame *precv_frame);
+union recv_frame *decryptor(_adapter *padapter, union recv_frame *precv_frame)
+{
+
+	struct rx_pkt_attrib *prxattrib = &precv_frame->u.hdr.attrib;
+	struct security_priv *psecuritypriv = &padapter->securitypriv;
+	union recv_frame *return_packet = precv_frame;
+	u32	 res = _SUCCESS;
+
+
+	DBG_COUNTER(padapter->rx_logs.core_rx_post_decrypt);
+
+
+	if (prxattrib->encrypt > 0) {
+		u8 *iv = precv_frame->u.hdr.rx_data + prxattrib->hdrlen;
+		prxattrib->key_index = (((iv[3]) >> 6) & 0x3) ;
+
+		if (prxattrib->key_index > WEP_KEYS) {
+			RTW_INFO("prxattrib->key_index(%d) > WEP_KEYS\n", prxattrib->key_index);
+
+			switch (prxattrib->encrypt) {
+			case _WEP40_:
+			case _WEP104_:
+				prxattrib->key_index = psecuritypriv->dot11PrivacyKeyIndex;
+				break;
+			case _TKIP_:
+			case _AES_:
+			default:
+				prxattrib->key_index = psecuritypriv->dot118021XGrpKeyid;
+				break;
+			}
+		}
+	}
+
+	if (prxattrib->encrypt && !prxattrib->bdecrypted) {
+		if (GetFrameType(get_recvframe_data(precv_frame)) == WIFI_DATA
+			#ifdef CONFIG_CONCURRENT_MODE
+			&& !IS_MCAST(prxattrib->ra) /* bc/mc packets may use sw decryption for concurrent mode */
+			#endif
+		)
+			psecuritypriv->hw_decrypted = _FALSE;
+
+#ifdef DBG_RX_SW_DECRYPTOR
+		RTW_INFO(ADPT_FMT" - sec_type:%s DO SW decryption\n",
+			ADPT_ARG(padapter), security_type_str(prxattrib->encrypt));
+#endif
+
+#ifdef DBG_RX_DECRYPTOR
+		RTW_INFO("[%s] %d:prxstat->bdecrypted:%d,  prxattrib->encrypt:%d,  Setting psecuritypriv->hw_decrypted = %d\n",
+			 __FUNCTION__,
+			 __LINE__,
+			 prxattrib->bdecrypted,
+			 prxattrib->encrypt,
+			 psecuritypriv->hw_decrypted);
+#endif
+
+		switch (prxattrib->encrypt) {
+		case _WEP40_:
+		case _WEP104_:
+			DBG_COUNTER(padapter->rx_logs.core_rx_post_decrypt_wep);
+			rtw_wep_decrypt(padapter, (u8 *)precv_frame);
+			break;
+		case _TKIP_:
+			DBG_COUNTER(padapter->rx_logs.core_rx_post_decrypt_tkip);
+			res = rtw_tkip_decrypt(padapter, (u8 *)precv_frame);
+			break;
+		case _AES_:
+			DBG_COUNTER(padapter->rx_logs.core_rx_post_decrypt_aes);
+			res = rtw_aes_decrypt(padapter, (u8 *)precv_frame);
+			break;
+#ifdef CONFIG_WAPI_SUPPORT
+		case _SMS4_:
+			DBG_COUNTER(padapter->rx_logs.core_rx_post_decrypt_wapi);
+			rtw_sms4_decrypt(padapter, (u8 *)precv_frame);
+			break;
+#endif
+		default:
+			break;
+		}
+	} else if (prxattrib->bdecrypted == 1
+		   && prxattrib->encrypt > 0
+		&& (psecuritypriv->busetkipkey == 1 || prxattrib->encrypt != _TKIP_)
+		  ) {
+#if 0
+		if ((prxstat->icv == 1) && (prxattrib->encrypt != _AES_)) {
+			psecuritypriv->hw_decrypted = _FALSE;
+
+
+			rtw_free_recvframe(precv_frame, &padapter->recvpriv.free_recv_queue);
+
+			return_packet = NULL;
+
+		} else
+#endif
+		{
+			DBG_COUNTER(padapter->rx_logs.core_rx_post_decrypt_hw);
+
+			psecuritypriv->hw_decrypted = _TRUE;
+#ifdef DBG_RX_DECRYPTOR
+			RTW_INFO("[%s] %d:prxstat->bdecrypted:%d,  prxattrib->encrypt:%d,  Setting psecuritypriv->hw_decrypted = %d\n",
+				 __FUNCTION__,
+				 __LINE__,
+				 prxattrib->bdecrypted,
+				 prxattrib->encrypt,
+				 psecuritypriv->hw_decrypted);
+
+#endif
+		}
+	} else {
+		DBG_COUNTER(padapter->rx_logs.core_rx_post_decrypt_unknown);
+#ifdef DBG_RX_DECRYPTOR
+		RTW_INFO("[%s] %d:prxstat->bdecrypted:%d,  prxattrib->encrypt:%d,  Setting psecuritypriv->hw_decrypted = %d\n",
+			 __FUNCTION__,
+			 __LINE__,
+			 prxattrib->bdecrypted,
+			 prxattrib->encrypt,
+			 psecuritypriv->hw_decrypted);
+#endif
+	}
+
+	#ifdef CONFIG_RTW_MESH
+	if (res != _FAIL
+		&& !prxattrib->amsdu
+		&& prxattrib->mesh_ctrl_present)
+		res = rtw_mesh_rx_validate_mctrl_non_amsdu(padapter, precv_frame);
+	#endif
+
+	if (res == _FAIL) {
+		rtw_free_recvframe(return_packet, &padapter->recvpriv.free_recv_queue);
+		return_packet = NULL;
+	} else
+		prxattrib->bdecrypted = _TRUE;
+	/* recvframe_chkmic(adapter, precv_frame);   */ /* move to recvframme_defrag function */
+
+
+	return return_packet;
+
+}
+/* ###set the security information in the recv_frame */
+union recv_frame *portctrl(_adapter *adapter, union recv_frame *precv_frame);
+union recv_frame *portctrl(_adapter *adapter, union recv_frame *precv_frame)
+{
+	u8 *psta_addr = NULL;
+	u8 *ptr;
+	uint  auth_alg;
+	struct recv_frame_hdr *pfhdr;
+	struct sta_info *psta;
+	struct sta_priv *pstapriv ;
+	union recv_frame *prtnframe;
+	u16	ether_type = 0;
+	u16  eapol_type = 0x888e;/* for Funia BD's WPA issue  */
+	struct rx_pkt_attrib *pattrib;
+
+
+	pstapriv = &adapter->stapriv;
+
+	auth_alg = adapter->securitypriv.dot11AuthAlgrthm;
+
+	ptr = get_recvframe_data(precv_frame);
+	pfhdr = &precv_frame->u.hdr;
+	pattrib = &pfhdr->attrib;
+	psta_addr = pattrib->ta;
+
+	prtnframe = NULL;
+
+	psta = rtw_get_stainfo(pstapriv, psta_addr);
+
+
+	if (auth_alg == dot11AuthAlgrthm_8021X) {
+		if ((psta != NULL) && (psta->ieee8021x_blocked)) {
+			/* blocked */
+			/* only accept EAPOL frame */
+
+			prtnframe = precv_frame;
+
+			/* get ether_type */
+			ptr = ptr + pfhdr->attrib.hdrlen + pfhdr->attrib.iv_len + LLC_HEADER_SIZE;
+			_rtw_memcpy(&ether_type, ptr, 2);
+			ether_type = ntohs((unsigned short)ether_type);
+
+			if (ether_type == eapol_type)
+				prtnframe = precv_frame;
+			else {
+				/* free this frame */
+				rtw_free_recvframe(precv_frame, &adapter->recvpriv.free_recv_queue);
+				prtnframe = NULL;
+			}
+		} else {
+			/* allowed */
+			/* check decryption status, and decrypt the frame if needed */
+
+
+			prtnframe = precv_frame;
+			/* check is the EAPOL frame or not (Rekey) */
+			/* if(ether_type == eapol_type){ */
+			/* check Rekey */
+
+			/*	prtnframe=precv_frame; */
+			/* } */
+		}
+	} else
+		prtnframe = precv_frame;
+
+
+	return prtnframe;
+
+}
+
+/* VALID_PN_CHK
+ * Return true when PN is legal, otherwise false.
+ * Legal PN:
+ *	1. If old PN is 0, any PN is legal
+ *	2. PN > old PN
+ */
+#define PN_LESS_CHK(a, b)	(((a-b) & 0x800000000000) != 0)
+#define VALID_PN_CHK(new, old)	(((old) == 0) || PN_LESS_CHK(old, new))
+#define CCMPH_2_KEYID(ch)	(((ch) & 0x00000000c0000000) >> 30)
+sint recv_ucast_pn_decache(union recv_frame *precv_frame);
+sint recv_ucast_pn_decache(union recv_frame *precv_frame)
+{
+	struct rx_pkt_attrib *pattrib = &precv_frame->u.hdr.attrib;
+	struct sta_info *sta = precv_frame->u.hdr.psta;
+	struct stainfo_rxcache *prxcache = &sta->sta_recvpriv.rxcache;
+	u8 *pdata = precv_frame->u.hdr.rx_data;
+	sint tid = precv_frame->u.hdr.attrib.priority;
+	u64 tmp_iv_hdr = 0;
+	u64 curr_pn = 0, pkt_pn = 0;
+
+	if (tid > 15)
+		return _FAIL;
+
+	if (pattrib->encrypt == _AES_) {
+		tmp_iv_hdr = le64_to_cpu(*(u64*)(pdata + pattrib->hdrlen));
+		pkt_pn = CCMPH_2_PN(tmp_iv_hdr);
+		tmp_iv_hdr = le64_to_cpu(*(u64*)prxcache->iv[tid]);
+		curr_pn = CCMPH_2_PN(tmp_iv_hdr);
+
+		if (!VALID_PN_CHK(pkt_pn, curr_pn)) {
+			/* return _FAIL; */
+		} else {
+			prxcache->last_tid = tid;
+			_rtw_memcpy(prxcache->iv[tid],
+				    (pdata + pattrib->hdrlen),
+				    sizeof(prxcache->iv[tid]));
+		}
+	}
+
+	return _SUCCESS;
+}
+
+sint recv_bcast_pn_decache(union recv_frame *precv_frame);
+sint recv_bcast_pn_decache(union recv_frame *precv_frame)
+{
+	_adapter *padapter = precv_frame->u.hdr.adapter;
+	struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
+	struct security_priv *psecuritypriv = &padapter->securitypriv;
+	struct rx_pkt_attrib *pattrib = &precv_frame->u.hdr.attrib;
+	u8 *pdata = precv_frame->u.hdr.rx_data;
+	u64 tmp_iv_hdr = 0;
+	u64 curr_pn = 0, pkt_pn = 0;
+	u8 key_id;
+
+	if ((pattrib->encrypt == _AES_) &&
+		(check_fwstate(pmlmepriv, WIFI_STATION_STATE) == _TRUE)) {
+
+		tmp_iv_hdr = le64_to_cpu(*(u64*)(pdata + pattrib->hdrlen));
+		key_id = CCMPH_2_KEYID(tmp_iv_hdr);
+		pkt_pn = CCMPH_2_PN(tmp_iv_hdr);
+
+		curr_pn = le64_to_cpu(*(u64*)psecuritypriv->iv_seq[key_id]);
+		curr_pn &= 0x0000ffffffffffff;
+
+		if (!VALID_PN_CHK(pkt_pn, curr_pn))
+			return _FAIL;
+
+		*(u64*)psecuritypriv->iv_seq[key_id] = cpu_to_le64(pkt_pn);
+	}
+
+	return _SUCCESS;
+}
+
+sint recv_decache(union recv_frame *precv_frame)
+{
+	struct sta_info *psta = precv_frame->u.hdr.psta;
+	struct rx_pkt_attrib *pattrib = &precv_frame->u.hdr.attrib;
+	_adapter *adapter = psta->padapter;
+	sint tid = pattrib->priority;
+	u16 seq_ctrl = ((precv_frame->u.hdr.attrib.seq_num & 0xffff) << 4) |
+		       (precv_frame->u.hdr.attrib.frag_num & 0xf);
+	u16 *prxseq;
+
+	if (tid > 15)
+		return _FAIL;
+
+	if (pattrib->qos) {
+		if (IS_MCAST(pattrib->ra))
+			prxseq = &psta->sta_recvpriv.bmc_tid_rxseq[tid];
+		else
+			prxseq = &psta->sta_recvpriv.rxcache.tid_rxseq[tid];
+	} else {
+		if (IS_MCAST(pattrib->ra)) {
+			prxseq = &psta->sta_recvpriv.nonqos_bmc_rxseq;
+			#ifdef DBG_RX_SEQ
+			RTW_INFO("DBG_RX_SEQ "FUNC_ADPT_FMT" nonqos bmc seq_num:%d\n"
+				, FUNC_ADPT_ARG(adapter), pattrib->seq_num);
+			#endif
+
+		} else {
+			prxseq = &psta->sta_recvpriv.nonqos_rxseq;
+			#ifdef DBG_RX_SEQ
+			RTW_INFO("DBG_RX_SEQ "FUNC_ADPT_FMT" nonqos seq_num:%d\n"
+				, FUNC_ADPT_ARG(adapter), pattrib->seq_num);
+			#endif
+		}
+	}
+
+	if (seq_ctrl == *prxseq) {
+		/* for non-AMPDU case	*/
+		psta->sta_stats.duplicate_cnt++;
+
+		if (psta->sta_stats.duplicate_cnt % 100 == 0)
+			RTW_INFO("%s: tid=%u seq=%d frag=%d\n", __func__
+				, tid, precv_frame->u.hdr.attrib.seq_num
+				, precv_frame->u.hdr.attrib.frag_num);
+
+		#ifdef DBG_RX_DROP_FRAME
+		RTW_INFO("DBG_RX_DROP_FRAME "FUNC_ADPT_FMT" recv_decache _FAIL for sta="MAC_FMT"\n"
+			, FUNC_ADPT_ARG(adapter), MAC_ARG(psta->cmn.mac_addr));
+		#endif
+		return _FAIL;
+	}
+	*prxseq = seq_ctrl;
+
+	return _SUCCESS;
+}
+
+void process_pwrbit_data(_adapter *padapter, union recv_frame *precv_frame, struct sta_info *psta)
+{
+#ifdef CONFIG_AP_MODE
+	unsigned char pwrbit;
+	u8 *ptr = precv_frame->u.hdr.rx_data;
+
+	pwrbit = GetPwrMgt(ptr);
+
+	if (pwrbit) {
+		if (!(psta->state & WIFI_SLEEP_STATE)) {
+			/* psta->state |= WIFI_SLEEP_STATE; */
+			/* rtw_tim_map_set(padapter, pstapriv->sta_dz_bitmap, BIT(psta->cmn.aid)); */
+
+			stop_sta_xmit(padapter, psta);
+			/* RTW_INFO_DUMP("to sleep, sta_dz_bitmap=", pstapriv->sta_dz_bitmap, pstapriv->aid_bmp_len); */
+		}
+	} else {
+		if (psta->state & WIFI_SLEEP_STATE) {
+			/* psta->state ^= WIFI_SLEEP_STATE; */
+			/* rtw_tim_map_clear(padapter, pstapriv->sta_dz_bitmap, BIT(psta->cmn.aid)); */
+
+			wakeup_sta_to_xmit(padapter, psta);
+			/* RTW_INFO_DUMP("to wakeup, sta_dz_bitmap=", pstapriv->sta_dz_bitmap, pstapriv->aid_bmp_len); */
+		}
+	}
+#endif
+}
+
+void process_wmmps_data(_adapter *padapter, union recv_frame *precv_frame, struct sta_info *psta)
+{
+#ifdef CONFIG_AP_MODE
+	struct rx_pkt_attrib *pattrib = &precv_frame->u.hdr.attrib;
+
+#ifdef CONFIG_TDLS
+	if (!(psta->tdls_sta_state & TDLS_LINKED_STATE)) {
+#endif /* CONFIG_TDLS */
+
+		if (!psta->qos_option)
+			return;
+
+		if (!(psta->qos_info & 0xf))
+			return;
+
+#ifdef CONFIG_TDLS
+	}
+#endif /* CONFIG_TDLS		 */
+
+	if (psta->state & WIFI_SLEEP_STATE) {
+		u8 wmmps_ac = 0;
+
+		switch (pattrib->priority) {
+		case 1:
+		case 2:
+			wmmps_ac = psta->uapsd_bk & BIT(1);
+			break;
+		case 4:
+		case 5:
+			wmmps_ac = psta->uapsd_vi & BIT(1);
+			break;
+		case 6:
+		case 7:
+			wmmps_ac = psta->uapsd_vo & BIT(1);
+			break;
+		case 0:
+		case 3:
+		default:
+			wmmps_ac = psta->uapsd_be & BIT(1);
+			break;
+		}
+
+		if (wmmps_ac) {
+			if (psta->sleepq_ac_len > 0) {
+				/* process received triggered frame */
+				xmit_delivery_enabled_frames(padapter, psta);
+			} else {
+				/* issue one qos null frame with More data bit = 0 and the EOSP bit set (=1) */
+				issue_qos_nulldata(padapter, psta->cmn.mac_addr, (u16)pattrib->priority, 0, 0, 0);
+			}
+		}
+
+	}
+
+
+#endif
+
+}
+
+#ifdef CONFIG_TDLS
+sint OnTDLS(_adapter *adapter, union recv_frame *precv_frame)
+{
+	struct rx_pkt_attrib	*pattrib = &precv_frame->u.hdr.attrib;
+	sint ret = _SUCCESS;
+	u8 *paction = get_recvframe_data(precv_frame);
+	u8 category_field = 1;
+#ifdef CONFIG_WFD
+	u8 WFA_OUI[3] = { 0x50, 0x6f, 0x9a };
+#endif /* CONFIG_WFD */
+	struct tdls_info *ptdlsinfo = &(adapter->tdlsinfo);
+	u8 *ptr = precv_frame->u.hdr.rx_data;
+	struct sta_priv *pstapriv = &(adapter->stapriv);
+	struct sta_info *ptdls_sta = NULL;
+
+	/* point to action field */
+	paction += pattrib->hdrlen
+		   + pattrib->iv_len
+		   + SNAP_SIZE
+		   + ETH_TYPE_LEN
+		   + PAYLOAD_TYPE_LEN
+		   + category_field;
+
+	RTW_INFO("[TDLS] Recv %s from "MAC_FMT" with SeqNum = %d\n", rtw_tdls_action_txt(*paction), MAC_ARG(pattrib->src), GetSequence(get_recvframe_data(precv_frame)));
+
+	if (hal_chk_wl_func(adapter, WL_FUNC_TDLS) == _FALSE) {
+		RTW_INFO("Ignore tdls frame since hal doesn't support tdls\n");
+		ret = _FAIL;
+		return ret;
+	}
+
+	if (rtw_is_tdls_enabled(adapter) == _FALSE) {
+		RTW_INFO("recv tdls frame, "
+			 "but tdls haven't enabled\n");
+		ret = _FAIL;
+		return ret;
+	}
+
+	ptdls_sta = rtw_get_stainfo(pstapriv, get_sa(ptr));
+	if (ptdls_sta == NULL) {
+		switch (*paction) {
+		case TDLS_SETUP_REQUEST:
+		case TDLS_DISCOVERY_REQUEST:
+			break;
+		default:
+			RTW_INFO("[TDLS] %s - Direct Link Peer = "MAC_FMT" not found for action = %d\n", __func__, MAC_ARG(get_sa(ptr)), *paction);
+			ret = _FAIL;
+			goto exit;
+		}
+	}
+
+	switch (*paction) {
+	case TDLS_SETUP_REQUEST:
+		ret = On_TDLS_Setup_Req(adapter, precv_frame, ptdls_sta);
+		break;
+	case TDLS_SETUP_RESPONSE:
+		ret = On_TDLS_Setup_Rsp(adapter, precv_frame, ptdls_sta);
+		break;
+	case TDLS_SETUP_CONFIRM:
+		ret = On_TDLS_Setup_Cfm(adapter, precv_frame, ptdls_sta);
+		break;
+	case TDLS_TEARDOWN:
+		ret = On_TDLS_Teardown(adapter, precv_frame, ptdls_sta);
+		break;
+	case TDLS_DISCOVERY_REQUEST:
+		ret = On_TDLS_Dis_Req(adapter, precv_frame);
+		break;
+	case TDLS_PEER_TRAFFIC_INDICATION:
+		ret = On_TDLS_Peer_Traffic_Indication(adapter, precv_frame, ptdls_sta);
+		break;
+	case TDLS_PEER_TRAFFIC_RESPONSE:
+		ret = On_TDLS_Peer_Traffic_Rsp(adapter, precv_frame, ptdls_sta);
+		break;
+#ifdef CONFIG_TDLS_CH_SW
+	case TDLS_CHANNEL_SWITCH_REQUEST:
+		ret = On_TDLS_Ch_Switch_Req(adapter, precv_frame, ptdls_sta);
+		break;
+	case TDLS_CHANNEL_SWITCH_RESPONSE:
+		ret = On_TDLS_Ch_Switch_Rsp(adapter, precv_frame, ptdls_sta);
+		break;
+#endif
+#ifdef CONFIG_WFD
+	/* First byte of WFA OUI */
+	case 0x50:
+		if (_rtw_memcmp(WFA_OUI, paction, 3)) {
+			/* Probe request frame */
+			if (*(paction + 3) == 0x04) {
+				/* WFDTDLS: for sigma test, do not setup direct link automatically */
+				ptdlsinfo->dev_discovered = _TRUE;
+				RTW_INFO("recv tunneled probe request frame\n");
+				issue_tunneled_probe_rsp(adapter, precv_frame);
+			}
+			/* Probe response frame */
+			if (*(paction + 3) == 0x05) {
+				/* WFDTDLS: for sigma test, do not setup direct link automatically */
+				ptdlsinfo->dev_discovered = _TRUE;
+				RTW_INFO("recv tunneled probe response frame\n");
+			}
+		}
+		break;
+#endif /* CONFIG_WFD */
+	default:
+		RTW_INFO("receive TDLS frame %d but not support\n", *paction);
+		ret = _FAIL;
+		break;
+	}
+
+exit:
+	return ret;
+
+}
+#endif /* CONFIG_TDLS */
+
+void count_rx_stats(_adapter *padapter, union recv_frame *prframe, struct sta_info *sta)
+{
+	int	sz;
+	struct sta_info		*psta = NULL;
+	struct stainfo_stats	*pstats = NULL;
+	struct rx_pkt_attrib	*pattrib = &prframe->u.hdr.attrib;
+	struct recv_priv		*precvpriv = &padapter->recvpriv;
+
+	sz = get_recvframe_len(prframe);
+	precvpriv->rx_bytes += sz;
+
+	padapter->mlmepriv.LinkDetectInfo.NumRxOkInPeriod++;
+
+	if ((!MacAddr_isBcst(pattrib->dst)) && (!IS_MCAST(pattrib->dst)))
+		padapter->mlmepriv.LinkDetectInfo.NumRxUnicastOkInPeriod++;
+
+	if (sta)
+		psta = sta;
+	else
+		psta = prframe->u.hdr.psta;
+
+	if (psta) {
+		u8 is_ra_bmc = IS_MCAST(pattrib->ra);
+
+		pstats = &psta->sta_stats;
+
+		pstats->last_rx_time = rtw_get_current_time();
+		pstats->rx_data_pkts++;
+		pstats->rx_bytes += sz;
+		if (is_broadcast_mac_addr(pattrib->ra)) {
+			pstats->rx_data_bc_pkts++;
+			pstats->rx_bc_bytes += sz;
+		} else if (is_ra_bmc) {
+			pstats->rx_data_mc_pkts++;
+			pstats->rx_mc_bytes += sz;
+		}
+
+		if (!is_ra_bmc) {
+			pstats->rxratecnt[pattrib->data_rate]++;
+			/*record rx packets for every tid*/
+			pstats->rx_data_qos_pkts[pattrib->priority]++;
+		}
+#ifdef CONFIG_DYNAMIC_SOML
+		rtw_dyn_soml_byte_update(padapter, pattrib->data_rate, sz);
+#endif
+#if defined(CONFIG_CHECK_LEAVE_LPS) && defined(CONFIG_LPS_CHK_BY_TP)
+		if (adapter_to_pwrctl(padapter)->lps_chk_by_tp)
+			traffic_check_for_leave_lps_by_tp(padapter, _FALSE, psta);
+#endif /* CONFIG_LPS */
+
+	}
+
+#ifdef CONFIG_CHECK_LEAVE_LPS
+#ifdef CONFIG_LPS_CHK_BY_TP
+	if (!adapter_to_pwrctl(padapter)->lps_chk_by_tp)
+#endif
+		traffic_check_for_leave_lps(padapter, _FALSE, 0);
+#endif /* CONFIG_CHECK_LEAVE_LPS */
+
+}
+
+sint sta2sta_data_frame(
+	_adapter *adapter,
+	union recv_frame *precv_frame,
+	struct sta_info **psta
+)
+{
+	u8 *ptr = precv_frame->u.hdr.rx_data;
+	sint ret = _SUCCESS;
+	struct rx_pkt_attrib *pattrib = &precv_frame->u.hdr.attrib;
+	struct	sta_priv		*pstapriv = &adapter->stapriv;
+	struct	mlme_priv	*pmlmepriv = &adapter->mlmepriv;
+	u8 *mybssid  = get_bssid(pmlmepriv);
+	u8 *myhwaddr = adapter_mac_addr(adapter);
+	u8 *sta_addr = pattrib->ta;
+	sint bmcast = IS_MCAST(pattrib->dst);
+
+#ifdef CONFIG_TDLS
+	struct tdls_info *ptdlsinfo = &adapter->tdlsinfo;
+#ifdef CONFIG_TDLS_CH_SW
+	struct tdls_ch_switch *pchsw_info = &ptdlsinfo->chsw_info;
+#endif
+	struct sta_info *ptdls_sta = NULL;
+	u8 *psnap_type = ptr + pattrib->hdrlen + pattrib->iv_len + SNAP_SIZE;
+	/* frame body located after [+2]: ether-type, [+1]: payload type */
+	u8 *pframe_body = psnap_type + 2 + 1;
+#endif
+
+
+	/* RTW_INFO("[%s] %d, seqnum:%d\n", __FUNCTION__, __LINE__, pattrib->seq_num); */
+
+	if ((check_fwstate(pmlmepriv, WIFI_ADHOC_STATE) == _TRUE) ||
+	    (check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE) == _TRUE)) {
+
+		/* filter packets that SA is myself or multicast or broadcast */
+		if (_rtw_memcmp(myhwaddr, pattrib->src, ETH_ALEN)) {
+			ret = _FAIL;
+			goto exit;
+		}
+
+		if ((!_rtw_memcmp(myhwaddr, pattrib->dst, ETH_ALEN))	&& (!bmcast)) {
+			ret = _FAIL;
+			goto exit;
+		}
+
+		if (_rtw_memcmp(pattrib->bssid, "\x0\x0\x0\x0\x0\x0", ETH_ALEN) ||
+		    _rtw_memcmp(mybssid, "\x0\x0\x0\x0\x0\x0", ETH_ALEN) ||
+		    (!_rtw_memcmp(pattrib->bssid, mybssid, ETH_ALEN))) {
+			ret = _FAIL;
+			goto exit;
+		}
+
+	} else if (check_fwstate(pmlmepriv, WIFI_STATION_STATE) == _TRUE) {
+#ifdef CONFIG_TDLS
+
+		/* direct link data transfer */
+		if (ptdlsinfo->link_established == _TRUE) {
+			*psta = ptdls_sta = rtw_get_stainfo(pstapriv, pattrib->ta);
+			if (ptdls_sta == NULL) {
+				ret = _FAIL;
+				goto exit;
+			} else if (ptdls_sta->tdls_sta_state & TDLS_LINKED_STATE) {
+				/* filter packets that SA is myself or multicast or broadcast */
+				if (_rtw_memcmp(myhwaddr, pattrib->src, ETH_ALEN)) {
+					ret = _FAIL;
+					goto exit;
+				}
+				/* da should be for me */
+				if ((!_rtw_memcmp(myhwaddr, pattrib->dst, ETH_ALEN)) && (!bmcast)) {
+					ret = _FAIL;
+					goto exit;
+				}
+				/* check BSSID */
+				if (_rtw_memcmp(pattrib->bssid, "\x0\x0\x0\x0\x0\x0", ETH_ALEN) ||
+				    _rtw_memcmp(mybssid, "\x0\x0\x0\x0\x0\x0", ETH_ALEN) ||
+				    (!_rtw_memcmp(pattrib->bssid, mybssid, ETH_ALEN))) {
+					ret = _FAIL;
+					goto exit;
+				}
+
+#ifdef CONFIG_TDLS_CH_SW
+				if (ATOMIC_READ(&pchsw_info->chsw_on) == _TRUE) {
+					if (adapter->mlmeextpriv.cur_channel != rtw_get_oper_ch(adapter)) {
+						pchsw_info->ch_sw_state |= TDLS_PEER_AT_OFF_STATE;
+						if (!(pchsw_info->ch_sw_state & TDLS_CH_SW_INITIATOR_STATE))
+							_cancel_timer_ex(&ptdls_sta->ch_sw_timer);
+						/* On_TDLS_Peer_Traffic_Rsp(adapter, precv_frame); */
+					}
+				}
+#endif
+
+				/* process UAPSD tdls sta */
+				process_pwrbit_data(adapter, precv_frame, ptdls_sta);
+
+				/* if NULL-frame, check pwrbit */
+				if ((get_frame_sub_type(ptr) & WIFI_DATA_NULL) == WIFI_DATA_NULL) {
+					/* NULL-frame with pwrbit=1, buffer_STA should buffer frames for sleep_STA */
+					if (GetPwrMgt(ptr)) {
+						/* it would be triggered when we are off channel and receiving NULL DATA */
+						/* we can confirm that peer STA is at off channel */
+						RTW_INFO("TDLS: recv peer null frame with pwr bit 1\n");
+						/* ptdls_sta->tdls_sta_state|=TDLS_PEER_SLEEP_STATE; */
+					}
+
+					/* TODO: Updated BSSID's seq. */
+					/* RTW_INFO("drop Null Data\n"); */
+					ptdls_sta->tdls_sta_state &= ~(TDLS_WAIT_PTR_STATE);
+					ret = _FAIL;
+					goto exit;
+				}
+
+				/* receive some of all TDLS management frames, process it at ON_TDLS */
+				if (_rtw_memcmp(psnap_type, SNAP_ETH_TYPE_TDLS, 2)) {
+					ret = OnTDLS(adapter, precv_frame);
+					goto exit;
+				}
+
+				if ((get_frame_sub_type(ptr) & WIFI_QOS_DATA_TYPE) == WIFI_QOS_DATA_TYPE)
+					process_wmmps_data(adapter, precv_frame, ptdls_sta);
+
+				ptdls_sta->tdls_sta_state &= ~(TDLS_WAIT_PTR_STATE);
+
+			}
+		} else
+#endif /* CONFIG_TDLS */
+		{
+			/* For Station mode, sa and bssid should always be BSSID, and DA is my mac-address */
+			if (!_rtw_memcmp(pattrib->bssid, pattrib->src, ETH_ALEN)) {
+				ret = _FAIL;
+				goto exit;
+			}
+		}
+
+	} else if (check_fwstate(pmlmepriv, WIFI_AP_STATE) == _TRUE) {
+		if (bmcast) {
+			/* For AP mode, if DA == MCAST, then BSSID should be also MCAST */
+			if (!IS_MCAST(pattrib->bssid)) {
+				ret = _FAIL;
+				goto exit;
+			}
+		} else { /* not mc-frame */
+			/* For AP mode, if DA is non-MCAST, then it must be BSSID, and bssid == BSSID */
+			if (!_rtw_memcmp(pattrib->bssid, pattrib->dst, ETH_ALEN)) {
+				ret = _FAIL;
+				goto exit;
+			}
+		}
+
+	} else if (check_fwstate(pmlmepriv, WIFI_MP_STATE) == _TRUE) {
+		_rtw_memcpy(pattrib->dst, GetAddr1Ptr(ptr), ETH_ALEN);
+		_rtw_memcpy(pattrib->src, get_addr2_ptr(ptr), ETH_ALEN);
+		_rtw_memcpy(pattrib->bssid, GetAddr3Ptr(ptr), ETH_ALEN);
+		_rtw_memcpy(pattrib->ra, pattrib->dst, ETH_ALEN);
+		_rtw_memcpy(pattrib->ta, pattrib->src, ETH_ALEN);
+
+		sta_addr = mybssid;
+	} else
+		ret  = _FAIL;
+
+#ifdef CONFIG_TDLS
+	if (ptdls_sta == NULL)
+#endif
+		*psta = rtw_get_stainfo(pstapriv, sta_addr);
+
+	if (*psta == NULL) {
+#ifdef CONFIG_MP_INCLUDED
+		if (adapter->registrypriv.mp_mode == 1) {
+			if (check_fwstate(pmlmepriv, WIFI_MP_STATE) == _TRUE)
+				adapter->mppriv.rx_pktloss++;
+		}
+#endif
+		ret = _FAIL;
+		goto exit;
+	}
+
+exit:
+	return ret;
+
+}
+
+sint ap2sta_data_frame(
+	_adapter *adapter,
+	union recv_frame *precv_frame,
+	struct sta_info **psta)
+{
+	u8 *ptr = precv_frame->u.hdr.rx_data;
+	struct rx_pkt_attrib *pattrib = &precv_frame->u.hdr.attrib;
+	sint ret = _SUCCESS;
+	struct	sta_priv		*pstapriv = &adapter->stapriv;
+	struct	mlme_priv	*pmlmepriv = &adapter->mlmepriv;
+	u8 *mybssid  = get_bssid(pmlmepriv);
+	u8 *myhwaddr = adapter_mac_addr(adapter);
+	sint bmcast = IS_MCAST(pattrib->dst);
+
+
+	if ((check_fwstate(pmlmepriv, WIFI_STATION_STATE) == _TRUE)
+	    && (check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE
+		|| check_fwstate(pmlmepriv, _FW_UNDER_LINKING) == _TRUE)
+	   ) {
+
+		/* filter packets that SA is myself or multicast or broadcast */
+		if (_rtw_memcmp(myhwaddr, pattrib->src, ETH_ALEN)) {
+			#ifdef DBG_RX_DROP_FRAME
+			RTW_INFO("DBG_RX_DROP_FRAME "FUNC_ADPT_FMT" SA="MAC_FMT", myhwaddr="MAC_FMT"\n"
+				, FUNC_ADPT_ARG(adapter), MAC_ARG(pattrib->src), MAC_ARG(myhwaddr));
+			#endif
+			ret = _FAIL;
+			goto exit;
+		}
+
+		/* da should be for me */
+		if ((!_rtw_memcmp(myhwaddr, pattrib->dst, ETH_ALEN)) && (!bmcast)) {
+			#ifdef DBG_RX_DROP_FRAME
+			RTW_INFO("DBG_RX_DROP_FRAME "FUNC_ADPT_FMT" DA="MAC_FMT"\n"
+				, FUNC_ADPT_ARG(adapter), MAC_ARG(pattrib->dst));
+			#endif
+			ret = _FAIL;
+			goto exit;
+		}
+
+
+		/* check BSSID */
+		if (_rtw_memcmp(pattrib->bssid, "\x0\x0\x0\x0\x0\x0", ETH_ALEN) ||
+		    _rtw_memcmp(mybssid, "\x0\x0\x0\x0\x0\x0", ETH_ALEN) ||
+		    (!_rtw_memcmp(pattrib->bssid, mybssid, ETH_ALEN))) {
+			#ifdef DBG_RX_DROP_FRAME
+			RTW_INFO("DBG_RX_DROP_FRAME "FUNC_ADPT_FMT" BSSID="MAC_FMT", mybssid="MAC_FMT"\n"
+				, FUNC_ADPT_ARG(adapter), MAC_ARG(pattrib->bssid), MAC_ARG(mybssid));
+			#endif
+
+			if (!bmcast
+				&& !IS_RADAR_DETECTED(adapter_to_rfctl(adapter))
+			) {
+				RTW_INFO(ADPT_FMT" -issue_deauth to the nonassociated ap=" MAC_FMT " for the reason(7)\n", ADPT_ARG(adapter), MAC_ARG(pattrib->bssid));
+				issue_deauth(adapter, pattrib->bssid, WLAN_REASON_CLASS3_FRAME_FROM_NONASSOC_STA);
+			}
+
+			ret = _FAIL;
+			goto exit;
+		}
+
+		*psta = rtw_get_stainfo(pstapriv, pattrib->ta);
+		if (*psta == NULL) {
+			#ifdef DBG_RX_DROP_FRAME
+			RTW_INFO("DBG_RX_DROP_FRAME "FUNC_ADPT_FMT" can't get psta under STATION_MODE ; drop pkt\n"
+				, FUNC_ADPT_ARG(adapter));
+			#endif
+			ret = _FAIL;
+			goto exit;
+		}
+
+		/*if ((get_frame_sub_type(ptr) & WIFI_QOS_DATA_TYPE) == WIFI_QOS_DATA_TYPE) {
+		}
+		*/
+
+		if (get_frame_sub_type(ptr) & BIT(6)) {
+			/* No data, will not indicate to upper layer, temporily count it here */
+			count_rx_stats(adapter, precv_frame, *psta);
+			ret = RTW_RX_HANDLED;
+			goto exit;
+		}
+
+	} else if ((check_fwstate(pmlmepriv, WIFI_MP_STATE) == _TRUE) &&
+		   (check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE)) {
+		_rtw_memcpy(pattrib->dst, GetAddr1Ptr(ptr), ETH_ALEN);
+		_rtw_memcpy(pattrib->src, get_addr2_ptr(ptr), ETH_ALEN);
+		_rtw_memcpy(pattrib->bssid, GetAddr3Ptr(ptr), ETH_ALEN);
+		_rtw_memcpy(pattrib->ra, pattrib->dst, ETH_ALEN);
+		_rtw_memcpy(pattrib->ta, pattrib->src, ETH_ALEN);
+
+
+		*psta = rtw_get_stainfo(pstapriv, pattrib->bssid); /* get sta_info */
+		if (*psta == NULL) {
+			#ifdef DBG_RX_DROP_FRAME
+			RTW_INFO("DBG_RX_DROP_FRAME "FUNC_ADPT_FMT" can't get psta under WIFI_MP_STATE ; drop pkt\n"
+				, FUNC_ADPT_ARG(adapter));
+			#endif
+			ret = _FAIL;
+			goto exit;
+		}
+
+
+	} else if (check_fwstate(pmlmepriv, WIFI_AP_STATE) == _TRUE) {
+		/* Special case */
+		ret = RTW_RX_HANDLED;
+		goto exit;
+	} else {
+		if (_rtw_memcmp(myhwaddr, pattrib->dst, ETH_ALEN) && (!bmcast)) {
+			*psta = rtw_get_stainfo(pstapriv, pattrib->ta);
+			if (*psta == NULL) {
+
+				/* for AP multicast issue , modify by yiwei */
+				static systime send_issue_deauth_time = 0;
+
+				/* RTW_INFO("After send deauth , %u ms has elapsed.\n", rtw_get_passing_time_ms(send_issue_deauth_time)); */
+
+				if (rtw_get_passing_time_ms(send_issue_deauth_time) > 10000 || send_issue_deauth_time == 0) {
+					send_issue_deauth_time = rtw_get_current_time();
+
+					RTW_INFO("issue_deauth to the ap=" MAC_FMT " for the reason(7)\n", MAC_ARG(pattrib->bssid));
+
+					issue_deauth(adapter, pattrib->bssid, WLAN_REASON_CLASS3_FRAME_FROM_NONASSOC_STA);
+				}
+			}
+		}
+
+		ret = _FAIL;
+		#ifdef DBG_RX_DROP_FRAME
+		RTW_INFO("DBG_RX_DROP_FRAME "FUNC_ADPT_FMT" fw_state:0x%x\n"
+			, FUNC_ADPT_ARG(adapter), get_fwstate(pmlmepriv));
+		#endif
+	}
+
+exit:
+
+
+	return ret;
+
+}
+
+sint sta2ap_data_frame(
+	_adapter *adapter,
+	union recv_frame *precv_frame,
+	struct sta_info **psta)
+{
+	u8 *ptr = precv_frame->u.hdr.rx_data;
+	struct rx_pkt_attrib *pattrib = &precv_frame->u.hdr.attrib;
+	struct	sta_priv		*pstapriv = &adapter->stapriv;
+	struct	mlme_priv	*pmlmepriv = &adapter->mlmepriv;
+	unsigned char *mybssid  = get_bssid(pmlmepriv);
+	sint ret = _SUCCESS;
+
+
+	if (check_fwstate(pmlmepriv, WIFI_AP_STATE) == _TRUE) {
+		/* For AP mode, RA=BSSID, TX=STA(SRC_ADDR), A3=DST_ADDR */
+		if (!_rtw_memcmp(pattrib->bssid, mybssid, ETH_ALEN)) {
+			ret = _FAIL;
+			goto exit;
+		}
+
+		*psta = rtw_get_stainfo(pstapriv, pattrib->ta);
+		if (*psta == NULL) {
+			if (!IS_RADAR_DETECTED(adapter_to_rfctl(adapter))) {
+				RTW_INFO("issue_deauth to sta=" MAC_FMT " for the reason(7)\n", MAC_ARG(pattrib->src));
+				issue_deauth(adapter, pattrib->src, WLAN_REASON_CLASS3_FRAME_FROM_NONASSOC_STA);
+			}
+
+			ret = RTW_RX_HANDLED;
+			goto exit;
+		}
+
+		process_pwrbit_data(adapter, precv_frame, *psta);
+
+		if ((get_frame_sub_type(ptr) & WIFI_QOS_DATA_TYPE) == WIFI_QOS_DATA_TYPE)
+			process_wmmps_data(adapter, precv_frame, *psta);
+
+		if (get_frame_sub_type(ptr) & BIT(6)) {
+			/* No data, will not indicate to upper layer, temporily count it here */
+			count_rx_stats(adapter, precv_frame, *psta);
+			ret = RTW_RX_HANDLED;
+			goto exit;
+		}
+	} else if ((check_fwstate(pmlmepriv, WIFI_MP_STATE) == _TRUE) &&
+		   (check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE)) {
+		/* RTW_INFO("%s ,in WIFI_MP_STATE\n",__func__); */
+		_rtw_memcpy(pattrib->dst, GetAddr1Ptr(ptr), ETH_ALEN);
+		_rtw_memcpy(pattrib->src, get_addr2_ptr(ptr), ETH_ALEN);
+		_rtw_memcpy(pattrib->bssid, GetAddr3Ptr(ptr), ETH_ALEN);
+		_rtw_memcpy(pattrib->ra, pattrib->dst, ETH_ALEN);
+		_rtw_memcpy(pattrib->ta, pattrib->src, ETH_ALEN);
+
+
+		*psta = rtw_get_stainfo(pstapriv, pattrib->bssid); /* get sta_info */
+		if (*psta == NULL) {
+			#ifdef DBG_RX_DROP_FRAME
+			RTW_INFO("DBG_RX_DROP_FRAME "FUNC_ADPT_FMT" can't get psta under WIFI_MP_STATE ; drop pkt\n"
+				, FUNC_ADPT_ARG(adapter));
+			#endif
+			ret = _FAIL;
+			goto exit;
+		}
+
+	} else {
+		u8 *myhwaddr = adapter_mac_addr(adapter);
+		if (!_rtw_memcmp(pattrib->ra, myhwaddr, ETH_ALEN)) {
+			ret = RTW_RX_HANDLED;
+			goto exit;
+		}
+		RTW_INFO("issue_deauth to sta=" MAC_FMT " for the reason(7)\n", MAC_ARG(pattrib->src));
+		issue_deauth(adapter, pattrib->src, WLAN_REASON_CLASS3_FRAME_FROM_NONASSOC_STA);
+		ret = RTW_RX_HANDLED;
+		goto exit;
+	}
+
+exit:
+
+
+	return ret;
+
+}
+
+sint validate_recv_ctrl_frame(_adapter *padapter, union recv_frame *precv_frame);
+sint validate_recv_ctrl_frame(_adapter *padapter, union recv_frame *precv_frame)
+{
+	struct rx_pkt_attrib *pattrib = &precv_frame->u.hdr.attrib;
+	struct sta_priv *pstapriv = &padapter->stapriv;
+	u8 *pframe = precv_frame->u.hdr.rx_data;
+	struct sta_info *psta = NULL;
+	/* uint len = precv_frame->u.hdr.len; */
+
+	/* RTW_INFO("+validate_recv_ctrl_frame\n"); */
+
+	if (GetFrameType(pframe) != WIFI_CTRL_TYPE)
+		return _FAIL;
+
+	/* receive the frames that ra(a1) is my address */
+	if (!_rtw_memcmp(GetAddr1Ptr(pframe), adapter_mac_addr(padapter), ETH_ALEN))
+		return _FAIL;
+
+	psta = rtw_get_stainfo(pstapriv, get_addr2_ptr(pframe));
+	if (psta == NULL)
+		return _FAIL;
+
+	/* for rx pkt statistics */
+	psta->sta_stats.last_rx_time = rtw_get_current_time();
+	psta->sta_stats.rx_ctrl_pkts++;
+
+	/* only handle ps-poll */
+	if (get_frame_sub_type(pframe) == WIFI_PSPOLL) {
+#ifdef CONFIG_AP_MODE
+		u16 aid;
+		u8 wmmps_ac = 0;
+
+		aid = GetAid(pframe);
+		if (psta->cmn.aid != aid)
+			return _FAIL;
+
+		switch (pattrib->priority) {
+		case 1:
+		case 2:
+			wmmps_ac = psta->uapsd_bk & BIT(0);
+			break;
+		case 4:
+		case 5:
+			wmmps_ac = psta->uapsd_vi & BIT(0);
+			break;
+		case 6:
+		case 7:
+			wmmps_ac = psta->uapsd_vo & BIT(0);
+			break;
+		case 0:
+		case 3:
+		default:
+			wmmps_ac = psta->uapsd_be & BIT(0);
+			break;
+		}
+
+		if (wmmps_ac)
+			return _FAIL;
+
+		if (psta->state & WIFI_STA_ALIVE_CHK_STATE) {
+			RTW_INFO("%s alive check-rx ps-poll\n", __func__);
+			psta->expire_to = pstapriv->expire_to;
+			psta->state ^= WIFI_STA_ALIVE_CHK_STATE;
+		}
+
+		if ((psta->state & WIFI_SLEEP_STATE) && (rtw_tim_map_is_set(padapter, pstapriv->sta_dz_bitmap, psta->cmn.aid))) {
+			_irqL irqL;
+			_list	*xmitframe_plist, *xmitframe_phead;
+			struct xmit_frame *pxmitframe = NULL;
+			struct xmit_priv *pxmitpriv = &padapter->xmitpriv;
+
+			/* _enter_critical_bh(&psta->sleep_q.lock, &irqL); */
+			_enter_critical_bh(&pxmitpriv->lock, &irqL);
+
+			xmitframe_phead = get_list_head(&psta->sleep_q);
+			xmitframe_plist = get_next(xmitframe_phead);
+
+			if ((rtw_end_of_queue_search(xmitframe_phead, xmitframe_plist)) == _FALSE) {
+				pxmitframe = LIST_CONTAINOR(xmitframe_plist, struct xmit_frame, list);
+
+				xmitframe_plist = get_next(xmitframe_plist);
+
+				rtw_list_delete(&pxmitframe->list);
+
+				psta->sleepq_len--;
+
+				if (psta->sleepq_len > 0)
+					pxmitframe->attrib.mdata = 1;
+				else
+					pxmitframe->attrib.mdata = 0;
+
+				pxmitframe->attrib.triggered = 1;
+
+				/* RTW_INFO("handling ps-poll, q_len=%d\n", psta->sleepq_len); */
+				/* RTW_INFO_DUMP("handling, tim=", pstapriv->tim_bitmap, pstapriv->aid_bmp_len); */
+
+#if 0
+				_exit_critical_bh(&psta->sleep_q.lock, &irqL);
+				if (rtw_hal_xmit(padapter, pxmitframe) == _TRUE)
+					rtw_os_xmit_complete(padapter, pxmitframe);
+				_enter_critical_bh(&psta->sleep_q.lock, &irqL);
+#endif
+				rtw_hal_xmitframe_enqueue(padapter, pxmitframe);
+
+				if (psta->sleepq_len == 0) {
+					rtw_tim_map_clear(padapter, pstapriv->tim_bitmap, psta->cmn.aid);
+
+					/* RTW_INFO("after handling ps-poll\n"); */
+					/* RTW_INFO_DUMP("after handling, tim=", pstapriv->tim_bitmap, pstapriv->aid_bmp_len); */
+
+					/* upate BCN for TIM IE */
+					/* update_BCNTIM(padapter);		 */
+					update_beacon(padapter, _TIM_IE_, NULL, _TRUE);
+				}
+
+				/* _exit_critical_bh(&psta->sleep_q.lock, &irqL); */
+				_exit_critical_bh(&pxmitpriv->lock, &irqL);
+
+			} else {
+				/* _exit_critical_bh(&psta->sleep_q.lock, &irqL); */
+				_exit_critical_bh(&pxmitpriv->lock, &irqL);
+
+				/* RTW_INFO("no buffered packets to xmit\n"); */
+				if (rtw_tim_map_is_set(padapter, pstapriv->tim_bitmap, psta->cmn.aid)) {
+					if (psta->sleepq_len == 0) {
+						RTW_INFO("no buffered packets to xmit\n");
+
+						/* issue nulldata with More data bit = 0 to indicate we have no buffered packets */
+						issue_nulldata(padapter, psta->cmn.mac_addr, 0, 0, 0);
+					} else {
+						RTW_INFO("error!psta->sleepq_len=%d\n", psta->sleepq_len);
+						psta->sleepq_len = 0;
+					}
+
+					rtw_tim_map_clear(padapter, pstapriv->tim_bitmap, psta->cmn.aid);
+
+					/* upate BCN for TIM IE */
+					/* update_BCNTIM(padapter); */
+					update_beacon(padapter, _TIM_IE_, NULL, _TRUE);
+				}
+			}
+		}
+#endif /* CONFIG_AP_MODE */
+	} else if (get_frame_sub_type(pframe) == WIFI_NDPA) {
+#ifdef CONFIG_BEAMFORMING
+		rtw_beamforming_get_ndpa_frame(padapter, precv_frame);
+#endif/*CONFIG_BEAMFORMING*/
+	} else if (get_frame_sub_type(pframe) == WIFI_BAR) {
+		rtw_process_bar_frame(padapter, precv_frame);
+	}
+
+	return _FAIL;
+
+}
+
+#if defined(CONFIG_IEEE80211W) || defined(CONFIG_RTW_MESH)
+static sint validate_mgmt_protect(_adapter *adapter, union recv_frame *precv_frame)
+{
+#define DBG_VALIDATE_MGMT_PROTECT 0
+#define DBG_VALIDATE_MGMT_DEC 0
+
+	struct security_priv *sec = &adapter->securitypriv;
+	struct rx_pkt_attrib *pattrib = &precv_frame->u.hdr.attrib;
+	struct sta_info	*psta = precv_frame->u.hdr.psta;
+	u8 *ptr;
+	u8 type;
+	u8 subtype;
+	u8 is_bmc;
+	u8 category = 0xFF;
+
+#ifdef CONFIG_IEEE80211W
+	const u8 *igtk;
+	u16 igtk_id;
+	u64* ipn;
+#endif
+
+	u8 *mgmt_DATA;
+	u32 data_len = 0;
+
+	sint ret;
+
+#ifdef CONFIG_RTW_MESH
+	if (MLME_IS_MESH(adapter)) {
+		if (!adapter->mesh_info.mesh_auth_id)
+			return pattrib->privacy ? _FAIL : _SUCCESS;
+	} else
+#endif
+	if (SEC_IS_BIP_KEY_INSTALLED(sec) == _FALSE)
+		return _SUCCESS;
+
+	ptr = precv_frame->u.hdr.rx_data;
+	type = GetFrameType(ptr);
+	subtype = get_frame_sub_type(ptr); /* bit(7)~bit(2) */
+	is_bmc = IS_MCAST(GetAddr1Ptr(ptr));
+
+#if DBG_VALIDATE_MGMT_PROTECT
+	if (subtype == WIFI_DEAUTH) {
+		RTW_INFO(FUNC_ADPT_FMT" bmc:%u, deauth, privacy:%u, encrypt:%u, bdecrypted:%u\n"
+			, FUNC_ADPT_ARG(adapter)
+			, is_bmc, pattrib->privacy, pattrib->encrypt, pattrib->bdecrypted);
+	} else if (subtype == WIFI_DISASSOC) {
+		RTW_INFO(FUNC_ADPT_FMT" bmc:%u, disassoc, privacy:%u, encrypt:%u, bdecrypted:%u\n"
+			, FUNC_ADPT_ARG(adapter)
+			, is_bmc, pattrib->privacy, pattrib->encrypt, pattrib->bdecrypted);
+	} if (subtype == WIFI_ACTION) {
+		if (pattrib->privacy) {
+			RTW_INFO(FUNC_ADPT_FMT" bmc:%u, action(?), privacy:%u, encrypt:%u, bdecrypted:%u\n"
+				, FUNC_ADPT_ARG(adapter)
+				, is_bmc, pattrib->privacy, pattrib->encrypt, pattrib->bdecrypted);
+		} else {
+			RTW_INFO(FUNC_ADPT_FMT" bmc:%u, action(%u), privacy:%u, encrypt:%u, bdecrypted:%u\n"
+				, FUNC_ADPT_ARG(adapter), is_bmc
+				, *(ptr + sizeof(struct rtw_ieee80211_hdr_3addr))
+				, pattrib->privacy, pattrib->encrypt, pattrib->bdecrypted);
+		}
+	}
+#endif
+
+	if (!pattrib->privacy) {
+		if (!psta || !(psta->flags & WLAN_STA_MFP)) {
+			/* peer is not MFP capable, no need to check */
+			goto exit;
+		}
+
+		if (subtype == WIFI_ACTION)
+			category = *(ptr + sizeof(struct rtw_ieee80211_hdr_3addr));
+
+		if (is_bmc) {
+			/* broadcast cases */
+			if (subtype == WIFI_ACTION) {
+				if (CATEGORY_IS_GROUP_PRIVACY(category)) {
+					/* drop broadcast group privacy action frame without encryption */
+					#if DBG_VALIDATE_MGMT_PROTECT
+					RTW_INFO(FUNC_ADPT_FMT" broadcast gp action(%u) w/o encrypt\n"
+						, FUNC_ADPT_ARG(adapter), category);
+					#endif
+					goto fail;
+				}
+				if (CATEGORY_IS_ROBUST(category)) {
+					/* broadcast robust action frame need BIP check */
+					goto bip_verify;
+				}
+			}
+			if (subtype == WIFI_DEAUTH || subtype == WIFI_DISASSOC) {
+				/* broadcast deauth or disassoc frame need BIP check */
+				goto bip_verify;
+			}
+			goto exit;
+
+		} else {
+			/* unicast cases */
+			#ifdef CONFIG_IEEE80211W
+			if (subtype == WIFI_DEAUTH || subtype == WIFI_DISASSOC) {
+				if (!MLME_IS_MESH(adapter)) {
+					unsigned short reason = le16_to_cpu(*(unsigned short *)(ptr + WLAN_HDR_A3_LEN));
+
+					#if DBG_VALIDATE_MGMT_PROTECT
+					RTW_INFO(FUNC_ADPT_FMT" unicast %s, reason=%d w/o encrypt\n"
+						, FUNC_ADPT_ARG(adapter), subtype == WIFI_DEAUTH ? "deauth" : "disassoc", reason);
+					#endif
+					if (reason == 6 || reason == 7) {
+						/* issue sa query request */
+						issue_action_SA_Query(adapter, psta->cmn.mac_addr, 0, 0, IEEE80211W_RIGHT_KEY);
+					}
+				}
+				goto fail;
+			}
+			#endif
+
+			if (subtype == WIFI_ACTION && CATEGORY_IS_ROBUST(category)) {
+				if (psta->bpairwise_key_installed == _TRUE) {
+					#if DBG_VALIDATE_MGMT_PROTECT
+					RTW_INFO(FUNC_ADPT_FMT" unicast robust action(%d) w/o encrypt\n"
+						, FUNC_ADPT_ARG(adapter), category);
+					#endif
+					goto fail;
+				}
+			}
+			goto exit;
+		}
+
+bip_verify:
+#ifdef CONFIG_IEEE80211W
+		#ifdef CONFIG_RTW_MESH
+		if (MLME_IS_MESH(adapter)) {
+			if (psta->igtk_bmp) {
+				igtk = psta->igtk.skey;
+				igtk_id = psta->igtk_id;
+				ipn = &psta->igtk_pn.val;
+			} else {
+				/* mesh MFP without IGTK */
+				goto exit;
+			}
+		} else
+		#endif
+		{
+			igtk = sec->dot11wBIPKey[sec->dot11wBIPKeyid].skey;
+			igtk_id = sec->dot11wBIPKeyid;
+			ipn = &sec->dot11wBIPrxpn.val;
+		}
+
+		/* verify BIP MME IE */
+		ret = rtw_BIP_verify(adapter
+			, get_recvframe_data(precv_frame)
+			, get_recvframe_len(precv_frame)
+			, igtk, igtk_id, ipn);
+		if (ret == _FAIL) {
+			/* RTW_INFO("802.11w BIP verify fail\n"); */
+			goto fail;
+
+		} else if (ret == RTW_RX_HANDLED) {
+			#if DBG_VALIDATE_MGMT_PROTECT
+			RTW_INFO(FUNC_ADPT_FMT" none protected packet\n", FUNC_ADPT_ARG(adapter));
+			#endif
+			goto fail;
+		}
+#endif /* CONFIG_IEEE80211W */
+		goto exit;
+	}
+
+	/* cases to decrypt mgmt frame */
+	pattrib->bdecrypted = 0;
+	pattrib->encrypt = _AES_;
+	pattrib->hdrlen = sizeof(struct rtw_ieee80211_hdr_3addr);
+
+	/* set iv and icv length */
+	SET_ICE_IV_LEN(pattrib->iv_len, pattrib->icv_len, pattrib->encrypt);
+	_rtw_memcpy(pattrib->ra, GetAddr1Ptr(ptr), ETH_ALEN);
+	_rtw_memcpy(pattrib->ta, get_addr2_ptr(ptr), ETH_ALEN);
+
+	/* actual management data frame body */
+	data_len = pattrib->pkt_len - pattrib->hdrlen - pattrib->iv_len - pattrib->icv_len;
+	mgmt_DATA = rtw_zmalloc(data_len);
+	if (mgmt_DATA == NULL) {
+		RTW_INFO(FUNC_ADPT_FMT" mgmt allocate fail  !!!!!!!!!\n", FUNC_ADPT_ARG(adapter));
+		goto fail;
+	}
+
+#if DBG_VALIDATE_MGMT_DEC
+	/* dump the packet content before decrypt */
+	{
+		int pp;
+
+		printk("pattrib->pktlen = %d =>", pattrib->pkt_len);
+		for (pp = 0; pp < pattrib->pkt_len; pp++)
+		printk(" %02x ", ptr[pp]);
+		printk("\n");
+	}
+#endif
+
+	precv_frame = decryptor(adapter, precv_frame);
+	/* save actual management data frame body */
+	_rtw_memcpy(mgmt_DATA, ptr + pattrib->hdrlen + pattrib->iv_len, data_len);
+	/* overwrite the iv field */
+	_rtw_memcpy(ptr + pattrib->hdrlen, mgmt_DATA, data_len);
+	/* remove the iv and icv length */
+	pattrib->pkt_len = pattrib->pkt_len - pattrib->iv_len - pattrib->icv_len;
+	rtw_mfree(mgmt_DATA, data_len);
+
+#if DBG_VALIDATE_MGMT_DEC
+	/* print packet content after decryption */
+	{
+		int pp;
+
+		printk("after decryption pattrib->pktlen = %d @@=>", pattrib->pkt_len);
+		for (pp = 0; pp < pattrib->pkt_len; pp++)
+		printk(" %02x ", ptr[pp]);
+		printk("\n");
+	}
+#endif
+
+	if (!precv_frame) {
+		#if DBG_VALIDATE_MGMT_PROTECT
+		RTW_INFO(FUNC_ADPT_FMT" mgmt descrypt fail  !!!!!!!!!\n", FUNC_ADPT_ARG(adapter));
+		#endif
+		goto fail;
+	}
+
+exit:
+	return _SUCCESS;
+
+fail:
+	return _FAIL;
+
+}
+#endif /* defined(CONFIG_IEEE80211W) || defined(CONFIG_RTW_MESH) */
+
+union recv_frame *recvframe_chk_defrag(PADAPTER padapter, union recv_frame *precv_frame);
+
+sint validate_recv_mgnt_frame(PADAPTER padapter, union recv_frame *precv_frame)
+{
+	struct sta_info *psta = precv_frame->u.hdr.psta
+		= rtw_get_stainfo(&padapter->stapriv, get_addr2_ptr(precv_frame->u.hdr.rx_data));
+
+#if defined(CONFIG_IEEE80211W) || defined(CONFIG_RTW_MESH)
+	if (validate_mgmt_protect(padapter, precv_frame) == _FAIL) {
+		DBG_COUNTER(padapter->rx_logs.core_rx_pre_mgmt_err_80211w);
+		goto exit;
+	}
+#endif
+
+	precv_frame = recvframe_chk_defrag(padapter, precv_frame);
+	if (precv_frame == NULL)
+		return _SUCCESS;
+
+	/* for rx pkt statistics */
+	if (psta) {
+		psta->sta_stats.last_rx_time = rtw_get_current_time();
+		psta->sta_stats.rx_mgnt_pkts++;
+		if (get_frame_sub_type(precv_frame->u.hdr.rx_data) == WIFI_BEACON)
+			psta->sta_stats.rx_beacon_pkts++;
+		else if (get_frame_sub_type(precv_frame->u.hdr.rx_data) == WIFI_PROBEREQ)
+			psta->sta_stats.rx_probereq_pkts++;
+		else if (get_frame_sub_type(precv_frame->u.hdr.rx_data) == WIFI_PROBERSP) {
+			if (_rtw_memcmp(adapter_mac_addr(padapter), GetAddr1Ptr(precv_frame->u.hdr.rx_data), ETH_ALEN) == _TRUE)
+				psta->sta_stats.rx_probersp_pkts++;
+			else if (is_broadcast_mac_addr(GetAddr1Ptr(precv_frame->u.hdr.rx_data))
+				|| is_multicast_mac_addr(GetAddr1Ptr(precv_frame->u.hdr.rx_data)))
+				psta->sta_stats.rx_probersp_bm_pkts++;
+			else
+				psta->sta_stats.rx_probersp_uo_pkts++;
+		}
+	}
+
+#ifdef CONFIG_INTEL_PROXIM
+	if (padapter->proximity.proxim_on == _TRUE) {
+		struct rx_pkt_attrib *pattrib = &precv_frame->u.hdr.attrib;
+		struct recv_stat *prxstat = (struct recv_stat *)  precv_frame->u.hdr.rx_head ;
+		u8 *pda, *psa, *pbssid, *ptr;
+		ptr = precv_frame->u.hdr.rx_data;
+		pda = get_da(ptr);
+		psa = get_sa(ptr);
+		pbssid = get_hdr_bssid(ptr);
+
+
+		_rtw_memcpy(pattrib->dst, pda, ETH_ALEN);
+		_rtw_memcpy(pattrib->src, psa, ETH_ALEN);
+
+		_rtw_memcpy(pattrib->bssid, pbssid, ETH_ALEN);
+
+		switch (pattrib->to_fr_ds) {
+		case 0:
+			_rtw_memcpy(pattrib->ra, pda, ETH_ALEN);
+			_rtw_memcpy(pattrib->ta, psa, ETH_ALEN);
+			break;
+
+		case 1:
+			_rtw_memcpy(pattrib->ra, pda, ETH_ALEN);
+			_rtw_memcpy(pattrib->ta, pbssid, ETH_ALEN);
+			break;
+
+		case 2:
+			_rtw_memcpy(pattrib->ra, pbssid, ETH_ALEN);
+			_rtw_memcpy(pattrib->ta, psa, ETH_ALEN);
+			break;
+
+		case 3:
+			_rtw_memcpy(pattrib->ra, GetAddr1Ptr(ptr), ETH_ALEN);
+			_rtw_memcpy(pattrib->ta, get_addr2_ptr(ptr), ETH_ALEN);
+			break;
+
+		default:
+			break;
+
+		}
+		pattrib->priority = 0;
+		pattrib->hdrlen = pattrib->to_fr_ds == 3 ? 30 : 24;
+
+		padapter->proximity.proxim_rx(padapter, precv_frame);
+	}
+#endif
+	mgt_dispatcher(padapter, precv_frame);
+
+#if defined(CONFIG_IEEE80211W) || defined(CONFIG_RTW_MESH)
+exit:
+#endif
+	return _SUCCESS;
+
+}
+
+sint validate_recv_data_frame(_adapter *adapter, union recv_frame *precv_frame)
+{
+	u8 bretry, a4_shift;
+	struct sta_info *psta = NULL;
+	u8 *ptr = precv_frame->u.hdr.rx_data;
+	struct rx_pkt_attrib	*pattrib = &precv_frame->u.hdr.attrib;
+	struct security_priv	*psecuritypriv = &adapter->securitypriv;
+	sint ret = _SUCCESS;
+
+	bretry = GetRetry(ptr);
+	a4_shift = (pattrib->to_fr_ds == 3) ? ETH_ALEN : 0;
+
+	/* some address fields are different when using AMSDU */
+	if (pattrib->qos)
+		pattrib->amsdu = GetAMsdu(ptr + WLAN_HDR_A3_LEN + a4_shift);
+	else
+		pattrib->amsdu = 0;
+
+#ifdef CONFIG_RTW_MESH
+	if (MLME_IS_MESH(adapter)) {
+		ret = rtw_mesh_rx_data_validate_hdr(adapter, precv_frame, &psta);
+		goto pre_validate_status_chk;
+	}
+#endif
+
+	switch (pattrib->to_fr_ds) {
+	case 0:
+		_rtw_memcpy(pattrib->ra, GetAddr1Ptr(ptr), ETH_ALEN);
+		_rtw_memcpy(pattrib->ta, get_addr2_ptr(ptr), ETH_ALEN);
+		_rtw_memcpy(pattrib->dst, GetAddr1Ptr(ptr), ETH_ALEN);
+		_rtw_memcpy(pattrib->src, get_addr2_ptr(ptr), ETH_ALEN);
+		_rtw_memcpy(pattrib->bssid, GetAddr3Ptr(ptr), ETH_ALEN);
+		ret = sta2sta_data_frame(adapter, precv_frame, &psta);
+		break;
+
+	case 1:
+		_rtw_memcpy(pattrib->ra, GetAddr1Ptr(ptr), ETH_ALEN);
+		_rtw_memcpy(pattrib->ta, get_addr2_ptr(ptr), ETH_ALEN);
+		_rtw_memcpy(pattrib->dst, GetAddr1Ptr(ptr), ETH_ALEN);
+		_rtw_memcpy(pattrib->src, GetAddr3Ptr(ptr), ETH_ALEN);
+		_rtw_memcpy(pattrib->bssid, get_addr2_ptr(ptr), ETH_ALEN);
+		ret = ap2sta_data_frame(adapter, precv_frame, &psta);
+		break;
+
+	case 2:
+		_rtw_memcpy(pattrib->ra, GetAddr1Ptr(ptr), ETH_ALEN);
+		_rtw_memcpy(pattrib->ta, get_addr2_ptr(ptr), ETH_ALEN);
+		_rtw_memcpy(pattrib->dst, GetAddr3Ptr(ptr), ETH_ALEN);
+		_rtw_memcpy(pattrib->src, get_addr2_ptr(ptr), ETH_ALEN);
+		_rtw_memcpy(pattrib->bssid, GetAddr1Ptr(ptr), ETH_ALEN);
+		ret = sta2ap_data_frame(adapter, precv_frame, &psta);
+		break;
+
+	case 3:
+	default:
+		/* WDS is not supported */
+		ret = _FAIL;
+		break;
+	}
+
+#ifdef CONFIG_RTW_MESH
+pre_validate_status_chk:
+#endif
+	if (ret == _FAIL) {
+		#ifdef DBG_RX_DROP_FRAME
+		RTW_INFO("DBG_RX_DROP_FRAME "FUNC_ADPT_FMT" case:%d, res:%d, ra="MAC_FMT", ta="MAC_FMT"\n"
+			, FUNC_ADPT_ARG(adapter), pattrib->to_fr_ds, ret, MAC_ARG(GetAddr1Ptr(ptr)), MAC_ARG(get_addr2_ptr(ptr)));
+		#endif
+		goto exit;
+	} else if (ret == RTW_RX_HANDLED)
+		goto exit;
+
+
+	if (psta == NULL) {
+		#ifdef DBG_RX_DROP_FRAME
+		RTW_INFO("DBG_RX_DROP_FRAME "FUNC_ADPT_FMT" psta == NULL, ra="MAC_FMT", ta="MAC_FMT"\n"
+			, FUNC_ADPT_ARG(adapter), MAC_ARG(GetAddr1Ptr(ptr)), MAC_ARG(get_addr2_ptr(ptr)));
+		#endif
+		ret = _FAIL;
+		goto exit;
+	}
+
+	precv_frame->u.hdr.psta = psta;
+	precv_frame->u.hdr.preorder_ctrl = NULL;
+	pattrib->ack_policy = 0;
+
+	/* parsing QC field */
+	if (pattrib->qos == 1) {
+		pattrib->priority = GetPriority((ptr + WLAN_HDR_A3_LEN + a4_shift)); /* point to Qos field*/
+		pattrib->ack_policy = GetAckpolicy((ptr + WLAN_HDR_A3_LEN + a4_shift));
+		pattrib->hdrlen = WLAN_HDR_A3_QOS_LEN + a4_shift;
+		if (pattrib->priority != 0 && pattrib->priority != 3)
+			adapter->recvpriv.is_any_non_be_pkts = _TRUE;
+		else
+			adapter->recvpriv.is_any_non_be_pkts = _FALSE;
+	} else {
+		pattrib->priority = 0;
+		pattrib->hdrlen = WLAN_HDR_A3_LEN + a4_shift;
+	}
+
+	if (pattrib->order) /* HT-CTRL 11n */
+		pattrib->hdrlen += 4;
+
+	/* decache, drop duplicate recv packets */
+	ret = recv_decache(precv_frame);
+	if (ret  == _FAIL)
+		goto exit;
+
+	if (!IS_MCAST(pattrib->ra)) {
+
+		if (pattrib->qos)
+			precv_frame->u.hdr.preorder_ctrl = &psta->recvreorder_ctrl[pattrib->priority];
+
+		if (recv_ucast_pn_decache(precv_frame) == _FAIL) {
+			#ifdef DBG_RX_DROP_FRAME
+			RTW_INFO("DBG_RX_DROP_FRAME "FUNC_ADPT_FMT" recv_ucast_pn_decache return _FAIL for sta="MAC_FMT"\n"
+				, FUNC_ADPT_ARG(adapter), MAC_ARG(psta->cmn.mac_addr));
+			#endif
+			ret = _FAIL;
+			goto exit;
+		}
+	} else {
+		if (recv_bcast_pn_decache(precv_frame) == _FAIL) {
+			#ifdef DBG_RX_DROP_FRAME
+			RTW_INFO("DBG_RX_DROP_FRAME "FUNC_ADPT_FMT" recv_bcast_pn_decache return _FAIL for sta="MAC_FMT"\n"
+				, FUNC_ADPT_ARG(adapter), MAC_ARG(psta->cmn.mac_addr));
+			#endif
+			ret = _FAIL;
+			goto exit;
+		}
+	}
+
+	if (pattrib->privacy) {
+#ifdef CONFIG_TDLS
+		if ((psta->tdls_sta_state & TDLS_LINKED_STATE) && (psta->dot118021XPrivacy == _AES_))
+			pattrib->encrypt = psta->dot118021XPrivacy;
+		else
+#endif /* CONFIG_TDLS */
+			GET_ENCRY_ALGO(psecuritypriv, psta, pattrib->encrypt, IS_MCAST(pattrib->ra));
+
+
+		SET_ICE_IV_LEN(pattrib->iv_len, pattrib->icv_len, pattrib->encrypt);
+	} else {
+		pattrib->encrypt = 0;
+		pattrib->iv_len = pattrib->icv_len = 0;
+	}
+
+#ifdef CONFIG_RTW_MESH
+	if (!pattrib->amsdu
+		&& pattrib->mesh_ctrl_present
+		&& (!pattrib->encrypt || pattrib->bdecrypted))
+		ret = rtw_mesh_rx_validate_mctrl_non_amsdu(adapter, precv_frame);
+#endif
+
+exit:
+	return ret;
+}
+
+static inline void dump_rx_packet(u8 *ptr)
+{
+	int i;
+
+	RTW_INFO("#############################\n");
+	for (i = 0; i < 64; i = i + 8)
+		RTW_INFO("%02X:%02X:%02X:%02X:%02X:%02X:%02X:%02X:\n", *(ptr + i),
+			*(ptr + i + 1), *(ptr + i + 2) , *(ptr + i + 3) , *(ptr + i + 4), *(ptr + i + 5), *(ptr + i + 6), *(ptr + i + 7));
+	RTW_INFO("#############################\n");
+}
+
+sint validate_recv_frame(_adapter *adapter, union recv_frame *precv_frame);
+sint validate_recv_frame(_adapter *adapter, union recv_frame *precv_frame)
+{
+	/* shall check frame subtype, to / from ds, da, bssid */
+
+	/* then call check if rx seq/frag. duplicated. */
+
+	u8 type;
+	u8 subtype;
+	sint retval = _SUCCESS;
+
+	struct rx_pkt_attrib *pattrib = &precv_frame->u.hdr.attrib;
+	struct recv_priv  *precvpriv = &adapter->recvpriv;
+
+	u8 *ptr = precv_frame->u.hdr.rx_data;
+	u8  ver = (unsigned char)(*ptr) & 0x3 ;
+#ifdef CONFIG_FIND_BEST_CHANNEL
+	struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter);
+	struct mlme_ext_priv *pmlmeext = &adapter->mlmeextpriv;
+#endif
+
+#ifdef CONFIG_TDLS
+	struct tdls_info *ptdlsinfo = &adapter->tdlsinfo;
+#endif /* CONFIG_TDLS */
+#ifdef CONFIG_WAPI_SUPPORT
+	PRT_WAPI_T	pWapiInfo = &adapter->wapiInfo;
+	struct recv_frame_hdr *phdr = &precv_frame->u.hdr;
+	u8 wai_pkt = 0;
+	u16 sc;
+	u8	external_len = 0;
+#endif
+
+
+#ifdef CONFIG_FIND_BEST_CHANNEL
+	if (pmlmeext->sitesurvey_res.state == SCAN_PROCESS) {
+		int ch_set_idx = rtw_chset_search_ch(rfctl->channel_set, rtw_get_oper_ch(adapter));
+		if (ch_set_idx >= 0)
+			rfctl->channel_set[ch_set_idx].rx_count++;
+	}
+#endif
+
+#ifdef CONFIG_TDLS
+	if (ptdlsinfo->ch_sensing == 1 && ptdlsinfo->cur_channel != 0)
+		ptdlsinfo->collect_pkt_num[ptdlsinfo->cur_channel - 1]++;
+#endif /* CONFIG_TDLS */
+
+#ifdef RTK_DMP_PLATFORM
+	if (0) {
+		RTW_INFO("++\n");
+		{
+			int i;
+			for (i = 0; i < 64; i = i + 8)
+				RTW_INFO("%02X:%02X:%02X:%02X:%02X:%02X:%02X:%02X:", *(ptr + i),
+					*(ptr + i + 1), *(ptr + i + 2) , *(ptr + i + 3) , *(ptr + i + 4), *(ptr + i + 5), *(ptr + i + 6), *(ptr + i + 7));
+
+		}
+		RTW_INFO("--\n");
+	}
+#endif /* RTK_DMP_PLATFORM */
+
+	/* add version chk */
+	if (ver != 0) {
+		retval = _FAIL;
+		DBG_COUNTER(adapter->rx_logs.core_rx_pre_ver_err);
+		goto exit;
+	}
+
+	type =  GetFrameType(ptr);
+	subtype = get_frame_sub_type(ptr); /* bit(7)~bit(2) */
+
+	pattrib->to_fr_ds = get_tofr_ds(ptr);
+
+	pattrib->frag_num = GetFragNum(ptr);
+	pattrib->seq_num = GetSequence(ptr);
+
+	pattrib->pw_save = GetPwrMgt(ptr);
+	pattrib->mfrag = GetMFrag(ptr);
+	pattrib->mdata = GetMData(ptr);
+	pattrib->privacy = GetPrivacy(ptr);
+	pattrib->order = GetOrder(ptr);
+#ifdef CONFIG_WAPI_SUPPORT
+	sc = (pattrib->seq_num << 4) | pattrib->frag_num;
+#endif
+
+#if 1 /* Dump rx packets */
+	{
+		u8 bDumpRxPkt = 0;
+
+		rtw_hal_get_def_var(adapter, HAL_DEF_DBG_DUMP_RXPKT, &(bDumpRxPkt));
+		if (bDumpRxPkt == 1) /* dump all rx packets */
+			dump_rx_packet(ptr);
+		else if ((bDumpRxPkt == 2) && (type == WIFI_MGT_TYPE))
+			dump_rx_packet(ptr);
+		else if ((bDumpRxPkt == 3) && (type == WIFI_DATA_TYPE))
+			dump_rx_packet(ptr);
+	}
+#endif
+	switch (type) {
+	case WIFI_MGT_TYPE: /* mgnt */
+		DBG_COUNTER(adapter->rx_logs.core_rx_pre_mgmt);
+		retval = validate_recv_mgnt_frame(adapter, precv_frame);
+		if (retval == _FAIL) {
+			DBG_COUNTER(adapter->rx_logs.core_rx_pre_mgmt_err);
+		}
+		retval = _FAIL; /* only data frame return _SUCCESS */
+		break;
+	case WIFI_CTRL_TYPE: /* ctrl */
+		DBG_COUNTER(adapter->rx_logs.core_rx_pre_ctrl);
+		retval = validate_recv_ctrl_frame(adapter, precv_frame);
+		if (retval == _FAIL) {
+			DBG_COUNTER(adapter->rx_logs.core_rx_pre_ctrl_err);
+		}
+		retval = _FAIL; /* only data frame return _SUCCESS */
+		break;
+	case WIFI_DATA_TYPE: /* data */
+		DBG_COUNTER(adapter->rx_logs.core_rx_pre_data);
+#ifdef CONFIG_WAPI_SUPPORT
+		if (pattrib->qos)
+			external_len = 2;
+		else
+			external_len = 0;
+
+		wai_pkt = rtw_wapi_is_wai_packet(adapter, ptr);
+
+		phdr->bIsWaiPacket = wai_pkt;
+
+		if (wai_pkt != 0) {
+			if (sc != adapter->wapiInfo.wapiSeqnumAndFragNum)
+				adapter->wapiInfo.wapiSeqnumAndFragNum = sc;
+			else {
+				retval = _FAIL;
+				DBG_COUNTER(adapter->rx_logs.core_rx_pre_data_wapi_seq_err);
+				break;
+			}
+		} else {
+
+			if (rtw_wapi_drop_for_key_absent(adapter, get_addr2_ptr(ptr))) {
+				retval = _FAIL;
+				WAPI_TRACE(WAPI_RX, "drop for key absent for rx\n");
+				DBG_COUNTER(adapter->rx_logs.core_rx_pre_data_wapi_key_err);
+				break;
+			}
+		}
+
+#endif
+
+		pattrib->qos = (subtype & BIT(7)) ? 1 : 0;
+		retval = validate_recv_data_frame(adapter, precv_frame);
+		if (retval == _FAIL) {
+			precvpriv->dbg_rx_drop_count++;
+			DBG_COUNTER(adapter->rx_logs.core_rx_pre_data_err);
+		} else if (retval == _SUCCESS) {
+			#ifdef DBG_RX_DUMP_EAP
+			if (!pattrib->encrypt || pattrib->bdecrypted) {
+				u8 bDumpRxPkt;
+				u16 eth_type;
+
+				/* dump eapol */
+				rtw_hal_get_def_var(adapter, HAL_DEF_DBG_DUMP_RXPKT, &(bDumpRxPkt));
+				/* get ether_type */
+				_rtw_memcpy(&eth_type, ptr + pattrib->hdrlen + pattrib->iv_len + RATTRIB_GET_MCTRL_LEN(pattrib) + LLC_HEADER_SIZE, 2);
+				eth_type = ntohs((unsigned short) eth_type);
+				if ((bDumpRxPkt == 4) && (eth_type == 0x888e))
+					dump_rx_packet(ptr);
+			}
+			#endif
+		} else
+			DBG_COUNTER(adapter->rx_logs.core_rx_pre_data_handled);
+		break;
+	default:
+		DBG_COUNTER(adapter->rx_logs.core_rx_pre_unknown);
+		#ifdef DBG_RX_DROP_FRAME
+		RTW_INFO("DBG_RX_DROP_FRAME "FUNC_ADPT_FMT" fail! type=0x%x\n"
+			, FUNC_ADPT_ARG(adapter), type);
+		#endif
+		retval = _FAIL;
+		break;
+	}
+
+exit:
+
+
+	return retval;
+}
+
+
+/* remove the wlanhdr and add the eth_hdr */
+#if 1
+sint wlanhdr_to_ethhdr(union recv_frame *precvframe)
+{
+	sint	rmv_len;
+	u16	eth_type, len;
+	u8	bsnaphdr;
+	u8	*psnap_type;
+	struct ieee80211_snap_hdr	*psnap;
+
+	sint ret = _SUCCESS;
+	_adapter			*adapter = precvframe->u.hdr.adapter;
+	struct mlme_priv	*pmlmepriv = &adapter->mlmepriv;
+
+	u8	*ptr = get_recvframe_data(precvframe) ; /* point to frame_ctrl field */
+	struct rx_pkt_attrib *pattrib = &precvframe->u.hdr.attrib;
+
+
+	if (pattrib->encrypt)
+		recvframe_pull_tail(precvframe, pattrib->icv_len);
+
+	psnap = (struct ieee80211_snap_hdr *)(ptr + pattrib->hdrlen + pattrib->iv_len + RATTRIB_GET_MCTRL_LEN(pattrib));
+	psnap_type = ptr + pattrib->hdrlen + pattrib->iv_len + RATTRIB_GET_MCTRL_LEN(pattrib) + SNAP_SIZE;
+	/* convert hdr + possible LLC headers into Ethernet header */
+	/* eth_type = (psnap_type[0] << 8) | psnap_type[1]; */
+	if ((_rtw_memcmp(psnap, rtw_rfc1042_header, SNAP_SIZE) &&
+	     (_rtw_memcmp(psnap_type, SNAP_ETH_TYPE_IPX, 2) == _FALSE) &&
+	     (_rtw_memcmp(psnap_type, SNAP_ETH_TYPE_APPLETALK_AARP, 2) == _FALSE)) ||
+	    /* eth_type != ETH_P_AARP && eth_type != ETH_P_IPX) || */
+	    _rtw_memcmp(psnap, rtw_bridge_tunnel_header, SNAP_SIZE)) {
+		/* remove RFC1042 or Bridge-Tunnel encapsulation and replace EtherType */
+		bsnaphdr = _TRUE;
+	} else {
+		/* Leave Ethernet header part of hdr and full payload */
+		bsnaphdr = _FALSE;
+	}
+
+	rmv_len = pattrib->hdrlen + pattrib->iv_len + RATTRIB_GET_MCTRL_LEN(pattrib) + (bsnaphdr ? SNAP_SIZE : 0);
+	len = precvframe->u.hdr.len - rmv_len;
+
+
+	_rtw_memcpy(&eth_type, ptr + rmv_len, 2);
+	eth_type = ntohs((unsigned short)eth_type); /* pattrib->ether_type */
+	pattrib->eth_type = eth_type;
+
+
+	if ((check_fwstate(pmlmepriv, WIFI_MP_STATE) == _TRUE)) {
+		ptr += rmv_len ;
+		*ptr = 0x87;
+		*(ptr + 1) = 0x12;
+
+		eth_type = 0x8712;
+		/* append rx status for mp test packets */
+		ptr = recvframe_pull(precvframe, (rmv_len - sizeof(struct ethhdr) + 2) - 24);
+		if (!ptr) {
+			ret = _FAIL;
+			goto exiting;
+		}
+		_rtw_memcpy(ptr, get_rxmem(precvframe), 24);
+		ptr += 24;
+	} else {
+		ptr = recvframe_pull(precvframe, (rmv_len - sizeof(struct ethhdr) + (bsnaphdr ? 2 : 0)));
+		if (!ptr) {
+			ret = _FAIL;
+			goto exiting;
+		}
+	}
+
+	if (ptr) {
+		_rtw_memcpy(ptr, pattrib->dst, ETH_ALEN);
+		_rtw_memcpy(ptr + ETH_ALEN, pattrib->src, ETH_ALEN);
+
+		if (!bsnaphdr) {
+			len = htons(len);
+			_rtw_memcpy(ptr + 12, &len, 2);
+		}
+
+		rtw_rframe_set_os_pkt(precvframe);
+	}
+
+exiting:
+	return ret;
+
+}
+
+#else
+static u8 SNAP_ETH_TYPE_APPLETALK_DDP[2] = {0x80, 0x9b};
+/* Datagram Delivery Protocol */
+static u8 SNAP_HDR_APPLETALK_DDP[3] = {0x08, 0x00, 0x07};
+static u8 oui_8021h[] = {0x00, 0x00, 0xf8};
+static u8 oui_rfc1042[] = {0x00, 0x00, 0x00};
+
+sint wlanhdr_to_ethhdr(union recv_frame *precvframe)
+{
+	sint rmv_len;
+	u16 eth_type;
+	u8	bsnaphdr;
+	u8	*psnap_type;
+	struct ieee80211_snap_hdr	*psnap;
+
+	sint ret = _SUCCESS;
+	_adapter	*adapter = precvframe->u.hdr.adapter;
+	struct	mlme_priv	*pmlmepriv = &adapter->mlmepriv;
+
+	u8 *ptr = get_recvframe_data(precvframe) ; /* point to frame_ctrl field */
+	struct rx_pkt_attrib *pattrib = &precvframe->u.hdr.attrib;
+	struct _vlan *pvlan = NULL;
+
+
+	psnap = (struct ieee80211_snap_hdr *)(ptr + pattrib->hdrlen + pattrib->iv_len);
+	psnap_type = ptr + pattrib->hdrlen + pattrib->iv_len + SNAP_SIZE;
+	if (psnap->dsap == 0xaa && psnap->ssap == 0xaa && psnap->ctrl == 0x03) {
+		if (_rtw_memcmp(psnap->oui, oui_rfc1042, WLAN_IEEE_OUI_LEN))
+			bsnaphdr = _TRUE; /* wlan_pkt_format = WLAN_PKT_FORMAT_SNAP_RFC1042;	 */
+		else if (_rtw_memcmp(psnap->oui, SNAP_HDR_APPLETALK_DDP, WLAN_IEEE_OUI_LEN) &&
+			_rtw_memcmp(psnap_type, SNAP_ETH_TYPE_APPLETALK_DDP, 2))
+			bsnaphdr = _TRUE;	/* wlan_pkt_format = WLAN_PKT_FORMAT_APPLETALK; */
+		else if (_rtw_memcmp(psnap->oui, oui_8021h, WLAN_IEEE_OUI_LEN))
+			bsnaphdr = _TRUE;	/* wlan_pkt_format = WLAN_PKT_FORMAT_SNAP_TUNNEL; */
+		else {
+			ret = _FAIL;
+			goto exit;
+		}
+
+	} else
+		bsnaphdr = _FALSE; /* wlan_pkt_format = WLAN_PKT_FORMAT_OTHERS; */
+
+	rmv_len = pattrib->hdrlen + pattrib->iv_len + (bsnaphdr ? SNAP_SIZE : 0);
+
+	if (check_fwstate(pmlmepriv, WIFI_MP_STATE) == _TRUE) {
+		ptr += rmv_len ;
+		*ptr = 0x87;
+		*(ptr + 1) = 0x12;
+
+		/* back to original pointer */
+		ptr -= rmv_len;
+	}
+
+	ptr += rmv_len ;
+
+	_rtw_memcpy(&eth_type, ptr, 2);
+	eth_type = ntohs((unsigned short)eth_type); /* pattrib->ether_type */
+	ptr += 2;
+
+	if (pattrib->encrypt)
+		recvframe_pull_tail(precvframe, pattrib->icv_len);
+
+	if (eth_type == 0x8100) { /* vlan */
+		pvlan = (struct _vlan *) ptr;
+
+		/* eth_type = get_vlan_encap_proto(pvlan); */
+		/* eth_type = pvlan->h_vlan_encapsulated_proto; */ /* ? */
+		rmv_len += 4;
+		ptr += 4;
+	}
+
+	if (eth_type == 0x0800) { /* ip */
+		/* struct iphdr*  piphdr = (struct iphdr*) ptr; */
+		/* __u8 tos = (unsigned char)(pattrib->priority & 0xff); */
+
+		/* piphdr->tos = tos; */
+
+	} else if (eth_type == 0x8712) { /* append rx status for mp test packets */
+		/* ptr -= 16; */
+		/* _rtw_memcpy(ptr, get_rxmem(precvframe), 16); */
+	} else {
+#ifdef PLATFORM_OS_XP
+		NDIS_PACKET_8021Q_INFO VlanPriInfo;
+		UINT32 UserPriority = precvframe->u.hdr.attrib.priority;
+		UINT32 VlanID = (pvlan != NULL ? get_vlan_id(pvlan) : 0);
+
+		VlanPriInfo.Value =          /* Get current value. */
+			NDIS_PER_PACKET_INFO_FROM_PACKET(precvframe->u.hdr.pkt, Ieee8021QInfo);
+
+		VlanPriInfo.TagHeader.UserPriority = UserPriority;
+		VlanPriInfo.TagHeader.VlanId =  VlanID ;
+
+		VlanPriInfo.TagHeader.CanonicalFormatId = 0; /* Should be zero. */
+		VlanPriInfo.TagHeader.Reserved = 0; /* Should be zero. */
+		NDIS_PER_PACKET_INFO_FROM_PACKET(precvframe->u.hdr.pkt, Ieee8021QInfo) = VlanPriInfo.Value;
+#endif
+	}
+
+	if (eth_type == 0x8712) { /* append rx status for mp test packets */
+		ptr = recvframe_pull(precvframe, (rmv_len - sizeof(struct ethhdr) + 2) - 24);
+		_rtw_memcpy(ptr, get_rxmem(precvframe), 24);
+		ptr += 24;
+	} else
+		ptr = recvframe_pull(precvframe, (rmv_len - sizeof(struct ethhdr) + 2));
+
+	_rtw_memcpy(ptr, pattrib->dst, ETH_ALEN);
+	_rtw_memcpy(ptr + ETH_ALEN, pattrib->src, ETH_ALEN);
+
+	eth_type = htons((unsigned short)eth_type) ;
+	_rtw_memcpy(ptr + 12, &eth_type, 2);
+
+exit:
+
+
+	return ret;
+}
+#endif
+
+
+#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
+#ifdef PLATFORM_LINUX
+static void recvframe_expand_pkt(
+	PADAPTER padapter,
+	union recv_frame *prframe)
+{
+	struct recv_frame_hdr *pfhdr;
+	_pkt *ppkt;
+	u8 shift_sz;
+	u32 alloc_sz;
+	u8 *ptr;
+
+
+	pfhdr = &prframe->u.hdr;
+
+	/*	6 is for IP header 8 bytes alignment in QoS packet case. */
+	if (pfhdr->attrib.qos)
+		shift_sz = 6;
+	else
+		shift_sz = 0;
+
+	/* for first fragment packet, need to allocate */
+	/* (1536 + RXDESC_SIZE + drvinfo_sz) to reassemble packet */
+	/*	8 is for skb->data 8 bytes alignment.
+	*	alloc_sz = _RND(1536 + RXDESC_SIZE + pfhdr->attrib.drvinfosize + shift_sz + 8, 128); */
+	alloc_sz = 1664; /* round (1536 + 24 + 32 + shift_sz + 8) to 128 bytes alignment */
+
+	/* 3 1. alloc new skb */
+	/* prepare extra space for 4 bytes alignment */
+	ppkt = rtw_skb_alloc(alloc_sz);
+
+	if (!ppkt)
+		return; /* no way to expand */
+
+	/* 3 2. Prepare new skb to replace & release old skb */
+	/* force ppkt->data at 8-byte alignment address */
+	skb_reserve(ppkt, 8 - ((SIZE_PTR)ppkt->data & 7));
+	/* force ip_hdr at 8-byte alignment address according to shift_sz */
+	skb_reserve(ppkt, shift_sz);
+
+	/* copy data to new pkt */
+	ptr = skb_put(ppkt, pfhdr->len);
+	if (ptr)
+		_rtw_memcpy(ptr, pfhdr->rx_data, pfhdr->len);
+
+	rtw_skb_free(pfhdr->pkt);
+
+	/* attach new pkt to recvframe */
+	pfhdr->pkt = ppkt;
+	pfhdr->rx_head = ppkt->head;
+	pfhdr->rx_data = ppkt->data;
+	pfhdr->rx_tail = skb_tail_pointer(ppkt);
+	pfhdr->rx_end = skb_end_pointer(ppkt);
+}
+#else
+#warning "recvframe_expand_pkt not implement, defrag may crash system"
+#endif
+#endif
+
+/* perform defrag */
+union recv_frame *recvframe_defrag(_adapter *adapter, _queue *defrag_q);
+union recv_frame *recvframe_defrag(_adapter *adapter, _queue *defrag_q)
+{
+	_list	*plist, *phead;
+	u8	*data, wlanhdr_offset;
+	u8	curfragnum;
+	struct recv_frame_hdr *pfhdr, *pnfhdr;
+	union recv_frame *prframe, *pnextrframe;
+	_queue	*pfree_recv_queue;
+
+
+	curfragnum = 0;
+	pfree_recv_queue = &adapter->recvpriv.free_recv_queue;
+
+	phead = get_list_head(defrag_q);
+	plist = get_next(phead);
+	prframe = LIST_CONTAINOR(plist, union recv_frame, u);
+	pfhdr = &prframe->u.hdr;
+	rtw_list_delete(&(prframe->u.list));
+
+	if (curfragnum != pfhdr->attrib.frag_num) {
+		/* the first fragment number must be 0 */
+		/* free the whole queue */
+		rtw_free_recvframe(prframe, pfree_recv_queue);
+		rtw_free_recvframe_queue(defrag_q, pfree_recv_queue);
+
+		return NULL;
+	}
+
+#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
+#ifndef CONFIG_SDIO_RX_COPY
+	recvframe_expand_pkt(adapter, prframe);
+#endif
+#endif
+
+	curfragnum++;
+
+	plist = get_list_head(defrag_q);
+
+	plist = get_next(plist);
+
+	data = get_recvframe_data(prframe);
+
+	while (rtw_end_of_queue_search(phead, plist) == _FALSE) {
+		pnextrframe = LIST_CONTAINOR(plist, union recv_frame , u);
+		pnfhdr = &pnextrframe->u.hdr;
+
+
+		/* check the fragment sequence  (2nd ~n fragment frame) */
+
+		if (curfragnum != pnfhdr->attrib.frag_num) {
+			/* the fragment number must be increasing  (after decache) */
+			/* release the defrag_q & prframe */
+			rtw_free_recvframe(prframe, pfree_recv_queue);
+			rtw_free_recvframe_queue(defrag_q, pfree_recv_queue);
+			return NULL;
+		}
+
+		curfragnum++;
+
+		/* copy the 2nd~n fragment frame's payload to the first fragment */
+		/* get the 2nd~last fragment frame's payload */
+
+		wlanhdr_offset = pnfhdr->attrib.hdrlen + pnfhdr->attrib.iv_len;
+
+		recvframe_pull(pnextrframe, wlanhdr_offset);
+
+		/* append  to first fragment frame's tail (if privacy frame, pull the ICV) */
+		recvframe_pull_tail(prframe, pfhdr->attrib.icv_len);
+
+		/* memcpy */
+		_rtw_memcpy(pfhdr->rx_tail, pnfhdr->rx_data, pnfhdr->len);
+
+		recvframe_put(prframe, pnfhdr->len);
+
+		pfhdr->attrib.icv_len = pnfhdr->attrib.icv_len;
+		plist = get_next(plist);
+
+	};
+
+	/* free the defrag_q queue and return the prframe */
+	rtw_free_recvframe_queue(defrag_q, pfree_recv_queue);
+
+
+
+	return prframe;
+}
+
+/* check if need to defrag, if needed queue the frame to defrag_q */
+union recv_frame *recvframe_chk_defrag(PADAPTER padapter, union recv_frame *precv_frame)
+{
+	u8	ismfrag;
+	u8	fragnum;
+	u8	*psta_addr;
+	struct recv_frame_hdr *pfhdr;
+	struct sta_info *psta;
+	struct sta_priv *pstapriv;
+	_list *phead;
+	union recv_frame *prtnframe = NULL;
+	_queue *pfree_recv_queue, *pdefrag_q = NULL;
+
+
+	pstapriv = &padapter->stapriv;
+
+	pfhdr = &precv_frame->u.hdr;
+
+	pfree_recv_queue = &padapter->recvpriv.free_recv_queue;
+
+	/* need to define struct of wlan header frame ctrl */
+	ismfrag = pfhdr->attrib.mfrag;
+	fragnum = pfhdr->attrib.frag_num;
+
+	psta_addr = pfhdr->attrib.ta;
+	psta = rtw_get_stainfo(pstapriv, psta_addr);
+	if (psta == NULL) {
+		u8 type = GetFrameType(pfhdr->rx_data);
+		if (type != WIFI_DATA_TYPE) {
+			psta = rtw_get_bcmc_stainfo(padapter);
+			if (psta)
+				pdefrag_q = &psta->sta_recvpriv.defrag_q;
+		} else
+			pdefrag_q = NULL;
+	} else
+		pdefrag_q = &psta->sta_recvpriv.defrag_q;
+
+	if ((ismfrag == 0) && (fragnum == 0)) {
+		prtnframe = precv_frame;/* isn't a fragment frame */
+	}
+
+	if (ismfrag == 1) {
+		/* 0~(n-1) fragment frame */
+		/* enqueue to defraf_g */
+		if (pdefrag_q != NULL) {
+			if (fragnum == 0) {
+				/* the first fragment */
+				if (_rtw_queue_empty(pdefrag_q) == _FALSE) {
+					/* free current defrag_q */
+					rtw_free_recvframe_queue(pdefrag_q, pfree_recv_queue);
+				}
+			}
+
+
+			/* Then enqueue the 0~(n-1) fragment into the defrag_q */
+
+			/* _rtw_spinlock(&pdefrag_q->lock); */
+			phead = get_list_head(pdefrag_q);
+			rtw_list_insert_tail(&pfhdr->list, phead);
+			/* _rtw_spinunlock(&pdefrag_q->lock); */
+
+
+			prtnframe = NULL;
+
+		} else {
+			/* can't find this ta's defrag_queue, so free this recv_frame */
+			rtw_free_recvframe(precv_frame, pfree_recv_queue);
+			prtnframe = NULL;
+		}
+
+	}
+
+	if ((ismfrag == 0) && (fragnum != 0)) {
+		/* the last fragment frame */
+		/* enqueue the last fragment */
+		if (pdefrag_q != NULL) {
+			/* _rtw_spinlock(&pdefrag_q->lock); */
+			phead = get_list_head(pdefrag_q);
+			rtw_list_insert_tail(&pfhdr->list, phead);
+			/* _rtw_spinunlock(&pdefrag_q->lock); */
+
+			/* call recvframe_defrag to defrag */
+			precv_frame = recvframe_defrag(padapter, pdefrag_q);
+			prtnframe = precv_frame;
+
+		} else {
+			/* can't find this ta's defrag_queue, so free this recv_frame */
+			rtw_free_recvframe(precv_frame, pfree_recv_queue);
+			prtnframe = NULL;
+		}
+
+	}
+
+
+	if ((prtnframe != NULL) && (prtnframe->u.hdr.attrib.privacy)) {
+		/* after defrag we must check tkip mic code */
+		if (recvframe_chkmic(padapter,  prtnframe) == _FAIL) {
+			rtw_free_recvframe(prtnframe, pfree_recv_queue);
+			prtnframe = NULL;
+		}
+	}
+
+
+	return prtnframe;
+
+}
+
+static int rtw_recv_indicatepkt_check(union recv_frame *rframe, u8 *ehdr_pos, u32 pkt_len)
+{
+	_adapter *adapter = rframe->u.hdr.adapter;
+	struct recv_priv *recvpriv = &adapter->recvpriv;
+	struct ethhdr *ehdr = (struct ethhdr *)ehdr_pos;
+	int ret = _FAIL;
+
+#ifdef CONFIG_WAPI_SUPPORT
+	if (rtw_wapi_check_for_drop(adapter, rframe, ehdr_pos)) {
+		#ifdef DBG_RX_DROP_FRAME
+		RTW_INFO("DBG_RX_DROP_FRAME "FUNC_ADPT_FMT" rtw_wapi_check_for_drop\n"
+			, FUNC_ADPT_ARG(adapter));
+		#endif
+		goto exit;
+	}
+#endif
+
+	if (rframe->u.hdr.psta)
+		rtw_st_ctl_rx(rframe->u.hdr.psta, ehdr_pos);
+
+	if (ntohs(ehdr->h_proto) == 0x888e)
+		parsing_eapol_packet(adapter, ehdr_pos + ETH_HLEN, rframe->u.hdr.psta, 0);
+#ifdef DBG_ARP_DUMP
+	else if (ntohs(ehdr->h_proto) == ETH_P_ARP)
+		dump_arp_pkt(RTW_DBGDUMP, ehdr->h_dest, ehdr->h_source, ehdr_pos + ETH_HLEN, 0);
+#endif
+
+	if (recvpriv->sink_udpport > 0)
+		rtw_sink_rtp_seq_dbg(adapter, ehdr_pos);
+
+#ifdef DBG_UDP_PKT_LOSE_11AC
+	#define PAYLOAD_LEN_LOC_OF_IP_HDR 0x10 /*ethernet payload length location of ip header (DA + SA+eth_type+(version&hdr_len)) */
+
+	if (ntohs(ehdr->h_proto) == ETH_P_ARP) {
+		/* ARP Payload length will be 42bytes or 42+18(tailer)=60bytes*/
+		if (pkt_len != 42 && pkt_len != 60)
+			RTW_INFO("Error !!%s,ARP Payload length %u not correct\n" , __func__ , pkt_len);
+	} else if (ntohs(ehdr->h_proto) == ETH_P_IP) {
+		if (be16_to_cpu(*((u16 *)(ehdr_pos + PAYLOAD_LEN_LOC_OF_IP_HDR))) != (pkt_len) - ETH_HLEN) {
+			RTW_INFO("Error !!%s,Payload length not correct\n" , __func__);
+			RTW_INFO("%s, IP header describe Total length=%u\n" , __func__ , be16_to_cpu(*((u16 *)(ehdr_pos + PAYLOAD_LEN_LOC_OF_IP_HDR))));
+			RTW_INFO("%s, Pkt real length=%u\n" , __func__ , (pkt_len) - ETH_HLEN);
+		}
+	}
+#endif
+
+#ifdef CONFIG_AUTO_AP_MODE
+	if (ntohs(ehdr->h_proto) == 0x8899)
+		rtw_auto_ap_rx_msg_dump(adapter, rframe, ehdr_pos);
+#endif
+
+	ret = _SUCCESS;
+
+#ifdef CONFIG_WAPI_SUPPORT
+exit:
+#endif
+	return ret;
+}
+
+static void recv_free_fwd_resource(_adapter *adapter, struct xmit_frame *fwd_frame, _list *b2u_list)
+{
+	struct xmit_priv *xmitpriv = &adapter->xmitpriv;
+
+	if (fwd_frame)
+		rtw_free_xmitframe(xmitpriv, fwd_frame);
+
+#ifdef CONFIG_RTW_MESH
+#if CONFIG_RTW_MESH_DATA_BMC_TO_UC
+	if (!rtw_is_list_empty(b2u_list)) {
+		struct xmit_frame *b2uframe;
+		_list *list;
+
+		list = get_next(b2u_list);
+		while (rtw_end_of_queue_search(b2u_list, list) == _FALSE) {
+			b2uframe = LIST_CONTAINOR(list, struct xmit_frame, list);
+			list = get_next(list);
+			rtw_list_delete(&b2uframe->list);
+			rtw_free_xmitframe(xmitpriv, b2uframe);
+		}
+	}
+#endif
+#endif /* CONFIG_RTW_MESH */
+}
+
+#ifdef CONFIG_RTW_MESH
+static void recv_fwd_pkt_hdl(_adapter *adapter, _pkt *pkt
+	, u8 act, struct xmit_frame *fwd_frame, _list *b2u_list)
+{
+	struct xmit_priv *xmitpriv = &adapter->xmitpriv;
+	_pkt *fwd_pkt = pkt;
+
+	if (act & RTW_RX_MSDU_ACT_INDICATE) {
+		fwd_pkt = rtw_os_pkt_copy(pkt);
+		if (!fwd_pkt) {
+			#ifdef DBG_TX_DROP_FRAME
+			RTW_INFO("DBG_TX_DROP_FRAME %s rtw_os_pkt_copy fail\n", __func__);
+			#endif
+			recv_free_fwd_resource(adapter, fwd_frame, b2u_list);
+			goto exit;
+		}
+	}
+
+#if CONFIG_RTW_MESH_DATA_BMC_TO_UC
+	if (!rtw_is_list_empty(b2u_list)) {
+		_list *list = get_next(b2u_list);
+		struct xmit_frame *b2uframe;
+
+		while (rtw_end_of_queue_search(b2u_list, list) == _FALSE) {
+			b2uframe = LIST_CONTAINOR(list, struct xmit_frame, list);
+			list = get_next(list);
+			rtw_list_delete(&b2uframe->list);
+
+			if (!fwd_frame && rtw_is_list_empty(b2u_list)) /* the last fwd_pkt */
+				b2uframe->pkt = fwd_pkt;
+			else
+				b2uframe->pkt = rtw_os_pkt_copy(fwd_pkt);
+			if (!b2uframe->pkt) {
+				rtw_free_xmitframe(xmitpriv, b2uframe);
+				continue;
+			}
+
+			rtw_xmit_posthandle(adapter, b2uframe, b2uframe->pkt);
+		}
+	}
+#endif
+
+	if (fwd_frame) {
+		fwd_frame->pkt = fwd_pkt;
+		if (rtw_xmit_posthandle(adapter, fwd_frame, fwd_pkt) < 0) {
+			#ifdef DBG_TX_DROP_FRAME
+			RTW_INFO("DBG_TX_DROP_FRAME %s rtw_xmit_posthandle fail\n", __func__);
+			#endif
+			xmitpriv->tx_drop++;
+		}
+	}
+
+exit:
+	return;
+}
+#endif /* CONFIG_RTW_MESH */
+
+int amsdu_to_msdu(_adapter *padapter, union recv_frame *prframe)
+{
+	struct rx_pkt_attrib *rattrib = &prframe->u.hdr.attrib;
+	int	a_len, padding_len;
+	u16	nSubframe_Length;
+	u8	nr_subframes, i;
+	u8	*pdata;
+	_pkt *sub_pkt, *subframes[MAX_SUBFRAME_COUNT];
+	struct recv_priv *precvpriv = &padapter->recvpriv;
+	_queue *pfree_recv_queue = &(precvpriv->free_recv_queue);
+	const u8 *da, *sa;
+	int act;
+	struct xmit_frame *fwd_frame;
+	_list b2u_list;
+	u8 mctrl_len = 0;
+	int	ret = _SUCCESS;
+
+	nr_subframes = 0;
+
+	recvframe_pull(prframe, rattrib->hdrlen);
+
+	if (rattrib->iv_len > 0)
+		recvframe_pull(prframe, rattrib->iv_len);
+
+	a_len = prframe->u.hdr.len;
+	pdata = prframe->u.hdr.rx_data;
+
+	while (a_len > ETH_HLEN) {
+		/* Offset 12 denote 2 mac address */
+		nSubframe_Length = RTW_GET_BE16(pdata + 12);
+		if (a_len < (ETHERNET_HEADER_SIZE + nSubframe_Length)) {
+			RTW_INFO("nRemain_Length is %d and nSubframe_Length is : %d\n", a_len, nSubframe_Length);
+			break;
+		}
+
+		act = RTW_RX_MSDU_ACT_INDICATE;
+		fwd_frame = NULL;
+
+		#ifdef CONFIG_RTW_MESH
+		if (MLME_IS_MESH(padapter)) {
+			u8 *mda = pdata, *msa = pdata + ETH_ALEN;
+			struct rtw_ieee80211s_hdr *mctrl = (struct rtw_ieee80211s_hdr *)(pdata + ETH_HLEN);
+			int v_ret;
+
+			v_ret = rtw_mesh_rx_data_validate_mctrl(padapter, prframe
+				, mctrl, mda, msa, &mctrl_len, &da, &sa);
+			if (v_ret != _SUCCESS)
+				goto move_to_next;
+
+			act = rtw_mesh_rx_msdu_act_check(prframe
+				, mda, msa, da, sa, mctrl, &fwd_frame, &b2u_list);
+		} else
+		#endif
+		{
+			da = pdata;
+			sa = pdata + ETH_ALEN;
+		}
+
+		if (!act)
+			goto move_to_next;
+
+		rtw_led_rx_control(padapter, da);
+
+		sub_pkt = rtw_os_alloc_msdu_pkt(prframe, da, sa
+			, pdata + ETH_HLEN + mctrl_len, nSubframe_Length - mctrl_len);
+		if (sub_pkt == NULL) {
+			if (act & RTW_RX_MSDU_ACT_INDICATE) {
+				#ifdef DBG_RX_DROP_FRAME
+				RTW_INFO("DBG_RX_DROP_FRAME %s rtw_os_alloc_msdu_pkt fail\n", __func__);
+				#endif
+			}
+			if (act & RTW_RX_MSDU_ACT_FORWARD) {
+				#ifdef DBG_TX_DROP_FRAME
+				RTW_INFO("DBG_TX_DROP_FRAME %s rtw_os_alloc_msdu_pkt fail\n", __func__);
+				#endif
+				recv_free_fwd_resource(padapter, fwd_frame, &b2u_list);
+			}
+			break;
+		}
+
+		#ifdef CONFIG_RTW_MESH
+		if (act & RTW_RX_MSDU_ACT_FORWARD) {
+			recv_fwd_pkt_hdl(padapter, sub_pkt, act, fwd_frame, &b2u_list);
+			if (!(act & RTW_RX_MSDU_ACT_INDICATE))
+				goto move_to_next;
+		}
+		#endif
+
+		if (rtw_recv_indicatepkt_check(prframe, rtw_os_pkt_data(sub_pkt), rtw_os_pkt_len(sub_pkt)) == _SUCCESS)
+			subframes[nr_subframes++] = sub_pkt;
+		else
+			rtw_os_pkt_free(sub_pkt);
+
+move_to_next:
+		/* move the data point to data content */
+		pdata += ETH_HLEN;
+		a_len -= ETH_HLEN;
+
+		if (nr_subframes >= MAX_SUBFRAME_COUNT) {
+			RTW_WARN("ParseSubframe(): Too many Subframes! Packets dropped!\n");
+			break;
+		}
+
+		pdata += nSubframe_Length;
+		a_len -= nSubframe_Length;
+		if (a_len != 0) {
+			padding_len = 4 - ((nSubframe_Length + ETH_HLEN) & (4 - 1));
+			if (padding_len == 4)
+				padding_len = 0;
+
+			if (a_len < padding_len) {
+				RTW_INFO("ParseSubframe(): a_len < padding_len !\n");
+				break;
+			}
+			pdata += padding_len;
+			a_len -= padding_len;
+		}
+	}
+
+	for (i = 0; i < nr_subframes; i++) {
+		sub_pkt = subframes[i];
+
+		/* Indicat the packets to upper layer */
+		if (sub_pkt)
+			rtw_os_recv_indicate_pkt(padapter, sub_pkt, prframe);
+	}
+
+	prframe->u.hdr.len = 0;
+	rtw_free_recvframe(prframe, pfree_recv_queue);/* free this recv_frame */
+
+	return ret;
+}
+
+static int recv_process_mpdu(_adapter *padapter, union recv_frame *prframe)
+{
+	_queue *pfree_recv_queue = &padapter->recvpriv.free_recv_queue;
+	struct rx_pkt_attrib *pattrib = &prframe->u.hdr.attrib;
+	int ret;
+
+	if (pattrib->amsdu) {
+		ret = amsdu_to_msdu(padapter, prframe);
+		if (ret != _SUCCESS) {
+			#ifdef DBG_RX_DROP_FRAME
+			RTW_INFO("DBG_RX_DROP_FRAME "FUNC_ADPT_FMT" amsdu_to_msdu fail\n"
+				, FUNC_ADPT_ARG(padapter));
+			#endif
+			rtw_free_recvframe(prframe, pfree_recv_queue);
+			goto exit;
+		}
+	} else {
+		int act = RTW_RX_MSDU_ACT_INDICATE;
+		struct xmit_frame *fwd_frame = NULL;
+		_list b2u_list;
+
+		#ifdef CONFIG_RTW_MESH
+		if (MLME_IS_MESH(padapter) && pattrib->mesh_ctrl_present) {
+			act = rtw_mesh_rx_msdu_act_check(prframe
+				, pattrib->mda, pattrib->msa
+				, pattrib->dst, pattrib->src
+				, (struct rtw_ieee80211s_hdr *)(get_recvframe_data(prframe) + pattrib->hdrlen + pattrib->iv_len)
+				, &fwd_frame, &b2u_list);
+		}
+		#endif
+
+		if (!act) {
+			rtw_free_recvframe(prframe, pfree_recv_queue);
+			ret = _FAIL;
+			goto exit;
+		}
+
+		rtw_led_rx_control(padapter, pattrib->dst);
+
+		ret = wlanhdr_to_ethhdr(prframe);
+		if (ret != _SUCCESS) {
+			if (act & RTW_RX_MSDU_ACT_INDICATE) {
+				#ifdef DBG_RX_DROP_FRAME
+				RTW_INFO("DBG_RX_DROP_FRAME "FUNC_ADPT_FMT" wlanhdr_to_ethhdr: drop pkt\n"
+					, FUNC_ADPT_ARG(padapter));
+				#endif
+			}
+			if (act & RTW_RX_MSDU_ACT_FORWARD) {
+				#ifdef DBG_TX_DROP_FRAME
+				RTW_INFO("DBG_TX_DROP_FRAME %s wlanhdr_to_ethhdr fail\n", __func__);
+				#endif
+				recv_free_fwd_resource(padapter, fwd_frame, &b2u_list);
+			}
+			rtw_free_recvframe(prframe, pfree_recv_queue);
+			goto exit;
+		}
+
+		#ifdef CONFIG_RTW_MESH
+		if (act & RTW_RX_MSDU_ACT_FORWARD) {
+			recv_fwd_pkt_hdl(padapter, prframe->u.hdr.pkt, act, fwd_frame, &b2u_list);
+			if (!(act & RTW_RX_MSDU_ACT_INDICATE)) {
+				prframe->u.hdr.pkt = NULL;
+				rtw_free_recvframe(prframe, pfree_recv_queue);
+				goto exit;
+			}
+		}
+		#endif
+
+		if (!RTW_CANNOT_RUN(padapter)) {
+			ret = rtw_recv_indicatepkt_check(prframe
+				, get_recvframe_data(prframe), get_recvframe_len(prframe));
+			if (ret != _SUCCESS) {
+				rtw_free_recvframe(prframe, pfree_recv_queue);
+				goto exit;
+			}
+
+			/* indicate this recv_frame */
+			ret = rtw_recv_indicatepkt(padapter, prframe);
+			if (ret != _SUCCESS) {
+				#ifdef DBG_RX_DROP_FRAME
+				RTW_INFO("DBG_RX_DROP_FRAME "FUNC_ADPT_FMT" rtw_recv_indicatepkt fail!\n"
+					, FUNC_ADPT_ARG(padapter));
+				#endif
+				goto exit;
+			}
+		} else {
+			#ifdef DBG_RX_DROP_FRAME
+			RTW_INFO("DBG_RX_DROP_FRAME "FUNC_ADPT_FMT" DS:%u SR:%u\n"
+				, FUNC_ADPT_ARG(padapter)
+				, rtw_is_drv_stopped(padapter)
+				, rtw_is_surprise_removed(padapter));
+			#endif
+			ret = _SUCCESS; /* don't count as packet drop */
+			rtw_free_recvframe(prframe, pfree_recv_queue);
+		}
+	}
+
+exit:
+	return ret;
+}
+
+#if defined(CONFIG_80211N_HT) && defined(CONFIG_RECV_REORDERING_CTRL)
+static int check_indicate_seq(struct recv_reorder_ctrl *preorder_ctrl, u16 seq_num)
+{
+	PADAPTER padapter = preorder_ctrl->padapter;
+	struct recv_priv  *precvpriv = &padapter->recvpriv;
+	u8	wsize = preorder_ctrl->wsize_b;
+	u16	wend = (preorder_ctrl->indicate_seq + wsize - 1) & 0xFFF; /* % 4096; */
+
+	/* Rx Reorder initialize condition. */
+	if (preorder_ctrl->indicate_seq == 0xFFFF) {
+		preorder_ctrl->indicate_seq = seq_num;
+		#ifdef DBG_RX_SEQ
+		RTW_INFO("DBG_RX_SEQ "FUNC_ADPT_FMT" tid:%u SN_INIT indicate_seq:%d, seq_num:%d\n"
+			, FUNC_ADPT_ARG(padapter), preorder_ctrl->tid, preorder_ctrl->indicate_seq, seq_num);
+		#endif
+	}
+
+	/* Drop out the packet which SeqNum is smaller than WinStart */
+	if (SN_LESS(seq_num, preorder_ctrl->indicate_seq)) {
+		#ifdef DBG_RX_DROP_FRAME
+		RTW_INFO(FUNC_ADPT_FMT" tid:%u indicate_seq:%d > seq_num:%d\n"
+			, FUNC_ADPT_ARG(padapter), preorder_ctrl->tid, preorder_ctrl->indicate_seq, seq_num);
+		#endif
+		return _FALSE;
+	}
+
+	/*
+	* Sliding window manipulation. Conditions includes:
+	* 1. Incoming SeqNum is equal to WinStart =>Window shift 1
+	* 2. Incoming SeqNum is larger than the WinEnd => Window shift N
+	*/
+	if (SN_EQUAL(seq_num, preorder_ctrl->indicate_seq)) {
+		preorder_ctrl->indicate_seq = (preorder_ctrl->indicate_seq + 1) & 0xFFF;
+		#ifdef DBG_RX_SEQ
+		RTW_INFO("DBG_RX_SEQ "FUNC_ADPT_FMT" tid:%u SN_EQUAL indicate_seq:%d, seq_num:%d\n"
+			, FUNC_ADPT_ARG(padapter), preorder_ctrl->tid, preorder_ctrl->indicate_seq, seq_num);
+		#endif
+
+	} else if (SN_LESS(wend, seq_num)) {
+		/* boundary situation, when seq_num cross 0xFFF */
+		if (seq_num >= (wsize - 1))
+			preorder_ctrl->indicate_seq = seq_num + 1 - wsize;
+		else
+			preorder_ctrl->indicate_seq = 0xFFF - (wsize - (seq_num + 1)) + 1;
+
+		precvpriv->dbg_rx_ampdu_window_shift_cnt++;
+		#ifdef DBG_RX_SEQ
+		RTW_INFO("DBG_RX_SEQ "FUNC_ADPT_FMT" tid:%u SN_LESS(wend, seq_num) indicate_seq:%d, seq_num:%d\n"
+			, FUNC_ADPT_ARG(padapter), preorder_ctrl->tid, preorder_ctrl->indicate_seq, seq_num);
+		#endif
+	}
+
+	return _TRUE;
+}
+
+static int enqueue_reorder_recvframe(struct recv_reorder_ctrl *preorder_ctrl, union recv_frame *prframe)
+{
+	struct rx_pkt_attrib *pattrib = &prframe->u.hdr.attrib;
+	_queue *ppending_recvframe_queue = &preorder_ctrl->pending_recvframe_queue;
+	_list	*phead, *plist;
+	union recv_frame *pnextrframe;
+	struct rx_pkt_attrib *pnextattrib;
+
+	/* DbgPrint("+enqueue_reorder_recvframe()\n"); */
+
+	/* _enter_critical_ex(&ppending_recvframe_queue->lock, &irql); */
+	/* _rtw_spinlock_ex(&ppending_recvframe_queue->lock); */
+
+
+	phead = get_list_head(ppending_recvframe_queue);
+	plist = get_next(phead);
+
+	while (rtw_end_of_queue_search(phead, plist) == _FALSE) {
+		pnextrframe = LIST_CONTAINOR(plist, union recv_frame, u);
+		pnextattrib = &pnextrframe->u.hdr.attrib;
+
+		if (SN_LESS(pnextattrib->seq_num, pattrib->seq_num))
+			plist = get_next(plist);
+		else if (SN_EQUAL(pnextattrib->seq_num, pattrib->seq_num)) {
+			/* Duplicate entry is found!! Do not insert current entry. */
+
+			/* _exit_critical_ex(&ppending_recvframe_queue->lock, &irql); */
+
+			return _FALSE;
+		} else
+			break;
+
+		/* DbgPrint("enqueue_reorder_recvframe():while\n"); */
+
+	}
+
+
+	/* _enter_critical_ex(&ppending_recvframe_queue->lock, &irql); */
+	/* _rtw_spinlock_ex(&ppending_recvframe_queue->lock); */
+
+	rtw_list_delete(&(prframe->u.hdr.list));
+
+	rtw_list_insert_tail(&(prframe->u.hdr.list), plist);
+
+	/* _rtw_spinunlock_ex(&ppending_recvframe_queue->lock); */
+	/* _exit_critical_ex(&ppending_recvframe_queue->lock, &irql); */
+
+
+	return _TRUE;
+
+}
+
+static void recv_indicatepkts_pkt_loss_cnt(_adapter *padapter, u64 prev_seq, u64 current_seq)
+{
+	struct recv_priv *precvpriv = &padapter->recvpriv;
+
+	if (current_seq < prev_seq) {
+		precvpriv->dbg_rx_ampdu_loss_count += (4096 + current_seq - prev_seq);
+		precvpriv->rx_drop += (4096 + current_seq - prev_seq);
+	} else {
+		precvpriv->dbg_rx_ampdu_loss_count += (current_seq - prev_seq);
+		precvpriv->rx_drop += (current_seq - prev_seq);
+	}
+}
+
+static int recv_indicatepkts_in_order(_adapter *padapter, struct recv_reorder_ctrl *preorder_ctrl, int bforced)
+{
+	/* _irqL irql; */
+	_list	*phead, *plist;
+	union recv_frame *prframe;
+	struct rx_pkt_attrib *pattrib;
+	/* u8 index = 0; */
+	int bPktInBuf = _FALSE;
+	struct recv_priv *precvpriv = &padapter->recvpriv;
+	_queue *ppending_recvframe_queue = &preorder_ctrl->pending_recvframe_queue;
+
+	DBG_COUNTER(padapter->rx_logs.core_rx_post_indicate_in_oder);
+
+	/* DbgPrint("+recv_indicatepkts_in_order\n"); */
+
+	/* _enter_critical_ex(&ppending_recvframe_queue->lock, &irql); */
+	/* _rtw_spinlock_ex(&ppending_recvframe_queue->lock); */
+
+	phead =	get_list_head(ppending_recvframe_queue);
+	plist = get_next(phead);
+
+#if 0
+	/* Check if there is any other indication thread running. */
+	if (pTS->RxIndicateState == RXTS_INDICATE_PROCESSING)
+		return;
+#endif
+
+	/* Handling some condition for forced indicate case. */
+	if (bforced == _TRUE) {
+		precvpriv->dbg_rx_ampdu_forced_indicate_count++;
+		if (rtw_is_list_empty(phead)) {
+			/* _exit_critical_ex(&ppending_recvframe_queue->lock, &irql); */
+			/* _rtw_spinunlock_ex(&ppending_recvframe_queue->lock); */
+			return _TRUE;
+		}
+
+		prframe = LIST_CONTAINOR(plist, union recv_frame, u);
+		pattrib = &prframe->u.hdr.attrib;
+
+		#ifdef DBG_RX_SEQ
+		RTW_INFO("DBG_RX_SEQ "FUNC_ADPT_FMT" tid:%u FORCE indicate_seq:%d, seq_num:%d\n"
+			, FUNC_ADPT_ARG(padapter), preorder_ctrl->tid, preorder_ctrl->indicate_seq, pattrib->seq_num);
+		#endif
+		recv_indicatepkts_pkt_loss_cnt(padapter, preorder_ctrl->indicate_seq, pattrib->seq_num);
+		preorder_ctrl->indicate_seq = pattrib->seq_num;
+	}
+
+	/* Prepare indication list and indication. */
+	/* Check if there is any packet need indicate. */
+	while (!rtw_is_list_empty(phead)) {
+
+		prframe = LIST_CONTAINOR(plist, union recv_frame, u);
+		pattrib = &prframe->u.hdr.attrib;
+
+		if (!SN_LESS(preorder_ctrl->indicate_seq, pattrib->seq_num)) {
+
+#if 0
+			/* This protect buffer from overflow. */
+			if (index >= REORDER_WIN_SIZE) {
+				RT_ASSERT(FALSE, ("IndicateRxReorderList(): Buffer overflow!!\n"));
+				bPktInBuf = TRUE;
+				break;
+			}
+#endif
+
+			plist = get_next(plist);
+			rtw_list_delete(&(prframe->u.hdr.list));
+
+			if (SN_EQUAL(preorder_ctrl->indicate_seq, pattrib->seq_num)) {
+				preorder_ctrl->indicate_seq = (preorder_ctrl->indicate_seq + 1) & 0xFFF;
+				#ifdef DBG_RX_SEQ
+				RTW_INFO("DBG_RX_SEQ "FUNC_ADPT_FMT" tid:%u SN_EQUAL indicate_seq:%d, seq_num:%d\n"
+					, FUNC_ADPT_ARG(padapter), preorder_ctrl->tid, preorder_ctrl->indicate_seq, pattrib->seq_num);
+				#endif
+			}
+
+#if 0
+			index++;
+			if (index == 1) {
+				/* Cancel previous pending timer. */
+				/* PlatformCancelTimer(Adapter, &pTS->RxPktPendingTimer); */
+				if (bforced != _TRUE) {
+					/* RTW_INFO("_cancel_timer_ex(&preorder_ctrl->reordering_ctrl_timer);\n"); */
+					_cancel_timer_ex(&preorder_ctrl->reordering_ctrl_timer);
+				}
+			}
+#endif
+
+			/* Set this as a lock to make sure that only one thread is indicating packet. */
+			/* pTS->RxIndicateState = RXTS_INDICATE_PROCESSING; */
+
+			/* Indicate packets */
+			/* RT_ASSERT((index<=REORDER_WIN_SIZE), ("RxReorderIndicatePacket(): Rx Reorder buffer full!!\n")); */
+
+
+			/* indicate this recv_frame */
+			/* DbgPrint("recv_indicatepkts_in_order, indicate_seq=%d, seq_num=%d\n", precvpriv->indicate_seq, pattrib->seq_num); */
+			if (recv_process_mpdu(padapter, prframe) != _SUCCESS)
+				precvpriv->dbg_rx_drop_count++;
+
+			/* Update local variables. */
+			bPktInBuf = _FALSE;
+
+		} else {
+			bPktInBuf = _TRUE;
+			break;
+		}
+
+		/* DbgPrint("recv_indicatepkts_in_order():while\n"); */
+
+	}
+
+	/* _rtw_spinunlock_ex(&ppending_recvframe_queue->lock); */
+	/* _exit_critical_ex(&ppending_recvframe_queue->lock, &irql); */
+
+#if 0
+	/* Release the indication lock and set to new indication step. */
+	if (bPktInBuf) {
+		/*  Set new pending timer. */
+		/* pTS->RxIndicateState = RXTS_INDICATE_REORDER; */
+		/* PlatformSetTimer(Adapter, &pTS->RxPktPendingTimer, pHTInfo->RxReorderPendingTime); */
+
+		_set_timer(&preorder_ctrl->reordering_ctrl_timer, REORDER_WAIT_TIME);
+	} else {
+		/* pTS->RxIndicateState = RXTS_INDICATE_IDLE; */
+	}
+#endif
+	/* _exit_critical_ex(&ppending_recvframe_queue->lock, &irql); */
+
+	/* return _TRUE; */
+	return bPktInBuf;
+
+}
+
+static int recv_indicatepkt_reorder(_adapter *padapter, union recv_frame *prframe)
+{
+	_irqL irql;
+	struct rx_pkt_attrib *pattrib = &prframe->u.hdr.attrib;
+	struct recv_reorder_ctrl *preorder_ctrl = prframe->u.hdr.preorder_ctrl;
+	_queue *ppending_recvframe_queue = preorder_ctrl ? &preorder_ctrl->pending_recvframe_queue : NULL;
+	struct recv_priv  *precvpriv = &padapter->recvpriv;
+
+	if (!pattrib->qos || !preorder_ctrl || preorder_ctrl->enable == _FALSE)
+		goto _success_exit;
+
+	DBG_COUNTER(padapter->rx_logs.core_rx_post_indicate_reoder);
+
+	_enter_critical_bh(&ppending_recvframe_queue->lock, &irql);
+
+	/* s2. check if winstart_b(indicate_seq) needs to been updated */
+	if (!check_indicate_seq(preorder_ctrl, pattrib->seq_num)) {
+		precvpriv->dbg_rx_ampdu_drop_count++;
+		/* pHTInfo->RxReorderDropCounter++; */
+		/* ReturnRFDList(Adapter, pRfd); */
+		/* _exit_critical_ex(&ppending_recvframe_queue->lock, &irql); */
+		/* return _FAIL; */
+
+		#ifdef DBG_RX_DROP_FRAME
+		RTW_INFO("DBG_RX_DROP_FRAME "FUNC_ADPT_FMT" check_indicate_seq fail\n"
+			, FUNC_ADPT_ARG(padapter));
+		#endif
+#if 0
+		rtw_recv_indicatepkt(padapter, prframe);
+
+		_exit_critical_bh(&ppending_recvframe_queue->lock, &irql);
+
+		goto _success_exit;
+#else
+		goto _err_exit;
+#endif
+	}
+
+
+	/* s3. Insert all packet into Reorder Queue to maintain its ordering. */
+	if (!enqueue_reorder_recvframe(preorder_ctrl, prframe)) {
+		/* DbgPrint("recv_indicatepkt_reorder, enqueue_reorder_recvframe fail!\n"); */
+		/* _exit_critical_ex(&ppending_recvframe_queue->lock, &irql); */
+		/* return _FAIL; */
+		#ifdef DBG_RX_DROP_FRAME
+		RTW_INFO("DBG_RX_DROP_FRAME "FUNC_ADPT_FMT" enqueue_reorder_recvframe fail\n"
+			, FUNC_ADPT_ARG(padapter));
+		#endif
+		goto _err_exit;
+	}
+
+
+	/* s4. */
+	/* Indication process. */
+	/* After Packet dropping and Sliding Window shifting as above, we can now just indicate the packets */
+	/* with the SeqNum smaller than latest WinStart and buffer other packets. */
+	/*  */
+	/* For Rx Reorder condition: */
+	/* 1. All packets with SeqNum smaller than WinStart => Indicate */
+	/* 2. All packets with SeqNum larger than or equal to WinStart => Buffer it. */
+	/*  */
+
+	/* recv_indicatepkts_in_order(padapter, preorder_ctrl, _TRUE); */
+	if (recv_indicatepkts_in_order(padapter, preorder_ctrl, _FALSE) == _TRUE) {
+		if (!preorder_ctrl->bReorderWaiting) {
+			preorder_ctrl->bReorderWaiting = _TRUE;
+			_set_timer(&preorder_ctrl->reordering_ctrl_timer, REORDER_WAIT_TIME);
+		}
+		_exit_critical_bh(&ppending_recvframe_queue->lock, &irql);
+	} else {
+		preorder_ctrl->bReorderWaiting = _FALSE;
+		_exit_critical_bh(&ppending_recvframe_queue->lock, &irql);
+		_cancel_timer_ex(&preorder_ctrl->reordering_ctrl_timer);
+	}
+
+	return RTW_RX_HANDLED;
+
+_success_exit:
+
+	return _SUCCESS;
+
+_err_exit:
+
+	_exit_critical_bh(&ppending_recvframe_queue->lock, &irql);
+
+	return _FAIL;
+}
+
+
+void rtw_reordering_ctrl_timeout_handler(void *pcontext)
+{
+	_irqL irql;
+	struct recv_reorder_ctrl *preorder_ctrl = (struct recv_reorder_ctrl *)pcontext;
+	_adapter *padapter = preorder_ctrl->padapter;
+	_queue *ppending_recvframe_queue = &preorder_ctrl->pending_recvframe_queue;
+
+
+	if (RTW_CANNOT_RUN(padapter))
+		return;
+
+	/* RTW_INFO("+rtw_reordering_ctrl_timeout_handler()=>\n"); */
+
+	_enter_critical_bh(&ppending_recvframe_queue->lock, &irql);
+
+	if (preorder_ctrl)
+		preorder_ctrl->bReorderWaiting = _FALSE;
+
+	if (recv_indicatepkts_in_order(padapter, preorder_ctrl, _TRUE) == _TRUE)
+		_set_timer(&preorder_ctrl->reordering_ctrl_timer, REORDER_WAIT_TIME);
+
+	_exit_critical_bh(&ppending_recvframe_queue->lock, &irql);
+
+}
+#endif /* defined(CONFIG_80211N_HT) && defined(CONFIG_RECV_REORDERING_CTRL) */
+
+static void recv_set_iseq_before_mpdu_process(union recv_frame *rframe, u16 seq_num, const char *caller)
+{
+#if defined(CONFIG_80211N_HT) && defined(CONFIG_RECV_REORDERING_CTRL)
+	struct recv_reorder_ctrl *reorder_ctrl = rframe->u.hdr.preorder_ctrl;
+
+	if (reorder_ctrl) {
+		reorder_ctrl->indicate_seq = seq_num;
+		#ifdef DBG_RX_SEQ
+		RTW_INFO("DBG_RX_SEQ %s("ADPT_FMT")-B tid:%u indicate_seq:%d, seq_num:%d\n"
+			, caller, ADPT_ARG(reorder_ctrl->padapter)
+			, reorder_ctrl->tid, reorder_ctrl->indicate_seq, seq_num);
+		#endif
+	}
+#endif
+}
+
+static void recv_set_iseq_after_mpdu_process(union recv_frame *rframe, u16 seq_num, const char *caller)
+{
+#if defined(CONFIG_80211N_HT) && defined(CONFIG_RECV_REORDERING_CTRL)
+	struct recv_reorder_ctrl *reorder_ctrl = rframe->u.hdr.preorder_ctrl;
+
+	if (reorder_ctrl) {
+		reorder_ctrl->indicate_seq = (reorder_ctrl->indicate_seq + 1) % 4096;
+		#ifdef DBG_RX_SEQ
+		RTW_INFO("DBG_RX_SEQ %s("ADPT_FMT")-A tid:%u indicate_seq:%d, seq_num:%d\n"
+			, caller, ADPT_ARG(reorder_ctrl->padapter)
+			, reorder_ctrl->tid, reorder_ctrl->indicate_seq, seq_num);
+		#endif
+	}
+#endif
+}
+
+#ifdef CONFIG_MP_INCLUDED
+int validate_mp_recv_frame(_adapter *adapter, union recv_frame *precv_frame)
+{
+	int ret = _SUCCESS;
+	u8 *ptr = precv_frame->u.hdr.rx_data;
+	u8 type, subtype;
+	struct mp_priv *pmppriv = &adapter->mppriv;
+	struct mp_tx		*pmptx;
+	unsigned char	*sa , *da, *bs;
+
+	pmptx = &pmppriv->tx;
+
+#if 0
+	if (1) {
+		u8 bDumpRxPkt;
+		type =  GetFrameType(ptr);
+		subtype = get_frame_sub_type(ptr); /* bit(7)~bit(2)	 */
+
+		rtw_hal_get_def_var(adapter, HAL_DEF_DBG_DUMP_RXPKT, &(bDumpRxPkt));
+		if (bDumpRxPkt == 1) { /* dump all rx packets */
+			int i;
+			RTW_INFO("############ type:0x%02x subtype:0x%02x #################\n", type, subtype);
+
+			for (i = 0; i < 64; i = i + 8)
+				RTW_INFO("%02X:%02X:%02X:%02X:%02X:%02X:%02X:%02X:\n", *(ptr + i),
+					*(ptr + i + 1), *(ptr + i + 2) , *(ptr + i + 3) , *(ptr + i + 4), *(ptr + i + 5), *(ptr + i + 6), *(ptr + i + 7));
+			RTW_INFO("#############################\n");
+		}
+	}
+#endif
+	if (pmppriv->bloopback) {
+		if (_rtw_memcmp(ptr + 24, pmptx->buf + 24, precv_frame->u.hdr.len - 24) == _FALSE) {
+			RTW_INFO("Compare payload content Fail !!!\n");
+			ret = _FAIL;
+		}
+	}
+ 	if (pmppriv->bSetRxBssid == _TRUE) {
+
+		sa = get_addr2_ptr(ptr);
+		da = GetAddr1Ptr(ptr);
+		bs = GetAddr3Ptr(ptr);
+		type =	GetFrameType(ptr);
+		subtype = get_frame_sub_type(ptr); /* bit(7)~bit(2)  */
+
+		if (_rtw_memcmp(bs, adapter->mppriv.network_macaddr, ETH_ALEN) == _FALSE)
+			ret = _FAIL;
+
+		RTW_DBG("############ type:0x%02x subtype:0x%02x #################\n", type, subtype);
+		RTW_DBG("A2 sa %02X:%02X:%02X:%02X:%02X:%02X \n", *(sa) , *(sa + 1), *(sa+ 2), *(sa + 3), *(sa + 4), *(sa + 5));
+		RTW_DBG("A1 da %02X:%02X:%02X:%02X:%02X:%02X \n", *(da) , *(da + 1), *(da+ 2), *(da + 3), *(da + 4), *(da + 5));
+		RTW_DBG("A3 bs %02X:%02X:%02X:%02X:%02X:%02X \n --------------------------\n", *(bs) , *(bs + 1), *(bs+ 2), *(bs + 3), *(bs + 4), *(bs + 5));
+	}
+
+	if (!adapter->mppriv.bmac_filter)
+		return ret;
+
+	if (_rtw_memcmp(get_addr2_ptr(ptr), adapter->mppriv.mac_filter, ETH_ALEN) == _FALSE)
+		ret = _FAIL;
+
+	return ret;
+}
+
+static sint MPwlanhdr_to_ethhdr(union recv_frame *precvframe)
+{
+	sint	rmv_len;
+	u16 eth_type, len;
+	u8	bsnaphdr;
+	u8	*psnap_type;
+	u8 mcastheadermac[] = {0x01, 0x00, 0x5e};
+
+	struct ieee80211_snap_hdr	*psnap;
+
+	sint ret = _SUCCESS;
+	_adapter			*adapter = precvframe->u.hdr.adapter;
+
+	u8	*ptr = get_recvframe_data(precvframe) ; /* point to frame_ctrl field */
+	struct rx_pkt_attrib *pattrib = &precvframe->u.hdr.attrib;
+
+
+	if (pattrib->encrypt)
+		recvframe_pull_tail(precvframe, pattrib->icv_len);
+
+	psnap = (struct ieee80211_snap_hdr *)(ptr + pattrib->hdrlen + pattrib->iv_len);
+	psnap_type = ptr + pattrib->hdrlen + pattrib->iv_len + SNAP_SIZE;
+	/* convert hdr + possible LLC headers into Ethernet header */
+	/* eth_type = (psnap_type[0] << 8) | psnap_type[1]; */
+	if ((_rtw_memcmp(psnap, rtw_rfc1042_header, SNAP_SIZE) &&
+	     (_rtw_memcmp(psnap_type, SNAP_ETH_TYPE_IPX, 2) == _FALSE) &&
+	     (_rtw_memcmp(psnap_type, SNAP_ETH_TYPE_APPLETALK_AARP, 2) == _FALSE)) ||
+	    /* eth_type != ETH_P_AARP && eth_type != ETH_P_IPX) || */
+	    _rtw_memcmp(psnap, rtw_bridge_tunnel_header, SNAP_SIZE)) {
+		/* remove RFC1042 or Bridge-Tunnel encapsulation and replace EtherType */
+		bsnaphdr = _TRUE;
+	} else {
+		/* Leave Ethernet header part of hdr and full payload */
+		bsnaphdr = _FALSE;
+	}
+
+	rmv_len = pattrib->hdrlen + pattrib->iv_len + (bsnaphdr ? SNAP_SIZE : 0);
+	len = precvframe->u.hdr.len - rmv_len;
+
+
+	_rtw_memcpy(&eth_type, ptr + rmv_len, 2);
+	eth_type = ntohs((unsigned short)eth_type); /* pattrib->ether_type */
+	pattrib->eth_type = eth_type;
+
+	{
+		ptr = recvframe_pull(precvframe, (rmv_len - sizeof(struct ethhdr) + (bsnaphdr ? 2 : 0)));
+	}
+
+	_rtw_memcpy(ptr, pattrib->dst, ETH_ALEN);
+	_rtw_memcpy(ptr + ETH_ALEN, pattrib->src, ETH_ALEN);
+
+	if (!bsnaphdr) {
+		len = htons(len);
+		_rtw_memcpy(ptr + 12, &len, 2);
+	}
+
+
+	len = htons(pattrib->seq_num);
+	/* RTW_INFO("wlan seq = %d ,seq_num =%x\n",len,pattrib->seq_num); */
+	_rtw_memcpy(ptr + 12, &len, 2);
+	if (adapter->mppriv.bRTWSmbCfg == _TRUE) {
+		/* if(_rtw_memcmp(mcastheadermac, pattrib->dst, 3) == _TRUE) */ /* SimpleConfig Dest. */
+		/*			_rtw_memcpy(ptr+ETH_ALEN, pattrib->bssid, ETH_ALEN); */
+
+		if (_rtw_memcmp(mcastheadermac, pattrib->bssid, 3) == _TRUE) /* SimpleConfig Dest. */
+			_rtw_memcpy(ptr, pattrib->bssid, ETH_ALEN);
+
+	}
+
+
+	return ret;
+
+}
+
+
+int mp_recv_frame(_adapter *padapter, union recv_frame *rframe)
+{
+	int ret = _SUCCESS;
+	struct rx_pkt_attrib *pattrib = &rframe->u.hdr.attrib;
+	_queue *pfree_recv_queue = &padapter->recvpriv.free_recv_queue;
+#ifdef CONFIG_MP_INCLUDED
+	struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
+	struct mp_priv *pmppriv = &padapter->mppriv;
+#endif /* CONFIG_MP_INCLUDED */
+	u8 type;
+	u8 *ptr = rframe->u.hdr.rx_data;
+	u8 *psa, *pda, *pbssid;
+	struct sta_info *psta = NULL;
+	DBG_COUNTER(padapter->rx_logs.core_rx_pre);
+
+	if ((check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE)) { /* &&(padapter->mppriv.check_mp_pkt == 0)) */
+		if (pattrib->crc_err == 1)
+			padapter->mppriv.rx_crcerrpktcount++;
+		else {
+			if (_SUCCESS == validate_mp_recv_frame(padapter, rframe))
+				padapter->mppriv.rx_pktcount++;
+			else
+				padapter->mppriv.rx_pktcount_filter_out++;
+		}
+
+		if (pmppriv->rx_bindicatePkt == _FALSE) {
+			ret = _FAIL;
+			rtw_free_recvframe(rframe, pfree_recv_queue);/* free this recv_frame */
+			goto exit;
+		} else {
+			type =	GetFrameType(ptr);
+			pattrib->to_fr_ds = get_tofr_ds(ptr);
+			pattrib->frag_num = GetFragNum(ptr);
+			pattrib->seq_num = GetSequence(ptr);
+			pattrib->pw_save = GetPwrMgt(ptr);
+			pattrib->mfrag = GetMFrag(ptr);
+			pattrib->mdata = GetMData(ptr);
+			pattrib->privacy = GetPrivacy(ptr);
+			pattrib->order = GetOrder(ptr);
+
+			if (type == WIFI_DATA_TYPE) {
+				pda = get_da(ptr);
+				psa = get_sa(ptr);
+				pbssid = get_hdr_bssid(ptr);
+
+				_rtw_memcpy(pattrib->dst, pda, ETH_ALEN);
+				_rtw_memcpy(pattrib->src, psa, ETH_ALEN);
+				_rtw_memcpy(pattrib->bssid, pbssid, ETH_ALEN);
+
+				switch (pattrib->to_fr_ds) {
+				case 0:
+					_rtw_memcpy(pattrib->ra, pda, ETH_ALEN);
+					_rtw_memcpy(pattrib->ta, psa, ETH_ALEN);
+					ret = sta2sta_data_frame(padapter, rframe, &psta);
+					break;
+
+				case 1:
+
+					_rtw_memcpy(pattrib->ra, pda, ETH_ALEN);
+					_rtw_memcpy(pattrib->ta, pbssid, ETH_ALEN);
+					ret = ap2sta_data_frame(padapter, rframe, &psta);
+
+					break;
+
+				case 2:
+					_rtw_memcpy(pattrib->ra, pbssid, ETH_ALEN);
+					_rtw_memcpy(pattrib->ta, psa, ETH_ALEN);
+					ret = sta2ap_data_frame(padapter, rframe, &psta);
+					break;
+
+				case 3:
+					_rtw_memcpy(pattrib->ra, GetAddr1Ptr(ptr), ETH_ALEN);
+					_rtw_memcpy(pattrib->ta, get_addr2_ptr(ptr), ETH_ALEN);
+					ret = _FAIL;
+					break;
+
+				default:
+					ret = _FAIL;
+					break;
+				}
+
+				ret = MPwlanhdr_to_ethhdr(rframe);
+
+				if (ret != _SUCCESS) {
+					#ifdef DBG_RX_DROP_FRAME
+					RTW_INFO("DBG_RX_DROP_FRAME "FUNC_ADPT_FMT" wlanhdr_to_ethhdr: drop pkt\n"
+						, FUNC_ADPT_ARG(padapter));
+					#endif
+					rtw_free_recvframe(rframe, pfree_recv_queue);/* free this recv_frame */
+					ret = _FAIL;
+					goto exit;
+				}
+				if (!RTW_CANNOT_RUN(padapter)) {
+					/* indicate this recv_frame */
+					ret = rtw_recv_indicatepkt(padapter, rframe);
+					if (ret != _SUCCESS) {
+						#ifdef DBG_RX_DROP_FRAME
+						RTW_INFO("DBG_RX_DROP_FRAME "FUNC_ADPT_FMT" rtw_recv_indicatepkt fail!\n"
+							, FUNC_ADPT_ARG(padapter));
+						#endif
+						rtw_free_recvframe(rframe, pfree_recv_queue);/* free this recv_frame */
+						ret = _FAIL;
+
+						goto exit;
+					}
+				} else {
+					#ifdef DBG_RX_DROP_FRAME
+					RTW_INFO("DBG_RX_DROP_FRAME "FUNC_ADPT_FMT" bDriverStopped(%s) OR bSurpriseRemoved(%s)\n"
+						, FUNC_ADPT_ARG(padapter)
+						, rtw_is_drv_stopped(padapter) ? "True" : "False"
+						, rtw_is_surprise_removed(padapter) ? "True" : "False");
+					#endif
+					ret = _FAIL;
+					rtw_free_recvframe(rframe, pfree_recv_queue);/* free this recv_frame */
+					goto exit;
+				}
+
+			}
+		}
+
+	}
+
+	rtw_free_recvframe(rframe, pfree_recv_queue);/* free this recv_frame */
+	ret = _FAIL;
+
+exit:
+	return ret;
+
+}
+#endif
+
+static sint fill_radiotap_hdr(_adapter *padapter, union recv_frame *precvframe, u8 *buf)
+{
+#define CHAN2FREQ(a) ((a < 14) ? (2407+5*a) : (5000+5*a))
+
+#if 0
+#define RTW_RX_RADIOTAP_PRESENT (\
+				 (1 << IEEE80211_RADIOTAP_TSFT)              | \
+				 (1 << IEEE80211_RADIOTAP_FLAGS)             | \
+				 (1 << IEEE80211_RADIOTAP_RATE)              | \
+				 (1 << IEEE80211_RADIOTAP_CHANNEL)           | \
+				 (0 << IEEE80211_RADIOTAP_FHSS)              | \
+				 (1 << IEEE80211_RADIOTAP_DBM_ANTSIGNAL)     | \
+				 (1 << IEEE80211_RADIOTAP_DBM_ANTNOISE)      | \
+				 (0 << IEEE80211_RADIOTAP_LOCK_QUALITY)      | \
+				 (0 << IEEE80211_RADIOTAP_TX_ATTENUATION)    | \
+				 (0 << IEEE80211_RADIOTAP_DB_TX_ATTENUATION) | \
+				 (0 << IEEE80211_RADIOTAP_DBM_TX_POWER)      | \
+				 (1 << IEEE80211_RADIOTAP_ANTENNA)           | \
+				 (1 << IEEE80211_RADIOTAP_DB_ANTSIGNAL)      | \
+				 (0 << IEEE80211_RADIOTAP_DB_ANTNOISE)       | \
+				 (0 << IEEE80211_RADIOTAP_RX_FLAGS)          | \
+				 (0 << IEEE80211_RADIOTAP_TX_FLAGS)          | \
+				 (0 << IEEE80211_RADIOTAP_RTS_RETRIES)       | \
+				 (0 << IEEE80211_RADIOTAP_DATA_RETRIES)      | \
+				 (0 << IEEE80211_RADIOTAP_MCS)               | \
+				 (0 << IEEE80211_RADIOTAP_RADIOTAP_NAMESPACE)| \
+				 (0 << IEEE80211_RADIOTAP_VENDOR_NAMESPACE)  | \
+				 (0 << IEEE80211_RADIOTAP_EXT)               | \
+				 0)
+
+	/* (0 << IEEE80211_RADIOTAP_AMPDU_STATUS)      | \ */
+	/* (0 << IEEE80211_RADIOTAP_VHT)               | \ */
+#endif
+
+#ifndef IEEE80211_RADIOTAP_RX_FLAGS
+#define IEEE80211_RADIOTAP_RX_FLAGS 14
+#endif
+
+#ifndef IEEE80211_RADIOTAP_MCS
+#define IEEE80211_RADIOTAP_MCS 19
+#endif
+#ifndef IEEE80211_RADIOTAP_VHT
+#define IEEE80211_RADIOTAP_VHT 21
+#endif
+
+#ifndef IEEE80211_RADIOTAP_F_BADFCS
+#define IEEE80211_RADIOTAP_F_BADFCS 0x40 /* bad FCS */
+#endif
+
+	sint ret = _SUCCESS;
+	struct rx_pkt_attrib *pattrib = &precvframe->u.hdr.attrib;
+
+	HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
+
+	u16 tmp_16bit = 0;
+
+	u8 data_rate[] = {
+		2, 4, 11, 22, /* CCK */
+		12, 18, 24, 36, 48, 72, 93, 108, /* OFDM */
+		0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, /* HT MCS index */
+		16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31,
+		0, 1, 2, 3, 4, 5, 6, 7, 8, 9, /* VHT Nss 1 */
+		0, 1, 2, 3, 4, 5, 6, 7, 8, 9, /* VHT Nss 2 */
+		0, 1, 2, 3, 4, 5, 6, 7, 8, 9, /* VHT Nss 3 */
+		0, 1, 2, 3, 4, 5, 6, 7, 8, 9, /* VHT Nss 4 */
+	};
+
+	_pkt *pskb = NULL;
+
+	struct ieee80211_radiotap_header *rtap_hdr = NULL;
+	u8 *ptr = NULL;
+
+	u8 hdr_buf[64] = {0};
+	u16 rt_len = 8;
+
+	/* create header */
+	rtap_hdr = (struct ieee80211_radiotap_header *)&hdr_buf[0];
+	rtap_hdr->it_version = PKTHDR_RADIOTAP_VERSION;
+
+	/* tsft */
+	if (pattrib->tsfl) {
+		u64 tmp_64bit;
+
+		rtap_hdr->it_present |= (1 << IEEE80211_RADIOTAP_TSFT);
+		tmp_64bit = cpu_to_le64(pattrib->tsfl);
+		memcpy(&hdr_buf[rt_len], &tmp_64bit, 8);
+		rt_len += 8;
+	}
+
+	/* flags */
+	rtap_hdr->it_present |= (1 << IEEE80211_RADIOTAP_FLAGS);
+	if (0)
+		hdr_buf[rt_len] |= IEEE80211_RADIOTAP_F_CFP;
+
+	if (0)
+		hdr_buf[rt_len] |= IEEE80211_RADIOTAP_F_SHORTPRE;
+
+	if ((pattrib->encrypt == 1) || (pattrib->encrypt == 5))
+		hdr_buf[rt_len] |= IEEE80211_RADIOTAP_F_WEP;
+
+	if (pattrib->mfrag)
+		hdr_buf[rt_len] |= IEEE80211_RADIOTAP_F_FRAG;
+
+	/* always append FCS */
+	hdr_buf[rt_len] |= IEEE80211_RADIOTAP_F_FCS;
+
+
+	if (0)
+		hdr_buf[rt_len] |= IEEE80211_RADIOTAP_F_DATAPAD;
+
+	if (pattrib->crc_err)
+		hdr_buf[rt_len] |= IEEE80211_RADIOTAP_F_BADFCS;
+
+	if (pattrib->sgi) {
+		/* Currently unspecified but used */
+		hdr_buf[rt_len] |= 0x80;
+	}
+	rt_len += 1;
+
+	/* rate */
+	if (pattrib->data_rate <= DESC_RATE54M) {
+		rtap_hdr->it_present |= (1 << IEEE80211_RADIOTAP_RATE);
+		if (pattrib->data_rate <= DESC_RATE11M) {
+			/* CCK */
+			hdr_buf[rt_len] = data_rate[pattrib->data_rate];
+		} else {
+			/* OFDM */
+			hdr_buf[rt_len] = data_rate[pattrib->data_rate];
+		}
+	}
+	rt_len += 1; /* force padding 1 byte for aligned */
+
+	/* channel */
+	tmp_16bit = 0;
+	rtap_hdr->it_present |= (1 << IEEE80211_RADIOTAP_CHANNEL);
+	tmp_16bit = CHAN2FREQ(rtw_get_oper_ch(padapter));
+	/*tmp_16bit = CHAN2FREQ(pHalData->current_channel);*/
+	memcpy(&hdr_buf[rt_len], &tmp_16bit, 2);
+	rt_len += 2;
+
+	/* channel flags */
+	tmp_16bit = 0;
+	if (pHalData->current_band_type == 0)
+		tmp_16bit |= cpu_to_le16(IEEE80211_CHAN_2GHZ);
+	else
+		tmp_16bit |= cpu_to_le16(IEEE80211_CHAN_5GHZ);
+
+	if (pattrib->data_rate <= DESC_RATE54M) {
+		if (pattrib->data_rate <= DESC_RATE11M) {
+			/* CCK */
+			tmp_16bit |= cpu_to_le16(IEEE80211_CHAN_CCK);
+		} else {
+			/* OFDM */
+			tmp_16bit |= cpu_to_le16(IEEE80211_CHAN_OFDM);
+		}
+	} else
+		tmp_16bit |= cpu_to_le16(IEEE80211_CHAN_DYN);
+	memcpy(&hdr_buf[rt_len], &tmp_16bit, 2);
+	rt_len += 2;
+
+	/* dBm Antenna Signal */
+	rtap_hdr->it_present |= (1 << IEEE80211_RADIOTAP_DBM_ANTSIGNAL);
+	hdr_buf[rt_len] = pattrib->phy_info.recv_signal_power;
+	rt_len += 1;
+
+#if 0
+	/* dBm Antenna Noise */
+	rtap_hdr->it_present |= (1 << IEEE80211_RADIOTAP_DBM_ANTNOISE);
+	hdr_buf[rt_len] = 0;
+	rt_len += 1;
+
+	/* Signal Quality */
+	rtap_hdr->it_present |= (1 << IEEE80211_RADIOTAP_LOCK_QUALITY);
+	hdr_buf[rt_len] = pattrib->phy_info.signal_quality;
+	rt_len += 1;
+#endif
+
+	/* Antenna */
+	rtap_hdr->it_present |= (1 << IEEE80211_RADIOTAP_ANTENNA);
+	hdr_buf[rt_len] = 0; /* pHalData->rf_type; */
+	rt_len += 1;
+
+	/* RX flags */
+	rtap_hdr->it_present |= (1 << IEEE80211_RADIOTAP_RX_FLAGS);
+#if 0
+	tmp_16bit = cpu_to_le16(0);
+	memcpy(ptr, &tmp_16bit, 1);
+#endif
+	rt_len += 2;
+
+	/* MCS information */
+	if (pattrib->data_rate >= DESC_RATEMCS0 && pattrib->data_rate <= DESC_RATEMCS31) {
+		rtap_hdr->it_present |= (1 << IEEE80211_RADIOTAP_MCS);
+		/* known, flag */
+		hdr_buf[rt_len] |= BIT1; /* MCS index known */
+
+		/* bandwidth */
+		hdr_buf[rt_len] |= BIT0;
+		hdr_buf[rt_len + 1] |= (pattrib->bw & 0x03);
+
+		/* guard interval */
+		hdr_buf[rt_len] |= BIT2;
+		hdr_buf[rt_len + 1] |= (pattrib->sgi & 0x01) << 2;
+
+		/* STBC */
+		hdr_buf[rt_len] |= BIT5;
+		hdr_buf[rt_len + 1] |= (pattrib->stbc & 0x03) << 5;
+
+		rt_len += 2;
+
+		/* MCS rate index */
+		hdr_buf[rt_len] = data_rate[pattrib->data_rate];
+		rt_len += 1;
+	}
+
+	/* VHT */
+	if (pattrib->data_rate >= DESC_RATEVHTSS1MCS0 && pattrib->data_rate <= DESC_RATEVHTSS4MCS9) {
+		rtap_hdr->it_present |= (1 << IEEE80211_RADIOTAP_VHT);
+
+		/* known 16 bit, flag 8 bit */
+		tmp_16bit = 0;
+
+		/* Bandwidth */
+		tmp_16bit |= BIT6;
+
+		/* Group ID */
+		tmp_16bit |= BIT7;
+
+		/* Partial AID */
+		tmp_16bit |= BIT8;
+
+		/* STBC */
+		tmp_16bit |= BIT0;
+		hdr_buf[rt_len + 2] |= (pattrib->stbc & 0x01);
+
+		/* Guard interval */
+		tmp_16bit |= BIT2;
+		hdr_buf[rt_len + 2] |= (pattrib->sgi & 0x01) << 2;
+
+		/* LDPC extra OFDM symbol */
+		tmp_16bit |= BIT4;
+		hdr_buf[rt_len + 2] |= (pattrib->ldpc & 0x01) << 4;
+
+		memcpy(&hdr_buf[rt_len], &tmp_16bit, 2);
+		rt_len += 3;
+
+		/* bandwidth */
+		if (pattrib->bw == 0)
+			hdr_buf[rt_len] |= 0;
+		else if (pattrib->bw == 1)
+			hdr_buf[rt_len] |= 1;
+		else if (pattrib->bw == 2)
+			hdr_buf[rt_len] |= 4;
+		else if (pattrib->bw == 3)
+			hdr_buf[rt_len] |= 11;
+		rt_len += 1;
+
+		/* mcs_nss */
+		if (pattrib->data_rate >= DESC_RATEVHTSS1MCS0 && pattrib->data_rate <= DESC_RATEVHTSS1MCS9) {
+			hdr_buf[rt_len] |= 1;
+			hdr_buf[rt_len] |= data_rate[pattrib->data_rate] << 4;
+		} else if (pattrib->data_rate >= DESC_RATEVHTSS2MCS0 && pattrib->data_rate <= DESC_RATEVHTSS2MCS9) {
+			hdr_buf[rt_len + 1] |= 2;
+			hdr_buf[rt_len + 1] |= data_rate[pattrib->data_rate] << 4;
+		} else if (pattrib->data_rate >= DESC_RATEVHTSS3MCS0 && pattrib->data_rate <= DESC_RATEVHTSS3MCS9) {
+			hdr_buf[rt_len + 2] |= 3;
+			hdr_buf[rt_len + 2] |= data_rate[pattrib->data_rate] << 4;
+		} else if (pattrib->data_rate >= DESC_RATEVHTSS4MCS0 && pattrib->data_rate <= DESC_RATEVHTSS4MCS9) {
+			hdr_buf[rt_len + 3] |= 4;
+			hdr_buf[rt_len + 3] |= data_rate[pattrib->data_rate] << 4;
+		}
+		rt_len += 4;
+
+		/* coding */
+		hdr_buf[rt_len] = 0;
+		rt_len += 1;
+
+		/* group_id */
+		hdr_buf[rt_len] = 0;
+		rt_len += 1;
+
+		/* partial_aid */
+		tmp_16bit = 0;
+		memcpy(&hdr_buf[rt_len], &tmp_16bit, 2);
+		rt_len += 2;
+	}
+
+	/* push to skb */
+	pskb = (_pkt *)buf;
+	if (skb_headroom(pskb) < rt_len) {
+		RTW_INFO("%s:%d %s headroom is too small.\n", __FILE__, __LINE__, __func__);
+		ret = _FAIL;
+		return ret;
+	}
+
+	ptr = skb_push(pskb, rt_len);
+	if (ptr) {
+		rtap_hdr->it_len = cpu_to_le16(rt_len);
+		rtap_hdr->it_present = cpu_to_le32(rtap_hdr->it_present);
+		memcpy(ptr, rtap_hdr, rt_len);
+	} else
+		ret = _FAIL;
+
+	return ret;
+
+}
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 24))
+int recv_frame_monitor(_adapter *padapter, union recv_frame *rframe)
+{
+	int ret = _SUCCESS;
+	_queue *pfree_recv_queue = &padapter->recvpriv.free_recv_queue;
+	_pkt *pskb = NULL;
+
+	/* read skb information from recv frame */
+	pskb = rframe->u.hdr.pkt;
+	pskb->len = rframe->u.hdr.len;
+	pskb->data = rframe->u.hdr.rx_data;
+	skb_set_tail_pointer(pskb, rframe->u.hdr.len);
+
+	/* fill radiotap header */
+	if (fill_radiotap_hdr(padapter, rframe, (u8 *)pskb) == _FAIL) {
+		ret = _FAIL;
+		rtw_free_recvframe(rframe, pfree_recv_queue); /* free this recv_frame */
+		goto exit;
+	}
+
+	/* write skb information to recv frame */
+	skb_reset_mac_header(pskb);
+	rframe->u.hdr.len = pskb->len;
+	rframe->u.hdr.rx_data = pskb->data;
+	rframe->u.hdr.rx_head = pskb->head;
+	rframe->u.hdr.rx_tail = skb_tail_pointer(pskb);
+	rframe->u.hdr.rx_end = skb_end_pointer(pskb);
+
+	if (!RTW_CANNOT_RUN(padapter)) {
+		/* indicate this recv_frame */
+		ret = rtw_recv_monitor(padapter, rframe);
+		if (ret != _SUCCESS) {
+			ret = _FAIL;
+			rtw_free_recvframe(rframe, pfree_recv_queue); /* free this recv_frame */
+			goto exit;
+		}
+	} else {
+		ret = _FAIL;
+		rtw_free_recvframe(rframe, pfree_recv_queue); /* free this recv_frame */
+		goto exit;
+	}
+
+exit:
+	return ret;
+}
+#endif
+int recv_func_prehandle(_adapter *padapter, union recv_frame *rframe)
+{
+	int ret = _SUCCESS;
+#ifdef DBG_RX_COUNTER_DUMP
+	struct rx_pkt_attrib *pattrib = &rframe->u.hdr.attrib;
+#endif
+	_queue *pfree_recv_queue = &padapter->recvpriv.free_recv_queue;
+
+#ifdef DBG_RX_COUNTER_DUMP
+	if (padapter->dump_rx_cnt_mode & DUMP_DRV_RX_COUNTER) {
+		if (pattrib->crc_err == 1)
+			padapter->drv_rx_cnt_crcerror++;
+		else
+			padapter->drv_rx_cnt_ok++;
+	}
+#endif
+
+#ifdef CONFIG_MP_INCLUDED
+	if (padapter->registrypriv.mp_mode == 1 || padapter->mppriv.bRTWSmbCfg == _TRUE) {
+		mp_recv_frame(padapter, rframe);
+		ret = _FAIL;
+		goto exit;
+	} else
+#endif
+	{
+		/* check the frame crtl field and decache */
+		ret = validate_recv_frame(padapter, rframe);
+		if (ret != _SUCCESS) {
+			rtw_free_recvframe(rframe, pfree_recv_queue);/* free this recv_frame */
+			goto exit;
+		}
+	}
+exit:
+	return ret;
+}
+
+/*#define DBG_RX_BMC_FRAME*/
+int recv_func_posthandle(_adapter *padapter, union recv_frame *prframe)
+{
+	int ret = _SUCCESS;
+	union recv_frame *orig_prframe = prframe;
+	struct rx_pkt_attrib *pattrib = &prframe->u.hdr.attrib;
+	struct recv_priv *precvpriv = &padapter->recvpriv;
+	_queue *pfree_recv_queue = &padapter->recvpriv.free_recv_queue;
+#ifdef CONFIG_TDLS
+	u8 *psnap_type, *pcategory;
+#endif /* CONFIG_TDLS */
+
+	DBG_COUNTER(padapter->rx_logs.core_rx_post);
+
+	prframe = decryptor(padapter, prframe);
+	if (prframe == NULL) {
+		#ifdef DBG_RX_DROP_FRAME
+		RTW_INFO("DBG_RX_DROP_FRAME "FUNC_ADPT_FMT" decryptor: drop pkt\n"
+			, FUNC_ADPT_ARG(padapter));
+		#endif
+		ret = _FAIL;
+		DBG_COUNTER(padapter->rx_logs.core_rx_post_decrypt_err);
+		goto _recv_data_drop;
+	}
+
+#ifdef DBG_RX_BMC_FRAME
+	if (IS_MCAST(pattrib->ra))
+		RTW_INFO("%s =>"ADPT_FMT" Rx BC/MC from "MAC_FMT"\n", __func__, ADPT_ARG(padapter), MAC_ARG(pattrib->ta));
+#endif
+
+#if 0
+	if (is_primary_adapter(padapter)) {
+		RTW_INFO("+++\n");
+		{
+			int i;
+			u8	*ptr = get_recvframe_data(prframe);
+			for (i = 0; i < 140; i = i + 8)
+				RTW_INFO("%02X:%02X:%02X:%02X:%02X:%02X:%02X:%02X:", *(ptr + i),
+					*(ptr + i + 1), *(ptr + i + 2) , *(ptr + i + 3) , *(ptr + i + 4), *(ptr + i + 5), *(ptr + i + 6), *(ptr + i + 7));
+
+		}
+		RTW_INFO("---\n");
+	}
+#endif
+
+#ifdef CONFIG_TDLS
+	/* check TDLS frame */
+	psnap_type = get_recvframe_data(orig_prframe) + pattrib->hdrlen + pattrib->iv_len + SNAP_SIZE;
+	pcategory = psnap_type + ETH_TYPE_LEN + PAYLOAD_TYPE_LEN;
+
+	if ((_rtw_memcmp(psnap_type, SNAP_ETH_TYPE_TDLS, ETH_TYPE_LEN)) &&
+	    ((*pcategory == RTW_WLAN_CATEGORY_TDLS) || (*pcategory == RTW_WLAN_CATEGORY_P2P))) {
+		ret = OnTDLS(padapter, prframe);
+		if (ret == _FAIL)
+			goto _exit_recv_func;
+	}
+#endif /* CONFIG_TDLS */
+
+	prframe = recvframe_chk_defrag(padapter, prframe);
+	if (prframe == NULL)	{
+		#ifdef DBG_RX_DROP_FRAME
+		RTW_INFO("DBG_RX_DROP_FRAME "FUNC_ADPT_FMT" recvframe_chk_defrag: drop pkt\n"
+			, FUNC_ADPT_ARG(padapter));
+		#endif
+		DBG_COUNTER(padapter->rx_logs.core_rx_post_defrag_err);
+		goto _recv_data_drop;
+	}
+
+	prframe = portctrl(padapter, prframe);
+	if (prframe == NULL) {
+		#ifdef DBG_RX_DROP_FRAME
+		RTW_INFO("DBG_RX_DROP_FRAME "FUNC_ADPT_FMT" portctrl: drop pkt\n"
+			, FUNC_ADPT_ARG(padapter));
+		#endif
+		ret = _FAIL;
+		DBG_COUNTER(padapter->rx_logs.core_rx_post_portctrl_err);
+		goto _recv_data_drop;
+	}
+
+	count_rx_stats(padapter, prframe, NULL);
+
+#ifdef CONFIG_WAPI_SUPPORT
+	rtw_wapi_update_info(padapter, prframe);
+#endif
+
+#if defined(CONFIG_80211N_HT) && defined(CONFIG_RECV_REORDERING_CTRL)
+	/* including perform A-MPDU Rx Ordering Buffer Control */
+	ret = recv_indicatepkt_reorder(padapter, prframe);
+	if (ret == _FAIL) {
+		rtw_free_recvframe(orig_prframe, pfree_recv_queue);
+		goto _recv_data_drop;
+	} else if (ret == RTW_RX_HANDLED) /* queued OR indicated in order */
+		goto _exit_recv_func;
+#endif
+
+	recv_set_iseq_before_mpdu_process(prframe, pattrib->seq_num, __func__);
+	ret = recv_process_mpdu(padapter, prframe);
+	recv_set_iseq_after_mpdu_process(prframe, pattrib->seq_num, __func__);
+	if (ret == _FAIL)
+		goto _recv_data_drop;
+
+_exit_recv_func:
+	return ret;
+
+_recv_data_drop:
+	precvpriv->dbg_rx_drop_count++;
+	return ret;
+}
+
+int recv_func(_adapter *padapter, union recv_frame *rframe)
+{
+	int ret;
+	struct rx_pkt_attrib *prxattrib = &rframe->u.hdr.attrib;
+	struct recv_priv *recvpriv = &padapter->recvpriv;
+	struct security_priv *psecuritypriv = &padapter->securitypriv;
+	struct mlme_priv *mlmepriv = &padapter->mlmepriv;
+
+	if (check_fwstate(mlmepriv, WIFI_MONITOR_STATE)) {
+		/* monitor mode */
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 24))
+		recv_frame_monitor(padapter, rframe);
+#endif
+		ret = _SUCCESS;
+		goto exit;
+	} else
+
+		/* check if need to handle uc_swdec_pending_queue*/
+		if (check_fwstate(mlmepriv, WIFI_STATION_STATE) && psecuritypriv->busetkipkey) {
+			union recv_frame *pending_frame;
+			int cnt = 0;
+
+			while ((pending_frame = rtw_alloc_recvframe(&padapter->recvpriv.uc_swdec_pending_queue))) {
+				cnt++;
+				DBG_COUNTER(padapter->rx_logs.core_rx_dequeue);
+				recv_func_posthandle(padapter, pending_frame);
+			}
+
+			if (cnt)
+				RTW_INFO(FUNC_ADPT_FMT" dequeue %d from uc_swdec_pending_queue\n",
+					 FUNC_ADPT_ARG(padapter), cnt);
+		}
+
+	DBG_COUNTER(padapter->rx_logs.core_rx);
+	ret = recv_func_prehandle(padapter, rframe);
+
+	if (ret == _SUCCESS) {
+
+		/* check if need to enqueue into uc_swdec_pending_queue*/
+		if (check_fwstate(mlmepriv, WIFI_STATION_STATE) &&
+		    !IS_MCAST(prxattrib->ra) && prxattrib->encrypt > 0 &&
+		    (prxattrib->bdecrypted == 0 || psecuritypriv->sw_decrypt == _TRUE) &&
+		    psecuritypriv->ndisauthtype == Ndis802_11AuthModeWPAPSK &&
+		    !psecuritypriv->busetkipkey) {
+			DBG_COUNTER(padapter->rx_logs.core_rx_enqueue);
+			rtw_enqueue_recvframe(rframe, &padapter->recvpriv.uc_swdec_pending_queue);
+			/* RTW_INFO("%s: no key, enqueue uc_swdec_pending_queue\n", __func__); */
+
+			if (recvpriv->free_recvframe_cnt < NR_RECVFRAME / 4) {
+				/* to prevent from recvframe starvation, get recvframe from uc_swdec_pending_queue to free_recvframe_cnt */
+				rframe = rtw_alloc_recvframe(&padapter->recvpriv.uc_swdec_pending_queue);
+				if (rframe)
+					goto do_posthandle;
+			}
+			goto exit;
+		}
+
+do_posthandle:
+		ret = recv_func_posthandle(padapter, rframe);
+	}
+
+exit:
+	return ret;
+}
+
+
+s32 rtw_recv_entry(union recv_frame *precvframe)
+{
+	_adapter *padapter;
+	struct recv_priv *precvpriv;
+	s32 ret = _SUCCESS;
+
+
+
+	padapter = precvframe->u.hdr.adapter;
+
+	precvpriv = &padapter->recvpriv;
+
+
+	ret = recv_func(padapter, precvframe);
+	if (ret == _FAIL) {
+		goto _recv_entry_drop;
+	}
+
+
+	precvpriv->rx_pkts++;
+
+
+	return ret;
+
+_recv_entry_drop:
+
+#ifdef CONFIG_MP_INCLUDED
+	if (padapter->registrypriv.mp_mode == 1)
+		padapter->mppriv.rx_pktloss = precvpriv->rx_drop;
+#endif
+
+
+
+	return ret;
+}
+
+#ifdef CONFIG_NEW_SIGNAL_STAT_PROCESS
+static void rtw_signal_stat_timer_hdl(void *ctx)
+{
+	_adapter *adapter = (_adapter *)ctx;
+	struct recv_priv *recvpriv = &adapter->recvpriv;
+
+	u32 tmp_s, tmp_q;
+	u8 avg_signal_strength = 0;
+	u8 avg_signal_qual = 0;
+	u32 num_signal_strength = 0;
+	u32 num_signal_qual = 0;
+	u8 ratio_pre_stat = 0, ratio_curr_stat = 0, ratio_total = 0, ratio_profile = SIGNAL_STAT_CALC_PROFILE_0;
+
+	if (adapter->recvpriv.is_signal_dbg) {
+		/* update the user specific value, signal_strength_dbg, to signal_strength, rssi */
+		adapter->recvpriv.signal_strength = adapter->recvpriv.signal_strength_dbg;
+		adapter->recvpriv.rssi = (s8)translate_percentage_to_dbm((u8)adapter->recvpriv.signal_strength_dbg);
+	} else {
+
+		if (recvpriv->signal_strength_data.update_req == 0) { /* update_req is clear, means we got rx */
+			avg_signal_strength = recvpriv->signal_strength_data.avg_val;
+			num_signal_strength = recvpriv->signal_strength_data.total_num;
+			/* after avg_vals are accquired, we can re-stat the signal values */
+			recvpriv->signal_strength_data.update_req = 1;
+		}
+
+		if (recvpriv->signal_qual_data.update_req == 0) { /* update_req is clear, means we got rx */
+			avg_signal_qual = recvpriv->signal_qual_data.avg_val;
+			num_signal_qual = recvpriv->signal_qual_data.total_num;
+			/* after avg_vals are accquired, we can re-stat the signal values */
+			recvpriv->signal_qual_data.update_req = 1;
+		}
+
+		if (num_signal_strength == 0) {
+			if (rtw_get_on_cur_ch_time(adapter) == 0
+			    || rtw_get_passing_time_ms(rtw_get_on_cur_ch_time(adapter)) < 2 * adapter->mlmeextpriv.mlmext_info.bcn_interval
+			   )
+				goto set_timer;
+		}
+
+		if (check_fwstate(&adapter->mlmepriv, _FW_UNDER_SURVEY) == _TRUE
+		    || check_fwstate(&adapter->mlmepriv, _FW_LINKED) == _FALSE
+		   )
+			goto set_timer;
+
+#ifdef CONFIG_CONCURRENT_MODE
+		if (rtw_mi_buddy_check_fwstate(adapter, _FW_UNDER_SURVEY) == _TRUE)
+			goto set_timer;
+#endif
+
+		if (RTW_SIGNAL_STATE_CALC_PROFILE < SIGNAL_STAT_CALC_PROFILE_MAX)
+			ratio_profile = RTW_SIGNAL_STATE_CALC_PROFILE;
+
+		ratio_pre_stat = signal_stat_calc_profile[ratio_profile][0];
+		ratio_curr_stat = signal_stat_calc_profile[ratio_profile][1];
+		ratio_total = ratio_pre_stat + ratio_curr_stat;
+
+		/* update value of signal_strength, rssi, signal_qual */
+		tmp_s = (ratio_curr_stat * avg_signal_strength + ratio_pre_stat * recvpriv->signal_strength);
+		if (tmp_s % ratio_total)
+			tmp_s = tmp_s / ratio_total + 1;
+		else
+			tmp_s = tmp_s / ratio_total;
+		if (tmp_s > 100)
+			tmp_s = 100;
+
+		tmp_q = (ratio_curr_stat * avg_signal_qual + ratio_pre_stat * recvpriv->signal_qual);
+		if (tmp_q % ratio_total)
+			tmp_q = tmp_q / ratio_total + 1;
+		else
+			tmp_q = tmp_q / ratio_total;
+		if (tmp_q > 100)
+			tmp_q = 100;
+
+		recvpriv->signal_strength = tmp_s;
+		recvpriv->rssi = (s8)translate_percentage_to_dbm(tmp_s);
+		recvpriv->signal_qual = tmp_q;
+
+#if defined(DBG_RX_SIGNAL_DISPLAY_PROCESSING) && 1
+		RTW_INFO(FUNC_ADPT_FMT" signal_strength:%3u, rssi:%3d, signal_qual:%3u"
+			 ", num_signal_strength:%u, num_signal_qual:%u"
+			 ", on_cur_ch_ms:%d"
+			 "\n"
+			 , FUNC_ADPT_ARG(adapter)
+			 , recvpriv->signal_strength
+			 , recvpriv->rssi
+			 , recvpriv->signal_qual
+			 , num_signal_strength, num_signal_qual
+			, rtw_get_on_cur_ch_time(adapter) ? rtw_get_passing_time_ms(rtw_get_on_cur_ch_time(adapter)) : 0
+			);
+#endif
+	}
+
+set_timer:
+	rtw_set_signal_stat_timer(recvpriv);
+
+}
+#endif /* CONFIG_NEW_SIGNAL_STAT_PROCESS */
+
+static void rx_process_rssi(_adapter *padapter, union recv_frame *prframe)
+{
+	struct rx_pkt_attrib *pattrib = &prframe->u.hdr.attrib;
+#ifdef CONFIG_NEW_SIGNAL_STAT_PROCESS
+	struct signal_stat *signal_stat = &padapter->recvpriv.signal_strength_data;
+#else /* CONFIG_NEW_SIGNAL_STAT_PROCESS */
+	u32 last_rssi, tmp_val;
+#endif /* CONFIG_NEW_SIGNAL_STAT_PROCESS */
+
+	/* RTW_INFO("process_rssi=> pattrib->rssil(%d) signal_strength(%d)\n ",pattrib->recv_signal_power,pattrib->signal_strength); */
+	/* if(pRfd->Status.bPacketToSelf || pRfd->Status.bPacketBeacon) */
+	{
+#ifdef CONFIG_NEW_SIGNAL_STAT_PROCESS
+		if (signal_stat->update_req) {
+			signal_stat->total_num = 0;
+			signal_stat->total_val = 0;
+			signal_stat->update_req = 0;
+		}
+
+		signal_stat->total_num++;
+		signal_stat->total_val  += pattrib->phy_info.signal_strength;
+		signal_stat->avg_val = signal_stat->total_val / signal_stat->total_num;
+#else /* CONFIG_NEW_SIGNAL_STAT_PROCESS */
+
+		/* Adapter->RxStats.RssiCalculateCnt++;	 */ /* For antenna Test */
+		if (padapter->recvpriv.signal_strength_data.total_num++ >= PHY_RSSI_SLID_WIN_MAX) {
+			padapter->recvpriv.signal_strength_data.total_num = PHY_RSSI_SLID_WIN_MAX;
+			last_rssi = padapter->recvpriv.signal_strength_data.elements[padapter->recvpriv.signal_strength_data.index];
+			padapter->recvpriv.signal_strength_data.total_val -= last_rssi;
+		}
+		padapter->recvpriv.signal_strength_data.total_val  += pattrib->phy_info.signal_strength;
+
+		padapter->recvpriv.signal_strength_data.elements[padapter->recvpriv.signal_strength_data.index++] = pattrib->phy_info.signal_strength;
+		if (padapter->recvpriv.signal_strength_data.index >= PHY_RSSI_SLID_WIN_MAX)
+			padapter->recvpriv.signal_strength_data.index = 0;
+
+
+		tmp_val = padapter->recvpriv.signal_strength_data.total_val / padapter->recvpriv.signal_strength_data.total_num;
+
+		if (padapter->recvpriv.is_signal_dbg) {
+			padapter->recvpriv.signal_strength = padapter->recvpriv.signal_strength_dbg;
+			padapter->recvpriv.rssi = (s8)translate_percentage_to_dbm(padapter->recvpriv.signal_strength_dbg);
+		} else {
+			padapter->recvpriv.signal_strength = tmp_val;
+			padapter->recvpriv.rssi = (s8)translate_percentage_to_dbm(tmp_val);
+		}
+
+#endif /* CONFIG_NEW_SIGNAL_STAT_PROCESS */
+	}
+}
+
+static void rx_process_link_qual(_adapter *padapter, union recv_frame *prframe)
+{
+	struct rx_pkt_attrib *pattrib;
+#ifdef CONFIG_NEW_SIGNAL_STAT_PROCESS
+	struct signal_stat *signal_stat;
+#else /* CONFIG_NEW_SIGNAL_STAT_PROCESS */
+	u32 last_evm = 0, tmpVal;
+#endif /* CONFIG_NEW_SIGNAL_STAT_PROCESS */
+
+	if (prframe == NULL || padapter == NULL)
+		return;
+
+	pattrib = &prframe->u.hdr.attrib;
+#ifdef CONFIG_NEW_SIGNAL_STAT_PROCESS
+	signal_stat = &padapter->recvpriv.signal_qual_data;
+#endif /* CONFIG_NEW_SIGNAL_STAT_PROCESS */
+
+	/* RTW_INFO("process_link_qual=> pattrib->signal_qual(%d)\n ",pattrib->signal_qual); */
+
+#ifdef CONFIG_NEW_SIGNAL_STAT_PROCESS
+	if (signal_stat->update_req) {
+		signal_stat->total_num = 0;
+		signal_stat->total_val = 0;
+		signal_stat->update_req = 0;
+	}
+
+	signal_stat->total_num++;
+	signal_stat->total_val  += pattrib->phy_info.signal_quality;
+	signal_stat->avg_val = signal_stat->total_val / signal_stat->total_num;
+
+#else /* CONFIG_NEW_SIGNAL_STAT_PROCESS */
+	if (pattrib->phy_info.signal_quality != 0) {
+		/*  */
+		/* 1. Record the general EVM to the sliding window. */
+		/*  */
+		if (padapter->recvpriv.signal_qual_data.total_num++ >= PHY_LINKQUALITY_SLID_WIN_MAX) {
+			padapter->recvpriv.signal_qual_data.total_num = PHY_LINKQUALITY_SLID_WIN_MAX;
+			last_evm = padapter->recvpriv.signal_qual_data.elements[padapter->recvpriv.signal_qual_data.index];
+			padapter->recvpriv.signal_qual_data.total_val -= last_evm;
+		}
+		padapter->recvpriv.signal_qual_data.total_val += pattrib->phy_info.signal_quality;
+
+		padapter->recvpriv.signal_qual_data.elements[padapter->recvpriv.signal_qual_data.index++] = pattrib->phy_info.signal_quality;
+		if (padapter->recvpriv.signal_qual_data.index >= PHY_LINKQUALITY_SLID_WIN_MAX)
+			padapter->recvpriv.signal_qual_data.index = 0;
+
+
+		/* <1> Showed on UI for user, in percentage. */
+		tmpVal = padapter->recvpriv.signal_qual_data.total_val / padapter->recvpriv.signal_qual_data.total_num;
+		padapter->recvpriv.signal_qual = (u8)tmpVal;
+
+	}
+#endif /* CONFIG_NEW_SIGNAL_STAT_PROCESS */
+}
+
+void rx_process_phy_info(_adapter *padapter, union recv_frame *rframe)
+{
+	/* Check RSSI */
+	rx_process_rssi(padapter, rframe);
+
+	/* Check PWDB */
+	/* process_PWDB(padapter, rframe); */
+
+	/* UpdateRxSignalStatistics8192C(Adapter, pRfd); */
+
+	/* Check EVM */
+	rx_process_link_qual(padapter, rframe);
+	rtw_store_phy_info(padapter, rframe);
+}
+
+void rx_query_phy_status(
+	union recv_frame	*precvframe,
+	u8 *pphy_status)
+{
+	PADAPTER			padapter = precvframe->u.hdr.adapter;
+	struct rx_pkt_attrib	*pattrib = &precvframe->u.hdr.attrib;
+	HAL_DATA_TYPE		*pHalData = GET_HAL_DATA(padapter);
+	struct phydm_phyinfo_struct *p_phy_info = &pattrib->phy_info;
+	u8					*wlanhdr;
+	struct phydm_perpkt_info_struct pkt_info;
+	u8 *ta, *ra;
+	u8 is_ra_bmc;
+	struct sta_priv *pstapriv;
+	struct sta_info *psta = NULL;
+	struct recv_priv  *precvpriv = &padapter->recvpriv;
+	/* _irqL		irqL; */
+
+	pkt_info.is_packet_match_bssid = _FALSE;
+	pkt_info.is_packet_to_self = _FALSE;
+	pkt_info.is_packet_beacon = _FALSE;
+	pkt_info.ppdu_cnt = pattrib->ppdu_cnt;
+	pkt_info.station_id = 0xFF;
+
+	wlanhdr = get_recvframe_data(precvframe);
+
+	ta = get_ta(wlanhdr);
+	ra = get_ra(wlanhdr);
+	is_ra_bmc = IS_MCAST(ra);
+
+	if (_rtw_memcmp(adapter_mac_addr(padapter), ta, ETH_ALEN) == _TRUE) {
+		static systime start_time = 0;
+
+#if 0 /*For debug */
+		if (IsFrameTypeCtrl(wlanhdr)) {
+			RTW_INFO("-->Control frame: Y\n");
+			RTW_INFO("-->pkt_len: %d\n", pattrib->pkt_len);
+			RTW_INFO("-->Sub Type = 0x%X\n", get_frame_sub_type(wlanhdr));
+		}
+
+		/* Dump first 40 bytes of header */
+		int i = 0;
+
+		for (i = 0; i < 40; i++)
+			RTW_INFO("%d: %X\n", i, *((u8 *)wlanhdr + i));
+
+		RTW_INFO("\n");
+#endif
+
+		if ((start_time == 0) || (rtw_get_passing_time_ms(start_time) > 5000)) {
+			RTW_PRINT("Warning!!! %s: Confilc mac addr!!\n", __func__);
+			start_time = rtw_get_current_time();
+		}
+		precvpriv->dbg_rx_conflic_mac_addr_cnt++;
+	} else {
+		pstapriv = &padapter->stapriv;
+		psta = rtw_get_stainfo(pstapriv, ta);
+		if (psta)
+			pkt_info.station_id = psta->cmn.mac_id;
+	}
+
+	pkt_info.is_packet_match_bssid = (!IsFrameTypeCtrl(wlanhdr))
+		&& (!pattrib->icv_err) && (!pattrib->crc_err)
+		&& ((!MLME_IS_MESH(padapter) && _rtw_memcmp(get_hdr_bssid(wlanhdr), get_bssid(&padapter->mlmepriv), ETH_ALEN))
+			|| (MLME_IS_MESH(padapter) && psta));
+
+	pkt_info.is_to_self = (!pattrib->icv_err) && (!pattrib->crc_err)
+		&& _rtw_memcmp(ra, adapter_mac_addr(padapter), ETH_ALEN);
+
+	pkt_info.is_packet_to_self = pkt_info.is_packet_match_bssid
+		&& _rtw_memcmp(ra, adapter_mac_addr(padapter), ETH_ALEN);
+
+	pkt_info.is_packet_beacon = pkt_info.is_packet_match_bssid
+				 && (get_frame_sub_type(wlanhdr) == WIFI_BEACON);
+
+	if (psta && IsFrameTypeData(wlanhdr)) {
+		if (is_ra_bmc)
+			psta->curr_rx_rate_bmc = pattrib->data_rate;
+		else
+			psta->curr_rx_rate = pattrib->data_rate;
+	}
+	pkt_info.data_rate = pattrib->data_rate;
+
+	odm_phy_status_query(&pHalData->odmpriv, p_phy_info, pphy_status, &pkt_info);
+
+	/* If bw is initial value, get from phy status */
+	if (pattrib->bw == CHANNEL_WIDTH_MAX)
+		pattrib->bw = p_phy_info->band_width;
+
+	{
+		precvframe->u.hdr.psta = NULL;
+		if (padapter->registrypriv.mp_mode != 1) {
+			if ((!MLME_IS_MESH(padapter) && pkt_info.is_packet_match_bssid)
+				|| (MLME_IS_MESH(padapter) && psta)) {
+				if (psta) {
+					precvframe->u.hdr.psta = psta;
+					rx_process_phy_info(padapter, precvframe);
+				}
+			} else if (pkt_info.is_packet_to_self || pkt_info.is_packet_beacon) {
+				if (psta)
+					precvframe->u.hdr.psta = psta;
+				rx_process_phy_info(padapter, precvframe);
+			}
+		} else {
+#ifdef CONFIG_MP_INCLUDED
+			if (padapter->mppriv.brx_filter_beacon == _TRUE) {
+				if (pkt_info.is_packet_beacon) {
+					RTW_INFO("in MP Rx is_packet_beacon\n");
+					if (psta)
+						precvframe->u.hdr.psta = psta;
+					rx_process_phy_info(padapter, precvframe);
+				}
+			} else 
+#endif
+			{
+					if (psta)
+						precvframe->u.hdr.psta = psta;
+					rx_process_phy_info(padapter, precvframe);
+			}
+		}
+	}
+
+	rtw_odm_parse_rx_phy_status_chinfo(precvframe, pphy_status);
+}
+/*
+* Increase and check if the continual_no_rx_packet of this @param pmlmepriv is larger than MAX_CONTINUAL_NORXPACKET_COUNT
+* @return _TRUE:
+* @return _FALSE:
+*/
+int rtw_inc_and_chk_continual_no_rx_packet(struct sta_info *sta, int tid_index)
+{
+
+	int ret = _FALSE;
+	int value = ATOMIC_INC_RETURN(&sta->continual_no_rx_packet[tid_index]);
+
+	if (value >= MAX_CONTINUAL_NORXPACKET_COUNT)
+		ret = _TRUE;
+
+	return ret;
+}
+
+/*
+* Set the continual_no_rx_packet of this @param pmlmepriv to 0
+*/
+void rtw_reset_continual_no_rx_packet(struct sta_info *sta, int tid_index)
+{
+	ATOMIC_SET(&sta->continual_no_rx_packet[tid_index], 0);
+}
+
+u8 adapter_allow_bmc_data_rx(_adapter *adapter)
+{
+	if (check_fwstate(&adapter->mlmepriv, WIFI_MONITOR_STATE | WIFI_MP_STATE) == _TRUE)
+		return 1;
+
+	if (MLME_IS_AP(adapter))
+		return 0;
+
+	if (rtw_linked_check(adapter) == _FALSE)
+		return 0;
+
+	return 1;
+}
+
+s32 pre_recv_entry(union recv_frame *precvframe, u8 *pphy_status)
+{
+	s32 ret = _SUCCESS;
+	u8 *pbuf = precvframe->u.hdr.rx_data;
+	u8 *pda = get_ra(pbuf);
+	u8 ra_is_bmc = IS_MCAST(pda);
+	_adapter *primary_padapter = precvframe->u.hdr.adapter;
+#ifdef CONFIG_CONCURRENT_MODE
+	_adapter *iface = NULL;
+
+	#ifdef CONFIG_MP_INCLUDED
+	if (rtw_mp_mode_check(primary_padapter))
+		goto bypass_concurrent_hdl;
+	#endif
+
+	if (ra_is_bmc == _FALSE) { /*unicast packets*/
+		iface = rtw_get_iface_by_macddr(primary_padapter , pda);
+		if (NULL == iface) {
+		#ifdef CONFIG_RTW_CFGVENDOR_RANDOM_MAC_OUI
+			if (_rtw_memcmp(pda, adapter_pno_mac_addr(primary_padapter),
+					ETH_ALEN) != _TRUE)
+		#endif
+			RTW_INFO("%s [WARN] Cannot find appropriate adapter - mac_addr : "MAC_FMT"\n", __func__, MAC_ARG(pda));
+			/*rtw_warn_on(1);*/
+		} else
+			precvframe->u.hdr.adapter = iface;
+	} else   /* Handle BC/MC Packets	*/
+		rtw_mi_buddy_clone_bcmc_packet(primary_padapter, precvframe, pphy_status);
+bypass_concurrent_hdl:
+#endif /* CONFIG_CONCURRENT_MODE */
+	if (primary_padapter->registrypriv.mp_mode != 1) {
+		/* skip unnecessary bmc data frame for primary adapter */
+		if (ra_is_bmc == _TRUE && GetFrameType(pbuf) == WIFI_DATA_TYPE
+			&& !adapter_allow_bmc_data_rx(precvframe->u.hdr.adapter)
+		) {
+			rtw_free_recvframe(precvframe, &precvframe->u.hdr.adapter->recvpriv.free_recv_queue);
+			goto exit;
+		}
+	}
+
+	if (pphy_status)
+		rx_query_phy_status(precvframe, pphy_status);
+	ret = rtw_recv_entry(precvframe);
+
+exit:
+	return ret;
+}
+
+#ifdef CONFIG_RECV_THREAD_MODE
+thread_return rtw_recv_thread(thread_context context)
+{
+	_adapter *adapter = (_adapter *)context;
+	struct recv_priv *recvpriv = &adapter->recvpriv;
+	s32 err = _SUCCESS;
+#ifdef RTW_RECV_THREAD_HIGH_PRIORITY
+#ifdef PLATFORM_LINUX
+	struct sched_param param = { .sched_priority = 1 };
+
+	sched_setscheduler(current, SCHED_FIFO, &param);
+#endif /* PLATFORM_LINUX */
+#endif /*RTW_RECV_THREAD_HIGH_PRIORITY*/
+	thread_enter("RTW_RECV_THREAD");
+
+	RTW_INFO(FUNC_ADPT_FMT" enter\n", FUNC_ADPT_ARG(adapter));
+
+	do {
+		err = _rtw_down_sema(&recvpriv->recv_sema);
+		if (_FAIL == err) {
+			RTW_ERR(FUNC_ADPT_FMT" down recv_sema fail!\n", FUNC_ADPT_ARG(adapter));
+			goto exit;
+		}
+
+		if (RTW_CANNOT_RUN(adapter)) {
+			RTW_DBG(FUNC_ADPT_FMT "- bDriverStopped(%s) bSurpriseRemoved(%s)\n",
+				FUNC_ADPT_ARG(adapter),
+				rtw_is_drv_stopped(adapter) ? "True" : "False",
+				rtw_is_surprise_removed(adapter) ? "True" : "False");
+			goto exit;
+		}
+
+		err = rtw_hal_recv_hdl(adapter);
+
+		if (err == RTW_RFRAME_UNAVAIL
+			|| err == RTW_RFRAME_PKT_UNAVAIL
+		) {
+			rtw_msleep_os(1);
+			_rtw_up_sema(&recvpriv->recv_sema);
+		}
+
+		flush_signals_thread();
+
+	} while (err != _FAIL);
+
+exit:
+
+	RTW_INFO(FUNC_ADPT_FMT " Exit\n", FUNC_ADPT_ARG(adapter));
+
+	rtw_thread_wait_stop();
+
+	return 0;
+}
+#endif /* CONFIG_RECV_THREAD_MODE */
+
+#if DBG_RX_BH_TRACKING
+void rx_bh_tk_set_stage(struct recv_priv *recv, u32 s)
+{
+	recv->rx_bh_stage = s;
+}
+
+void rx_bh_tk_set_buf(struct recv_priv *recv, void *buf, void *data, u32 dlen)
+{
+	if (recv->rx_bh_cbuf)
+		recv->rx_bh_lbuf = recv->rx_bh_cbuf;
+	recv->rx_bh_cbuf = buf;
+	if (buf) {
+		recv->rx_bh_cbuf_data = data;
+		recv->rx_bh_cbuf_dlen = dlen;
+		recv->rx_bh_buf_dq_cnt++;
+	} else {
+		recv->rx_bh_cbuf_data = NULL;
+		recv->rx_bh_cbuf_dlen = 0;
+	}
+}
+
+void rx_bh_tk_set_buf_pos(struct recv_priv *recv, void *pos)
+{
+	if (recv->rx_bh_cbuf) {
+		recv->rx_bh_cbuf_pos = pos - recv->rx_bh_cbuf_data;
+	} else {
+		rtw_warn_on(1);
+		recv->rx_bh_cbuf_pos = 0;
+	}
+}
+
+void rx_bh_tk_set_frame(struct recv_priv *recv, void *frame)
+{
+	recv->rx_bh_cframe = frame;
+}
+
+void dump_rx_bh_tk(void *sel, struct recv_priv *recv)
+{
+	RTW_PRINT_SEL(sel, "[RXBHTK]s:%u, buf_dqc:%u, lbuf:%p, cbuf:%p, dlen:%u, pos:%u, cframe:%p\n"
+		, recv->rx_bh_stage
+		, recv->rx_bh_buf_dq_cnt
+		, recv->rx_bh_lbuf
+		, recv->rx_bh_cbuf
+		, recv->rx_bh_cbuf_dlen
+		, recv->rx_bh_cbuf_pos
+		, recv->rx_bh_cframe
+	);
+}
+#endif /* DBG_RX_BH_TRACKING */
+
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/core/rtw_rf.c linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/core/rtw_rf.c
--- linux-5.6.3/3rdparty/rtl8821ce/core/rtw_rf.c	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/core/rtw_rf.c	2020-04-10 16:35:06.778658294 +0300
@@ -0,0 +1,1384 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#define _RTW_RF_C_
+
+#include <drv_types.h>
+#include <hal_data.h>
+
+u8 center_ch_2g[CENTER_CH_2G_NUM] = {
+/* G00 */1, 2,
+/* G01 */3, 4, 5,
+/* G02 */6, 7, 8,
+/* G03 */9, 10, 11,
+/* G04 */12, 13,
+/* G05 */14
+};
+
+u8 center_ch_2g_40m[CENTER_CH_2G_40M_NUM] = {
+	3,
+	4,
+	5,
+	6,
+	7,
+	8,
+	9,
+	10,
+	11,
+};
+
+u8 op_chs_of_cch_2g_40m[CENTER_CH_2G_40M_NUM][2] = {
+	{1, 5}, /* 3 */
+	{2, 6}, /* 4 */
+	{3, 7}, /* 5 */
+	{4, 8}, /* 6 */
+	{5, 9}, /* 7 */
+	{6, 10}, /* 8 */
+	{7, 11}, /* 9 */
+	{8, 12}, /* 10 */
+	{9, 13}, /* 11 */
+};
+
+u8 center_ch_5g_all[CENTER_CH_5G_ALL_NUM] = {
+/* G00 */36, 38, 40,
+	42,
+/* G01 */44, 46, 48,
+	/* 50, */
+/* G02 */52, 54, 56,
+	58,
+/* G03 */60, 62, 64,
+/* G04 */100, 102, 104,
+	106,
+/* G05 */108, 110, 112,
+	/* 114, */
+/* G06 */116, 118, 120,
+	122,
+/* G07 */124, 126, 128,
+/* G08 */132, 134, 136,
+	138,
+/* G09 */140, 142, 144,
+/* G10 */149, 151, 153,
+	155,
+/* G11 */157, 159, 161,
+	/* 163, */
+/* G12 */165, 167, 169,
+	171,
+/* G13 */173, 175, 177
+};
+
+u8 center_ch_5g_20m[CENTER_CH_5G_20M_NUM] = {
+/* G00 */36, 40,
+/* G01 */44, 48,
+/* G02 */52, 56,
+/* G03 */60, 64,
+/* G04 */100, 104,
+/* G05 */108, 112,
+/* G06 */116, 120,
+/* G07 */124, 128,
+/* G08 */132, 136,
+/* G09 */140, 144,
+/* G10 */149, 153,
+/* G11 */157, 161,
+/* G12 */165, 169,
+/* G13 */173, 177
+};
+
+u8 center_ch_5g_40m[CENTER_CH_5G_40M_NUM] = {
+/* G00 */38,
+/* G01 */46,
+/* G02 */54,
+/* G03 */62,
+/* G04 */102,
+/* G05 */110,
+/* G06 */118,
+/* G07 */126,
+/* G08 */134,
+/* G09 */142,
+/* G10 */151,
+/* G11 */159,
+/* G12 */167,
+/* G13 */175
+};
+
+u8 center_ch_5g_20m_40m[CENTER_CH_5G_20M_NUM + CENTER_CH_5G_40M_NUM] = {
+/* G00 */36, 38, 40,
+/* G01 */44, 46, 48,
+/* G02 */52, 54, 56,
+/* G03 */60, 62, 64,
+/* G04 */100, 102, 104,
+/* G05 */108, 110, 112,
+/* G06 */116, 118, 120,
+/* G07 */124, 126, 128,
+/* G08 */132, 134, 136,
+/* G09 */140, 142, 144,
+/* G10 */149, 151, 153,
+/* G11 */157, 159, 161,
+/* G12 */165, 167, 169,
+/* G13 */173, 175, 177
+};
+
+u8 op_chs_of_cch_5g_40m[CENTER_CH_5G_40M_NUM][2] = {
+	{36, 40}, /* 38 */
+	{44, 48}, /* 46 */
+	{52, 56}, /* 54 */
+	{60, 64}, /* 62 */
+	{100, 104}, /* 102 */
+	{108, 112}, /* 110 */
+	{116, 120}, /* 118 */
+	{124, 128}, /* 126 */
+	{132, 136}, /* 134 */
+	{140, 144}, /* 142 */
+	{149, 153}, /* 151 */
+	{157, 161}, /* 159 */
+	{165, 169}, /* 167 */
+	{173, 177}, /* 175 */
+};
+
+u8 center_ch_5g_80m[CENTER_CH_5G_80M_NUM] = {
+/* G00 ~ G01*/42,
+/* G02 ~ G03*/58,
+/* G04 ~ G05*/106,
+/* G06 ~ G07*/122,
+/* G08 ~ G09*/138,
+/* G10 ~ G11*/155,
+/* G12 ~ G13*/171
+};
+
+u8 op_chs_of_cch_5g_80m[CENTER_CH_5G_80M_NUM][4] = {
+	{36, 40, 44, 48}, /* 42 */
+	{52, 56, 60, 64}, /* 58 */
+	{100, 104, 108, 112}, /* 106 */
+	{116, 120, 124, 128}, /* 122 */
+	{132, 136, 140, 144}, /* 138 */
+	{149, 153, 157, 161}, /* 155 */
+	{165, 169, 173, 177}, /* 171 */
+};
+
+u8 center_ch_5g_160m[CENTER_CH_5G_160M_NUM] = {
+/* G00 ~ G03*/50,
+/* G04 ~ G07*/114,
+/* G10 ~ G13*/163
+};
+
+u8 op_chs_of_cch_5g_160m[CENTER_CH_5G_160M_NUM][8] = {
+	{36, 40, 44, 48, 52, 56, 60, 64}, /* 50 */
+	{100, 104, 108, 112, 116, 120, 124, 128}, /* 114 */
+	{149, 153, 157, 161, 165, 169, 173, 177}, /* 163 */
+};
+
+struct center_chs_ent_t {
+	u8 ch_num;
+	u8 *chs;
+};
+
+struct center_chs_ent_t center_chs_2g_by_bw[] = {
+	{CENTER_CH_2G_NUM, center_ch_2g},
+	{CENTER_CH_2G_40M_NUM, center_ch_2g_40m},
+};
+
+struct center_chs_ent_t center_chs_5g_by_bw[] = {
+	{CENTER_CH_5G_20M_NUM, center_ch_5g_20m},
+	{CENTER_CH_5G_40M_NUM, center_ch_5g_40m},
+	{CENTER_CH_5G_80M_NUM, center_ch_5g_80m},
+	{CENTER_CH_5G_160M_NUM, center_ch_5g_160m},
+};
+
+/*
+ * Get center channel of smaller bandwidth by @param cch, @param bw, @param offset
+ * @cch: the given center channel
+ * @bw: the given bandwidth
+ * @offset: the given primary SC offset of the given bandwidth
+ *
+ * return center channel of smaller bandiwdth if valid, or 0
+ */
+u8 rtw_get_scch_by_cch_offset(u8 cch, u8 bw, u8 offset)
+{
+	u8 t_cch = 0;
+
+	if (bw == CHANNEL_WIDTH_20) {
+		t_cch = cch;
+		goto exit;
+	}
+
+	if (offset == HAL_PRIME_CHNL_OFFSET_DONT_CARE) {
+		rtw_warn_on(1);
+		goto exit;
+	}
+
+	/* 2.4G, 40MHz */
+	if (cch >= 3 && cch <= 11 && bw == CHANNEL_WIDTH_40) {
+		t_cch = (offset == HAL_PRIME_CHNL_OFFSET_UPPER) ? cch + 2 : cch - 2;
+		goto exit;
+	}
+
+	/* 5G, 160MHz */
+	if (cch >= 50 && cch <= 163 && bw == CHANNEL_WIDTH_160) {
+		t_cch = (offset == HAL_PRIME_CHNL_OFFSET_UPPER) ? cch + 8 : cch - 8;
+		goto exit;
+
+	/* 5G, 80MHz */
+	} else if (cch >= 42 && cch <= 171 && bw == CHANNEL_WIDTH_80) {
+		t_cch = (offset == HAL_PRIME_CHNL_OFFSET_UPPER) ? cch + 4 : cch - 4;
+		goto exit;
+
+	/* 5G, 40MHz */
+	} else if (cch >= 38 && cch <= 175 && bw == CHANNEL_WIDTH_40) {
+		t_cch = (offset == HAL_PRIME_CHNL_OFFSET_UPPER) ? cch + 2 : cch - 2;
+		goto exit;
+
+	} else {
+		rtw_warn_on(1);
+		goto exit;
+	}
+
+exit:
+	return t_cch;
+}
+
+struct op_chs_ent_t {
+	u8 ch_num;
+	u8 *chs;
+};
+
+struct op_chs_ent_t op_chs_of_cch_2g_by_bw[] = {
+	{1, center_ch_2g},
+	{2, (u8 *)op_chs_of_cch_2g_40m},
+};
+
+struct op_chs_ent_t op_chs_of_cch_5g_by_bw[] = {
+	{1, center_ch_5g_20m},
+	{2, (u8 *)op_chs_of_cch_5g_40m},
+	{4, (u8 *)op_chs_of_cch_5g_80m},
+	{8, (u8 *)op_chs_of_cch_5g_160m},
+};
+
+inline u8 center_chs_2g_num(u8 bw)
+{
+	if (bw > CHANNEL_WIDTH_40)
+		return 0;
+
+	return center_chs_2g_by_bw[bw].ch_num;
+}
+
+inline u8 center_chs_2g(u8 bw, u8 id)
+{
+	if (bw > CHANNEL_WIDTH_40)
+		return 0;
+
+	if (id >= center_chs_2g_num(bw))
+		return 0;
+
+	return center_chs_2g_by_bw[bw].chs[id];
+}
+
+inline u8 center_chs_5g_num(u8 bw)
+{
+	if (bw > CHANNEL_WIDTH_80)
+		return 0;
+
+	return center_chs_5g_by_bw[bw].ch_num;
+}
+
+inline u8 center_chs_5g(u8 bw, u8 id)
+{
+	if (bw > CHANNEL_WIDTH_80)
+		return 0;
+
+	if (id >= center_chs_5g_num(bw))
+		return 0;
+
+	return center_chs_5g_by_bw[bw].chs[id];
+}
+
+/*
+ * Get available op channels by @param cch, @param bw
+ * @cch: the given center channel
+ * @bw: the given bandwidth
+ * @op_chs: the pointer to return pointer of op channel array
+ * @op_ch_num: the pointer to return pointer of op channel number
+ *
+ * return valid (1) or not (0)
+ */
+u8 rtw_get_op_chs_by_cch_bw(u8 cch, u8 bw, u8 **op_chs, u8 *op_ch_num)
+{
+	int i;
+	struct center_chs_ent_t *c_chs_ent = NULL;
+	struct op_chs_ent_t *op_chs_ent = NULL;
+	u8 valid = 1;
+
+	if (cch <= 14
+		&& bw >= CHANNEL_WIDTH_20 && bw <= CHANNEL_WIDTH_40
+	) {
+		c_chs_ent = &center_chs_2g_by_bw[bw];
+		op_chs_ent = &op_chs_of_cch_2g_by_bw[bw];
+	} else if (cch >= 36 && cch <= 177
+		&& bw >= CHANNEL_WIDTH_20 && bw <= CHANNEL_WIDTH_160
+	) {
+		c_chs_ent = &center_chs_5g_by_bw[bw];
+		op_chs_ent = &op_chs_of_cch_5g_by_bw[bw];
+	} else {
+		valid = 0;
+		goto exit;
+	}
+
+	for (i = 0; i < c_chs_ent->ch_num; i++)
+		if (cch == *(c_chs_ent->chs + i))
+			break;
+
+	if (i == c_chs_ent->ch_num) {
+		valid = 0;
+		goto exit;
+	}
+
+	*op_chs = op_chs_ent->chs + op_chs_ent->ch_num * i;
+	*op_ch_num = op_chs_ent->ch_num;
+
+exit:
+	return valid;
+}
+
+u8 rtw_get_ch_group(u8 ch, u8 *group, u8 *cck_group)
+{
+	BAND_TYPE band = BAND_MAX;
+	s8 gp = -1, cck_gp = -1;
+
+	if (ch <= 14) {
+		band = BAND_ON_2_4G;
+
+		if (1 <= ch && ch <= 2)
+			gp = 0;
+		else if (3  <= ch && ch <= 5)
+			gp = 1;
+		else if (6  <= ch && ch <= 8)
+			gp = 2;
+		else if (9  <= ch && ch <= 11)
+			gp = 3;
+		else if (12 <= ch && ch <= 14)
+			gp = 4;
+		else
+			band = BAND_MAX;
+
+		if (ch == 14)
+			cck_gp = 5;
+		else
+			cck_gp = gp;
+	} else {
+		band = BAND_ON_5G;
+
+		if (36 <= ch && ch <= 42)
+			gp = 0;
+		else if (44   <= ch && ch <=  48)
+			gp = 1;
+		else if (50   <= ch && ch <=  58)
+			gp = 2;
+		else if (60   <= ch && ch <=  64)
+			gp = 3;
+		else if (100  <= ch && ch <= 106)
+			gp = 4;
+		else if (108  <= ch && ch <= 114)
+			gp = 5;
+		else if (116  <= ch && ch <= 122)
+			gp = 6;
+		else if (124  <= ch && ch <= 130)
+			gp = 7;
+		else if (132  <= ch && ch <= 138)
+			gp = 8;
+		else if (140  <= ch && ch <= 144)
+			gp = 9;
+		else if (149  <= ch && ch <= 155)
+			gp = 10;
+		else if (157  <= ch && ch <= 161)
+			gp = 11;
+		else if (165  <= ch && ch <= 171)
+			gp = 12;
+		else if (173  <= ch && ch <= 177)
+			gp = 13;
+		else
+			band = BAND_MAX;
+	}
+
+	if (band == BAND_MAX
+		|| (band == BAND_ON_2_4G && cck_gp == -1)
+		|| gp == -1
+	) {
+		RTW_WARN("%s invalid channel:%u", __func__, ch);
+		rtw_warn_on(1);
+		goto exit;
+	}
+
+	if (group)
+		*group = gp;
+	if (cck_group && band == BAND_ON_2_4G)
+		*cck_group = cck_gp;
+
+exit:
+	return band;
+}
+
+int rtw_ch2freq(int chan)
+{
+	/* see 802.11 17.3.8.3.2 and Annex J
+	* there are overlapping channel numbers in 5GHz and 2GHz bands */
+
+	/*
+	* RTK: don't consider the overlapping channel numbers: 5G channel <= 14,
+	* because we don't support it. simply judge from channel number
+	*/
+
+	if (chan >= 1 && chan <= 14) {
+		if (chan == 14)
+			return 2484;
+		else if (chan < 14)
+			return 2407 + chan * 5;
+	} else if (chan >= 36 && chan <= 177)
+		return 5000 + chan * 5;
+
+	return 0; /* not supported */
+}
+
+int rtw_freq2ch(int freq)
+{
+	/* see 802.11 17.3.8.3.2 and Annex J */
+	if (freq == 2484)
+		return 14;
+	else if (freq < 2484)
+		return (freq - 2407) / 5;
+	else if (freq >= 4910 && freq <= 4980)
+		return (freq - 4000) / 5;
+	else if (freq <= 45000) /* DMG band lower limit */
+		return (freq - 5000) / 5;
+	else if (freq >= 58320 && freq <= 64800)
+		return (freq - 56160) / 2160;
+	else
+		return 0;
+}
+
+bool rtw_chbw_to_freq_range(u8 ch, u8 bw, u8 offset, u32 *hi, u32 *lo)
+{
+	u8 c_ch;
+	u32 freq;
+	u32 hi_ret = 0, lo_ret = 0;
+	bool valid = _FALSE;
+
+	if (hi)
+		*hi = 0;
+	if (lo)
+		*lo = 0;
+
+	c_ch = rtw_get_center_ch(ch, bw, offset);
+	freq = rtw_ch2freq(c_ch);
+
+	if (!freq) {
+		rtw_warn_on(1);
+		goto exit;
+	}
+
+	if (bw == CHANNEL_WIDTH_80) {
+		hi_ret = freq + 40;
+		lo_ret = freq - 40;
+	} else if (bw == CHANNEL_WIDTH_40) {
+		hi_ret = freq + 20;
+		lo_ret = freq - 20;
+	} else if (bw == CHANNEL_WIDTH_20) {
+		hi_ret = freq + 10;
+		lo_ret = freq - 10;
+	} else
+		rtw_warn_on(1);
+
+	if (hi)
+		*hi = hi_ret;
+	if (lo)
+		*lo = lo_ret;
+
+	valid = _TRUE;
+
+exit:
+	return valid;
+}
+
+const char *const _ch_width_str[CHANNEL_WIDTH_MAX] = {
+	"20MHz",
+	"40MHz",
+	"80MHz",
+	"160MHz",
+	"80_80MHz",
+	"5MHz",
+	"10MHz",
+};
+
+const u8 _ch_width_to_bw_cap[CHANNEL_WIDTH_MAX] = {
+	BW_CAP_20M,
+	BW_CAP_40M,
+	BW_CAP_80M,
+	BW_CAP_160M,
+	BW_CAP_80_80M,
+	BW_CAP_5M,
+	BW_CAP_10M,
+};
+
+const char *const _band_str[] = {
+	"2.4G",
+	"5G",
+	"BOTH",
+	"BAND_MAX",
+};
+
+const u8 _band_to_band_cap[] = {
+	BAND_CAP_2G,
+	BAND_CAP_5G,
+	0,
+	0,
+};
+
+const u8 _rf_type_to_rf_tx_cnt[] = {
+	1, /*RF_1T1R*/
+	1, /*RF_1T2R*/
+	2, /*RF_2T2R*/
+	2, /*RF_2T3R*/
+	2, /*RF_2T4R*/
+	3, /*RF_3T3R*/
+	3, /*RF_3T4R*/
+	4, /*RF_4T4R*/
+	1, /*RF_TYPE_MAX*/
+};
+
+const u8 _rf_type_to_rf_rx_cnt[] = {
+	1, /*RF_1T1R*/
+	2, /*RF_1T2R*/
+	2, /*RF_2T2R*/
+	3, /*RF_2T3R*/
+	4, /*RF_2T4R*/
+	3, /*RF_3T3R*/
+	4, /*RF_3T4R*/
+	4, /*RF_4T4R*/
+	1, /*RF_TYPE_MAX*/
+};
+
+const char *const _regd_str[] = {
+	"NONE",
+	"FCC",
+	"MKK",
+	"ETSI",
+	"IC",
+	"KCC",
+	"ACMA",
+	"CHILE",
+	"WW",
+};
+
+#ifdef CONFIG_TXPWR_LIMIT
+void _dump_regd_exc_list(void *sel, struct rf_ctl_t *rfctl)
+{
+	struct regd_exc_ent *ent;
+	_list *cur, *head;
+
+	RTW_PRINT_SEL(sel, "regd_exc_num:%u\n", rfctl->regd_exc_num);
+
+	if (!rfctl->regd_exc_num)
+		goto exit;
+
+	RTW_PRINT_SEL(sel, "%-7s %-6s %-9s\n", "country", "domain", "regd_name");
+
+	head = &rfctl->reg_exc_list;
+	cur = get_next(head);
+
+	while ((rtw_end_of_queue_search(head, cur)) == _FALSE) {
+		u8 has_country;
+
+		ent = LIST_CONTAINOR(cur, struct regd_exc_ent, list);
+		cur = get_next(cur);
+		has_country = (ent->country[0] == '\0' && ent->country[1] == '\0') ? 0 : 1;
+
+		RTW_PRINT_SEL(sel, "     %c%c   0x%02x %s\n"
+			, has_country ? ent->country[0] : '0'
+			, has_country ? ent->country[1] : '0'
+			, ent->domain
+			, ent->regd_name
+		);
+	}
+
+exit:
+	return;
+}
+
+inline void dump_regd_exc_list(void *sel, struct rf_ctl_t *rfctl)
+{
+	_irqL irqL;
+
+	_enter_critical_mutex(&rfctl->txpwr_lmt_mutex, &irqL);
+	_dump_regd_exc_list(sel, rfctl);
+	_exit_critical_mutex(&rfctl->txpwr_lmt_mutex, &irqL);
+}
+
+void rtw_regd_exc_add_with_nlen(struct rf_ctl_t *rfctl, const char *country, u8 domain, const char *regd_name, u32 nlen)
+{
+	struct regd_exc_ent *ent;
+	_irqL irqL;
+
+	if (!regd_name || !nlen) {
+		rtw_warn_on(1);
+		goto exit;
+	}
+
+	ent = (struct regd_exc_ent *)rtw_zmalloc(sizeof(struct regd_exc_ent) + nlen + 1);
+	if (!ent)
+		goto exit;
+
+	_rtw_init_listhead(&ent->list);
+	if (country)
+		_rtw_memcpy(ent->country, country, 2);
+	ent->domain = domain;
+	_rtw_memcpy(ent->regd_name, regd_name, nlen);
+
+	_enter_critical_mutex(&rfctl->txpwr_lmt_mutex, &irqL);
+
+	rtw_list_insert_tail(&ent->list, &rfctl->reg_exc_list);
+	rfctl->regd_exc_num++;
+
+	_exit_critical_mutex(&rfctl->txpwr_lmt_mutex, &irqL);
+
+exit:
+	return;
+}
+
+inline void rtw_regd_exc_add(struct rf_ctl_t *rfctl, const char *country, u8 domain, const char *regd_name)
+{
+	rtw_regd_exc_add_with_nlen(rfctl, country, domain, regd_name, strlen(regd_name));
+}
+
+struct regd_exc_ent *_rtw_regd_exc_search(struct rf_ctl_t *rfctl, const char *country, u8 domain)
+{
+	struct regd_exc_ent *ent;
+	_list *cur, *head;
+	u8 match = 0;
+
+	head = &rfctl->reg_exc_list;
+	cur = get_next(head);
+
+	while ((rtw_end_of_queue_search(head, cur)) == _FALSE) {
+		u8 has_country;
+
+		ent = LIST_CONTAINOR(cur, struct regd_exc_ent, list);
+		cur = get_next(cur);
+		has_country = (ent->country[0] == '\0' && ent->country[1] == '\0') ? 0 : 1;
+
+		/* entry has country condition to match */
+		if (has_country) {
+			if (!country)
+				continue;
+			if (ent->country[0] != country[0]
+				|| ent->country[1] != country[1])
+				continue;
+		}
+
+		/* entry has domain condition to match */
+		if (ent->domain != 0xFF) {
+			if (domain == 0xFF)
+				continue;
+			if (ent->domain != domain)
+				continue;
+		}
+
+		match = 1;
+		break;
+	}
+
+	if (match)
+		return ent;
+	else
+		return NULL;
+}
+
+inline struct regd_exc_ent *rtw_regd_exc_search(struct rf_ctl_t *rfctl, const char *country, u8 domain)
+{
+	struct regd_exc_ent *ent;
+	_irqL irqL;
+
+	_enter_critical_mutex(&rfctl->txpwr_lmt_mutex, &irqL);
+	ent = _rtw_regd_exc_search(rfctl, country, domain);
+	_exit_critical_mutex(&rfctl->txpwr_lmt_mutex, &irqL);
+
+	return ent;
+}
+
+void rtw_regd_exc_list_free(struct rf_ctl_t *rfctl)
+{
+	struct regd_exc_ent *ent;
+	_irqL irqL;
+	_list *cur, *head;
+
+	_enter_critical_mutex(&rfctl->txpwr_lmt_mutex, &irqL);
+
+	head = &rfctl->reg_exc_list;
+	cur = get_next(head);
+
+	while ((rtw_end_of_queue_search(head, cur)) == _FALSE) {
+		ent = LIST_CONTAINOR(cur, struct regd_exc_ent, list);
+		cur = get_next(cur);
+		rtw_list_delete(&ent->list);
+		rtw_mfree((u8 *)ent, sizeof(struct regd_exc_ent) + strlen(ent->regd_name) + 1);
+	}
+	rfctl->regd_exc_num = 0;
+
+	_exit_critical_mutex(&rfctl->txpwr_lmt_mutex, &irqL);
+}
+
+void dump_txpwr_lmt(void *sel, _adapter *adapter)
+{
+#define TMP_STR_LEN 16
+	struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter);
+	struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter);
+	_irqL irqL;
+	char fmt[16];
+	char tmp_str[TMP_STR_LEN];
+	s8 *lmt_idx = NULL;
+	int bw, band, ch_num, tlrs, ntx_idx, rs, i, path;
+	u8 ch, n, rfpath_num;
+
+	_enter_critical_mutex(&rfctl->txpwr_lmt_mutex, &irqL);
+
+	_dump_regd_exc_list(sel, rfctl);
+	RTW_PRINT_SEL(sel, "\n");
+
+	if (!rfctl->txpwr_regd_num)
+		goto release_lock;
+
+	lmt_idx = rtw_malloc(sizeof(s8) * RF_PATH_MAX * rfctl->txpwr_regd_num);
+	if (!lmt_idx) {
+		RTW_ERR("%s alloc fail\n", __func__);
+		goto release_lock;
+	}
+
+	RTW_PRINT_SEL(sel, "txpwr_lmt_2g_cck_ofdm_state:0x%02x\n", rfctl->txpwr_lmt_2g_cck_ofdm_state);
+	#ifdef CONFIG_IEEE80211_BAND_5GHZ
+	if (IS_HARDWARE_TYPE_JAGUAR_AND_JAGUAR2(adapter))
+		RTW_PRINT_SEL(sel, "txpwr_lmt_5g_cck_ofdm_state:0x%02x\n", rfctl->txpwr_lmt_5g_cck_ofdm_state);
+		RTW_PRINT_SEL(sel, "txpwr_lmt_5g_20_40_ref:0x%02x\n", rfctl->txpwr_lmt_5g_20_40_ref);
+	#endif
+	RTW_PRINT_SEL(sel, "\n");
+
+	for (band = BAND_ON_2_4G; band <= BAND_ON_5G; band++) {
+		if (!hal_is_band_support(adapter, band))
+			continue;
+
+		rfpath_num = (band == BAND_ON_2_4G ? hal_spec->rfpath_num_2g : hal_spec->rfpath_num_5g);
+
+		for (bw = 0; bw < MAX_5G_BANDWIDTH_NUM; bw++) {
+
+			if (bw >= CHANNEL_WIDTH_160)
+				break;
+			if (band == BAND_ON_2_4G && bw >= CHANNEL_WIDTH_80)
+				break;
+
+			if (band == BAND_ON_2_4G)
+				ch_num = CENTER_CH_2G_NUM;
+			else
+				ch_num = center_chs_5g_num(bw);
+
+			if (ch_num == 0) {
+				rtw_warn_on(1);
+				break;
+			}
+
+			for (tlrs = TXPWR_LMT_RS_CCK; tlrs < TXPWR_LMT_RS_NUM; tlrs++) {
+
+				if (band == BAND_ON_2_4G && tlrs == TXPWR_LMT_RS_VHT)
+					continue;
+				if (band == BAND_ON_5G && tlrs == TXPWR_LMT_RS_CCK)
+					continue;
+				if (bw > CHANNEL_WIDTH_20 && (tlrs == TXPWR_LMT_RS_CCK || tlrs == TXPWR_LMT_RS_OFDM))
+					continue;
+				if (bw > CHANNEL_WIDTH_40 && tlrs == TXPWR_LMT_RS_HT)
+					continue;
+				if (tlrs == TXPWR_LMT_RS_VHT && !IS_HARDWARE_TYPE_JAGUAR_AND_JAGUAR2(adapter))
+					continue;
+
+				for (ntx_idx = RF_1TX; ntx_idx < MAX_TX_COUNT; ntx_idx++) {
+					struct txpwr_lmt_ent *ent;
+					_list *cur, *head;
+
+					if (ntx_idx >= hal_spec->tx_nss_num)
+						continue;
+
+					/* bypass CCK multi-TX is not defined */
+					if (tlrs == TXPWR_LMT_RS_CCK && ntx_idx > RF_1TX) {
+						if (band == BAND_ON_2_4G
+							&& !(rfctl->txpwr_lmt_2g_cck_ofdm_state & (TXPWR_LMT_HAS_CCK_1T << ntx_idx)))
+							continue;
+					}
+
+					/* bypass OFDM multi-TX is not defined */
+					if (tlrs == TXPWR_LMT_RS_OFDM && ntx_idx > RF_1TX) {
+						if (band == BAND_ON_2_4G
+							&& !(rfctl->txpwr_lmt_2g_cck_ofdm_state & (TXPWR_LMT_HAS_OFDM_1T << ntx_idx)))
+							continue;
+						#ifdef CONFIG_IEEE80211_BAND_5GHZ
+						if (band == BAND_ON_5G
+							&& !(rfctl->txpwr_lmt_5g_cck_ofdm_state & (TXPWR_LMT_HAS_OFDM_1T << ntx_idx)))
+							continue;
+						#endif
+					}
+
+					/* bypass 5G 20M, 40M pure reference */
+					#ifdef CONFIG_IEEE80211_BAND_5GHZ
+					if (band == BAND_ON_5G && (bw == CHANNEL_WIDTH_20 || bw == CHANNEL_WIDTH_40)) {
+						if (rfctl->txpwr_lmt_5g_20_40_ref == TXPWR_LMT_REF_HT_FROM_VHT) {
+							if (tlrs == TXPWR_LMT_RS_HT)
+								continue;
+						} else if (rfctl->txpwr_lmt_5g_20_40_ref == TXPWR_LMT_REF_VHT_FROM_HT) {
+							if (tlrs == TXPWR_LMT_RS_VHT && bw <= CHANNEL_WIDTH_40)
+								continue;
+						}
+					}
+					#endif
+
+					/* choose n-SS mapping rate section to get lmt diff value */
+					if (tlrs == TXPWR_LMT_RS_CCK)
+						rs = CCK;
+					else if (tlrs == TXPWR_LMT_RS_OFDM)
+						rs = OFDM;
+					else if (tlrs == TXPWR_LMT_RS_HT)
+						rs = HT_1SS + ntx_idx;
+					else if (tlrs == TXPWR_LMT_RS_VHT)
+						rs = VHT_1SS + ntx_idx;
+					else {
+						RTW_ERR("%s invalid tlrs %u\n", __func__, tlrs);
+						continue;
+					}
+
+					RTW_PRINT_SEL(sel, "[%s][%s][%s][%uT]\n"
+						, band_str(band)
+						, ch_width_str(bw)
+						, txpwr_lmt_rs_str(tlrs)
+						, ntx_idx + 1
+					);
+
+					/* header for limit in db */
+					RTW_PRINT_SEL(sel, "%3s ", "ch");
+
+					head = &rfctl->txpwr_lmt_list;
+					cur = get_next(head);
+					while ((rtw_end_of_queue_search(head, cur)) == _FALSE) {
+						ent = LIST_CONTAINOR(cur, struct txpwr_lmt_ent, list);
+						cur = get_next(cur);
+
+						sprintf(fmt, "%%%zus%%s ", strlen(ent->regd_name) >= 6 ? 1 : 6 - strlen(ent->regd_name));
+						snprintf(tmp_str, TMP_STR_LEN, fmt
+							, strcmp(ent->regd_name, rfctl->regd_name) == 0 ? "*" : ""
+							, ent->regd_name);
+						_RTW_PRINT_SEL(sel, "%s", tmp_str);
+					}
+					sprintf(fmt, "%%%zus%%s ", strlen(regd_str(TXPWR_LMT_WW)) >= 6 ? 1 : 6 - strlen(regd_str(TXPWR_LMT_WW)));
+					snprintf(tmp_str, TMP_STR_LEN, fmt
+						, strcmp(rfctl->regd_name, regd_str(TXPWR_LMT_WW)) == 0 ? "*" : ""
+						, regd_str(TXPWR_LMT_WW));
+					_RTW_PRINT_SEL(sel, "%s", tmp_str);
+
+					/* header for limit offset */
+					for (path = 0; path < RF_PATH_MAX; path++) {
+						if (path >= rfpath_num)
+							break;
+						_RTW_PRINT_SEL(sel, "|");
+						head = &rfctl->txpwr_lmt_list;
+						cur = get_next(head);
+						while ((rtw_end_of_queue_search(head, cur)) == _FALSE) {
+							ent = LIST_CONTAINOR(cur, struct txpwr_lmt_ent, list);
+							cur = get_next(cur);
+							_RTW_PRINT_SEL(sel, "%3c "
+								, strcmp(ent->regd_name, rfctl->regd_name) == 0 ? rf_path_char(path) : ' ');
+						}
+						_RTW_PRINT_SEL(sel, "%3c "
+								, strcmp(rfctl->regd_name, regd_str(TXPWR_LMT_WW)) == 0 ? rf_path_char(path) : ' ');
+					}
+					_RTW_PRINT_SEL(sel, "\n");
+
+					for (n = 0; n < ch_num; n++) {
+						s8 lmt;
+						s8 lmt_offset;
+						u8 base;
+
+						if (band == BAND_ON_2_4G)
+							ch = n + 1;
+						else
+							ch = center_chs_5g(bw, n);
+
+						if (ch == 0) {
+							rtw_warn_on(1);
+							break;
+						}
+
+						/* dump limit in db */
+						RTW_PRINT_SEL(sel, "%3u ", ch);
+						head = &rfctl->txpwr_lmt_list;
+						cur = get_next(head);
+						while ((rtw_end_of_queue_search(head, cur)) == _FALSE) {
+							ent = LIST_CONTAINOR(cur, struct txpwr_lmt_ent, list);
+							cur = get_next(cur);
+							lmt = phy_get_txpwr_lmt_abs(adapter, ent->regd_name, band, bw, tlrs, ntx_idx, ch, 0);
+							if (lmt == hal_spec->txgi_max) {
+								sprintf(fmt, "%%%zus ", strlen(ent->regd_name) >= 6 ? strlen(ent->regd_name) + 1 : 6);
+								snprintf(tmp_str, TMP_STR_LEN, fmt, "NA");
+								_RTW_PRINT_SEL(sel, "%s", tmp_str);
+							} else if (lmt > -hal_spec->txgi_pdbm && lmt < 0) { /* -0.xx */
+								sprintf(fmt, "%%%zus-0.%%d ", strlen(ent->regd_name) >= 6 ? strlen(ent->regd_name) - 4 : 1);
+								snprintf(tmp_str, TMP_STR_LEN, fmt, "", (rtw_abs(lmt) % hal_spec->txgi_pdbm) * 100 / hal_spec->txgi_pdbm);
+								_RTW_PRINT_SEL(sel, "%s", tmp_str);
+							} else if (lmt % hal_spec->txgi_pdbm) { /* d.xx */
+								sprintf(fmt, "%%%zud.%%d ", strlen(ent->regd_name) >= 6 ? strlen(ent->regd_name) - 2 : 3);
+								snprintf(tmp_str, TMP_STR_LEN, fmt, lmt / hal_spec->txgi_pdbm, (rtw_abs(lmt) % hal_spec->txgi_pdbm) * 100 / hal_spec->txgi_pdbm);
+								_RTW_PRINT_SEL(sel, "%s", tmp_str);
+							} else { /* d */
+								sprintf(fmt, "%%%zud ", strlen(ent->regd_name) >= 6 ? strlen(ent->regd_name) + 1 : 6);
+								snprintf(tmp_str, TMP_STR_LEN, fmt, lmt / hal_spec->txgi_pdbm);
+								_RTW_PRINT_SEL(sel, "%s", tmp_str);
+							}
+						}
+						lmt = phy_get_txpwr_lmt_abs(adapter, regd_str(TXPWR_LMT_WW), band, bw, tlrs, ntx_idx, ch, 0);
+						if (lmt == hal_spec->txgi_max) {
+							sprintf(fmt, "%%%zus ", strlen(regd_str(TXPWR_LMT_WW)) >= 6 ? strlen(regd_str(TXPWR_LMT_WW)) + 1 : 6);
+							snprintf(tmp_str, TMP_STR_LEN, fmt, "NA");
+							_RTW_PRINT_SEL(sel, "%s", tmp_str);
+						} else if (lmt > -hal_spec->txgi_pdbm && lmt < 0) { /* -0.xx */
+							sprintf(fmt, "%%%zus-0.%%d ", strlen(regd_str(TXPWR_LMT_WW)) >= 6 ? strlen(regd_str(TXPWR_LMT_WW)) - 4 : 1);
+							snprintf(tmp_str, TMP_STR_LEN, fmt, "", (rtw_abs(lmt) % hal_spec->txgi_pdbm) * 100 / hal_spec->txgi_pdbm);
+							_RTW_PRINT_SEL(sel, "%s", tmp_str);
+						} else if (lmt % hal_spec->txgi_pdbm) { /* d.xx */
+							sprintf(fmt, "%%%zud.%%d ", strlen(regd_str(TXPWR_LMT_WW)) >= 6 ? strlen(regd_str(TXPWR_LMT_WW)) - 2 : 3);
+							snprintf(tmp_str, TMP_STR_LEN, fmt, lmt / hal_spec->txgi_pdbm, (rtw_abs(lmt) % hal_spec->txgi_pdbm) * 100 / hal_spec->txgi_pdbm);
+							_RTW_PRINT_SEL(sel, "%s", tmp_str);
+						} else { /* d */
+							sprintf(fmt, "%%%zud ", strlen(regd_str(TXPWR_LMT_WW)) >= 6 ? strlen(regd_str(TXPWR_LMT_WW)) + 1 : 6);
+							snprintf(tmp_str, TMP_STR_LEN, fmt, lmt / hal_spec->txgi_pdbm);
+							_RTW_PRINT_SEL(sel, "%s", tmp_str);
+						}
+
+						/* dump limit offset of each path */
+						for (path = RF_PATH_A; path < RF_PATH_MAX; path++) {
+							if (path >= rfpath_num)
+								break;
+
+							base = PHY_GetTxPowerByRateBase(adapter, band, path, rs);
+
+							_RTW_PRINT_SEL(sel, "|");
+							head = &rfctl->txpwr_lmt_list;
+							cur = get_next(head);
+							i = 0;
+							while ((rtw_end_of_queue_search(head, cur)) == _FALSE) {
+								ent = LIST_CONTAINOR(cur, struct txpwr_lmt_ent, list);
+								cur = get_next(cur);
+								lmt_offset = phy_get_txpwr_lmt(adapter, ent->regd_name, band, bw, path, rs, ntx_idx, ch, 0);
+								if (lmt_offset == hal_spec->txgi_max) {
+									*(lmt_idx + i * RF_PATH_MAX + path) = hal_spec->txgi_max;
+									_RTW_PRINT_SEL(sel, "%3s ", "NA");
+								} else {
+									*(lmt_idx + i * RF_PATH_MAX + path) = lmt_offset + base;
+									_RTW_PRINT_SEL(sel, "%3d ", lmt_offset);
+								}
+								i++;
+							}
+							lmt_offset = phy_get_txpwr_lmt(adapter, regd_str(TXPWR_LMT_WW), band, bw, path, rs, ntx_idx, ch, 0);
+							if (lmt_offset == hal_spec->txgi_max)
+								_RTW_PRINT_SEL(sel, "%3s ", "NA");
+							else
+								_RTW_PRINT_SEL(sel, "%3d ", lmt_offset);
+
+						}
+
+						/* compare limit_idx of each path, print 'x' when mismatch */
+						if (rfpath_num > 1) {
+							for (i = 0; i < rfctl->txpwr_regd_num; i++) {
+								for (path = 0; path < RF_PATH_MAX; path++) {
+									if (path >= rfpath_num)
+										break;
+									if (*(lmt_idx + i * RF_PATH_MAX + path) != *(lmt_idx + i * RF_PATH_MAX + ((path + 1) % rfpath_num)))
+										break;
+								}
+								if (path >= rfpath_num)
+									_RTW_PRINT_SEL(sel, " ");
+								else
+									_RTW_PRINT_SEL(sel, "x");
+							}
+						}
+						_RTW_PRINT_SEL(sel, "\n");
+
+					}
+					RTW_PRINT_SEL(sel, "\n");
+				}
+			} /* loop for rate sections */
+		} /* loop for bandwidths */
+	} /* loop for bands */
+
+	if (lmt_idx)
+		rtw_mfree(lmt_idx, sizeof(s8) * RF_PATH_MAX * rfctl->txpwr_regd_num);
+
+release_lock:
+	_exit_critical_mutex(&rfctl->txpwr_lmt_mutex, &irqL);
+}
+
+/* search matcing first, if not found, alloc one */
+void rtw_txpwr_lmt_add_with_nlen(struct rf_ctl_t *rfctl, const char *regd_name, u32 nlen
+	, u8 band, u8 bw, u8 tlrs, u8 ntx_idx, u8 ch_idx, s8 lmt)
+{
+	struct hal_spec_t *hal_spec = GET_HAL_SPEC(dvobj_get_primary_adapter(rfctl_to_dvobj(rfctl)));
+	struct txpwr_lmt_ent *ent;
+	_irqL irqL;
+	_list *cur, *head;
+	s8 pre_lmt;
+
+	if (!regd_name || !nlen) {
+		rtw_warn_on(1);
+		goto exit;
+	}
+
+	_enter_critical_mutex(&rfctl->txpwr_lmt_mutex, &irqL);
+
+	/* search for existed entry */
+	head = &rfctl->txpwr_lmt_list;
+	cur = get_next(head);
+	while ((rtw_end_of_queue_search(head, cur)) == _FALSE) {
+		ent = LIST_CONTAINOR(cur, struct txpwr_lmt_ent, list);
+		cur = get_next(cur);
+
+		if (strlen(ent->regd_name) == nlen
+			&& _rtw_memcmp(ent->regd_name, regd_name, nlen) == _TRUE)
+			goto chk_lmt_val;
+	}
+
+	/* alloc new one */
+	ent = (struct txpwr_lmt_ent *)rtw_zvmalloc(sizeof(struct txpwr_lmt_ent) + nlen + 1);
+	if (!ent)
+		goto release_lock;
+
+	_rtw_init_listhead(&ent->list);
+	_rtw_memcpy(ent->regd_name, regd_name, nlen);
+	{
+		u8 j, k, l, m;
+
+		for (j = 0; j < MAX_2_4G_BANDWIDTH_NUM; ++j)
+			for (k = 0; k < TXPWR_LMT_RS_NUM_2G; ++k)
+				for (m = 0; m < CENTER_CH_2G_NUM; ++m)
+					for (l = 0; l < MAX_TX_COUNT; ++l)
+						ent->lmt_2g[j][k][m][l] = hal_spec->txgi_max;
+		#ifdef CONFIG_IEEE80211_BAND_5GHZ
+		for (j = 0; j < MAX_5G_BANDWIDTH_NUM; ++j)
+			for (k = 0; k < TXPWR_LMT_RS_NUM_5G; ++k)
+				for (m = 0; m < CENTER_CH_5G_ALL_NUM; ++m)
+					for (l = 0; l < MAX_TX_COUNT; ++l)
+						ent->lmt_5g[j][k][m][l] = hal_spec->txgi_max;
+		#endif
+	}
+
+	rtw_list_insert_tail(&ent->list, &rfctl->txpwr_lmt_list);
+	rfctl->txpwr_regd_num++;
+
+chk_lmt_val:
+	if (band == BAND_ON_2_4G)
+		pre_lmt = ent->lmt_2g[bw][tlrs][ch_idx][ntx_idx];
+	#ifdef CONFIG_IEEE80211_BAND_5GHZ
+	else if (band == BAND_ON_5G)
+		pre_lmt = ent->lmt_5g[bw][tlrs - 1][ch_idx][ntx_idx];
+	#endif
+	else
+		goto release_lock;
+
+	if (pre_lmt != hal_spec->txgi_max)
+		RTW_PRINT("duplicate txpwr_lmt for [%s][%s][%s][%s][%uT][%d]\n"
+			, regd_name, band_str(band), ch_width_str(bw), txpwr_lmt_rs_str(tlrs), ntx_idx + 1
+			, band == BAND_ON_2_4G ? ch_idx + 1 : center_ch_5g_all[ch_idx]);
+
+	lmt = rtw_min(pre_lmt, lmt);
+	if (band == BAND_ON_2_4G)
+		ent->lmt_2g[bw][tlrs][ch_idx][ntx_idx] = lmt;
+	#ifdef CONFIG_IEEE80211_BAND_5GHZ
+	else if (band == BAND_ON_5G)
+		ent->lmt_5g[bw][tlrs - 1][ch_idx][ntx_idx] = lmt;
+	#endif
+
+	if (0)
+		RTW_PRINT("%s, %4s, %6s, %7s, %uT, ch%3d = %d\n"
+			, regd_name, band_str(band), ch_width_str(bw), txpwr_lmt_rs_str(tlrs), ntx_idx + 1
+			, band == BAND_ON_2_4G ? ch_idx + 1 : center_ch_5g_all[ch_idx]
+			, lmt);
+
+release_lock:
+	_exit_critical_mutex(&rfctl->txpwr_lmt_mutex, &irqL);
+
+exit:
+	return;
+}
+
+inline void rtw_txpwr_lmt_add(struct rf_ctl_t *rfctl, const char *regd_name
+	, u8 band, u8 bw, u8 tlrs, u8 ntx_idx, u8 ch_idx, s8 lmt)
+{
+	rtw_txpwr_lmt_add_with_nlen(rfctl, regd_name, strlen(regd_name)
+		, band, bw, tlrs, ntx_idx, ch_idx, lmt);
+}
+
+struct txpwr_lmt_ent *_rtw_txpwr_lmt_get_by_name(struct rf_ctl_t *rfctl, const char *regd_name)
+{
+	struct txpwr_lmt_ent *ent;
+	_list *cur, *head;
+	u8 found = 0;
+
+	head = &rfctl->txpwr_lmt_list;
+	cur = get_next(head);
+
+	while ((rtw_end_of_queue_search(head, cur)) == _FALSE) {
+		ent = LIST_CONTAINOR(cur, struct txpwr_lmt_ent, list);
+		cur = get_next(cur);
+
+		if (strcmp(ent->regd_name, regd_name) == 0) {
+			found = 1;
+			break;
+		}
+	}
+
+	if (found)
+		return ent;
+	return NULL;
+}
+
+inline struct txpwr_lmt_ent *rtw_txpwr_lmt_get_by_name(struct rf_ctl_t *rfctl, const char *regd_name)
+{
+	struct txpwr_lmt_ent *ent;
+	_irqL irqL;
+
+	_enter_critical_mutex(&rfctl->txpwr_lmt_mutex, &irqL);
+	ent = _rtw_txpwr_lmt_get_by_name(rfctl, regd_name);
+	_exit_critical_mutex(&rfctl->txpwr_lmt_mutex, &irqL);
+
+	return ent;
+}
+
+void rtw_txpwr_lmt_list_free(struct rf_ctl_t *rfctl)
+{
+	struct txpwr_lmt_ent *ent;
+	_irqL irqL;
+	_list *cur, *head;
+
+	_enter_critical_mutex(&rfctl->txpwr_lmt_mutex, &irqL);
+
+	head = &rfctl->txpwr_lmt_list;
+	cur = get_next(head);
+
+	while ((rtw_end_of_queue_search(head, cur)) == _FALSE) {
+		ent = LIST_CONTAINOR(cur, struct txpwr_lmt_ent, list);
+		cur = get_next(cur);
+		if (ent->regd_name == rfctl->regd_name)
+			rfctl->regd_name = regd_str(TXPWR_LMT_NONE);
+		rtw_list_delete(&ent->list);
+		rtw_vmfree((u8 *)ent, sizeof(struct txpwr_lmt_ent) + strlen(ent->regd_name) + 1);
+	}
+	rfctl->txpwr_regd_num = 0;
+
+	_exit_critical_mutex(&rfctl->txpwr_lmt_mutex, &irqL);
+}
+#endif /* CONFIG_TXPWR_LIMIT */
+
+int rtw_ch_to_bb_gain_sel(int ch)
+{
+	int sel = -1;
+
+	if (ch >= 1 && ch <= 14)
+		sel = BB_GAIN_2G;
+#ifdef CONFIG_IEEE80211_BAND_5GHZ
+	else if (ch >= 36 && ch < 48)
+		sel = BB_GAIN_5GLB1;
+	else if (ch >= 52 && ch <= 64)
+		sel = BB_GAIN_5GLB2;
+	else if (ch >= 100 && ch <= 120)
+		sel = BB_GAIN_5GMB1;
+	else if (ch >= 124 && ch <= 144)
+		sel = BB_GAIN_5GMB2;
+	else if (ch >= 149 && ch <= 177)
+		sel = BB_GAIN_5GHB;
+#endif
+
+	return sel;
+}
+
+s8 rtw_rf_get_kfree_tx_gain_offset(_adapter *padapter, u8 path, u8 ch)
+{
+	s8 kfree_offset = 0;
+
+#ifdef CONFIG_RF_POWER_TRIM
+	struct kfree_data_t *kfree_data = GET_KFREE_DATA(padapter);
+	s8 bb_gain_sel = rtw_ch_to_bb_gain_sel(ch);
+
+	if (bb_gain_sel < BB_GAIN_2G || bb_gain_sel >= BB_GAIN_NUM) {
+		rtw_warn_on(1);
+		goto exit;
+	}
+
+	if (kfree_data->flag & KFREE_FLAG_ON) {
+		kfree_offset = kfree_data->bb_gain[bb_gain_sel][path];
+		if (IS_HARDWARE_TYPE_8723D(padapter))
+			RTW_INFO("%s path:%s, ch:%u, bb_gain_sel:%d, kfree_offset:%d\n"
+				, __func__, (path == 0)?"S1":"S0", 
+				ch, bb_gain_sel, kfree_offset);
+		else
+			RTW_INFO("%s path:%u, ch:%u, bb_gain_sel:%d, kfree_offset:%d\n"
+				, __func__, path, ch, bb_gain_sel, kfree_offset);
+	}
+exit:
+#endif /* CONFIG_RF_POWER_TRIM */
+	return kfree_offset;
+}
+
+void rtw_rf_set_tx_gain_offset(_adapter *adapter, u8 path, s8 offset)
+{
+#if !defined(CONFIG_RTL8814A) && !defined(CONFIG_RTL8822B) && !defined(CONFIG_RTL8821C)
+	u8 write_value;
+#endif
+	u8 target_path = 0;
+	u32 val32 = 0;
+
+	if (IS_HARDWARE_TYPE_8723D(adapter)) {
+		target_path = RF_PATH_A; /*in 8723D case path means S0/S1*/
+		if (path == PPG_8723D_S1)
+			RTW_INFO("kfree gain_offset 0x55:0x%x ",
+			rtw_hal_read_rfreg(adapter, target_path, 0x55, 0xffffffff));
+		else if (path == PPG_8723D_S0)
+			RTW_INFO("kfree gain_offset 0x65:0x%x ",
+			rtw_hal_read_rfreg(adapter, target_path, 0x65, 0xffffffff));
+	} else {
+		target_path = path;
+		RTW_INFO("kfree gain_offset 0x55:0x%x ", rtw_hal_read_rfreg(adapter, target_path, 0x55, 0xffffffff));
+	}
+	
+	switch (rtw_get_chip_type(adapter)) {
+#ifdef CONFIG_RTL8723D
+	case RTL8723D:
+		write_value = RF_TX_GAIN_OFFSET_8723D(offset);
+		if (path == PPG_8723D_S1)
+			rtw_hal_write_rfreg(adapter, target_path, 0x55, 0x0f8000, write_value);
+		else if (path == PPG_8723D_S0)
+			rtw_hal_write_rfreg(adapter, target_path, 0x65, 0x0f8000, write_value);
+		break;
+#endif /* CONFIG_RTL8723D */
+#ifdef CONFIG_RTL8703B
+	case RTL8703B:
+		write_value = RF_TX_GAIN_OFFSET_8703B(offset);
+		rtw_hal_write_rfreg(adapter, target_path, 0x55, 0x0fc000, write_value);
+		break;
+#endif /* CONFIG_RTL8703B */
+#ifdef CONFIG_RTL8188F
+	case RTL8188F:
+		write_value = RF_TX_GAIN_OFFSET_8188F(offset);
+		rtw_hal_write_rfreg(adapter, target_path, 0x55, 0x0fc000, write_value);
+		break;
+#endif /* CONFIG_RTL8188F */
+#ifdef CONFIG_RTL8188GTV
+	case RTL8188GTV:
+		write_value = RF_TX_GAIN_OFFSET_8188GTV(offset);
+		rtw_hal_write_rfreg(adapter, target_path, 0x55, 0x0fc000, write_value);
+		break;
+#endif /* CONFIG_RTL8188GTV */
+#ifdef CONFIG_RTL8192E
+	case RTL8192E:
+		write_value = RF_TX_GAIN_OFFSET_8192E(offset);
+		rtw_hal_write_rfreg(adapter, target_path, 0x55, 0x0f8000, write_value);
+		break;
+#endif /* CONFIG_RTL8188F */
+
+#ifdef CONFIG_RTL8821A
+	case RTL8821:
+		write_value = RF_TX_GAIN_OFFSET_8821A(offset);
+		rtw_hal_write_rfreg(adapter, target_path, 0x55, 0x0f8000, write_value);
+		break;
+#endif /* CONFIG_RTL8821A */
+#if defined(CONFIG_RTL8814A) || defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C) || defined(CONFIG_RTL8192F)
+	case RTL8814A:
+	case RTL8822B:
+	case RTL8821C:
+	case RTL8192F:
+		RTW_INFO("\nkfree by PhyDM on the sw CH. path %d\n", path);
+		break;
+#endif /* CONFIG_RTL8814A || CONFIG_RTL8822B || CONFIG_RTL8821C */
+
+	default:
+		rtw_warn_on(1);
+		break;
+	}
+	
+	if (IS_HARDWARE_TYPE_8723D(adapter)) {
+		if (path == PPG_8723D_S1)
+			val32 = rtw_hal_read_rfreg(adapter, target_path, 0x55, 0xffffffff);
+		else if (path == PPG_8723D_S0)
+			val32 = rtw_hal_read_rfreg(adapter, target_path, 0x65, 0xffffffff);
+	} else {
+		val32 = rtw_hal_read_rfreg(adapter, target_path, 0x55, 0xffffffff);
+	}
+	RTW_INFO(" after :0x%x\n", val32);
+}
+
+void rtw_rf_apply_tx_gain_offset(_adapter *adapter, u8 ch)
+{
+	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
+	s8 kfree_offset = 0;
+	s8 tx_pwr_track_offset = 0; /* TODO: 8814A should consider tx pwr track when setting tx gain offset */
+	s8 total_offset;
+	int i, total = 0;
+
+	if (IS_HARDWARE_TYPE_8723D(adapter))
+		total = 2; /* S1 and S0 */
+	else
+		total = hal_data->NumTotalRFPath;
+
+	for (i = 0; i < total; i++) {
+		kfree_offset = rtw_rf_get_kfree_tx_gain_offset(adapter, i, ch);
+		total_offset = kfree_offset + tx_pwr_track_offset;
+		rtw_rf_set_tx_gain_offset(adapter, i, total_offset);
+	}
+}
+
+inline u8 rtw_is_dfs_range(u32 hi, u32 lo)
+{
+	return rtw_is_range_overlap(hi, lo, 5720 + 10, 5260 - 10);
+}
+
+u8 rtw_is_dfs_ch(u8 ch)
+{
+	u32 hi, lo;
+
+	if (!rtw_chbw_to_freq_range(ch, CHANNEL_WIDTH_20, HAL_PRIME_CHNL_OFFSET_DONT_CARE, &hi, &lo))
+		return 0;
+
+	return rtw_is_dfs_range(hi, lo);
+}
+
+u8 rtw_is_dfs_chbw(u8 ch, u8 bw, u8 offset)
+{
+	u32 hi, lo;
+
+	if (!rtw_chbw_to_freq_range(ch, bw, offset, &hi, &lo))
+		return 0;
+
+	return rtw_is_dfs_range(hi, lo);
+}
+
+bool rtw_is_long_cac_range(u32 hi, u32 lo, u8 dfs_region)
+{
+	return (dfs_region == PHYDM_DFS_DOMAIN_ETSI && rtw_is_range_overlap(hi, lo, 5650, 5600)) ? _TRUE : _FALSE;
+}
+
+bool rtw_is_long_cac_ch(u8 ch, u8 bw, u8 offset, u8 dfs_region)
+{
+	u32 hi, lo;
+
+	if (rtw_chbw_to_freq_range(ch, bw, offset, &hi, &lo) == _FALSE)
+		return _FALSE;
+
+	return rtw_is_long_cac_range(hi, lo, dfs_region) ? _TRUE : _FALSE;
+}
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/core/rtw_rm.c linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/core/rtw_rm.c
--- linux-5.6.3/3rdparty/rtl8821ce/core/rtw_rm.c	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/core/rtw_rm.c	2020-04-10 16:35:06.778658294 +0300
@@ -0,0 +1,2470 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+
+#include <drv_types.h>
+#include <hal_data.h>
+#include "rtw_rm_fsm.h"
+
+#define pstr(s) s+strlen(s)
+
+u8 rm_post_event_hdl(_adapter *padapter, u8 *pbuf)
+{
+#ifdef CONFIG_RTW_80211K
+	struct rm_event *pev = (struct rm_event *)pbuf;
+
+	_rm_post_event(padapter, pev->rmid, pev->evid);
+	rm_handler(padapter, pev);
+#endif
+	return H2C_SUCCESS;
+}
+
+#ifdef CONFIG_RTW_80211K
+
+/* 802.11-2012 Table E-1 Operationg classes in United States */
+static RT_OPERATING_CLASS RTW_OP_CLASS_US[] = {
+	/* 0, OP_CLASS_NULL */	{  0,  0, {}},
+	/* 1, OP_CLASS_1 */	{115,  4, {36, 40, 44, 48}},
+	/* 2, OP_CLASS_2 */	{118,  4, {52, 56, 60, 64}},
+	/* 3, OP_CLASS_3 */	{124,  4, {149, 153, 157, 161}},
+	/* 4, OP_CLASS_4 */	{121, 11, {100, 104, 108, 112, 116, 120, 124,
+						128, 132, 136, 140}},
+	/* 5, OP_CLASS_5 */	{125,  5, {149, 153, 157, 161, 165}},
+	/* 6, OP_CLASS_12 */	{ 81, 11, {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11}}
+};
+
+struct cmd_meas_type_ {
+	u8 id;
+	char *name;
+};
+
+char *rm_type_req_name(u8 meas_type) {
+
+	switch (meas_type) {
+	case basic_req:
+		return "basic_req";
+	case cca_req:
+		return "cca_req";
+	case rpi_histo_req:
+		return "rpi_histo_req";
+	case ch_load_req:
+		return "ch_load_req";
+	case noise_histo_req:
+		return "noise_histo_req";
+	case bcn_req:
+		return "bcn_req";
+	case frame_req:
+		return "frame_req";
+	case sta_statis_req:
+		return "sta_statis_req";
+	}
+	return "unknown_req";
+};
+
+char *rm_type_rep_name(u8 meas_type) {
+
+	switch (meas_type) {
+	case basic_rep:
+		return "basic_rep";
+	case cca_rep:
+		return "cca_rep";
+	case rpi_histo_rep:
+		return "rpi_histo_rep";
+	case ch_load_rep:
+		return "ch_load_rep";
+	case noise_histo_rep:
+		return "noise_histo_rep";
+	case bcn_rep:
+		return "bcn_rep";
+	case frame_rep:
+		return "frame_rep";
+	case sta_statis_rep:
+		return "sta_statis_rep";
+	}
+	return "unknown_rep";
+};
+
+char *rm_en_cap_name(enum rm_cap_en en)
+{
+	switch (en) {
+	case RM_LINK_MEAS_CAP_EN:
+		return "RM_LINK_MEAS_CAP_EN";
+	case RM_NB_REP_CAP_EN:
+		return "RM_NB_REP_CAP_EN";
+	case RM_PARAL_MEAS_CAP_EN:
+		return "RM_PARAL_MEAS_CAP_EN";
+	case RM_REPEAT_MEAS_CAP_EN:
+		return "RM_REPEAT_MEAS_CAP_EN";
+	case RM_BCN_PASSIVE_MEAS_CAP_EN:
+		return "RM_BCN_PASSIVE_MEAS_CAP_EN";
+	case RM_BCN_ACTIVE_MEAS_CAP_EN:
+		return "RM_BCN_ACTIVE_MEAS_CAP_EN";
+	case RM_BCN_TABLE_MEAS_CAP_EN:
+		return "RM_BCN_TABLE_MEAS_CAP_EN";
+	case RM_BCN_MEAS_REP_COND_CAP_EN:
+		return "RM_BCN_MEAS_REP_COND_CAP_EN";
+
+	case RM_FRAME_MEAS_CAP_EN:
+		return "RM_FRAME_MEAS_CAP_EN";
+	case RM_CH_LOAD_CAP_EN:
+		return "RM_CH_LOAD_CAP_EN";
+	case RM_NOISE_HISTO_CAP_EN:
+		return "RM_NOISE_HISTO_CAP_EN";
+	case RM_STATIS_MEAS_CAP_EN:
+		return "RM_STATIS_MEAS_CAP_EN";
+	case RM_LCI_MEAS_CAP_EN:
+		return "RM_LCI_MEAS_CAP_EN";
+	case RM_LCI_AMIMUTH_CAP_EN:
+		return "RM_LCI_AMIMUTH_CAP_EN";
+	case RM_TRANS_STREAM_CAT_MEAS_CAP_EN:
+		return "RM_TRANS_STREAM_CAT_MEAS_CAP_EN";
+	case RM_TRIG_TRANS_STREAM_CAT_MEAS_CAP_EN:
+		return "RM_TRIG_TRANS_STREAM_CAT_MEAS_CAP_EN";
+
+	case RM_AP_CH_REP_CAP_EN:
+		return "RM_AP_CH_REP_CAP_EN";
+	case RM_RM_MIB_CAP_EN:
+		return "RM_RM_MIB_CAP_EN";
+	case RM_OP_CH_MAX_MEAS_DUR0:
+		return "RM_OP_CH_MAX_MEAS_DUR0";
+	case RM_OP_CH_MAX_MEAS_DUR1:
+		return "RM_OP_CH_MAX_MEAS_DUR1";
+	case RM_OP_CH_MAX_MEAS_DUR2:
+		return "RM_OP_CH_MAX_MEAS_DUR2";
+	case RM_NONOP_CH_MAX_MEAS_DUR0:
+		return "RM_NONOP_CH_MAX_MEAS_DUR0";
+	case RM_NONOP_CH_MAX_MEAS_DUR1:
+		return "RM_NONOP_CH_MAX_MEAS_DUR1";
+	case RM_NONOP_CH_MAX_MEAS_DUR2:
+		return "RM_NONOP_CH_MAX_MEAS_DUR2";
+
+	case RM_MEAS_PILOT_CAP0:
+		return "RM_MEAS_PILOT_CAP0";		/* 24-26 */
+	case RM_MEAS_PILOT_CAP1:
+		return "RM_MEAS_PILOT_CAP1";
+	case RM_MEAS_PILOT_CAP2:
+		return "RM_MEAS_PILOT_CAP2";
+	case RM_MEAS_PILOT_TRANS_INFO_CAP_EN:
+		return "RM_MEAS_PILOT_TRANS_INFO_CAP_EN";
+	case RM_NB_REP_TSF_OFFSET_CAP_EN:
+		return "RM_NB_REP_TSF_OFFSET_CAP_EN";
+	case RM_RCPI_MEAS_CAP_EN:
+		return "RM_RCPI_MEAS_CAP_EN";		/* 29 */
+	case RM_RSNI_MEAS_CAP_EN:
+		return "RM_RSNI_MEAS_CAP_EN";
+	case RM_BSS_AVG_ACCESS_DELAY_CAP_EN:
+		return "RM_BSS_AVG_ACCESS_DELAY_CAP_EN";
+
+	case RM_AVALB_ADMIS_CAPACITY_CAP_EN:
+		return "RM_AVALB_ADMIS_CAPACITY_CAP_EN";
+	case RM_ANT_CAP_EN:
+		return "RM_ANT_CAP_EN";
+	case RM_RSVD:
+	case RM_MAX:
+	default:
+		break;
+	}
+	return "unknown";
+}
+
+int rm_en_cap_chk_and_set(struct rm_obj *prm, enum rm_cap_en en)
+{
+	int idx;
+	u8 cap;
+
+
+	if (en >= RM_MAX)
+		return _FALSE;
+
+	idx = en / 8;
+	cap = prm->psta->padapter->rmpriv.rm_en_cap_def[idx];
+
+	if (!(cap & BIT(en - (idx*8)))) {
+		RTW_INFO("RM: %s incapable\n",rm_en_cap_name(en));
+		rm_set_rep_mode(prm, MEAS_REP_MOD_INCAP);
+		return _FALSE;
+	}
+	return _SUCCESS;
+}
+
+static u8 rm_get_oper_class_via_ch(u8 ch)
+{
+	int i,j,sz;
+
+
+	sz = sizeof(RTW_OP_CLASS_US)/sizeof(struct _RT_OPERATING_CLASS);
+
+	for (i = 0; i < sz; i++) {
+		for (j = 0; j < RTW_OP_CLASS_US[i].Len; j++) {
+			if ( ch == RTW_OP_CLASS_US[i].Channel[j]) {
+				RTW_INFO("RM: ch %u in oper_calss %u\n",
+					ch, RTW_OP_CLASS_US[i].global_op_class);
+				return RTW_OP_CLASS_US[i].global_op_class;
+				break;
+			}
+		}
+	}
+	return 0;
+}
+
+static u8 rm_get_ch_set(
+	struct rtw_ieee80211_channel *pch_set, u8 op_class, u8 ch_num)
+{
+	int i,j,sz;
+	u8 ch_amount = 0;
+
+
+	sz = sizeof(RTW_OP_CLASS_US)/sizeof(struct _RT_OPERATING_CLASS);
+
+	if (ch_num != 0) {
+		pch_set[0].hw_value = ch_num;
+		ch_amount = 1;
+		RTW_INFO("RM: meas_ch->hw_value = %u\n", pch_set->hw_value);
+		goto done;
+	}
+
+	for (i = 0; i < sz; i++) {
+
+		if (RTW_OP_CLASS_US[i].global_op_class == op_class) {
+
+			for (j = 0; j < RTW_OP_CLASS_US[i].Len; j++) {
+				pch_set[j].hw_value =
+					RTW_OP_CLASS_US[i].Channel[j];
+				RTW_INFO("RM: meas_ch[%d].hw_value = %u\n",
+					j, pch_set[j].hw_value);
+			}
+			ch_amount = RTW_OP_CLASS_US[i].Len;
+			break;
+		}
+	}
+done:
+	return ch_amount;
+}
+
+static int is_wildcard_bssid(u8 *bssid)
+{
+	int i;
+	u8 val8 = 0xff;
+
+
+	for (i=0;i<6;i++)
+		val8 &= bssid[i];
+
+	if (val8 == 0xff)
+		return _SUCCESS;
+	return _FALSE;
+}
+
+/* for caller outside rm */
+u8 rm_add_nb_req(_adapter *padapter, struct sta_info *psta)
+{
+	struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
+	struct mlme_ext_info *pmlmeinfo = &pmlmeext->mlmext_info;
+	struct rm_obj *prm;
+
+
+	prm = rm_alloc_rmobj(padapter);
+
+	if (prm == NULL) {
+		RTW_ERR("RM: unable to alloc rm obj for requeset\n");
+		return _FALSE;
+	}
+
+	prm->psta = psta;
+	prm->q.category = RTW_WLAN_CATEGORY_RADIO_MEAS;
+	prm->q.diag_token = pmlmeinfo->dialogToken++;
+	prm->q.m_token = 1;
+
+	prm->rmid = psta->cmn.aid << 16
+		| prm->q.diag_token << 8
+		| RM_MASTER;
+
+	prm->q.action_code = RM_ACT_NB_REP_REQ;
+
+	#if 0
+	if (pmac) { /* find sta_info according to bssid */
+		pmac += 4; /* skip mac= */
+		if (hwaddr_parse(pmac, bssid) == NULL) {
+			sprintf(pstr(s), "Err: \nincorrect mac format\n");
+			return _FAIL;
+		}
+		psta = rm_get_sta(padapter, 0xff, bssid);
+	}
+	#endif
+
+	/* enquee rmobj */
+	rm_enqueue_rmobj(padapter, prm, _FALSE);
+
+	RTW_INFO("RM: rmid=%x add req to " MAC_FMT "\n",
+		prm->rmid, MAC_ARG(psta->cmn.mac_addr));
+
+	return _SUCCESS;
+}
+
+
+static u8 *build_wlan_hdr(_adapter *padapter, struct xmit_frame *pmgntframe,
+	struct sta_info *psta, u16 frame_type)
+{
+	u8 *pframe;
+	u16 *fctrl;
+	struct pkt_attrib *pattr;
+	struct rtw_ieee80211_hdr *pwlanhdr;
+	struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
+	struct mlme_ext_info *pmlmeinfo = &pmlmeext->mlmext_info;
+
+
+	/* update attribute */
+	pattr = &pmgntframe->attrib;
+	update_mgntframe_attrib(padapter, pattr);
+
+	_rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET);
+
+	pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET;
+	pwlanhdr = (struct rtw_ieee80211_hdr *)pframe;
+
+	fctrl = &(pwlanhdr->frame_ctl);
+	*(fctrl) = 0;
+
+	_rtw_memcpy(pwlanhdr->addr1, psta->cmn.mac_addr, ETH_ALEN);
+	_rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN);
+	_rtw_memcpy(pwlanhdr->addr3,
+		get_my_bssid(&(pmlmeinfo->network)),ETH_ALEN);
+
+	RTW_INFO("RM: dst = " MAC_FMT "\n", MAC_ARG(pwlanhdr->addr1));
+
+	SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq);
+	pmlmeext->mgnt_seq++;
+	SetFragNum(pframe, 0);
+
+	set_frame_sub_type(pframe, WIFI_ACTION);
+
+	pframe += sizeof(struct rtw_ieee80211_hdr_3addr);
+	pattr->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr);
+
+	return pframe;
+}
+
+void rm_set_rep_mode(struct rm_obj *prm, u8 mode)
+{
+
+	RTW_INFO("RM: rmid=%x set %s\n",
+		prm->rmid,
+		mode|MEAS_REP_MOD_INCAP?"INCAP":
+		mode|MEAS_REP_MOD_REFUSE?"REFUSE":
+		mode|MEAS_REP_MOD_LATE?"LATE":"");
+
+	prm->p.m_mode |= mode;
+}
+
+int issue_null_reply(struct rm_obj *prm)
+{
+	int len=0, my_len;
+	u8 *pframe, m_mode;
+	_adapter *padapter = prm->psta->padapter;
+	struct pkt_attrib *pattr;
+	struct xmit_frame *pmgntframe;
+	struct xmit_priv *pxmitpriv = &(padapter->xmitpriv);
+
+
+	m_mode = prm->p.m_mode;
+	if (m_mode || prm->p.rpt == 0) {
+		RTW_INFO("RM: rmid=%x reply (%s repeat=%d)\n",
+			prm->rmid,
+			m_mode&MEAS_REP_MOD_INCAP?"INCAP":
+			m_mode&MEAS_REP_MOD_REFUSE?"REFUSE":
+			m_mode&MEAS_REP_MOD_LATE?"LATE":"no content",
+			prm->p.rpt);
+	}
+
+	switch (prm->p.action_code) {
+	case RM_ACT_RADIO_MEAS_REQ:
+		len = 8;
+		break;
+	case RM_ACT_NB_REP_REQ:
+		len = 3;
+		break;
+	case RM_ACT_LINK_MEAS_REQ:
+		len = 3;
+		break;
+	default:
+		break;
+	}
+
+	if (len==0)
+		return _FALSE;
+
+	pmgntframe = alloc_mgtxmitframe(pxmitpriv);
+	if (pmgntframe == NULL) {
+		RTW_ERR("RM: %s alloc xmit_frame fail\n",__func__);
+		return _FALSE;
+	}
+	pattr = &pmgntframe->attrib;
+	pframe = build_wlan_hdr(padapter, pmgntframe, prm->psta, WIFI_ACTION);
+	pframe = rtw_set_fixed_ie(pframe, 3, &prm->p.category, &pattr->pktlen);
+
+	my_len = 0;
+	if (len>5) {
+		prm->p.len = len - 3 - 2;
+		pframe = rtw_set_fixed_ie(pframe, len - 3,
+			&prm->p.e_id, &my_len);
+	}
+
+	pattr->pktlen += my_len;
+	pattr->last_txcmdsz = pattr->pktlen;
+	dump_mgntframe(padapter, pmgntframe);
+
+	return _SUCCESS;
+}
+
+int ready_for_scan(struct rm_obj *prm)
+{
+	_adapter *padapter = prm->psta->padapter;
+	u8 ssc_chk;
+
+	if (!rtw_is_adapter_up(padapter))
+		return _FALSE;
+
+	ssc_chk = rtw_sitesurvey_condition_check(padapter, _FALSE);
+
+	if (ssc_chk == SS_ALLOW)
+		return _SUCCESS;
+
+	return _FALSE;
+}
+
+int rm_sitesurvey(struct rm_obj *prm)
+{
+	int meas_ch_num=0;
+	u8 ch_num=0, op_class=0, val8;
+	struct rtw_ieee80211_channel *pch_set;
+	struct sitesurvey_parm parm;
+
+
+	RTW_INFO("RM: rmid=%x %s\n",prm->rmid, __func__);
+
+	pch_set = &prm->q.ch_set[0];
+
+	_rtw_memset(pch_set, 0,
+		sizeof(struct rtw_ieee80211_channel) * MAX_OP_CHANNEL_SET_NUM);
+
+	if (prm->q.ch_num == 0) {
+		/* ch_num=0   : scan all ch in operating class */
+		op_class = prm->q.op_class;
+
+	} else if (prm->q.ch_num == 255) {
+		/* 802.11 p.499 */
+		/* ch_num=255 : scan all ch in current operating class */
+		op_class = rm_get_oper_class_via_ch(
+			(u8)prm->psta->padapter->mlmeextpriv.cur_channel);
+	} else
+		ch_num = prm->q.ch_num;
+
+	/* get means channel */
+	meas_ch_num = rm_get_ch_set(pch_set, op_class, ch_num);
+	prm->q.ch_set_ch_amount = meas_ch_num;
+
+	_rtw_memset(&parm, 0, sizeof(struct sitesurvey_parm));
+	_rtw_memcpy(parm.ch, pch_set,
+		sizeof(struct rtw_ieee80211_channel) * MAX_OP_CHANNEL_SET_NUM);
+
+	_rtw_memcpy(&parm.ssid[0], &prm->q.opt.bcn.ssid, IW_ESSID_MAX_SIZE);
+
+	parm.ssid_num = 1;
+	parm.scan_mode = prm->q.m_mode;
+	parm.ch_num = meas_ch_num;
+	parm.igi = 0;
+	parm.token = prm->rmid;
+	parm.duration = prm->q.meas_dur;
+	/* parm.bw = BW_20M; */
+
+	rtw_sitesurvey_cmd(prm->psta->padapter, &parm);
+
+	return _SUCCESS;
+}
+
+static u8 translate_percentage_to_rcpi(u32 SignalStrengthIndex)
+{
+	s32 SignalPower; /* in dBm. */
+	u8 rcpi;
+
+	/* Translate to dBm (x=y-100) */
+	SignalPower = SignalStrengthIndex - 100;
+
+	/* RCPI = Int{(Power in dBm + 110)*2} for 0dBm > Power > -110dBm
+	 *    0	: power <= -110.0 dBm
+	 *    1	: power =  -109.5 dBm
+	 *    2	: power =  -109.0 dBm
+	 */
+
+	rcpi = (SignalPower + 110)*2;
+	return rcpi;
+}
+
+static int rm_parse_ch_load_s_elem(struct rm_obj *prm, u8 *pbody, int req_len)
+{
+	u8 *popt_id;
+	int i, p=0; /* position */
+	int len = req_len;
+
+
+	prm->q.opt_s_elem_len = len;
+#if (RM_MORE_DBG_MSG)
+	RTW_INFO("RM: opt_s_elem_len=%d\n", len);
+#endif
+	while (len) {
+
+		switch (pbody[p]) {
+		case ch_load_rep_info:
+			/* check RM_EN */
+			rm_en_cap_chk_and_set(prm, RM_CH_LOAD_CAP_EN);
+
+			_rtw_memcpy(&(prm->q.opt.clm.rep_cond),
+				&pbody[p+2], sizeof(prm->q.opt.clm.rep_cond));
+
+			RTW_INFO("RM: ch_load_rep_info=%u:%u\n",
+				prm->q.opt.clm.rep_cond.cond,
+				prm->q.opt.clm.rep_cond.threshold);
+			break;
+		default:
+			break;
+
+		}
+		len = len - (int)pbody[p+1] - 2;
+		p = p + (int)pbody[p+1] + 2;
+#if (RM_MORE_DBG_MSG)
+		RTW_INFO("RM: opt_s_elem_len=%d\n",len);
+#endif
+	}
+	return _SUCCESS;
+}
+
+static int rm_parse_noise_histo_s_elem(struct rm_obj *prm,
+	u8 *pbody, int req_len)
+{
+	u8 *popt_id;
+	int i, p=0; /* position */
+	int len = req_len;
+
+
+	prm->q.opt_s_elem_len = len;
+#if (RM_MORE_DBG_MSG)
+	RTW_INFO("RM: opt_s_elem_len=%d\n", len);
+#endif
+
+	while (len) {
+
+		switch (pbody[p]) {
+		case noise_histo_rep_info:
+			/* check RM_EN */
+			rm_en_cap_chk_and_set(prm, RM_NOISE_HISTO_CAP_EN);
+
+			_rtw_memcpy(&(prm->q.opt.nhm.rep_cond),
+				&pbody[p+2], sizeof(prm->q.opt.nhm.rep_cond));
+
+			RTW_INFO("RM: noise_histo_rep_info=%u:%u\n",
+				prm->q.opt.nhm.rep_cond.cond,
+				prm->q.opt.nhm.rep_cond.threshold);
+			break;
+		default:
+			break;
+
+       		}
+		len = len - (int)pbody[p+1] - 2;
+		p = p + (int)pbody[p+1] + 2;
+#if (RM_MORE_DBG_MSG)
+		RTW_INFO("RM: opt_s_elem_len=%d\n",len);
+#endif
+	}
+	return _SUCCESS;
+}
+
+static int rm_parse_bcn_req_s_elem(struct rm_obj *prm, u8 *pbody, int req_len)
+{
+	u8 *popt_id;
+	int i, p=0; /* position */
+	int len = req_len;
+
+
+	/* opt length,2:pbody[0]+ pbody[1] */
+	/* first opt id : pbody[18] */
+
+	prm->q.opt_s_elem_len = len;
+#if (RM_MORE_DBG_MSG)
+	RTW_INFO("RM: opt_s_elem_len=%d\n", len);
+#endif
+
+	popt_id = prm->q.opt.bcn.opt_id;
+	while (len && prm->q.opt.bcn.opt_id_num < BCN_REQ_OPT_MAX_NUM) {
+
+		switch (pbody[p]) {
+		case bcn_req_ssid:
+			RTW_INFO("bcn_req_ssid\n");
+
+#if (DBG_BCN_REQ_WILDCARD)
+			RTW_INFO("DBG set ssid to WILDCARD\n");
+#else
+#if (DBG_BCN_REQ_SSID)
+			RTW_INFO("DBG set ssid to %s\n",DBG_BCN_REQ_SSID_NAME);
+			i = strlen(DBG_BCN_REQ_SSID_NAME);
+			prm->q.opt.bcn.ssid.SsidLength = i;
+			_rtw_memcpy(&(prm->q.opt.bcn.ssid.Ssid),
+				DBG_BCN_REQ_SSID_NAME, i);
+
+#else /* original */
+			prm->q.opt.bcn.ssid.SsidLength = pbody[p+1];
+			_rtw_memcpy(&(prm->q.opt.bcn.ssid.Ssid),
+				&pbody[p+2], pbody[p+1]);
+#endif
+#endif
+
+			RTW_INFO("RM: bcn_req_ssid=%s\n",
+				prm->q.opt.bcn.ssid.Ssid);
+
+			popt_id[prm->q.opt.bcn.opt_id_num++] = pbody[p];
+			break;
+
+		case bcn_req_rep_info:
+			/* check RM_EN */
+			rm_en_cap_chk_and_set(prm, RM_BCN_MEAS_REP_COND_CAP_EN);
+
+			_rtw_memcpy(&(prm->q.opt.bcn.rep_cond),
+				&pbody[p+2], sizeof(prm->q.opt.bcn.rep_cond));
+
+			RTW_INFO("bcn_req_rep_info=%u:%u\n",
+				prm->q.opt.bcn.rep_cond.cond,
+				prm->q.opt.bcn.rep_cond.threshold);
+
+			/*popt_id[prm->q.opt.bcn.opt_id_num++] = pbody[p];*/
+			break;
+
+		case bcn_req_rep_detail:
+#if DBG_BCN_REQ_DETAIL
+			prm->q.opt.bcn.rep_detail = 2; /* all IE in beacon */
+#else
+			prm->q.opt.bcn.rep_detail = pbody[p+2];
+#endif
+			popt_id[prm->q.opt.bcn.opt_id_num++] = pbody[p];
+
+#if (RM_MORE_DBG_MSG)
+			RTW_INFO("RM: report_detail=%d\n",
+				prm->q.opt.bcn.rep_detail);
+#endif
+			break;
+
+		case bcn_req_req:
+			RTW_INFO("RM: bcn_req_req\n");
+
+			prm->q.opt.bcn.req_start = rtw_malloc(pbody[p+1]);
+
+			if (prm->q.opt.bcn.req_start == NULL) {
+				RTW_ERR("RM: req_start malloc fail!!\n");
+				break;
+			}
+
+			for (i = 0; i < pbody[p+1]; i++)
+				*((prm->q.opt.bcn.req_start)+i) =
+					pbody[p+2+i];
+
+			prm->q.opt.bcn.req_len = pbody[p+1];
+			popt_id[prm->q.opt.bcn.opt_id_num++] = pbody[p];
+			break;
+
+		case bcn_req_ac_ch_rep:
+#if (RM_MORE_DBG_MSG)
+			RTW_INFO("RM: bcn_req_ac_ch_rep\n");
+#endif
+			popt_id[prm->q.opt.bcn.opt_id_num++] = pbody[p];
+			break;
+
+		default:
+			break;
+
+       		}
+		len = len - (int)pbody[p+1] - 2;
+		p = p + (int)pbody[p+1] + 2;
+#if (RM_MORE_DBG_MSG)
+		RTW_INFO("RM: opt_s_elem_len=%d\n",len);
+#endif
+	}
+
+	return _SUCCESS;
+}
+
+static int rm_parse_meas_req(struct rm_obj *prm, u8 *pbody)
+{
+	int p; /* position */
+	int req_len;
+
+
+	req_len = (int)pbody[1];
+	p = 5;
+
+	prm->q.op_class = pbody[p++];
+	prm->q.ch_num = pbody[p++];
+	prm->q.rand_intvl = le16_to_cpu(*(u16*)(&pbody[p]));
+	p+=2;
+	prm->q.meas_dur = le16_to_cpu(*(u16*)(&pbody[p]));
+	p+=2;
+
+	if (prm->q.m_type == bcn_req) {
+		/*
+		 * 0: passive
+		 * 1: active
+		 * 2: bcn_table
+		 */
+		prm->q.m_mode = pbody[p++];
+
+		/* BSSID */
+		_rtw_memcpy(&(prm->q.bssid), &pbody[p], 6);
+		p+=6;
+
+		/*
+		 * default, used when Reporting detail subelement
+		 * is not included in Beacon Request
+		 */
+		prm->q.opt.bcn.rep_detail = 2;
+	}
+
+	if (req_len-(p-2) <= 0) /* without sub-element */
+		return _SUCCESS;
+
+	switch (prm->q.m_type) {
+	case bcn_req:
+		rm_parse_bcn_req_s_elem(prm, &pbody[p], req_len-(p-2));
+		break;
+	case ch_load_req:
+		rm_parse_ch_load_s_elem(prm, &pbody[p], req_len-(p-2));
+		break;
+	case noise_histo_req:
+		rm_parse_noise_histo_s_elem(prm, &pbody[p], req_len-(p-2));
+		break;
+	default:
+		break;
+	}
+
+	return _SUCCESS;
+}
+
+/* receive measurement request */
+int rm_recv_radio_mens_req(_adapter *padapter,
+	union recv_frame *precv_frame, struct sta_info *psta)
+{
+	struct rm_obj *prm;
+	struct rm_priv *prmpriv = &padapter->rmpriv;
+	u8 *pdiag_body = (u8 *)(precv_frame->u.hdr.rx_data +
+		sizeof(struct rtw_ieee80211_hdr_3addr));
+	u8 *pmeas_body = &pdiag_body[5];
+	u8 rmid, update = 0;
+
+
+#if 0
+	/* search existing rm_obj */
+	rmid = psta->cmn.aid << 16
+		| pdiag_body[2] << 8
+		| RM_SLAVE;
+
+	prm = rm_get_rmobj(padapter, rmid);
+	if (prm) {
+		RTW_INFO("RM: Found an exist meas rmid=%u\n", rmid);
+		update = 1;
+	} else
+#endif
+	prm = rm_alloc_rmobj(padapter);
+
+	if (prm == NULL) {
+		RTW_ERR("RM: unable to alloc rm obj for requeset\n");
+		return _FALSE;
+	}
+
+	prm->psta = psta;
+	prm->q.diag_token = pdiag_body[2];
+	prm->q.rpt = le16_to_cpu(*(u16*)(&pdiag_body[3]));
+
+	/* Figure 8-104 Measurement Requested format */
+	prm->q.e_id = pmeas_body[0];
+	prm->q.m_token = pmeas_body[2];
+	prm->q.m_mode = pmeas_body[3];
+	prm->q.m_type = pmeas_body[4];
+
+	prm->rmid = psta->cmn.aid << 16
+		| prm->q.diag_token << 8
+		| RM_SLAVE;
+
+	RTW_INFO("RM: rmid=%x, bssid " MAC_FMT "\n", prm->rmid,
+		MAC_ARG(prm->psta->cmn.mac_addr));
+
+#if (RM_MORE_DBG_MSG)
+	RTW_INFO("RM: element_id = %d\n", prm->q.e_id);
+	RTW_INFO("RM: length = %d\n", (int)pmeas_body[1]);
+	RTW_INFO("RM: meas_token = %d\n", prm->q.m_token);
+	RTW_INFO("RM: meas_mode = %d\n", prm->q.m_mode);
+	RTW_INFO("RM: meas_type = %d\n", prm->q.m_type);
+#endif
+
+	if (prm->q.e_id != _MEAS_REQ_IE_) /* 38 */
+		return _FALSE;
+
+	switch (prm->q.m_type) {
+	case bcn_req:
+		RTW_INFO("RM: recv beacon_request\n");
+		switch (prm->q.m_mode) {
+		case bcn_req_passive:
+			rm_en_cap_chk_and_set(prm, RM_BCN_PASSIVE_MEAS_CAP_EN);
+			break;
+		case bcn_req_active:
+			rm_en_cap_chk_and_set(prm, RM_BCN_ACTIVE_MEAS_CAP_EN);
+			break;
+		case bcn_req_bcn_table:
+			rm_en_cap_chk_and_set(prm, RM_BCN_TABLE_MEAS_CAP_EN);
+			break;
+		default:
+			rm_set_rep_mode(prm, MEAS_REP_MOD_INCAP);
+			break;
+		}
+		break;
+	case ch_load_req:
+		RTW_INFO("RM: recv ch_load_request\n");
+		rm_en_cap_chk_and_set(prm, RM_CH_LOAD_CAP_EN);
+		break;
+	case noise_histo_req:
+		RTW_INFO("RM: recv noise_histogram_request\n");
+		rm_en_cap_chk_and_set(prm, RM_NOISE_HISTO_CAP_EN);
+		break;
+	default:
+		RTW_INFO("RM: recv unknown request type 0x%02x\n",
+			prm->q.m_type);
+		rm_set_rep_mode(prm, MEAS_REP_MOD_INCAP);
+		goto done;
+       }
+	rm_parse_meas_req(prm, pmeas_body);
+done:
+	if (!update)
+		rm_enqueue_rmobj(padapter, prm, _FALSE);
+
+	return _SUCCESS;
+}
+
+/* receive measurement report */
+int rm_recv_radio_mens_rep(_adapter *padapter,
+	union recv_frame *precv_frame, struct sta_info *psta)
+{
+	int ret = _FALSE;
+	struct rm_obj *prm;
+	u32 rmid;
+	u8 *pdiag_body = (u8 *)(precv_frame->u.hdr.rx_data +
+		sizeof(struct rtw_ieee80211_hdr_3addr));
+	u8 *pmeas_body = &pdiag_body[3];
+
+
+	rmid = psta->cmn.aid << 16
+		| pdiag_body[2] << 8
+		| RM_MASTER;
+
+	prm = rm_get_rmobj(padapter, rmid);
+	if (prm == NULL)
+		return _FALSE;
+
+	prm->p.action_code = pdiag_body[1];
+	prm->p.diag_token = pdiag_body[2];
+
+	/* Figure 8-140 Measuremnt Report format */
+	prm->p.e_id = pmeas_body[0];
+	prm->p.m_token = pmeas_body[2];
+	prm->p.m_mode = pmeas_body[3];
+	prm->p.m_type = pmeas_body[4];
+
+	RTW_INFO("RM: rmid=%x, bssid " MAC_FMT "\n", prm->rmid,
+		MAC_ARG(prm->psta->cmn.mac_addr));
+
+#if (RM_MORE_DBG_MSG)
+	RTW_INFO("RM: element_id = %d\n", prm->p.e_id);
+	RTW_INFO("RM: length = %d\n", (int)pmeas_body[1]);
+	RTW_INFO("RM: meas_token = %d\n", prm->p.m_token);
+	RTW_INFO("RM: meas_mode = %d\n", prm->p.m_mode);
+	RTW_INFO("RM: meas_type = %d\n", prm->p.m_type);
+#endif
+	if (prm->p.e_id != _MEAS_RSP_IE_) /* 39 */
+		return _FALSE;
+
+	RTW_INFO("RM: recv %s\n", rm_type_rep_name(prm->p.m_type));
+	rm_post_event(padapter, prm->rmid, RM_EV_recv_rep);
+
+	return ret;
+}
+
+int rm_radio_mens_nb_rep(_adapter *padapter,
+	union recv_frame *precv_frame, struct sta_info *psta)
+{
+	u8 *pdiag_body = (u8 *)(precv_frame->u.hdr.rx_data +
+		sizeof(struct rtw_ieee80211_hdr_3addr));
+	u8 *pmeas_body = &pdiag_body[3];
+	u32 len = precv_frame->u.hdr.len;
+	u32 rmid;
+	struct rm_obj *prm;
+
+
+	rmid = psta->cmn.aid << 16
+		| pdiag_body[2] << 8
+		| RM_MASTER;
+
+	prm = rm_get_rmobj(padapter, rmid);
+	if (prm == NULL)
+		return _FALSE;
+
+	prm->p.action_code = pdiag_body[1];
+	prm->p.diag_token = pdiag_body[2];
+	prm->p.e_id = pmeas_body[0];
+
+	RTW_INFO("RM: rmid=%x, bssid " MAC_FMT "\n", prm->rmid,
+		MAC_ARG(prm->psta->cmn.mac_addr));
+
+#if (RM_MORE_DBG_MSG)
+	RTW_INFO("RM: element_id = %d\n", prm->p.e_id);
+	RTW_INFO("RM: length = %d\n", (int)pmeas_body[1]);
+#endif
+	rm_post_event(padapter, prm->rmid, RM_EV_recv_rep);
+
+#ifdef CONFIG_LAYER2_ROAMING
+	if (rtw_wnm_btm_candidates_survey(padapter
+			,(pdiag_body + 3)
+			,(len - sizeof(struct rtw_ieee80211_hdr_3addr))
+			,_FALSE) == _FAIL)
+		return _FALSE;
+#endif
+	rtw_cfg80211_rx_rrm_action(padapter, precv_frame);
+
+	return _TRUE;
+}
+
+unsigned int rm_on_action(_adapter *padapter, union recv_frame *precv_frame)
+{
+	u32 ret = _FAIL;
+	u8 *pframe = NULL;
+	u8 *pframe_body = NULL;
+	u8 action_code = 0;
+	u8 diag_token = 0;
+	struct rtw_ieee80211_hdr_3addr *whdr;
+	struct sta_info *psta;
+
+
+	pframe = precv_frame->u.hdr.rx_data;
+
+	/* check RA matches or not */
+	if (!_rtw_memcmp(adapter_mac_addr(padapter),
+		GetAddr1Ptr(pframe), ETH_ALEN))
+		goto exit;
+
+	whdr = (struct rtw_ieee80211_hdr_3addr *)pframe;
+	RTW_INFO("RM: %s bssid = " MAC_FMT "\n",
+		__func__, MAC_ARG(whdr->addr2));
+
+	psta = rtw_get_stainfo(&padapter->stapriv, whdr->addr2);
+
+        if (!psta) {
+		RTW_ERR("RM: psta not found\n");
+                goto exit;
+        }
+
+	pframe_body = (unsigned char *)(pframe +
+		sizeof(struct rtw_ieee80211_hdr_3addr));
+
+	/* Figure 8-438 radio measurement request frame Action field format */
+	/* Category = pframe_body[0] = 5 (Radio Measurement) */
+	action_code = pframe_body[1];
+	diag_token = pframe_body[2];
+
+#if (RM_MORE_DBG_MSG)
+	RTW_INFO("RM: %s radio_action=%x, diag_token=%x\n", __func__,
+		action_code, diag_token);
+#endif
+
+	switch (action_code) {
+
+	case RM_ACT_RADIO_MEAS_REQ:
+		RTW_INFO("RM: RM_ACT_RADIO_MEAS_REQ\n");
+		ret = rm_recv_radio_mens_req(padapter, precv_frame, psta);
+		break;
+
+	case RM_ACT_RADIO_MEAS_REP:
+		RTW_INFO("RM: RM_ACT_RADIO_MEAS_REP\n");
+		ret = rm_recv_radio_mens_rep(padapter, precv_frame, psta);
+		break;
+
+	case RM_ACT_LINK_MEAS_REQ:
+		RTW_INFO("RM: RM_ACT_LINK_MEAS_REQ\n");
+		break;
+
+	case RM_ACT_LINK_MEAS_REP:
+		RTW_INFO("RM: RM_ACT_LINK_MEAS_REP\n");
+		break;
+
+	case RM_ACT_NB_REP_REQ:
+		RTW_INFO("RM: RM_ACT_NB_REP_REQ\n");
+		break;
+
+	case RM_ACT_NB_REP_RESP:
+		RTW_INFO("RM: RM_ACT_NB_REP_RESP\n");
+		ret = rm_radio_mens_nb_rep(padapter, precv_frame, psta);
+		break;
+
+	default:
+		/* TODO reply incabable */
+		RTW_ERR("RM: unknown specturm management action %2x\n",
+			action_code);
+		break;
+	}
+exit:
+	return ret;
+}
+
+static u8 *rm_gen_bcn_detail_elem(_adapter *padapter, u8 *pframe,
+	struct rm_obj *prm, struct wlan_network *pnetwork,
+	unsigned int *fr_len)
+{
+	WLAN_BSSID_EX *pbss = &pnetwork->network;
+	unsigned int my_len;
+	int j, k, len;
+	u8 *plen;
+	u8 *ptr;
+	u8 val8, eid;
+
+
+	my_len = 0;
+	/* Reporting Detail values
+	 * 0: No fixed length fields or elements
+	 * 1: All fixed length fields and any requested elements
+	 *    in the Request info element if present
+	 * 2: All fixed length fields and elements
+	 * 3-255: Reserved
+	 */
+
+	/* report_detail = 0 */
+	if (prm->q.opt.bcn.rep_detail == 0
+		|| prm->q.opt.bcn.rep_detail > 2) {
+		return pframe;
+	}
+
+	/* ID */
+	val8 = 1; /* 1:reported frame body */
+	pframe = rtw_set_fixed_ie(pframe, 1, &val8, &my_len);
+
+	plen = pframe;
+	val8 = 0;
+	pframe = rtw_set_fixed_ie(pframe, 1, &val8, &my_len);
+
+	/* report_detail = 2 */
+	if (prm->q.opt.bcn.rep_detail == 2) {
+		pframe = rtw_set_fixed_ie(pframe, pbss->IELength - 4,
+			pbss->IEs, &my_len); /* -4 remove FCS */
+		goto done;
+	}
+
+	/* report_detail = 1 */
+	/* all fixed lenght fields */
+	pframe = rtw_set_fixed_ie(pframe,
+		_FIXED_IE_LENGTH_, pbss->IEs, &my_len);
+
+	for (j = 0; j < prm->q.opt.bcn.opt_id_num; j++) {
+		switch (prm->q.opt.bcn.opt_id[j]) {
+		case bcn_req_ssid:
+			/* SSID */
+#if (RM_MORE_DBG_MSG)
+			RTW_INFO("RM: bcn_req_ssid\n");
+#endif
+			pframe = rtw_set_ie(pframe, _SSID_IE_,
+				pbss->Ssid.SsidLength,
+				pbss->Ssid.Ssid, &my_len);
+			break;
+		case bcn_req_req:
+			if (prm->q.opt.bcn.req_start == NULL)
+				break;
+#if (RM_MORE_DBG_MSG)
+			RTW_INFO("RM: bcn_req_req");
+#endif
+			for (k=0; k<prm->q.opt.bcn.req_len; k++) {
+				eid = prm->q.opt.bcn.req_start[k];
+
+				val8 = pbss->IELength - _FIXED_IE_LENGTH_;
+				ptr = rtw_get_ie(pbss->IEs + _FIXED_IE_LENGTH_,
+					eid, &len, val8);
+
+				if (!ptr)
+					continue;
+#if (RM_MORE_DBG_MSG)
+				switch (eid) {
+				case EID_QBSSLoad:
+					RTW_INFO("RM: EID_QBSSLoad\n");
+					break;
+				case EID_HTCapability:
+					RTW_INFO("RM: EID_HTCapability\n");
+					break;
+				case _MDIE_:
+					RTW_INFO("RM: EID_MobilityDomain\n");
+					break;
+				default:
+					RTW_INFO("RM: EID %d todo\n",eid);
+					break;
+				}
+#endif
+				pframe = rtw_set_ie(pframe, eid,
+					len,ptr+2, &my_len);
+			} /* for() */
+			break;
+		case bcn_req_ac_ch_rep:
+		default:
+			RTW_INFO("RM: OPT %d TODO\n",prm->q.opt.bcn.opt_id[j]);
+			break;
+		}
+	}
+done:
+	/*
+	 * update my length
+	 * content length does NOT include ID and LEN
+	 */
+	val8 = my_len - 2;
+	rtw_set_fixed_ie(plen, 1, &val8, &j);
+
+	/* update length to caller */
+	*fr_len += my_len;
+
+	return pframe;
+}
+
+static u8 rm_get_rcpi(struct rm_obj *prm, struct wlan_network *pnetwork)
+{
+	return translate_percentage_to_rcpi(
+		pnetwork->network.PhyInfo.SignalStrength);
+}
+
+static u8 rm_get_rsni(struct rm_obj *prm, struct wlan_network *pnetwork)
+{
+	int i;
+	u8 val8, snr;
+	HAL_DATA_TYPE *pHalData = GET_HAL_DATA(prm->psta->padapter);
+
+
+	if (pnetwork->network.PhyInfo.is_cck_rate) {
+		/* current HW doesn't have CCK RSNI */
+		/* 255 indicates RSNI is unavailable */
+		val8 = 255;
+	} else {
+		snr = 0;
+		for (i = 0; i < pHalData->NumTotalRFPath; i++) {
+			snr += pnetwork->network.PhyInfo.rx_snr[i];
+		}
+		snr = snr / pHalData->NumTotalRFPath;
+		val8 = (u8)(snr + 10)*2;
+	}
+	return val8;
+}
+
+u8 rm_bcn_req_cond_mach(struct rm_obj *prm, struct wlan_network *pnetwork)
+{
+	u8 val8;
+
+
+	switch(prm->q.opt.bcn.rep_cond.cond) {
+	case bcn_rep_cond_immediately:
+		return _SUCCESS;
+	case bcn_req_cond_rcpi_greater:
+		val8 = rm_get_rcpi(prm, pnetwork);
+		if (val8 > prm->q.opt.bcn.rep_cond.threshold)
+			return _SUCCESS;
+		break;
+	case bcn_req_cond_rcpi_less:
+		val8 = rm_get_rcpi(prm, pnetwork);
+		if (val8 < prm->q.opt.bcn.rep_cond.threshold)
+			return _SUCCESS;
+		break;
+	case bcn_req_cond_rsni_greater:
+		val8 = rm_get_rsni(prm, pnetwork);
+		if (val8 != 255 && val8 > prm->q.opt.bcn.rep_cond.threshold)
+			return _SUCCESS;
+		break;
+	case bcn_req_cond_rsni_less:
+		val8 = rm_get_rsni(prm, pnetwork);
+		if (val8 != 255 && val8 < prm->q.opt.bcn.rep_cond.threshold)
+			return _SUCCESS;
+		break;
+	default:
+		RTW_ERR("RM: bcn_req cond %u not support\n",
+			prm->q.opt.bcn.rep_cond.cond);
+		break;
+	}
+	return _FALSE;
+}
+
+static u8 *rm_bcn_rep_fill_scan_resule (struct rm_obj *prm,
+	u8 *pframe, struct wlan_network *pnetwork, unsigned int *fr_len)
+{
+	int snr, i;
+	u8 val8, *plen;
+	u16 val16;
+	u32 val32;
+	u64 val64;
+	PWLAN_BSSID_EX pbss;
+	unsigned int my_len;
+	_adapter *padapter = prm->psta->padapter;
+
+
+	my_len = 0;
+	/* meas ID */
+	val8 = EID_MeasureReport;
+	pframe = rtw_set_fixed_ie(pframe, 1, &val8, &my_len);
+
+	/* remember position form elelment length */
+	plen = pframe;
+
+	/* meas_rpt_len */
+	/* default 3 = mode + token + type but no beacon content */
+	val8 = 3;
+	pframe = rtw_set_fixed_ie(pframe, 1, &val8, &my_len);
+
+	/* meas_token */
+	val8 = prm->q.m_token;
+	pframe = rtw_set_fixed_ie(pframe, 1, &val8, &my_len);
+
+	/* meas_rpt_mode F8-141 */
+	val8 = prm->p.m_mode;
+	pframe = rtw_set_fixed_ie(pframe, 1, &val8, &my_len);
+
+	/* meas_type T8-81 */
+	val8 = bcn_rep;
+	pframe = rtw_set_fixed_ie(pframe, 1, &val8, &my_len);
+
+	if (pnetwork == NULL)
+		goto done;
+
+	pframe = rtw_set_fixed_ie(pframe, 1, &prm->q.op_class, &my_len);
+
+	/* channel */
+	pbss = &pnetwork->network;
+	val8 = pbss->Configuration.DSConfig;
+	pframe = rtw_set_fixed_ie(pframe, 1, &val8, &my_len);
+
+	/* Actual Measurement StartTime */
+	val64 = cpu_to_le64(prm->meas_start_time);
+	pframe = rtw_set_fixed_ie(pframe, 8, (u8 *)&val64, &my_len);
+
+	/* Measurement Duration */
+	val16 = prm->meas_end_time - prm->meas_start_time;
+	val16 = cpu_to_le16(val16);
+	pframe = rtw_set_fixed_ie(pframe, 2, (u8 *)&val16, &my_len);
+
+	/* TODO
+	 * ReportedFrameInformation:
+	 * 0 :beacon or probe rsp
+	 * 1 :pilot frame
+	 */
+	val8 = 0; /* report frame info */
+	pframe = rtw_set_fixed_ie(pframe, 1, &val8, &my_len);
+
+	/* RCPI */
+	val8 = rm_get_rcpi(prm, pnetwork);
+	pframe = rtw_set_fixed_ie(pframe, 1, &val8, &my_len);
+
+	/* RSNI */
+	val8 = rm_get_rsni(prm, pnetwork);
+	pframe = rtw_set_fixed_ie(pframe, 1, &val8, &my_len);
+
+	/* BSSID */
+	pframe = rtw_set_fixed_ie(pframe, 6, (u8 *)&pbss->MacAddress, &my_len);
+
+	/*
+	 * AntennaID
+	 * 0: unknown
+	 * 255: multiple antenna (Diversity)
+	 */
+	val8 = 0;
+	pframe = rtw_set_fixed_ie(pframe, 1, &val8, &my_len);
+
+	/* ParentTSF */
+	val32 = prm->meas_start_time + pnetwork->network.PhyInfo.free_cnt;
+	pframe = rtw_set_fixed_ie(pframe, 4, (u8 *)&val32, &my_len);
+
+	/*
+	 * Generate Beacon detail
+	 */
+	pframe = rm_gen_bcn_detail_elem(padapter, pframe,
+		prm, pnetwork, &my_len);
+done:
+	/*
+	 * update my length
+	 * content length does NOT include ID and LEN
+	 */
+	val8 = my_len - 2;
+	rtw_set_fixed_ie(plen, 1, &val8, &i);
+
+	/* update length to caller */
+	*fr_len += my_len;
+
+	return pframe;
+}
+
+static u8 *rm_gen_bcn_rep_ie (struct rm_obj *prm,
+	u8 *pframe, struct wlan_network *pnetwork, unsigned int *fr_len)
+{
+	int snr, i;
+	u8 val8, *plen;
+	u16 val16;
+	u32 val32;
+	u64 val64;
+	unsigned int my_len;
+	_adapter *padapter = prm->psta->padapter;
+
+
+	my_len = 0;
+	plen = pframe + 1;
+	pframe = rtw_set_fixed_ie(pframe, 7, &prm->p.e_id, &my_len);
+
+	/* Actual Measurement StartTime */
+	val64 = cpu_to_le64(prm->meas_start_time);
+	pframe = rtw_set_fixed_ie(pframe, 8, (u8 *)&val64, &my_len);
+
+	/* Measurement Duration */
+	val16 = prm->meas_end_time - prm->meas_start_time;
+	val16 = cpu_to_le16(val16);
+	pframe = rtw_set_fixed_ie(pframe, 2, (u8*)&val16, &my_len);
+
+	/* TODO
+	* ReportedFrameInformation:
+	* 0 :beacon or probe rsp
+	* 1 :pilot frame
+	*/
+	val8 = 0; /* report frame info */
+	pframe = rtw_set_fixed_ie(pframe, 1, &val8, &my_len);
+
+	/* RCPI */
+	val8 = rm_get_rcpi(prm, pnetwork);
+	pframe = rtw_set_fixed_ie(pframe, 1, &val8, &my_len);
+
+	/* RSNI */
+	val8 = rm_get_rsni(prm, pnetwork);
+	pframe = rtw_set_fixed_ie(pframe, 1, &val8, &my_len);
+
+	/* BSSID */
+	pframe = rtw_set_fixed_ie(pframe, 6,
+		(u8 *)&pnetwork->network.MacAddress, &my_len);
+
+	/*
+	 * AntennaID
+	 * 0: unknown
+	 * 255: multiple antenna (Diversity)
+	 */
+	val8 = 0;
+	pframe = rtw_set_fixed_ie(pframe, 1, &val8, &my_len);
+
+	/* ParentTSF */
+	val32 = prm->meas_start_time + pnetwork->network.PhyInfo.free_cnt;
+	pframe = rtw_set_fixed_ie(pframe, 4, (u8 *)&val32, &my_len);
+
+	/* Generate Beacon detail */
+	pframe = rm_gen_bcn_detail_elem(padapter, pframe,
+		prm, pnetwork, &my_len);
+done:
+	/*
+	* update my length
+	* content length does NOT include ID and LEN
+	*/
+	val8 = my_len - 2;
+	rtw_set_fixed_ie(plen, 1, &val8, &i);
+
+	/* update length to caller */
+	*fr_len += my_len;
+
+	return pframe;
+}
+
+static int retrieve_scan_result(struct rm_obj *prm)
+{
+	_irqL irqL;
+	_list *plist, *phead;
+	_queue *queue;
+	_adapter *padapter = prm->psta->padapter;
+	struct rtw_ieee80211_channel *pch_set;
+	struct wlan_network *pnetwork = NULL;
+	struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
+	int i, meas_ch_num=0;
+	PWLAN_BSSID_EX pbss;
+	unsigned int matched_network;
+	int len, my_len;
+	u8 buf_idx, *pbuf = NULL, *tmp_buf = NULL;
+
+
+	tmp_buf = rtw_malloc(MAX_XMIT_EXTBUF_SZ);
+	if (tmp_buf == NULL)
+		return 0;
+
+	my_len = 0;
+	buf_idx = 0;
+	matched_network = 0;
+	queue = &(pmlmepriv->scanned_queue);
+
+	_enter_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);
+
+	phead = get_list_head(queue);
+	plist = get_next(phead);
+
+	/* get requested measurement channel set */
+	pch_set = prm->q.ch_set;
+	meas_ch_num = prm->q.ch_set_ch_amount;
+
+	/* search scan queue to find requested SSID */
+	while (1) {
+
+		if (rtw_end_of_queue_search(phead, plist) == _TRUE)
+			break;
+
+		pnetwork = LIST_CONTAINOR(plist, struct wlan_network, list);
+		pbss = &pnetwork->network;
+
+		/*
+		* report network if requested channel set contains
+		* the channel matchs selected network
+		*/
+		if (rtw_chset_search_ch(adapter_to_chset(padapter),
+			pbss->Configuration.DSConfig) == 0)
+			goto next;
+
+		if (rtw_mlme_band_check(padapter, pbss->Configuration.DSConfig)
+			== _FALSE)
+			goto next;
+
+		if (rtw_validate_ssid(&(pbss->Ssid)) == _FALSE)
+			goto next;
+
+		/* go through measurement requested channels */
+		for (i = 0; i < meas_ch_num; i++) {
+
+			/* match channel */
+			if (pch_set[i].hw_value != pbss->Configuration.DSConfig)
+				continue;
+
+			/* match bssid */
+			if (is_wildcard_bssid(prm->q.bssid) == FALSE)
+				if (_rtw_memcmp(prm->q.bssid,
+					pbss->MacAddress, 6) == _FALSE) {
+					continue;
+				}
+			/*
+			 * default wildcard SSID. wildcard SSID:
+			 * A SSID value (null) used to represent all SSIDs
+			 */
+
+			/* match ssid */
+			if ((prm->q.opt.bcn.ssid.SsidLength > 0) &&
+				_rtw_memcmp(prm->q.opt.bcn.ssid.Ssid,
+				pbss->Ssid.Ssid,
+				prm->q.opt.bcn.ssid.SsidLength) == _FALSE)
+				continue;
+
+			/* match condition */
+			if (rm_bcn_req_cond_mach(prm, pnetwork) == _FALSE) {
+				RTW_INFO("RM: condition mismatch ch %u ssid %s bssid "MAC_FMT"\n",
+					pch_set[i].hw_value, pbss->Ssid.Ssid,
+					MAC_ARG(pbss->MacAddress));
+				RTW_INFO("RM: condition %u:%u\n",
+					prm->q.opt.bcn.rep_cond.cond,
+					prm->q.opt.bcn.rep_cond.threshold);
+				continue;
+			}
+
+			/* Found a matched SSID */
+			matched_network++;
+
+			RTW_INFO("RM: ch %u Found %s bssid "MAC_FMT"\n",
+				pch_set[i].hw_value, pbss->Ssid.Ssid,
+				MAC_ARG(pbss->MacAddress));
+
+			len = 0;
+			_rtw_memset(tmp_buf, 0, MAX_XMIT_EXTBUF_SZ);
+			rm_gen_bcn_rep_ie(prm, tmp_buf, pnetwork, &len);
+new_packet:
+			if (my_len == 0) {
+				pbuf = rtw_malloc(MAX_XMIT_EXTBUF_SZ);
+				if (pbuf == NULL)
+					goto fail;
+				prm->buf[buf_idx].pbuf = pbuf;
+			}
+
+			if ((MAX_XMIT_EXTBUF_SZ - (my_len+len+24+4)) > 0) {
+				pbuf = rtw_set_fixed_ie(pbuf,
+					len, tmp_buf, &my_len);
+				prm->buf[buf_idx].len = my_len;
+			} else {
+				if (my_len == 0) /* not enough space */
+					goto fail;
+
+				my_len = 0;
+				buf_idx++;
+				goto new_packet;
+			}
+		} /* for() */
+next:
+		plist = get_next(plist);
+	} /* while() */
+fail:
+	_exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);
+
+	if (tmp_buf)
+		rtw_mfree(tmp_buf, MAX_XMIT_EXTBUF_SZ);
+
+	RTW_INFO("RM: Found %d matched %s\n", matched_network,
+		prm->q.opt.bcn.ssid.Ssid);
+
+	if (prm->buf[buf_idx].pbuf)
+		return buf_idx+1;
+
+	return 0;
+}
+
+int issue_beacon_rep(struct rm_obj *prm)
+{
+	int i, my_len;
+	u8 *pframe;
+	_adapter *padapter = prm->psta->padapter;
+	struct pkt_attrib *pattr;
+	struct xmit_frame *pmgntframe;
+	struct xmit_priv *pxmitpriv = &(padapter->xmitpriv);
+	int pkt_num;
+
+
+	pkt_num = retrieve_scan_result(prm);
+
+	if (pkt_num == 0) {
+		issue_null_reply(prm);
+		return _SUCCESS;
+	}
+
+	for (i=0;i<pkt_num;i++) {
+
+		pmgntframe = alloc_mgtxmitframe(pxmitpriv);
+		if (pmgntframe == NULL) {
+			RTW_ERR("RM: %s alloc xmit_frame fail\n",__func__);
+			goto fail;
+		}
+		pattr = &pmgntframe->attrib;
+		pframe = build_wlan_hdr(padapter,
+			pmgntframe, prm->psta, WIFI_ACTION);
+		pframe = rtw_set_fixed_ie(pframe,
+			3, &prm->p.category, &pattr->pktlen);
+
+		my_len = 0;
+		pframe = rtw_set_fixed_ie(pframe,
+			prm->buf[i].len, prm->buf[i].pbuf, &my_len);
+
+		pattr->pktlen += my_len;
+		pattr->last_txcmdsz = pattr->pktlen;
+		dump_mgntframe(padapter, pmgntframe);
+	}
+fail:
+	for (i=0;i<pkt_num;i++) {
+		if (prm->buf[i].pbuf) {
+			rtw_mfree(prm->buf[i].pbuf, MAX_XMIT_EXTBUF_SZ);
+			prm->buf[i].pbuf = NULL;
+			prm->buf[i].len = 0;
+		}
+	}
+	return _SUCCESS;
+}
+
+/* neighbor request */
+int issue_nb_req(struct rm_obj *prm)
+{
+	_adapter *padapter = prm->psta->padapter;
+	struct sta_info *psta = prm->psta;
+	struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
+	struct xmit_priv *pxmitpriv = &padapter->xmitpriv;
+	struct xmit_frame *pmgntframe = NULL;
+	struct pkt_attrib *pattr = NULL;
+	u8 val8;
+	u8 *pframe = NULL;
+
+
+	RTW_INFO("RM: %s\n", __func__);
+
+	pmgntframe = alloc_mgtxmitframe(pxmitpriv);
+	if (pmgntframe == NULL) {
+		RTW_ERR("RM: %s alloc xmit_frame fail\n",__func__);
+		return _FALSE;
+	}
+	pattr = &pmgntframe->attrib;
+	pframe = build_wlan_hdr(padapter, pmgntframe, psta, WIFI_ACTION);
+	pframe = rtw_set_fixed_ie(pframe,
+		3, &prm->q.category, &pattr->pktlen);
+
+	if (prm->q.pssid) {
+
+		u8 sub_ie[64] = {0};
+		u8 *pie = &sub_ie[2];
+
+		RTW_INFO("RM: Send NB Req to "MAC_FMT" for(SSID) %s searching\n",
+			MAC_ARG(pmlmepriv->cur_network.network.MacAddress),
+			pmlmepriv->cur_network.network.Ssid.Ssid);
+
+		val8 = strlen(prm->q.pssid);
+		sub_ie[0] = 0; /*SSID*/
+		sub_ie[1] = val8;
+
+		_rtw_memcpy(pie, prm->q.pssid, val8);
+
+		pframe = rtw_set_fixed_ie(pframe, val8 + 2,
+			sub_ie, &pattr->pktlen);
+	} else {
+
+		if (!pmlmepriv->cur_network.network.Ssid.SsidLength)
+			RTW_INFO("RM: Send NB Req to "MAC_FMT"\n",
+				MAC_ARG(pmlmepriv->cur_network.network.MacAddress));
+		else {
+			u8 sub_ie[64] = {0};
+			u8 *pie = &sub_ie[2];
+
+			RTW_INFO("RM: Send NB Req to "MAC_FMT" for(SSID) %s searching\n",
+				MAC_ARG(pmlmepriv->cur_network.network.MacAddress),
+				pmlmepriv->cur_network.network.Ssid.Ssid);
+
+			sub_ie[0] = 0; /*SSID*/
+			sub_ie[1] = pmlmepriv->cur_network.network.Ssid.SsidLength;
+
+			_rtw_memcpy(pie, pmlmepriv->cur_network.network.Ssid.Ssid,
+				pmlmepriv->cur_network.network.Ssid.SsidLength);
+
+			pframe = rtw_set_fixed_ie(pframe,
+				pmlmepriv->cur_network.network.Ssid.SsidLength + 2,
+				sub_ie, &pattr->pktlen);
+		}
+	}
+
+	pattr->last_txcmdsz = pattr->pktlen;
+	dump_mgntframe(padapter, pmgntframe);
+
+	return _SUCCESS;
+}
+
+static u8 *rm_gen_bcn_req_s_elem(_adapter *padapter,
+	u8 *pframe, unsigned int *fr_len)
+{
+	u8 val8;
+	unsigned int my_len = 0;
+	u8 bssid[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
+
+
+	val8 = bcn_req_active; /* measurement mode T8-64 */
+	pframe = rtw_set_fixed_ie(pframe, 1, &val8, &my_len);
+
+	pframe = rtw_set_fixed_ie(pframe, 6, bssid, &my_len);
+
+	/* update length to caller */
+	*fr_len += my_len;
+
+	/* optional subelements */
+	return pframe;
+}
+
+static u8 *rm_gen_ch_load_req_s_elem(_adapter *padapter,
+	u8 *pframe, unsigned int *fr_len)
+{
+	u8 val8;
+	unsigned int my_len = 0;
+
+
+	val8 = 1; /* 1: channel load T8-60 */
+	pframe = rtw_set_fixed_ie(pframe, 1, &val8, &my_len);
+
+	val8 = 2; /* channel load length = 2 (extensible)  */
+	pframe = rtw_set_fixed_ie(pframe, 1, &val8, &my_len);
+
+	val8 = 0; /* channel load condition : 0 (issue when meas done) T8-61 */
+	pframe = rtw_set_fixed_ie(pframe, 1, &val8, &my_len);
+
+	val8 = 0; /* channel load reference value : 0 */
+	pframe = rtw_set_fixed_ie(pframe, 1, &val8, &my_len);
+
+	/* update length to caller */
+	*fr_len += my_len;
+
+	return pframe;
+}
+
+static u8 *rm_gen_noise_histo_req_s_elem(_adapter *padapter,
+	u8 *pframe, unsigned int *fr_len)
+{
+	u8 val8;
+	unsigned int my_len = 0;
+
+
+	val8 = 1; /* 1: noise histogram T8-62 */
+	pframe = rtw_set_fixed_ie(pframe, 1, &val8, &my_len);
+
+	val8 = 2; /* noise histogram length = 2 (extensible)  */
+	pframe = rtw_set_fixed_ie(pframe, 1, &val8, &my_len);
+
+	val8 = 0; /* noise histogram condition : 0 (issue when meas done) T8-63 */
+	pframe = rtw_set_fixed_ie(pframe, 1, &val8, &my_len);
+
+	val8 = 0; /* noise histogram reference value : 0 */
+	pframe = rtw_set_fixed_ie(pframe, 1, &val8, &my_len);
+
+	/* update length to caller */
+	*fr_len += my_len;
+
+	return pframe;
+}
+
+int issue_radio_meas_req(struct rm_obj *prm)
+{
+	u8 val8;
+	u8 *pframe;
+	u8 *plen;
+	u16 val16;
+	int my_len, i;
+	struct xmit_frame *pmgntframe;
+	struct pkt_attrib *pattr;
+	_adapter *padapter = prm->psta->padapter;
+	struct xmit_priv *pxmitpriv = &padapter->xmitpriv;
+
+
+	RTW_INFO("RM: %s - %s\n", __func__, rm_type_req_name(prm->q.m_type));
+
+	pmgntframe = alloc_mgtxmitframe(pxmitpriv);
+	if (pmgntframe == NULL) {
+		RTW_ERR("RM: %s alloc xmit_frame fail\n",__func__);
+		return _FALSE;
+	}
+	pattr = &pmgntframe->attrib;
+	pframe = build_wlan_hdr(padapter, pmgntframe, prm->psta, WIFI_ACTION);
+	pframe = rtw_set_fixed_ie(pframe, 3, &prm->q.category, &pattr->pktlen);
+
+	/* repeat */
+	val16 = cpu_to_le16(prm->q.rpt);
+	pframe = rtw_set_fixed_ie(pframe, 2,
+		(unsigned char *)&(val16), &pattr->pktlen);
+
+	my_len = 0;
+	plen = pframe + 1;
+	pframe = rtw_set_fixed_ie(pframe, 7, &prm->q.e_id, &my_len);
+
+	/* random interval */
+	val16 = 100; /* 100 TU */
+	val16 = cpu_to_le16(val16);
+	pframe = rtw_set_fixed_ie(pframe, 2, (u8 *)&val16, &my_len);
+
+	/* measurement duration */
+	val16 = 100;
+	val16 = cpu_to_le16(val16);
+	pframe = rtw_set_fixed_ie(pframe, 2, (u8 *)&val16, &my_len);
+
+	/* optional subelement */
+	switch (prm->q.m_type) {
+	case bcn_req:
+		pframe = rm_gen_bcn_req_s_elem(padapter, pframe, &my_len);
+		break;
+	case ch_load_req:
+		pframe = rm_gen_ch_load_req_s_elem(padapter, pframe, &my_len);
+		break;
+	case noise_histo_req:
+		pframe = rm_gen_noise_histo_req_s_elem(padapter,
+			pframe, &my_len);
+		break;
+	case basic_req:
+	default:
+		break;
+	}
+
+	/* length */
+	val8 = (u8)my_len - 2;
+	rtw_set_fixed_ie(plen, 1, &val8, &i);
+
+	pattr->pktlen += my_len;
+
+	pattr->last_txcmdsz = pattr->pktlen;
+	dump_mgntframe(padapter, pmgntframe);
+
+	return _SUCCESS;
+}
+
+/* noise histogram */
+static u8 rm_get_anpi(struct rm_obj *prm, struct wlan_network *pnetwork)
+{
+	return translate_percentage_to_rcpi(
+		pnetwork->network.PhyInfo.SignalStrength);
+}
+
+int rm_radio_meas_report_cond(struct rm_obj *prm)
+{
+	u8 val8;
+	int i;
+
+
+	switch (prm->q.m_type) {
+	case ch_load_req:
+
+		val8 = prm->p.ch_load;
+		switch (prm->q.opt.clm.rep_cond.cond) {
+		case ch_load_cond_immediately:
+			return _SUCCESS;
+		case ch_load_cond_anpi_equal_greater:
+			if (val8 >= prm->q.opt.clm.rep_cond.threshold)
+				return _SUCCESS;
+		case ch_load_cond_anpi_equal_less:
+			if (val8 <= prm->q.opt.clm.rep_cond.threshold)
+				return _SUCCESS;
+		default:
+			break;
+		}
+		break;
+	case noise_histo_req:
+		val8 = prm->p.anpi;
+		switch (prm->q.opt.nhm.rep_cond.cond) {
+		case noise_histo_cond_immediately:
+			return _SUCCESS;
+		case noise_histo_cond_anpi_equal_greater:
+			if (val8 >= prm->q.opt.nhm.rep_cond.threshold)
+				return _SUCCESS;
+			break;
+		case noise_histo_cond_anpi_equal_less:
+			if (val8 <= prm->q.opt.nhm.rep_cond.threshold)
+				return _SUCCESS;
+			break;
+		default:
+			break;
+		}
+		break;
+	default:
+		break;
+	}
+	return _FAIL;
+}
+
+int retrieve_radio_meas_result(struct rm_obj *prm)
+{
+	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(prm->psta->padapter);
+	int i, ch = -1;
+	u8 val8;
+
+
+	ch = rtw_chset_search_ch(adapter_to_chset(prm->psta->padapter),
+		prm->q.ch_num);
+
+	if ((ch == -1) || (ch >= MAX_CHANNEL_NUM)) {
+		RTW_ERR("RM: get ch(CH:%d) fail\n", prm->q.ch_num);
+		ch = 0;
+	}
+
+	switch (prm->q.m_type) {
+	case ch_load_req:
+#ifdef CONFIG_RTW_ACS
+		val8 = hal_data->acs.clm_ratio[ch];
+#else
+		val8 = 0;
+#endif
+		prm->p.ch_load = val8;
+		break;
+	case noise_histo_req:
+#ifdef CONFIG_RTW_ACS
+		/* ANPI */
+		prm->p.anpi = hal_data->acs.nhm_ratio[ch];
+
+		/* IPI 0~10 */
+		for (i=0;i<11;i++)
+			prm->p.ipi[i] = hal_data->acs.nhm[ch][i];
+		
+#else
+		val8 = 0;
+		prm->p.anpi = val8;
+		for (i=0;i<11;i++)
+			prm->p.ipi[i] = val8;
+#endif
+		break;
+	default:
+		break;
+	}
+	return _SUCCESS;
+}
+
+int issue_radio_meas_rep(struct rm_obj *prm)
+{
+	u8 val8;
+	u8 *pframe;
+	u8 *plen;
+	u16 val16;
+	u64 val64;
+	unsigned int my_len;
+	_adapter *padapter = prm->psta->padapter;
+	struct xmit_frame *pmgntframe;
+	struct pkt_attrib *pattr;
+	struct xmit_priv *pxmitpriv = &(padapter->xmitpriv);
+	struct sta_info *psta = prm->psta;
+	int i;
+
+
+	RTW_INFO("RM: %s\n", __func__);
+
+	pmgntframe = alloc_mgtxmitframe(pxmitpriv);
+	if (pmgntframe == NULL) {
+		RTW_ERR("RM: ERR %s alloc xmit_frame fail\n",__func__);
+		return _FALSE;
+	}
+	pattr = &pmgntframe->attrib;
+	pframe = build_wlan_hdr(padapter, pmgntframe, psta, WIFI_ACTION);
+	pframe = rtw_set_fixed_ie(pframe, 3,
+		&prm->p.category, &pattr->pktlen);
+
+	my_len = 0;
+	plen = pframe + 1;
+	pframe = rtw_set_fixed_ie(pframe, 7, &prm->p.e_id, &my_len);
+
+	/* Actual Meas start time - 8 bytes */
+	val64 = cpu_to_le64(prm->meas_start_time);
+	pframe = rtw_set_fixed_ie(pframe, 8, (u8 *)&val64, &my_len);
+
+	/* measurement duration */
+	val16 = prm->meas_end_time - prm->meas_start_time;
+	val16 = cpu_to_le16(val16);
+	pframe = rtw_set_fixed_ie(pframe, 2, (u8 *)&val16, &my_len);
+
+	/* optional subelement */
+	switch (prm->q.m_type) {
+	case ch_load_req:
+		val8 = prm->p.ch_load;
+		pframe = rtw_set_fixed_ie(pframe, 1, &val8, &my_len);
+		break;
+	case noise_histo_req:
+		/*
+		 * AntennaID
+		 * 0: unknown
+		 * 255: multiple antenna (Diversity)
+		 */
+		val8 = 0;
+		pframe = rtw_set_fixed_ie(pframe, 1, &val8, &my_len);
+		/* ANPI */
+		val8 = prm->p.anpi;
+		pframe = rtw_set_fixed_ie(pframe, 1, &val8, &my_len);
+		/* IPI 0~10 */
+		for (i=0;i<11;i++) {
+			val8 = prm->p.ipi[i];
+			pframe = rtw_set_fixed_ie(pframe, 1, &val8, &my_len);
+		}
+		break;
+	default:
+		break;
+	}
+done:
+	/* length */
+	val8 = (u8)my_len-2;
+	rtw_set_fixed_ie(plen, 1, &val8, &i); /* use variable i to ignore it */
+
+	pattr->pktlen += my_len;
+	pattr->last_txcmdsz = pattr->pktlen;
+	dump_mgntframe(padapter, pmgntframe);
+
+	return _SUCCESS;
+}
+
+void rtw_ap_parse_sta_rm_en_cap(_adapter *padapter,
+	struct sta_info *psta, struct rtw_ieee802_11_elems *elem)
+{
+	if (elem->rm_en_cap) {
+		RTW_INFO("assoc.rm_en_cap="RM_CAP_FMT"\n",
+			RM_CAP_ARG(elem->rm_en_cap));
+		_rtw_memcpy(psta->rm_en_cap,
+			(elem->rm_en_cap), elem->rm_en_cap_len);
+	}
+}
+
+void RM_IE_handler(_adapter *padapter, PNDIS_802_11_VARIABLE_IEs pIE)
+{
+	int i;
+
+	_rtw_memcpy(&padapter->rmpriv.rm_en_cap_assoc, pIE->data, pIE->Length);
+	RTW_INFO("assoc.rm_en_cap="RM_CAP_FMT"\n", RM_CAP_ARG(pIE->data));
+}
+
+/* Debug command */
+
+#if (RM_SUPPORT_IWPRIV_DBG)
+static int hex2num(char c)
+{
+	if (c >= '0' && c <= '9')
+		return c - '0';
+	if (c >= 'a' && c <= 'f')
+		return c - 'a' + 10;
+	if (c >= 'A' && c <= 'F')
+		return c - 'A' + 10;
+	return -1;
+}
+
+int hex2byte(const char *hex)
+{
+	int a, b;
+	a = hex2num(*hex++);
+	if (a < 0)
+		return -1;
+	b = hex2num(*hex++);
+	if (b < 0)
+		return -1;
+	return (a << 4) | b;
+}
+
+static char * hwaddr_parse(char *txt, u8 *addr)
+{
+	size_t i;
+
+	for (i = 0; i < ETH_ALEN; i++) {
+		int a;
+
+		a = hex2byte(txt);
+		if (a < 0)
+			return NULL;
+		txt += 2;
+		addr[i] = a;
+		if (i < ETH_ALEN - 1 && *txt++ != ':')
+			return NULL;
+	}
+	return txt;
+}
+
+void rm_dbg_list_sta(_adapter *padapter, char *s)
+{
+	int i;
+	_irqL irqL;
+	struct sta_info *psta;
+	struct sta_priv *pstapriv = &padapter->stapriv;
+	_list *plist, *phead;
+
+
+	sprintf(pstr(s), "\n");
+	_enter_critical_bh(&pstapriv->sta_hash_lock, &irqL);
+	for (i = 0; i < NUM_STA; i++) {
+		phead = &(pstapriv->sta_hash[i]);
+		plist = get_next(phead);
+
+		while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) {
+			psta = LIST_CONTAINOR(plist,
+				struct sta_info, hash_list);
+
+			plist = get_next(plist);
+
+			sprintf(pstr(s), "=========================================\n");
+			sprintf(pstr(s), "mac=" MAC_FMT "\n",
+				MAC_ARG(psta->cmn.mac_addr));
+			sprintf(pstr(s), "state=0x%x, aid=%d, macid=%d\n",
+				psta->state, psta->cmn.aid, psta->cmn.mac_id);
+			sprintf(pstr(s), "rm_cap="RM_CAP_FMT"\n",
+				RM_CAP_ARG(psta->rm_en_cap));
+		}
+
+	}
+	_exit_critical_bh(&pstapriv->sta_hash_lock, &irqL);
+	sprintf(pstr(s), "=========================================\n");
+}
+
+void rm_dbg_help(_adapter *padapter, char *s)
+{
+	int i;
+
+
+	sprintf(pstr(s), "\n");
+	sprintf(pstr(s), "rrm list_sta\n");
+	sprintf(pstr(s), "rrm list_meas\n");
+
+	sprintf(pstr(s), "rrm add_meas <aid=1|mac=>,m=<bcn|clm|nhm|nb>,rpt=\n");
+	sprintf(pstr(s), "rrm run_meas <aid=1|evid=>\n");
+	sprintf(pstr(s), "rrm del_meas\n");
+
+	sprintf(pstr(s), "rrm run_meas rmid=xxxx,ev=xx\n");
+	sprintf(pstr(s), "rrm activate\n");
+
+	for (i=0;i<RM_EV_max;i++)
+		sprintf(pstr(s), "\t%2d %s\n",i, rm_event_name(i) );
+	sprintf(pstr(s), "\n");
+}
+
+struct sta_info *rm_get_sta(_adapter *padapter, u16 aid, u8* pbssid)
+{
+	int i;
+	_irqL irqL;
+	struct sta_info *psta = NULL;
+	struct sta_priv *pstapriv = &padapter->stapriv;
+	_list *plist, *phead;
+
+
+	_enter_critical_bh(&pstapriv->sta_hash_lock, &irqL);
+
+	for (i = 0; i < NUM_STA; i++) {
+		phead = &(pstapriv->sta_hash[i]);
+		plist = get_next(phead);
+
+		while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) {
+			psta = LIST_CONTAINOR(plist,
+				struct sta_info, hash_list);
+
+			plist = get_next(plist);
+
+			if (psta->cmn.aid == aid)
+				goto done;
+
+			if (pbssid && _rtw_memcmp(psta->cmn.mac_addr,
+				pbssid, 6))
+				goto done;
+		}
+
+	}
+	psta = NULL;
+done:
+	_exit_critical_bh(&pstapriv->sta_hash_lock, &irqL);
+	return psta;
+}
+
+static int rm_dbg_modify_meas(_adapter *padapter, char *s)
+{
+	struct rm_priv *prmpriv = &padapter->rmpriv;
+	struct mlme_ext_info *pmlmeinfo = &padapter->mlmeextpriv.mlmext_info;
+	struct rm_obj *prm;
+	struct sta_info *psta;
+	char *pmac, *ptr, *paid, *prpt, *pnbp, *pclm, *pnhm, *pbcn;
+	unsigned val;
+	u8 bssid[ETH_ALEN];
+
+
+	/* example :
+	* rrm add_meas <aid=1|mac=>,m=<nb|clm|nhm|bcn>,<rept=>
+	* rrm run_meas <aid=1|evid=>
+	*/
+	paid = strstr(s, "aid=");
+	pmac = strstr(s, "mac=");
+	pbcn = strstr(s, "m=bcn");
+	pclm = strstr(s, "m=clm");
+	pnhm = strstr(s, "m=nhm");
+	pnbp = strstr(s, "m=nb");
+	prpt = strstr(s, "rpt=");
+
+	/* set all ',' to NULL (end of line) */
+	ptr = s;
+	while (ptr) {
+		ptr = strchr(ptr, ',');
+		if (ptr) {
+			*(ptr) = 0x0;
+			ptr++;
+		}
+	}
+	prm = (struct rm_obj *)prmpriv->prm_sel;
+	prm->q.m_token = 1;
+	psta = prm->psta;
+
+	if (paid) { /* find sta_info according to aid */
+		paid += 4; /* skip aid= */
+		sscanf(paid, "%u", &val); /* aid=x */
+		psta = rm_get_sta(padapter, val, NULL);
+
+	} else if (pmac) { /* find sta_info according to bssid */
+		pmac += 4; /* skip mac= */
+		if (hwaddr_parse(pmac, bssid) == NULL) {
+			sprintf(pstr(s), "Err: \nincorrect mac format\n");
+			return _FAIL;
+		}
+		psta = rm_get_sta(padapter, 0xff, bssid);
+	}
+
+	if (psta) {
+		prm->psta = psta;
+
+#if 0
+		prm->q.diag_token = psta->rm_diag_token++;
+#else
+		/* TODO dialog should base on sta_info */
+		prm->q.diag_token = pmlmeinfo->dialogToken++;
+#endif
+		prm->rmid = psta->cmn.aid << 16
+			| prm->q.diag_token << 8
+			| RM_MASTER;
+	} else
+		return _FAIL;
+
+	prm->q.action_code = RM_ACT_RADIO_MEAS_REQ;
+	if (pbcn) {
+		prm->q.m_type = bcn_req;
+	} else if (pnhm) {
+		prm->q.m_type = noise_histo_req;
+	} else if (pclm) {
+		prm->q.m_type = ch_load_req;
+	} else if (pnbp) {
+		prm->q.action_code = RM_ACT_NB_REP_REQ;
+	} else
+		return _FAIL;
+
+	if (prpt) {
+		prpt += 4; /* skip rpt= */
+		sscanf(prpt, "%u", &val);
+		prm->q.rpt = (u8)val;
+	}
+
+	return _SUCCESS;
+}
+
+static void rm_dbg_activate_meas(_adapter *padapter, char *s)
+{
+	struct rm_priv *prmpriv = &(padapter->rmpriv);
+	struct rm_obj *prm;
+
+
+	if (prmpriv->prm_sel == NULL) {
+		sprintf(pstr(s), "\nErr: No inActivate measurement\n");
+		return;
+	}
+	prm = (struct rm_obj *)prmpriv->prm_sel;
+
+	/* verify attributes */
+	if (prm->psta == NULL) {
+		sprintf(pstr(s), "\nErr: inActivate meas has no psta\n");
+		return;
+	}
+
+	/* measure current channel */
+	prm->q.ch_num = padapter->mlmeextpriv.cur_channel;
+	prm->q.op_class = rm_get_oper_class_via_ch(prm->q.ch_num);
+
+	/* enquee rmobj */
+	rm_enqueue_rmobj(padapter, prm, _FALSE);
+
+	sprintf(pstr(s), "\nActivate rmid=%x, state=%s, meas_type=%s\n",
+		prm->rmid, rm_state_name(prm->state),
+		rm_type_req_name(prm->q.m_type));
+
+	sprintf(pstr(s), "aid=%d, mac=" MAC_FMT "\n",
+		prm->psta->cmn.aid, MAC_ARG(prm->psta->cmn.mac_addr));
+
+	/* clearn inActivate prm info */
+	prmpriv->prm_sel = NULL;
+}
+
+static void rm_dbg_add_meas(_adapter *padapter, char *s)
+{
+	struct rm_priv *prmpriv = &(padapter->rmpriv);
+	struct rm_obj *prm;
+	char *pact;
+
+
+	/* example :
+	* rrm add_meas <aid=1|mac=>,m=<nb_req|clm_req|nhm_req>
+	* rrm run_meas <aid=1|evid=>
+	*/
+	prm = (struct rm_obj *)prmpriv->prm_sel;
+	if (prm == NULL)
+		prm = rm_alloc_rmobj(padapter);
+
+	if (prm == NULL) {
+		sprintf(pstr(s), "\nErr: alloc meas fail\n");
+		return;
+	}
+
+        prmpriv->prm_sel = prm;
+
+	pact = strstr(s, "act");
+	if (rm_dbg_modify_meas(padapter, s) == _FAIL) {
+
+		sprintf(pstr(s), "\nErr: add meas fail\n");
+		rm_free_rmobj(prm);
+		prmpriv->prm_sel = NULL;
+		return;
+	}
+	prm->q.category = RTW_WLAN_CATEGORY_RADIO_MEAS;
+	prm->q.e_id = _MEAS_REQ_IE_; /* 38 */
+
+	if (prm->q.action_code == RM_ACT_RADIO_MEAS_REQ)
+		sprintf(pstr(s), "\nAdd rmid=%x, meas_type=%s ok\n",
+			prm->rmid, rm_type_req_name(prm->q.m_type));
+	else  if (prm->q.action_code == RM_ACT_NB_REP_REQ) 
+		sprintf(pstr(s), "\nAdd rmid=%x, meas_type=bcn_req ok\n",
+			prm->rmid);
+
+	if (prm->psta)
+		sprintf(pstr(s), "mac="MAC_FMT"\n",
+			MAC_ARG(prm->psta->cmn.mac_addr));
+
+	if (pact)
+		rm_dbg_activate_meas(padapter, pstr(s));
+}
+
+static void rm_dbg_del_meas(_adapter *padapter, char *s)
+{
+	struct rm_priv *prmpriv = &padapter->rmpriv;
+	struct rm_obj *prm = (struct rm_obj *)prmpriv->prm_sel;
+
+
+	if (prm) {
+		sprintf(pstr(s), "\ndelete rmid=%x\n",prm->rmid);
+
+		/* free inActivate meas - enqueue yet  */
+		prmpriv->prm_sel = NULL;
+		rtw_mfree(prmpriv->prm_sel, sizeof(struct rm_obj));
+	} else
+		sprintf(pstr(s), "Err: no inActivate measurement\n");
+}
+
+static void rm_dbg_run_meas(_adapter *padapter, char *s)
+{
+	struct rm_obj *prm;
+	char *pevid, *prmid;
+	u32 rmid, evid;
+
+
+	prmid = strstr(s, "rmid="); /* hex */
+	pevid = strstr(s, "evid="); /* dec */
+
+	if (prmid && pevid) {
+		prmid += 5; /* rmid= */
+		sscanf(prmid, "%x", &rmid);
+
+		pevid += 5; /* evid= */
+		sscanf(pevid, "%u", &evid);
+	} else {
+		sprintf(pstr(s), "\nErr: incorrect attribute\n");
+		return;
+	}
+
+	prm = rm_get_rmobj(padapter, rmid);
+
+	if (!prm) {
+		sprintf(pstr(s), "\nErr: measurement not found\n");
+		return;
+	}
+
+	if (evid >= RM_EV_max) {
+		sprintf(pstr(s), "\nErr: wrong event id\n");
+		return;
+	}
+
+	rm_post_event(padapter, prm->rmid, evid);
+	sprintf(pstr(s), "\npost %s to rmid=%x\n",rm_event_name(evid), rmid);
+}
+
+static void rm_dbg_show_meas(struct rm_obj *prm, char *s)
+{
+	struct sta_info *psta;
+
+	psta = prm->psta;
+
+	if (prm->q.action_code == RM_ACT_RADIO_MEAS_REQ) {
+
+		sprintf(pstr(s), "\nrmid=%x, meas_type=%s\n",
+			prm->rmid, rm_type_req_name(prm->q.m_type));
+
+	} else  if (prm->q.action_code == RM_ACT_NB_REP_REQ) {
+
+		sprintf(pstr(s), "\nrmid=%x, action=neighbor_req\n",
+			prm->rmid);
+	} else
+		sprintf(pstr(s), "\nrmid=%x, action=unknown\n",
+			prm->rmid);
+
+	if (psta)
+		sprintf(pstr(s), "aid=%d, mac="MAC_FMT"\n",
+			psta->cmn.aid, MAC_ARG(psta->cmn.mac_addr));
+
+	sprintf(pstr(s), "clock=%d, state=%s, rpt=%u/%u\n",
+		(int)ATOMIC_READ(&prm->pclock->counter),
+		rm_state_name(prm->state), prm->p.rpt, prm->q.rpt);
+}
+
+static void rm_dbg_list_meas(_adapter *padapter, char *s)
+{
+	int meas_amount;
+	_irqL irqL;
+	struct rm_obj *prm;
+	struct sta_info *psta;
+	struct rm_priv *prmpriv = &padapter->rmpriv;
+	_queue *queue = &prmpriv->rm_queue;
+	_list *plist, *phead;
+
+
+	sprintf(pstr(s), "\n");
+	_enter_critical(&queue->lock, &irqL);
+	phead = get_list_head(queue);
+	plist = get_next(phead);
+	meas_amount = 0;
+
+	while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) {
+		prm = LIST_CONTAINOR(plist, struct rm_obj, list);
+		meas_amount++;
+		plist = get_next(plist);
+		psta = prm->psta;
+		sprintf(pstr(s), "=========================================\n");
+
+		rm_dbg_show_meas(prm, s);
+	}
+	_exit_critical(&queue->lock, &irqL);
+
+	sprintf(pstr(s), "=========================================\n");
+
+	if (meas_amount==0) {
+		sprintf(pstr(s), "No Activate measurement\n");
+		sprintf(pstr(s), "=========================================\n");
+	}
+
+	if (prmpriv->prm_sel == NULL)
+		sprintf(pstr(s), "\nNo inActivate measurement\n");
+	else {
+		sprintf(pstr(s), "\ninActivate measurement\n");
+		rm_dbg_show_meas((struct rm_obj *)prmpriv->prm_sel, s);
+	}
+}
+#endif /* RM_SUPPORT_IWPRIV_DBG */
+
+void rm_dbg_cmd(_adapter *padapter, char *s)
+{
+	unsigned val;
+	char *paid;
+	struct sta_info *psta=NULL;
+
+#if (RM_SUPPORT_IWPRIV_DBG)
+	if (_rtw_memcmp(s, "help", 4)) {
+		rm_dbg_help(padapter, s);
+
+	} else if (_rtw_memcmp(s, "list_sta", 8)) {
+		rm_dbg_list_sta(padapter, s);
+
+	} else if (_rtw_memcmp(s, "list_meas", 9)) {
+		rm_dbg_list_meas(padapter, s);
+
+	} else if (_rtw_memcmp(s, "add_meas", 8)) {
+		rm_dbg_add_meas(padapter, s);
+
+	} else if (_rtw_memcmp(s, "del_meas", 8)) {
+		rm_dbg_del_meas(padapter, s);
+
+	} else if (_rtw_memcmp(s, "activate", 8)) {
+		rm_dbg_activate_meas(padapter, s);
+
+	} else if (_rtw_memcmp(s, "run_meas", 8)) {
+		rm_dbg_run_meas(padapter, s);
+	} else if (_rtw_memcmp(s, "nb", 2)) {
+
+		paid = strstr(s, "aid=");
+
+		if (paid) { /* find sta_info according to aid */
+			paid += 4; /* skip aid= */
+			sscanf(paid, "%u", &val); /* aid=x */
+			psta = rm_get_sta(padapter, val, NULL);
+
+			if (psta)
+				rm_add_nb_req(padapter, psta);
+		}
+	}
+#else
+	sprintf(pstr(s), "\n");
+	sprintf(pstr(s), "rrm debug command was disabled\n");
+#endif
+}
+#endif /* CONFIG_RTW_80211K */
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/core/rtw_rm_fsm.c linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/core/rtw_rm_fsm.c
--- linux-5.6.3/3rdparty/rtl8821ce/core/rtw_rm_fsm.c	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/core/rtw_rm_fsm.c	2020-04-10 16:35:06.778658294 +0300
@@ -0,0 +1,998 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+
+#include <drv_types.h>
+#include <hal_data.h>
+#include "rtw_rm_fsm.h"
+
+#ifdef CONFIG_RTW_80211K
+
+struct fsm_state {
+	u8 *name;
+	int(*fsm_func)(struct rm_obj *prm, enum RM_EV_ID evid);
+};
+
+static void rm_state_initial(struct rm_obj *prm);
+static void rm_state_goto(struct rm_obj *prm, enum RM_STATE rm_state);
+static void rm_state_run(struct rm_obj *prm, enum RM_EV_ID evid);
+static struct rm_event *rm_dequeue_ev(_queue *queue);
+static struct rm_obj *rm_dequeue_rm(_queue *queue);
+
+void rm_timer_callback(void *data)
+{
+	int i;
+	_adapter *padapter = (_adapter *)data;
+	struct rm_priv *prmpriv = &padapter->rmpriv;
+	struct rm_clock *pclock;
+
+
+	/* deal with clock */
+	for (i=0;i<RM_TIMER_NUM;i++) {
+		pclock = &prmpriv->clock[i];
+		if (pclock->prm == NULL
+			||(ATOMIC_READ(&(pclock->counter)) == 0))
+			continue;
+
+		ATOMIC_DEC(&(pclock->counter));
+
+		if (ATOMIC_READ(&(pclock->counter)) == 0)
+			rm_post_event(pclock->prm->psta->padapter,
+				pclock->prm->rmid, prmpriv->clock[i].evid);
+	}
+	_set_timer(&prmpriv->rm_timer, CLOCK_UNIT);
+}
+
+int rtw_init_rm(_adapter *padapter)
+{
+	struct rm_priv *prmpriv = &padapter->rmpriv;
+
+
+	RTW_INFO("RM: %s\n",__func__);
+	_rtw_init_queue(&(prmpriv->rm_queue));
+	_rtw_init_queue(&(prmpriv->ev_queue));
+
+	/* bit 0-7 */
+	prmpriv->rm_en_cap_def[0] = 0
+		/*| BIT(RM_LINK_MEAS_CAP_EN)*/
+		| BIT(RM_NB_REP_CAP_EN)
+		/*| BIT(RM_PARAL_MEAS_CAP_EN)*/
+		| BIT(RM_REPEAT_MEAS_CAP_EN)
+		| BIT(RM_BCN_PASSIVE_MEAS_CAP_EN)
+		| BIT(RM_BCN_ACTIVE_MEAS_CAP_EN)
+		| BIT(RM_BCN_TABLE_MEAS_CAP_EN)
+		/*| BIT(RM_BCN_MEAS_REP_COND_CAP_EN)*/;
+
+	/* bit  8-15 */
+	prmpriv->rm_en_cap_def[1] = 0
+		/*| BIT(RM_FRAME_MEAS_CAP_EN - 8)*/
+#ifdef CONFIG_RTW_ACS
+		| BIT(RM_CH_LOAD_CAP_EN - 8)
+		| BIT(RM_NOISE_HISTO_CAP_EN - 8)
+#endif
+		/*| BIT(RM_STATIS_MEAS_CAP_EN - 8)*/
+		/*| BIT(RM_LCI_MEAS_CAP_EN - 8)*/
+		/*| BIT(RM_LCI_AMIMUTH_CAP_EN - 8)*/
+		/*| BIT(RM_TRANS_STREAM_CAT_MEAS_CAP_EN - 8)*/
+		/*| BIT(RM_TRIG_TRANS_STREAM_CAT_MEAS_CAP_EN - 8)*/;
+
+	/* bit 16-23 */
+	prmpriv->rm_en_cap_def[2] = 0
+		/*| BIT(RM_AP_CH_REP_CAP_EN - 16)*/
+		/*| BIT(RM_RM_MIB_CAP_EN - 16)*/
+		/*| BIT(RM_OP_CH_MAX_MEAS_DUR0 - 16)*/
+		/*| BIT(RM_OP_CH_MAX_MEAS_DUR1 - 16)*/
+		/*| BIT(RM_OP_CH_MAX_MEAS_DUR2 - 16)*/
+		/*| BIT(RM_NONOP_CH_MAX_MEAS_DUR0 - 16)*/
+		/*| BIT(RM_NONOP_CH_MAX_MEAS_DUR1 - 16)*/
+		/*| BIT(RM_NONOP_CH_MAX_MEAS_DUR2 - 16)*/;
+
+	/* bit 24-31 */
+	prmpriv->rm_en_cap_def[3] = 0
+		/*| BIT(RM_MEAS_PILOT_CAP0 - 24)*/
+		/*| BIT(RM_MEAS_PILOT_CAP1 - 24)*/
+		/*| BIT(RM_MEAS_PILOT_CAP2 - 24)*/
+		/*| BIT(RM_MEAS_PILOT_TRANS_INFO_CAP_EN - 24)*/
+		/*| BIT(RM_NB_REP_TSF_OFFSET_CAP_EN - 24)*/
+		| BIT(RM_RCPI_MEAS_CAP_EN - 24)
+		| BIT(RM_RSNI_MEAS_CAP_EN - 24)
+		/*| BIT(RM_BSS_AVG_ACCESS_DELAY_CAP_EN - 24)*/;
+
+	/* bit 32-39 */
+	prmpriv->rm_en_cap_def[4] = 0
+		/*| BIT(RM_BSS_AVG_ACCESS_DELAY_CAP_EN - 32)*/
+		/*| BIT(RM_AVALB_ADMIS_CAPACITY_CAP_EN - 32)*/
+		/*| BIT(RM_ANT_CAP_EN - 32)*/;
+
+	prmpriv->enable = _TRUE;
+
+	/* clock timer */
+	rtw_init_timer(&prmpriv->rm_timer,
+		padapter, rm_timer_callback, padapter);
+	_set_timer(&prmpriv->rm_timer, CLOCK_UNIT);
+
+	return _SUCCESS;
+}
+
+int rtw_deinit_rm(_adapter *padapter)
+{
+	struct rm_priv *prmpriv = &padapter->rmpriv;
+	struct rm_obj *prm;
+	struct rm_event *pev;
+
+
+	RTW_INFO("RM: %s\n",__func__);
+	prmpriv->enable = _FALSE;
+	_cancel_timer_ex(&prmpriv->rm_timer);
+
+	/* free all events and measurements */
+	while((pev = rm_dequeue_ev(&prmpriv->ev_queue)) != NULL)
+		rtw_mfree((void *)pev, sizeof(struct rm_event));
+
+	while((prm = rm_dequeue_rm(&prmpriv->rm_queue)) != NULL)
+		rm_state_run(prm, RM_EV_cancel);
+
+	_rtw_deinit_queue(&(prmpriv->rm_queue));
+	_rtw_deinit_queue(&(prmpriv->ev_queue));
+
+	return _SUCCESS;
+}
+
+int rtw_free_rm_priv(_adapter *padapter)
+{
+	return rtw_deinit_rm(padapter);
+}
+
+static int rm_enqueue_ev(_queue *queue, struct rm_event *obj, bool to_head)
+{
+	_irqL irqL;
+
+
+	if (obj == NULL)
+		return _FAIL;
+
+	_enter_critical(&queue->lock, &irqL);
+
+	if (to_head)
+		rtw_list_insert_head(&obj->list, &queue->queue);
+	else
+		rtw_list_insert_tail(&obj->list, &queue->queue);
+
+	_exit_critical(&queue->lock, &irqL);
+
+	return _SUCCESS;
+}
+
+static void rm_set_clock(struct rm_obj *prm, u32 ms, enum RM_EV_ID evid)
+{
+	ATOMIC_SET(&(prm->pclock->counter), (ms/CLOCK_UNIT));
+	prm->pclock->evid = evid;
+}
+
+static struct rm_clock *rm_alloc_clock(_adapter *padapter, struct rm_obj *prm)
+{
+	int i;
+	struct rm_priv *prmpriv = &padapter->rmpriv;
+	struct rm_clock *pclock = NULL;
+
+
+	for (i=0;i<RM_TIMER_NUM;i++) {
+		pclock = &prmpriv->clock[i];
+
+		if (pclock->prm == NULL) {
+			pclock->prm = prm;
+			ATOMIC_SET(&(pclock->counter), 0);
+			pclock->evid = RM_EV_max;
+			break;
+		}
+	}
+	return pclock;
+}
+
+static void rm_cancel_clock(struct rm_obj *prm)
+{
+	ATOMIC_SET(&(prm->pclock->counter), 0);
+	prm->pclock->evid = RM_EV_max;
+}
+
+static void rm_free_clock(struct rm_clock *pclock)
+{
+	pclock->prm = NULL;
+	ATOMIC_SET(&(pclock->counter), 0);
+	pclock->evid = RM_EV_max;
+}
+
+static int is_list_linked(const struct list_head *head)
+{
+	return head->prev != NULL;
+}
+
+void rm_free_rmobj(struct rm_obj *prm)
+{
+	if (is_list_linked(&prm->list))
+		rtw_list_delete(&prm->list);
+
+	if (prm->q.pssid)
+		rtw_mfree(prm->q.pssid, strlen(prm->q.pssid)+1);
+
+	if (prm->q.opt.bcn.req_start)
+		rtw_mfree(prm->q.opt.bcn.req_start,
+			prm->q.opt.bcn.req_len);
+
+	if (prm->pclock)
+		rm_free_clock(prm->pclock);
+
+	rtw_mfree((void *)prm, sizeof(struct rm_obj));
+}
+
+struct rm_obj *rm_alloc_rmobj(_adapter *padapter)
+{
+	struct rm_obj *prm;
+
+
+	prm = (struct rm_obj *)rtw_malloc(sizeof(struct rm_obj));
+	if (prm == NULL)
+		return NULL;
+
+	_rtw_memset(prm, 0, sizeof(struct rm_obj));
+
+	/* alloc timer */
+	if ((prm->pclock = rm_alloc_clock(padapter, prm)) == NULL) {
+		rm_free_rmobj(prm);
+		return NULL;
+	}
+	return prm;
+}
+
+int rm_enqueue_rmobj(_adapter *padapter, struct rm_obj *prm, bool to_head)
+{
+	_irqL irqL;
+	struct rm_priv *prmpriv = &padapter->rmpriv;
+	_queue *queue = &prmpriv->rm_queue;
+
+
+	if (prm == NULL)
+		return _FAIL;
+
+	_enter_critical(&queue->lock, &irqL);
+	if (to_head)
+		rtw_list_insert_head(&prm->list, &queue->queue);
+	else
+		rtw_list_insert_tail(&prm->list, &queue->queue);
+	_exit_critical(&queue->lock, &irqL);
+
+	rm_state_initial(prm);
+
+	return _SUCCESS;
+}
+
+static struct rm_obj *rm_dequeue_rm(_queue *queue)
+{
+	_irqL irqL;
+	struct rm_obj *prm;
+
+
+	_enter_critical(&queue->lock, &irqL);
+	if (rtw_is_list_empty(&(queue->queue)))
+		prm = NULL;
+	else {
+		prm = LIST_CONTAINOR(get_next(&(queue->queue)),
+			struct rm_obj, list);
+		/* rtw_list_delete(&prm->list); */
+	}
+	_exit_critical(&queue->lock, &irqL);
+
+	return prm;
+}
+
+static struct rm_event *rm_dequeue_ev(_queue *queue)
+{
+	_irqL irqL;
+	struct rm_event *ev;
+
+
+	_enter_critical(&queue->lock, &irqL);
+	if (rtw_is_list_empty(&(queue->queue)))
+		ev = NULL;
+	else {
+		ev = LIST_CONTAINOR(get_next(&(queue->queue)),
+			struct rm_event, list);
+		rtw_list_delete(&ev->list);
+	}
+	_exit_critical(&queue->lock, &irqL);
+
+	return ev;
+}
+
+static struct rm_obj *_rm_get_rmobj(_queue *queue, u32 rmid)
+{
+	_irqL irqL;
+	_list *phead, *plist;
+	struct rm_obj *prm = NULL;
+
+
+	if (rmid == 0)
+		return NULL;
+
+	_enter_critical(&queue->lock, &irqL);
+
+	phead = get_list_head(queue);
+	plist = get_next(phead);
+	while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) {
+
+		prm = LIST_CONTAINOR(plist, struct rm_obj, list);
+		if (rmid == (prm->rmid)) {
+			_exit_critical(&queue->lock, &irqL);
+			return prm;
+		}
+		plist = get_next(plist);
+	}
+	_exit_critical(&queue->lock, &irqL);
+
+	return NULL;
+}
+
+struct sta_info *rm_get_psta(_adapter *padapter, u32 rmid)
+{
+	struct rm_priv *prmpriv = &padapter->rmpriv;
+	struct rm_obj *prm;
+
+
+	prm = _rm_get_rmobj(&prmpriv->rm_queue, rmid);
+
+	if (prm)
+		return prm->psta;
+
+	return NULL;
+}
+
+struct rm_obj *rm_get_rmobj(_adapter *padapter, u32 rmid)
+{
+	struct rm_priv *prmpriv = &padapter->rmpriv;
+
+	return _rm_get_rmobj(&prmpriv->rm_queue, rmid);
+}
+
+u8 rtw_rm_post_envent_cmd(_adapter *padapter, u32 rmid, u8 evid)
+{
+	struct cmd_obj *pcmd;
+	struct rm_event *pev;
+	struct cmd_priv *pcmdpriv = &padapter->cmdpriv;
+	u8 res = _SUCCESS;
+
+
+	pcmd = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj));
+	if (pcmd == NULL) {
+		res = _FAIL;
+		goto exit;
+	}
+	pev = (struct rm_event*)rtw_zmalloc(sizeof(struct rm_event));
+
+	if (pev == NULL) {
+		rtw_mfree((u8 *) pcmd, sizeof(struct cmd_obj));
+		res = _FAIL;
+		goto exit;
+	}
+	pev->rmid = rmid;
+	pev->evid = evid;
+
+	init_h2fwcmd_w_parm_no_rsp(pcmd, pev, GEN_CMD_CODE(_RM_POST_EVENT));
+	res = rtw_enqueue_cmd(pcmdpriv, pcmd);
+exit:
+	return res;
+}
+
+int rm_post_event(_adapter *padapter, u32 rmid, enum RM_EV_ID evid)
+{
+	if (padapter->rmpriv.enable == _FALSE)
+		return _FALSE;
+
+	RTW_INFO("RM: post asyn %s to rmid=%x\n", rm_event_name(evid), rmid);
+	rtw_rm_post_envent_cmd(padapter, rmid, evid);
+	return _SUCCESS;
+}
+
+int _rm_post_event(_adapter *padapter, u32 rmid, enum RM_EV_ID evid)
+{
+	struct rm_priv *prmpriv = &padapter->rmpriv;
+	struct rm_event *pev;
+
+	if (evid >= RM_EV_max || rmid == 0)
+		return _FALSE;
+
+	pev = (struct rm_event *)rtw_malloc(sizeof(struct rm_event));
+	if (pev == NULL)
+		return _FALSE;
+
+	pev->rmid = rmid;
+	pev->evid = evid;
+
+	RTW_INFO("RM: post sync %s to rmid=%x\n", rm_event_name(evid), rmid);
+	rm_enqueue_ev(&prmpriv->ev_queue, pev, FALSE);
+
+	return _SUCCESS;
+}
+
+static void rm_bcast_aid_handler(_adapter *padapter, struct rm_event *pev)
+{
+	_irqL irqL;
+	_list *phead, *plist;
+	_queue *queue = &padapter->rmpriv.rm_queue;
+	struct rm_obj *prm;
+
+
+	_enter_critical(&queue->lock, &irqL);
+	phead = get_list_head(queue);
+	plist = get_next(phead);
+	while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) {
+
+		prm = LIST_CONTAINOR(plist, struct rm_obj, list);
+		plist = get_next(plist);
+		if (RM_GET_AID(pev->rmid) == RM_GET_AID(prm->rmid)) {
+			_exit_critical(&queue->lock, &irqL);
+			rm_state_run(prm, pev->evid);
+			_enter_critical(&queue->lock, &irqL);
+		}
+	}
+	_exit_critical(&queue->lock, &irqL);
+	return;
+}
+
+/* main handler of RM (Resource Management) */
+void rm_handler(_adapter *padapter, struct rm_event *pe)
+{
+	int i;
+	struct rm_priv *prmpriv = &padapter->rmpriv;
+	struct rm_obj *prm;
+	struct rm_event *pev;
+
+
+	/* dequeue event */
+	while((pev = rm_dequeue_ev(&prmpriv->ev_queue)) != NULL)
+	{
+		if (RM_IS_ID_FOR_ALL(pev->rmid)) {
+			/* apply to all aid mateched measurement */
+			rm_bcast_aid_handler(padapter, pev);
+			rtw_mfree((void *)pev, sizeof(struct rm_event));
+			continue;
+		}
+
+		/* retrieve rmobj */
+		prm = _rm_get_rmobj(&prmpriv->rm_queue, pev->rmid);
+		if (prm == NULL) {
+			RTW_ERR("RM: rmid=%x event=%s doesn't find rm obj\n",
+				pev->rmid, rm_event_name(pev->evid));
+			rtw_mfree((void *)pev, sizeof(struct rm_event));
+			return;
+		}
+		/* run state machine */
+		rm_state_run(prm, pev->evid);
+		rtw_mfree((void *)pev, sizeof(struct rm_event));
+	}
+}
+
+static int rm_issue_meas_req(struct rm_obj *prm)
+{
+	switch (prm->q.action_code) {
+	case RM_ACT_RADIO_MEAS_REQ:
+		switch (prm->q.m_type) {
+		case bcn_req:
+		case ch_load_req:
+		case noise_histo_req:
+			issue_radio_meas_req(prm);
+			break;
+		default:
+			break;
+		} /* meas_type */
+		break;
+	case RM_ACT_NB_REP_REQ:
+		/* issue neighbor request */
+		issue_nb_req(prm);
+		break;
+	case RM_ACT_LINK_MEAS_REQ:
+	default:
+		return _FALSE;
+	} /* action_code */
+
+	return _SUCCESS;
+}
+
+/*
+* RM state machine
+*/
+
+static int rm_state_idle(struct rm_obj *prm, enum RM_EV_ID evid)
+{
+	_adapter *padapter = prm->psta->padapter;
+	u8 val8;
+	u32 val32;
+
+
+	prm->p.category = RTW_WLAN_CATEGORY_RADIO_MEAS;
+
+	switch (evid) {
+	case RM_EV_state_in:
+		switch (prm->q.action_code) {
+		case RM_ACT_RADIO_MEAS_REQ:
+			/* copy attrib from meas_req to meas_rep */
+			prm->p.action_code = RM_ACT_RADIO_MEAS_REP;
+			prm->p.diag_token = prm->q.diag_token;
+			prm->p.e_id = _MEAS_RSP_IE_;
+			prm->p.m_token = prm->q.m_token;
+			prm->p.m_type = prm->q.m_type;
+			prm->p.rpt = prm->q.rpt;
+			prm->p.ch_num = prm->q.ch_num;
+			prm->p.op_class = prm->q.op_class;
+
+			if (prm->q.m_type == ch_load_req
+				|| prm->q.m_type == noise_histo_req) {
+				/*
+				 * phydm measure current ch periodically
+				 * scan current ch is not necessary
+				 */
+				val8 = padapter->mlmeextpriv.cur_channel;
+				if (prm->q.ch_num == val8)
+					prm->poll_mode = 1;
+			}
+			RTW_INFO("RM: rmid=%x %s switch in repeat=%u\n",
+				prm->rmid, rm_type_req_name(prm->q.m_type),
+				prm->q.rpt);
+			break;
+		case RM_ACT_NB_REP_REQ:
+			prm->p.action_code = RM_ACT_NB_REP_RESP;
+			RTW_INFO("RM: rmid=%x Neighbor request switch in\n",
+				prm->rmid);
+			break;
+		case RM_ACT_LINK_MEAS_REQ:
+			prm->p.action_code = RM_ACT_LINK_MEAS_REP;
+			rm_set_rep_mode(prm, MEAS_REP_MOD_INCAP);
+			RTW_INFO("RM: rmid=%x Link meas switch in\n",
+				prm->rmid);
+			break;
+		default:
+			prm->p.action_code = prm->q.action_code;
+			rm_set_rep_mode(prm, MEAS_REP_MOD_INCAP);
+			RTW_INFO("RM: rmid=%x recv unknown action %d\n",
+				prm->rmid,prm->p.action_code);
+			break;
+		} /* switch() */
+
+		if (prm->rmid & RM_MASTER) {
+			if (rm_issue_meas_req(prm) == _SUCCESS)
+				rm_state_goto(prm, RM_ST_WAIT_MEAS);
+			else
+				rm_state_goto(prm, RM_ST_END);
+			return _SUCCESS;
+		} else {
+			rm_state_goto(prm, RM_ST_DO_MEAS);
+			return _SUCCESS;
+		}
+
+		if (prm->p.m_mode) {
+			issue_null_reply(prm);
+			rm_state_goto(prm, RM_ST_END);
+			return _SUCCESS;
+		}
+		if (prm->q.rand_intvl) {
+			/* get low tsf to generate random interval */
+			val32 = rtw_read32(padapter, REG_TSFTR);
+			val32 = val32 % prm->q.rand_intvl;
+			RTW_INFO("RM: rmid=%x rand_intval=%d, rand=%d\n",
+				prm->rmid, (int)prm->q.rand_intvl,val32);
+			rm_set_clock(prm, prm->q.rand_intvl,
+				RM_EV_delay_timer_expire);
+			return _SUCCESS;
+		}
+		break;
+	case RM_EV_delay_timer_expire:
+		rm_state_goto(prm, RM_ST_DO_MEAS);
+		break;
+	case RM_EV_cancel:
+		rm_state_goto(prm, RM_ST_END);
+		break;
+	case RM_EV_state_out:
+		rm_cancel_clock(prm);
+		break;
+	default:
+		break;
+	}
+	return _SUCCESS;
+}
+
+/* we do the measuring */
+static int rm_state_do_meas(struct rm_obj *prm, enum RM_EV_ID evid)
+{
+	_adapter *padapter = prm->psta->padapter;
+	u8 val8;
+	u64 val64;
+
+
+	switch (evid) {
+	case RM_EV_state_in:
+		if (prm->q.action_code == RM_ACT_RADIO_MEAS_REQ) {
+			switch (prm->q.m_type) {
+			case bcn_req:
+				if (prm->q.m_mode == bcn_req_bcn_table) {
+					RTW_INFO("RM: rmid=%x Beacon table\n",
+						prm->rmid);
+					_rm_post_event(padapter, prm->rmid,
+						RM_EV_survey_done);
+					return _SUCCESS;
+				}
+				break;
+			case ch_load_req:
+			case noise_histo_req:
+				if (prm->poll_mode)
+					_rm_post_event(padapter, prm->rmid,
+						RM_EV_survey_done);
+				return _SUCCESS;
+			default:
+				rm_state_goto(prm, RM_ST_END);
+				return _SUCCESS;
+			}
+
+			if (!ready_for_scan(prm)) {
+				prm->wait_busy = RM_BUSY_TRAFFIC_TIMES;
+				RTW_INFO("RM: wait busy traffic - %d\n",
+					prm->wait_busy);
+				rm_set_clock(prm, RM_WAIT_BUSY_TIMEOUT,
+					RM_EV_busy_timer_expire);
+				return _SUCCESS;
+			}
+		}
+		_rm_post_event(padapter, prm->rmid, RM_EV_start_meas);
+		break;
+	case RM_EV_start_meas:
+		if (prm->q.action_code == RM_ACT_RADIO_MEAS_REQ) {
+			/* resotre measurement start time */
+			prm->meas_start_time = rtw_hal_get_tsftr_by_port(padapter
+									, rtw_hal_get_port(padapter));
+
+			switch (prm->q.m_type) {
+			case bcn_req:
+				val8 = 1; /* Enable free run counter */
+				rtw_hal_set_hwreg(padapter,
+					HW_VAR_FREECNT, &val8);
+				rm_sitesurvey(prm);
+				break;
+			case ch_load_req:
+			case noise_histo_req:
+				rm_sitesurvey(prm);
+				break;
+			default:
+				rm_state_goto(prm, RM_ST_END);
+				return _SUCCESS;
+				break;
+			}
+		}
+		/* handle measurement timeout */
+		rm_set_clock(prm, RM_MEAS_TIMEOUT, RM_EV_meas_timer_expire);
+		break;
+	case RM_EV_survey_done:
+		if (prm->q.action_code == RM_ACT_RADIO_MEAS_REQ) {
+			switch (prm->q.m_type) {
+			case bcn_req:
+				rm_cancel_clock(prm);
+				rm_state_goto(prm, RM_ST_SEND_REPORT);
+				return _SUCCESS;
+			case ch_load_req:
+			case noise_histo_req:
+				retrieve_radio_meas_result(prm);
+
+				if (rm_radio_meas_report_cond(prm) == _SUCCESS)
+					rm_state_goto(prm, RM_ST_SEND_REPORT);
+				else
+					rm_set_clock(prm, RM_COND_INTVL,
+						RM_EV_retry_timer_expire);
+				break;
+			default:
+				rm_state_goto(prm, RM_ST_END);
+				return _SUCCESS;
+			}
+		}
+		break;
+	case RM_EV_meas_timer_expire:
+		RTW_INFO("RM: rmid=%x measurement timeount\n",prm->rmid);
+		rm_set_rep_mode(prm, MEAS_REP_MOD_REFUSE);
+		issue_null_reply(prm);
+		rm_state_goto(prm, RM_ST_END);
+		break;
+	case RM_EV_busy_timer_expire:
+		if (!ready_for_scan(prm) && prm->wait_busy--) {
+			RTW_INFO("RM: wait busy - %d\n",prm->wait_busy);
+			rm_set_clock(prm, RM_WAIT_BUSY_TIMEOUT,
+				RM_EV_busy_timer_expire);
+			break;
+		}
+		else if (prm->wait_busy <= 0) {
+			RTW_INFO("RM: wait busy timeout\n");
+			rm_set_rep_mode(prm, MEAS_REP_MOD_REFUSE);
+			issue_null_reply(prm);
+			rm_state_goto(prm, RM_ST_END);
+			return _SUCCESS;
+		}
+		_rm_post_event(padapter, prm->rmid, RM_EV_start_meas);
+		break;
+	case RM_EV_request_timer_expire:
+		rm_set_rep_mode(prm, MEAS_REP_MOD_REFUSE);
+		issue_null_reply(prm);
+		rm_state_goto(prm, RM_ST_END);
+		break;
+	case RM_EV_retry_timer_expire:
+		/* expired due to meas condition mismatch, meas again */
+		_rm_post_event(padapter, prm->rmid, RM_EV_start_meas);
+		break;
+	case RM_EV_cancel:
+		rm_set_rep_mode(prm, MEAS_REP_MOD_REFUSE);
+		issue_null_reply(prm);
+		rm_state_goto(prm, RM_ST_END);
+		break;
+	case RM_EV_state_out:
+		rm_cancel_clock(prm);
+		/* resotre measurement end time */
+		prm->meas_end_time = rtw_hal_get_tsftr_by_port(padapter
+								, rtw_hal_get_port(padapter));
+
+		val8 = 0; /* Disable free run counter */
+		rtw_hal_set_hwreg(padapter, HW_VAR_FREECNT, &val8);
+		break;
+	default:
+		break;
+	}
+
+	return _SUCCESS;
+}
+
+static int rm_state_wait_meas(struct rm_obj *prm, enum RM_EV_ID evid)
+{
+	u8 val8;
+	u64 val64;
+
+
+	switch (evid) {
+	case RM_EV_state_in:
+		/* we create meas_req, waiting for peer report */
+		rm_set_clock(prm, RM_REQ_TIMEOUT,
+			RM_EV_request_timer_expire);
+		break;
+	case RM_EV_recv_rep:
+		rm_state_goto(prm, RM_ST_RECV_REPORT);
+		break;
+	case RM_EV_request_timer_expire:
+	case RM_EV_cancel:
+		rm_state_goto(prm, RM_ST_END);
+		break;
+	case RM_EV_state_out:
+		rm_cancel_clock(prm);
+		break;
+	default:
+		break;
+	}
+	return _SUCCESS;
+}
+
+static int rm_state_send_report(struct rm_obj *prm, enum RM_EV_ID evid)
+{
+	u8 val8;
+
+
+	switch (evid) {
+	case RM_EV_state_in:
+		/* we have to issue report */
+		switch (prm->q.m_type) {
+		case bcn_req:
+			issue_beacon_rep(prm);
+			break;
+		case ch_load_req:
+		case noise_histo_req:
+			issue_radio_meas_rep(prm);
+			break;
+		default:
+			rm_state_goto(prm, RM_ST_END);
+			return _SUCCESS;
+		}
+
+		/* check repeat */
+		if (prm->p.rpt) {
+			RTW_INFO("RM: rmid=%x repeat=%u/%u\n",
+				prm->rmid, prm->p.rpt,
+				prm->q.rpt);
+			prm->p.rpt--;
+			/*
+			* we recv meas_req,
+			* delay for a wihile and than meas again
+			*/
+			if (prm->poll_mode)
+				rm_set_clock(prm, RM_REPT_POLL_INTVL,
+					RM_EV_repeat_delay_expire);
+			else
+				rm_set_clock(prm, RM_REPT_SCAN_INTVL,
+					RM_EV_repeat_delay_expire);
+			return _SUCCESS;
+		}
+		/* we are done */
+		rm_state_goto(prm, RM_ST_END);
+		break;
+	case RM_EV_repeat_delay_expire:
+		rm_state_goto(prm, RM_ST_DO_MEAS);
+		break;
+	case RM_EV_cancel:
+		rm_state_goto(prm, RM_ST_END);
+		break;
+	case RM_EV_state_out:
+		rm_cancel_clock(prm);
+		break;
+	default:
+		break;
+	}
+	return _SUCCESS;
+}
+
+static int rm_state_recv_report(struct rm_obj *prm, enum RM_EV_ID evid)
+{
+	u8 val8;
+
+
+	switch (evid) {
+	case RM_EV_state_in:
+		/* we issue meas_req, got peer's meas report */
+		switch (prm->p.action_code) {
+		case RM_ACT_RADIO_MEAS_REP:
+			/* check refuse, incapable and repeat */
+			val8 = prm->p.m_mode;
+			if (val8) {
+				RTW_INFO("RM: rmid=%x peer reject (%s repeat=%d)\n",
+					prm->rmid,
+					val8|MEAS_REP_MOD_INCAP?"INCAP":
+					val8|MEAS_REP_MOD_REFUSE?"REFUSE":
+					val8|MEAS_REP_MOD_LATE?"LATE":"",
+					prm->p.rpt);
+				rm_state_goto(prm, RM_ST_END);
+				return _SUCCESS;
+			}
+			break;
+		case RM_ACT_NB_REP_RESP:
+			/* report to upper layer if needing */
+			rm_state_goto(prm, RM_ST_END);
+			return _SUCCESS;
+		default:
+			rm_state_goto(prm, RM_ST_END);
+			return _SUCCESS;
+		}
+		/* check repeat */
+		if (prm->p.rpt) {
+			RTW_INFO("RM: rmid=%x repeat=%u/%u\n",
+				prm->rmid, prm->p.rpt,
+				prm->q.rpt);
+			prm->p.rpt--;
+			/* waitting more report */
+			rm_state_goto(prm, RM_ST_WAIT_MEAS);
+			break;
+		}
+		/* we are done */
+		rm_state_goto(prm, RM_ST_END);
+		break;
+	case RM_EV_cancel:
+		rm_state_goto(prm, RM_ST_END);
+		break;
+	case RM_EV_state_out:
+		rm_cancel_clock(prm);
+		break;
+	default:
+		break;
+	}
+	return _SUCCESS;
+}
+
+static int rm_state_end(struct rm_obj *prm, enum RM_EV_ID evid)
+{
+	switch (evid) {
+	case RM_EV_state_in:
+		_rm_post_event(prm->psta->padapter, prm->rmid, RM_EV_state_out);
+		break;
+
+	case RM_EV_cancel:
+	case RM_EV_state_out:
+	default:
+		rm_free_rmobj(prm);
+		break;
+	}
+	return _SUCCESS;
+}
+
+struct fsm_state rm_fsm[] = {
+	{"RM_ST_IDLE",		rm_state_idle},
+	{"RM_ST_DO_MEAS",	rm_state_do_meas},
+	{"RM_ST_WAIT_MEAS", 	rm_state_wait_meas},
+	{"RM_ST_SEND_REPORT", 	rm_state_send_report},
+	{"RM_ST_RECV_REPORT", 	rm_state_recv_report},
+	{"RM_ST_END", 		rm_state_end}
+};
+
+char *rm_state_name(enum RM_STATE state)
+{
+	return rm_fsm[state].name;
+}
+
+char *rm_event_name(enum RM_EV_ID evid)
+{
+	switch(evid) {
+	case RM_EV_state_in:
+		return "RM_EV_state_in";
+	case RM_EV_busy_timer_expire:
+		return "RM_EV_busy_timer_expire";
+	case RM_EV_delay_timer_expire:
+		return "RM_EV_delay_timer_expire";
+	case RM_EV_meas_timer_expire:
+		return "RM_EV_meas_timer_expire";
+	case RM_EV_repeat_delay_expire:
+		return "RM_EV_repeat_delay_expire";
+	case RM_EV_retry_timer_expire:
+		return "RM_EV_retry_timer_expire";
+	case RM_EV_request_timer_expire:
+		return "RM_EV_request_timer_expire";
+	case RM_EV_wait_report:
+		return "RM_EV_wait_report";
+	case RM_EV_start_meas:
+		return "RM_EV_start_meas";
+	case RM_EV_survey_done:
+		return "RM_EV_survey_done";
+	case RM_EV_recv_rep:
+		return "RM_EV_recv_report";
+	case RM_EV_cancel:
+		return "RM_EV_cancel";
+	case RM_EV_state_out:
+		return "RM_EV_state_out";
+	case RM_EV_max:
+		return "RM_EV_max";
+	default:
+		return "RM_EV_unknown";
+	}
+	return "UNKNOWN";
+}
+
+static void rm_state_initial(struct rm_obj *prm)
+{
+	prm->state = RM_ST_IDLE;
+
+	RTW_INFO("\n");
+	RTW_INFO("RM: rmid=%x %-18s -> %s\n",prm->rmid,
+		"new measurement", rm_fsm[prm->state].name);
+
+	rm_post_event(prm->psta->padapter, prm->rmid, RM_EV_state_in);
+}
+
+static void rm_state_run(struct rm_obj *prm, enum RM_EV_ID evid)
+{
+	RTW_INFO("RM: rmid=%x %-18s    %s\n",prm->rmid,
+		rm_fsm[prm->state].name,rm_event_name(evid));
+
+	rm_fsm[prm->state].fsm_func(prm, evid);
+}
+
+static void rm_state_goto(struct rm_obj *prm, enum RM_STATE rm_state)
+{
+	if (prm->state == rm_state)
+		return;
+
+	rm_state_run(prm, RM_EV_state_out);
+
+	RTW_INFO("\n");
+	RTW_INFO("RM: rmid=%x %-18s -> %s\n",prm->rmid,
+		rm_fsm[prm->state].name, rm_fsm[rm_state].name);
+
+	prm->state = rm_state;
+	rm_state_run(prm, RM_EV_state_in);
+}
+#endif /* CONFIG_RTW_80211K */
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/core/rtw_rson.c linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/core/rtw_rson.c
--- linux-5.6.3/3rdparty/rtl8821ce/core/rtw_rson.c	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/core/rtw_rson.c	2020-04-10 16:35:06.778658294 +0300
@@ -0,0 +1,595 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
+ *
+ *
+ ******************************************************************************/
+#define _RTW_RSON_C_
+
+#include <drv_types.h>
+
+#ifdef CONFIG_RTW_REPEATER_SON
+
+/********	Custommize Part	***********************/
+
+unsigned char	RTW_RSON_OUI[] = {0xFA, 0xFA, 0xFA};
+#define RSON_SCORE_DIFF_TH				8
+
+/*
+	Calculate the corresponding score.
+*/
+inline u8 rtw_cal_rson_score(struct rtw_rson_struct *cand_rson_data, NDIS_802_11_RSSI  Rssi)
+{
+	if ((cand_rson_data->hopcnt == RTW_RSON_HC_NOTREADY)
+		|| (cand_rson_data->connectible == RTW_RSON_DENYCONNECT))
+		return RTW_RSON_SCORE_NOTCNNT;
+
+	return RTW_RSON_SCORE_MAX - (cand_rson_data->hopcnt * 10) + (Rssi/10);
+}
+
+/*************************************************/
+
+
+static u8 rtw_rson_block_bssid_idx = 0;
+u8 rtw_rson_block_bssid[10][6] = {
+			/*{0x02, 0xE0, 0x4C, 0x07, 0xC3, 0xF6}*/
+};
+
+/* fake root, regard a real AP as a SO root */
+static u8 rtw_rson_root_bssid_idx = 0;
+u8 rtw_rson_root_bssid[10][6] = {
+			/*{0x1c, 0x5f, 0x2b, 0x5a, 0x60, 0x24}*/
+};
+
+int is_match_bssid(u8 *mac, u8 bssid_array[][6], int num)
+{
+	int i;
+
+	for (i = 0; i < num; i++)
+		if (_rtw_memcmp(mac, bssid_array[i], 6) == _TRUE)
+			return _TRUE;
+	return _FALSE;
+}
+
+void init_rtw_rson_data(struct dvobj_priv *dvobj)
+{
+	/*Aries  todo.  if pdvobj->rson_data.ver == 1 */
+	dvobj->rson_data.ver = RTW_RSON_VER;
+	dvobj->rson_data.id = CONFIG_RTW_REPEATER_SON_ID;
+#ifdef CONFIG_RTW_REPEATER_SON_ROOT
+	dvobj->rson_data.hopcnt = RTW_RSON_HC_ROOT;
+	dvobj->rson_data.connectible = RTW_RSON_ALLOWCONNECT;
+#else
+	dvobj->rson_data.hopcnt = RTW_RSON_HC_NOTREADY;
+	dvobj->rson_data.connectible = RTW_RSON_DENYCONNECT;
+#endif
+	dvobj->rson_data.loading = 0;
+	_rtw_memset(dvobj->rson_data.res, 0xAA, sizeof(dvobj->rson_data.res));
+}
+
+void	rtw_rson_get_property_str(_adapter *padapter, char *rson_data_str)
+{
+	struct dvobj_priv *pdvobj = adapter_to_dvobj(padapter);
+
+	sprintf(rson_data_str, "version : \t%d\nid : \t\t%08x\nhop count : \t%d\nconnectible : \t%s\nloading : \t%d\nreserve : \t%16ph\n",
+		pdvobj->rson_data.ver,
+		pdvobj->rson_data.id,
+		pdvobj->rson_data.hopcnt,
+		pdvobj->rson_data.connectible ? "connectable":"unconnectable",
+		pdvobj->rson_data.loading,
+		pdvobj->rson_data.res);
+}
+
+int str2hexbuf(char *str, u8 *hexbuf, int len)
+{
+	u8 *p;
+	int i, slen, idx = 0;
+
+	p = (unsigned char *)str;
+	if ((*p != '0') || (*(p+1) != 'x'))
+		return _FALSE;
+	slen = strlen(str);
+	if (slen > (len*2) + 2)
+		return _FALSE;
+	p += 2;
+	for (i = 0 ; i < len; i++, idx = idx+2) {
+		hexbuf[i] = key_2char2num(p[idx], p[idx + 1]);
+		if (slen <= idx+2)
+			break;
+	}
+	return _TRUE;
+}
+
+int rtw_rson_set_property(_adapter *padapter, char *field, char *value)
+{
+	struct dvobj_priv *pdvobj = adapter_to_dvobj(padapter);
+	int num = 0;
+
+	if (_rtw_memcmp(field, (u8 *)"ver", 3) == _TRUE)
+		pdvobj->rson_data.ver = rtw_atoi(value);
+	else if (_rtw_memcmp(field, (u8 *)"id", 2) == _TRUE)
+		num = sscanf(value, "%08x",   &(pdvobj->rson_data.id));
+	else if (_rtw_memcmp(field, (u8 *)"hc", 2) == _TRUE)
+		num = sscanf(value, "%hhu", &(pdvobj->rson_data.hopcnt));
+	else if (_rtw_memcmp(field, (u8 *)"cnt", 3) == _TRUE)
+		num = sscanf(value, "%hhu", &(pdvobj->rson_data.connectible));
+	else if (_rtw_memcmp(field, (u8 *)"loading", 2) == _TRUE)
+		num = sscanf(value, "%hhu", &(pdvobj->rson_data.loading));
+	else if (_rtw_memcmp(field, (u8 *)"res", 2) == _TRUE) {
+		str2hexbuf(value, pdvobj->rson_data.res, 16);
+		return 1;
+	} else
+		return _FALSE;
+	return num;
+}
+
+/*
+	return :	TRUE  -- competitor is taking advantage than condidate
+			FALSE -- we should continue keeping candidate
+*/
+int rtw_rson_choose(struct wlan_network **candidate, struct wlan_network *competitor)
+{
+	s16 comp_score = 0, cand_score = 0;
+	struct rtw_rson_struct rson_cand, rson_comp;
+
+	if (is_match_bssid(competitor->network.MacAddress, rtw_rson_block_bssid, rtw_rson_block_bssid_idx) == _TRUE)
+		return _FALSE;
+
+	if ((competitor == NULL)
+		|| (rtw_get_rson_struct(&(competitor->network), &rson_comp) != _TRUE)
+		|| (rson_comp.id != CONFIG_RTW_REPEATER_SON_ID))
+		return _FALSE;
+
+	comp_score = rtw_cal_rson_score(&rson_comp, competitor->network.Rssi);
+	if (comp_score == RTW_RSON_SCORE_NOTCNNT)
+		return _FALSE;
+
+	if (*candidate == NULL)
+		return _TRUE;
+	if (rtw_get_rson_struct(&((*candidate)->network), &rson_cand) != _TRUE)
+		return _FALSE;
+
+	cand_score = rtw_cal_rson_score(&rson_cand, (*candidate)->network.Rssi);
+	RTW_INFO("%s: competitor_score=%d,  candidate_score=%d\n", __func__, comp_score, cand_score);
+	if (comp_score - cand_score > RSON_SCORE_DIFF_TH)
+		return _TRUE;
+
+	return _FALSE;
+}
+
+inline u8 rtw_rson_varify_ie(u8 *p)
+{
+	u8 *ptr = NULL;
+	u8 ver;
+	u32 id;
+	u8 hopcnt;
+	u8 allcnnt;
+
+	ptr = p + 2 + sizeof(RTW_RSON_OUI);
+	ver = *ptr;
+
+	/*	for (ver == 1)	*/
+	if (ver != 1)
+		return _FALSE;
+
+	return _TRUE;
+}
+
+/*
+	Parsing RTK self-organization vendor IE
+*/
+int rtw_get_rson_struct(WLAN_BSSID_EX *bssid, struct  rtw_rson_struct *rson_data)
+{
+	sint  limit = 0;
+	u32	len;
+	u8	*p;
+
+	if ((rson_data == NULL) || (bssid == NULL))
+		return -EINVAL;
+
+	/*	Default		*/
+	rson_data->id = 0;
+	rson_data->ver = 0;
+	rson_data->hopcnt = 0;
+	rson_data->connectible = 0;
+	rson_data->loading = 0;
+	/*	fake root		*/
+	if (is_match_bssid(bssid->MacAddress, rtw_rson_root_bssid, rtw_rson_root_bssid_idx) == _TRUE) {
+		rson_data->id = CONFIG_RTW_REPEATER_SON_ID;
+		rson_data->ver = RTW_RSON_VER;
+		rson_data->hopcnt = RTW_RSON_HC_ROOT;
+		rson_data->connectible = RTW_RSON_ALLOWCONNECT;
+		rson_data->loading = 0;
+		return _TRUE;
+	}
+	limit = bssid->IELength - _BEACON_IE_OFFSET_;
+
+	for (p = bssid->IEs + _BEACON_IE_OFFSET_; ; p += (len + 2)) {
+		p = rtw_get_ie(p, _VENDOR_SPECIFIC_IE_, &len, limit);
+		limit -= len;
+		if ((p == NULL) || (len == 0))
+			break;
+		if (p && (_rtw_memcmp(p + 2, RTW_RSON_OUI, sizeof(RTW_RSON_OUI)) == _TRUE)
+			&& rtw_rson_varify_ie(p)) {
+			p = p + 2 + sizeof(RTW_RSON_OUI);
+			rson_data->ver = *p;
+			/*	for (ver == 1)		*/
+			p = p + 1;
+			rson_data->id = le32_to_cpup((__le32 *)p);
+			p = p + 4;
+			rson_data->hopcnt = *p;
+			p = p + 1;
+			rson_data->connectible = *p;
+			p = p + 1;
+			rson_data->loading = *p;
+
+			return _TRUE;
+		}
+	}
+	return -EBADMSG;
+}
+
+u32 rtw_rson_append_ie(_adapter *padapter, unsigned char *pframe, u32 *len)
+{
+	u8 *ptr, *ori, ie_len = 0;
+	struct dvobj_priv *pdvobj = adapter_to_dvobj(padapter);
+	struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
+/*	static int iii = 0;*/
+
+	if ((!pdvobj) || (!pframe))
+		return 0;
+	ptr = ori = pframe;
+	*ptr++ = _VENDOR_SPECIFIC_IE_;
+	*ptr++ = ie_len = sizeof(RTW_RSON_OUI)+sizeof(pdvobj->rson_data);
+	_rtw_memcpy(ptr, RTW_RSON_OUI, sizeof(RTW_RSON_OUI));
+	ptr = ptr + sizeof(RTW_RSON_OUI);
+	*ptr++ = pdvobj->rson_data.ver;
+	*(s32 *)ptr = cpu_to_le32(pdvobj->rson_data.id);
+	ptr = ptr + sizeof(pdvobj->rson_data.id);
+	*ptr++ = pdvobj->rson_data.hopcnt;
+	*ptr++ = pdvobj->rson_data.connectible;
+	*ptr++ = pdvobj->rson_data.loading;
+	_rtw_memcpy(ptr, pdvobj->rson_data.res, sizeof(pdvobj->rson_data.res));
+	pframe = ptr;
+/*
+	iii = iii % 20;
+	if (iii++ == 0)
+		RTW_INFO("%s : RTW RSON IE : %20ph\n", __func__, ori);
+*/
+	*len += (ie_len+2);
+	return ie_len;
+
+}
+
+void rtw_rson_do_disconnect(_adapter *padapter)
+{
+	struct dvobj_priv *pdvobj = adapter_to_dvobj(padapter);
+
+	RTW_INFO(FUNC_ADPT_FMT"\n", FUNC_ADPT_ARG(padapter));
+#ifndef CONFIG_RTW_REPEATER_SON_ROOT
+	pdvobj->rson_data.ver = RTW_RSON_VER;
+	pdvobj->rson_data.id = CONFIG_RTW_REPEATER_SON_ID;
+	pdvobj->rson_data.hopcnt = RTW_RSON_HC_NOTREADY;
+	pdvobj->rson_data.connectible = RTW_RSON_DENYCONNECT;
+	pdvobj->rson_data.loading = 0;
+	rtw_mi_tx_beacon_hdl(padapter);
+#endif
+}
+
+void rtw_rson_join_done(_adapter *padapter)
+{
+	struct dvobj_priv *pdvobj = adapter_to_dvobj(padapter);
+	WLAN_BSSID_EX	*cur_network = NULL;
+	struct rtw_rson_struct  rson_data;
+
+	RTW_INFO(FUNC_ADPT_FMT"\n", FUNC_ADPT_ARG(padapter));
+	if (!padapter->mlmepriv.cur_network_scanned)
+		return;
+	cur_network = &(padapter->mlmepriv.cur_network_scanned->network);
+	if (rtw_get_rson_struct(cur_network, &rson_data) != _TRUE) {
+		RTW_ERR("%s: try to join a improper network(%s)\n", __func__, cur_network->Ssid.Ssid);
+		return;
+	}
+
+#ifndef CONFIG_RTW_REPEATER_SON_ROOT
+	/* update rson_data */
+	pdvobj->rson_data.ver = RTW_RSON_VER;
+	pdvobj->rson_data.id = rson_data.id;
+	pdvobj->rson_data.hopcnt = rson_data.hopcnt + 1;
+	pdvobj->rson_data.connectible = RTW_RSON_ALLOWCONNECT;
+	pdvobj->rson_data.loading = 0;
+	rtw_mi_tx_beacon_hdl(padapter);
+#endif
+}
+
+int rtw_rson_isupdate_roamcan(struct mlme_priv *mlme
+	, struct wlan_network **candidate, struct wlan_network *competitor)
+{
+	struct rtw_rson_struct  rson_cand, rson_comp, rson_curr;
+	s16 comp_score, cand_score, curr_score;
+
+	if ((competitor == NULL)
+		|| (rtw_get_rson_struct(&(competitor->network), &rson_comp) != _TRUE)
+		|| (rson_comp.id != CONFIG_RTW_REPEATER_SON_ID))
+		return _FALSE;
+
+	if (is_match_bssid(competitor->network.MacAddress, rtw_rson_block_bssid, rtw_rson_block_bssid_idx) == _TRUE)
+		return _FALSE;
+
+	if ((!mlme->cur_network_scanned)
+		|| (mlme->cur_network_scanned == competitor)
+		|| (rtw_get_rson_struct(&(mlme->cur_network_scanned->network), &rson_curr)) != _TRUE)
+		return _FALSE;
+
+	if (rtw_get_passing_time_ms((u32)competitor->last_scanned) >= mlme->roam_scanr_exp_ms)
+		return _FALSE;
+
+	comp_score = rtw_cal_rson_score(&rson_comp, competitor->network.Rssi);
+	curr_score = rtw_cal_rson_score(&rson_curr, mlme->cur_network_scanned->network.Rssi);
+	if (comp_score - curr_score < RSON_SCORE_DIFF_TH)
+		return _FALSE;
+
+	if (*candidate == NULL)
+		return _TRUE;
+
+	if (rtw_get_rson_struct(&((*candidate)->network), &rson_cand) != _TRUE) {
+		RTW_ERR("%s : Unable to get rson_struct from candidate(%s -- " MAC_FMT")\n",
+				__func__, (*candidate)->network.Ssid.Ssid, MAC_ARG((*candidate)->network.MacAddress));
+		return _FALSE;
+	}
+	cand_score = rtw_cal_rson_score(&rson_cand, (*candidate)->network.Rssi);
+	RTW_DBG("comp_score=%d , cand_score=%d , curr_score=%d\n", comp_score, cand_score, curr_score);
+	if (cand_score < comp_score)
+		return _TRUE;
+
+#if 0		/*	Handle 11R protocol	*/
+#ifdef CONFIG_RTW_80211R
+	if (rtw_chk_ft_flags(adapter, RTW_FT_SUPPORTED)) {
+		ptmp = rtw_get_ie(&competitor->network.IEs[12], _MDIE_, &mdie_len, competitor->network.IELength-12);
+		if (ptmp) {
+			if (!_rtw_memcmp(&pftpriv->mdid, ptmp+2, 2))
+				goto exit;
+
+			/*The candidate don't support over-the-DS*/
+			if (rtw_chk_ft_flags(adapter, RTW_FT_STA_OVER_DS_SUPPORTED)) {
+				if ((rtw_chk_ft_flags(adapter, RTW_FT_OVER_DS_SUPPORTED) && !(*(ptmp+4) & 0x01)) ||
+					(!rtw_chk_ft_flags(adapter, RTW_FT_OVER_DS_SUPPORTED) && (*(ptmp+4) & 0x01))) {
+					RTW_INFO("FT: ignore the candidate(" MAC_FMT ") for over-the-DS\n", MAC_ARG(competitor->network.MacAddress));
+					rtw_clr_ft_flags(adapter, RTW_FT_OVER_DS_SUPPORTED);
+					goto exit;
+				}
+			}
+		} else
+			goto exit;
+	}
+#endif
+#endif
+	return _FALSE;
+}
+
+void rtw_rson_show_survey_info(struct seq_file *m, _list *plist, _list *phead)
+{
+	struct wlan_network	*pnetwork = NULL;
+	struct rtw_rson_struct  rson_data;
+	s16 rson_score;
+	u16  index = 0;
+
+	RTW_PRINT_SEL(m, "%5s  %-17s  %3s  %5s %14s  %10s  %-3s  %5s %32s\n", "index", "bssid", "ch", "id", "hop_cnt", "loading", "RSSI", "score", "ssid");
+	while (1) {
+		if (rtw_end_of_queue_search(phead, plist) == _TRUE)
+			break;
+
+		pnetwork = LIST_CONTAINOR(plist, struct wlan_network, list);
+		if (!pnetwork)
+			break;
+
+		_rtw_memset(&rson_data, 0, sizeof(rson_data));
+		rson_score = 0;
+		if (rtw_get_rson_struct(&(pnetwork->network), &rson_data) == _TRUE)
+			rson_score = rtw_cal_rson_score(&rson_data, pnetwork->network.Rssi);
+		RTW_PRINT_SEL(m, "%5d  "MAC_FMT" %3d  0x%08x %6d %10d   %6d %6d   %32s\n",
+			      ++index,
+			      MAC_ARG(pnetwork->network.MacAddress),
+			      pnetwork->network.Configuration.DSConfig,
+			      rson_data.id,
+			      rson_data.hopcnt,
+			      rson_data.loading,
+			      (int)pnetwork->network.Rssi,
+			      rson_score,
+			      pnetwork->network.Ssid.Ssid);
+		plist = get_next(plist);
+		}
+
+}
+
+/*
+	Description :	As a AP role, We need to check the qualify of associating STA.
+					We also need to check if we are ready to be associated.
+
+	return :	TRUE  -- AP REJECT this STA
+				FALSE -- AP ACCEPT this STA
+*/
+u8 rtw_rson_ap_check_sta(_adapter *padapter, u8 *pframe, uint pkt_len, unsigned short ie_offset)
+{
+	struct wlan_network	*pnetwork = NULL;
+	struct rtw_rson_struct  rson_target;
+	struct dvobj_priv *pdvobj = adapter_to_dvobj(padapter);
+	int len = 0;
+	u8 ret = _FALSE;
+	u8 *p;
+
+#ifndef CONFIG_RTW_REPEATER_SON_ROOT
+	_rtw_memset(&rson_target, 0, sizeof(rson_target));
+	for (p = pframe + WLAN_HDR_A3_LEN + ie_offset; ; p += (len + 2)) {
+		p = rtw_get_ie(p, _VENDOR_SPECIFIC_IE_, &len, pkt_len - WLAN_HDR_A3_LEN - ie_offset);
+
+		if ((p == NULL) || (len == 0))
+			break;
+
+		if (p && (_rtw_memcmp(p + 2, RTW_RSON_OUI, sizeof(RTW_RSON_OUI)) == _TRUE)
+			&& rtw_rson_varify_ie(p)) {
+			p = p + 2 + sizeof(RTW_RSON_OUI);
+			rson_target.ver = *p;
+			/*	for (ver == 1)		*/
+			p = p + 1;
+			rson_target.id = le32_to_cpup((__le32 *)p);
+			p = p + 4;
+			rson_target.hopcnt = *p;
+			p = p + 1;
+			rson_target.connectible = *p;
+			p = p + 1;
+			rson_target.loading = *p;
+			break;
+		}
+	}
+
+	if (rson_target.id == 0)		/*	Normal STA, not a RSON STA	*/
+		ret = _FALSE;
+	else if (rson_target.id != pdvobj->rson_data.id) {
+		ret = _TRUE;
+		RTW_INFO("%s : Reject AssoReq because RSON ID not match, STA=%08x, our=%08x\n",
+				__func__, rson_target.id, pdvobj->rson_data.id);
+	} else if ((pdvobj->rson_data.hopcnt == RTW_RSON_HC_NOTREADY)
+		|| (pdvobj->rson_data.connectible == RTW_RSON_DENYCONNECT)) {
+		ret = _TRUE;
+		RTW_INFO("%s : Reject AssoReq becuase our hopcnt=%d or connectbile=%d\n",
+				__func__, pdvobj->rson_data.hopcnt, pdvobj->rson_data.connectible);
+	}
+#endif
+	return ret;
+}
+
+u8 rtw_rson_scan_wk_cmd(_adapter *padapter, int op)
+{
+	struct cmd_obj *ph2c;
+	struct drvextra_cmd_parm *pdrvextra_cmd_parm;
+	struct cmd_priv *pcmdpriv = &padapter->cmdpriv;
+	u8 *extra_cmd_buf;
+	u8 res = _SUCCESS;
+
+	ph2c = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj));
+	if (ph2c == NULL) {
+		res = _FAIL;
+		goto exit;
+	}
+
+	pdrvextra_cmd_parm = (struct drvextra_cmd_parm *)rtw_zmalloc(sizeof(struct drvextra_cmd_parm));
+	if (pdrvextra_cmd_parm == NULL) {
+		rtw_mfree((u8 *)ph2c, sizeof(struct cmd_obj));
+		res = _FAIL;
+		goto exit;
+	}
+	pdrvextra_cmd_parm->ec_id = RSON_SCAN_WK_CID;
+	pdrvextra_cmd_parm->type = op;
+	pdrvextra_cmd_parm->size = 0;
+	pdrvextra_cmd_parm->pbuf = NULL;
+
+	init_h2fwcmd_w_parm_no_rsp(ph2c, pdrvextra_cmd_parm, GEN_CMD_CODE(_Set_Drv_Extra));
+
+	res = rtw_enqueue_cmd(pcmdpriv, ph2c);
+
+exit:
+	return res;
+
+}
+
+void rtw_rson_scan_cmd_hdl(_adapter *padapter, int op)
+{
+	struct cmd_priv *pcmdpriv = &padapter->cmdpriv;
+	struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
+	struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
+	u8 val8;
+
+	if (mlmeext_chk_scan_state(pmlmeext, SCAN_DISABLE) != _TRUE)
+		return;
+	if (op == RSON_SCAN_PROCESS) {
+		padapter->rtw_rson_scanstage = RSON_SCAN_PROCESS;
+		val8 = 0x1e;
+		rtw_hal_set_odm_var(padapter, HAL_ODM_INITIAL_GAIN, &val8, _FALSE);
+		val8 = 1;
+		rtw_hal_set_hwreg(padapter, HW_VAR_MLME_SITESURVEY, (u8 *)(&val8));
+		issue_probereq(padapter, NULL, NULL);
+		/*	stop rson_scan after 100ms	*/
+		_set_timer(&(pmlmeext->rson_scan_timer), 100);
+	} else if  (op == RSON_SCAN_DISABLE) {
+		padapter->rtw_rson_scanstage = RSON_SCAN_DISABLE;
+		val8 = 0;
+		rtw_hal_set_hwreg(padapter, HW_VAR_MLME_SITESURVEY, (u8 *)(&val8));
+		val8 = 0xff;
+		rtw_hal_set_odm_var(padapter, HAL_ODM_INITIAL_GAIN, &val8, _FALSE);
+		/*	report_surveydone_event(padapter);*/
+		if (pmlmepriv->to_join == _TRUE) {
+			if (check_fwstate(pmlmepriv, WIFI_ADHOC_STATE) != _TRUE) {
+				int s_ret;
+
+				set_fwstate(pmlmepriv, _FW_UNDER_LINKING);
+				pmlmepriv->to_join = _FALSE;
+				s_ret = rtw_select_and_join_from_scanned_queue(pmlmepriv);
+				if (s_ret == _SUCCESS)
+					_set_timer(&pmlmepriv->assoc_timer, MAX_JOIN_TIMEOUT);
+				else if (s_ret == 2) {
+					_clr_fwstate_(pmlmepriv, _FW_UNDER_LINKING);
+					rtw_indicate_connect(padapter);
+				} else {
+					RTW_INFO("try_to_join, but select scanning queue fail, to_roam:%d\n", rtw_to_roam(padapter));
+					if (rtw_to_roam(padapter) != 0) {
+						if (rtw_dec_to_roam(padapter) == 0) {
+							rtw_set_to_roam(padapter, 0);
+#ifdef CONFIG_INTEL_WIDI
+							if (padapter->mlmepriv.widi_state == INTEL_WIDI_STATE_ROAMING) {
+								_rtw_memset(pmlmepriv->sa_ext, 0x00, L2SDTA_SERVICE_VE_LEN);
+								intel_widi_wk_cmd(padapter, INTEL_WIDI_LISTEN_WK, NULL, 0);
+								RTW_INFO("change to widi listen\n");
+							}
+#endif /* CONFIG_INTEL_WIDI */
+							rtw_free_assoc_resources(padapter, _TRUE);
+							rtw_indicate_disconnect(padapter, 0, _FALSE);
+						} else
+							pmlmepriv->to_join = _TRUE;
+					} else
+						rtw_indicate_disconnect(padapter, 0, _FALSE);
+					_clr_fwstate_(pmlmepriv, _FW_UNDER_LINKING);
+				}
+			}
+		} else {
+			if (rtw_chk_roam_flags(padapter, RTW_ROAM_ACTIVE)) {
+				if (check_fwstate(pmlmepriv, WIFI_STATION_STATE)
+				    && check_fwstate(pmlmepriv, _FW_LINKED)) {
+					if (rtw_select_roaming_candidate(pmlmepriv) == _SUCCESS) {
+#ifdef CONFIG_RTW_80211R
+						if (rtw_chk_ft_flags(padapter, RTW_FT_OVER_DS_SUPPORTED)) {
+							start_clnt_ft_action(adapter, (u8 *)pmlmepriv->roam_network->network.MacAddress);
+						} else {
+							/*wait a little time to retrieve packets buffered in the current ap while scan*/
+							_set_timer(&pmlmeext->ft_roam_timer, 30);
+						}
+#else
+						receive_disconnect(padapter, pmlmepriv->cur_network.network.MacAddress
+							, WLAN_REASON_ACTIVE_ROAM, _FALSE);
+#endif
+					}
+				}
+			}
+			issue_action_BSSCoexistPacket(padapter);
+			issue_action_BSSCoexistPacket(padapter);
+			issue_action_BSSCoexistPacket(padapter);
+		}
+	} else {
+		RTW_ERR("%s : improper parameter -- op = %d\n", __func__, op);
+	}
+}
+
+#endif	/* CONFIG_RTW_REPEATER_SON */
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/core/rtw_sdio.c linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/core/rtw_sdio.c
--- linux-5.6.3/3rdparty/rtl8821ce/core/rtw_sdio.c	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/core/rtw_sdio.c	2020-04-10 16:35:06.778658294 +0300
@@ -0,0 +1,130 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2015 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#define _RTW_SDIO_C_
+
+#include <drv_types.h>		/* struct dvobj_priv and etc. */
+#include <drv_types_sdio.h>	/* RTW_SDIO_ADDR_CMD52_GEN */
+
+/*
+ * Description:
+ *	Use SDIO cmd52 or cmd53 to read/write data
+ *
+ * Parameters:
+ *	d	pointer of device object(struct dvobj_priv)
+ *	addr	SDIO address, 17 bits
+ *	buf	buffer for I/O
+ *	len	length
+ *	write	0:read, 1:write
+ *	cmd52	0:cmd52, 1:cmd53
+ *
+ * Return:
+ *	_SUCCESS	I/O ok.
+ *	_FAIL		I/O fail.
+ */
+static u8 sdio_io(struct dvobj_priv *d, u32 addr, void *buf, size_t len, u8 write, u8 cmd52)
+{
+	u32 addr_drv;	/* address with driver defined bit */
+	int err;
+	u8 retry = 0;
+	u8 stop_retry = _FALSE;	/* flag for stopping retry or not */
+
+
+	if (rtw_is_surprise_removed(dvobj_get_primary_adapter(d))) {
+		RTW_ERR("%s: bSurpriseRemoved, skip %s 0x%05x, %zu bytes\n",
+			__FUNCTION__, write?"write":"read", addr, len);
+		return _FAIL;
+	}
+
+	addr_drv = addr;
+	if (cmd52)
+		addr_drv = RTW_SDIO_ADDR_CMD52_GEN(addr_drv);
+
+	do {
+		if (write)
+			err = d->intf_ops->write(d, addr_drv, buf, len, 0);
+		else
+			err = d->intf_ops->read(d, addr_drv, buf, len, 0);
+		if (!err) {
+			if (retry) {
+				RTW_INFO("%s: Retry %s OK! addr=0x%05x %zu bytes, retry=%u,%u\n",
+					 __FUNCTION__, write?"write":"read",
+					 addr, len, retry, ATOMIC_READ(&d->continual_io_error));
+				RTW_INFO_DUMP("Data: ", buf, len);
+			}
+			rtw_reset_continual_io_error(d);
+			break;
+		}
+		RTW_ERR("%s: %s FAIL! error(%d) addr=0x%05x %zu bytes, retry=%u,%u\n",
+			__FUNCTION__, write?"write":"read", err, addr, len,
+			retry, ATOMIC_READ(&d->continual_io_error));
+
+		retry++;
+		stop_retry = rtw_inc_and_chk_continual_io_error(d);
+		if ((err == -1) || (stop_retry == _TRUE) || (retry > SD_IO_TRY_CNT)) {
+			/* critical error, unrecoverable */
+			RTW_ERR("%s: Fatal error! Set surprise remove flag ON! (retry=%u,%u)\n",
+				__FUNCTION__, retry, ATOMIC_READ(&d->continual_io_error));
+			rtw_set_surprise_removed(dvobj_get_primary_adapter(d));
+			return _FAIL;
+		}
+
+		/* WLAN IOREG or SDIO Local */
+		if ((addr & 0x10000) || !(addr & 0xE000)) {
+			RTW_WARN("%s: Retry %s addr=0x%05x %zu bytes, retry=%u,%u\n",
+				 __FUNCTION__, write?"write":"read", addr, len,
+				 retry, ATOMIC_READ(&d->continual_io_error));
+			continue;
+		}
+		return _FAIL;
+	} while (1);
+
+	return _SUCCESS;
+}
+
+u8 rtw_sdio_read_cmd52(struct dvobj_priv *d, u32 addr, void *buf, size_t len)
+{
+	return sdio_io(d, addr, buf, len, 0, 1);
+}
+
+u8 rtw_sdio_read_cmd53(struct dvobj_priv *d, u32 addr, void *buf, size_t len)
+{
+	return sdio_io(d, addr, buf, len, 0, 0);
+}
+
+u8 rtw_sdio_write_cmd52(struct dvobj_priv *d, u32 addr, void *buf, size_t len)
+{
+	return sdio_io(d, addr, buf, len, 1, 1);
+}
+
+u8 rtw_sdio_write_cmd53(struct dvobj_priv *d, u32 addr, void *buf, size_t len)
+{
+	return sdio_io(d, addr, buf, len, 1, 0);
+}
+
+u8 rtw_sdio_f0_read(struct dvobj_priv *d, u32 addr, void *buf, size_t len)
+{
+	int err;
+	u8 ret;
+
+
+	ret = _SUCCESS;
+	addr = RTW_SDIO_ADDR_F0_GEN(addr);
+
+	err = d->intf_ops->read(d, addr, buf, len, 0);
+	if (err)
+		ret = _FAIL;
+
+	return ret;
+}
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/core/rtw_security.c linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/core/rtw_security.c
--- linux-5.6.3/3rdparty/rtl8821ce/core/rtw_security.c	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/core/rtw_security.c	2020-04-10 16:35:06.778658294 +0300
@@ -0,0 +1,3408 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#define  _RTW_SECURITY_C_
+
+#include <drv_types.h>
+
+static const char *_security_type_str[] = {
+	"N/A",
+	"WEP40",
+	"TKIP",
+	"TKIP_WM",
+	"AES",
+	"WEP104",
+	"SMS4",
+	"WEP_WPA",
+	"BIP",
+};
+
+const char *security_type_str(u8 value)
+{
+#ifdef CONFIG_IEEE80211W
+	if (value <= _BIP_)
+#else
+	if (value <= _WEP_WPA_MIXED_)
+#endif
+		return _security_type_str[value];
+	return NULL;
+}
+
+#ifdef DBG_SW_SEC_CNT
+#define WEP_SW_ENC_CNT_INC(sec, ra) do {\
+	if (is_broadcast_mac_addr(ra)) \
+		sec->wep_sw_enc_cnt_bc++; \
+	else if (is_multicast_mac_addr(ra)) \
+		sec->wep_sw_enc_cnt_mc++; \
+	else \
+		sec->wep_sw_enc_cnt_uc++; \
+	} while (0)
+
+#define WEP_SW_DEC_CNT_INC(sec, ra) do {\
+	if (is_broadcast_mac_addr(ra)) \
+		sec->wep_sw_dec_cnt_bc++; \
+	else if (is_multicast_mac_addr(ra)) \
+		sec->wep_sw_dec_cnt_mc++; \
+	else \
+		sec->wep_sw_dec_cnt_uc++; \
+	} while (0)
+
+#define TKIP_SW_ENC_CNT_INC(sec, ra) do {\
+	if (is_broadcast_mac_addr(ra)) \
+		sec->tkip_sw_enc_cnt_bc++; \
+	else if (is_multicast_mac_addr(ra)) \
+		sec->tkip_sw_enc_cnt_mc++; \
+	else \
+		sec->tkip_sw_enc_cnt_uc++; \
+	} while (0)
+
+#define TKIP_SW_DEC_CNT_INC(sec, ra) do {\
+	if (is_broadcast_mac_addr(ra)) \
+		sec->tkip_sw_dec_cnt_bc++; \
+	else if (is_multicast_mac_addr(ra)) \
+		sec->tkip_sw_dec_cnt_mc++; \
+	else \
+		sec->tkip_sw_dec_cnt_uc++; \
+	} while (0)
+
+#define AES_SW_ENC_CNT_INC(sec, ra) do {\
+	if (is_broadcast_mac_addr(ra)) \
+		sec->aes_sw_enc_cnt_bc++; \
+	else if (is_multicast_mac_addr(ra)) \
+		sec->aes_sw_enc_cnt_mc++; \
+	else \
+		sec->aes_sw_enc_cnt_uc++; \
+	} while (0)
+
+#define AES_SW_DEC_CNT_INC(sec, ra) do {\
+	if (is_broadcast_mac_addr(ra)) \
+		sec->aes_sw_dec_cnt_bc++; \
+	else if (is_multicast_mac_addr(ra)) \
+		sec->aes_sw_dec_cnt_mc++; \
+	else \
+		sec->aes_sw_dec_cnt_uc++; \
+	} while (0)
+#else
+#define WEP_SW_ENC_CNT_INC(sec, ra)
+#define WEP_SW_DEC_CNT_INC(sec, ra)
+#define TKIP_SW_ENC_CNT_INC(sec, ra)
+#define TKIP_SW_DEC_CNT_INC(sec, ra)
+#define AES_SW_ENC_CNT_INC(sec, ra)
+#define AES_SW_DEC_CNT_INC(sec, ra)
+#endif /* DBG_SW_SEC_CNT */
+
+/* *****WEP related***** */
+
+#define CRC32_POLY 0x04c11db7
+
+struct arc4context {
+	u32 x;
+	u32 y;
+	u8 state[256];
+};
+
+
+static void arcfour_init(struct arc4context	*parc4ctx, u8 *key, u32	key_len)
+{
+	u32	t, u;
+	u32	keyindex;
+	u32	stateindex;
+	u8 *state;
+	u32	counter;
+	state = parc4ctx->state;
+	parc4ctx->x = 0;
+	parc4ctx->y = 0;
+	for (counter = 0; counter < 256; counter++)
+		state[counter] = (u8)counter;
+	keyindex = 0;
+	stateindex = 0;
+	for (counter = 0; counter < 256; counter++) {
+		t = state[counter];
+		stateindex = (stateindex + key[keyindex] + t) & 0xff;
+		u = state[stateindex];
+		state[stateindex] = (u8)t;
+		state[counter] = (u8)u;
+		if (++keyindex >= key_len)
+			keyindex = 0;
+	}
+}
+static u32 arcfour_byte(struct arc4context	*parc4ctx)
+{
+	u32 x;
+	u32 y;
+	u32 sx, sy;
+	u8 *state;
+	state = parc4ctx->state;
+	x = (parc4ctx->x + 1) & 0xff;
+	sx = state[x];
+	y = (sx + parc4ctx->y) & 0xff;
+	sy = state[y];
+	parc4ctx->x = x;
+	parc4ctx->y = y;
+	state[y] = (u8)sx;
+	state[x] = (u8)sy;
+	return state[(sx + sy) & 0xff];
+}
+
+
+static void arcfour_encrypt(struct arc4context	*parc4ctx,
+			    u8 *dest,
+			    u8 *src,
+			    u32 len)
+{
+	u32	i;
+	for (i = 0; i < len; i++)
+		dest[i] = src[i] ^ (unsigned char)arcfour_byte(parc4ctx);
+}
+
+static sint bcrc32initialized = 0;
+static u32 crc32_table[256];
+
+
+static u8 crc32_reverseBit(u8 data)
+{
+	return (u8)((data << 7) & 0x80) | ((data << 5) & 0x40) | ((data << 3) & 0x20) | ((data << 1) & 0x10) | ((data >> 1) & 0x08) | ((data >> 3) & 0x04) | ((data >> 5) & 0x02) | ((
+				data >> 7) & 0x01) ;
+}
+
+static void crc32_init(void)
+{
+	if (bcrc32initialized == 1)
+		goto exit;
+	else {
+		sint i, j;
+		u32 c;
+		u8 *p = (u8 *)&c, *p1;
+		u8 k;
+
+		c = 0x12340000;
+
+		for (i = 0; i < 256; ++i) {
+			k = crc32_reverseBit((u8)i);
+			for (c = ((u32)k) << 24, j = 8; j > 0; --j)
+				c = c & 0x80000000 ? (c << 1) ^ CRC32_POLY : (c << 1);
+			p1 = (u8 *)&crc32_table[i];
+
+			p1[0] = crc32_reverseBit(p[3]);
+			p1[1] = crc32_reverseBit(p[2]);
+			p1[2] = crc32_reverseBit(p[1]);
+			p1[3] = crc32_reverseBit(p[0]);
+		}
+		bcrc32initialized = 1;
+	}
+exit:
+	return;
+}
+
+static u32 getcrc32(u8 *buf, sint len)
+{
+	u8 *p;
+	u32  crc;
+	if (bcrc32initialized == 0)
+		crc32_init();
+
+	crc = 0xffffffff;       /* preload shift register, per CRC-32 spec */
+
+	for (p = buf; len > 0; ++p, --len)
+		crc = crc32_table[(crc ^ *p) & 0xff] ^ (crc >> 8);
+	return ~crc;    /* transmit complement, per CRC-32 spec */
+}
+
+
+/*
+	Need to consider the fragment  situation
+*/
+void rtw_wep_encrypt(_adapter *padapter, u8 *pxmitframe)
+{
+	/* exclude ICV */
+
+	unsigned char	crc[4];
+	struct arc4context	 mycontext;
+
+	sint	curfragnum, length;
+	u32	keylength;
+
+	u8	*pframe, *payload, *iv;   /* ,*wepkey */
+	u8	wepkey[16];
+	u8   hw_hdr_offset = 0;
+	struct	pkt_attrib	*pattrib = &((struct xmit_frame *)pxmitframe)->attrib;
+	struct	security_priv	*psecuritypriv = &padapter->securitypriv;
+	struct	xmit_priv		*pxmitpriv = &padapter->xmitpriv;
+
+
+
+	if (((struct xmit_frame *)pxmitframe)->buf_addr == NULL)
+		return;
+
+#ifdef CONFIG_USB_TX_AGGREGATION
+	hw_hdr_offset = TXDESC_SIZE +
+		(((struct xmit_frame *)pxmitframe)->pkt_offset * PACKET_OFFSET_SZ);
+#else
+#ifdef CONFIG_TX_EARLY_MODE
+	hw_hdr_offset = TXDESC_OFFSET + EARLY_MODE_INFO_SIZE;
+#else
+	hw_hdr_offset = TXDESC_OFFSET;
+#endif
+#endif
+
+	pframe = ((struct xmit_frame *)pxmitframe)->buf_addr + hw_hdr_offset;
+
+	/* start to encrypt each fragment */
+	if ((pattrib->encrypt == _WEP40_) || (pattrib->encrypt == _WEP104_)) {
+		keylength = psecuritypriv->dot11DefKeylen[psecuritypriv->dot11PrivacyKeyIndex];
+
+		for (curfragnum = 0; curfragnum < pattrib->nr_frags; curfragnum++) {
+			iv = pframe + pattrib->hdrlen;
+			_rtw_memcpy(&wepkey[0], iv, 3);
+			_rtw_memcpy(&wepkey[3], &psecuritypriv->dot11DefKey[psecuritypriv->dot11PrivacyKeyIndex].skey[0], keylength);
+			payload = pframe + pattrib->iv_len + pattrib->hdrlen;
+
+			if ((curfragnum + 1) == pattrib->nr_frags) {
+				/* the last fragment */
+
+				length = pattrib->last_txcmdsz - pattrib->hdrlen - pattrib->iv_len - pattrib->icv_len;
+
+				*((u32 *)crc) = cpu_to_le32(getcrc32(payload, length));
+
+				arcfour_init(&mycontext, wepkey, 3 + keylength);
+				arcfour_encrypt(&mycontext, payload, payload, length);
+				arcfour_encrypt(&mycontext, payload + length, crc, 4);
+
+			} else {
+				length = pxmitpriv->frag_len - pattrib->hdrlen - pattrib->iv_len - pattrib->icv_len ;
+				*((u32 *)crc) = cpu_to_le32(getcrc32(payload, length));
+				arcfour_init(&mycontext, wepkey, 3 + keylength);
+				arcfour_encrypt(&mycontext, payload, payload, length);
+				arcfour_encrypt(&mycontext, payload + length, crc, 4);
+
+				pframe += pxmitpriv->frag_len;
+				pframe = (u8 *)RND4((SIZE_PTR)(pframe));
+
+			}
+
+		}
+
+		WEP_SW_ENC_CNT_INC(psecuritypriv, pattrib->ra);
+	}
+
+
+}
+
+void rtw_wep_decrypt(_adapter  *padapter, u8 *precvframe)
+{
+	/* exclude ICV */
+	u8	crc[4];
+	struct arc4context	 mycontext;
+	sint	length;
+	u32	keylength;
+	u8	*pframe, *payload, *iv, wepkey[16];
+	u8	 keyindex;
+	struct	rx_pkt_attrib	*prxattrib = &(((union recv_frame *)precvframe)->u.hdr.attrib);
+	struct	security_priv	*psecuritypriv = &padapter->securitypriv;
+
+
+	pframe = (unsigned char *)((union recv_frame *)precvframe)->u.hdr.rx_data;
+
+	/* start to decrypt recvframe */
+	if ((prxattrib->encrypt == _WEP40_) || (prxattrib->encrypt == _WEP104_)) {
+		iv = pframe + prxattrib->hdrlen;
+		/* keyindex=(iv[3]&0x3); */
+		keyindex = prxattrib->key_index;
+		keylength = psecuritypriv->dot11DefKeylen[keyindex];
+		_rtw_memcpy(&wepkey[0], iv, 3);
+		/* _rtw_memcpy(&wepkey[3], &psecuritypriv->dot11DefKey[psecuritypriv->dot11PrivacyKeyIndex].skey[0],keylength); */
+		_rtw_memcpy(&wepkey[3], &psecuritypriv->dot11DefKey[keyindex].skey[0], keylength);
+		length = ((union recv_frame *)precvframe)->u.hdr.len - prxattrib->hdrlen - prxattrib->iv_len;
+
+		payload = pframe + prxattrib->iv_len + prxattrib->hdrlen;
+
+		/* decrypt payload include icv */
+		arcfour_init(&mycontext, wepkey, 3 + keylength);
+		arcfour_encrypt(&mycontext, payload, payload,  length);
+
+		/* calculate icv and compare the icv */
+		*((u32 *)crc) = le32_to_cpu(getcrc32(payload, length - 4));
+
+
+		WEP_SW_DEC_CNT_INC(psecuritypriv, prxattrib->ra);
+	}
+
+
+	return;
+
+}
+
+/* 3		=====TKIP related===== */
+
+static u32 secmicgetuint32(u8 *p)
+/* Convert from Byte[] to Us4Byte32 in a portable way */
+{
+	s32 i;
+	u32 res = 0;
+	for (i = 0; i < 4; i++)
+		res |= ((u32)(*p++)) << (8 * i);
+	return res;
+}
+
+static void secmicputuint32(u8 *p, u32 val)
+/* Convert from Us4Byte32 to Byte[] in a portable way */
+{
+	long i;
+	for (i = 0; i < 4; i++) {
+		*p++ = (u8)(val & 0xff);
+		val >>= 8;
+	}
+}
+
+static void secmicclear(struct mic_data *pmicdata)
+{
+	/* Reset the state to the empty message. */
+	pmicdata->L = pmicdata->K0;
+	pmicdata->R = pmicdata->K1;
+	pmicdata->nBytesInM = 0;
+	pmicdata->M = 0;
+}
+
+void rtw_secmicsetkey(struct mic_data *pmicdata, u8 *key)
+{
+	/* Set the key */
+	pmicdata->K0 = secmicgetuint32(key);
+	pmicdata->K1 = secmicgetuint32(key + 4);
+	/* and reset the message */
+	secmicclear(pmicdata);
+}
+
+void rtw_secmicappendbyte(struct mic_data *pmicdata, u8 b)
+{
+	/* Append the byte to our word-sized buffer */
+	pmicdata->M |= ((unsigned long)b) << (8 * pmicdata->nBytesInM);
+	pmicdata->nBytesInM++;
+	/* Process the word if it is full. */
+	if (pmicdata->nBytesInM >= 4) {
+		pmicdata->L ^= pmicdata->M;
+		pmicdata->R ^= ROL32(pmicdata->L, 17);
+		pmicdata->L += pmicdata->R;
+		pmicdata->R ^= ((pmicdata->L & 0xff00ff00) >> 8) | ((pmicdata->L & 0x00ff00ff) << 8);
+		pmicdata->L += pmicdata->R;
+		pmicdata->R ^= ROL32(pmicdata->L, 3);
+		pmicdata->L += pmicdata->R;
+		pmicdata->R ^= ROR32(pmicdata->L, 2);
+		pmicdata->L += pmicdata->R;
+		/* Clear the buffer */
+		pmicdata->M = 0;
+		pmicdata->nBytesInM = 0;
+	}
+}
+
+void rtw_secmicappend(struct mic_data *pmicdata, u8 *src, u32 nbytes)
+{
+	/* This is simple */
+	while (nbytes > 0) {
+		rtw_secmicappendbyte(pmicdata, *src++);
+		nbytes--;
+	}
+}
+
+void rtw_secgetmic(struct mic_data *pmicdata, u8 *dst)
+{
+	/* Append the minimum padding */
+	rtw_secmicappendbyte(pmicdata, 0x5a);
+	rtw_secmicappendbyte(pmicdata, 0);
+	rtw_secmicappendbyte(pmicdata, 0);
+	rtw_secmicappendbyte(pmicdata, 0);
+	rtw_secmicappendbyte(pmicdata, 0);
+	/* and then zeroes until the length is a multiple of 4 */
+	while (pmicdata->nBytesInM != 0)
+		rtw_secmicappendbyte(pmicdata, 0);
+	/* The appendByte function has already computed the result. */
+	secmicputuint32(dst, pmicdata->L);
+	secmicputuint32(dst + 4, pmicdata->R);
+	/* Reset to the empty message. */
+	secmicclear(pmicdata);
+}
+
+
+void rtw_seccalctkipmic(u8 *key, u8 *header, u8 *data, u32 data_len, u8 *mic_code, u8 pri)
+{
+
+	struct mic_data	micdata;
+	u8 priority[4] = {0x0, 0x0, 0x0, 0x0};
+	rtw_secmicsetkey(&micdata, key);
+	priority[0] = pri;
+
+	/* Michael MIC pseudo header: DA, SA, 3 x 0, Priority */
+	if (header[1] & 1) { /* ToDS==1 */
+		rtw_secmicappend(&micdata, &header[16], 6);  /* DA */
+		if (header[1] & 2) /* From Ds==1 */
+			rtw_secmicappend(&micdata, &header[24], 6);
+		else
+			rtw_secmicappend(&micdata, &header[10], 6);
+	} else {	/* ToDS==0 */
+		rtw_secmicappend(&micdata, &header[4], 6);   /* DA */
+		if (header[1] & 2) /* From Ds==1 */
+			rtw_secmicappend(&micdata, &header[16], 6);
+		else
+			rtw_secmicappend(&micdata, &header[10], 6);
+
+	}
+	rtw_secmicappend(&micdata, &priority[0], 4);
+
+
+	rtw_secmicappend(&micdata, data, data_len);
+
+	rtw_secgetmic(&micdata, mic_code);
+}
+
+
+
+
+/* macros for extraction/creation of unsigned char/unsigned short values */
+#define RotR1(v16)   ((((v16) >> 1) & 0x7FFF) ^ (((v16) & 1) << 15))
+#define   Lo8(v16)   ((u8)((v16)       & 0x00FF))
+#define   Hi8(v16)   ((u8)(((v16) >> 8) & 0x00FF))
+#define  Lo16(v32)   ((u16)((v32)       & 0xFFFF))
+#define  Hi16(v32)   ((u16)(((v32) >> 16) & 0xFFFF))
+#define  Mk16(hi, lo) ((lo) ^ (((u16)(hi)) << 8))
+
+/* select the Nth 16-bit word of the temporal key unsigned char array TK[]  */
+#define  TK16(N)     Mk16(tk[2*(N)+1], tk[2*(N)])
+
+/* S-box lookup: 16 bits --> 16 bits */
+#define _S_(v16)     (Sbox1[0][Lo8(v16)] ^ Sbox1[1][Hi8(v16)])
+
+/* fixed algorithm "parameters" */
+#define PHASE1_LOOP_CNT   8    /* this needs to be "big enough"     */
+#define TA_SIZE           6    /*  48-bit transmitter address      */
+#define TK_SIZE          16    /* 128-bit temporal key             */
+#define P1K_SIZE         10    /*  80-bit Phase1 key               */
+#define RC4_KEY_SIZE     16    /* 128-bit RC4KEY (104 bits unknown) */
+
+
+/* 2-unsigned char by 2-unsigned char subset of the full AES S-box table */
+static const unsigned short Sbox1[2][256] =      /* Sbox for hash (can be in ROM)    */
+{ {
+		0xC6A5, 0xF884, 0xEE99, 0xF68D, 0xFF0D, 0xD6BD, 0xDEB1, 0x9154,
+		0x6050, 0x0203, 0xCEA9, 0x567D, 0xE719, 0xB562, 0x4DE6, 0xEC9A,
+		0x8F45, 0x1F9D, 0x8940, 0xFA87, 0xEF15, 0xB2EB, 0x8EC9, 0xFB0B,
+		0x41EC, 0xB367, 0x5FFD, 0x45EA, 0x23BF, 0x53F7, 0xE496, 0x9B5B,
+		0x75C2, 0xE11C, 0x3DAE, 0x4C6A, 0x6C5A, 0x7E41, 0xF502, 0x834F,
+		0x685C, 0x51F4, 0xD134, 0xF908, 0xE293, 0xAB73, 0x6253, 0x2A3F,
+		0x080C, 0x9552, 0x4665, 0x9D5E, 0x3028, 0x37A1, 0x0A0F, 0x2FB5,
+		0x0E09, 0x2436, 0x1B9B, 0xDF3D, 0xCD26, 0x4E69, 0x7FCD, 0xEA9F,
+		0x121B, 0x1D9E, 0x5874, 0x342E, 0x362D, 0xDCB2, 0xB4EE, 0x5BFB,
+		0xA4F6, 0x764D, 0xB761, 0x7DCE, 0x527B, 0xDD3E, 0x5E71, 0x1397,
+		0xA6F5, 0xB968, 0x0000, 0xC12C, 0x4060, 0xE31F, 0x79C8, 0xB6ED,
+		0xD4BE, 0x8D46, 0x67D9, 0x724B, 0x94DE, 0x98D4, 0xB0E8, 0x854A,
+		0xBB6B, 0xC52A, 0x4FE5, 0xED16, 0x86C5, 0x9AD7, 0x6655, 0x1194,
+		0x8ACF, 0xE910, 0x0406, 0xFE81, 0xA0F0, 0x7844, 0x25BA, 0x4BE3,
+		0xA2F3, 0x5DFE, 0x80C0, 0x058A, 0x3FAD, 0x21BC, 0x7048, 0xF104,
+		0x63DF, 0x77C1, 0xAF75, 0x4263, 0x2030, 0xE51A, 0xFD0E, 0xBF6D,
+		0x814C, 0x1814, 0x2635, 0xC32F, 0xBEE1, 0x35A2, 0x88CC, 0x2E39,
+		0x9357, 0x55F2, 0xFC82, 0x7A47, 0xC8AC, 0xBAE7, 0x322B, 0xE695,
+		0xC0A0, 0x1998, 0x9ED1, 0xA37F, 0x4466, 0x547E, 0x3BAB, 0x0B83,
+		0x8CCA, 0xC729, 0x6BD3, 0x283C, 0xA779, 0xBCE2, 0x161D, 0xAD76,
+		0xDB3B, 0x6456, 0x744E, 0x141E, 0x92DB, 0x0C0A, 0x486C, 0xB8E4,
+		0x9F5D, 0xBD6E, 0x43EF, 0xC4A6, 0x39A8, 0x31A4, 0xD337, 0xF28B,
+		0xD532, 0x8B43, 0x6E59, 0xDAB7, 0x018C, 0xB164, 0x9CD2, 0x49E0,
+		0xD8B4, 0xACFA, 0xF307, 0xCF25, 0xCAAF, 0xF48E, 0x47E9, 0x1018,
+		0x6FD5, 0xF088, 0x4A6F, 0x5C72, 0x3824, 0x57F1, 0x73C7, 0x9751,
+		0xCB23, 0xA17C, 0xE89C, 0x3E21, 0x96DD, 0x61DC, 0x0D86, 0x0F85,
+		0xE090, 0x7C42, 0x71C4, 0xCCAA, 0x90D8, 0x0605, 0xF701, 0x1C12,
+		0xC2A3, 0x6A5F, 0xAEF9, 0x69D0, 0x1791, 0x9958, 0x3A27, 0x27B9,
+		0xD938, 0xEB13, 0x2BB3, 0x2233, 0xD2BB, 0xA970, 0x0789, 0x33A7,
+		0x2DB6, 0x3C22, 0x1592, 0xC920, 0x8749, 0xAAFF, 0x5078, 0xA57A,
+		0x038F, 0x59F8, 0x0980, 0x1A17, 0x65DA, 0xD731, 0x84C6, 0xD0B8,
+		0x82C3, 0x29B0, 0x5A77, 0x1E11, 0x7BCB, 0xA8FC, 0x6DD6, 0x2C3A,
+	},
+
+
+	{  /* second half of table is unsigned char-reversed version of first! */
+		0xA5C6, 0x84F8, 0x99EE, 0x8DF6, 0x0DFF, 0xBDD6, 0xB1DE, 0x5491,
+		0x5060, 0x0302, 0xA9CE, 0x7D56, 0x19E7, 0x62B5, 0xE64D, 0x9AEC,
+		0x458F, 0x9D1F, 0x4089, 0x87FA, 0x15EF, 0xEBB2, 0xC98E, 0x0BFB,
+		0xEC41, 0x67B3, 0xFD5F, 0xEA45, 0xBF23, 0xF753, 0x96E4, 0x5B9B,
+		0xC275, 0x1CE1, 0xAE3D, 0x6A4C, 0x5A6C, 0x417E, 0x02F5, 0x4F83,
+		0x5C68, 0xF451, 0x34D1, 0x08F9, 0x93E2, 0x73AB, 0x5362, 0x3F2A,
+		0x0C08, 0x5295, 0x6546, 0x5E9D, 0x2830, 0xA137, 0x0F0A, 0xB52F,
+		0x090E, 0x3624, 0x9B1B, 0x3DDF, 0x26CD, 0x694E, 0xCD7F, 0x9FEA,
+		0x1B12, 0x9E1D, 0x7458, 0x2E34, 0x2D36, 0xB2DC, 0xEEB4, 0xFB5B,
+		0xF6A4, 0x4D76, 0x61B7, 0xCE7D, 0x7B52, 0x3EDD, 0x715E, 0x9713,
+		0xF5A6, 0x68B9, 0x0000, 0x2CC1, 0x6040, 0x1FE3, 0xC879, 0xEDB6,
+		0xBED4, 0x468D, 0xD967, 0x4B72, 0xDE94, 0xD498, 0xE8B0, 0x4A85,
+		0x6BBB, 0x2AC5, 0xE54F, 0x16ED, 0xC586, 0xD79A, 0x5566, 0x9411,
+		0xCF8A, 0x10E9, 0x0604, 0x81FE, 0xF0A0, 0x4478, 0xBA25, 0xE34B,
+		0xF3A2, 0xFE5D, 0xC080, 0x8A05, 0xAD3F, 0xBC21, 0x4870, 0x04F1,
+		0xDF63, 0xC177, 0x75AF, 0x6342, 0x3020, 0x1AE5, 0x0EFD, 0x6DBF,
+		0x4C81, 0x1418, 0x3526, 0x2FC3, 0xE1BE, 0xA235, 0xCC88, 0x392E,
+		0x5793, 0xF255, 0x82FC, 0x477A, 0xACC8, 0xE7BA, 0x2B32, 0x95E6,
+		0xA0C0, 0x9819, 0xD19E, 0x7FA3, 0x6644, 0x7E54, 0xAB3B, 0x830B,
+		0xCA8C, 0x29C7, 0xD36B, 0x3C28, 0x79A7, 0xE2BC, 0x1D16, 0x76AD,
+		0x3BDB, 0x5664, 0x4E74, 0x1E14, 0xDB92, 0x0A0C, 0x6C48, 0xE4B8,
+		0x5D9F, 0x6EBD, 0xEF43, 0xA6C4, 0xA839, 0xA431, 0x37D3, 0x8BF2,
+		0x32D5, 0x438B, 0x596E, 0xB7DA, 0x8C01, 0x64B1, 0xD29C, 0xE049,
+		0xB4D8, 0xFAAC, 0x07F3, 0x25CF, 0xAFCA, 0x8EF4, 0xE947, 0x1810,
+		0xD56F, 0x88F0, 0x6F4A, 0x725C, 0x2438, 0xF157, 0xC773, 0x5197,
+		0x23CB, 0x7CA1, 0x9CE8, 0x213E, 0xDD96, 0xDC61, 0x860D, 0x850F,
+		0x90E0, 0x427C, 0xC471, 0xAACC, 0xD890, 0x0506, 0x01F7, 0x121C,
+		0xA3C2, 0x5F6A, 0xF9AE, 0xD069, 0x9117, 0x5899, 0x273A, 0xB927,
+		0x38D9, 0x13EB, 0xB32B, 0x3322, 0xBBD2, 0x70A9, 0x8907, 0xA733,
+		0xB62D, 0x223C, 0x9215, 0x20C9, 0x4987, 0xFFAA, 0x7850, 0x7AA5,
+		0x8F03, 0xF859, 0x8009, 0x171A, 0xDA65, 0x31D7, 0xC684, 0xB8D0,
+		0xC382, 0xB029, 0x775A, 0x111E, 0xCB7B, 0xFCA8, 0xD66D, 0x3A2C,
+	}
+};
+
+/*
+**********************************************************************
+* Routine: Phase 1 -- generate P1K, given TA, TK, IV32
+*
+* Inputs:
+*     tk[]      = temporal key                         [128 bits]
+*     ta[]      = transmitter's MAC address            [ 48 bits]
+*     iv32      = upper 32 bits of IV                  [ 32 bits]
+* Output:
+*     p1k[]     = Phase 1 key                          [ 80 bits]
+*
+* Note:
+*     This function only needs to be called every 2**16 packets,
+*     although in theory it could be called every packet.
+*
+**********************************************************************
+*/
+static void phase1(u16 *p1k, const u8 *tk, const u8 *ta, u32 iv32)
+{
+	sint  i;
+	/* Initialize the 80 bits of P1K[] from IV32 and TA[0..5]    */
+	p1k[0]      = Lo16(iv32);
+	p1k[1]      = Hi16(iv32);
+	p1k[2]      = Mk16(ta[1], ta[0]); /* use TA[] as little-endian */
+	p1k[3]      = Mk16(ta[3], ta[2]);
+	p1k[4]      = Mk16(ta[5], ta[4]);
+
+	/* Now compute an unbalanced Feistel cipher with 80-bit block */
+	/* size on the 80-bit block P1K[], using the 128-bit key TK[] */
+	for (i = 0; i < PHASE1_LOOP_CNT ; i++) {
+		/* Each add operation here is mod 2**16 */
+		p1k[0] += _S_(p1k[4] ^ TK16((i & 1) + 0));
+		p1k[1] += _S_(p1k[0] ^ TK16((i & 1) + 2));
+		p1k[2] += _S_(p1k[1] ^ TK16((i & 1) + 4));
+		p1k[3] += _S_(p1k[2] ^ TK16((i & 1) + 6));
+		p1k[4] += _S_(p1k[3] ^ TK16((i & 1) + 0));
+		p1k[4] += (unsigned short)i;                     /* avoid "slide attacks" */
+	}
+}
+
+
+/*
+**********************************************************************
+* Routine: Phase 2 -- generate RC4KEY, given TK, P1K, IV16
+*
+* Inputs:
+*     tk[]      = Temporal key                         [128 bits]
+*     p1k[]     = Phase 1 output key                   [ 80 bits]
+*     iv16      = low 16 bits of IV counter            [ 16 bits]
+* Output:
+*     rc4key[]  = the key used to encrypt the packet   [128 bits]
+*
+* Note:
+*     The value {TA,IV32,IV16} for Phase1/Phase2 must be unique
+*     across all packets using the same key TK value. Then, for a
+*     given value of TK[], this TKIP48 construction guarantees that
+*     the final RC4KEY value is unique across all packets.
+*
+* Suggested implementation optimization: if PPK[] is "overlaid"
+*     appropriately on RC4KEY[], there is no need for the final
+*     for loop below that copies the PPK[] result into RC4KEY[].
+*
+**********************************************************************
+*/
+static void phase2(u8 *rc4key, const u8 *tk, const u16 *p1k, u16 iv16)
+{
+	sint  i;
+	u16 PPK[6];                          /* temporary key for mixing   */
+	/* Note: all adds in the PPK[] equations below are mod 2**16        */
+	for (i = 0; i < 5; i++)
+		PPK[i] = p1k[i];    /* first, copy P1K to PPK     */
+	PPK[5]  =  p1k[4] + iv16;            /* next,  add in IV16         */
+
+	/* Bijective non-linear mixing of the 96 bits of PPK[0..5]          */
+	PPK[0] +=    _S_(PPK[5] ^ TK16(0));   /* Mix key in each "round"     */
+	PPK[1] +=    _S_(PPK[0] ^ TK16(1));
+	PPK[2] +=    _S_(PPK[1] ^ TK16(2));
+	PPK[3] +=    _S_(PPK[2] ^ TK16(3));
+	PPK[4] +=    _S_(PPK[3] ^ TK16(4));
+	PPK[5] +=    _S_(PPK[4] ^ TK16(5));   /* Total # S-box lookups == 6 */
+
+	/* Final sweep: bijective, "linear". Rotates kill LSB correlations   */
+	PPK[0] +=  RotR1(PPK[5] ^ TK16(6));
+	PPK[1] +=  RotR1(PPK[0] ^ TK16(7));   /* Use all of TK[] in Phase2  */
+	PPK[2] +=  RotR1(PPK[1]);
+	PPK[3] +=  RotR1(PPK[2]);
+	PPK[4] +=  RotR1(PPK[3]);
+	PPK[5] +=  RotR1(PPK[4]);
+	/* Note: At this point, for a given key TK[0..15], the 96-bit output */
+	/*       value PPK[0..5] is guaranteed to be unique, as a function  */
+	/*       of the 96-bit "input" value   {TA,IV32,IV16}. That is, P1K  */
+	/*       is now a keyed permutation of {TA,IV32,IV16}.              */
+
+	/* Set RC4KEY[0..3], which includes "cleartext" portion of RC4 key   */
+	rc4key[0] = Hi8(iv16);                /* RC4KEY[0..2] is the WEP IV */
+	rc4key[1] = (Hi8(iv16) | 0x20) & 0x7F; /* Help avoid weak (FMS) keys */
+	rc4key[2] = Lo8(iv16);
+	rc4key[3] = Lo8((PPK[5] ^ TK16(0)) >> 1);
+
+
+	/* Copy 96 bits of PPK[0..5] to RC4KEY[4..15]  (little-endian)      */
+	for (i = 0; i < 6; i++) {
+		rc4key[4 + 2 * i] = Lo8(PPK[i]);
+		rc4key[5 + 2 * i] = Hi8(PPK[i]);
+	}
+}
+
+
+/* The hlen isn't include the IV */
+u32	rtw_tkip_encrypt(_adapter *padapter, u8 *pxmitframe)
+{
+	/* exclude ICV */
+	u16	pnl;
+	u32	pnh;
+	u8	rc4key[16];
+	u8   ttkey[16];
+	u8	crc[4];
+	u8   hw_hdr_offset = 0;
+	struct arc4context mycontext;
+	sint			curfragnum, length;
+	u32	prwskeylen;
+
+	u8	*pframe, *payload, *iv, *prwskey;
+	union pn48 dot11txpn;
+	/* struct	sta_info		*stainfo; */
+	struct	pkt_attrib	*pattrib = &((struct xmit_frame *)pxmitframe)->attrib;
+	struct	security_priv	*psecuritypriv = &padapter->securitypriv;
+	struct	xmit_priv		*pxmitpriv = &padapter->xmitpriv;
+	u32	res = _SUCCESS;
+
+	if (((struct xmit_frame *)pxmitframe)->buf_addr == NULL)
+		return _FAIL;
+
+#ifdef CONFIG_USB_TX_AGGREGATION
+	hw_hdr_offset = TXDESC_SIZE +
+		(((struct xmit_frame *)pxmitframe)->pkt_offset * PACKET_OFFSET_SZ);
+#else
+#ifdef CONFIG_TX_EARLY_MODE
+	hw_hdr_offset = TXDESC_OFFSET + EARLY_MODE_INFO_SIZE;
+#else
+	hw_hdr_offset = TXDESC_OFFSET;
+#endif
+#endif
+
+	pframe = ((struct xmit_frame *)pxmitframe)->buf_addr + hw_hdr_offset;
+	/* 4 start to encrypt each fragment */
+	if (pattrib->encrypt == _TKIP_) {
+
+		/*
+				if(pattrib->psta)
+				{
+					stainfo = pattrib->psta;
+				}
+				else
+				{
+					RTW_INFO("%s, call rtw_get_stainfo()\n", __func__);
+					stainfo=rtw_get_stainfo(&padapter->stapriv ,&pattrib->ra[0] );
+				}
+		*/
+		/* if (stainfo!=NULL) */
+		{
+			/*
+						if(!(stainfo->state &_FW_LINKED))
+						{
+							RTW_INFO("%s, psta->state(0x%x) != _FW_LINKED\n", __func__, stainfo->state);
+							return _FAIL;
+						}
+			*/
+
+			if (IS_MCAST(pattrib->ra))
+				prwskey = psecuritypriv->dot118021XGrpKey[psecuritypriv->dot118021XGrpKeyid].skey;
+			else {
+				/* prwskey=&stainfo->dot118021x_UncstKey.skey[0]; */
+				prwskey = pattrib->dot118021x_UncstKey.skey;
+			}
+
+			prwskeylen = 16;
+
+			for (curfragnum = 0; curfragnum < pattrib->nr_frags; curfragnum++) {
+				iv = pframe + pattrib->hdrlen;
+				payload = pframe + pattrib->iv_len + pattrib->hdrlen;
+
+				GET_TKIP_PN(iv, dot11txpn);
+
+				pnl = (u16)(dot11txpn.val);
+				pnh = (u32)(dot11txpn.val >> 16);
+
+				phase1((u16 *)&ttkey[0], prwskey, &pattrib->ta[0], pnh);
+
+				phase2(&rc4key[0], prwskey, (u16 *)&ttkey[0], pnl);
+
+				if ((curfragnum + 1) == pattrib->nr_frags) {	/* 4 the last fragment */
+					length = pattrib->last_txcmdsz - pattrib->hdrlen - pattrib->iv_len - pattrib->icv_len;
+					*((u32 *)crc) = cpu_to_le32(getcrc32(payload, length)); /* modified by Amy*/
+
+					arcfour_init(&mycontext, rc4key, 16);
+					arcfour_encrypt(&mycontext, payload, payload, length);
+					arcfour_encrypt(&mycontext, payload + length, crc, 4);
+
+				} else {
+					length = pxmitpriv->frag_len - pattrib->hdrlen - pattrib->iv_len - pattrib->icv_len ;
+					*((u32 *)crc) = cpu_to_le32(getcrc32(payload, length)); /* modified by Amy*/
+					arcfour_init(&mycontext, rc4key, 16);
+					arcfour_encrypt(&mycontext, payload, payload, length);
+					arcfour_encrypt(&mycontext, payload + length, crc, 4);
+
+					pframe += pxmitpriv->frag_len;
+					pframe = (u8 *)RND4((SIZE_PTR)(pframe));
+
+				}
+			}
+
+			TKIP_SW_ENC_CNT_INC(psecuritypriv, pattrib->ra);
+		}
+		/*
+				else{
+					RTW_INFO("%s, psta==NUL\n", __func__);
+					res=_FAIL;
+				}
+		*/
+
+	}
+	return res;
+
+}
+
+
+/* The hlen isn't include the IV */
+u32 rtw_tkip_decrypt(_adapter *padapter, u8 *precvframe)
+{
+	/* exclude ICV */
+	u16 pnl;
+	u32 pnh;
+	u8   rc4key[16];
+	u8   ttkey[16];
+	u8	crc[4];
+	struct arc4context mycontext;
+	sint			length;
+	u32	prwskeylen;
+
+	u8	*pframe, *payload, *iv, *prwskey;
+	union pn48 dot11txpn;
+	struct	sta_info		*stainfo;
+	struct	rx_pkt_attrib	*prxattrib = &((union recv_frame *)precvframe)->u.hdr.attrib;
+	struct	security_priv	*psecuritypriv = &padapter->securitypriv;
+	/*	struct	recv_priv		*precvpriv=&padapter->recvpriv; */
+	u32		res = _SUCCESS;
+
+
+	pframe = (unsigned char *)((union recv_frame *)precvframe)->u.hdr.rx_data;
+
+	/* 4 start to decrypt recvframe */
+	if (prxattrib->encrypt == _TKIP_) {
+
+		stainfo = rtw_get_stainfo(&padapter->stapriv , &prxattrib->ta[0]);
+		if (stainfo != NULL) {
+
+			if (IS_MCAST(prxattrib->ra)) {
+				static systime start = 0;
+				static u32 no_gkey_bc_cnt = 0;
+				static u32 no_gkey_mc_cnt = 0;
+
+				if (psecuritypriv->binstallGrpkey == _FALSE) {
+					res = _FAIL;
+
+					if (start == 0)
+						start = rtw_get_current_time();
+
+					if (is_broadcast_mac_addr(prxattrib->ra))
+						no_gkey_bc_cnt++;
+					else
+						no_gkey_mc_cnt++;
+
+					if (rtw_get_passing_time_ms(start) > 1000) {
+						if (no_gkey_bc_cnt || no_gkey_mc_cnt) {
+							RTW_PRINT(FUNC_ADPT_FMT" no_gkey_bc_cnt:%u, no_gkey_mc_cnt:%u\n",
+								FUNC_ADPT_ARG(padapter), no_gkey_bc_cnt, no_gkey_mc_cnt);
+						}
+						start = rtw_get_current_time();
+						no_gkey_bc_cnt = 0;
+						no_gkey_mc_cnt = 0;
+					}
+					goto exit;
+				}
+
+				if (no_gkey_bc_cnt || no_gkey_mc_cnt) {
+					RTW_PRINT(FUNC_ADPT_FMT" gkey installed. no_gkey_bc_cnt:%u, no_gkey_mc_cnt:%u\n",
+						FUNC_ADPT_ARG(padapter), no_gkey_bc_cnt, no_gkey_mc_cnt);
+				}
+				start = 0;
+				no_gkey_bc_cnt = 0;
+				no_gkey_mc_cnt = 0;
+
+				/* RTW_INFO("rx bc/mc packets, to perform sw rtw_tkip_decrypt\n"); */
+				/* prwskey = psecuritypriv->dot118021XGrpKey[psecuritypriv->dot118021XGrpKeyid].skey; */
+				prwskey = psecuritypriv->dot118021XGrpKey[prxattrib->key_index].skey;
+				prwskeylen = 16;
+			} else {
+				prwskey = &stainfo->dot118021x_UncstKey.skey[0];
+				prwskeylen = 16;
+			}
+
+			iv = pframe + prxattrib->hdrlen;
+			payload = pframe + prxattrib->iv_len + prxattrib->hdrlen;
+			length = ((union recv_frame *)precvframe)->u.hdr.len - prxattrib->hdrlen - prxattrib->iv_len;
+
+			GET_TKIP_PN(iv, dot11txpn);
+
+			pnl = (u16)(dot11txpn.val);
+			pnh = (u32)(dot11txpn.val >> 16);
+
+			phase1((u16 *)&ttkey[0], prwskey, &prxattrib->ta[0], pnh);
+			phase2(&rc4key[0], prwskey, (unsigned short *)&ttkey[0], pnl);
+
+			/* 4 decrypt payload include icv */
+
+			arcfour_init(&mycontext, rc4key, 16);
+			arcfour_encrypt(&mycontext, payload, payload, length);
+
+			*((u32 *)crc) = le32_to_cpu(getcrc32(payload, length - 4));
+
+			if (crc[3] != payload[length - 1] || crc[2] != payload[length - 2] || crc[1] != payload[length - 3] || crc[0] != payload[length - 4]) {
+				res = _FAIL;
+			}
+
+			TKIP_SW_DEC_CNT_INC(psecuritypriv, prxattrib->ra);
+		} else {
+			res = _FAIL;
+		}
+
+	}
+exit:
+	return res;
+
+}
+
+
+/* 3			=====AES related===== */
+
+
+
+#define MAX_MSG_SIZE	2048
+/*****************************/
+/******** SBOX Table *********/
+/*****************************/
+
+static  u8 sbox_table[256] = {
+	0x63, 0x7c, 0x77, 0x7b, 0xf2, 0x6b, 0x6f, 0xc5,
+	0x30, 0x01, 0x67, 0x2b, 0xfe, 0xd7, 0xab, 0x76,
+	0xca, 0x82, 0xc9, 0x7d, 0xfa, 0x59, 0x47, 0xf0,
+	0xad, 0xd4, 0xa2, 0xaf, 0x9c, 0xa4, 0x72, 0xc0,
+	0xb7, 0xfd, 0x93, 0x26, 0x36, 0x3f, 0xf7, 0xcc,
+	0x34, 0xa5, 0xe5, 0xf1, 0x71, 0xd8, 0x31, 0x15,
+	0x04, 0xc7, 0x23, 0xc3, 0x18, 0x96, 0x05, 0x9a,
+	0x07, 0x12, 0x80, 0xe2, 0xeb, 0x27, 0xb2, 0x75,
+	0x09, 0x83, 0x2c, 0x1a, 0x1b, 0x6e, 0x5a, 0xa0,
+	0x52, 0x3b, 0xd6, 0xb3, 0x29, 0xe3, 0x2f, 0x84,
+	0x53, 0xd1, 0x00, 0xed, 0x20, 0xfc, 0xb1, 0x5b,
+	0x6a, 0xcb, 0xbe, 0x39, 0x4a, 0x4c, 0x58, 0xcf,
+	0xd0, 0xef, 0xaa, 0xfb, 0x43, 0x4d, 0x33, 0x85,
+	0x45, 0xf9, 0x02, 0x7f, 0x50, 0x3c, 0x9f, 0xa8,
+	0x51, 0xa3, 0x40, 0x8f, 0x92, 0x9d, 0x38, 0xf5,
+	0xbc, 0xb6, 0xda, 0x21, 0x10, 0xff, 0xf3, 0xd2,
+	0xcd, 0x0c, 0x13, 0xec, 0x5f, 0x97, 0x44, 0x17,
+	0xc4, 0xa7, 0x7e, 0x3d, 0x64, 0x5d, 0x19, 0x73,
+	0x60, 0x81, 0x4f, 0xdc, 0x22, 0x2a, 0x90, 0x88,
+	0x46, 0xee, 0xb8, 0x14, 0xde, 0x5e, 0x0b, 0xdb,
+	0xe0, 0x32, 0x3a, 0x0a, 0x49, 0x06, 0x24, 0x5c,
+	0xc2, 0xd3, 0xac, 0x62, 0x91, 0x95, 0xe4, 0x79,
+	0xe7, 0xc8, 0x37, 0x6d, 0x8d, 0xd5, 0x4e, 0xa9,
+	0x6c, 0x56, 0xf4, 0xea, 0x65, 0x7a, 0xae, 0x08,
+	0xba, 0x78, 0x25, 0x2e, 0x1c, 0xa6, 0xb4, 0xc6,
+	0xe8, 0xdd, 0x74, 0x1f, 0x4b, 0xbd, 0x8b, 0x8a,
+	0x70, 0x3e, 0xb5, 0x66, 0x48, 0x03, 0xf6, 0x0e,
+	0x61, 0x35, 0x57, 0xb9, 0x86, 0xc1, 0x1d, 0x9e,
+	0xe1, 0xf8, 0x98, 0x11, 0x69, 0xd9, 0x8e, 0x94,
+	0x9b, 0x1e, 0x87, 0xe9, 0xce, 0x55, 0x28, 0xdf,
+	0x8c, 0xa1, 0x89, 0x0d, 0xbf, 0xe6, 0x42, 0x68,
+	0x41, 0x99, 0x2d, 0x0f, 0xb0, 0x54, 0xbb, 0x16
+};
+
+/*****************************/
+/**** Function Prototypes ****/
+/*****************************/
+
+static void bitwise_xor(u8 *ina, u8 *inb, u8 *out);
+static void construct_mic_iv(
+	u8 *mic_header1,
+	sint qc_exists,
+	sint a4_exists,
+	u8 *mpdu,
+	uint payload_length,
+	u8 *pn_vector,
+	uint frtype);/* add for CONFIG_IEEE80211W, none 11w also can use */
+static void construct_mic_header1(
+	u8 *mic_header1,
+	sint header_length,
+	u8 *mpdu,
+	uint frtype);/* add for CONFIG_IEEE80211W, none 11w also can use */
+static void construct_mic_header2(
+	u8 *mic_header2,
+	u8 *mpdu,
+	sint a4_exists,
+	sint qc_exists);
+static void construct_ctr_preload(
+	u8 *ctr_preload,
+	sint a4_exists,
+	sint qc_exists,
+	u8 *mpdu,
+	u8 *pn_vector,
+	sint c,
+	uint frtype);/* add for CONFIG_IEEE80211W, none 11w also can use */
+static void xor_128(u8 *a, u8 *b, u8 *out);
+static void xor_32(u8 *a, u8 *b, u8 *out);
+static u8 sbox(u8 a);
+static void next_key(u8 *key, sint round);
+static void byte_sub(u8 *in, u8 *out);
+static void shift_row(u8 *in, u8 *out);
+static void mix_column(u8 *in, u8 *out);
+static void aes128k128d(u8 *key, u8 *data, u8 *ciphertext);
+
+
+/****************************************/
+/* aes128k128d()                       */
+/* Performs a 128 bit AES encrypt with */
+/* 128 bit data.                       */
+/****************************************/
+static void xor_128(u8 *a, u8 *b, u8 *out)
+{
+	sint i;
+	for (i = 0; i < 16; i++)
+		out[i] = a[i] ^ b[i];
+}
+
+
+static void xor_32(u8 *a, u8 *b, u8 *out)
+{
+	sint i;
+	for (i = 0; i < 4; i++)
+		out[i] = a[i] ^ b[i];
+}
+
+
+static u8 sbox(u8 a)
+{
+	return sbox_table[(sint)a];
+}
+
+
+static void next_key(u8 *key, sint round)
+{
+	u8 rcon;
+	u8 sbox_key[4];
+	u8 rcon_table[12] = {
+		0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80,
+		0x1b, 0x36, 0x36, 0x36
+	};
+	sbox_key[0] = sbox(key[13]);
+	sbox_key[1] = sbox(key[14]);
+	sbox_key[2] = sbox(key[15]);
+	sbox_key[3] = sbox(key[12]);
+
+	rcon = rcon_table[round];
+
+	xor_32(&key[0], sbox_key, &key[0]);
+	key[0] = key[0] ^ rcon;
+
+	xor_32(&key[4], &key[0], &key[4]);
+	xor_32(&key[8], &key[4], &key[8]);
+	xor_32(&key[12], &key[8], &key[12]);
+}
+
+
+static void byte_sub(u8 *in, u8 *out)
+{
+	sint i;
+	for (i = 0; i < 16; i++)
+		out[i] = sbox(in[i]);
+}
+
+
+static void shift_row(u8 *in, u8 *out)
+{
+	out[0] =  in[0];
+	out[1] =  in[5];
+	out[2] =  in[10];
+	out[3] =  in[15];
+	out[4] =  in[4];
+	out[5] =  in[9];
+	out[6] =  in[14];
+	out[7] =  in[3];
+	out[8] =  in[8];
+	out[9] =  in[13];
+	out[10] = in[2];
+	out[11] = in[7];
+	out[12] = in[12];
+	out[13] = in[1];
+	out[14] = in[6];
+	out[15] = in[11];
+}
+
+
+static void mix_column(u8 *in, u8 *out)
+{
+	sint i;
+	u8 add1b[4];
+	u8 add1bf7[4];
+	u8 rotl[4];
+	u8 swap_halfs[4];
+	u8 andf7[4];
+	u8 rotr[4];
+	u8 temp[4];
+	u8 tempb[4];
+	for (i = 0 ; i < 4; i++) {
+		if ((in[i] & 0x80) == 0x80)
+			add1b[i] = 0x1b;
+		else
+			add1b[i] = 0x00;
+	}
+
+	swap_halfs[0] = in[2];    /* Swap halfs */
+	swap_halfs[1] = in[3];
+	swap_halfs[2] = in[0];
+	swap_halfs[3] = in[1];
+
+	rotl[0] = in[3];        /* Rotate left 8 bits */
+	rotl[1] = in[0];
+	rotl[2] = in[1];
+	rotl[3] = in[2];
+
+	andf7[0] = in[0] & 0x7f;
+	andf7[1] = in[1] & 0x7f;
+	andf7[2] = in[2] & 0x7f;
+	andf7[3] = in[3] & 0x7f;
+
+	for (i = 3; i > 0; i--) { /* logical shift left 1 bit */
+		andf7[i] = andf7[i] << 1;
+		if ((andf7[i - 1] & 0x80) == 0x80)
+			andf7[i] = (andf7[i] | 0x01);
+	}
+	andf7[0] = andf7[0] << 1;
+	andf7[0] = andf7[0] & 0xfe;
+
+	xor_32(add1b, andf7, add1bf7);
+
+	xor_32(in, add1bf7, rotr);
+
+	temp[0] = rotr[0];         /* Rotate right 8 bits */
+	rotr[0] = rotr[1];
+	rotr[1] = rotr[2];
+	rotr[2] = rotr[3];
+	rotr[3] = temp[0];
+
+	xor_32(add1bf7, rotr, temp);
+	xor_32(swap_halfs, rotl, tempb);
+	xor_32(temp, tempb, out);
+}
+
+
+static void aes128k128d(u8 *key, u8 *data, u8 *ciphertext)
+{
+	sint round;
+	sint i;
+	u8 intermediatea[16];
+	u8 intermediateb[16];
+	u8 round_key[16];
+	for (i = 0; i < 16; i++)
+		round_key[i] = key[i];
+
+	for (round = 0; round < 11; round++) {
+		if (round == 0) {
+			xor_128(round_key, data, ciphertext);
+			next_key(round_key, round);
+		} else if (round == 10) {
+			byte_sub(ciphertext, intermediatea);
+			shift_row(intermediatea, intermediateb);
+			xor_128(intermediateb, round_key, ciphertext);
+		} else { /* 1 - 9 */
+			byte_sub(ciphertext, intermediatea);
+			shift_row(intermediatea, intermediateb);
+			mix_column(&intermediateb[0], &intermediatea[0]);
+			mix_column(&intermediateb[4], &intermediatea[4]);
+			mix_column(&intermediateb[8], &intermediatea[8]);
+			mix_column(&intermediateb[12], &intermediatea[12]);
+			xor_128(intermediatea, round_key, ciphertext);
+			next_key(round_key, round);
+		}
+	}
+}
+
+
+/************************************************/
+/* construct_mic_iv()                          */
+/* Builds the MIC IV from header fields and PN */
+/* Baron think the function is construct CCM   */
+/* nonce                                       */
+/************************************************/
+static void construct_mic_iv(
+	u8 *mic_iv,
+	sint qc_exists,
+	sint a4_exists,
+	u8 *mpdu,
+	uint payload_length,
+	u8 *pn_vector,
+	uint frtype/* add for CONFIG_IEEE80211W, none 11w also can use */
+)
+{
+	sint i;
+	mic_iv[0] = 0x59;
+	if (qc_exists && a4_exists)
+		mic_iv[1] = mpdu[30] & 0x0f;    /* QoS_TC          */
+	if (qc_exists && !a4_exists)
+		mic_iv[1] = mpdu[24] & 0x0f;   /* mute bits 7-4   */
+	if (!qc_exists)
+		mic_iv[1] = 0x00;
+#if defined(CONFIG_IEEE80211W) || defined(CONFIG_RTW_MESH)
+	/* 802.11w management frame should set management bit(4) */
+	if (frtype == WIFI_MGT_TYPE)
+		mic_iv[1] |= BIT(4);
+#endif
+	for (i = 2; i < 8; i++)
+		mic_iv[i] = mpdu[i + 8];                    /* mic_iv[2:7] = A2[0:5] = mpdu[10:15] */
+#ifdef CONSISTENT_PN_ORDER
+	for (i = 8; i < 14; i++)
+		mic_iv[i] = pn_vector[i - 8];           /* mic_iv[8:13] = PN[0:5] */
+#else
+	for (i = 8; i < 14; i++)
+		mic_iv[i] = pn_vector[13 - i];          /* mic_iv[8:13] = PN[5:0] */
+#endif
+	mic_iv[14] = (unsigned char)(payload_length / 256);
+	mic_iv[15] = (unsigned char)(payload_length % 256);
+}
+
+
+/************************************************/
+/* construct_mic_header1()                     */
+/* Builds the first MIC header block from      */
+/* header fields.                              */
+/* Build AAD SC,A1,A2                          */
+/************************************************/
+static void construct_mic_header1(
+	u8 *mic_header1,
+	sint header_length,
+	u8 *mpdu,
+	uint frtype/* add for CONFIG_IEEE80211W, none 11w also can use */
+)
+{
+	mic_header1[0] = (u8)((header_length - 2) / 256);
+	mic_header1[1] = (u8)((header_length - 2) % 256);
+#if defined(CONFIG_IEEE80211W) || defined(CONFIG_RTW_MESH)
+	/* 802.11w management frame don't AND subtype bits 4,5,6 of frame control field */
+	if (frtype == WIFI_MGT_TYPE)
+		mic_header1[2] = mpdu[0];
+	else
+#endif
+		mic_header1[2] = mpdu[0] & 0xcf;    /* Mute CF poll & CF ack bits */
+
+	mic_header1[3] = mpdu[1] & 0xc7;    /* Mute retry, more data and pwr mgt bits */
+	mic_header1[4] = mpdu[4];       /* A1 */
+	mic_header1[5] = mpdu[5];
+	mic_header1[6] = mpdu[6];
+	mic_header1[7] = mpdu[7];
+	mic_header1[8] = mpdu[8];
+	mic_header1[9] = mpdu[9];
+	mic_header1[10] = mpdu[10];     /* A2 */
+	mic_header1[11] = mpdu[11];
+	mic_header1[12] = mpdu[12];
+	mic_header1[13] = mpdu[13];
+	mic_header1[14] = mpdu[14];
+	mic_header1[15] = mpdu[15];
+}
+
+
+/************************************************/
+/* construct_mic_header2()                     */
+/* Builds the last MIC header block from       */
+/* header fields.                              */
+/************************************************/
+static void construct_mic_header2(
+	u8 *mic_header2,
+	u8 *mpdu,
+	sint a4_exists,
+	sint qc_exists
+)
+{
+	sint i;
+	for (i = 0; i < 16; i++)
+		mic_header2[i] = 0x00;
+
+	mic_header2[0] = mpdu[16];    /* A3 */
+	mic_header2[1] = mpdu[17];
+	mic_header2[2] = mpdu[18];
+	mic_header2[3] = mpdu[19];
+	mic_header2[4] = mpdu[20];
+	mic_header2[5] = mpdu[21];
+
+	/* mic_header2[6] = mpdu[22] & 0xf0;    SC */
+	mic_header2[6] = 0x00;
+	mic_header2[7] = 0x00; /* mpdu[23]; */
+
+
+	if (!qc_exists && a4_exists) {
+		for (i = 0; i < 6; i++)
+			mic_header2[8 + i] = mpdu[24 + i]; /* A4 */
+
+	}
+
+	if (qc_exists && !a4_exists) {
+		mic_header2[8] = mpdu[24] & 0x0f; /* mute bits 15 - 4 */
+		mic_header2[9] = mpdu[25] & 0x00;
+	}
+
+	if (qc_exists && a4_exists) {
+		for (i = 0; i < 6; i++)
+			mic_header2[8 + i] = mpdu[24 + i]; /* A4 */
+
+		mic_header2[14] = mpdu[30] & 0x0f;
+		mic_header2[15] = mpdu[31] & 0x00;
+	}
+
+}
+
+
+/************************************************/
+/* construct_mic_header2()                     */
+/* Builds the last MIC header block from       */
+/* header fields.                              */
+/* Baron think the function is construct CCM   */
+/* nonce                                       */
+/************************************************/
+static void construct_ctr_preload(
+	u8 *ctr_preload,
+	sint a4_exists,
+	sint qc_exists,
+	u8 *mpdu,
+	u8 *pn_vector,
+	sint c,
+	uint frtype /* add for CONFIG_IEEE80211W, none 11w also can use */
+)
+{
+	sint i = 0;
+	for (i = 0; i < 16; i++)
+		ctr_preload[i] = 0x00;
+	i = 0;
+
+	ctr_preload[0] = 0x01;                                  /* flag */
+	if (qc_exists && a4_exists)
+		ctr_preload[1] = mpdu[30] & 0x0f;   /* QoC_Control */
+	if (qc_exists && !a4_exists)
+		ctr_preload[1] = mpdu[24] & 0x0f;
+#if defined(CONFIG_IEEE80211W) || defined(CONFIG_RTW_MESH)
+	/* 802.11w management frame should set management bit(4) */
+	if (frtype == WIFI_MGT_TYPE)
+		ctr_preload[1] |= BIT(4);
+#endif
+	for (i = 2; i < 8; i++)
+		ctr_preload[i] = mpdu[i + 8];                       /* ctr_preload[2:7] = A2[0:5] = mpdu[10:15] */
+#ifdef CONSISTENT_PN_ORDER
+	for (i = 8; i < 14; i++)
+		ctr_preload[i] =    pn_vector[i - 8];           /* ctr_preload[8:13] = PN[0:5] */
+#else
+	for (i = 8; i < 14; i++)
+		ctr_preload[i] =    pn_vector[13 - i];          /* ctr_preload[8:13] = PN[5:0] */
+#endif
+	ctr_preload[14] = (unsigned char)(c / 256);   /* Ctr */
+	ctr_preload[15] = (unsigned char)(c % 256);
+}
+
+
+/************************************/
+/* bitwise_xor()                   */
+/* A 128 bit, bitwise exclusive or */
+/************************************/
+static void bitwise_xor(u8 *ina, u8 *inb, u8 *out)
+{
+	sint i;
+	for (i = 0; i < 16; i++)
+		out[i] = ina[i] ^ inb[i];
+}
+
+
+static sint aes_cipher(u8 *key, uint	hdrlen,
+		       u8 *pframe, uint plen)
+{
+	/*	static unsigned char	message[MAX_MSG_SIZE]; */
+	uint	qc_exists, a4_exists, i, j, payload_remainder,
+		num_blocks, payload_index;
+
+	u8 pn_vector[6];
+	u8 mic_iv[16];
+	u8 mic_header1[16];
+	u8 mic_header2[16];
+	u8 ctr_preload[16];
+
+	/* Intermediate Buffers */
+	u8 chain_buffer[16];
+	u8 aes_out[16];
+	u8 padded_buffer[16];
+	u8 mic[8];
+	/*	uint	offset = 0; */
+	uint	frtype  = GetFrameType(pframe);
+	uint	frsubtype  = get_frame_sub_type(pframe);
+
+	frsubtype = frsubtype >> 4;
+
+
+	_rtw_memset((void *)mic_iv, 0, 16);
+	_rtw_memset((void *)mic_header1, 0, 16);
+	_rtw_memset((void *)mic_header2, 0, 16);
+	_rtw_memset((void *)ctr_preload, 0, 16);
+	_rtw_memset((void *)chain_buffer, 0, 16);
+	_rtw_memset((void *)aes_out, 0, 16);
+	_rtw_memset((void *)padded_buffer, 0, 16);
+
+	if ((hdrlen == WLAN_HDR_A3_LEN) || (hdrlen ==  WLAN_HDR_A3_QOS_LEN))
+		a4_exists = 0;
+	else
+		a4_exists = 1;
+
+	if (
+		((frtype | frsubtype) == WIFI_DATA_CFACK) ||
+		((frtype | frsubtype) == WIFI_DATA_CFPOLL) ||
+		((frtype | frsubtype) == WIFI_DATA_CFACKPOLL)) {
+		qc_exists = 1;
+		if (hdrlen != WLAN_HDR_A3_QOS_LEN && hdrlen != WLAN_HDR_A4_QOS_LEN)
+			hdrlen += 2;
+	}
+	/* add for CONFIG_IEEE80211W, none 11w also can use */
+	else if ((frtype == WIFI_DATA) &&
+		 ((frsubtype == 0x08) ||
+		  (frsubtype == 0x09) ||
+		  (frsubtype == 0x0a) ||
+		  (frsubtype == 0x0b))) {
+		if (hdrlen != WLAN_HDR_A3_QOS_LEN && hdrlen != WLAN_HDR_A4_QOS_LEN)
+			hdrlen += 2;
+		qc_exists = 1;
+	} else
+		qc_exists = 0;
+
+	pn_vector[0] = pframe[hdrlen];
+	pn_vector[1] = pframe[hdrlen + 1];
+	pn_vector[2] = pframe[hdrlen + 4];
+	pn_vector[3] = pframe[hdrlen + 5];
+	pn_vector[4] = pframe[hdrlen + 6];
+	pn_vector[5] = pframe[hdrlen + 7];
+
+	construct_mic_iv(
+		mic_iv,
+		qc_exists,
+		a4_exists,
+		pframe,	 /* message, */
+		plen,
+		pn_vector,
+		frtype /* add for CONFIG_IEEE80211W, none 11w also can use */
+	);
+
+	construct_mic_header1(
+		mic_header1,
+		hdrlen,
+		pframe,	/* message */
+		frtype /* add for CONFIG_IEEE80211W, none 11w also can use */
+	);
+	construct_mic_header2(
+		mic_header2,
+		pframe,	/* message, */
+		a4_exists,
+		qc_exists
+	);
+
+
+	payload_remainder = plen % 16;
+	num_blocks = plen / 16;
+
+	/* Find start of payload */
+	payload_index = (hdrlen + 8);
+
+	/* Calculate MIC */
+	aes128k128d(key, mic_iv, aes_out);
+	bitwise_xor(aes_out, mic_header1, chain_buffer);
+	aes128k128d(key, chain_buffer, aes_out);
+	bitwise_xor(aes_out, mic_header2, chain_buffer);
+	aes128k128d(key, chain_buffer, aes_out);
+
+	for (i = 0; i < num_blocks; i++) {
+		bitwise_xor(aes_out, &pframe[payload_index], chain_buffer);/* bitwise_xor(aes_out, &message[payload_index], chain_buffer); */
+
+		payload_index += 16;
+		aes128k128d(key, chain_buffer, aes_out);
+	}
+
+	/* Add on the final payload block if it needs padding */
+	if (payload_remainder > 0) {
+		for (j = 0; j < 16; j++)
+			padded_buffer[j] = 0x00;
+		for (j = 0; j < payload_remainder; j++) {
+			padded_buffer[j] = pframe[payload_index++];/* padded_buffer[j] = message[payload_index++]; */
+		}
+		bitwise_xor(aes_out, padded_buffer, chain_buffer);
+		aes128k128d(key, chain_buffer, aes_out);
+
+	}
+
+	for (j = 0 ; j < 8; j++)
+		mic[j] = aes_out[j];
+
+	/* Insert MIC into payload */
+	for (j = 0; j < 8; j++)
+		pframe[payload_index + j] = mic[j];	/* message[payload_index+j] = mic[j]; */
+
+	payload_index = hdrlen + 8;
+	for (i = 0; i < num_blocks; i++) {
+		construct_ctr_preload(
+			ctr_preload,
+			a4_exists,
+			qc_exists,
+			pframe,	/* message, */
+			pn_vector,
+			i + 1,
+			frtype); /* add for CONFIG_IEEE80211W, none 11w also can use */
+		aes128k128d(key, ctr_preload, aes_out);
+		bitwise_xor(aes_out, &pframe[payload_index], chain_buffer);/* bitwise_xor(aes_out, &message[payload_index], chain_buffer); */
+		for (j = 0; j < 16; j++)
+			pframe[payload_index++] = chain_buffer[j];/* for (j=0; j<16;j++) message[payload_index++] = chain_buffer[j]; */
+	}
+
+	if (payload_remainder > 0) {        /* If there is a short final block, then pad it,*/
+		/* encrypt it and copy the unpadded part back  */
+		construct_ctr_preload(
+			ctr_preload,
+			a4_exists,
+			qc_exists,
+			pframe,	/* message, */
+			pn_vector,
+			num_blocks + 1,
+			frtype); /* add for CONFIG_IEEE80211W, none 11w also can use */
+
+		for (j = 0; j < 16; j++)
+			padded_buffer[j] = 0x00;
+		for (j = 0; j < payload_remainder; j++) {
+			padded_buffer[j] = pframe[payload_index + j]; /* padded_buffer[j] = message[payload_index+j]; */
+		}
+		aes128k128d(key, ctr_preload, aes_out);
+		bitwise_xor(aes_out, padded_buffer, chain_buffer);
+		for (j = 0; j < payload_remainder; j++)
+			pframe[payload_index++] = chain_buffer[j];/* for (j=0; j<payload_remainder;j++) message[payload_index++] = chain_buffer[j]; */
+	}
+
+	/* Encrypt the MIC */
+	construct_ctr_preload(
+		ctr_preload,
+		a4_exists,
+		qc_exists,
+		pframe,	/* message, */
+		pn_vector,
+		0,
+		frtype); /* add for CONFIG_IEEE80211W, none 11w also can use */
+
+	for (j = 0; j < 16; j++)
+		padded_buffer[j] = 0x00;
+	for (j = 0; j < 8; j++) {
+		padded_buffer[j] = pframe[j + hdrlen + 8 + plen]; /* padded_buffer[j] = message[j+hdrlen+8+plen]; */
+	}
+
+	aes128k128d(key, ctr_preload, aes_out);
+	bitwise_xor(aes_out, padded_buffer, chain_buffer);
+	for (j = 0; j < 8; j++)
+		pframe[payload_index++] = chain_buffer[j];/* for (j=0; j<8;j++) message[payload_index++] = chain_buffer[j]; */
+	return _SUCCESS;
+}
+
+
+
+
+
+u32	rtw_aes_encrypt(_adapter *padapter, u8 *pxmitframe)
+{
+	/* exclude ICV */
+
+
+	/*static*/
+	/*	unsigned char	message[MAX_MSG_SIZE]; */
+
+	/* Intermediate Buffers */
+	sint	curfragnum, length;
+	u32	prwskeylen;
+	u8	*pframe, *prwskey;	/* , *payload,*iv */
+	u8   hw_hdr_offset = 0;
+	/* struct	sta_info		*stainfo=NULL; */
+	struct	pkt_attrib	*pattrib = &((struct xmit_frame *)pxmitframe)->attrib;
+	struct	security_priv	*psecuritypriv = &padapter->securitypriv;
+	struct	xmit_priv		*pxmitpriv = &padapter->xmitpriv;
+
+	/*	uint	offset = 0; */
+	u32 res = _SUCCESS;
+
+	if (((struct xmit_frame *)pxmitframe)->buf_addr == NULL)
+		return _FAIL;
+
+#ifdef CONFIG_USB_TX_AGGREGATION
+	hw_hdr_offset = TXDESC_SIZE +
+		(((struct xmit_frame *)pxmitframe)->pkt_offset * PACKET_OFFSET_SZ);
+#else
+#ifdef CONFIG_TX_EARLY_MODE
+	hw_hdr_offset = TXDESC_OFFSET + EARLY_MODE_INFO_SIZE;
+#else
+	hw_hdr_offset = TXDESC_OFFSET;
+#endif
+#endif
+
+	pframe = ((struct xmit_frame *)pxmitframe)->buf_addr + hw_hdr_offset;
+
+	/* 4 start to encrypt each fragment */
+	if ((pattrib->encrypt == _AES_)) {
+		/*
+				if(pattrib->psta)
+				{
+					stainfo = pattrib->psta;
+				}
+				else
+				{
+					RTW_INFO("%s, call rtw_get_stainfo()\n", __func__);
+					stainfo=rtw_get_stainfo(&padapter->stapriv ,&pattrib->ra[0] );
+				}
+		*/
+		/* if (stainfo!=NULL) */
+		{
+			/*
+						if(!(stainfo->state &_FW_LINKED))
+						{
+							RTW_INFO("%s, psta->state(0x%x) != _FW_LINKED\n", __func__, stainfo->state);
+							return _FAIL;
+						}
+			*/
+
+			if (IS_MCAST(pattrib->ra))
+				prwskey = psecuritypriv->dot118021XGrpKey[psecuritypriv->dot118021XGrpKeyid].skey;
+			else {
+				/* prwskey=&stainfo->dot118021x_UncstKey.skey[0]; */
+				prwskey = pattrib->dot118021x_UncstKey.skey;
+			}
+
+#ifdef CONFIG_TDLS
+			{
+				/* Swencryption */
+				struct	sta_info		*ptdls_sta;
+				ptdls_sta = rtw_get_stainfo(&padapter->stapriv , &pattrib->dst[0]);
+				if ((ptdls_sta != NULL) && (ptdls_sta->tdls_sta_state & TDLS_LINKED_STATE)) {
+					RTW_INFO("[%s] for tdls link\n", __FUNCTION__);
+					prwskey = &ptdls_sta->tpk.tk[0];
+				}
+			}
+#endif /* CONFIG_TDLS */
+
+			prwskeylen = 16;
+
+			for (curfragnum = 0; curfragnum < pattrib->nr_frags; curfragnum++) {
+
+				if ((curfragnum + 1) == pattrib->nr_frags) {	/* 4 the last fragment */
+					length = pattrib->last_txcmdsz - pattrib->hdrlen - pattrib->iv_len - pattrib->icv_len;
+
+					aes_cipher(prwskey, pattrib->hdrlen, pframe, length);
+				} else {
+					length = pxmitpriv->frag_len - pattrib->hdrlen - pattrib->iv_len - pattrib->icv_len ;
+
+					aes_cipher(prwskey, pattrib->hdrlen, pframe, length);
+					pframe += pxmitpriv->frag_len;
+					pframe = (u8 *)RND4((SIZE_PTR)(pframe));
+
+				}
+			}
+
+			AES_SW_ENC_CNT_INC(psecuritypriv, pattrib->ra);
+		}
+		/*
+				else{
+					RTW_INFO("%s, psta==NUL\n", __func__);
+					res=_FAIL;
+				}
+		*/
+	}
+
+
+
+	return res;
+}
+
+static sint aes_decipher(u8 *key, uint	hdrlen,
+			 u8 *pframe, uint plen)
+{
+	static u8	message[MAX_MSG_SIZE];
+	uint	qc_exists, a4_exists, i, j, payload_remainder,
+		num_blocks, payload_index;
+	sint res = _SUCCESS;
+	u8 pn_vector[6];
+	u8 mic_iv[16];
+	u8 mic_header1[16];
+	u8 mic_header2[16];
+	u8 ctr_preload[16];
+
+	/* Intermediate Buffers */
+	u8 chain_buffer[16];
+	u8 aes_out[16];
+	u8 padded_buffer[16];
+	u8 mic[8];
+
+
+	/*	uint	offset = 0; */
+	uint	frtype  = GetFrameType(pframe);
+	uint	frsubtype  = get_frame_sub_type(pframe);
+	frsubtype = frsubtype >> 4;
+
+
+	_rtw_memset((void *)mic_iv, 0, 16);
+	_rtw_memset((void *)mic_header1, 0, 16);
+	_rtw_memset((void *)mic_header2, 0, 16);
+	_rtw_memset((void *)ctr_preload, 0, 16);
+	_rtw_memset((void *)chain_buffer, 0, 16);
+	_rtw_memset((void *)aes_out, 0, 16);
+	_rtw_memset((void *)padded_buffer, 0, 16);
+
+	/* start to decrypt the payload */
+
+	num_blocks = (plen - 8) / 16; /* (plen including LLC, payload_length and mic ) */
+
+	payload_remainder = (plen - 8) % 16;
+
+	pn_vector[0]  = pframe[hdrlen];
+	pn_vector[1]  = pframe[hdrlen + 1];
+	pn_vector[2]  = pframe[hdrlen + 4];
+	pn_vector[3]  = pframe[hdrlen + 5];
+	pn_vector[4]  = pframe[hdrlen + 6];
+	pn_vector[5]  = pframe[hdrlen + 7];
+
+	if ((hdrlen == WLAN_HDR_A3_LEN) || (hdrlen ==  WLAN_HDR_A3_QOS_LEN))
+		a4_exists = 0;
+	else
+		a4_exists = 1;
+
+	if (
+		((frtype | frsubtype) == WIFI_DATA_CFACK) ||
+		((frtype | frsubtype) == WIFI_DATA_CFPOLL) ||
+		((frtype | frsubtype) == WIFI_DATA_CFACKPOLL)) {
+		qc_exists = 1;
+		if (hdrlen != WLAN_HDR_A3_QOS_LEN && hdrlen != WLAN_HDR_A4_QOS_LEN)
+			hdrlen += 2;
+	} /* only for data packet . add for CONFIG_IEEE80211W, none 11w also can use */
+	else if ((frtype == WIFI_DATA) &&
+		 ((frsubtype == 0x08) ||
+		  (frsubtype == 0x09) ||
+		  (frsubtype == 0x0a) ||
+		  (frsubtype == 0x0b))) {
+		if (hdrlen != WLAN_HDR_A3_QOS_LEN && hdrlen != WLAN_HDR_A4_QOS_LEN)
+			hdrlen += 2;
+		qc_exists = 1;
+	} else
+		qc_exists = 0;
+
+
+	/* now, decrypt pframe with hdrlen offset and plen long */
+
+	payload_index = hdrlen + 8; /* 8 is for extiv */
+
+	for (i = 0; i < num_blocks; i++) {
+		construct_ctr_preload(
+			ctr_preload,
+			a4_exists,
+			qc_exists,
+			pframe,
+			pn_vector,
+			i + 1,
+			frtype /* add for CONFIG_IEEE80211W, none 11w also can use */
+		);
+
+		aes128k128d(key, ctr_preload, aes_out);
+		bitwise_xor(aes_out, &pframe[payload_index], chain_buffer);
+
+		for (j = 0; j < 16; j++)
+			pframe[payload_index++] = chain_buffer[j];
+	}
+
+	if (payload_remainder > 0) {        /* If there is a short final block, then pad it,*/
+		/* encrypt it and copy the unpadded part back  */
+		construct_ctr_preload(
+			ctr_preload,
+			a4_exists,
+			qc_exists,
+			pframe,
+			pn_vector,
+			num_blocks + 1,
+			frtype /* add for CONFIG_IEEE80211W, none 11w also can use */
+		);
+
+		for (j = 0; j < 16; j++)
+			padded_buffer[j] = 0x00;
+		for (j = 0; j < payload_remainder; j++)
+			padded_buffer[j] = pframe[payload_index + j];
+		aes128k128d(key, ctr_preload, aes_out);
+		bitwise_xor(aes_out, padded_buffer, chain_buffer);
+		for (j = 0; j < payload_remainder; j++)
+			pframe[payload_index++] = chain_buffer[j];
+	}
+
+	/* start to calculate the mic	 */
+	if ((hdrlen + plen + 8) <= MAX_MSG_SIZE)
+		_rtw_memcpy((void *)message, pframe, (hdrlen + plen + 8)); /* 8 is for ext iv len */
+
+
+	pn_vector[0] = pframe[hdrlen];
+	pn_vector[1] = pframe[hdrlen + 1];
+	pn_vector[2] = pframe[hdrlen + 4];
+	pn_vector[3] = pframe[hdrlen + 5];
+	pn_vector[4] = pframe[hdrlen + 6];
+	pn_vector[5] = pframe[hdrlen + 7];
+
+
+
+	construct_mic_iv(
+		mic_iv,
+		qc_exists,
+		a4_exists,
+		message,
+		plen - 8,
+		pn_vector,
+		frtype /* add for CONFIG_IEEE80211W, none 11w also can use */
+	);
+
+	construct_mic_header1(
+		mic_header1,
+		hdrlen,
+		message,
+		frtype /* add for CONFIG_IEEE80211W, none 11w also can use */
+	);
+	construct_mic_header2(
+		mic_header2,
+		message,
+		a4_exists,
+		qc_exists
+	);
+
+
+	payload_remainder = (plen - 8) % 16;
+	num_blocks = (plen - 8) / 16;
+
+	/* Find start of payload */
+	payload_index = (hdrlen + 8);
+
+	/* Calculate MIC */
+	aes128k128d(key, mic_iv, aes_out);
+	bitwise_xor(aes_out, mic_header1, chain_buffer);
+	aes128k128d(key, chain_buffer, aes_out);
+	bitwise_xor(aes_out, mic_header2, chain_buffer);
+	aes128k128d(key, chain_buffer, aes_out);
+
+	for (i = 0; i < num_blocks; i++) {
+		bitwise_xor(aes_out, &message[payload_index], chain_buffer);
+
+		payload_index += 16;
+		aes128k128d(key, chain_buffer, aes_out);
+	}
+
+	/* Add on the final payload block if it needs padding */
+	if (payload_remainder > 0) {
+		for (j = 0; j < 16; j++)
+			padded_buffer[j] = 0x00;
+		for (j = 0; j < payload_remainder; j++)
+			padded_buffer[j] = message[payload_index++];
+		bitwise_xor(aes_out, padded_buffer, chain_buffer);
+		aes128k128d(key, chain_buffer, aes_out);
+
+	}
+
+	for (j = 0 ; j < 8; j++)
+		mic[j] = aes_out[j];
+
+	/* Insert MIC into payload */
+	for (j = 0; j < 8; j++)
+		message[payload_index + j] = mic[j];
+
+	payload_index = hdrlen + 8;
+	for (i = 0; i < num_blocks; i++) {
+		construct_ctr_preload(
+			ctr_preload,
+			a4_exists,
+			qc_exists,
+			message,
+			pn_vector,
+			i + 1,
+			frtype); /* add for CONFIG_IEEE80211W, none 11w also can use */
+		aes128k128d(key, ctr_preload, aes_out);
+		bitwise_xor(aes_out, &message[payload_index], chain_buffer);
+		for (j = 0; j < 16; j++)
+			message[payload_index++] = chain_buffer[j];
+	}
+
+	if (payload_remainder > 0) {        /* If there is a short final block, then pad it,*/
+		/* encrypt it and copy the unpadded part back  */
+		construct_ctr_preload(
+			ctr_preload,
+			a4_exists,
+			qc_exists,
+			message,
+			pn_vector,
+			num_blocks + 1,
+			frtype); /* add for CONFIG_IEEE80211W, none 11w also can use */
+
+		for (j = 0; j < 16; j++)
+			padded_buffer[j] = 0x00;
+		for (j = 0; j < payload_remainder; j++)
+			padded_buffer[j] = message[payload_index + j];
+		aes128k128d(key, ctr_preload, aes_out);
+		bitwise_xor(aes_out, padded_buffer, chain_buffer);
+		for (j = 0; j < payload_remainder; j++)
+			message[payload_index++] = chain_buffer[j];
+	}
+
+	/* Encrypt the MIC */
+	construct_ctr_preload(
+		ctr_preload,
+		a4_exists,
+		qc_exists,
+		message,
+		pn_vector,
+		0,
+		frtype); /* add for CONFIG_IEEE80211W, none 11w also can use */
+
+	for (j = 0; j < 16; j++)
+		padded_buffer[j] = 0x00;
+	for (j = 0; j < 8; j++)
+		padded_buffer[j] = message[j + hdrlen + 8 + plen - 8];
+
+	aes128k128d(key, ctr_preload, aes_out);
+	bitwise_xor(aes_out, padded_buffer, chain_buffer);
+	for (j = 0; j < 8; j++)
+		message[payload_index++] = chain_buffer[j];
+
+	/* compare the mic */
+	for (i = 0; i < 8; i++) {
+		if (pframe[hdrlen + 8 + plen - 8 + i] != message[hdrlen + 8 + plen - 8 + i]) {
+			RTW_INFO("aes_decipher:mic check error mic[%d]: pframe(%x) != message(%x)\n",
+				i, pframe[hdrlen + 8 + plen - 8 + i], message[hdrlen + 8 + plen - 8 + i]);
+			res = _FAIL;
+		}
+	}
+	return res;
+}
+
+u32	rtw_aes_decrypt(_adapter *padapter, u8 *precvframe)
+{
+	/* exclude ICV */
+
+
+	/*static*/
+	/*	unsigned char	message[MAX_MSG_SIZE]; */
+
+
+	/* Intermediate Buffers */
+
+
+	sint		length;
+	u8	*pframe, *prwskey;	/* , *payload,*iv */
+	struct	sta_info		*stainfo;
+	struct	rx_pkt_attrib	*prxattrib = &((union recv_frame *)precvframe)->u.hdr.attrib;
+	struct	security_priv	*psecuritypriv = &padapter->securitypriv;
+	/*	struct	recv_priv		*precvpriv=&padapter->recvpriv; */
+	u32	res = _SUCCESS;
+	pframe = (unsigned char *)((union recv_frame *)precvframe)->u.hdr.rx_data;
+	/* 4 start to encrypt each fragment */
+	if ((prxattrib->encrypt == _AES_)) {
+
+		stainfo = rtw_get_stainfo(&padapter->stapriv , &prxattrib->ta[0]);
+		if (stainfo != NULL) {
+
+			if (IS_MCAST(prxattrib->ra)) {
+				static systime start = 0;
+				static u32 no_gkey_bc_cnt = 0;
+				static u32 no_gkey_mc_cnt = 0;
+
+				/* RTW_INFO("rx bc/mc packets, to perform sw rtw_aes_decrypt\n"); */
+				/* prwskey = psecuritypriv->dot118021XGrpKey[psecuritypriv->dot118021XGrpKeyid].skey; */
+				if ((!MLME_IS_MESH(padapter) && psecuritypriv->binstallGrpkey == _FALSE)
+					#ifdef CONFIG_RTW_MESH
+					|| !(stainfo->gtk_bmp | BIT(prxattrib->key_index))
+					#endif
+				) {
+					res = _FAIL;
+
+					if (start == 0)
+						start = rtw_get_current_time();
+
+					if (is_broadcast_mac_addr(prxattrib->ra))
+						no_gkey_bc_cnt++;
+					else
+						no_gkey_mc_cnt++;
+
+					if (rtw_get_passing_time_ms(start) > 1000) {
+						if (no_gkey_bc_cnt || no_gkey_mc_cnt) {
+							RTW_PRINT(FUNC_ADPT_FMT" no_gkey_bc_cnt:%u, no_gkey_mc_cnt:%u\n",
+								FUNC_ADPT_ARG(padapter), no_gkey_bc_cnt, no_gkey_mc_cnt);
+						}
+						start = rtw_get_current_time();
+						no_gkey_bc_cnt = 0;
+						no_gkey_mc_cnt = 0;
+					}
+
+					goto exit;
+				}
+
+				if (no_gkey_bc_cnt || no_gkey_mc_cnt) {
+					RTW_PRINT(FUNC_ADPT_FMT" gkey installed. no_gkey_bc_cnt:%u, no_gkey_mc_cnt:%u\n",
+						FUNC_ADPT_ARG(padapter), no_gkey_bc_cnt, no_gkey_mc_cnt);
+				}
+				start = 0;
+				no_gkey_bc_cnt = 0;
+				no_gkey_mc_cnt = 0;
+
+				#ifdef CONFIG_RTW_MESH
+				if (MLME_IS_MESH(padapter)) {
+					/* TODO: multiple GK? */
+					prwskey = &stainfo->gtk.skey[0];
+				} else
+				#endif
+				{
+					prwskey = psecuritypriv->dot118021XGrpKey[prxattrib->key_index].skey;
+					if (psecuritypriv->dot118021XGrpKeyid != prxattrib->key_index) {
+						RTW_DBG("not match packet_index=%d, install_index=%d\n"
+							, prxattrib->key_index, psecuritypriv->dot118021XGrpKeyid);
+						res = _FAIL;
+						goto exit;
+					}
+				}
+			} else
+				prwskey = &stainfo->dot118021x_UncstKey.skey[0];
+
+			length = ((union recv_frame *)precvframe)->u.hdr.len - prxattrib->hdrlen - prxattrib->iv_len;
+#if 0
+			/*  add for CONFIG_IEEE80211W, debug */
+			if (0)
+				printk("@@@@@@@@@@@@@@@@@@ length=%d, prxattrib->hdrlen=%d, prxattrib->pkt_len=%d\n"
+				       , length, prxattrib->hdrlen, prxattrib->pkt_len);
+			if (0) {
+				int no;
+				/* test print PSK */
+				printk("PSK key below:\n");
+				for (no = 0; no < 16; no++)
+					printk(" %02x ", prwskey[no]);
+				printk("\n");
+			}
+			if (0) {
+				int no;
+				/* test print PSK */
+				printk("frame:\n");
+				for (no = 0; no < prxattrib->pkt_len; no++)
+					printk(" %02x ", pframe[no]);
+				printk("\n");
+			}
+#endif
+
+			res = aes_decipher(prwskey, prxattrib->hdrlen, pframe, length);
+
+			AES_SW_DEC_CNT_INC(psecuritypriv, prxattrib->ra);
+		} else {
+			res = _FAIL;
+		}
+
+	}
+exit:
+	return res;
+}
+
+#ifdef CONFIG_IEEE80211W
+u32	rtw_BIP_verify(_adapter *padapter, u8 *whdr_pos, sint flen
+	, const u8 *key, u16 keyid, u64* ipn)
+{
+	u8 *BIP_AAD, *mme;
+	u32	res = _FAIL;
+	uint len, ori_len;
+	u16 pkt_keyid = 0;
+	u64 pkt_ipn = 0;
+	struct rtw_ieee80211_hdr *pwlanhdr;
+	u8 mic[16];
+
+	mme = whdr_pos + flen - 18;
+	if (*mme != _MME_IE_)
+		return RTW_RX_HANDLED;
+
+	/* copy key index */
+	_rtw_memcpy(&pkt_keyid, mme + 2, 2);
+	pkt_keyid = le16_to_cpu(pkt_keyid);
+	if (pkt_keyid != keyid) {
+		RTW_INFO("BIP key index error!\n");
+		return _FAIL;
+	}
+
+	/* save packet number */
+	_rtw_memcpy(&pkt_ipn, mme + 4, 6);
+	pkt_ipn = le64_to_cpu(pkt_ipn);
+	/* BIP packet number should bigger than previous BIP packet */
+	if (pkt_ipn <= *ipn) { /* wrap around? */
+		RTW_INFO("replay BIP packet\n");
+		return _FAIL;
+	}
+
+	ori_len = flen - WLAN_HDR_A3_LEN + BIP_AAD_SIZE;
+	BIP_AAD = rtw_zmalloc(ori_len);
+	if (BIP_AAD == NULL) {
+		RTW_INFO("BIP AAD allocate fail\n");
+		return _FAIL;
+	}
+
+	/* mapping to wlan header */
+	pwlanhdr = (struct rtw_ieee80211_hdr *)whdr_pos;
+
+	/* save the frame body + MME */
+	_rtw_memcpy(BIP_AAD + BIP_AAD_SIZE, whdr_pos + WLAN_HDR_A3_LEN, flen - WLAN_HDR_A3_LEN);
+
+	/* point mme to the copy */
+	mme = BIP_AAD + ori_len - 18;
+
+	/* clear the MIC field of MME to zero */
+	_rtw_memset(mme + 10, 0, 8);
+
+	/* conscruct AAD, copy frame control field */
+	_rtw_memcpy(BIP_AAD, &pwlanhdr->frame_ctl, 2);
+	ClearRetry(BIP_AAD);
+	ClearPwrMgt(BIP_AAD);
+	ClearMData(BIP_AAD);
+	/* conscruct AAD, copy address 1 to address 3 */
+	_rtw_memcpy(BIP_AAD + 2, pwlanhdr->addr1, 18);
+
+	if (omac1_aes_128(key, BIP_AAD, ori_len, mic))
+		goto BIP_exit;
+
+#if 0
+	/* management packet content */
+	{
+		int pp;
+		RTW_INFO("pkt: ");
+		for (pp = 0; pp < flen; pp++)
+			printk(" %02x ", whdr_pos[pp]);
+		RTW_INFO("\n");
+		/* BIP AAD + management frame body + MME(MIC is zero) */
+		RTW_INFO("AAD+PKT: ");
+		for (pp = 0; pp < ori_len; pp++)
+			RTW_INFO(" %02x ", BIP_AAD[pp]);
+		RTW_INFO("\n");
+		/* show the MIC result */
+		RTW_INFO("mic: ");
+		for (pp = 0; pp < 16; pp++)
+			RTW_INFO(" %02x ", mic[pp]);
+		RTW_INFO("\n");
+	}
+#endif
+
+	/* MIC field should be last 8 bytes of packet (packet without FCS) */
+	if (_rtw_memcmp(mic, whdr_pos + flen - 8, 8)) {
+		*ipn = pkt_ipn;
+		res = _SUCCESS;
+	} else
+		RTW_INFO("BIP MIC error!\n");
+
+BIP_exit:
+
+	rtw_mfree(BIP_AAD, ori_len);
+	return res;
+}
+#endif /* CONFIG_IEEE80211W */
+
+#ifndef PLATFORM_FREEBSD
+#if defined(CONFIG_TDLS)
+/* compress 512-bits */
+static int sha256_compress(struct _sha256_state *md, unsigned char *buf)
+{
+	u32 S[8], W[64], t0, t1;
+	u32 t;
+	int i;
+
+	/* copy state into S */
+	for (i = 0; i < 8; i++)
+		S[i] = md->state[i];
+
+	/* copy the state into 512-bits into W[0..15] */
+	for (i = 0; i < 16; i++)
+		W[i] = WPA_GET_BE32(buf + (4 * i));
+
+	/* fill W[16..63] */
+	for (i = 16; i < 64; i++) {
+		W[i] = Gamma1(W[i - 2]) + W[i - 7] + Gamma0(W[i - 15]) +
+		       W[i - 16];
+	}
+
+	/* Compress */
+#define RND(a, b, c, d, e, f, g, h, i)                          do {\
+	t0 = h + Sigma1(e) + Ch(e, f, g) + K[i] + W[i];	\
+	t1 = Sigma0(a) + Maj(a, b, c);			\
+	d += t0;					\
+	h  = t0 + t1;	\
+	} while (0)
+
+	for (i = 0; i < 64; ++i) {
+		RND(S[0], S[1], S[2], S[3], S[4], S[5], S[6], S[7], i);
+		t = S[7];
+		S[7] = S[6];
+		S[6] = S[5];
+		S[5] = S[4];
+		S[4] = S[3];
+		S[3] = S[2];
+		S[2] = S[1];
+		S[1] = S[0];
+		S[0] = t;
+	}
+
+	/* feedback */
+	for (i = 0; i < 8; i++)
+		md->state[i] = md->state[i] + S[i];
+	return 0;
+}
+
+/* Initialize the hash state */
+static void sha256_init(struct _sha256_state *md)
+{
+	md->curlen = 0;
+	md->length = 0;
+	md->state[0] = 0x6A09E667UL;
+	md->state[1] = 0xBB67AE85UL;
+	md->state[2] = 0x3C6EF372UL;
+	md->state[3] = 0xA54FF53AUL;
+	md->state[4] = 0x510E527FUL;
+	md->state[5] = 0x9B05688CUL;
+	md->state[6] = 0x1F83D9ABUL;
+	md->state[7] = 0x5BE0CD19UL;
+}
+
+/**
+   Process a block of memory though the hash
+   @param md     The hash state
+   @param in     The data to hash
+   @param inlen  The length of the data (octets)
+   @return CRYPT_OK if successful
+*/
+static int sha256_process(struct _sha256_state *md, unsigned char *in,
+			  unsigned long inlen)
+{
+	unsigned long n;
+#define block_size 64
+
+	if (md->curlen >= sizeof(md->buf))
+		return -1;
+
+	while (inlen > 0) {
+		if (md->curlen == 0 && inlen >= block_size) {
+			if (sha256_compress(md, (unsigned char *) in) < 0)
+				return -1;
+			md->length += block_size * 8;
+			in += block_size;
+			inlen -= block_size;
+		} else {
+			n = MIN(inlen, (block_size - md->curlen));
+			_rtw_memcpy(md->buf + md->curlen, in, n);
+			md->curlen += n;
+			in += n;
+			inlen -= n;
+			if (md->curlen == block_size) {
+				if (sha256_compress(md, md->buf) < 0)
+					return -1;
+				md->length += 8 * block_size;
+				md->curlen = 0;
+			}
+		}
+	}
+
+	return 0;
+}
+
+
+/**
+   Terminate the hash to get the digest
+   @param md  The hash state
+   @param out [out] The destination of the hash (32 bytes)
+   @return CRYPT_OK if successful
+*/
+static int sha256_done(struct _sha256_state *md, unsigned char *out)
+{
+	int i;
+
+	if (md->curlen >= sizeof(md->buf))
+		return -1;
+
+	/* increase the length of the message */
+	md->length += md->curlen * 8;
+
+	/* append the '1' bit */
+	md->buf[md->curlen++] = (unsigned char) 0x80;
+
+	/* if the length is currently above 56 bytes we append zeros
+	 * then compress.  Then we can fall back to padding zeros and length
+	 * encoding like normal.
+	 */
+	if (md->curlen > 56) {
+		while (md->curlen < 64)
+			md->buf[md->curlen++] = (unsigned char) 0;
+		sha256_compress(md, md->buf);
+		md->curlen = 0;
+	}
+
+	/* pad upto 56 bytes of zeroes */
+	while (md->curlen < 56)
+		md->buf[md->curlen++] = (unsigned char) 0;
+
+	/* store length */
+	WPA_PUT_BE64(md->buf + 56, md->length);
+	sha256_compress(md, md->buf);
+
+	/* copy output */
+	for (i = 0; i < 8; i++)
+		WPA_PUT_BE32(out + (4 * i), md->state[i]);
+
+	return 0;
+}
+
+/**
+ * sha256_vector - SHA256 hash for data vector
+ * @num_elem: Number of elements in the data vector
+ * @addr: Pointers to the data areas
+ * @len: Lengths of the data blocks
+ * @mac: Buffer for the hash
+ * Returns: 0 on success, -1 of failure
+ */
+static int sha256_vector(size_t num_elem, u8 *addr[], size_t *len,
+			 u8 *mac)
+{
+	struct _sha256_state ctx;
+	size_t i;
+
+	sha256_init(&ctx);
+	for (i = 0; i < num_elem; i++)
+		if (sha256_process(&ctx, addr[i], len[i]))
+			return -1;
+	if (sha256_done(&ctx, mac))
+		return -1;
+	return 0;
+}
+
+static u8 os_strlen(const char *s)
+{
+	const char *p = s;
+	while (*p)
+		p++;
+	return p - s;
+}
+#endif
+
+#if defined(CONFIG_TDLS) || defined(CONFIG_RTW_MESH_AEK)
+static int os_memcmp(const void *s1, const void *s2, u8 n)
+{
+	const unsigned char *p1 = s1, *p2 = s2;
+
+	if (n == 0)
+		return 0;
+
+	while (*p1 == *p2) {
+		p1++;
+		p2++;
+		n--;
+		if (n == 0)
+			return 0;
+	}
+
+	return *p1 - *p2;
+}
+#endif
+
+/**
+ * hmac_sha256_vector - HMAC-SHA256 over data vector (RFC 2104)
+ * @key: Key for HMAC operations
+ * @key_len: Length of the key in bytes
+ * @num_elem: Number of elements in the data vector
+ * @addr: Pointers to the data areas
+ * @len: Lengths of the data blocks
+ * @mac: Buffer for the hash (32 bytes)
+ */
+#if defined(CONFIG_TDLS)
+static void hmac_sha256_vector(u8 *key, size_t key_len, size_t num_elem,
+			       u8 *addr[], size_t *len, u8 *mac)
+{
+	unsigned char k_pad[64]; /* padding - key XORd with ipad/opad */
+	unsigned char tk[32];
+	u8 *_addr[6];
+	size_t _len[6], i;
+
+	if (num_elem > 5) {
+		/*
+		 * Fixed limit on the number of fragments to avoid having to
+		 * allocate memory (which could fail).
+		 */
+		return;
+	}
+
+	/* if key is longer than 64 bytes reset it to key = SHA256(key) */
+	if (key_len > 64) {
+		sha256_vector(1, &key, &key_len, tk);
+		key = tk;
+		key_len = 32;
+	}
+
+	/* the HMAC_SHA256 transform looks like:
+	 *
+	 * SHA256(K XOR opad, SHA256(K XOR ipad, text))
+	 *
+	 * where K is an n byte key
+	 * ipad is the byte 0x36 repeated 64 times
+	 * opad is the byte 0x5c repeated 64 times
+	 * and text is the data being protected */
+
+	/* start out by storing key in ipad */
+	_rtw_memset(k_pad, 0, sizeof(k_pad));
+	_rtw_memcpy(k_pad, key, key_len);
+	/* XOR key with ipad values */
+	for (i = 0; i < 64; i++)
+		k_pad[i] ^= 0x36;
+
+	/* perform inner SHA256 */
+	_addr[0] = k_pad;
+	_len[0] = 64;
+	for (i = 0; i < num_elem; i++) {
+		_addr[i + 1] = addr[i];
+		_len[i + 1] = len[i];
+	}
+	sha256_vector(1 + num_elem, _addr, _len, mac);
+
+	_rtw_memset(k_pad, 0, sizeof(k_pad));
+	_rtw_memcpy(k_pad, key, key_len);
+	/* XOR key with opad values */
+	for (i = 0; i < 64; i++)
+		k_pad[i] ^= 0x5c;
+
+	/* perform outer SHA256 */
+	_addr[0] = k_pad;
+	_len[0] = 64;
+	_addr[1] = mac;
+	_len[1] = 32;
+	sha256_vector(2, _addr, _len, mac);
+}
+#endif /* CONFIG_TDLS */
+#endif /* PLATFORM_FREEBSD */
+/**
+ * sha256_prf - SHA256-based Pseudo-Random Function (IEEE 802.11r, 8.5.1.5.2)
+ * @key: Key for PRF
+ * @key_len: Length of the key in bytes
+ * @label: A unique label for each purpose of the PRF
+ * @data: Extra data to bind into the key
+ * @data_len: Length of the data
+ * @buf: Buffer for the generated pseudo-random key
+ * @buf_len: Number of bytes of key to generate
+ *
+ * This function is used to derive new, cryptographically separate keys from a
+ * given key.
+ */
+#ifndef PLATFORM_FREEBSD /* Baron */
+#if defined(CONFIG_TDLS)
+static void sha256_prf(u8 *key, size_t key_len, char *label,
+		       u8 *data, size_t data_len, u8 *buf, size_t buf_len)
+{
+	u16 counter = 1;
+	size_t pos, plen;
+	u8 hash[SHA256_MAC_LEN];
+	u8 *addr[4];
+	size_t len[4];
+	u8 counter_le[2], length_le[2];
+
+	addr[0] = counter_le;
+	len[0] = 2;
+	addr[1] = (u8 *) label;
+	len[1] = os_strlen(label);
+	addr[2] = data;
+	len[2] = data_len;
+	addr[3] = length_le;
+	len[3] = sizeof(length_le);
+
+	WPA_PUT_LE16(length_le, buf_len * 8);
+	pos = 0;
+	while (pos < buf_len) {
+		plen = buf_len - pos;
+		WPA_PUT_LE16(counter_le, counter);
+		if (plen >= SHA256_MAC_LEN) {
+			hmac_sha256_vector(key, key_len, 4, addr, len,
+					   &buf[pos]);
+			pos += SHA256_MAC_LEN;
+		} else {
+			hmac_sha256_vector(key, key_len, 4, addr, len, hash);
+			_rtw_memcpy(&buf[pos], hash, plen);
+			break;
+		}
+		counter++;
+	}
+}
+#endif
+#endif /* PLATFORM_FREEBSD Baron */
+
+/* AES tables*/
+const u32 Te0[256] = {
+	0xc66363a5U, 0xf87c7c84U, 0xee777799U, 0xf67b7b8dU,
+	0xfff2f20dU, 0xd66b6bbdU, 0xde6f6fb1U, 0x91c5c554U,
+	0x60303050U, 0x02010103U, 0xce6767a9U, 0x562b2b7dU,
+	0xe7fefe19U, 0xb5d7d762U, 0x4dababe6U, 0xec76769aU,
+	0x8fcaca45U, 0x1f82829dU, 0x89c9c940U, 0xfa7d7d87U,
+	0xeffafa15U, 0xb25959ebU, 0x8e4747c9U, 0xfbf0f00bU,
+	0x41adadecU, 0xb3d4d467U, 0x5fa2a2fdU, 0x45afafeaU,
+	0x239c9cbfU, 0x53a4a4f7U, 0xe4727296U, 0x9bc0c05bU,
+	0x75b7b7c2U, 0xe1fdfd1cU, 0x3d9393aeU, 0x4c26266aU,
+	0x6c36365aU, 0x7e3f3f41U, 0xf5f7f702U, 0x83cccc4fU,
+	0x6834345cU, 0x51a5a5f4U, 0xd1e5e534U, 0xf9f1f108U,
+	0xe2717193U, 0xabd8d873U, 0x62313153U, 0x2a15153fU,
+	0x0804040cU, 0x95c7c752U, 0x46232365U, 0x9dc3c35eU,
+	0x30181828U, 0x379696a1U, 0x0a05050fU, 0x2f9a9ab5U,
+	0x0e070709U, 0x24121236U, 0x1b80809bU, 0xdfe2e23dU,
+	0xcdebeb26U, 0x4e272769U, 0x7fb2b2cdU, 0xea75759fU,
+	0x1209091bU, 0x1d83839eU, 0x582c2c74U, 0x341a1a2eU,
+	0x361b1b2dU, 0xdc6e6eb2U, 0xb45a5aeeU, 0x5ba0a0fbU,
+	0xa45252f6U, 0x763b3b4dU, 0xb7d6d661U, 0x7db3b3ceU,
+	0x5229297bU, 0xdde3e33eU, 0x5e2f2f71U, 0x13848497U,
+	0xa65353f5U, 0xb9d1d168U, 0x00000000U, 0xc1eded2cU,
+	0x40202060U, 0xe3fcfc1fU, 0x79b1b1c8U, 0xb65b5bedU,
+	0xd46a6abeU, 0x8dcbcb46U, 0x67bebed9U, 0x7239394bU,
+	0x944a4adeU, 0x984c4cd4U, 0xb05858e8U, 0x85cfcf4aU,
+	0xbbd0d06bU, 0xc5efef2aU, 0x4faaaae5U, 0xedfbfb16U,
+	0x864343c5U, 0x9a4d4dd7U, 0x66333355U, 0x11858594U,
+	0x8a4545cfU, 0xe9f9f910U, 0x04020206U, 0xfe7f7f81U,
+	0xa05050f0U, 0x783c3c44U, 0x259f9fbaU, 0x4ba8a8e3U,
+	0xa25151f3U, 0x5da3a3feU, 0x804040c0U, 0x058f8f8aU,
+	0x3f9292adU, 0x219d9dbcU, 0x70383848U, 0xf1f5f504U,
+	0x63bcbcdfU, 0x77b6b6c1U, 0xafdada75U, 0x42212163U,
+	0x20101030U, 0xe5ffff1aU, 0xfdf3f30eU, 0xbfd2d26dU,
+	0x81cdcd4cU, 0x180c0c14U, 0x26131335U, 0xc3ecec2fU,
+	0xbe5f5fe1U, 0x359797a2U, 0x884444ccU, 0x2e171739U,
+	0x93c4c457U, 0x55a7a7f2U, 0xfc7e7e82U, 0x7a3d3d47U,
+	0xc86464acU, 0xba5d5de7U, 0x3219192bU, 0xe6737395U,
+	0xc06060a0U, 0x19818198U, 0x9e4f4fd1U, 0xa3dcdc7fU,
+	0x44222266U, 0x542a2a7eU, 0x3b9090abU, 0x0b888883U,
+	0x8c4646caU, 0xc7eeee29U, 0x6bb8b8d3U, 0x2814143cU,
+	0xa7dede79U, 0xbc5e5ee2U, 0x160b0b1dU, 0xaddbdb76U,
+	0xdbe0e03bU, 0x64323256U, 0x743a3a4eU, 0x140a0a1eU,
+	0x924949dbU, 0x0c06060aU, 0x4824246cU, 0xb85c5ce4U,
+	0x9fc2c25dU, 0xbdd3d36eU, 0x43acacefU, 0xc46262a6U,
+	0x399191a8U, 0x319595a4U, 0xd3e4e437U, 0xf279798bU,
+	0xd5e7e732U, 0x8bc8c843U, 0x6e373759U, 0xda6d6db7U,
+	0x018d8d8cU, 0xb1d5d564U, 0x9c4e4ed2U, 0x49a9a9e0U,
+	0xd86c6cb4U, 0xac5656faU, 0xf3f4f407U, 0xcfeaea25U,
+	0xca6565afU, 0xf47a7a8eU, 0x47aeaee9U, 0x10080818U,
+	0x6fbabad5U, 0xf0787888U, 0x4a25256fU, 0x5c2e2e72U,
+	0x381c1c24U, 0x57a6a6f1U, 0x73b4b4c7U, 0x97c6c651U,
+	0xcbe8e823U, 0xa1dddd7cU, 0xe874749cU, 0x3e1f1f21U,
+	0x964b4bddU, 0x61bdbddcU, 0x0d8b8b86U, 0x0f8a8a85U,
+	0xe0707090U, 0x7c3e3e42U, 0x71b5b5c4U, 0xcc6666aaU,
+	0x904848d8U, 0x06030305U, 0xf7f6f601U, 0x1c0e0e12U,
+	0xc26161a3U, 0x6a35355fU, 0xae5757f9U, 0x69b9b9d0U,
+	0x17868691U, 0x99c1c158U, 0x3a1d1d27U, 0x279e9eb9U,
+	0xd9e1e138U, 0xebf8f813U, 0x2b9898b3U, 0x22111133U,
+	0xd26969bbU, 0xa9d9d970U, 0x078e8e89U, 0x339494a7U,
+	0x2d9b9bb6U, 0x3c1e1e22U, 0x15878792U, 0xc9e9e920U,
+	0x87cece49U, 0xaa5555ffU, 0x50282878U, 0xa5dfdf7aU,
+	0x038c8c8fU, 0x59a1a1f8U, 0x09898980U, 0x1a0d0d17U,
+	0x65bfbfdaU, 0xd7e6e631U, 0x844242c6U, 0xd06868b8U,
+	0x824141c3U, 0x299999b0U, 0x5a2d2d77U, 0x1e0f0f11U,
+	0x7bb0b0cbU, 0xa85454fcU, 0x6dbbbbd6U, 0x2c16163aU,
+};
+const u32 Td0[256] = {
+	0x51f4a750U, 0x7e416553U, 0x1a17a4c3U, 0x3a275e96U,
+	0x3bab6bcbU, 0x1f9d45f1U, 0xacfa58abU, 0x4be30393U,
+	0x2030fa55U, 0xad766df6U, 0x88cc7691U, 0xf5024c25U,
+	0x4fe5d7fcU, 0xc52acbd7U, 0x26354480U, 0xb562a38fU,
+	0xdeb15a49U, 0x25ba1b67U, 0x45ea0e98U, 0x5dfec0e1U,
+	0xc32f7502U, 0x814cf012U, 0x8d4697a3U, 0x6bd3f9c6U,
+	0x038f5fe7U, 0x15929c95U, 0xbf6d7aebU, 0x955259daU,
+	0xd4be832dU, 0x587421d3U, 0x49e06929U, 0x8ec9c844U,
+	0x75c2896aU, 0xf48e7978U, 0x99583e6bU, 0x27b971ddU,
+	0xbee14fb6U, 0xf088ad17U, 0xc920ac66U, 0x7dce3ab4U,
+	0x63df4a18U, 0xe51a3182U, 0x97513360U, 0x62537f45U,
+	0xb16477e0U, 0xbb6bae84U, 0xfe81a01cU, 0xf9082b94U,
+	0x70486858U, 0x8f45fd19U, 0x94de6c87U, 0x527bf8b7U,
+	0xab73d323U, 0x724b02e2U, 0xe31f8f57U, 0x6655ab2aU,
+	0xb2eb2807U, 0x2fb5c203U, 0x86c57b9aU, 0xd33708a5U,
+	0x302887f2U, 0x23bfa5b2U, 0x02036abaU, 0xed16825cU,
+	0x8acf1c2bU, 0xa779b492U, 0xf307f2f0U, 0x4e69e2a1U,
+	0x65daf4cdU, 0x0605bed5U, 0xd134621fU, 0xc4a6fe8aU,
+	0x342e539dU, 0xa2f355a0U, 0x058ae132U, 0xa4f6eb75U,
+	0x0b83ec39U, 0x4060efaaU, 0x5e719f06U, 0xbd6e1051U,
+	0x3e218af9U, 0x96dd063dU, 0xdd3e05aeU, 0x4de6bd46U,
+	0x91548db5U, 0x71c45d05U, 0x0406d46fU, 0x605015ffU,
+	0x1998fb24U, 0xd6bde997U, 0x894043ccU, 0x67d99e77U,
+	0xb0e842bdU, 0x07898b88U, 0xe7195b38U, 0x79c8eedbU,
+	0xa17c0a47U, 0x7c420fe9U, 0xf8841ec9U, 0x00000000U,
+	0x09808683U, 0x322bed48U, 0x1e1170acU, 0x6c5a724eU,
+	0xfd0efffbU, 0x0f853856U, 0x3daed51eU, 0x362d3927U,
+	0x0a0fd964U, 0x685ca621U, 0x9b5b54d1U, 0x24362e3aU,
+	0x0c0a67b1U, 0x9357e70fU, 0xb4ee96d2U, 0x1b9b919eU,
+	0x80c0c54fU, 0x61dc20a2U, 0x5a774b69U, 0x1c121a16U,
+	0xe293ba0aU, 0xc0a02ae5U, 0x3c22e043U, 0x121b171dU,
+	0x0e090d0bU, 0xf28bc7adU, 0x2db6a8b9U, 0x141ea9c8U,
+	0x57f11985U, 0xaf75074cU, 0xee99ddbbU, 0xa37f60fdU,
+	0xf701269fU, 0x5c72f5bcU, 0x44663bc5U, 0x5bfb7e34U,
+	0x8b432976U, 0xcb23c6dcU, 0xb6edfc68U, 0xb8e4f163U,
+	0xd731dccaU, 0x42638510U, 0x13972240U, 0x84c61120U,
+	0x854a247dU, 0xd2bb3df8U, 0xaef93211U, 0xc729a16dU,
+	0x1d9e2f4bU, 0xdcb230f3U, 0x0d8652ecU, 0x77c1e3d0U,
+	0x2bb3166cU, 0xa970b999U, 0x119448faU, 0x47e96422U,
+	0xa8fc8cc4U, 0xa0f03f1aU, 0x567d2cd8U, 0x223390efU,
+	0x87494ec7U, 0xd938d1c1U, 0x8ccaa2feU, 0x98d40b36U,
+	0xa6f581cfU, 0xa57ade28U, 0xdab78e26U, 0x3fadbfa4U,
+	0x2c3a9de4U, 0x5078920dU, 0x6a5fcc9bU, 0x547e4662U,
+	0xf68d13c2U, 0x90d8b8e8U, 0x2e39f75eU, 0x82c3aff5U,
+	0x9f5d80beU, 0x69d0937cU, 0x6fd52da9U, 0xcf2512b3U,
+	0xc8ac993bU, 0x10187da7U, 0xe89c636eU, 0xdb3bbb7bU,
+	0xcd267809U, 0x6e5918f4U, 0xec9ab701U, 0x834f9aa8U,
+	0xe6956e65U, 0xaaffe67eU, 0x21bccf08U, 0xef15e8e6U,
+	0xbae79bd9U, 0x4a6f36ceU, 0xea9f09d4U, 0x29b07cd6U,
+	0x31a4b2afU, 0x2a3f2331U, 0xc6a59430U, 0x35a266c0U,
+	0x744ebc37U, 0xfc82caa6U, 0xe090d0b0U, 0x33a7d815U,
+	0xf104984aU, 0x41ecdaf7U, 0x7fcd500eU, 0x1791f62fU,
+	0x764dd68dU, 0x43efb04dU, 0xccaa4d54U, 0xe49604dfU,
+	0x9ed1b5e3U, 0x4c6a881bU, 0xc12c1fb8U, 0x4665517fU,
+	0x9d5eea04U, 0x018c355dU, 0xfa877473U, 0xfb0b412eU,
+	0xb3671d5aU, 0x92dbd252U, 0xe9105633U, 0x6dd64713U,
+	0x9ad7618cU, 0x37a10c7aU, 0x59f8148eU, 0xeb133c89U,
+	0xcea927eeU, 0xb761c935U, 0xe11ce5edU, 0x7a47b13cU,
+	0x9cd2df59U, 0x55f2733fU, 0x1814ce79U, 0x73c737bfU,
+	0x53f7cdeaU, 0x5ffdaa5bU, 0xdf3d6f14U, 0x7844db86U,
+	0xcaaff381U, 0xb968c43eU, 0x3824342cU, 0xc2a3405fU,
+	0x161dc372U, 0xbce2250cU, 0x283c498bU, 0xff0d9541U,
+	0x39a80171U, 0x080cb3deU, 0xd8b4e49cU, 0x6456c190U,
+	0x7bcb8461U, 0xd532b670U, 0x486c5c74U, 0xd0b85742U,
+};
+const u8 Td4s[256] = {
+	0x52U, 0x09U, 0x6aU, 0xd5U, 0x30U, 0x36U, 0xa5U, 0x38U,
+	0xbfU, 0x40U, 0xa3U, 0x9eU, 0x81U, 0xf3U, 0xd7U, 0xfbU,
+	0x7cU, 0xe3U, 0x39U, 0x82U, 0x9bU, 0x2fU, 0xffU, 0x87U,
+	0x34U, 0x8eU, 0x43U, 0x44U, 0xc4U, 0xdeU, 0xe9U, 0xcbU,
+	0x54U, 0x7bU, 0x94U, 0x32U, 0xa6U, 0xc2U, 0x23U, 0x3dU,
+	0xeeU, 0x4cU, 0x95U, 0x0bU, 0x42U, 0xfaU, 0xc3U, 0x4eU,
+	0x08U, 0x2eU, 0xa1U, 0x66U, 0x28U, 0xd9U, 0x24U, 0xb2U,
+	0x76U, 0x5bU, 0xa2U, 0x49U, 0x6dU, 0x8bU, 0xd1U, 0x25U,
+	0x72U, 0xf8U, 0xf6U, 0x64U, 0x86U, 0x68U, 0x98U, 0x16U,
+	0xd4U, 0xa4U, 0x5cU, 0xccU, 0x5dU, 0x65U, 0xb6U, 0x92U,
+	0x6cU, 0x70U, 0x48U, 0x50U, 0xfdU, 0xedU, 0xb9U, 0xdaU,
+	0x5eU, 0x15U, 0x46U, 0x57U, 0xa7U, 0x8dU, 0x9dU, 0x84U,
+	0x90U, 0xd8U, 0xabU, 0x00U, 0x8cU, 0xbcU, 0xd3U, 0x0aU,
+	0xf7U, 0xe4U, 0x58U, 0x05U, 0xb8U, 0xb3U, 0x45U, 0x06U,
+	0xd0U, 0x2cU, 0x1eU, 0x8fU, 0xcaU, 0x3fU, 0x0fU, 0x02U,
+	0xc1U, 0xafU, 0xbdU, 0x03U, 0x01U, 0x13U, 0x8aU, 0x6bU,
+	0x3aU, 0x91U, 0x11U, 0x41U, 0x4fU, 0x67U, 0xdcU, 0xeaU,
+	0x97U, 0xf2U, 0xcfU, 0xceU, 0xf0U, 0xb4U, 0xe6U, 0x73U,
+	0x96U, 0xacU, 0x74U, 0x22U, 0xe7U, 0xadU, 0x35U, 0x85U,
+	0xe2U, 0xf9U, 0x37U, 0xe8U, 0x1cU, 0x75U, 0xdfU, 0x6eU,
+	0x47U, 0xf1U, 0x1aU, 0x71U, 0x1dU, 0x29U, 0xc5U, 0x89U,
+	0x6fU, 0xb7U, 0x62U, 0x0eU, 0xaaU, 0x18U, 0xbeU, 0x1bU,
+	0xfcU, 0x56U, 0x3eU, 0x4bU, 0xc6U, 0xd2U, 0x79U, 0x20U,
+	0x9aU, 0xdbU, 0xc0U, 0xfeU, 0x78U, 0xcdU, 0x5aU, 0xf4U,
+	0x1fU, 0xddU, 0xa8U, 0x33U, 0x88U, 0x07U, 0xc7U, 0x31U,
+	0xb1U, 0x12U, 0x10U, 0x59U, 0x27U, 0x80U, 0xecU, 0x5fU,
+	0x60U, 0x51U, 0x7fU, 0xa9U, 0x19U, 0xb5U, 0x4aU, 0x0dU,
+	0x2dU, 0xe5U, 0x7aU, 0x9fU, 0x93U, 0xc9U, 0x9cU, 0xefU,
+	0xa0U, 0xe0U, 0x3bU, 0x4dU, 0xaeU, 0x2aU, 0xf5U, 0xb0U,
+	0xc8U, 0xebU, 0xbbU, 0x3cU, 0x83U, 0x53U, 0x99U, 0x61U,
+	0x17U, 0x2bU, 0x04U, 0x7eU, 0xbaU, 0x77U, 0xd6U, 0x26U,
+	0xe1U, 0x69U, 0x14U, 0x63U, 0x55U, 0x21U, 0x0cU, 0x7dU,
+};
+const u8 rcons[] = {
+	0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80, 0x1B, 0x36
+	/* for 128-bit blocks, Rijndael never uses more than 10 rcon values */
+};
+
+/**
+ * Expand the cipher key into the encryption key schedule.
+ *
+ * @return	the number of rounds for the given cipher key size.
+ */
+#ifndef PLATFORM_FREEBSD /* Baron */
+static void rijndaelKeySetupEnc(u32 rk[/*44*/], const u8 cipherKey[])
+{
+	int i;
+	u32 temp;
+
+	rk[0] = GETU32(cipherKey);
+	rk[1] = GETU32(cipherKey +  4);
+	rk[2] = GETU32(cipherKey +  8);
+	rk[3] = GETU32(cipherKey + 12);
+	for (i = 0; i < 10; i++) {
+		temp  = rk[3];
+		rk[4] = rk[0] ^
+			TE421(temp) ^ TE432(temp) ^ TE443(temp) ^ TE414(temp) ^
+			RCON(i);
+		rk[5] = rk[1] ^ rk[4];
+		rk[6] = rk[2] ^ rk[5];
+		rk[7] = rk[3] ^ rk[6];
+		rk += 4;
+	}
+}
+
+static void rijndaelEncrypt(u32 rk[/*44*/], u8 pt[16], u8 ct[16])
+{
+	u32 s0, s1, s2, s3, t0, t1, t2, t3;
+	int Nr = 10;
+#ifndef FULL_UNROLL
+	int r;
+#endif /* ?FULL_UNROLL */
+
+	/*
+	 * map byte array block to cipher state
+	 * and add initial round key:
+	 */
+	s0 = GETU32(pt) ^ rk[0];
+	s1 = GETU32(pt +  4) ^ rk[1];
+	s2 = GETU32(pt +  8) ^ rk[2];
+	s3 = GETU32(pt + 12) ^ rk[3];
+
+#define ROUND(i, d, s) do {\
+	d##0 = TE0(s##0) ^ TE1(s##1) ^ TE2(s##2) ^ TE3(s##3) ^ rk[4 * i]; \
+	d##1 = TE0(s##1) ^ TE1(s##2) ^ TE2(s##3) ^ TE3(s##0) ^ rk[4 * i + 1]; \
+	d##2 = TE0(s##2) ^ TE1(s##3) ^ TE2(s##0) ^ TE3(s##1) ^ rk[4 * i + 2]; \
+	d##3 = TE0(s##3) ^ TE1(s##0) ^ TE2(s##1) ^ TE3(s##2) ^ rk[4 * i + 3]; \
+	} while (0)
+
+#ifdef FULL_UNROLL
+
+	ROUND(1, t, s);
+	ROUND(2, s, t);
+	ROUND(3, t, s);
+	ROUND(4, s, t);
+	ROUND(5, t, s);
+	ROUND(6, s, t);
+	ROUND(7, t, s);
+	ROUND(8, s, t);
+	ROUND(9, t, s);
+
+	rk += Nr << 2;
+
+#else  /* !FULL_UNROLL */
+
+	/* Nr - 1 full rounds: */
+	r = Nr >> 1;
+	for (;;) {
+		ROUND(1, t, s);
+		rk += 8;
+		if (--r == 0)
+			break;
+		ROUND(0, s, t);
+	}
+
+#endif /* ?FULL_UNROLL */
+
+#undef ROUND
+
+	/*
+	 * apply last round and
+	 * map cipher state to byte array block:
+	 */
+	s0 = TE41(t0) ^ TE42(t1) ^ TE43(t2) ^ TE44(t3) ^ rk[0];
+	PUTU32(ct     , s0);
+	s1 = TE41(t1) ^ TE42(t2) ^ TE43(t3) ^ TE44(t0) ^ rk[1];
+	PUTU32(ct +  4, s1);
+	s2 = TE41(t2) ^ TE42(t3) ^ TE43(t0) ^ TE44(t1) ^ rk[2];
+	PUTU32(ct +  8, s2);
+	s3 = TE41(t3) ^ TE42(t0) ^ TE43(t1) ^ TE44(t2) ^ rk[3];
+	PUTU32(ct + 12, s3);
+}
+
+static void *aes_encrypt_init(const u8 *key, size_t len)
+{
+	u32 *rk;
+	if (len != 16)
+		return NULL;
+	rk = (u32 *)rtw_malloc(AES_PRIV_SIZE);
+	if (rk == NULL)
+		return NULL;
+	rijndaelKeySetupEnc(rk, key);
+	return rk;
+}
+
+static void aes_128_encrypt(void *ctx, u8 *plain, u8 *crypt)
+{
+	rijndaelEncrypt(ctx, plain, crypt);
+}
+
+
+static void gf_mulx(u8 *pad)
+{
+	int i, carry;
+
+	carry = pad[0] & 0x80;
+	for (i = 0; i < AES_BLOCK_SIZE - 1; i++)
+		pad[i] = (pad[i] << 1) | (pad[i + 1] >> 7);
+	pad[AES_BLOCK_SIZE - 1] <<= 1;
+	if (carry)
+		pad[AES_BLOCK_SIZE - 1] ^= 0x87;
+}
+
+static void aes_encrypt_deinit(void *ctx)
+{
+	_rtw_memset(ctx, 0, AES_PRIV_SIZE);
+	rtw_mfree(ctx, AES_PRIV_SIZE);
+}
+
+
+/**
+ * omac1_aes_128_vector - One-Key CBC MAC (OMAC1) hash with AES-128
+ * @key: 128-bit key for the hash operation
+ * @num_elem: Number of elements in the data vector
+ * @addr: Pointers to the data areas
+ * @len: Lengths of the data blocks
+ * @mac: Buffer for MAC (128 bits, i.e., 16 bytes)
+ * Returns: 0 on success, -1 on failure
+ *
+ * This is a mode for using block cipher (AES in this case) for authentication.
+ * OMAC1 was standardized with the name CMAC by NIST in a Special Publication
+ * (SP) 800-38B.
+ */
+static int omac1_aes_128_vector(const u8 *key, size_t num_elem,
+			 const u8 *addr[], const size_t *len, u8 *mac)
+{
+	void *ctx;
+	u8 cbc[AES_BLOCK_SIZE], pad[AES_BLOCK_SIZE];
+	const u8 *pos, *end;
+	size_t i, e, left, total_len;
+
+	ctx = aes_encrypt_init(key, 16);
+	if (ctx == NULL)
+		return -1;
+	_rtw_memset(cbc, 0, AES_BLOCK_SIZE);
+
+	total_len = 0;
+	for (e = 0; e < num_elem; e++)
+		total_len += len[e];
+	left = total_len;
+
+	e = 0;
+	pos = addr[0];
+	end = pos + len[0];
+
+	while (left >= AES_BLOCK_SIZE) {
+		for (i = 0; i < AES_BLOCK_SIZE; i++) {
+			cbc[i] ^= *pos++;
+			if (pos >= end) {
+				e++;
+				pos = addr[e];
+				end = pos + len[e];
+			}
+		}
+		if (left > AES_BLOCK_SIZE)
+			aes_128_encrypt(ctx, cbc, cbc);
+		left -= AES_BLOCK_SIZE;
+	}
+
+	_rtw_memset(pad, 0, AES_BLOCK_SIZE);
+	aes_128_encrypt(ctx, pad, pad);
+	gf_mulx(pad);
+
+	if (left || total_len == 0) {
+		for (i = 0; i < left; i++) {
+			cbc[i] ^= *pos++;
+			if (pos >= end) {
+				e++;
+				pos = addr[e];
+				end = pos + len[e];
+			}
+		}
+		cbc[left] ^= 0x80;
+		gf_mulx(pad);
+	}
+
+	for (i = 0; i < AES_BLOCK_SIZE; i++)
+		pad[i] ^= cbc[i];
+	aes_128_encrypt(ctx, pad, mac);
+	aes_encrypt_deinit(ctx);
+	return 0;
+}
+
+
+/**
+ * omac1_aes_128 - One-Key CBC MAC (OMAC1) hash with AES-128 (aka AES-CMAC)
+ * @key: 128-bit key for the hash operation
+ * @data: Data buffer for which a MAC is determined
+ * @data_len: Length of data buffer in bytes
+ * @mac: Buffer for MAC (128 bits, i.e., 16 bytes)
+ * Returns: 0 on success, -1 on failure
+ *
+ * This is a mode for using block cipher (AES in this case) for authentication.
+ * OMAC1 was standardized with the name CMAC by NIST in a Special Publication
+ * (SP) 800-38B.
+ */ /* modify for CONFIG_IEEE80211W */
+int omac1_aes_128(const u8 *key, const u8 *data, size_t data_len, u8 *mac)
+{
+	return omac1_aes_128_vector(key, 1, &data, &data_len, mac);
+}
+#endif /* PLATFORM_FREEBSD Baron */
+
+#ifdef CONFIG_RTW_MESH_AEK
+/* for AES-SIV */
+#define os_memset _rtw_memset
+#define os_memcpy _rtw_memcpy
+#define os_malloc rtw_malloc
+#define bin_clear_free(bin, len) \
+	do { \
+		if (bin) { \
+			os_memset(bin, 0, len); \
+			rtw_mfree(bin, len); \
+		} \
+	} while (0)
+
+static const u8 zero[AES_BLOCK_SIZE];
+
+static void dbl(u8 *pad)
+{
+	int i, carry;
+
+	carry = pad[0] & 0x80;
+	for (i = 0; i < AES_BLOCK_SIZE - 1; i++)
+		pad[i] = (pad[i] << 1) | (pad[i + 1] >> 7);
+	pad[AES_BLOCK_SIZE - 1] <<= 1;
+	if (carry)
+		pad[AES_BLOCK_SIZE - 1] ^= 0x87;
+}
+
+static void xor(u8 *a, const u8 *b)
+{
+	int i;
+
+	for (i = 0; i < AES_BLOCK_SIZE; i++)
+		*a++ ^= *b++;
+}
+
+static void xorend(u8 *a, int alen, const u8 *b, int blen)
+{
+	int i;
+
+	if (alen < blen)
+		return;
+
+	for (i = 0; i < blen; i++)
+		a[alen - blen + i] ^= b[i];
+}
+
+static void pad_block(u8 *pad, const u8 *addr, size_t len)
+{
+	os_memset(pad, 0, AES_BLOCK_SIZE);
+	os_memcpy(pad, addr, len);
+
+	if (len < AES_BLOCK_SIZE)
+		pad[len] = 0x80;
+}
+
+static int aes_s2v(const u8 *key, size_t num_elem, const u8 *addr[],
+		   size_t *len, u8 *mac)
+{
+	u8 tmp[AES_BLOCK_SIZE], tmp2[AES_BLOCK_SIZE];
+	u8 *buf = NULL;
+	int ret;
+	size_t i;
+
+	if (!num_elem) {
+		os_memcpy(tmp, zero, sizeof(zero));
+		tmp[AES_BLOCK_SIZE - 1] = 1;
+		return omac1_aes_128(key, tmp, sizeof(tmp), mac);
+	}
+
+	ret = omac1_aes_128(key, zero, sizeof(zero), tmp);
+	if (ret)
+		return ret;
+
+	for (i = 0; i < num_elem - 1; i++) {
+		ret = omac1_aes_128(key, addr[i], len[i], tmp2);
+		if (ret)
+			return ret;
+
+		dbl(tmp);
+		xor(tmp, tmp2);
+	}
+	if (len[i] >= AES_BLOCK_SIZE) {
+		buf = os_malloc(len[i]);
+		if (!buf)
+			return -ENOMEM;
+
+		os_memcpy(buf, addr[i], len[i]);
+		xorend(buf, len[i], tmp, AES_BLOCK_SIZE);
+		ret = omac1_aes_128(key, buf, len[i], mac);
+		bin_clear_free(buf, len[i]);
+		return ret;
+	}
+
+	dbl(tmp);
+	pad_block(tmp2, addr[i], len[i]);
+	xor(tmp, tmp2);
+
+	return omac1_aes_128(key, tmp, sizeof(tmp), mac);
+}
+
+/**
+ * aes_128_ctr_encrypt - AES-128 CTR mode encryption
+ * @key: Key for encryption (16 bytes)
+ * @nonce: Nonce for counter mode (16 bytes)
+ * @data: Data to encrypt in-place
+ * @data_len: Length of data in bytes
+ * Returns: 0 on success, -1 on failure
+ */
+int aes_128_ctr_encrypt(const u8 *key, const u8 *nonce,
+			u8 *data, size_t data_len)
+{
+	void *ctx;
+	size_t j, len, left = data_len;
+	int i;
+	u8 *pos = data;
+	u8 counter[AES_BLOCK_SIZE], buf[AES_BLOCK_SIZE];
+
+	ctx = aes_encrypt_init(key, 16);
+	if (ctx == NULL)
+		return -1;
+	os_memcpy(counter, nonce, AES_BLOCK_SIZE);
+
+	while (left > 0) {
+		#if 0
+		aes_encrypt(ctx, counter, buf);
+		#else
+		aes_128_encrypt(ctx, counter, buf);
+		#endif
+
+		len = (left < AES_BLOCK_SIZE) ? left : AES_BLOCK_SIZE;
+		for (j = 0; j < len; j++)
+			pos[j] ^= buf[j];
+		pos += len;
+		left -= len;
+
+		for (i = AES_BLOCK_SIZE - 1; i >= 0; i--) {
+			counter[i]++;
+			if (counter[i])
+				break;
+		}
+	}
+	aes_encrypt_deinit(ctx);
+	return 0;
+}
+
+int aes_siv_encrypt(const u8 *key, const u8 *pw,
+		    size_t pwlen, size_t num_elem,
+		    const u8 *addr[], const size_t *len, u8 *out)
+{
+	const u8 *_addr[6];
+	size_t _len[6];
+	const u8 *k1 = key, *k2 = key + 16;
+	u8 v[AES_BLOCK_SIZE];
+	size_t i;
+	u8 *iv, *crypt_pw;
+
+	if (num_elem > ARRAY_SIZE(_addr) - 1)
+		return -1;
+
+	for (i = 0; i < num_elem; i++) {
+		_addr[i] = addr[i];
+		_len[i] = len[i];
+	}
+	_addr[num_elem] = pw;
+	_len[num_elem] = pwlen;
+
+	if (aes_s2v(k1, num_elem + 1, _addr, _len, v))
+		return -1;
+
+	iv = out;
+	crypt_pw = out + AES_BLOCK_SIZE;
+
+	os_memcpy(iv, v, AES_BLOCK_SIZE);
+	os_memcpy(crypt_pw, pw, pwlen);
+
+	/* zero out 63rd and 31st bits of ctr (from right) */
+	v[8] &= 0x7f;
+	v[12] &= 0x7f;
+	return aes_128_ctr_encrypt(k2, v, crypt_pw, pwlen);
+}
+
+int aes_siv_decrypt(const u8 *key, const u8 *iv_crypt, size_t iv_c_len,
+		    size_t num_elem, const u8 *addr[], const size_t *len,
+		    u8 *out)
+{
+	const u8 *_addr[6];
+	size_t _len[6];
+	const u8 *k1 = key, *k2 = key + 16;
+	size_t crypt_len;
+	size_t i;
+	int ret;
+	u8 iv[AES_BLOCK_SIZE];
+	u8 check[AES_BLOCK_SIZE];
+
+	if (iv_c_len < AES_BLOCK_SIZE || num_elem > ARRAY_SIZE(_addr) - 1)
+		return -1;
+	crypt_len = iv_c_len - AES_BLOCK_SIZE;
+
+	for (i = 0; i < num_elem; i++) {
+		_addr[i] = addr[i];
+		_len[i] = len[i];
+	}
+	_addr[num_elem] = out;
+	_len[num_elem] = crypt_len;
+
+	os_memcpy(iv, iv_crypt, AES_BLOCK_SIZE);
+	os_memcpy(out, iv_crypt + AES_BLOCK_SIZE, crypt_len);
+
+	iv[8] &= 0x7f;
+	iv[12] &= 0x7f;
+
+	ret = aes_128_ctr_encrypt(k2, iv, out, crypt_len);
+	if (ret)
+		return ret;
+
+	ret = aes_s2v(k1, num_elem + 1, _addr, _len, check);
+	if (ret)
+		return ret;
+	if (os_memcmp(check, iv_crypt, AES_BLOCK_SIZE) == 0)
+		return 0;
+
+	return -1;
+}
+#endif /* CONFIG_RTW_MESH_AEK */
+
+#ifdef CONFIG_TDLS
+void wpa_tdls_generate_tpk(_adapter *padapter, PVOID sta)
+{
+	struct sta_info *psta = (struct sta_info *)sta;
+	struct mlme_priv	*pmlmepriv = &padapter->mlmepriv;
+	u8 *SNonce = psta->SNonce;
+	u8 *ANonce = psta->ANonce;
+
+	u8 key_input[SHA256_MAC_LEN];
+	u8 *nonce[2];
+	size_t len[2];
+	u8 data[3 * ETH_ALEN];
+
+	/* IEEE Std 802.11z-2010 8.5.9.1:
+	 * TPK-Key-Input = SHA-256(min(SNonce, ANonce) || max(SNonce, ANonce))
+	 */
+	len[0] = 32;
+	len[1] = 32;
+	if (os_memcmp(SNonce, ANonce, 32) < 0) {
+		nonce[0] = SNonce;
+		nonce[1] = ANonce;
+	} else {
+		nonce[0] = ANonce;
+		nonce[1] = SNonce;
+	}
+
+	sha256_vector(2, nonce, len, key_input);
+
+	/*
+	 * TPK-Key-Data = KDF-N_KEY(TPK-Key-Input, "TDLS PMK",
+	 *	min(MAC_I, MAC_R) || max(MAC_I, MAC_R) || BSSID || N_KEY)
+	 * TODO: is N_KEY really included in KDF Context and if so, in which
+	 * presentation format (little endian 16-bit?) is it used? It gets
+	 * added by the KDF anyway..
+	 */
+
+	if (os_memcmp(adapter_mac_addr(padapter), psta->cmn.mac_addr, ETH_ALEN) < 0) {
+		_rtw_memcpy(data, adapter_mac_addr(padapter), ETH_ALEN);
+		_rtw_memcpy(data + ETH_ALEN, psta->cmn.mac_addr, ETH_ALEN);
+	} else {
+		_rtw_memcpy(data, psta->cmn.mac_addr, ETH_ALEN);
+		_rtw_memcpy(data + ETH_ALEN, adapter_mac_addr(padapter), ETH_ALEN);
+	}
+	_rtw_memcpy(data + 2 * ETH_ALEN, get_bssid(pmlmepriv), ETH_ALEN);
+
+	sha256_prf(key_input, SHA256_MAC_LEN, "TDLS PMK", data, sizeof(data), (u8 *) &psta->tpk, sizeof(psta->tpk));
+
+
+}
+
+/**
+ * wpa_tdls_ftie_mic - Calculate TDLS FTIE MIC
+ * @kck: TPK-KCK
+ * @lnkid: Pointer to the beginning of Link Identifier IE
+ * @rsnie: Pointer to the beginning of RSN IE used for handshake
+ * @timeoutie: Pointer to the beginning of Timeout IE used for handshake
+ * @ftie: Pointer to the beginning of FT IE
+ * @mic: Pointer for writing MIC
+ *
+ * Calculate MIC for TDLS frame.
+ */
+int wpa_tdls_ftie_mic(u8 *kck, u8 trans_seq,
+		      u8 *lnkid, u8 *rsnie, u8 *timeoutie, u8 *ftie,
+		      u8 *mic)
+{
+	u8 *buf, *pos;
+	struct wpa_tdls_ftie *_ftie;
+	struct wpa_tdls_lnkid *_lnkid;
+	int ret;
+	int len = 2 * ETH_ALEN + 1 + 2 + lnkid[1] + 2 + rsnie[1] +
+		  2 + timeoutie[1] + 2 + ftie[1];
+	buf = rtw_zmalloc(len);
+	if (!buf) {
+		RTW_INFO("TDLS: No memory for MIC calculation\n");
+		return -1;
+	}
+
+	pos = buf;
+	_lnkid = (struct wpa_tdls_lnkid *) lnkid;
+	/* 1) TDLS initiator STA MAC address */
+	_rtw_memcpy(pos, _lnkid->init_sta, ETH_ALEN);
+	pos += ETH_ALEN;
+	/* 2) TDLS responder STA MAC address */
+	_rtw_memcpy(pos, _lnkid->resp_sta, ETH_ALEN);
+	pos += ETH_ALEN;
+	/* 3) Transaction Sequence number */
+	*pos++ = trans_seq;
+	/* 4) Link Identifier IE */
+	_rtw_memcpy(pos, lnkid, 2 + lnkid[1]);
+	pos += 2 + lnkid[1];
+	/* 5) RSN IE */
+	_rtw_memcpy(pos, rsnie, 2 + rsnie[1]);
+	pos += 2 + rsnie[1];
+	/* 6) Timeout Interval IE */
+	_rtw_memcpy(pos, timeoutie, 2 + timeoutie[1]);
+	pos += 2 + timeoutie[1];
+	/* 7) FTIE, with the MIC field of the FTIE set to 0 */
+	_rtw_memcpy(pos, ftie, 2 + ftie[1]);
+	_ftie = (struct wpa_tdls_ftie *) pos;
+	_rtw_memset(_ftie->mic, 0, TDLS_MIC_LEN);
+	pos += 2 + ftie[1];
+
+	ret = omac1_aes_128(kck, buf, pos - buf, mic);
+	rtw_mfree(buf, len);
+	return ret;
+
+}
+
+/**
+ * wpa_tdls_teardown_ftie_mic - Calculate TDLS TEARDOWN FTIE MIC
+ * @kck: TPK-KCK
+ * @lnkid: Pointer to the beginning of Link Identifier IE
+ * @reason: Reason code of TDLS Teardown
+ * @dialog_token: Dialog token that was used in the MIC calculation for TPK Handshake Message 3
+ * @trans_seq: Transaction Sequence number (1 octet) which shall be set to the value 4
+ * @ftie: Pointer to the beginning of FT IE
+ * @mic: Pointer for writing MIC
+ *
+ * Calculate MIC for TDLS TEARDOWN frame according to Section 10.22.5 in IEEE 802.11 - 2012.
+ */
+int wpa_tdls_teardown_ftie_mic(u8 *kck, u8 *lnkid, u16 reason,
+			       u8 dialog_token, u8 trans_seq, u8 *ftie, u8 *mic)
+{
+	u8 *buf, *pos;
+	struct wpa_tdls_ftie *_ftie;
+	int ret;
+	int len = 2 + lnkid[1] + 2 + 1 + 1 + 2 + ftie[1];
+
+	buf = rtw_zmalloc(len);
+	if (!buf) {
+		RTW_INFO("TDLS: No memory for MIC calculation\n");
+		return -1;
+	}
+
+	pos = buf;
+	/* 1) Link Identifier IE */
+	_rtw_memcpy(pos, lnkid, 2 + lnkid[1]);
+	pos += 2 + lnkid[1];
+	/* 2) Reason Code */
+	_rtw_memcpy(pos, (u8 *)&reason, 2);
+	pos += 2;
+	/* 3) Dialog Token */
+	*pos++ = dialog_token;
+	/* 4) Transaction Sequence number */
+	*pos++ = trans_seq;
+	/* 5) FTIE, with the MIC field of the FTIE set to 0 */
+	_rtw_memcpy(pos, ftie, 2 + ftie[1]);
+	_ftie = (struct wpa_tdls_ftie *) pos;
+	_rtw_memset(_ftie->mic, 0, TDLS_MIC_LEN);
+	pos += 2 + ftie[1];
+
+	ret = omac1_aes_128(kck, buf, pos - buf, mic);
+	rtw_mfree(buf, len);
+	return ret;
+
+}
+
+int tdls_verify_mic(u8 *kck, u8 trans_seq,
+		    u8 *lnkid, u8 *rsnie, u8 *timeoutie, u8 *ftie)
+{
+	u8 *buf, *pos;
+	int len;
+	u8 mic[16];
+	int ret;
+	u8 *rx_ftie, *tmp_ftie;
+
+	if (lnkid == NULL || rsnie == NULL ||
+	    timeoutie == NULL || ftie == NULL)
+		return _FAIL;
+
+	len = 2 * ETH_ALEN + 1 + 2 + 18 + 2 + *(rsnie + 1) + 2 + *(timeoutie + 1) + 2 + *(ftie + 1);
+
+	buf = rtw_zmalloc(len);
+	if (buf == NULL)
+		return _FAIL;
+
+	pos = buf;
+	/* 1) TDLS initiator STA MAC address */
+	_rtw_memcpy(pos, lnkid + ETH_ALEN + 2, ETH_ALEN);
+	pos += ETH_ALEN;
+	/* 2) TDLS responder STA MAC address */
+	_rtw_memcpy(pos, lnkid + 2 * ETH_ALEN + 2, ETH_ALEN);
+	pos += ETH_ALEN;
+	/* 3) Transaction Sequence number */
+	*pos++ = trans_seq;
+	/* 4) Link Identifier IE */
+	_rtw_memcpy(pos, lnkid, 2 + 18);
+	pos += 2 + 18;
+	/* 5) RSN IE */
+	_rtw_memcpy(pos, rsnie, 2 + *(rsnie + 1));
+	pos += 2 + *(rsnie + 1);
+	/* 6) Timeout Interval IE */
+	_rtw_memcpy(pos, timeoutie, 2 + *(timeoutie + 1));
+	pos += 2 + *(timeoutie + 1);
+	/* 7) FTIE, with the MIC field of the FTIE set to 0 */
+	_rtw_memcpy(pos, ftie, 2 + *(ftie + 1));
+	pos += 2;
+	tmp_ftie = (u8 *)(pos + 2);
+	_rtw_memset(tmp_ftie, 0, 16);
+	pos += *(ftie + 1);
+
+	ret = omac1_aes_128(kck, buf, pos - buf, mic);
+	rtw_mfree(buf, len);
+	if (ret)
+		return _FAIL;
+	rx_ftie = ftie + 4;
+
+	if (os_memcmp(mic, rx_ftie, 16) == 0) {
+		/* Valid MIC */
+		return _SUCCESS;
+	}
+
+	/* Invalid MIC */
+	RTW_INFO("[%s] Invalid MIC\n", __FUNCTION__);
+	return _FAIL;
+
+}
+#endif /* CONFIG_TDLS */
+
+/* Restore HW wep key setting according to key_mask */
+void rtw_sec_restore_wep_key(_adapter *adapter)
+{
+	struct security_priv *securitypriv = &(adapter->securitypriv);
+	sint keyid;
+
+	if ((_WEP40_ == securitypriv->dot11PrivacyAlgrthm) || (_WEP104_ == securitypriv->dot11PrivacyAlgrthm)) {
+		for (keyid = 0; keyid < 4; keyid++) {
+			if (securitypriv->key_mask & BIT(keyid)) {
+				if (keyid == securitypriv->dot11PrivacyKeyIndex)
+					rtw_set_key(adapter, securitypriv, keyid, 1, _FALSE);
+				else
+					rtw_set_key(adapter, securitypriv, keyid, 0, _FALSE);
+			}
+		}
+	}
+}
+
+u8 rtw_handle_tkip_countermeasure(_adapter *adapter, const char *caller)
+{
+	struct security_priv *securitypriv = &(adapter->securitypriv);
+	u8 status = _SUCCESS;
+
+	if (securitypriv->btkip_countermeasure == _TRUE) {
+		u32 passing_ms = rtw_get_passing_time_ms(securitypriv->btkip_countermeasure_time);
+		if (passing_ms > 60 * 1000) {
+			RTW_PRINT("%s("ADPT_FMT") countermeasure time:%ds > 60s\n",
+				  caller, ADPT_ARG(adapter), passing_ms / 1000);
+			securitypriv->btkip_countermeasure = _FALSE;
+			securitypriv->btkip_countermeasure_time = 0;
+		} else {
+			RTW_PRINT("%s("ADPT_FMT") countermeasure time:%ds < 60s\n",
+				  caller, ADPT_ARG(adapter), passing_ms / 1000);
+			status = _FAIL;
+		}
+	}
+
+	return status;
+}
+
+#ifdef CONFIG_WOWLAN
+u16 rtw_cal_crc16(u8 data, u16 crc)
+{
+	u8 shift_in, data_bit;
+	u8 crc_bit4, crc_bit11, crc_bit15;
+	u16 crc_result;
+	int index;
+
+	for (index = 0; index < 8; index++) {
+		crc_bit15 = ((crc & BIT15) ? 1 : 0);
+		data_bit = (data & (BIT0 << index) ? 1 : 0);
+		shift_in = crc_bit15 ^ data_bit;
+		/*printf("crc_bit15=%d, DataBit=%d, shift_in=%d\n",
+		 * crc_bit15, data_bit, shift_in);*/
+
+		crc_result = crc << 1;
+
+		if (shift_in == 0)
+			crc_result &= (~BIT0);
+		else
+			crc_result |= BIT0;
+		/*printf("CRC =%x\n",CRC_Result);*/
+
+		crc_bit11 = ((crc & BIT11) ? 1 : 0) ^ shift_in;
+
+		if (crc_bit11 == 0)
+			crc_result &= (~BIT12);
+		else
+			crc_result |= BIT12;
+
+		/*printf("bit12 CRC =%x\n",CRC_Result);*/
+
+		crc_bit4 = ((crc & BIT4) ? 1 : 0) ^ shift_in;
+
+		if (crc_bit4 == 0)
+			crc_result &= (~BIT5);
+		else
+			crc_result |= BIT5;
+
+		/* printf("bit5 CRC =%x\n",CRC_Result); */
+		/* repeat using the last result*/
+		crc = crc_result;
+	}
+	return crc;
+}
+
+/*
+ * function name :rtw_calc_crc
+ *
+ * input: char* pattern , pattern size
+ *
+ */
+u16 rtw_calc_crc(u8  *pdata, int length)
+{
+	u16 crc = 0xffff;
+	int i;
+
+	for (i = 0; i < length; i++)
+		crc = rtw_cal_crc16(pdata[i], crc);
+	/* get 1' complement */
+	crc = ~crc;
+
+	return crc;
+}
+#endif /*CONFIG_WOWLAN*/
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/core/rtw_sreset.c linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/core/rtw_sreset.c
--- linux-5.6.3/3rdparty/rtl8821ce/core/rtw_sreset.c	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/core/rtw_sreset.c	2020-04-10 16:35:06.778658294 +0300
@@ -0,0 +1,314 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+
+#include <drv_types.h>
+#include <hal_data.h>
+#include <rtw_sreset.h>
+
+void sreset_init_value(_adapter *padapter)
+{
+#if defined(DBG_CONFIG_ERROR_DETECT)
+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(padapter);
+	struct sreset_priv *psrtpriv = &pHalData->srestpriv;
+
+	_rtw_mutex_init(&psrtpriv->silentreset_mutex);
+	psrtpriv->silent_reset_inprogress = _FALSE;
+	psrtpriv->Wifi_Error_Status = WIFI_STATUS_SUCCESS;
+	psrtpriv->last_tx_time = 0;
+	psrtpriv->last_tx_complete_time = 0;
+#endif
+}
+void sreset_reset_value(_adapter *padapter)
+{
+#if defined(DBG_CONFIG_ERROR_DETECT)
+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(padapter);
+	struct sreset_priv *psrtpriv = &pHalData->srestpriv;
+
+	psrtpriv->Wifi_Error_Status = WIFI_STATUS_SUCCESS;
+	psrtpriv->last_tx_time = 0;
+	psrtpriv->last_tx_complete_time = 0;
+#endif
+}
+
+u8 sreset_get_wifi_status(_adapter *padapter)
+{
+#if defined(DBG_CONFIG_ERROR_DETECT)
+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(padapter);
+	struct sreset_priv *psrtpriv = &pHalData->srestpriv;
+	u8 status = WIFI_STATUS_SUCCESS;
+	u32 val32 = 0;
+
+	if (psrtpriv->silent_reset_inprogress == _TRUE)
+		return status;
+	val32 = rtw_read32(padapter, REG_TXDMA_STATUS);
+	if (val32 == 0xeaeaeaea)
+		psrtpriv->Wifi_Error_Status = WIFI_IF_NOT_EXIST;
+	else if (val32 != 0) {
+		RTW_INFO("txdmastatu(%x)\n", val32);
+		psrtpriv->Wifi_Error_Status = WIFI_MAC_TXDMA_ERROR;
+	}
+
+	if (WIFI_STATUS_SUCCESS != psrtpriv->Wifi_Error_Status) {
+		RTW_INFO("==>%s error_status(0x%x)\n", __FUNCTION__, psrtpriv->Wifi_Error_Status);
+		status = (psrtpriv->Wifi_Error_Status & (~(USB_READ_PORT_FAIL | USB_WRITE_PORT_FAIL)));
+	}
+	RTW_INFO("==> %s wifi_status(0x%x)\n", __FUNCTION__, status);
+
+	/* status restore */
+	psrtpriv->Wifi_Error_Status = WIFI_STATUS_SUCCESS;
+
+	return status;
+#else
+	return WIFI_STATUS_SUCCESS;
+#endif
+}
+
+void sreset_set_wifi_error_status(_adapter *padapter, u32 status)
+{
+#if defined(DBG_CONFIG_ERROR_DETECT)
+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(padapter);
+	pHalData->srestpriv.Wifi_Error_Status = status;
+#endif
+}
+
+void sreset_set_trigger_point(_adapter *padapter, s32 tgp)
+{
+#if defined(DBG_CONFIG_ERROR_DETECT)
+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(padapter);
+	pHalData->srestpriv.dbg_trigger_point = tgp;
+#endif
+}
+
+bool sreset_inprogress(_adapter *padapter)
+{
+#if defined(DBG_CONFIG_ERROR_RESET)
+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(padapter);
+	return pHalData->srestpriv.silent_reset_inprogress;
+#else
+	return _FALSE;
+#endif
+}
+
+void sreset_restore_security_station(_adapter *padapter)
+{
+	struct mlme_priv *mlmepriv = &padapter->mlmepriv;
+	struct sta_priv *pstapriv = &padapter->stapriv;
+	struct sta_info *psta;
+	struct mlme_ext_info	*pmlmeinfo = &padapter->mlmeextpriv.mlmext_info;
+
+	{
+		u8 val8;
+
+		if (pmlmeinfo->auth_algo == dot11AuthAlgrthm_8021X) {
+			val8 = 0xcc;
+#ifdef CONFIG_WAPI_SUPPORT
+		} else if (padapter->wapiInfo.bWapiEnable && pmlmeinfo->auth_algo == dot11AuthAlgrthm_WAPI) {
+			/* Disable TxUseDefaultKey, RxUseDefaultKey, RxBroadcastUseDefaultKey. */
+			val8 = 0x4c;
+#endif
+		} else
+			val8 = 0xcf;
+		rtw_hal_set_hwreg(padapter, HW_VAR_SEC_CFG, (u8 *)(&val8));
+	}
+
+	if ((padapter->securitypriv.dot11PrivacyAlgrthm == _TKIP_) ||
+	    (padapter->securitypriv.dot11PrivacyAlgrthm == _AES_)) {
+		psta = rtw_get_stainfo(pstapriv, get_bssid(mlmepriv));
+		if (psta == NULL) {
+			/* DEBUG_ERR( ("Set wpa_set_encryption: Obtain Sta_info fail\n")); */
+		} else {
+			/* pairwise key */
+			rtw_setstakey_cmd(padapter, psta, UNICAST_KEY, _FALSE);
+			/* group key */
+			rtw_set_key(padapter, &padapter->securitypriv, padapter->securitypriv.dot118021XGrpKeyid, 0, _FALSE);
+		}
+	}
+}
+
+void sreset_restore_network_station(_adapter *padapter)
+{
+	struct mlme_priv *mlmepriv = &padapter->mlmepriv;
+	struct mlme_ext_priv	*pmlmeext = &padapter->mlmeextpriv;
+	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
+	u8 doiqk = _FALSE;
+
+	rtw_setopmode_cmd(padapter, Ndis802_11Infrastructure, RTW_CMDF_DIRECTLY);
+
+	{
+		u8 threshold;
+#ifdef CONFIG_USB_HCI
+		/* TH=1 => means that invalidate usb rx aggregation */
+		/* TH=0 => means that validate usb rx aggregation, use init value. */
+#ifdef CONFIG_80211N_HT
+		if (mlmepriv->htpriv.ht_option) {
+			if (padapter->registrypriv.wifi_spec == 1)
+				threshold = 1;
+			else
+				threshold = 0;
+			rtw_hal_set_hwreg(padapter, HW_VAR_RXDMA_AGG_PG_TH, (u8 *)(&threshold));
+		} else {
+			threshold = 1;
+			rtw_hal_set_hwreg(padapter, HW_VAR_RXDMA_AGG_PG_TH, (u8 *)(&threshold));
+		}
+#endif /* CONFIG_80211N_HT */
+#endif
+	}
+
+	doiqk = _TRUE;
+	rtw_hal_set_hwreg(padapter, HW_VAR_DO_IQK , &doiqk);
+
+	set_channel_bwmode(padapter, pmlmeext->cur_channel, pmlmeext->cur_ch_offset, pmlmeext->cur_bwmode);
+
+	doiqk = _FALSE;
+	rtw_hal_set_hwreg(padapter , HW_VAR_DO_IQK , &doiqk);
+	/* disable dynamic functions, such as high power, DIG */
+	/*rtw_phydm_func_disable_all(padapter);*/
+
+	rtw_hal_set_hwreg(padapter, HW_VAR_BSSID, pmlmeinfo->network.MacAddress);
+
+	{
+		u8	join_type = 0;
+
+		rtw_hal_rcr_set_chk_bssid(padapter, MLME_STA_CONNECTING);
+		rtw_hal_set_hwreg(padapter, HW_VAR_MLME_JOIN, (u8 *)(&join_type));
+	}
+
+	Set_MSR(padapter, (pmlmeinfo->state & 0x3));
+
+	mlmeext_joinbss_event_callback(padapter, 1);
+	/* restore Sequence No. */
+	rtw_hal_set_hwreg(padapter, HW_VAR_RESTORE_HW_SEQ, 0);
+
+	sreset_restore_security_station(padapter);
+}
+
+
+void sreset_restore_network_status(_adapter *padapter)
+{
+	struct mlme_priv *mlmepriv = &padapter->mlmepriv;
+
+	if (check_fwstate(mlmepriv, WIFI_STATION_STATE)) {
+		RTW_INFO(FUNC_ADPT_FMT" fwstate:0x%08x - WIFI_STATION_STATE\n", FUNC_ADPT_ARG(padapter), get_fwstate(mlmepriv));
+		sreset_restore_network_station(padapter);
+	} else if (MLME_IS_AP(padapter) || MLME_IS_MESH(padapter)) {
+		RTW_INFO(FUNC_ADPT_FMT" %s\n", FUNC_ADPT_ARG(padapter), MLME_IS_AP(padapter) ? "AP" : "MESH");
+		rtw_ap_restore_network(padapter);
+	} else if (check_fwstate(mlmepriv, WIFI_ADHOC_STATE))
+		RTW_INFO(FUNC_ADPT_FMT" fwstate:0x%08x - WIFI_ADHOC_STATE\n", FUNC_ADPT_ARG(padapter), get_fwstate(mlmepriv));
+	else
+		RTW_INFO(FUNC_ADPT_FMT" fwstate:0x%08x - ???\n", FUNC_ADPT_ARG(padapter), get_fwstate(mlmepriv));
+}
+
+void sreset_stop_adapter(_adapter *padapter)
+{
+	struct mlme_priv	*pmlmepriv = &(padapter->mlmepriv);
+	struct xmit_priv	*pxmitpriv = &padapter->xmitpriv;
+
+	if (padapter == NULL)
+		return;
+
+	RTW_INFO(FUNC_ADPT_FMT"\n", FUNC_ADPT_ARG(padapter));
+
+	rtw_netif_stop_queue(padapter->pnetdev);
+
+	rtw_cancel_all_timer(padapter);
+
+	/* TODO: OS and HCI independent */
+#if defined(PLATFORM_LINUX) && defined(CONFIG_USB_HCI)
+	tasklet_kill(&pxmitpriv->xmit_tasklet);
+#endif
+
+	if (check_fwstate(pmlmepriv, _FW_UNDER_SURVEY))
+		rtw_scan_abort(padapter);
+
+	if (check_fwstate(pmlmepriv, _FW_UNDER_LINKING)) {
+		rtw_set_to_roam(padapter, 0);
+		rtw_join_timeout_handler(padapter);
+	}
+
+}
+
+void sreset_start_adapter(_adapter *padapter)
+{
+	struct mlme_priv	*pmlmepriv = &(padapter->mlmepriv);
+	struct xmit_priv	*pxmitpriv = &padapter->xmitpriv;
+
+	if (padapter == NULL)
+		return;
+
+	RTW_INFO(FUNC_ADPT_FMT"\n", FUNC_ADPT_ARG(padapter));
+
+	if (check_fwstate(pmlmepriv, _FW_LINKED))
+		sreset_restore_network_status(padapter);
+
+	/* TODO: OS and HCI independent */
+#if defined(PLATFORM_LINUX) && defined(CONFIG_USB_HCI)
+	tasklet_hi_schedule(&pxmitpriv->xmit_tasklet);
+#endif
+
+	if (is_primary_adapter(padapter))
+		_set_timer(&adapter_to_dvobj(padapter)->dynamic_chk_timer, 2000);
+
+	rtw_netif_wake_queue(padapter->pnetdev);
+}
+
+void sreset_reset(_adapter *padapter)
+{
+#ifdef DBG_CONFIG_ERROR_RESET
+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(padapter);
+	struct sreset_priv *psrtpriv = &pHalData->srestpriv;
+	struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter);
+	struct mlme_priv	*pmlmepriv = &(padapter->mlmepriv);
+	struct xmit_priv	*pxmitpriv = &padapter->xmitpriv;
+	_irqL irqL;
+	systime start = rtw_get_current_time();
+	struct dvobj_priv *psdpriv = padapter->dvobj;
+	struct debug_priv *pdbgpriv = &psdpriv->drv_dbg;
+
+	RTW_INFO("%s\n", __FUNCTION__);
+
+	psrtpriv->Wifi_Error_Status = WIFI_STATUS_SUCCESS;
+
+
+#ifdef CONFIG_LPS
+	rtw_set_ps_mode(padapter, PS_MODE_ACTIVE, 0, 0, "SRESET");
+#endif/* #ifdef CONFIG_LPS */
+
+	_enter_pwrlock(&pwrpriv->lock);
+
+	psrtpriv->silent_reset_inprogress = _TRUE;
+	pwrpriv->change_rfpwrstate = rf_off;
+
+	rtw_mi_sreset_adapter_hdl(padapter, _FALSE);/*sreset_stop_adapter*/
+#ifdef CONFIG_IPS
+	_ips_enter(padapter);
+	_ips_leave(padapter);
+#endif
+#ifdef CONFIG_CONCURRENT_MODE
+	rtw_mi_ap_info_restore(padapter);
+#endif
+	rtw_mi_sreset_adapter_hdl(padapter, _TRUE);/*sreset_start_adapter*/
+
+	psrtpriv->silent_reset_inprogress = _FALSE;
+
+	_exit_pwrlock(&pwrpriv->lock);
+
+	RTW_INFO("%s done in %d ms\n", __FUNCTION__, rtw_get_passing_time_ms(start));
+	pdbgpriv->dbg_sreset_cnt++;
+
+	psrtpriv->self_dect_fw = _FALSE;
+	psrtpriv->rx_cnt = 0;
+#endif
+}
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/core/rtw_sta_mgt.c linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/core/rtw_sta_mgt.c
--- linux-5.6.3/3rdparty/rtl8821ce/core/rtw_sta_mgt.c	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/core/rtw_sta_mgt.c	2020-04-10 16:35:06.778658294 +0300
@@ -0,0 +1,1330 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#define _RTW_STA_MGT_C_
+
+#include <drv_types.h>
+
+#if defined(PLATFORM_LINUX) && defined (PLATFORM_WINDOWS)
+
+	#error "Shall be Linux or Windows, but not both!\n"
+
+#endif
+
+
+bool test_st_match_rule(_adapter *adapter, u8 *local_naddr, u8 *local_port, u8 *remote_naddr, u8 *remote_port)
+{
+	if (ntohs(*((u16 *)local_port)) == 5001 || ntohs(*((u16 *)remote_port)) == 5001)
+		return _TRUE;
+	return _FALSE;
+}
+
+struct st_register test_st_reg = {
+	.s_proto = 0x06,
+	.rule = test_st_match_rule,
+};
+
+inline void rtw_st_ctl_init(struct st_ctl_t *st_ctl)
+{
+	_rtw_memset(st_ctl->reg, 0 , sizeof(struct st_register) * SESSION_TRACKER_REG_ID_NUM);
+	_rtw_init_queue(&st_ctl->tracker_q);
+}
+
+inline void rtw_st_ctl_clear_tracker_q(struct st_ctl_t *st_ctl)
+{
+	_irqL irqL;
+	_list *plist, *phead;
+	struct session_tracker *st;
+
+	_enter_critical_bh(&st_ctl->tracker_q.lock, &irqL);
+	phead = &st_ctl->tracker_q.queue;
+	plist = get_next(phead);
+	while (rtw_end_of_queue_search(phead, plist) == _FALSE) {
+		st = LIST_CONTAINOR(plist, struct session_tracker, list);
+		plist = get_next(plist);
+		rtw_list_delete(&st->list);
+		rtw_mfree((u8 *)st, sizeof(struct session_tracker));
+	}
+	_exit_critical_bh(&st_ctl->tracker_q.lock, &irqL);
+}
+
+inline void rtw_st_ctl_deinit(struct st_ctl_t *st_ctl)
+{
+	rtw_st_ctl_clear_tracker_q(st_ctl);
+	_rtw_deinit_queue(&st_ctl->tracker_q);
+}
+
+inline void rtw_st_ctl_register(struct st_ctl_t *st_ctl, u8 st_reg_id, struct st_register *reg)
+{
+	if (st_reg_id >= SESSION_TRACKER_REG_ID_NUM) {
+		rtw_warn_on(1);
+		return;
+	}
+
+	st_ctl->reg[st_reg_id].s_proto = reg->s_proto;
+	st_ctl->reg[st_reg_id].rule = reg->rule;
+}
+
+inline void rtw_st_ctl_unregister(struct st_ctl_t *st_ctl, u8 st_reg_id)
+{
+	int i;
+
+	if (st_reg_id >= SESSION_TRACKER_REG_ID_NUM) {
+		rtw_warn_on(1);
+		return;
+	}
+
+	st_ctl->reg[st_reg_id].s_proto = 0;
+	st_ctl->reg[st_reg_id].rule = NULL;
+
+	/* clear tracker queue if no session trecker registered */
+	for (i = 0; i < SESSION_TRACKER_REG_ID_NUM; i++)
+		if (st_ctl->reg[i].s_proto != 0)
+			break;
+	if (i >= SESSION_TRACKER_REG_ID_NUM)
+		rtw_st_ctl_clear_tracker_q(st_ctl);
+}
+
+inline bool rtw_st_ctl_chk_reg_s_proto(struct st_ctl_t *st_ctl, u8 s_proto)
+{
+	bool ret = _FALSE;
+	int i;
+
+	for (i = 0; i < SESSION_TRACKER_REG_ID_NUM; i++) {
+		if (st_ctl->reg[i].s_proto == s_proto) {
+			ret = _TRUE;
+			break;
+		}
+	}
+
+	return ret;
+}
+
+inline bool rtw_st_ctl_chk_reg_rule(struct st_ctl_t *st_ctl, _adapter *adapter, u8 *local_naddr, u8 *local_port, u8 *remote_naddr, u8 *remote_port)
+{
+	bool ret = _FALSE;
+	int i;
+	st_match_rule rule;
+
+	for (i = 0; i < SESSION_TRACKER_REG_ID_NUM; i++) {
+		rule = st_ctl->reg[i].rule;
+		if (rule && rule(adapter, local_naddr, local_port, remote_naddr, remote_port) == _TRUE) {
+			ret = _TRUE;
+			break;
+		}
+	}
+
+	return ret;
+}
+
+void rtw_st_ctl_rx(struct sta_info *sta, u8 *ehdr_pos)
+{
+	_adapter *adapter = sta->padapter;
+	struct ethhdr *etherhdr = (struct ethhdr *)ehdr_pos;
+
+	if (ntohs(etherhdr->h_proto) == ETH_P_IP) {
+		u8 *ip = ehdr_pos + ETH_HLEN;
+
+		if (GET_IPV4_PROTOCOL(ip) == 0x06  /* TCP */
+			&& rtw_st_ctl_chk_reg_s_proto(&sta->st_ctl, 0x06) == _TRUE
+		) {
+			u8 *tcp = ip + GET_IPV4_IHL(ip) * 4;
+
+			if (rtw_st_ctl_chk_reg_rule(&sta->st_ctl, adapter, IPV4_DST(ip), TCP_DST(tcp), IPV4_SRC(ip), TCP_SRC(tcp)) == _TRUE) {
+				if (GET_TCP_SYN(tcp) && GET_TCP_ACK(tcp)) {
+					session_tracker_add_cmd(adapter, sta
+						, IPV4_DST(ip), TCP_DST(tcp)
+						, IPV4_SRC(ip), TCP_SRC(tcp));
+					if (DBG_SESSION_TRACKER)
+						RTW_INFO(FUNC_ADPT_FMT" local:"IP_FMT":"PORT_FMT", remote:"IP_FMT":"PORT_FMT" SYN-ACK\n"
+							, FUNC_ADPT_ARG(adapter)
+							, IP_ARG(IPV4_DST(ip)), PORT_ARG(TCP_DST(tcp))
+							, IP_ARG(IPV4_SRC(ip)), PORT_ARG(TCP_SRC(tcp)));
+				}
+				if (GET_TCP_FIN(tcp)) {
+					session_tracker_del_cmd(adapter, sta
+						, IPV4_DST(ip), TCP_DST(tcp)
+						, IPV4_SRC(ip), TCP_SRC(tcp));
+					if (DBG_SESSION_TRACKER)
+						RTW_INFO(FUNC_ADPT_FMT" local:"IP_FMT":"PORT_FMT", remote:"IP_FMT":"PORT_FMT" FIN\n"
+							, FUNC_ADPT_ARG(adapter)
+							, IP_ARG(IPV4_DST(ip)), PORT_ARG(TCP_DST(tcp))
+							, IP_ARG(IPV4_SRC(ip)), PORT_ARG(TCP_SRC(tcp)));
+				}
+			}
+
+		}
+	}
+}
+
+#define SESSION_TRACKER_FMT IP_FMT":"PORT_FMT" "IP_FMT":"PORT_FMT" %u %d"
+#define SESSION_TRACKER_ARG(st) IP_ARG(&(st)->local_naddr), PORT_ARG(&(st)->local_port), IP_ARG(&(st)->remote_naddr), PORT_ARG(&(st)->remote_port), (st)->status, rtw_get_passing_time_ms((st)->set_time)
+
+void dump_st_ctl(void *sel, struct st_ctl_t *st_ctl)
+{
+	int i;
+	_irqL irqL;
+	_list *plist, *phead;
+	struct session_tracker *st;
+
+	if (!DBG_SESSION_TRACKER)
+		return;
+
+	for (i = 0; i < SESSION_TRACKER_REG_ID_NUM; i++)
+		RTW_PRINT_SEL(sel, "reg%d: %u %p\n", i, st_ctl->reg[i].s_proto, st_ctl->reg[i].rule);
+
+	_enter_critical_bh(&st_ctl->tracker_q.lock, &irqL);
+	phead = &st_ctl->tracker_q.queue;
+	plist = get_next(phead);
+	while (rtw_end_of_queue_search(phead, plist) == _FALSE) {
+		st = LIST_CONTAINOR(plist, struct session_tracker, list);
+		plist = get_next(plist);
+
+		RTW_PRINT_SEL(sel, SESSION_TRACKER_FMT"\n", SESSION_TRACKER_ARG(st));
+	}
+	_exit_critical_bh(&st_ctl->tracker_q.lock, &irqL);
+
+}
+
+void _rtw_init_stainfo(struct sta_info *psta);
+void _rtw_init_stainfo(struct sta_info *psta)
+{
+	_rtw_memset((u8 *)psta, 0, sizeof(struct sta_info));
+
+	_rtw_spinlock_init(&psta->lock);
+	_rtw_init_listhead(&psta->list);
+	_rtw_init_listhead(&psta->hash_list);
+	/* _rtw_init_listhead(&psta->asoc_list); */
+	/* _rtw_init_listhead(&psta->sleep_list); */
+	/* _rtw_init_listhead(&psta->wakeup_list);	 */
+
+	_rtw_init_queue(&psta->sleep_q);
+
+	_rtw_init_sta_xmit_priv(&psta->sta_xmitpriv);
+	_rtw_init_sta_recv_priv(&psta->sta_recvpriv);
+
+#ifdef CONFIG_AP_MODE
+	_rtw_init_listhead(&psta->asoc_list);
+	_rtw_init_listhead(&psta->auth_list);
+	psta->bpairwise_key_installed = _FALSE;
+
+#ifdef CONFIG_RTW_80211R
+	psta->ft_pairwise_key_installed = _FALSE;
+#endif
+#endif /* CONFIG_AP_MODE	 */
+
+	rtw_st_ctl_init(&psta->st_ctl);
+}
+
+u32	_rtw_init_sta_priv(struct	sta_priv *pstapriv)
+{
+	_adapter *adapter = container_of(pstapriv, _adapter, stapriv);
+	struct macid_ctl_t *macid_ctl = adapter_to_macidctl(adapter);
+	struct sta_info *psta;
+	s32 i;
+	u32 ret = _FAIL;
+
+	pstapriv->padapter = adapter;
+
+	pstapriv->pallocated_stainfo_buf = rtw_zvmalloc(sizeof(struct sta_info) * NUM_STA + 4);
+	if (!pstapriv->pallocated_stainfo_buf)
+		goto exit;
+
+	pstapriv->pstainfo_buf = pstapriv->pallocated_stainfo_buf + 4 -
+			 ((SIZE_PTR)(pstapriv->pallocated_stainfo_buf) & 3);
+
+	_rtw_init_queue(&pstapriv->free_sta_queue);
+
+	_rtw_spinlock_init(&pstapriv->sta_hash_lock);
+
+	/* _rtw_init_queue(&pstapriv->asoc_q); */
+	pstapriv->asoc_sta_count = 0;
+	_rtw_init_queue(&pstapriv->sleep_q);
+	_rtw_init_queue(&pstapriv->wakeup_q);
+
+	psta = (struct sta_info *)(pstapriv->pstainfo_buf);
+
+
+	for (i = 0; i < NUM_STA; i++) {
+		_rtw_init_stainfo(psta);
+
+		_rtw_init_listhead(&(pstapriv->sta_hash[i]));
+
+		rtw_list_insert_tail(&psta->list, get_list_head(&pstapriv->free_sta_queue));
+
+		psta++;
+	}
+
+	pstapriv->adhoc_expire_to = 4; /* 4 * 2 = 8 sec */
+
+#ifdef CONFIG_AP_MODE
+	pstapriv->max_aid = macid_ctl->num;
+	pstapriv->rr_aid = 0;
+	pstapriv->started_aid = 1;
+	pstapriv->sta_aid = rtw_zmalloc(pstapriv->max_aid * sizeof(struct sta_info *));
+	if (!pstapriv->sta_aid)
+		goto exit;
+	pstapriv->aid_bmp_len = AID_BMP_LEN(pstapriv->max_aid);
+	pstapriv->sta_dz_bitmap = rtw_zmalloc(pstapriv->aid_bmp_len);
+	if (!pstapriv->sta_dz_bitmap)
+		goto exit;
+	pstapriv->tim_bitmap = rtw_zmalloc(pstapriv->aid_bmp_len);
+	if (!pstapriv->tim_bitmap)
+		goto exit;
+
+	_rtw_init_listhead(&pstapriv->asoc_list);
+	_rtw_init_listhead(&pstapriv->auth_list);
+	_rtw_spinlock_init(&pstapriv->asoc_list_lock);
+	_rtw_spinlock_init(&pstapriv->auth_list_lock);
+	pstapriv->asoc_list_cnt = 0;
+	pstapriv->auth_list_cnt = 0;
+
+	pstapriv->auth_to = 3; /* 3*2 = 6 sec */
+	pstapriv->assoc_to = 3;
+	/* pstapriv->expire_to = 900; */ /* 900*2 = 1800 sec = 30 min, expire after no any traffic. */
+	/* pstapriv->expire_to = 30; */ /* 30*2 = 60 sec = 1 min, expire after no any traffic. */
+#ifdef CONFIG_ACTIVE_KEEP_ALIVE_CHECK
+	pstapriv->expire_to = 3; /* 3*2 = 6 sec */
+#else
+	pstapriv->expire_to = 60;/* 60*2 = 120 sec = 2 min, expire after no any traffic. */
+#endif
+#ifdef CONFIG_ATMEL_RC_PATCH
+	_rtw_memset(pstapriv->atmel_rc_pattern, 0, ETH_ALEN);
+#endif
+	pstapriv->max_num_sta = NUM_STA;
+
+#endif
+
+#if CONFIG_RTW_MACADDR_ACL
+	for (i = 0; i < RTW_ACL_PERIOD_NUM; i++)
+		rtw_macaddr_acl_init(adapter, i);
+#endif
+
+#if CONFIG_RTW_PRE_LINK_STA
+	rtw_pre_link_sta_ctl_init(pstapriv);
+#endif
+
+	ret = _SUCCESS;
+
+exit:
+	if (ret != _SUCCESS) {
+		if (pstapriv->pallocated_stainfo_buf)
+			rtw_vmfree(pstapriv->pallocated_stainfo_buf, sizeof(struct sta_info) * NUM_STA + 4);
+		#ifdef CONFIG_AP_MODE
+		if (pstapriv->sta_aid)
+			rtw_mfree(pstapriv->sta_aid, pstapriv->max_aid * sizeof(struct sta_info *));
+		if (pstapriv->sta_dz_bitmap)
+			rtw_mfree(pstapriv->sta_dz_bitmap, pstapriv->aid_bmp_len);
+		#endif
+	}
+
+	return ret;
+}
+
+inline int rtw_stainfo_offset(struct sta_priv *stapriv, struct sta_info *sta)
+{
+	int offset = (((u8 *)sta) - stapriv->pstainfo_buf) / sizeof(struct sta_info);
+
+	if (!stainfo_offset_valid(offset))
+		RTW_INFO("%s invalid offset(%d), out of range!!!", __func__, offset);
+
+	return offset;
+}
+
+inline struct sta_info *rtw_get_stainfo_by_offset(struct sta_priv *stapriv, int offset)
+{
+	if (!stainfo_offset_valid(offset))
+		RTW_INFO("%s invalid offset(%d), out of range!!!", __func__, offset);
+
+	return (struct sta_info *)(stapriv->pstainfo_buf + offset * sizeof(struct sta_info));
+}
+
+void	_rtw_free_sta_xmit_priv_lock(struct sta_xmit_priv *psta_xmitpriv);
+void	_rtw_free_sta_xmit_priv_lock(struct sta_xmit_priv *psta_xmitpriv)
+{
+
+	_rtw_spinlock_free(&psta_xmitpriv->lock);
+
+	_rtw_spinlock_free(&(psta_xmitpriv->be_q.sta_pending.lock));
+	_rtw_spinlock_free(&(psta_xmitpriv->bk_q.sta_pending.lock));
+	_rtw_spinlock_free(&(psta_xmitpriv->vi_q.sta_pending.lock));
+	_rtw_spinlock_free(&(psta_xmitpriv->vo_q.sta_pending.lock));
+}
+
+static void	_rtw_free_sta_recv_priv_lock(struct sta_recv_priv *psta_recvpriv)
+{
+
+	_rtw_spinlock_free(&psta_recvpriv->lock);
+
+	_rtw_spinlock_free(&(psta_recvpriv->defrag_q.lock));
+
+
+}
+
+void rtw_mfree_stainfo(struct sta_info *psta);
+void rtw_mfree_stainfo(struct sta_info *psta)
+{
+
+	if (&psta->lock != NULL)
+		_rtw_spinlock_free(&psta->lock);
+
+	_rtw_free_sta_xmit_priv_lock(&psta->sta_xmitpriv);
+	_rtw_free_sta_recv_priv_lock(&psta->sta_recvpriv);
+
+}
+
+
+/* this function is used to free the memory of lock || sema for all stainfos */
+void rtw_mfree_all_stainfo(struct sta_priv *pstapriv);
+void rtw_mfree_all_stainfo(struct sta_priv *pstapriv)
+{
+	_irqL	 irqL;
+	_list	*plist, *phead;
+	struct sta_info *psta = NULL;
+
+
+	_enter_critical_bh(&pstapriv->sta_hash_lock, &irqL);
+
+	phead = get_list_head(&pstapriv->free_sta_queue);
+	plist = get_next(phead);
+
+	while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) {
+		psta = LIST_CONTAINOR(plist, struct sta_info , list);
+		plist = get_next(plist);
+
+		rtw_mfree_stainfo(psta);
+	}
+
+	_exit_critical_bh(&pstapriv->sta_hash_lock, &irqL);
+
+
+}
+
+void rtw_mfree_sta_priv_lock(struct	sta_priv *pstapriv);
+void rtw_mfree_sta_priv_lock(struct	sta_priv *pstapriv)
+{
+	rtw_mfree_all_stainfo(pstapriv); /* be done before free sta_hash_lock */
+
+	_rtw_spinlock_free(&pstapriv->free_sta_queue.lock);
+
+	_rtw_spinlock_free(&pstapriv->sta_hash_lock);
+	_rtw_spinlock_free(&pstapriv->wakeup_q.lock);
+	_rtw_spinlock_free(&pstapriv->sleep_q.lock);
+
+#ifdef CONFIG_AP_MODE
+	_rtw_spinlock_free(&pstapriv->asoc_list_lock);
+	_rtw_spinlock_free(&pstapriv->auth_list_lock);
+#endif
+
+}
+
+u32	_rtw_free_sta_priv(struct	sta_priv *pstapriv)
+{
+	_irqL	irqL;
+	_list	*phead, *plist;
+	struct sta_info *psta = NULL;
+	struct recv_reorder_ctrl *preorder_ctrl;
+	int	index;
+
+	if (pstapriv) {
+
+		/*	delete all reordering_ctrl_timer		*/
+		_enter_critical_bh(&pstapriv->sta_hash_lock, &irqL);
+		for (index = 0; index < NUM_STA; index++) {
+			phead = &(pstapriv->sta_hash[index]);
+			plist = get_next(phead);
+
+			while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) {
+				int i;
+				psta = LIST_CONTAINOR(plist, struct sta_info , hash_list);
+				plist = get_next(plist);
+
+				for (i = 0; i < 16 ; i++) {
+					preorder_ctrl = &psta->recvreorder_ctrl[i];
+					_cancel_timer_ex(&preorder_ctrl->reordering_ctrl_timer);
+				}
+			}
+		}
+		_exit_critical_bh(&pstapriv->sta_hash_lock, &irqL);
+		/*===============================*/
+
+		rtw_mfree_sta_priv_lock(pstapriv);
+
+#if CONFIG_RTW_MACADDR_ACL
+		for (index = 0; index < RTW_ACL_PERIOD_NUM; index++)
+			rtw_macaddr_acl_deinit(pstapriv->padapter, index);
+#endif
+
+#if CONFIG_RTW_PRE_LINK_STA
+		rtw_pre_link_sta_ctl_deinit(pstapriv);
+#endif
+
+		if (pstapriv->pallocated_stainfo_buf)
+			rtw_vmfree(pstapriv->pallocated_stainfo_buf, sizeof(struct sta_info) * NUM_STA + 4);
+		#ifdef CONFIG_AP_MODE
+		if (pstapriv->sta_aid)
+			rtw_mfree(pstapriv->sta_aid, pstapriv->max_aid * sizeof(struct sta_info *));
+		if (pstapriv->sta_dz_bitmap)
+			rtw_mfree(pstapriv->sta_dz_bitmap, pstapriv->aid_bmp_len);
+		if (pstapriv->tim_bitmap)
+			rtw_mfree(pstapriv->tim_bitmap, pstapriv->aid_bmp_len);
+		#endif
+	}
+
+	return _SUCCESS;
+}
+
+
+static void rtw_init_recv_timer(struct recv_reorder_ctrl *preorder_ctrl)
+{
+	_adapter *padapter = preorder_ctrl->padapter;
+
+#if defined(CONFIG_80211N_HT) && defined(CONFIG_RECV_REORDERING_CTRL)
+	rtw_init_timer(&(preorder_ctrl->reordering_ctrl_timer), padapter, rtw_reordering_ctrl_timeout_handler, preorder_ctrl);
+#endif
+}
+
+/* struct	sta_info *rtw_alloc_stainfo(_queue *pfree_sta_queue, unsigned char *hwaddr) */
+struct	sta_info *rtw_alloc_stainfo(struct	sta_priv *pstapriv, const u8 *hwaddr)
+{
+	_irqL irqL2;
+	s32	index;
+	_list	*phash_list;
+	struct sta_info	*psta;
+	_queue *pfree_sta_queue;
+	struct recv_reorder_ctrl *preorder_ctrl;
+	int i = 0;
+	u16  wRxSeqInitialValue = 0xffff;
+
+
+	pfree_sta_queue = &pstapriv->free_sta_queue;
+
+	/* _enter_critical_bh(&(pfree_sta_queue->lock), &irqL); */
+	_enter_critical_bh(&(pstapriv->sta_hash_lock), &irqL2);
+	if (_rtw_queue_empty(pfree_sta_queue) == _TRUE) {
+		/* _exit_critical_bh(&(pfree_sta_queue->lock), &irqL); */
+		_exit_critical_bh(&(pstapriv->sta_hash_lock), &irqL2);
+		psta = NULL;
+	} else {
+		psta = LIST_CONTAINOR(get_next(&pfree_sta_queue->queue), struct sta_info, list);
+
+		rtw_list_delete(&(psta->list));
+
+		/* _exit_critical_bh(&(pfree_sta_queue->lock), &irqL); */
+		_rtw_init_stainfo(psta);
+
+		psta->padapter = pstapriv->padapter;
+
+		_rtw_memcpy(psta->cmn.mac_addr, hwaddr, ETH_ALEN);
+
+		index = wifi_mac_hash(hwaddr);
+
+
+		if (index >= NUM_STA) {
+			psta = NULL;
+			goto exit;
+		}
+		phash_list = &(pstapriv->sta_hash[index]);
+
+		/* _enter_critical_bh(&(pstapriv->sta_hash_lock), &irqL2); */
+
+		rtw_list_insert_tail(&psta->hash_list, phash_list);
+
+		pstapriv->asoc_sta_count++;
+
+		/* _exit_critical_bh(&(pstapriv->sta_hash_lock), &irqL2); */
+
+		/* Commented by Albert 2009/08/13
+		 * For the SMC router, the sequence number of first packet of WPS handshake will be 0.
+		 * In this case, this packet will be dropped by recv_decache function if we use the 0x00 as the default value for tid_rxseq variable.
+		 * So, we initialize the tid_rxseq variable as the 0xffff. */
+
+		for (i = 0; i < 16; i++) {
+			_rtw_memcpy(&psta->sta_recvpriv.rxcache.tid_rxseq[i], &wRxSeqInitialValue, 2);
+			_rtw_memcpy(&psta->sta_recvpriv.bmc_tid_rxseq[i], &wRxSeqInitialValue, 2);
+			_rtw_memset(&psta->sta_recvpriv.rxcache.iv[i], 0, sizeof(psta->sta_recvpriv.rxcache.iv[i]));
+		}
+
+		rtw_init_timer(&psta->addba_retry_timer, psta->padapter, addba_timer_hdl, psta);
+#ifdef CONFIG_IEEE80211W
+		rtw_init_timer(&psta->dot11w_expire_timer, psta->padapter, sa_query_timer_hdl, psta);
+#endif /* CONFIG_IEEE80211W */
+#ifdef CONFIG_TDLS
+		rtw_init_tdls_timer(pstapriv->padapter, psta);
+#endif /* CONFIG_TDLS */
+
+		/* for A-MPDU Rx reordering buffer control */
+		for (i = 0; i < 16 ; i++) {
+			preorder_ctrl = &psta->recvreorder_ctrl[i];
+			preorder_ctrl->padapter = pstapriv->padapter;
+			preorder_ctrl->tid = i;
+			preorder_ctrl->enable = _FALSE;
+			preorder_ctrl->indicate_seq = 0xffff;
+			#ifdef DBG_RX_SEQ
+			RTW_INFO("DBG_RX_SEQ "FUNC_ADPT_FMT" tid:%u SN_CLEAR indicate_seq:%d\n"
+				, FUNC_ADPT_ARG(pstapriv->padapter), i, preorder_ctrl->indicate_seq);
+			#endif
+			preorder_ctrl->wend_b = 0xffff;
+			/* preorder_ctrl->wsize_b = (NR_RECVBUFF-2); */
+			preorder_ctrl->wsize_b = 64;/* 64; */
+			preorder_ctrl->ampdu_size = RX_AMPDU_SIZE_INVALID;
+
+			_rtw_init_queue(&preorder_ctrl->pending_recvframe_queue);
+
+			rtw_init_recv_timer(preorder_ctrl);
+		}
+
+
+		/* init for DM */
+		psta->cmn.rssi_stat.rssi = (-1);
+		psta->cmn.rssi_stat.rssi_cck = (-1);
+		psta->cmn.rssi_stat.rssi_ofdm = (-1);
+#ifdef CONFIG_ATMEL_RC_PATCH
+		psta->flag_atmel_rc = 0;
+#endif
+		/* init for the sequence number of received management frame */
+		psta->RxMgmtFrameSeqNum = 0xffff;
+		_rtw_memset(&psta->sta_stats, 0, sizeof(struct stainfo_stats));
+
+		rtw_alloc_macid(pstapriv->padapter, psta);
+
+	}
+
+exit:
+
+	_exit_critical_bh(&(pstapriv->sta_hash_lock), &irqL2);
+
+
+	if (psta)
+		rtw_mi_update_iface_status(&(pstapriv->padapter->mlmepriv), 0);
+
+	return psta;
+}
+
+
+/* using pstapriv->sta_hash_lock to protect */
+u32	rtw_free_stainfo(_adapter *padapter , struct sta_info *psta)
+{
+	int i;
+	_irqL irqL0;
+	_queue *pfree_sta_queue;
+	struct recv_reorder_ctrl *preorder_ctrl;
+	struct	sta_xmit_priv	*pstaxmitpriv;
+	struct	xmit_priv	*pxmitpriv = &padapter->xmitpriv;
+	struct	sta_priv *pstapriv = &padapter->stapriv;
+	struct hw_xmit *phwxmit;
+	struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
+	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
+
+	int pending_qcnt[4];
+	u8 is_pre_link_sta = _FALSE;
+
+	if (psta == NULL)
+		goto exit;
+
+#ifdef CONFIG_RTW_80211K
+	rm_post_event(padapter, RM_ID_FOR_ALL(psta->cmn.aid), RM_EV_cancel);
+#endif
+
+	is_pre_link_sta = rtw_is_pre_link_sta(pstapriv, psta->cmn.mac_addr);
+
+	if (is_pre_link_sta == _FALSE) {
+		_enter_critical_bh(&(pstapriv->sta_hash_lock), &irqL0);
+		rtw_list_delete(&psta->hash_list);
+		pstapriv->asoc_sta_count--;
+		_exit_critical_bh(&(pstapriv->sta_hash_lock), &irqL0);
+		rtw_mi_update_iface_status(&(padapter->mlmepriv), 0);
+	} else {
+		_enter_critical_bh(&psta->lock, &irqL0);
+		psta->state = WIFI_FW_PRE_LINK;
+		_exit_critical_bh(&psta->lock, &irqL0);
+	}
+
+	_enter_critical_bh(&psta->lock, &irqL0);
+	psta->state &= ~_FW_LINKED;
+	_exit_critical_bh(&psta->lock, &irqL0);
+
+	pfree_sta_queue = &pstapriv->free_sta_queue;
+
+
+	pstaxmitpriv = &psta->sta_xmitpriv;
+
+	/* rtw_list_delete(&psta->sleep_list); */
+
+	/* rtw_list_delete(&psta->wakeup_list); */
+
+	_enter_critical_bh(&pxmitpriv->lock, &irqL0);
+
+	rtw_free_xmitframe_queue(pxmitpriv, &psta->sleep_q);
+	psta->sleepq_len = 0;
+
+	/* vo */
+	/* _enter_critical_bh(&(pxmitpriv->vo_pending.lock), &irqL0); */
+	rtw_free_xmitframe_queue(pxmitpriv, &pstaxmitpriv->vo_q.sta_pending);
+	rtw_list_delete(&(pstaxmitpriv->vo_q.tx_pending));
+	phwxmit = pxmitpriv->hwxmits;
+	phwxmit->accnt -= pstaxmitpriv->vo_q.qcnt;
+	pending_qcnt[0] = pstaxmitpriv->vo_q.qcnt;
+	pstaxmitpriv->vo_q.qcnt = 0;
+	/* _exit_critical_bh(&(pxmitpriv->vo_pending.lock), &irqL0); */
+
+	/* vi */
+	/* _enter_critical_bh(&(pxmitpriv->vi_pending.lock), &irqL0); */
+	rtw_free_xmitframe_queue(pxmitpriv, &pstaxmitpriv->vi_q.sta_pending);
+	rtw_list_delete(&(pstaxmitpriv->vi_q.tx_pending));
+	phwxmit = pxmitpriv->hwxmits + 1;
+	phwxmit->accnt -= pstaxmitpriv->vi_q.qcnt;
+	pending_qcnt[1] = pstaxmitpriv->vi_q.qcnt;
+	pstaxmitpriv->vi_q.qcnt = 0;
+	/* _exit_critical_bh(&(pxmitpriv->vi_pending.lock), &irqL0); */
+
+	/* be */
+	/* _enter_critical_bh(&(pxmitpriv->be_pending.lock), &irqL0); */
+	rtw_free_xmitframe_queue(pxmitpriv, &pstaxmitpriv->be_q.sta_pending);
+	rtw_list_delete(&(pstaxmitpriv->be_q.tx_pending));
+	phwxmit = pxmitpriv->hwxmits + 2;
+	phwxmit->accnt -= pstaxmitpriv->be_q.qcnt;
+	pending_qcnt[2] = pstaxmitpriv->be_q.qcnt;
+	pstaxmitpriv->be_q.qcnt = 0;
+	/* _exit_critical_bh(&(pxmitpriv->be_pending.lock), &irqL0); */
+
+	/* bk */
+	/* _enter_critical_bh(&(pxmitpriv->bk_pending.lock), &irqL0); */
+	rtw_free_xmitframe_queue(pxmitpriv, &pstaxmitpriv->bk_q.sta_pending);
+	rtw_list_delete(&(pstaxmitpriv->bk_q.tx_pending));
+	phwxmit = pxmitpriv->hwxmits + 3;
+	phwxmit->accnt -= pstaxmitpriv->bk_q.qcnt;
+	pending_qcnt[3] = pstaxmitpriv->bk_q.qcnt;
+	pstaxmitpriv->bk_q.qcnt = 0;
+	/* _exit_critical_bh(&(pxmitpriv->bk_pending.lock), &irqL0); */
+
+	rtw_os_wake_queue_at_free_stainfo(padapter, pending_qcnt);
+
+	_exit_critical_bh(&pxmitpriv->lock, &irqL0);
+
+
+	/* re-init sta_info; 20061114 */ /* will be init in alloc_stainfo */
+	/* _rtw_init_sta_xmit_priv(&psta->sta_xmitpriv); */
+	/* _rtw_init_sta_recv_priv(&psta->sta_recvpriv); */
+#ifdef CONFIG_IEEE80211W
+	_cancel_timer_ex(&psta->dot11w_expire_timer);
+#endif /* CONFIG_IEEE80211W */
+	_cancel_timer_ex(&psta->addba_retry_timer);
+
+#ifdef CONFIG_TDLS
+	psta->tdls_sta_state = TDLS_STATE_NONE;
+#endif /* CONFIG_TDLS */
+
+	/* for A-MPDU Rx reordering buffer control, cancel reordering_ctrl_timer */
+	for (i = 0; i < 16 ; i++) {
+		_irqL irqL;
+		_list	*phead, *plist;
+		union recv_frame *prframe;
+		_queue *ppending_recvframe_queue;
+		_queue *pfree_recv_queue = &padapter->recvpriv.free_recv_queue;
+
+		preorder_ctrl = &psta->recvreorder_ctrl[i];
+
+		_cancel_timer_ex(&preorder_ctrl->reordering_ctrl_timer);
+
+
+		ppending_recvframe_queue = &preorder_ctrl->pending_recvframe_queue;
+
+		_enter_critical_bh(&ppending_recvframe_queue->lock, &irqL);
+
+		phead =	get_list_head(ppending_recvframe_queue);
+		plist = get_next(phead);
+
+		while (!rtw_is_list_empty(phead)) {
+			prframe = LIST_CONTAINOR(plist, union recv_frame, u);
+
+			plist = get_next(plist);
+
+			rtw_list_delete(&(prframe->u.hdr.list));
+
+			rtw_free_recvframe(prframe, pfree_recv_queue);
+		}
+
+		_exit_critical_bh(&ppending_recvframe_queue->lock, &irqL);
+
+	}
+
+	if (!((psta->state & WIFI_AP_STATE) || MacAddr_isBcst(psta->cmn.mac_addr)) && is_pre_link_sta == _FALSE)
+		rtw_hal_set_odm_var(padapter, HAL_ODM_STA_INFO, psta, _FALSE);
+
+
+	/* release mac id for non-bc/mc station, */
+	if (is_pre_link_sta == _FALSE)
+		rtw_release_macid(pstapriv->padapter, psta);
+
+#ifdef CONFIG_AP_MODE
+
+	/*
+		_enter_critical_bh(&pstapriv->asoc_list_lock, &irqL0);
+		rtw_list_delete(&psta->asoc_list);
+		_exit_critical_bh(&pstapriv->asoc_list_lock, &irqL0);
+	*/
+	_enter_critical_bh(&pstapriv->auth_list_lock, &irqL0);
+	if (!rtw_is_list_empty(&psta->auth_list)) {
+		rtw_list_delete(&psta->auth_list);
+		pstapriv->auth_list_cnt--;
+	}
+	_exit_critical_bh(&pstapriv->auth_list_lock, &irqL0);
+
+	psta->expire_to = 0;
+#ifdef CONFIG_ATMEL_RC_PATCH
+	psta->flag_atmel_rc = 0;
+#endif
+	psta->sleepq_ac_len = 0;
+	psta->qos_info = 0;
+
+	psta->max_sp_len = 0;
+	psta->uapsd_bk = 0;
+	psta->uapsd_be = 0;
+	psta->uapsd_vi = 0;
+	psta->uapsd_vo = 0;
+
+	psta->has_legacy_ac = 0;
+
+#ifdef CONFIG_NATIVEAP_MLME
+
+	if (pmlmeinfo->state == _HW_STATE_AP_) {
+		rtw_tim_map_clear(padapter, pstapriv->sta_dz_bitmap, psta->cmn.aid);
+		rtw_tim_map_clear(padapter, pstapriv->tim_bitmap, psta->cmn.aid);
+
+		/* rtw_indicate_sta_disassoc_event(padapter, psta); */
+
+		if ((psta->cmn.aid > 0) && (pstapriv->sta_aid[psta->cmn.aid - 1] == psta)) {
+			pstapriv->sta_aid[psta->cmn.aid - 1] = NULL;
+			psta->cmn.aid = 0;
+		}
+	}
+
+#endif /* CONFIG_NATIVEAP_MLME	 */
+
+#ifdef CONFIG_TX_MCAST2UNI
+	psta->under_exist_checking = 0;
+#endif /* CONFIG_TX_MCAST2UNI */
+
+#endif /* CONFIG_AP_MODE	 */
+
+	rtw_st_ctl_deinit(&psta->st_ctl);
+
+	if (is_pre_link_sta == _FALSE) {
+		_rtw_spinlock_free(&psta->lock);
+
+		/* _enter_critical_bh(&(pfree_sta_queue->lock), &irqL0); */
+		_enter_critical_bh(&(pstapriv->sta_hash_lock), &irqL0);
+		rtw_list_insert_tail(&psta->list, get_list_head(pfree_sta_queue));
+		_exit_critical_bh(&(pstapriv->sta_hash_lock), &irqL0);
+		/* _exit_critical_bh(&(pfree_sta_queue->lock), &irqL0); */
+	}
+
+exit:
+	return _SUCCESS;
+}
+
+/* free all stainfo which in sta_hash[all] */
+void rtw_free_all_stainfo(_adapter *padapter)
+{
+	_irqL	 irqL;
+	_list	*plist, *phead;
+	s32	index;
+	struct sta_info *psta = NULL;
+	struct	sta_priv *pstapriv = &padapter->stapriv;
+	struct sta_info *pbcmc_stainfo = rtw_get_bcmc_stainfo(padapter);
+	u8 free_sta_num = 0;
+	char free_sta_list[NUM_STA];
+	int stainfo_offset;
+
+
+	if (pstapriv->asoc_sta_count == 1)
+		goto exit;
+
+	_enter_critical_bh(&pstapriv->sta_hash_lock, &irqL);
+
+	for (index = 0; index < NUM_STA; index++) {
+		phead = &(pstapriv->sta_hash[index]);
+		plist = get_next(phead);
+
+		while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) {
+			psta = LIST_CONTAINOR(plist, struct sta_info , hash_list);
+
+			plist = get_next(plist);
+
+			if (pbcmc_stainfo != psta) {
+				if (rtw_is_pre_link_sta(pstapriv, psta->cmn.mac_addr) == _FALSE)
+					rtw_list_delete(&psta->hash_list);
+
+				stainfo_offset = rtw_stainfo_offset(pstapriv, psta);
+				if (stainfo_offset_valid(stainfo_offset))
+					free_sta_list[free_sta_num++] = stainfo_offset;
+			}
+
+		}
+	}
+
+	_exit_critical_bh(&pstapriv->sta_hash_lock, &irqL);
+
+
+	for (index = 0; index < free_sta_num; index++) {
+		psta = rtw_get_stainfo_by_offset(pstapriv, free_sta_list[index]);
+		rtw_free_stainfo(padapter , psta);
+	}
+
+exit:
+	return;
+}
+
+/* any station allocated can be searched by hash list */
+struct sta_info *rtw_get_stainfo(struct sta_priv *pstapriv, const u8 *hwaddr)
+{
+
+	_irqL	 irqL;
+
+	_list	*plist, *phead;
+
+	struct sta_info *psta = NULL;
+
+	u32	index;
+
+	const u8 *addr;
+
+	u8 bc_addr[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
+
+
+	if (hwaddr == NULL)
+		return NULL;
+
+	if (IS_MCAST(hwaddr))
+		addr = bc_addr;
+	else
+		addr = hwaddr;
+
+	index = wifi_mac_hash(addr);
+
+	_enter_critical_bh(&pstapriv->sta_hash_lock, &irqL);
+
+	phead = &(pstapriv->sta_hash[index]);
+	plist = get_next(phead);
+
+
+	while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) {
+
+		psta = LIST_CONTAINOR(plist, struct sta_info, hash_list);
+
+		if ((_rtw_memcmp(psta->cmn.mac_addr, addr, ETH_ALEN)) == _TRUE) {
+			/* if found the matched address */
+			break;
+		}
+		psta = NULL;
+		plist = get_next(plist);
+	}
+
+	_exit_critical_bh(&pstapriv->sta_hash_lock, &irqL);
+	return psta;
+
+}
+
+u32 rtw_init_bcmc_stainfo(_adapter *padapter)
+{
+
+	struct sta_info	*psta;
+	struct tx_servq	*ptxservq;
+	u32 res = _SUCCESS;
+	NDIS_802_11_MAC_ADDRESS	bcast_addr = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
+
+	struct	sta_priv *pstapriv = &padapter->stapriv;
+	/* _queue	*pstapending = &padapter->xmitpriv.bm_pending; */
+
+
+	psta = rtw_alloc_stainfo(pstapriv, bcast_addr);
+
+	if (psta == NULL) {
+		res = _FAIL;
+		goto exit;
+	}
+#ifdef CONFIG_BEAMFORMING
+	psta->cmn.bf_info.g_id = 63;
+	psta->cmn.bf_info.p_aid = 0;
+#endif
+
+	ptxservq = &(psta->sta_xmitpriv.be_q);
+
+	/*
+		_enter_critical(&pstapending->lock, &irqL0);
+
+		if (rtw_is_list_empty(&ptxservq->tx_pending))
+			rtw_list_insert_tail(&ptxservq->tx_pending, get_list_head(pstapending));
+
+		_exit_critical(&pstapending->lock, &irqL0);
+	*/
+
+exit:
+	return _SUCCESS;
+
+}
+
+
+struct sta_info *rtw_get_bcmc_stainfo(_adapter *padapter)
+{
+	struct sta_info	*psta;
+	struct sta_priv	*pstapriv = &padapter->stapriv;
+	u8 bc_addr[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
+	psta = rtw_get_stainfo(pstapriv, bc_addr);
+	return psta;
+
+}
+
+#ifdef CONFIG_AP_MODE
+u16 rtw_aid_alloc(_adapter *adapter, struct sta_info *sta)
+{
+	struct sta_priv *stapriv = &adapter->stapriv;
+	u16 aid, i, used_cnt = 0;
+
+	for (i = 0; i < stapriv->max_aid; i++) {
+		aid = ((i + stapriv->started_aid - 1) % stapriv->max_aid) + 1;
+		if (stapriv->sta_aid[aid - 1] == NULL)
+			break;
+		if (++used_cnt >= stapriv->max_num_sta)
+			break;
+	}
+
+	/* check for aid limit and assoc limit  */
+	if (i >= stapriv->max_aid || used_cnt >= stapriv->max_num_sta)
+		aid = 0;
+
+	sta->cmn.aid = aid;
+	if (aid) {
+		stapriv->sta_aid[aid - 1] = sta;
+		if (stapriv->rr_aid)
+			stapriv->started_aid = (aid % stapriv->max_aid) + 1;
+	}
+
+	return aid;
+}
+
+void dump_aid_status(void *sel, _adapter *adapter)
+{
+	struct sta_priv *stapriv = &adapter->stapriv;
+	u8 *aid_bmp;
+	u16 i, used_cnt = 0;
+
+	aid_bmp = rtw_zmalloc(stapriv->aid_bmp_len);
+	if (!aid_bmp)
+		return;
+
+	for (i = 1; i <= stapriv->max_aid; i++) {
+		if (stapriv->sta_aid[i - 1]) {
+			aid_bmp[i / 8] |= BIT(i % 8);
+			++used_cnt;
+		}
+	}
+
+	RTW_PRINT_SEL(sel, "used_cnt:%u/%u\n", used_cnt, stapriv->max_aid);
+	RTW_MAP_DUMP_SEL(sel, "aid_map:", aid_bmp, stapriv->aid_bmp_len);
+	RTW_PRINT_SEL(sel, "\n");
+
+	RTW_PRINT_SEL(sel, "%-2s %-11s\n", "rr", "started_aid");
+	RTW_PRINT_SEL(sel, "%2d %11d\n", stapriv->rr_aid, stapriv->started_aid);
+
+	rtw_mfree(aid_bmp, stapriv->aid_bmp_len);
+}
+#endif /* CONFIG_AP_MODE */
+
+#if CONFIG_RTW_MACADDR_ACL
+const char *const _acl_period_str[RTW_ACL_PERIOD_NUM] = {
+	"DEV",
+	"BSS",
+};
+
+const char *const _acl_mode_str[RTW_ACL_MODE_MAX] = {
+	"DISABLED",
+	"ACCEPT_UNLESS_LISTED",
+	"DENY_UNLESS_LISTED",
+};
+
+u8 _rtw_access_ctrl(_adapter *adapter, u8 period, const u8 *mac_addr)
+{
+	u8 res = _TRUE;
+	_irqL irqL;
+	_list *list, *head;
+	struct rtw_wlan_acl_node *acl_node;
+	u8 match = _FALSE;
+	struct sta_priv *stapriv = &adapter->stapriv;
+	struct wlan_acl_pool *acl;
+	_queue	*acl_node_q;
+
+	if (period >= RTW_ACL_PERIOD_NUM) {
+		rtw_warn_on(1);
+		goto exit;
+	}
+
+	acl = &stapriv->acl_list[period];
+	acl_node_q = &acl->acl_node_q;
+
+	if (acl->mode != RTW_ACL_MODE_ACCEPT_UNLESS_LISTED
+		&& acl->mode != RTW_ACL_MODE_DENY_UNLESS_LISTED)
+		goto exit;
+
+	_enter_critical_bh(&(acl_node_q->lock), &irqL);
+	head = get_list_head(acl_node_q);
+	list = get_next(head);
+	while (rtw_end_of_queue_search(head, list) == _FALSE) {
+		acl_node = LIST_CONTAINOR(list, struct rtw_wlan_acl_node, list);
+		list = get_next(list);
+
+		if (_rtw_memcmp(acl_node->addr, mac_addr, ETH_ALEN)) {
+			if (acl_node->valid == _TRUE) {
+				match = _TRUE;
+				break;
+			}
+		}
+	}
+	_exit_critical_bh(&(acl_node_q->lock), &irqL);
+
+	if (acl->mode == RTW_ACL_MODE_ACCEPT_UNLESS_LISTED)
+		res = (match == _TRUE) ?  _FALSE : _TRUE;
+	else /* RTW_ACL_MODE_DENY_UNLESS_LISTED */
+		res = (match == _TRUE) ?  _TRUE : _FALSE;
+
+exit:
+	return res;
+}
+
+u8 rtw_access_ctrl(_adapter *adapter, const u8 *mac_addr)
+{
+	int i;
+
+	for (i = 0; i < RTW_ACL_PERIOD_NUM; i++)
+		if (_rtw_access_ctrl(adapter, i, mac_addr) == _FALSE)
+			return _FALSE;
+
+	return _TRUE;
+}
+
+void dump_macaddr_acl(void *sel, _adapter *adapter)
+{
+	struct sta_priv *stapriv = &adapter->stapriv;
+	struct wlan_acl_pool *acl;
+	int i, j;
+
+	for (j = 0; j < RTW_ACL_PERIOD_NUM; j++) {
+		RTW_PRINT_SEL(sel, "period:%s(%d)\n", acl_period_str(j), j);
+
+		acl = &stapriv->acl_list[j];
+		RTW_PRINT_SEL(sel, "mode:%s(%d)\n", acl_mode_str(acl->mode), acl->mode);
+		RTW_PRINT_SEL(sel, "num:%d/%d\n", acl->num, NUM_ACL);
+		for (i = 0; i < NUM_ACL; i++) {
+			if (acl->aclnode[i].valid == _FALSE)
+				continue;
+			RTW_PRINT_SEL(sel, MAC_FMT"\n", MAC_ARG(acl->aclnode[i].addr));
+		}
+		RTW_PRINT_SEL(sel, "\n");
+	}
+}
+#endif /* CONFIG_RTW_MACADDR_ACL */
+
+bool rtw_is_pre_link_sta(struct sta_priv *stapriv, u8 *addr)
+{
+#if CONFIG_RTW_PRE_LINK_STA
+	struct pre_link_sta_ctl_t *pre_link_sta_ctl = &stapriv->pre_link_sta_ctl;
+	struct sta_info *sta = NULL;
+	u8 exist = _FALSE;
+	int i;
+	_irqL irqL;
+
+	_enter_critical_bh(&(pre_link_sta_ctl->lock), &irqL);
+	for (i = 0; i < RTW_PRE_LINK_STA_NUM; i++) {
+		if (pre_link_sta_ctl->node[i].valid == _TRUE
+			&& _rtw_memcmp(pre_link_sta_ctl->node[i].addr, addr, ETH_ALEN) == _TRUE
+		) {
+			exist = _TRUE;
+			break;
+		}
+	}
+	_exit_critical_bh(&(pre_link_sta_ctl->lock), &irqL);
+
+	return exist;
+#else
+	return _FALSE;
+#endif
+}
+
+#if CONFIG_RTW_PRE_LINK_STA
+struct sta_info *rtw_pre_link_sta_add(struct sta_priv *stapriv, u8 *hwaddr)
+{
+	struct pre_link_sta_ctl_t *pre_link_sta_ctl = &stapriv->pre_link_sta_ctl;
+	struct pre_link_sta_node_t *node = NULL;
+	struct sta_info *sta = NULL;
+	u8 exist = _FALSE;
+	int i;
+	_irqL irqL;
+
+	if (rtw_check_invalid_mac_address(hwaddr, _FALSE) == _TRUE)
+		goto exit;
+
+	_enter_critical_bh(&(pre_link_sta_ctl->lock), &irqL);
+	for (i = 0; i < RTW_PRE_LINK_STA_NUM; i++) {
+		if (pre_link_sta_ctl->node[i].valid == _TRUE
+			&& _rtw_memcmp(pre_link_sta_ctl->node[i].addr, hwaddr, ETH_ALEN) == _TRUE
+		) {
+			node = &pre_link_sta_ctl->node[i];
+			exist = _TRUE;
+			break;
+		}
+
+		if (node == NULL && pre_link_sta_ctl->node[i].valid == _FALSE)
+			node = &pre_link_sta_ctl->node[i];
+	}
+
+	if (exist == _FALSE && node) {
+		_rtw_memcpy(node->addr, hwaddr, ETH_ALEN);
+		node->valid = _TRUE;
+		pre_link_sta_ctl->num++;
+	}
+	_exit_critical_bh(&(pre_link_sta_ctl->lock), &irqL);
+
+	if (node == NULL)
+		goto exit;
+
+	sta = rtw_get_stainfo(stapriv, hwaddr);
+	if (sta)
+		goto odm_hook;
+
+	sta = rtw_alloc_stainfo(stapriv, hwaddr);
+	if (!sta)
+		goto exit;
+
+	sta->state = WIFI_FW_PRE_LINK;
+
+odm_hook:
+	rtw_hal_set_odm_var(stapriv->padapter, HAL_ODM_STA_INFO, sta, _TRUE);
+
+exit:
+	return sta;
+}
+
+void rtw_pre_link_sta_del(struct sta_priv *stapriv, u8 *hwaddr)
+{
+	struct pre_link_sta_ctl_t *pre_link_sta_ctl = &stapriv->pre_link_sta_ctl;
+	struct pre_link_sta_node_t *node = NULL;
+	struct sta_info *sta = NULL;
+	u8 exist = _FALSE;
+	int i;
+	_irqL irqL;
+
+	if (rtw_check_invalid_mac_address(hwaddr, _FALSE) == _TRUE)
+		goto exit;
+
+	_enter_critical_bh(&(pre_link_sta_ctl->lock), &irqL);
+	for (i = 0; i < RTW_PRE_LINK_STA_NUM; i++) {
+		if (pre_link_sta_ctl->node[i].valid == _TRUE
+			&& _rtw_memcmp(pre_link_sta_ctl->node[i].addr, hwaddr, ETH_ALEN) == _TRUE
+		) {
+			node = &pre_link_sta_ctl->node[i];
+			exist = _TRUE;
+			break;
+		}
+	}
+
+	if (exist == _TRUE && node) {
+		node->valid = _FALSE;
+		pre_link_sta_ctl->num--;
+	}
+	_exit_critical_bh(&(pre_link_sta_ctl->lock), &irqL);
+
+	if (exist == _FALSE)
+		goto exit;
+
+	sta = rtw_get_stainfo(stapriv, hwaddr);
+	if (!sta)
+		goto exit;
+
+	if (sta->state == WIFI_FW_PRE_LINK)
+		rtw_free_stainfo(stapriv->padapter, sta);
+
+exit:
+	return;
+}
+
+void rtw_pre_link_sta_ctl_reset(struct sta_priv *stapriv)
+{
+	struct pre_link_sta_ctl_t *pre_link_sta_ctl = &stapriv->pre_link_sta_ctl;
+	struct pre_link_sta_node_t *node = NULL;
+	struct sta_info *sta = NULL;
+	int i, j = 0;
+	_irqL irqL;
+
+	u8 addrs[RTW_PRE_LINK_STA_NUM][ETH_ALEN];
+
+	_rtw_memset(addrs, 0, RTW_PRE_LINK_STA_NUM * ETH_ALEN);
+
+	_enter_critical_bh(&(pre_link_sta_ctl->lock), &irqL);
+	for (i = 0; i < RTW_PRE_LINK_STA_NUM; i++) {
+		if (pre_link_sta_ctl->node[i].valid == _FALSE)
+			continue;
+		_rtw_memcpy(&(addrs[j][0]), pre_link_sta_ctl->node[i].addr, ETH_ALEN);
+		pre_link_sta_ctl->node[i].valid = _FALSE;
+		pre_link_sta_ctl->num--;
+		j++;
+	}
+	_exit_critical_bh(&(pre_link_sta_ctl->lock), &irqL);
+
+	for (i = 0; i < j; i++) {
+		sta = rtw_get_stainfo(stapriv, &(addrs[i][0]));
+		if (!sta)
+			continue;
+
+		if (sta->state == WIFI_FW_PRE_LINK)
+			rtw_free_stainfo(stapriv->padapter, sta);
+	}
+}
+
+void rtw_pre_link_sta_ctl_init(struct sta_priv *stapriv)
+{
+	struct pre_link_sta_ctl_t *pre_link_sta_ctl = &stapriv->pre_link_sta_ctl;
+	int i;
+
+	_rtw_spinlock_init(&pre_link_sta_ctl->lock);
+	pre_link_sta_ctl->num = 0;
+	for (i = 0; i < RTW_PRE_LINK_STA_NUM; i++)
+		pre_link_sta_ctl->node[i].valid = _FALSE;
+}
+
+void rtw_pre_link_sta_ctl_deinit(struct sta_priv *stapriv)
+{
+	struct pre_link_sta_ctl_t *pre_link_sta_ctl = &stapriv->pre_link_sta_ctl;
+	int i;
+
+	rtw_pre_link_sta_ctl_reset(stapriv);
+
+	_rtw_spinlock_free(&pre_link_sta_ctl->lock);
+}
+
+void dump_pre_link_sta_ctl(void *sel, struct sta_priv *stapriv)
+{
+	struct pre_link_sta_ctl_t *pre_link_sta_ctl = &stapriv->pre_link_sta_ctl;
+	int i;
+
+	RTW_PRINT_SEL(sel, "num:%d/%d\n", pre_link_sta_ctl->num, RTW_PRE_LINK_STA_NUM);
+
+	for (i = 0; i < RTW_PRE_LINK_STA_NUM; i++) {
+		if (pre_link_sta_ctl->node[i].valid == _FALSE)
+			continue;
+		RTW_PRINT_SEL(sel, MAC_FMT"\n", MAC_ARG(pre_link_sta_ctl->node[i].addr));
+	}
+}
+#endif /* CONFIG_RTW_PRE_LINK_STA */
+
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/core/rtw_tdls.c linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/core/rtw_tdls.c
--- linux-5.6.3/3rdparty/rtl8821ce/core/rtw_tdls.c	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/core/rtw_tdls.c	2020-04-10 16:35:06.779658341 +0300
@@ -0,0 +1,3505 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#define _RTW_TDLS_C_
+
+#include <drv_types.h>
+#include <hal_data.h>
+
+#ifdef CONFIG_TDLS
+#define ONE_SEC 	1000 /* 1000 ms */
+
+extern unsigned char MCS_rate_2R[16];
+extern unsigned char MCS_rate_1R[16];
+
+inline void rtw_tdls_set_link_established(_adapter *adapter, bool en)
+{
+	adapter->tdlsinfo.link_established = en;
+	rtw_mi_update_iface_status(&(adapter->mlmepriv), 0);
+}
+
+void rtw_reset_tdls_info(_adapter *padapter)
+{
+	struct tdls_info *ptdlsinfo = &padapter->tdlsinfo;
+
+	ptdlsinfo->ap_prohibited = _FALSE;
+
+	/* For TDLS channel switch, currently we only allow it to work in wifi logo test mode */
+	if (padapter->registrypriv.wifi_spec == 1)
+		ptdlsinfo->ch_switch_prohibited = _FALSE;
+	else
+		ptdlsinfo->ch_switch_prohibited = _TRUE;
+
+	rtw_tdls_set_link_established(padapter, _FALSE);
+	ptdlsinfo->sta_cnt = 0;
+	ptdlsinfo->sta_maximum = _FALSE;
+
+#ifdef CONFIG_TDLS_CH_SW
+	ptdlsinfo->chsw_info.ch_sw_state = TDLS_STATE_NONE;
+	ATOMIC_SET(&ptdlsinfo->chsw_info.chsw_on, _FALSE);
+	ptdlsinfo->chsw_info.off_ch_num = 0;
+	ptdlsinfo->chsw_info.ch_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
+	ptdlsinfo->chsw_info.cur_time = 0;
+	ptdlsinfo->chsw_info.delay_switch_back = _FALSE;
+	ptdlsinfo->chsw_info.dump_stack = _FALSE;
+#endif
+
+	ptdlsinfo->ch_sensing = 0;
+	ptdlsinfo->watchdog_count = 0;
+	ptdlsinfo->dev_discovered = _FALSE;
+
+#ifdef CONFIG_WFD
+	ptdlsinfo->wfd_info = &padapter->wfd_info;
+#endif
+
+	ptdlsinfo->tdls_sctx = NULL;
+}
+
+int rtw_init_tdls_info(_adapter *padapter)
+{
+	int	res = _SUCCESS;
+	struct tdls_info *ptdlsinfo = &padapter->tdlsinfo;
+
+	rtw_reset_tdls_info(padapter);
+
+#ifdef CONFIG_TDLS_DRIVER_SETUP
+	ptdlsinfo->driver_setup = _TRUE;
+#else
+	ptdlsinfo->driver_setup = _FALSE;
+#endif /* CONFIG_TDLS_DRIVER_SETUP */
+
+	_rtw_spinlock_init(&ptdlsinfo->cmd_lock);
+	_rtw_spinlock_init(&ptdlsinfo->hdl_lock);
+
+	return res;
+
+}
+
+void rtw_free_tdls_info(struct tdls_info *ptdlsinfo)
+{
+	_rtw_spinlock_free(&ptdlsinfo->cmd_lock);
+	_rtw_spinlock_free(&ptdlsinfo->hdl_lock);
+
+	_rtw_memset(ptdlsinfo, 0, sizeof(struct tdls_info));
+
+}
+
+void rtw_free_all_tdls_sta(_adapter *padapter, u8 enqueue_cmd)
+{
+	struct sta_priv *pstapriv = &padapter->stapriv;
+	struct tdls_info *ptdlsinfo = &padapter->tdlsinfo;
+	_irqL	 irqL;
+	_list	*plist, *phead;
+	s32	index;
+	struct sta_info *psta = NULL;
+	struct sta_info *ptdls_sta[NUM_STA];
+	u8 empty_hwaddr[ETH_ALEN] = { 0x00 };
+
+	_rtw_memset(ptdls_sta, 0x00, sizeof(ptdls_sta));
+
+	_enter_critical_bh(&pstapriv->sta_hash_lock, &irqL);
+	for (index = 0; index < NUM_STA; index++) {
+		phead = &(pstapriv->sta_hash[index]);
+		plist = get_next(phead);
+
+		while (rtw_end_of_queue_search(phead, plist) == _FALSE) {
+			psta = LIST_CONTAINOR(plist, struct sta_info, hash_list);
+
+			plist = get_next(plist);
+
+			if (psta->tdls_sta_state != TDLS_STATE_NONE)
+				ptdls_sta[index] = psta;
+		}
+	}
+	_exit_critical_bh(&pstapriv->sta_hash_lock, &irqL);
+
+	for (index = 0; index < NUM_STA; index++) {
+		if (ptdls_sta[index]) {
+			struct TDLSoption_param tdls_param;
+
+			psta = ptdls_sta[index];
+
+			RTW_INFO("Do tear down to "MAC_FMT" by enqueue_cmd = %d\n", MAC_ARG(psta->cmn.mac_addr), enqueue_cmd);
+
+			_rtw_memcpy(&(tdls_param.addr), psta->cmn.mac_addr, ETH_ALEN);
+			tdls_param.option = TDLS_TEARDOWN_STA_NO_WAIT;
+			tdls_hdl(padapter, (unsigned char *)&(tdls_param));
+
+			rtw_tdls_teardown_pre_hdl(padapter, psta);
+
+			if (enqueue_cmd == _TRUE)
+				rtw_tdls_cmd(padapter, psta->cmn.mac_addr, TDLS_TEARDOWN_STA_LOCALLY_POST);
+			else
+			 {
+				tdls_param.option = TDLS_TEARDOWN_STA_LOCALLY_POST;
+				tdls_hdl(padapter, (unsigned char *)&(tdls_param));
+			}
+		}
+	}
+}
+
+int check_ap_tdls_prohibited(u8 *pframe, u8 pkt_len)
+{
+	u8 tdls_prohibited_bit = 0x40; /* bit(38); TDLS_prohibited */
+
+	if (pkt_len < 5)
+		return _FALSE;
+
+	pframe += 4;
+	if ((*pframe) & tdls_prohibited_bit)
+		return _TRUE;
+
+	return _FALSE;
+}
+
+int check_ap_tdls_ch_switching_prohibited(u8 *pframe, u8 pkt_len)
+{
+	u8 tdls_ch_swithcing_prohibited_bit = 0x80; /* bit(39); TDLS_channel_switching prohibited */
+
+	if (pkt_len < 5)
+		return _FALSE;
+
+	pframe += 4;
+	if ((*pframe) & tdls_ch_swithcing_prohibited_bit)
+		return _TRUE;
+
+	return _FALSE;
+}
+
+u8 rtw_is_tdls_enabled(_adapter *padapter)
+{
+	return padapter->registrypriv.en_tdls;
+}
+
+void rtw_set_tdls_enable(_adapter *padapter, u8 enable)
+{
+	padapter->registrypriv.en_tdls = enable;
+	RTW_INFO("%s: en_tdls = %d\n", __func__, rtw_is_tdls_enabled(padapter));
+}
+
+void rtw_enable_tdls_func(_adapter *padapter)
+{
+	if (rtw_is_tdls_enabled(padapter) == _TRUE)
+		return;
+
+#if 0
+#ifdef CONFIG_MCC_MODE
+	if (rtw_hal_check_mcc_status(padapter, MCC_STATUS_DOING_MCC) == _TRUE) {
+		RTW_INFO("[TDLS] MCC is running, can't enable TDLS !\n");
+		return;
+	}
+#endif
+#endif
+	rtw_set_tdls_enable(padapter, _TRUE);
+}
+
+void rtw_disable_tdls_func(_adapter *padapter, u8 enqueue_cmd)
+{
+	if (rtw_is_tdls_enabled(padapter) == _FALSE)
+		return;
+
+	rtw_free_all_tdls_sta(padapter, enqueue_cmd);
+	rtw_tdls_cmd(padapter, NULL, TDLS_RS_RCR);
+	rtw_reset_tdls_info(padapter);
+
+	rtw_set_tdls_enable(padapter, _FALSE);
+}
+
+u8 rtw_is_tdls_sta_existed(_adapter *padapter)
+{
+	struct sta_priv *pstapriv = &padapter->stapriv;
+	struct sta_info *psta;
+	int i = 0;
+	_irqL irqL;
+	_list	*plist, *phead;
+	u8 ret = _FALSE;
+
+	if (rtw_is_tdls_enabled(padapter) == _FALSE)
+		return _FALSE;
+
+	_enter_critical_bh(&pstapriv->sta_hash_lock, &irqL);
+
+	for (i = 0; i < NUM_STA; i++) {
+		phead = &(pstapriv->sta_hash[i]);
+		plist = get_next(phead);
+		while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) {
+			psta = LIST_CONTAINOR(plist, struct sta_info, hash_list);
+			plist = get_next(plist);
+			if (psta->tdls_sta_state != TDLS_STATE_NONE) {
+				ret = _TRUE;
+				goto Exit;
+			}
+		}
+	}
+
+Exit:
+
+	_exit_critical_bh(&pstapriv->sta_hash_lock, &irqL);
+
+	return ret;
+}
+
+u8 rtw_tdls_is_setup_allowed(_adapter *padapter)
+{
+	struct tdls_info *ptdlsinfo = &padapter->tdlsinfo;
+
+	if (is_client_associated_to_ap(padapter) == _FALSE)
+		return _FALSE;
+
+	if (ptdlsinfo->ap_prohibited == _TRUE)
+		return _FALSE;
+
+	return _TRUE;
+}
+
+#ifdef CONFIG_TDLS_CH_SW
+u8 rtw_tdls_is_chsw_allowed(_adapter *padapter)
+{
+	struct tdls_info *ptdlsinfo = &padapter->tdlsinfo;
+
+	if (ptdlsinfo->ch_switch_prohibited == _TRUE)
+		return _FALSE;
+
+	if (padapter->registrypriv.wifi_spec == 0)
+		return _FALSE;
+
+	return _TRUE;
+}
+#endif
+
+int _issue_nulldata_to_TDLS_peer_STA(_adapter *padapter, unsigned char *da, unsigned int power_mode, int wait_ms)
+{
+	int ret = _FAIL;
+	struct xmit_frame			*pmgntframe;
+	struct pkt_attrib			*pattrib;
+	unsigned char					*pframe;
+	struct rtw_ieee80211_hdr	*pwlanhdr;
+	unsigned short				*fctrl, *qc;
+	struct xmit_priv			*pxmitpriv = &(padapter->xmitpriv);
+	struct mlme_ext_priv	*pmlmeext = &(padapter->mlmeextpriv);
+	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
+
+	pmgntframe = alloc_mgtxmitframe(pxmitpriv);
+	if (pmgntframe == NULL)
+		goto exit;
+
+	pattrib = &pmgntframe->attrib;
+	update_mgntframe_attrib(padapter, pattrib);
+
+	pattrib->hdrlen += 2;
+	pattrib->qos_en = _TRUE;
+	pattrib->eosp = 1;
+	pattrib->ack_policy = 0;
+	pattrib->mdata = 0;
+	pattrib->retry_ctrl = _FALSE;
+
+	_rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET);
+
+	pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET;
+	pwlanhdr = (struct rtw_ieee80211_hdr *)pframe;
+
+	fctrl = &(pwlanhdr->frame_ctl);
+	*(fctrl) = 0;
+
+	if (power_mode)
+		SetPwrMgt(fctrl);
+
+	qc = (unsigned short *)(pframe + pattrib->hdrlen - 2);
+
+	SetPriority(qc, 7);	/* Set priority to VO */
+
+	SetEOSP(qc, pattrib->eosp);
+
+	SetAckpolicy(qc, pattrib->ack_policy);
+
+	_rtw_memcpy(pwlanhdr->addr1, da, ETH_ALEN);
+	_rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN);
+	_rtw_memcpy(pwlanhdr->addr3, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN);
+
+	SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq);
+	pmlmeext->mgnt_seq++;
+	set_frame_sub_type(pframe, WIFI_QOS_DATA_NULL);
+
+	pframe += sizeof(struct rtw_ieee80211_hdr_3addr_qos);
+	pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr_qos);
+
+	pattrib->last_txcmdsz = pattrib->pktlen;
+
+	if (wait_ms)
+		ret = dump_mgntframe_and_wait_ack_timeout(padapter, pmgntframe, wait_ms);
+	else {
+		dump_mgntframe(padapter, pmgntframe);
+		ret = _SUCCESS;
+	}
+
+exit:
+	return ret;
+
+}
+
+/*
+ *wait_ms == 0 means that there is no need to wait ack through C2H_CCX_TX_RPT
+ *wait_ms > 0 means you want to wait ack through C2H_CCX_TX_RPT, and the value of wait_ms means the interval between each TX
+ *try_cnt means the maximal TX count to try
+ */
+int issue_nulldata_to_TDLS_peer_STA(_adapter *padapter, unsigned char *da, unsigned int power_mode, int try_cnt, int wait_ms)
+{
+	int ret;
+	int i = 0;
+	systime start = rtw_get_current_time();
+	struct mlme_ext_priv	*pmlmeext = &(padapter->mlmeextpriv);
+	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
+
+#if 0
+	psta = rtw_get_stainfo(&padapter->stapriv, da);
+	if (psta) {
+		if (power_mode)
+			rtw_hal_macid_sleep(padapter, psta->cmn.mac_id);
+		else
+			rtw_hal_macid_wakeup(padapter, psta->cmn.mac_id);
+	} else {
+		RTW_INFO(FUNC_ADPT_FMT ": Can't find sta info for " MAC_FMT ", skip macid %s!!\n",
+			FUNC_ADPT_ARG(padapter), MAC_ARG(da), power_mode ? "sleep" : "wakeup");
+		rtw_warn_on(1);
+	}
+#endif
+
+	do {
+		ret = _issue_nulldata_to_TDLS_peer_STA(padapter, da, power_mode, wait_ms);
+
+		i++;
+
+		if (RTW_CANNOT_RUN(padapter))
+			break;
+
+		if (i < try_cnt && wait_ms > 0 && ret == _FAIL)
+			rtw_msleep_os(wait_ms);
+
+	} while ((i < try_cnt) && (ret == _FAIL || wait_ms == 0));
+
+	if (ret != _FAIL) {
+		ret = _SUCCESS;
+#ifndef DBG_XMIT_ACK
+		goto exit;
+#endif
+	}
+
+	if (try_cnt && wait_ms) {
+		if (da)
+			RTW_INFO(FUNC_ADPT_FMT" to "MAC_FMT", ch:%u%s, %d/%d in %u ms\n",
+				FUNC_ADPT_ARG(padapter), MAC_ARG(da), rtw_get_oper_ch(padapter),
+				ret == _SUCCESS ? ", acked" : "", i, try_cnt, rtw_get_passing_time_ms(start));
+		else
+			RTW_INFO(FUNC_ADPT_FMT", ch:%u%s, %d/%d in %u ms\n",
+				FUNC_ADPT_ARG(padapter), rtw_get_oper_ch(padapter),
+				ret == _SUCCESS ? ", acked" : "", i, try_cnt, rtw_get_passing_time_ms(start));
+	}
+exit:
+	return ret;
+}
+
+/* TDLS encryption(if needed) will always be CCMP */
+void rtw_tdls_set_key(_adapter *padapter, struct sta_info *ptdls_sta)
+{
+	ptdls_sta->dot118021XPrivacy = _AES_;
+	rtw_setstakey_cmd(padapter, ptdls_sta, TDLS_KEY, _TRUE);
+}
+
+#ifdef CONFIG_80211N_HT
+void rtw_tdls_process_ht_cap(_adapter *padapter, struct sta_info *ptdls_sta, u8 *data, u8 Length)
+{
+	struct mlme_ext_priv	*pmlmeext = &padapter->mlmeextpriv;
+	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
+	struct mlme_priv		*pmlmepriv = &padapter->mlmepriv;
+	struct ht_priv			*phtpriv = &pmlmepriv->htpriv;
+	u8	max_AMPDU_len, min_MPDU_spacing;
+	u8	cur_ldpc_cap = 0, cur_stbc_cap = 0, cur_beamform_cap = 0;
+
+	/* Save HT capabilities in the sta object */
+	_rtw_memset(&ptdls_sta->htpriv.ht_cap, 0, sizeof(struct rtw_ieee80211_ht_cap));
+	if (data && Length >= sizeof(struct rtw_ieee80211_ht_cap)) {
+		ptdls_sta->flags |= WLAN_STA_HT;
+		ptdls_sta->flags |= WLAN_STA_WME;
+
+		_rtw_memcpy(&ptdls_sta->htpriv.ht_cap, data, sizeof(struct rtw_ieee80211_ht_cap));
+	} else {
+		ptdls_sta->flags &= ~WLAN_STA_HT;
+		return;
+	}
+
+	if (ptdls_sta->flags & WLAN_STA_HT) {
+		if (padapter->registrypriv.ht_enable == _TRUE && is_supported_ht(padapter->registrypriv.wireless_mode) ) {
+			ptdls_sta->htpriv.ht_option = _TRUE;
+			ptdls_sta->qos_option = _TRUE;
+		} else {
+			ptdls_sta->htpriv.ht_option = _FALSE;
+			ptdls_sta->qos_option = _FALSE;
+		}
+	}
+
+	/* HT related cap */
+	if (ptdls_sta->htpriv.ht_option) {
+		/* Check if sta supports rx ampdu */
+		if (padapter->registrypriv.ampdu_enable == 1)
+			ptdls_sta->htpriv.ampdu_enable = _TRUE;
+
+		/* AMPDU Parameters field */
+		/* Get MIN of MAX AMPDU Length Exp */
+		if ((pmlmeinfo->HT_caps.u.HT_cap_element.AMPDU_para & 0x3) > (data[2] & 0x3))
+			max_AMPDU_len = (data[2] & 0x3);
+		else
+			max_AMPDU_len = (pmlmeinfo->HT_caps.u.HT_cap_element.AMPDU_para & 0x3);
+		/* Get MAX of MIN MPDU Start Spacing */
+		if ((pmlmeinfo->HT_caps.u.HT_cap_element.AMPDU_para & 0x1c) > (data[2] & 0x1c))
+			min_MPDU_spacing = (pmlmeinfo->HT_caps.u.HT_cap_element.AMPDU_para & 0x1c);
+		else
+			min_MPDU_spacing = (data[2] & 0x1c);
+		ptdls_sta->htpriv.rx_ampdu_min_spacing = max_AMPDU_len | min_MPDU_spacing;
+
+		/* Check if sta support s Short GI 20M */
+		if ((phtpriv->sgi_20m == _TRUE) && (ptdls_sta->htpriv.ht_cap.cap_info & cpu_to_le16(IEEE80211_HT_CAP_SGI_20)))
+			ptdls_sta->htpriv.sgi_20m = _TRUE;
+
+		/* Check if sta support s Short GI 40M */
+		if ((phtpriv->sgi_40m == _TRUE) && (ptdls_sta->htpriv.ht_cap.cap_info & cpu_to_le16(IEEE80211_HT_CAP_SGI_40)))
+			ptdls_sta->htpriv.sgi_40m = _TRUE;
+
+		/* Bwmode would still followed AP's setting */
+		if (ptdls_sta->htpriv.ht_cap.cap_info & cpu_to_le16(IEEE80211_HT_CAP_SUP_WIDTH)) {
+			if (padapter->mlmeextpriv.cur_bwmode >= CHANNEL_WIDTH_40)
+				ptdls_sta->cmn.bw_mode = CHANNEL_WIDTH_40;
+			ptdls_sta->htpriv.ch_offset = padapter->mlmeextpriv.cur_ch_offset;
+		}
+
+		/* Config LDPC Coding Capability */
+		if (TEST_FLAG(phtpriv->ldpc_cap, LDPC_HT_ENABLE_TX) && GET_HT_CAP_ELE_LDPC_CAP(data)) {
+			SET_FLAG(cur_ldpc_cap, (LDPC_HT_ENABLE_TX | LDPC_HT_CAP_TX));
+			RTW_INFO("Enable HT Tx LDPC!\n");
+		}
+		ptdls_sta->htpriv.ldpc_cap = cur_ldpc_cap;
+
+		/* Config STBC setting */
+		if (TEST_FLAG(phtpriv->stbc_cap, STBC_HT_ENABLE_TX) && GET_HT_CAP_ELE_RX_STBC(data)) {
+			SET_FLAG(cur_stbc_cap, (STBC_HT_ENABLE_TX | STBC_HT_CAP_TX));
+			RTW_INFO("Enable HT Tx STBC!\n");
+		}
+		ptdls_sta->htpriv.stbc_cap = cur_stbc_cap;
+
+#ifdef CONFIG_BEAMFORMING
+		/* Config Tx beamforming setting */
+		if (TEST_FLAG(phtpriv->beamform_cap, BEAMFORMING_HT_BEAMFORMEE_ENABLE) &&
+		    GET_HT_CAP_TXBF_EXPLICIT_COMP_STEERING_CAP(data))
+			SET_FLAG(cur_beamform_cap, BEAMFORMING_HT_BEAMFORMER_ENABLE);
+
+		if (TEST_FLAG(phtpriv->beamform_cap, BEAMFORMING_HT_BEAMFORMER_ENABLE) &&
+		    GET_HT_CAP_TXBF_EXPLICIT_COMP_FEEDBACK_CAP(data))
+			SET_FLAG(cur_beamform_cap, BEAMFORMING_HT_BEAMFORMEE_ENABLE);
+		ptdls_sta->htpriv.beamform_cap = cur_beamform_cap;
+		if (cur_beamform_cap)
+			RTW_INFO("Client HT Beamforming Cap = 0x%02X\n", cur_beamform_cap);
+#endif /* CONFIG_BEAMFORMING */
+	}
+
+}
+
+u8 *rtw_tdls_set_ht_cap(_adapter *padapter, u8 *pframe, struct pkt_attrib *pattrib)
+{
+	rtw_ht_use_default_setting(padapter);
+
+	if (padapter->registrypriv.wifi_spec == 1) {
+		padapter->mlmepriv.htpriv.sgi_20m = _FALSE;
+		padapter->mlmepriv.htpriv.sgi_40m = _FALSE;
+	}
+
+	rtw_restructure_ht_ie(padapter, NULL, pframe, 0, &(pattrib->pktlen), padapter->mlmeextpriv.cur_channel);
+
+	return pframe + pattrib->pktlen;
+}
+#endif
+
+#ifdef CONFIG_80211AC_VHT
+void rtw_tdls_process_vht_cap(_adapter *padapter, struct sta_info *ptdls_sta, u8 *data, u8 Length)
+{
+	struct rf_ctl_t *rfctl = adapter_to_rfctl(padapter);
+	struct hal_spec_t *hal_spec = GET_HAL_SPEC(padapter);
+	struct mlme_priv		*pmlmepriv = &padapter->mlmepriv;
+	struct vht_priv			*pvhtpriv = &pmlmepriv->vhtpriv;
+	u8	cur_ldpc_cap = 0, cur_stbc_cap = 0, cur_beamform_cap = 0, rf_type = RF_1T1R, tx_nss = 0;
+	u8	*pcap_mcs;
+
+	_rtw_memset(&ptdls_sta->vhtpriv, 0, sizeof(struct vht_priv));
+	if (data && Length == 12) {
+		ptdls_sta->flags |= WLAN_STA_VHT;
+
+		_rtw_memcpy(ptdls_sta->vhtpriv.vht_cap, data, 12);
+
+#if 0
+		if (elems.vht_op_mode_notify && elems.vht_op_mode_notify_len == 1)
+			_rtw_memcpy(&pstat->vhtpriv.vht_op_mode_notify, elems.vht_op_mode_notify, 1);
+		else /* for Frame without Operating Mode notify ie; default: 80M */
+			pstat->vhtpriv.vht_op_mode_notify = CHANNEL_WIDTH_80;
+#else
+		ptdls_sta->vhtpriv.vht_op_mode_notify = CHANNEL_WIDTH_80;
+#endif
+	} else {
+		ptdls_sta->flags &= ~WLAN_STA_VHT;
+		return;
+	}
+
+	if (ptdls_sta->flags & WLAN_STA_VHT) {
+		if (REGSTY_IS_11AC_ENABLE(&padapter->registrypriv)
+		    && is_supported_vht(padapter->registrypriv.wireless_mode)
+		    && (!rfctl->country_ent || COUNTRY_CHPLAN_EN_11AC(rfctl->country_ent)))
+			ptdls_sta->vhtpriv.vht_option = _TRUE;
+		else
+			ptdls_sta->vhtpriv.vht_option = _FALSE;
+	}
+
+	/* B4 Rx LDPC */
+	if (TEST_FLAG(pvhtpriv->ldpc_cap, LDPC_VHT_ENABLE_TX) &&
+	    GET_VHT_CAPABILITY_ELE_RX_LDPC(data)) {
+		SET_FLAG(cur_ldpc_cap, (LDPC_VHT_ENABLE_TX | LDPC_VHT_CAP_TX));
+		RTW_INFO("Current VHT LDPC Setting = %02X\n", cur_ldpc_cap);
+	}
+	ptdls_sta->vhtpriv.ldpc_cap = cur_ldpc_cap;
+
+	/* B5 Short GI for 80 MHz */
+	ptdls_sta->vhtpriv.sgi_80m = (GET_VHT_CAPABILITY_ELE_SHORT_GI80M(data) & pvhtpriv->sgi_80m) ? _TRUE : _FALSE;
+
+	/* B8 B9 B10 Rx STBC */
+	if (TEST_FLAG(pvhtpriv->stbc_cap, STBC_VHT_ENABLE_TX) &&
+	    GET_VHT_CAPABILITY_ELE_RX_STBC(data)) {
+		SET_FLAG(cur_stbc_cap, (STBC_VHT_ENABLE_TX | STBC_VHT_CAP_TX));
+		RTW_INFO("Current VHT STBC Setting = %02X\n", cur_stbc_cap);
+	}
+	ptdls_sta->vhtpriv.stbc_cap = cur_stbc_cap;
+
+	#ifdef CONFIG_BEAMFORMING
+	/* B11 SU Beamformer Capable, the target supports Beamformer and we are Beamformee */
+	if (TEST_FLAG(pvhtpriv->beamform_cap, BEAMFORMING_VHT_BEAMFORMER_ENABLE) &&
+	    GET_VHT_CAPABILITY_ELE_SU_BFEE(data))
+		SET_FLAG(cur_beamform_cap, BEAMFORMING_VHT_BEAMFORMEE_ENABLE);
+
+	/* B12 SU Beamformee Capable, the target supports Beamformee and we are Beamformer */
+	if (TEST_FLAG(pvhtpriv->beamform_cap, BEAMFORMING_VHT_BEAMFORMEE_ENABLE) &&
+	    GET_VHT_CAPABILITY_ELE_SU_BFER(data))
+		SET_FLAG(cur_beamform_cap, BEAMFORMING_VHT_BEAMFORMER_ENABLE);
+	ptdls_sta->vhtpriv.beamform_cap = cur_beamform_cap;
+	if (cur_beamform_cap)
+		RTW_INFO("Current VHT Beamforming Setting = %02X\n", cur_beamform_cap);
+	#endif /*CONFIG_BEAMFORMING*/
+
+	/* B23 B24 B25 Maximum A-MPDU Length Exponent */
+	ptdls_sta->vhtpriv.ampdu_len = GET_VHT_CAPABILITY_ELE_MAX_RXAMPDU_FACTOR(data);
+
+	pcap_mcs = GET_VHT_CAPABILITY_ELE_RX_MCS(data);
+	rtw_hal_get_hwreg(padapter, HW_VAR_RF_TYPE, (u8 *)(&rf_type));
+	tx_nss = rtw_min(rf_type_to_rf_tx_cnt(rf_type), hal_spec->tx_nss_num);
+	rtw_vht_nss_to_mcsmap(tx_nss, ptdls_sta->vhtpriv.vht_mcs_map, pcap_mcs);
+	ptdls_sta->vhtpriv.vht_highest_rate = rtw_get_vht_highest_rate(ptdls_sta->vhtpriv.vht_mcs_map);
+}
+
+void rtw_tdls_process_vht_operation(_adapter *padapter, struct sta_info *ptdls_sta, u8 *data, u8 Length)
+{
+	struct mlme_priv		*pmlmepriv = &padapter->mlmepriv;
+	struct mlme_ext_priv	*pmlmeext = &padapter->mlmeextpriv;
+	struct registry_priv *regsty = adapter_to_regsty(padapter);
+	u8 operation_bw = 0;
+
+	if (GET_VHT_OPERATION_ELE_CHL_WIDTH(data) >= 1) {
+
+		operation_bw = CHANNEL_WIDTH_80;
+
+		if (hal_is_bw_support(padapter, operation_bw) && REGSTY_IS_BW_5G_SUPPORT(regsty, operation_bw)
+			&& (operation_bw <= pmlmeext->cur_bwmode))
+			ptdls_sta->cmn.bw_mode = operation_bw;
+		else
+			ptdls_sta->cmn.bw_mode = pmlmeext->cur_bwmode;
+	} else
+		ptdls_sta->cmn.bw_mode = pmlmeext->cur_bwmode;
+}
+
+void rtw_tdls_process_vht_op_mode_notify(_adapter *padapter, struct sta_info *ptdls_sta, u8 *data, u8 Length)
+{
+	struct mlme_priv		*pmlmepriv = &padapter->mlmepriv;
+	struct vht_priv		*pvhtpriv = &pmlmepriv->vhtpriv;
+	struct mlme_ext_priv	*pmlmeext = &padapter->mlmeextpriv;
+	struct registry_priv *regsty = adapter_to_regsty(padapter);
+	u8	target_bw;
+	u8	target_rxss, current_rxss;
+
+	if (pvhtpriv->vht_option == _FALSE)
+		return;
+
+	target_bw = GET_VHT_OPERATING_MODE_FIELD_CHNL_WIDTH(data);
+	target_rxss = (GET_VHT_OPERATING_MODE_FIELD_RX_NSS(data) + 1);
+
+	if (hal_is_bw_support(padapter, target_bw) && REGSTY_IS_BW_5G_SUPPORT(regsty, target_bw)
+		&& (target_bw <= pmlmeext->cur_bwmode))
+		ptdls_sta->cmn.bw_mode = target_bw;
+	else
+		ptdls_sta->cmn.bw_mode = pmlmeext->cur_bwmode;
+
+	current_rxss = rtw_vht_mcsmap_to_nss(ptdls_sta->vhtpriv.vht_mcs_map);
+	if (target_rxss != current_rxss) {
+		u8	vht_mcs_map[2] = {};
+
+		rtw_vht_nss_to_mcsmap(target_rxss, vht_mcs_map, ptdls_sta->vhtpriv.vht_mcs_map);
+		_rtw_memcpy(ptdls_sta->vhtpriv.vht_mcs_map, vht_mcs_map, 2);
+	}
+}
+
+u8 *rtw_tdls_set_aid(_adapter *padapter, u8 *pframe, struct pkt_attrib *pattrib)
+{
+	return rtw_set_ie(pframe, EID_AID, 2, (u8 *)&(padapter->mlmepriv.cur_network.aid), &(pattrib->pktlen));
+}
+
+u8 *rtw_tdls_set_vht_cap(_adapter *padapter, u8 *pframe, struct pkt_attrib *pattrib)
+{
+	u32 ie_len = 0;
+
+	rtw_vht_use_default_setting(padapter);
+
+	ie_len = rtw_build_vht_cap_ie(padapter, pframe);
+	pattrib->pktlen += ie_len;
+
+	return pframe + ie_len;
+}
+
+u8 *rtw_tdls_set_vht_operation(_adapter *padapter, u8 *pframe, struct pkt_attrib *pattrib, u8 channel)
+{
+	u32 ie_len = 0;
+
+	ie_len = rtw_build_vht_operation_ie(padapter, pframe, channel);
+	pattrib->pktlen += ie_len;
+
+	return pframe + ie_len;
+}
+
+u8 *rtw_tdls_set_vht_op_mode_notify(_adapter *padapter, u8 *pframe, struct pkt_attrib *pattrib, u8 bw)
+{
+	u32 ie_len = 0;
+
+	ie_len = rtw_build_vht_op_mode_notify_ie(padapter, pframe, bw);
+	pattrib->pktlen += ie_len;
+
+	return pframe + ie_len;
+}
+#endif
+
+
+u8 *rtw_tdls_set_sup_ch(_adapter *adapter, u8 *pframe, struct pkt_attrib *pattrib)
+{
+	struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter);
+	u8 sup_ch[30 * 2] = {0x00}, ch_set_idx = 0, sup_ch_idx = 2;
+
+	while (ch_set_idx < rfctl->max_chan_nums && rfctl->channel_set[ch_set_idx].ChannelNum != 0) {
+		if (rfctl->channel_set[ch_set_idx].ChannelNum <= 14) {
+			/* TODO: fix 2.4G supported channel when channel doesn't start from 1 and continuous */
+			sup_ch[0] = 1;	/* First channel number */
+			sup_ch[1] = rfctl->channel_set[ch_set_idx].ChannelNum;	/* Number of channel */
+		} else {
+			sup_ch[sup_ch_idx++] = rfctl->channel_set[ch_set_idx].ChannelNum;
+			sup_ch[sup_ch_idx++] = 1;
+		}
+		ch_set_idx++;
+	}
+
+	return rtw_set_ie(pframe, _SUPPORTED_CH_IE_, sup_ch_idx, sup_ch, &(pattrib->pktlen));
+}
+
+u8 *rtw_tdls_set_rsnie(struct tdls_txmgmt *ptxmgmt, u8 *pframe, struct pkt_attrib *pattrib,  int init, struct sta_info *ptdls_sta)
+{
+	u8 *p = NULL;
+	int len = 0;
+
+	if (ptxmgmt->len > 0)
+		p = rtw_get_ie(ptxmgmt->buf, _RSN_IE_2_, &len, ptxmgmt->len);
+
+	if (p != NULL)
+		return rtw_set_ie(pframe, _RSN_IE_2_, len, p + 2, &(pattrib->pktlen));
+	else if (init == _TRUE)
+		return rtw_set_ie(pframe, _RSN_IE_2_, sizeof(TDLS_RSNIE), TDLS_RSNIE, &(pattrib->pktlen));
+	else
+		return rtw_set_ie(pframe, _RSN_IE_2_, sizeof(ptdls_sta->TDLS_RSNIE), ptdls_sta->TDLS_RSNIE, &(pattrib->pktlen));
+}
+
+u8 *rtw_tdls_set_ext_cap(u8 *pframe, struct pkt_attrib *pattrib)
+{
+	return rtw_set_ie(pframe, _EXT_CAP_IE_ , sizeof(TDLS_EXT_CAPIE), TDLS_EXT_CAPIE, &(pattrib->pktlen));
+}
+
+u8 *rtw_tdls_set_qos_cap(u8 *pframe, struct pkt_attrib *pattrib)
+{
+	return rtw_set_ie(pframe, _VENDOR_SPECIFIC_IE_, sizeof(TDLS_WMMIE), TDLS_WMMIE,  &(pattrib->pktlen));
+}
+
+u8 *rtw_tdls_set_ftie(struct tdls_txmgmt *ptxmgmt, u8 *pframe, struct pkt_attrib *pattrib, u8 *ANonce, u8 *SNonce)
+{
+	struct wpa_tdls_ftie FTIE = {0};
+	u8 *p = NULL;
+	int len = 0;
+
+	if (ptxmgmt->len > 0)
+		p = rtw_get_ie(ptxmgmt->buf, _FTIE_, &len, ptxmgmt->len);
+
+	if (p != NULL)
+		return rtw_set_ie(pframe, _FTIE_, len, p + 2, &(pattrib->pktlen));
+	else {
+		if (ANonce != NULL)
+			_rtw_memcpy(FTIE.Anonce, ANonce, WPA_NONCE_LEN);
+		if (SNonce != NULL)
+			_rtw_memcpy(FTIE.Snonce, SNonce, WPA_NONCE_LEN);
+
+		return rtw_set_ie(pframe, _FTIE_, TDLS_FTIE_DATA_LEN,
+						  (u8 *)FTIE.data, &(pattrib->pktlen));
+	}
+}
+
+u8 *rtw_tdls_set_timeout_interval(struct tdls_txmgmt *ptxmgmt, u8 *pframe, struct pkt_attrib *pattrib, int init, struct sta_info *ptdls_sta)
+{
+	u8 timeout_itvl[5];	/* set timeout interval to maximum value */
+	u32 timeout_interval = TDLS_TPK_RESEND_COUNT;
+	u8 *p = NULL;
+	int len = 0;
+
+	if (ptxmgmt->len > 0)
+		p = rtw_get_ie(ptxmgmt->buf, _TIMEOUT_ITVL_IE_, &len, ptxmgmt->len);
+
+	if (p != NULL)
+		return rtw_set_ie(pframe, _TIMEOUT_ITVL_IE_, len, p + 2, &(pattrib->pktlen));
+	else {
+		/* Timeout interval */
+		timeout_itvl[0] = 0x02;
+		if (init == _TRUE)
+			_rtw_memcpy(timeout_itvl + 1, &timeout_interval, 4);
+		else
+			_rtw_memcpy(timeout_itvl + 1, (u8 *)(&ptdls_sta->TDLS_PeerKey_Lifetime), 4);
+
+		return rtw_set_ie(pframe, _TIMEOUT_ITVL_IE_, 5, timeout_itvl, &(pattrib->pktlen));
+	}
+}
+
+u8 *rtw_tdls_set_bss_coexist(_adapter *padapter, u8 *pframe, struct pkt_attrib *pattrib)
+{
+	u8 iedata = 0;
+
+	if (padapter->mlmepriv.num_FortyMHzIntolerant > 0)
+		iedata |= BIT(2);	/* 20 MHz BSS Width Request */
+
+	/* Information Bit should be set by TDLS test plan 5.9 */
+	iedata |= BIT(0);
+	return rtw_set_ie(pframe, EID_BSSCoexistence, 1, &iedata, &(pattrib->pktlen));
+}
+
+u8 *rtw_tdls_set_payload_type(u8 *pframe, struct pkt_attrib *pattrib)
+{
+	u8 payload_type = 0x02;
+	return rtw_set_fixed_ie(pframe, 1, &(payload_type), &(pattrib->pktlen));
+}
+
+u8 *rtw_tdls_set_category(u8 *pframe, struct pkt_attrib *pattrib, u8 category)
+{
+	return rtw_set_fixed_ie(pframe, 1, &(category), &(pattrib->pktlen));
+}
+
+u8 *rtw_tdls_set_action(u8 *pframe, struct pkt_attrib *pattrib, struct tdls_txmgmt *ptxmgmt)
+{
+	return rtw_set_fixed_ie(pframe, 1, &(ptxmgmt->action_code), &(pattrib->pktlen));
+}
+
+u8 *rtw_tdls_set_status_code(u8 *pframe, struct pkt_attrib *pattrib, struct tdls_txmgmt *ptxmgmt)
+{
+	return rtw_set_fixed_ie(pframe, 2, (u8 *)&(ptxmgmt->status_code), &(pattrib->pktlen));
+}
+
+u8 *rtw_tdls_set_dialog(u8 *pframe, struct pkt_attrib *pattrib, struct tdls_txmgmt *ptxmgmt)
+{
+	u8 dialogtoken = 1;
+	if (ptxmgmt->dialog_token)
+		return rtw_set_fixed_ie(pframe, 1, &(ptxmgmt->dialog_token), &(pattrib->pktlen));
+	else
+		return rtw_set_fixed_ie(pframe, 1, &(dialogtoken), &(pattrib->pktlen));
+}
+
+u8 *rtw_tdls_set_reg_class(u8 *pframe, struct pkt_attrib *pattrib, struct sta_info *ptdls_sta)
+{
+	u8 reg_class = 22;
+	return rtw_set_fixed_ie(pframe, 1, &(reg_class), &(pattrib->pktlen));
+}
+
+u8 *rtw_tdls_set_second_channel_offset(u8 *pframe, struct pkt_attrib *pattrib, u8 ch_offset)
+{
+	return rtw_set_ie(pframe, EID_SecondaryChnlOffset , 1, &ch_offset, &(pattrib->pktlen));
+}
+
+u8 *rtw_tdls_set_capability(_adapter *padapter, u8 *pframe, struct pkt_attrib *pattrib)
+{
+	struct mlme_ext_priv	*pmlmeext = &padapter->mlmeextpriv;
+	struct mlme_ext_info	*pmlmeinfo = &pmlmeext->mlmext_info;
+	u8 cap_from_ie[2] = {0};
+
+	_rtw_memcpy(cap_from_ie, rtw_get_capability_from_ie(pmlmeinfo->network.IEs), 2);
+
+	return rtw_set_fixed_ie(pframe, 2, cap_from_ie, &(pattrib->pktlen));
+}
+
+u8 *rtw_tdls_set_supported_rate(_adapter *padapter, u8 *pframe, struct pkt_attrib *pattrib)
+{
+	u8 bssrate[NDIS_802_11_LENGTH_RATES_EX];
+	int bssrate_len = 0;
+	u8 more_supportedrates = 0;
+
+	rtw_set_supported_rate(bssrate, (padapter->registrypriv.wireless_mode == WIRELESS_MODE_MAX) ? padapter->mlmeextpriv.cur_wireless_mode : padapter->registrypriv.wireless_mode);
+	bssrate_len = rtw_get_rateset_len(bssrate);
+
+	if (bssrate_len > 8) {
+		pframe = rtw_set_ie(pframe, _SUPPORTEDRATES_IE_ , 8, bssrate, &(pattrib->pktlen));
+		more_supportedrates = 1;
+	} else
+		pframe = rtw_set_ie(pframe, _SUPPORTEDRATES_IE_ , bssrate_len , bssrate, &(pattrib->pktlen));
+
+	/* extended supported rates */
+	if (more_supportedrates == 1)
+		pframe = rtw_set_ie(pframe, _EXT_SUPPORTEDRATES_IE_ , (bssrate_len - 8), (bssrate + 8), &(pattrib->pktlen));
+
+	return pframe;
+}
+
+u8 *rtw_tdls_set_sup_reg_class(u8 *pframe, struct pkt_attrib *pattrib)
+{
+	return rtw_set_ie(pframe, _SRC_IE_ , sizeof(TDLS_SRC), TDLS_SRC, &(pattrib->pktlen));
+}
+
+u8 *rtw_tdls_set_linkid(_adapter *padapter, u8 *pframe, struct pkt_attrib *pattrib, u8 init)
+{
+	struct mlme_ext_priv	*pmlmeext = &(padapter->mlmeextpriv);
+	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
+
+	u8 link_id_addr[18] = {0};
+
+	_rtw_memcpy(link_id_addr, get_my_bssid(&(pmlmeinfo->network)), 6);
+
+	if (init == _TRUE) {
+		_rtw_memcpy((link_id_addr + 6), pattrib->src, 6);
+		_rtw_memcpy((link_id_addr + 12), pattrib->dst, 6);
+	} else {
+		_rtw_memcpy((link_id_addr + 6), pattrib->dst, 6);
+		_rtw_memcpy((link_id_addr + 12), pattrib->src, 6);
+	}
+	return rtw_set_ie(pframe, _LINK_ID_IE_, 18, link_id_addr, &(pattrib->pktlen));
+}
+
+#ifdef CONFIG_TDLS_CH_SW
+u8 *rtw_tdls_set_target_ch(_adapter *padapter, u8 *pframe, struct pkt_attrib *pattrib)
+{
+	u8 target_ch = 1;
+	if (padapter->tdlsinfo.chsw_info.off_ch_num)
+		return rtw_set_fixed_ie(pframe, 1, &(padapter->tdlsinfo.chsw_info.off_ch_num), &(pattrib->pktlen));
+	else
+		return rtw_set_fixed_ie(pframe, 1, &(target_ch), &(pattrib->pktlen));
+}
+
+u8 *rtw_tdls_set_ch_sw(u8 *pframe, struct pkt_attrib *pattrib, struct sta_info *ptdls_sta)
+{
+	u8 ch_switch_timing[4] = {0};
+	u16 switch_time = (ptdls_sta->ch_switch_time >= TDLS_CH_SWITCH_TIME * 1000) ?
+			  ptdls_sta->ch_switch_time : TDLS_CH_SWITCH_TIME;
+	u16 switch_timeout = (ptdls_sta->ch_switch_timeout >= TDLS_CH_SWITCH_TIMEOUT * 1000) ?
+		     ptdls_sta->ch_switch_timeout : TDLS_CH_SWITCH_TIMEOUT;
+
+	_rtw_memcpy(ch_switch_timing, &switch_time, 2);
+	_rtw_memcpy(ch_switch_timing + 2, &switch_timeout, 2);
+
+	return rtw_set_ie(pframe, _CH_SWITCH_TIMING_,  4, ch_switch_timing, &(pattrib->pktlen));
+}
+
+void rtw_tdls_set_ch_sw_oper_control(_adapter *padapter, u8 enable)
+{
+	HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
+
+	if (enable == _TRUE) {
+#ifdef CONFIG_TDLS_CH_SW_V2
+		pHalData->ch_switch_offload = _TRUE;
+#endif
+
+#ifdef CONFIG_TDLS_CH_SW_BY_DRV
+		pHalData->ch_switch_offload = _FALSE;
+#endif
+	}
+	else
+		pHalData->ch_switch_offload = _FALSE;
+	
+	if (ATOMIC_READ(&padapter->tdlsinfo.chsw_info.chsw_on) != enable)
+		ATOMIC_SET(&padapter->tdlsinfo.chsw_info.chsw_on, enable);
+
+	rtw_hal_set_hwreg(padapter, HW_VAR_TDLS_BCN_EARLY_C2H_RPT, &enable);
+	RTW_INFO("[TDLS] %s Bcn Early C2H Report\n", (enable == _TRUE) ? "Start" : "Stop");
+}
+
+void rtw_tdls_ch_sw_back_to_base_chnl(_adapter *padapter)
+{
+	struct mlme_priv *pmlmepriv;
+	struct tdls_ch_switch *pchsw_info = &padapter->tdlsinfo.chsw_info;
+
+	pmlmepriv = &padapter->mlmepriv;
+
+	if ((ATOMIC_READ(&pchsw_info->chsw_on) == _TRUE) &&
+	    (padapter->mlmeextpriv.cur_channel != rtw_get_oper_ch(padapter)))
+		rtw_tdls_cmd(padapter, pchsw_info->addr, TDLS_CH_SW_TO_BASE_CHNL_UNSOLICITED);
+}
+
+static void rtw_tdls_chsw_oper_init(_adapter *padapter, u32 timeout_ms)
+{
+	struct submit_ctx	*chsw_sctx = &padapter->tdlsinfo.chsw_info.chsw_sctx;
+
+	rtw_sctx_init(chsw_sctx, timeout_ms);
+}
+
+static int rtw_tdls_chsw_oper_wait(_adapter *padapter)
+{
+	struct submit_ctx	*chsw_sctx = &padapter->tdlsinfo.chsw_info.chsw_sctx;
+
+	return rtw_sctx_wait(chsw_sctx, __func__);
+}
+
+void rtw_tdls_chsw_oper_done(_adapter *padapter)
+{
+	struct submit_ctx	*chsw_sctx = &padapter->tdlsinfo.chsw_info.chsw_sctx;
+
+	rtw_sctx_done(&chsw_sctx);
+}
+
+s32 rtw_tdls_do_ch_sw(_adapter *padapter, struct sta_info *ptdls_sta, u8 chnl_type, u8 channel, u8 channel_offset, u16 bwmode, u16 ch_switch_time)
+{
+	HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
+	u8 center_ch, chnl_offset80 = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
+	u32 ch_sw_time_start, ch_sw_time_spent, wait_time;
+	u8 take_care_iqk;
+	s32 ret = _FAIL;
+
+	ch_sw_time_start = rtw_systime_to_ms(rtw_get_current_time());
+
+	/* set mac_id sleep before channel switch */
+	rtw_hal_macid_sleep(padapter, ptdls_sta->cmn.mac_id);
+
+#if defined(CONFIG_TDLS_CH_SW_BY_DRV) || defined(CONFIG_TDLS_CH_SW_V2)
+	set_channel_bwmode(padapter, channel, channel_offset, bwmode);
+	ret = _SUCCESS;
+#else
+	rtw_tdls_chsw_oper_init(padapter, TDLS_CH_SWITCH_OPER_OFFLOAD_TIMEOUT);
+
+	/* channel switch IOs offload to FW */
+	if (rtw_hal_ch_sw_oper_offload(padapter, channel, channel_offset, bwmode) == _SUCCESS) {
+		if (rtw_tdls_chsw_oper_wait(padapter) == _SUCCESS) {
+			/* set channel and bw related variables in driver */
+			_enter_critical_mutex(&(adapter_to_dvobj(padapter)->setch_mutex), NULL);
+
+			rtw_set_oper_ch(padapter, channel);
+			rtw_set_oper_choffset(padapter, channel_offset);
+			rtw_set_oper_bw(padapter, bwmode);
+
+			center_ch = rtw_get_center_ch(channel, bwmode, channel_offset);
+			pHalData->current_channel = center_ch;
+			pHalData->CurrentCenterFrequencyIndex1 = center_ch;
+			pHalData->current_channel_bw = bwmode;
+			pHalData->nCur40MhzPrimeSC = channel_offset;
+
+			if (bwmode == CHANNEL_WIDTH_80) {
+				if (center_ch > channel)
+					chnl_offset80 = HAL_PRIME_CHNL_OFFSET_LOWER;
+				else if (center_ch < channel)
+					chnl_offset80 = HAL_PRIME_CHNL_OFFSET_UPPER;
+				else
+					chnl_offset80 = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
+			}
+			pHalData->nCur80MhzPrimeSC = chnl_offset80;
+
+			pHalData->CurrentCenterFrequencyIndex1 = center_ch;
+
+			_exit_critical_mutex(&(adapter_to_dvobj(padapter)->setch_mutex), NULL);
+
+			rtw_hal_get_hwreg(padapter, HW_VAR_CH_SW_NEED_TO_TAKE_CARE_IQK_INFO, &take_care_iqk);
+			if (take_care_iqk == _TRUE)
+				rtw_hal_ch_sw_iqk_info_restore(padapter, CH_SW_USE_CASE_TDLS);
+
+			ret = _SUCCESS;
+		} else
+			RTW_INFO("[TDLS] chsw oper wait fail !!\n");
+	}
+#endif
+
+	if (ret == _SUCCESS) {
+		ch_sw_time_spent = rtw_systime_to_ms(rtw_get_current_time()) - ch_sw_time_start;
+		if (chnl_type == TDLS_CH_SW_OFF_CHNL) {
+			if ((u32)ch_switch_time / 1000 > ch_sw_time_spent)
+				wait_time = (u32)ch_switch_time / 1000 - ch_sw_time_spent;
+			else
+				wait_time = 0;
+
+			if (wait_time > 0)
+				rtw_msleep_os(wait_time);
+		}
+	}
+
+	/* set mac_id wakeup after channel switch */
+	rtw_hal_macid_wakeup(padapter, ptdls_sta->cmn.mac_id);
+
+	return ret;
+}
+#endif
+
+u8 *rtw_tdls_set_wmm_params(_adapter *padapter, u8 *pframe, struct pkt_attrib *pattrib)
+{
+	struct mlme_ext_priv	*pmlmeext = &(padapter->mlmeextpriv);
+	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
+	u8 wmm_param_ele[24] = {0};
+
+	if (&pmlmeinfo->WMM_param) {
+		_rtw_memcpy(wmm_param_ele, WMM_PARA_OUI, 6);
+		if (_rtw_memcmp(&pmlmeinfo->WMM_param, &wmm_param_ele[6], 18) == _TRUE)
+			/* Use default WMM Param */
+			_rtw_memcpy(wmm_param_ele + 6, (u8 *)&TDLS_WMM_PARAM_IE, sizeof(TDLS_WMM_PARAM_IE));
+		else
+			_rtw_memcpy(wmm_param_ele + 6, (u8 *)&pmlmeinfo->WMM_param, sizeof(pmlmeinfo->WMM_param));
+		return rtw_set_ie(pframe, _VENDOR_SPECIFIC_IE_,  24, wmm_param_ele, &(pattrib->pktlen));
+	} else
+		return pframe;
+}
+
+#ifdef CONFIG_WFD
+void rtw_tdls_process_wfd_ie(struct tdls_info *ptdlsinfo, u8 *ptr, u8 length)
+{
+	u8 *wfd_ie;
+	u32	wfd_ielen = 0;
+
+	if (!hal_chk_wl_func(tdls_info_to_adapter(ptdlsinfo), WL_FUNC_MIRACAST))
+		return;
+
+	/* Try to get the TCP port information when receiving the negotiation response. */
+
+	wfd_ie = rtw_get_wfd_ie(ptr, length, NULL, &wfd_ielen);
+	while (wfd_ie) {
+		u8 *attr_content;
+		u32	attr_contentlen = 0;
+		int	i;
+
+		RTW_INFO("[%s] WFD IE Found!!\n", __FUNCTION__);
+		attr_content = rtw_get_wfd_attr_content(wfd_ie, wfd_ielen, WFD_ATTR_DEVICE_INFO, NULL, &attr_contentlen);
+		if (attr_content && attr_contentlen) {
+			ptdlsinfo->wfd_info->peer_rtsp_ctrlport = RTW_GET_BE16(attr_content + 2);
+			RTW_INFO("[%s] Peer PORT NUM = %d\n", __FUNCTION__, ptdlsinfo->wfd_info->peer_rtsp_ctrlport);
+		}
+
+		attr_content = rtw_get_wfd_attr_content(wfd_ie, wfd_ielen, WFD_ATTR_LOCAL_IP_ADDR, NULL, &attr_contentlen);
+		if (attr_content && attr_contentlen) {
+			_rtw_memcpy(ptdlsinfo->wfd_info->peer_ip_address, (attr_content + 1), 4);
+			RTW_INFO("[%s] Peer IP = %02u.%02u.%02u.%02u\n", __FUNCTION__,
+				ptdlsinfo->wfd_info->peer_ip_address[0], ptdlsinfo->wfd_info->peer_ip_address[1],
+				ptdlsinfo->wfd_info->peer_ip_address[2], ptdlsinfo->wfd_info->peer_ip_address[3]);
+		}
+
+		wfd_ie = rtw_get_wfd_ie(wfd_ie + wfd_ielen, (ptr + length) - (wfd_ie + wfd_ielen), NULL, &wfd_ielen);
+	}
+}
+
+int issue_tunneled_probe_req(_adapter *padapter)
+{
+	struct xmit_frame			*pmgntframe;
+	struct pkt_attrib			*pattrib;
+	struct mlme_priv	*pmlmepriv = &padapter->mlmepriv;
+	struct xmit_priv			*pxmitpriv = &(padapter->xmitpriv);
+	u8 baddr[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
+	struct tdls_txmgmt txmgmt;
+	int ret = _FAIL;
+
+	RTW_INFO("[%s]\n", __FUNCTION__);
+
+	_rtw_memset(&txmgmt, 0x00, sizeof(struct tdls_txmgmt));
+	txmgmt.action_code = TUNNELED_PROBE_REQ;
+
+	pmgntframe = alloc_mgtxmitframe(pxmitpriv);
+	if (pmgntframe == NULL)
+		goto exit;
+
+	pattrib = &pmgntframe->attrib;
+
+	pmgntframe->frame_tag = DATA_FRAMETAG;
+	pattrib->ether_type = 0x890d;
+
+	_rtw_memcpy(pattrib->dst, baddr, ETH_ALEN);
+	_rtw_memcpy(pattrib->src, adapter_mac_addr(padapter), ETH_ALEN);
+	_rtw_memcpy(pattrib->ra, get_bssid(pmlmepriv), ETH_ALEN);
+	_rtw_memcpy(pattrib->ta, pattrib->src, ETH_ALEN);
+
+	update_tdls_attrib(padapter, pattrib);
+	pattrib->qsel = pattrib->priority;
+	if (rtw_xmit_tdls_coalesce(padapter, pmgntframe, &txmgmt) != _SUCCESS) {
+		rtw_free_xmitbuf(pxmitpriv, pmgntframe->pxmitbuf);
+		rtw_free_xmitframe(pxmitpriv, pmgntframe);
+		goto exit;
+	}
+	dump_mgntframe(padapter, pmgntframe);
+	ret = _SUCCESS;
+exit:
+
+	return ret;
+}
+
+int issue_tunneled_probe_rsp(_adapter *padapter, union recv_frame *precv_frame)
+{
+	struct xmit_frame			*pmgntframe;
+	struct pkt_attrib			*pattrib;
+	struct mlme_priv	*pmlmepriv = &padapter->mlmepriv;
+	struct xmit_priv			*pxmitpriv = &(padapter->xmitpriv);
+	struct tdls_txmgmt txmgmt;
+	int ret = _FAIL;
+
+	RTW_INFO("[%s]\n", __FUNCTION__);
+
+	_rtw_memset(&txmgmt, 0x00, sizeof(struct tdls_txmgmt));
+	txmgmt.action_code = TUNNELED_PROBE_RSP;
+
+	pmgntframe = alloc_mgtxmitframe(pxmitpriv);
+	if (pmgntframe == NULL)
+		goto exit;
+
+	pattrib = &pmgntframe->attrib;
+
+	pmgntframe->frame_tag = DATA_FRAMETAG;
+	pattrib->ether_type = 0x890d;
+
+	_rtw_memcpy(pattrib->dst, precv_frame->u.hdr.attrib.src, ETH_ALEN);
+	_rtw_memcpy(pattrib->src, adapter_mac_addr(padapter), ETH_ALEN);
+	_rtw_memcpy(pattrib->ra, get_bssid(pmlmepriv), ETH_ALEN);
+	_rtw_memcpy(pattrib->ta, pattrib->src, ETH_ALEN);
+
+	update_tdls_attrib(padapter, pattrib);
+	pattrib->qsel = pattrib->priority;
+	if (rtw_xmit_tdls_coalesce(padapter, pmgntframe, &txmgmt) != _SUCCESS) {
+		rtw_free_xmitbuf(pxmitpriv, pmgntframe->pxmitbuf);
+		rtw_free_xmitframe(pxmitpriv, pmgntframe);
+		goto exit;
+	}
+	dump_mgntframe(padapter, pmgntframe);
+	ret = _SUCCESS;
+exit:
+
+	return ret;
+}
+#endif /* CONFIG_WFD */
+
+int issue_tdls_setup_req(_adapter *padapter, struct tdls_txmgmt *ptxmgmt, int wait_ack)
+{
+	struct tdls_info	*ptdlsinfo = &padapter->tdlsinfo;
+	struct xmit_frame			*pmgntframe;
+	struct pkt_attrib			*pattrib;
+	struct mlme_priv	*pmlmepriv = &padapter->mlmepriv;
+	struct xmit_priv			*pxmitpriv = &(padapter->xmitpriv);
+	struct sta_priv *pstapriv = &padapter->stapriv;
+	struct sta_info *ptdls_sta = NULL;
+	_irqL irqL;
+	int ret = _FAIL;
+	/* Retry timer should be set at least 301 sec, using TPK_count counting 301 times. */
+	u32 timeout_interval = TDLS_TPK_RESEND_COUNT;
+
+	RTW_INFO("[TDLS] %s\n", __FUNCTION__);
+
+	if (rtw_tdls_is_setup_allowed(padapter) == _FALSE)
+		goto exit;
+
+	if (IS_MCAST(ptxmgmt->peer))
+		goto exit;
+
+	ptdls_sta = rtw_get_stainfo(pstapriv, ptxmgmt->peer);
+	if (ptdlsinfo->sta_maximum == _TRUE) {
+		if (ptdls_sta == NULL)
+			goto exit;
+		else if (!(ptdls_sta->tdls_sta_state & TDLS_LINKED_STATE))
+			goto exit;
+	}
+
+	pmgntframe = alloc_mgtxmitframe(pxmitpriv);
+	if (pmgntframe == NULL)
+		goto exit;
+
+	if (ptdls_sta == NULL) {
+		ptdls_sta = rtw_alloc_stainfo(pstapriv, ptxmgmt->peer);
+		if (ptdls_sta == NULL) {
+			RTW_INFO("[%s] rtw_alloc_stainfo fail\n", __FUNCTION__);
+			rtw_free_xmitbuf(pxmitpriv, pmgntframe->pxmitbuf);
+			rtw_free_xmitframe(pxmitpriv, pmgntframe);
+			goto exit;
+		}
+		ptdlsinfo->sta_cnt++;
+	}
+
+	ptxmgmt->action_code = TDLS_SETUP_REQUEST;
+
+	pattrib = &pmgntframe->attrib;
+	pmgntframe->frame_tag = DATA_FRAMETAG;
+	pattrib->ether_type = 0x890d;
+
+	_rtw_memcpy(pattrib->dst, ptxmgmt->peer, ETH_ALEN);
+	_rtw_memcpy(pattrib->src, adapter_mac_addr(padapter), ETH_ALEN);
+	_rtw_memcpy(pattrib->ra, get_bssid(pmlmepriv), ETH_ALEN);
+	_rtw_memcpy(pattrib->ta, pattrib->src, ETH_ALEN);
+
+	update_tdls_attrib(padapter, pattrib);
+
+	if (ptdlsinfo->sta_cnt == MAX_ALLOWED_TDLS_STA_NUM)
+		ptdlsinfo->sta_maximum  = _TRUE;
+
+	ptdls_sta->tdls_sta_state |= TDLS_RESPONDER_STATE;
+
+	if (rtw_tdls_is_driver_setup(padapter) == _TRUE) {
+		ptdls_sta->TDLS_PeerKey_Lifetime = timeout_interval;
+		_set_timer(&ptdls_sta->handshake_timer, TDLS_HANDSHAKE_TIME);
+	}
+
+	pattrib->qsel = pattrib->priority;
+
+	if (rtw_xmit_tdls_coalesce(padapter, pmgntframe, ptxmgmt) != _SUCCESS) {
+		rtw_free_xmitbuf(pxmitpriv, pmgntframe->pxmitbuf);
+		rtw_free_xmitframe(pxmitpriv, pmgntframe);
+		goto exit;
+	}
+
+	if (wait_ack)
+		ret = dump_mgntframe_and_wait_ack(padapter, pmgntframe);
+	else {
+		dump_mgntframe(padapter, pmgntframe);
+		ret = _SUCCESS;
+	}
+
+exit:
+
+	return ret;
+}
+
+int _issue_tdls_teardown(_adapter *padapter, struct tdls_txmgmt *ptxmgmt, struct sta_info *ptdls_sta, u8 wait_ack)
+{
+	struct xmit_frame			*pmgntframe;
+	struct pkt_attrib			*pattrib;
+	struct mlme_priv	*pmlmepriv = &padapter->mlmepriv;
+	struct xmit_priv			*pxmitpriv = &(padapter->xmitpriv);
+	struct sta_priv *pstapriv = &padapter->stapriv;
+	_irqL irqL;
+	int ret = _FAIL;
+
+	RTW_INFO("[TDLS] %s\n", __FUNCTION__);
+
+	ptxmgmt->action_code = TDLS_TEARDOWN;
+
+	pmgntframe = alloc_mgtxmitframe(pxmitpriv);
+	if (pmgntframe == NULL)
+		goto exit;
+
+	rtw_mi_set_scan_deny(padapter, 550);
+	rtw_mi_scan_abort(padapter, _TRUE);
+
+	pattrib = &pmgntframe->attrib;
+
+	pmgntframe->frame_tag = DATA_FRAMETAG;
+	pattrib->ether_type = 0x890d;
+
+	_rtw_memcpy(pattrib->dst, ptxmgmt->peer, ETH_ALEN);
+	_rtw_memcpy(pattrib->src, adapter_mac_addr(padapter), ETH_ALEN);
+
+	if (ptxmgmt->status_code == _RSON_TDLS_TEAR_UN_RSN_)
+		_rtw_memcpy(pattrib->ra, ptxmgmt->peer, ETH_ALEN);
+	else
+		_rtw_memcpy(pattrib->ra, get_bssid(pmlmepriv), ETH_ALEN);
+
+	_rtw_memcpy(pattrib->ta, pattrib->src, ETH_ALEN);
+
+	update_tdls_attrib(padapter, pattrib);
+	pattrib->qsel = pattrib->priority;
+	if (rtw_xmit_tdls_coalesce(padapter, pmgntframe, ptxmgmt) != _SUCCESS) {
+		rtw_free_xmitbuf(pxmitpriv, pmgntframe->pxmitbuf);
+		rtw_free_xmitframe(pxmitpriv, pmgntframe);
+		goto exit;
+	}
+
+	if (rtw_tdls_is_driver_setup(padapter) == _TRUE)
+		if (ptdls_sta->tdls_sta_state & TDLS_LINKED_STATE)
+			if (pattrib->encrypt)
+				_cancel_timer_ex(&ptdls_sta->TPK_timer);
+
+	if (wait_ack)
+		ret = dump_mgntframe_and_wait_ack(padapter, pmgntframe);
+	else {
+		dump_mgntframe(padapter, pmgntframe);
+		ret = _SUCCESS;
+	}
+
+exit:
+
+	return ret;
+}
+
+int issue_tdls_teardown(_adapter *padapter, struct tdls_txmgmt *ptxmgmt, u8 wait_ack)
+{
+	struct sta_info *ptdls_sta = NULL;
+	int ret = _FAIL;
+
+	ptdls_sta = rtw_get_stainfo(&(padapter->stapriv), ptxmgmt->peer);
+	if (ptdls_sta == NULL) {
+		RTW_INFO("No tdls_sta for tearing down\n");
+		goto exit;
+	}
+
+	ret = _issue_tdls_teardown(padapter, ptxmgmt, ptdls_sta, wait_ack);
+	if ((ptxmgmt->status_code == _RSON_TDLS_TEAR_UN_RSN_) && (ret == _FAIL)) {
+		/* Change status code and send teardown again via AP */
+		ptxmgmt->status_code = _RSON_TDLS_TEAR_TOOFAR_;
+		ret = _issue_tdls_teardown(padapter, ptxmgmt, ptdls_sta, wait_ack);
+	}
+
+	if (rtw_tdls_is_driver_setup(padapter)) {
+		rtw_tdls_teardown_pre_hdl(padapter, ptdls_sta);
+		rtw_tdls_cmd(padapter, ptxmgmt->peer, TDLS_TEARDOWN_STA_LOCALLY_POST);
+	}
+
+exit:
+	return ret;
+}
+
+int issue_tdls_dis_req(_adapter *padapter, struct tdls_txmgmt *ptxmgmt)
+{
+	struct xmit_frame			*pmgntframe;
+	struct pkt_attrib			*pattrib;
+	struct mlme_priv	*pmlmepriv = &padapter->mlmepriv;
+	struct xmit_priv			*pxmitpriv = &(padapter->xmitpriv);
+	int ret = _FAIL;
+
+	RTW_INFO("[TDLS] %s\n", __FUNCTION__);
+
+	ptxmgmt->action_code = TDLS_DISCOVERY_REQUEST;
+	pmgntframe = alloc_mgtxmitframe(pxmitpriv);
+	if (pmgntframe == NULL)
+		goto exit;
+
+	pattrib = &pmgntframe->attrib;
+	pmgntframe->frame_tag = DATA_FRAMETAG;
+	pattrib->ether_type = 0x890d;
+
+	_rtw_memcpy(pattrib->dst, ptxmgmt->peer, ETH_ALEN);
+	_rtw_memcpy(pattrib->src, adapter_mac_addr(padapter), ETH_ALEN);
+	_rtw_memcpy(pattrib->ra, get_bssid(pmlmepriv), ETH_ALEN);
+	_rtw_memcpy(pattrib->ta, pattrib->src, ETH_ALEN);
+
+	update_tdls_attrib(padapter, pattrib);
+	pattrib->qsel = pattrib->priority;
+	if (rtw_xmit_tdls_coalesce(padapter, pmgntframe, ptxmgmt) != _SUCCESS) {
+		rtw_free_xmitbuf(pxmitpriv, pmgntframe->pxmitbuf);
+		rtw_free_xmitframe(pxmitpriv, pmgntframe);
+		goto exit;
+	}
+	dump_mgntframe(padapter, pmgntframe);
+	RTW_INFO("issue tdls dis req\n");
+
+	ret = _SUCCESS;
+exit:
+
+	return ret;
+}
+
+int issue_tdls_setup_rsp(_adapter *padapter, struct tdls_txmgmt *ptxmgmt)
+{
+	struct xmit_frame			*pmgntframe;
+	struct pkt_attrib			*pattrib;
+	struct xmit_priv			*pxmitpriv = &(padapter->xmitpriv);
+	int ret = _FAIL;
+
+	RTW_INFO("[TDLS] %s\n", __FUNCTION__);
+
+	ptxmgmt->action_code = TDLS_SETUP_RESPONSE;
+	pmgntframe = alloc_mgtxmitframe(pxmitpriv);
+	if (pmgntframe == NULL)
+		goto exit;
+
+	pattrib = &pmgntframe->attrib;
+	pmgntframe->frame_tag = DATA_FRAMETAG;
+	pattrib->ether_type = 0x890d;
+
+	_rtw_memcpy(pattrib->dst, ptxmgmt->peer, ETH_ALEN);
+	_rtw_memcpy(pattrib->src, adapter_mac_addr(padapter), ETH_ALEN);
+	_rtw_memcpy(pattrib->ra, get_bssid(&(padapter->mlmepriv)), ETH_ALEN);
+	_rtw_memcpy(pattrib->ta, pattrib->src, ETH_ALEN);
+
+	update_tdls_attrib(padapter, pattrib);
+	pattrib->qsel = pattrib->priority;
+	if (rtw_xmit_tdls_coalesce(padapter, pmgntframe, ptxmgmt) != _SUCCESS) {
+		rtw_free_xmitbuf(pxmitpriv, pmgntframe->pxmitbuf);
+		rtw_free_xmitframe(pxmitpriv, pmgntframe);
+		goto exit;
+	}
+
+	dump_mgntframe(padapter, pmgntframe);
+
+	ret = _SUCCESS;
+exit:
+
+	return ret;
+
+}
+
+int issue_tdls_setup_cfm(_adapter *padapter, struct tdls_txmgmt *ptxmgmt)
+{
+	struct tdls_info *ptdlsinfo = &padapter->tdlsinfo;
+	struct xmit_frame			*pmgntframe;
+	struct pkt_attrib			*pattrib;
+	struct xmit_priv			*pxmitpriv = &(padapter->xmitpriv);
+	int ret = _FAIL;
+
+	RTW_INFO("[TDLS] %s\n", __FUNCTION__);
+
+	ptxmgmt->action_code = TDLS_SETUP_CONFIRM;
+	pmgntframe = alloc_mgtxmitframe(pxmitpriv);
+	if (pmgntframe == NULL)
+		goto exit;
+
+	pattrib = &pmgntframe->attrib;
+	pmgntframe->frame_tag = DATA_FRAMETAG;
+	pattrib->ether_type = 0x890d;
+
+	_rtw_memcpy(pattrib->dst, ptxmgmt->peer, ETH_ALEN);
+	_rtw_memcpy(pattrib->src, adapter_mac_addr(padapter), ETH_ALEN);
+	_rtw_memcpy(pattrib->ra, get_bssid(&padapter->mlmepriv), ETH_ALEN);
+	_rtw_memcpy(pattrib->ta, pattrib->src, ETH_ALEN);
+
+	update_tdls_attrib(padapter, pattrib);
+	pattrib->qsel = pattrib->priority;
+	if (rtw_xmit_tdls_coalesce(padapter, pmgntframe, ptxmgmt) != _SUCCESS) {
+		rtw_free_xmitbuf(pxmitpriv, pmgntframe->pxmitbuf);
+		rtw_free_xmitframe(pxmitpriv, pmgntframe);
+		goto exit;
+	}
+
+	dump_mgntframe(padapter, pmgntframe);
+
+	ret = _SUCCESS;
+exit:
+
+	return ret;
+
+}
+
+/* TDLS Discovery Response frame is a management action frame */
+int issue_tdls_dis_rsp(_adapter *padapter, struct tdls_txmgmt *ptxmgmt, u8 privacy)
+{
+	struct xmit_frame		*pmgntframe;
+	struct pkt_attrib		*pattrib;
+	unsigned char			*pframe;
+	struct rtw_ieee80211_hdr	*pwlanhdr;
+	unsigned short		*fctrl;
+	struct xmit_priv		*pxmitpriv = &(padapter->xmitpriv);
+	struct mlme_ext_priv	*pmlmeext = &(padapter->mlmeextpriv);
+	int ret = _FAIL;
+
+	RTW_INFO("[TDLS] %s\n", __FUNCTION__);
+
+	pmgntframe = alloc_mgtxmitframe(pxmitpriv);
+	if (pmgntframe == NULL)
+		goto exit;
+
+	pattrib = &pmgntframe->attrib;
+	update_mgntframe_attrib(padapter, pattrib);
+
+	_rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET);
+
+	pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET;
+	pwlanhdr = (struct rtw_ieee80211_hdr *)pframe;
+
+	fctrl = &(pwlanhdr->frame_ctl);
+	*(fctrl) = 0;
+
+	/* unicast probe request frame */
+	_rtw_memcpy(pwlanhdr->addr1, ptxmgmt->peer, ETH_ALEN);
+	_rtw_memcpy(pattrib->dst, pwlanhdr->addr1, ETH_ALEN);
+	_rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN);
+	_rtw_memcpy(pattrib->src, pwlanhdr->addr2, ETH_ALEN);
+	_rtw_memcpy(pwlanhdr->addr3, get_bssid(&padapter->mlmepriv), ETH_ALEN);
+	_rtw_memcpy(pattrib->ra, pwlanhdr->addr3, ETH_ALEN);
+
+	SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq);
+	pmlmeext->mgnt_seq++;
+	set_frame_sub_type(pframe, WIFI_ACTION);
+
+	pframe += sizeof(struct rtw_ieee80211_hdr_3addr);
+	pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr);
+
+	rtw_build_tdls_dis_rsp_ies(padapter, pmgntframe, pframe, ptxmgmt, privacy);
+
+	pattrib->nr_frags = 1;
+	pattrib->last_txcmdsz = pattrib->pktlen;
+
+	dump_mgntframe(padapter, pmgntframe);
+	ret = _SUCCESS;
+
+exit:
+	return ret;
+}
+
+int issue_tdls_peer_traffic_rsp(_adapter *padapter, struct sta_info *ptdls_sta, struct tdls_txmgmt *ptxmgmt)
+{
+	struct xmit_frame	*pmgntframe;
+	struct pkt_attrib	*pattrib;
+	struct mlme_priv	*pmlmepriv = &padapter->mlmepriv;
+	struct xmit_priv	*pxmitpriv = &(padapter->xmitpriv);
+	int ret = _FAIL;
+
+	RTW_INFO("[TDLS] %s\n", __FUNCTION__);
+
+	ptxmgmt->action_code = TDLS_PEER_TRAFFIC_RESPONSE;
+
+	pmgntframe = alloc_mgtxmitframe(pxmitpriv);
+	if (pmgntframe == NULL)
+		goto exit;
+
+	pattrib = &pmgntframe->attrib;
+
+	pmgntframe->frame_tag = DATA_FRAMETAG;
+	pattrib->ether_type = 0x890d;
+
+	_rtw_memcpy(pattrib->dst, ptdls_sta->cmn.mac_addr, ETH_ALEN);
+	_rtw_memcpy(pattrib->src, adapter_mac_addr(padapter), ETH_ALEN);
+	_rtw_memcpy(pattrib->ra, ptdls_sta->cmn.mac_addr, ETH_ALEN);
+	_rtw_memcpy(pattrib->ta, pattrib->src, ETH_ALEN);
+
+	update_tdls_attrib(padapter, pattrib);
+	pattrib->qsel = pattrib->priority;
+
+	if (rtw_xmit_tdls_coalesce(padapter, pmgntframe, ptxmgmt) != _SUCCESS) {
+		rtw_free_xmitbuf(pxmitpriv, pmgntframe->pxmitbuf);
+		rtw_free_xmitframe(pxmitpriv, pmgntframe);
+		goto exit;
+	}
+
+	dump_mgntframe(padapter, pmgntframe);
+	ret = _SUCCESS;
+
+exit:
+
+	return ret;
+}
+
+int issue_tdls_peer_traffic_indication(_adapter *padapter, struct sta_info *ptdls_sta)
+{
+	struct xmit_frame			*pmgntframe;
+	struct pkt_attrib			*pattrib;
+	struct mlme_priv	*pmlmepriv = &padapter->mlmepriv;
+	struct xmit_priv			*pxmitpriv = &(padapter->xmitpriv);
+	struct tdls_txmgmt txmgmt;
+	int ret = _FAIL;
+
+	RTW_INFO("[TDLS] %s\n", __FUNCTION__);
+
+	_rtw_memset(&txmgmt, 0x00, sizeof(struct tdls_txmgmt));
+	txmgmt.action_code = TDLS_PEER_TRAFFIC_INDICATION;
+
+	pmgntframe = alloc_mgtxmitframe(pxmitpriv);
+	if (pmgntframe == NULL)
+		goto exit;
+
+	pattrib = &pmgntframe->attrib;
+
+	pmgntframe->frame_tag = DATA_FRAMETAG;
+	pattrib->ether_type = 0x890d;
+
+	_rtw_memcpy(pattrib->dst, ptdls_sta->cmn.mac_addr, ETH_ALEN);
+	_rtw_memcpy(pattrib->src, adapter_mac_addr(padapter), ETH_ALEN);
+	_rtw_memcpy(pattrib->ra, get_bssid(pmlmepriv), ETH_ALEN);
+	_rtw_memcpy(pattrib->ta, pattrib->src, ETH_ALEN);
+
+	/* PTI frame's priority should be AC_VO */
+	pattrib->priority = 7;
+
+	update_tdls_attrib(padapter, pattrib);
+	pattrib->qsel = pattrib->priority;
+	if (rtw_xmit_tdls_coalesce(padapter, pmgntframe, &txmgmt) != _SUCCESS) {
+		rtw_free_xmitbuf(pxmitpriv, pmgntframe->pxmitbuf);
+		rtw_free_xmitframe(pxmitpriv, pmgntframe);
+		goto exit;
+	}
+
+	dump_mgntframe(padapter, pmgntframe);
+	ret = _SUCCESS;
+
+exit:
+
+	return ret;
+}
+
+#ifdef CONFIG_TDLS_CH_SW
+int issue_tdls_ch_switch_req(_adapter *padapter, struct sta_info *ptdls_sta)
+{
+	struct xmit_frame	*pmgntframe;
+	struct pkt_attrib	*pattrib;
+	struct mlme_priv	*pmlmepriv = &padapter->mlmepriv;
+	struct xmit_priv	*pxmitpriv = &(padapter->xmitpriv);
+	struct tdls_txmgmt txmgmt;
+	int ret = _FAIL;
+
+	RTW_INFO("[TDLS] %s\n", __FUNCTION__);
+
+	if (rtw_tdls_is_chsw_allowed(padapter) == _FALSE) {
+		RTW_INFO("[TDLS] Ignore %s since channel switch is not allowed\n", __func__);
+		goto exit;
+	}
+
+	_rtw_memset(&txmgmt, 0x00, sizeof(struct tdls_txmgmt));
+	txmgmt.action_code = TDLS_CHANNEL_SWITCH_REQUEST;
+
+	pmgntframe = alloc_mgtxmitframe(pxmitpriv);
+	if (pmgntframe == NULL)
+		goto exit;
+
+	pattrib = &pmgntframe->attrib;
+
+	pmgntframe->frame_tag = DATA_FRAMETAG;
+	pattrib->ether_type = 0x890d;
+
+	_rtw_memcpy(pattrib->dst, ptdls_sta->cmn.mac_addr, ETH_ALEN);
+	_rtw_memcpy(pattrib->src, adapter_mac_addr(padapter), ETH_ALEN);
+	_rtw_memcpy(pattrib->ra, ptdls_sta->cmn.mac_addr, ETH_ALEN);
+	_rtw_memcpy(pattrib->ta, pattrib->src, ETH_ALEN);
+
+	update_tdls_attrib(padapter, pattrib);
+	pattrib->qsel = pattrib->priority;
+	if (rtw_xmit_tdls_coalesce(padapter, pmgntframe, &txmgmt) != _SUCCESS) {
+		rtw_free_xmitbuf(pxmitpriv, pmgntframe->pxmitbuf);
+		rtw_free_xmitframe(pxmitpriv, pmgntframe);
+		goto exit;
+	}
+
+	dump_mgntframe(padapter, pmgntframe);
+	ret = _SUCCESS;
+exit:
+
+	return ret;
+}
+
+int issue_tdls_ch_switch_rsp(_adapter *padapter, struct tdls_txmgmt *ptxmgmt, int wait_ack)
+{
+	struct xmit_frame	*pmgntframe;
+	struct pkt_attrib	*pattrib;
+	struct mlme_priv	*pmlmepriv = &padapter->mlmepriv;
+	struct xmit_priv	*pxmitpriv = &(padapter->xmitpriv);
+	int ret = _FAIL;
+
+	RTW_INFO("[TDLS] %s\n", __FUNCTION__);
+
+	if (rtw_tdls_is_chsw_allowed(padapter) == _FALSE) {
+		RTW_INFO("[TDLS] Ignore %s since channel switch is not allowed\n", __func__);
+		goto exit;
+	}
+
+	ptxmgmt->action_code = TDLS_CHANNEL_SWITCH_RESPONSE;
+
+	pmgntframe = alloc_mgtxmitframe(pxmitpriv);
+	if (pmgntframe == NULL)
+		goto exit;
+
+	pattrib = &pmgntframe->attrib;
+
+	pmgntframe->frame_tag = DATA_FRAMETAG;
+	pattrib->ether_type = 0x890d;
+
+	_rtw_memcpy(pattrib->dst, ptxmgmt->peer, ETH_ALEN);
+	_rtw_memcpy(pattrib->src, adapter_mac_addr(padapter), ETH_ALEN);
+	_rtw_memcpy(pattrib->ra, ptxmgmt->peer, ETH_ALEN);
+	_rtw_memcpy(pattrib->ta, pattrib->src, ETH_ALEN);
+
+	update_tdls_attrib(padapter, pattrib);
+	pattrib->qsel = pattrib->priority;
+	/*
+		_enter_critical_bh(&pxmitpriv->lock, &irqL);
+		if(xmitframe_enqueue_for_tdls_sleeping_sta(padapter, pmgntframe)==_TRUE){
+			_exit_critical_bh(&pxmitpriv->lock, &irqL);
+			return _FALSE;
+		}
+	*/
+	if (rtw_xmit_tdls_coalesce(padapter, pmgntframe, ptxmgmt) != _SUCCESS) {
+		rtw_free_xmitbuf(pxmitpriv, pmgntframe->pxmitbuf);
+		rtw_free_xmitframe(pxmitpriv, pmgntframe);
+		goto exit;
+	}
+
+	if (wait_ack)
+		ret = dump_mgntframe_and_wait_ack_timeout(padapter, pmgntframe, 10);
+	else {
+		dump_mgntframe(padapter, pmgntframe);
+		ret = _SUCCESS;
+	}
+exit:
+
+	return ret;
+}
+#endif
+
+int On_TDLS_Dis_Rsp(_adapter *padapter, union recv_frame *precv_frame)
+{
+	struct sta_info *ptdls_sta = NULL, *psta = rtw_get_stainfo(&(padapter->stapriv), get_bssid(&(padapter->mlmepriv)));
+	struct recv_priv *precvpriv = &(padapter->recvpriv);
+	u8 *ptr = precv_frame->u.hdr.rx_data, *psa;
+	struct rx_pkt_attrib *pattrib = &(precv_frame->u.hdr.attrib);
+	struct tdls_info *ptdlsinfo = &(padapter->tdlsinfo);
+	u8 empty_addr[ETH_ALEN] = { 0x00 };
+	int rssi = 0;
+	struct tdls_txmgmt txmgmt;
+	int ret = _SUCCESS;
+
+	if (psta)
+		rssi = psta->cmn.rssi_stat.rssi;
+
+	_rtw_memset(&txmgmt, 0x00, sizeof(struct tdls_txmgmt));
+	/* WFDTDLS: for sigma test, not to setup direct link automatically */
+	ptdlsinfo->dev_discovered = _TRUE;
+
+	psa = get_sa(ptr);
+	ptdls_sta = rtw_get_stainfo(&(padapter->stapriv), psa);
+	if (ptdls_sta != NULL)
+		ptdls_sta->sta_stats.rx_tdls_disc_rsp_pkts++;
+
+#ifdef CONFIG_TDLS_AUTOSETUP
+	if (ptdls_sta != NULL) {
+		/* Record the tdls sta with lowest signal strength */
+		if (ptdlsinfo->sta_maximum == _TRUE && ptdls_sta->alive_count >= 1) {
+			if (_rtw_memcmp(ptdlsinfo->ss_record.macaddr, empty_addr, ETH_ALEN)) {
+				_rtw_memcpy(ptdlsinfo->ss_record.macaddr, psa, ETH_ALEN);
+				ptdlsinfo->ss_record.RxPWDBAll = pattrib->phy_info.rx_pwdb_all;
+			} else {
+				if (ptdlsinfo->ss_record.RxPWDBAll < pattrib->phy_info.rx_pwdb_all) {
+					_rtw_memcpy(ptdlsinfo->ss_record.macaddr, psa, ETH_ALEN);
+					ptdlsinfo->ss_record.RxPWDBAll = pattrib->phy_info.rx_pwdb_all;
+				}
+			}
+		}
+	} else {
+		if (ptdlsinfo->sta_maximum == _TRUE) {
+			if (_rtw_memcmp(ptdlsinfo->ss_record.macaddr, empty_addr, ETH_ALEN)) {
+				/* All traffics are busy, do not set up another direct link. */
+				ret = _FAIL;
+				goto exit;
+			} else {
+				if (pattrib->phy_info.rx_pwdb_all > ptdlsinfo->ss_record.RxPWDBAll) {
+					_rtw_memcpy(txmgmt.peer, ptdlsinfo->ss_record.macaddr, ETH_ALEN);
+					/* issue_tdls_teardown(padapter, ptdlsinfo->ss_record.macaddr, _FALSE); */
+				} else {
+					ret = _FAIL;
+					goto exit;
+				}
+			}
+		}
+
+
+		if (pattrib->phy_info.rx_pwdb_all + TDLS_SIGNAL_THRESH >= rssi) {
+			RTW_INFO("pattrib->RxPWDBAll=%d, pdmpriv->undecorated_smoothed_pwdb=%d\n", pattrib->phy_info.rx_pwdb_all, rssi);
+			_rtw_memcpy(txmgmt.peer, psa, ETH_ALEN);
+			issue_tdls_setup_req(padapter, &txmgmt, _FALSE);
+		}
+	}
+#endif /* CONFIG_TDLS_AUTOSETUP */
+
+exit:
+	return ret;
+
+}
+
+sint On_TDLS_Setup_Req(_adapter *padapter, union recv_frame *precv_frame, struct sta_info *ptdls_sta)
+{
+	struct tdls_info *ptdlsinfo = &padapter->tdlsinfo;
+	u8 *psa, *pmyid;
+	struct sta_priv *pstapriv = &padapter->stapriv;
+	u8 *ptr = precv_frame->u.hdr.rx_data;
+	struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
+	struct security_priv *psecuritypriv = &padapter->securitypriv;
+	_irqL irqL;
+	struct rx_pkt_attrib	*prx_pkt_attrib = &precv_frame->u.hdr.attrib;
+	u8 *prsnie, *ppairwise_cipher;
+	u8 i, k;
+	u8 ccmp_included = 0, rsnie_included = 0;
+	u16 j, pairwise_count;
+	u8 SNonce[32];
+	u32 timeout_interval = TDLS_TPK_RESEND_COUNT;
+	sint parsing_length;	/* Frame body length, without icv_len */
+	PNDIS_802_11_VARIABLE_IEs	pIE;
+	u8 FIXED_IE = 5;
+	unsigned char		supportRate[16];
+	int				supportRateNum = 0;
+	struct tdls_txmgmt txmgmt;
+
+	if (rtw_tdls_is_setup_allowed(padapter) == _FALSE)
+		goto exit;
+
+	_rtw_memset(&txmgmt, 0x00, sizeof(struct tdls_txmgmt));
+	psa = get_sa(ptr);
+
+	if (ptdlsinfo->sta_maximum == _TRUE) {
+		if (ptdls_sta == NULL)
+			goto exit;
+		else if (!(ptdls_sta->tdls_sta_state & TDLS_LINKED_STATE))
+			goto exit;
+	}
+
+	pmyid = adapter_mac_addr(padapter);
+	ptr += prx_pkt_attrib->hdrlen + prx_pkt_attrib->iv_len + LLC_HEADER_SIZE + ETH_TYPE_LEN + PAYLOAD_TYPE_LEN;
+	parsing_length = ((union recv_frame *)precv_frame)->u.hdr.len
+			 - prx_pkt_attrib->hdrlen
+			 - prx_pkt_attrib->iv_len
+			 - prx_pkt_attrib->icv_len
+			 - LLC_HEADER_SIZE
+			 - ETH_TYPE_LEN
+			 - PAYLOAD_TYPE_LEN;
+
+	if (ptdls_sta == NULL) {
+		ptdls_sta = rtw_alloc_stainfo(pstapriv, psa);
+		if (ptdls_sta == NULL)
+			goto exit;
+		
+		ptdlsinfo->sta_cnt++;
+	}
+	else {
+		if (ptdls_sta->tdls_sta_state & TDLS_LINKED_STATE) {
+			/* If the direct link is already set up */
+			/* Process as re-setup after tear down */
+			RTW_INFO("re-setup a direct link\n");
+		}
+		/* Already receiving TDLS setup request */
+		else if (ptdls_sta->tdls_sta_state & TDLS_INITIATOR_STATE) {
+			RTW_INFO("receive duplicated TDLS setup request frame in handshaking\n");
+			goto exit;
+		}
+		/* When receiving and sending setup_req to the same link at the same time */
+		/* STA with higher MAC_addr would be initiator */
+		else if (ptdls_sta->tdls_sta_state & TDLS_RESPONDER_STATE) {
+			RTW_INFO("receive setup_req after sending setup_req\n");
+			for (i = 0; i < 6; i++) {
+				if (*(pmyid + i) == *(psa + i)) {
+				} else if (*(pmyid + i) > *(psa + i)) {
+					ptdls_sta->tdls_sta_state = TDLS_INITIATOR_STATE;
+					break;
+				} else if (*(pmyid + i) < *(psa + i))
+					goto exit;
+			}
+		}
+	}
+
+	if (ptdls_sta) {
+		txmgmt.dialog_token = *(ptr + 2);	/* Copy dialog token */
+		txmgmt.status_code = _STATS_SUCCESSFUL_;
+
+		/* Parsing information element */
+		for (j = FIXED_IE; j < parsing_length;) {
+
+			pIE = (PNDIS_802_11_VARIABLE_IEs)(ptr + j);
+
+			switch (pIE->ElementID) {
+			case _SUPPORTEDRATES_IE_:
+				_rtw_memcpy(supportRate, pIE->data, pIE->Length);
+				supportRateNum = pIE->Length;
+				break;
+			case _COUNTRY_IE_:
+				break;
+			case _EXT_SUPPORTEDRATES_IE_:
+				if (supportRateNum < sizeof(supportRate)) {
+					_rtw_memcpy(supportRate + supportRateNum, pIE->data, pIE->Length);
+					supportRateNum += pIE->Length;
+				}
+				break;
+			case _SUPPORTED_CH_IE_:
+				break;
+			case _RSN_IE_2_:
+				rsnie_included = 1;
+				if (prx_pkt_attrib->encrypt) {
+					prsnie = (u8 *)pIE;
+					/* Check CCMP pairwise_cipher presence. */
+					ppairwise_cipher = prsnie + 10;
+					_rtw_memcpy(ptdls_sta->TDLS_RSNIE, pIE->data, pIE->Length);
+					pairwise_count = *(u16 *)(ppairwise_cipher - 2);
+					for (k = 0; k < pairwise_count; k++) {
+						if (_rtw_memcmp(ppairwise_cipher + 4 * k, RSN_CIPHER_SUITE_CCMP, 4) == _TRUE)
+							ccmp_included = 1;
+					}
+
+					if (ccmp_included == 0)
+						txmgmt.status_code = _STATS_INVALID_RSNIE_;
+				}
+				break;
+			case _EXT_CAP_IE_:
+				break;
+			case _VENDOR_SPECIFIC_IE_:
+				break;
+			case _FTIE_:
+				if (prx_pkt_attrib->encrypt)
+					_rtw_memcpy(SNonce, (ptr + j + 52), 32);
+				break;
+			case _TIMEOUT_ITVL_IE_:
+				if (prx_pkt_attrib->encrypt)
+					timeout_interval = cpu_to_le32(*(u32 *)(ptr + j + 3));
+				break;
+			case _RIC_Descriptor_IE_:
+				break;
+#ifdef CONFIG_80211N_HT
+			case _HT_CAPABILITY_IE_:
+				rtw_tdls_process_ht_cap(padapter, ptdls_sta, pIE->data, pIE->Length);
+				break;
+#endif
+#ifdef CONFIG_80211AC_VHT
+			case EID_AID:
+				break;
+			case EID_VHTCapability:
+				rtw_tdls_process_vht_cap(padapter, ptdls_sta, pIE->data, pIE->Length);
+				break;
+#endif
+			case EID_BSSCoexistence:
+				break;
+			case _LINK_ID_IE_:
+				if (_rtw_memcmp(get_bssid(pmlmepriv), pIE->data, 6) == _FALSE)
+					txmgmt.status_code = _STATS_NOT_IN_SAME_BSS_;
+				break;
+			default:
+				break;
+			}
+
+			j += (pIE->Length + 2);
+
+		}
+
+		/* Check status code */
+		/* If responder STA has/hasn't security on AP, but request hasn't/has RSNIE, it should reject */
+		if (txmgmt.status_code == _STATS_SUCCESSFUL_) {
+			if (rsnie_included && prx_pkt_attrib->encrypt == 0)
+				txmgmt.status_code = _STATS_SEC_DISABLED_;
+			else if (rsnie_included == 0 && prx_pkt_attrib->encrypt)
+				txmgmt.status_code = _STATS_INVALID_PARAMETERS_;
+
+#ifdef CONFIG_WFD
+			/* WFD test plan version 0.18.2 test item 5.1.5 */
+			/* SoUT does not use TDLS if AP uses weak security */
+			if (padapter->wdinfo.wfd_tdls_enable && (rsnie_included && prx_pkt_attrib->encrypt != _AES_))
+				txmgmt.status_code = _STATS_SEC_DISABLED_;
+#endif /* CONFIG_WFD */
+		}
+
+		ptdls_sta->tdls_sta_state |= TDLS_INITIATOR_STATE;
+		if (prx_pkt_attrib->encrypt) {
+			_rtw_memcpy(ptdls_sta->SNonce, SNonce, 32);
+
+			if (timeout_interval <= 300)
+				ptdls_sta->TDLS_PeerKey_Lifetime = TDLS_TPK_RESEND_COUNT;
+			else
+				ptdls_sta->TDLS_PeerKey_Lifetime = timeout_interval;
+		}
+
+		/* Update station supportRate */
+		ptdls_sta->bssratelen = supportRateNum;
+		_rtw_memcpy(ptdls_sta->bssrateset, supportRate, supportRateNum);
+
+		/* -2: AP + BC/MC sta, -4: default key */
+		if (ptdlsinfo->sta_cnt == MAX_ALLOWED_TDLS_STA_NUM)
+			ptdlsinfo->sta_maximum = _TRUE;
+
+#ifdef CONFIG_WFD
+		rtw_tdls_process_wfd_ie(ptdlsinfo, ptr + FIXED_IE, parsing_length);
+#endif
+
+	} else
+		goto exit;
+
+	_rtw_memcpy(txmgmt.peer, prx_pkt_attrib->src, ETH_ALEN);
+
+	if (rtw_tdls_is_driver_setup(padapter)) {
+		issue_tdls_setup_rsp(padapter, &txmgmt);
+
+		if (txmgmt.status_code == _STATS_SUCCESSFUL_)
+			_set_timer(&ptdls_sta->handshake_timer, TDLS_HANDSHAKE_TIME);
+		else {
+			rtw_tdls_teardown_pre_hdl(padapter, ptdls_sta);
+			rtw_tdls_cmd(padapter, ptdls_sta->cmn.mac_addr, TDLS_TEARDOWN_STA_LOCALLY_POST);
+		}
+	}
+
+exit:
+
+	return _SUCCESS;
+}
+
+int On_TDLS_Setup_Rsp(_adapter *padapter, union recv_frame *precv_frame, struct sta_info *ptdls_sta)
+{
+	struct registry_priv	*pregistrypriv = &padapter->registrypriv;
+	struct tdls_info *ptdlsinfo = &padapter->tdlsinfo;
+	struct sta_priv *pstapriv = &padapter->stapriv;
+	u8 *ptr = precv_frame->u.hdr.rx_data;
+	_irqL irqL;
+	struct rx_pkt_attrib	*prx_pkt_attrib = &precv_frame->u.hdr.attrib;
+	u8 *psa;
+	u16 status_code = 0;
+	sint parsing_length;	/* Frame body length, without icv_len */
+	PNDIS_802_11_VARIABLE_IEs	pIE;
+	u8 FIXED_IE = 7;
+	u8 ANonce[32];
+	u8  *pftie = NULL, *ptimeout_ie = NULL, *plinkid_ie = NULL, *prsnie = NULL, *pftie_mic = NULL, *ppairwise_cipher = NULL;
+	u16 pairwise_count, j, k;
+	u8 verify_ccmp = 0;
+	unsigned char		supportRate[16];
+	int				supportRateNum = 0;
+	struct tdls_txmgmt txmgmt;
+	int ret = _SUCCESS;
+	u32 timeout_interval = TDLS_TPK_RESEND_COUNT;
+
+	_rtw_memset(&txmgmt, 0x00, sizeof(struct tdls_txmgmt));
+	psa = get_sa(ptr);
+
+	ptr += prx_pkt_attrib->hdrlen + prx_pkt_attrib->iv_len + LLC_HEADER_SIZE + ETH_TYPE_LEN + PAYLOAD_TYPE_LEN;
+	parsing_length = ((union recv_frame *)precv_frame)->u.hdr.len
+			 - prx_pkt_attrib->hdrlen
+			 - prx_pkt_attrib->iv_len
+			 - prx_pkt_attrib->icv_len
+			 - LLC_HEADER_SIZE
+			 - ETH_TYPE_LEN
+			 - PAYLOAD_TYPE_LEN;
+
+	_rtw_memcpy(&status_code, ptr + 2, 2);
+
+	if (status_code != 0) {
+		RTW_INFO("[TDLS] %s status_code = %d, free_tdls_sta\n", __FUNCTION__, status_code);
+		rtw_tdls_teardown_pre_hdl(padapter, ptdls_sta);
+		rtw_tdls_cmd(padapter, ptdls_sta->cmn.mac_addr, TDLS_TEARDOWN_STA_LOCALLY_POST);
+		ret = _FAIL;
+		goto exit;
+	}
+
+	status_code = 0;
+
+	/* parsing information element */
+	for (j = FIXED_IE; j < parsing_length;) {
+		pIE = (PNDIS_802_11_VARIABLE_IEs)(ptr + j);
+
+		switch (pIE->ElementID) {
+		case _SUPPORTEDRATES_IE_:
+			_rtw_memcpy(supportRate, pIE->data, pIE->Length);
+			supportRateNum = pIE->Length;
+			break;
+		case _COUNTRY_IE_:
+			break;
+		case _EXT_SUPPORTEDRATES_IE_:
+			if (supportRateNum < sizeof(supportRate)) {
+				_rtw_memcpy(supportRate + supportRateNum, pIE->data, pIE->Length);
+				supportRateNum += pIE->Length;
+			}
+			break;
+		case _SUPPORTED_CH_IE_:
+			break;
+		case _RSN_IE_2_:
+			prsnie = (u8 *)pIE;
+			/* Check CCMP pairwise_cipher presence. */
+			ppairwise_cipher = prsnie + 10;
+			_rtw_memcpy(&pairwise_count, (u16 *)(ppairwise_cipher - 2), 2);
+			for (k = 0; k < pairwise_count; k++) {
+				if (_rtw_memcmp(ppairwise_cipher + 4 * k, RSN_CIPHER_SUITE_CCMP, 4) == _TRUE)
+					verify_ccmp = 1;
+			}
+		case _EXT_CAP_IE_:
+			break;
+		case _VENDOR_SPECIFIC_IE_:
+			if (_rtw_memcmp((u8 *)pIE + 2, WMM_INFO_OUI, 6) == _TRUE) {
+				/* WMM Info ID and OUI */
+				if ((pregistrypriv->wmm_enable == _TRUE) || (padapter->mlmepriv.htpriv.ht_option == _TRUE))
+					ptdls_sta->qos_option = _TRUE;
+			}
+			break;
+		case _FTIE_:
+			pftie = (u8 *)pIE;
+			_rtw_memcpy(ANonce, (ptr + j + 20), 32);
+			break;
+		case _TIMEOUT_ITVL_IE_:
+			ptimeout_ie = (u8 *)pIE;
+			timeout_interval = cpu_to_le32(*(u32 *)(ptimeout_ie + 3));
+			break;
+		case _RIC_Descriptor_IE_:
+			break;
+#ifdef CONFIG_80211N_HT
+		case _HT_CAPABILITY_IE_:
+			rtw_tdls_process_ht_cap(padapter, ptdls_sta, pIE->data, pIE->Length);
+			break;
+#endif
+#ifdef CONFIG_80211AC_VHT
+		case EID_AID:
+			/* todo in the future if necessary */
+			break;
+		case EID_VHTCapability:
+			rtw_tdls_process_vht_cap(padapter, ptdls_sta, pIE->data, pIE->Length);
+			break;
+		case EID_OpModeNotification:
+			rtw_tdls_process_vht_op_mode_notify(padapter, ptdls_sta, pIE->data, pIE->Length);
+			break;
+#endif
+		case EID_BSSCoexistence:
+			break;
+		case _LINK_ID_IE_:
+			plinkid_ie = (u8 *)pIE;
+			break;
+		default:
+			break;
+		}
+
+		j += (pIE->Length + 2);
+
+	}
+
+	ptdls_sta->bssratelen = supportRateNum;
+	_rtw_memcpy(ptdls_sta->bssrateset, supportRate, supportRateNum);
+	_rtw_memcpy(ptdls_sta->ANonce, ANonce, 32);
+
+#ifdef CONFIG_WFD
+	rtw_tdls_process_wfd_ie(ptdlsinfo, ptr + FIXED_IE, parsing_length);
+#endif
+
+	if (prx_pkt_attrib->encrypt) {
+		if (verify_ccmp == 1) {
+			txmgmt.status_code = _STATS_SUCCESSFUL_;
+			if (rtw_tdls_is_driver_setup(padapter) == _TRUE) {
+				wpa_tdls_generate_tpk(padapter, ptdls_sta);
+				if (tdls_verify_mic(ptdls_sta->tpk.kck, 2, plinkid_ie, prsnie, ptimeout_ie, pftie) == _FAIL) {
+					RTW_INFO("[TDLS] %s tdls_verify_mic fail, free_tdls_sta\n", __FUNCTION__);
+					rtw_tdls_teardown_pre_hdl(padapter, ptdls_sta);
+					rtw_tdls_cmd(padapter, ptdls_sta->cmn.mac_addr, TDLS_TEARDOWN_STA_LOCALLY_POST);
+					ret = _FAIL;
+					goto exit;
+				}
+				ptdls_sta->TDLS_PeerKey_Lifetime = timeout_interval;
+			}
+		} else
+			txmgmt.status_code = _STATS_INVALID_RSNIE_;
+	} else
+		txmgmt.status_code = _STATS_SUCCESSFUL_;
+
+	if (rtw_tdls_is_driver_setup(padapter) == _TRUE) {
+		_rtw_memcpy(txmgmt.peer, prx_pkt_attrib->src, ETH_ALEN);
+		issue_tdls_setup_cfm(padapter, &txmgmt);
+
+		if (txmgmt.status_code == _STATS_SUCCESSFUL_) {
+			rtw_tdls_set_link_established(padapter, _TRUE);
+
+			if (ptdls_sta->tdls_sta_state & TDLS_RESPONDER_STATE) {
+				ptdls_sta->tdls_sta_state |= TDLS_LINKED_STATE;
+				ptdls_sta->state |= _FW_LINKED;
+				_cancel_timer_ex(&ptdls_sta->handshake_timer);
+			}
+
+			if (prx_pkt_attrib->encrypt)
+				rtw_tdls_set_key(padapter, ptdls_sta);
+
+			rtw_tdls_cmd(padapter, ptdls_sta->cmn.mac_addr, TDLS_ESTABLISHED);
+
+		}
+	}
+
+exit:
+	if (rtw_tdls_is_driver_setup(padapter) == _TRUE)
+		return ret;
+	else
+		return _SUCCESS;
+
+}
+
+int On_TDLS_Setup_Cfm(_adapter *padapter, union recv_frame *precv_frame, struct sta_info *ptdls_sta)
+{
+	struct tdls_info *ptdlsinfo = &padapter->tdlsinfo;
+	struct sta_priv *pstapriv = &padapter->stapriv;
+	u8 *ptr = precv_frame->u.hdr.rx_data;
+	_irqL irqL;
+	struct rx_pkt_attrib	*prx_pkt_attrib = &precv_frame->u.hdr.attrib;
+	u8 *psa;
+	u16 status_code = 0;
+	sint parsing_length;
+	PNDIS_802_11_VARIABLE_IEs	pIE;
+	u8 FIXED_IE = 5;
+	u8  *pftie = NULL, *ptimeout_ie = NULL, *plinkid_ie = NULL, *prsnie = NULL, *pftie_mic = NULL, *ppairwise_cipher = NULL;
+	u16 j, pairwise_count;
+	int ret = _SUCCESS;
+
+	psa = get_sa(ptr);
+
+	ptr += prx_pkt_attrib->hdrlen + prx_pkt_attrib->iv_len + LLC_HEADER_SIZE + ETH_TYPE_LEN + PAYLOAD_TYPE_LEN;
+	parsing_length = ((union recv_frame *)precv_frame)->u.hdr.len
+			 - prx_pkt_attrib->hdrlen
+			 - prx_pkt_attrib->iv_len
+			 - prx_pkt_attrib->icv_len
+			 - LLC_HEADER_SIZE
+			 - ETH_TYPE_LEN
+			 - PAYLOAD_TYPE_LEN;
+
+	_rtw_memcpy(&status_code, ptr + 2, 2);
+
+	if (status_code != 0) {
+		RTW_INFO("[%s] status_code = %d\n, free_tdls_sta", __FUNCTION__, status_code);
+		rtw_tdls_teardown_pre_hdl(padapter, ptdls_sta);
+		rtw_tdls_cmd(padapter, ptdls_sta->cmn.mac_addr, TDLS_TEARDOWN_STA_LOCALLY_POST);
+		ret = _FAIL;
+		goto exit;
+	}
+
+	/* Parsing information element */
+	for (j = FIXED_IE; j < parsing_length;) {
+
+		pIE = (PNDIS_802_11_VARIABLE_IEs)(ptr + j);
+
+		switch (pIE->ElementID) {
+		case _RSN_IE_2_:
+			prsnie = (u8 *)pIE;
+			break;
+		case _VENDOR_SPECIFIC_IE_:
+			if (_rtw_memcmp((u8 *)pIE + 2, WMM_PARA_OUI, 6) == _TRUE) {
+				/* WMM Parameter ID and OUI */
+				ptdls_sta->qos_option = _TRUE;
+			}
+			break;
+		case _FTIE_:
+			pftie = (u8 *)pIE;
+			break;
+		case _TIMEOUT_ITVL_IE_:
+			ptimeout_ie = (u8 *)pIE;
+			break;
+#ifdef CONFIG_80211N_HT
+		case _HT_EXTRA_INFO_IE_:
+			break;
+#endif
+#ifdef CONFIG_80211AC_VHT
+		case EID_VHTOperation:
+			rtw_tdls_process_vht_operation(padapter, ptdls_sta, pIE->data, pIE->Length);
+			break;
+		case EID_OpModeNotification:
+			rtw_tdls_process_vht_op_mode_notify(padapter, ptdls_sta, pIE->data, pIE->Length);
+			break;
+#endif
+		case _LINK_ID_IE_:
+			plinkid_ie = (u8 *)pIE;
+			break;
+		default:
+			break;
+		}
+
+		j += (pIE->Length + 2);
+
+	}
+
+	if (prx_pkt_attrib->encrypt) {
+		/* Verify mic in FTIE MIC field */
+		if (rtw_tdls_is_driver_setup(padapter) &&
+		    (tdls_verify_mic(ptdls_sta->tpk.kck, 3, plinkid_ie, prsnie, ptimeout_ie, pftie) == _FAIL)) {
+			rtw_tdls_teardown_pre_hdl(padapter, ptdls_sta);
+			rtw_tdls_cmd(padapter, ptdls_sta->cmn.mac_addr, TDLS_TEARDOWN_STA_LOCALLY_POST);
+			ret = _FAIL;
+			goto exit;
+		}
+	}
+
+	if (rtw_tdls_is_driver_setup(padapter)) {
+		rtw_tdls_set_link_established(padapter, _TRUE);
+
+		if (ptdls_sta->tdls_sta_state & TDLS_INITIATOR_STATE) {
+			ptdls_sta->tdls_sta_state |= TDLS_LINKED_STATE;
+			ptdls_sta->state |= _FW_LINKED;
+			_cancel_timer_ex(&ptdls_sta->handshake_timer);
+		}
+
+		if (prx_pkt_attrib->encrypt) {
+			rtw_tdls_set_key(padapter, ptdls_sta);
+
+			/* Start  TPK timer */
+			ptdls_sta->TPK_count = 0;
+			_set_timer(&ptdls_sta->TPK_timer, ONE_SEC);
+		}
+
+		rtw_tdls_cmd(padapter, ptdls_sta->cmn.mac_addr, TDLS_ESTABLISHED);
+	}
+
+exit:
+	return ret;
+
+}
+
+int On_TDLS_Dis_Req(_adapter *padapter, union recv_frame *precv_frame)
+{
+	struct rx_pkt_attrib	*prx_pkt_attrib = &precv_frame->u.hdr.attrib;
+	struct sta_priv *pstapriv = &padapter->stapriv;
+	struct sta_info *psta_ap;
+	u8 *ptr = precv_frame->u.hdr.rx_data;
+	sint parsing_length;	/* Frame body length, without icv_len */
+	PNDIS_802_11_VARIABLE_IEs	pIE;
+	u8 FIXED_IE = 3, *dst;
+	u16 j;
+	struct tdls_txmgmt txmgmt;
+	int ret = _SUCCESS;
+
+	if (rtw_tdls_is_driver_setup(padapter) == _FALSE)
+		goto exit;
+
+	_rtw_memset(&txmgmt, 0x00, sizeof(struct tdls_txmgmt));
+	ptr += prx_pkt_attrib->hdrlen + prx_pkt_attrib->iv_len + LLC_HEADER_SIZE + ETH_TYPE_LEN + PAYLOAD_TYPE_LEN;
+	txmgmt.dialog_token = *(ptr + 2);
+	_rtw_memcpy(&txmgmt.peer, precv_frame->u.hdr.attrib.src, ETH_ALEN);
+	txmgmt.action_code = TDLS_DISCOVERY_RESPONSE;
+	parsing_length = ((union recv_frame *)precv_frame)->u.hdr.len
+			 - prx_pkt_attrib->hdrlen
+			 - prx_pkt_attrib->iv_len
+			 - prx_pkt_attrib->icv_len
+			 - LLC_HEADER_SIZE
+			 - ETH_TYPE_LEN
+			 - PAYLOAD_TYPE_LEN;
+
+	/* Parsing information element */
+	for (j = FIXED_IE; j < parsing_length;) {
+
+		pIE = (PNDIS_802_11_VARIABLE_IEs)(ptr + j);
+
+		switch (pIE->ElementID) {
+		case _LINK_ID_IE_:
+			psta_ap = rtw_get_stainfo(pstapriv, pIE->data);
+			if (psta_ap == NULL)
+				goto exit;
+			dst = pIE->data + 12;
+			if (MacAddr_isBcst(dst) == _FALSE && (_rtw_memcmp(adapter_mac_addr(padapter), dst, ETH_ALEN) == _FALSE))
+				goto exit;
+			break;
+		default:
+			break;
+		}
+
+		j += (pIE->Length + 2);
+
+	}
+
+	issue_tdls_dis_rsp(padapter, &txmgmt, prx_pkt_attrib->privacy);
+
+exit:
+	return ret;
+
+}
+
+int On_TDLS_Teardown(_adapter *padapter, union recv_frame *precv_frame, struct sta_info *ptdls_sta)
+{
+	u8 *ptr = precv_frame->u.hdr.rx_data;
+	struct rx_pkt_attrib	*prx_pkt_attrib = &precv_frame->u.hdr.attrib;
+	struct mlme_ext_priv	*pmlmeext = &(padapter->mlmeextpriv);
+	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
+	struct sta_priv	*pstapriv = &padapter->stapriv;
+	_irqL irqL;
+	u8 reason;
+
+	reason = *(ptr + prx_pkt_attrib->hdrlen + prx_pkt_attrib->iv_len + LLC_HEADER_SIZE + ETH_TYPE_LEN + PAYLOAD_TYPE_LEN + 2);
+	RTW_INFO("[TDLS] %s Reason code(%d)\n", __FUNCTION__, reason);
+
+	if (rtw_tdls_is_driver_setup(padapter)) {
+		rtw_tdls_teardown_pre_hdl(padapter, ptdls_sta);
+		rtw_tdls_cmd(padapter, ptdls_sta->cmn.mac_addr, TDLS_TEARDOWN_STA_LOCALLY_POST);
+	}
+
+	return _SUCCESS;
+
+}
+
+#if 0
+u8 TDLS_check_ch_state(uint state)
+{
+	if (state & TDLS_CH_SWITCH_ON_STATE &&
+	    state & TDLS_PEER_AT_OFF_STATE) {
+		if (state & TDLS_PEER_SLEEP_STATE)
+			return 2;	/* U-APSD + ch. switch */
+		else
+			return 1;	/* ch. switch */
+	} else
+		return 0;
+}
+#endif
+
+int On_TDLS_Peer_Traffic_Indication(_adapter *padapter, union recv_frame *precv_frame, struct sta_info *ptdls_sta)
+{
+	struct rx_pkt_attrib	*pattrib = &precv_frame->u.hdr.attrib;
+	u8 *ptr = precv_frame->u.hdr.rx_data;
+	struct tdls_txmgmt txmgmt;
+
+	ptr += pattrib->hdrlen + pattrib->iv_len + LLC_HEADER_SIZE + ETH_TYPE_LEN + PAYLOAD_TYPE_LEN;
+	_rtw_memset(&txmgmt, 0x00, sizeof(struct tdls_txmgmt));
+
+		txmgmt.dialog_token = *(ptr + 2);
+		issue_tdls_peer_traffic_rsp(padapter, ptdls_sta, &txmgmt);
+		/* issue_nulldata_to_TDLS_peer_STA(padapter, ptdls_sta->cmn.mac_addr, 0, 0, 0); */
+
+	return _SUCCESS;
+}
+
+/* We process buffered data for 1. U-APSD, 2. ch. switch, 3. U-APSD + ch. switch here */
+int On_TDLS_Peer_Traffic_Rsp(_adapter *padapter, union recv_frame *precv_frame, struct sta_info *ptdls_sta)
+{
+	struct tdls_info *ptdlsinfo = &padapter->tdlsinfo;
+	struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
+	struct rx_pkt_attrib	*pattrib = &precv_frame->u.hdr.attrib;
+	struct sta_priv *pstapriv = &padapter->stapriv;
+	u8 wmmps_ac = 0;
+	/* u8 state=TDLS_check_ch_state(ptdls_sta->tdls_sta_state); */
+	int i;
+
+	ptdls_sta->sta_stats.rx_data_pkts++;
+
+	ptdls_sta->tdls_sta_state &= ~(TDLS_WAIT_PTR_STATE);
+
+	/* Check 4-AC queue bit */
+	if (ptdls_sta->uapsd_vo || ptdls_sta->uapsd_vi || ptdls_sta->uapsd_be || ptdls_sta->uapsd_bk)
+		wmmps_ac = 1;
+
+	/* If it's a direct link and have buffered frame */
+	if (ptdls_sta->tdls_sta_state & TDLS_LINKED_STATE) {
+		if (wmmps_ac) {
+			_irqL irqL;
+			_list	*xmitframe_plist, *xmitframe_phead;
+			struct xmit_frame *pxmitframe = NULL;
+
+			_enter_critical_bh(&ptdls_sta->sleep_q.lock, &irqL);
+
+			xmitframe_phead = get_list_head(&ptdls_sta->sleep_q);
+			xmitframe_plist = get_next(xmitframe_phead);
+
+			/* transmit buffered frames */
+			while (rtw_end_of_queue_search(xmitframe_phead, xmitframe_plist) == _FALSE) {
+				pxmitframe = LIST_CONTAINOR(xmitframe_plist, struct xmit_frame, list);
+				xmitframe_plist = get_next(xmitframe_plist);
+				rtw_list_delete(&pxmitframe->list);
+
+				ptdls_sta->sleepq_len--;
+				ptdls_sta->sleepq_ac_len--;
+				if (ptdls_sta->sleepq_len > 0) {
+					pxmitframe->attrib.mdata = 1;
+					pxmitframe->attrib.eosp = 0;
+				} else {
+					pxmitframe->attrib.mdata = 0;
+					pxmitframe->attrib.eosp = 1;
+				}
+				pxmitframe->attrib.triggered = 1;
+
+				rtw_hal_xmitframe_enqueue(padapter, pxmitframe);
+			}
+
+			if (ptdls_sta->sleepq_len == 0)
+				RTW_INFO("no buffered packets for tdls to xmit\n");
+			else {
+				RTW_INFO("error!psta->sleepq_len=%d\n", ptdls_sta->sleepq_len);
+				ptdls_sta->sleepq_len = 0;
+			}
+
+			_exit_critical_bh(&ptdls_sta->sleep_q.lock, &irqL);
+
+		}
+
+	}
+
+	return _SUCCESS;
+}
+
+#ifdef CONFIG_TDLS_CH_SW
+sint On_TDLS_Ch_Switch_Req(_adapter *padapter, union recv_frame *precv_frame, struct sta_info *ptdls_sta)
+{
+	struct tdls_ch_switch *pchsw_info = &padapter->tdlsinfo.chsw_info;
+	struct sta_priv *pstapriv = &padapter->stapriv;
+	u8 *ptr = precv_frame->u.hdr.rx_data;
+	struct rx_pkt_attrib	*prx_pkt_attrib = &precv_frame->u.hdr.attrib;
+	sint parsing_length;
+	PNDIS_802_11_VARIABLE_IEs	pIE;
+	u8 FIXED_IE = 4;
+	u16 j;
+	struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
+	u8 zaddr[ETH_ALEN] = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00};
+	u16 switch_time = TDLS_CH_SWITCH_TIME * 1000, switch_timeout = TDLS_CH_SWITCH_TIMEOUT * 1000;
+	u8 take_care_iqk;
+
+	if (rtw_tdls_is_chsw_allowed(padapter) == _FALSE) {
+		RTW_INFO("[TDLS] Ignore %s since channel switch is not allowed\n", __func__);
+		return _FAIL;
+	}
+
+	ptdls_sta->ch_switch_time = switch_time;
+	ptdls_sta->ch_switch_timeout = switch_timeout;
+
+	ptr += prx_pkt_attrib->hdrlen + prx_pkt_attrib->iv_len + LLC_HEADER_SIZE + ETH_TYPE_LEN + PAYLOAD_TYPE_LEN;
+	parsing_length = ((union recv_frame *)precv_frame)->u.hdr.len
+			 - prx_pkt_attrib->hdrlen
+			 - prx_pkt_attrib->iv_len
+			 - prx_pkt_attrib->icv_len
+			 - LLC_HEADER_SIZE
+			 - ETH_TYPE_LEN
+			 - PAYLOAD_TYPE_LEN;
+
+	pchsw_info->off_ch_num = *(ptr + 2);
+
+	if ((*(ptr + 2) == 2) && (hal_is_band_support(padapter, BAND_ON_5G)))
+		pchsw_info->off_ch_num = 44;
+
+	if (pchsw_info->off_ch_num != pmlmeext->cur_channel)
+		pchsw_info->delay_switch_back = _FALSE;
+
+	/* Parsing information element */
+	for (j = FIXED_IE; j < parsing_length;) {
+		pIE = (PNDIS_802_11_VARIABLE_IEs)(ptr + j);
+
+		switch (pIE->ElementID) {
+		case EID_SecondaryChnlOffset:
+			switch (*(pIE->data)) {
+			case EXTCHNL_OFFSET_UPPER:
+				pchsw_info->ch_offset = HAL_PRIME_CHNL_OFFSET_LOWER;
+				break;
+
+			case EXTCHNL_OFFSET_LOWER:
+				pchsw_info->ch_offset = HAL_PRIME_CHNL_OFFSET_UPPER;
+				break;
+
+			default:
+				pchsw_info->ch_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
+				break;
+			}
+			break;
+		case _LINK_ID_IE_:
+			break;
+		case _CH_SWITCH_TIMING_:
+			ptdls_sta->ch_switch_time = (RTW_GET_LE16(pIE->data) >= TDLS_CH_SWITCH_TIME * 1000) ?
+				RTW_GET_LE16(pIE->data) : TDLS_CH_SWITCH_TIME * 1000;
+			ptdls_sta->ch_switch_timeout = (RTW_GET_LE16(pIE->data + 2) >= TDLS_CH_SWITCH_TIMEOUT * 1000) ?
+				RTW_GET_LE16(pIE->data + 2) : TDLS_CH_SWITCH_TIMEOUT * 1000;
+			RTW_INFO("[TDLS] %s ch_switch_time:%d, ch_switch_timeout:%d\n"
+				, __FUNCTION__, RTW_GET_LE16(pIE->data), RTW_GET_LE16(pIE->data + 2));
+		default:
+			break;
+		}
+
+		j += (pIE->Length + 2);
+	}
+
+	rtw_hal_get_hwreg(padapter, HW_VAR_CH_SW_NEED_TO_TAKE_CARE_IQK_INFO, &take_care_iqk);
+	if (take_care_iqk == _TRUE) {
+		u8 central_chnl;
+		u8 bw_mode;
+
+		bw_mode = (pchsw_info->ch_offset) ? CHANNEL_WIDTH_40 : CHANNEL_WIDTH_20;
+		central_chnl = rtw_get_center_ch(pchsw_info->off_ch_num, bw_mode, pchsw_info->ch_offset);
+		if (rtw_hal_ch_sw_iqk_info_search(padapter, central_chnl, bw_mode) < 0) {
+			if (!(pchsw_info->ch_sw_state & TDLS_CH_SWITCH_PREPARE_STATE))
+				rtw_tdls_cmd(padapter, ptdls_sta->cmn.mac_addr, TDLS_CH_SW_PREPARE);
+
+			return _FAIL;
+		}
+	}
+
+	/* cancel ch sw monitor timer for responder */
+	if (!(pchsw_info->ch_sw_state & TDLS_CH_SW_INITIATOR_STATE))
+		_cancel_timer_ex(&ptdls_sta->ch_sw_monitor_timer);
+
+	if (_rtw_memcmp(pchsw_info->addr, zaddr, ETH_ALEN) == _TRUE)
+		_rtw_memcpy(pchsw_info->addr, ptdls_sta->cmn.mac_addr, ETH_ALEN);
+
+	if (ATOMIC_READ(&pchsw_info->chsw_on) == _FALSE)
+		rtw_tdls_cmd(padapter, ptdls_sta->cmn.mac_addr, TDLS_CH_SW_START);
+
+	rtw_tdls_cmd(padapter, ptdls_sta->cmn.mac_addr, TDLS_CH_SW_RESP);
+
+	return _SUCCESS;
+}
+
+sint On_TDLS_Ch_Switch_Rsp(_adapter *padapter, union recv_frame *precv_frame, struct sta_info *ptdls_sta)
+{
+	struct tdls_ch_switch *pchsw_info = &padapter->tdlsinfo.chsw_info;
+	struct sta_priv *pstapriv = &padapter->stapriv;
+	u8 *ptr = precv_frame->u.hdr.rx_data;
+	struct rx_pkt_attrib	*prx_pkt_attrib = &precv_frame->u.hdr.attrib;
+	sint parsing_length;
+	PNDIS_802_11_VARIABLE_IEs	pIE;
+	u8 FIXED_IE = 4;
+	u16 status_code, j, switch_time, switch_timeout;
+	struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
+	int ret = _SUCCESS;
+
+	if (rtw_tdls_is_chsw_allowed(padapter) == _FALSE) {
+		RTW_INFO("[TDLS] Ignore %s since channel switch is not allowed\n", __func__);
+		return _SUCCESS;
+	}
+
+	/* If we receive Unsolicited TDLS Channel Switch Response when channel switch is running, */
+	/* we will go back to base channel and terminate this channel switch procedure */
+	if (ATOMIC_READ(&pchsw_info->chsw_on) == _TRUE) {
+		if (pmlmeext->cur_channel != rtw_get_oper_ch(padapter)) {
+			RTW_INFO("[TDLS] Rx unsolicited channel switch response\n");
+			rtw_tdls_cmd(padapter, ptdls_sta->cmn.mac_addr, TDLS_CH_SW_TO_BASE_CHNL);
+			goto exit;
+		}
+	}
+
+	ptr += prx_pkt_attrib->hdrlen + prx_pkt_attrib->iv_len + LLC_HEADER_SIZE + ETH_TYPE_LEN + PAYLOAD_TYPE_LEN;
+	parsing_length = ((union recv_frame *)precv_frame)->u.hdr.len
+			 - prx_pkt_attrib->hdrlen
+			 - prx_pkt_attrib->iv_len
+			 - prx_pkt_attrib->icv_len
+			 - LLC_HEADER_SIZE
+			 - ETH_TYPE_LEN
+			 - PAYLOAD_TYPE_LEN;
+
+	_rtw_memcpy(&status_code, ptr + 2, 2);
+
+	if (status_code != 0) {
+		RTW_INFO("[TDLS] %s status_code:%d\n", __func__, status_code);
+		pchsw_info->ch_sw_state &= ~(TDLS_CH_SW_INITIATOR_STATE);
+		rtw_tdls_cmd(padapter, ptdls_sta->cmn.mac_addr, TDLS_CH_SW_END);
+		ret = _FAIL;
+		goto exit;
+	}
+
+	/* Parsing information element */
+	for (j = FIXED_IE; j < parsing_length;) {
+		pIE = (PNDIS_802_11_VARIABLE_IEs)(ptr + j);
+
+		switch (pIE->ElementID) {
+		case _LINK_ID_IE_:
+			break;
+		case _CH_SWITCH_TIMING_:
+			_rtw_memcpy(&switch_time, pIE->data, 2);
+			if (switch_time > ptdls_sta->ch_switch_time)
+				_rtw_memcpy(&ptdls_sta->ch_switch_time, &switch_time, 2);
+
+			_rtw_memcpy(&switch_timeout, pIE->data + 2, 2);
+			if (switch_timeout > ptdls_sta->ch_switch_timeout)
+				_rtw_memcpy(&ptdls_sta->ch_switch_timeout, &switch_timeout, 2);
+			break;
+		default:
+			break;
+		}
+
+		j += (pIE->Length + 2);
+	}
+
+	if ((pmlmeext->cur_channel == rtw_get_oper_ch(padapter)) &&
+	    (pchsw_info->ch_sw_state & TDLS_WAIT_CH_RSP_STATE)) {
+		if (ATOMIC_READ(&pchsw_info->chsw_on) == _TRUE)
+			rtw_tdls_cmd(padapter, ptdls_sta->cmn.mac_addr, TDLS_CH_SW_TO_OFF_CHNL);
+	}
+
+exit:
+	return ret;
+}
+#endif /* CONFIG_TDLS_CH_SW */
+
+#ifdef CONFIG_WFD
+void wfd_ie_tdls(_adapter *padapter, u8 *pframe, u32 *pktlen)
+{
+	struct mlme_priv		*pmlmepriv = &padapter->mlmepriv;
+	struct wifi_display_info	*pwfd_info = padapter->tdlsinfo.wfd_info;
+	u8 wfdie[MAX_WFD_IE_LEN] = { 0x00 };
+	u32 wfdielen = 0;
+	u16 v16 = 0;
+
+	if (!hal_chk_wl_func(padapter, WL_FUNC_MIRACAST))
+		return;
+
+	/* WFD OUI */
+	wfdielen = 0;
+	wfdie[wfdielen++] = 0x50;
+	wfdie[wfdielen++] = 0x6F;
+	wfdie[wfdielen++] = 0x9A;
+	wfdie[wfdielen++] = 0x0A;	/* WFA WFD v1.0 */
+
+	/*
+	 *	Commented by Albert 20110825
+	 *	According to the WFD Specification, the negotiation request frame should contain 3 WFD attributes
+	 *	1. WFD Device Information
+	 *	2. Associated BSSID ( Optional )
+	 *	3. Local IP Adress ( Optional )
+	 */
+
+	/* WFD Device Information ATTR */
+	/* Type: */
+	wfdie[wfdielen++] = WFD_ATTR_DEVICE_INFO;
+
+	/* Length: */
+	/* Note: In the WFD specification, the size of length field is 2. */
+	RTW_PUT_BE16(wfdie + wfdielen, 0x0006);
+	wfdielen += 2;
+
+	/* Value1: */
+	/* WFD device information */
+	/* available for WFD session + Preferred TDLS + WSD ( WFD Service Discovery ) */
+	v16 = pwfd_info->wfd_device_type | WFD_DEVINFO_SESSION_AVAIL
+		| WFD_DEVINFO_PC_TDLS | WFD_DEVINFO_WSD;
+	RTW_PUT_BE16(wfdie + wfdielen, v16);
+	wfdielen += 2;
+
+	/* Value2: */
+	/* Session Management Control Port */
+	/* Default TCP port for RTSP messages is 554 */
+	RTW_PUT_BE16(wfdie + wfdielen, pwfd_info->tdls_rtsp_ctrlport);
+	wfdielen += 2;
+
+	/* Value3: */
+	/* WFD Device Maximum Throughput */
+	/* 300Mbps is the maximum throughput */
+	RTW_PUT_BE16(wfdie + wfdielen, 300);
+	wfdielen += 2;
+
+	/* Associated BSSID ATTR */
+	/* Type: */
+	wfdie[wfdielen++] = WFD_ATTR_ASSOC_BSSID;
+
+	/* Length: */
+	/* Note: In the WFD specification, the size of length field is 2. */
+	RTW_PUT_BE16(wfdie + wfdielen, 0x0006);
+	wfdielen += 2;
+
+	/* Value: */
+	/* Associated BSSID */
+	if (check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE)
+		_rtw_memcpy(wfdie + wfdielen, &pmlmepriv->assoc_bssid[0], ETH_ALEN);
+	else
+		_rtw_memset(wfdie + wfdielen, 0x00, ETH_ALEN);
+
+	/* Local IP Address ATTR */
+	wfdie[wfdielen++] = WFD_ATTR_LOCAL_IP_ADDR;
+
+	/* Length: */
+	/* Note: In the WFD specification, the size of length field is 2. */
+	RTW_PUT_BE16(wfdie + wfdielen, 0x0005);
+	wfdielen += 2;
+
+	/* Version: */
+	/* 0x01: Version1;IPv4 */
+	wfdie[wfdielen++] = 0x01;
+
+	/* IPv4 Address */
+	_rtw_memcpy(wfdie + wfdielen, pwfd_info->ip_address, 4);
+	wfdielen += 4;
+
+	pframe = rtw_set_ie(pframe, _VENDOR_SPECIFIC_IE_, wfdielen, (unsigned char *) wfdie, pktlen);
+
+}
+#endif /* CONFIG_WFD */
+
+void rtw_build_tdls_setup_req_ies(_adapter *padapter, struct xmit_frame *pxmitframe, u8 *pframe, struct tdls_txmgmt *ptxmgmt, struct sta_info *ptdls_sta)
+{
+	struct rf_ctl_t *rfctl = adapter_to_rfctl(padapter);
+	struct registry_priv	*pregistrypriv = &padapter->registrypriv;
+	struct mlme_ext_priv	*pmlmeext = &(padapter->mlmeextpriv);
+	struct pkt_attrib	*pattrib = &pxmitframe->attrib;
+	int i = 0 ;
+	u32 time;
+	u8 *pframe_head;
+
+	/* SNonce */
+	if (pattrib->encrypt) {
+		for (i = 0; i < 8; i++) {
+			time = rtw_get_current_time();
+			_rtw_memcpy(&ptdls_sta->SNonce[4 * i], (u8 *)&time, 4);
+		}
+	}
+
+	pframe_head = pframe;	/* For rtw_tdls_set_ht_cap() */
+
+	pframe = rtw_tdls_set_payload_type(pframe, pattrib);
+	pframe = rtw_tdls_set_category(pframe, pattrib, RTW_WLAN_CATEGORY_TDLS);
+	pframe = rtw_tdls_set_action(pframe, pattrib, ptxmgmt);
+	pframe = rtw_tdls_set_dialog(pframe, pattrib, ptxmgmt);
+
+	pframe = rtw_tdls_set_capability(padapter, pframe, pattrib);
+	pframe = rtw_tdls_set_supported_rate(padapter, pframe, pattrib);
+	pframe = rtw_tdls_set_sup_ch(padapter, pframe, pattrib);
+	pframe = rtw_tdls_set_sup_reg_class(pframe, pattrib);
+
+	if (pattrib->encrypt)
+		pframe = rtw_tdls_set_rsnie(ptxmgmt, pframe, pattrib,  _TRUE, ptdls_sta);
+
+	pframe = rtw_tdls_set_ext_cap(pframe, pattrib);
+
+	if (pattrib->encrypt) {
+		pframe = rtw_tdls_set_ftie(ptxmgmt
+					   , pframe
+					   , pattrib
+					   , NULL
+					   , ptdls_sta->SNonce);
+
+		pframe = rtw_tdls_set_timeout_interval(ptxmgmt, pframe, pattrib, _TRUE, ptdls_sta);
+	}
+
+#ifdef CONFIG_80211N_HT
+	/* Sup_reg_classes(optional) */
+	if (pregistrypriv->ht_enable == _TRUE)
+		pframe = rtw_tdls_set_ht_cap(padapter, pframe_head, pattrib);
+#endif
+
+	pframe = rtw_tdls_set_bss_coexist(padapter, pframe, pattrib);
+
+	pframe = rtw_tdls_set_linkid(padapter, pframe, pattrib, _TRUE);
+
+	if ((pregistrypriv->wmm_enable == _TRUE) || (padapter->mlmepriv.htpriv.ht_option == _TRUE))
+		pframe = rtw_tdls_set_qos_cap(pframe, pattrib);
+
+#ifdef CONFIG_80211AC_VHT
+	if ((padapter->mlmepriv.htpriv.ht_option == _TRUE) && (pmlmeext->cur_channel > 14)
+	    && REGSTY_IS_11AC_ENABLE(pregistrypriv)
+	    && is_supported_vht(pregistrypriv->wireless_mode)
+	    && (!rfctl->country_ent || COUNTRY_CHPLAN_EN_11AC(rfctl->country_ent))
+	   ) {
+		pframe = rtw_tdls_set_aid(padapter, pframe, pattrib);
+		pframe = rtw_tdls_set_vht_cap(padapter, pframe, pattrib);
+	}
+#endif
+
+#ifdef CONFIG_WFD
+	if (padapter->wdinfo.wfd_tdls_enable == 1)
+		wfd_ie_tdls(padapter, pframe, &(pattrib->pktlen));
+#endif
+
+}
+
+void rtw_build_tdls_setup_rsp_ies(_adapter *padapter, struct xmit_frame *pxmitframe, u8 *pframe, struct tdls_txmgmt *ptxmgmt, struct sta_info *ptdls_sta)
+{
+	struct rf_ctl_t *rfctl = adapter_to_rfctl(padapter);
+	struct registry_priv	*pregistrypriv = &padapter->registrypriv;
+	struct mlme_ext_priv	*pmlmeext = &(padapter->mlmeextpriv);
+	struct pkt_attrib	*pattrib = &pxmitframe->attrib;
+	u8 k; /* for random ANonce */
+	u8  *pftie = NULL, *ptimeout_ie = NULL, *plinkid_ie = NULL, *prsnie = NULL, *pftie_mic = NULL;
+	u32 time;
+	u8 *pframe_head;
+
+	if (pattrib->encrypt) {
+		for (k = 0; k < 8; k++) {
+			time = rtw_get_current_time();
+			_rtw_memcpy(&ptdls_sta->ANonce[4 * k], (u8 *)&time, 4);
+		}
+	}
+
+	pframe_head = pframe;
+
+	pframe = rtw_tdls_set_payload_type(pframe, pattrib);
+	pframe = rtw_tdls_set_category(pframe, pattrib, RTW_WLAN_CATEGORY_TDLS);
+	pframe = rtw_tdls_set_action(pframe, pattrib, ptxmgmt);
+	pframe = rtw_tdls_set_status_code(pframe, pattrib, ptxmgmt);
+
+	if (ptxmgmt->status_code != 0) {
+		RTW_INFO("[%s] status_code:%04x\n", __FUNCTION__, ptxmgmt->status_code);
+		return;
+	}
+
+	pframe = rtw_tdls_set_dialog(pframe, pattrib, ptxmgmt);
+	pframe = rtw_tdls_set_capability(padapter, pframe, pattrib);
+	pframe = rtw_tdls_set_supported_rate(padapter, pframe, pattrib);
+	pframe = rtw_tdls_set_sup_ch(padapter, pframe, pattrib);
+	pframe = rtw_tdls_set_sup_reg_class(pframe, pattrib);
+
+	if (pattrib->encrypt) {
+		prsnie = pframe;
+		pframe = rtw_tdls_set_rsnie(ptxmgmt, pframe, pattrib,  _FALSE, ptdls_sta);
+	}
+
+	pframe = rtw_tdls_set_ext_cap(pframe, pattrib);
+
+	if (pattrib->encrypt) {
+		if (rtw_tdls_is_driver_setup(padapter) == _TRUE)
+			wpa_tdls_generate_tpk(padapter, ptdls_sta);
+
+		pftie = pframe;
+		pftie_mic = pframe + 4;
+		pframe = rtw_tdls_set_ftie(ptxmgmt
+					   , pframe
+					   , pattrib
+					   , ptdls_sta->ANonce
+					   , ptdls_sta->SNonce);
+
+		ptimeout_ie = pframe;
+		pframe = rtw_tdls_set_timeout_interval(ptxmgmt, pframe, pattrib, _FALSE, ptdls_sta);
+	}
+
+#ifdef CONFIG_80211N_HT
+	/* Sup_reg_classes(optional) */
+	if (pregistrypriv->ht_enable == _TRUE)
+		pframe = rtw_tdls_set_ht_cap(padapter, pframe_head, pattrib);
+#endif
+
+	pframe = rtw_tdls_set_bss_coexist(padapter, pframe, pattrib);
+
+	plinkid_ie = pframe;
+	pframe = rtw_tdls_set_linkid(padapter, pframe, pattrib, _FALSE);
+
+	/* Fill FTIE mic */
+	if (pattrib->encrypt && rtw_tdls_is_driver_setup(padapter) == _TRUE)
+		wpa_tdls_ftie_mic(ptdls_sta->tpk.kck, 2, plinkid_ie, prsnie, ptimeout_ie, pftie, pftie_mic);
+
+	if ((pregistrypriv->wmm_enable == _TRUE) || (padapter->mlmepriv.htpriv.ht_option == _TRUE))
+		pframe = rtw_tdls_set_qos_cap(pframe, pattrib);
+
+#ifdef CONFIG_80211AC_VHT
+	if ((padapter->mlmepriv.htpriv.ht_option == _TRUE) && (pmlmeext->cur_channel > 14)
+	    && REGSTY_IS_11AC_ENABLE(pregistrypriv)
+	    && is_supported_vht(pregistrypriv->wireless_mode)
+	    && (!rfctl->country_ent || COUNTRY_CHPLAN_EN_11AC(rfctl->country_ent))
+	   ) {
+		pframe = rtw_tdls_set_aid(padapter, pframe, pattrib);
+		pframe = rtw_tdls_set_vht_cap(padapter, pframe, pattrib);
+		pframe = rtw_tdls_set_vht_op_mode_notify(padapter, pframe, pattrib, pmlmeext->cur_bwmode);
+	}
+#endif
+
+#ifdef CONFIG_WFD
+	if (padapter->wdinfo.wfd_tdls_enable)
+		wfd_ie_tdls(padapter, pframe, &(pattrib->pktlen));
+#endif
+
+}
+
+void rtw_build_tdls_setup_cfm_ies(_adapter *padapter, struct xmit_frame *pxmitframe, u8 *pframe, struct tdls_txmgmt *ptxmgmt, struct sta_info *ptdls_sta)
+{
+	struct rf_ctl_t *rfctl = adapter_to_rfctl(padapter);
+	struct registry_priv	*pregistrypriv = &padapter->registrypriv;
+	struct mlme_ext_priv	*pmlmeext = &(padapter->mlmeextpriv);
+	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
+	struct pkt_attrib	*pattrib = &pxmitframe->attrib;
+
+	unsigned int ie_len;
+	unsigned char *p;
+	u8 wmm_param_ele[24] = {0};
+	u8  *pftie = NULL, *ptimeout_ie = NULL, *plinkid_ie = NULL, *prsnie = NULL, *pftie_mic = NULL;
+
+	pframe = rtw_tdls_set_payload_type(pframe, pattrib);
+	pframe = rtw_tdls_set_category(pframe, pattrib, RTW_WLAN_CATEGORY_TDLS);
+	pframe = rtw_tdls_set_action(pframe, pattrib, ptxmgmt);
+	pframe = rtw_tdls_set_status_code(pframe, pattrib, ptxmgmt);
+	pframe = rtw_tdls_set_dialog(pframe, pattrib, ptxmgmt);
+
+	if (ptxmgmt->status_code != 0)
+		return;
+
+	if (pattrib->encrypt) {
+		prsnie = pframe;
+		pframe = rtw_tdls_set_rsnie(ptxmgmt, pframe, pattrib, _TRUE, ptdls_sta);
+	}
+
+	if (pattrib->encrypt) {
+		pftie = pframe;
+		pftie_mic = pframe + 4;
+		pframe = rtw_tdls_set_ftie(ptxmgmt
+					   , pframe
+					   , pattrib
+					   , ptdls_sta->ANonce
+					   , ptdls_sta->SNonce);
+
+		ptimeout_ie = pframe;
+		pframe = rtw_tdls_set_timeout_interval(ptxmgmt, pframe, pattrib, _TRUE, ptdls_sta);
+
+		if (rtw_tdls_is_driver_setup(padapter) == _TRUE) {
+			/* Start TPK timer */
+			ptdls_sta->TPK_count = 0;
+			_set_timer(&ptdls_sta->TPK_timer, ONE_SEC);
+		}
+	}
+
+	/* HT operation; todo */
+
+	plinkid_ie = pframe;
+	pframe = rtw_tdls_set_linkid(padapter, pframe, pattrib, _TRUE);
+
+	if (pattrib->encrypt && (rtw_tdls_is_driver_setup(padapter) == _TRUE))
+		wpa_tdls_ftie_mic(ptdls_sta->tpk.kck, 3, plinkid_ie, prsnie, ptimeout_ie, pftie, pftie_mic);
+
+	if (ptdls_sta->qos_option == _TRUE)
+		pframe = rtw_tdls_set_wmm_params(padapter, pframe, pattrib);
+
+#ifdef CONFIG_80211AC_VHT
+	if ((padapter->mlmepriv.htpriv.ht_option == _TRUE)
+	    && (ptdls_sta->vhtpriv.vht_option == _TRUE) && (pmlmeext->cur_channel > 14)
+	    && REGSTY_IS_11AC_ENABLE(pregistrypriv)
+	    && is_supported_vht(pregistrypriv->wireless_mode)
+	    && (!rfctl->country_ent || COUNTRY_CHPLAN_EN_11AC(rfctl->country_ent))
+	   ) {
+		pframe = rtw_tdls_set_vht_operation(padapter, pframe, pattrib, pmlmeext->cur_channel);
+		pframe = rtw_tdls_set_vht_op_mode_notify(padapter, pframe, pattrib, pmlmeext->cur_bwmode);
+	}
+#endif
+}
+
+void rtw_build_tdls_teardown_ies(_adapter *padapter, struct xmit_frame *pxmitframe, u8 *pframe, struct tdls_txmgmt *ptxmgmt, struct sta_info *ptdls_sta)
+{
+	struct pkt_attrib	*pattrib = &pxmitframe->attrib;
+	u8  *pftie = NULL, *pftie_mic = NULL, *plinkid_ie = NULL;
+
+	pframe = rtw_tdls_set_payload_type(pframe, pattrib);
+	pframe = rtw_tdls_set_category(pframe, pattrib, RTW_WLAN_CATEGORY_TDLS);
+	pframe = rtw_tdls_set_action(pframe, pattrib, ptxmgmt);
+	pframe = rtw_tdls_set_status_code(pframe, pattrib, ptxmgmt);
+
+	if (pattrib->encrypt) {
+		pftie = pframe;
+		pftie_mic = pframe + 4;
+		pframe = rtw_tdls_set_ftie(ptxmgmt
+					   , pframe
+					   , pattrib
+					   , ptdls_sta->ANonce
+					   , ptdls_sta->SNonce);
+	}
+
+	plinkid_ie = pframe;
+	if (ptdls_sta->tdls_sta_state & TDLS_INITIATOR_STATE)
+		pframe = rtw_tdls_set_linkid(padapter, pframe, pattrib, _FALSE);
+	else if (ptdls_sta->tdls_sta_state & TDLS_RESPONDER_STATE)
+		pframe = rtw_tdls_set_linkid(padapter, pframe, pattrib, _TRUE);
+
+	if (pattrib->encrypt && (rtw_tdls_is_driver_setup(padapter) == _TRUE))
+		wpa_tdls_teardown_ftie_mic(ptdls_sta->tpk.kck, plinkid_ie, ptxmgmt->status_code, 1, 4, pftie, pftie_mic);
+}
+
+void rtw_build_tdls_dis_req_ies(_adapter *padapter, struct xmit_frame *pxmitframe, u8 *pframe, struct tdls_txmgmt *ptxmgmt)
+{
+	struct pkt_attrib *pattrib = &pxmitframe->attrib;
+
+	pframe = rtw_tdls_set_payload_type(pframe, pattrib);
+	pframe = rtw_tdls_set_category(pframe, pattrib, RTW_WLAN_CATEGORY_TDLS);
+	pframe = rtw_tdls_set_action(pframe, pattrib, ptxmgmt);
+	pframe = rtw_tdls_set_dialog(pframe, pattrib, ptxmgmt);
+	pframe = rtw_tdls_set_linkid(padapter, pframe, pattrib, _TRUE);
+
+}
+
+void rtw_build_tdls_dis_rsp_ies(_adapter *padapter, struct xmit_frame *pxmitframe, u8 *pframe, struct tdls_txmgmt *ptxmgmt, u8 privacy)
+{
+	struct registry_priv	*pregistrypriv = &padapter->registrypriv;
+	struct mlme_ext_priv	*pmlmeext = &padapter->mlmeextpriv;
+	struct pkt_attrib	*pattrib = &pxmitframe->attrib;
+	u8 *pframe_head, pktlen_index;
+
+	pktlen_index = pattrib->pktlen;
+	pframe_head = pframe;
+
+	pframe = rtw_tdls_set_category(pframe, pattrib, RTW_WLAN_CATEGORY_PUBLIC);
+	pframe = rtw_tdls_set_action(pframe, pattrib, ptxmgmt);
+	pframe = rtw_tdls_set_dialog(pframe, pattrib, ptxmgmt);
+	pframe = rtw_tdls_set_capability(padapter, pframe, pattrib);
+
+	pframe = rtw_tdls_set_supported_rate(padapter, pframe, pattrib);
+
+	pframe = rtw_tdls_set_sup_ch(padapter, pframe, pattrib);
+
+	if (privacy)
+		pframe = rtw_tdls_set_rsnie(ptxmgmt, pframe, pattrib, _TRUE, NULL);
+
+	pframe = rtw_tdls_set_ext_cap(pframe, pattrib);
+
+	if (privacy) {
+		pframe = rtw_tdls_set_ftie(ptxmgmt, pframe, pattrib, NULL, NULL);
+		pframe = rtw_tdls_set_timeout_interval(ptxmgmt, pframe, pattrib,  _TRUE, NULL);
+	}
+
+#ifdef CONFIG_80211N_HT
+	if (pregistrypriv->ht_enable == _TRUE)
+		pframe = rtw_tdls_set_ht_cap(padapter, pframe_head - pktlen_index, pattrib);
+#endif
+
+	pframe = rtw_tdls_set_bss_coexist(padapter, pframe, pattrib);
+	pframe = rtw_tdls_set_linkid(padapter, pframe, pattrib, _FALSE);
+
+}
+
+
+void rtw_build_tdls_peer_traffic_indication_ies(_adapter *padapter, struct xmit_frame *pxmitframe, u8 *pframe, struct tdls_txmgmt *ptxmgmt, struct sta_info *ptdls_sta)
+{
+
+	struct pkt_attrib	*pattrib = &pxmitframe->attrib;
+	u8 AC_queue = 0;
+
+	pframe = rtw_tdls_set_payload_type(pframe, pattrib);
+	pframe = rtw_tdls_set_category(pframe, pattrib, RTW_WLAN_CATEGORY_TDLS);
+	pframe = rtw_tdls_set_action(pframe, pattrib, ptxmgmt);
+	pframe = rtw_tdls_set_dialog(pframe, pattrib, ptxmgmt);
+
+	if (ptdls_sta->tdls_sta_state & TDLS_INITIATOR_STATE)
+		pframe = rtw_tdls_set_linkid(padapter, pframe, pattrib, _FALSE);
+	else if (ptdls_sta->tdls_sta_state & TDLS_RESPONDER_STATE)
+		pframe = rtw_tdls_set_linkid(padapter, pframe, pattrib, _TRUE);
+
+	/* PTI control */
+	/* PU buffer status */
+	if (ptdls_sta->uapsd_bk & BIT(1))
+		AC_queue = BIT(0);
+	if (ptdls_sta->uapsd_be & BIT(1))
+		AC_queue = BIT(1);
+	if (ptdls_sta->uapsd_vi & BIT(1))
+		AC_queue = BIT(2);
+	if (ptdls_sta->uapsd_vo & BIT(1))
+		AC_queue = BIT(3);
+	pframe = rtw_set_ie(pframe, _PTI_BUFFER_STATUS_, 1, &AC_queue, &(pattrib->pktlen));
+
+}
+
+void rtw_build_tdls_peer_traffic_rsp_ies(_adapter *padapter, struct xmit_frame *pxmitframe, u8 *pframe, struct tdls_txmgmt *ptxmgmt, struct sta_info *ptdls_sta)
+{
+
+	struct pkt_attrib	*pattrib = &pxmitframe->attrib;
+
+	pframe = rtw_tdls_set_payload_type(pframe, pattrib);
+	pframe = rtw_tdls_set_category(pframe, pattrib, RTW_WLAN_CATEGORY_TDLS);
+	pframe = rtw_tdls_set_action(pframe, pattrib, ptxmgmt);
+	pframe = rtw_tdls_set_dialog(pframe, pattrib, ptxmgmt);
+
+	if (ptdls_sta->tdls_sta_state & TDLS_INITIATOR_STATE)
+		pframe = rtw_tdls_set_linkid(padapter, pframe, pattrib, _FALSE);
+	else if (ptdls_sta->tdls_sta_state & TDLS_RESPONDER_STATE)
+		pframe = rtw_tdls_set_linkid(padapter, pframe, pattrib, _TRUE);
+}
+
+#ifdef CONFIG_TDLS_CH_SW
+void rtw_build_tdls_ch_switch_req_ies(_adapter *padapter, struct xmit_frame *pxmitframe, u8 *pframe, struct tdls_txmgmt *ptxmgmt, struct sta_info *ptdls_sta)
+{
+	struct tdls_info *ptdlsinfo = &padapter->tdlsinfo;
+	struct pkt_attrib	*pattrib = &pxmitframe->attrib;
+	struct sta_priv	*pstapriv = &padapter->stapriv;
+	u16 switch_time = TDLS_CH_SWITCH_TIME * 1000, switch_timeout = TDLS_CH_SWITCH_TIMEOUT * 1000;
+
+	ptdls_sta->ch_switch_time = switch_time;
+	ptdls_sta->ch_switch_timeout = switch_timeout;
+
+	pframe = rtw_tdls_set_payload_type(pframe, pattrib);
+	pframe = rtw_tdls_set_category(pframe, pattrib, RTW_WLAN_CATEGORY_TDLS);
+	pframe = rtw_tdls_set_action(pframe, pattrib, ptxmgmt);
+	pframe = rtw_tdls_set_target_ch(padapter, pframe, pattrib);
+	pframe = rtw_tdls_set_reg_class(pframe, pattrib, ptdls_sta);
+
+	if (ptdlsinfo->chsw_info.ch_offset != HAL_PRIME_CHNL_OFFSET_DONT_CARE) {
+		switch (ptdlsinfo->chsw_info.ch_offset) {
+		case HAL_PRIME_CHNL_OFFSET_LOWER:
+			pframe = rtw_tdls_set_second_channel_offset(pframe, pattrib, SCA);
+			break;
+		case HAL_PRIME_CHNL_OFFSET_UPPER:
+			pframe = rtw_tdls_set_second_channel_offset(pframe, pattrib, SCB);
+			break;
+		}
+	}
+
+	if (ptdls_sta->tdls_sta_state & TDLS_INITIATOR_STATE)
+		pframe = rtw_tdls_set_linkid(padapter, pframe, pattrib, _FALSE);
+	else if (ptdls_sta->tdls_sta_state & TDLS_RESPONDER_STATE)
+		pframe = rtw_tdls_set_linkid(padapter, pframe, pattrib, _TRUE);
+
+	pframe = rtw_tdls_set_ch_sw(pframe, pattrib, ptdls_sta);
+
+}
+
+void rtw_build_tdls_ch_switch_rsp_ies(_adapter *padapter, struct xmit_frame *pxmitframe, u8 *pframe, struct tdls_txmgmt *ptxmgmt, struct sta_info *ptdls_sta)
+{
+
+	struct pkt_attrib	*pattrib = &pxmitframe->attrib;
+	struct sta_priv	*pstapriv = &padapter->stapriv;
+
+	pframe = rtw_tdls_set_payload_type(pframe, pattrib);
+	pframe = rtw_tdls_set_category(pframe, pattrib, RTW_WLAN_CATEGORY_TDLS);
+	pframe = rtw_tdls_set_action(pframe, pattrib, ptxmgmt);
+	pframe = rtw_tdls_set_status_code(pframe, pattrib, ptxmgmt);
+
+	if (ptdls_sta->tdls_sta_state & TDLS_INITIATOR_STATE)
+		pframe = rtw_tdls_set_linkid(padapter, pframe, pattrib, _FALSE);
+	else if (ptdls_sta->tdls_sta_state & TDLS_RESPONDER_STATE)
+		pframe = rtw_tdls_set_linkid(padapter, pframe, pattrib, _TRUE);
+
+	pframe = rtw_tdls_set_ch_sw(pframe, pattrib, ptdls_sta);
+}
+#endif
+
+#ifdef CONFIG_WFD
+void rtw_build_tunneled_probe_req_ies(_adapter *padapter, struct xmit_frame *pxmitframe, u8 *pframe)
+{
+	u8 i;
+	_adapter *iface = NULL;
+	struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
+	struct pkt_attrib *pattrib = &pxmitframe->attrib;
+	struct wifidirect_info *pwdinfo;
+
+	u8 category = RTW_WLAN_CATEGORY_P2P;
+	u8 WFA_OUI[3] = { 0x50, 0x6f, 0x9a};
+	u8 probe_req = 4;
+	u8 wfdielen = 0;
+
+	pframe = rtw_tdls_set_payload_type(pframe, pattrib);
+	pframe = rtw_set_fixed_ie(pframe, 1, &(category), &(pattrib->pktlen));
+	pframe = rtw_set_fixed_ie(pframe, 3, WFA_OUI, &(pattrib->pktlen));
+	pframe = rtw_set_fixed_ie(pframe, 1, &(probe_req), &(pattrib->pktlen));
+
+	for (i = 0; i < dvobj->iface_nums; i++) {
+		iface = dvobj->padapters[i];
+		if ((iface) && rtw_is_adapter_up(iface)) {
+			pwdinfo = &iface->wdinfo;
+			if (!rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE)) {
+				wfdielen = build_probe_req_wfd_ie(pwdinfo, pframe);
+				pframe += wfdielen;
+				pattrib->pktlen += wfdielen;
+			}
+		}
+	}
+}
+
+void rtw_build_tunneled_probe_rsp_ies(_adapter *padapter, struct xmit_frame *pxmitframe, u8 *pframe)
+{
+	u8 i;
+	_adapter *iface = NULL;
+	struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
+	struct pkt_attrib	*pattrib = &pxmitframe->attrib;
+	struct wifidirect_info *pwdinfo;
+	u8 category = RTW_WLAN_CATEGORY_P2P;
+	u8 WFA_OUI[3] = { 0x50, 0x6f, 0x9a};
+	u8 probe_rsp = 5;
+	u8 wfdielen = 0;
+
+	pframe = rtw_tdls_set_payload_type(pframe, pattrib);
+	pframe = rtw_set_fixed_ie(pframe, 1, &(category), &(pattrib->pktlen));
+	pframe = rtw_set_fixed_ie(pframe, 3, WFA_OUI, &(pattrib->pktlen));
+	pframe = rtw_set_fixed_ie(pframe, 1, &(probe_rsp), &(pattrib->pktlen));
+
+	for (i = 0; i < dvobj->iface_nums; i++) {
+		iface = dvobj->padapters[i];
+		if ((iface) && rtw_is_adapter_up(iface)) {
+			pwdinfo = &iface->wdinfo;
+			if (!rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE)) {
+				wfdielen = build_probe_resp_wfd_ie(pwdinfo, pframe, 1);
+				pframe += wfdielen;
+				pattrib->pktlen += wfdielen;
+			}
+		}
+	}
+}
+#endif /* CONFIG_WFD */
+
+void _tdls_tpk_timer_hdl(void *FunctionContext)
+{
+	struct sta_info *ptdls_sta = (struct sta_info *)FunctionContext;
+	struct tdls_txmgmt txmgmt;
+
+	_rtw_memset(&txmgmt, 0x00, sizeof(struct tdls_txmgmt));
+	ptdls_sta->TPK_count++;
+	/* TPK_timer expired in a second */
+	/* Retry timer should set at least 301 sec. */
+	if (ptdls_sta->TPK_count >= (ptdls_sta->TDLS_PeerKey_Lifetime - 3)) {
+		RTW_INFO("[TDLS] %s, Re-Setup TDLS link with "MAC_FMT" since TPK lifetime expires!\n",
+			__FUNCTION__, MAC_ARG(ptdls_sta->cmn.mac_addr));
+		ptdls_sta->TPK_count = 0;
+		_rtw_memcpy(txmgmt.peer, ptdls_sta->cmn.mac_addr, ETH_ALEN);
+		issue_tdls_setup_req(ptdls_sta->padapter, &txmgmt, _FALSE);
+	}
+
+	_set_timer(&ptdls_sta->TPK_timer, ONE_SEC);
+}
+
+#ifdef CONFIG_TDLS_CH_SW
+void _tdls_ch_switch_timer_hdl(void *FunctionContext)
+{
+	struct sta_info *ptdls_sta = (struct sta_info *)FunctionContext;
+	_adapter *padapter = ptdls_sta->padapter;
+	struct tdls_ch_switch *pchsw_info = &padapter->tdlsinfo.chsw_info;
+
+	rtw_tdls_cmd(padapter, ptdls_sta->cmn.mac_addr, TDLS_CH_SW_END_TO_BASE_CHNL);
+	RTW_INFO("[TDLS] %s, can't get traffic from op_ch:%d\n", __func__, rtw_get_oper_ch(padapter));
+}
+
+void _tdls_delay_timer_hdl(void *FunctionContext)
+{
+	struct sta_info *ptdls_sta = (struct sta_info *)FunctionContext;
+	_adapter *padapter = ptdls_sta->padapter;
+	struct tdls_ch_switch *pchsw_info = &padapter->tdlsinfo.chsw_info;
+
+	RTW_INFO("[TDLS] %s, op_ch:%d, tdls_state:0x%08x\n", __func__, rtw_get_oper_ch(padapter), ptdls_sta->tdls_sta_state);
+	pchsw_info->delay_switch_back = _TRUE;
+}
+
+void _tdls_stay_on_base_chnl_timer_hdl(void *FunctionContext)
+{
+	struct sta_info *ptdls_sta = (struct sta_info *)FunctionContext;
+	_adapter *padapter = ptdls_sta->padapter;
+	struct tdls_ch_switch *pchsw_info = &padapter->tdlsinfo.chsw_info;
+
+	if (ptdls_sta != NULL) {
+		issue_tdls_ch_switch_req(padapter, ptdls_sta);
+		pchsw_info->ch_sw_state |= TDLS_WAIT_CH_RSP_STATE;
+	}
+}
+
+void _tdls_ch_switch_monitor_timer_hdl(void *FunctionContext)
+{
+	struct sta_info *ptdls_sta = (struct sta_info *)FunctionContext;
+	_adapter *padapter = ptdls_sta->padapter;
+	struct tdls_ch_switch *pchsw_info = &padapter->tdlsinfo.chsw_info;
+
+	rtw_tdls_cmd(padapter, ptdls_sta->cmn.mac_addr, TDLS_CH_SW_END);
+	RTW_INFO("[TDLS] %s, does not receive ch sw req\n", __func__);
+}
+
+#endif
+
+void _tdls_handshake_timer_hdl(void *FunctionContext)
+{
+	struct sta_info *ptdls_sta = (struct sta_info *)FunctionContext;
+	_adapter *padapter = NULL;
+	struct tdls_txmgmt txmgmt;
+
+	_rtw_memset(&txmgmt, 0x00, sizeof(struct tdls_txmgmt));
+	_rtw_memcpy(txmgmt.peer, ptdls_sta->cmn.mac_addr, ETH_ALEN);
+	txmgmt.status_code = _RSON_TDLS_TEAR_UN_RSN_;
+
+	if (ptdls_sta != NULL) {
+		padapter = ptdls_sta->padapter;
+
+		RTW_INFO("[TDLS] Handshake time out\n");
+		if (ptdls_sta->tdls_sta_state & TDLS_LINKED_STATE)
+			rtw_tdls_cmd(padapter, ptdls_sta->cmn.mac_addr, TDLS_TEARDOWN_STA);
+		else
+			rtw_tdls_cmd(padapter, ptdls_sta->cmn.mac_addr, TDLS_TEARDOWN_STA_LOCALLY);
+	}
+}
+
+void _tdls_pti_timer_hdl(void *FunctionContext)
+{
+	struct sta_info *ptdls_sta = (struct sta_info *)FunctionContext;
+	_adapter *padapter = NULL;
+	struct tdls_txmgmt txmgmt;
+
+	_rtw_memset(&txmgmt, 0x00, sizeof(struct tdls_txmgmt));
+	_rtw_memcpy(txmgmt.peer, ptdls_sta->cmn.mac_addr, ETH_ALEN);
+	txmgmt.status_code = _RSON_TDLS_TEAR_TOOFAR_;
+
+	if (ptdls_sta != NULL) {
+		padapter = ptdls_sta->padapter;
+
+		if (ptdls_sta->tdls_sta_state & TDLS_WAIT_PTR_STATE) {
+			RTW_INFO("[TDLS] Doesn't receive PTR from peer dev:"MAC_FMT"; "
+				"Send TDLS Tear Down\n", MAC_ARG(ptdls_sta->cmn.mac_addr));
+			rtw_tdls_cmd(padapter, ptdls_sta->cmn.mac_addr, TDLS_TEARDOWN_STA);
+		}
+	}
+}
+
+void rtw_init_tdls_timer(_adapter *padapter, struct sta_info *psta)
+{
+	psta->padapter = padapter;
+	rtw_init_timer(&psta->TPK_timer, padapter, _tdls_tpk_timer_hdl, psta);
+#ifdef CONFIG_TDLS_CH_SW
+	rtw_init_timer(&psta->ch_sw_timer, padapter, _tdls_ch_switch_timer_hdl, psta);
+	rtw_init_timer(&psta->delay_timer, padapter, _tdls_delay_timer_hdl, psta);
+	rtw_init_timer(&psta->stay_on_base_chnl_timer, padapter, _tdls_stay_on_base_chnl_timer_hdl, psta);
+	rtw_init_timer(&psta->ch_sw_monitor_timer, padapter, _tdls_ch_switch_monitor_timer_hdl, psta);
+#endif
+	rtw_init_timer(&psta->handshake_timer, padapter, _tdls_handshake_timer_hdl, psta);
+	rtw_init_timer(&psta->pti_timer, padapter, _tdls_pti_timer_hdl, psta);
+}
+
+void rtw_cancel_tdls_timer(struct sta_info *psta)
+{
+	_cancel_timer_ex(&psta->TPK_timer);
+#ifdef CONFIG_TDLS_CH_SW
+	_cancel_timer_ex(&psta->ch_sw_timer);
+	_cancel_timer_ex(&psta->delay_timer);
+	_cancel_timer_ex(&psta->stay_on_base_chnl_timer);
+	_cancel_timer_ex(&psta->ch_sw_monitor_timer);
+#endif
+	_cancel_timer_ex(&psta->handshake_timer);
+	_cancel_timer_ex(&psta->pti_timer);
+}
+
+void rtw_tdls_teardown_pre_hdl(_adapter *padapter, struct sta_info *psta)
+{
+	struct tdls_info *ptdlsinfo = &padapter->tdlsinfo;
+	struct sta_priv *pstapriv = &padapter->stapriv;
+	_irqL irqL;
+
+	rtw_cancel_tdls_timer(psta);
+
+	_enter_critical_bh(&(pstapriv->sta_hash_lock), &irqL);
+	if (ptdlsinfo->sta_cnt != 0)
+		ptdlsinfo->sta_cnt--;
+	_exit_critical_bh(&(pstapriv->sta_hash_lock), &irqL);
+
+	if (ptdlsinfo->sta_cnt < MAX_ALLOWED_TDLS_STA_NUM) {
+		ptdlsinfo->sta_maximum = _FALSE;
+		_rtw_memset(&ptdlsinfo->ss_record, 0x00, sizeof(struct tdls_ss_record));
+	}
+
+	if (ptdlsinfo->sta_cnt == 0)
+		rtw_tdls_set_link_established(padapter, _FALSE);
+	else
+		RTW_INFO("Remain tdls sta:%02x\n", ptdlsinfo->sta_cnt);
+}
+
+void rtw_tdls_teardown_post_hdl(_adapter *padapter, struct sta_info *psta, u8 enqueue_cmd)
+{
+	struct tdls_info *ptdlsinfo = &padapter->tdlsinfo;
+
+	/* Clear cam */
+	rtw_clearstakey_cmd(padapter, psta, enqueue_cmd);
+
+	/* Update sta media status */
+	if (enqueue_cmd)
+		rtw_sta_media_status_rpt_cmd(padapter, psta, 0);
+	else
+		rtw_sta_media_status_rpt(padapter, psta, 0);
+
+	/* Set RCR if necessary */
+	if (ptdlsinfo->sta_cnt == 0) {
+		if (enqueue_cmd)
+			rtw_tdls_cmd(padapter, NULL, TDLS_RS_RCR);
+		else
+			rtw_hal_rcr_set_chk_bssid(padapter, MLME_TDLS_NOLINK);
+	}
+
+	/* Free tdls sta info */
+	rtw_free_stainfo(padapter,  psta);
+}
+
+int rtw_tdls_is_driver_setup(_adapter *padapter)
+{
+	return padapter->tdlsinfo.driver_setup;
+}
+
+const char *rtw_tdls_action_txt(enum TDLS_ACTION_FIELD action)
+{
+	switch (action) {
+	case TDLS_SETUP_REQUEST:
+		return "TDLS_SETUP_REQUEST";
+	case TDLS_SETUP_RESPONSE:
+		return "TDLS_SETUP_RESPONSE";
+	case TDLS_SETUP_CONFIRM:
+		return "TDLS_SETUP_CONFIRM";
+	case TDLS_TEARDOWN:
+		return "TDLS_TEARDOWN";
+	case TDLS_PEER_TRAFFIC_INDICATION:
+		return "TDLS_PEER_TRAFFIC_INDICATION";
+	case TDLS_CHANNEL_SWITCH_REQUEST:
+		return "TDLS_CHANNEL_SWITCH_REQUEST";
+	case TDLS_CHANNEL_SWITCH_RESPONSE:
+		return "TDLS_CHANNEL_SWITCH_RESPONSE";
+	case TDLS_PEER_PSM_REQUEST:
+		return "TDLS_PEER_PSM_REQUEST";
+	case TDLS_PEER_PSM_RESPONSE:
+		return "TDLS_PEER_PSM_RESPONSE";
+	case TDLS_PEER_TRAFFIC_RESPONSE:
+		return "TDLS_PEER_TRAFFIC_RESPONSE";
+	case TDLS_DISCOVERY_REQUEST:
+		return "TDLS_DISCOVERY_REQUEST";
+	case TDLS_DISCOVERY_RESPONSE:
+		return "TDLS_DISCOVERY_RESPONSE";
+	default:
+		return "UNKNOWN";
+	}
+}
+
+#endif /* CONFIG_TDLS */
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/core/rtw_wapi.c linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/core/rtw_wapi.c
--- linux-5.6.3/3rdparty/rtl8821ce/core/rtw_wapi.c	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/core/rtw_wapi.c	2020-04-10 16:35:06.779658341 +0300
@@ -0,0 +1,1312 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2016 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#ifdef CONFIG_WAPI_SUPPORT
+
+#include <linux/unistd.h>
+#include <linux/etherdevice.h>
+#include <drv_types.h>
+#include <rtw_wapi.h>
+
+
+u32 wapi_debug_component =
+	/*				WAPI_INIT	|
+	 *				WAPI_API	|
+	 *				WAPI_TX	|
+	 *				WAPI_RX	| */
+	WAPI_ERR ; /* always open err flags on */
+
+void WapiFreeAllStaInfo(_adapter *padapter)
+{
+	PRT_WAPI_T				pWapiInfo;
+	PRT_WAPI_STA_INFO		pWapiStaInfo;
+	PRT_WAPI_BKID			pWapiBkid;
+
+	WAPI_TRACE(WAPI_INIT, "===========> %s\n", __FUNCTION__);
+	pWapiInfo = &padapter->wapiInfo;
+
+	/* Pust to Idle List */
+	rtw_wapi_return_all_sta_info(padapter);
+
+	/* Sta Info List */
+	while (!list_empty(&(pWapiInfo->wapiSTAIdleList))) {
+		pWapiStaInfo = (PRT_WAPI_STA_INFO)list_entry(pWapiInfo->wapiSTAIdleList.next, RT_WAPI_STA_INFO, list);
+		list_del_init(&pWapiStaInfo->list);
+	}
+
+	/* BKID List */
+	while (!list_empty(&(pWapiInfo->wapiBKIDIdleList))) {
+		pWapiBkid = (PRT_WAPI_BKID)list_entry(pWapiInfo->wapiBKIDIdleList.next, RT_WAPI_BKID, list);
+		list_del_init(&pWapiBkid->list);
+	}
+	WAPI_TRACE(WAPI_INIT, "<=========== %s\n", __FUNCTION__);
+	return;
+}
+
+void WapiSetIE(_adapter *padapter)
+{
+	PRT_WAPI_T		pWapiInfo = &(padapter->wapiInfo);
+	/* PRT_WAPI_BKID	pWapiBkid; */
+	u16		protocolVer = 1;
+	u16		akmCnt = 1;
+	u16		suiteCnt = 1;
+	u16		capability = 0;
+	u8		OUI[3];
+
+	OUI[0] = 0x00;
+	OUI[1] = 0x14;
+	OUI[2] = 0x72;
+
+	pWapiInfo->wapiIELength = 0;
+	/* protocol version */
+	memcpy(pWapiInfo->wapiIE + pWapiInfo->wapiIELength, &protocolVer, 2);
+	pWapiInfo->wapiIELength += 2;
+	/* akm */
+	memcpy(pWapiInfo->wapiIE + pWapiInfo->wapiIELength, &akmCnt, 2);
+	pWapiInfo->wapiIELength += 2;
+
+	if (pWapiInfo->bWapiPSK) {
+		memcpy(pWapiInfo->wapiIE + pWapiInfo->wapiIELength, OUI, 3);
+		pWapiInfo->wapiIELength += 3;
+		pWapiInfo->wapiIE[pWapiInfo->wapiIELength] = 0x2;
+		pWapiInfo->wapiIELength += 1;
+	} else {
+		memcpy(pWapiInfo->wapiIE + pWapiInfo->wapiIELength, OUI, 3);
+		pWapiInfo->wapiIELength += 3;
+		pWapiInfo->wapiIE[pWapiInfo->wapiIELength] = 0x1;
+		pWapiInfo->wapiIELength += 1;
+	}
+
+	/* usk */
+	memcpy(pWapiInfo->wapiIE + pWapiInfo->wapiIELength, &suiteCnt, 2);
+	pWapiInfo->wapiIELength += 2;
+	memcpy(pWapiInfo->wapiIE + pWapiInfo->wapiIELength, OUI, 3);
+	pWapiInfo->wapiIELength += 3;
+	pWapiInfo->wapiIE[pWapiInfo->wapiIELength] = 0x1;
+	pWapiInfo->wapiIELength += 1;
+
+	/* msk */
+	memcpy(pWapiInfo->wapiIE + pWapiInfo->wapiIELength, OUI, 3);
+	pWapiInfo->wapiIELength += 3;
+	pWapiInfo->wapiIE[pWapiInfo->wapiIELength] = 0x1;
+	pWapiInfo->wapiIELength += 1;
+
+	/* Capbility */
+	memcpy(pWapiInfo->wapiIE + pWapiInfo->wapiIELength, &capability, 2);
+	pWapiInfo->wapiIELength += 2;
+}
+
+
+/*  PN1 > PN2, return 1,
+ *  else return 0.
+ */
+u32 WapiComparePN(u8 *PN1, u8 *PN2)
+{
+	char i;
+
+	if ((NULL == PN1) || (NULL == PN2))
+		return 1;
+
+	/* overflow case */
+	if ((PN2[15] - PN1[15]) & 0x80)
+		return 1;
+
+	for (i = 16; i > 0; i--) {
+		if (PN1[i - 1] == PN2[i - 1])
+			continue;
+		else if (PN1[i - 1] > PN2[i - 1])
+			return 1;
+		else
+			return 0;
+	}
+
+	return 0;
+}
+
+u8
+WapiGetEntryForCamWrite(_adapter *padapter, u8 *pMacAddr, u8 KID, BOOLEAN IsMsk)
+{
+	PRT_WAPI_T		pWapiInfo = NULL;
+	/* PRT_WAPI_CAM_ENTRY	pEntry=NULL; */
+	u8 i = 0;
+	u8 ret = 0xff;
+
+	WAPI_TRACE(WAPI_API, "===========> %s\n", __FUNCTION__);
+
+	pWapiInfo =  &padapter->wapiInfo;
+
+	/* exist? */
+	for (i = 0; i < WAPI_CAM_ENTRY_NUM; i++) {
+		if (pWapiInfo->wapiCamEntry[i].IsUsed
+		    && (_rtw_memcmp(pMacAddr, pWapiInfo->wapiCamEntry[i].PeerMacAddr, ETH_ALEN) == _TRUE)
+		    && pWapiInfo->wapiCamEntry[i].keyidx == KID
+		    && pWapiInfo->wapiCamEntry[i].type == IsMsk) {
+			ret = pWapiInfo->wapiCamEntry[i].entry_idx; /* cover it */
+			break;
+		}
+	}
+
+	if (i == WAPI_CAM_ENTRY_NUM) { /* not found */
+		for (i = 0; i < WAPI_CAM_ENTRY_NUM; i++) {
+			if (pWapiInfo->wapiCamEntry[i].IsUsed == 0) {
+				pWapiInfo->wapiCamEntry[i].IsUsed = 1;
+				pWapiInfo->wapiCamEntry[i].type = IsMsk;
+				pWapiInfo->wapiCamEntry[i].keyidx = KID;
+				_rtw_memcpy(pWapiInfo->wapiCamEntry[i].PeerMacAddr, pMacAddr, ETH_ALEN);
+				ret = pWapiInfo->wapiCamEntry[i].entry_idx;
+				break;
+			}
+		}
+	}
+
+	WAPI_TRACE(WAPI_API, "<========== %s\n", __FUNCTION__);
+	return ret;
+
+	/*
+		if(RTIsListEmpty(&pWapiInfo->wapiCamIdleList)) {
+			return 0;
+		}
+
+		pEntry = (PRT_WAPI_CAM_ENTRY)RTRemoveHeadList(&pWapiInfo->wapiCamIdleList);
+		RTInsertTailList(&pWapiInfo->wapiCamUsedList, &pEntry->list);
+
+
+		return pEntry->entry_idx;*/
+}
+
+u8 WapiGetEntryForCamClear(_adapter *padapter, u8 *pPeerMac, u8 keyid, u8 IsMsk)
+{
+	PRT_WAPI_T		pWapiInfo = NULL;
+	u8		i = 0;
+
+	WAPI_TRACE(WAPI_API, "===========> %s\n", __FUNCTION__);
+
+	pWapiInfo =  &padapter->wapiInfo;
+
+	for (i = 0; i < WAPI_CAM_ENTRY_NUM; i++) {
+		if (pWapiInfo->wapiCamEntry[i].IsUsed
+		    && (_rtw_memcmp(pPeerMac, pWapiInfo->wapiCamEntry[i].PeerMacAddr, ETH_ALEN) == _TRUE)
+		    && pWapiInfo->wapiCamEntry[i].keyidx == keyid
+		    && pWapiInfo->wapiCamEntry[i].type == IsMsk) {
+			pWapiInfo->wapiCamEntry[i].IsUsed = 0;
+			pWapiInfo->wapiCamEntry[i].keyidx = 2;
+			_rtw_memset(pWapiInfo->wapiCamEntry[i].PeerMacAddr, 0, ETH_ALEN);
+
+			WAPI_TRACE(WAPI_API, "<========== %s\n", __FUNCTION__);
+			return pWapiInfo->wapiCamEntry[i].entry_idx;
+		}
+	}
+
+	WAPI_TRACE(WAPI_API, "<====WapiGetReturnCamEntry(), No this cam entry.\n");
+	return 0xff;
+	/*
+		if(RTIsListEmpty(&pWapiInfo->wapiCamUsedList)) {
+			return FALSE;
+		}
+
+		pList = &pWapiInfo->wapiCamUsedList;
+		while(pList->Flink != &pWapiInfo->wapiCamUsedList)
+		{
+			pEntry = (PRT_WAPI_CAM_ENTRY)pList->Flink;
+			if(PlatformCompareMemory(pPeerMac,pEntry->PeerMacAddr, ETHER_ADDRLEN)== 0
+				&& keyid == pEntry->keyidx)
+			{
+				RTRemoveEntryList(pList);
+				RTInsertHeadList(&pWapiInfo->wapiCamIdleList, pList);
+				return pEntry->entry_idx;
+			}
+			pList = pList->Flink;
+		}
+
+		return 0;
+	*/
+}
+
+void
+WapiResetAllCamEntry(_adapter *padapter)
+{
+	PRT_WAPI_T		pWapiInfo;
+	int				i;
+
+	WAPI_TRACE(WAPI_API, "===========> %s\n", __FUNCTION__);
+
+	pWapiInfo =  &padapter->wapiInfo;
+
+	for (i = 0; i < WAPI_CAM_ENTRY_NUM; i++) {
+		_rtw_memset(pWapiInfo->wapiCamEntry[i].PeerMacAddr, 0, ETH_ALEN);
+		pWapiInfo->wapiCamEntry[i].IsUsed = 0;
+		pWapiInfo->wapiCamEntry[i].keyidx = 2; /* invalid */
+		pWapiInfo->wapiCamEntry[i].entry_idx = 4 + i * 2;
+	}
+
+	WAPI_TRACE(WAPI_API, "<========== %s\n", __FUNCTION__);
+
+	return;
+}
+
+u8 WapiWriteOneCamEntry(
+	_adapter	*padapter,
+	u8			*pMacAddr,
+	u8			KeyId,
+	u8			EntryId,
+	u8			EncAlg,
+	u8			bGroupKey,
+	u8			*pKey
+)
+{
+	u8 retVal = 0;
+	u16 usConfig = 0;
+
+	WAPI_TRACE(WAPI_API, "===========> %s\n", __FUNCTION__);
+
+	if (EntryId >= 32) {
+		WAPI_TRACE(WAPI_ERR, "<=== CamAddOneEntry(): ulKeyId exceed!\n");
+		return retVal;
+	}
+
+	usConfig = usConfig | (0x01 << 15) | ((u16)(EncAlg) << 2) | (KeyId);
+
+	if (EncAlg == _SMS4_) {
+		if (bGroupKey == 1)
+			usConfig |= (0x01 << 6);
+		if ((EntryId % 2) == 1) /* ==0 sec key; == 1mic key */
+			usConfig |= (0x01 << 5);
+	}
+
+	write_cam(padapter, EntryId, usConfig, pMacAddr, pKey);
+
+	WAPI_TRACE(WAPI_API, "===========> %s\n", __FUNCTION__);
+	return 1;
+}
+
+void rtw_wapi_init(_adapter *padapter)
+{
+	PRT_WAPI_T		pWapiInfo;
+	int				i;
+
+	WAPI_TRACE(WAPI_INIT, "===========> %s\n", __FUNCTION__);
+	RT_ASSERT_RET(padapter);
+
+	if (!padapter->WapiSupport) {
+		WAPI_TRACE(WAPI_INIT, "<========== %s, WAPI not supported!\n", __FUNCTION__);
+		return;
+	}
+
+	pWapiInfo =  &padapter->wapiInfo;
+	pWapiInfo->bWapiEnable = false;
+
+	/* Init BKID List */
+	INIT_LIST_HEAD(&pWapiInfo->wapiBKIDIdleList);
+	INIT_LIST_HEAD(&pWapiInfo->wapiBKIDStoreList);
+	for (i = 0; i < WAPI_MAX_BKID_NUM; i++)
+		list_add_tail(&pWapiInfo->wapiBKID[i].list, &pWapiInfo->wapiBKIDIdleList);
+
+	/* Init STA List */
+	INIT_LIST_HEAD(&pWapiInfo->wapiSTAIdleList);
+	INIT_LIST_HEAD(&pWapiInfo->wapiSTAUsedList);
+	for (i = 0; i < WAPI_MAX_STAINFO_NUM; i++)
+		list_add_tail(&pWapiInfo->wapiSta[i].list, &pWapiInfo->wapiSTAIdleList);
+
+	for (i = 0; i < WAPI_CAM_ENTRY_NUM; i++) {
+		pWapiInfo->wapiCamEntry[i].IsUsed = 0;
+		pWapiInfo->wapiCamEntry[i].keyidx = 2; /* invalid */
+		pWapiInfo->wapiCamEntry[i].entry_idx = 4 + i * 2;
+	}
+
+	WAPI_TRACE(WAPI_INIT, "<========== %s\n", __FUNCTION__);
+}
+
+void rtw_wapi_free(_adapter *padapter)
+{
+	WAPI_TRACE(WAPI_INIT, "===========> %s\n", __FUNCTION__);
+	RT_ASSERT_RET(padapter);
+
+	if (!padapter->WapiSupport) {
+		WAPI_TRACE(WAPI_INIT, "<========== %s, WAPI not supported!\n", __FUNCTION__);
+		return;
+	}
+
+	WapiFreeAllStaInfo(padapter);
+
+	WAPI_TRACE(WAPI_INIT, "<========== %s\n", __FUNCTION__);
+}
+
+void rtw_wapi_disable_tx(_adapter *padapter)
+{
+	WAPI_TRACE(WAPI_INIT, "===========> %s\n", __FUNCTION__);
+	RT_ASSERT_RET(padapter);
+
+	if (!padapter->WapiSupport) {
+		WAPI_TRACE(WAPI_INIT, "<========== %s, WAPI not supported!\n", __FUNCTION__);
+		return;
+	}
+
+	padapter->wapiInfo.wapiTxMsk.bTxEnable = false;
+	padapter->wapiInfo.wapiTxMsk.bSet = false;
+
+	WAPI_TRACE(WAPI_INIT, "<========== %s\n", __FUNCTION__);
+}
+
+u8 rtw_wapi_is_wai_packet(_adapter *padapter, u8 *pkt_data)
+{
+	PRT_WAPI_T pWapiInfo = &(padapter->wapiInfo);
+	struct mlme_priv	*pmlmepriv = &padapter->mlmepriv;
+	struct security_priv   *psecuritypriv = &padapter->securitypriv;
+	PRT_WAPI_STA_INFO pWapiSta = NULL;
+	u8 WaiPkt = 0, *pTaddr, bFind = false;
+	u8 Offset_TypeWAI = 0 ;	/* (mac header len + llc length) */
+
+	WAPI_TRACE(WAPI_TX | WAPI_RX, "===========> %s\n", __FUNCTION__);
+
+	if ((!padapter->WapiSupport) || (!pWapiInfo->bWapiEnable)) {
+		WAPI_TRACE(WAPI_MLME, "<========== %s, WAPI not supported or not enabled!\n", __FUNCTION__);
+		return 0;
+	}
+
+	Offset_TypeWAI = 24 + 6 ;
+
+	/* YJ,add,091103. Data frame may also have skb->data[30]=0x88 and skb->data[31]=0xb4. */
+	if ((pkt_data[1] & 0x40) != 0) {
+		/* RTW_INFO("data is privacy\n"); */
+		return 0;
+	}
+
+	pTaddr = get_addr2_ptr(pkt_data);
+	if (list_empty(&pWapiInfo->wapiSTAUsedList))
+		bFind = false;
+	else {
+		list_for_each_entry(pWapiSta, &pWapiInfo->wapiSTAUsedList, list) {
+			if (_rtw_memcmp(pTaddr, pWapiSta->PeerMacAddr, 6) == _TRUE) {
+				bFind = true;
+				break;
+			}
+		}
+	}
+
+	WAPI_TRACE(WAPI_TX | WAPI_RX, "%s: bFind=%d pTaddr="MAC_FMT"\n", __FUNCTION__, bFind, MAC_ARG(pTaddr));
+
+	if (pkt_data[0] == WIFI_QOS_DATA_TYPE)
+		Offset_TypeWAI += 2;
+
+	/* 88b4? */
+	if ((pkt_data[Offset_TypeWAI] == 0x88) && (pkt_data[Offset_TypeWAI + 1] == 0xb4)) {
+		WaiPkt = pkt_data[Offset_TypeWAI + 5];
+
+		psecuritypriv->hw_decrypted = _TRUE;
+	} else
+		WAPI_TRACE(WAPI_TX | WAPI_RX, "%s(): non wai packet\n", __FUNCTION__);
+
+	WAPI_TRACE(WAPI_TX | WAPI_RX, "%s(): Recvd WAI frame. IsWAIPkt(%d)\n", __FUNCTION__, WaiPkt);
+
+	return	WaiPkt;
+}
+
+
+void rtw_wapi_update_info(_adapter *padapter, union recv_frame *precv_frame)
+{
+	PRT_WAPI_T     pWapiInfo = &(padapter->wapiInfo);
+	struct recv_frame_hdr *precv_hdr;
+	u8	*ptr;
+	u8	*pTA;
+	u8	*pRecvPN;
+
+
+	WAPI_TRACE(WAPI_RX, "===========> %s\n", __FUNCTION__);
+
+	if ((!padapter->WapiSupport) || (!pWapiInfo->bWapiEnable)) {
+		WAPI_TRACE(WAPI_RX, "<========== %s, WAPI not supported or not enabled!\n", __FUNCTION__);
+		return;
+	}
+
+	precv_hdr = &precv_frame->u.hdr;
+	ptr = precv_hdr->rx_data;
+
+	if (precv_hdr->attrib.qos == 1)
+		precv_hdr->UserPriority = GetTid(ptr);
+	else
+		precv_hdr->UserPriority = 0;
+
+	pTA = get_addr2_ptr(ptr);
+	_rtw_memcpy((u8 *)precv_hdr->WapiSrcAddr, pTA, 6);
+	pRecvPN = ptr + precv_hdr->attrib.hdrlen + 2;
+	_rtw_memcpy((u8 *)precv_hdr->WapiTempPN, pRecvPN, 16);
+
+	WAPI_TRACE(WAPI_RX, "<========== %s\n", __FUNCTION__);
+}
+
+/****************************************************************************
+TRUE-----------------Drop
+FALSE---------------- handle
+add to support WAPI to N-mode
+*****************************************************************************/
+u8 rtw_wapi_check_for_drop(
+	_adapter *padapter,
+	union recv_frame *precv_frame,
+	u8 *ehdr_ops
+)
+{
+	PRT_WAPI_T     pWapiInfo = &(padapter->wapiInfo);
+	u8			*pLastRecvPN = NULL;
+	u8			bFind = false;
+	PRT_WAPI_STA_INFO	pWapiSta = NULL;
+	u8			bDrop = false;
+	struct recv_frame_hdr *precv_hdr = &precv_frame->u.hdr;
+	u8					WapiAEPNInitialValueSrc[16] = {0x37, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C} ;
+	u8					WapiAEMultiCastPNInitialValueSrc[16] = {0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C} ;
+	u8					*ptr = ehdr_ops;
+	int					i;
+
+	WAPI_TRACE(WAPI_RX, "===========> %s\n", __FUNCTION__);
+
+	if ((!padapter->WapiSupport) || (!pWapiInfo->bWapiEnable)) {
+		WAPI_TRACE(WAPI_RX, "<========== %s, WAPI not supported or not enabled!\n", __FUNCTION__);
+		return false;
+	}
+
+	if (precv_hdr->bIsWaiPacket != 0) {
+		if (precv_hdr->bIsWaiPacket == 0x8) {
+
+			RTW_INFO("rtw_wapi_check_for_drop: dump packet\n");
+			for (i = 0; i < 50; i++) {
+				RTW_INFO("%02X  ", ptr[i]);
+				if ((i + 1) % 8 == 0)
+					RTW_INFO("\n");
+			}
+			RTW_INFO("\n rtw_wapi_check_for_drop: dump packet\n");
+
+			for (i = 0; i < 16; i++) {
+				if (ptr[i + 27] != 0)
+					break;
+			}
+
+			if (i == 16) {
+				WAPI_TRACE(WAPI_RX, "rtw_wapi_check_for_drop: drop with zero BKID\n");
+				return true;
+			} else
+				return false;
+		} else
+			return false;
+	}
+
+	if (list_empty(&pWapiInfo->wapiSTAUsedList))
+		bFind = false;
+	else {
+		list_for_each_entry(pWapiSta, &pWapiInfo->wapiSTAUsedList, list) {
+			if (_rtw_memcmp(precv_hdr->WapiSrcAddr, pWapiSta->PeerMacAddr, ETH_ALEN) == _TRUE) {
+				bFind = true;
+				break;
+			}
+		}
+	}
+	WAPI_TRACE(WAPI_RX, "%s: bFind=%d prxb->WapiSrcAddr="MAC_FMT"\n", __FUNCTION__, bFind, MAC_ARG(precv_hdr->WapiSrcAddr));
+
+	if (bFind) {
+		if (IS_MCAST(precv_hdr->attrib.ra)) {
+			WAPI_TRACE(WAPI_RX, "rtw_wapi_check_for_drop: multicast case\n");
+			pLastRecvPN = pWapiSta->lastRxMulticastPN;
+		} else {
+			WAPI_TRACE(WAPI_RX, "rtw_wapi_check_for_drop: unicast case\n");
+			switch (precv_hdr->UserPriority) {
+			case 0:
+			case 3:
+				pLastRecvPN = pWapiSta->lastRxUnicastPNBEQueue;
+				break;
+			case 1:
+			case 2:
+				pLastRecvPN = pWapiSta->lastRxUnicastPNBKQueue;
+				break;
+			case 4:
+			case 5:
+				pLastRecvPN = pWapiSta->lastRxUnicastPNVIQueue;
+				break;
+			case 6:
+			case 7:
+				pLastRecvPN = pWapiSta->lastRxUnicastPNVOQueue;
+				break;
+			default:
+				WAPI_TRACE(WAPI_ERR, "%s: Unknown TID\n", __FUNCTION__);
+				break;
+			}
+		}
+
+		if (!WapiComparePN(precv_hdr->WapiTempPN, pLastRecvPN)) {
+			WAPI_TRACE(WAPI_RX, "%s: Equal PN!!\n", __FUNCTION__);
+			if (IS_MCAST(precv_hdr->attrib.ra))
+				_rtw_memcpy(pLastRecvPN, WapiAEMultiCastPNInitialValueSrc, 16);
+			else
+				_rtw_memcpy(pLastRecvPN, WapiAEPNInitialValueSrc, 16);
+			bDrop = true;
+		} else
+			_rtw_memcpy(pLastRecvPN, precv_hdr->WapiTempPN, 16);
+	}
+
+	WAPI_TRACE(WAPI_RX, "<========== %s\n", __FUNCTION__);
+	return bDrop;
+}
+
+void rtw_build_probe_resp_wapi_ie(_adapter *padapter, unsigned char *pframe, struct pkt_attrib *pattrib)
+{
+	PRT_WAPI_T pWapiInfo = &(padapter->wapiInfo);
+	u8 WapiIELength = 0;
+
+	WAPI_TRACE(WAPI_MLME, "===========> %s\n", __FUNCTION__);
+
+	if ((!padapter->WapiSupport)  || (!pWapiInfo->bWapiEnable)) {
+		WAPI_TRACE(WAPI_MLME, "<========== %s, WAPI not supported!\n", __FUNCTION__);
+		return;
+	}
+
+	WapiSetIE(padapter);
+	WapiIELength = pWapiInfo->wapiIELength;
+	pframe[0] = _WAPI_IE_;
+	pframe[1] = WapiIELength;
+	_rtw_memcpy(pframe + 2, pWapiInfo->wapiIE, WapiIELength);
+	pframe += WapiIELength + 2;
+	pattrib->pktlen += WapiIELength + 2;
+
+	WAPI_TRACE(WAPI_MLME, "<========== %s\n", __FUNCTION__);
+}
+
+void rtw_build_beacon_wapi_ie(_adapter *padapter, unsigned char *pframe, struct pkt_attrib *pattrib)
+{
+	PRT_WAPI_T pWapiInfo = &(padapter->wapiInfo);
+	u8 WapiIELength = 0;
+	WAPI_TRACE(WAPI_MLME, "===========> %s\n", __FUNCTION__);
+
+	if ((!padapter->WapiSupport)  || (!pWapiInfo->bWapiEnable)) {
+		WAPI_TRACE(WAPI_MLME, "<========== %s, WAPI not supported!\n", __FUNCTION__);
+		return;
+	}
+
+	WapiSetIE(padapter);
+	WapiIELength = pWapiInfo->wapiIELength;
+	pframe[0] = _WAPI_IE_;
+	pframe[1] = WapiIELength;
+	_rtw_memcpy(pframe + 2, pWapiInfo->wapiIE, WapiIELength);
+	pframe += WapiIELength + 2;
+	pattrib->pktlen += WapiIELength + 2;
+
+	WAPI_TRACE(WAPI_MLME, "<========== %s\n", __FUNCTION__);
+}
+
+void rtw_build_assoc_req_wapi_ie(_adapter *padapter, unsigned char *pframe, struct pkt_attrib *pattrib)
+{
+	PRT_WAPI_BKID		pWapiBKID;
+	u16					bkidNum;
+	PRT_WAPI_T			pWapiInfo = &(padapter->wapiInfo);
+	u8					WapiIELength = 0;
+
+	WAPI_TRACE(WAPI_MLME, "===========> %s\n", __FUNCTION__);
+
+	if ((!padapter->WapiSupport) || (!pWapiInfo->bWapiEnable)) {
+		WAPI_TRACE(WAPI_MLME, "<========== %s, WAPI not supported!\n", __FUNCTION__);
+		return;
+	}
+
+	WapiSetIE(padapter);
+	WapiIELength = pWapiInfo->wapiIELength;
+	bkidNum = 0;
+	if (!list_empty(&(pWapiInfo->wapiBKIDStoreList))) {
+		list_for_each_entry(pWapiBKID, &pWapiInfo->wapiBKIDStoreList, list) {
+			bkidNum++;
+			_rtw_memcpy(pWapiInfo->wapiIE + WapiIELength + 2, pWapiBKID->bkid, 16);
+			WapiIELength += 16;
+		}
+	}
+	_rtw_memcpy(pWapiInfo->wapiIE + WapiIELength, &bkidNum, 2);
+	WapiIELength += 2;
+
+	pframe[0] = _WAPI_IE_;
+	pframe[1] = WapiIELength;
+	_rtw_memcpy(pframe + 2, pWapiInfo->wapiIE, WapiIELength);
+	pframe += WapiIELength + 2;
+	pattrib->pktlen += WapiIELength + 2;
+	WAPI_TRACE(WAPI_MLME, "<========== %s\n", __FUNCTION__);
+}
+
+void rtw_wapi_on_assoc_ok(_adapter *padapter, PNDIS_802_11_VARIABLE_IEs pIE)
+{
+	PRT_WAPI_T pWapiInfo = &(padapter->wapiInfo);
+	PRT_WAPI_STA_INFO pWapiSta;
+	u8 WapiAEPNInitialValueSrc[16] = {0x37, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C} ;
+	/* u8 WapiASUEPNInitialValueSrc[16] = {0x36,0x5C,0x36,0x5C,0x36,0x5C,0x36,0x5C,0x36,0x5C,0x36,0x5C,0x36,0x5C,0x36,0x5C} ; */
+	u8 WapiAEMultiCastPNInitialValueSrc[16] = {0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C} ;
+
+	WAPI_TRACE(WAPI_MLME, "===========> %s\n", __FUNCTION__);
+
+	if ((!padapter->WapiSupport) || (!pWapiInfo->bWapiEnable)) {
+		WAPI_TRACE(WAPI_MLME, "<========== %s, WAPI not supported or not enabled!\n", __FUNCTION__);
+		return;
+	}
+
+	pWapiSta = (PRT_WAPI_STA_INFO)list_entry(pWapiInfo->wapiSTAIdleList.next, RT_WAPI_STA_INFO, list);
+	list_del_init(&pWapiSta->list);
+	list_add_tail(&pWapiSta->list, &pWapiInfo->wapiSTAUsedList);
+	_rtw_memcpy(pWapiSta->PeerMacAddr, padapter->mlmeextpriv.mlmext_info.network.MacAddress, 6);
+	_rtw_memcpy(pWapiSta->lastRxMulticastPN, WapiAEMultiCastPNInitialValueSrc, 16);
+	_rtw_memcpy(pWapiSta->lastRxUnicastPN, WapiAEPNInitialValueSrc, 16);
+
+	/* For chenk PN error with Qos Data after s3: add by ylb 20111114 */
+	_rtw_memcpy(pWapiSta->lastRxUnicastPNBEQueue, WapiAEPNInitialValueSrc, 16);
+	_rtw_memcpy(pWapiSta->lastRxUnicastPNBKQueue, WapiAEPNInitialValueSrc, 16);
+	_rtw_memcpy(pWapiSta->lastRxUnicastPNVIQueue, WapiAEPNInitialValueSrc, 16);
+	_rtw_memcpy(pWapiSta->lastRxUnicastPNVOQueue, WapiAEPNInitialValueSrc, 16);
+
+	WAPI_TRACE(WAPI_MLME, "<========== %s\n", __FUNCTION__);
+}
+
+
+void rtw_wapi_return_one_sta_info(_adapter *padapter, u8 *MacAddr)
+{
+	PRT_WAPI_T				pWapiInfo;
+	PRT_WAPI_STA_INFO		pWapiStaInfo = NULL;
+	PRT_WAPI_BKID			pWapiBkid = NULL;
+	struct mlme_priv	*pmlmepriv = &padapter->mlmepriv;
+
+	pWapiInfo = &padapter->wapiInfo;
+
+	WAPI_TRACE(WAPI_API, "==========> %s\n", __FUNCTION__);
+
+	if ((!padapter->WapiSupport) || (!pWapiInfo->bWapiEnable)) {
+		WAPI_TRACE(WAPI_MLME, "<========== %s, WAPI not supported or not enabled!\n", __FUNCTION__);
+		return;
+	}
+
+	if (check_fwstate(pmlmepriv, WIFI_STATION_STATE)) {
+		while (!list_empty(&(pWapiInfo->wapiBKIDStoreList))) {
+			pWapiBkid = (PRT_WAPI_BKID)list_entry(pWapiInfo->wapiBKIDStoreList.next, RT_WAPI_BKID, list);
+			list_del_init(&pWapiBkid->list);
+			_rtw_memset(pWapiBkid->bkid, 0, 16);
+			list_add_tail(&pWapiBkid->list, &pWapiInfo->wapiBKIDIdleList);
+		}
+	}
+
+
+	WAPI_TRACE(WAPI_API, " %s: after clear bkid\n", __FUNCTION__);
+
+
+	/* Remove STA info */
+	if (list_empty(&(pWapiInfo->wapiSTAUsedList))) {
+		WAPI_TRACE(WAPI_API, " %s: wapiSTAUsedList is null\n", __FUNCTION__);
+		return;
+	} else {
+
+		WAPI_TRACE(WAPI_API, " %s: wapiSTAUsedList is not null\n", __FUNCTION__);
+#if 0
+		pWapiStaInfo = (PRT_WAPI_STA_INFO)list_entry((pWapiInfo->wapiSTAUsedList.next), RT_WAPI_STA_INFO, list);
+
+		list_for_each_entry(pWapiStaInfo, &(pWapiInfo->wapiSTAUsedList), list) {
+
+			RTW_INFO("MAC Addr %02x-%02x-%02x-%02x-%02x-%02x\n", MacAddr[0], MacAddr[1], MacAddr[2], MacAddr[3], MacAddr[4], MacAddr[5]);
+
+
+			RTW_INFO("peer Addr %02x-%02x-%02x-%02x-%02x-%02x\n", pWapiStaInfo->PeerMacAddr[0], pWapiStaInfo->PeerMacAddr[1], pWapiStaInfo->PeerMacAddr[2], pWapiStaInfo->PeerMacAddr[3],
+				pWapiStaInfo->PeerMacAddr[4], pWapiStaInfo->PeerMacAddr[5]);
+
+			if (pWapiStaInfo == NULL) {
+				WAPI_TRACE(WAPI_API, " %s: pWapiStaInfo == NULL Case\n", __FUNCTION__);
+				return;
+			}
+
+			if (pWapiStaInfo->PeerMacAddr == NULL) {
+				WAPI_TRACE(WAPI_API, " %s: pWapiStaInfo->PeerMacAddr == NULL Case\n", __FUNCTION__);
+				return;
+			}
+
+			if (MacAddr == NULL) {
+				WAPI_TRACE(WAPI_API, " %s: MacAddr == NULL Case\n", __FUNCTION__);
+				return;
+			}
+
+			if (_rtw_memcmp(pWapiStaInfo->PeerMacAddr, MacAddr, ETH_ALEN) == _TRUE) {
+				pWapiStaInfo->bAuthenticateInProgress = false;
+				pWapiStaInfo->bSetkeyOk = false;
+				_rtw_memset(pWapiStaInfo->PeerMacAddr, 0, ETH_ALEN);
+				list_del_init(&pWapiStaInfo->list);
+				list_add_tail(&pWapiStaInfo->list, &pWapiInfo->wapiSTAIdleList);
+				break;
+			}
+
+		}
+#endif
+
+		while (!list_empty(&(pWapiInfo->wapiSTAUsedList))) {
+			pWapiStaInfo = (PRT_WAPI_STA_INFO)list_entry(pWapiInfo->wapiSTAUsedList.next, RT_WAPI_STA_INFO, list);
+
+			RTW_INFO("peer Addr %02x-%02x-%02x-%02x-%02x-%02x\n", pWapiStaInfo->PeerMacAddr[0], pWapiStaInfo->PeerMacAddr[1], pWapiStaInfo->PeerMacAddr[2], pWapiStaInfo->PeerMacAddr[3],
+				pWapiStaInfo->PeerMacAddr[4], pWapiStaInfo->PeerMacAddr[5]);
+
+			list_del_init(&pWapiStaInfo->list);
+			memset(pWapiStaInfo->PeerMacAddr, 0, ETH_ALEN);
+			pWapiStaInfo->bSetkeyOk = 0;
+			list_add_tail(&pWapiStaInfo->list, &pWapiInfo->wapiSTAIdleList);
+		}
+
+	}
+
+	WAPI_TRACE(WAPI_API, "<========== %s\n", __FUNCTION__);
+	return;
+}
+
+void rtw_wapi_return_all_sta_info(_adapter *padapter)
+{
+	PRT_WAPI_T				pWapiInfo;
+	PRT_WAPI_STA_INFO		pWapiStaInfo;
+	PRT_WAPI_BKID			pWapiBkid;
+	WAPI_TRACE(WAPI_API, "===========> %s\n", __FUNCTION__);
+
+	pWapiInfo = &padapter->wapiInfo;
+
+	if ((!padapter->WapiSupport) || (!pWapiInfo->bWapiEnable)) {
+		WAPI_TRACE(WAPI_MLME, "<========== %s, WAPI not supported or not enabled!\n", __FUNCTION__);
+		return;
+	}
+
+	/* Sta Info List */
+	while (!list_empty(&(pWapiInfo->wapiSTAUsedList))) {
+		pWapiStaInfo = (PRT_WAPI_STA_INFO)list_entry(pWapiInfo->wapiSTAUsedList.next, RT_WAPI_STA_INFO, list);
+		list_del_init(&pWapiStaInfo->list);
+		memset(pWapiStaInfo->PeerMacAddr, 0, ETH_ALEN);
+		pWapiStaInfo->bSetkeyOk = 0;
+		list_add_tail(&pWapiStaInfo->list, &pWapiInfo->wapiSTAIdleList);
+	}
+
+	/* BKID List */
+	while (!list_empty(&(pWapiInfo->wapiBKIDStoreList))) {
+		pWapiBkid = (PRT_WAPI_BKID)list_entry(pWapiInfo->wapiBKIDStoreList.next, RT_WAPI_BKID, list);
+		list_del_init(&pWapiBkid->list);
+		memset(pWapiBkid->bkid, 0, 16);
+		list_add_tail(&pWapiBkid->list, &pWapiInfo->wapiBKIDIdleList);
+	}
+	WAPI_TRACE(WAPI_API, "<========== %s\n", __FUNCTION__);
+}
+
+void rtw_wapi_clear_cam_entry(_adapter *padapter, u8 *pMacAddr)
+{
+	u8 UcIndex = 0;
+
+	WAPI_TRACE(WAPI_API, "===========> %s\n", __FUNCTION__);
+
+	if ((!padapter->WapiSupport) || (!padapter->wapiInfo.bWapiEnable)) {
+		WAPI_TRACE(WAPI_MLME, "<========== %s, WAPI not supported or not enabled!\n", __FUNCTION__);
+		return;
+	}
+
+	UcIndex = WapiGetEntryForCamClear(padapter, pMacAddr, 0, 0);
+	if (UcIndex != 0xff) {
+		/* CAM_mark_invalid(Adapter, UcIndex); */
+		CAM_empty_entry(padapter, UcIndex);
+	}
+
+	UcIndex = WapiGetEntryForCamClear(padapter, pMacAddr, 1, 0);
+	if (UcIndex != 0xff) {
+		/* CAM_mark_invalid(Adapter, UcIndex); */
+		CAM_empty_entry(padapter, UcIndex);
+	}
+
+	UcIndex = WapiGetEntryForCamClear(padapter, pMacAddr, 0, 1);
+	if (UcIndex != 0xff) {
+		/* CAM_mark_invalid(Adapter, UcIndex); */
+		CAM_empty_entry(padapter, UcIndex);
+	}
+
+	UcIndex = WapiGetEntryForCamClear(padapter, pMacAddr, 1, 1);
+	if (UcIndex != 0xff) {
+		/* CAM_mark_invalid(padapter, UcIndex); */
+		CAM_empty_entry(padapter, UcIndex);
+	}
+
+	WAPI_TRACE(WAPI_API, "<========== %s\n", __FUNCTION__);
+}
+
+void rtw_wapi_clear_all_cam_entry(_adapter *padapter)
+{
+	WAPI_TRACE(WAPI_API, "===========> %s\n", __FUNCTION__);
+
+	if ((!padapter->WapiSupport) || (!padapter->wapiInfo.bWapiEnable)) {
+		WAPI_TRACE(WAPI_MLME, "<========== %s, WAPI not supported or not enabled!\n", __FUNCTION__);
+		return;
+	}
+
+	invalidate_cam_all(padapter); /* is this ok? */
+	WapiResetAllCamEntry(padapter);
+
+	WAPI_TRACE(WAPI_API, "===========> %s\n", __FUNCTION__);
+}
+
+void rtw_wapi_set_key(_adapter *padapter, RT_WAPI_KEY *pWapiKey, RT_WAPI_STA_INFO *pWapiSta, u8 bGroupKey, u8 bUseDefaultKey)
+{
+	PRT_WAPI_T		pWapiInfo =  &padapter->wapiInfo;
+	u8				*pMacAddr = pWapiSta->PeerMacAddr;
+	u32 EntryId = 0;
+	BOOLEAN IsPairWise = false ;
+	u8 EncAlgo;
+
+	WAPI_TRACE(WAPI_API, "===========> %s\n", __FUNCTION__);
+
+	if ((!padapter->WapiSupport) || (!padapter->wapiInfo.bWapiEnable)) {
+		WAPI_TRACE(WAPI_API, "<========== %s, WAPI not supported or not enabled!\n", __FUNCTION__);
+		return;
+	}
+
+	EncAlgo = _SMS4_;
+
+	/* For Tx bc/mc pkt,use defualt key entry */
+	if (bUseDefaultKey) {
+		/* when WAPI update key, keyid will be 0 or 1 by turns. */
+		if (pWapiKey->keyId == 0)
+			EntryId = 0;
+		else
+			EntryId = 2;
+	} else {
+		/* tx/rx unicast pkt, or rx broadcast, find the key entry by peer's MacAddr */
+		EntryId = WapiGetEntryForCamWrite(padapter, pMacAddr, pWapiKey->keyId, bGroupKey);
+	}
+
+	if (EntryId == 0xff) {
+		WAPI_TRACE(WAPI_API, "===>No entry for WAPI setkey! !!\n");
+		return;
+	}
+
+	/* EntryId is also used to diff Sec key and Mic key */
+	/* Sec Key */
+	WapiWriteOneCamEntry(padapter,
+			     pMacAddr,
+			     pWapiKey->keyId, /* keyid */
+			     EntryId,	/* entry */
+			     EncAlgo, /* type */
+			     bGroupKey, /* pairwise or group key */
+			     pWapiKey->dataKey);
+	/* MIC key */
+	WapiWriteOneCamEntry(padapter,
+			     pMacAddr,
+			     pWapiKey->keyId, /* keyid */
+			     EntryId + 1,	/* entry */
+			     EncAlgo, /* type */
+			     bGroupKey, /* pairwise or group key */
+			     pWapiKey->micKey);
+
+	WAPI_TRACE(WAPI_API, "Set Wapi Key :KeyId:%d,EntryId:%d,PairwiseKey:%d.\n", pWapiKey->keyId, EntryId, !bGroupKey);
+	WAPI_TRACE(WAPI_API, "===========> %s\n", __FUNCTION__);
+
+}
+
+#if 0
+/* YJ,test,091013 */
+void wapi_test_set_key(struct _adapter *padapter, u8 *buf)
+{
+	/*Data: keyType(1) + bTxEnable(1) + bAuthenticator(1) + bUpdate(1) + PeerAddr(6) + DataKey(16) + MicKey(16) + KeyId(1)*/
+	PRT_WAPI_T			pWapiInfo = &padapter->wapiInfo;
+	PRT_WAPI_BKID		pWapiBkid;
+	PRT_WAPI_STA_INFO	pWapiSta;
+	u8					data[43];
+	bool					bTxEnable;
+	bool					bUpdate;
+	bool					bAuthenticator;
+	u8					PeerAddr[6];
+	u8					WapiAEPNInitialValueSrc[16] = {0x37, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C} ;
+	u8					WapiASUEPNInitialValueSrc[16] = {0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C} ;
+	u8					WapiAEMultiCastPNInitialValueSrc[16] = {0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C} ;
+
+	WAPI_TRACE(WAPI_INIT, "===========>%s\n", __FUNCTION__);
+
+	if (!padapter->WapiSupport)
+		return;
+
+	copy_from_user(data, buf, 43);
+	bTxEnable = data[1];
+	bAuthenticator = data[2];
+	bUpdate = data[3];
+	memcpy(PeerAddr, data + 4, 6);
+
+	if (data[0] == 0x3) {
+		if (!list_empty(&(pWapiInfo->wapiBKIDIdleList))) {
+			pWapiBkid = (PRT_WAPI_BKID)list_entry(pWapiInfo->wapiBKIDIdleList.next, RT_WAPI_BKID, list);
+			list_del_init(&pWapiBkid->list);
+			memcpy(pWapiBkid->bkid, data + 10, 16);
+			WAPI_DATA(WAPI_INIT, "SetKey - BKID", pWapiBkid->bkid, 16);
+			list_add_tail(&pWapiBkid->list, &pWapiInfo->wapiBKIDStoreList);
+		}
+	} else {
+		list_for_each_entry(pWapiSta, &pWapiInfo->wapiSTAUsedList, list) {
+			if (!memcmp(pWapiSta->PeerMacAddr, PeerAddr, 6)) {
+				pWapiSta->bAuthenticatorInUpdata = false;
+				switch (data[0]) {
+				case 1:              /* usk */
+					if (bAuthenticator) {       /* authenticator */
+						memcpy(pWapiSta->lastTxUnicastPN, WapiAEPNInitialValueSrc, 16);
+						if (!bUpdate) {    /* first */
+							WAPI_TRACE(WAPI_INIT, "AE fisrt set usk\n");
+							pWapiSta->wapiUsk.bSet = true;
+							memcpy(pWapiSta->wapiUsk.dataKey, data + 10, 16);
+							memcpy(pWapiSta->wapiUsk.micKey, data + 26, 16);
+							pWapiSta->wapiUsk.keyId = *(data + 42);
+							pWapiSta->wapiUsk.bTxEnable = true;
+							WAPI_DATA(WAPI_INIT, "SetKey - AE USK Data Key", pWapiSta->wapiUsk.dataKey, 16);
+							WAPI_DATA(WAPI_INIT, "SetKey - AE USK Mic Key", pWapiSta->wapiUsk.micKey, 16);
+						} else {           /* update */
+							WAPI_TRACE(WAPI_INIT, "AE update usk\n");
+							pWapiSta->wapiUskUpdate.bSet = true;
+							pWapiSta->bAuthenticatorInUpdata = true;
+							memcpy(pWapiSta->wapiUskUpdate.dataKey, data + 10, 16);
+							memcpy(pWapiSta->wapiUskUpdate.micKey, data + 26, 16);
+							memcpy(pWapiSta->lastRxUnicastPNBEQueue, WapiASUEPNInitialValueSrc, 16);
+							memcpy(pWapiSta->lastRxUnicastPNBKQueue, WapiASUEPNInitialValueSrc, 16);
+							memcpy(pWapiSta->lastRxUnicastPNVIQueue, WapiASUEPNInitialValueSrc, 16);
+							memcpy(pWapiSta->lastRxUnicastPNVOQueue, WapiASUEPNInitialValueSrc, 16);
+							memcpy(pWapiSta->lastRxUnicastPN, WapiASUEPNInitialValueSrc, 16);
+							pWapiSta->wapiUskUpdate.keyId = *(data + 42);
+							pWapiSta->wapiUskUpdate.bTxEnable = true;
+						}
+					} else {
+						if (!bUpdate) {
+							WAPI_TRACE(WAPI_INIT, "ASUE fisrt set usk\n");
+							if (bTxEnable) {
+								pWapiSta->wapiUsk.bTxEnable = true;
+								memcpy(pWapiSta->lastTxUnicastPN, WapiASUEPNInitialValueSrc, 16);
+							} else {
+								pWapiSta->wapiUsk.bSet = true;
+								memcpy(pWapiSta->wapiUsk.dataKey, data + 10, 16);
+								memcpy(pWapiSta->wapiUsk.micKey, data + 26, 16);
+								pWapiSta->wapiUsk.keyId = *(data + 42);
+								pWapiSta->wapiUsk.bTxEnable = false;
+							}
+						} else {
+							WAPI_TRACE(WAPI_INIT, "ASUE update usk\n");
+							if (bTxEnable) {
+								pWapiSta->wapiUskUpdate.bTxEnable = true;
+								if (pWapiSta->wapiUskUpdate.bSet) {
+									memcpy(pWapiSta->wapiUsk.dataKey, pWapiSta->wapiUskUpdate.dataKey, 16);
+									memcpy(pWapiSta->wapiUsk.micKey, pWapiSta->wapiUskUpdate.micKey, 16);
+									pWapiSta->wapiUsk.keyId = pWapiSta->wapiUskUpdate.keyId;
+									memcpy(pWapiSta->lastRxUnicastPNBEQueue, WapiASUEPNInitialValueSrc, 16);
+									memcpy(pWapiSta->lastRxUnicastPNBKQueue, WapiASUEPNInitialValueSrc, 16);
+									memcpy(pWapiSta->lastRxUnicastPNVIQueue, WapiASUEPNInitialValueSrc, 16);
+									memcpy(pWapiSta->lastRxUnicastPNVOQueue, WapiASUEPNInitialValueSrc, 16);
+									memcpy(pWapiSta->lastRxUnicastPN, WapiASUEPNInitialValueSrc, 16);
+									pWapiSta->wapiUskUpdate.bTxEnable = false;
+									pWapiSta->wapiUskUpdate.bSet = false;
+								}
+								memcpy(pWapiSta->lastTxUnicastPN, WapiASUEPNInitialValueSrc, 16);
+							} else {
+								pWapiSta->wapiUskUpdate.bSet = true;
+								memcpy(pWapiSta->wapiUskUpdate.dataKey, data + 10, 16);
+								memcpy(pWapiSta->wapiUskUpdate.micKey, data + 26, 16);
+								pWapiSta->wapiUskUpdate.keyId = *(data + 42);
+								pWapiSta->wapiUskUpdate.bTxEnable = false;
+							}
+						}
+					}
+					break;
+				case 2:		/* msk */
+					if (bAuthenticator) {        /* authenticator */
+						pWapiInfo->wapiTxMsk.bSet = true;
+						memcpy(pWapiInfo->wapiTxMsk.dataKey, data + 10, 16);
+						memcpy(pWapiInfo->wapiTxMsk.micKey, data + 26, 16);
+						pWapiInfo->wapiTxMsk.keyId = *(data + 42);
+						pWapiInfo->wapiTxMsk.bTxEnable = true;
+						memcpy(pWapiInfo->lastTxMulticastPN, WapiAEMultiCastPNInitialValueSrc, 16);
+
+						if (!bUpdate) {    /* first */
+							WAPI_TRACE(WAPI_INIT, "AE fisrt set msk\n");
+							if (!pWapiSta->bSetkeyOk)
+								pWapiSta->bSetkeyOk = true;
+							pWapiInfo->bFirstAuthentiateInProgress = false;
+						} else                /* update */
+							WAPI_TRACE(WAPI_INIT, "AE update msk\n");
+
+						WAPI_DATA(WAPI_INIT, "SetKey - AE MSK Data Key", pWapiInfo->wapiTxMsk.dataKey, 16);
+						WAPI_DATA(WAPI_INIT, "SetKey - AE MSK Mic Key", pWapiInfo->wapiTxMsk.micKey, 16);
+					} else {
+						if (!bUpdate) {
+							WAPI_TRACE(WAPI_INIT, "ASUE fisrt set msk\n");
+							pWapiSta->wapiMsk.bSet = true;
+							memcpy(pWapiSta->wapiMsk.dataKey, data + 10, 16);
+							memcpy(pWapiSta->wapiMsk.micKey, data + 26, 16);
+							pWapiSta->wapiMsk.keyId = *(data + 42);
+							pWapiSta->wapiMsk.bTxEnable = false;
+							if (!pWapiSta->bSetkeyOk)
+								pWapiSta->bSetkeyOk = true;
+							pWapiInfo->bFirstAuthentiateInProgress = false;
+							WAPI_DATA(WAPI_INIT, "SetKey - ASUE MSK Data Key", pWapiSta->wapiMsk.dataKey, 16);
+							WAPI_DATA(WAPI_INIT, "SetKey - ASUE MSK Mic Key", pWapiSta->wapiMsk.micKey, 16);
+						} else {
+							WAPI_TRACE(WAPI_INIT, "ASUE update msk\n");
+							pWapiSta->wapiMskUpdate.bSet = true;
+							memcpy(pWapiSta->wapiMskUpdate.dataKey, data + 10, 16);
+							memcpy(pWapiSta->wapiMskUpdate.micKey, data + 26, 16);
+							pWapiSta->wapiMskUpdate.keyId = *(data + 42);
+							pWapiSta->wapiMskUpdate.bTxEnable = false;
+						}
+					}
+					break;
+				default:
+					WAPI_TRACE(WAPI_ERR, "Unknown Flag\n");
+					break;
+				}
+			}
+		}
+	}
+	WAPI_TRACE(WAPI_INIT, "<===========%s\n", __FUNCTION__);
+}
+
+
+void wapi_test_init(struct _adapter *padapter)
+{
+	u8 keybuf[100];
+	u8 mac_addr[ETH_ALEN] = {0x00, 0xe0, 0x4c, 0x72, 0x04, 0x70};
+	u8 UskDataKey[16] = {0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f};
+	u8 UskMicKey[16] = {0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 0x1e, 0x1f};
+	u8 UskId = 0;
+	u8 MskDataKey[16] = {0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27, 0x28, 0x29, 0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f};
+	u8 MskMicKey[16] = {0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x3a, 0x3b, 0x3c, 0x3d, 0x3e, 0x3f};
+	u8 MskId = 0;
+
+	WAPI_TRACE(WAPI_INIT, "===========>%s\n", __FUNCTION__);
+
+	/* Enable Wapi */
+	WAPI_TRACE(WAPI_INIT, "%s: Enable wapi!!!!\n", __FUNCTION__);
+	padapter->wapiInfo.bWapiEnable = true;
+	padapter->pairwise_key_type = KEY_TYPE_SMS4;
+	ieee->group_key_type = KEY_TYPE_SMS4;
+	padapter->wapiInfo.extra_prefix_len = WAPI_EXT_LEN;
+	padapter->wapiInfo.extra_postfix_len = SMS4_MIC_LEN;
+
+	/* set usk */
+	WAPI_TRACE(WAPI_INIT, "%s: Set USK!!!!\n", __FUNCTION__);
+	memset(keybuf, 0, 100);
+	keybuf[0] = 1;                           /* set usk */
+	keybuf[1] = 1; 				/* enable tx */
+	keybuf[2] = 1; 				/* AE */
+	keybuf[3] = 0; 				/* not update */
+
+	memcpy(keybuf + 4, mac_addr, ETH_ALEN);
+	memcpy(keybuf + 10, UskDataKey, 16);
+	memcpy(keybuf + 26, UskMicKey, 16);
+	keybuf[42] = UskId;
+	wapi_test_set_key(padapter, keybuf);
+
+	memset(keybuf, 0, 100);
+	keybuf[0] = 1;                           /* set usk */
+	keybuf[1] = 1; 				/* enable tx */
+	keybuf[2] = 0; 				/* AE */
+	keybuf[3] = 0; 				/* not update */
+
+	memcpy(keybuf + 4, mac_addr, ETH_ALEN);
+	memcpy(keybuf + 10, UskDataKey, 16);
+	memcpy(keybuf + 26, UskMicKey, 16);
+	keybuf[42] = UskId;
+	wapi_test_set_key(padapter, keybuf);
+
+	/* set msk */
+	WAPI_TRACE(WAPI_INIT, "%s: Set MSK!!!!\n", __FUNCTION__);
+	memset(keybuf, 0, 100);
+	keybuf[0] = 2;                                /* set msk */
+	keybuf[1] = 1;                               /* Enable TX */
+	keybuf[2] = 1; 				/* AE */
+	keybuf[3] = 0;                              /* not update */
+	memcpy(keybuf + 4, mac_addr, ETH_ALEN);
+	memcpy(keybuf + 10, MskDataKey, 16);
+	memcpy(keybuf + 26, MskMicKey, 16);
+	keybuf[42] = MskId;
+	wapi_test_set_key(padapter, keybuf);
+
+	memset(keybuf, 0, 100);
+	keybuf[0] = 2;                                /* set msk */
+	keybuf[1] = 1;                               /* Enable TX */
+	keybuf[2] = 0; 				/* AE */
+	keybuf[3] = 0;                              /* not update */
+	memcpy(keybuf + 4, mac_addr, ETH_ALEN);
+	memcpy(keybuf + 10, MskDataKey, 16);
+	memcpy(keybuf + 26, MskMicKey, 16);
+	keybuf[42] = MskId;
+	wapi_test_set_key(padapter, keybuf);
+	WAPI_TRACE(WAPI_INIT, "<===========%s\n", __FUNCTION__);
+}
+#endif
+
+void rtw_wapi_get_iv(_adapter *padapter, u8 *pRA, u8 *IV)
+{
+	PWLAN_HEADER_WAPI_EXTENSION pWapiExt = NULL;
+	PRT_WAPI_T         pWapiInfo = &padapter->wapiInfo;
+	bool	bPNOverflow = false;
+	bool	bFindMatchPeer = false;
+	PRT_WAPI_STA_INFO  pWapiSta = NULL;
+
+	pWapiExt = (PWLAN_HEADER_WAPI_EXTENSION)IV;
+
+	WAPI_DATA(WAPI_RX, "wapi_get_iv: pra", pRA, 6);
+
+	if (IS_MCAST(pRA)) {
+		if (!pWapiInfo->wapiTxMsk.bTxEnable) {
+			WAPI_TRACE(WAPI_ERR, "%s: bTxEnable = 0!!\n", __FUNCTION__);
+			return;
+		}
+
+		if (pWapiInfo->wapiTxMsk.keyId <= 1) {
+			pWapiExt->KeyIdx = pWapiInfo->wapiTxMsk.keyId;
+			pWapiExt->Reserved = 0;
+			bPNOverflow = WapiIncreasePN(pWapiInfo->lastTxMulticastPN, 1);
+			memcpy(pWapiExt->PN, pWapiInfo->lastTxMulticastPN, 16);
+		}
+	} else {
+		if (list_empty(&pWapiInfo->wapiSTAUsedList)) {
+			WAPI_TRACE(WAPI_RX, "rtw_wapi_get_iv: list is empty\n");
+			_rtw_memset(IV, 10, 18);
+			return;
+		} else {
+			list_for_each_entry(pWapiSta, &pWapiInfo->wapiSTAUsedList, list) {
+				WAPI_DATA(WAPI_RX, "rtw_wapi_get_iv: peermacaddr ", pWapiSta->PeerMacAddr, 6);
+				if (_rtw_memcmp((u8 *)pWapiSta->PeerMacAddr, pRA, 6) == _TRUE) {
+					bFindMatchPeer = true;
+					break;
+				}
+			}
+
+			WAPI_TRACE(WAPI_RX, "bFindMatchPeer: %d\n", bFindMatchPeer);
+			WAPI_DATA(WAPI_RX, "Addr", pRA, 6);
+
+			if (bFindMatchPeer) {
+				if ((!pWapiSta->wapiUskUpdate.bTxEnable) && (!pWapiSta->wapiUsk.bTxEnable))
+					return;
+
+				if (pWapiSta->wapiUsk.keyId <= 1) {
+					if (pWapiSta->wapiUskUpdate.bTxEnable)
+						pWapiExt->KeyIdx = pWapiSta->wapiUskUpdate.keyId;
+					else
+						pWapiExt->KeyIdx = pWapiSta->wapiUsk.keyId;
+
+					pWapiExt->Reserved = 0;
+					bPNOverflow = WapiIncreasePN(pWapiSta->lastTxUnicastPN, 2);
+					_rtw_memcpy(pWapiExt->PN, pWapiSta->lastTxUnicastPN, 16);
+
+				}
+			}
+		}
+
+	}
+
+}
+
+bool rtw_wapi_drop_for_key_absent(_adapter *padapter, u8 *pRA)
+{
+	PRT_WAPI_T         pWapiInfo = &padapter->wapiInfo;
+	bool				bFindMatchPeer = false;
+	bool				bDrop = false;
+	PRT_WAPI_STA_INFO  pWapiSta = NULL;
+	struct security_priv		*psecuritypriv = &padapter->securitypriv;
+
+	WAPI_DATA(WAPI_RX, "rtw_wapi_drop_for_key_absent: ra ", pRA, 6);
+
+	if (psecuritypriv->dot11PrivacyAlgrthm == _SMS4_) {
+		if ((!padapter->WapiSupport) || (!pWapiInfo->bWapiEnable))
+			return true;
+
+		if (IS_MCAST(pRA)) {
+			if (!pWapiInfo->wapiTxMsk.bTxEnable) {
+				bDrop = true;
+				WAPI_TRACE(WAPI_RX, "rtw_wapi_drop_for_key_absent: multicast key is absent\n");
+				return bDrop;
+			}
+		} else {
+			if (!list_empty(&pWapiInfo->wapiSTAUsedList)) {
+				list_for_each_entry(pWapiSta, &pWapiInfo->wapiSTAUsedList, list) {
+					WAPI_DATA(WAPI_RX, "rtw_wapi_drop_for_key_absent: pWapiSta->PeerMacAddr ", pWapiSta->PeerMacAddr, 6);
+					if (_rtw_memcmp(pRA, pWapiSta->PeerMacAddr, 6) == _TRUE) {
+						bFindMatchPeer = true;
+						break;
+					}
+				}
+				if (bFindMatchPeer)	{
+					if (!pWapiSta->wapiUsk.bTxEnable) {
+						bDrop = true;
+						WAPI_TRACE(WAPI_RX, "rtw_wapi_drop_for_key_absent: unicast key is absent\n");
+						return bDrop;
+					}
+				} else {
+					bDrop = true;
+					WAPI_TRACE(WAPI_RX, "rtw_wapi_drop_for_key_absent: no peer find\n");
+					return bDrop;
+				}
+
+			} else {
+				bDrop = true;
+				WAPI_TRACE(WAPI_RX, "rtw_wapi_drop_for_key_absent: no sta  exist\n");
+				return bDrop;
+			}
+		}
+	} else
+		return bDrop;
+
+	return bDrop;
+}
+
+void rtw_wapi_set_set_encryption(_adapter *padapter, struct ieee_param *param)
+{
+	struct security_priv *psecuritypriv = &padapter->securitypriv;
+	struct mlme_priv	*pmlmepriv = &padapter->mlmepriv;
+	PRT_WAPI_T			pWapiInfo = &padapter->wapiInfo;
+	PRT_WAPI_STA_INFO	pWapiSta;
+	u8					WapiASUEPNInitialValueSrc[16] = {0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C} ;
+	u8					WapiAEPNInitialValueSrc[16] = {0x37, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C} ;
+	u8					WapiAEMultiCastPNInitialValueSrc[16] = {0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C} ;
+
+	if (param->u.crypt.set_tx == 1) {
+		list_for_each_entry(pWapiSta, &pWapiInfo->wapiSTAUsedList, list) {
+			if (_rtw_memcmp(pWapiSta->PeerMacAddr, param->sta_addr, 6)) {
+				_rtw_memcpy(pWapiSta->lastTxUnicastPN, WapiASUEPNInitialValueSrc, 16);
+
+				pWapiSta->wapiUsk.bSet = true;
+				_rtw_memcpy(pWapiSta->wapiUsk.dataKey, param->u.crypt.key, 16);
+				_rtw_memcpy(pWapiSta->wapiUsk.micKey, param->u.crypt.key + 16, 16);
+				pWapiSta->wapiUsk.keyId = param->u.crypt.idx ;
+				pWapiSta->wapiUsk.bTxEnable = true;
+
+				_rtw_memcpy(pWapiSta->lastRxUnicastPNBEQueue, WapiAEPNInitialValueSrc, 16);
+				_rtw_memcpy(pWapiSta->lastRxUnicastPNBKQueue, WapiAEPNInitialValueSrc, 16);
+				_rtw_memcpy(pWapiSta->lastRxUnicastPNVIQueue, WapiAEPNInitialValueSrc, 16);
+				_rtw_memcpy(pWapiSta->lastRxUnicastPNVOQueue, WapiAEPNInitialValueSrc, 16);
+				_rtw_memcpy(pWapiSta->lastRxUnicastPN, WapiAEPNInitialValueSrc, 16);
+				pWapiSta->wapiUskUpdate.bTxEnable = false;
+				pWapiSta->wapiUskUpdate.bSet = false;
+
+				if (psecuritypriv->sw_encrypt == false || psecuritypriv->sw_decrypt == false) {
+					/* set unicast key for ASUE */
+					rtw_wapi_set_key(padapter, &pWapiSta->wapiUsk, pWapiSta, false, false);
+				}
+			}
+		}
+	} else {
+		list_for_each_entry(pWapiSta, &pWapiInfo->wapiSTAUsedList, list) {
+			if (_rtw_memcmp(pWapiSta->PeerMacAddr, get_bssid(pmlmepriv), 6)) {
+				pWapiSta->wapiMsk.bSet = true;
+				_rtw_memcpy(pWapiSta->wapiMsk.dataKey, param->u.crypt.key, 16);
+				_rtw_memcpy(pWapiSta->wapiMsk.micKey, param->u.crypt.key + 16, 16);
+				pWapiSta->wapiMsk.keyId = param->u.crypt.idx ;
+				pWapiSta->wapiMsk.bTxEnable = false;
+				if (!pWapiSta->bSetkeyOk)
+					pWapiSta->bSetkeyOk = true;
+				pWapiSta->bAuthenticateInProgress = false;
+
+				_rtw_memcpy(pWapiSta->lastRxMulticastPN, WapiAEMultiCastPNInitialValueSrc, 16);
+
+				if (psecuritypriv->sw_decrypt == false) {
+					/* set rx broadcast key for ASUE */
+					rtw_wapi_set_key(padapter, &pWapiSta->wapiMsk, pWapiSta, true, false);
+				}
+			}
+		}
+	}
+}
+#endif
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/core/rtw_wapi_sms4.c linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/core/rtw_wapi_sms4.c
--- linux-5.6.3/3rdparty/rtl8821ce/core/rtw_wapi_sms4.c	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/core/rtw_wapi_sms4.c	2020-04-10 16:35:06.779658341 +0300
@@ -0,0 +1,922 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2016 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#ifdef CONFIG_WAPI_SUPPORT
+
+#include <linux/unistd.h>
+#include <linux/etherdevice.h>
+#include <drv_types.h>
+#include <rtw_wapi.h>
+
+
+#ifdef CONFIG_WAPI_SW_SMS4
+
+#define WAPI_LITTLE_ENDIAN
+/* #define BIG_ENDIAN */
+#define ENCRYPT  0
+#define DECRYPT  1
+
+
+/**********************************************************
+ **********************************************************/
+const u8 Sbox[256] = {
+	0xd6, 0x90, 0xe9, 0xfe, 0xcc, 0xe1, 0x3d, 0xb7, 0x16, 0xb6, 0x14, 0xc2, 0x28, 0xfb, 0x2c, 0x05,
+	0x2b, 0x67, 0x9a, 0x76, 0x2a, 0xbe, 0x04, 0xc3, 0xaa, 0x44, 0x13, 0x26, 0x49, 0x86, 0x06, 0x99,
+	0x9c, 0x42, 0x50, 0xf4, 0x91, 0xef, 0x98, 0x7a, 0x33, 0x54, 0x0b, 0x43, 0xed, 0xcf, 0xac, 0x62,
+	0xe4, 0xb3, 0x1c, 0xa9, 0xc9, 0x08, 0xe8, 0x95, 0x80, 0xdf, 0x94, 0xfa, 0x75, 0x8f, 0x3f, 0xa6,
+	0x47, 0x07, 0xa7, 0xfc, 0xf3, 0x73, 0x17, 0xba, 0x83, 0x59, 0x3c, 0x19, 0xe6, 0x85, 0x4f, 0xa8,
+	0x68, 0x6b, 0x81, 0xb2, 0x71, 0x64, 0xda, 0x8b, 0xf8, 0xeb, 0x0f, 0x4b, 0x70, 0x56, 0x9d, 0x35,
+	0x1e, 0x24, 0x0e, 0x5e, 0x63, 0x58, 0xd1, 0xa2, 0x25, 0x22, 0x7c, 0x3b, 0x01, 0x21, 0x78, 0x87,
+	0xd4, 0x00, 0x46, 0x57, 0x9f, 0xd3, 0x27, 0x52, 0x4c, 0x36, 0x02, 0xe7, 0xa0, 0xc4, 0xc8, 0x9e,
+	0xea, 0xbf, 0x8a, 0xd2, 0x40, 0xc7, 0x38, 0xb5, 0xa3, 0xf7, 0xf2, 0xce, 0xf9, 0x61, 0x15, 0xa1,
+	0xe0, 0xae, 0x5d, 0xa4, 0x9b, 0x34, 0x1a, 0x55, 0xad, 0x93, 0x32, 0x30, 0xf5, 0x8c, 0xb1, 0xe3,
+	0x1d, 0xf6, 0xe2, 0x2e, 0x82, 0x66, 0xca, 0x60, 0xc0, 0x29, 0x23, 0xab, 0x0d, 0x53, 0x4e, 0x6f,
+	0xd5, 0xdb, 0x37, 0x45, 0xde, 0xfd, 0x8e, 0x2f, 0x03, 0xff, 0x6a, 0x72, 0x6d, 0x6c, 0x5b, 0x51,
+	0x8d, 0x1b, 0xaf, 0x92, 0xbb, 0xdd, 0xbc, 0x7f, 0x11, 0xd9, 0x5c, 0x41, 0x1f, 0x10, 0x5a, 0xd8,
+	0x0a, 0xc1, 0x31, 0x88, 0xa5, 0xcd, 0x7b, 0xbd, 0x2d, 0x74, 0xd0, 0x12, 0xb8, 0xe5, 0xb4, 0xb0,
+	0x89, 0x69, 0x97, 0x4a, 0x0c, 0x96, 0x77, 0x7e, 0x65, 0xb9, 0xf1, 0x09, 0xc5, 0x6e, 0xc6, 0x84,
+	0x18, 0xf0, 0x7d, 0xec, 0x3a, 0xdc, 0x4d, 0x20, 0x79, 0xee, 0x5f, 0x3e, 0xd7, 0xcb, 0x39, 0x48
+};
+
+const u32 CK[32] = {
+	0x00070e15, 0x1c232a31, 0x383f464d, 0x545b6269,
+	0x70777e85, 0x8c939aa1, 0xa8afb6bd, 0xc4cbd2d9,
+	0xe0e7eef5, 0xfc030a11, 0x181f262d, 0x343b4249,
+	0x50575e65, 0x6c737a81, 0x888f969d, 0xa4abb2b9,
+	0xc0c7ced5, 0xdce3eaf1, 0xf8ff060d, 0x141b2229,
+	0x30373e45, 0x4c535a61, 0x686f767d, 0x848b9299,
+	0xa0a7aeb5, 0xbcc3cad1, 0xd8dfe6ed, 0xf4fb0209,
+	0x10171e25, 0x2c333a41, 0x484f565d, 0x646b7279
+};
+
+#define Rotl(_x, _y) (((_x) << (_y)) | ((_x) >> (32 - (_y))))
+
+#define ByteSub(_A) (Sbox[(_A) >> 24 & 0xFF] << 24 | \
+		     Sbox[(_A) >> 16 & 0xFF] << 16 | \
+		     Sbox[(_A) >>  8 & 0xFF] <<  8 | \
+		     Sbox[(_A) & 0xFF])
+
+#define L1(_B) ((_B) ^ Rotl(_B, 2) ^ Rotl(_B, 10) ^ Rotl(_B, 18) ^ Rotl(_B, 24))
+#define L2(_B) ((_B) ^ Rotl(_B, 13) ^ Rotl(_B, 23))
+
+static void
+xor_block(void *dst, void *src1, void *src2)
+/* 128-bit xor: *dst = *src1 xor *src2. Pointers must be 32-bit aligned */
+{
+	((u32 *)dst)[0] = ((u32 *)src1)[0] ^ ((u32 *)src2)[0];
+	((u32 *)dst)[1] = ((u32 *)src1)[1] ^ ((u32 *)src2)[1];
+	((u32 *)dst)[2] = ((u32 *)src1)[2] ^ ((u32 *)src2)[2];
+	((u32 *)dst)[3] = ((u32 *)src1)[3] ^ ((u32 *)src2)[3];
+}
+
+
+void SMS4Crypt(u8 *Input, u8 *Output, u32 *rk)
+{
+	u32 r, mid, x0, x1, x2, x3, *p;
+	p = (u32 *)Input;
+	x0 = p[0];
+	x1 = p[1];
+	x2 = p[2];
+	x3 = p[3];
+#ifdef WAPI_LITTLE_ENDIAN
+	x0 = Rotl(x0, 16);
+	x0 = ((x0 & 0x00FF00FF) << 8) | ((x0 & 0xFF00FF00) >> 8);
+	x1 = Rotl(x1, 16);
+	x1 = ((x1 & 0x00FF00FF) << 8) | ((x1 & 0xFF00FF00) >> 8);
+	x2 = Rotl(x2, 16);
+	x2 = ((x2 & 0x00FF00FF) << 8) | ((x2 & 0xFF00FF00) >> 8);
+	x3 = Rotl(x3, 16);
+	x3 = ((x3 & 0x00FF00FF) << 8) | ((x3 & 0xFF00FF00) >> 8);
+#endif
+	for (r = 0; r < 32; r += 4) {
+		mid = x1 ^ x2 ^ x3 ^ rk[r + 0];
+		mid = ByteSub(mid);
+		x0 ^= L1(mid);
+		mid = x2 ^ x3 ^ x0 ^ rk[r + 1];
+		mid = ByteSub(mid);
+		x1 ^= L1(mid);
+		mid = x3 ^ x0 ^ x1 ^ rk[r + 2];
+		mid = ByteSub(mid);
+		x2 ^= L1(mid);
+		mid = x0 ^ x1 ^ x2 ^ rk[r + 3];
+		mid = ByteSub(mid);
+		x3 ^= L1(mid);
+	}
+#ifdef WAPI_LITTLE_ENDIAN
+	x0 = Rotl(x0, 16);
+	x0 = ((x0 & 0x00FF00FF) << 8) | ((x0 & 0xFF00FF00) >> 8);
+	x1 = Rotl(x1, 16);
+	x1 = ((x1 & 0x00FF00FF) << 8) | ((x1 & 0xFF00FF00) >> 8);
+	x2 = Rotl(x2, 16);
+	x2 = ((x2 & 0x00FF00FF) << 8) | ((x2 & 0xFF00FF00) >> 8);
+	x3 = Rotl(x3, 16);
+	x3 = ((x3 & 0x00FF00FF) << 8) | ((x3 & 0xFF00FF00) >> 8);
+#endif
+	p = (u32 *)Output;
+	p[0] = x3;
+	p[1] = x2;
+	p[2] = x1;
+	p[3] = x0;
+}
+
+
+
+void SMS4KeyExt(u8 *Key, u32 *rk, u32 CryptFlag)
+{
+	u32 r, mid, x0, x1, x2, x3, *p;
+
+	p = (u32 *)Key;
+	x0 = p[0];
+	x1 = p[1];
+	x2 = p[2];
+	x3 = p[3];
+#ifdef WAPI_LITTLE_ENDIAN
+	x0 = Rotl(x0, 16);
+	x0 = ((x0 & 0xFF00FF) << 8) | ((x0 & 0xFF00FF00) >> 8);
+	x1 = Rotl(x1, 16);
+	x1 = ((x1 & 0xFF00FF) << 8) | ((x1 & 0xFF00FF00) >> 8);
+	x2 = Rotl(x2, 16);
+	x2 = ((x2 & 0xFF00FF) << 8) | ((x2 & 0xFF00FF00) >> 8);
+	x3 = Rotl(x3, 16);
+	x3 = ((x3 & 0xFF00FF) << 8) | ((x3 & 0xFF00FF00) >> 8);
+#endif
+
+	x0 ^= 0xa3b1bac6;
+	x1 ^= 0x56aa3350;
+	x2 ^= 0x677d9197;
+	x3 ^= 0xb27022dc;
+	for (r = 0; r < 32; r += 4) {
+		mid = x1 ^ x2 ^ x3 ^ CK[r + 0];
+		mid = ByteSub(mid);
+		rk[r + 0] = x0 ^= L2(mid);
+		mid = x2 ^ x3 ^ x0 ^ CK[r + 1];
+		mid = ByteSub(mid);
+		rk[r + 1] = x1 ^= L2(mid);
+		mid = x3 ^ x0 ^ x1 ^ CK[r + 2];
+		mid = ByteSub(mid);
+		rk[r + 2] = x2 ^= L2(mid);
+		mid = x0 ^ x1 ^ x2 ^ CK[r + 3];
+		mid = ByteSub(mid);
+		rk[r + 3] = x3 ^= L2(mid);
+	}
+	if (CryptFlag == DECRYPT) {
+		for (r = 0; r < 16; r++)
+			mid = rk[r], rk[r] = rk[31 - r], rk[31 - r] = mid;
+	}
+}
+
+
+void WapiSMS4Cryption(u8 *Key, u8 *IV, u8 *Input, u16 InputLength,
+		      u8 *Output, u16 *OutputLength, u32 CryptFlag)
+{
+	u32 blockNum, i, j, rk[32];
+	u16 remainder;
+	u8 blockIn[16], blockOut[16], tempIV[16], k;
+
+	*OutputLength = 0;
+	remainder = InputLength & 0x0F;
+	blockNum = InputLength >> 4;
+	if (remainder != 0)
+		blockNum++;
+	else
+		remainder = 16;
+
+	for (k = 0; k < 16; k++)
+		tempIV[k] = IV[15 - k];
+
+	memcpy(blockIn, tempIV, 16);
+
+	SMS4KeyExt((u8 *)Key, rk, CryptFlag);
+
+	for (i = 0; i < blockNum - 1; i++) {
+		SMS4Crypt((u8 *)blockIn, blockOut, rk);
+		xor_block(&Output[i * 16], &Input[i * 16], blockOut);
+		memcpy(blockIn, blockOut, 16);
+	}
+
+	*OutputLength = i * 16;
+
+	SMS4Crypt((u8 *)blockIn, blockOut, rk);
+
+	for (j = 0; j < remainder; j++)
+		Output[i * 16 + j] = Input[i * 16 + j] ^ blockOut[j];
+	*OutputLength += remainder;
+
+}
+
+void WapiSMS4Encryption(u8 *Key, u8 *IV, u8 *Input, u16 InputLength,
+			u8 *Output, u16 *OutputLength)
+{
+
+	WapiSMS4Cryption(Key, IV, Input, InputLength, Output, OutputLength, ENCRYPT);
+}
+
+void WapiSMS4Decryption(u8 *Key, u8 *IV, u8 *Input, u16 InputLength,
+			u8 *Output, u16 *OutputLength)
+{
+	/* OFB mode: is also ENCRYPT flag */
+	WapiSMS4Cryption(Key, IV, Input, InputLength, Output, OutputLength, ENCRYPT);
+}
+
+void WapiSMS4CalculateMic(u8 *Key, u8 *IV, u8 *Input1, u8 Input1Length,
+		  u8 *Input2, u16 Input2Length, u8 *Output, u8 *OutputLength)
+{
+	u32 blockNum, i, remainder, rk[32];
+	u8 BlockIn[16], BlockOut[16], TempBlock[16], tempIV[16], k;
+
+	*OutputLength = 0;
+	remainder = Input1Length & 0x0F;
+	blockNum = Input1Length >> 4;
+
+	for (k = 0; k < 16; k++)
+		tempIV[k] = IV[15 - k];
+
+	memcpy(BlockIn, tempIV, 16);
+
+	SMS4KeyExt((u8 *)Key, rk, ENCRYPT);
+
+	SMS4Crypt((u8 *)BlockIn, BlockOut, rk);
+
+	for (i = 0; i < blockNum; i++) {
+		xor_block(BlockIn, (Input1 + i * 16), BlockOut);
+		SMS4Crypt((u8 *)BlockIn, BlockOut, rk);
+	}
+
+	if (remainder != 0) {
+		memset(TempBlock, 0, 16);
+		memcpy(TempBlock, (Input1 + blockNum * 16), remainder);
+
+		xor_block(BlockIn, TempBlock, BlockOut);
+		SMS4Crypt((u8 *)BlockIn, BlockOut, rk);
+	}
+
+	remainder = Input2Length & 0x0F;
+	blockNum = Input2Length >> 4;
+
+	for (i = 0; i < blockNum; i++) {
+		xor_block(BlockIn, (Input2 + i * 16), BlockOut);
+		SMS4Crypt((u8 *)BlockIn, BlockOut, rk);
+	}
+
+	if (remainder != 0) {
+		memset(TempBlock, 0, 16);
+		memcpy(TempBlock, (Input2 + blockNum * 16), remainder);
+
+		xor_block(BlockIn, TempBlock, BlockOut);
+		SMS4Crypt((u8 *)BlockIn, BlockOut, rk);
+	}
+
+	memcpy(Output, BlockOut, 16);
+	*OutputLength = 16;
+}
+
+void SecCalculateMicSMS4(
+	u8		KeyIdx,
+	u8        *MicKey,
+	u8        *pHeader,
+	u8        *pData,
+	u16       DataLen,
+	u8        *MicBuffer
+)
+{
+#if 0
+	struct ieee80211_hdr_3addr_qos *header;
+	u8 TempBuf[34], TempLen = 32, MicLen, QosOffset, *IV;
+	u16 *pTemp, fc;
+
+	WAPI_TRACE(WAPI_TX | WAPI_RX, "=========>%s\n", __FUNCTION__);
+
+	header = (struct ieee80211_hdr_3addr_qos *)pHeader;
+	memset(TempBuf, 0, 34);
+	memcpy(TempBuf, pHeader, 2); /* FrameCtrl */
+	pTemp = (u16 *)TempBuf;
+	*pTemp &= 0xc78f;       /* bit4,5,6,11,12,13 */
+
+	memcpy((TempBuf + 2), (pHeader + 4), 12); /* Addr1, Addr2 */
+	memcpy((TempBuf + 14), (pHeader + 22), 2); /* SeqCtrl */
+	pTemp = (u16 *)(TempBuf + 14);
+	*pTemp &= 0x000f;
+
+	memcpy((TempBuf + 16), (pHeader + 16), 6); /* Addr3 */
+
+	fc = le16_to_cpu(header->frame_ctl);
+
+
+
+	if (GetFrDs((u16 *)&fc) && GetToDs((u16 *)&fc)) {
+		memcpy((TempBuf + 22), (pHeader + 24), 6);
+		QosOffset = 30;
+	} else {
+		memset((TempBuf + 22), 0, 6);
+		QosOffset = 24;
+	}
+
+	if ((fc & 0x0088) == 0x0088) {
+		memcpy((TempBuf + 28), (pHeader + QosOffset), 2);
+		TempLen += 2;
+		/* IV = pHeader + QosOffset + 2 + SNAP_SIZE + sizeof(u16) + 2; */
+		IV = pHeader + QosOffset + 2 + 2;
+	} else {
+		IV = pHeader + QosOffset + 2;
+		/* IV = pHeader + QosOffset + SNAP_SIZE + sizeof(u16) + 2; */
+	}
+
+	TempBuf[TempLen - 1] = (u8)(DataLen & 0xff);
+	TempBuf[TempLen - 2] = (u8)((DataLen & 0xff00) >> 8);
+	TempBuf[TempLen - 4] = KeyIdx;
+
+	WAPI_DATA(WAPI_TX, "CalculateMic - KEY", MicKey, 16);
+	WAPI_DATA(WAPI_TX, "CalculateMic - IV", IV, 16);
+	WAPI_DATA(WAPI_TX, "CalculateMic - TempBuf", TempBuf, TempLen);
+	WAPI_DATA(WAPI_TX, "CalculateMic - pData", pData, DataLen);
+
+	WapiSMS4CalculateMic(MicKey, IV, TempBuf, TempLen,
+			     pData, DataLen, MicBuffer, &MicLen);
+
+	if (MicLen != 16)
+		WAPI_TRACE(WAPI_ERR, "%s: MIC Length Error!!\n", __FUNCTION__);
+
+	WAPI_TRACE(WAPI_TX | WAPI_RX, "<=========%s\n", __FUNCTION__);
+#endif
+}
+
+/* AddCount: 1 or 2.
+ *  If overflow, return 1,
+ *  else return 0.
+ */
+u8 WapiIncreasePN(u8 *PN, u8 AddCount)
+{
+	u8  i;
+
+	if (NULL == PN)
+		return 1;
+	/* YJ,test,091102 */
+	/*
+	if(AddCount == 2){
+		RTW_INFO("############################%s(): PN[0]=0x%x\n", __FUNCTION__, PN[0]);
+		if(PN[0] == 0x48){
+			PN[0] += AddCount;
+			return 1;
+		}else{
+			PN[0] += AddCount;
+			return 0;
+		}
+	}
+	*/
+	/* YJ,test,091102,end */
+
+	for (i = 0; i < 16; i++) {
+		if (PN[i] + AddCount <= 0xff) {
+			PN[i] += AddCount;
+			return 0;
+		} else {
+			PN[i] += AddCount;
+			AddCount = 1;
+		}
+	}
+	return 1;
+}
+
+
+void WapiGetLastRxUnicastPNForQoSData(
+	u8			UserPriority,
+	PRT_WAPI_STA_INFO    pWapiStaInfo,
+	u8 *PNOut
+)
+{
+	WAPI_TRACE(WAPI_RX, "===========> %s\n", __FUNCTION__);
+	switch (UserPriority) {
+	case 0:
+	case 3:
+		memcpy(PNOut, pWapiStaInfo->lastRxUnicastPNBEQueue, 16);
+		break;
+	case 1:
+	case 2:
+		memcpy(PNOut, pWapiStaInfo->lastRxUnicastPNBKQueue, 16);
+		break;
+	case 4:
+	case 5:
+		memcpy(PNOut, pWapiStaInfo->lastRxUnicastPNVIQueue, 16);
+		break;
+	case 6:
+	case 7:
+		memcpy(PNOut, pWapiStaInfo->lastRxUnicastPNVOQueue, 16);
+		break;
+	default:
+		WAPI_TRACE(WAPI_ERR, "%s: Unknown TID\n", __FUNCTION__);
+		break;
+	}
+	WAPI_TRACE(WAPI_RX, "<=========== %s\n", __FUNCTION__);
+}
+
+
+void WapiSetLastRxUnicastPNForQoSData(
+	u8		UserPriority,
+	u8           *PNIn,
+	PRT_WAPI_STA_INFO    pWapiStaInfo
+)
+{
+	WAPI_TRACE(WAPI_RX, "===========> %s\n", __FUNCTION__);
+	switch (UserPriority) {
+	case 0:
+	case 3:
+		memcpy(pWapiStaInfo->lastRxUnicastPNBEQueue, PNIn, 16);
+		break;
+	case 1:
+	case 2:
+		memcpy(pWapiStaInfo->lastRxUnicastPNBKQueue, PNIn, 16);
+		break;
+	case 4:
+	case 5:
+		memcpy(pWapiStaInfo->lastRxUnicastPNVIQueue, PNIn, 16);
+		break;
+	case 6:
+	case 7:
+		memcpy(pWapiStaInfo->lastRxUnicastPNVOQueue, PNIn, 16);
+		break;
+	default:
+		WAPI_TRACE(WAPI_ERR, "%s: Unknown TID\n", __FUNCTION__);
+		break;
+	}
+	WAPI_TRACE(WAPI_RX, "<=========== %s\n", __FUNCTION__);
+}
+
+
+/****************************************************************************
+ FALSE not RX-Reorder
+ TRUE do RX Reorder
+add to support WAPI to N-mode
+*****************************************************************************/
+u8 WapiCheckPnInSwDecrypt(
+	_adapter *padapter,
+	struct sk_buff *pskb
+)
+{
+	u8				ret = false;
+
+#if 0
+	struct ieee80211_hdr_3addr_qos *header;
+	u16				fc;
+	u8				*pDaddr, *pTaddr, *pRaddr;
+
+	header = (struct ieee80211_hdr_3addr_qos *)pskb->data;
+	pTaddr = header->addr2;
+	pRaddr = header->addr1;
+	fc = le16_to_cpu(header->frame_ctl);
+
+	if (GetToDs(&fc))
+		pDaddr = header->addr3;
+	else
+		pDaddr = header->addr1;
+
+	if ((_rtw_memcmp(pRaddr, padapter->pnetdev->dev_addr, ETH_ALEN) == 0)
+	    &&	!(pDaddr)
+	    && (GetFrameType(&fc) == WIFI_QOS_DATA_TYPE))
+		/* && ieee->pHTInfo->bCurrentHTSupport && */
+		/* ieee->pHTInfo->bCurRxReorderEnable) */
+		ret = false;
+	else
+		ret = true;
+#endif
+	WAPI_TRACE(WAPI_RX, "%s: return %d\n", __FUNCTION__, ret);
+	return ret;
+}
+
+int SecSMS4HeaderFillIV(_adapter *padapter, u8 *pxmitframe)
+{
+	struct pkt_attrib *pattrib = &((struct xmit_frame *)pxmitframe)->attrib;
+	u8 *frame = ((struct xmit_frame *)pxmitframe)->buf_addr + TXDESC_OFFSET;
+	u8 *pSecHeader = NULL, *pos = NULL, *pRA = NULL;
+	u8 bPNOverflow = false, bFindMatchPeer = false, hdr_len = 0;
+	PWLAN_HEADER_WAPI_EXTENSION pWapiExt = NULL;
+	PRT_WAPI_T         pWapiInfo = &padapter->wapiInfo;
+	PRT_WAPI_STA_INFO  pWapiSta = NULL;
+	int ret = 0;
+
+	WAPI_TRACE(WAPI_TX, "=========>%s\n", __FUNCTION__);
+
+	return ret;
+#if 0
+	hdr_len = sMacHdrLng;
+	if (GetFrameType(pskb->data) == WIFI_QOS_DATA_TYPE)
+		hdr_len += 2;
+	/* hdr_len += SNAP_SIZE + sizeof(u16); */
+
+	pos = skb_push(pskb, padapter->wapiInfo.extra_prefix_len);
+	memmove(pos, pos + padapter->wapiInfo.extra_prefix_len, hdr_len);
+
+	pSecHeader = pskb->data + hdr_len;
+	pWapiExt = (PWLAN_HEADER_WAPI_EXTENSION)pSecHeader;
+	pRA = pskb->data + 4;
+
+	WAPI_DATA(WAPI_TX, "FillIV - Before Fill IV", pskb->data, pskb->len);
+
+	/* Address 1 is always receiver's address */
+	if (IS_MCAST(pRA)) {
+		if (!pWapiInfo->wapiTxMsk.bTxEnable) {
+			WAPI_TRACE(WAPI_ERR, "%s: bTxEnable = 0!!\n", __FUNCTION__);
+			return -2;
+		}
+		if (pWapiInfo->wapiTxMsk.keyId <= 1) {
+			pWapiExt->KeyIdx = pWapiInfo->wapiTxMsk.keyId;
+			pWapiExt->Reserved = 0;
+			bPNOverflow = WapiIncreasePN(pWapiInfo->lastTxMulticastPN, 1);
+			memcpy(pWapiExt->PN, pWapiInfo->lastTxMulticastPN, 16);
+			if (bPNOverflow) {
+				/* Update MSK Notification. */
+				WAPI_TRACE(WAPI_ERR, "===============>%s():multicast PN overflow\n", __FUNCTION__);
+				rtw_wapi_app_event_handler(padapter, NULL, 0, pRA, false, false, true, 0, false);
+			}
+		} else {
+			WAPI_TRACE(WAPI_ERR, "%s: Invalid Wapi Multicast KeyIdx!!\n", __FUNCTION__);
+			ret = -3;
+		}
+	} else {
+		list_for_each_entry(pWapiSta, &pWapiInfo->wapiSTAUsedList, list) {
+			if (!memcmp(pWapiSta->PeerMacAddr, pRA, 6)) {
+				bFindMatchPeer = true;
+				break;
+			}
+		}
+		if (bFindMatchPeer) {
+			if ((!pWapiSta->wapiUskUpdate.bTxEnable) && (!pWapiSta->wapiUsk.bTxEnable)) {
+				WAPI_TRACE(WAPI_ERR, "%s: bTxEnable = 0!!\n", __FUNCTION__);
+				return -4;
+			}
+			if (pWapiSta->wapiUsk.keyId <= 1) {
+				if (pWapiSta->wapiUskUpdate.bTxEnable)
+					pWapiExt->KeyIdx = pWapiSta->wapiUskUpdate.keyId;
+				else
+					pWapiExt->KeyIdx = pWapiSta->wapiUsk.keyId;
+
+				pWapiExt->Reserved = 0;
+				bPNOverflow = WapiIncreasePN(pWapiSta->lastTxUnicastPN, 2);
+				memcpy(pWapiExt->PN, pWapiSta->lastTxUnicastPN, 16);
+				if (bPNOverflow) {
+					/* Update USK Notification. */
+					WAPI_TRACE(WAPI_ERR, "===============>%s():unicast PN overflow\n", __FUNCTION__);
+					rtw_wapi_app_event_handler(padapter, NULL, 0, pWapiSta->PeerMacAddr, false, true, false, 0, false);
+				}
+			} else {
+				WAPI_TRACE(WAPI_ERR, "%s: Invalid Wapi Unicast KeyIdx!!\n", __FUNCTION__);
+				ret = -5;
+			}
+		} else {
+			WAPI_TRACE(WAPI_ERR, "%s: Can not find Peer Sta "MAC_FMT"!!\n", __FUNCTION__, MAC_ARG(pRA));
+			ret = -6;
+		}
+	}
+
+	WAPI_DATA(WAPI_TX, "FillIV - After Fill IV", pskb->data, pskb->len);
+	WAPI_TRACE(WAPI_TX, "<=========%s\n", __FUNCTION__);
+	return ret;
+#endif
+}
+
+/* WAPI SW Enc: must have done Coalesce! */
+void SecSWSMS4Encryption(
+	_adapter *padapter,
+	u8 *pxmitframe
+)
+{
+	PRT_WAPI_T		pWapiInfo = &padapter->wapiInfo;
+	PRT_WAPI_STA_INFO   pWapiSta = NULL;
+	u8 *pframe = ((struct xmit_frame *)pxmitframe)->buf_addr + TXDESC_SIZE;
+	struct pkt_attrib *pattrib = &((struct xmit_frame *)pxmitframe)->attrib;
+
+	u8 *SecPtr = NULL, *pRA, *pMicKey = NULL, *pDataKey = NULL, *pIV = NULL;
+	u8 IVOffset, DataOffset, bFindMatchPeer = false, KeyIdx = 0, MicBuffer[16];
+	u16 OutputLength;
+
+	WAPI_TRACE(WAPI_TX, "=========>%s\n", __FUNCTION__);
+
+	WAPI_TRACE(WAPI_TX, "hdrlen: %d\n", pattrib->hdrlen);
+
+	return;
+
+	DataOffset = pattrib->hdrlen + pattrib->iv_len;
+
+	pRA = pframe + 4;
+
+
+	if (IS_MCAST(pRA)) {
+		KeyIdx = pWapiInfo->wapiTxMsk.keyId;
+		pIV = pWapiInfo->lastTxMulticastPN;
+		pMicKey = pWapiInfo->wapiTxMsk.micKey;
+		pDataKey = pWapiInfo->wapiTxMsk.dataKey;
+	} else {
+		if (!list_empty(&(pWapiInfo->wapiSTAUsedList))) {
+			list_for_each_entry(pWapiSta, &pWapiInfo->wapiSTAUsedList, list) {
+				if (0 == memcmp(pWapiSta->PeerMacAddr, pRA, 6)) {
+					bFindMatchPeer = true;
+					break;
+				}
+			}
+
+			if (bFindMatchPeer) {
+				if (pWapiSta->wapiUskUpdate.bTxEnable) {
+					KeyIdx = pWapiSta->wapiUskUpdate.keyId;
+					WAPI_TRACE(WAPI_TX, "%s(): Use update USK!! KeyIdx=%d\n", __FUNCTION__, KeyIdx);
+					pIV = pWapiSta->lastTxUnicastPN;
+					pMicKey = pWapiSta->wapiUskUpdate.micKey;
+					pDataKey = pWapiSta->wapiUskUpdate.dataKey;
+				} else {
+					KeyIdx = pWapiSta->wapiUsk.keyId;
+					WAPI_TRACE(WAPI_TX, "%s(): Use USK!! KeyIdx=%d\n", __FUNCTION__, KeyIdx);
+					pIV = pWapiSta->lastTxUnicastPN;
+					pMicKey = pWapiSta->wapiUsk.micKey;
+					pDataKey = pWapiSta->wapiUsk.dataKey;
+				}
+			} else {
+				WAPI_TRACE(WAPI_ERR, "%s: Can not find Peer Sta!!\n", __FUNCTION__);
+				return;
+			}
+		} else {
+			WAPI_TRACE(WAPI_ERR, "%s: wapiSTAUsedList is empty!!\n", __FUNCTION__);
+			return;
+		}
+	}
+
+	SecPtr = pframe;
+	SecCalculateMicSMS4(KeyIdx, pMicKey, SecPtr, (SecPtr + DataOffset), pattrib->pktlen, MicBuffer);
+
+	WAPI_DATA(WAPI_TX, "Encryption - MIC", MicBuffer, padapter->wapiInfo.extra_postfix_len);
+
+	memcpy(pframe + pattrib->hdrlen + pattrib->iv_len + pattrib->pktlen - pattrib->icv_len,
+	       (u8 *)MicBuffer,
+	       padapter->wapiInfo.extra_postfix_len
+	      );
+
+
+	WapiSMS4Encryption(pDataKey, pIV, (SecPtr + DataOffset), pattrib->pktlen + pattrib->icv_len, (SecPtr + DataOffset), &OutputLength);
+
+	WAPI_DATA(WAPI_TX, "Encryption - After SMS4 encryption", pframe, pattrib->hdrlen + pattrib->iv_len + pattrib->pktlen);
+
+	WAPI_TRACE(WAPI_TX, "<=========%s\n", __FUNCTION__);
+}
+
+u8 SecSWSMS4Decryption(
+	_adapter *padapter,
+	u8		*precv_frame,
+	struct recv_priv *precv_priv
+)
+{
+	PRT_WAPI_T pWapiInfo = &padapter->wapiInfo;
+	struct recv_frame_hdr *precv_hdr;
+	PRT_WAPI_STA_INFO   pWapiSta = NULL;
+	u8 IVOffset, DataOffset, bFindMatchPeer = false, bUseUpdatedKey = false;
+	u8 KeyIdx, MicBuffer[16], lastRxPNforQoS[16];
+	u8 *pRA, *pTA, *pMicKey, *pDataKey, *pLastRxPN, *pRecvPN, *pSecData, *pRecvMic, *pos;
+	u8 TID = 0;
+	u16 OutputLength, DataLen;
+	u8   bQosData;
+	struct sk_buff	*pskb;
+
+	WAPI_TRACE(WAPI_RX, "=========>%s\n", __FUNCTION__);
+
+	return 0;
+
+	precv_hdr = &((union recv_frame *)precv_frame)->u.hdr;
+	pskb = (struct sk_buff *)(precv_hdr->rx_data);
+	precv_hdr->bWapiCheckPNInDecrypt = WapiCheckPnInSwDecrypt(padapter, pskb);
+	WAPI_TRACE(WAPI_RX, "=========>%s: check PN  %d\n", __FUNCTION__, precv_hdr->bWapiCheckPNInDecrypt);
+	WAPI_DATA(WAPI_RX, "Decryption - Before decryption", pskb->data, pskb->len);
+
+	IVOffset = sMacHdrLng;
+	bQosData = GetFrameType(pskb->data) == WIFI_QOS_DATA_TYPE;
+	if (bQosData)
+		IVOffset += 2;
+
+	/* if(GetHTC()) */
+	/*	IVOffset += 4; */
+
+	/* IVOffset += SNAP_SIZE + sizeof(u16); */
+
+	DataOffset = IVOffset + padapter->wapiInfo.extra_prefix_len;
+
+	pRA = pskb->data + 4;
+	pTA = pskb->data + 10;
+	KeyIdx = *(pskb->data + IVOffset);
+	pRecvPN = pskb->data + IVOffset + 2;
+	pSecData = pskb->data + DataOffset;
+	DataLen = pskb->len - DataOffset;
+	pRecvMic = pskb->data + pskb->len - padapter->wapiInfo.extra_postfix_len;
+	TID = GetTid(pskb->data);
+
+	if (!list_empty(&(pWapiInfo->wapiSTAUsedList))) {
+		list_for_each_entry(pWapiSta, &pWapiInfo->wapiSTAUsedList, list) {
+			if (0 == memcmp(pWapiSta->PeerMacAddr, pTA, 6)) {
+				bFindMatchPeer = true;
+				break;
+			}
+		}
+	}
+
+	if (!bFindMatchPeer) {
+		WAPI_TRACE(WAPI_ERR, "%s: Can not find Peer Sta "MAC_FMT" for Key Info!!!\n", __FUNCTION__, MAC_ARG(pTA));
+		return false;
+	}
+
+	if (IS_MCAST(pRA)) {
+		WAPI_TRACE(WAPI_RX, "%s: Multicast decryption !!!\n", __FUNCTION__);
+		if (pWapiSta->wapiMsk.keyId == KeyIdx && pWapiSta->wapiMsk.bSet) {
+			pLastRxPN = pWapiSta->lastRxMulticastPN;
+			if (!WapiComparePN(pRecvPN, pLastRxPN)) {
+				WAPI_TRACE(WAPI_ERR, "%s: MSK PN is not larger than last, Dropped!!!\n", __FUNCTION__);
+				WAPI_DATA(WAPI_ERR, "pRecvPN:", pRecvPN, 16);
+				WAPI_DATA(WAPI_ERR, "pLastRxPN:", pLastRxPN, 16);
+				return false;
+			}
+
+			memcpy(pLastRxPN, pRecvPN, 16);
+			pMicKey = pWapiSta->wapiMsk.micKey;
+			pDataKey = pWapiSta->wapiMsk.dataKey;
+		} else if (pWapiSta->wapiMskUpdate.keyId == KeyIdx && pWapiSta->wapiMskUpdate.bSet) {
+			WAPI_TRACE(WAPI_RX, "%s: Use Updated MSK for Decryption !!!\n", __FUNCTION__);
+			bUseUpdatedKey = true;
+			memcpy(pWapiSta->lastRxMulticastPN, pRecvPN, 16);
+			pMicKey = pWapiSta->wapiMskUpdate.micKey;
+			pDataKey = pWapiSta->wapiMskUpdate.dataKey;
+		} else {
+			WAPI_TRACE(WAPI_ERR, "%s: Can not find MSK with matched KeyIdx(%d), Dropped !!!\n", __FUNCTION__, KeyIdx);
+			return false;
+		}
+	} else {
+		WAPI_TRACE(WAPI_RX, "%s: Unicast decryption !!!\n", __FUNCTION__);
+		if (pWapiSta->wapiUsk.keyId == KeyIdx && pWapiSta->wapiUsk.bSet) {
+			WAPI_TRACE(WAPI_RX, "%s: Use USK for Decryption!!!\n", __FUNCTION__);
+			if (precv_hdr->bWapiCheckPNInDecrypt) {
+				if (GetFrameType(pskb->data) == WIFI_QOS_DATA_TYPE) {
+					WapiGetLastRxUnicastPNForQoSData(TID, pWapiSta, lastRxPNforQoS);
+					pLastRxPN = lastRxPNforQoS;
+				} else
+					pLastRxPN = pWapiSta->lastRxUnicastPN;
+				if (!WapiComparePN(pRecvPN, pLastRxPN))
+					return false;
+				if (bQosData)
+					WapiSetLastRxUnicastPNForQoSData(TID, pRecvPN, pWapiSta);
+				else
+					memcpy(pWapiSta->lastRxUnicastPN, pRecvPN, 16);
+			} else
+				memcpy(precv_hdr->WapiTempPN, pRecvPN, 16);
+
+			if (check_fwstate(&padapter->mlmepriv, WIFI_STATION_STATE)) {
+				if ((pRecvPN[0] & 0x1) == 0) {
+					WAPI_TRACE(WAPI_ERR, "%s: Rx USK PN is not odd when Infra STA mode, Dropped !!!\n", __FUNCTION__);
+					return false;
+				}
+			}
+
+			pMicKey = pWapiSta->wapiUsk.micKey;
+			pDataKey = pWapiSta->wapiUsk.dataKey;
+		} else if (pWapiSta->wapiUskUpdate.keyId == KeyIdx && pWapiSta->wapiUskUpdate.bSet) {
+			WAPI_TRACE(WAPI_RX, "%s: Use Updated USK for Decryption!!!\n", __FUNCTION__);
+			if (pWapiSta->bAuthenticatorInUpdata)
+				bUseUpdatedKey = true;
+			else
+				bUseUpdatedKey = false;
+
+			if (bQosData)
+				WapiSetLastRxUnicastPNForQoSData(TID, pRecvPN, pWapiSta);
+			else
+				memcpy(pWapiSta->lastRxUnicastPN, pRecvPN, 16);
+			pMicKey = pWapiSta->wapiUskUpdate.micKey;
+			pDataKey = pWapiSta->wapiUskUpdate.dataKey;
+		} else {
+			WAPI_TRACE(WAPI_ERR, "%s: No valid USK!!!KeyIdx=%d pWapiSta->wapiUsk.keyId=%d pWapiSta->wapiUskUpdate.keyId=%d\n", __FUNCTION__, KeyIdx, pWapiSta->wapiUsk.keyId,
+				   pWapiSta->wapiUskUpdate.keyId);
+			/* dump_buf(pskb->data,pskb->len); */
+			return false;
+		}
+	}
+
+	WAPI_DATA(WAPI_RX, "Decryption - DataKey", pDataKey, 16);
+	WAPI_DATA(WAPI_RX, "Decryption - IV", pRecvPN, 16);
+	WapiSMS4Decryption(pDataKey, pRecvPN, pSecData, DataLen, pSecData, &OutputLength);
+
+	if (OutputLength != DataLen)
+		WAPI_TRACE(WAPI_ERR, "%s:  Output Length Error!!!!\n", __FUNCTION__);
+
+	WAPI_DATA(WAPI_RX, "Decryption - After decryption", pskb->data, pskb->len);
+
+	DataLen -= padapter->wapiInfo.extra_postfix_len;
+
+	SecCalculateMicSMS4(KeyIdx, pMicKey, pskb->data, pSecData, DataLen, MicBuffer);
+
+	WAPI_DATA(WAPI_RX, "Decryption - MIC received", pRecvMic, SMS4_MIC_LEN);
+	WAPI_DATA(WAPI_RX, "Decryption - MIC calculated", MicBuffer, SMS4_MIC_LEN);
+
+	if (0 == memcmp(MicBuffer, pRecvMic, padapter->wapiInfo.extra_postfix_len)) {
+		WAPI_TRACE(WAPI_RX, "%s: Check MIC OK!!\n", __FUNCTION__);
+		if (bUseUpdatedKey) {
+			/* delete the old key */
+			if (IS_MCAST(pRA)) {
+				WAPI_TRACE(WAPI_API, "%s(): AE use new update MSK!!\n", __FUNCTION__);
+				pWapiSta->wapiMsk.keyId = pWapiSta->wapiMskUpdate.keyId;
+				memcpy(pWapiSta->wapiMsk.dataKey, pWapiSta->wapiMskUpdate.dataKey, 16);
+				memcpy(pWapiSta->wapiMsk.micKey, pWapiSta->wapiMskUpdate.micKey, 16);
+				pWapiSta->wapiMskUpdate.bTxEnable = pWapiSta->wapiMskUpdate.bSet = false;
+			} else {
+				WAPI_TRACE(WAPI_API, "%s(): AE use new update USK!!\n", __FUNCTION__);
+				pWapiSta->wapiUsk.keyId = pWapiSta->wapiUskUpdate.keyId;
+				memcpy(pWapiSta->wapiUsk.dataKey, pWapiSta->wapiUskUpdate.dataKey, 16);
+				memcpy(pWapiSta->wapiUsk.micKey, pWapiSta->wapiUskUpdate.micKey, 16);
+				pWapiSta->wapiUskUpdate.bTxEnable = pWapiSta->wapiUskUpdate.bSet = false;
+			}
+		}
+	} else {
+		WAPI_TRACE(WAPI_ERR, "%s:  Check MIC Error, Dropped !!!!\n", __FUNCTION__);
+		return false;
+	}
+
+	pos = pskb->data;
+	memmove(pos + padapter->wapiInfo.extra_prefix_len, pos, IVOffset);
+	skb_pull(pskb, padapter->wapiInfo.extra_prefix_len);
+
+	WAPI_TRACE(WAPI_RX, "<=========%s\n", __FUNCTION__);
+
+	return true;
+}
+
+u32	rtw_sms4_encrypt(_adapter *padapter, u8 *pxmitframe)
+{
+
+	u8	*pframe;
+	u32 res = _SUCCESS;
+
+	WAPI_TRACE(WAPI_TX, "=========>%s\n", __FUNCTION__);
+
+	if ((!padapter->WapiSupport) || (!padapter->wapiInfo.bWapiEnable)) {
+		WAPI_TRACE(WAPI_TX, "<========== %s, WAPI not supported or enabled!\n", __FUNCTION__);
+		return _FAIL;
+	}
+
+	if (((struct xmit_frame *)pxmitframe)->buf_addr == NULL)
+		return _FAIL;
+
+	pframe = ((struct xmit_frame *)pxmitframe)->buf_addr + TXDESC_OFFSET;
+
+	SecSWSMS4Encryption(padapter, pxmitframe);
+
+	WAPI_TRACE(WAPI_TX, "<=========%s\n", __FUNCTION__);
+	return res;
+}
+
+u32	rtw_sms4_decrypt(_adapter *padapter, u8 *precvframe)
+{
+	u8	*pframe;
+	u32 res = _SUCCESS;
+
+	WAPI_TRACE(WAPI_RX, "=========>%s\n", __FUNCTION__);
+
+	if ((!padapter->WapiSupport) || (!padapter->wapiInfo.bWapiEnable)) {
+		WAPI_TRACE(WAPI_RX, "<========== %s, WAPI not supported or enabled!\n", __FUNCTION__);
+		return _FAIL;
+	}
+
+
+	/* drop packet when hw decrypt fail
+	* return tempraily */
+	return _FAIL;
+
+	/* pframe=(unsigned char *)((union recv_frame*)precvframe)->u.hdr.rx_data; */
+
+	if (false == SecSWSMS4Decryption(padapter, precvframe, &padapter->recvpriv)) {
+		WAPI_TRACE(WAPI_ERR, "%s():SMS4 decrypt frame error\n", __FUNCTION__);
+		return _FAIL;
+	}
+
+	WAPI_TRACE(WAPI_RX, "<=========%s\n", __FUNCTION__);
+	return res;
+}
+
+#else
+
+u32	rtw_sms4_encrypt(_adapter *padapter, u8 *pxmitframe)
+{
+	WAPI_TRACE(WAPI_TX, "=========>Dummy %s\n", __FUNCTION__);
+	WAPI_TRACE(WAPI_TX, "<=========Dummy %s\n", __FUNCTION__);
+	return _SUCCESS;
+}
+
+u32	rtw_sms4_decrypt(_adapter *padapter, u8 *precvframe)
+{
+	WAPI_TRACE(WAPI_RX, "=========>Dummy %s\n", __FUNCTION__);
+	WAPI_TRACE(WAPI_RX, "<=========Dummy %s\n", __FUNCTION__);
+	return _SUCCESS;
+}
+
+#endif
+
+#endif
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/core/rtw_vht.c linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/core/rtw_vht.c
--- linux-5.6.3/3rdparty/rtl8821ce/core/rtw_vht.c	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/core/rtw_vht.c	2020-04-10 16:35:06.779658341 +0300
@@ -0,0 +1,1135 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#define _RTW_VHT_C
+
+#include <drv_types.h>
+#include <hal_data.h>
+
+#ifdef CONFIG_80211AC_VHT
+const u16 _vht_max_mpdu_len[] = {
+	3895,
+	7991,
+	11454,
+	0,
+};
+
+const u8 _vht_sup_ch_width_set_to_bw_cap[] = {
+	BW_CAP_80M,
+	BW_CAP_80M | BW_CAP_160M,
+	BW_CAP_80M | BW_CAP_160M | BW_CAP_80_80M,
+	0,
+};
+
+const char *const _vht_sup_ch_width_set_str[] = {
+	"80MHz",
+	"160MHz",
+	"160MHz & 80+80MHz",
+	"BW-RSVD",
+};
+
+void dump_vht_cap_ie_content(void *sel, const u8 *buf, u32 buf_len)
+{
+	if (buf_len != VHT_CAP_IE_LEN) {
+		RTW_PRINT_SEL(sel, "Invalid VHT capability IE len:%d != %d\n", buf_len, VHT_CAP_IE_LEN);
+		return;
+	}
+
+	RTW_PRINT_SEL(sel, "cap_info:%02x %02x %02x %02x: MAX_MPDU_LEN:%u %s%s%s%s%s RX-STBC:%u MAX_AMPDU_LEN:%u\n"
+		, *(buf), *(buf + 1), *(buf + 2), *(buf + 3)
+		, vht_max_mpdu_len(GET_VHT_CAPABILITY_ELE_MAX_MPDU_LENGTH(buf))
+		, vht_sup_ch_width_set_str(GET_VHT_CAPABILITY_ELE_CHL_WIDTH(buf))
+		, GET_VHT_CAPABILITY_ELE_RX_LDPC(buf) ? " RX-LDPC" : ""
+		, GET_VHT_CAPABILITY_ELE_SHORT_GI80M(buf) ? " SGI-80" : ""
+		, GET_VHT_CAPABILITY_ELE_SHORT_GI160M(buf) ? " SGI-160" : ""
+		, GET_VHT_CAPABILITY_ELE_TX_STBC(buf) ? " TX-STBC" : ""
+		, GET_VHT_CAPABILITY_ELE_RX_STBC(buf)
+		, VHT_MAX_AMPDU_LEN(GET_VHT_CAPABILITY_ELE_MAX_RXAMPDU_FACTOR(buf))
+	);
+}
+
+void dump_vht_cap_ie(void *sel, const u8 *ie, u32 ie_len)
+{
+	const u8 *vht_cap_ie;
+	sint vht_cap_ielen;
+
+	vht_cap_ie = rtw_get_ie(ie, WLAN_EID_VHT_CAPABILITY, &vht_cap_ielen, ie_len);
+	if (!ie || vht_cap_ie != ie)
+		return;
+
+	dump_vht_cap_ie_content(sel, vht_cap_ie + 2, vht_cap_ielen);
+}
+
+const char *const _vht_op_ch_width_str[] = {
+	"20 or 40MHz",
+	"80MHz",
+	"160MHz",
+	"80+80MHz",
+	"BW-RSVD",
+};
+
+void dump_vht_op_ie_content(void *sel, const u8 *buf, u32 buf_len)
+{
+	if (buf_len != VHT_OP_IE_LEN) {
+		RTW_PRINT_SEL(sel, "Invalid VHT operation IE len:%d != %d\n", buf_len, VHT_OP_IE_LEN);
+		return;
+	}
+
+	RTW_PRINT_SEL(sel, "%s, ch0:%u, ch1:%u\n"
+		, vht_op_ch_width_str(GET_VHT_OPERATION_ELE_CHL_WIDTH(buf))
+		, GET_VHT_OPERATION_ELE_CENTER_FREQ1(buf)
+		, GET_VHT_OPERATION_ELE_CENTER_FREQ2(buf)
+	);
+}
+
+void dump_vht_op_ie(void *sel, const u8 *ie, u32 ie_len)
+{
+	const u8 *vht_op_ie;
+	sint vht_op_ielen;
+
+	vht_op_ie = rtw_get_ie(ie, WLAN_EID_VHT_OPERATION, &vht_op_ielen, ie_len);
+	if (!ie || vht_op_ie != ie)
+		return;
+
+	dump_vht_op_ie_content(sel, vht_op_ie + 2, vht_op_ielen);
+}
+
+/*				20/40/80,	ShortGI,	MCS Rate  */
+const u16 VHT_MCS_DATA_RATE[3][2][30] = {
+	{	{
+			13, 26, 39, 52, 78, 104, 117, 130, 156, 156,
+			26, 52, 78, 104, 156, 208, 234, 260, 312, 312,
+			39, 78, 117, 156, 234, 312, 351, 390, 468, 520
+		},			/* Long GI, 20MHz */
+		{
+			14, 29, 43, 58, 87, 116, 130, 144, 173, 173,
+			29, 58, 87, 116, 173, 231, 260, 289, 347, 347,
+			43,	87, 130, 173, 260, 347, 390,	433,	520, 578
+		}
+	},		/* Short GI, 20MHz */
+	{	{
+			27, 54, 81, 108, 162, 216, 243, 270, 324, 360,
+			54, 108, 162, 216, 324, 432, 486, 540, 648, 720,
+			81, 162, 243, 324, 486, 648, 729, 810, 972, 1080
+		}, 		/* Long GI, 40MHz */
+		{
+			30, 60, 90, 120, 180, 240, 270, 300, 360, 400,
+			60, 120, 180, 240, 360, 480, 540, 600, 720, 800,
+			90, 180, 270, 360, 540, 720, 810, 900, 1080, 1200
+		}
+	},		/* Short GI, 40MHz */
+	{	{
+			59, 117,  176, 234, 351, 468, 527, 585, 702, 780,
+			117, 234, 351, 468, 702, 936, 1053, 1170, 1404, 1560,
+			176, 351, 527, 702, 1053, 1404, 1580, 1755, 2106, 2340
+		},	/* Long GI, 80MHz */
+		{
+			65, 130, 195, 260, 390, 520, 585, 650, 780, 867,
+			130, 260, 390, 520, 780, 1040, 1170, 1300, 1560, 1734,
+			195, 390, 585, 780, 1170, 1560, 1755, 1950, 2340, 2600
+		}
+	}	/* Short GI, 80MHz */
+};
+
+u8	rtw_get_vht_highest_rate(u8 *pvht_mcs_map)
+{
+	u8	i, j;
+	u8	bit_map;
+	u8	vht_mcs_rate = 0;
+
+	for (i = 0; i < 2; i++) {
+		if (pvht_mcs_map[i] != 0xff) {
+			for (j = 0; j < 8; j += 2) {
+				bit_map = (pvht_mcs_map[i] >> j) & 3;
+
+				if (bit_map != 3)
+					vht_mcs_rate = MGN_VHT1SS_MCS7 + 10 * j / 2 + i * 40 + bit_map; /* VHT rate indications begin from 0x90 */
+			}
+		}
+	}
+
+	/* RTW_INFO("HighestVHTMCSRate is %x\n", vht_mcs_rate); */
+	return vht_mcs_rate;
+}
+
+u8	rtw_vht_mcsmap_to_nss(u8 *pvht_mcs_map)
+{
+	u8	i, j;
+	u8	bit_map;
+	u8	nss = 0;
+
+	for (i = 0; i < 2; i++) {
+		if (pvht_mcs_map[i] != 0xff) {
+			for (j = 0; j < 8; j += 2) {
+				bit_map = (pvht_mcs_map[i] >> j) & 3;
+
+				if (bit_map != 3)
+					nss++;
+			}
+		}
+	}
+
+	/* RTW_INFO("%s : %dSS\n", __FUNCTION__, nss); */
+	return nss;
+}
+
+void rtw_vht_nss_to_mcsmap(u8 nss, u8 *target_mcs_map, u8 *cur_mcs_map)
+{
+	u8	i, j;
+	u8	cur_rate, target_rate;
+
+	for (i = 0; i < 2; i++) {
+		target_mcs_map[i] = 0;
+		for (j = 0; j < 8; j += 2) {
+			cur_rate = (cur_mcs_map[i] >> j) & 3;
+			if (cur_rate == 3) /* 0x3 indicates not supported that num of SS */
+				target_rate = 3;
+			else if (nss <= ((j / 2) + i * 4))
+				target_rate = 3;
+			else
+				target_rate = cur_rate;
+
+			target_mcs_map[i] |= (target_rate << j);
+		}
+	}
+
+	/* RTW_INFO("%s : %dSS\n", __FUNCTION__, nss); */
+}
+
+u16	rtw_vht_mcs_to_data_rate(u8 bw, u8 short_GI, u8 vht_mcs_rate)
+{
+	if (vht_mcs_rate > MGN_VHT3SS_MCS9)
+		vht_mcs_rate = MGN_VHT3SS_MCS9;
+	/* RTW_INFO("bw=%d, short_GI=%d, ((vht_mcs_rate - MGN_VHT1SS_MCS0)&0x3f)=%d\n", bw, short_GI, ((vht_mcs_rate - MGN_VHT1SS_MCS0)&0x3f)); */
+	return VHT_MCS_DATA_RATE[bw][short_GI][((vht_mcs_rate - MGN_VHT1SS_MCS0) & 0x3f)];
+}
+
+void	rtw_vht_use_default_setting(_adapter *padapter)
+{
+	struct mlme_priv		*pmlmepriv = &padapter->mlmepriv;
+	struct vht_priv		*pvhtpriv = &pmlmepriv->vhtpriv;
+	struct registry_priv	*pregistrypriv = &padapter->registrypriv;
+	BOOLEAN		bHwLDPCSupport = _FALSE, bHwSTBCSupport = _FALSE;
+#ifdef CONFIG_BEAMFORMING
+	BOOLEAN		bHwSupportBeamformer = _FALSE, bHwSupportBeamformee = _FALSE;
+	u8	mu_bfer, mu_bfee;
+#endif /* CONFIG_BEAMFORMING */
+	u8	rf_type = 0;
+	u8 tx_nss, rx_nss;
+	struct hal_spec_t *hal_spec = GET_HAL_SPEC(padapter);
+	struct mlme_ext_priv	*pmlmeext = &(padapter->mlmeextpriv);
+	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
+	pvhtpriv->sgi_80m = TEST_FLAG(pregistrypriv->short_gi, BIT2) ? _TRUE : _FALSE;
+
+	/* LDPC support */
+	rtw_hal_get_def_var(padapter, HAL_DEF_RX_LDPC, (u8 *)&bHwLDPCSupport);
+	CLEAR_FLAGS(pvhtpriv->ldpc_cap);
+	if (bHwLDPCSupport) {
+		if (TEST_FLAG(pregistrypriv->ldpc_cap, BIT0))
+			SET_FLAG(pvhtpriv->ldpc_cap, LDPC_VHT_ENABLE_RX);
+	}
+	rtw_hal_get_def_var(padapter, HAL_DEF_TX_LDPC, (u8 *)&bHwLDPCSupport);
+	if (bHwLDPCSupport) {
+		if (TEST_FLAG(pregistrypriv->ldpc_cap, BIT1))
+			SET_FLAG(pvhtpriv->ldpc_cap, LDPC_VHT_ENABLE_TX);
+	}
+	if (pvhtpriv->ldpc_cap)
+		RTW_INFO("[VHT] Support LDPC = 0x%02X\n", pvhtpriv->ldpc_cap);
+
+	/* STBC */
+	rtw_hal_get_def_var(padapter, HAL_DEF_TX_STBC, (u8 *)&bHwSTBCSupport);
+	CLEAR_FLAGS(pvhtpriv->stbc_cap);
+	if (bHwSTBCSupport) {
+		if (TEST_FLAG(pregistrypriv->stbc_cap, BIT1))
+			SET_FLAG(pvhtpriv->stbc_cap, STBC_VHT_ENABLE_TX);
+	}
+	rtw_hal_get_def_var(padapter, HAL_DEF_RX_STBC, (u8 *)&bHwSTBCSupport);
+	if (bHwSTBCSupport) {
+		if (TEST_FLAG(pregistrypriv->stbc_cap, BIT0))
+			SET_FLAG(pvhtpriv->stbc_cap, STBC_VHT_ENABLE_RX);
+	}
+	if (pvhtpriv->stbc_cap)
+		RTW_INFO("[VHT] Support STBC = 0x%02X\n", pvhtpriv->stbc_cap);
+
+	/* Beamforming setting */
+	CLEAR_FLAGS(pvhtpriv->beamform_cap);
+#ifdef CONFIG_BEAMFORMING
+#ifdef RTW_BEAMFORMING_VERSION_2
+	/* only enable beamforming in STA client mode */
+	if (MLME_IS_STA(padapter) && !MLME_IS_GC(padapter)
+				  && !MLME_IS_ADHOC(padapter)
+				  && !MLME_IS_MESH(padapter))
+#endif
+	{
+		rtw_hal_get_def_var(padapter, HAL_DEF_EXPLICIT_BEAMFORMER,
+			(u8 *)&bHwSupportBeamformer);
+		rtw_hal_get_def_var(padapter, HAL_DEF_EXPLICIT_BEAMFORMEE,
+			(u8 *)&bHwSupportBeamformee);
+		mu_bfer = _FALSE;
+		mu_bfee = _FALSE;
+		rtw_hal_get_def_var(padapter, HAL_DEF_VHT_MU_BEAMFORMER, &mu_bfer);
+		rtw_hal_get_def_var(padapter, HAL_DEF_VHT_MU_BEAMFORMEE, &mu_bfee);
+		if (TEST_FLAG(pregistrypriv->beamform_cap, BIT0) && bHwSupportBeamformer) {
+#ifdef CONFIG_CONCURRENT_MODE
+			if ((pmlmeinfo->state & 0x03) == WIFI_FW_AP_STATE) {
+				SET_FLAG(pvhtpriv->beamform_cap, BEAMFORMING_VHT_BEAMFORMER_ENABLE);
+				RTW_INFO("[VHT] CONCURRENT AP Support Beamformer\n");
+				if (TEST_FLAG(pregistrypriv->beamform_cap, BIT(2))
+				    && (_TRUE == mu_bfer)) {
+					SET_FLAG(pvhtpriv->beamform_cap, BEAMFORMING_VHT_MU_MIMO_AP_ENABLE);
+					RTW_INFO("[VHT] Support MU-MIMO AP\n");
+				}
+			} else
+				RTW_INFO("[VHT] CONCURRENT not AP ;not allow  Support Beamformer\n");
+#else
+			SET_FLAG(pvhtpriv->beamform_cap, BEAMFORMING_VHT_BEAMFORMER_ENABLE);
+			RTW_INFO("[VHT] Support Beamformer\n");
+			if (TEST_FLAG(pregistrypriv->beamform_cap, BIT(2))
+			    && (_TRUE == mu_bfer)
+			    && ((pmlmeinfo->state & 0x03) == WIFI_FW_AP_STATE)) {
+				SET_FLAG(pvhtpriv->beamform_cap, BEAMFORMING_VHT_MU_MIMO_AP_ENABLE);
+				RTW_INFO("[VHT] Support MU-MIMO AP\n");
+			}
+#endif
+		}
+		if (TEST_FLAG(pregistrypriv->beamform_cap, BIT1) && bHwSupportBeamformee) {
+			SET_FLAG(pvhtpriv->beamform_cap, BEAMFORMING_VHT_BEAMFORMEE_ENABLE);
+			RTW_INFO("[VHT] Support Beamformee\n");
+			if (TEST_FLAG(pregistrypriv->beamform_cap, BIT(3))
+			    && (_TRUE == mu_bfee)
+			    && ((pmlmeinfo->state & 0x03) != WIFI_FW_AP_STATE)) {
+				SET_FLAG(pvhtpriv->beamform_cap, BEAMFORMING_VHT_MU_MIMO_STA_ENABLE);
+				RTW_INFO("[VHT] Support MU-MIMO STA\n");
+			}
+		}
+	}
+#endif /* CONFIG_BEAMFORMING */
+
+	pvhtpriv->ampdu_len = pregistrypriv->ampdu_factor;
+
+	rtw_hal_get_hwreg(padapter, HW_VAR_RF_TYPE, (u8 *)(&rf_type));
+	tx_nss = rtw_min(rf_type_to_rf_tx_cnt(rf_type), hal_spec->tx_nss_num);
+	rx_nss = rtw_min(rf_type_to_rf_rx_cnt(rf_type), hal_spec->rx_nss_num);
+
+	/* for now, vhtpriv.vht_mcs_map comes from RX NSS */
+	rtw_vht_nss_to_mcsmap(rx_nss, pvhtpriv->vht_mcs_map, pregistrypriv->vht_rx_mcs_map);
+	pvhtpriv->vht_highest_rate = rtw_get_vht_highest_rate(pvhtpriv->vht_mcs_map);
+}
+
+u64	rtw_vht_mcs_map_to_bitmap(u8 *mcs_map, u8 nss)
+{
+	u8 i, j, tmp;
+	u64 bitmap = 0;
+	u8 bits_nss = nss * 2;
+
+	for (i = j = 0; i < bits_nss; i += 2, j += 10) {
+		/* every two bits means single sptial stream */
+		tmp = (mcs_map[i / 8] >> i) & 3;
+
+		switch (tmp) {
+		case 2:
+			bitmap = bitmap | (0x03ff << j);
+			break;
+		case 1:
+			bitmap = bitmap | (0x01ff << j);
+			break;
+		case 0:
+			bitmap = bitmap | (0x00ff << j);
+			break;
+		default:
+			break;
+		}
+	}
+
+	RTW_INFO("vht_mcs_map=%02x %02x, nss=%u => bitmap=%016llx\n"
+		, mcs_map[0], mcs_map[1], nss, bitmap);
+
+	return bitmap;
+}
+
+#ifdef CONFIG_BEAMFORMING
+void update_sta_vht_info_apmode_bf_cap(_adapter *padapter, struct sta_info *psta)
+{
+	struct mlme_priv	*pmlmepriv = &(padapter->mlmepriv);
+	struct vht_priv	*pvhtpriv_ap = &pmlmepriv->vhtpriv;
+	struct vht_priv	*pvhtpriv_sta = &psta->vhtpriv;
+	u16	cur_beamform_cap = 0;
+
+	/* B11 SU Beamformer Capable, the target supports Beamformer and we are Beamformee */
+	if (TEST_FLAG(pvhtpriv_ap->beamform_cap, BEAMFORMING_VHT_BEAMFORMER_ENABLE) &&
+	    GET_VHT_CAPABILITY_ELE_SU_BFEE(pvhtpriv_sta->vht_cap)) {
+		SET_FLAG(cur_beamform_cap, BEAMFORMING_VHT_BEAMFORMEE_ENABLE);
+		/*Shift to BEAMFORMING_VHT_BEAMFORMER_STS_CAP*/
+		SET_FLAG(cur_beamform_cap, GET_VHT_CAPABILITY_ELE_SU_BFEE_STS_CAP(pvhtpriv_sta->vht_cap) << 8);
+	}
+
+	/* B12 SU Beamformee Capable, the target supports Beamformee and we are Beamformer */
+	if (TEST_FLAG(pvhtpriv_ap->beamform_cap, BEAMFORMING_VHT_BEAMFORMEE_ENABLE) &&
+	    GET_VHT_CAPABILITY_ELE_SU_BFER(pvhtpriv_sta->vht_cap)) {
+		SET_FLAG(cur_beamform_cap, BEAMFORMING_VHT_BEAMFORMER_ENABLE);
+		/*Shit to BEAMFORMING_VHT_BEAMFORMEE_SOUND_DIM*/
+		SET_FLAG(cur_beamform_cap, GET_VHT_CAPABILITY_ELE_SU_BFER_SOUND_DIM_NUM(pvhtpriv_sta->vht_cap) << 12);
+	}
+
+	if (cur_beamform_cap)
+		RTW_INFO("Current STA(%d) VHT Beamforming Setting = %02X\n", psta->cmn.aid, cur_beamform_cap);
+
+	pvhtpriv_sta->beamform_cap = cur_beamform_cap;
+	psta->cmn.bf_info.vht_beamform_cap = cur_beamform_cap;
+}
+#endif
+
+void	update_sta_vht_info_apmode(_adapter *padapter, PVOID sta)
+{
+	struct sta_info	*psta = (struct sta_info *)sta;
+	struct mlme_priv	*pmlmepriv = &(padapter->mlmepriv);
+	struct mlme_ext_priv	*pmlmeext = &padapter->mlmeextpriv;
+	struct vht_priv	*pvhtpriv_ap = &pmlmepriv->vhtpriv;
+	struct vht_priv	*pvhtpriv_sta = &psta->vhtpriv;
+	u8	cur_ldpc_cap = 0, cur_stbc_cap = 0;
+	s8 bw_mode = -1;
+	u8	*pcap_mcs;
+
+	if (pvhtpriv_sta->vht_option == _FALSE)
+		return;
+
+	if (pvhtpriv_sta->op_present) {
+		switch (GET_VHT_OPERATION_ELE_CHL_WIDTH(pvhtpriv_sta->vht_op)) {
+		case 1: /* 80MHz */
+		case 2: /* 160MHz */
+		case 3: /* 80+80 */
+			bw_mode = CHANNEL_WIDTH_80; /* only support up to 80MHz for now */
+			break;
+		}
+	}
+
+	if (pvhtpriv_sta->notify_present)
+		bw_mode = GET_VHT_OPERATING_MODE_FIELD_CHNL_WIDTH(&pvhtpriv_sta->vht_op_mode_notify);
+	else if (MLME_IS_AP(padapter)) {
+		/* for VHT client without Operating Mode Notify IE; minimal 80MHz */
+		if (bw_mode < CHANNEL_WIDTH_80)
+			bw_mode = CHANNEL_WIDTH_80;
+	}
+
+	if (bw_mode != -1)
+		psta->cmn.bw_mode = bw_mode; /* update bw_mode only if get value from VHT IEs */
+
+	psta->cmn.ra_info.is_vht_enable = _TRUE;
+
+	/* B4 Rx LDPC */
+	if (TEST_FLAG(pvhtpriv_ap->ldpc_cap, LDPC_VHT_ENABLE_TX) &&
+	    GET_VHT_CAPABILITY_ELE_RX_LDPC(pvhtpriv_sta->vht_cap)) {
+		SET_FLAG(cur_ldpc_cap, (LDPC_VHT_ENABLE_TX | LDPC_VHT_CAP_TX));
+		RTW_INFO("Current STA(%d) VHT LDPC = %02X\n", psta->cmn.aid, cur_ldpc_cap);
+	}
+	pvhtpriv_sta->ldpc_cap = cur_ldpc_cap;
+
+	if (psta->cmn.bw_mode > pmlmeext->cur_bwmode)
+		psta->cmn.bw_mode = pmlmeext->cur_bwmode;
+
+	if (psta->cmn.bw_mode == CHANNEL_WIDTH_80) {
+		/* B5 Short GI for 80 MHz */
+		pvhtpriv_sta->sgi_80m = (GET_VHT_CAPABILITY_ELE_SHORT_GI80M(pvhtpriv_sta->vht_cap) & pvhtpriv_ap->sgi_80m) ? _TRUE : _FALSE;
+		/* RTW_INFO("Current STA ShortGI80MHz = %d\n", pvhtpriv_sta->sgi_80m); */
+	} else if (psta->cmn.bw_mode >= CHANNEL_WIDTH_160) {
+		/* B5 Short GI for 80 MHz */
+		pvhtpriv_sta->sgi_80m = (GET_VHT_CAPABILITY_ELE_SHORT_GI160M(pvhtpriv_sta->vht_cap) & pvhtpriv_ap->sgi_80m) ? _TRUE : _FALSE;
+		/* RTW_INFO("Current STA ShortGI160MHz = %d\n", pvhtpriv_sta->sgi_80m); */
+	}
+
+	/* B8 B9 B10 Rx STBC */
+	if (TEST_FLAG(pvhtpriv_ap->stbc_cap, STBC_VHT_ENABLE_TX) &&
+	    GET_VHT_CAPABILITY_ELE_RX_STBC(pvhtpriv_sta->vht_cap)) {
+		SET_FLAG(cur_stbc_cap, (STBC_VHT_ENABLE_TX | STBC_VHT_CAP_TX));
+		RTW_INFO("Current STA(%d) VHT STBC = %02X\n", psta->cmn.aid, cur_stbc_cap);
+	}
+	pvhtpriv_sta->stbc_cap = cur_stbc_cap;
+
+#ifdef CONFIG_BEAMFORMING
+	update_sta_vht_info_apmode_bf_cap(padapter, psta);
+#endif
+
+	/* B23 B24 B25 Maximum A-MPDU Length Exponent */
+	pvhtpriv_sta->ampdu_len = GET_VHT_CAPABILITY_ELE_MAX_RXAMPDU_FACTOR(pvhtpriv_sta->vht_cap);
+
+	pcap_mcs = GET_VHT_CAPABILITY_ELE_RX_MCS(pvhtpriv_sta->vht_cap);
+	_rtw_memcpy(pvhtpriv_sta->vht_mcs_map, pcap_mcs, 2);
+	pvhtpriv_sta->vht_highest_rate = rtw_get_vht_highest_rate(pvhtpriv_sta->vht_mcs_map);
+}
+
+void	update_hw_vht_param(_adapter *padapter)
+{
+	struct mlme_priv		*pmlmepriv = &padapter->mlmepriv;
+	struct vht_priv		*pvhtpriv = &pmlmepriv->vhtpriv;
+	struct mlme_ext_priv	*pmlmeext = &padapter->mlmeextpriv;
+	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
+	u8	ht_AMPDU_len;
+
+	ht_AMPDU_len = pmlmeinfo->HT_caps.u.HT_cap_element.AMPDU_para & 0x03;
+
+	if (pvhtpriv->ampdu_len > ht_AMPDU_len)
+		rtw_hal_set_hwreg(padapter, HW_VAR_AMPDU_FACTOR, (u8 *)(&pvhtpriv->ampdu_len));
+}
+
+#ifdef ROKU_PRIVATE
+u8 VHT_get_ss_from_map(u8 *vht_mcs_map)
+{
+	u8 i, j;
+	u8 ss = 0;
+
+	for (i = 0; i < 2; i++) {
+		if (vht_mcs_map[i] != 0xff) {
+			for (j = 0; j < 8; j += 2) {
+				if (((vht_mcs_map[i] >> j) & 0x03) == 0x03)
+					break;
+				ss++;
+			}
+		}
+
+	}
+
+return ss;
+}
+
+void VHT_caps_handler_infra_ap(_adapter *padapter, PNDIS_802_11_VARIABLE_IEs pIE)
+{
+	struct mlme_priv		*pmlmepriv = &padapter->mlmepriv;
+	struct vht_priv_infra_ap	*pvhtpriv = &pmlmepriv->vhtpriv_infra_ap;
+	u8      cur_stbc_cap_infra_ap = 0;
+	u16	cur_beamform_cap_infra_ap = 0;
+	u8	*pcap_mcs;
+	u8	*pcap_mcs_tx;
+	u8	Rx_ss = 0, Tx_ss = 0;
+
+	struct mlme_ext_priv		*pmlmeext = &padapter->mlmeextpriv;
+	struct mlme_ext_info		*pmlmeinfo = &(pmlmeext->mlmext_info);
+
+	if (pIE == NULL)
+		return;
+
+	pmlmeinfo->ht_vht_received |= BIT(1);
+
+	pvhtpriv->ldpc_cap_infra_ap = GET_VHT_CAPABILITY_ELE_RX_LDPC(pIE->data);
+
+	if (GET_VHT_CAPABILITY_ELE_RX_STBC(pIE->data))
+		SET_FLAG(cur_stbc_cap_infra_ap, STBC_VHT_ENABLE_RX);
+	if (GET_VHT_CAPABILITY_ELE_TX_STBC(pIE->data))
+		SET_FLAG(cur_stbc_cap_infra_ap, STBC_VHT_ENABLE_TX);
+	pvhtpriv->stbc_cap_infra_ap = cur_stbc_cap_infra_ap;
+
+	/*store ap info for channel bandwidth*/
+	pvhtpriv->channel_width_infra_ap = GET_VHT_CAPABILITY_ELE_CHL_WIDTH(pIE->data);
+
+	/*check B11: SU Beamformer Capable and B12: SU Beamformee B19: MU Beamformer B20:MU Beamformee*/
+	if (GET_VHT_CAPABILITY_ELE_SU_BFER(pIE->data))
+		SET_FLAG(cur_beamform_cap_infra_ap, BEAMFORMING_VHT_BEAMFORMER_ENABLE);
+	if (GET_VHT_CAPABILITY_ELE_SU_BFEE(pIE->data))
+		SET_FLAG(cur_beamform_cap_infra_ap, BEAMFORMING_VHT_BEAMFORMEE_ENABLE);
+	if (GET_VHT_CAPABILITY_ELE_MU_BFER(pIE->data))
+		SET_FLAG(cur_beamform_cap_infra_ap, BEAMFORMING_VHT_MU_MIMO_AP_ENABLE);
+	if (GET_VHT_CAPABILITY_ELE_MU_BFEE(pIE->data))
+		SET_FLAG(cur_beamform_cap_infra_ap, BEAMFORMING_VHT_MU_MIMO_STA_ENABLE);
+	pvhtpriv->beamform_cap_infra_ap = cur_beamform_cap_infra_ap;
+
+	/*store information about vht_mcs_set*/
+	pcap_mcs = GET_VHT_CAPABILITY_ELE_RX_MCS(pIE->data);
+	pcap_mcs_tx = GET_VHT_CAPABILITY_ELE_TX_MCS(pIE->data);
+	_rtw_memcpy(pvhtpriv->vht_mcs_map_infra_ap, pcap_mcs, 2);
+	_rtw_memcpy(pvhtpriv->vht_mcs_map_tx_infra_ap, pcap_mcs_tx, 2);
+
+	Rx_ss = VHT_get_ss_from_map(pvhtpriv->vht_mcs_map_infra_ap);
+	Tx_ss = VHT_get_ss_from_map(pvhtpriv->vht_mcs_map_tx_infra_ap);
+	if (Rx_ss >= Tx_ss) {
+		pvhtpriv->number_of_streams_infra_ap = Rx_ss;
+	} else{
+		pvhtpriv->number_of_streams_infra_ap = Tx_ss;
+	}
+
+}
+#endif /* ROKU_PRIVATE */
+
+void VHT_caps_handler(_adapter *padapter, PNDIS_802_11_VARIABLE_IEs pIE)
+{
+	struct hal_spec_t *hal_spec = GET_HAL_SPEC(padapter);
+	struct mlme_priv		*pmlmepriv = &padapter->mlmepriv;
+	struct vht_priv		*pvhtpriv = &pmlmepriv->vhtpriv;
+	struct mlme_ext_priv	*pmlmeext = &padapter->mlmeextpriv;
+	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
+	u8	cur_ldpc_cap = 0, cur_stbc_cap = 0, rf_type = RF_1T1R, tx_nss = 0;
+	u16	cur_beamform_cap = 0;
+	u8	*pcap_mcs;
+
+	if (pIE == NULL)
+		return;
+
+	if (pvhtpriv->vht_option == _FALSE)
+		return;
+
+	pmlmeinfo->VHT_enable = 1;
+
+	/* B4 Rx LDPC */
+	if (TEST_FLAG(pvhtpriv->ldpc_cap, LDPC_VHT_ENABLE_TX) &&
+	    GET_VHT_CAPABILITY_ELE_RX_LDPC(pIE->data)) {
+		SET_FLAG(cur_ldpc_cap, (LDPC_VHT_ENABLE_TX | LDPC_VHT_CAP_TX));
+		RTW_INFO("Current VHT LDPC Setting = %02X\n", cur_ldpc_cap);
+	}
+	pvhtpriv->ldpc_cap = cur_ldpc_cap;
+
+	/* B5 Short GI for 80 MHz */
+	pvhtpriv->sgi_80m = (GET_VHT_CAPABILITY_ELE_SHORT_GI80M(pIE->data) & pvhtpriv->sgi_80m) ? _TRUE : _FALSE;
+	/* RTW_INFO("Current ShortGI80MHz = %d\n", pvhtpriv->sgi_80m); */
+
+	/* B8 B9 B10 Rx STBC */
+	if (TEST_FLAG(pvhtpriv->stbc_cap, STBC_VHT_ENABLE_TX) &&
+	    GET_VHT_CAPABILITY_ELE_RX_STBC(pIE->data)) {
+		SET_FLAG(cur_stbc_cap, (STBC_VHT_ENABLE_TX | STBC_VHT_CAP_TX));
+		RTW_INFO("Current VHT STBC Setting = %02X\n", cur_stbc_cap);
+	}
+	pvhtpriv->stbc_cap = cur_stbc_cap;
+#ifdef CONFIG_BEAMFORMING
+#ifdef RTW_BEAMFORMING_VERSION_2
+	/*
+	 * B11 SU Beamformer Capable,
+	 * the target supports Beamformer and we are Beamformee
+	 */
+	if (TEST_FLAG(pvhtpriv->beamform_cap, BEAMFORMING_VHT_BEAMFORMEE_ENABLE)
+	    && GET_VHT_CAPABILITY_ELE_SU_BFER(pIE->data)) {
+		SET_FLAG(cur_beamform_cap, BEAMFORMING_VHT_BEAMFORMEE_ENABLE);
+
+		/* Shift to BEAMFORMING_VHT_BEAMFORMEE_STS_CAP */
+		SET_FLAG(cur_beamform_cap, GET_VHT_CAPABILITY_ELE_SU_BFEE_STS_CAP(pIE->data) << 8);
+
+		/*
+		 * B19 MU Beamformer Capable,
+		 * the target supports Beamformer and we are Beamformee
+		 */
+		if (TEST_FLAG(pvhtpriv->beamform_cap, BEAMFORMING_VHT_MU_MIMO_STA_ENABLE)
+		    && GET_VHT_CAPABILITY_ELE_MU_BFER(pIE->data))
+			SET_FLAG(cur_beamform_cap, BEAMFORMING_VHT_MU_MIMO_STA_ENABLE);
+	}
+
+	/*
+	 * B12 SU Beamformee Capable,
+	 * the target supports Beamformee and we are Beamformer
+	 */
+	if (TEST_FLAG(pvhtpriv->beamform_cap, BEAMFORMING_VHT_BEAMFORMER_ENABLE)
+	    && GET_VHT_CAPABILITY_ELE_SU_BFEE(pIE->data)) {
+		SET_FLAG(cur_beamform_cap, BEAMFORMING_VHT_BEAMFORMER_ENABLE);
+
+		/* Shit to BEAMFORMING_VHT_BEAMFORMER_SOUND_DIM */
+		SET_FLAG(cur_beamform_cap, GET_VHT_CAPABILITY_ELE_SU_BFER_SOUND_DIM_NUM(pIE->data) << 12);
+
+		/*
+		 * B20 MU Beamformee Capable,
+		 * the target supports Beamformee and we are Beamformer
+		 */
+		if (TEST_FLAG(pvhtpriv->beamform_cap, BEAMFORMING_VHT_MU_MIMO_AP_ENABLE)
+		    && GET_VHT_CAPABILITY_ELE_MU_BFEE(pIE->data))
+			SET_FLAG(cur_beamform_cap, BEAMFORMING_VHT_MU_MIMO_AP_ENABLE);
+	}
+
+	pvhtpriv->beamform_cap = cur_beamform_cap;
+	RTW_INFO("Current VHT Beamforming Setting=0x%04X\n", cur_beamform_cap);
+#else /* !RTW_BEAMFORMING_VERSION_2 */
+	/* B11 SU Beamformer Capable, the target supports Beamformer and we are Beamformee */
+	if (TEST_FLAG(pvhtpriv->beamform_cap, BEAMFORMING_VHT_BEAMFORMER_ENABLE) &&
+	    GET_VHT_CAPABILITY_ELE_SU_BFEE(pIE->data)) {
+		SET_FLAG(cur_beamform_cap, BEAMFORMING_VHT_BEAMFORMEE_ENABLE);
+		/*Shift to BEAMFORMING_VHT_BEAMFORMER_STS_CAP*/
+		SET_FLAG(cur_beamform_cap, GET_VHT_CAPABILITY_ELE_SU_BFEE_STS_CAP(pIE->data) << 8);
+	}
+
+	/* B12 SU Beamformee Capable, the target supports Beamformee and we are Beamformer */
+	if (TEST_FLAG(pvhtpriv->beamform_cap, BEAMFORMING_VHT_BEAMFORMEE_ENABLE) &&
+	    GET_VHT_CAPABILITY_ELE_SU_BFER(pIE->data)) {
+		SET_FLAG(cur_beamform_cap, BEAMFORMING_VHT_BEAMFORMER_ENABLE);
+		/*Shit to BEAMFORMING_VHT_BEAMFORMEE_SOUND_DIM*/
+		SET_FLAG(cur_beamform_cap, GET_VHT_CAPABILITY_ELE_SU_BFER_SOUND_DIM_NUM(pIE->data) << 12);
+
+	}
+	pvhtpriv->beamform_cap = cur_beamform_cap;
+	if (cur_beamform_cap)
+		RTW_INFO("Current VHT Beamforming Setting = %02X\n", cur_beamform_cap);
+#endif /* !RTW_BEAMFORMING_VERSION_2 */
+#endif /* CONFIG_BEAMFORMING */
+	/* B23 B24 B25 Maximum A-MPDU Length Exponent */
+	pvhtpriv->ampdu_len = GET_VHT_CAPABILITY_ELE_MAX_RXAMPDU_FACTOR(pIE->data);
+
+	pcap_mcs = GET_VHT_CAPABILITY_ELE_RX_MCS(pIE->data);
+	rtw_hal_get_hwreg(padapter, HW_VAR_RF_TYPE, (u8 *)(&rf_type));
+	tx_nss = rtw_min(rf_type_to_rf_tx_cnt(rf_type), hal_spec->tx_nss_num);
+	rtw_vht_nss_to_mcsmap(tx_nss, pvhtpriv->vht_mcs_map, pcap_mcs);
+	pvhtpriv->vht_highest_rate = rtw_get_vht_highest_rate(pvhtpriv->vht_mcs_map);
+}
+
+void VHT_operation_handler(_adapter *padapter, PNDIS_802_11_VARIABLE_IEs pIE)
+{
+	struct mlme_priv		*pmlmepriv = &padapter->mlmepriv;
+	struct vht_priv		*pvhtpriv = &pmlmepriv->vhtpriv;
+
+	if (pIE == NULL)
+		return;
+
+	if (pvhtpriv->vht_option == _FALSE)
+		return;
+}
+
+void rtw_process_vht_op_mode_notify(_adapter *padapter, u8 *pframe, PVOID sta)
+{
+	struct sta_info		*psta = (struct sta_info *)sta;
+	struct mlme_priv		*pmlmepriv = &padapter->mlmepriv;
+	struct vht_priv		*pvhtpriv = &pmlmepriv->vhtpriv;
+	struct registry_priv *regsty = adapter_to_regsty(padapter);
+	u8	target_bw;
+	u8	target_rxss, current_rxss;
+	u8	update_ra = _FALSE;
+	u8 tx_nss = 0, rf_type = RF_1T1R;
+	struct hal_spec_t *hal_spec = GET_HAL_SPEC(padapter);
+
+	if (pvhtpriv->vht_option == _FALSE)
+		return;
+
+	target_bw = GET_VHT_OPERATING_MODE_FIELD_CHNL_WIDTH(pframe);
+
+	rtw_hal_get_hwreg(padapter, HW_VAR_RF_TYPE, (u8 *)(&rf_type));
+	tx_nss = rtw_min(rf_type_to_rf_tx_cnt(rf_type), hal_spec->tx_nss_num);
+	target_rxss = rtw_min(tx_nss, (GET_VHT_OPERATING_MODE_FIELD_RX_NSS(pframe) + 1));
+
+	if (target_bw != psta->cmn.bw_mode) {
+		if (hal_is_bw_support(padapter, target_bw)
+		    && REGSTY_IS_BW_5G_SUPPORT(regsty, target_bw)
+		   ) {
+			update_ra = _TRUE;
+			psta->cmn.bw_mode = target_bw;
+		}
+	}
+
+	current_rxss = rtw_vht_mcsmap_to_nss(psta->vhtpriv.vht_mcs_map);
+	if (target_rxss != current_rxss) {
+		u8	vht_mcs_map[2] = {};
+
+		update_ra = _TRUE;
+
+		rtw_vht_nss_to_mcsmap(target_rxss, vht_mcs_map, psta->vhtpriv.vht_mcs_map);
+		_rtw_memcpy(psta->vhtpriv.vht_mcs_map, vht_mcs_map, 2);
+
+		rtw_hal_update_sta_ra_info(padapter, psta);
+	}
+
+	if (update_ra)
+		rtw_dm_ra_mask_wk_cmd(padapter, (u8 *)psta);
+}
+
+u32	rtw_build_vht_operation_ie(_adapter *padapter, u8 *pbuf, u8 channel)
+{
+	struct registry_priv	*pregistrypriv = &padapter->registrypriv;
+	struct mlme_priv		*pmlmepriv = &padapter->mlmepriv;
+	struct vht_priv		*pvhtpriv = &pmlmepriv->vhtpriv;
+	/* struct mlme_ext_priv	*pmlmeext = &padapter->mlmeextpriv; */
+	u8	ChnlWidth, center_freq, bw_mode;
+	u32	len = 0;
+	u8	operation[5];
+
+	_rtw_memset(operation, 0, 5);
+
+	bw_mode = REGSTY_BW_5G(pregistrypriv); /* TODO: control op bw with other info */
+
+	if (hal_chk_bw_cap(padapter, BW_CAP_80M | BW_CAP_160M)
+	    && REGSTY_BW_5G(pregistrypriv) >= CHANNEL_WIDTH_80
+	   ) {
+		center_freq = rtw_get_center_ch(channel, bw_mode, HAL_PRIME_CHNL_OFFSET_LOWER);
+		ChnlWidth = 1;
+	} else {
+		center_freq = 0;
+		ChnlWidth = 0;
+	}
+
+
+	SET_VHT_OPERATION_ELE_CHL_WIDTH(operation, ChnlWidth);
+	/* center frequency */
+	SET_VHT_OPERATION_ELE_CHL_CENTER_FREQ1(operation, center_freq);/* Todo: need to set correct center channel */
+	SET_VHT_OPERATION_ELE_CHL_CENTER_FREQ2(operation, 0);
+
+	_rtw_memcpy(operation + 3, pvhtpriv->vht_mcs_map, 2);
+
+	rtw_set_ie(pbuf, EID_VHTOperation, 5, operation, &len);
+
+	return len;
+}
+
+u32	rtw_build_vht_op_mode_notify_ie(_adapter *padapter, u8 *pbuf, u8 bw)
+{
+	/* struct registry_priv *pregistrypriv = &padapter->registrypriv; */
+	struct mlme_priv	*pmlmepriv = &padapter->mlmepriv;
+	struct vht_priv	*pvhtpriv = &pmlmepriv->vhtpriv;
+	u32	len = 0;
+	u8	opmode = 0;
+	u8	chnl_width, rx_nss;
+
+	chnl_width = bw;
+	rx_nss = rtw_vht_mcsmap_to_nss(pvhtpriv->vht_mcs_map);
+
+	SET_VHT_OPERATING_MODE_FIELD_CHNL_WIDTH(&opmode, chnl_width);
+	SET_VHT_OPERATING_MODE_FIELD_RX_NSS(&opmode, (rx_nss - 1));
+	SET_VHT_OPERATING_MODE_FIELD_RX_NSS_TYPE(&opmode, 0); /* Todo */
+
+	pvhtpriv->vht_op_mode_notify = opmode;
+
+	pbuf = rtw_set_ie(pbuf, EID_OpModeNotification, 1, &opmode, &len);
+
+	return len;
+}
+
+u32	rtw_build_vht_cap_ie(_adapter *padapter, u8 *pbuf)
+{
+	u8	bw, rf_num, rx_stbc_nss = 0;
+	u16	HighestRate;
+	u8	*pcap, *pcap_mcs;
+	u32	len = 0;
+	u32 rx_packet_offset, max_recvbuf_sz;
+	struct registry_priv *pregistrypriv = &padapter->registrypriv;
+	struct mlme_priv	*pmlmepriv = &padapter->mlmepriv;
+	struct vht_priv	*pvhtpriv = &pmlmepriv->vhtpriv;
+	struct mlme_ext_priv	*pmlmeext = &padapter->mlmeextpriv;
+	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
+
+	pcap = pvhtpriv->vht_cap;
+	_rtw_memset(pcap, 0, 32);
+
+	/* B0 B1 Maximum MPDU Length */
+	rtw_hal_get_def_var(padapter, HAL_DEF_RX_PACKET_OFFSET, &rx_packet_offset);
+	rtw_hal_get_def_var(padapter, HAL_DEF_MAX_RECVBUF_SZ, &max_recvbuf_sz);
+
+	RTW_DBG("%s, line%d, Available RX buf size = %d bytes\n", __FUNCTION__, __LINE__, max_recvbuf_sz - rx_packet_offset);
+
+	if ((max_recvbuf_sz - rx_packet_offset) >= 11454) {
+		SET_VHT_CAPABILITY_ELE_MAX_MPDU_LENGTH(pcap, 2);
+		RTW_INFO("%s, line%d, Set MAX MPDU len = 11454 bytes\n", __FUNCTION__, __LINE__);
+	} else if ((max_recvbuf_sz - rx_packet_offset) >= 7991) {
+		SET_VHT_CAPABILITY_ELE_MAX_MPDU_LENGTH(pcap, 1);
+		RTW_INFO("%s, line%d, Set MAX MPDU len = 7991 bytes\n", __FUNCTION__, __LINE__);
+	} else if ((max_recvbuf_sz - rx_packet_offset) >= 3895) {
+		SET_VHT_CAPABILITY_ELE_MAX_MPDU_LENGTH(pcap, 0);
+		RTW_INFO("%s, line%d, Set MAX MPDU len = 3895 bytes\n", __FUNCTION__, __LINE__);
+	} else
+		RTW_ERR("%s, line%d, Error!! Available RX buf size < 3895 bytes\n", __FUNCTION__, __LINE__);
+
+	/* B2 B3 Supported Channel Width Set */
+	if (hal_chk_bw_cap(padapter, BW_CAP_160M) && REGSTY_IS_BW_5G_SUPPORT(pregistrypriv, CHANNEL_WIDTH_160)) {
+		if (hal_chk_bw_cap(padapter, BW_CAP_80_80M) && REGSTY_IS_BW_5G_SUPPORT(pregistrypriv, CHANNEL_WIDTH_80_80))
+			SET_VHT_CAPABILITY_ELE_CHL_WIDTH(pcap, 2);
+		else
+			SET_VHT_CAPABILITY_ELE_CHL_WIDTH(pcap, 1);
+	} else
+		SET_VHT_CAPABILITY_ELE_CHL_WIDTH(pcap, 0);
+
+	/* B4 Rx LDPC */
+	if (TEST_FLAG(pvhtpriv->ldpc_cap, LDPC_VHT_ENABLE_RX)) {
+		SET_VHT_CAPABILITY_ELE_RX_LDPC(pcap, 1);
+		RTW_INFO("[VHT] Declare supporting RX LDPC\n");
+	}
+
+	/* B5 ShortGI for 80MHz */
+	SET_VHT_CAPABILITY_ELE_SHORT_GI80M(pcap, pvhtpriv->sgi_80m ? 1 : 0); /* We can receive Short GI of 80M */
+	if (pvhtpriv->sgi_80m)
+		RTW_INFO("[VHT] Declare supporting SGI 80MHz\n");
+
+	/* B6 ShortGI for 160MHz */
+	/* SET_VHT_CAPABILITY_ELE_SHORT_GI160M(pcap, pvhtpriv->sgi_80m? 1 : 0); */
+
+	/* B7 Tx STBC */
+	if (TEST_FLAG(pvhtpriv->stbc_cap, STBC_VHT_ENABLE_TX)) {
+		SET_VHT_CAPABILITY_ELE_TX_STBC(pcap, 1);
+		RTW_INFO("[VHT] Declare supporting TX STBC\n");
+	}
+
+	/* B8 B9 B10 Rx STBC */
+	if (TEST_FLAG(pvhtpriv->stbc_cap, STBC_VHT_ENABLE_RX)) {
+		rtw_hal_get_def_var(padapter, HAL_DEF_RX_STBC, (u8 *)(&rx_stbc_nss));
+
+		SET_VHT_CAPABILITY_ELE_RX_STBC(pcap, rx_stbc_nss);
+		RTW_INFO("[VHT] Declare supporting RX STBC = %d\n", rx_stbc_nss);
+	}
+	#ifdef CONFIG_BEAMFORMING
+	/* B11 SU Beamformer Capable */
+	if (TEST_FLAG(pvhtpriv->beamform_cap, BEAMFORMING_VHT_BEAMFORMER_ENABLE)) {
+		SET_VHT_CAPABILITY_ELE_SU_BFER(pcap, 1);
+		RTW_INFO("[VHT] Declare supporting SU Bfer\n");
+		/* B16 17 18 Number of Sounding Dimensions */
+		rtw_hal_get_def_var(padapter, HAL_DEF_BEAMFORMER_CAP, (u8 *)&rf_num);
+		SET_VHT_CAPABILITY_ELE_SOUNDING_DIMENSIONS(pcap, rf_num);
+		/* B19 MU Beamformer Capable */
+		if (TEST_FLAG(pvhtpriv->beamform_cap, BEAMFORMING_VHT_MU_MIMO_AP_ENABLE)) {
+			SET_VHT_CAPABILITY_ELE_MU_BFER(pcap, 1);
+			RTW_INFO("[VHT] Declare supporting MU Bfer\n");
+		}
+	}
+
+	/* B12 SU Beamformee Capable */
+	if (TEST_FLAG(pvhtpriv->beamform_cap, BEAMFORMING_VHT_BEAMFORMEE_ENABLE)) {
+		SET_VHT_CAPABILITY_ELE_SU_BFEE(pcap, 1);
+		RTW_INFO("[VHT] Declare supporting SU Bfee\n");
+
+		rtw_hal_get_def_var(padapter, HAL_DEF_BEAMFORMEE_CAP, (u8 *)&rf_num);
+
+		/* IOT action suggested by Yu Chen 2017/3/3 */
+#ifdef CONFIG_80211AC_VHT
+		if ((pmlmeinfo->assoc_AP_vendor == HT_IOT_PEER_BROADCOM) &&
+			!pvhtpriv->ap_is_mu_bfer)
+			rf_num = (rf_num >= 2 ? 2 : rf_num);
+#endif
+		/* B13 14 15 Compressed Steering Number of Beamformer Antennas Supported */
+		SET_VHT_CAPABILITY_ELE_BFER_ANT_SUPP(pcap, rf_num);
+		/* B20 SU Beamformee Capable */
+		if (TEST_FLAG(pvhtpriv->beamform_cap, BEAMFORMING_VHT_MU_MIMO_STA_ENABLE)) {
+			SET_VHT_CAPABILITY_ELE_MU_BFEE(pcap, 1);
+			RTW_INFO("[VHT] Declare supporting MU Bfee\n");
+		}
+	}
+	#endif/*CONFIG_BEAMFORMING*/
+
+	/* B21 VHT TXOP PS */
+	SET_VHT_CAPABILITY_ELE_TXOP_PS(pcap, 0);
+	/* B22 +HTC-VHT Capable */
+	SET_VHT_CAPABILITY_ELE_HTC_VHT(pcap, 1);
+	/* B23 24 25 Maximum A-MPDU Length Exponent */
+	if (pregistrypriv->ampdu_factor != 0xFE)
+		SET_VHT_CAPABILITY_ELE_MAX_RXAMPDU_FACTOR(pcap, pregistrypriv->ampdu_factor);
+	else
+		SET_VHT_CAPABILITY_ELE_MAX_RXAMPDU_FACTOR(pcap, 7);
+	/* B26 27 VHT Link Adaptation Capable */
+	SET_VHT_CAPABILITY_ELE_LINK_ADAPTION(pcap, 0);
+
+	pcap_mcs = GET_VHT_CAPABILITY_ELE_RX_MCS(pcap);
+	_rtw_memcpy(pcap_mcs, pvhtpriv->vht_mcs_map, 2);
+
+	pcap_mcs = GET_VHT_CAPABILITY_ELE_TX_MCS(pcap);
+	_rtw_memcpy(pcap_mcs, pvhtpriv->vht_mcs_map, 2);
+
+	/* find the largest bw supported by both registry and hal */
+	bw = hal_largest_bw(padapter, REGSTY_BW_5G(pregistrypriv));
+
+	HighestRate = VHT_MCS_DATA_RATE[bw][pvhtpriv->sgi_80m][((pvhtpriv->vht_highest_rate - MGN_VHT1SS_MCS0) & 0x3f)];
+	HighestRate = (HighestRate + 1) >> 1;
+
+	SET_VHT_CAPABILITY_ELE_MCS_RX_HIGHEST_RATE(pcap, HighestRate); /* indicate we support highest rx rate is 600Mbps. */
+	SET_VHT_CAPABILITY_ELE_MCS_TX_HIGHEST_RATE(pcap, HighestRate); /* indicate we support highest tx rate is 600Mbps. */
+
+	pbuf = rtw_set_ie(pbuf, EID_VHTCapability, 12, pcap, &len);
+
+	return len;
+}
+
+u32 rtw_restructure_vht_ie(_adapter *padapter, u8 *in_ie, u8 *out_ie, uint in_len, uint *pout_len)
+{
+	struct rf_ctl_t *rfctl = adapter_to_rfctl(padapter);
+	RT_CHANNEL_INFO *chset = rfctl->channel_set;
+	u32	ielen;
+	u8 max_bw;
+	u8 oper_ch, oper_bw = CHANNEL_WIDTH_20, oper_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
+	u8 *out_vht_op_ie, *ht_op_ie, *vht_cap_ie, *vht_op_ie;
+	struct registry_priv *pregistrypriv = &padapter->registrypriv;
+	struct mlme_priv	*pmlmepriv = &padapter->mlmepriv;
+	struct vht_priv	*pvhtpriv = &pmlmepriv->vhtpriv;
+
+	rtw_vht_use_default_setting(padapter);
+
+	ht_op_ie = rtw_get_ie(in_ie + 12, WLAN_EID_HT_OPERATION, &ielen, in_len - 12);
+	if (!ht_op_ie || ielen != HT_OP_IE_LEN)
+		goto exit;
+	vht_cap_ie = rtw_get_ie(in_ie + 12, EID_VHTCapability, &ielen, in_len - 12);
+	if (!vht_cap_ie || ielen != VHT_CAP_IE_LEN)
+		goto exit;
+	vht_op_ie = rtw_get_ie(in_ie + 12, EID_VHTOperation, &ielen, in_len - 12);
+	if (!vht_op_ie || ielen != VHT_OP_IE_LEN)
+		goto exit;
+
+	/* VHT Capabilities element */
+	*pout_len += rtw_build_vht_cap_ie(padapter, out_ie + *pout_len);
+
+
+	/* VHT Operation element */
+	out_vht_op_ie = out_ie + *pout_len;
+	rtw_set_ie(out_vht_op_ie, EID_VHTOperation, VHT_OP_IE_LEN, vht_op_ie + 2 , pout_len);
+
+	/* get primary channel from HT_OP_IE */
+	oper_ch = GET_HT_OP_ELE_PRI_CHL(ht_op_ie + 2);
+
+	/* find the largest bw supported by both registry and hal */
+	max_bw = hal_largest_bw(padapter, REGSTY_BW_5G(pregistrypriv));
+
+	if (max_bw >= CHANNEL_WIDTH_40) {
+		/* get bw offset form HT_OP_IE */
+		if (GET_HT_OP_ELE_STA_CHL_WIDTH(ht_op_ie + 2)) {
+			switch (GET_HT_OP_ELE_2ND_CHL_OFFSET(ht_op_ie + 2)) {
+			case SCA:
+				oper_bw = CHANNEL_WIDTH_40;
+				oper_offset = HAL_PRIME_CHNL_OFFSET_LOWER;
+				break;
+			case SCB:
+				oper_bw = CHANNEL_WIDTH_40;
+				oper_offset = HAL_PRIME_CHNL_OFFSET_UPPER;
+				break;
+			}
+		}
+
+		if (oper_bw == CHANNEL_WIDTH_40) {
+			switch (GET_VHT_OPERATION_ELE_CHL_WIDTH(vht_op_ie + 2)) {
+			case 1: /* 80MHz */
+			case 2: /* 160MHz */
+			case 3: /* 80+80 */
+				oper_bw = CHANNEL_WIDTH_80; /* only support up to 80MHz for now */
+				break;
+			}
+
+			oper_bw = rtw_min(oper_bw, max_bw);
+
+			/* try downgrage bw to fit in channel plan setting */
+			while (!rtw_chset_is_chbw_valid(chset, oper_ch, oper_bw, oper_offset)
+				|| (IS_DFS_SLAVE_WITH_RD(rfctl)
+					&& !rtw_odm_dfs_domain_unknown(rfctl_to_dvobj(rfctl))
+					&& rtw_chset_is_chbw_non_ocp(chset, oper_ch, oper_bw, oper_offset))
+			) {
+				oper_bw--;
+				if (oper_bw == CHANNEL_WIDTH_20) {
+					oper_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
+					break;
+				}
+			}
+		}
+	}
+
+	rtw_warn_on(!rtw_chset_is_chbw_valid(chset, oper_ch, oper_bw, oper_offset));
+	if (IS_DFS_SLAVE_WITH_RD(rfctl) && !rtw_odm_dfs_domain_unknown(rfctl_to_dvobj(rfctl)))
+		rtw_warn_on(rtw_chset_is_chbw_non_ocp(chset, oper_ch, oper_bw, oper_offset));
+
+	/* update VHT_OP_IE */
+	if (oper_bw < CHANNEL_WIDTH_80) {
+		SET_VHT_OPERATION_ELE_CHL_WIDTH(out_vht_op_ie + 2, 0);
+		SET_VHT_OPERATION_ELE_CHL_CENTER_FREQ1(out_vht_op_ie + 2, 0);
+		SET_VHT_OPERATION_ELE_CHL_CENTER_FREQ2(out_vht_op_ie + 2, 0);
+	} else if (oper_bw == CHANNEL_WIDTH_80) {
+		u8 cch = rtw_get_center_ch(oper_ch, oper_bw, oper_offset);
+
+		SET_VHT_OPERATION_ELE_CHL_WIDTH(out_vht_op_ie + 2, 1);
+		SET_VHT_OPERATION_ELE_CHL_CENTER_FREQ1(out_vht_op_ie + 2, cch);
+		SET_VHT_OPERATION_ELE_CHL_CENTER_FREQ2(out_vht_op_ie + 2, 0);
+	} else {
+		RTW_ERR(FUNC_ADPT_FMT" unsupported BW:%u\n", FUNC_ADPT_ARG(padapter), oper_bw);
+		rtw_warn_on(1);
+	}
+
+	/* Operating Mode Notification element */
+	*pout_len += rtw_build_vht_op_mode_notify_ie(padapter, out_ie + *pout_len, oper_bw);
+
+	pvhtpriv->vht_option = _TRUE;
+
+exit:
+	return pvhtpriv->vht_option;
+
+}
+
+void VHTOnAssocRsp(_adapter *padapter)
+{
+	struct mlme_priv		*pmlmepriv = &padapter->mlmepriv;
+	struct vht_priv		*pvhtpriv = &pmlmepriv->vhtpriv;
+	struct mlme_ext_priv	*pmlmeext = &padapter->mlmeextpriv;
+	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
+	u8	ht_AMPDU_len;
+
+	RTW_INFO("%s\n", __FUNCTION__);
+
+	if (!pmlmeinfo->HT_enable)
+		return;
+
+	if (!pmlmeinfo->VHT_enable)
+		return;
+
+	ht_AMPDU_len = pmlmeinfo->HT_caps.u.HT_cap_element.AMPDU_para & 0x03;
+
+	if (pvhtpriv->ampdu_len > ht_AMPDU_len)
+		rtw_hal_set_hwreg(padapter, HW_VAR_AMPDU_FACTOR, (u8 *)(&pvhtpriv->ampdu_len));
+
+	rtw_hal_set_hwreg(padapter, HW_VAR_AMPDU_MAX_TIME, (u8 *)(&pvhtpriv->vht_highest_rate));
+}
+
+void rtw_vht_ies_attach(_adapter *padapter, WLAN_BSSID_EX *pnetwork)
+{
+	struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
+	u8 cap_len, operation_len;
+	uint len = 0;
+	sint ie_len = 0;
+	u8 *p = NULL;
+
+	p = rtw_get_ie(pnetwork->IEs + _BEACON_IE_OFFSET_, EID_VHTCapability, &ie_len,
+			(pnetwork->IELength - _BEACON_IE_OFFSET_));
+	if (p && ie_len > 0)
+		return;
+
+	rtw_vht_use_default_setting(padapter);
+
+	/* VHT Operation mode notifiy bit in Extended IE (127) */
+	SET_EXT_CAPABILITY_ELE_OP_MODE_NOTIF(pmlmepriv->ext_capab_ie_data, 1);
+	pmlmepriv->ext_capab_ie_len = 10;
+	rtw_set_ie(pnetwork->IEs + pnetwork->IELength, EID_EXTCapability, 8, pmlmepriv->ext_capab_ie_data, &len);
+	pnetwork->IELength += pmlmepriv->ext_capab_ie_len;
+
+	/* VHT Capabilities element */
+	cap_len = rtw_build_vht_cap_ie(padapter, pnetwork->IEs + pnetwork->IELength);
+	pnetwork->IELength += cap_len;
+
+	/* VHT Operation element */
+	operation_len = rtw_build_vht_operation_ie(padapter, pnetwork->IEs + pnetwork->IELength,
+										pnetwork->Configuration.DSConfig);
+	pnetwork->IELength += operation_len;
+
+	rtw_check_for_vht20(padapter, pnetwork->IEs + _BEACON_IE_OFFSET_, pnetwork->IELength - _BEACON_IE_OFFSET_);
+
+	pmlmepriv->vhtpriv.vht_option = _TRUE;
+}
+
+void rtw_vht_ies_detach(_adapter *padapter, WLAN_BSSID_EX *pnetwork)
+{
+	struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
+
+	rtw_remove_bcn_ie(padapter, pnetwork, EID_EXTCapability);
+	rtw_remove_bcn_ie(padapter, pnetwork, EID_VHTCapability);
+	rtw_remove_bcn_ie(padapter, pnetwork, EID_VHTOperation);
+
+	pmlmepriv->vhtpriv.vht_option = _FALSE;
+}
+
+void rtw_check_for_vht20(_adapter *adapter, u8 *ies, int ies_len)
+{
+	u8 ht_ch, ht_bw, ht_offset;
+	u8 vht_ch, vht_bw, vht_offset;
+
+	rtw_ies_get_chbw(ies, ies_len, &ht_ch, &ht_bw, &ht_offset, 1, 0);
+	rtw_ies_get_chbw(ies, ies_len, &vht_ch, &vht_bw, &vht_offset, 1, 1);
+
+	if (ht_bw == CHANNEL_WIDTH_20 && vht_bw >= CHANNEL_WIDTH_80) {
+		u8 *vht_op_ie;
+		int vht_op_ielen;
+
+		RTW_INFO(FUNC_ADPT_FMT" vht80 is not allowed without ht40\n", FUNC_ADPT_ARG(adapter));
+		vht_op_ie = rtw_get_ie(ies, EID_VHTOperation, &vht_op_ielen, ies_len);
+		if (vht_op_ie && vht_op_ielen) {
+			RTW_INFO(FUNC_ADPT_FMT" switch to vht20\n", FUNC_ADPT_ARG(adapter));
+			SET_VHT_OPERATION_ELE_CHL_WIDTH(vht_op_ie + 2, 0);
+			SET_VHT_OPERATION_ELE_CHL_CENTER_FREQ1(vht_op_ie + 2, 0);
+			SET_VHT_OPERATION_ELE_CHL_CENTER_FREQ2(vht_op_ie + 2, 0);
+		}
+	}
+}
+#endif /* CONFIG_80211AC_VHT */
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/core/rtw_wlan_util.c linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/core/rtw_wlan_util.c
--- linux-5.6.3/3rdparty/rtl8821ce/core/rtw_wlan_util.c	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/core/rtw_wlan_util.c	2020-04-10 16:35:06.780658387 +0300
@@ -0,0 +1,4941 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#define _RTW_WLAN_UTIL_C_
+
+#include <drv_types.h>
+#include <hal_data.h>
+
+#if defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN)
+	#include <linux/inetdevice.h>
+	#define ETH_TYPE_OFFSET	12
+	#define PROTOCOL_OFFSET	23
+	#define IP_OFFSET	30
+	#define IPv6_OFFSET	38
+	#define IPv6_PROTOCOL_OFFSET	20
+#endif
+
+unsigned char ARTHEROS_OUI1[] = {0x00, 0x03, 0x7f};
+unsigned char ARTHEROS_OUI2[] = {0x00, 0x13, 0x74};
+
+unsigned char BROADCOM_OUI1[] = {0x00, 0x10, 0x18};
+unsigned char BROADCOM_OUI2[] = {0x00, 0x0a, 0xf7};
+unsigned char BROADCOM_OUI3[] = {0x00, 0x05, 0xb5};
+
+
+unsigned char CISCO_OUI[] = {0x00, 0x40, 0x96};
+unsigned char MARVELL_OUI[] = {0x00, 0x50, 0x43};
+unsigned char RALINK_OUI[] = {0x00, 0x0c, 0x43};
+unsigned char REALTEK_OUI[] = {0x00, 0xe0, 0x4c};
+unsigned char AIRGOCAP_OUI[] = {0x00, 0x0a, 0xf5};
+
+unsigned char REALTEK_96B_IE[] = {0x00, 0xe0, 0x4c, 0x02, 0x01, 0x20};
+
+extern unsigned char RTW_WPA_OUI[];
+extern unsigned char WPA_TKIP_CIPHER[4];
+extern unsigned char RSN_TKIP_CIPHER[4];
+
+#define R2T_PHY_DELAY	(0)
+
+/* #define WAIT_FOR_BCN_TO_MIN	(3000) */
+#define WAIT_FOR_BCN_TO_MIN	(6000)
+#define WAIT_FOR_BCN_TO_MAX	(20000)
+
+static u8 rtw_basic_rate_cck[4] = {
+	IEEE80211_CCK_RATE_1MB | IEEE80211_BASIC_RATE_MASK, IEEE80211_CCK_RATE_2MB | IEEE80211_BASIC_RATE_MASK,
+	IEEE80211_CCK_RATE_5MB | IEEE80211_BASIC_RATE_MASK, IEEE80211_CCK_RATE_11MB | IEEE80211_BASIC_RATE_MASK
+};
+
+static u8 rtw_basic_rate_ofdm[3] = {
+	IEEE80211_OFDM_RATE_6MB | IEEE80211_BASIC_RATE_MASK, IEEE80211_OFDM_RATE_12MB | IEEE80211_BASIC_RATE_MASK,
+	IEEE80211_OFDM_RATE_24MB | IEEE80211_BASIC_RATE_MASK
+};
+
+static u8 rtw_basic_rate_mix[7] = {
+	IEEE80211_CCK_RATE_1MB | IEEE80211_BASIC_RATE_MASK, IEEE80211_CCK_RATE_2MB | IEEE80211_BASIC_RATE_MASK,
+	IEEE80211_CCK_RATE_5MB | IEEE80211_BASIC_RATE_MASK, IEEE80211_CCK_RATE_11MB | IEEE80211_BASIC_RATE_MASK,
+	IEEE80211_OFDM_RATE_6MB | IEEE80211_BASIC_RATE_MASK, IEEE80211_OFDM_RATE_12MB | IEEE80211_BASIC_RATE_MASK,
+	IEEE80211_OFDM_RATE_24MB | IEEE80211_BASIC_RATE_MASK
+};
+
+/* test if rate is defined in rtw_basic_rate_cck */
+bool rtw_is_basic_rate_cck(u8 rate)
+{
+	int i;
+
+	for (i = 0; i < 4; i++)
+		if ((rtw_basic_rate_cck[i] & 0x7F) == (rate & 0x7F))
+			return 1;
+	return 0;
+}
+
+/* test if rate is defined in rtw_basic_rate_ofdm */
+bool rtw_is_basic_rate_ofdm(u8 rate)
+{
+	int i;
+
+	for (i = 0; i < 3; i++)
+		if ((rtw_basic_rate_ofdm[i] & 0x7F) == (rate & 0x7F))
+			return 1;
+	return 0;
+}
+
+/* test if rate is defined in rtw_basic_rate_mix */
+bool rtw_is_basic_rate_mix(u8 rate)
+{
+	int i;
+
+	for (i = 0; i < 7; i++)
+		if ((rtw_basic_rate_mix[i] & 0x7F) == (rate & 0x7F))
+			return 1;
+	return 0;
+}
+#ifdef CONFIG_BCN_CNT_CONFIRM_HDL
+int new_bcn_max = 3;
+#endif
+int cckrates_included(unsigned char *rate, int ratelen)
+{
+	int	i;
+
+	for (i = 0; i < ratelen; i++) {
+		if ((((rate[i]) & 0x7f) == 2)	|| (((rate[i]) & 0x7f) == 4) ||
+		    (((rate[i]) & 0x7f) == 11)  || (((rate[i]) & 0x7f) == 22))
+			return _TRUE;
+	}
+
+	return _FALSE;
+
+}
+
+int cckratesonly_included(unsigned char *rate, int ratelen)
+{
+	int	i;
+
+	for (i = 0; i < ratelen; i++) {
+		if ((((rate[i]) & 0x7f) != 2) && (((rate[i]) & 0x7f) != 4) &&
+		    (((rate[i]) & 0x7f) != 11)  && (((rate[i]) & 0x7f) != 22))
+			return _FALSE;
+	}
+
+	return _TRUE;
+}
+
+s8 rtw_get_sta_rx_nss(_adapter *adapter, struct sta_info *psta)
+{
+	struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter);
+	u8 rf_type = RF_1T1R, custom_rf_type;
+	s8 nss = 1;
+
+	if (!psta)
+		return nss;
+
+	custom_rf_type = adapter->registrypriv.rf_config;
+	rtw_hal_get_hwreg(adapter, HW_VAR_RF_TYPE, (u8 *)(&rf_type));
+	if (RF_TYPE_VALID(custom_rf_type))
+		rf_type = custom_rf_type;
+
+	nss = rtw_min(rf_type_to_rf_rx_cnt(rf_type), hal_spec->rx_nss_num);
+
+#ifdef CONFIG_80211N_HT
+	#ifdef CONFIG_80211AC_VHT
+	if (psta->vhtpriv.vht_option)
+		nss = rtw_min(nss, rtw_vht_mcsmap_to_nss(psta->vhtpriv.vht_mcs_map));
+	else
+	#endif /* CONFIG_80211AC_VHT */
+	if (psta->htpriv.ht_option)
+		nss = rtw_min(nss, rtw_ht_mcsset_to_nss(psta->htpriv.ht_cap.supp_mcs_set));
+#endif /*CONFIG_80211N_HT*/
+	RTW_INFO("%s: %d SS\n", __func__, nss);
+	return nss;
+}
+
+s8 rtw_get_sta_tx_nss(_adapter *adapter, struct sta_info *psta)
+{
+	struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter);
+	u8 rf_type = RF_1T1R, custom_rf_type;
+	s8 nss = 1;
+
+	if (!psta)
+		return nss;
+
+	custom_rf_type = adapter->registrypriv.rf_config;
+	rtw_hal_get_hwreg(adapter, HW_VAR_RF_TYPE, (u8 *)(&rf_type));
+	if (RF_TYPE_VALID(custom_rf_type))
+		rf_type = custom_rf_type;
+
+	nss = rtw_min(rf_type_to_rf_tx_cnt(rf_type), hal_spec->tx_nss_num);
+
+#ifdef CONFIG_80211N_HT
+	#ifdef CONFIG_80211AC_VHT
+	if (psta->vhtpriv.vht_option)
+		nss = rtw_min(nss, rtw_vht_mcsmap_to_nss(psta->vhtpriv.vht_mcs_map));
+	else
+	#endif /* CONFIG_80211AC_VHT */
+	if (psta->htpriv.ht_option)
+		nss = rtw_min(nss, rtw_ht_mcsset_to_nss(psta->htpriv.ht_cap.supp_mcs_set));
+#endif /*CONFIG_80211N_HT*/
+	RTW_INFO("%s: %d SS\n", __func__, nss);
+	return nss;
+}
+
+u8 judge_network_type(_adapter *padapter, unsigned char *rate, int ratelen)
+{
+	u8 network_type = 0;
+	struct mlme_ext_priv	*pmlmeext = &padapter->mlmeextpriv;
+	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
+
+
+	if (pmlmeext->cur_channel > 14) {
+		if (pmlmeinfo->VHT_enable)
+			network_type = WIRELESS_11AC;
+		else if (pmlmeinfo->HT_enable)
+			network_type = WIRELESS_11_5N;
+
+		network_type |= WIRELESS_11A;
+	} else {
+		if (pmlmeinfo->HT_enable)
+			network_type = WIRELESS_11_24N;
+
+		if ((cckratesonly_included(rate, ratelen)) == _TRUE)
+			network_type |= WIRELESS_11B;
+		else if ((cckrates_included(rate, ratelen)) == _TRUE)
+			network_type |= WIRELESS_11BG;
+		else
+			network_type |= WIRELESS_11G;
+	}
+
+	return	network_type;
+}
+
+unsigned char ratetbl_val_2wifirate(unsigned char rate);
+unsigned char ratetbl_val_2wifirate(unsigned char rate)
+{
+	unsigned char val = 0;
+
+	switch (rate & 0x7f) {
+	case 0:
+		val = IEEE80211_CCK_RATE_1MB;
+		break;
+
+	case 1:
+		val = IEEE80211_CCK_RATE_2MB;
+		break;
+
+	case 2:
+		val = IEEE80211_CCK_RATE_5MB;
+		break;
+
+	case 3:
+		val = IEEE80211_CCK_RATE_11MB;
+		break;
+
+	case 4:
+		val = IEEE80211_OFDM_RATE_6MB;
+		break;
+
+	case 5:
+		val = IEEE80211_OFDM_RATE_9MB;
+		break;
+
+	case 6:
+		val = IEEE80211_OFDM_RATE_12MB;
+		break;
+
+	case 7:
+		val = IEEE80211_OFDM_RATE_18MB;
+		break;
+
+	case 8:
+		val = IEEE80211_OFDM_RATE_24MB;
+		break;
+
+	case 9:
+		val = IEEE80211_OFDM_RATE_36MB;
+		break;
+
+	case 10:
+		val = IEEE80211_OFDM_RATE_48MB;
+		break;
+
+	case 11:
+		val = IEEE80211_OFDM_RATE_54MB;
+		break;
+
+	}
+
+	return val;
+
+}
+
+int is_basicrate(_adapter *padapter, unsigned char rate);
+int is_basicrate(_adapter *padapter, unsigned char rate)
+{
+	int i;
+	unsigned char val;
+	struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
+
+	for (i = 0; i < NumRates; i++) {
+		val = pmlmeext->basicrate[i];
+
+		if ((val != 0xff) && (val != 0xfe)) {
+			if (rate == ratetbl_val_2wifirate(val))
+				return _TRUE;
+		}
+	}
+
+	return _FALSE;
+}
+
+unsigned int ratetbl2rateset(_adapter *padapter, unsigned char *rateset);
+unsigned int ratetbl2rateset(_adapter *padapter, unsigned char *rateset)
+{
+	int i;
+	unsigned char rate;
+	unsigned int	len = 0;
+	struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
+
+	for (i = 0; i < NumRates; i++) {
+		rate = pmlmeext->datarate[i];
+
+		if (rtw_get_oper_ch(padapter) > 14 && rate < _6M_RATE_) /*5G no support CCK rate*/
+			continue;
+
+		switch (rate) {
+		case 0xff:
+			return len;
+
+		case 0xfe:
+			continue;
+
+		default:
+			rate = ratetbl_val_2wifirate(rate);
+
+			if (is_basicrate(padapter, rate) == _TRUE)
+				rate |= IEEE80211_BASIC_RATE_MASK;
+
+			rateset[len] = rate;
+			len++;
+			break;
+		}
+	}
+	return len;
+}
+
+void get_rate_set(_adapter *padapter, unsigned char *pbssrate, int *bssrate_len)
+{
+	unsigned char supportedrates[NumRates];
+
+	_rtw_memset(supportedrates, 0, NumRates);
+	*bssrate_len = ratetbl2rateset(padapter, supportedrates);
+	_rtw_memcpy(pbssrate, supportedrates, *bssrate_len);
+}
+
+void set_mcs_rate_by_mask(u8 *mcs_set, u32 mask)
+{
+	u8 mcs_rate_1r = (u8)(mask & 0xff);
+	u8 mcs_rate_2r = (u8)((mask >> 8) & 0xff);
+	u8 mcs_rate_3r = (u8)((mask >> 16) & 0xff);
+	u8 mcs_rate_4r = (u8)((mask >> 24) & 0xff);
+
+	mcs_set[0] &= mcs_rate_1r;
+	mcs_set[1] &= mcs_rate_2r;
+	mcs_set[2] &= mcs_rate_3r;
+	mcs_set[3] &= mcs_rate_4r;
+}
+
+void UpdateBrateTbl(
+	IN PADAPTER		Adapter,
+	IN u8			*mBratesOS
+)
+{
+	u8	i;
+	u8	rate;
+
+	/* 1M, 2M, 5.5M, 11M, 6M, 12M, 24M are mandatory. */
+	for (i = 0; i < NDIS_802_11_LENGTH_RATES_EX; i++) {
+		rate = mBratesOS[i] & 0x7f;
+		switch (rate) {
+		case IEEE80211_CCK_RATE_1MB:
+		case IEEE80211_CCK_RATE_2MB:
+		case IEEE80211_CCK_RATE_5MB:
+		case IEEE80211_CCK_RATE_11MB:
+		case IEEE80211_OFDM_RATE_6MB:
+		case IEEE80211_OFDM_RATE_12MB:
+		case IEEE80211_OFDM_RATE_24MB:
+			mBratesOS[i] |= IEEE80211_BASIC_RATE_MASK;
+			break;
+		}
+	}
+
+}
+
+void UpdateBrateTblForSoftAP(u8 *bssrateset, u32 bssratelen)
+{
+	u8	i;
+	u8	rate;
+
+	for (i = 0; i < bssratelen; i++) {
+		rate = bssrateset[i] & 0x7f;
+		switch (rate) {
+		case IEEE80211_CCK_RATE_1MB:
+		case IEEE80211_CCK_RATE_2MB:
+		case IEEE80211_CCK_RATE_5MB:
+		case IEEE80211_CCK_RATE_11MB:
+			bssrateset[i] |= IEEE80211_BASIC_RATE_MASK;
+			break;
+		}
+	}
+
+}
+void Set_MSR(_adapter *padapter, u8 type)
+{
+	rtw_hal_set_hwreg(padapter, HW_VAR_MEDIA_STATUS, (u8 *)(&type));
+}
+
+inline u8 rtw_get_oper_ch(_adapter *adapter)
+{
+	return adapter_to_dvobj(adapter)->oper_channel;
+}
+
+inline void rtw_set_oper_ch(_adapter *adapter, u8 ch)
+{
+#ifdef DBG_CH_SWITCH
+	const int len = 128;
+	char msg[128] = {0};
+	int cnt = 0;
+	int i = 0;
+#endif  /* DBG_CH_SWITCH */
+	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
+
+	if (dvobj->oper_channel != ch) {
+		dvobj->on_oper_ch_time = rtw_get_current_time();
+
+#ifdef DBG_CH_SWITCH
+		cnt += snprintf(msg + cnt, len - cnt, "switch to ch %3u", ch);
+
+		for (i = 0; i < dvobj->iface_nums; i++) {
+			_adapter *iface = dvobj->padapters[i];
+			cnt += snprintf(msg + cnt, len - cnt, " ["ADPT_FMT":", ADPT_ARG(iface));
+			if (iface->mlmeextpriv.cur_channel == ch)
+				cnt += snprintf(msg + cnt, len - cnt, "C");
+			else
+				cnt += snprintf(msg + cnt, len - cnt, "_");
+			if (iface->wdinfo.listen_channel == ch && !rtw_p2p_chk_state(&iface->wdinfo, P2P_STATE_NONE))
+				cnt += snprintf(msg + cnt, len - cnt, "L");
+			else
+				cnt += snprintf(msg + cnt, len - cnt, "_");
+			cnt += snprintf(msg + cnt, len - cnt, "]");
+		}
+
+		RTW_INFO(FUNC_ADPT_FMT" %s\n", FUNC_ADPT_ARG(adapter), msg);
+#endif /* DBG_CH_SWITCH */
+	}
+
+	dvobj->oper_channel = ch;
+}
+
+inline u8 rtw_get_oper_bw(_adapter *adapter)
+{
+	return adapter_to_dvobj(adapter)->oper_bwmode;
+}
+
+inline void rtw_set_oper_bw(_adapter *adapter, u8 bw)
+{
+	adapter_to_dvobj(adapter)->oper_bwmode = bw;
+}
+
+inline u8 rtw_get_oper_choffset(_adapter *adapter)
+{
+	return adapter_to_dvobj(adapter)->oper_ch_offset;
+}
+
+inline void rtw_set_oper_choffset(_adapter *adapter, u8 offset)
+{
+	adapter_to_dvobj(adapter)->oper_ch_offset = offset;
+}
+
+u8 rtw_get_offset_by_chbw(u8 ch, u8 bw, u8 *r_offset)
+{
+	u8 valid = 1;
+	u8 offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
+
+	if (bw == CHANNEL_WIDTH_20)
+		goto exit;
+
+	if (bw >= CHANNEL_WIDTH_80 && ch <= 14) {
+		valid = 0;
+		goto exit;
+	}
+
+	if (ch >= 1 && ch <= 4)
+		offset = HAL_PRIME_CHNL_OFFSET_LOWER;
+	else if (ch >= 5 && ch <= 9) {
+		if (*r_offset == HAL_PRIME_CHNL_OFFSET_LOWER || *r_offset == HAL_PRIME_CHNL_OFFSET_UPPER)
+			offset = *r_offset; /* both lower and upper is valid, obey input value */
+		else
+			offset = HAL_PRIME_CHNL_OFFSET_UPPER; /* default use upper */
+	} else if (ch >= 10 && ch <= 13)
+		offset = HAL_PRIME_CHNL_OFFSET_UPPER;
+	else if (ch == 14) {
+		valid = 0; /* ch14 doesn't support 40MHz bandwidth */
+		goto exit;
+	} else if (ch >= 36 && ch <= 177) {
+		switch (ch) {
+		case 36:
+		case 44:
+		case 52:
+		case 60:
+		case 100:
+		case 108:
+		case 116:
+		case 124:
+		case 132:
+		case 140:
+		case 149:
+		case 157:
+		case 165:
+		case 173:
+			offset = HAL_PRIME_CHNL_OFFSET_LOWER;
+			break;
+		case 40:
+		case 48:
+		case 56:
+		case 64:
+		case 104:
+		case 112:
+		case 120:
+		case 128:
+		case 136:
+		case 144:
+		case 153:
+		case 161:
+		case 169:
+		case 177:
+			offset = HAL_PRIME_CHNL_OFFSET_UPPER;
+			break;
+		default:
+			valid = 0;
+			break;
+		}
+	} else
+		valid = 0;
+
+exit:
+	if (valid && r_offset)
+		*r_offset = offset;
+	return valid;
+}
+
+u8 rtw_get_center_ch(u8 channel, u8 chnl_bw, u8 chnl_offset)
+{
+	u8 center_ch = channel;
+
+	if (chnl_bw == CHANNEL_WIDTH_80) {
+		if (channel == 36 || channel == 40 || channel == 44 || channel == 48)
+			center_ch = 42;
+		else if (channel == 52 || channel == 56 || channel == 60 || channel == 64)
+			center_ch = 58;
+		else if (channel == 100 || channel == 104 || channel == 108 || channel == 112)
+			center_ch = 106;
+		else if (channel == 116 || channel == 120 || channel == 124 || channel == 128)
+			center_ch = 122;
+		else if (channel == 132 || channel == 136 || channel == 140 || channel == 144)
+			center_ch = 138;
+		else if (channel == 149 || channel == 153 || channel == 157 || channel == 161)
+			center_ch = 155;
+		else if (channel == 165 || channel == 169 || channel == 173 || channel == 177)
+			center_ch = 171;
+		else if (channel <= 14)
+			center_ch = 7;
+	} else if (chnl_bw == CHANNEL_WIDTH_40) {
+		if (chnl_offset == HAL_PRIME_CHNL_OFFSET_LOWER)
+			center_ch = channel + 2;
+		else
+			center_ch = channel - 2;
+	} else if (chnl_bw == CHANNEL_WIDTH_20)
+		center_ch = channel;
+	else
+		rtw_warn_on(1);
+
+	return center_ch;
+}
+
+inline systime rtw_get_on_oper_ch_time(_adapter *adapter)
+{
+	return adapter_to_dvobj(adapter)->on_oper_ch_time;
+}
+
+inline systime rtw_get_on_cur_ch_time(_adapter *adapter)
+{
+	if (adapter->mlmeextpriv.cur_channel == adapter_to_dvobj(adapter)->oper_channel)
+		return adapter_to_dvobj(adapter)->on_oper_ch_time;
+	else
+		return 0;
+}
+
+void set_channel_bwmode(_adapter *padapter, unsigned char channel, unsigned char channel_offset, unsigned short bwmode)
+{
+	u8 center_ch, chnl_offset80 = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
+#if (defined(CONFIG_TDLS) && defined(CONFIG_TDLS_CH_SW)) || defined(CONFIG_MCC_MODE)
+	u8 iqk_info_backup = _FALSE;
+#endif
+
+	if (padapter->bNotifyChannelChange)
+		RTW_INFO("[%s] ch = %d, offset = %d, bwmode = %d\n", __FUNCTION__, channel, channel_offset, bwmode);
+
+	center_ch = rtw_get_center_ch(channel, bwmode, channel_offset);
+
+	if (bwmode == CHANNEL_WIDTH_80) {
+		if (center_ch > channel)
+			chnl_offset80 = HAL_PRIME_CHNL_OFFSET_LOWER;
+		else if (center_ch < channel)
+			chnl_offset80 = HAL_PRIME_CHNL_OFFSET_UPPER;
+		else
+			chnl_offset80 = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
+	}
+	_enter_critical_mutex(&(adapter_to_dvobj(padapter)->setch_mutex), NULL);
+
+#ifdef CONFIG_MCC_MODE
+	if (MCC_EN(padapter)) {
+		/* driver doesn't set channel setting reg under MCC */
+		if (rtw_hal_check_mcc_status(padapter, MCC_STATUS_DOING_MCC))
+			RTW_INFO("Warning: Do not set channel setting reg MCC mode\n");
+	}
+#endif
+
+#ifdef CONFIG_DFS_MASTER
+	{
+		struct rf_ctl_t *rfctl = adapter_to_rfctl(padapter);
+		bool ori_overlap_radar_detect_ch = rtw_rfctl_overlap_radar_detect_ch(rfctl);
+		bool new_overlap_radar_detect_ch = _rtw_rfctl_overlap_radar_detect_ch(rfctl, channel, bwmode, channel_offset);
+
+		if (new_overlap_radar_detect_ch && IS_CH_WAITING(rfctl)) {
+			u8 pause = 0xFF;
+
+			rtw_hal_set_hwreg(padapter, HW_VAR_TXPAUSE, &pause);
+		}
+#endif /* CONFIG_DFS_MASTER */
+
+		/* set Channel */
+		/* saved channel/bw info */
+		rtw_set_oper_ch(padapter, channel);
+		rtw_set_oper_bw(padapter, bwmode);
+		rtw_set_oper_choffset(padapter, channel_offset);
+
+#if (defined(CONFIG_TDLS) && defined(CONFIG_TDLS_CH_SW)) || defined(CONFIG_MCC_MODE)
+		/* To check if we need to backup iqk info after switch chnl & bw */
+		{
+			u8 take_care_iqk, do_iqk;
+
+			rtw_hal_get_hwreg(padapter, HW_VAR_CH_SW_NEED_TO_TAKE_CARE_IQK_INFO, &take_care_iqk);
+			rtw_hal_get_hwreg(padapter, HW_VAR_DO_IQK, &do_iqk);
+			if ((take_care_iqk == _TRUE) && (do_iqk == _TRUE))
+				iqk_info_backup = _TRUE;
+		}
+#endif
+
+		rtw_hal_set_chnl_bw(padapter, center_ch, bwmode, channel_offset, chnl_offset80); /* set center channel */
+
+#if (defined(CONFIG_TDLS) && defined(CONFIG_TDLS_CH_SW)) || defined(CONFIG_MCC_MODE)
+		if (iqk_info_backup == _TRUE)
+			rtw_hal_ch_sw_iqk_info_backup(padapter);
+#endif
+
+#ifdef CONFIG_DFS_MASTER
+		if (new_overlap_radar_detect_ch)
+			rtw_odm_radar_detect_enable(padapter);
+		else if (ori_overlap_radar_detect_ch) {
+			u8 pause = 0x00;
+
+			rtw_odm_radar_detect_disable(padapter);
+			rtw_hal_set_hwreg(padapter, HW_VAR_TXPAUSE, &pause);
+		}
+	}
+#endif /* CONFIG_DFS_MASTER */
+
+	_exit_critical_mutex(&(adapter_to_dvobj(padapter)->setch_mutex), NULL);
+}
+
+__inline u8 *get_my_bssid(WLAN_BSSID_EX *pnetwork)
+{
+	return pnetwork->MacAddress;
+}
+
+u16 get_beacon_interval(WLAN_BSSID_EX *bss)
+{
+	unsigned short val;
+	_rtw_memcpy((unsigned char *)&val, rtw_get_beacon_interval_from_ie(bss->IEs), 2);
+
+	return le16_to_cpu(val);
+
+}
+
+int is_client_associated_to_ap(_adapter *padapter)
+{
+	struct mlme_ext_priv	*pmlmeext;
+	struct mlme_ext_info	*pmlmeinfo;
+
+	if (!padapter)
+		return _FAIL;
+
+	pmlmeext = &padapter->mlmeextpriv;
+	pmlmeinfo = &(pmlmeext->mlmext_info);
+
+	if ((pmlmeinfo->state & WIFI_FW_ASSOC_SUCCESS) && ((pmlmeinfo->state & 0x03) == WIFI_FW_STATION_STATE))
+		return _TRUE;
+	else
+		return _FAIL;
+}
+
+int is_client_associated_to_ibss(_adapter *padapter)
+{
+	struct mlme_ext_priv	*pmlmeext = &padapter->mlmeextpriv;
+	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
+
+	if ((pmlmeinfo->state & WIFI_FW_ASSOC_SUCCESS) && ((pmlmeinfo->state & 0x03) == WIFI_FW_ADHOC_STATE))
+		return _TRUE;
+	else
+		return _FAIL;
+}
+
+int is_IBSS_empty(_adapter *padapter)
+{
+	int i;
+	struct macid_ctl_t *macid_ctl = &padapter->dvobj->macid_ctl;
+
+	for (i = 0; i < macid_ctl->num; i++) {
+		if (!rtw_macid_is_used(macid_ctl, i))
+			continue;
+		if (!rtw_macid_is_iface_specific(macid_ctl, i, padapter))
+			continue;
+		if (!GET_H2CCMD_MSRRPT_PARM_OPMODE(&macid_ctl->h2c_msr[i]))
+			continue;
+		if (GET_H2CCMD_MSRRPT_PARM_ROLE(&macid_ctl->h2c_msr[i]) == H2C_MSR_ROLE_ADHOC)
+			return _FAIL;
+	}
+
+	return _TRUE;
+}
+
+unsigned int decide_wait_for_beacon_timeout(unsigned int bcn_interval)
+{
+	if ((bcn_interval << 2) < WAIT_FOR_BCN_TO_MIN)
+		return WAIT_FOR_BCN_TO_MIN;
+	else if ((bcn_interval << 2) > WAIT_FOR_BCN_TO_MAX)
+		return WAIT_FOR_BCN_TO_MAX;
+	else
+		return bcn_interval << 2;
+}
+
+void CAM_empty_entry(
+	PADAPTER	Adapter,
+	u8			ucIndex
+)
+{
+	rtw_hal_set_hwreg(Adapter, HW_VAR_CAM_EMPTY_ENTRY, (u8 *)(&ucIndex));
+}
+
+void invalidate_cam_all(_adapter *padapter)
+{
+	struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
+	struct cam_ctl_t *cam_ctl = &dvobj->cam_ctl;
+	_irqL irqL;
+	u8 val8 = 0;
+
+	rtw_hal_set_hwreg(padapter, HW_VAR_CAM_INVALID_ALL, &val8);
+
+	_enter_critical_bh(&cam_ctl->lock, &irqL);
+	rtw_sec_cam_map_clr_all(&cam_ctl->used);
+	_rtw_memset(dvobj->cam_cache, 0, sizeof(struct sec_cam_ent) * SEC_CAM_ENT_NUM_SW_LIMIT);
+	_exit_critical_bh(&cam_ctl->lock, &irqL);
+}
+
+void _clear_cam_entry(_adapter *padapter, u8 entry)
+{
+	unsigned char null_sta[] = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00};
+	unsigned char null_key[] = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00};
+
+	rtw_sec_write_cam_ent(padapter, entry, 0, null_sta, null_key);
+}
+
+inline void write_cam(_adapter *adapter, u8 id, u16 ctrl, u8 *mac, u8 *key)
+{
+#ifdef CONFIG_WRITE_CACHE_ONLY
+	write_cam_cache(adapter, id , ctrl, mac, key);
+#else
+	rtw_sec_write_cam_ent(adapter, id, ctrl, mac, key);
+	write_cam_cache(adapter, id , ctrl, mac, key);
+#endif
+}
+
+inline void clear_cam_entry(_adapter *adapter, u8 id)
+{
+	_clear_cam_entry(adapter, id);
+	clear_cam_cache(adapter, id);
+}
+
+inline void write_cam_from_cache(_adapter *adapter, u8 id)
+{
+	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
+	struct cam_ctl_t *cam_ctl = &dvobj->cam_ctl;
+	_irqL irqL;
+	struct sec_cam_ent cache;
+
+	_enter_critical_bh(&cam_ctl->lock, &irqL);
+	_rtw_memcpy(&cache, &dvobj->cam_cache[id], sizeof(struct sec_cam_ent));
+	_exit_critical_bh(&cam_ctl->lock, &irqL);
+
+	rtw_sec_write_cam_ent(adapter, id, cache.ctrl, cache.mac, cache.key);
+}
+void write_cam_cache(_adapter *adapter, u8 id, u16 ctrl, u8 *mac, u8 *key)
+{
+	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
+	struct cam_ctl_t *cam_ctl = &dvobj->cam_ctl;
+	_irqL irqL;
+
+	_enter_critical_bh(&cam_ctl->lock, &irqL);
+
+	dvobj->cam_cache[id].ctrl = ctrl;
+	_rtw_memcpy(dvobj->cam_cache[id].mac, mac, ETH_ALEN);
+	_rtw_memcpy(dvobj->cam_cache[id].key, key, 16);
+
+	_exit_critical_bh(&cam_ctl->lock, &irqL);
+}
+
+void clear_cam_cache(_adapter *adapter, u8 id)
+{
+	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
+	struct cam_ctl_t *cam_ctl = &dvobj->cam_ctl;
+	_irqL irqL;
+
+	_enter_critical_bh(&cam_ctl->lock, &irqL);
+
+	_rtw_memset(&(dvobj->cam_cache[id]), 0, sizeof(struct sec_cam_ent));
+
+	_exit_critical_bh(&cam_ctl->lock, &irqL);
+}
+
+inline bool _rtw_camctl_chk_cap(_adapter *adapter, u8 cap)
+{
+	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
+	struct cam_ctl_t *cam_ctl = &dvobj->cam_ctl;
+
+	if (cam_ctl->sec_cap & cap)
+		return _TRUE;
+	return _FALSE;
+}
+
+inline void _rtw_camctl_set_flags(_adapter *adapter, u32 flags)
+{
+	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
+	struct cam_ctl_t *cam_ctl = &dvobj->cam_ctl;
+
+	cam_ctl->flags |= flags;
+}
+
+inline void rtw_camctl_set_flags(_adapter *adapter, u32 flags)
+{
+	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
+	struct cam_ctl_t *cam_ctl = &dvobj->cam_ctl;
+	_irqL irqL;
+
+	_enter_critical_bh(&cam_ctl->lock, &irqL);
+	_rtw_camctl_set_flags(adapter, flags);
+	_exit_critical_bh(&cam_ctl->lock, &irqL);
+}
+
+inline void _rtw_camctl_clr_flags(_adapter *adapter, u32 flags)
+{
+	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
+	struct cam_ctl_t *cam_ctl = &dvobj->cam_ctl;
+
+	cam_ctl->flags &= ~flags;
+}
+
+inline void rtw_camctl_clr_flags(_adapter *adapter, u32 flags)
+{
+	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
+	struct cam_ctl_t *cam_ctl = &dvobj->cam_ctl;
+	_irqL irqL;
+
+	_enter_critical_bh(&cam_ctl->lock, &irqL);
+	_rtw_camctl_clr_flags(adapter, flags);
+	_exit_critical_bh(&cam_ctl->lock, &irqL);
+}
+
+inline bool _rtw_camctl_chk_flags(_adapter *adapter, u32 flags)
+{
+	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
+	struct cam_ctl_t *cam_ctl = &dvobj->cam_ctl;
+
+	if (cam_ctl->flags & flags)
+		return _TRUE;
+	return _FALSE;
+}
+
+void dump_sec_cam_map(void *sel, struct sec_cam_bmp *map, u8 max_num)
+{
+	RTW_PRINT_SEL(sel, "0x%08x\n", map->m0);
+#if (SEC_CAM_ENT_NUM_SW_LIMIT > 32)
+	if (max_num && max_num > 32)
+		RTW_PRINT_SEL(sel, "0x%08x\n", map->m1);
+#endif
+#if (SEC_CAM_ENT_NUM_SW_LIMIT > 64)
+	if (max_num && max_num > 64)
+		RTW_PRINT_SEL(sel, "0x%08x\n", map->m2);
+#endif
+#if (SEC_CAM_ENT_NUM_SW_LIMIT > 96)
+	if (max_num && max_num > 96)
+		RTW_PRINT_SEL(sel, "0x%08x\n", map->m3);
+#endif
+}
+
+inline bool rtw_sec_camid_is_set(struct sec_cam_bmp *map, u8 id)
+{
+	if (id < 32)
+		return map->m0 & BIT(id);
+#if (SEC_CAM_ENT_NUM_SW_LIMIT > 32)
+	else if (id < 64)
+		return map->m1 & BIT(id - 32);
+#endif
+#if (SEC_CAM_ENT_NUM_SW_LIMIT > 64)
+	else if (id < 96)
+		return map->m2 & BIT(id - 64);
+#endif
+#if (SEC_CAM_ENT_NUM_SW_LIMIT > 96)
+	else if (id < 128)
+		return map->m3 & BIT(id - 96);
+#endif
+	else
+		rtw_warn_on(1);
+
+	return 0;
+}
+
+inline void rtw_sec_cam_map_set(struct sec_cam_bmp *map, u8 id)
+{
+	if (id < 32)
+		map->m0 |= BIT(id);
+#if (SEC_CAM_ENT_NUM_SW_LIMIT > 32)
+	else if (id < 64)
+		map->m1 |= BIT(id - 32);
+#endif
+#if (SEC_CAM_ENT_NUM_SW_LIMIT > 64)
+	else if (id < 96)
+		map->m2 |= BIT(id - 64);
+#endif
+#if (SEC_CAM_ENT_NUM_SW_LIMIT > 96)
+	else if (id < 128)
+		map->m3 |= BIT(id - 96);
+#endif
+	else
+		rtw_warn_on(1);
+}
+
+inline void rtw_sec_cam_map_clr(struct sec_cam_bmp *map, u8 id)
+{
+	if (id < 32)
+		map->m0 &= ~BIT(id);
+#if (SEC_CAM_ENT_NUM_SW_LIMIT > 32)
+	else if (id < 64)
+		map->m1 &= ~BIT(id - 32);
+#endif
+#if (SEC_CAM_ENT_NUM_SW_LIMIT > 64)
+	else if (id < 96)
+		map->m2 &= ~BIT(id - 64);
+#endif
+#if (SEC_CAM_ENT_NUM_SW_LIMIT > 96)
+	else if (id < 128)
+		map->m3 &= ~BIT(id - 96);
+#endif
+	else
+		rtw_warn_on(1);
+}
+
+inline void rtw_sec_cam_map_clr_all(struct sec_cam_bmp *map)
+{
+	map->m0 = 0;
+#if (SEC_CAM_ENT_NUM_SW_LIMIT > 32)
+	map->m1 = 0;
+#endif
+#if (SEC_CAM_ENT_NUM_SW_LIMIT > 64)
+	map->m2 = 0;
+#endif
+#if (SEC_CAM_ENT_NUM_SW_LIMIT > 96)
+	map->m3 = 0;
+#endif
+}
+
+inline bool rtw_sec_camid_is_drv_forbid(struct cam_ctl_t *cam_ctl, u8 id)
+{
+	struct sec_cam_bmp forbid_map;
+
+	forbid_map.m0 = 0x00000ff0;
+#if (SEC_CAM_ENT_NUM_SW_LIMIT > 32)
+	forbid_map.m1 = 0x00000000;
+#endif
+#if (SEC_CAM_ENT_NUM_SW_LIMIT > 64)
+	forbid_map.m2 = 0x00000000;
+#endif
+#if (SEC_CAM_ENT_NUM_SW_LIMIT > 96)
+	forbid_map.m3 = 0x00000000;
+#endif
+
+	if (id < 32)
+		return forbid_map.m0 & BIT(id);
+#if (SEC_CAM_ENT_NUM_SW_LIMIT > 32)
+	else if (id < 64)
+		return forbid_map.m1 & BIT(id - 32);
+#endif
+#if (SEC_CAM_ENT_NUM_SW_LIMIT > 64)
+	else if (id < 96)
+		return forbid_map.m2 & BIT(id - 64);
+#endif
+#if (SEC_CAM_ENT_NUM_SW_LIMIT > 96)
+	else if (id < 128)
+		return forbid_map.m3 & BIT(id - 96);
+#endif
+	else
+		rtw_warn_on(1);
+
+	return 1;
+}
+
+bool _rtw_sec_camid_is_used(struct cam_ctl_t *cam_ctl, u8 id)
+{
+	bool ret = _FALSE;
+
+	if (id >= cam_ctl->num) {
+		rtw_warn_on(1);
+		goto exit;
+	}
+
+#if 0 /* for testing */
+	if (rtw_sec_camid_is_drv_forbid(cam_ctl, id)) {
+		ret = _TRUE;
+		goto exit;
+	}
+#endif
+
+	ret = rtw_sec_camid_is_set(&cam_ctl->used, id);
+
+exit:
+	return ret;
+}
+
+inline bool rtw_sec_camid_is_used(struct cam_ctl_t *cam_ctl, u8 id)
+{
+	_irqL irqL;
+	bool ret;
+
+	_enter_critical_bh(&cam_ctl->lock, &irqL);
+	ret = _rtw_sec_camid_is_used(cam_ctl, id);
+	_exit_critical_bh(&cam_ctl->lock, &irqL);
+
+	return ret;
+}
+u8 rtw_get_sec_camid(_adapter *adapter, u8 max_bk_key_num, u8 *sec_key_id)
+{
+	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
+	struct cam_ctl_t *cam_ctl = &dvobj->cam_ctl;
+	int i;
+	_irqL irqL;
+	u8 sec_cam_num = 0;
+
+	_enter_critical_bh(&cam_ctl->lock, &irqL);
+	for (i = 0; i < cam_ctl->num; i++) {
+		if (_rtw_sec_camid_is_used(cam_ctl, i)) {
+			sec_key_id[sec_cam_num++] = i;
+			if (sec_cam_num == max_bk_key_num)
+				break;
+		}
+	}
+	_exit_critical_bh(&cam_ctl->lock, &irqL);
+
+	return sec_cam_num;
+}
+
+inline bool _rtw_camid_is_gk(_adapter *adapter, u8 cam_id)
+{
+	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
+	struct cam_ctl_t *cam_ctl = &dvobj->cam_ctl;
+	bool ret = _FALSE;
+
+	if (cam_id >= cam_ctl->num) {
+		rtw_warn_on(1);
+		goto exit;
+	}
+
+	if (_rtw_sec_camid_is_used(cam_ctl, cam_id) == _FALSE)
+		goto exit;
+
+	ret = (dvobj->cam_cache[cam_id].ctrl & BIT6) ? _TRUE : _FALSE;
+
+exit:
+	return ret;
+}
+
+inline bool rtw_camid_is_gk(_adapter *adapter, u8 cam_id)
+{
+	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
+	struct cam_ctl_t *cam_ctl = &dvobj->cam_ctl;
+	_irqL irqL;
+	bool ret;
+
+	_enter_critical_bh(&cam_ctl->lock, &irqL);
+	ret = _rtw_camid_is_gk(adapter, cam_id);
+	_exit_critical_bh(&cam_ctl->lock, &irqL);
+
+	return ret;
+}
+
+bool cam_cache_chk(_adapter *adapter, u8 id, u8 *addr, s16 kid, s8 gk)
+{
+	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
+	bool ret = _FALSE;
+
+	if (addr && _rtw_memcmp(dvobj->cam_cache[id].mac, addr, ETH_ALEN) == _FALSE)
+		goto exit;
+	if (kid >= 0 && kid != (dvobj->cam_cache[id].ctrl & 0x03))
+		goto exit;
+	if (gk != -1 && (gk ? _TRUE : _FALSE) != _rtw_camid_is_gk(adapter, id))
+		goto exit;
+
+	ret = _TRUE;
+
+exit:
+	return ret;
+}
+
+s16 _rtw_camid_search(_adapter *adapter, u8 *addr, s16 kid, s8 gk)
+{
+	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
+	struct cam_ctl_t *cam_ctl = &dvobj->cam_ctl;
+	int i;
+	s16 cam_id = -1;
+
+	for (i = 0; i < cam_ctl->num; i++) {
+		if (cam_cache_chk(adapter, i, addr, kid, gk)) {
+			cam_id = i;
+			break;
+		}
+	}
+
+	if (0) {
+		if (addr)
+			RTW_INFO(FUNC_ADPT_FMT" addr:"MAC_FMT" kid:%d, gk:%d, return cam_id:%d\n"
+				, FUNC_ADPT_ARG(adapter), MAC_ARG(addr), kid, gk, cam_id);
+		else
+			RTW_INFO(FUNC_ADPT_FMT" addr:%p kid:%d, gk:%d, return cam_id:%d\n"
+				, FUNC_ADPT_ARG(adapter), addr, kid, gk, cam_id);
+	}
+
+	return cam_id;
+}
+
+s16 rtw_camid_search(_adapter *adapter, u8 *addr, s16 kid, s8 gk)
+{
+	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
+	struct cam_ctl_t *cam_ctl = &dvobj->cam_ctl;
+	_irqL irqL;
+	s16 cam_id = -1;
+
+	_enter_critical_bh(&cam_ctl->lock, &irqL);
+	cam_id = _rtw_camid_search(adapter, addr, kid, gk);
+	_exit_critical_bh(&cam_ctl->lock, &irqL);
+
+	return cam_id;
+}
+
+s16 rtw_get_camid(_adapter *adapter, u8 *addr, s16 kid, u8 gk)
+{
+	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
+	struct cam_ctl_t *cam_ctl = &dvobj->cam_ctl;
+	int i;
+#if 0 /* for testing */
+	static u8 start_id = 0;
+#else
+	u8 start_id = 0;
+#endif
+	s16 cam_id = -1;
+
+	if (addr == NULL) {
+		RTW_PRINT(FUNC_ADPT_FMT" mac_address is NULL\n"
+			  , FUNC_ADPT_ARG(adapter));
+		rtw_warn_on(1);
+		goto _exit;
+	}
+
+	/* find cam entry which has the same addr, kid (, gk bit) */
+	if (_rtw_camctl_chk_cap(adapter, SEC_CAP_CHK_BMC) == _TRUE)
+		i = _rtw_camid_search(adapter, addr, kid, gk);
+	else
+		i = _rtw_camid_search(adapter, addr, kid, -1);
+
+	if (i >= 0) {
+		cam_id = i;
+		goto _exit;
+	}
+
+	for (i = 0; i < cam_ctl->num; i++) {
+		/* bypass default key which is allocated statically */
+#ifndef CONFIG_CONCURRENT_MODE
+		if (((i + start_id) % cam_ctl->num) < 4)
+			continue;
+#endif
+		if (_rtw_sec_camid_is_used(cam_ctl, ((i + start_id) % cam_ctl->num)) == _FALSE)
+			break;
+	}
+
+	if (i == cam_ctl->num) {
+		RTW_PRINT(FUNC_ADPT_FMT" %s key with "MAC_FMT" id:%u no room\n"
+			, FUNC_ADPT_ARG(adapter), gk ? "group" : "pairwise", MAC_ARG(addr), kid);
+		rtw_warn_on(1);
+		goto _exit;
+	}
+
+	cam_id = ((i + start_id) % cam_ctl->num);
+	start_id = ((i + start_id + 1) % cam_ctl->num);
+
+_exit:
+	return cam_id;
+}
+
+s16 rtw_camid_alloc(_adapter *adapter, struct sta_info *sta, u8 kid, u8 gk, bool *used)
+{
+	struct mlme_ext_info *mlmeinfo = &adapter->mlmeextpriv.mlmext_info;
+	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
+	struct cam_ctl_t *cam_ctl = &dvobj->cam_ctl;
+	_irqL irqL;
+	s16 cam_id = -1;
+
+	*used = _FALSE;
+
+	_enter_critical_bh(&cam_ctl->lock, &irqL);
+
+	if ((((mlmeinfo->state & 0x03) == WIFI_FW_AP_STATE) || ((mlmeinfo->state & 0x03) == WIFI_FW_ADHOC_STATE))
+	    && !sta) {
+		/*
+		* 1. non-STA mode WEP key
+		* 2. group TX key
+		*/
+#ifndef CONFIG_CONCURRENT_MODE
+		/* static alloction to default key by key ID when concurrent is not defined */
+		if (kid > 3) {
+			RTW_PRINT(FUNC_ADPT_FMT" group key with invalid key id:%u\n"
+				  , FUNC_ADPT_ARG(adapter), kid);
+			rtw_warn_on(1);
+			goto bitmap_handle;
+		}
+		cam_id = kid;
+#else
+		u8 *addr = adapter_mac_addr(adapter);
+
+		cam_id = rtw_get_camid(adapter, addr, kid, gk);
+		if (1)
+			RTW_PRINT(FUNC_ADPT_FMT" group key with "MAC_FMT" assigned cam_id:%u\n"
+				, FUNC_ADPT_ARG(adapter), MAC_ARG(addr), cam_id);
+#endif
+	} else {
+		/*
+		* 1. STA mode WEP key
+		* 2. STA mode group RX key
+		* 3. sta key (pairwise, group RX)
+		*/
+		u8 *addr = sta ? sta->cmn.mac_addr : NULL;
+
+		if (!sta) {
+			if (!(mlmeinfo->state & WIFI_FW_ASSOC_SUCCESS)) {
+				/* bypass STA mode group key setting before connected(ex:WEP) because bssid is not ready */
+				goto bitmap_handle;
+			}
+			addr = get_bssid(&adapter->mlmepriv);/*A2*/
+		}
+		cam_id = rtw_get_camid(adapter, addr, kid, gk);
+	}
+
+
+bitmap_handle:
+	if (cam_id >= 0) {
+		*used = _rtw_sec_camid_is_used(cam_ctl, cam_id);
+		rtw_sec_cam_map_set(&cam_ctl->used, cam_id);
+	}
+
+	_exit_critical_bh(&cam_ctl->lock, &irqL);
+
+	return cam_id;
+}
+
+void rtw_camid_set(_adapter *adapter, u8 cam_id)
+{
+	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
+	struct cam_ctl_t *cam_ctl = &dvobj->cam_ctl;
+	_irqL irqL;
+
+	_enter_critical_bh(&cam_ctl->lock, &irqL);
+
+	if (cam_id < cam_ctl->num)
+		rtw_sec_cam_map_set(&cam_ctl->used, cam_id);
+
+	_exit_critical_bh(&cam_ctl->lock, &irqL);
+}
+
+void rtw_camid_free(_adapter *adapter, u8 cam_id)
+{
+	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
+	struct cam_ctl_t *cam_ctl = &dvobj->cam_ctl;
+	_irqL irqL;
+
+	_enter_critical_bh(&cam_ctl->lock, &irqL);
+
+	if (cam_id < cam_ctl->num)
+		rtw_sec_cam_map_clr(&cam_ctl->used, cam_id);
+
+	_exit_critical_bh(&cam_ctl->lock, &irqL);
+}
+
+/*Must pause TX/RX before use this API*/
+inline void rtw_sec_cam_swap(_adapter *adapter, u8 cam_id_a, u8 cam_id_b)
+{
+	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
+	struct cam_ctl_t *cam_ctl = &dvobj->cam_ctl;
+	struct sec_cam_ent cache_a, cache_b;
+	_irqL irqL;
+	bool cam_a_used, cam_b_used;
+
+	if (1)
+		RTW_INFO(ADPT_FMT" - sec_cam %d,%d swap\n", ADPT_ARG(adapter), cam_id_a, cam_id_b);
+
+	if (cam_id_a == cam_id_b)
+		return;
+
+#ifdef CONFIG_CONCURRENT_MODE
+	rtw_mi_update_ap_bmc_camid(adapter, cam_id_a, cam_id_b);
+#endif
+
+	/*setp-1. backup org cam_info*/
+	_enter_critical_bh(&cam_ctl->lock, &irqL);
+
+	cam_a_used = _rtw_sec_camid_is_used(cam_ctl, cam_id_a);
+	cam_b_used = _rtw_sec_camid_is_used(cam_ctl, cam_id_b);
+
+	if (cam_a_used)
+		_rtw_memcpy(&cache_a, &dvobj->cam_cache[cam_id_a], sizeof(struct sec_cam_ent));
+
+	if (cam_b_used)
+		_rtw_memcpy(&cache_b, &dvobj->cam_cache[cam_id_b], sizeof(struct sec_cam_ent));
+
+	_exit_critical_bh(&cam_ctl->lock, &irqL);
+
+	/*setp-2. clean cam_info*/
+	if (cam_a_used) {
+		rtw_camid_free(adapter, cam_id_a);
+		clear_cam_entry(adapter, cam_id_a);
+	}
+	if (cam_b_used) {
+		rtw_camid_free(adapter, cam_id_b);
+		clear_cam_entry(adapter, cam_id_b);
+	}
+
+	/*setp-3. set cam_info*/
+	if (cam_a_used) {
+		write_cam(adapter, cam_id_b, cache_a.ctrl, cache_a.mac, cache_a.key);
+		rtw_camid_set(adapter, cam_id_b);
+	}
+
+	if (cam_b_used) {
+		write_cam(adapter, cam_id_a, cache_b.ctrl, cache_b.mac, cache_b.key);
+		rtw_camid_set(adapter, cam_id_a);
+	}
+}
+
+s16 rtw_get_empty_cam_entry(_adapter *adapter, u8 start_camid)
+{
+	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
+	struct cam_ctl_t *cam_ctl = &dvobj->cam_ctl;
+	_irqL irqL;
+	int i;
+	s16 cam_id = -1;
+
+	_enter_critical_bh(&cam_ctl->lock, &irqL);
+	for (i = start_camid; i < cam_ctl->num; i++) {
+		if (_FALSE == _rtw_sec_camid_is_used(cam_ctl, i)) {
+			cam_id = i;
+			break;
+		}
+	}
+	_exit_critical_bh(&cam_ctl->lock, &irqL);
+
+	return cam_id;
+}
+void rtw_clean_dk_section(_adapter *adapter)
+{
+	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
+	struct cam_ctl_t *cam_ctl = dvobj_to_sec_camctl(dvobj);
+	s16 ept_cam_id;
+	int i;
+
+	for (i = 0; i < 4; i++) {
+		if (rtw_sec_camid_is_used(cam_ctl, i)) {
+			ept_cam_id = rtw_get_empty_cam_entry(adapter, 4);
+			if (ept_cam_id > 0)
+				rtw_sec_cam_swap(adapter, i, ept_cam_id);
+		}
+	}
+}
+void rtw_clean_hw_dk_cam(_adapter *adapter)
+{
+	int i;
+
+	for (i = 0; i < 4; i++)
+		rtw_sec_clr_cam_ent(adapter, i);
+		/*_clear_cam_entry(adapter, i);*/
+}
+
+void flush_all_cam_entry(_adapter *padapter)
+{
+#ifdef CONFIG_CONCURRENT_MODE
+	struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
+	struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
+	struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
+	struct security_priv *psecpriv = &padapter->securitypriv;
+
+	if (check_fwstate(pmlmepriv, WIFI_STATION_STATE)) {
+		struct sta_priv	*pstapriv = &padapter->stapriv;
+		struct sta_info		*psta;
+
+		psta = rtw_get_stainfo(pstapriv, pmlmeinfo->network.MacAddress);
+		if (psta) {
+			if (psta->state & WIFI_AP_STATE) {
+				/*clear cam when ap free per sta_info*/
+			} else
+				rtw_clearstakey_cmd(padapter, psta, _FALSE);
+		}
+	} else if (MLME_IS_AP(padapter) || MLME_IS_MESH(padapter)) {
+#if 1
+		int cam_id = -1;
+		u8 *addr = adapter_mac_addr(padapter);
+
+		while ((cam_id = rtw_camid_search(padapter, addr, -1, -1)) >= 0) {
+			RTW_PRINT("clear wep or group key for addr:"MAC_FMT", camid:%d\n", MAC_ARG(addr), cam_id);
+			clear_cam_entry(padapter, cam_id);
+			rtw_camid_free(padapter, cam_id);
+		}
+#else
+		/* clear default key */
+		int i, cam_id;
+		u8 null_addr[ETH_ALEN] = {0, 0, 0, 0, 0, 0};
+
+		for (i = 0; i < 4; i++) {
+			cam_id = rtw_camid_search(padapter, null_addr, i, -1);
+			if (cam_id >= 0) {
+				clear_cam_entry(padapter, cam_id);
+				rtw_camid_free(padapter, cam_id);
+			}
+		}
+		/* clear default key related key search setting */
+		rtw_hal_set_hwreg(padapter, HW_VAR_SEC_DK_CFG, (u8 *)_FALSE);
+#endif
+	}
+
+#else /*NON CONFIG_CONCURRENT_MODE*/
+
+	invalidate_cam_all(padapter);
+	/* clear default key related key search setting */
+	rtw_hal_set_hwreg(padapter, HW_VAR_SEC_DK_CFG, (u8 *)_FALSE);
+#endif
+}
+
+#if defined(CONFIG_P2P) && defined(CONFIG_WFD)
+void rtw_process_wfd_ie(_adapter *adapter, u8 *wfd_ie, u8 wfd_ielen, const char *tag)
+{
+	struct wifidirect_info *wdinfo = &adapter->wdinfo;
+
+	u8 *attr_content;
+	u32 attr_contentlen = 0;
+
+	if (!hal_chk_wl_func(adapter, WL_FUNC_MIRACAST))
+		return;
+
+	RTW_INFO("[%s] Found WFD IE\n", tag);
+	attr_content = rtw_get_wfd_attr_content(wfd_ie, wfd_ielen, WFD_ATTR_DEVICE_INFO, NULL, &attr_contentlen);
+	if (attr_content && attr_contentlen) {
+		wdinfo->wfd_info->peer_rtsp_ctrlport = RTW_GET_BE16(attr_content + 2);
+		RTW_INFO("[%s] Peer PORT NUM = %d\n", tag, wdinfo->wfd_info->peer_rtsp_ctrlport);
+	}
+}
+
+void rtw_process_wfd_ies(_adapter *adapter, u8 *ies, u8 ies_len, const char *tag)
+{
+	u8 *wfd_ie;
+	u32	wfd_ielen;
+
+	if (!hal_chk_wl_func(adapter, WL_FUNC_MIRACAST))
+		return;
+
+	wfd_ie = rtw_get_wfd_ie(ies, ies_len, NULL, &wfd_ielen);
+	while (wfd_ie) {
+		rtw_process_wfd_ie(adapter, wfd_ie, wfd_ielen, tag);
+		wfd_ie = rtw_get_wfd_ie(wfd_ie + wfd_ielen, (ies + ies_len) - (wfd_ie + wfd_ielen), NULL, &wfd_ielen);
+	}
+}
+#endif /* defined(CONFIG_P2P) && defined(CONFIG_WFD) */
+
+int WMM_param_handler(_adapter *padapter, PNDIS_802_11_VARIABLE_IEs	pIE)
+{
+	/* struct registry_priv	*pregpriv = &padapter->registrypriv; */
+	struct mlme_priv	*pmlmepriv = &(padapter->mlmepriv);
+	struct mlme_ext_priv	*pmlmeext = &padapter->mlmeextpriv;
+	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
+
+	if (pmlmepriv->qospriv.qos_option == 0) {
+		pmlmeinfo->WMM_enable = 0;
+		return _FALSE;
+	}
+
+	if (_rtw_memcmp(&(pmlmeinfo->WMM_param), (pIE->data + 6), sizeof(struct WMM_para_element)))
+		return _FALSE;
+	else
+		_rtw_memcpy(&(pmlmeinfo->WMM_param), (pIE->data + 6), sizeof(struct WMM_para_element));
+	pmlmeinfo->WMM_enable = 1;
+	return _TRUE;
+
+#if 0
+	if (pregpriv->wifi_spec == 1) {
+		if (pmlmeinfo->WMM_enable == 1) {
+			/* todo: compare the parameter set count & decide wheher to update or not */
+			return _FAIL;
+		} else {
+			pmlmeinfo->WMM_enable = 1;
+			_rtw_rtw_memcpy(&(pmlmeinfo->WMM_param), (pIE->data + 6), sizeof(struct WMM_para_element));
+			return _TRUE;
+		}
+	} else {
+		pmlmeinfo->WMM_enable = 0;
+		return _FAIL;
+	}
+#endif
+
+}
+
+void WMMOnAssocRsp(_adapter *padapter)
+{
+	u8	ACI, ACM, AIFS, ECWMin, ECWMax, aSifsTime;
+	u8	acm_mask;
+	u16	TXOP;
+	u32	acParm, i;
+	u32	edca[4], inx[4];
+	struct mlme_ext_priv	*pmlmeext = &padapter->mlmeextpriv;
+	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
+	struct xmit_priv		*pxmitpriv = &padapter->xmitpriv;
+	struct registry_priv	*pregpriv = &padapter->registrypriv;
+#ifdef CONFIG_WMMPS_STA
+	struct mlme_priv	*pmlmepriv = &(padapter->mlmepriv);
+	struct qos_priv	*pqospriv = &pmlmepriv->qospriv;
+#endif /* CONFIG_WMMPS_STA */	
+
+	acm_mask = 0;
+
+	if (is_supported_5g(pmlmeext->cur_wireless_mode) ||
+	    (pmlmeext->cur_wireless_mode & WIRELESS_11_24N))
+		aSifsTime = 16;
+	else
+		aSifsTime = 10;
+
+	if (pmlmeinfo->WMM_enable == 0) {
+		padapter->mlmepriv.acm_mask = 0;
+
+		AIFS = aSifsTime + (2 * pmlmeinfo->slotTime);
+
+		if (pmlmeext->cur_wireless_mode & (WIRELESS_11G | WIRELESS_11A)) {
+			ECWMin = 4;
+			ECWMax = 10;
+		} else if (pmlmeext->cur_wireless_mode & WIRELESS_11B) {
+			ECWMin = 5;
+			ECWMax = 10;
+		} else {
+			ECWMin = 4;
+			ECWMax = 10;
+		}
+
+		TXOP = 0;
+		acParm = AIFS | (ECWMin << 8) | (ECWMax << 12) | (TXOP << 16);
+		rtw_hal_set_hwreg(padapter, HW_VAR_AC_PARAM_BE, (u8 *)(&acParm));
+		rtw_hal_set_hwreg(padapter, HW_VAR_AC_PARAM_BK, (u8 *)(&acParm));
+		rtw_hal_set_hwreg(padapter, HW_VAR_AC_PARAM_VI, (u8 *)(&acParm));
+
+		ECWMin = 2;
+		ECWMax = 3;
+		TXOP = 0x2f;
+		acParm = AIFS | (ECWMin << 8) | (ECWMax << 12) | (TXOP << 16);
+		rtw_hal_set_hwreg(padapter, HW_VAR_AC_PARAM_VO, (u8 *)(&acParm));
+	} else {
+		edca[0] = edca[1] = edca[2] = edca[3] = 0;
+
+		for (i = 0; i < 4; i++) {
+			ACI = (pmlmeinfo->WMM_param.ac_param[i].ACI_AIFSN >> 5) & 0x03;
+			ACM = (pmlmeinfo->WMM_param.ac_param[i].ACI_AIFSN >> 4) & 0x01;
+
+			/* AIFS = AIFSN * slot time + SIFS - r2t phy delay */
+			AIFS = (pmlmeinfo->WMM_param.ac_param[i].ACI_AIFSN & 0x0f) * pmlmeinfo->slotTime + aSifsTime;
+
+			ECWMin = (pmlmeinfo->WMM_param.ac_param[i].CW & 0x0f);
+			ECWMax = (pmlmeinfo->WMM_param.ac_param[i].CW & 0xf0) >> 4;
+			TXOP = le16_to_cpu(pmlmeinfo->WMM_param.ac_param[i].TXOP_limit);
+
+			acParm = AIFS | (ECWMin << 8) | (ECWMax << 12) | (TXOP << 16);
+
+			switch (ACI) {
+			case 0x0:
+				rtw_hal_set_hwreg(padapter, HW_VAR_AC_PARAM_BE, (u8 *)(&acParm));
+				acm_mask |= (ACM ? BIT(1) : 0);
+				edca[XMIT_BE_QUEUE] = acParm;
+				break;
+
+			case 0x1:
+				rtw_hal_set_hwreg(padapter, HW_VAR_AC_PARAM_BK, (u8 *)(&acParm));
+				/* acm_mask |= (ACM? BIT(0):0); */
+				edca[XMIT_BK_QUEUE] = acParm;
+				break;
+
+			case 0x2:
+				rtw_hal_set_hwreg(padapter, HW_VAR_AC_PARAM_VI, (u8 *)(&acParm));
+				acm_mask |= (ACM ? BIT(2) : 0);
+				edca[XMIT_VI_QUEUE] = acParm;
+				break;
+
+			case 0x3:
+				rtw_hal_set_hwreg(padapter, HW_VAR_AC_PARAM_VO, (u8 *)(&acParm));
+				acm_mask |= (ACM ? BIT(3) : 0);
+				edca[XMIT_VO_QUEUE] = acParm;
+				break;
+			}
+
+			RTW_INFO("WMM(%x): %x, %x\n", ACI, ACM, acParm);
+		}
+
+		if (padapter->registrypriv.acm_method == 1)
+			rtw_hal_set_hwreg(padapter, HW_VAR_ACM_CTRL, (u8 *)(&acm_mask));
+		else
+			padapter->mlmepriv.acm_mask = acm_mask;
+
+		inx[0] = 0;
+		inx[1] = 1;
+		inx[2] = 2;
+		inx[3] = 3;
+
+		if (pregpriv->wifi_spec == 1) {
+			u32	j, tmp, change_inx = _FALSE;
+
+			/* entry indx: 0->vo, 1->vi, 2->be, 3->bk. */
+			for (i = 0; i < 4; i++) {
+				for (j = i + 1; j < 4; j++) {
+					/* compare CW and AIFS */
+					if ((edca[j] & 0xFFFF) < (edca[i] & 0xFFFF))
+						change_inx = _TRUE;
+					else if ((edca[j] & 0xFFFF) == (edca[i] & 0xFFFF)) {
+						/* compare TXOP */
+						if ((edca[j] >> 16) > (edca[i] >> 16))
+							change_inx = _TRUE;
+					}
+
+					if (change_inx) {
+						tmp = edca[i];
+						edca[i] = edca[j];
+						edca[j] = tmp;
+
+						tmp = inx[i];
+						inx[i] = inx[j];
+						inx[j] = tmp;
+
+						change_inx = _FALSE;
+					}
+				}
+			}
+		}
+
+		for (i = 0; i < 4; i++) {
+			pxmitpriv->wmm_para_seq[i] = inx[i];
+			RTW_INFO("wmm_para_seq(%d): %d\n", i, pxmitpriv->wmm_para_seq[i]);
+		}
+		
+#ifdef CONFIG_WMMPS_STA
+		/* if AP supports UAPSD function, driver must set each uapsd TID to coresponding mac register 0x693 */
+		if (pmlmeinfo->WMM_param.QoS_info & AP_SUPPORTED_UAPSD) {
+			pqospriv->uapsd_ap_supported = 1;
+			rtw_hal_set_hwreg(padapter, HW_VAR_UAPSD_TID, NULL);
+		}
+#endif /* CONFIG_WMMPS_STA */
+	}
+}
+
+static void bwmode_update_check(_adapter *padapter, PNDIS_802_11_VARIABLE_IEs pIE)
+{
+#ifdef CONFIG_80211N_HT
+	unsigned char	 new_bwmode;
+	unsigned char  new_ch_offset;
+	struct HT_info_element	*pHT_info;
+	struct mlme_priv	*pmlmepriv = &(padapter->mlmepriv);
+	struct mlme_ext_priv	*pmlmeext = &padapter->mlmeextpriv;
+	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
+	struct registry_priv *pregistrypriv = &padapter->registrypriv;
+	struct ht_priv			*phtpriv = &pmlmepriv->htpriv;
+	u8	cbw40_enable = 0;
+
+	if (!pIE)
+		return;
+
+	if (phtpriv->ht_option == _FALSE)
+		return;
+
+	if (pmlmeext->cur_bwmode >= CHANNEL_WIDTH_80)
+		return;
+
+	if (pIE->Length > sizeof(struct HT_info_element))
+		return;
+
+	pHT_info = (struct HT_info_element *)pIE->data;
+
+	if (hal_chk_bw_cap(padapter, BW_CAP_40M)) {
+		if (pmlmeext->cur_channel > 14) {
+			if (REGSTY_IS_BW_5G_SUPPORT(pregistrypriv, CHANNEL_WIDTH_40))
+				cbw40_enable = 1;
+		} else {
+			if (REGSTY_IS_BW_2G_SUPPORT(pregistrypriv, CHANNEL_WIDTH_40))
+				cbw40_enable = 1;
+		}
+	}
+
+	if ((pHT_info->infos[0] & BIT(2)) && cbw40_enable) {
+		new_bwmode = CHANNEL_WIDTH_40;
+
+		switch (pHT_info->infos[0] & 0x3) {
+		case 1:
+			new_ch_offset = HAL_PRIME_CHNL_OFFSET_LOWER;
+			break;
+
+		case 3:
+			new_ch_offset = HAL_PRIME_CHNL_OFFSET_UPPER;
+			break;
+
+		default:
+			new_bwmode = CHANNEL_WIDTH_20;
+			new_ch_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
+			break;
+		}
+	} else {
+		new_bwmode = CHANNEL_WIDTH_20;
+		new_ch_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
+	}
+
+
+	if ((new_bwmode != pmlmeext->cur_bwmode || new_ch_offset != pmlmeext->cur_ch_offset)
+	    && new_bwmode < pmlmeext->cur_bwmode
+	   ) {
+		pmlmeinfo->bwmode_updated = _TRUE;
+
+		pmlmeext->cur_bwmode = new_bwmode;
+		pmlmeext->cur_ch_offset = new_ch_offset;
+
+		/* update HT info also */
+		HT_info_handler(padapter, pIE);
+	} else
+		pmlmeinfo->bwmode_updated = _FALSE;
+
+
+	if (_TRUE == pmlmeinfo->bwmode_updated) {
+		struct sta_info *psta;
+		WLAN_BSSID_EX	*cur_network = &(pmlmeinfo->network);
+		struct sta_priv	*pstapriv = &padapter->stapriv;
+
+		/* set_channel_bwmode(padapter, pmlmeext->cur_channel, pmlmeext->cur_ch_offset, pmlmeext->cur_bwmode); */
+
+
+		/* update ap's stainfo */
+		psta = rtw_get_stainfo(pstapriv, cur_network->MacAddress);
+		if (psta) {
+			struct ht_priv	*phtpriv_sta = &psta->htpriv;
+
+			if (phtpriv_sta->ht_option) {
+				/* bwmode				 */
+				psta->cmn.bw_mode = pmlmeext->cur_bwmode;
+				phtpriv_sta->ch_offset = pmlmeext->cur_ch_offset;
+			} else {
+				psta->cmn.bw_mode = CHANNEL_WIDTH_20;
+				phtpriv_sta->ch_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
+			}
+
+			rtw_dm_ra_mask_wk_cmd(padapter, (u8 *)psta);
+		}
+
+		/* pmlmeinfo->bwmode_updated = _FALSE; */ /* bwmode_updated done, reset it! */
+	}
+#endif /* CONFIG_80211N_HT */
+}
+
+#ifdef ROKU_PRIVATE
+void Supported_rate_infra_ap(_adapter *padapter, PNDIS_802_11_VARIABLE_IEs pIE)
+{
+	unsigned int	i;
+	struct mlme_ext_priv		*pmlmeext = &padapter->mlmeextpriv;
+	struct mlme_ext_info		*pmlmeinfo = &(pmlmeext->mlmext_info);
+
+	if (pIE == NULL)
+		return;
+
+	for (i = 0 ; i < pIE->Length; i++)
+		pmlmeinfo->SupportedRates_infra_ap[i] = (pIE->data[i]);
+
+}
+
+void Extended_Supported_rate_infra_ap(_adapter *padapter, PNDIS_802_11_VARIABLE_IEs pIE)
+{
+	unsigned int i, j;
+	struct mlme_ext_priv		*pmlmeext = &padapter->mlmeextpriv;
+	struct mlme_ext_info		*pmlmeinfo = &(pmlmeext->mlmext_info);
+
+	if (pIE == NULL)
+		return;
+
+	if (pIE->Length > 0) {
+		for (i = 0; i < NDIS_802_11_LENGTH_RATES_EX; i++) {
+			if (pmlmeinfo->SupportedRates_infra_ap[i] == 0)
+				break;
+		}
+		for (j = 0; j < pIE->Length; j++)
+			pmlmeinfo->SupportedRates_infra_ap[i+j] = (pIE->data[j]);
+	}
+
+}
+
+void HT_get_ss_from_mcs_set(u8 *mcs_set, u8 *Rx_ss)
+{
+	u8 i, j;
+	u8 r_ss = 0, t_ss = 0;
+
+	for (i = 0; i < 4; i++) {
+		if ((mcs_set[3-i] & 0xff) != 0x00) {
+			r_ss = 4-i;
+			break;
+		}
+	}
+
+	*Rx_ss = r_ss;
+}
+
+void HT_caps_handler_infra_ap(_adapter *padapter, PNDIS_802_11_VARIABLE_IEs pIE)
+{
+	unsigned int	i;
+	u8	cur_stbc_cap_infra_ap = 0;
+	struct mlme_priv		*pmlmepriv = &padapter->mlmepriv;
+	struct ht_priv_infra_ap		*phtpriv = &pmlmepriv->htpriv_infra_ap;
+
+	struct mlme_ext_priv		*pmlmeext = &padapter->mlmeextpriv;
+	struct mlme_ext_info		*pmlmeinfo = &(pmlmeext->mlmext_info);
+
+	if (pIE == NULL)
+		return;
+
+	pmlmeinfo->ht_vht_received |= BIT(0);
+
+	/*copy MCS_SET*/
+	for (i = 3; i < 19; i++)
+		phtpriv->MCS_set_infra_ap[i-3] = (pIE->data[i]);
+
+	/*get number of stream from mcs set*/
+	HT_get_ss_from_mcs_set(phtpriv->MCS_set_infra_ap, &phtpriv->Rx_ss_infra_ap);
+
+	phtpriv->rx_highest_data_rate_infra_ap = le16_to_cpu(GET_HT_CAP_ELE_RX_HIGHEST_DATA_RATE(pIE->data));
+
+	phtpriv->ldpc_cap_infra_ap = GET_HT_CAP_ELE_LDPC_CAP(pIE->data);
+
+	if (GET_HT_CAP_ELE_RX_STBC(pIE->data))
+		SET_FLAG(cur_stbc_cap_infra_ap, STBC_HT_ENABLE_RX);
+	if (GET_HT_CAP_ELE_TX_STBC(pIE->data))
+		SET_FLAG(cur_stbc_cap_infra_ap, STBC_HT_ENABLE_TX);
+	phtpriv->stbc_cap_infra_ap = cur_stbc_cap_infra_ap;
+
+	/*store ap info SGI 20m 40m*/
+	phtpriv->sgi_20m_infra_ap = GET_HT_CAP_ELE_SHORT_GI20M(pIE->data);
+	phtpriv->sgi_40m_infra_ap = GET_HT_CAP_ELE_SHORT_GI40M(pIE->data);
+
+	/*store ap info for supported channel bandwidth*/
+	phtpriv->channel_width_infra_ap = GET_HT_CAP_ELE_CHL_WIDTH(pIE->data);
+}
+#endif /* ROKU_PRIVATE */
+
+void HT_caps_handler(_adapter *padapter, PNDIS_802_11_VARIABLE_IEs pIE)
+{
+#ifdef CONFIG_80211N_HT
+	unsigned int	i;
+	u8	rf_type = RF_1T1R;
+	u8	max_AMPDU_len, min_MPDU_spacing;
+	u8	cur_ldpc_cap = 0, cur_stbc_cap = 0, cur_beamform_cap = 0, tx_nss = 0;
+	struct mlme_ext_priv	*pmlmeext = &padapter->mlmeextpriv;
+	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
+	struct mlme_priv		*pmlmepriv = &padapter->mlmepriv;
+	struct ht_priv			*phtpriv = &pmlmepriv->htpriv;
+#ifdef CONFIG_DISABLE_MCS13TO15
+	struct registry_priv	*pregistrypriv = &padapter->registrypriv;
+#endif
+	struct hal_spec_t *hal_spec = GET_HAL_SPEC(padapter);
+
+	if (pIE == NULL)
+		return;
+
+	if (phtpriv->ht_option == _FALSE)
+		return;
+
+	pmlmeinfo->HT_caps_enable = 1;
+
+	for (i = 0; i < (pIE->Length); i++) {
+		if (i != 2) {
+			/*	Commented by Albert 2010/07/12 */
+			/*	Got the endian issue here. */
+			pmlmeinfo->HT_caps.u.HT_cap[i] &= (pIE->data[i]);
+		} else {
+			/* AMPDU Parameters field */
+
+			/* Get MIN of MAX AMPDU Length Exp */
+			if ((pmlmeinfo->HT_caps.u.HT_cap_element.AMPDU_para & 0x3) > (pIE->data[i] & 0x3))
+				max_AMPDU_len = (pIE->data[i] & 0x3);
+			else
+				max_AMPDU_len = (pmlmeinfo->HT_caps.u.HT_cap_element.AMPDU_para & 0x3);
+
+			/* Get MAX of MIN MPDU Start Spacing */
+			if ((pmlmeinfo->HT_caps.u.HT_cap_element.AMPDU_para & 0x1c) > (pIE->data[i] & 0x1c))
+				min_MPDU_spacing = (pmlmeinfo->HT_caps.u.HT_cap_element.AMPDU_para & 0x1c);
+			else
+				min_MPDU_spacing = (pIE->data[i] & 0x1c);
+
+			pmlmeinfo->HT_caps.u.HT_cap_element.AMPDU_para = max_AMPDU_len | min_MPDU_spacing;
+		}
+	}
+
+	/*	Commented by Albert 2010/07/12 */
+	/*	Have to handle the endian issue after copying. */
+	/*	HT_ext_caps didn't be used yet.	 */
+	pmlmeinfo->HT_caps.u.HT_cap_element.HT_caps_info = le16_to_cpu(pmlmeinfo->HT_caps.u.HT_cap_element.HT_caps_info);
+	pmlmeinfo->HT_caps.u.HT_cap_element.HT_ext_caps = le16_to_cpu(pmlmeinfo->HT_caps.u.HT_cap_element.HT_ext_caps);
+
+	/* update the MCS set */
+	for (i = 0; i < 16; i++)
+		pmlmeinfo->HT_caps.u.HT_cap_element.MCS_rate[i] &= pmlmeext->default_supported_mcs_set[i];
+
+	rtw_hal_get_hwreg(padapter, HW_VAR_RF_TYPE, (u8 *)(&rf_type));
+	tx_nss = rtw_min(rf_type_to_rf_tx_cnt(rf_type), hal_spec->tx_nss_num);
+
+	switch (tx_nss) {
+	case 1:
+		set_mcs_rate_by_mask(pmlmeinfo->HT_caps.u.HT_cap_element.MCS_rate, MCS_RATE_1R);
+		break;
+	case 2:
+		#ifdef CONFIG_DISABLE_MCS13TO15
+		if (pmlmeext->cur_bwmode == CHANNEL_WIDTH_40 && pregistrypriv->wifi_spec != 1)
+			set_mcs_rate_by_mask(pmlmeinfo->HT_caps.u.HT_cap_element.MCS_rate, MCS_RATE_2R_13TO15_OFF);
+		else
+		#endif
+			set_mcs_rate_by_mask(pmlmeinfo->HT_caps.u.HT_cap_element.MCS_rate, MCS_RATE_2R);
+		break;
+	case 3:
+		set_mcs_rate_by_mask(pmlmeinfo->HT_caps.u.HT_cap_element.MCS_rate, MCS_RATE_3R);
+		break;
+	case 4:
+		set_mcs_rate_by_mask(pmlmeinfo->HT_caps.u.HT_cap_element.MCS_rate, MCS_RATE_4R);
+		break;
+	default:
+		RTW_WARN("rf_type:%d or tx_nss:%u is not expected\n", rf_type, hal_spec->tx_nss_num);
+	}
+
+	if (check_fwstate(pmlmepriv, WIFI_AP_STATE)) {
+		/* Config STBC setting */
+		if (TEST_FLAG(phtpriv->stbc_cap, STBC_HT_ENABLE_TX) && GET_HT_CAP_ELE_RX_STBC(pIE->data)) {
+			SET_FLAG(cur_stbc_cap, STBC_HT_ENABLE_TX);
+			RTW_INFO("Enable HT Tx STBC !\n");
+		}
+		phtpriv->stbc_cap = cur_stbc_cap;
+
+#ifdef CONFIG_BEAMFORMING
+		/* Config Tx beamforming setting */
+		if (TEST_FLAG(phtpriv->beamform_cap, BEAMFORMING_HT_BEAMFORMER_ENABLE) &&
+		    GET_HT_CAP_TXBF_EXPLICIT_COMP_STEERING_CAP(pIE->data)) {
+			SET_FLAG(cur_beamform_cap, BEAMFORMING_HT_BEAMFORMER_ENABLE);
+			/* Shift to BEAMFORMING_HT_BEAMFORMEE_CHNL_EST_CAP*/
+			SET_FLAG(cur_beamform_cap, GET_HT_CAP_TXBF_CHNL_ESTIMATION_NUM_ANTENNAS(pIE->data) << 6);
+		}
+
+		if (TEST_FLAG(phtpriv->beamform_cap, BEAMFORMING_HT_BEAMFORMEE_ENABLE) &&
+		    GET_HT_CAP_TXBF_EXPLICIT_COMP_FEEDBACK_CAP(pIE->data)) {
+			SET_FLAG(cur_beamform_cap, BEAMFORMING_HT_BEAMFORMEE_ENABLE);
+			/* Shift to BEAMFORMING_HT_BEAMFORMER_STEER_NUM*/
+			SET_FLAG(cur_beamform_cap, GET_HT_CAP_TXBF_COMP_STEERING_NUM_ANTENNAS(pIE->data) << 4);
+		}
+		phtpriv->beamform_cap = cur_beamform_cap;
+		if (cur_beamform_cap)
+			RTW_INFO("AP HT Beamforming Cap = 0x%02X\n", cur_beamform_cap);
+#endif /*CONFIG_BEAMFORMING*/
+	} else {
+		/*WIFI_STATION_STATEorI_ADHOC_STATE or WIFI_ADHOC_MASTER_STATE*/
+		/* Config LDPC Coding Capability */
+		if (TEST_FLAG(phtpriv->ldpc_cap, LDPC_HT_ENABLE_TX) && GET_HT_CAP_ELE_LDPC_CAP(pIE->data)) {
+			SET_FLAG(cur_ldpc_cap, (LDPC_HT_ENABLE_TX | LDPC_HT_CAP_TX));
+			RTW_INFO("Enable HT Tx LDPC!\n");
+		}
+		phtpriv->ldpc_cap = cur_ldpc_cap;
+
+		/* Config STBC setting */
+		if (TEST_FLAG(phtpriv->stbc_cap, STBC_HT_ENABLE_TX) && GET_HT_CAP_ELE_RX_STBC(pIE->data)) {
+			SET_FLAG(cur_stbc_cap, (STBC_HT_ENABLE_TX | STBC_HT_CAP_TX));
+			RTW_INFO("Enable HT Tx STBC!\n");
+		}
+		phtpriv->stbc_cap = cur_stbc_cap;
+
+#ifdef CONFIG_BEAMFORMING
+#ifdef RTW_BEAMFORMING_VERSION_2
+		/* Config beamforming setting */
+		if (TEST_FLAG(phtpriv->beamform_cap, BEAMFORMING_HT_BEAMFORMEE_ENABLE) &&
+		    GET_HT_CAP_TXBF_EXPLICIT_COMP_STEERING_CAP(pIE->data)) {
+			SET_FLAG(cur_beamform_cap, BEAMFORMING_HT_BEAMFORMEE_ENABLE);
+			/* Shift to BEAMFORMING_HT_BEAMFORMEE_CHNL_EST_CAP*/
+			SET_FLAG(cur_beamform_cap, GET_HT_CAP_TXBF_CHNL_ESTIMATION_NUM_ANTENNAS(pIE->data) << 6);
+		}
+
+		if (TEST_FLAG(phtpriv->beamform_cap, BEAMFORMING_HT_BEAMFORMER_ENABLE) &&
+		    GET_HT_CAP_TXBF_EXPLICIT_COMP_FEEDBACK_CAP(pIE->data)) {
+			SET_FLAG(cur_beamform_cap, BEAMFORMING_HT_BEAMFORMER_ENABLE);
+			/* Shift to BEAMFORMING_HT_BEAMFORMER_STEER_NUM*/
+			SET_FLAG(cur_beamform_cap, GET_HT_CAP_TXBF_COMP_STEERING_NUM_ANTENNAS(pIE->data) << 4);
+		}
+#else /* !RTW_BEAMFORMING_VERSION_2 */
+		/* Config Tx beamforming setting */
+		if (TEST_FLAG(phtpriv->beamform_cap, BEAMFORMING_HT_BEAMFORMEE_ENABLE) &&
+		    GET_HT_CAP_TXBF_EXPLICIT_COMP_STEERING_CAP(pIE->data)) {
+			SET_FLAG(cur_beamform_cap, BEAMFORMING_HT_BEAMFORMER_ENABLE);
+			/* Shift to BEAMFORMING_HT_BEAMFORMEE_CHNL_EST_CAP*/
+			SET_FLAG(cur_beamform_cap, GET_HT_CAP_TXBF_CHNL_ESTIMATION_NUM_ANTENNAS(pIE->data) << 6);
+		}
+
+		if (TEST_FLAG(phtpriv->beamform_cap, BEAMFORMING_HT_BEAMFORMER_ENABLE) &&
+		    GET_HT_CAP_TXBF_EXPLICIT_COMP_FEEDBACK_CAP(pIE->data)) {
+			SET_FLAG(cur_beamform_cap, BEAMFORMING_HT_BEAMFORMEE_ENABLE);
+			/* Shift to BEAMFORMING_HT_BEAMFORMER_STEER_NUM*/
+			SET_FLAG(cur_beamform_cap, GET_HT_CAP_TXBF_COMP_STEERING_NUM_ANTENNAS(pIE->data) << 4);
+		}
+#endif /* !RTW_BEAMFORMING_VERSION_2 */
+		phtpriv->beamform_cap = cur_beamform_cap;
+		if (cur_beamform_cap)
+			RTW_INFO("Client HT Beamforming Cap = 0x%02X\n", cur_beamform_cap);
+#endif /*CONFIG_BEAMFORMING*/
+	}
+
+#endif /* CONFIG_80211N_HT */
+}
+
+void HT_info_handler(_adapter *padapter, PNDIS_802_11_VARIABLE_IEs pIE)
+{
+#ifdef CONFIG_80211N_HT
+	struct mlme_ext_priv	*pmlmeext = &padapter->mlmeextpriv;
+	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
+	struct mlme_priv		*pmlmepriv = &padapter->mlmepriv;
+	struct ht_priv			*phtpriv = &pmlmepriv->htpriv;
+
+	if (pIE == NULL)
+		return;
+
+	if (phtpriv->ht_option == _FALSE)
+		return;
+
+
+	if (pIE->Length > sizeof(struct HT_info_element))
+		return;
+
+	pmlmeinfo->HT_info_enable = 1;
+	_rtw_memcpy(&(pmlmeinfo->HT_info), pIE->data, pIE->Length);
+#endif /* CONFIG_80211N_HT */
+	return;
+}
+
+void HTOnAssocRsp(_adapter *padapter)
+{
+	unsigned char		max_AMPDU_len;
+	unsigned char		min_MPDU_spacing;
+	/* struct registry_priv	 *pregpriv = &padapter->registrypriv; */
+	struct mlme_ext_priv	*pmlmeext = &padapter->mlmeextpriv;
+	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
+
+	RTW_INFO("%s\n", __FUNCTION__);
+
+	if ((pmlmeinfo->HT_info_enable) && (pmlmeinfo->HT_caps_enable))
+		pmlmeinfo->HT_enable = 1;
+	else {
+		pmlmeinfo->HT_enable = 0;
+		/* set_channel_bwmode(padapter, pmlmeext->cur_channel, pmlmeext->cur_ch_offset, pmlmeext->cur_bwmode); */
+		return;
+	}
+
+	/* handle A-MPDU parameter field */
+	/*
+		AMPDU_para [1:0]:Max AMPDU Len => 0:8k , 1:16k, 2:32k, 3:64k
+		AMPDU_para [4:2]:Min MPDU Start Spacing
+	*/
+	max_AMPDU_len = pmlmeinfo->HT_caps.u.HT_cap_element.AMPDU_para & 0x03;
+
+	min_MPDU_spacing = (pmlmeinfo->HT_caps.u.HT_cap_element.AMPDU_para & 0x1c) >> 2;
+
+	rtw_hal_set_hwreg(padapter, HW_VAR_AMPDU_MIN_SPACE, (u8 *)(&min_MPDU_spacing));
+#ifdef CONFIG_80211N_HT
+	rtw_hal_set_hwreg(padapter, HW_VAR_AMPDU_FACTOR, (u8 *)(&max_AMPDU_len));
+#endif /* CONFIG_80211N_HT */
+#if 0 /* move to rtw_update_ht_cap() */
+	if ((pregpriv->bw_mode > 0) &&
+	    (pmlmeinfo->HT_caps.u.HT_cap_element.HT_caps_info & BIT(1)) &&
+	    (pmlmeinfo->HT_info.infos[0] & BIT(2))) {
+		/* switch to the 40M Hz mode accoring to the AP */
+		pmlmeext->cur_bwmode = CHANNEL_WIDTH_40;
+		switch ((pmlmeinfo->HT_info.infos[0] & 0x3)) {
+		case EXTCHNL_OFFSET_UPPER:
+			pmlmeext->cur_ch_offset = HAL_PRIME_CHNL_OFFSET_LOWER;
+			break;
+
+		case EXTCHNL_OFFSET_LOWER:
+			pmlmeext->cur_ch_offset = HAL_PRIME_CHNL_OFFSET_UPPER;
+			break;
+
+		default:
+			pmlmeext->cur_ch_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
+			break;
+		}
+	}
+#endif
+
+	/* set_channel_bwmode(padapter, pmlmeext->cur_channel, pmlmeext->cur_ch_offset, pmlmeext->cur_bwmode); */
+
+#if 0 /* move to rtw_update_ht_cap() */
+	/*  */
+	/* Config SM Power Save setting */
+	/*  */
+	pmlmeinfo->SM_PS = (pmlmeinfo->HT_caps.u.HT_cap_element.HT_caps_info & 0x0C) >> 2;
+	if (pmlmeinfo->SM_PS == WLAN_HT_CAP_SM_PS_STATIC) {
+#if 0
+		u8 i;
+		/* update the MCS rates */
+		for (i = 0; i < 16; i++)
+			pmlmeinfo->HT_caps.HT_cap_element.MCS_rate[i] &= MCS_rate_1R[i];
+#endif
+		RTW_INFO("%s(): WLAN_HT_CAP_SM_PS_STATIC\n", __FUNCTION__);
+	}
+
+	/*  */
+	/* Config current HT Protection mode. */
+	/*  */
+	pmlmeinfo->HT_protection = pmlmeinfo->HT_info.infos[1] & 0x3;
+#endif
+
+}
+
+void ERP_IE_handler(_adapter *padapter, PNDIS_802_11_VARIABLE_IEs pIE)
+{
+	struct mlme_ext_priv	*pmlmeext = &padapter->mlmeextpriv;
+	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
+
+	if (pIE->Length > 1)
+		return;
+
+	pmlmeinfo->ERP_enable = 1;
+	_rtw_memcpy(&(pmlmeinfo->ERP_IE), pIE->data, pIE->Length);
+}
+
+void VCS_update(_adapter *padapter, struct sta_info *psta)
+{
+	struct registry_priv	*pregpriv = &padapter->registrypriv;
+	struct mlme_ext_priv	*pmlmeext = &padapter->mlmeextpriv;
+	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
+
+	switch (pregpriv->vrtl_carrier_sense) { /* 0:off 1:on 2:auto */
+	case 0: /* off */
+		psta->rtsen = 0;
+		psta->cts2self = 0;
+		break;
+
+	case 1: /* on */
+		if (pregpriv->vcs_type == 1) { /* 1:RTS/CTS 2:CTS to self */
+			psta->rtsen = 1;
+			psta->cts2self = 0;
+		} else {
+			psta->rtsen = 0;
+			psta->cts2self = 1;
+		}
+		break;
+
+	case 2: /* auto */
+	default:
+		if (((pmlmeinfo->ERP_enable) && (pmlmeinfo->ERP_IE & BIT(1)))
+			/*||(pmlmepriv->ht_op_mode & HT_INFO_OPERATION_MODE_NON_GF_DEVS_PRESENT)*/
+		) {
+			if (pregpriv->vcs_type == 1) {
+				psta->rtsen = 1;
+				psta->cts2self = 0;
+			} else {
+				psta->rtsen = 0;
+				psta->cts2self = 1;
+			}
+		} else {
+			psta->rtsen = 0;
+			psta->cts2self = 0;
+		}
+		break;
+	}
+}
+
+void	update_ldpc_stbc_cap(struct sta_info *psta)
+{
+#ifdef CONFIG_80211N_HT
+
+#ifdef CONFIG_80211AC_VHT
+	if (psta->vhtpriv.vht_option) {
+		if (TEST_FLAG(psta->vhtpriv.ldpc_cap, LDPC_VHT_ENABLE_TX))
+			psta->cmn.ldpc_en = VHT_LDPC_EN;
+		else
+			psta->cmn.ldpc_en = 0;
+
+		if (TEST_FLAG(psta->vhtpriv.stbc_cap, STBC_VHT_ENABLE_TX))
+			psta->cmn.stbc_en = VHT_STBC_EN;
+		else
+			psta->cmn.stbc_en = 0;
+	} else
+#endif /* CONFIG_80211AC_VHT */
+		if (psta->htpriv.ht_option) {
+			if (TEST_FLAG(psta->htpriv.ldpc_cap, LDPC_HT_ENABLE_TX))
+				psta->cmn.ldpc_en = HT_LDPC_EN;
+			else
+				psta->cmn.ldpc_en = 0;
+
+			if (TEST_FLAG(psta->htpriv.stbc_cap, STBC_HT_ENABLE_TX))
+				psta->cmn.stbc_en = HT_STBC_EN;
+			else
+				psta->cmn.stbc_en = 0;
+		} else {
+			psta->cmn.ldpc_en = 0;
+			psta->cmn.stbc_en = 0;
+		}
+
+#endif /* CONFIG_80211N_HT */
+}
+
+int check_ielen(u8 *start, uint len)
+{
+	int left = len;
+	u8 *pos = start;
+	u8 id, elen;
+
+	while (left >= 2) {
+		id = *pos++;
+		elen = *pos++;
+		left -= 2;
+
+		if (elen > left) {
+			RTW_INFO("IEEE 802.11 element parse failed (id=%d elen=%d left=%lu)\n",
+					id, elen, (unsigned long) left);
+			return _FALSE;
+		}
+		if ((id == WLAN_EID_VENDOR_SPECIFIC) && (elen < 3))
+				return _FALSE;
+
+		left -= elen;
+		pos += elen;
+	}
+	if (left)
+		return _FALSE;
+
+	return _TRUE;
+}
+
+int validate_beacon_len(u8 *pframe, u32 len)
+{
+	u8 ie_offset = _BEACON_IE_OFFSET_ + sizeof(struct rtw_ieee80211_hdr_3addr);
+
+	if (len < ie_offset) {
+		RTW_INFO("%s: incorrect beacon length(%d)\n", __func__, len);
+		return _FALSE;
+	}
+
+	if (check_ielen(pframe + ie_offset, len - ie_offset) == _FALSE)
+		return _FALSE;
+
+	return _TRUE;
+}
+
+
+u8 support_rate_ranges[] = {
+	IEEE80211_CCK_RATE_1MB,
+	IEEE80211_CCK_RATE_2MB,
+	IEEE80211_CCK_RATE_5MB,
+	IEEE80211_CCK_RATE_11MB,
+	IEEE80211_OFDM_RATE_6MB,
+	IEEE80211_OFDM_RATE_9MB,
+	IEEE80211_OFDM_RATE_12MB,
+	IEEE80211_OFDM_RATE_18MB,
+	IEEE80211_OFDM_RATE_24MB,
+	IEEE80211_OFDM_RATE_36MB,
+	IEEE80211_OFDM_RATE_48MB,
+	IEEE80211_OFDM_RATE_54MB,
+	IEEE80211_PBCC_RATE_22MB,
+  IEEE80211_PBCC_RATE_33MB
+};
+
+inline bool match_ranges(u16 EID, u32 value)
+{
+	int i;
+	int nr_range;
+
+	switch (EID) {
+	case _EXT_SUPPORTEDRATES_IE_:
+	case _SUPPORTEDRATES_IE_:
+		nr_range = sizeof(support_rate_ranges)/sizeof(u8);
+		for (i = 0; i < nr_range; i++) {
+			/*	clear bit7 before searching.	*/
+			value &= ~BIT(7);
+			if (value == support_rate_ranges[i])
+				return _TRUE;
+		}
+		break;
+	default:
+		break;
+	};
+	return _FALSE;
+}
+
+/*
+ * rtw_validate_value: validate the IE contain.
+ *
+ *	Input : 
+ *		EID : Element ID
+ *		p	: IE buffer (without EID & length)
+ *		len	: IE length
+ *	return: 
+ * 		_TRUE	: All Values are validated.
+ *		_FALSE	: At least one value is NOT validated.
+ */
+bool rtw_validate_value(u16 EID, u8 *p, u16 len)
+{
+	u8 rate;
+	u32 i, nr_val;
+
+	switch (EID) {
+	case _EXT_SUPPORTEDRATES_IE_:
+	case _SUPPORTEDRATES_IE_:
+		nr_val = len;
+		for (i=0; i<nr_val; i++) {
+			rate = *(p+i);
+			if (match_ranges(EID, rate) == _FALSE)
+				return _FALSE;
+		}
+		break;
+	default:
+		break;
+	};
+	return _TRUE;
+}
+
+inline bool hidden_ssid_ap(WLAN_BSSID_EX *snetwork)
+{
+	return ((snetwork->Ssid.SsidLength == 0) ||  
+		is_all_null(snetwork->Ssid.Ssid, snetwork->Ssid.SsidLength) == _TRUE);
+}
+
+/*
+	Get SSID if this ilegal frame(probe resp) comes from a hidden SSID AP.
+	Update the SSID to the corresponding pnetwork in scan queue.
+*/
+void rtw_absorb_ssid_ifneed(_adapter *padapter, WLAN_BSSID_EX *bssid, u8 *pframe)
+{
+	struct wlan_network *scanned = NULL;
+	WLAN_BSSID_EX	*snetwork;
+	u8 ie_offset, *p=NULL, *next_ie=NULL, *mac = get_addr2_ptr(pframe);
+	sint len, ssid_len_ori;
+	u32 remain_len = 0;
+	u8 backupIE[MAX_IE_SZ];
+	u16 subtype = get_frame_sub_type(pframe);
+	_irqL irqL;
+
+	if ((!bssid) || (!pframe))
+		return;
+
+	if (subtype == WIFI_BEACON) {
+		bssid->Reserved[0] = BSS_TYPE_BCN;
+		ie_offset = _BEACON_IE_OFFSET_;
+	} else {
+		/* FIXME : more type */
+		if (subtype == WIFI_PROBERSP) {
+			ie_offset = _PROBERSP_IE_OFFSET_;
+			bssid->Reserved[0] = BSS_TYPE_PROB_RSP;
+		} else if (subtype == WIFI_PROBEREQ) {
+			ie_offset = _PROBEREQ_IE_OFFSET_;
+			bssid->Reserved[0] = BSS_TYPE_PROB_REQ;
+		} else {
+			bssid->Reserved[0] = BSS_TYPE_UNDEF;
+			ie_offset = _FIXED_IE_LENGTH_;
+		}
+	}
+	
+	_enter_critical_bh(&padapter->mlmepriv.scanned_queue.lock, &irqL);
+	scanned = _rtw_find_network(&padapter->mlmepriv.scanned_queue, mac);
+	if (!scanned) {
+		_exit_critical_bh(&padapter->mlmepriv.scanned_queue.lock, &irqL);
+		return;
+	}
+
+	snetwork = &(scanned->network);
+	/* scan queue records as Hidden SSID && Input frame is NOT Hidden SSID	*/
+	if (hidden_ssid_ap(snetwork) && !hidden_ssid_ap(bssid)) {
+		p = rtw_get_ie(snetwork->IEs+ie_offset, _SSID_IE_, &ssid_len_ori, snetwork->IELength-ie_offset);
+		if (!p) {
+			_exit_critical_bh(&padapter->mlmepriv.scanned_queue.lock, &irqL);
+			return;
+		}
+		next_ie = p + 2 + ssid_len_ori;
+		remain_len = snetwork->IELength - (next_ie - snetwork->IEs);
+		scanned->network.Ssid.SsidLength = bssid->Ssid.SsidLength;
+		_rtw_memcpy(scanned->network.Ssid.Ssid, bssid->Ssid.Ssid, bssid->Ssid.SsidLength);
+
+		//update pnetwork->ssid, pnetwork->ssidlen
+		_rtw_memcpy(backupIE, next_ie, remain_len);
+		*(p+1) = bssid->Ssid.SsidLength;
+		_rtw_memcpy(p+2, bssid->Ssid.Ssid, bssid->Ssid.SsidLength);
+		_rtw_memcpy(p+2+bssid->Ssid.SsidLength, backupIE, remain_len);
+		snetwork->IELength += bssid->Ssid.SsidLength;
+	}
+	_exit_critical_bh(&padapter->mlmepriv.scanned_queue.lock, &irqL);
+}
+
+#ifdef DBG_RX_BCN
+void rtw_debug_rx_bcn(_adapter *adapter, u8 *pframe, u32 packet_len)
+{
+	struct mlme_ext_priv *pmlmeext = &adapter->mlmeextpriv;
+	struct mlme_ext_info *mlmeinfo = &(pmlmeext->mlmext_info);
+	u16 sn = ((struct rtw_ieee80211_hdr_3addr *)pframe)->seq_ctl >> 4;
+	u64 tsf, tsf_offset;
+	u8 dtim_cnt, dtim_period, tim_bmap, tim_pvbit;
+
+	update_TSF(pmlmeext, pframe, packet_len);
+	tsf = pmlmeext->TSFValue;
+	tsf_offset = rtw_modular64(pmlmeext->TSFValue, (mlmeinfo->bcn_interval * 1024));
+
+	/*get TIM IE*/
+	/*DTIM Count*/
+	dtim_cnt = pmlmeext->tim[0];
+	/*DTIM Period*/
+	dtim_period = pmlmeext->tim[1];
+	/*Bitmap*/
+	tim_bmap = pmlmeext->tim[2];
+	/*Partial VBitmap AID 0 ~ 7*/
+	tim_pvbit = pmlmeext->tim[3];
+
+	RTW_INFO("[BCN] SN-%d, TSF-%lld(us), offset-%lld, bcn_interval-%d DTIM-%d[%d] bitmap-0x%02x-0x%02x\n",
+		sn, tsf, tsf_offset, mlmeinfo->bcn_interval, dtim_period, dtim_cnt, tim_bmap, tim_pvbit);
+}
+#endif
+
+/*
+ * rtw_get_bcn_keys: get beacon keys from recv frame
+ *
+ * TODO:
+ *	WLAN_EID_COUNTRY
+ *	WLAN_EID_ERP_INFO
+ *	WLAN_EID_CHANNEL_SWITCH
+ *	WLAN_EID_PWR_CONSTRAINT
+ */
+int rtw_get_bcn_keys(ADAPTER *Adapter, u8 *pframe, u32 packet_len,
+		     struct beacon_keys *recv_beacon)
+{
+	int left;
+	u16 capability;
+	unsigned char *pos;
+	struct rtw_ieee802_11_elems elems;
+	struct rtw_ieee80211_ht_cap *pht_cap = NULL;
+	struct HT_info_element *pht_info = NULL;
+
+	_rtw_memset(recv_beacon, 0, sizeof(*recv_beacon));
+
+	/* checking capabilities */
+	capability = le16_to_cpu(*(unsigned short *)(pframe + WLAN_HDR_A3_LEN + 10));
+
+	/* checking IEs */
+	left = packet_len - sizeof(struct rtw_ieee80211_hdr_3addr) - _BEACON_IE_OFFSET_;
+	pos = pframe + sizeof(struct rtw_ieee80211_hdr_3addr) + _BEACON_IE_OFFSET_;
+	if (rtw_ieee802_11_parse_elems(pos, left, &elems, 1) == ParseFailed)
+		return _FALSE;
+
+	/* check bw and channel offset */
+	if (elems.ht_capabilities) {
+		if (elems.ht_capabilities_len != sizeof(*pht_cap))
+			return _FALSE;
+
+		pht_cap = (struct rtw_ieee80211_ht_cap *) elems.ht_capabilities;
+		recv_beacon->ht_cap_info = pht_cap->cap_info;
+	}
+
+	if (elems.ht_operation) {
+		if (elems.ht_operation_len != sizeof(*pht_info))
+			return _FALSE;
+
+		pht_info = (struct HT_info_element *) elems.ht_operation;
+		recv_beacon->ht_info_infos_0_sco = pht_info->infos[0] & 0x03;
+	}
+
+	/* Checking for channel */
+	if (elems.ds_params && elems.ds_params_len == sizeof(recv_beacon->bcn_channel))
+		_rtw_memcpy(&recv_beacon->bcn_channel, elems.ds_params,
+			    sizeof(recv_beacon->bcn_channel));
+	else if (pht_info)
+		/* In 5G, some ap do not have DSSET IE checking HT info for channel */
+		recv_beacon->bcn_channel = pht_info->primary_channel;
+	else {
+		/* we don't find channel IE, so don't check it */
+		/* RTW_INFO("Oops: %s we don't find channel IE, so don't check it\n", __func__); */
+		recv_beacon->bcn_channel = Adapter->mlmeextpriv.cur_channel;
+	}
+
+	/* checking SSID */
+	if (elems.ssid) {
+		if (elems.ssid_len > sizeof(recv_beacon->ssid))
+			return _FALSE;
+
+		_rtw_memcpy(recv_beacon->ssid, elems.ssid, elems.ssid_len);
+		recv_beacon->ssid_len = elems.ssid_len;
+	} else
+		; /* means hidden ssid */
+
+	/* checking RSN first */
+	if (elems.rsn_ie && elems.rsn_ie_len) {
+		recv_beacon->encryp_protocol = ENCRYP_PROTOCOL_WPA2;
+		rtw_parse_wpa2_ie(elems.rsn_ie - 2, elems.rsn_ie_len + 2,
+			&recv_beacon->group_cipher, &recv_beacon->pairwise_cipher,
+				  &recv_beacon->is_8021x, NULL);
+	}
+	/* checking WPA secon */
+	else if (elems.wpa_ie && elems.wpa_ie_len) {
+		recv_beacon->encryp_protocol = ENCRYP_PROTOCOL_WPA;
+		rtw_parse_wpa_ie(elems.wpa_ie - 2, elems.wpa_ie_len + 2,
+			&recv_beacon->group_cipher, &recv_beacon->pairwise_cipher,
+				 &recv_beacon->is_8021x);
+	} else if (capability & BIT(4))
+		recv_beacon->encryp_protocol = ENCRYP_PROTOCOL_WEP;
+
+	if (elems.tim && elems.tim_len) {
+		struct mlme_ext_priv *pmlmeext = &Adapter->mlmeextpriv;
+
+		#ifdef DBG_RX_BCN
+		_rtw_memcpy(pmlmeext->tim, elems.tim, 4);
+		#endif
+		pmlmeext->dtim = elems.tim[1];
+	}
+
+	return _TRUE;
+}
+
+void rtw_dump_bcn_keys(struct beacon_keys *recv_beacon)
+{
+	u8 ssid[IW_ESSID_MAX_SIZE + 1];
+
+	_rtw_memcpy(ssid, recv_beacon->ssid, recv_beacon->ssid_len);
+	ssid[recv_beacon->ssid_len] = '\0';
+
+	RTW_INFO("%s: ssid = %s\n", __func__, ssid);
+	RTW_INFO("%s: channel = %d\n", __func__, recv_beacon->bcn_channel);
+	RTW_INFO("%s: ht_cap = 0x%04x\n", __func__,	recv_beacon->ht_cap_info);
+	RTW_INFO("%s: ht_info_infos_0_sco = 0x%02x\n", __func__, recv_beacon->ht_info_infos_0_sco);
+	RTW_INFO("%s: sec=%d, group = %x, pair = %x, 8021X = %x\n", __func__,
+		 recv_beacon->encryp_protocol, recv_beacon->group_cipher,
+		 recv_beacon->pairwise_cipher, recv_beacon->is_8021x);
+}
+#define DBG_BCN_CNT
+int rtw_check_bcn_info(ADAPTER *Adapter, u8 *pframe, u32 packet_len)
+{
+	unsigned int len;
+	u8 *pbssid = GetAddr3Ptr(pframe);
+	struct mlme_priv *pmlmepriv = &Adapter->mlmepriv;
+	struct wlan_network *cur_network = &(Adapter->mlmepriv.cur_network);
+	struct beacon_keys recv_beacon;
+
+	if (is_client_associated_to_ap(Adapter) == _FALSE)
+		return _TRUE;
+
+	len = packet_len - sizeof(struct rtw_ieee80211_hdr_3addr);
+
+	if (len > MAX_IE_SZ) {
+		RTW_WARN("%s IE too long for survey event\n", __func__);
+		return _FAIL;
+	}
+
+	if (_rtw_memcmp(cur_network->network.MacAddress, pbssid, 6) == _FALSE) {
+		RTW_WARN("Oops: rtw_check_network_encrypt linked but recv other bssid bcn\n" MAC_FMT MAC_FMT,
+			MAC_ARG(pbssid), MAC_ARG(cur_network->network.MacAddress));
+		return _TRUE;
+	}
+
+	if (rtw_get_bcn_keys(Adapter, pframe, packet_len, &recv_beacon) == _FALSE)
+		return _TRUE; /* parsing failed => broken IE */
+
+#ifdef DBG_RX_BCN
+	rtw_debug_bcn(Adapter, pframe, packet_len);
+#endif
+
+	/* don't care hidden ssid, use current beacon ssid directly */
+	if (recv_beacon.ssid_len == 0) {
+		_rtw_memcpy(recv_beacon.ssid, pmlmepriv->cur_beacon_keys.ssid,
+			    pmlmepriv->cur_beacon_keys.ssid_len);
+		recv_beacon.ssid_len = pmlmepriv->cur_beacon_keys.ssid_len;
+	}
+#ifdef CONFIG_BCN_CNT_CONFIRM_HDL
+	if (_rtw_memcmp(&recv_beacon, &pmlmepriv->cur_beacon_keys, sizeof(recv_beacon)) == _TRUE)
+		pmlmepriv->new_beacon_cnts = 0;
+	else if ((pmlmepriv->new_beacon_cnts == 0) ||
+		_rtw_memcmp(&recv_beacon, &pmlmepriv->new_beacon_keys, sizeof(recv_beacon)) == _FALSE) {
+		RTW_DBG("%s: start new beacon (seq=%d)\n", __func__, GetSequence(pframe));
+
+		if (pmlmepriv->new_beacon_cnts == 0) {
+			RTW_ERR("%s: cur beacon key\n", __func__);
+			RTW_DBG_EXPR(rtw_dump_bcn_keys(&pmlmepriv->cur_beacon_keys));
+		}
+
+		RTW_DBG("%s: new beacon key\n", __func__);
+		RTW_DBG_EXPR(rtw_dump_bcn_keys(&recv_beacon));
+
+		_rtw_memcpy(&pmlmepriv->new_beacon_keys, &recv_beacon, sizeof(recv_beacon));
+		pmlmepriv->new_beacon_cnts = 1;
+	} else {
+		RTW_DBG("%s: new beacon again (seq=%d)\n", __func__, GetSequence(pframe));
+		pmlmepriv->new_beacon_cnts++;
+	}
+
+	/* if counter >= max, it means beacon is changed really */
+	if (pmlmepriv->new_beacon_cnts >= new_bcn_max)
+#else
+	if (_rtw_memcmp(&recv_beacon, &pmlmepriv->cur_beacon_keys, sizeof(recv_beacon)) == _FALSE)
+#endif
+	{
+		/* check bw mode change only? */
+		pmlmepriv->cur_beacon_keys.ht_cap_info = recv_beacon.ht_cap_info;
+		pmlmepriv->cur_beacon_keys.ht_info_infos_0_sco = recv_beacon.ht_info_infos_0_sco;
+		if (_rtw_memcmp(&recv_beacon, &pmlmepriv->cur_beacon_keys,
+				sizeof(recv_beacon)) == _FALSE) {
+			/* beacon is changed, have to do disconnect/connect */
+			RTW_WARN("%s: new beacon occur!!\n", __func__);
+			#ifdef DBG_BCN_CNT
+			rtw_dump_bcn_keys(&recv_beacon);
+			#endif
+			return _FAIL;
+		}
+		#ifdef DBG_BCN_CNT
+		RTW_INFO("%s bw mode change\n", __func__);
+		RTW_INFO("%s bcn now: ht_cap_info:%x ht_info_infos_0:%x\n", __func__,
+			 cur_network->BcnInfo.ht_cap_info,
+			 cur_network->BcnInfo.ht_info_infos_0);
+		#endif
+
+		cur_network->BcnInfo.ht_cap_info = recv_beacon.ht_cap_info;
+		cur_network->BcnInfo.ht_info_infos_0 =
+			(cur_network->BcnInfo.ht_info_infos_0 & (~0x03)) |
+			recv_beacon.ht_info_infos_0_sco;
+
+		#ifdef DBG_BCN_CNT
+		RTW_INFO("%s bcn link: ht_cap_info:%x ht_info_infos_0:%x\n", __func__,
+			 cur_network->BcnInfo.ht_cap_info,
+			 cur_network->BcnInfo.ht_info_infos_0);
+		#endif
+		_rtw_memcpy(&pmlmepriv->cur_beacon_keys, &recv_beacon, sizeof(recv_beacon));
+		#ifdef CONFIG_BCN_CNT_CONFIRM_HDL
+		pmlmepriv->new_beacon_cnts = 0;
+		#endif
+	}
+
+	return _SUCCESS;
+}
+
+void update_beacon_info(_adapter *padapter, u8 *pframe, uint pkt_len, struct sta_info *psta)
+{
+	unsigned int i;
+	unsigned int len;
+	PNDIS_802_11_VARIABLE_IEs	pIE;
+
+#ifdef CONFIG_TDLS
+	struct tdls_info *ptdlsinfo = &padapter->tdlsinfo;
+	u8 tdls_prohibited[] = { 0x00, 0x00, 0x00, 0x00, 0x10 }; /* bit(38): TDLS_prohibited */
+#endif /* CONFIG_TDLS */
+
+	len = pkt_len - (_BEACON_IE_OFFSET_ + WLAN_HDR_A3_LEN);
+
+	for (i = 0; i < len;) {
+		pIE = (PNDIS_802_11_VARIABLE_IEs)(pframe + (_BEACON_IE_OFFSET_ + WLAN_HDR_A3_LEN) + i);
+
+		switch (pIE->ElementID) {
+		case _VENDOR_SPECIFIC_IE_:
+			/* to update WMM paramter set while receiving beacon */
+			if (_rtw_memcmp(pIE->data, WMM_PARA_OUI, 6) && pIE->Length == WLAN_WMM_LEN)	/* WMM */
+				(WMM_param_handler(padapter, pIE)) ? report_wmm_edca_update(padapter) : 0;
+
+			break;
+
+		case _HT_EXTRA_INFO_IE_:	/* HT info */
+			/* HT_info_handler(padapter, pIE); */
+			bwmode_update_check(padapter, pIE);
+			break;
+#ifdef CONFIG_80211AC_VHT
+		case EID_OpModeNotification:
+			rtw_process_vht_op_mode_notify(padapter, pIE->data, psta);
+			break;
+#endif /* CONFIG_80211AC_VHT */
+		case _ERPINFO_IE_:
+			ERP_IE_handler(padapter, pIE);
+			VCS_update(padapter, psta);
+			break;
+
+#ifdef CONFIG_TDLS
+		case _EXT_CAP_IE_:
+			if (check_ap_tdls_prohibited(pIE->data, pIE->Length) == _TRUE)
+				ptdlsinfo->ap_prohibited = _TRUE;
+			if (check_ap_tdls_ch_switching_prohibited(pIE->data, pIE->Length) == _TRUE)
+				ptdlsinfo->ch_switch_prohibited = _TRUE;
+			break;
+#endif /* CONFIG_TDLS */
+		default:
+			break;
+		}
+
+		i += (pIE->Length + 2);
+	}
+}
+
+#ifdef CONFIG_DFS
+void process_csa_ie(_adapter *padapter, u8 *ies, uint ies_len)
+{
+	struct rf_ctl_t *rfctl = adapter_to_rfctl(padapter);
+	unsigned int i;
+	PNDIS_802_11_VARIABLE_IEs	pIE;
+	u8 ch = 0;
+
+	/* TODO: compare with scheduling CSA */
+	if (rfctl->csa_ch)
+		return;
+
+	for (i = 0; i + 1 < ies_len;) {
+		pIE = (PNDIS_802_11_VARIABLE_IEs)(ies + i);
+
+		switch (pIE->ElementID) {
+		case _CH_SWTICH_ANNOUNCE_:
+			ch = *(pIE->data + 1);
+			break;
+		default:
+			break;
+		}
+
+		i += (pIE->Length + 2);
+	}
+
+	if (ch != 0) {
+		rfctl->csa_ch = ch;
+		if (rtw_set_csa_cmd(padapter) != _SUCCESS)
+			rfctl->csa_ch = 0;
+	}
+}
+#endif /* CONFIG_DFS */
+
+void parsing_eapol_packet(_adapter *padapter, u8 *key_payload, struct sta_info *psta, u8 trx_type)
+{
+	struct security_priv *psecuritypriv = &(padapter->securitypriv);
+	struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
+	struct sta_priv *pstapriv = &(padapter->stapriv);
+	struct ieee802_1x_hdr *hdr;
+	struct wpa_eapol_key *key;
+	u16 key_info, key_data_length;
+	char *trx_msg = trx_type ? "send" : "recv";
+
+	hdr = (struct ieee802_1x_hdr *) key_payload;
+
+	 /* WPS - eapol start packet */
+	if (hdr->type == 1 && hdr->length == 0) {
+		RTW_INFO("%s eapol start packet\n", trx_msg);
+		return;
+	}
+
+	if (hdr->type == 0) { /* WPS - eapol packet */
+		RTW_INFO("%s eapol packet\n", trx_msg);
+		return;
+	}
+
+	key = (struct wpa_eapol_key *) (hdr + 1);
+	key_info = be16_to_cpu(*((u16 *)(key->key_info)));
+	key_data_length = be16_to_cpu(*((u16 *)(key->key_data_length)));
+
+	if (!(key_info & WPA_KEY_INFO_KEY_TYPE)) { /* WPA group key handshake */
+		if (key_info & WPA_KEY_INFO_ACK) {
+			RTW_PRINT("%s eapol packet - WPA Group Key 1/2\n", trx_msg);
+		} else {
+			RTW_PRINT("%s eapol packet - WPA Group Key 2/2\n", trx_msg);
+
+			/* WPA key-handshake has completed */
+			if (psecuritypriv->ndisauthtype == Ndis802_11AuthModeWPAPSK)
+				psta->state &= (~WIFI_UNDER_KEY_HANDSHAKE);
+		}
+	} else if (key_info & WPA_KEY_INFO_MIC) {
+		if (key_data_length == 0)
+			RTW_PRINT("%s eapol packet 4/4\n", trx_msg);
+		else if (key_info & WPA_KEY_INFO_ACK)
+			RTW_PRINT("%s eapol packet 3/4\n", trx_msg);
+		else
+			RTW_PRINT("%s eapol packet 2/4\n", trx_msg);
+	} else {
+		RTW_PRINT("%s eapol packet 1/4\n", trx_msg);
+	}
+
+}
+
+unsigned int is_ap_in_tkip(_adapter *padapter)
+{
+	u32 i;
+	PNDIS_802_11_VARIABLE_IEs	pIE;
+	struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
+	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
+	WLAN_BSSID_EX		*cur_network = &(pmlmeinfo->network);
+
+	if (rtw_get_capability((WLAN_BSSID_EX *)cur_network) & WLAN_CAPABILITY_PRIVACY) {
+		for (i = sizeof(NDIS_802_11_FIXED_IEs); i < pmlmeinfo->network.IELength;) {
+			pIE = (PNDIS_802_11_VARIABLE_IEs)(pmlmeinfo->network.IEs + i);
+
+			switch (pIE->ElementID) {
+			case _VENDOR_SPECIFIC_IE_:
+				if ((_rtw_memcmp(pIE->data, RTW_WPA_OUI, 4)) && (_rtw_memcmp((pIE->data + 12), WPA_TKIP_CIPHER, 4)))
+					return _TRUE;
+				break;
+
+			case _RSN_IE_2_:
+				if (_rtw_memcmp((pIE->data + 8), RSN_TKIP_CIPHER, 4))
+					return _TRUE;
+
+			default:
+				break;
+			}
+
+			i += (pIE->Length + 2);
+		}
+
+		return _FALSE;
+	} else
+		return _FALSE;
+
+}
+
+unsigned int should_forbid_n_rate(_adapter *padapter)
+{
+	u32 i;
+	PNDIS_802_11_VARIABLE_IEs	pIE;
+	struct mlme_priv	*pmlmepriv = &padapter->mlmepriv;
+	WLAN_BSSID_EX  *cur_network = &pmlmepriv->cur_network.network;
+
+	if (rtw_get_capability((WLAN_BSSID_EX *)cur_network) & WLAN_CAPABILITY_PRIVACY) {
+		for (i = sizeof(NDIS_802_11_FIXED_IEs); i < cur_network->IELength;) {
+			pIE = (PNDIS_802_11_VARIABLE_IEs)(cur_network->IEs + i);
+
+			switch (pIE->ElementID) {
+			case _VENDOR_SPECIFIC_IE_:
+				if (_rtw_memcmp(pIE->data, RTW_WPA_OUI, 4) &&
+				    ((_rtw_memcmp((pIE->data + 12), WPA_CIPHER_SUITE_CCMP, 4)) ||
+				     (_rtw_memcmp((pIE->data + 16), WPA_CIPHER_SUITE_CCMP, 4))))
+					return _FALSE;
+				break;
+
+			case _RSN_IE_2_:
+				if ((_rtw_memcmp((pIE->data + 8), RSN_CIPHER_SUITE_CCMP, 4))  ||
+				    (_rtw_memcmp((pIE->data + 12), RSN_CIPHER_SUITE_CCMP, 4)))
+					return _FALSE;
+
+			default:
+				break;
+			}
+
+			i += (pIE->Length + 2);
+		}
+
+		return _TRUE;
+	} else
+		return _FALSE;
+
+}
+
+
+unsigned int is_ap_in_wep(_adapter *padapter)
+{
+	u32 i;
+	PNDIS_802_11_VARIABLE_IEs	pIE;
+	struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
+	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
+	WLAN_BSSID_EX		*cur_network = &(pmlmeinfo->network);
+
+	if (rtw_get_capability((WLAN_BSSID_EX *)cur_network) & WLAN_CAPABILITY_PRIVACY) {
+		for (i = sizeof(NDIS_802_11_FIXED_IEs); i < pmlmeinfo->network.IELength;) {
+			pIE = (PNDIS_802_11_VARIABLE_IEs)(pmlmeinfo->network.IEs + i);
+
+			switch (pIE->ElementID) {
+			case _VENDOR_SPECIFIC_IE_:
+				if (_rtw_memcmp(pIE->data, RTW_WPA_OUI, 4))
+					return _FALSE;
+				break;
+
+			case _RSN_IE_2_:
+				return _FALSE;
+
+			default:
+				break;
+			}
+
+			i += (pIE->Length + 2);
+		}
+
+		return _TRUE;
+	} else
+		return _FALSE;
+
+}
+
+int wifirate2_ratetbl_inx(unsigned char rate);
+int wifirate2_ratetbl_inx(unsigned char rate)
+{
+	int	inx = 0;
+	rate = rate & 0x7f;
+
+	switch (rate) {
+	case 54*2:
+		inx = 11;
+		break;
+
+	case 48*2:
+		inx = 10;
+		break;
+
+	case 36*2:
+		inx = 9;
+		break;
+
+	case 24*2:
+		inx = 8;
+		break;
+
+	case 18*2:
+		inx = 7;
+		break;
+
+	case 12*2:
+		inx = 6;
+		break;
+
+	case 9*2:
+		inx = 5;
+		break;
+
+	case 6*2:
+		inx = 4;
+		break;
+
+	case 11*2:
+		inx = 3;
+		break;
+	case 11:
+		inx = 2;
+		break;
+
+	case 2*2:
+		inx = 1;
+		break;
+
+	case 1*2:
+		inx = 0;
+		break;
+
+	}
+	return inx;
+}
+
+unsigned int update_basic_rate(unsigned char *ptn, unsigned int ptn_sz)
+{
+	unsigned int i, num_of_rate;
+	unsigned int mask = 0;
+
+	num_of_rate = (ptn_sz > NumRates) ? NumRates : ptn_sz;
+
+	for (i = 0; i < num_of_rate; i++) {
+		if ((*(ptn + i)) & 0x80)
+			mask |= 0x1 << wifirate2_ratetbl_inx(*(ptn + i));
+	}
+	return mask;
+}
+
+unsigned int update_supported_rate(unsigned char *ptn, unsigned int ptn_sz)
+{
+	unsigned int i, num_of_rate;
+	unsigned int mask = 0;
+
+	num_of_rate = (ptn_sz > NumRates) ? NumRates : ptn_sz;
+
+	for (i = 0; i < num_of_rate; i++)
+		mask |= 0x1 << wifirate2_ratetbl_inx(*(ptn + i));
+
+	return mask;
+}
+
+int support_short_GI(_adapter *padapter, struct HT_caps_element *pHT_caps, u8 bwmode)
+{
+	unsigned char					bit_offset;
+	struct mlme_ext_priv	*pmlmeext = &padapter->mlmeextpriv;
+	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
+
+	if (!(pmlmeinfo->HT_enable))
+		return _FAIL;
+
+	bit_offset = (bwmode & CHANNEL_WIDTH_40) ? 6 : 5;
+
+	if (pHT_caps->u.HT_cap_element.HT_caps_info & (0x1 << bit_offset))
+		return _SUCCESS;
+	else
+		return _FAIL;
+}
+
+unsigned char get_highest_rate_idx(u64 mask)
+{
+	int i;
+	unsigned char rate_idx = 0;
+
+	for (i = 63; i >= 0; i--) {
+		if ((mask >> i) & 0x01) {
+			rate_idx = i;
+			break;
+		}
+	}
+
+	return rate_idx;
+}
+unsigned char get_lowest_rate_idx_ex(u64 mask, int start_bit)
+{
+	int i;
+	unsigned char rate_idx = 0;
+
+	for (i = start_bit; i < 64; i++) {
+		if ((mask >> i) & 0x01) {
+			rate_idx = i;
+			break;
+		}
+	}
+
+	return rate_idx;
+}
+
+void Update_RA_Entry(_adapter *padapter, struct sta_info *psta)
+{
+	rtw_hal_update_ra_mask(psta);
+}
+
+void set_sta_rate(_adapter *padapter, struct sta_info *psta)
+{
+	/* rate adaptive	 */
+	rtw_hal_update_ra_mask(psta);
+}
+
+/* Update RRSR and Rate for USERATE */
+void update_tx_basic_rate(_adapter *padapter, u8 wirelessmode)
+{
+	NDIS_802_11_RATES_EX	supported_rates;
+	struct mlme_ext_priv	*pmlmeext = &padapter->mlmeextpriv;
+#ifdef CONFIG_P2P
+	struct wifidirect_info	*pwdinfo = &padapter->wdinfo;
+
+	/*	Added by Albert 2011/03/22 */
+	/*	In the P2P mode, the driver should not support the b mode. */
+	/*	So, the Tx packet shouldn't use the CCK rate */
+	if (!rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE))
+		return;
+#endif /* CONFIG_P2P */
+#ifdef CONFIG_INTEL_WIDI
+	if (padapter->mlmepriv.widi_state != INTEL_WIDI_STATE_NONE)
+		return;
+#endif /* CONFIG_INTEL_WIDI */
+
+	_rtw_memset(supported_rates, 0, NDIS_802_11_LENGTH_RATES_EX);
+
+	/* clear B mod if current channel is in 5G band, avoid tx cck rate in 5G band. */
+	if (pmlmeext->cur_channel > 14)
+		wirelessmode &= ~(WIRELESS_11B);
+
+	if ((wirelessmode & WIRELESS_11B) && (wirelessmode == WIRELESS_11B))
+		_rtw_memcpy(supported_rates, rtw_basic_rate_cck, 4);
+	else if (wirelessmode & WIRELESS_11B)
+		_rtw_memcpy(supported_rates, rtw_basic_rate_mix, 7);
+	else
+		_rtw_memcpy(supported_rates, rtw_basic_rate_ofdm, 3);
+
+	if (wirelessmode & WIRELESS_11B)
+		update_mgnt_tx_rate(padapter, IEEE80211_CCK_RATE_1MB);
+	else
+		update_mgnt_tx_rate(padapter, IEEE80211_OFDM_RATE_6MB);
+
+	rtw_hal_set_hwreg(padapter, HW_VAR_BASIC_RATE, supported_rates);
+}
+
+unsigned char check_assoc_AP(u8 *pframe, uint len)
+{
+	unsigned int	i;
+	PNDIS_802_11_VARIABLE_IEs	pIE;
+
+	for (i = sizeof(NDIS_802_11_FIXED_IEs); i < len;) {
+		pIE = (PNDIS_802_11_VARIABLE_IEs)(pframe + i);
+
+		switch (pIE->ElementID) {
+		case _VENDOR_SPECIFIC_IE_:
+			if ((_rtw_memcmp(pIE->data, ARTHEROS_OUI1, 3)) || (_rtw_memcmp(pIE->data, ARTHEROS_OUI2, 3))) {
+				RTW_INFO("link to Artheros AP\n");
+				return HT_IOT_PEER_ATHEROS;
+			} else if ((_rtw_memcmp(pIE->data, BROADCOM_OUI1, 3))
+				   || (_rtw_memcmp(pIE->data, BROADCOM_OUI2, 3))
+				|| (_rtw_memcmp(pIE->data, BROADCOM_OUI3, 3))) {
+				RTW_INFO("link to Broadcom AP\n");
+				return HT_IOT_PEER_BROADCOM;
+			} else if (_rtw_memcmp(pIE->data, MARVELL_OUI, 3)) {
+				RTW_INFO("link to Marvell AP\n");
+				return HT_IOT_PEER_MARVELL;
+			} else if (_rtw_memcmp(pIE->data, RALINK_OUI, 3)) {
+				RTW_INFO("link to Ralink AP\n");
+				return HT_IOT_PEER_RALINK;
+			} else if (_rtw_memcmp(pIE->data, CISCO_OUI, 3)) {
+				RTW_INFO("link to Cisco AP\n");
+				return HT_IOT_PEER_CISCO;
+			} else if (_rtw_memcmp(pIE->data, REALTEK_OUI, 3)) {
+				u32	Vender = HT_IOT_PEER_REALTEK;
+
+				if (pIE->Length >= 5) {
+					if (pIE->data[4] == 1) {
+						/* if(pIE->data[5] & RT_HT_CAP_USE_LONG_PREAMBLE) */
+						/*	bssDesc->BssHT.RT2RT_HT_Mode |= RT_HT_CAP_USE_LONG_PREAMBLE; */
+
+						if (pIE->data[5] & RT_HT_CAP_USE_92SE) {
+							/* bssDesc->BssHT.RT2RT_HT_Mode |= RT_HT_CAP_USE_92SE; */
+							Vender = HT_IOT_PEER_REALTEK_92SE;
+						}
+					}
+
+					if (pIE->data[5] & RT_HT_CAP_USE_SOFTAP)
+						Vender = HT_IOT_PEER_REALTEK_SOFTAP;
+
+					if (pIE->data[4] == 2) {
+						if (pIE->data[6] & RT_HT_CAP_USE_JAGUAR_BCUT) {
+							Vender = HT_IOT_PEER_REALTEK_JAGUAR_BCUTAP;
+							RTW_INFO("link to Realtek JAGUAR_BCUTAP\n");
+						}
+						if (pIE->data[6] & RT_HT_CAP_USE_JAGUAR_CCUT) {
+							Vender = HT_IOT_PEER_REALTEK_JAGUAR_CCUTAP;
+							RTW_INFO("link to Realtek JAGUAR_CCUTAP\n");
+						}
+					}
+				}
+
+				RTW_INFO("link to Realtek AP\n");
+				return Vender;
+			} else if (_rtw_memcmp(pIE->data, AIRGOCAP_OUI, 3)) {
+				RTW_INFO("link to Airgo Cap\n");
+				return HT_IOT_PEER_AIRGO;
+			} else
+				break;
+
+		default:
+			break;
+		}
+
+		i += (pIE->Length + 2);
+	}
+
+	RTW_INFO("link to new AP\n");
+	return HT_IOT_PEER_UNKNOWN;
+}
+
+void get_assoc_AP_Vendor(char *vendor, u8 assoc_AP_vendor)
+{
+	switch (assoc_AP_vendor) {
+	
+	case HT_IOT_PEER_UNKNOWN:
+	sprintf(vendor, "%s", "unknown");
+	break;
+
+	case HT_IOT_PEER_REALTEK:
+	case HT_IOT_PEER_REALTEK_92SE:
+	case HT_IOT_PEER_REALTEK_SOFTAP:
+	case HT_IOT_PEER_REALTEK_JAGUAR_BCUTAP:
+	case HT_IOT_PEER_REALTEK_JAGUAR_CCUTAP:
+
+	sprintf(vendor, "%s", "Realtek");
+	break;
+
+	case HT_IOT_PEER_BROADCOM:
+	sprintf(vendor, "%s", "Broadcom");
+	break;
+
+	case HT_IOT_PEER_MARVELL:
+	sprintf(vendor, "%s", "Marvell");
+	break;
+
+	case HT_IOT_PEER_RALINK:
+	sprintf(vendor, "%s", "Ralink");
+	break;
+
+	case HT_IOT_PEER_CISCO:
+	sprintf(vendor, "%s", "Cisco");
+	break;
+
+	case HT_IOT_PEER_AIRGO:
+	sprintf(vendor, "%s", "Airgo");
+	break;
+
+	case HT_IOT_PEER_ATHEROS:
+	sprintf(vendor, "%s", "Atheros");
+	break;
+
+	default:
+	sprintf(vendor, "%s", "unkown");
+	break;
+	}
+
+}
+
+#ifdef CONFIG_80211AC_VHT
+unsigned char get_vht_mu_bfer_cap(u8 *pframe, uint len)
+{
+	unsigned int i;
+	unsigned int mu_bfer=0;
+	PNDIS_802_11_VARIABLE_IEs pIE;
+
+	for (i = sizeof(NDIS_802_11_FIXED_IEs); i < len;) {
+		pIE = (PNDIS_802_11_VARIABLE_IEs)(pframe + i);
+
+		switch (pIE->ElementID) {
+
+		case EID_VHTCapability:
+			mu_bfer = GET_VHT_CAPABILITY_ELE_MU_BFER(pIE->data);
+			break;
+		default:
+			break;
+		}
+		i += (pIE->Length + 2);
+	}
+	return mu_bfer;
+}
+#endif
+
+void update_capinfo(PADAPTER Adapter, u16 updateCap)
+{
+	struct mlme_ext_priv	*pmlmeext = &Adapter->mlmeextpriv;
+	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
+	BOOLEAN		ShortPreamble;
+
+	/* Check preamble mode, 2005.01.06, by rcnjko. */
+	/* Mark to update preamble value forever, 2008.03.18 by lanhsin */
+	/* if( pMgntInfo->RegPreambleMode == PREAMBLE_AUTO ) */
+	{
+
+		if (updateCap & cShortPreamble) {
+			/* Short Preamble */
+			if (pmlmeinfo->preamble_mode != PREAMBLE_SHORT) { /* PREAMBLE_LONG or PREAMBLE_AUTO */
+				ShortPreamble = _TRUE;
+				pmlmeinfo->preamble_mode = PREAMBLE_SHORT;
+				rtw_hal_set_hwreg(Adapter, HW_VAR_ACK_PREAMBLE, (u8 *)&ShortPreamble);
+			}
+		} else {
+			/* Long Preamble */
+			if (pmlmeinfo->preamble_mode != PREAMBLE_LONG) { /* PREAMBLE_SHORT or PREAMBLE_AUTO */
+				ShortPreamble = _FALSE;
+				pmlmeinfo->preamble_mode = PREAMBLE_LONG;
+				rtw_hal_set_hwreg(Adapter, HW_VAR_ACK_PREAMBLE, (u8 *)&ShortPreamble);
+			}
+		}
+	}
+
+	if (updateCap & cIBSS) {
+		/* Filen: See 802.11-2007 p.91 */
+		pmlmeinfo->slotTime = NON_SHORT_SLOT_TIME;
+	} else {
+		/* Filen: See 802.11-2007 p.90 */
+		if (pmlmeext->cur_wireless_mode & (WIRELESS_11_24N | WIRELESS_11A | WIRELESS_11_5N | WIRELESS_11AC))
+			pmlmeinfo->slotTime = SHORT_SLOT_TIME;
+		else if (pmlmeext->cur_wireless_mode & (WIRELESS_11G)) {
+			if ((updateCap & cShortSlotTime) /* && (!(pMgntInfo->pHTInfo->RT2RT_HT_Mode & RT_HT_CAP_USE_LONG_PREAMBLE)) */) {
+				/* Short Slot Time */
+				pmlmeinfo->slotTime = SHORT_SLOT_TIME;
+			} else {
+				/* Long Slot Time */
+				pmlmeinfo->slotTime = NON_SHORT_SLOT_TIME;
+			}
+		} else {
+			/* B Mode */
+			pmlmeinfo->slotTime = NON_SHORT_SLOT_TIME;
+		}
+	}
+
+	rtw_hal_set_hwreg(Adapter, HW_VAR_SLOT_TIME, &pmlmeinfo->slotTime);
+
+}
+
+/*
+* set adapter.mlmeextpriv.mlmext_info.HT_enable
+* set adapter.mlmeextpriv.cur_wireless_mode
+* set SIFS register
+* set mgmt tx rate
+*/
+void update_wireless_mode(_adapter *padapter)
+{
+	int ratelen, network_type = 0;
+	u32 SIFS_Timer;
+	struct mlme_ext_priv	*pmlmeext = &padapter->mlmeextpriv;
+	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
+	WLAN_BSSID_EX		*cur_network = &(pmlmeinfo->network);
+	unsigned char			*rate = cur_network->SupportedRates;
+#ifdef CONFIG_P2P
+	struct wifidirect_info	*pwdinfo = &(padapter->wdinfo);
+#endif /* CONFIG_P2P */
+
+	ratelen = rtw_get_rateset_len(cur_network->SupportedRates);
+
+	if ((pmlmeinfo->HT_info_enable) && (pmlmeinfo->HT_caps_enable))
+		pmlmeinfo->HT_enable = 1;
+
+	if (pmlmeext->cur_channel > 14) {
+		if (pmlmeinfo->VHT_enable)
+			network_type = WIRELESS_11AC;
+		else if (pmlmeinfo->HT_enable)
+			network_type = WIRELESS_11_5N;
+
+		network_type |= WIRELESS_11A;
+	} else {
+		if (pmlmeinfo->VHT_enable)
+			network_type = WIRELESS_11AC;
+		else if (pmlmeinfo->HT_enable)
+			network_type = WIRELESS_11_24N;
+
+		if ((cckratesonly_included(rate, ratelen)) == _TRUE)
+			network_type |= WIRELESS_11B;
+		else if ((cckrates_included(rate, ratelen)) == _TRUE)
+			network_type |= WIRELESS_11BG;
+		else
+			network_type |= WIRELESS_11G;
+	}
+
+	pmlmeext->cur_wireless_mode = network_type & padapter->registrypriv.wireless_mode;
+	/* RTW_INFO("network_type=%02x, padapter->registrypriv.wireless_mode=%02x\n", network_type, padapter->registrypriv.wireless_mode); */
+#if 0
+	if ((pmlmeext->cur_wireless_mode == WIRELESS_11G) ||
+	    (pmlmeext->cur_wireless_mode == WIRELESS_11BG)) /* WIRELESS_MODE_G) */
+		SIFS_Timer = 0x0a0a;/* CCK */
+	else
+		SIFS_Timer = 0x0e0e;/* pHalData->SifsTime; //OFDM */
+#endif
+
+	SIFS_Timer = 0x0a0a0808; /* 0x0808->for CCK, 0x0a0a->for OFDM
+                              * change this value if having IOT issues. */
+
+	rtw_hal_set_hwreg(padapter, HW_VAR_RESP_SIFS, (u8 *)&SIFS_Timer);
+
+	rtw_hal_set_hwreg(padapter, HW_VAR_WIRELESS_MODE, (u8 *)&(pmlmeext->cur_wireless_mode));
+
+	if ((pmlmeext->cur_wireless_mode & WIRELESS_11B)
+		#ifdef CONFIG_P2P
+		&& (rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE)
+			#ifdef CONFIG_IOCTL_CFG80211
+			|| !rtw_cfg80211_iface_has_p2p_group_cap(padapter)
+			#endif
+			)
+		#endif
+	)
+		update_mgnt_tx_rate(padapter, IEEE80211_CCK_RATE_1MB);
+	else
+		update_mgnt_tx_rate(padapter, IEEE80211_OFDM_RATE_6MB);
+}
+
+void fire_write_MAC_cmd(_adapter *padapter, unsigned int addr, unsigned int value);
+void fire_write_MAC_cmd(_adapter *padapter, unsigned int addr, unsigned int value)
+{
+#if 0
+	struct cmd_obj					*ph2c;
+	struct reg_rw_parm			*pwriteMacPara;
+	struct cmd_priv					*pcmdpriv = &(padapter->cmdpriv);
+
+	ph2c = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj));
+	if (ph2c == NULL)
+		return;
+
+	pwriteMacPara = (struct reg_rw_parm *)rtw_malloc(sizeof(struct reg_rw_parm));
+	if (pwriteMacPara == NULL) {
+		rtw_mfree((unsigned char *)ph2c, sizeof(struct cmd_obj));
+		return;
+	}
+
+	pwriteMacPara->rw = 1;
+	pwriteMacPara->addr = addr;
+	pwriteMacPara->value = value;
+
+	init_h2fwcmd_w_parm_no_rsp(ph2c, pwriteMacPara, GEN_CMD_CODE(_Write_MACREG));
+	rtw_enqueue_cmd(pcmdpriv, ph2c);
+#endif
+}
+
+void update_sta_basic_rate(struct sta_info *psta, u8 wireless_mode)
+{
+	if (IsSupportedTxCCK(wireless_mode)) {
+		/* Only B, B/G, and B/G/N AP could use CCK rate */
+		_rtw_memcpy(psta->bssrateset, rtw_basic_rate_cck, 4);
+		psta->bssratelen = 4;
+	} else {
+		_rtw_memcpy(psta->bssrateset, rtw_basic_rate_ofdm, 3);
+		psta->bssratelen = 3;
+	}
+}
+
+int rtw_ies_get_supported_rate(u8 *ies, uint ies_len, u8 *rate_set, u8 *rate_num)
+{
+	u8 *ie, *p;
+	unsigned int ie_len;
+	int i, j;
+
+	struct support_rate_handler support_rate_tbl[] = {
+		{IEEE80211_CCK_RATE_1MB, 		_FALSE,		_FALSE},
+		{IEEE80211_CCK_RATE_2MB, 		_FALSE,		_FALSE},
+		{IEEE80211_CCK_RATE_5MB, 		_FALSE,		_FALSE},
+		{IEEE80211_CCK_RATE_11MB,		_FALSE,		_FALSE},
+		{IEEE80211_OFDM_RATE_6MB,		_FALSE,		_FALSE},
+		{IEEE80211_OFDM_RATE_9MB,		_FALSE,		_FALSE},
+		{IEEE80211_OFDM_RATE_12MB,		_FALSE,		_FALSE},
+		{IEEE80211_OFDM_RATE_18MB,		_FALSE,		_FALSE},
+		{IEEE80211_OFDM_RATE_24MB,		_FALSE,		_FALSE},
+		{IEEE80211_OFDM_RATE_36MB,		_FALSE,		_FALSE},
+		{IEEE80211_OFDM_RATE_48MB,		_FALSE,		_FALSE},
+		{IEEE80211_OFDM_RATE_54MB,		_FALSE,		_FALSE},
+	};
+
+	if (!rate_set || !rate_num)
+		return _FALSE;
+
+	*rate_num = 0;
+
+	ie = rtw_get_ie(ies, _SUPPORTEDRATES_IE_, &ie_len, ies_len);
+	if (ie == NULL)
+		goto ext_rate;
+
+	/* get valid supported rates */
+	for (i = 0; i < 12; i++) {
+		p = ie + 2;
+		for (j = 0; j < ie_len; j++) {
+			if ((*p & ~BIT(7)) == support_rate_tbl[i].rate){
+				support_rate_tbl[i].existence = _TRUE;
+				if ((*p) & BIT(7))
+					support_rate_tbl[i].basic = _TRUE;
+			}
+			p++;
+		}
+	}
+
+ext_rate:
+	ie = rtw_get_ie(ies, _EXT_SUPPORTEDRATES_IE_, &ie_len, ies_len);
+	if (ie) {
+		/* get valid extended supported rates */
+		for (i = 0; i < 12; i++) {
+			p = ie + 2;
+			for (j = 0; j < ie_len; j++) {
+				if ((*p & ~BIT(7)) == support_rate_tbl[i].rate){
+					support_rate_tbl[i].existence = _TRUE;
+					if ((*p) & BIT(7))
+						support_rate_tbl[i].basic = _TRUE;
+				}
+				p++;
+			}
+		}
+	}
+
+	for (i = 0; i < 12; i++){
+		if (support_rate_tbl[i].existence){
+			if (support_rate_tbl[i].basic)
+				rate_set[*rate_num] = support_rate_tbl[i].rate | IEEE80211_BASIC_RATE_MASK;
+			else
+				rate_set[*rate_num] = support_rate_tbl[i].rate;
+			*rate_num += 1;
+		}
+	}
+
+	if (*rate_num == 0)
+		return _FAIL;
+
+	if (0) {
+		int i;
+
+		for (i = 0; i < *rate_num; i++)
+			RTW_INFO("rate:0x%02x\n", *(rate_set + i));
+	}
+
+	return _SUCCESS;
+}
+
+void process_addba_req(_adapter *padapter, u8 *paddba_req, u8 *addr)
+{
+	struct sta_info *psta;
+	u16 tid, start_seq, param;
+	struct sta_priv *pstapriv = &padapter->stapriv;
+	struct ADDBA_request	*preq = (struct ADDBA_request *)paddba_req;
+	u8 size, accept = _FALSE;
+
+	psta = rtw_get_stainfo(pstapriv, addr);
+	if (!psta)
+		goto exit;
+
+	start_seq = le16_to_cpu(preq->BA_starting_seqctrl) >> 4;
+
+	param = le16_to_cpu(preq->BA_para_set);
+	tid = (param >> 2) & 0x0f;
+
+
+	accept = rtw_rx_ampdu_is_accept(padapter);
+	if (padapter->fix_rx_ampdu_size != RX_AMPDU_SIZE_INVALID)
+		size = padapter->fix_rx_ampdu_size;
+	else {
+		size = rtw_rx_ampdu_size(padapter);
+		size = rtw_min(size, rx_ampdu_size_sta_limit(padapter, psta));
+	}
+
+	if (accept == _TRUE)
+		rtw_addbarsp_cmd(padapter, addr, tid, 0, size, start_seq);
+	else
+		rtw_addbarsp_cmd(padapter, addr, tid, 37, size, start_seq); /* reject ADDBA Req */
+
+exit:
+	return;
+}
+
+void rtw_process_bar_frame(_adapter *padapter, union recv_frame *precv_frame)
+{
+	struct sta_priv *pstapriv = &padapter->stapriv;
+	u8 *pframe = precv_frame->u.hdr.rx_data;
+	struct sta_info *psta = NULL;
+	struct recv_reorder_ctrl *preorder_ctrl = NULL;
+	u8 tid = 0;
+	u16 start_seq=0;
+
+	psta = rtw_get_stainfo(pstapriv, get_addr2_ptr(pframe));
+	if (psta == NULL)
+		goto exit;
+
+	tid = ((cpu_to_le16((*(u16 *)(pframe + 16))) & 0xf000) >> 12);
+	preorder_ctrl = &psta->recvreorder_ctrl[tid];
+	start_seq = ((cpu_to_le16(*(u16 *)(pframe + 18))) >> 4);
+	preorder_ctrl->indicate_seq = start_seq;
+
+	/* for Debug use */
+	if (0)
+		RTW_INFO(FUNC_ADPT_FMT" tid=%d, start_seq=%d\n", FUNC_ADPT_ARG(padapter),  tid, start_seq);
+
+exit:
+	return;
+}
+
+void update_TSF(struct mlme_ext_priv *pmlmeext, u8 *pframe, uint len)
+{
+	u8 *pIE;
+	u32 *pbuf;
+
+	pIE = pframe + sizeof(struct rtw_ieee80211_hdr_3addr);
+	pbuf = (u32 *)pIE;
+
+	pmlmeext->TSFValue = le32_to_cpu(*(pbuf + 1));
+
+	pmlmeext->TSFValue = pmlmeext->TSFValue << 32;
+
+	pmlmeext->TSFValue |= le32_to_cpu(*pbuf);
+}
+
+void correct_TSF(_adapter *padapter, u8 mlme_state)
+{
+	u8 m_state = mlme_state;
+
+	rtw_hal_set_hwreg(padapter, HW_VAR_CORRECT_TSF, (u8 *)&m_state);
+}
+
+#ifdef CONFIG_BCN_RECV_TIME
+/*	calculate beacon receiving time
+	1.RxBCNTime(CCK_1M) = [192us(preamble)] + [length of beacon(byte)*8us] + [10us]
+	2.RxBCNTime(OFDM_6M) = [8us(S) + 8us(L) + 4us(L-SIG)] + [(length of beacon(byte)/3 + 1] *4us] + [10us]
+*/
+inline u16 _rx_bcn_time_calculate(uint bcn_len, u8 data_rate)
+{
+	u16 rx_bcn_time = 0;/*us*/
+
+	if (data_rate == DESC_RATE1M)
+		rx_bcn_time = 192 + bcn_len * 8 + 10;
+	else if(data_rate == DESC_RATE6M)
+		rx_bcn_time = 8 + 8 + 4 + (bcn_len /3 + 1) * 4 + 10;
+/*
+	else
+		RTW_ERR("%s invalid data rate(0x%02x)\n", __func__, data_rate);
+*/
+	return rx_bcn_time;
+}
+void rtw_rx_bcn_time_update(_adapter *adapter, uint bcn_len, u8 data_rate)
+{
+	struct mlme_ext_priv *pmlmeext = &adapter->mlmeextpriv;
+
+	pmlmeext->bcn_rx_time = _rx_bcn_time_calculate(bcn_len, data_rate);
+}
+#endif
+
+void beacon_timing_control(_adapter *padapter)
+{
+	rtw_hal_bcn_related_reg_setting(padapter);
+}
+
+void dump_macid_map(void *sel, struct macid_bmp *map, u8 max_num)
+{
+	RTW_PRINT_SEL(sel, "0x%08x\n", map->m0);
+#if (MACID_NUM_SW_LIMIT > 32)
+	if (max_num && max_num > 32)
+		RTW_PRINT_SEL(sel, "0x%08x\n", map->m1);
+#endif
+#if (MACID_NUM_SW_LIMIT > 64)
+	if (max_num && max_num > 64)
+		RTW_PRINT_SEL(sel, "0x%08x\n", map->m2);
+#endif
+#if (MACID_NUM_SW_LIMIT > 96)
+	if (max_num && max_num > 96)
+		RTW_PRINT_SEL(sel, "0x%08x\n", map->m3);
+#endif
+}
+
+inline bool rtw_macid_is_set(struct macid_bmp *map, u8 id)
+{
+	if (id < 32)
+		return map->m0 & BIT(id);
+#if (MACID_NUM_SW_LIMIT > 32)
+	else if (id < 64)
+		return map->m1 & BIT(id - 32);
+#endif
+#if (MACID_NUM_SW_LIMIT > 64)
+	else if (id < 96)
+		return map->m2 & BIT(id - 64);
+#endif
+#if (MACID_NUM_SW_LIMIT > 96)
+	else if (id < 128)
+		return map->m3 & BIT(id - 96);
+#endif
+	else
+		rtw_warn_on(1);
+
+	return 0;
+}
+
+inline void rtw_macid_map_set(struct macid_bmp *map, u8 id)
+{
+	if (id < 32)
+		map->m0 |= BIT(id);
+#if (MACID_NUM_SW_LIMIT > 32)
+	else if (id < 64)
+		map->m1 |= BIT(id - 32);
+#endif
+#if (MACID_NUM_SW_LIMIT > 64)
+	else if (id < 96)
+		map->m2 |= BIT(id - 64);
+#endif
+#if (MACID_NUM_SW_LIMIT > 96)
+	else if (id < 128)
+		map->m3 |= BIT(id - 96);
+#endif
+	else
+		rtw_warn_on(1);
+}
+
+inline void rtw_macid_map_clr(struct macid_bmp *map, u8 id)
+{
+	if (id < 32)
+		map->m0 &= ~BIT(id);
+#if (MACID_NUM_SW_LIMIT > 32)
+	else if (id < 64)
+		map->m1 &= ~BIT(id - 32);
+#endif
+#if (MACID_NUM_SW_LIMIT > 64)
+	else if (id < 96)
+		map->m2 &= ~BIT(id - 64);
+#endif
+#if (MACID_NUM_SW_LIMIT > 96)
+	else if (id < 128)
+		map->m3 &= ~BIT(id - 96);
+#endif
+	else
+		rtw_warn_on(1);
+}
+
+inline bool rtw_macid_is_used(struct macid_ctl_t *macid_ctl, u8 id)
+{
+	return rtw_macid_is_set(&macid_ctl->used, id);
+}
+
+inline bool rtw_macid_is_bmc(struct macid_ctl_t *macid_ctl, u8 id)
+{
+	return rtw_macid_is_set(&macid_ctl->bmc, id);
+}
+
+inline u8 rtw_macid_get_iface_bmp(struct macid_ctl_t *macid_ctl, u8 id)
+{
+	int i;
+	u8 iface_bmp = 0;
+
+	for (i = 0; i < CONFIG_IFACE_NUMBER; i++) {
+		if (rtw_macid_is_set(&macid_ctl->if_g[i], id))
+			iface_bmp |= BIT(i);
+	}
+	return iface_bmp;
+}
+
+inline bool rtw_macid_is_iface_shared(struct macid_ctl_t *macid_ctl, u8 id)
+{
+	int i;
+	u8 iface_bmp = 0;
+
+	for (i = 0; i < CONFIG_IFACE_NUMBER; i++) {
+		if (rtw_macid_is_set(&macid_ctl->if_g[i], id)) {
+			if (iface_bmp)
+				return 1;
+			iface_bmp |= BIT(i);
+		}
+	}
+
+	return 0;
+}
+
+inline bool rtw_macid_is_iface_specific(struct macid_ctl_t *macid_ctl, u8 id, _adapter *adapter)
+{
+	int i;
+	u8 iface_bmp = 0;
+
+	for (i = 0; i < CONFIG_IFACE_NUMBER; i++) {
+		if (rtw_macid_is_set(&macid_ctl->if_g[i], id)) {
+			if (iface_bmp || i != adapter->iface_id)
+				return 0;
+			iface_bmp |= BIT(i);
+		}
+	}
+
+	return iface_bmp ? 1 : 0;
+}
+
+inline s8 rtw_macid_get_ch_g(struct macid_ctl_t *macid_ctl, u8 id)
+{
+	int i;
+
+	for (i = 0; i < 2; i++) {
+		if (rtw_macid_is_set(&macid_ctl->ch_g[i], id))
+			return i;
+	}
+	return -1;
+}
+
+/*Record bc's mac-id and sec-cam-id*/
+inline void rtw_iface_bcmc_id_set(_adapter *padapter, u8 mac_id)
+{
+	struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
+	struct macid_ctl_t *macid_ctl = dvobj_to_macidctl(dvobj);
+
+	macid_ctl->iface_bmc[padapter->iface_id] = mac_id;
+}
+inline u8 rtw_iface_bcmc_id_get(_adapter *padapter)
+{
+	struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
+	struct macid_ctl_t *macid_ctl = dvobj_to_macidctl(dvobj);
+
+	return macid_ctl->iface_bmc[padapter->iface_id];
+}
+#if defined(DBG_CONFIG_ERROR_RESET) && defined(CONFIG_CONCURRENT_MODE)
+void rtw_iface_bcmc_sec_cam_map_restore(_adapter *adapter)
+{
+	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
+	struct cam_ctl_t *cam_ctl = dvobj_to_sec_camctl(dvobj);
+	int cam_id = -1;
+
+	cam_id = rtw_iface_bcmc_id_get(adapter);
+	if (cam_id != INVALID_SEC_MAC_CAM_ID)
+		rtw_sec_cam_map_set(&cam_ctl->used, cam_id);
+}
+#endif
+void rtw_alloc_macid(_adapter *padapter, struct sta_info *psta)
+{
+	int i;
+	_irqL irqL;
+	u8 bc_addr[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
+	struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
+	struct macid_ctl_t *macid_ctl = dvobj_to_macidctl(dvobj);
+	struct macid_bmp *used_map = &macid_ctl->used;
+	/* static u8 last_id = 0;  for testing */
+	u8 last_id = 0;
+	u8 is_bc_sta = _FALSE;
+
+	if (_rtw_memcmp(psta->cmn.mac_addr, adapter_mac_addr(padapter), ETH_ALEN)) {
+		psta->cmn.mac_id = macid_ctl->num;
+		return;
+	}
+
+	if (_rtw_memcmp(psta->cmn.mac_addr, bc_addr, ETH_ALEN)) {
+		is_bc_sta = _TRUE;
+		rtw_iface_bcmc_id_set(padapter, INVALID_SEC_MAC_CAM_ID);	/*init default value*/
+	}
+
+	if (is_bc_sta
+		#ifdef CONFIG_CONCURRENT_MODE
+		&& (MLME_IS_STA(padapter) || MLME_IS_NULL(padapter))
+		#endif
+	) {
+		/* STA mode have no BMC data TX, shared with this macid */
+		/* When non-concurrent, only one BMC data TX is used, shared with this macid */
+		/* TODO: When concurrent, non-security BMC data TX may use this, but will not control by specific macid sleep */
+		i = RTW_DEFAULT_MGMT_MACID;
+		goto assigned;
+	}
+
+	_enter_critical_bh(&macid_ctl->lock, &irqL);
+
+	for (i = last_id; i < macid_ctl->num; i++) {
+#ifdef CONFIG_MCC_MODE
+		/* macid 0/1 reserve for mcc for mgnt queue macid */
+		if (MCC_EN(padapter)) {
+			if (i == MCC_ROLE_STA_GC_MGMT_QUEUE_MACID)
+				continue;
+			if (i == MCC_ROLE_SOFTAP_GO_MGMT_QUEUE_MACID)
+				continue;
+		}
+#endif /* CONFIG_MCC_MODE */
+
+		if (is_bc_sta) {
+			struct cam_ctl_t *cam_ctl = dvobj_to_sec_camctl(dvobj);
+
+			if ((!rtw_macid_is_used(macid_ctl, i)) && (!rtw_sec_camid_is_used(cam_ctl, i)))
+				break;
+		} else {
+			if (!rtw_macid_is_used(macid_ctl, i))
+				break;
+		}
+	}
+
+	if (i < macid_ctl->num) {
+
+		rtw_macid_map_set(used_map, i);
+
+		if (is_bc_sta) {
+			struct cam_ctl_t *cam_ctl = dvobj_to_sec_camctl(dvobj);
+
+			rtw_macid_map_set(&macid_ctl->bmc, i);
+			rtw_iface_bcmc_id_set(padapter, i);
+			rtw_sec_cam_map_set(&cam_ctl->used, i);
+		}
+
+		rtw_macid_map_set(&macid_ctl->if_g[padapter->iface_id], i);
+		macid_ctl->sta[i] = psta;
+
+		/* TODO ch_g? */
+
+		last_id++;
+		last_id %= macid_ctl->num;
+	}
+
+	_exit_critical_bh(&macid_ctl->lock, &irqL);
+
+	if (i >= macid_ctl->num) {
+		psta->cmn.mac_id = macid_ctl->num;
+		RTW_ERR(FUNC_ADPT_FMT" if%u, mac_addr:"MAC_FMT" no available macid\n"
+			, FUNC_ADPT_ARG(padapter), padapter->iface_id + 1, MAC_ARG(psta->cmn.mac_addr));
+		rtw_warn_on(1);
+		goto exit;
+	} else
+		goto assigned;
+
+assigned:
+	psta->cmn.mac_id = i;
+	RTW_INFO(FUNC_ADPT_FMT" if%u, mac_addr:"MAC_FMT" macid:%u\n"
+		, FUNC_ADPT_ARG(padapter), padapter->iface_id + 1, MAC_ARG(psta->cmn.mac_addr), psta->cmn.mac_id);
+
+exit:
+	return;
+}
+
+void rtw_release_macid(_adapter *padapter, struct sta_info *psta)
+{
+	_irqL irqL;
+	u8 bc_addr[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
+	struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
+	struct macid_ctl_t *macid_ctl = dvobj_to_macidctl(dvobj);
+	u8 ifbmp;
+	int i;
+
+	if (_rtw_memcmp(psta->cmn.mac_addr, adapter_mac_addr(padapter), ETH_ALEN))
+		goto exit;
+
+	if (psta->cmn.mac_id >= macid_ctl->num) {
+		RTW_WARN(FUNC_ADPT_FMT" if%u, mac_addr:"MAC_FMT" macid:%u not valid\n"
+			, FUNC_ADPT_ARG(padapter), padapter->iface_id + 1
+			, MAC_ARG(psta->cmn.mac_addr), psta->cmn.mac_id);
+		rtw_warn_on(1);
+		goto exit;
+	}
+
+	if (psta->cmn.mac_id == RTW_DEFAULT_MGMT_MACID)
+		goto msg;
+
+	_enter_critical_bh(&macid_ctl->lock, &irqL);
+
+	if (!rtw_macid_is_used(macid_ctl, psta->cmn.mac_id)) {
+		RTW_WARN(FUNC_ADPT_FMT" if%u, mac_addr:"MAC_FMT" macid:%u not used\n"
+			, FUNC_ADPT_ARG(padapter), padapter->iface_id + 1
+			, MAC_ARG(psta->cmn.mac_addr), psta->cmn.mac_id);
+		_exit_critical_bh(&macid_ctl->lock, &irqL);
+		rtw_warn_on(1);
+		goto exit;
+	}
+
+	ifbmp = rtw_macid_get_iface_bmp(macid_ctl, psta->cmn.mac_id);
+	if (!(ifbmp & BIT(padapter->iface_id))) {
+		RTW_WARN(FUNC_ADPT_FMT" if%u, mac_addr:"MAC_FMT" macid:%u not used by self\n"
+			, FUNC_ADPT_ARG(padapter), padapter->iface_id + 1
+			, MAC_ARG(psta->cmn.mac_addr), psta->cmn.mac_id);
+		_exit_critical_bh(&macid_ctl->lock, &irqL);
+		rtw_warn_on(1);
+		goto exit;
+	}
+
+	if (_rtw_memcmp(psta->cmn.mac_addr, bc_addr, ETH_ALEN)) {
+		struct cam_ctl_t *cam_ctl = dvobj_to_sec_camctl(dvobj);
+		u8 id = rtw_iface_bcmc_id_get(padapter);
+
+		if ((id != INVALID_SEC_MAC_CAM_ID) && (id < cam_ctl->num))
+			rtw_sec_cam_map_clr(&cam_ctl->used, id);
+
+		rtw_iface_bcmc_id_set(padapter, INVALID_SEC_MAC_CAM_ID);
+	}
+
+	rtw_macid_map_clr(&macid_ctl->if_g[padapter->iface_id], psta->cmn.mac_id);
+
+	ifbmp &= ~BIT(padapter->iface_id);
+	if (!ifbmp) { /* only used by self */
+		rtw_macid_map_clr(&macid_ctl->used, psta->cmn.mac_id);
+		rtw_macid_map_clr(&macid_ctl->bmc, psta->cmn.mac_id);
+		for (i = 0; i < 2; i++)
+			rtw_macid_map_clr(&macid_ctl->ch_g[i], psta->cmn.mac_id);
+		macid_ctl->sta[psta->cmn.mac_id] = NULL;
+	}
+
+	_exit_critical_bh(&macid_ctl->lock, &irqL);
+
+msg:
+	RTW_INFO(FUNC_ADPT_FMT" if%u, mac_addr:"MAC_FMT" macid:%u\n"
+		, FUNC_ADPT_ARG(padapter), padapter->iface_id + 1
+		, MAC_ARG(psta->cmn.mac_addr), psta->cmn.mac_id
+	);
+
+exit:
+	psta->cmn.mac_id = macid_ctl->num;
+}
+
+/* For 8188E RA */
+u8 rtw_search_max_mac_id(_adapter *padapter)
+{
+	u8 max_mac_id = 0;
+	struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
+	struct macid_ctl_t *macid_ctl = dvobj_to_macidctl(dvobj);
+	int i;
+	_irqL irqL;
+
+	/* TODO: Only search for connected macid? */
+
+	_enter_critical_bh(&macid_ctl->lock, &irqL);
+	for (i = (macid_ctl->num - 1); i > 0 ; i--) {
+		if (rtw_macid_is_used(macid_ctl, i))
+			break;
+	}
+	_exit_critical_bh(&macid_ctl->lock, &irqL);
+	max_mac_id = i;
+
+	return max_mac_id;
+}
+
+inline void rtw_macid_ctl_set_h2c_msr(struct macid_ctl_t *macid_ctl, u8 id, u8 h2c_msr)
+{
+	if (id >= macid_ctl->num) {
+		rtw_warn_on(1);
+		return;
+	}
+
+	macid_ctl->h2c_msr[id] = h2c_msr;
+	if (0)
+		RTW_INFO("macid:%u, h2c_msr:"H2C_MSR_FMT"\n", id, H2C_MSR_ARG(&macid_ctl->h2c_msr[id]));
+}
+
+inline void rtw_macid_ctl_set_bw(struct macid_ctl_t *macid_ctl, u8 id, u8 bw)
+{
+	if (id >= macid_ctl->num) {
+		rtw_warn_on(1);
+		return;
+	}
+
+	macid_ctl->bw[id] = bw;
+	if (0)
+		RTW_INFO("macid:%u, bw:%s\n", id, ch_width_str(macid_ctl->bw[id]));
+}
+
+inline void rtw_macid_ctl_set_vht_en(struct macid_ctl_t *macid_ctl, u8 id, u8 en)
+{
+	if (id >= macid_ctl->num) {
+		rtw_warn_on(1);
+		return;
+	}
+
+	macid_ctl->vht_en[id] = en;
+	if (0)
+		RTW_INFO("macid:%u, vht_en:%u\n", id, macid_ctl->vht_en[id]);
+}
+
+inline void rtw_macid_ctl_set_rate_bmp0(struct macid_ctl_t *macid_ctl, u8 id, u32 bmp)
+{
+	if (id >= macid_ctl->num) {
+		rtw_warn_on(1);
+		return;
+	}
+
+	macid_ctl->rate_bmp0[id] = bmp;
+	if (0)
+		RTW_INFO("macid:%u, rate_bmp0:0x%08X\n", id, macid_ctl->rate_bmp0[id]);
+}
+
+inline void rtw_macid_ctl_set_rate_bmp1(struct macid_ctl_t *macid_ctl, u8 id, u32 bmp)
+{
+	if (id >= macid_ctl->num) {
+		rtw_warn_on(1);
+		return;
+	}
+
+	macid_ctl->rate_bmp1[id] = bmp;
+	if (0)
+		RTW_INFO("macid:%u, rate_bmp1:0x%08X\n", id, macid_ctl->rate_bmp1[id]);
+}
+
+inline void rtw_macid_ctl_init_sleep_reg(struct macid_ctl_t *macid_ctl, u16 m0, u16 m1, u16 m2, u16 m3)
+{
+	macid_ctl->reg_sleep_m0 = m0;
+#if (MACID_NUM_SW_LIMIT > 32)
+	macid_ctl->reg_sleep_m1 = m1;
+#endif
+#if (MACID_NUM_SW_LIMIT > 64)
+	macid_ctl->reg_sleep_m2 = m2;
+#endif
+#if (MACID_NUM_SW_LIMIT > 96)
+	macid_ctl->reg_sleep_m3 = m3;
+#endif
+}
+
+inline void rtw_macid_ctl_init(struct macid_ctl_t *macid_ctl)
+{
+	int i;
+	u8 id = RTW_DEFAULT_MGMT_MACID;
+
+	rtw_macid_map_set(&macid_ctl->used, id);
+	rtw_macid_map_set(&macid_ctl->bmc, id);
+	for (i = 0; i < CONFIG_IFACE_NUMBER; i++)
+		rtw_macid_map_set(&macid_ctl->if_g[i], id);
+	macid_ctl->sta[id] = NULL;
+
+	_rtw_spinlock_init(&macid_ctl->lock);
+}
+
+inline void rtw_macid_ctl_deinit(struct macid_ctl_t *macid_ctl)
+{
+	_rtw_spinlock_free(&macid_ctl->lock);
+}
+
+inline bool rtw_bmp_is_set(const u8 *bmp, u8 bmp_len, u8 id)
+{
+	if (id / 8 >= bmp_len)
+		return 0;
+
+	return bmp[id / 8] & BIT(id % 8);
+}
+
+inline void rtw_bmp_set(u8 *bmp, u8 bmp_len, u8 id)
+{
+	if (id / 8 < bmp_len)
+		bmp[id / 8] |= BIT(id % 8);
+}
+
+inline void rtw_bmp_clear(u8 *bmp, u8 bmp_len, u8 id)
+{
+	if (id / 8 < bmp_len)
+		bmp[id / 8] &= ~BIT(id % 8);
+}
+
+inline bool rtw_bmp_not_empty(const u8 *bmp, u8 bmp_len)
+{
+	int i;
+
+	for (i = 0; i < bmp_len; i++) {
+		if (bmp[i])
+			return 1;
+	}
+
+	return 0;
+}
+
+inline bool rtw_bmp_not_empty_exclude_bit0(const u8 *bmp, u8 bmp_len)
+{
+	int i;
+
+	for (i = 0; i < bmp_len; i++) {
+		if (i == 0) {
+			if (bmp[i] & 0xFE)
+				return 1;
+		} else {
+			if (bmp[i])
+				return 1;
+		}
+	}
+
+	return 0;
+}
+
+#ifdef CONFIG_AP_MODE
+/* Check the id be set or not in map , if yes , return a none zero value*/
+bool rtw_tim_map_is_set(_adapter *padapter, const u8 *map, u8 id)
+{
+	return rtw_bmp_is_set(map, padapter->stapriv.aid_bmp_len, id);
+}
+
+/* Set the id into map array*/
+void rtw_tim_map_set(_adapter *padapter, u8 *map, u8 id)
+{
+	rtw_bmp_set(map, padapter->stapriv.aid_bmp_len, id);
+}
+
+/* Clear the id from map array*/
+void rtw_tim_map_clear(_adapter *padapter, u8 *map, u8 id)
+{
+	rtw_bmp_clear(map, padapter->stapriv.aid_bmp_len, id);
+}
+
+/* Check have anyone bit be set , if yes return true*/
+bool rtw_tim_map_anyone_be_set(_adapter *padapter, const u8 *map)
+{
+	return rtw_bmp_not_empty(map, padapter->stapriv.aid_bmp_len);
+}
+
+/* Check have anyone bit be set exclude bit0 , if yes return true*/
+bool rtw_tim_map_anyone_be_set_exclude_aid0(_adapter *padapter, const u8 *map)
+{
+	return rtw_bmp_not_empty_exclude_bit0(map, padapter->stapriv.aid_bmp_len);
+}
+#endif /* CONFIG_AP_MODE */
+
+#if 0
+unsigned int setup_beacon_frame(_adapter *padapter, unsigned char *beacon_frame)
+{
+	unsigned short				ATIMWindow;
+	unsigned char					*pframe;
+	struct tx_desc				*ptxdesc;
+	struct rtw_ieee80211_hdr	*pwlanhdr;
+	unsigned short				*fctrl;
+	unsigned int					rate_len, len = 0;
+	struct xmit_priv			*pxmitpriv = &(padapter->xmitpriv);
+	struct mlme_ext_priv	*pmlmeext = &(padapter->mlmeextpriv);
+	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
+	WLAN_BSSID_EX		*cur_network = &(pmlmeinfo->network);
+	u8	bc_addr[] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
+
+	_rtw_memset(beacon_frame, 0, 256);
+
+	pframe = beacon_frame + TXDESC_SIZE;
+
+	pwlanhdr = (struct rtw_ieee80211_hdr *)pframe;
+
+	fctrl = &(pwlanhdr->frame_ctl);
+	*(fctrl) = 0;
+
+	_rtw_memcpy(pwlanhdr->addr1, bc_addr, ETH_ALEN);
+	_rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN);
+	_rtw_memcpy(pwlanhdr->addr3, get_my_bssid(cur_network), ETH_ALEN);
+
+	set_frame_sub_type(pframe, WIFI_BEACON);
+
+	pframe += sizeof(struct rtw_ieee80211_hdr_3addr);
+	len = sizeof(struct rtw_ieee80211_hdr_3addr);
+
+	/* timestamp will be inserted by hardware */
+	pframe += 8;
+	len += 8;
+
+	/* beacon interval: 2 bytes */
+	_rtw_memcpy(pframe, (unsigned char *)(rtw_get_beacon_interval_from_ie(cur_network->IEs)), 2);
+
+	pframe += 2;
+	len += 2;
+
+	/* capability info: 2 bytes */
+	_rtw_memcpy(pframe, (unsigned char *)(rtw_get_capability_from_ie(cur_network->IEs)), 2);
+
+	pframe += 2;
+	len += 2;
+
+	/* SSID */
+	pframe = rtw_set_ie(pframe, _SSID_IE_, cur_network->Ssid.SsidLength, cur_network->Ssid.Ssid, &len);
+
+	/* supported rates... */
+	rate_len = rtw_get_rateset_len(cur_network->SupportedRates);
+	pframe = rtw_set_ie(pframe, _SUPPORTEDRATES_IE_, ((rate_len > 8) ? 8 : rate_len), cur_network->SupportedRates, &len);
+
+	/* DS parameter set */
+	pframe = rtw_set_ie(pframe, _DSSET_IE_, 1, (unsigned char *)&(cur_network->Configuration.DSConfig), &len);
+
+	/* IBSS Parameter Set... */
+	/* ATIMWindow = cur->Configuration.ATIMWindow; */
+	ATIMWindow = 0;
+	pframe = rtw_set_ie(pframe, _IBSS_PARA_IE_, 2, (unsigned char *)(&ATIMWindow), &len);
+
+	/* todo: ERP IE */
+
+	/* EXTERNDED SUPPORTED RATE */
+	if (rate_len > 8)
+		pframe = rtw_set_ie(pframe, _EXT_SUPPORTEDRATES_IE_, (rate_len - 8), (cur_network->SupportedRates + 8), &len);
+
+	if ((len + TXDESC_SIZE) > 256) {
+		/* RTW_INFO("marc: beacon frame too large\n"); */
+		return 0;
+	}
+
+	/* fill the tx descriptor */
+	ptxdesc = (struct tx_desc *)beacon_frame;
+
+	/* offset 0	 */
+	ptxdesc->txdw0 |= cpu_to_le32(len & 0x0000ffff);
+	ptxdesc->txdw0 |= cpu_to_le32(((TXDESC_SIZE + OFFSET_SZ) << OFFSET_SHT) & 0x00ff0000); /* default = 32 bytes for TX Desc */
+
+	/* offset 4	 */
+	ptxdesc->txdw1 |= cpu_to_le32((0x10 << QSEL_SHT) & 0x00001f00);
+
+	/* offset 8		 */
+	ptxdesc->txdw2 |= cpu_to_le32(BMC);
+	ptxdesc->txdw2 |= cpu_to_le32(BK);
+
+	/* offset 16		 */
+	ptxdesc->txdw4 = 0x80000000;
+
+	/* offset 20 */
+	ptxdesc->txdw5 = 0x00000000; /* 1M	 */
+
+	return len + TXDESC_SIZE;
+}
+#endif
+
+_adapter *dvobj_get_port0_adapter(struct dvobj_priv *dvobj)
+{
+	_adapter *port0_iface = NULL;
+	int i;
+	for (i = 0; i < dvobj->iface_nums; i++) {
+		if (get_hw_port(dvobj->padapters[i]) == HW_PORT0)
+			break;
+	}
+
+	if (i < 0 || i >= dvobj->iface_nums)
+		rtw_warn_on(1);
+	else
+		port0_iface = dvobj->padapters[i];
+
+	return port0_iface;
+}
+
+_adapter *dvobj_get_unregisterd_adapter(struct dvobj_priv *dvobj)
+{
+	_adapter *adapter = NULL;
+	int i;
+
+	for (i = 0; i < dvobj->iface_nums; i++) {
+		if (dvobj->padapters[i]->registered == 0)
+			break;
+	}
+
+	if (i < dvobj->iface_nums)
+		adapter = dvobj->padapters[i];
+
+	return adapter;
+}
+
+_adapter *dvobj_get_adapter_by_addr(struct dvobj_priv *dvobj, u8 *addr)
+{
+	_adapter *adapter = NULL;
+	int i;
+
+	for (i = 0; i < dvobj->iface_nums; i++) {
+		if (_rtw_memcmp(dvobj->padapters[i]->mac_addr, addr, ETH_ALEN) == _TRUE)
+			break;
+	}
+
+	if (i < dvobj->iface_nums)
+		adapter = dvobj->padapters[i];
+
+	return adapter;
+}
+
+#ifdef CONFIG_WOWLAN
+bool rtw_wowlan_parser_pattern_cmd(u8 *input, char *pattern,
+				   int *pattern_len, char *bit_mask)
+{
+	char *cp = NULL, *end = NULL;
+	size_t len = 0;
+	int pos = 0, mask_pos = 0, res = 0;
+	u8 member[2] = {0};
+
+	cp = strchr(input, '=');
+	if (cp) {
+		*cp = 0;
+		cp++;
+		input = cp;
+	}
+
+	while (1) {
+		cp = strchr(input, ':');
+
+		if (cp) {
+			len = strlen(input) - strlen(cp);
+			*cp = 0;
+			cp++;
+		} else
+			len = 2;
+
+		if (bit_mask && (strcmp(input, "-") == 0 ||
+				 strcmp(input, "xx") == 0 ||
+				 strcmp(input, "--") == 0)) {
+			/* skip this byte and leave mask bit unset */
+		} else {
+			u8 hex;
+
+			strncpy(member, input, len);
+			if (!rtw_check_pattern_valid(member, sizeof(member))) {
+				RTW_INFO("%s:[ERROR] pattern is invalid!!\n",
+					 __func__);
+				goto error;
+			}
+
+			res = sscanf(member, "%02hhx", &hex);
+			pattern[pos] = hex;
+			mask_pos = pos / 8;
+			if (bit_mask)
+				bit_mask[mask_pos] |= 1 << (pos % 8);
+		}
+
+		pos++;
+		if (!cp)
+			break;
+		input = cp;
+	}
+
+	(*pattern_len) = pos;
+
+	return _TRUE;
+error:
+	return _FALSE;
+}
+
+bool rtw_check_pattern_valid(u8 *input, u8 len)
+{
+	int i = 0;
+	bool res = _FALSE;
+
+	if (len != 2)
+		goto exit;
+
+	for (i = 0 ; i < len ; i++)
+		if (IsHexDigit(input[i]) == _FALSE)
+			goto exit;
+
+	res = _SUCCESS;
+
+exit:
+	return res;
+}
+void rtw_wow_pattern_sw_reset(_adapter *adapter)
+{
+	int i;
+	struct pwrctrl_priv *pwrctrlpriv = adapter_to_pwrctl(adapter);
+
+	if (pwrctrlpriv->default_patterns_en == _TRUE)
+		pwrctrlpriv->wowlan_pattern_idx = DEFAULT_PATTERN_NUM;
+	else
+		pwrctrlpriv->wowlan_pattern_idx = 0;
+
+	for (i = 0 ; i < MAX_WKFM_CAM_NUM; i++) {
+		_rtw_memset(pwrctrlpriv->patterns[i].content, '\0', sizeof(pwrctrlpriv->patterns[i].content));
+		_rtw_memset(pwrctrlpriv->patterns[i].mask, '\0', sizeof(pwrctrlpriv->patterns[i].mask));
+		pwrctrlpriv->patterns[i].len = 0;
+	}
+}
+
+u8 rtw_set_default_pattern(_adapter *adapter)
+{
+	struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(adapter);
+	struct mlme_ext_priv *pmlmeext = &adapter->mlmeextpriv;
+	struct mlme_ext_info *pmlmeinfo = &pmlmeext->mlmext_info;
+	u8 index = 0;
+	u8 multicast_addr[3] = {0x01, 0x00, 0x5e};
+	u8 multicast_ip[4] = {0xe0, 0x28, 0x28, 0x2a};
+
+	u8 unicast_mask[5] = {0x3f, 0x70, 0x80, 0xc0, 0x03};
+	u8 icmpv6_mask[7] = {0x00, 0x70, 0x10, 0x00, 0xc0, 0xc0, 0x3f};
+	u8 multicast_mask[5] = {0x07, 0x70, 0x80, 0xc0, 0x03};
+
+	u8 ip_protocol[3] = {0x08, 0x00, 0x45};
+	u8 ipv6_protocol[3] = {0x86, 0xdd, 0x60};
+
+	u8 *target = NULL;
+
+	if (pwrpriv->default_patterns_en == _FALSE)
+		return 0;
+
+	for (index = 0 ; index < DEFAULT_PATTERN_NUM ; index++) {
+		_rtw_memset(pwrpriv->patterns[index].content, 0,
+			    sizeof(pwrpriv->patterns[index].content));
+		_rtw_memset(pwrpriv->patterns[index].mask, 0,
+			    sizeof(pwrpriv->patterns[index].mask));
+		pwrpriv->patterns[index].len = 0;
+	}
+
+	/*TCP/ICMP unicast*/
+	for (index = 0 ; index < DEFAULT_PATTERN_NUM ; index++) {
+		switch (index) {
+		case 0:
+			target = pwrpriv->patterns[index].content;
+			_rtw_memcpy(target, adapter_mac_addr(adapter),
+				    ETH_ALEN);
+
+			target += ETH_TYPE_OFFSET;
+			_rtw_memcpy(target, &ip_protocol,
+				    sizeof(ip_protocol));
+
+			/* TCP */
+			target += (PROTOCOL_OFFSET - ETH_TYPE_OFFSET);
+			_rtw_memset(target, 0x06, 1);
+
+			target += (IP_OFFSET - PROTOCOL_OFFSET);
+
+			_rtw_memcpy(target, pmlmeinfo->ip_addr,
+				    RTW_IP_ADDR_LEN);
+
+			_rtw_memcpy(pwrpriv->patterns[index].mask,
+				    &unicast_mask, sizeof(unicast_mask));
+
+			pwrpriv->patterns[index].len =
+				IP_OFFSET + RTW_IP_ADDR_LEN;
+			break;
+		case 1:
+			target = pwrpriv->patterns[index].content;
+			_rtw_memcpy(target, adapter_mac_addr(adapter),
+				    ETH_ALEN);
+
+			target += ETH_TYPE_OFFSET;
+			_rtw_memcpy(target, &ip_protocol, sizeof(ip_protocol));
+
+			/* ICMP */
+			target += (PROTOCOL_OFFSET - ETH_TYPE_OFFSET);
+			_rtw_memset(target, 0x01, 1);
+
+			target += (IP_OFFSET - PROTOCOL_OFFSET);
+			_rtw_memcpy(target, pmlmeinfo->ip_addr,
+				    RTW_IP_ADDR_LEN);
+
+			_rtw_memcpy(pwrpriv->patterns[index].mask,
+				    &unicast_mask, sizeof(unicast_mask));
+			pwrpriv->patterns[index].len =
+
+				IP_OFFSET + RTW_IP_ADDR_LEN;
+			break;
+#ifdef CONFIG_IPV6
+		case 2:
+			if (pwrpriv->wowlan_ns_offload_en == _TRUE) {
+				target = pwrpriv->patterns[index].content;
+				target += ETH_TYPE_OFFSET;
+
+				_rtw_memcpy(target, &ipv6_protocol,
+					    sizeof(ipv6_protocol));
+
+				/* ICMPv6 */
+				target += (IPv6_PROTOCOL_OFFSET -
+					   ETH_TYPE_OFFSET);
+				_rtw_memset(target, 0x3a, 1);
+
+				target += (IPv6_OFFSET - IPv6_PROTOCOL_OFFSET);
+				_rtw_memcpy(target, pmlmeinfo->ip6_addr,
+					    RTW_IPv6_ADDR_LEN);
+
+				_rtw_memcpy(pwrpriv->patterns[index].mask,
+					    &icmpv6_mask, sizeof(icmpv6_mask));
+				pwrpriv->patterns[index].len =
+					IPv6_OFFSET + RTW_IPv6_ADDR_LEN;
+			}
+			break;
+#endif /*CONFIG_IPV6*/
+		case 3:
+			target = pwrpriv->patterns[index].content;
+			_rtw_memcpy(target, &multicast_addr,
+				    sizeof(multicast_addr));
+
+			target += ETH_TYPE_OFFSET;
+			_rtw_memcpy(target, &ip_protocol, sizeof(ip_protocol));
+
+			/* UDP */
+			target += (PROTOCOL_OFFSET - ETH_TYPE_OFFSET);
+			_rtw_memset(target, 0x11, 1);
+
+			target += (IP_OFFSET - PROTOCOL_OFFSET);
+			_rtw_memcpy(target, &multicast_ip,
+				    sizeof(multicast_ip));
+
+			_rtw_memcpy(pwrpriv->patterns[index].mask,
+				    &multicast_mask, sizeof(multicast_mask));
+
+			pwrpriv->patterns[index].len =
+				IP_OFFSET + sizeof(multicast_ip);
+			break;
+		default:
+			break;
+		}
+	}
+	return index;
+}
+
+void rtw_dump_priv_pattern(_adapter *adapter, u8 idx)
+{
+	struct pwrctrl_priv *pwrctl = adapter_to_pwrctl(adapter);
+	char str_1[128];
+	char *p_str;
+	u8 val8 = 0;
+	int i = 0, j = 0, len = 0, max_len = 0;
+
+	RTW_INFO("=========[%d]========\n", idx);
+
+	RTW_INFO(">>>priv_pattern_content:\n");
+	p_str = str_1;
+	max_len = sizeof(str_1);
+	for (i = 0 ; i < MAX_WKFM_PATTERN_SIZE / 8 ; i++) {
+		_rtw_memset(p_str, 0, max_len);
+		len = 0;
+		for (j = 0 ; j < 8 ; j++) {
+			val8 = pwrctl->patterns[idx].content[i * 8 + j];
+			len += snprintf(p_str + len, max_len - len,
+					"%02x ", val8);
+		}
+		RTW_INFO("%s\n", p_str);
+	}
+
+	RTW_INFO(">>>priv_pattern_mask:\n");
+	for (i = 0 ; i < MAX_WKFM_SIZE / 8 ; i++) {
+		_rtw_memset(p_str, 0, max_len);
+		len = 0;
+		for (j = 0 ; j < 8 ; j++) {
+			val8 = pwrctl->patterns[idx].mask[i * 8 + j];
+			len += snprintf(p_str + len, max_len - len,
+					"%02x ", val8);
+		}
+		RTW_INFO("%s\n", p_str);
+	}
+
+	RTW_INFO(">>>priv_pattern_len:\n");
+	RTW_INFO("%s: len: %d\n", __func__, pwrctl->patterns[idx].len);
+}
+
+void rtw_wow_pattern_sw_dump(_adapter *adapter)
+{
+	int i;
+
+	RTW_INFO("********[RTK priv-patterns]*********\n");
+	for (i = 0 ; i < MAX_WKFM_CAM_NUM; i++)
+		rtw_dump_priv_pattern(adapter, i);
+}
+
+void rtw_get_sec_iv(PADAPTER padapter, u8 *pcur_dot11txpn, u8 *StaAddr)
+{
+	struct sta_info		*psta;
+	struct security_priv *psecpriv = &padapter->securitypriv;
+
+	_rtw_memset(pcur_dot11txpn, 0, 8);
+	if (NULL == StaAddr)
+		return;
+	psta = rtw_get_stainfo(&padapter->stapriv, StaAddr);
+	RTW_INFO("%s(): StaAddr: %02x %02x %02x %02x %02x %02x\n",
+		 __func__, StaAddr[0], StaAddr[1], StaAddr[2],
+		 StaAddr[3], StaAddr[4], StaAddr[5]);
+
+	if (psta) {
+		if (psecpriv->dot11PrivacyAlgrthm == _AES_)
+			AES_IV(pcur_dot11txpn, psta->dot11txpn, 0);
+		else if (psecpriv->dot11PrivacyAlgrthm == _TKIP_)
+			TKIP_IV(pcur_dot11txpn, psta->dot11txpn, 0);
+
+		RTW_INFO("%s(): CurrentIV: %02x %02x %02x %02x %02x %02x %02x %02x\n"
+			 , __func__, pcur_dot11txpn[0], pcur_dot11txpn[1],
+			pcur_dot11txpn[2], pcur_dot11txpn[3], pcur_dot11txpn[4],
+			pcur_dot11txpn[5], pcur_dot11txpn[6], pcur_dot11txpn[7]);
+	}
+}
+#endif /* CONFIG_WOWLAN */
+
+#ifdef CONFIG_PNO_SUPPORT
+#define	CSCAN_TLV_TYPE_SSID_IE	'S'
+#define CIPHER_IE "key_mgmt="
+#define CIPHER_NONE "NONE"
+#define CIPHER_WPA_PSK "WPA-PSK"
+#define CIPHER_WPA_EAP "WPA-EAP IEEE8021X"
+/*
+ *  SSIDs list parsing from cscan tlv list
+ */
+int rtw_parse_ssid_list_tlv(char **list_str, pno_ssid_t *ssid,
+			    int max, int *bytes_left)
+{
+	char *str;
+
+	int idx = 0;
+
+	if ((list_str == NULL) || (*list_str == NULL) || (*bytes_left < 0)) {
+		RTW_INFO("%s error paramters\n", __func__);
+		return -1;
+	}
+
+	str = *list_str;
+	while (*bytes_left > 0) {
+
+		if (str[0] != CSCAN_TLV_TYPE_SSID_IE) {
+			*list_str = str;
+			RTW_INFO("nssid=%d left_parse=%d %d\n", idx, *bytes_left, str[0]);
+			return idx;
+		}
+
+		/* Get proper CSCAN_TLV_TYPE_SSID_IE */
+		*bytes_left -= 1;
+		str += 1;
+
+		if (str[0] == 0) {
+			/* Broadcast SSID */
+			ssid[idx].SSID_len = 0;
+			memset((char *)ssid[idx].SSID, 0x0, WLAN_SSID_MAXLEN);
+			*bytes_left -= 1;
+			str += 1;
+
+			RTW_INFO("BROADCAST SCAN  left=%d\n", *bytes_left);
+		} else if (str[0] <= WLAN_SSID_MAXLEN) {
+			/* Get proper SSID size */
+			ssid[idx].SSID_len = str[0];
+			*bytes_left -= 1;
+			str += 1;
+
+			/* Get SSID */
+			if (ssid[idx].SSID_len > *bytes_left) {
+				RTW_INFO("%s out of memory range len=%d but left=%d\n",
+					__func__, ssid[idx].SSID_len, *bytes_left);
+				return -1;
+			}
+
+			memcpy((char *)ssid[idx].SSID, str, ssid[idx].SSID_len);
+
+			*bytes_left -= ssid[idx].SSID_len;
+			str += ssid[idx].SSID_len;
+
+			RTW_INFO("%s :size=%d left=%d\n",
+				(char *)ssid[idx].SSID, ssid[idx].SSID_len, *bytes_left);
+		} else {
+			RTW_INFO("### SSID size more that %d\n", str[0]);
+			return -1;
+		}
+
+		if (idx++ >  max) {
+			RTW_INFO("%s number of SSIDs more that %d\n", __func__, idx);
+			return -1;
+		}
+	}
+
+	*list_str = str;
+	return idx;
+}
+
+int rtw_parse_cipher_list(struct pno_nlo_info *nlo_info, char *list_str)
+{
+
+	char *pch, *pnext, *pend;
+	u8 key_len = 0, index = 0;
+
+	pch = list_str;
+
+	if (nlo_info == NULL || list_str == NULL) {
+		RTW_INFO("%s error paramters\n", __func__);
+		return -1;
+	}
+
+	while (strlen(pch) != 0) {
+		pnext = strstr(pch, "key_mgmt=");
+		if (pnext != NULL) {
+			pch = pnext + strlen(CIPHER_IE);
+			pend = strstr(pch, "}");
+			if (strncmp(pch, CIPHER_NONE,
+				    strlen(CIPHER_NONE)) == 0)
+				nlo_info->ssid_cipher_info[index] = 0x00;
+			else if (strncmp(pch, CIPHER_WPA_PSK,
+					 strlen(CIPHER_WPA_PSK)) == 0)
+				nlo_info->ssid_cipher_info[index] = 0x66;
+			else if (strncmp(pch, CIPHER_WPA_EAP,
+					 strlen(CIPHER_WPA_EAP)) == 0)
+				nlo_info->ssid_cipher_info[index] = 0x01;
+			index++;
+			pch = pend + 1;
+		} else
+			break;
+	}
+	return 0;
+}
+
+int rtw_dev_nlo_info_set(struct pno_nlo_info *nlo_info, pno_ssid_t *ssid,
+		 int num, int pno_time, int pno_repeat, int pno_freq_expo_max)
+{
+
+	int i = 0;
+	struct file *fp;
+	mm_segment_t fs;
+	loff_t pos = 0;
+	u8 *source = NULL;
+	long len = 0;
+
+	RTW_INFO("+%s+\n", __func__);
+
+	nlo_info->fast_scan_period = pno_time;
+	nlo_info->ssid_num = num & BIT_LEN_MASK_32(8);
+	nlo_info->hidden_ssid_num = num & BIT_LEN_MASK_32(8);
+	nlo_info->slow_scan_period = (pno_time * 2);
+	nlo_info->fast_scan_iterations = 5;
+
+	if (nlo_info->hidden_ssid_num > 8)
+		nlo_info->hidden_ssid_num = 8;
+
+	/* TODO: channel list and probe index is all empty. */
+	for (i = 0 ; i < num ; i++) {
+		nlo_info->ssid_length[i]
+			= ssid[i].SSID_len;
+	}
+
+	/* cipher array */
+	fp = filp_open("/data/misc/wifi/wpa_supplicant.conf", O_RDONLY,  0644);
+	if (IS_ERR(fp)) {
+		RTW_INFO("Error, wpa_supplicant.conf doesn't exist.\n");
+		RTW_INFO("Error, cipher array using default value.\n");
+		return 0;
+	}
+
+	len = i_size_read(fp->f_path.dentry->d_inode);
+	if (len < 0 || len > 2048) {
+		RTW_INFO("Error, file size is bigger than 2048.\n");
+		RTW_INFO("Error, cipher array using default value.\n");
+		return 0;
+	}
+
+	fs = get_fs();
+	set_fs(KERNEL_DS);
+
+	source = rtw_zmalloc(2048);
+
+	if (source != NULL) {
+		len = vfs_read(fp, source, len, &pos);
+		rtw_parse_cipher_list(nlo_info, source);
+		rtw_mfree(source, 2048);
+	}
+
+	set_fs(fs);
+	filp_close(fp, NULL);
+
+	RTW_INFO("-%s-\n", __func__);
+	return 0;
+}
+
+int rtw_dev_ssid_list_set(struct pno_ssid_list *pno_ssid_list,
+			  pno_ssid_t *ssid, u8 num)
+{
+
+	int i = 0;
+	if (num > MAX_PNO_LIST_COUNT)
+		num = MAX_PNO_LIST_COUNT;
+
+	for (i = 0 ; i < num ; i++) {
+		_rtw_memcpy(&pno_ssid_list->node[i].SSID,
+			    ssid[i].SSID, ssid[i].SSID_len);
+		pno_ssid_list->node[i].SSID_len = ssid[i].SSID_len;
+	}
+	return 0;
+}
+
+int rtw_dev_scan_info_set(_adapter *padapter, pno_ssid_t *ssid,
+	  unsigned char ch, unsigned char ch_offset, unsigned short bw_mode)
+{
+
+	struct pwrctrl_priv *pwrctl = adapter_to_pwrctl(padapter);
+	struct pno_scan_info *scan_info = pwrctl->pscan_info;
+	int i;
+
+	scan_info->channel_num = MAX_SCAN_LIST_COUNT;
+	scan_info->orig_ch = ch;
+	scan_info->orig_bw = bw_mode;
+	scan_info->orig_40_offset = ch_offset;
+
+	for (i = 0 ; i < scan_info->channel_num ; i++) {
+		if (i < 11)
+			scan_info->ssid_channel_info[i].active = 1;
+		else
+			scan_info->ssid_channel_info[i].active = 0;
+
+		scan_info->ssid_channel_info[i].timeout = 100;
+
+		scan_info->ssid_channel_info[i].tx_power =
+			phy_get_tx_power_index(padapter, 0, 0x02, bw_mode, i + 1);
+
+		scan_info->ssid_channel_info[i].channel = i + 1;
+	}
+
+	RTW_INFO("%s, channel_num: %d, orig_ch: %d, orig_bw: %d orig_40_offset: %d\n",
+		 __func__, scan_info->channel_num, scan_info->orig_ch,
+		 scan_info->orig_bw, scan_info->orig_40_offset);
+	return 0;
+}
+
+int rtw_dev_pno_set(struct net_device *net, pno_ssid_t *ssid, int num,
+		    int pno_time, int pno_repeat, int pno_freq_expo_max)
+{
+
+	_adapter *padapter = (_adapter *)rtw_netdev_priv(net);
+	struct pwrctrl_priv *pwrctl = adapter_to_pwrctl(padapter);
+	struct mlme_ext_priv	*pmlmeext = &padapter->mlmeextpriv;
+
+	int ret = -1;
+
+	if (num == 0) {
+		RTW_INFO("%s, nssid is zero, no need to setup pno ssid list\n", __func__);
+		return 0;
+	}
+
+	if (pwrctl == NULL) {
+		RTW_INFO("%s, ERROR: pwrctl is NULL\n", __func__);
+		return -1;
+	} else {
+		pwrctl->pnlo_info =
+			(pno_nlo_info_t *)rtw_zmalloc(sizeof(pno_nlo_info_t));
+		pwrctl->pno_ssid_list =
+			(pno_ssid_list_t *)rtw_zmalloc(sizeof(pno_ssid_list_t));
+		pwrctl->pscan_info =
+			(pno_scan_info_t *)rtw_zmalloc(sizeof(pno_scan_info_t));
+	}
+
+	if (pwrctl->pnlo_info == NULL ||
+	    pwrctl->pscan_info == NULL ||
+	    pwrctl->pno_ssid_list == NULL) {
+		RTW_INFO("%s, ERROR: alloc nlo_info, ssid_list, scan_info fail\n", __func__);
+		goto failing;
+	}
+
+	pwrctl->wowlan_in_resume = _FALSE;
+
+	pwrctl->pno_inited = _TRUE;
+	/* NLO Info */
+	ret = rtw_dev_nlo_info_set(pwrctl->pnlo_info, ssid, num,
+				   pno_time, pno_repeat, pno_freq_expo_max);
+
+	/* SSID Info */
+	ret = rtw_dev_ssid_list_set(pwrctl->pno_ssid_list, ssid, num);
+
+	/* SCAN Info */
+	ret = rtw_dev_scan_info_set(padapter, ssid, pmlmeext->cur_channel,
+			    pmlmeext->cur_ch_offset, pmlmeext->cur_bwmode);
+
+	RTW_INFO("+%s num: %d, pno_time: %d, pno_repeat:%d, pno_freq_expo_max:%d+\n",
+		 __func__, num, pno_time, pno_repeat, pno_freq_expo_max);
+
+	return 0;
+
+failing:
+	if (pwrctl->pnlo_info) {
+		rtw_mfree((u8 *)pwrctl->pnlo_info, sizeof(pno_nlo_info_t));
+		pwrctl->pnlo_info = NULL;
+	}
+	if (pwrctl->pno_ssid_list) {
+		rtw_mfree((u8 *)pwrctl->pno_ssid_list, sizeof(pno_ssid_list_t));
+		pwrctl->pno_ssid_list = NULL;
+	}
+	if (pwrctl->pscan_info) {
+		rtw_mfree((u8 *)pwrctl->pscan_info, sizeof(pno_scan_info_t));
+		pwrctl->pscan_info = NULL;
+	}
+
+	return -1;
+}
+
+#ifdef CONFIG_PNO_SET_DEBUG
+void rtw_dev_pno_debug(struct net_device *net)
+{
+	_adapter *padapter = (_adapter *)rtw_netdev_priv(net);
+	struct pwrctrl_priv *pwrctl = adapter_to_pwrctl(padapter);
+	int i = 0, j = 0;
+
+	RTW_INFO("*******NLO_INFO********\n");
+	RTW_INFO("ssid_num: %d\n", pwrctl->pnlo_info->ssid_num);
+	RTW_INFO("fast_scan_iterations: %d\n",
+		 pwrctl->pnlo_info->fast_scan_iterations);
+	RTW_INFO("fast_scan_period: %d\n", pwrctl->pnlo_info->fast_scan_period);
+	RTW_INFO("slow_scan_period: %d\n", pwrctl->pnlo_info->slow_scan_period);
+
+
+
+	for (i = 0 ; i < MAX_PNO_LIST_COUNT ; i++) {
+		RTW_INFO("%d SSID (%s) length (%d) cipher(%x) channel(%d)\n",
+			i, pwrctl->pno_ssid_list->node[i].SSID, pwrctl->pnlo_info->ssid_length[i],
+			pwrctl->pnlo_info->ssid_cipher_info[i], pwrctl->pnlo_info->ssid_channel_info[i]);
+	}
+
+	RTW_INFO("******SCAN_INFO******\n");
+	RTW_INFO("ch_num: %d\n", pwrctl->pscan_info->channel_num);
+	RTW_INFO("orig_ch: %d\n", pwrctl->pscan_info->orig_ch);
+	RTW_INFO("orig bw: %d\n", pwrctl->pscan_info->orig_bw);
+	RTW_INFO("orig 40 offset: %d\n", pwrctl->pscan_info->orig_40_offset);
+	for (i = 0 ; i < MAX_SCAN_LIST_COUNT ; i++) {
+		RTW_INFO("[%02d] avtive:%d, timeout:%d, tx_power:%d, ch:%02d\n",
+			 i, pwrctl->pscan_info->ssid_channel_info[i].active,
+			 pwrctl->pscan_info->ssid_channel_info[i].timeout,
+			 pwrctl->pscan_info->ssid_channel_info[i].tx_power,
+			 pwrctl->pscan_info->ssid_channel_info[i].channel);
+	}
+	RTW_INFO("*****************\n");
+}
+#endif /* CONFIG_PNO_SET_DEBUG */
+#endif /* CONFIG_PNO_SUPPORT */
+
+inline void rtw_collect_bcn_info(_adapter *adapter)
+{
+	struct mlme_ext_priv *pmlmeext = &adapter->mlmeextpriv;
+
+	if (!is_client_associated_to_ap(adapter))
+		return;
+
+	pmlmeext->cur_bcn_cnt = pmlmeext->bcn_cnt - pmlmeext->last_bcn_cnt;
+	pmlmeext->last_bcn_cnt = pmlmeext->bcn_cnt;
+	/*TODO get offset of bcn's timestamp*/
+	/*pmlmeext->bcn_timestamp;*/
+}
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/core/rtw_xmit.c linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/core/rtw_xmit.c
--- linux-5.6.3/3rdparty/rtl8821ce/core/rtw_xmit.c	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/core/rtw_xmit.c	2020-04-10 16:35:06.780658387 +0300
@@ -0,0 +1,5874 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#define _RTW_XMIT_C_
+
+#include <drv_types.h>
+#include <hal_data.h>
+
+#if defined(PLATFORM_LINUX) && defined (PLATFORM_WINDOWS)
+	#error "Shall be Linux or Windows, but not both!\n"
+#endif
+
+
+static u8 P802_1H_OUI[P80211_OUI_LEN] = { 0x00, 0x00, 0xf8 };
+static u8 RFC1042_OUI[P80211_OUI_LEN] = { 0x00, 0x00, 0x00 };
+
+static void _init_txservq(struct tx_servq *ptxservq)
+{
+	_rtw_init_listhead(&ptxservq->tx_pending);
+	_rtw_init_queue(&ptxservq->sta_pending);
+	ptxservq->qcnt = 0;
+}
+
+
+void	_rtw_init_sta_xmit_priv(struct sta_xmit_priv *psta_xmitpriv)
+{
+
+
+	_rtw_memset((unsigned char *)psta_xmitpriv, 0, sizeof(struct sta_xmit_priv));
+
+	_rtw_spinlock_init(&psta_xmitpriv->lock);
+
+	/* for(i = 0 ; i < MAX_NUMBLKS; i++) */
+	/*	_init_txservq(&(psta_xmitpriv->blk_q[i])); */
+
+	_init_txservq(&psta_xmitpriv->be_q);
+	_init_txservq(&psta_xmitpriv->bk_q);
+	_init_txservq(&psta_xmitpriv->vi_q);
+	_init_txservq(&psta_xmitpriv->vo_q);
+	_rtw_init_listhead(&psta_xmitpriv->legacy_dz);
+	_rtw_init_listhead(&psta_xmitpriv->apsd);
+
+
+}
+
+void rtw_init_xmit_block(_adapter *padapter)
+{
+	struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
+
+	_rtw_spinlock_init(&dvobj->xmit_block_lock);
+	dvobj->xmit_block = XMIT_BLOCK_NONE;
+
+}
+void rtw_free_xmit_block(_adapter *padapter)
+{
+	struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
+
+	_rtw_spinlock_free(&dvobj->xmit_block_lock);
+}
+
+s32	_rtw_init_xmit_priv(struct xmit_priv *pxmitpriv, _adapter *padapter)
+{
+	int i;
+	struct xmit_buf *pxmitbuf;
+	struct xmit_frame *pxframe;
+	sint	res = _SUCCESS;
+
+
+	/* We don't need to memset padapter->XXX to zero, because adapter is allocated by rtw_zvmalloc(). */
+	/* _rtw_memset((unsigned char *)pxmitpriv, 0, sizeof(struct xmit_priv)); */
+
+	_rtw_spinlock_init(&pxmitpriv->lock);
+	_rtw_spinlock_init(&pxmitpriv->lock_sctx);
+	_rtw_init_sema(&pxmitpriv->xmit_sema, 0);
+
+	/*
+	Please insert all the queue initializaiton using _rtw_init_queue below
+	*/
+
+	pxmitpriv->adapter = padapter;
+
+	/* for(i = 0 ; i < MAX_NUMBLKS; i++) */
+	/*	_rtw_init_queue(&pxmitpriv->blk_strms[i]); */
+
+	_rtw_init_queue(&pxmitpriv->be_pending);
+	_rtw_init_queue(&pxmitpriv->bk_pending);
+	_rtw_init_queue(&pxmitpriv->vi_pending);
+	_rtw_init_queue(&pxmitpriv->vo_pending);
+	_rtw_init_queue(&pxmitpriv->bm_pending);
+
+	/* _rtw_init_queue(&pxmitpriv->legacy_dz_queue); */
+	/* _rtw_init_queue(&pxmitpriv->apsd_queue); */
+
+	_rtw_init_queue(&pxmitpriv->free_xmit_queue);
+
+	/*
+	Please allocate memory with the sz = (struct xmit_frame) * NR_XMITFRAME,
+	and initialize free_xmit_frame below.
+	Please also apply  free_txobj to link_up all the xmit_frames...
+	*/
+
+	pxmitpriv->pallocated_frame_buf = rtw_zvmalloc(NR_XMITFRAME * sizeof(struct xmit_frame) + 4);
+
+	if (pxmitpriv->pallocated_frame_buf  == NULL) {
+		pxmitpriv->pxmit_frame_buf = NULL;
+		res = _FAIL;
+		goto exit;
+	}
+	pxmitpriv->pxmit_frame_buf = (u8 *)N_BYTE_ALIGMENT((SIZE_PTR)(pxmitpriv->pallocated_frame_buf), 4);
+	/* pxmitpriv->pxmit_frame_buf = pxmitpriv->pallocated_frame_buf + 4 - */
+	/*						((SIZE_PTR) (pxmitpriv->pallocated_frame_buf) &3); */
+
+	pxframe = (struct xmit_frame *) pxmitpriv->pxmit_frame_buf;
+
+	for (i = 0; i < NR_XMITFRAME; i++) {
+		_rtw_init_listhead(&(pxframe->list));
+
+		pxframe->padapter = padapter;
+		pxframe->frame_tag = NULL_FRAMETAG;
+
+		pxframe->pkt = NULL;
+
+		pxframe->buf_addr = NULL;
+		pxframe->pxmitbuf = NULL;
+
+		rtw_list_insert_tail(&(pxframe->list), &(pxmitpriv->free_xmit_queue.queue));
+
+		pxframe++;
+	}
+
+	pxmitpriv->free_xmitframe_cnt = NR_XMITFRAME;
+
+	pxmitpriv->frag_len = MAX_FRAG_THRESHOLD;
+
+
+	/* init xmit_buf */
+	_rtw_init_queue(&pxmitpriv->free_xmitbuf_queue);
+	_rtw_init_queue(&pxmitpriv->pending_xmitbuf_queue);
+
+	pxmitpriv->pallocated_xmitbuf = rtw_zvmalloc(NR_XMITBUFF * sizeof(struct xmit_buf) + 4);
+
+	if (pxmitpriv->pallocated_xmitbuf  == NULL) {
+		res = _FAIL;
+		goto exit;
+	}
+
+	pxmitpriv->pxmitbuf = (u8 *)N_BYTE_ALIGMENT((SIZE_PTR)(pxmitpriv->pallocated_xmitbuf), 4);
+	/* pxmitpriv->pxmitbuf = pxmitpriv->pallocated_xmitbuf + 4 - */
+	/*						((SIZE_PTR) (pxmitpriv->pallocated_xmitbuf) &3); */
+
+	pxmitbuf = (struct xmit_buf *)pxmitpriv->pxmitbuf;
+
+	for (i = 0; i < NR_XMITBUFF; i++) {
+		_rtw_init_listhead(&pxmitbuf->list);
+
+		pxmitbuf->priv_data = NULL;
+		pxmitbuf->padapter = padapter;
+		pxmitbuf->buf_tag = XMITBUF_DATA;
+
+		/* Tx buf allocation may fail sometimes, so sleep and retry. */
+		res = rtw_os_xmit_resource_alloc(padapter, pxmitbuf, (MAX_XMITBUF_SZ + XMITBUF_ALIGN_SZ), _TRUE);
+		if (res == _FAIL) {
+			rtw_msleep_os(10);
+			res = rtw_os_xmit_resource_alloc(padapter, pxmitbuf, (MAX_XMITBUF_SZ + XMITBUF_ALIGN_SZ), _TRUE);
+			if (res == _FAIL)
+				goto exit;
+		}
+
+#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
+		pxmitbuf->phead = pxmitbuf->pbuf;
+		pxmitbuf->pend = pxmitbuf->pbuf + MAX_XMITBUF_SZ;
+		pxmitbuf->len = 0;
+		pxmitbuf->pdata = pxmitbuf->ptail = pxmitbuf->phead;
+#endif
+
+		pxmitbuf->flags = XMIT_VO_QUEUE;
+
+		rtw_list_insert_tail(&pxmitbuf->list, &(pxmitpriv->free_xmitbuf_queue.queue));
+#ifdef DBG_XMIT_BUF
+		pxmitbuf->no = i;
+#endif
+
+		pxmitbuf++;
+
+	}
+
+	pxmitpriv->free_xmitbuf_cnt = NR_XMITBUFF;
+
+	/* init xframe_ext queue,  the same count as extbuf */
+	_rtw_init_queue(&pxmitpriv->free_xframe_ext_queue);
+
+	pxmitpriv->xframe_ext_alloc_addr = rtw_zvmalloc(NR_XMIT_EXTBUFF * sizeof(struct xmit_frame) + 4);
+
+	if (pxmitpriv->xframe_ext_alloc_addr  == NULL) {
+		pxmitpriv->xframe_ext = NULL;
+		res = _FAIL;
+		goto exit;
+	}
+	pxmitpriv->xframe_ext = (u8 *)N_BYTE_ALIGMENT((SIZE_PTR)(pxmitpriv->xframe_ext_alloc_addr), 4);
+	pxframe = (struct xmit_frame *)pxmitpriv->xframe_ext;
+
+	for (i = 0; i < NR_XMIT_EXTBUFF; i++) {
+		_rtw_init_listhead(&(pxframe->list));
+
+		pxframe->padapter = padapter;
+		pxframe->frame_tag = NULL_FRAMETAG;
+
+		pxframe->pkt = NULL;
+
+		pxframe->buf_addr = NULL;
+		pxframe->pxmitbuf = NULL;
+
+		pxframe->ext_tag = 1;
+
+		rtw_list_insert_tail(&(pxframe->list), &(pxmitpriv->free_xframe_ext_queue.queue));
+
+		pxframe++;
+	}
+	pxmitpriv->free_xframe_ext_cnt = NR_XMIT_EXTBUFF;
+
+	/* Init xmit extension buff */
+	_rtw_init_queue(&pxmitpriv->free_xmit_extbuf_queue);
+
+	pxmitpriv->pallocated_xmit_extbuf = rtw_zvmalloc(NR_XMIT_EXTBUFF * sizeof(struct xmit_buf) + 4);
+
+	if (pxmitpriv->pallocated_xmit_extbuf  == NULL) {
+		res = _FAIL;
+		goto exit;
+	}
+
+	pxmitpriv->pxmit_extbuf = (u8 *)N_BYTE_ALIGMENT((SIZE_PTR)(pxmitpriv->pallocated_xmit_extbuf), 4);
+
+	pxmitbuf = (struct xmit_buf *)pxmitpriv->pxmit_extbuf;
+
+	for (i = 0; i < NR_XMIT_EXTBUFF; i++) {
+		_rtw_init_listhead(&pxmitbuf->list);
+
+		pxmitbuf->priv_data = NULL;
+		pxmitbuf->padapter = padapter;
+		pxmitbuf->buf_tag = XMITBUF_MGNT;
+
+		res = rtw_os_xmit_resource_alloc(padapter, pxmitbuf, MAX_XMIT_EXTBUF_SZ + XMITBUF_ALIGN_SZ, _TRUE);
+		if (res == _FAIL) {
+			res = _FAIL;
+			goto exit;
+		}
+
+#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
+		pxmitbuf->phead = pxmitbuf->pbuf;
+		pxmitbuf->pend = pxmitbuf->pbuf + MAX_XMIT_EXTBUF_SZ;
+		pxmitbuf->len = 0;
+		pxmitbuf->pdata = pxmitbuf->ptail = pxmitbuf->phead;
+#endif
+
+		rtw_list_insert_tail(&pxmitbuf->list, &(pxmitpriv->free_xmit_extbuf_queue.queue));
+#ifdef DBG_XMIT_BUF_EXT
+		pxmitbuf->no = i;
+#endif
+		pxmitbuf++;
+
+	}
+
+	pxmitpriv->free_xmit_extbuf_cnt = NR_XMIT_EXTBUFF;
+
+	for (i = 0; i < CMDBUF_MAX; i++) {
+		pxmitbuf = &pxmitpriv->pcmd_xmitbuf[i];
+		if (pxmitbuf) {
+			_rtw_init_listhead(&pxmitbuf->list);
+
+			pxmitbuf->priv_data = NULL;
+			pxmitbuf->padapter = padapter;
+			pxmitbuf->buf_tag = XMITBUF_CMD;
+
+			res = rtw_os_xmit_resource_alloc(padapter, pxmitbuf, MAX_CMDBUF_SZ + XMITBUF_ALIGN_SZ, _TRUE);
+			if (res == _FAIL) {
+				res = _FAIL;
+				goto exit;
+			}
+
+#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
+			pxmitbuf->phead = pxmitbuf->pbuf;
+			pxmitbuf->pend = pxmitbuf->pbuf + MAX_CMDBUF_SZ;
+			pxmitbuf->len = 0;
+			pxmitbuf->pdata = pxmitbuf->ptail = pxmitbuf->phead;
+#endif
+			pxmitbuf->alloc_sz = MAX_CMDBUF_SZ + XMITBUF_ALIGN_SZ;
+		}
+	}
+
+	rtw_alloc_hwxmits(padapter);
+	rtw_init_hwxmits(pxmitpriv->hwxmits, pxmitpriv->hwxmit_entry);
+
+	for (i = 0; i < 4; i++)
+		pxmitpriv->wmm_para_seq[i] = i;
+
+#ifdef CONFIG_USB_HCI
+	pxmitpriv->txirp_cnt = 1;
+
+	_rtw_init_sema(&(pxmitpriv->tx_retevt), 0);
+
+	/* per AC pending irp */
+	pxmitpriv->beq_cnt = 0;
+	pxmitpriv->bkq_cnt = 0;
+	pxmitpriv->viq_cnt = 0;
+	pxmitpriv->voq_cnt = 0;
+#endif
+
+
+#ifdef CONFIG_XMIT_ACK
+	pxmitpriv->ack_tx = _FALSE;
+	_rtw_mutex_init(&pxmitpriv->ack_tx_mutex);
+	rtw_sctx_init(&pxmitpriv->ack_tx_ops, 0);
+#endif
+
+#ifdef CONFIG_TX_AMSDU
+	rtw_init_timer(&(pxmitpriv->amsdu_vo_timer), padapter,
+		rtw_amsdu_vo_timeout_handler, padapter);
+	pxmitpriv->amsdu_vo_timeout = RTW_AMSDU_TIMER_UNSET;
+
+	rtw_init_timer(&(pxmitpriv->amsdu_vi_timer), padapter,
+		rtw_amsdu_vi_timeout_handler, padapter);
+	pxmitpriv->amsdu_vi_timeout = RTW_AMSDU_TIMER_UNSET;
+
+	rtw_init_timer(&(pxmitpriv->amsdu_be_timer), padapter,
+		rtw_amsdu_be_timeout_handler, padapter);
+	pxmitpriv->amsdu_be_timeout = RTW_AMSDU_TIMER_UNSET;
+
+	rtw_init_timer(&(pxmitpriv->amsdu_bk_timer), padapter,
+		rtw_amsdu_bk_timeout_handler, padapter);
+	pxmitpriv->amsdu_bk_timeout = RTW_AMSDU_TIMER_UNSET;
+
+	pxmitpriv->amsdu_debug_set_timer = 0;
+	pxmitpriv->amsdu_debug_timeout = 0;
+	pxmitpriv->amsdu_debug_coalesce_one = 0;
+	pxmitpriv->amsdu_debug_coalesce_two = 0;
+#endif
+#ifdef DBG_TXBD_DESC_DUMP
+	pxmitpriv->dump_txbd_desc = 0;
+#endif
+	rtw_init_xmit_block(padapter);
+	rtw_hal_init_xmit_priv(padapter);
+
+exit:
+
+
+	return res;
+}
+
+void  rtw_mfree_xmit_priv_lock(struct xmit_priv *pxmitpriv);
+void  rtw_mfree_xmit_priv_lock(struct xmit_priv *pxmitpriv)
+{
+	_rtw_spinlock_free(&pxmitpriv->lock);
+	_rtw_free_sema(&pxmitpriv->xmit_sema);
+
+	_rtw_spinlock_free(&pxmitpriv->be_pending.lock);
+	_rtw_spinlock_free(&pxmitpriv->bk_pending.lock);
+	_rtw_spinlock_free(&pxmitpriv->vi_pending.lock);
+	_rtw_spinlock_free(&pxmitpriv->vo_pending.lock);
+	_rtw_spinlock_free(&pxmitpriv->bm_pending.lock);
+
+	/* _rtw_spinlock_free(&pxmitpriv->legacy_dz_queue.lock); */
+	/* _rtw_spinlock_free(&pxmitpriv->apsd_queue.lock); */
+
+	_rtw_spinlock_free(&pxmitpriv->free_xmit_queue.lock);
+	_rtw_spinlock_free(&pxmitpriv->free_xmitbuf_queue.lock);
+	_rtw_spinlock_free(&pxmitpriv->pending_xmitbuf_queue.lock);
+}
+
+
+void _rtw_free_xmit_priv(struct xmit_priv *pxmitpriv)
+{
+	int i;
+	_adapter *padapter = pxmitpriv->adapter;
+	struct xmit_frame	*pxmitframe = (struct xmit_frame *) pxmitpriv->pxmit_frame_buf;
+	struct xmit_buf *pxmitbuf = (struct xmit_buf *)pxmitpriv->pxmitbuf;
+
+
+	rtw_hal_free_xmit_priv(padapter);
+
+	rtw_mfree_xmit_priv_lock(pxmitpriv);
+
+	if (pxmitpriv->pxmit_frame_buf == NULL)
+		goto out;
+
+	for (i = 0; i < NR_XMITFRAME; i++) {
+		rtw_os_xmit_complete(padapter, pxmitframe);
+
+		pxmitframe++;
+	}
+
+	for (i = 0; i < NR_XMITBUFF; i++) {
+		rtw_os_xmit_resource_free(padapter, pxmitbuf, (MAX_XMITBUF_SZ + XMITBUF_ALIGN_SZ), _TRUE);
+
+		pxmitbuf++;
+	}
+
+	if (pxmitpriv->pallocated_frame_buf)
+		rtw_vmfree(pxmitpriv->pallocated_frame_buf, NR_XMITFRAME * sizeof(struct xmit_frame) + 4);
+
+
+	if (pxmitpriv->pallocated_xmitbuf)
+		rtw_vmfree(pxmitpriv->pallocated_xmitbuf, NR_XMITBUFF * sizeof(struct xmit_buf) + 4);
+
+	/* free xframe_ext queue,  the same count as extbuf */
+	if ((pxmitframe = (struct xmit_frame *)pxmitpriv->xframe_ext)) {
+		for (i = 0; i < NR_XMIT_EXTBUFF; i++) {
+			rtw_os_xmit_complete(padapter, pxmitframe);
+			pxmitframe++;
+		}
+	}
+	if (pxmitpriv->xframe_ext_alloc_addr)
+		rtw_vmfree(pxmitpriv->xframe_ext_alloc_addr, NR_XMIT_EXTBUFF * sizeof(struct xmit_frame) + 4);
+	_rtw_spinlock_free(&pxmitpriv->free_xframe_ext_queue.lock);
+
+	/* free xmit extension buff */
+	_rtw_spinlock_free(&pxmitpriv->free_xmit_extbuf_queue.lock);
+
+	pxmitbuf = (struct xmit_buf *)pxmitpriv->pxmit_extbuf;
+	for (i = 0; i < NR_XMIT_EXTBUFF; i++) {
+		rtw_os_xmit_resource_free(padapter, pxmitbuf, (MAX_XMIT_EXTBUF_SZ + XMITBUF_ALIGN_SZ), _TRUE);
+
+		pxmitbuf++;
+	}
+
+	if (pxmitpriv->pallocated_xmit_extbuf)
+		rtw_vmfree(pxmitpriv->pallocated_xmit_extbuf, NR_XMIT_EXTBUFF * sizeof(struct xmit_buf) + 4);
+
+	for (i = 0; i < CMDBUF_MAX; i++) {
+		pxmitbuf = &pxmitpriv->pcmd_xmitbuf[i];
+		if (pxmitbuf != NULL)
+			rtw_os_xmit_resource_free(padapter, pxmitbuf, MAX_CMDBUF_SZ + XMITBUF_ALIGN_SZ , _TRUE);
+	}
+
+	rtw_free_hwxmits(padapter);
+
+#ifdef CONFIG_XMIT_ACK
+	_rtw_mutex_free(&pxmitpriv->ack_tx_mutex);
+#endif
+	rtw_free_xmit_block(padapter);
+out:
+	return;
+}
+
+u8 rtw_get_tx_bw_mode(_adapter *adapter, struct sta_info *sta)
+{
+	u8 bw;
+
+	bw = sta->cmn.bw_mode;
+	if (MLME_STATE(adapter) & WIFI_ASOC_STATE) {
+		if (adapter->mlmeextpriv.cur_channel <= 14)
+			bw = rtw_min(bw, ADAPTER_TX_BW_2G(adapter));
+		else
+			bw = rtw_min(bw, ADAPTER_TX_BW_5G(adapter));
+	}
+
+	return bw;
+}
+
+void rtw_get_adapter_tx_rate_bmp_by_bw(_adapter *adapter, u8 bw, u16 *r_bmp_cck_ofdm, u32 *r_bmp_ht, u32 *r_bmp_vht)
+{
+	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
+	struct macid_ctl_t *macid_ctl = dvobj_to_macidctl(dvobj);
+	u8 fix_bw = 0xFF;
+	u16 bmp_cck_ofdm = 0;
+	u32 bmp_ht = 0;
+	u32 bmp_vht = 0;
+	int i;
+
+	if (adapter->fix_rate != 0xFF && adapter->fix_bw != 0xFF)
+		fix_bw = adapter->fix_bw;
+
+	/* TODO: adapter->fix_rate */
+
+	for (i = 0; i < macid_ctl->num; i++) {
+		if (!rtw_macid_is_used(macid_ctl, i))
+			continue;
+		if (!rtw_macid_is_iface_specific(macid_ctl, i, adapter))
+			continue;
+
+		if (bw == CHANNEL_WIDTH_20) /* CCK, OFDM always 20MHz */
+			bmp_cck_ofdm |= macid_ctl->rate_bmp0[i] & 0x00000FFF;
+
+		/* bypass mismatch bandwidth for HT, VHT */
+		if ((fix_bw != 0xFF && fix_bw != bw) || (fix_bw == 0xFF && macid_ctl->bw[i] != bw))
+			continue;
+
+		if (macid_ctl->vht_en[i])
+			bmp_vht |= (macid_ctl->rate_bmp0[i] >> 12) | (macid_ctl->rate_bmp1[i] << 20);
+		else
+			bmp_ht |= (macid_ctl->rate_bmp0[i] >> 12) | (macid_ctl->rate_bmp1[i] << 20);
+	}
+
+	/* TODO: mlmeext->tx_rate*/
+
+	if (r_bmp_cck_ofdm)
+		*r_bmp_cck_ofdm = bmp_cck_ofdm;
+	if (r_bmp_ht)
+		*r_bmp_ht = bmp_ht;
+	if (r_bmp_vht)
+		*r_bmp_vht = bmp_vht;
+}
+
+void rtw_get_shared_macid_tx_rate_bmp_by_bw(struct dvobj_priv *dvobj, u8 bw, u16 *r_bmp_cck_ofdm, u32 *r_bmp_ht, u32 *r_bmp_vht)
+{
+	struct macid_ctl_t *macid_ctl = dvobj_to_macidctl(dvobj);
+	u16 bmp_cck_ofdm = 0;
+	u32 bmp_ht = 0;
+	u32 bmp_vht = 0;
+	int i;
+
+	for (i = 0; i < macid_ctl->num; i++) {
+		if (!rtw_macid_is_used(macid_ctl, i))
+			continue;
+		if (!rtw_macid_is_iface_shared(macid_ctl, i))
+			continue;
+
+		if (bw == CHANNEL_WIDTH_20) /* CCK, OFDM always 20MHz */
+			bmp_cck_ofdm |= macid_ctl->rate_bmp0[i] & 0x00000FFF;
+
+		/* bypass mismatch bandwidth for HT, VHT */
+		if (macid_ctl->bw[i] != bw)
+			continue;
+
+		if (macid_ctl->vht_en[i])
+			bmp_vht |= (macid_ctl->rate_bmp0[i] >> 12) | (macid_ctl->rate_bmp1[i] << 20);
+		else
+			bmp_ht |= (macid_ctl->rate_bmp0[i] >> 12) | (macid_ctl->rate_bmp1[i] << 20);
+	}
+
+	if (r_bmp_cck_ofdm)
+		*r_bmp_cck_ofdm = bmp_cck_ofdm;
+	if (r_bmp_ht)
+		*r_bmp_ht = bmp_ht;
+	if (r_bmp_vht)
+		*r_bmp_vht = bmp_vht;
+}
+
+void rtw_update_tx_rate_bmp(struct dvobj_priv *dvobj)
+{
+	struct rf_ctl_t *rf_ctl = dvobj_to_rfctl(dvobj);
+	_adapter *adapter = dvobj_get_primary_adapter(dvobj);
+	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
+	u8 bw;
+	u16 bmp_cck_ofdm, tmp_cck_ofdm;
+	u32 bmp_ht, tmp_ht, ori_bmp_ht[2];
+	u8 ori_highest_ht_rate_bw_bmp;
+	u32 bmp_vht, tmp_vht, ori_bmp_vht[4];
+	u8 ori_highest_vht_rate_bw_bmp;
+	int i;
+
+	/* backup the original ht & vht highest bw bmp */
+	ori_highest_ht_rate_bw_bmp = rf_ctl->highest_ht_rate_bw_bmp;
+	ori_highest_vht_rate_bw_bmp = rf_ctl->highest_vht_rate_bw_bmp;
+
+	for (bw = CHANNEL_WIDTH_20; bw <= CHANNEL_WIDTH_160; bw++) {
+		/* backup the original ht & vht bmp */
+		if (bw <= CHANNEL_WIDTH_40)
+			ori_bmp_ht[bw] = rf_ctl->rate_bmp_ht_by_bw[bw];
+		if (bw <= CHANNEL_WIDTH_160)
+			ori_bmp_vht[bw] = rf_ctl->rate_bmp_vht_by_bw[bw];
+
+		bmp_cck_ofdm = bmp_ht = bmp_vht = 0;
+		if (hal_is_bw_support(dvobj_get_primary_adapter(dvobj), bw)) {
+			for (i = 0; i < dvobj->iface_nums; i++) {
+				if (!dvobj->padapters[i])
+					continue;
+				rtw_get_adapter_tx_rate_bmp_by_bw(dvobj->padapters[i], bw, &tmp_cck_ofdm, &tmp_ht, &tmp_vht);
+				bmp_cck_ofdm |= tmp_cck_ofdm;
+				bmp_ht |= tmp_ht;
+				bmp_vht |= tmp_vht;
+			}
+			rtw_get_shared_macid_tx_rate_bmp_by_bw(dvobj, bw, &tmp_cck_ofdm, &tmp_ht, &tmp_vht);
+			bmp_cck_ofdm |= tmp_cck_ofdm;
+			bmp_ht |= tmp_ht;
+			bmp_vht |= tmp_vht;
+		}
+		if (bw == CHANNEL_WIDTH_20)
+			rf_ctl->rate_bmp_cck_ofdm = bmp_cck_ofdm;
+		if (bw <= CHANNEL_WIDTH_40)
+			rf_ctl->rate_bmp_ht_by_bw[bw] = bmp_ht;
+		if (bw <= CHANNEL_WIDTH_160)
+			rf_ctl->rate_bmp_vht_by_bw[bw] = bmp_vht;
+	}
+
+#ifndef DBG_HIGHEST_RATE_BMP_BW_CHANGE
+#define DBG_HIGHEST_RATE_BMP_BW_CHANGE 0
+#endif
+
+	{
+		u8 highest_rate_bw;
+		u8 highest_rate_bw_bmp;
+		u8 update_ht_rs = _FALSE;
+		u8 update_vht_rs = _FALSE;
+
+		highest_rate_bw_bmp = BW_CAP_20M;
+		highest_rate_bw = CHANNEL_WIDTH_20;
+		for (bw = CHANNEL_WIDTH_20; bw <= CHANNEL_WIDTH_40; bw++) {
+			if (rf_ctl->rate_bmp_ht_by_bw[highest_rate_bw] < rf_ctl->rate_bmp_ht_by_bw[bw]) {
+				highest_rate_bw_bmp = ch_width_to_bw_cap(bw);
+				highest_rate_bw = bw;
+			} else if (rf_ctl->rate_bmp_ht_by_bw[highest_rate_bw] == rf_ctl->rate_bmp_ht_by_bw[bw])
+				highest_rate_bw_bmp |= ch_width_to_bw_cap(bw);
+		}
+		rf_ctl->highest_ht_rate_bw_bmp = highest_rate_bw_bmp;
+
+		if (ori_highest_ht_rate_bw_bmp != rf_ctl->highest_ht_rate_bw_bmp
+			|| largest_bit(ori_bmp_ht[highest_rate_bw]) != largest_bit(rf_ctl->rate_bmp_ht_by_bw[highest_rate_bw])
+		) {
+			if (DBG_HIGHEST_RATE_BMP_BW_CHANGE) {
+				RTW_INFO("highest_ht_rate_bw_bmp:0x%02x=>0x%02x\n", ori_highest_ht_rate_bw_bmp, rf_ctl->highest_ht_rate_bw_bmp);
+				RTW_INFO("rate_bmp_ht_by_bw[%u]:0x%08x=>0x%08x\n", highest_rate_bw, ori_bmp_ht[highest_rate_bw], rf_ctl->rate_bmp_ht_by_bw[highest_rate_bw]);
+			}
+			update_ht_rs = _TRUE;
+		}
+
+		highest_rate_bw_bmp = BW_CAP_20M;
+		highest_rate_bw = CHANNEL_WIDTH_20;
+		for (bw = CHANNEL_WIDTH_20; bw <= CHANNEL_WIDTH_160; bw++) {
+			if (rf_ctl->rate_bmp_vht_by_bw[highest_rate_bw] < rf_ctl->rate_bmp_vht_by_bw[bw]) {
+				highest_rate_bw_bmp = ch_width_to_bw_cap(bw);
+				highest_rate_bw = bw;
+			} else if (rf_ctl->rate_bmp_vht_by_bw[highest_rate_bw] == rf_ctl->rate_bmp_vht_by_bw[bw])
+				highest_rate_bw_bmp |= ch_width_to_bw_cap(bw);
+		}
+		rf_ctl->highest_vht_rate_bw_bmp = highest_rate_bw_bmp;
+
+		if (ori_highest_vht_rate_bw_bmp != rf_ctl->highest_vht_rate_bw_bmp
+			|| largest_bit(ori_bmp_vht[highest_rate_bw]) != largest_bit(rf_ctl->rate_bmp_vht_by_bw[highest_rate_bw])
+		) {
+			if (DBG_HIGHEST_RATE_BMP_BW_CHANGE) {
+				RTW_INFO("highest_vht_rate_bw_bmp:0x%02x=>0x%02x\n", ori_highest_vht_rate_bw_bmp, rf_ctl->highest_vht_rate_bw_bmp);
+				RTW_INFO("rate_bmp_vht_by_bw[%u]:0x%08x=>0x%08x\n", highest_rate_bw, ori_bmp_vht[highest_rate_bw], rf_ctl->rate_bmp_vht_by_bw[highest_rate_bw]);
+			}
+			update_vht_rs = _TRUE;
+		}
+
+		/* TODO: per rfpath and rate section handling? */
+		if (update_ht_rs == _TRUE || update_vht_rs == _TRUE)
+			rtw_hal_set_tx_power_level(dvobj_get_primary_adapter(dvobj), hal_data->current_channel);
+	}
+}
+
+inline u16 rtw_get_tx_rate_bmp_cck_ofdm(struct dvobj_priv *dvobj)
+{
+	struct rf_ctl_t *rf_ctl = dvobj_to_rfctl(dvobj);
+
+	return rf_ctl->rate_bmp_cck_ofdm;
+}
+
+inline u32 rtw_get_tx_rate_bmp_ht_by_bw(struct dvobj_priv *dvobj, u8 bw)
+{
+	struct rf_ctl_t *rf_ctl = dvobj_to_rfctl(dvobj);
+
+	return rf_ctl->rate_bmp_ht_by_bw[bw];
+}
+
+inline u32 rtw_get_tx_rate_bmp_vht_by_bw(struct dvobj_priv *dvobj, u8 bw)
+{
+	struct rf_ctl_t *rf_ctl = dvobj_to_rfctl(dvobj);
+
+	return rf_ctl->rate_bmp_vht_by_bw[bw];
+}
+
+u8 rtw_get_tx_bw_bmp_of_ht_rate(struct dvobj_priv *dvobj, u8 rate, u8 max_bw)
+{
+	struct rf_ctl_t *rf_ctl = dvobj_to_rfctl(dvobj);
+	u8 bw;
+	u8 bw_bmp = 0;
+	u32 rate_bmp;
+
+	if (!IS_HT_RATE(rate)) {
+		rtw_warn_on(1);
+		goto exit;
+	}
+
+	rate_bmp = 1 << (rate - MGN_MCS0);
+
+	if (max_bw > CHANNEL_WIDTH_40)
+		max_bw = CHANNEL_WIDTH_40;
+
+	for (bw = CHANNEL_WIDTH_20; bw <= max_bw; bw++) {
+		/* RA may use lower rate for retry */
+		if (rf_ctl->rate_bmp_ht_by_bw[bw] >= rate_bmp)
+			bw_bmp |= ch_width_to_bw_cap(bw);
+	}
+
+exit:
+	return bw_bmp;
+}
+
+u8 rtw_get_tx_bw_bmp_of_vht_rate(struct dvobj_priv *dvobj, u8 rate, u8 max_bw)
+{
+	struct rf_ctl_t *rf_ctl = dvobj_to_rfctl(dvobj);
+	u8 bw;
+	u8 bw_bmp = 0;
+	u32 rate_bmp;
+
+	if (!IS_VHT_RATE(rate)) {
+		rtw_warn_on(1);
+		goto exit;
+	}
+
+	rate_bmp = 1 << (rate - MGN_VHT1SS_MCS0);
+
+	if (max_bw > CHANNEL_WIDTH_160)
+		max_bw = CHANNEL_WIDTH_160;
+
+	for (bw = CHANNEL_WIDTH_20; bw <= max_bw; bw++) {
+		/* RA may use lower rate for retry */
+		if (rf_ctl->rate_bmp_vht_by_bw[bw] >= rate_bmp)
+			bw_bmp |= ch_width_to_bw_cap(bw);
+	}
+
+exit:
+	return bw_bmp;
+}
+
+u8 query_ra_short_GI(struct sta_info *psta, u8 bw)
+{
+	u8	sgi = _FALSE, sgi_20m = _FALSE, sgi_40m = _FALSE, sgi_80m = _FALSE;
+
+#ifdef CONFIG_80211N_HT
+#ifdef CONFIG_80211AC_VHT
+	if (psta->vhtpriv.vht_option)
+		sgi_80m = psta->vhtpriv.sgi_80m;
+#endif
+	sgi_20m = psta->htpriv.sgi_20m;
+	sgi_40m = psta->htpriv.sgi_40m;
+#endif
+
+	switch (bw) {
+	case CHANNEL_WIDTH_80:
+		sgi = sgi_80m;
+		break;
+	case CHANNEL_WIDTH_40:
+		sgi = sgi_40m;
+		break;
+	case CHANNEL_WIDTH_20:
+	default:
+		sgi = sgi_20m;
+		break;
+	}
+
+	return sgi;
+}
+
+static void update_attrib_vcs_info(_adapter *padapter, struct xmit_frame *pxmitframe)
+{
+	u32	sz;
+	struct pkt_attrib	*pattrib = &pxmitframe->attrib;
+	/* struct sta_info	*psta = pattrib->psta; */
+	struct mlme_ext_priv	*pmlmeext = &(padapter->mlmeextpriv);
+	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
+
+	/*
+		if(pattrib->psta)
+		{
+			psta = pattrib->psta;
+		}
+		else
+		{
+			RTW_INFO("%s, call rtw_get_stainfo()\n", __func__);
+			psta=rtw_get_stainfo(&padapter->stapriv ,&pattrib->ra[0] );
+		}
+
+		if(psta==NULL)
+		{
+			RTW_INFO("%s, psta==NUL\n", __func__);
+			return;
+		}
+
+		if(!(psta->state &_FW_LINKED))
+		{
+			RTW_INFO("%s, psta->state(0x%x) != _FW_LINKED\n", __func__, psta->state);
+			return;
+		}
+	*/
+
+	if (pattrib->nr_frags != 1)
+		sz = padapter->xmitpriv.frag_len;
+	else /* no frag */
+		sz = pattrib->last_txcmdsz;
+
+	/* (1) RTS_Threshold is compared to the MPDU, not MSDU. */
+	/* (2) If there are more than one frag in  this MSDU, only the first frag uses protection frame. */
+	/*		Other fragments are protected by previous fragment. */
+	/*		So we only need to check the length of first fragment. */
+	if (pmlmeext->cur_wireless_mode < WIRELESS_11_24N  || padapter->registrypriv.wifi_spec) {
+		if (sz > padapter->registrypriv.rts_thresh)
+			pattrib->vcs_mode = RTS_CTS;
+		else {
+			if (pattrib->rtsen)
+				pattrib->vcs_mode = RTS_CTS;
+			else if (pattrib->cts2self)
+				pattrib->vcs_mode = CTS_TO_SELF;
+			else
+				pattrib->vcs_mode = NONE_VCS;
+		}
+	} else {
+		while (_TRUE) {
+#if 0 /* Todo */
+			/* check IOT action */
+			if (pHTInfo->IOTAction & HT_IOT_ACT_FORCED_CTS2SELF) {
+				pattrib->vcs_mode = CTS_TO_SELF;
+				pattrib->rts_rate = MGN_24M;
+				break;
+			} else if (pHTInfo->IOTAction & (HT_IOT_ACT_FORCED_RTS | HT_IOT_ACT_PURE_N_MODE)) {
+				pattrib->vcs_mode = RTS_CTS;
+				pattrib->rts_rate = MGN_24M;
+				break;
+			}
+#endif
+
+			/* IOT action */
+			if ((pmlmeinfo->assoc_AP_vendor == HT_IOT_PEER_ATHEROS) && (pattrib->ampdu_en == _TRUE) &&
+			    (padapter->securitypriv.dot11PrivacyAlgrthm == _AES_)) {
+				pattrib->vcs_mode = CTS_TO_SELF;
+				break;
+			}
+
+
+			/* check ERP protection */
+			if (pattrib->rtsen || pattrib->cts2self) {
+				if (pattrib->rtsen)
+					pattrib->vcs_mode = RTS_CTS;
+				else if (pattrib->cts2self)
+					pattrib->vcs_mode = CTS_TO_SELF;
+
+				break;
+			}
+
+			/* check HT op mode */
+			if (pattrib->ht_en) {
+				u8 HTOpMode = pmlmeinfo->HT_protection;
+				if ((pmlmeext->cur_bwmode && (HTOpMode == 2 || HTOpMode == 3)) ||
+				    (!pmlmeext->cur_bwmode && HTOpMode == 3)) {
+					pattrib->vcs_mode = RTS_CTS;
+					break;
+				}
+			}
+
+			/* check rts */
+			if (sz > padapter->registrypriv.rts_thresh) {
+				pattrib->vcs_mode = RTS_CTS;
+				break;
+			}
+
+			/* to do list: check MIMO power save condition. */
+
+			/* check AMPDU aggregation for TXOP */
+			if ((pattrib->ampdu_en == _TRUE) && (!IS_HARDWARE_TYPE_8812(padapter))) {
+				pattrib->vcs_mode = RTS_CTS;
+				break;
+			}
+
+			pattrib->vcs_mode = NONE_VCS;
+			break;
+		}
+	}
+
+	/* for debug : force driver control vrtl_carrier_sense. */
+	if (padapter->driver_vcs_en == 1) {
+		/* u8 driver_vcs_en; */ /* Enable=1, Disable=0 driver control vrtl_carrier_sense. */
+		/* u8 driver_vcs_type; */ /* force 0:disable VCS, 1:RTS-CTS, 2:CTS-to-self when vcs_en=1. */
+		pattrib->vcs_mode = padapter->driver_vcs_type;
+	}
+
+}
+
+#ifdef CONFIG_WMMPS_STA
+/*
+ * update_attrib_trigger_frame_info
+ * For Station mode, if a specific TID of driver setting and an AP support uapsd function, the data 
+ * frame with corresponding TID will be a trigger frame when driver is in wmm power saving mode.
+ * 
+ * Arguments:
+ * @padapter: _adapter pointer.
+ * @pattrib: pkt_attrib pointer.
+ *
+ * Auther: Arvin Liu
+ * Date: 2017/06/05
+ */
+static void update_attrib_trigger_frame_info(_adapter *padapter, struct pkt_attrib *pattrib) {
+	struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
+	struct pwrctrl_priv 	*pwrpriv = adapter_to_pwrctl(padapter); 
+	struct qos_priv 	*pqospriv = &pmlmepriv->qospriv;
+	u8 trigger_frame_en = 0;
+
+	if (check_fwstate(pmlmepriv, WIFI_STATION_STATE) == _TRUE) {
+		if ((pwrpriv->pwr_mode == PS_MODE_MIN) || (pwrpriv->pwr_mode == PS_MODE_MAX)) {
+			if((pqospriv->uapsd_ap_supported) && ((pqospriv->uapsd_tid & BIT(pattrib->priority)) == _TRUE)) {
+				trigger_frame_en = 1;
+				RTW_INFO("[WMMPS]"FUNC_ADPT_FMT": This is a Trigger Frame\n", FUNC_ADPT_ARG(padapter));
+			}
+		}
+	}
+
+	pattrib->trigger_frame = trigger_frame_en;
+}
+#endif /* CONFIG_WMMPS_STA */
+
+static void update_attrib_phy_info(_adapter *padapter, struct pkt_attrib *pattrib, struct sta_info *psta)
+{
+	struct mlme_ext_priv *mlmeext = &padapter->mlmeextpriv;
+	u8 bw;
+
+	pattrib->rtsen = psta->rtsen;
+	pattrib->cts2self = psta->cts2self;
+
+	pattrib->mdata = 0;
+	pattrib->eosp = 0;
+	pattrib->triggered = 0;
+	pattrib->ampdu_spacing = 0;
+
+	/* ht_en, init rate, ,bw, ch_offset, sgi */
+
+	pattrib->raid = psta->cmn.ra_info.rate_id;
+
+	bw = rtw_get_tx_bw_mode(padapter, psta);
+	pattrib->bwmode = rtw_min(bw, mlmeext->cur_bwmode);
+	pattrib->sgi = query_ra_short_GI(psta, pattrib->bwmode);
+
+	pattrib->ldpc = psta->cmn.ldpc_en;
+	pattrib->stbc = psta->cmn.stbc_en;
+
+#ifdef CONFIG_80211N_HT
+	if(padapter->registrypriv.ht_enable &&
+		is_supported_ht(padapter->registrypriv.wireless_mode)) {
+		pattrib->ht_en = psta->htpriv.ht_option;
+		pattrib->ch_offset = psta->htpriv.ch_offset;
+		pattrib->ampdu_en = _FALSE;
+
+		if (padapter->driver_ampdu_spacing != 0xFF) /* driver control AMPDU Density for peer sta's rx */
+			pattrib->ampdu_spacing = padapter->driver_ampdu_spacing;
+		else
+			pattrib->ampdu_spacing = psta->htpriv.rx_ampdu_min_spacing;
+
+		/* check if enable ampdu */
+		if (pattrib->ht_en && psta->htpriv.ampdu_enable) {
+			if (psta->htpriv.agg_enable_bitmap & BIT(pattrib->priority)) {
+				pattrib->ampdu_en = _TRUE;
+				if (psta->htpriv.tx_amsdu_enable == _TRUE)
+					pattrib->amsdu_ampdu_en = _TRUE;
+				else
+					pattrib->amsdu_ampdu_en = _FALSE;
+			}
+		}
+	}
+#endif /* CONFIG_80211N_HT */
+	/* if(pattrib->ht_en && psta->htpriv.ampdu_enable) */
+	/* { */
+	/*	if(psta->htpriv.agg_enable_bitmap & BIT(pattrib->priority)) */
+	/*		pattrib->ampdu_en = _TRUE; */
+	/* }	 */
+
+#ifdef CONFIG_TDLS
+	if (pattrib->direct_link == _TRUE) {
+		psta = pattrib->ptdls_sta;
+
+		pattrib->raid = psta->cmn.ra_info.rate_id;
+#ifdef CONFIG_80211N_HT
+	if(padapter->registrypriv.ht_enable &&
+		is_supported_ht(padapter->registrypriv.wireless_mode)) {
+			pattrib->bwmode = rtw_get_tx_bw_mode(padapter, psta);
+			pattrib->ht_en = psta->htpriv.ht_option;
+			pattrib->ch_offset = psta->htpriv.ch_offset;
+			pattrib->sgi = query_ra_short_GI(psta, pattrib->bwmode);
+	}
+#endif /* CONFIG_80211N_HT */
+	}
+#endif /* CONFIG_TDLS */
+
+	pattrib->retry_ctrl = _FALSE;
+
+#ifdef CONFIG_AUTO_AP_MODE
+	if (psta->isrc && psta->pid > 0)
+		pattrib->pctrl = _TRUE;
+#endif
+
+}
+
+static s32 update_attrib_sec_info(_adapter *padapter, struct pkt_attrib *pattrib, struct sta_info *psta)
+{
+	sint res = _SUCCESS;
+	struct mlme_priv	*pmlmepriv = &padapter->mlmepriv;
+	struct security_priv *psecuritypriv = &padapter->securitypriv;
+	sint bmcast = IS_MCAST(pattrib->ra);
+
+	_rtw_memset(pattrib->dot118021x_UncstKey.skey,  0, 16);
+	_rtw_memset(pattrib->dot11tkiptxmickey.skey,  0, 16);
+	pattrib->mac_id = psta->cmn.mac_id;
+
+	if (psta->ieee8021x_blocked == _TRUE) {
+
+		pattrib->encrypt = 0;
+
+		if ((pattrib->ether_type != 0x888e) && (check_fwstate(pmlmepriv, WIFI_MP_STATE) == _FALSE)) {
+#ifdef DBG_TX_DROP_FRAME
+			RTW_INFO("DBG_TX_DROP_FRAME %s psta->ieee8021x_blocked == _TRUE,  pattrib->ether_type(%04x) != 0x888e\n", __FUNCTION__, pattrib->ether_type);
+#endif
+			res = _FAIL;
+			goto exit;
+		}
+	} else {
+		GET_ENCRY_ALGO(psecuritypriv, psta, pattrib->encrypt, bmcast);
+
+#ifdef CONFIG_WAPI_SUPPORT
+		if (pattrib->ether_type == 0x88B4)
+			pattrib->encrypt = _NO_PRIVACY_;
+#endif
+
+		switch (psecuritypriv->dot11AuthAlgrthm) {
+		case dot11AuthAlgrthm_Open:
+		case dot11AuthAlgrthm_Shared:
+		case dot11AuthAlgrthm_Auto:
+			pattrib->key_idx = (u8)psecuritypriv->dot11PrivacyKeyIndex;
+			break;
+		case dot11AuthAlgrthm_8021X:
+			if (bmcast)
+				pattrib->key_idx = (u8)psecuritypriv->dot118021XGrpKeyid;
+			else
+				pattrib->key_idx = 0;
+			break;
+		default:
+			pattrib->key_idx = 0;
+			break;
+		}
+
+		/* For WPS 1.0 WEP, driver should not encrypt EAPOL Packet for WPS handshake. */
+		if (((pattrib->encrypt == _WEP40_) || (pattrib->encrypt == _WEP104_)) && (pattrib->ether_type == 0x888e))
+			pattrib->encrypt = _NO_PRIVACY_;
+
+	}
+
+#ifdef CONFIG_TDLS
+	if (pattrib->direct_link == _TRUE) {
+		if (pattrib->encrypt > 0)
+			pattrib->encrypt = _AES_;
+	}
+#endif
+
+	switch (pattrib->encrypt) {
+	case _WEP40_:
+	case _WEP104_:
+		pattrib->iv_len = 4;
+		pattrib->icv_len = 4;
+		WEP_IV(pattrib->iv, psta->dot11txpn, pattrib->key_idx);
+		break;
+
+	case _TKIP_:
+		pattrib->iv_len = 8;
+		pattrib->icv_len = 4;
+
+		if (psecuritypriv->busetkipkey == _FAIL) {
+#ifdef DBG_TX_DROP_FRAME
+			RTW_INFO("DBG_TX_DROP_FRAME %s psecuritypriv->busetkipkey(%d)==_FAIL drop packet\n", __FUNCTION__, psecuritypriv->busetkipkey);
+#endif
+			res = _FAIL;
+			goto exit;
+		}
+
+		if (bmcast)
+			TKIP_IV(pattrib->iv, psta->dot11txpn, pattrib->key_idx);
+		else
+			TKIP_IV(pattrib->iv, psta->dot11txpn, 0);
+
+
+		_rtw_memcpy(pattrib->dot11tkiptxmickey.skey, psta->dot11tkiptxmickey.skey, 16);
+
+		break;
+
+	case _AES_:
+
+		pattrib->iv_len = 8;
+		pattrib->icv_len = 8;
+
+		if (bmcast)
+			AES_IV(pattrib->iv, psta->dot11txpn, pattrib->key_idx);
+		else
+			AES_IV(pattrib->iv, psta->dot11txpn, 0);
+
+		break;
+
+#ifdef CONFIG_WAPI_SUPPORT
+	case _SMS4_:
+		pattrib->iv_len = 18;
+		pattrib->icv_len = 16;
+		rtw_wapi_get_iv(padapter, pattrib->ra, pattrib->iv);
+		break;
+#endif
+	default:
+		pattrib->iv_len = 0;
+		pattrib->icv_len = 0;
+		break;
+	}
+
+	if (pattrib->encrypt > 0)
+		_rtw_memcpy(pattrib->dot118021x_UncstKey.skey, psta->dot118021x_UncstKey.skey, 16);
+
+
+	if (pattrib->encrypt &&
+	    ((padapter->securitypriv.sw_encrypt == _TRUE) || (psecuritypriv->hw_decrypted == _FALSE))) {
+		pattrib->bswenc = _TRUE;
+	} else {
+		pattrib->bswenc = _FALSE;
+	}
+
+#if defined(CONFIG_CONCURRENT_MODE)
+	pattrib->bmc_camid = padapter->securitypriv.dot118021x_bmc_cam_id;
+#endif
+
+	if (pattrib->encrypt && bmcast && _rtw_camctl_chk_flags(padapter, SEC_STATUS_STA_PK_GK_CONFLICT_DIS_BMC_SEARCH))
+		pattrib->bswenc = _TRUE;
+
+#ifdef CONFIG_WAPI_SUPPORT
+	if (pattrib->encrypt == _SMS4_)
+		pattrib->bswenc = _FALSE;
+#endif
+
+exit:
+
+	return res;
+
+}
+
+u8	qos_acm(u8 acm_mask, u8 priority)
+{
+	u8	change_priority = priority;
+
+	switch (priority) {
+	case 0:
+	case 3:
+		if (acm_mask & BIT(1))
+			change_priority = 1;
+		break;
+	case 1:
+	case 2:
+		break;
+	case 4:
+	case 5:
+		if (acm_mask & BIT(2))
+			change_priority = 0;
+		break;
+	case 6:
+	case 7:
+		if (acm_mask & BIT(3))
+			change_priority = 5;
+		break;
+	default:
+		RTW_INFO("qos_acm(): invalid pattrib->priority: %d!!!\n", priority);
+		break;
+	}
+
+	return change_priority;
+}
+
+static void set_qos(struct pkt_file *ppktfile, struct pkt_attrib *pattrib)
+{
+	struct ethhdr etherhdr;
+	struct iphdr ip_hdr;
+	s32 UserPriority = 0;
+
+
+	_rtw_open_pktfile(ppktfile->pkt, ppktfile);
+	_rtw_pktfile_read(ppktfile, (unsigned char *)&etherhdr, ETH_HLEN);
+
+	/* get UserPriority from IP hdr */
+	if (pattrib->ether_type == 0x0800) {
+		_rtw_pktfile_read(ppktfile, (u8 *)&ip_hdr, sizeof(ip_hdr));
+		/*		UserPriority = (ntohs(ip_hdr.tos) >> 5) & 0x3; */
+		UserPriority = ip_hdr.tos >> 5;
+	}
+	/*
+		else if (pattrib->ether_type == 0x888e) {
+
+
+			UserPriority = 7;
+		}
+	*/
+
+	#ifdef CONFIG_ICMP_VOQ
+	if(pattrib->icmp_pkt==1)/*use VO queue to send icmp packet*/
+		UserPriority = 7;
+	#endif
+	pattrib->priority = UserPriority;
+	pattrib->hdrlen = WLAN_HDR_A3_QOS_LEN;
+	pattrib->subtype = WIFI_QOS_DATA_TYPE;
+}
+
+#ifdef CONFIG_TDLS
+u8 rtw_check_tdls_established(_adapter *padapter, struct pkt_attrib *pattrib)
+{
+	pattrib->ptdls_sta = NULL;
+
+	pattrib->direct_link = _FALSE;
+	if (padapter->tdlsinfo.link_established == _TRUE) {
+		pattrib->ptdls_sta = rtw_get_stainfo(&padapter->stapriv, pattrib->dst);
+#if 1
+		if ((pattrib->ptdls_sta != NULL) &&
+		    (pattrib->ptdls_sta->tdls_sta_state & TDLS_LINKED_STATE) &&
+		    (pattrib->ether_type != 0x0806)) {
+			pattrib->direct_link = _TRUE;
+			/* RTW_INFO("send ptk to "MAC_FMT" using direct link\n", MAC_ARG(pattrib->dst)); */
+		}
+#else
+		if (pattrib->ptdls_sta != NULL &&
+		    pattrib->ptdls_sta->tdls_sta_state & TDLS_LINKED_STATE) {
+			pattrib->direct_link = _TRUE;
+#if 0
+			RTW_INFO("send ptk to "MAC_FMT" using direct link\n", MAC_ARG(pattrib->dst));
+#endif
+		}
+
+		/* ARP frame may be helped by AP*/
+		if (pattrib->ether_type != 0x0806)
+			pattrib->direct_link = _FALSE;
+#endif
+	}
+
+	return pattrib->direct_link;
+}
+
+s32 update_tdls_attrib(_adapter *padapter, struct pkt_attrib *pattrib)
+{
+
+	struct sta_info *psta = NULL;
+	struct sta_priv		*pstapriv = &padapter->stapriv;
+	struct security_priv	*psecuritypriv = &padapter->securitypriv;
+	struct mlme_priv	*pmlmepriv = &padapter->mlmepriv;
+	struct qos_priv		*pqospriv = &pmlmepriv->qospriv;
+
+	s32 res = _SUCCESS;
+
+	psta = rtw_get_stainfo(pstapriv, pattrib->ra);
+	if (psta == NULL)	{
+		res = _FAIL;
+		goto exit;
+	}
+
+	pattrib->mac_id = psta->cmn.mac_id;
+	pattrib->psta = psta;
+	pattrib->ack_policy = 0;
+	/* get ether_hdr_len */
+	pattrib->pkt_hdrlen = ETH_HLEN;
+
+	/* [TDLS] TODO: setup req/rsp should be AC_BK */
+	if (pqospriv->qos_option &&  psta->qos_option) {
+		pattrib->priority = 4;	/* tdls management frame should be AC_VI */
+		pattrib->hdrlen = WLAN_HDR_A3_QOS_LEN;
+		pattrib->subtype = WIFI_QOS_DATA_TYPE;
+	} else {
+		pattrib->priority = 0;
+		pattrib->hdrlen = WLAN_HDR_A3_LEN;
+		pattrib->subtype = WIFI_DATA_TYPE;
+	}
+
+	/* TODO:_lock */
+	if (update_attrib_sec_info(padapter, pattrib, psta) == _FAIL) {
+		res = _FAIL;
+		goto exit;
+	}
+
+	update_attrib_phy_info(padapter, pattrib, psta);
+
+
+exit:
+
+	return res;
+}
+
+#endif /* CONFIG_TDLS */
+
+/*get non-qos hw_ssn control register,mapping to REG_HW_SEQ 0,1,2,3*/
+inline u8 rtw_get_hwseq_no(_adapter *padapter)
+{
+	u8 hwseq_num = 0;
+
+#ifdef CONFIG_CONCURRENT_MODE
+	#if defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C) || defined(CONFIG_RTL8822C)
+	hwseq_num = padapter->iface_id;
+	if (hwseq_num > 3)
+		hwseq_num = 3;
+	#else
+	if (!is_primary_adapter(padapter))
+		hwseq_num = 1;
+	#endif
+#endif /* CONFIG_CONCURRENT_MODE */
+	return hwseq_num;
+}
+#ifdef CONFIG_LPS
+#define LPS_PT_NORMAL	0
+#define LPS_PT_SP		1/* only DHCP packets is as SPECIAL_PACKET*/
+#define LPS_PT_ICMP		2
+
+/*If EAPOL , ARP , OR DHCP packet, driver must be in active mode.*/
+static u8 _rtw_lps_chk_packet_type(struct pkt_attrib *pattrib)
+{
+	u8 pkt_type = LPS_PT_NORMAL; /*normal data frame*/
+
+	#ifdef CONFIG_WAPI_SUPPORT
+	if ((pattrib->ether_type == 0x88B4) || (pattrib->ether_type == 0x0806) || (pattrib->ether_type == 0x888e) || (pattrib->dhcp_pkt == 1))
+		pkt_type = LPS_PT_SP;
+	#else /* !CONFIG_WAPI_SUPPORT */
+
+	#ifndef CONFIG_LPS_NOT_LEAVE_FOR_ICMP
+	if (pattrib->icmp_pkt == 1)
+		pkt_type = LPS_PT_ICMP;
+	else
+	#endif
+		if (pattrib->dhcp_pkt == 1)
+			pkt_type = LPS_PT_SP;
+	#endif
+	return pkt_type;
+}
+#endif
+static s32 update_attrib(_adapter *padapter, _pkt *pkt, struct pkt_attrib *pattrib)
+{
+	uint i;
+	struct pkt_file pktfile;
+	struct sta_info *psta = NULL;
+	struct ethhdr etherhdr;
+
+	sint bmcast;
+	struct sta_priv		*pstapriv = &padapter->stapriv;
+	struct mlme_priv		*pmlmepriv = &padapter->mlmepriv;
+	struct qos_priv		*pqospriv = &pmlmepriv->qospriv;
+	struct xmit_priv		*pxmitpriv = &padapter->xmitpriv;
+	sint res = _SUCCESS;
+#ifdef CONFIG_LPS
+	u8 pkt_type = 0;
+#endif
+
+	DBG_COUNTER(padapter->tx_logs.core_tx_upd_attrib);
+
+	_rtw_open_pktfile(pkt, &pktfile);
+	i = _rtw_pktfile_read(&pktfile, (u8 *)&etherhdr, ETH_HLEN);
+
+	pattrib->ether_type = ntohs(etherhdr.h_proto);
+
+	if (MLME_IS_MESH(padapter)) /* address resolve is done for mesh */
+		goto get_sta_info;
+
+	_rtw_memcpy(pattrib->dst, &etherhdr.h_dest, ETH_ALEN);
+	_rtw_memcpy(pattrib->src, &etherhdr.h_source, ETH_ALEN);
+
+	if ((check_fwstate(pmlmepriv, WIFI_ADHOC_STATE) == _TRUE) ||
+	    (check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE) == _TRUE)) {
+		_rtw_memcpy(pattrib->ra, pattrib->dst, ETH_ALEN);
+		_rtw_memcpy(pattrib->ta, adapter_mac_addr(padapter), ETH_ALEN);
+		DBG_COUNTER(padapter->tx_logs.core_tx_upd_attrib_adhoc);
+	} else if (check_fwstate(pmlmepriv, WIFI_STATION_STATE)) {
+#ifdef CONFIG_TDLS
+		if (rtw_check_tdls_established(padapter, pattrib) == _TRUE)
+			_rtw_memcpy(pattrib->ra, pattrib->dst, ETH_ALEN);	/* For TDLS direct link Tx, set ra to be same to dst */
+		else
+#endif
+			_rtw_memcpy(pattrib->ra, get_bssid(pmlmepriv), ETH_ALEN);
+		_rtw_memcpy(pattrib->ta, adapter_mac_addr(padapter), ETH_ALEN);
+		DBG_COUNTER(padapter->tx_logs.core_tx_upd_attrib_sta);
+	} else if (check_fwstate(pmlmepriv, WIFI_AP_STATE)) {
+		_rtw_memcpy(pattrib->ra, pattrib->dst, ETH_ALEN);
+		_rtw_memcpy(pattrib->ta, get_bssid(pmlmepriv), ETH_ALEN);
+		DBG_COUNTER(padapter->tx_logs.core_tx_upd_attrib_ap);
+	} else
+		DBG_COUNTER(padapter->tx_logs.core_tx_upd_attrib_unknown);
+
+get_sta_info:
+	bmcast = IS_MCAST(pattrib->ra);
+	if (bmcast) {
+		psta = rtw_get_bcmc_stainfo(padapter);
+		if (psta == NULL) { /* if we cannot get psta => drop the pkt */
+			DBG_COUNTER(padapter->tx_logs.core_tx_upd_attrib_err_sta);
+			#ifdef DBG_TX_DROP_FRAME
+			RTW_INFO("DBG_TX_DROP_FRAME %s get sta_info fail, ra:" MAC_FMT"\n", __func__, MAC_ARG(pattrib->ra));
+			#endif
+			res = _FAIL;
+			goto exit;
+		}
+	} else {
+		psta = rtw_get_stainfo(pstapriv, pattrib->ra);
+		if (psta == NULL) { /* if we cannot get psta => drop the pkt */
+			DBG_COUNTER(padapter->tx_logs.core_tx_upd_attrib_err_ucast_sta);
+			#ifdef DBG_TX_DROP_FRAME
+			RTW_INFO("DBG_TX_DROP_FRAME %s get sta_info fail, ra:" MAC_FMT"\n", __func__, MAC_ARG(pattrib->ra));
+			#endif
+			res = _FAIL;
+			goto exit;
+		} else if (check_fwstate(pmlmepriv, WIFI_AP_STATE) == _TRUE && !(psta->state & _FW_LINKED)) {
+			DBG_COUNTER(padapter->tx_logs.core_tx_upd_attrib_err_ucast_ap_link);
+			res = _FAIL;
+			goto exit;
+		}
+	}
+
+	if (!(psta->state & _FW_LINKED)) {
+		DBG_COUNTER(padapter->tx_logs.core_tx_upd_attrib_err_link);
+		RTW_INFO("%s-"ADPT_FMT" psta("MAC_FMT")->state(0x%x) != _FW_LINKED\n",
+			__func__, ADPT_ARG(padapter), MAC_ARG(psta->cmn.mac_addr), psta->state);
+		res = _FAIL;
+		goto exit;
+	}
+
+	pattrib->pktlen = pktfile.pkt_len;
+
+	/* TODO: 802.1Q VLAN header */
+	/* TODO: IPV6 */
+
+	if (ETH_P_IP == pattrib->ether_type) {
+		u8 ip[20];
+
+		_rtw_pktfile_read(&pktfile, ip, 20);
+
+		if (GET_IPV4_IHL(ip) * 4 > 20)
+			_rtw_pktfile_read(&pktfile, NULL, GET_IPV4_IHL(ip) - 20);
+
+		pattrib->icmp_pkt = 0;
+		pattrib->dhcp_pkt = 0;
+
+		if (GET_IPV4_PROTOCOL(ip) == 0x01) { /* ICMP */
+			pattrib->icmp_pkt = 1;
+			DBG_COUNTER(padapter->tx_logs.core_tx_upd_attrib_icmp);
+
+		} else if (GET_IPV4_PROTOCOL(ip) == 0x11) { /* UDP */
+			u8 udp[8];
+
+			_rtw_pktfile_read(&pktfile, udp, 8);
+
+			if ((GET_UDP_SRC(udp) == 68 && GET_UDP_DST(udp) == 67)
+				|| (GET_UDP_SRC(udp) == 67 && GET_UDP_DST(udp) == 68)
+			) {
+				/* 67 : UDP BOOTP server, 68 : UDP BOOTP client */
+				if (pattrib->pktlen > 282) { /* MINIMUM_DHCP_PACKET_SIZE */
+					pattrib->dhcp_pkt = 1;
+					DBG_COUNTER(padapter->tx_logs.core_tx_upd_attrib_dhcp);
+					if (0)
+						RTW_INFO("send DHCP packet\n");
+				}
+			}
+
+		} else if (GET_IPV4_PROTOCOL(ip) == 0x06 /* TCP */
+			&& rtw_st_ctl_chk_reg_s_proto(&psta->st_ctl, 0x06) == _TRUE
+		) {
+			u8 tcp[20];
+
+			_rtw_pktfile_read(&pktfile, tcp, 20);
+
+			if (rtw_st_ctl_chk_reg_rule(&psta->st_ctl, padapter, IPV4_SRC(ip), TCP_SRC(tcp), IPV4_DST(ip), TCP_DST(tcp)) == _TRUE) {
+				if (GET_TCP_SYN(tcp) && GET_TCP_ACK(tcp)) {
+					session_tracker_add_cmd(padapter, psta
+						, IPV4_SRC(ip), TCP_SRC(tcp)
+						, IPV4_SRC(ip), TCP_DST(tcp));
+					if (DBG_SESSION_TRACKER)
+						RTW_INFO(FUNC_ADPT_FMT" local:"IP_FMT":"PORT_FMT", remote:"IP_FMT":"PORT_FMT" SYN-ACK\n"
+							, FUNC_ADPT_ARG(padapter)
+							, IP_ARG(IPV4_SRC(ip)), PORT_ARG(TCP_SRC(tcp))
+							, IP_ARG(IPV4_DST(ip)), PORT_ARG(TCP_DST(tcp)));
+				}
+				if (GET_TCP_FIN(tcp)) {
+					session_tracker_del_cmd(padapter, psta
+						, IPV4_SRC(ip), TCP_SRC(tcp)
+						, IPV4_SRC(ip), TCP_DST(tcp));
+					if (DBG_SESSION_TRACKER)
+						RTW_INFO(FUNC_ADPT_FMT" local:"IP_FMT":"PORT_FMT", remote:"IP_FMT":"PORT_FMT" FIN\n"
+							, FUNC_ADPT_ARG(padapter)
+							, IP_ARG(IPV4_SRC(ip)), PORT_ARG(TCP_SRC(tcp))
+							, IP_ARG(IPV4_DST(ip)), PORT_ARG(TCP_DST(tcp)));
+				}
+			}
+		}
+
+	} else if (0x888e == pattrib->ether_type)
+		parsing_eapol_packet(padapter, pktfile.cur_addr, psta, 1);
+#ifdef DBG_ARP_DUMP
+	else if (pattrib->ether_type == ETH_P_ARP) {
+		u8 arp[28] = {0};
+
+		_rtw_pktfile_read(&pktfile, arp, 28);
+		dump_arp_pkt(RTW_DBGDUMP, etherhdr.h_dest, etherhdr.h_source, arp, 1);
+	}
+#endif
+
+	if ((pattrib->ether_type == 0x888e) || (pattrib->dhcp_pkt == 1))
+		rtw_mi_set_scan_deny(padapter, 3000);
+
+	if (check_fwstate(pmlmepriv, WIFI_STATION_STATE) &&
+		pattrib->ether_type == ETH_P_ARP &&
+		!IS_MCAST(pattrib->dst)) {
+		rtw_mi_set_scan_deny(padapter, 1000);
+		rtw_mi_scan_abort(padapter, _FALSE); /*rtw_scan_abort_no_wait*/
+	}
+
+#ifdef CONFIG_LPS
+	pkt_type = _rtw_lps_chk_packet_type(pattrib);
+
+	if (pkt_type == LPS_PT_SP) {/*packet is as SPECIAL_PACKET*/
+		DBG_COUNTER(padapter->tx_logs.core_tx_upd_attrib_active);
+		rtw_lps_ctrl_wk_cmd(padapter, LPS_CTRL_SPECIAL_PACKET, 1);
+	} else if (pkt_type == LPS_PT_ICMP)
+		rtw_lps_ctrl_wk_cmd(padapter, LPS_CTRL_LEAVE, 1);
+#endif /* CONFIG_LPS */
+
+#ifdef CONFIG_BEAMFORMING
+	update_attrib_txbf_info(padapter, pattrib, psta);
+#endif
+
+	/* TODO:_lock */
+	if (update_attrib_sec_info(padapter, pattrib, psta) == _FAIL) {
+		DBG_COUNTER(padapter->tx_logs.core_tx_upd_attrib_err_sec);
+		res = _FAIL;
+		goto exit;
+	}
+
+	/* get ether_hdr_len */
+	pattrib->pkt_hdrlen = ETH_HLEN;/* (pattrib->ether_type == 0x8100) ? (14 + 4 ): 14; */ /* vlan tag */
+
+	pattrib->hdrlen = WLAN_HDR_A3_LEN;
+	pattrib->subtype = WIFI_DATA_TYPE;
+	pattrib->qos_en = psta->qos_option;
+	pattrib->priority = 0;
+
+	if (check_fwstate(pmlmepriv, WIFI_AP_STATE | WIFI_MESH_STATE
+		| WIFI_ADHOC_STATE | WIFI_ADHOC_MASTER_STATE)
+	) {
+		if (pattrib->qos_en) {
+			set_qos(&pktfile, pattrib);
+			#ifdef CONFIG_RTW_MESH
+			if (MLME_IS_MESH(padapter))
+				rtw_mesh_tx_set_whdr_mctrl_len(pattrib->mesh_frame_mode, pattrib);
+			#endif
+		}
+	} else {
+#ifdef CONFIG_TDLS
+		if (pattrib->direct_link == _TRUE) {
+			if (pattrib->qos_en)
+				set_qos(&pktfile, pattrib);
+		} else
+#endif
+		{
+			if (pqospriv->qos_option) {
+				set_qos(&pktfile, pattrib);
+
+				if (pmlmepriv->acm_mask != 0)
+					pattrib->priority = qos_acm(pmlmepriv->acm_mask, pattrib->priority);
+			}
+		}
+	}
+	
+	update_attrib_phy_info(padapter, pattrib, psta);
+
+	/* RTW_INFO("%s ==> mac_id(%d)\n",__FUNCTION__,pattrib->mac_id ); */
+
+	pattrib->psta = psta;
+	/* TODO:_unlock */
+
+	pattrib->pctrl = 0;
+
+	pattrib->ack_policy = 0;
+
+	if (bmcast)
+		pattrib->rate = psta->init_rate;
+
+
+#ifdef CONFIG_WMMPS_STA
+	update_attrib_trigger_frame_info(padapter, pattrib);
+#endif /* CONFIG_WMMPS_STA */	
+
+	/* pattrib->priority = 5; */ /* force to used VI queue, for testing */
+	pattrib->hw_ssn_sel = pxmitpriv->hw_ssn_seq_no;
+	rtw_set_tx_chksum_offload(pkt, pattrib);
+
+exit:
+
+
+	return res;
+}
+
+static s32 xmitframe_addmic(_adapter *padapter, struct xmit_frame *pxmitframe)
+{
+	sint			curfragnum, length;
+	u8	*pframe, *payload, mic[8];
+	struct	mic_data		micdata;
+	/* struct	sta_info		*stainfo; */
+	struct	pkt_attrib	*pattrib = &pxmitframe->attrib;
+	struct	security_priv	*psecuritypriv = &padapter->securitypriv;
+	struct	xmit_priv		*pxmitpriv = &padapter->xmitpriv;
+	u8 priority[4] = {0x0, 0x0, 0x0, 0x0};
+	u8 hw_hdr_offset = 0;
+	sint bmcst = IS_MCAST(pattrib->ra);
+
+	/*
+		if(pattrib->psta)
+		{
+			stainfo = pattrib->psta;
+		}
+		else
+		{
+			RTW_INFO("%s, call rtw_get_stainfo()\n", __func__);
+			stainfo=rtw_get_stainfo(&padapter->stapriv ,&pattrib->ra[0]);
+		}
+
+		if(stainfo==NULL)
+		{
+			RTW_INFO("%s, psta==NUL\n", __func__);
+			return _FAIL;
+		}
+
+		if(!(stainfo->state &_FW_LINKED))
+		{
+			RTW_INFO("%s, psta->state(0x%x) != _FW_LINKED\n", __func__, stainfo->state);
+			return _FAIL;
+		}
+	*/
+
+
+#ifdef CONFIG_USB_TX_AGGREGATION
+	hw_hdr_offset = TXDESC_SIZE + (pxmitframe->pkt_offset * PACKET_OFFSET_SZ);;
+#else
+#ifdef CONFIG_TX_EARLY_MODE
+	hw_hdr_offset = TXDESC_OFFSET + EARLY_MODE_INFO_SIZE;
+#else
+	hw_hdr_offset = TXDESC_OFFSET;
+#endif
+#endif
+
+	if (pattrib->encrypt == _TKIP_) { /* if(psecuritypriv->dot11PrivacyAlgrthm==_TKIP_PRIVACY_) */
+		/* encode mic code */
+		/* if(stainfo!= NULL) */
+		{
+			u8 null_key[16] = {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0};
+
+			pframe = pxmitframe->buf_addr + hw_hdr_offset;
+
+			if (bmcst) {
+				if (_rtw_memcmp(psecuritypriv->dot118021XGrptxmickey[psecuritypriv->dot118021XGrpKeyid].skey, null_key, 16) == _TRUE) {
+					/* DbgPrint("\nxmitframe_addmic:stainfo->dot11tkiptxmickey==0\n"); */
+					/* rtw_msleep_os(10); */
+					return _FAIL;
+				}
+				/* start to calculate the mic code */
+				rtw_secmicsetkey(&micdata, psecuritypriv->dot118021XGrptxmickey[psecuritypriv->dot118021XGrpKeyid].skey);
+			} else {
+				if (_rtw_memcmp(&pattrib->dot11tkiptxmickey.skey[0], null_key, 16) == _TRUE) {
+					/* DbgPrint("\nxmitframe_addmic:stainfo->dot11tkiptxmickey==0\n"); */
+					/* rtw_msleep_os(10); */
+					return _FAIL;
+				}
+				/* start to calculate the mic code */
+				rtw_secmicsetkey(&micdata, &pattrib->dot11tkiptxmickey.skey[0]);
+			}
+
+			if (pframe[1] & 1) { /* ToDS==1 */
+				rtw_secmicappend(&micdata, &pframe[16], 6);  /* DA */
+				if (pframe[1] & 2) /* From Ds==1 */
+					rtw_secmicappend(&micdata, &pframe[24], 6);
+				else
+					rtw_secmicappend(&micdata, &pframe[10], 6);
+			} else {	/* ToDS==0 */
+				rtw_secmicappend(&micdata, &pframe[4], 6);   /* DA */
+				if (pframe[1] & 2) /* From Ds==1 */
+					rtw_secmicappend(&micdata, &pframe[16], 6);
+				else
+					rtw_secmicappend(&micdata, &pframe[10], 6);
+
+			}
+
+			if (pattrib->qos_en)
+				priority[0] = (u8)pxmitframe->attrib.priority;
+
+
+			rtw_secmicappend(&micdata, &priority[0], 4);
+
+			payload = pframe;
+
+			for (curfragnum = 0; curfragnum < pattrib->nr_frags; curfragnum++) {
+				payload = (u8 *)RND4((SIZE_PTR)(payload));
+
+				payload = payload + pattrib->hdrlen + pattrib->iv_len;
+				if ((curfragnum + 1) == pattrib->nr_frags) {
+					length = pattrib->last_txcmdsz - pattrib->hdrlen - pattrib->iv_len - ((pattrib->bswenc) ? pattrib->icv_len : 0);
+					rtw_secmicappend(&micdata, payload, length);
+					payload = payload + length;
+				} else {
+					length = pxmitpriv->frag_len - pattrib->hdrlen - pattrib->iv_len - ((pattrib->bswenc) ? pattrib->icv_len : 0);
+					rtw_secmicappend(&micdata, payload, length);
+					payload = payload + length + pattrib->icv_len;
+				}
+			}
+			rtw_secgetmic(&micdata, &(mic[0]));
+			/* add mic code  and add the mic code length in last_txcmdsz */
+
+			_rtw_memcpy(payload, &(mic[0]), 8);
+			pattrib->last_txcmdsz += 8;
+
+			payload = payload - pattrib->last_txcmdsz + 8;
+		}
+	}
+
+
+	return _SUCCESS;
+}
+
+/*#define DBG_TX_SW_ENCRYPTOR*/
+
+static s32 xmitframe_swencrypt(_adapter *padapter, struct xmit_frame *pxmitframe)
+{
+
+	struct	pkt_attrib	*pattrib = &pxmitframe->attrib;
+	/* struct 	security_priv	*psecuritypriv=&padapter->securitypriv; */
+
+
+	/* if((psecuritypriv->sw_encrypt)||(pattrib->bswenc))	 */
+	if (pattrib->bswenc) {
+#ifdef DBG_TX_SW_ENCRYPTOR
+		RTW_INFO(ADPT_FMT" - sec_type:%s DO SW encryption\n",
+			ADPT_ARG(padapter), security_type_str(pattrib->encrypt));
+#endif
+
+		switch (pattrib->encrypt) {
+		case _WEP40_:
+		case _WEP104_:
+			rtw_wep_encrypt(padapter, (u8 *)pxmitframe);
+			break;
+		case _TKIP_:
+			rtw_tkip_encrypt(padapter, (u8 *)pxmitframe);
+			break;
+		case _AES_:
+			rtw_aes_encrypt(padapter, (u8 *)pxmitframe);
+			break;
+#ifdef CONFIG_WAPI_SUPPORT
+		case _SMS4_:
+			rtw_sms4_encrypt(padapter, (u8 *)pxmitframe);
+#endif
+		default:
+			break;
+		}
+
+	}
+
+
+	return _SUCCESS;
+}
+
+s32 rtw_make_wlanhdr(_adapter *padapter , u8 *hdr, struct pkt_attrib *pattrib)
+{
+	u16 *qc;
+
+	struct rtw_ieee80211_hdr *pwlanhdr = (struct rtw_ieee80211_hdr *)hdr;
+	struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
+	struct qos_priv *pqospriv = &pmlmepriv->qospriv;
+	u8 qos_option = _FALSE;
+	sint res = _SUCCESS;
+	u16 *fctrl = &pwlanhdr->frame_ctl;
+
+	/* struct sta_info *psta; */
+
+	/* sint bmcst = IS_MCAST(pattrib->ra); */
+
+
+	/*
+		psta = rtw_get_stainfo(&padapter->stapriv, pattrib->ra);
+		if(pattrib->psta != psta)
+		{
+			RTW_INFO("%s, pattrib->psta(%p) != psta(%p)\n", __func__, pattrib->psta, psta);
+			return;
+		}
+
+		if(psta==NULL)
+		{
+			RTW_INFO("%s, psta==NUL\n", __func__);
+			return _FAIL;
+		}
+
+		if(!(psta->state &_FW_LINKED))
+		{
+			RTW_INFO("%s, psta->state(0x%x) != _FW_LINKED\n", __func__, psta->state);
+			return _FAIL;
+		}
+	*/
+
+	_rtw_memset(hdr, 0, WLANHDR_OFFSET);
+
+	set_frame_sub_type(fctrl, pattrib->subtype);
+
+	if (pattrib->subtype & WIFI_DATA_TYPE) {
+		if ((check_fwstate(pmlmepriv,  WIFI_STATION_STATE) == _TRUE)) {
+#ifdef CONFIG_TDLS
+			if (pattrib->direct_link == _TRUE) {
+				/* TDLS data transfer, ToDS=0, FrDs=0 */
+				_rtw_memcpy(pwlanhdr->addr1, pattrib->dst, ETH_ALEN);
+				_rtw_memcpy(pwlanhdr->addr2, pattrib->src, ETH_ALEN);
+				_rtw_memcpy(pwlanhdr->addr3, get_bssid(pmlmepriv), ETH_ALEN);
+
+				if (pattrib->qos_en)
+					qos_option = _TRUE;
+			} else
+#endif /* CONFIG_TDLS */
+			{
+				/* to_ds = 1, fr_ds = 0; */
+				/* 1.Data transfer to AP */
+				/* 2.Arp pkt will relayed by AP */
+				SetToDs(fctrl);
+				_rtw_memcpy(pwlanhdr->addr1, get_bssid(pmlmepriv), ETH_ALEN);
+				_rtw_memcpy(pwlanhdr->addr2, pattrib->ta, ETH_ALEN);
+				_rtw_memcpy(pwlanhdr->addr3, pattrib->dst, ETH_ALEN);
+
+				if (pqospriv->qos_option)
+					qos_option = _TRUE;
+			}
+		} else if ((check_fwstate(pmlmepriv,  WIFI_AP_STATE) == _TRUE)) {
+			/* to_ds = 0, fr_ds = 1; */
+			SetFrDs(fctrl);
+			_rtw_memcpy(pwlanhdr->addr1, pattrib->dst, ETH_ALEN);
+			_rtw_memcpy(pwlanhdr->addr2, get_bssid(pmlmepriv), ETH_ALEN);
+			_rtw_memcpy(pwlanhdr->addr3, pattrib->src, ETH_ALEN);
+
+			if (pattrib->qos_en)
+				qos_option = _TRUE;
+		} else if ((check_fwstate(pmlmepriv, WIFI_ADHOC_STATE) == _TRUE) ||
+			(check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE) == _TRUE)) {
+			_rtw_memcpy(pwlanhdr->addr1, pattrib->dst, ETH_ALEN);
+			_rtw_memcpy(pwlanhdr->addr2, pattrib->ta, ETH_ALEN);
+			_rtw_memcpy(pwlanhdr->addr3, get_bssid(pmlmepriv), ETH_ALEN);
+
+			if (pattrib->qos_en)
+				qos_option = _TRUE;
+#ifdef CONFIG_RTW_MESH
+		} else if (check_fwstate(pmlmepriv, WIFI_MESH_STATE) == _TRUE) {
+			rtw_mesh_tx_build_whdr(padapter, pattrib, fctrl, pwlanhdr);
+			if (pattrib->qos_en)
+				qos_option = _TRUE;
+			else {
+				RTW_WARN("[%s] !qos_en in Mesh\n", __FUNCTION__);
+				res = _FAIL;
+				goto exit;
+			}
+#endif
+		} else {
+			res = _FAIL;
+			goto exit;
+		}
+
+		if (pattrib->mdata)
+			SetMData(fctrl);
+
+		if (pattrib->encrypt)
+			SetPrivacy(fctrl);
+
+		if (qos_option) {
+			qc = (unsigned short *)(hdr + pattrib->hdrlen - 2);
+
+			if (pattrib->priority)
+				SetPriority(qc, pattrib->priority);
+
+			SetEOSP(qc, pattrib->eosp);
+
+			SetAckpolicy(qc, pattrib->ack_policy);
+
+			if(pattrib->amsdu)
+				SetAMsdu(qc, pattrib->amsdu);
+#ifdef CONFIG_RTW_MESH
+			if (MLME_IS_MESH(padapter)) {
+				/* active: don't care, light sleep: 0, deep sleep: 1*/
+				set_mps_lv(qc, 0); //TBD
+
+				/* TBD: temporary set (rspi, eosp) = (0, 1) which means End MPSP */
+				set_rspi(qc, 0);
+				SetEOSP(qc, 1);
+				
+				set_mctrl_present(qc, 1);
+			}
+#endif
+		}
+
+		/* TODO: fill HT Control Field */
+
+		/* Update Seq Num will be handled by f/w */
+		{
+			struct sta_info *psta;
+			psta = rtw_get_stainfo(&padapter->stapriv, pattrib->ra);
+			if (pattrib->psta != psta) {
+				RTW_INFO("%s, pattrib->psta(%p) != psta(%p)\n", __func__, pattrib->psta, psta);
+				return _FAIL;
+			}
+
+			if (psta == NULL) {
+				RTW_INFO("%s, psta==NUL\n", __func__);
+				return _FAIL;
+			}
+
+			if (!(psta->state & _FW_LINKED)) {
+				RTW_INFO("%s, psta->state(0x%x) != _FW_LINKED\n", __func__, psta->state);
+				return _FAIL;
+			}
+
+
+			if (psta) {
+				psta->sta_xmitpriv.txseq_tid[pattrib->priority]++;
+				psta->sta_xmitpriv.txseq_tid[pattrib->priority] &= 0xFFF;
+				pattrib->seqnum = psta->sta_xmitpriv.txseq_tid[pattrib->priority];
+
+				SetSeqNum(hdr, pattrib->seqnum);
+
+#ifdef CONFIG_80211N_HT
+#if 0 /* move into update_attrib_phy_info(). */
+				/* check if enable ampdu */
+				if (pattrib->ht_en && psta->htpriv.ampdu_enable) {
+					if (psta->htpriv.agg_enable_bitmap & BIT(pattrib->priority))
+						pattrib->ampdu_en = _TRUE;
+				}
+#endif
+				/* re-check if enable ampdu by BA_starting_seqctrl */
+				if (pattrib->ampdu_en == _TRUE) {
+					u16 tx_seq;
+
+					tx_seq = psta->BA_starting_seqctrl[pattrib->priority & 0x0f];
+
+					/* check BA_starting_seqctrl */
+					if (SN_LESS(pattrib->seqnum, tx_seq)) {
+						/* RTW_INFO("tx ampdu seqnum(%d) < tx_seq(%d)\n", pattrib->seqnum, tx_seq); */
+						pattrib->ampdu_en = _FALSE;/* AGG BK */
+					} else if (SN_EQUAL(pattrib->seqnum, tx_seq)) {
+						psta->BA_starting_seqctrl[pattrib->priority & 0x0f] = (tx_seq + 1) & 0xfff;
+
+						pattrib->ampdu_en = _TRUE;/* AGG EN */
+					} else {
+						/* RTW_INFO("tx ampdu over run\n"); */
+						psta->BA_starting_seqctrl[pattrib->priority & 0x0f] = (pattrib->seqnum + 1) & 0xfff;
+						pattrib->ampdu_en = _TRUE;/* AGG EN */
+					}
+
+				}
+#endif /* CONFIG_80211N_HT */
+			}
+		}
+
+	} else {
+
+	}
+
+exit:
+
+
+	return res;
+}
+
+s32 rtw_txframes_pending(_adapter *padapter)
+{
+	struct xmit_priv *pxmitpriv = &padapter->xmitpriv;
+
+	return ((_rtw_queue_empty(&pxmitpriv->be_pending) == _FALSE) ||
+		(_rtw_queue_empty(&pxmitpriv->bk_pending) == _FALSE) ||
+		(_rtw_queue_empty(&pxmitpriv->vi_pending) == _FALSE) ||
+		(_rtw_queue_empty(&pxmitpriv->vo_pending) == _FALSE));
+}
+
+s32 rtw_txframes_sta_ac_pending(_adapter *padapter, struct pkt_attrib *pattrib)
+{
+	struct sta_info *psta;
+	struct tx_servq *ptxservq;
+	int priority = pattrib->priority;
+	/*
+		if(pattrib->psta)
+		{
+			psta = pattrib->psta;
+		}
+		else
+		{
+			RTW_INFO("%s, call rtw_get_stainfo()\n", __func__);
+			psta=rtw_get_stainfo(&padapter->stapriv ,&pattrib->ra[0]);
+		}
+	*/
+	psta = rtw_get_stainfo(&padapter->stapriv, pattrib->ra);
+	if (pattrib->psta != psta) {
+		RTW_INFO("%s, pattrib->psta(%p) != psta(%p)\n", __func__, pattrib->psta, psta);
+		return 0;
+	}
+
+	if (psta == NULL) {
+		RTW_INFO("%s, psta==NUL\n", __func__);
+		return 0;
+	}
+
+	if (!(psta->state & _FW_LINKED)) {
+		RTW_INFO("%s, psta->state(0x%x) != _FW_LINKED\n", __func__, psta->state);
+		return 0;
+	}
+
+	switch (priority) {
+	case 1:
+	case 2:
+		ptxservq = &(psta->sta_xmitpriv.bk_q);
+		break;
+	case 4:
+	case 5:
+		ptxservq = &(psta->sta_xmitpriv.vi_q);
+		break;
+	case 6:
+	case 7:
+		ptxservq = &(psta->sta_xmitpriv.vo_q);
+		break;
+	case 0:
+	case 3:
+	default:
+		ptxservq = &(psta->sta_xmitpriv.be_q);
+		break;
+
+	}
+
+	return ptxservq->qcnt;
+}
+
+#ifdef CONFIG_TDLS
+
+int rtw_build_tdls_ies(_adapter *padapter, struct xmit_frame *pxmitframe, u8 *pframe, struct tdls_txmgmt *ptxmgmt)
+{
+	struct pkt_attrib *pattrib = &pxmitframe->attrib;
+	struct sta_info *ptdls_sta = NULL;
+	int res = _SUCCESS;
+
+	ptdls_sta = rtw_get_stainfo((&padapter->stapriv), pattrib->dst);
+	if (ptdls_sta == NULL) {
+		switch (ptxmgmt->action_code) {
+		case TDLS_DISCOVERY_REQUEST:
+		case TUNNELED_PROBE_REQ:
+		case TUNNELED_PROBE_RSP:
+			break;
+		default:
+			RTW_INFO("[TDLS] %s - Direct Link Peer = "MAC_FMT" not found for action = %d\n", __func__, MAC_ARG(pattrib->dst), ptxmgmt->action_code);
+			res = _FAIL;
+			goto exit;
+		}
+	}
+
+	switch (ptxmgmt->action_code) {
+	case TDLS_SETUP_REQUEST:
+		rtw_build_tdls_setup_req_ies(padapter, pxmitframe, pframe, ptxmgmt, ptdls_sta);
+		break;
+	case TDLS_SETUP_RESPONSE:
+		rtw_build_tdls_setup_rsp_ies(padapter, pxmitframe, pframe, ptxmgmt, ptdls_sta);
+		break;
+	case TDLS_SETUP_CONFIRM:
+		rtw_build_tdls_setup_cfm_ies(padapter, pxmitframe, pframe, ptxmgmt, ptdls_sta);
+		break;
+	case TDLS_TEARDOWN:
+		rtw_build_tdls_teardown_ies(padapter, pxmitframe, pframe, ptxmgmt, ptdls_sta);
+		break;
+	case TDLS_DISCOVERY_REQUEST:
+		rtw_build_tdls_dis_req_ies(padapter, pxmitframe, pframe, ptxmgmt);
+		break;
+	case TDLS_PEER_TRAFFIC_INDICATION:
+		rtw_build_tdls_peer_traffic_indication_ies(padapter, pxmitframe, pframe, ptxmgmt, ptdls_sta);
+		break;
+#ifdef CONFIG_TDLS_CH_SW
+	case TDLS_CHANNEL_SWITCH_REQUEST:
+		rtw_build_tdls_ch_switch_req_ies(padapter, pxmitframe, pframe, ptxmgmt, ptdls_sta);
+		break;
+	case TDLS_CHANNEL_SWITCH_RESPONSE:
+		rtw_build_tdls_ch_switch_rsp_ies(padapter, pxmitframe, pframe, ptxmgmt, ptdls_sta);
+		break;
+#endif
+	case TDLS_PEER_TRAFFIC_RESPONSE:
+		rtw_build_tdls_peer_traffic_rsp_ies(padapter, pxmitframe, pframe, ptxmgmt, ptdls_sta);
+		break;
+#ifdef CONFIG_WFD
+	case TUNNELED_PROBE_REQ:
+		rtw_build_tunneled_probe_req_ies(padapter, pxmitframe, pframe);
+		break;
+	case TUNNELED_PROBE_RSP:
+		rtw_build_tunneled_probe_rsp_ies(padapter, pxmitframe, pframe);
+		break;
+#endif /* CONFIG_WFD */
+	default:
+		res = _FAIL;
+		break;
+	}
+
+exit:
+	return res;
+}
+
+s32 rtw_make_tdls_wlanhdr(_adapter *padapter , u8 *hdr, struct pkt_attrib *pattrib, struct tdls_txmgmt *ptxmgmt)
+{
+	u16 *qc;
+	struct rtw_ieee80211_hdr *pwlanhdr = (struct rtw_ieee80211_hdr *)hdr;
+	struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
+	struct qos_priv *pqospriv = &pmlmepriv->qospriv;
+	struct sta_priv	*pstapriv = &padapter->stapriv;
+	struct sta_info *psta = NULL, *ptdls_sta = NULL;
+	u8 tdls_seq = 0, baddr[ETH_ALEN] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
+
+	sint res = _SUCCESS;
+	u16 *fctrl = &pwlanhdr->frame_ctl;
+
+
+	_rtw_memset(hdr, 0, WLANHDR_OFFSET);
+
+	set_frame_sub_type(fctrl, pattrib->subtype);
+
+	switch (ptxmgmt->action_code) {
+	case TDLS_SETUP_REQUEST:
+	case TDLS_SETUP_RESPONSE:
+	case TDLS_SETUP_CONFIRM:
+	case TDLS_PEER_TRAFFIC_INDICATION:
+	case TDLS_PEER_PSM_REQUEST:
+	case TUNNELED_PROBE_REQ:
+	case TUNNELED_PROBE_RSP:
+	case TDLS_DISCOVERY_REQUEST:
+		SetToDs(fctrl);
+		_rtw_memcpy(pwlanhdr->addr1, get_bssid(pmlmepriv), ETH_ALEN);
+		_rtw_memcpy(pwlanhdr->addr2, pattrib->src, ETH_ALEN);
+		_rtw_memcpy(pwlanhdr->addr3, pattrib->dst, ETH_ALEN);
+		break;
+	case TDLS_CHANNEL_SWITCH_REQUEST:
+	case TDLS_CHANNEL_SWITCH_RESPONSE:
+	case TDLS_PEER_PSM_RESPONSE:
+	case TDLS_PEER_TRAFFIC_RESPONSE:
+		_rtw_memcpy(pwlanhdr->addr1, pattrib->dst, ETH_ALEN);
+		_rtw_memcpy(pwlanhdr->addr2, pattrib->src, ETH_ALEN);
+		_rtw_memcpy(pwlanhdr->addr3, get_bssid(pmlmepriv), ETH_ALEN);
+		tdls_seq = 1;
+		break;
+	case TDLS_TEARDOWN:
+		if (ptxmgmt->status_code == _RSON_TDLS_TEAR_UN_RSN_) {
+			_rtw_memcpy(pwlanhdr->addr1, pattrib->dst, ETH_ALEN);
+			_rtw_memcpy(pwlanhdr->addr2, pattrib->src, ETH_ALEN);
+			_rtw_memcpy(pwlanhdr->addr3, get_bssid(pmlmepriv), ETH_ALEN);
+			tdls_seq = 1;
+		} else {
+			SetToDs(fctrl);
+			_rtw_memcpy(pwlanhdr->addr1, get_bssid(pmlmepriv), ETH_ALEN);
+			_rtw_memcpy(pwlanhdr->addr2, pattrib->src, ETH_ALEN);
+			_rtw_memcpy(pwlanhdr->addr3, pattrib->dst, ETH_ALEN);
+		}
+		break;
+	}
+
+	if (pattrib->encrypt)
+		SetPrivacy(fctrl);
+
+	if (ptxmgmt->action_code == TDLS_PEER_TRAFFIC_RESPONSE)
+		SetPwrMgt(fctrl);
+
+	if (pqospriv->qos_option) {
+		qc = (unsigned short *)(hdr + pattrib->hdrlen - 2);
+		if (pattrib->priority)
+			SetPriority(qc, pattrib->priority);
+		SetAckpolicy(qc, pattrib->ack_policy);
+	}
+
+	psta = pattrib->psta;
+
+	/* 1. update seq_num per link by sta_info */
+	/* 2. rewrite encrypt to _AES_, also rewrite iv_len, icv_len */
+	if (tdls_seq == 1) {
+		ptdls_sta = rtw_get_stainfo(pstapriv, pattrib->dst);
+		if (ptdls_sta) {
+			ptdls_sta->sta_xmitpriv.txseq_tid[pattrib->priority]++;
+			ptdls_sta->sta_xmitpriv.txseq_tid[pattrib->priority] &= 0xFFF;
+			pattrib->seqnum = ptdls_sta->sta_xmitpriv.txseq_tid[pattrib->priority];
+			SetSeqNum(hdr, pattrib->seqnum);
+
+			if (pattrib->encrypt) {
+				pattrib->encrypt = _AES_;
+				pattrib->iv_len = 8;
+				pattrib->icv_len = 8;
+				pattrib->bswenc = _FALSE;
+			}
+			pattrib->mac_id = ptdls_sta->cmn.mac_id;
+		} else {
+			res = _FAIL;
+			goto exit;
+		}
+	} else if (psta) {
+		psta->sta_xmitpriv.txseq_tid[pattrib->priority]++;
+		psta->sta_xmitpriv.txseq_tid[pattrib->priority] &= 0xFFF;
+		pattrib->seqnum = psta->sta_xmitpriv.txseq_tid[pattrib->priority];
+		SetSeqNum(hdr, pattrib->seqnum);
+	}
+
+
+exit:
+
+
+	return res;
+}
+
+s32 rtw_xmit_tdls_coalesce(_adapter *padapter, struct xmit_frame *pxmitframe, struct tdls_txmgmt *ptxmgmt)
+{
+	s32 llc_sz;
+
+	u8 *pframe, *mem_start;
+
+	struct sta_info		*psta;
+	struct sta_priv		*pstapriv = &padapter->stapriv;
+	struct mlme_priv	*pmlmepriv = &padapter->mlmepriv;
+	struct pkt_attrib	*pattrib = &pxmitframe->attrib;
+	u8 *pbuf_start;
+	s32 bmcst = IS_MCAST(pattrib->ra);
+	s32 res = _SUCCESS;
+
+
+	if (pattrib->psta)
+		psta = pattrib->psta;
+	else {
+		if (bmcst)
+			psta = rtw_get_bcmc_stainfo(padapter);
+		else
+			psta = rtw_get_stainfo(&padapter->stapriv, pattrib->ra);
+	}
+
+	if (psta == NULL) {
+		res = _FAIL;
+		goto exit;
+	}
+
+	if (pxmitframe->buf_addr == NULL) {
+		res = _FAIL;
+		goto exit;
+	}
+
+	pbuf_start = pxmitframe->buf_addr;
+	mem_start = pbuf_start + TXDESC_OFFSET;
+
+	if (rtw_make_tdls_wlanhdr(padapter, mem_start, pattrib, ptxmgmt) == _FAIL) {
+		res = _FAIL;
+		goto exit;
+	}
+
+	pframe = mem_start;
+	pframe += pattrib->hdrlen;
+
+	/* adding icv, if necessary... */
+	if (pattrib->iv_len) {
+		if (psta != NULL) {
+			switch (pattrib->encrypt) {
+			case _WEP40_:
+			case _WEP104_:
+				WEP_IV(pattrib->iv, psta->dot11txpn, pattrib->key_idx);
+				break;
+			case _TKIP_:
+				if (bmcst)
+					TKIP_IV(pattrib->iv, psta->dot11txpn, pattrib->key_idx);
+				else
+					TKIP_IV(pattrib->iv, psta->dot11txpn, 0);
+				break;
+			case _AES_:
+				if (bmcst)
+					AES_IV(pattrib->iv, psta->dot11txpn, pattrib->key_idx);
+				else
+					AES_IV(pattrib->iv, psta->dot11txpn, 0);
+				break;
+			}
+		}
+
+		_rtw_memcpy(pframe, pattrib->iv, pattrib->iv_len);
+		pframe += pattrib->iv_len;
+
+	}
+
+	llc_sz = rtw_put_snap(pframe, pattrib->ether_type);
+	pframe += llc_sz;
+
+	/* pattrib->pktlen will be counted in rtw_build_tdls_ies */
+	pattrib->pktlen = 0;
+
+	rtw_build_tdls_ies(padapter, pxmitframe, pframe, ptxmgmt);
+
+	if ((pattrib->icv_len > 0) && (pattrib->bswenc)) {
+		pframe += pattrib->pktlen;
+		_rtw_memcpy(pframe, pattrib->icv, pattrib->icv_len);
+		pframe += pattrib->icv_len;
+	}
+
+	pattrib->nr_frags = 1;
+	pattrib->last_txcmdsz = pattrib->hdrlen + pattrib->iv_len + llc_sz +
+		((pattrib->bswenc) ? pattrib->icv_len : 0) + pattrib->pktlen;
+
+	if (xmitframe_addmic(padapter, pxmitframe) == _FAIL) {
+		res = _FAIL;
+		goto exit;
+	}
+
+	xmitframe_swencrypt(padapter, pxmitframe);
+
+	update_attrib_vcs_info(padapter, pxmitframe);
+
+exit:
+
+
+	return res;
+}
+#endif /* CONFIG_TDLS */
+
+/*
+ * Calculate wlan 802.11 packet MAX size from pkt_attrib
+ * This function doesn't consider fragment case
+ */
+u32 rtw_calculate_wlan_pkt_size_by_attribue(struct pkt_attrib *pattrib)
+{
+	u32	len = 0;
+
+	len = pattrib->hdrlen /* WLAN Header */
+		+ pattrib->iv_len /* IV */
+		+ XATTRIB_GET_MCTRL_LEN(pattrib)
+		+ SNAP_SIZE + sizeof(u16) /* LLC */
+		+ pattrib->pktlen
+		+ (pattrib->encrypt == _TKIP_ ? 8 : 0) /* MIC */
+		+ (pattrib->bswenc ? pattrib->icv_len : 0) /* ICV */
+		;
+
+	return len;
+}
+
+#ifdef CONFIG_TX_AMSDU
+s32 check_amsdu(struct xmit_frame *pxmitframe)
+{
+	struct pkt_attrib *pattrib;
+	s32 ret = _TRUE;
+
+	if (!pxmitframe)
+		ret = _FALSE;
+
+	pattrib = &pxmitframe->attrib;
+
+	if (IS_MCAST(pattrib->ra))
+		ret = _FALSE;
+
+	if ((pattrib->ether_type == 0x888e) ||
+		(pattrib->ether_type == 0x0806) ||
+		(pattrib->ether_type == 0x88b4) ||
+		(pattrib->dhcp_pkt == 1))
+		ret = _FALSE;
+
+	if ((pattrib->encrypt == _WEP40_) ||
+	    (pattrib->encrypt == _WEP104_) ||
+	    (pattrib->encrypt == _TKIP_))
+		ret = _FALSE;
+
+	if (!pattrib->qos_en)
+		ret = _FALSE;
+
+	if (IS_AMSDU_AMPDU_NOT_VALID(pattrib))
+		ret = _FALSE;
+
+	return ret;
+}
+
+s32 check_amsdu_tx_support(_adapter *padapter)
+{
+	struct dvobj_priv *pdvobjpriv;
+	int tx_amsdu;
+	int tx_amsdu_rate;
+	int current_tx_rate;
+	s32 ret = _FALSE;
+
+	pdvobjpriv = adapter_to_dvobj(padapter);
+	tx_amsdu = padapter->tx_amsdu;
+	tx_amsdu_rate = padapter->tx_amsdu_rate;
+	current_tx_rate = pdvobjpriv->traffic_stat.cur_tx_tp;
+
+	if (tx_amsdu == 1)
+		ret = _TRUE;
+	else if (tx_amsdu == 2 && (tx_amsdu_rate == 0 || current_tx_rate > tx_amsdu_rate))
+		ret = _TRUE;
+	else
+		ret = _FALSE;
+
+	return ret;
+}
+
+s32 rtw_xmitframe_coalesce_amsdu(_adapter *padapter, struct xmit_frame *pxmitframe, struct xmit_frame *pxmitframe_queue)
+{
+
+	struct pkt_file pktfile;
+	struct pkt_attrib *pattrib;
+	_pkt *pkt;
+
+	struct pkt_file pktfile_queue;
+	struct pkt_attrib *pattrib_queue;
+	_pkt *pkt_queue;
+
+	s32 llc_sz, mem_sz;
+
+	s32 padding = 0;
+
+	u8 *pframe, *mem_start;
+	u8 hw_hdr_offset;
+
+	u16* len;
+	u8 *pbuf_start;
+	s32 res = _SUCCESS;
+
+	if (pxmitframe->buf_addr == NULL) {
+		RTW_INFO("==> %s buf_addr==NULL\n", __FUNCTION__);
+		return _FAIL;
+	}
+
+
+	pbuf_start = pxmitframe->buf_addr;
+
+#ifdef CONFIG_USB_TX_AGGREGATION
+	hw_hdr_offset =  TXDESC_SIZE + (pxmitframe->pkt_offset * PACKET_OFFSET_SZ);
+#else
+#ifdef CONFIG_TX_EARLY_MODE /* for SDIO && Tx Agg */
+	hw_hdr_offset = TXDESC_OFFSET + EARLY_MODE_INFO_SIZE;
+#else
+	hw_hdr_offset = TXDESC_OFFSET;
+#endif
+#endif
+
+	mem_start = pbuf_start + hw_hdr_offset; //for DMA
+
+	pattrib = &pxmitframe->attrib;
+
+	pattrib->amsdu = 1;
+
+	if (rtw_make_wlanhdr(padapter, mem_start, pattrib) == _FAIL) {
+		RTW_INFO("rtw_xmitframe_coalesce: rtw_make_wlanhdr fail; drop pkt\n");
+		res = _FAIL;
+		goto exit;
+	}
+
+	llc_sz = 0;
+
+	pframe = mem_start;
+
+	//SetMFrag(mem_start);
+	ClearMFrag(mem_start);
+
+	pframe += pattrib->hdrlen;
+
+	/* adding icv, if necessary... */
+	if (pattrib->iv_len) {
+		_rtw_memcpy(pframe, pattrib->iv, pattrib->iv_len); // queue or new?
+
+		RTW_DBG("rtw_xmitframe_coalesce: keyid=%d pattrib->iv[3]=%.2x pframe=%.2x %.2x %.2x %.2x\n",
+			padapter->securitypriv.dot11PrivacyKeyIndex, pattrib->iv[3], *pframe, *(pframe + 1), *(pframe + 2), *(pframe + 3));
+
+		pframe += pattrib->iv_len;
+	}
+
+	pattrib->last_txcmdsz = pattrib->hdrlen + pattrib->iv_len;
+
+	if(pxmitframe_queue)
+	{
+		pattrib_queue = &pxmitframe_queue->attrib;
+		pkt_queue = pxmitframe_queue->pkt;
+
+		_rtw_open_pktfile(pkt_queue, &pktfile_queue);
+		_rtw_pktfile_read(&pktfile_queue, NULL, pattrib_queue->pkt_hdrlen);
+
+		#ifdef CONFIG_RTW_MESH
+		if (MLME_IS_MESH(padapter)) {
+			/* mDA(6), mSA(6), len(2), mctrl */
+			_rtw_memcpy(pframe, pattrib_queue->mda, ETH_ALEN);
+			pframe += ETH_ALEN;
+			_rtw_memcpy(pframe, pattrib_queue->msa, ETH_ALEN);
+			pframe += ETH_ALEN;
+			len = (u16*)pframe;
+			pframe += 2;
+			rtw_mesh_tx_build_mctrl(padapter, pattrib_queue, pframe);
+			pframe += XATTRIB_GET_MCTRL_LEN(pattrib_queue);
+		} else
+		#endif
+		{
+			/* 802.3 MAC Header DA(6)  SA(6)  Len(2)*/
+			_rtw_memcpy(pframe, pattrib_queue->dst, ETH_ALEN);
+			pframe += ETH_ALEN;
+			_rtw_memcpy(pframe, pattrib_queue->src, ETH_ALEN);
+			pframe += ETH_ALEN;
+			len = (u16*)pframe;
+			pframe += 2;
+		}
+
+		llc_sz = rtw_put_snap(pframe, pattrib_queue->ether_type);
+		pframe += llc_sz;
+
+		mem_sz = _rtw_pktfile_read(&pktfile_queue, pframe, pattrib_queue->pktlen);
+		pframe += mem_sz;
+
+		*len = htons(XATTRIB_GET_MCTRL_LEN(pattrib_queue) + llc_sz + mem_sz);
+
+		//calc padding
+		padding = 4 - ((ETH_HLEN + XATTRIB_GET_MCTRL_LEN(pattrib_queue) + llc_sz + mem_sz) & (4-1));
+		if(padding == 4)
+			padding = 0;
+
+		//_rtw_memset(pframe,0xaa, padding);
+		pframe += padding;
+
+		pattrib->last_txcmdsz += ETH_HLEN + XATTRIB_GET_MCTRL_LEN(pattrib_queue) + llc_sz + mem_sz + padding ;
+	}
+
+	//2nd mpdu
+
+	pkt = pxmitframe->pkt;
+	_rtw_open_pktfile(pkt, &pktfile);
+	_rtw_pktfile_read(&pktfile, NULL, pattrib->pkt_hdrlen);
+
+#ifdef CONFIG_RTW_MESH
+	if (MLME_IS_MESH(padapter)) {
+		/* mDA(6), mSA(6), len(2), mctrl */
+		_rtw_memcpy(pframe, pattrib->mda, ETH_ALEN);
+		pframe += ETH_ALEN;
+		_rtw_memcpy(pframe, pattrib->msa, ETH_ALEN);
+		pframe += ETH_ALEN;
+		len = (u16*)pframe;
+		pframe += 2;
+		rtw_mesh_tx_build_mctrl(padapter, pattrib, pframe);
+		pframe += XATTRIB_GET_MCTRL_LEN(pattrib);
+	} else
+#endif
+	{
+		/* 802.3 MAC Header  DA(6)  SA(6)  Len(2) */
+		_rtw_memcpy(pframe, pattrib->dst, ETH_ALEN);
+		pframe += ETH_ALEN;
+		_rtw_memcpy(pframe, pattrib->src, ETH_ALEN);
+		pframe += ETH_ALEN;
+		len = (u16*)pframe;
+		pframe += 2;
+	}
+
+	llc_sz = rtw_put_snap(pframe, pattrib->ether_type);
+	pframe += llc_sz;
+
+	mem_sz = _rtw_pktfile_read(&pktfile, pframe, pattrib->pktlen);
+
+	pframe += mem_sz;
+
+	*len = htons(XATTRIB_GET_MCTRL_LEN(pattrib) + llc_sz + mem_sz);
+
+	//the last ampdu has no padding
+	padding = 0;
+
+	pattrib->nr_frags = 1;
+
+	pattrib->last_txcmdsz += ETH_HLEN + XATTRIB_GET_MCTRL_LEN(pattrib) + llc_sz + mem_sz + padding +
+		((pattrib->bswenc) ? pattrib->icv_len : 0) ;
+
+	if ((pattrib->icv_len > 0) && (pattrib->bswenc)) {
+		_rtw_memcpy(pframe, pattrib->icv, pattrib->icv_len);
+		pframe += pattrib->icv_len;
+	}
+
+	if (xmitframe_addmic(padapter, pxmitframe) == _FAIL) {
+		RTW_INFO("xmitframe_addmic(padapter, pxmitframe)==_FAIL\n");
+		res = _FAIL;
+		goto exit;
+	}
+
+	xmitframe_swencrypt(padapter, pxmitframe);
+
+	update_attrib_vcs_info(padapter, pxmitframe);
+
+exit:
+	return res;
+}
+#endif /* CONFIG_TX_AMSDU */
+
+/*
+
+This sub-routine will perform all the following:
+
+1. remove 802.3 header.
+2. create wlan_header, based on the info in pxmitframe
+3. append sta's iv/ext-iv
+4. append LLC
+5. move frag chunk from pframe to pxmitframe->mem
+6. apply sw-encrypt, if necessary.
+
+*/
+s32 rtw_xmitframe_coalesce(_adapter *padapter, _pkt *pkt, struct xmit_frame *pxmitframe)
+{
+	struct pkt_file pktfile;
+
+	s32 frg_inx, frg_len, mpdu_len, llc_sz, mem_sz;
+
+	SIZE_PTR addr;
+
+	u8 *pframe, *mem_start;
+	u8 hw_hdr_offset;
+
+	/* struct sta_info		*psta; */
+	/* struct sta_priv		*pstapriv = &padapter->stapriv; */
+	/* struct mlme_priv	*pmlmepriv = &padapter->mlmepriv; */
+	struct xmit_priv	*pxmitpriv = &padapter->xmitpriv;
+
+	struct pkt_attrib	*pattrib = &pxmitframe->attrib;
+
+	u8 *pbuf_start;
+
+	s32 bmcst = IS_MCAST(pattrib->ra);
+	s32 res = _SUCCESS;
+
+
+	/*
+		if (pattrib->psta)
+		{
+			psta = pattrib->psta;
+		} else
+		{
+			RTW_INFO("%s, call rtw_get_stainfo()\n", __func__);
+			psta = rtw_get_stainfo(&padapter->stapriv, pattrib->ra);
+		}
+
+		if(psta==NULL)
+		{
+
+			RTW_INFO("%s, psta==NUL\n", __func__);
+			return _FAIL;
+		}
+
+
+		if(!(psta->state &_FW_LINKED))
+		{
+			RTW_INFO("%s, psta->state(0x%x) != _FW_LINKED\n", __func__, psta->state);
+			return _FAIL;
+		}
+	*/
+	if (pxmitframe->buf_addr == NULL) {
+		RTW_INFO("==> %s buf_addr==NULL\n", __FUNCTION__);
+		return _FAIL;
+	}
+
+	pbuf_start = pxmitframe->buf_addr;
+
+#ifdef CONFIG_USB_TX_AGGREGATION
+	hw_hdr_offset =  TXDESC_SIZE + (pxmitframe->pkt_offset * PACKET_OFFSET_SZ);
+#else
+#ifdef CONFIG_TX_EARLY_MODE /* for SDIO && Tx Agg */
+	hw_hdr_offset = TXDESC_OFFSET + EARLY_MODE_INFO_SIZE;
+#else
+	hw_hdr_offset = TXDESC_OFFSET;
+#endif
+#endif
+
+	mem_start = pbuf_start +	hw_hdr_offset;
+
+	if (rtw_make_wlanhdr(padapter, mem_start, pattrib) == _FAIL) {
+		RTW_INFO("rtw_xmitframe_coalesce: rtw_make_wlanhdr fail; drop pkt\n");
+		res = _FAIL;
+		goto exit;
+	}
+
+	_rtw_open_pktfile(pkt, &pktfile);
+	_rtw_pktfile_read(&pktfile, NULL, pattrib->pkt_hdrlen);
+
+	frg_inx = 0;
+	frg_len = pxmitpriv->frag_len - 4;/* 2346-4 = 2342 */
+
+	while (1) {
+		llc_sz = 0;
+
+		mpdu_len = frg_len;
+
+		pframe = mem_start;
+
+		SetMFrag(mem_start);
+
+		pframe += pattrib->hdrlen;
+		mpdu_len -= pattrib->hdrlen;
+
+		/* adding icv, if necessary... */
+		if (pattrib->iv_len) {
+#if 0
+			/* if (check_fwstate(pmlmepriv, WIFI_MP_STATE)) */
+			/*	psta = rtw_get_stainfo(pstapriv, get_bssid(pmlmepriv)); */
+			/* else */
+			/*	psta = rtw_get_stainfo(pstapriv, pattrib->ra); */
+
+			if (psta != NULL) {
+				switch (pattrib->encrypt) {
+				case _WEP40_:
+				case _WEP104_:
+					WEP_IV(pattrib->iv, psta->dot11txpn, pattrib->key_idx);
+					break;
+				case _TKIP_:
+					if (bmcst)
+						TKIP_IV(pattrib->iv, psta->dot11txpn, pattrib->key_idx);
+					else
+						TKIP_IV(pattrib->iv, psta->dot11txpn, 0);
+					break;
+				case _AES_:
+					if (bmcst)
+						AES_IV(pattrib->iv, psta->dot11txpn, pattrib->key_idx);
+					else
+						AES_IV(pattrib->iv, psta->dot11txpn, 0);
+					break;
+#ifdef CONFIG_WAPI_SUPPORT
+				case _SMS4_:
+					rtw_wapi_get_iv(padapter, pattrib->ra, pattrib->iv);
+					break;
+#endif
+				}
+			}
+#endif
+			_rtw_memcpy(pframe, pattrib->iv, pattrib->iv_len);
+
+
+			pframe += pattrib->iv_len;
+
+			mpdu_len -= pattrib->iv_len;
+		}
+
+		if (frg_inx == 0) {
+			#ifdef CONFIG_RTW_MESH
+			if (MLME_IS_MESH(padapter)) {
+				rtw_mesh_tx_build_mctrl(padapter, pattrib, pframe);
+				pframe += XATTRIB_GET_MCTRL_LEN(pattrib);
+				mpdu_len -= XATTRIB_GET_MCTRL_LEN(pattrib);
+			}
+			#endif
+
+			llc_sz = rtw_put_snap(pframe, pattrib->ether_type);
+			pframe += llc_sz;
+			mpdu_len -= llc_sz;
+		}
+
+		if ((pattrib->icv_len > 0) && (pattrib->bswenc))
+			mpdu_len -= pattrib->icv_len;
+
+
+		if (bmcst) {
+			/* don't do fragment to broadcat/multicast packets */
+			mem_sz = _rtw_pktfile_read(&pktfile, pframe, pattrib->pktlen);
+		} else
+			mem_sz = _rtw_pktfile_read(&pktfile, pframe, mpdu_len);
+
+		pframe += mem_sz;
+
+		if ((pattrib->icv_len > 0) && (pattrib->bswenc)) {
+			_rtw_memcpy(pframe, pattrib->icv, pattrib->icv_len);
+			pframe += pattrib->icv_len;
+		}
+
+		frg_inx++;
+
+		if (bmcst || (rtw_endofpktfile(&pktfile) == _TRUE)) {
+			pattrib->nr_frags = frg_inx;
+
+			pattrib->last_txcmdsz = pattrib->hdrlen + pattrib->iv_len +
+				((pattrib->nr_frags == 1) ? (XATTRIB_GET_MCTRL_LEN(pattrib) + llc_sz) : 0) +
+				((pattrib->bswenc) ? pattrib->icv_len : 0) + mem_sz;
+
+			ClearMFrag(mem_start);
+
+			break;
+		}
+
+		addr = (SIZE_PTR)(pframe);
+
+		mem_start = (unsigned char *)RND4(addr) + hw_hdr_offset;
+		_rtw_memcpy(mem_start, pbuf_start + hw_hdr_offset, pattrib->hdrlen);
+
+	}
+
+	if (xmitframe_addmic(padapter, pxmitframe) == _FAIL) {
+		RTW_INFO("xmitframe_addmic(padapter, pxmitframe)==_FAIL\n");
+		res = _FAIL;
+		goto exit;
+	}
+
+	xmitframe_swencrypt(padapter, pxmitframe);
+
+	if (bmcst == _FALSE)
+		update_attrib_vcs_info(padapter, pxmitframe);
+	else
+		pattrib->vcs_mode = NONE_VCS;
+
+exit:
+
+
+	return res;
+}
+
+#if defined(CONFIG_IEEE80211W) || defined(CONFIG_RTW_MESH)
+/*
+ * CCMP encryption for unicast robust mgmt frame and broadcast group privicy action
+ * BIP for broadcast robust mgmt frame
+ */
+s32 rtw_mgmt_xmitframe_coalesce(_adapter *padapter, _pkt *pkt, struct xmit_frame *pxmitframe)
+{
+#define DBG_MGMT_XMIT_COALESEC_DUMP 0
+#define DBG_MGMT_XMIT_BIP_DUMP 0
+#define DBG_MGMT_XMIT_ENC_DUMP 0
+
+	struct pkt_file pktfile;
+	s32 frg_inx, frg_len, mpdu_len, llc_sz, mem_sz;
+	SIZE_PTR addr;
+	u8 *pframe, *mem_start = NULL, *tmp_buf = NULL;
+	u8 hw_hdr_offset, subtype ;
+	u8 category = 0xFF;
+	struct sta_info		*psta = NULL;
+	struct xmit_priv	*pxmitpriv = &padapter->xmitpriv;
+	struct pkt_attrib	*pattrib = &pxmitframe->attrib;
+	u8 *pbuf_start;
+	s32 bmcst = IS_MCAST(pattrib->ra);
+	s32 res = _FAIL;
+	u8 *BIP_AAD = NULL;
+	u8 *MGMT_body = NULL;
+
+	struct mlme_ext_priv	*pmlmeext = &padapter->mlmeextpriv;
+	struct mlme_priv	*pmlmepriv = &padapter->mlmepriv;
+	struct rtw_ieee80211_hdr	*pwlanhdr;
+	u8 MME[_MME_IE_LENGTH_];
+
+	_irqL irqL;
+	u32	ori_len;
+	union pn48 *pn = NULL;
+	u8 kid;
+
+	if (pxmitframe->buf_addr == NULL) {
+		RTW_WARN(FUNC_ADPT_FMT" pxmitframe->buf_addr\n"
+			, FUNC_ADPT_ARG(padapter));
+		return _FAIL;
+	}
+
+	mem_start = pframe = (u8 *)(pxmitframe->buf_addr) + TXDESC_OFFSET;
+	pwlanhdr = (struct rtw_ieee80211_hdr *)pframe;
+	subtype = get_frame_sub_type(pframe); /* bit(7)~bit(2) */
+
+	/* check if robust mgmt frame */
+	if (subtype != WIFI_DEAUTH && subtype != WIFI_DISASSOC && subtype != WIFI_ACTION)
+		return _SUCCESS;
+	if (subtype == WIFI_ACTION) {
+		category = *(pframe + sizeof(struct rtw_ieee80211_hdr_3addr));
+		if (CATEGORY_IS_NON_ROBUST(category))
+			return _SUCCESS;
+	}
+	if (!bmcst) {
+		if (pattrib->psta)
+			psta = pattrib->psta;
+		else
+			pattrib->psta = psta = rtw_get_stainfo(&padapter->stapriv, pattrib->ra);
+		if (psta == NULL) {
+			RTW_INFO(FUNC_ADPT_FMT" unicast sta == NULL\n", FUNC_ADPT_ARG(padapter));
+			return _FAIL;
+		}
+		if (!(psta->flags & WLAN_STA_MFP)) {
+			/* peer is not MFP capable, no need to encrypt */
+			return _SUCCESS;
+		}
+		if (psta->bpairwise_key_installed != _TRUE) {
+			RTW_INFO(FUNC_ADPT_FMT" PTK is not installed\n"
+				, FUNC_ADPT_ARG(padapter));
+			return _FAIL;
+		}
+	}
+
+	ori_len = BIP_AAD_SIZE + pattrib->pktlen;
+	tmp_buf = BIP_AAD = rtw_zmalloc(ori_len);
+	if (BIP_AAD == NULL)
+		return _FAIL;
+
+	_enter_critical_bh(&padapter->security_key_mutex, &irqL);
+
+	if (bmcst) {
+		if (subtype == WIFI_ACTION && CATEGORY_IS_GROUP_PRIVACY(category)) {
+			/* broadcast group privacy action frame */
+			#if DBG_MGMT_XMIT_COALESEC_DUMP
+			RTW_INFO(FUNC_ADPT_FMT" broadcast gp action(%u)\n"
+				, FUNC_ADPT_ARG(padapter), category);
+			#endif
+
+			if (pattrib->psta)
+				psta = pattrib->psta;
+			else
+				pattrib->psta = psta = rtw_get_bcmc_stainfo(padapter);
+			if (psta == NULL) {
+				RTW_INFO(FUNC_ADPT_FMT" broadcast sta == NULL\n"
+					, FUNC_ADPT_ARG(padapter));
+				goto xmitframe_coalesce_fail;
+			}
+			if (padapter->securitypriv.binstallGrpkey != _TRUE) {
+				RTW_INFO(FUNC_ADPT_FMT" GTK is not installed\n"
+					, FUNC_ADPT_ARG(padapter));
+				goto xmitframe_coalesce_fail;
+			}
+
+			pn = &psta->dot11txpn;
+			kid = padapter->securitypriv.dot118021XGrpKeyid;
+		} else {
+			#ifdef CONFIG_IEEE80211W
+			/* broadcast robust mgmt frame, using BIP */
+			int frame_body_len;
+			u8 mic[16];
+
+			/* IGTK key is not install ex: mesh MFP without IGTK */
+			if (SEC_IS_BIP_KEY_INSTALLED(&padapter->securitypriv) != _TRUE)
+				goto xmitframe_coalesce_success;
+
+			#if DBG_MGMT_XMIT_COALESEC_DUMP
+			if (subtype == WIFI_DEAUTH)
+				RTW_INFO(FUNC_ADPT_FMT" braodcast deauth\n", FUNC_ADPT_ARG(padapter));
+			else if (subtype == WIFI_DISASSOC)
+				RTW_INFO(FUNC_ADPT_FMT" braodcast disassoc\n", FUNC_ADPT_ARG(padapter));
+			else if (subtype == WIFI_ACTION) {
+				RTW_INFO(FUNC_ADPT_FMT" braodcast action(%u)\n"
+					, FUNC_ADPT_ARG(padapter), category);
+			}
+			#endif
+
+			_rtw_memset(MME, 0, _MME_IE_LENGTH_);
+
+			MGMT_body = pframe + sizeof(struct rtw_ieee80211_hdr_3addr);
+			pframe += pattrib->pktlen;
+
+			/* octent 0 and 1 is key index ,BIP keyid is 4 or 5, LSB only need octent 0 */
+			MME[0] = padapter->securitypriv.dot11wBIPKeyid;
+			/* increase PN and apply to packet */
+			padapter->securitypriv.dot11wBIPtxpn.val++;
+			RTW_PUT_LE64(&MME[2], padapter->securitypriv.dot11wBIPtxpn.val);
+
+			/* add MME IE with MIC all zero, MME string doesn't include element id and length */
+			pframe = rtw_set_ie(pframe, _MME_IE_ , 16 , MME, &(pattrib->pktlen));
+			pattrib->last_txcmdsz = pattrib->pktlen;
+			/* total frame length - header length */
+			frame_body_len = pattrib->pktlen - sizeof(struct rtw_ieee80211_hdr_3addr);
+
+			/* conscruct AAD, copy frame control field */
+			_rtw_memcpy(BIP_AAD, &pwlanhdr->frame_ctl, 2);
+			ClearRetry(BIP_AAD);
+			ClearPwrMgt(BIP_AAD);
+			ClearMData(BIP_AAD);
+			/* conscruct AAD, copy address 1 to address 3 */
+			_rtw_memcpy(BIP_AAD + 2, pwlanhdr->addr1, 18);
+			/* copy management fram body */
+			_rtw_memcpy(BIP_AAD + BIP_AAD_SIZE, MGMT_body, frame_body_len);
+
+			#if DBG_MGMT_XMIT_BIP_DUMP
+			/* dump total packet include MME with zero MIC */
+			{
+				int i;
+				printk("Total packet: ");
+				for (i = 0; i < BIP_AAD_SIZE + frame_body_len; i++)
+					printk(" %02x ", BIP_AAD[i]);
+				printk("\n");
+			}
+			#endif
+
+			/* calculate mic */
+			if (omac1_aes_128(padapter->securitypriv.dot11wBIPKey[padapter->securitypriv.dot11wBIPKeyid].skey
+				  , BIP_AAD, BIP_AAD_SIZE + frame_body_len, mic))
+				goto xmitframe_coalesce_fail;
+
+			#if DBG_MGMT_XMIT_BIP_DUMP
+			/* dump calculated mic result */
+			{
+				int i;
+				printk("Calculated mic result: ");
+				for (i = 0; i < 16; i++)
+					printk(" %02x ", mic[i]);
+				printk("\n");
+			}
+			#endif
+
+			/* copy right BIP mic value, total is 128bits, we use the 0~63 bits */
+			_rtw_memcpy(pframe - 8, mic, 8);
+
+			#if DBG_MGMT_XMIT_BIP_DUMP
+			/*dump all packet after mic ok */
+			{
+				int pp;
+				printk("pattrib->pktlen = %d\n", pattrib->pktlen);
+				for(pp=0;pp< pattrib->pktlen; pp++)
+					printk(" %02x ", mem_start[pp]);
+				printk("\n");
+			}
+			#endif
+
+			#endif /* CONFIG_IEEE80211W */
+
+			goto xmitframe_coalesce_success;
+		}
+	}
+	else {
+		/* unicast robust mgmt frame */
+		#if DBG_MGMT_XMIT_COALESEC_DUMP
+		if (subtype == WIFI_DEAUTH) {
+			RTW_INFO(FUNC_ADPT_FMT" unicast deauth to "MAC_FMT"\n"
+				, FUNC_ADPT_ARG(padapter), MAC_ARG(pattrib->ra));
+		} else if (subtype == WIFI_DISASSOC) {
+			RTW_INFO(FUNC_ADPT_FMT" unicast disassoc to "MAC_FMT"\n"
+				, FUNC_ADPT_ARG(padapter), MAC_ARG(pattrib->ra));
+		} else if (subtype == WIFI_ACTION) {
+			RTW_INFO(FUNC_ADPT_FMT" unicast action(%u) to "MAC_FMT"\n"
+				, FUNC_ADPT_ARG(padapter), category, MAC_ARG(pattrib->ra));
+		}
+		#endif
+
+		_rtw_memcpy(pattrib->dot118021x_UncstKey.skey, psta->dot118021x_UncstKey.skey, 16);
+
+		/* To use wrong key */
+		if (pattrib->key_type == IEEE80211W_WRONG_KEY) {
+			RTW_INFO("use wrong key\n");
+			pattrib->dot118021x_UncstKey.skey[0] = 0xff;
+		}
+
+		pn = &psta->dot11txpn;
+		kid = 0;
+	}
+
+	#if DBG_MGMT_XMIT_ENC_DUMP
+	/* before encrypt dump the management packet content */
+	{
+		int i;
+		printk("Management pkt: ");
+		for(i=0; i<pattrib->pktlen; i++)
+		printk(" %02x ", pframe[i]);
+		printk("=======\n");
+	}
+	#endif
+
+	/* bakeup original management packet */
+	_rtw_memcpy(tmp_buf, pframe, pattrib->pktlen);
+	/* move to data portion */
+	pframe += pattrib->hdrlen;
+
+	/* 802.11w encrypted management packet must be _AES_ */
+	if (pattrib->key_type != IEEE80211W_NO_KEY) {
+		pattrib->encrypt = _AES_;
+		pattrib->bswenc = _TRUE;
+	}
+
+	pattrib->iv_len = 8;
+	/* it's MIC of AES */
+	pattrib->icv_len = 8;
+
+	switch (pattrib->encrypt) {
+	case _AES_:
+		/* set AES IV header */
+		AES_IV(pattrib->iv, (*pn), kid);
+		break;
+	default:
+		goto xmitframe_coalesce_fail;
+	}
+
+	/* insert iv header into management frame */
+	_rtw_memcpy(pframe, pattrib->iv, pattrib->iv_len);
+	pframe += pattrib->iv_len;
+	/* copy mgmt data portion after CCMP header */
+	_rtw_memcpy(pframe, tmp_buf + pattrib->hdrlen, pattrib->pktlen - pattrib->hdrlen);
+	/* move pframe to end of mgmt pkt */
+	pframe += pattrib->pktlen - pattrib->hdrlen;
+	/* add 8 bytes CCMP IV header to length */
+	pattrib->pktlen += pattrib->iv_len;
+
+	#if DBG_MGMT_XMIT_ENC_DUMP
+	/* dump management packet include AES IV header */
+	{
+		int i;
+		printk("Management pkt + IV: ");
+		/* for(i=0; i<pattrib->pktlen; i++) */
+
+		printk("@@@@@@@@@@@@@\n");
+	}
+	#endif
+
+	if ((pattrib->icv_len > 0) && (pattrib->bswenc)) {
+		_rtw_memcpy(pframe, pattrib->icv, pattrib->icv_len);
+		pframe += pattrib->icv_len;
+	}
+	/* add 8 bytes MIC */
+	pattrib->pktlen += pattrib->icv_len;
+	/* set final tx command size */
+	pattrib->last_txcmdsz = pattrib->pktlen;
+
+	/* set protected bit must be beofre SW encrypt */
+	SetPrivacy(mem_start);
+
+	#if DBG_MGMT_XMIT_ENC_DUMP
+	/* dump management packet include AES header */
+	{
+		int i;
+		printk("prepare to enc Management pkt + IV: ");
+		for (i = 0; i < pattrib->pktlen; i++)
+			printk(" %02x ", mem_start[i]);
+		printk("@@@@@@@@@@@@@\n");
+	}
+	#endif
+
+	/* software encrypt */
+	xmitframe_swencrypt(padapter, pxmitframe);
+
+xmitframe_coalesce_success:
+	_exit_critical_bh(&padapter->security_key_mutex, &irqL);
+	rtw_mfree(BIP_AAD, ori_len);
+	return _SUCCESS;
+
+xmitframe_coalesce_fail:
+	_exit_critical_bh(&padapter->security_key_mutex, &irqL);
+	rtw_mfree(BIP_AAD, ori_len);
+
+	return _FAIL;
+}
+#endif /* defined(CONFIG_IEEE80211W) || defined(CONFIG_RTW_MESH) */
+
+/* Logical Link Control(LLC) SubNetwork Attachment Point(SNAP) header
+ * IEEE LLC/SNAP header contains 8 octets
+ * First 3 octets comprise the LLC portion
+ * SNAP portion, 5 octets, is divided into two fields:
+ *	Organizationally Unique Identifier(OUI), 3 octets,
+ *	type, defined by that organization, 2 octets.
+ */
+s32 rtw_put_snap(u8 *data, u16 h_proto)
+{
+	struct ieee80211_snap_hdr *snap;
+	u8 *oui;
+
+
+	snap = (struct ieee80211_snap_hdr *)data;
+	snap->dsap = 0xaa;
+	snap->ssap = 0xaa;
+	snap->ctrl = 0x03;
+
+	if (h_proto == 0x8137 || h_proto == 0x80f3)
+		oui = P802_1H_OUI;
+	else
+		oui = RFC1042_OUI;
+
+	snap->oui[0] = oui[0];
+	snap->oui[1] = oui[1];
+	snap->oui[2] = oui[2];
+
+	*(u16 *)(data + SNAP_SIZE) = htons(h_proto);
+
+
+	return SNAP_SIZE + sizeof(u16);
+}
+
+void rtw_update_protection(_adapter *padapter, u8 *ie, uint ie_len)
+{
+
+	uint	protection;
+	u8	*perp;
+	sint	 erp_len;
+	struct	xmit_priv *pxmitpriv = &padapter->xmitpriv;
+	struct	registry_priv *pregistrypriv = &padapter->registrypriv;
+
+
+	switch (pxmitpriv->vcs_setting) {
+	case DISABLE_VCS:
+		pxmitpriv->vcs = NONE_VCS;
+		break;
+
+	case ENABLE_VCS:
+		break;
+
+	case AUTO_VCS:
+	default:
+		perp = rtw_get_ie(ie, _ERPINFO_IE_, &erp_len, ie_len);
+		if (perp == NULL)
+			pxmitpriv->vcs = NONE_VCS;
+		else {
+			protection = (*(perp + 2)) & BIT(1);
+			if (protection) {
+				if (pregistrypriv->vcs_type == RTS_CTS)
+					pxmitpriv->vcs = RTS_CTS;
+				else
+					pxmitpriv->vcs = CTS_TO_SELF;
+			} else
+				pxmitpriv->vcs = NONE_VCS;
+		}
+
+		break;
+
+	}
+
+
+}
+
+void rtw_count_tx_stats(PADAPTER padapter, struct xmit_frame *pxmitframe, int sz)
+{
+	struct sta_info *psta = NULL;
+	struct stainfo_stats *pstats = NULL;
+	struct xmit_priv	*pxmitpriv = &padapter->xmitpriv;
+	struct mlme_priv	*pmlmepriv = &padapter->mlmepriv;
+	u8	pkt_num = 1;
+
+	if ((pxmitframe->frame_tag & 0x0f) == DATA_FRAMETAG) {
+#if defined(CONFIG_USB_TX_AGGREGATION) || defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
+		pkt_num = pxmitframe->agg_num;
+#endif
+		pmlmepriv->LinkDetectInfo.NumTxOkInPeriod += pkt_num;
+
+		pxmitpriv->tx_pkts += pkt_num;
+
+		pxmitpriv->tx_bytes += sz;
+
+		psta = pxmitframe->attrib.psta;
+		if (psta) {
+			pstats = &psta->sta_stats;
+
+			pstats->tx_pkts += pkt_num;
+
+			pstats->tx_bytes += sz;
+			#if defined(CONFIG_CHECK_LEAVE_LPS) && defined(CONFIG_LPS_CHK_BY_TP)
+			if (adapter_to_pwrctl(padapter)->lps_chk_by_tp)
+				traffic_check_for_leave_lps_by_tp(padapter, _TRUE, psta);
+			#endif /* CONFIG_LPS */
+		}
+
+#ifdef CONFIG_CHECK_LEAVE_LPS
+		/* traffic_check_for_leave_lps(padapter, _TRUE); */
+#endif /* CONFIG_CHECK_LEAVE_LPS */
+
+	}
+}
+
+static struct xmit_buf *__rtw_alloc_cmd_xmitbuf(struct xmit_priv *pxmitpriv,
+		enum cmdbuf_type buf_type)
+{
+	struct xmit_buf *pxmitbuf =  NULL;
+
+
+	pxmitbuf = &pxmitpriv->pcmd_xmitbuf[buf_type];
+	if (pxmitbuf !=  NULL) {
+		pxmitbuf->priv_data = NULL;
+
+#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
+		pxmitbuf->len = 0;
+		pxmitbuf->pdata = pxmitbuf->ptail = pxmitbuf->phead;
+		pxmitbuf->agg_num = 0;
+		pxmitbuf->pg_num = 0;
+#endif
+#ifdef CONFIG_PCI_HCI
+		pxmitbuf->len = 0;
+#ifdef CONFIG_TRX_BD_ARCH
+		/*pxmitbuf->buf_desc = NULL;*/
+#else
+		pxmitbuf->desc = NULL;
+#endif
+#endif
+
+		if (pxmitbuf->sctx) {
+			RTW_INFO("%s pxmitbuf->sctx is not NULL\n", __func__);
+			rtw_sctx_done_err(&pxmitbuf->sctx, RTW_SCTX_DONE_BUF_ALLOC);
+		}
+	} else
+		RTW_INFO("%s fail, no xmitbuf available !!!\n", __func__);
+
+	return pxmitbuf;
+}
+
+struct xmit_frame *__rtw_alloc_cmdxmitframe(struct xmit_priv *pxmitpriv,
+		enum cmdbuf_type buf_type)
+{
+	struct xmit_frame		*pcmdframe;
+	struct xmit_buf		*pxmitbuf;
+
+	pcmdframe = rtw_alloc_xmitframe(pxmitpriv);
+	if (pcmdframe == NULL) {
+		RTW_INFO("%s, alloc xmitframe fail\n", __FUNCTION__);
+		return NULL;
+	}
+
+	pxmitbuf = __rtw_alloc_cmd_xmitbuf(pxmitpriv, buf_type);
+	if (pxmitbuf == NULL) {
+		RTW_INFO("%s, alloc xmitbuf fail\n", __FUNCTION__);
+		rtw_free_xmitframe(pxmitpriv, pcmdframe);
+		return NULL;
+	}
+
+	pcmdframe->frame_tag = MGNT_FRAMETAG;
+
+	pcmdframe->pxmitbuf = pxmitbuf;
+
+	pcmdframe->buf_addr = pxmitbuf->pbuf;
+
+	/* initial memory to zero */
+	_rtw_memset(pcmdframe->buf_addr, 0, MAX_CMDBUF_SZ);
+
+	pxmitbuf->priv_data = pcmdframe;
+
+	return pcmdframe;
+
+}
+
+struct xmit_buf *rtw_alloc_xmitbuf_ext(struct xmit_priv *pxmitpriv)
+{
+	_irqL irqL;
+	struct xmit_buf *pxmitbuf =  NULL;
+	_list *plist, *phead;
+	_queue *pfree_queue = &pxmitpriv->free_xmit_extbuf_queue;
+
+
+	_enter_critical(&pfree_queue->lock, &irqL);
+
+	if (_rtw_queue_empty(pfree_queue) == _TRUE)
+		pxmitbuf = NULL;
+	else {
+
+		phead = get_list_head(pfree_queue);
+
+		plist = get_next(phead);
+
+		pxmitbuf = LIST_CONTAINOR(plist, struct xmit_buf, list);
+
+		rtw_list_delete(&(pxmitbuf->list));
+	}
+
+	if (pxmitbuf !=  NULL) {
+		pxmitpriv->free_xmit_extbuf_cnt--;
+#ifdef DBG_XMIT_BUF_EXT
+		RTW_INFO("DBG_XMIT_BUF_EXT ALLOC no=%d,  free_xmit_extbuf_cnt=%d\n", pxmitbuf->no, pxmitpriv->free_xmit_extbuf_cnt);
+#endif
+
+
+		pxmitbuf->priv_data = NULL;
+
+#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
+		pxmitbuf->len = 0;
+		pxmitbuf->pdata = pxmitbuf->ptail = pxmitbuf->phead;
+		pxmitbuf->agg_num = 1;
+#endif
+#ifdef CONFIG_PCI_HCI
+		pxmitbuf->len = 0;
+#ifdef CONFIG_TRX_BD_ARCH
+		/*pxmitbuf->buf_desc = NULL;*/
+#else
+		pxmitbuf->desc = NULL;
+#endif
+#endif
+
+		if (pxmitbuf->sctx) {
+			RTW_INFO("%s pxmitbuf->sctx is not NULL\n", __func__);
+			rtw_sctx_done_err(&pxmitbuf->sctx, RTW_SCTX_DONE_BUF_ALLOC);
+		}
+
+	}
+
+	_exit_critical(&pfree_queue->lock, &irqL);
+
+
+	return pxmitbuf;
+}
+
+s32 rtw_free_xmitbuf_ext(struct xmit_priv *pxmitpriv, struct xmit_buf *pxmitbuf)
+{
+	_irqL irqL;
+	_queue *pfree_queue = &pxmitpriv->free_xmit_extbuf_queue;
+
+
+	if (pxmitbuf == NULL)
+		return _FAIL;
+
+	_enter_critical(&pfree_queue->lock, &irqL);
+
+	rtw_list_delete(&pxmitbuf->list);
+
+	rtw_list_insert_tail(&(pxmitbuf->list), get_list_head(pfree_queue));
+	pxmitpriv->free_xmit_extbuf_cnt++;
+#ifdef DBG_XMIT_BUF_EXT
+	RTW_INFO("DBG_XMIT_BUF_EXT FREE no=%d, free_xmit_extbuf_cnt=%d\n", pxmitbuf->no , pxmitpriv->free_xmit_extbuf_cnt);
+#endif
+
+	_exit_critical(&pfree_queue->lock, &irqL);
+
+
+	return _SUCCESS;
+}
+
+struct xmit_buf *rtw_alloc_xmitbuf(struct xmit_priv *pxmitpriv)
+{
+	_irqL irqL;
+	struct xmit_buf *pxmitbuf =  NULL;
+	_list *plist, *phead;
+	_queue *pfree_xmitbuf_queue = &pxmitpriv->free_xmitbuf_queue;
+
+
+	/* RTW_INFO("+rtw_alloc_xmitbuf\n"); */
+
+	_enter_critical(&pfree_xmitbuf_queue->lock, &irqL);
+
+	if (_rtw_queue_empty(pfree_xmitbuf_queue) == _TRUE)
+		pxmitbuf = NULL;
+	else {
+
+		phead = get_list_head(pfree_xmitbuf_queue);
+
+		plist = get_next(phead);
+
+		pxmitbuf = LIST_CONTAINOR(plist, struct xmit_buf, list);
+
+		rtw_list_delete(&(pxmitbuf->list));
+	}
+
+	if (pxmitbuf !=  NULL) {
+		pxmitpriv->free_xmitbuf_cnt--;
+#ifdef DBG_XMIT_BUF
+		RTW_INFO("DBG_XMIT_BUF ALLOC no=%d,  free_xmitbuf_cnt=%d\n", pxmitbuf->no, pxmitpriv->free_xmitbuf_cnt);
+#endif
+		/* RTW_INFO("alloc, free_xmitbuf_cnt=%d\n", pxmitpriv->free_xmitbuf_cnt); */
+
+		pxmitbuf->priv_data = NULL;
+
+#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
+		pxmitbuf->len = 0;
+		pxmitbuf->pdata = pxmitbuf->ptail = pxmitbuf->phead;
+		pxmitbuf->agg_num = 0;
+		pxmitbuf->pg_num = 0;
+#endif
+#ifdef CONFIG_PCI_HCI
+		pxmitbuf->len = 0;
+#ifdef CONFIG_TRX_BD_ARCH
+		/*pxmitbuf->buf_desc = NULL;*/
+#else
+		pxmitbuf->desc = NULL;
+#endif
+#endif
+
+		if (pxmitbuf->sctx) {
+			RTW_INFO("%s pxmitbuf->sctx is not NULL\n", __func__);
+			rtw_sctx_done_err(&pxmitbuf->sctx, RTW_SCTX_DONE_BUF_ALLOC);
+		}
+	}
+#ifdef DBG_XMIT_BUF
+	else
+		RTW_INFO("DBG_XMIT_BUF rtw_alloc_xmitbuf return NULL\n");
+#endif
+
+	_exit_critical(&pfree_xmitbuf_queue->lock, &irqL);
+
+
+	return pxmitbuf;
+}
+
+s32 rtw_free_xmitbuf(struct xmit_priv *pxmitpriv, struct xmit_buf *pxmitbuf)
+{
+	_irqL irqL;
+	_queue *pfree_xmitbuf_queue = &pxmitpriv->free_xmitbuf_queue;
+
+
+	/* RTW_INFO("+rtw_free_xmitbuf\n"); */
+
+	if (pxmitbuf == NULL)
+		return _FAIL;
+
+	if (pxmitbuf->sctx) {
+		RTW_INFO("%s pxmitbuf->sctx is not NULL\n", __func__);
+		rtw_sctx_done_err(&pxmitbuf->sctx, RTW_SCTX_DONE_BUF_FREE);
+	}
+
+	if (pxmitbuf->buf_tag == XMITBUF_CMD) {
+	} else if (pxmitbuf->buf_tag == XMITBUF_MGNT)
+		rtw_free_xmitbuf_ext(pxmitpriv, pxmitbuf);
+	else {
+		_enter_critical(&pfree_xmitbuf_queue->lock, &irqL);
+
+		rtw_list_delete(&pxmitbuf->list);
+
+		rtw_list_insert_tail(&(pxmitbuf->list), get_list_head(pfree_xmitbuf_queue));
+
+		pxmitpriv->free_xmitbuf_cnt++;
+		/* RTW_INFO("FREE, free_xmitbuf_cnt=%d\n", pxmitpriv->free_xmitbuf_cnt); */
+#ifdef DBG_XMIT_BUF
+		RTW_INFO("DBG_XMIT_BUF FREE no=%d, free_xmitbuf_cnt=%d\n", pxmitbuf->no , pxmitpriv->free_xmitbuf_cnt);
+#endif
+		_exit_critical(&pfree_xmitbuf_queue->lock, &irqL);
+	}
+
+
+	return _SUCCESS;
+}
+
+void rtw_init_xmitframe(struct xmit_frame *pxframe)
+{
+	if (pxframe !=  NULL) { /* default value setting */
+		pxframe->buf_addr = NULL;
+		pxframe->pxmitbuf = NULL;
+
+		_rtw_memset(&pxframe->attrib, 0, sizeof(struct pkt_attrib));
+		/* pxframe->attrib.psta = NULL; */
+
+		pxframe->frame_tag = DATA_FRAMETAG;
+
+#ifdef CONFIG_USB_HCI
+		pxframe->pkt = NULL;
+#ifdef USB_PACKET_OFFSET_SZ
+		pxframe->pkt_offset = (PACKET_OFFSET_SZ / 8);
+#else
+		pxframe->pkt_offset = 1;/* default use pkt_offset to fill tx desc */
+#endif
+
+#ifdef CONFIG_USB_TX_AGGREGATION
+		pxframe->agg_num = 1;
+#endif
+
+#endif /* #ifdef CONFIG_USB_HCI */
+
+#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
+		pxframe->pg_num = 1;
+		pxframe->agg_num = 1;
+#endif
+
+#ifdef CONFIG_XMIT_ACK
+		pxframe->ack_report = 0;
+#endif
+
+	}
+}
+
+/*
+Calling context:
+1. OS_TXENTRY
+2. RXENTRY (rx_thread or RX_ISR/RX_CallBack)
+
+If we turn on USE_RXTHREAD, then, no need for critical section.
+Otherwise, we must use _enter/_exit critical to protect free_xmit_queue...
+
+Must be very very cautious...
+
+*/
+struct xmit_frame *rtw_alloc_xmitframe(struct xmit_priv *pxmitpriv)/* (_queue *pfree_xmit_queue) */
+{
+	/*
+		Please remember to use all the osdep_service api,
+		and lock/unlock or _enter/_exit critical to protect
+		pfree_xmit_queue
+	*/
+
+	_irqL irqL;
+	struct xmit_frame *pxframe = NULL;
+	_list *plist, *phead;
+	_queue *pfree_xmit_queue = &pxmitpriv->free_xmit_queue;
+
+
+	_enter_critical_bh(&pfree_xmit_queue->lock, &irqL);
+
+	if (_rtw_queue_empty(pfree_xmit_queue) == _TRUE) {
+		pxframe =  NULL;
+	} else {
+		phead = get_list_head(pfree_xmit_queue);
+
+		plist = get_next(phead);
+
+		pxframe = LIST_CONTAINOR(plist, struct xmit_frame, list);
+
+		rtw_list_delete(&(pxframe->list));
+		pxmitpriv->free_xmitframe_cnt--;
+	}
+
+	_exit_critical_bh(&pfree_xmit_queue->lock, &irqL);
+
+	rtw_init_xmitframe(pxframe);
+
+
+	return pxframe;
+}
+
+struct xmit_frame *rtw_alloc_xmitframe_ext(struct xmit_priv *pxmitpriv)
+{
+	_irqL irqL;
+	struct xmit_frame *pxframe = NULL;
+	_list *plist, *phead;
+	_queue *queue = &pxmitpriv->free_xframe_ext_queue;
+
+
+	_enter_critical_bh(&queue->lock, &irqL);
+
+	if (_rtw_queue_empty(queue) == _TRUE) {
+		pxframe =  NULL;
+	} else {
+		phead = get_list_head(queue);
+		plist = get_next(phead);
+		pxframe = LIST_CONTAINOR(plist, struct xmit_frame, list);
+
+		rtw_list_delete(&(pxframe->list));
+		pxmitpriv->free_xframe_ext_cnt--;
+	}
+
+	_exit_critical_bh(&queue->lock, &irqL);
+
+	rtw_init_xmitframe(pxframe);
+
+
+	return pxframe;
+}
+
+struct xmit_frame *rtw_alloc_xmitframe_once(struct xmit_priv *pxmitpriv)
+{
+	struct xmit_frame *pxframe = NULL;
+	u8 *alloc_addr;
+
+	alloc_addr = rtw_zmalloc(sizeof(struct xmit_frame) + 4);
+
+	if (alloc_addr == NULL)
+		goto exit;
+
+	pxframe = (struct xmit_frame *)N_BYTE_ALIGMENT((SIZE_PTR)(alloc_addr), 4);
+	pxframe->alloc_addr = alloc_addr;
+
+	pxframe->padapter = pxmitpriv->adapter;
+	pxframe->frame_tag = NULL_FRAMETAG;
+
+	pxframe->pkt = NULL;
+
+	pxframe->buf_addr = NULL;
+	pxframe->pxmitbuf = NULL;
+
+	rtw_init_xmitframe(pxframe);
+
+	RTW_INFO("################## %s ##################\n", __func__);
+
+exit:
+	return pxframe;
+}
+
+s32 rtw_free_xmitframe(struct xmit_priv *pxmitpriv, struct xmit_frame *pxmitframe)
+{
+	_irqL irqL;
+	_queue *queue = NULL;
+	_adapter *padapter = pxmitpriv->adapter;
+	_pkt *pndis_pkt = NULL;
+
+
+	if (pxmitframe == NULL) {
+		goto exit;
+	}
+
+	if (pxmitframe->pkt) {
+		pndis_pkt = pxmitframe->pkt;
+		pxmitframe->pkt = NULL;
+	}
+
+	if (pxmitframe->alloc_addr) {
+		RTW_INFO("################## %s with alloc_addr ##################\n", __func__);
+		rtw_mfree(pxmitframe->alloc_addr, sizeof(struct xmit_frame) + 4);
+		goto check_pkt_complete;
+	}
+
+	if (pxmitframe->ext_tag == 0)
+		queue = &pxmitpriv->free_xmit_queue;
+	else if (pxmitframe->ext_tag == 1)
+		queue = &pxmitpriv->free_xframe_ext_queue;
+	else
+		rtw_warn_on(1);
+
+	_enter_critical_bh(&queue->lock, &irqL);
+
+	rtw_list_delete(&pxmitframe->list);
+	rtw_list_insert_tail(&pxmitframe->list, get_list_head(queue));
+	if (pxmitframe->ext_tag == 0) {
+		pxmitpriv->free_xmitframe_cnt++;
+	} else if (pxmitframe->ext_tag == 1) {
+		pxmitpriv->free_xframe_ext_cnt++;
+	} else {
+	}
+
+	_exit_critical_bh(&queue->lock, &irqL);
+
+check_pkt_complete:
+
+	if (pndis_pkt)
+		rtw_os_pkt_complete(padapter, pndis_pkt);
+
+exit:
+
+
+	return _SUCCESS;
+}
+
+void rtw_free_xmitframe_queue(struct xmit_priv *pxmitpriv, _queue *pframequeue)
+{
+	_irqL irqL;
+	_list	*plist, *phead;
+	struct	xmit_frame	*pxmitframe;
+
+
+	_enter_critical_bh(&(pframequeue->lock), &irqL);
+
+	phead = get_list_head(pframequeue);
+	plist = get_next(phead);
+
+	while (rtw_end_of_queue_search(phead, plist) == _FALSE) {
+
+		pxmitframe = LIST_CONTAINOR(plist, struct xmit_frame, list);
+
+		plist = get_next(plist);
+
+		rtw_free_xmitframe(pxmitpriv, pxmitframe);
+
+	}
+	_exit_critical_bh(&(pframequeue->lock), &irqL);
+
+}
+
+s32 rtw_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe)
+{
+	DBG_COUNTER(padapter->tx_logs.core_tx_enqueue);
+	if (rtw_xmit_classifier(padapter, pxmitframe) == _FAIL) {
+		/*		pxmitframe->pkt = NULL; */
+		return _FAIL;
+	}
+
+	return _SUCCESS;
+}
+
+static struct xmit_frame *dequeue_one_xmitframe(struct xmit_priv *pxmitpriv, struct hw_xmit *phwxmit, struct tx_servq *ptxservq, _queue *pframe_queue)
+{
+	_list	*xmitframe_plist, *xmitframe_phead;
+	struct	xmit_frame	*pxmitframe = NULL;
+
+	xmitframe_phead = get_list_head(pframe_queue);
+	xmitframe_plist = get_next(xmitframe_phead);
+
+	while ((rtw_end_of_queue_search(xmitframe_phead, xmitframe_plist)) == _FALSE) {
+		pxmitframe = LIST_CONTAINOR(xmitframe_plist, struct xmit_frame, list);
+
+		/* xmitframe_plist = get_next(xmitframe_plist); */
+
+		/*#ifdef RTK_DMP_PLATFORM
+		#ifdef CONFIG_USB_TX_AGGREGATION
+				if((ptxservq->qcnt>0) && (ptxservq->qcnt<=2))
+				{
+					pxmitframe = NULL;
+
+					tasklet_schedule(&pxmitpriv->xmit_tasklet);
+
+					break;
+				}
+		#endif
+		#endif*/
+		rtw_list_delete(&pxmitframe->list);
+
+		ptxservq->qcnt--;
+
+		/* rtw_list_insert_tail(&pxmitframe->list, &phwxmit->pending); */
+
+		/* ptxservq->qcnt--; */
+
+		break;
+
+		/* pxmitframe = NULL; */
+
+	}
+
+	return pxmitframe;
+}
+
+static struct xmit_frame *get_one_xmitframe(struct xmit_priv *pxmitpriv, struct hw_xmit *phwxmit, struct tx_servq *ptxservq, _queue *pframe_queue)
+{
+	_list	*xmitframe_plist, *xmitframe_phead;
+	struct	xmit_frame	*pxmitframe = NULL;
+
+	xmitframe_phead = get_list_head(pframe_queue);
+	xmitframe_plist = get_next(xmitframe_phead);
+
+	while ((rtw_end_of_queue_search(xmitframe_phead, xmitframe_plist)) == _FALSE) {
+		pxmitframe = LIST_CONTAINOR(xmitframe_plist, struct xmit_frame, list);
+		break;
+	}
+
+	return pxmitframe;
+}
+
+struct xmit_frame *rtw_get_xframe(struct xmit_priv *pxmitpriv, int *num_frame)
+{
+	_irqL irqL0;
+	_list *sta_plist, *sta_phead;
+	struct hw_xmit *phwxmit_i = pxmitpriv->hwxmits;
+	sint entry =  pxmitpriv->hwxmit_entry;
+
+	struct hw_xmit *phwxmit;
+	struct tx_servq *ptxservq = NULL;
+	_queue *pframe_queue = NULL;
+	struct xmit_frame *pxmitframe = NULL;
+	_adapter *padapter = pxmitpriv->adapter;
+	struct registry_priv	*pregpriv = &padapter->registrypriv;
+	int i, inx[4];
+
+	inx[0] = 0;
+	inx[1] = 1;
+	inx[2] = 2;
+	inx[3] = 3;
+
+	*num_frame = 0;
+
+	/*No amsdu when wifi_spec on*/
+	if (pregpriv->wifi_spec == 1) {
+		return NULL;
+	}
+
+	_enter_critical_bh(&pxmitpriv->lock, &irqL0);
+
+	for (i = 0; i < entry; i++) {
+		phwxmit = phwxmit_i + inx[i];
+
+		sta_phead = get_list_head(phwxmit->sta_queue);
+		sta_plist = get_next(sta_phead);
+
+		while ((rtw_end_of_queue_search(sta_phead, sta_plist)) == _FALSE) {
+
+			ptxservq = LIST_CONTAINOR(sta_plist, struct tx_servq, tx_pending);
+			pframe_queue = &ptxservq->sta_pending;
+
+			if(ptxservq->qcnt)
+			{
+				*num_frame = ptxservq->qcnt;
+				pxmitframe = get_one_xmitframe(pxmitpriv, phwxmit, ptxservq, pframe_queue);
+				goto exit;
+			}
+			sta_plist = get_next(sta_plist);
+		}
+	}
+
+exit:
+
+	_exit_critical_bh(&pxmitpriv->lock, &irqL0);
+
+	return pxmitframe;
+}
+
+
+struct xmit_frame *rtw_dequeue_xframe(struct xmit_priv *pxmitpriv, struct hw_xmit *phwxmit_i, sint entry)
+{
+	_irqL irqL0;
+	_list *sta_plist, *sta_phead;
+	struct hw_xmit *phwxmit;
+	struct tx_servq *ptxservq = NULL;
+	_queue *pframe_queue = NULL;
+	struct xmit_frame *pxmitframe = NULL;
+	_adapter *padapter = pxmitpriv->adapter;
+	struct registry_priv	*pregpriv = &padapter->registrypriv;
+	int i, inx[4];
+
+	inx[0] = 0;
+	inx[1] = 1;
+	inx[2] = 2;
+	inx[3] = 3;
+
+	if (pregpriv->wifi_spec == 1) {
+		int j;
+#if 0
+		if (flags < XMIT_QUEUE_ENTRY) {
+			/* priority exchange according to the completed xmitbuf flags. */
+			inx[flags] = 0;
+			inx[0] = flags;
+		}
+#endif
+
+#if defined(CONFIG_USB_HCI) || defined(CONFIG_SDIO_HCI) || defined(CONFIG_PCI_HCI)
+		for (j = 0; j < 4; j++)
+			inx[j] = pxmitpriv->wmm_para_seq[j];
+#endif
+	}
+
+	_enter_critical_bh(&pxmitpriv->lock, &irqL0);
+
+	for (i = 0; i < entry; i++) {
+		phwxmit = phwxmit_i + inx[i];
+
+		/* _enter_critical_ex(&phwxmit->sta_queue->lock, &irqL0); */
+
+		sta_phead = get_list_head(phwxmit->sta_queue);
+		sta_plist = get_next(sta_phead);
+
+		while ((rtw_end_of_queue_search(sta_phead, sta_plist)) == _FALSE) {
+
+			ptxservq = LIST_CONTAINOR(sta_plist, struct tx_servq, tx_pending);
+
+			pframe_queue = &ptxservq->sta_pending;
+
+			pxmitframe = dequeue_one_xmitframe(pxmitpriv, phwxmit, ptxservq, pframe_queue);
+
+			if (pxmitframe) {
+				phwxmit->accnt--;
+
+				/* Remove sta node when there is no pending packets. */
+				if (_rtw_queue_empty(pframe_queue)) /* must be done after get_next and before break */
+					rtw_list_delete(&ptxservq->tx_pending);
+
+				/* _exit_critical_ex(&phwxmit->sta_queue->lock, &irqL0); */
+
+				goto exit;
+			}
+
+			sta_plist = get_next(sta_plist);
+
+		}
+
+		/* _exit_critical_ex(&phwxmit->sta_queue->lock, &irqL0); */
+
+	}
+
+exit:
+
+	_exit_critical_bh(&pxmitpriv->lock, &irqL0);
+
+	return pxmitframe;
+}
+
+#if 1
+struct tx_servq *rtw_get_sta_pending(_adapter *padapter, struct sta_info *psta, sint up, u8 *ac)
+{
+	struct tx_servq *ptxservq = NULL;
+
+
+	switch (up) {
+	case 1:
+	case 2:
+		ptxservq = &(psta->sta_xmitpriv.bk_q);
+		*(ac) = 3;
+		break;
+
+	case 4:
+	case 5:
+		ptxservq = &(psta->sta_xmitpriv.vi_q);
+		*(ac) = 1;
+		break;
+
+	case 6:
+	case 7:
+		ptxservq = &(psta->sta_xmitpriv.vo_q);
+		*(ac) = 0;
+		break;
+
+	case 0:
+	case 3:
+	default:
+		ptxservq = &(psta->sta_xmitpriv.be_q);
+		*(ac) = 2;
+		break;
+
+	}
+
+
+	return ptxservq;
+}
+#else
+__inline static struct tx_servq *rtw_get_sta_pending
+(_adapter *padapter, _queue **ppstapending, struct sta_info *psta, sint up)
+{
+	struct tx_servq *ptxservq;
+	struct hw_xmit *phwxmits =  padapter->xmitpriv.hwxmits;
+
+
+#ifdef CONFIG_RTL8711
+
+	if (IS_MCAST(psta->cmn.mac_addr)) {
+		ptxservq = &(psta->sta_xmitpriv.be_q); /* we will use be_q to queue bc/mc frames in BCMC_stainfo */
+		*ppstapending = &padapter->xmitpriv.bm_pending;
+	} else
+#endif
+	{
+		switch (up) {
+		case 1:
+		case 2:
+			ptxservq = &(psta->sta_xmitpriv.bk_q);
+			*ppstapending = &padapter->xmitpriv.bk_pending;
+			(phwxmits + 3)->accnt++;
+			break;
+
+		case 4:
+		case 5:
+			ptxservq = &(psta->sta_xmitpriv.vi_q);
+			*ppstapending = &padapter->xmitpriv.vi_pending;
+			(phwxmits + 1)->accnt++;
+			break;
+
+		case 6:
+		case 7:
+			ptxservq = &(psta->sta_xmitpriv.vo_q);
+			*ppstapending = &padapter->xmitpriv.vo_pending;
+			(phwxmits + 0)->accnt++;
+			break;
+
+		case 0:
+		case 3:
+		default:
+			ptxservq = &(psta->sta_xmitpriv.be_q);
+			*ppstapending = &padapter->xmitpriv.be_pending;
+			(phwxmits + 2)->accnt++;
+			break;
+
+		}
+
+	}
+
+
+	return ptxservq;
+}
+#endif
+
+/*
+ * Will enqueue pxmitframe to the proper queue,
+ * and indicate it to xx_pending list.....
+ */
+s32 rtw_xmit_classifier(_adapter *padapter, struct xmit_frame *pxmitframe)
+{
+	/* _irqL irqL0; */
+	u8	ac_index;
+	struct sta_info	*psta;
+	struct tx_servq	*ptxservq;
+	struct pkt_attrib	*pattrib = &pxmitframe->attrib;
+	struct hw_xmit	*phwxmits =  padapter->xmitpriv.hwxmits;
+	sint res = _SUCCESS;
+
+
+	DBG_COUNTER(padapter->tx_logs.core_tx_enqueue_class);
+
+	/*
+		if (pattrib->psta) {
+			psta = pattrib->psta;
+		} else {
+			RTW_INFO("%s, call rtw_get_stainfo()\n", __func__);
+			psta = rtw_get_stainfo(pstapriv, pattrib->ra);
+		}
+	*/
+
+	psta = rtw_get_stainfo(&padapter->stapriv, pattrib->ra);
+	if (pattrib->psta != psta) {
+		DBG_COUNTER(padapter->tx_logs.core_tx_enqueue_class_err_sta);
+		RTW_INFO("%s, pattrib->psta(%p) != psta(%p)\n", __func__, pattrib->psta, psta);
+		return _FAIL;
+	}
+
+	if (psta == NULL) {
+		DBG_COUNTER(padapter->tx_logs.core_tx_enqueue_class_err_nosta);
+		res = _FAIL;
+		RTW_INFO("rtw_xmit_classifier: psta == NULL\n");
+		goto exit;
+	}
+
+	if (!(psta->state & _FW_LINKED)) {
+		DBG_COUNTER(padapter->tx_logs.core_tx_enqueue_class_err_fwlink);
+		RTW_INFO("%s, psta->state(0x%x) != _FW_LINKED\n", __func__, psta->state);
+		return _FAIL;
+	}
+
+	ptxservq = rtw_get_sta_pending(padapter, psta, pattrib->priority, (u8 *)(&ac_index));
+
+	/* _enter_critical(&pstapending->lock, &irqL0); */
+
+	if (rtw_is_list_empty(&ptxservq->tx_pending))
+		rtw_list_insert_tail(&ptxservq->tx_pending, get_list_head(phwxmits[ac_index].sta_queue));
+
+	/* _enter_critical(&ptxservq->sta_pending.lock, &irqL1); */
+
+	rtw_list_insert_tail(&pxmitframe->list, get_list_head(&ptxservq->sta_pending));
+	ptxservq->qcnt++;
+	phwxmits[ac_index].accnt++;
+
+	/* _exit_critical(&ptxservq->sta_pending.lock, &irqL1); */
+
+	/* _exit_critical(&pstapending->lock, &irqL0); */
+
+exit:
+
+
+	return res;
+}
+
+void rtw_alloc_hwxmits(_adapter *padapter)
+{
+	struct hw_xmit *hwxmits;
+	struct xmit_priv *pxmitpriv = &padapter->xmitpriv;
+
+	pxmitpriv->hwxmit_entry = HWXMIT_ENTRY;
+
+	pxmitpriv->hwxmits = NULL;
+
+	pxmitpriv->hwxmits = (struct hw_xmit *)rtw_zmalloc(sizeof(struct hw_xmit) * pxmitpriv->hwxmit_entry);
+
+	if (pxmitpriv->hwxmits == NULL) {
+		RTW_INFO("alloc hwxmits fail!...\n");
+		return;
+	}
+
+	hwxmits = pxmitpriv->hwxmits;
+
+	if (pxmitpriv->hwxmit_entry == 5) {
+		/* pxmitpriv->bmc_txqueue.head = 0; */
+		/* hwxmits[0] .phwtxqueue = &pxmitpriv->bmc_txqueue; */
+		hwxmits[0] .sta_queue = &pxmitpriv->bm_pending;
+
+		/* pxmitpriv->vo_txqueue.head = 0; */
+		/* hwxmits[1] .phwtxqueue = &pxmitpriv->vo_txqueue; */
+		hwxmits[1] .sta_queue = &pxmitpriv->vo_pending;
+
+		/* pxmitpriv->vi_txqueue.head = 0; */
+		/* hwxmits[2] .phwtxqueue = &pxmitpriv->vi_txqueue; */
+		hwxmits[2] .sta_queue = &pxmitpriv->vi_pending;
+
+		/* pxmitpriv->bk_txqueue.head = 0; */
+		/* hwxmits[3] .phwtxqueue = &pxmitpriv->bk_txqueue; */
+		hwxmits[3] .sta_queue = &pxmitpriv->bk_pending;
+
+		/* pxmitpriv->be_txqueue.head = 0; */
+		/* hwxmits[4] .phwtxqueue = &pxmitpriv->be_txqueue; */
+		hwxmits[4] .sta_queue = &pxmitpriv->be_pending;
+
+	} else if (pxmitpriv->hwxmit_entry == 4) {
+
+		/* pxmitpriv->vo_txqueue.head = 0; */
+		/* hwxmits[0] .phwtxqueue = &pxmitpriv->vo_txqueue; */
+		hwxmits[0] .sta_queue = &pxmitpriv->vo_pending;
+
+		/* pxmitpriv->vi_txqueue.head = 0; */
+		/* hwxmits[1] .phwtxqueue = &pxmitpriv->vi_txqueue; */
+		hwxmits[1] .sta_queue = &pxmitpriv->vi_pending;
+
+		/* pxmitpriv->be_txqueue.head = 0; */
+		/* hwxmits[2] .phwtxqueue = &pxmitpriv->be_txqueue; */
+		hwxmits[2] .sta_queue = &pxmitpriv->be_pending;
+
+		/* pxmitpriv->bk_txqueue.head = 0; */
+		/* hwxmits[3] .phwtxqueue = &pxmitpriv->bk_txqueue; */
+		hwxmits[3] .sta_queue = &pxmitpriv->bk_pending;
+	} else {
+
+
+	}
+
+
+}
+
+void rtw_free_hwxmits(_adapter *padapter)
+{
+	struct hw_xmit *hwxmits;
+	struct xmit_priv *pxmitpriv = &padapter->xmitpriv;
+
+	hwxmits = pxmitpriv->hwxmits;
+	if (hwxmits)
+		rtw_mfree((u8 *)hwxmits, (sizeof(struct hw_xmit) * pxmitpriv->hwxmit_entry));
+}
+
+void rtw_init_hwxmits(struct hw_xmit *phwxmit, sint entry)
+{
+	sint i;
+	for (i = 0; i < entry; i++, phwxmit++) {
+		/* _rtw_spinlock_init(&phwxmit->xmit_lock); */
+		/* _rtw_init_listhead(&phwxmit->pending);		 */
+		/* phwxmit->txcmdcnt = 0; */
+		phwxmit->accnt = 0;
+	}
+}
+
+#ifdef CONFIG_BR_EXT
+int rtw_br_client_tx(_adapter *padapter, struct sk_buff **pskb)
+{
+	struct sk_buff *skb = *pskb;
+	_irqL irqL;
+	/* if(check_fwstate(pmlmepriv, WIFI_STATION_STATE|WIFI_ADHOC_STATE) == _TRUE) */
+	{
+		void dhcp_flag_bcast(_adapter *priv, struct sk_buff *skb);
+		int res, is_vlan_tag = 0, i, do_nat25 = 1;
+		unsigned short vlan_hdr = 0;
+		void *br_port = NULL;
+
+		/* mac_clone_handle_frame(priv, skb); */
+
+#if (LINUX_VERSION_CODE <= KERNEL_VERSION(2, 6, 35))
+		br_port = padapter->pnetdev->br_port;
+#else   /* (LINUX_VERSION_CODE <= KERNEL_VERSION(2, 6, 35)) */
+		rcu_read_lock();
+		br_port = rcu_dereference(padapter->pnetdev->rx_handler_data);
+		rcu_read_unlock();
+#endif /* (LINUX_VERSION_CODE <= KERNEL_VERSION(2, 6, 35)) */
+		_enter_critical_bh(&padapter->br_ext_lock, &irqL);
+		if (!(skb->data[0] & 1) &&
+		    br_port &&
+		    memcmp(skb->data + MACADDRLEN, padapter->br_mac, MACADDRLEN) &&
+		    *((unsigned short *)(skb->data + MACADDRLEN * 2)) != __constant_htons(ETH_P_8021Q) &&
+		    *((unsigned short *)(skb->data + MACADDRLEN * 2)) == __constant_htons(ETH_P_IP) &&
+		    !memcmp(padapter->scdb_mac, skb->data + MACADDRLEN, MACADDRLEN) && padapter->scdb_entry) {
+			memcpy(skb->data + MACADDRLEN, GET_MY_HWADDR(padapter), MACADDRLEN);
+			padapter->scdb_entry->ageing_timer = jiffies;
+			_exit_critical_bh(&padapter->br_ext_lock, &irqL);
+		} else
+			/* if (!priv->pmib->ethBrExtInfo.nat25_disable)		 */
+		{
+			/*			if (priv->dev->br_port &&
+			 *				 !memcmp(skb->data+MACADDRLEN, priv->br_mac, MACADDRLEN)) { */
+#if 1
+			if (*((unsigned short *)(skb->data + MACADDRLEN * 2)) == __constant_htons(ETH_P_8021Q)) {
+				is_vlan_tag = 1;
+				vlan_hdr = *((unsigned short *)(skb->data + MACADDRLEN * 2 + 2));
+				for (i = 0; i < 6; i++)
+					*((unsigned short *)(skb->data + MACADDRLEN * 2 + 2 - i * 2)) = *((unsigned short *)(skb->data + MACADDRLEN * 2 - 2 - i * 2));
+				skb_pull(skb, 4);
+			}
+			/* if SA == br_mac && skb== IP  => copy SIP to br_ip ?? why */
+			if (!memcmp(skb->data + MACADDRLEN, padapter->br_mac, MACADDRLEN) &&
+			    (*((unsigned short *)(skb->data + MACADDRLEN * 2)) == __constant_htons(ETH_P_IP)))
+				memcpy(padapter->br_ip, skb->data + WLAN_ETHHDR_LEN + 12, 4);
+
+			if (*((unsigned short *)(skb->data + MACADDRLEN * 2)) == __constant_htons(ETH_P_IP)) {
+				if (memcmp(padapter->scdb_mac, skb->data + MACADDRLEN, MACADDRLEN)) {
+					void *scdb_findEntry(_adapter *priv, unsigned char *macAddr, unsigned char *ipAddr);
+
+					padapter->scdb_entry = (struct nat25_network_db_entry *)scdb_findEntry(padapter,
+						skb->data + MACADDRLEN, skb->data + WLAN_ETHHDR_LEN + 12);
+					if (padapter->scdb_entry != NULL) {
+						memcpy(padapter->scdb_mac, skb->data + MACADDRLEN, MACADDRLEN);
+						memcpy(padapter->scdb_ip, skb->data + WLAN_ETHHDR_LEN + 12, 4);
+						padapter->scdb_entry->ageing_timer = jiffies;
+						do_nat25 = 0;
+					}
+				} else {
+					if (padapter->scdb_entry) {
+						padapter->scdb_entry->ageing_timer = jiffies;
+						do_nat25 = 0;
+					} else {
+						memset(padapter->scdb_mac, 0, MACADDRLEN);
+						memset(padapter->scdb_ip, 0, 4);
+					}
+				}
+			}
+			_exit_critical_bh(&padapter->br_ext_lock, &irqL);
+#endif /* 1 */
+			if (do_nat25) {
+				int nat25_db_handle(_adapter *priv, struct sk_buff *skb, int method);
+				if (nat25_db_handle(padapter, skb, NAT25_CHECK) == 0) {
+					struct sk_buff *newskb;
+
+					if (is_vlan_tag) {
+						skb_push(skb, 4);
+						for (i = 0; i < 6; i++)
+							*((unsigned short *)(skb->data + i * 2)) = *((unsigned short *)(skb->data + 4 + i * 2));
+						*((unsigned short *)(skb->data + MACADDRLEN * 2)) = __constant_htons(ETH_P_8021Q);
+						*((unsigned short *)(skb->data + MACADDRLEN * 2 + 2)) = vlan_hdr;
+					}
+
+					newskb = rtw_skb_copy(skb);
+					if (newskb == NULL) {
+						/* priv->ext_stats.tx_drops++; */
+						DEBUG_ERR("TX DROP: rtw_skb_copy fail!\n");
+						/* goto stop_proc; */
+						return -1;
+					}
+					rtw_skb_free(skb);
+
+					*pskb = skb = newskb;
+					if (is_vlan_tag) {
+						vlan_hdr = *((unsigned short *)(skb->data + MACADDRLEN * 2 + 2));
+						for (i = 0; i < 6; i++)
+							*((unsigned short *)(skb->data + MACADDRLEN * 2 + 2 - i * 2)) = *((unsigned short *)(skb->data + MACADDRLEN * 2 - 2 - i * 2));
+						skb_pull(skb, 4);
+					}
+				}
+
+				if (skb_is_nonlinear(skb))
+					DEBUG_ERR("%s(): skb_is_nonlinear!!\n", __FUNCTION__);
+
+
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 18))
+				res = skb_linearize(skb, GFP_ATOMIC);
+#else	/* (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 18)) */
+				res = skb_linearize(skb);
+#endif /* (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 18)) */
+				if (res < 0) {
+					DEBUG_ERR("TX DROP: skb_linearize fail!\n");
+					/* goto free_and_stop; */
+					return -1;
+				}
+
+				res = nat25_db_handle(padapter, skb, NAT25_INSERT);
+				if (res < 0) {
+					if (res == -2) {
+						/* priv->ext_stats.tx_drops++; */
+						DEBUG_ERR("TX DROP: nat25_db_handle fail!\n");
+						/* goto free_and_stop; */
+						return -1;
+
+					}
+					/* we just print warning message and let it go */
+					/* DEBUG_WARN("%s()-%d: nat25_db_handle INSERT Warning!\n", __FUNCTION__, __LINE__); */
+					/* return -1; */ /* return -1 will cause system crash on 2011/08/30! */
+					return 0;
+				}
+			}
+
+			memcpy(skb->data + MACADDRLEN, GET_MY_HWADDR(padapter), MACADDRLEN);
+
+			dhcp_flag_bcast(padapter, skb);
+
+			if (is_vlan_tag) {
+				skb_push(skb, 4);
+				for (i = 0; i < 6; i++)
+					*((unsigned short *)(skb->data + i * 2)) = *((unsigned short *)(skb->data + 4 + i * 2));
+				*((unsigned short *)(skb->data + MACADDRLEN * 2)) = __constant_htons(ETH_P_8021Q);
+				*((unsigned short *)(skb->data + MACADDRLEN * 2 + 2)) = vlan_hdr;
+			}
+		}
+#if 0
+		else {
+			if (*((unsigned short *)(skb->data + MACADDRLEN * 2)) == __constant_htons(ETH_P_8021Q))
+				is_vlan_tag = 1;
+
+			if (is_vlan_tag) {
+				if (ICMPV6_MCAST_MAC(skb->data) && ICMPV6_PROTO1A_VALN(skb->data))
+					memcpy(skb->data + MACADDRLEN, GET_MY_HWADDR(padapter), MACADDRLEN);
+			} else {
+				if (ICMPV6_MCAST_MAC(skb->data) && ICMPV6_PROTO1A(skb->data))
+					memcpy(skb->data + MACADDRLEN, GET_MY_HWADDR(padapter), MACADDRLEN);
+			}
+		}
+#endif /* 0 */
+
+		/* check if SA is equal to our MAC */
+		if (memcmp(skb->data + MACADDRLEN, GET_MY_HWADDR(padapter), MACADDRLEN)) {
+			/* priv->ext_stats.tx_drops++; */
+			DEBUG_ERR("TX DROP: untransformed frame SA:%02X%02X%02X%02X%02X%02X!\n",
+				skb->data[6], skb->data[7], skb->data[8], skb->data[9], skb->data[10], skb->data[11]);
+			/* goto free_and_stop; */
+			return -1;
+		}
+	}
+	return 0;
+}
+#endif /* CONFIG_BR_EXT */
+
+u32 rtw_get_ff_hwaddr(struct xmit_frame *pxmitframe)
+{
+	u32 addr;
+	struct pkt_attrib *pattrib = &pxmitframe->attrib;
+
+	switch (pattrib->qsel) {
+	case 0:
+	case 3:
+		addr = BE_QUEUE_INX;
+		break;
+	case 1:
+	case 2:
+		addr = BK_QUEUE_INX;
+		break;
+	case 4:
+	case 5:
+		addr = VI_QUEUE_INX;
+		break;
+	case 6:
+	case 7:
+		addr = VO_QUEUE_INX;
+		break;
+	case 0x10:
+		addr = BCN_QUEUE_INX;
+		break;
+	case 0x11: /* BC/MC in PS (HIQ) */
+		addr = HIGH_QUEUE_INX;
+		break;
+	case 0x13:
+		addr = TXCMD_QUEUE_INX;
+		break;
+	case 0x12:
+	default:
+		addr = MGT_QUEUE_INX;
+		break;
+
+	}
+
+	return addr;
+
+}
+
+static void do_queue_select(_adapter	*padapter, struct pkt_attrib *pattrib)
+{
+	u8 qsel;
+
+	qsel = pattrib->priority;
+
+#ifdef CONFIG_MCC_MODE
+	if (MCC_EN(padapter)) {
+		/* Under MCC */
+		if (rtw_hal_check_mcc_status(padapter, MCC_STATUS_NEED_MCC)) {
+			if (padapter->mcc_adapterpriv.role == MCC_ROLE_GO
+			    || padapter->mcc_adapterpriv.role == MCC_ROLE_AP) {
+				pattrib->qsel = QSLT_VO; /* AP interface VO queue */
+			} else {
+				pattrib->qsel = QSLT_BE; /* STA interface BE queue */
+			}
+		} else
+			/* Not Under MCC */
+			pattrib->qsel = qsel;
+	} else
+		/* Not enable MCC */
+		pattrib->qsel = qsel;
+#else /* !CONFIG_MCC_MODE */
+	pattrib->qsel = qsel;
+#endif /* CONFIG_MCC_MODE */
+}
+
+/*
+ * The main transmit(tx) entry
+ *
+ * Return
+ *	1	enqueue
+ *	0	success, hardware will handle this xmit frame(packet)
+ *	<0	fail
+ */
+ #if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 24))
+s32 rtw_monitor_xmit_entry(struct sk_buff *skb, struct net_device *ndev)
+{
+	u16 frame_ctl;
+	struct ieee80211_radiotap_header rtap_hdr;
+	_adapter *padapter = (_adapter *)rtw_netdev_priv(ndev);
+	struct pkt_file pktfile;
+	struct rtw_ieee80211_hdr *pwlanhdr;
+	struct pkt_attrib	*pattrib;
+	struct xmit_frame		*pmgntframe;
+	struct mlme_ext_priv	*pmlmeext = &(padapter->mlmeextpriv);
+	struct xmit_priv	*pxmitpriv = &(padapter->xmitpriv);
+	unsigned char	*pframe;
+	u8 dummybuf[32];
+	int len = skb->len, rtap_len;
+
+	if (skb)
+		rtw_mstat_update(MSTAT_TYPE_SKB, MSTAT_ALLOC_SUCCESS, skb->truesize);
+
+	if (unlikely(skb->len < sizeof(struct ieee80211_radiotap_header)))
+		goto fail;
+
+	_rtw_open_pktfile((_pkt *)skb, &pktfile);
+	_rtw_pktfile_read(&pktfile, (u8 *)(&rtap_hdr), sizeof(struct ieee80211_radiotap_header));
+	rtap_len = ieee80211_get_radiotap_len((u8 *)(&rtap_hdr));
+	if (unlikely(rtap_hdr.it_version))
+		goto fail;
+
+	if (unlikely(skb->len < rtap_len))
+		goto fail;
+
+	if (rtap_len != 12) {
+		RTW_INFO("radiotap len (should be 14): %d\n", rtap_len);
+		goto fail;
+	}
+	_rtw_pktfile_read(&pktfile, dummybuf, rtap_len-sizeof(struct ieee80211_radiotap_header));
+	len = len - rtap_len;
+
+	pmgntframe = alloc_mgtxmitframe(pxmitpriv);
+	if (pmgntframe == NULL) {
+		rtw_udelay_os(500);
+		goto fail;
+	}
+
+	_rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET);
+	pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET;
+//	_rtw_memcpy(pframe, (void *)checking, len);
+	_rtw_pktfile_read(&pktfile, pframe, len);
+
+
+	/* Check DATA/MGNT frames */
+	pwlanhdr = (struct rtw_ieee80211_hdr *)pframe;
+	frame_ctl = le16_to_cpu(pwlanhdr->frame_ctl);
+	if ((frame_ctl & RTW_IEEE80211_FCTL_FTYPE) == RTW_IEEE80211_FTYPE_DATA) {
+
+		pattrib = &pmgntframe->attrib;
+		update_monitor_frame_attrib(padapter, pattrib);
+
+		if (is_broadcast_mac_addr(pwlanhdr->addr3) || is_broadcast_mac_addr(pwlanhdr->addr1))
+			pattrib->rate = MGN_24M;
+
+	} else {
+
+		pattrib = &pmgntframe->attrib;
+		update_mgntframe_attrib(padapter, pattrib);
+
+	}
+	pattrib->retry_ctrl = _FALSE;
+	pattrib->pktlen = len;
+	pmlmeext->mgnt_seq = GetSequence(pwlanhdr);
+	pattrib->seqnum = pmlmeext->mgnt_seq;
+	pmlmeext->mgnt_seq++;
+	pattrib->last_txcmdsz = pattrib->pktlen;
+
+	dump_mgntframe(padapter, pmgntframe);
+
+fail:
+	rtw_endofpktfile(&pktfile);
+	rtw_skb_free(skb);
+	return 0;
+}
+#endif
+
+/*
+ * The main transmit(tx) entry post handle
+ *
+ * Return
+ *	1	enqueue
+ *	0	success, hardware will handle this xmit frame(packet)
+ *	<0	fail
+ */
+s32 rtw_xmit_posthandle(_adapter *padapter, struct xmit_frame *pxmitframe, _pkt *pkt)
+{
+#ifdef CONFIG_AP_MODE
+	_irqL irqL0;
+#endif
+	struct xmit_priv *pxmitpriv = &padapter->xmitpriv;
+	s32 res;
+
+	res = update_attrib(padapter, pkt, &pxmitframe->attrib);
+
+#ifdef CONFIG_MCC_MODE
+	/* record data kernel TX to driver to check MCC concurrent TX */
+	rtw_hal_mcc_calc_tx_bytes_from_kernel(padapter, pxmitframe->attrib.pktlen);
+#endif /* CONFIG_MCC_MODE */
+
+#ifdef CONFIG_WAPI_SUPPORT
+	if (pxmitframe->attrib.ether_type != 0x88B4) {
+		if (rtw_wapi_drop_for_key_absent(padapter, pxmitframe->attrib.ra)) {
+			WAPI_TRACE(WAPI_RX, "drop for key absend when tx\n");
+			res = _FAIL;
+		}
+	}
+#endif
+	if (res == _FAIL) {
+		/*RTW_INFO("%s-"ADPT_FMT" update attrib fail\n", __func__, ADPT_ARG(padapter));*/
+#ifdef DBG_TX_DROP_FRAME
+		RTW_INFO("DBG_TX_DROP_FRAME %s update attrib fail\n", __FUNCTION__);
+#endif
+		rtw_free_xmitframe(pxmitpriv, pxmitframe);
+		return -1;
+	}
+	pxmitframe->pkt = pkt;
+
+	rtw_led_tx_control(padapter, pxmitframe->attrib.dst);
+
+	do_queue_select(padapter, &pxmitframe->attrib);
+
+#ifdef CONFIG_AP_MODE
+	_enter_critical_bh(&pxmitpriv->lock, &irqL0);
+	if (xmitframe_enqueue_for_sleeping_sta(padapter, pxmitframe) == _TRUE) {
+		_exit_critical_bh(&pxmitpriv->lock, &irqL0);
+		DBG_COUNTER(padapter->tx_logs.core_tx_ap_enqueue);
+		return 1;
+	}
+	_exit_critical_bh(&pxmitpriv->lock, &irqL0);
+#endif
+
+	/* pre_xmitframe */
+	if (rtw_hal_xmit(padapter, pxmitframe) == _FALSE)
+		return 1;
+
+	return 0;
+}
+
+/*
+ * The main transmit(tx) entry
+ *
+ * Return
+ *	1	enqueue
+ *	0	success, hardware will handle this xmit frame(packet)
+ *	<0	fail
+ */
+s32 rtw_xmit(_adapter *padapter, _pkt **ppkt)
+{
+	static systime start = 0;
+	static u32 drop_cnt = 0;
+	struct xmit_priv *pxmitpriv = &padapter->xmitpriv;
+	struct xmit_frame *pxmitframe = NULL;
+	s32 res;
+
+	DBG_COUNTER(padapter->tx_logs.core_tx);
+
+	if (IS_CH_WAITING(adapter_to_rfctl(padapter)))
+		return -1;
+
+	if (rtw_linked_check(padapter) == _FALSE)
+		return -1;
+
+	if (start == 0)
+		start = rtw_get_current_time();
+
+	pxmitframe = rtw_alloc_xmitframe(pxmitpriv);
+
+	if (rtw_get_passing_time_ms(start) > 2000) {
+		if (drop_cnt)
+			RTW_INFO("DBG_TX_DROP_FRAME %s no more pxmitframe, drop_cnt:%u\n", __FUNCTION__, drop_cnt);
+		start = rtw_get_current_time();
+		drop_cnt = 0;
+	}
+
+	if (pxmitframe == NULL) {
+		drop_cnt++;
+		/*RTW_INFO("%s-"ADPT_FMT" no more xmitframe\n", __func__, ADPT_ARG(padapter));*/
+		DBG_COUNTER(padapter->tx_logs.core_tx_err_pxmitframe);
+		return -1;
+	}
+
+#ifdef CONFIG_BR_EXT
+	if (check_fwstate(&padapter->mlmepriv, WIFI_STATION_STATE | WIFI_ADHOC_STATE) == _TRUE) {
+		void *br_port = NULL;
+
+		#if (LINUX_VERSION_CODE <= KERNEL_VERSION(2, 6, 35))
+		br_port = padapter->pnetdev->br_port;
+		#else
+		rcu_read_lock();
+		br_port = rcu_dereference(padapter->pnetdev->rx_handler_data);
+		rcu_read_unlock();
+		#endif
+
+		if (br_port) {
+			res = rtw_br_client_tx(padapter, ppkt);
+			if (res == -1) {
+				rtw_free_xmitframe(pxmitpriv, pxmitframe);
+				DBG_COUNTER(padapter->tx_logs.core_tx_err_brtx);
+				return -1;
+			}
+		}
+	}
+#endif /* CONFIG_BR_EXT */
+
+#ifdef CONFIG_RTW_MESH
+	if (MLME_IS_MESH(padapter)) {
+		_list b2u_list;
+
+		res = rtw_mesh_addr_resolve(padapter, pxmitframe, *ppkt, &b2u_list);
+		if (res == RTW_RA_RESOLVING)
+			return 1;
+		if (res == _FAIL)
+			return -1;
+
+		#if CONFIG_RTW_MESH_DATA_BMC_TO_UC
+		if (!rtw_is_list_empty(&b2u_list)) {
+			_list *list = get_next(&b2u_list);
+			struct xmit_frame *b2uframe;
+
+			while ((rtw_end_of_queue_search(&b2u_list, list)) == _FALSE) {
+				b2uframe = LIST_CONTAINOR(list, struct xmit_frame, list);
+				list = get_next(list);
+				rtw_list_delete(&b2uframe->list);
+
+				b2uframe->pkt = rtw_os_pkt_copy(*ppkt);
+				if (!b2uframe->pkt) {
+					if (res == RTW_BMC_NO_NEED)
+						res = _SUCCESS;
+					rtw_free_xmitframe(pxmitpriv, b2uframe);
+					continue;
+				}
+
+				rtw_xmit_posthandle(padapter, b2uframe, b2uframe->pkt);
+			}
+		}
+		#endif /* CONFIG_RTW_MESH_DATA_BMC_TO_UC */
+
+		if (res == RTW_BMC_NO_NEED) {
+			rtw_free_xmitframe(&padapter->xmitpriv, pxmitframe);
+			return 0;
+		}
+	}
+#endif /* CONFIG_RTW_MESH */
+
+	pxmitframe->pkt = NULL; /* let rtw_xmit_posthandle not to free pkt inside */
+	res = rtw_xmit_posthandle(padapter, pxmitframe, *ppkt);
+
+	return res;
+}
+
+#ifdef CONFIG_TDLS
+sint xmitframe_enqueue_for_tdls_sleeping_sta(_adapter *padapter, struct xmit_frame *pxmitframe)
+{
+	sint ret = _FALSE;
+
+	_irqL irqL;
+	struct sta_info *ptdls_sta = NULL;
+	struct sta_priv *pstapriv = &padapter->stapriv;
+	struct pkt_attrib *pattrib = &pxmitframe->attrib;
+	struct mlme_ext_priv	*pmlmeext = &(padapter->mlmeextpriv);
+	int i;
+
+	ptdls_sta = rtw_get_stainfo(pstapriv, pattrib->dst);
+	if (ptdls_sta == NULL)
+		return ret;
+	else if (ptdls_sta->tdls_sta_state & TDLS_LINKED_STATE) {
+
+		if (pattrib->triggered == 1) {
+			ret = _TRUE;
+			return ret;
+		}
+
+		_enter_critical_bh(&ptdls_sta->sleep_q.lock, &irqL);
+
+		if (ptdls_sta->state & WIFI_SLEEP_STATE) {
+			rtw_list_delete(&pxmitframe->list);
+
+			/* _enter_critical_bh(&psta->sleep_q.lock, &irqL);	 */
+
+			rtw_list_insert_tail(&pxmitframe->list, get_list_head(&ptdls_sta->sleep_q));
+
+			ptdls_sta->sleepq_len++;
+			ptdls_sta->sleepq_ac_len++;
+
+			/* indicate 4-AC queue bit in TDLS peer traffic indication */
+			switch (pattrib->priority) {
+			case 1:
+			case 2:
+				ptdls_sta->uapsd_bk |= BIT(1);
+				break;
+			case 4:
+			case 5:
+				ptdls_sta->uapsd_vi |= BIT(1);
+				break;
+			case 6:
+			case 7:
+				ptdls_sta->uapsd_vo |= BIT(1);
+				break;
+			case 0:
+			case 3:
+			default:
+				ptdls_sta->uapsd_be |= BIT(1);
+				break;
+			}
+
+			/* Transmit TDLS PTI via AP */
+			if (ptdls_sta->sleepq_len == 1)
+				rtw_tdls_cmd(padapter, ptdls_sta->cmn.mac_addr, TDLS_ISSUE_PTI);
+
+			ret = _TRUE;
+		}
+
+		_exit_critical_bh(&ptdls_sta->sleep_q.lock, &irqL);
+	}
+
+	return ret;
+
+}
+#endif /* CONFIG_TDLS */
+
+#define RTW_HIQ_FILTER_ALLOW_ALL 0
+#define RTW_HIQ_FILTER_ALLOW_SPECIAL 1
+#define RTW_HIQ_FILTER_DENY_ALL 2
+
+inline bool xmitframe_hiq_filter(struct xmit_frame *xmitframe)
+{
+	bool allow = _FALSE;
+	_adapter *adapter = xmitframe->padapter;
+	struct registry_priv *registry = &adapter->registrypriv;
+
+	if (adapter->registrypriv.wifi_spec == 1)
+		allow = _TRUE;
+	else if (registry->hiq_filter == RTW_HIQ_FILTER_ALLOW_SPECIAL) {
+
+		struct pkt_attrib *attrib = &xmitframe->attrib;
+
+		if (attrib->ether_type == 0x0806
+		    || attrib->ether_type == 0x888e
+#ifdef CONFIG_WAPI_SUPPORT
+		    || attrib->ether_type == 0x88B4
+#endif
+		    || attrib->dhcp_pkt
+		   ) {
+			if (0)
+				RTW_INFO(FUNC_ADPT_FMT" ether_type:0x%04x%s\n", FUNC_ADPT_ARG(xmitframe->padapter)
+					, attrib->ether_type, attrib->dhcp_pkt ? " DHCP" : "");
+			allow = _TRUE;
+		}
+	} else if (registry->hiq_filter == RTW_HIQ_FILTER_ALLOW_ALL)
+		allow = _TRUE;
+	else if (registry->hiq_filter == RTW_HIQ_FILTER_DENY_ALL)
+		allow = _FALSE;
+	else
+		rtw_warn_on(1);
+
+	return allow;
+}
+
+#if defined(CONFIG_AP_MODE) || defined(CONFIG_TDLS)
+
+sint xmitframe_enqueue_for_sleeping_sta(_adapter *padapter, struct xmit_frame *pxmitframe)
+{
+	_irqL irqL;
+	sint ret = _FALSE;
+	struct sta_info *psta = NULL;
+	struct sta_priv *pstapriv = &padapter->stapriv;
+	struct pkt_attrib *pattrib = &pxmitframe->attrib;
+	sint bmcst = IS_MCAST(pattrib->ra);
+	bool update_tim = _FALSE;
+#ifdef CONFIG_TDLS
+
+	if (padapter->tdlsinfo.link_established == _TRUE)
+		ret = xmitframe_enqueue_for_tdls_sleeping_sta(padapter, pxmitframe);
+#endif /* CONFIG_TDLS */
+
+	if (!MLME_IS_AP(padapter) && !MLME_IS_MESH(padapter)) {
+		DBG_COUNTER(padapter->tx_logs.core_tx_ap_enqueue_warn_fwstate);
+		return ret;
+	}
+	/*
+		if(pattrib->psta)
+		{
+			psta = pattrib->psta;
+		}
+		else
+		{
+			RTW_INFO("%s, call rtw_get_stainfo()\n", __func__);
+			psta=rtw_get_stainfo(pstapriv, pattrib->ra);
+		}
+	*/
+	psta = rtw_get_stainfo(&padapter->stapriv, pattrib->ra);
+	if (pattrib->psta != psta) {
+		DBG_COUNTER(padapter->tx_logs.core_tx_ap_enqueue_warn_sta);
+		RTW_INFO("%s, pattrib->psta(%p) != psta(%p)\n", __func__, pattrib->psta, psta);
+		return _FALSE;
+	}
+
+	if (psta == NULL) {
+		DBG_COUNTER(padapter->tx_logs.core_tx_ap_enqueue_warn_nosta);
+		RTW_INFO("%s, psta==NUL\n", __func__);
+		return _FALSE;
+	}
+
+	if (!(psta->state & _FW_LINKED)) {
+		DBG_COUNTER(padapter->tx_logs.core_tx_ap_enqueue_warn_link);
+		RTW_INFO("%s, psta->state(0x%x) != _FW_LINKED\n", __func__, psta->state);
+		return _FALSE;
+	}
+
+	if (pattrib->triggered == 1) {
+		DBG_COUNTER(padapter->tx_logs.core_tx_ap_enqueue_warn_trigger);
+		/* RTW_INFO("directly xmit pspoll_triggered packet\n"); */
+
+		/* pattrib->triggered=0; */
+		if (bmcst && xmitframe_hiq_filter(pxmitframe) == _TRUE)
+			pattrib->qsel = QSLT_HIGH;/* HIQ */
+
+		return ret;
+	}
+
+
+	if (bmcst) {
+		_enter_critical_bh(&psta->sleep_q.lock, &irqL);
+
+		if (rtw_tim_map_anyone_be_set(padapter, pstapriv->sta_dz_bitmap)) { /* if anyone sta is in ps mode */
+			/* pattrib->qsel = QSLT_HIGH; */ /* HIQ */
+
+			rtw_list_delete(&pxmitframe->list);
+
+			/*_enter_critical_bh(&psta->sleep_q.lock, &irqL);*/
+
+			rtw_list_insert_tail(&pxmitframe->list, get_list_head(&psta->sleep_q));
+
+			psta->sleepq_len++;
+
+			if (!(rtw_tim_map_is_set(padapter, pstapriv->tim_bitmap, 0)))
+				update_tim = _TRUE;
+
+			rtw_tim_map_set(padapter, pstapriv->tim_bitmap, 0);
+			rtw_tim_map_set(padapter, pstapriv->sta_dz_bitmap, 0);
+
+			/* RTW_INFO("enqueue, sq_len=%d\n", psta->sleepq_len); */
+			/* RTW_INFO_DUMP("enqueue, tim=", pstapriv->tim_bitmap, pstapriv->aid_bmp_len); */
+			if (update_tim == _TRUE) {
+				if (is_broadcast_mac_addr(pattrib->ra))
+					_update_beacon(padapter, _TIM_IE_, NULL, _TRUE, "buffer BC");
+				else
+					_update_beacon(padapter, _TIM_IE_, NULL, _TRUE, "buffer MC");
+			} else
+				chk_bmc_sleepq_cmd(padapter);
+
+			/*_exit_critical_bh(&psta->sleep_q.lock, &irqL);*/
+
+			ret = _TRUE;
+
+			DBG_COUNTER(padapter->tx_logs.core_tx_ap_enqueue_mcast);
+		}
+
+		_exit_critical_bh(&psta->sleep_q.lock, &irqL);
+
+		return ret;
+
+	}
+
+
+	_enter_critical_bh(&psta->sleep_q.lock, &irqL);
+
+	if (psta->state & WIFI_SLEEP_STATE) {
+		u8 wmmps_ac = 0;
+
+		if (rtw_tim_map_is_set(padapter, pstapriv->sta_dz_bitmap, psta->cmn.aid)) {
+			rtw_list_delete(&pxmitframe->list);
+
+			/* _enter_critical_bh(&psta->sleep_q.lock, &irqL);	 */
+
+			rtw_list_insert_tail(&pxmitframe->list, get_list_head(&psta->sleep_q));
+
+			psta->sleepq_len++;
+
+			switch (pattrib->priority) {
+			case 1:
+			case 2:
+				wmmps_ac = psta->uapsd_bk & BIT(0);
+				break;
+			case 4:
+			case 5:
+				wmmps_ac = psta->uapsd_vi & BIT(0);
+				break;
+			case 6:
+			case 7:
+				wmmps_ac = psta->uapsd_vo & BIT(0);
+				break;
+			case 0:
+			case 3:
+			default:
+				wmmps_ac = psta->uapsd_be & BIT(0);
+				break;
+			}
+
+			if (wmmps_ac)
+				psta->sleepq_ac_len++;
+
+			if (((psta->has_legacy_ac) && (!wmmps_ac)) || ((!psta->has_legacy_ac) && (wmmps_ac))) {
+				if (!(rtw_tim_map_is_set(padapter, pstapriv->tim_bitmap, psta->cmn.aid)))
+					update_tim = _TRUE;
+
+				rtw_tim_map_set(padapter, pstapriv->tim_bitmap, psta->cmn.aid);
+
+				/* RTW_INFO("enqueue, sq_len=%d\n", psta->sleepq_len); */
+				/* RTW_INFO_DUMP("enqueue, tim=", pstapriv->tim_bitmap, pstapriv->aid_bmp_len); */
+
+				if (update_tim == _TRUE) {
+					/* RTW_INFO("sleepq_len==1, update BCNTIM\n"); */
+					/* upate BCN for TIM IE */
+					_update_beacon(padapter, _TIM_IE_, NULL, _TRUE, "buffer UC");
+				}
+			}
+
+			/* _exit_critical_bh(&psta->sleep_q.lock, &irqL);			 */
+
+			/* if(psta->sleepq_len > (NR_XMITFRAME>>3)) */
+			/* { */
+			/*	wakeup_sta_to_xmit(padapter, psta); */
+			/* }	 */
+
+			ret = _TRUE;
+
+			DBG_COUNTER(padapter->tx_logs.core_tx_ap_enqueue_ucast);
+		}
+
+	}
+
+	_exit_critical_bh(&psta->sleep_q.lock, &irqL);
+
+	return ret;
+
+}
+
+static void dequeue_xmitframes_to_sleeping_queue(_adapter *padapter, struct sta_info *psta, _queue *pframequeue)
+{
+	sint ret;
+	_list	*plist, *phead;
+	u8	ac_index;
+	struct tx_servq	*ptxservq;
+	struct pkt_attrib	*pattrib;
+	struct xmit_frame	*pxmitframe;
+	struct hw_xmit *phwxmits =  padapter->xmitpriv.hwxmits;
+
+	phead = get_list_head(pframequeue);
+	plist = get_next(phead);
+
+	while (rtw_end_of_queue_search(phead, plist) == _FALSE) {
+		pxmitframe = LIST_CONTAINOR(plist, struct xmit_frame, list);
+
+		plist = get_next(plist);
+
+		pattrib = &pxmitframe->attrib;
+
+		pattrib->triggered = 0;
+
+		ret = xmitframe_enqueue_for_sleeping_sta(padapter, pxmitframe);
+
+		if (_TRUE == ret) {
+			ptxservq = rtw_get_sta_pending(padapter, psta, pattrib->priority, (u8 *)(&ac_index));
+
+			ptxservq->qcnt--;
+			phwxmits[ac_index].accnt--;
+		} else {
+			/* RTW_INFO("xmitframe_enqueue_for_sleeping_sta return _FALSE\n"); */
+		}
+
+	}
+
+}
+
+void stop_sta_xmit(_adapter *padapter, struct sta_info *psta)
+{
+	_irqL irqL0;
+	struct sta_info *psta_bmc;
+	struct sta_xmit_priv *pstaxmitpriv;
+	struct sta_priv *pstapriv = &padapter->stapriv;
+	struct xmit_priv *pxmitpriv = &padapter->xmitpriv;
+
+	pstaxmitpriv = &psta->sta_xmitpriv;
+
+	/* for BC/MC Frames */
+	psta_bmc = rtw_get_bcmc_stainfo(padapter);
+
+
+	_enter_critical_bh(&pxmitpriv->lock, &irqL0);
+
+	psta->state |= WIFI_SLEEP_STATE;
+
+#ifdef CONFIG_TDLS
+	if (!(psta->tdls_sta_state & TDLS_LINKED_STATE))
+#endif /* CONFIG_TDLS */
+		rtw_tim_map_set(padapter, pstapriv->sta_dz_bitmap, psta->cmn.aid);
+
+	dequeue_xmitframes_to_sleeping_queue(padapter, psta, &pstaxmitpriv->vo_q.sta_pending);
+	rtw_list_delete(&(pstaxmitpriv->vo_q.tx_pending));
+	dequeue_xmitframes_to_sleeping_queue(padapter, psta, &pstaxmitpriv->vi_q.sta_pending);
+	rtw_list_delete(&(pstaxmitpriv->vi_q.tx_pending));
+	dequeue_xmitframes_to_sleeping_queue(padapter, psta, &pstaxmitpriv->be_q.sta_pending);
+	rtw_list_delete(&(pstaxmitpriv->be_q.tx_pending));
+	dequeue_xmitframes_to_sleeping_queue(padapter, psta, &pstaxmitpriv->bk_q.sta_pending);
+	rtw_list_delete(&(pstaxmitpriv->bk_q.tx_pending));
+
+#ifdef CONFIG_TDLS
+	if (!(psta->tdls_sta_state & TDLS_LINKED_STATE) && (psta_bmc != NULL)) {
+#endif /* CONFIG_TDLS */
+
+		/* for BC/MC Frames */
+		pstaxmitpriv = &psta_bmc->sta_xmitpriv;
+		dequeue_xmitframes_to_sleeping_queue(padapter, psta_bmc, &pstaxmitpriv->vo_q.sta_pending);
+		rtw_list_delete(&(pstaxmitpriv->vo_q.tx_pending));
+		dequeue_xmitframes_to_sleeping_queue(padapter, psta_bmc, &pstaxmitpriv->vi_q.sta_pending);
+		rtw_list_delete(&(pstaxmitpriv->vi_q.tx_pending));
+		dequeue_xmitframes_to_sleeping_queue(padapter, psta_bmc, &pstaxmitpriv->be_q.sta_pending);
+		rtw_list_delete(&(pstaxmitpriv->be_q.tx_pending));
+		dequeue_xmitframes_to_sleeping_queue(padapter, psta_bmc, &pstaxmitpriv->bk_q.sta_pending);
+		rtw_list_delete(&(pstaxmitpriv->bk_q.tx_pending));
+
+#ifdef CONFIG_TDLS
+	}
+#endif /* CONFIG_TDLS	 */
+	_exit_critical_bh(&pxmitpriv->lock, &irqL0);
+
+
+}
+
+void wakeup_sta_to_xmit(_adapter *padapter, struct sta_info *psta)
+{
+	_irqL irqL;
+	u8 update_mask = 0, wmmps_ac = 0;
+	struct sta_info *psta_bmc;
+	_list	*xmitframe_plist, *xmitframe_phead;
+	struct xmit_frame *pxmitframe = NULL;
+	struct sta_priv *pstapriv = &padapter->stapriv;
+	struct xmit_priv *pxmitpriv = &padapter->xmitpriv;
+
+	psta_bmc = rtw_get_bcmc_stainfo(padapter);
+
+
+	/* _enter_critical_bh(&psta->sleep_q.lock, &irqL); */
+	_enter_critical_bh(&pxmitpriv->lock, &irqL);
+
+	xmitframe_phead = get_list_head(&psta->sleep_q);
+	xmitframe_plist = get_next(xmitframe_phead);
+
+	while ((rtw_end_of_queue_search(xmitframe_phead, xmitframe_plist)) == _FALSE) {
+		pxmitframe = LIST_CONTAINOR(xmitframe_plist, struct xmit_frame, list);
+
+		xmitframe_plist = get_next(xmitframe_plist);
+
+		rtw_list_delete(&pxmitframe->list);
+
+		switch (pxmitframe->attrib.priority) {
+		case 1:
+		case 2:
+			wmmps_ac = psta->uapsd_bk & BIT(1);
+			break;
+		case 4:
+		case 5:
+			wmmps_ac = psta->uapsd_vi & BIT(1);
+			break;
+		case 6:
+		case 7:
+			wmmps_ac = psta->uapsd_vo & BIT(1);
+			break;
+		case 0:
+		case 3:
+		default:
+			wmmps_ac = psta->uapsd_be & BIT(1);
+			break;
+		}
+
+		psta->sleepq_len--;
+		if (psta->sleepq_len > 0)
+			pxmitframe->attrib.mdata = 1;
+		else
+			pxmitframe->attrib.mdata = 0;
+
+		if (wmmps_ac) {
+			psta->sleepq_ac_len--;
+			if (psta->sleepq_ac_len > 0) {
+				pxmitframe->attrib.mdata = 1;
+				pxmitframe->attrib.eosp = 0;
+			} else {
+				pxmitframe->attrib.mdata = 0;
+				pxmitframe->attrib.eosp = 1;
+			}
+		}
+
+		pxmitframe->attrib.triggered = 1;
+
+		/*
+				_exit_critical_bh(&psta->sleep_q.lock, &irqL);
+				if(rtw_hal_xmit(padapter, pxmitframe) == _TRUE)
+				{
+					rtw_os_xmit_complete(padapter, pxmitframe);
+				}
+				_enter_critical_bh(&psta->sleep_q.lock, &irqL);
+		*/
+		rtw_hal_xmitframe_enqueue(padapter, pxmitframe);
+
+
+	}
+
+	if (psta->sleepq_len == 0) {
+#ifdef CONFIG_TDLS
+		if (psta->tdls_sta_state & TDLS_LINKED_STATE) {
+			if (psta->state & WIFI_SLEEP_STATE)
+				psta->state ^= WIFI_SLEEP_STATE;
+
+			_exit_critical_bh(&pxmitpriv->lock, &irqL);
+			return;
+		}
+#endif /* CONFIG_TDLS */
+
+		if (rtw_tim_map_is_set(padapter, pstapriv->tim_bitmap, psta->cmn.aid)) {
+			/* RTW_INFO("wakeup to xmit, qlen==0\n"); */
+			/* RTW_INFO_DUMP("update_BCNTIM, tim=", pstapriv->tim_bitmap, pstapriv->aid_bmp_len); */
+			/* upate BCN for TIM IE */
+			/* update_BCNTIM(padapter); */
+			update_mask = BIT(0);
+		}
+
+		rtw_tim_map_clear(padapter, pstapriv->tim_bitmap, psta->cmn.aid);
+
+		if (psta->state & WIFI_SLEEP_STATE)
+			psta->state ^= WIFI_SLEEP_STATE;
+
+		if (psta->state & WIFI_STA_ALIVE_CHK_STATE) {
+			RTW_INFO("%s alive check\n", __func__);
+			psta->expire_to = pstapriv->expire_to;
+			psta->state ^= WIFI_STA_ALIVE_CHK_STATE;
+		}
+
+		rtw_tim_map_clear(padapter, pstapriv->sta_dz_bitmap, psta->cmn.aid);
+	}
+
+	/* for BC/MC Frames */
+	if (!psta_bmc)
+		goto _exit;
+
+	if (!(rtw_tim_map_anyone_be_set_exclude_aid0(padapter, pstapriv->sta_dz_bitmap))) { /* no any sta in ps mode */
+		xmitframe_phead = get_list_head(&psta_bmc->sleep_q);
+		xmitframe_plist = get_next(xmitframe_phead);
+
+		while ((rtw_end_of_queue_search(xmitframe_phead, xmitframe_plist)) == _FALSE) {
+			pxmitframe = LIST_CONTAINOR(xmitframe_plist, struct xmit_frame, list);
+
+			xmitframe_plist = get_next(xmitframe_plist);
+
+			rtw_list_delete(&pxmitframe->list);
+
+			psta_bmc->sleepq_len--;
+			if (psta_bmc->sleepq_len > 0)
+				pxmitframe->attrib.mdata = 1;
+			else
+				pxmitframe->attrib.mdata = 0;
+
+
+			pxmitframe->attrib.triggered = 1;
+			/*
+						_exit_critical_bh(&psta_bmc->sleep_q.lock, &irqL);
+						if(rtw_hal_xmit(padapter, pxmitframe) == _TRUE)
+						{
+							rtw_os_xmit_complete(padapter, pxmitframe);
+						}
+						_enter_critical_bh(&psta_bmc->sleep_q.lock, &irqL);
+
+			*/
+			rtw_hal_xmitframe_enqueue(padapter, pxmitframe);
+
+		}
+
+		if (psta_bmc->sleepq_len == 0) {
+			if (rtw_tim_map_is_set(padapter, pstapriv->tim_bitmap, 0)) {
+				/* RTW_INFO("wakeup to xmit, qlen==0\n"); */
+				/* RTW_INFO_DUMP("update_BCNTIM, tim=", pstapriv->tim_bitmap, pstapriv->aid_bmp_len); */
+				/* upate BCN for TIM IE */
+				/* update_BCNTIM(padapter); */
+				update_mask |= BIT(1);
+			}
+			rtw_tim_map_clear(padapter, pstapriv->tim_bitmap, 0);
+			rtw_tim_map_clear(padapter, pstapriv->sta_dz_bitmap, 0);
+		}
+
+	}
+
+_exit:
+
+	/* _exit_critical_bh(&psta_bmc->sleep_q.lock, &irqL);	 */
+	_exit_critical_bh(&pxmitpriv->lock, &irqL);
+
+	if (update_mask) {
+		/* update_BCNTIM(padapter); */
+		if ((update_mask & (BIT(0) | BIT(1))) == (BIT(0) | BIT(1)))
+			_update_beacon(padapter, _TIM_IE_, NULL, _TRUE, "clear UC&BMC");
+		else if ((update_mask & BIT(1)) == BIT(1))
+			_update_beacon(padapter, _TIM_IE_, NULL, _TRUE, "clear BMC");
+		else
+			_update_beacon(padapter, _TIM_IE_, NULL, _TRUE, "clear UC");
+	}
+
+}
+
+void xmit_delivery_enabled_frames(_adapter *padapter, struct sta_info *psta)
+{
+	_irqL irqL;
+	u8 wmmps_ac = 0;
+	_list	*xmitframe_plist, *xmitframe_phead;
+	struct xmit_frame *pxmitframe = NULL;
+	struct sta_priv *pstapriv = &padapter->stapriv;
+	struct xmit_priv *pxmitpriv = &padapter->xmitpriv;
+
+
+	/* _enter_critical_bh(&psta->sleep_q.lock, &irqL); */
+	_enter_critical_bh(&pxmitpriv->lock, &irqL);
+
+	xmitframe_phead = get_list_head(&psta->sleep_q);
+	xmitframe_plist = get_next(xmitframe_phead);
+
+	while ((rtw_end_of_queue_search(xmitframe_phead, xmitframe_plist)) == _FALSE) {
+		pxmitframe = LIST_CONTAINOR(xmitframe_plist, struct xmit_frame, list);
+
+		xmitframe_plist = get_next(xmitframe_plist);
+
+		switch (pxmitframe->attrib.priority) {
+		case 1:
+		case 2:
+			wmmps_ac = psta->uapsd_bk & BIT(1);
+			break;
+		case 4:
+		case 5:
+			wmmps_ac = psta->uapsd_vi & BIT(1);
+			break;
+		case 6:
+		case 7:
+			wmmps_ac = psta->uapsd_vo & BIT(1);
+			break;
+		case 0:
+		case 3:
+		default:
+			wmmps_ac = psta->uapsd_be & BIT(1);
+			break;
+		}
+
+		if (!wmmps_ac)
+			continue;
+
+		rtw_list_delete(&pxmitframe->list);
+
+		psta->sleepq_len--;
+		psta->sleepq_ac_len--;
+
+		if (psta->sleepq_ac_len > 0) {
+			pxmitframe->attrib.mdata = 1;
+			pxmitframe->attrib.eosp = 0;
+		} else {
+			pxmitframe->attrib.mdata = 0;
+			pxmitframe->attrib.eosp = 1;
+		}
+
+		pxmitframe->attrib.triggered = 1;
+		rtw_hal_xmitframe_enqueue(padapter, pxmitframe);
+
+		if ((psta->sleepq_ac_len == 0) && (!psta->has_legacy_ac) && (wmmps_ac)) {
+#ifdef CONFIG_TDLS
+			if (psta->tdls_sta_state & TDLS_LINKED_STATE) {
+				/* _exit_critical_bh(&psta->sleep_q.lock, &irqL); */
+				goto exit;
+			}
+#endif /* CONFIG_TDLS */
+			rtw_tim_map_clear(padapter, pstapriv->tim_bitmap, psta->cmn.aid);
+
+			/* RTW_INFO("wakeup to xmit, qlen==0\n"); */
+			/* RTW_INFO_DUMP("update_BCNTIM, tim=", pstapriv->tim_bitmap, pstapriv->aid_bmp_len); */
+			/* upate BCN for TIM IE */
+			/* update_BCNTIM(padapter); */
+			update_beacon(padapter, _TIM_IE_, NULL, _TRUE);
+			/* update_mask = BIT(0); */
+		}
+
+	}
+
+#ifdef CONFIG_TDLS
+exit:
+#endif
+	/* _exit_critical_bh(&psta->sleep_q.lock, &irqL);	 */
+	_exit_critical_bh(&pxmitpriv->lock, &irqL);
+
+	return;
+}
+
+#endif /* defined(CONFIG_AP_MODE) || defined(CONFIG_TDLS) */
+
+#ifdef CONFIG_XMIT_THREAD_MODE
+void enqueue_pending_xmitbuf(
+	struct xmit_priv *pxmitpriv,
+	struct xmit_buf *pxmitbuf)
+{
+	_irqL irql;
+	_queue *pqueue;
+	_adapter *pri_adapter = pxmitpriv->adapter;
+
+	pqueue = &pxmitpriv->pending_xmitbuf_queue;
+
+	_enter_critical_bh(&pqueue->lock, &irql);
+	rtw_list_delete(&pxmitbuf->list);
+	rtw_list_insert_tail(&pxmitbuf->list, get_list_head(pqueue));
+	_exit_critical_bh(&pqueue->lock, &irql);
+
+#if defined(CONFIG_SDIO_HCI) && defined(CONFIG_CONCURRENT_MODE)
+	pri_adapter = GET_PRIMARY_ADAPTER(pri_adapter);
+#endif /*SDIO_HCI + CONCURRENT*/
+	_rtw_up_sema(&(pri_adapter->xmitpriv.xmit_sema));
+}
+
+void enqueue_pending_xmitbuf_to_head(
+	struct xmit_priv *pxmitpriv,
+	struct xmit_buf *pxmitbuf)
+{
+	_irqL irql;
+	_queue *pqueue = &pxmitpriv->pending_xmitbuf_queue;
+
+	_enter_critical_bh(&pqueue->lock, &irql);
+	rtw_list_delete(&pxmitbuf->list);
+	rtw_list_insert_head(&pxmitbuf->list, get_list_head(pqueue));
+	_exit_critical_bh(&pqueue->lock, &irql);
+}
+
+struct xmit_buf *dequeue_pending_xmitbuf(
+	struct xmit_priv *pxmitpriv)
+{
+	_irqL irql;
+	struct xmit_buf *pxmitbuf;
+	_queue *pqueue;
+
+
+	pxmitbuf = NULL;
+	pqueue = &pxmitpriv->pending_xmitbuf_queue;
+
+	_enter_critical_bh(&pqueue->lock, &irql);
+
+	if (_rtw_queue_empty(pqueue) == _FALSE) {
+		_list *plist, *phead;
+
+		phead = get_list_head(pqueue);
+		plist = get_next(phead);
+		pxmitbuf = LIST_CONTAINOR(plist, struct xmit_buf, list);
+		rtw_list_delete(&pxmitbuf->list);
+	}
+
+	_exit_critical_bh(&pqueue->lock, &irql);
+
+	return pxmitbuf;
+}
+
+static struct xmit_buf *dequeue_pending_xmitbuf_ext(
+	struct xmit_priv *pxmitpriv)
+{
+	_irqL irql;
+	struct xmit_buf *pxmitbuf;
+	_queue *pqueue;
+
+	pxmitbuf = NULL;
+	pqueue = &pxmitpriv->pending_xmitbuf_queue;
+
+	_enter_critical_bh(&pqueue->lock, &irql);
+
+	if (_rtw_queue_empty(pqueue) == _FALSE) {
+		_list *plist, *phead;
+		u8 type = 0;
+
+		phead = get_list_head(pqueue);
+		plist = phead;
+		do {
+			plist = get_next(plist);
+			if (plist == phead)
+				break;
+
+			pxmitbuf = LIST_CONTAINOR(plist, struct xmit_buf, list);
+
+			if (pxmitbuf->buf_tag == XMITBUF_MGNT) {
+				rtw_list_delete(&pxmitbuf->list);
+				break;
+			}
+			pxmitbuf = NULL;
+		} while (1);
+	}
+
+	_exit_critical_bh(&pqueue->lock, &irql);
+
+	return pxmitbuf;
+}
+
+struct xmit_buf *select_and_dequeue_pending_xmitbuf(_adapter *padapter)
+{
+	struct xmit_priv *pxmitpriv = &padapter->xmitpriv;
+	struct xmit_buf *pxmitbuf = NULL;
+
+	if (_TRUE == rtw_is_xmit_blocked(padapter))
+		return pxmitbuf;
+
+	pxmitbuf = dequeue_pending_xmitbuf_ext(pxmitpriv);
+	if (pxmitbuf == NULL && rtw_xmit_ac_blocked(padapter) != _TRUE)
+		pxmitbuf = dequeue_pending_xmitbuf(pxmitpriv);
+
+	return pxmitbuf;
+}
+
+sint check_pending_xmitbuf(
+	struct xmit_priv *pxmitpriv)
+{
+	_irqL irql;
+	_queue *pqueue;
+	sint	ret = _FALSE;
+
+	pqueue = &pxmitpriv->pending_xmitbuf_queue;
+
+	_enter_critical_bh(&pqueue->lock, &irql);
+
+	if (_rtw_queue_empty(pqueue) == _FALSE)
+		ret = _TRUE;
+
+	_exit_critical_bh(&pqueue->lock, &irql);
+
+	return ret;
+}
+
+thread_return rtw_xmit_thread(thread_context context)
+{
+	s32 err;
+	PADAPTER padapter;
+
+
+	err = _SUCCESS;
+	padapter = (PADAPTER)context;
+
+	thread_enter("RTW_XMIT_THREAD");
+
+	do {
+		err = rtw_hal_xmit_thread_handler(padapter);
+		flush_signals_thread();
+	} while (_SUCCESS == err);
+
+	RTW_INFO(FUNC_ADPT_FMT " Exit\n", FUNC_ADPT_ARG(padapter));
+
+	rtw_thread_wait_stop();
+
+	return 0;
+}
+#endif
+
+#ifdef DBG_XMIT_BLOCK
+void dump_xmit_block(void *sel, _adapter *padapter)
+{
+	struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
+
+	RTW_PRINT_SEL(sel, "[XMIT-BLOCK] xmit_block :0x%02x\n", dvobj->xmit_block);
+	if (dvobj->xmit_block & XMIT_BLOCK_REDLMEM)
+		RTW_PRINT_SEL(sel, "Reason:%s\n", "XMIT_BLOCK_REDLMEM");
+	if (dvobj->xmit_block & XMIT_BLOCK_SUSPEND)
+		RTW_PRINT_SEL(sel, "Reason:%s\n", "XMIT_BLOCK_SUSPEND");
+	if (dvobj->xmit_block == XMIT_BLOCK_NONE)
+		RTW_PRINT_SEL(sel, "Reason:%s\n", "XMIT_BLOCK_NONE");
+}
+void dump_xmit_block_info(void *sel, const char *fun_name, _adapter *padapter)
+{
+	struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
+
+	RTW_INFO("\n"ADPT_FMT" call %s\n", ADPT_ARG(padapter), fun_name);
+	dump_xmit_block(sel, padapter);
+}
+#define DBG_XMIT_BLOCK_DUMP(adapter)	dump_xmit_block_info(RTW_DBGDUMP, __func__, adapter)
+#endif
+
+void rtw_set_xmit_block(_adapter *padapter, enum XMIT_BLOCK_REASON reason)
+{
+	_irqL irqL;
+	struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
+
+	_enter_critical_bh(&dvobj->xmit_block_lock, &irqL);
+	dvobj->xmit_block |= reason;
+	_exit_critical_bh(&dvobj->xmit_block_lock, &irqL);
+
+	#ifdef DBG_XMIT_BLOCK
+	DBG_XMIT_BLOCK_DUMP(padapter);
+	#endif
+}
+
+void rtw_clr_xmit_block(_adapter *padapter, enum XMIT_BLOCK_REASON reason)
+{
+	_irqL irqL;
+	struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
+
+	_enter_critical_bh(&dvobj->xmit_block_lock, &irqL);
+	dvobj->xmit_block &= ~reason;
+	_exit_critical_bh(&dvobj->xmit_block_lock, &irqL);
+
+	#ifdef DBG_XMIT_BLOCK
+	DBG_XMIT_BLOCK_DUMP(padapter);
+	#endif
+}
+bool rtw_is_xmit_blocked(_adapter *padapter)
+{
+	struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
+
+	#ifdef DBG_XMIT_BLOCK
+	DBG_XMIT_BLOCK_DUMP(padapter);
+	#endif
+	return ((dvobj->xmit_block) ? _TRUE : _FALSE);
+}
+
+bool rtw_xmit_ac_blocked(_adapter *adapter)
+{
+	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
+	struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter);
+	_adapter *iface;
+	struct mlme_ext_priv *mlmeext;
+	bool blocked = _FALSE;
+	int i;
+#ifdef DBG_CONFIG_ERROR_DETECT
+#ifdef DBG_CONFIG_ERROR_RESET
+#ifdef CONFIG_USB_HCI
+	if (rtw_hal_sreset_inprogress(adapter) == _TRUE) {
+		blocked = _TRUE;
+		goto exit;
+	}
+#endif/* #ifdef CONFIG_USB_HCI */
+#endif/* #ifdef DBG_CONFIG_ERROR_RESET */
+#endif/* #ifdef DBG_CONFIG_ERROR_DETECT */
+
+	if (rfctl->offch_state != OFFCHS_NONE
+		#ifdef CONFIG_DFS
+		|| IS_RADAR_DETECTED(rfctl) || rfctl->csa_ch
+		#endif
+	) {
+		blocked = _TRUE;
+		goto exit;
+	}
+
+	for (i = 0; i < dvobj->iface_nums; i++) {
+		iface = dvobj->padapters[i];
+		mlmeext = &iface->mlmeextpriv;
+
+		/* check scan state */
+		if (mlmeext_scan_state(mlmeext) != SCAN_DISABLE
+			&& mlmeext_scan_state(mlmeext) != SCAN_BACK_OP
+		) {
+			blocked = _TRUE;
+			goto exit;
+		}
+
+		if (mlmeext_scan_state(mlmeext) == SCAN_BACK_OP
+			&& !mlmeext_chk_scan_backop_flags(mlmeext, SS_BACKOP_TX_RESUME)
+		) {
+			blocked = _TRUE;
+			goto exit;
+		}
+	}
+
+#ifdef CONFIG_MCC_MODE
+	if (MCC_EN(adapter)) {
+		if (rtw_hal_check_mcc_status(adapter, MCC_STATUS_DOING_MCC)) {
+			if (MCC_STOP(adapter)) {
+				blocked = _TRUE;
+				goto exit;
+			}
+		}
+	}
+#endif /*  CONFIG_MCC_MODE */
+
+exit:
+	return blocked;
+}
+
+#ifdef CONFIG_TX_AMSDU
+void rtw_amsdu_vo_timeout_handler(void *FunctionContext)
+{
+	_adapter *adapter = (_adapter *)FunctionContext;
+
+	adapter->xmitpriv.amsdu_vo_timeout = RTW_AMSDU_TIMER_TIMEOUT;
+
+	tasklet_hi_schedule(&adapter->xmitpriv.xmit_tasklet);
+}
+
+void rtw_amsdu_vi_timeout_handler(void *FunctionContext)
+{
+	_adapter *adapter = (_adapter *)FunctionContext;
+
+	adapter->xmitpriv.amsdu_vi_timeout = RTW_AMSDU_TIMER_TIMEOUT;
+
+	tasklet_hi_schedule(&adapter->xmitpriv.xmit_tasklet);
+}
+
+void rtw_amsdu_be_timeout_handler(void *FunctionContext)
+{
+	_adapter *adapter = (_adapter *)FunctionContext;
+
+	adapter->xmitpriv.amsdu_be_timeout = RTW_AMSDU_TIMER_TIMEOUT;
+
+	if (printk_ratelimit())
+		RTW_INFO("%s Timeout!\n",__FUNCTION__);
+
+	tasklet_hi_schedule(&adapter->xmitpriv.xmit_tasklet);
+}
+
+void rtw_amsdu_bk_timeout_handler(void *FunctionContext)
+{
+	_adapter *adapter = (_adapter *)FunctionContext;
+
+	adapter->xmitpriv.amsdu_bk_timeout = RTW_AMSDU_TIMER_TIMEOUT;
+
+	tasklet_hi_schedule(&adapter->xmitpriv.xmit_tasklet);
+}
+
+u8 rtw_amsdu_get_timer_status(_adapter *padapter, u8 priority)
+{
+	struct xmit_priv        *pxmitpriv = &padapter->xmitpriv;
+
+	u8 status =  RTW_AMSDU_TIMER_UNSET;
+
+	switch(priority)
+	{
+		case 1:
+		case 2:
+			status = pxmitpriv->amsdu_bk_timeout;
+			break;
+		case 4:
+		case 5:
+			status = pxmitpriv->amsdu_vi_timeout;
+			break;
+		case 6:
+		case 7:
+			status = pxmitpriv->amsdu_vo_timeout;
+			break;
+		case 0:
+		case 3:
+		default:
+			status = pxmitpriv->amsdu_be_timeout;
+			break;
+	}
+	return status;
+}
+
+void rtw_amsdu_set_timer_status(_adapter *padapter, u8 priority, u8 status)
+{
+	struct xmit_priv        *pxmitpriv = &padapter->xmitpriv;
+
+	switch(priority)
+	{
+		case 1:
+		case 2:
+			pxmitpriv->amsdu_bk_timeout = status;
+			break;
+		case 4:
+		case 5:
+			pxmitpriv->amsdu_vi_timeout = status;
+			break;
+		case 6:
+		case 7:
+			pxmitpriv->amsdu_vo_timeout = status;
+			break;
+		case 0:
+		case 3:
+		default:
+			pxmitpriv->amsdu_be_timeout = status;
+			break;
+	}
+}
+
+void rtw_amsdu_set_timer(_adapter *padapter, u8 priority)
+{
+	struct xmit_priv        *pxmitpriv = &padapter->xmitpriv;
+
+	_timer* amsdu_timer = NULL;
+
+	switch(priority)
+	{
+		case 1:
+		case 2:
+			amsdu_timer = &pxmitpriv->amsdu_bk_timer;
+			break;
+		case 4:
+		case 5:
+			amsdu_timer = &pxmitpriv->amsdu_vi_timer;
+			break;
+		case 6:
+		case 7:
+			amsdu_timer = &pxmitpriv->amsdu_vo_timer;
+			break;
+		case 0:
+		case 3:
+		default:
+			amsdu_timer = &pxmitpriv->amsdu_be_timer;
+			break;
+	}
+	_set_timer(amsdu_timer, 1);
+}
+
+void rtw_amsdu_cancel_timer(_adapter *padapter, u8 priority)
+{
+	struct xmit_priv        *pxmitpriv = &padapter->xmitpriv;
+	_timer* amsdu_timer = NULL;
+
+	switch(priority)
+	{
+		case 1:
+		case 2:
+			amsdu_timer = &pxmitpriv->amsdu_bk_timer;
+			break;
+		case 4:
+		case 5:
+			amsdu_timer = &pxmitpriv->amsdu_vi_timer;
+			break;
+		case 6:
+		case 7:
+			amsdu_timer = &pxmitpriv->amsdu_vo_timer;
+			break;
+		case 0:
+		case 3:
+		default:
+			amsdu_timer = &pxmitpriv->amsdu_be_timer;
+			break;
+	}
+	_cancel_timer_ex(amsdu_timer);
+}
+#endif /* CONFIG_TX_AMSDU */
+
+#ifdef DBG_TXBD_DESC_DUMP
+static struct rtw_tx_desc_backup tx_backup[HW_QUEUE_ENTRY][TX_BAK_FRMAE_CNT];
+static u8 backup_idx[HW_QUEUE_ENTRY];
+
+void rtw_tx_desc_backup(_adapter *padapter, struct xmit_frame *pxmitframe, u8 desc_size, u8 hwq)
+{
+	u32 tmp32;
+	u8 *pxmit_buf;
+
+	if (rtw_get_hw_init_completed(padapter) == _FALSE)
+		return;
+
+	pxmit_buf = pxmitframe->pxmitbuf->pbuf;
+
+	_rtw_memcpy(tx_backup[hwq][backup_idx[hwq]].tx_bak_desc, pxmit_buf, desc_size);
+	_rtw_memcpy(tx_backup[hwq][backup_idx[hwq]].tx_bak_data_hdr, pxmit_buf+desc_size, TX_BAK_DATA_LEN);
+
+	tmp32 = rtw_read32(padapter, get_txbd_rw_reg(hwq));
+
+	tx_backup[hwq][backup_idx[hwq]].tx_bak_rp = (tmp32>>16)&0xfff;
+	tx_backup[hwq][backup_idx[hwq]].tx_bak_wp = tmp32&0xfff;
+
+	tx_backup[hwq][backup_idx[hwq]].tx_desc_size = desc_size;
+
+	backup_idx[hwq] = (backup_idx[hwq] + 1) % TX_BAK_FRMAE_CNT;
+}
+
+void rtw_tx_desc_backup_reset(void)
+{
+	int i, j;
+
+	for (i = 0; i < HW_QUEUE_ENTRY; i++) {
+		for (j = 0; j < TX_BAK_FRMAE_CNT; j++)
+			_rtw_memset(&tx_backup[i][j], 0, sizeof(struct rtw_tx_desc_backup));
+
+		backup_idx[i] = 0;
+	}
+}
+
+u8 rtw_get_tx_desc_backup(_adapter *padapter, u8 hwq, struct rtw_tx_desc_backup **pbak)
+{
+	*pbak = &tx_backup[hwq][0];
+
+	return backup_idx[hwq];
+}
+#endif
+
+void rtw_sctx_init(struct submit_ctx *sctx, int timeout_ms)
+{
+	sctx->timeout_ms = timeout_ms;
+	sctx->submit_time = rtw_get_current_time();
+#ifdef PLATFORM_LINUX /* TODO: add condition wating interface for other os */
+	init_completion(&sctx->done);
+#endif
+	sctx->status = RTW_SCTX_SUBMITTED;
+}
+
+int rtw_sctx_wait(struct submit_ctx *sctx, const char *msg)
+{
+	int ret = _FAIL;
+	unsigned long expire;
+	int status = 0;
+
+#ifdef PLATFORM_LINUX
+	expire = sctx->timeout_ms ? msecs_to_jiffies(sctx->timeout_ms) : MAX_SCHEDULE_TIMEOUT;
+	if (!wait_for_completion_timeout(&sctx->done, expire)) {
+		/* timeout, do something?? */
+		status = RTW_SCTX_DONE_TIMEOUT;
+		RTW_INFO("%s timeout: %s\n", __func__, msg);
+	} else
+		status = sctx->status;
+#endif
+
+	if (status == RTW_SCTX_DONE_SUCCESS)
+		ret = _SUCCESS;
+
+	return ret;
+}
+
+bool rtw_sctx_chk_waring_status(int status)
+{
+	switch (status) {
+	case RTW_SCTX_DONE_UNKNOWN:
+	case RTW_SCTX_DONE_BUF_ALLOC:
+	case RTW_SCTX_DONE_BUF_FREE:
+
+	case RTW_SCTX_DONE_DRV_STOP:
+	case RTW_SCTX_DONE_DEV_REMOVE:
+		return _TRUE;
+	default:
+		return _FALSE;
+	}
+}
+
+void rtw_sctx_done_err(struct submit_ctx **sctx, int status)
+{
+	if (*sctx) {
+		if (rtw_sctx_chk_waring_status(status))
+			RTW_INFO("%s status:%d\n", __func__, status);
+		(*sctx)->status = status;
+#ifdef PLATFORM_LINUX
+		complete(&((*sctx)->done));
+#endif
+		*sctx = NULL;
+	}
+}
+
+void rtw_sctx_done(struct submit_ctx **sctx)
+{
+	rtw_sctx_done_err(sctx, RTW_SCTX_DONE_SUCCESS);
+}
+
+#ifdef CONFIG_XMIT_ACK
+int rtw_ack_tx_wait(struct xmit_priv *pxmitpriv, u32 timeout_ms)
+{
+	struct submit_ctx *pack_tx_ops = &pxmitpriv->ack_tx_ops;
+
+	pack_tx_ops->submit_time = rtw_get_current_time();
+	pack_tx_ops->timeout_ms = timeout_ms;
+	pack_tx_ops->status = RTW_SCTX_SUBMITTED;
+
+	return rtw_sctx_wait(pack_tx_ops, __func__);
+}
+
+void rtw_ack_tx_done(struct xmit_priv *pxmitpriv, int status)
+{
+	struct submit_ctx *pack_tx_ops = &pxmitpriv->ack_tx_ops;
+
+	if (pxmitpriv->ack_tx)
+		rtw_sctx_done_err(&pack_tx_ops, status);
+	else
+		RTW_INFO("%s ack_tx not set\n", __func__);
+}
+#endif /* CONFIG_XMIT_ACK */
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/btc/halbtc8192e1ant.c linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/btc/halbtc8192e1ant.c
--- linux-5.6.3/3rdparty/rtl8821ce/hal/btc/halbtc8192e1ant.c	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/btc/halbtc8192e1ant.c	2020-04-10 16:35:06.780658387 +0300
@@ -0,0 +1,3417 @@
+/* ************************************************************
+ * Description:
+ *
+ * This file is for RTL8192E Co-exist mechanism
+ *
+ * History
+ * 2012/11/15 Cosa first check in.
+ *
+ * ************************************************************ */
+
+/* ************************************************************
+ * include files
+ * ************************************************************ */
+#include "mp_precomp.h"
+
+#if (BT_SUPPORT == 1 && COEX_SUPPORT == 1)
+
+#if (RTL8192E_SUPPORT == 1)
+/* ************************************************************
+ * Global variables, these are static variables
+ * ************************************************************ */
+static u8	 *trace_buf = &gl_btc_trace_buf[0];
+static struct  coex_dm_8192e_1ant		glcoex_dm_8192e_1ant;
+static struct  coex_dm_8192e_1ant	*coex_dm = &glcoex_dm_8192e_1ant;
+static struct  coex_sta_8192e_1ant		glcoex_sta_8192e_1ant;
+static struct  coex_sta_8192e_1ant	*coex_sta = &glcoex_sta_8192e_1ant;
+
+const char *const glbt_info_src_8192e_1ant[] = {
+	"BT Info[wifi fw]",
+	"BT Info[bt rsp]",
+	"BT Info[bt auto report]",
+};
+
+u32	glcoex_ver_date_8192e_1ant = 20140527;
+u32	glcoex_ver_8192e_1ant = 0x4f;
+
+/* ************************************************************
+ * local function proto type if needed
+ * ************************************************************
+ * ************************************************************
+ * local function start with halbtc8192e1ant_
+ * ************************************************************ */
+u8 halbtc8192e1ant_bt_rssi_state(u8 level_num, u8 rssi_thresh, u8 rssi_thresh1)
+{
+	s32			bt_rssi = 0;
+	u8			bt_rssi_state = coex_sta->pre_bt_rssi_state;
+
+	bt_rssi = coex_sta->bt_rssi;
+
+	if (level_num == 2) {
+		if ((coex_sta->pre_bt_rssi_state == BTC_RSSI_STATE_LOW) ||
+		    (coex_sta->pre_bt_rssi_state ==
+		     BTC_RSSI_STATE_STAY_LOW)) {
+			if (bt_rssi >= (rssi_thresh +
+					BTC_RSSI_COEX_THRESH_TOL_8192E_1ANT))
+				bt_rssi_state = BTC_RSSI_STATE_HIGH;
+			else
+				bt_rssi_state = BTC_RSSI_STATE_STAY_LOW;
+		} else {
+			if (bt_rssi < rssi_thresh)
+				bt_rssi_state = BTC_RSSI_STATE_LOW;
+			else
+				bt_rssi_state = BTC_RSSI_STATE_STAY_HIGH;
+		}
+	} else if (level_num == 3) {
+		if (rssi_thresh > rssi_thresh1) {
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				    "[BTCoex], BT Rssi thresh error!!\n");
+			BTC_TRACE(trace_buf);
+			return coex_sta->pre_bt_rssi_state;
+		}
+
+		if ((coex_sta->pre_bt_rssi_state == BTC_RSSI_STATE_LOW) ||
+		    (coex_sta->pre_bt_rssi_state ==
+		     BTC_RSSI_STATE_STAY_LOW)) {
+			if (bt_rssi >= (rssi_thresh +
+					BTC_RSSI_COEX_THRESH_TOL_8192E_1ANT))
+				bt_rssi_state = BTC_RSSI_STATE_MEDIUM;
+			else
+				bt_rssi_state = BTC_RSSI_STATE_STAY_LOW;
+		} else if ((coex_sta->pre_bt_rssi_state ==
+			    BTC_RSSI_STATE_MEDIUM) ||
+			   (coex_sta->pre_bt_rssi_state ==
+			    BTC_RSSI_STATE_STAY_MEDIUM)) {
+			if (bt_rssi >= (rssi_thresh1 +
+					BTC_RSSI_COEX_THRESH_TOL_8192E_1ANT))
+				bt_rssi_state = BTC_RSSI_STATE_HIGH;
+			else if (bt_rssi < rssi_thresh)
+				bt_rssi_state = BTC_RSSI_STATE_LOW;
+			else
+				bt_rssi_state = BTC_RSSI_STATE_STAY_MEDIUM;
+		} else {
+			if (bt_rssi < rssi_thresh1)
+				bt_rssi_state = BTC_RSSI_STATE_MEDIUM;
+			else
+				bt_rssi_state = BTC_RSSI_STATE_STAY_HIGH;
+		}
+	}
+
+	coex_sta->pre_bt_rssi_state = bt_rssi_state;
+
+	return bt_rssi_state;
+}
+
+u8 halbtc8192e1ant_wifi_rssi_state(IN struct btc_coexist *btcoexist,
+	   IN u8 index, IN u8 level_num, IN u8 rssi_thresh, IN u8 rssi_thresh1)
+{
+	s32			wifi_rssi = 0;
+	u8			wifi_rssi_state = coex_sta->pre_wifi_rssi_state[index];
+
+	btcoexist->btc_get(btcoexist, BTC_GET_S4_WIFI_RSSI, &wifi_rssi);
+
+	if (level_num == 2) {
+		if ((coex_sta->pre_wifi_rssi_state[index] == BTC_RSSI_STATE_LOW)
+		    ||
+		    (coex_sta->pre_wifi_rssi_state[index] ==
+		     BTC_RSSI_STATE_STAY_LOW)) {
+			if (wifi_rssi >= (rssi_thresh +
+					  BTC_RSSI_COEX_THRESH_TOL_8192E_1ANT))
+				wifi_rssi_state = BTC_RSSI_STATE_HIGH;
+			else
+				wifi_rssi_state = BTC_RSSI_STATE_STAY_LOW;
+		} else {
+			if (wifi_rssi < rssi_thresh)
+				wifi_rssi_state = BTC_RSSI_STATE_LOW;
+			else
+				wifi_rssi_state = BTC_RSSI_STATE_STAY_HIGH;
+		}
+	} else if (level_num == 3) {
+		if (rssi_thresh > rssi_thresh1) {
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				    "[BTCoex], wifi RSSI thresh error!!\n");
+			BTC_TRACE(trace_buf);
+			return coex_sta->pre_wifi_rssi_state[index];
+		}
+
+		if ((coex_sta->pre_wifi_rssi_state[index] == BTC_RSSI_STATE_LOW)
+		    ||
+		    (coex_sta->pre_wifi_rssi_state[index] ==
+		     BTC_RSSI_STATE_STAY_LOW)) {
+			if (wifi_rssi >= (rssi_thresh +
+					  BTC_RSSI_COEX_THRESH_TOL_8192E_1ANT))
+				wifi_rssi_state = BTC_RSSI_STATE_MEDIUM;
+			else
+				wifi_rssi_state = BTC_RSSI_STATE_STAY_LOW;
+		} else if ((coex_sta->pre_wifi_rssi_state[index] ==
+			    BTC_RSSI_STATE_MEDIUM) ||
+			   (coex_sta->pre_wifi_rssi_state[index] ==
+			    BTC_RSSI_STATE_STAY_MEDIUM)) {
+			if (wifi_rssi >= (rssi_thresh1 +
+					  BTC_RSSI_COEX_THRESH_TOL_8192E_1ANT))
+				wifi_rssi_state = BTC_RSSI_STATE_HIGH;
+			else if (wifi_rssi < rssi_thresh)
+				wifi_rssi_state = BTC_RSSI_STATE_LOW;
+			else
+				wifi_rssi_state = BTC_RSSI_STATE_STAY_MEDIUM;
+		} else {
+			if (wifi_rssi < rssi_thresh1)
+				wifi_rssi_state = BTC_RSSI_STATE_MEDIUM;
+			else
+				wifi_rssi_state = BTC_RSSI_STATE_STAY_HIGH;
+		}
+	}
+
+	coex_sta->pre_wifi_rssi_state[index] = wifi_rssi_state;
+
+	return wifi_rssi_state;
+}
+
+void halbtc8192e1ant_update_ra_mask(IN struct btc_coexist *btcoexist,
+				    IN boolean force_exec, IN u32 dis_rate_mask)
+{
+	coex_dm->cur_ra_mask = dis_rate_mask;
+
+	if (force_exec || (coex_dm->pre_ra_mask != coex_dm->cur_ra_mask))
+		btcoexist->btc_set(btcoexist, BTC_SET_ACT_UPDATE_RAMASK,
+				   &coex_dm->cur_ra_mask);
+	coex_dm->pre_ra_mask = coex_dm->cur_ra_mask;
+}
+
+void halbtc8192e1ant_auto_rate_fallback_retry(IN struct btc_coexist *btcoexist,
+		IN boolean force_exec, IN u8 type)
+{
+	boolean	wifi_under_b_mode = false;
+
+	coex_dm->cur_arfr_type = type;
+
+	if (force_exec || (coex_dm->pre_arfr_type != coex_dm->cur_arfr_type)) {
+		switch (coex_dm->cur_arfr_type) {
+		case 0:	/* normal mode */
+			btcoexist->btc_write_4byte(btcoexist, 0x430,
+						   coex_dm->backup_arfr_cnt1);
+			btcoexist->btc_write_4byte(btcoexist, 0x434,
+						   coex_dm->backup_arfr_cnt2);
+			break;
+		case 1:
+			btcoexist->btc_get(btcoexist,
+					   BTC_GET_BL_WIFI_UNDER_B_MODE,
+					   &wifi_under_b_mode);
+			if (wifi_under_b_mode) {
+				btcoexist->btc_write_4byte(btcoexist,
+							   0x430, 0x0);
+				btcoexist->btc_write_4byte(btcoexist,
+							   0x434, 0x01010101);
+			} else {
+				btcoexist->btc_write_4byte(btcoexist,
+							   0x430, 0x0);
+				btcoexist->btc_write_4byte(btcoexist,
+							   0x434, 0x04030201);
+			}
+			break;
+		default:
+			break;
+		}
+	}
+
+	coex_dm->pre_arfr_type = coex_dm->cur_arfr_type;
+}
+
+void halbtc8192e1ant_retry_limit(IN struct btc_coexist *btcoexist,
+				 IN boolean force_exec, IN u8 type)
+{
+	coex_dm->cur_retry_limit_type = type;
+
+	if (force_exec ||
+	    (coex_dm->pre_retry_limit_type !=
+	     coex_dm->cur_retry_limit_type)) {
+		switch (coex_dm->cur_retry_limit_type) {
+		case 0:	/* normal mode */
+			btcoexist->btc_write_2byte(btcoexist, 0x42a,
+						   coex_dm->backup_retry_limit);
+			break;
+		case 1:	/* retry limit=8 */
+			btcoexist->btc_write_2byte(btcoexist, 0x42a,
+						   0x0808);
+			break;
+		default:
+			break;
+		}
+	}
+
+	coex_dm->pre_retry_limit_type = coex_dm->cur_retry_limit_type;
+}
+
+void halbtc8192e1ant_ampdu_max_time(IN struct btc_coexist *btcoexist,
+				    IN boolean force_exec, IN u8 type)
+{
+	coex_dm->cur_ampdu_time_type = type;
+
+	if (force_exec ||
+	    (coex_dm->pre_ampdu_time_type != coex_dm->cur_ampdu_time_type)) {
+		switch (coex_dm->cur_ampdu_time_type) {
+		case 0:	/* normal mode */
+			btcoexist->btc_write_1byte(btcoexist, 0x456,
+					   coex_dm->backup_ampdu_max_time);
+			break;
+		case 1:	/* AMPDU timw = 0x38 * 32us */
+			btcoexist->btc_write_1byte(btcoexist, 0x456,
+						   0x38);
+			break;
+		default:
+			break;
+		}
+	}
+
+	coex_dm->pre_ampdu_time_type = coex_dm->cur_ampdu_time_type;
+}
+
+void halbtc8192e1ant_limited_tx(IN struct btc_coexist *btcoexist,
+		IN boolean force_exec, IN u8 ra_mask_type, IN u8 arfr_type,
+				IN u8 retry_limit_type, IN u8 ampdu_time_type)
+{
+	switch (ra_mask_type) {
+	case 0:	/* normal mode */
+		halbtc8192e1ant_update_ra_mask(btcoexist, force_exec,
+					       0x0);
+		break;
+	case 1:	/* disable cck 1/2 */
+		halbtc8192e1ant_update_ra_mask(btcoexist, force_exec,
+					       0x00000003);
+		break;
+	case 2:	/* disable cck 1/2/5.5, ofdm 6/9/12/18/24, mcs 0/1/2/3/4 */
+		halbtc8192e1ant_update_ra_mask(btcoexist, force_exec,
+					       0x0001f1f7);
+		break;
+	default:
+		break;
+	}
+
+	halbtc8192e1ant_auto_rate_fallback_retry(btcoexist, force_exec,
+			arfr_type);
+	halbtc8192e1ant_retry_limit(btcoexist, force_exec, retry_limit_type);
+	halbtc8192e1ant_ampdu_max_time(btcoexist, force_exec, ampdu_time_type);
+}
+
+void halbtc8192e1ant_limited_rx(IN struct btc_coexist *btcoexist,
+			IN boolean force_exec, IN boolean rej_ap_agg_pkt,
+			IN boolean bt_ctrl_agg_buf_size, IN u8 agg_buf_size)
+{
+	boolean	reject_rx_agg = rej_ap_agg_pkt;
+	boolean	bt_ctrl_rx_agg_size = bt_ctrl_agg_buf_size;
+	u8	rx_agg_size = agg_buf_size;
+
+	/* ============================================ */
+	/*	Rx Aggregation related setting */
+	/* ============================================ */
+	btcoexist->btc_set(btcoexist, BTC_SET_BL_TO_REJ_AP_AGG_PKT,
+			   &reject_rx_agg);
+	/* decide BT control aggregation buf size or not */
+	btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_CTRL_AGG_SIZE,
+			   &bt_ctrl_rx_agg_size);
+	/* aggregation buf size, only work when BT control Rx aggregation size. */
+	btcoexist->btc_set(btcoexist, BTC_SET_U1_AGG_BUF_SIZE, &rx_agg_size);
+	/* real update aggregation setting */
+	btcoexist->btc_set(btcoexist, BTC_SET_ACT_AGGREGATE_CTRL, NULL);
+
+
+}
+
+void halbtc8192e1ant_query_bt_info(IN struct btc_coexist *btcoexist)
+{
+	u8			h2c_parameter[1] = {0};
+
+	coex_sta->c2h_bt_info_req_sent = true;
+
+	h2c_parameter[0] |= BIT(0);	/* trigger */
+
+	btcoexist->btc_fill_h2c(btcoexist, 0x61, 1, h2c_parameter);
+}
+
+void halbtc8192e1ant_monitor_bt_ctr(IN struct btc_coexist *btcoexist)
+{
+	u32			reg_hp_txrx, reg_lp_txrx, u32tmp;
+	u32			reg_hp_tx = 0, reg_hp_rx = 0, reg_lp_tx = 0, reg_lp_rx = 0;
+	static u8		num_of_bt_counter_chk = 0;
+
+	/* to avoid 0x76e[3] = 1 (WLAN_Act control by PTA) during IPS */
+	/* if (! (btcoexist->btc_read_1byte(btcoexist, 0x76e) & 0x8) ) */
+
+	if (coex_sta->under_ips) {
+		coex_sta->high_priority_tx = 65535;
+		coex_sta->high_priority_rx = 65535;
+		coex_sta->low_priority_tx = 65535;
+		coex_sta->low_priority_rx = 65535;
+		return;
+	}
+
+	reg_hp_txrx = 0x770;
+	reg_lp_txrx = 0x774;
+
+	u32tmp = btcoexist->btc_read_4byte(btcoexist, reg_hp_txrx);
+	reg_hp_tx = u32tmp & MASKLWORD;
+	reg_hp_rx = (u32tmp & MASKHWORD) >> 16;
+
+	u32tmp = btcoexist->btc_read_4byte(btcoexist, reg_lp_txrx);
+	reg_lp_tx = u32tmp & MASKLWORD;
+	reg_lp_rx = (u32tmp & MASKHWORD) >> 16;
+
+	coex_sta->high_priority_tx = reg_hp_tx;
+	coex_sta->high_priority_rx = reg_hp_rx;
+	coex_sta->low_priority_tx = reg_lp_tx;
+	coex_sta->low_priority_rx = reg_lp_rx;
+
+	if ((coex_sta->low_priority_tx >= 1050)  &&
+	    (!coex_sta->c2h_bt_inquiry_page))
+		coex_sta->pop_event_cnt++;
+
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+		    "[BTCoex], Hi-Pri Rx/Tx: %d/%d, Lo-Pri Rx/Tx: %d/%d\n",
+		    reg_hp_rx, reg_hp_tx, reg_lp_rx, reg_lp_tx);
+	BTC_TRACE(trace_buf);
+
+	/* reset counter */
+	btcoexist->btc_write_1byte(btcoexist, 0x76e, 0xc);
+
+	if ((reg_hp_tx == 0) && (reg_hp_rx == 0) && (reg_lp_tx == 0) &&
+	    (reg_lp_rx == 0)) {
+		num_of_bt_counter_chk++;
+		if (num_of_bt_counter_chk >= 3) {
+			halbtc8192e1ant_query_bt_info(btcoexist);
+			num_of_bt_counter_chk = 0;
+		}
+	}
+}
+
+
+void halbtc8192e1ant_monitor_wifi_ctr(IN struct btc_coexist *btcoexist)
+{
+	s32	wifi_rssi = 0;
+	boolean wifi_busy = false, wifi_under_b_mode = false;
+	static u8 cck_lock_counter = 0;
+
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy);
+	btcoexist->btc_get(btcoexist, BTC_GET_S4_WIFI_RSSI, &wifi_rssi);
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_B_MODE,
+			   &wifi_under_b_mode);
+
+	if (coex_sta->under_ips) {
+		coex_sta->crc_ok_cck = 0;
+		coex_sta->crc_ok_11g = 0;
+		coex_sta->crc_ok_11n = 0;
+		coex_sta->crc_ok_11n_agg = 0;
+
+		coex_sta->crc_err_cck = 0;
+		coex_sta->crc_err_11g = 0;
+		coex_sta->crc_err_11n = 0;
+		coex_sta->crc_err_11n_agg = 0;
+	} else {
+		coex_sta->crc_ok_cck	= btcoexist->btc_read_4byte(btcoexist,
+					  0xf88);
+		coex_sta->crc_ok_11g	= btcoexist->btc_read_2byte(btcoexist,
+					  0xf94);
+		coex_sta->crc_ok_11n	= btcoexist->btc_read_2byte(btcoexist,
+					  0xf90);
+		coex_sta->crc_ok_11n_agg = btcoexist->btc_read_2byte(btcoexist,
+					   0xfb8);
+
+		coex_sta->crc_err_cck	 = btcoexist->btc_read_4byte(btcoexist,
+					   0xf84);
+		coex_sta->crc_err_11g	 = btcoexist->btc_read_2byte(btcoexist,
+					   0xf96);
+		coex_sta->crc_err_11n	 = btcoexist->btc_read_2byte(btcoexist,
+					   0xf92);
+		coex_sta->crc_err_11n_agg = btcoexist->btc_read_2byte(btcoexist,
+					    0xfba);
+	}
+
+
+	/* reset counter */
+	btcoexist->btc_write_1byte_bitmask(btcoexist, 0xf16, 0x1, 0x1);
+	btcoexist->btc_write_1byte_bitmask(btcoexist, 0xf16, 0x1, 0x0);
+
+	if ((wifi_busy) && (wifi_rssi >= 30) && (!wifi_under_b_mode)) {
+		if ((coex_dm->bt_status == BT_8192E_1ANT_BT_STATUS_ACL_BUSY) ||
+		    (coex_dm->bt_status ==
+		     BT_8192E_1ANT_BT_STATUS_ACL_SCO_BUSY) ||
+		    (coex_dm->bt_status ==
+		     BT_8192E_1ANT_BT_STATUS_SCO_BUSY)) {
+			if (coex_sta->crc_ok_cck > (coex_sta->crc_ok_11g +
+						    coex_sta->crc_ok_11n +
+						    coex_sta->crc_ok_11n_agg)) {
+				if (cck_lock_counter < 5)
+					cck_lock_counter++;
+			} else {
+				if (cck_lock_counter > 0)
+					cck_lock_counter--;
+			}
+
+		} else {
+			if (cck_lock_counter > 0)
+				cck_lock_counter--;
+		}
+	} else {
+		if (cck_lock_counter > 0)
+			cck_lock_counter--;
+	}
+
+	if (!coex_sta->pre_ccklock) {
+
+		if (cck_lock_counter >= 5)
+			coex_sta->cck_lock = true;
+		else
+			coex_sta->cck_lock = false;
+	} else {
+		if (cck_lock_counter == 0)
+			coex_sta->cck_lock = false;
+		else
+			coex_sta->cck_lock = true;
+	}
+
+	coex_sta->pre_ccklock =  coex_sta->cck_lock;
+
+
+}
+
+boolean halbtc8192e1ant_is_wifi_status_changed(IN struct btc_coexist *btcoexist)
+{
+	static boolean	pre_wifi_busy = false, pre_under_4way = false,
+			pre_bt_hs_on = false;
+	boolean wifi_busy = false, under_4way = false, bt_hs_on = false;
+	boolean wifi_connected = false;
+
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED,
+			   &wifi_connected);
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy);
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on);
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_4_WAY_PROGRESS,
+			   &under_4way);
+
+	if (wifi_connected) {
+		if (wifi_busy != pre_wifi_busy) {
+			pre_wifi_busy = wifi_busy;
+			return true;
+		}
+		if (under_4way != pre_under_4way) {
+			pre_under_4way = under_4way;
+			return true;
+		}
+		if (bt_hs_on != pre_bt_hs_on) {
+			pre_bt_hs_on = bt_hs_on;
+			return true;
+		}
+	}
+
+	return false;
+}
+
+void halbtc8192e1ant_update_bt_link_info(IN struct btc_coexist *btcoexist)
+{
+	struct  btc_bt_link_info	*bt_link_info = &btcoexist->bt_link_info;
+	boolean				bt_hs_on = false;
+
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on);
+
+	bt_link_info->bt_link_exist = coex_sta->bt_link_exist;
+	bt_link_info->sco_exist = coex_sta->sco_exist;
+	bt_link_info->a2dp_exist = coex_sta->a2dp_exist;
+	bt_link_info->pan_exist = coex_sta->pan_exist;
+	bt_link_info->hid_exist = coex_sta->hid_exist;
+
+	/* work around for HS mode. */
+	if (bt_hs_on) {
+		bt_link_info->pan_exist = true;
+		bt_link_info->bt_link_exist = true;
+	}
+
+	/* check if Sco only */
+	if (bt_link_info->sco_exist &&
+	    !bt_link_info->a2dp_exist &&
+	    !bt_link_info->pan_exist &&
+	    !bt_link_info->hid_exist)
+		bt_link_info->sco_only = true;
+	else
+		bt_link_info->sco_only = false;
+
+	/* check if A2dp only */
+	if (!bt_link_info->sco_exist &&
+	    bt_link_info->a2dp_exist &&
+	    !bt_link_info->pan_exist &&
+	    !bt_link_info->hid_exist)
+		bt_link_info->a2dp_only = true;
+	else
+		bt_link_info->a2dp_only = false;
+
+	/* check if Pan only */
+	if (!bt_link_info->sco_exist &&
+	    !bt_link_info->a2dp_exist &&
+	    bt_link_info->pan_exist &&
+	    !bt_link_info->hid_exist)
+		bt_link_info->pan_only = true;
+	else
+		bt_link_info->pan_only = false;
+
+	/* check if Hid only */
+	if (!bt_link_info->sco_exist &&
+	    !bt_link_info->a2dp_exist &&
+	    !bt_link_info->pan_exist &&
+	    bt_link_info->hid_exist)
+		bt_link_info->hid_only = true;
+	else
+		bt_link_info->hid_only = false;
+}
+
+u8 halbtc8192e1ant_action_algorithm(IN struct btc_coexist *btcoexist)
+{
+	struct  btc_bt_link_info	*bt_link_info = &btcoexist->bt_link_info;
+	boolean				bt_hs_on = false;
+	u8				algorithm = BT_8192E_1ANT_COEX_ALGO_UNDEFINED;
+	u8				num_of_diff_profile = 0;
+
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on);
+
+	if (!bt_link_info->bt_link_exist) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], No BT link exists!!!\n");
+		BTC_TRACE(trace_buf);
+		return algorithm;
+	}
+
+	if (bt_link_info->sco_exist)
+		num_of_diff_profile++;
+	if (bt_link_info->hid_exist)
+		num_of_diff_profile++;
+	if (bt_link_info->pan_exist)
+		num_of_diff_profile++;
+	if (bt_link_info->a2dp_exist)
+		num_of_diff_profile++;
+
+	if (num_of_diff_profile == 1) {
+		if (bt_link_info->sco_exist) {
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				    "[BTCoex], BT Profile = SCO only\n");
+			BTC_TRACE(trace_buf);
+			algorithm = BT_8192E_1ANT_COEX_ALGO_SCO;
+		} else {
+			if (bt_link_info->hid_exist) {
+				BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+					"[BTCoex], BT Profile = HID only\n");
+				BTC_TRACE(trace_buf);
+				algorithm = BT_8192E_1ANT_COEX_ALGO_HID;
+			} else if (bt_link_info->a2dp_exist) {
+				BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+					"[BTCoex], BT Profile = A2DP only\n");
+				BTC_TRACE(trace_buf);
+				algorithm = BT_8192E_1ANT_COEX_ALGO_A2DP;
+			} else if (bt_link_info->pan_exist) {
+				if (bt_hs_on) {
+					BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+						"[BTCoex], BT Profile = PAN(HS) only\n");
+					BTC_TRACE(trace_buf);
+					algorithm =
+						BT_8192E_1ANT_COEX_ALGO_PANHS;
+				} else {
+					BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+						"[BTCoex], BT Profile = PAN(EDR) only\n");
+					BTC_TRACE(trace_buf);
+					algorithm =
+						BT_8192E_1ANT_COEX_ALGO_PANEDR;
+				}
+			}
+		}
+	} else if (num_of_diff_profile == 2) {
+		if (bt_link_info->sco_exist) {
+			if (bt_link_info->hid_exist) {
+				BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+					"[BTCoex], BT Profile = SCO + HID\n");
+				BTC_TRACE(trace_buf);
+				algorithm = BT_8192E_1ANT_COEX_ALGO_HID;
+			} else if (bt_link_info->a2dp_exist) {
+				BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+					"[BTCoex], BT Profile = SCO + A2DP ==> SCO\n");
+				BTC_TRACE(trace_buf);
+				algorithm = BT_8192E_1ANT_COEX_ALGO_SCO;
+			} else if (bt_link_info->pan_exist) {
+				if (bt_hs_on) {
+					BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+						"[BTCoex], BT Profile = SCO + PAN(HS)\n");
+					BTC_TRACE(trace_buf);
+					algorithm = BT_8192E_1ANT_COEX_ALGO_SCO;
+				} else {
+					BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+						"[BTCoex], BT Profile = SCO + PAN(EDR)\n");
+					BTC_TRACE(trace_buf);
+					algorithm =
+						BT_8192E_1ANT_COEX_ALGO_PANEDR_HID;
+				}
+			}
+		} else {
+			if (bt_link_info->hid_exist &&
+			    bt_link_info->a2dp_exist) {
+				BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+					"[BTCoex], BT Profile = HID + A2DP\n");
+				BTC_TRACE(trace_buf);
+				algorithm = BT_8192E_1ANT_COEX_ALGO_HID_A2DP;
+			} else if (bt_link_info->hid_exist &&
+				   bt_link_info->pan_exist) {
+				if (bt_hs_on) {
+					BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+						"[BTCoex], BT Profile = HID + PAN(HS)\n");
+					BTC_TRACE(trace_buf);
+					algorithm =
+						BT_8192E_1ANT_COEX_ALGO_HID_A2DP;
+				} else {
+					BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+						"[BTCoex], BT Profile = HID + PAN(EDR)\n");
+					BTC_TRACE(trace_buf);
+					algorithm =
+						BT_8192E_1ANT_COEX_ALGO_PANEDR_HID;
+				}
+			} else if (bt_link_info->pan_exist &&
+				   bt_link_info->a2dp_exist) {
+				if (bt_hs_on) {
+					BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+						"[BTCoex], BT Profile = A2DP + PAN(HS)\n");
+					BTC_TRACE(trace_buf);
+					algorithm =
+						BT_8192E_1ANT_COEX_ALGO_A2DP_PANHS;
+				} else {
+					BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+						"[BTCoex], BT Profile = A2DP + PAN(EDR)\n");
+					BTC_TRACE(trace_buf);
+					algorithm =
+						BT_8192E_1ANT_COEX_ALGO_PANEDR_A2DP;
+				}
+			}
+		}
+	} else if (num_of_diff_profile == 3) {
+		if (bt_link_info->sco_exist) {
+			if (bt_link_info->hid_exist &&
+			    bt_link_info->a2dp_exist) {
+				BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+					"[BTCoex], BT Profile = SCO + HID + A2DP ==> HID\n");
+				BTC_TRACE(trace_buf);
+				algorithm = BT_8192E_1ANT_COEX_ALGO_HID;
+			} else if (bt_link_info->hid_exist &&
+				   bt_link_info->pan_exist) {
+				if (bt_hs_on) {
+					BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+						"[BTCoex], BT Profile = SCO + HID + PAN(HS)\n");
+					BTC_TRACE(trace_buf);
+					algorithm =
+						BT_8192E_1ANT_COEX_ALGO_HID_A2DP;
+				} else {
+					BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+						"[BTCoex], BT Profile = SCO + HID + PAN(EDR)\n");
+					BTC_TRACE(trace_buf);
+					algorithm =
+						BT_8192E_1ANT_COEX_ALGO_PANEDR_HID;
+				}
+			} else if (bt_link_info->pan_exist &&
+				   bt_link_info->a2dp_exist) {
+				if (bt_hs_on) {
+					BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+						"[BTCoex], BT Profile = SCO + A2DP + PAN(HS)\n");
+					BTC_TRACE(trace_buf);
+					algorithm = BT_8192E_1ANT_COEX_ALGO_SCO;
+				} else {
+					BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+						"[BTCoex], BT Profile = SCO + A2DP + PAN(EDR) ==> HID\n");
+					BTC_TRACE(trace_buf);
+					algorithm =
+						BT_8192E_1ANT_COEX_ALGO_PANEDR_HID;
+				}
+			}
+		} else {
+			if (bt_link_info->hid_exist &&
+			    bt_link_info->pan_exist &&
+			    bt_link_info->a2dp_exist) {
+				if (bt_hs_on) {
+					BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+						"[BTCoex], BT Profile = HID + A2DP + PAN(HS)\n");
+					BTC_TRACE(trace_buf);
+					algorithm =
+						BT_8192E_1ANT_COEX_ALGO_HID_A2DP;
+				} else {
+					BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+						"[BTCoex], BT Profile = HID + A2DP + PAN(EDR)\n");
+					BTC_TRACE(trace_buf);
+					algorithm =
+						BT_8192E_1ANT_COEX_ALGO_HID_A2DP_PANEDR;
+				}
+			}
+		}
+	} else if (num_of_diff_profile >= 3) {
+		if (bt_link_info->sco_exist) {
+			if (bt_link_info->hid_exist &&
+			    bt_link_info->pan_exist &&
+			    bt_link_info->a2dp_exist) {
+				if (bt_hs_on) {
+					BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+						"[BTCoex], Error!!! BT Profile = SCO + HID + A2DP + PAN(HS)\n");
+					BTC_TRACE(trace_buf);
+
+				} else {
+					BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+						"[BTCoex], BT Profile = SCO + HID + A2DP + PAN(EDR)==>PAN(EDR)+HID\n");
+					BTC_TRACE(trace_buf);
+					algorithm =
+						BT_8192E_1ANT_COEX_ALGO_PANEDR_HID;
+				}
+			}
+		}
+	}
+
+	return algorithm;
+}
+
+void halbtc8192e1ant_set_bt_auto_report(IN struct btc_coexist *btcoexist,
+					IN boolean enable_auto_report)
+{
+	u8			h2c_parameter[1] = {0};
+
+	h2c_parameter[0] = 0;
+
+	if (enable_auto_report)
+		h2c_parameter[0] |= BIT(0);
+
+	btcoexist->btc_fill_h2c(btcoexist, 0x68, 1, h2c_parameter);
+}
+
+void halbtc8192e1ant_bt_auto_report(IN struct btc_coexist *btcoexist,
+		    IN boolean force_exec, IN boolean enable_auto_report)
+{
+	coex_dm->cur_bt_auto_report = enable_auto_report;
+
+	if (!force_exec) {
+		if (coex_dm->pre_bt_auto_report == coex_dm->cur_bt_auto_report)
+			return;
+	}
+	halbtc8192e1ant_set_bt_auto_report(btcoexist,
+					   coex_dm->cur_bt_auto_report);
+
+	coex_dm->pre_bt_auto_report = coex_dm->cur_bt_auto_report;
+}
+
+void halbtc8192e1ant_set_sw_penalty_tx_rate_adaptive(IN struct btc_coexist
+		*btcoexist, IN boolean low_penalty_ra)
+{
+	u8			h2c_parameter[6] = {0};
+
+	h2c_parameter[0] = 0x6;	/* op_code, 0x6= Retry_Penalty */
+
+	if (low_penalty_ra) {
+		h2c_parameter[1] |= BIT(0);
+		h2c_parameter[2] =
+			0x00;  /* normal rate except MCS7/6/5, OFDM54/48/36 */
+		h2c_parameter[3] = 0xf7;  /* MCS7 or OFDM54 */
+		h2c_parameter[4] = 0xf8;  /* MCS6 or OFDM48 */
+		h2c_parameter[5] = 0xf9;	/* MCS5 or OFDM36	 */
+	}
+
+	btcoexist->btc_fill_h2c(btcoexist, 0x69, 6, h2c_parameter);
+}
+
+void halbtc8192e1ant_low_penalty_ra(IN struct btc_coexist *btcoexist,
+			    IN boolean force_exec, IN boolean low_penalty_ra)
+{
+	coex_dm->cur_low_penalty_ra = low_penalty_ra;
+
+	if (!force_exec) {
+		if (coex_dm->pre_low_penalty_ra == coex_dm->cur_low_penalty_ra)
+			return;
+	}
+	halbtc8192e1ant_set_sw_penalty_tx_rate_adaptive(btcoexist,
+			coex_dm->cur_low_penalty_ra);
+
+	coex_dm->pre_low_penalty_ra = coex_dm->cur_low_penalty_ra;
+}
+
+void halbtc8192e1ant_set_coex_table(IN struct btc_coexist *btcoexist,
+	    IN u32 val0x6c0, IN u32 val0x6c4, IN u32 val0x6c8, IN u8 val0x6cc)
+{
+	btcoexist->btc_write_4byte(btcoexist, 0x6c0, val0x6c0);
+
+	btcoexist->btc_write_4byte(btcoexist, 0x6c4, val0x6c4);
+
+	btcoexist->btc_write_4byte(btcoexist, 0x6c8, val0x6c8);
+
+	btcoexist->btc_write_1byte(btcoexist, 0x6cc, val0x6cc);
+}
+
+void halbtc8192e1ant_coex_table(IN struct btc_coexist *btcoexist,
+			IN boolean force_exec, IN u32 val0x6c0, IN u32 val0x6c4,
+				IN u32 val0x6c8, IN u8 val0x6cc)
+{
+	coex_dm->cur_val0x6c0 = val0x6c0;
+	coex_dm->cur_val0x6c4 = val0x6c4;
+	coex_dm->cur_val0x6c8 = val0x6c8;
+	coex_dm->cur_val0x6cc = val0x6cc;
+
+	if (!force_exec) {
+		if ((coex_dm->pre_val0x6c0 == coex_dm->cur_val0x6c0) &&
+		    (coex_dm->pre_val0x6c4 == coex_dm->cur_val0x6c4) &&
+		    (coex_dm->pre_val0x6c8 == coex_dm->cur_val0x6c8) &&
+		    (coex_dm->pre_val0x6cc == coex_dm->cur_val0x6cc))
+			return;
+	}
+	halbtc8192e1ant_set_coex_table(btcoexist, val0x6c0, val0x6c4, val0x6c8,
+				       val0x6cc);
+
+	coex_dm->pre_val0x6c0 = coex_dm->cur_val0x6c0;
+	coex_dm->pre_val0x6c4 = coex_dm->cur_val0x6c4;
+	coex_dm->pre_val0x6c8 = coex_dm->cur_val0x6c8;
+	coex_dm->pre_val0x6cc = coex_dm->cur_val0x6cc;
+}
+
+void halbtc8192e1ant_coex_table_with_type(IN struct btc_coexist *btcoexist,
+		IN boolean force_exec, IN u8 type)
+{
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+		    "[BTCoex], ********** CoexTable(%d) **********\n", type);
+	BTC_TRACE(trace_buf);
+
+	coex_sta->coex_table_type = type;
+
+	switch (type) {
+	case 0:
+		halbtc8192e1ant_coex_table(btcoexist, force_exec,
+				   0x55555555, 0x55555555, 0xffffff, 0x3);
+		break;
+	case 1:
+		halbtc8192e1ant_coex_table(btcoexist, force_exec,
+				   0x55555555, 0x5a5a5a5a, 0xffffff, 0x3);
+		break;
+	case 2:
+		halbtc8192e1ant_coex_table(btcoexist, force_exec,
+				   0x5a5a5a5a, 0x5a5a5a5a, 0xffffff, 0x3);
+		break;
+	case 3:
+		halbtc8192e1ant_coex_table(btcoexist, force_exec,
+				   0x55555555, 0x5a5a5a5a, 0xffffff, 0x3);
+		break;
+	case 4:
+		halbtc8192e1ant_coex_table(btcoexist, force_exec,
+				   0x55555555, 0xaaaa5a5a, 0xffffff, 0x3);
+		break;
+	case 5:
+		halbtc8192e1ant_coex_table(btcoexist, force_exec,
+				   0x5a5a5a5a, 0xaa5a5a5a, 0xffffff, 0x3);
+		break;
+	case 6:
+		halbtc8192e1ant_coex_table(btcoexist, force_exec,
+				   0x55555555, 0xaaaaaaaa, 0xffffff, 0x3);
+		break;
+	case 7:
+		halbtc8192e1ant_coex_table(btcoexist, force_exec,
+				   0xaaaaaaaa, 0xaaaaaaaa, 0xffffff, 0x3);
+		break;
+	default:
+		break;
+	}
+}
+
+void halbtc8192e1ant_set_fw_ignore_wlan_act(IN struct btc_coexist *btcoexist,
+		IN boolean enable)
+{
+	u8			h2c_parameter[1] = {0};
+
+	if (enable)
+		h2c_parameter[0] |= BIT(0);		/* function enable */
+
+	btcoexist->btc_fill_h2c(btcoexist, 0x63, 1, h2c_parameter);
+}
+
+void halbtc8192e1ant_ignore_wlan_act(IN struct btc_coexist *btcoexist,
+				     IN boolean force_exec, IN boolean enable)
+{
+	coex_dm->cur_ignore_wlan_act = enable;
+
+	if (!force_exec) {
+		if (coex_dm->pre_ignore_wlan_act ==
+		    coex_dm->cur_ignore_wlan_act)
+			return;
+	}
+	halbtc8192e1ant_set_fw_ignore_wlan_act(btcoexist, enable);
+
+	coex_dm->pre_ignore_wlan_act = coex_dm->cur_ignore_wlan_act;
+}
+
+void halbtc8192e1ant_set_lps_rpwm(IN struct btc_coexist *btcoexist,
+				  IN u8 lps_val, IN u8 rpwm_val)
+{
+	u8	lps = lps_val;
+	u8	rpwm = rpwm_val;
+
+	btcoexist->btc_set(btcoexist, BTC_SET_U1_LPS_VAL, &lps);
+	btcoexist->btc_set(btcoexist, BTC_SET_U1_RPWM_VAL, &rpwm);
+}
+
+void halbtc8192e1ant_lps_rpwm(IN struct btc_coexist *btcoexist,
+		      IN boolean force_exec, IN u8 lps_val, IN u8 rpwm_val)
+{
+	coex_dm->cur_lps = lps_val;
+	coex_dm->cur_rpwm = rpwm_val;
+
+	if (!force_exec) {
+		if ((coex_dm->pre_lps == coex_dm->cur_lps) &&
+		    (coex_dm->pre_rpwm == coex_dm->cur_rpwm))
+			return;
+	}
+	halbtc8192e1ant_set_lps_rpwm(btcoexist, lps_val, rpwm_val);
+
+	coex_dm->pre_lps = coex_dm->cur_lps;
+	coex_dm->pre_rpwm = coex_dm->cur_rpwm;
+}
+
+void halbtc8192e1ant_sw_mechanism(IN struct btc_coexist *btcoexist,
+				  IN boolean low_penalty_ra)
+{
+	halbtc8192e1ant_low_penalty_ra(btcoexist, NORMAL_EXEC, low_penalty_ra);
+}
+
+void halbtc8192e1ant_set_ant_path(IN struct btc_coexist *btcoexist,
+	  IN u8 ant_pos_type, IN boolean init_hwcfg, IN boolean wifi_off)
+{
+	u32			u32tmp = 0;
+
+	if (init_hwcfg) {
+		btcoexist->btc_write_1byte(btcoexist, 0x944, 0x24);
+		btcoexist->btc_write_4byte(btcoexist, 0x930, 0x700700);
+		if (btcoexist->chip_interface == BTC_INTF_USB)
+			btcoexist->btc_write_4byte(btcoexist, 0x64, 0x30430004);
+		else
+			btcoexist->btc_write_4byte(btcoexist, 0x64, 0x30030004);
+
+		/* 0x4c[27][24]='00', Set Antenna to BB */
+		u32tmp = btcoexist->btc_read_4byte(btcoexist, 0x4c);
+		u32tmp &= ~BIT(24);
+		u32tmp &= ~BIT(27);
+		btcoexist->btc_write_4byte(btcoexist, 0x4c, u32tmp);
+	} else if (wifi_off) {
+		if (btcoexist->chip_interface == BTC_INTF_USB)
+			btcoexist->btc_write_4byte(btcoexist, 0x64, 0x30430004);
+		else
+			btcoexist->btc_write_4byte(btcoexist, 0x64, 0x30030004);
+
+		/* 0x4c[27][24]='11', Set Antenna to BT, 0x64[8:7]=0, 0x64[2]=1 */
+		u32tmp = btcoexist->btc_read_4byte(btcoexist, 0x4c);
+		u32tmp |= BIT(24);
+		u32tmp |= BIT(27);
+		btcoexist->btc_write_4byte(btcoexist, 0x4c, u32tmp);
+	}
+
+	/* ext switch setting */
+	switch (ant_pos_type) {
+	case BTC_ANT_PATH_WIFI:
+		btcoexist->btc_write_1byte(btcoexist, 0x92c, 0x4);
+		break;
+	case BTC_ANT_PATH_BT:
+		btcoexist->btc_write_1byte(btcoexist, 0x92c, 0x20);
+		break;
+	default:
+	case BTC_ANT_PATH_PTA:
+		btcoexist->btc_write_1byte(btcoexist, 0x92c, 0x4);
+		break;
+	}
+}
+
+void halbtc8192e1ant_set_fw_pstdma(IN struct btc_coexist *btcoexist,
+	   IN u8 byte1, IN u8 byte2, IN u8 byte3, IN u8 byte4, IN u8 byte5)
+{
+	u8			h2c_parameter[5] = {0};
+	u8			real_byte1 = byte1, real_byte5 = byte5;
+	boolean			ap_enable = false;
+
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_AP_MODE_ENABLE,
+			   &ap_enable);
+
+	if (ap_enable) {
+		if (byte1 & BIT(4) && !(byte1 & BIT(5))) {
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				    "[BTCoex], FW for 1Ant AP mode\n");
+			BTC_TRACE(trace_buf);
+			real_byte1 &= ~BIT(4);
+			real_byte1 |= BIT(5);
+
+			real_byte5 |= BIT(5);
+			real_byte5 &= ~BIT(6);
+		}
+	}
+
+	h2c_parameter[0] = real_byte1;
+	h2c_parameter[1] = byte2;
+	h2c_parameter[2] = byte3;
+	h2c_parameter[3] = byte4;
+	h2c_parameter[4] = real_byte5;
+
+	coex_dm->ps_tdma_para[0] = real_byte1;
+	coex_dm->ps_tdma_para[1] = byte2;
+	coex_dm->ps_tdma_para[2] = byte3;
+	coex_dm->ps_tdma_para[3] = byte4;
+	coex_dm->ps_tdma_para[4] = real_byte5;
+
+	btcoexist->btc_fill_h2c(btcoexist, 0x60, 5, h2c_parameter);
+}
+
+
+void halbtc8192e1ant_ps_tdma(IN struct btc_coexist *btcoexist,
+		     IN boolean force_exec, IN boolean turn_on, IN u8 type)
+{
+	struct  btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
+	boolean			wifi_busy = false;
+	u8			rssi_adjust_val = 0;
+	u8			ps_tdma_byte4_val = 0x50, ps_tdma_byte0_val = 0x51,
+				ps_tdma_byte3_val =  0x10;
+	s8			wifi_duration_adjust = 0x0;
+
+	coex_dm->cur_ps_tdma_on = turn_on;
+	coex_dm->cur_ps_tdma = type;
+
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy);
+
+	if (coex_dm->cur_ps_tdma_on) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], ********** TDMA(on, %d) **********\n",
+			    coex_dm->cur_ps_tdma);
+		BTC_TRACE(trace_buf);
+	} else {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], ********** TDMA(off, %d) **********\n",
+			    coex_dm->cur_ps_tdma);
+		BTC_TRACE(trace_buf);
+	}
+
+	if (!force_exec) {
+		if ((coex_dm->pre_ps_tdma_on == coex_dm->cur_ps_tdma_on) &&
+		    (coex_dm->pre_ps_tdma == coex_dm->cur_ps_tdma))
+			return;
+	}
+
+	if (coex_sta->scan_ap_num <= 5)
+		wifi_duration_adjust = 5;
+	else if (coex_sta->scan_ap_num >= 40)
+		wifi_duration_adjust = -15;
+	else if (coex_sta->scan_ap_num >= 20)
+		wifi_duration_adjust = -10;
+
+	if (!coex_sta->force_lps_on) { /* only for A2DP-only case 1/2/9/11 while wifi noisy threshold > 30 */
+		ps_tdma_byte0_val = 0x61;  /* no null-pkt */
+		ps_tdma_byte3_val = 0x11; /* no tx-pause at BT-slot */
+		ps_tdma_byte4_val = 0x10; /* 0x778 = d/1 toggle */
+	}
+
+	if ((type == 3) || (type == 13) || (type == 14))
+		ps_tdma_byte4_val = ps_tdma_byte4_val &
+			    0xbf;  /* no dynamic slot for multi-profile */
+
+	if (bt_link_info->slave_role == true)
+		ps_tdma_byte4_val = ps_tdma_byte4_val |
+			0x1;  /* 0x778 = 0x1 at wifi slot (no blocking BT Low-Pri pkts) */
+
+	if (turn_on) {
+		switch (type) {
+		default:
+			halbtc8192e1ant_set_fw_pstdma(btcoexist, 0x51,
+				      0x1a, 0x1a, 0x0, ps_tdma_byte4_val);
+			break;
+		case 1:
+			halbtc8192e1ant_set_fw_pstdma(btcoexist,
+						      ps_tdma_byte0_val, 0x3a +
+					      wifi_duration_adjust, 0x03,
+				      ps_tdma_byte3_val, ps_tdma_byte4_val);
+			break;
+		case 2:
+			halbtc8192e1ant_set_fw_pstdma(btcoexist,
+						      ps_tdma_byte0_val, 0x2d +
+					      wifi_duration_adjust, 0x03,
+				      ps_tdma_byte3_val, ps_tdma_byte4_val);
+			break;
+		case 3:
+			halbtc8192e1ant_set_fw_pstdma(btcoexist, 0x51,
+				      0x1d, 0x1d, 0x0, ps_tdma_byte4_val);
+			break;
+		case 4:
+			halbtc8192e1ant_set_fw_pstdma(btcoexist, 0x93,
+						      0x15, 0x3, 0x14, 0x0);
+			break;
+		case 5:
+			halbtc8192e1ant_set_fw_pstdma(btcoexist, 0x61,
+						      0x15, 0x3, 0x11, 0x11);
+			break;
+		case 6:
+			halbtc8192e1ant_set_fw_pstdma(btcoexist, 0x61,
+						      0x20, 0x3, 0x11, 0x11);
+			break;
+		case 7:
+			halbtc8192e1ant_set_fw_pstdma(btcoexist, 0x13,
+						      0xc, 0x5, 0x0, 0x0);
+			break;
+		case 8:
+			halbtc8192e1ant_set_fw_pstdma(btcoexist, 0x93,
+						      0x25, 0x3, 0x10, 0x0);
+			break;
+		case 9:
+			halbtc8192e1ant_set_fw_pstdma(btcoexist,
+					      ps_tdma_byte0_val, 0x21, 0x3,
+				      ps_tdma_byte3_val, ps_tdma_byte4_val);
+			break;
+		case 10:
+			halbtc8192e1ant_set_fw_pstdma(btcoexist, 0x13,
+						      0xa, 0xa, 0x0, 0x40);
+			break;
+		case 11:
+			halbtc8192e1ant_set_fw_pstdma(btcoexist,
+					      ps_tdma_byte0_val, 0x21, 0x03,
+				      ps_tdma_byte3_val, ps_tdma_byte4_val);
+			break;
+		case 12:
+			halbtc8192e1ant_set_fw_pstdma(btcoexist, 0x51,
+						      0x0a, 0x0a, 0x0, 0x50);
+			break;
+		case 13:
+			halbtc8192e1ant_set_fw_pstdma(btcoexist, 0x51,
+				      0x12, 0x12, 0x0, ps_tdma_byte4_val);
+			break;
+		case 14:
+			halbtc8192e1ant_set_fw_pstdma(btcoexist, 0x51,
+				      0x21, 0x3, 0x10, ps_tdma_byte4_val);
+			break;
+		case 15:
+			halbtc8192e1ant_set_fw_pstdma(btcoexist, 0x13,
+						      0xa, 0x3, 0x8, 0x0);
+			break;
+		case 16:
+			halbtc8192e1ant_set_fw_pstdma(btcoexist, 0x93,
+						      0x15, 0x3, 0x10, 0x0);
+			break;
+		case 18:
+			halbtc8192e1ant_set_fw_pstdma(btcoexist, 0x93,
+						      0x25, 0x3, 0x10, 0x0);
+			break;
+		case 20:
+			halbtc8192e1ant_set_fw_pstdma(btcoexist, 0x61,
+						      0x3f, 0x03, 0x11, 0x10);
+			break;
+		case 21:
+			halbtc8192e1ant_set_fw_pstdma(btcoexist, 0x61,
+						      0x25, 0x03, 0x11, 0x11);
+			break;
+		case 22:
+			halbtc8192e1ant_set_fw_pstdma(btcoexist, 0x61,
+						      0x25, 0x03, 0x11, 0x10);
+			break;
+		case 23:
+			halbtc8192e1ant_set_fw_pstdma(btcoexist, 0xe3,
+						      0x25, 0x3, 0x31, 0x18);
+			break;
+		case 24:
+			halbtc8192e1ant_set_fw_pstdma(btcoexist, 0xe3,
+						      0x15, 0x3, 0x31, 0x18);
+			break;
+		case 25:
+			halbtc8192e1ant_set_fw_pstdma(btcoexist, 0xe3,
+						      0xa, 0x3, 0x31, 0x18);
+			break;
+		case 26:
+			halbtc8192e1ant_set_fw_pstdma(btcoexist, 0xe3,
+						      0xa, 0x3, 0x31, 0x18);
+			break;
+		case 27:
+			halbtc8192e1ant_set_fw_pstdma(btcoexist, 0xe3,
+						      0x25, 0x3, 0x31, 0x98);
+			break;
+		case 28:
+			halbtc8192e1ant_set_fw_pstdma(btcoexist, 0x69,
+						      0x25, 0x3, 0x31, 0x0);
+			break;
+		case 29:
+			halbtc8192e1ant_set_fw_pstdma(btcoexist, 0xab,
+						      0x1a, 0x1a, 0x1, 0x10);
+			break;
+		case 30:
+			halbtc8192e1ant_set_fw_pstdma(btcoexist, 0x51,
+						      0x30, 0x3, 0x10, 0x10);
+			break;
+		case 31:
+			halbtc8192e1ant_set_fw_pstdma(btcoexist, 0xd3,
+						      0x1a, 0x1a, 0, 0x58);
+			break;
+		case 32:
+			halbtc8192e1ant_set_fw_pstdma(btcoexist, 0x61,
+						      0x35, 0x3, 0x11, 0x11);
+			break;
+		case 33:
+			halbtc8192e1ant_set_fw_pstdma(btcoexist, 0xa3,
+						      0x25, 0x3, 0x30, 0x90);
+			break;
+		case 34:
+			halbtc8192e1ant_set_fw_pstdma(btcoexist, 0x53,
+						      0x1a, 0x1a, 0x0, 0x10);
+			break;
+		case 35:
+			halbtc8192e1ant_set_fw_pstdma(btcoexist, 0x63,
+						      0x1a, 0x1a, 0x0, 0x10);
+			break;
+		case 36:
+			halbtc8192e1ant_set_fw_pstdma(btcoexist, 0xd3,
+						      0x12, 0x3, 0x14, 0x50);
+			break;
+		case 40: /* SoftAP only with no sta associated,BT disable ,TDMA mode for power saving */
+			/* here softap mode screen off will cost 70-80mA for phone */
+			halbtc8192e1ant_set_fw_pstdma(btcoexist, 0x23,
+						      0x18, 0x00, 0x10, 0x24);
+			break;
+		}
+	} else {
+
+		/* disable PS tdma */
+		switch (type) {
+		case 8: /* PTA Control */
+			halbtc8192e1ant_set_fw_pstdma(btcoexist, 0x8,
+						      0x0, 0x0, 0x0, 0x0);
+			halbtc8192e1ant_set_ant_path(btcoexist,
+					     BTC_ANT_PATH_PTA, false, false);
+			break;
+		case 0:
+		default:  /* Software control, Antenna at BT side */
+			halbtc8192e1ant_set_fw_pstdma(btcoexist, 0x0,
+						      0x0, 0x0, 0x0, 0x0);
+			halbtc8192e1ant_set_ant_path(btcoexist,
+					     BTC_ANT_PATH_BT, false, false);
+			break;
+		case 9:   /* Software control, Antenna at WiFi side */
+			halbtc8192e1ant_set_fw_pstdma(btcoexist, 0x0,
+						      0x0, 0x0, 0x0, 0x0);
+			halbtc8192e1ant_set_ant_path(btcoexist,
+					     BTC_ANT_PATH_WIFI, false, false);
+			break;
+		}
+	}
+	rssi_adjust_val = 0;
+	btcoexist->btc_set(btcoexist,
+		BTC_SET_U1_RSSI_ADJ_VAL_FOR_1ANT_COEX_TYPE, &rssi_adjust_val);
+
+
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+		"############# [BTCoex], 0x948=0x%x, 0x765=0x%x, 0x67=0x%x\n",
+		    btcoexist->btc_read_4byte(btcoexist, 0x948),
+		    btcoexist->btc_read_1byte(btcoexist, 0x765),
+		    btcoexist->btc_read_1byte(btcoexist, 0x67));
+	BTC_TRACE(trace_buf);
+	/* update pre state */
+	coex_dm->pre_ps_tdma_on = coex_dm->cur_ps_tdma_on;
+	coex_dm->pre_ps_tdma = coex_dm->cur_ps_tdma;
+}
+
+void halbtc8192e1ant_coex_all_off(IN struct btc_coexist *btcoexist)
+{
+	/* sw all off */
+	halbtc8192e1ant_sw_mechanism(btcoexist, false);
+
+	/* hw all off */
+	halbtc8192e1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0);
+}
+
+boolean halbtc8192e1ant_is_common_action(IN struct btc_coexist *btcoexist)
+{
+	boolean			common = false, wifi_connected = false, wifi_busy = false;
+
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED,
+			   &wifi_connected);
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy);
+
+	if (!wifi_connected &&
+	    BT_8192E_1ANT_BT_STATUS_NON_CONNECTED_IDLE ==
+	    coex_dm->bt_status) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			"[BTCoex], Wifi non connected-idle + BT non connected-idle!!\n");
+		BTC_TRACE(trace_buf);
+		/* halbtc8192e1ant_sw_mechanism(btcoexist, false); */
+
+		common = true;
+	} else if (wifi_connected &&
+		   (BT_8192E_1ANT_BT_STATUS_NON_CONNECTED_IDLE ==
+		    coex_dm->bt_status)) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			"[BTCoex], Wifi connected + BT non connected-idle!!\n");
+		BTC_TRACE(trace_buf);
+		/* halbtc8192e1ant_sw_mechanism(btcoexist, false); */
+
+		common = true;
+	} else if (!wifi_connected &&
+		(BT_8192E_1ANT_BT_STATUS_CONNECTED_IDLE == coex_dm->bt_status)) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			"[BTCoex], Wifi non connected-idle + BT connected-idle!!\n");
+		BTC_TRACE(trace_buf);
+		/* halbtc8192e1ant_sw_mechanism(btcoexist, false); */
+
+		common = true;
+	} else if (wifi_connected &&
+		(BT_8192E_1ANT_BT_STATUS_CONNECTED_IDLE == coex_dm->bt_status)) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], Wifi connected + BT connected-idle!!\n");
+		BTC_TRACE(trace_buf);
+		/* halbtc8192e1ant_sw_mechanism(btcoexist, false); */
+
+		common = true;
+	} else if (!wifi_connected &&
+		(BT_8192E_1ANT_BT_STATUS_CONNECTED_IDLE != coex_dm->bt_status)) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], Wifi non connected-idle + BT Busy!!\n");
+		BTC_TRACE(trace_buf);
+		/* halbtc8192e1ant_sw_mechanism(btcoexist, false); */
+
+		common = true;
+	} else {
+		if (wifi_busy) {
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				"[BTCoex], Wifi Connected-Busy + BT Busy!!\n");
+			BTC_TRACE(trace_buf);
+		} else {
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				"[BTCoex], Wifi Connected-Idle + BT Busy!!\n");
+			BTC_TRACE(trace_buf);
+		}
+
+		common = false;
+	}
+
+	return common;
+}
+
+
+void halbtc8192e1ant_tdma_duration_adjust_for_acl(IN struct btc_coexist
+		*btcoexist, IN u8 wifi_status)
+{
+	static s32		up, dn, m, n, wait_count;
+	s32			result;   /* 0: no change, +1: increase WiFi duration, -1: decrease WiFi duration */
+	u8			retry_count = 0, bt_info_ext;
+	boolean			wifi_busy = false;
+	/*static boolean	pre_wifi_busy = false;*/
+
+	if (BT_8192E_1ANT_WIFI_STATUS_CONNECTED_BUSY == wifi_status)
+		wifi_busy = true;
+	else
+		wifi_busy = false;
+
+	if ((BT_8192E_1ANT_WIFI_STATUS_NON_CONNECTED_ASSO_AUTH_SCAN ==
+	     wifi_status) ||
+	    (BT_8192E_1ANT_WIFI_STATUS_CONNECTED_SCAN == wifi_status) ||
+	    (BT_8192E_1ANT_WIFI_STATUS_CONNECTED_SPECIFIC_PKT ==
+	     wifi_status)) {
+		if (coex_dm->cur_ps_tdma != 1 &&
+		    coex_dm->cur_ps_tdma != 2 &&
+		    coex_dm->cur_ps_tdma != 3 &&
+		    coex_dm->cur_ps_tdma != 9) {
+			halbtc8192e1ant_ps_tdma(btcoexist, NORMAL_EXEC, true,
+						9);
+			coex_dm->ps_tdma_du_adj_type = 9;
+
+			up = 0;
+			dn = 0;
+			m = 1;
+			n = 3;
+			result = 0;
+			wait_count = 0;
+		}
+		return;
+	}
+
+	if (!coex_dm->auto_tdma_adjust) {
+		coex_dm->auto_tdma_adjust = true;
+
+		halbtc8192e1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 2);
+		coex_dm->ps_tdma_du_adj_type = 2;
+		/* ============ */
+		up = 0;
+		dn = 0;
+		m = 1;
+		n = 3;
+		result = 0;
+		wait_count = 0;
+	} else {
+		/* acquire the BT TRx retry count from BT_Info byte2 */
+		retry_count = coex_sta->bt_retry_cnt;
+		bt_info_ext = coex_sta->bt_info_ext;
+
+		if ((coex_sta->low_priority_tx) > 1050 ||
+		    (coex_sta->low_priority_rx) > 1250)
+			retry_count++;
+
+		result = 0;
+		wait_count++;
+
+		if (retry_count ==
+		    0) { /* no retry in the last 2-second duration */
+			up++;
+			dn--;
+
+			if (dn <= 0)
+				dn = 0;
+
+			if (up >= n) {	/* if retry count during continuous n*2 seconds is 0, enlarge WiFi duration */
+				wait_count = 0;
+				n = 3;
+				up = 0;
+				dn = 0;
+				result = 1;
+			}
+		} else if (retry_count <=
+			   3) {	/* <=3 retry in the last 2-second duration */
+			up--;
+			dn++;
+
+			if (up <= 0)
+				up = 0;
+
+			if (dn == 2) {	/* if continuous 2 retry count(every 2 seconds) >0 and < 3, reduce WiFi duration */
+				if (wait_count <= 2)
+					m++; /* to avoid loop between the two levels */
+				else
+					m = 1;
+
+				if (m >= 20)  /* maximum of m = 20 ' will recheck if need to adjust wifi duration in maximum time interval 120 seconds */
+					m = 20;
+
+				n = 3 * m;
+				up = 0;
+				dn = 0;
+				wait_count = 0;
+				result = -1;
+			}
+		} else { /* retry count > 3, once retry count > 3, to reduce WiFi duration */
+			if (wait_count == 1)
+				m++; /* to avoid loop between the two levels */
+			else
+				m = 1;
+
+			if (m >= 20)  /* maximum of m = 20 ' will recheck if need to adjust wifi duration in maximum time interval 120 seconds */
+				m = 20;
+
+			n = 3 * m;
+			up = 0;
+			dn = 0;
+			wait_count = 0;
+			result = -1;
+		}
+
+		if (result == -1) {
+			if ((BT_INFO_8192E_1ANT_A2DP_BASIC_RATE(bt_info_ext)) &&
+			    ((coex_dm->cur_ps_tdma == 1) ||
+			     (coex_dm->cur_ps_tdma == 2))) {
+				halbtc8192e1ant_ps_tdma(btcoexist, NORMAL_EXEC,
+							true, 9);
+				coex_dm->ps_tdma_du_adj_type = 9;
+			} else if (coex_dm->cur_ps_tdma == 1) {
+				halbtc8192e1ant_ps_tdma(btcoexist, NORMAL_EXEC,
+							true, 2);
+				coex_dm->ps_tdma_du_adj_type = 2;
+			} else if (coex_dm->cur_ps_tdma == 2) {
+				halbtc8192e1ant_ps_tdma(btcoexist, NORMAL_EXEC,
+							true, 9);
+				coex_dm->ps_tdma_du_adj_type = 9;
+			} else if (coex_dm->cur_ps_tdma == 9) {
+				halbtc8192e1ant_ps_tdma(btcoexist, NORMAL_EXEC,
+							true, 11);
+				coex_dm->ps_tdma_du_adj_type = 11;
+			}
+		} else if (result == 1) {
+			if ((BT_INFO_8192E_1ANT_A2DP_BASIC_RATE(bt_info_ext)) &&
+			    ((coex_dm->cur_ps_tdma == 1) ||
+			     (coex_dm->cur_ps_tdma == 2))) {
+				halbtc8192e1ant_ps_tdma(btcoexist, NORMAL_EXEC,
+							true, 9);
+				coex_dm->ps_tdma_du_adj_type = 9;
+			} else if (coex_dm->cur_ps_tdma == 11) {
+				halbtc8192e1ant_ps_tdma(btcoexist, NORMAL_EXEC,
+							true, 9);
+				coex_dm->ps_tdma_du_adj_type = 9;
+			} else if (coex_dm->cur_ps_tdma == 9) {
+				halbtc8192e1ant_ps_tdma(btcoexist, NORMAL_EXEC,
+							true, 2);
+				coex_dm->ps_tdma_du_adj_type = 2;
+			} else if (coex_dm->cur_ps_tdma == 2) {
+				halbtc8192e1ant_ps_tdma(btcoexist, NORMAL_EXEC,
+							true, 1);
+				coex_dm->ps_tdma_du_adj_type = 1;
+			}
+		} else { /* no change */
+			/* Bryant Modify
+			if(wifi_busy != pre_wifi_busy)
+			{
+				pre_wifi_busy = wifi_busy;
+				halbtc8192e1ant_ps_tdma(btcoexist, FORCE_EXEC, true, coex_dm->cur_ps_tdma);
+			}
+			*/
+		}
+
+		if (coex_dm->cur_ps_tdma != 1 &&
+		    coex_dm->cur_ps_tdma != 2 &&
+		    coex_dm->cur_ps_tdma != 9 &&
+		    coex_dm->cur_ps_tdma != 11) {
+			/* recover to previous adjust type */
+			halbtc8192e1ant_ps_tdma(btcoexist, NORMAL_EXEC, true,
+						coex_dm->ps_tdma_du_adj_type);
+		}
+	}
+}
+
+void halbtc8192e1ant_ps_tdma_check_for_power_save_state(
+	IN struct btc_coexist *btcoexist, IN boolean new_ps_state)
+{
+	u8	lps_mode = 0x0;
+
+	btcoexist->btc_get(btcoexist, BTC_GET_U1_LPS_MODE, &lps_mode);
+
+	if (lps_mode) {	/* already under LPS state */
+		if (new_ps_state) {
+			/* keep state under LPS, do nothing. */
+		} else {
+			/* will leave LPS state, turn off psTdma first */
+			halbtc8192e1ant_ps_tdma(btcoexist, NORMAL_EXEC, false,
+						0);
+		}
+	} else {					/* NO PS state */
+		if (new_ps_state) {
+			/* will enter LPS state, turn off psTdma first */
+			halbtc8192e1ant_ps_tdma(btcoexist, NORMAL_EXEC, false,
+						0);
+		} else {
+			/* keep state under NO PS state, do nothing. */
+		}
+	}
+}
+
+void halbtc8192e1ant_power_save_state(IN struct btc_coexist *btcoexist,
+			      IN u8 ps_type, IN u8 lps_val, IN u8 rpwm_val)
+{
+	boolean		low_pwr_disable = false;
+
+	switch (ps_type) {
+	case BTC_PS_WIFI_NATIVE:
+		/* recover to original 32k low power setting */
+		low_pwr_disable = false;
+		btcoexist->btc_set(btcoexist,
+				   BTC_SET_ACT_DISABLE_LOW_POWER,
+				   &low_pwr_disable);
+		btcoexist->btc_set(btcoexist, BTC_SET_ACT_NORMAL_LPS,
+				   NULL);
+		coex_sta->force_lps_on = false;
+		break;
+	case BTC_PS_LPS_ON:
+		halbtc8192e1ant_ps_tdma_check_for_power_save_state(
+			btcoexist, true);
+		halbtc8192e1ant_lps_rpwm(btcoexist, NORMAL_EXEC,
+					 lps_val, rpwm_val);
+		/* when coex force to enter LPS, do not enter 32k low power. */
+		low_pwr_disable = true;
+		btcoexist->btc_set(btcoexist,
+				   BTC_SET_ACT_DISABLE_LOW_POWER,
+				   &low_pwr_disable);
+		/* power save must executed before psTdma.			 */
+		btcoexist->btc_set(btcoexist, BTC_SET_ACT_ENTER_LPS,
+				   NULL);
+		coex_sta->force_lps_on = true;
+		break;
+	case BTC_PS_LPS_OFF:
+		halbtc8192e1ant_ps_tdma_check_for_power_save_state(
+			btcoexist, false);
+		btcoexist->btc_set(btcoexist, BTC_SET_ACT_LEAVE_LPS,
+				   NULL);
+		coex_sta->force_lps_on = false;
+		break;
+	default:
+		break;
+	}
+}
+
+void halbtc8192e1ant_action_wifi_only(IN struct btc_coexist *btcoexist)
+{
+	halbtc8192e1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0);
+	halbtc8192e1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 9);
+}
+
+void halbtc8192e1ant_monitor_bt_enable_disable(IN struct btc_coexist *btcoexist)
+{
+	static u32		bt_disable_cnt = 0;
+	boolean			bt_active = true, bt_disabled = false;
+
+	/* This function check if bt is disabled */
+
+	if (coex_sta->high_priority_tx == 0 &&
+	    coex_sta->high_priority_rx == 0 &&
+	    coex_sta->low_priority_tx == 0 &&
+	    coex_sta->low_priority_rx == 0)
+		bt_active = false;
+	if (coex_sta->high_priority_tx == 0xffff &&
+	    coex_sta->high_priority_rx == 0xffff &&
+	    coex_sta->low_priority_tx == 0xffff &&
+	    coex_sta->low_priority_rx == 0xffff)
+		bt_active = false;
+	if (bt_active) {
+		bt_disable_cnt = 0;
+		bt_disabled = false;
+		btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_DISABLE,
+				   &bt_disabled);
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], BT is enabled !!\n");
+		BTC_TRACE(trace_buf);
+	} else {
+		bt_disable_cnt++;
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], bt all counters=0, %d times!!\n",
+			    bt_disable_cnt);
+		BTC_TRACE(trace_buf);
+		if (bt_disable_cnt >= 2) {
+			bt_disabled = true;
+			btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_DISABLE,
+					   &bt_disabled);
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				    "[BTCoex], BT is disabled !!\n");
+			BTC_TRACE(trace_buf);
+			halbtc8192e1ant_action_wifi_only(btcoexist);
+		}
+	}
+	if (coex_sta->bt_disabled != bt_disabled) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], BT is from %s to %s!!\n",
+			    (coex_sta->bt_disabled ? "disabled" : "enabled"),
+			    (bt_disabled ? "disabled" : "enabled"));
+		BTC_TRACE(trace_buf);
+		coex_sta->bt_disabled = bt_disabled;
+		if (!bt_disabled) {
+		} else {
+			btcoexist->btc_set(btcoexist, BTC_SET_ACT_LEAVE_LPS,
+					   NULL);
+			btcoexist->btc_set(btcoexist, BTC_SET_ACT_NORMAL_LPS,
+					   NULL);
+		}
+	}
+}
+
+/* *********************************************
+ *
+ *	Software Coex Mechanism start
+ *
+ * ********************************************* */
+
+/* SCO only or SCO+PAN(HS) */
+
+/*
+void halbtc8192e1ant_action_sco(IN struct btc_coexist* btcoexist)
+{
+	halbtc8192e1ant_sw_mechanism(btcoexist, true);
+}
+
+
+void halbtc8192e1ant_action_hid(IN struct btc_coexist* btcoexist)
+{
+	halbtc8192e1ant_sw_mechanism(btcoexist, true);
+}
+
+
+void halbtc8192e1ant_action_a2dp(IN struct btc_coexist* btcoexist)
+{
+	halbtc8192e1ant_sw_mechanism(btcoexist, false);
+}
+
+void halbtc8192e1ant_action_a2dp_pan_hs(IN struct btc_coexist* btcoexist)
+{
+	halbtc8192e1ant_sw_mechanism(btcoexist, false);
+}
+
+void halbtc8192e1ant_action_pan_edr(IN struct btc_coexist* btcoexist)
+{
+	halbtc8192e1ant_sw_mechanism(btcoexist, false);
+}
+
+
+void halbtc8192e1ant_action_pan_hs(IN struct btc_coexist* btcoexist)
+{
+	halbtc8192e1ant_sw_mechanism(btcoexist, false);
+}
+
+
+void halbtc8192e1ant_action_pan_edr_a2dp(IN struct btc_coexist* btcoexist)
+{
+	halbtc8192e1ant_sw_mechanism(btcoexist, false);
+}
+
+void halbtc8192e1ant_action_pan_edr_hid(IN struct btc_coexist* btcoexist)
+{
+	halbtc8192e1ant_sw_mechanism(btcoexist, true);
+}
+
+
+void halbtc8192e1ant_action_hid_a2dp_pan_edr(IN struct btc_coexist* btcoexist)
+{
+	halbtc8192e1ant_sw_mechanism(btcoexist, true);
+}
+
+void halbtc8192e1ant_action_hid_a2dp(IN struct btc_coexist* btcoexist)
+{
+	halbtc8192e1ant_sw_mechanism(btcoexist, true);
+}
+
+*/
+
+/* *********************************************
+ *
+ *	Non-Software Coex Mechanism start
+ *
+ * ********************************************* */
+void halbtc8192e1ant_action_wifi_multi_port(IN struct btc_coexist *btcoexist)
+{
+	halbtc8192e1ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, 0x0,
+					 0x0);
+
+	halbtc8192e1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 8);
+	halbtc8192e1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 2);
+}
+
+void halbtc8192e1ant_action_hs(IN struct btc_coexist *btcoexist)
+{
+	halbtc8192e1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 5);
+	halbtc8192e1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 2);
+}
+
+void halbtc8192e1ant_action_bt_inquiry(IN struct btc_coexist *btcoexist)
+{
+	struct  btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
+	boolean			wifi_connected = false, ap_enable = false, wifi_busy = false,
+				bt_busy = false;
+
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_AP_MODE_ENABLE,
+			   &ap_enable);
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED,
+			   &wifi_connected);
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy);
+	btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_TRAFFIC_BUSY, &bt_busy);
+
+	if ((!wifi_connected) && (!coex_sta->wifi_is_high_pri_task)) {
+		halbtc8192e1ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE,
+						 0x0, 0x0);
+		halbtc8192e1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 8);
+
+		halbtc8192e1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0);
+	} else if ((bt_link_info->sco_exist) || (bt_link_info->hid_exist) ||
+		   (bt_link_info->a2dp_exist)) {
+		/* SCO/HID/A2DP  busy */
+		halbtc8192e1ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE,
+						 0x0, 0x0);
+		halbtc8192e1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 32);
+
+		halbtc8192e1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4);
+	} else if ((bt_link_info->pan_exist) || (wifi_busy)) {
+		halbtc8192e1ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE,
+						 0x0, 0x0);
+		halbtc8192e1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 20);
+
+		halbtc8192e1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4);
+	} else {
+		halbtc8192e1ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE,
+						 0x0, 0x0);
+		halbtc8192e1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 8);
+
+		halbtc8192e1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 7);
+	}
+}
+
+void halbtc8192e1ant_action_bt_sco_hid_only_busy(IN struct btc_coexist
+		*btcoexist, IN u8 wifi_status)
+{
+	struct  btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
+	boolean	wifi_connected = false;
+
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED,
+			   &wifi_connected);
+
+	/* tdma and coex table */
+
+	if (bt_link_info->sco_exist) {
+		halbtc8192e1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 5);
+		halbtc8192e1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 5);
+	} else { /* HID */
+		halbtc8192e1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 6);
+		halbtc8192e1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 5);
+	}
+}
+
+void halbtc8192e1ant_action_wifi_connected_bt_acl_busy(IN struct btc_coexist
+		*btcoexist, IN u8 wifi_status)
+{
+	u8		bt_rssi_state;
+
+	struct  btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
+
+	bt_rssi_state = halbtc8192e1ant_bt_rssi_state(2, 28, 0);
+
+	if ((coex_sta->low_priority_rx >= 1000)  &&
+	    (coex_sta->low_priority_rx != 65535))
+		bt_link_info->slave_role = true;
+	else
+		bt_link_info->slave_role = false;
+
+	if (bt_link_info->hid_only) { /* HID */
+		halbtc8192e1ant_action_bt_sco_hid_only_busy(btcoexist,
+				wifi_status);
+		coex_dm->auto_tdma_adjust = false;
+		return;
+	} else if (bt_link_info->a2dp_only) { /* A2DP		 */
+		if (BT_8192E_1ANT_WIFI_STATUS_CONNECTED_IDLE == wifi_status) {
+			halbtc8192e1ant_ps_tdma(btcoexist, NORMAL_EXEC, true,
+						32);
+			halbtc8192e1ant_coex_table_with_type(btcoexist,
+							     NORMAL_EXEC, 4);
+			coex_dm->auto_tdma_adjust = false;
+		} else {
+			halbtc8192e1ant_tdma_duration_adjust_for_acl(btcoexist,
+					wifi_status);
+#if 0
+			if (coex_sta->cck_lock)
+				halbtc8192e1ant_coex_table_with_type(btcoexist,
+							     NORMAL_EXEC, 3);
+			else
+#endif
+				halbtc8192e1ant_coex_table_with_type(btcoexist,
+							     NORMAL_EXEC, 4);
+			coex_dm->auto_tdma_adjust = true;
+		}
+	} else if (((bt_link_info->a2dp_exist) && (bt_link_info->pan_exist)) ||
+		   (bt_link_info->hid_exist && bt_link_info->a2dp_exist &&
+		bt_link_info->pan_exist)) { /* A2DP+PAN(OPP,FTP), HID+A2DP+PAN(OPP,FTP) */
+		halbtc8192e1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 13);
+		halbtc8192e1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4);
+		coex_dm->auto_tdma_adjust = false;
+	} else if (bt_link_info->hid_exist &&
+		   bt_link_info->a2dp_exist) { /* HID+A2DP */
+		halbtc8192e1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 14);
+		coex_dm->auto_tdma_adjust = false;
+
+		halbtc8192e1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 3);
+	} else if ((bt_link_info->pan_only) || (bt_link_info->hid_exist &&
+		bt_link_info->pan_exist)) { /* PAN(OPP,FTP), HID+PAN(OPP,FTP)			 */
+		halbtc8192e1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 3);
+		halbtc8192e1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4);
+		coex_dm->auto_tdma_adjust = false;
+	} else {
+		/* BT no-profile busy (0x9) */
+		halbtc8192e1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 32);
+		halbtc8192e1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4);
+		coex_dm->auto_tdma_adjust = false;
+	}
+}
+
+void halbtc8192e1ant_action_wifi_not_connected(IN struct btc_coexist *btcoexist)
+{
+	/* power save state */
+	halbtc8192e1ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, 0x0,
+					 0x0);
+
+	/* tdma and coex table */
+	halbtc8192e1ant_ps_tdma(btcoexist, FORCE_EXEC, false, 8);
+	halbtc8192e1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0);
+}
+
+void halbtc8192e1ant_action_wifi_not_connected_scan(IN struct btc_coexist
+		*btcoexist)
+{
+	struct  btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
+
+	halbtc8192e1ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, 0x0,
+					 0x0);
+
+	/* tdma and coex table */
+	if (BT_8192E_1ANT_BT_STATUS_ACL_BUSY == coex_dm->bt_status) {
+		if (bt_link_info->a2dp_exist) {
+			halbtc8192e1ant_ps_tdma(btcoexist, NORMAL_EXEC, true,
+						32);
+			halbtc8192e1ant_coex_table_with_type(btcoexist,
+							     NORMAL_EXEC, 4);
+		} else if (bt_link_info->a2dp_exist &&
+			   bt_link_info->pan_exist) {
+			halbtc8192e1ant_ps_tdma(btcoexist, NORMAL_EXEC, true,
+						22);
+			halbtc8192e1ant_coex_table_with_type(btcoexist,
+							     NORMAL_EXEC, 4);
+		} else {
+			halbtc8192e1ant_ps_tdma(btcoexist, NORMAL_EXEC, true,
+						20);
+			halbtc8192e1ant_coex_table_with_type(btcoexist,
+							     NORMAL_EXEC, 4);
+		}
+	} else if ((BT_8192E_1ANT_BT_STATUS_SCO_BUSY == coex_dm->bt_status) ||
+		   (BT_8192E_1ANT_BT_STATUS_ACL_SCO_BUSY ==
+		    coex_dm->bt_status)) {
+		halbtc8192e1ant_action_bt_sco_hid_only_busy(btcoexist,
+				BT_8192E_1ANT_WIFI_STATUS_CONNECTED_SCAN);
+	} else {
+		/* Bryant Add */
+		halbtc8192e1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 8);
+		halbtc8192e1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 2);
+	}
+}
+
+void halbtc8192e1ant_action_wifi_not_connected_asso_auth(
+	IN struct btc_coexist *btcoexist)
+{
+	struct  btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
+
+	halbtc8192e1ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, 0x0,
+					 0x0);
+
+	/* tdma and coex table */
+	if ((bt_link_info->sco_exist)  || (bt_link_info->hid_exist) ||
+	    (bt_link_info->a2dp_exist)) {
+		halbtc8192e1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 32);
+		halbtc8192e1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4);
+	} else if (bt_link_info->pan_exist) {
+		halbtc8192e1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 20);
+		halbtc8192e1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4);
+	} else {
+		halbtc8192e1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 8);
+		halbtc8192e1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 2);
+	}
+}
+
+void halbtc8192e1ant_action_wifi_connected_scan(IN struct btc_coexist
+		*btcoexist)
+{
+	struct  btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
+
+	halbtc8192e1ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, 0x0,
+					 0x0);
+
+	/* tdma and coex table */
+	if (BT_8192E_1ANT_BT_STATUS_ACL_BUSY == coex_dm->bt_status) {
+		if (bt_link_info->a2dp_exist) {
+			halbtc8192e1ant_ps_tdma(btcoexist, NORMAL_EXEC, true,
+						32);
+			halbtc8192e1ant_coex_table_with_type(btcoexist,
+							     NORMAL_EXEC, 4);
+		} else if (bt_link_info->a2dp_exist &&
+			   bt_link_info->pan_exist) {
+			halbtc8192e1ant_ps_tdma(btcoexist, NORMAL_EXEC, true,
+						22);
+			halbtc8192e1ant_coex_table_with_type(btcoexist,
+							     NORMAL_EXEC, 4);
+		} else {
+			halbtc8192e1ant_ps_tdma(btcoexist, NORMAL_EXEC, true,
+						20);
+			halbtc8192e1ant_coex_table_with_type(btcoexist,
+							     NORMAL_EXEC, 4);
+		}
+	} else if ((BT_8192E_1ANT_BT_STATUS_SCO_BUSY == coex_dm->bt_status) ||
+		   (BT_8192E_1ANT_BT_STATUS_ACL_SCO_BUSY ==
+		    coex_dm->bt_status)) {
+		halbtc8192e1ant_action_bt_sco_hid_only_busy(btcoexist,
+				BT_8192E_1ANT_WIFI_STATUS_CONNECTED_SCAN);
+	} else {
+		/* Bryant Add */
+		halbtc8192e1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 8);
+		halbtc8192e1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 2);
+	}
+}
+
+void halbtc8192e1ant_action_wifi_connected_specific_packet(
+	IN struct btc_coexist *btcoexist)
+{
+	struct  btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
+
+	halbtc8192e1ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, 0x0,
+					 0x0);
+
+	/* tdma and coex table */
+	if ((bt_link_info->sco_exist) || (bt_link_info->hid_exist) ||
+	    (bt_link_info->a2dp_exist)) {
+		halbtc8192e1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 32);
+		halbtc8192e1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4);
+	} else if (bt_link_info->pan_exist) {
+		halbtc8192e1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 20);
+		halbtc8192e1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4);
+	} else {
+		halbtc8192e1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 8);
+		halbtc8192e1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 2);
+	}
+}
+
+void halbtc8192e1ant_action_wifi_connected(IN struct btc_coexist *btcoexist)
+{
+	boolean	wifi_busy = false;
+	boolean		scan = false, link = false, roam = false;
+	boolean		under_4way = false, ap_enable = false;
+
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+		    "[BTCoex], CoexForWifiConnect()===>\n");
+	BTC_TRACE(trace_buf);
+
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_4_WAY_PROGRESS,
+			   &under_4way);
+	if (under_4way) {
+		halbtc8192e1ant_action_wifi_connected_specific_packet(btcoexist);
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			"[BTCoex], CoexForWifiConnect(), return for wifi is under 4way<===\n");
+		BTC_TRACE(trace_buf);
+		return;
+	}
+
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_SCAN, &scan);
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_LINK, &link);
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_ROAM, &roam);
+	if (scan || link || roam) {
+		if (scan)
+			halbtc8192e1ant_action_wifi_connected_scan(btcoexist);
+		else
+			halbtc8192e1ant_action_wifi_connected_specific_packet(
+				btcoexist);
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			"[BTCoex], CoexForWifiConnect(), return for wifi is under scan<===\n");
+		BTC_TRACE(trace_buf);
+		return;
+	}
+
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_AP_MODE_ENABLE,
+			   &ap_enable);
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy);
+
+	/* power save state */
+	if (!ap_enable &&
+	    BT_8192E_1ANT_BT_STATUS_ACL_BUSY == coex_dm->bt_status &&
+	    !btcoexist->bt_link_info.hid_only) {
+		if (btcoexist->bt_link_info.a2dp_only) {	/* A2DP */
+			if (!wifi_busy)
+				halbtc8192e1ant_power_save_state(btcoexist,
+						 BTC_PS_WIFI_NATIVE, 0x0, 0x0);
+			else { /* busy */
+				if (coex_sta->scan_ap_num >=
+				    BT_8192E_1ANT_WIFI_NOISY_THRESH)  /* no force LPS, no PS-TDMA, use pure TDMA */
+					halbtc8192e1ant_power_save_state(
+						btcoexist, BTC_PS_WIFI_NATIVE,
+						0x0, 0x0);
+				else
+					halbtc8192e1ant_power_save_state(
+						btcoexist, BTC_PS_LPS_ON, 0x50,
+						0x4);
+			}
+		} else if ((coex_sta->pan_exist == false) &&
+			   (coex_sta->a2dp_exist == false) &&
+			   (coex_sta->hid_exist == false))
+			halbtc8192e1ant_power_save_state(btcoexist,
+						 BTC_PS_WIFI_NATIVE, 0x0, 0x0);
+		else
+			halbtc8192e1ant_power_save_state(btcoexist,
+						 BTC_PS_LPS_ON, 0x50, 0x4);
+	} else
+		halbtc8192e1ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE,
+						 0x0, 0x0);
+
+	/* tdma and coex table */
+	if (!wifi_busy) {
+		if (BT_8192E_1ANT_BT_STATUS_ACL_BUSY == coex_dm->bt_status) {
+			halbtc8192e1ant_action_wifi_connected_bt_acl_busy(
+				btcoexist,
+				BT_8192E_1ANT_WIFI_STATUS_CONNECTED_IDLE);
+		} else if ((BT_8192E_1ANT_BT_STATUS_SCO_BUSY ==
+			    coex_dm->bt_status) ||
+			   (BT_8192E_1ANT_BT_STATUS_ACL_SCO_BUSY ==
+			    coex_dm->bt_status)) {
+			halbtc8192e1ant_action_bt_sco_hid_only_busy(btcoexist,
+				BT_8192E_1ANT_WIFI_STATUS_CONNECTED_IDLE);
+		} else {
+			halbtc8192e1ant_ps_tdma(btcoexist, NORMAL_EXEC, false,
+						8);
+
+			if ((coex_sta->high_priority_tx) +
+			    (coex_sta->high_priority_rx) <= 60)
+				halbtc8192e1ant_coex_table_with_type(btcoexist,
+							     NORMAL_EXEC, 2);
+			else
+				halbtc8192e1ant_coex_table_with_type(btcoexist,
+							     NORMAL_EXEC, 7);
+		}
+	} else {
+		if (BT_8192E_1ANT_BT_STATUS_ACL_BUSY == coex_dm->bt_status) {
+			halbtc8192e1ant_action_wifi_connected_bt_acl_busy(
+				btcoexist,
+				BT_8192E_1ANT_WIFI_STATUS_CONNECTED_BUSY);
+		} else if ((BT_8192E_1ANT_BT_STATUS_SCO_BUSY ==
+			    coex_dm->bt_status) ||
+			   (BT_8192E_1ANT_BT_STATUS_ACL_SCO_BUSY ==
+			    coex_dm->bt_status)) {
+			halbtc8192e1ant_action_bt_sco_hid_only_busy(btcoexist,
+				BT_8192E_1ANT_WIFI_STATUS_CONNECTED_BUSY);
+		} else {
+			halbtc8192e1ant_ps_tdma(btcoexist, NORMAL_EXEC, false,
+						8);
+
+			if ((coex_sta->high_priority_tx) +
+			    (coex_sta->high_priority_rx) <= 60)
+				halbtc8192e1ant_coex_table_with_type(btcoexist,
+							     NORMAL_EXEC, 2);
+			else
+				halbtc8192e1ant_coex_table_with_type(btcoexist,
+							     NORMAL_EXEC, 7);
+		}
+	}
+}
+
+void halbtc8192e1ant_run_sw_coexist_mechanism(IN struct btc_coexist *btcoexist)
+{
+	u8				algorithm = 0;
+
+	algorithm = halbtc8192e1ant_action_algorithm(btcoexist);
+	coex_dm->cur_algorithm = algorithm;
+
+	if (halbtc8192e1ant_is_common_action(btcoexist)) {
+
+	} else {
+		switch (coex_dm->cur_algorithm) {
+		case BT_8192E_1ANT_COEX_ALGO_SCO:
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				    "[BTCoex], Action algorithm = SCO.\n");
+			BTC_TRACE(trace_buf);
+			/* halbtc8192e1ant_action_sco(btcoexist); */
+			break;
+		case BT_8192E_1ANT_COEX_ALGO_HID:
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				    "[BTCoex], Action algorithm = HID.\n");
+			BTC_TRACE(trace_buf);
+			/* halbtc8192e1ant_action_hid(btcoexist); */
+			break;
+		case BT_8192E_1ANT_COEX_ALGO_A2DP:
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				    "[BTCoex], Action algorithm = A2DP.\n");
+			BTC_TRACE(trace_buf);
+			/* halbtc8192e1ant_action_a2dp(btcoexist); */
+			break;
+		case BT_8192E_1ANT_COEX_ALGO_A2DP_PANHS:
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				"[BTCoex], Action algorithm = A2DP+PAN(HS).\n");
+			BTC_TRACE(trace_buf);
+			/* halbtc8192e1ant_action_a2dp_pan_hs(btcoexist); */
+			break;
+		case BT_8192E_1ANT_COEX_ALGO_PANEDR:
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				    "[BTCoex], Action algorithm = PAN(EDR).\n");
+			BTC_TRACE(trace_buf);
+			/* halbtc8192e1ant_action_pan_edr(btcoexist); */
+			break;
+		case BT_8192E_1ANT_COEX_ALGO_PANHS:
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				    "[BTCoex], Action algorithm = HS mode.\n");
+			BTC_TRACE(trace_buf);
+			/* halbtc8192e1ant_action_pan_hs(btcoexist); */
+			break;
+		case BT_8192E_1ANT_COEX_ALGO_PANEDR_A2DP:
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				    "[BTCoex], Action algorithm = PAN+A2DP.\n");
+			BTC_TRACE(trace_buf);
+			/* halbtc8192e1ant_action_pan_edr_a2dp(btcoexist); */
+			break;
+		case BT_8192E_1ANT_COEX_ALGO_PANEDR_HID:
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				"[BTCoex], Action algorithm = PAN(EDR)+HID.\n");
+			BTC_TRACE(trace_buf);
+			/* halbtc8192e1ant_action_pan_edr_hid(btcoexist); */
+			break;
+		case BT_8192E_1ANT_COEX_ALGO_HID_A2DP_PANEDR:
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				"[BTCoex], Action algorithm = HID+A2DP+PAN.\n");
+			BTC_TRACE(trace_buf);
+			/* halbtc8192e1ant_action_hid_a2dp_pan_edr(btcoexist); */
+			break;
+		case BT_8192E_1ANT_COEX_ALGO_HID_A2DP:
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				    "[BTCoex], Action algorithm = HID+A2DP.\n");
+			BTC_TRACE(trace_buf);
+			/* halbtc8192e1ant_action_hid_a2dp(btcoexist); */
+			break;
+		default:
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				"[BTCoex], Action algorithm = coexist All Off!!\n");
+			BTC_TRACE(trace_buf);
+			/* halbtc8192e1ant_coex_all_off(btcoexist); */
+			break;
+		}
+		coex_dm->pre_algorithm = coex_dm->cur_algorithm;
+	}
+}
+
+void halbtc8192e1ant_run_coexist_mechanism(IN struct btc_coexist *btcoexist)
+{
+	struct  btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
+	boolean	wifi_connected = false, bt_hs_on = false;
+	boolean	increase_scan_dev_num = false;
+	boolean	bt_ctrl_agg_buf_size = false;
+	boolean	miracast_plus_bt = false;
+	u8	agg_buf_size = 5;
+	u32	wifi_link_status = 0;
+	u32	num_of_wifi_link = 0;
+
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+		    "[BTCoex], RunCoexistMechanism()===>\n");
+	BTC_TRACE(trace_buf);
+
+	if (btcoexist->manual_control) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			"[BTCoex], RunCoexistMechanism(), return for Manual CTRL <===\n");
+		BTC_TRACE(trace_buf);
+		return;
+	}
+
+	if (btcoexist->stop_coex_dm) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			"[BTCoex], RunCoexistMechanism(), return for Stop Coex DM <===\n");
+		BTC_TRACE(trace_buf);
+		return;
+	}
+
+	if (coex_sta->under_ips) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], wifi is under IPS !!!\n");
+		BTC_TRACE(trace_buf);
+		return;
+	}
+
+	if ((BT_8192E_1ANT_BT_STATUS_ACL_BUSY == coex_dm->bt_status) ||
+	    (BT_8192E_1ANT_BT_STATUS_SCO_BUSY == coex_dm->bt_status) ||
+	    (BT_8192E_1ANT_BT_STATUS_ACL_SCO_BUSY == coex_dm->bt_status))
+		increase_scan_dev_num = true;
+
+	btcoexist->btc_set(btcoexist, BTC_SET_BL_INC_SCAN_DEV_NUM,
+			   &increase_scan_dev_num);
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED,
+			   &wifi_connected);
+
+	btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_LINK_STATUS,
+			   &wifi_link_status);
+	num_of_wifi_link = wifi_link_status >> 16;
+
+	if ((num_of_wifi_link >= 2) ||
+	    (wifi_link_status & WIFI_P2P_GO_CONNECTED)) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			"############# [BTCoex],  Multi-Port num_of_wifi_link = %d, wifi_link_status = 0x%x\n",
+			    num_of_wifi_link, wifi_link_status);
+		BTC_TRACE(trace_buf);
+
+		if (bt_link_info->bt_link_exist) {
+			halbtc8192e1ant_limited_tx(btcoexist, NORMAL_EXEC, 1, 1,
+						   0, 1);
+			miracast_plus_bt = true;
+		} else {
+			halbtc8192e1ant_limited_tx(btcoexist, NORMAL_EXEC, 0, 0,
+						   0, 0);
+			miracast_plus_bt = false;
+		}
+		btcoexist->btc_set(btcoexist, BTC_SET_BL_MIRACAST_PLUS_BT,
+				   &miracast_plus_bt);
+		halbtc8192e1ant_limited_rx(btcoexist, NORMAL_EXEC, false,
+					   bt_ctrl_agg_buf_size, agg_buf_size);
+
+		if ((bt_link_info->a2dp_exist) &&
+		    (coex_sta->c2h_bt_inquiry_page)) {
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				"############# [BTCoex],  BT Is Inquirying\n");
+			BTC_TRACE(trace_buf);
+			halbtc8192e1ant_action_bt_inquiry(btcoexist);
+		} else
+			halbtc8192e1ant_action_wifi_multi_port(btcoexist);
+
+		return;
+	}
+
+	miracast_plus_bt = false;
+	btcoexist->btc_set(btcoexist, BTC_SET_BL_MIRACAST_PLUS_BT,
+			   &miracast_plus_bt);
+
+	if ((bt_link_info->bt_link_exist) && (wifi_connected)) {
+		halbtc8192e1ant_limited_tx(btcoexist, NORMAL_EXEC, 1, 1, 0, 1);
+
+		if (bt_link_info->sco_exist)
+			halbtc8192e1ant_limited_rx(btcoexist, NORMAL_EXEC,
+						   false, true, 0x5);
+		else
+			halbtc8192e1ant_limited_rx(btcoexist, NORMAL_EXEC,
+						   false, true, 0x8);
+
+		halbtc8192e1ant_sw_mechanism(btcoexist, true);
+		halbtc8192e1ant_run_sw_coexist_mechanism(
+			btcoexist);  /* just print debug message */
+	} else {
+		halbtc8192e1ant_limited_tx(btcoexist, NORMAL_EXEC, 0, 0, 0, 0);
+
+		halbtc8192e1ant_limited_rx(btcoexist, NORMAL_EXEC, false, false,
+					   0x5);
+
+		halbtc8192e1ant_sw_mechanism(btcoexist, false);
+		halbtc8192e1ant_run_sw_coexist_mechanism(
+			btcoexist); /* just print debug message */
+	}
+
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on);
+	if (coex_sta->c2h_bt_inquiry_page) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "############# [BTCoex],  BT Is Inquirying\n");
+		BTC_TRACE(trace_buf);
+		halbtc8192e1ant_action_bt_inquiry(btcoexist);
+		return;
+	} else if (bt_hs_on) {
+		halbtc8192e1ant_action_hs(btcoexist);
+		return;
+	}
+
+
+	if (!wifi_connected) {
+		boolean	scan = false, link = false, roam = false;
+
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], wifi is non connected-idle !!!\n");
+		BTC_TRACE(trace_buf);
+
+		btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_SCAN, &scan);
+		btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_LINK, &link);
+		btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_ROAM, &roam);
+
+		if (scan || link || roam) {
+			if (scan)
+				halbtc8192e1ant_action_wifi_not_connected_scan(
+					btcoexist);
+			else
+				halbtc8192e1ant_action_wifi_not_connected_asso_auth(
+					btcoexist);
+		} else
+			halbtc8192e1ant_action_wifi_not_connected(btcoexist);
+	} else	/* wifi LPS/Busy */
+		halbtc8192e1ant_action_wifi_connected(btcoexist);
+}
+
+void halbtc8192e1ant_init_coex_dm(IN struct btc_coexist *btcoexist)
+{
+	/* force to reset coex mechanism */
+
+	/* sw all off */
+	halbtc8192e1ant_sw_mechanism(btcoexist, false);
+
+	/* halbtc8192e1ant_ps_tdma(btcoexist, FORCE_EXEC, false, 8); */
+	halbtc8192e1ant_coex_table_with_type(btcoexist, FORCE_EXEC, 0);
+
+	coex_sta->pop_event_cnt = 0;
+}
+
+void halbtc8192e1ant_init_hw_config(IN struct btc_coexist *btcoexist,
+				    IN boolean wifi_only)
+{
+	u16	u16tmp = 0;
+	u8	u8tmp = 0;
+
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+		    "[BTCoex], 1Ant Init HW Config!!\n");
+	BTC_TRACE(trace_buf);
+
+	/* antenna sw ctrl to bt */
+	halbtc8192e1ant_set_ant_path(btcoexist, BTC_ANT_PATH_BT, true, false);
+
+	halbtc8192e1ant_coex_table_with_type(btcoexist, FORCE_EXEC, 0);
+
+	/* antenna switch control parameter */
+	btcoexist->btc_write_4byte(btcoexist, 0x858, 0x55555555);
+
+	/* coex parameters */
+	btcoexist->btc_write_1byte(btcoexist, 0x778, 0x1);
+	/* 0x790[5:0]=0x5 */
+	u8tmp = btcoexist->btc_read_1byte(btcoexist, 0x790);
+	u8tmp &= 0xc0;
+	u8tmp |= 0x5;
+	btcoexist->btc_write_1byte(btcoexist, 0x790, u8tmp);
+
+	/* enable counter statistics */
+	btcoexist->btc_write_1byte(btcoexist, 0x76e, 0x4);
+
+	/* enable PTA */
+	btcoexist->btc_write_1byte(btcoexist, 0x40, 0x20);
+	/* enable mailbox interface */
+	u16tmp = btcoexist->btc_read_2byte(btcoexist, 0x40);
+	u16tmp |= BIT(9);
+	btcoexist->btc_write_2byte(btcoexist, 0x40, u16tmp);
+
+	/* enable PTA I2C mailbox */
+	u8tmp = btcoexist->btc_read_1byte(btcoexist, 0x101);
+	u8tmp |= BIT(4);
+	btcoexist->btc_write_1byte(btcoexist, 0x101, u8tmp);
+
+	/* enable bt clock when wifi is disabled. */
+	u8tmp = btcoexist->btc_read_1byte(btcoexist, 0x93);
+	u8tmp |= BIT(0);
+	btcoexist->btc_write_1byte(btcoexist, 0x93, u8tmp);
+	/* enable bt clock when suspend. */
+	u8tmp = btcoexist->btc_read_1byte(btcoexist, 0x7);
+	u8tmp |= BIT(0);
+	btcoexist->btc_write_1byte(btcoexist, 0x7, u8tmp);
+}
+
+
+/*
+void halbtc8192e1ant_wifi_off_hw_cfg(IN struct btc_coexist* btcoexist)
+{
+
+
+}
+*/
+
+/* ************************************************************
+ * work around function start with wa_halbtc8192e1ant_
+ * ************************************************************
+ * ************************************************************
+ * extern function start with ex_halbtc8192e1ant_
+ * ************************************************************ */
+void ex_halbtc8192e1ant_power_on_setting(IN struct btc_coexist *btcoexist)
+{
+#if 0
+	struct  btc_board_info	*board_info = &btcoexist->board_info;
+	u8 u8tmp = 0x0;
+	u16 u16tmp = 0x0;
+
+	btcoexist->stop_coex_dm = true;
+
+	btcoexist->btc_write_1byte(btcoexist, 0x67, 0x20);
+
+	/* enable BB, REG_SYS_FUNC_EN such that we can write 0x948 correctly. */
+	u16tmp = btcoexist->btc_read_2byte(btcoexist, 0x2);
+	btcoexist->btc_write_2byte(btcoexist, 0x2, u16tmp | BIT(0) | BIT(1));
+
+	/* set GRAN_BT = 1 */
+	btcoexist->btc_write_1byte(btcoexist, 0x765, 0x18);
+	/* set WLAN_ACT = 0 */
+	btcoexist->btc_write_1byte(btcoexist, 0x76e, 0x4);
+
+	/*  */
+	/* S0 or S1 setting and Local register setting(By the setting fw can get ant number, S0/S1, ... info) */
+	/* Local setting bit define */
+	/*	BIT0: "0" for no antenna inverse; "1" for antenna inverse  */
+	/*	BIT1: "0" for internal switch; "1" for external switch */
+	/*	BIT2: "0" for one antenna; "1" for two antenna */
+	/* NOTE: here default all internal switch and 1-antenna ==> BIT1=0 and BIT2=0 */
+	if (btcoexist->chip_interface == BTC_INTF_USB) {
+		/* fixed at S0 for USB interface */
+		btcoexist->btc_write_4byte(btcoexist, 0x948, 0x0);
+
+		u8tmp |= 0x1;	/* antenna inverse */
+		btcoexist->btc_write_local_reg_1byte(btcoexist, 0xfe08, u8tmp);
+
+		board_info->btdm_ant_pos = BTC_ANTENNA_AT_AUX_PORT;
+	} else {
+		/* for PCIE and SDIO interface, we check efuse 0xc3[6] */
+		if (board_info->single_ant_path == 0) {
+			/* set to S1 */
+			btcoexist->btc_write_4byte(btcoexist, 0x948, 0x280);
+			board_info->btdm_ant_pos = BTC_ANTENNA_AT_MAIN_PORT;
+		} else if (board_info->single_ant_path == 1) {
+			/* set to S0 */
+			btcoexist->btc_write_4byte(btcoexist, 0x948, 0x0);
+			u8tmp |= 0x1;	/* antenna inverse */
+			board_info->btdm_ant_pos = BTC_ANTENNA_AT_AUX_PORT;
+		}
+
+		if (btcoexist->chip_interface == BTC_INTF_PCI)
+			btcoexist->btc_write_local_reg_1byte(btcoexist, 0x384,
+							     u8tmp);
+		else if (btcoexist->chip_interface == BTC_INTF_SDIO)
+			btcoexist->btc_write_local_reg_1byte(btcoexist, 0x60,
+							     u8tmp);
+	}
+#endif
+}
+
+void ex_halbtc8192e1ant_pre_load_firmware(IN struct btc_coexist *btcoexist)
+{
+}
+
+void ex_halbtc8192e1ant_init_hw_config(IN struct btc_coexist *btcoexist,
+				       IN boolean wifi_only)
+{
+	halbtc8192e1ant_init_hw_config(btcoexist, wifi_only);
+	btcoexist->stop_coex_dm = false;
+}
+
+void ex_halbtc8192e1ant_init_coex_dm(IN struct btc_coexist *btcoexist)
+{
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+		    "[BTCoex], Coex Mechanism Init!!\n");
+	BTC_TRACE(trace_buf);
+
+	btcoexist->stop_coex_dm = false;
+
+	halbtc8192e1ant_init_coex_dm(btcoexist);
+
+	halbtc8192e1ant_query_bt_info(btcoexist);
+}
+
+void ex_halbtc8192e1ant_display_coex_info(IN struct btc_coexist *btcoexist)
+{
+	struct  btc_board_info		*board_info = &btcoexist->board_info;
+	struct  btc_bt_link_info	*bt_link_info = &btcoexist->bt_link_info;
+	u8				*cli_buf = btcoexist->cli_buf;
+	u8				u8tmp[4], i, bt_info_ext, ps_tdma_case = 0;
+	u32				u32tmp[4];
+	u32				fw_ver = 0, bt_patch_ver = 0;
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+		   "\r\n ============[BT Coexist info]============");
+	CL_PRINTF(cli_buf);
+
+	if (btcoexist->manual_control) {
+		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+			"\r\n ============[Under Manual Control]============");
+		CL_PRINTF(cli_buf);
+		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+			   "\r\n ==========================================");
+		CL_PRINTF(cli_buf);
+	}
+	if (btcoexist->stop_coex_dm) {
+		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+			   "\r\n ============[Coex is STOPPED]============");
+		CL_PRINTF(cli_buf);
+		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+			   "\r\n ==========================================");
+		CL_PRINTF(cli_buf);
+	}
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d ",
+		   "Ant PG number/ Ant mechanism:",
+		   board_info->pg_ant_num, board_info->btdm_ant_num);
+	CL_PRINTF(cli_buf);
+
+	btcoexist->btc_get(btcoexist, BTC_GET_U4_BT_PATCH_VER, &bt_patch_ver);
+	btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_FW_VER, &fw_ver);
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+		   "\r\n %-35s = %d_%d/ 0x%x/ 0x%x(%d)",
+		   "CoexVer/ FwVer/ PatchVer",
+		   glcoex_ver_date_8192e_1ant, glcoex_ver_8192e_1ant, fw_ver,
+		   bt_patch_ver, bt_patch_ver);
+	CL_PRINTF(cli_buf);
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %02x %02x %02x ",
+		   "Wifi channel informed to BT",
+		   coex_dm->wifi_chnl_info[0], coex_dm->wifi_chnl_info[1],
+		   coex_dm->wifi_chnl_info[2]);
+	CL_PRINTF(cli_buf);
+
+	/* wifi status */
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s",
+		   "============[Wifi Status]============");
+	CL_PRINTF(cli_buf);
+	btcoexist->btc_disp_dbg_msg(btcoexist, BTC_DBG_DISP_WIFI_STATUS);
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s",
+		   "============[BT Status]============");
+	CL_PRINTF(cli_buf);
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = [%s/ %d/ %d] ",
+		   "BT [status/ rssi/ retryCnt]",
+		   ((coex_sta->bt_disabled) ? ("disabled") :	((
+		   coex_sta->c2h_bt_inquiry_page) ? ("inquiry/page scan")
+			   : ((BT_8192E_1ANT_BT_STATUS_NON_CONNECTED_IDLE ==
+			       coex_dm->bt_status) ? "non-connected idle" :
+		((BT_8192E_1ANT_BT_STATUS_CONNECTED_IDLE == coex_dm->bt_status)
+				       ? "connected-idle" : "busy")))),
+		   coex_sta->bt_rssi, coex_sta->bt_retry_cnt);
+	CL_PRINTF(cli_buf);
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d / %d / %d / %d",
+		   "SCO/HID/PAN/A2DP",
+		   bt_link_info->sco_exist, bt_link_info->hid_exist,
+		   bt_link_info->pan_exist, bt_link_info->a2dp_exist);
+	CL_PRINTF(cli_buf);
+	btcoexist->btc_disp_dbg_msg(btcoexist, BTC_DBG_DISP_BT_LINK_INFO);
+
+	bt_info_ext = coex_sta->bt_info_ext;
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s",
+		   "BT Info A2DP rate",
+		   (bt_info_ext & BIT(0)) ? "Basic rate" : "EDR rate");
+	CL_PRINTF(cli_buf);
+
+	for (i = 0; i < BT_INFO_SRC_8192E_1ANT_MAX; i++) {
+		if (coex_sta->bt_info_c2h_cnt[i]) {
+			CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+				"\r\n %-35s = %02x %02x %02x %02x %02x %02x %02x(%d)",
+				   glbt_info_src_8192e_1ant[i],
+				   coex_sta->bt_info_c2h[i][0],
+				   coex_sta->bt_info_c2h[i][1],
+				   coex_sta->bt_info_c2h[i][2],
+				   coex_sta->bt_info_c2h[i][3],
+				   coex_sta->bt_info_c2h[i][4],
+				   coex_sta->bt_info_c2h[i][5],
+				   coex_sta->bt_info_c2h[i][6],
+				   coex_sta->bt_info_c2h_cnt[i]);
+			CL_PRINTF(cli_buf);
+		}
+	}
+
+	if (!btcoexist->manual_control) {
+		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s",
+			   "============[mechanisms]============");
+		CL_PRINTF(cli_buf);
+
+		ps_tdma_case = coex_dm->cur_ps_tdma;
+		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+			"\r\n %-35s = %02x %02x %02x %02x %02x case-%d (auto:%d)",
+			   "PS TDMA",
+			   coex_dm->ps_tdma_para[0], coex_dm->ps_tdma_para[1],
+			   coex_dm->ps_tdma_para[2], coex_dm->ps_tdma_para[3],
+			   coex_dm->ps_tdma_para[4], ps_tdma_case,
+			   coex_dm->auto_tdma_adjust);
+		CL_PRINTF(cli_buf);
+
+		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x ",
+			   "Latest error condition(should be 0)",
+			   coex_dm->error_condition);
+		CL_PRINTF(cli_buf);
+
+		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d ",
+			   "IgnWlanAct",
+			   coex_dm->cur_ignore_wlan_act);
+		CL_PRINTF(cli_buf);
+	}
+
+	/* Hw setting		 */
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s",
+		   "============[Hw setting]============");
+	CL_PRINTF(cli_buf);
+
+	u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0xc04);
+	u32tmp[1] = btcoexist->btc_read_4byte(btcoexist, 0xd04);
+	u32tmp[2] = btcoexist->btc_read_4byte(btcoexist, 0x90c);
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x/ 0x%x",
+		   "0xc04/ 0xd04/ 0x90c",
+		   u32tmp[0], u32tmp[1], u32tmp[2]);
+	CL_PRINTF(cli_buf);
+
+	u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x778);
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x", "0x778",
+		   u8tmp[0]);
+	CL_PRINTF(cli_buf);
+
+	u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x92c);
+	u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x930);
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x",
+		   "0x92c/ 0x930",
+		   (u8tmp[0]), u32tmp[0]);
+	CL_PRINTF(cli_buf);
+
+	u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x40);
+	u8tmp[1] = btcoexist->btc_read_1byte(btcoexist, 0x4f);
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x",
+		   "0x40/ 0x4f",
+		   u8tmp[0], u8tmp[1]);
+	CL_PRINTF(cli_buf);
+
+	u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x550);
+	u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x522);
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x",
+		   "0x550(bcn ctrl)/0x522",
+		   u32tmp[0], u8tmp[0]);
+	CL_PRINTF(cli_buf);
+
+	u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0xc50);
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x", "0xc50(dig)",
+		   u32tmp[0]);
+	CL_PRINTF(cli_buf);
+
+	u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x6c0);
+	u32tmp[1] = btcoexist->btc_read_4byte(btcoexist, 0x6c4);
+	u32tmp[2] = btcoexist->btc_read_4byte(btcoexist, 0x6c8);
+	u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x6cc);
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+		   "\r\n %-35s = 0x%x/ 0x%x/ 0x%x/ 0x%x",
+		   "0x6c0/0x6c4/0x6c8/0x6cc(coexTable)",
+		   u32tmp[0], u32tmp[1], u32tmp[2], u8tmp[0]);
+	CL_PRINTF(cli_buf);
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d",
+		   "0x770(hp rx[31:16]/tx[15:0])",
+		   coex_sta->high_priority_rx, coex_sta->high_priority_tx);
+	CL_PRINTF(cli_buf);
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d",
+		   "0x774(lp rx[31:16]/tx[15:0])",
+		   coex_sta->low_priority_rx, coex_sta->low_priority_tx);
+	CL_PRINTF(cli_buf);
+#if (BT_AUTO_REPORT_ONLY_8192E_1ANT == 1)
+	halbtc8192e1ant_monitor_bt_ctr(btcoexist);
+#endif
+
+	btcoexist->btc_disp_dbg_msg(btcoexist, BTC_DBG_DISP_COEX_STATISTICS);
+}
+
+void ex_halbtc8192e1ant_ips_notify(IN struct btc_coexist *btcoexist, IN u8 type)
+{
+	if (btcoexist->manual_control ||	btcoexist->stop_coex_dm)
+		return;
+
+	if (BTC_IPS_ENTER == type) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], IPS ENTER notify\n");
+		BTC_TRACE(trace_buf);
+		coex_sta->under_ips = true;
+
+		halbtc8192e1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 0);
+		halbtc8192e1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0);
+		halbtc8192e1ant_set_ant_path(btcoexist, BTC_ANT_PATH_BT, false,
+					     true);
+	} else if (BTC_IPS_LEAVE == type) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], IPS LEAVE notify\n");
+		BTC_TRACE(trace_buf);
+		coex_sta->under_ips = false;
+
+		halbtc8192e1ant_init_hw_config(btcoexist, false);
+		halbtc8192e1ant_init_coex_dm(btcoexist);
+		halbtc8192e1ant_query_bt_info(btcoexist);
+	}
+}
+
+void ex_halbtc8192e1ant_lps_notify(IN struct btc_coexist *btcoexist, IN u8 type)
+{
+	if (btcoexist->manual_control || btcoexist->stop_coex_dm)
+		return;
+
+	if (BTC_LPS_ENABLE == type) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], LPS ENABLE notify\n");
+		BTC_TRACE(trace_buf);
+		coex_sta->under_lps = true;
+	} else if (BTC_LPS_DISABLE == type) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], LPS DISABLE notify\n");
+		BTC_TRACE(trace_buf);
+		coex_sta->under_lps = false;
+	}
+}
+
+void ex_halbtc8192e1ant_scan_notify(IN struct btc_coexist *btcoexist,
+				    IN u8 type)
+{
+	boolean wifi_connected = false, bt_hs_on = false;
+	u32	wifi_link_status = 0;
+	u32	num_of_wifi_link = 0;
+	boolean	bt_ctrl_agg_buf_size = false;
+	u8	agg_buf_size = 5;
+
+	u8 u8tmpa, u8tmpb;
+	u32 u32tmp;
+
+	if (btcoexist->manual_control ||
+	    btcoexist->stop_coex_dm)
+		return;
+
+	if (BTC_SCAN_START == type) {
+		coex_sta->wifi_is_high_pri_task = true;
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], SCAN START notify\n");
+		BTC_TRACE(trace_buf);
+
+		halbtc8192e1ant_ps_tdma(btcoexist, FORCE_EXEC, false,
+			8);  /* Force antenna setup for no scan result issue */
+		u32tmp = btcoexist->btc_read_4byte(btcoexist, 0x948);
+		u8tmpa = btcoexist->btc_read_1byte(btcoexist, 0x765);
+		u8tmpb = btcoexist->btc_read_1byte(btcoexist, 0x67);
+
+
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], 0x948=0x%x, 0x765=0x%x, 0x67=0x%x\n",
+			    u32tmp,  u8tmpa, u8tmpb);
+		BTC_TRACE(trace_buf);
+	} else {
+		coex_sta->wifi_is_high_pri_task = false;
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], SCAN FINISH notify\n");
+		BTC_TRACE(trace_buf);
+
+		btcoexist->btc_get(btcoexist, BTC_GET_U1_AP_NUM,
+				   &coex_sta->scan_ap_num);
+	}
+
+	if (coex_sta->bt_disabled)
+		return;
+
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on);
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED,
+			   &wifi_connected);
+
+	halbtc8192e1ant_query_bt_info(btcoexist);
+
+	btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_LINK_STATUS,
+			   &wifi_link_status);
+	num_of_wifi_link = wifi_link_status >> 16;
+	if (num_of_wifi_link >= 2) {
+		halbtc8192e1ant_limited_tx(btcoexist, NORMAL_EXEC, 0, 0, 0, 0);
+		halbtc8192e1ant_limited_rx(btcoexist, NORMAL_EXEC, false,
+					   bt_ctrl_agg_buf_size, agg_buf_size);
+		halbtc8192e1ant_action_wifi_multi_port(btcoexist);
+		return;
+	}
+
+	if (coex_sta->c2h_bt_inquiry_page) {
+		halbtc8192e1ant_action_bt_inquiry(btcoexist);
+		return;
+	} else if (bt_hs_on) {
+		halbtc8192e1ant_action_hs(btcoexist);
+		return;
+	}
+
+	if (BTC_SCAN_START == type) {
+		if (!wifi_connected)	/* non-connected scan */
+			halbtc8192e1ant_action_wifi_not_connected_scan(
+				btcoexist);
+		else	/* wifi is connected */
+			halbtc8192e1ant_action_wifi_connected_scan(btcoexist);
+	} else if (BTC_SCAN_FINISH == type) {
+		if (!wifi_connected)	/* non-connected scan */
+			halbtc8192e1ant_action_wifi_not_connected(btcoexist);
+		else
+			halbtc8192e1ant_action_wifi_connected(btcoexist);
+	}
+}
+
+void ex_halbtc8192e1ant_connect_notify(IN struct btc_coexist *btcoexist,
+				       IN u8 type)
+{
+	boolean	wifi_connected = false, bt_hs_on = false;
+	u32	wifi_link_status = 0;
+	u32	num_of_wifi_link = 0;
+	boolean	bt_ctrl_agg_buf_size = false;
+	u8	agg_buf_size = 5;
+
+	if (btcoexist->manual_control ||
+	    btcoexist->stop_coex_dm ||
+	    coex_sta->bt_disabled)
+		return;
+
+	if (BTC_ASSOCIATE_START == type) {
+		coex_sta->wifi_is_high_pri_task = true;
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], CONNECT START notify\n");
+		BTC_TRACE(trace_buf);
+		coex_dm->arp_cnt = 0;
+	} else {
+		coex_sta->wifi_is_high_pri_task = false;
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], CONNECT FINISH notify\n");
+		BTC_TRACE(trace_buf);
+		/* coex_dm->arp_cnt = 0; */
+	}
+
+	btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_LINK_STATUS,
+			   &wifi_link_status);
+	num_of_wifi_link = wifi_link_status >> 16;
+	if (num_of_wifi_link >= 2) {
+		halbtc8192e1ant_limited_tx(btcoexist, NORMAL_EXEC, 0, 0, 0, 0);
+		halbtc8192e1ant_limited_rx(btcoexist, NORMAL_EXEC, false,
+					   bt_ctrl_agg_buf_size, agg_buf_size);
+		halbtc8192e1ant_action_wifi_multi_port(btcoexist);
+		return;
+	}
+
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on);
+	if (coex_sta->c2h_bt_inquiry_page) {
+		halbtc8192e1ant_action_bt_inquiry(btcoexist);
+		return;
+	} else if (bt_hs_on) {
+		halbtc8192e1ant_action_hs(btcoexist);
+		return;
+	}
+
+	if (BTC_ASSOCIATE_START == type)
+		halbtc8192e1ant_action_wifi_not_connected_asso_auth(btcoexist);
+	else if (BTC_ASSOCIATE_FINISH == type) {
+		btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED,
+				   &wifi_connected);
+		if (!wifi_connected) /* non-connected scan */
+			halbtc8192e1ant_action_wifi_not_connected(btcoexist);
+		else
+			halbtc8192e1ant_action_wifi_connected(btcoexist);
+	}
+}
+
+void ex_halbtc8192e1ant_media_status_notify(IN struct btc_coexist *btcoexist,
+		IN u8 type)
+{
+	u8			h2c_parameter[3] = {0};
+	u32			wifi_bw;
+	u8			wifi_central_chnl;
+	boolean			wifi_under_b_mode = false;
+
+	if (btcoexist->manual_control ||
+	    btcoexist->stop_coex_dm ||
+	    coex_sta->bt_disabled)
+		return;
+
+	if (BTC_MEDIA_CONNECT == type) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], MEDIA connect notify\n");
+		BTC_TRACE(trace_buf);
+
+		btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_B_MODE,
+				   &wifi_under_b_mode);
+
+		/* Set CCK Tx/Rx high Pri except 11b mode */
+		if (wifi_under_b_mode) {
+			btcoexist->btc_write_1byte(btcoexist, 0x6cd,
+						   0x00); /* CCK Tx */
+			btcoexist->btc_write_1byte(btcoexist, 0x6cf,
+						   0x00); /* CCK Rx */
+		} else {
+			btcoexist->btc_write_1byte(btcoexist, 0x6cd,
+						   0x10); /* CCK Tx */
+			btcoexist->btc_write_1byte(btcoexist, 0x6cf,
+						   0x10); /* CCK Rx */
+		}
+
+		coex_dm->backup_arfr_cnt1 = btcoexist->btc_read_4byte(btcoexist,
+					    0x430);
+		coex_dm->backup_arfr_cnt2 = btcoexist->btc_read_4byte(btcoexist,
+					    0x434);
+		coex_dm->backup_retry_limit = btcoexist->btc_read_2byte(
+						      btcoexist, 0x42a);
+		coex_dm->backup_ampdu_max_time = btcoexist->btc_read_1byte(
+				btcoexist, 0x456);
+	} else {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], MEDIA disconnect notify\n");
+		BTC_TRACE(trace_buf);
+		coex_dm->arp_cnt = 0;
+
+		btcoexist->btc_write_1byte(btcoexist, 0x6cd, 0x0); /* CCK Tx */
+		btcoexist->btc_write_1byte(btcoexist, 0x6cf, 0x0); /* CCK Rx */
+	}
+
+	/* only 2.4G we need to inform bt the chnl mask */
+	btcoexist->btc_get(btcoexist, BTC_GET_U1_WIFI_CENTRAL_CHNL,
+			   &wifi_central_chnl);
+	if ((BTC_MEDIA_CONNECT == type) &&
+	    (wifi_central_chnl <= 14)) {
+		/* h2c_parameter[0] = 0x1; */
+		h2c_parameter[0] = 0x0;
+		h2c_parameter[1] = wifi_central_chnl;
+		btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw);
+		if (BTC_WIFI_BW_HT40 == wifi_bw)
+			h2c_parameter[2] = 0x30;
+		else
+			h2c_parameter[2] = 0x20;
+	}
+
+	coex_dm->wifi_chnl_info[0] = h2c_parameter[0];
+	coex_dm->wifi_chnl_info[1] = h2c_parameter[1];
+	coex_dm->wifi_chnl_info[2] = h2c_parameter[2];
+
+	btcoexist->btc_fill_h2c(btcoexist, 0x66, 3, h2c_parameter);
+}
+
+void ex_halbtc8192e1ant_specific_packet_notify(IN struct btc_coexist *btcoexist,
+		IN u8 type)
+{
+	boolean	bt_hs_on = false;
+	u32	wifi_link_status = 0;
+	u32	num_of_wifi_link = 0;
+	boolean	bt_ctrl_agg_buf_size = false;
+	u8	agg_buf_size = 5;
+
+	if (btcoexist->manual_control ||
+	    btcoexist->stop_coex_dm ||
+	    coex_sta->bt_disabled)
+		return;
+
+	if (BTC_PACKET_DHCP == type ||
+	    BTC_PACKET_EAPOL == type ||
+	    BTC_PACKET_ARP == type) {
+		if (BTC_PACKET_ARP == type) {
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				    "[BTCoex], specific Packet ARP notify\n");
+			BTC_TRACE(trace_buf);
+
+			coex_dm->arp_cnt++;
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				    "[BTCoex], ARP Packet Count = %d\n",
+				    coex_dm->arp_cnt);
+			BTC_TRACE(trace_buf);
+
+			if (coex_dm->arp_cnt >=
+			    10) /* if APR PKT > 10 after connect, do not go to ActionWifiConnectedSpecificPacket(btcoexist) */
+				coex_sta->wifi_is_high_pri_task = false;
+			else
+				coex_sta->wifi_is_high_pri_task = true;
+		} else {
+			coex_sta->wifi_is_high_pri_task = true;
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				"[BTCoex], specific Packet DHCP or EAPOL notify\n");
+			BTC_TRACE(trace_buf);
+		}
+	} else {
+		coex_sta->wifi_is_high_pri_task = false;
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			"[BTCoex], specific Packet [Type = %d] notify\n", type);
+		BTC_TRACE(trace_buf);
+	}
+
+	coex_sta->specific_pkt_period_cnt = 0;
+
+	btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_LINK_STATUS,
+			   &wifi_link_status);
+	num_of_wifi_link = wifi_link_status >> 16;
+	if (num_of_wifi_link >= 2) {
+		halbtc8192e1ant_limited_tx(btcoexist, NORMAL_EXEC, 0, 0, 0, 0);
+		halbtc8192e1ant_limited_rx(btcoexist, NORMAL_EXEC, false,
+					   bt_ctrl_agg_buf_size, agg_buf_size);
+		halbtc8192e1ant_action_wifi_multi_port(btcoexist);
+		return;
+	}
+
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on);
+	if (coex_sta->c2h_bt_inquiry_page) {
+		halbtc8192e1ant_action_bt_inquiry(btcoexist);
+		return;
+	} else if (bt_hs_on) {
+		halbtc8192e1ant_action_hs(btcoexist);
+		return;
+	}
+
+	if (BTC_PACKET_DHCP == type ||
+	    BTC_PACKET_EAPOL == type ||
+	    ((BTC_PACKET_ARP == type) && (coex_sta->wifi_is_high_pri_task)))
+		halbtc8192e1ant_action_wifi_connected_specific_packet(btcoexist);
+}
+
+void ex_halbtc8192e1ant_bt_info_notify(IN struct btc_coexist *btcoexist,
+				       IN u8 *tmp_buf, IN u8 length)
+{
+	u8				bt_info = 0;
+	u8				i, rsp_source = 0;
+	boolean				wifi_connected = false;
+	boolean				bt_busy = false;
+
+	coex_sta->c2h_bt_info_req_sent = false;
+
+	rsp_source = tmp_buf[0] & 0xf;
+	if (rsp_source >= BT_INFO_SRC_8192E_1ANT_MAX)
+		rsp_source = BT_INFO_SRC_8192E_1ANT_WIFI_FW;
+	coex_sta->bt_info_c2h_cnt[rsp_source]++;
+
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+		    "[BTCoex], Bt info[%d], length=%d, hex data=[", rsp_source,
+		    length);
+	BTC_TRACE(trace_buf);
+	for (i = 0; i < length; i++) {
+		coex_sta->bt_info_c2h[rsp_source][i] = tmp_buf[i];
+		if (i == 1)
+			bt_info = tmp_buf[i];
+		if (i == length - 1) {
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "0x%02x]\n",
+				    tmp_buf[i]);
+			BTC_TRACE(trace_buf);
+		} else {
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "0x%02x, ",
+				    tmp_buf[i]);
+			BTC_TRACE(trace_buf);
+		}
+	}
+
+	if (BT_INFO_SRC_8192E_1ANT_WIFI_FW != rsp_source) {
+		coex_sta->bt_retry_cnt =	/* [3:0] */
+			coex_sta->bt_info_c2h[rsp_source][2] & 0xf;
+
+		if (coex_sta->bt_retry_cnt >= 1)
+			coex_sta->pop_event_cnt++;
+
+		if (coex_sta->bt_info_c2h[rsp_source][2] & 0x20)
+			coex_sta->c2h_bt_page = true;
+		else
+			coex_sta->c2h_bt_page = false;
+
+		coex_sta->bt_rssi =
+			coex_sta->bt_info_c2h[rsp_source][3] * 2 - 90;
+		/* coex_sta->bt_info_c2h[rsp_source][3]*2+10; */
+
+		coex_sta->bt_info_ext =
+			coex_sta->bt_info_c2h[rsp_source][4];
+
+		coex_sta->bt_tx_rx_mask = (coex_sta->bt_info_c2h[rsp_source][2]
+					   & 0x40);
+		btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_TX_RX_MASK,
+				   &coex_sta->bt_tx_rx_mask);
+		if (!coex_sta->bt_tx_rx_mask) {
+			/* BT into is responded by BT FW and BT RF REG 0x3C != 0x15 => Need to switch BT TRx Mask */
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				"[BTCoex], Switch BT TRx Mask since BT RF REG 0x3C != 0x15\n");
+			BTC_TRACE(trace_buf);
+			btcoexist->btc_set_bt_reg(btcoexist, BTC_BT_REG_RF,
+						  0x3c, 0x15);
+		}
+
+		/* Here we need to resend some wifi info to BT */
+		/* because bt is reset and loss of the info. */
+		if (coex_sta->bt_info_ext & BIT(1)) {
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				"[BTCoex], BT ext info bit1 check, send wifi BW&Chnl to BT!!\n");
+			BTC_TRACE(trace_buf);
+			btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED,
+					   &wifi_connected);
+			if (wifi_connected)
+				ex_halbtc8192e1ant_media_status_notify(
+					btcoexist, BTC_MEDIA_CONNECT);
+			else
+				ex_halbtc8192e1ant_media_status_notify(
+					btcoexist, BTC_MEDIA_DISCONNECT);
+		}
+
+		if (coex_sta->bt_info_ext & BIT(3)) {
+			if (!btcoexist->manual_control &&
+			    !btcoexist->stop_coex_dm) {
+				BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+					"[BTCoex], BT ext info bit3 check, set BT NOT to ignore Wlan active!!\n");
+				BTC_TRACE(trace_buf);
+				halbtc8192e1ant_ignore_wlan_act(btcoexist,
+							FORCE_EXEC, false);
+			}
+		} else {
+			/* BT already NOT ignore Wlan active, do nothing here. */
+		}
+#if (BT_AUTO_REPORT_ONLY_8192E_1ANT == 0)
+		if ((coex_sta->bt_info_ext & BIT(4))) {
+			/* BT auto report already enabled, do nothing */
+		} else
+			halbtc8192e1ant_bt_auto_report(btcoexist, FORCE_EXEC,
+						       true);
+#endif
+	}
+
+	/* check BIT2 first ==> check if bt is under inquiry or page scan */
+	if (bt_info & BT_INFO_8192E_1ANT_B_INQ_PAGE)
+		coex_sta->c2h_bt_inquiry_page = true;
+	else
+		coex_sta->c2h_bt_inquiry_page = false;
+
+	/* set link exist status */
+	if (!(bt_info & BT_INFO_8192E_1ANT_B_CONNECTION)) {
+		coex_sta->bt_link_exist = false;
+		coex_sta->pan_exist = false;
+		coex_sta->a2dp_exist = false;
+		coex_sta->hid_exist = false;
+		coex_sta->sco_exist = false;
+	} else {	/* connection exists */
+		coex_sta->bt_link_exist = true;
+		if (bt_info & BT_INFO_8192E_1ANT_B_FTP)
+			coex_sta->pan_exist = true;
+		else
+			coex_sta->pan_exist = false;
+		if (bt_info & BT_INFO_8192E_1ANT_B_A2DP)
+			coex_sta->a2dp_exist = true;
+		else
+			coex_sta->a2dp_exist = false;
+		if (bt_info & BT_INFO_8192E_1ANT_B_HID)
+			coex_sta->hid_exist = true;
+		else
+			coex_sta->hid_exist = false;
+		if (bt_info & BT_INFO_8192E_1ANT_B_SCO_ESCO)
+			coex_sta->sco_exist = true;
+		else
+			coex_sta->sco_exist = false;
+	}
+
+	halbtc8192e1ant_update_bt_link_info(btcoexist);
+
+	bt_info = bt_info &
+		0x1f;  /* mask profile bit for connect-ilde identification ( for CSR case: A2DP idle --> 0x41) */
+
+	if (!(bt_info & BT_INFO_8192E_1ANT_B_CONNECTION)) {
+		coex_dm->bt_status = BT_8192E_1ANT_BT_STATUS_NON_CONNECTED_IDLE;
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			"[BTCoex], BtInfoNotify(), BT Non-Connected idle!!!\n");
+		BTC_TRACE(trace_buf);
+	} else if (bt_info ==
+		BT_INFO_8192E_1ANT_B_CONNECTION) {	/* connection exists but no busy */
+		coex_dm->bt_status = BT_8192E_1ANT_BT_STATUS_CONNECTED_IDLE;
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], BtInfoNotify(), BT Connected-idle!!!\n");
+		BTC_TRACE(trace_buf);
+	} else if ((bt_info & BT_INFO_8192E_1ANT_B_SCO_ESCO) ||
+		   (bt_info & BT_INFO_8192E_1ANT_B_SCO_BUSY)) {
+		coex_dm->bt_status = BT_8192E_1ANT_BT_STATUS_SCO_BUSY;
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], BtInfoNotify(), BT SCO busy!!!\n");
+		BTC_TRACE(trace_buf);
+	} else if (bt_info & BT_INFO_8192E_1ANT_B_ACL_BUSY) {
+		if (BT_8192E_1ANT_BT_STATUS_ACL_BUSY != coex_dm->bt_status)
+			coex_dm->auto_tdma_adjust = false;
+		coex_dm->bt_status = BT_8192E_1ANT_BT_STATUS_ACL_BUSY;
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], BtInfoNotify(), BT ACL busy!!!\n");
+		BTC_TRACE(trace_buf);
+	} else {
+		coex_dm->bt_status = BT_8192E_1ANT_BT_STATUS_MAX;
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			"[BTCoex], BtInfoNotify(), BT Non-Defined state!!!\n");
+		BTC_TRACE(trace_buf);
+	}
+
+	if ((BT_8192E_1ANT_BT_STATUS_ACL_BUSY == coex_dm->bt_status) ||
+	    (BT_8192E_1ANT_BT_STATUS_SCO_BUSY == coex_dm->bt_status) ||
+	    (BT_8192E_1ANT_BT_STATUS_ACL_SCO_BUSY == coex_dm->bt_status))
+		bt_busy = true;
+	else
+		bt_busy = false;
+	btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_TRAFFIC_BUSY, &bt_busy);
+
+	halbtc8192e1ant_run_coexist_mechanism(btcoexist);
+}
+
+void ex_halbtc8192e1ant_rf_status_notify(IN struct btc_coexist *btcoexist,
+		IN u8 type)
+{
+	u32	u32tmp;
+	u8	u8tmpa, u8tmpb, u8tmpc;
+
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], RF Status notify\n");
+	BTC_TRACE(trace_buf);
+
+	if (BTC_RF_ON == type) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], RF is turned ON!!\n");
+		BTC_TRACE(trace_buf);
+		btcoexist->stop_coex_dm = false;
+	} else if (BTC_RF_OFF == type) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], RF is turned OFF!!\n");
+		BTC_TRACE(trace_buf);
+
+		halbtc8192e1ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE,
+						 0x0, 0x0);
+		halbtc8192e1ant_ps_tdma(btcoexist, FORCE_EXEC, false, 0);
+		halbtc8192e1ant_set_ant_path(btcoexist, BTC_ANT_PATH_BT, false,
+					     true);
+
+		halbtc8192e1ant_ignore_wlan_act(btcoexist, FORCE_EXEC, true);
+		btcoexist->stop_coex_dm = true;
+
+		u32tmp = btcoexist->btc_read_4byte(btcoexist, 0x948);
+		u8tmpa = btcoexist->btc_read_1byte(btcoexist, 0x765);
+		u8tmpb = btcoexist->btc_read_1byte(btcoexist, 0x67);
+		u8tmpc = btcoexist->btc_read_1byte(btcoexist, 0x76e);
+
+
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			"############# [BTCoex], 0x948=0x%x, 0x765=0x%x, 0x67=0x%x, 0x76e=0x%x\n",
+			    u32tmp,  u8tmpa, u8tmpb, u8tmpc);
+		BTC_TRACE(trace_buf);
+
+	}
+}
+
+void ex_halbtc8192e1ant_halt_notify(IN struct btc_coexist *btcoexist)
+{
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], Halt notify\n");
+	BTC_TRACE(trace_buf);
+
+	halbtc8192e1ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, 0x0,
+					 0x0);
+	halbtc8192e1ant_ps_tdma(btcoexist, FORCE_EXEC, false, 0);
+	halbtc8192e1ant_set_ant_path(btcoexist, BTC_ANT_PATH_BT, false, true);
+
+	halbtc8192e1ant_ignore_wlan_act(btcoexist, FORCE_EXEC, true);
+
+	ex_halbtc8192e1ant_media_status_notify(btcoexist, BTC_MEDIA_DISCONNECT);
+
+	btcoexist->stop_coex_dm = true;
+}
+
+void ex_halbtc8192e1ant_pnp_notify(IN struct btc_coexist *btcoexist,
+				   IN u8 pnp_state)
+{
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], Pnp notify\n");
+	BTC_TRACE(trace_buf);
+
+	if (BTC_WIFI_PNP_SLEEP == pnp_state) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], Pnp notify to SLEEP\n");
+		BTC_TRACE(trace_buf);
+
+		halbtc8192e1ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE,
+						 0x0, 0x0);
+		halbtc8192e1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 0);
+		halbtc8192e1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 2);
+		halbtc8192e1ant_set_ant_path(btcoexist, BTC_ANT_PATH_BT, false,
+					     true);
+
+		/* Sinda 20150819, workaround for driver skip leave IPS/LPS to speed up sleep time. */
+		/* Driver do not leave IPS/LPS when driver is going to sleep, so BTCoexistence think wifi is still under IPS/LPS */
+		/* BT should clear UnderIPS/UnderLPS state to avoid mismatch state after wakeup. */
+		coex_sta->under_ips = false;
+		coex_sta->under_lps = false;
+		btcoexist->stop_coex_dm = true;
+	} else if (BTC_WIFI_PNP_WAKE_UP == pnp_state) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], Pnp notify to WAKE UP\n");
+		BTC_TRACE(trace_buf);
+		btcoexist->stop_coex_dm = false;
+		halbtc8192e1ant_init_hw_config(btcoexist, false);
+		halbtc8192e1ant_init_coex_dm(btcoexist);
+		halbtc8192e1ant_query_bt_info(btcoexist);
+	}
+}
+
+void ex_halbtc8192e1ant_coex_dm_reset(IN struct btc_coexist *btcoexist)
+{
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+		"[BTCoex], *****************Coex DM Reset*****************\n");
+	BTC_TRACE(trace_buf);
+
+	halbtc8192e1ant_init_hw_config(btcoexist, false);
+	/* btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1, 0xfffff, 0x0); */
+	/* btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x2, 0xfffff, 0x0); */
+	halbtc8192e1ant_init_coex_dm(btcoexist);
+}
+
+void ex_halbtc8192e1ant_periodical(IN struct btc_coexist *btcoexist)
+{
+#if (BT_AUTO_REPORT_ONLY_8192E_1ANT == 0)
+	halbtc8192e1ant_query_bt_info(btcoexist);
+	halbtc8192e1ant_monitor_bt_enable_disable(btcoexist);
+#else
+	halbtc8192e1ant_monitor_bt_ctr(btcoexist);
+	halbtc8192e1ant_monitor_wifi_ctr(btcoexist);
+
+	if (halbtc8192e1ant_is_wifi_status_changed(btcoexist) ||
+	    coex_dm->auto_tdma_adjust)
+
+		halbtc8192e1ant_run_coexist_mechanism(btcoexist);
+
+	coex_sta->specific_pkt_period_cnt++;
+#endif
+}
+
+
+void ex_halbtc8192e1ant_dbg_control(IN struct btc_coexist *btcoexist,
+				    IN u8 op_code, IN u8 op_len, IN u8 *pdata)
+{
+	switch (op_code) {
+	case BTC_DBG_SET_COEX_NORMAL:
+		btcoexist->manual_control = false;
+		halbtc8192e1ant_init_coex_dm(btcoexist);
+		break;
+	case BTC_DBG_SET_COEX_WIFI_ONLY:
+		btcoexist->manual_control = true;
+		halbtc8192e1ant_power_save_state(btcoexist,
+						 BTC_PS_WIFI_NATIVE, 0x0, 0x0);
+		halbtc8192e1ant_ps_tdma(btcoexist, NORMAL_EXEC, false,
+					9);
+		break;
+	case BTC_DBG_SET_COEX_BT_ONLY:
+		/* todo */
+		break;
+	default:
+		break;
+	}
+}
+
+#endif	/*  #if (RTL8192E_SUPPORT == 1) */
+
+#endif	/* #if (BT_SUPPORT == 1 && COEX_SUPPORT == 1) */
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/btc/halbtc8192e1ant.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/btc/halbtc8192e1ant.h
--- linux-5.6.3/3rdparty/rtl8821ce/hal/btc/halbtc8192e1ant.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/btc/halbtc8192e1ant.h	2020-04-10 16:35:06.780658387 +0300
@@ -0,0 +1,226 @@
+
+#if (BT_SUPPORT == 1 && COEX_SUPPORT == 1)
+
+#if (RTL8192E_SUPPORT == 1)
+
+/* *******************************************
+ * The following is for 8192E 1ANT BT Co-exist definition
+ * ******************************************* */
+#define	BT_AUTO_REPORT_ONLY_8192E_1ANT				1
+
+#define	BT_INFO_8192E_1ANT_B_FTP						BIT(7)
+#define	BT_INFO_8192E_1ANT_B_A2DP					BIT(6)
+#define	BT_INFO_8192E_1ANT_B_HID						BIT(5)
+#define	BT_INFO_8192E_1ANT_B_SCO_BUSY				BIT(4)
+#define	BT_INFO_8192E_1ANT_B_ACL_BUSY				BIT(3)
+#define	BT_INFO_8192E_1ANT_B_INQ_PAGE				BIT(2)
+#define	BT_INFO_8192E_1ANT_B_SCO_ESCO				BIT(1)
+#define	BT_INFO_8192E_1ANT_B_CONNECTION				BIT(0)
+
+#define	BT_INFO_8192E_1ANT_A2DP_BASIC_RATE(_BT_INFO_EXT_)	\
+		(((_BT_INFO_EXT_&BIT(0))) ? true : false)
+
+#define	BTC_RSSI_COEX_THRESH_TOL_8192E_1ANT		2
+
+#define  BT_8192E_1ANT_WIFI_NOISY_THRESH								30   /* max: 255 */
+
+enum bt_info_src_8192e_1ant {
+	BT_INFO_SRC_8192E_1ANT_WIFI_FW			= 0x0,
+	BT_INFO_SRC_8192E_1ANT_BT_RSP				= 0x1,
+	BT_INFO_SRC_8192E_1ANT_BT_ACTIVE_SEND		= 0x2,
+	BT_INFO_SRC_8192E_1ANT_MAX
+};
+
+enum bt_8192e_1ant_bt_status {
+	BT_8192E_1ANT_BT_STATUS_NON_CONNECTED_IDLE	= 0x0,
+	BT_8192E_1ANT_BT_STATUS_CONNECTED_IDLE		= 0x1,
+	BT_8192E_1ANT_BT_STATUS_INQ_PAGE				= 0x2,
+	BT_8192E_1ANT_BT_STATUS_ACL_BUSY				= 0x3,
+	BT_8192E_1ANT_BT_STATUS_SCO_BUSY				= 0x4,
+	BT_8192E_1ANT_BT_STATUS_ACL_SCO_BUSY			= 0x5,
+	BT_8192E_1ANT_BT_STATUS_MAX
+};
+
+enum bt_8192e_1ant_wifi_status {
+	BT_8192E_1ANT_WIFI_STATUS_NON_CONNECTED_IDLE				= 0x0,
+	BT_8192E_1ANT_WIFI_STATUS_NON_CONNECTED_ASSO_AUTH_SCAN		= 0x1,
+	BT_8192E_1ANT_WIFI_STATUS_CONNECTED_SCAN					= 0x2,
+	BT_8192E_1ANT_WIFI_STATUS_CONNECTED_SPECIFIC_PKT				= 0x3,
+	BT_8192E_1ANT_WIFI_STATUS_CONNECTED_IDLE					= 0x4,
+	BT_8192E_1ANT_WIFI_STATUS_CONNECTED_BUSY					= 0x5,
+	BT_8192E_1ANT_WIFI_STATUS_MAX
+};
+
+enum bt_8192e_1ant_coex_algo {
+	BT_8192E_1ANT_COEX_ALGO_UNDEFINED			= 0x0,
+	BT_8192E_1ANT_COEX_ALGO_SCO				= 0x1,
+	BT_8192E_1ANT_COEX_ALGO_HID				= 0x2,
+	BT_8192E_1ANT_COEX_ALGO_A2DP				= 0x3,
+	BT_8192E_1ANT_COEX_ALGO_A2DP_PANHS		= 0x4,
+	BT_8192E_1ANT_COEX_ALGO_PANEDR			= 0x5,
+	BT_8192E_1ANT_COEX_ALGO_PANHS			= 0x6,
+	BT_8192E_1ANT_COEX_ALGO_PANEDR_A2DP		= 0x7,
+	BT_8192E_1ANT_COEX_ALGO_PANEDR_HID		= 0x8,
+	BT_8192E_1ANT_COEX_ALGO_HID_A2DP_PANEDR	= 0x9,
+	BT_8192E_1ANT_COEX_ALGO_HID_A2DP			= 0xa,
+	BT_8192E_1ANT_COEX_ALGO_MAX				= 0xb,
+};
+
+struct coex_dm_8192e_1ant {
+	/* fw mechanism */
+	boolean		cur_ignore_wlan_act;
+	boolean		pre_ignore_wlan_act;
+	u8		pre_ps_tdma;
+	u8		cur_ps_tdma;
+	u8		ps_tdma_para[5];
+	u8		ps_tdma_du_adj_type;
+	boolean		auto_tdma_adjust;
+	boolean		pre_ps_tdma_on;
+	boolean		cur_ps_tdma_on;
+	boolean		pre_bt_auto_report;
+	boolean		cur_bt_auto_report;
+	u8		pre_lps;
+	u8		cur_lps;
+	u8		pre_rpwm;
+	u8		cur_rpwm;
+
+	/* sw mechanism */
+	boolean	pre_low_penalty_ra;
+	boolean		cur_low_penalty_ra;
+	u32		pre_val0x6c0;
+	u32		cur_val0x6c0;
+	u32		pre_val0x6c4;
+	u32		cur_val0x6c4;
+	u32		pre_val0x6c8;
+	u32		cur_val0x6c8;
+	u8		pre_val0x6cc;
+	u8		cur_val0x6cc;
+	boolean		limited_dig;
+
+	u32		backup_arfr_cnt1;	/* Auto Rate Fallback Retry cnt */
+	u32		backup_arfr_cnt2;	/* Auto Rate Fallback Retry cnt */
+	u16		backup_retry_limit;
+	u8		backup_ampdu_max_time;
+
+	/* algorithm related */
+	u8		pre_algorithm;
+	u8		cur_algorithm;
+	u8		bt_status;
+	u8		wifi_chnl_info[3];
+
+	u32		pre_ra_mask;
+	u32		cur_ra_mask;
+	u8		pre_arfr_type;
+	u8		cur_arfr_type;
+	u8		pre_retry_limit_type;
+	u8		cur_retry_limit_type;
+	u8		pre_ampdu_time_type;
+	u8		cur_ampdu_time_type;
+	u32		arp_cnt;
+
+	u8		error_condition;
+};
+
+struct coex_sta_8192e_1ant {
+	boolean					bt_disabled;
+	boolean					bt_link_exist;
+	boolean					sco_exist;
+	boolean					a2dp_exist;
+	boolean					hid_exist;
+	boolean					pan_exist;
+
+	boolean					under_lps;
+	boolean					under_ips;
+	u32					specific_pkt_period_cnt;
+	u32					high_priority_tx;
+	u32					high_priority_rx;
+	u32					low_priority_tx;
+	u32					low_priority_rx;
+	s8					bt_rssi;
+	boolean					bt_tx_rx_mask;
+	u8					pre_bt_rssi_state;
+	u8					pre_wifi_rssi_state[4];
+	boolean					c2h_bt_info_req_sent;
+	u8					bt_info_c2h[BT_INFO_SRC_8192E_1ANT_MAX][10];
+	u32					bt_info_c2h_cnt[BT_INFO_SRC_8192E_1ANT_MAX];
+	boolean					c2h_bt_inquiry_page;
+	boolean					c2h_bt_page;				/* Add for win8.1 page out issue */
+	boolean					wifi_is_high_pri_task;		/* Add for win8.1 page out issue */
+	u8					bt_retry_cnt;
+	u8					bt_info_ext;
+	u32					pop_event_cnt;
+	u8					scan_ap_num;
+
+	u32					crc_ok_cck;
+	u32					crc_ok_11g;
+	u32					crc_ok_11n;
+	u32					crc_ok_11n_agg;
+
+	u32					crc_err_cck;
+	u32					crc_err_11g;
+	u32					crc_err_11n;
+	u32					crc_err_11n_agg;
+
+	boolean					cck_lock;
+	boolean					pre_ccklock;
+	u8					coex_table_type;
+
+	boolean					force_lps_on;
+};
+
+/* *******************************************
+ * The following is interface which will notify coex module.
+ * ******************************************* */
+void ex_halbtc8192e1ant_power_on_setting(IN struct btc_coexist *btcoexist);
+void ex_halbtc8192e1ant_pre_load_firmware(IN struct btc_coexist *btcoexist);
+void ex_halbtc8192e1ant_init_hw_config(IN struct btc_coexist *btcoexist,
+				       IN boolean wifi_only);
+void ex_halbtc8192e1ant_init_coex_dm(IN struct btc_coexist *btcoexist);
+void ex_halbtc8192e1ant_ips_notify(IN struct btc_coexist *btcoexist,
+				   IN u8 type);
+void ex_halbtc8192e1ant_lps_notify(IN struct btc_coexist *btcoexist,
+				   IN u8 type);
+void ex_halbtc8192e1ant_scan_notify(IN struct btc_coexist *btcoexist,
+				    IN u8 type);
+void ex_halbtc8192e1ant_connect_notify(IN struct btc_coexist *btcoexist,
+				       IN u8 type);
+void ex_halbtc8192e1ant_media_status_notify(IN struct btc_coexist *btcoexist,
+		IN u8 type);
+void ex_halbtc8192e1ant_specific_packet_notify(IN struct btc_coexist *btcoexist,
+		IN u8 type);
+void ex_halbtc8192e1ant_bt_info_notify(IN struct btc_coexist *btcoexist,
+				       IN u8 *tmp_buf, IN u8 length);
+void ex_halbtc8192e1ant_rf_status_notify(IN struct btc_coexist *btcoexist,
+		IN u8 type);
+void ex_halbtc8192e1ant_halt_notify(IN struct btc_coexist *btcoexist);
+void ex_halbtc8192e1ant_pnp_notify(IN struct btc_coexist *btcoexist,
+				   IN u8 pnp_state);
+void ex_halbtc8192e1ant_coex_dm_reset(IN struct btc_coexist *btcoexist);
+void ex_halbtc8192e1ant_periodical(IN struct btc_coexist *btcoexist);
+void ex_halbtc8192e1ant_display_coex_info(IN struct btc_coexist *btcoexist);
+void ex_halbtc8192e1ant_dbg_control(IN struct btc_coexist *btcoexist,
+				    IN u8 op_code, IN u8 op_len, IN u8 *pdata);
+
+#else	/*  #if (RTL8192E_SUPPORT == 1) */
+#define	ex_halbtc8192e1ant_power_on_setting(btcoexist)
+#define	ex_halbtc8192e1ant_pre_load_firmware(btcoexist)
+#define	ex_halbtc8192e1ant_init_hw_config(btcoexist, wifi_only)
+#define	ex_halbtc8192e1ant_init_coex_dm(btcoexist)
+#define	ex_halbtc8192e1ant_ips_notify(btcoexist, type)
+#define	ex_halbtc8192e1ant_lps_notify(btcoexist, type)
+#define	ex_halbtc8192e1ant_scan_notify(btcoexist, type)
+#define	ex_halbtc8192e1ant_connect_notify(btcoexist, type)
+#define	ex_halbtc8192e1ant_media_status_notify(btcoexist, type)
+#define	ex_halbtc8192e1ant_specific_packet_notify(btcoexist, type)
+#define	ex_halbtc8192e1ant_bt_info_notify(btcoexist, tmp_buf, length)
+#define	ex_halbtc8192e1ant_rf_status_notify(btcoexist, type)
+#define	ex_halbtc8192e1ant_halt_notify(btcoexist)
+#define	ex_halbtc8192e1ant_pnp_notify(btcoexist, pnp_state)
+#define	ex_halbtc8192e1ant_coex_dm_reset(btcoexist)
+#define	ex_halbtc8192e1ant_periodical(btcoexist)
+#define	ex_halbtc8192e1ant_display_coex_info(btcoexist)
+#define	ex_halbtc8192e1ant_dbg_control(btcoexist, op_code, op_len, pdata)
+
+#endif
+
+#endif
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/btc/halbtc8192e2ant.c linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/btc/halbtc8192e2ant.c
--- linux-5.6.3/3rdparty/rtl8821ce/hal/btc/halbtc8192e2ant.c	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/btc/halbtc8192e2ant.c	2020-04-10 16:35:06.781658433 +0300
@@ -0,0 +1,4252 @@
+/* ************************************************************
+ * Description:
+ *
+ * This file is for RTL8192E Co-exist mechanism
+ *
+ * History
+ * 2012/11/15 Cosa first check in.
+ *
+ * ************************************************************ */
+
+/* ************************************************************
+ * include files
+ * ************************************************************ */
+#include "mp_precomp.h"
+
+
+#if (BT_SUPPORT == 1 && COEX_SUPPORT == 1)
+
+#if (RTL8192E_SUPPORT == 1)
+/* ************************************************************
+ * Global variables, these are static variables
+ * ************************************************************ */
+static u8	 *trace_buf = &gl_btc_trace_buf[0];
+static struct  coex_dm_8192e_2ant		glcoex_dm_8192e_2ant;
+static struct  coex_dm_8192e_2ant	*coex_dm = &glcoex_dm_8192e_2ant;
+static struct  coex_sta_8192e_2ant		glcoex_sta_8192e_2ant;
+static struct  coex_sta_8192e_2ant	*coex_sta = &glcoex_sta_8192e_2ant;
+
+const char *const glbt_info_src_8192e_2ant[] = {
+	"BT Info[wifi fw]",
+	"BT Info[bt rsp]",
+	"BT Info[bt auto report]",
+};
+/* ************************************************************
+ * BtCoex Version Format:
+ * 1. date :			glcoex_ver_date_XXXXX_1ant
+ * 2. WifiCoexVersion : glcoex_ver_XXXX_1ant
+ * 3. BtCoexVersion :	glcoex_ver_btdesired_XXXXX_1ant
+ * 4. others :			glcoex_ver_XXXXXX_XXXXX_1ant
+ *
+ * Variable should be indicated IC and Antenna numbers !!!
+ * Please strictly follow this order and naming style !!!
+ *
+ * ************************************************************ */
+u32	glcoex_ver_date_8192e_2ant = 20161024;
+u32	glcoex_ver_8192e_2ant = 0x45;
+u32	glcoex_ver_btdesired_8192e_2ant = 0x03;
+/*1.BT FW update BLE channel map with high priority*/
+/* ************************************************************
+ * local function proto type if needed
+ * ************************************************************
+ * ************************************************************
+ * local function start with halbtc8192e2ant_
+ * ************************************************************ */
+u8 halbtc8192e2ant_bt_rssi_state(u8 level_num, u8 rssi_thresh, u8 rssi_thresh1)
+{
+	s32			bt_rssi = 0;
+	u8			bt_rssi_state = coex_sta->pre_bt_rssi_state;
+
+	bt_rssi = coex_sta->bt_rssi;
+
+	if (level_num == 2) {
+		if ((coex_sta->pre_bt_rssi_state == BTC_RSSI_STATE_LOW) ||
+		    (coex_sta->pre_bt_rssi_state ==
+		     BTC_RSSI_STATE_STAY_LOW)) {
+			if (bt_rssi >= (rssi_thresh +
+					BTC_RSSI_COEX_THRESH_TOL_8192E_2ANT))
+				bt_rssi_state = BTC_RSSI_STATE_HIGH;
+			else
+				bt_rssi_state = BTC_RSSI_STATE_STAY_LOW;
+		} else {
+			if (bt_rssi < rssi_thresh)
+				bt_rssi_state = BTC_RSSI_STATE_LOW;
+			else
+				bt_rssi_state = BTC_RSSI_STATE_STAY_HIGH;
+		}
+	} else if (level_num == 3) {
+		if (rssi_thresh > rssi_thresh1) {
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				    "[BTCoex], BT Rssi thresh error!!\n");
+			BTC_TRACE(trace_buf);
+			return coex_sta->pre_bt_rssi_state;
+		}
+
+		if ((coex_sta->pre_bt_rssi_state == BTC_RSSI_STATE_LOW) ||
+		    (coex_sta->pre_bt_rssi_state ==
+		     BTC_RSSI_STATE_STAY_LOW)) {
+			if (bt_rssi >= (rssi_thresh +
+					BTC_RSSI_COEX_THRESH_TOL_8192E_2ANT))
+				bt_rssi_state = BTC_RSSI_STATE_MEDIUM;
+			else
+				bt_rssi_state = BTC_RSSI_STATE_STAY_LOW;
+		} else if ((coex_sta->pre_bt_rssi_state ==
+			    BTC_RSSI_STATE_MEDIUM) ||
+			   (coex_sta->pre_bt_rssi_state ==
+			    BTC_RSSI_STATE_STAY_MEDIUM)) {
+			if (bt_rssi >= (rssi_thresh1 +
+					BTC_RSSI_COEX_THRESH_TOL_8192E_2ANT))
+				bt_rssi_state = BTC_RSSI_STATE_HIGH;
+			else if (bt_rssi < rssi_thresh)
+				bt_rssi_state = BTC_RSSI_STATE_LOW;
+			else
+				bt_rssi_state = BTC_RSSI_STATE_STAY_MEDIUM;
+		} else {
+			if (bt_rssi < rssi_thresh1)
+				bt_rssi_state = BTC_RSSI_STATE_MEDIUM;
+			else
+				bt_rssi_state = BTC_RSSI_STATE_STAY_HIGH;
+		}
+	}
+
+	coex_sta->pre_bt_rssi_state = bt_rssi_state;
+
+	return bt_rssi_state;
+}
+
+u8 halbtc8192e2ant_wifi_rssi_state(IN struct btc_coexist *btcoexist,
+	   IN u8 index, IN u8 level_num, IN u8 rssi_thresh, IN u8 rssi_thresh1)
+{
+	s32			wifi_rssi = 0;
+	u8			wifi_rssi_state = coex_sta->pre_wifi_rssi_state[index];
+
+	btcoexist->btc_get(btcoexist, BTC_GET_S4_WIFI_RSSI, &wifi_rssi);
+
+	if (level_num == 2) {
+		if ((coex_sta->pre_wifi_rssi_state[index] == BTC_RSSI_STATE_LOW)
+		    ||
+		    (coex_sta->pre_wifi_rssi_state[index] ==
+		     BTC_RSSI_STATE_STAY_LOW)) {
+			if (wifi_rssi >= (rssi_thresh +
+					  BTC_RSSI_COEX_THRESH_TOL_8192E_2ANT))
+				wifi_rssi_state = BTC_RSSI_STATE_HIGH;
+			else
+				wifi_rssi_state = BTC_RSSI_STATE_STAY_LOW;
+		} else {
+			if (wifi_rssi < rssi_thresh)
+				wifi_rssi_state = BTC_RSSI_STATE_LOW;
+			else
+				wifi_rssi_state = BTC_RSSI_STATE_STAY_HIGH;
+		}
+	} else if (level_num == 3) {
+		if (rssi_thresh > rssi_thresh1) {
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				    "[BTCoex], wifi RSSI thresh error!!\n");
+			BTC_TRACE(trace_buf);
+			return coex_sta->pre_wifi_rssi_state[index];
+		}
+
+		if ((coex_sta->pre_wifi_rssi_state[index] == BTC_RSSI_STATE_LOW)
+		    ||
+		    (coex_sta->pre_wifi_rssi_state[index] ==
+		     BTC_RSSI_STATE_STAY_LOW)) {
+			if (wifi_rssi >= (rssi_thresh +
+					  BTC_RSSI_COEX_THRESH_TOL_8192E_2ANT))
+				wifi_rssi_state = BTC_RSSI_STATE_MEDIUM;
+			else
+				wifi_rssi_state = BTC_RSSI_STATE_STAY_LOW;
+		} else if ((coex_sta->pre_wifi_rssi_state[index] ==
+			    BTC_RSSI_STATE_MEDIUM) ||
+			   (coex_sta->pre_wifi_rssi_state[index] ==
+			    BTC_RSSI_STATE_STAY_MEDIUM)) {
+			if (wifi_rssi >= (rssi_thresh1 +
+					  BTC_RSSI_COEX_THRESH_TOL_8192E_2ANT))
+				wifi_rssi_state = BTC_RSSI_STATE_HIGH;
+			else if (wifi_rssi < rssi_thresh)
+				wifi_rssi_state = BTC_RSSI_STATE_LOW;
+			else
+				wifi_rssi_state = BTC_RSSI_STATE_STAY_MEDIUM;
+		} else {
+			if (wifi_rssi < rssi_thresh1)
+				wifi_rssi_state = BTC_RSSI_STATE_MEDIUM;
+			else
+				wifi_rssi_state = BTC_RSSI_STATE_STAY_HIGH;
+		}
+	}
+
+	coex_sta->pre_wifi_rssi_state[index] = wifi_rssi_state;
+
+	return wifi_rssi_state;
+}
+
+void halbtc8192e2ant_monitor_bt_enable_disable(IN struct btc_coexist *btcoexist)
+{
+	static u32	bt_disable_cnt = 0;
+	boolean			bt_active = true, bt_disabled = false;
+
+	/* This function check if bt is disabled */
+
+	if (coex_sta->high_priority_tx == 0 &&
+	    coex_sta->high_priority_rx == 0 &&
+	    coex_sta->low_priority_tx == 0 &&
+	    coex_sta->low_priority_rx == 0)
+		bt_active = false;
+	if (coex_sta->high_priority_tx == 0xffff &&
+	    coex_sta->high_priority_rx == 0xffff &&
+	    coex_sta->low_priority_tx == 0xffff &&
+	    coex_sta->low_priority_rx == 0xffff)
+		bt_active = false;
+	if (bt_active) {
+		bt_disable_cnt = 0;
+		bt_disabled = false;
+		btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_DISABLE,
+				   &bt_disabled);
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], BT is enabled !!\n");
+		BTC_TRACE(trace_buf);
+	} else {
+		bt_disable_cnt++;
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], bt all counters=0, %d times!!\n",
+			    bt_disable_cnt);
+		BTC_TRACE(trace_buf);
+		if (bt_disable_cnt >= 2) {
+			bt_disabled = true;
+			btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_DISABLE,
+					   &bt_disabled);
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				    "[BTCoex], BT is disabled !!\n");
+			BTC_TRACE(trace_buf);
+		}
+	}
+	if (coex_sta->bt_disabled != bt_disabled) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], BT is from %s to %s!!\n",
+			    (coex_sta->bt_disabled ? "disabled" : "enabled"),
+			    (bt_disabled ? "disabled" : "enabled"));
+		BTC_TRACE(trace_buf);
+		coex_sta->bt_disabled = bt_disabled;
+		/* if (!bt_disabled) {
+		} else {
+		} */
+	}
+}
+
+u32 halbtc8192e2ant_decide_ra_mask(IN struct btc_coexist *btcoexist,
+				   IN u8 ss_type, IN u32 ra_mask_type)
+{
+	u32	dis_ra_mask = 0x0;
+
+	switch (ra_mask_type) {
+	case 0: /* normal mode */
+		if (ss_type == 2)
+			dis_ra_mask = 0x0;			/* enable 2ss */
+		else
+			dis_ra_mask = 0xfff00000;		/* disable 2ss */
+		break;
+	case 1: /* disable cck 1/2 */
+		if (ss_type == 2)
+			dis_ra_mask = 0x00000003;		/* enable 2ss */
+		else
+			dis_ra_mask = 0xfff00003;		/* disable 2ss */
+		break;
+	case 2: /* disable cck 1/2/5.5, ofdm 6/9/12/18/24, mcs 0/1/2/3/4 */
+		if (ss_type == 2)
+			dis_ra_mask = 0x0001f1f7;		/* enable 2ss */
+		else
+			dis_ra_mask = 0xfff1f1f7;		/* disable 2ss */
+		break;
+	default:
+		break;
+	}
+
+	return dis_ra_mask;
+}
+
+void halbtc8192e2ant_update_ra_mask(IN struct btc_coexist *btcoexist,
+				    IN boolean force_exec, IN u32 dis_rate_mask)
+{
+	coex_dm->cur_ra_mask = dis_rate_mask;
+
+	if (force_exec || (coex_dm->pre_ra_mask != coex_dm->cur_ra_mask))
+		btcoexist->btc_set(btcoexist, BTC_SET_ACT_UPDATE_RAMASK,
+				   &coex_dm->cur_ra_mask);
+	coex_dm->pre_ra_mask = coex_dm->cur_ra_mask;
+}
+
+void halbtc8192e2ant_auto_rate_fallback_retry(IN struct btc_coexist *btcoexist,
+		IN boolean force_exec, IN u8 type)
+{
+	boolean	wifi_under_b_mode = false;
+
+	coex_dm->cur_arfr_type = type;
+
+	if (force_exec || (coex_dm->pre_arfr_type != coex_dm->cur_arfr_type)) {
+		switch (coex_dm->cur_arfr_type) {
+		case 0:	/* normal mode */
+			btcoexist->btc_write_4byte(btcoexist, 0x430,
+						   coex_dm->backup_arfr_cnt1);
+			btcoexist->btc_write_4byte(btcoexist, 0x434,
+						   coex_dm->backup_arfr_cnt2);
+			break;
+		case 1:
+			btcoexist->btc_get(btcoexist,
+					   BTC_GET_BL_WIFI_UNDER_B_MODE,
+					   &wifi_under_b_mode);
+			if (wifi_under_b_mode) {
+				btcoexist->btc_write_4byte(btcoexist,
+							   0x430, 0x0);
+				btcoexist->btc_write_4byte(btcoexist,
+							   0x434, 0x01010101);
+			} else {
+				btcoexist->btc_write_4byte(btcoexist,
+							   0x430, 0x0);
+				btcoexist->btc_write_4byte(btcoexist,
+							   0x434, 0x04030201);
+			}
+			break;
+		default:
+			break;
+		}
+	}
+
+	coex_dm->pre_arfr_type = coex_dm->cur_arfr_type;
+}
+
+void halbtc8192e2ant_retry_limit(IN struct btc_coexist *btcoexist,
+				 IN boolean force_exec, IN u8 type)
+{
+	coex_dm->cur_retry_limit_type = type;
+
+	if (force_exec ||
+	    (coex_dm->pre_retry_limit_type !=
+	     coex_dm->cur_retry_limit_type)) {
+		switch (coex_dm->cur_retry_limit_type) {
+		case 0:	/* normal mode */
+			btcoexist->btc_write_2byte(btcoexist, 0x42a,
+						   coex_dm->backup_retry_limit);
+			break;
+		case 1:	/* retry limit=8 */
+			btcoexist->btc_write_2byte(btcoexist, 0x42a,
+						   0x0808);
+			break;
+		default:
+			break;
+		}
+	}
+
+	coex_dm->pre_retry_limit_type = coex_dm->cur_retry_limit_type;
+}
+
+void halbtc8192e2ant_ampdu_max_time(IN struct btc_coexist *btcoexist,
+				    IN boolean force_exec, IN u8 type)
+{
+	coex_dm->cur_ampdu_time_type = type;
+
+	if (force_exec ||
+	    (coex_dm->pre_ampdu_time_type != coex_dm->cur_ampdu_time_type)) {
+		switch (coex_dm->cur_ampdu_time_type) {
+		case 0:	/* normal mode */
+			btcoexist->btc_write_1byte(btcoexist, 0x456,
+					   coex_dm->backup_ampdu_max_time);
+			break;
+		case 1:	/* AMPDU timw = 0x38 * 32us */
+			btcoexist->btc_write_1byte(btcoexist, 0x456,
+						   0x38);
+			break;
+		default:
+			break;
+		}
+	}
+
+	coex_dm->pre_ampdu_time_type = coex_dm->cur_ampdu_time_type;
+}
+
+void halbtc8192e2ant_limited_tx(IN struct btc_coexist *btcoexist,
+		IN boolean force_exec, IN u8 ra_mask_type, IN u8 arfr_type,
+				IN u8 retry_limit_type, IN u8 ampdu_time_type)
+{
+	u32	dis_ra_mask = 0x0;
+
+	coex_dm->cur_ra_mask_type = ra_mask_type;
+	dis_ra_mask = halbtc8192e2ant_decide_ra_mask(btcoexist,
+			coex_dm->cur_ss_type, ra_mask_type);
+	halbtc8192e2ant_update_ra_mask(btcoexist, force_exec, dis_ra_mask);
+
+	halbtc8192e2ant_auto_rate_fallback_retry(btcoexist, force_exec,
+			arfr_type);
+	halbtc8192e2ant_retry_limit(btcoexist, force_exec, retry_limit_type);
+	halbtc8192e2ant_ampdu_max_time(btcoexist, force_exec, ampdu_time_type);
+}
+
+void halbtc8192e2ant_limited_rx(IN struct btc_coexist *btcoexist,
+			IN boolean force_exec, IN boolean rej_ap_agg_pkt,
+			IN boolean bt_ctrl_agg_buf_size, IN u8 agg_buf_size)
+{
+	boolean	reject_rx_agg = rej_ap_agg_pkt;
+	boolean	bt_ctrl_rx_agg_size = bt_ctrl_agg_buf_size;
+	u8	rx_agg_size = agg_buf_size;
+
+	/* ============================================ */
+	/*	Rx Aggregation related setting */
+	/* ============================================ */
+	btcoexist->btc_set(btcoexist, BTC_SET_BL_TO_REJ_AP_AGG_PKT,
+			   &reject_rx_agg);
+	/* decide BT control aggregation buf size or not */
+	btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_CTRL_AGG_SIZE,
+			   &bt_ctrl_rx_agg_size);
+	/* aggregation buf size, only work when BT control Rx aggregation size. */
+	btcoexist->btc_set(btcoexist, BTC_SET_U1_AGG_BUF_SIZE, &rx_agg_size);
+	/* real update aggregation setting */
+	btcoexist->btc_set(btcoexist, BTC_SET_ACT_AGGREGATE_CTRL, NULL);
+
+
+}
+
+void halbtc8192e2ant_monitor_bt_ctr(IN struct btc_coexist *btcoexist)
+{
+	u32			reg_hp_txrx, reg_lp_txrx, u32tmp;
+	u32			reg_hp_tx = 0, reg_hp_rx = 0, reg_lp_tx = 0, reg_lp_rx = 0;
+
+	reg_hp_txrx = 0x770;
+	reg_lp_txrx = 0x774;
+
+	u32tmp = btcoexist->btc_read_4byte(btcoexist, reg_hp_txrx);
+	reg_hp_tx = u32tmp & MASKLWORD;
+	reg_hp_rx = (u32tmp & MASKHWORD) >> 16;
+
+	u32tmp = btcoexist->btc_read_4byte(btcoexist, reg_lp_txrx);
+	reg_lp_tx = u32tmp & MASKLWORD;
+	reg_lp_rx = (u32tmp & MASKHWORD) >> 16;
+
+	coex_sta->high_priority_tx = reg_hp_tx;
+	coex_sta->high_priority_rx = reg_hp_rx;
+	coex_sta->low_priority_tx = reg_lp_tx;
+	coex_sta->low_priority_rx = reg_lp_rx;
+
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+		"[BTCoex], High Priority Tx/Rx (reg 0x%x)=0x%x(%d)/0x%x(%d)\n",
+		    reg_hp_txrx, reg_hp_tx, reg_hp_tx, reg_hp_rx, reg_hp_rx);
+	BTC_TRACE(trace_buf);
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+		"[BTCoex], Low Priority Tx/Rx (reg 0x%x)=0x%x(%d)/0x%x(%d)\n",
+		    reg_lp_txrx, reg_lp_tx, reg_lp_tx, reg_lp_rx, reg_lp_rx);
+	BTC_TRACE(trace_buf);
+
+	/* reset counter */
+	btcoexist->btc_write_1byte(btcoexist, 0x76e, 0xc);
+}
+
+
+void halbtc8192e2ant_monitor_wifi_ctr(IN struct btc_coexist *btcoexist)
+{
+#if 1
+
+	coex_sta->crc_ok_cck =
+		btcoexist->btc_phydm_query_PHY_counter(
+			btcoexist,
+			PHYDM_INFO_CRC32_OK_CCK);
+	coex_sta->crc_ok_11g =
+		btcoexist->btc_phydm_query_PHY_counter(
+			btcoexist,
+			PHYDM_INFO_CRC32_OK_LEGACY);
+	coex_sta->crc_ok_11n =
+		btcoexist->btc_phydm_query_PHY_counter(
+			btcoexist,
+			PHYDM_INFO_CRC32_OK_HT);
+	coex_sta->crc_ok_11n_vht =
+		btcoexist->btc_phydm_query_PHY_counter(
+			btcoexist,
+			PHYDM_INFO_CRC32_OK_VHT);
+
+	coex_sta->crc_err_cck =
+		btcoexist->btc_phydm_query_PHY_counter(
+			btcoexist,
+			PHYDM_INFO_CRC32_ERROR_CCK);
+	coex_sta->crc_err_11g =
+		btcoexist->btc_phydm_query_PHY_counter(
+			btcoexist,
+			PHYDM_INFO_CRC32_ERROR_LEGACY);
+	coex_sta->crc_err_11n =
+		btcoexist->btc_phydm_query_PHY_counter(
+			btcoexist,
+			PHYDM_INFO_CRC32_ERROR_HT);
+	coex_sta->crc_err_11n_vht =
+		btcoexist->btc_phydm_query_PHY_counter(
+			btcoexist,
+			PHYDM_INFO_CRC32_ERROR_VHT);
+#endif
+}
+
+
+
+void halbtc8192e2ant_query_bt_info(IN struct btc_coexist *btcoexist)
+{
+	u8			h2c_parameter[1] = {0};
+
+	coex_sta->c2h_bt_info_req_sent = true;
+
+	h2c_parameter[0] |= BIT(0);	/* trigger */
+
+	btcoexist->btc_fill_h2c(btcoexist, 0x61, 1, h2c_parameter);
+
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+		    "[BTCoex],Query BT info!!!! H2C 0x61 = 0x1\n");
+	BTC_TRACE(trace_buf);
+}
+
+boolean halbtc8192e2ant_is_wifi_status_changed(IN struct btc_coexist *btcoexist)
+{
+	static boolean	pre_wifi_busy = false, pre_under_4way = false,
+			pre_bt_hs_on = false;
+	boolean	wifi_busy = false, under_4way = false, bt_hs_on = false;
+	boolean	wifi_connected = false;
+	u8	wifi_rssi_state = BTC_RSSI_STATE_HIGH;
+
+
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED,
+			   &wifi_connected);
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy);
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on);
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_4_WAY_PROGRESS,
+			   &under_4way);
+
+	if (wifi_connected) {
+		if (wifi_busy != pre_wifi_busy) {
+			pre_wifi_busy = wifi_busy;
+			return true;
+		}
+		if (under_4way != pre_under_4way) {
+			pre_under_4way = under_4way;
+			return true;
+		}
+		if (bt_hs_on != pre_bt_hs_on) {
+			pre_bt_hs_on = bt_hs_on;
+			return true;
+		}
+
+		wifi_rssi_state = halbtc8192e2ant_wifi_rssi_state(btcoexist, 0,
+				  2, 34, 0);
+
+		if ((BTC_RSSI_STATE_HIGH == wifi_rssi_state) ||
+		    (BTC_RSSI_STATE_LOW == wifi_rssi_state))
+			return true;
+	}
+
+	return false;
+}
+
+void halbtc8192e2ant_update_bt_link_info(IN struct btc_coexist *btcoexist)
+{
+	struct  btc_bt_link_info	*bt_link_info = &btcoexist->bt_link_info;
+	boolean				bt_hs_on = false;
+
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on);
+
+	bt_link_info->bt_link_exist = coex_sta->bt_link_exist;
+	bt_link_info->sco_exist = coex_sta->sco_exist;
+	bt_link_info->a2dp_exist = coex_sta->a2dp_exist;
+	bt_link_info->pan_exist = coex_sta->pan_exist;
+	bt_link_info->hid_exist = coex_sta->hid_exist;
+
+	/* work around for HS mode. */
+	if (bt_hs_on) {
+		bt_link_info->pan_exist = true;
+		bt_link_info->bt_link_exist = true;
+	}
+
+	/* check if Sco only */
+	if (bt_link_info->sco_exist &&
+	    !bt_link_info->a2dp_exist &&
+	    !bt_link_info->pan_exist &&
+	    !bt_link_info->hid_exist)
+		bt_link_info->sco_only = true;
+	else
+		bt_link_info->sco_only = false;
+
+	/* check if A2dp only */
+	if (!bt_link_info->sco_exist &&
+	    bt_link_info->a2dp_exist &&
+	    !bt_link_info->pan_exist &&
+	    !bt_link_info->hid_exist)
+		bt_link_info->a2dp_only = true;
+	else
+		bt_link_info->a2dp_only = false;
+
+	/* check if Pan only */
+	if (!bt_link_info->sco_exist &&
+	    !bt_link_info->a2dp_exist &&
+	    bt_link_info->pan_exist &&
+	    !bt_link_info->hid_exist)
+		bt_link_info->pan_only = true;
+	else
+		bt_link_info->pan_only = false;
+
+	/* check if Hid only */
+	if (!bt_link_info->sco_exist &&
+	    !bt_link_info->a2dp_exist &&
+	    !bt_link_info->pan_exist &&
+	    bt_link_info->hid_exist)
+		bt_link_info->hid_only = true;
+	else
+		bt_link_info->hid_only = false;
+}
+
+u8 halbtc8192e2ant_action_algorithm(IN struct btc_coexist *btcoexist)
+{
+	struct  btc_bt_link_info	*bt_link_info = &btcoexist->bt_link_info;
+	struct  btc_stack_info	*stack_info = &btcoexist->stack_info;
+	boolean				bt_hs_on = false;
+	u8				algorithm = BT_8192E_2ANT_COEX_ALGO_UNDEFINED;
+	u8				num_of_diff_profile = 0;
+
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on);
+
+	if (!bt_link_info->bt_link_exist) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], No BT link exists!!!\n");
+		BTC_TRACE(trace_buf);
+		return algorithm;
+	}
+
+	if (bt_link_info->sco_exist)
+		num_of_diff_profile++;
+	if (bt_link_info->hid_exist)
+		num_of_diff_profile++;
+	if (bt_link_info->pan_exist)
+		num_of_diff_profile++;
+	if (bt_link_info->a2dp_exist)
+		num_of_diff_profile++;
+
+	if (num_of_diff_profile == 1) {
+		if (bt_link_info->sco_exist) {
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				    "[BTCoex], SCO only\n");
+			BTC_TRACE(trace_buf);
+			algorithm = BT_8192E_2ANT_COEX_ALGO_SCO;
+		} else {
+			if (bt_link_info->hid_exist) {
+				BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+					    "[BTCoex], HID only\n");
+				BTC_TRACE(trace_buf);
+				algorithm = BT_8192E_2ANT_COEX_ALGO_HID;
+			} else if (bt_link_info->a2dp_exist) {
+				BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+					    "[BTCoex], A2DP only\n");
+				BTC_TRACE(trace_buf);
+				algorithm = BT_8192E_2ANT_COEX_ALGO_A2DP;
+			} else if (bt_link_info->pan_exist) {
+				if (bt_hs_on) {
+					BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+						    "[BTCoex], PAN(HS) only\n");
+					BTC_TRACE(trace_buf);
+					algorithm =
+						BT_8192E_2ANT_COEX_ALGO_PANHS;
+				} else {
+					BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+						"[BTCoex], PAN(EDR) only\n");
+					BTC_TRACE(trace_buf);
+					algorithm =
+						BT_8192E_2ANT_COEX_ALGO_PANEDR;
+				}
+			}
+		}
+	} else if (num_of_diff_profile == 2) {
+		if (bt_link_info->sco_exist) {
+			if (bt_link_info->hid_exist) {
+				BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+					    "[BTCoex], SCO + HID\n");
+				BTC_TRACE(trace_buf);
+				algorithm = BT_8192E_2ANT_COEX_ALGO_SCO;
+			} else if (bt_link_info->a2dp_exist) {
+				BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+					    "[BTCoex], SCO + A2DP ==> SCO\n");
+				BTC_TRACE(trace_buf);
+				algorithm = BT_8192E_2ANT_COEX_ALGO_PANEDR_HID;
+			} else if (bt_link_info->pan_exist) {
+				if (bt_hs_on) {
+					BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+						"[BTCoex], SCO + PAN(HS)\n");
+					BTC_TRACE(trace_buf);
+					algorithm = BT_8192E_2ANT_COEX_ALGO_SCO;
+				} else {
+					BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+						"[BTCoex], SCO + PAN(EDR)\n");
+					BTC_TRACE(trace_buf);
+					algorithm =
+						BT_8192E_2ANT_COEX_ALGO_SCO_PAN;
+				}
+			}
+		} else {
+			if (bt_link_info->hid_exist &&
+			    bt_link_info->a2dp_exist) {
+				if (stack_info->num_of_hid >= 2) {
+					BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+						    "[BTCoex], HID*2 + A2DP\n");
+					BTC_TRACE(trace_buf);
+					algorithm =
+						BT_8192E_2ANT_COEX_ALGO_HID_A2DP_PANEDR;
+				} else {
+					BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+						    "[BTCoex], HID + A2DP\n");
+					BTC_TRACE(trace_buf);
+					algorithm =
+						BT_8192E_2ANT_COEX_ALGO_HID_A2DP;
+				}
+			} else if (bt_link_info->hid_exist &&
+				   bt_link_info->pan_exist) {
+				if (bt_hs_on) {
+					BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+						"[BTCoex], HID + PAN(HS)\n");
+					BTC_TRACE(trace_buf);
+					algorithm = BT_8192E_2ANT_COEX_ALGO_HID;
+				} else {
+					BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+						"[BTCoex], HID + PAN(EDR)\n");
+					BTC_TRACE(trace_buf);
+					algorithm =
+						BT_8192E_2ANT_COEX_ALGO_PANEDR_HID;
+				}
+			} else if (bt_link_info->pan_exist &&
+				   bt_link_info->a2dp_exist) {
+				if (bt_hs_on) {
+					BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+						"[BTCoex], A2DP + PAN(HS)\n");
+					BTC_TRACE(trace_buf);
+					algorithm =
+						BT_8192E_2ANT_COEX_ALGO_A2DP_PANHS;
+				} else {
+					BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+						"[BTCoex], A2DP + PAN(EDR)\n");
+					BTC_TRACE(trace_buf);
+					algorithm =
+						BT_8192E_2ANT_COEX_ALGO_PANEDR_A2DP;
+				}
+			}
+		}
+	} else if (num_of_diff_profile == 3) {
+		if (bt_link_info->sco_exist) {
+			if (bt_link_info->hid_exist &&
+			    bt_link_info->a2dp_exist) {
+				BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+					"[BTCoex], SCO + HID + A2DP ==> HID\n");
+				BTC_TRACE(trace_buf);
+				algorithm = BT_8192E_2ANT_COEX_ALGO_PANEDR_HID;
+			} else if (bt_link_info->hid_exist &&
+				   bt_link_info->pan_exist) {
+				if (bt_hs_on) {
+					BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+						"[BTCoex], SCO + HID + PAN(HS)\n");
+					BTC_TRACE(trace_buf);
+					algorithm = BT_8192E_2ANT_COEX_ALGO_SCO;
+				} else {
+					BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+						"[BTCoex], SCO + HID + PAN(EDR)\n");
+					BTC_TRACE(trace_buf);
+					algorithm =
+						BT_8192E_2ANT_COEX_ALGO_SCO_PAN;
+				}
+			} else if (bt_link_info->pan_exist &&
+				   bt_link_info->a2dp_exist) {
+				if (bt_hs_on) {
+					BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+						"[BTCoex], SCO + A2DP + PAN(HS)\n");
+					BTC_TRACE(trace_buf);
+					algorithm = BT_8192E_2ANT_COEX_ALGO_SCO;
+				} else {
+					BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+						"[BTCoex], SCO + A2DP + PAN(EDR) ==> HID\n");
+					BTC_TRACE(trace_buf);
+					algorithm =
+						BT_8192E_2ANT_COEX_ALGO_PANEDR_HID;
+				}
+			}
+		} else {
+			if (bt_link_info->hid_exist &&
+			    bt_link_info->pan_exist &&
+			    bt_link_info->a2dp_exist) {
+				if (bt_hs_on) {
+					BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+						"[BTCoex], HID + A2DP + PAN(HS)\n");
+					BTC_TRACE(trace_buf);
+					algorithm =
+						BT_8192E_2ANT_COEX_ALGO_HID_A2DP;
+				} else {
+					BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+						"[BTCoex], HID + A2DP + PAN(EDR)\n");
+					BTC_TRACE(trace_buf);
+					algorithm =
+						BT_8192E_2ANT_COEX_ALGO_HID_A2DP_PANEDR;
+				}
+			}
+		}
+	} else if (num_of_diff_profile >= 3) {
+		if (bt_link_info->sco_exist) {
+			if (bt_link_info->hid_exist &&
+			    bt_link_info->pan_exist &&
+			    bt_link_info->a2dp_exist) {
+				if (bt_hs_on) {
+					BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+						"[BTCoex], Error!!! SCO + HID + A2DP + PAN(HS)\n");
+					BTC_TRACE(trace_buf);
+				} else {
+					BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+						"[BTCoex], SCO + HID + A2DP + PAN(EDR)==>PAN(EDR)+HID\n");
+					BTC_TRACE(trace_buf);
+					algorithm =
+						BT_8192E_2ANT_COEX_ALGO_PANEDR_HID;
+				}
+			}
+		}
+	}
+
+	return algorithm;
+}
+
+void halbtc8192e2ant_set_fw_dac_swing_level(IN struct btc_coexist *btcoexist,
+		IN u8 dac_swing_lvl)
+{
+	u8			h2c_parameter[1] = {0};
+
+	/* There are several type of dacswing */
+	/* 0x18/ 0x10/ 0xc/ 0x8/ 0x4/ 0x6 */
+	h2c_parameter[0] = dac_swing_lvl;
+
+	btcoexist->btc_fill_h2c(btcoexist, 0x64, 1, h2c_parameter);
+}
+
+void halbtc8192e2ant_set_fw_dec_bt_pwr(IN struct btc_coexist *btcoexist,
+				       IN u8 dec_bt_pwr_lvl)
+{
+	u8			h2c_parameter[1] = {0};
+
+	h2c_parameter[0] = dec_bt_pwr_lvl;
+
+	btcoexist->btc_fill_h2c(btcoexist, 0x62, 1, h2c_parameter);
+}
+
+void halbtc8192e2ant_dec_bt_pwr(IN struct btc_coexist *btcoexist,
+				IN boolean force_exec, IN u8 dec_bt_pwr_lvl)
+{
+	coex_dm->cur_bt_dec_pwr_lvl = dec_bt_pwr_lvl;
+
+	if (!force_exec) {
+#if 0	/* work around, avoid h2c command fail. */
+		if (coex_dm->pre_bt_dec_pwr_lvl == coex_dm->cur_bt_dec_pwr_lvl)
+			return;
+#endif
+	}
+	halbtc8192e2ant_set_fw_dec_bt_pwr(btcoexist,
+					  coex_dm->cur_bt_dec_pwr_lvl);
+
+	coex_dm->pre_bt_dec_pwr_lvl = coex_dm->cur_bt_dec_pwr_lvl;
+}
+
+void halbtc8192e2ant_set_bt_auto_report(IN struct btc_coexist *btcoexist,
+					IN boolean enable_auto_report)
+{
+	u8			h2c_parameter[1] = {0};
+
+	h2c_parameter[0] = 0;
+
+	if (enable_auto_report)
+		h2c_parameter[0] |= BIT(0);
+
+	btcoexist->btc_fill_h2c(btcoexist, 0x68, 1, h2c_parameter);
+}
+
+void halbtc8192e2ant_bt_auto_report(IN struct btc_coexist *btcoexist,
+		    IN boolean force_exec, IN boolean enable_auto_report)
+{
+	coex_dm->cur_bt_auto_report = enable_auto_report;
+
+	if (!force_exec) {
+		if (coex_dm->pre_bt_auto_report == coex_dm->cur_bt_auto_report)
+			return;
+	}
+	halbtc8192e2ant_set_bt_auto_report(btcoexist,
+					   coex_dm->cur_bt_auto_report);
+
+	coex_dm->pre_bt_auto_report = coex_dm->cur_bt_auto_report;
+}
+
+void halbtc8192e2ant_fw_dac_swing_lvl(IN struct btc_coexist *btcoexist,
+			      IN boolean force_exec, IN u8 fw_dac_swing_lvl)
+{
+	coex_dm->cur_fw_dac_swing_lvl = fw_dac_swing_lvl;
+
+	if (!force_exec) {
+		if (coex_dm->pre_fw_dac_swing_lvl ==
+		    coex_dm->cur_fw_dac_swing_lvl)
+			return;
+	}
+
+	halbtc8192e2ant_set_fw_dac_swing_level(btcoexist,
+					       coex_dm->cur_fw_dac_swing_lvl);
+
+	coex_dm->pre_fw_dac_swing_lvl = coex_dm->cur_fw_dac_swing_lvl;
+}
+
+void halbtc8192e2ant_set_sw_rf_rx_lpf_corner(IN struct btc_coexist *btcoexist,
+		IN boolean rx_rf_shrink_on)
+{
+	if (rx_rf_shrink_on) {
+		/* Shrink RF Rx LPF corner */
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], Shrink RF Rx LPF corner!!\n");
+		BTC_TRACE(trace_buf);
+		btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1e, 0xfffff,
+					  0xffffc);
+	} else {
+		/* Resume RF Rx LPF corner */
+		/* After initialized, we can use coex_dm->bt_rf_0x1e_backup */
+		if (btcoexist->initilized) {
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				    "[BTCoex], Resume RF Rx LPF corner!!\n");
+			BTC_TRACE(trace_buf);
+			btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1e,
+					  0xfffff, coex_dm->bt_rf_0x1e_backup);
+		}
+	}
+}
+
+void halbtc8192e2ant_rf_shrink(IN struct btc_coexist *btcoexist,
+		       IN boolean force_exec, IN boolean rx_rf_shrink_on)
+{
+	coex_dm->cur_rf_rx_lpf_shrink = rx_rf_shrink_on;
+
+	if (!force_exec) {
+		if (coex_dm->pre_rf_rx_lpf_shrink ==
+		    coex_dm->cur_rf_rx_lpf_shrink)
+			return;
+	}
+	halbtc8192e2ant_set_sw_rf_rx_lpf_corner(btcoexist,
+						coex_dm->cur_rf_rx_lpf_shrink);
+
+	coex_dm->pre_rf_rx_lpf_shrink = coex_dm->cur_rf_rx_lpf_shrink;
+}
+
+void halbtc8192e2ant_set_sw_penalty_tx_rate_adaptive(IN struct btc_coexist
+		*btcoexist, IN boolean low_penalty_ra)
+{
+	u8			h2c_parameter[6] = {0};
+
+	h2c_parameter[0] = 0x6;	/* op_code, 0x6= Retry_Penalty */
+
+	if (low_penalty_ra) {
+		h2c_parameter[1] |= BIT(0);
+		h2c_parameter[2] =
+			0x00;  /* normal rate except MCS7/6/5, OFDM54/48/36 */
+		h2c_parameter[3] = 0xf7;  /* MCS7 or OFDM54 */
+		h2c_parameter[4] = 0xf8;  /* MCS6 or OFDM48 */
+		h2c_parameter[5] = 0xf9;	/* MCS5 or OFDM36	 */
+	}
+
+	btcoexist->btc_fill_h2c(btcoexist, 0x69, 6, h2c_parameter);
+}
+
+void halbtc8192e2ant_low_penalty_ra(IN struct btc_coexist *btcoexist,
+			    IN boolean force_exec, IN boolean low_penalty_ra)
+{
+	coex_dm->cur_low_penalty_ra = low_penalty_ra;
+
+	if (!force_exec) {
+		if (coex_dm->pre_low_penalty_ra == coex_dm->cur_low_penalty_ra)
+			return;
+	}
+	halbtc8192e2ant_set_sw_penalty_tx_rate_adaptive(btcoexist,
+			coex_dm->cur_low_penalty_ra);
+
+	coex_dm->pre_low_penalty_ra = coex_dm->cur_low_penalty_ra;
+}
+
+void halbtc8192e2ant_set_dac_swing_reg(IN struct btc_coexist *btcoexist,
+				       IN u32 level)
+{
+	u8	val = (u8)level;
+
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+		    "[BTCoex], Write SwDacSwing = 0x%x\n", level);
+	BTC_TRACE(trace_buf);
+	btcoexist->btc_write_1byte_bitmask(btcoexist, 0x883, 0x3e, val);
+}
+
+void halbtc8192e2ant_set_sw_full_time_dac_swing(IN struct btc_coexist
+		*btcoexist, IN boolean sw_dac_swing_on, IN u32 sw_dac_swing_lvl)
+{
+	if (sw_dac_swing_on)
+		halbtc8192e2ant_set_dac_swing_reg(btcoexist, sw_dac_swing_lvl);
+	else
+		halbtc8192e2ant_set_dac_swing_reg(btcoexist, 0x18);
+}
+
+
+void halbtc8192e2ant_dac_swing(IN struct btc_coexist *btcoexist,
+	IN boolean force_exec, IN boolean dac_swing_on, IN u32 dac_swing_lvl)
+{
+	coex_dm->cur_dac_swing_on = dac_swing_on;
+	coex_dm->cur_dac_swing_lvl = dac_swing_lvl;
+
+	if (!force_exec) {
+		if ((coex_dm->pre_dac_swing_on == coex_dm->cur_dac_swing_on) &&
+		    (coex_dm->pre_dac_swing_lvl ==
+		     coex_dm->cur_dac_swing_lvl))
+			return;
+	}
+	delay_ms(30);
+	halbtc8192e2ant_set_sw_full_time_dac_swing(btcoexist, dac_swing_on,
+			dac_swing_lvl);
+
+	coex_dm->pre_dac_swing_on = coex_dm->cur_dac_swing_on;
+	coex_dm->pre_dac_swing_lvl = coex_dm->cur_dac_swing_lvl;
+}
+
+void halbtc8192e2ant_set_adc_back_off(IN struct btc_coexist *btcoexist,
+				      IN boolean adc_back_off)
+{
+	if (adc_back_off) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], BB BackOff Level On!\n");
+		BTC_TRACE(trace_buf);
+		btcoexist->btc_write_1byte_bitmask(btcoexist, 0xc05, 0x30, 0x3);
+	} else {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], BB BackOff Level Off!\n");
+		BTC_TRACE(trace_buf);
+		btcoexist->btc_write_1byte_bitmask(btcoexist, 0xc05, 0x30, 0x1);
+	}
+}
+
+void halbtc8192e2ant_adc_back_off(IN struct btc_coexist *btcoexist,
+			  IN boolean force_exec, IN boolean adc_back_off)
+{
+	coex_dm->cur_adc_back_off = adc_back_off;
+
+	if (!force_exec) {
+		if (coex_dm->pre_adc_back_off == coex_dm->cur_adc_back_off)
+			return;
+	}
+	halbtc8192e2ant_set_adc_back_off(btcoexist, coex_dm->cur_adc_back_off);
+
+	coex_dm->pre_adc_back_off = coex_dm->cur_adc_back_off;
+}
+
+void halbtc8192e2ant_set_agc_table(IN struct btc_coexist *btcoexist,
+				   IN boolean agc_table_en)
+{
+	/* =================BB AGC Gain Table */
+	if (agc_table_en) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], BB Agc Table On!\n");
+		BTC_TRACE(trace_buf);
+		btcoexist->btc_write_4byte(btcoexist, 0xc78, 0x0a1A0001);
+		btcoexist->btc_write_4byte(btcoexist, 0xc78, 0x091B0001);
+		btcoexist->btc_write_4byte(btcoexist, 0xc78, 0x081C0001);
+		btcoexist->btc_write_4byte(btcoexist, 0xc78, 0x071D0001);
+		btcoexist->btc_write_4byte(btcoexist, 0xc78, 0x061E0001);
+		btcoexist->btc_write_4byte(btcoexist, 0xc78, 0x051F0001);
+	} else {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], BB Agc Table Off!\n");
+		BTC_TRACE(trace_buf);
+		btcoexist->btc_write_4byte(btcoexist, 0xc78, 0xaa1A0001);
+		btcoexist->btc_write_4byte(btcoexist, 0xc78, 0xa91B0001);
+		btcoexist->btc_write_4byte(btcoexist, 0xc78, 0xa81C0001);
+		btcoexist->btc_write_4byte(btcoexist, 0xc78, 0xa71D0001);
+		btcoexist->btc_write_4byte(btcoexist, 0xc78, 0xa61E0001);
+		btcoexist->btc_write_4byte(btcoexist, 0xc78, 0xa51F0001);
+	}
+}
+
+void halbtc8192e2ant_agc_table(IN struct btc_coexist *btcoexist,
+			       IN boolean force_exec, IN boolean agc_table_en)
+{
+	coex_dm->cur_agc_table_en = agc_table_en;
+
+	if (!force_exec) {
+		if (coex_dm->pre_agc_table_en == coex_dm->cur_agc_table_en)
+			return;
+	}
+	halbtc8192e2ant_set_agc_table(btcoexist, agc_table_en);
+
+	coex_dm->pre_agc_table_en = coex_dm->cur_agc_table_en;
+}
+
+void halbtc8192e2ant_set_coex_table(IN struct btc_coexist *btcoexist,
+	    IN u32 val0x6c0, IN u32 val0x6c4, IN u32 val0x6c8, IN u8 val0x6cc)
+{
+	btcoexist->btc_write_4byte(btcoexist, 0x6c0, val0x6c0);
+
+	btcoexist->btc_write_4byte(btcoexist, 0x6c4, val0x6c4);
+
+	btcoexist->btc_write_4byte(btcoexist, 0x6c8, val0x6c8);
+
+	btcoexist->btc_write_1byte(btcoexist, 0x6cc, val0x6cc);
+}
+
+void halbtc8192e2ant_coex_table(IN struct btc_coexist *btcoexist,
+			IN boolean force_exec, IN u32 val0x6c0, IN u32 val0x6c4,
+				IN u32 val0x6c8, IN u8 val0x6cc)
+{
+	coex_dm->cur_val0x6c0 = val0x6c0;
+	coex_dm->cur_val0x6c4 = val0x6c4;
+	coex_dm->cur_val0x6c8 = val0x6c8;
+	coex_dm->cur_val0x6cc = val0x6cc;
+
+	if (!force_exec) {
+		if ((coex_dm->pre_val0x6c0 == coex_dm->cur_val0x6c0) &&
+		    (coex_dm->pre_val0x6c4 == coex_dm->cur_val0x6c4) &&
+		    (coex_dm->pre_val0x6c8 == coex_dm->cur_val0x6c8) &&
+		    (coex_dm->pre_val0x6cc == coex_dm->cur_val0x6cc))
+			return;
+	}
+	halbtc8192e2ant_set_coex_table(btcoexist, val0x6c0, val0x6c4, val0x6c8,
+				       val0x6cc);
+
+	coex_dm->pre_val0x6c0 = coex_dm->cur_val0x6c0;
+	coex_dm->pre_val0x6c4 = coex_dm->cur_val0x6c4;
+	coex_dm->pre_val0x6c8 = coex_dm->cur_val0x6c8;
+	coex_dm->pre_val0x6cc = coex_dm->cur_val0x6cc;
+}
+
+void halbtc8192e2ant_coex_table_with_type(IN struct btc_coexist *btcoexist,
+		IN boolean force_exec, IN u8 type)
+{
+	switch (type) {
+	case 0:
+		halbtc8192e2ant_coex_table(btcoexist, force_exec, 0x55555555,
+					   0x5a5a5a5a, 0xffffff, 0x3);
+		break;
+	case 1:
+		halbtc8192e2ant_coex_table(btcoexist, force_exec, 0x5a5a5a5a,
+					   0x5a5a5a5a, 0xffffff, 0x3);
+		break;
+	case 2:
+		halbtc8192e2ant_coex_table(btcoexist, force_exec, 0x55dd55dd,
+					   0x5ada5ada, 0xffffff, 0x3);
+		break;
+	case 3:
+		halbtc8192e2ant_coex_table(btcoexist, force_exec, 0x5fdf5fdf,
+					   0x5fdb5fdb, 0xffffff, 0x3);
+		break;
+	case 4:
+		halbtc8192e2ant_coex_table(btcoexist, force_exec, 0xdfffdfff,
+					   0x5ffb5ffb, 0xffffff, 0x3);
+		break;
+	case 5:
+		halbtc8192e2ant_coex_table(btcoexist, force_exec, 0x5ddd5ddd,
+					   0x5fdb5fdb, 0xffffff, 0x3);
+		break;
+	case 6:
+		halbtc8192e2ant_coex_table(btcoexist, force_exec, 0x5fff5fff,
+					   0x5a5a5a5a, 0xffffff, 0x3);
+		break;
+	case 7:
+		if (coex_sta->scan_ap_num <= NOISY_AP_NUM_THRESH_8192E)
+			halbtc8192e2ant_coex_table(btcoexist, force_exec,  0xffffffff, 0xfafafafa, 0xffffff, 0x3);
+		else
+			halbtc8192e2ant_coex_table(btcoexist, force_exec, 0xffffffff, 0x5a5a5a5a, 0xffffff, 0x3);
+		break;
+	case 8:
+		halbtc8192e2ant_coex_table(btcoexist, force_exec, 0x5f5f5f5f, 0x5a5a5a5a, 0xffffff, 0x3);
+		break;
+	case 9:
+		halbtc8192e2ant_coex_table(btcoexist, force_exec, 0x55555555, 0xfafafafa, 0xffffff, 0x3);
+		break;
+	case 10:
+		halbtc8192e2ant_coex_table(btcoexist, force_exec, 0x55555555, 0xaaaaaaaa, 0xffffff, 0x3);
+		break;
+	case 11:
+		halbtc8192e2ant_coex_table(btcoexist, force_exec, 0x55555555, 0xfafafafa, 0xffffff, 0x3);
+		break;
+	default:
+		break;
+	}
+}
+
+void halbtc8192e2ant_set_fw_ignore_wlan_act(IN struct btc_coexist *btcoexist,
+		IN boolean enable)
+{
+	u8			h2c_parameter[1] = {0};
+
+	if (enable)
+		h2c_parameter[0] |= BIT(0);		/* function enable */
+
+	btcoexist->btc_fill_h2c(btcoexist, 0x63, 1, h2c_parameter);
+}
+
+void halbtc8192e2ant_ignore_wlan_act(IN struct btc_coexist *btcoexist,
+				     IN boolean force_exec, IN boolean enable)
+{
+	coex_dm->cur_ignore_wlan_act = enable;
+
+	if (!force_exec) {
+		if (coex_dm->pre_ignore_wlan_act ==
+		    coex_dm->cur_ignore_wlan_act)
+			return;
+	}
+	halbtc8192e2ant_set_fw_ignore_wlan_act(btcoexist, enable);
+
+	coex_dm->pre_ignore_wlan_act = coex_dm->cur_ignore_wlan_act;
+}
+
+void halbtc8192e2ant_set_lps_rpwm(IN struct btc_coexist *btcoexist,
+				  IN u8 lps_val, IN u8 rpwm_val)
+{
+	u8	lps = lps_val;
+	u8	rpwm = rpwm_val;
+
+	btcoexist->btc_set(btcoexist, BTC_SET_U1_LPS_VAL, &lps);
+	btcoexist->btc_set(btcoexist, BTC_SET_U1_RPWM_VAL, &rpwm);
+}
+
+void halbtc8192e2ant_lps_rpwm(IN struct btc_coexist *btcoexist,
+		      IN boolean force_exec, IN u8 lps_val, IN u8 rpwm_val)
+{
+	coex_dm->cur_lps = lps_val;
+	coex_dm->cur_rpwm = rpwm_val;
+
+	if (!force_exec) {
+		if ((coex_dm->pre_lps == coex_dm->cur_lps) &&
+		    (coex_dm->pre_rpwm == coex_dm->cur_rpwm))
+			return;
+	}
+	halbtc8192e2ant_set_lps_rpwm(btcoexist, lps_val, rpwm_val);
+
+	coex_dm->pre_lps = coex_dm->cur_lps;
+	coex_dm->pre_rpwm = coex_dm->cur_rpwm;
+}
+
+void halbtc8192e2ant_ps_tdma_check_for_power_save_state(
+	IN struct btc_coexist *btcoexist, IN boolean new_ps_state)
+{
+	u8	lps_mode = 0x0;
+	u8	h2c_parameter[5] = {0x8, 0, 0, 0, 0};
+
+	btcoexist->btc_get(btcoexist, BTC_GET_U1_LPS_MODE, &lps_mode);
+
+	if (lps_mode) {	/* already under LPS state */
+		if (new_ps_state) {
+			/* keep state under LPS, do nothing. */
+		} else {
+			/* will leave LPS state, turn off psTdma first */
+			/*halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 0);*/
+			btcoexist->btc_fill_h2c(btcoexist, 0x60, 5, h2c_parameter);
+
+		}
+	} else {					/* NO PS state */
+		if (new_ps_state) {
+			/* will enter LPS state, turn off psTdma first */
+			/*halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 0);*/
+			btcoexist->btc_fill_h2c(btcoexist, 0x60, 5, h2c_parameter);
+		} else {
+			/* keep state under NO PS state, do nothing. */
+		}
+	}
+}
+
+
+void halbtc8192e2ant_power_save_state(IN struct btc_coexist *btcoexist,
+		      IN u8 ps_type,  IN u8 lps_val,  IN u8 rpwm_val)
+{
+	boolean		low_pwr_disable = false;
+	boolean		bApEnable = false;
+
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_AP_MODE_ENABLE, &bApEnable);
+	if (bApEnable) {
+		ps_type = BTC_PS_WIFI_NATIVE;
+		lps_val = 0x0;
+		rpwm_val = 0x0;
+	}
+	/*for 8192e, NO 32k*/
+	low_pwr_disable = true;
+	switch (ps_type) {
+	case BTC_PS_WIFI_NATIVE:
+		coex_sta->force_lps_on = false;
+		btcoexist->btc_set(btcoexist, BTC_SET_ACT_DISABLE_LOW_POWER, &low_pwr_disable);
+		btcoexist->btc_set(btcoexist, BTC_SET_ACT_NORMAL_LPS, NULL);
+		break;
+	case BTC_PS_LPS_ON:
+		coex_sta->force_lps_on = true;
+		halbtc8192e2ant_ps_tdma_check_for_power_save_state(btcoexist, true);
+		halbtc8192e2ant_lps_rpwm(btcoexist, NORMAL_EXEC, lps_val, rpwm_val);
+		btcoexist->btc_set(btcoexist, BTC_SET_ACT_DISABLE_LOW_POWER, &low_pwr_disable);
+		/* power save must executed before psTdma. */
+		btcoexist->btc_set(btcoexist, BTC_SET_ACT_ENTER_LPS, NULL);
+		break;
+	case BTC_PS_LPS_OFF:
+		coex_sta->force_lps_on = false;
+		halbtc8192e2ant_ps_tdma_check_for_power_save_state(btcoexist, false);
+		btcoexist->btc_set(btcoexist, BTC_SET_ACT_LEAVE_LPS, NULL);
+		break;
+	default:
+		break;
+	}
+}
+
+void halbtc8192e2ant_set_fw_pstdma(IN struct btc_coexist *btcoexist,
+	   IN u8 byte1, IN u8 byte2, IN u8 byte3, IN u8 byte4, IN u8 byte5)
+{
+	u8			h2c_parameter[5] = {0};
+	u8			real_byte1 = byte1, real_byte5 = byte5;
+	boolean		ap_enable = false;
+
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_AP_MODE_ENABLE,
+			   &ap_enable);
+
+	if (ap_enable) {
+		if (byte1 & BIT(4) && !(byte1 & BIT(5))) {
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				    "[BTCoex], FW for 1Ant AP mode\n");
+			real_byte1 &= ~BIT(4);
+			real_byte1 |= BIT(5);
+
+			real_byte5 |= BIT(5);
+			real_byte5 &= ~BIT(6);
+		}
+	} else if ((byte1 & BIT(4)) && (!(byte1 & BIT(5))))
+		halbtc8192e2ant_power_save_state(btcoexist, BTC_PS_LPS_ON, 0x50, 0x4);
+	else
+		halbtc8192e2ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, 0x0, 0x0);
+
+
+	h2c_parameter[0] = byte1;
+	h2c_parameter[1] = byte2;
+	h2c_parameter[2] = byte3;
+	h2c_parameter[3] = byte4;
+	h2c_parameter[4] = byte5;
+
+	coex_dm->ps_tdma_para[0] = byte1;
+	coex_dm->ps_tdma_para[1] = byte2;
+	coex_dm->ps_tdma_para[2] = byte3;
+	coex_dm->ps_tdma_para[3] = byte4;
+	coex_dm->ps_tdma_para[4] = byte5;
+
+	btcoexist->btc_fill_h2c(btcoexist, 0x60, 5, h2c_parameter);
+}
+
+void halbtc8192e2ant_sw_mechanism1(IN struct btc_coexist *btcoexist,
+			   IN boolean shrink_rx_lpf, IN boolean low_penalty_ra,
+			   IN boolean limited_dig, IN boolean bt_lna_constrain)
+{
+	/*
+	u32	wifi_bw;
+
+	btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw);
+
+	if(BTC_WIFI_BW_HT40 != wifi_bw)
+	{
+		if (shrink_rx_lpf)
+			shrink_rx_lpf = false;
+	}
+	*/
+
+	halbtc8192e2ant_rf_shrink(btcoexist, NORMAL_EXEC, shrink_rx_lpf);
+	/* halbtc8192e2ant_low_penalty_ra(btcoexist, NORMAL_EXEC, low_penalty_ra); */
+}
+
+void halbtc8192e2ant_sw_mechanism2(IN struct btc_coexist *btcoexist,
+			   IN boolean agc_table_shift, IN boolean adc_back_off,
+			   IN boolean sw_dac_swing, IN u32 dac_swing_lvl)
+{
+	halbtc8192e2ant_agc_table(btcoexist, NORMAL_EXEC, agc_table_shift);
+	/* halbtc8192e2ant_adc_back_off(btcoexist, NORMAL_EXEC, adc_back_off); */
+	halbtc8192e2ant_dac_swing(btcoexist, NORMAL_EXEC, sw_dac_swing,
+				  dac_swing_lvl);
+}
+
+void halbtc8192e2ant_set_ant_path(IN struct btc_coexist *btcoexist,
+	  IN u8 ant_pos_type, IN boolean init_hwcfg, IN boolean wifi_off)
+{
+	u32			u32tmp = 0;
+
+	if (init_hwcfg) {
+		btcoexist->btc_write_1byte(btcoexist, 0x944, 0x24);
+		btcoexist->btc_write_4byte(btcoexist, 0x930, 0x700700);
+		if (btcoexist->chip_interface == BTC_INTF_USB)
+			btcoexist->btc_write_4byte(btcoexist, 0x64, 0x30430004);
+		else
+			btcoexist->btc_write_4byte(btcoexist, 0x64, 0x30030004);
+
+		/* 0x4c[27][24]='00', Set Antenna to BB */
+		u32tmp = btcoexist->btc_read_4byte(btcoexist, 0x4c);
+		u32tmp &= ~BIT(24);
+		u32tmp &= ~BIT(27);
+		btcoexist->btc_write_4byte(btcoexist, 0x4c, u32tmp);
+	} else if (wifi_off) {
+		if (btcoexist->chip_interface == BTC_INTF_USB)
+			btcoexist->btc_write_4byte(btcoexist, 0x64, 0x30430004);
+		else
+			btcoexist->btc_write_4byte(btcoexist, 0x64, 0x30030004);
+
+		/* 0x4c[27][24]='11', Set Antenna to BT, 0x64[8:7]=0, 0x64[2]=1 */
+		u32tmp = btcoexist->btc_read_4byte(btcoexist, 0x4c);
+		u32tmp |= BIT(24);
+		u32tmp |= BIT(27);
+		btcoexist->btc_write_4byte(btcoexist, 0x4c, u32tmp);
+	}
+
+	/* ext switch setting */
+	switch (ant_pos_type) {
+	case BTC_ANT_PATH_WIFI:
+		btcoexist->btc_write_1byte(btcoexist, 0x92c, 0x4);
+		break;
+	case BTC_ANT_PATH_BT:
+		btcoexist->btc_write_1byte(btcoexist, 0x92c, 0x20);
+		break;
+	default:
+	case BTC_ANT_PATH_PTA:
+		btcoexist->btc_write_1byte(btcoexist, 0x92c, 0x4);
+		break;
+	}
+}
+
+void halbtc8192e2ant_set_switch_ss_type(IN struct btc_coexist *btcoexist,
+					IN u8 ss_type)
+{
+	u8	mimo_ps = BTC_MIMO_PS_DYNAMIC;
+	u32	dis_ra_mask = 0x0;
+
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+		    "[BTCoex], REAL set SS Type = %d\n", ss_type);
+	BTC_TRACE(trace_buf);
+
+	dis_ra_mask = halbtc8192e2ant_decide_ra_mask(btcoexist, ss_type,
+			coex_dm->cur_ra_mask_type);
+	halbtc8192e2ant_update_ra_mask(btcoexist, FORCE_EXEC, dis_ra_mask);
+
+	if (ss_type == 1) {
+		/*halbtc8192e2ant_ps_tdma(btcoexist, FORCE_EXEC, false, 1);*/
+		/* switch ofdm path */
+		btcoexist->btc_write_1byte(btcoexist, 0xc04, 0x11);
+		btcoexist->btc_write_1byte(btcoexist, 0xd04, 0x1);
+		btcoexist->btc_write_4byte(btcoexist, 0x90c, 0x81111111);
+		/* switch cck patch */
+		/* btcoexist->btc_write_1byte_bitmask(btcoexist, 0xe77, 0x4, 0x1); */
+		/* btcoexist->btc_write_1byte(btcoexist, 0xa07, 0x81); */
+		mimo_ps = BTC_MIMO_PS_STATIC;
+	} else if (ss_type == 2) {
+		/*halbtc8192e2ant_ps_tdma(btcoexist, FORCE_EXEC, false, 0);*/
+		btcoexist->btc_write_1byte(btcoexist, 0xc04, 0x33);
+		btcoexist->btc_write_1byte(btcoexist, 0xd04, 0x3);
+		btcoexist->btc_write_4byte(btcoexist, 0x90c, 0x81121313);
+		/* remove, if 0xe77[2]=0x0 then CCK will fail, advised by Jenyu */
+		/* btcoexist->btc_write_1byte_bitmask(btcoexist, 0xe77, 0x4, 0x0); */
+		/* btcoexist->btc_write_1byte(btcoexist, 0xa07, 0x41); */
+		mimo_ps = BTC_MIMO_PS_DYNAMIC;
+	}
+
+	btcoexist->btc_set(btcoexist, BTC_SET_ACT_SEND_MIMO_PS,
+			   &mimo_ps);	/* set rx 1ss or 2ss */
+}
+
+void halbtc8192e2ant_switch_ss_type(IN struct btc_coexist *btcoexist,
+				    IN boolean force_exec, IN u8 new_ss_type)
+{
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+		    "[BTCoex], %s Switch SS Type = %d\n",
+		    (force_exec ? "force to" : ""), new_ss_type);
+	BTC_TRACE(trace_buf);
+	coex_dm->cur_ss_type = new_ss_type;
+
+	if (!force_exec) {
+		if (coex_dm->pre_ss_type == coex_dm->cur_ss_type)
+			return;
+	}
+	halbtc8192e2ant_set_switch_ss_type(btcoexist, coex_dm->cur_ss_type);
+
+	coex_dm->pre_ss_type = coex_dm->cur_ss_type;
+}
+
+void halbtc8192e2ant_ps_tdma(IN struct btc_coexist *btcoexist,
+		     IN boolean force_exec, IN boolean turn_on, IN u8 type)
+{
+	s8		wifi_duration_adjust = 0x0;
+
+	coex_dm->cur_ps_tdma_on = turn_on;
+	coex_dm->cur_ps_tdma = type;
+
+	if (!force_exec) {
+		if ((coex_dm->pre_ps_tdma_on == coex_dm->cur_ps_tdma_on) &&
+		    (coex_dm->pre_ps_tdma == coex_dm->cur_ps_tdma))
+			return;
+	}
+
+	if (coex_sta->scan_ap_num  >= 40)
+		wifi_duration_adjust = -15;
+	else if (coex_sta->scan_ap_num  >= 20)
+		wifi_duration_adjust = -10;
+
+
+	if (turn_on) {
+		switch (type) {
+		case 1:
+		default:	/*d1,wb*/
+			halbtc8192e2ant_set_fw_pstdma(btcoexist, 0xe3, 0x3c, 0x03, 0x11, 0x10);
+			break;
+		case 2:
+			halbtc8192e2ant_set_fw_pstdma(btcoexist, 0xe3, 0x32, 0x03, 0x11, 0x10);
+			break;
+		case 3:
+			halbtc8192e2ant_set_fw_pstdma(btcoexist, 0xe3, 0x28, 0x03, 0x11, 0x10);
+			break;
+		case 4:
+			halbtc8192e2ant_set_fw_pstdma(btcoexist, 0xe3, 0x1e, 0x03, 0x11, 0x10);
+			break;
+		case 5:		/*d1,pb,TXpause*/
+			halbtc8192e2ant_set_fw_pstdma(btcoexist, 0x63, 0x3c, 0x03, 0x90, 0x10);
+			break;
+		case 6:
+			halbtc8192e2ant_set_fw_pstdma(btcoexist, 0x63, 0x32, 0x03, 0x90, 0x10);
+			break;
+		case 7:
+			halbtc8192e2ant_set_fw_pstdma(btcoexist, 0x63, 0x28, 0x03, 0x90, 0x10);
+			break;
+		case 8:
+			halbtc8192e2ant_set_fw_pstdma(btcoexist, 0x63, 0x1e, 0x03, 0x90, 0x10);
+			break;
+		case 9:		/*d1,bb*/
+			halbtc8192e2ant_set_fw_pstdma(btcoexist, 0xe3, 0x3c, 0x03, 0x31, 0x10);
+			break;
+		case 10:
+			halbtc8192e2ant_set_fw_pstdma(btcoexist, 0xe3, 0x32, 0x03, 0x31, 0x10);
+			break;
+		case 11:
+			halbtc8192e2ant_set_fw_pstdma(btcoexist, 0xe3, 0x28, 0x03, 0x31, 0x10);
+			break;
+		case 12:
+			halbtc8192e2ant_set_fw_pstdma(btcoexist, 0xe3, 0x1e, 0x03, 0x31, 0x10);
+			break;
+		case 13:		/*d1,bb,TXpause*/
+			halbtc8192e2ant_set_fw_pstdma(btcoexist, 0xe3, 0x3c, 0x03, 0x30, 0x10);
+			break;
+		case 14:
+			halbtc8192e2ant_set_fw_pstdma(btcoexist, 0xe3, 0x32, 0x03, 0x30, 0x10);
+			break;
+		case 15:
+			halbtc8192e2ant_set_fw_pstdma(btcoexist, 0xe3, 0x28, 0x03, 0x30, 0x10);
+			break;
+		case 16:
+			halbtc8192e2ant_set_fw_pstdma(btcoexist, 0xe3, 0x1e, 0x03, 0x30, 0x10);
+			break;
+		case 17:
+			halbtc8192e2ant_set_fw_pstdma(btcoexist, 0x61, 0x20, 0x03, 0x10, 0x10);
+			break;
+		case 18:
+			halbtc8192e2ant_set_fw_pstdma(btcoexist, 0xe3, 0x5, 0x5, 0xe1, 0x90);
+			break;
+		case 19:
+			halbtc8192e2ant_set_fw_pstdma(btcoexist, 0xe3, 0x25, 0x25, 0xe1, 0x90);
+			break;
+		case 20:
+			halbtc8192e2ant_set_fw_pstdma(btcoexist, 0xe3, 0x25, 0x25, 0x60, 0x90);
+			break;
+		case 21:
+			halbtc8192e2ant_set_fw_pstdma(btcoexist, 0x61, 0x15, 0x03, 0x11, 0x11);
+			break;
+		case 22:	/* d1,wb */
+			halbtc8192e2ant_set_fw_pstdma(btcoexist, 0xe3, 0x14, 0x03, 0x11, 0x14);
+			break;
+		case 23:	/* d1,pb,TXpause */
+			halbtc8192e2ant_set_fw_pstdma(btcoexist, 0x63, 0x14, 0x03, 0x90, 0x14);
+			break;
+		case 24:	/* d1,bb */
+			halbtc8192e2ant_set_fw_pstdma(btcoexist, 0xe3, 0x14, 0x03, 0x31, 0x14);
+			break;
+		case 25:	/* d1,bb,TXpause */
+			halbtc8192e2ant_set_fw_pstdma(btcoexist, 0xe3, 0x14, 0x03, 0x30, 0x14);
+			break;
+		case 26:	/*d1,wp,noTXpause*/
+			halbtc8192e2ant_set_fw_pstdma(btcoexist, 0xe1, 0x3c, 0x03, 0x11, 0x10);
+			break;
+		case 27:	/*11,pp,noTXpause*/
+			halbtc8192e2ant_set_fw_pstdma(btcoexist, 0x61, 0x3c, 0x03, 0x11, 0x11);
+			break;
+		case 28:	/*11,pp,noTXpause*/
+			halbtc8192e2ant_set_fw_pstdma(btcoexist, 0x61, 0x50, 0x03, 0x11, 0x11);
+			break;
+		case 29:
+			halbtc8192e2ant_set_fw_pstdma(btcoexist, 0x61, 0x15, 0x03, 0x11, 0x11);
+			break;
+		case 30:
+			halbtc8192e2ant_set_fw_pstdma(btcoexist, 0xe3, 0x14, 0x03, 0x10, 0x14);
+			break;
+		case 31: /*d3,bb,TXpause*/
+			halbtc8192e2ant_set_fw_pstdma(btcoexist, 0xe3, 0x14, 0x03, 0x30, 0x94);
+			break;
+		case 32:
+			halbtc8192e2ant_set_fw_pstdma(btcoexist, 0x61, 0x35, 0x03, 0x11, 0x11);
+			break;
+		case 71:
+			halbtc8192e2ant_set_fw_pstdma(btcoexist, 0xe3, 0x1a, 0x1a, 0xe1, 0x90);
+			break;
+		/* following cases is for wifi rssi low // bad antenna isolation, started from 81 */
+		case 80:
+			halbtc8192e2ant_set_fw_pstdma(btcoexist, 0x51, 0x3c, 0x3, 0x10, 0x50);
+			break;
+		case 81:
+			halbtc8192e2ant_set_fw_pstdma(btcoexist, 0x51, 0x3a + wifi_duration_adjust, 0x3, 0x10, 0x50);
+			break;
+		case 82:
+			halbtc8192e2ant_set_fw_pstdma(btcoexist, 0x51, 0x30 + wifi_duration_adjust, 0x03, 0x10, 0x50);
+			break;
+		case 83:
+			halbtc8192e2ant_set_fw_pstdma(btcoexist, 0x51, 0x21, 0x03, 0x10, 0x50);
+			break;
+		case 84:
+			halbtc8192e2ant_set_fw_pstdma(btcoexist, 0x51, 0x15, 0x3, 0x10, 0x50);
+			break;
+		case 85:
+			halbtc8192e2ant_set_fw_pstdma(btcoexist, 0x51, 0x3a, 0x03, 0x10, 0x50);
+			break;
+		case 86:
+			halbtc8192e2ant_set_fw_pstdma(btcoexist, 0x51, 0x21, 0x03, 0x10, 0x50);
+			break;
+		case 87:
+			halbtc8192e2ant_set_fw_pstdma(btcoexist, 0x51, 0x14, 0x03, 0x10, 0x54);
+			break;
+		case 88:
+			halbtc8192e2ant_set_fw_pstdma(btcoexist, 0x53, 0x14, 0x03, 0x10, 0x54);
+			break;
+		}
+	} else {
+		/* disable PS tdma */
+		switch (type) {
+		default:
+		case 0:  /* ANT2PTA, 0x778=1 */
+			halbtc8192e2ant_set_fw_pstdma(btcoexist, 0x8, 0x0, 0x0, 0x0, 0x0);
+			halbtc8192e2ant_set_ant_path(btcoexist, BTC_ANT_PATH_PTA, false, false);
+			break;
+		case 1:  /* ANT2BT, 0x778=3 */
+			halbtc8192e2ant_set_fw_pstdma(btcoexist, 0x0, 0x0, 0x0, 0x8, 0x0);
+			delay_ms(5);
+			halbtc8192e2ant_set_ant_path(btcoexist, BTC_ANT_PATH_BT, false, false);
+			break;
+		}
+	}
+
+	/* update pre state */
+	coex_dm->pre_ps_tdma_on = coex_dm->cur_ps_tdma_on;
+	coex_dm->pre_ps_tdma = coex_dm->cur_ps_tdma;
+}
+
+
+void halbtc8192e2ant_coex_all_off(IN struct btc_coexist *btcoexist)
+{
+	/* fw all off */
+	halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 1);
+	halbtc8192e2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6);
+	halbtc8192e2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);
+
+	/* sw all off */
+	halbtc8192e2ant_sw_mechanism1(btcoexist, false, false, false, false);
+	halbtc8192e2ant_sw_mechanism2(btcoexist, false, false, false, 0x18);
+
+	/* hw all off */
+	halbtc8192e2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0);
+}
+
+void halbtc8192e2ant_init_coex_dm(IN struct btc_coexist *btcoexist)
+{
+	coex_sta->cnt_setup_link = 0;
+
+	/* force to reset coex mechanism */
+	halbtc8192e2ant_ps_tdma(btcoexist, FORCE_EXEC, false, 0);
+	halbtc8192e2ant_fw_dac_swing_lvl(btcoexist, FORCE_EXEC, 6);
+	halbtc8192e2ant_dec_bt_pwr(btcoexist, FORCE_EXEC, 0);
+
+	halbtc8192e2ant_coex_table_with_type(btcoexist, FORCE_EXEC, 0);
+	halbtc8192e2ant_switch_ss_type(btcoexist, FORCE_EXEC, 2);
+
+	halbtc8192e2ant_sw_mechanism1(btcoexist, false, false, false, false);
+	halbtc8192e2ant_sw_mechanism2(btcoexist, false, false, false, 0x18);
+}
+
+void halbtc8192e2ant_action_bt_inquiry(IN struct btc_coexist *btcoexist)
+{
+	struct	btc_bt_link_info	*bt_link_info = &btcoexist->bt_link_info;
+
+	if (coex_sta->wifi_is_high_pri_task && (!bt_link_info->a2dp_exist)) {
+		halbtc8192e2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 11);
+		halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 32);
+	} else {
+		halbtc8192e2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0);
+		halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 29);
+	}
+
+	halbtc8192e2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6);
+	halbtc8192e2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);
+
+	halbtc8192e2ant_sw_mechanism1(btcoexist, false, false, false, false);
+	halbtc8192e2ant_sw_mechanism2(btcoexist, false, false, false, 0x18);
+}
+
+boolean halbtc8192e2ant_is_common_action(IN struct btc_coexist *btcoexist)
+{
+	struct  btc_bt_link_info	*bt_link_info = &btcoexist->bt_link_info;
+	boolean			common = false, wifi_connected = false, wifi_busy = false;
+	boolean			bt_hs_on = false, low_pwr_disable = false;
+
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on);
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED,
+			   &wifi_connected);
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy);
+
+	if (bt_link_info->sco_exist || bt_link_info->hid_exist)
+		halbtc8192e2ant_limited_tx(btcoexist, NORMAL_EXEC, 1, 0, 0, 0);
+	else
+		halbtc8192e2ant_limited_tx(btcoexist, NORMAL_EXEC, 0, 0, 0, 0);
+
+	if (!wifi_connected) {
+
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], Wifi non-connected idle!!\n");
+		BTC_TRACE(trace_buf);
+
+		if ((coex_dm->bt_status == BT_8192E_2ANT_BT_STATUS_NON_CONNECTED_IDLE) ||
+		    (coex_dm->bt_status == BT_8192E_2ANT_BT_STATUS_CONNECTED_IDLE)) {
+			halbtc8192e2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 1);
+			halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 0);
+		} else {
+			halbtc8192e2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0);
+			halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 1);
+		}
+		halbtc8192e2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6);
+		halbtc8192e2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);
+
+		halbtc8192e2ant_sw_mechanism1(btcoexist, false, false, false, false);
+		halbtc8192e2ant_sw_mechanism2(btcoexist, false, false, false, 0x18);
+		common = true;
+	} else {
+		if (coex_dm->bt_status == BT_8192E_2ANT_BT_STATUS_NON_CONNECTED_IDLE) {
+			if (wifi_busy) {
+				BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], Wifi busy + BT non connected-idle!!\n");
+				BTC_TRACE(trace_buf);
+
+				halbtc8192e2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 9);
+				halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 26);
+				halbtc8192e2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6);
+				halbtc8192e2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);
+				halbtc8192e2ant_sw_mechanism1(btcoexist, false, false, false, false);
+				halbtc8192e2ant_sw_mechanism2(btcoexist, false, false, false, 0x18);
+				common = true;
+			} else {
+				BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], Wifi connected-idle + BT non connected-idle!!\n");
+				BTC_TRACE(trace_buf);
+				halbtc8192e2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0);
+				halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 0);
+				halbtc8192e2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6);
+				halbtc8192e2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);
+				halbtc8192e2ant_sw_mechanism1(btcoexist, false, false, false, false);
+				halbtc8192e2ant_sw_mechanism2(btcoexist, false, false, false, 0x18);
+				common = true;
+			}
+		} else if (coex_dm->bt_status == BT_8192E_2ANT_BT_STATUS_CONNECTED_IDLE) {
+
+			if (bt_hs_on)
+				return false;
+
+			if (wifi_busy) {
+				BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], Wifi busy + BT connected-idle!!\n");
+				BTC_TRACE(trace_buf);
+				halbtc8192e2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 10);
+				halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 27);
+				halbtc8192e2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6);
+				halbtc8192e2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);
+				halbtc8192e2ant_sw_mechanism1(btcoexist, false, false, false, false);
+				halbtc8192e2ant_sw_mechanism2(btcoexist, false, false, false, 0x18);
+				common = true;
+			} else {
+				BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], Wifi connected-idle + BT connected-idle!!\n");
+				BTC_TRACE(trace_buf);
+				halbtc8192e2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0);
+				halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 0);
+				halbtc8192e2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6);
+				halbtc8192e2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);
+				halbtc8192e2ant_sw_mechanism1(btcoexist, true, false, false, false);
+				halbtc8192e2ant_sw_mechanism2(btcoexist, false, false, false, 0x18);
+				common = true;
+			}
+		} else {
+
+			if (wifi_busy) {
+				BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+					"[BTCoex], Wifi Connected-Busy + BT Busy!!\n");
+				BTC_TRACE(trace_buf);
+				common = false;
+			} else {
+				BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+					"[BTCoex], Wifi Connected-Idle + BT Busy!!\n");
+				BTC_TRACE(trace_buf);
+				halbtc8192e2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0);
+				halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 21);
+				halbtc8192e2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6);
+				halbtc8192e2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);
+				halbtc8192e2ant_sw_mechanism1(btcoexist, false, false, false, false);
+				halbtc8192e2ant_sw_mechanism2(btcoexist, false, false, false, 0x18);
+				common = true;
+			}
+		}
+	}
+	return common;
+}
+
+
+void halbtc8192e2ant_tdma_duration_adjust(IN struct btc_coexist *btcoexist,
+		IN boolean sco_hid, IN boolean tx_pause, IN u8 max_interval)
+{
+	static s32		up, dn, m, n, wait_count;
+	s32			result;   /* 0: no change, +1: increase WiFi duration, -1: decrease WiFi duration */
+	u8			retry_count = 0;
+
+
+	if (!coex_dm->auto_tdma_adjust) {
+		coex_dm->auto_tdma_adjust = true;
+		{
+			if (sco_hid) {
+				if (tx_pause) {
+					if (max_interval == 1) {
+						halbtc8192e2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 13);
+						coex_dm->ps_tdma_du_adj_type =
+							13;
+					} else if (max_interval == 2) {
+						halbtc8192e2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 14);
+						coex_dm->ps_tdma_du_adj_type =
+							14;
+					} else if (max_interval == 3) {
+						halbtc8192e2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 15);
+						coex_dm->ps_tdma_du_adj_type =
+							15;
+					} else {
+						halbtc8192e2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 15);
+						coex_dm->ps_tdma_du_adj_type =
+							15;
+					}
+				} else {
+					if (max_interval == 1) {
+						halbtc8192e2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 9);
+						coex_dm->ps_tdma_du_adj_type =
+							9;
+					} else if (max_interval == 2) {
+						halbtc8192e2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 10);
+						coex_dm->ps_tdma_du_adj_type =
+							10;
+					} else if (max_interval == 3) {
+						halbtc8192e2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 11);
+						coex_dm->ps_tdma_du_adj_type =
+							11;
+					} else {
+						halbtc8192e2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 11);
+						coex_dm->ps_tdma_du_adj_type =
+							11;
+					}
+				}
+			} else {
+				if (tx_pause) {
+					if (max_interval == 1) {
+						halbtc8192e2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 5);
+						coex_dm->ps_tdma_du_adj_type =
+							5;
+					} else if (max_interval == 2) {
+						halbtc8192e2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 6);
+						coex_dm->ps_tdma_du_adj_type =
+							6;
+					} else if (max_interval == 3) {
+						halbtc8192e2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 7);
+						coex_dm->ps_tdma_du_adj_type =
+							7;
+					} else {
+						halbtc8192e2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 7);
+						coex_dm->ps_tdma_du_adj_type =
+							7;
+					}
+				} else {
+					if (max_interval == 1) {
+						halbtc8192e2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 1);
+						coex_dm->ps_tdma_du_adj_type =
+							1;
+					} else if (max_interval == 2) {
+						halbtc8192e2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 2);
+						coex_dm->ps_tdma_du_adj_type =
+							2;
+					} else if (max_interval == 3) {
+						halbtc8192e2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 3);
+						coex_dm->ps_tdma_du_adj_type =
+							3;
+					} else {
+						halbtc8192e2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 3);
+						coex_dm->ps_tdma_du_adj_type =
+							3;
+					}
+				}
+			}
+		}
+		/* ============ */
+		up = 0;
+		dn = 0;
+		m = 1;
+		n = 3;
+		result = 0;
+		wait_count = 0;
+	} else {
+		/* acquire the BT TRx retry count from BT_Info byte2 */
+		retry_count = coex_sta->bt_retry_cnt;
+		result = 0;
+		wait_count++;
+
+		if (retry_count ==
+		    0) { /* no retry in the last 2-second duration */
+			up++;
+			dn--;
+
+			if (dn <= 0)
+				dn = 0;
+
+			if (up >= n) {	/* if retry count during continuous n*2 seconds is 0, enlarge WiFi duration */
+				wait_count = 0;
+				n = 3;
+				up = 0;
+				dn = 0;
+				result = 1;
+			}
+		} else if (retry_count <=
+			   3) {	/* <=3 retry in the last 2-second duration */
+			up--;
+			dn++;
+
+			if (up <= 0)
+				up = 0;
+
+			if (dn == 2) {	/* if continuous 2 retry count(every 2 seconds) >0 and < 3, reduce WiFi duration */
+				if (wait_count <= 2)
+					m++; /* to avoid loop between the two levels */
+				else
+					m = 1;
+
+				if (m >= 20)  /* maximum of m = 20 ' will recheck if need to adjust wifi duration in maximum time interval 120 seconds */
+					m = 20;
+
+				n = 3 * m;
+				up = 0;
+				dn = 0;
+				wait_count = 0;
+				result = -1;
+			}
+		} else { /* retry count > 3, once retry count > 3, to reduce WiFi duration */
+			if (wait_count == 1)
+				m++; /* to avoid loop between the two levels */
+			else
+				m = 1;
+
+			if (m >= 20)  /* maximum of m = 20 ' will recheck if need to adjust wifi duration in maximum time interval 120 seconds */
+				m = 20;
+
+			n = 3 * m;
+			up = 0;
+			dn = 0;
+			wait_count = 0;
+			result = -1;
+		}
+
+		if (max_interval == 1) {
+			if (tx_pause) {
+				if (coex_dm->cur_ps_tdma == 1) {
+					halbtc8192e2ant_ps_tdma(btcoexist,
+							NORMAL_EXEC, true, 5);
+					coex_dm->ps_tdma_du_adj_type = 5;
+				} else if (coex_dm->cur_ps_tdma == 2) {
+					halbtc8192e2ant_ps_tdma(btcoexist,
+							NORMAL_EXEC, true, 6);
+					coex_dm->ps_tdma_du_adj_type = 6;
+				} else if (coex_dm->cur_ps_tdma == 3) {
+					halbtc8192e2ant_ps_tdma(btcoexist,
+							NORMAL_EXEC, true, 7);
+					coex_dm->ps_tdma_du_adj_type = 7;
+				} else if (coex_dm->cur_ps_tdma == 4) {
+					halbtc8192e2ant_ps_tdma(btcoexist,
+							NORMAL_EXEC, true, 8);
+					coex_dm->ps_tdma_du_adj_type = 8;
+				}
+				if (coex_dm->cur_ps_tdma == 9) {
+					halbtc8192e2ant_ps_tdma(btcoexist,
+							NORMAL_EXEC, true, 13);
+					coex_dm->ps_tdma_du_adj_type = 13;
+				} else if (coex_dm->cur_ps_tdma == 10) {
+					halbtc8192e2ant_ps_tdma(btcoexist,
+							NORMAL_EXEC, true, 14);
+					coex_dm->ps_tdma_du_adj_type = 14;
+				} else if (coex_dm->cur_ps_tdma == 11) {
+					halbtc8192e2ant_ps_tdma(btcoexist,
+							NORMAL_EXEC, true, 15);
+					coex_dm->ps_tdma_du_adj_type = 15;
+				} else if (coex_dm->cur_ps_tdma == 12) {
+					halbtc8192e2ant_ps_tdma(btcoexist,
+							NORMAL_EXEC, true, 16);
+					coex_dm->ps_tdma_du_adj_type = 16;
+				}
+
+				if (result == -1) {
+					if (coex_dm->cur_ps_tdma == 5) {
+						halbtc8192e2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 6);
+						coex_dm->ps_tdma_du_adj_type =
+							6;
+					} else if (coex_dm->cur_ps_tdma == 6) {
+						halbtc8192e2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 7);
+						coex_dm->ps_tdma_du_adj_type =
+							7;
+					} else if (coex_dm->cur_ps_tdma == 7) {
+						halbtc8192e2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 8);
+						coex_dm->ps_tdma_du_adj_type =
+							8;
+					} else if (coex_dm->cur_ps_tdma == 13) {
+						halbtc8192e2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 14);
+						coex_dm->ps_tdma_du_adj_type =
+							14;
+					} else if (coex_dm->cur_ps_tdma == 14) {
+						halbtc8192e2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 15);
+						coex_dm->ps_tdma_du_adj_type =
+							15;
+					} else if (coex_dm->cur_ps_tdma == 15) {
+						halbtc8192e2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 16);
+						coex_dm->ps_tdma_du_adj_type =
+							16;
+					}
+				} else if (result == 1) {
+					if (coex_dm->cur_ps_tdma == 8) {
+						halbtc8192e2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 7);
+						coex_dm->ps_tdma_du_adj_type =
+							7;
+					} else if (coex_dm->cur_ps_tdma == 7) {
+						halbtc8192e2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 6);
+						coex_dm->ps_tdma_du_adj_type =
+							6;
+					} else if (coex_dm->cur_ps_tdma == 6) {
+						halbtc8192e2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 5);
+						coex_dm->ps_tdma_du_adj_type =
+							5;
+					} else if (coex_dm->cur_ps_tdma == 16) {
+						halbtc8192e2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 15);
+						coex_dm->ps_tdma_du_adj_type =
+							15;
+					} else if (coex_dm->cur_ps_tdma == 15) {
+						halbtc8192e2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 14);
+						coex_dm->ps_tdma_du_adj_type =
+							14;
+					} else if (coex_dm->cur_ps_tdma == 14) {
+						halbtc8192e2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 13);
+						coex_dm->ps_tdma_du_adj_type =
+							13;
+					}
+				}
+			} else {
+				if (coex_dm->cur_ps_tdma == 5) {
+					halbtc8192e2ant_ps_tdma(btcoexist,
+							NORMAL_EXEC, true, 1);
+					coex_dm->ps_tdma_du_adj_type = 1;
+				} else if (coex_dm->cur_ps_tdma == 6) {
+					halbtc8192e2ant_ps_tdma(btcoexist,
+							NORMAL_EXEC, true, 2);
+					coex_dm->ps_tdma_du_adj_type = 2;
+				} else if (coex_dm->cur_ps_tdma == 7) {
+					halbtc8192e2ant_ps_tdma(btcoexist,
+							NORMAL_EXEC, true, 3);
+					coex_dm->ps_tdma_du_adj_type = 3;
+				} else if (coex_dm->cur_ps_tdma == 8) {
+					halbtc8192e2ant_ps_tdma(btcoexist,
+							NORMAL_EXEC, true, 4);
+					coex_dm->ps_tdma_du_adj_type = 4;
+				}
+				if (coex_dm->cur_ps_tdma == 13) {
+					halbtc8192e2ant_ps_tdma(btcoexist,
+							NORMAL_EXEC, true, 9);
+					coex_dm->ps_tdma_du_adj_type = 9;
+				} else if (coex_dm->cur_ps_tdma == 14) {
+					halbtc8192e2ant_ps_tdma(btcoexist,
+							NORMAL_EXEC, true, 10);
+					coex_dm->ps_tdma_du_adj_type = 10;
+				} else if (coex_dm->cur_ps_tdma == 15) {
+					halbtc8192e2ant_ps_tdma(btcoexist,
+							NORMAL_EXEC, true, 11);
+					coex_dm->ps_tdma_du_adj_type = 11;
+				} else if (coex_dm->cur_ps_tdma == 16) {
+					halbtc8192e2ant_ps_tdma(btcoexist,
+							NORMAL_EXEC, true, 12);
+					coex_dm->ps_tdma_du_adj_type = 12;
+				}
+
+				if (result == -1) {
+					if (coex_dm->cur_ps_tdma == 1) {
+						halbtc8192e2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 2);
+						coex_dm->ps_tdma_du_adj_type =
+							2;
+					} else if (coex_dm->cur_ps_tdma == 2) {
+						halbtc8192e2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 3);
+						coex_dm->ps_tdma_du_adj_type =
+							3;
+					} else if (coex_dm->cur_ps_tdma == 3) {
+						halbtc8192e2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 4);
+						coex_dm->ps_tdma_du_adj_type =
+							4;
+					} else if (coex_dm->cur_ps_tdma == 9) {
+						halbtc8192e2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 10);
+						coex_dm->ps_tdma_du_adj_type =
+							10;
+					} else if (coex_dm->cur_ps_tdma == 10) {
+						halbtc8192e2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 11);
+						coex_dm->ps_tdma_du_adj_type =
+							11;
+					} else if (coex_dm->cur_ps_tdma == 11) {
+						halbtc8192e2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 12);
+						coex_dm->ps_tdma_du_adj_type =
+							12;
+					}
+				} else if (result == 1) {
+					if (coex_dm->cur_ps_tdma == 4) {
+						halbtc8192e2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 3);
+						coex_dm->ps_tdma_du_adj_type =
+							3;
+					} else if (coex_dm->cur_ps_tdma == 3) {
+						halbtc8192e2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 2);
+						coex_dm->ps_tdma_du_adj_type =
+							2;
+					} else if (coex_dm->cur_ps_tdma == 2) {
+						halbtc8192e2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 1);
+						coex_dm->ps_tdma_du_adj_type =
+							1;
+					} else if (coex_dm->cur_ps_tdma == 1) {
+						halbtc8192e2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 71);
+						coex_dm->ps_tdma_du_adj_type =
+							71;
+					} else if (coex_dm->cur_ps_tdma == 12) {
+						halbtc8192e2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 11);
+						coex_dm->ps_tdma_du_adj_type =
+							11;
+					} else if (coex_dm->cur_ps_tdma == 11) {
+						halbtc8192e2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 10);
+						coex_dm->ps_tdma_du_adj_type =
+							10;
+					} else if (coex_dm->cur_ps_tdma == 10) {
+						halbtc8192e2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 9);
+						coex_dm->ps_tdma_du_adj_type =
+							9;
+					}
+				}
+			}
+		} else if (max_interval == 2) {
+			if (tx_pause) {
+				if (coex_dm->cur_ps_tdma == 1) {
+					halbtc8192e2ant_ps_tdma(btcoexist,
+							NORMAL_EXEC, true, 6);
+					coex_dm->ps_tdma_du_adj_type = 6;
+				} else if (coex_dm->cur_ps_tdma == 2) {
+					halbtc8192e2ant_ps_tdma(btcoexist,
+							NORMAL_EXEC, true, 6);
+					coex_dm->ps_tdma_du_adj_type = 6;
+				} else if (coex_dm->cur_ps_tdma == 3) {
+					halbtc8192e2ant_ps_tdma(btcoexist,
+							NORMAL_EXEC, true, 7);
+					coex_dm->ps_tdma_du_adj_type = 7;
+				} else if (coex_dm->cur_ps_tdma == 4) {
+					halbtc8192e2ant_ps_tdma(btcoexist,
+							NORMAL_EXEC, true, 8);
+					coex_dm->ps_tdma_du_adj_type = 8;
+				}
+				if (coex_dm->cur_ps_tdma == 9) {
+					halbtc8192e2ant_ps_tdma(btcoexist,
+							NORMAL_EXEC, true, 14);
+					coex_dm->ps_tdma_du_adj_type = 14;
+				} else if (coex_dm->cur_ps_tdma == 10) {
+					halbtc8192e2ant_ps_tdma(btcoexist,
+							NORMAL_EXEC, true, 14);
+					coex_dm->ps_tdma_du_adj_type = 14;
+				} else if (coex_dm->cur_ps_tdma == 11) {
+					halbtc8192e2ant_ps_tdma(btcoexist,
+							NORMAL_EXEC, true, 15);
+					coex_dm->ps_tdma_du_adj_type = 15;
+				} else if (coex_dm->cur_ps_tdma == 12) {
+					halbtc8192e2ant_ps_tdma(btcoexist,
+							NORMAL_EXEC, true, 16);
+					coex_dm->ps_tdma_du_adj_type = 16;
+				}
+				if (result == -1) {
+					if (coex_dm->cur_ps_tdma == 5) {
+						halbtc8192e2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 6);
+						coex_dm->ps_tdma_du_adj_type =
+							6;
+					} else if (coex_dm->cur_ps_tdma == 6) {
+						halbtc8192e2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 7);
+						coex_dm->ps_tdma_du_adj_type =
+							7;
+					} else if (coex_dm->cur_ps_tdma == 7) {
+						halbtc8192e2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 8);
+						coex_dm->ps_tdma_du_adj_type =
+							8;
+					} else if (coex_dm->cur_ps_tdma == 13) {
+						halbtc8192e2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 14);
+						coex_dm->ps_tdma_du_adj_type =
+							14;
+					} else if (coex_dm->cur_ps_tdma == 14) {
+						halbtc8192e2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 15);
+						coex_dm->ps_tdma_du_adj_type =
+							15;
+					} else if (coex_dm->cur_ps_tdma == 15) {
+						halbtc8192e2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 16);
+						coex_dm->ps_tdma_du_adj_type =
+							16;
+					}
+				} else if (result == 1) {
+					if (coex_dm->cur_ps_tdma == 8) {
+						halbtc8192e2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 7);
+						coex_dm->ps_tdma_du_adj_type =
+							7;
+					} else if (coex_dm->cur_ps_tdma == 7) {
+						halbtc8192e2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 6);
+						coex_dm->ps_tdma_du_adj_type =
+							6;
+					} else if (coex_dm->cur_ps_tdma == 6) {
+						halbtc8192e2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 6);
+						coex_dm->ps_tdma_du_adj_type =
+							6;
+					} else if (coex_dm->cur_ps_tdma == 16) {
+						halbtc8192e2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 15);
+						coex_dm->ps_tdma_du_adj_type =
+							15;
+					} else if (coex_dm->cur_ps_tdma == 15) {
+						halbtc8192e2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 14);
+						coex_dm->ps_tdma_du_adj_type =
+							14;
+					} else if (coex_dm->cur_ps_tdma == 14) {
+						halbtc8192e2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 14);
+						coex_dm->ps_tdma_du_adj_type =
+							14;
+					}
+				}
+			} else {
+				if (coex_dm->cur_ps_tdma == 5) {
+					halbtc8192e2ant_ps_tdma(btcoexist,
+							NORMAL_EXEC, true, 2);
+					coex_dm->ps_tdma_du_adj_type = 2;
+				} else if (coex_dm->cur_ps_tdma == 6) {
+					halbtc8192e2ant_ps_tdma(btcoexist,
+							NORMAL_EXEC, true, 2);
+					coex_dm->ps_tdma_du_adj_type = 2;
+				} else if (coex_dm->cur_ps_tdma == 7) {
+					halbtc8192e2ant_ps_tdma(btcoexist,
+							NORMAL_EXEC, true, 3);
+					coex_dm->ps_tdma_du_adj_type = 3;
+				} else if (coex_dm->cur_ps_tdma == 8) {
+					halbtc8192e2ant_ps_tdma(btcoexist,
+							NORMAL_EXEC, true, 4);
+					coex_dm->ps_tdma_du_adj_type = 4;
+				}
+				if (coex_dm->cur_ps_tdma == 13) {
+					halbtc8192e2ant_ps_tdma(btcoexist,
+							NORMAL_EXEC, true, 10);
+					coex_dm->ps_tdma_du_adj_type = 10;
+				} else if (coex_dm->cur_ps_tdma == 14) {
+					halbtc8192e2ant_ps_tdma(btcoexist,
+							NORMAL_EXEC, true, 10);
+					coex_dm->ps_tdma_du_adj_type = 10;
+				} else if (coex_dm->cur_ps_tdma == 15) {
+					halbtc8192e2ant_ps_tdma(btcoexist,
+							NORMAL_EXEC, true, 11);
+					coex_dm->ps_tdma_du_adj_type = 11;
+				} else if (coex_dm->cur_ps_tdma == 16) {
+					halbtc8192e2ant_ps_tdma(btcoexist,
+							NORMAL_EXEC, true, 12);
+					coex_dm->ps_tdma_du_adj_type = 12;
+				}
+				if (result == -1) {
+					if (coex_dm->cur_ps_tdma == 1) {
+						halbtc8192e2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 2);
+						coex_dm->ps_tdma_du_adj_type =
+							2;
+					} else if (coex_dm->cur_ps_tdma == 2) {
+						halbtc8192e2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 3);
+						coex_dm->ps_tdma_du_adj_type =
+							3;
+					} else if (coex_dm->cur_ps_tdma == 3) {
+						halbtc8192e2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 4);
+						coex_dm->ps_tdma_du_adj_type =
+							4;
+					} else if (coex_dm->cur_ps_tdma == 9) {
+						halbtc8192e2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 10);
+						coex_dm->ps_tdma_du_adj_type =
+							10;
+					} else if (coex_dm->cur_ps_tdma == 10) {
+						halbtc8192e2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 11);
+						coex_dm->ps_tdma_du_adj_type =
+							11;
+					} else if (coex_dm->cur_ps_tdma == 11) {
+						halbtc8192e2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 12);
+						coex_dm->ps_tdma_du_adj_type =
+							12;
+					}
+				} else if (result == 1) {
+					if (coex_dm->cur_ps_tdma == 4) {
+						halbtc8192e2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 3);
+						coex_dm->ps_tdma_du_adj_type =
+							3;
+					} else if (coex_dm->cur_ps_tdma == 3) {
+						halbtc8192e2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 2);
+						coex_dm->ps_tdma_du_adj_type =
+							2;
+					} else if (coex_dm->cur_ps_tdma == 2) {
+						halbtc8192e2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 2);
+						coex_dm->ps_tdma_du_adj_type =
+							2;
+					} else if (coex_dm->cur_ps_tdma == 12) {
+						halbtc8192e2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 11);
+						coex_dm->ps_tdma_du_adj_type =
+							11;
+					} else if (coex_dm->cur_ps_tdma == 11) {
+						halbtc8192e2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 10);
+						coex_dm->ps_tdma_du_adj_type =
+							10;
+					} else if (coex_dm->cur_ps_tdma == 10) {
+						halbtc8192e2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 10);
+						coex_dm->ps_tdma_du_adj_type =
+							10;
+					}
+				}
+			}
+		} else if (max_interval == 3) {
+			if (tx_pause) {
+				if (coex_dm->cur_ps_tdma == 1) {
+					halbtc8192e2ant_ps_tdma(btcoexist,
+							NORMAL_EXEC, true, 7);
+					coex_dm->ps_tdma_du_adj_type = 7;
+				} else if (coex_dm->cur_ps_tdma == 2) {
+					halbtc8192e2ant_ps_tdma(btcoexist,
+							NORMAL_EXEC, true, 7);
+					coex_dm->ps_tdma_du_adj_type = 7;
+				} else if (coex_dm->cur_ps_tdma == 3) {
+					halbtc8192e2ant_ps_tdma(btcoexist,
+							NORMAL_EXEC, true, 7);
+					coex_dm->ps_tdma_du_adj_type = 7;
+				} else if (coex_dm->cur_ps_tdma == 4) {
+					halbtc8192e2ant_ps_tdma(btcoexist,
+							NORMAL_EXEC, true, 8);
+					coex_dm->ps_tdma_du_adj_type = 8;
+				}
+				if (coex_dm->cur_ps_tdma == 9) {
+					halbtc8192e2ant_ps_tdma(btcoexist,
+							NORMAL_EXEC, true, 15);
+					coex_dm->ps_tdma_du_adj_type = 15;
+				} else if (coex_dm->cur_ps_tdma == 10) {
+					halbtc8192e2ant_ps_tdma(btcoexist,
+							NORMAL_EXEC, true, 15);
+					coex_dm->ps_tdma_du_adj_type = 15;
+				} else if (coex_dm->cur_ps_tdma == 11) {
+					halbtc8192e2ant_ps_tdma(btcoexist,
+							NORMAL_EXEC, true, 15);
+					coex_dm->ps_tdma_du_adj_type = 15;
+				} else if (coex_dm->cur_ps_tdma == 12) {
+					halbtc8192e2ant_ps_tdma(btcoexist,
+							NORMAL_EXEC, true, 16);
+					coex_dm->ps_tdma_du_adj_type = 16;
+				}
+				if (result == -1) {
+					if (coex_dm->cur_ps_tdma == 5) {
+						halbtc8192e2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 7);
+						coex_dm->ps_tdma_du_adj_type =
+							7;
+					} else if (coex_dm->cur_ps_tdma == 6) {
+						halbtc8192e2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 7);
+						coex_dm->ps_tdma_du_adj_type =
+							7;
+					} else if (coex_dm->cur_ps_tdma == 7) {
+						halbtc8192e2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 8);
+						coex_dm->ps_tdma_du_adj_type =
+							8;
+					} else if (coex_dm->cur_ps_tdma == 13) {
+						halbtc8192e2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 15);
+						coex_dm->ps_tdma_du_adj_type =
+							15;
+					} else if (coex_dm->cur_ps_tdma == 14) {
+						halbtc8192e2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 15);
+						coex_dm->ps_tdma_du_adj_type =
+							15;
+					} else if (coex_dm->cur_ps_tdma == 15) {
+						halbtc8192e2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 16);
+						coex_dm->ps_tdma_du_adj_type =
+							16;
+					}
+				} else if (result == 1) {
+					if (coex_dm->cur_ps_tdma == 8) {
+						halbtc8192e2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 7);
+						coex_dm->ps_tdma_du_adj_type =
+							7;
+					} else if (coex_dm->cur_ps_tdma == 7) {
+						halbtc8192e2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 7);
+						coex_dm->ps_tdma_du_adj_type =
+							7;
+					} else if (coex_dm->cur_ps_tdma == 6) {
+						halbtc8192e2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 7);
+						coex_dm->ps_tdma_du_adj_type =
+							7;
+					} else if (coex_dm->cur_ps_tdma == 16) {
+						halbtc8192e2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 15);
+						coex_dm->ps_tdma_du_adj_type =
+							15;
+					} else if (coex_dm->cur_ps_tdma == 15) {
+						halbtc8192e2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 15);
+						coex_dm->ps_tdma_du_adj_type =
+							15;
+					} else if (coex_dm->cur_ps_tdma == 14) {
+						halbtc8192e2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 15);
+						coex_dm->ps_tdma_du_adj_type =
+							15;
+					}
+				}
+			} else {
+				if (coex_dm->cur_ps_tdma == 5) {
+					halbtc8192e2ant_ps_tdma(btcoexist,
+							NORMAL_EXEC, true, 3);
+					coex_dm->ps_tdma_du_adj_type = 3;
+				} else if (coex_dm->cur_ps_tdma == 6) {
+					halbtc8192e2ant_ps_tdma(btcoexist,
+							NORMAL_EXEC, true, 3);
+					coex_dm->ps_tdma_du_adj_type = 3;
+				} else if (coex_dm->cur_ps_tdma == 7) {
+					halbtc8192e2ant_ps_tdma(btcoexist,
+							NORMAL_EXEC, true, 3);
+					coex_dm->ps_tdma_du_adj_type = 3;
+				} else if (coex_dm->cur_ps_tdma == 8) {
+					halbtc8192e2ant_ps_tdma(btcoexist,
+							NORMAL_EXEC, true, 4);
+					coex_dm->ps_tdma_du_adj_type = 4;
+				}
+				if (coex_dm->cur_ps_tdma == 13) {
+					halbtc8192e2ant_ps_tdma(btcoexist,
+							NORMAL_EXEC, true, 11);
+					coex_dm->ps_tdma_du_adj_type = 11;
+				} else if (coex_dm->cur_ps_tdma == 14) {
+					halbtc8192e2ant_ps_tdma(btcoexist,
+							NORMAL_EXEC, true, 11);
+					coex_dm->ps_tdma_du_adj_type = 11;
+				} else if (coex_dm->cur_ps_tdma == 15) {
+					halbtc8192e2ant_ps_tdma(btcoexist,
+							NORMAL_EXEC, true, 11);
+					coex_dm->ps_tdma_du_adj_type = 11;
+				} else if (coex_dm->cur_ps_tdma == 16) {
+					halbtc8192e2ant_ps_tdma(btcoexist,
+							NORMAL_EXEC, true, 12);
+					coex_dm->ps_tdma_du_adj_type = 12;
+				}
+				if (result == -1) {
+					if (coex_dm->cur_ps_tdma == 1) {
+						halbtc8192e2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 3);
+						coex_dm->ps_tdma_du_adj_type =
+							3;
+					} else if (coex_dm->cur_ps_tdma == 2) {
+						halbtc8192e2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 3);
+						coex_dm->ps_tdma_du_adj_type =
+							3;
+					} else if (coex_dm->cur_ps_tdma == 3) {
+						halbtc8192e2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 4);
+						coex_dm->ps_tdma_du_adj_type =
+							4;
+					} else if (coex_dm->cur_ps_tdma == 9) {
+						halbtc8192e2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 11);
+						coex_dm->ps_tdma_du_adj_type =
+							11;
+					} else if (coex_dm->cur_ps_tdma == 10) {
+						halbtc8192e2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 11);
+						coex_dm->ps_tdma_du_adj_type =
+							11;
+					} else if (coex_dm->cur_ps_tdma == 11) {
+						halbtc8192e2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 12);
+						coex_dm->ps_tdma_du_adj_type =
+							12;
+					}
+				} else if (result == 1) {
+					if (coex_dm->cur_ps_tdma == 4) {
+						halbtc8192e2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 3);
+						coex_dm->ps_tdma_du_adj_type =
+							3;
+					} else if (coex_dm->cur_ps_tdma == 3) {
+						halbtc8192e2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 3);
+						coex_dm->ps_tdma_du_adj_type =
+							3;
+					} else if (coex_dm->cur_ps_tdma == 2) {
+						halbtc8192e2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 3);
+						coex_dm->ps_tdma_du_adj_type =
+							3;
+					} else if (coex_dm->cur_ps_tdma == 12) {
+						halbtc8192e2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 11);
+						coex_dm->ps_tdma_du_adj_type =
+							11;
+					} else if (coex_dm->cur_ps_tdma == 11) {
+						halbtc8192e2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 11);
+						coex_dm->ps_tdma_du_adj_type =
+							11;
+					} else if (coex_dm->cur_ps_tdma == 10) {
+						halbtc8192e2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 11);
+						coex_dm->ps_tdma_du_adj_type =
+							11;
+					}
+				}
+			}
+		}
+	}
+
+	/* if current PsTdma not match with the recorded one (when scan, dhcp...), */
+	/* then we have to adjust it back to the previous record one. */
+	if (coex_dm->cur_ps_tdma != coex_dm->ps_tdma_du_adj_type) {
+		boolean	scan = false, link = false, roam = false;
+
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			"[BTCoex], PsTdma type dismatch!!!, cur_ps_tdma=%d, recordPsTdma=%d\n",
+			    coex_dm->cur_ps_tdma, coex_dm->ps_tdma_du_adj_type);
+		BTC_TRACE(trace_buf);
+
+		btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_SCAN, &scan);
+		btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_LINK, &link);
+		btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_ROAM, &roam);
+
+		if (!scan && !link && !roam)
+			halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, true,
+						coex_dm->ps_tdma_du_adj_type);
+		else {
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				"[BTCoex], roaming/link/scan is under progress, will adjust next time!!!\n");
+			BTC_TRACE(trace_buf);
+		}
+	}
+}
+
+/* ******************
+ * pstdma for wifi rssi low
+ * ****************** */
+void halbtc8192e2ant_tdma_duration_adjust_for_wifi_rssi_low(
+	IN struct btc_coexist *btcoexist/* , */ /* IN u8 wifi_status */)
+{
+	static s32		up, dn, m, n, wait_count;
+	s32			result;   /* 0: no change, +1: increase WiFi duration, -1: decrease WiFi duration */
+	u8			retry_count = 0, bt_info_ext;
+
+	coex_dm->auto_tdma_adjust = false;
+
+	retry_count = coex_sta->bt_retry_cnt;
+	bt_info_ext = coex_sta->bt_info_ext;
+
+	if (!coex_dm->auto_tdma_adjust_low_rssi) {
+		coex_dm->auto_tdma_adjust_low_rssi = true;
+		halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 81);
+		coex_dm->ps_tdma_du_adj_type = 81;
+		/* ============ */
+		up = 0;
+		dn = 0;
+		m = 1;
+		n = 3;
+		result = 0;
+		wait_count = 0;
+	} else {
+		/* acquire the BT TRx retry count from BT_Info byte2
+		*		retry_count = coex_sta->bt_retry_cnt;
+		*		bt_info_ext = coex_sta->bt_info_ext; */
+		result = 0;
+		wait_count++;
+
+		if ((coex_sta->low_priority_tx) > 1050 ||
+		    (coex_sta->low_priority_rx) > 1250)
+			retry_count++;
+
+		if (retry_count ==
+		    0) { /* no retry in the last 2-second duration */
+			up++;
+			dn--;
+
+			if (dn <= 0)
+				dn = 0;
+
+			if (up >= n) {	/* if retry count during continuous n*2 seconds is 0, enlarge WiFi duration */
+				wait_count = 0;
+				n = 3;
+				up = 0;
+				dn = 0;
+				result = 1;
+			}
+		} else if (retry_count <=
+			   3) {	/* <=3 retry in the last 2-second duration */
+			up--;
+			dn++;
+
+			if (up <= 0)
+				up = 0;
+
+			if (dn == 2) {	/* if continuous 2 retry count(every 2 seconds) >0 and < 3, reduce WiFi duration */
+				if (wait_count <= 2)
+					m++; /* to avoid loop between the two levels */
+				else
+					m = 1;
+
+				if (m >= 20)  /* maximum of m = 20 ' will recheck if need to adjust wifi duration in maximum time interval 120 seconds */
+					m = 20;
+
+				n = 3 * m;
+				up = 0;
+				dn = 0;
+				wait_count = 0;
+				result = -1;
+			}
+		} else { /* retry count > 3, once retry count > 3, to reduce WiFi duration */
+			if (wait_count == 1)
+				m++; /* to avoid loop between the two levels */
+			else
+				m = 1;
+
+			if (m >= 20)  /* maximum of m = 20 ' will recheck if need to adjust wifi duration in maximum time interval 120 seconds */
+				m = 20;
+
+			n = 3 * m;
+			up = 0;
+			dn = 0;
+			wait_count = 0;
+			result = -1;
+		}
+
+		if (result == -1) {
+			if (coex_dm->cur_ps_tdma == 80) {
+				halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC,
+							true, 81);
+				coex_dm->ps_tdma_du_adj_type = 81;
+			} else if (coex_dm->cur_ps_tdma == 81) {
+				halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC,
+							true, 82);
+				coex_dm->ps_tdma_du_adj_type = 82;
+			} else if (coex_dm->cur_ps_tdma == 82) {
+				halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC,
+							true, 83);
+				coex_dm->ps_tdma_du_adj_type = 83;
+			} else if (coex_dm->cur_ps_tdma == 83) {
+				halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC,
+							true, 84);
+				coex_dm->ps_tdma_du_adj_type = 84;
+			}
+		} else if (result == 1) {
+			if (coex_dm->cur_ps_tdma == 84) {
+				halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC,
+							true, 83);
+				coex_dm->ps_tdma_du_adj_type = 83;
+			} else if (coex_dm->cur_ps_tdma == 83) {
+				halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC,
+							true, 82);
+				coex_dm->ps_tdma_du_adj_type = 82;
+			} else if (coex_dm->cur_ps_tdma == 82) {
+				halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC,
+							true, 81);
+				coex_dm->ps_tdma_du_adj_type = 81;
+			} else if ((coex_dm->cur_ps_tdma == 81) &&
+				   (coex_sta->scan_ap_num <= 5)) {
+				halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC,
+							true, 81);
+				coex_dm->ps_tdma_du_adj_type = 81;
+			}
+		}
+
+		if (coex_dm->cur_ps_tdma != 80 &&
+		    coex_dm->cur_ps_tdma != 81 &&
+		    coex_dm->cur_ps_tdma != 82 &&
+		    coex_dm->cur_ps_tdma != 83 &&
+		    coex_dm->cur_ps_tdma != 84) {
+			/* recover to previous adjust type */
+			halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, true,
+						coex_dm->ps_tdma_du_adj_type);
+		}
+	}
+}
+
+
+void halbtc8192e2ant_get_bt_rssi_threshold(IN struct btc_coexist *btcoexist,
+		IN u8 *pThres0, IN u8 *pThres1)
+{
+	u8 ant_type;
+
+	struct  btc_board_info  *board_info = &btcoexist->board_info;
+
+	ant_type = board_info->ant_type;
+
+	switch (ant_type) {
+	case BTC_ANT_TYPE_0:
+		*pThres0 = 100;
+		*pThres1 = 100;
+		break;
+	case BTC_ANT_TYPE_1:
+		*pThres0 = 34;
+		*pThres1 = 42;
+		break;
+	case BTC_ANT_TYPE_2:
+		*pThres0 = 34;
+		*pThres1 = 42;
+		break;
+	case BTC_ANT_TYPE_3:
+		*pThres0 = 34;
+		*pThres1 = 42;
+		break;
+	case BTC_ANT_TYPE_4:
+		*pThres0 = 34;
+		*pThres1 = 42;
+		break;
+	default:
+		break;
+	}
+}
+
+void halbtc8192e2ant_action_bt_relink(IN struct btc_coexist *btcoexist)
+{
+	if (coex_sta->wifi_is_high_pri_task) {
+		halbtc8192e2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0);
+		halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 1);
+	} else {
+		halbtc8192e2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0);
+		halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 0);
+	}
+	halbtc8192e2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6);
+	halbtc8192e2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);
+	halbtc8192e2ant_sw_mechanism1(btcoexist, false, false, false, false);
+	halbtc8192e2ant_sw_mechanism2(btcoexist, false, false, false, 0x18);
+}
+
+
+/* SCO only or SCO+PAN(HS) */
+void halbtc8192e2ant_action_sco(IN struct btc_coexist *btcoexist)
+{
+	u8	wifi_rssi_state, bt_rssi_state = BTC_RSSI_STATE_STAY_LOW;
+	u32	wifi_bw;
+	u8	bt_thresh0 = 0, bt_thresh1 = 0;
+
+	halbtc8192e2ant_get_bt_rssi_threshold(btcoexist, &bt_thresh0,
+					      &bt_thresh1);
+	bt_rssi_state = halbtc8192e2ant_bt_rssi_state(3, bt_thresh0,
+			bt_thresh1);
+
+	wifi_rssi_state = halbtc8192e2ant_wifi_rssi_state(btcoexist, 0, 2, 34,
+			  0);
+
+	if (BTC_RSSI_HIGH(wifi_rssi_state) && (!BTC_RSSI_LOW(bt_rssi_state)))
+		halbtc8192e2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0);
+	else
+		halbtc8192e2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0);
+
+
+	if (BTC_RSSI_HIGH(wifi_rssi_state) &&	(!BTC_RSSI_LOW(bt_rssi_state)))
+		halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 0);
+	else
+		halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 0);
+
+
+	halbtc8192e2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);
+	halbtc8192e2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, 0x8);
+	halbtc8192e2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6);
+
+	halbtc8192e2ant_sw_mechanism1(btcoexist, false, false, false, false);
+	halbtc8192e2ant_sw_mechanism2(btcoexist, false, false, false, 0x18);
+}
+
+void halbtc8192e2ant_action_sco_pan(IN struct btc_coexist *btcoexist)
+{
+	u8	wifi_rssi_state, bt_rssi_state = BTC_RSSI_STATE_STAY_LOW;
+	u32	wifi_bw;
+	u8		bt_thresh0 = 0, bt_thresh1 = 0;
+
+
+	halbtc8192e2ant_get_bt_rssi_threshold(btcoexist, &bt_thresh0,
+					      &bt_thresh1);
+	bt_rssi_state = halbtc8192e2ant_bt_rssi_state(3, bt_thresh0,
+			bt_thresh1);
+
+	wifi_rssi_state = halbtc8192e2ant_wifi_rssi_state(btcoexist, 0, 2, 34,
+			  0);
+
+	if (BTC_RSSI_HIGH(wifi_rssi_state) && (!BTC_RSSI_LOW(bt_rssi_state)))
+		halbtc8192e2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4);
+	else
+		halbtc8192e2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0);
+
+
+
+	if (BTC_RSSI_HIGH(wifi_rssi_state) && (!BTC_RSSI_LOW(bt_rssi_state)))
+		halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 10);
+	else
+		halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 86);
+
+	halbtc8192e2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, 0x8);
+	halbtc8192e2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6);
+
+	halbtc8192e2ant_sw_mechanism1(btcoexist, false, false, false, false);
+	if (BTC_RSSI_HIGH(wifi_rssi_state) && (!BTC_RSSI_LOW(bt_rssi_state)) &&
+	    (coex_sta->scan_ap_num < NOISY_AP_NUM_THRESH_8192E))
+		halbtc8192e2ant_sw_mechanism2(btcoexist, false, false, false,
+					      0x18);
+	else if (BTC_RSSI_HIGH(wifi_rssi_state) &&
+		 (!BTC_RSSI_LOW(bt_rssi_state)) &&
+		 (coex_sta->scan_ap_num > NOISY_AP_NUM_THRESH_8192E))
+		halbtc8192e2ant_sw_mechanism2(btcoexist, false, false, false,
+					      0x18);
+	else
+		halbtc8192e2ant_sw_mechanism2(btcoexist, false, false, false,
+					      0x18);
+}
+
+
+void halbtc8192e2ant_action_hid(IN struct btc_coexist *btcoexist)
+{
+	u8	wifi_rssi_state, bt_rssi_state = BTC_RSSI_STATE_HIGH;
+	u32	wifi_bw;
+	u8	anttype = 0;
+
+	btcoexist->btc_get(btcoexist, BTC_GET_U1_ANT_TYPE, &anttype);
+
+	wifi_rssi_state = halbtc8192e2ant_wifi_rssi_state(btcoexist, 0, 2, 34, 0);
+	bt_rssi_state = halbtc8192e2ant_bt_rssi_state(3, 34, 42);
+
+	if (anttype == 0) {
+		/*ANTTYPE = 0   2ant with SPDT*/
+		halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 28);
+		halbtc8192e2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0);
+	} else if (anttype == 1) {
+		/*2ant with coupler and bad ant. isolation, 3ant with bad ant. isolation*/
+		halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 28);
+		halbtc8192e2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0);
+	} else if (anttype == 2) {
+		/*ANTTYPE = 2, 2ant with coupler and normal/good ant. isolation, 3ant with normal ant. isolation*/
+		if (BTC_RSSI_HIGH(wifi_rssi_state) && (!BTC_RSSI_LOW(bt_rssi_state))) {
+			halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 9);
+			halbtc8192e2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 3);
+		} else {
+			halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 9);
+			halbtc8192e2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 3);
+		}
+	} else if (anttype == 3) {
+		/*ANTTYPE = 3,  3ant with good ant. isolation*/
+		if (BTC_RSSI_HIGH(wifi_rssi_state) && (!BTC_RSSI_LOW(bt_rssi_state))) {
+			halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 1);
+			halbtc8192e2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0);
+		} else {
+			halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 1);
+			halbtc8192e2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0);
+		}
+	}
+
+	halbtc8192e2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);
+
+	halbtc8192e2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, 0x8);
+	halbtc8192e2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6);
+
+	halbtc8192e2ant_sw_mechanism1(btcoexist, false, false, false, false);
+	halbtc8192e2ant_sw_mechanism2(btcoexist, false, false, false, 0x18);
+}
+
+/* A2DP only / PAN(EDR) only/ A2DP+PAN(HS) */
+void halbtc8192e2ant_action_a2dp(IN struct btc_coexist *btcoexist)
+{
+	u8		wifi_rssi_state, bt_rssi_state = BTC_RSSI_STATE_HIGH;
+	u32		wifi_bw;
+	boolean		long_dist = false;
+	u8	anttype = 0;
+
+	btcoexist->btc_get(btcoexist, BTC_GET_U1_ANT_TYPE, &anttype);
+
+	wifi_rssi_state = halbtc8192e2ant_wifi_rssi_state(btcoexist, 0, 2, 34, 0);
+	bt_rssi_state = halbtc8192e2ant_bt_rssi_state(3, 34, 42);
+
+	if (anttype == 0) {
+		/*ANTTYPE = 0   2ant with SPDT*/
+		if ((coex_sta->scan_ap_num > 40) && (BTC_RSSI_HIGH(wifi_rssi_state) && (!BTC_RSSI_LOW(bt_rssi_state)))) {
+			halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 30);
+			halbtc8192e2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 7);
+		} else {
+			halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 88);
+			halbtc8192e2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 7);
+		}
+	} else if (anttype == 1) {
+		/*2ant with coupler and bad ant. isolation, 3ant with bad ant. isolation*/
+		if (BTC_RSSI_HIGH(wifi_rssi_state) && (!BTC_RSSI_LOW(bt_rssi_state))) {
+			halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 25);
+			halbtc8192e2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 7);
+		} else {
+			halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 88);
+			halbtc8192e2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 7);
+		}
+	} else if (anttype == 2) {
+		/*ANTTYPE = 2, 2ant with coupler and normal/good ant. isolation, 3ant with normal ant. isolation*/
+		if (BTC_RSSI_HIGH(wifi_rssi_state) && (!BTC_RSSI_LOW(bt_rssi_state))) {
+			halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 22);
+			halbtc8192e2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 5);
+		} else {
+			halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 88);
+			halbtc8192e2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 7);
+		}
+	} else if (anttype == 3) {
+		/*ANTTYPE = 3,  3ant with good ant. isolation*/
+		halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 1);
+		halbtc8192e2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0);
+	}
+	halbtc8192e2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);
+	halbtc8192e2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, 0x8);
+	halbtc8192e2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6);
+	halbtc8192e2ant_sw_mechanism1(btcoexist, false, false, false, false);
+	halbtc8192e2ant_sw_mechanism2(btcoexist, false, false, false, 0x18);
+}
+
+void halbtc8192e2ant_action_a2dp_pan_hs(IN struct btc_coexist *btcoexist)
+{
+	u8		wifi_rssi_state, bt_rssi_state = BTC_RSSI_STATE_HIGH;
+	u32		wifi_bw;
+
+	wifi_rssi_state = halbtc8192e2ant_wifi_rssi_state(btcoexist, 0, 2, 15,
+			  0);
+	bt_rssi_state = halbtc8192e2ant_bt_rssi_state(3, 34, 42);
+
+	halbtc8192e2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, 0x8);
+
+	halbtc8192e2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6);
+	halbtc8192e2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 2);
+
+	if ((bt_rssi_state == BTC_RSSI_STATE_LOW) ||
+	    (bt_rssi_state == BTC_RSSI_STATE_STAY_LOW)) {
+		halbtc8192e2ant_tdma_duration_adjust(btcoexist, false, true, 2);
+		halbtc8192e2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);
+	} else if ((bt_rssi_state == BTC_RSSI_STATE_MEDIUM) ||
+		   (bt_rssi_state == BTC_RSSI_STATE_STAY_MEDIUM)) {
+		halbtc8192e2ant_tdma_duration_adjust(btcoexist, false, false,
+						     2);
+		halbtc8192e2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2);
+	} else if ((bt_rssi_state == BTC_RSSI_STATE_HIGH) ||
+		   (bt_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
+		halbtc8192e2ant_tdma_duration_adjust(btcoexist, false, false,
+						     2);
+		halbtc8192e2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 4);
+	}
+
+	/* sw mechanism */
+	btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw);
+	if (BTC_WIFI_BW_HT40 == wifi_bw) {
+		if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) ||
+		    (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
+			halbtc8192e2ant_sw_mechanism1(btcoexist, true, false,
+						      false, false);
+			halbtc8192e2ant_sw_mechanism2(btcoexist, true, false,
+						      true, 0x6);
+		} else {
+			halbtc8192e2ant_sw_mechanism1(btcoexist, true, false,
+						      false, false);
+			halbtc8192e2ant_sw_mechanism2(btcoexist, false, false,
+						      true, 0x6);
+		}
+	} else {
+		if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) ||
+		    (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
+			halbtc8192e2ant_sw_mechanism1(btcoexist, false, false,
+						      false, false);
+			halbtc8192e2ant_sw_mechanism2(btcoexist, true, false,
+						      true, 0x6);
+		} else {
+			halbtc8192e2ant_sw_mechanism1(btcoexist, false, false,
+						      false, false);
+			halbtc8192e2ant_sw_mechanism2(btcoexist, false, false,
+						      true, 0x6);
+		}
+	}
+}
+
+void halbtc8192e2ant_action_pan_edr(IN struct btc_coexist *btcoexist)
+{
+	u8		wifi_rssi_state, bt_rssi_state = BTC_RSSI_STATE_HIGH;
+	u32		wifi_bw;
+	u8		bt_thresh0 = 0, bt_thresh1 = 0;
+
+	halbtc8192e2ant_get_bt_rssi_threshold(btcoexist, &bt_thresh0,
+					      &bt_thresh1);
+	bt_rssi_state = halbtc8192e2ant_bt_rssi_state(3, bt_thresh0,
+			bt_thresh1);
+	/*	wifi_rssi_state = halbtc8192e2ant_wifi_rssi_state(btcoexist, 0, 2, 34, 0); */
+	wifi_rssi_state = BTC_RSSI_STATE_LOW;
+
+	if (BTC_RSSI_HIGH(wifi_rssi_state) && (!BTC_RSSI_LOW(bt_rssi_state)))
+		halbtc8192e2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 2);
+	else
+		halbtc8192e2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0);
+
+	if (BTC_RSSI_HIGH(wifi_rssi_state) &&	(!BTC_RSSI_LOW(bt_rssi_state)))
+		halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 1);
+	else
+		halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 85);
+
+	halbtc8192e2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, 0x8);
+	halbtc8192e2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6);
+
+	halbtc8192e2ant_sw_mechanism1(btcoexist, false, false, false, false);
+	halbtc8192e2ant_sw_mechanism2(btcoexist, false, false, false, 0x18);
+}
+
+/* PAN(HS) only */
+void halbtc8192e2ant_action_pan_hs(IN struct btc_coexist *btcoexist)
+{
+	u8		wifi_rssi_state, bt_rssi_state = BTC_RSSI_STATE_HIGH;
+	u32		wifi_bw;
+
+	wifi_rssi_state = halbtc8192e2ant_wifi_rssi_state(btcoexist, 0, 2, 15,
+			  0);
+	bt_rssi_state = halbtc8192e2ant_bt_rssi_state(3, 34, 42);
+
+	halbtc8192e2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, 0x8);
+
+	halbtc8192e2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6);
+
+	halbtc8192e2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 2);
+
+	if ((bt_rssi_state == BTC_RSSI_STATE_LOW) ||
+	    (bt_rssi_state == BTC_RSSI_STATE_STAY_LOW))
+		halbtc8192e2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);
+	else if ((bt_rssi_state == BTC_RSSI_STATE_MEDIUM) ||
+		 (bt_rssi_state == BTC_RSSI_STATE_STAY_MEDIUM))
+		halbtc8192e2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2);
+	else if ((bt_rssi_state == BTC_RSSI_STATE_HIGH) ||
+		 (bt_rssi_state == BTC_RSSI_STATE_STAY_HIGH))
+		halbtc8192e2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 4);
+	halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 1);
+
+	btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw);
+	if (BTC_WIFI_BW_HT40 == wifi_bw) {
+		if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) ||
+		    (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
+			halbtc8192e2ant_sw_mechanism1(btcoexist, true, false,
+						      false, false);
+			halbtc8192e2ant_sw_mechanism2(btcoexist, true, false,
+						      false, 0x18);
+		} else {
+			halbtc8192e2ant_sw_mechanism1(btcoexist, true, false,
+						      false, false);
+			halbtc8192e2ant_sw_mechanism2(btcoexist, false, false,
+						      false, 0x18);
+		}
+	} else {
+		if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) ||
+		    (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
+			halbtc8192e2ant_sw_mechanism1(btcoexist, false, false,
+						      false, false);
+			halbtc8192e2ant_sw_mechanism2(btcoexist, true, false,
+						      false, 0x18);
+		} else {
+			halbtc8192e2ant_sw_mechanism1(btcoexist, false, false,
+						      false, false);
+			halbtc8192e2ant_sw_mechanism2(btcoexist, false, false,
+						      false, 0x18);
+		}
+	}
+}
+
+/* PAN(EDR)+A2DP */
+void halbtc8192e2ant_action_pan_edr_a2dp(IN struct btc_coexist *btcoexist)
+{
+	u8		wifi_rssi_state, bt_rssi_state = BTC_RSSI_STATE_HIGH;
+	u32		wifi_bw;
+	u8		bt_thresh0 = 0, bt_thresh1 = 0;
+
+	halbtc8192e2ant_get_bt_rssi_threshold(btcoexist, &bt_thresh0,
+					      &bt_thresh1);
+	bt_rssi_state = halbtc8192e2ant_bt_rssi_state(3, bt_thresh0,
+			bt_thresh1);
+	/*	wifi_rssi_state = halbtc8192e2ant_wifi_rssi_state(btcoexist, 0, 2, 34, 0); */
+	wifi_rssi_state = BTC_RSSI_STATE_LOW;
+
+	if (BTC_RSSI_HIGH(wifi_rssi_state) && (!BTC_RSSI_LOW(bt_rssi_state)))
+		halbtc8192e2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 2);
+	else
+		halbtc8192e2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0);
+
+	if (BTC_RSSI_HIGH(wifi_rssi_state) && (!BTC_RSSI_LOW(bt_rssi_state)))
+		halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 4);
+	else
+		halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 86);
+
+	halbtc8192e2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, 0x8);
+	halbtc8192e2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6);
+
+	halbtc8192e2ant_sw_mechanism1(btcoexist, false, false, false, false);
+	halbtc8192e2ant_sw_mechanism2(btcoexist, false, false, false, 0x18);
+
+}
+
+void halbtc8192e2ant_action_pan_edr_hid(IN struct btc_coexist *btcoexist)
+{
+	u8		wifi_rssi_state, bt_rssi_state = BTC_RSSI_STATE_HIGH;
+	u32		wifi_bw;
+	u8		bt_thresh0 = 0, bt_thresh1 = 0;
+
+	halbtc8192e2ant_get_bt_rssi_threshold(btcoexist, &bt_thresh0,
+					      &bt_thresh1);
+	bt_rssi_state = halbtc8192e2ant_bt_rssi_state(3, bt_thresh0,
+			bt_thresh1);
+
+	wifi_rssi_state = halbtc8192e2ant_wifi_rssi_state(btcoexist, 0, 2, 34,
+			  0);
+
+	if (BTC_RSSI_HIGH(wifi_rssi_state) && (!BTC_RSSI_LOW(bt_rssi_state)))
+		halbtc8192e2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 3);
+	else
+		halbtc8192e2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0);
+
+	if (BTC_RSSI_HIGH(wifi_rssi_state) &&	(!BTC_RSSI_LOW(bt_rssi_state)))
+		halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 10);
+	else
+		halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 86);
+
+	halbtc8192e2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, 0x8);
+	halbtc8192e2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6);
+
+	halbtc8192e2ant_sw_mechanism1(btcoexist, false, false, false, false);
+	halbtc8192e2ant_sw_mechanism2(btcoexist, false, false, false, 0x18);
+}
+
+/* HID+A2DP+PAN(EDR) */
+void halbtc8192e2ant_action_hid_a2dp_pan_edr(IN struct btc_coexist *btcoexist)
+{
+	u8		wifi_rssi_state, bt_rssi_state = BTC_RSSI_STATE_HIGH;
+	u32		wifi_bw;
+	u8		bt_thresh0 = 0, bt_thresh1 = 0;
+
+	halbtc8192e2ant_get_bt_rssi_threshold(btcoexist, &bt_thresh0,
+					      &bt_thresh1);
+	bt_rssi_state = halbtc8192e2ant_bt_rssi_state(3, bt_thresh0,
+			bt_thresh1);
+	wifi_rssi_state = halbtc8192e2ant_wifi_rssi_state(btcoexist, 0, 2, 34,
+			  0);
+
+	if (BTC_RSSI_HIGH(wifi_rssi_state) && (!BTC_RSSI_LOW(bt_rssi_state)))
+		halbtc8192e2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 3);
+	else
+		halbtc8192e2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0);
+
+	if (BTC_RSSI_HIGH(wifi_rssi_state) && (!BTC_RSSI_LOW(bt_rssi_state)))
+		halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 4);
+	else
+		halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 86);
+
+	halbtc8192e2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, 0x8);
+	halbtc8192e2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6);
+
+	halbtc8192e2ant_sw_mechanism1(btcoexist, false, false, false, false);
+	halbtc8192e2ant_sw_mechanism2(btcoexist, false, false, false, 0x18);
+}
+
+void halbtc8192e2ant_action_hid_a2dp(IN struct btc_coexist *btcoexist)
+{
+	u8		wifi_rssi_state, bt_rssi_state = BTC_RSSI_STATE_HIGH;
+	u32		wifi_bw;
+	u8		bt_thresh0 = 0, bt_thresh1 = 0, anttype = 0;
+
+	btcoexist->btc_get(btcoexist, BTC_GET_U1_ANT_TYPE, &anttype);
+
+	wifi_rssi_state = halbtc8192e2ant_wifi_rssi_state(btcoexist, 0, 2, 34, 0);
+	bt_rssi_state = halbtc8192e2ant_bt_rssi_state(3, 34, 42);
+
+	if (anttype == 0) {
+		/*2ant with SPDT*/
+		if ((coex_sta->scan_ap_num > 40) && (BTC_RSSI_HIGH(wifi_rssi_state) && (!BTC_RSSI_LOW(bt_rssi_state)))) {
+			halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 31);
+			halbtc8192e2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 11);
+		} else {
+			halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 88);
+			halbtc8192e2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 8);
+		}
+	} else if (anttype == 1) {
+		/*2ant with coupler and bad ant. isolation, 3ant with bad ant. isolation*/
+		if (BTC_RSSI_HIGH(wifi_rssi_state) && (!BTC_RSSI_LOW(bt_rssi_state))) {
+			halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 25);
+			halbtc8192e2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 8);
+		} else {
+			halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 87);
+			halbtc8192e2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 8);
+		}
+	} else if (anttype == 2) {
+		/*ANTTYPE = 2, 2ant with coupler and normal/good ant. isolation, 3ant with normal ant. isolation*/
+		if (BTC_RSSI_HIGH(wifi_rssi_state) && (!BTC_RSSI_LOW(bt_rssi_state))) {
+			halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 25);
+			halbtc8192e2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 8);
+		} else {
+			halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 87);
+			halbtc8192e2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 8);
+		}
+	} else if (anttype == 3) {
+		/*ANTTYPE = 3,  3ant with good ant. isolation*/
+		halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 1);
+		halbtc8192e2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0);
+	}
+
+	halbtc8192e2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, 0x8);
+	halbtc8192e2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6);
+
+	halbtc8192e2ant_sw_mechanism1(btcoexist, false, false, false, false);
+	halbtc8192e2ant_sw_mechanism2(btcoexist, false, false, false, 0x18);
+}
+
+void halbtc8192e2ant_run_coexist_mechanism(IN struct btc_coexist *btcoexist)
+{
+	u8				algorithm = 0;
+
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+		    "[BTCoex], RunCoexistMechanism()===>\n");
+	BTC_TRACE(trace_buf);
+
+	if (btcoexist->manual_control) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			"[BTCoex], RunCoexistMechanism(), return for Manual CTRL <===\n");
+		BTC_TRACE(trace_buf);
+		return;
+	}
+
+	if (coex_sta->under_ips) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], wifi is under IPS !!!\n");
+		BTC_TRACE(trace_buf);
+		return;
+	}
+
+	algorithm = halbtc8192e2ant_action_algorithm(btcoexist);
+	if (coex_sta->c2h_bt_inquiry_page &&
+	    (BT_8192E_2ANT_COEX_ALGO_PANHS != algorithm)) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], BT is under inquiry/page scan !!\n");
+		BTC_TRACE(trace_buf);
+		halbtc8192e2ant_action_bt_inquiry(btcoexist);
+		return;
+	}
+
+	if (coex_sta->is_setup_link) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], BT is re-link !!!\n");
+		halbtc8192e2ant_action_bt_relink(btcoexist);
+		return;
+	}
+
+
+	coex_dm->cur_algorithm = algorithm;
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], Algorithm = %d\n",
+		    coex_dm->cur_algorithm);
+	BTC_TRACE(trace_buf);
+
+	if (halbtc8192e2ant_is_common_action(btcoexist)) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], Action 2-Ant common.\n");
+		BTC_TRACE(trace_buf);
+		coex_dm->auto_tdma_adjust = false;
+		coex_dm->auto_tdma_adjust_low_rssi = false;
+
+	} else {
+		if (coex_dm->cur_algorithm != coex_dm->pre_algorithm) {
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				"[BTCoex], pre_algorithm=%d, cur_algorithm=%d\n",
+				coex_dm->pre_algorithm, coex_dm->cur_algorithm);
+			BTC_TRACE(trace_buf);
+			coex_dm->auto_tdma_adjust = false;
+			coex_dm->auto_tdma_adjust_low_rssi = false;
+
+		}
+		switch (coex_dm->cur_algorithm) {
+		case BT_8192E_2ANT_COEX_ALGO_SCO:
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				"[BTCoex], Action 2-Ant, algorithm = SCO.\n");
+			BTC_TRACE(trace_buf);
+			halbtc8192e2ant_action_sco(btcoexist);
+			break;
+		case BT_8192E_2ANT_COEX_ALGO_SCO_PAN:
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				"[BTCoex], Action 2-Ant, algorithm = SCO+PAN(EDR).\n");
+			BTC_TRACE(trace_buf);
+			halbtc8192e2ant_action_sco_pan(btcoexist);
+			break;
+		case BT_8192E_2ANT_COEX_ALGO_HID:
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				"[BTCoex], Action 2-Ant, algorithm = HID.\n");
+			BTC_TRACE(trace_buf);
+			halbtc8192e2ant_action_hid(btcoexist);
+			break;
+		case BT_8192E_2ANT_COEX_ALGO_A2DP:
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				"[BTCoex], Action 2-Ant, algorithm = A2DP.\n");
+			BTC_TRACE(trace_buf);
+			halbtc8192e2ant_action_a2dp(btcoexist);
+			break;
+		case BT_8192E_2ANT_COEX_ALGO_A2DP_PANHS:
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				"[BTCoex], Action 2-Ant, algorithm = A2DP+PAN(HS).\n");
+			BTC_TRACE(trace_buf);
+			halbtc8192e2ant_action_a2dp_pan_hs(btcoexist);
+			break;
+		case BT_8192E_2ANT_COEX_ALGO_PANEDR:
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				"[BTCoex], Action 2-Ant, algorithm = PAN(EDR).\n");
+			BTC_TRACE(trace_buf);
+			halbtc8192e2ant_action_pan_edr(btcoexist);
+			break;
+		case BT_8192E_2ANT_COEX_ALGO_PANHS:
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				"[BTCoex], Action 2-Ant, algorithm = HS mode.\n");
+			BTC_TRACE(trace_buf);
+			halbtc8192e2ant_action_pan_hs(btcoexist);
+			break;
+		case BT_8192E_2ANT_COEX_ALGO_PANEDR_A2DP:
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				"[BTCoex], Action 2-Ant, algorithm = PAN+A2DP.\n");
+			BTC_TRACE(trace_buf);
+			halbtc8192e2ant_action_pan_edr_a2dp(btcoexist);
+			break;
+		case BT_8192E_2ANT_COEX_ALGO_PANEDR_HID:
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				"[BTCoex], Action 2-Ant, algorithm = PAN(EDR)+HID.\n");
+			BTC_TRACE(trace_buf);
+			halbtc8192e2ant_action_pan_edr_hid(btcoexist);
+			break;
+		case BT_8192E_2ANT_COEX_ALGO_HID_A2DP_PANEDR:
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				"[BTCoex], Action 2-Ant, algorithm = HID+A2DP+PAN.\n");
+			BTC_TRACE(trace_buf);
+			halbtc8192e2ant_action_hid_a2dp_pan_edr(
+				btcoexist);
+			break;
+		case BT_8192E_2ANT_COEX_ALGO_HID_A2DP:
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				"[BTCoex], Action 2-Ant, algorithm = HID+A2DP.\n");
+			BTC_TRACE(trace_buf);
+			halbtc8192e2ant_action_hid_a2dp(btcoexist);
+			break;
+		default:
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				"[BTCoex], Action 2-Ant, algorithm = unknown!!\n");
+			BTC_TRACE(trace_buf);
+			halbtc8192e2ant_coex_all_off(btcoexist);
+			break;
+		}
+		coex_dm->pre_algorithm = coex_dm->cur_algorithm;
+	}
+}
+
+void halbtc8192e2ant_init_hw_config(IN struct btc_coexist *btcoexist,
+				    IN boolean back_up)
+{
+	u16	u16tmp = 0;
+	u8	u8tmp = 0;
+
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+		    "[BTCoex], 2Ant Init HW Config!!\n");
+	BTC_TRACE(trace_buf);
+
+	if (back_up) {
+		/* backup rf 0x1e value */
+		coex_dm->bt_rf_0x1e_backup =
+			btcoexist->btc_get_rf_reg(btcoexist, BTC_RF_A, 0x1e,
+						  0xfffff);
+
+		coex_dm->backup_arfr_cnt1 = btcoexist->btc_read_4byte(btcoexist,
+					    0x430);
+		coex_dm->backup_arfr_cnt2 = btcoexist->btc_read_4byte(btcoexist,
+					    0x434);
+		coex_dm->backup_retry_limit = btcoexist->btc_read_2byte(
+						      btcoexist, 0x42a);
+		coex_dm->backup_ampdu_max_time = btcoexist->btc_read_1byte(
+				btcoexist, 0x456);
+	}
+
+	/* antenna sw ctrl to bt */
+	halbtc8192e2ant_set_ant_path(btcoexist, BTC_ANT_PATH_BT, true, false);
+
+	halbtc8192e2ant_coex_table_with_type(btcoexist, FORCE_EXEC, 0);
+
+	/* antenna switch control parameter */
+	/*	btcoexist->btc_write_4byte(btcoexist, 0x858, 0x55555555); */
+
+	/* coex parameters */
+	btcoexist->btc_write_1byte(btcoexist, 0x778, 0x3);
+	/* 0x790[5:0]=0x5 */
+	u8tmp = btcoexist->btc_read_1byte(btcoexist, 0x790);
+	u8tmp &= 0xc0;
+	u8tmp |= 0x5;
+	btcoexist->btc_write_1byte(btcoexist, 0x790, u8tmp);
+
+	/* enable counter statistics */
+	btcoexist->btc_write_1byte(btcoexist, 0x76e, 0x4);
+
+	/* enable PTA */
+	btcoexist->btc_write_1byte(btcoexist, 0x40, 0x20);
+	/* enable mailbox interface */
+	u16tmp = btcoexist->btc_read_2byte(btcoexist, 0x40);
+	u16tmp |= BIT(9);
+	btcoexist->btc_write_2byte(btcoexist, 0x40, u16tmp);
+
+	/* enable PTA I2C mailbox */
+	u8tmp = btcoexist->btc_read_1byte(btcoexist, 0x101);
+	u8tmp |= BIT(4);
+	btcoexist->btc_write_1byte(btcoexist, 0x101, u8tmp);
+
+	/* enable bt clock when wifi is disabled. */
+	u8tmp = btcoexist->btc_read_1byte(btcoexist, 0x93);
+	u8tmp |= BIT(0);
+	btcoexist->btc_write_1byte(btcoexist, 0x93, u8tmp);
+	/* enable bt clock when suspend. */
+	u8tmp = btcoexist->btc_read_1byte(btcoexist, 0x7);
+	u8tmp |= BIT(0);
+	btcoexist->btc_write_1byte(btcoexist, 0x7, u8tmp);
+
+	/* Give bt_coex_supported_version the default value */
+	coex_sta->bt_coex_supported_version = 0;
+}
+
+/* ************************************************************
+ * work around function start with wa_halbtc8192e2ant_
+ * ************************************************************
+ * ************************************************************
+ * extern function start with ex_halbtc8192e2ant_
+ * ************************************************************ */
+void ex_halbtc8192e2ant_power_on_setting(IN struct btc_coexist *btcoexist)
+{
+}
+
+void ex_halbtc8192e2ant_init_hw_config(IN struct btc_coexist *btcoexist,
+				       IN boolean wifi_only)
+{
+	halbtc8192e2ant_init_hw_config(btcoexist, true);
+}
+
+void ex_halbtc8192e2ant_init_coex_dm(IN struct btc_coexist *btcoexist)
+{
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+		    "[BTCoex], Coex Mechanism Init!!\n");
+	BTC_TRACE(trace_buf);
+
+	halbtc8192e2ant_init_coex_dm(btcoexist);
+}
+
+void ex_halbtc8192e2ant_display_coex_info(IN struct btc_coexist *btcoexist)
+{
+	struct  btc_board_info		*board_info = &btcoexist->board_info;
+	struct  btc_stack_info		*stack_info = &btcoexist->stack_info;
+	u8				*cli_buf = btcoexist->cli_buf;
+	u8				u8tmp[4], i, bt_info_ext, ps_tdma_case = 0;
+	u16				u16tmp[4];
+	u32				u32tmp[4];
+	u32				fa_ofdm, fa_cck, cca_ofdm, cca_cck;
+	u32				fw_ver = 0, bt_patch_ver = 0, bt_coex_ver = 0;
+	u32				phyver = 0;
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+		   "\r\n ============[BT Coexist info]============");
+	CL_PRINTF(cli_buf);
+
+	if (btcoexist->manual_control) {
+		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+			"\r\n ============[Under Manual Control]============");
+		CL_PRINTF(cli_buf);
+		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+			   "\r\n ==========================================");
+		CL_PRINTF(cli_buf);
+	}
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d ",
+		   "Ant PG number/ Ant mechanism:",
+		   board_info->pg_ant_num, board_info->btdm_ant_num);
+	CL_PRINTF(cli_buf);
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d", "Antenna type:",
+		   board_info->ant_type);
+	CL_PRINTF(cli_buf);
+
+	btcoexist->btc_get(btcoexist, BTC_GET_U4_BT_PATCH_VER, &bt_patch_ver);
+	btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_FW_VER, &fw_ver);
+	phyver = btcoexist->btc_get_bt_phydm_version(btcoexist);
+	bt_coex_ver = ((coex_sta->bt_coex_supported_version & 0xff00) >> 8);
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+		   "\r\n %-35s = %d_%02x/ 0x%02x/ 0x%02x (%s)",
+		   "CoexVer WL/  BT_Desired/ BT_Report",
+		   glcoex_ver_date_8192e_2ant, glcoex_ver_8192e_2ant,
+		   glcoex_ver_btdesired_8192e_2ant, bt_coex_ver,
+		   (bt_coex_ver == 0xff ? "Unknown" : (bt_coex_ver >=
+				   glcoex_ver_btdesired_8192e_2ant ? "Match" :
+				   "Mis-Match")));
+	CL_PRINTF(cli_buf);
+
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+		   "\r\n %-35s = 0x%x/ 0x%x/ v%d",
+		   "W_FW/ B_FW/ Phy", fw_ver, bt_patch_ver, phyver);
+	CL_PRINTF(cli_buf);
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %02x %02x %02x ",
+		   "Wifi channel informed to BT",
+		   coex_dm->wifi_chnl_info[0], coex_dm->wifi_chnl_info[1],
+		   coex_dm->wifi_chnl_info[2]);
+	CL_PRINTF(cli_buf);
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s/", "WifibHiPri",
+		(coex_sta->wifi_is_high_pri_task ? "Yes" : "No"));
+	CL_PRINTF(cli_buf);
+
+#if 0
+		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s/", "test patch version",
+			"20161003_v3");
+		CL_PRINTF(cli_buf);
+#endif
+
+	/* wifi status */
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s",
+		   "============[Wifi Status]============");
+	CL_PRINTF(cli_buf);
+	btcoexist->btc_disp_dbg_msg(btcoexist, BTC_DBG_DISP_WIFI_STATUS);
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s",
+		   "============[BT Status]============");
+	CL_PRINTF(cli_buf);
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = [%s/ %d/ %d] ",
+		   "BT [status/ rssi/ retryCnt]",
+		   ((coex_sta->bt_disabled) ? ("disabled") :	((
+		   coex_sta->c2h_bt_inquiry_page) ? ("inquiry/page scan")
+			   : ((BT_8192E_2ANT_BT_STATUS_NON_CONNECTED_IDLE ==
+			       coex_dm->bt_status) ? "non-connected idle" :
+		((BT_8192E_2ANT_BT_STATUS_CONNECTED_IDLE == coex_dm->bt_status)
+				       ? "connected-idle" : "busy")))),
+		   coex_sta->bt_rssi, coex_sta->bt_retry_cnt);
+	CL_PRINTF(cli_buf);
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d / %d / %d / %d",
+		   "SCO/HID/PAN/A2DP",
+		   stack_info->sco_exist, stack_info->hid_exist,
+		   stack_info->pan_exist, stack_info->a2dp_exist);
+	CL_PRINTF(cli_buf);
+	btcoexist->btc_disp_dbg_msg(btcoexist, BTC_DBG_DISP_BT_LINK_INFO);
+
+	bt_info_ext = coex_sta->bt_info_ext;
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s",
+		   "BT Info A2DP rate",
+		   (bt_info_ext & BIT(0)) ? "Basic rate" : "EDR rate");
+	CL_PRINTF(cli_buf);
+
+	for (i = 0; i < BT_INFO_SRC_8192E_2ANT_MAX; i++) {
+		if (coex_sta->bt_info_c2h_cnt[i]) {
+			CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+				"\r\n %-35s = %02x %02x %02x %02x %02x %02x %02x(%d)",
+				   glbt_info_src_8192e_2ant[i],
+				   coex_sta->bt_info_c2h[i][0],
+				   coex_sta->bt_info_c2h[i][1],
+				   coex_sta->bt_info_c2h[i][2],
+				   coex_sta->bt_info_c2h[i][3],
+				   coex_sta->bt_info_c2h[i][4],
+				   coex_sta->bt_info_c2h[i][5],
+				   coex_sta->bt_info_c2h[i][6],
+				   coex_sta->bt_info_c2h_cnt[i]);
+			CL_PRINTF(cli_buf);
+		}
+	}
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x ", "SS Type",
+		   coex_dm->cur_ss_type);
+	CL_PRINTF(cli_buf);
+
+	/* Sw mechanism	 */
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s",
+		   "============[Sw mechanism]============");
+	CL_PRINTF(cli_buf);
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d ",
+		   "SM1[ShRf/ LpRA/ LimDig]",
+		   coex_dm->cur_rf_rx_lpf_shrink, coex_dm->cur_low_penalty_ra,
+		   coex_dm->limited_dig);
+	CL_PRINTF(cli_buf);
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d(0x%x) ",
+		   "SM2[AgcT/ AdcB/ SwDacSwing(lvl)]",
+		   coex_dm->cur_agc_table_en, coex_dm->cur_adc_back_off,
+		   coex_dm->cur_dac_swing_on, coex_dm->cur_dac_swing_lvl);
+	CL_PRINTF(cli_buf);
+
+	/* Fw mechanism		 */
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s",
+		   "============[Fw mechanism]============");
+	CL_PRINTF(cli_buf);
+
+	ps_tdma_case = coex_dm->cur_ps_tdma;
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+		   "\r\n %-35s = %02x %02x %02x %02x %02x case-%d (auto:%d)",
+		   "PS TDMA",
+		   coex_dm->ps_tdma_para[0], coex_dm->ps_tdma_para[1],
+		   coex_dm->ps_tdma_para[2], coex_dm->ps_tdma_para[3],
+		   coex_dm->ps_tdma_para[4], ps_tdma_case,
+		   coex_dm->auto_tdma_adjust);
+	CL_PRINTF(cli_buf);
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d ",
+		   "DecBtPwr/ IgnWlanAct",
+		   coex_dm->cur_bt_dec_pwr_lvl, coex_dm->cur_ignore_wlan_act);
+	CL_PRINTF(cli_buf);
+
+	/* Hw setting		 */
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s",
+		   "============[Hw setting]============");
+	CL_PRINTF(cli_buf);
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x",
+		   "RF-A, 0x1e initVal",
+		   coex_dm->bt_rf_0x1e_backup);
+	CL_PRINTF(cli_buf);
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/0x%x/0x%x/0x%x",
+		   "backup ARFR1/ARFR2/RL/AMaxTime",
+		   coex_dm->backup_arfr_cnt1, coex_dm->backup_arfr_cnt2,
+		   coex_dm->backup_retry_limit,
+		   coex_dm->backup_ampdu_max_time);
+	CL_PRINTF(cli_buf);
+
+	u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x430);
+	u32tmp[1] = btcoexist->btc_read_4byte(btcoexist, 0x434);
+	u16tmp[0] = btcoexist->btc_read_2byte(btcoexist, 0x42a);
+	u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x456);
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/0x%x/0x%x/0x%x",
+		   "0x430/0x434/0x42a/0x456",
+		   u32tmp[0], u32tmp[1], u16tmp[0], u8tmp[0]);
+	CL_PRINTF(cli_buf);
+
+	u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0xc04);
+	u32tmp[1] = btcoexist->btc_read_4byte(btcoexist, 0xd04);
+	u32tmp[2] = btcoexist->btc_read_4byte(btcoexist, 0x90c);
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x/ 0x%x",
+		   "0xc04/ 0xd04/ 0x90c",
+		   u32tmp[0], u32tmp[1], u32tmp[2]);
+	CL_PRINTF(cli_buf);
+
+	u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x778);
+	u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x880);
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x", "0x778/0x880[29:25]",
+		u8tmp[0], (u32tmp[0] & 0x3e000000) >> 25);
+	CL_PRINTF(cli_buf);
+
+	u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x92c);
+	u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x930);
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x",
+		   "0x92c/ 0x930",
+		   (u8tmp[0]), u32tmp[0]);
+	CL_PRINTF(cli_buf);
+
+	u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x40);
+	u8tmp[1] = btcoexist->btc_read_1byte(btcoexist, 0x4f);
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x",
+		   "0x40/ 0x4f",
+		   u8tmp[0], u8tmp[1]);
+	CL_PRINTF(cli_buf);
+
+	u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x550);
+	u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x522);
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x",
+		   "0x550(bcn ctrl)/0x522",
+		   u32tmp[0], u8tmp[0]);
+	CL_PRINTF(cli_buf);
+
+	u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0xc50);
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x", "0xc50(dig)",
+		   u32tmp[0]);
+	CL_PRINTF(cli_buf);
+
+	fa_ofdm = btcoexist->btc_phydm_query_PHY_counter(btcoexist,
+			PHYDM_INFO_FA_OFDM);
+	fa_cck = btcoexist->btc_phydm_query_PHY_counter(btcoexist,
+			PHYDM_INFO_FA_CCK);
+	cca_ofdm = btcoexist->btc_phydm_query_PHY_counter(btcoexist,
+			PHYDM_INFO_CCA_OFDM);
+	cca_cck = btcoexist->btc_phydm_query_PHY_counter(btcoexist,
+			PHYDM_INFO_CCA_CCK);
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+		   "\r\n %-35s = 0x%x/ 0x%x/ 0x%x/ 0x%x",
+		   "CCK-CCA/CCK-FA/OFDM-CCA/OFDM-FA",
+		   cca_cck, fa_cck, cca_ofdm, fa_ofdm);
+	CL_PRINTF(cli_buf);
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d/ %d",
+		   "CRC_OK CCK/11g/11n/11n-agg",
+		   coex_sta->crc_ok_cck, coex_sta->crc_ok_11g,
+		   coex_sta->crc_ok_11n, coex_sta->crc_ok_11n_vht);
+	CL_PRINTF(cli_buf);
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d/ %d",
+		   "CRC_Err CCK/11g/11n/11n-agg",
+		   coex_sta->crc_err_cck, coex_sta->crc_err_11g,
+		   coex_sta->crc_err_11n, coex_sta->crc_err_11n_vht);
+	CL_PRINTF(cli_buf);
+
+	u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x6c0);
+	u32tmp[1] = btcoexist->btc_read_4byte(btcoexist, 0x6c4);
+	u32tmp[2] = btcoexist->btc_read_4byte(btcoexist, 0x6c8);
+	u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x6cc);
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+		   "\r\n %-35s = 0x%x/ 0x%x/ 0x%x/ 0x%x",
+		   "0x6c0/0x6c4/0x6c8/0x6cc(coexTable)",
+		   u32tmp[0], u32tmp[1], u32tmp[2], u8tmp[0]);
+	CL_PRINTF(cli_buf);
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d",
+		   "0x770(hp rx[31:16]/tx[15:0])",
+		   coex_sta->high_priority_rx, coex_sta->high_priority_tx);
+	CL_PRINTF(cli_buf);
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d",
+		   "0x774(lp rx[31:16]/tx[15:0])",
+		   coex_sta->low_priority_rx, coex_sta->low_priority_tx);
+	CL_PRINTF(cli_buf);
+#if (BT_AUTO_REPORT_ONLY_8192E_2ANT == 1)
+	halbtc8192e2ant_monitor_bt_ctr(btcoexist);
+#endif
+	btcoexist->btc_disp_dbg_msg(btcoexist, BTC_DBG_DISP_COEX_STATISTICS);
+}
+
+
+void ex_halbtc8192e2ant_ips_notify(IN struct btc_coexist *btcoexist, IN u8 type)
+{
+	if (BTC_IPS_ENTER == type) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], IPS ENTER notify\n");
+		BTC_TRACE(trace_buf);
+		coex_sta->under_ips = true;
+		halbtc8192e2ant_coex_all_off(btcoexist);
+		halbtc8192e2ant_set_ant_path(btcoexist, BTC_ANT_PATH_BT, false, true);
+		halbtc8192e2ant_ignore_wlan_act(btcoexist, FORCE_EXEC, true);
+	} else if (BTC_IPS_LEAVE == type) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], IPS LEAVE notify\n");
+		BTC_TRACE(trace_buf);
+		coex_sta->under_ips = false;
+		halbtc8192e2ant_init_hw_config(btcoexist, false);
+		halbtc8192e2ant_init_coex_dm(btcoexist);
+	}
+}
+
+void ex_halbtc8192e2ant_lps_notify(IN struct btc_coexist *btcoexist, IN u8 type)
+{
+	if (BTC_LPS_ENABLE == type) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], LPS ENABLE notify\n");
+		BTC_TRACE(trace_buf);
+		coex_sta->under_lps = true;
+
+	} else if (BTC_LPS_DISABLE == type) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], LPS DISABLE notify\n");
+		BTC_TRACE(trace_buf);
+		coex_sta->under_lps = false;
+	}
+}
+
+void ex_halbtc8192e2ant_scan_notify(IN struct btc_coexist *btcoexist,
+				    IN u8 type)
+{
+	if (BTC_SCAN_START == type) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], SCAN START notify\n");
+		BTC_TRACE(trace_buf);
+	} else if (BTC_SCAN_FINISH == type) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], SCAN FINISH notify\n");
+		BTC_TRACE(trace_buf);
+		btcoexist->btc_get(btcoexist, BTC_GET_U1_AP_NUM,
+				   &coex_sta->scan_ap_num);
+
+	}
+}
+
+void ex_halbtc8192e2ant_connect_notify(IN struct btc_coexist *btcoexist,
+				       IN u8 type)
+{
+	if (BTC_ASSOCIATE_START == type) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], CONNECT START notify\n");
+		BTC_TRACE(trace_buf);
+		coex_sta->wifi_is_high_pri_task = true;
+		coex_sta->cnt_wifi_high_pri = 2;
+		halbtc8192e2ant_ignore_wlan_act(btcoexist, FORCE_EXEC, false);
+		halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 32);
+		halbtc8192e2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 11);
+		halbtc8192e2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);
+	} else if (BTC_ASSOCIATE_FINISH == type) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], CONNECT FINISH notify\n");
+		BTC_TRACE(trace_buf);
+		coex_sta->wifi_is_high_pri_task = false;
+		halbtc8192e2ant_run_coexist_mechanism(btcoexist);
+	}
+}
+
+void ex_halbtc8192e2ant_media_status_notify(IN struct btc_coexist *btcoexist,
+		IN u8 type)
+{
+	u8			h2c_parameter[3] = {0};
+	u32			wifi_bw;
+	u8			wifi_central_chnl;
+
+	if (btcoexist->manual_control ||
+	    btcoexist->stop_coex_dm ||
+	    coex_sta->bt_disabled)
+		return;
+
+	if (BTC_MEDIA_CONNECT == type) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], MEDIA connect notify\n");
+		BTC_TRACE(trace_buf);
+	} else {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], MEDIA disconnect notify\n");
+		BTC_TRACE(trace_buf);
+	}
+
+	/* only 2.4G we need to inform bt the chnl mask */
+	btcoexist->btc_get(btcoexist, BTC_GET_U1_WIFI_CENTRAL_CHNL,
+			   &wifi_central_chnl);
+	if ((BTC_MEDIA_CONNECT == type) &&
+	    (wifi_central_chnl <= 14)) {
+		h2c_parameter[0] = 0x1;
+		h2c_parameter[1] = wifi_central_chnl;
+		btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw);
+		if (BTC_WIFI_BW_HT40 == wifi_bw)
+			h2c_parameter[2] = 0x30;
+		else
+			h2c_parameter[2] = 0x20;
+	}
+
+	coex_dm->wifi_chnl_info[0] = h2c_parameter[0];
+	coex_dm->wifi_chnl_info[1] = h2c_parameter[1];
+	coex_dm->wifi_chnl_info[2] = h2c_parameter[2];
+
+	btcoexist->btc_fill_h2c(btcoexist, 0x66, 3, h2c_parameter);
+}
+
+void ex_halbtc8192e2ant_specific_packet_notify(IN struct btc_coexist *btcoexist,
+		IN u8 type)
+{
+	if (type == BTC_PACKET_DHCP) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], DHCP Packet notify\n");
+		BTC_TRACE(trace_buf);
+	}
+}
+
+void ex_halbtc8192e2ant_bt_info_notify(IN struct btc_coexist *btcoexist,
+				       IN u8 *tmp_buf, IN u8 length)
+{
+	u8			bt_info = 0;
+	u8			i, rsp_source = 0;
+	boolean			bt_busy = false, limited_dig = false;
+	boolean			wifi_connected = false;
+	static u8		bt_info_for_wifi_fw_count = 0;
+
+	coex_sta->c2h_bt_info_req_sent = false;
+
+	rsp_source = tmp_buf[0] & 0xf;
+	if (rsp_source >= BT_INFO_SRC_8192E_2ANT_MAX)
+		rsp_source = BT_INFO_SRC_8192E_2ANT_WIFI_FW;
+	coex_sta->bt_info_c2h_cnt[rsp_source]++;
+
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+		    "[BTCoex], Bt info[%d], length=%d, hex data=[", rsp_source,
+		    length);
+	BTC_TRACE(trace_buf);
+
+	/*avoid mailbox issue*/
+	if (rsp_source == BT_INFO_SRC_8192E_2ANT_WIFI_FW) {
+		bt_info_for_wifi_fw_count++;
+		if (bt_info_for_wifi_fw_count < 5)
+			return;
+	} else
+		bt_info_for_wifi_fw_count = 0;
+
+	for (i = 0; i < length; i++) {
+		coex_sta->bt_info_c2h[rsp_source][i] = tmp_buf[i];
+		if (i == 1)
+			bt_info = tmp_buf[i];
+		if (i == length - 1) {
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "0x%02x]\n",
+				    tmp_buf[i]);
+			BTC_TRACE(trace_buf);
+		} else {
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "0x%02x, ",
+				    tmp_buf[i]);
+			BTC_TRACE(trace_buf);
+		}
+	}
+
+	if (BT_INFO_SRC_8192E_2ANT_WIFI_FW != rsp_source) {
+		coex_sta->bt_retry_cnt =	/* [3:0] */
+			coex_sta->bt_info_c2h[rsp_source][2] & 0xf;
+
+		coex_sta->bt_rssi =
+			coex_sta->bt_info_c2h[rsp_source][3] * 2 + 10;
+
+		coex_sta->bt_info_ext =
+			coex_sta->bt_info_c2h[rsp_source][4];
+
+		/* Here we need to resend some wifi info to BT */
+		/* because bt is reset and loss of the info. */
+		if ((coex_sta->bt_info_ext & BIT(1))) {
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				"[BTCoex], BT ext info bit1 check, send wifi BW&Chnl to BT!!\n");
+			BTC_TRACE(trace_buf);
+			btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED,
+					   &wifi_connected);
+			if (wifi_connected)
+				ex_halbtc8192e2ant_media_status_notify(
+					btcoexist, BTC_MEDIA_CONNECT);
+			else
+				ex_halbtc8192e2ant_media_status_notify(
+					btcoexist, BTC_MEDIA_DISCONNECT);
+		}
+
+		if (coex_sta->bt_info_ext & BIT(2)) {
+			coex_sta->cnt_setup_link++;
+			coex_sta->is_setup_link = true;
+
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				    "[BTCoex], Re-Link start in BT info!!\n");
+			BTC_TRACE(trace_buf);
+		} else
+			coex_sta->is_setup_link = false;
+
+		if ((coex_sta->bt_info_ext & BIT(3))) {
+			if (!btcoexist->manual_control &&
+			    !btcoexist->stop_coex_dm) {
+				BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+					"[BTCoex], BT ext info bit3 check, set BT NOT to ignore Wlan active!!\n");
+				BTC_TRACE(trace_buf);
+				halbtc8192e2ant_ignore_wlan_act(btcoexist,
+							FORCE_EXEC, false);
+			}
+		} else {
+			/* BT already NOT ignore Wlan active, do nothing here. */
+		}
+
+#if (BT_AUTO_REPORT_ONLY_8192E_2ANT == 0)
+		if ((coex_sta->bt_info_ext & BIT(4))) {
+			/* BT auto report already enabled, do nothing */
+		} else
+			halbtc8192e2ant_bt_auto_report(btcoexist, FORCE_EXEC,
+						       true);
+#endif
+	}
+
+	/* check BIT2 first ==> check if bt is under inquiry or page scan */
+	if (bt_info & BT_INFO_8192E_2ANT_B_INQ_PAGE)
+		coex_sta->c2h_bt_inquiry_page = true;
+	else
+		coex_sta->c2h_bt_inquiry_page = false;
+
+	/* set link exist status */
+	if (!(bt_info & BT_INFO_8192E_2ANT_B_CONNECTION)) {
+		coex_sta->bt_link_exist = false;
+		coex_sta->pan_exist = false;
+		coex_sta->a2dp_exist = false;
+		coex_sta->hid_exist = false;
+		coex_sta->sco_exist = false;
+	} else {	/* connection exists */
+		coex_sta->bt_link_exist = true;
+		if (bt_info & BT_INFO_8192E_2ANT_B_FTP)
+			coex_sta->pan_exist = true;
+		else
+			coex_sta->pan_exist = false;
+		if (bt_info & BT_INFO_8192E_2ANT_B_A2DP)
+			coex_sta->a2dp_exist = true;
+		else
+			coex_sta->a2dp_exist = false;
+		if (bt_info & BT_INFO_8192E_2ANT_B_HID)
+			coex_sta->hid_exist = true;
+		else
+			coex_sta->hid_exist = false;
+		if (bt_info & BT_INFO_8192E_2ANT_B_SCO_ESCO)
+			coex_sta->sco_exist = true;
+		else
+			coex_sta->sco_exist = false;
+	}
+
+	halbtc8192e2ant_update_bt_link_info(btcoexist);
+
+	if (!(bt_info & BT_INFO_8192E_2ANT_B_CONNECTION)) {
+		coex_dm->bt_status = BT_8192E_2ANT_BT_STATUS_NON_CONNECTED_IDLE;
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			"[BTCoex], BtInfoNotify(), BT Non-Connected idle!!!\n");
+		BTC_TRACE(trace_buf);
+	} else if (bt_info ==
+		BT_INFO_8192E_2ANT_B_CONNECTION) {	/* connection exists but no busy */
+		coex_dm->bt_status = BT_8192E_2ANT_BT_STATUS_CONNECTED_IDLE;
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], BtInfoNotify(), BT Connected-idle!!!\n");
+		BTC_TRACE(trace_buf);
+	} else if ((bt_info & BT_INFO_8192E_2ANT_B_SCO_ESCO) ||
+		   (bt_info & BT_INFO_8192E_2ANT_B_SCO_BUSY)) {
+		coex_dm->bt_status = BT_8192E_2ANT_BT_STATUS_SCO_BUSY;
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], BtInfoNotify(), BT SCO busy!!!\n");
+		BTC_TRACE(trace_buf);
+	} else if (bt_info & BT_INFO_8192E_2ANT_B_ACL_BUSY) {
+		coex_dm->bt_status = BT_8192E_2ANT_BT_STATUS_ACL_BUSY;
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], BtInfoNotify(), BT ACL busy!!!\n");
+		BTC_TRACE(trace_buf);
+	} else {
+		coex_dm->bt_status = BT_8192E_2ANT_BT_STATUS_MAX;
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			"[BTCoex], BtInfoNotify(), BT Non-Defined state!!!\n");
+		BTC_TRACE(trace_buf);
+	}
+
+	if ((BT_8192E_2ANT_BT_STATUS_ACL_BUSY == coex_dm->bt_status) ||
+	    (BT_8192E_2ANT_BT_STATUS_SCO_BUSY == coex_dm->bt_status) ||
+	    (BT_8192E_2ANT_BT_STATUS_ACL_SCO_BUSY == coex_dm->bt_status)) {
+		bt_busy = true;
+		limited_dig = true;
+	} else {
+		bt_busy = false;
+		limited_dig = false;
+	}
+
+	btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_TRAFFIC_BUSY, &bt_busy);
+
+	coex_dm->limited_dig = limited_dig;
+	btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_LIMITED_DIG, &limited_dig);
+
+	halbtc8192e2ant_run_coexist_mechanism(btcoexist);
+}
+
+void ex_halbtc8192e2ant_halt_notify(IN struct btc_coexist *btcoexist)
+{
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], Halt notify\n");
+	BTC_TRACE(trace_buf);
+
+	halbtc8192e2ant_set_ant_path(btcoexist, BTC_ANT_PATH_BT, false, true);
+	halbtc8192e2ant_ignore_wlan_act(btcoexist, FORCE_EXEC, true);
+	ex_halbtc8192e2ant_media_status_notify(btcoexist, BTC_MEDIA_DISCONNECT);
+}
+
+void ex_halbtc8192e2ant_periodical(IN struct btc_coexist *btcoexist)
+{
+	boolean			wifi_connected = false;
+	static u8			count = 0;
+	static boolean		pre_wifi_connected = false;
+
+	if ((coex_sta->bt_coex_supported_version == 0) ||
+	    (coex_sta->bt_coex_supported_version == 0xffff))
+		coex_sta->bt_coex_supported_version =
+			btcoexist->btc_get_bt_coex_supported_version(btcoexist);
+
+
+/*If wifi is connecting, the update of wifi channel mask may fail caused by wifi FW*/
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, &wifi_connected);
+
+	if (pre_wifi_connected != wifi_connected)
+		count = 0;
+
+	if  (count < 10)
+		count++;
+
+	if (count == 2) {
+		if (wifi_connected)
+			ex_halbtc8192e2ant_media_status_notify(btcoexist, BTC_MEDIA_CONNECT);
+		else
+			ex_halbtc8192e2ant_media_status_notify(btcoexist, BTC_MEDIA_DISCONNECT);
+	}
+
+	pre_wifi_connected = wifi_connected;
+/*If wifi is connecting, the update of wifi channel mask may fail caused by wifi FW*/
+
+
+#if (BT_AUTO_REPORT_ONLY_8192E_2ANT == 0)
+	halbtc8192e2ant_query_bt_info(btcoexist);
+	halbtc8192e2ant_monitor_bt_ctr(btcoexist);
+	halbtc8192e2ant_monitor_wifi_ctr(btcoexist);
+	halbtc8192e2ant_monitor_bt_enable_disable(btcoexist);
+#else
+	halbtc8192e2ant_monitor_wifi_ctr(btcoexist);
+
+	if (halbtc8192e2ant_is_wifi_status_changed(btcoexist) ||
+	    coex_dm->auto_tdma_adjust)
+		halbtc8192e2ant_run_coexist_mechanism(btcoexist);
+#endif
+}
+
+#endif
+
+#endif	/* #if (BT_SUPPORT == 1 && COEX_SUPPORT == 1) */
+
+
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/btc/halbtc8192e2ant.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/btc/halbtc8192e2ant.h
--- linux-5.6.3/3rdparty/rtl8821ce/hal/btc/halbtc8192e2ant.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/btc/halbtc8192e2ant.h	2020-04-10 16:35:06.781658433 +0300
@@ -0,0 +1,216 @@
+
+#if (BT_SUPPORT == 1 && COEX_SUPPORT == 1)
+
+#if (RTL8192E_SUPPORT == 1)
+/* *******************************************
+ * The following is for 8192E 2Ant BT Co-exist definition
+ * ******************************************* */
+#define	BT_AUTO_REPORT_ONLY_8192E_2ANT				0
+
+#define	BT_INFO_8192E_2ANT_B_FTP						BIT(7)
+#define	BT_INFO_8192E_2ANT_B_A2DP					BIT(6)
+#define	BT_INFO_8192E_2ANT_B_HID						BIT(5)
+#define	BT_INFO_8192E_2ANT_B_SCO_BUSY				BIT(4)
+#define	BT_INFO_8192E_2ANT_B_ACL_BUSY				BIT(3)
+#define	BT_INFO_8192E_2ANT_B_INQ_PAGE				BIT(2)
+#define	BT_INFO_8192E_2ANT_B_SCO_ESCO				BIT(1)
+#define	BT_INFO_8192E_2ANT_B_CONNECTION				BIT(0)
+
+#define		BTC_RSSI_COEX_THRESH_TOL_8192E_2ANT		2
+#define	NOISY_AP_NUM_THRESH_8192E				10
+
+enum bt_info_src_8192e_2ant {
+	BT_INFO_SRC_8192E_2ANT_WIFI_FW			= 0x0,
+	BT_INFO_SRC_8192E_2ANT_BT_RSP				= 0x1,
+	BT_INFO_SRC_8192E_2ANT_BT_ACTIVE_SEND		= 0x2,
+	BT_INFO_SRC_8192E_2ANT_MAX
+};
+
+enum bt_8192e_2ant_bt_status {
+	BT_8192E_2ANT_BT_STATUS_NON_CONNECTED_IDLE	= 0x0,
+	BT_8192E_2ANT_BT_STATUS_CONNECTED_IDLE		= 0x1,
+	BT_8192E_2ANT_BT_STATUS_INQ_PAGE				= 0x2,
+	BT_8192E_2ANT_BT_STATUS_ACL_BUSY				= 0x3,
+	BT_8192E_2ANT_BT_STATUS_SCO_BUSY				= 0x4,
+	BT_8192E_2ANT_BT_STATUS_ACL_SCO_BUSY			= 0x5,
+	BT_8192E_2ANT_BT_STATUS_MAX
+};
+
+enum bt_8192e_2ant_coex_algo {
+	BT_8192E_2ANT_COEX_ALGO_UNDEFINED		= 0x0,
+	BT_8192E_2ANT_COEX_ALGO_SCO				= 0x1,
+	BT_8192E_2ANT_COEX_ALGO_SCO_PAN			= 0x2,
+	BT_8192E_2ANT_COEX_ALGO_HID				= 0x3,
+	BT_8192E_2ANT_COEX_ALGO_A2DP			= 0x4,
+	BT_8192E_2ANT_COEX_ALGO_A2DP_PANHS		= 0x5,
+	BT_8192E_2ANT_COEX_ALGO_PANEDR			= 0x6,
+	BT_8192E_2ANT_COEX_ALGO_PANHS			= 0x7,
+	BT_8192E_2ANT_COEX_ALGO_PANEDR_A2DP		= 0x8,
+	BT_8192E_2ANT_COEX_ALGO_PANEDR_HID		= 0x9,
+	BT_8192E_2ANT_COEX_ALGO_HID_A2DP_PANEDR	= 0xa,
+	BT_8192E_2ANT_COEX_ALGO_HID_A2DP		= 0xb,
+	BT_8192E_2ANT_COEX_ALGO_MAX				= 0xc
+};
+
+struct coex_dm_8192e_2ant {
+	/* fw mechanism */
+	u8		pre_bt_dec_pwr_lvl;
+	u8		cur_bt_dec_pwr_lvl;
+	u8		pre_fw_dac_swing_lvl;
+	u8		cur_fw_dac_swing_lvl;
+	boolean		cur_ignore_wlan_act;
+	boolean		pre_ignore_wlan_act;
+	u8		pre_ps_tdma;
+	u8		cur_ps_tdma;
+	u8		ps_tdma_para[5];
+	u8		ps_tdma_du_adj_type;
+	boolean		reset_tdma_adjust;
+	boolean		auto_tdma_adjust;
+	boolean		auto_tdma_adjust_low_rssi;
+	boolean		pre_ps_tdma_on;
+	boolean		cur_ps_tdma_on;
+	boolean		pre_bt_auto_report;
+	boolean		cur_bt_auto_report;
+
+	/* sw mechanism */
+	boolean		pre_rf_rx_lpf_shrink;
+	boolean		cur_rf_rx_lpf_shrink;
+	u32		bt_rf_0x1e_backup;
+	boolean	pre_low_penalty_ra;
+	boolean		cur_low_penalty_ra;
+	boolean		pre_dac_swing_on;
+	u32		pre_dac_swing_lvl;
+	boolean		cur_dac_swing_on;
+	u32		cur_dac_swing_lvl;
+	boolean		pre_adc_back_off;
+	boolean		cur_adc_back_off;
+	boolean	pre_agc_table_en;
+	boolean		cur_agc_table_en;
+	u32		pre_val0x6c0;
+	u32		cur_val0x6c0;
+	u32		pre_val0x6c4;
+	u32		cur_val0x6c4;
+	u32		pre_val0x6c8;
+	u32		cur_val0x6c8;
+	u8		pre_val0x6cc;
+	u8		cur_val0x6cc;
+	boolean		limited_dig;
+
+	u32		backup_arfr_cnt1;	/* Auto Rate Fallback Retry cnt */
+	u32		backup_arfr_cnt2;	/* Auto Rate Fallback Retry cnt */
+	u16		backup_retry_limit;
+	u8		backup_ampdu_max_time;
+
+	/* algorithm related */
+	u8		pre_algorithm;
+	u8		cur_algorithm;
+	u8		bt_status;
+	u8		wifi_chnl_info[3];
+
+	u8		pre_ss_type;
+	u8		cur_ss_type;
+
+	u8		pre_lps;
+	u8		cur_lps;
+	u8		pre_rpwm;
+	u8		cur_rpwm;
+
+
+	u32		pre_ra_mask;
+	u32		cur_ra_mask;
+	u8		cur_ra_mask_type;
+	u8		pre_arfr_type;
+	u8		cur_arfr_type;
+	u8		pre_retry_limit_type;
+	u8		cur_retry_limit_type;
+	u8		pre_ampdu_time_type;
+	u8		cur_ampdu_time_type;
+};
+
+struct coex_sta_8192e_2ant {
+	boolean					bt_disabled;
+	boolean					bt_link_exist;
+	boolean					sco_exist;
+	boolean					a2dp_exist;
+	boolean					hid_exist;
+	boolean					pan_exist;
+	boolean					force_lps_on;
+
+	boolean					under_lps;
+	boolean					under_ips;
+	u32					high_priority_tx;
+	u32					high_priority_rx;
+	u32					low_priority_tx;
+	u32					low_priority_rx;
+	u8					bt_rssi;
+	u8					pre_bt_rssi_state;
+	u8					pre_wifi_rssi_state[4];
+	boolean					c2h_bt_info_req_sent;
+	u8					bt_info_c2h[BT_INFO_SRC_8192E_2ANT_MAX][10];
+	u32					bt_info_c2h_cnt[BT_INFO_SRC_8192E_2ANT_MAX];
+	boolean					c2h_bt_inquiry_page;
+	u8					bt_retry_cnt;
+	u8					bt_info_ext;
+	u8					scan_ap_num;
+	u32				bt_coex_supported_version;
+	u32					cnt_setup_link;
+	u32					cnt_wifi_high_pri;
+	boolean				is_setup_link;
+	boolean				wifi_is_high_pri_task;
+
+	u32				crc_ok_cck;
+	u32				crc_ok_11g;
+	u32				crc_ok_11n;
+	u32				crc_ok_11n_vht;
+
+	u32				crc_err_cck;
+	u32				crc_err_11g;
+	u32				crc_err_11n;
+	u32				crc_err_11n_vht;
+};
+
+/* *******************************************
+ * The following is interface which will notify coex module.
+ * ******************************************* */
+void ex_halbtc8192e2ant_power_on_setting(IN struct btc_coexist *btcoexist);
+void ex_halbtc8192e2ant_init_hw_config(IN struct btc_coexist *btcoexist,
+				       IN boolean wifi_only);
+void ex_halbtc8192e2ant_init_coex_dm(IN struct btc_coexist *btcoexist);
+void ex_halbtc8192e2ant_ips_notify(IN struct btc_coexist *btcoexist,
+				   IN u8 type);
+void ex_halbtc8192e2ant_lps_notify(IN struct btc_coexist *btcoexist,
+				   IN u8 type);
+void ex_halbtc8192e2ant_scan_notify(IN struct btc_coexist *btcoexist,
+				    IN u8 type);
+void ex_halbtc8192e2ant_connect_notify(IN struct btc_coexist *btcoexist,
+				       IN u8 type);
+void ex_halbtc8192e2ant_media_status_notify(IN struct btc_coexist *btcoexist,
+		IN u8 type);
+void ex_halbtc8192e2ant_specific_packet_notify(IN struct btc_coexist *btcoexist,
+		IN u8 type);
+void ex_halbtc8192e2ant_bt_info_notify(IN struct btc_coexist *btcoexist,
+				       IN u8 *tmp_buf, IN u8 length);
+void ex_halbtc8192e2ant_halt_notify(IN struct btc_coexist *btcoexist);
+void ex_halbtc8192e2ant_periodical(IN struct btc_coexist *btcoexist);
+void ex_halbtc8192e2ant_display_coex_info(IN struct btc_coexist *btcoexist);
+
+#else	/*  #if (RTL8192E_SUPPORT == 1) */
+#define	ex_halbtc8192e2ant_power_on_setting(btcoexist)
+#define	ex_halbtc8192e2ant_init_hw_config(btcoexist, wifi_only)
+#define	ex_halbtc8192e2ant_init_coex_dm(btcoexist)
+#define	ex_halbtc8192e2ant_ips_notify(btcoexist, type)
+#define	ex_halbtc8192e2ant_lps_notify(btcoexist, type)
+#define	ex_halbtc8192e2ant_scan_notify(btcoexist, type)
+#define	ex_halbtc8192e2ant_connect_notify(btcoexist, type)
+#define	ex_halbtc8192e2ant_media_status_notify(btcoexist, type)
+#define	ex_halbtc8192e2ant_specific_packet_notify(btcoexist, type)
+#define	ex_halbtc8192e2ant_bt_info_notify(btcoexist, tmp_buf, length)
+#define	ex_halbtc8192e2ant_halt_notify(btcoexist)
+#define	ex_halbtc8192e2ant_periodical(btcoexist)
+#define	ex_halbtc8192e2ant_display_coex_info(btcoexist)
+
+#endif
+
+#endif
+
+
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/btc/halbtc8703b1ant.c linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/btc/halbtc8703b1ant.c
--- linux-5.6.3/3rdparty/rtl8821ce/hal/btc/halbtc8703b1ant.c	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/btc/halbtc8703b1ant.c	2020-04-10 16:35:06.781658433 +0300
@@ -0,0 +1,4263 @@
+/* ************************************************************
+ * Description:
+ *
+ * This file is for RTL8703B Co-exist mechanism
+ *
+ * History
+ * 2012/11/15 Cosa first check in.
+ *
+ * ************************************************************ */
+
+/* ************************************************************
+ * include files
+ * ************************************************************ */
+#include "mp_precomp.h"
+
+#if (BT_SUPPORT == 1 && COEX_SUPPORT == 1)
+
+#if (RTL8703B_SUPPORT == 1)
+/* ************************************************************
+ * Global variables, these are static variables
+ * ************************************************************ */
+static u8	*trace_buf = &gl_btc_trace_buf[0];
+static struct  coex_dm_8703b_1ant		glcoex_dm_8703b_1ant;
+static struct  coex_dm_8703b_1ant	*coex_dm = &glcoex_dm_8703b_1ant;
+static struct  coex_sta_8703b_1ant		glcoex_sta_8703b_1ant;
+static struct  coex_sta_8703b_1ant	*coex_sta = &glcoex_sta_8703b_1ant;
+static struct  psdscan_sta_8703b_1ant	gl_psd_scan_8703b_1ant;
+static struct  psdscan_sta_8703b_1ant *psd_scan = &gl_psd_scan_8703b_1ant;
+
+
+const char *const glbt_info_src_8703b_1ant[] = {
+	"BT Info[wifi fw]",
+	"BT Info[bt rsp]",
+	"BT Info[bt auto report]",
+};
+/* ************************************************************
+ * BtCoex Version Format:
+ * 1. date :			glcoex_ver_date_XXXXX_1ant
+ * 2. WifiCoexVersion : glcoex_ver_XXXX_1ant
+ * 3. BtCoexVersion :	glcoex_ver_btdesired_XXXXX_1ant
+ * 4. others :			glcoex_ver_XXXXXX_XXXXX_1ant
+ *
+ * Variable should be indicated IC and Antenna numbers !!!
+ * Please strictly follow this order and naming style !!!
+ *
+ * ************************************************************ */
+u32	glcoex_ver_date_8703b_1ant = 20161220;
+u32	glcoex_ver_8703b_1ant = 0x13;
+u32	glcoex_ver_btdesired_8703b_1ant = 0x10;
+
+
+/* ************************************************************
+ * local function proto type if needed
+ * ************************************************************
+ * ************************************************************
+ * local function start with halbtc8703b1ant_
+ * ************************************************************ */
+u8 halbtc8703b1ant_bt_rssi_state(u8 level_num, u8 rssi_thresh, u8 rssi_thresh1)
+{
+	s32			bt_rssi = 0;
+	u8			bt_rssi_state = coex_sta->pre_bt_rssi_state;
+
+	bt_rssi = coex_sta->bt_rssi;
+
+	if (level_num == 2) {
+		if ((coex_sta->pre_bt_rssi_state == BTC_RSSI_STATE_LOW) ||
+		    (coex_sta->pre_bt_rssi_state ==
+		     BTC_RSSI_STATE_STAY_LOW)) {
+			if (bt_rssi >= (rssi_thresh +
+					BTC_RSSI_COEX_THRESH_TOL_8703B_1ANT))
+				bt_rssi_state = BTC_RSSI_STATE_HIGH;
+			else
+				bt_rssi_state = BTC_RSSI_STATE_STAY_LOW;
+		} else {
+			if (bt_rssi < rssi_thresh)
+				bt_rssi_state = BTC_RSSI_STATE_LOW;
+			else
+				bt_rssi_state = BTC_RSSI_STATE_STAY_HIGH;
+		}
+	} else if (level_num == 3) {
+		if (rssi_thresh > rssi_thresh1) {
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				    "[BTCoex], BT Rssi thresh error!!\n");
+			BTC_TRACE(trace_buf);
+			return coex_sta->pre_bt_rssi_state;
+		}
+
+		if ((coex_sta->pre_bt_rssi_state == BTC_RSSI_STATE_LOW) ||
+		    (coex_sta->pre_bt_rssi_state ==
+		     BTC_RSSI_STATE_STAY_LOW)) {
+			if (bt_rssi >= (rssi_thresh +
+					BTC_RSSI_COEX_THRESH_TOL_8703B_1ANT))
+				bt_rssi_state = BTC_RSSI_STATE_MEDIUM;
+			else
+				bt_rssi_state = BTC_RSSI_STATE_STAY_LOW;
+		} else if ((coex_sta->pre_bt_rssi_state ==
+			    BTC_RSSI_STATE_MEDIUM) ||
+			   (coex_sta->pre_bt_rssi_state ==
+			    BTC_RSSI_STATE_STAY_MEDIUM)) {
+			if (bt_rssi >= (rssi_thresh1 +
+					BTC_RSSI_COEX_THRESH_TOL_8703B_1ANT))
+				bt_rssi_state = BTC_RSSI_STATE_HIGH;
+			else if (bt_rssi < rssi_thresh)
+				bt_rssi_state = BTC_RSSI_STATE_LOW;
+			else
+				bt_rssi_state = BTC_RSSI_STATE_STAY_MEDIUM;
+		} else {
+			if (bt_rssi < rssi_thresh1)
+				bt_rssi_state = BTC_RSSI_STATE_MEDIUM;
+			else
+				bt_rssi_state = BTC_RSSI_STATE_STAY_HIGH;
+		}
+	}
+
+	coex_sta->pre_bt_rssi_state = bt_rssi_state;
+
+	return bt_rssi_state;
+}
+
+u8 halbtc8703b1ant_wifi_rssi_state(IN struct btc_coexist *btcoexist,
+	   IN u8 index, IN u8 level_num, IN u8 rssi_thresh, IN u8 rssi_thresh1)
+{
+	s32			wifi_rssi = 0;
+	u8			wifi_rssi_state = coex_sta->pre_wifi_rssi_state[index];
+
+	btcoexist->btc_get(btcoexist, BTC_GET_S4_WIFI_RSSI, &wifi_rssi);
+
+	if (level_num == 2) {
+		if ((coex_sta->pre_wifi_rssi_state[index] == BTC_RSSI_STATE_LOW)
+		    ||
+		    (coex_sta->pre_wifi_rssi_state[index] ==
+		     BTC_RSSI_STATE_STAY_LOW)) {
+			if (wifi_rssi >= (rssi_thresh +
+					  BTC_RSSI_COEX_THRESH_TOL_8703B_1ANT))
+				wifi_rssi_state = BTC_RSSI_STATE_HIGH;
+			else
+				wifi_rssi_state = BTC_RSSI_STATE_STAY_LOW;
+		} else {
+			if (wifi_rssi < rssi_thresh)
+				wifi_rssi_state = BTC_RSSI_STATE_LOW;
+			else
+				wifi_rssi_state = BTC_RSSI_STATE_STAY_HIGH;
+		}
+	} else if (level_num == 3) {
+		if (rssi_thresh > rssi_thresh1) {
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				    "[BTCoex], wifi RSSI thresh error!!\n");
+			BTC_TRACE(trace_buf);
+			return coex_sta->pre_wifi_rssi_state[index];
+		}
+
+		if ((coex_sta->pre_wifi_rssi_state[index] == BTC_RSSI_STATE_LOW)
+		    ||
+		    (coex_sta->pre_wifi_rssi_state[index] ==
+		     BTC_RSSI_STATE_STAY_LOW)) {
+			if (wifi_rssi >= (rssi_thresh +
+					  BTC_RSSI_COEX_THRESH_TOL_8703B_1ANT))
+				wifi_rssi_state = BTC_RSSI_STATE_MEDIUM;
+			else
+				wifi_rssi_state = BTC_RSSI_STATE_STAY_LOW;
+		} else if ((coex_sta->pre_wifi_rssi_state[index] ==
+			    BTC_RSSI_STATE_MEDIUM) ||
+			   (coex_sta->pre_wifi_rssi_state[index] ==
+			    BTC_RSSI_STATE_STAY_MEDIUM)) {
+			if (wifi_rssi >= (rssi_thresh1 +
+					  BTC_RSSI_COEX_THRESH_TOL_8703B_1ANT))
+				wifi_rssi_state = BTC_RSSI_STATE_HIGH;
+			else if (wifi_rssi < rssi_thresh)
+				wifi_rssi_state = BTC_RSSI_STATE_LOW;
+			else
+				wifi_rssi_state = BTC_RSSI_STATE_STAY_MEDIUM;
+		} else {
+			if (wifi_rssi < rssi_thresh1)
+				wifi_rssi_state = BTC_RSSI_STATE_MEDIUM;
+			else
+				wifi_rssi_state = BTC_RSSI_STATE_STAY_HIGH;
+		}
+	}
+
+	coex_sta->pre_wifi_rssi_state[index] = wifi_rssi_state;
+
+	return wifi_rssi_state;
+}
+
+void halbtc8703b1ant_update_ra_mask(IN struct btc_coexist *btcoexist,
+				    IN boolean force_exec, IN u32 dis_rate_mask)
+{
+	coex_dm->cur_ra_mask = dis_rate_mask;
+
+	if (force_exec || (coex_dm->pre_ra_mask != coex_dm->cur_ra_mask))
+		btcoexist->btc_set(btcoexist, BTC_SET_ACT_UPDATE_RAMASK,
+				   &coex_dm->cur_ra_mask);
+	coex_dm->pre_ra_mask = coex_dm->cur_ra_mask;
+}
+
+void halbtc8703b1ant_auto_rate_fallback_retry(IN struct btc_coexist *btcoexist,
+		IN boolean force_exec, IN u8 type)
+{
+	boolean	wifi_under_b_mode = false;
+
+	coex_dm->cur_arfr_type = type;
+
+	if (force_exec || (coex_dm->pre_arfr_type != coex_dm->cur_arfr_type)) {
+		switch (coex_dm->cur_arfr_type) {
+		case 0:	/* normal mode */
+			btcoexist->btc_write_4byte(btcoexist, 0x430,
+						   coex_dm->backup_arfr_cnt1);
+			btcoexist->btc_write_4byte(btcoexist, 0x434,
+						   coex_dm->backup_arfr_cnt2);
+			break;
+		case 1:
+			btcoexist->btc_get(btcoexist,
+					   BTC_GET_BL_WIFI_UNDER_B_MODE,
+					   &wifi_under_b_mode);
+			if (wifi_under_b_mode) {
+				btcoexist->btc_write_4byte(btcoexist,
+							   0x430, 0x0);
+				btcoexist->btc_write_4byte(btcoexist,
+							   0x434, 0x01010101);
+			} else {
+				btcoexist->btc_write_4byte(btcoexist,
+							   0x430, 0x0);
+				btcoexist->btc_write_4byte(btcoexist,
+							   0x434, 0x04030201);
+			}
+			break;
+		default:
+			break;
+		}
+	}
+
+	coex_dm->pre_arfr_type = coex_dm->cur_arfr_type;
+}
+
+void halbtc8703b1ant_retry_limit(IN struct btc_coexist *btcoexist,
+				 IN boolean force_exec, IN u8 type)
+{
+	coex_dm->cur_retry_limit_type = type;
+
+	if (force_exec ||
+	    (coex_dm->pre_retry_limit_type !=
+	     coex_dm->cur_retry_limit_type)) {
+		switch (coex_dm->cur_retry_limit_type) {
+		case 0:	/* normal mode */
+			btcoexist->btc_write_2byte(btcoexist, 0x42a,
+						   coex_dm->backup_retry_limit);
+			break;
+		case 1:	/* retry limit=8 */
+			btcoexist->btc_write_2byte(btcoexist, 0x42a,
+						   0x0808);
+			break;
+		default:
+			break;
+		}
+	}
+
+	coex_dm->pre_retry_limit_type = coex_dm->cur_retry_limit_type;
+}
+
+void halbtc8703b1ant_ampdu_max_time(IN struct btc_coexist *btcoexist,
+				    IN boolean force_exec, IN u8 type)
+{
+	coex_dm->cur_ampdu_time_type = type;
+
+	if (force_exec ||
+	    (coex_dm->pre_ampdu_time_type != coex_dm->cur_ampdu_time_type)) {
+		switch (coex_dm->cur_ampdu_time_type) {
+		case 0:	/* normal mode */
+			btcoexist->btc_write_1byte(btcoexist, 0x456,
+					   coex_dm->backup_ampdu_max_time);
+			break;
+		case 1:	/* AMPDU timw = 0x38 * 32us */
+			btcoexist->btc_write_1byte(btcoexist, 0x456,
+						   0x38);
+			break;
+		default:
+			break;
+		}
+	}
+
+	coex_dm->pre_ampdu_time_type = coex_dm->cur_ampdu_time_type;
+}
+
+void halbtc8703b1ant_limited_tx(IN struct btc_coexist *btcoexist,
+		IN boolean force_exec, IN u8 ra_mask_type, IN u8 arfr_type,
+				IN u8 retry_limit_type, IN u8 ampdu_time_type)
+{
+	switch (ra_mask_type) {
+	case 0:	/* normal mode */
+		halbtc8703b1ant_update_ra_mask(btcoexist, force_exec,
+					       0x0);
+		break;
+	case 1:	/* disable cck 1/2 */
+		halbtc8703b1ant_update_ra_mask(btcoexist, force_exec,
+					       0x00000003);
+		break;
+	case 2:	/* disable cck 1/2/5.5, ofdm 6/9/12/18/24, mcs 0/1/2/3/4 */
+		halbtc8703b1ant_update_ra_mask(btcoexist, force_exec,
+					       0x0001f1f7);
+		break;
+	default:
+		break;
+	}
+
+	halbtc8703b1ant_auto_rate_fallback_retry(btcoexist, force_exec,
+			arfr_type);
+	halbtc8703b1ant_retry_limit(btcoexist, force_exec, retry_limit_type);
+	halbtc8703b1ant_ampdu_max_time(btcoexist, force_exec, ampdu_time_type);
+}
+
+void halbtc8703b1ant_limited_rx(IN struct btc_coexist *btcoexist,
+			IN boolean force_exec, IN boolean rej_ap_agg_pkt,
+			IN boolean bt_ctrl_agg_buf_size, IN u8 agg_buf_size)
+{
+	boolean	reject_rx_agg = rej_ap_agg_pkt;
+	boolean	bt_ctrl_rx_agg_size = bt_ctrl_agg_buf_size;
+	u8	rx_agg_size = agg_buf_size;
+
+	/* ============================================ */
+	/*	Rx Aggregation related setting */
+	/* ============================================ */
+	btcoexist->btc_set(btcoexist, BTC_SET_BL_TO_REJ_AP_AGG_PKT,
+			   &reject_rx_agg);
+	/* decide BT control aggregation buf size or not */
+	btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_CTRL_AGG_SIZE,
+			   &bt_ctrl_rx_agg_size);
+	/* aggregation buf size, only work when BT control Rx aggregation size. */
+	btcoexist->btc_set(btcoexist, BTC_SET_U1_AGG_BUF_SIZE, &rx_agg_size);
+	/* real update aggregation setting */
+	btcoexist->btc_set(btcoexist, BTC_SET_ACT_AGGREGATE_CTRL, NULL);
+
+
+}
+
+void halbtc8703b1ant_query_bt_info(IN struct btc_coexist *btcoexist)
+{
+	u8			h2c_parameter[1] = {0};
+
+
+	h2c_parameter[0] |= BIT(0);	/* trigger */
+
+	btcoexist->btc_fill_h2c(btcoexist, 0x61, 1, h2c_parameter);
+}
+
+void halbtc8703b1ant_monitor_bt_ctr(IN struct btc_coexist *btcoexist)
+{
+	u32			reg_hp_txrx, reg_lp_txrx, u32tmp;
+	u32			reg_hp_tx = 0, reg_hp_rx = 0, reg_lp_tx = 0, reg_lp_rx = 0;
+	static u8		num_of_bt_counter_chk = 0, cnt_slave = 0, cnt_overhead = 0;
+	struct  btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
+
+	/* to avoid 0x76e[3] = 1 (WLAN_Act control by PTA) during IPS */
+	/* if (! (btcoexist->btc_read_1byte(btcoexist, 0x76e) & 0x8) ) */
+
+	reg_hp_txrx = 0x770;
+	reg_lp_txrx = 0x774;
+
+	u32tmp = btcoexist->btc_read_4byte(btcoexist, reg_hp_txrx);
+	reg_hp_tx = u32tmp & MASKLWORD;
+	reg_hp_rx = (u32tmp & MASKHWORD) >> 16;
+
+	u32tmp = btcoexist->btc_read_4byte(btcoexist, reg_lp_txrx);
+	reg_lp_tx = u32tmp & MASKLWORD;
+	reg_lp_rx = (u32tmp & MASKHWORD) >> 16;
+
+	coex_sta->high_priority_tx = reg_hp_tx;
+	coex_sta->high_priority_rx = reg_hp_rx;
+	coex_sta->low_priority_tx = reg_lp_tx;
+	coex_sta->low_priority_rx = reg_lp_rx;
+
+	if (BT_8703B_1ANT_BT_STATUS_NON_CONNECTED_IDLE ==
+			coex_dm->bt_status) {
+
+			if (coex_sta->high_priority_rx >= 15) {
+					if (cnt_overhead < 3)
+						cnt_overhead++;
+
+					if (cnt_overhead == 3)
+						coex_sta->is_hiPri_rx_overhead = true;
+			} else {
+					if (cnt_overhead > 0)
+						cnt_overhead--;
+
+					if (cnt_overhead == 0)
+						coex_sta->is_hiPri_rx_overhead = false;
+			}
+	} else
+		coex_sta->is_hiPri_rx_overhead = false;
+
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+		    "[BTCoex], Hi-Pri Rx/Tx: %d/%d, Lo-Pri Rx/Tx: %d/%d\n",
+		    reg_hp_rx, reg_hp_tx, reg_lp_rx, reg_lp_tx);
+
+	BTC_TRACE(trace_buf);
+
+	/* reset counter */
+	btcoexist->btc_write_1byte(btcoexist, 0x76e, 0xc);
+
+	if ((coex_sta->low_priority_tx > 1150)  &&
+	    (!coex_sta->c2h_bt_inquiry_page))
+		coex_sta->pop_event_cnt++;
+
+	if ((coex_sta->low_priority_rx >= 1150) &&
+	    (coex_sta->low_priority_rx >= coex_sta->low_priority_tx)
+	    && (!coex_sta->under_ips)  && (!coex_sta->c2h_bt_inquiry_page) &&
+	    (coex_sta->bt_link_exist))	{
+		if (cnt_slave >= 3) {
+			bt_link_info->slave_role = true;
+			cnt_slave = 3;
+		} else
+			cnt_slave++;
+	} else {
+		if (cnt_slave == 0)	{
+			bt_link_info->slave_role = false;
+			cnt_slave = 0;
+		} else
+			cnt_slave--;
+
+	}
+
+	if (!coex_sta->bt_disabled) {
+		if ((coex_sta->high_priority_tx == 0) &&
+		    (coex_sta->high_priority_rx == 0) &&
+		    (coex_sta->low_priority_tx == 0) &&
+		    (coex_sta->low_priority_rx == 0)) {
+			num_of_bt_counter_chk++;
+			if (num_of_bt_counter_chk >= 3) {
+				halbtc8703b1ant_query_bt_info(btcoexist);
+				num_of_bt_counter_chk = 0;
+			}
+		}
+	}
+
+}
+
+
+void halbtc8703b1ant_monitor_wifi_ctr(IN struct btc_coexist *btcoexist)
+{
+#if 1
+		s32 wifi_rssi = 0;
+		boolean wifi_busy = false, wifi_under_b_mode = false,
+				wifi_scan = false;
+		boolean bt_idle = false, wl_idle = false;
+		static u8 cck_lock_counter = 0, wl_noisy_count0 = 0,
+			   wl_noisy_count1 = 3, wl_noisy_count2 = 0;
+		u32 total_cnt, reg_val1, reg_val2, cck_cnt;
+
+		btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy);
+		btcoexist->btc_get(btcoexist, BTC_GET_S4_WIFI_RSSI, &wifi_rssi);
+		btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_B_MODE,
+				   &wifi_under_b_mode);
+
+		btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_SCAN, &wifi_scan);
+
+		coex_sta->crc_ok_cck = btcoexist->btc_phydm_query_PHY_counter(
+									btcoexist, PHYDM_INFO_CRC32_OK_CCK);
+		coex_sta->crc_ok_11g = btcoexist->btc_phydm_query_PHY_counter(
+									btcoexist, PHYDM_INFO_CRC32_OK_LEGACY);
+		coex_sta->crc_ok_11n = btcoexist->btc_phydm_query_PHY_counter(
+									btcoexist, PHYDM_INFO_CRC32_OK_HT);
+		coex_sta->crc_ok_11n_vht = btcoexist->btc_phydm_query_PHY_counter(
+									btcoexist, PHYDM_INFO_CRC32_OK_VHT);
+
+		coex_sta->crc_err_cck = btcoexist->btc_phydm_query_PHY_counter(
+									btcoexist, PHYDM_INFO_CRC32_ERROR_CCK);
+		coex_sta->crc_err_11g =  btcoexist->btc_phydm_query_PHY_counter(
+									btcoexist, PHYDM_INFO_CRC32_ERROR_LEGACY);
+		coex_sta->crc_err_11n = btcoexist->btc_phydm_query_PHY_counter(
+									btcoexist, PHYDM_INFO_CRC32_ERROR_HT);
+		coex_sta->crc_err_11n_vht = btcoexist->btc_phydm_query_PHY_counter(
+									btcoexist, PHYDM_INFO_CRC32_ERROR_VHT);
+
+		cck_cnt = coex_sta->crc_ok_cck + coex_sta->crc_err_cck;
+
+		if ((coex_dm->bt_status == BT_8703B_1ANT_BT_STATUS_NON_CONNECTED_IDLE) ||
+			(coex_dm->bt_status == BT_8703B_1ANT_BT_STATUS_CONNECTED_IDLE) ||
+			(coex_sta->bt_disabled))
+			bt_idle = true;
+
+		if ((!wifi_busy) && (!wifi_scan) && (!coex_sta->under_lps)
+			&& (!coex_sta->under_ips))
+			wl_idle = true;
+
+		if ((wl_idle) && (bt_idle)) {
+			if (cck_cnt > 250) {
+				if (wl_noisy_count2 < 3)
+					wl_noisy_count2++;
+
+				if (wl_noisy_count2 == 3) {
+					wl_noisy_count0 = 0;
+					wl_noisy_count1 = 0;
+				}
+			} else if (cck_cnt < 50) {
+				if (wl_noisy_count0 < 3)
+					wl_noisy_count0++;
+
+				if (wl_noisy_count0 == 3) {
+					wl_noisy_count1 = 0;
+					wl_noisy_count2 = 0;
+				}
+			} else {
+				if (wl_noisy_count1 < 3)
+					wl_noisy_count1++;
+
+				if (wl_noisy_count1 == 3) {
+					wl_noisy_count0 = 0;
+					wl_noisy_count2 = 0;
+				}
+			}
+
+			if (wl_noisy_count2 == 3)
+				coex_sta->wl_noisy_level = 2;
+			else if (wl_noisy_count1 == 3)
+				coex_sta->wl_noisy_level = 1;
+			else
+				coex_sta->wl_noisy_level = 0;
+		}
+
+		if ((wifi_busy) && (wifi_rssi >= 30) && (!wifi_under_b_mode)) {
+			total_cnt = coex_sta->crc_ok_cck + coex_sta->crc_ok_11g +
+					coex_sta->crc_ok_11n + coex_sta->crc_ok_11n_vht;
+
+			if ((coex_dm->bt_status == BT_8703B_1ANT_BT_STATUS_ACL_BUSY) ||
+				(coex_dm->bt_status == BT_8703B_1ANT_BT_STATUS_ACL_SCO_BUSY) ||
+				(coex_dm->bt_status == BT_8703B_1ANT_BT_STATUS_SCO_BUSY)) {
+				if (coex_sta->crc_ok_cck > (total_cnt -
+								coex_sta->crc_ok_cck)) {
+					if (cck_lock_counter < 3)
+						cck_lock_counter++;
+				} else {
+					if (cck_lock_counter > 0)
+						cck_lock_counter--;
+				}
+
+			} else {
+				if (cck_lock_counter > 0)
+					cck_lock_counter--;
+			}
+		} else {
+			if (cck_lock_counter > 0)
+				cck_lock_counter--;
+		}
+
+		if (!coex_sta->pre_ccklock) {
+
+			if (cck_lock_counter >= 3)
+				coex_sta->cck_lock = true;
+			else
+				coex_sta->cck_lock = false;
+		} else {
+			if (cck_lock_counter == 0)
+				coex_sta->cck_lock = false;
+			else
+				coex_sta->cck_lock = true;
+		}
+
+		if (coex_sta->cck_lock)
+			coex_sta->cck_ever_lock = true;
+
+		coex_sta->pre_ccklock =  coex_sta->cck_lock;
+
+#endif
+}
+
+void halbtc8703b1ant_update_bt_link_info(IN struct btc_coexist *btcoexist)
+{
+	struct  btc_bt_link_info	*bt_link_info = &btcoexist->bt_link_info;
+	boolean				bt_hs_on = false;
+	boolean		bt_busy = false;
+
+
+	coex_sta->num_of_profile = 0;
+
+	/* set link exist status */
+	if (!(coex_sta->bt_info & BT_INFO_8703B_1ANT_B_CONNECTION)) {
+		coex_sta->bt_link_exist = false;
+		coex_sta->pan_exist = false;
+		coex_sta->a2dp_exist = false;
+		coex_sta->hid_exist = false;
+		coex_sta->sco_exist = false;
+	} else {	/* connection exists */
+		coex_sta->bt_link_exist = true;
+		if (coex_sta->bt_info & BT_INFO_8703B_1ANT_B_FTP) {
+			coex_sta->pan_exist = true;
+			coex_sta->num_of_profile++;
+		} else
+			coex_sta->pan_exist = false;
+
+		if (coex_sta->bt_info & BT_INFO_8703B_1ANT_B_A2DP) {
+			coex_sta->a2dp_exist = true;
+			coex_sta->num_of_profile++;
+		} else
+			coex_sta->a2dp_exist = false;
+
+		if (coex_sta->bt_info & BT_INFO_8703B_1ANT_B_HID) {
+			coex_sta->hid_exist = true;
+			coex_sta->num_of_profile++;
+		} else
+			coex_sta->hid_exist = false;
+
+		if (coex_sta->bt_info & BT_INFO_8703B_1ANT_B_SCO_ESCO) {
+			coex_sta->sco_exist = true;
+			coex_sta->num_of_profile++;
+		} else
+			coex_sta->sco_exist = false;
+
+	}
+
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on);
+
+	bt_link_info->bt_link_exist = coex_sta->bt_link_exist;
+	bt_link_info->sco_exist = coex_sta->sco_exist;
+	bt_link_info->a2dp_exist = coex_sta->a2dp_exist;
+	bt_link_info->pan_exist = coex_sta->pan_exist;
+	bt_link_info->hid_exist = coex_sta->hid_exist;
+	bt_link_info->acl_busy = coex_sta->acl_busy;
+
+	/* work around for HS mode. */
+	if (bt_hs_on) {
+		bt_link_info->pan_exist = true;
+		bt_link_info->bt_link_exist = true;
+	}
+
+	/* check if Sco only */
+	if (bt_link_info->sco_exist &&
+	    !bt_link_info->a2dp_exist &&
+	    !bt_link_info->pan_exist &&
+	    !bt_link_info->hid_exist)
+		bt_link_info->sco_only = true;
+	else
+		bt_link_info->sco_only = false;
+
+	/* check if A2dp only */
+	if (!bt_link_info->sco_exist &&
+	    bt_link_info->a2dp_exist &&
+	    !bt_link_info->pan_exist &&
+	    !bt_link_info->hid_exist)
+		bt_link_info->a2dp_only = true;
+	else
+		bt_link_info->a2dp_only = false;
+
+	/* check if Pan only */
+	if (!bt_link_info->sco_exist &&
+	    !bt_link_info->a2dp_exist &&
+	    bt_link_info->pan_exist &&
+	    !bt_link_info->hid_exist)
+		bt_link_info->pan_only = true;
+	else
+		bt_link_info->pan_only = false;
+
+	/* check if Hid only */
+	if (!bt_link_info->sco_exist &&
+	    !bt_link_info->a2dp_exist &&
+	    !bt_link_info->pan_exist &&
+	    bt_link_info->hid_exist)
+		bt_link_info->hid_only = true;
+	else
+		bt_link_info->hid_only = false;
+
+	if (coex_sta->bt_info & BT_INFO_8703B_1ANT_B_INQ_PAGE) {
+		coex_dm->bt_status = BT_8703B_1ANT_BT_STATUS_INQ_PAGE;
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			"[BTCoex], BtInfoNotify(), BT Inq/page!!!\n");
+	} else if (!(coex_sta->bt_info & BT_INFO_8703B_1ANT_B_CONNECTION)) {
+		coex_dm->bt_status = BT_8703B_1ANT_BT_STATUS_NON_CONNECTED_IDLE;
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			"[BTCoex], BtInfoNotify(), BT Non-Connected idle!!!\n");
+	} else if (coex_sta->bt_info == BT_INFO_8703B_1ANT_B_CONNECTION) {
+		/* connection exists but no busy */
+		coex_dm->bt_status = BT_8703B_1ANT_BT_STATUS_CONNECTED_IDLE;
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], BtInfoNotify(), BT Connected-idle!!!\n");
+	} else if (((coex_sta->bt_info & BT_INFO_8703B_1ANT_B_SCO_ESCO) ||
+		    (coex_sta->bt_info & BT_INFO_8703B_1ANT_B_SCO_BUSY)) &&
+		   (coex_sta->bt_info & BT_INFO_8703B_1ANT_B_ACL_BUSY)) {
+		coex_dm->bt_status = BT_8703B_1ANT_BT_STATUS_ACL_SCO_BUSY;
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], BtInfoNotify(), BT ACL SCO busy!!!\n");
+	} else if ((coex_sta->bt_info & BT_INFO_8703B_1ANT_B_SCO_ESCO) ||
+		   (coex_sta->bt_info & BT_INFO_8703B_1ANT_B_SCO_BUSY)) {
+		coex_dm->bt_status = BT_8703B_1ANT_BT_STATUS_SCO_BUSY;
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], BtInfoNotify(), BT SCO busy!!!\n");
+	} else if (coex_sta->bt_info & BT_INFO_8703B_1ANT_B_ACL_BUSY) {
+		coex_dm->bt_status = BT_8703B_1ANT_BT_STATUS_ACL_BUSY;
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], BtInfoNotify(), BT ACL busy!!!\n");
+	} else {
+		coex_dm->bt_status = BT_8703B_1ANT_BT_STATUS_MAX;
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			"[BTCoex], BtInfoNotify(), BT Non-Defined state!!!\n");
+	}
+
+	BTC_TRACE(trace_buf);
+
+	if ((BT_8703B_1ANT_BT_STATUS_ACL_BUSY == coex_dm->bt_status) ||
+	    (BT_8703B_1ANT_BT_STATUS_SCO_BUSY == coex_dm->bt_status) ||
+	    (BT_8703B_1ANT_BT_STATUS_ACL_SCO_BUSY == coex_dm->bt_status))
+		bt_busy = true;
+	else
+		bt_busy = false;
+
+	btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_TRAFFIC_BUSY, &bt_busy);
+}
+
+
+void halbtc8703b1ant_update_wifi_channel_info(IN struct btc_coexist *btcoexist,
+		IN u8 type)
+{
+	u8			h2c_parameter[3] = {0};
+	u32			wifi_bw;
+	u8			wifi_central_chnl;
+
+	/* only 2.4G we need to inform bt the chnl mask */
+	btcoexist->btc_get(btcoexist, BTC_GET_U1_WIFI_CENTRAL_CHNL,
+			   &wifi_central_chnl);
+	if ((BTC_MEDIA_CONNECT == type) &&
+	    (wifi_central_chnl <= 14)) {
+		h2c_parameter[0] =
+			0x1;  /* enable BT AFH skip WL channel for 8703b because BT Rx LO interference */
+		/* h2c_parameter[0] = 0x0; */
+		h2c_parameter[1] = wifi_central_chnl;
+		btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw);
+		if (BTC_WIFI_BW_HT40 == wifi_bw)
+			h2c_parameter[2] = 0x30;
+		else
+			h2c_parameter[2] = 0x20;
+	}
+
+	coex_dm->wifi_chnl_info[0] = h2c_parameter[0];
+	coex_dm->wifi_chnl_info[1] = h2c_parameter[1];
+	coex_dm->wifi_chnl_info[2] = h2c_parameter[2];
+
+	btcoexist->btc_fill_h2c(btcoexist, 0x66, 3, h2c_parameter);
+
+}
+
+void halbtc8703b1ant_set_bt_auto_report(IN struct btc_coexist *btcoexist,
+					IN boolean enable_auto_report)
+{
+	u8			h2c_parameter[1] = {0};
+
+	h2c_parameter[0] = 0;
+
+	if (enable_auto_report)
+		h2c_parameter[0] |= BIT(0);
+
+	btcoexist->btc_fill_h2c(btcoexist, 0x68, 1, h2c_parameter);
+}
+
+void halbtc8703b1ant_bt_auto_report(IN struct btc_coexist *btcoexist,
+		    IN boolean force_exec, IN boolean enable_auto_report)
+{
+	coex_dm->cur_bt_auto_report = enable_auto_report;
+
+	if (!force_exec) {
+		if (coex_dm->pre_bt_auto_report == coex_dm->cur_bt_auto_report)
+			return;
+	}
+	halbtc8703b1ant_set_bt_auto_report(btcoexist,
+					   coex_dm->cur_bt_auto_report);
+
+	coex_dm->pre_bt_auto_report = coex_dm->cur_bt_auto_report;
+}
+
+void halbtc8703b1ant_set_fw_low_penalty_ra(IN struct btc_coexist
+		*btcoexist, IN boolean low_penalty_ra)
+{
+	u8			h2c_parameter[6] = {0};
+
+	h2c_parameter[0] = 0x6;	/* op_code, 0x6= Retry_Penalty */
+
+	if (low_penalty_ra) {
+		h2c_parameter[1] |= BIT(0);
+		h2c_parameter[2] =
+			0x00;  /* normal rate except MCS7/6/5, OFDM54/48/36 */
+		h2c_parameter[3] = 0xf7;  /* MCS7 or OFDM54 */
+		h2c_parameter[4] = 0xf8;  /* MCS6 or OFDM48 */
+		h2c_parameter[5] = 0xf9;	/* MCS5 or OFDM36	 */
+	}
+
+	btcoexist->btc_fill_h2c(btcoexist, 0x69, 6, h2c_parameter);
+}
+
+void halbtc8703b1ant_low_penalty_ra(IN struct btc_coexist *btcoexist,
+			    IN boolean force_exec, IN boolean low_penalty_ra)
+{
+	coex_dm->cur_low_penalty_ra = low_penalty_ra;
+
+	if (!force_exec) {
+		if (coex_dm->pre_low_penalty_ra == coex_dm->cur_low_penalty_ra)
+			return;
+	}
+
+	halbtc8703b1ant_set_fw_low_penalty_ra(btcoexist,
+					      coex_dm->cur_low_penalty_ra);
+
+	coex_dm->pre_low_penalty_ra = coex_dm->cur_low_penalty_ra;
+}
+
+void halbtc8703b1ant_write_score_board(
+	IN	struct  btc_coexist		*btcoexist,
+	IN	u16				bitpos,
+	IN	boolean		state
+)
+{
+
+	static u16 originalval = 0x8002;
+
+	if (state)
+		originalval = originalval | bitpos;
+	else
+		originalval = originalval & (~bitpos);
+
+
+	btcoexist->btc_write_2byte(btcoexist, 0xaa, originalval);
+#if 0
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+		    "\n [BTCoex], ********** Write Scoreboard = %x**********\n",
+		    originalval);
+	BTC_TRACE(trace_buf);
+#endif
+
+}
+
+void halbtc8703b1ant_read_score_board(
+	IN	struct  btc_coexist		*btcoexist,
+	IN   u16				*score_board_val
+)
+{
+
+	*score_board_val = (btcoexist->btc_read_2byte(btcoexist,
+			    0xaa)) & 0x7fff;
+}
+
+void halbtc8703b1ant_post_state_to_bt(
+	IN	struct  btc_coexist		*btcoexist,
+	IN	u16						type,
+	IN  boolean                 state
+)
+{
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+		"[BTCoex], halbtc8703b1ant_post_state_to_bt: type = %d, state =%d\n",
+		type, state);
+	BTC_TRACE(trace_buf);
+
+	halbtc8703b1ant_write_score_board(btcoexist, (u16) type, state);
+}
+
+boolean halbtc8703b1ant_is_wifibt_status_changed(IN struct btc_coexist
+		*btcoexist)
+{
+	static boolean	pre_wifi_busy = false, pre_under_4way = false,
+			pre_bt_hs_on = false, pre_bt_off = false, pre_bt_slave = false;
+	static u8 pre_hid_busy_num = 0, pre_wl_noisy_level = 0;
+	boolean wifi_busy = false, under_4way = false, bt_hs_on = false;
+	boolean wifi_connected = false;
+	struct	btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
+
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED,
+			   &wifi_connected);
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy);
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on);
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_4_WAY_PROGRESS,
+			   &under_4way);
+
+	if (coex_sta->bt_disabled != pre_bt_off) {
+		pre_bt_off = coex_sta->bt_disabled;
+
+		if (coex_sta->bt_disabled)
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+					"[BTCoex], BT is disabled !!\n");
+		else
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+					"[BTCoex], BT is enabled !!\n");
+
+		BTC_TRACE(trace_buf);
+
+		coex_sta->bt_coex_supported_feature = 0;
+		coex_sta->bt_coex_supported_version = 0;
+		coex_sta->bt_ble_scan_type = 0;
+		coex_sta->bt_ble_scan_para[0] = 0;
+		coex_sta->bt_ble_scan_para[1] = 0;
+		coex_sta->bt_ble_scan_para[2] = 0;
+
+		return true;
+	}
+
+	if (wifi_connected) {
+		if (wifi_busy != pre_wifi_busy) {
+			pre_wifi_busy = wifi_busy;
+
+			if (wifi_busy)
+				halbtc8703b1ant_post_state_to_bt(btcoexist,
+						BT_8703B_1ANT_SCOREBOARD_UNDERTEST, true);
+			else
+				halbtc8703b1ant_post_state_to_bt(btcoexist,
+						BT_8703B_1ANT_SCOREBOARD_UNDERTEST, false);
+			return true;
+		}
+		if (under_4way != pre_under_4way) {
+			pre_under_4way = under_4way;
+			return true;
+		}
+		if (bt_hs_on != pre_bt_hs_on) {
+			pre_bt_hs_on = bt_hs_on;
+			return true;
+		}
+		if (coex_sta->wl_noisy_level != pre_wl_noisy_level) {
+			pre_wl_noisy_level = coex_sta->wl_noisy_level;
+			return true;
+		}
+	}
+
+	if (!coex_sta->bt_disabled) {
+		if (coex_sta->hid_busy_num != pre_hid_busy_num) {
+			pre_hid_busy_num = coex_sta->hid_busy_num;
+			return true;
+		}
+	}
+
+	if (bt_link_info->slave_role != pre_bt_slave) {
+		pre_bt_slave = bt_link_info->slave_role;
+		return true;
+	}
+
+	return false;
+}
+
+
+void halbtc8703b1ant_monitor_bt_enable_disable(IN struct btc_coexist *btcoexist)
+{
+	static u32		bt_disable_cnt = 0;
+	boolean			bt_active = true, bt_disabled = false;
+	u16			u16tmp;
+
+	/* This function check if bt is disabled */
+#if 1
+	if (coex_sta->high_priority_tx == 0 &&
+	    coex_sta->high_priority_rx == 0 &&
+	    coex_sta->low_priority_tx == 0 &&
+	    coex_sta->low_priority_rx == 0)
+		bt_active = false;
+	if (coex_sta->high_priority_tx == 0xffff &&
+	    coex_sta->high_priority_rx == 0xffff &&
+	    coex_sta->low_priority_tx == 0xffff &&
+	    coex_sta->low_priority_rx == 0xffff)
+		bt_active = false;
+
+
+#else   /*  8703b BT can't show correct on/off status in scoreboard[1] 2015/11/26 */
+
+	halbtc8703b1ant_read_score_board(btcoexist,	&u16tmp);
+
+	bt_active = u16tmp & BIT(1);
+
+
+#endif
+
+	if (bt_active) {
+		bt_disable_cnt = 0;
+		bt_disabled = false;
+		btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_DISABLE,
+				   &bt_disabled);
+	} else {
+
+		bt_disable_cnt++;
+		if (bt_disable_cnt >= 10) {
+			bt_disabled = true;
+			bt_disable_cnt = 10;
+		}
+
+		btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_DISABLE,
+				   &bt_disabled);
+	}
+
+	if (bt_disabled)
+		halbtc8703b1ant_low_penalty_ra(btcoexist, NORMAL_EXEC, false);
+	else
+		halbtc8703b1ant_low_penalty_ra(btcoexist, NORMAL_EXEC, true);
+
+	if (coex_sta->bt_disabled != bt_disabled) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], BT is from %s to %s!!\n",
+			    (coex_sta->bt_disabled ? "disabled" : "enabled"),
+			    (bt_disabled ? "disabled" : "enabled"));
+		BTC_TRACE(trace_buf);
+		coex_sta->bt_disabled = bt_disabled;
+
+	}
+}
+
+
+
+void halbtc8703b1ant_enable_gnt_to_gpio(IN struct btc_coexist *btcoexist,
+					IN boolean isenable)
+{
+
+#if (BT_8703B_1ANT_ENABLE_GNTBT_TO_GPIO14 == 1)
+	if (isenable) {
+		/* enable GNT_WL/GNT_BT debug signal to GPIO14/15 */
+		btcoexist->btc_write_1byte_bitmask(btcoexist, 0x73, 0x8, 0x1);
+
+		/* enable GNT_BT debug to GPIO */
+		btcoexist->btc_write_1byte_bitmask(btcoexist, 0x4e, 0x40, 0x0);
+		btcoexist->btc_write_1byte_bitmask(btcoexist, 0x67, 0x1, 0x0);
+	} else {
+		/* enable GNT_WL/GNT_BT debug signal to GPIO14/15 */
+		btcoexist->btc_write_1byte_bitmask(btcoexist, 0x73, 0x8, 0x0);
+
+		/* Disable GNT_BT debug to GPIO, and enable chip_wakeup_host */
+		btcoexist->btc_write_1byte_bitmask(btcoexist, 0x4e, 0x40, 0x1);
+		btcoexist->btc_write_1byte_bitmask(btcoexist, 0x67, 0x1, 0x1);
+	}
+#endif
+}
+
+u32 halbtc8703b1ant_ltecoex_indirect_read_reg(IN struct btc_coexist *btcoexist,
+		IN u16 reg_addr)
+{
+	u32 j = 0, delay_count = 0;
+
+
+	/* wait for ready bit before access 0x7c0		 */
+	btcoexist->btc_write_4byte(btcoexist, 0x7c0, 0x800F0000 | reg_addr);
+
+	while (1) {
+		if ((btcoexist->btc_read_1byte(btcoexist, 0x7c3)&BIT(5)) == 0) {
+			delay_ms(50);
+			delay_count++;
+			if (delay_count >= 10) {
+				delay_count = 0;
+				break;
+			}
+		} else
+			break;
+	}
+
+	return btcoexist->btc_read_4byte(btcoexist,
+					 0x7c8);  /* get read data */
+
+}
+
+void halbtc8703b1ant_ltecoex_indirect_write_reg(IN struct btc_coexist
+		*btcoexist,
+		IN u16 reg_addr, IN u32 bit_mask, IN u32 reg_value)
+{
+	u32 val, i = 0, j = 0, bitpos = 0, delay_count = 0;
+
+
+	if (bit_mask == 0x0)
+		return;
+	if (bit_mask == 0xffffffff) {
+		btcoexist->btc_write_4byte(btcoexist, 0x7c4,
+					   reg_value); /* put write data */
+
+		/* wait for ready bit before access 0x7c0 */
+	while (1) {
+		if ((btcoexist->btc_read_1byte(btcoexist, 0x7c3)&BIT(5)) == 0) {
+			delay_ms(50);
+			delay_count++;
+			if (delay_count >= 10) {
+				delay_count = 0;
+				break;
+			}
+		} else
+			break;
+	}
+
+		btcoexist->btc_write_4byte(btcoexist, 0x7c0,
+					   0xc00F0000 | reg_addr);
+	} else {
+		for (i = 0; i <= 31; i++) {
+			if (((bit_mask >> i) & 0x1) == 0x1) {
+				bitpos = i;
+				break;
+			}
+		}
+
+		/* read back register value before write */
+		val = halbtc8703b1ant_ltecoex_indirect_read_reg(btcoexist,
+				reg_addr);
+		val = (val & (~bit_mask)) | (reg_value << bitpos);
+
+		btcoexist->btc_write_4byte(btcoexist, 0x7c4,
+					   val); /* put write data */
+
+		/* wait for ready bit before access 0x7c0		 */
+		while (1) {
+		if ((btcoexist->btc_read_1byte(btcoexist, 0x7c3)&BIT(5)) == 0) {
+			delay_ms(50);
+			delay_count++;
+			if (delay_count >= 10) {
+				delay_count = 0;
+				break;
+			}
+		} else
+			break;
+	}
+
+		btcoexist->btc_write_4byte(btcoexist, 0x7c0,
+					   0xc00F0000 | reg_addr);
+
+	}
+
+}
+
+void halbtc8703b1ant_ltecoex_enable(IN struct btc_coexist *btcoexist,
+				    IN boolean enable)
+{
+	u8 val;
+
+	val = (enable) ? 1 : 0;
+	halbtc8703b1ant_ltecoex_indirect_write_reg(btcoexist, 0x38, 0x80,
+			val);  /* 0x38[7] */
+
+}
+
+void halbtc8703b1ant_ltecoex_pathcontrol_owner(IN struct btc_coexist *btcoexist,
+		IN boolean wifi_control)
+{
+	u8 val;
+
+	val = (wifi_control) ? 1 : 0;
+	btcoexist->btc_write_1byte_bitmask(btcoexist, 0x73, 0x4,
+					   val); /* 0x70[26] */
+
+}
+
+void halbtc8703b1ant_ltecoex_set_gnt_bt(IN struct btc_coexist *btcoexist,
+			IN u8 control_block, IN boolean sw_control, IN u8 state)
+{
+	u32 val = 0, val_orig = 0;
+
+	if (!sw_control)
+		val = 0x0;
+	else if (state & 0x1)
+		val = 0x3;
+	else
+		val = 0x1;
+
+	val_orig = halbtc8703b1ant_ltecoex_indirect_read_reg(btcoexist,
+				0x38);
+
+	switch (control_block) {
+	case BT_8703B_1ANT_GNT_BLOCK_RFC_BB:
+	default:
+		val = ((val << 14) | (val << 10)) | (val_orig & 0xffff33ff);
+		break;
+	case BT_8703B_1ANT_GNT_BLOCK_RFC:
+		val = (val << 14) | (val_orig & 0xffff3fff);
+		break;
+	case BT_8703B_1ANT_GNT_BLOCK_BB:
+		val = (val << 10) | (val_orig & 0xfffff3ff);
+		break;
+	}
+
+	halbtc8703b1ant_ltecoex_indirect_write_reg(btcoexist,
+			0x38, 0xffffffff, val);
+}
+
+
+void halbtc8703b1ant_ltecoex_set_gnt_wl(IN struct btc_coexist *btcoexist,
+			IN u8 control_block, IN boolean sw_control, IN u8 state)
+{
+	u32 val = 0, val_orig = 0;
+
+	if (!sw_control)
+		val = 0x0;
+	else if (state & 0x1)
+		val = 0x3;
+	else
+		val = 0x1;
+
+	val_orig = halbtc8703b1ant_ltecoex_indirect_read_reg(btcoexist,
+				0x38);
+
+	switch (control_block) {
+	case BT_8703B_1ANT_GNT_BLOCK_RFC_BB:
+	default:
+		val = ((val << 12) | (val << 8)) | (val_orig & 0xffffccff);
+		break;
+	case BT_8703B_1ANT_GNT_BLOCK_RFC:
+		val = (val << 12) | (val_orig & 0xffffcfff);
+		break;
+	case BT_8703B_1ANT_GNT_BLOCK_BB:
+		val = (val << 8) | (val_orig & 0xfffffcff);
+		break;
+	}
+
+	halbtc8703b1ant_ltecoex_indirect_write_reg(btcoexist,
+			0x38, 0xffffffff, val);
+}
+
+
+void halbtc8703b1ant_ltecoex_set_coex_table(IN struct btc_coexist *btcoexist,
+		IN u8 table_type, IN u16 table_content)
+{
+	u16 reg_addr = 0x0000;
+
+	switch (table_type) {
+	case BT_8703B_1ANT_CTT_WL_VS_LTE:
+		reg_addr = 0xa0;
+		break;
+	case BT_8703B_1ANT_CTT_BT_VS_LTE:
+		reg_addr = 0xa4;
+		break;
+	}
+
+	if (reg_addr != 0x0000)
+		halbtc8703b1ant_ltecoex_indirect_write_reg(btcoexist, reg_addr,
+			0xffff, table_content); /* 0xa0[15:0] or 0xa4[15:0] */
+
+
+}
+
+
+void halbtc8703b1ant_ltecoex_set_break_table(IN struct btc_coexist *btcoexist,
+		IN u8 table_type, IN u8 table_content)
+{
+	u16 reg_addr = 0x0000;
+
+	switch (table_type) {
+	case BT_8703B_1ANT_LBTT_WL_BREAK_LTE:
+		reg_addr = 0xa8;
+		break;
+	case BT_8703B_1ANT_LBTT_BT_BREAK_LTE:
+		reg_addr = 0xac;
+		break;
+	case BT_8703B_1ANT_LBTT_LTE_BREAK_WL:
+		reg_addr = 0xb0;
+		break;
+	case BT_8703B_1ANT_LBTT_LTE_BREAK_BT:
+		reg_addr = 0xb4;
+		break;
+	}
+
+	if (reg_addr != 0x0000)
+		halbtc8703b1ant_ltecoex_indirect_write_reg(btcoexist, reg_addr,
+			0xff, table_content); /* 0xa8[15:0] or 0xb4[15:0] */
+
+
+}
+
+void halbtc8703b1ant_set_wltoggle_coex_table(IN struct btc_coexist *btcoexist,
+		IN boolean force_exec,  IN u8 interval,
+		IN u8 val0x6c4_b0, IN u8 val0x6c4_b1, IN u8 val0x6c4_b2,
+		IN u8 val0x6c4_b3)
+{
+	static u8 pre_h2c_parameter[6] = {0};
+	u8	cur_h2c_parameter[6] = {0};
+	u8 i, match_cnt = 0;
+
+	cur_h2c_parameter[0] = 0x7;	/* op_code, 0x7= wlan toggle slot*/
+
+	cur_h2c_parameter[1] = interval;
+	cur_h2c_parameter[2] = val0x6c4_b0;
+	cur_h2c_parameter[3] = val0x6c4_b1;
+	cur_h2c_parameter[4] = val0x6c4_b2;
+	cur_h2c_parameter[5] = val0x6c4_b3;
+
+	if (!force_exec) {
+		for (i = 1; i <= 5; i++) {
+			if (cur_h2c_parameter[i] != pre_h2c_parameter[i])
+				break;
+
+			match_cnt++;
+		}
+
+		if (match_cnt == 5)
+			return;
+	}
+
+	for (i = 1; i <= 5; i++)
+		pre_h2c_parameter[i] = cur_h2c_parameter[i];
+
+	btcoexist->btc_fill_h2c(btcoexist, 0x69, 6, cur_h2c_parameter);
+}
+
+
+void halbtc8703b1ant_set_coex_table(IN struct btc_coexist *btcoexist,
+	    IN u32 val0x6c0, IN u32 val0x6c4, IN u32 val0x6c8, IN u8 val0x6cc)
+{
+	btcoexist->btc_write_4byte(btcoexist, 0x6c0, val0x6c0);
+
+	btcoexist->btc_write_4byte(btcoexist, 0x6c4, val0x6c4);
+
+	btcoexist->btc_write_4byte(btcoexist, 0x6c8, val0x6c8);
+
+	btcoexist->btc_write_1byte(btcoexist, 0x6cc, val0x6cc);
+}
+
+void halbtc8703b1ant_coex_table(IN struct btc_coexist *btcoexist,
+			IN boolean force_exec, IN u32 val0x6c0, IN u32 val0x6c4,
+				IN u32 val0x6c8, IN u8 val0x6cc)
+{
+	coex_dm->cur_val0x6c0 = val0x6c0;
+	coex_dm->cur_val0x6c4 = val0x6c4;
+	coex_dm->cur_val0x6c8 = val0x6c8;
+	coex_dm->cur_val0x6cc = val0x6cc;
+
+	if (!force_exec) {
+		if ((coex_dm->pre_val0x6c0 == coex_dm->cur_val0x6c0) &&
+		    (coex_dm->pre_val0x6c4 == coex_dm->cur_val0x6c4) &&
+		    (coex_dm->pre_val0x6c8 == coex_dm->cur_val0x6c8) &&
+		    (coex_dm->pre_val0x6cc == coex_dm->cur_val0x6cc))
+			return;
+	}
+	halbtc8703b1ant_set_coex_table(btcoexist, val0x6c0, val0x6c4, val0x6c8,
+				       val0x6cc);
+
+	coex_dm->pre_val0x6c0 = coex_dm->cur_val0x6c0;
+	coex_dm->pre_val0x6c4 = coex_dm->cur_val0x6c4;
+	coex_dm->pre_val0x6c8 = coex_dm->cur_val0x6c8;
+	coex_dm->pre_val0x6cc = coex_dm->cur_val0x6cc;
+}
+
+void halbtc8703b1ant_coex_table_with_type(IN struct btc_coexist *btcoexist,
+		IN boolean force_exec, IN u8 type)
+{
+	u32	break_table;
+	u8	select_table;
+
+	coex_sta->coex_table_type = type;
+
+	if (coex_sta->concurrent_rx_mode_on == true) {
+		break_table = 0xf0ffffff;  /* set WL hi-pri can break BT */
+		select_table =
+			0xb;		/* set Tx response = Hi-Pri (ex: Transmitting ACK,BA,CTS) */
+	} else {
+		break_table = 0xffffff;
+		select_table = 0x3;
+	}
+
+		switch (type) {
+		case 0:
+			halbtc8703b1ant_coex_table(btcoexist, force_exec,
+						   0x55555555, 0x55555555, break_table,
+						   select_table);
+			break;
+		case 1:
+			halbtc8703b1ant_coex_table(btcoexist, force_exec,
+						   0x55555555, 0xaa5a5a5a, break_table,
+						   select_table);
+			break;
+		case 2:
+			halbtc8703b1ant_coex_table(btcoexist, force_exec,
+						   0xaa5a5a5a, 0xaa5a5a5a, break_table,
+						   select_table);
+			break;
+		case 3:
+			halbtc8703b1ant_coex_table(btcoexist, force_exec,
+						   0x55555555, 0x5a5a5a5a, break_table,
+						   select_table);
+			break;
+		case 4:
+			halbtc8703b1ant_coex_table(btcoexist, force_exec,
+						   0xa5555555, 0xaa5a5a5a, break_table,
+						   select_table);
+			break;
+		case 5:
+			halbtc8703b1ant_coex_table(btcoexist, force_exec,
+						   0x5a5a5a5a, 0x5a5a5a5a, break_table,
+						   select_table);
+			break;
+		case 6:
+			halbtc8703b1ant_coex_table(btcoexist, force_exec,
+						   0xa5555555, 0x5a5a5a5a, break_table,
+						   select_table);
+			break;
+		case 7:
+			halbtc8703b1ant_coex_table(btcoexist, force_exec,
+						   0xaa555555, 0xaa555555, break_table,
+						   select_table);
+			break;
+		case 8:
+			halbtc8703b1ant_coex_table(btcoexist, force_exec,
+						   0xa5555555, 0xaaaaaaaa, break_table,
+						   select_table);
+			break;
+		case 9:
+			halbtc8703b1ant_coex_table(btcoexist, force_exec,
+						   0x5a5a5a5a, 0xaaaa5aaa, break_table,
+						   select_table);
+			break;
+		case 10:
+			halbtc8703b1ant_coex_table(btcoexist, force_exec,
+						   0xaaaaaaaa, 0xaaaaaaaa, break_table,
+						   select_table);
+			break;
+		default:
+			break;
+		}
+}
+
+void halbtc8703b1ant_set_fw_ignore_wlan_act(IN struct btc_coexist *btcoexist,
+		IN boolean enable)
+{
+	u8			h2c_parameter[1] = {0};
+
+	if (enable)
+		h2c_parameter[0] |= BIT(0);/* function enable */
+
+	btcoexist->btc_fill_h2c(btcoexist, 0x63, 1, h2c_parameter);
+}
+
+void halbtc8703b1ant_ignore_wlan_act(IN struct btc_coexist *btcoexist,
+				     IN boolean force_exec, IN boolean enable)
+{
+	coex_dm->cur_ignore_wlan_act = enable;
+
+	if (!force_exec) {
+		if (coex_dm->pre_ignore_wlan_act ==
+		    coex_dm->cur_ignore_wlan_act)
+			return;
+	}
+	halbtc8703b1ant_set_fw_ignore_wlan_act(btcoexist, enable);
+
+	coex_dm->pre_ignore_wlan_act = coex_dm->cur_ignore_wlan_act;
+}
+
+void halbtc8703b1ant_set_lps_rpwm(IN struct btc_coexist *btcoexist,
+				  IN u8 lps_val, IN u8 rpwm_val)
+{
+	u8	lps = lps_val;
+	u8	rpwm = rpwm_val;
+
+	btcoexist->btc_set(btcoexist, BTC_SET_U1_LPS_VAL, &lps);
+	btcoexist->btc_set(btcoexist, BTC_SET_U1_RPWM_VAL, &rpwm);
+}
+
+void halbtc8703b1ant_lps_rpwm(IN struct btc_coexist *btcoexist,
+		      IN boolean force_exec, IN u8 lps_val, IN u8 rpwm_val)
+{
+	coex_dm->cur_lps = lps_val;
+	coex_dm->cur_rpwm = rpwm_val;
+
+	if (!force_exec) {
+		if ((coex_dm->pre_lps == coex_dm->cur_lps) &&
+		    (coex_dm->pre_rpwm == coex_dm->cur_rpwm))
+			return;
+	}
+	halbtc8703b1ant_set_lps_rpwm(btcoexist, lps_val, rpwm_val);
+
+	coex_dm->pre_lps = coex_dm->cur_lps;
+	coex_dm->pre_rpwm = coex_dm->cur_rpwm;
+}
+
+void halbtc8703b1ant_ps_tdma_check_for_power_save_state(
+	IN struct btc_coexist *btcoexist, IN boolean new_ps_state)
+{
+	u8	lps_mode = 0x0;
+	u8	h2c_parameter[5] = {0x8, 0, 0, 0, 0};
+
+	btcoexist->btc_get(btcoexist, BTC_GET_U1_LPS_MODE, &lps_mode);
+
+	if (lps_mode) {	/* already under LPS state */
+		if (new_ps_state) {
+			/* keep state under LPS, do nothing. */
+		} else {
+			/* will leave LPS state, turn off psTdma first */
+			/*halbtc8703b1ant_ps_tdma(btcoexist, NORMAL_EXEC, false,
+						8); */
+			btcoexist->btc_fill_h2c(btcoexist, 0x60, 5,
+						h2c_parameter);
+		}
+	} else {					/* NO PS state */
+		if (new_ps_state) {
+			/* will enter LPS state, turn off psTdma first */
+			/*halbtc8703b1ant_ps_tdma(btcoexist, NORMAL_EXEC, false,
+						8);*/
+			btcoexist->btc_fill_h2c(btcoexist, 0x60, 5,
+						h2c_parameter);
+		} else {
+			/* keep state under NO PS state, do nothing. */
+		}
+	}
+}
+
+void halbtc8703b1ant_power_save_state(IN struct btc_coexist *btcoexist,
+			      IN u8 ps_type, IN u8 lps_val, IN u8 rpwm_val)
+{
+	boolean		low_pwr_disable = false;
+
+	switch (ps_type) {
+	case BTC_PS_WIFI_NATIVE:
+		/* recover to original 32k low power setting */
+		coex_sta->force_lps_on = false;
+		low_pwr_disable = false;
+		btcoexist->btc_set(btcoexist,
+				   BTC_SET_ACT_DISABLE_LOW_POWER,
+				   &low_pwr_disable);
+		btcoexist->btc_set(btcoexist, BTC_SET_ACT_NORMAL_LPS,
+				   NULL);
+
+		break;
+	case BTC_PS_LPS_ON:
+		coex_sta->force_lps_on = true;
+		halbtc8703b1ant_ps_tdma_check_for_power_save_state(
+			btcoexist, true);
+		halbtc8703b1ant_lps_rpwm(btcoexist, NORMAL_EXEC,
+					 lps_val, rpwm_val);
+		/* when coex force to enter LPS, do not enter 32k low power. */
+		low_pwr_disable = true;
+		btcoexist->btc_set(btcoexist,
+				   BTC_SET_ACT_DISABLE_LOW_POWER,
+				   &low_pwr_disable);
+		/* power save must executed before psTdma.			 */
+		btcoexist->btc_set(btcoexist, BTC_SET_ACT_ENTER_LPS,
+				   NULL);
+
+		break;
+	case BTC_PS_LPS_OFF:
+		coex_sta->force_lps_on = false;
+		halbtc8703b1ant_ps_tdma_check_for_power_save_state(
+			btcoexist, false);
+		btcoexist->btc_set(btcoexist, BTC_SET_ACT_LEAVE_LPS,
+				   NULL);
+
+		break;
+	default:
+		break;
+	}
+}
+
+
+
+void halbtc8703b1ant_set_fw_pstdma(IN struct btc_coexist *btcoexist,
+	   IN u8 byte1, IN u8 byte2, IN u8 byte3, IN u8 byte4, IN u8 byte5)
+{
+	u8			h2c_parameter[5] = {0};
+	u8			real_byte1 = byte1, real_byte5 = byte5;
+	boolean			ap_enable = false;
+
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_AP_MODE_ENABLE,
+			   &ap_enable);
+
+	if (ap_enable) {
+		if (byte1 & BIT(4) && !(byte1 & BIT(5))) {
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				    "[BTCoex], FW for 1Ant AP mode\n");
+			BTC_TRACE(trace_buf);
+			real_byte1 &= ~BIT(4);
+			real_byte1 |= BIT(5);
+
+			real_byte5 |= BIT(5);
+			real_byte5 &= ~BIT(6);
+
+			halbtc8703b1ant_power_save_state(btcoexist,
+						 BTC_PS_WIFI_NATIVE, 0x0,
+							 0x0);
+		}
+	} else if (byte1 & BIT(4) && !(byte1 & BIT(5))) {
+
+		halbtc8703b1ant_power_save_state(
+			btcoexist, BTC_PS_LPS_ON, 0x50,
+			0x4);
+	} else {
+		halbtc8703b1ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE,
+						 0x0,
+						 0x0);
+	}
+
+
+	h2c_parameter[0] = real_byte1;
+	h2c_parameter[1] = byte2;
+	h2c_parameter[2] = byte3;
+	h2c_parameter[3] = byte4;
+	h2c_parameter[4] = real_byte5;
+
+	coex_dm->ps_tdma_para[0] = real_byte1;
+	coex_dm->ps_tdma_para[1] = byte2;
+	coex_dm->ps_tdma_para[2] = byte3;
+	coex_dm->ps_tdma_para[3] = byte4;
+	coex_dm->ps_tdma_para[4] = real_byte5;
+
+	btcoexist->btc_fill_h2c(btcoexist, 0x60, 5, h2c_parameter);
+}
+
+
+void halbtc8703b1ant_ps_tdma(IN struct btc_coexist *btcoexist,
+		     IN boolean force_exec, IN boolean turn_on, IN u8 type)
+{
+	struct  btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
+	boolean			wifi_busy = false;
+	u8			rssi_adjust_val = 0;
+	static u8			psTdmaByte4Modify = 0x0, pre_psTdmaByte4Modify = 0x0;
+	static boolean	 pre_wifi_busy = false;
+
+	coex_dm->cur_ps_tdma_on = turn_on;
+	coex_dm->cur_ps_tdma = type;
+
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy);
+
+	if (wifi_busy != pre_wifi_busy) {
+		force_exec = true;
+		pre_wifi_busy = wifi_busy;
+	}
+
+	/* 0x778 = 0x1 at wifi slot (no blocking BT Low-Pri pkts) */
+	if ((bt_link_info->slave_role) && (bt_link_info->a2dp_exist))
+		psTdmaByte4Modify = 0x1;
+	else
+		psTdmaByte4Modify = 0x0;
+
+	if (pre_psTdmaByte4Modify != psTdmaByte4Modify) {
+
+		force_exec = true;
+		pre_psTdmaByte4Modify = psTdmaByte4Modify;
+	}
+
+	if (!force_exec) {
+		if ((coex_dm->pre_ps_tdma_on == coex_dm->cur_ps_tdma_on) &&
+		    (coex_dm->pre_ps_tdma == coex_dm->cur_ps_tdma))
+			return;
+	}
+
+	if (coex_dm->cur_ps_tdma_on) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], ********** TDMA(on, %d) **********\n",
+			    coex_dm->cur_ps_tdma);
+		BTC_TRACE(trace_buf);
+	} else {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], ********** TDMA(off, %d) **********\n",
+			    coex_dm->cur_ps_tdma);
+		BTC_TRACE(trace_buf);
+	}
+
+	if (turn_on)	{
+
+		btcoexist->btc_write_1byte_bitmask(btcoexist, 0x550, 0x8,
+					   0x1);  /* enable TBTT nterrupt */
+	}
+
+
+	if (turn_on) {
+		switch (type) {
+		default:
+			halbtc8703b1ant_set_fw_pstdma(btcoexist,
+							0x61, 0x35, 0x03, 0x11, 0x11);
+			break;
+
+		case 3:
+			halbtc8703b1ant_set_fw_pstdma(btcoexist,
+							0x51, 0x3a, 0x03, 0x10, 0x50);
+			break;
+		case 4:
+			halbtc8703b1ant_set_fw_pstdma(btcoexist,
+							0x51, 0x21, 0x03, 0x10, 0x50);
+			break;
+		case 5:
+			halbtc8703b1ant_set_fw_pstdma(btcoexist,
+							0x61, 0x15, 0x03, 0x11, 0x11);
+			break;
+		case 6:
+			halbtc8703b1ant_set_fw_pstdma(btcoexist,
+							0x61, 0x20, 0x03, 0x11, 0x11);
+			break;
+		case 7:
+			halbtc8703b1ant_set_fw_pstdma(btcoexist,
+							0x51, 0x10, 0x03, 0x10,  0x54 |
+							psTdmaByte4Modify);
+			break;
+		case 8:
+			halbtc8703b1ant_set_fw_pstdma(btcoexist,
+							0x51, 0x10, 0x03, 0x10,  0x54 |
+							psTdmaByte4Modify);
+			break;
+		case 9:
+			halbtc8703b1ant_set_fw_pstdma(btcoexist,
+							0x55, 0x10, 0x03, 0x10,  0x54 |
+							psTdmaByte4Modify);
+			break;
+		case 10:
+			halbtc8703b1ant_set_fw_pstdma(btcoexist,
+							0x61, 0x30, 0x03, 0x11, 0x10);
+			break;
+		case 11:
+			halbtc8703b1ant_set_fw_pstdma(btcoexist,
+							0x65, 0x25, 0x03, 0x11,  0x11 |
+							psTdmaByte4Modify);
+			break;
+		case 12:
+			halbtc8703b1ant_set_fw_pstdma(btcoexist,
+							0x55, 0x30, 0x03, 0x10,  0x50 |
+							psTdmaByte4Modify);
+			break;
+		case 13:
+			halbtc8703b1ant_set_fw_pstdma(btcoexist,
+							0x51, 0x25, 0x03, 0x10,  0x50 |
+							psTdmaByte4Modify);
+			break;
+		case 14:
+			halbtc8703b1ant_set_fw_pstdma(btcoexist,
+							0x51, 0x15, 0x03, 0x10,  0x50 |
+							psTdmaByte4Modify);
+			break;
+		case 15:
+			halbtc8703b1ant_set_fw_pstdma(btcoexist,
+							0x51, 0x20, 0x03, 0x10,  0x50 |
+							psTdmaByte4Modify);
+			break;
+		case 16:
+			halbtc8703b1ant_set_fw_pstdma(btcoexist,
+							0x61, 0x10, 0x03, 0x11,  0x15 |
+							psTdmaByte4Modify);
+			break;
+		case 17:
+			halbtc8703b1ant_set_fw_pstdma(btcoexist,
+							0x61, 0x10, 0x03, 0x11, 0x14);
+			break;
+		case 18:
+			halbtc8703b1ant_set_fw_pstdma(btcoexist,
+							0x51, 0x30, 0x03, 0x10,  0x50 |
+							psTdmaByte4Modify);
+			break;
+		case 19:
+			halbtc8703b1ant_set_fw_pstdma(btcoexist,
+							0x61, 0x15, 0x03, 0x11, 0x10);
+			break;
+		case 20:
+			halbtc8703b1ant_set_fw_pstdma(btcoexist,
+							0x61, 0x30, 0x03, 0x11, 0x10);
+			break;
+		case 21:
+			halbtc8703b1ant_set_fw_pstdma(btcoexist,
+							0x61, 0x30, 0x03, 0x11, 0x10);
+			break;
+		case 22:
+			halbtc8703b1ant_set_fw_pstdma(btcoexist,
+							0x61, 0x25, 0x03, 0x11, 0x10);
+			break;
+		case 27:
+			halbtc8703b1ant_set_fw_pstdma(btcoexist,
+							0x61, 0x10, 0x03, 0x11, 0x15);
+			break;
+		case 32:
+			halbtc8703b1ant_set_fw_pstdma(btcoexist,
+							0x61, 0x35, 0x03, 0x11, 0x11);
+			break;
+		case 33:
+			halbtc8703b1ant_set_fw_pstdma(btcoexist,
+							0x61, 0x35, 0x03, 0x11, 0x10);
+			break;
+		case 57:
+			halbtc8703b1ant_set_fw_pstdma(btcoexist,
+							0x51, 0x10, 0x03, 0x10,  0x50 |
+							psTdmaByte4Modify);
+			break;
+		case 58:
+			halbtc8703b1ant_set_fw_pstdma(btcoexist,
+							0x51, 0x10, 0x03, 0x10,  0x50 |
+							psTdmaByte4Modify);
+			break;
+		case 67:
+			halbtc8703b1ant_set_fw_pstdma(btcoexist,
+							0x61, 0x10, 0x03, 0x11,  0x10 |
+							psTdmaByte4Modify);
+			break;
+		}
+	} else {
+
+		/* disable PS tdma */
+		switch (type) {
+		case 8: /* PTA Control */
+			halbtc8703b1ant_set_fw_pstdma(btcoexist, 0x8,
+							0x0, 0x0, 0x0, 0x0);
+			break;
+		case 0:
+		default:  /* Software control, Antenna at BT side */
+			halbtc8703b1ant_set_fw_pstdma(btcoexist, 0x0,
+							0x0, 0x0, 0x0, 0x0);
+			break;
+		case 1: /* 2-Ant, 0x778=3, antenna control by antenna diversity */
+			halbtc8703b1ant_set_fw_pstdma(btcoexist, 0x0,
+							0x0, 0x0, 0x48, 0x0);
+			break;
+		}
+	}
+
+	/* update pre state */
+	coex_dm->pre_ps_tdma_on = coex_dm->cur_ps_tdma_on;
+	coex_dm->pre_ps_tdma = coex_dm->cur_ps_tdma;
+}
+
+void halbtc8703b1ant_set_ant_path(IN struct btc_coexist *btcoexist,
+				  IN u8 ant_pos_type, IN boolean force_exec,
+				  IN u8 phase)
+{
+	u32	cnt_bt_cal_chk = 0;
+	boolean	is_in_mp_mode = false;
+	u8	u8tmp = 0;
+	u32	u32tmp1 = 0, u32tmp2 = 0;
+
+
+	u32tmp1 = halbtc8703b1ant_ltecoex_indirect_read_reg(btcoexist,
+				0x38);
+
+	/* To avoid indirect access fail	*/
+	if (((u32tmp1 & 0xf000) >> 12) != ((u32tmp1 & 0x0f00) >> 8)) {
+		force_exec = true;
+		coex_sta->gnt_error_cnt++;
+	}
+
+#if 1
+	u32tmp2 = halbtc8703b1ant_ltecoex_indirect_read_reg(btcoexist,
+			0x54);
+	u8tmp  = btcoexist->btc_read_1byte(btcoexist, 0x73);
+
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+		"[BTCoex], ********** (Before Ant Setup) 0x73 = 0x%x, 0x38= 0x%x, 0x54= 0x%x**********\n",
+		    u8tmp, u32tmp1, u32tmp2);
+	BTC_TRACE(trace_buf);
+#endif
+
+	coex_dm->cur_ant_pos_type = ant_pos_type;
+
+	if (!force_exec) {
+		if (coex_dm->cur_ant_pos_type == coex_dm->pre_ant_pos_type) {
+
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				"[BTCoex], ********** Skip Antenna Path Setup because no change!!**********\n");
+			BTC_TRACE(trace_buf);
+			return;
+		}
+	}
+
+	coex_dm->pre_ant_pos_type = coex_dm->cur_ant_pos_type;
+
+	switch (phase) {
+	case BT_8703B_1ANT_PHASE_COEX_INIT:
+		/* Disable LTE Coex Function in WiFi side (this should be on if LTE coex is required) */
+		halbtc8703b1ant_ltecoex_enable(btcoexist, 0x0);
+
+		/* GNT_WL_LTE always = 1 (this should be config if LTE coex is required) */
+		halbtc8703b1ant_ltecoex_set_coex_table(
+			btcoexist,
+			BT_8703B_1ANT_CTT_WL_VS_LTE,
+			0xffff);
+
+		/* GNT_BT_LTE always = 1 (this should be config if LTE coex is required) */
+		halbtc8703b1ant_ltecoex_set_coex_table(
+			btcoexist,
+			BT_8703B_1ANT_CTT_BT_VS_LTE,
+			0xffff);
+
+		/* Wait If BT IQK running, because Path control owner is at BT during BT IQK (setup by WiFi firmware) */
+		while (cnt_bt_cal_chk <= 20) {
+			u8tmp = btcoexist->btc_read_1byte(
+					btcoexist,
+					0x49d);
+			cnt_bt_cal_chk++;
+			if (u8tmp & BIT(0)) {
+				BTC_SPRINTF(trace_buf,
+					    BT_TMP_BUF_SIZE,
+					"[BTCoex], ########### BT is calibrating (wait cnt=%d) ###########\n",
+					    cnt_bt_cal_chk);
+				BTC_TRACE(trace_buf);
+				delay_ms(50);
+			} else {
+				BTC_SPRINTF(trace_buf,
+					    BT_TMP_BUF_SIZE,
+					"[BTCoex], ********** BT is NOT calibrating (wait cnt=%d)**********\n",
+					    cnt_bt_cal_chk);
+				BTC_TRACE(trace_buf);
+				break;
+			}
+		}
+
+
+		/* set Path control owner to WL at initial step */
+		halbtc8703b1ant_ltecoex_pathcontrol_owner(
+			btcoexist,
+			BT_8703B_1ANT_PCO_WLSIDE);
+
+		/* set GNT_BT to SW high */
+		halbtc8703b1ant_ltecoex_set_gnt_bt(btcoexist,
+					   BT_8703B_1ANT_GNT_BLOCK_RFC_BB,
+					   BT_8703B_1ANT_GNT_TYPE_CTRL_BY_SW,
+					   BT_8703B_1ANT_SIG_STA_SET_TO_HIGH);
+		/* Set GNT_WL to SW low */
+		halbtc8703b1ant_ltecoex_set_gnt_wl(btcoexist,
+					   BT_8703B_1ANT_GNT_BLOCK_RFC_BB,
+					   BT_8703B_1ANT_GNT_TYPE_CTRL_BY_SW,
+					   BT_8703B_1ANT_SIG_STA_SET_TO_LOW);
+
+		if (BTC_ANT_PATH_AUTO == ant_pos_type)
+			ant_pos_type = BTC_ANT_PATH_BT;
+
+		coex_sta->run_time_state = false;
+		break;
+	case BT_8703B_1ANT_PHASE_WLANONLY_INIT:
+		/* Disable LTE Coex Function in WiFi side (this should be on if LTE coex is required) */
+		halbtc8703b1ant_ltecoex_enable(btcoexist, 0x0);
+
+		/* GNT_WL_LTE always = 1 (this should be config if LTE coex is required) */
+		halbtc8703b1ant_ltecoex_set_coex_table(
+			btcoexist,
+			BT_8703B_1ANT_CTT_WL_VS_LTE,
+			0xffff);
+
+		/* GNT_BT_LTE always = 1 (this should be config if LTE coex is required) */
+		halbtc8703b1ant_ltecoex_set_coex_table(
+			btcoexist,
+			BT_8703B_1ANT_CTT_BT_VS_LTE,
+			0xffff);
+
+		/* set Path control owner to WL at initial step */
+		halbtc8703b1ant_ltecoex_pathcontrol_owner(
+			btcoexist,
+			BT_8703B_1ANT_PCO_WLSIDE);
+
+		/* set GNT_BT to SW low */
+		halbtc8703b1ant_ltecoex_set_gnt_bt(btcoexist,
+					   BT_8703B_1ANT_GNT_BLOCK_RFC_BB,
+					   BT_8703B_1ANT_GNT_TYPE_CTRL_BY_SW,
+					   BT_8703B_1ANT_SIG_STA_SET_TO_LOW);
+		/* Set GNT_WL to SW high */
+		halbtc8703b1ant_ltecoex_set_gnt_wl(btcoexist,
+					   BT_8703B_1ANT_GNT_BLOCK_RFC_BB,
+					   BT_8703B_1ANT_GNT_TYPE_CTRL_BY_SW,
+					   BT_8703B_1ANT_SIG_STA_SET_TO_HIGH);
+
+		if (BTC_ANT_PATH_AUTO == ant_pos_type)
+			ant_pos_type =
+				BTC_ANT_PATH_WIFI;
+
+		coex_sta->run_time_state = false;
+		break;
+	case BT_8703B_1ANT_PHASE_WLAN_OFF:
+		/* Disable LTE Coex Function in WiFi side */
+		halbtc8703b1ant_ltecoex_enable(btcoexist, 0x0);
+
+		/* set Path control owner to BT */
+		halbtc8703b1ant_ltecoex_pathcontrol_owner(
+			btcoexist,
+			BT_8703B_1ANT_PCO_BTSIDE);
+
+		if (BTC_ANT_PATH_AUTO == ant_pos_type)
+			ant_pos_type = BTC_ANT_PATH_BT;
+
+		coex_sta->run_time_state = false;
+		break;
+	case BT_8703B_1ANT_PHASE_2G_RUNTIME:
+		halbtc8703b1ant_ltecoex_pathcontrol_owner(
+			btcoexist,
+			BT_8703B_1ANT_PCO_WLSIDE);
+
+		/* set GNT_BT to PTA */
+		halbtc8703b1ant_ltecoex_set_gnt_bt(btcoexist,
+					   BT_8703B_1ANT_GNT_BLOCK_RFC_BB,
+					   BT_8703B_1ANT_GNT_TYPE_CTRL_BY_PTA,
+					   BT_8703B_1ANT_SIG_STA_SET_BY_HW);
+		/* Set GNT_WL to PTA */
+		halbtc8703b1ant_ltecoex_set_gnt_wl(btcoexist,
+					   BT_8703B_1ANT_GNT_BLOCK_RFC_BB,
+					   BT_8703B_1ANT_GNT_TYPE_CTRL_BY_PTA,
+					   BT_8703B_1ANT_SIG_STA_SET_BY_HW);
+
+		if (BTC_ANT_PATH_AUTO == ant_pos_type)
+			ant_pos_type = BTC_ANT_PATH_PTA;
+
+		coex_sta->run_time_state = true;
+		break;
+	case BT_8703B_1ANT_PHASE_BTMPMODE:
+		halbtc8703b1ant_ltecoex_pathcontrol_owner(
+			btcoexist,
+			BT_8703B_1ANT_PCO_WLSIDE);
+
+		/* set GNT_BT to high */
+		halbtc8703b1ant_ltecoex_set_gnt_bt(btcoexist,
+					   BT_8703B_1ANT_GNT_BLOCK_RFC_BB,
+					   BT_8703B_1ANT_GNT_TYPE_CTRL_BY_SW,
+					   BT_8703B_1ANT_SIG_STA_SET_TO_HIGH);
+		/* Set GNT_WL to low */
+		halbtc8703b1ant_ltecoex_set_gnt_wl(btcoexist,
+					   BT_8703B_1ANT_GNT_BLOCK_RFC_BB,
+					   BT_8703B_1ANT_GNT_TYPE_CTRL_BY_SW,
+					   BT_8703B_1ANT_SIG_STA_SET_TO_LOW);
+
+		if (BTC_ANT_PATH_AUTO == ant_pos_type)
+			ant_pos_type = BTC_ANT_PATH_BT;
+
+		coex_sta->run_time_state = false;
+		break;
+	}
+
+
+#if 1
+	u32tmp1 = halbtc8703b1ant_ltecoex_indirect_read_reg(btcoexist, 0x38);
+	u32tmp2 = halbtc8703b1ant_ltecoex_indirect_read_reg(btcoexist, 0x54);
+	u8tmp  = btcoexist->btc_read_1byte(btcoexist, 0x73);
+
+
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+		"[BTCoex], ********** (After Ant-Setup) 0x73 = 0x%x, 0x38= 0x%x, 0x54= 0x%x**********\n",
+		    u8tmp, u32tmp1, u32tmp2);
+	BTC_TRACE(trace_buf);
+
+#endif
+}
+
+
+boolean halbtc8703b1ant_is_common_action(IN struct btc_coexist *btcoexist)
+{
+	boolean			common = false, wifi_connected = false, wifi_busy = false;
+
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED,
+			   &wifi_connected);
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy);
+
+	if (!wifi_connected &&
+	    BT_8703B_1ANT_BT_STATUS_NON_CONNECTED_IDLE ==
+	    coex_dm->bt_status) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			"[BTCoex], Wifi non connected-idle + BT non connected-idle!!\n");
+		BTC_TRACE(trace_buf);
+		common = true;
+	} else if (wifi_connected &&
+		   (BT_8703B_1ANT_BT_STATUS_NON_CONNECTED_IDLE ==
+		    coex_dm->bt_status)) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			"[BTCoex], Wifi connected + BT non connected-idle!!\n");
+		BTC_TRACE(trace_buf);
+		common = true;
+	} else if (!wifi_connected &&
+		   (BT_8703B_1ANT_BT_STATUS_CONNECTED_IDLE ==
+		    coex_dm->bt_status)) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			"[BTCoex], Wifi non connected-idle + BT connected-idle!!\n");
+		BTC_TRACE(trace_buf);
+		common = true;
+	} else if (wifi_connected &&
+		   (BT_8703B_1ANT_BT_STATUS_CONNECTED_IDLE ==
+		    coex_dm->bt_status)) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], Wifi connected + BT connected-idle!!\n");
+		BTC_TRACE(trace_buf);
+		common = true;
+	} else if (!wifi_connected &&
+		   (BT_8703B_1ANT_BT_STATUS_CONNECTED_IDLE !=
+		    coex_dm->bt_status)) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], Wifi non connected-idle + BT Busy!!\n");
+		BTC_TRACE(trace_buf);
+		common = true;
+	} else {
+		if (wifi_busy) {
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				"[BTCoex], Wifi Connected-Busy + BT Busy!!\n");
+			BTC_TRACE(trace_buf);
+		} else {
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				"[BTCoex], Wifi Connected-Idle + BT Busy!!\n");
+			BTC_TRACE(trace_buf);
+		}
+
+		common = false;
+	}
+
+	return common;
+}
+
+
+/* *********************************************
+ *
+ *	Non-Software Coex Mechanism start
+ *
+ * ********************************************* */
+u8 halbtc8703b1ant_action_algorithm(IN struct btc_coexist *btcoexist)
+{
+	struct  btc_bt_link_info	*bt_link_info = &btcoexist->bt_link_info;
+	boolean	bt_hs_on = false;
+	u8	algorithm = BT_8703B_1ANT_COEX_ALGO_UNDEFINED;
+	u8	num_of_diff_profile = 0;
+
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on);
+
+	if (!bt_link_info->bt_link_exist) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], No BT link exists!!!\n");
+		BTC_TRACE(trace_buf);
+		return algorithm;
+	}
+
+	if (bt_link_info->sco_exist)
+		num_of_diff_profile++;
+	if (bt_link_info->hid_exist)
+		num_of_diff_profile++;
+	if (bt_link_info->pan_exist)
+		num_of_diff_profile++;
+	if (bt_link_info->a2dp_exist)
+		num_of_diff_profile++;
+
+	if (num_of_diff_profile == 1) {
+		if (bt_link_info->sco_exist) {
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				    "[BTCoex], BT Profile = SCO only\n");
+			BTC_TRACE(trace_buf);
+			algorithm = BT_8703B_1ANT_COEX_ALGO_SCO;
+		} else {
+			if (bt_link_info->hid_exist) {
+				BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+					"[BTCoex], BT Profile = HID only\n");
+				BTC_TRACE(trace_buf);
+				algorithm = BT_8703B_1ANT_COEX_ALGO_HID;
+			} else if (bt_link_info->a2dp_exist) {
+				BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+					"[BTCoex], BT Profile = A2DP only\n");
+				BTC_TRACE(trace_buf);
+				algorithm = BT_8703B_1ANT_COEX_ALGO_A2DP;
+			} else if (bt_link_info->pan_exist) {
+				if (bt_hs_on) {
+					BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+						"[BTCoex], BT Profile = PAN(HS) only\n");
+					BTC_TRACE(trace_buf);
+					algorithm =
+						BT_8703B_1ANT_COEX_ALGO_PANHS;
+				} else {
+					BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+						"[BTCoex], BT Profile = PAN(EDR) only\n");
+					BTC_TRACE(trace_buf);
+					algorithm =
+						BT_8703B_1ANT_COEX_ALGO_PANEDR;
+				}
+			}
+		}
+	} else if (num_of_diff_profile == 2) {
+		if (bt_link_info->sco_exist) {
+			if (bt_link_info->hid_exist) {
+				BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+					"[BTCoex], BT Profile = SCO + HID\n");
+				BTC_TRACE(trace_buf);
+				algorithm = BT_8703B_1ANT_COEX_ALGO_HID;
+			} else if (bt_link_info->a2dp_exist) {
+				BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+					"[BTCoex], BT Profile = SCO + A2DP ==> SCO\n");
+				BTC_TRACE(trace_buf);
+				algorithm = BT_8703B_1ANT_COEX_ALGO_SCO;
+			} else if (bt_link_info->pan_exist) {
+				if (bt_hs_on) {
+					BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+						"[BTCoex], BT Profile = SCO + PAN(HS)\n");
+					BTC_TRACE(trace_buf);
+					algorithm = BT_8703B_1ANT_COEX_ALGO_SCO;
+				} else {
+					BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+						"[BTCoex], BT Profile = SCO + PAN(EDR)\n");
+					BTC_TRACE(trace_buf);
+					algorithm =
+						BT_8703B_1ANT_COEX_ALGO_PANEDR_HID;
+				}
+			}
+		} else {
+			if (bt_link_info->hid_exist &&
+			    bt_link_info->a2dp_exist) {
+				BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+					"[BTCoex], BT Profile = HID + A2DP\n");
+				BTC_TRACE(trace_buf);
+				algorithm = BT_8703B_1ANT_COEX_ALGO_HID_A2DP;
+			} else if (bt_link_info->hid_exist &&
+				   bt_link_info->pan_exist) {
+				if (bt_hs_on) {
+					BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+						"[BTCoex], BT Profile = HID + PAN(HS)\n");
+					BTC_TRACE(trace_buf);
+					algorithm =
+						BT_8703B_1ANT_COEX_ALGO_HID_A2DP;
+				} else {
+					BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+						"[BTCoex], BT Profile = HID + PAN(EDR)\n");
+					BTC_TRACE(trace_buf);
+					algorithm =
+						BT_8703B_1ANT_COEX_ALGO_PANEDR_HID;
+				}
+			} else if (bt_link_info->pan_exist &&
+				   bt_link_info->a2dp_exist) {
+				if (bt_hs_on) {
+					BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+						"[BTCoex], BT Profile = A2DP + PAN(HS)\n");
+					BTC_TRACE(trace_buf);
+					algorithm =
+						BT_8703B_1ANT_COEX_ALGO_A2DP_PANHS;
+				} else {
+					BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+						"[BTCoex], BT Profile = A2DP + PAN(EDR)\n");
+					BTC_TRACE(trace_buf);
+					algorithm =
+						BT_8703B_1ANT_COEX_ALGO_PANEDR_A2DP;
+				}
+			}
+		}
+	} else if (num_of_diff_profile == 3) {
+		if (bt_link_info->sco_exist) {
+			if (bt_link_info->hid_exist &&
+			    bt_link_info->a2dp_exist) {
+				BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+					"[BTCoex], BT Profile = SCO + HID + A2DP ==> HID\n");
+				BTC_TRACE(trace_buf);
+				algorithm = BT_8703B_1ANT_COEX_ALGO_HID;
+			} else if (bt_link_info->hid_exist &&
+				   bt_link_info->pan_exist) {
+				if (bt_hs_on) {
+					BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+						"[BTCoex], BT Profile = SCO + HID + PAN(HS)\n");
+					BTC_TRACE(trace_buf);
+					algorithm =
+						BT_8703B_1ANT_COEX_ALGO_HID_A2DP;
+				} else {
+					BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+						"[BTCoex], BT Profile = SCO + HID + PAN(EDR)\n");
+					BTC_TRACE(trace_buf);
+					algorithm =
+						BT_8703B_1ANT_COEX_ALGO_PANEDR_HID;
+				}
+			} else if (bt_link_info->pan_exist &&
+				   bt_link_info->a2dp_exist) {
+				if (bt_hs_on) {
+					BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+						"[BTCoex], BT Profile = SCO + A2DP + PAN(HS)\n");
+					BTC_TRACE(trace_buf);
+					algorithm = BT_8703B_1ANT_COEX_ALGO_SCO;
+				} else {
+					BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+						"[BTCoex], BT Profile = SCO + A2DP + PAN(EDR) ==> HID\n");
+					BTC_TRACE(trace_buf);
+					algorithm =
+						BT_8703B_1ANT_COEX_ALGO_PANEDR_HID;
+				}
+			}
+		} else {
+			if (bt_link_info->hid_exist &&
+			    bt_link_info->pan_exist &&
+			    bt_link_info->a2dp_exist) {
+				if (bt_hs_on) {
+					BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+						"[BTCoex], BT Profile = HID + A2DP + PAN(HS)\n");
+					BTC_TRACE(trace_buf);
+					algorithm =
+						BT_8703B_1ANT_COEX_ALGO_HID_A2DP;
+				} else {
+					BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+						"[BTCoex], BT Profile = HID + A2DP + PAN(EDR)\n");
+					BTC_TRACE(trace_buf);
+					algorithm =
+						BT_8703B_1ANT_COEX_ALGO_HID_A2DP_PANEDR;
+				}
+			}
+		}
+	} else if (num_of_diff_profile >= 3) {
+		if (bt_link_info->sco_exist) {
+			if (bt_link_info->hid_exist &&
+			    bt_link_info->pan_exist &&
+			    bt_link_info->a2dp_exist) {
+				if (bt_hs_on) {
+					BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+						"[BTCoex], Error!!! BT Profile = SCO + HID + A2DP + PAN(HS)\n");
+					BTC_TRACE(trace_buf);
+
+				} else {
+					BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+						"[BTCoex], BT Profile = SCO + HID + A2DP + PAN(EDR)==>PAN(EDR)+HID\n");
+					BTC_TRACE(trace_buf);
+					algorithm =
+						BT_8703B_1ANT_COEX_ALGO_PANEDR_HID;
+				}
+			}
+		}
+	}
+
+	return algorithm;
+}
+
+void halbtc8703b1ant_action_bt_whql_test(IN struct btc_coexist *btcoexist)
+{
+	halbtc8703b1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 8);
+	halbtc8703b1ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, NORMAL_EXEC,
+				     BT_8703B_1ANT_PHASE_2G_RUNTIME);
+	halbtc8703b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0);
+}
+
+void halbtc8703b1ant_action_bt_hs(IN struct btc_coexist *btcoexist)
+{
+	halbtc8703b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 5);
+	halbtc8703b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 2);
+}
+
+void halbtc8703b1ant_action_bt_relink(IN struct btc_coexist *btcoexist)
+{
+	halbtc8703b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 5);
+	halbtc8703b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 1);
+}
+
+void halbtc8703b1ant_action_bt_idle(IN struct btc_coexist *btcoexist)
+{
+	boolean wifi_busy = false;
+
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy);
+
+	if (!wifi_busy) {
+		halbtc8703b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true,
+							6);
+		halbtc8703b1ant_coex_table_with_type(btcoexist,
+							NORMAL_EXEC, 3);
+	} else {/* if wl busy */
+
+	if (BT_8703B_1ANT_BT_STATUS_NON_CONNECTED_IDLE ==
+			coex_dm->bt_status) {
+
+		if (coex_sta->is_hiPri_rx_overhead)
+			halbtc8703b1ant_coex_table_with_type(btcoexist,
+								NORMAL_EXEC, 7);
+		else
+			halbtc8703b1ant_coex_table_with_type(btcoexist,
+								NORMAL_EXEC, 8);
+
+		halbtc8703b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true,
+							33);
+	} else {
+
+	   halbtc8703b1ant_coex_table_with_type(btcoexist,
+							     NORMAL_EXEC, 8);
+	   halbtc8703b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true,
+							32);
+	  }
+	}
+}
+
+void halbtc8703b1ant_action_bt_inquiry(IN struct btc_coexist *btcoexist)
+{
+	struct  btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
+	boolean			wifi_connected = false, ap_enable = false, wifi_busy = false,
+				bt_busy = false;
+	boolean	wifi_scan = false, wifi_link = false, wifi_roam = false;
+
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_AP_MODE_ENABLE,
+			   &ap_enable);
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED,
+			   &wifi_connected);
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy);
+	btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_TRAFFIC_BUSY, &bt_busy);
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_SCAN, &wifi_scan);
+
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_LINK, &wifi_link);
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_ROAM, &wifi_roam);
+
+	if ((wifi_link) || (wifi_roam)  || (coex_sta->wifi_is_high_pri_task)) {
+
+		halbtc8703b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 33);
+		halbtc8703b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 1);
+
+	} else if (((wifi_scan) || (wifi_busy)) &&
+		   (coex_sta->bt_create_connection)) {
+
+		halbtc8703b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 33);
+		halbtc8703b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 1);
+
+	} else if ((!wifi_connected) && (!wifi_scan)) {
+
+		halbtc8703b1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 8);
+		halbtc8703b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0);
+	}  else if ((bt_link_info->sco_exist) || (bt_link_info->hid_exist)) {
+
+		halbtc8703b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 6);
+		halbtc8703b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 5);
+	} else if ((bt_link_info->a2dp_exist) && (bt_link_info->pan_exist)) {
+
+		halbtc8703b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 22);
+		halbtc8703b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4);
+
+	} else if (bt_link_info->a2dp_exist) {
+
+		halbtc8703b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 32);
+
+		halbtc8703b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4);
+	} else if (wifi_scan) {
+
+		halbtc8703b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 20);
+
+		halbtc8703b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4);
+
+	} else if (wifi_busy) {
+		halbtc8703b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 21);
+
+		halbtc8703b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4);
+	} else {
+		halbtc8703b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 21);
+
+		halbtc8703b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4);
+	}
+}
+
+void halbtc8703b1ant_action_bt_sco_hid_only_busy(IN struct btc_coexist
+		*btcoexist)
+{
+	struct  btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
+	boolean	wifi_connected = false, wifi_busy = false;
+	u32  wifi_bw = 1;
+
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED,
+			   &wifi_connected);
+
+	btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW,
+			   &wifi_bw);
+
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy);
+
+
+	if (bt_link_info->sco_exist) {
+			halbtc8703b1ant_ps_tdma(btcoexist, NORMAL_EXEC,	true, 5);
+			halbtc8703b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 5);
+		} else if (coex_sta->hid_busy_num >= 2) {/*for 4/18 hid */
+		/* if 11bg mode */
+		if (wifi_bw == 0) {
+
+			halbtc8703b1ant_coex_table_with_type(btcoexist,
+								NORMAL_EXEC, 6);
+			halbtc8703b1ant_set_wltoggle_coex_table(btcoexist,
+								NORMAL_EXEC,
+								0x1, 0xaa,
+								0x5a, 0xaa,
+								0xaa);
+			halbtc8703b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 11);
+		} else {
+
+		if (wifi_busy) {
+
+			halbtc8703b1ant_coex_table_with_type(btcoexist,
+								NORMAL_EXEC, 6);
+			halbtc8703b1ant_set_wltoggle_coex_table(btcoexist,
+								NORMAL_EXEC,
+								0x2, 0xaa,
+								0x5a, 0xaa,
+								0xaa);
+		     halbtc8703b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 11);
+		  } else {
+
+			halbtc8703b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 6);
+			halbtc8703b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 3);
+		  }
+		}
+	} else {
+			halbtc8703b1ant_ps_tdma(btcoexist, NORMAL_EXEC,
+						true, 6);
+			halbtc8703b1ant_coex_table_with_type(btcoexist,
+							     NORMAL_EXEC, 3);
+		}
+}
+
+
+void halbtc8703b1ant_action_wifi_only(IN struct btc_coexist *btcoexist)
+{
+	halbtc8703b1ant_ps_tdma(btcoexist, FORCE_EXEC, false, 8);
+	halbtc8703b1ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, FORCE_EXEC,
+				     BT_8703B_1ANT_PHASE_2G_RUNTIME);
+	halbtc8703b1ant_coex_table_with_type(btcoexist, FORCE_EXEC, 10);
+}
+
+void halbtc8703b1ant_action_wifi_multi_port(IN struct btc_coexist *btcoexist)
+{
+	struct  btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
+
+	halbtc8703b1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 8);
+	halbtc8703b1ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, NORMAL_EXEC,
+				     BT_8703B_1ANT_PHASE_2G_RUNTIME);
+
+	if ((BT_8703B_1ANT_BT_STATUS_NON_CONNECTED_IDLE ==
+		coex_dm->bt_status) ||
+		(BT_8703B_1ANT_BT_STATUS_CONNECTED_IDLE ==
+		coex_dm->bt_status))
+		halbtc8703b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 7);
+	else if (!bt_link_info->pan_exist)
+		halbtc8703b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0);
+	else
+		halbtc8703b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 2);
+}
+
+void halbtc8703b1ant_action_wifi_linkscan_process(IN struct btc_coexist
+		*btcoexist)
+{
+	struct  btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
+
+	if (bt_link_info->pan_exist) {
+
+		halbtc8703b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 22);
+
+		halbtc8703b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4);
+
+	} else if (bt_link_info->a2dp_exist) {
+
+		halbtc8703b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 27);
+
+		halbtc8703b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4);
+	} else {
+
+		halbtc8703b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 21);
+
+		halbtc8703b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4);
+	}
+}
+
+void halbtc8703b1ant_action_wifi_connected_bt_acl_busy(IN struct btc_coexist
+		*btcoexist)
+{
+	struct	btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
+	boolean	wifi_busy = false, wifi_turbo = false;
+
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy);
+	btcoexist->btc_get(btcoexist, BTC_GET_U1_AP_NUM,
+				&coex_sta->scan_ap_num);
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			"############# [BTCoex],  scan_ap_num = %d, wl_noisy_level = %d\n",
+			coex_sta->scan_ap_num, coex_sta->wl_noisy_level);
+	BTC_TRACE(trace_buf);
+
+#if 1
+	if ((wifi_busy) && (coex_sta->wl_noisy_level == 0))
+		wifi_turbo = true;
+#endif
+
+	if (bt_link_info->a2dp_only) { /* A2DP		 */
+		if (!wifi_busy) {
+			/*halbtc8703b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true,
+						32);*/
+			halbtc8703b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true,
+						27);
+			halbtc8703b1ant_coex_table_with_type(btcoexist,
+								 NORMAL_EXEC, 4);
+		} else {
+
+			if (coex_sta->wl_noisy_level == 2)
+				halbtc8703b1ant_ps_tdma(btcoexist,
+							NORMAL_EXEC, true, 17);
+			else
+				halbtc8703b1ant_ps_tdma(btcoexist,
+							NORMAL_EXEC, true, 7);
+
+			if (wifi_turbo)
+				halbtc8703b1ant_coex_table_with_type(btcoexist,
+								 NORMAL_EXEC, 8);
+			else
+				halbtc8703b1ant_coex_table_with_type(btcoexist,
+								 NORMAL_EXEC, 4);
+		}
+	} else if (((bt_link_info->a2dp_exist) &&
+			(bt_link_info->pan_exist)) ||
+		   (bt_link_info->hid_exist && bt_link_info->a2dp_exist &&
+		bt_link_info->pan_exist)) { /* A2DP+PAN(OPP,FTP), HID+A2DP+PAN(OPP,FTP) */
+
+		if ((bt_link_info->hid_exist) && (coex_sta->hid_busy_num >= 2)) {
+			halbtc8703b1ant_coex_table_with_type(btcoexist,
+								 NORMAL_EXEC, 6);
+			halbtc8703b1ant_set_wltoggle_coex_table(btcoexist,
+								NORMAL_EXEC,
+								0x2, 0xaa,
+								0x5a, 0xaa,
+									0xaa);
+			halbtc8703b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true,
+							12);
+		} else if (wifi_busy)	{
+			if (((coex_sta->a2dp_bit_pool > 40) &&
+				 (coex_sta->a2dp_bit_pool < 255)) ||
+				(!coex_sta->is_A2DP_3M))
+				halbtc8703b1ant_ps_tdma(btcoexist, NORMAL_EXEC,
+							true, 15);
+			else if (wifi_turbo)
+				halbtc8703b1ant_ps_tdma(btcoexist, NORMAL_EXEC,
+							true, 18);
+			else
+				halbtc8703b1ant_ps_tdma(btcoexist, NORMAL_EXEC,
+							true, 13);
+		} else
+			halbtc8703b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true,
+						14);
+
+		if (bt_link_info->hid_exist)
+			halbtc8703b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 1);
+		else if (wifi_turbo)
+			halbtc8703b1ant_coex_table_with_type(btcoexist,
+								NORMAL_EXEC, 8);
+		else
+			halbtc8703b1ant_coex_table_with_type(btcoexist,
+								NORMAL_EXEC, 4);
+	} else if (bt_link_info->hid_exist &&
+					bt_link_info->a2dp_exist) {/* HID+A2DP */
+
+			if ((wifi_busy) && (coex_sta->hid_busy_num >= 2)) { /*for 4/18 hid */
+				halbtc8703b1ant_coex_table_with_type(btcoexist,
+								NORMAL_EXEC, 6);
+				halbtc8703b1ant_set_wltoggle_coex_table(btcoexist,
+								NORMAL_EXEC,
+								0x2, 0xaa,
+								0x5a, 0xaa,
+								0xaa);
+				halbtc8703b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true,
+							9);
+			} else {
+				halbtc8703b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true,
+							8);
+				halbtc8703b1ant_coex_table_with_type(btcoexist,
+							NORMAL_EXEC, 1);
+			}
+
+	} else if ((bt_link_info->pan_only)
+					|| (bt_link_info->hid_exist && bt_link_info->pan_exist)) {
+			/* PAN(OPP,FTP), HID+PAN(OPP,FTP) */
+
+		if ((bt_link_info->hid_exist) && (bt_link_info->pan_exist) &&
+				(coex_sta->hid_busy_num >= 2)) {
+
+				halbtc8703b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 6);
+				halbtc8703b1ant_set_wltoggle_coex_table(btcoexist,
+								NORMAL_EXEC,
+								0x2, 0xaa,
+								0x5a, 0xaa,
+								0xaa);
+				halbtc8703b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true,
+							12);
+		} else {
+
+			if (!wifi_busy)
+				halbtc8703b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true,
+							4);
+			else
+				halbtc8703b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true,
+							3);
+
+			if (bt_link_info->hid_exist)
+				halbtc8703b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 1);
+			else if (wifi_turbo)
+				halbtc8703b1ant_coex_table_with_type(btcoexist,
+									 NORMAL_EXEC, 8);
+			else
+				halbtc8703b1ant_coex_table_with_type(btcoexist,
+									 NORMAL_EXEC, 4);
+		}
+	} else {
+		/* BT no-profile busy (0x9) */
+		halbtc8703b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 33);
+		halbtc8703b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4);
+	}
+}
+
+void halbtc8703b1ant_action_wifi_not_connected(IN struct btc_coexist *btcoexist)
+{
+	/* tdma and coex table */
+	halbtc8703b1ant_ps_tdma(btcoexist, FORCE_EXEC, false, 8);
+	halbtc8703b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0);
+}
+
+void halbtc8703b1ant_action_wifi_connected(IN struct btc_coexist *btcoexist)
+{
+	struct	btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
+	boolean wifi_busy = false;
+
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			"[BTCoex], CoexForWifiConnect()===>\n");
+	BTC_TRACE(trace_buf);
+
+	halbtc8703b1ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO,
+					NORMAL_EXEC,
+					BT_8703B_1ANT_PHASE_2G_RUNTIME);
+
+	if (BT_8703B_1ANT_BT_STATUS_ACL_BUSY == coex_dm->bt_status) {
+
+		if (bt_link_info->hid_only)/* HID only */
+			halbtc8703b1ant_action_bt_sco_hid_only_busy(btcoexist);
+		else
+			halbtc8703b1ant_action_wifi_connected_bt_acl_busy(btcoexist);
+
+	} else if ((BT_8703B_1ANT_BT_STATUS_SCO_BUSY ==
+				coex_dm->bt_status) ||
+			   (BT_8703B_1ANT_BT_STATUS_ACL_SCO_BUSY ==
+				coex_dm->bt_status)) {
+			halbtc8703b1ant_action_bt_sco_hid_only_busy(btcoexist);
+	} else
+		halbtc8703b1ant_action_bt_idle(btcoexist);
+}
+
+
+void halbtc8703b1ant_run_sw_coexist_mechanism(IN struct btc_coexist *btcoexist)
+{
+	u8	algorithm = 0;
+
+	algorithm = halbtc8703b1ant_action_algorithm(btcoexist);
+	coex_dm->cur_algorithm = algorithm;
+
+	if (halbtc8703b1ant_is_common_action(btcoexist)) {
+
+	} else {
+		switch (coex_dm->cur_algorithm) {
+		case BT_8703B_1ANT_COEX_ALGO_SCO:
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				    "[BTCoex], Action algorithm = SCO.\n");
+			BTC_TRACE(trace_buf);
+			break;
+		case BT_8703B_1ANT_COEX_ALGO_HID:
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				    "[BTCoex], Action algorithm = HID.\n");
+			BTC_TRACE(trace_buf);
+			break;
+		case BT_8703B_1ANT_COEX_ALGO_A2DP:
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				    "[BTCoex], Action algorithm = A2DP.\n");
+			BTC_TRACE(trace_buf);
+			break;
+		case BT_8703B_1ANT_COEX_ALGO_A2DP_PANHS:
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				"[BTCoex], Action algorithm = A2DP+PAN(HS).\n");
+			BTC_TRACE(trace_buf);
+			break;
+		case BT_8703B_1ANT_COEX_ALGO_PANEDR:
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				    "[BTCoex], Action algorithm = PAN(EDR).\n");
+			BTC_TRACE(trace_buf);
+			break;
+		case BT_8703B_1ANT_COEX_ALGO_PANHS:
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				    "[BTCoex], Action algorithm = HS mode.\n");
+			BTC_TRACE(trace_buf);
+			break;
+		case BT_8703B_1ANT_COEX_ALGO_PANEDR_A2DP:
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				    "[BTCoex], Action algorithm = PAN+A2DP.\n");
+			BTC_TRACE(trace_buf);
+			break;
+		case BT_8703B_1ANT_COEX_ALGO_PANEDR_HID:
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				"[BTCoex], Action algorithm = PAN(EDR)+HID.\n");
+			BTC_TRACE(trace_buf);
+			break;
+		case BT_8703B_1ANT_COEX_ALGO_HID_A2DP_PANEDR:
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				"[BTCoex], Action algorithm = HID+A2DP+PAN.\n");
+			BTC_TRACE(trace_buf);
+			break;
+		case BT_8703B_1ANT_COEX_ALGO_HID_A2DP:
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				    "[BTCoex], Action algorithm = HID+A2DP.\n");
+			BTC_TRACE(trace_buf);
+			break;
+		default:
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				"[BTCoex], Action algorithm = coexist All Off!!\n");
+			BTC_TRACE(trace_buf);
+			break;
+		}
+		coex_dm->pre_algorithm = coex_dm->cur_algorithm;
+	}
+}
+
+void halbtc8703b1ant_run_coexist_mechanism(IN struct btc_coexist *btcoexist)
+{
+	struct	btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
+	boolean wifi_connected = false, bt_hs_on = false;
+	boolean increase_scan_dev_num = false;
+	boolean bt_ctrl_agg_buf_size = false;
+	boolean miracast_plus_bt = false, wifi_under_5g = false;
+	u8	agg_buf_size = 5;
+	u32 wifi_link_status = 0;
+	u32 num_of_wifi_link = 0, wifi_bw;
+	u8	iot_peer = BTC_IOT_PEER_UNKNOWN;
+	boolean scan = false, link = false, roam = false, under_4way = false;
+
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			"[BTCoex], RunCoexistMechanism()===>\n");
+	BTC_TRACE(trace_buf);
+
+	if (btcoexist->manual_control) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			"[BTCoex], RunCoexistMechanism(), return for Manual CTRL <===\n");
+		BTC_TRACE(trace_buf);
+		return;
+	}
+
+	if (btcoexist->stop_coex_dm) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			"[BTCoex], RunCoexistMechanism(), return for Stop Coex DM <===\n");
+		BTC_TRACE(trace_buf);
+		return;
+	}
+
+	if (coex_sta->under_ips) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				"[BTCoex], wifi is under IPS !!!\n");
+		BTC_TRACE(trace_buf);
+		return;
+	}
+
+	if (!coex_sta->run_time_state) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			"[BTCoex], return for run_time_state = false !!!\n");
+		BTC_TRACE(trace_buf);
+		return;
+	}
+
+	if (coex_sta->freeze_coexrun_by_btinfo) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			"[BTCoex], BtInfoNotify(), return for freeze_coexrun_by_btinfo\n");
+		BTC_TRACE(trace_buf);
+		return;
+	}
+
+	if (coex_sta->bt_whck_test) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				"[BTCoex], BT is under WHCK TEST!!!\n");
+		BTC_TRACE(trace_buf);
+		halbtc8703b1ant_action_bt_whql_test(btcoexist);
+		return;
+	}
+
+	if (coex_sta->bt_disabled) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				"[BTCoex], BT is disabled !!!\n");
+		halbtc8703b1ant_action_wifi_only(btcoexist);
+		return;
+	}
+
+	if (coex_sta->c2h_bt_inquiry_page) {
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+					"[BTCoex], BT is under inquiry/page scan !!\n");
+			BTC_TRACE(trace_buf);
+			halbtc8703b1ant_action_bt_inquiry(btcoexist);
+			return;
+	}
+
+	if (coex_sta->is_setupLink) {
+		 BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+		 "[BTCoex], BT is re-link !!!\n");
+		 halbtc8703b1ant_action_bt_relink(btcoexist);
+		 return;
+	}
+
+	if ((BT_8703B_1ANT_BT_STATUS_ACL_BUSY == coex_dm->bt_status) ||
+		(BT_8703B_1ANT_BT_STATUS_SCO_BUSY == coex_dm->bt_status) ||
+		(BT_8703B_1ANT_BT_STATUS_ACL_SCO_BUSY == coex_dm->bt_status))
+		increase_scan_dev_num = true;
+
+	btcoexist->btc_set(btcoexist, BTC_SET_BL_INC_SCAN_DEV_NUM,
+				&increase_scan_dev_num);
+
+	btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_LINK_STATUS,
+				&wifi_link_status);
+
+	num_of_wifi_link = wifi_link_status >> 16;
+
+	if ((num_of_wifi_link >= 2) ||
+		(wifi_link_status & WIFI_P2P_GO_CONNECTED)) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			"############# [BTCoex],  Multi-Port num_of_wifi_link = %d, wifi_link_status = 0x%x\n",
+				num_of_wifi_link, wifi_link_status);
+		BTC_TRACE(trace_buf);
+
+		if (bt_link_info->bt_link_exist)
+			miracast_plus_bt = true;
+		else
+			miracast_plus_bt = false;
+
+		btcoexist->btc_set(btcoexist, BTC_SET_BL_MIRACAST_PLUS_BT,
+				   &miracast_plus_bt);
+
+		halbtc8703b1ant_limited_rx(btcoexist, NORMAL_EXEC, false,
+					false, 0x5);
+
+		halbtc8703b1ant_action_wifi_multi_port(btcoexist);
+
+		return;
+	} else {
+
+	miracast_plus_bt = false;
+	btcoexist->btc_set(btcoexist, BTC_SET_BL_MIRACAST_PLUS_BT,
+				&miracast_plus_bt);
+	}
+
+	btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw);
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, &wifi_connected);
+
+	if ((bt_link_info->bt_link_exist) && (wifi_connected)) {
+
+		btcoexist->btc_get(btcoexist, BTC_GET_U1_IOT_PEER, &iot_peer);
+
+		if (BTC_IOT_PEER_CISCO == iot_peer) {
+
+			if (BTC_WIFI_BW_HT40 == wifi_bw)
+					halbtc8703b1ant_limited_rx(btcoexist,
+						NORMAL_EXEC, false, true, 0x10);
+			else
+					halbtc8703b1ant_limited_rx(btcoexist,
+						NORMAL_EXEC, false, true, 0x8);
+		}  else
+				halbtc8703b1ant_limited_rx(btcoexist, NORMAL_EXEC, false, false,
+						0x5);
+	}
+
+	halbtc8703b1ant_run_sw_coexist_mechanism(
+			btcoexist);  /* just print debug message */
+
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on);
+
+	if (bt_hs_on) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				"############# [BTCoex],  BT Is hs\n");
+		BTC_TRACE(trace_buf);
+		halbtc8703b1ant_action_bt_hs(btcoexist);
+		return;
+	}
+
+	if ((BT_8703B_1ANT_BT_STATUS_NON_CONNECTED_IDLE ==
+			coex_dm->bt_status) ||
+		(BT_8703B_1ANT_BT_STATUS_CONNECTED_IDLE ==
+			coex_dm->bt_status)) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				"############# [BTCoex],  BT Is idle\n");
+		BTC_TRACE(trace_buf);
+		halbtc8703b1ant_action_bt_idle(btcoexist);
+		return;
+	}
+
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_SCAN, &scan);
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_LINK, &link);
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_ROAM, &roam);
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_4_WAY_PROGRESS,
+			&under_4way);
+
+	if (scan || link || roam || under_4way) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			"[BTCoex], scan = %d, link = %d, roam = %d 4way = %d!!!\n",
+					scan, link, roam, under_4way);
+		BTC_TRACE(trace_buf);
+
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			"[BTCoex], wifi is under linkscan process!!\n");
+		BTC_TRACE(trace_buf);
+
+		halbtc8703b1ant_action_wifi_linkscan_process(btcoexist);
+	} else if (wifi_connected) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			"[BTCoex], wifi is under connected!!\n");
+		BTC_TRACE(trace_buf);
+
+		halbtc8703b1ant_action_wifi_connected(btcoexist);
+	} else {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			"[BTCoex], wifi is under not-connected!!\n");
+		BTC_TRACE(trace_buf);
+
+		halbtc8703b1ant_action_wifi_not_connected(btcoexist);
+	 }
+}
+
+
+void halbtc8703b1ant_init_coex_dm(IN struct btc_coexist *btcoexist)
+{
+	/* force to reset coex mechanism */
+
+	halbtc8703b1ant_low_penalty_ra(btcoexist, NORMAL_EXEC, false);
+
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+		    "[BTCoex], Coex Mechanism Init!!\n");
+	BTC_TRACE(trace_buf);
+
+	coex_sta->pop_event_cnt = 0;
+	coex_sta->cnt_RemoteNameReq = 0;
+	coex_sta->cnt_ReInit = 0;
+	coex_sta->cnt_setupLink = 0;
+	coex_sta->cnt_IgnWlanAct = 0;
+	coex_sta->cnt_Page = 0;
+}
+
+void halbtc8703b1ant_init_hw_config(IN struct btc_coexist *btcoexist,
+				    IN boolean back_up, IN boolean wifi_only)
+{
+	u32				u32tmp0 = 0, u32tmp1 = 0, u32tmp2 = 0;
+
+	u32tmp0 = btcoexist->btc_read_4byte(btcoexist, 0x70),
+	u32tmp1 = halbtc8703b1ant_ltecoex_indirect_read_reg(btcoexist, 0x38);
+	u32tmp2 = halbtc8703b1ant_ltecoex_indirect_read_reg(btcoexist, 0x54);
+
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+		"\n [BTCoex], ********** 0x70/ 0x38/ 0x54 (Before Init HW config) = 0x%x/ 0x%x/ 0x%x**********\n",
+		    u32tmp0,
+		    u32tmp1, u32tmp2);
+	BTC_TRACE(trace_buf);
+
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+		    "[BTCoex], 1Ant Init HW Config!!\n");
+	BTC_TRACE(trace_buf);
+
+	coex_sta->bt_coex_supported_feature = 0;
+	coex_sta->bt_coex_supported_version = 0;
+	coex_sta->bt_ble_scan_type = 0;
+	coex_sta->bt_ble_scan_para[0] = 0;
+	coex_sta->bt_ble_scan_para[1] = 0;
+	coex_sta->bt_ble_scan_para[2] = 0;
+	coex_sta->gnt_error_cnt = 0;
+
+
+	/* 0xf0[15:12] --> Chip Cut information */
+	coex_sta->cut_version = (btcoexist->btc_read_1byte(btcoexist,
+				 0xf1) & 0xf0) >> 4;
+
+	btcoexist->btc_write_1byte_bitmask(btcoexist, 0x550, 0x8,
+					   0x1);  /* enable TBTT nterrupt */
+
+	/* BT report packet sample rate	 */
+	btcoexist->btc_write_1byte(btcoexist, 0x790, 0x5);
+
+	/* Enable BT counter statistics */
+	btcoexist->btc_write_1byte(btcoexist, 0x778, 0x1);
+
+	/* Enable PTA (3-wire function form BT side) */
+	btcoexist->btc_write_1byte_bitmask(btcoexist, 0x40, 0x20, 0x1);
+	btcoexist->btc_write_1byte_bitmask(btcoexist, 0x41, 0x02, 0x1);
+
+	/* Enable PTA (tx/rx signal form WiFi side) */
+	btcoexist->btc_write_1byte_bitmask(btcoexist, 0x4c6, 0x10, 0x1);
+
+	halbtc8703b1ant_enable_gnt_to_gpio(btcoexist, false);
+
+#if 0
+	if (btcoexist->btc_read_1byte(btcoexist, 0x80) == 0xc6)
+		halbtc8703b1ant_post_state_to_bt(btcoexist,
+					 BT_8703B_1ANT_SCOREBOARD_ONOFF, true);
+#endif
+
+	halbtc8703b1ant_ps_tdma(btcoexist, FORCE_EXEC, false, 8);
+
+	/* Antenna config */
+	if (wifi_only) {
+		coex_sta->concurrent_rx_mode_on = false;
+		halbtc8703b1ant_set_ant_path(btcoexist, BTC_ANT_PATH_WIFI,
+					     FORCE_EXEC,
+					     BT_8703B_1ANT_PHASE_WLANONLY_INIT);
+	} else {
+		coex_sta->concurrent_rx_mode_on = true;
+		btcoexist->btc_write_1byte_bitmask(btcoexist, 0x953, 0x2, 0x1);
+		/* RF 0x1[0] = 0->Set GNT_WL_RF_Rx always = 1 for con-current Rx */
+		btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1, 0x1, 0x0);
+		halbtc8703b1ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO,
+					     FORCE_EXEC,
+					     BT_8703B_1ANT_PHASE_COEX_INIT);
+	}
+
+	/* PTA parameter */
+	halbtc8703b1ant_coex_table_with_type(btcoexist, FORCE_EXEC, 0);
+
+	u32tmp0 = btcoexist->btc_read_4byte(btcoexist, 0x70),
+	u32tmp1 = halbtc8703b1ant_ltecoex_indirect_read_reg(btcoexist, 0x38);
+	u32tmp2 = halbtc8703b1ant_ltecoex_indirect_read_reg(btcoexist, 0x54);
+
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+		"[BTCoex], ********** 0x70/ 0x38/ 0x54 (After Init HW config) = 0x%x/ 0x%x/ 0x%x**********\n",
+		    u32tmp0,
+		    u32tmp1, u32tmp2);
+	BTC_TRACE(trace_buf);
+
+}
+
+
+
+/* ************************************************************
+ * work around function start with wa_halbtc8703b1ant_
+ * ************************************************************
+ * ************************************************************
+ * extern function start with ex_halbtc8703b1ant_
+ * ************************************************************ */
+void ex_halbtc8703b1ant_power_on_setting(IN struct btc_coexist *btcoexist)
+{
+	struct  btc_board_info	*board_info = &btcoexist->board_info;
+	u8 u8tmp = 0x0;
+	u16 u16tmp = 0x0;
+
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+		"xxxxxxxxxxxxxxxx Execute 8703b 1-Ant PowerOn Setting xxxxxxxxxxxxxxxx!!\n");
+	BTC_TRACE(trace_buf);
+
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+		    "Ant Det Finish = %s, Ant Det Number  = %d\n",
+		    (board_info->btdm_ant_det_finish ? "Yes" : "No"),
+		    board_info->btdm_ant_num_by_ant_det);
+	BTC_TRACE(trace_buf);
+
+	btcoexist->stop_coex_dm = true;
+
+	/* enable BB, REG_SYS_FUNC_EN such that we can write BB/MAC reg correctly. */
+	u16tmp = btcoexist->btc_read_2byte(btcoexist, 0x2);
+	btcoexist->btc_write_2byte(btcoexist, 0x2, u16tmp | BIT(0) | BIT(1));
+
+	/* set Path control owner to WiFi */
+	halbtc8703b1ant_ltecoex_pathcontrol_owner(btcoexist,
+			BT_8703B_1ANT_PCO_WLSIDE);
+
+	/* set GNT_BT to high */
+	halbtc8703b1ant_ltecoex_set_gnt_bt(btcoexist,
+					   BT_8703B_1ANT_GNT_BLOCK_RFC_BB,
+					   BT_8703B_1ANT_GNT_TYPE_CTRL_BY_SW,
+					   BT_8703B_1ANT_SIG_STA_SET_TO_HIGH);
+	/* Set GNT_WL to low */
+	halbtc8703b1ant_ltecoex_set_gnt_wl(btcoexist,
+					   BT_8703B_1ANT_GNT_BLOCK_RFC_BB,
+					   BT_8703B_1ANT_GNT_TYPE_CTRL_BY_SW,
+					   BT_8703B_1ANT_SIG_STA_SET_TO_LOW);
+
+	/* set WLAN_ACT = 0 */
+	btcoexist->btc_write_1byte(btcoexist, 0x76e, 0x4);
+
+	halbtc8703b1ant_enable_gnt_to_gpio(btcoexist, false);
+
+	/* */
+	/* S0 or S1 setting and Local register setting(By the setting fw can get ant number, S0/S1, ... info) */
+	/* Local setting bit define */
+	/*	BIT0: "0" for no antenna inverse; "1" for antenna inverse  */
+	/*	BIT1: "0" for internal switch; "1" for external switch */
+	/*	BIT2: "0" for one antenna; "1" for two antenna */
+	/* NOTE: here default all internal switch and 1-antenna ==> BIT1=0 and BIT2=0 */
+
+	u8tmp = 0;
+	board_info->btdm_ant_pos = BTC_ANTENNA_AT_MAIN_PORT;
+
+	if (btcoexist->chip_interface == BTC_INTF_USB)
+		btcoexist->btc_write_local_reg_1byte(btcoexist, 0xfe08, u8tmp);
+	else if (btcoexist->chip_interface == BTC_INTF_SDIO)
+		btcoexist->btc_write_local_reg_1byte(btcoexist, 0x60, u8tmp);
+
+
+
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+		"[BTCoex], **********  0x70(MAC)/0x38/0x54 (Power-On) =0x%x/  0x%x/ 0x%x**********\n",
+		    btcoexist->btc_read_4byte(btcoexist, 0x70),
+		    halbtc8703b1ant_ltecoex_indirect_read_reg(btcoexist, 0x38),
+		    halbtc8703b1ant_ltecoex_indirect_read_reg(btcoexist, 0x54));
+	BTC_TRACE(trace_buf);
+
+
+}
+
+void ex_halbtc8703b1ant_pre_load_firmware(IN struct btc_coexist *btcoexist)
+{
+}
+
+void ex_halbtc8703b1ant_init_hw_config(IN struct btc_coexist *btcoexist,
+				       IN boolean wifi_only)
+{
+	halbtc8703b1ant_init_hw_config(btcoexist, true, wifi_only);
+	btcoexist->stop_coex_dm = false;
+}
+
+void ex_halbtc8703b1ant_init_coex_dm(IN struct btc_coexist *btcoexist)
+{
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+		    "[BTCoex], Coex Mechanism Init!!\n");
+	BTC_TRACE(trace_buf);
+
+	halbtc8703b1ant_init_coex_dm(btcoexist);
+}
+
+void ex_halbtc8703b1ant_display_coex_info(IN struct btc_coexist *btcoexist)
+{
+	struct  btc_board_info		*board_info = &btcoexist->board_info;
+	struct  btc_stack_info		*stack_info = &btcoexist->stack_info;
+	struct  btc_bt_link_info	*bt_link_info = &btcoexist->bt_link_info;
+	u8				*cli_buf = btcoexist->cli_buf;
+	u8				u8tmp[4], i, bt_info_ext, ps_tdma_case = 0;
+	u16				u16tmp[4];
+	u32				u32tmp[4];
+	u32				fa_ofdm, fa_cck, cca_ofdm, cca_cck;
+	u32				fw_ver = 0, bt_patch_ver = 0, bt_coex_ver = 0;
+	static u8			pop_report_in_10s = 0;
+	u32			phyver = 0;
+	boolean			lte_coex_on = false;
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+		   "\r\n ============[BT Coexist info]============");
+	CL_PRINTF(cli_buf);
+
+	if (btcoexist->manual_control) {
+		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+			"\r\n ============[Under Manual Control]============");
+		CL_PRINTF(cli_buf);
+		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+			   "\r\n ==========================================");
+		CL_PRINTF(cli_buf);
+	}
+	if (btcoexist->stop_coex_dm) {
+		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+			   "\r\n ============[Coex is STOPPED]============");
+		CL_PRINTF(cli_buf);
+		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+			   "\r\n ==========================================");
+		CL_PRINTF(cli_buf);
+	}
+
+	if (!coex_sta->bt_disabled) {
+		if (coex_sta->bt_coex_supported_feature == 0)
+			btcoexist->btc_get(btcoexist, BTC_GET_U4_SUPPORTED_FEATURE,
+						&coex_sta->bt_coex_supported_feature);
+
+		if ((coex_sta->bt_coex_supported_version == 0) ||
+			 (coex_sta->bt_coex_supported_version == 0xffff))
+			btcoexist->btc_get(btcoexist, BTC_GET_U4_SUPPORTED_VERSION,
+						&coex_sta->bt_coex_supported_version);
+
+		btcoexist->btc_get(btcoexist, BTC_GET_U4_BT_PATCH_VER, &bt_patch_ver);
+		btcoexist->bt_info.bt_get_fw_ver = bt_patch_ver;
+	}
+
+	if (psd_scan->ant_det_try_count == 0) {
+		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d",
+			   "Ant PG Num/ Mech/ Pos",
+			   board_info->pg_ant_num, board_info->btdm_ant_num,
+			   board_info->btdm_ant_pos);
+		CL_PRINTF(cli_buf);
+	} else {
+		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+			   "\r\n %-35s = %d/ %d/ %d  (%d/%d/%d)",
+			   "Ant PG Num/ Mech(Ant_Det)/ Pos",
+			   board_info->pg_ant_num,
+			   board_info->btdm_ant_num_by_ant_det,
+			   board_info->btdm_ant_pos,
+			   psd_scan->ant_det_try_count,
+			   psd_scan->ant_det_fail_count,
+			   psd_scan->ant_det_result);
+		CL_PRINTF(cli_buf);
+
+		if (board_info->btdm_ant_det_finish) {
+			CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s",
+				   "Ant Det PSD Value",
+				   psd_scan->ant_det_peak_val);
+			CL_PRINTF(cli_buf);
+		}
+	}
+
+
+	/*bt_patch_ver = btcoexist->bt_info.bt_get_fw_ver;*/
+	bt_patch_ver = btcoexist->bt_info.bt_get_fw_ver;
+	btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_FW_VER, &fw_ver);
+	phyver = btcoexist->btc_get_bt_phydm_version(btcoexist);
+
+	bt_coex_ver = ((coex_sta->bt_coex_supported_version & 0xff00) >> 8);
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+		   "\r\n %-35s = %d_%02x/ 0x%02x/ 0x%02x (%s)",
+		   "CoexVer WL/  BT_Desired/ BT_Report",
+		   glcoex_ver_date_8703b_1ant, glcoex_ver_8703b_1ant,
+		   glcoex_ver_btdesired_8703b_1ant,
+		   bt_coex_ver,
+		   (bt_coex_ver == 0xff ? "Unknown" :
+		   (bt_coex_ver >= glcoex_ver_btdesired_8703b_1ant ?
+		      "Match":"Mis-Match")));
+	CL_PRINTF(cli_buf);
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+		   "\r\n %-35s = 0x%x/ 0x%x/ v%d/ %c",
+		   "W_FW/ B_FW/ Phy/ Kt",
+		   fw_ver, bt_patch_ver, phyver,
+		   coex_sta->cut_version + 65);
+	CL_PRINTF(cli_buf);
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %02x %02x %02x ",
+		   "Wifi channel informed to BT",
+		   coex_dm->wifi_chnl_info[0], coex_dm->wifi_chnl_info[1],
+		   coex_dm->wifi_chnl_info[2]);
+	CL_PRINTF(cli_buf);
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s/ %s/ %s",
+		   "WifibHiPri/ Ccklock/ CckEverLock",
+		   (coex_sta->wifi_is_high_pri_task ? "Yes" : "No"),
+		   (coex_sta->cck_lock ? "Yes" : "No"),
+		   (coex_sta->cck_ever_lock ? "Yes" : "No"));
+	CL_PRINTF(cli_buf);
+
+	/* wifi status */
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s",
+		   "============[Wifi Status]============");
+	CL_PRINTF(cli_buf);
+	btcoexist->btc_disp_dbg_msg(btcoexist, BTC_DBG_DISP_WIFI_STATUS);
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s",
+		   "============[BT Status]============");
+	CL_PRINTF(cli_buf);
+
+	pop_report_in_10s++;
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = [%s/ %d/ %d/ %d] ",
+		   "BT [status/ rssi/ retryCnt/ popCnt]",
+		   ((coex_sta->bt_disabled) ? ("disabled") :	((
+			   coex_sta->c2h_bt_inquiry_page) ? ("inquiry/page")
+			   : ((BT_8703B_1ANT_BT_STATUS_NON_CONNECTED_IDLE ==
+			       coex_dm->bt_status) ? "non-connected idle" :
+		((BT_8703B_1ANT_BT_STATUS_CONNECTED_IDLE == coex_dm->bt_status)
+				       ? "connected-idle" : "busy")))),
+		   coex_sta->bt_rssi - 100, coex_sta->bt_retry_cnt,
+		   coex_sta->pop_event_cnt);
+	CL_PRINTF(cli_buf);
+
+	if (pop_report_in_10s >= 5) {
+		coex_sta->pop_event_cnt = 0;
+		pop_report_in_10s = 0;
+	}
+
+	if (coex_sta->num_of_profile != 0)
+		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+			   "\r\n %-35s = %s%s%s%s%s",
+			   "Profiles",
+			   ((bt_link_info->a2dp_exist) ? "A2DP," : ""),
+			   ((bt_link_info->sco_exist) ?  "SCO," : ""),
+			   ((bt_link_info->hid_exist) ?
+			    ((coex_sta->hid_busy_num >= 2) ? "HID(4/18)," :
+			     "HID(2/18),") : ""),
+			   ((bt_link_info->pan_exist) ?  "PAN," : ""),
+			   ((coex_sta->voice_over_HOGP) ? "Voice" : ""));
+	else
+		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+			   "\r\n %-35s = None",
+			   "Profiles");
+
+	CL_PRINTF(cli_buf);
+
+	if (bt_link_info->a2dp_exist) {
+		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s/ %d/ %s",
+			   "A2DP Rate/Bitpool/Auto_Slot",
+			   ((coex_sta->is_A2DP_3M) ? "3M" : "No_3M"),
+			   coex_sta->a2dp_bit_pool,
+			   ((coex_sta->is_autoslot) ? "On" : "Off")
+			  );
+		CL_PRINTF(cli_buf);
+	}
+
+	if (bt_link_info->hid_exist) {
+		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d",
+			   "HID PairNum/Forbid_Slot",
+			   coex_sta->hid_pair_cnt,
+			   coex_sta->forbidden_slot
+			  );
+		CL_PRINTF(cli_buf);
+	}
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s / %s/ 0x%x",
+		   "Role/IgnWlanAct/Feature",
+		   ((bt_link_info->slave_role) ? "Slave" : "Master"),
+		   ((coex_dm->cur_ignore_wlan_act) ? "Yes" : "No"),
+		   coex_sta->bt_coex_supported_feature);
+	CL_PRINTF(cli_buf);
+
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d/ %d/ %d",
+		   "ReInit/ReLink/IgnWlact/Page/NameReq",
+		   coex_sta->cnt_ReInit,
+		   coex_sta->cnt_setupLink,
+		   coex_sta->cnt_IgnWlanAct,
+		   coex_sta->cnt_Page,
+		   coex_sta->cnt_RemoteNameReq
+		  );
+	CL_PRINTF(cli_buf);
+
+	halbtc8703b1ant_read_score_board(btcoexist, &u16tmp[0]);
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %04x",
+		   "ScoreBoard[14:0] (from BT)", u16tmp[0]);
+	CL_PRINTF(cli_buf);
+
+
+	for (i = 0; i < BT_INFO_SRC_8703B_1ANT_MAX; i++) {
+		if (coex_sta->bt_info_c2h_cnt[i]) {
+			CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+				"\r\n %-35s = %02x %02x %02x %02x %02x %02x %02x(%d)",
+				   glbt_info_src_8703b_1ant[i],
+				   coex_sta->bt_info_c2h[i][0],
+				   coex_sta->bt_info_c2h[i][1],
+				   coex_sta->bt_info_c2h[i][2],
+				   coex_sta->bt_info_c2h[i][3],
+				   coex_sta->bt_info_c2h[i][4],
+				   coex_sta->bt_info_c2h[i][5],
+				   coex_sta->bt_info_c2h[i][6],
+				   coex_sta->bt_info_c2h_cnt[i]);
+			CL_PRINTF(cli_buf);
+		}
+	}
+
+	if (btcoexist->manual_control)
+		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s",
+			"============[mechanisms] (before Manual)============");
+	else
+		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s",
+			   "============[mechanisms]============");
+	CL_PRINTF(cli_buf);
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d",
+		   "SM[LowPenaltyRA]",
+		   coex_dm->cur_low_penalty_ra);
+	CL_PRINTF(cli_buf);
+
+	ps_tdma_case = coex_dm->cur_ps_tdma;
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+		   "\r\n %-35s = %02x %02x %02x %02x %02x case-%d (%s,%s)",
+		   "PS TDMA",
+		   coex_dm->ps_tdma_para[0], coex_dm->ps_tdma_para[1],
+		   coex_dm->ps_tdma_para[2], coex_dm->ps_tdma_para[3],
+		   coex_dm->ps_tdma_para[4], ps_tdma_case,
+		   (coex_dm->cur_ps_tdma_on ? "On" : "Off"),
+		   (coex_dm->auto_tdma_adjust ? "Adj" : "Fix"));
+
+	CL_PRINTF(cli_buf);
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d",
+		   "WL/BT Coex Table Type",
+		   coex_sta->coex_table_type);
+	CL_PRINTF(cli_buf);
+
+	u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x6c0);
+	u32tmp[1] = btcoexist->btc_read_4byte(btcoexist, 0x6c4);
+	u32tmp[2] = btcoexist->btc_read_4byte(btcoexist, 0x6c8);
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+		   "\r\n %-35s = 0x%x/ 0x%x/ 0x%x",
+		   "0x6c0/0x6c4/0x6c8(coexTable)",
+		   u32tmp[0], u32tmp[1], u32tmp[2]);
+	CL_PRINTF(cli_buf);
+
+	u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x778);
+	u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x6cc);
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+		   "\r\n %-35s = 0x%x/ 0x%x/ 0x%x",
+		   "0x778/0x6cc/IgnWlanAct",
+		   u8tmp[0], u32tmp[0],  coex_dm->cur_ignore_wlan_act);
+	CL_PRINTF(cli_buf);
+
+	u32tmp[0] = halbtc8703b1ant_ltecoex_indirect_read_reg(btcoexist, 0x38);
+	lte_coex_on = ((u32tmp[0] & BIT(7)) >> 7) ?  true : false;
+
+	if (lte_coex_on) {
+		u32tmp[0] = halbtc8703b1ant_ltecoex_indirect_read_reg(btcoexist,
+				0xa0);
+		u32tmp[1] = halbtc8703b1ant_ltecoex_indirect_read_reg(btcoexist,
+				0xa4);
+
+		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x",
+			   "LTE Coex Table W_L/B_L",
+			   u32tmp[0] & 0xffff, u32tmp[1] & 0xffff);
+		CL_PRINTF(cli_buf);
+
+		u32tmp[0] = halbtc8703b1ant_ltecoex_indirect_read_reg(btcoexist,
+				0xa8);
+		u32tmp[1] = halbtc8703b1ant_ltecoex_indirect_read_reg(btcoexist,
+				0xac);
+		u32tmp[2] = halbtc8703b1ant_ltecoex_indirect_read_reg(btcoexist,
+				0xb0);
+		u32tmp[3] = halbtc8703b1ant_ltecoex_indirect_read_reg(btcoexist,
+				0xb4);
+
+		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+			   "\r\n %-35s = 0x%x/ 0x%x/ 0x%x/ 0x%x",
+			   "LTE Break Table W_L/B_L/L_W/L_B",
+			   u32tmp[0] & 0xffff, u32tmp[1] & 0xffff,
+			   u32tmp[2] & 0xffff, u32tmp[3] & 0xffff);
+		CL_PRINTF(cli_buf);
+	}
+	/* Hw setting		 */
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s",
+		   "============[Hw setting]============");
+	CL_PRINTF(cli_buf);
+
+	u32tmp[0] = halbtc8703b1ant_ltecoex_indirect_read_reg(btcoexist, 0x38);
+	u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x73);
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %s",
+		   "LTE CoexOn/Path Ctrl Owner",
+		   (int)((u32tmp[0] & BIT(7)) >> 7),
+		   ((u8tmp[0] & BIT(2)) ? "WL" : "BT"));
+	CL_PRINTF(cli_buf);
+
+	if (lte_coex_on) {
+		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d/ %d",
+			   "LTE 3Wire/OPMode/UART/UARTMode",
+			   (int)((u32tmp[0] & BIT(6)) >> 6),
+			   (int)((u32tmp[0] & (BIT(5) | BIT(4))) >> 4),
+			   (int)((u32tmp[0] & BIT(3)) >> 3),
+			   (int)(u32tmp[0] & (BIT(2) | BIT(1) | BIT(0))));
+		CL_PRINTF(cli_buf);
+	}
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+			   "\r\n %-35s = %s (BB:%s)/ %s (BB:%s)/ %s %d",
+			   "GNT_WL_Ctrl/GNT_BT_Ctrl/Dbg",
+			   ((u32tmp[0] & BIT(12)) ? "SW" : "HW"),
+			   ((u32tmp[0] & BIT(8)) ?	"SW" : "HW"),
+			   ((u32tmp[0] & BIT(14)) ? "SW" : "HW"),
+			   ((u32tmp[0] & BIT(10)) ?  "SW" : "HW"),
+			   ((u8tmp[0] & BIT(3)) ? "On" : "Off"),
+			   coex_sta->gnt_error_cnt);
+	CL_PRINTF(cli_buf);
+
+	u32tmp[0] = halbtc8703b1ant_ltecoex_indirect_read_reg(btcoexist, 0x54);
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d/ %d",
+		   "GNT_WL/GNT_BT/LTE_Busy/UART_Busy",
+		   (int)((u32tmp[0] & BIT(2)) >> 2),
+		   (int)((u32tmp[0] & BIT(3)) >> 3),
+		   (int)((u32tmp[0] & BIT(1)) >> 1), (int)(u32tmp[0] & BIT(0)));
+	CL_PRINTF(cli_buf);
+
+
+	u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x4c6);
+	u8tmp[1] = btcoexist->btc_read_1byte(btcoexist, 0x40);
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x",
+		   "0x4c6[4]/0x40[5] (WL/BT PTA)",
+		   (int)((u8tmp[0] & BIT(4)) >> 4),
+		   (int)((u8tmp[1] & BIT(5)) >> 5));
+	CL_PRINTF(cli_buf);
+
+	u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x550);
+	u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x522);
+	u8tmp[1] = btcoexist->btc_read_1byte(btcoexist, 0x953);
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x/ %s",
+		   "0x550(bcn ctrl)/0x522/4-RxAGC",
+		   u32tmp[0], u8tmp[0], (u8tmp[1] & 0x2) ? "On" : "Off");
+	CL_PRINTF(cli_buf);
+
+	fa_ofdm = btcoexist->btc_phydm_query_PHY_counter(btcoexist, PHYDM_INFO_FA_OFDM);
+	fa_cck = btcoexist->btc_phydm_query_PHY_counter(btcoexist, PHYDM_INFO_FA_CCK);
+	cca_ofdm = btcoexist->btc_phydm_query_PHY_counter(btcoexist, PHYDM_INFO_CCA_OFDM);
+	cca_cck = btcoexist->btc_phydm_query_PHY_counter(btcoexist, PHYDM_INFO_CCA_CCK);
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+		   "\r\n %-35s = 0x%x/ 0x%x/ 0x%x/ 0x%x",
+		   "CCK-CCA/CCK-FA/OFDM-CCA/OFDM-FA",
+		   cca_cck, fa_cck, cca_ofdm, fa_ofdm);
+	CL_PRINTF(cli_buf);
+
+#if 1
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d/ %d",
+		   "CRC_OK CCK/11g/11n/11n-agg",
+		   coex_sta->crc_ok_cck, coex_sta->crc_ok_11g,
+		   coex_sta->crc_ok_11n, coex_sta->crc_ok_11n_vht);
+	CL_PRINTF(cli_buf);
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d/ %d",
+		   "CRC_Err CCK/11g/11n/11n-agg",
+		   coex_sta->crc_err_cck, coex_sta->crc_err_11g,
+		   coex_sta->crc_err_11n, coex_sta->crc_err_11n_vht);
+	CL_PRINTF(cli_buf);
+#endif
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s/ %s/ %s/ %d",
+			   "WlHiPri/ Locking/ Locked/ Noisy",
+			   (coex_sta->wifi_is_high_pri_task ? "Yes" : "No"),
+			   (coex_sta->cck_lock ? "Yes" : "No"),
+			   (coex_sta->cck_ever_lock ? "Yes" : "No"),
+			   coex_sta->wl_noisy_level);
+	CL_PRINTF(cli_buf);
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d %s",
+		   "0x770(Hi-pri rx/tx)",
+		   coex_sta->high_priority_rx, coex_sta->high_priority_tx,
+		   (coex_sta->is_hiPri_rx_overhead ? "(scan overhead!!)" : ""));
+	CL_PRINTF(cli_buf);
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d %s",
+		   "0x774(Lo-pri rx/tx)",
+		   coex_sta->low_priority_rx, coex_sta->low_priority_tx,
+		   (bt_link_info->slave_role ? "(Slave!!)" : ""));
+	CL_PRINTF(cli_buf);
+
+	btcoexist->btc_disp_dbg_msg(btcoexist, BTC_DBG_DISP_COEX_STATISTICS);
+}
+
+
+void ex_halbtc8703b1ant_ips_notify(IN struct btc_coexist *btcoexist, IN u8 type)
+{
+	if (btcoexist->manual_control ||	btcoexist->stop_coex_dm)
+		return;
+
+	if (BTC_IPS_ENTER == type) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], IPS ENTER notify\n");
+		BTC_TRACE(trace_buf);
+		coex_sta->under_ips = true;
+		coex_sta->under_lps = false;
+
+		/* Write WL "Active" in Score-board for LPS off */
+		halbtc8703b1ant_post_state_to_bt(btcoexist,
+				BT_8703B_1ANT_SCOREBOARD_ACTIVE |
+				BT_8703B_1ANT_SCOREBOARD_ONOFF |
+				BT_8703B_1ANT_SCOREBOARD_SCAN |
+				BT_8703B_1ANT_SCOREBOARD_UNDERTEST,
+				false);
+
+		halbtc8703b1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 0);
+
+		halbtc8703b1ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO,
+					     FORCE_EXEC,
+					     BT_8703B_1ANT_PHASE_WLAN_OFF);
+
+		halbtc8703b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0);
+	} else if (BTC_IPS_LEAVE == type) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], IPS LEAVE notify\n");
+		BTC_TRACE(trace_buf);
+#if 0
+		halbtc8703b1ant_post_state_to_bt(btcoexist,
+				 BT_8703B_1ANT_SCOREBOARD_ACTIVE, true);
+#endif
+		halbtc8703b1ant_init_hw_config(btcoexist, false, false);
+		halbtc8703b1ant_init_coex_dm(btcoexist);
+		halbtc8703b1ant_query_bt_info(btcoexist);
+
+		coex_sta->under_ips = false;
+	}
+}
+
+void ex_halbtc8703b1ant_lps_notify(IN struct btc_coexist *btcoexist, IN u8 type)
+{
+	if (btcoexist->manual_control || btcoexist->stop_coex_dm)
+		return;
+
+	if (BTC_LPS_ENABLE == type) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], LPS ENABLE notify\n");
+		BTC_TRACE(trace_buf);
+		coex_sta->under_lps = true;
+		coex_sta->under_ips = false;
+
+		if (coex_sta->force_lps_on == true) { /* LPS No-32K */
+			/* Write WL "Active" in Score-board for PS-TDMA */
+			halbtc8703b1ant_post_state_to_bt(btcoexist,
+				 BT_8703B_1ANT_SCOREBOARD_ACTIVE, true);
+
+		} else { /* LPS-32K, need check if this h2c 0x71 can work?? (2015/08/28) */
+			/* Write WL "Non-Active" in Score-board for Native-PS */
+			halbtc8703b1ant_post_state_to_bt(btcoexist,
+				 BT_8703B_1ANT_SCOREBOARD_ACTIVE, false);
+		}
+	} else if (BTC_LPS_DISABLE == type) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], LPS DISABLE notify\n");
+		BTC_TRACE(trace_buf);
+		coex_sta->under_lps = false;
+
+
+		/* Write WL "Active" in Score-board for LPS off */
+		halbtc8703b1ant_post_state_to_bt(btcoexist,
+				 BT_8703B_1ANT_SCOREBOARD_ACTIVE, true);
+	}
+}
+
+void ex_halbtc8703b1ant_scan_notify(IN struct btc_coexist *btcoexist,
+				    IN u8 type)
+{
+	boolean wifi_connected = false;
+
+	if (btcoexist->manual_control ||
+	    btcoexist->stop_coex_dm)
+		return;
+
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED,
+			   &wifi_connected);
+
+	halbtc8703b1ant_query_bt_info(btcoexist);
+
+	if (BTC_SCAN_START == type) {
+
+		coex_sta->wifi_is_high_pri_task = true;
+
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], SCAN START notify\n");
+		BTC_TRACE(trace_buf);
+
+		halbtc8703b1ant_post_state_to_bt(btcoexist,
+					BT_8703B_1ANT_SCOREBOARD_ACTIVE |
+					BT_8703B_1ANT_SCOREBOARD_SCAN |
+					BT_8703B_1ANT_SCOREBOARD_ONOFF,
+					true);
+
+		halbtc8703b1ant_ps_tdma(btcoexist, FORCE_EXEC, false,
+					8);
+
+		/* Force antenna setup for no scan result issue */
+		halbtc8703b1ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO,
+					     FORCE_EXEC,
+					     BT_8703B_1ANT_PHASE_2G_RUNTIME);
+
+		halbtc8703b1ant_run_coexist_mechanism(btcoexist);
+
+	} else {
+
+		coex_sta->wifi_is_high_pri_task = false;
+
+		btcoexist->btc_get(btcoexist, BTC_GET_U1_AP_NUM,
+				   &coex_sta->scan_ap_num);
+
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], SCAN FINISH notify  (Scan-AP = %d)\n",
+			    coex_sta->scan_ap_num);
+		BTC_TRACE(trace_buf);
+
+		halbtc8703b1ant_run_coexist_mechanism(btcoexist);
+	}
+
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+		    "[BTCoex], SCAN START Notify() end\n");
+	BTC_TRACE(trace_buf);
+
+}
+
+void ex_halbtc8703b1ant_connect_notify(IN struct btc_coexist *btcoexist,
+				       IN u8 type)
+{
+	boolean	wifi_connected = false;
+
+	if (btcoexist->manual_control ||
+	    btcoexist->stop_coex_dm)
+		return;
+
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED,
+			   &wifi_connected);
+
+	if (BTC_ASSOCIATE_START == type) {
+		coex_sta->wifi_is_high_pri_task = true;
+
+		halbtc8703b1ant_post_state_to_bt(btcoexist,
+					 BT_8703B_1ANT_SCOREBOARD_ACTIVE |
+					 BT_8703B_1ANT_SCOREBOARD_SCAN |
+					 BT_8703B_1ANT_SCOREBOARD_ONOFF,
+					 true);
+
+		halbtc8703b1ant_ps_tdma(btcoexist, FORCE_EXEC, false,
+					8);
+
+		/* Force antenna setup for no scan result issue */
+		halbtc8703b1ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO,
+					     FORCE_EXEC,
+					     BT_8703B_1ANT_PHASE_2G_RUNTIME);
+		/* psd_scan->ant_det_is_ant_det_available = true; */
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], CONNECT START notify\n");
+		BTC_TRACE(trace_buf);
+		coex_dm->arp_cnt = 0;
+
+		halbtc8703b1ant_run_coexist_mechanism(btcoexist);
+	} else {
+		coex_sta->wifi_is_high_pri_task = false;
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], CONNECT FINISH notify\n");
+		BTC_TRACE(trace_buf);
+
+		halbtc8703b1ant_run_coexist_mechanism(btcoexist);
+	}
+
+}
+
+void ex_halbtc8703b1ant_media_status_notify(IN struct btc_coexist *btcoexist,
+		IN u8 type)
+{
+	boolean			wifi_under_b_mode = false;
+
+	if (btcoexist->manual_control ||
+	    btcoexist->stop_coex_dm)
+		return;
+
+	if (BTC_MEDIA_CONNECT == type) {
+
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], MEDIA connect notify\n");
+		BTC_TRACE(trace_buf);
+
+		halbtc8703b1ant_post_state_to_bt(btcoexist,
+					 BT_8703B_1ANT_SCOREBOARD_ACTIVE |
+					 BT_8703B_1ANT_SCOREBOARD_ONOFF,
+					 true);
+
+		halbtc8703b1ant_ps_tdma(btcoexist, FORCE_EXEC, false,
+					8);
+
+		/* Force antenna setup for no scan result issue */
+		halbtc8703b1ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO,
+					     FORCE_EXEC,
+					     BT_8703B_1ANT_PHASE_2G_RUNTIME);
+
+		btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_B_MODE,
+				   &wifi_under_b_mode);
+
+		/* Set CCK Tx/Rx high Pri except 11b mode */
+		if (wifi_under_b_mode) {
+			btcoexist->btc_write_1byte(btcoexist, 0x6cd,
+						   0x00); /* CCK Tx */
+			btcoexist->btc_write_1byte(btcoexist, 0x6cf,
+						   0x00); /* CCK Rx */
+		} else {
+			/* btcoexist->btc_write_1byte(btcoexist, 0x6cd, 0x10); */ /*CCK Tx */
+			/* btcoexist->btc_write_1byte(btcoexist, 0x6cf, 0x10); */ /*CCK Rx */
+			btcoexist->btc_write_1byte(btcoexist, 0x6cd,
+						   0x00); /* CCK Tx */
+			btcoexist->btc_write_1byte(btcoexist, 0x6cf,
+						   0x10); /* CCK Rx */
+		}
+
+		coex_dm->backup_arfr_cnt1 = btcoexist->btc_read_4byte(btcoexist,
+					    0x430);
+		coex_dm->backup_arfr_cnt2 = btcoexist->btc_read_4byte(btcoexist,
+					    0x434);
+		coex_dm->backup_retry_limit = btcoexist->btc_read_2byte(
+						      btcoexist, 0x42a);
+		coex_dm->backup_ampdu_max_time = btcoexist->btc_read_1byte(
+				btcoexist, 0x456);
+	} else {
+
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], MEDIA disconnect notify\n");
+		BTC_TRACE(trace_buf);
+
+		halbtc8703b1ant_post_state_to_bt(btcoexist,
+				 BT_8703B_1ANT_SCOREBOARD_ACTIVE, false);
+
+		btcoexist->btc_write_1byte(btcoexist, 0x6cd, 0x0); /* CCK Tx */
+		btcoexist->btc_write_1byte(btcoexist, 0x6cf, 0x0); /* CCK Rx */
+
+		coex_sta->cck_ever_lock = false;
+	}
+
+	halbtc8703b1ant_update_wifi_channel_info(btcoexist, type);
+
+}
+
+void ex_halbtc8703b1ant_specific_packet_notify(IN struct btc_coexist *btcoexist,
+		IN u8 type)
+{
+	boolean	under_4way = false;
+
+	if (btcoexist->manual_control ||
+	    btcoexist->stop_coex_dm)
+		return;
+
+
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_4_WAY_PROGRESS,
+			   &under_4way);
+
+	if (under_4way) {
+
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], specific Packet ---- under_4way!!\n");
+		BTC_TRACE(trace_buf);
+
+		coex_sta->wifi_is_high_pri_task = true;
+		coex_sta->specific_pkt_period_cnt = 2;
+	} else if (BTC_PACKET_ARP == type) {
+
+		coex_dm->arp_cnt++;
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], specific Packet ARP notify -cnt = %d\n",
+			    coex_dm->arp_cnt);
+		BTC_TRACE(trace_buf);
+
+	} else {
+
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			"[BTCoex], specific Packet DHCP or EAPOL notify [Type = %d]\n",
+			    type);
+		BTC_TRACE(trace_buf);
+
+		coex_sta->wifi_is_high_pri_task = true;
+		coex_sta->specific_pkt_period_cnt = 2;
+	}
+
+	if (coex_sta->wifi_is_high_pri_task) {
+		halbtc8703b1ant_post_state_to_bt(btcoexist,
+					 BT_8703B_1ANT_SCOREBOARD_SCAN, true);
+		halbtc8703b1ant_run_coexist_mechanism(btcoexist);
+	}
+}
+
+void ex_halbtc8703b1ant_bt_info_notify(IN struct btc_coexist *btcoexist,
+				       IN u8 *tmp_buf, IN u8 length)
+{
+	u8				i, rsp_source = 0;
+	boolean				wifi_connected = false;
+	boolean	wifi_scan = false, wifi_link = false, wifi_roam = false,
+		    wifi_busy = false;
+	static boolean is_scoreboard_scan = false;
+
+
+	rsp_source = tmp_buf[0] & 0xf;
+	if (rsp_source >= BT_INFO_SRC_8703B_1ANT_MAX)
+		rsp_source = BT_INFO_SRC_8703B_1ANT_WIFI_FW;
+	coex_sta->bt_info_c2h_cnt[rsp_source]++;
+
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+		    "[BTCoex], Bt_info[%d], len=%d, data=[", rsp_source,
+		    length);
+	BTC_TRACE(trace_buf);
+
+	for (i = 0; i < length; i++) {
+		coex_sta->bt_info_c2h[rsp_source][i] = tmp_buf[i];
+
+		if (i == length - 1) {
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "0x%02x]\n",
+				    tmp_buf[i]);
+			BTC_TRACE(trace_buf);
+		} else {
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "0x%02x, ",
+				    tmp_buf[i]);
+			BTC_TRACE(trace_buf);
+		}
+	}
+
+	coex_sta->bt_info = coex_sta->bt_info_c2h[rsp_source][1];
+	coex_sta->bt_info_ext = coex_sta->bt_info_c2h[rsp_source][4];
+	coex_sta->bt_info_ext2 = coex_sta->bt_info_c2h[rsp_source][5];
+
+	if (BT_INFO_SRC_8703B_1ANT_WIFI_FW != rsp_source) {
+
+		/* if 0xff, it means BT is under WHCK test */
+		coex_sta->bt_whck_test = ((coex_sta->bt_info == 0xff) ? true :
+					  false);
+
+		coex_sta->bt_create_connection = ((
+			coex_sta->bt_info_c2h[rsp_source][2] & 0x80) ? true :
+						  false);
+
+		/* unit: %, value-100 to translate to unit: dBm */
+		coex_sta->bt_rssi = coex_sta->bt_info_c2h[rsp_source][3] * 2 +
+				    10;
+
+		coex_sta->c2h_bt_remote_name_req = ((
+			coex_sta->bt_info_c2h[rsp_source][2] & 0x20) ? true :
+						    false);
+
+		coex_sta->is_A2DP_3M = ((coex_sta->bt_info_c2h[rsp_source][2] &
+					 0x10) ? true : false);
+
+		coex_sta->acl_busy = ((coex_sta->bt_info_c2h[rsp_source][1] &
+				       0x9) ? true : false);
+
+		coex_sta->voice_over_HOGP = ((coex_sta->bt_info_ext & 0x10) ?
+					     true : false);
+
+		coex_sta->c2h_bt_inquiry_page = ((coex_sta->bt_info &
+			  BT_INFO_8703B_1ANT_B_INQ_PAGE) ? true : false);
+
+		coex_sta->a2dp_bit_pool = (((
+			coex_sta->bt_info_c2h[rsp_source][1] & 0x49) == 0x49) ?
+				   coex_sta->bt_info_c2h[rsp_source][6] : 0);
+
+		coex_sta->bt_retry_cnt = coex_sta->bt_info_c2h[rsp_source][2] &
+					 0xf;
+
+		coex_sta->is_autoslot = coex_sta->bt_info_ext2 & 0x8;
+
+		coex_sta->forbidden_slot = coex_sta->bt_info_ext2 & 0x7;
+
+		coex_sta->hid_busy_num = (coex_sta->bt_info_ext2 & 0x30) >> 4;
+
+		coex_sta->hid_pair_cnt = (coex_sta->bt_info_ext2 & 0xc0) >> 6;
+
+		if (coex_sta->bt_retry_cnt >= 1)
+			coex_sta->pop_event_cnt++;
+
+		if (coex_sta->c2h_bt_remote_name_req)
+			coex_sta->cnt_RemoteNameReq++;
+
+		if (coex_sta->bt_info_ext & BIT(1))
+			coex_sta->cnt_ReInit++;
+
+		if (coex_sta->bt_info_ext & BIT(2)) {
+			coex_sta->cnt_setupLink++;
+			coex_sta->is_setupLink = true;
+		} else
+			coex_sta->is_setupLink = false;
+
+		if (coex_sta->bt_info_ext & BIT(3))
+			coex_sta->cnt_IgnWlanAct++;
+
+		if (coex_sta->bt_create_connection) {
+			coex_sta->cnt_Page++;
+
+			btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY,
+					   &wifi_busy);
+
+			btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_SCAN, &wifi_scan);
+			btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_LINK, &wifi_link);
+			btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_ROAM, &wifi_roam);
+
+			if ((wifi_link) || (wifi_roam) || (wifi_scan) ||
+			    (coex_sta->wifi_is_high_pri_task) || (wifi_busy)) {
+
+				is_scoreboard_scan = true;
+				halbtc8703b1ant_post_state_to_bt(btcoexist,
+					 BT_8703B_1ANT_SCOREBOARD_SCAN, true);
+
+			} else
+				halbtc8703b1ant_post_state_to_bt(btcoexist,
+					 BT_8703B_1ANT_SCOREBOARD_SCAN, false);
+
+		} else {
+				if (is_scoreboard_scan) {
+					halbtc8703b1ant_post_state_to_bt(btcoexist,
+						 BT_8703B_1ANT_SCOREBOARD_SCAN, false);
+					is_scoreboard_scan = false;
+				}
+		}
+
+		/* Here we need to resend some wifi info to BT */
+		/* because bt is reset and loss of the info. */
+
+		if ((!btcoexist->manual_control) &&
+		    (!btcoexist->stop_coex_dm)) {
+
+			btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED,
+					   &wifi_connected);
+
+			/*  Re-Init */
+			if ((coex_sta->bt_info_ext & BIT(1))) {
+				BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+					"[BTCoex], BT ext info bit1 check, send wifi BW&Chnl to BT!!\n");
+				BTC_TRACE(trace_buf);
+				if (wifi_connected)
+					halbtc8703b1ant_update_wifi_channel_info(
+						btcoexist, BTC_MEDIA_CONNECT);
+				else
+					halbtc8703b1ant_update_wifi_channel_info(
+						btcoexist,
+						BTC_MEDIA_DISCONNECT);
+			}
+
+
+			/*  If Ignore_WLanAct && not SetUp_Link */
+			if ((coex_sta->bt_info_ext & BIT(3)) &&
+			    (!(coex_sta->bt_info_ext & BIT(2)))) {
+
+				BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+					"[BTCoex], BT ext info bit3 check, set BT NOT to ignore Wlan active!!\n");
+				BTC_TRACE(trace_buf);
+				halbtc8703b1ant_ignore_wlan_act(btcoexist,
+							FORCE_EXEC, false);
+			}
+		}
+
+	}
+	if ((coex_sta->bt_info_ext & BIT(5))) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+					"[BTCoex], BT ext info bit4 check, query BLE Scan type!!\n");
+		BTC_TRACE(trace_buf);
+		coex_sta->bt_ble_scan_type = btcoexist->btc_get_ble_scan_type_from_bt(btcoexist);
+
+		if ((coex_sta->bt_ble_scan_type & 0x1) == 0x1)
+			coex_sta->bt_ble_scan_para[0]  = btcoexist->btc_get_ble_scan_para_from_bt(btcoexist, 0x1);
+		if ((coex_sta->bt_ble_scan_type & 0x2) == 0x2)
+			coex_sta->bt_ble_scan_para[1]  = btcoexist->btc_get_ble_scan_para_from_bt(btcoexist, 0x2);
+		if ((coex_sta->bt_ble_scan_type & 0x4) == 0x4)
+			coex_sta->bt_ble_scan_para[2]  = btcoexist->btc_get_ble_scan_para_from_bt(btcoexist, 0x4);
+	}
+
+	halbtc8703b1ant_update_bt_link_info(btcoexist);
+
+	halbtc8703b1ant_run_coexist_mechanism(btcoexist);
+}
+
+
+void ex_halbtc8703b1ant_rf_status_notify(IN struct btc_coexist *btcoexist,
+		IN u8 type)
+{
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], RF Status notify\n");
+	BTC_TRACE(trace_buf);
+
+	if (BTC_RF_ON == type) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], RF is turned ON!!\n");
+		BTC_TRACE(trace_buf);
+
+		btcoexist->stop_coex_dm = false;
+#if 0
+		halbtc8703b1ant_post_state_to_bt(btcoexist,
+				 BT_8703B_1ANT_SCOREBOARD_ACTIVE, true);
+		halbtc8703b1ant_post_state_to_bt(btcoexist,
+					 BT_8703B_1ANT_SCOREBOARD_ONOFF, true);
+#endif
+		/*	halbtc8703b1ant_init_hw_config(btcoexist, false, false); */
+	} else if (BTC_RF_OFF == type) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], RF is turned OFF!!\n");
+		BTC_TRACE(trace_buf);
+		halbtc8703b1ant_post_state_to_bt(btcoexist,
+				BT_8703B_1ANT_SCOREBOARD_ACTIVE |
+				BT_8703B_1ANT_SCOREBOARD_ONOFF |
+				BT_8703B_1ANT_SCOREBOARD_SCAN |
+				BT_8703B_1ANT_SCOREBOARD_UNDERTEST,
+				false);
+
+		halbtc8703b1ant_ps_tdma(btcoexist, FORCE_EXEC, false, 0);
+		halbtc8703b1ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO,
+					     FORCE_EXEC,
+					     BT_8703B_1ANT_PHASE_WLAN_OFF);
+
+		btcoexist->stop_coex_dm = true;
+
+	}
+}
+
+void ex_halbtc8703b1ant_halt_notify(IN struct btc_coexist *btcoexist)
+{
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], Halt notify\n");
+	BTC_TRACE(trace_buf);
+
+	halbtc8703b1ant_post_state_to_bt(btcoexist,
+				BT_8703B_1ANT_SCOREBOARD_ACTIVE |
+				BT_8703B_1ANT_SCOREBOARD_ONOFF |
+				BT_8703B_1ANT_SCOREBOARD_SCAN |
+				BT_8703B_1ANT_SCOREBOARD_UNDERTEST,
+				false);
+
+	halbtc8703b1ant_ps_tdma(btcoexist, FORCE_EXEC, false, 0);
+	halbtc8703b1ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, FORCE_EXEC,
+				     BT_8703B_1ANT_PHASE_WLAN_OFF);
+
+	ex_halbtc8703b1ant_media_status_notify(btcoexist, BTC_MEDIA_DISCONNECT);
+
+	halbtc8703b1ant_enable_gnt_to_gpio(btcoexist, false);
+
+	btcoexist->stop_coex_dm = true;
+}
+
+void ex_halbtc8703b1ant_pnp_notify(IN struct btc_coexist *btcoexist,
+				   IN u8 pnp_state)
+{
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], Pnp notify\n");
+	BTC_TRACE(trace_buf);
+
+	if ((BTC_WIFI_PNP_SLEEP == pnp_state) ||
+	    (BTC_WIFI_PNP_SLEEP_KEEP_ANT == pnp_state)) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], Pnp notify to SLEEP\n");
+		BTC_TRACE(trace_buf);
+
+		halbtc8703b1ant_post_state_to_bt(btcoexist,
+				BT_8703B_1ANT_SCOREBOARD_ACTIVE |
+				BT_8703B_1ANT_SCOREBOARD_ONOFF |
+				BT_8703B_1ANT_SCOREBOARD_SCAN |
+				BT_8703B_1ANT_SCOREBOARD_UNDERTEST,
+				false);
+
+		if (BTC_WIFI_PNP_SLEEP_KEEP_ANT == pnp_state) {
+
+			halbtc8703b1ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO,
+						     FORCE_EXEC,
+					     BT_8703B_1ANT_PHASE_2G_RUNTIME);
+		} else {
+
+			halbtc8703b1ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO,
+						     FORCE_EXEC,
+					     BT_8703B_1ANT_PHASE_WLAN_OFF);
+		}
+
+		btcoexist->stop_coex_dm = true;
+	} else if (BTC_WIFI_PNP_WAKE_UP == pnp_state) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], Pnp notify to WAKE UP\n");
+		BTC_TRACE(trace_buf);
+#if 0
+		halbtc8703b1ant_post_state_to_bt(btcoexist,
+				 BT_8703B_1ANT_SCOREBOARD_ACTIVE, true);
+		halbtc8703b1ant_post_state_to_bt(btcoexist,
+							 BT_8703B_1ANT_SCOREBOARD_ONOFF, true);
+#endif
+		btcoexist->stop_coex_dm = false;
+	}
+}
+
+void ex_halbtc8703b1ant_coex_dm_reset(IN struct btc_coexist *btcoexist)
+{
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+		"[BTCoex], *****************Coex DM Reset*****************\n");
+	BTC_TRACE(trace_buf);
+
+	halbtc8703b1ant_init_hw_config(btcoexist, false, false);
+	halbtc8703b1ant_init_coex_dm(btcoexist);
+}
+
+void ex_halbtc8703b1ant_periodical(IN struct btc_coexist *btcoexist)
+{
+	u32	bt_patch_ver;
+	boolean wifi_busy = false;
+
+#if (BT_AUTO_REPORT_ONLY_8703B_1ANT == 0)
+	halbtc8703b1ant_query_bt_info(btcoexist);
+#endif
+
+	halbtc8703b1ant_monitor_bt_ctr(btcoexist);
+	halbtc8703b1ant_monitor_wifi_ctr(btcoexist);
+
+	halbtc8703b1ant_monitor_bt_enable_disable(btcoexist);
+
+#if 0
+		btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy);
+
+		/* halbtc8703b1ant_read_score_board(btcoexist, &bt_scoreboard_val); */
+
+		if (wifi_busy) {
+			halbtc8703b1ant_post_state_to_bt(btcoexist,
+					BT_8703B_1ANT_SCOREBOARD_UNDERTEST, true);
+			/*
+			halbtc8703b1ant_post_state_to_bt(btcoexist,
+						 BT_8703B_1ANT_SCOREBOARD_WLBUSY, true);
+
+			if (bt_scoreboard_val & BIT(6))
+				halbtc8703b1ant_query_bt_info(btcoexist); */
+		} else {
+			halbtc8703b1ant_post_state_to_bt(btcoexist,
+						BT_8703B_1ANT_SCOREBOARD_UNDERTEST, false);
+			/*
+			halbtc8703b1ant_post_state_to_bt(btcoexist,
+						BT_8703B_1ANT_SCOREBOARD_WLBUSY,
+						false);  */
+		}
+#endif
+
+
+	/* for 4-way, DHCP, EAPOL packet */
+	if (coex_sta->specific_pkt_period_cnt > 0) {
+
+		coex_sta->specific_pkt_period_cnt--;
+
+		if ((coex_sta->specific_pkt_period_cnt == 0) &&
+		    (coex_sta->wifi_is_high_pri_task))
+			coex_sta->wifi_is_high_pri_task = false;
+
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			"[BTCoex], ***************** Hi-Pri Task = %s*****************\n",
+			    (coex_sta->wifi_is_high_pri_task ? "Yes" :
+			     "No"));
+		BTC_TRACE(trace_buf);
+
+	}
+
+	if (halbtc8703b1ant_is_wifibt_status_changed(btcoexist))
+		halbtc8703b1ant_run_coexist_mechanism(btcoexist);
+}
+
+void ex_halbtc8703b1ant_antenna_detection(IN struct btc_coexist *btcoexist,
+		IN u32 cent_freq, IN u32 offset, IN u32 span, IN u32 seconds)
+{
+	/* No Antenna Detection required because 8730b is only 1-Ant */
+}
+
+void ex_halbtc8703b1ant_antenna_isolation(IN struct btc_coexist *btcoexist,
+		IN u32 cent_freq, IN u32 offset, IN u32 span, IN u32 seconds)
+{
+
+
+}
+
+void ex_halbtc8703b1ant_psd_scan(IN struct btc_coexist *btcoexist,
+		 IN u32 cent_freq, IN u32 offset, IN u32 span, IN u32 seconds)
+{
+
+
+}
+
+void ex_halbtc8703b1ant_display_ant_detection(IN struct btc_coexist *btcoexist)
+{
+
+}
+
+#endif
+
+#endif	/* #if (BT_SUPPORT == 1 && COEX_SUPPORT == 1) */
+
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/btc/halbtc8703b1ant.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/btc/halbtc8703b1ant.h
--- linux-5.6.3/3rdparty/rtl8821ce/hal/btc/halbtc8703b1ant.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/btc/halbtc8703b1ant.h	2020-04-10 16:35:06.781658433 +0300
@@ -0,0 +1,399 @@
+
+#if (BT_SUPPORT == 1 && COEX_SUPPORT == 1)
+
+#if (RTL8703B_SUPPORT == 1)
+/* *******************************************
+ * The following is for 8703B 1ANT BT Co-exist definition
+ * ******************************************* */
+#define	BT_AUTO_REPORT_ONLY_8703B_1ANT				1
+#define BT_8703B_1ANT_ENABLE_GNTBT_TO_GPIO14		0
+
+#define	BT_INFO_8703B_1ANT_B_FTP						BIT(7)
+#define	BT_INFO_8703B_1ANT_B_A2DP					BIT(6)
+#define	BT_INFO_8703B_1ANT_B_HID						BIT(5)
+#define	BT_INFO_8703B_1ANT_B_SCO_BUSY				BIT(4)
+#define	BT_INFO_8703B_1ANT_B_ACL_BUSY				BIT(3)
+#define	BT_INFO_8703B_1ANT_B_INQ_PAGE				BIT(2)
+#define	BT_INFO_8703B_1ANT_B_SCO_ESCO				BIT(1)
+#define	BT_INFO_8703B_1ANT_B_CONNECTION				BIT(0)
+
+#define	BT_INFO_8703B_1ANT_A2DP_BASIC_RATE(_BT_INFO_EXT_)	\
+	(((_BT_INFO_EXT_&BIT(0))) ? true : false)
+
+#define	BTC_RSSI_COEX_THRESH_TOL_8703B_1ANT		2
+
+#define  BT_8703B_1ANT_WIFI_NOISY_THRESH							50   /* max: 255 */
+
+/* for Antenna detection */
+#define	BT_8703B_1ANT_ANTDET_PSDTHRES_BACKGROUND					50
+#define	BT_8703B_1ANT_ANTDET_PSDTHRES_2ANT_BADISOLATION				70
+#define	BT_8703B_1ANT_ANTDET_PSDTHRES_2ANT_GOODISOLATION			55
+#define	BT_8703B_1ANT_ANTDET_PSDTHRES_1ANT							35
+#define	BT_8703B_1ANT_ANTDET_RETRY_INTERVAL							10	/* retry timer if ant det is fail, unit: second */
+#define	BT_8703B_1ANT_ANTDET_SWEEPPOINT_DELAY							40000
+#define	BT_8703B_1ANT_ANTDET_ENABLE									0
+#define	BT_8703B_1ANT_ANTDET_COEXMECHANISMSWITCH_ENABLE				0
+
+#define	BT_8703B_1ANT_LTECOEX_INDIRECTREG_ACCESS_TIMEOUT		30000
+
+enum bt_8703b_1ant_signal_state {
+	BT_8703B_1ANT_SIG_STA_SET_TO_LOW		= 0x0,
+	BT_8703B_1ANT_SIG_STA_SET_BY_HW		= 0x0,
+	BT_8703B_1ANT_SIG_STA_SET_TO_HIGH		= 0x1,
+	BT_8703B_1ANT_SIG_STA_MAX
+};
+
+enum bt_8703b_1ant_path_ctrl_owner {
+	BT_8703B_1ANT_PCO_BTSIDE		= 0x0,
+	BT_8703B_1ANT_PCO_WLSIDE	= 0x1,
+	BT_8703B_1ANT_PCO_MAX
+};
+
+enum bt_8703b_1ant_gnt_ctrl_type {
+	BT_8703B_1ANT_GNT_TYPE_CTRL_BY_PTA		= 0x0,
+	BT_8703B_1ANT_GNT_TYPE_CTRL_BY_SW		= 0x1,
+	BT_8703B_1ANT_GNT_TYPE_MAX
+};
+
+enum bt_8703b_1ant_gnt_ctrl_block {
+	BT_8703B_1ANT_GNT_BLOCK_RFC_BB		= 0x0,
+	BT_8703B_1ANT_GNT_BLOCK_RFC			= 0x1,
+	BT_8703B_1ANT_GNT_BLOCK_BB			= 0x2,
+	BT_8703B_1ANT_GNT_BLOCK_MAX
+};
+
+enum bt_8703b_1ant_lte_coex_table_type {
+	BT_8703B_1ANT_CTT_WL_VS_LTE			= 0x0,
+	BT_8703B_1ANT_CTT_BT_VS_LTE			= 0x1,
+	BT_8703B_1ANT_CTT_MAX
+};
+
+enum bt_8703b_1ant_lte_break_table_type {
+	BT_8703B_1ANT_LBTT_WL_BREAK_LTE			= 0x0,
+	BT_8703B_1ANT_LBTT_BT_BREAK_LTE				= 0x1,
+	BT_8703B_1ANT_LBTT_LTE_BREAK_WL			= 0x2,
+	BT_8703B_1ANT_LBTT_LTE_BREAK_BT				= 0x3,
+	BT_8703B_1ANT_LBTT_MAX
+};
+
+enum bt_info_src_8703b_1ant {
+	BT_INFO_SRC_8703B_1ANT_WIFI_FW			= 0x0,
+	BT_INFO_SRC_8703B_1ANT_BT_RSP				= 0x1,
+	BT_INFO_SRC_8703B_1ANT_BT_ACTIVE_SEND		= 0x2,
+	BT_INFO_SRC_8703B_1ANT_MAX
+};
+
+enum bt_8703b_1ant_bt_status {
+	BT_8703B_1ANT_BT_STATUS_NON_CONNECTED_IDLE	= 0x0,
+	BT_8703B_1ANT_BT_STATUS_CONNECTED_IDLE		= 0x1,
+	BT_8703B_1ANT_BT_STATUS_INQ_PAGE				= 0x2,
+	BT_8703B_1ANT_BT_STATUS_ACL_BUSY				= 0x3,
+	BT_8703B_1ANT_BT_STATUS_SCO_BUSY				= 0x4,
+	BT_8703B_1ANT_BT_STATUS_ACL_SCO_BUSY			= 0x5,
+	BT_8703B_1ANT_BT_STATUS_MAX
+};
+
+enum bt_8703b_1ant_wifi_status {
+	BT_8703B_1ANT_WIFI_STATUS_NON_CONNECTED_IDLE				= 0x0,
+	BT_8703B_1ANT_WIFI_STATUS_NON_CONNECTED_ASSO_AUTH_SCAN		= 0x1,
+	BT_8703B_1ANT_WIFI_STATUS_CONNECTED_SCAN					= 0x2,
+	BT_8703B_1ANT_WIFI_STATUS_CONNECTED_SPECIFIC_PKT				= 0x3,
+	BT_8703B_1ANT_WIFI_STATUS_CONNECTED_IDLE					= 0x4,
+	BT_8703B_1ANT_WIFI_STATUS_CONNECTED_BUSY					= 0x5,
+	BT_8703B_1ANT_WIFI_STATUS_MAX
+};
+
+enum bt_8703b_1ant_coex_algo {
+	BT_8703B_1ANT_COEX_ALGO_UNDEFINED			= 0x0,
+	BT_8703B_1ANT_COEX_ALGO_SCO				= 0x1,
+	BT_8703B_1ANT_COEX_ALGO_HID				= 0x2,
+	BT_8703B_1ANT_COEX_ALGO_A2DP				= 0x3,
+	BT_8703B_1ANT_COEX_ALGO_A2DP_PANHS		= 0x4,
+	BT_8703B_1ANT_COEX_ALGO_PANEDR			= 0x5,
+	BT_8703B_1ANT_COEX_ALGO_PANHS			= 0x6,
+	BT_8703B_1ANT_COEX_ALGO_PANEDR_A2DP		= 0x7,
+	BT_8703B_1ANT_COEX_ALGO_PANEDR_HID		= 0x8,
+	BT_8703B_1ANT_COEX_ALGO_HID_A2DP_PANEDR	= 0x9,
+	BT_8703B_1ANT_COEX_ALGO_HID_A2DP			= 0xa,
+	BT_8703B_1ANT_COEX_ALGO_MAX				= 0xb,
+};
+
+enum bt_8703b_1ant_phase {
+	BT_8703B_1ANT_PHASE_COEX_INIT								= 0x0,
+	BT_8703B_1ANT_PHASE_WLANONLY_INIT							= 0x1,
+	BT_8703B_1ANT_PHASE_WLAN_OFF								= 0x2,
+	BT_8703B_1ANT_PHASE_2G_RUNTIME								= 0x3,
+	BT_8703B_1ANT_PHASE_5G_RUNTIME								= 0x4,
+	BT_8703B_1ANT_PHASE_BTMPMODE								= 0x5,
+	BT_8703B_1ANT_PHASE_ANTENNA_DET								= 0x6,
+	BT_8703B_1ANT_PHASE_MAX
+};
+
+enum bt_8703b_1ant_Scoreboard {
+	BT_8703B_1ANT_SCOREBOARD_ACTIVE								= BIT(0),
+	BT_8703B_1ANT_SCOREBOARD_ONOFF								= BIT(1),
+	BT_8703B_1ANT_SCOREBOARD_SCAN								= BIT(2),
+	BT_8703B_1ANT_SCOREBOARD_UNDERTEST							= BIT(3),
+	BT_8703B_1ANT_SCOREBOARD_WLBUSY								= BIT(6)
+};
+
+
+struct coex_dm_8703b_1ant {
+	/* hw setting */
+	u8		pre_ant_pos_type;
+	u8		cur_ant_pos_type;
+	/* fw mechanism */
+	boolean		cur_ignore_wlan_act;
+	boolean		pre_ignore_wlan_act;
+	u8		pre_ps_tdma;
+	u8		cur_ps_tdma;
+	u8		ps_tdma_para[5];
+	u8		ps_tdma_du_adj_type;
+	boolean		auto_tdma_adjust;
+	boolean		pre_ps_tdma_on;
+	boolean		cur_ps_tdma_on;
+	boolean		pre_bt_auto_report;
+	boolean		cur_bt_auto_report;
+	u8		pre_lps;
+	u8		cur_lps;
+	u8		pre_rpwm;
+	u8		cur_rpwm;
+
+	/* sw mechanism */
+	boolean	pre_low_penalty_ra;
+	boolean		cur_low_penalty_ra;
+	u32		pre_val0x6c0;
+	u32		cur_val0x6c0;
+	u32		pre_val0x6c4;
+	u32		cur_val0x6c4;
+	u32		pre_val0x6c8;
+	u32		cur_val0x6c8;
+	u8		pre_val0x6cc;
+	u8		cur_val0x6cc;
+	boolean		limited_dig;
+
+	u32		backup_arfr_cnt1;	/* Auto Rate Fallback Retry cnt */
+	u32		backup_arfr_cnt2;	/* Auto Rate Fallback Retry cnt */
+	u16		backup_retry_limit;
+	u8		backup_ampdu_max_time;
+
+	/* algorithm related */
+	u8		pre_algorithm;
+	u8		cur_algorithm;
+	u8		bt_status;
+	u8		wifi_chnl_info[3];
+
+	u32		pre_ra_mask;
+	u32		cur_ra_mask;
+	u8		pre_arfr_type;
+	u8		cur_arfr_type;
+	u8		pre_retry_limit_type;
+	u8		cur_retry_limit_type;
+	u8		pre_ampdu_time_type;
+	u8		cur_ampdu_time_type;
+	u32		arp_cnt;
+
+	u8		error_condition;
+};
+
+struct coex_sta_8703b_1ant {
+	boolean				bt_disabled;
+	boolean				bt_link_exist;
+	boolean				sco_exist;
+	boolean				a2dp_exist;
+	boolean				hid_exist;
+	boolean				pan_exist;
+	boolean				bt_hi_pri_link_exist;
+	u8					num_of_profile;
+
+	boolean				under_lps;
+	boolean				under_ips;
+	u32					specific_pkt_period_cnt;
+	u32					high_priority_tx;
+	u32					high_priority_rx;
+	u32					low_priority_tx;
+	u32					low_priority_rx;
+	boolean             is_hiPri_rx_overhead;
+	s8					bt_rssi;
+	boolean				bt_tx_rx_mask;
+	u8					pre_bt_rssi_state;
+	u8					pre_wifi_rssi_state[4];
+	u8					bt_info_c2h[BT_INFO_SRC_8703B_1ANT_MAX][10];
+	u32					bt_info_c2h_cnt[BT_INFO_SRC_8703B_1ANT_MAX];
+	boolean			    bt_whck_test;
+	boolean				c2h_bt_inquiry_page;
+	boolean				c2h_bt_remote_name_req;
+	boolean				c2h_bt_page;				/* Add for win8.1 page out issue */
+	boolean				wifi_is_high_pri_task;		/* Add for win8.1 page out issue */
+	u8					bt_retry_cnt;
+	u8					bt_info_ext;
+	u8					bt_info_ext2;
+	u32					pop_event_cnt;
+	u8					scan_ap_num;
+
+	u32					crc_ok_cck;
+	u32					crc_ok_11g;
+	u32					crc_ok_11n;
+	u32					crc_ok_11n_vht;
+
+	u32					crc_err_cck;
+	u32					crc_err_11g;
+	u32					crc_err_11n;
+	u32					crc_err_11n_vht;
+
+	boolean				cck_lock;
+	boolean				pre_ccklock;
+	boolean				cck_ever_lock;
+	u8					coex_table_type;
+
+	boolean				force_lps_on;
+
+	boolean				concurrent_rx_mode_on;
+
+	u16					score_board;
+	u8					isolation_btween_wb;   /* 0~ 50 */
+
+	u8					a2dp_bit_pool;
+	u8					cut_version;
+	boolean				acl_busy;
+	boolean				bt_create_connection;
+
+	u32					bt_coex_supported_feature;
+	u32					bt_coex_supported_version;
+
+	u8					bt_ble_scan_type;
+	u32					bt_ble_scan_para[3];
+
+	boolean				run_time_state;
+	boolean				freeze_coexrun_by_btinfo;
+
+	boolean				is_A2DP_3M;
+	boolean				voice_over_HOGP;
+	u8                  bt_info;
+	boolean				is_autoslot;
+	u8					forbidden_slot;
+	u8					hid_busy_num;
+	u8					hid_pair_cnt;
+
+	u32					cnt_RemoteNameReq;
+	u32					cnt_setupLink;
+	u32					cnt_ReInit;
+	u32					cnt_IgnWlanAct;
+	u32					cnt_Page;
+
+	u16					bt_reg_vendor_ac;
+	u16					bt_reg_vendor_ae;
+
+	boolean				is_setupLink;
+	u8					wl_noisy_level;
+	u32                 gnt_error_cnt;
+};
+
+#define  BT_8703B_1ANT_ANTDET_PSD_POINTS			256	/* MAX:1024 */
+#define  BT_8703B_1ANT_ANTDET_PSD_AVGNUM			1	/* MAX:3 */
+#define	BT_8703B_1ANT_ANTDET_BUF_LEN				16
+
+struct psdscan_sta_8703b_1ant {
+
+	u32			ant_det_bt_le_channel;  /* BT LE Channel ex:2412 */
+	u32			ant_det_bt_tx_time;
+	u32			ant_det_pre_psdscan_peak_val;
+	boolean			ant_det_is_ant_det_available;
+	u32			ant_det_psd_scan_peak_val;
+	boolean			ant_det_is_btreply_available;
+	u32			ant_det_psd_scan_peak_freq;
+
+	u8			ant_det_result;
+	u8			ant_det_peak_val[BT_8703B_1ANT_ANTDET_BUF_LEN];
+	u8			ant_det_peak_freq[BT_8703B_1ANT_ANTDET_BUF_LEN];
+	u32			ant_det_try_count;
+	u32			ant_det_fail_count;
+	u32			ant_det_inteval_count;
+	u32			ant_det_thres_offset;
+
+	u32			real_cent_freq;
+	s32			real_offset;
+	u32			real_span;
+
+	u32			psd_band_width;  /* unit: Hz */
+	u32			psd_point;		/* 128/256/512/1024 */
+	u32			psd_report[1024];  /* unit:dB (20logx), 0~255 */
+	u32			psd_report_max_hold[1024];  /* unit:dB (20logx), 0~255 */
+	u32			psd_start_point;
+	u32			psd_stop_point;
+	u32			psd_max_value_point;
+	u32			psd_max_value;
+	u32			psd_start_base;
+	u32			psd_avg_num;	/* 1/8/16/32 */
+	u32			psd_gen_count;
+	boolean			is_psd_running;
+	boolean			is_psd_show_max_only;
+};
+
+/* *******************************************
+ * The following is interface which will notify coex module.
+ * ******************************************* */
+void ex_halbtc8703b1ant_power_on_setting(IN struct btc_coexist *btcoexist);
+void ex_halbtc8703b1ant_pre_load_firmware(IN struct btc_coexist *btcoexist);
+void ex_halbtc8703b1ant_init_hw_config(IN struct btc_coexist *btcoexist,
+				       IN boolean wifi_only);
+void ex_halbtc8703b1ant_init_coex_dm(IN struct btc_coexist *btcoexist);
+void ex_halbtc8703b1ant_ips_notify(IN struct btc_coexist *btcoexist,
+				   IN u8 type);
+void ex_halbtc8703b1ant_lps_notify(IN struct btc_coexist *btcoexist,
+				   IN u8 type);
+void ex_halbtc8703b1ant_scan_notify(IN struct btc_coexist *btcoexist,
+				    IN u8 type);
+void ex_halbtc8703b1ant_connect_notify(IN struct btc_coexist *btcoexist,
+				       IN u8 type);
+void ex_halbtc8703b1ant_media_status_notify(IN struct btc_coexist *btcoexist,
+		IN u8 type);
+void ex_halbtc8703b1ant_specific_packet_notify(IN struct btc_coexist *btcoexist,
+		IN u8 type);
+void ex_halbtc8703b1ant_bt_info_notify(IN struct btc_coexist *btcoexist,
+				       IN u8 *tmp_buf, IN u8 length);
+void ex_halbtc8703b1ant_rf_status_notify(IN struct btc_coexist *btcoexist,
+		IN u8 type);
+void ex_halbtc8703b1ant_halt_notify(IN struct btc_coexist *btcoexist);
+void ex_halbtc8703b1ant_pnp_notify(IN struct btc_coexist *btcoexist,
+				   IN u8 pnp_state);
+void ex_halbtc8703b1ant_coex_dm_reset(IN struct btc_coexist *btcoexist);
+void ex_halbtc8703b1ant_periodical(IN struct btc_coexist *btcoexist);
+void ex_halbtc8703b1ant_display_coex_info(IN struct btc_coexist *btcoexist);
+void ex_halbtc8703b1ant_antenna_detection(IN struct btc_coexist *btcoexist,
+		IN u32 cent_freq, IN u32 offset, IN u32 span, IN u32 seconds);
+void ex_halbtc8703b1ant_antenna_isolation(IN struct btc_coexist *btcoexist,
+		IN u32 cent_freq, IN u32 offset, IN u32 span, IN u32 seconds);
+
+void ex_halbtc8703b1ant_psd_scan(IN struct btc_coexist *btcoexist,
+		 IN u32 cent_freq, IN u32 offset, IN u32 span, IN u32 seconds);
+void ex_halbtc8703b1ant_display_ant_detection(IN struct btc_coexist *btcoexist);
+
+#else
+#define	ex_halbtc8703b1ant_power_on_setting(btcoexist)
+#define	ex_halbtc8703b1ant_pre_load_firmware(btcoexist)
+#define	ex_halbtc8703b1ant_init_hw_config(btcoexist, wifi_only)
+#define	ex_halbtc8703b1ant_init_coex_dm(btcoexist)
+#define	ex_halbtc8703b1ant_ips_notify(btcoexist, type)
+#define	ex_halbtc8703b1ant_lps_notify(btcoexist, type)
+#define	ex_halbtc8703b1ant_scan_notify(btcoexist, type)
+#define	ex_halbtc8703b1ant_connect_notify(btcoexist, type)
+#define	ex_halbtc8703b1ant_media_status_notify(btcoexist, type)
+#define	ex_halbtc8703b1ant_specific_packet_notify(btcoexist, type)
+#define	ex_halbtc8703b1ant_bt_info_notify(btcoexist, tmp_buf, length)
+#define	ex_halbtc8703b1ant_rf_status_notify(btcoexist, type)
+#define	ex_halbtc8703b1ant_halt_notify(btcoexist)
+#define	ex_halbtc8703b1ant_pnp_notify(btcoexist, pnp_state)
+#define	ex_halbtc8703b1ant_coex_dm_reset(btcoexist)
+#define	ex_halbtc8703b1ant_periodical(btcoexist)
+#define	ex_halbtc8703b1ant_display_coex_info(btcoexist)
+#define	ex_halbtc8703b1ant_antenna_detection(btcoexist, cent_freq, offset, span, seconds)
+#define	ex_halbtc8703b1ant_antenna_isolation(btcoexist, cent_freq, offset, span, seconds)
+#define	ex_halbtc8703b1ant_psd_scan(btcoexist, cent_freq, offset, span, seconds)
+#define	ex_halbtc8703b1ant_display_ant_detection(btcoexist)
+
+#endif
+
+
+#endif
+
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/btc/halbtc8723b1ant.c linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/btc/halbtc8723b1ant.c
--- linux-5.6.3/3rdparty/rtl8821ce/hal/btc/halbtc8723b1ant.c	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/btc/halbtc8723b1ant.c	2020-04-10 16:35:06.781658433 +0300
@@ -0,0 +1,5113 @@
+/* ************************************************************
+ * Description:
+ *
+ * This file is for RTL8723B Co-exist mechanism
+ *
+ * History
+ * 2012/11/15 Cosa first check in.
+ *
+ * ************************************************************ */
+
+/* ************************************************************
+ * include files
+ * ************************************************************ */
+#include "mp_precomp.h"
+
+#if (BT_SUPPORT == 1 && COEX_SUPPORT == 1)
+
+#if (RTL8723B_SUPPORT == 1)
+/* ************************************************************
+ * Global variables, these are static variables
+ * ************************************************************ */
+static u8	 *trace_buf = &gl_btc_trace_buf[0];
+static struct  coex_dm_8723b_1ant		glcoex_dm_8723b_1ant;
+static struct  coex_dm_8723b_1ant	*coex_dm = &glcoex_dm_8723b_1ant;
+static struct  coex_sta_8723b_1ant		glcoex_sta_8723b_1ant;
+static struct  coex_sta_8723b_1ant	*coex_sta = &glcoex_sta_8723b_1ant;
+static struct  psdscan_sta_8723b_1ant	gl_psd_scan_8723b_1ant;
+static struct  psdscan_sta_8723b_1ant *psd_scan = &gl_psd_scan_8723b_1ant;
+
+
+const char *const glbt_info_src_8723b_1ant[] = {
+	"BT Info[wifi fw]",
+	"BT Info[bt rsp]",
+	"BT Info[bt auto report]",
+};
+
+u32	glcoex_ver_date_8723b_1ant = 20161007;
+u32	glcoex_ver_8723b_1ant = 0x69;
+u32	glcoex_ver_btdesired_8723b_1ant = 0x69;
+
+/* ************************************************************
+ * local function proto type if needed
+ * ************************************************************
+ * ************************************************************
+ * local function start with halbtc8723b1ant_
+ * ************************************************************ */
+
+void halbtc8723b1ant_update_ra_mask(IN struct btc_coexist *btcoexist,
+				    IN boolean force_exec, IN u32 dis_rate_mask)
+{
+	coex_dm->cur_ra_mask = dis_rate_mask;
+
+	if (force_exec || (coex_dm->pre_ra_mask != coex_dm->cur_ra_mask))
+		btcoexist->btc_set(btcoexist, BTC_SET_ACT_UPDATE_RAMASK,
+				   &coex_dm->cur_ra_mask);
+	coex_dm->pre_ra_mask = coex_dm->cur_ra_mask;
+}
+
+void halbtc8723b1ant_auto_rate_fallback_retry(IN struct btc_coexist *btcoexist,
+		IN boolean force_exec, IN u8 type)
+{
+	boolean	wifi_under_b_mode = false;
+
+	coex_dm->cur_arfr_type = type;
+
+	if (force_exec || (coex_dm->pre_arfr_type != coex_dm->cur_arfr_type)) {
+		switch (coex_dm->cur_arfr_type) {
+		case 0:	/* normal mode */
+			btcoexist->btc_write_4byte(btcoexist, 0x430,
+						   coex_dm->backup_arfr_cnt1);
+			btcoexist->btc_write_4byte(btcoexist, 0x434,
+						   coex_dm->backup_arfr_cnt2);
+			break;
+		case 1:
+			btcoexist->btc_get(btcoexist,
+					   BTC_GET_BL_WIFI_UNDER_B_MODE,
+					   &wifi_under_b_mode);
+			if (wifi_under_b_mode) {
+				btcoexist->btc_write_4byte(btcoexist,
+							   0x430, 0x0);
+				btcoexist->btc_write_4byte(btcoexist,
+							   0x434, 0x01010101);
+			} else {
+				btcoexist->btc_write_4byte(btcoexist,
+							   0x430, 0x0);
+				btcoexist->btc_write_4byte(btcoexist,
+							   0x434, 0x04030201);
+			}
+			break;
+		default:
+			break;
+		}
+	}
+
+	coex_dm->pre_arfr_type = coex_dm->cur_arfr_type;
+}
+
+void halbtc8723b1ant_retry_limit(IN struct btc_coexist *btcoexist,
+				 IN boolean force_exec, IN u8 type)
+{
+	coex_dm->cur_retry_limit_type = type;
+
+	if (force_exec ||
+	    (coex_dm->pre_retry_limit_type !=
+	     coex_dm->cur_retry_limit_type)) {
+		switch (coex_dm->cur_retry_limit_type) {
+		case 0:	/* normal mode */
+			btcoexist->btc_write_2byte(btcoexist, 0x42a,
+						   coex_dm->backup_retry_limit);
+			break;
+		case 1:	/* retry limit=8 */
+			btcoexist->btc_write_2byte(btcoexist, 0x42a,
+						   0x0808);
+			break;
+		default:
+			break;
+		}
+	}
+
+	coex_dm->pre_retry_limit_type = coex_dm->cur_retry_limit_type;
+}
+
+void halbtc8723b1ant_ampdu_max_time(IN struct btc_coexist *btcoexist,
+				    IN boolean force_exec, IN u8 type)
+{
+	coex_dm->cur_ampdu_time_type = type;
+
+	if (force_exec ||
+	    (coex_dm->pre_ampdu_time_type != coex_dm->cur_ampdu_time_type)) {
+		switch (coex_dm->cur_ampdu_time_type) {
+		case 0:	/* normal mode */
+			btcoexist->btc_write_1byte(btcoexist, 0x456,
+					   coex_dm->backup_ampdu_max_time);
+			break;
+		case 1:	/* AMPDU timw = 0x38 * 32us */
+			btcoexist->btc_write_1byte(btcoexist, 0x456,
+						   0x38);
+			break;
+		default:
+			break;
+		}
+	}
+
+	coex_dm->pre_ampdu_time_type = coex_dm->cur_ampdu_time_type;
+}
+
+void halbtc8723b1ant_limited_tx(IN struct btc_coexist *btcoexist,
+		IN boolean force_exec, IN u8 ra_mask_type, IN u8 arfr_type,
+				IN u8 retry_limit_type, IN u8 ampdu_time_type)
+{
+	switch (ra_mask_type) {
+	case 0:	/* normal mode */
+		halbtc8723b1ant_update_ra_mask(btcoexist, force_exec,
+					       0x0);
+		break;
+	case 1:	/* disable cck 1/2 */
+		halbtc8723b1ant_update_ra_mask(btcoexist, force_exec,
+					       0x00000003);
+		break;
+	case 2:	/* disable cck 1/2/5.5, ofdm 6/9/12/18/24, mcs 0/1/2/3/4 */
+		halbtc8723b1ant_update_ra_mask(btcoexist, force_exec,
+					       0x0001f1f7);
+		break;
+	default:
+		break;
+	}
+
+	halbtc8723b1ant_auto_rate_fallback_retry(btcoexist, force_exec,
+			arfr_type);
+	halbtc8723b1ant_retry_limit(btcoexist, force_exec, retry_limit_type);
+	halbtc8723b1ant_ampdu_max_time(btcoexist, force_exec, ampdu_time_type);
+}
+
+void halbtc8723b1ant_limited_rx(IN struct btc_coexist *btcoexist,
+			IN boolean force_exec, IN boolean rej_ap_agg_pkt,
+			IN boolean bt_ctrl_agg_buf_size, IN u8 agg_buf_size)
+{
+	boolean	reject_rx_agg = rej_ap_agg_pkt;
+	boolean	bt_ctrl_rx_agg_size = bt_ctrl_agg_buf_size;
+	u8	rx_agg_size = agg_buf_size;
+
+	/* ============================================ */
+	/*	Rx Aggregation related setting */
+	/* ============================================ */
+	btcoexist->btc_set(btcoexist, BTC_SET_BL_TO_REJ_AP_AGG_PKT,
+			   &reject_rx_agg);
+	/* decide BT control aggregation buf size or not */
+	btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_CTRL_AGG_SIZE,
+			   &bt_ctrl_rx_agg_size);
+	/* aggregation buf size, only work when BT control Rx aggregation size. */
+	btcoexist->btc_set(btcoexist, BTC_SET_U1_AGG_BUF_SIZE, &rx_agg_size);
+	/* real update aggregation setting */
+	btcoexist->btc_set(btcoexist, BTC_SET_ACT_AGGREGATE_CTRL, NULL);
+
+
+}
+
+void halbtc8723b1ant_query_bt_info(IN struct btc_coexist *btcoexist)
+{
+	u8			h2c_parameter[1] = {0};
+
+	coex_sta->c2h_bt_info_req_sent = true;
+
+	h2c_parameter[0] |= BIT(0);	/* trigger */
+
+	btcoexist->btc_fill_h2c(btcoexist, 0x61, 1, h2c_parameter);
+}
+
+void halbtc8723b1ant_monitor_bt_ctr(IN struct btc_coexist *btcoexist)
+{
+	u32			reg_hp_txrx, reg_lp_txrx, u32tmp;
+	u32			reg_hp_tx = 0, reg_hp_rx = 0, reg_lp_tx = 0, reg_lp_rx = 0;
+	static u32		num_of_bt_counter_chk = 0;
+	struct  btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
+
+	/* to avoid 0x76e[3] = 1 (WLAN_Act control by PTA) during IPS */
+	/* if (! (btcoexist->btc_read_1byte(btcoexist, 0x76e) & 0x8) ) */
+
+	reg_hp_txrx = 0x770;
+	reg_lp_txrx = 0x774;
+
+	u32tmp = btcoexist->btc_read_4byte(btcoexist, reg_hp_txrx);
+	reg_hp_tx = u32tmp & MASKLWORD;
+	reg_hp_rx = (u32tmp & MASKHWORD) >> 16;
+
+	u32tmp = btcoexist->btc_read_4byte(btcoexist, reg_lp_txrx);
+	reg_lp_tx = u32tmp & MASKLWORD;
+	reg_lp_rx = (u32tmp & MASKHWORD) >> 16;
+
+	coex_sta->high_priority_tx = reg_hp_tx;
+	coex_sta->high_priority_rx = reg_hp_rx;
+	coex_sta->low_priority_tx = reg_lp_tx;
+	coex_sta->low_priority_rx = reg_lp_rx;
+
+	if ((coex_sta->high_priority_tx  + coex_sta->high_priority_rx < 50) &&
+	    (bt_link_info->hid_exist == true))
+		bt_link_info->hid_exist  = false;
+
+	if ((coex_sta->low_priority_tx > 1050)  &&
+	    (!coex_sta->c2h_bt_inquiry_page))
+		coex_sta->pop_event_cnt++;
+
+	if ((coex_sta->low_priority_rx >= 950)  && (!coex_sta->under_ips)
+	    && (coex_sta->low_priority_rx >=
+		coex_sta->low_priority_tx)  &&
+	    (!coex_sta->c2h_bt_inquiry_page))
+		bt_link_info->slave_role = true;
+	else
+		bt_link_info->slave_role = false;
+
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+		    "[BTCoex], Hi-Pri Rx/Tx: %d/%d, Lo-Pri Rx/Tx: %d/%d\n",
+		    reg_hp_rx, reg_hp_tx, reg_lp_rx, reg_lp_tx);
+	BTC_TRACE(trace_buf);
+
+	/* reset counter */
+	btcoexist->btc_write_1byte(btcoexist, 0x76e, 0xc);
+
+	/* This part is for wifi FW and driver to update BT's status as disabled. */
+	/* The flow is as the following */
+	/* 1. disable BT */
+	/* 2. if all BT Tx/Rx counter=0, after 6 sec we query bt info */
+	/* 3. Because BT will not rsp from mailbox, so wifi fw will know BT is disabled */
+	/* 4. FW will rsp c2h for BT that driver will know BT is disabled. */
+	if ((reg_hp_tx == 0) && (reg_hp_rx == 0) && (reg_lp_tx == 0) &&
+	    (reg_lp_rx == 0)) {
+		num_of_bt_counter_chk++;
+		if (num_of_bt_counter_chk >= 3) {
+			halbtc8723b1ant_query_bt_info(btcoexist);
+			num_of_bt_counter_chk = 0;
+		}
+	}
+
+}
+
+
+void halbtc8723b1ant_monitor_wifi_ctr(IN struct btc_coexist *btcoexist)
+{
+	s32	wifi_rssi = 0;
+	boolean wifi_busy = false, wifi_under_b_mode = false;
+	static u8 cck_lock_counter = 0;
+	u32	total_cnt;
+
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy);
+	btcoexist->btc_get(btcoexist, BTC_GET_S4_WIFI_RSSI, &wifi_rssi);
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_B_MODE,
+			   &wifi_under_b_mode);
+
+#if 1
+
+	coex_sta->crc_ok_cck = btcoexist->btc_phydm_query_PHY_counter(
+				       btcoexist,
+				       PHYDM_INFO_CRC32_OK_CCK);
+	coex_sta->crc_ok_11g = btcoexist->btc_phydm_query_PHY_counter(
+				       btcoexist,
+				       PHYDM_INFO_CRC32_OK_LEGACY);
+	coex_sta->crc_ok_11n = btcoexist->btc_phydm_query_PHY_counter(
+				       btcoexist,
+				       PHYDM_INFO_CRC32_OK_HT);
+	coex_sta->crc_ok_11n_vht =
+		btcoexist->btc_phydm_query_PHY_counter(
+			btcoexist,
+			PHYDM_INFO_CRC32_OK_VHT);
+
+	coex_sta->crc_err_cck = btcoexist->btc_phydm_query_PHY_counter(
+					btcoexist,
+					PHYDM_INFO_CRC32_ERROR_CCK);
+	coex_sta->crc_err_11g =  btcoexist->btc_phydm_query_PHY_counter(
+					 btcoexist,
+					 PHYDM_INFO_CRC32_ERROR_LEGACY);
+	coex_sta->crc_err_11n = btcoexist->btc_phydm_query_PHY_counter(
+					btcoexist,
+					PHYDM_INFO_CRC32_ERROR_HT);
+	coex_sta->crc_err_11n_vht =
+		btcoexist->btc_phydm_query_PHY_counter(
+			btcoexist,
+			PHYDM_INFO_CRC32_ERROR_VHT);
+
+#endif
+
+	if ((wifi_busy) && (wifi_rssi >= 30) && (!wifi_under_b_mode)) {
+		total_cnt = coex_sta->crc_ok_cck + coex_sta->crc_ok_11g +
+			    coex_sta->crc_ok_11n +
+			    coex_sta->crc_ok_11n_vht;
+
+		if ((coex_dm->bt_status == BT_8723B_1ANT_BT_STATUS_ACL_BUSY) ||
+		    (coex_dm->bt_status ==
+		     BT_8723B_1ANT_BT_STATUS_ACL_SCO_BUSY) ||
+		    (coex_dm->bt_status ==
+		     BT_8723B_1ANT_BT_STATUS_SCO_BUSY)) {
+			if (coex_sta->crc_ok_cck > (total_cnt -
+						    coex_sta->crc_ok_cck))			{
+				if (cck_lock_counter < 3)
+					cck_lock_counter++;
+			} else {
+				if (cck_lock_counter > 0)
+					cck_lock_counter--;
+			}
+
+		} else {
+			if (cck_lock_counter > 0)
+				cck_lock_counter--;
+		}
+	} else {
+		if (cck_lock_counter > 0)
+			cck_lock_counter--;
+	}
+
+	if (!coex_sta->pre_ccklock) {
+
+		if (cck_lock_counter >= 3)
+			coex_sta->cck_lock = true;
+		else
+			coex_sta->cck_lock = false;
+	} else {
+		if (cck_lock_counter == 0)
+			coex_sta->cck_lock = false;
+		else
+			coex_sta->cck_lock = true;
+	}
+
+	if (coex_sta->cck_lock)
+		coex_sta->cck_ever_lock = true;
+
+	coex_sta->pre_ccklock =  coex_sta->cck_lock;
+
+
+}
+
+boolean halbtc8723b1ant_is_wifi_status_changed(IN struct btc_coexist *btcoexist)
+{
+	static boolean	pre_wifi_busy = false, pre_under_4way = false,
+			pre_bt_hs_on = false;
+	boolean wifi_busy = false, under_4way = false, bt_hs_on = false;
+	boolean wifi_connected = false;
+
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED,
+			   &wifi_connected);
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy);
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on);
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_4_WAY_PROGRESS,
+			   &under_4way);
+
+	if (wifi_connected) {
+		if (wifi_busy != pre_wifi_busy) {
+			pre_wifi_busy = wifi_busy;
+			return true;
+		}
+		if (under_4way != pre_under_4way) {
+			pre_under_4way = under_4way;
+			return true;
+		}
+		if (bt_hs_on != pre_bt_hs_on) {
+			pre_bt_hs_on = bt_hs_on;
+			return true;
+		}
+
+
+	}
+
+	return false;
+}
+
+void halbtc8723b1ant_monitor_bt_enable_disable(IN struct btc_coexist *btcoexist)
+{
+	static u32		bt_disable_cnt = 0;
+	boolean			bt_active = true, bt_disabled = false, bt_change = false;
+
+	/* This function check if bt is disabled */
+
+	if (coex_sta->high_priority_tx == 0 &&
+	    coex_sta->high_priority_rx == 0 &&
+	    coex_sta->low_priority_tx == 0 &&
+	    coex_sta->low_priority_rx == 0)
+		bt_active = false;
+	if (coex_sta->high_priority_tx == 0xffff &&
+	    coex_sta->high_priority_rx == 0xffff &&
+	    coex_sta->low_priority_tx == 0xffff &&
+	    coex_sta->low_priority_rx == 0xffff)
+		bt_active = false;
+	if (bt_active) {
+		bt_disable_cnt = 0;
+		bt_disabled = false;
+	} else {
+		bt_disable_cnt++;
+		if (bt_disable_cnt >= 10)
+			bt_disabled = true;
+	}
+	if (coex_sta->bt_disabled != bt_disabled) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], BT is from %s to %s!!\n",
+			    (coex_sta->bt_disabled ? "disabled" : "enabled"),
+			    (bt_disabled ? "disabled" : "enabled"));
+		BTC_TRACE(trace_buf);
+		bt_change = true;
+
+		btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_DISABLE,
+				   &bt_disabled);
+
+		btcoexist->btc_set(btcoexist,
+				   BTC_SET_BL_BT_ENABLE_DISABLE_CHANGE,
+				   &bt_change);
+
+		coex_sta->bt_disabled = bt_disabled;
+	} else {
+		btcoexist->btc_set(btcoexist,
+				   BTC_SET_BL_BT_ENABLE_DISABLE_CHANGE,
+				   &bt_change);
+	}
+}
+
+void halbtc8723b1ant_update_bt_link_info(IN struct btc_coexist *btcoexist)
+{
+	struct  btc_bt_link_info	*bt_link_info = &btcoexist->bt_link_info;
+	boolean				bt_hs_on = false;
+
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on);
+
+	bt_link_info->bt_link_exist = coex_sta->bt_link_exist;
+	bt_link_info->sco_exist = coex_sta->sco_exist;
+	bt_link_info->a2dp_exist = coex_sta->a2dp_exist;
+	bt_link_info->pan_exist = coex_sta->pan_exist;
+	bt_link_info->hid_exist = coex_sta->hid_exist;
+	bt_link_info->bt_hi_pri_link_exist = coex_sta->bt_hi_pri_link_exist;
+
+	/* work around for HS mode. */
+	if (bt_hs_on) {
+		bt_link_info->pan_exist = true;
+		bt_link_info->bt_link_exist = true;
+	}
+
+	/* check if Sco only */
+	if (bt_link_info->sco_exist &&
+	    !bt_link_info->a2dp_exist &&
+	    !bt_link_info->pan_exist &&
+	    !bt_link_info->hid_exist)
+		bt_link_info->sco_only = true;
+	else
+		bt_link_info->sco_only = false;
+
+	/* check if A2dp only */
+	if (!bt_link_info->sco_exist &&
+	    bt_link_info->a2dp_exist &&
+	    !bt_link_info->pan_exist &&
+	    !bt_link_info->hid_exist)
+		bt_link_info->a2dp_only = true;
+	else
+		bt_link_info->a2dp_only = false;
+
+	/* check if Pan only */
+	if (!bt_link_info->sco_exist &&
+	    !bt_link_info->a2dp_exist &&
+	    bt_link_info->pan_exist &&
+	    !bt_link_info->hid_exist)
+		bt_link_info->pan_only = true;
+	else
+		bt_link_info->pan_only = false;
+
+	/* check if Hid only */
+	if (!bt_link_info->sco_exist &&
+	    !bt_link_info->a2dp_exist &&
+	    !bt_link_info->pan_exist &&
+	    bt_link_info->hid_exist)
+		bt_link_info->hid_only = true;
+	else
+		bt_link_info->hid_only = false;
+}
+
+void halbtc8723b1ant_set_bt_auto_report(IN struct btc_coexist *btcoexist,
+					IN boolean enable_auto_report)
+{
+	u8			h2c_parameter[1] = {0};
+
+	h2c_parameter[0] = 0;
+
+	if (enable_auto_report)
+		h2c_parameter[0] |= BIT(0);
+
+	btcoexist->btc_fill_h2c(btcoexist, 0x68, 1, h2c_parameter);
+}
+
+void halbtc8723b1ant_bt_auto_report(IN struct btc_coexist *btcoexist,
+		    IN boolean force_exec, IN boolean enable_auto_report)
+{
+	coex_dm->cur_bt_auto_report = enable_auto_report;
+
+	if (!force_exec) {
+		if (coex_dm->pre_bt_auto_report == coex_dm->cur_bt_auto_report)
+			return;
+	}
+	halbtc8723b1ant_set_bt_auto_report(btcoexist,
+					   coex_dm->cur_bt_auto_report);
+
+	coex_dm->pre_bt_auto_report = coex_dm->cur_bt_auto_report;
+}
+
+void halbtc8723b1ant_set_sw_penalty_tx_rate_adaptive(IN struct btc_coexist
+		*btcoexist, IN boolean low_penalty_ra)
+{
+	u8			h2c_parameter[6] = {0};
+
+	h2c_parameter[0] = 0x6;	/* op_code, 0x6= Retry_Penalty */
+
+	if (low_penalty_ra) {
+		h2c_parameter[1] |= BIT(0);
+		h2c_parameter[2] =
+			0x00;  /* normal rate except MCS7/6/5, OFDM54/48/36 */
+		h2c_parameter[3] = 0xf7;  /* MCS7 or OFDM54 */
+		h2c_parameter[4] = 0xf8;  /* MCS6 or OFDM48 */
+		h2c_parameter[5] = 0xf9;	/* MCS5 or OFDM36	 */
+	}
+
+	btcoexist->btc_fill_h2c(btcoexist, 0x69, 6, h2c_parameter);
+}
+
+void halbtc8723b1ant_low_penalty_ra(IN struct btc_coexist *btcoexist,
+			    IN boolean force_exec, IN boolean low_penalty_ra)
+{
+	coex_dm->cur_low_penalty_ra = low_penalty_ra;
+
+	if (!force_exec) {
+		if (coex_dm->pre_low_penalty_ra == coex_dm->cur_low_penalty_ra)
+			return;
+	}
+	halbtc8723b1ant_set_sw_penalty_tx_rate_adaptive(btcoexist,
+			coex_dm->cur_low_penalty_ra);
+
+	coex_dm->pre_low_penalty_ra = coex_dm->cur_low_penalty_ra;
+}
+
+void halbtc8723b1ant_sw_mechanism(IN struct btc_coexist *btcoexist,
+				  IN boolean low_penalty_ra)
+{
+	halbtc8723b1ant_low_penalty_ra(btcoexist, NORMAL_EXEC, low_penalty_ra);
+}
+
+void halbtc8723b1ant_set_coex_table(IN struct btc_coexist *btcoexist,
+	    IN u32 val0x6c0, IN u32 val0x6c4, IN u32 val0x6c8, IN u8 val0x6cc)
+{
+	btcoexist->btc_write_4byte(btcoexist, 0x6c0, val0x6c0);
+
+	btcoexist->btc_write_4byte(btcoexist, 0x6c4, val0x6c4);
+
+	btcoexist->btc_write_4byte(btcoexist, 0x6c8, val0x6c8);
+
+	btcoexist->btc_write_1byte(btcoexist, 0x6cc, val0x6cc);
+}
+
+
+
+void halbtc8723b1ant_coex_table(IN struct btc_coexist *btcoexist,
+			IN boolean force_exec, IN u32 val0x6c0, IN u32 val0x6c4,
+				IN u32 val0x6c8, IN u8 val0x6cc)
+{
+	coex_dm->cur_val0x6c0 = val0x6c0;
+	coex_dm->cur_val0x6c4 = val0x6c4;
+	coex_dm->cur_val0x6c8 = val0x6c8;
+	coex_dm->cur_val0x6cc = val0x6cc;
+
+	if (!force_exec) {
+		if ((coex_dm->pre_val0x6c0 == coex_dm->cur_val0x6c0) &&
+		    (coex_dm->pre_val0x6c4 == coex_dm->cur_val0x6c4) &&
+		    (coex_dm->pre_val0x6c8 == coex_dm->cur_val0x6c8) &&
+		    (coex_dm->pre_val0x6cc == coex_dm->cur_val0x6cc))
+			return;
+	}
+	halbtc8723b1ant_set_coex_table(btcoexist, val0x6c0, val0x6c4, val0x6c8,
+				       val0x6cc);
+
+	coex_dm->pre_val0x6c0 = coex_dm->cur_val0x6c0;
+	coex_dm->pre_val0x6c4 = coex_dm->cur_val0x6c4;
+	coex_dm->pre_val0x6c8 = coex_dm->cur_val0x6c8;
+	coex_dm->pre_val0x6cc = coex_dm->cur_val0x6cc;
+}
+
+void halbtc8723b1ant_coex_table_with_type(IN struct btc_coexist *btcoexist,
+		IN boolean force_exec, IN u8 type)
+{
+	struct  btc_board_info	*board_info = &btcoexist->board_info;
+
+#if BT_8723B_1ANT_ANTDET_ENABLE
+#if BT_8723B_1ANT_ANTDET_COEXMECHANISMSWITCH_ENABLE
+	if (board_info->btdm_ant_num_by_ant_det == 2) {
+		if (type == 3)
+			type = 14;
+		else if (type == 4)
+			type  = 13;
+		else if (type == 5)
+			type = 8;
+	}
+#endif
+#endif
+
+	coex_sta->coex_table_type = type;
+
+	switch (type) {
+	case 0:
+		halbtc8723b1ant_coex_table(btcoexist, force_exec,
+				   0x55555555, 0x55555555, 0xffffff, 0x3);
+		break;
+	case 1:
+		halbtc8723b1ant_coex_table(btcoexist, force_exec,
+				   0x55555555, 0x5a5a5a5a, 0xffffff, 0x3);
+		break;
+	case 2:
+		halbtc8723b1ant_coex_table(btcoexist, force_exec,
+				   0x5a5a5a5a, 0x5a5a5a5a, 0xffffff, 0x3);
+		break;
+	case 3:
+		halbtc8723b1ant_coex_table(btcoexist, force_exec,
+				   0x55555555, 0x5a5a5a5a, 0xffffff, 0x3);
+		break;
+	case 4:
+		if ((coex_sta->cck_ever_lock)  &&
+		    (coex_sta->scan_ap_num <= 5))
+			halbtc8723b1ant_coex_table(btcoexist,
+					   force_exec, 0x55555555, 0xaaaa5a5a,
+						   0xffffff, 0x3);
+		else
+			halbtc8723b1ant_coex_table(btcoexist,
+					   force_exec, 0x55555555, 0x5a5a5a5a,
+						   0xffffff, 0x3);
+		break;
+	case 5:
+		if ((coex_sta->cck_ever_lock)  &&
+		    (coex_sta->scan_ap_num <= 5))
+			halbtc8723b1ant_coex_table(btcoexist,
+					   force_exec, 0x5a5a5a5a, 0x5aaa5a5a,
+						   0xffffff, 0x3);
+		else
+			halbtc8723b1ant_coex_table(btcoexist,
+					   force_exec, 0x5a5a5a5a, 0x5aaa5a5a,
+						   0xffffff, 0x3);
+		break;
+	case 6:
+		halbtc8723b1ant_coex_table(btcoexist, force_exec,
+				   0x55555555, 0xaaaaaaaa, 0xffffff, 0x3);
+		break;
+	case 7:
+		halbtc8723b1ant_coex_table(btcoexist, force_exec,
+				   0xaaaaaaaa, 0xaaaaaaaa, 0xffffff, 0x3);
+		break;
+	case 8:
+		halbtc8723b1ant_coex_table(btcoexist, force_exec,
+				   0x55dd55dd, 0x5ada5ada, 0xffffff, 0x3);
+		break;
+	case 9:
+		halbtc8723b1ant_coex_table(btcoexist, force_exec,
+				   0x55dd55dd, 0x5ada5ada, 0xffffff, 0x3);
+		break;
+	case 10:
+		halbtc8723b1ant_coex_table(btcoexist, force_exec,
+				   0x55dd55dd, 0x5ada5ada, 0xffffff, 0x3);
+		break;
+	case 11:
+		halbtc8723b1ant_coex_table(btcoexist, force_exec,
+				   0x55dd55dd, 0x5ada5ada, 0xffffff, 0x3);
+		break;
+	case 12:
+		halbtc8723b1ant_coex_table(btcoexist, force_exec,
+				   0x55dd55dd, 0x5ada5ada, 0xffffff, 0x3);
+		break;
+	case 13:
+		halbtc8723b1ant_coex_table(btcoexist, force_exec,
+				   0x5fff5fff, 0xaaaaaaaa, 0xffffff, 0x3);
+		break;
+	case 14:
+		halbtc8723b1ant_coex_table(btcoexist, force_exec,
+				   0x5fff5fff, 0x5ada5ada, 0xffffff, 0x3);
+		break;
+	case 15:
+		halbtc8723b1ant_coex_table(btcoexist, force_exec,
+				   0x55dd55dd, 0xaaaaaaaa, 0xffffff, 0x3);
+		break;
+	default:
+		break;
+	}
+}
+
+void halbtc8723b1ant_set_fw_ignore_wlan_act(IN struct btc_coexist *btcoexist,
+		IN boolean enable)
+{
+	u8			h2c_parameter[1] = {0};
+
+	if (enable)
+		h2c_parameter[0] |= BIT(0);		/* function enable */
+
+	btcoexist->btc_fill_h2c(btcoexist, 0x63, 1, h2c_parameter);
+}
+
+void halbtc8723b1ant_ignore_wlan_act(IN struct btc_coexist *btcoexist,
+				     IN boolean force_exec, IN boolean enable)
+{
+	coex_dm->cur_ignore_wlan_act = enable;
+
+	if (!force_exec) {
+		if (coex_dm->pre_ignore_wlan_act ==
+		    coex_dm->cur_ignore_wlan_act)
+			return;
+	}
+	halbtc8723b1ant_set_fw_ignore_wlan_act(btcoexist, enable);
+
+	coex_dm->pre_ignore_wlan_act = coex_dm->cur_ignore_wlan_act;
+}
+
+void halbtc8723b1ant_set_lps_rpwm(IN struct btc_coexist *btcoexist,
+				  IN u8 lps_val, IN u8 rpwm_val)
+{
+	u8	lps = lps_val;
+	u8	rpwm = rpwm_val;
+
+	btcoexist->btc_set(btcoexist, BTC_SET_U1_LPS_VAL, &lps);
+	btcoexist->btc_set(btcoexist, BTC_SET_U1_RPWM_VAL, &rpwm);
+}
+
+void halbtc8723b1ant_lps_rpwm(IN struct btc_coexist *btcoexist,
+		      IN boolean force_exec, IN u8 lps_val, IN u8 rpwm_val)
+{
+	coex_dm->cur_lps = lps_val;
+	coex_dm->cur_rpwm = rpwm_val;
+
+	if (!force_exec) {
+		if ((coex_dm->pre_lps == coex_dm->cur_lps) &&
+		    (coex_dm->pre_rpwm == coex_dm->cur_rpwm))
+			return;
+	}
+	halbtc8723b1ant_set_lps_rpwm(btcoexist, lps_val, rpwm_val);
+
+	coex_dm->pre_lps = coex_dm->cur_lps;
+	coex_dm->pre_rpwm = coex_dm->cur_rpwm;
+}
+
+void halbtc8723b1ant_set_ant_path(IN struct btc_coexist *btcoexist,
+	  IN u8 ant_pos_type, IN boolean force_exec, IN boolean init_hwcfg,
+				  IN boolean wifi_off)
+{
+	struct  btc_board_info *board_info = &btcoexist->board_info;
+	u32			fw_ver = 0, u32tmp = 0, cnt_bt_cal_chk = 0;
+	boolean			pg_ext_switch = false;
+	boolean			use_ext_switch = false;
+	boolean			is_in_mp_mode = false;
+	u8			h2c_parameter[2] = {0}, u8tmp = 0;
+	u32         u32tmp_1[4];
+	boolean		is_fw_ready;
+
+	coex_dm->cur_ant_pos_type = ant_pos_type;
+
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_EXT_SWITCH, &pg_ext_switch);
+	btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_FW_VER,
+			   &fw_ver);	/* [31:16]=fw ver, [15:0]=fw sub ver */
+
+	if ((fw_ver > 0 && fw_ver < 0xc0000) || pg_ext_switch)
+		use_ext_switch = true;
+
+#if BT_8723B_1ANT_ANTDET_ENABLE
+#if BT_8723B_1ANT_ANTDET_COEXMECHANISMSWITCH_ENABLE
+	if (ant_pos_type == BTC_ANT_PATH_PTA) {
+		if ((board_info->btdm_ant_det_finish) &&
+		    (board_info->btdm_ant_num_by_ant_det == 2)) {
+			if (board_info->btdm_ant_pos ==
+			    BTC_ANTENNA_AT_MAIN_PORT)
+				ant_pos_type = BTC_ANT_PATH_WIFI;
+			else
+				ant_pos_type = BTC_ANT_PATH_BT;
+		}
+	}
+#endif
+#endif
+
+	if (init_hwcfg) {
+		btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1, 0xfffff,
+					  0x780); /* WiFi TRx Mask on */
+		/* remove due to interrupt is disabled that polling c2h will fail and delay 100ms. */
+		/* btcoexist->btc_set_bt_reg(btcoexist, BTC_BT_REG_RF, 0x3c, 0x15); */ /*BT TRx Mask on */
+
+		if (fw_ver >= 0x180000) {
+			/* Use H2C to set GNT_BT to HIGH */
+			h2c_parameter[0] = 1;
+			btcoexist->btc_fill_h2c(btcoexist, 0x6E, 1,
+						h2c_parameter);
+
+			cnt_bt_cal_chk = 0;
+			while (1) {
+				btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_FW_READY, &is_fw_ready);
+				if (is_fw_ready == false) {
+					BTC_SPRINTF(trace_buf , BT_TMP_BUF_SIZE,
+						("halbtc8723b1ant_set_ant_path(): we don't need to wait for H2C command completion because of Fw download fail!!!\n"));
+					BTC_TRACE(trace_buf);
+					break;
+				}
+
+				if (btcoexist->btc_read_1byte(btcoexist,
+							      0x765) == 0x18)
+					break;
+
+				cnt_bt_cal_chk++;
+				if (cnt_bt_cal_chk > 20)
+					break;
+			}
+		} else {
+			/* set grant_bt to high */
+			btcoexist->btc_write_1byte(btcoexist, 0x765, 0x18);
+		}
+		/* set wlan_act control by PTA */
+		btcoexist->btc_write_1byte(btcoexist, 0x76e, 0x4);
+
+		btcoexist->btc_write_1byte_bitmask(btcoexist, 0x67, 0x20,
+			   0x0); /* BT select s0/s1 is controlled by BT */
+
+		btcoexist->btc_write_1byte_bitmask(btcoexist, 0x39, 0x8, 0x1);
+		btcoexist->btc_write_1byte(btcoexist, 0x974, 0xff);
+		btcoexist->btc_write_1byte_bitmask(btcoexist, 0x944, 0x3, 0x3);
+		btcoexist->btc_write_1byte(btcoexist, 0x930, 0x77);
+	} else if (wifi_off) {
+		if (fw_ver >= 0x180000) {
+			/* Use H2C to set GNT_BT to HIGH */
+			h2c_parameter[0] = 1;
+			btcoexist->btc_fill_h2c(btcoexist, 0x6E, 1,
+						h2c_parameter);
+
+			cnt_bt_cal_chk = 0;
+			while (1) {
+				btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_FW_READY, &is_fw_ready);
+				if (is_fw_ready == false) {
+					BTC_SPRINTF(trace_buf , BT_TMP_BUF_SIZE,
+						("halbtc8723b1ant_set_ant_path(): we don't need to wait for H2C command completion because of Fw download fail!!!\n"));
+					BTC_TRACE(trace_buf);
+					break;
+				}
+
+				if (btcoexist->btc_read_1byte(btcoexist,
+							      0x765) == 0x18)
+					break;
+
+				cnt_bt_cal_chk++;
+				if (cnt_bt_cal_chk > 20)
+					break;
+			}
+		} else {
+			/* set grant_bt to high */
+			btcoexist->btc_write_1byte(btcoexist, 0x765, 0x18);
+		}
+		/* set wlan_act to always low */
+		btcoexist->btc_write_1byte(btcoexist, 0x76e, 0x4);
+
+		btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_IS_IN_MP_MODE,
+				   &is_in_mp_mode);
+		if (!is_in_mp_mode)
+			btcoexist->btc_write_1byte_bitmask(btcoexist, 0x67,
+				0x20, 0x0); /* BT select s0/s1 is controlled by BT */
+		else
+			btcoexist->btc_write_1byte_bitmask(btcoexist, 0x67,
+				0x20, 0x1); /* BT select s0/s1 is controlled by WiFi */
+
+		/* 0x4c[24:23]=00, Set Antenna control by BT_RFE_CTRL	BT Vendor 0xac=0xf002 */
+		u32tmp = btcoexist->btc_read_4byte(btcoexist, 0x4c);
+		u32tmp &= ~BIT(23);
+		u32tmp &= ~BIT(24);
+		btcoexist->btc_write_4byte(btcoexist, 0x4c, u32tmp);
+	} else {
+		/* Use H2C to set GNT_BT to LOW */
+		if (fw_ver >= 0x180000) {
+			if (btcoexist->btc_read_1byte(btcoexist, 0x765) != 0) {
+				h2c_parameter[0] = 0;
+				btcoexist->btc_fill_h2c(btcoexist, 0x6E, 1,
+							h2c_parameter);
+
+				cnt_bt_cal_chk = 0;
+				while (1) {
+					btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_FW_READY, &is_fw_ready);
+					if (is_fw_ready == false) {
+						BTC_SPRINTF(trace_buf ,
+							    BT_TMP_BUF_SIZE,
+							("halbtc8723b1ant_set_ant_path(): we don't need to wait for H2C command completion because of Fw download fail!!!\n"));
+						BTC_TRACE(trace_buf);
+						break;
+					}
+
+					if (btcoexist->btc_read_1byte(btcoexist,
+							      0x765) == 0x0)
+						break;
+
+					cnt_bt_cal_chk++;
+					if (cnt_bt_cal_chk > 20)
+						break;
+				}
+			}
+		} else {
+			/* BT calibration check */
+			while (cnt_bt_cal_chk <= 20) {
+				u8tmp = btcoexist->btc_read_1byte(btcoexist,
+								  0x49d);
+				cnt_bt_cal_chk++;
+				if (u8tmp & BIT(0)) {
+					BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+						"[BTCoex], ########### BT is calibrating (wait cnt=%d) ###########\n",
+						    cnt_bt_cal_chk);
+					BTC_TRACE(trace_buf);
+					delay_ms(50);
+				} else {
+					BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+						"[BTCoex], ********** BT is NOT calibrating (wait cnt=%d)**********\n",
+						    cnt_bt_cal_chk);
+					BTC_TRACE(trace_buf);
+					break;
+				}
+			}
+
+			/* set grant_bt to PTA */
+			btcoexist->btc_write_1byte(btcoexist, 0x765, 0x0);
+		}
+
+		if (btcoexist->btc_read_1byte(btcoexist, 0x76e) != 0xc) {
+			/* set wlan_act control by PTA */
+			btcoexist->btc_write_1byte(btcoexist, 0x76e, 0xc);
+		}
+
+		btcoexist->btc_write_1byte_bitmask(btcoexist, 0x67, 0x20,
+			   0x1); /* BT select s0/s1 is controlled by WiFi */
+	}
+
+	if (use_ext_switch) {
+		if (init_hwcfg) {
+			/* 0x4c[23]=0, 0x4c[24]=1  Antenna control by WL/BT */
+			u32tmp = btcoexist->btc_read_4byte(btcoexist, 0x4c);
+			u32tmp &= ~BIT(23);
+			u32tmp |= BIT(24);
+			btcoexist->btc_write_4byte(btcoexist, 0x4c, u32tmp);
+
+
+			u32tmp_1[0] = btcoexist->btc_read_4byte(btcoexist,
+								0x948);
+			if ((u32tmp_1[0] == 0x40) || (u32tmp_1[0] == 0x240))
+				btcoexist->btc_write_4byte(btcoexist, 0x948,
+							   u32tmp_1[0]);
+			else
+				btcoexist->btc_write_4byte(btcoexist, 0x948,
+							   0x0);
+
+
+			if (board_info->btdm_ant_pos ==
+			    BTC_ANTENNA_AT_MAIN_PORT) {
+				/* tell firmware "no antenna inverse" */
+				h2c_parameter[0] = 0;
+				h2c_parameter[1] = 1;  /* ext switch type */
+				btcoexist->btc_fill_h2c(btcoexist, 0x65, 2,
+							h2c_parameter);
+			} else {
+				/* tell firmware "antenna inverse" */
+				h2c_parameter[0] = 1;
+				h2c_parameter[1] = 1;  /* ext switch type */
+				btcoexist->btc_fill_h2c(btcoexist, 0x65, 2,
+							h2c_parameter);
+			}
+		}
+
+		if (force_exec ||
+		    (coex_dm->cur_ant_pos_type !=
+		     coex_dm->pre_ant_pos_type)) {
+			/* ext switch setting */
+			switch (ant_pos_type) {
+			case BTC_ANT_PATH_WIFI:
+				if (board_info->btdm_ant_pos ==
+				    BTC_ANTENNA_AT_MAIN_PORT)
+					btcoexist->btc_write_1byte_bitmask(
+						btcoexist, 0x92c, 0x3,
+						0x1);
+				else
+					btcoexist->btc_write_1byte_bitmask(
+						btcoexist, 0x92c, 0x3,
+						0x2);
+				break;
+			case BTC_ANT_PATH_BT:
+				if (board_info->btdm_ant_pos ==
+				    BTC_ANTENNA_AT_MAIN_PORT)
+					btcoexist->btc_write_1byte_bitmask(
+						btcoexist, 0x92c, 0x3,
+						0x2);
+				else
+					btcoexist->btc_write_1byte_bitmask(
+						btcoexist, 0x92c, 0x3,
+						0x1);
+				break;
+			default:
+			case BTC_ANT_PATH_PTA:
+				if (board_info->btdm_ant_pos ==
+				    BTC_ANTENNA_AT_MAIN_PORT)
+					btcoexist->btc_write_1byte_bitmask(
+						btcoexist, 0x92c, 0x3,
+						0x1);
+				else
+					btcoexist->btc_write_1byte_bitmask(
+						btcoexist, 0x92c, 0x3,
+						0x2);
+				break;
+			}
+		}
+	} else {
+		if (init_hwcfg) {
+			/* 0x4c[23]=1, 0x4c[24]=0  Antenna control by 0x64 */
+			u32tmp = btcoexist->btc_read_4byte(btcoexist, 0x4c);
+			u32tmp |= BIT(23);
+			u32tmp &= ~BIT(24);
+			btcoexist->btc_write_4byte(btcoexist, 0x4c, u32tmp);
+
+			/* Fix Ext switch Main->S1, Aux->S0 */
+			btcoexist->btc_write_1byte_bitmask(btcoexist, 0x64, 0x1,
+							   0x0);
+
+			if (board_info->btdm_ant_pos ==
+			    BTC_ANTENNA_AT_MAIN_PORT) {
+
+				/* tell firmware "no antenna inverse" */
+				h2c_parameter[0] = 0;
+				h2c_parameter[1] =
+					0;  /* internal switch type */
+				btcoexist->btc_fill_h2c(btcoexist, 0x65, 2,
+							h2c_parameter);
+			} else {
+
+				/* tell firmware "antenna inverse" */
+				h2c_parameter[0] = 1;
+				h2c_parameter[1] =
+					0;  /* internal switch type */
+				btcoexist->btc_fill_h2c(btcoexist, 0x65, 2,
+							h2c_parameter);
+			}
+		}
+
+		if (force_exec ||
+		    (coex_dm->cur_ant_pos_type !=
+		     coex_dm->pre_ant_pos_type)) {
+			/* internal switch setting */
+			switch (ant_pos_type) {
+			case BTC_ANT_PATH_WIFI:
+				if (board_info->btdm_ant_pos ==
+				    BTC_ANTENNA_AT_MAIN_PORT) {
+					u32tmp_1[0] = btcoexist->btc_read_4byte(
+							      btcoexist, 0x948);
+					if ((u32tmp_1[0] == 0x40) ||
+					    (u32tmp_1[0] == 0x240))
+						btcoexist->btc_write_4byte(
+							btcoexist, 0x948,
+							u32tmp_1[0]);
+					else
+						btcoexist->btc_write_4byte(
+							btcoexist, 0x948, 0x0);
+				} else {
+					u32tmp_1[0] = btcoexist->btc_read_4byte(
+							      btcoexist, 0x948);
+					if ((u32tmp_1[0] == 0x40) ||
+					    (u32tmp_1[0] == 0x240))
+						btcoexist->btc_write_4byte(
+							btcoexist, 0x948,
+							u32tmp_1[0]);
+					else
+						btcoexist->btc_write_4byte(
+							btcoexist, 0x948,
+							0x280);
+				}
+				break;
+			case BTC_ANT_PATH_BT:
+				if (board_info->btdm_ant_pos ==
+				    BTC_ANTENNA_AT_MAIN_PORT) {
+					u32tmp_1[0] = btcoexist->btc_read_4byte(
+							      btcoexist, 0x948);
+					if ((u32tmp_1[0] == 0x40) ||
+					    (u32tmp_1[0] == 0x240))
+						btcoexist->btc_write_4byte(
+							btcoexist, 0x948,
+							u32tmp_1[0]);
+					else
+						btcoexist->btc_write_4byte(
+							btcoexist, 0x948,
+							0x280);
+				} else {
+					u32tmp_1[0] = btcoexist->btc_read_4byte(
+							      btcoexist, 0x948);
+					if ((u32tmp_1[0] == 0x40) ||
+					    (u32tmp_1[0] == 0x240))
+						btcoexist->btc_write_4byte(
+							btcoexist, 0x948,
+							u32tmp_1[0]);
+					else
+						btcoexist->btc_write_4byte(
+							btcoexist, 0x948, 0x0);
+				}
+				break;
+			default:
+			case BTC_ANT_PATH_PTA:
+				if (board_info->btdm_ant_pos ==
+				    BTC_ANTENNA_AT_MAIN_PORT)
+					btcoexist->btc_write_4byte(
+						btcoexist, 0x948,
+						0x200);
+				else
+					btcoexist->btc_write_4byte(
+						btcoexist, 0x948, 0x80);
+				break;
+			}
+		}
+	}
+
+	coex_dm->pre_ant_pos_type = coex_dm->cur_ant_pos_type;
+}
+
+void halbtc8723b1ant_ps_tdma_check_for_power_save_state(
+	IN struct btc_coexist *btcoexist, IN boolean new_ps_state)
+{
+	u8	lps_mode = 0x0;
+	u8	h2c_parameter[5] = {0x8, 0, 0, 0, 0};
+
+	btcoexist->btc_get(btcoexist, BTC_GET_U1_LPS_MODE, &lps_mode);
+
+	if (lps_mode) {	/* already under LPS state */
+		if (new_ps_state) {
+			/* keep state under LPS, do nothing. */
+		} else {
+			/* will leave LPS state, turn off psTdma first */
+			/* halbtc8723b1ant_ps_tdma(btcoexist, NORMAL_EXEC, false,
+						8); */
+			btcoexist->btc_fill_h2c(btcoexist, 0x60, 5,
+				h2c_parameter);
+		}
+	} else {					/* NO PS state */
+		if (new_ps_state) {
+			/* will enter LPS state, turn off psTdma first */
+			/* halbtc8723b1ant_ps_tdma(btcoexist, NORMAL_EXEC, false,
+						8); */
+			btcoexist->btc_fill_h2c(btcoexist, 0x60, 5,
+				h2c_parameter);
+		} else {
+			/* keep state under NO PS state, do nothing. */
+		}
+	}
+}
+
+
+void halbtc8723b1ant_power_save_state(IN struct btc_coexist *btcoexist,
+			      IN u8 ps_type, IN u8 lps_val, IN u8 rpwm_val)
+{
+	boolean		low_pwr_disable = false;
+
+	switch (ps_type) {
+	case BTC_PS_WIFI_NATIVE:
+		/* recover to original 32k low power setting */
+		low_pwr_disable = false;
+		btcoexist->btc_set(btcoexist,
+				   BTC_SET_ACT_DISABLE_LOW_POWER,
+				   &low_pwr_disable);
+		btcoexist->btc_set(btcoexist, BTC_SET_ACT_NORMAL_LPS,
+				   NULL);
+		coex_sta->force_lps_on = false;
+		break;
+	case BTC_PS_LPS_ON:
+		halbtc8723b1ant_ps_tdma_check_for_power_save_state(
+			btcoexist, true);
+		halbtc8723b1ant_lps_rpwm(btcoexist, NORMAL_EXEC,
+					 lps_val, rpwm_val);
+		/* when coex force to enter LPS, do not enter 32k low power. */
+		low_pwr_disable = true;
+		btcoexist->btc_set(btcoexist,
+				   BTC_SET_ACT_DISABLE_LOW_POWER,
+				   &low_pwr_disable);
+		/* power save must executed before psTdma.			 */
+		btcoexist->btc_set(btcoexist, BTC_SET_ACT_ENTER_LPS,
+				   NULL);
+		coex_sta->force_lps_on = true;
+		break;
+	case BTC_PS_LPS_OFF:
+		halbtc8723b1ant_ps_tdma_check_for_power_save_state(
+			btcoexist, false);
+		btcoexist->btc_set(btcoexist, BTC_SET_ACT_LEAVE_LPS,
+				   NULL);
+		coex_sta->force_lps_on = false;
+		break;
+	default:
+		break;
+	}
+}
+
+
+void halbtc8723b1ant_set_fw_pstdma(IN struct btc_coexist *btcoexist,
+	   IN u8 byte1, IN u8 byte2, IN u8 byte3, IN u8 byte4, IN u8 byte5)
+{
+	u8			h2c_parameter[5] = {0};
+	u8			real_byte1 = byte1, real_byte5 = byte5;
+	boolean		ap_enable = false;
+
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_AP_MODE_ENABLE,
+			   &ap_enable);
+
+	if (ap_enable) {
+		if (byte1 & BIT(4) && !(byte1 & BIT(5))) {
+			real_byte1 &= ~BIT(4);
+			real_byte1 |= BIT(5);
+
+			real_byte5 |= BIT(5);
+			real_byte5 &= ~BIT(6);
+
+			halbtc8723b1ant_power_save_state(btcoexist,
+				BTC_PS_WIFI_NATIVE, 0x0, 0x0);
+		}
+	} else if (byte1 & BIT(4) && !(byte1 & BIT(5))) {
+			halbtc8723b1ant_power_save_state(btcoexist,
+				BTC_PS_LPS_ON, 0x50, 0x4);
+
+	} else {
+			halbtc8723b1ant_power_save_state(btcoexist,
+				BTC_PS_WIFI_NATIVE, 0x0, 0x0);
+	}
+
+	h2c_parameter[0] = real_byte1;
+	h2c_parameter[1] = byte2;
+	h2c_parameter[2] = byte3;
+	h2c_parameter[3] = byte4;
+	h2c_parameter[4] = real_byte5;
+
+	coex_dm->ps_tdma_para[0] = real_byte1;
+	coex_dm->ps_tdma_para[1] = byte2;
+	coex_dm->ps_tdma_para[2] = byte3;
+	coex_dm->ps_tdma_para[3] = byte4;
+	coex_dm->ps_tdma_para[4] = real_byte5;
+
+	btcoexist->btc_fill_h2c(btcoexist, 0x60, 5, h2c_parameter);
+}
+
+
+void halbtc8723b1ant_ps_tdma(IN struct btc_coexist *btcoexist,
+		     IN boolean force_exec, IN boolean turn_on, IN u8 type)
+{
+	struct  btc_board_info	*board_info = &btcoexist->board_info;
+	struct  btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
+	boolean			wifi_busy = false;
+	u8			rssi_adjust_val = 0;
+	u8			ps_tdma_byte4_val = 0x50, ps_tdma_byte0_val = 0x51,
+				ps_tdma_byte3_val =  0x10;
+	s8			wifi_duration_adjust = 0x0;
+	static boolean	 pre_wifi_busy = false;
+
+	coex_dm->cur_ps_tdma_on = turn_on;
+	coex_dm->cur_ps_tdma = type;
+
+#if BT_8723B_1ANT_ANTDET_ENABLE
+#if BT_8723B_1ANT_ANTDET_COEXMECHANISMSWITCH_ENABLE
+	if (board_info->btdm_ant_num_by_ant_det == 2) {
+		if (turn_on)
+			type = type +
+			       100; /* for WiFi RSSI low or BT RSSI low */
+		else
+			type = 1; /* always translate to TDMA(off,1) for TDMA-off case */
+	}
+
+#endif
+#endif
+
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy);
+
+	if (wifi_busy != pre_wifi_busy) {
+		force_exec = true;
+		pre_wifi_busy = wifi_busy;
+	}
+
+	if (!force_exec) {
+		if ((coex_dm->pre_ps_tdma_on == coex_dm->cur_ps_tdma_on) &&
+		    (coex_dm->pre_ps_tdma == coex_dm->cur_ps_tdma))
+			return;
+	}
+
+	if (coex_sta->scan_ap_num <= 5) {
+		wifi_duration_adjust = 5;
+
+		if (coex_sta->a2dp_bit_pool >= 35)
+			wifi_duration_adjust = -10;
+		else if (coex_sta->a2dp_bit_pool >= 45)
+			wifi_duration_adjust = -15;
+	} else if (coex_sta->scan_ap_num >= 40) {
+		wifi_duration_adjust = -15;
+
+		if (coex_sta->a2dp_bit_pool < 35)
+			wifi_duration_adjust = -5;
+		else if (coex_sta->a2dp_bit_pool < 45)
+			wifi_duration_adjust = -10;
+	} else if (coex_sta->scan_ap_num >= 20) {
+		wifi_duration_adjust = -10;
+
+		if (coex_sta->a2dp_bit_pool >= 45)
+			wifi_duration_adjust = -15;
+	} else {
+		wifi_duration_adjust = 0;
+
+		if (coex_sta->a2dp_bit_pool >= 35)
+			wifi_duration_adjust = -10;
+		else if (coex_sta->a2dp_bit_pool >= 45)
+			wifi_duration_adjust = -15;
+	}
+
+	if ((type == 1) || (type == 2) || (type == 9) || (type == 11) ||
+	    (type == 101)
+	    || (type == 102) || (type == 109) || (type == 101)) {
+		if (!coex_sta->force_lps_on) { /* Native power save TDMA, only for A2DP-only case 1/2/9/11 while wifi noisy threshold > 30 */
+			ps_tdma_byte0_val = 0x61;  /* no null-pkt */
+			ps_tdma_byte3_val = 0x11; /* no tx-pause at BT-slot */
+			ps_tdma_byte4_val =
+				0x10; /* 0x778 = d/1 toggle, no dynamic slot */
+		} else {
+			ps_tdma_byte0_val = 0x51;  /* null-pkt */
+			ps_tdma_byte3_val = 0x10; /* tx-pause at BT-slot */
+			ps_tdma_byte4_val =
+				0x50; /* 0x778 = d/1 toggle, dynamic slot */
+		}
+	} else if ((type == 3) || (type == 13) || (type == 14) ||
+		   (type == 103) || (type == 113) || (type == 114)) {
+		ps_tdma_byte0_val = 0x51;  /* null-pkt */
+		ps_tdma_byte3_val = 0x10; /* tx-pause at BT-slot */
+		ps_tdma_byte4_val =
+			0x10; /* 0x778 = d/1 toggle, no dynamic slot */
+#if 0
+		if (!wifi_busy)
+			ps_tdma_byte4_val = ps_tdma_byte4_val |
+				0x1;  /* 0x778 = 0x1 at wifi slot (no blocking BT Low-Pri pkts) */
+#endif
+	} else { /* native power save case */
+		ps_tdma_byte0_val = 0x61;  /* no null-pkt */
+		ps_tdma_byte3_val = 0x11; /* no tx-pause at BT-slot */
+		ps_tdma_byte4_val =
+			0x11; /* 0x778 = d/1 toggle, no dynamic slot */
+		/* psTdmaByte4Va is not defne for 0x778 = d/1, 1/1 case */
+	}
+
+	/* if (bt_link_info->slave_role == true) */
+	if ((bt_link_info->slave_role == true)	&& (bt_link_info->a2dp_exist))
+		ps_tdma_byte4_val = ps_tdma_byte4_val |
+			0x1;  /* 0x778 = 0x1 at wifi slot (no blocking BT Low-Pri pkts) */
+
+	if (type > 100) {
+		ps_tdma_byte0_val = ps_tdma_byte0_val |
+				    0x82; /* set antenna control by SW	 */
+		ps_tdma_byte3_val = ps_tdma_byte3_val |
+			0x60;  /* set antenna no toggle, control by antenna diversity */
+	}
+
+
+	if (turn_on) {
+		switch (type) {
+		default:
+			halbtc8723b1ant_set_fw_pstdma(btcoexist, 0x51,
+				      0x1a, 0x1a, 0x0, ps_tdma_byte4_val);
+			break;
+		case 1:
+			halbtc8723b1ant_set_fw_pstdma(btcoexist,
+						      ps_tdma_byte0_val, 0x3a +
+					      wifi_duration_adjust, 0x03,
+				      ps_tdma_byte3_val, ps_tdma_byte4_val);
+			break;
+		case 2:
+			halbtc8723b1ant_set_fw_pstdma(btcoexist,
+						      ps_tdma_byte0_val, 0x2d +
+					      wifi_duration_adjust, 0x03,
+				      ps_tdma_byte3_val, ps_tdma_byte4_val);
+			break;
+		case 3:
+			halbtc8723b1ant_set_fw_pstdma(btcoexist,
+					      ps_tdma_byte0_val, 0x30, 0x03,
+				      ps_tdma_byte3_val, ps_tdma_byte4_val);
+			break;
+		case 4:
+			halbtc8723b1ant_set_fw_pstdma(btcoexist, 0x93,
+						      0x15, 0x3, 0x14, 0x0);
+			break;
+		case 5:
+			halbtc8723b1ant_set_fw_pstdma(btcoexist,
+					      ps_tdma_byte0_val, 0x1f, 0x3,
+						      ps_tdma_byte3_val, 0x11);
+			break;
+		case 6:
+			halbtc8723b1ant_set_fw_pstdma(btcoexist,
+					      ps_tdma_byte0_val, 0x20, 0x3,
+						      ps_tdma_byte3_val, 0x11);
+			break;
+		case 7:
+			halbtc8723b1ant_set_fw_pstdma(btcoexist, 0x13,
+						      0xc, 0x5, 0x0, 0x0);
+			break;
+		case 8:
+			halbtc8723b1ant_set_fw_pstdma(btcoexist, 0x93,
+						      0x25, 0x3, 0x10, 0x0);
+			break;
+		case 9:
+			halbtc8723b1ant_set_fw_pstdma(btcoexist,
+					      ps_tdma_byte0_val, 0x21, 0x3,
+				      ps_tdma_byte3_val, ps_tdma_byte4_val);
+			break;
+		case 10:
+			halbtc8723b1ant_set_fw_pstdma(btcoexist, 0x13,
+						      0xa, 0xa, 0x0, 0x40);
+			break;
+		case 11:
+			halbtc8723b1ant_set_fw_pstdma(btcoexist,
+					      ps_tdma_byte0_val, 0x21, 0x03,
+				      ps_tdma_byte3_val, ps_tdma_byte4_val);
+			break;
+		case 12:
+			halbtc8723b1ant_set_fw_pstdma(btcoexist, 0x51,
+						      0x0a, 0x0a, 0x0, 0x50);
+			break;
+		case 13:
+			if (coex_sta->scan_ap_num <= 3)
+				halbtc8723b1ant_set_fw_pstdma(btcoexist,
+					      ps_tdma_byte0_val, 0x40, 0x3,
+							      ps_tdma_byte3_val,
+						      ps_tdma_byte4_val);
+			else
+				halbtc8723b1ant_set_fw_pstdma(btcoexist,
+					      ps_tdma_byte0_val, 0x21, 0x3,
+							      ps_tdma_byte3_val,
+						      ps_tdma_byte4_val);
+			break;
+		case 14:
+			if (coex_sta->scan_ap_num <= 3)
+				halbtc8723b1ant_set_fw_pstdma(btcoexist,
+					      0x51, 0x30, 0x3, 0x10, 0x50);
+			else
+				halbtc8723b1ant_set_fw_pstdma(btcoexist,
+					      ps_tdma_byte0_val, 0x21, 0x3,
+							      ps_tdma_byte3_val,
+						      ps_tdma_byte4_val);
+			break;
+		case 15:
+			halbtc8723b1ant_set_fw_pstdma(btcoexist, 0x13,
+						      0xa, 0x3, 0x8, 0x0);
+			break;
+		case 16:
+			halbtc8723b1ant_set_fw_pstdma(btcoexist, 0x93,
+						      0x15, 0x3, 0x10, 0x0);
+			break;
+		case 18:
+			halbtc8723b1ant_set_fw_pstdma(btcoexist, 0x93,
+						      0x25, 0x3, 0x10, 0x0);
+			break;
+		case 20:
+			halbtc8723b1ant_set_fw_pstdma(btcoexist,
+					      ps_tdma_byte0_val, 0x3f, 0x03,
+						      ps_tdma_byte3_val, 0x10);
+			break;
+		case 21:
+			halbtc8723b1ant_set_fw_pstdma(btcoexist, 0x61,
+						      0x25, 0x03, 0x11, 0x11);
+			break;
+		case 22:
+			halbtc8723b1ant_set_fw_pstdma(btcoexist,
+					      ps_tdma_byte0_val, 0x25, 0x03,
+						      ps_tdma_byte3_val, 0x10);
+			break;
+		case 23:
+			halbtc8723b1ant_set_fw_pstdma(btcoexist, 0xe3,
+						      0x25, 0x3, 0x31, 0x18);
+			break;
+		case 24:
+			halbtc8723b1ant_set_fw_pstdma(btcoexist, 0xe3,
+						      0x15, 0x3, 0x31, 0x18);
+			break;
+		case 25:
+			halbtc8723b1ant_set_fw_pstdma(btcoexist, 0xe3,
+						      0xa, 0x3, 0x31, 0x18);
+			break;
+		case 26:
+			halbtc8723b1ant_set_fw_pstdma(btcoexist, 0xe3,
+						      0xa, 0x3, 0x31, 0x18);
+			break;
+		case 27:
+			halbtc8723b1ant_set_fw_pstdma(btcoexist, 0xe3,
+						      0x25, 0x3, 0x31, 0x98);
+			break;
+		case 28:
+			halbtc8723b1ant_set_fw_pstdma(btcoexist, 0x69,
+						      0x25, 0x3, 0x31, 0x0);
+			break;
+		case 29:
+			halbtc8723b1ant_set_fw_pstdma(btcoexist, 0xab,
+						      0x1a, 0x1a, 0x1, 0x10);
+			break;
+		case 30:
+			halbtc8723b1ant_set_fw_pstdma(btcoexist, 0x51,
+						      0x30, 0x3, 0x10, 0x10);
+			break;
+		case 31:
+			halbtc8723b1ant_set_fw_pstdma(btcoexist, 0xd3,
+						      0x1a, 0x1a, 0, 0x58);
+			break;
+		case 32:
+			halbtc8723b1ant_set_fw_pstdma(btcoexist,
+					      ps_tdma_byte0_val, 0x35, 0x3,
+				      ps_tdma_byte3_val, ps_tdma_byte4_val);
+			break;
+		case 33:
+			halbtc8723b1ant_set_fw_pstdma(btcoexist,
+					      ps_tdma_byte0_val, 0x35, 0x3,
+						      ps_tdma_byte3_val, 0x10);
+			break;
+		case 34:
+			halbtc8723b1ant_set_fw_pstdma(btcoexist, 0x53,
+						      0x1a, 0x1a, 0x0, 0x10);
+			break;
+		case 35:
+			halbtc8723b1ant_set_fw_pstdma(btcoexist, 0x63,
+						      0x1a, 0x1a, 0x0, 0x10);
+			break;
+		case 36:
+			halbtc8723b1ant_set_fw_pstdma(btcoexist, 0xd3,
+						      0x12, 0x3, 0x14, 0x50);
+			break;
+		case 40: /* SoftAP only with no sta associated,BT disable ,TDMA mode for power saving */
+			/* here softap mode screen off will cost 70-80mA for phone */
+			halbtc8723b1ant_set_fw_pstdma(btcoexist, 0x23,
+						      0x18, 0x00, 0x10, 0x24);
+			break;
+
+		/* for 1-Ant translate to 2-Ant	 */
+		case 101:
+			halbtc8723b1ant_set_fw_pstdma(btcoexist,
+						      ps_tdma_byte0_val, 0x3a +
+					      wifi_duration_adjust, 0x03,
+				      ps_tdma_byte3_val, ps_tdma_byte4_val);
+			break;
+		case 102:
+			halbtc8723b1ant_set_fw_pstdma(btcoexist,
+						      ps_tdma_byte0_val, 0x2d +
+					      wifi_duration_adjust, 0x03,
+				      ps_tdma_byte3_val, ps_tdma_byte4_val);
+			break;
+		case 103:
+			/* halbtc8723b1ant_set_fw_pstdma(btcoexist, 0x51, 0x1d, 0x1d, 0x0, ps_tdma_byte4_val); */
+			halbtc8723b1ant_set_fw_pstdma(btcoexist,
+					      ps_tdma_byte0_val, 0x3a, 0x03,
+				      ps_tdma_byte3_val, ps_tdma_byte4_val);
+			break;
+		case 105:
+			halbtc8723b1ant_set_fw_pstdma(btcoexist,
+					      ps_tdma_byte0_val, 0x15, 0x3,
+						      ps_tdma_byte3_val, 0x11);
+			break;
+		case 106:
+			halbtc8723b1ant_set_fw_pstdma(btcoexist,
+					      ps_tdma_byte0_val, 0x20, 0x3,
+						      ps_tdma_byte3_val, 0x11);
+			break;
+		case 109:
+			halbtc8723b1ant_set_fw_pstdma(btcoexist,
+					      ps_tdma_byte0_val, 0x21, 0x3,
+				      ps_tdma_byte3_val, ps_tdma_byte4_val);
+			break;
+		case 111:
+			halbtc8723b1ant_set_fw_pstdma(btcoexist,
+					      ps_tdma_byte0_val, 0x21, 0x03,
+				      ps_tdma_byte3_val, ps_tdma_byte4_val);
+			break;
+		case 113:
+			/* halbtc8723b1ant_set_fw_pstdma(btcoexist, 0x51, 0x12, 0x12, 0x0, ps_tdma_byte4_val); */
+			halbtc8723b1ant_set_fw_pstdma(btcoexist,
+					      ps_tdma_byte0_val, 0x21, 0x3,
+				      ps_tdma_byte3_val, ps_tdma_byte4_val);
+			break;
+		case 114:
+			halbtc8723b1ant_set_fw_pstdma(btcoexist,
+					      ps_tdma_byte0_val, 0x21, 0x3,
+				      ps_tdma_byte3_val, ps_tdma_byte4_val);
+			break;
+		case 120:
+			halbtc8723b1ant_set_fw_pstdma(btcoexist,
+					      ps_tdma_byte0_val, 0x3f, 0x03,
+						      ps_tdma_byte3_val, 0x10);
+			break;
+		case 122:
+			halbtc8723b1ant_set_fw_pstdma(btcoexist,
+					      ps_tdma_byte0_val, 0x25, 0x03,
+						      ps_tdma_byte3_val, 0x10);
+			break;
+		case 132:
+			halbtc8723b1ant_set_fw_pstdma(btcoexist,
+					      ps_tdma_byte0_val, 0x25, 0x03,
+				      ps_tdma_byte3_val, ps_tdma_byte4_val);
+			break;
+		case 133:
+			halbtc8723b1ant_set_fw_pstdma(btcoexist,
+					      ps_tdma_byte0_val, 0x25, 0x03,
+						      ps_tdma_byte3_val, 0x11);
+			break;
+
+		}
+	} else {
+
+		/* disable PS tdma */
+		switch (type) {
+		case 8: /* PTA Control */
+			halbtc8723b1ant_set_fw_pstdma(btcoexist, 0x8,
+						      0x0, 0x0, 0x0, 0x0);
+			break;
+		case 0:
+		default:  /* Software control, Antenna at BT side */
+			halbtc8723b1ant_set_fw_pstdma(btcoexist, 0x0,
+						      0x0, 0x0, 0x0, 0x0);
+			break;
+		case 1: /* 2-Ant, 0x778=3, antenna control by antenna diversity */
+			halbtc8723b1ant_set_fw_pstdma(btcoexist, 0x0,
+						      0x0, 0x0, 0x48, 0x0);
+			break;
+		}
+	}
+	rssi_adjust_val = 0;
+	btcoexist->btc_set(btcoexist,
+		BTC_SET_U1_RSSI_ADJ_VAL_FOR_1ANT_COEX_TYPE, &rssi_adjust_val);
+
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+		"############# [BTCoex], 0x948=0x%x, 0x765=0x%x, 0x67=0x%x\n",
+		    btcoexist->btc_read_4byte(btcoexist, 0x948),
+		    btcoexist->btc_read_1byte(btcoexist, 0x765),
+		    btcoexist->btc_read_1byte(btcoexist, 0x67));
+	BTC_TRACE(trace_buf);
+
+	/* update pre state */
+	coex_dm->pre_ps_tdma_on = coex_dm->cur_ps_tdma_on;
+	coex_dm->pre_ps_tdma = coex_dm->cur_ps_tdma;
+}
+
+void halbtc8723b1ant_tdma_duration_adjust_for_acl(IN struct btc_coexist
+		*btcoexist, IN u8 wifi_status)
+{
+	static s32		up, dn, m, n, wait_count;
+	s32			result;   /* 0: no change, +1: increase WiFi duration, -1: decrease WiFi duration */
+	u8			retry_count = 0, bt_info_ext;
+	boolean			wifi_busy = false;
+
+	if (BT_8723B_1ANT_WIFI_STATUS_CONNECTED_BUSY == wifi_status)
+		wifi_busy = true;
+	else
+		wifi_busy = false;
+
+	if ((BT_8723B_1ANT_WIFI_STATUS_NON_CONNECTED_ASSO_AUTH_SCAN ==
+	     wifi_status) ||
+	    (BT_8723B_1ANT_WIFI_STATUS_CONNECTED_SCAN == wifi_status) ||
+	    (BT_8723B_1ANT_WIFI_STATUS_CONNECTED_SPECIFIC_PKT ==
+	     wifi_status)) {
+		if (coex_dm->cur_ps_tdma != 1 &&
+		    coex_dm->cur_ps_tdma != 2 &&
+		    coex_dm->cur_ps_tdma != 3 &&
+		    coex_dm->cur_ps_tdma != 9) {
+			halbtc8723b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true,
+						9);
+			coex_dm->ps_tdma_du_adj_type = 9;
+
+			up = 0;
+			dn = 0;
+			m = 1;
+			n = 3;
+			result = 0;
+			wait_count = 0;
+		}
+		return;
+	}
+
+	if (!coex_dm->auto_tdma_adjust) {
+		coex_dm->auto_tdma_adjust = true;
+
+		halbtc8723b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 2);
+		coex_dm->ps_tdma_du_adj_type = 2;
+		/* ============ */
+		up = 0;
+		dn = 0;
+		m = 1;
+		n = 3;
+		result = 0;
+		wait_count = 0;
+	} else {
+		/* acquire the BT TRx retry count from BT_Info byte2 */
+		retry_count = coex_sta->bt_retry_cnt;
+		bt_info_ext = coex_sta->bt_info_ext;
+
+		if ((coex_sta->low_priority_tx) > 1050 ||
+		    (coex_sta->low_priority_rx) > 1250)
+			retry_count++;
+
+		result = 0;
+		wait_count++;
+
+		if (retry_count ==
+		    0) { /* no retry in the last 2-second duration */
+			up++;
+			dn--;
+
+			if (dn <= 0)
+				dn = 0;
+
+			if (up >= n) {	/* if retry count during continuous n*2 seconds is 0, enlarge WiFi duration */
+				wait_count = 0;
+				n = 3;
+				up = 0;
+				dn = 0;
+				result = 1;
+			}
+		} else if (retry_count <=
+			   3) {	/* <=3 retry in the last 2-second duration */
+			up--;
+			dn++;
+
+			if (up <= 0)
+				up = 0;
+
+			if (dn == 2) {	/* if continuous 2 retry count(every 2 seconds) >0 and < 3, reduce WiFi duration */
+				if (wait_count <= 2)
+					m++; /* to avoid loop between the two levels */
+				else
+					m = 1;
+
+				if (m >= 20)  /* maximum of m = 20 ' will recheck if need to adjust wifi duration in maximum time interval 120 seconds */
+					m = 20;
+
+				n = 3 * m;
+				up = 0;
+				dn = 0;
+				wait_count = 0;
+				result = -1;
+			}
+		} else { /* retry count > 3, once retry count > 3, to reduce WiFi duration */
+			if (wait_count == 1)
+				m++; /* to avoid loop between the two levels */
+			else
+				m = 1;
+
+			if (m >= 20)  /* maximum of m = 20 ' will recheck if need to adjust wifi duration in maximum time interval 120 seconds */
+				m = 20;
+
+			n = 3 * m;
+			up = 0;
+			dn = 0;
+			wait_count = 0;
+			result = -1;
+		}
+
+		if (result == -1) {
+			/*		if( (BT_INFO_8723B_1ANT_A2DP_BASIC_RATE(bt_info_ext)) &&
+						((coex_dm->cur_ps_tdma == 1) ||(coex_dm->cur_ps_tdma == 2)) )
+					{
+						halbtc8723b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 9);
+						coex_dm->ps_tdma_du_adj_type = 9;
+					}
+					else */ if (coex_dm->cur_ps_tdma == 1) {
+							halbtc8723b1ant_ps_tdma(btcoexist, NORMAL_EXEC,
+							true, 2);
+				coex_dm->ps_tdma_du_adj_type = 2;
+			} else if (coex_dm->cur_ps_tdma == 2) {
+				halbtc8723b1ant_ps_tdma(btcoexist, NORMAL_EXEC,
+							true, 9);
+				coex_dm->ps_tdma_du_adj_type = 9;
+			} else if (coex_dm->cur_ps_tdma == 9) {
+				halbtc8723b1ant_ps_tdma(btcoexist, NORMAL_EXEC,
+							true, 11);
+				coex_dm->ps_tdma_du_adj_type = 11;
+			}
+		} else if (result == 1) {
+			/*			if( (BT_INFO_8723B_1ANT_A2DP_BASIC_RATE(bt_info_ext)) &&
+							((coex_dm->cur_ps_tdma == 1) ||(coex_dm->cur_ps_tdma == 2)) )
+						{
+							halbtc8723b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 9);
+							coex_dm->ps_tdma_du_adj_type = 9;
+						}
+						else */ if (coex_dm->cur_ps_tdma == 11) {
+								halbtc8723b1ant_ps_tdma(btcoexist, NORMAL_EXEC,
+								true, 9);
+				coex_dm->ps_tdma_du_adj_type = 9;
+			} else if (coex_dm->cur_ps_tdma == 9) {
+				halbtc8723b1ant_ps_tdma(btcoexist, NORMAL_EXEC,
+							true, 2);
+				coex_dm->ps_tdma_du_adj_type = 2;
+			} else if (coex_dm->cur_ps_tdma == 2) {
+				halbtc8723b1ant_ps_tdma(btcoexist, NORMAL_EXEC,
+							true, 1);
+				coex_dm->ps_tdma_du_adj_type = 1;
+			}
+		} else { /* no change */
+			/* Bryant Modify
+			if(wifi_busy != pre_wifi_busy)
+			{
+				pre_wifi_busy = wifi_busy;
+				halbtc8723b1ant_ps_tdma(btcoexist, FORCE_EXEC, true, coex_dm->cur_ps_tdma);
+			}
+			*/
+
+		}
+
+		if (coex_dm->cur_ps_tdma != 1 &&
+		    coex_dm->cur_ps_tdma != 2 &&
+		    coex_dm->cur_ps_tdma != 9 &&
+		    coex_dm->cur_ps_tdma != 11) {
+			/* recover to previous adjust type */
+			halbtc8723b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true,
+						coex_dm->ps_tdma_du_adj_type);
+		}
+	}
+}
+
+
+/* *********************************************
+ *
+ *	Non-Software Coex Mechanism start
+ *
+ * ********************************************* */
+void halbtc8723b1ant_action_bt_whck_test(IN struct btc_coexist *btcoexist)
+{
+	halbtc8723b1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 8);
+	halbtc8723b1ant_set_ant_path(btcoexist, BTC_ANT_PATH_PTA, NORMAL_EXEC,
+				     false, false);
+	halbtc8723b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0);
+}
+
+
+void halbtc8723b1ant_action_hs(IN struct btc_coexist *btcoexist)
+{
+	halbtc8723b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 5);
+	halbtc8723b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 2);
+}
+
+void halbtc8723b1ant_action_bt_inquiry(IN struct btc_coexist *btcoexist)
+{
+	struct  btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
+	boolean			wifi_connected = false, ap_enable = false, wifi_busy = false,
+				bt_busy = false;
+
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_AP_MODE_ENABLE,
+			   &ap_enable);
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED,
+			   &wifi_connected);
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy);
+	btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_TRAFFIC_BUSY, &bt_busy);
+
+	if (coex_sta->bt_abnormal_scan) {
+		halbtc8723b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true,
+					33);
+		halbtc8723b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 7);
+	} else if ((!wifi_connected) && (!coex_sta->wifi_is_high_pri_task)) {
+		halbtc8723b1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 8);
+		halbtc8723b1ant_set_ant_path(btcoexist, BTC_ANT_PATH_PTA,
+					     NORMAL_EXEC, false, false);
+		halbtc8723b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0);
+	} else if ((bt_link_info->sco_exist) || (bt_link_info->hid_exist) ||
+		   (bt_link_info->a2dp_exist)) {
+		/* SCO/HID/A2DP  busy */
+
+		if (coex_sta->c2h_bt_remote_name_req)
+			halbtc8723b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true,
+						33);
+		else
+			halbtc8723b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true,
+						32);
+
+		halbtc8723b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4);
+	} else if ((bt_link_info->pan_exist) || (wifi_busy)) {
+
+		if (coex_sta->c2h_bt_remote_name_req)
+			halbtc8723b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true,
+						33);
+		else
+			halbtc8723b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true,
+						32);
+
+		halbtc8723b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4);
+	} else {
+
+		halbtc8723b1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 8);
+		halbtc8723b1ant_set_ant_path(btcoexist, BTC_ANT_PATH_PTA,
+					     NORMAL_EXEC, false, false);
+		halbtc8723b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 7);
+
+	}
+}
+
+void halbtc8723b1ant_action_bt_sco_hid_only_busy(IN struct btc_coexist
+		*btcoexist, IN u8 wifi_status)
+{
+	struct  btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
+	boolean	wifi_connected = false;
+
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED,
+			   &wifi_connected);
+
+	/* tdma and coex table */
+
+	if (bt_link_info->sco_exist) {
+		halbtc8723b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 5);
+		halbtc8723b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 5);
+	} else { /* HID */
+		halbtc8723b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 6);
+		halbtc8723b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 5);
+	}
+}
+
+void halbtc8723b1ant_action_wifi_only(IN struct btc_coexist *btcoexist)
+{
+	halbtc8723b1ant_coex_table_with_type(btcoexist, FORCE_EXEC, 0);
+	halbtc8723b1ant_ps_tdma(btcoexist, FORCE_EXEC, false, 8);
+	halbtc8723b1ant_set_ant_path(btcoexist, BTC_ANT_PATH_PTA, FORCE_EXEC,
+				     false, false);
+}
+
+void halbtc8723b1ant_action_wifi_multi_port(IN struct btc_coexist *btcoexist)
+{
+	halbtc8723b1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 8);
+	halbtc8723b1ant_set_ant_path(btcoexist, BTC_ANT_PATH_PTA, NORMAL_EXEC,
+				     false, false);
+	halbtc8723b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 2);
+}
+
+void halbtc8723b1ant_action_wifi_connected_bt_acl_busy(IN struct btc_coexist
+		*btcoexist, IN u8 wifi_status)
+{
+	struct  btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
+
+	if ((coex_sta->low_priority_rx >= 950)  && (!coex_sta->under_ips))
+		bt_link_info->slave_role = true;
+	else
+		bt_link_info->slave_role = false;
+
+	if (bt_link_info->hid_only) { /* HID */
+		halbtc8723b1ant_action_bt_sco_hid_only_busy(btcoexist,
+				wifi_status);
+		coex_dm->auto_tdma_adjust = false;
+		return;
+	} else if (bt_link_info->a2dp_only) { /* A2DP		 */
+		if (BT_8723B_1ANT_WIFI_STATUS_CONNECTED_IDLE == wifi_status) {
+			halbtc8723b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true,
+						32);
+			halbtc8723b1ant_coex_table_with_type(btcoexist,
+							     NORMAL_EXEC, 4);
+			coex_dm->auto_tdma_adjust = false;
+		} else {
+			halbtc8723b1ant_tdma_duration_adjust_for_acl(btcoexist,
+					wifi_status);
+			halbtc8723b1ant_coex_table_with_type(btcoexist,
+							     NORMAL_EXEC, 4);
+			coex_dm->auto_tdma_adjust = true;
+		}
+	} else if (((bt_link_info->a2dp_exist) && (bt_link_info->pan_exist)) ||
+		   (bt_link_info->hid_exist && bt_link_info->a2dp_exist &&
+		bt_link_info->pan_exist)) { /* A2DP+PAN(OPP,FTP), HID+A2DP+PAN(OPP,FTP) */
+		halbtc8723b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 13);
+		halbtc8723b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4);
+		coex_dm->auto_tdma_adjust = false;
+	} else if (bt_link_info->hid_exist &&
+		   bt_link_info->a2dp_exist) { /* HID+A2DP */
+		halbtc8723b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 14);
+		coex_dm->auto_tdma_adjust = false;
+
+		halbtc8723b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4);
+	} else if ((bt_link_info->pan_only) || (bt_link_info->hid_exist &&
+		bt_link_info->pan_exist)) { /* PAN(OPP,FTP), HID+PAN(OPP,FTP)			 */
+
+		if (BT_8723B_1ANT_WIFI_STATUS_CONNECTED_IDLE == wifi_status)
+			halbtc8723b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true,
+						9);
+		else
+			halbtc8723b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true,
+						3);
+
+		halbtc8723b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4);
+		coex_dm->auto_tdma_adjust = false;
+	} else {
+		/* BT no-profile busy (0x9) */
+		halbtc8723b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 33);
+		halbtc8723b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4);
+		coex_dm->auto_tdma_adjust = false;
+	}
+}
+
+void halbtc8723b1ant_action_wifi_not_connected(IN struct btc_coexist *btcoexist)
+{
+
+	/* tdma and coex table */
+	halbtc8723b1ant_ps_tdma(btcoexist, FORCE_EXEC, false, 8);
+	halbtc8723b1ant_set_ant_path(btcoexist, BTC_ANT_PATH_PTA, NORMAL_EXEC,
+				     false, false);
+	halbtc8723b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0);
+}
+
+void halbtc8723b1ant_action_wifi_not_connected_scan(IN struct btc_coexist
+		*btcoexist)
+{
+	struct  btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
+
+	/* tdma and coex table */
+	if (BT_8723B_1ANT_BT_STATUS_ACL_BUSY == coex_dm->bt_status) {
+		if (bt_link_info->a2dp_exist) {
+			halbtc8723b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true,
+						32);
+			halbtc8723b1ant_coex_table_with_type(btcoexist,
+							     NORMAL_EXEC, 4);
+		} else if (bt_link_info->a2dp_exist &&
+			   bt_link_info->pan_exist) {
+			halbtc8723b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true,
+						22);
+			halbtc8723b1ant_coex_table_with_type(btcoexist,
+							     NORMAL_EXEC, 4);
+		} else {
+			halbtc8723b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true,
+						20);
+			halbtc8723b1ant_coex_table_with_type(btcoexist,
+							     NORMAL_EXEC, 4);
+		}
+	} else if ((BT_8723B_1ANT_BT_STATUS_SCO_BUSY == coex_dm->bt_status) ||
+		   (BT_8723B_1ANT_BT_STATUS_ACL_SCO_BUSY ==
+		    coex_dm->bt_status)) {
+		halbtc8723b1ant_action_bt_sco_hid_only_busy(btcoexist,
+				BT_8723B_1ANT_WIFI_STATUS_CONNECTED_SCAN);
+	} else {
+		/* Bryant Add */
+		halbtc8723b1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 8);
+		halbtc8723b1ant_set_ant_path(btcoexist, BTC_ANT_PATH_PTA,
+					     NORMAL_EXEC, false, false);
+		halbtc8723b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 2);
+	}
+}
+
+void halbtc8723b1ant_action_wifi_not_connected_asso_auth(
+	IN struct btc_coexist *btcoexist)
+{
+	struct  btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
+
+	/* tdma and coex table */
+	if ((bt_link_info->sco_exist)  || (bt_link_info->hid_exist) ||
+	    (bt_link_info->a2dp_exist)) {
+		halbtc8723b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 32);
+		halbtc8723b1ant_coex_table_with_type(btcoexist, FORCE_EXEC, 4);
+	} else if (bt_link_info->pan_exist) {
+		halbtc8723b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 20);
+		halbtc8723b1ant_coex_table_with_type(btcoexist, FORCE_EXEC, 4);
+	} else {
+		halbtc8723b1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 8);
+		halbtc8723b1ant_set_ant_path(btcoexist, BTC_ANT_PATH_PTA,
+					     NORMAL_EXEC, false, false);
+		halbtc8723b1ant_coex_table_with_type(btcoexist, FORCE_EXEC, 2);
+	}
+}
+
+void halbtc8723b1ant_action_wifi_connected_scan(IN struct btc_coexist
+		*btcoexist)
+{
+	struct  btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
+
+	/* tdma and coex table */
+	if (BT_8723B_1ANT_BT_STATUS_ACL_BUSY == coex_dm->bt_status) {
+		if (bt_link_info->a2dp_exist) {
+			halbtc8723b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true,
+						32);
+			halbtc8723b1ant_coex_table_with_type(btcoexist,
+							     NORMAL_EXEC, 4);
+		} else if (bt_link_info->a2dp_exist &&
+			   bt_link_info->pan_exist) {
+			halbtc8723b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true,
+						22);
+			halbtc8723b1ant_coex_table_with_type(btcoexist,
+							     NORMAL_EXEC, 4);
+		} else {
+			halbtc8723b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true,
+						20);
+			halbtc8723b1ant_coex_table_with_type(btcoexist,
+							     NORMAL_EXEC, 4);
+		}
+	} else if ((BT_8723B_1ANT_BT_STATUS_SCO_BUSY == coex_dm->bt_status) ||
+		   (BT_8723B_1ANT_BT_STATUS_ACL_SCO_BUSY ==
+		    coex_dm->bt_status)) {
+		halbtc8723b1ant_action_bt_sco_hid_only_busy(btcoexist,
+				BT_8723B_1ANT_WIFI_STATUS_CONNECTED_SCAN);
+	} else {
+		/* Bryant Add */
+		halbtc8723b1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 8);
+		halbtc8723b1ant_set_ant_path(btcoexist, BTC_ANT_PATH_PTA,
+					     NORMAL_EXEC, false, false);
+		halbtc8723b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 2);
+	}
+}
+
+void halbtc8723b1ant_action_wifi_connected_specific_packet(
+	IN struct btc_coexist *btcoexist)
+{
+	struct  btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
+	boolean wifi_busy = false;
+
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy);
+
+	/* no specific packet process for both WiFi and BT very busy */
+	if ((wifi_busy) && ((bt_link_info->pan_exist) ||
+			    (coex_sta->num_of_profile >= 2)))
+		return;
+
+	/* tdma and coex table */
+	if ((bt_link_info->sco_exist) || (bt_link_info->hid_exist)) {
+		halbtc8723b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 32);
+		halbtc8723b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 5);
+	} else if (bt_link_info->a2dp_exist) {
+		halbtc8723b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 32);
+		halbtc8723b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4);
+	} else if (bt_link_info->pan_exist) {
+		halbtc8723b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 20);
+		halbtc8723b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4);
+	} else {
+		halbtc8723b1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 8);
+		halbtc8723b1ant_set_ant_path(btcoexist, BTC_ANT_PATH_PTA,
+					     NORMAL_EXEC, false, false);
+		halbtc8723b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 2);
+	}
+}
+
+void halbtc8723b1ant_action_wifi_connected(IN struct btc_coexist *btcoexist)
+{
+	boolean	wifi_busy = false;
+	boolean		scan = false, link = false, roam = false;
+	boolean		under_4way = false, ap_enable = false;
+
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+		    "[BTCoex], CoexForWifiConnect()===>\n");
+	BTC_TRACE(trace_buf);
+
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_4_WAY_PROGRESS,
+			   &under_4way);
+	if (under_4way) {
+		halbtc8723b1ant_action_wifi_connected_specific_packet(
+			btcoexist);
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			"[BTCoex], CoexForWifiConnect(), return for wifi is under 4way<===\n");
+		BTC_TRACE(trace_buf);
+		return;
+	}
+
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_SCAN, &scan);
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_LINK, &link);
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_ROAM, &roam);
+	if (scan || link || roam) {
+		if (scan)
+			halbtc8723b1ant_action_wifi_connected_scan(btcoexist);
+		else
+			halbtc8723b1ant_action_wifi_connected_specific_packet(
+				btcoexist);
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			"[BTCoex], CoexForWifiConnect(), return for wifi is under scan<===\n");
+		BTC_TRACE(trace_buf);
+		return;
+	}
+
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_AP_MODE_ENABLE,
+			   &ap_enable);
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy);
+
+
+	/* tdma and coex table */
+	if (!wifi_busy) {
+		if (BT_8723B_1ANT_BT_STATUS_ACL_BUSY == coex_dm->bt_status) {
+			halbtc8723b1ant_action_wifi_connected_bt_acl_busy(
+				btcoexist,
+				BT_8723B_1ANT_WIFI_STATUS_CONNECTED_IDLE);
+		} else if ((BT_8723B_1ANT_BT_STATUS_SCO_BUSY ==
+			    coex_dm->bt_status) ||
+			   (BT_8723B_1ANT_BT_STATUS_ACL_SCO_BUSY ==
+			    coex_dm->bt_status)) {
+			halbtc8723b1ant_action_bt_sco_hid_only_busy(btcoexist,
+				BT_8723B_1ANT_WIFI_STATUS_CONNECTED_IDLE);
+		} else {
+			halbtc8723b1ant_ps_tdma(btcoexist, NORMAL_EXEC, false,
+						8);
+			halbtc8723b1ant_set_ant_path(btcoexist,
+				BTC_ANT_PATH_PTA, NORMAL_EXEC, false, false);
+			/* if ((coex_sta->high_priority_tx) +
+			    (coex_sta->high_priority_rx) <= 60) */
+			halbtc8723b1ant_coex_table_with_type(btcoexist,
+							     NORMAL_EXEC, 2);
+			/* else
+				halbtc8723b1ant_coex_table_with_type(btcoexist,
+							     NORMAL_EXEC, 7); */
+		}
+	} else {
+		if (BT_8723B_1ANT_BT_STATUS_ACL_BUSY == coex_dm->bt_status) {
+			halbtc8723b1ant_action_wifi_connected_bt_acl_busy(
+				btcoexist,
+				BT_8723B_1ANT_WIFI_STATUS_CONNECTED_BUSY);
+		} else if ((BT_8723B_1ANT_BT_STATUS_SCO_BUSY ==
+			    coex_dm->bt_status) ||
+			   (BT_8723B_1ANT_BT_STATUS_ACL_SCO_BUSY ==
+			    coex_dm->bt_status)) {
+			halbtc8723b1ant_action_bt_sco_hid_only_busy(btcoexist,
+				BT_8723B_1ANT_WIFI_STATUS_CONNECTED_BUSY);
+		} else {
+			/* halbtc8723b1ant_ps_tdma(btcoexist, NORMAL_EXEC, false,
+						8);
+			halbtc8723b1ant_set_ant_path(btcoexist,
+				BTC_ANT_PATH_PTA, NORMAL_EXEC, false, false);
+			if ((coex_sta->high_priority_tx) +
+			    (coex_sta->high_priority_rx) <= 60)
+				halbtc8723b1ant_coex_table_with_type(btcoexist,
+							     NORMAL_EXEC, 2);
+			else
+				halbtc8723b1ant_coex_table_with_type(btcoexist,
+							     NORMAL_EXEC, 7); */
+			halbtc8723b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true,
+						32);
+			halbtc8723b1ant_set_ant_path(btcoexist,
+				BTC_ANT_PATH_PTA, NORMAL_EXEC, false, false);
+			halbtc8723b1ant_coex_table_with_type(btcoexist,
+							     NORMAL_EXEC, 4);
+
+		}
+	}
+}
+
+void halbtc8723b1ant_run_coexist_mechanism(IN struct btc_coexist *btcoexist)
+{
+	struct  btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
+	boolean	wifi_connected = false, bt_hs_on = false, wifi_busy = false;
+	boolean	increase_scan_dev_num = false;
+	boolean	bt_ctrl_agg_buf_size = false;
+	boolean	miracast_plus_bt = false;
+	u8	agg_buf_size = 5;
+	u32	wifi_link_status = 0;
+	u32	num_of_wifi_link = 0, wifi_bw;
+	u8	iot_peer = BTC_IOT_PEER_UNKNOWN;
+
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+		    "[BTCoex], RunCoexistMechanism()===>\n");
+	BTC_TRACE(trace_buf);
+
+	if (btcoexist->manual_control) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			"[BTCoex], RunCoexistMechanism(), return for Manual CTRL <===\n");
+		BTC_TRACE(trace_buf);
+		return;
+	}
+
+	if (btcoexist->stop_coex_dm) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			"[BTCoex], RunCoexistMechanism(), return for Stop Coex DM <===\n");
+		BTC_TRACE(trace_buf);
+		return;
+	}
+
+	if (coex_sta->under_ips) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], wifi is under IPS !!!\n");
+		BTC_TRACE(trace_buf);
+		return;
+	}
+
+	if (coex_sta->bt_whck_test) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], BT is under WHCK TEST!!!\n");
+		BTC_TRACE(trace_buf);
+		halbtc8723b1ant_action_bt_whck_test(btcoexist);
+		return;
+	}
+
+	if ((BT_8723B_1ANT_BT_STATUS_ACL_BUSY == coex_dm->bt_status) ||
+	    (BT_8723B_1ANT_BT_STATUS_SCO_BUSY == coex_dm->bt_status) ||
+	    (BT_8723B_1ANT_BT_STATUS_ACL_SCO_BUSY == coex_dm->bt_status))
+		increase_scan_dev_num = true;
+
+	btcoexist->btc_set(btcoexist, BTC_SET_BL_INC_SCAN_DEV_NUM,
+			   &increase_scan_dev_num);
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED,
+			   &wifi_connected);
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy);
+
+	btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_LINK_STATUS,
+			   &wifi_link_status);
+	num_of_wifi_link = wifi_link_status >> 16;
+
+	if ((num_of_wifi_link >= 2) ||
+	    (wifi_link_status & WIFI_P2P_GO_CONNECTED)) {
+		if (bt_link_info->bt_link_exist) {
+			halbtc8723b1ant_limited_tx(btcoexist, NORMAL_EXEC, 1, 1,
+						   0, 1);
+			miracast_plus_bt = true;
+		} else {
+			halbtc8723b1ant_limited_tx(btcoexist, NORMAL_EXEC, 0, 0,
+						   0, 0);
+			miracast_plus_bt = false;
+		}
+		btcoexist->btc_set(btcoexist, BTC_SET_BL_MIRACAST_PLUS_BT,
+				   &miracast_plus_bt);
+		halbtc8723b1ant_limited_rx(btcoexist, NORMAL_EXEC, false,
+					   bt_ctrl_agg_buf_size, agg_buf_size);
+
+		if (((bt_link_info->a2dp_exist) || (wifi_busy)) &&
+		    (coex_sta->c2h_bt_inquiry_page))
+			halbtc8723b1ant_action_bt_inquiry(btcoexist);
+		else
+			halbtc8723b1ant_action_wifi_multi_port(btcoexist);
+
+		return;
+	}
+
+	miracast_plus_bt = false;
+	btcoexist->btc_set(btcoexist, BTC_SET_BL_MIRACAST_PLUS_BT,
+			   &miracast_plus_bt);
+
+	btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw);
+
+	if ((bt_link_info->bt_link_exist) && (wifi_connected)) {
+		halbtc8723b1ant_limited_tx(btcoexist, NORMAL_EXEC, 1, 1, 0, 1);
+
+		btcoexist->btc_get(btcoexist, BTC_GET_U1_IOT_PEER, &iot_peer);
+
+		/* if(BTC_IOT_PEER_CISCO != iot_peer)		 */
+		if ((BTC_IOT_PEER_CISCO != iot_peer) &&
+		    (BTC_IOT_PEER_BROADCOM != iot_peer)) {
+			if (bt_link_info->sco_exist) /* if (bt_link_info->bt_hi_pri_link_exist) */
+				/* halbtc8723b1ant_limited_rx(btcoexist, NORMAL_EXEC, true, false, 0x5);				 */
+				halbtc8723b1ant_limited_rx(btcoexist,
+					   NORMAL_EXEC, true, false, 0x5);
+			else
+				halbtc8723b1ant_limited_rx(btcoexist,
+					   NORMAL_EXEC, false, false, 0x5);
+			/* halbtc8723b1ant_limited_rx(btcoexist, NORMAL_EXEC, false, true, 0x8);		 */
+		} else {
+			if (bt_link_info->sco_exist)
+				halbtc8723b1ant_limited_rx(btcoexist,
+					   NORMAL_EXEC, true, false, 0x5);
+			else if (bt_link_info->hid_exist)
+				halbtc8723b1ant_limited_rx(btcoexist,
+					   NORMAL_EXEC, false, true, 0x3);
+			else {
+				if (BTC_WIFI_BW_HT40 == wifi_bw)
+					halbtc8723b1ant_limited_rx(btcoexist,
+						NORMAL_EXEC, false, true, 0x10);
+				else
+					halbtc8723b1ant_limited_rx(btcoexist,
+						NORMAL_EXEC, false, true, 0x8);
+			}
+		}
+
+		halbtc8723b1ant_sw_mechanism(btcoexist, true);
+
+		/* low pelnaty ra in pcr ra */
+		btcoexist->btc_phydm_modify_RA_PCR_threshold(btcoexist, 0, 35);
+
+	} else {
+		halbtc8723b1ant_limited_tx(btcoexist, NORMAL_EXEC, 0, 0, 0, 0);
+
+		halbtc8723b1ant_limited_rx(btcoexist, NORMAL_EXEC, false, false,
+					   0x5);
+
+		halbtc8723b1ant_sw_mechanism(btcoexist, false);
+	}
+
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on);
+	if (coex_sta->c2h_bt_inquiry_page) {
+		halbtc8723b1ant_action_bt_inquiry(btcoexist);
+		return;
+	} else if (bt_hs_on) {
+		halbtc8723b1ant_action_hs(btcoexist);
+		return;
+	}
+
+
+	if (!wifi_connected) {
+		boolean	scan = false, link = false, roam = false;
+
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], wifi is non connected-idle !!!\n");
+		BTC_TRACE(trace_buf);
+
+		btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_SCAN, &scan);
+		btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_LINK, &link);
+		btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_ROAM, &roam);
+
+		if (scan || link || roam) {
+			if (scan)
+				halbtc8723b1ant_action_wifi_not_connected_scan(
+					btcoexist);
+			else
+				halbtc8723b1ant_action_wifi_not_connected_asso_auth(
+					btcoexist);
+		} else
+			halbtc8723b1ant_action_wifi_not_connected(btcoexist);
+	} else	/* wifi LPS/Busy */
+		halbtc8723b1ant_action_wifi_connected(btcoexist);
+}
+
+void halbtc8723b1ant_init_coex_dm(IN struct btc_coexist *btcoexist)
+{
+	/* force to reset coex mechanism */
+
+	/* sw all off */
+	halbtc8723b1ant_sw_mechanism(btcoexist, false);
+
+	/* halbtc8723b1ant_ps_tdma(btcoexist, FORCE_EXEC, false, 8); */
+	/* halbtc8723b1ant_coex_table_with_type(btcoexist, FORCE_EXEC, 0); */
+
+	coex_sta->pop_event_cnt = 0;
+}
+
+void halbtc8723b1ant_init_hw_config(IN struct btc_coexist *btcoexist,
+				    IN boolean back_up, IN boolean wifi_only)
+{
+	u32				u32tmp = 0; /* , fw_ver; */
+	u8				u8tmpa = 0, u8tmpb = 0;
+
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+		    "[BTCoex], 1Ant Init HW Config!!\n");
+	BTC_TRACE(trace_buf);
+
+	psd_scan->ant_det_is_ant_det_available = false;
+
+
+	/* Give bt_coex_supported_version the default value */
+	coex_sta->bt_coex_supported_version = 0;
+
+	/* 0xf0[15:12] --> Chip Cut information */
+	coex_sta->cut_version = (btcoexist->btc_read_1byte(btcoexist,
+				 0xf1) & 0xf0) >> 4;
+
+	btcoexist->btc_write_1byte_bitmask(btcoexist, 0x550, 0x8,
+					   0x1);  /* enable TBTT nterrupt */
+
+	/* 0x790[5:0]=0x5	 */
+	btcoexist->btc_write_1byte(btcoexist, 0x790, 0x5);
+
+	/* Enable counter statistics */
+	/* btcoexist->btc_write_1byte(btcoexist, 0x76e, 0xc); */ /*0x76e[3] =1, WLAN_Act control by PTA */
+	btcoexist->btc_write_1byte(btcoexist, 0x778, 0x1);
+	btcoexist->btc_write_1byte_bitmask(btcoexist, 0x40, 0x20, 0x1);
+
+
+	/* btcoexist->btc_write_1byte_bitmask(btcoexist, 0x67, 0x20, 0x1); */ /*BT select s0/s1 is controlled by WiFi */
+
+	halbtc8723b1ant_ps_tdma(btcoexist, FORCE_EXEC, false, 8);
+
+	/* Antenna config */
+	if (wifi_only)
+		halbtc8723b1ant_set_ant_path(btcoexist, BTC_ANT_PATH_WIFI,
+					     FORCE_EXEC, true, false);
+	else
+		halbtc8723b1ant_set_ant_path(btcoexist, BTC_ANT_PATH_BT,
+					     FORCE_EXEC, true, false);
+
+	/* PTA parameter */
+	halbtc8723b1ant_coex_table_with_type(btcoexist, FORCE_EXEC, 0);
+
+	u32tmp = btcoexist->btc_read_4byte(btcoexist, 0x948);
+	u8tmpa = btcoexist->btc_read_1byte(btcoexist, 0x765);
+	u8tmpb = btcoexist->btc_read_1byte(btcoexist, 0x67);
+
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+		"############# [BTCoex], 0x948=0x%x, 0x765=0x%x, 0x67=0x%x\n",
+		    u32tmp,  u8tmpa, u8tmpb);
+	BTC_TRACE(trace_buf);
+
+}
+
+/* Donot remove optimize off flag, otherwise antenna detection would trigger BT collapsed */
+#ifdef PLATFORM_WINDOWS
+#pragma optimize("", off)
+#endif
+void halbtc8723b1ant_mechanism_switch(IN struct btc_coexist *btcoexist,
+				      IN boolean bSwitchTo2Antenna)
+{
+
+	if (bSwitchTo2Antenna) {
+
+		/* BT TRx mask off */
+		btcoexist->btc_set_bt_trx_mask(btcoexist, 0);
+
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			"############# [BTCoex], BT TRx Mask off for mechanism_switch\n");
+
+		BTC_TRACE(trace_buf);
+
+	} else {
+
+		/* BT TRx mask on */
+		btcoexist->btc_set_bt_trx_mask(btcoexist, 1);
+
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			"############# [BTCoex], BT TRx Mask on for mechanism_switch\n");
+
+		BTC_TRACE(trace_buf);
+	}
+
+
+#if 0
+	if (bSwitchTo2Antenna) { /* 1-Ant -> 2-Ant */
+		/* un-lock TRx Mask setup for 8723b f-cut */
+		btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0xdd, 0x80, 0x1);
+		btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0xdf, 0x1, 0x1);
+		/* WiFi TRx Mask on				 */
+		btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1, 0xfffff,
+					  0x0);
+
+		/* BT TRx Mask un-lock 0x2c[0], 0x30[0] = 1 */
+		btcoexist->btc_set_bt_reg(btcoexist, BTC_BT_REG_RF, 0x2c,
+					  0x7c45);
+		btcoexist->btc_set_bt_reg(btcoexist, BTC_BT_REG_RF, 0x30,
+					  0x7c45);
+
+		/* BT TRx Mask on */
+		btcoexist->btc_set_bt_reg(btcoexist, BTC_BT_REG_RF, 0x3c, 0x1);
+
+		halbtc8723b1ant_set_ant_path(btcoexist, BTC_ANT_PATH_BT,
+					     FORCE_EXEC, false, false);
+	} else {
+		/* WiFi TRx Mask on				 */
+		btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1, 0xfffff,
+					  0x780);
+
+		/* lock TRx Mask setup for 8723b f-cut */
+		btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0xdd, 0x80, 0x0);
+		btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0xdf, 0x1, 0x0);
+
+		/* BT TRx Mask on */
+		btcoexist->btc_set_bt_reg(btcoexist, BTC_BT_REG_RF, 0x3c, 0x15);
+
+		/* BT TRx Mask ock 0x2c[0], 0x30[0]  = 0 */
+		btcoexist->btc_set_bt_reg(btcoexist, BTC_BT_REG_RF, 0x2c,
+					  0x7c44);
+		btcoexist->btc_set_bt_reg(btcoexist, BTC_BT_REG_RF, 0x30,
+					  0x7c44);
+
+
+		halbtc8723b1ant_set_ant_path(btcoexist, BTC_ANT_PATH_PTA,
+					     FORCE_EXEC, false, false);
+	}
+
+#endif
+}
+
+u32 halbtc8723b1ant_psd_log2base(IN struct btc_coexist *btcoexist, IN u32 val)
+{
+	u8	j;
+	u32	tmp, tmp2, val_integerd_b = 0, tindex, shiftcount = 0;
+	u32	result, val_fractiond_b = 0, table_fraction[21] = {0, 432, 332, 274, 232, 200,
+				   174, 151, 132, 115, 100, 86, 74, 62, 51, 42,
+							   32, 23, 15, 7, 0
+							      };
+
+	if (val == 0)
+		return 0;
+
+	tmp = val;
+
+	while (1) {
+		if (tmp == 1)
+			break;
+
+		tmp = (tmp >> 1);
+		shiftcount++;
+	}
+
+
+	val_integerd_b = shiftcount + 1;
+
+	tmp2 = 1;
+	for (j = 1; j <= val_integerd_b; j++)
+		tmp2 = tmp2 * 2;
+
+	tmp = (val * 100) / tmp2;
+	tindex = tmp / 5;
+
+	if (tindex > 20)
+		tindex = 20;
+
+	val_fractiond_b = table_fraction[tindex];
+
+	result = val_integerd_b * 100 - val_fractiond_b;
+
+	return result;
+
+
+}
+
+void halbtc8723b1ant_psd_show_antenna_detect_result(IN struct btc_coexist
+		*btcoexist)
+{
+	u8		*cli_buf = btcoexist->cli_buf;
+	struct  btc_board_info	*board_info = &btcoexist->board_info;
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+		   "\r\n============[Antenna Detection info]  ============\n");
+	CL_PRINTF(cli_buf);
+
+	if (psd_scan->ant_det_result == 1)
+		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s (>%d)",
+			   "Ant Det Result", "2-Antenna (Bad-Isolation)",
+			   BT_8723B_1ANT_ANTDET_PSDTHRES_2ANT_BADISOLATION);
+	else if (psd_scan->ant_det_result == 2)
+		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s (%d~%d)",
+			   "Ant Det Result", "2-Antenna (Good-Isolation)",
+			   BT_8723B_1ANT_ANTDET_PSDTHRES_2ANT_GOODISOLATION
+			   + psd_scan->ant_det_thres_offset,
+			   BT_8723B_1ANT_ANTDET_PSDTHRES_2ANT_BADISOLATION);
+	else
+		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s (%d~%d)",
+			   "Ant Det Result", "1-Antenna",
+			   BT_8723B_1ANT_ANTDET_PSDTHRES_1ANT,
+			   BT_8723B_1ANT_ANTDET_PSDTHRES_2ANT_GOODISOLATION
+			   + psd_scan->ant_det_thres_offset);
+
+	CL_PRINTF(cli_buf);
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s ",
+		   "Antenna Detection Finish",
+		   (board_info->btdm_ant_det_finish
+		    ? "Yes" : "No"));
+	CL_PRINTF(cli_buf);
+
+	switch (psd_scan->ant_det_result) {
+	case 0:
+		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+			   "(BT is not available)");
+		break;
+	case 1:  /* 2-Ant bad-isolation */
+		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+			   "(BT is available)");
+		break;
+	case 2:  /* 2-Ant good-isolation */
+		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+			   "(BT is available)");
+		break;
+	case 3:  /* 1-Ant */
+		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+			   "(BT is available)");
+		break;
+	case 4:
+		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+			   "(Uncertainty result)");
+		break;
+	case 5:
+		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "(Pre-Scan fai)");
+		break;
+	case 6:
+		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+			   "(WiFi is Scanning)");
+		break;
+	case 7:
+		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+			   "(BT is not idle)");
+		break;
+	case 8:
+		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+			   "(Abort by WiFi Scanning)");
+		break;
+	case 9:
+		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+			   "(Antenna Init is not ready)");
+		break;
+	case 10:
+		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+			   "(BT is Inquiry or page)");
+		break;
+	case 11:
+		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+			   "(BT is Disabled)");
+		break;
+	}
+	CL_PRINTF(cli_buf);
+
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d",
+		   "Ant Detect Total Count", psd_scan->ant_det_try_count);
+	CL_PRINTF(cli_buf);
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d",
+		   "Ant Detect Fail Count", psd_scan->ant_det_fail_count);
+	CL_PRINTF(cli_buf);
+
+	if ((!board_info->btdm_ant_det_finish) &&
+	    (psd_scan->ant_det_result != 5))
+		return;
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s", "BT Response",
+		   (psd_scan->ant_det_result ? "ok" : "fail"));
+	CL_PRINTF(cli_buf);
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d ms", "BT Tx Time",
+		   psd_scan->ant_det_bt_tx_time);
+	CL_PRINTF(cli_buf);
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d", "BT Tx Ch",
+		   psd_scan->ant_det_bt_le_channel);
+	CL_PRINTF(cli_buf);
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d",
+		   "WiFi PSD Cent-Ch/Offset/Span",
+		   psd_scan->real_cent_freq, psd_scan->real_offset,
+		   psd_scan->real_span);
+	CL_PRINTF(cli_buf);
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d dB",
+		   "PSD Pre-Scan Peak Value",
+		   psd_scan->ant_det_pre_psdscan_peak_val / 100);
+	CL_PRINTF(cli_buf);
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s (<= %d)",
+		   "PSD Pre-Scan result",
+		   (psd_scan->ant_det_result != 5 ? "ok" : "fail"),
+		   BT_8723B_1ANT_ANTDET_PSDTHRES_BACKGROUND
+		   + psd_scan->ant_det_thres_offset);
+	CL_PRINTF(cli_buf);
+
+	if (psd_scan->ant_det_result == 5)
+		return;
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s dB",
+		   "PSD Scan Peak Value", psd_scan->ant_det_peak_val);
+	CL_PRINTF(cli_buf);
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s MHz",
+		   "PSD Scan Peak Freq", psd_scan->ant_det_peak_freq);
+	CL_PRINTF(cli_buf);
+
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s", "TFBGA Package",
+		   (board_info->tfbga_package) ?  "Yes" : "No");
+	CL_PRINTF(cli_buf);
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d",
+		   "PSD Threshold Offset", psd_scan->ant_det_thres_offset);
+	CL_PRINTF(cli_buf);
+
+}
+
+void halbtc8723b1ant_psd_showdata(IN struct btc_coexist *btcoexist)
+{
+	u8		*cli_buf = btcoexist->cli_buf;
+	u32		delta_freq_per_point;
+	u32		freq, freq1, freq2, n = 0, i = 0, j = 0, m = 0, psd_rep1, psd_rep2;
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+		   "\r\n\n============[PSD info]  (%d)============\n",
+		   psd_scan->psd_gen_count);
+	CL_PRINTF(cli_buf);
+
+	if (psd_scan->psd_gen_count == 0) {
+		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n No data !!\n");
+		CL_PRINTF(cli_buf);
+		return;
+	}
+
+	if (psd_scan->psd_point == 0)
+		delta_freq_per_point = 0;
+	else
+		delta_freq_per_point = psd_scan->psd_band_width /
+				       psd_scan->psd_point;
+
+	/* if (psd_scan->is_psd_show_max_only) */
+	if (0) {
+		psd_rep1 = psd_scan->psd_max_value / 100;
+		psd_rep2 = psd_scan->psd_max_value - psd_rep1 * 100;
+
+		freq = ((psd_scan->real_cent_freq - 20) * 1000000 +
+			psd_scan->psd_max_value_point * delta_freq_per_point);
+		freq1 = freq / 1000000;
+		freq2 = freq / 1000 - freq1 * 1000;
+
+		if (freq2 < 100)
+			CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+				   "\r\n Freq = %d.0%d MHz",
+				   freq1, freq2);
+		else
+			CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+				   "\r\n Freq = %d.%d MHz",
+				   freq1, freq2);
+
+		if (psd_rep2 < 10)
+			CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+				   ", Value = %d.0%d dB, (%d)\n",
+				   psd_rep1, psd_rep2, psd_scan->psd_max_value);
+		else
+			CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+				   ", Value = %d.%d dB, (%d)\n",
+				   psd_rep1, psd_rep2, psd_scan->psd_max_value);
+
+		CL_PRINTF(cli_buf);
+	} else {
+		m = psd_scan->psd_start_point;
+		n = psd_scan->psd_start_point;
+		i = 1;
+		j = 1;
+
+		while (1) {
+			do {
+				freq = ((psd_scan->real_cent_freq - 20) *
+					1000000 + m *
+					delta_freq_per_point);
+				freq1 = freq / 1000000;
+				freq2 = freq / 1000 - freq1 * 1000;
+
+				if (i == 1) {
+					if (freq2 == 0)
+						CL_SPRINTF(cli_buf,
+							   BT_TMP_BUF_SIZE,
+							   "\r\n Freq%6d.000",
+							   freq1);
+					else if (freq2 < 100)
+						CL_SPRINTF(cli_buf,
+							   BT_TMP_BUF_SIZE,
+							   "\r\n Freq%6d.0%2d",
+							   freq1,
+							   freq2);
+					else
+						CL_SPRINTF(cli_buf,
+							   BT_TMP_BUF_SIZE,
+							   "\r\n Freq%6d.%3d",
+							   freq1,
+							   freq2);
+				} else if ((i % 8 == 0) ||
+					   (m == psd_scan->psd_stop_point)) {
+					if (freq2 == 0)
+						CL_SPRINTF(cli_buf,
+							   BT_TMP_BUF_SIZE,
+							   "%6d.000\n", freq1);
+					else if (freq2 < 100)
+						CL_SPRINTF(cli_buf,
+							   BT_TMP_BUF_SIZE,
+							   "%6d.0%2d\n", freq1,
+							   freq2);
+					else
+						CL_SPRINTF(cli_buf,
+							   BT_TMP_BUF_SIZE,
+							   "%6d.%3d\n", freq1,
+							   freq2);
+				} else {
+					if (freq2 == 0)
+						CL_SPRINTF(cli_buf,
+							   BT_TMP_BUF_SIZE,
+							   "%6d.000", freq1);
+					else if (freq2 < 100)
+						CL_SPRINTF(cli_buf,
+							   BT_TMP_BUF_SIZE,
+							   "%6d.0%2d", freq1,
+							   freq2);
+					else
+						CL_SPRINTF(cli_buf,
+							   BT_TMP_BUF_SIZE,
+							   "%6d.%3d", freq1,
+							   freq2);
+				}
+
+				i++;
+				m++;
+				CL_PRINTF(cli_buf);
+
+			} while ((i <= 8) && (m <= psd_scan->psd_stop_point));
+
+
+			do {
+				psd_rep1 = psd_scan->psd_report_max_hold[n] /
+					   100;
+				psd_rep2 = psd_scan->psd_report_max_hold[n] -
+					   psd_rep1 *
+					   100;
+
+				if (j == 1) {
+					if (psd_rep2 < 10)
+						CL_SPRINTF(cli_buf,
+							   BT_TMP_BUF_SIZE,
+							   "\r\n Val %7d.0%d",
+							   psd_rep1,
+							   psd_rep2);
+					else
+						CL_SPRINTF(cli_buf,
+							   BT_TMP_BUF_SIZE,
+							   "\r\n Val %7d.%d",
+							   psd_rep1,
+							   psd_rep2);
+				} else if ((j % 8 == 0)  ||
+					   (n == psd_scan->psd_stop_point)) {
+					if (psd_rep2 < 10)
+						CL_SPRINTF(cli_buf,
+							   BT_TMP_BUF_SIZE,
+							"%7d.0%d\n", psd_rep1,
+							   psd_rep2);
+					else
+						CL_SPRINTF(cli_buf,
+							   BT_TMP_BUF_SIZE,
+							   "%7d.%d\n", psd_rep1,
+							   psd_rep2);
+				} else {
+					if (psd_rep2 < 10)
+						CL_SPRINTF(cli_buf,
+							   BT_TMP_BUF_SIZE,
+							   "%7d.0%d", psd_rep1,
+							   psd_rep2);
+					else
+						CL_SPRINTF(cli_buf,
+							   BT_TMP_BUF_SIZE,
+							   "%7d.%d", psd_rep1,
+							   psd_rep2);
+				}
+
+				j++;
+				n++;
+				CL_PRINTF(cli_buf);
+
+			} while ((j <= 8) && (n <= psd_scan->psd_stop_point));
+
+			if ((m > psd_scan->psd_stop_point) ||
+			    (n > psd_scan->psd_stop_point))
+				break;
+
+			i = 1;
+			j = 1;
+		}
+	}
+
+
+}
+
+void halbtc8723b1ant_psd_max_holddata(IN struct btc_coexist *btcoexist,
+				      IN u32 gen_count)
+{
+	u32	i = 0, i_max = 0, val_max = 0;
+
+	if (gen_count == 1) {
+		memcpy(psd_scan->psd_report_max_hold,
+		       psd_scan->psd_report,
+		       BT_8723B_1ANT_ANTDET_PSD_POINTS * sizeof(u32));
+
+		psd_scan->psd_max_value_point = 0;
+		psd_scan->psd_max_value = 0;
+
+	} else {
+		for (i = psd_scan->psd_start_point;
+		     i <= psd_scan->psd_stop_point; i++) {
+			if (psd_scan->psd_report[i] >
+			    psd_scan->psd_report_max_hold[i])
+				psd_scan->psd_report_max_hold[i] =
+					psd_scan->psd_report[i];
+
+			/* search Max Value */
+			if (i == psd_scan->psd_start_point) {
+				i_max = i;
+				val_max = psd_scan->psd_report_max_hold[i];
+			} else {
+				if (psd_scan->psd_report_max_hold[i] >
+				    val_max) {
+					i_max = i;
+					val_max = psd_scan->psd_report_max_hold[i];
+				}
+			}
+
+		}
+
+		psd_scan->psd_max_value_point = i_max;
+		psd_scan->psd_max_value = val_max;
+
+	}
+
+
+}
+
+u32 halbtc8723b1ant_psd_getdata(IN struct btc_coexist *btcoexist, IN u32 point)
+{
+	/* reg 0x808[9:0]: FFT data x */
+	/* reg 0x808[22]: 0-->1 to get 1 FFT data y */
+	/* reg 0x8b4[15:0]: FFT data y report */
+
+	u32 val = 0, psd_report = 0;
+	int k = 0;
+
+	val = btcoexist->btc_read_4byte(btcoexist, 0x808);
+
+	val &= 0xffbffc00;
+	val |= point;
+
+	btcoexist->btc_write_4byte(btcoexist, 0x808, val);
+
+	val |= 0x00400000;
+	btcoexist->btc_write_4byte(btcoexist, 0x808, val);
+
+	while (1) {
+		if (k++ > BT_8723B_1ANT_ANTDET_SWEEPPOINT_DELAY)
+			break;
+	}
+
+	val = btcoexist->btc_read_4byte(btcoexist, 0x8b4);
+
+	psd_report = val & 0x0000ffff;
+
+	return psd_report;
+}
+
+
+boolean halbtc8723b1ant_psd_sweep_point(IN struct btc_coexist *btcoexist,
+		IN u32 cent_freq, IN s32 offset, IN u32 span, IN u32 points,
+					IN u32 avgnum, IN u32 loopcnt)
+{
+	u32	 i, val, n, k = 0, j, point_index = 0;
+	u32	points1 = 0, psd_report = 0;
+	u32	start_p = 0, stop_p = 0, delta_freq_per_point = 156250;
+	u32    psd_center_freq = 20 * 10 ^ 6;
+	boolean outloop = false, scan , roam, is_sweep_ok = true;
+	u8	 flag = 0;
+	u32	tmp;
+	u32	wifi_original_channel = 1;
+
+	psd_scan->is_psd_running = true;
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+		    "xxxxxxxxxxxxxxxx PSD Sweep Start!!\n");
+	BTC_TRACE(trace_buf);
+
+	do {
+		switch (flag) {
+		case 0:  /* Get PSD parameters */
+		default:
+
+			psd_scan->psd_band_width = 40 * 1000000;
+			psd_scan->psd_point = points;
+			psd_scan->psd_start_base = points / 2;
+			psd_scan->psd_avg_num = avgnum;
+			psd_scan->real_cent_freq = cent_freq;
+			psd_scan->real_offset = offset;
+			psd_scan->real_span = span;
+
+
+			points1 = psd_scan->psd_point;
+			delta_freq_per_point = psd_scan->psd_band_width /
+					       psd_scan->psd_point;
+
+			/* PSD point setup */
+			val = btcoexist->btc_read_4byte(btcoexist, 0x808);
+			val &= 0xffff0fff;
+
+			switch (psd_scan->psd_point) {
+			case 128:
+				val |= 0x0;
+				break;
+			case 256:
+			default:
+				val |= 0x00004000;
+				break;
+			case 512:
+				val |= 0x00008000;
+				break;
+			case 1024:
+				val |= 0x0000c000;
+				break;
+			}
+
+			switch (psd_scan->psd_avg_num) {
+			case 1:
+				val |= 0x0;
+				break;
+			case 8:
+				val |= 0x00001000;
+				break;
+			case 16:
+				val |= 0x00002000;
+				break;
+			case 32:
+			default:
+				val |= 0x00003000;
+				break;
+			}
+			btcoexist->btc_write_4byte(btcoexist, 0x808, val);
+
+			flag = 1;
+			break;
+		case 1:	  /* calculate the PSD point index from freq/offset/span */
+			psd_center_freq = psd_scan->psd_band_width / 2 +
+					  offset * (1000000);
+
+			start_p = psd_scan->psd_start_base + (psd_center_freq -
+				span * (1000000) / 2) / delta_freq_per_point;
+			psd_scan->psd_start_point = start_p -
+						    psd_scan->psd_start_base;
+
+			stop_p = psd_scan->psd_start_base + (psd_center_freq +
+				span * (1000000) / 2) / delta_freq_per_point;
+			psd_scan->psd_stop_point = stop_p -
+						   psd_scan->psd_start_base - 1;
+
+			flag = 2;
+			break;
+		case 2:  /* set RF channel/BW/Mode */
+
+			/* set 3-wire off */
+			val = btcoexist->btc_read_4byte(btcoexist, 0x88c);
+			val |= 0x00300000;
+			btcoexist->btc_write_4byte(btcoexist, 0x88c, val);
+
+			/* CCK off */
+			val = btcoexist->btc_read_4byte(btcoexist, 0x800);
+			val &= 0xfeffffff;
+			btcoexist->btc_write_4byte(btcoexist, 0x800, val);
+
+			/* store WiFi original channel */
+			wifi_original_channel = btcoexist->btc_get_rf_reg(
+					btcoexist, BTC_RF_A, 0x18, 0x3ff);
+
+			/* Set RF channel */
+			if (cent_freq == 2484)
+				btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A,
+							  0x18, 0x3ff, 0xe);
+			else
+				btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A,
+					  0x18, 0x3ff, (cent_freq - 2412) / 5 +
+						  1); /* WiFi TRx Mask on */
+
+
+			/* Set RF Rx filter corner */
+			btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1e,
+						  0xfffff, 0x3e4);
+
+			/* Set TRx mask off */
+			/* un-lock TRx Mask setup */
+			btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0xdd,
+						  0x80, 0x1);
+			btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0xdf,
+						  0x1, 0x1);
+
+			btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1,
+						  0xfffff, 0x0);
+
+			/* Set  RF mode = Rx, RF Gain = 0x8a0 */
+			btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x0,
+						  0xfffff, 0x308a0);
+
+			while (1) {
+				if (k++ > BT_8723B_1ANT_ANTDET_SWEEPPOINT_DELAY)
+					break;
+			}
+			flag = 3;
+			break;
+		case 3:
+			psd_scan->psd_gen_count = 0;
+			for (j = 1; j <= loopcnt; j++) {
+
+				btcoexist->btc_get(btcoexist,
+						   BTC_GET_BL_WIFI_SCAN, &scan);
+				btcoexist->btc_get(btcoexist,
+						   BTC_GET_BL_WIFI_ROAM, &roam);
+
+				if (scan || roam) {
+					is_sweep_ok = false;
+					break;
+				}
+				memset(psd_scan->psd_report, 0,
+				       psd_scan->psd_point * sizeof(u32));
+				start_p = psd_scan->psd_start_point +
+					  psd_scan->psd_start_base;
+				stop_p = psd_scan->psd_stop_point +
+					 psd_scan->psd_start_base + 1;
+
+				i = start_p;
+				point_index = 0;
+
+				while (i < stop_p) {
+					if (i >= points1)
+						psd_report =
+							halbtc8723b1ant_psd_getdata(
+							btcoexist, i - points1);
+					else
+						psd_report =
+							halbtc8723b1ant_psd_getdata(
+								btcoexist, i);
+
+					BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+						"Point=%d, psd_raw_data = 0x%08x\n",
+						    i, psd_report);
+					BTC_TRACE(trace_buf);
+					if (psd_report == 0)
+						tmp = 0;
+					else
+						/* tmp =  20*log10((double)psd_report); */
+						/* 20*log2(x)/log2(10), log2Base return theresult of the psd_report*100 */
+						tmp = 6 * halbtc8723b1ant_psd_log2base(
+							btcoexist, psd_report);
+
+					n = i - psd_scan->psd_start_base;
+					psd_scan->psd_report[n] =  tmp;
+
+
+					halbtc8723b1ant_psd_max_holddata(
+						btcoexist, j);
+
+					i++;
+
+				}
+
+				psd_scan->psd_gen_count = j;
+			}
+
+			flag = 100;
+			break;
+		case 99:	/* error */
+
+			outloop = true;
+			break;
+		case 100: /* recovery */
+
+			/* set 3-wire on */
+			val = btcoexist->btc_read_4byte(btcoexist, 0x88c);
+			val &= 0xffcfffff;
+			btcoexist->btc_write_4byte(btcoexist, 0x88c, val);
+
+			/* CCK on */
+			val = btcoexist->btc_read_4byte(btcoexist, 0x800);
+			val |= 0x01000000;
+			btcoexist->btc_write_4byte(btcoexist, 0x800, val);
+
+			/* PSD off */
+			val = btcoexist->btc_read_4byte(btcoexist, 0x808);
+			val &= 0xffbfffff;
+			btcoexist->btc_write_4byte(btcoexist, 0x808, val);
+
+			/* TRx Mask on */
+			btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1,
+						  0xfffff, 0x780);
+
+			/* lock TRx Mask setup */
+			btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0xdd,
+						  0x80, 0x0);
+			btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0xdf,
+						  0x1, 0x0);
+
+			/* Set RF Rx filter corner */
+			btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1e,
+						  0xfffff, 0x0);
+
+			/* restore WiFi original channel */
+			btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x18,
+						  0x3ff, wifi_original_channel);
+
+			outloop = true;
+			break;
+
+		}
+
+	} while (!outloop);
+
+
+
+	psd_scan->is_psd_running = false;
+
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+		    "xxxxxxxxxxxxxxxx PSD Sweep Stop!!\n");
+	BTC_TRACE(trace_buf);
+	return is_sweep_ok;
+
+}
+
+void halbtc8723b1ant_psd_antenna_detection(IN struct btc_coexist *btcoexist,
+		IN u32 bt_tx_time, IN u32 bt_le_channel)
+{
+	u32	i = 0;
+	u32	wlpsd_cent_freq = 2484, wlpsd_span = 2, wlpsd_sweep_count = 50;
+	s32	wlpsd_offset = -4;
+	u8	bt_le_ch[13] = {3, 6, 8, 11, 13, 16, 18, 21, 23, 26, 28, 31, 33};
+
+	u8	h2c_parameter[3] = {0}, u8tmpa, u8tmpb;
+
+	u8	state = 0;
+	boolean		outloop = false, bt_resp = false;
+	u32		freq, freq1, freq2, psd_rep1, psd_rep2, delta_freq_per_point,
+			u32tmp;
+	struct  btc_board_info	*board_info = &btcoexist->board_info;
+
+	board_info->btdm_ant_det_finish = false;
+	memset(psd_scan->ant_det_peak_val, 0, 16 * sizeof(u8));
+	memset(psd_scan->ant_det_peak_freq, 0, 16 * sizeof(u8));
+
+	if (board_info->tfbga_package) /* for TFBGA */
+		psd_scan->ant_det_thres_offset = 5;
+	else
+		psd_scan->ant_det_thres_offset = 0;
+
+	do {
+		switch (state) {
+		case 0:
+			if (bt_le_channel == 39)
+				wlpsd_cent_freq = 2484;
+			else {
+				for (i = 1; i <= 13; i++) {
+					if (bt_le_ch[i - 1] ==
+					    bt_le_channel) {
+						wlpsd_cent_freq = 2412
+								  + (i - 1) * 5;
+						break;
+					}
+				}
+
+				if (i == 14) {
+
+					BTC_SPRINTF(trace_buf,
+						    BT_TMP_BUF_SIZE,
+						"xxxxxxxxxxxxxxxx AntennaDetect(), Abort!!, Invalid LE channel = %d\n ",
+						    bt_le_channel);
+					BTC_TRACE(trace_buf);
+					outloop = true;
+					break;
+				}
+			}
+
+			wlpsd_sweep_count = bt_tx_time * 238 /
+					    100; /* bt_tx_time/0.42								 */
+			wlpsd_sweep_count = wlpsd_sweep_count / 5;
+
+			if (wlpsd_sweep_count % 5 != 0)
+				wlpsd_sweep_count = (wlpsd_sweep_count /
+						     5 + 1) * 5;
+
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				"xxxxxxxxxxxxxxxx AntennaDetect(), BT_LETxTime=%d,  BT_LECh = %d\n",
+				    bt_tx_time, bt_le_channel);
+			BTC_TRACE(trace_buf);
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				"xxxxxxxxxxxxxxxx AntennaDetect(), wlpsd_cent_freq=%d,  wlpsd_offset = %d, wlpsd_span = %d, wlpsd_sweep_count = %d\n",
+				    wlpsd_cent_freq,
+				    wlpsd_offset,
+				    wlpsd_span,
+				    wlpsd_sweep_count);
+			BTC_TRACE(trace_buf);
+
+			state = 1;
+			break;
+		case 1: /* stop coex DM & set antenna path */
+			/* Stop Coex DM */
+
+			/*
+			btcoexist->stop_coex_dm = true;
+
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				"xxxxxxxxxxxxxxxx AntennaDetect(), Stop Coex DM!!\n");
+			BTC_TRACE(trace_buf);  */
+
+			/* Set TDMA off,				 */
+			halbtc8723b1ant_ps_tdma(btcoexist, FORCE_EXEC,
+						false, 0);
+
+			/* Set coex table */
+			halbtc8723b1ant_coex_table_with_type(btcoexist,
+							     FORCE_EXEC, 0);
+
+			if (board_info->btdm_ant_pos ==
+			    BTC_ANTENNA_AT_MAIN_PORT) {
+				BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+					"xxxxxxxxxxxxxxxx AntennaDetect(), Antenna at Main Port\n");
+				BTC_TRACE(trace_buf);
+			} else {
+				BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+					"xxxxxxxxxxxxxxxx AntennaDetect(), Antenna at Aux Port\n");
+				BTC_TRACE(trace_buf);
+			}
+
+			/* Set Antenna path, switch WiFi to un-certain antenna port */
+			halbtc8723b1ant_set_ant_path(btcoexist,
+					     BTC_ANT_PATH_BT, FORCE_EXEC, false,
+						     false);
+
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				"xxxxxxxxxxxxxxxx AntennaDetect(), Set Antenna to BT!!\n");
+			BTC_TRACE(trace_buf);
+
+			/* Set AFH mask on at WiFi channel 2472MHz +/- 10MHz */
+			h2c_parameter[0] = 0x1;
+			h2c_parameter[1] = 0xd;
+			h2c_parameter[2] = 0x14;
+
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				"xxxxxxxxxxxxxxxx AntennaDetect(), Set AFH on, Cent-Ch= %d,  Mask=%d\n",
+				    h2c_parameter[1],
+				    h2c_parameter[2]);
+			BTC_TRACE(trace_buf);
+
+			btcoexist->btc_fill_h2c(btcoexist, 0x66, 3,
+						h2c_parameter);
+
+			u32tmp = btcoexist->btc_read_4byte(btcoexist,
+							   0x948);
+			u8tmpa = btcoexist->btc_read_1byte(btcoexist, 0x765);
+			u8tmpb = btcoexist->btc_read_1byte(btcoexist,
+							   0x778);
+
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				"############# [BTCoex], 0x948=0x%x, 0x765=0x%x, 0x778=0x%x\n",
+				    u32tmp,  u8tmpa, u8tmpb);
+			BTC_TRACE(trace_buf);
+
+			state = 2;
+			break;
+		case 2:	/* Pre-sweep background psd */
+			if (!halbtc8723b1ant_psd_sweep_point(btcoexist,
+				     wlpsd_cent_freq, wlpsd_offset, wlpsd_span,
+					     BT_8723B_1ANT_ANTDET_PSD_POINTS,
+				     BT_8723B_1ANT_ANTDET_PSD_AVGNUM, 3)) {
+				board_info->btdm_ant_det_finish = false;
+				board_info->btdm_ant_num_by_ant_det = 1;
+				psd_scan->ant_det_result = 8;
+				state = 99;
+				break;
+			}
+
+			psd_scan->ant_det_pre_psdscan_peak_val =
+				psd_scan->psd_max_value;
+
+			if (psd_scan->psd_max_value >
+			    (BT_8723B_1ANT_ANTDET_PSDTHRES_BACKGROUND
+			     + psd_scan->ant_det_thres_offset) * 100) {
+				BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+					"xxxxxxxxxxxxxxxx AntennaDetect(), Abort Antenna Detection!! becaus background = %d > thres (%d)\n",
+					    psd_scan->psd_max_value / 100,
+					BT_8723B_1ANT_ANTDET_PSDTHRES_BACKGROUND
+					    + psd_scan->ant_det_thres_offset);
+				BTC_TRACE(trace_buf);
+				board_info->btdm_ant_det_finish = false;
+				board_info->btdm_ant_num_by_ant_det = 1;
+				psd_scan->ant_det_result = 5;
+				state = 99;
+			} else {
+				BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+					"xxxxxxxxxxxxxxxx AntennaDetect(), Start Antenna Detection!! becaus background = %d <= thres (%d)\n",
+					    psd_scan->psd_max_value / 100,
+					BT_8723B_1ANT_ANTDET_PSDTHRES_BACKGROUND
+					    + psd_scan->ant_det_thres_offset);
+				BTC_TRACE(trace_buf);
+				state = 3;
+			}
+			break;
+		case 3:
+			bt_resp = btcoexist->btc_set_bt_ant_detection(
+					  btcoexist, (u8)(bt_tx_time & 0xff),
+					  (u8)(bt_le_channel & 0xff));
+
+			if (!halbtc8723b1ant_psd_sweep_point(btcoexist,
+					     wlpsd_cent_freq, wlpsd_offset,
+							     wlpsd_span,
+					     BT_8723B_1ANT_ANTDET_PSD_POINTS,
+					     BT_8723B_1ANT_ANTDET_PSD_AVGNUM,
+						     wlpsd_sweep_count)) {
+				board_info->btdm_ant_det_finish = false;
+				board_info->btdm_ant_num_by_ant_det = 1;
+				psd_scan->ant_det_result = 8;
+				state = 99;
+				break;
+			}
+
+			psd_scan->ant_det_psd_scan_peak_val =
+				psd_scan->psd_max_value;
+			psd_scan->ant_det_psd_scan_peak_freq =
+				psd_scan->psd_max_value_point;
+			state = 4;
+			break;
+		case 4:
+
+			if (psd_scan->psd_point == 0)
+				delta_freq_per_point = 0;
+			else
+				delta_freq_per_point =
+					psd_scan->psd_band_width /
+					psd_scan->psd_point;
+
+			psd_rep1 = psd_scan->psd_max_value / 100;
+			psd_rep2 = psd_scan->psd_max_value - psd_rep1 *
+				   100;
+
+			freq = ((psd_scan->real_cent_freq - 20) *
+				1000000 + psd_scan->psd_max_value_point
+				* delta_freq_per_point);
+			freq1 = freq / 1000000;
+			freq2 = freq / 1000 - freq1 * 1000;
+
+			if (freq2 < 100) {
+				BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+					"xxxxxxxxxxxxxxxx AntennaDetect(), Max Value: Freq = %d.0%d MHz",
+					    freq1, freq2);
+				BTC_TRACE(trace_buf);
+				CL_SPRINTF(psd_scan->ant_det_peak_freq,
+					   BT_8723B_1ANT_ANTDET_BUF_LEN,
+					   "%d.0%d", freq1, freq2);
+			} else {
+				BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+					"xxxxxxxxxxxxxxxx AntennaDetect(), Max Value: Freq = %d.%d MHz",
+					    freq1, freq2);
+				BTC_TRACE(trace_buf);
+				CL_SPRINTF(psd_scan->ant_det_peak_freq,
+					   BT_8723B_1ANT_ANTDET_BUF_LEN,
+					   "%d.%d", freq1, freq2);
+			}
+
+			if (psd_rep2 < 10) {
+				BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+					    ", Value = %d.0%d dB\n",
+					    psd_rep1, psd_rep2);
+				BTC_TRACE(trace_buf);
+				CL_SPRINTF(psd_scan->ant_det_peak_val,
+					   BT_8723B_1ANT_ANTDET_BUF_LEN,
+					   "%d.0%d", psd_rep1, psd_rep2);
+			} else {
+				BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+					    ", Value = %d.%d dB\n",
+					    psd_rep1, psd_rep2);
+				BTC_TRACE(trace_buf);
+				CL_SPRINTF(psd_scan->ant_det_peak_val,
+					   BT_8723B_1ANT_ANTDET_BUF_LEN,
+					   "%d.%d", psd_rep1, psd_rep2);
+			}
+
+			psd_scan->ant_det_is_btreply_available = true;
+
+			if (bt_resp == false) {
+				psd_scan->ant_det_is_btreply_available =
+					false;
+				psd_scan->ant_det_result = 0;
+				board_info->btdm_ant_det_finish = false;
+				board_info->btdm_ant_num_by_ant_det = 1;
+				BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+					"xxxxxxxxxxxxxxxx AntennaDetect(), BT Response = Fail\n ");
+				BTC_TRACE(trace_buf);
+			} else if (psd_scan->psd_max_value >
+				(BT_8723B_1ANT_ANTDET_PSDTHRES_2ANT_BADISOLATION)
+				   * 100) {
+				psd_scan->ant_det_result = 1;
+				board_info->btdm_ant_det_finish = true;
+				board_info->btdm_ant_det_already_init_phydm =
+					true;
+				board_info->btdm_ant_num_by_ant_det = 2;
+				BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+					"xxxxxxxxxxxxxxxx AntennaDetect(), Detect Result = 2-Ant, Bad-Isolation!!\n");
+				BTC_TRACE(trace_buf);
+			} else if (psd_scan->psd_max_value >
+				(BT_8723B_1ANT_ANTDET_PSDTHRES_2ANT_GOODISOLATION
+				    + psd_scan->ant_det_thres_offset) * 100) {
+				psd_scan->ant_det_result = 2;
+				board_info->btdm_ant_det_finish = true;
+				board_info->btdm_ant_det_already_init_phydm =
+					true;
+				board_info->btdm_ant_num_by_ant_det = 2;
+				BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+					"xxxxxxxxxxxxxxxx AntennaDetect(), Detect Result = 2-Ant, Good-Isolation!!\n");
+				BTC_TRACE(trace_buf);
+			} else if (psd_scan->psd_max_value >
+				   (BT_8723B_1ANT_ANTDET_PSDTHRES_1ANT) *
+				   100) {
+				psd_scan->ant_det_result = 3;
+				board_info->btdm_ant_det_finish = true;
+				board_info->btdm_ant_det_already_init_phydm =
+					true;
+				board_info->btdm_ant_num_by_ant_det = 1;
+				BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+					"xxxxxxxxxxxxxxxx AntennaDetect(), Detect Result = 1-Ant!!\n");
+				BTC_TRACE(trace_buf);
+			} else {
+				psd_scan->ant_det_result = 4;
+				board_info->btdm_ant_det_finish = false;
+				board_info->btdm_ant_num_by_ant_det = 1;
+				BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+					"xxxxxxxxxxxxxxxx AntennaDetect(), Detect Result = 1-Ant, un-certainity!!\n");
+				BTC_TRACE(trace_buf);
+			}
+
+			state = 99;
+			break;
+		case 99:  /* restore setup */
+
+			/* Set AFH mask off at WiFi channel 2472MHz +/- 10MHz */
+			h2c_parameter[0] = 0x0;
+			h2c_parameter[1] = 0x0;
+			h2c_parameter[2] = 0x0;
+
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				"xxxxxxxxxxxxxxxx AntennaDetect(), Set AFH on, Cent-Ch= %d,  Mask=%d\n",
+				    h2c_parameter[1], h2c_parameter[2]);
+			BTC_TRACE(trace_buf);
+
+			btcoexist->btc_fill_h2c(btcoexist, 0x66, 3,
+						h2c_parameter);
+
+			/* Set Antenna Path					 */
+			halbtc8723b1ant_set_ant_path(btcoexist,
+				     BTC_ANT_PATH_PTA, FORCE_EXEC, false,
+						     false);
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				"xxxxxxxxxxxxxxxx AntennaDetect(), Set Antenna to PTA\n!!");
+			BTC_TRACE(trace_buf);
+
+			/* Resume Coex DM */
+			/*
+			btcoexist->stop_coex_dm = false;
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				"xxxxxxxxxxxxxxxx AntennaDetect(), Resume Coex DM\n!!");
+			BTC_TRACE(trace_buf); */
+
+			/* stimulate coex running */
+			/*
+			halbtc8723b1ant_run_coexist_mechanism(
+				btcoexist);
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				"xxxxxxxxxxxxxxxx AntennaDetect(), Stimulate Coex running\n!!");
+			BTC_TRACE(trace_buf);
+			*/
+
+			outloop = true;
+			break;
+		}
+
+	} while (!outloop);
+
+
+
+}
+
+void halbtc8723b1ant_psd_antenna_detection_check(IN struct btc_coexist
+		*btcoexist)
+{
+	static u32 ant_det_count = 0, ant_det_fail_count = 0;
+	struct  btc_board_info	*board_info = &btcoexist->board_info;
+
+	boolean scan, roam;
+
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_SCAN, &scan);
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_ROAM, &roam);
+
+
+	/* psd_scan->ant_det_bt_tx_time = 20; */
+	psd_scan->ant_det_bt_tx_time =
+		BT_8723B_1ANT_ANTDET_BTTXTIME;	   /* 0.42ms*50 = 20ms (0.42ms = 1 PSD sweep) */
+	psd_scan->ant_det_bt_le_channel = BT_8723B_1ANT_ANTDET_BTTXCHANNEL;
+
+	ant_det_count++;
+
+	psd_scan->ant_det_try_count = ant_det_count;
+
+	if (scan || roam) {
+		board_info->btdm_ant_det_finish = false;
+		psd_scan->ant_det_result = 6;
+	} else if (coex_sta->bt_disabled) {
+		board_info->btdm_ant_det_finish = false;
+		psd_scan->ant_det_result = 11;
+	} else if (coex_sta->num_of_profile >= 1) {
+		board_info->btdm_ant_det_finish = false;
+		psd_scan->ant_det_result = 7;
+	} else if (
+		!psd_scan->ant_det_is_ant_det_available) { /* Antenna initial setup is not ready */
+		board_info->btdm_ant_det_finish = false;
+		psd_scan->ant_det_result = 9;
+	} else if (coex_sta->c2h_bt_inquiry_page) {
+		board_info->btdm_ant_det_finish = false;
+		psd_scan->ant_det_result = 10;
+	} else {
+		btcoexist->stop_coex_dm = true;
+
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			"xxxxxxxxxxxxxxxx AntennaDetect(), Stop Coex DM!!\n");
+		BTC_TRACE(trace_buf);
+
+		halbtc8723b1ant_psd_antenna_detection(btcoexist,
+					      psd_scan->ant_det_bt_tx_time,
+					      psd_scan->ant_det_bt_le_channel);
+
+		delay_ms(psd_scan->ant_det_bt_tx_time);
+
+		btcoexist->stop_coex_dm = false;
+
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			"xxxxxxxxxxxxxxxx AntennaDetect(), Resume Coex DM\n!!");
+		BTC_TRACE(trace_buf);
+
+		/* stimulate coex running */
+
+		halbtc8723b1ant_run_coexist_mechanism(
+			btcoexist);
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			"xxxxxxxxxxxxxxxx AntennaDetect(), Stimulate Coex running\n!!");
+		BTC_TRACE(trace_buf);
+	}
+
+	board_info->ant_det_result = psd_scan->ant_det_result;
+	if (!board_info->btdm_ant_det_finish)
+		ant_det_fail_count++;
+
+	psd_scan->ant_det_fail_count = ant_det_fail_count;
+
+}
+
+
+/* ************************************************************
+ * work around function start with wa_halbtc8723b1ant_
+ * ************************************************************
+ * ************************************************************
+ * extern function start with ex_halbtc8723b1ant_
+ * ************************************************************ */
+void ex_halbtc8723b1ant_power_on_setting(IN struct btc_coexist *btcoexist)
+{
+	struct  btc_board_info	*board_info = &btcoexist->board_info;
+	u8				u8tmp = 0x0;
+	u16				u16tmp = 0x0;
+	u32				value;
+
+
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+		"xxxxxxxxxxxxxxxx Execute 8723b 1-Ant PowerOn Setting xxxxxxxxxxxxxxxx!!\n");
+	BTC_TRACE(trace_buf);
+
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+		    "Ant Det Finish = %s, Ant Det Number  = %d\n",
+		    (board_info->btdm_ant_det_finish ? "Yes" : "No"),
+		    board_info->btdm_ant_num_by_ant_det);
+	BTC_TRACE(trace_buf);
+
+
+	btcoexist->stop_coex_dm = true;
+
+	btcoexist->btc_write_1byte(btcoexist, 0x67, 0x20);
+
+	/* enable BB, REG_SYS_FUNC_EN such that we can write 0x948 correctly. */
+	u16tmp = btcoexist->btc_read_2byte(btcoexist, 0x2);
+	btcoexist->btc_write_2byte(btcoexist, 0x2, u16tmp | BIT(0) | BIT(1));
+
+	/* set GRAN_BT = 1 */
+	btcoexist->btc_write_1byte(btcoexist, 0x765, 0x18);
+	/* set WLAN_ACT = 0 */
+	btcoexist->btc_write_1byte(btcoexist, 0x76e, 0x4);
+
+	/* */
+	/* S0 or S1 setting and Local register setting(By the setting fw can get ant number, S0/S1, ... info) */
+	/* Local setting bit define */
+	/*	BIT0: "0" for no antenna inverse; "1" for antenna inverse  */
+	/*	BIT1: "0" for internal switch; "1" for external switch */
+	/*	BIT2: "0" for one antenna; "1" for two antenna */
+	/* NOTE: here default all internal switch and 1-antenna ==> BIT1=0 and BIT2=0 */
+	if (btcoexist->chip_interface == BTC_INTF_USB) {
+		/* fixed at S0 for USB interface */
+		btcoexist->btc_write_4byte(btcoexist, 0x948, 0x0);
+
+		u8tmp |= 0x1;	/* antenna inverse */
+		btcoexist->btc_write_local_reg_1byte(btcoexist, 0xfe08, u8tmp);
+
+		board_info->btdm_ant_pos = BTC_ANTENNA_AT_AUX_PORT;
+	} else {
+		/* for PCIE and SDIO interface, we check efuse 0xc3[6] */
+		if (board_info->single_ant_path == 0) {
+			/* set to S1 */
+			btcoexist->btc_write_4byte(btcoexist, 0x948, 0x280);
+			board_info->btdm_ant_pos = BTC_ANTENNA_AT_MAIN_PORT;
+			value = 1;
+		} else if (board_info->single_ant_path == 1) {
+			/* set to S0 */
+			btcoexist->btc_write_4byte(btcoexist, 0x948, 0x0);
+			u8tmp |= 0x1;	/* antenna inverse */
+			board_info->btdm_ant_pos = BTC_ANTENNA_AT_AUX_PORT;
+			value = 0;
+		}
+
+		btcoexist->btc_set(btcoexist, BTC_SET_ACT_ANTPOSREGRISTRY_CTRL,
+				   &value);
+
+		if (btcoexist->chip_interface == BTC_INTF_PCI)
+			btcoexist->btc_write_local_reg_1byte(btcoexist, 0x384,
+							     u8tmp);
+		else if (btcoexist->chip_interface == BTC_INTF_SDIO)
+			btcoexist->btc_write_local_reg_1byte(btcoexist, 0x60,
+							     u8tmp);
+	}
+}
+
+void ex_halbtc8723b1ant_pre_load_firmware(IN struct btc_coexist *btcoexist)
+{
+}
+
+void ex_halbtc8723b1ant_init_hw_config(IN struct btc_coexist *btcoexist,
+				       IN boolean wifi_only)
+{
+	halbtc8723b1ant_init_hw_config(btcoexist, true, wifi_only);
+	btcoexist->stop_coex_dm = false;
+}
+
+void ex_halbtc8723b1ant_init_coex_dm(IN struct btc_coexist *btcoexist)
+{
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+		    "[BTCoex], Coex Mechanism Init!!\n");
+	BTC_TRACE(trace_buf);
+
+	btcoexist->stop_coex_dm = false;
+
+	halbtc8723b1ant_init_coex_dm(btcoexist);
+
+	halbtc8723b1ant_query_bt_info(btcoexist);
+}
+
+void ex_halbtc8723b1ant_display_coex_info(IN struct btc_coexist *btcoexist)
+{
+	struct  btc_board_info	*board_info = &btcoexist->board_info;
+	struct  btc_bt_link_info	*bt_link_info = &btcoexist->bt_link_info;
+	u8				*cli_buf = btcoexist->cli_buf;
+	u8				u8tmp[4], i, bt_info_ext, ps_tdma_case = 0;
+	u16				u16tmp[4];
+	u32				u32tmp[4];
+	u32				fa_ofdm, fa_cck, cca_ofdm, cca_cck;
+	u32				fw_ver = 0, bt_patch_ver = 0;
+	u32				bt_coex_ver = 0;
+	static u8			pop_report_in_10s = 0;
+	u32				phyver = 0;
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+		   "\r\n ============[BT Coexist info]============");
+	CL_PRINTF(cli_buf);
+
+	if (btcoexist->manual_control) {
+		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+			"\r\n ============[Under Manual Control]============");
+		CL_PRINTF(cli_buf);
+		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+			   "\r\n ==========================================");
+		CL_PRINTF(cli_buf);
+	}
+	if (btcoexist->stop_coex_dm) {
+		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+			   "\r\n ============[Coex is STOPPED]============");
+		CL_PRINTF(cli_buf);
+		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+			   "\r\n ==========================================");
+		CL_PRINTF(cli_buf);
+	}
+
+	if (psd_scan->ant_det_try_count == 0) {
+		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d",
+			   "Ant PG Num/ Mech/ Pos",
+			   board_info->pg_ant_num, board_info->btdm_ant_num,
+			   board_info->btdm_ant_pos);
+		CL_PRINTF(cli_buf);
+	} else {
+		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+			   "\r\n %-35s = %d/ %d/ %d  (%d/%d/%d)",
+			   "Ant PG Num/ Mech(Ant_Det)/ Pos",
+			   board_info->pg_ant_num,
+			   board_info->btdm_ant_num_by_ant_det,
+			   board_info->btdm_ant_pos,
+			   psd_scan->ant_det_try_count,
+			   psd_scan->ant_det_fail_count,
+			   psd_scan->ant_det_result);
+		CL_PRINTF(cli_buf);
+
+		if (board_info->btdm_ant_det_finish) {
+			CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s",
+				   "Ant Det PSD Value",
+				   psd_scan->ant_det_peak_val);
+			CL_PRINTF(cli_buf);
+		}
+	}
+
+	if (board_info->ant_det_result_five_complete) {
+		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+			   "\r\n %-35s = %d",
+			   "Ant number by AntDet",
+			   board_info->btdm_ant_num_by_ant_det);
+		CL_PRINTF(cli_buf);
+	}
+
+	/* btcoexist->btc_get(btcoexist, BTC_GET_U4_BT_PATCH_VER, &bt_patch_ver); */
+	bt_patch_ver = btcoexist->bt_info.bt_get_fw_ver;
+	btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_FW_VER, &fw_ver);
+	phyver = btcoexist->btc_get_bt_phydm_version(btcoexist);
+	bt_coex_ver = ((coex_sta->bt_coex_supported_version & 0xff00) >> 8);
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+		   "\r\n %-35s = %d_%02x/ 0x%02x/ 0x%02x (%s)",
+		   "CoexVer WL/  BT_Desired/ BT_Report",
+		   glcoex_ver_date_8723b_1ant, glcoex_ver_8723b_1ant,
+		   glcoex_ver_btdesired_8723b_1ant,
+		   bt_coex_ver,
+		   (bt_coex_ver == 0xff ? "Unknown" :
+		    (bt_coex_ver >= glcoex_ver_btdesired_8723b_1ant ?
+		     "Match" : "Mis-Match")));
+	CL_PRINTF(cli_buf);
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+		   "\r\n %-35s = 0x%x/ 0x%x/ v%d/ %c",
+		   "W_FW/ B_FW/ Phy/ Kt",
+		   fw_ver, bt_patch_ver, phyver,
+		   coex_sta->cut_version + 65);
+	CL_PRINTF(cli_buf);
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %02x %02x %02x ",
+		   "Wifi channel informed to BT",
+		   coex_dm->wifi_chnl_info[0], coex_dm->wifi_chnl_info[1],
+		   coex_dm->wifi_chnl_info[2]);
+	CL_PRINTF(cli_buf);
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s/ %s/ %s",
+		   "WifibHiPri/ Ccklock/ CckEverLock",
+		   (coex_sta->wifi_is_high_pri_task ? "Yes" : "No"),
+		   (coex_sta->cck_lock ? "Yes" : "No"),
+		   (coex_sta->cck_ever_lock ? "Yes" : "No"));
+	CL_PRINTF(cli_buf);
+
+	/* wifi status */
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s",
+		   "============[Wifi Status]============");
+	CL_PRINTF(cli_buf);
+	btcoexist->btc_disp_dbg_msg(btcoexist, BTC_DBG_DISP_WIFI_STATUS);
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s",
+		   "============[BT Status]============");
+	CL_PRINTF(cli_buf);
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s",
+		   "BT Abnormal scan",
+		   (coex_sta->bt_abnormal_scan) ? "Yes" : "No");
+	CL_PRINTF(cli_buf);
+
+	pop_report_in_10s++;
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = [%s/ %d/ %d/ %d] ",
+		   "BT [status/ rssi/ retryCnt/ popCnt]",
+		   ((coex_sta->bt_disabled) ? ("disabled") :	((
+		   coex_sta->c2h_bt_inquiry_page) ? ("inquiry/page scan")
+			   : ((BT_8723B_1ANT_BT_STATUS_NON_CONNECTED_IDLE ==
+			       coex_dm->bt_status) ? "non-connected idle" :
+		((BT_8723B_1ANT_BT_STATUS_CONNECTED_IDLE == coex_dm->bt_status)
+				       ? "connected-idle" : "busy")))),
+		   coex_sta->bt_rssi, coex_sta->bt_retry_cnt,
+		   coex_sta->pop_event_cnt);
+	CL_PRINTF(cli_buf);
+
+	if (pop_report_in_10s >= 5) {
+		coex_sta->pop_event_cnt = 0;
+		pop_report_in_10s = 0;
+	}
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+		   "\r\n %-35s = %d / %d / %d / %d / %d / %d",
+		   "SCO/HID/PAN/A2DP/NameReq/WHQL",
+		   bt_link_info->sco_exist, bt_link_info->hid_exist,
+		   bt_link_info->pan_exist, bt_link_info->a2dp_exist,
+		   coex_sta->c2h_bt_remote_name_req,
+		   coex_sta->bt_whck_test);
+	CL_PRINTF(cli_buf);
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s",
+		   "BT Role",
+		   (bt_link_info->slave_role) ? "Slave" : "Master");
+	CL_PRINTF(cli_buf);
+
+	bt_info_ext = coex_sta->bt_info_ext;
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s/ %d",
+		   "A2DP Rate/Bitpool",
+		(bt_info_ext & BIT(0)) ? "BR" : "EDR", coex_sta->a2dp_bit_pool);
+	CL_PRINTF(cli_buf);
+
+	for (i = 0; i < BT_INFO_SRC_8723B_1ANT_MAX; i++) {
+		if (coex_sta->bt_info_c2h_cnt[i]) {
+			CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+				"\r\n %-35s = %02x %02x %02x %02x %02x %02x %02x(%d)",
+				   glbt_info_src_8723b_1ant[i],
+				   coex_sta->bt_info_c2h[i][0],
+				   coex_sta->bt_info_c2h[i][1],
+				   coex_sta->bt_info_c2h[i][2],
+				   coex_sta->bt_info_c2h[i][3],
+				   coex_sta->bt_info_c2h[i][4],
+				   coex_sta->bt_info_c2h[i][5],
+				   coex_sta->bt_info_c2h[i][6],
+				   coex_sta->bt_info_c2h_cnt[i]);
+			CL_PRINTF(cli_buf);
+		}
+	}
+
+
+	if (btcoexist->manual_control)
+		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s",
+			"============[mechanisms] (before Manual)============");
+	else
+		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s",
+			   "============[mechanisms]============");
+	CL_PRINTF(cli_buf);
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d",
+		   "SM[LowPenaltyRA]",
+		   coex_dm->cur_low_penalty_ra);
+	CL_PRINTF(cli_buf);
+
+	ps_tdma_case = coex_dm->cur_ps_tdma;
+	if (board_info->btdm_ant_num_by_ant_det == 2) {
+		if (coex_dm->cur_ps_tdma_on)
+			ps_tdma_case = ps_tdma_case +
+				100; /* for WiFi RSSI low or BT RSSI low */
+		else
+			ps_tdma_case =
+				1; /* always translate to TDMA(off,1) for TDMA-off case */
+	}
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+		   "\r\n %-35s = %02x %02x %02x %02x %02x case-%d (%s,%s)",
+		   "PS TDMA",
+		   coex_dm->ps_tdma_para[0], coex_dm->ps_tdma_para[1],
+		   coex_dm->ps_tdma_para[2], coex_dm->ps_tdma_para[3],
+		   coex_dm->ps_tdma_para[4], ps_tdma_case,
+		   (coex_dm->cur_ps_tdma_on ? "On" : "Off"),
+		   (coex_dm->auto_tdma_adjust ? "Adj" : "Fix"));
+
+	CL_PRINTF(cli_buf);
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d",
+		   "Coex Table Type",
+		   coex_sta->coex_table_type);
+	CL_PRINTF(cli_buf);
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d",
+		   "IgnWlanAct",
+		   coex_dm->cur_ignore_wlan_act);
+	CL_PRINTF(cli_buf);
+
+	/*
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x ", "Latest error condition(should be 0)",
+		coex_dm->error_condition);
+	CL_PRINTF(cli_buf);
+	*/
+
+	/* Hw setting		 */
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s",
+		   "============[Hw setting]============");
+	CL_PRINTF(cli_buf);
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/0x%x/0x%x/0x%x",
+		   "backup ARFR1/ARFR2/RL/AMaxTime",
+		   coex_dm->backup_arfr_cnt1, coex_dm->backup_arfr_cnt2,
+		   coex_dm->backup_retry_limit,
+		   coex_dm->backup_ampdu_max_time);
+	CL_PRINTF(cli_buf);
+
+	u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x430);
+	u32tmp[1] = btcoexist->btc_read_4byte(btcoexist, 0x434);
+	u16tmp[0] = btcoexist->btc_read_2byte(btcoexist, 0x42a);
+	u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x456);
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/0x%x/0x%x/0x%x",
+		   "0x430/0x434/0x42a/0x456",
+		   u32tmp[0], u32tmp[1], u16tmp[0], u8tmp[0]);
+	CL_PRINTF(cli_buf);
+
+	u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x778);
+	u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x6cc);
+	u32tmp[1] = btcoexist->btc_read_4byte(btcoexist, 0x880);
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x/ 0x%x",
+		   "0x778/0x6cc/0x880[29:25]",
+		   u8tmp[0], u32tmp[0], (u32tmp[1] & 0x3e000000) >> 25);
+	CL_PRINTF(cli_buf);
+
+	u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x948);
+	u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x67);
+	u32tmp[1] = btcoexist->btc_read_4byte(btcoexist, 0x764);
+	u8tmp[1] = btcoexist->btc_read_1byte(btcoexist, 0x76e);
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+		   "\r\n %-35s = 0x%x/ 0x%x/ 0x%x/ 0x%x",
+		   "0x948/ 0x67[5] / 0x764 / 0x76e",
+		   u32tmp[0], ((u8tmp[0] & 0x20) >> 5), (u32tmp[1] & 0xffff),
+		   u8tmp[1]);
+	CL_PRINTF(cli_buf);
+
+	u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x92c);
+	u32tmp[1] = btcoexist->btc_read_4byte(btcoexist, 0x930);
+	u32tmp[2] = btcoexist->btc_read_4byte(btcoexist, 0x944);
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x/ 0x%x",
+		   "0x92c[1:0]/ 0x930[7:0]/0x944[1:0]",
+		   u32tmp[0] & 0x3, u32tmp[1] & 0xff, u32tmp[2] & 0x3);
+	CL_PRINTF(cli_buf);
+
+	u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x39);
+	u8tmp[1] = btcoexist->btc_read_1byte(btcoexist, 0x40);
+	u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x4c);
+	u8tmp[2] = btcoexist->btc_read_1byte(btcoexist, 0x64);
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+		   "\r\n %-35s = 0x%x/ 0x%x/ 0x%x/ 0x%x",
+		   "0x38[11]/0x40/0x4c[24:23]/0x64[0]",
+		   ((u8tmp[0] & 0x8) >> 3), u8tmp[1],
+		   ((u32tmp[0] & 0x01800000) >> 23), u8tmp[2] & 0x1);
+	CL_PRINTF(cli_buf);
+
+	u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x550);
+	u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x522);
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x",
+		   "0x550(bcn ctrl)/0x522",
+		   u32tmp[0], u8tmp[0]);
+	CL_PRINTF(cli_buf);
+
+	u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0xc50);
+	u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x49c);
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x",
+		   "0xc50(dig)/0x49c(null-drop)",
+		   u32tmp[0] & 0xff, u8tmp[0]);
+	CL_PRINTF(cli_buf);
+
+	fa_ofdm = btcoexist->btc_phydm_query_PHY_counter(btcoexist,
+			PHYDM_INFO_FA_OFDM);
+	fa_cck = btcoexist->btc_phydm_query_PHY_counter(btcoexist,
+			PHYDM_INFO_FA_CCK);
+	cca_ofdm = btcoexist->btc_phydm_query_PHY_counter(btcoexist,
+			PHYDM_INFO_CCA_OFDM);
+	cca_cck = btcoexist->btc_phydm_query_PHY_counter(btcoexist,
+			PHYDM_INFO_CCA_CCK);
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+		   "\r\n %-35s = 0x%x/ 0x%x/ 0x%x/ 0x%x",
+		   "CCK-CCA/CCK-FA/OFDM-CCA/OFDM-FA",
+		   cca_cck, fa_cck, cca_ofdm, fa_ofdm);
+	CL_PRINTF(cli_buf);
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d/ %d",
+		   "CRC_OK CCK/11g/11n/11n-agg",
+		   coex_sta->crc_ok_cck, coex_sta->crc_ok_11g,
+		   coex_sta->crc_ok_11n, coex_sta->crc_ok_11n_vht);
+	CL_PRINTF(cli_buf);
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d/ %d",
+		   "CRC_Err CCK/11g/11n/11n-agg",
+		   coex_sta->crc_err_cck, coex_sta->crc_err_11g,
+		   coex_sta->crc_err_11n, coex_sta->crc_err_11n_vht);
+	CL_PRINTF(cli_buf);
+
+	u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x6c0);
+	u32tmp[1] = btcoexist->btc_read_4byte(btcoexist, 0x6c4);
+	u32tmp[2] = btcoexist->btc_read_4byte(btcoexist, 0x6c8);
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x/ 0x%x",
+		   "0x6c0/0x6c4/0x6c8(coexTable)",
+		   u32tmp[0], u32tmp[1], u32tmp[2]);
+	CL_PRINTF(cli_buf);
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d",
+		   "0x770(high-pri rx/tx)",
+		   coex_sta->high_priority_rx, coex_sta->high_priority_tx);
+	CL_PRINTF(cli_buf);
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d",
+		   "0x774(low-pri rx/tx)",
+		   coex_sta->low_priority_rx, coex_sta->low_priority_tx);
+	CL_PRINTF(cli_buf);
+#if (BT_AUTO_REPORT_ONLY_8723B_1ANT == 1)
+	/* halbtc8723b1ant_monitor_bt_ctr(btcoexist); */
+#endif
+	btcoexist->btc_disp_dbg_msg(btcoexist, BTC_DBG_DISP_COEX_STATISTICS);
+}
+
+
+void ex_halbtc8723b1ant_ips_notify(IN struct btc_coexist *btcoexist, IN u8 type)
+{
+	if (btcoexist->manual_control ||	btcoexist->stop_coex_dm)
+		return;
+
+	if (BTC_IPS_ENTER == type) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], IPS ENTER notify\n");
+		BTC_TRACE(trace_buf);
+		coex_sta->under_ips = true;
+
+		halbtc8723b1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 0);
+		halbtc8723b1ant_set_ant_path(btcoexist, BTC_ANT_PATH_BT,
+					     FORCE_EXEC, false, true);
+		halbtc8723b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0);
+	} else if (BTC_IPS_LEAVE == type) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], IPS LEAVE notify\n");
+		BTC_TRACE(trace_buf);
+
+		halbtc8723b1ant_init_hw_config(btcoexist, false, false);
+		halbtc8723b1ant_init_coex_dm(btcoexist);
+		halbtc8723b1ant_query_bt_info(btcoexist);
+
+		coex_sta->under_ips = false;
+	}
+}
+
+void ex_halbtc8723b1ant_lps_notify(IN struct btc_coexist *btcoexist, IN u8 type)
+{
+	if (btcoexist->manual_control || btcoexist->stop_coex_dm)
+		return;
+
+	if (BTC_LPS_ENABLE == type) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], LPS ENABLE notify\n");
+		BTC_TRACE(trace_buf);
+		coex_sta->under_lps = true;
+	} else if (BTC_LPS_DISABLE == type) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], LPS DISABLE notify\n");
+		BTC_TRACE(trace_buf);
+		coex_sta->under_lps = false;
+	}
+}
+
+void ex_halbtc8723b1ant_scan_notify(IN struct btc_coexist *btcoexist,
+				    IN u8 type)
+{
+	boolean wifi_connected = false, bt_hs_on = false;
+	u32	wifi_link_status = 0;
+	u32	num_of_wifi_link = 0;
+	boolean	bt_ctrl_agg_buf_size = false;
+	u8	agg_buf_size = 5;
+
+	u8 u8tmpa, u8tmpb;
+	u32 u32tmp;
+
+	if (btcoexist->manual_control ||
+	    btcoexist->stop_coex_dm)
+		return;
+
+	if (BTC_SCAN_START == type) {
+		coex_sta->wifi_is_high_pri_task = true;
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], SCAN START notify\n");
+		BTC_TRACE(trace_buf);
+		psd_scan->ant_det_is_ant_det_available = true;
+		halbtc8723b1ant_ps_tdma(btcoexist, FORCE_EXEC, false,
+			8);  /* Force antenna setup for no scan result issue */
+		halbtc8723b1ant_set_ant_path(btcoexist, BTC_ANT_PATH_PTA,
+					     FORCE_EXEC, false, false);
+		u32tmp = btcoexist->btc_read_4byte(btcoexist, 0x948);
+		u8tmpa = btcoexist->btc_read_1byte(btcoexist, 0x765);
+		u8tmpb = btcoexist->btc_read_1byte(btcoexist, 0x67);
+
+
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], 0x948=0x%x, 0x765=0x%x, 0x67=0x%x\n",
+			    u32tmp,  u8tmpa, u8tmpb);
+		BTC_TRACE(trace_buf);
+	} else {
+		coex_sta->wifi_is_high_pri_task = false;
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], SCAN FINISH notify\n");
+		BTC_TRACE(trace_buf);
+
+		btcoexist->btc_get(btcoexist, BTC_GET_U1_AP_NUM,
+				   &coex_sta->scan_ap_num);
+	}
+
+	if (coex_sta->bt_disabled)
+		return;
+
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on);
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED,
+			   &wifi_connected);
+
+	halbtc8723b1ant_query_bt_info(btcoexist);
+
+	btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_LINK_STATUS,
+			   &wifi_link_status);
+	num_of_wifi_link = wifi_link_status >> 16;
+	if (num_of_wifi_link >= 2) {
+		halbtc8723b1ant_limited_tx(btcoexist, NORMAL_EXEC, 0, 0, 0, 0);
+		halbtc8723b1ant_limited_rx(btcoexist, NORMAL_EXEC, false,
+					   bt_ctrl_agg_buf_size, agg_buf_size);
+		halbtc8723b1ant_action_wifi_multi_port(btcoexist);
+		return;
+	}
+
+	if (coex_sta->c2h_bt_inquiry_page) {
+		halbtc8723b1ant_action_bt_inquiry(btcoexist);
+		return;
+	} else if (bt_hs_on) {
+		halbtc8723b1ant_action_hs(btcoexist);
+		return;
+	}
+
+	if (BTC_SCAN_START == type) {
+		if (!wifi_connected)	/* non-connected scan */
+			halbtc8723b1ant_action_wifi_not_connected_scan(
+				btcoexist);
+		else	/* wifi is connected */
+			halbtc8723b1ant_action_wifi_connected_scan(btcoexist);
+	} else if (BTC_SCAN_FINISH == type) {
+		if (!wifi_connected)	/* non-connected scan */
+			halbtc8723b1ant_action_wifi_not_connected(btcoexist);
+		else
+			halbtc8723b1ant_action_wifi_connected(btcoexist);
+	}
+}
+
+void ex_halbtc8723b1ant_set_antenna_notify(IN struct btc_coexist *btcoexist,
+		IN u8 type)
+{
+	struct  btc_board_info	*board_info = &btcoexist->board_info;
+
+	if (btcoexist->manual_control || btcoexist->stop_coex_dm)
+		return;
+
+	if (type == 2) /* two antenna */
+		halbtc8723b1ant_mechanism_switch(btcoexist, true);
+	else /* one antenna */
+		halbtc8723b1ant_mechanism_switch(btcoexist, false);
+}
+
+void ex_halbtc8723b1ant_connect_notify(IN struct btc_coexist *btcoexist,
+				       IN u8 type)
+{
+	boolean	wifi_connected = false, bt_hs_on = false;
+	u32	wifi_link_status = 0;
+	u32	num_of_wifi_link = 0;
+	boolean	bt_ctrl_agg_buf_size = false;
+	u8	agg_buf_size = 5;
+
+	if (btcoexist->manual_control ||
+	    btcoexist->stop_coex_dm)
+		return;
+
+	if (BTC_ASSOCIATE_START == type) {
+		coex_sta->wifi_is_high_pri_task = true;
+		psd_scan->ant_det_is_ant_det_available = true;
+		halbtc8723b1ant_ps_tdma(btcoexist, FORCE_EXEC, false,
+			8);  /* Force antenna setup for no scan result issue */
+		halbtc8723b1ant_set_ant_path(btcoexist, BTC_ANT_PATH_PTA,
+					     FORCE_EXEC, false, false);
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], CONNECT START notify\n");
+		BTC_TRACE(trace_buf);
+		coex_dm->arp_cnt = 0;
+	} else {
+		coex_sta->wifi_is_high_pri_task = false;
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], CONNECT FINISH notify\n");
+		BTC_TRACE(trace_buf);
+		/* coex_dm->arp_cnt = 0; */
+	}
+
+	btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_LINK_STATUS,
+			   &wifi_link_status);
+	num_of_wifi_link = wifi_link_status >> 16;
+	if (num_of_wifi_link >= 2) {
+		halbtc8723b1ant_limited_tx(btcoexist, NORMAL_EXEC, 0, 0, 0, 0);
+		halbtc8723b1ant_limited_rx(btcoexist, NORMAL_EXEC, false,
+					   bt_ctrl_agg_buf_size, agg_buf_size);
+		halbtc8723b1ant_action_wifi_multi_port(btcoexist);
+		return;
+	}
+
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on);
+	if (coex_sta->c2h_bt_inquiry_page) {
+		halbtc8723b1ant_action_bt_inquiry(btcoexist);
+		return;
+	} else if (bt_hs_on) {
+		halbtc8723b1ant_action_hs(btcoexist);
+		return;
+	}
+
+	if (BTC_ASSOCIATE_START == type)
+		halbtc8723b1ant_action_wifi_not_connected_asso_auth(btcoexist);
+	else if (BTC_ASSOCIATE_FINISH == type) {
+		btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED,
+				   &wifi_connected);
+		if (!wifi_connected) /* non-connected scan */
+			halbtc8723b1ant_action_wifi_not_connected(btcoexist);
+		else
+			halbtc8723b1ant_action_wifi_connected(btcoexist);
+	}
+}
+
+void ex_halbtc8723b1ant_media_status_notify(IN struct btc_coexist *btcoexist,
+		IN u8 type)
+{
+	u8			h2c_parameter[3] = {0};
+	u32			wifi_bw;
+	u8			wifi_central_chnl;
+	boolean			wifi_under_b_mode = false;
+
+	if (btcoexist->manual_control ||
+	    btcoexist->stop_coex_dm)
+		return;
+
+	if (BTC_MEDIA_CONNECT == type) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], MEDIA connect notify\n");
+		BTC_TRACE(trace_buf);
+		halbtc8723b1ant_ps_tdma(btcoexist, FORCE_EXEC, false,
+			8);  /* Force antenna setup for no scan result issue */
+		halbtc8723b1ant_set_ant_path(btcoexist, BTC_ANT_PATH_PTA,
+					     FORCE_EXEC, false, false);
+		psd_scan->ant_det_is_ant_det_available = true;
+		btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_B_MODE,
+				   &wifi_under_b_mode);
+
+		/* Set CCK Tx/Rx high Pri except 11b mode */
+		if (wifi_under_b_mode) {
+			btcoexist->btc_write_1byte(btcoexist, 0x6cd,
+						   0x00); /* CCK Tx */
+			btcoexist->btc_write_1byte(btcoexist, 0x6cf,
+						   0x00); /* CCK Rx */
+		} else {
+			btcoexist->btc_write_1byte(btcoexist, 0x6cd,
+						   0x00); /* CCK Tx */
+			btcoexist->btc_write_1byte(btcoexist, 0x6cf,
+						   0x10); /* CCK Rx */
+		}
+
+		coex_dm->backup_arfr_cnt1 = btcoexist->btc_read_4byte(btcoexist,
+					    0x430);
+		coex_dm->backup_arfr_cnt2 = btcoexist->btc_read_4byte(btcoexist,
+					    0x434);
+		coex_dm->backup_retry_limit = btcoexist->btc_read_2byte(
+						      btcoexist, 0x42a);
+		coex_dm->backup_ampdu_max_time = btcoexist->btc_read_1byte(
+				btcoexist, 0x456);
+	} else {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], MEDIA disconnect notify\n");
+		BTC_TRACE(trace_buf);
+		coex_dm->arp_cnt = 0;
+
+		btcoexist->btc_write_1byte(btcoexist, 0x6cd, 0x0); /* CCK Tx */
+		btcoexist->btc_write_1byte(btcoexist, 0x6cf, 0x0); /* CCK Rx */
+
+		coex_sta->cck_ever_lock = false;
+	}
+
+	/* only 2.4G we need to inform bt the chnl mask */
+	btcoexist->btc_get(btcoexist, BTC_GET_U1_WIFI_CENTRAL_CHNL,
+			   &wifi_central_chnl);
+	if ((BTC_MEDIA_CONNECT == type) &&
+	    (wifi_central_chnl <= 14)) {
+		/* h2c_parameter[0] = 0x1; */
+		h2c_parameter[0] = 0x0;
+		h2c_parameter[1] = wifi_central_chnl;
+		btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw);
+		if (BTC_WIFI_BW_HT40 == wifi_bw)
+			h2c_parameter[2] = 0x30;
+		else
+			h2c_parameter[2] = 0x20;
+	}
+
+	coex_dm->wifi_chnl_info[0] = h2c_parameter[0];
+	coex_dm->wifi_chnl_info[1] = h2c_parameter[1];
+	coex_dm->wifi_chnl_info[2] = h2c_parameter[2];
+
+	btcoexist->btc_fill_h2c(btcoexist, 0x66, 3, h2c_parameter);
+}
+
+void ex_halbtc8723b1ant_specific_packet_notify(IN struct btc_coexist *btcoexist,
+		IN u8 type)
+{
+	boolean	bt_hs_on = false;
+	u32	wifi_link_status = 0;
+	u32	num_of_wifi_link = 0;
+	boolean	bt_ctrl_agg_buf_size = false, under_4way = false;
+	u8	agg_buf_size = 5;
+
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_4_WAY_PROGRESS,
+			   &under_4way);
+
+	if (btcoexist->manual_control ||
+	    btcoexist->stop_coex_dm)
+		return;
+
+	if (BTC_PACKET_DHCP == type ||
+	    BTC_PACKET_EAPOL == type ||
+	    BTC_PACKET_ARP == type) {
+		if (BTC_PACKET_ARP == type) {
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				    "[BTCoex], specific Packet ARP notify\n");
+			BTC_TRACE(trace_buf);
+
+			coex_dm->arp_cnt++;
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				    "[BTCoex], ARP Packet Count = %d\n",
+				    coex_dm->arp_cnt);
+			BTC_TRACE(trace_buf);
+
+			if ((coex_dm->arp_cnt >= 10) &&
+			    (!under_4way))  /* if APR PKT > 10 after connect, do not go to ActionWifiConnectedSpecificPacket(btcoexist) */
+				coex_sta->wifi_is_high_pri_task = false;
+			else
+				coex_sta->wifi_is_high_pri_task = true;
+		} else {
+			coex_sta->wifi_is_high_pri_task = true;
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				"[BTCoex], specific Packet DHCP or EAPOL notify\n");
+			BTC_TRACE(trace_buf);
+		}
+	} else {
+		coex_sta->wifi_is_high_pri_task = false;
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			"[BTCoex], specific Packet [Type = %d] notify\n", type);
+		BTC_TRACE(trace_buf);
+	}
+
+	coex_sta->specific_pkt_period_cnt = 0;
+
+	btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_LINK_STATUS,
+			   &wifi_link_status);
+	num_of_wifi_link = wifi_link_status >> 16;
+	if (num_of_wifi_link >= 2) {
+		halbtc8723b1ant_limited_tx(btcoexist, NORMAL_EXEC, 0, 0, 0, 0);
+		halbtc8723b1ant_limited_rx(btcoexist, NORMAL_EXEC, false,
+					   bt_ctrl_agg_buf_size, agg_buf_size);
+		halbtc8723b1ant_action_wifi_multi_port(btcoexist);
+		return;
+	}
+
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on);
+	if (coex_sta->c2h_bt_inquiry_page) {
+		halbtc8723b1ant_action_bt_inquiry(btcoexist);
+		return;
+	} else if (bt_hs_on) {
+		halbtc8723b1ant_action_hs(btcoexist);
+		return;
+	}
+
+	if (BTC_PACKET_DHCP == type ||
+	    BTC_PACKET_EAPOL == type ||
+	    ((BTC_PACKET_ARP == type) && (coex_sta->wifi_is_high_pri_task)))
+		halbtc8723b1ant_action_wifi_connected_specific_packet(
+			btcoexist);
+}
+
+/* Donot remove optimize off flag, otherwise antenna detection would trigger BT collapsed */
+#ifdef PLATFORM_WINDOWS
+#pragma optimize("", off)
+#endif
+void ex_halbtc8723b1ant_bt_info_notify(IN struct btc_coexist *btcoexist,
+				       IN u8 *tmp_buf, IN u8 length)
+{
+	u8				bt_info = 0;
+	u8				i, rsp_source = 0;
+	boolean				wifi_connected = false;
+	boolean				bt_busy = false;
+	struct  btc_board_info	*board_info = &btcoexist->board_info;
+
+	coex_sta->c2h_bt_info_req_sent = false;
+
+	rsp_source = tmp_buf[0] & 0xf;
+	if (rsp_source >= BT_INFO_SRC_8723B_1ANT_MAX)
+		rsp_source = BT_INFO_SRC_8723B_1ANT_WIFI_FW;
+	coex_sta->bt_info_c2h_cnt[rsp_source]++;
+
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+		    "[BTCoex], Bt info[%d], length=%d, hex data=[", rsp_source,
+		    length);
+	BTC_TRACE(trace_buf);
+	for (i = 0; i < length; i++) {
+		coex_sta->bt_info_c2h[rsp_source][i] = tmp_buf[i];
+		if (i == 1)
+			bt_info = tmp_buf[i];
+		if (i == length - 1) {
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "0x%02x]\n",
+				    tmp_buf[i]);
+			BTC_TRACE(trace_buf);
+		} else {
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "0x%02x, ",
+				    tmp_buf[i]);
+			BTC_TRACE(trace_buf);
+		}
+	}
+
+	/* if 0xff, it means BT is under WHCK test */
+	if (bt_info == 0xff)
+		coex_sta->bt_whck_test = true;
+	else
+		coex_sta->bt_whck_test = false;
+
+	if (BT_INFO_SRC_8723B_1ANT_WIFI_FW != rsp_source) {
+		coex_sta->bt_retry_cnt =	/* [3:0] */
+			coex_sta->bt_info_c2h[rsp_source][2] & 0xf;
+
+		if (coex_sta->bt_retry_cnt >= 1)
+			coex_sta->pop_event_cnt++;
+
+		if (coex_sta->bt_info_c2h[rsp_source][2] & 0x20)
+			coex_sta->c2h_bt_remote_name_req = true;
+		else
+			coex_sta->c2h_bt_remote_name_req = false;
+
+		coex_sta->bt_rssi =
+			coex_sta->bt_info_c2h[rsp_source][3] * 2 - 90;
+		/* coex_sta->bt_info_c2h[rsp_source][3]*2+10; */
+
+		coex_sta->bt_info_ext =
+			coex_sta->bt_info_c2h[rsp_source][4];
+
+		if (coex_sta->bt_info_c2h[rsp_source][1] == 0x49) {
+			coex_sta->a2dp_bit_pool =
+				coex_sta->bt_info_c2h[rsp_source][6];
+		} else
+			coex_sta->a2dp_bit_pool = 0;
+
+		coex_sta->bt_tx_rx_mask = (coex_sta->bt_info_c2h[rsp_source][2]
+					   & 0x40);
+		btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_TX_RX_MASK,
+				   &coex_sta->bt_tx_rx_mask);
+
+		if (btcoexist->stop_coex_dm) {
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				"############# [BTCoex], BT info Notify() return because stop_coex_dm\n");
+			BTC_TRACE(trace_buf);
+
+			return;
+		}
+
+
+#if BT_8723B_1ANT_ANTDET_ENABLE
+#if BT_8723B_1ANT_ANTDET_COEXMECHANISMSWITCH_ENABLE
+		if ((board_info->btdm_ant_det_finish) &&
+		    (board_info->btdm_ant_num_by_ant_det == 2)) {
+			if (coex_sta->bt_tx_rx_mask) {
+
+				/* BT TRx mask off */
+				btcoexist->btc_set_bt_trx_mask(btcoexist, 0);
+
+				BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+					"############# [BTCoex], BT TRx Mask off for BT Info Notify\n");
+				BTC_TRACE(trace_buf);
+#if 0
+				/* BT into is responded by BT FW and BT RF REG 0x3C != 0x15 => Need to switch BT TRx Mask */
+				BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+					"[BTCoex], Switch BT TRx Mask since BT RF REG 0x3C != 0x1\n");
+				BTC_TRACE(trace_buf);
+
+				/* BT TRx Mask un-lock 0x2c[0], 0x30[0] = 1 */
+				btcoexist->btc_set_bt_reg(btcoexist,
+						  BTC_BT_REG_RF, 0x2c, 0x7c45);
+				btcoexist->btc_set_bt_reg(btcoexist,
+						  BTC_BT_REG_RF, 0x30, 0x7c45);
+
+				btcoexist->btc_set_bt_reg(btcoexist,
+						  BTC_BT_REG_RF, 0x3c, 0x1);
+#endif
+			}
+		} else
+#endif
+#endif
+
+		{
+			if (!coex_sta->bt_tx_rx_mask) {
+
+				/* BT TRx mask on */
+				btcoexist->btc_set_bt_trx_mask(btcoexist, 1);
+
+				BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+					"############# [BTCoex], BT TRx Mask on for  BT Info Notify\n");
+				BTC_TRACE(trace_buf);
+#if 0
+				/* BT into is responded by BT FW and BT RF REG 0x3C != 0x15 => Need to switch BT TRx Mask */
+				BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+					"[BTCoex], Switch BT TRx Mask since BT RF REG 0x3C != 0x15\n");
+				BTC_TRACE(trace_buf);
+				btcoexist->btc_set_bt_reg(btcoexist,
+							  BTC_BT_REG_RF,
+							  0x3c, 0x15);
+
+				/* BT TRx Mask lock 0x2c[0], 0x30[0] = 0 */
+				btcoexist->btc_set_bt_reg(btcoexist,
+							  BTC_BT_REG_RF,
+							  0x2c, 0x7c44);
+				btcoexist->btc_set_bt_reg(btcoexist,
+							  BTC_BT_REG_RF,
+							  0x30, 0x7c44);
+#endif
+			}
+		}
+
+		/* Here we need to resend some wifi info to BT */
+		/* because bt is reset and loss of the info. */
+		if (coex_sta->bt_info_ext & BIT(1)) {
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				"[BTCoex], BT ext info bit1 check, send wifi BW&Chnl to BT!!\n");
+			BTC_TRACE(trace_buf);
+			btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED,
+					   &wifi_connected);
+			if (wifi_connected)
+				ex_halbtc8723b1ant_media_status_notify(
+					btcoexist, BTC_MEDIA_CONNECT);
+			else
+				ex_halbtc8723b1ant_media_status_notify(
+					btcoexist, BTC_MEDIA_DISCONNECT);
+		}
+
+		if (coex_sta->bt_info_ext & BIT(3)) {
+			if (!btcoexist->manual_control &&
+			    !btcoexist->stop_coex_dm) {
+				BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+					"[BTCoex], BT ext info bit3 check, set BT NOT to ignore Wlan active!!\n");
+				BTC_TRACE(trace_buf);
+				halbtc8723b1ant_ignore_wlan_act(btcoexist,
+							FORCE_EXEC, false);
+			}
+		} else {
+			/* BT already NOT ignore Wlan active, do nothing here. */
+		}
+#if (BT_AUTO_REPORT_ONLY_8723B_1ANT == 0)
+		if ((coex_sta->bt_info_ext & BIT(4))) {
+			/* BT auto report already enabled, do nothing */
+		} else
+			halbtc8723b1ant_bt_auto_report(btcoexist, FORCE_EXEC,
+						       true);
+#endif
+	}
+
+	/* check BIT2 first ==> check if bt is under inquiry or page scan */
+	if (bt_info & BT_INFO_8723B_1ANT_B_INQ_PAGE)
+		coex_sta->c2h_bt_inquiry_page = true;
+	else
+		coex_sta->c2h_bt_inquiry_page = false;
+
+	coex_sta->num_of_profile = 0;
+
+	/* set link exist status */
+	if (!(bt_info & BT_INFO_8723B_1ANT_B_CONNECTION)) {
+		coex_sta->bt_link_exist = false;
+		coex_sta->pan_exist = false;
+		coex_sta->a2dp_exist = false;
+		coex_sta->hid_exist = false;
+		coex_sta->sco_exist = false;
+
+		coex_sta->bt_hi_pri_link_exist = false;
+	} else {	/* connection exists */
+		coex_sta->bt_link_exist = true;
+		if (bt_info & BT_INFO_8723B_1ANT_B_FTP) {
+			coex_sta->pan_exist = true;
+			coex_sta->num_of_profile++;
+		} else
+			coex_sta->pan_exist = false;
+		if (bt_info & BT_INFO_8723B_1ANT_B_A2DP) {
+			coex_sta->a2dp_exist = true;
+			coex_sta->num_of_profile++;
+		} else
+			coex_sta->a2dp_exist = false;
+		if (bt_info & BT_INFO_8723B_1ANT_B_HID) {
+			coex_sta->hid_exist = true;
+			coex_sta->num_of_profile++;
+		} else
+			coex_sta->hid_exist = false;
+		if (bt_info & BT_INFO_8723B_1ANT_B_SCO_ESCO) {
+			coex_sta->sco_exist = true;
+			coex_sta->num_of_profile++;
+		} else
+			coex_sta->sco_exist = false;
+
+		if ((coex_sta->hid_exist == false) &&
+		    (coex_sta->c2h_bt_inquiry_page == false) &&
+		    (coex_sta->sco_exist == false)) {
+			if (coex_sta->high_priority_tx  +
+			    coex_sta->high_priority_rx >= 160) {
+				coex_sta->hid_exist = true;
+				coex_sta->wrong_profile_notification++;
+				coex_sta->num_of_profile++;
+				bt_info = bt_info | 0x28;
+			}
+		}
+
+		/* Add Hi-Pri Tx/Rx counter to avoid false detection */
+		if (((coex_sta->hid_exist) || (coex_sta->sco_exist)) &&
+		    (coex_sta->high_priority_tx  +
+		     coex_sta->high_priority_rx >= 160)
+		    && (!coex_sta->c2h_bt_inquiry_page))
+			coex_sta->bt_hi_pri_link_exist = true;
+
+		if ((bt_info & BT_INFO_8723B_1ANT_B_ACL_BUSY) &&
+		    (coex_sta->num_of_profile == 0)) {
+			if (coex_sta->low_priority_tx  +
+			    coex_sta->low_priority_rx >= 160) {
+				coex_sta->pan_exist = true;
+				coex_sta->num_of_profile++;
+				coex_sta->wrong_profile_notification++;
+				bt_info = bt_info | 0x88;
+			}
+		}
+	}
+
+	halbtc8723b1ant_update_bt_link_info(btcoexist);
+
+	bt_info = bt_info &
+		0x1f;  /* mask profile bit for connect-ilde identification ( for CSR case: A2DP idle --> 0x41) */
+
+	if (!(bt_info & BT_INFO_8723B_1ANT_B_CONNECTION))
+		coex_dm->bt_status = BT_8723B_1ANT_BT_STATUS_NON_CONNECTED_IDLE;
+	else if (bt_info ==
+		BT_INFO_8723B_1ANT_B_CONNECTION)	/* connection exists but no busy */
+		coex_dm->bt_status = BT_8723B_1ANT_BT_STATUS_CONNECTED_IDLE;
+	else if ((bt_info & BT_INFO_8723B_1ANT_B_SCO_ESCO) ||
+		 (bt_info & BT_INFO_8723B_1ANT_B_SCO_BUSY))
+		coex_dm->bt_status = BT_8723B_1ANT_BT_STATUS_SCO_BUSY;
+	else if (bt_info & BT_INFO_8723B_1ANT_B_ACL_BUSY) {
+		if (BT_8723B_1ANT_BT_STATUS_ACL_BUSY != coex_dm->bt_status)
+			coex_dm->auto_tdma_adjust = false;
+		coex_dm->bt_status = BT_8723B_1ANT_BT_STATUS_ACL_BUSY;
+	} else
+		coex_dm->bt_status = BT_8723B_1ANT_BT_STATUS_MAX;
+
+	if ((BT_8723B_1ANT_BT_STATUS_ACL_BUSY == coex_dm->bt_status) ||
+	    (BT_8723B_1ANT_BT_STATUS_SCO_BUSY == coex_dm->bt_status) ||
+	    (BT_8723B_1ANT_BT_STATUS_ACL_SCO_BUSY == coex_dm->bt_status))
+		bt_busy = true;
+	else
+		bt_busy = false;
+	btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_TRAFFIC_BUSY, &bt_busy);
+
+	halbtc8723b1ant_run_coexist_mechanism(btcoexist);
+}
+
+void ex_halbtc8723b1ant_rf_status_notify(IN struct btc_coexist *btcoexist,
+		IN u8 type)
+{
+	u32	u32tmp;
+	u8	u8tmpa, u8tmpb, u8tmpc;
+
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], RF Status notify\n");
+	BTC_TRACE(trace_buf);
+
+	if (BTC_RF_ON == type) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], RF is turned ON!!\n");
+		BTC_TRACE(trace_buf);
+		btcoexist->stop_coex_dm = false;
+	} else if (BTC_RF_OFF == type) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], RF is turned OFF!!\n");
+		BTC_TRACE(trace_buf);
+
+		halbtc8723b1ant_ps_tdma(btcoexist, FORCE_EXEC, false, 0);
+		halbtc8723b1ant_set_ant_path(btcoexist, BTC_ANT_PATH_BT,
+					     FORCE_EXEC, false, true);
+
+		halbtc8723b1ant_ignore_wlan_act(btcoexist, FORCE_EXEC, true);
+		btcoexist->stop_coex_dm = true;
+
+		u32tmp = btcoexist->btc_read_4byte(btcoexist, 0x948);
+		u8tmpa = btcoexist->btc_read_1byte(btcoexist, 0x765);
+		u8tmpb = btcoexist->btc_read_1byte(btcoexist, 0x67);
+		u8tmpc = btcoexist->btc_read_1byte(btcoexist, 0x76e);
+
+
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			"############# [BTCoex], 0x948=0x%x, 0x765=0x%x, 0x67=0x%x, 0x76e=0x%x\n",
+			    u32tmp,  u8tmpa, u8tmpb, u8tmpc);
+		BTC_TRACE(trace_buf);
+
+	}
+}
+
+void ex_halbtc8723b1ant_halt_notify(IN struct btc_coexist *btcoexist)
+{
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], Halt notify\n");
+	BTC_TRACE(trace_buf);
+
+	halbtc8723b1ant_ps_tdma(btcoexist, FORCE_EXEC, false, 0);
+	halbtc8723b1ant_set_ant_path(btcoexist, BTC_ANT_PATH_BT, FORCE_EXEC,
+				     false, true);
+
+	halbtc8723b1ant_ignore_wlan_act(btcoexist, FORCE_EXEC, true);
+
+	ex_halbtc8723b1ant_media_status_notify(btcoexist, BTC_MEDIA_DISCONNECT);
+
+	btcoexist->stop_coex_dm = true;
+}
+
+void ex_halbtc8723b1ant_pnp_notify(IN struct btc_coexist *btcoexist,
+				   IN u8 pnp_state)
+{
+	if (BTC_WIFI_PNP_SLEEP == pnp_state) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], Pnp notify to SLEEP\n");
+		BTC_TRACE(trace_buf);
+
+		halbtc8723b1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 0);
+		halbtc8723b1ant_set_ant_path(btcoexist, BTC_ANT_PATH_BT,
+					     FORCE_EXEC, false, true);
+		halbtc8723b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 2);
+
+		/* Sinda 20150819, workaround for driver skip leave IPS/LPS to speed up sleep time. */
+		/* Driver do not leave IPS/LPS when driver is going to sleep, so BTCoexistence think wifi is still under IPS/LPS */
+		/* BT should clear UnderIPS/UnderLPS state to avoid mismatch state after wakeup. */
+		coex_sta->under_ips = false;
+		coex_sta->under_lps = false;
+		btcoexist->stop_coex_dm = true;
+	} else if (BTC_WIFI_PNP_WAKE_UP == pnp_state) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], Pnp notify to WAKE UP\n");
+		BTC_TRACE(trace_buf);
+		btcoexist->stop_coex_dm = false;
+		halbtc8723b1ant_init_hw_config(btcoexist, false, false);
+		halbtc8723b1ant_init_coex_dm(btcoexist);
+		halbtc8723b1ant_query_bt_info(btcoexist);
+	}
+}
+
+void ex_halbtc8723b1ant_coex_dm_reset(IN struct btc_coexist *btcoexist)
+{
+
+	halbtc8723b1ant_init_hw_config(btcoexist, false, false);
+	/* btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1, 0xfffff, 0x0); */
+	/* btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x2, 0xfffff, 0x0); */
+	halbtc8723b1ant_init_coex_dm(btcoexist);
+}
+
+void ex_halbtc8723b1ant_periodical(IN struct btc_coexist *btcoexist)
+{
+	u32 bt_patch_ver;
+
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+		"[BTCoex], ==========================Periodical===========================\n");
+	BTC_TRACE(trace_buf);
+
+#if (BT_AUTO_REPORT_ONLY_8723B_1ANT == 0)
+	halbtc8723b1ant_query_bt_info(btcoexist);
+#endif
+	halbtc8723b1ant_monitor_bt_ctr(btcoexist);
+	halbtc8723b1ant_monitor_wifi_ctr(btcoexist);
+
+	halbtc8723b1ant_monitor_bt_enable_disable(btcoexist);
+
+
+	if (halbtc8723b1ant_is_wifi_status_changed(btcoexist) ||
+	    coex_dm->auto_tdma_adjust ||
+	    btcoexist->bt_info.bt_enable_disable_change)
+		halbtc8723b1ant_run_coexist_mechanism(btcoexist);
+
+	if (((coex_sta->bt_coex_supported_version == 0) ||
+	     (coex_sta->bt_coex_supported_version == 0xffff)) && (!coex_sta->bt_disabled))
+		btcoexist->btc_get(btcoexist, BTC_GET_U4_SUPPORTED_VERSION, &coex_sta->bt_coex_supported_version);
+
+	btcoexist->btc_get(btcoexist, BTC_GET_U4_BT_PATCH_VER, &bt_patch_ver);
+	btcoexist->bt_info.bt_get_fw_ver = bt_patch_ver;
+	coex_sta->specific_pkt_period_cnt++;
+
+	/* sample to set bt to execute Ant detection */
+	/* btcoexist->btc_set_bt_ant_detection(btcoexist, 20, 14);
+	*
+	if (psd_scan->is_ant_det_enable)
+	{
+		 if (psd_scan->psd_gen_count > psd_scan->realseconds)
+			psd_scan->psd_gen_count = 0;
+
+		halbtc8723b1ant_antenna_detection(btcoexist, psd_scan->realcent_freq,  psd_scan->realoffset, psd_scan->realspan,  psd_scan->realseconds);
+		psd_scan->psd_gen_total_count +=2;
+		psd_scan->psd_gen_count += 2;
+	}
+	*/
+}
+
+/* Donot remove optimize off flag, otherwise antenna detection would trigger BT collapsed */
+#ifdef PLATFORM_WINDOWS
+#pragma optimize("", off)
+#endif
+void ex_halbtc8723b1ant_antenna_detection(IN struct btc_coexist *btcoexist,
+		IN u32 cent_freq, IN u32 offset, IN u32 span, IN u32 seconds)
+{
+#if BT_8723B_1ANT_ANTDET_ENABLE
+	static u32 ant_det_count = 0, ant_det_fail_count = 0;
+	struct  btc_board_info	*board_info = &btcoexist->board_info;
+	/*boolean scan, roam;*/
+
+	if (seconds == 0) {
+		psd_scan->ant_det_try_count	= 0;
+		psd_scan->ant_det_fail_count	= 0;
+		ant_det_count = 0;
+		ant_det_fail_count = 0;
+		board_info->btdm_ant_det_finish = false;
+		board_info->btdm_ant_num_by_ant_det = 1;
+		return;
+	}
+
+	if (!board_info->btdm_ant_det_finish) {
+		psd_scan->ant_det_inteval_count =
+			psd_scan->ant_det_inteval_count + 2;
+
+		if (psd_scan->ant_det_inteval_count >=
+		    BT_8723B_1ANT_ANTDET_RETRY_INTERVAL) {
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				"xxxxxxxxxxxxxxxx AntennaDetect(), Antenna Det Timer is up, Try Detect!!\n");
+			BTC_TRACE(trace_buf);
+			halbtc8723b1ant_psd_antenna_detection_check(btcoexist);
+
+			if (board_info->btdm_ant_det_finish) {
+				BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+					"xxxxxxxxxxxxxxxx AntennaDetect(), Antenna Det Success!!\n");
+				BTC_TRACE(trace_buf);
+
+
+#if 1
+				if (board_info->btdm_ant_num_by_ant_det == 2)
+					halbtc8723b1ant_mechanism_switch(
+						btcoexist, true);
+				else
+					halbtc8723b1ant_mechanism_switch(
+						btcoexist, false);
+#endif
+
+				board_info->btdm_ant_det_complete_fail = false;
+
+			} else {
+				BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+					"xxxxxxxxxxxxxxxx AntennaDetect(), Antenna Det Fail!!\n");
+				BTC_TRACE(trace_buf);
+
+				board_info->btdm_ant_det_complete_fail = true;
+			}
+			psd_scan->ant_det_inteval_count = 0;
+		} else {
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				"xxxxxxxxxxxxxxxx AntennaDetect(), Antenna Det Timer is not up! (%d)\n",
+				    psd_scan->ant_det_inteval_count);
+			BTC_TRACE(trace_buf);
+		}
+
+	}
+#endif
+
+
+	/*
+			btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_SCAN, &scan);
+			btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_ROAM, &roam);
+
+
+			psd_scan->ant_det_bt_tx_time = seconds;
+		psd_scan->ant_det_bt_le_channel = cent_freq;
+
+		if (seconds == 0)
+			{
+			psd_scan->ant_det_try_count	= 0;
+			psd_scan->ant_det_fail_count	= 0;
+			ant_det_count = 0;
+			ant_det_fail_count = 0;
+			board_info->btdm_ant_det_finish = false;
+			board_info->btdm_ant_num_by_ant_det = 1;
+				 return;
+		}
+		else
+		{
+			ant_det_count++;
+
+			psd_scan->ant_det_try_count = ant_det_count;
+
+				if (scan ||roam)
+			{
+				board_info->btdm_ant_det_finish = false;
+				psd_scan->ant_det_result = 6;
+			}
+			else if (coex_sta->num_of_profile >= 1)
+			{
+				board_info->btdm_ant_det_finish = false;
+				psd_scan->ant_det_result = 7;
+			}
+				else if (!psd_scan->ant_det_is_ant_det_available)
+			{
+				board_info->btdm_ant_det_finish = false;
+				psd_scan->ant_det_result = 9;
+			}
+			else if (coex_sta->c2h_bt_inquiry_page)
+			{
+				board_info->btdm_ant_det_finish = false;
+				psd_scan->ant_det_result = 10;
+			}
+			else
+			{
+
+		}
+
+			if (!board_info->btdm_ant_det_finish)
+				ant_det_fail_count++;
+
+			psd_scan->ant_det_fail_count = ant_det_fail_count;
+		}
+	*/
+}
+
+
+void ex_halbtc8723b1ant_display_ant_detection(IN struct btc_coexist *btcoexist)
+{
+#if BT_8723B_1ANT_ANTDET_ENABLE
+	struct  btc_board_info	*board_info = &btcoexist->board_info;
+
+	if (psd_scan->ant_det_try_count != 0) {
+		halbtc8723b1ant_psd_show_antenna_detect_result(btcoexist);
+
+		if (board_info->btdm_ant_det_finish)
+			halbtc8723b1ant_psd_showdata(btcoexist);
+		return;
+	}
+#endif
+
+	/* halbtc8723b1ant_show_psd_data(btcoexist); */
+}
+
+#endif
+
+#endif	/* #if (BT_SUPPORT == 1 && COEX_SUPPORT == 1) */
+
+
+
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/btc/halbtc8723b1ant.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/btc/halbtc8723b1ant.h
--- linux-5.6.3/3rdparty/rtl8821ce/hal/btc/halbtc8723b1ant.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/btc/halbtc8723b1ant.h	2020-04-10 16:35:06.782658480 +0300
@@ -0,0 +1,293 @@
+
+#if (BT_SUPPORT == 1 && COEX_SUPPORT == 1)
+
+#if (RTL8723B_SUPPORT == 1)
+/* *******************************************
+ * The following is for 8723B 1ANT BT Co-exist definition
+ * ******************************************* */
+#define	BT_AUTO_REPORT_ONLY_8723B_1ANT				1
+
+#define	BT_INFO_8723B_1ANT_B_FTP						BIT(7)
+#define	BT_INFO_8723B_1ANT_B_A2DP					BIT(6)
+#define	BT_INFO_8723B_1ANT_B_HID						BIT(5)
+#define	BT_INFO_8723B_1ANT_B_SCO_BUSY				BIT(4)
+#define	BT_INFO_8723B_1ANT_B_ACL_BUSY				BIT(3)
+#define	BT_INFO_8723B_1ANT_B_INQ_PAGE				BIT(2)
+#define	BT_INFO_8723B_1ANT_B_SCO_ESCO				BIT(1)
+#define	BT_INFO_8723B_1ANT_B_CONNECTION				BIT(0)
+
+#define	BT_INFO_8723B_1ANT_A2DP_BASIC_RATE(_BT_INFO_EXT_)	\
+		(((_BT_INFO_EXT_&BIT(0))) ? true : false)
+
+#define	BTC_RSSI_COEX_THRESH_TOL_8723B_1ANT		2
+
+#define  BT_8723B_1ANT_WIFI_NOISY_THRESH								50 /* 30   /max: 255								 */
+
+/* for Antenna detection */
+#define	BT_8723B_1ANT_ANTDET_PSDTHRES_BACKGROUND						50
+#define	BT_8723B_1ANT_ANTDET_PSDTHRES_2ANT_BADISOLATION				70
+#define	BT_8723B_1ANT_ANTDET_PSDTHRES_2ANT_GOODISOLATION			48
+#define	BT_8723B_1ANT_ANTDET_PSDTHRES_1ANT							32
+#define	BT_8723B_1ANT_ANTDET_RETRY_INTERVAL							10	/* retry timer if ant det is fail, unit: second */
+#define	BT_8723B_1ANT_ANTDET_SWEEPPOINT_DELAY							40000
+#define	BT_8723B_1ANT_ANTDET_ENABLE										1
+#define	BT_8723B_1ANT_ANTDET_COEXMECHANISMSWITCH_ENABLE				1
+#define	BT_8723B_1ANT_ANTDET_BTTXTIME									100
+#define	BT_8723B_1ANT_ANTDET_BTTXCHANNEL								39
+
+enum bt_info_src_8723b_1ant {
+	BT_INFO_SRC_8723B_1ANT_WIFI_FW			= 0x0,
+	BT_INFO_SRC_8723B_1ANT_BT_RSP				= 0x1,
+	BT_INFO_SRC_8723B_1ANT_BT_ACTIVE_SEND		= 0x2,
+	BT_INFO_SRC_8723B_1ANT_MAX
+};
+
+enum bt_8723b_1ant_bt_status {
+	BT_8723B_1ANT_BT_STATUS_NON_CONNECTED_IDLE	= 0x0,
+	BT_8723B_1ANT_BT_STATUS_CONNECTED_IDLE		= 0x1,
+	BT_8723B_1ANT_BT_STATUS_INQ_PAGE				= 0x2,
+	BT_8723B_1ANT_BT_STATUS_ACL_BUSY				= 0x3,
+	BT_8723B_1ANT_BT_STATUS_SCO_BUSY				= 0x4,
+	BT_8723B_1ANT_BT_STATUS_ACL_SCO_BUSY			= 0x5,
+	BT_8723B_1ANT_BT_STATUS_MAX
+};
+
+enum bt_8723b_1ant_wifi_status {
+	BT_8723B_1ANT_WIFI_STATUS_NON_CONNECTED_IDLE				= 0x0,
+	BT_8723B_1ANT_WIFI_STATUS_NON_CONNECTED_ASSO_AUTH_SCAN		= 0x1,
+	BT_8723B_1ANT_WIFI_STATUS_CONNECTED_SCAN					= 0x2,
+	BT_8723B_1ANT_WIFI_STATUS_CONNECTED_SPECIFIC_PKT				= 0x3,
+	BT_8723B_1ANT_WIFI_STATUS_CONNECTED_IDLE					= 0x4,
+	BT_8723B_1ANT_WIFI_STATUS_CONNECTED_BUSY					= 0x5,
+	BT_8723B_1ANT_WIFI_STATUS_MAX
+};
+
+enum bt_8723b_1ant_coex_algo {
+	BT_8723B_1ANT_COEX_ALGO_UNDEFINED			= 0x0,
+	BT_8723B_1ANT_COEX_ALGO_SCO				= 0x1,
+	BT_8723B_1ANT_COEX_ALGO_HID				= 0x2,
+	BT_8723B_1ANT_COEX_ALGO_A2DP				= 0x3,
+	BT_8723B_1ANT_COEX_ALGO_A2DP_PANHS		= 0x4,
+	BT_8723B_1ANT_COEX_ALGO_PANEDR			= 0x5,
+	BT_8723B_1ANT_COEX_ALGO_PANHS			= 0x6,
+	BT_8723B_1ANT_COEX_ALGO_PANEDR_A2DP		= 0x7,
+	BT_8723B_1ANT_COEX_ALGO_PANEDR_HID		= 0x8,
+	BT_8723B_1ANT_COEX_ALGO_HID_A2DP_PANEDR	= 0x9,
+	BT_8723B_1ANT_COEX_ALGO_HID_A2DP			= 0xa,
+	BT_8723B_1ANT_COEX_ALGO_MAX				= 0xb,
+};
+
+struct coex_dm_8723b_1ant {
+	/* hw setting */
+	u8		pre_ant_pos_type;
+	u8		cur_ant_pos_type;
+	/* fw mechanism */
+	boolean		cur_ignore_wlan_act;
+	boolean		pre_ignore_wlan_act;
+	u8		pre_ps_tdma;
+	u8		cur_ps_tdma;
+	u8		ps_tdma_para[5];
+	u8		ps_tdma_du_adj_type;
+	boolean		auto_tdma_adjust;
+	boolean		pre_ps_tdma_on;
+	boolean		cur_ps_tdma_on;
+	boolean		pre_bt_auto_report;
+	boolean		cur_bt_auto_report;
+	u8		pre_lps;
+	u8		cur_lps;
+	u8		pre_rpwm;
+	u8		cur_rpwm;
+
+	/* sw mechanism */
+	boolean	pre_low_penalty_ra;
+	boolean		cur_low_penalty_ra;
+	u32		pre_val0x6c0;
+	u32		cur_val0x6c0;
+	u32		pre_val0x6c4;
+	u32		cur_val0x6c4;
+	u32		pre_val0x6c8;
+	u32		cur_val0x6c8;
+	u8		pre_val0x6cc;
+	u8		cur_val0x6cc;
+
+	u32		backup_arfr_cnt1;	/* Auto Rate Fallback Retry cnt */
+	u32		backup_arfr_cnt2;	/* Auto Rate Fallback Retry cnt */
+	u16		backup_retry_limit;
+	u8		backup_ampdu_max_time;
+
+	/* algorithm related */
+	u8		bt_status;
+	u8		wifi_chnl_info[3];
+
+	u32		pre_ra_mask;
+	u32		cur_ra_mask;
+	u8		pre_arfr_type;
+	u8		cur_arfr_type;
+	u8		pre_retry_limit_type;
+	u8		cur_retry_limit_type;
+	u8		pre_ampdu_time_type;
+	u8		cur_ampdu_time_type;
+	u32		arp_cnt;
+
+	u8		error_condition;
+};
+
+struct coex_sta_8723b_1ant {
+	boolean					bt_disabled;
+	boolean					bt_enable_disable_change;
+	boolean					bt_link_exist;
+	boolean					sco_exist;
+	boolean					a2dp_exist;
+	boolean					hid_exist;
+	boolean					pan_exist;
+	boolean					bt_hi_pri_link_exist;
+	u8					num_of_profile;
+	boolean					bt_abnormal_scan;
+
+	boolean					under_lps;
+	boolean					under_ips;
+	u32					specific_pkt_period_cnt;
+	u32					high_priority_tx;
+	u32					high_priority_rx;
+	u32					low_priority_tx;
+	u32					low_priority_rx;
+	s8					bt_rssi;
+	boolean					bt_tx_rx_mask;
+	boolean					c2h_bt_info_req_sent;
+	u8					bt_info_c2h[BT_INFO_SRC_8723B_1ANT_MAX][10];
+	u32					bt_info_c2h_cnt[BT_INFO_SRC_8723B_1ANT_MAX];
+	boolean					bt_whck_test;
+	boolean					c2h_bt_inquiry_page;
+	boolean					c2h_bt_remote_name_req;
+	boolean					wifi_is_high_pri_task;		/* Add for win8.1 page out issue */
+	u8					bt_retry_cnt;
+	u8					bt_info_ext;
+	u32					pop_event_cnt;
+	u8					scan_ap_num;
+
+	u32					crc_ok_cck;
+	u32					crc_ok_11g;
+	u32					crc_ok_11n;
+	u32					crc_ok_11n_vht;
+
+	u32					crc_err_cck;
+	u32					crc_err_11g;
+	u32					crc_err_11n;
+	u32					crc_err_11n_vht;
+
+	boolean					cck_lock;
+	boolean					pre_ccklock;
+	boolean					cck_ever_lock;
+	u8					coex_table_type;
+
+	boolean					force_lps_on;
+	u32					wrong_profile_notification;
+	u32					bt_coex_supported_version;
+	u8					a2dp_bit_pool;
+	u8					cut_version;
+};
+
+#define BT_8723B_1ANT_ANTDET_PSD_POINTS			256	/* MAX:1024 */
+#define BT_8723B_1ANT_ANTDET_PSD_AVGNUM		1	/* MAX:3 */
+#define	BT_8723B_1ANT_ANTDET_BUF_LEN			16
+
+struct psdscan_sta_8723b_1ant {
+
+	u32			ant_det_bt_le_channel;  /* BT LE Channel ex:2412 */
+	u32			ant_det_bt_tx_time;
+	u32			ant_det_pre_psdscan_peak_val;
+	boolean			ant_det_is_ant_det_available;
+	u32			ant_det_psd_scan_peak_val;
+	boolean			ant_det_is_btreply_available;
+	u32			ant_det_psd_scan_peak_freq;
+
+	u8			ant_det_result;
+	u8			ant_det_peak_val[BT_8723B_1ANT_ANTDET_BUF_LEN];
+	u8			ant_det_peak_freq[BT_8723B_1ANT_ANTDET_BUF_LEN];
+	u32			ant_det_try_count;
+	u32			ant_det_fail_count;
+	u32			ant_det_inteval_count;
+	u32			ant_det_thres_offset;
+
+	u32			real_cent_freq;
+	s32			real_offset;
+	u32			real_span;
+
+	u32			psd_band_width;  /* unit: Hz */
+	u32			psd_point;		/* 128/256/512/1024 */
+	u32			psd_report[1024];  /* unit:dB (20logx), 0~255 */
+	u32			psd_report_max_hold[1024];  /* unit:dB (20logx), 0~255 */
+	u32			psd_start_point;
+	u32			psd_stop_point;
+	u32			psd_max_value_point;
+	u32			psd_max_value;
+	u32			psd_start_base;
+	u32			psd_avg_num;	/* 1/8/16/32 */
+	u32			psd_gen_count;
+	boolean			is_psd_running;
+	boolean			is_psd_show_max_only;
+};
+
+/* *******************************************
+ * The following is interface which will notify coex module.
+ * ******************************************* */
+void ex_halbtc8723b1ant_power_on_setting(IN struct btc_coexist *btcoexist);
+void ex_halbtc8723b1ant_pre_load_firmware(IN struct btc_coexist *btcoexist);
+void ex_halbtc8723b1ant_init_hw_config(IN struct btc_coexist *btcoexist,
+				       IN boolean wifi_only);
+void ex_halbtc8723b1ant_init_coex_dm(IN struct btc_coexist *btcoexist);
+void ex_halbtc8723b1ant_ips_notify(IN struct btc_coexist *btcoexist,
+				   IN u8 type);
+void ex_halbtc8723b1ant_lps_notify(IN struct btc_coexist *btcoexist,
+				   IN u8 type);
+void ex_halbtc8723b1ant_scan_notify(IN struct btc_coexist *btcoexist,
+				    IN u8 type);
+void ex_halbtc8723b1ant_set_antenna_notify(IN struct btc_coexist *btcoexist,
+		IN u8 type);
+void ex_halbtc8723b1ant_connect_notify(IN struct btc_coexist *btcoexist,
+				       IN u8 type);
+void ex_halbtc8723b1ant_media_status_notify(IN struct btc_coexist *btcoexist,
+		IN u8 type);
+void ex_halbtc8723b1ant_specific_packet_notify(IN struct btc_coexist *btcoexist,
+		IN u8 type);
+void ex_halbtc8723b1ant_bt_info_notify(IN struct btc_coexist *btcoexist,
+				       IN u8 *tmp_buf, IN u8 length);
+void ex_halbtc8723b1ant_rf_status_notify(IN struct btc_coexist *btcoexist,
+		IN u8 type);
+void ex_halbtc8723b1ant_halt_notify(IN struct btc_coexist *btcoexist);
+void ex_halbtc8723b1ant_pnp_notify(IN struct btc_coexist *btcoexist,
+				   IN u8 pnp_state);
+void ex_halbtc8723b1ant_coex_dm_reset(IN struct btc_coexist *btcoexist);
+void ex_halbtc8723b1ant_periodical(IN struct btc_coexist *btcoexist);
+void ex_halbtc8723b1ant_display_coex_info(IN struct btc_coexist *btcoexist);
+void ex_halbtc8723b1ant_antenna_detection(IN struct btc_coexist *btcoexist,
+		IN u32 cent_freq, IN u32 offset, IN u32 span, IN u32 seconds);
+
+void ex_halbtc8723b1ant_display_ant_detection(IN struct btc_coexist *btcoexist);
+
+#else
+#define	ex_halbtc8723b1ant_power_on_setting(btcoexist)
+#define	ex_halbtc8723b1ant_pre_load_firmware(btcoexist)
+#define	ex_halbtc8723b1ant_init_hw_config(btcoexist, wifi_only)
+#define	ex_halbtc8723b1ant_init_coex_dm(btcoexist)
+#define	ex_halbtc8723b1ant_ips_notify(btcoexist, type)
+#define	ex_halbtc8723b1ant_lps_notify(btcoexist, type)
+#define	ex_halbtc8723b1ant_scan_notify(btcoexist, type)
+#define	ex_halbtc8723b1ant_set_antenna_notify(btcoexist, type)
+#define	ex_halbtc8723b1ant_connect_notify(btcoexist, type)
+#define	ex_halbtc8723b1ant_media_status_notify(btcoexist, type)
+#define	ex_halbtc8723b1ant_specific_packet_notify(btcoexist, type)
+#define	ex_halbtc8723b1ant_bt_info_notify(btcoexist, tmp_buf, length)
+#define	ex_halbtc8723b1ant_rf_status_notify(btcoexist, type)
+#define	ex_halbtc8723b1ant_halt_notify(btcoexist)
+#define	ex_halbtc8723b1ant_pnp_notify(btcoexist, pnp_state)
+#define	ex_halbtc8723b1ant_coex_dm_reset(btcoexist)
+#define	ex_halbtc8723b1ant_periodical(btcoexist)
+#define	ex_halbtc8723b1ant_display_coex_info(btcoexist)
+#define	ex_halbtc8723b1ant_antenna_detection(btcoexist, cent_freq, offset, span, seconds)
+#define	ex_halbtc8723b1ant_display_ant_detection(btcoexist)
+
+#endif
+
+#endif
+
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/btc/halbtc8723b2ant.c linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/btc/halbtc8723b2ant.c
--- linux-5.6.3/3rdparty/rtl8821ce/hal/btc/halbtc8723b2ant.c	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/btc/halbtc8723b2ant.c	2020-04-10 16:35:06.782658480 +0300
@@ -0,0 +1,4958 @@
+/* ************************************************************
+ * Description:
+ *
+ * This file is for RTL8723B Co-exist mechanism
+ *
+ * History
+ * 2012/11/15 Cosa first check in.
+ *
+ * ************************************************************ */
+
+/* ************************************************************
+ * include files
+ * ************************************************************ */
+#include "mp_precomp.h"
+
+#if (BT_SUPPORT == 1 && COEX_SUPPORT == 1)
+
+#if (RTL8723B_SUPPORT == 1)
+/* ************************************************************
+ * Global variables, these are static variables
+ * ************************************************************ */
+static u8	 *trace_buf = &gl_btc_trace_buf[0];
+static struct  coex_dm_8723b_2ant		glcoex_dm_8723b_2ant;
+static struct  coex_dm_8723b_2ant	*coex_dm = &glcoex_dm_8723b_2ant;
+static struct  coex_sta_8723b_2ant		glcoex_sta_8723b_2ant;
+static struct  coex_sta_8723b_2ant	*coex_sta = &glcoex_sta_8723b_2ant;
+
+const char *const glbt_info_src_8723b_2ant[] = {
+	"BT Info[wifi fw]",
+	"BT Info[bt rsp]",
+	"BT Info[bt auto report]",
+};
+
+u32	glcoex_ver_date_8723b_2ant = 20161007;
+u32	glcoex_ver_8723b_2ant = 0x4c;
+u32	glcoex_ver_btdesired_8723b_2ant = 0x4c;
+
+/* ************************************************************
+ * local function proto type if needed
+ * ************************************************************
+ * ************************************************************
+ * local function start with halbtc8723b2ant_
+ * ************************************************************ */
+u8 halbtc8723b2ant_bt_rssi_state(u8 *ppre_bt_rssi_state, u8 level_num,
+				 u8 rssi_thresh, u8 rssi_thresh1)
+{
+	s32			bt_rssi = 0;
+	u8			bt_rssi_state = *ppre_bt_rssi_state;
+
+	bt_rssi = coex_sta->bt_rssi;
+
+	if (level_num == 2) {
+		if ((*ppre_bt_rssi_state == BTC_RSSI_STATE_LOW) ||
+		    (*ppre_bt_rssi_state == BTC_RSSI_STATE_STAY_LOW)) {
+			if (bt_rssi >= (rssi_thresh +
+					BTC_RSSI_COEX_THRESH_TOL_8723B_2ANT))
+				bt_rssi_state = BTC_RSSI_STATE_HIGH;
+			else
+				bt_rssi_state = BTC_RSSI_STATE_STAY_LOW;
+		} else {
+			if (bt_rssi < rssi_thresh)
+				bt_rssi_state = BTC_RSSI_STATE_LOW;
+			else
+				bt_rssi_state = BTC_RSSI_STATE_STAY_HIGH;
+		}
+	} else if (level_num == 3) {
+		if (rssi_thresh > rssi_thresh1) {
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				    "[BTCoex], BT Rssi thresh error!!\n");
+			BTC_TRACE(trace_buf);
+			return *ppre_bt_rssi_state;
+		}
+
+		if ((*ppre_bt_rssi_state == BTC_RSSI_STATE_LOW) ||
+		    (*ppre_bt_rssi_state == BTC_RSSI_STATE_STAY_LOW)) {
+			if (bt_rssi >= (rssi_thresh +
+					BTC_RSSI_COEX_THRESH_TOL_8723B_2ANT))
+				bt_rssi_state = BTC_RSSI_STATE_MEDIUM;
+			else
+				bt_rssi_state = BTC_RSSI_STATE_STAY_LOW;
+		} else if ((*ppre_bt_rssi_state == BTC_RSSI_STATE_MEDIUM) ||
+			(*ppre_bt_rssi_state == BTC_RSSI_STATE_STAY_MEDIUM)) {
+			if (bt_rssi >= (rssi_thresh1 +
+					BTC_RSSI_COEX_THRESH_TOL_8723B_2ANT))
+				bt_rssi_state = BTC_RSSI_STATE_HIGH;
+			else if (bt_rssi < rssi_thresh)
+				bt_rssi_state = BTC_RSSI_STATE_LOW;
+			else
+				bt_rssi_state = BTC_RSSI_STATE_STAY_MEDIUM;
+		} else {
+			if (bt_rssi < rssi_thresh1)
+				bt_rssi_state = BTC_RSSI_STATE_MEDIUM;
+			else
+				bt_rssi_state = BTC_RSSI_STATE_STAY_HIGH;
+		}
+	}
+
+	*ppre_bt_rssi_state = bt_rssi_state;
+
+	return bt_rssi_state;
+}
+
+u8 halbtc8723b2ant_wifi_rssi_state(IN struct btc_coexist *btcoexist,
+	   IN u8 *pprewifi_rssi_state, IN u8 level_num, IN u8 rssi_thresh,
+				   IN u8 rssi_thresh1)
+{
+	s32			wifi_rssi = 0;
+	u8			wifi_rssi_state = *pprewifi_rssi_state;
+
+	btcoexist->btc_get(btcoexist, BTC_GET_S4_WIFI_RSSI, &wifi_rssi);
+
+	if (level_num == 2) {
+		if ((*pprewifi_rssi_state == BTC_RSSI_STATE_LOW) ||
+		    (*pprewifi_rssi_state == BTC_RSSI_STATE_STAY_LOW)) {
+			if (wifi_rssi >= (rssi_thresh +
+					  BTC_RSSI_COEX_THRESH_TOL_8723B_2ANT))
+				wifi_rssi_state = BTC_RSSI_STATE_HIGH;
+			else
+				wifi_rssi_state = BTC_RSSI_STATE_STAY_LOW;
+		} else {
+			if (wifi_rssi < rssi_thresh)
+				wifi_rssi_state = BTC_RSSI_STATE_LOW;
+			else
+				wifi_rssi_state = BTC_RSSI_STATE_STAY_HIGH;
+		}
+	} else if (level_num == 3) {
+		if (rssi_thresh > rssi_thresh1) {
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				    "[BTCoex], wifi RSSI thresh error!!\n");
+			BTC_TRACE(trace_buf);
+			return *pprewifi_rssi_state;
+		}
+
+		if ((*pprewifi_rssi_state == BTC_RSSI_STATE_LOW) ||
+		    (*pprewifi_rssi_state == BTC_RSSI_STATE_STAY_LOW)) {
+			if (wifi_rssi >= (rssi_thresh +
+					  BTC_RSSI_COEX_THRESH_TOL_8723B_2ANT))
+				wifi_rssi_state = BTC_RSSI_STATE_MEDIUM;
+			else
+				wifi_rssi_state = BTC_RSSI_STATE_STAY_LOW;
+		} else if ((*pprewifi_rssi_state == BTC_RSSI_STATE_MEDIUM) ||
+			(*pprewifi_rssi_state == BTC_RSSI_STATE_STAY_MEDIUM)) {
+			if (wifi_rssi >= (rssi_thresh1 +
+					  BTC_RSSI_COEX_THRESH_TOL_8723B_2ANT))
+				wifi_rssi_state = BTC_RSSI_STATE_HIGH;
+			else if (wifi_rssi < rssi_thresh)
+				wifi_rssi_state = BTC_RSSI_STATE_LOW;
+			else
+				wifi_rssi_state = BTC_RSSI_STATE_STAY_MEDIUM;
+		} else {
+			if (wifi_rssi < rssi_thresh1)
+				wifi_rssi_state = BTC_RSSI_STATE_MEDIUM;
+			else
+				wifi_rssi_state = BTC_RSSI_STATE_STAY_HIGH;
+		}
+	}
+
+	*pprewifi_rssi_state = wifi_rssi_state;
+
+	return wifi_rssi_state;
+}
+
+void halbtc8723b2ant_monitor_bt_enable_disable(IN struct btc_coexist *btcoexist)
+{
+	static u32		bt_disable_cnt = 0;
+	boolean		bt_active = true, bt_disabled = false;
+
+	/* This function check if bt is disabled */
+
+	if (coex_sta->high_priority_tx == 0 &&
+	    coex_sta->high_priority_rx == 0 &&
+	    coex_sta->low_priority_tx == 0 &&
+	    coex_sta->low_priority_rx == 0)
+		bt_active = false;
+	if (coex_sta->high_priority_tx == 0xffff &&
+	    coex_sta->high_priority_rx == 0xffff &&
+	    coex_sta->low_priority_tx == 0xffff &&
+	    coex_sta->low_priority_rx == 0xffff)
+		bt_active = false;
+	if (bt_active) {
+		bt_disable_cnt = 0;
+		bt_disabled = false;
+	} else {
+		bt_disable_cnt++;
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], bt all counters=0, %d times!!\n",
+			    bt_disable_cnt);
+		BTC_TRACE(trace_buf);
+		if (bt_disable_cnt >= 10)
+			bt_disabled = true;
+	}
+	if (coex_sta->bt_disabled != bt_disabled) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], BT is from %s to %s!!\n",
+			    (coex_sta->bt_disabled ? "disabled" : "enabled"),
+			    (bt_disabled ? "disabled" : "enabled"));
+		BTC_TRACE(trace_buf);
+
+		coex_sta->bt_disabled = bt_disabled;
+		btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_DISABLE,
+				   &bt_disabled);
+		if (bt_disabled) {
+			btcoexist->btc_set(btcoexist, BTC_SET_ACT_LEAVE_LPS,
+					   NULL);
+			btcoexist->btc_set(btcoexist, BTC_SET_ACT_NORMAL_LPS,
+					   NULL);
+		}
+	}
+}
+
+
+void halbtc8723b2ant_limited_rx(IN struct btc_coexist *btcoexist,
+			IN boolean force_exec, IN boolean rej_ap_agg_pkt,
+			IN boolean bt_ctrl_agg_buf_size, IN u8 agg_buf_size)
+{
+	boolean	reject_rx_agg = rej_ap_agg_pkt;
+	boolean	bt_ctrl_rx_agg_size = bt_ctrl_agg_buf_size;
+	u8	rx_agg_size = agg_buf_size;
+
+	/* ============================================ */
+	/*	Rx Aggregation related setting */
+	/* ============================================ */
+	btcoexist->btc_set(btcoexist, BTC_SET_BL_TO_REJ_AP_AGG_PKT,
+			   &reject_rx_agg);
+	/* decide BT control aggregation buf size or not */
+	btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_CTRL_AGG_SIZE,
+			   &bt_ctrl_rx_agg_size);
+	/* aggregation buf size, only work when BT control Rx aggregation size. */
+	btcoexist->btc_set(btcoexist, BTC_SET_U1_AGG_BUF_SIZE, &rx_agg_size);
+	/* real update aggregation setting */
+	btcoexist->btc_set(btcoexist, BTC_SET_ACT_AGGREGATE_CTRL, NULL);
+}
+
+void halbtc8723b2ant_monitor_bt_ctr(IN struct btc_coexist *btcoexist)
+{
+	u32			reg_hp_txrx, reg_lp_txrx, u32tmp;
+	u32			reg_hp_tx = 0, reg_hp_rx = 0, reg_lp_tx = 0, reg_lp_rx = 0;
+
+	struct  btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
+
+	reg_hp_txrx = 0x770;
+	reg_lp_txrx = 0x774;
+
+	u32tmp = btcoexist->btc_read_4byte(btcoexist, reg_hp_txrx);
+	reg_hp_tx = u32tmp & MASKLWORD;
+	reg_hp_rx = (u32tmp & MASKHWORD) >> 16;
+
+	u32tmp = btcoexist->btc_read_4byte(btcoexist, reg_lp_txrx);
+	reg_lp_tx = u32tmp & MASKLWORD;
+	reg_lp_rx = (u32tmp & MASKHWORD) >> 16;
+
+	coex_sta->high_priority_tx = reg_hp_tx;
+	coex_sta->high_priority_rx = reg_hp_rx;
+	coex_sta->low_priority_tx = reg_lp_tx;
+	coex_sta->low_priority_rx = reg_lp_rx;
+
+	if ((coex_sta->low_priority_tx > 1050)  &&
+	    (!coex_sta->c2h_bt_inquiry_page))
+		coex_sta->pop_event_cnt++;
+
+	if ((coex_sta->low_priority_rx >= 950)  &&
+	    (coex_sta->low_priority_rx >= coex_sta->low_priority_tx) &&
+	    (!coex_sta->under_ips))
+		bt_link_info->slave_role = true;
+	else
+		bt_link_info->slave_role = false;
+
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+		"[BTCoex], High Priority Tx/Rx (reg 0x%x)=0x%x(%d)/0x%x(%d)\n",
+		    reg_hp_txrx, reg_hp_tx, reg_hp_tx, reg_hp_rx, reg_hp_rx);
+	BTC_TRACE(trace_buf);
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+		"[BTCoex], Low Priority Tx/Rx (reg 0x%x)=0x%x(%d)/0x%x(%d)\n",
+		    reg_lp_txrx, reg_lp_tx, reg_lp_tx, reg_lp_rx, reg_lp_rx);
+	BTC_TRACE(trace_buf);
+
+	/* reset counter */
+	btcoexist->btc_write_1byte(btcoexist, 0x76e, 0xc);
+}
+
+void halbtc8723b2ant_monitor_wifi_ctr(IN struct btc_coexist *btcoexist)
+{
+#if 1
+
+	coex_sta->crc_ok_cck = btcoexist->btc_phydm_query_PHY_counter(
+				       btcoexist,
+				       PHYDM_INFO_CRC32_OK_CCK);
+	coex_sta->crc_ok_11g = btcoexist->btc_phydm_query_PHY_counter(
+				       btcoexist,
+				       PHYDM_INFO_CRC32_OK_LEGACY);
+	coex_sta->crc_ok_11n = btcoexist->btc_phydm_query_PHY_counter(
+				       btcoexist,
+				       PHYDM_INFO_CRC32_OK_HT);
+	coex_sta->crc_ok_11n_vht =
+		btcoexist->btc_phydm_query_PHY_counter(
+			btcoexist,
+			PHYDM_INFO_CRC32_OK_VHT);
+
+	coex_sta->crc_err_cck = btcoexist->btc_phydm_query_PHY_counter(
+					btcoexist,
+					PHYDM_INFO_CRC32_ERROR_CCK);
+	coex_sta->crc_err_11g =  btcoexist->btc_phydm_query_PHY_counter(
+					 btcoexist,
+					 PHYDM_INFO_CRC32_ERROR_LEGACY);
+	coex_sta->crc_err_11n = btcoexist->btc_phydm_query_PHY_counter(
+					btcoexist,
+					PHYDM_INFO_CRC32_ERROR_HT);
+	coex_sta->crc_err_11n_vht =
+		btcoexist->btc_phydm_query_PHY_counter(
+			btcoexist,
+			PHYDM_INFO_CRC32_ERROR_VHT);
+
+#endif
+}
+
+void halbtc8723b2ant_query_bt_info(IN struct btc_coexist *btcoexist)
+{
+	u8			h2c_parameter[1] = {0};
+
+	coex_sta->c2h_bt_info_req_sent = true;
+
+	h2c_parameter[0] |= BIT(0);	/* trigger */
+
+	btcoexist->btc_fill_h2c(btcoexist, 0x61, 1, h2c_parameter);
+}
+
+boolean halbtc8723b2ant_is_wifi_status_changed(IN struct btc_coexist *btcoexist)
+{
+	static boolean	pre_wifi_busy = false, pre_under_4way = false,
+			pre_bt_hs_on = false;
+	static u8	prewifi_rssi_state = BTC_RSSI_STATE_LOW;
+	boolean			wifi_busy = false, under_4way = false, bt_hs_on = false;
+	boolean			wifi_connected = false;
+	u8			wifi_rssi_state = BTC_RSSI_STATE_HIGH;
+
+
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED,
+			   &wifi_connected);
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy);
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on);
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_4_WAY_PROGRESS,
+			   &under_4way);
+
+	if (wifi_connected) {
+		if (wifi_busy != pre_wifi_busy) {
+			pre_wifi_busy = wifi_busy;
+			return true;
+		}
+		if (under_4way != pre_under_4way) {
+			pre_under_4way = under_4way;
+			return true;
+		}
+		if (bt_hs_on != pre_bt_hs_on) {
+			pre_bt_hs_on = bt_hs_on;
+			return true;
+		}
+
+
+		wifi_rssi_state = halbtc8723b2ant_wifi_rssi_state(btcoexist,
+				  &prewifi_rssi_state, 2,
+				  BT_8723B_2ANT_WIFI_RSSI_COEXSWITCH_THRES -
+				  coex_dm->switch_thres_offset, 0);
+
+		if ((BTC_RSSI_STATE_HIGH == wifi_rssi_state) ||
+		    (BTC_RSSI_STATE_LOW == wifi_rssi_state))
+			return true;
+
+	}
+
+	return false;
+}
+
+void halbtc8723b2ant_update_bt_link_info(IN struct btc_coexist *btcoexist)
+{
+	struct  btc_bt_link_info	*bt_link_info = &btcoexist->bt_link_info;
+	boolean				bt_hs_on = false;
+
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on);
+
+	bt_link_info->bt_link_exist = coex_sta->bt_link_exist;
+	bt_link_info->sco_exist = coex_sta->sco_exist;
+	bt_link_info->a2dp_exist = coex_sta->a2dp_exist;
+	bt_link_info->pan_exist = coex_sta->pan_exist;
+	bt_link_info->hid_exist = coex_sta->hid_exist;
+
+	/* work around for HS mode. */
+	if (bt_hs_on) {
+		bt_link_info->pan_exist = true;
+		bt_link_info->bt_link_exist = true;
+	}
+
+	/* check if Sco only */
+	if (bt_link_info->sco_exist &&
+	    !bt_link_info->a2dp_exist &&
+	    !bt_link_info->pan_exist &&
+	    !bt_link_info->hid_exist)
+		bt_link_info->sco_only = true;
+	else
+		bt_link_info->sco_only = false;
+
+	/* check if A2dp only */
+	if (!bt_link_info->sco_exist &&
+	    bt_link_info->a2dp_exist &&
+	    !bt_link_info->pan_exist &&
+	    !bt_link_info->hid_exist)
+		bt_link_info->a2dp_only = true;
+	else
+		bt_link_info->a2dp_only = false;
+
+	/* check if Pan only */
+	if (!bt_link_info->sco_exist &&
+	    !bt_link_info->a2dp_exist &&
+	    bt_link_info->pan_exist &&
+	    !bt_link_info->hid_exist)
+		bt_link_info->pan_only = true;
+	else
+		bt_link_info->pan_only = false;
+
+	/* check if Hid only */
+	if (!bt_link_info->sco_exist &&
+	    !bt_link_info->a2dp_exist &&
+	    !bt_link_info->pan_exist &&
+	    bt_link_info->hid_exist)
+		bt_link_info->hid_only = true;
+	else
+		bt_link_info->hid_only = false;
+}
+
+u8 halbtc8723b2ant_action_algorithm(IN struct btc_coexist *btcoexist)
+{
+	struct  btc_bt_link_info	*bt_link_info = &btcoexist->bt_link_info;
+	boolean				bt_hs_on = false;
+	u8				algorithm = BT_8723B_2ANT_COEX_ALGO_UNDEFINED;
+	u8				num_of_diff_profile = 0;
+
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on);
+
+	if (!bt_link_info->bt_link_exist) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], No BT link exists!!!\n");
+		BTC_TRACE(trace_buf);
+		return algorithm;
+	}
+
+	if (bt_link_info->sco_exist)
+		num_of_diff_profile++;
+	if (bt_link_info->hid_exist)
+		num_of_diff_profile++;
+	if (bt_link_info->pan_exist)
+		num_of_diff_profile++;
+	if (bt_link_info->a2dp_exist)
+		num_of_diff_profile++;
+
+	if (num_of_diff_profile == 1) {
+		if (bt_link_info->sco_exist) {
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				    "[BTCoex], SCO only\n");
+			BTC_TRACE(trace_buf);
+			algorithm = BT_8723B_2ANT_COEX_ALGO_SCO;
+		} else {
+			if (bt_link_info->hid_exist) {
+				BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+					    "[BTCoex], HID only\n");
+				BTC_TRACE(trace_buf);
+				algorithm = BT_8723B_2ANT_COEX_ALGO_HID;
+			} else if (bt_link_info->a2dp_exist) {
+				BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+					    "[BTCoex], A2DP only\n");
+				BTC_TRACE(trace_buf);
+				algorithm = BT_8723B_2ANT_COEX_ALGO_A2DP;
+			} else if (bt_link_info->pan_exist) {
+				if (bt_hs_on) {
+					BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+						    "[BTCoex], PAN(HS) only\n");
+					BTC_TRACE(trace_buf);
+					algorithm =
+						BT_8723B_2ANT_COEX_ALGO_PANHS;
+				} else {
+					BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+						"[BTCoex], PAN(EDR) only\n");
+					BTC_TRACE(trace_buf);
+					algorithm =
+						BT_8723B_2ANT_COEX_ALGO_PANEDR;
+				}
+			}
+		}
+	} else if (num_of_diff_profile == 2) {
+		if (bt_link_info->sco_exist) {
+			if (bt_link_info->hid_exist) {
+				BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+					    "[BTCoex], SCO + HID\n");
+				BTC_TRACE(trace_buf);
+				algorithm = BT_8723B_2ANT_COEX_ALGO_PANEDR_HID;
+			} else if (bt_link_info->a2dp_exist) {
+				BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+					    "[BTCoex], SCO + A2DP ==> SCO\n");
+				BTC_TRACE(trace_buf);
+				algorithm = BT_8723B_2ANT_COEX_ALGO_PANEDR_HID;
+			} else if (bt_link_info->pan_exist) {
+				if (bt_hs_on) {
+					BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+						"[BTCoex], SCO + PAN(HS)\n");
+					BTC_TRACE(trace_buf);
+					algorithm = BT_8723B_2ANT_COEX_ALGO_SCO;
+				} else {
+					BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+						"[BTCoex], SCO + PAN(EDR)\n");
+					BTC_TRACE(trace_buf);
+					algorithm =
+						BT_8723B_2ANT_COEX_ALGO_PANEDR_HID;
+				}
+			}
+		} else {
+			if (bt_link_info->hid_exist &&
+			    bt_link_info->a2dp_exist) {
+				{
+					BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+						    "[BTCoex], HID + A2DP\n");
+					BTC_TRACE(trace_buf);
+					algorithm =
+						BT_8723B_2ANT_COEX_ALGO_HID_A2DP;
+				}
+			} else if (bt_link_info->hid_exist &&
+				   bt_link_info->pan_exist) {
+				if (bt_hs_on) {
+					BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+						"[BTCoex], HID + PAN(HS)\n");
+					BTC_TRACE(trace_buf);
+					algorithm = BT_8723B_2ANT_COEX_ALGO_HID;
+				} else {
+					BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+						"[BTCoex], HID + PAN(EDR)\n");
+					BTC_TRACE(trace_buf);
+					algorithm =
+						BT_8723B_2ANT_COEX_ALGO_PANEDR_HID;
+				}
+			} else if (bt_link_info->pan_exist &&
+				   bt_link_info->a2dp_exist) {
+				if (bt_hs_on) {
+					BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+						"[BTCoex], A2DP + PAN(HS)\n");
+					BTC_TRACE(trace_buf);
+					algorithm =
+						BT_8723B_2ANT_COEX_ALGO_A2DP_PANHS;
+				} else {
+					BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+						"[BTCoex], A2DP + PAN(EDR)\n");
+					BTC_TRACE(trace_buf);
+					algorithm =
+						BT_8723B_2ANT_COEX_ALGO_PANEDR_A2DP;
+				}
+			}
+		}
+	} else if (num_of_diff_profile == 3) {
+		if (bt_link_info->sco_exist) {
+			if (bt_link_info->hid_exist &&
+			    bt_link_info->a2dp_exist) {
+				BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+					"[BTCoex], SCO + HID + A2DP ==> HID\n");
+				BTC_TRACE(trace_buf);
+				algorithm = BT_8723B_2ANT_COEX_ALGO_PANEDR_HID;
+			} else if (bt_link_info->hid_exist &&
+				   bt_link_info->pan_exist) {
+				if (bt_hs_on) {
+					BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+						"[BTCoex], SCO + HID + PAN(HS)\n");
+					BTC_TRACE(trace_buf);
+					algorithm =
+						BT_8723B_2ANT_COEX_ALGO_PANEDR_HID;
+				} else {
+					BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+						"[BTCoex], SCO + HID + PAN(EDR)\n");
+					BTC_TRACE(trace_buf);
+					algorithm =
+						BT_8723B_2ANT_COEX_ALGO_PANEDR_HID;
+				}
+			} else if (bt_link_info->pan_exist &&
+				   bt_link_info->a2dp_exist) {
+				if (bt_hs_on) {
+					BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+						"[BTCoex], SCO + A2DP + PAN(HS)\n");
+					BTC_TRACE(trace_buf);
+					algorithm =
+						BT_8723B_2ANT_COEX_ALGO_PANEDR_HID;
+				} else {
+					BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+						"[BTCoex], SCO + A2DP + PAN(EDR) ==> HID\n");
+					BTC_TRACE(trace_buf);
+					algorithm =
+						BT_8723B_2ANT_COEX_ALGO_PANEDR_HID;
+				}
+			}
+		} else {
+			if (bt_link_info->hid_exist &&
+			    bt_link_info->pan_exist &&
+			    bt_link_info->a2dp_exist) {
+				if (bt_hs_on) {
+					BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+						"[BTCoex], HID + A2DP + PAN(HS)\n");
+					BTC_TRACE(trace_buf);
+					algorithm =
+						BT_8723B_2ANT_COEX_ALGO_HID_A2DP;
+				} else {
+					BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+						"[BTCoex], HID + A2DP + PAN(EDR)\n");
+					BTC_TRACE(trace_buf);
+					algorithm =
+						BT_8723B_2ANT_COEX_ALGO_HID_A2DP_PANEDR;
+				}
+			}
+		}
+	} else if (num_of_diff_profile >= 3) {
+		if (bt_link_info->sco_exist) {
+			if (bt_link_info->hid_exist &&
+			    bt_link_info->pan_exist &&
+			    bt_link_info->a2dp_exist) {
+				if (bt_hs_on) {
+					BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+						"[BTCoex], Error!!! SCO + HID + A2DP + PAN(HS)\n");
+					BTC_TRACE(trace_buf);
+
+				} else {
+					BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+						"[BTCoex], SCO + HID + A2DP + PAN(EDR)==>PAN(EDR)+HID\n");
+					BTC_TRACE(trace_buf);
+					algorithm =
+						BT_8723B_2ANT_COEX_ALGO_PANEDR_HID;
+				}
+			}
+		}
+	}
+
+	return algorithm;
+}
+
+void halbtc8723b2ant_set_fw_dac_swing_level(IN struct btc_coexist *btcoexist,
+		IN u8 dac_swing_lvl)
+{
+	u8			h2c_parameter[1] = {0};
+
+	/* There are several type of dacswing */
+	/* 0x18/ 0x10/ 0xc/ 0x8/ 0x4/ 0x6 */
+	h2c_parameter[0] = dac_swing_lvl;
+
+	btcoexist->btc_fill_h2c(btcoexist, 0x64, 1, h2c_parameter);
+}
+
+void halbtc8723b2ant_set_fw_dec_bt_pwr(IN struct btc_coexist *btcoexist,
+				       IN u8 dec_bt_pwr_lvl)
+{
+	u8			h2c_parameter[1] = {0};
+
+	h2c_parameter[0] = dec_bt_pwr_lvl;
+
+	btcoexist->btc_fill_h2c(btcoexist, 0x62, 1, h2c_parameter);
+}
+
+void halbtc8723b2ant_dec_bt_pwr(IN struct btc_coexist *btcoexist,
+				IN boolean force_exec, IN u8 dec_bt_pwr_lvl)
+{
+	coex_dm->cur_bt_dec_pwr_lvl = dec_bt_pwr_lvl;
+
+	if (!force_exec) {
+		if (coex_dm->pre_bt_dec_pwr_lvl == coex_dm->cur_bt_dec_pwr_lvl)
+			return;
+	}
+	halbtc8723b2ant_set_fw_dec_bt_pwr(btcoexist,
+					  coex_dm->cur_bt_dec_pwr_lvl);
+
+	coex_dm->pre_bt_dec_pwr_lvl = coex_dm->cur_bt_dec_pwr_lvl;
+}
+
+void halbtc8723b2ant_set_bt_auto_report(IN struct btc_coexist *btcoexist,
+					IN boolean enable_auto_report)
+{
+	u8			h2c_parameter[1] = {0};
+
+	h2c_parameter[0] = 0;
+
+	if (enable_auto_report)
+		h2c_parameter[0] |= BIT(0);
+
+	btcoexist->btc_fill_h2c(btcoexist, 0x68, 1, h2c_parameter);
+}
+
+void halbtc8723b2ant_bt_auto_report(IN struct btc_coexist *btcoexist,
+		    IN boolean force_exec, IN boolean enable_auto_report)
+{
+	coex_dm->cur_bt_auto_report = enable_auto_report;
+
+	if (!force_exec) {
+		if (coex_dm->pre_bt_auto_report == coex_dm->cur_bt_auto_report)
+			return;
+	}
+	halbtc8723b2ant_set_bt_auto_report(btcoexist,
+					   coex_dm->cur_bt_auto_report);
+
+	coex_dm->pre_bt_auto_report = coex_dm->cur_bt_auto_report;
+}
+
+void halbtc8723b2ant_fw_dac_swing_lvl(IN struct btc_coexist *btcoexist,
+			      IN boolean force_exec, IN u8 fw_dac_swing_lvl)
+{
+	coex_dm->cur_fw_dac_swing_lvl = fw_dac_swing_lvl;
+
+	if (!force_exec) {
+		if (coex_dm->pre_fw_dac_swing_lvl ==
+		    coex_dm->cur_fw_dac_swing_lvl)
+			return;
+	}
+
+	halbtc8723b2ant_set_fw_dac_swing_level(btcoexist,
+					       coex_dm->cur_fw_dac_swing_lvl);
+
+	coex_dm->pre_fw_dac_swing_lvl = coex_dm->cur_fw_dac_swing_lvl;
+}
+
+void halbtc8723b2ant_set_sw_rf_rx_lpf_corner(IN struct btc_coexist *btcoexist,
+		IN boolean rx_rf_shrink_on)
+{
+	if (rx_rf_shrink_on) {
+		/* Shrink RF Rx LPF corner */
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], Shrink RF Rx LPF corner!!\n");
+		BTC_TRACE(trace_buf);
+		btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1e, 0xfffff,
+					  0xffffc);
+	} else {
+		/* Resume RF Rx LPF corner */
+		/* After initialized, we can use coex_dm->bt_rf_0x1e_backup */
+		if (btcoexist->initilized) {
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				    "[BTCoex], Resume RF Rx LPF corner!!\n");
+			BTC_TRACE(trace_buf);
+			btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1e,
+					  0xfffff, coex_dm->bt_rf_0x1e_backup);
+		}
+	}
+}
+
+void halbtc8723b2ant_rf_shrink(IN struct btc_coexist *btcoexist,
+		       IN boolean force_exec, IN boolean rx_rf_shrink_on)
+{
+	coex_dm->cur_rf_rx_lpf_shrink = rx_rf_shrink_on;
+
+	if (!force_exec) {
+		if (coex_dm->pre_rf_rx_lpf_shrink ==
+		    coex_dm->cur_rf_rx_lpf_shrink)
+			return;
+	}
+	halbtc8723b2ant_set_sw_rf_rx_lpf_corner(btcoexist,
+						coex_dm->cur_rf_rx_lpf_shrink);
+
+	coex_dm->pre_rf_rx_lpf_shrink = coex_dm->cur_rf_rx_lpf_shrink;
+}
+
+void halbtc8723b2ant_set_sw_penalty_tx_rate_adaptive(IN struct btc_coexist
+		*btcoexist, IN boolean low_penalty_ra)
+{
+	u8			h2c_parameter[6] = {0};
+
+	h2c_parameter[0] = 0x6;	/* op_code, 0x6= Retry_Penalty */
+
+	if (low_penalty_ra) {
+		h2c_parameter[1] |= BIT(0);
+		h2c_parameter[2] =
+			0x00;  /* normal rate except MCS7/6/5, OFDM54/48/36 */
+		h2c_parameter[3] = 0xf4;  /* MCS7 or OFDM54 */
+		h2c_parameter[4] = 0xf5;  /* MCS6 or OFDM48 */
+		h2c_parameter[5] = 0xf6;	/* MCS5 or OFDM36	 */
+	}
+
+	btcoexist->btc_fill_h2c(btcoexist, 0x69, 6, h2c_parameter);
+}
+
+void halbtc8723b2ant_low_penalty_ra(IN struct btc_coexist *btcoexist,
+			    IN boolean force_exec, IN boolean low_penalty_ra)
+{
+	coex_dm->cur_low_penalty_ra = low_penalty_ra;
+
+	if (!force_exec) {
+		if (coex_dm->pre_low_penalty_ra == coex_dm->cur_low_penalty_ra)
+			return;
+	}
+	halbtc8723b2ant_set_sw_penalty_tx_rate_adaptive(btcoexist,
+			coex_dm->cur_low_penalty_ra);
+
+	coex_dm->pre_low_penalty_ra = coex_dm->cur_low_penalty_ra;
+}
+
+void halbtc8723b2ant_set_dac_swing_reg(IN struct btc_coexist *btcoexist,
+				       IN u32 level)
+{
+	u8	val = (u8)level;
+
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+		    "[BTCoex], Write SwDacSwing = 0x%x\n", level);
+	BTC_TRACE(trace_buf);
+	btcoexist->btc_write_1byte_bitmask(btcoexist, 0x883, 0x3e, val);
+}
+
+void halbtc8723b2ant_set_sw_full_time_dac_swing(IN struct btc_coexist
+		*btcoexist, IN boolean sw_dac_swing_on, IN u32 sw_dac_swing_lvl)
+{
+	if (sw_dac_swing_on)
+		halbtc8723b2ant_set_dac_swing_reg(btcoexist, sw_dac_swing_lvl);
+	else
+		halbtc8723b2ant_set_dac_swing_reg(btcoexist, 0x18);
+}
+
+
+void halbtc8723b2ant_dac_swing(IN struct btc_coexist *btcoexist,
+	IN boolean force_exec, IN boolean dac_swing_on, IN u32 dac_swing_lvl)
+{
+	coex_dm->cur_dac_swing_on = dac_swing_on;
+	coex_dm->cur_dac_swing_lvl = dac_swing_lvl;
+
+	if (!force_exec) {
+		if ((coex_dm->pre_dac_swing_on == coex_dm->cur_dac_swing_on) &&
+		    (coex_dm->pre_dac_swing_lvl ==
+		     coex_dm->cur_dac_swing_lvl))
+			return;
+	}
+	delay_ms(30);
+	halbtc8723b2ant_set_sw_full_time_dac_swing(btcoexist, dac_swing_on,
+			dac_swing_lvl);
+
+	coex_dm->pre_dac_swing_on = coex_dm->cur_dac_swing_on;
+	coex_dm->pre_dac_swing_lvl = coex_dm->cur_dac_swing_lvl;
+}
+
+void halbtc8723b2ant_set_adc_back_off(IN struct btc_coexist *btcoexist,
+				      IN boolean adc_back_off)
+{
+	if (adc_back_off) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], BB BackOff Level On!\n");
+		BTC_TRACE(trace_buf);
+		btcoexist->btc_write_1byte_bitmask(btcoexist, 0xc05, 0x30, 0x3);
+	} else {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], BB BackOff Level Off!\n");
+		BTC_TRACE(trace_buf);
+		btcoexist->btc_write_1byte_bitmask(btcoexist, 0xc05, 0x30, 0x1);
+	}
+}
+
+void halbtc8723b2ant_adc_back_off(IN struct btc_coexist *btcoexist,
+			  IN boolean force_exec, IN boolean adc_back_off)
+{
+	coex_dm->cur_adc_back_off = adc_back_off;
+
+	if (!force_exec) {
+		if (coex_dm->pre_adc_back_off == coex_dm->cur_adc_back_off)
+			return;
+	}
+	halbtc8723b2ant_set_adc_back_off(btcoexist, coex_dm->cur_adc_back_off);
+
+	coex_dm->pre_adc_back_off = coex_dm->cur_adc_back_off;
+}
+
+void halbtc8723b2ant_set_agc_table(IN struct btc_coexist *btcoexist,
+				   IN boolean agc_table_en)
+{
+	u8		rssi_adjust_val = 0;
+
+	/* =================BB AGC Gain Table */
+	if (agc_table_en) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], BB Agc Table On!\n");
+		BTC_TRACE(trace_buf);
+		btcoexist->btc_write_4byte(btcoexist, 0xc78, 0x6e1A0001);
+		btcoexist->btc_write_4byte(btcoexist, 0xc78, 0x6d1B0001);
+		btcoexist->btc_write_4byte(btcoexist, 0xc78, 0x6c1C0001);
+		btcoexist->btc_write_4byte(btcoexist, 0xc78, 0x6b1D0001);
+		btcoexist->btc_write_4byte(btcoexist, 0xc78, 0x6a1E0001);
+		btcoexist->btc_write_4byte(btcoexist, 0xc78, 0x691F0001);
+		btcoexist->btc_write_4byte(btcoexist, 0xc78, 0x68200001);
+	} else {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], BB Agc Table Off!\n");
+		BTC_TRACE(trace_buf);
+		btcoexist->btc_write_4byte(btcoexist, 0xc78, 0xaa1A0001);
+		btcoexist->btc_write_4byte(btcoexist, 0xc78, 0xa91B0001);
+		btcoexist->btc_write_4byte(btcoexist, 0xc78, 0xa81C0001);
+		btcoexist->btc_write_4byte(btcoexist, 0xc78, 0xa71D0001);
+		btcoexist->btc_write_4byte(btcoexist, 0xc78, 0xa61E0001);
+		btcoexist->btc_write_4byte(btcoexist, 0xc78, 0xa51F0001);
+		btcoexist->btc_write_4byte(btcoexist, 0xc78, 0xa4200001);
+	}
+
+
+	/* =================RF Gain */
+	btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0xef, 0xfffff, 0x02000);
+	if (agc_table_en) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], Agc Table On!\n");
+		BTC_TRACE(trace_buf);
+		btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x3b, 0xfffff,
+					  0x38fff);
+		btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x3b, 0xfffff,
+					  0x38ffe);
+	} else {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], Agc Table Off!\n");
+		BTC_TRACE(trace_buf);
+		btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x3b, 0xfffff,
+					  0x380c3);
+		btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x3b, 0xfffff,
+					  0x28ce6);
+	}
+	btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0xef, 0xfffff, 0x0);
+
+	btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0xed, 0xfffff, 0x1);
+	if (agc_table_en) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], Agc Table On!\n");
+		BTC_TRACE(trace_buf);
+		btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x40, 0xfffff,
+					  0x38fff);
+		btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x40, 0xfffff,
+					  0x38ffe);
+	} else {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], Agc Table Off!\n");
+		BTC_TRACE(trace_buf);
+		btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x40, 0xfffff,
+					  0x380c3);
+		btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x40, 0xfffff,
+					  0x28ce6);
+	}
+	btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0xed, 0xfffff, 0x0);
+
+	/* set rssi_adjust_val for wifi module. */
+	if (agc_table_en)
+		rssi_adjust_val = 8;
+	btcoexist->btc_set(btcoexist, BTC_SET_U1_RSSI_ADJ_VAL_FOR_AGC_TABLE_ON,
+			   &rssi_adjust_val);
+}
+
+void halbtc8723b2ant_agc_table(IN struct btc_coexist *btcoexist,
+			       IN boolean force_exec, IN boolean agc_table_en)
+{
+	coex_dm->cur_agc_table_en = agc_table_en;
+
+	if (!force_exec) {
+		if (coex_dm->pre_agc_table_en == coex_dm->cur_agc_table_en)
+			return;
+	}
+	halbtc8723b2ant_set_agc_table(btcoexist, agc_table_en);
+
+	coex_dm->pre_agc_table_en = coex_dm->cur_agc_table_en;
+}
+
+void halbtc8723b2ant_sw_mechanism1(IN struct btc_coexist *btcoexist,
+			   IN boolean shrink_rx_lpf, IN boolean low_penalty_ra,
+			   IN boolean limited_dig, IN boolean bt_lna_constrain)
+{
+	/*
+	u32	wifi_bw;
+
+	btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw);
+
+	if(BTC_WIFI_BW_HT40 != wifi_bw)
+	{
+		if (shrink_rx_lpf)
+			shrink_rx_lpf = false;
+	}
+	*/
+
+	/* halbtc8723b2ant_rf_shrink(btcoexist, NORMAL_EXEC, shrink_rx_lpf); */
+	halbtc8723b2ant_low_penalty_ra(btcoexist, NORMAL_EXEC, low_penalty_ra);
+}
+
+void halbtc8723b2ant_sw_mechanism2(IN struct btc_coexist *btcoexist,
+			   IN boolean agc_table_shift, IN boolean adc_back_off,
+			   IN boolean sw_dac_swing, IN u32 dac_swing_lvl)
+{
+	/* halbtc8723b2ant_agc_table(btcoexist, NORMAL_EXEC, agc_table_shift); */
+	/* halbtc8723b2ant_adc_back_off(btcoexist, NORMAL_EXEC, adc_back_off); */
+	/* halbtc8723b2ant_dac_swing(btcoexist, NORMAL_EXEC, sw_dac_swing, dac_swing_lvl); */
+}
+
+void halbtc8723b2ant_set_coex_table(IN struct btc_coexist *btcoexist,
+	    IN u32 val0x6c0, IN u32 val0x6c4, IN u32 val0x6c8, IN u8 val0x6cc)
+{
+	btcoexist->btc_write_4byte(btcoexist, 0x6c0, val0x6c0);
+
+	btcoexist->btc_write_4byte(btcoexist, 0x6c4, val0x6c4);
+
+	btcoexist->btc_write_4byte(btcoexist, 0x6c8, val0x6c8);
+
+	btcoexist->btc_write_1byte(btcoexist, 0x6cc, val0x6cc);
+}
+
+void halbtc8723b2ant_coex_table(IN struct btc_coexist *btcoexist,
+			IN boolean force_exec, IN u32 val0x6c0, IN u32 val0x6c4,
+				IN u32 val0x6c8, IN u8 val0x6cc)
+{
+	coex_dm->cur_val0x6c0 = val0x6c0;
+	coex_dm->cur_val0x6c4 = val0x6c4;
+	coex_dm->cur_val0x6c8 = val0x6c8;
+	coex_dm->cur_val0x6cc = val0x6cc;
+
+	if (!force_exec) {
+		if ((coex_dm->pre_val0x6c0 == coex_dm->cur_val0x6c0) &&
+		    (coex_dm->pre_val0x6c4 == coex_dm->cur_val0x6c4) &&
+		    (coex_dm->pre_val0x6c8 == coex_dm->cur_val0x6c8) &&
+		    (coex_dm->pre_val0x6cc == coex_dm->cur_val0x6cc))
+			return;
+	}
+	halbtc8723b2ant_set_coex_table(btcoexist, val0x6c0, val0x6c4, val0x6c8,
+				       val0x6cc);
+
+	coex_dm->pre_val0x6c0 = coex_dm->cur_val0x6c0;
+	coex_dm->pre_val0x6c4 = coex_dm->cur_val0x6c4;
+	coex_dm->pre_val0x6c8 = coex_dm->cur_val0x6c8;
+	coex_dm->pre_val0x6cc = coex_dm->cur_val0x6cc;
+}
+
+void halbtc8723b2ant_coex_table_with_type(IN struct btc_coexist *btcoexist,
+		IN boolean force_exec, IN u8 type)
+{
+	coex_sta->coex_table_type = type;
+
+	switch (type) {
+	case 0:
+		halbtc8723b2ant_coex_table(btcoexist, force_exec,
+				   0x55555555, 0x55555555, 0xffffff, 0x3);
+		break;
+	case 1:
+		halbtc8723b2ant_coex_table(btcoexist, force_exec,
+				   0x55555555, 0x5afa5afa, 0xffffff, 0x3);
+		break;
+	case 2:
+		halbtc8723b2ant_coex_table(btcoexist, force_exec,
+				   0x5ada5ada, 0x5ada5ada, 0xffffff, 0x3);
+		break;
+	case 3:
+		halbtc8723b2ant_coex_table(btcoexist, force_exec,
+				   0xaaaaaaaa, 0xaaaaaaaa, 0xffffff, 0x3);
+		break;
+	case 4:
+		halbtc8723b2ant_coex_table(btcoexist, force_exec,
+				   0xffffffff, 0xffffffff, 0xffffff, 0x3);
+		break;
+	case 5:
+		halbtc8723b2ant_coex_table(btcoexist, force_exec,
+				   0x5fff5fff, 0x5fff5fff, 0xffffff, 0x3);
+		break;
+	case 6:
+		halbtc8723b2ant_coex_table(btcoexist, force_exec,
+				   0x55ff55ff, 0x5a5a5a5a, 0xffffff, 0x3);
+		break;
+	case 7:
+		halbtc8723b2ant_coex_table(btcoexist, force_exec,
+				   0x55dd55dd, 0x5ada5ada, 0xffffff, 0x3);
+		break;
+	case 8:
+		halbtc8723b2ant_coex_table(btcoexist, force_exec,
+				   0x55dd55dd, 0x5ada5ada, 0xffffff, 0x3);
+		break;
+	case 9:
+		halbtc8723b2ant_coex_table(btcoexist, force_exec,
+				   0x55dd55dd, 0x5ada5ada, 0xffffff, 0x3);
+		break;
+	case 10:
+		halbtc8723b2ant_coex_table(btcoexist, force_exec,
+				   0x55dd55dd, 0x5ada5ada, 0xffffff, 0x3);
+		break;
+	case 11:
+		halbtc8723b2ant_coex_table(btcoexist, force_exec,
+				   0x55dd55dd, 0x5ada5ada, 0xffffff, 0x3);
+		break;
+	case 12:
+		halbtc8723b2ant_coex_table(btcoexist, force_exec,
+				   0x55dd55dd, 0x5ada5ada, 0xffffff, 0x3);
+		break;
+	case 13:
+		halbtc8723b2ant_coex_table(btcoexist, force_exec,
+				   0x5fff5fff, 0xaaaaaaaa, 0xffffff, 0x3);
+		break;
+	case 14:
+		halbtc8723b2ant_coex_table(btcoexist, force_exec,
+				   0x5fff5fff, 0x5ada5ada, 0xffffff, 0x3);
+		break;
+	case 15:
+		halbtc8723b2ant_coex_table(btcoexist, force_exec,
+				   0x55dd55dd, 0xaaaaaaaa, 0xffffff, 0x3);
+		break;
+	default:
+		break;
+	}
+}
+
+void halbtc8723b2ant_set_fw_ignore_wlan_act(IN struct btc_coexist *btcoexist,
+		IN boolean enable)
+{
+	u8			h2c_parameter[1] = {0};
+
+	if (enable)
+		h2c_parameter[0] |= BIT(0);		/* function enable */
+
+	btcoexist->btc_fill_h2c(btcoexist, 0x63, 1, h2c_parameter);
+}
+
+void halbtc8723b2ant_ignore_wlan_act(IN struct btc_coexist *btcoexist,
+				     IN boolean force_exec, IN boolean enable)
+{
+	coex_dm->cur_ignore_wlan_act = enable;
+
+	if (!force_exec) {
+		if (coex_dm->pre_ignore_wlan_act ==
+		    coex_dm->cur_ignore_wlan_act)
+			return;
+	}
+	halbtc8723b2ant_set_fw_ignore_wlan_act(btcoexist, enable);
+
+	coex_dm->pre_ignore_wlan_act = coex_dm->cur_ignore_wlan_act;
+}
+
+void halbtc8723b2ant_set_lps_rpwm(IN struct btc_coexist *btcoexist,
+				  IN u8 lps_val, IN u8 rpwm_val)
+{
+	u8	lps = lps_val;
+	u8	rpwm = rpwm_val;
+
+	btcoexist->btc_set(btcoexist, BTC_SET_U1_LPS_VAL, &lps);
+	btcoexist->btc_set(btcoexist, BTC_SET_U1_RPWM_VAL, &rpwm);
+}
+
+void halbtc8723b2ant_lps_rpwm(IN struct btc_coexist *btcoexist,
+		      IN boolean force_exec, IN u8 lps_val, IN u8 rpwm_val)
+{
+	coex_dm->cur_lps = lps_val;
+	coex_dm->cur_rpwm = rpwm_val;
+
+	if (!force_exec) {
+		if ((coex_dm->pre_lps == coex_dm->cur_lps) &&
+		    (coex_dm->pre_rpwm == coex_dm->cur_rpwm))
+			return;
+	}
+	halbtc8723b2ant_set_lps_rpwm(btcoexist, lps_val, rpwm_val);
+
+	coex_dm->pre_lps = coex_dm->cur_lps;
+	coex_dm->pre_rpwm = coex_dm->cur_rpwm;
+}
+
+void halbtc8723b2ant_ps_tdma_check_for_power_save_state(
+	IN struct btc_coexist *btcoexist, IN boolean new_ps_state)
+{
+	u8	lps_mode = 0x0;
+	u8	h2c_parameter[5] = {0x0, 0, 0, 48, 0};
+
+	btcoexist->btc_get(btcoexist, BTC_GET_U1_LPS_MODE, &lps_mode);
+
+	if (lps_mode) {	/* already under LPS state */
+		if (new_ps_state) {
+			/* keep state under LPS, do nothing. */
+		} else {
+			/* will leave LPS state, turn off psTdma first */
+			/* halbtc8723b2ant_ps_tdma(btcoexist, NORMAL_EXEC, false,
+						1); */
+			btcoexist->btc_fill_h2c(btcoexist, 0x60, 5,
+				h2c_parameter);
+		}
+	} else {					/* NO PS state */
+		if (new_ps_state) {
+			/* will enter LPS state, turn off psTdma first */
+			/* halbtc8723b2ant_ps_tdma(btcoexist, NORMAL_EXEC, false,
+						1); */
+			btcoexist->btc_fill_h2c(btcoexist, 0x60, 5,
+				h2c_parameter);
+		} else {
+			/* keep state under NO PS state, do nothing. */
+		}
+	}
+}
+
+void halbtc8723b2ant_power_save_state(IN struct btc_coexist *btcoexist,
+			      IN u8 ps_type, IN u8 lps_val, IN u8 rpwm_val)
+{
+	boolean		low_pwr_disable = false;
+
+	switch (ps_type) {
+	case BTC_PS_WIFI_NATIVE:
+		/* recover to original 32k low power setting */
+		low_pwr_disable = false;
+		btcoexist->btc_set(btcoexist,
+				   BTC_SET_ACT_DISABLE_LOW_POWER,
+				   &low_pwr_disable);
+		btcoexist->btc_set(btcoexist, BTC_SET_ACT_NORMAL_LPS,
+				   NULL);
+		coex_sta->force_lps_on = false;
+		break;
+	case BTC_PS_LPS_ON:
+		halbtc8723b2ant_ps_tdma_check_for_power_save_state(
+			btcoexist, true);
+		halbtc8723b2ant_lps_rpwm(btcoexist, NORMAL_EXEC,
+					 lps_val, rpwm_val);
+		/* when coex force to enter LPS, do not enter 32k low power. */
+		low_pwr_disable = true;
+		btcoexist->btc_set(btcoexist,
+				   BTC_SET_ACT_DISABLE_LOW_POWER,
+				   &low_pwr_disable);
+		/* power save must executed before psTdma.			 */
+		btcoexist->btc_set(btcoexist, BTC_SET_ACT_ENTER_LPS,
+				   NULL);
+		coex_sta->force_lps_on = true;
+		break;
+	case BTC_PS_LPS_OFF:
+		halbtc8723b2ant_ps_tdma_check_for_power_save_state(
+			btcoexist, false);
+		btcoexist->btc_set(btcoexist, BTC_SET_ACT_LEAVE_LPS,
+				   NULL);
+		coex_sta->force_lps_on = false;
+		break;
+	default:
+		break;
+	}
+}
+
+
+void halbtc8723b2ant_set_fw_pstdma(IN struct btc_coexist *btcoexist,
+	   IN u8 byte1, IN u8 byte2, IN u8 byte3, IN u8 byte4, IN u8 byte5)
+{
+	u8			h2c_parameter[5] = {0};
+	u8			real_byte1 = byte1, real_byte5 = byte5;
+	boolean		ap_enable = false;
+
+	if ((coex_sta->a2dp_exist) && (coex_sta->hid_exist))
+		byte5 = byte5 | 0x1;
+
+
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_AP_MODE_ENABLE,
+			   &ap_enable);
+
+	if (ap_enable) {
+		if (byte1 & BIT(4) && !(byte1 & BIT(5))) {
+			real_byte1 &= ~BIT(4);
+			real_byte1 |= BIT(5);
+
+			real_byte5 |= BIT(5);
+			real_byte5 &= ~BIT(6);
+
+			halbtc8723b2ant_power_save_state(btcoexist,
+				BTC_PS_WIFI_NATIVE, 0x0, 0x0);
+		}
+	} else if (byte1 & BIT(4) && !(byte1 & BIT(5))) {
+			halbtc8723b2ant_power_save_state(btcoexist,
+				BTC_PS_LPS_ON, 0x50, 0x4);
+
+	} else {
+			halbtc8723b2ant_power_save_state(btcoexist,
+				BTC_PS_WIFI_NATIVE, 0x0, 0x0);
+	}
+
+	h2c_parameter[0] = byte1;
+	h2c_parameter[1] = byte2;
+	h2c_parameter[2] = byte3;
+	h2c_parameter[3] = byte4;
+	h2c_parameter[4] = byte5;
+
+	coex_dm->ps_tdma_para[0] = byte1;
+	coex_dm->ps_tdma_para[1] = byte2;
+	coex_dm->ps_tdma_para[2] = byte3;
+	coex_dm->ps_tdma_para[3] = byte4;
+	coex_dm->ps_tdma_para[4] = byte5;
+
+	btcoexist->btc_fill_h2c(btcoexist, 0x60, 5, h2c_parameter);
+}
+
+void halbtc8723b2ant_ps_tdma(IN struct btc_coexist *btcoexist,
+		     IN boolean force_exec, IN boolean turn_on, IN u8 type)
+{
+	static u8	prewifi_rssi_state = BTC_RSSI_STATE_LOW;
+	static u8	pre_bt_rssi_state = BTC_RSSI_STATE_LOW;
+	u8			wifi_rssi_state1,  bt_rssi_state;
+	s8			wifi_duration_adjust = 0x0;
+	u8			psTdmaByte4Modify = 0x0;
+	struct  btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
+
+	wifi_rssi_state1 = halbtc8723b2ant_wifi_rssi_state(btcoexist,
+		&prewifi_rssi_state, 2, BT_8723B_2ANT_WIFI_RSSI_COEXSWITCH_THRES
+			   - coex_dm->switch_thres_offset, 0);
+	bt_rssi_state = halbtc8723b2ant_bt_rssi_state(&pre_bt_rssi_state, 2,
+			BT_8723B_2ANT_BT_RSSI_COEXSWITCH_THRES -
+			coex_dm->switch_thres_offset, 0);
+
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+		    "[BTCoex], %s turn %s PS TDMA, type=%d\n",
+		(force_exec ? "force to" : ""), (turn_on ? "ON" : "OFF"), type);
+	BTC_TRACE(trace_buf);
+	coex_dm->cur_ps_tdma_on = turn_on;
+	coex_dm->cur_ps_tdma = type;
+
+	if (!(BTC_RSSI_HIGH(wifi_rssi_state1) &&
+	      BTC_RSSI_HIGH(bt_rssi_state)) && turn_on)
+		/* if (halbtc8723b2ant_CoexSwitchThresCheck(btcoexist) &&  turn_on) */
+	{
+		type = type + 100; /* for WiFi RSSI low or BT RSSI low */
+		coex_dm->is_switch_to_1dot5_ant = true;
+	} else
+		coex_dm->is_switch_to_1dot5_ant = false;
+
+
+	if (!force_exec) {
+		if ((coex_dm->pre_ps_tdma_on == coex_dm->cur_ps_tdma_on) &&
+		    (coex_dm->pre_ps_tdma == coex_dm->cur_ps_tdma))
+			return;
+	}
+
+	if (coex_sta->scan_ap_num <= 5) {
+		if (coex_sta->a2dp_bit_pool >= 45)
+			wifi_duration_adjust = -15;
+		else if (coex_sta->a2dp_bit_pool >= 35)
+			wifi_duration_adjust = -10;
+		else
+			wifi_duration_adjust = 5;
+	} else  if (coex_sta->scan_ap_num <= 20) {
+		if (coex_sta->a2dp_bit_pool >= 45)
+			wifi_duration_adjust = -15;
+		else if (coex_sta->a2dp_bit_pool >= 35)
+			wifi_duration_adjust = -10;
+		else
+			wifi_duration_adjust = 0;
+	} else if (coex_sta->scan_ap_num <= 40) {
+		if (coex_sta->a2dp_bit_pool >= 45)
+			wifi_duration_adjust = -15;
+		else if (coex_sta->a2dp_bit_pool >= 35)
+			wifi_duration_adjust = -10;
+		else
+			wifi_duration_adjust = -5;
+	} else {
+		if (coex_sta->a2dp_bit_pool >= 45)
+			wifi_duration_adjust = -15;
+		else if (coex_sta->a2dp_bit_pool >= 35)
+			wifi_duration_adjust = -10;
+		else
+			wifi_duration_adjust = -10;
+	}
+
+	if ((bt_link_info->slave_role == true)	&& (bt_link_info->a2dp_exist))
+		psTdmaByte4Modify =
+			0x1;  /* 0x778 = 0x1 at wifi slot (no blocking BT Low-Pri pkts) */
+
+
+	if (turn_on) {
+		switch (type) {
+		case 1:
+		default:
+			halbtc8723b2ant_set_fw_pstdma(btcoexist, 0xe3,
+				      0x3c + wifi_duration_adjust, 0x03, 0xf1,
+						      0x90 | psTdmaByte4Modify);
+			break;
+		case 2:
+			halbtc8723b2ant_set_fw_pstdma(btcoexist, 0xe3,
+				      0x2d + wifi_duration_adjust, 0x03, 0xf1,
+						      0x90 | psTdmaByte4Modify);
+			break;
+		case 3:
+			halbtc8723b2ant_set_fw_pstdma(btcoexist, 0xe3,
+						      0x1c, 0x3, 0xf1,  0x90 |
+						      psTdmaByte4Modify);
+			break;
+		case 4:
+			halbtc8723b2ant_set_fw_pstdma(btcoexist, 0xe3,
+						      0x10, 0x03, 0xf1,  0x90 |
+						      psTdmaByte4Modify);
+			break;
+		case 5:
+			halbtc8723b2ant_set_fw_pstdma(btcoexist, 0xe3,
+				      0x3c + wifi_duration_adjust, 0x3, 0x70,
+						      0x90 | psTdmaByte4Modify);
+			break;
+		case 6:
+			halbtc8723b2ant_set_fw_pstdma(btcoexist, 0xe3,
+				      0x2d + wifi_duration_adjust, 0x3, 0x70,
+						      0x90 | psTdmaByte4Modify);
+			break;
+		case 7:
+			halbtc8723b2ant_set_fw_pstdma(btcoexist, 0xe3,
+						      0x1c, 0x3, 0x70,  0x90 |
+						      psTdmaByte4Modify);
+			break;
+		case 8:
+			halbtc8723b2ant_set_fw_pstdma(btcoexist, 0xa3,
+						      0x10, 0x3, 0x70,  0x90 |
+						      psTdmaByte4Modify);
+			break;
+		case 9:
+			/*
+				halbtc8723b2ant_set_fw_pstdma(btcoexist, 0xe3,
+					      0x3c + wifi_duration_adjust, 0x03, 0xf1,
+							      0x90 | psTdmaByte4Modify);
+			*/
+			/* Bryant Modify for BT no-profile busy case */
+			halbtc8723b2ant_set_fw_pstdma(btcoexist, 0xe3,
+				      0x3c + wifi_duration_adjust, 0x03, 0xf1,
+						      0x91);
+
+			break;
+		case 10:
+			halbtc8723b2ant_set_fw_pstdma(btcoexist, 0xe3,
+				      0x2d + wifi_duration_adjust, 0x03, 0xf1,
+						      0x90 | psTdmaByte4Modify);
+			break;
+		case 11:
+			halbtc8723b2ant_set_fw_pstdma(btcoexist, 0xe3,
+						      0x1c, 0x3, 0xf1,  0x90 |
+						      psTdmaByte4Modify);
+			break;
+		case 12:
+			halbtc8723b2ant_set_fw_pstdma(btcoexist, 0xe3,
+						      0x10, 0x3, 0xf1,  0x90 |
+						      psTdmaByte4Modify);
+			break;
+		case 13:
+			/*
+				halbtc8723b2ant_set_fw_pstdma(btcoexist, 0xe3,
+					      0x3c + wifi_duration_adjust, 0x3, 0x70,
+							      0x90 | psTdmaByte4Modify);
+			*/
+			/* Bryant Modify for BT no-profile busy case */
+			halbtc8723b2ant_set_fw_pstdma(btcoexist, 0xe3,
+				      0x3c + wifi_duration_adjust, 0x3, 0x70,
+						      0x91);
+			break;
+		case 14:
+			halbtc8723b2ant_set_fw_pstdma(btcoexist, 0xe3,
+				      0x2d + wifi_duration_adjust, 0x3, 0x70,
+						      0x90 | psTdmaByte4Modify);
+			break;
+		case 15:
+			halbtc8723b2ant_set_fw_pstdma(btcoexist, 0xe3,
+						      0x1c, 0x3, 0x70,  0x90 |
+						      psTdmaByte4Modify);
+			break;
+		case 16:
+			halbtc8723b2ant_set_fw_pstdma(btcoexist, 0xe3,
+						      0x10, 0x3, 0x70,  0x90 |
+						      psTdmaByte4Modify);
+			break;
+		case 17:
+			halbtc8723b2ant_set_fw_pstdma(btcoexist, 0xa3,
+						      0x2f, 0x2f, 0x60, 0x90);
+			break;
+		case 18:
+			halbtc8723b2ant_set_fw_pstdma(btcoexist, 0xe3,
+						      0x5, 0x5, 0xe1, 0x90);
+			break;
+		case 19:
+			halbtc8723b2ant_set_fw_pstdma(btcoexist, 0xe3,
+						      0x25, 0x25, 0xe1, 0x90);
+			break;
+		case 20:
+			halbtc8723b2ant_set_fw_pstdma(btcoexist, 0xe3,
+						      0x25, 0x25, 0x60, 0x90);
+			break;
+		case 21:
+			halbtc8723b2ant_set_fw_pstdma(btcoexist, 0xe3,
+						      0x15, 0x03, 0x70, 0x90);
+			break;
+		case 22:
+			halbtc8723b2ant_set_fw_pstdma(btcoexist, 0xe3,
+						      0x35, 0x03, 0xf1, 0x90);
+			break;
+		case 23:
+			halbtc8723b2ant_set_fw_pstdma(btcoexist, 0xe3,
+						      0x35, 0x03, 0x71, 0x10);
+			break;
+
+		case 25:
+			halbtc8723b2ant_set_fw_pstdma(btcoexist, 0xe3,
+						      0x30, 0x03, 0x71, 0x10);
+			break;
+
+		case 33:
+			halbtc8723b2ant_set_fw_pstdma(btcoexist, 0xe3,
+						      0x1c, 0x3, 0xf1,  0x91);
+
+			break;
+		case 71:
+			halbtc8723b2ant_set_fw_pstdma(btcoexist, 0xe3,
+				      0x3c + wifi_duration_adjust, 0x03, 0xf1,
+						      0x90);
+			break;
+		case 101:
+		case 105:
+		case 113:
+		case 171:
+			halbtc8723b2ant_set_fw_pstdma(btcoexist, 0xd3,
+				      0x3a + wifi_duration_adjust, 0x03, 0x70,
+						      0x50 | psTdmaByte4Modify);
+			break;
+		case 102:
+		case 106:
+		case 110:
+		case 114:
+			halbtc8723b2ant_set_fw_pstdma(btcoexist, 0xd3,
+				      0x2d + wifi_duration_adjust, 0x03, 0x70,
+						      0x50 | psTdmaByte4Modify);
+			break;
+		case 103:
+		case 107:
+		case 111:
+		case 115:
+			halbtc8723b2ant_set_fw_pstdma(btcoexist, 0xd3,
+						      0x1c, 0x03, 0x70, 0x50 |
+						      psTdmaByte4Modify);
+			break;
+		case 104:
+		case 108:
+		case 112:
+		case 116:
+			halbtc8723b2ant_set_fw_pstdma(btcoexist, 0xd3,
+						      0x10, 0x03, 0x70, 0x50 |
+						      psTdmaByte4Modify);
+			break;
+		case 109:
+			halbtc8723b2ant_set_fw_pstdma(btcoexist, 0xe3,
+						      0x3c, 0x03, 0xf1, 0x90 |
+						      psTdmaByte4Modify);
+			break;
+		/* case 113:
+			halbtc8723b2ant_set_fw_pstdma(btcoexist, 0xe3,
+						      0x3c, 0x03, 0x70, 0x90 |
+						      psTdmaByte4Modify);
+			break; */
+		case 121:
+			halbtc8723b2ant_set_fw_pstdma(btcoexist, 0xe3,
+						      0x15, 0x03, 0x70, 0x90 |
+						      psTdmaByte4Modify);
+			break;
+		case 122:
+			halbtc8723b2ant_set_fw_pstdma(btcoexist, 0xe3,
+						      0x35, 0x03, 0x71, 0x11);
+			break;
+		case 123:
+			halbtc8723b2ant_set_fw_pstdma(btcoexist, 0xe3,
+						      0x35, 0x03, 0x71, 0x10);
+			break;
+		case 125:
+			halbtc8723b2ant_set_fw_pstdma(btcoexist, 0xd3,
+						      0x30, 0x03, 0x70, 0x51);
+			break;
+
+		case 133:
+			halbtc8723b2ant_set_fw_pstdma(btcoexist, 0xd3,
+						      0x1c, 0x3, 0x70,  0x51);
+
+			break;
+		}
+	} else {
+		/* disable PS tdma */
+		switch (type) {
+		case 0:
+			halbtc8723b2ant_set_fw_pstdma(btcoexist, 0x0,
+						      0x0, 0x0, 0x40, 0x0);
+			break;
+		case 1:
+			halbtc8723b2ant_set_fw_pstdma(btcoexist, 0x0,
+						      0x0, 0x0, 0x48, 0x0);
+			break;
+		default:
+			halbtc8723b2ant_set_fw_pstdma(btcoexist, 0x0,
+						      0x0, 0x0, 0x40, 0x0);
+			break;
+		}
+	}
+
+	/* update pre state */
+	coex_dm->pre_ps_tdma_on = coex_dm->cur_ps_tdma_on;
+	coex_dm->pre_ps_tdma = coex_dm->cur_ps_tdma;
+}
+
+
+void halbtc8723b2ant_set_ant_path(IN struct btc_coexist *btcoexist,
+	  IN u8 ant_pos_type, IN boolean init_hwcfg, IN boolean wifi_off)
+{
+	struct  btc_board_info *board_info = &btcoexist->board_info;
+	u32			fw_ver = 0, u32tmp = 0, cnt_bt_cal_chk = 0;
+	boolean			pg_ext_switch = false;
+	boolean			use_ext_switch = false;
+	u8			h2c_parameter[2] = {0};
+	u32				u32tmp_1[4];
+	boolean		is_fw_ready;
+
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_EXT_SWITCH, &pg_ext_switch);
+	btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_FW_VER,
+			   &fw_ver);	/* [31:16]=fw ver, [15:0]=fw sub ver */
+
+	if ((fw_ver > 0 && fw_ver < 0xc0000) || pg_ext_switch)
+		use_ext_switch = true;
+
+	if (init_hwcfg) {
+		btcoexist->btc_write_1byte_bitmask(btcoexist, 0x39, 0x8, 0x1);
+		btcoexist->btc_write_1byte(btcoexist, 0x974, 0xff);
+		btcoexist->btc_write_1byte_bitmask(btcoexist, 0x944, 0x3, 0x3);
+		btcoexist->btc_write_1byte(btcoexist, 0x930, 0x77);
+		btcoexist->btc_write_1byte_bitmask(btcoexist, 0x67, 0x20, 0x1);
+
+		if (fw_ver >= 0x180000) {
+			/* Use H2C to set GNT_BT to High to avoid A2DP click */
+			h2c_parameter[0] = 1;
+			btcoexist->btc_fill_h2c(btcoexist, 0x6E, 1,
+						h2c_parameter);
+
+			cnt_bt_cal_chk = 0;
+			while (1) {
+				btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_FW_READY, &is_fw_ready);
+				if (is_fw_ready == false)
+					break;
+
+				if (btcoexist->btc_read_1byte(btcoexist,
+							      0x765) == 0x18)
+					break;
+
+				cnt_bt_cal_chk++;
+				if (cnt_bt_cal_chk > 20)
+					break;
+			}
+		} else
+			btcoexist->btc_write_1byte(btcoexist, 0x765, 0x18);
+		u32tmp_1[0] = btcoexist->btc_read_4byte(btcoexist, 0x948);
+		if ((u32tmp_1[0] == 0x40) || (u32tmp_1[0] == 0x240))
+			btcoexist->btc_write_4byte(btcoexist, 0x948,
+						   u32tmp_1[0]);
+		else
+			btcoexist->btc_write_4byte(btcoexist, 0x948, 0x0);
+
+		btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1, 0xfffff,
+					  0x0); /* WiFi TRx Mask off */
+		/* remove due to interrupt is disabled that polling c2h will fail and delay 100ms. */
+		/* btcoexist->btc_set_bt_reg(btcoexist, BTC_BT_REG_RF, 0x3c, 0x01); */ /*BT TRx Mask off */
+
+		if (board_info->btdm_ant_pos == BTC_ANTENNA_AT_MAIN_PORT) {
+			/* tell firmware "no antenna inverse" */
+			h2c_parameter[0] = 0;
+		} else {
+			/* tell firmware "antenna inverse" */
+			h2c_parameter[0] = 1;
+		}
+
+		if (use_ext_switch) {
+			/* ext switch type */
+			h2c_parameter[1] = 1;
+		} else {
+			/* int switch type */
+			h2c_parameter[1] = 0;
+		}
+		btcoexist->btc_fill_h2c(btcoexist, 0x65, 2, h2c_parameter);
+	} else {
+		if (fw_ver >= 0x180000) {
+			/* Use H2C to set GNT_BT to "Control by PTA"*/
+			h2c_parameter[0] = 0;
+			btcoexist->btc_fill_h2c(btcoexist, 0x6E, 1,
+						h2c_parameter);
+
+			cnt_bt_cal_chk = 0;
+			while (1) {
+				btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_FW_READY, &is_fw_ready);
+				if (is_fw_ready == false)
+					break;
+
+				if (btcoexist->btc_read_1byte(btcoexist,
+							      0x765) == 0x0)
+					break;
+
+				cnt_bt_cal_chk++;
+				if (cnt_bt_cal_chk > 20)
+					break;
+			}
+		} else
+			btcoexist->btc_write_1byte(btcoexist, 0x765, 0x0);
+	}
+
+	/* ext switch setting */
+	if (use_ext_switch) {
+		if (init_hwcfg) {
+			/* 0x4c[23]=0, 0x4c[24]=1  Antenna control by WL/BT */
+			u32tmp = btcoexist->btc_read_4byte(btcoexist, 0x4c);
+			u32tmp &= ~BIT(23);
+			u32tmp |= BIT(24);
+			btcoexist->btc_write_4byte(btcoexist, 0x4c, u32tmp);
+		}
+		u32tmp_1[0] = btcoexist->btc_read_4byte(btcoexist, 0x948);
+		if ((u32tmp_1[0] == 0x40) || (u32tmp_1[0] == 0x240))
+			btcoexist->btc_write_4byte(btcoexist, 0x948,
+						   u32tmp_1[0]);
+		else
+			btcoexist->btc_write_4byte(btcoexist, 0x948, 0x0);
+
+		switch (ant_pos_type) {
+		case BTC_ANT_WIFI_AT_MAIN:
+			btcoexist->btc_write_1byte_bitmask(btcoexist,
+							   0x92c, 0x3,
+					   0x1);	/* ext switch main at wifi */
+			break;
+		case BTC_ANT_WIFI_AT_AUX:
+			btcoexist->btc_write_1byte_bitmask(btcoexist,
+							   0x92c, 0x3,
+					   0x2);	/* ext switch aux at wifi */
+			break;
+		}
+	} else {	/* internal switch */
+		if (init_hwcfg) {
+			/* 0x4c[23]=0, 0x4c[24]=1  Antenna control by WL/BT */
+			u32tmp = btcoexist->btc_read_4byte(btcoexist, 0x4c);
+			u32tmp |= BIT(23);
+			u32tmp &= ~BIT(24);
+			btcoexist->btc_write_4byte(btcoexist, 0x4c, u32tmp);
+		}
+
+		btcoexist->btc_write_1byte_bitmask(btcoexist, 0x64, 0x1,
+			   0x0); /* fixed external switch S1->Main, S0->Aux */
+		switch (ant_pos_type) {
+		case BTC_ANT_WIFI_AT_MAIN:
+			u32tmp_1[0] = btcoexist->btc_read_4byte(btcoexist,
+								0x948);
+			if ((u32tmp_1[0] == 0x40) || (u32tmp_1[0] == 0x240))
+				btcoexist->btc_write_4byte(btcoexist, 0x948,
+							   u32tmp_1[0]);
+			else
+				btcoexist->btc_write_4byte(btcoexist, 0x948,
+							   0x0);
+			break;
+		case BTC_ANT_WIFI_AT_AUX:
+			u32tmp_1[0] = btcoexist->btc_read_4byte(btcoexist,
+								0x948);
+			if ((u32tmp_1[0] == 0x40) || (u32tmp_1[0] == 0x240))
+				btcoexist->btc_write_4byte(btcoexist, 0x948,
+							   u32tmp_1[0]);
+			else
+				btcoexist->btc_write_4byte(btcoexist, 0x948,
+							   0x280);
+			break;
+		}
+	}
+}
+#if 0
+boolean halbtc8723b2ant_CoexSwitchThresCheck(IN struct btc_coexist *btcoexist)
+{
+	static u8	prewifi_rssi_state = BTC_RSSI_STATE_LOW;
+	static u8	pre_bt_rssi_state = BTC_RSSI_STATE_LOW;
+	u8 wifi_rssi_state1, bt_rssi_state;
+	u32 vendor;
+	u8 offset = 0;
+
+	btcoexist->btc_get(btcoexist, BTC_GET_U4_VENDOR, &vendor);
+
+	/* if (vendor == BTC_VENDOR_LENOVO) */
+	/*	offset = 20; */
+
+	wifi_rssi_state1 = halbtc8723b2ant_wifi_rssi_state(btcoexist,
+		&prewifi_rssi_state, 2, BT_8723B_2ANT_WIFI_RSSI_COEXSWITCH_THRES
+			   - coex_dm->switch_thres_offset, 0);
+	bt_rssi_state = halbtc8723b2ant_bt_rssi_state(&pre_bt_rssi_state, 2,
+			BT_8723B_2ANT_BT_RSSI_COEXSWITCH_THRES -
+			coex_dm->switch_thres_offset, 0);
+
+	if (BTC_RSSI_LOW(wifi_rssi_state1) || BTC_RSSI_LOW(bt_rssi_state))
+		return true;
+
+	return false;
+}
+#endif
+
+
+void halbtc8723b2ant_coex_all_off(IN struct btc_coexist *btcoexist)
+{
+	/* fw all off */
+	halbtc8723b2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 1);
+	halbtc8723b2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6);
+	halbtc8723b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);
+
+	/* sw all off */
+	halbtc8723b2ant_sw_mechanism1(btcoexist, false, false, false, false);
+	halbtc8723b2ant_sw_mechanism2(btcoexist, false, false, false, 0x18);
+
+	/* hw all off */
+	/* btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1, 0xfffff, 0x0); */
+	halbtc8723b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0);
+}
+
+void halbtc8723b2ant_init_coex_dm(IN struct btc_coexist *btcoexist)
+{
+	/* force to reset coex mechanism */
+	halbtc8723b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0);
+
+	halbtc8723b2ant_ps_tdma(btcoexist, FORCE_EXEC, false, 1);
+	halbtc8723b2ant_fw_dac_swing_lvl(btcoexist, FORCE_EXEC, 6);
+	halbtc8723b2ant_dec_bt_pwr(btcoexist, FORCE_EXEC, 0);
+
+	halbtc8723b2ant_sw_mechanism1(btcoexist, false, false, false, false);
+	halbtc8723b2ant_sw_mechanism2(btcoexist, false, false, false, 0x18);
+
+	coex_sta->pop_event_cnt = 0;
+
+}
+
+void halbtc8723b2ant_action_bt_inquiry(IN struct btc_coexist *btcoexist)
+{
+	static u8	prewifi_rssi_state = BTC_RSSI_STATE_LOW,
+			prewifi_rssi_state1 = BTC_RSSI_STATE_LOW;
+	static u8	pre_bt_rssi_state = BTC_RSSI_STATE_LOW;
+	u8		wifi_rssi_state, wifi_rssi_state1, bt_rssi_state;
+	boolean	wifi_connected = false;
+	boolean	low_pwr_disable = true;
+	boolean		scan = false, link = false, roam = false;
+	boolean wifi_busy = false;
+
+
+	wifi_rssi_state = halbtc8723b2ant_wifi_rssi_state(btcoexist,
+			  &prewifi_rssi_state, 2, 15, 0);
+	wifi_rssi_state1 = halbtc8723b2ant_wifi_rssi_state(btcoexist,
+			   &prewifi_rssi_state1, 2,
+			   BT_8723B_2ANT_WIFI_RSSI_COEXSWITCH_THRES -
+			   coex_dm->switch_thres_offset, 0);
+	bt_rssi_state = halbtc8723b2ant_bt_rssi_state(&pre_bt_rssi_state, 2,
+			BT_8723B_2ANT_BT_RSSI_COEXSWITCH_THRES -
+			coex_dm->switch_thres_offset, 0);
+
+	btcoexist->btc_set(btcoexist, BTC_SET_ACT_DISABLE_LOW_POWER,
+			   &low_pwr_disable);
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED,
+			   &wifi_connected);
+
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_SCAN, &scan);
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_LINK, &link);
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_ROAM, &roam);
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy);
+
+
+	if (coex_sta->bt_abnormal_scan) {
+		halbtc8723b2ant_ps_tdma(btcoexist, NORMAL_EXEC, true,
+					23);
+		halbtc8723b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 3);
+	} else if (scan || link || roam) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], Wifi link process + BT Inq/Page!!\n");
+		BTC_TRACE(trace_buf);
+		halbtc8723b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC,
+						     7);
+		halbtc8723b2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 3);
+	} else if (wifi_connected) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], Wifi connected + BT Inq/Page!!\n");
+		BTC_TRACE(trace_buf);
+		halbtc8723b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC,
+						     7);
+
+		if (wifi_busy)
+			halbtc8723b2ant_ps_tdma(btcoexist, NORMAL_EXEC, true,
+						3);
+		else
+			halbtc8723b2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 33);
+	} else {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], Wifi no-link + BT Inq/Page!!\n");
+		BTC_TRACE(trace_buf);
+		halbtc8723b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0);
+		halbtc8723b2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 1);
+	}
+
+	halbtc8723b2ant_fw_dac_swing_lvl(btcoexist, FORCE_EXEC, 6);
+	halbtc8723b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);
+
+	halbtc8723b2ant_sw_mechanism1(btcoexist, false, false, false, false);
+	halbtc8723b2ant_sw_mechanism2(btcoexist, false, false, false, 0x18);
+	/*
+		coex_dm->need_recover0x948 = true;
+		coex_dm->backup0x948 = btcoexist->btc_read_4byte(btcoexist, 0x948);
+
+		halbtc8723b2ant_set_ant_path(btcoexist, BTC_ANT_WIFI_AT_AUX, false, false);
+	*/
+}
+
+
+void halbtc8723b2ant_action_wifi_link_process(IN struct btc_coexist *btcoexist)
+{
+	u32	u32tmp;
+	u8	u8tmpa, u8tmpb;
+
+	halbtc8723b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 15);
+	halbtc8723b2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 22);
+
+	halbtc8723b2ant_sw_mechanism1(btcoexist, false, false, false, false);
+	halbtc8723b2ant_sw_mechanism2(btcoexist, false, false, false, 0x18);
+
+
+	u32tmp = btcoexist->btc_read_4byte(btcoexist, 0x948);
+	u8tmpa = btcoexist->btc_read_1byte(btcoexist, 0x765);
+	u8tmpb = btcoexist->btc_read_1byte(btcoexist, 0x76e);
+
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+		"############# [BTCoex], 0x948=0x%x, 0x765=0x%x, 0x76e=0x%x\n",
+		    u32tmp,  u8tmpa, u8tmpb);
+	BTC_TRACE(trace_buf);
+}
+
+boolean halbtc8723b2ant_action_wifi_idle_process(IN struct btc_coexist
+		*btcoexist)
+{
+	static u8	prewifi_rssi_state = BTC_RSSI_STATE_LOW,
+			prewifi_rssi_state1 = BTC_RSSI_STATE_LOW;
+	static u8	pre_bt_rssi_state = BTC_RSSI_STATE_LOW;
+	u8		wifi_rssi_state, wifi_rssi_state1, bt_rssi_state;
+	u8		ap_num = 0;
+
+	wifi_rssi_state = halbtc8723b2ant_wifi_rssi_state(btcoexist,
+			  &prewifi_rssi_state, 2, 15, 0);
+	/* wifi_rssi_state1 = halbtc8723b2ant_wifi_rssi_state(btcoexist, 1, 2, BT_8723B_2ANT_WIFI_RSSI_COEXSWITCH_THRES-coex_dm->switch_thres_offset-coex_dm->switch_thres_offset, 0); */
+	wifi_rssi_state1 = halbtc8723b2ant_wifi_rssi_state(btcoexist,
+			   &prewifi_rssi_state1, 2,
+			   BT_8723B_2ANT_WIFI_RSSI_COEXSWITCH_THRES -
+		coex_dm->switch_thres_offset - coex_dm->switch_thres_offset, 0);
+	bt_rssi_state = halbtc8723b2ant_bt_rssi_state(&pre_bt_rssi_state, 2,
+			BT_8723B_2ANT_BT_RSSI_COEXSWITCH_THRES -
+		coex_dm->switch_thres_offset - coex_dm->switch_thres_offset, 0);
+
+	btcoexist->btc_get(btcoexist, BTC_GET_U1_AP_NUM, &ap_num);
+
+	/* define the office environment */
+	if (BTC_RSSI_HIGH(wifi_rssi_state1) &&
+	    (coex_sta->hid_exist == true) &&
+	    (coex_sta->a2dp_exist == true)) {
+
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			"[BTCoex], Wifi  idle process for BT HID+A2DP exist!!\n");
+		BTC_TRACE(trace_buf);
+
+		halbtc8723b2ant_dac_swing(btcoexist, NORMAL_EXEC, true, 0x6);
+		halbtc8723b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);
+
+		/* sw all off */
+		halbtc8723b2ant_sw_mechanism1(btcoexist, false, false, false,
+					      false);
+		halbtc8723b2ant_sw_mechanism2(btcoexist, false, false, false,
+					      0x18);
+
+		halbtc8723b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0);
+
+		halbtc8723b2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 1);
+
+		return true;
+	}
+
+	halbtc8723b2ant_dac_swing(btcoexist, NORMAL_EXEC, true, 0x18);
+	return false;
+}
+
+
+
+boolean halbtc8723b2ant_is_common_action(IN struct btc_coexist *btcoexist)
+{
+	boolean			common = false, wifi_connected = false, wifi_busy = false;
+	boolean			bt_hs_on = false, low_pwr_disable = false;
+	boolean			asus_8723b = false;
+
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on);
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED,
+			   &wifi_connected);
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy);
+
+	if (!wifi_connected) {
+		low_pwr_disable = false;
+		btcoexist->btc_set(btcoexist, BTC_SET_ACT_DISABLE_LOW_POWER,
+				   &low_pwr_disable);
+		halbtc8723b2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false,
+					   0x8);
+
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], Wifi non-connected idle!!\n");
+		BTC_TRACE(trace_buf);
+
+		btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1, 0xfffff,
+					  0x0);
+		halbtc8723b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0);
+
+		halbtc8723b2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 1);
+		halbtc8723b2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6);
+		halbtc8723b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);
+
+		halbtc8723b2ant_sw_mechanism1(btcoexist, false, false, false,
+					      false);
+		halbtc8723b2ant_sw_mechanism2(btcoexist, false, false, false,
+					      0x18);
+
+		common = true;
+	} else {
+		if (BT_8723B_2ANT_BT_STATUS_NON_CONNECTED_IDLE ==
+		    coex_dm->bt_status) {
+			low_pwr_disable = false;
+			btcoexist->btc_set(btcoexist,
+					   BTC_SET_ACT_DISABLE_LOW_POWER,
+					   &low_pwr_disable);
+			halbtc8723b2ant_limited_rx(btcoexist, NORMAL_EXEC,
+						   false, false, 0x8);
+
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				"[BTCoex], Wifi connected + BT non connected-idle!!\n");
+			BTC_TRACE(trace_buf);
+
+			btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1,
+						  0xfffff, 0x0);
+			halbtc8723b2ant_coex_table_with_type(btcoexist,
+							     NORMAL_EXEC, 0);
+
+			halbtc8723b2ant_ps_tdma(btcoexist, NORMAL_EXEC, false,
+						1);
+			halbtc8723b2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC,
+							 0xb);
+			halbtc8723b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);
+
+			halbtc8723b2ant_sw_mechanism1(btcoexist, false, false,
+						      false,
+						      false);
+			halbtc8723b2ant_sw_mechanism2(btcoexist, false, false,
+						      false, 0x18);
+
+			common = true;
+		} else if (BT_8723B_2ANT_BT_STATUS_CONNECTED_IDLE ==
+			   coex_dm->bt_status) {
+			low_pwr_disable = true;
+			btcoexist->btc_set(btcoexist,
+					   BTC_SET_ACT_DISABLE_LOW_POWER,
+					   &low_pwr_disable);
+
+			if (bt_hs_on)
+				return false;
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				"[BTCoex], Wifi connected + BT connected-idle!!\n");
+			BTC_TRACE(trace_buf);
+			halbtc8723b2ant_limited_rx(btcoexist, NORMAL_EXEC,
+						   false, false, 0x8);
+
+			btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1,
+						  0xfffff, 0x0);
+			halbtc8723b2ant_coex_table_with_type(btcoexist,
+							     NORMAL_EXEC, 0);
+			halbtc8723b2ant_ps_tdma(btcoexist, NORMAL_EXEC, false,
+						1);
+			halbtc8723b2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC,
+							 0xb);
+			halbtc8723b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);
+
+			halbtc8723b2ant_sw_mechanism1(btcoexist, true, false,
+						      false, false);
+			halbtc8723b2ant_sw_mechanism2(btcoexist, false, false,
+						      false, 0x18);
+
+			common = true;
+		} else {
+			low_pwr_disable = true;
+			btcoexist->btc_set(btcoexist,
+					   BTC_SET_ACT_DISABLE_LOW_POWER,
+					   &low_pwr_disable);
+
+			if (wifi_busy) {
+				BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+					"[BTCoex], Wifi Connected-Busy + BT Busy!!\n");
+				BTC_TRACE(trace_buf);
+				/* btcoexist->btc_get(btcoexist,
+					BTC_GET_BL_IS_ASUS_8723B, &asus_8723b);
+				if (!asus_8723b)
+					common = false;
+				else
+					common = halbtc8723b2ant_action_wifi_idle_process(
+							 btcoexist); */
+				common = false;
+			} else {
+				BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+					"[BTCoex], Wifi Connected-Idle + BT Busy!!\n");
+				BTC_TRACE(trace_buf);
+				/* common = false;	 */
+				common = halbtc8723b2ant_action_wifi_idle_process(
+						 btcoexist);
+			}
+		}
+	}
+
+	return common;
+}
+void halbtc8723b2ant_tdma_duration_adjust(IN struct btc_coexist *btcoexist,
+		IN boolean sco_hid, IN boolean tx_pause, IN u8 max_interval)
+{
+	static s32		up, dn, m, n, wait_count;
+	s32			result;   /* 0: no change, +1: increase WiFi duration, -1: decrease WiFi duration */
+	u8			retry_count = 0;
+
+	if (!coex_dm->auto_tdma_adjust) {
+		coex_dm->auto_tdma_adjust = true;
+		{
+			if (sco_hid) {
+				if (tx_pause) {
+					if (max_interval == 1) {
+						halbtc8723b2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 13);
+						coex_dm->ps_tdma_du_adj_type =
+							13;
+					} else if (max_interval == 2) {
+						halbtc8723b2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 14);
+						coex_dm->ps_tdma_du_adj_type =
+							14;
+					} else if (max_interval == 3) {
+						halbtc8723b2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 15);
+						coex_dm->ps_tdma_du_adj_type =
+							15;
+					} else {
+						halbtc8723b2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 15);
+						coex_dm->ps_tdma_du_adj_type =
+							15;
+					}
+				} else {
+					if (max_interval == 1) {
+						halbtc8723b2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 9);
+						coex_dm->ps_tdma_du_adj_type =
+							9;
+					} else if (max_interval == 2) {
+						halbtc8723b2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 10);
+						coex_dm->ps_tdma_du_adj_type =
+							10;
+					} else if (max_interval == 3) {
+						halbtc8723b2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 11);
+						coex_dm->ps_tdma_du_adj_type =
+							11;
+					} else {
+						halbtc8723b2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 11);
+						coex_dm->ps_tdma_du_adj_type =
+							11;
+					}
+				}
+			} else {
+				if (tx_pause) {
+					if (max_interval == 1) {
+						halbtc8723b2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 5);
+						coex_dm->ps_tdma_du_adj_type =
+							5;
+					} else if (max_interval == 2) {
+						halbtc8723b2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 6);
+						coex_dm->ps_tdma_du_adj_type =
+							6;
+					} else if (max_interval == 3) {
+						halbtc8723b2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 7);
+						coex_dm->ps_tdma_du_adj_type =
+							7;
+					} else {
+						halbtc8723b2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 7);
+						coex_dm->ps_tdma_du_adj_type =
+							7;
+					}
+				} else {
+					if (max_interval == 1) {
+						halbtc8723b2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 1);
+						coex_dm->ps_tdma_du_adj_type =
+							1;
+					} else if (max_interval == 2) {
+						halbtc8723b2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 2);
+						coex_dm->ps_tdma_du_adj_type =
+							2;
+					} else if (max_interval == 3) {
+						halbtc8723b2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 3);
+						coex_dm->ps_tdma_du_adj_type =
+							3;
+					} else {
+						halbtc8723b2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 3);
+						coex_dm->ps_tdma_du_adj_type =
+							3;
+					}
+				}
+			}
+		}
+		/* ============ */
+		up = 0;
+		dn = 0;
+		m = 1;
+		n = 3;
+		result = 0;
+		wait_count = 0;
+	} else {
+		/* acquire the BT TRx retry count from BT_Info byte2 */
+		retry_count = coex_sta->bt_retry_cnt;
+
+		if ((coex_sta->low_priority_tx) > 1050 ||
+		    (coex_sta->low_priority_rx) > 1250)
+			retry_count++;
+
+		result = 0;
+		wait_count++;
+
+		if (retry_count ==
+		    0) { /* no retry in the last 2-second duration */
+			up++;
+			dn--;
+
+			if (dn <= 0)
+				dn = 0;
+
+			if (up >= n) {	/* if retry count during continuous n*2 seconds is 0, enlarge WiFi duration */
+				wait_count = 0;
+				n = 3;
+				up = 0;
+				dn = 0;
+				result = 1;
+			}
+		} else if (retry_count <=
+			   3) {	/* <=3 retry in the last 2-second duration */
+			up--;
+			dn++;
+
+			if (up <= 0)
+				up = 0;
+
+			if (dn == 2) {/* if continuous 2 retry count(every 2 seconds) >0 and < 3, reduce WiFi duration */
+				if (wait_count <= 2)
+					m++; /* to avoid loop between the two levels */
+				else
+					m = 1;
+
+				if (m >= 20)  /* maximum of m = 20 ' will recheck if need to adjust wifi duration in maximum time interval 120 seconds */
+					m = 20;
+
+				n = 3 * m;
+				up = 0;
+				dn = 0;
+				wait_count = 0;
+				result = -1;
+			}
+		} else { /* retry count > 3, once retry count > 3, to reduce WiFi duration */
+			if (wait_count == 1)
+				m++; /* to avoid loop between the two levels */
+			else
+				m = 1;
+
+			if (m >= 20)  /* maximum of m = 20 ' will recheck if need to adjust wifi duration in maximum time interval 120 seconds */
+				m = 20;
+
+			n = 3 * m;
+			up = 0;
+			dn = 0;
+			wait_count = 0;
+			result = -1;
+		}
+
+		if (max_interval == 1) {
+			if (tx_pause) {
+				if (coex_dm->cur_ps_tdma == 71) {
+					halbtc8723b2ant_ps_tdma(btcoexist,
+							NORMAL_EXEC, true, 5);
+					coex_dm->ps_tdma_du_adj_type = 5;
+				} else if (coex_dm->cur_ps_tdma == 1) {
+					halbtc8723b2ant_ps_tdma(btcoexist,
+							NORMAL_EXEC, true, 5);
+					coex_dm->ps_tdma_du_adj_type = 5;
+				} else if (coex_dm->cur_ps_tdma == 2) {
+					halbtc8723b2ant_ps_tdma(btcoexist,
+							NORMAL_EXEC, true, 6);
+					coex_dm->ps_tdma_du_adj_type = 6;
+				} else if (coex_dm->cur_ps_tdma == 3) {
+					halbtc8723b2ant_ps_tdma(btcoexist,
+							NORMAL_EXEC, true, 7);
+					coex_dm->ps_tdma_du_adj_type = 7;
+				} else if (coex_dm->cur_ps_tdma == 4) {
+					halbtc8723b2ant_ps_tdma(btcoexist,
+							NORMAL_EXEC, true, 8);
+					coex_dm->ps_tdma_du_adj_type = 8;
+				}
+				if (coex_dm->cur_ps_tdma == 9) {
+					halbtc8723b2ant_ps_tdma(btcoexist,
+							NORMAL_EXEC, true, 13);
+					coex_dm->ps_tdma_du_adj_type = 13;
+				} else if (coex_dm->cur_ps_tdma == 10) {
+					halbtc8723b2ant_ps_tdma(btcoexist,
+							NORMAL_EXEC, true, 14);
+					coex_dm->ps_tdma_du_adj_type = 14;
+				} else if (coex_dm->cur_ps_tdma == 11) {
+					halbtc8723b2ant_ps_tdma(btcoexist,
+							NORMAL_EXEC, true, 15);
+					coex_dm->ps_tdma_du_adj_type = 15;
+				} else if (coex_dm->cur_ps_tdma == 12) {
+					halbtc8723b2ant_ps_tdma(btcoexist,
+							NORMAL_EXEC, true, 16);
+					coex_dm->ps_tdma_du_adj_type = 16;
+				}
+
+				if (result == -1) {
+					if (coex_dm->cur_ps_tdma == 5) {
+						halbtc8723b2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 6);
+						coex_dm->ps_tdma_du_adj_type =
+							6;
+					} else if (coex_dm->cur_ps_tdma == 6) {
+						halbtc8723b2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 7);
+						coex_dm->ps_tdma_du_adj_type =
+							7;
+					} else if (coex_dm->cur_ps_tdma == 7) {
+						halbtc8723b2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 8);
+						coex_dm->ps_tdma_du_adj_type =
+							8;
+					} else if (coex_dm->cur_ps_tdma == 13) {
+						halbtc8723b2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 14);
+						coex_dm->ps_tdma_du_adj_type =
+							14;
+					} else if (coex_dm->cur_ps_tdma == 14) {
+						halbtc8723b2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 15);
+						coex_dm->ps_tdma_du_adj_type =
+							15;
+					} else if (coex_dm->cur_ps_tdma == 15) {
+						halbtc8723b2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 16);
+						coex_dm->ps_tdma_du_adj_type =
+							16;
+					}
+				} else if (result == 1) {
+					if (coex_dm->cur_ps_tdma == 8) {
+						halbtc8723b2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 7);
+						coex_dm->ps_tdma_du_adj_type =
+							7;
+					} else if (coex_dm->cur_ps_tdma == 7) {
+						halbtc8723b2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 6);
+						coex_dm->ps_tdma_du_adj_type =
+							6;
+					} else if (coex_dm->cur_ps_tdma == 6) {
+						halbtc8723b2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 5);
+						coex_dm->ps_tdma_du_adj_type =
+							5;
+					} else if (coex_dm->cur_ps_tdma == 16) {
+						halbtc8723b2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 15);
+						coex_dm->ps_tdma_du_adj_type =
+							15;
+					} else if (coex_dm->cur_ps_tdma == 15) {
+						halbtc8723b2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 14);
+						coex_dm->ps_tdma_du_adj_type =
+							14;
+					} else if (coex_dm->cur_ps_tdma == 14) {
+						halbtc8723b2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 13);
+						coex_dm->ps_tdma_du_adj_type =
+							13;
+					}
+				}
+			} else {
+				if (coex_dm->cur_ps_tdma == 5) {
+					halbtc8723b2ant_ps_tdma(btcoexist,
+							NORMAL_EXEC, true, 71);
+					coex_dm->ps_tdma_du_adj_type = 71;
+				} else if (coex_dm->cur_ps_tdma == 6) {
+					halbtc8723b2ant_ps_tdma(btcoexist,
+							NORMAL_EXEC, true, 2);
+					coex_dm->ps_tdma_du_adj_type = 2;
+				} else if (coex_dm->cur_ps_tdma == 7) {
+					halbtc8723b2ant_ps_tdma(btcoexist,
+							NORMAL_EXEC, true, 3);
+					coex_dm->ps_tdma_du_adj_type = 3;
+				} else if (coex_dm->cur_ps_tdma == 8) {
+					halbtc8723b2ant_ps_tdma(btcoexist,
+							NORMAL_EXEC, true, 4);
+					coex_dm->ps_tdma_du_adj_type = 4;
+				}
+				if (coex_dm->cur_ps_tdma == 13) {
+					halbtc8723b2ant_ps_tdma(btcoexist,
+							NORMAL_EXEC, true, 9);
+					coex_dm->ps_tdma_du_adj_type = 9;
+				} else if (coex_dm->cur_ps_tdma == 14) {
+					halbtc8723b2ant_ps_tdma(btcoexist,
+							NORMAL_EXEC, true, 10);
+					coex_dm->ps_tdma_du_adj_type = 10;
+				} else if (coex_dm->cur_ps_tdma == 15) {
+					halbtc8723b2ant_ps_tdma(btcoexist,
+							NORMAL_EXEC, true, 11);
+					coex_dm->ps_tdma_du_adj_type = 11;
+				} else if (coex_dm->cur_ps_tdma == 16) {
+					halbtc8723b2ant_ps_tdma(btcoexist,
+							NORMAL_EXEC, true, 12);
+					coex_dm->ps_tdma_du_adj_type = 12;
+				}
+
+				if (result == -1) {
+					if (coex_dm->cur_ps_tdma == 71) {
+						halbtc8723b2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 1);
+						coex_dm->ps_tdma_du_adj_type =
+							1;
+					} else if (coex_dm->cur_ps_tdma == 1) {
+						halbtc8723b2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 2);
+						coex_dm->ps_tdma_du_adj_type =
+							2;
+					} else if (coex_dm->cur_ps_tdma == 2) {
+						halbtc8723b2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 3);
+						coex_dm->ps_tdma_du_adj_type =
+							3;
+					} else if (coex_dm->cur_ps_tdma == 3) {
+						halbtc8723b2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 4);
+						coex_dm->ps_tdma_du_adj_type =
+							4;
+					} else if (coex_dm->cur_ps_tdma == 9) {
+						halbtc8723b2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 10);
+						coex_dm->ps_tdma_du_adj_type =
+							10;
+					} else if (coex_dm->cur_ps_tdma == 10) {
+						halbtc8723b2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 11);
+						coex_dm->ps_tdma_du_adj_type =
+							11;
+					} else if (coex_dm->cur_ps_tdma == 11) {
+						halbtc8723b2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 12);
+						coex_dm->ps_tdma_du_adj_type =
+							12;
+					}
+				} else if (result == 1) {
+					if (coex_dm->cur_ps_tdma == 4) {
+						halbtc8723b2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 3);
+						coex_dm->ps_tdma_du_adj_type =
+							3;
+					} else if (coex_dm->cur_ps_tdma == 3) {
+						halbtc8723b2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 2);
+						coex_dm->ps_tdma_du_adj_type =
+							2;
+					} else if (coex_dm->cur_ps_tdma == 2) {
+						halbtc8723b2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 1);
+						coex_dm->ps_tdma_du_adj_type =
+							1;
+					} else if (coex_dm->cur_ps_tdma == 1) {
+						halbtc8723b2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 71);
+						coex_dm->ps_tdma_du_adj_type =
+							71;
+					} else if (coex_dm->cur_ps_tdma == 12) {
+						halbtc8723b2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 11);
+						coex_dm->ps_tdma_du_adj_type =
+							11;
+					} else if (coex_dm->cur_ps_tdma == 11) {
+						halbtc8723b2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 10);
+						coex_dm->ps_tdma_du_adj_type =
+							10;
+					} else if (coex_dm->cur_ps_tdma == 10) {
+						halbtc8723b2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 9);
+						coex_dm->ps_tdma_du_adj_type =
+							9;
+					}
+				}
+			}
+		} else if (max_interval == 2) {
+			if (tx_pause) {
+				if (coex_dm->cur_ps_tdma == 1) {
+					halbtc8723b2ant_ps_tdma(btcoexist,
+							NORMAL_EXEC, true, 6);
+					coex_dm->ps_tdma_du_adj_type = 6;
+				} else if (coex_dm->cur_ps_tdma == 2) {
+					halbtc8723b2ant_ps_tdma(btcoexist,
+							NORMAL_EXEC, true, 6);
+					coex_dm->ps_tdma_du_adj_type = 6;
+				} else if (coex_dm->cur_ps_tdma == 3) {
+					halbtc8723b2ant_ps_tdma(btcoexist,
+							NORMAL_EXEC, true, 7);
+					coex_dm->ps_tdma_du_adj_type = 7;
+				} else if (coex_dm->cur_ps_tdma == 4) {
+					halbtc8723b2ant_ps_tdma(btcoexist,
+							NORMAL_EXEC, true, 8);
+					coex_dm->ps_tdma_du_adj_type = 8;
+				}
+				if (coex_dm->cur_ps_tdma == 9) {
+					halbtc8723b2ant_ps_tdma(btcoexist,
+							NORMAL_EXEC, true, 14);
+					coex_dm->ps_tdma_du_adj_type = 14;
+				} else if (coex_dm->cur_ps_tdma == 10) {
+					halbtc8723b2ant_ps_tdma(btcoexist,
+							NORMAL_EXEC, true, 14);
+					coex_dm->ps_tdma_du_adj_type = 14;
+				} else if (coex_dm->cur_ps_tdma == 11) {
+					halbtc8723b2ant_ps_tdma(btcoexist,
+							NORMAL_EXEC, true, 15);
+					coex_dm->ps_tdma_du_adj_type = 15;
+				} else if (coex_dm->cur_ps_tdma == 12) {
+					halbtc8723b2ant_ps_tdma(btcoexist,
+							NORMAL_EXEC, true, 16);
+					coex_dm->ps_tdma_du_adj_type = 16;
+				}
+				if (result == -1) {
+					if (coex_dm->cur_ps_tdma == 5) {
+						halbtc8723b2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 6);
+						coex_dm->ps_tdma_du_adj_type =
+							6;
+					} else if (coex_dm->cur_ps_tdma == 6) {
+						halbtc8723b2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 7);
+						coex_dm->ps_tdma_du_adj_type =
+							7;
+					} else if (coex_dm->cur_ps_tdma == 7) {
+						halbtc8723b2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 8);
+						coex_dm->ps_tdma_du_adj_type =
+							8;
+					} else if (coex_dm->cur_ps_tdma == 13) {
+						halbtc8723b2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 14);
+						coex_dm->ps_tdma_du_adj_type =
+							14;
+					} else if (coex_dm->cur_ps_tdma == 14) {
+						halbtc8723b2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 15);
+						coex_dm->ps_tdma_du_adj_type =
+							15;
+					} else if (coex_dm->cur_ps_tdma == 15) {
+						halbtc8723b2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 16);
+						coex_dm->ps_tdma_du_adj_type =
+							16;
+					}
+				} else if (result == 1) {
+					if (coex_dm->cur_ps_tdma == 8) {
+						halbtc8723b2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 7);
+						coex_dm->ps_tdma_du_adj_type =
+							7;
+					} else if (coex_dm->cur_ps_tdma == 7) {
+						halbtc8723b2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 6);
+						coex_dm->ps_tdma_du_adj_type =
+							6;
+					} else if (coex_dm->cur_ps_tdma == 6) {
+						halbtc8723b2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 6);
+						coex_dm->ps_tdma_du_adj_type =
+							6;
+					} else if (coex_dm->cur_ps_tdma == 16) {
+						halbtc8723b2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 15);
+						coex_dm->ps_tdma_du_adj_type =
+							15;
+					} else if (coex_dm->cur_ps_tdma == 15) {
+						halbtc8723b2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 14);
+						coex_dm->ps_tdma_du_adj_type =
+							14;
+					} else if (coex_dm->cur_ps_tdma == 14) {
+						halbtc8723b2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 14);
+						coex_dm->ps_tdma_du_adj_type =
+							14;
+					}
+				}
+			} else {
+				if (coex_dm->cur_ps_tdma == 5) {
+					halbtc8723b2ant_ps_tdma(btcoexist,
+							NORMAL_EXEC, true, 2);
+					coex_dm->ps_tdma_du_adj_type = 2;
+				} else if (coex_dm->cur_ps_tdma == 6) {
+					halbtc8723b2ant_ps_tdma(btcoexist,
+							NORMAL_EXEC, true, 2);
+					coex_dm->ps_tdma_du_adj_type = 2;
+				} else if (coex_dm->cur_ps_tdma == 7) {
+					halbtc8723b2ant_ps_tdma(btcoexist,
+							NORMAL_EXEC, true, 3);
+					coex_dm->ps_tdma_du_adj_type = 3;
+				} else if (coex_dm->cur_ps_tdma == 8) {
+					halbtc8723b2ant_ps_tdma(btcoexist,
+							NORMAL_EXEC, true, 4);
+					coex_dm->ps_tdma_du_adj_type = 4;
+				}
+				if (coex_dm->cur_ps_tdma == 13) {
+					halbtc8723b2ant_ps_tdma(btcoexist,
+							NORMAL_EXEC, true, 10);
+					coex_dm->ps_tdma_du_adj_type = 10;
+				} else if (coex_dm->cur_ps_tdma == 14) {
+					halbtc8723b2ant_ps_tdma(btcoexist,
+							NORMAL_EXEC, true, 10);
+					coex_dm->ps_tdma_du_adj_type = 10;
+				} else if (coex_dm->cur_ps_tdma == 15) {
+					halbtc8723b2ant_ps_tdma(btcoexist,
+							NORMAL_EXEC, true, 11);
+					coex_dm->ps_tdma_du_adj_type = 11;
+				} else if (coex_dm->cur_ps_tdma == 16) {
+					halbtc8723b2ant_ps_tdma(btcoexist,
+							NORMAL_EXEC, true, 12);
+					coex_dm->ps_tdma_du_adj_type = 12;
+				}
+				if (result == -1) {
+					if (coex_dm->cur_ps_tdma == 1) {
+						halbtc8723b2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 2);
+						coex_dm->ps_tdma_du_adj_type =
+							2;
+					} else if (coex_dm->cur_ps_tdma == 2) {
+						halbtc8723b2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 3);
+						coex_dm->ps_tdma_du_adj_type =
+							3;
+					} else if (coex_dm->cur_ps_tdma == 3) {
+						halbtc8723b2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 4);
+						coex_dm->ps_tdma_du_adj_type =
+							4;
+					} else if (coex_dm->cur_ps_tdma == 9) {
+						halbtc8723b2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 10);
+						coex_dm->ps_tdma_du_adj_type =
+							10;
+					} else if (coex_dm->cur_ps_tdma == 10) {
+						halbtc8723b2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 11);
+						coex_dm->ps_tdma_du_adj_type =
+							11;
+					} else if (coex_dm->cur_ps_tdma == 11) {
+						halbtc8723b2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 12);
+						coex_dm->ps_tdma_du_adj_type =
+							12;
+					}
+				} else if (result == 1) {
+					if (coex_dm->cur_ps_tdma == 4) {
+						halbtc8723b2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 3);
+						coex_dm->ps_tdma_du_adj_type =
+							3;
+					} else if (coex_dm->cur_ps_tdma == 3) {
+						halbtc8723b2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 2);
+						coex_dm->ps_tdma_du_adj_type =
+							2;
+					} else if (coex_dm->cur_ps_tdma == 2) {
+						halbtc8723b2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 2);
+						coex_dm->ps_tdma_du_adj_type =
+							2;
+					} else if (coex_dm->cur_ps_tdma == 12) {
+						halbtc8723b2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 11);
+						coex_dm->ps_tdma_du_adj_type =
+							11;
+					} else if (coex_dm->cur_ps_tdma == 11) {
+						halbtc8723b2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 10);
+						coex_dm->ps_tdma_du_adj_type =
+							10;
+					} else if (coex_dm->cur_ps_tdma == 10) {
+						halbtc8723b2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 10);
+						coex_dm->ps_tdma_du_adj_type =
+							10;
+					}
+				}
+			}
+		} else if (max_interval == 3) {
+			if (tx_pause) {
+				if (coex_dm->cur_ps_tdma == 1) {
+					halbtc8723b2ant_ps_tdma(btcoexist,
+							NORMAL_EXEC, true, 7);
+					coex_dm->ps_tdma_du_adj_type = 7;
+				} else if (coex_dm->cur_ps_tdma == 2) {
+					halbtc8723b2ant_ps_tdma(btcoexist,
+							NORMAL_EXEC, true, 7);
+					coex_dm->ps_tdma_du_adj_type = 7;
+				} else if (coex_dm->cur_ps_tdma == 3) {
+					halbtc8723b2ant_ps_tdma(btcoexist,
+							NORMAL_EXEC, true, 7);
+					coex_dm->ps_tdma_du_adj_type = 7;
+				} else if (coex_dm->cur_ps_tdma == 4) {
+					halbtc8723b2ant_ps_tdma(btcoexist,
+							NORMAL_EXEC, true, 8);
+					coex_dm->ps_tdma_du_adj_type = 8;
+				}
+				if (coex_dm->cur_ps_tdma == 9) {
+					halbtc8723b2ant_ps_tdma(btcoexist,
+							NORMAL_EXEC, true, 15);
+					coex_dm->ps_tdma_du_adj_type = 15;
+				} else if (coex_dm->cur_ps_tdma == 10) {
+					halbtc8723b2ant_ps_tdma(btcoexist,
+							NORMAL_EXEC, true, 15);
+					coex_dm->ps_tdma_du_adj_type = 15;
+				} else if (coex_dm->cur_ps_tdma == 11) {
+					halbtc8723b2ant_ps_tdma(btcoexist,
+							NORMAL_EXEC, true, 15);
+					coex_dm->ps_tdma_du_adj_type = 15;
+				} else if (coex_dm->cur_ps_tdma == 12) {
+					halbtc8723b2ant_ps_tdma(btcoexist,
+							NORMAL_EXEC, true, 16);
+					coex_dm->ps_tdma_du_adj_type = 16;
+				}
+				if (result == -1) {
+					if (coex_dm->cur_ps_tdma == 5) {
+						halbtc8723b2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 7);
+						coex_dm->ps_tdma_du_adj_type =
+							7;
+					} else if (coex_dm->cur_ps_tdma == 6) {
+						halbtc8723b2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 7);
+						coex_dm->ps_tdma_du_adj_type =
+							7;
+					} else if (coex_dm->cur_ps_tdma == 7) {
+						halbtc8723b2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 8);
+						coex_dm->ps_tdma_du_adj_type =
+							8;
+					} else if (coex_dm->cur_ps_tdma == 13) {
+						halbtc8723b2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 15);
+						coex_dm->ps_tdma_du_adj_type =
+							15;
+					} else if (coex_dm->cur_ps_tdma == 14) {
+						halbtc8723b2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 15);
+						coex_dm->ps_tdma_du_adj_type =
+							15;
+					} else if (coex_dm->cur_ps_tdma == 15) {
+						halbtc8723b2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 16);
+						coex_dm->ps_tdma_du_adj_type =
+							16;
+					}
+				} else if (result == 1) {
+					if (coex_dm->cur_ps_tdma == 8) {
+						halbtc8723b2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 7);
+						coex_dm->ps_tdma_du_adj_type =
+							7;
+					} else if (coex_dm->cur_ps_tdma == 7) {
+						halbtc8723b2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 7);
+						coex_dm->ps_tdma_du_adj_type =
+							7;
+					} else if (coex_dm->cur_ps_tdma == 6) {
+						halbtc8723b2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 7);
+						coex_dm->ps_tdma_du_adj_type =
+							7;
+					} else if (coex_dm->cur_ps_tdma == 16) {
+						halbtc8723b2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 15);
+						coex_dm->ps_tdma_du_adj_type =
+							15;
+					} else if (coex_dm->cur_ps_tdma == 15) {
+						halbtc8723b2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 15);
+						coex_dm->ps_tdma_du_adj_type =
+							15;
+					} else if (coex_dm->cur_ps_tdma == 14) {
+						halbtc8723b2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 15);
+						coex_dm->ps_tdma_du_adj_type =
+							15;
+					}
+				}
+			} else {
+				if (coex_dm->cur_ps_tdma == 5) {
+					halbtc8723b2ant_ps_tdma(btcoexist,
+							NORMAL_EXEC, true, 3);
+					coex_dm->ps_tdma_du_adj_type = 3;
+				} else if (coex_dm->cur_ps_tdma == 6) {
+					halbtc8723b2ant_ps_tdma(btcoexist,
+							NORMAL_EXEC, true, 3);
+					coex_dm->ps_tdma_du_adj_type = 3;
+				} else if (coex_dm->cur_ps_tdma == 7) {
+					halbtc8723b2ant_ps_tdma(btcoexist,
+							NORMAL_EXEC, true, 3);
+					coex_dm->ps_tdma_du_adj_type = 3;
+				} else if (coex_dm->cur_ps_tdma == 8) {
+					halbtc8723b2ant_ps_tdma(btcoexist,
+							NORMAL_EXEC, true, 4);
+					coex_dm->ps_tdma_du_adj_type = 4;
+				}
+				if (coex_dm->cur_ps_tdma == 13) {
+					halbtc8723b2ant_ps_tdma(btcoexist,
+							NORMAL_EXEC, true, 11);
+					coex_dm->ps_tdma_du_adj_type = 11;
+				} else if (coex_dm->cur_ps_tdma == 14) {
+					halbtc8723b2ant_ps_tdma(btcoexist,
+							NORMAL_EXEC, true, 11);
+					coex_dm->ps_tdma_du_adj_type = 11;
+				} else if (coex_dm->cur_ps_tdma == 15) {
+					halbtc8723b2ant_ps_tdma(btcoexist,
+							NORMAL_EXEC, true, 11);
+					coex_dm->ps_tdma_du_adj_type = 11;
+				} else if (coex_dm->cur_ps_tdma == 16) {
+					halbtc8723b2ant_ps_tdma(btcoexist,
+							NORMAL_EXEC, true, 12);
+					coex_dm->ps_tdma_du_adj_type = 12;
+				}
+				if (result == -1) {
+					if (coex_dm->cur_ps_tdma == 1) {
+						halbtc8723b2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 3);
+						coex_dm->ps_tdma_du_adj_type =
+							3;
+					} else if (coex_dm->cur_ps_tdma == 2) {
+						halbtc8723b2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 3);
+						coex_dm->ps_tdma_du_adj_type =
+							3;
+					} else if (coex_dm->cur_ps_tdma == 3) {
+						halbtc8723b2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 4);
+						coex_dm->ps_tdma_du_adj_type =
+							4;
+					} else if (coex_dm->cur_ps_tdma == 9) {
+						halbtc8723b2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 11);
+						coex_dm->ps_tdma_du_adj_type =
+							11;
+					} else if (coex_dm->cur_ps_tdma == 10) {
+						halbtc8723b2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 11);
+						coex_dm->ps_tdma_du_adj_type =
+							11;
+					} else if (coex_dm->cur_ps_tdma == 11) {
+						halbtc8723b2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 12);
+						coex_dm->ps_tdma_du_adj_type =
+							12;
+					}
+				} else if (result == 1) {
+					if (coex_dm->cur_ps_tdma == 4) {
+						halbtc8723b2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 3);
+						coex_dm->ps_tdma_du_adj_type =
+							3;
+					} else if (coex_dm->cur_ps_tdma == 3) {
+						halbtc8723b2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 3);
+						coex_dm->ps_tdma_du_adj_type =
+							3;
+					} else if (coex_dm->cur_ps_tdma == 2) {
+						halbtc8723b2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 3);
+						coex_dm->ps_tdma_du_adj_type =
+							3;
+					} else if (coex_dm->cur_ps_tdma == 12) {
+						halbtc8723b2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 11);
+						coex_dm->ps_tdma_du_adj_type =
+							11;
+					} else if (coex_dm->cur_ps_tdma == 11) {
+						halbtc8723b2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 11);
+						coex_dm->ps_tdma_du_adj_type =
+							11;
+					} else if (coex_dm->cur_ps_tdma == 10) {
+						halbtc8723b2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 11);
+						coex_dm->ps_tdma_du_adj_type =
+							11;
+					}
+				}
+			}
+		}
+	}
+
+	/* if current PsTdma not match with the recorded one (when scan, dhcp...), */
+	/* then we have to adjust it back to the previous record one. */
+	if (coex_dm->cur_ps_tdma != coex_dm->ps_tdma_du_adj_type) {
+		boolean	scan = false, link = false, roam = false;
+
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			"[BTCoex], PsTdma type dismatch!!!, cur_ps_tdma=%d, recordPsTdma=%d\n",
+			    coex_dm->cur_ps_tdma, coex_dm->ps_tdma_du_adj_type);
+		BTC_TRACE(trace_buf);
+
+		btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_SCAN, &scan);
+		btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_LINK, &link);
+		btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_ROAM, &roam);
+
+		if (!scan && !link && !roam)
+			halbtc8723b2ant_ps_tdma(btcoexist, NORMAL_EXEC, true,
+						coex_dm->ps_tdma_du_adj_type);
+		else {
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				"[BTCoex], roaming/link/scan is under progress, will adjust next time!!!\n");
+			BTC_TRACE(trace_buf);
+		}
+	}
+}
+
+/* SCO only or SCO+PAN(HS) */
+void halbtc8723b2ant_action_sco(IN struct btc_coexist *btcoexist)
+{
+	static u8	prewifi_rssi_state = BTC_RSSI_STATE_LOW;
+	static u8	pre_bt_rssi_state = BTC_RSSI_STATE_LOW;
+	u8	wifi_rssi_state, bt_rssi_state;
+	u32	wifi_bw;
+
+	wifi_rssi_state = halbtc8723b2ant_wifi_rssi_state(btcoexist,
+			  &prewifi_rssi_state, 2, 15, 0);
+	bt_rssi_state = halbtc8723b2ant_bt_rssi_state(&pre_bt_rssi_state, 2,
+			BT_8723B_2ANT_BT_RSSI_COEXSWITCH_THRES -
+			coex_dm->switch_thres_offset, 0);
+
+	btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1, 0xfffff, 0x0);
+
+	halbtc8723b2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, 0x8);
+
+	halbtc8723b2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 4);
+
+	if (BTC_RSSI_HIGH(bt_rssi_state))
+		halbtc8723b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2);
+	else
+		halbtc8723b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);
+
+	btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw);
+
+	if (BTC_WIFI_BW_LEGACY == wifi_bw) /* for SCO quality at 11b/g mode */
+		halbtc8723b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 2);
+	else  /* for SCO quality & wifi performance balance at 11n mode */
+		halbtc8723b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 8);
+
+	halbtc8723b2ant_ps_tdma(btcoexist, NORMAL_EXEC, false,
+				0); /* for voice quality */
+
+	/* sw mechanism */
+	if (BTC_WIFI_BW_HT40 == wifi_bw) {
+		if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) ||
+		    (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
+			halbtc8723b2ant_sw_mechanism1(btcoexist, true, true,
+						      false, false);
+			halbtc8723b2ant_sw_mechanism2(btcoexist, true, false,
+						      true, 0x4);
+		} else {
+			halbtc8723b2ant_sw_mechanism1(btcoexist, true, true,
+						      false, false);
+			halbtc8723b2ant_sw_mechanism2(btcoexist, false, false,
+						      true, 0x4);
+		}
+	} else {
+		if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) ||
+		    (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
+			halbtc8723b2ant_sw_mechanism1(btcoexist, false, true,
+						      false, false);
+			halbtc8723b2ant_sw_mechanism2(btcoexist, true, false,
+						      true, 0x4);
+		} else {
+			halbtc8723b2ant_sw_mechanism1(btcoexist, false, true,
+						      false, false);
+			halbtc8723b2ant_sw_mechanism2(btcoexist, false, false,
+						      true, 0x4);
+		}
+	}
+}
+
+
+void halbtc8723b2ant_action_hid(IN struct btc_coexist *btcoexist)
+{
+	static u8	prewifi_rssi_state = BTC_RSSI_STATE_LOW;
+	static u8	pre_bt_rssi_state = BTC_RSSI_STATE_LOW;
+	u8	wifi_rssi_state, bt_rssi_state;
+	u32	wifi_bw;
+
+	btcoexist->btc_phydm_modify_RA_PCR_threshold(btcoexist, 0, 25);
+
+	wifi_rssi_state = halbtc8723b2ant_wifi_rssi_state(btcoexist,
+			  &prewifi_rssi_state, 2, 15, 0);
+	bt_rssi_state = halbtc8723b2ant_bt_rssi_state(&pre_bt_rssi_state, 2,
+			BT_8723B_2ANT_BT_RSSI_COEXSWITCH_THRES -
+			coex_dm->switch_thres_offset, 0);
+
+	btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1, 0xfffff, 0x0);
+
+	halbtc8723b2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, 0x8);
+
+	halbtc8723b2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6);
+
+	if (BTC_RSSI_HIGH(bt_rssi_state))
+		halbtc8723b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2);
+	else
+		halbtc8723b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);
+
+	btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw);
+
+	if (BTC_WIFI_BW_LEGACY == wifi_bw) /* for HID at 11b/g mode */
+		halbtc8723b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 7);
+	else  /* for HID quality & wifi performance balance at 11n mode */
+		halbtc8723b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 9);
+
+	if ((bt_rssi_state == BTC_RSSI_STATE_HIGH) ||
+	    (bt_rssi_state == BTC_RSSI_STATE_STAY_HIGH))
+		halbtc8723b2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 9);
+	else
+		halbtc8723b2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 13);
+
+	/* sw mechanism */
+	if (BTC_WIFI_BW_HT40 == wifi_bw) {
+		if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) ||
+		    (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
+			halbtc8723b2ant_sw_mechanism1(btcoexist, true, true,
+						      false, false);
+			halbtc8723b2ant_sw_mechanism2(btcoexist, true, false,
+						      false, 0x18);
+		} else {
+			halbtc8723b2ant_sw_mechanism1(btcoexist, true, true,
+						      false, false);
+			halbtc8723b2ant_sw_mechanism2(btcoexist, false, false,
+						      false, 0x18);
+		}
+	} else {
+		if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) ||
+		    (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
+			halbtc8723b2ant_sw_mechanism1(btcoexist, false, true,
+						      false, false);
+			halbtc8723b2ant_sw_mechanism2(btcoexist, true, false,
+						      false, 0x18);
+		} else {
+			halbtc8723b2ant_sw_mechanism1(btcoexist, false, true,
+						      false, false);
+			halbtc8723b2ant_sw_mechanism2(btcoexist, false, false,
+						      false, 0x18);
+		}
+	}
+}
+
+/* A2DP only / PAN(EDR) only/ A2DP+PAN(HS) */
+void halbtc8723b2ant_action_a2dp(IN struct btc_coexist *btcoexist)
+{
+	static u8	prewifi_rssi_state = BTC_RSSI_STATE_LOW,
+			prewifi_rssi_state1 = BTC_RSSI_STATE_LOW;
+	static u8	pre_bt_rssi_state = BTC_RSSI_STATE_LOW;
+	u8		wifi_rssi_state, wifi_rssi_state1, bt_rssi_state;
+	u32		wifi_bw;
+	u8		ap_num = 0;
+
+	wifi_rssi_state = halbtc8723b2ant_wifi_rssi_state(btcoexist,
+			  &prewifi_rssi_state, 2, 15, 0);
+	wifi_rssi_state1 = halbtc8723b2ant_wifi_rssi_state(btcoexist,
+			   &prewifi_rssi_state1, 2,
+			   BT_8723B_2ANT_WIFI_RSSI_COEXSWITCH_THRES -
+			   coex_dm->switch_thres_offset, 0);
+	bt_rssi_state = halbtc8723b2ant_bt_rssi_state(&pre_bt_rssi_state, 2,
+			BT_8723B_2ANT_BT_RSSI_COEXSWITCH_THRES -
+			coex_dm->switch_thres_offset, 0);
+
+	btcoexist->btc_get(btcoexist, BTC_GET_U1_AP_NUM, &ap_num);
+
+	/* define the office environment */
+	if ((ap_num >= 10) && BTC_RSSI_HIGH(wifi_rssi_state1) &&
+	    BTC_RSSI_HIGH(bt_rssi_state)) {
+		/* dbg_print(" AP#>10(%d)\n", ap_num); */
+
+		btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1, 0xfffff,
+					  0x0);
+		halbtc8723b2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false,
+					   0x8);
+		halbtc8723b2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6);
+		halbtc8723b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2);
+
+		halbtc8723b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0);
+
+		halbtc8723b2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 1);
+
+		/* sw mechanism */
+		btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw);
+		if (BTC_WIFI_BW_HT40 == wifi_bw) {
+			halbtc8723b2ant_sw_mechanism1(btcoexist, true, false,
+						      false, false);
+			halbtc8723b2ant_sw_mechanism2(btcoexist, true, false,
+						      true, 0x18);
+		} else {
+			halbtc8723b2ant_sw_mechanism1(btcoexist, false, false,
+						      false, false);
+			halbtc8723b2ant_sw_mechanism2(btcoexist, true, false,
+						      true, 0x18);
+		}
+		return;
+
+	}
+
+	btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1, 0xfffff, 0x0);
+	halbtc8723b2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, 0x8);
+
+	halbtc8723b2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6);
+
+	if (BTC_RSSI_HIGH(bt_rssi_state))
+		halbtc8723b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2);
+	else
+		halbtc8723b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);
+
+
+	if (BTC_RSSI_HIGH(wifi_rssi_state1) && BTC_RSSI_HIGH(bt_rssi_state)) {
+		halbtc8723b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 7);
+
+	} else {
+		halbtc8723b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC,
+						     13);
+	}
+
+
+	if ((bt_rssi_state == BTC_RSSI_STATE_HIGH) ||
+	    (bt_rssi_state == BTC_RSSI_STATE_STAY_HIGH))
+		halbtc8723b2ant_tdma_duration_adjust(btcoexist, false, false,
+						     1);
+	else
+		halbtc8723b2ant_tdma_duration_adjust(btcoexist, false, true, 1);
+
+	/* sw mechanism */
+	btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw);
+	if (BTC_WIFI_BW_HT40 == wifi_bw) {
+		if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) ||
+		    (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
+			halbtc8723b2ant_sw_mechanism1(btcoexist, true, false,
+						      false, false);
+			halbtc8723b2ant_sw_mechanism2(btcoexist, true, false,
+						      false, 0x18);
+		} else {
+			halbtc8723b2ant_sw_mechanism1(btcoexist, true, false,
+						      false, false);
+			halbtc8723b2ant_sw_mechanism2(btcoexist, false, false,
+						      false, 0x18);
+		}
+	} else {
+		if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) ||
+		    (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
+			halbtc8723b2ant_sw_mechanism1(btcoexist, false, false,
+						      false, false);
+			halbtc8723b2ant_sw_mechanism2(btcoexist, true, false,
+						      false, 0x18);
+		} else {
+			halbtc8723b2ant_sw_mechanism1(btcoexist, false, false,
+						      false, false);
+			halbtc8723b2ant_sw_mechanism2(btcoexist, false, false,
+						      false, 0x18);
+		}
+	}
+}
+
+void halbtc8723b2ant_action_a2dp_pan_hs(IN struct btc_coexist *btcoexist)
+{
+	static u8	prewifi_rssi_state = BTC_RSSI_STATE_LOW,
+			prewifi_rssi_state1 = BTC_RSSI_STATE_LOW;
+	static u8	pre_bt_rssi_state = BTC_RSSI_STATE_LOW;
+	u8		wifi_rssi_state, wifi_rssi_state1, bt_rssi_state;
+	u32		wifi_bw;
+
+	wifi_rssi_state = halbtc8723b2ant_wifi_rssi_state(btcoexist,
+			  &prewifi_rssi_state, 2, 15, 0);
+	wifi_rssi_state1 = halbtc8723b2ant_wifi_rssi_state(btcoexist,
+			   &prewifi_rssi_state1, 2,
+			   BT_8723B_2ANT_WIFI_RSSI_COEXSWITCH_THRES -
+			   coex_dm->switch_thres_offset, 0);
+	bt_rssi_state = halbtc8723b2ant_bt_rssi_state(&pre_bt_rssi_state, 2,
+			BT_8723B_2ANT_BT_RSSI_COEXSWITCH_THRES -
+			coex_dm->switch_thres_offset, 0);
+
+	btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1, 0xfffff, 0x0);
+
+	halbtc8723b2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, 0x8);
+
+	halbtc8723b2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6);
+
+	if (BTC_RSSI_HIGH(bt_rssi_state))
+		halbtc8723b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2);
+	else
+		halbtc8723b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);
+
+	if (BTC_RSSI_HIGH(wifi_rssi_state1) && BTC_RSSI_HIGH(bt_rssi_state)) {
+		halbtc8723b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 7);
+
+	} else {
+		halbtc8723b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC,
+						     13);
+	}
+
+	halbtc8723b2ant_tdma_duration_adjust(btcoexist, false, true, 2);
+
+	/* sw mechanism */
+	btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw);
+	if (BTC_WIFI_BW_HT40 == wifi_bw) {
+		if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) ||
+		    (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
+			halbtc8723b2ant_sw_mechanism1(btcoexist, true, false,
+						      false, false);
+			halbtc8723b2ant_sw_mechanism2(btcoexist, true, false,
+						      false, 0x18);
+		} else {
+			halbtc8723b2ant_sw_mechanism1(btcoexist, true, false,
+						      false, false);
+			halbtc8723b2ant_sw_mechanism2(btcoexist, false, false,
+						      false, 0x18);
+		}
+	} else {
+		if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) ||
+		    (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
+			halbtc8723b2ant_sw_mechanism1(btcoexist, false, false,
+						      false, false);
+			halbtc8723b2ant_sw_mechanism2(btcoexist, true, false,
+						      false, 0x18);
+		} else {
+			halbtc8723b2ant_sw_mechanism1(btcoexist, false, false,
+						      false, false);
+			halbtc8723b2ant_sw_mechanism2(btcoexist, false, false,
+						      false, 0x18);
+		}
+	}
+}
+
+void halbtc8723b2ant_action_pan_edr(IN struct btc_coexist *btcoexist)
+{
+	static u8	prewifi_rssi_state = BTC_RSSI_STATE_LOW,
+			prewifi_rssi_state1 = BTC_RSSI_STATE_LOW;
+	static u8	pre_bt_rssi_state = BTC_RSSI_STATE_LOW;
+	u8		wifi_rssi_state, wifi_rssi_state1, bt_rssi_state;
+	u32		wifi_bw;
+
+	wifi_rssi_state = halbtc8723b2ant_wifi_rssi_state(btcoexist,
+			  &prewifi_rssi_state, 2, 15, 0);
+	wifi_rssi_state1 = halbtc8723b2ant_wifi_rssi_state(btcoexist,
+			   &prewifi_rssi_state1, 2,
+			   BT_8723B_2ANT_WIFI_RSSI_COEXSWITCH_THRES -
+			   coex_dm->switch_thres_offset, 0);
+	bt_rssi_state = halbtc8723b2ant_bt_rssi_state(&pre_bt_rssi_state, 2,
+			BT_8723B_2ANT_BT_RSSI_COEXSWITCH_THRES -
+			coex_dm->switch_thres_offset, 0);
+
+	btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1, 0xfffff, 0x0);
+
+	halbtc8723b2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, 0x8);
+
+	halbtc8723b2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6);
+
+	if (BTC_RSSI_HIGH(bt_rssi_state))
+		halbtc8723b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2);
+	else
+		halbtc8723b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);
+
+	if (BTC_RSSI_HIGH(wifi_rssi_state1) && BTC_RSSI_HIGH(bt_rssi_state)) {
+		halbtc8723b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC,
+						     10);
+	} else {
+		halbtc8723b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC,
+						     13);
+	}
+
+	if ((bt_rssi_state == BTC_RSSI_STATE_HIGH) ||
+	    (bt_rssi_state == BTC_RSSI_STATE_STAY_HIGH))
+		halbtc8723b2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 1);
+	else
+		halbtc8723b2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 5);
+
+	/* sw mechanism */
+	btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw);
+	if (BTC_WIFI_BW_HT40 == wifi_bw) {
+		if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) ||
+		    (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
+			halbtc8723b2ant_sw_mechanism1(btcoexist, true, false,
+						      false, false);
+			halbtc8723b2ant_sw_mechanism2(btcoexist, true, false,
+						      false, 0x18);
+		} else {
+			halbtc8723b2ant_sw_mechanism1(btcoexist, true, false,
+						      false, false);
+			halbtc8723b2ant_sw_mechanism2(btcoexist, false, false,
+						      false, 0x18);
+		}
+	} else {
+		if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) ||
+		    (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
+			halbtc8723b2ant_sw_mechanism1(btcoexist, false, false,
+						      false, false);
+			halbtc8723b2ant_sw_mechanism2(btcoexist, true, false,
+						      false, 0x18);
+		} else {
+			halbtc8723b2ant_sw_mechanism1(btcoexist, false, false,
+						      false, false);
+			halbtc8723b2ant_sw_mechanism2(btcoexist, false, false,
+						      false, 0x18);
+		}
+	}
+}
+
+
+/* PAN(HS) only */
+void halbtc8723b2ant_action_pan_hs(IN struct btc_coexist *btcoexist)
+{
+	static u8	prewifi_rssi_state = BTC_RSSI_STATE_LOW,
+			prewifi_rssi_state1 = BTC_RSSI_STATE_LOW;
+	static u8	pre_bt_rssi_state = BTC_RSSI_STATE_LOW;
+	u8		wifi_rssi_state, wifi_rssi_state1, bt_rssi_state;
+	u32		wifi_bw;
+
+	wifi_rssi_state = halbtc8723b2ant_wifi_rssi_state(btcoexist,
+			  &prewifi_rssi_state, 2, 15, 0);
+	wifi_rssi_state1 = halbtc8723b2ant_wifi_rssi_state(btcoexist,
+			   &prewifi_rssi_state1, 2,
+			   BT_8723B_2ANT_WIFI_RSSI_COEXSWITCH_THRES -
+			   coex_dm->switch_thres_offset, 0);
+	bt_rssi_state = halbtc8723b2ant_bt_rssi_state(&pre_bt_rssi_state, 2,
+			BT_8723B_2ANT_BT_RSSI_COEXSWITCH_THRES -
+			coex_dm->switch_thres_offset, 0);
+
+	btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1, 0xfffff, 0x0);
+
+	halbtc8723b2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, 0x8);
+
+	halbtc8723b2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6);
+
+	if (BTC_RSSI_HIGH(bt_rssi_state))
+		halbtc8723b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2);
+	else
+		halbtc8723b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);
+
+	halbtc8723b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 7);
+
+	halbtc8723b2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 1);
+
+	btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw);
+	if (BTC_WIFI_BW_HT40 == wifi_bw) {
+		if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) ||
+		    (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
+			halbtc8723b2ant_sw_mechanism1(btcoexist, true, false,
+						      false, false);
+			halbtc8723b2ant_sw_mechanism2(btcoexist, true, false,
+						      false, 0x18);
+		} else {
+			halbtc8723b2ant_sw_mechanism1(btcoexist, true, false,
+						      false, false);
+			halbtc8723b2ant_sw_mechanism2(btcoexist, false, false,
+						      false, 0x18);
+		}
+	} else {
+		if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) ||
+		    (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
+			halbtc8723b2ant_sw_mechanism1(btcoexist, false, false,
+						      false, false);
+			halbtc8723b2ant_sw_mechanism2(btcoexist, true, false,
+						      false, 0x18);
+		} else {
+			halbtc8723b2ant_sw_mechanism1(btcoexist, false, false,
+						      false, false);
+			halbtc8723b2ant_sw_mechanism2(btcoexist, false, false,
+						      false, 0x18);
+		}
+	}
+}
+
+/* PAN(EDR)+A2DP */
+void halbtc8723b2ant_action_pan_edr_a2dp(IN struct btc_coexist *btcoexist)
+{
+	static u8	prewifi_rssi_state = BTC_RSSI_STATE_LOW,
+			prewifi_rssi_state1 = BTC_RSSI_STATE_LOW;
+	static u8	pre_bt_rssi_state = BTC_RSSI_STATE_LOW;
+	u8		wifi_rssi_state, wifi_rssi_state1, bt_rssi_state;
+	u8		ap_num = 0;
+	u32		wifi_bw;
+
+	wifi_rssi_state = halbtc8723b2ant_wifi_rssi_state(btcoexist,
+			  &prewifi_rssi_state, 2, 15, 0);
+	wifi_rssi_state1 = halbtc8723b2ant_wifi_rssi_state(btcoexist,
+			   &prewifi_rssi_state1, 2,
+			   BT_8723B_2ANT_WIFI_RSSI_COEXSWITCH_THRES -
+			   coex_dm->switch_thres_offset, 0);
+	bt_rssi_state = halbtc8723b2ant_bt_rssi_state(&pre_bt_rssi_state, 2,
+			BT_8723B_2ANT_BT_RSSI_COEXSWITCH_THRES -
+			coex_dm->switch_thres_offset, 0);
+
+	btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1, 0xfffff, 0x0);
+
+	halbtc8723b2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, 0x8);
+
+	halbtc8723b2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6);
+
+	if (BTC_RSSI_HIGH(bt_rssi_state))
+		halbtc8723b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2);
+	else
+		halbtc8723b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);
+
+	btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw);
+	btcoexist->btc_get(btcoexist, BTC_GET_U1_AP_NUM,
+			   &ap_num);
+
+	if ((bt_rssi_state == BTC_RSSI_STATE_HIGH) ||
+	    (bt_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
+		halbtc8723b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC,
+						     12);
+
+		if (ap_num < 10)
+			halbtc8723b2ant_tdma_duration_adjust(btcoexist, true,
+							     false, 1);
+		else
+			halbtc8723b2ant_tdma_duration_adjust(btcoexist, true,
+							     false, 3);
+
+	} else {
+		halbtc8723b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC,
+						     13);
+		if (ap_num < 10)
+			halbtc8723b2ant_tdma_duration_adjust(btcoexist, true,
+							     true, 1);
+		else
+			halbtc8723b2ant_tdma_duration_adjust(btcoexist, true,
+							     true, 3);
+	}
+
+	/* sw mechanism	 */
+	if (BTC_WIFI_BW_HT40 == wifi_bw) {
+		if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) ||
+		    (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
+			halbtc8723b2ant_sw_mechanism1(btcoexist, true, false,
+						      false, false);
+			halbtc8723b2ant_sw_mechanism2(btcoexist, true, false,
+						      false, 0x18);
+		} else {
+			halbtc8723b2ant_sw_mechanism1(btcoexist, true, false,
+						      false, false);
+			halbtc8723b2ant_sw_mechanism2(btcoexist, false, false,
+						      false, 0x18);
+		}
+	} else {
+		if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) ||
+		    (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
+			halbtc8723b2ant_sw_mechanism1(btcoexist, false, false,
+						      false, false);
+			halbtc8723b2ant_sw_mechanism2(btcoexist, true, false,
+						      false, 0x18);
+		} else {
+			halbtc8723b2ant_sw_mechanism1(btcoexist, false, false,
+						      false, false);
+			halbtc8723b2ant_sw_mechanism2(btcoexist, false, false,
+						      false, 0x18);
+		}
+	}
+}
+
+void halbtc8723b2ant_action_pan_edr_hid(IN struct btc_coexist *btcoexist)
+{
+	static u8	prewifi_rssi_state = BTC_RSSI_STATE_LOW,
+			prewifi_rssi_state1 = BTC_RSSI_STATE_LOW;
+	static u8	pre_bt_rssi_state = BTC_RSSI_STATE_LOW;
+	u8		wifi_rssi_state, wifi_rssi_state1, bt_rssi_state;
+	u32		wifi_bw;
+
+	btcoexist->btc_phydm_modify_RA_PCR_threshold(btcoexist, 0, 25);
+
+	wifi_rssi_state = halbtc8723b2ant_wifi_rssi_state(btcoexist,
+			  &prewifi_rssi_state, 2, 15, 0);
+	wifi_rssi_state1 = halbtc8723b2ant_wifi_rssi_state(btcoexist,
+			   &prewifi_rssi_state1, 2,
+			   BT_8723B_2ANT_WIFI_RSSI_COEXSWITCH_THRES -
+			   coex_dm->switch_thres_offset, 0);
+	bt_rssi_state = halbtc8723b2ant_bt_rssi_state(&pre_bt_rssi_state, 2,
+			BT_8723B_2ANT_BT_RSSI_COEXSWITCH_THRES -
+			coex_dm->switch_thres_offset, 0);
+	btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw);
+
+	halbtc8723b2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, 0x8);
+
+	if (BTC_RSSI_HIGH(bt_rssi_state))
+		halbtc8723b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2);
+	else
+		halbtc8723b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);
+
+	if (BTC_RSSI_HIGH(wifi_rssi_state1) && BTC_RSSI_HIGH(bt_rssi_state)) {
+		halbtc8723b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 7);
+	} else {
+		halbtc8723b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC,
+						     14);
+	}
+
+	if ((bt_rssi_state == BTC_RSSI_STATE_HIGH) ||
+	    (bt_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
+		if (BTC_WIFI_BW_HT40 == wifi_bw) {
+			halbtc8723b2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC,
+							 3);
+			/* halbtc8723b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 11); */
+			btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1,
+						  0xfffff, 0x780);
+		} else {
+			halbtc8723b2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC,
+							 6);
+			/* halbtc8723b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 7); */
+			btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1,
+						  0xfffff, 0x0);
+		}
+		halbtc8723b2ant_tdma_duration_adjust(btcoexist, true, false, 2);
+	} else {
+		halbtc8723b2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6);
+		/* halbtc8723b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 14); */
+		btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1, 0xfffff,
+					  0x0);
+		halbtc8723b2ant_tdma_duration_adjust(btcoexist, true, true, 2);
+	}
+
+	/* sw mechanism */
+	if (BTC_WIFI_BW_HT40 == wifi_bw) {
+		if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) ||
+		    (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
+			halbtc8723b2ant_sw_mechanism1(btcoexist, true, true,
+						      false, false);
+			halbtc8723b2ant_sw_mechanism2(btcoexist, true, false,
+						      false, 0x18);
+		} else {
+			halbtc8723b2ant_sw_mechanism1(btcoexist, true, true,
+						      false, false);
+			halbtc8723b2ant_sw_mechanism2(btcoexist, false, false,
+						      false, 0x18);
+		}
+	} else {
+		if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) ||
+		    (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
+			halbtc8723b2ant_sw_mechanism1(btcoexist, false, true,
+						      false, false);
+			halbtc8723b2ant_sw_mechanism2(btcoexist, true, false,
+						      false, 0x18);
+		} else {
+			halbtc8723b2ant_sw_mechanism1(btcoexist, false, true,
+						      false, false);
+			halbtc8723b2ant_sw_mechanism2(btcoexist, false, false,
+						      false, 0x18);
+		}
+	}
+}
+
+/* HID+A2DP+PAN(EDR) */
+void halbtc8723b2ant_action_hid_a2dp_pan_edr(IN struct btc_coexist *btcoexist)
+{
+	static u8	prewifi_rssi_state = BTC_RSSI_STATE_LOW,
+			prewifi_rssi_state1 = BTC_RSSI_STATE_LOW;
+	static u8	pre_bt_rssi_state = BTC_RSSI_STATE_LOW;
+	u8		wifi_rssi_state, wifi_rssi_state1,  bt_rssi_state;
+	u32		wifi_bw;
+
+	btcoexist->btc_phydm_modify_RA_PCR_threshold(btcoexist, 0, 25);
+
+	wifi_rssi_state = halbtc8723b2ant_wifi_rssi_state(btcoexist,
+			  &prewifi_rssi_state, 2, 15, 0);
+	wifi_rssi_state1 = halbtc8723b2ant_wifi_rssi_state(btcoexist,
+			   &prewifi_rssi_state1, 2,
+			   BT_8723B_2ANT_WIFI_RSSI_COEXSWITCH_THRES -
+			   coex_dm->switch_thres_offset, 0);
+	bt_rssi_state = halbtc8723b2ant_bt_rssi_state(&pre_bt_rssi_state, 2,
+			BT_8723B_2ANT_BT_RSSI_COEXSWITCH_THRES -
+			coex_dm->switch_thres_offset, 0);
+
+	btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1, 0xfffff, 0x0);
+
+	halbtc8723b2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, 0x8);
+
+	halbtc8723b2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6);
+
+	if (BTC_RSSI_HIGH(bt_rssi_state))
+		halbtc8723b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2);
+	else
+		halbtc8723b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);
+
+	if (BTC_RSSI_HIGH(wifi_rssi_state1) && BTC_RSSI_HIGH(bt_rssi_state)) {
+		halbtc8723b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 7);
+	} else {
+		halbtc8723b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC,
+						     14);
+	}
+
+	btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw);
+
+	if ((bt_rssi_state == BTC_RSSI_STATE_HIGH) ||
+	    (bt_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
+		if (BTC_WIFI_BW_HT40 == wifi_bw)
+			halbtc8723b2ant_tdma_duration_adjust(btcoexist, true,
+							     true, 3);
+		else
+			halbtc8723b2ant_tdma_duration_adjust(btcoexist, true,
+							     false, 3);
+	} else
+		halbtc8723b2ant_tdma_duration_adjust(btcoexist, true, true, 3);
+
+	/* sw mechanism */
+	if (BTC_WIFI_BW_HT40 == wifi_bw) {
+		if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) ||
+		    (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
+			halbtc8723b2ant_sw_mechanism1(btcoexist, true, true,
+						      false, false);
+			halbtc8723b2ant_sw_mechanism2(btcoexist, true, false,
+						      false, 0x18);
+		} else {
+			halbtc8723b2ant_sw_mechanism1(btcoexist, true, true,
+						      false, false);
+			halbtc8723b2ant_sw_mechanism2(btcoexist, false, false,
+						      false, 0x18);
+		}
+	} else {
+		if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) ||
+		    (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
+			halbtc8723b2ant_sw_mechanism1(btcoexist, false, true,
+						      false, false);
+			halbtc8723b2ant_sw_mechanism2(btcoexist, true, false,
+						      false, 0x18);
+		} else {
+			halbtc8723b2ant_sw_mechanism1(btcoexist, false, true,
+						      false, false);
+			halbtc8723b2ant_sw_mechanism2(btcoexist, false, false,
+						      false, 0x18);
+		}
+	}
+}
+
+void halbtc8723b2ant_action_hid_a2dp(IN struct btc_coexist *btcoexist)
+{
+	static u8	prewifi_rssi_state = BTC_RSSI_STATE_LOW,
+			prewifi_rssi_state1 = BTC_RSSI_STATE_LOW;
+	static u8	pre_bt_rssi_state = BTC_RSSI_STATE_LOW;
+	u8		wifi_rssi_state, wifi_rssi_state1, bt_rssi_state;
+	u32		wifi_bw;
+	u8		ap_num = 0;
+
+	btcoexist->btc_phydm_modify_RA_PCR_threshold(btcoexist, 0, 35);
+
+
+	wifi_rssi_state = halbtc8723b2ant_wifi_rssi_state(btcoexist,
+			  &prewifi_rssi_state, 2, 15, 0);
+	/* bt_rssi_state = halbtc8723b2ant_bt_rssi_state(2, 29, 0); */
+	wifi_rssi_state1 = halbtc8723b2ant_wifi_rssi_state(btcoexist,
+			   &prewifi_rssi_state1, 2,
+			   BT_8723B_2ANT_WIFI_RSSI_COEXSWITCH_THRES -
+			   coex_dm->switch_thres_offset, 0);
+	bt_rssi_state = halbtc8723b2ant_bt_rssi_state(&pre_bt_rssi_state, 3,
+			BT_8723B_2ANT_BT_RSSI_COEXSWITCH_THRES -
+			coex_dm->switch_thres_offset, 37);
+
+	btcoexist->btc_get(btcoexist, BTC_GET_U1_AP_NUM,
+			   &ap_num);
+
+	btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1, 0xfffff, 0x0);
+
+	halbtc8723b2ant_limited_rx(btcoexist, NORMAL_EXEC, false, true, 0x5);
+
+	halbtc8723b2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6);
+
+	btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw);
+	if (BTC_WIFI_BW_LEGACY == wifi_bw) {
+		if (BTC_RSSI_HIGH(bt_rssi_state))
+			halbtc8723b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2);
+		else if (BTC_RSSI_MEDIUM(bt_rssi_state))
+			halbtc8723b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2);
+		else
+			halbtc8723b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);
+	} else {
+		/* only 802.11N mode we have to dec bt power to 4 degree */
+		if (BTC_RSSI_HIGH(bt_rssi_state)) {
+			/* need to check ap Number of Not */
+			if (ap_num < 10)
+				halbtc8723b2ant_dec_bt_pwr(btcoexist,
+							   NORMAL_EXEC, 4);
+			else
+				halbtc8723b2ant_dec_bt_pwr(btcoexist,
+							   NORMAL_EXEC, 2);
+		} else if (BTC_RSSI_MEDIUM(bt_rssi_state))
+			halbtc8723b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2);
+		else
+			halbtc8723b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);
+	}
+
+	if (BTC_RSSI_HIGH(wifi_rssi_state1) && BTC_RSSI_HIGH(bt_rssi_state)) {
+		halbtc8723b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 7);
+	} else {
+		halbtc8723b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC,
+						     14);
+	}
+
+	if (BTC_RSSI_HIGH(bt_rssi_state)) {
+		if (ap_num < 10)
+			halbtc8723b2ant_tdma_duration_adjust(btcoexist, true,
+							     false, 2);
+
+		else
+			halbtc8723b2ant_tdma_duration_adjust(btcoexist, true,
+							     false, 3);
+	} else {
+		halbtc8723b2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 18);
+		btcoexist->btc_write_1byte(btcoexist, 0x456, 0x38);
+		btcoexist->btc_write_2byte(btcoexist, 0x42a, 0x0808);
+		btcoexist->btc_write_4byte(btcoexist, 0x430, 0x0);
+		btcoexist->btc_write_4byte(btcoexist, 0x434, 0x01010000);
+
+		if (ap_num < 10)
+			halbtc8723b2ant_tdma_duration_adjust(btcoexist, true,
+							     true, 2);
+
+		else
+			halbtc8723b2ant_tdma_duration_adjust(btcoexist, true,
+							     true, 3);
+	}
+
+	/* sw mechanism */
+	if (BTC_WIFI_BW_HT40 == wifi_bw) {
+		if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) ||
+		    (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
+			halbtc8723b2ant_sw_mechanism1(btcoexist, true, true,
+						      false, false);
+			halbtc8723b2ant_sw_mechanism2(btcoexist, true, false,
+						      false, 0x18);
+		} else {
+			halbtc8723b2ant_sw_mechanism1(btcoexist, true, true,
+						      false, false);
+			halbtc8723b2ant_sw_mechanism2(btcoexist, false, false,
+						      false, 0x18);
+		}
+	} else {
+		if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) ||
+		    (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
+			halbtc8723b2ant_sw_mechanism1(btcoexist, false, true,
+						      false, false);
+			halbtc8723b2ant_sw_mechanism2(btcoexist, true, false,
+						      false, 0x18);
+		} else {
+			halbtc8723b2ant_sw_mechanism1(btcoexist, false, true,
+						      false, false);
+			halbtc8723b2ant_sw_mechanism2(btcoexist, false, false,
+						      false, 0x18);
+		}
+	}
+}
+
+void halbtc8723b2ant_action_bt_whck_test(IN struct btc_coexist *btcoexist)
+{
+	halbtc8723b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);
+
+	/* sw all off */
+	halbtc8723b2ant_sw_mechanism1(btcoexist, false, false, false, false);
+	halbtc8723b2ant_sw_mechanism2(btcoexist, false, false, false, 0x18);
+
+	halbtc8723b2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 1);
+	halbtc8723b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0);
+}
+
+void halbtc8723b2ant_action_wifi_multi_port(IN struct btc_coexist *btcoexist)
+{
+	halbtc8723b2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6);
+	halbtc8723b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);
+
+	/* sw all off */
+	halbtc8723b2ant_sw_mechanism1(btcoexist, false, false, false, false);
+	halbtc8723b2ant_sw_mechanism2(btcoexist, false, false, false, 0x18);
+
+	/* hw all off */
+	/* btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1, 0xfffff, 0x0); */
+	halbtc8723b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0);
+
+	halbtc8723b2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 1);
+}
+
+void halbtc8723b2ant_run_coexist_mechanism(IN struct btc_coexist *btcoexist)
+{
+	u8				algorithm = 0;
+	u32				num_of_wifi_link = 0;
+	u32				wifi_link_status = 0;
+	struct  btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
+	boolean				miracast_plus_bt = false;
+	boolean				scan = false, link = false, roam = false;
+
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+		    "[BTCoex], RunCoexistMechanism()===>\n");
+	BTC_TRACE(trace_buf);
+
+	if (btcoexist->manual_control) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			"[BTCoex], RunCoexistMechanism(), return for Manual CTRL <===\n");
+		BTC_TRACE(trace_buf);
+		return;
+	}
+
+	if (coex_sta->under_ips) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], wifi is under IPS !!!\n");
+		BTC_TRACE(trace_buf);
+		return;
+	}
+
+	if (coex_sta->bt_whck_test) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], BT is under WHCK TEST!!!\n");
+		BTC_TRACE(trace_buf);
+		halbtc8723b2ant_action_bt_whck_test(btcoexist);
+		return;
+	}
+
+	algorithm = halbtc8723b2ant_action_algorithm(btcoexist);
+	if (coex_sta->c2h_bt_inquiry_page &&
+	    (BT_8723B_2ANT_COEX_ALGO_PANHS != algorithm)) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], BT is under inquiry/page scan !!\n");
+		BTC_TRACE(trace_buf);
+		halbtc8723b2ant_action_bt_inquiry(btcoexist);
+		return;
+	}
+
+	/*
+		if(coex_dm->need_recover0x948)
+		{
+			coex_dm->need_recover0x948 = false;
+			btcoexist->btc_write_4byte(btcoexist, 0x948, coex_dm->backup0x948);
+		}
+	*/
+
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_SCAN, &scan);
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_LINK, &link);
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_ROAM, &roam);
+
+	if (scan || link || roam) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], WiFi is under Link Process !!\n");
+		BTC_TRACE(trace_buf);
+		halbtc8723b2ant_action_wifi_link_process(btcoexist);
+		return;
+	}
+
+	/* for P2P */
+
+	btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_LINK_STATUS,
+			   &wifi_link_status);
+	num_of_wifi_link = wifi_link_status >> 16;
+
+	if ((num_of_wifi_link >= 2) ||
+	    (wifi_link_status & WIFI_P2P_GO_CONNECTED)) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			"############# [BTCoex],  Multi-Port num_of_wifi_link = %d, wifi_link_status = 0x%x\n",
+			    num_of_wifi_link, wifi_link_status);
+		BTC_TRACE(trace_buf);
+
+		if (bt_link_info->bt_link_exist)
+			miracast_plus_bt = true;
+		else
+			miracast_plus_bt = false;
+
+		btcoexist->btc_set(btcoexist, BTC_SET_BL_MIRACAST_PLUS_BT,
+				   &miracast_plus_bt);
+		halbtc8723b2ant_action_wifi_multi_port(btcoexist);
+
+		return;
+	}
+
+	miracast_plus_bt = false;
+	btcoexist->btc_set(btcoexist, BTC_SET_BL_MIRACAST_PLUS_BT,
+			   &miracast_plus_bt);
+
+	coex_dm->cur_algorithm = algorithm;
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], Algorithm = %d\n",
+		    coex_dm->cur_algorithm);
+	BTC_TRACE(trace_buf);
+
+	if (halbtc8723b2ant_is_common_action(btcoexist)) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], Action 2-Ant common.\n");
+		BTC_TRACE(trace_buf);
+		coex_dm->auto_tdma_adjust = false;
+	} else {
+		if (coex_dm->cur_algorithm != coex_dm->pre_algorithm) {
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				"[BTCoex], pre_algorithm=%d, cur_algorithm=%d\n",
+				coex_dm->pre_algorithm, coex_dm->cur_algorithm);
+			BTC_TRACE(trace_buf);
+			coex_dm->auto_tdma_adjust = false;
+		}
+		switch (coex_dm->cur_algorithm) {
+		case BT_8723B_2ANT_COEX_ALGO_SCO:
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				"[BTCoex], Action 2-Ant, algorithm = SCO.\n");
+			BTC_TRACE(trace_buf);
+			halbtc8723b2ant_action_sco(btcoexist);
+			break;
+		case BT_8723B_2ANT_COEX_ALGO_HID:
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				"[BTCoex], Action 2-Ant, algorithm = HID.\n");
+			BTC_TRACE(trace_buf);
+			halbtc8723b2ant_action_hid(btcoexist);
+			break;
+		case BT_8723B_2ANT_COEX_ALGO_A2DP:
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				"[BTCoex], Action 2-Ant, algorithm = A2DP.\n");
+			BTC_TRACE(trace_buf);
+			halbtc8723b2ant_action_a2dp(btcoexist);
+			break;
+		case BT_8723B_2ANT_COEX_ALGO_A2DP_PANHS:
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				"[BTCoex], Action 2-Ant, algorithm = A2DP+PAN(HS).\n");
+			BTC_TRACE(trace_buf);
+			halbtc8723b2ant_action_a2dp_pan_hs(btcoexist);
+			break;
+		case BT_8723B_2ANT_COEX_ALGO_PANEDR:
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				"[BTCoex], Action 2-Ant, algorithm = PAN(EDR).\n");
+			BTC_TRACE(trace_buf);
+			halbtc8723b2ant_action_pan_edr(btcoexist);
+			break;
+		case BT_8723B_2ANT_COEX_ALGO_PANHS:
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				"[BTCoex], Action 2-Ant, algorithm = HS mode.\n");
+			BTC_TRACE(trace_buf);
+			halbtc8723b2ant_action_pan_hs(btcoexist);
+			break;
+		case BT_8723B_2ANT_COEX_ALGO_PANEDR_A2DP:
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				"[BTCoex], Action 2-Ant, algorithm = PAN+A2DP.\n");
+			BTC_TRACE(trace_buf);
+			halbtc8723b2ant_action_pan_edr_a2dp(btcoexist);
+			break;
+		case BT_8723B_2ANT_COEX_ALGO_PANEDR_HID:
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				"[BTCoex], Action 2-Ant, algorithm = PAN(EDR)+HID.\n");
+			BTC_TRACE(trace_buf);
+			halbtc8723b2ant_action_pan_edr_hid(btcoexist);
+			break;
+		case BT_8723B_2ANT_COEX_ALGO_HID_A2DP_PANEDR:
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				"[BTCoex], Action 2-Ant, algorithm = HID+A2DP+PAN.\n");
+			BTC_TRACE(trace_buf);
+			halbtc8723b2ant_action_hid_a2dp_pan_edr(
+				btcoexist);
+			break;
+		case BT_8723B_2ANT_COEX_ALGO_HID_A2DP:
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				"[BTCoex], Action 2-Ant, algorithm = HID+A2DP.\n");
+			BTC_TRACE(trace_buf);
+			halbtc8723b2ant_action_hid_a2dp(btcoexist);
+			break;
+		default:
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				"[BTCoex], Action 2-Ant, algorithm = coexist All Off!!\n");
+			BTC_TRACE(trace_buf);
+			halbtc8723b2ant_coex_all_off(btcoexist);
+			break;
+		}
+		coex_dm->pre_algorithm = coex_dm->cur_algorithm;
+	}
+}
+
+void halbtc8723b2ant_wifi_off_hw_cfg(IN struct btc_coexist *btcoexist)
+{
+	boolean	is_in_mp_mode = false;
+	u8 h2c_parameter[2] = {0};
+	u32 fw_ver = 0;
+
+	/* set wlan_act to low */
+	btcoexist->btc_write_1byte(btcoexist, 0x76e, 0x4);
+
+	btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1, 0xfffff,
+			  0x780); /* WiFi goto standby while GNT_BT 0-->1 */
+	btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_FW_VER, &fw_ver);
+	if (fw_ver >= 0x180000) {
+		/* Use H2C to set GNT_BT to HIGH */
+		h2c_parameter[0] = 1;
+		btcoexist->btc_fill_h2c(btcoexist, 0x6E, 1, h2c_parameter);
+	} else
+		btcoexist->btc_write_1byte(btcoexist, 0x765, 0x18);
+
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_IS_IN_MP_MODE,
+			   &is_in_mp_mode);
+	if (!is_in_mp_mode)
+		btcoexist->btc_write_1byte_bitmask(btcoexist, 0x67, 0x20,
+			   0x0); /* BT select s0/s1 is controlled by BT */
+	else
+		btcoexist->btc_write_1byte_bitmask(btcoexist, 0x67, 0x20,
+			   0x1); /* BT select s0/s1 is controlled by WiFi */
+}
+
+void halbtc8723b2ant_init_hw_config(IN struct btc_coexist *btcoexist,
+				    IN boolean back_up)
+{
+	u8	u8tmp = 0;
+	u32	 vendor;
+
+
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+		    "[BTCoex], 2Ant Init HW Config!!\n");
+	BTC_TRACE(trace_buf);
+	btcoexist->btc_get(btcoexist, BTC_GET_U4_VENDOR, &vendor);
+	if (vendor == BTC_VENDOR_LENOVO)
+		coex_dm->switch_thres_offset = 0;
+	else if (vendor == BTC_VENDOR_ASUS)
+		coex_dm->switch_thres_offset = 0;
+	else
+		coex_dm->switch_thres_offset = 20;
+
+	/* 0xf0[15:12] --> Chip Cut information */
+	coex_sta->cut_version = (btcoexist->btc_read_1byte(btcoexist,
+				 0xf1) & 0xf0) >> 4;
+
+	/* backup rf 0x1e value */
+	coex_dm->bt_rf_0x1e_backup =
+		btcoexist->btc_get_rf_reg(btcoexist, BTC_RF_A, 0x1e, 0xfffff);
+
+	/* 0x790[5:0]=0x5 */
+	u8tmp = btcoexist->btc_read_1byte(btcoexist, 0x790);
+	u8tmp &= 0xc0;
+	u8tmp |= 0x5;
+	btcoexist->btc_write_1byte(btcoexist, 0x790, u8tmp);
+
+	/* Antenna config	 */
+	halbtc8723b2ant_set_ant_path(btcoexist, BTC_ANT_WIFI_AT_MAIN, true,
+				     false);
+	coex_sta->dis_ver_info_cnt = 0;
+
+	/* PTA parameter */
+	halbtc8723b2ant_coex_table_with_type(btcoexist, FORCE_EXEC, 0);
+
+	/* Enable counter statistics */
+	btcoexist->btc_write_1byte(btcoexist, 0x76e,
+			   0x4); /* 0x76e[3] =1, WLAN_Act control by PTA */
+	btcoexist->btc_write_1byte(btcoexist, 0x778, 0x3);
+	btcoexist->btc_write_1byte_bitmask(btcoexist, 0x40, 0x20, 0x1);
+
+	/* Give bt_coex_supported_version the default value */
+	coex_sta->bt_coex_supported_version = 0;
+
+}
+
+/* ************************************************************
+ * work around function start with wa_halbtc8723b2ant_
+ * ************************************************************
+ * ************************************************************
+ * extern function start with ex_halbtc8723b2ant_
+ * ************************************************************ */
+void ex_halbtc8723b2ant_power_on_setting(IN struct btc_coexist *btcoexist)
+{
+	struct  btc_board_info	*board_info = &btcoexist->board_info;
+	u16 u16tmp = 0x0;
+	u32				value = 0;
+	u32    u32tmp_1[4];
+
+	btcoexist->btc_write_1byte(btcoexist, 0x67, 0x20);
+
+	/* enable BB, REG_SYS_FUNC_EN such that we can write 0x948 correctly. */
+	u16tmp = btcoexist->btc_read_2byte(btcoexist, 0x2);
+	btcoexist->btc_write_2byte(btcoexist, 0x2, u16tmp | BIT(0) | BIT(1));
+
+	btcoexist->btc_write_4byte(btcoexist, 0x948, 0x0);
+
+	if (btcoexist->chip_interface == BTC_INTF_USB) {
+		/* fixed at S0 for USB interface */
+		board_info->btdm_ant_pos = BTC_ANTENNA_AT_AUX_PORT;
+	} else {
+		/* for PCIE and SDIO interface, we check efuse 0xc3[6] */
+		if (board_info->single_ant_path == 0) {
+			/* set to S1 */
+			board_info->btdm_ant_pos = BTC_ANTENNA_AT_MAIN_PORT;
+		} else if (board_info->single_ant_path == 1) {
+			/* set to S0 */
+			board_info->btdm_ant_pos = BTC_ANTENNA_AT_AUX_PORT;
+		}
+		btcoexist->btc_set(btcoexist, BTC_SET_ACT_ANTPOSREGRISTRY_CTRL,
+				   &value);
+	}
+}
+
+void ex_halbtc8723b2ant_pre_load_firmware(IN struct btc_coexist *btcoexist)
+{
+	struct  btc_board_info	*board_info = &btcoexist->board_info;
+	u8 u8tmp = 0x4; /* Set BIT2 by default since it's 2ant case */
+
+	/* */
+	/* S0 or S1 setting and Local register setting(By the setting fw can get ant number, S0/S1, ... info) */
+	/* Local setting bit define */
+	/*	BIT0: "0" for no antenna inverse; "1" for antenna inverse  */
+	/*	BIT1: "0" for internal switch; "1" for external switch */
+	/*	BIT2: "0" for one antenna; "1" for two antenna */
+	/* NOTE: here default all internal switch and 1-antenna ==> BIT1=0 and BIT2=0 */
+	if (btcoexist->chip_interface == BTC_INTF_USB) {
+		/* fixed at S0 for USB interface */
+		u8tmp |= 0x1;	/* antenna inverse */
+		btcoexist->btc_write_local_reg_1byte(btcoexist, 0xfe08, u8tmp);
+	} else {
+		if (board_info->single_ant_path == 1) {
+			/* set to S0 */
+			u8tmp |= 0x1;	/* antenna inverse */
+		}
+
+		if (btcoexist->chip_interface == BTC_INTF_PCI)
+			btcoexist->btc_write_local_reg_1byte(btcoexist, 0x384,
+							     u8tmp);
+		else if (btcoexist->chip_interface == BTC_INTF_SDIO)
+			btcoexist->btc_write_local_reg_1byte(btcoexist, 0x60,
+							     u8tmp);
+	}
+}
+
+void ex_halbtc8723b2ant_init_hw_config(IN struct btc_coexist *btcoexist,
+				       IN boolean wifi_only)
+{
+	halbtc8723b2ant_init_hw_config(btcoexist, true);
+}
+
+void ex_halbtc8723b2ant_init_coex_dm(IN struct btc_coexist *btcoexist)
+{
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+		    "[BTCoex], Coex Mechanism Init!!\n");
+	BTC_TRACE(trace_buf);
+
+	halbtc8723b2ant_init_coex_dm(btcoexist);
+}
+
+void ex_halbtc8723b2ant_display_coex_info(IN struct btc_coexist *btcoexist)
+{
+	struct  btc_board_info		*board_info = &btcoexist->board_info;
+	struct  btc_bt_link_info	*bt_link_info = &btcoexist->bt_link_info;
+	u8				*cli_buf = btcoexist->cli_buf;
+	u8				u8tmp[4], i, bt_info_ext, ps_tdma_case = 0;
+	u32				u32tmp[4];
+	u32				fa_ofdm, fa_cck, cca_ofdm, cca_cck;
+	u32				fw_ver = 0, bt_patch_ver = 0;
+	u32				bt_coex_ver = 0;
+	static u8			pop_report_in_10s = 0;
+	u32				phyver = 0;
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+		   "\r\n ============[BT Coexist info]============");
+	CL_PRINTF(cli_buf);
+
+	if (btcoexist->manual_control) {
+		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+			"\r\n ============[Under Manual Control]============");
+		CL_PRINTF(cli_buf);
+		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+			   "\r\n ==========================================");
+		CL_PRINTF(cli_buf);
+	}
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d ",
+		   "Ant PG number/ Ant mechanism:",
+		   board_info->pg_ant_num, board_info->btdm_ant_num);
+	CL_PRINTF(cli_buf);
+
+	/* btcoexist->btc_get(btcoexist, BTC_GET_U4_BT_PATCH_VER, &bt_patch_ver); */
+	bt_patch_ver = btcoexist->bt_info.bt_get_fw_ver;
+	btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_FW_VER, &fw_ver);
+	phyver = btcoexist->btc_get_bt_phydm_version(btcoexist);
+	bt_coex_ver = coex_sta->bt_coex_supported_version & 0xff;
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+		   "\r\n %-35s = %d_%02x/ 0x%02x/ 0x%02x (%s)",
+		   "CoexVer WL/  BT_Desired/ BT_Report",
+		   glcoex_ver_date_8723b_2ant, glcoex_ver_8723b_2ant,
+		   glcoex_ver_btdesired_8723b_2ant,
+		   bt_coex_ver,
+		   (bt_coex_ver == 0xff ? "Unknown" :
+		    (bt_coex_ver >= glcoex_ver_btdesired_8723b_2ant ?
+		     "Match" : "Mis-Match")));
+	CL_PRINTF(cli_buf);
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+		   "\r\n %-35s = 0x%x/ 0x%x/ v%d/ %c",
+		   "W_FW/ B_FW/ Phy/ Kt",
+		   fw_ver, bt_patch_ver, phyver,
+		   coex_sta->cut_version + 65);
+	CL_PRINTF(cli_buf);
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %02x %02x %02x ",
+		   "Wifi channel informed to BT",
+		   coex_dm->wifi_chnl_info[0], coex_dm->wifi_chnl_info[1],
+		   coex_dm->wifi_chnl_info[2]);
+	CL_PRINTF(cli_buf);
+
+	/* wifi status */
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s",
+		   "============[Wifi Status]============");
+	CL_PRINTF(cli_buf);
+	btcoexist->btc_disp_dbg_msg(btcoexist, BTC_DBG_DISP_WIFI_STATUS);
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s",
+		   "============[BT Status]============");
+	CL_PRINTF(cli_buf);
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s",
+		   "BT Abnormal scan",
+		   (coex_sta->bt_abnormal_scan) ? "Yes" : "No");
+	CL_PRINTF(cli_buf);
+
+	pop_report_in_10s++;
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = [%s/ %d/ %d/ %d] ",
+		   "BT [status/ rssi/ retryCnt/ popCnt]",
+		   ((coex_sta->bt_disabled) ? ("disabled") :	((
+		   coex_sta->c2h_bt_inquiry_page) ? ("inquiry/page scan")
+			   : ((BT_8723B_1ANT_BT_STATUS_NON_CONNECTED_IDLE ==
+			       coex_dm->bt_status) ? "non-connected idle" :
+		((BT_8723B_2ANT_BT_STATUS_CONNECTED_IDLE == coex_dm->bt_status)
+				       ? "connected-idle" : "busy")))),
+		   coex_sta->bt_rssi - 100, coex_sta->bt_retry_cnt,
+		   coex_sta->pop_event_cnt);
+	CL_PRINTF(cli_buf);
+
+	if (pop_report_in_10s >= 5) {
+		coex_sta->pop_event_cnt = 0;
+		pop_report_in_10s = 0;
+	}
+
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+		   "\r\n %-35s = %d / %d / %d / %d / %d / %d",
+		   "SCO/HID/PAN/A2DP/NameReq/WHQL",
+		   bt_link_info->sco_exist, bt_link_info->hid_exist,
+		   bt_link_info->pan_exist, bt_link_info->a2dp_exist,
+		   coex_sta->c2h_bt_remote_name_req,
+		   coex_sta->bt_whck_test);
+	CL_PRINTF(cli_buf);
+
+	{
+		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s",
+			   "BT Role",
+			   (bt_link_info->slave_role) ? "Slave" : "Master");
+		CL_PRINTF(cli_buf);
+	}
+
+	bt_info_ext = coex_sta->bt_info_ext;
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s / %d",
+		   "A2DP Rate/Bitpool",
+		(bt_info_ext & BIT(0)) ? "BR" : "EDR", coex_sta->a2dp_bit_pool);
+	CL_PRINTF(cli_buf);
+
+	for (i = 0; i < BT_INFO_SRC_8723B_2ANT_MAX; i++) {
+		if (coex_sta->bt_info_c2h_cnt[i]) {
+			CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+				"\r\n %-35s = %02x %02x %02x %02x %02x %02x %02x(%d)",
+				   glbt_info_src_8723b_2ant[i],
+				   coex_sta->bt_info_c2h[i][0],
+				   coex_sta->bt_info_c2h[i][1],
+				   coex_sta->bt_info_c2h[i][2],
+				   coex_sta->bt_info_c2h[i][3],
+				   coex_sta->bt_info_c2h[i][4],
+				   coex_sta->bt_info_c2h[i][5],
+				   coex_sta->bt_info_c2h[i][6],
+				   coex_sta->bt_info_c2h_cnt[i]);
+			CL_PRINTF(cli_buf);
+		}
+	}
+
+	/* Sw mechanism	 */
+	if (btcoexist->manual_control)
+		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s",
+			"============[Sw mechanism] (before Manual)============");
+	else
+		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s",
+			   "============[Sw mechanism]============");
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d ",
+		   "SM1[ShRf/ LpRA/ LimDig]",
+		   coex_dm->cur_rf_rx_lpf_shrink, coex_dm->cur_low_penalty_ra,
+		   coex_dm->limited_dig);
+	CL_PRINTF(cli_buf);
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d(0x%x) ",
+		   "SM2[AgcT/ AdcB/ SwDacSwing(lvl)]",
+		   coex_dm->cur_agc_table_en, coex_dm->cur_adc_back_off,
+		   coex_dm->cur_dac_swing_on, coex_dm->cur_dac_swing_lvl);
+	CL_PRINTF(cli_buf);
+
+	/* Fw mechanism		 */
+	if (btcoexist->manual_control)
+		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s",
+			"============[Fw mechanism] (before Manual) ============");
+	else
+		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s",
+			   "============[Fw mechanism]============");
+
+	ps_tdma_case = coex_dm->cur_ps_tdma;
+
+	if (coex_dm->is_switch_to_1dot5_ant)
+		ps_tdma_case = ps_tdma_case + 100;
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+		   "\r\n %-35s = %02x %02x %02x %02x %02x case-%d (%s,%s)",
+		   "PS TDMA",
+		   coex_dm->ps_tdma_para[0], coex_dm->ps_tdma_para[1],
+		   coex_dm->ps_tdma_para[2], coex_dm->ps_tdma_para[3],
+		   coex_dm->ps_tdma_para[4], ps_tdma_case,
+		   (coex_dm->cur_ps_tdma_on ? "On" : "Off"),
+		   (coex_dm->auto_tdma_adjust ? "Adj" : "Fix"));
+	CL_PRINTF(cli_buf);
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d",
+		   "Coex Table Type",
+		   coex_sta->coex_table_type);
+	CL_PRINTF(cli_buf);
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d ",
+		   "DecBtPwr/ IgnWlanAct",
+		   coex_dm->cur_bt_dec_pwr_lvl, coex_dm->cur_ignore_wlan_act);
+	CL_PRINTF(cli_buf);
+
+	/* Hw setting		 */
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s",
+		   "============[Hw setting]============");
+	CL_PRINTF(cli_buf);
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x",
+		   "RF-A, 0x1e initVal",
+		   coex_dm->bt_rf_0x1e_backup);
+	CL_PRINTF(cli_buf);
+
+	u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x778);
+	u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x880);
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x",
+		   "0x778/0x880[29:25]",
+		   u8tmp[0], (u32tmp[0] & 0x3e000000) >> 25);
+	CL_PRINTF(cli_buf);
+
+
+	u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x948);
+	u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x67);
+	u8tmp[1] = btcoexist->btc_read_1byte(btcoexist, 0x765);
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x/ 0x%x",
+		   "0x948/ 0x67[5] / 0x765",
+		   u32tmp[0], ((u8tmp[0] & 0x20) >> 5), u8tmp[1]);
+	CL_PRINTF(cli_buf);
+
+	u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x92c);
+	u32tmp[1] = btcoexist->btc_read_4byte(btcoexist, 0x930);
+	u32tmp[2] = btcoexist->btc_read_4byte(btcoexist, 0x944);
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x/ 0x%x",
+		   "0x92c[1:0]/ 0x930[7:0]/0x944[1:0]",
+		   u32tmp[0] & 0x3, u32tmp[1] & 0xff, u32tmp[2] & 0x3);
+	CL_PRINTF(cli_buf);
+
+
+	u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x39);
+	u8tmp[1] = btcoexist->btc_read_1byte(btcoexist, 0x40);
+	u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x4c);
+	u8tmp[2] = btcoexist->btc_read_1byte(btcoexist, 0x64);
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+		   "\r\n %-35s = 0x%x/ 0x%x/ 0x%x/ 0x%x",
+		   "0x38[11]/0x40/0x4c[24:23]/0x64[0]",
+		   ((u8tmp[0] & 0x8) >> 3), u8tmp[1],
+		   ((u32tmp[0] & 0x01800000) >> 23), u8tmp[2] & 0x1);
+	CL_PRINTF(cli_buf);
+
+	u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x550);
+	u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x522);
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x",
+		   "0x550(bcn ctrl)/0x522",
+		   u32tmp[0], u8tmp[0]);
+	CL_PRINTF(cli_buf);
+
+	u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0xc50);
+	u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x49c);
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x",
+		   "0xc50(dig)/0x49c(null-drop)",
+		   u32tmp[0] & 0xff, u8tmp[0]);
+	CL_PRINTF(cli_buf);
+
+	fa_ofdm = btcoexist->btc_phydm_query_PHY_counter(btcoexist,
+			PHYDM_INFO_FA_OFDM);
+	fa_cck = btcoexist->btc_phydm_query_PHY_counter(btcoexist,
+			PHYDM_INFO_FA_CCK);
+	cca_ofdm = btcoexist->btc_phydm_query_PHY_counter(btcoexist,
+			PHYDM_INFO_CCA_OFDM);
+	cca_cck = btcoexist->btc_phydm_query_PHY_counter(btcoexist,
+			PHYDM_INFO_CCA_CCK);
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+		   "\r\n %-35s = 0x%x/ 0x%x/ 0x%x/ 0x%x",
+		   "CCK-CCA/CCK-FA/OFDM-CCA/OFDM-FA",
+		   cca_cck, fa_cck, cca_ofdm, fa_ofdm);
+	CL_PRINTF(cli_buf);
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d/ %d",
+		   "CRC_OK CCK/11g/11n/11n-agg",
+		   coex_sta->crc_ok_cck, coex_sta->crc_ok_11g,
+		   coex_sta->crc_ok_11n, coex_sta->crc_ok_11n_vht);
+	CL_PRINTF(cli_buf);
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d/ %d",
+		   "CRC_Err CCK/11g/11n/11n-agg",
+		   coex_sta->crc_err_cck, coex_sta->crc_err_11g,
+		   coex_sta->crc_err_11n, coex_sta->crc_err_11n_vht);
+	CL_PRINTF(cli_buf);
+
+	u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x6c0);
+	u32tmp[1] = btcoexist->btc_read_4byte(btcoexist, 0x6c4);
+	u32tmp[2] = btcoexist->btc_read_4byte(btcoexist, 0x6c8);
+	u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x6cc);
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+		   "\r\n %-35s = 0x%x/ 0x%x/ 0x%x/ 0x%x",
+		   "0x6c0/0x6c4/0x6c8/0x6cc(coexTable)",
+		   u32tmp[0], u32tmp[1], u32tmp[2], u8tmp[0]);
+	CL_PRINTF(cli_buf);
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d",
+		   "0x770(high-pri rx/tx)",
+		   coex_sta->high_priority_rx, coex_sta->high_priority_tx);
+	CL_PRINTF(cli_buf);
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d",
+		   "0x774(low-pri rx/tx)",
+		   coex_sta->low_priority_rx, coex_sta->low_priority_tx);
+	CL_PRINTF(cli_buf);
+#if (BT_AUTO_REPORT_ONLY_8723B_2ANT == 1)
+	/* halbtc8723b2ant_monitor_bt_ctr(btcoexist); */
+#endif
+	btcoexist->btc_disp_dbg_msg(btcoexist, BTC_DBG_DISP_COEX_STATISTICS);
+}
+
+
+void ex_halbtc8723b2ant_ips_notify(IN struct btc_coexist *btcoexist, IN u8 type)
+{
+	if (BTC_IPS_ENTER == type) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], IPS ENTER notify\n");
+		BTC_TRACE(trace_buf);
+		coex_sta->under_ips = true;
+		halbtc8723b2ant_wifi_off_hw_cfg(btcoexist);
+		halbtc8723b2ant_ignore_wlan_act(btcoexist, FORCE_EXEC, true);
+		halbtc8723b2ant_coex_all_off(btcoexist);
+	} else if (BTC_IPS_LEAVE == type) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], IPS LEAVE notify\n");
+		BTC_TRACE(trace_buf);
+		coex_sta->under_ips = false;
+		halbtc8723b2ant_init_hw_config(btcoexist, false);
+		halbtc8723b2ant_init_coex_dm(btcoexist);
+		halbtc8723b2ant_query_bt_info(btcoexist);
+	}
+}
+
+void ex_halbtc8723b2ant_lps_notify(IN struct btc_coexist *btcoexist, IN u8 type)
+{
+	if (BTC_LPS_ENABLE == type) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], LPS ENABLE notify\n");
+		BTC_TRACE(trace_buf);
+		coex_sta->under_lps = true;
+	} else if (BTC_LPS_DISABLE == type) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], LPS DISABLE notify\n");
+		BTC_TRACE(trace_buf);
+		coex_sta->under_lps = false;
+	}
+}
+
+void ex_halbtc8723b2ant_scan_notify(IN struct btc_coexist *btcoexist,
+				    IN u8 type)
+{
+	u32	u32tmp;
+	u8	u8tmpa, u8tmpb;
+
+
+
+	u32tmp = btcoexist->btc_read_4byte(btcoexist, 0x948);
+	u8tmpa = btcoexist->btc_read_1byte(btcoexist, 0x765);
+	u8tmpb = btcoexist->btc_read_1byte(btcoexist, 0x76e);
+
+	if (BTC_SCAN_START == type) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], SCAN START notify\n");
+		BTC_TRACE(trace_buf);
+		halbtc8723b2ant_set_ant_path(btcoexist, BTC_ANT_WIFI_AT_MAIN,
+					     false, false);
+	} else if (BTC_SCAN_FINISH == type) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], SCAN FINISH notify\n");
+		BTC_TRACE(trace_buf);
+		btcoexist->btc_get(btcoexist, BTC_GET_U1_AP_NUM,
+				   &coex_sta->scan_ap_num);
+	}
+
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+		"############# [BTCoex], 0x948=0x%x, 0x765=0x%x, 0x76e=0x%x\n",
+		    u32tmp,  u8tmpa, u8tmpb);
+	BTC_TRACE(trace_buf);
+}
+
+void ex_halbtc8723b2ant_connect_notify(IN struct btc_coexist *btcoexist,
+				       IN u8 type)
+{
+	if (BTC_ASSOCIATE_START == type) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], CONNECT START notify\n");
+		BTC_TRACE(trace_buf);
+		halbtc8723b2ant_set_ant_path(btcoexist, BTC_ANT_WIFI_AT_MAIN,
+					     false, false);
+	} else if (BTC_ASSOCIATE_FINISH == type) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], CONNECT FINISH notify\n");
+		BTC_TRACE(trace_buf);
+	}
+}
+
+void ex_halbtc8723b2ant_media_status_notify(IN struct btc_coexist *btcoexist,
+		IN u8 type)
+{
+	u8			h2c_parameter[3] = {0};
+	u32			wifi_bw;
+	u8			wifi_central_chnl;
+	u8			ap_num = 0;
+
+	if (BTC_MEDIA_CONNECT == type) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], MEDIA connect notify\n");
+		BTC_TRACE(trace_buf);
+		halbtc8723b2ant_set_ant_path(btcoexist, BTC_ANT_WIFI_AT_MAIN,
+					     false, false);
+	} else {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], MEDIA disconnect notify\n");
+		BTC_TRACE(trace_buf);
+	}
+
+	/* only 2.4G we need to inform bt the chnl mask */
+	btcoexist->btc_get(btcoexist, BTC_GET_U1_WIFI_CENTRAL_CHNL,
+			   &wifi_central_chnl);
+	if ((BTC_MEDIA_CONNECT == type) &&
+	    (wifi_central_chnl <= 14)) {
+		h2c_parameter[0] = 0x1;
+		h2c_parameter[1] = wifi_central_chnl;
+		btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw);
+		if (BTC_WIFI_BW_HT40 == wifi_bw)
+			h2c_parameter[2] = 0x30;
+		else {
+			btcoexist->btc_get(btcoexist, BTC_GET_U1_AP_NUM,
+					   &ap_num);
+			if (ap_num < 10)
+				h2c_parameter[2] = 0x30;
+			else
+				h2c_parameter[2] = 0x20;
+		}
+	}
+
+	coex_dm->wifi_chnl_info[0] = h2c_parameter[0];
+	coex_dm->wifi_chnl_info[1] = h2c_parameter[1];
+	coex_dm->wifi_chnl_info[2] = h2c_parameter[2];
+
+	btcoexist->btc_fill_h2c(btcoexist, 0x66, 3, h2c_parameter);
+}
+
+void ex_halbtc8723b2ant_specific_packet_notify(IN struct btc_coexist *btcoexist,
+		IN u8 type)
+{
+	if (type == BTC_PACKET_DHCP) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], DHCP Packet notify\n");
+		BTC_TRACE(trace_buf);
+	}
+}
+
+void ex_halbtc8723b2ant_bt_info_notify(IN struct btc_coexist *btcoexist,
+				       IN u8 *tmp_buf, IN u8 length)
+{
+	u8			bt_info = 0;
+	u8			i, rsp_source = 0;
+	boolean			bt_busy = false, limited_dig = false;
+	boolean			wifi_connected = false;
+
+	coex_sta->c2h_bt_info_req_sent = false;
+
+	rsp_source = tmp_buf[0] & 0xf;
+	if (rsp_source >= BT_INFO_SRC_8723B_2ANT_MAX)
+		rsp_source = BT_INFO_SRC_8723B_2ANT_WIFI_FW;
+	coex_sta->bt_info_c2h_cnt[rsp_source]++;
+
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+		    "[BTCoex], Bt info[%d], length=%d, hex data=[", rsp_source,
+		    length);
+	BTC_TRACE(trace_buf);
+	for (i = 0; i < length; i++) {
+		coex_sta->bt_info_c2h[rsp_source][i] = tmp_buf[i];
+		if (i == 1)
+			bt_info = tmp_buf[i];
+		if (i == length - 1) {
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "0x%02x]\n",
+				    tmp_buf[i]);
+			BTC_TRACE(trace_buf);
+		} else {
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "0x%02x, ",
+				    tmp_buf[i]);
+			BTC_TRACE(trace_buf);
+		}
+	}
+
+	if (btcoexist->manual_control) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			"[BTCoex], BtInfoNotify(), return for Manual CTRL<===\n");
+		BTC_TRACE(trace_buf);
+		return;
+	}
+
+	/* if 0xff, it means BT is under WHCK test */
+	if (bt_info == 0xff)
+		coex_sta->bt_whck_test = true;
+	else
+		coex_sta->bt_whck_test = false;
+
+	if (BT_INFO_SRC_8723B_2ANT_WIFI_FW != rsp_source) {
+		coex_sta->bt_retry_cnt =	/* [3:0] */
+			coex_sta->bt_info_c2h[rsp_source][2] & 0xf;
+
+		if (coex_sta->bt_retry_cnt >= 1)
+			coex_sta->pop_event_cnt++;
+
+		coex_sta->bt_rssi =
+			coex_sta->bt_info_c2h[rsp_source][3] * 2 + 10;
+
+		coex_sta->bt_info_ext =
+			coex_sta->bt_info_c2h[rsp_source][4];
+
+		if (coex_sta->bt_info_c2h[rsp_source][2] & 0x20)
+			coex_sta->c2h_bt_remote_name_req = true;
+		else
+			coex_sta->c2h_bt_remote_name_req = false;
+
+		if (coex_sta->bt_info_c2h[rsp_source][1] == 0x49) {
+			coex_sta->a2dp_bit_pool =
+				coex_sta->bt_info_c2h[rsp_source][6];
+		} else
+			coex_sta->a2dp_bit_pool = 0;
+
+		coex_sta->bt_tx_rx_mask = (coex_sta->bt_info_c2h[rsp_source][2]
+					   & 0x40);
+		btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_TX_RX_MASK,
+				   &coex_sta->bt_tx_rx_mask);
+		if (coex_sta->bt_tx_rx_mask) {
+			/* BT into is responded by BT FW and BT RF REG 0x3C != 0x01 => Need to switch BT TRx Mask */
+			/* BT TRx mask off */
+			btcoexist->btc_set_bt_trx_mask(btcoexist, 0);
+
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				"############# [BTCoex], BT TRx Mask off for BT Info Notify\n");
+			BTC_TRACE(trace_buf);
+#if 0
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				"[BTCoex], Switch BT TRx Mask since BT RF REG 0x3C != 0x01\n");
+			BTC_TRACE(trace_buf);
+			btcoexist->btc_set_bt_reg(btcoexist, BTC_BT_REG_RF,
+						  0x3c, 0x01);
+#endif
+		}
+
+		/* Here we need to resend some wifi info to BT */
+		/* because bt is reset and loss of the info. */
+		if ((coex_sta->bt_info_ext & BIT(1))) {
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				"[BTCoex], BT ext info bit1 check, send wifi BW&Chnl to BT!!\n");
+			BTC_TRACE(trace_buf);
+			btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED,
+					   &wifi_connected);
+			if (wifi_connected)
+				ex_halbtc8723b2ant_media_status_notify(
+					btcoexist, BTC_MEDIA_CONNECT);
+			else
+				ex_halbtc8723b2ant_media_status_notify(
+					btcoexist, BTC_MEDIA_DISCONNECT);
+		}
+
+		if ((coex_sta->bt_info_ext & BIT(3))) {
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				"[BTCoex], BT ext info bit3 check, set BT NOT to ignore Wlan active!!\n");
+			BTC_TRACE(trace_buf);
+			halbtc8723b2ant_ignore_wlan_act(btcoexist, FORCE_EXEC,
+							false);
+		} else {
+			/* BT already NOT ignore Wlan active, do nothing here. */
+		}
+#if (BT_AUTO_REPORT_ONLY_8723B_2ANT == 0)
+		if ((coex_sta->bt_info_ext & BIT(4))) {
+			/* BT auto report already enabled, do nothing */
+		} else
+			halbtc8723b2ant_bt_auto_report(btcoexist, FORCE_EXEC,
+						       true);
+#endif
+	}
+
+	/* check BIT2 first ==> check if bt is under inquiry or page scan */
+	if (bt_info & BT_INFO_8723B_2ANT_B_INQ_PAGE)
+		coex_sta->c2h_bt_inquiry_page = true;
+	else
+		coex_sta->c2h_bt_inquiry_page = false;
+
+	/* set link exist status */
+	if (!(bt_info & BT_INFO_8723B_2ANT_B_CONNECTION)) {
+		coex_sta->bt_link_exist = false;
+		coex_sta->pan_exist = false;
+		coex_sta->a2dp_exist = false;
+		coex_sta->hid_exist = false;
+		coex_sta->sco_exist = false;
+	} else {	/* connection exists */
+		coex_sta->bt_link_exist = true;
+		if (bt_info & BT_INFO_8723B_2ANT_B_FTP)
+			coex_sta->pan_exist = true;
+		else
+			coex_sta->pan_exist = false;
+		if (bt_info & BT_INFO_8723B_2ANT_B_A2DP)
+			coex_sta->a2dp_exist = true;
+		else
+			coex_sta->a2dp_exist = false;
+		if (bt_info & BT_INFO_8723B_2ANT_B_HID)
+			coex_sta->hid_exist = true;
+		else
+			coex_sta->hid_exist = false;
+		if (bt_info & BT_INFO_8723B_2ANT_B_SCO_ESCO)
+			coex_sta->sco_exist = true;
+		else
+			coex_sta->sco_exist = false;
+
+		if ((coex_sta->hid_exist == false) &&
+		    (coex_sta->c2h_bt_inquiry_page == false) &&
+		    (coex_sta->sco_exist == false)) {
+			if (coex_sta->high_priority_tx  +
+			    coex_sta->high_priority_rx >= 160) {
+				coex_sta->hid_exist = true;
+				bt_info = bt_info | 0x28;
+			}
+		}
+	}
+
+	halbtc8723b2ant_update_bt_link_info(btcoexist);
+
+	if (!(bt_info & BT_INFO_8723B_2ANT_B_CONNECTION)) {
+		coex_dm->bt_status = BT_8723B_2ANT_BT_STATUS_NON_CONNECTED_IDLE;
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			"[BTCoex], BtInfoNotify(), BT Non-Connected idle!!!\n");
+		BTC_TRACE(trace_buf);
+	} else if (bt_info ==
+		BT_INFO_8723B_2ANT_B_CONNECTION) {	/* connection exists but no busy */
+		coex_dm->bt_status = BT_8723B_2ANT_BT_STATUS_CONNECTED_IDLE;
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], BtInfoNotify(), BT Connected-idle!!!\n");
+		BTC_TRACE(trace_buf);
+	} else if ((bt_info & BT_INFO_8723B_2ANT_B_SCO_ESCO) ||
+		   (bt_info & BT_INFO_8723B_2ANT_B_SCO_BUSY)) {
+		coex_dm->bt_status = BT_8723B_2ANT_BT_STATUS_SCO_BUSY;
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], BtInfoNotify(), BT SCO busy!!!\n");
+		BTC_TRACE(trace_buf);
+	} else if (bt_info & BT_INFO_8723B_2ANT_B_ACL_BUSY) {
+		coex_dm->bt_status = BT_8723B_2ANT_BT_STATUS_ACL_BUSY;
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], BtInfoNotify(), BT ACL busy!!!\n");
+		BTC_TRACE(trace_buf);
+	} else {
+		coex_dm->bt_status = BT_8723B_2ANT_BT_STATUS_MAX;
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			"[BTCoex], BtInfoNotify(), BT Non-Defined state!!!\n");
+		BTC_TRACE(trace_buf);
+	}
+
+	if ((BT_8723B_2ANT_BT_STATUS_ACL_BUSY == coex_dm->bt_status) ||
+	    (BT_8723B_2ANT_BT_STATUS_SCO_BUSY == coex_dm->bt_status) ||
+	    (BT_8723B_2ANT_BT_STATUS_ACL_SCO_BUSY == coex_dm->bt_status)) {
+		bt_busy = true;
+		limited_dig = true;
+	} else {
+		bt_busy = false;
+		limited_dig = false;
+	}
+
+	btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_TRAFFIC_BUSY, &bt_busy);
+
+	coex_dm->limited_dig = limited_dig;
+	btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_LIMITED_DIG, &limited_dig);
+
+	halbtc8723b2ant_run_coexist_mechanism(btcoexist);
+}
+
+void ex_halbtc8723b2ant_halt_notify(IN struct btc_coexist *btcoexist)
+{
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], Halt notify\n");
+	BTC_TRACE(trace_buf);
+
+	halbtc8723b2ant_wifi_off_hw_cfg(btcoexist);
+	/* remove due to interrupt is disabled that polling c2h will fail and delay 100ms. */
+	/* btcoexist->btc_set_bt_reg(btcoexist, BTC_BT_REG_RF, 0x3c, 0x15); */ /*BT goto standby while GNT_BT 1-->0 */
+	halbtc8723b2ant_ignore_wlan_act(btcoexist, FORCE_EXEC, true);
+
+	ex_halbtc8723b2ant_media_status_notify(btcoexist, BTC_MEDIA_DISCONNECT);
+}
+
+void ex_halbtc8723b2ant_pnp_notify(IN struct btc_coexist *btcoexist,
+				   IN u8 pnp_state)
+{
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], Pnp notify\n");
+	BTC_TRACE(trace_buf);
+
+	if (BTC_WIFI_PNP_SLEEP == pnp_state) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], Pnp notify to SLEEP\n");
+		BTC_TRACE(trace_buf);
+
+		/* Sinda 20150819, workaround for driver skip leave IPS/LPS to speed up sleep time. */
+		/* Driver do not leave IPS/LPS when driver is going to sleep, so BTCoexistence think wifi is still under IPS/LPS */
+		/* BT should clear UnderIPS/UnderLPS state to avoid mismatch state after wakeup. */
+		coex_sta->under_ips = false;
+		coex_sta->under_lps = false;
+	} else if (BTC_WIFI_PNP_WAKE_UP == pnp_state) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], Pnp notify to WAKE UP\n");
+		BTC_TRACE(trace_buf);
+		halbtc8723b2ant_init_hw_config(btcoexist, false);
+		halbtc8723b2ant_init_coex_dm(btcoexist);
+		halbtc8723b2ant_query_bt_info(btcoexist);
+	}
+}
+
+void ex_halbtc8723b2ant_periodical(IN struct btc_coexist *btcoexist)
+{
+	u32 bt_patch_ver;
+
+	struct  btc_bt_link_info	*bt_link_info = &btcoexist->bt_link_info;
+
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+		"[BTCoex], ==========================Periodical===========================\n");
+	BTC_TRACE(trace_buf);
+	if (coex_sta->dis_ver_info_cnt <= 5) {
+		coex_sta->dis_ver_info_cnt += 1;
+		if (coex_sta->dis_ver_info_cnt == 3) {
+			/* Antenna config to set 0x765 = 0x0 (GNT_BT control by PTA) after initial */
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				    "[BTCoex], Set GNT_BT control by PTA\n");
+			BTC_TRACE(trace_buf);
+			halbtc8723b2ant_set_ant_path(btcoexist,
+				     BTC_ANT_WIFI_AT_MAIN, false, false);
+		}
+	}
+
+	if (((coex_sta->bt_coex_supported_version == 0) ||
+	     (coex_sta->bt_coex_supported_version == 0xffff)) && (!coex_sta->bt_disabled))
+		btcoexist->btc_get(btcoexist, BTC_GET_U4_SUPPORTED_VERSION, &coex_sta->bt_coex_supported_version);
+
+
+	btcoexist->btc_get(btcoexist, BTC_GET_U4_BT_PATCH_VER, &bt_patch_ver);
+	btcoexist->bt_info.bt_get_fw_ver = bt_patch_ver;
+
+#if (BT_AUTO_REPORT_ONLY_8723B_2ANT == 0)
+	halbtc8723b2ant_query_bt_info(btcoexist);
+	halbtc8723b2ant_monitor_bt_enable_disable(btcoexist);
+#else
+	halbtc8723b2ant_monitor_bt_ctr(btcoexist);
+	halbtc8723b2ant_monitor_wifi_ctr(btcoexist);
+
+	/* for some BT speaker that Hi-Pri pkt appear begore start play, this will cause HID exist */
+	if ((coex_sta->high_priority_tx  + coex_sta->high_priority_rx < 50) &&
+	    (bt_link_info->hid_exist == true))
+		bt_link_info->hid_exist  = false;
+
+	if (halbtc8723b2ant_is_wifi_status_changed(btcoexist) ||
+	    coex_dm->auto_tdma_adjust)
+		halbtc8723b2ant_run_coexist_mechanism(btcoexist);
+#endif
+}
+
+#endif
+
+#endif	/* #if (BT_SUPPORT == 1 && COEX_SUPPORT == 1) */
+
+
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/btc/halbtc8723b2ant.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/btc/halbtc8723b2ant.h
--- linux-5.6.3/3rdparty/rtl8821ce/hal/btc/halbtc8723b2ant.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/btc/halbtc8723b2ant.h	2020-04-10 16:35:06.782658480 +0300
@@ -0,0 +1,217 @@
+
+#if (BT_SUPPORT == 1 && COEX_SUPPORT == 1)
+
+#if (RTL8723B_SUPPORT == 1)
+/* *******************************************
+ * The following is for 8723B 2Ant BT Co-exist definition
+ * ******************************************* */
+#define	BT_AUTO_REPORT_ONLY_8723B_2ANT				1
+
+
+#define	BT_INFO_8723B_2ANT_B_FTP						BIT(7)
+#define	BT_INFO_8723B_2ANT_B_A2DP					BIT(6)
+#define	BT_INFO_8723B_2ANT_B_HID						BIT(5)
+#define	BT_INFO_8723B_2ANT_B_SCO_BUSY				BIT(4)
+#define	BT_INFO_8723B_2ANT_B_ACL_BUSY				BIT(3)
+#define	BT_INFO_8723B_2ANT_B_INQ_PAGE				BIT(2)
+#define	BT_INFO_8723B_2ANT_B_SCO_ESCO				BIT(1)
+#define	BT_INFO_8723B_2ANT_B_CONNECTION				BIT(0)
+
+#define		BTC_RSSI_COEX_THRESH_TOL_8723B_2ANT		2
+
+
+#define	BT_8723B_2ANT_WIFI_RSSI_COEXSWITCH_THRES				42  /* WiFi RSSI Threshold for 2-Ant TDMA/1-Ant PS-TDMA translation */
+#define	BT_8723B_2ANT_BT_RSSI_COEXSWITCH_THRES				46 /* BT RSSI Threshold for 2-Ant TDMA/1-Ant PS-TDMA translation */
+
+enum bt_info_src_8723b_2ant {
+	BT_INFO_SRC_8723B_2ANT_WIFI_FW			= 0x0,
+	BT_INFO_SRC_8723B_2ANT_BT_RSP				= 0x1,
+	BT_INFO_SRC_8723B_2ANT_BT_ACTIVE_SEND		= 0x2,
+	BT_INFO_SRC_8723B_2ANT_MAX
+};
+
+enum bt_8723b_2ant_bt_status {
+	BT_8723B_2ANT_BT_STATUS_NON_CONNECTED_IDLE	= 0x0,
+	BT_8723B_2ANT_BT_STATUS_CONNECTED_IDLE		= 0x1,
+	BT_8723B_2ANT_BT_STATUS_INQ_PAGE				= 0x2,
+	BT_8723B_2ANT_BT_STATUS_ACL_BUSY				= 0x3,
+	BT_8723B_2ANT_BT_STATUS_SCO_BUSY				= 0x4,
+	BT_8723B_2ANT_BT_STATUS_ACL_SCO_BUSY			= 0x5,
+	BT_8723B_2ANT_BT_STATUS_MAX
+};
+
+enum bt_8723b_2ant_coex_algo {
+	BT_8723B_2ANT_COEX_ALGO_UNDEFINED			= 0x0,
+	BT_8723B_2ANT_COEX_ALGO_SCO				= 0x1,
+	BT_8723B_2ANT_COEX_ALGO_HID				= 0x2,
+	BT_8723B_2ANT_COEX_ALGO_A2DP				= 0x3,
+	BT_8723B_2ANT_COEX_ALGO_A2DP_PANHS		= 0x4,
+	BT_8723B_2ANT_COEX_ALGO_PANEDR			= 0x5,
+	BT_8723B_2ANT_COEX_ALGO_PANHS			= 0x6,
+	BT_8723B_2ANT_COEX_ALGO_PANEDR_A2DP		= 0x7,
+	BT_8723B_2ANT_COEX_ALGO_PANEDR_HID		= 0x8,
+	BT_8723B_2ANT_COEX_ALGO_HID_A2DP_PANEDR	= 0x9,
+	BT_8723B_2ANT_COEX_ALGO_HID_A2DP			= 0xa,
+	BT_8723B_2ANT_COEX_ALGO_MAX				= 0xb,
+};
+
+struct coex_dm_8723b_2ant {
+	/* fw mechanism */
+	u8		pre_bt_dec_pwr_lvl;
+	u8		cur_bt_dec_pwr_lvl;
+	u8		pre_fw_dac_swing_lvl;
+	u8		cur_fw_dac_swing_lvl;
+	boolean		cur_ignore_wlan_act;
+	boolean		pre_ignore_wlan_act;
+	u8		pre_ps_tdma;
+	u8		cur_ps_tdma;
+	u8		ps_tdma_para[5];
+	u8		ps_tdma_du_adj_type;
+	boolean		reset_tdma_adjust;
+	boolean		auto_tdma_adjust;
+	boolean		pre_ps_tdma_on;
+	boolean		cur_ps_tdma_on;
+	boolean		pre_bt_auto_report;
+	boolean		cur_bt_auto_report;
+
+	/* sw mechanism */
+	boolean		pre_rf_rx_lpf_shrink;
+	boolean		cur_rf_rx_lpf_shrink;
+	u32		bt_rf_0x1e_backup;
+	boolean	pre_low_penalty_ra;
+	boolean		cur_low_penalty_ra;
+	boolean		pre_dac_swing_on;
+	u32		pre_dac_swing_lvl;
+	boolean		cur_dac_swing_on;
+	u32		cur_dac_swing_lvl;
+	boolean		pre_adc_back_off;
+	boolean		cur_adc_back_off;
+	boolean	pre_agc_table_en;
+	boolean		cur_agc_table_en;
+	u32		pre_val0x6c0;
+	u32		cur_val0x6c0;
+	u32		pre_val0x6c4;
+	u32		cur_val0x6c4;
+	u32		pre_val0x6c8;
+	u32		cur_val0x6c8;
+	u8		pre_val0x6cc;
+	u8		cur_val0x6cc;
+	boolean		limited_dig;
+
+	/* algorithm related */
+	u8		pre_algorithm;
+	u8		cur_algorithm;
+	u8		bt_status;
+	u8		wifi_chnl_info[3];
+
+	boolean		need_recover0x948;
+	u32		backup0x948;
+
+	u8		pre_lps;
+	u8		cur_lps;
+	u8		pre_rpwm;
+	u8		cur_rpwm;
+
+	boolean		is_switch_to_1dot5_ant;
+	u8		switch_thres_offset;
+};
+
+struct coex_sta_8723b_2ant {
+	boolean					bt_disabled;
+	boolean					bt_link_exist;
+	boolean					sco_exist;
+	boolean					a2dp_exist;
+	boolean					hid_exist;
+	boolean					pan_exist;
+	boolean					bt_abnormal_scan;
+	boolean					under_lps;
+	boolean					under_ips;
+	u32					high_priority_tx;
+	u32					high_priority_rx;
+	u32					low_priority_tx;
+	u32					low_priority_rx;
+	u8					bt_rssi;
+	boolean					bt_tx_rx_mask;
+	u8					pre_bt_rssi_state;
+	u8					pre_wifi_rssi_state[4];
+	boolean					c2h_bt_info_req_sent;
+	u8					bt_info_c2h[BT_INFO_SRC_8723B_2ANT_MAX][10];
+	u32					bt_info_c2h_cnt[BT_INFO_SRC_8723B_2ANT_MAX];
+	boolean				bt_whck_test;
+	boolean					c2h_bt_inquiry_page;
+	boolean					c2h_bt_remote_name_req;
+	u8					bt_retry_cnt;
+	u8					bt_info_ext;
+	u32					pop_event_cnt;
+	u8					scan_ap_num;
+
+	u32					crc_ok_cck;
+	u32					crc_ok_11g;
+	u32					crc_ok_11n;
+	u32					crc_ok_11n_vht;
+
+	u32					crc_err_cck;
+	u32					crc_err_11g;
+	u32					crc_err_11n;
+	u32					crc_err_11n_vht;
+
+	u32					bt_coex_supported_version;
+
+	u8					coex_table_type;
+	boolean					force_lps_on;
+
+	u8					dis_ver_info_cnt;
+
+	u8					a2dp_bit_pool;
+	u8					cut_version;
+};
+
+/* *******************************************
+ * The following is interface which will notify coex module.
+ * ******************************************* */
+void ex_halbtc8723b2ant_power_on_setting(IN struct btc_coexist *btcoexist);
+void ex_halbtc8723b2ant_pre_load_firmware(IN struct btc_coexist *btcoexist);
+void ex_halbtc8723b2ant_init_hw_config(IN struct btc_coexist *btcoexist,
+				       IN boolean wifi_only);
+void ex_halbtc8723b2ant_init_coex_dm(IN struct btc_coexist *btcoexist);
+void ex_halbtc8723b2ant_ips_notify(IN struct btc_coexist *btcoexist,
+				   IN u8 type);
+void ex_halbtc8723b2ant_lps_notify(IN struct btc_coexist *btcoexist,
+				   IN u8 type);
+void ex_halbtc8723b2ant_scan_notify(IN struct btc_coexist *btcoexist,
+				    IN u8 type);
+void ex_halbtc8723b2ant_connect_notify(IN struct btc_coexist *btcoexist,
+				       IN u8 type);
+void ex_halbtc8723b2ant_media_status_notify(IN struct btc_coexist *btcoexist,
+		IN u8 type);
+void ex_halbtc8723b2ant_specific_packet_notify(IN struct btc_coexist *btcoexist,
+		IN u8 type);
+void ex_halbtc8723b2ant_bt_info_notify(IN struct btc_coexist *btcoexist,
+				       IN u8 *tmp_buf, IN u8 length);
+void ex_halbtc8723b2ant_halt_notify(IN struct btc_coexist *btcoexist);
+void ex_halbtc8723b2ant_pnp_notify(IN struct btc_coexist *btcoexist,
+				   IN u8 pnp_state);
+void ex_halbtc8723b2ant_periodical(IN struct btc_coexist *btcoexist);
+void ex_halbtc8723b2ant_display_coex_info(IN struct btc_coexist *btcoexist);
+
+#else
+#define	ex_halbtc8723b2ant_power_on_setting(btcoexist)
+#define	ex_halbtc8723b2ant_pre_load_firmware(btcoexist)
+#define	ex_halbtc8723b2ant_init_hw_config(btcoexist, wifi_only)
+#define	ex_halbtc8723b2ant_init_coex_dm(btcoexist)
+#define	ex_halbtc8723b2ant_ips_notify(btcoexist, type)
+#define	ex_halbtc8723b2ant_lps_notify(btcoexist, type)
+#define	ex_halbtc8723b2ant_scan_notify(btcoexist, type)
+#define	ex_halbtc8723b2ant_connect_notify(btcoexist, type)
+#define	ex_halbtc8723b2ant_media_status_notify(btcoexist, type)
+#define	ex_halbtc8723b2ant_specific_packet_notify(btcoexist, type)
+#define	ex_halbtc8723b2ant_bt_info_notify(btcoexist, tmp_buf, length)
+#define	ex_halbtc8723b2ant_halt_notify(btcoexist)
+#define	ex_halbtc8723b2ant_pnp_notify(btcoexist, pnp_state)
+#define	ex_halbtc8723b2ant_periodical(btcoexist)
+#define	ex_halbtc8723b2ant_display_coex_info(btcoexist)
+
+#endif
+
+#endif
+
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/btc/halbtc8723bwifionly.c linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/btc/halbtc8723bwifionly.c
--- linux-5.6.3/3rdparty/rtl8821ce/hal/btc/halbtc8723bwifionly.c	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/btc/halbtc8723bwifionly.c	2020-04-10 16:35:06.782658480 +0300
@@ -0,0 +1,68 @@
+#include "mp_precomp.h"
+
+
+VOID
+ex_hal8723b_wifi_only_hw_config(
+	IN struct wifi_only_cfg *pwifionlycfg
+	)
+{
+	struct wifi_only_haldata *pwifionly_haldata = &pwifionlycfg->haldata_info;
+
+
+	halwifionly_write1byte(pwifionlycfg, 0x778, 0x3); /* Set pta for wifi first priority, 0x1 need to reference pta table to determine wifi and bt priority */
+	halwifionly_bitmaskwrite1byte(pwifionlycfg, 0x40, 0x20, 0x1);
+
+	/* Set Antenna path to Wifi */
+	halwifionly_write2byte(pwifionlycfg, 0x0765, 0x8); /* Set pta for wifi first priority, 0x0 need to reference pta table to determine wifi and bt priority */
+	halwifionly_write2byte(pwifionlycfg, 0x076e, 0xc);
+
+	halwifionly_write4byte(pwifionlycfg, 0x000006c0, 0xaaaaaaaa); /* pta table, 0xaaaaaaaa means wifi is higher priority than bt */
+	halwifionly_write4byte(pwifionlycfg, 0x000006c4, 0xaaaaaaaa);
+
+	halwifionly_bitmaskwrite1byte(pwifionlycfg, 0x67, 0x20, 0x1); /* BT select s0/s1 is controlled by WiFi */
+
+	/* 0x948 setting */
+	if (pwifionlycfg->chip_interface == WIFIONLY_INTF_PCI) {
+		/* HP Foxconn NGFF at S0
+		 not sure HP pg correct or not(EEPROMBluetoothSingleAntPath), so here we just write
+		 0x948=0x280 for HP HW id NIC. */
+		if (pwifionly_haldata->customer_id == CUSTOMER_HP_1) {
+			halwifionly_write4byte(pwifionlycfg, 0x948, 0x280);
+			halwifionly_phy_set_rf_reg(pwifionlycfg, 0, 0x1, 0xfffff, 0x0); /* WiFi TRx Mask off */
+			return;
+		}
+	}
+
+	if (pwifionly_haldata->efuse_pg_antnum == 2) {
+		halwifionly_write4byte(pwifionlycfg, 0x948, 0x0);
+	} else {
+	/* 3Attention !!! For 8723BU  !!!!
+	 For 8723BU single ant case: jira [USB-1237]
+		   Because of 8723BU S1 has HW problem, we only can use S0 instead.
+		   Whether Efuse 0xc3 [6] is 0 or 1, we should always use S0 and write 0x948 to 80/280
+
+	 --------------------------------------------------
+	 BT Team :
+		  When in Single Ant case, Reg[0x948] has two case : 0x80 or 0x200
+		 When in Two Ant case, Reg[0x948] has two case : 0x280 or 0x0
+		  Efuse 0xc3 [6] Antenna Path
+		  0xc3 [6] = 0	 ==>  S1	 ==>   0x948 = 0/40/200
+		  0xc3 [6] = 1	 ==>  S0	 ==>   0x948 = 80/240/280 */
+
+		if (pwifionlycfg->chip_interface == WIFIONLY_INTF_USB)
+			halwifionly_write4byte(pwifionlycfg, 0x948, 0x80);
+		else {
+			if (pwifionly_haldata->efuse_pg_antpath == 0)
+				halwifionly_write4byte(pwifionlycfg, 0x948, 0x0);
+			else
+				halwifionly_write4byte(pwifionlycfg, 0x948, 0x280);
+		}
+
+	}
+
+
+	/* after 8723B F-cut, TRx Mask should be set when 0x948=0x0 or 0x280
+	PHY_SetRFReg(Adapter, 0, 0x1, 0xfffff, 0x780); WiFi TRx Mask on */
+	halwifionly_phy_set_rf_reg(pwifionlycfg, 0, 0x1, 0xfffff, 0x0); /*WiFi TRx Mask off */
+
+}
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/btc/halbtc8723bwifionly.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/btc/halbtc8723bwifionly.h
--- linux-5.6.3/3rdparty/rtl8821ce/hal/btc/halbtc8723bwifionly.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/btc/halbtc8723bwifionly.h	2020-04-10 16:35:06.782658480 +0300
@@ -0,0 +1,8 @@
+#ifndef __INC_HAL8723BWIFIONLYHWCFG_H
+#define __INC_HAL8723BWIFIONLYHWCFG_H
+
+VOID
+ex_hal8723b_wifi_only_hw_config(
+	IN struct wifi_only_cfg *pwifionlycfg
+	);
+#endif
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/btc/halbtc8723d1ant.c linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/btc/halbtc8723d1ant.c
--- linux-5.6.3/3rdparty/rtl8821ce/hal/btc/halbtc8723d1ant.c	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/btc/halbtc8723d1ant.c	2020-04-10 16:35:06.782658480 +0300
@@ -0,0 +1,6293 @@
+/* ************************************************************
+ * Description:
+ *
+ * This file is for RTL8723D Co-exist mechanism
+ *
+ * History
+ * 2012/11/15 Cosa first check in.
+ *
+ * ************************************************************ */
+
+/* ************************************************************
+ * include files
+ * ************************************************************ */
+#include "mp_precomp.h"
+
+#if (BT_SUPPORT == 1 && COEX_SUPPORT == 1)
+
+#if (RTL8723D_SUPPORT == 1)
+/* ************************************************************
+ * Global variables, these are static variables
+ * ************************************************************ */
+static u8	*trace_buf = &gl_btc_trace_buf[0];
+static struct  coex_dm_8723d_1ant		glcoex_dm_8723d_1ant;
+static struct  coex_dm_8723d_1ant	*coex_dm = &glcoex_dm_8723d_1ant;
+static struct  coex_sta_8723d_1ant		glcoex_sta_8723d_1ant;
+static struct  coex_sta_8723d_1ant	*coex_sta = &glcoex_sta_8723d_1ant;
+static struct  psdscan_sta_8723d_1ant	gl_psd_scan_8723d_1ant;
+static struct  psdscan_sta_8723d_1ant *psd_scan = &gl_psd_scan_8723d_1ant;
+
+
+const char *const glbt_info_src_8723d_1ant[] = {
+	"BT Info[wifi fw]",
+	"BT Info[bt rsp]",
+	"BT Info[bt auto report]",
+};
+/* ************************************************************
+ * BtCoex Version Format:
+ * 1. date :			glcoex_ver_date_XXXXX_1ant
+ * 2. WifiCoexVersion : glcoex_ver_XXXX_1ant
+ * 3. BtCoexVersion :	glcoex_ver_btdesired_XXXXX_1ant
+ * 4. others :			glcoex_ver_XXXXXX_XXXXX_1ant
+ *
+ * Variable should be indicated IC and Antenna numbers !!!
+ * Please strictly follow this order and naming style !!!
+ *
+ * ************************************************************ */
+u32	glcoex_ver_date_8723d_1ant = 20161220;
+u32	glcoex_ver_8723d_1ant = 0x13;
+u32 glcoex_ver_btdesired_8723d_1ant = 0x10;
+
+
+/* ************************************************************
+ * local function proto type if needed
+ * ************************************************************
+ * ************************************************************
+ * local function start with halbtc8723d1ant_
+ * ************************************************************ */
+u8 halbtc8723d1ant_bt_rssi_state(u8 level_num, u8 rssi_thresh, u8 rssi_thresh1)
+{
+	s32			bt_rssi = 0;
+	u8			bt_rssi_state = coex_sta->pre_bt_rssi_state;
+
+	bt_rssi = coex_sta->bt_rssi;
+
+	if (level_num == 2) {
+		if ((coex_sta->pre_bt_rssi_state == BTC_RSSI_STATE_LOW) ||
+		    (coex_sta->pre_bt_rssi_state ==
+		     BTC_RSSI_STATE_STAY_LOW)) {
+			if (bt_rssi >= (rssi_thresh +
+					BTC_RSSI_COEX_THRESH_TOL_8723D_1ANT))
+				bt_rssi_state = BTC_RSSI_STATE_HIGH;
+			else
+				bt_rssi_state = BTC_RSSI_STATE_STAY_LOW;
+		} else {
+			if (bt_rssi < rssi_thresh)
+				bt_rssi_state = BTC_RSSI_STATE_LOW;
+			else
+				bt_rssi_state = BTC_RSSI_STATE_STAY_HIGH;
+		}
+	} else if (level_num == 3) {
+		if (rssi_thresh > rssi_thresh1) {
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				    "[BTCoex], BT Rssi thresh error!!\n");
+			BTC_TRACE(trace_buf);
+			return coex_sta->pre_bt_rssi_state;
+		}
+
+		if ((coex_sta->pre_bt_rssi_state == BTC_RSSI_STATE_LOW) ||
+		    (coex_sta->pre_bt_rssi_state ==
+		     BTC_RSSI_STATE_STAY_LOW)) {
+			if (bt_rssi >= (rssi_thresh +
+					BTC_RSSI_COEX_THRESH_TOL_8723D_1ANT))
+				bt_rssi_state = BTC_RSSI_STATE_MEDIUM;
+			else
+				bt_rssi_state = BTC_RSSI_STATE_STAY_LOW;
+		} else if ((coex_sta->pre_bt_rssi_state ==
+			    BTC_RSSI_STATE_MEDIUM) ||
+			   (coex_sta->pre_bt_rssi_state ==
+			    BTC_RSSI_STATE_STAY_MEDIUM)) {
+			if (bt_rssi >= (rssi_thresh1 +
+					BTC_RSSI_COEX_THRESH_TOL_8723D_1ANT))
+				bt_rssi_state = BTC_RSSI_STATE_HIGH;
+			else if (bt_rssi < rssi_thresh)
+				bt_rssi_state = BTC_RSSI_STATE_LOW;
+			else
+				bt_rssi_state = BTC_RSSI_STATE_STAY_MEDIUM;
+		} else {
+			if (bt_rssi < rssi_thresh1)
+				bt_rssi_state = BTC_RSSI_STATE_MEDIUM;
+			else
+				bt_rssi_state = BTC_RSSI_STATE_STAY_HIGH;
+		}
+	}
+
+	coex_sta->pre_bt_rssi_state = bt_rssi_state;
+
+	return bt_rssi_state;
+}
+
+u8 halbtc8723d1ant_wifi_rssi_state(IN struct btc_coexist *btcoexist,
+	   IN u8 index, IN u8 level_num, IN u8 rssi_thresh, IN u8 rssi_thresh1)
+{
+	s32			wifi_rssi = 0;
+	u8			wifi_rssi_state = coex_sta->pre_wifi_rssi_state[index];
+
+	btcoexist->btc_get(btcoexist, BTC_GET_S4_WIFI_RSSI, &wifi_rssi);
+
+	if (level_num == 2) {
+		if ((coex_sta->pre_wifi_rssi_state[index] == BTC_RSSI_STATE_LOW)
+		    ||
+		    (coex_sta->pre_wifi_rssi_state[index] ==
+		     BTC_RSSI_STATE_STAY_LOW)) {
+			if (wifi_rssi >= (rssi_thresh +
+					  BTC_RSSI_COEX_THRESH_TOL_8723D_1ANT))
+				wifi_rssi_state = BTC_RSSI_STATE_HIGH;
+			else
+				wifi_rssi_state = BTC_RSSI_STATE_STAY_LOW;
+		} else {
+			if (wifi_rssi < rssi_thresh)
+				wifi_rssi_state = BTC_RSSI_STATE_LOW;
+			else
+				wifi_rssi_state = BTC_RSSI_STATE_STAY_HIGH;
+		}
+	} else if (level_num == 3) {
+		if (rssi_thresh > rssi_thresh1) {
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				    "[BTCoex], wifi RSSI thresh error!!\n");
+			BTC_TRACE(trace_buf);
+			return coex_sta->pre_wifi_rssi_state[index];
+		}
+
+		if ((coex_sta->pre_wifi_rssi_state[index] == BTC_RSSI_STATE_LOW)
+		    ||
+		    (coex_sta->pre_wifi_rssi_state[index] ==
+		     BTC_RSSI_STATE_STAY_LOW)) {
+			if (wifi_rssi >= (rssi_thresh +
+					  BTC_RSSI_COEX_THRESH_TOL_8723D_1ANT))
+				wifi_rssi_state = BTC_RSSI_STATE_MEDIUM;
+			else
+				wifi_rssi_state = BTC_RSSI_STATE_STAY_LOW;
+		} else if ((coex_sta->pre_wifi_rssi_state[index] ==
+			    BTC_RSSI_STATE_MEDIUM) ||
+			   (coex_sta->pre_wifi_rssi_state[index] ==
+			    BTC_RSSI_STATE_STAY_MEDIUM)) {
+			if (wifi_rssi >= (rssi_thresh1 +
+					  BTC_RSSI_COEX_THRESH_TOL_8723D_1ANT))
+				wifi_rssi_state = BTC_RSSI_STATE_HIGH;
+			else if (wifi_rssi < rssi_thresh)
+				wifi_rssi_state = BTC_RSSI_STATE_LOW;
+			else
+				wifi_rssi_state = BTC_RSSI_STATE_STAY_MEDIUM;
+		} else {
+			if (wifi_rssi < rssi_thresh1)
+				wifi_rssi_state = BTC_RSSI_STATE_MEDIUM;
+			else
+				wifi_rssi_state = BTC_RSSI_STATE_STAY_HIGH;
+		}
+	}
+
+	coex_sta->pre_wifi_rssi_state[index] = wifi_rssi_state;
+
+	return wifi_rssi_state;
+}
+
+void halbtc8723d1ant_update_ra_mask(IN struct btc_coexist *btcoexist,
+				    IN boolean force_exec, IN u32 dis_rate_mask)
+{
+	coex_dm->cur_ra_mask = dis_rate_mask;
+
+	if (force_exec || (coex_dm->pre_ra_mask != coex_dm->cur_ra_mask))
+		btcoexist->btc_set(btcoexist, BTC_SET_ACT_UPDATE_RAMASK,
+				   &coex_dm->cur_ra_mask);
+	coex_dm->pre_ra_mask = coex_dm->cur_ra_mask;
+}
+
+void halbtc8723d1ant_auto_rate_fallback_retry(IN struct btc_coexist *btcoexist,
+		IN boolean force_exec, IN u8 type)
+{
+	boolean	wifi_under_b_mode = false;
+
+	coex_dm->cur_arfr_type = type;
+
+	if (force_exec || (coex_dm->pre_arfr_type != coex_dm->cur_arfr_type)) {
+		switch (coex_dm->cur_arfr_type) {
+		case 0:	/* normal mode */
+			btcoexist->btc_write_4byte(btcoexist, 0x430,
+						   coex_dm->backup_arfr_cnt1);
+			btcoexist->btc_write_4byte(btcoexist, 0x434,
+						   coex_dm->backup_arfr_cnt2);
+			break;
+		case 1:
+			btcoexist->btc_get(btcoexist,
+					   BTC_GET_BL_WIFI_UNDER_B_MODE,
+					   &wifi_under_b_mode);
+			if (wifi_under_b_mode) {
+				btcoexist->btc_write_4byte(btcoexist,
+							   0x430, 0x0);
+				btcoexist->btc_write_4byte(btcoexist,
+							   0x434, 0x01010101);
+			} else {
+				btcoexist->btc_write_4byte(btcoexist,
+							   0x430, 0x0);
+				btcoexist->btc_write_4byte(btcoexist,
+							   0x434, 0x04030201);
+			}
+			break;
+		default:
+			break;
+		}
+	}
+
+	coex_dm->pre_arfr_type = coex_dm->cur_arfr_type;
+}
+
+void halbtc8723d1ant_retry_limit(IN struct btc_coexist *btcoexist,
+				 IN boolean force_exec, IN u8 type)
+{
+	coex_dm->cur_retry_limit_type = type;
+
+	if (force_exec ||
+	    (coex_dm->pre_retry_limit_type !=
+	     coex_dm->cur_retry_limit_type)) {
+		switch (coex_dm->cur_retry_limit_type) {
+		case 0:	/* normal mode */
+			btcoexist->btc_write_2byte(btcoexist, 0x42a,
+						   coex_dm->backup_retry_limit);
+			break;
+		case 1:	/* retry limit=8 */
+			btcoexist->btc_write_2byte(btcoexist, 0x42a,
+						   0x0808);
+			break;
+		default:
+			break;
+		}
+	}
+
+	coex_dm->pre_retry_limit_type = coex_dm->cur_retry_limit_type;
+}
+
+void halbtc8723d1ant_ampdu_max_time(IN struct btc_coexist *btcoexist,
+				    IN boolean force_exec, IN u8 type)
+{
+	coex_dm->cur_ampdu_time_type = type;
+
+	if (force_exec ||
+	    (coex_dm->pre_ampdu_time_type != coex_dm->cur_ampdu_time_type)) {
+		switch (coex_dm->cur_ampdu_time_type) {
+		case 0:	/* normal mode */
+			btcoexist->btc_write_1byte(btcoexist, 0x456,
+					   coex_dm->backup_ampdu_max_time);
+			break;
+		case 1:	/* AMPDU timw = 0x38 * 32us */
+			btcoexist->btc_write_1byte(btcoexist, 0x456,
+						   0x38);
+			break;
+		default:
+			break;
+		}
+	}
+
+	coex_dm->pre_ampdu_time_type = coex_dm->cur_ampdu_time_type;
+}
+
+void halbtc8723d1ant_limited_tx(IN struct btc_coexist *btcoexist,
+		IN boolean force_exec, IN u8 ra_mask_type, IN u8 arfr_type,
+				IN u8 retry_limit_type, IN u8 ampdu_time_type)
+{
+	switch (ra_mask_type) {
+	case 0:	/* normal mode */
+		halbtc8723d1ant_update_ra_mask(btcoexist, force_exec,
+					       0x0);
+		break;
+	case 1:	/* disable cck 1/2 */
+		halbtc8723d1ant_update_ra_mask(btcoexist, force_exec,
+					       0x00000003);
+		break;
+	case 2:	/* disable cck 1/2/5.5, ofdm 6/9/12/18/24, mcs 0/1/2/3/4 */
+		halbtc8723d1ant_update_ra_mask(btcoexist, force_exec,
+					       0x0001f1f7);
+		break;
+	default:
+		break;
+	}
+
+	halbtc8723d1ant_auto_rate_fallback_retry(btcoexist, force_exec,
+			arfr_type);
+	halbtc8723d1ant_retry_limit(btcoexist, force_exec, retry_limit_type);
+	halbtc8723d1ant_ampdu_max_time(btcoexist, force_exec, ampdu_time_type);
+}
+
+void halbtc8723d1ant_limited_rx(IN struct btc_coexist *btcoexist,
+			IN boolean force_exec, IN boolean rej_ap_agg_pkt,
+			IN boolean bt_ctrl_agg_buf_size, IN u8 agg_buf_size)
+{
+	boolean	reject_rx_agg = rej_ap_agg_pkt;
+	boolean	bt_ctrl_rx_agg_size = bt_ctrl_agg_buf_size;
+	u8	rx_agg_size = agg_buf_size;
+
+	/* ============================================ */
+	/*	Rx Aggregation related setting */
+	/* ============================================ */
+	btcoexist->btc_set(btcoexist, BTC_SET_BL_TO_REJ_AP_AGG_PKT,
+			   &reject_rx_agg);
+	/* decide BT control aggregation buf size or not */
+	btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_CTRL_AGG_SIZE,
+			   &bt_ctrl_rx_agg_size);
+	/* aggregation buf size, only work when BT control Rx aggregation size. */
+	btcoexist->btc_set(btcoexist, BTC_SET_U1_AGG_BUF_SIZE, &rx_agg_size);
+	/* real update aggregation setting */
+	btcoexist->btc_set(btcoexist, BTC_SET_ACT_AGGREGATE_CTRL, NULL);
+
+
+}
+
+void halbtc8723d1ant_query_bt_info(IN struct btc_coexist *btcoexist)
+{
+	u8			h2c_parameter[1] = {0};
+
+	h2c_parameter[0] |= BIT(0);	/* trigger */
+
+	btcoexist->btc_fill_h2c(btcoexist, 0x61, 1, h2c_parameter);
+
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+		    "[BTCoex], WL query BT info!!\n");
+	BTC_TRACE(trace_buf);
+}
+
+void halbtc8723d1ant_monitor_bt_ctr(IN struct btc_coexist *btcoexist)
+{
+	u32 reg_hp_txrx, reg_lp_txrx, u32tmp;
+	u32 reg_hp_tx = 0, reg_hp_rx = 0, reg_lp_tx = 0, reg_lp_rx = 0;
+	static u8		num_of_bt_counter_chk = 0, cnt_slave = 0, cnt_overhead = 0,
+				cnt_autoslot_hang = 0;
+	struct	btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
+
+	/* to avoid 0x76e[3] = 1 (WLAN_Act control by PTA) during IPS */
+	/* if (! (btcoexist->btc_read_1byte(btcoexist, 0x76e) & 0x8) ) */
+
+	reg_hp_txrx = 0x770;
+	reg_lp_txrx = 0x774;
+
+	u32tmp = btcoexist->btc_read_4byte(btcoexist, reg_hp_txrx);
+	reg_hp_tx = u32tmp & MASKLWORD;
+	reg_hp_rx = (u32tmp & MASKHWORD) >> 16;
+
+	u32tmp = btcoexist->btc_read_4byte(btcoexist, reg_lp_txrx);
+	reg_lp_tx = u32tmp & MASKLWORD;
+	reg_lp_rx = (u32tmp & MASKHWORD) >> 16;
+
+	coex_sta->high_priority_tx = reg_hp_tx;
+	coex_sta->high_priority_rx = reg_hp_rx;
+	coex_sta->low_priority_tx = reg_lp_tx;
+	coex_sta->low_priority_rx = reg_lp_rx;
+
+	if (BT_8723D_1ANT_BT_STATUS_NON_CONNECTED_IDLE ==
+		coex_dm->bt_status) {
+
+			if (coex_sta->high_priority_rx >= 15) {
+					if (cnt_overhead < 3)
+						cnt_overhead++;
+
+					if (cnt_overhead == 3)
+						coex_sta->is_hiPri_rx_overhead = true;
+			} else {
+					if (cnt_overhead > 0)
+						cnt_overhead--;
+
+					if (cnt_overhead == 0)
+						coex_sta->is_hiPri_rx_overhead = false;
+			}
+	} else
+		coex_sta->is_hiPri_rx_overhead = false;
+
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			"[BTCoex], Hi-Pri Rx/Tx: %d/%d, Lo-Pri Rx/Tx: %d/%d\n",
+			reg_hp_rx, reg_hp_tx, reg_lp_rx, reg_lp_tx);
+
+	BTC_TRACE(trace_buf);
+
+	/* reset counter */
+	btcoexist->btc_write_1byte(btcoexist, 0x76e, 0xc);
+
+	if ((coex_sta->low_priority_tx > 1150)	&&
+		(!coex_sta->c2h_bt_inquiry_page))
+		coex_sta->pop_event_cnt++;
+
+	if ((coex_sta->low_priority_rx >= 1150) &&
+		(coex_sta->low_priority_rx >= coex_sta->low_priority_tx)
+		&& (!coex_sta->under_ips)  && (!coex_sta->c2h_bt_inquiry_page) &&
+		(coex_sta->bt_link_exist))	{
+		if (cnt_slave >= 2) {
+			bt_link_info->slave_role = true;
+			cnt_slave = 2;
+		} else
+			cnt_slave++;
+	} else {
+		if (cnt_slave == 0) {
+			bt_link_info->slave_role = false;
+			cnt_slave = 0;
+		} else
+			cnt_slave--;
+
+	}
+
+	if (coex_sta->is_tdma_btautoslot) {
+		if ((coex_sta->low_priority_tx >= 1300) &&
+			(coex_sta->low_priority_rx <= 150)) {
+			if (cnt_autoslot_hang >= 2) {
+				coex_sta->is_tdma_btautoslot_hang = true;
+				cnt_autoslot_hang = 2;
+			} else
+				cnt_autoslot_hang++;
+		} else {
+			if (cnt_autoslot_hang == 0)	{
+				coex_sta->is_tdma_btautoslot_hang = false;
+				cnt_autoslot_hang = 0;
+			} else
+				cnt_autoslot_hang--;
+		}
+	}
+
+	if (!coex_sta->bt_disabled) {
+
+		if ((coex_sta->high_priority_tx == 0) &&
+			(coex_sta->high_priority_rx == 0) &&
+			(coex_sta->low_priority_tx == 0) &&
+			(coex_sta->low_priority_rx == 0)) {
+			num_of_bt_counter_chk++;
+			if (num_of_bt_counter_chk >= 3) {
+				halbtc8723d1ant_query_bt_info(btcoexist);
+				num_of_bt_counter_chk = 0;
+			}
+		}
+	}
+
+}
+
+void halbtc8723d1ant_monitor_wifi_ctr(IN struct btc_coexist *btcoexist)
+{
+#if 1
+		s32 wifi_rssi = 0;
+		boolean wifi_busy = false, wifi_under_b_mode = false,
+			    wifi_scan = false;
+		boolean	bt_idle = false, wl_idle = false;
+	    static u8 cck_lock_counter = 0, wl_noisy_count0 = 0,
+		       wl_noisy_count1 = 3, wl_noisy_count2 = 0;
+		u32 total_cnt, reg_val1, reg_val2, cck_cnt;
+
+		btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy);
+		btcoexist->btc_get(btcoexist, BTC_GET_S4_WIFI_RSSI, &wifi_rssi);
+		btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_B_MODE,
+				   &wifi_under_b_mode);
+
+		btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_SCAN, &wifi_scan);
+
+		coex_sta->crc_ok_cck = btcoexist->btc_phydm_query_PHY_counter(
+									btcoexist, PHYDM_INFO_CRC32_OK_CCK);
+		coex_sta->crc_ok_11g = btcoexist->btc_phydm_query_PHY_counter(
+									btcoexist, PHYDM_INFO_CRC32_OK_LEGACY);
+		coex_sta->crc_ok_11n = btcoexist->btc_phydm_query_PHY_counter(
+									btcoexist, PHYDM_INFO_CRC32_OK_HT);
+		coex_sta->crc_ok_11n_vht = btcoexist->btc_phydm_query_PHY_counter(
+									btcoexist, PHYDM_INFO_CRC32_OK_VHT);
+
+		coex_sta->crc_err_cck = btcoexist->btc_phydm_query_PHY_counter(
+									btcoexist, PHYDM_INFO_CRC32_ERROR_CCK);
+		coex_sta->crc_err_11g =  btcoexist->btc_phydm_query_PHY_counter(
+									btcoexist, PHYDM_INFO_CRC32_ERROR_LEGACY);
+		coex_sta->crc_err_11n = btcoexist->btc_phydm_query_PHY_counter(
+									btcoexist, PHYDM_INFO_CRC32_ERROR_HT);
+		coex_sta->crc_err_11n_vht = btcoexist->btc_phydm_query_PHY_counter(
+									btcoexist, PHYDM_INFO_CRC32_ERROR_VHT);
+
+		cck_cnt = coex_sta->crc_ok_cck + coex_sta->crc_err_cck;
+
+		if (cck_cnt > 250) {
+			if (wl_noisy_count2 < 3)
+				wl_noisy_count2++;
+
+			if (wl_noisy_count2 == 3) {
+				wl_noisy_count0 = 0;
+				wl_noisy_count1 = 0;
+			}
+		} else if (cck_cnt < 50) {
+			if (wl_noisy_count0 < 3)
+				wl_noisy_count0++;
+
+			if (wl_noisy_count0 == 3) {
+				wl_noisy_count1 = 0;
+				wl_noisy_count2 = 0;
+			}
+		} else {
+			if (wl_noisy_count1 < 3)
+				wl_noisy_count1++;
+
+			if (wl_noisy_count1 == 3) {
+				wl_noisy_count0 = 0;
+				wl_noisy_count2 = 0;
+			}
+		}
+
+		if (wl_noisy_count2 == 3)
+			coex_sta->wl_noisy_level = 2;
+		else if (wl_noisy_count1 == 3)
+			coex_sta->wl_noisy_level = 1;
+		else
+			coex_sta->wl_noisy_level = 0;
+
+		if ((wifi_busy) && (wifi_rssi >= 30) && (!wifi_under_b_mode)) {
+			total_cnt = coex_sta->crc_ok_cck + coex_sta->crc_ok_11g +
+					coex_sta->crc_ok_11n + coex_sta->crc_ok_11n_vht;
+
+			if ((coex_dm->bt_status == BT_8723D_1ANT_BT_STATUS_ACL_BUSY) ||
+				(coex_dm->bt_status == BT_8723D_1ANT_BT_STATUS_ACL_SCO_BUSY) ||
+				(coex_dm->bt_status == BT_8723D_1ANT_BT_STATUS_SCO_BUSY)) {
+				if (coex_sta->crc_ok_cck > (total_cnt -
+								coex_sta->crc_ok_cck)) {
+					if (cck_lock_counter < 3)
+						cck_lock_counter++;
+				} else {
+					if (cck_lock_counter > 0)
+						cck_lock_counter--;
+				}
+
+			} else {
+				if (cck_lock_counter > 0)
+					cck_lock_counter--;
+			}
+		} else {
+			if (cck_lock_counter > 0)
+				cck_lock_counter--;
+		}
+
+		if (!coex_sta->pre_ccklock) {
+
+			if (cck_lock_counter >= 3)
+				coex_sta->cck_lock = true;
+			else
+				coex_sta->cck_lock = false;
+		} else {
+			if (cck_lock_counter == 0)
+				coex_sta->cck_lock = false;
+			else
+				coex_sta->cck_lock = true;
+		}
+
+		if (coex_sta->cck_lock)
+			coex_sta->cck_ever_lock = true;
+
+		coex_sta->pre_ccklock =  coex_sta->cck_lock;
+
+#endif
+}
+
+void halbtc8723d1ant_update_bt_link_info(IN struct btc_coexist *btcoexist)
+{
+	struct	btc_bt_link_info	*bt_link_info = &btcoexist->bt_link_info;
+	boolean		bt_hs_on = false;
+	boolean		bt_busy = false;
+
+
+	coex_sta->num_of_profile = 0;
+
+	/* set link exist status */
+	if (!(coex_sta->bt_info & BT_INFO_8723D_1ANT_B_CONNECTION)) {
+		coex_sta->bt_link_exist = false;
+		coex_sta->pan_exist = false;
+		coex_sta->a2dp_exist = false;
+		coex_sta->hid_exist = false;
+		coex_sta->sco_exist = false;
+	} else {	/* connection exists */
+		coex_sta->bt_link_exist = true;
+		if (coex_sta->bt_info & BT_INFO_8723D_1ANT_B_FTP) {
+			coex_sta->pan_exist = true;
+			coex_sta->num_of_profile++;
+		} else
+			coex_sta->pan_exist = false;
+
+		if (coex_sta->bt_info & BT_INFO_8723D_1ANT_B_A2DP) {
+			coex_sta->a2dp_exist = true;
+			coex_sta->num_of_profile++;
+		} else
+			coex_sta->a2dp_exist = false;
+
+		if (coex_sta->bt_info & BT_INFO_8723D_1ANT_B_HID) {
+			coex_sta->hid_exist = true;
+			coex_sta->num_of_profile++;
+		} else
+			coex_sta->hid_exist = false;
+
+		if (coex_sta->bt_info & BT_INFO_8723D_1ANT_B_SCO_ESCO) {
+			coex_sta->sco_exist = true;
+			coex_sta->num_of_profile++;
+		} else
+			coex_sta->sco_exist = false;
+
+	}
+
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on);
+
+	bt_link_info->bt_link_exist = coex_sta->bt_link_exist;
+	bt_link_info->sco_exist = coex_sta->sco_exist;
+	bt_link_info->a2dp_exist = coex_sta->a2dp_exist;
+	bt_link_info->pan_exist = coex_sta->pan_exist;
+	bt_link_info->hid_exist = coex_sta->hid_exist;
+	bt_link_info->acl_busy = coex_sta->acl_busy;
+
+	/* work around for HS mode. */
+	if (bt_hs_on) {
+		bt_link_info->pan_exist = true;
+		bt_link_info->bt_link_exist = true;
+	}
+
+	/* check if Sco only */
+	if (bt_link_info->sco_exist &&
+	    !bt_link_info->a2dp_exist &&
+	    !bt_link_info->pan_exist &&
+	    !bt_link_info->hid_exist)
+		bt_link_info->sco_only = true;
+	else
+		bt_link_info->sco_only = false;
+
+	/* check if A2dp only */
+	if (!bt_link_info->sco_exist &&
+	    bt_link_info->a2dp_exist &&
+	    !bt_link_info->pan_exist &&
+	    !bt_link_info->hid_exist)
+		bt_link_info->a2dp_only = true;
+	else
+		bt_link_info->a2dp_only = false;
+
+	/* check if Pan only */
+	if (!bt_link_info->sco_exist &&
+	    !bt_link_info->a2dp_exist &&
+	    bt_link_info->pan_exist &&
+	    !bt_link_info->hid_exist)
+		bt_link_info->pan_only = true;
+	else
+		bt_link_info->pan_only = false;
+
+	/* check if Hid only */
+	if (!bt_link_info->sco_exist &&
+	    !bt_link_info->a2dp_exist &&
+	    !bt_link_info->pan_exist &&
+	    bt_link_info->hid_exist)
+		bt_link_info->hid_only = true;
+	else
+		bt_link_info->hid_only = false;
+
+	if (coex_sta->bt_info & BT_INFO_8723D_1ANT_B_INQ_PAGE) {
+		coex_dm->bt_status = BT_8723D_1ANT_BT_STATUS_INQ_PAGE;
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			"[BTCoex], BtInfoNotify(), BT Inq/page!!!\n");
+	} else if (!(coex_sta->bt_info & BT_INFO_8723D_1ANT_B_CONNECTION)) {
+		coex_dm->bt_status = BT_8723D_1ANT_BT_STATUS_NON_CONNECTED_IDLE;
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			"[BTCoex], BtInfoNotify(), BT Non-Connected idle!!!\n");
+	} else if (coex_sta->bt_info == BT_INFO_8723D_1ANT_B_CONNECTION) {
+		/* connection exists but no busy */
+		coex_dm->bt_status = BT_8723D_1ANT_BT_STATUS_CONNECTED_IDLE;
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], BtInfoNotify(), BT Connected-idle!!!\n");
+	} else if (((coex_sta->bt_info & BT_INFO_8723D_1ANT_B_SCO_ESCO) ||
+		    (coex_sta->bt_info & BT_INFO_8723D_1ANT_B_SCO_BUSY)) &&
+		   (coex_sta->bt_info & BT_INFO_8723D_1ANT_B_ACL_BUSY)) {
+		coex_dm->bt_status = BT_8723D_1ANT_BT_STATUS_ACL_SCO_BUSY;
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], BtInfoNotify(), BT ACL SCO busy!!!\n");
+	} else if ((coex_sta->bt_info & BT_INFO_8723D_1ANT_B_SCO_ESCO) ||
+		   (coex_sta->bt_info & BT_INFO_8723D_1ANT_B_SCO_BUSY)) {
+		coex_dm->bt_status = BT_8723D_1ANT_BT_STATUS_SCO_BUSY;
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], BtInfoNotify(), BT SCO busy!!!\n");
+	} else if (coex_sta->bt_info & BT_INFO_8723D_1ANT_B_ACL_BUSY) {
+		coex_dm->bt_status = BT_8723D_1ANT_BT_STATUS_ACL_BUSY;
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], BtInfoNotify(), BT ACL busy!!!\n");
+	} else {
+		coex_dm->bt_status = BT_8723D_1ANT_BT_STATUS_MAX;
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			"[BTCoex], BtInfoNotify(), BT Non-Defined state!!!\n");
+	}
+
+	BTC_TRACE(trace_buf);
+
+	if ((BT_8723D_1ANT_BT_STATUS_ACL_BUSY == coex_dm->bt_status) ||
+	    (BT_8723D_1ANT_BT_STATUS_SCO_BUSY == coex_dm->bt_status) ||
+	    (BT_8723D_1ANT_BT_STATUS_ACL_SCO_BUSY == coex_dm->bt_status))
+		bt_busy = true;
+	else
+		bt_busy = false;
+
+	btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_TRAFFIC_BUSY, &bt_busy);
+}
+
+
+void halbtc8723d1ant_update_wifi_channel_info(IN struct btc_coexist *btcoexist,
+		IN u8 type)
+{
+	u8			h2c_parameter[3] = {0};
+	u32			wifi_bw;
+	u8			wifi_central_chnl;
+
+	/* only 2.4G we need to inform bt the chnl mask */
+	btcoexist->btc_get(btcoexist, BTC_GET_U1_WIFI_CENTRAL_CHNL,
+			   &wifi_central_chnl);
+	if ((BTC_MEDIA_CONNECT == type) &&
+	    (wifi_central_chnl <= 14)) {
+		h2c_parameter[0] =
+			0x1;  /* enable BT AFH skip WL channel for 8723d because BT Rx LO interference */
+		/* h2c_parameter[0] = 0x0; */
+		h2c_parameter[1] = wifi_central_chnl;
+		btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw);
+		if (BTC_WIFI_BW_HT40 == wifi_bw)
+			h2c_parameter[2] = 0x30;
+		else
+			h2c_parameter[2] = 0x20;
+	}
+
+	coex_dm->wifi_chnl_info[0] = h2c_parameter[0];
+	coex_dm->wifi_chnl_info[1] = h2c_parameter[1];
+	coex_dm->wifi_chnl_info[2] = h2c_parameter[2];
+
+	btcoexist->btc_fill_h2c(btcoexist, 0x66, 3, h2c_parameter);
+
+}
+
+u8 halbtc8723d1ant_action_algorithm(IN struct btc_coexist *btcoexist)
+{
+	struct  btc_bt_link_info	*bt_link_info = &btcoexist->bt_link_info;
+	boolean				bt_hs_on = false;
+	u8				algorithm = BT_8723D_1ANT_COEX_ALGO_UNDEFINED;
+	u8				num_of_diff_profile = 0;
+
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on);
+
+	if (!bt_link_info->bt_link_exist) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], No BT link exists!!!\n");
+		BTC_TRACE(trace_buf);
+		return algorithm;
+	}
+
+	if (bt_link_info->sco_exist)
+		num_of_diff_profile++;
+	if (bt_link_info->hid_exist)
+		num_of_diff_profile++;
+	if (bt_link_info->pan_exist)
+		num_of_diff_profile++;
+	if (bt_link_info->a2dp_exist)
+		num_of_diff_profile++;
+
+	if (num_of_diff_profile == 1) {
+		if (bt_link_info->sco_exist) {
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				    "[BTCoex], BT Profile = SCO only\n");
+			BTC_TRACE(trace_buf);
+			algorithm = BT_8723D_1ANT_COEX_ALGO_SCO;
+		} else {
+			if (bt_link_info->hid_exist) {
+				BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+					"[BTCoex], BT Profile = HID only\n");
+				BTC_TRACE(trace_buf);
+				algorithm = BT_8723D_1ANT_COEX_ALGO_HID;
+			} else if (bt_link_info->a2dp_exist) {
+				BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+					"[BTCoex], BT Profile = A2DP only\n");
+				BTC_TRACE(trace_buf);
+				algorithm = BT_8723D_1ANT_COEX_ALGO_A2DP;
+			} else if (bt_link_info->pan_exist) {
+				if (bt_hs_on) {
+					BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+						"[BTCoex], BT Profile = PAN(HS) only\n");
+					BTC_TRACE(trace_buf);
+					algorithm =
+						BT_8723D_1ANT_COEX_ALGO_PANHS;
+				} else {
+					BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+						"[BTCoex], BT Profile = PAN(EDR) only\n");
+					BTC_TRACE(trace_buf);
+					algorithm =
+						BT_8723D_1ANT_COEX_ALGO_PANEDR;
+				}
+			}
+		}
+	} else if (num_of_diff_profile == 2) {
+		if (bt_link_info->sco_exist) {
+			if (bt_link_info->hid_exist) {
+				BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+					"[BTCoex], BT Profile = SCO + HID\n");
+				BTC_TRACE(trace_buf);
+				algorithm = BT_8723D_1ANT_COEX_ALGO_HID;
+			} else if (bt_link_info->a2dp_exist) {
+				BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+					"[BTCoex], BT Profile = SCO + A2DP ==> SCO\n");
+				BTC_TRACE(trace_buf);
+				algorithm = BT_8723D_1ANT_COEX_ALGO_SCO;
+			} else if (bt_link_info->pan_exist) {
+				if (bt_hs_on) {
+					BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+						"[BTCoex], BT Profile = SCO + PAN(HS)\n");
+					BTC_TRACE(trace_buf);
+					algorithm = BT_8723D_1ANT_COEX_ALGO_SCO;
+				} else {
+					BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+						"[BTCoex], BT Profile = SCO + PAN(EDR)\n");
+					BTC_TRACE(trace_buf);
+					algorithm =
+						BT_8723D_1ANT_COEX_ALGO_PANEDR_HID;
+				}
+			}
+		} else {
+			if (bt_link_info->hid_exist &&
+			    bt_link_info->a2dp_exist) {
+				BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+					"[BTCoex], BT Profile = HID + A2DP\n");
+				BTC_TRACE(trace_buf);
+				algorithm = BT_8723D_1ANT_COEX_ALGO_HID_A2DP;
+			} else if (bt_link_info->hid_exist &&
+				   bt_link_info->pan_exist) {
+				if (bt_hs_on) {
+					BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+						"[BTCoex], BT Profile = HID + PAN(HS)\n");
+					BTC_TRACE(trace_buf);
+					algorithm =
+						BT_8723D_1ANT_COEX_ALGO_HID_A2DP;
+				} else {
+					BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+						"[BTCoex], BT Profile = HID + PAN(EDR)\n");
+					BTC_TRACE(trace_buf);
+					algorithm =
+						BT_8723D_1ANT_COEX_ALGO_PANEDR_HID;
+				}
+			} else if (bt_link_info->pan_exist &&
+				   bt_link_info->a2dp_exist) {
+				if (bt_hs_on) {
+					BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+						"[BTCoex], BT Profile = A2DP + PAN(HS)\n");
+					BTC_TRACE(trace_buf);
+					algorithm =
+						BT_8723D_1ANT_COEX_ALGO_A2DP_PANHS;
+				} else {
+					BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+						"[BTCoex], BT Profile = A2DP + PAN(EDR)\n");
+					BTC_TRACE(trace_buf);
+					algorithm =
+						BT_8723D_1ANT_COEX_ALGO_PANEDR_A2DP;
+				}
+			}
+		}
+	} else if (num_of_diff_profile == 3) {
+		if (bt_link_info->sco_exist) {
+			if (bt_link_info->hid_exist &&
+			    bt_link_info->a2dp_exist) {
+				BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+					"[BTCoex], BT Profile = SCO + HID + A2DP ==> HID\n");
+				BTC_TRACE(trace_buf);
+				algorithm = BT_8723D_1ANT_COEX_ALGO_HID;
+			} else if (bt_link_info->hid_exist &&
+				   bt_link_info->pan_exist) {
+				if (bt_hs_on) {
+					BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+						"[BTCoex], BT Profile = SCO + HID + PAN(HS)\n");
+					BTC_TRACE(trace_buf);
+					algorithm =
+						BT_8723D_1ANT_COEX_ALGO_HID_A2DP;
+				} else {
+					BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+						"[BTCoex], BT Profile = SCO + HID + PAN(EDR)\n");
+					BTC_TRACE(trace_buf);
+					algorithm =
+						BT_8723D_1ANT_COEX_ALGO_PANEDR_HID;
+				}
+			} else if (bt_link_info->pan_exist &&
+				   bt_link_info->a2dp_exist) {
+				if (bt_hs_on) {
+					BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+						"[BTCoex], BT Profile = SCO + A2DP + PAN(HS)\n");
+					BTC_TRACE(trace_buf);
+					algorithm = BT_8723D_1ANT_COEX_ALGO_SCO;
+				} else {
+					BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+						"[BTCoex], BT Profile = SCO + A2DP + PAN(EDR) ==> HID\n");
+					BTC_TRACE(trace_buf);
+					algorithm =
+						BT_8723D_1ANT_COEX_ALGO_PANEDR_HID;
+				}
+			}
+		} else {
+			if (bt_link_info->hid_exist &&
+			    bt_link_info->pan_exist &&
+			    bt_link_info->a2dp_exist) {
+				if (bt_hs_on) {
+					BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+						"[BTCoex], BT Profile = HID + A2DP + PAN(HS)\n");
+					BTC_TRACE(trace_buf);
+					algorithm =
+						BT_8723D_1ANT_COEX_ALGO_HID_A2DP;
+				} else {
+					BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+						"[BTCoex], BT Profile = HID + A2DP + PAN(EDR)\n");
+					BTC_TRACE(trace_buf);
+					algorithm =
+						BT_8723D_1ANT_COEX_ALGO_HID_A2DP_PANEDR;
+				}
+			}
+		}
+	} else if (num_of_diff_profile >= 3) {
+		if (bt_link_info->sco_exist) {
+			if (bt_link_info->hid_exist &&
+			    bt_link_info->pan_exist &&
+			    bt_link_info->a2dp_exist) {
+				if (bt_hs_on) {
+					BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+						"[BTCoex], Error!!! BT Profile = SCO + HID + A2DP + PAN(HS)\n");
+					BTC_TRACE(trace_buf);
+
+				} else {
+					BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+						"[BTCoex], BT Profile = SCO + HID + A2DP + PAN(EDR)==>PAN(EDR)+HID\n");
+					BTC_TRACE(trace_buf);
+					algorithm =
+						BT_8723D_1ANT_COEX_ALGO_PANEDR_HID;
+				}
+			}
+		}
+	}
+
+	return algorithm;
+}
+
+void halbtc8723d1ant_set_bt_auto_report(IN struct btc_coexist *btcoexist,
+					IN boolean enable_auto_report)
+{
+	u8			h2c_parameter[1] = {0};
+
+	h2c_parameter[0] = 0;
+
+	if (enable_auto_report)
+		h2c_parameter[0] |= BIT(0);
+
+	btcoexist->btc_fill_h2c(btcoexist, 0x68, 1, h2c_parameter);
+}
+
+void halbtc8723d1ant_bt_auto_report(IN struct btc_coexist *btcoexist,
+		    IN boolean force_exec, IN boolean enable_auto_report)
+{
+	coex_dm->cur_bt_auto_report = enable_auto_report;
+
+	if (!force_exec) {
+		if (coex_dm->pre_bt_auto_report == coex_dm->cur_bt_auto_report)
+			return;
+	}
+	halbtc8723d1ant_set_bt_auto_report(btcoexist,
+					   coex_dm->cur_bt_auto_report);
+
+	coex_dm->pre_bt_auto_report = coex_dm->cur_bt_auto_report;
+}
+
+void halbtc8723d1ant_set_fw_low_penalty_ra(IN struct btc_coexist
+		*btcoexist, IN boolean low_penalty_ra)
+{
+#if 1
+	u8			h2c_parameter[6] = {0};
+
+	h2c_parameter[0] = 0x6;	/* op_code, 0x6= Retry_Penalty */
+
+	if (low_penalty_ra) {
+		h2c_parameter[1] |= BIT(0);
+		h2c_parameter[2] =
+			0x00;  /* normal rate except MCS7/6/5, OFDM54/48/36 */
+		h2c_parameter[3] = 0xf7;  /* MCS7 or OFDM54 */
+		h2c_parameter[4] = 0xf8;  /* MCS6 or OFDM48 */
+		h2c_parameter[5] = 0xf9;	/* MCS5 or OFDM36	 */
+	}
+
+	btcoexist->btc_fill_h2c(btcoexist, 0x69, 6, h2c_parameter);
+#endif
+}
+
+void halbtc8723d1ant_low_penalty_ra(IN struct btc_coexist *btcoexist,
+			    IN boolean force_exec, IN boolean low_penalty_ra)
+{
+#if 1
+	coex_dm->cur_low_penalty_ra = low_penalty_ra;
+
+	if (!force_exec) {
+		if (coex_dm->pre_low_penalty_ra == coex_dm->cur_low_penalty_ra)
+			return;
+	}
+
+	halbtc8723d1ant_set_fw_low_penalty_ra(btcoexist,
+					      coex_dm->cur_low_penalty_ra);
+
+#if 0
+	if (low_penalty_ra)
+		btcoexist->btc_phydm_modify_RA_PCR_threshold(btcoexist, 0, 15);
+	else
+		btcoexist->btc_phydm_modify_RA_PCR_threshold(btcoexist, 0, 0);
+#endif
+	coex_dm->pre_low_penalty_ra = coex_dm->cur_low_penalty_ra;
+
+#endif
+
+}
+
+void halbtc8723d1ant_write_score_board(
+	IN	struct  btc_coexist		*btcoexist,
+	IN	u16				bitpos,
+	IN	boolean		state
+)
+{
+
+	static u16 originalval = 0x8002;
+
+	if (state)
+		originalval = originalval | bitpos;
+	else
+		originalval = originalval & (~bitpos);
+
+
+	btcoexist->btc_write_2byte(btcoexist, 0xaa, originalval);
+
+}
+
+void halbtc8723d1ant_read_score_board(
+	IN	struct  btc_coexist		*btcoexist,
+	IN   u16				*score_board_val
+)
+{
+
+	*score_board_val = (btcoexist->btc_read_2byte(btcoexist,
+			    0xaa)) & 0x7fff;
+}
+
+void halbtc8723d1ant_post_state_to_bt(
+	IN	struct  btc_coexist		*btcoexist,
+	IN	u16						type,
+	IN  boolean                 state
+)
+{
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+		"[BTCoex], halbtc8723d1ant_post_state_to_bt: type = %d, state =%d\n",
+		type, state);
+	BTC_TRACE(trace_buf);
+
+	halbtc8723d1ant_write_score_board(btcoexist, (u16) type, state);
+}
+
+boolean halbtc8723d1ant_is_wifibt_status_changed(IN struct btc_coexist
+		*btcoexist)
+{
+	static boolean	pre_wifi_busy = false, pre_under_4way = false,
+			pre_bt_hs_on = false, pre_bt_off = false, pre_bt_slave = false;
+	static u8 pre_hid_busy_num = 0, pre_wl_noisy_level = 0;
+	boolean wifi_busy = false, under_4way = false, bt_hs_on = false;
+	boolean wifi_connected = false;
+	struct  btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
+
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED,
+			   &wifi_connected);
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy);
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on);
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_4_WAY_PROGRESS,
+			   &under_4way);
+
+	if (coex_sta->bt_disabled != pre_bt_off) {
+		pre_bt_off = coex_sta->bt_disabled;
+
+		if (coex_sta->bt_disabled)
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				    "[BTCoex], BT is disabled !!\n");
+		else
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				    "[BTCoex], BT is enabled !!\n");
+
+		BTC_TRACE(trace_buf);
+
+		coex_sta->bt_coex_supported_feature = 0;
+		coex_sta->bt_coex_supported_version = 0;
+		coex_sta->bt_ble_scan_type = 0;
+		coex_sta->bt_ble_scan_para[0] = 0;
+		coex_sta->bt_ble_scan_para[1] = 0;
+		coex_sta->bt_ble_scan_para[2] = 0;
+		coex_sta->bt_reg_vendor_ac = 0xffff;
+		coex_sta->bt_reg_vendor_ae = 0xffff;
+		return true;
+	}
+
+	if (wifi_connected) {
+		if (wifi_busy != pre_wifi_busy) {
+			pre_wifi_busy = wifi_busy;
+
+			if (wifi_busy)
+				halbtc8723d1ant_post_state_to_bt(btcoexist,
+						BT_8723D_1ANT_SCOREBOARD_UNDERTEST, true);
+			else
+				halbtc8723d1ant_post_state_to_bt(btcoexist,
+						BT_8723D_1ANT_SCOREBOARD_UNDERTEST, false);
+			return true;
+		}
+		if (under_4way != pre_under_4way) {
+			pre_under_4way = under_4way;
+			return true;
+		}
+		if (bt_hs_on != pre_bt_hs_on) {
+			pre_bt_hs_on = bt_hs_on;
+			return true;
+		}
+		if (coex_sta->wl_noisy_level != pre_wl_noisy_level) {
+			pre_wl_noisy_level = coex_sta->wl_noisy_level;
+			return true;
+		}
+	}
+
+	if (!coex_sta->bt_disabled) {
+		if (coex_sta->hid_busy_num != pre_hid_busy_num) {
+			pre_hid_busy_num = coex_sta->hid_busy_num;
+			return true;
+		}
+	}
+
+	if (bt_link_info->slave_role != pre_bt_slave) {
+		pre_bt_slave = bt_link_info->slave_role;
+		return true;
+	}
+
+	return false;
+}
+
+void halbtc8723d1ant_monitor_bt_enable_disable(IN struct btc_coexist *btcoexist)
+{
+	static u32		bt_disable_cnt = 0;
+	boolean			bt_active = true, bt_disabled = false;
+	u16			u16tmp;
+
+	/* This function check if bt is disabled */
+#if 0
+	if (coex_sta->high_priority_tx == 0 &&
+	    coex_sta->high_priority_rx == 0 &&
+	    coex_sta->low_priority_tx == 0 &&
+	    coex_sta->low_priority_rx == 0)
+		bt_active = false;
+	if (coex_sta->high_priority_tx == 0xffff &&
+	    coex_sta->high_priority_rx == 0xffff &&
+	    coex_sta->low_priority_tx == 0xffff &&
+	    coex_sta->low_priority_rx == 0xffff)
+		bt_active = false;
+
+
+#else
+
+	/* Read BT on/off status from scoreboard[1], enable this only if BT patch support this feature */
+	halbtc8723d1ant_read_score_board(btcoexist,	&u16tmp);
+
+	bt_active = u16tmp & BIT(1);
+
+
+#endif
+
+	if (bt_active) {
+		bt_disable_cnt = 0;
+		bt_disabled = false;
+		btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_DISABLE,
+				   &bt_disabled);
+	} else {
+
+		bt_disable_cnt++;
+		if (bt_disable_cnt >= 2) {
+			bt_disabled = true;
+			bt_disable_cnt = 2;
+		}
+
+		btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_DISABLE,
+				   &bt_disabled);
+	}
+
+	if (bt_disabled)
+		halbtc8723d1ant_low_penalty_ra(btcoexist, NORMAL_EXEC, false);
+	else
+		halbtc8723d1ant_low_penalty_ra(btcoexist, NORMAL_EXEC, true);
+
+	if (coex_sta->bt_disabled != bt_disabled) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], BT is from %s to %s!!\n",
+			    (coex_sta->bt_disabled ? "disabled" : "enabled"),
+			    (bt_disabled ? "disabled" : "enabled"));
+		BTC_TRACE(trace_buf);
+		coex_sta->bt_disabled = bt_disabled;
+	}
+
+}
+
+
+
+void halbtc8723d1ant_enable_gnt_to_gpio(IN struct btc_coexist *btcoexist,
+					boolean isenable)
+{
+#if BT_8723D_1ANT_COEX_DBG
+	if (isenable) {
+		btcoexist->btc_write_1byte_bitmask(btcoexist, 0x73, 0x8, 0x1);
+
+		/* enable GNT_BT to GPIO debug */
+		btcoexist->btc_write_1byte_bitmask(btcoexist, 0x4e, 0x40, 0x0);
+		btcoexist->btc_write_1byte_bitmask(btcoexist, 0x67, 0x1, 0x0);
+
+		/* 0x48[20] = 0  for GPIO14 =  GNT_WL*/
+		btcoexist->btc_write_1byte_bitmask(btcoexist, 0x4a, 0x10, 0x0);
+		/* 0x40[17] = 0  for GPIO14 =  GNT_WL*/
+		btcoexist->btc_write_1byte_bitmask(btcoexist, 0x42, 0x02, 0x0);
+
+		/* 0x66[9] = 0   for GPIO15 =  GNT_B T*/
+		btcoexist->btc_write_1byte_bitmask(btcoexist, 0x67, 0x02, 0x0);
+		/* 0x66[7] = 0
+		for GPIO15 =  GNT_BT*/
+		btcoexist->btc_write_1byte_bitmask(btcoexist, 0x66, 0x80, 0x0);
+		/* 0x8[8] = 0    for GPIO15 =  GNT_BT*/
+		btcoexist->btc_write_1byte_bitmask(btcoexist, 0x9, 0x1, 0x0);
+
+		/* BT Vendor Reg 0x76[0] = 0  for GPIO15 =  GNT_BT, this is not set here*/
+	} else {
+		btcoexist->btc_write_1byte_bitmask(btcoexist, 0x73, 0x8, 0x0);
+
+		/* Disable GNT_BT debug to GPIO, and enable chip_wakeup_host */
+		btcoexist->btc_write_1byte_bitmask(btcoexist, 0x4e, 0x40, 0x1);
+		btcoexist->btc_write_1byte_bitmask(btcoexist, 0x67, 0x1, 0x1);
+
+		/* 0x48[20] = 0  for GPIO14 =  GNT_WL*/
+		btcoexist->btc_write_1byte_bitmask(btcoexist, 0x4a, 0x10, 0x1);
+	}
+
+#endif
+}
+
+u32 halbtc8723d1ant_ltecoex_indirect_read_reg(IN struct btc_coexist *btcoexist,
+		IN u16 reg_addr)
+{
+	u32 j = 0, delay_count = 0;
+
+
+	/* wait for ready bit before access 0x7c0		 */
+	btcoexist->btc_write_4byte(btcoexist, 0x7c0, 0x800F0000 | reg_addr);
+
+	while (1) {
+		if ((btcoexist->btc_read_1byte(btcoexist, 0x7c3)&BIT(5)) == 0) {
+			delay_ms(50);
+			delay_count++;
+			if (delay_count >= 10) {
+				delay_count = 0;
+				break;
+			}
+		} else
+			break;
+	}
+
+	return btcoexist->btc_read_4byte(btcoexist,
+					 0x7c8);  /* get read data */
+
+}
+
+void halbtc8723d1ant_ltecoex_indirect_write_reg(IN struct btc_coexist
+		*btcoexist,
+		IN u16 reg_addr, IN u32 bit_mask, IN u32 reg_value)
+{
+	u32 val, i = 0, j = 0, bitpos = 0, delay_count = 0;
+
+
+	if (bit_mask == 0x0)
+		return;
+	if (bit_mask == 0xffffffff) {
+		btcoexist->btc_write_4byte(btcoexist, 0x7c4,
+					   reg_value); /* put write data */
+
+		/* wait for ready bit before access 0x7c0 */
+		while (1) {
+		if ((btcoexist->btc_read_1byte(btcoexist, 0x7c3) & BIT(5)) == 0) {
+			delay_ms(50);
+			delay_count++;
+			if (delay_count >= 10) {
+				delay_count = 0;
+				break;
+			}
+		} else
+			break;
+	}
+
+		btcoexist->btc_write_4byte(btcoexist, 0x7c0,
+					   0xc00F0000 | reg_addr);
+	} else {
+		for (i = 0; i <= 31; i++) {
+			if (((bit_mask >> i) & 0x1) == 0x1) {
+				bitpos = i;
+				break;
+			}
+		}
+
+		/* read back register value before write */
+		val = halbtc8723d1ant_ltecoex_indirect_read_reg(btcoexist,
+				reg_addr);
+		val = (val & (~bit_mask)) | (reg_value << bitpos);
+
+		btcoexist->btc_write_4byte(btcoexist, 0x7c4,
+					   val); /* put write data */
+
+		/* wait for ready bit before access 0x7c0		 */
+		while (1) {
+		if ((btcoexist->btc_read_1byte(btcoexist, 0x7c3) & BIT(5)) == 0) {
+			delay_ms(50);
+			delay_count++;
+			if (delay_count >= 10) {
+				delay_count = 0;
+				break;
+			}
+		} else
+			break;
+	}
+
+		btcoexist->btc_write_4byte(btcoexist, 0x7c0,
+					   0xc00F0000 | reg_addr);
+
+	}
+
+}
+
+void halbtc8723d1ant_ltecoex_enable(IN struct btc_coexist *btcoexist,
+				    IN boolean enable)
+{
+	u8 val;
+
+	val = (enable) ? 1 : 0;
+	halbtc8723d1ant_ltecoex_indirect_write_reg(btcoexist, 0x38, 0x80,
+			val);  /* 0x38[7] */
+
+}
+
+void halbtc8723d1ant_ltecoex_pathcontrol_owner(IN struct btc_coexist *btcoexist,
+		IN boolean wifi_control)
+{
+	u8 val;
+
+	val = (wifi_control) ? 1 : 0;
+	btcoexist->btc_write_1byte_bitmask(btcoexist, 0x73, 0x4,
+					   val); /* 0x70[26] */
+
+}
+
+void halbtc8723d1ant_ltecoex_set_gnt_bt(IN struct btc_coexist *btcoexist,
+			IN u8 control_block, IN boolean sw_control, IN u8 state)
+{
+	u32 val = 0, val_orig = 0;
+
+	if (!sw_control)
+		val = 0x0;
+	else if (state & 0x1)
+		val = 0x3;
+	else
+		val = 0x1;
+
+	val_orig = halbtc8723d1ant_ltecoex_indirect_read_reg(btcoexist,
+				0x38);
+
+	switch (control_block) {
+	case BT_8723D_1ANT_GNT_BLOCK_RFC_BB:
+	default:
+		val = ((val << 14) | (val << 10)) | (val_orig & 0xffff33ff);
+		break;
+	case BT_8723D_1ANT_GNT_BLOCK_RFC:
+		val = (val << 14) | (val_orig & 0xffff3fff);
+		break;
+	case BT_8723D_1ANT_GNT_BLOCK_BB:
+		val = (val << 10) | (val_orig & 0xfffff3ff);
+		break;
+	}
+
+	halbtc8723d1ant_ltecoex_indirect_write_reg(btcoexist,
+				0x38, 0xffffffff, val);
+}
+
+
+void halbtc8723d1ant_ltecoex_set_gnt_wl(IN struct btc_coexist *btcoexist,
+			IN u8 control_block, IN boolean sw_control, IN u8 state)
+{
+	u32 val = 0, val_orig = 0;
+
+	if (!sw_control)
+		val = 0x0;
+	else if (state & 0x1)
+		val = 0x3;
+	else
+		val = 0x1;
+
+	val_orig = halbtc8723d1ant_ltecoex_indirect_read_reg(btcoexist,
+				0x38);
+
+	switch (control_block) {
+	case BT_8723D_1ANT_GNT_BLOCK_RFC_BB:
+	default:
+		val = ((val << 12) | (val << 8)) | (val_orig & 0xffffccff);
+		break;
+	case BT_8723D_1ANT_GNT_BLOCK_RFC:
+		val = (val << 12) | (val_orig & 0xffffcfff);
+		break;
+	case BT_8723D_1ANT_GNT_BLOCK_BB:
+		val = (val << 8) | (val_orig & 0xfffffcff);
+		break;
+	}
+
+	halbtc8723d1ant_ltecoex_indirect_write_reg(btcoexist, 0x38,
+		0xffffffff, val);
+}
+
+
+void halbtc8723d1ant_ltecoex_set_coex_table(IN struct btc_coexist *btcoexist,
+		IN u8 table_type, IN u16 table_content)
+{
+	u16 reg_addr = 0x0000;
+
+	switch (table_type) {
+	case BT_8723D_1ANT_CTT_WL_VS_LTE:
+		reg_addr = 0xa0;
+		break;
+	case BT_8723D_1ANT_CTT_BT_VS_LTE:
+		reg_addr = 0xa4;
+		break;
+	}
+
+	if (reg_addr != 0x0000)
+		halbtc8723d1ant_ltecoex_indirect_write_reg(btcoexist, reg_addr,
+			0xffff, table_content); /* 0xa0[15:0] or 0xa4[15:0] */
+
+
+}
+
+
+void halbtc8723d1ant_ltecoex_set_break_table(IN struct btc_coexist *btcoexist,
+		IN u8 table_type, IN u8 table_content)
+{
+	u16 reg_addr = 0x0000;
+
+	switch (table_type) {
+	case BT_8723D_1ANT_LBTT_WL_BREAK_LTE:
+		reg_addr = 0xa8;
+		break;
+	case BT_8723D_1ANT_LBTT_BT_BREAK_LTE:
+		reg_addr = 0xac;
+		break;
+	case BT_8723D_1ANT_LBTT_LTE_BREAK_WL:
+		reg_addr = 0xb0;
+		break;
+	case BT_8723D_1ANT_LBTT_LTE_BREAK_BT:
+		reg_addr = 0xb4;
+		break;
+	}
+
+	if (reg_addr != 0x0000)
+		halbtc8723d1ant_ltecoex_indirect_write_reg(btcoexist, reg_addr,
+			0xff, table_content); /* 0xa8[15:0] or 0xb4[15:0] */
+
+}
+
+void halbtc8723d1ant_set_wltoggle_coex_table(IN struct btc_coexist *btcoexist,
+		IN boolean force_exec,  IN u8 interval,
+		IN u8 val0x6c4_b0, IN u8 val0x6c4_b1, IN u8 val0x6c4_b2,
+		IN u8 val0x6c4_b3)
+{
+	static u8 pre_h2c_parameter[6] = {0};
+	u8	cur_h2c_parameter[6] = {0};
+	u8 i, match_cnt = 0;
+
+	cur_h2c_parameter[0] = 0x7;	/* op_code, 0x7= wlan toggle slot*/
+
+	cur_h2c_parameter[1] = interval;
+	cur_h2c_parameter[2] = val0x6c4_b0;
+	cur_h2c_parameter[3] = val0x6c4_b1;
+	cur_h2c_parameter[4] = val0x6c4_b2;
+	cur_h2c_parameter[5] = val0x6c4_b3;
+
+	if (!force_exec) {
+		for (i = 1; i <= 5; i++) {
+			if (cur_h2c_parameter[i] != pre_h2c_parameter[i])
+				break;
+
+			match_cnt++;
+		}
+
+		if (match_cnt == 5)
+			return;
+	}
+
+	for (i = 1; i <= 5; i++)
+		pre_h2c_parameter[i] = cur_h2c_parameter[i];
+
+	btcoexist->btc_fill_h2c(btcoexist, 0x69, 6, cur_h2c_parameter);
+}
+
+
+void halbtc8723d1ant_set_coex_table(IN struct btc_coexist *btcoexist,
+	    IN u32 val0x6c0, IN u32 val0x6c4, IN u32 val0x6c8, IN u8 val0x6cc)
+{
+	btcoexist->btc_write_4byte(btcoexist, 0x6c0, val0x6c0);
+
+	btcoexist->btc_write_4byte(btcoexist, 0x6c4, val0x6c4);
+
+	btcoexist->btc_write_4byte(btcoexist, 0x6c8, val0x6c8);
+
+	btcoexist->btc_write_1byte(btcoexist, 0x6cc, val0x6cc);
+}
+
+void halbtc8723d1ant_coex_table(IN struct btc_coexist *btcoexist,
+			IN boolean force_exec, IN u32 val0x6c0, IN u32 val0x6c4,
+				IN u32 val0x6c8, IN u8 val0x6cc)
+{
+	coex_dm->cur_val0x6c0 = val0x6c0;
+	coex_dm->cur_val0x6c4 = val0x6c4;
+	coex_dm->cur_val0x6c8 = val0x6c8;
+	coex_dm->cur_val0x6cc = val0x6cc;
+
+	if (!force_exec) {
+		if ((coex_dm->pre_val0x6c0 == coex_dm->cur_val0x6c0) &&
+		    (coex_dm->pre_val0x6c4 == coex_dm->cur_val0x6c4) &&
+		    (coex_dm->pre_val0x6c8 == coex_dm->cur_val0x6c8) &&
+		    (coex_dm->pre_val0x6cc == coex_dm->cur_val0x6cc))
+			return;
+	}
+
+	halbtc8723d1ant_set_coex_table(btcoexist, val0x6c0, val0x6c4, val0x6c8,
+				       val0x6cc);
+
+	coex_dm->pre_val0x6c0 = coex_dm->cur_val0x6c0;
+	coex_dm->pre_val0x6c4 = coex_dm->cur_val0x6c4;
+	coex_dm->pre_val0x6c8 = coex_dm->cur_val0x6c8;
+	coex_dm->pre_val0x6cc = coex_dm->cur_val0x6cc;
+}
+
+void halbtc8723d1ant_coex_table_with_type(IN struct btc_coexist *btcoexist,
+		IN boolean force_exec, IN u8 type)
+{
+	u32	break_table;
+	u8	select_table;
+
+	coex_sta->coex_table_type = type;
+
+	if (coex_sta->concurrent_rx_mode_on == true) {
+		break_table = 0xf0ffffff;  /* set WL hi-pri can break BT */
+		select_table =
+			0xb;		/* set Tx response = Hi-Pri (ex: Transmitting ACK,BA,CTS) */
+	} else {
+		break_table = 0xffffff;
+		select_table = 0x3;
+	}
+
+		switch (type) {
+		case 0:
+			halbtc8723d1ant_coex_table(btcoexist, force_exec,
+							0x55555555, 0x55555555, break_table,
+							select_table);
+			break;
+		case 1:
+			halbtc8723d1ant_coex_table(btcoexist, force_exec,
+							0x55555555, 0x5a5a5a5a, break_table,
+							select_table);
+			break;
+		case 2:
+			halbtc8723d1ant_coex_table(btcoexist, force_exec,
+							0xaa5a5a5a, 0xaa5a5a5a, break_table,
+							select_table);
+			break;
+		case 3:
+			halbtc8723d1ant_coex_table(btcoexist, force_exec,
+							0x55555555, 0x5a5a5a5a, break_table,
+							select_table);
+			break;
+		case 4:
+			halbtc8723d1ant_coex_table(btcoexist, force_exec,
+							0xa5555555, 0x5a5a5a5a, break_table,
+							select_table);
+			break;
+		case 5:
+			halbtc8723d1ant_coex_table(btcoexist, force_exec,
+							0x5a5a5a5a, 0x5a5a5a5a, break_table,
+							select_table);
+			break;
+		case 6:
+			halbtc8723d1ant_coex_table(btcoexist, force_exec,
+							0xa5555555, 0x5a5a5a5a, break_table,
+							select_table);
+			break;
+		case 7:
+			halbtc8723d1ant_coex_table(btcoexist, force_exec,
+							0xaa555555, 0xaa555555, break_table,
+							select_table);
+			break;
+		case 8:
+			halbtc8723d1ant_coex_table(btcoexist, force_exec,
+							0xa5555555, 0xaaaaaaaa, break_table,
+							select_table);
+			break;
+		case 9:
+			halbtc8723d1ant_coex_table(btcoexist, force_exec,
+							0x5a5a5a5a, 0xaaaa5aaa, break_table,
+							select_table);
+			break;
+		case 10:
+			halbtc8723d1ant_coex_table(btcoexist, force_exec,
+							0xaaaaaaaa, 0xaaaaaaaa, break_table,
+							select_table);
+			break;
+		default:
+			break;
+		}
+}
+
+void halbtc8723d1ant_set_fw_ignore_wlan_act(IN struct btc_coexist *btcoexist,
+		IN boolean enable)
+{
+	u8			h2c_parameter[1] = {0};
+
+	if (enable) {
+		h2c_parameter[0] |= BIT(0);		/* function enable */
+	}
+
+	btcoexist->btc_fill_h2c(btcoexist, 0x63, 1, h2c_parameter);
+}
+
+void halbtc8723d1ant_ignore_wlan_act(IN struct btc_coexist *btcoexist,
+				     IN boolean force_exec, IN boolean enable)
+{
+	coex_dm->cur_ignore_wlan_act = enable;
+
+	if (!force_exec) {
+		if (coex_dm->pre_ignore_wlan_act ==
+		    coex_dm->cur_ignore_wlan_act)
+			return;
+	}
+	halbtc8723d1ant_set_fw_ignore_wlan_act(btcoexist, enable);
+
+	coex_dm->pre_ignore_wlan_act = coex_dm->cur_ignore_wlan_act;
+}
+
+void halbtc8723d1ant_set_lps_rpwm(IN struct btc_coexist *btcoexist,
+				  IN u8 lps_val, IN u8 rpwm_val)
+{
+	u8	lps = lps_val;
+	u8	rpwm = rpwm_val;
+
+	btcoexist->btc_set(btcoexist, BTC_SET_U1_LPS_VAL, &lps);
+	btcoexist->btc_set(btcoexist, BTC_SET_U1_RPWM_VAL, &rpwm);
+}
+
+void halbtc8723d1ant_lps_rpwm(IN struct btc_coexist *btcoexist,
+		      IN boolean force_exec, IN u8 lps_val, IN u8 rpwm_val)
+{
+	coex_dm->cur_lps = lps_val;
+	coex_dm->cur_rpwm = rpwm_val;
+
+	if (!force_exec) {
+		if ((coex_dm->pre_lps == coex_dm->cur_lps) &&
+		    (coex_dm->pre_rpwm == coex_dm->cur_rpwm))
+			return;
+	}
+	halbtc8723d1ant_set_lps_rpwm(btcoexist, lps_val, rpwm_val);
+
+	coex_dm->pre_lps = coex_dm->cur_lps;
+	coex_dm->pre_rpwm = coex_dm->cur_rpwm;
+}
+
+void halbtc8723d1ant_ps_tdma_check_for_power_save_state(
+	IN struct btc_coexist *btcoexist, IN boolean new_ps_state)
+{
+	u8	lps_mode = 0x0;
+	u8	h2c_parameter[5] = {0x8, 0, 0, 0, 0};
+
+	btcoexist->btc_get(btcoexist, BTC_GET_U1_LPS_MODE, &lps_mode);
+
+	if (lps_mode) {	/* already under LPS state */
+		if (new_ps_state) {
+			/* keep state under LPS, do nothing. */
+		} else {
+			/* will leave LPS state, turn off psTdma first */
+			/*halbtc8723d1ant_ps_tdma(btcoexist, NORMAL_EXEC, false,
+						8); */
+			btcoexist->btc_fill_h2c(btcoexist, 0x60, 5,
+						h2c_parameter);
+		}
+	} else {					/* NO PS state */
+		if (new_ps_state) {
+			/* will enter LPS state, turn off psTdma first */
+			/*halbtc8723d1ant_ps_tdma(btcoexist, NORMAL_EXEC, false,
+						8);*/
+			btcoexist->btc_fill_h2c(btcoexist, 0x60, 5,
+						h2c_parameter);
+		} else {
+			/* keep state under NO PS state, do nothing. */
+		}
+	}
+}
+
+void halbtc8723d1ant_power_save_state(IN struct btc_coexist *btcoexist,
+			      IN u8 ps_type, IN u8 lps_val, IN u8 rpwm_val)
+{
+	boolean		low_pwr_disable = false;
+
+	switch (ps_type) {
+	case BTC_PS_WIFI_NATIVE:
+		/* recover to original 32k low power setting */
+		coex_sta->force_lps_on = false;
+		low_pwr_disable = false;
+		btcoexist->btc_set(btcoexist,
+				   BTC_SET_ACT_DISABLE_LOW_POWER,
+				   &low_pwr_disable);
+		btcoexist->btc_set(btcoexist, BTC_SET_ACT_NORMAL_LPS,
+				   NULL);
+
+		break;
+	case BTC_PS_LPS_ON:
+		coex_sta->force_lps_on = true;
+		halbtc8723d1ant_ps_tdma_check_for_power_save_state(
+			btcoexist, true);
+		halbtc8723d1ant_lps_rpwm(btcoexist, NORMAL_EXEC,
+					 lps_val, rpwm_val);
+		/* when coex force to enter LPS, do not enter 32k low power. */
+		low_pwr_disable = true;
+		btcoexist->btc_set(btcoexist,
+				   BTC_SET_ACT_DISABLE_LOW_POWER,
+				   &low_pwr_disable);
+		/* power save must executed before psTdma.			 */
+		btcoexist->btc_set(btcoexist, BTC_SET_ACT_ENTER_LPS,
+				   NULL);
+
+		break;
+	case BTC_PS_LPS_OFF:
+		coex_sta->force_lps_on = false;
+		halbtc8723d1ant_ps_tdma_check_for_power_save_state(
+			btcoexist, false);
+		btcoexist->btc_set(btcoexist, BTC_SET_ACT_LEAVE_LPS,
+				   NULL);
+
+		break;
+	default:
+		break;
+	}
+}
+
+
+void halbtc8723d1ant_set_fw_pstdma(IN struct btc_coexist *btcoexist,
+	   IN u8 byte1, IN u8 byte2, IN u8 byte3, IN u8 byte4, IN u8 byte5)
+{
+	u8			h2c_parameter[5] = {0};
+	u8			real_byte1 = byte1, real_byte5 = byte5;
+	boolean			ap_enable = false;
+	struct  btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
+
+	if (byte5 & BIT(2))
+		coex_sta->is_tdma_btautoslot = true;
+	else
+		coex_sta->is_tdma_btautoslot = false;
+
+	/* release bt-auto slot for auto-slot hang is detected!! */
+	if (coex_sta->is_tdma_btautoslot)
+		if ((coex_sta->is_tdma_btautoslot_hang) ||
+			(bt_link_info->slave_role))
+			byte5 = byte5 & 0xfb;
+
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_AP_MODE_ENABLE,
+			   &ap_enable);
+
+	if (ap_enable) {
+		if (byte1 & BIT(4) && !(byte1 & BIT(5))) {
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				    "[BTCoex], FW for AP mode\n");
+			BTC_TRACE(trace_buf);
+			real_byte1 &= ~BIT(4);
+			real_byte1 |= BIT(5);
+
+			real_byte5 |= BIT(5);
+			real_byte5 &= ~BIT(6);
+
+			halbtc8723d1ant_power_save_state(btcoexist,
+						 BTC_PS_WIFI_NATIVE, 0x0,
+							 0x0);
+		}
+	} else if (byte1 & BIT(4) && !(byte1 & BIT(5))) {
+
+		halbtc8723d1ant_power_save_state(
+			btcoexist, BTC_PS_LPS_ON, 0x50,
+			0x4);
+	} else {
+		halbtc8723d1ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE,
+						 0x0,
+						 0x0);
+	}
+
+
+	h2c_parameter[0] = real_byte1;
+	h2c_parameter[1] = byte2;
+	h2c_parameter[2] = byte3;
+	h2c_parameter[3] = byte4;
+	h2c_parameter[4] = real_byte5;
+
+	coex_dm->ps_tdma_para[0] = real_byte1;
+	coex_dm->ps_tdma_para[1] = byte2;
+	coex_dm->ps_tdma_para[2] = byte3;
+	coex_dm->ps_tdma_para[3] = byte4;
+	coex_dm->ps_tdma_para[4] = real_byte5;
+
+	btcoexist->btc_fill_h2c(btcoexist, 0x60, 5, h2c_parameter);
+}
+
+
+void halbtc8723d1ant_ps_tdma(IN struct btc_coexist *btcoexist,
+		     IN boolean force_exec, IN boolean turn_on, IN u8 type)
+{
+	struct  btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
+	struct  btc_board_info	*board_info = &btcoexist->board_info;
+	boolean			wifi_busy = false;
+	static u8			psTdmaByte4Modify = 0x0, pre_psTdmaByte4Modify = 0x0;
+	static boolean	 pre_wifi_busy = false;
+
+
+#if BT_8723D_1ANT_ANTDET_ENABLE
+
+	if (board_info->btdm_ant_num_by_ant_det == 2) {
+#if 0
+		if (turn_on)
+			type = type +
+			       100;
+#endif
+	}
+
+#endif
+
+	coex_dm->cur_ps_tdma_on = turn_on;
+	coex_dm->cur_ps_tdma = type;
+
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy);
+
+	if (wifi_busy != pre_wifi_busy) {
+		force_exec = true;
+		pre_wifi_busy = wifi_busy;
+	}
+
+	/* 0x778 = 0x1 at wifi slot (no blocking BT Low-Pri pkts) */
+	if ((bt_link_info->slave_role) && (bt_link_info->a2dp_exist))
+		psTdmaByte4Modify = 0x1;
+	else
+		psTdmaByte4Modify = 0x0;
+
+	if (pre_psTdmaByte4Modify != psTdmaByte4Modify) {
+
+		force_exec = true;
+		pre_psTdmaByte4Modify = psTdmaByte4Modify;
+	}
+
+	if (!force_exec) {
+		if ((coex_dm->pre_ps_tdma_on == coex_dm->cur_ps_tdma_on) &&
+		    (coex_dm->pre_ps_tdma == coex_dm->cur_ps_tdma))
+			return;
+	}
+
+	if (coex_dm->cur_ps_tdma_on) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], ********** TDMA(on, %d) **********\n",
+			    coex_dm->cur_ps_tdma);
+		BTC_TRACE(trace_buf);
+
+		btcoexist->btc_write_1byte_bitmask(btcoexist, 0x550, 0x8,
+					   0x1);  /* enable TBTT nterrupt */
+	} else {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], ********** TDMA(off, %d) **********\n",
+			    coex_dm->cur_ps_tdma);
+		BTC_TRACE(trace_buf);
+	}
+
+
+	if (turn_on) {
+		switch (type) {
+		default:
+			halbtc8723d1ant_set_fw_pstdma(btcoexist,
+							0x61, 0x35, 0x03, 0x11, 0x11);
+			break;
+		case 3:
+			halbtc8723d1ant_set_fw_pstdma(btcoexist,
+							0x51, 0x3a, 0x03, 0x10, 0x50);
+			break;
+		case 4:
+			halbtc8723d1ant_set_fw_pstdma(btcoexist,
+							0x51, 0x21, 0x03, 0x10, 0x50);
+			break;
+		case 5:
+			halbtc8723d1ant_set_fw_pstdma(btcoexist,
+							0x61, 0x15, 0x03, 0x11, 0x11);
+			break;
+		case 6:
+			halbtc8723d1ant_set_fw_pstdma(btcoexist,
+							0x61, 0x20, 0x03, 0x11, 0x11);
+			break;
+		case 7:
+			halbtc8723d1ant_set_fw_pstdma(btcoexist,
+							0x51, 0x10, 0x03, 0x10,  0x54 |
+							psTdmaByte4Modify);
+			break;
+		case 8:
+			halbtc8723d1ant_set_fw_pstdma(btcoexist,
+							0x51, 0x10, 0x03, 0x10,  0x54 |
+							psTdmaByte4Modify);
+			break;
+		case 9:
+			halbtc8723d1ant_set_fw_pstdma(btcoexist,
+							0x55, 0x10, 0x03, 0x10,  0x54 |
+							psTdmaByte4Modify);
+			break;
+		case 10:
+			halbtc8723d1ant_set_fw_pstdma(btcoexist,
+							0x61, 0x30, 0x03, 0x11, 0x10);
+			break;
+		case 11:
+			halbtc8723d1ant_set_fw_pstdma(btcoexist,
+							0x65, 0x25, 0x03, 0x11,  0x11 |
+							psTdmaByte4Modify);
+			break;
+		case 12:
+			halbtc8723d1ant_set_fw_pstdma(btcoexist,
+							0x55, 0x30, 0x03, 0x10,  0x50 |
+							psTdmaByte4Modify);
+			break;
+		case 13:
+			halbtc8723d1ant_set_fw_pstdma(btcoexist,
+							0x51, 0x25, 0x03, 0x10,  0x50 |
+							psTdmaByte4Modify);
+			break;
+		case 14:
+			halbtc8723d1ant_set_fw_pstdma(btcoexist,
+							0x51, 0x15, 0x03, 0x10,  0x50 |
+							psTdmaByte4Modify);
+			break;
+		case 15:
+			halbtc8723d1ant_set_fw_pstdma(btcoexist,
+							0x51, 0x20, 0x03, 0x10,  0x50 |
+							psTdmaByte4Modify);
+			break;
+		case 16:
+			halbtc8723d1ant_set_fw_pstdma(btcoexist,
+							0x61, 0x10, 0x03, 0x11,  0x15 |
+							psTdmaByte4Modify);
+			break;
+		case 17:
+			halbtc8723d1ant_set_fw_pstdma(btcoexist,
+							0x61, 0x10, 0x03, 0x11, 0x14);
+			break;
+		case 18:
+			halbtc8723d1ant_set_fw_pstdma(btcoexist,
+							0x51, 0x30, 0x03, 0x10,  0x50 |
+							psTdmaByte4Modify);
+			break;
+		case 19:
+			halbtc8723d1ant_set_fw_pstdma(btcoexist,
+							0x61, 0x15, 0x03, 0x11, 0x10);
+			break;
+		case 20:
+			halbtc8723d1ant_set_fw_pstdma(btcoexist,
+							0x61, 0x30, 0x03, 0x11, 0x10);
+			break;
+		case 21:
+			halbtc8723d1ant_set_fw_pstdma(btcoexist,
+							0x61, 0x30, 0x03, 0x11, 0x10);
+			break;
+		case 22:
+			halbtc8723d1ant_set_fw_pstdma(btcoexist,
+							0x61, 0x25, 0x03, 0x11, 0x10);
+			break;
+		case 23:
+			halbtc8723d1ant_set_fw_pstdma(btcoexist,
+							0x61, 0x10, 0x03, 0x11, 0x10);
+			break;
+		case 27:
+			halbtc8723d1ant_set_fw_pstdma(btcoexist,
+							0x61, 0x10, 0x03, 0x11, 0x15);
+			break;
+		case 32:
+			halbtc8723d1ant_set_fw_pstdma(btcoexist,
+							0x61, 0x35, 0x03, 0x11, 0x11);
+			break;
+		case 33:
+			halbtc8723d1ant_set_fw_pstdma(btcoexist,
+							0x61, 0x35, 0x03, 0x11, 0x10);
+			break;
+		case 57:
+			halbtc8723d1ant_set_fw_pstdma(btcoexist,
+							0x51, 0x10, 0x03, 0x10,  0x50 |
+							psTdmaByte4Modify);
+			break;
+		case 58:
+			halbtc8723d1ant_set_fw_pstdma(btcoexist,
+							0x51, 0x10, 0x03, 0x10,  0x50 |
+							psTdmaByte4Modify);
+			break;
+		case 67:
+			halbtc8723d1ant_set_fw_pstdma(btcoexist,
+							0x61, 0x10, 0x03, 0x11,  0x10 |
+							psTdmaByte4Modify);
+			break;
+		/*     1-Ant to 2-Ant      TDMA case */
+		case 103:
+			halbtc8723d1ant_set_fw_pstdma(btcoexist,
+							0xd3, 0x3a, 0x03, 0x70, 0x10);
+			break;
+		case 104:
+			halbtc8723d1ant_set_fw_pstdma(btcoexist,
+							0xd3, 0x21, 0x03, 0x70, 0x10);
+			break;
+		case 105:
+			halbtc8723d1ant_set_fw_pstdma(btcoexist,
+							0xe3, 0x15, 0x03, 0x71, 0x11);
+			break;
+		case 106:
+			halbtc8723d1ant_set_fw_pstdma(btcoexist,
+							0xe3, 0x20, 0x03, 0x71, 0x11);
+			break;
+		case 107:
+			halbtc8723d1ant_set_fw_pstdma(btcoexist,
+							0xd3, 0x10, 0x03, 0x70,  0x14 |
+							psTdmaByte4Modify);
+			break;
+		case 108:
+			halbtc8723d1ant_set_fw_pstdma(btcoexist,
+							0xd3, 0x10, 0x03, 0x70,  0x14 |
+							psTdmaByte4Modify);
+			break;
+		case 113:
+			halbtc8723d1ant_set_fw_pstdma(btcoexist,
+							0xd3, 0x25, 0x03, 0x70,  0x10 |
+							psTdmaByte4Modify);
+			break;
+		case 114:
+			halbtc8723d1ant_set_fw_pstdma(btcoexist,
+							0xd3, 0x15, 0x03, 0x70,  0x10 |
+							psTdmaByte4Modify);
+			break;
+		case 115:
+			halbtc8723d1ant_set_fw_pstdma(btcoexist,
+							0xd3, 0x20, 0x03, 0x70,  0x10 |
+							psTdmaByte4Modify);
+			break;
+		case 117:
+			halbtc8723d1ant_set_fw_pstdma(btcoexist,
+							0xe3, 0x10, 0x03, 0x71,  0x14 |
+							psTdmaByte4Modify);
+			break;
+		case 119:
+			halbtc8723d1ant_set_fw_pstdma(btcoexist,
+							0xe3, 0x15, 0x03, 0x71, 0x10);
+			break;
+		case 120:
+			halbtc8723d1ant_set_fw_pstdma(btcoexist,
+							0xe3, 0x30, 0x03, 0x71, 0x10);
+			break;
+		case 121:
+			halbtc8723d1ant_set_fw_pstdma(btcoexist,
+							0xe3, 0x30, 0x03, 0x71, 0x10);
+			break;
+		case 122:
+			halbtc8723d1ant_set_fw_pstdma(btcoexist,
+							0xe3, 0x25, 0x03, 0x71, 0x10);
+			break;
+		case 132:
+			halbtc8723d1ant_set_fw_pstdma(btcoexist,
+							0xe3, 0x35, 0x03, 0x71, 0x11);
+			break;
+		case 133:
+			halbtc8723d1ant_set_fw_pstdma(btcoexist,
+							0xe3, 0x35, 0x03, 0x71, 0x10);
+			break;
+		}
+	} else {
+
+		/* disable PS tdma */
+		switch (type) {
+		case 8: /* PTA Control */
+			halbtc8723d1ant_set_fw_pstdma(btcoexist, 0x8,
+						      0x0, 0x0, 0x0, 0x0);
+			break;
+		case 0:
+		default:  /* Software control, Antenna at BT side */
+			halbtc8723d1ant_set_fw_pstdma(btcoexist, 0x0,
+						      0x0, 0x0, 0x0, 0x0);
+			break;
+		case 1: /* 2-Ant, 0x778=3, antenna control by antenna diversity */
+			halbtc8723d1ant_set_fw_pstdma(btcoexist, 0x0,
+						      0x0, 0x0, 0x48, 0x0);
+			break;
+		}
+	}
+
+	/* update pre state */
+	coex_dm->pre_ps_tdma_on = coex_dm->cur_ps_tdma_on;
+	coex_dm->pre_ps_tdma = coex_dm->cur_ps_tdma;
+}
+
+
+void halbtc8723d1ant_set_ant_path(IN struct btc_coexist *btcoexist,
+				  IN u8 ant_pos_type, IN boolean force_exec,
+				  IN u8 phase)
+{
+	struct  btc_board_info *board_info = &btcoexist->board_info;
+	u32			cnt_bt_cal_chk = 0;
+	boolean			is_in_mp_mode = false, is_hw_ant_div_on = false;
+	u8			u8tmp0 = 0, u8tmp1 = 0;
+	u32			u32tmp1 = 0, u32tmp2 = 0, u32tmp3 = 0;
+	u16			u16tmp0, u16tmp1 = 0;
+
+#if BT_8723D_1ANT_ANTDET_ENABLE
+
+	if (ant_pos_type == BTC_ANT_PATH_PTA) {
+		if ((board_info->btdm_ant_det_finish) &&
+		    (board_info->btdm_ant_num_by_ant_det == 2)) {
+			if (board_info->btdm_ant_pos ==
+			    BTC_ANTENNA_AT_MAIN_PORT)
+				ant_pos_type = BTC_ANT_PATH_WIFI;
+			else
+				ant_pos_type = BTC_ANT_PATH_BT;
+		}
+	}
+
+#endif
+
+	u32tmp1 = halbtc8723d1ant_ltecoex_indirect_read_reg(btcoexist,
+				0x38);
+
+	/* To avoid indirect access fail	*/
+	if (((u32tmp1 & 0xf000) >> 12) != ((u32tmp1 & 0x0f00) >> 8)) {
+		force_exec = true;
+		coex_sta->gnt_error_cnt++;
+	}
+
+#if BT_8723D_1ANT_COEX_DBG
+	u32tmp2 = halbtc8723d1ant_ltecoex_indirect_read_reg(btcoexist, 0x54);
+	u16tmp0 = btcoexist->btc_read_2byte(btcoexist, 0xaa);
+	u16tmp1 = btcoexist->btc_read_2byte(btcoexist, 0x948);
+	u8tmp1  = btcoexist->btc_read_1byte(btcoexist, 0x73);
+	u8tmp0 =  btcoexist->btc_read_1byte(btcoexist, 0x67);
+
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+		"[BTCoex], ********** 0x67 = 0x%x, 0x948 = 0x%x, 0x73 = 0x%x(Before Set Ant Pat)\n",
+		    u8tmp0, u16tmp1, u8tmp1);
+	BTC_TRACE(trace_buf);
+
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+		"[BTCoex], **********0x38= 0x%x, 0x54= 0x%x, 0xaa = 0x%x(Before Set Ant Path)\n",
+		    u32tmp1, u32tmp2, u16tmp0);
+	BTC_TRACE(trace_buf);
+#endif
+
+	coex_dm->cur_ant_pos_type = ant_pos_type;
+
+	if (!force_exec) {
+		if (coex_dm->cur_ant_pos_type == coex_dm->pre_ant_pos_type) {
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				"[BTCoex], ********** Skip Antenna Path Setup because no change!!**********\n");
+			BTC_TRACE(trace_buf);
+			return;
+		}
+	}
+
+	coex_dm->pre_ant_pos_type = coex_dm->cur_ant_pos_type;
+
+
+	switch (phase) {
+	case BT_8723D_1ANT_PHASE_COEX_POWERON:
+		/* Set Path control to WL */
+		btcoexist->btc_write_1byte_bitmask(btcoexist, 0x67,
+						   0x80, 0x0);
+
+		/* set Path control owner to WL at initial step */
+		halbtc8723d1ant_ltecoex_pathcontrol_owner(btcoexist,
+				BT_8723D_1ANT_PCO_BTSIDE);
+
+		/* set GNT_BT to SW high */
+		halbtc8723d1ant_ltecoex_set_gnt_bt(btcoexist,
+					   BT_8723D_1ANT_GNT_BLOCK_RFC_BB,
+					   BT_8723D_1ANT_GNT_TYPE_CTRL_BY_SW,
+					   BT_8723D_1ANT_SIG_STA_SET_TO_HIGH);
+		/* Set GNT_WL to SW low */
+		halbtc8723d1ant_ltecoex_set_gnt_wl(btcoexist,
+					   BT_8723D_1ANT_GNT_BLOCK_RFC_BB,
+					   BT_8723D_1ANT_GNT_TYPE_CTRL_BY_SW,
+					   BT_8723D_1ANT_SIG_STA_SET_TO_HIGH);
+
+		if (BTC_ANT_PATH_AUTO == ant_pos_type)
+			ant_pos_type = BTC_ANT_PATH_BT;
+
+		coex_sta->run_time_state = false;
+
+		break;
+	case BT_8723D_1ANT_PHASE_COEX_INIT:
+		/* Disable LTE Coex Function in WiFi side (this should be on if LTE coex is required) */
+		halbtc8723d1ant_ltecoex_enable(btcoexist, 0x0);
+
+		/* GNT_WL_LTE always = 1 (this should be config if LTE coex is required) */
+		halbtc8723d1ant_ltecoex_set_coex_table(btcoexist,
+				       BT_8723D_1ANT_CTT_WL_VS_LTE, 0xffff);
+
+		/* GNT_BT_LTE always = 1 (this should be config if LTE coex is required) */
+		halbtc8723d1ant_ltecoex_set_coex_table(btcoexist,
+				       BT_8723D_1ANT_CTT_BT_VS_LTE, 0xffff);
+
+		/* Wait If BT IQK running, because Path control owner is at BT during BT IQK (setup by WiFi firmware) */
+		while (cnt_bt_cal_chk <= 20) {
+			u8tmp0 = btcoexist->btc_read_1byte(btcoexist,
+							   0x49d);
+			cnt_bt_cal_chk++;
+			if (u8tmp0 & BIT(0)) {
+				BTC_SPRINTF(trace_buf,
+					    BT_TMP_BUF_SIZE,
+					"[BTCoex], ########### BT is calibrating (wait cnt=%d) ###########\n",
+					    cnt_bt_cal_chk);
+				BTC_TRACE(trace_buf);
+				delay_ms(50);
+			} else {
+				BTC_SPRINTF(trace_buf,
+					    BT_TMP_BUF_SIZE,
+					"[BTCoex], ********** WL is NOT calibrating (wait cnt=%d)**********\n",
+					    cnt_bt_cal_chk);
+				BTC_TRACE(trace_buf);
+				break;
+			}
+		}
+
+		/* Set Path control to WL */
+		btcoexist->btc_write_1byte_bitmask(btcoexist, 0x67,
+						   0x80, 0x1);
+
+		/* set Path control owner to WL at initial step */
+		halbtc8723d1ant_ltecoex_pathcontrol_owner(btcoexist,
+				BT_8723D_1ANT_PCO_WLSIDE);
+
+		/* set GNT_BT to SW high */
+		halbtc8723d1ant_ltecoex_set_gnt_bt(btcoexist,
+					   BT_8723D_1ANT_GNT_BLOCK_RFC_BB,
+					   BT_8723D_1ANT_GNT_TYPE_CTRL_BY_SW,
+					   BT_8723D_1ANT_SIG_STA_SET_TO_HIGH);
+		/* Set GNT_WL to SW low */
+		halbtc8723d1ant_ltecoex_set_gnt_wl(btcoexist,
+					   BT_8723D_1ANT_GNT_BLOCK_RFC_BB,
+					   BT_8723D_1ANT_GNT_TYPE_CTRL_BY_SW,
+					   BT_8723D_1ANT_SIG_STA_SET_TO_HIGH);
+
+		if (BTC_ANT_PATH_AUTO == ant_pos_type)
+			ant_pos_type = BTC_ANT_PATH_BT;
+
+		coex_sta->run_time_state = false;
+		break;
+	case BT_8723D_1ANT_PHASE_WLANONLY_INIT:
+		/* Disable LTE Coex Function in WiFi side (this should be on if LTE coex is required) */
+		halbtc8723d1ant_ltecoex_enable(btcoexist, 0x0);
+
+		/* GNT_WL_LTE always = 1 (this should be config if LTE coex is required) */
+		halbtc8723d1ant_ltecoex_set_coex_table(btcoexist,
+				       BT_8723D_1ANT_CTT_WL_VS_LTE, 0xffff);
+
+		/* GNT_BT_LTE always = 1 (this should be config if LTE coex is required) */
+		halbtc8723d1ant_ltecoex_set_coex_table(btcoexist,
+				       BT_8723D_1ANT_CTT_BT_VS_LTE, 0xffff);
+
+		/* Set Path control to WL */
+		btcoexist->btc_write_1byte_bitmask(btcoexist, 0x67,
+						   0x80, 0x1);
+
+		/* set Path control owner to WL at initial step */
+		halbtc8723d1ant_ltecoex_pathcontrol_owner(btcoexist,
+				BT_8723D_1ANT_PCO_WLSIDE);
+
+		/* set GNT_BT to SW low */
+		halbtc8723d1ant_ltecoex_set_gnt_bt(btcoexist,
+					   BT_8723D_1ANT_GNT_BLOCK_RFC_BB,
+					   BT_8723D_1ANT_GNT_TYPE_CTRL_BY_SW,
+					   BT_8723D_1ANT_SIG_STA_SET_TO_LOW);
+		/* Set GNT_WL to SW high */
+		halbtc8723d1ant_ltecoex_set_gnt_wl(btcoexist,
+					   BT_8723D_1ANT_GNT_BLOCK_RFC_BB,
+					   BT_8723D_1ANT_GNT_TYPE_CTRL_BY_SW,
+					   BT_8723D_1ANT_SIG_STA_SET_TO_HIGH);
+
+		if (BTC_ANT_PATH_AUTO == ant_pos_type)
+			ant_pos_type = BTC_ANT_PATH_WIFI;
+
+		coex_sta->run_time_state = false;
+		break;
+	case BT_8723D_1ANT_PHASE_WLAN_OFF:
+		/* Disable LTE Coex Function in WiFi side */
+		halbtc8723d1ant_ltecoex_enable(btcoexist, 0x0);
+
+		/* Set Path control to BT */
+		btcoexist->btc_write_1byte_bitmask(btcoexist, 0x67,
+						   0x80, 0x0);
+
+		/* set Path control owner to BT */
+		halbtc8723d1ant_ltecoex_pathcontrol_owner(btcoexist,
+				BT_8723D_1ANT_PCO_BTSIDE);
+
+		if (BTC_ANT_PATH_AUTO == ant_pos_type)
+			ant_pos_type = BTC_ANT_PATH_BT;
+
+		coex_sta->run_time_state = false;
+		break;
+	case BT_8723D_1ANT_PHASE_2G_RUNTIME:
+
+		/* wait for WL/BT IQK finish, keep 0x38 = 0xff00 for WL IQK */
+		while (cnt_bt_cal_chk <= 20) {
+			u8tmp0 = btcoexist->btc_read_1byte(btcoexist,
+							   0x1e6);
+
+			u8tmp1 = btcoexist->btc_read_1byte(btcoexist,
+							   0x49d);
+
+			cnt_bt_cal_chk++;
+			if ((u8tmp0 & BIT(0)) || (u8tmp1 & BIT(0))) {
+				BTC_SPRINTF(trace_buf,
+					    BT_TMP_BUF_SIZE,
+					"[BTCoex], ########### WL or BT is IQK (wait cnt=%d)\n",
+					    cnt_bt_cal_chk);
+				BTC_TRACE(trace_buf);
+				delay_ms(50);
+			} else {
+				BTC_SPRINTF(trace_buf,
+					    BT_TMP_BUF_SIZE,
+					"[BTCoex], ********** WL and BT is NOT IQK (wait cnt=%d)\n",
+					    cnt_bt_cal_chk);
+				BTC_TRACE(trace_buf);
+				break;
+			}
+		}
+
+
+		/* Set Path control to WL */
+		/* btcoexist->btc_write_1byte_bitmask(btcoexist, 0x67, 0x80, 0x1); */
+
+		halbtc8723d1ant_ltecoex_pathcontrol_owner(btcoexist,
+				BT_8723D_1ANT_PCO_WLSIDE);
+
+		/* set GNT_BT to PTA */
+		halbtc8723d1ant_ltecoex_set_gnt_bt(btcoexist,
+					   BT_8723D_1ANT_GNT_BLOCK_RFC_BB,
+					   BT_8723D_1ANT_GNT_TYPE_CTRL_BY_PTA,
+					   BT_8723D_1ANT_SIG_STA_SET_BY_HW);
+		/* Set GNT_WL to PTA */
+		halbtc8723d1ant_ltecoex_set_gnt_wl(btcoexist,
+					   BT_8723D_1ANT_GNT_BLOCK_RFC_BB,
+					   BT_8723D_1ANT_GNT_TYPE_CTRL_BY_PTA,
+					   BT_8723D_1ANT_SIG_STA_SET_BY_HW);
+
+		if (BTC_ANT_PATH_AUTO == ant_pos_type)
+			ant_pos_type = BTC_ANT_PATH_PTA;
+
+		coex_sta->run_time_state = true;
+		break;
+	case BT_8723D_1ANT_PHASE_BTMPMODE:
+		halbtc8723d1ant_ltecoex_pathcontrol_owner(btcoexist,
+				BT_8723D_1ANT_PCO_WLSIDE);
+
+		/* Set Path control to WL */
+		btcoexist->btc_write_1byte_bitmask(btcoexist, 0x67,
+						   0x80, 0x1);
+
+		/* set GNT_BT to high */
+		halbtc8723d1ant_ltecoex_set_gnt_bt(btcoexist,
+					   BT_8723D_1ANT_GNT_BLOCK_RFC_BB,
+					   BT_8723D_1ANT_GNT_TYPE_CTRL_BY_SW,
+					   BT_8723D_1ANT_SIG_STA_SET_TO_HIGH);
+		/* Set GNT_WL to low */
+		halbtc8723d1ant_ltecoex_set_gnt_wl(btcoexist,
+					   BT_8723D_1ANT_GNT_BLOCK_RFC_BB,
+					   BT_8723D_1ANT_GNT_TYPE_CTRL_BY_SW,
+					   BT_8723D_1ANT_SIG_STA_SET_TO_LOW);
+
+		if (BTC_ANT_PATH_AUTO == ant_pos_type)
+			ant_pos_type = BTC_ANT_PATH_BT;
+
+		coex_sta->run_time_state = false;
+		break;
+	case BT_8723D_1ANT_PHASE_ANTENNA_DET:
+		halbtc8723d1ant_ltecoex_pathcontrol_owner(btcoexist,
+				BT_8723D_1ANT_PCO_WLSIDE);
+
+		/* Set Path control to WL */
+		btcoexist->btc_write_1byte_bitmask(btcoexist, 0x67,
+						   0x80, 0x1);
+
+		/* set GNT_BT to high */
+		halbtc8723d1ant_ltecoex_set_gnt_bt(btcoexist,
+					   BT_8723D_1ANT_GNT_BLOCK_RFC_BB,
+					   BT_8723D_1ANT_GNT_TYPE_CTRL_BY_SW,
+					   BT_8723D_1ANT_SIG_STA_SET_TO_HIGH);
+		/* Set GNT_WL to high */
+		halbtc8723d1ant_ltecoex_set_gnt_wl(btcoexist,
+					   BT_8723D_1ANT_GNT_BLOCK_RFC_BB,
+					   BT_8723D_1ANT_GNT_TYPE_CTRL_BY_SW,
+					   BT_8723D_1ANT_SIG_STA_SET_TO_HIGH);
+
+		if (BTC_ANT_PATH_AUTO == ant_pos_type)
+			ant_pos_type = BTC_ANT_PATH_BT;
+
+		coex_sta->run_time_state = false;
+
+		break;
+	}
+
+
+	is_hw_ant_div_on = board_info->ant_div_cfg;
+
+	if ((is_hw_ant_div_on) && (phase != BT_8723D_1ANT_PHASE_ANTENNA_DET))
+
+		if (board_info->btdm_ant_pos == BTC_ANTENNA_AT_MAIN_PORT)
+			/* 0x948 = 0x200, 0x0 while antenna diversity */
+			btcoexist->btc_write_2byte(btcoexist, 0x948, 0x100);
+		else /* 0x948 = 0x80, 0x0 while antenna diversity */
+			btcoexist->btc_write_2byte(btcoexist, 0x948, 0x40);
+
+	else if ((is_hw_ant_div_on == false) &&
+		(phase != BT_8723D_1ANT_PHASE_WLAN_OFF)) {  /* internal switch setting */
+
+		switch (ant_pos_type) {
+
+		case BTC_ANT_PATH_WIFI:
+			if (board_info->btdm_ant_pos ==
+			    BTC_ANTENNA_AT_MAIN_PORT)
+
+				btcoexist->btc_write_2byte(
+					btcoexist, 0x948, 0x0);
+			else
+				btcoexist->btc_write_2byte(
+					btcoexist, 0x948, 0x280);
+
+			break;
+		case BTC_ANT_PATH_BT:
+			if (board_info->btdm_ant_pos ==
+			    BTC_ANTENNA_AT_MAIN_PORT)
+
+				btcoexist->btc_write_2byte(
+					btcoexist, 0x948, 0x280);
+			else
+				btcoexist->btc_write_2byte(
+					btcoexist, 0x948, 0x0);
+
+			break;
+		default:
+		case BTC_ANT_PATH_PTA:
+			if (board_info->btdm_ant_pos ==
+			    BTC_ANTENNA_AT_MAIN_PORT)
+				btcoexist->btc_write_2byte(
+					btcoexist, 0x948,
+					0x200);
+			else
+				btcoexist->btc_write_2byte(
+					btcoexist, 0x948, 0x80);
+			break;
+		}
+	}
+
+
+#if BT_8723D_1ANT_COEX_DBG
+	u32tmp1 = halbtc8723d1ant_ltecoex_indirect_read_reg(btcoexist, 0x38);
+	u32tmp2 = halbtc8723d1ant_ltecoex_indirect_read_reg(btcoexist, 0x54);
+	u16tmp0 = btcoexist->btc_read_2byte(btcoexist, 0xaa);
+	u16tmp1 = btcoexist->btc_read_2byte(btcoexist, 0x948);
+	u8tmp1  = btcoexist->btc_read_1byte(btcoexist, 0x73);
+	u8tmp0 =  btcoexist->btc_read_1byte(btcoexist, 0x67);
+
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+		"[BTCoex], ********** 0x67 = 0x%x, 0x948 = 0x%x, 0x73 = 0x%x(After Set Ant Pat)\n",
+		    u8tmp0, u16tmp1, u8tmp1);
+	BTC_TRACE(trace_buf);
+
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+		"[BTCoex], **********0x38= 0x%x, 0x54= 0x%x, 0xaa = 0x%x(After Set Ant Path)\n",
+		    u32tmp1, u32tmp2, u16tmp0);
+	BTC_TRACE(trace_buf);
+#endif
+
+}
+
+
+boolean halbtc8723d1ant_is_common_action(IN struct btc_coexist *btcoexist)
+{
+	boolean			common = false, wifi_connected = false, wifi_busy = false;
+
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED,
+			   &wifi_connected);
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy);
+
+	if (!wifi_connected &&
+	    BT_8723D_1ANT_BT_STATUS_NON_CONNECTED_IDLE ==
+	    coex_dm->bt_status) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			"[BTCoex], Wifi non connected-idle + BT non connected-idle!!\n");
+		BTC_TRACE(trace_buf);
+		common = true;
+	} else if (wifi_connected &&
+		   (BT_8723D_1ANT_BT_STATUS_NON_CONNECTED_IDLE ==
+		    coex_dm->bt_status)) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			"[BTCoex], Wifi connected + BT non connected-idle!!\n");
+		BTC_TRACE(trace_buf);
+		common = true;
+	} else if (!wifi_connected &&
+		   (BT_8723D_1ANT_BT_STATUS_CONNECTED_IDLE ==
+		    coex_dm->bt_status)) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			"[BTCoex], Wifi non connected-idle + BT connected-idle!!\n");
+		BTC_TRACE(trace_buf);
+		common = true;
+	} else if (wifi_connected &&
+		   (BT_8723D_1ANT_BT_STATUS_CONNECTED_IDLE ==
+		    coex_dm->bt_status)) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], Wifi connected + BT connected-idle!!\n");
+		BTC_TRACE(trace_buf);
+		common = true;
+	} else if (!wifi_connected &&
+		   (BT_8723D_1ANT_BT_STATUS_CONNECTED_IDLE !=
+		    coex_dm->bt_status)) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], Wifi non connected-idle + BT Busy!!\n");
+		BTC_TRACE(trace_buf);
+		common = true;
+	} else {
+		if (wifi_busy) {
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				"[BTCoex], Wifi Connected-Busy + BT Busy!!\n");
+			BTC_TRACE(trace_buf);
+		} else {
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				"[BTCoex], Wifi Connected-Idle + BT Busy!!\n");
+			BTC_TRACE(trace_buf);
+		}
+
+		common = false;
+	}
+
+	return common;
+}
+
+
+/* *********************************************
+ *
+ *	Non-Software Coex Mechanism start
+ *
+ * ********************************************* */
+void halbtc8723d1ant_action_bt_whql_test(IN struct btc_coexist *btcoexist)
+{
+	halbtc8723d1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 8);
+	halbtc8723d1ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, NORMAL_EXEC,
+				     BT_8723D_1ANT_PHASE_2G_RUNTIME);
+	halbtc8723d1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0);
+}
+
+void halbtc8723d1ant_action_bt_hs(IN struct btc_coexist *btcoexist)
+{
+	halbtc8723d1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 5);
+	halbtc8723d1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 2);
+}
+
+void halbtc8723d1ant_action_bt_relink(IN struct btc_coexist *btcoexist)
+{
+	halbtc8723d1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 5);
+	halbtc8723d1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 1);
+	coex_sta->bt_relink_downcount = 2;
+}
+
+void halbtc8723d1ant_action_bt_idle(IN struct btc_coexist *btcoexist)
+{
+	boolean wifi_busy = false;
+
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy);
+
+	if (!wifi_busy) {
+		halbtc8723d1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 6);
+		halbtc8723d1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 3);
+	} else {
+	/* if wl busy */
+	if (BT_8723D_1ANT_BT_STATUS_NON_CONNECTED_IDLE ==
+		coex_dm->bt_status) {
+		halbtc8723d1ant_coex_table_with_type(btcoexist,
+							     NORMAL_EXEC, 8);
+
+		halbtc8723d1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 33);
+	} else {
+		halbtc8723d1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 8);
+		halbtc8723d1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 32);
+	}
+}
+
+}
+
+void halbtc8723d1ant_action_bt_inquiry(IN struct btc_coexist *btcoexist)
+{
+	struct	btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
+	boolean wifi_connected = false, wifi_busy = false, bt_busy = false;
+	boolean wifi_scan = false, wifi_link = false, wifi_roam = false;
+
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED,
+			   &wifi_connected);
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy);
+	btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_TRAFFIC_BUSY, &bt_busy);
+
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_SCAN, &wifi_scan);
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_LINK, &wifi_link);
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_ROAM, &wifi_roam);
+
+
+	if ((coex_sta->bt_create_connection) && ((wifi_link) || (wifi_roam)
+		|| (wifi_scan) || (wifi_busy) || (coex_sta->wifi_is_high_pri_task))) {
+
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			"[BTCoex], Wifi link/roam/Scan/busy/hi-pri-task + BT Inq/Page!!\n");
+		BTC_TRACE(trace_buf);
+
+		halbtc8723d1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 1);
+
+		if ((bt_link_info->a2dp_exist) && (!bt_link_info->pan_exist))
+			halbtc8723d1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 17);
+		else
+			halbtc8723d1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 33);
+		} else if ((!wifi_connected) && (!wifi_scan)) {
+
+		halbtc8723d1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 8);
+
+		halbtc8723d1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0);
+	} else if (bt_link_info->pan_exist) {
+
+		halbtc8723d1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 22);
+
+		halbtc8723d1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4);
+
+	} else if (bt_link_info->a2dp_exist) {
+
+		halbtc8723d1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 16);
+
+		halbtc8723d1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4);
+	} else {
+
+		if ((wifi_link) || (wifi_roam) || (wifi_scan) || (wifi_busy)
+			|| (coex_sta->wifi_is_high_pri_task))
+			halbtc8723d1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 21);
+		else
+			halbtc8723d1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 23);
+
+		halbtc8723d1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4);
+	}
+}
+
+
+void halbtc8723d1ant_action_bt_sco_hid_only_busy(IN struct btc_coexist
+		*btcoexist)
+{
+	struct  btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
+	boolean	wifi_connected = false, wifi_busy = false;
+	u32  wifi_bw = 1;
+
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED,
+			   &wifi_connected);
+
+	btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW,
+			   &wifi_bw);
+
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy);
+
+
+	if (bt_link_info->sco_exist) {
+			halbtc8723d1ant_ps_tdma(btcoexist, NORMAL_EXEC,
+						true, 5);
+			halbtc8723d1ant_coex_table_with_type(btcoexist,
+							     NORMAL_EXEC, 5);
+		} else if (coex_sta->hid_busy_num >= 2) {
+		 /*for 4/18 hid */
+		 /* if 11bg mode */
+		if (wifi_bw == 0) {
+
+		halbtc8723d1ant_coex_table_with_type(btcoexist,
+							     NORMAL_EXEC, 6);
+		halbtc8723d1ant_set_wltoggle_coex_table(btcoexist,
+								NORMAL_EXEC,
+								0x1, 0xaa,
+								0x5a, 0xaa,
+								0xaa);
+		halbtc8723d1ant_ps_tdma(btcoexist, NORMAL_EXEC, true,
+							11);
+		} else {
+
+		if (wifi_busy) {
+
+		     halbtc8723d1ant_coex_table_with_type(btcoexist,
+								NORMAL_EXEC, 6);
+		     halbtc8723d1ant_set_wltoggle_coex_table(btcoexist,
+								NORMAL_EXEC,
+								0x2, 0xaa,
+								0x5a, 0xaa,
+								0xaa);
+		     halbtc8723d1ant_ps_tdma(btcoexist, NORMAL_EXEC, true,
+							11);
+		  } else {
+
+		     halbtc8723d1ant_ps_tdma(btcoexist, NORMAL_EXEC,
+						true, 6);
+			 halbtc8723d1ant_coex_table_with_type(btcoexist,
+							     NORMAL_EXEC, 3);
+
+		  }
+		}
+	} else {
+			halbtc8723d1ant_ps_tdma(btcoexist, NORMAL_EXEC,
+						true, 6);
+			halbtc8723d1ant_coex_table_with_type(btcoexist,
+							     NORMAL_EXEC, 3);
+	}
+}
+
+
+void halbtc8723d1ant_action_wifi_only(IN struct btc_coexist *btcoexist)
+{
+	halbtc8723d1ant_ps_tdma(btcoexist, FORCE_EXEC, false, 8);
+	halbtc8723d1ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, FORCE_EXEC,
+				     BT_8723D_1ANT_PHASE_2G_RUNTIME);
+	/* halbtc8723d1ant_coex_table_with_type(btcoexist, FORCE_EXEC, 0); */
+	halbtc8723d1ant_coex_table_with_type(btcoexist, FORCE_EXEC, 10);
+}
+
+void halbtc8723d1ant_action_wifi_multi_port(IN struct btc_coexist *btcoexist)
+{
+	struct  btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
+
+	halbtc8723d1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 8);
+	halbtc8723d1ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, NORMAL_EXEC,
+				     BT_8723D_1ANT_PHASE_2G_RUNTIME);
+
+	if ((BT_8723D_1ANT_BT_STATUS_NON_CONNECTED_IDLE ==
+		coex_dm->bt_status) ||
+		(BT_8723D_1ANT_BT_STATUS_CONNECTED_IDLE ==
+		coex_dm->bt_status))
+		halbtc8723d1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 7);
+	else if (!bt_link_info->pan_exist)
+		halbtc8723d1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0);
+	else
+		halbtc8723d1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 2);
+}
+
+void halbtc8723d1ant_action_wifi_linkscan_process(IN struct btc_coexist
+		*btcoexist)
+{
+	struct  btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
+
+	if (bt_link_info->pan_exist) {
+
+		halbtc8723d1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 22);
+
+		halbtc8723d1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4);
+
+	} else if (bt_link_info->a2dp_exist) {
+
+		halbtc8723d1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 27);
+
+		halbtc8723d1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4);
+	} else {
+
+		halbtc8723d1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 21);
+
+		halbtc8723d1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4);
+	}
+}
+
+void halbtc8723d1ant_action_wifi_connected_bt_acl_busy(IN struct btc_coexist
+		*btcoexist)
+{
+	struct  btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
+	boolean			wifi_busy = false, wifi_turbo = false;
+	u32 wifi_bw = 1;
+
+	btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw);
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy);
+	btcoexist->btc_get(btcoexist, BTC_GET_U1_AP_NUM, &coex_sta->scan_ap_num);
+
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+		    "############# [BTCoex],  scan_ap_num = %d, wl_noisy_level = %d\n",
+		    coex_sta->scan_ap_num, coex_sta->wl_noisy_level);
+	BTC_TRACE(trace_buf);
+
+#if 1
+	if ((wifi_busy) && (coex_sta->wl_noisy_level == 0))
+		wifi_turbo = true;
+#endif
+
+	if ((coex_sta->bt_relink_downcount != 0)
+			&& (!bt_link_info->pan_exist) && (wifi_busy)) {
+
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			"############# [BTCoex],  BT Re-Link + A2DP + WL busy\n");
+		BTC_TRACE(trace_buf);
+
+		/*halbtc8821c1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 32);*/
+		halbtc8723d1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 8);
+		halbtc8723d1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0);
+
+	} else if (bt_link_info->a2dp_only) { /* A2DP		 */
+		if (!wifi_busy) {
+			/*halbtc8723d1ant_ps_tdma(btcoexist, NORMAL_EXEC, true,
+						32);*/
+			halbtc8723d1ant_ps_tdma(btcoexist, NORMAL_EXEC, true,
+						27);
+			halbtc8723d1ant_coex_table_with_type(btcoexist,
+							     NORMAL_EXEC, 4);
+		} else {
+
+			if (coex_sta->wl_noisy_level == 2)
+				halbtc8723d1ant_ps_tdma(btcoexist,
+							NORMAL_EXEC, true, 17);
+			else
+				halbtc8723d1ant_ps_tdma(btcoexist,
+							NORMAL_EXEC, true, 7);
+
+			if (wifi_turbo)
+				halbtc8723d1ant_coex_table_with_type(btcoexist,
+							     NORMAL_EXEC, 8);
+			else
+				halbtc8723d1ant_coex_table_with_type(btcoexist,
+							     NORMAL_EXEC, 4);
+		}
+	} else if (((bt_link_info->a2dp_exist) &&
+		    (bt_link_info->pan_exist)) ||
+		   (bt_link_info->hid_exist && bt_link_info->a2dp_exist &&
+		bt_link_info->pan_exist)) { /* A2DP+PAN(OPP,FTP), HID+A2DP+PAN(OPP,FTP) */
+
+		if ((bt_link_info->hid_exist) && (coex_sta->hid_busy_num >= 2)) {
+			halbtc8723d1ant_coex_table_with_type(btcoexist,
+							     NORMAL_EXEC, 6);
+			if (wifi_bw == 0) /* 11bg mode  */
+				halbtc8723d1ant_set_wltoggle_coex_table(btcoexist,
+								NORMAL_EXEC,
+								0x1, 0xaa,
+								0x5a, 0xaa,
+								0xaa);
+			else
+				halbtc8723d1ant_set_wltoggle_coex_table(btcoexist,
+								NORMAL_EXEC,
+								0x2, 0xaa,
+								0x5a, 0xaa,
+								0xaa);
+			halbtc8723d1ant_ps_tdma(btcoexist, NORMAL_EXEC, true,
+							12);
+		} else if (wifi_busy)	{
+			if (((coex_sta->a2dp_bit_pool > 40) &&
+			     (coex_sta->a2dp_bit_pool < 255)) ||
+			    (!coex_sta->is_A2DP_3M))
+				halbtc8723d1ant_ps_tdma(btcoexist, NORMAL_EXEC,
+							true, 15);
+			else if (wifi_turbo)
+				halbtc8723d1ant_ps_tdma(btcoexist, NORMAL_EXEC,
+							true, 18);
+			else
+				halbtc8723d1ant_ps_tdma(btcoexist, NORMAL_EXEC,
+							true, 13);
+		} else
+			halbtc8723d1ant_ps_tdma(btcoexist, NORMAL_EXEC, true,
+						14);
+
+		if (bt_link_info->hid_exist)
+			halbtc8723d1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 1);
+		else if (wifi_turbo)
+			halbtc8723d1ant_coex_table_with_type(btcoexist,
+							     NORMAL_EXEC, 8);
+		else
+			halbtc8723d1ant_coex_table_with_type(btcoexist,
+							     NORMAL_EXEC, 4);
+	} else if (bt_link_info->hid_exist &&
+		   bt_link_info->a2dp_exist) { /* HID+A2DP */
+
+			if ((wifi_busy) && (coex_sta->hid_busy_num >= 2)) { /*for 4/18 hid */
+				halbtc8723d1ant_coex_table_with_type(btcoexist,
+							     NORMAL_EXEC, 6);
+				if (wifi_bw == 0) /* 11bg mode  */
+					halbtc8723d1ant_set_wltoggle_coex_table(btcoexist,
+								NORMAL_EXEC,
+								0x1, 0xaa,
+								0x5a, 0xaa,
+								0xaa);
+				else
+					halbtc8723d1ant_set_wltoggle_coex_table(btcoexist,
+								NORMAL_EXEC,
+								0x2, 0xaa,
+								0x5a, 0xaa,
+								0xaa);
+				halbtc8723d1ant_ps_tdma(btcoexist, NORMAL_EXEC, true,
+							9);
+			} else {
+				halbtc8723d1ant_ps_tdma(btcoexist, NORMAL_EXEC, true,
+							8);
+				halbtc8723d1ant_coex_table_with_type(btcoexist,
+							     NORMAL_EXEC, 1);
+			}
+
+	} else if ((bt_link_info->pan_only)
+	   || (bt_link_info->hid_exist && bt_link_info->pan_exist)) {
+	   /* PAN(OPP,FTP), HID+PAN(OPP,FTP) */
+
+		if ((bt_link_info->hid_exist) && (bt_link_info->pan_exist) &&
+			(coex_sta->hid_busy_num >= 2)) {
+
+				halbtc8723d1ant_coex_table_with_type(btcoexist,
+							     NORMAL_EXEC, 6);
+				if (wifi_bw == 0) /* 11bg mode  */
+					halbtc8723d1ant_set_wltoggle_coex_table(btcoexist,
+								NORMAL_EXEC,
+								0x1, 0xaa,
+								0x5a, 0xaa,
+								0xaa);
+				else
+					halbtc8723d1ant_set_wltoggle_coex_table(btcoexist,
+								NORMAL_EXEC,
+								0x2, 0xaa,
+								0x5a, 0xaa,
+								0xaa);
+				halbtc8723d1ant_ps_tdma(btcoexist, NORMAL_EXEC, true,
+							12);
+		} else {
+			if (!wifi_busy)
+				halbtc8723d1ant_ps_tdma(btcoexist, NORMAL_EXEC, true,
+							4);
+			else
+				halbtc8723d1ant_ps_tdma(btcoexist, NORMAL_EXEC, true,
+							3);
+
+			if (bt_link_info->hid_exist)
+				halbtc8723d1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 1);
+			else if (wifi_turbo)
+				halbtc8723d1ant_coex_table_with_type(btcoexist,
+								     NORMAL_EXEC, 8);
+			else
+				halbtc8723d1ant_coex_table_with_type(btcoexist,
+								     NORMAL_EXEC, 4);
+		}
+	} else {
+		/* BT no-profile busy (0x9) */
+		halbtc8723d1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 33);
+		halbtc8723d1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4);
+	}
+}
+
+void halbtc8723d1ant_action_wifi_not_connected(IN struct btc_coexist *btcoexist)
+{
+	/* tdma and coex table */
+	halbtc8723d1ant_ps_tdma(btcoexist, FORCE_EXEC, false, 8);
+	halbtc8723d1ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, NORMAL_EXEC,
+				     BT_8723D_1ANT_PHASE_2G_RUNTIME);
+	halbtc8723d1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0);
+}
+
+
+void halbtc8723d1ant_action_wifi_connected(IN struct btc_coexist *btcoexist)
+{
+	struct	btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
+	boolean wifi_busy = false;
+
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			"[BTCoex], CoexForWifiConnect()===>\n");
+	BTC_TRACE(trace_buf);
+
+	halbtc8723d1ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO,
+					 NORMAL_EXEC,
+					 BT_8723D_1ANT_PHASE_2G_RUNTIME);
+
+	if (BT_8723D_1ANT_BT_STATUS_ACL_BUSY == coex_dm->bt_status) {
+
+		if (bt_link_info->hid_only)  /* HID only */
+		   halbtc8723d1ant_action_bt_sco_hid_only_busy(btcoexist);
+		else
+			halbtc8723d1ant_action_wifi_connected_bt_acl_busy(btcoexist);
+
+	} else if ((BT_8723D_1ANT_BT_STATUS_SCO_BUSY ==
+				coex_dm->bt_status) ||
+			   (BT_8723D_1ANT_BT_STATUS_ACL_SCO_BUSY ==
+				coex_dm->bt_status)) {
+			halbtc8723d1ant_action_bt_sco_hid_only_busy(btcoexist);
+	} else
+			halbtc8723d1ant_action_bt_idle(btcoexist);
+}
+
+
+void halbtc8723d1ant_run_sw_coexist_mechanism(IN struct btc_coexist *btcoexist)
+{
+	u8				algorithm = 0;
+
+	algorithm = halbtc8723d1ant_action_algorithm(btcoexist);
+	coex_dm->cur_algorithm = algorithm;
+
+	if (halbtc8723d1ant_is_common_action(btcoexist)) {
+
+	} else {
+		switch (coex_dm->cur_algorithm) {
+		case BT_8723D_1ANT_COEX_ALGO_SCO:
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				    "[BTCoex], Action algorithm = SCO.\n");
+			BTC_TRACE(trace_buf);
+			break;
+		case BT_8723D_1ANT_COEX_ALGO_HID:
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				    "[BTCoex], Action algorithm = HID.\n");
+			BTC_TRACE(trace_buf);
+			break;
+		case BT_8723D_1ANT_COEX_ALGO_A2DP:
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				    "[BTCoex], Action algorithm = A2DP.\n");
+			BTC_TRACE(trace_buf);
+			break;
+		case BT_8723D_1ANT_COEX_ALGO_A2DP_PANHS:
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				"[BTCoex], Action algorithm = A2DP+PAN(HS).\n");
+			BTC_TRACE(trace_buf);
+			break;
+		case BT_8723D_1ANT_COEX_ALGO_PANEDR:
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				    "[BTCoex], Action algorithm = PAN(EDR).\n");
+			BTC_TRACE(trace_buf);
+			break;
+		case BT_8723D_1ANT_COEX_ALGO_PANHS:
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				    "[BTCoex], Action algorithm = HS mode.\n");
+			BTC_TRACE(trace_buf);
+			break;
+		case BT_8723D_1ANT_COEX_ALGO_PANEDR_A2DP:
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				    "[BTCoex], Action algorithm = PAN+A2DP.\n");
+			BTC_TRACE(trace_buf);
+			break;
+		case BT_8723D_1ANT_COEX_ALGO_PANEDR_HID:
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				"[BTCoex], Action algorithm = PAN(EDR)+HID.\n");
+			BTC_TRACE(trace_buf);
+			break;
+		case BT_8723D_1ANT_COEX_ALGO_HID_A2DP_PANEDR:
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				"[BTCoex], Action algorithm = HID+A2DP+PAN.\n");
+			BTC_TRACE(trace_buf);
+			break;
+		case BT_8723D_1ANT_COEX_ALGO_HID_A2DP:
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				    "[BTCoex], Action algorithm = HID+A2DP.\n");
+			BTC_TRACE(trace_buf);
+			break;
+		default:
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				"[BTCoex], Action algorithm = coexist All Off!!\n");
+			BTC_TRACE(trace_buf);
+			break;
+		}
+		coex_dm->pre_algorithm = coex_dm->cur_algorithm;
+	}
+}
+
+
+void halbtc8723d1ant_run_coexist_mechanism(IN struct btc_coexist *btcoexist)
+{
+	struct	btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
+	boolean wifi_connected = false, bt_hs_on = false;
+	boolean increase_scan_dev_num = false;
+	boolean bt_ctrl_agg_buf_size = false;
+	boolean miracast_plus_bt = false, wifi_under_5g = false;
+	u8	agg_buf_size = 5;
+	u32 wifi_link_status = 0;
+	u32 num_of_wifi_link = 0, wifi_bw;
+	u8	iot_peer = BTC_IOT_PEER_UNKNOWN;
+	boolean scan = false, link = false, roam = false, under_4way = false;
+
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_SCAN, &scan);
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_LINK, &link);
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_ROAM, &roam);
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_4_WAY_PROGRESS,
+			   &under_4way);
+
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			"[BTCoex], RunCoexistMechanism()===>\n");
+	BTC_TRACE(trace_buf);
+
+	if (btcoexist->manual_control) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			"[BTCoex], RunCoexistMechanism(), return for Manual CTRL <===\n");
+		BTC_TRACE(trace_buf);
+		return;
+	}
+
+	if (btcoexist->stop_coex_dm) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			"[BTCoex], RunCoexistMechanism(), return for Stop Coex DM <===\n");
+		BTC_TRACE(trace_buf);
+		return;
+	}
+
+	if (coex_sta->under_ips) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				"[BTCoex], wifi is under IPS !!!\n");
+		BTC_TRACE(trace_buf);
+		return;
+	}
+
+	if (!coex_sta->run_time_state) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			"[BTCoex], return for run_time_state = false !!!\n");
+		BTC_TRACE(trace_buf);
+		return;
+	}
+
+	if (coex_sta->freeze_coexrun_by_btinfo) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			"[BTCoex], BtInfoNotify(), return for freeze_coexrun_by_btinfo\n");
+		BTC_TRACE(trace_buf);
+		return;
+	}
+
+	if (coex_sta->bt_whck_test) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				"[BTCoex], BT is under WHCK TEST!!!\n");
+		BTC_TRACE(trace_buf);
+		halbtc8723d1ant_action_bt_whql_test(btcoexist);
+		return;
+	}
+
+	if (coex_sta->bt_disabled) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				"[BTCoex], BT is disabled !!!\n");
+		halbtc8723d1ant_action_wifi_only(btcoexist);
+		return;
+	}
+
+	if (coex_sta->c2h_bt_inquiry_page) {
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+					"[BTCoex], BT is under inquiry/page scan !!\n");
+			BTC_TRACE(trace_buf);
+			halbtc8723d1ant_action_bt_inquiry(btcoexist);
+			return;
+	}
+
+	if (coex_sta->is_setupLink) {
+		 BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+		 "[BTCoex], BT is re-link !!!\n");
+		 halbtc8723d1ant_action_bt_relink(btcoexist);
+		 return;
+	}
+
+	if ((BT_8723D_1ANT_BT_STATUS_ACL_BUSY == coex_dm->bt_status) ||
+		(BT_8723D_1ANT_BT_STATUS_SCO_BUSY == coex_dm->bt_status) ||
+		(BT_8723D_1ANT_BT_STATUS_ACL_SCO_BUSY == coex_dm->bt_status))
+		increase_scan_dev_num = true;
+
+	btcoexist->btc_set(btcoexist, BTC_SET_BL_INC_SCAN_DEV_NUM,
+			   &increase_scan_dev_num);
+
+	btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_LINK_STATUS,
+			   &wifi_link_status);
+
+	num_of_wifi_link = wifi_link_status >> 16;
+
+	if ((num_of_wifi_link >= 2) ||
+		(wifi_link_status & WIFI_P2P_GO_CONNECTED)) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			"############# [BTCoex],  Multi-Port num_of_wifi_link = %d, wifi_link_status = 0x%x\n",
+				num_of_wifi_link, wifi_link_status);
+		BTC_TRACE(trace_buf);
+
+		if (bt_link_info->bt_link_exist)
+			miracast_plus_bt = true;
+		else
+			miracast_plus_bt = false;
+
+		btcoexist->btc_set(btcoexist, BTC_SET_BL_MIRACAST_PLUS_BT,
+				   &miracast_plus_bt);
+
+		halbtc8723d1ant_limited_rx(btcoexist, NORMAL_EXEC, false,
+					false, 0x5);
+
+		if (scan || link || roam || under_4way) {
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				"[BTCoex], scan = %d, link = %d, roam = %d 4way = %d!!!\n",
+				    scan, link, roam, under_4way);
+			BTC_TRACE(trace_buf);
+
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				"[BTCoex], wifi is under linkscan process + Multi-Port !!\n");
+			BTC_TRACE(trace_buf);
+
+			halbtc8723d1ant_action_wifi_linkscan_process(btcoexist);
+		} else
+
+			halbtc8723d1ant_action_wifi_multi_port(btcoexist);
+
+		return;
+	} else {
+
+	miracast_plus_bt = false;
+	btcoexist->btc_set(btcoexist, BTC_SET_BL_MIRACAST_PLUS_BT,
+				&miracast_plus_bt);
+	}
+
+	btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw);
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED,
+				&wifi_connected);
+
+	if ((bt_link_info->bt_link_exist) && (wifi_connected)) {
+
+		btcoexist->btc_get(btcoexist, BTC_GET_U1_IOT_PEER, &iot_peer);
+
+		if (BTC_IOT_PEER_CISCO == iot_peer) {
+
+			if (BTC_WIFI_BW_HT40 == wifi_bw)
+				halbtc8723d1ant_limited_rx(btcoexist,
+						NORMAL_EXEC, false, true, 0x10);
+			else
+				halbtc8723d1ant_limited_rx(btcoexist,
+						NORMAL_EXEC, false, true, 0x8);
+			}  else
+			halbtc8723d1ant_limited_rx(btcoexist, NORMAL_EXEC, false, false,
+					   0x5);
+	}
+
+	halbtc8723d1ant_run_sw_coexist_mechanism(
+			btcoexist);  /* just print debug message */
+
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on);
+
+	if (bt_hs_on) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				"############# [BTCoex],  BT Is hs\n");
+		BTC_TRACE(trace_buf);
+		halbtc8723d1ant_action_bt_hs(btcoexist);
+		return;
+	}
+
+	if ((BT_8723D_1ANT_BT_STATUS_NON_CONNECTED_IDLE ==
+		coex_dm->bt_status) ||
+		(BT_8723D_1ANT_BT_STATUS_CONNECTED_IDLE ==
+		coex_dm->bt_status)) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				"############# [BTCoex],  BT Is idle\n");
+		BTC_TRACE(trace_buf);
+		halbtc8723d1ant_action_bt_idle(btcoexist);
+		return;
+	}
+
+	if (scan || link || roam || under_4way) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+		   "[BTCoex], scan = %d, link = %d, roam = %d 4way = %d!!!\n",
+					scan, link, roam, under_4way);
+		BTC_TRACE(trace_buf);
+
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+		   "[BTCoex], wifi is under linkscan process!!\n");
+		BTC_TRACE(trace_buf);
+
+		halbtc8723d1ant_action_wifi_linkscan_process(btcoexist);
+	} else if (wifi_connected) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+		   "[BTCoex], wifi is under connected!!\n");
+		BTC_TRACE(trace_buf);
+
+		halbtc8723d1ant_action_wifi_connected(btcoexist);
+	} else {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+		   "[BTCoex], wifi is under not-connected!!\n");
+		BTC_TRACE(trace_buf);
+
+		halbtc8723d1ant_action_wifi_not_connected(btcoexist);
+	 }
+}
+
+
+void halbtc8723d1ant_init_coex_dm(IN struct btc_coexist *btcoexist)
+{
+	/* force to reset coex mechanism */
+	halbtc8723d1ant_low_penalty_ra(btcoexist, NORMAL_EXEC, false);
+
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+		    "[BTCoex], Coex Mechanism Init!!\n");
+	BTC_TRACE(trace_buf);
+
+	coex_sta->pop_event_cnt = 0;
+	coex_sta->cnt_RemoteNameReq = 0;
+	coex_sta->cnt_ReInit = 0;
+	coex_sta->cnt_setupLink = 0;
+	coex_sta->cnt_IgnWlanAct = 0;
+	coex_sta->cnt_Page = 0;
+	coex_sta->cnt_RoleSwitch = 0;
+
+	halbtc8723d1ant_query_bt_info(btcoexist);
+}
+
+void halbtc8723d1ant_init_hw_config(IN struct btc_coexist *btcoexist,
+				    IN boolean back_up, IN boolean wifi_only)
+{
+	u32			u32tmp1 = 0, u32tmp2 = 0;
+	u16			u16tmp1 = 0;
+	u8	u8tmp0 = 0, u8tmp1 = 0;
+	struct  btc_board_info *board_info = &btcoexist->board_info;
+	u8 i = 0;
+
+
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+		    "[BTCoex], 1Ant Init HW Config!!\n");
+	BTC_TRACE(trace_buf);
+
+#if BT_8723D_1ANT_COEX_DBG
+	u32tmp1 = halbtc8723d1ant_ltecoex_indirect_read_reg(btcoexist,
+			0x38);
+	u32tmp2 = halbtc8723d1ant_ltecoex_indirect_read_reg(btcoexist,
+			0x54);
+	u16tmp1 = btcoexist->btc_read_2byte(btcoexist, 0x948);
+	u8tmp1	= btcoexist->btc_read_1byte(btcoexist, 0x73);
+	u8tmp0 =  btcoexist->btc_read_1byte(btcoexist, 0x67);
+
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+		"[BTCoex], ********** 0x67 = 0x%x, 0x948 = 0x%x, 0x73 = 0x%x(Before init_hw_config)\n",
+		    u8tmp0, u16tmp1, u8tmp1);
+	BTC_TRACE(trace_buf);
+
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+		"[BTCoex], **********0x38= 0x%x, 0x54= 0x%x (Before init_hw_config)\n",
+		    u32tmp1, u32tmp2);
+	BTC_TRACE(trace_buf);
+#endif
+
+
+	coex_sta->bt_coex_supported_feature = 0;
+	coex_sta->bt_coex_supported_version = 0;
+	coex_sta->bt_ble_scan_type = 0;
+	coex_sta->bt_ble_scan_para[0] = 0;
+	coex_sta->bt_ble_scan_para[1] = 0;
+	coex_sta->bt_ble_scan_para[2] = 0;
+	coex_sta->bt_reg_vendor_ac = 0xffff;
+	coex_sta->bt_reg_vendor_ae = 0xffff;
+	coex_sta->isolation_btween_wb = BT_8723D_1ANT_DEFAULT_ISOLATION;
+	coex_sta->gnt_error_cnt = 0;
+	coex_sta->bt_relink_downcount = 0;
+
+	for (i = 0; i <= 9; i++)
+		coex_sta->bt_afh_map[i] = 0;
+
+	/* 0xf0[15:12] --> Chip Cut information */
+	coex_sta->cut_version = (btcoexist->btc_read_1byte(btcoexist,
+				 0xf1) & 0xf0) >> 4;
+
+	btcoexist->btc_write_1byte_bitmask(btcoexist, 0x550, 0x8,
+					   0x1);  /* enable TBTT nterrupt */
+
+	/* BT report packet sample rate	 */
+	btcoexist->btc_write_1byte(btcoexist, 0x790, 0x5);
+
+	/* Init 0x778 = 0x1 for 1-Ant */
+	btcoexist->btc_write_1byte(btcoexist, 0x778, 0x1);
+
+	/* Enable PTA (3-wire function form BT side) */
+	btcoexist->btc_write_1byte_bitmask(btcoexist, 0x40, 0x20, 0x1);
+	btcoexist->btc_write_1byte_bitmask(btcoexist, 0x41, 0x02, 0x1);
+
+	/* Enable PTA (tx/rx signal form WiFi side) */
+	btcoexist->btc_write_1byte_bitmask(btcoexist, 0x4c6, 0x10, 0x1);
+
+	halbtc8723d1ant_enable_gnt_to_gpio(btcoexist, true);
+
+#if 0
+	/* check if WL firmware download ok */
+	if (btcoexist->btc_read_1byte(btcoexist, 0x80) == 0xc6)
+		halbtc8723d1ant_post_state_to_bt(btcoexist,
+					 BT_8723D_1ANT_SCOREBOARD_ONOFF, true);
+#endif
+
+	/* PTA parameter */
+	halbtc8723d1ant_ps_tdma(btcoexist, FORCE_EXEC, false, 8);
+
+	halbtc8723d1ant_coex_table_with_type(btcoexist, FORCE_EXEC, 0);
+
+	psd_scan->ant_det_is_ant_det_available = true;
+
+	/* Antenna config */
+	if (wifi_only) {
+		coex_sta->concurrent_rx_mode_on = false;
+		halbtc8723d1ant_set_ant_path(btcoexist, BTC_ANT_PATH_WIFI,
+					     FORCE_EXEC,
+					     BT_8723D_1ANT_PHASE_WLANONLY_INIT);
+
+		btcoexist->stop_coex_dm = true;
+	} else {
+		/*Set BT polluted packet on for Tx rate adaptive not including Tx retry break by PTA, 0x45c[19] =1 */
+		btcoexist->btc_write_1byte_bitmask(btcoexist, 0x45e, 0x8, 0x1);
+
+		coex_sta->concurrent_rx_mode_on = true;
+		btcoexist->btc_write_1byte_bitmask(btcoexist, 0x953, 0x2, 0x1);
+		/* RF 0x1[0] = 0->Set GNT_WL_RF_Rx always = 1 for con-current Rx */
+		btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1, 0x1, 0x0);
+		halbtc8723d1ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO,
+					     FORCE_EXEC,
+					     BT_8723D_1ANT_PHASE_COEX_INIT);
+
+		btcoexist->stop_coex_dm = false;
+	}
+
+	if (board_info->btdm_ant_pos == BTC_ANTENNA_AT_MAIN_PORT) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			"[BTCoex], **********  Single Antenna, Antenna at Main Port: S1**********\n");
+		BTC_TRACE(trace_buf);
+	} else {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			"[BTCoex], **********  Single Antenna, Antenna at Aux Port: S0**********\n");
+		BTC_TRACE(trace_buf);
+	}
+
+}
+
+u32 halbtc8723d1ant_psd_log2base(IN struct btc_coexist *btcoexist, IN u32 val)
+{
+	u8	j;
+	u32	tmp, tmp2, val_integerd_b = 0, tindex, shiftcount = 0;
+	u32	result, val_fractiond_b = 0, table_fraction[21] = {0, 432, 332, 274, 232, 200,
+				   174, 151, 132, 115, 100, 86, 74, 62, 51, 42,
+							   32, 23, 15, 7, 0
+							      };
+
+	if (val == 0)
+		return 0;
+
+	tmp = val;
+
+	while (1) {
+		if (tmp == 1)
+			break;
+		else {
+			tmp = (tmp >> 1);
+			shiftcount++;
+		}
+	}
+
+
+	val_integerd_b = shiftcount + 1;
+
+	tmp2 = 1;
+	for (j = 1; j <= val_integerd_b; j++)
+		tmp2 = tmp2 * 2;
+
+	tmp = (val * 100) / tmp2;
+	tindex = tmp / 5;
+
+	if (tindex > 20)
+		tindex = 20;
+
+	val_fractiond_b = table_fraction[tindex];
+
+	result = val_integerd_b * 100 - val_fractiond_b;
+
+	return result;
+
+
+}
+
+void halbtc8723d1ant_psd_show_antenna_detect_result(IN struct btc_coexist
+		*btcoexist)
+{
+	u8		*cli_buf = btcoexist->cli_buf;
+	struct  btc_board_info	*board_info = &btcoexist->board_info;
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+		   "\r\n============[Antenna Detection info]  ============\n");
+	CL_PRINTF(cli_buf);
+
+	if (psd_scan->ant_det_result == 12) { /* Get Ant Det from BT  */
+
+		if (board_info->btdm_ant_num_by_ant_det == 1)
+			CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+				   "\r\n %-35s = %s (%d~%d)",
+				   "Ant Det Result", "1-Antenna",
+				   BT_8723D_1ANT_ANTDET_PSDTHRES_1ANT,
+				BT_8723D_1ANT_ANTDET_PSDTHRES_2ANT_GOODISOLATION);
+		else {
+
+			if (psd_scan->ant_det_psd_scan_peak_val >
+			    (BT_8723D_1ANT_ANTDET_PSDTHRES_2ANT_BADISOLATION)
+			    * 100)
+				CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+					   "\r\n %-35s = %s (>%d)",
+					"Ant Det Result", "2-Antenna (Bad-Isolation)",
+					BT_8723D_1ANT_ANTDET_PSDTHRES_2ANT_BADISOLATION);
+			else
+				CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+					   "\r\n %-35s = %s (%d~%d)",
+					"Ant Det Result", "2-Antenna (Good-Isolation)",
+					BT_8723D_1ANT_ANTDET_PSDTHRES_2ANT_GOODISOLATION,
+					BT_8723D_1ANT_ANTDET_PSDTHRES_2ANT_BADISOLATION);
+		}
+	} else if (psd_scan->ant_det_result == 1)
+		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s (>%d)",
+			   "Ant Det Result", "2-Antenna (Bad-Isolation)",
+			   BT_8723D_1ANT_ANTDET_PSDTHRES_2ANT_BADISOLATION);
+	else if (psd_scan->ant_det_result == 2)
+		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s (%d~%d)",
+			   "Ant Det Result", "2-Antenna (Good-Isolation)",
+			   BT_8723D_1ANT_ANTDET_PSDTHRES_2ANT_GOODISOLATION
+			   + psd_scan->ant_det_thres_offset,
+			   BT_8723D_1ANT_ANTDET_PSDTHRES_2ANT_BADISOLATION);
+	else
+		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s (%d~%d)",
+			   "Ant Det Result", "1-Antenna",
+			   BT_8723D_1ANT_ANTDET_PSDTHRES_1ANT,
+			   BT_8723D_1ANT_ANTDET_PSDTHRES_2ANT_GOODISOLATION
+			   + psd_scan->ant_det_thres_offset);
+
+	CL_PRINTF(cli_buf);
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s ",
+		   "Antenna Detection Finish",
+		   (board_info->btdm_ant_det_finish
+		    ? "Yes" : "No"));
+	CL_PRINTF(cli_buf);
+
+	switch (psd_scan->ant_det_result) {
+	case 0:
+		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+			   "(BT is not available)");
+		break;
+	case 1:  /* 2-Ant bad-isolation */
+		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+			   "(BT is available)");
+		break;
+	case 2:  /* 2-Ant good-isolation */
+		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+			   "(BT is available)");
+		break;
+	case 3:  /* 1-Ant */
+		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+			   "(BT is available)");
+		break;
+	case 4:
+		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+			   "(Uncertainty result)");
+		break;
+	case 5:
+		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "(Pre-Scan fai)");
+		break;
+	case 6:
+		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+			   "(WiFi is Scanning)");
+		break;
+	case 7:
+		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+			   "(BT is not idle)");
+		break;
+	case 8:
+		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+			   "(Abort by WiFi Scanning)");
+		break;
+	case 9:
+		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+			   "(Antenna Init is not ready)");
+		break;
+	case 10:
+		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+			   "(BT is Inquiry or page)");
+		break;
+	case 11:
+		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+			   "(BT is Disabled)");
+	case 12:
+		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+			   "(BT is available, result from BT");
+		break;
+	}
+	CL_PRINTF(cli_buf);
+
+	if (psd_scan->ant_det_result == 12) {
+		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d dB",
+			   "PSD Scan Peak Value",
+			   psd_scan->ant_det_psd_scan_peak_val / 100);
+		CL_PRINTF(cli_buf);
+		return;
+	}
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d",
+		   "Ant Detect Total Count", psd_scan->ant_det_try_count);
+	CL_PRINTF(cli_buf);
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d",
+		   "Ant Detect Fail Count", psd_scan->ant_det_fail_count);
+	CL_PRINTF(cli_buf);
+
+	if ((!board_info->btdm_ant_det_finish) &&
+	    (psd_scan->ant_det_result != 5))
+		return;
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s", "BT Response",
+		   (psd_scan->ant_det_result ? "ok" : "fail"));
+	CL_PRINTF(cli_buf);
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d ms", "BT Tx Time",
+		   psd_scan->ant_det_bt_tx_time);
+	CL_PRINTF(cli_buf);
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d", "BT Tx Ch",
+		   psd_scan->ant_det_bt_le_channel);
+	CL_PRINTF(cli_buf);
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d",
+		   "WiFi PSD Cent-Ch/Offset/Span",
+		   psd_scan->real_cent_freq, psd_scan->real_offset,
+		   psd_scan->real_span);
+	CL_PRINTF(cli_buf);
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d dB",
+		   "PSD Pre-Scan Peak Value",
+		   psd_scan->ant_det_pre_psdscan_peak_val / 100);
+	CL_PRINTF(cli_buf);
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s (<= %d)",
+		   "PSD Pre-Scan result",
+		   (psd_scan->ant_det_result != 5 ? "ok" : "fail"),
+		   BT_8723D_1ANT_ANTDET_PSDTHRES_BACKGROUND
+		   + psd_scan->ant_det_thres_offset);
+	CL_PRINTF(cli_buf);
+
+	if (psd_scan->ant_det_result == 5)
+		return;
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s dB",
+		   "PSD Scan Peak Value", psd_scan->ant_det_peak_val);
+	CL_PRINTF(cli_buf);
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s MHz",
+		   "PSD Scan Peak Freq", psd_scan->ant_det_peak_freq);
+	CL_PRINTF(cli_buf);
+
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s", "TFBGA Package",
+		   (board_info->tfbga_package) ?  "Yes" : "No");
+	CL_PRINTF(cli_buf);
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d",
+		   "PSD Threshold Offset", psd_scan->ant_det_thres_offset);
+	CL_PRINTF(cli_buf);
+
+}
+
+
+
+void halbtc8723d1ant_psd_showdata(IN struct btc_coexist *btcoexist)
+{
+	u8		*cli_buf = btcoexist->cli_buf;
+	u32		delta_freq_per_point;
+	u32		freq, freq1, freq2, n = 0, i = 0, j = 0, m = 0, psd_rep1, psd_rep2;
+
+	if (psd_scan->ant_det_result == 12)
+		return;
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+		   "\r\n\n============[PSD info]  (%d)============\n",
+		   psd_scan->psd_gen_count);
+	CL_PRINTF(cli_buf);
+
+	if (psd_scan->psd_gen_count == 0) {
+		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n No data !!\n");
+		CL_PRINTF(cli_buf);
+		return;
+	}
+
+	if (psd_scan->psd_point == 0)
+		delta_freq_per_point = 0;
+	else
+		delta_freq_per_point = psd_scan->psd_band_width /
+				       psd_scan->psd_point;
+
+	/* if (psd_scan->is_psd_show_max_only) */
+	if (0) {
+		psd_rep1 = psd_scan->psd_max_value / 100;
+		psd_rep2 = psd_scan->psd_max_value - psd_rep1 * 100;
+
+		freq = ((psd_scan->real_cent_freq - 20) * 1000000 +
+			psd_scan->psd_max_value_point * delta_freq_per_point);
+		freq1 = freq / 1000000;
+		freq2 = freq / 1000 - freq1 * 1000;
+
+		if (freq2 < 100)
+			CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+				   "\r\n Freq = %d.0%d MHz",
+				   freq1, freq2);
+		else
+			CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+				   "\r\n Freq = %d.%d MHz",
+				   freq1, freq2);
+
+		if (psd_rep2 < 10)
+			CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+				   ", Value = %d.0%d dB, (%d)\n",
+				   psd_rep1, psd_rep2, psd_scan->psd_max_value);
+		else
+			CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+				   ", Value = %d.%d dB, (%d)\n",
+				   psd_rep1, psd_rep2, psd_scan->psd_max_value);
+
+		CL_PRINTF(cli_buf);
+	} else {
+		m = psd_scan->psd_start_point;
+		n = psd_scan->psd_start_point;
+		i = 1;
+		j = 1;
+
+		while (1) {
+			do {
+				freq = ((psd_scan->real_cent_freq - 20) *
+					1000000 + m *
+					delta_freq_per_point);
+				freq1 = freq / 1000000;
+				freq2 = freq / 1000 - freq1 * 1000;
+
+				if (i == 1) {
+					if (freq2 == 0)
+						CL_SPRINTF(cli_buf,
+							   BT_TMP_BUF_SIZE,
+							   "\r\n Freq%6d.000",
+							   freq1);
+					else if (freq2 < 100)
+						CL_SPRINTF(cli_buf,
+							   BT_TMP_BUF_SIZE,
+							   "\r\n Freq%6d.0%2d",
+							   freq1,
+							   freq2);
+					else
+						CL_SPRINTF(cli_buf,
+							   BT_TMP_BUF_SIZE,
+							   "\r\n Freq%6d.%3d",
+							   freq1,
+							   freq2);
+				} else if ((i % 8 == 0) ||
+					   (m == psd_scan->psd_stop_point)) {
+					if (freq2 == 0)
+						CL_SPRINTF(cli_buf,
+							   BT_TMP_BUF_SIZE,
+							   "%6d.000\n", freq1);
+					else if (freq2 < 100)
+						CL_SPRINTF(cli_buf,
+							   BT_TMP_BUF_SIZE,
+							   "%6d.0%2d\n", freq1,
+							   freq2);
+					else
+						CL_SPRINTF(cli_buf,
+							   BT_TMP_BUF_SIZE,
+							   "%6d.%3d\n", freq1,
+							   freq2);
+				} else {
+					if (freq2 == 0)
+						CL_SPRINTF(cli_buf,
+							   BT_TMP_BUF_SIZE,
+							   "%6d.000", freq1);
+					else if (freq2 < 100)
+						CL_SPRINTF(cli_buf,
+							   BT_TMP_BUF_SIZE,
+							   "%6d.0%2d", freq1,
+							   freq2);
+					else
+						CL_SPRINTF(cli_buf,
+							   BT_TMP_BUF_SIZE,
+							   "%6d.%3d", freq1,
+							   freq2);
+				}
+
+				i++;
+				m++;
+				CL_PRINTF(cli_buf);
+
+			} while ((i <= 8) && (m <= psd_scan->psd_stop_point));
+
+
+			do {
+				psd_rep1 = psd_scan->psd_report_max_hold[n] /
+					   100;
+				psd_rep2 = psd_scan->psd_report_max_hold[n] -
+					   psd_rep1 *
+					   100;
+
+				if (j == 1) {
+					if (psd_rep2 < 10)
+						CL_SPRINTF(cli_buf,
+							   BT_TMP_BUF_SIZE,
+							   "\r\n Val %7d.0%d",
+							   psd_rep1,
+							   psd_rep2);
+					else
+						CL_SPRINTF(cli_buf,
+							   BT_TMP_BUF_SIZE,
+							   "\r\n Val %7d.%d",
+							   psd_rep1,
+							   psd_rep2);
+				} else if ((j % 8 == 0)  ||
+					   (n == psd_scan->psd_stop_point)) {
+					if (psd_rep2 < 10)
+						CL_SPRINTF(cli_buf,
+							   BT_TMP_BUF_SIZE,
+							"%7d.0%d\n", psd_rep1,
+							   psd_rep2);
+					else
+						CL_SPRINTF(cli_buf,
+							   BT_TMP_BUF_SIZE,
+							   "%7d.%d\n", psd_rep1,
+							   psd_rep2);
+				} else {
+					if (psd_rep2 < 10)
+						CL_SPRINTF(cli_buf,
+							   BT_TMP_BUF_SIZE,
+							   "%7d.0%d", psd_rep1,
+							   psd_rep2);
+					else
+						CL_SPRINTF(cli_buf,
+							   BT_TMP_BUF_SIZE,
+							   "%7d.%d", psd_rep1,
+							   psd_rep2);
+				}
+
+				j++;
+				n++;
+				CL_PRINTF(cli_buf);
+
+			} while ((j <= 8) && (n <= psd_scan->psd_stop_point));
+
+			if ((m > psd_scan->psd_stop_point) ||
+			    (n > psd_scan->psd_stop_point))
+				break;
+			else {
+				i = 1;
+				j = 1;
+			}
+
+		}
+	}
+
+
+}
+
+
+#ifdef PLATFORM_WINDOWS
+#pragma optimize("", off)
+#endif
+void halbtc8723d1ant_psd_maxholddata(IN struct btc_coexist *btcoexist,
+				     IN u32 gen_count)
+{
+	u32	i = 0;
+	u32 loop_i_max = 0, loop_val_max = 0;
+
+	if (gen_count == 1) {
+		memcpy(psd_scan->psd_report_max_hold,
+		       psd_scan->psd_report,
+		       BT_8723D_1ANT_ANTDET_PSD_POINTS * sizeof(u32));
+	}
+
+	for (i = psd_scan->psd_start_point;
+	     i <= psd_scan->psd_stop_point; i++) {
+
+		/* update max-hold value at each freq point */
+		if (psd_scan->psd_report[i] > psd_scan->psd_report_max_hold[i])
+			psd_scan->psd_report_max_hold[i] =
+				psd_scan->psd_report[i];
+
+		/*  search the max value in this seep */
+		if (psd_scan->psd_report[i] > loop_val_max) {
+			loop_val_max = psd_scan->psd_report[i];
+			loop_i_max = i;
+		}
+	}
+
+	if (gen_count <= BT_8723D_1ANT_ANTDET_PSD_SWWEEPCOUNT)
+		psd_scan->psd_loop_max_value[gen_count - 1] = loop_val_max;
+}
+
+#ifdef PLATFORM_WINDOWS
+#pragma optimize("", off)
+#endif
+u32 halbtc8723d1ant_psd_getdata(IN struct btc_coexist *btcoexist, IN u32 point)
+{
+	/* reg 0x808[9:0]: FFT data x */
+	/* reg 0x808[22]: 0-->1 to get 1 FFT data y */
+	/* reg 0x8b4[15:0]: FFT data y report */
+
+	u32 val = 0, psd_report = 0;
+	int k = 0;
+
+	val = btcoexist->btc_read_4byte(btcoexist, 0x808);
+
+	val &= 0xffbffc00;
+	val |= point;
+
+	btcoexist->btc_write_4byte(btcoexist, 0x808, val);
+
+	val |= 0x00400000;
+	btcoexist->btc_write_4byte(btcoexist, 0x808, val);
+
+	while (1) {
+		if (k++ > BT_8723D_1ANT_ANTDET_SWEEPPOINT_DELAY)
+			break;
+	}
+
+	val = btcoexist->btc_read_4byte(btcoexist, 0x8b4);
+
+	psd_report = val & 0x0000ffff;
+
+	return psd_report;
+}
+
+#ifdef PLATFORM_WINDOWS
+#pragma optimize("", off)
+#endif
+boolean halbtc8723d1ant_psd_sweep_point(IN struct btc_coexist *btcoexist,
+		IN u32 cent_freq, IN s32 offset, IN u32 span, IN u32 points,
+					IN u32 avgnum, IN u32 loopcnt)
+{
+	u32	 i = 0, val = 0, n = 0, k = 0, j, point_index = 0;
+	u32	points1 = 0, psd_report = 0;
+	u32	start_p = 0, stop_p = 0, delta_freq_per_point = 156250;
+	u32    psd_center_freq = 20 * 10 ^ 6;
+	boolean outloop = false, scan , roam, is_sweep_ok = true;
+	u8	 flag = 0;
+	u32	tmp = 0, u32tmp1 = 0;
+	u32	wifi_original_channel = 1;
+	u32 psd_sum = 0, avg_cnt = 0;
+	u32	i_max = 0, val_max = 0, val_max2 = 0;
+
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+		    "xxxxxxxxxxxxxxxx PSD Sweep Start!!\n");
+	BTC_TRACE(trace_buf);
+
+	do {
+		switch (flag) {
+		case 0:  /* Get PSD parameters */
+		default:
+
+			psd_scan->psd_band_width = 40 * 1000000;
+			psd_scan->psd_point = points;
+			psd_scan->psd_start_base = points / 2;
+			psd_scan->psd_avg_num = avgnum;
+			psd_scan->real_cent_freq = cent_freq;
+			psd_scan->real_offset = offset;
+			psd_scan->real_span = span;
+
+
+			points1 = psd_scan->psd_point;
+			delta_freq_per_point = psd_scan->psd_band_width /
+					       psd_scan->psd_point;
+
+			/* PSD point setup */
+			val = btcoexist->btc_read_4byte(btcoexist, 0x808);
+			val &= 0xffff0fff;
+
+			switch (psd_scan->psd_point) {
+			case 128:
+				val |= 0x0;
+				break;
+			case 256:
+			default:
+				val |= 0x00004000;
+				break;
+			case 512:
+				val |= 0x00008000;
+				break;
+			case 1024:
+				val |= 0x0000c000;
+				break;
+			}
+
+			switch (psd_scan->psd_avg_num) {
+			case 1:
+				val |= 0x0;
+				break;
+			case 8:
+				val |= 0x00001000;
+				break;
+			case 16:
+				val |= 0x00002000;
+				break;
+			case 32:
+			default:
+				val |= 0x00003000;
+				break;
+			}
+			btcoexist->btc_write_4byte(btcoexist, 0x808, val);
+
+			flag = 1;
+			break;
+		case 1:	  /* calculate the PSD point index from freq/offset/span */
+			psd_center_freq = psd_scan->psd_band_width / 2 +
+					  offset * (1000000);
+
+			start_p = psd_scan->psd_start_base + (psd_center_freq -
+				span * (1000000) / 2) / delta_freq_per_point;
+			psd_scan->psd_start_point = start_p -
+						    psd_scan->psd_start_base;
+
+			stop_p = psd_scan->psd_start_base + (psd_center_freq +
+				span * (1000000) / 2) / delta_freq_per_point;
+			psd_scan->psd_stop_point = stop_p -
+						   psd_scan->psd_start_base - 1;
+
+			flag = 2;
+			break;
+		case 2:  /* set RF channel/BW/Mode */
+
+			/* set 3-wire off */
+			val = btcoexist->btc_read_4byte(btcoexist, 0x88c);
+			val |= 0x00300000;
+			btcoexist->btc_write_4byte(btcoexist, 0x88c, val);
+
+			/* CCK off */
+			val = btcoexist->btc_read_4byte(btcoexist, 0x800);
+			val &= 0xfeffffff;
+			btcoexist->btc_write_4byte(btcoexist, 0x800, val);
+
+			/* Tx-pause on */
+			btcoexist->btc_write_1byte(btcoexist, 0x522, 0x6f);
+
+			/* store WiFi original channel */
+			wifi_original_channel = btcoexist->btc_get_rf_reg(
+					btcoexist, BTC_RF_A, 0x18, 0x3ff);
+
+			/* Set RF channel */
+			if (cent_freq == 2484)
+				btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A,
+							  0x18, 0x3ff, 0xe);
+			else
+				btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A,
+					  0x18, 0x3ff, (cent_freq - 2412) / 5 +
+						  1); /* WiFi TRx Mask on */
+
+			/* save original RCK value */
+			u32tmp1 =  btcoexist->btc_get_rf_reg(
+					   btcoexist, BTC_RF_A, 0x1d, 0xfffff);
+
+			/* Enter debug mode */
+			btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0xde,
+						  0x2, 0x1);
+
+			/* Set RF Rx filter corner */
+			btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1d,
+						  0xfffff, 0x2e);
+
+
+			/* Set  RF mode = Rx, RF Gain = 0x320a0 */
+			btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x0,
+						  0xfffff, 0x320a0);
+
+			while (1) {
+				if (k++ > BT_8723D_1ANT_ANTDET_SWEEPPOINT_DELAY)
+					break;
+			}
+			flag = 3;
+			break;
+		case 3:
+			psd_scan->psd_gen_count = 0;
+			for (j = 1; j <= loopcnt; j++) {
+
+				btcoexist->btc_get(btcoexist,
+						   BTC_GET_BL_WIFI_SCAN, &scan);
+				btcoexist->btc_get(btcoexist,
+						   BTC_GET_BL_WIFI_ROAM, &roam);
+
+				if (scan || roam) {
+					is_sweep_ok = false;
+					break;
+				}
+				memset(psd_scan->psd_report, 0,
+				       psd_scan->psd_point * sizeof(u32));
+				start_p = psd_scan->psd_start_point +
+					  psd_scan->psd_start_base;
+				stop_p = psd_scan->psd_stop_point +
+					 psd_scan->psd_start_base + 1;
+
+				i = start_p;
+				point_index = 0;
+
+				while (i < stop_p) {
+					if (i >= points1)
+						psd_report =
+							halbtc8723d1ant_psd_getdata(
+							btcoexist, i - points1);
+					else
+						psd_report =
+							halbtc8723d1ant_psd_getdata(
+								btcoexist, i);
+
+					if (psd_report == 0)
+						tmp = 0;
+					else
+						/* tmp =  20*log10((double)psd_report); */
+						/* 20*log2(x)/log2(10), log2Base return theresult of the psd_report*100 */
+						tmp = 6 * halbtc8723d1ant_psd_log2base(
+							btcoexist, psd_report);
+
+					n = i - psd_scan->psd_start_base;
+					psd_scan->psd_report[n] =  tmp;
+
+					BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+						"Point=%d, psd_dB_data = %d\n",
+						    i, psd_scan->psd_report[n]);
+					BTC_TRACE(trace_buf);
+
+					i++;
+
+				}
+
+				halbtc8723d1ant_psd_maxholddata(btcoexist, j);
+
+				psd_scan->psd_gen_count = j;
+
+				/*Accumulate Max PSD value in this loop if the value > threshold */
+				if (psd_scan->psd_loop_max_value[j - 1] >=
+				    4000) {
+					psd_sum = psd_sum +
+						psd_scan->psd_loop_max_value[j -
+								       1];
+					avg_cnt++;
+				}
+
+				BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+					    "Loop=%d, Max_dB_data = %d\n",
+					    j, psd_scan->psd_loop_max_value[j
+							    - 1]);
+				BTC_TRACE(trace_buf);
+
+			}
+
+			if (loopcnt == BT_8723D_1ANT_ANTDET_PSD_SWWEEPCOUNT) {
+
+				/* search the Max Value between each-freq-point-max-hold value of all sweep*/
+				for (i = 1;
+				     i <= BT_8723D_1ANT_ANTDET_PSD_SWWEEPCOUNT;
+				     i++) {
+
+					if (i == 1) {
+						i_max = i;
+						val_max = psd_scan->psd_loop_max_value[i
+								       - 1];
+						val_max2 =
+							psd_scan->psd_loop_max_value[i
+								     - 1];
+					} else if (
+						psd_scan->psd_loop_max_value[i -
+							     1] > val_max) {
+						val_max2 = val_max;
+						i_max = i;
+						val_max = psd_scan->psd_loop_max_value[i
+								       - 1];
+					} else if (
+						psd_scan->psd_loop_max_value[i -
+							     1] > val_max2)
+						val_max2 =
+							psd_scan->psd_loop_max_value[i
+								     - 1];
+
+					BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+						"i = %d, val_hold= %d, val_max = %d, val_max2 = %d\n",
+						i, psd_scan->psd_loop_max_value[i
+								    - 1],
+						    val_max, val_max2);
+
+					BTC_TRACE(trace_buf);
+				}
+
+				psd_scan->psd_max_value_point = i_max;
+				psd_scan->psd_max_value = val_max;
+				psd_scan->psd_max_value2 = val_max2;
+
+				BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+					    "val_max = %d, val_max2 = %d\n",
+					    psd_scan->psd_max_value,
+					    psd_scan->psd_max_value2);
+				BTC_TRACE(trace_buf);
+			}
+
+			if (avg_cnt != 0) {
+				psd_scan->psd_avg_value = (psd_sum / avg_cnt);
+				if ((psd_sum % avg_cnt) >= (avg_cnt / 2))
+					psd_scan->psd_avg_value++;
+			} else
+				psd_scan->psd_avg_value = 0;
+
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				    "AvgLoop=%d, Avg_dB_data = %d\n",
+				    avg_cnt, psd_scan->psd_avg_value);
+			BTC_TRACE(trace_buf);
+
+			flag = 100;
+			break;
+		case 99:	/* error */
+
+			outloop = true;
+			break;
+		case 100: /* recovery */
+
+			/* set 3-wire on */
+			val = btcoexist->btc_read_4byte(btcoexist, 0x88c);
+			val &= 0xffcfffff;
+			btcoexist->btc_write_4byte(btcoexist, 0x88c, val);
+
+			/* CCK on */
+			val = btcoexist->btc_read_4byte(btcoexist, 0x800);
+			val |= 0x01000000;
+			btcoexist->btc_write_4byte(btcoexist, 0x800, val);
+
+			/* Tx-pause off */
+			btcoexist->btc_write_1byte(btcoexist, 0x522, 0x0);
+
+			/* PSD off */
+			val = btcoexist->btc_read_4byte(btcoexist, 0x808);
+			val &= 0xffbfffff;
+			btcoexist->btc_write_4byte(btcoexist, 0x808, val);
+
+			/* restore RF Rx filter corner */
+			btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1d,
+						  0xfffff, u32tmp1);
+
+			/* Exit debug mode */
+			btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0xde,
+						  0x2, 0x0);
+
+			/* restore WiFi original channel */
+			btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x18,
+						  0x3ff, wifi_original_channel);
+
+			outloop = true;
+			break;
+
+		}
+
+	} while (!outloop);
+
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+		    "xxxxxxxxxxxxxxxx PSD Sweep Stop!!\n");
+	BTC_TRACE(trace_buf);
+	return is_sweep_ok;
+
+}
+
+#ifdef PLATFORM_WINDOWS
+#pragma optimize("", off)
+#endif
+boolean halbtc8723d1ant_psd_antenna_detection(IN struct btc_coexist
+		*btcoexist)
+{
+	u32	i = 0;
+	u32	wlpsd_cent_freq = 2484, wlpsd_span = 2;
+	s32	wlpsd_offset = -4;
+	u32 bt_tx_time, bt_le_channel;
+	u8	bt_le_ch[13] = {3, 6, 8, 11, 13, 16, 18, 21, 23, 26, 28, 31, 33};
+
+	u8	h2c_parameter[3] = {0}, u8tmpa, u8tmpb;
+
+	u8	state = 0;
+	boolean		outloop = false, bt_resp = false, ant_det_finish = false;
+	u32		freq, freq1, freq2, psd_rep1, psd_rep2, delta_freq_per_point,
+			u32tmp, u32tmp0, u32tmp1, u32tmp2 ;
+	struct  btc_board_info	*board_info = &btcoexist->board_info;
+
+	memset(psd_scan->ant_det_peak_val, 0, 16 * sizeof(u8));
+	memset(psd_scan->ant_det_peak_freq, 0, 16 * sizeof(u8));
+
+	psd_scan->ant_det_bt_tx_time =
+		BT_8723D_1ANT_ANTDET_BTTXTIME;	   /* 0.42ms*50 = 20ms (0.42ms = 1 PSD sweep) */
+	psd_scan->ant_det_bt_le_channel = BT_8723D_1ANT_ANTDET_BTTXCHANNEL;
+
+	bt_tx_time = psd_scan->ant_det_bt_tx_time;
+	bt_le_channel = psd_scan->ant_det_bt_le_channel;
+
+	if (board_info->tfbga_package) /* for TFBGA */
+		psd_scan->ant_det_thres_offset = 5;
+	else
+		psd_scan->ant_det_thres_offset = 0;
+
+	do {
+		switch (state) {
+		case 0:
+			if (bt_le_channel == 39)
+				wlpsd_cent_freq = 2484;
+			else {
+				for (i = 1; i <= 13; i++) {
+					if (bt_le_ch[i - 1] ==
+					    bt_le_channel) {
+						wlpsd_cent_freq = 2412
+								  + (i - 1) * 5;
+						break;
+					}
+				}
+
+				if (i == 14) {
+
+					BTC_SPRINTF(trace_buf,
+						    BT_TMP_BUF_SIZE,
+						"xxxxxxxxxxxxxxxx AntennaDetect(), Abort!!, Invalid LE channel = %d\n ",
+						    bt_le_channel);
+					BTC_TRACE(trace_buf);
+					outloop = true;
+					break;
+				}
+			}
+#if 0
+			wlpsd_sweep_count = bt_tx_time * 238 /
+					    100; /* bt_tx_time/0.42								 */
+			wlpsd_sweep_count = wlpsd_sweep_count / 5;
+
+			if (wlpsd_sweep_count % 5 != 0)
+				wlpsd_sweep_count = (wlpsd_sweep_count /
+						     5 + 1) * 5;
+#endif
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				"xxxxxxxxxxxxxxxx AntennaDetect(), BT_LETxTime=%d,  BT_LECh = %d\n",
+				    bt_tx_time, bt_le_channel);
+			BTC_TRACE(trace_buf);
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				"xxxxxxxxxxxxxxxx AntennaDetect(), wlpsd_cent_freq=%d,  wlpsd_offset = %d, wlpsd_span = %d, wlpsd_sweep_count = %d\n",
+				    wlpsd_cent_freq,
+				    wlpsd_offset,
+				    wlpsd_span,
+				    BT_8723D_1ANT_ANTDET_PSD_SWWEEPCOUNT);
+			BTC_TRACE(trace_buf);
+
+			state = 1;
+			break;
+		case 1: /* stop coex DM & set antenna path */
+			/* Stop Coex DM */
+			btcoexist->stop_coex_dm = true;
+
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				"xxxxxxxxxxxxxxxx AntennaDetect(), Stop Coex DM!!\n");
+			BTC_TRACE(trace_buf);
+
+			/* Set TDMA off,				 */
+			halbtc8723d1ant_ps_tdma(btcoexist, FORCE_EXEC,
+						false, 0);
+
+			/* Set coex table */
+			halbtc8723d1ant_coex_table_with_type(btcoexist,
+							     FORCE_EXEC, 0);
+
+			if (board_info->btdm_ant_pos ==
+			    BTC_ANTENNA_AT_MAIN_PORT) {
+				BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+					"xxxxxxxxxxxxxxxx AntennaDetect(), Antenna at Main Port\n");
+				BTC_TRACE(trace_buf);
+			} else {
+				BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+					"xxxxxxxxxxxxxxxx AntennaDetect(), Antenna at Aux Port\n");
+				BTC_TRACE(trace_buf);
+			}
+
+			/* Set Antenna path, switch WiFi to un-certain antenna port */
+			/* Set Antenna Path,  both GNT_WL/GNT_BT = 1, and control by SW */
+			halbtc8723d1ant_set_ant_path(btcoexist, BTC_ANT_PATH_BT,
+						     FORCE_EXEC,
+					     BT_8723D_1ANT_PHASE_ANTENNA_DET);
+
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				"xxxxxxxxxxxxxxxx AntennaDetect(), Set Antenna to BT!!\n");
+			BTC_TRACE(trace_buf);
+
+			/* Set AFH mask on at WiFi channel 2472MHz +/- 10MHz */
+			h2c_parameter[0] = 0x1;
+			h2c_parameter[1] = 0xd;
+			h2c_parameter[2] = 0x14;
+
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				"xxxxxxxxxxxxxxxx AntennaDetect(), Set AFH on, Cent-Ch= %d,  Mask=%d\n",
+				    h2c_parameter[1],
+				    h2c_parameter[2]);
+			BTC_TRACE(trace_buf);
+
+			btcoexist->btc_fill_h2c(btcoexist, 0x66, 3,
+						h2c_parameter);
+
+			u32tmp = btcoexist->btc_read_2byte(btcoexist, 0x948);
+			u32tmp0 = btcoexist->btc_read_4byte(btcoexist, 0x70);
+			u32tmp1 = halbtc8723d1ant_ltecoex_indirect_read_reg(
+					  btcoexist, 0x38);
+			u32tmp2 = halbtc8723d1ant_ltecoex_indirect_read_reg(
+					  btcoexist, 0x54);
+
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				"[BTCoex], ********** 0x948 = 0x%x, 0x70 = 0x%x, 0x38= 0x%x, 0x54= 0x%x (Before Ant Det)\n",
+				    u32tmp, u32tmp0, u32tmp1, u32tmp2);
+			BTC_TRACE(trace_buf);
+
+			state = 2;
+			break;
+		case 2:	/* Pre-sweep background psd */
+			if (!halbtc8723d1ant_psd_sweep_point(btcoexist,
+				     wlpsd_cent_freq, wlpsd_offset, wlpsd_span,
+					     BT_8723D_1ANT_ANTDET_PSD_POINTS,
+				     BT_8723D_1ANT_ANTDET_PSD_AVGNUM, 3)) {
+				ant_det_finish = false;
+				board_info->btdm_ant_num_by_ant_det = 1;
+				psd_scan->ant_det_result = 8;
+				state = 99;
+				break;
+			}
+
+			psd_scan->ant_det_pre_psdscan_peak_val =
+				psd_scan->psd_max_value;
+
+			if (psd_scan->ant_det_pre_psdscan_peak_val >
+			    (BT_8723D_1ANT_ANTDET_PSDTHRES_BACKGROUND
+			     + psd_scan->ant_det_thres_offset) * 100) {
+				BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+					"xxxxxxxxxxxxxxxx AntennaDetect(), Abort Antenna Detection!! becaus background = %d > thres (%d)\n",
+					psd_scan->ant_det_pre_psdscan_peak_val /
+					    100,
+					BT_8723D_1ANT_ANTDET_PSDTHRES_BACKGROUND
+					    + psd_scan->ant_det_thres_offset);
+				BTC_TRACE(trace_buf);
+				ant_det_finish = false;
+				board_info->btdm_ant_num_by_ant_det = 1;
+				psd_scan->ant_det_result = 5;
+				state = 99;
+			} else {
+				BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+					"xxxxxxxxxxxxxxxx AntennaDetect(), Start Antenna Detection!! becaus background = %d <= thres (%d)\n",
+					psd_scan->ant_det_pre_psdscan_peak_val /
+					    100,
+					BT_8723D_1ANT_ANTDET_PSDTHRES_BACKGROUND
+					    + psd_scan->ant_det_thres_offset);
+				BTC_TRACE(trace_buf);
+				state = 3;
+			}
+			break;
+		case 3:
+
+			bt_resp = btcoexist->btc_set_bt_ant_detection(
+					  btcoexist, (u8)(bt_tx_time & 0xff),
+					  (u8)(bt_le_channel & 0xff));
+
+			/* Sync WL Rx PSD with BT Tx time because H2C->Mailbox delay */
+			delay_ms(20);
+
+			if (!halbtc8723d1ant_psd_sweep_point(btcoexist,
+					     wlpsd_cent_freq, wlpsd_offset,
+							     wlpsd_span,
+					     BT_8723D_1ANT_ANTDET_PSD_POINTS,
+					     BT_8723D_1ANT_ANTDET_PSD_AVGNUM,
+				     BT_8723D_1ANT_ANTDET_PSD_SWWEEPCOUNT)) {
+				ant_det_finish = false;
+				board_info->btdm_ant_num_by_ant_det = 1;
+				psd_scan->ant_det_result = 8;
+				state = 99;
+				break;
+			}
+
+#if 1
+			psd_scan->ant_det_psd_scan_peak_val =
+				psd_scan->psd_max_value;
+#endif
+#if 0
+			psd_scan->ant_det_psd_scan_peak_val =
+				((psd_scan->psd_max_value - psd_scan->psd_avg_value) <
+				 800) ?
+				psd_scan->psd_max_value : ((
+						psd_scan->psd_max_value -
+					psd_scan->psd_max_value2 <= 300) ?
+						   psd_scan->psd_avg_value :
+						   psd_scan->psd_max_value2);
+#endif
+			psd_scan->ant_det_psd_scan_peak_freq =
+				psd_scan->psd_max_value_point;
+			state = 4;
+			break;
+		case 4:
+
+			if (psd_scan->psd_point == 0)
+				delta_freq_per_point = 0;
+			else
+				delta_freq_per_point =
+					psd_scan->psd_band_width /
+					psd_scan->psd_point;
+
+			psd_rep1 = psd_scan->ant_det_psd_scan_peak_val / 100;
+			psd_rep2 = psd_scan->ant_det_psd_scan_peak_val -
+				   psd_rep1 *
+				   100;
+
+			freq = ((psd_scan->real_cent_freq - 20) *
+				1000000 + psd_scan->psd_max_value_point
+				* delta_freq_per_point);
+			freq1 = freq / 1000000;
+			freq2 = freq / 1000 - freq1 * 1000;
+
+			if (freq2 < 100) {
+				BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+					"xxxxxxxxxxxxxxxx AntennaDetect(), Max Value: Freq = %d.0%d MHz",
+					    freq1, freq2);
+				BTC_TRACE(trace_buf);
+				CL_SPRINTF(psd_scan->ant_det_peak_freq,
+					   BT_8723D_1ANT_ANTDET_BUF_LEN,
+					   "%d.0%d", freq1, freq2);
+			} else {
+				BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+					"xxxxxxxxxxxxxxxx AntennaDetect(), Max Value: Freq = %d.%d MHz",
+					    freq1, freq2);
+				BTC_TRACE(trace_buf);
+				CL_SPRINTF(psd_scan->ant_det_peak_freq,
+					   BT_8723D_1ANT_ANTDET_BUF_LEN,
+					   "%d.%d", freq1, freq2);
+			}
+
+			if (psd_rep2 < 10) {
+				BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+					    ", Value = %d.0%d dB\n",
+					    psd_rep1, psd_rep2);
+				BTC_TRACE(trace_buf);
+				CL_SPRINTF(psd_scan->ant_det_peak_val,
+					   BT_8723D_1ANT_ANTDET_BUF_LEN,
+					   "%d.0%d", psd_rep1, psd_rep2);
+			} else {
+				BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+					    ", Value = %d.%d dB\n",
+					    psd_rep1, psd_rep2);
+				BTC_TRACE(trace_buf);
+				CL_SPRINTF(psd_scan->ant_det_peak_val,
+					   BT_8723D_1ANT_ANTDET_BUF_LEN,
+					   "%d.%d", psd_rep1, psd_rep2);
+			}
+
+			psd_scan->ant_det_is_btreply_available = true;
+
+			if (bt_resp == false) {
+				psd_scan->ant_det_is_btreply_available =
+					false;
+				psd_scan->ant_det_result = 0;
+				ant_det_finish = false;
+				board_info->btdm_ant_num_by_ant_det = 1;
+				BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+					"xxxxxxxxxxxxxxxx AntennaDetect(), BT Response = Fail\n ");
+				BTC_TRACE(trace_buf);
+			} else if (psd_scan->ant_det_psd_scan_peak_val >
+				(BT_8723D_1ANT_ANTDET_PSDTHRES_2ANT_BADISOLATION)
+				   * 100) {
+				psd_scan->ant_det_result = 1;
+				ant_det_finish = true;
+				board_info->btdm_ant_num_by_ant_det = 2;
+				coex_sta->isolation_btween_wb = (u8)(85 -
+					psd_scan->ant_det_psd_scan_peak_val /
+							     100) & 0xff;
+				BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+					"xxxxxxxxxxxxxxxx AntennaDetect(), Detect Result = 2-Ant, Bad-Isolation!!\n");
+				BTC_TRACE(trace_buf);
+			} else if (psd_scan->ant_det_psd_scan_peak_val >
+				(BT_8723D_1ANT_ANTDET_PSDTHRES_2ANT_GOODISOLATION
+				    + psd_scan->ant_det_thres_offset) * 100) {
+				psd_scan->ant_det_result = 2;
+				ant_det_finish = true;
+				board_info->btdm_ant_num_by_ant_det = 2;
+				coex_sta->isolation_btween_wb = (u8)(85 -
+					psd_scan->ant_det_psd_scan_peak_val /
+							     100) & 0xff;
+				BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+					"xxxxxxxxxxxxxxxx AntennaDetect(), Detect Result = 2-Ant, Good-Isolation!!\n");
+				BTC_TRACE(trace_buf);
+			} else if (psd_scan->ant_det_psd_scan_peak_val >
+				   (BT_8723D_1ANT_ANTDET_PSDTHRES_1ANT) *
+				   100) {
+				psd_scan->ant_det_result = 3;
+				ant_det_finish = true;
+				board_info->btdm_ant_num_by_ant_det = 1;
+				coex_sta->isolation_btween_wb = (u8)(85 -
+					psd_scan->ant_det_psd_scan_peak_val /
+							     100) & 0xff;
+				BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+					"xxxxxxxxxxxxxxxx AntennaDetect(), Detect Result = 1-Ant!!\n");
+				BTC_TRACE(trace_buf);
+			} else {
+				psd_scan->ant_det_result = 4;
+				ant_det_finish = false;
+				board_info->btdm_ant_num_by_ant_det = 1;
+				BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+					"xxxxxxxxxxxxxxxx AntennaDetect(), Detect Result = 1-Ant, un-certainity!!\n");
+				BTC_TRACE(trace_buf);
+			}
+
+			state = 99;
+			break;
+		case 99:  /* restore setup */
+
+			/* Set AFH mask off at WiFi channel 2472MHz +/- 10MHz */
+			h2c_parameter[0] = 0x0;
+			h2c_parameter[1] = 0x0;
+			h2c_parameter[2] = 0x0;
+
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				"xxxxxxxxxxxxxxxx AntennaDetect(), Set AFH on, Cent-Ch= %d,  Mask=%d\n",
+				    h2c_parameter[1], h2c_parameter[2]);
+			BTC_TRACE(trace_buf);
+
+			btcoexist->btc_fill_h2c(btcoexist, 0x66, 3,
+						h2c_parameter);
+
+			/* Set Antenna Path, GNT_WL/GNT_BT control by PTA */
+			/* Set Antenna path, switch WiFi to certain antenna port */
+			halbtc8723d1ant_set_ant_path(btcoexist,
+					     BTC_ANT_PATH_AUTO, FORCE_EXEC,
+					     BT_8723D_1ANT_PHASE_2G_RUNTIME);
+
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				"xxxxxxxxxxxxxxxx AntennaDetect(), Set Antenna to PTA\n!!");
+			BTC_TRACE(trace_buf);
+
+			btcoexist->stop_coex_dm = false;
+
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				"xxxxxxxxxxxxxxxx AntennaDetect(), Resume Coex DM\n!!");
+			BTC_TRACE(trace_buf);
+
+			outloop = true;
+			break;
+		}
+
+	} while (!outloop);
+
+	return ant_det_finish;
+
+}
+
+#ifdef PLATFORM_WINDOWS
+#pragma optimize("", off)
+#endif
+boolean halbtc8723d1ant_psd_antenna_detection_check(IN struct btc_coexist
+		*btcoexist)
+{
+	static u32 ant_det_count = 0, ant_det_fail_count = 0;
+	struct  btc_board_info	*board_info = &btcoexist->board_info;
+
+	boolean scan, roam, ant_det_finish = false;
+
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_SCAN, &scan);
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_ROAM, &roam);
+
+	ant_det_count++;
+
+	psd_scan->ant_det_try_count = ant_det_count;
+
+	if (scan || roam) {
+		ant_det_finish = false;
+		psd_scan->ant_det_result = 6;
+	} else if (coex_sta->bt_disabled) {
+		ant_det_finish = false;
+		psd_scan->ant_det_result = 11;
+	} else if (coex_sta->num_of_profile >= 1) {
+		ant_det_finish = false;
+		psd_scan->ant_det_result = 7;
+	} else if (
+		!psd_scan->ant_det_is_ant_det_available) { /* Antenna initial setup is not ready */
+		ant_det_finish = false;
+		psd_scan->ant_det_result = 9;
+	} else if (coex_sta->c2h_bt_inquiry_page) {
+		ant_det_finish = false;
+		psd_scan->ant_det_result = 10;
+	} else {
+
+		ant_det_finish = halbtc8723d1ant_psd_antenna_detection(
+					 btcoexist);
+
+		delay_ms(psd_scan->ant_det_bt_tx_time);
+	}
+
+	/* board_info->ant_det_result = psd_scan->ant_det_result; */
+
+	if (!ant_det_finish)
+		ant_det_fail_count++;
+
+	psd_scan->ant_det_fail_count = ant_det_fail_count;
+
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+		"xxxxxxxxxxxxxxxx AntennaDetect(), result = %d, fail_count = %d, finish = %s\n",
+		    psd_scan->ant_det_result,
+		    psd_scan->ant_det_fail_count,
+		    ant_det_finish == true ? "Yes" : "No");
+	BTC_TRACE(trace_buf);
+
+	return ant_det_finish;
+
+}
+
+
+
+/* ************************************************************
+ * work around function start with wa_halbtc8723d1ant_
+ * ************************************************************
+ * ************************************************************
+ * extern function start with ex_halbtc8723d1ant_
+ * ************************************************************ */
+void ex_halbtc8723d1ant_power_on_setting(IN struct btc_coexist *btcoexist)
+{
+	struct  btc_board_info	*board_info = &btcoexist->board_info;
+	u8 u8tmp = 0x0;
+	u16 u16tmp = 0x0;
+	u32	value = 0;
+
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+		"xxxxxxxxxxxxxxxx Execute 8723d 1-Ant PowerOn Setting xxxxxxxxxxxxxxxx!!\n");
+	BTC_TRACE(trace_buf);
+
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+		    "Ant Det Finish = %s, Ant Det Number  = %d\n",
+		    (board_info->btdm_ant_det_finish ? "Yes" : "No"),
+		    board_info->btdm_ant_num_by_ant_det);
+	BTC_TRACE(trace_buf);
+
+	btcoexist->stop_coex_dm = true;
+	psd_scan->ant_det_is_ant_det_available = false;
+
+	/* enable BB, REG_SYS_FUNC_EN such that we can write BB Register correctly. */
+	u16tmp = btcoexist->btc_read_2byte(btcoexist, 0x2);
+	btcoexist->btc_write_2byte(btcoexist, 0x2, u16tmp | BIT(0) | BIT(1));
+
+	/* Local setting bit define */
+	/*	BIT0: "0" for no antenna inverse; "1" for antenna inverse  */
+	/*	BIT1: "0" for internal switch; "1" for external switch */
+	/*	BIT2: "0" for one antenna; "1" for two antenna */
+	/* NOTE: here default all internal switch and 1-antenna ==> BIT1=0 and BIT2=0 */
+
+	/* Set Antenna Path to BT side */
+	/* Check efuse 0xc3[6] for Single Antenna Path */
+	if (board_info->single_ant_path == 0) {
+		/* set to S1 */
+		board_info->btdm_ant_pos = BTC_ANTENNA_AT_MAIN_PORT;
+		u8tmp = 0;
+		value = 1;
+	} else if (board_info->single_ant_path == 1) {
+		/* set to S0 */
+		board_info->btdm_ant_pos = BTC_ANTENNA_AT_AUX_PORT;
+		u8tmp = 1;
+		value = 0;
+	}
+
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+		"[BTCoex], ********** (Power On) single_ant_path  = %d, btdm_ant_pos = %d **********\n",
+		    board_info->single_ant_path , board_info->btdm_ant_pos);
+	BTC_TRACE(trace_buf);
+
+	/* Set Antenna Path to BT side */
+	halbtc8723d1ant_set_ant_path(btcoexist,
+				     BTC_ANT_PATH_AUTO,
+				     FORCE_EXEC,
+				     BT_8723D_1ANT_PHASE_COEX_POWERON);
+
+	/* Write Single Antenna Position to Registry to tell BT for 8723d. This line can be removed
+	since BT EFuse also add "single antenna position" in EFuse for 8723d*/
+	btcoexist->btc_set(btcoexist, BTC_SET_ACT_ANTPOSREGRISTRY_CTRL,
+			   &value);
+
+	/* Save"single antenna position" info in Local register setting for FW reading, because FW may not ready at  power on */
+	if (btcoexist->chip_interface == BTC_INTF_PCI)
+		btcoexist->btc_write_local_reg_1byte(btcoexist, 0x3e0, u8tmp);
+	else if (btcoexist->chip_interface == BTC_INTF_USB)
+		btcoexist->btc_write_local_reg_1byte(btcoexist, 0xfe08, u8tmp);
+	else if (btcoexist->chip_interface == BTC_INTF_SDIO)
+		btcoexist->btc_write_local_reg_1byte(btcoexist, 0x60, u8tmp);
+
+	/* enable GNT_WL/GNT_BT debug signal to GPIO14/15 */
+	halbtc8723d1ant_enable_gnt_to_gpio(btcoexist, true);
+
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+		"[BTCoex], **********  LTE coex Reg 0x38 (Power-On) = 0x%x**********\n",
+		    halbtc8723d1ant_ltecoex_indirect_read_reg(btcoexist, 0x38));
+	BTC_TRACE(trace_buf);
+
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+		"[BTCoex], **********  MAC Reg 0x70/ BB Reg 0x948 (Power-On) = 0x%x / 0x%x**********\n",
+		    btcoexist->btc_read_4byte(btcoexist, 0x70),
+		    btcoexist->btc_read_2byte(btcoexist, 0x948));
+	BTC_TRACE(trace_buf);
+
+}
+
+void ex_halbtc8723d1ant_pre_load_firmware(IN struct btc_coexist *btcoexist)
+{
+}
+
+void ex_halbtc8723d1ant_init_hw_config(IN struct btc_coexist *btcoexist,
+				       IN boolean wifi_only)
+{
+	halbtc8723d1ant_init_hw_config(btcoexist, true, wifi_only);
+}
+
+void ex_halbtc8723d1ant_init_coex_dm(IN struct btc_coexist *btcoexist)
+{
+	halbtc8723d1ant_init_coex_dm(btcoexist);
+}
+
+void ex_halbtc8723d1ant_display_coex_info(IN struct btc_coexist *btcoexist)
+{
+	struct  btc_board_info		*board_info = &btcoexist->board_info;
+	struct  btc_stack_info		*stack_info = &btcoexist->stack_info;
+	struct  btc_bt_link_info	*bt_link_info = &btcoexist->bt_link_info;
+	u8				*cli_buf = btcoexist->cli_buf;
+	u8				u8tmp[4], i, ps_tdma_case = 0;
+	u16				u16tmp[4];
+	u32				u32tmp[4];
+	u32				fa_ofdm, fa_cck, cca_ofdm, cca_cck;
+	u32				fw_ver = 0, bt_patch_ver = 0, bt_coex_ver = 0;
+	static u8			pop_report_in_10s = 0, cnt = 0;
+	u32			phyver = 0;
+	boolean			lte_coex_on = false;
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+		   "\r\n ============[BT Coexist info]============");
+	CL_PRINTF(cli_buf);
+
+	if (btcoexist->manual_control) {
+		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+			"\r\n ============[Under Manual Control]============");
+		CL_PRINTF(cli_buf);
+		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+			   "\r\n ==========================================");
+		CL_PRINTF(cli_buf);
+	}
+	if (btcoexist->stop_coex_dm) {
+		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+			   "\r\n ============[Coex is STOPPED]============");
+		CL_PRINTF(cli_buf);
+		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+			   "\r\n ==========================================");
+		CL_PRINTF(cli_buf);
+	}
+
+	if (!coex_sta->bt_disabled) {
+		if (coex_sta->bt_coex_supported_feature == 0)
+			btcoexist->btc_get(btcoexist, BTC_GET_U4_SUPPORTED_FEATURE,
+						&coex_sta->bt_coex_supported_feature);
+
+		if ((coex_sta->bt_coex_supported_version == 0) ||
+			 (coex_sta->bt_coex_supported_version == 0xffff))
+			btcoexist->btc_get(btcoexist, BTC_GET_U4_SUPPORTED_VERSION,
+						&coex_sta->bt_coex_supported_version);
+
+		if (coex_sta->bt_reg_vendor_ac == 0xffff)
+			coex_sta->bt_reg_vendor_ac = (u16)(
+						btcoexist->btc_get_bt_reg(btcoexist, 3,
+						0xac) & 0xffff);
+
+		if (coex_sta->bt_reg_vendor_ae == 0xffff)
+			coex_sta->bt_reg_vendor_ae = (u16)(
+						btcoexist->btc_get_bt_reg(btcoexist, 3,
+						0xae) & 0xffff);
+
+		btcoexist->btc_get(btcoexist, BTC_GET_U4_BT_PATCH_VER,
+						&bt_patch_ver);
+		btcoexist->bt_info.bt_get_fw_ver = bt_patch_ver;
+
+		if (coex_sta->num_of_profile > 0) {
+			cnt++;
+
+			if (cnt >= 3) {
+				btcoexist->btc_get_bt_afh_map_from_bt(btcoexist, 0,
+					&coex_sta->bt_afh_map[0]);
+				cnt = 0;
+			}
+		}
+	}
+
+	if (psd_scan->ant_det_try_count == 0) {
+		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %s",
+			   "Ant PG Num/ Mech/ Pos",
+			   board_info->pg_ant_num, board_info->btdm_ant_num,
+			   (board_info->btdm_ant_pos == 1 ? "S1" : "S0"));
+		CL_PRINTF(cli_buf);
+	} else {
+		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+			   "\r\n %-35s = %d/ %d/ %s  (%d/%d/%d)",
+			   "Ant PG Num/ Mech(Ant_Det)/ Pos",
+			   board_info->pg_ant_num,
+			   board_info->btdm_ant_num_by_ant_det,
+			   (board_info->btdm_ant_pos == 1 ? "S1" : "S0"),
+			   psd_scan->ant_det_try_count,
+			   psd_scan->ant_det_fail_count,
+			   psd_scan->ant_det_result);
+		CL_PRINTF(cli_buf);
+
+		if (board_info->btdm_ant_det_finish) {
+
+			if (psd_scan->ant_det_result != 12)
+				CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+					   "\r\n %-35s = %s",
+					   "Ant Det PSD Value",
+					   psd_scan->ant_det_peak_val);
+			else
+				CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+					   "\r\n %-35s = %d",
+					   "Ant Det PSD Value",
+					   psd_scan->ant_det_psd_scan_peak_val
+					   / 100);
+			CL_PRINTF(cli_buf);
+		}
+	}
+
+	if (board_info->ant_det_result_five_complete) {
+		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+			   "\r\n %-35s = %d/ %d",
+			   "AntDet(Registry) Num/PSD Value",
+			   board_info->btdm_ant_num_by_ant_det,
+			   (board_info->antdetval & 0x7f));
+		CL_PRINTF(cli_buf);
+	}
+
+	bt_patch_ver = btcoexist->bt_info.bt_get_fw_ver;
+	btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_FW_VER, &fw_ver);
+	phyver = btcoexist->btc_get_bt_phydm_version(btcoexist);
+
+	bt_coex_ver = ((coex_sta->bt_coex_supported_version & 0xff00) >> 8);
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+				"\r\n %-35s = %d_%02x/ 0x%02x/ 0x%02x (%s)",
+				"CoexVer WL/  BT_Desired/ BT_Report",
+				glcoex_ver_date_8723d_1ant, glcoex_ver_8723d_1ant,
+				glcoex_ver_btdesired_8723d_1ant,
+				bt_coex_ver,
+				(bt_coex_ver == 0xff ? "Unknown" :
+				(coex_sta->bt_disabled ? "BT-disable" :
+				(bt_coex_ver >= glcoex_ver_btdesired_8723d_1ant ?
+				"Match" : "Mis-Match"))));
+	CL_PRINTF(cli_buf);
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+		   "\r\n %-35s = 0x%x/ 0x%x/ v%d/ %c",
+		   "W_FW/ B_FW/ Phy/ Kt",
+		   fw_ver, bt_patch_ver, phyver,
+		   coex_sta->cut_version + 65);
+	CL_PRINTF(cli_buf);
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %02x %02x %02x ",
+		   "Wifi channel informed to BT",
+		   coex_dm->wifi_chnl_info[0], coex_dm->wifi_chnl_info[1],
+		   coex_dm->wifi_chnl_info[2]);
+	CL_PRINTF(cli_buf);
+
+	/* wifi status */
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s",
+		   "============[Wifi Status]============");
+	CL_PRINTF(cli_buf);
+	btcoexist->btc_disp_dbg_msg(btcoexist, BTC_DBG_DISP_WIFI_STATUS);
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s",
+		   "============[BT Status]============");
+	CL_PRINTF(cli_buf);
+
+	pop_report_in_10s++;
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+		   "\r\n %-35s = [%s/ %d dBm/ %d/ %d] ",
+		   "BT [status/ rssi/ retryCnt/ popCnt]",
+		   ((coex_sta->bt_disabled) ? ("disabled") :	((
+			   coex_sta->c2h_bt_inquiry_page) ? ("inquiry/page")
+			   : ((BT_8723D_1ANT_BT_STATUS_NON_CONNECTED_IDLE ==
+			       coex_dm->bt_status) ? "non-connected idle" :
+		((BT_8723D_1ANT_BT_STATUS_CONNECTED_IDLE == coex_dm->bt_status)
+				       ? "connected-idle" : "busy")))),
+		   coex_sta->bt_rssi - 100, coex_sta->bt_retry_cnt,
+		   coex_sta->pop_event_cnt);
+	CL_PRINTF(cli_buf);
+
+	if (pop_report_in_10s >= 5) {
+		coex_sta->pop_event_cnt = 0;
+		pop_report_in_10s = 0;
+	}
+
+	if (coex_sta->num_of_profile != 0)
+		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+			   "\r\n %-35s = %s%s%s%s%s",
+			   "Profiles",
+			   ((bt_link_info->a2dp_exist) ? "A2DP," : ""),
+			   ((bt_link_info->sco_exist) ?  "SCO," : ""),
+			   ((bt_link_info->hid_exist) ?
+			    ((coex_sta->hid_busy_num >= 2) ? "HID(4/18)," :
+			     "HID(2/18),") : ""),
+			   ((bt_link_info->pan_exist) ?  "PAN," : ""),
+			   ((coex_sta->voice_over_HOGP) ? "Voice" : ""));
+	else
+		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+			   "\r\n %-35s = None",
+			   "Profiles");
+
+	CL_PRINTF(cli_buf);
+
+	if (bt_link_info->a2dp_exist) {
+		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s/ %d/ %s",
+			   "A2DP Rate/Bitpool/Auto_Slot",
+			   ((coex_sta->is_A2DP_3M) ? "3M" : "No_3M"),
+			   coex_sta->a2dp_bit_pool,
+			   ((coex_sta->is_autoslot) ? "On" : "Off")
+			  );
+		CL_PRINTF(cli_buf);
+	}
+
+	if (bt_link_info->hid_exist) {
+		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d",
+			   "HID PairNum/Forbid_Slot",
+			   coex_sta->hid_pair_cnt,
+			   coex_sta->forbidden_slot
+			  );
+		CL_PRINTF(cli_buf);
+	}
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s/ %d/ %s/ 0x%x",
+				"Role/RoleSwCnt/IgnWlact/Feature",
+				((bt_link_info->slave_role) ? "Slave" : "Master"),
+				coex_sta->cnt_RoleSwitch,
+				((coex_dm->cur_ignore_wlan_act) ? "Yes" : "No"),
+				coex_sta->bt_coex_supported_feature);
+	CL_PRINTF(cli_buf);
+
+	if ((coex_sta->bt_ble_scan_type & 0x7) != 0x0) {
+			CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+				"\r\n %-35s = 0x%x/ 0x%x/ 0x%x/ 0x%x",
+				"BLEScan Type/TV/Init/Ble",
+				coex_sta->bt_ble_scan_type,
+				(coex_sta->bt_ble_scan_type & 0x1 ?
+				coex_sta->bt_ble_scan_para[0] : 0x0),
+				(coex_sta->bt_ble_scan_type & 0x2 ?
+				coex_sta->bt_ble_scan_para[1] : 0x0),
+				(coex_sta->bt_ble_scan_type & 0x4 ?
+				coex_sta->bt_ble_scan_para[2] : 0x0));
+			CL_PRINTF(cli_buf);
+	}
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d/ %d/ %d",
+		   "ReInit/ReLink/IgnWlact/Page/NameReq",
+		   coex_sta->cnt_ReInit,
+		   coex_sta->cnt_setupLink,
+		   coex_sta->cnt_IgnWlanAct,
+		   coex_sta->cnt_Page,
+		   coex_sta->cnt_RemoteNameReq
+		  );
+	CL_PRINTF(cli_buf);
+
+	halbtc8723d1ant_read_score_board(btcoexist,	&u16tmp[0]);
+
+	if ((coex_sta->bt_reg_vendor_ae == 0xffff) ||
+	    (coex_sta->bt_reg_vendor_ac == 0xffff))
+		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = x/ x/ %04x",
+			   "0xae[4]/0xac[1:0]/Scoreboard", u16tmp[0]);
+	else
+		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+			   "\r\n %-35s = 0x%x/ 0x%x/ %04x",
+			   "0xae[4]/0xac[1:0]/Scoreboard",
+			   ((coex_sta->bt_reg_vendor_ae & BIT(4)) >> 4),
+			   coex_sta->bt_reg_vendor_ac & 0x3, u16tmp[0]);
+	CL_PRINTF(cli_buf);
+
+	if (coex_sta->num_of_profile > 0) {
+
+		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+			"\r\n %-35s = %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x",
+			"AFH MAP",
+			coex_sta->bt_afh_map[0],
+			coex_sta->bt_afh_map[1],
+			coex_sta->bt_afh_map[2],
+			coex_sta->bt_afh_map[3],
+			coex_sta->bt_afh_map[4],
+			coex_sta->bt_afh_map[5],
+			coex_sta->bt_afh_map[6],
+			coex_sta->bt_afh_map[7],
+			coex_sta->bt_afh_map[8],
+			coex_sta->bt_afh_map[9]
+			   );
+		CL_PRINTF(cli_buf);
+	}
+
+	for (i = 0; i < BT_INFO_SRC_8723D_1ANT_MAX; i++) {
+		if (coex_sta->bt_info_c2h_cnt[i]) {
+			CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+				"\r\n %-35s = %02x %02x %02x %02x %02x %02x %02x (%d)",
+				   glbt_info_src_8723d_1ant[i],
+				   coex_sta->bt_info_c2h[i][0],
+				   coex_sta->bt_info_c2h[i][1],
+				   coex_sta->bt_info_c2h[i][2],
+				   coex_sta->bt_info_c2h[i][3],
+				   coex_sta->bt_info_c2h[i][4],
+				   coex_sta->bt_info_c2h[i][5],
+				   coex_sta->bt_info_c2h[i][6],
+				   coex_sta->bt_info_c2h_cnt[i]);
+			CL_PRINTF(cli_buf);
+		}
+	}
+
+
+	if (btcoexist->manual_control)
+		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s",
+			"============[mechanisms] (before Manual)============");
+	else
+		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s",
+			   "============[Mechanisms]============");
+
+	CL_PRINTF(cli_buf);
+
+	ps_tdma_case = coex_dm->cur_ps_tdma;
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+		   "\r\n %-35s = %02x %02x %02x %02x %02x (case-%d, %s)",
+		   "TDMA",
+		   coex_dm->ps_tdma_para[0], coex_dm->ps_tdma_para[1],
+		   coex_dm->ps_tdma_para[2], coex_dm->ps_tdma_para[3],
+		   coex_dm->ps_tdma_para[4], ps_tdma_case,
+		   (coex_dm->cur_ps_tdma_on ? "TDMA On" : "TDMA Off"));
+
+	CL_PRINTF(cli_buf);
+
+	u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x6c0);
+	u32tmp[1] = btcoexist->btc_read_4byte(btcoexist, 0x6c4);
+	u32tmp[2] = btcoexist->btc_read_4byte(btcoexist, 0x6c8);
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+		   "\r\n %-35s = %d/ 0x%x/ 0x%x/ 0x%x",
+		   "Table/0x6c0/0x6c4/0x6c8",
+		   coex_sta->coex_table_type, u32tmp[0], u32tmp[1], u32tmp[2]);
+	CL_PRINTF(cli_buf);
+
+	u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x778);
+	u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x6cc);
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+		   "\r\n %-35s = 0x%x/ 0x%x",
+		   "0x778/0x6cc",
+		   u8tmp[0], u32tmp[0]);
+	CL_PRINTF(cli_buf);
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s/ %s",
+		   "AntDiv/ ForceLPS",
+		   ((board_info->ant_div_cfg) ? "On" : "Off"),
+		   ((coex_sta->force_lps_on) ? "On" : "Off"));
+	CL_PRINTF(cli_buf);
+
+	u32tmp[0] = halbtc8723d1ant_ltecoex_indirect_read_reg(btcoexist, 0x38);
+	lte_coex_on = ((u32tmp[0] & BIT(7)) >> 7) ?  true : false;
+
+	if (lte_coex_on) {
+
+		u32tmp[0] = halbtc8723d1ant_ltecoex_indirect_read_reg(btcoexist,
+				0xa0);
+		u32tmp[1] = halbtc8723d1ant_ltecoex_indirect_read_reg(btcoexist,
+				0xa4);
+
+		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x",
+			   "LTE Coex  Table W_L/B_L",
+			   u32tmp[0] & 0xffff, u32tmp[1] & 0xffff);
+		CL_PRINTF(cli_buf);
+
+		u32tmp[0] = halbtc8723d1ant_ltecoex_indirect_read_reg(btcoexist,
+				0xa8);
+		u32tmp[1] = halbtc8723d1ant_ltecoex_indirect_read_reg(btcoexist,
+				0xac);
+		u32tmp[2] = halbtc8723d1ant_ltecoex_indirect_read_reg(btcoexist,
+				0xb0);
+		u32tmp[3] = halbtc8723d1ant_ltecoex_indirect_read_reg(btcoexist,
+				0xb4);
+
+		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+			   "\r\n %-35s = 0x%x/ 0x%x/ 0x%x/ 0x%x",
+			   "LTE Break Table W_L/B_L/L_W/L_B",
+			   u32tmp[0] & 0xffff, u32tmp[1] & 0xffff,
+			   u32tmp[2] & 0xffff, u32tmp[3] & 0xffff);
+		CL_PRINTF(cli_buf);
+
+	}
+
+	/* Hw setting		 */
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s",
+		   "============[Hw setting]============");
+	CL_PRINTF(cli_buf);
+	/*
+		u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x430);
+		u32tmp[1] = btcoexist->btc_read_4byte(btcoexist, 0x434);
+		u16tmp[0] = btcoexist->btc_read_2byte(btcoexist, 0x42a);
+		u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x456);
+		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/0x%x/0x%x/0x%x",
+			   "0x430/0x434/0x42a/0x456",
+			   u32tmp[0], u32tmp[1], u16tmp[0], u8tmp[0]);
+		CL_PRINTF(cli_buf);
+	*/
+
+	u32tmp[0] = halbtc8723d1ant_ltecoex_indirect_read_reg(btcoexist, 0x38);
+	u32tmp[1] = halbtc8723d1ant_ltecoex_indirect_read_reg(btcoexist, 0x54);
+	u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x73);
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s/ %s",
+		   "LTE Coex/Path Owner",
+		   ((lte_coex_on) ? "On" : "Off") ,
+		   ((u8tmp[0] & BIT(2)) ? "WL" : "BT"));
+	CL_PRINTF(cli_buf);
+
+	if (lte_coex_on) {
+		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+			   "\r\n %-35s = %d/ %d/ %d/ %d",
+			   "LTE 3Wire/OPMode/UART/UARTMode",
+			   (int)((u32tmp[0] & BIT(6)) >> 6),
+			   (int)((u32tmp[0] & (BIT(5) | BIT(4))) >> 4),
+			   (int)((u32tmp[0] & BIT(3)) >> 3),
+			   (int)(u32tmp[0] & (BIT(2) | BIT(1) | BIT(0))));
+		CL_PRINTF(cli_buf);
+
+		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d",
+			   "LTE_Busy/UART_Busy",
+			(int)((u32tmp[1] & BIT(1)) >> 1), (int)(u32tmp[1] & BIT(0)));
+		CL_PRINTF(cli_buf);
+	}
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+			   "\r\n %-35s = %s (BB:%s)/ %s (BB:%s)/ %s %d",
+			   "GNT_WL_Ctrl/GNT_BT_Ctrl/Dbg",
+			   ((u32tmp[0] & BIT(12)) ? "SW" : "HW"),
+			   ((u32tmp[0] & BIT(8)) ?	"SW" : "HW"),
+			   ((u32tmp[0] & BIT(14)) ? "SW" : "HW"),
+			   ((u32tmp[0] & BIT(10)) ?  "SW" : "HW"),
+			   ((u8tmp[0] & BIT(3)) ? "On" : "Off"),
+			   coex_sta->gnt_error_cnt);
+	CL_PRINTF(cli_buf);
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d",
+		   "GNT_WL/GNT_BT",
+		   (int)((u32tmp[1] & BIT(2)) >> 2),
+		   (int)((u32tmp[1] & BIT(3)) >> 3));
+	CL_PRINTF(cli_buf);
+
+	u16tmp[0] = btcoexist->btc_read_2byte(btcoexist, 0x948);
+	u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x67);
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x",
+		   "0x948/0x67[7]",
+		   u16tmp[0], (int)((u8tmp[0] & BIT(7)) >> 7));
+	CL_PRINTF(cli_buf);
+
+	u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x964);
+	u8tmp[1] = btcoexist->btc_read_1byte(btcoexist, 0x864);
+	u8tmp[2] = btcoexist->btc_read_1byte(btcoexist, 0xab7);
+	u8tmp[3] = btcoexist->btc_read_1byte(btcoexist, 0xa01);
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+		   "\r\n %-35s = 0x%x/ 0x%x/ 0x%x/ 0x%x",
+		   "0x964[1]/0x864[0]/0xab7[5]/0xa01[7]",
+		   (int)((u8tmp[0] & BIT(1)) >> 1), (int)((u8tmp[1] & BIT(0))),
+		   (int)((u8tmp[2] & BIT(3)) >> 3),
+		   (int)((u8tmp[3] & BIT(7)) >> 7));
+	CL_PRINTF(cli_buf);
+
+	u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x4c6);
+	u8tmp[1] = btcoexist->btc_read_1byte(btcoexist, 0x40);
+	u8tmp[2] = btcoexist->btc_read_1byte(btcoexist, 0x45e);
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x/ 0x%x",
+		   "0x4c6[4]/0x40[5]/0x45e[3](TxRetry)",
+		   (int)((u8tmp[0] & BIT(4)) >> 4),
+		   (int)((u8tmp[1] & BIT(5)) >> 5),
+		   (int)((u8tmp[2] & BIT(3)) >> 3));
+	CL_PRINTF(cli_buf);
+
+	u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x550);
+	u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x522);
+	u8tmp[1] = btcoexist->btc_read_1byte(btcoexist, 0x953);
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x/ %s",
+		   "0x550/0x522/4-RxAGC",
+		   u32tmp[0], u8tmp[0], (u8tmp[1] & 0x2) ? "On" : "Off");
+	CL_PRINTF(cli_buf);
+
+	fa_ofdm = btcoexist->btc_phydm_query_PHY_counter(btcoexist, PHYDM_INFO_FA_OFDM);
+	fa_cck = btcoexist->btc_phydm_query_PHY_counter(btcoexist, PHYDM_INFO_FA_CCK);
+	cca_ofdm = btcoexist->btc_phydm_query_PHY_counter(btcoexist, PHYDM_INFO_CCA_OFDM);
+	cca_cck = btcoexist->btc_phydm_query_PHY_counter(btcoexist, PHYDM_INFO_CCA_CCK);
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+		   "\r\n %-35s = 0x%x/ 0x%x/ 0x%x/ 0x%x",
+		   "CCK-CCA/CCK-FA/OFDM-CCA/OFDM-FA",
+		   cca_cck, fa_cck, cca_ofdm, fa_ofdm);
+	CL_PRINTF(cli_buf);
+
+#if 1
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d/ %d",
+		   "CRC_OK CCK/11g/11n/11n-agg",
+		   coex_sta->crc_ok_cck, coex_sta->crc_ok_11g,
+		   coex_sta->crc_ok_11n, coex_sta->crc_ok_11n_vht);
+	CL_PRINTF(cli_buf);
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d/ %d",
+		   "CRC_Err CCK/11g/11n/11n-agg",
+		   coex_sta->crc_err_cck, coex_sta->crc_err_11g,
+		   coex_sta->crc_err_11n, coex_sta->crc_err_11n_vht);
+	CL_PRINTF(cli_buf);
+#endif
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s/ %s/ %s/ %d",
+		   "WlHiPri/ Locking/ Locked/ Noisy",
+		   (coex_sta->wifi_is_high_pri_task ? "Yes" : "No"),
+		   (coex_sta->cck_lock ? "Yes" : "No"),
+		   (coex_sta->cck_ever_lock ? "Yes" : "No"),
+		   coex_sta->wl_noisy_level);
+	CL_PRINTF(cli_buf);
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d %s",
+		   "0x770(Hi-pri rx/tx)",
+		   coex_sta->high_priority_rx, coex_sta->high_priority_tx,
+		   (coex_sta->is_hiPri_rx_overhead ? "(scan overhead!!)" : ""));
+	CL_PRINTF(cli_buf);
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d %s",
+		   "0x774(Lo-pri rx/tx)",
+		   coex_sta->low_priority_rx, coex_sta->low_priority_tx,
+		   (bt_link_info->slave_role ? "(Slave!!)" : (
+		   coex_sta->is_tdma_btautoslot_hang ? "(auto-slot hang!!)" : "")));
+	CL_PRINTF(cli_buf);
+
+	btcoexist->btc_disp_dbg_msg(btcoexist, BTC_DBG_DISP_COEX_STATISTICS);
+}
+
+
+void ex_halbtc8723d1ant_ips_notify(IN struct btc_coexist *btcoexist, IN u8 type)
+{
+	if (btcoexist->manual_control ||	btcoexist->stop_coex_dm)
+		return;
+
+	if (BTC_IPS_ENTER == type) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], IPS ENTER notify\n");
+		BTC_TRACE(trace_buf);
+		coex_sta->under_ips = true;
+
+		/* Write WL "Active" in Score-board for LPS off */
+		halbtc8723d1ant_post_state_to_bt(btcoexist,
+				BT_8723D_1ANT_SCOREBOARD_ACTIVE |
+				BT_8723D_1ANT_SCOREBOARD_ONOFF |
+				BT_8723D_1ANT_SCOREBOARD_SCAN |
+				BT_8723D_1ANT_SCOREBOARD_UNDERTEST,
+				false);
+
+		halbtc8723d1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 0);
+
+		halbtc8723d1ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO,
+					     FORCE_EXEC,
+					     BT_8723D_1ANT_PHASE_WLAN_OFF);
+
+		halbtc8723d1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0);
+	} else if (BTC_IPS_LEAVE == type) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], IPS LEAVE notify\n");
+		BTC_TRACE(trace_buf);
+#if 0
+		halbtc8723d1ant_post_state_to_bt(btcoexist,
+					 BT_8723D_1ANT_SCOREBOARD_ACTIVE, true);
+
+		halbtc8723d1ant_post_state_to_bt(btcoexist,
+				 BT_8723D_1ANT_SCOREBOARD_ONOFF, true);
+#endif
+
+		halbtc8723d1ant_init_hw_config(btcoexist, false, false);
+		halbtc8723d1ant_init_coex_dm(btcoexist);;
+
+		coex_sta->under_ips = false;
+	}
+}
+
+void ex_halbtc8723d1ant_lps_notify(IN struct btc_coexist *btcoexist, IN u8 type)
+{
+	if (btcoexist->manual_control || btcoexist->stop_coex_dm)
+		return;
+
+	if (BTC_LPS_ENABLE == type) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], LPS ENABLE notify\n");
+		BTC_TRACE(trace_buf);
+		coex_sta->under_lps = true;
+
+		if (coex_sta->force_lps_on == true) { /* LPS No-32K */
+			/* Write WL "Active" in Score-board for PS-TDMA */
+			halbtc8723d1ant_post_state_to_bt(btcoexist,
+					 BT_8723D_1ANT_SCOREBOARD_ACTIVE, true);
+
+		} else { /* LPS-32K, need check if this h2c 0x71 can work?? (2015/08/28) */
+			/* Write WL "Non-Active" in Score-board for Native-PS */
+			halbtc8723d1ant_post_state_to_bt(btcoexist,
+				 BT_8723D_1ANT_SCOREBOARD_ACTIVE, false);
+
+		}
+	} else if (BTC_LPS_DISABLE == type) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], LPS DISABLE notify\n");
+		BTC_TRACE(trace_buf);
+		coex_sta->under_lps = false;
+
+		/* Write WL "Active" in Score-board for LPS off */
+		halbtc8723d1ant_post_state_to_bt(btcoexist,
+					 BT_8723D_1ANT_SCOREBOARD_ACTIVE, true);
+
+	}
+}
+
+void ex_halbtc8723d1ant_scan_notify(IN struct btc_coexist *btcoexist,
+				    IN u8 type)
+{
+	boolean wifi_connected = false;
+
+	if (btcoexist->manual_control ||
+	    btcoexist->stop_coex_dm)
+		return;
+
+	coex_sta->freeze_coexrun_by_btinfo = false;
+
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED,
+			   &wifi_connected);
+
+	halbtc8723d1ant_query_bt_info(btcoexist);
+
+	if (BTC_SCAN_START == type) {
+
+		if (!wifi_connected)
+			coex_sta->wifi_is_high_pri_task = true;
+
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], SCAN START notify\n");
+		BTC_TRACE(trace_buf);
+
+		halbtc8723d1ant_post_state_to_bt(btcoexist,
+					BT_8723D_1ANT_SCOREBOARD_ACTIVE |
+					BT_8723D_1ANT_SCOREBOARD_SCAN |
+					BT_8723D_1ANT_SCOREBOARD_ONOFF,
+					true);
+
+		/* Force antenna setup for no scan result issue */
+		halbtc8723d1ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO,
+					     FORCE_EXEC,
+					     BT_8723D_1ANT_PHASE_2G_RUNTIME);
+
+		halbtc8723d1ant_run_coexist_mechanism(btcoexist);
+
+	} else {
+
+		coex_sta->wifi_is_high_pri_task = false;
+
+		btcoexist->btc_get(btcoexist, BTC_GET_U1_AP_NUM,
+				   &coex_sta->scan_ap_num);
+
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], SCAN FINISH notify  (Scan-AP = %d)\n",
+			    coex_sta->scan_ap_num);
+		BTC_TRACE(trace_buf);
+
+		halbtc8723d1ant_run_coexist_mechanism(btcoexist);
+	}
+
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+		    "[BTCoex], SCAN Notify() end\n");
+	BTC_TRACE(trace_buf);
+
+}
+
+void ex_halbtc8723d1ant_connect_notify(IN struct btc_coexist *btcoexist,
+				       IN u8 type)
+{
+	boolean	wifi_connected = false;
+
+	if (btcoexist->manual_control ||
+	    btcoexist->stop_coex_dm)
+		return;
+
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED,
+			   &wifi_connected);
+
+	if (BTC_ASSOCIATE_START == type) {
+
+		coex_sta->wifi_is_high_pri_task = true;
+
+		halbtc8723d1ant_post_state_to_bt(btcoexist,
+					 BT_8723D_1ANT_SCOREBOARD_ACTIVE |
+					 BT_8723D_1ANT_SCOREBOARD_SCAN |
+					 BT_8723D_1ANT_SCOREBOARD_ONOFF,
+					 true);
+
+		/* Force antenna setup for no scan result issue */
+		halbtc8723d1ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO,
+					     FORCE_EXEC,
+					     BT_8723D_1ANT_PHASE_2G_RUNTIME);
+
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], CONNECT START notify\n");
+		BTC_TRACE(trace_buf);
+
+		coex_dm->arp_cnt = 0;
+
+		halbtc8723d1ant_run_coexist_mechanism(btcoexist);
+
+		/* To keep TDMA case during connect process,
+		to avoid changed by Btinfo and runcoexmechanism */
+		coex_sta->freeze_coexrun_by_btinfo = true;
+	} else {
+
+		coex_sta->wifi_is_high_pri_task = false;
+		coex_sta->freeze_coexrun_by_btinfo = false;
+
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], CONNECT FINISH notify\n");
+		BTC_TRACE(trace_buf);
+
+		halbtc8723d1ant_run_coexist_mechanism(btcoexist);
+	}
+
+}
+
+void ex_halbtc8723d1ant_media_status_notify(IN struct btc_coexist *btcoexist,
+		IN u8 type)
+{
+	boolean			wifi_under_b_mode = false;
+
+	if (btcoexist->manual_control ||
+	    btcoexist->stop_coex_dm)
+		return;
+
+	if (BTC_MEDIA_CONNECT == type) {
+
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], MEDIA connect notify\n");
+		BTC_TRACE(trace_buf);
+
+		halbtc8723d1ant_post_state_to_bt(btcoexist,
+					 BT_8723D_1ANT_SCOREBOARD_ACTIVE |
+					 BT_8723D_1ANT_SCOREBOARD_ONOFF,
+					 true);
+
+		/* Force antenna setup for no scan result issue */
+		halbtc8723d1ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO,
+					     FORCE_EXEC,
+					     BT_8723D_1ANT_PHASE_2G_RUNTIME);
+
+		btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_B_MODE,
+				   &wifi_under_b_mode);
+
+		/* Set CCK Tx/Rx high Pri except 11b mode */
+		if (wifi_under_b_mode) {
+			btcoexist->btc_write_1byte(btcoexist, 0x6cd,
+						   0x00); /* CCK Tx */
+			btcoexist->btc_write_1byte(btcoexist, 0x6cf,
+						   0x00); /* CCK Rx */
+		} else {
+			/* btcoexist->btc_write_1byte(btcoexist, 0x6cd, 0x10); */ /*CCK Tx */
+			/* btcoexist->btc_write_1byte(btcoexist, 0x6cf, 0x10); */ /*CCK Rx */
+			btcoexist->btc_write_1byte(btcoexist, 0x6cd,
+						   0x00); /* CCK Tx */
+			btcoexist->btc_write_1byte(btcoexist, 0x6cf,
+						   0x10); /* CCK Rx */
+		}
+
+		coex_dm->backup_arfr_cnt1 = btcoexist->btc_read_4byte(btcoexist,
+					    0x430);
+		coex_dm->backup_arfr_cnt2 = btcoexist->btc_read_4byte(btcoexist,
+					    0x434);
+		coex_dm->backup_retry_limit = btcoexist->btc_read_2byte(
+						      btcoexist, 0x42a);
+		coex_dm->backup_ampdu_max_time = btcoexist->btc_read_1byte(
+				btcoexist, 0x456);
+	} else {
+
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], MEDIA disconnect notify\n");
+		BTC_TRACE(trace_buf);
+
+		halbtc8723d1ant_post_state_to_bt(btcoexist,
+				 BT_8723D_1ANT_SCOREBOARD_ACTIVE, false);
+
+		btcoexist->btc_write_1byte(btcoexist, 0x6cd, 0x0); /* CCK Tx */
+		btcoexist->btc_write_1byte(btcoexist, 0x6cf, 0x0); /* CCK Rx */
+
+		coex_sta->cck_ever_lock = false;
+	}
+
+	halbtc8723d1ant_update_wifi_channel_info(btcoexist, type);
+
+}
+
+void ex_halbtc8723d1ant_specific_packet_notify(IN struct btc_coexist *btcoexist,
+		IN u8 type)
+{
+	boolean	under_4way = false;
+
+	if (btcoexist->manual_control ||
+	    btcoexist->stop_coex_dm)
+		return;
+
+
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_4_WAY_PROGRESS,
+			   &under_4way);
+
+	if (under_4way) {
+
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], specific Packet ---- under_4way!!\n");
+		BTC_TRACE(trace_buf);
+
+		coex_sta->wifi_is_high_pri_task = true;
+		coex_sta->specific_pkt_period_cnt = 2;
+	} else if (BTC_PACKET_ARP == type) {
+
+		coex_dm->arp_cnt++;
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], specific Packet ARP notify -cnt = %d\n",
+			    coex_dm->arp_cnt);
+		BTC_TRACE(trace_buf);
+
+	} else {
+
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			"[BTCoex], specific Packet DHCP or EAPOL notify [Type = %d]\n",
+			    type);
+		BTC_TRACE(trace_buf);
+
+		coex_sta->wifi_is_high_pri_task = true;
+		coex_sta->specific_pkt_period_cnt = 2;
+	}
+
+	if (coex_sta->wifi_is_high_pri_task) {
+		halbtc8723d1ant_post_state_to_bt(btcoexist,
+					 BT_8723D_1ANT_SCOREBOARD_SCAN, true);
+		halbtc8723d1ant_run_coexist_mechanism(btcoexist);
+	}
+}
+
+void ex_halbtc8723d1ant_bt_info_notify(IN struct btc_coexist *btcoexist,
+				       IN u8 *tmp_buf, IN u8 length)
+{
+	u8			i, rsp_source = 0;
+	boolean	wifi_connected = false;
+	boolean	wifi_scan = false, wifi_link = false, wifi_roam = false,
+		    wifi_busy = false;
+	static boolean is_scoreboard_scan = false;
+
+	if (psd_scan->is_AntDet_running == true) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			"[BTCoex], bt_info_notify return for AntDet is running\n");
+		BTC_TRACE(trace_buf);
+		return;
+	}
+
+	rsp_source = tmp_buf[0] & 0xf;
+	if (rsp_source >= BT_INFO_SRC_8723D_1ANT_MAX)
+		rsp_source = BT_INFO_SRC_8723D_1ANT_WIFI_FW;
+	coex_sta->bt_info_c2h_cnt[rsp_source]++;
+
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+		    "[BTCoex], Bt_info[%d], len=%d, data=[", rsp_source,
+		    length);
+	BTC_TRACE(trace_buf);
+
+	for (i = 0; i < length; i++) {
+		coex_sta->bt_info_c2h[rsp_source][i] = tmp_buf[i];
+
+		if (i == length - 1) {
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "0x%02x]\n",
+				    tmp_buf[i]);
+			BTC_TRACE(trace_buf);
+		} else {
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "0x%02x, ",
+				    tmp_buf[i]);
+			BTC_TRACE(trace_buf);
+		}
+	}
+
+	coex_sta->bt_info = coex_sta->bt_info_c2h[rsp_source][1];
+	coex_sta->bt_info_ext = coex_sta->bt_info_c2h[rsp_source][4];
+	coex_sta->bt_info_ext2 = coex_sta->bt_info_c2h[rsp_source][5];
+
+	if (BT_INFO_SRC_8723D_1ANT_WIFI_FW != rsp_source) {
+
+		/* if 0xff, it means BT is under WHCK test */
+		coex_sta->bt_whck_test = ((coex_sta->bt_info == 0xff) ? true :
+					  false);
+
+		coex_sta->bt_create_connection = ((
+			coex_sta->bt_info_c2h[rsp_source][2] & 0x80) ? true :
+						  false);
+
+		/* unit: %, value-100 to translate to unit: dBm */
+		coex_sta->bt_rssi = coex_sta->bt_info_c2h[rsp_source][3] * 2 +
+				    10;
+
+		coex_sta->c2h_bt_remote_name_req = ((
+			coex_sta->bt_info_c2h[rsp_source][2] & 0x20) ? true :
+						    false);
+
+		coex_sta->is_A2DP_3M = ((coex_sta->bt_info_c2h[rsp_source][2] &
+					 0x10) ? true : false);
+
+		coex_sta->acl_busy = ((coex_sta->bt_info_c2h[rsp_source][1] &
+				       0x9) ? true : false);
+
+		coex_sta->voice_over_HOGP = ((coex_sta->bt_info_ext & 0x10) ?
+					     true : false);
+
+		coex_sta->c2h_bt_inquiry_page = ((coex_sta->bt_info &
+			  BT_INFO_8723D_1ANT_B_INQ_PAGE) ? true : false);
+
+		coex_sta->a2dp_bit_pool = (((
+			coex_sta->bt_info_c2h[rsp_source][1] & 0x49) == 0x49) ?
+				   coex_sta->bt_info_c2h[rsp_source][6] : 0);
+
+		coex_sta->bt_retry_cnt = coex_sta->bt_info_c2h[rsp_source][2] &
+					 0xf;
+
+		coex_sta->is_autoslot = coex_sta->bt_info_ext2 & 0x8;
+
+		coex_sta->forbidden_slot = coex_sta->bt_info_ext2 & 0x7;
+
+		coex_sta->hid_busy_num = (coex_sta->bt_info_ext2 & 0x30) >> 4;
+
+		coex_sta->hid_pair_cnt = (coex_sta->bt_info_ext2 & 0xc0) >> 6;
+
+		if (coex_sta->bt_retry_cnt >= 1)
+			coex_sta->pop_event_cnt++;
+
+		if (coex_sta->c2h_bt_remote_name_req)
+			coex_sta->cnt_RemoteNameReq++;
+
+		if (coex_sta->bt_info_ext & BIT(1))
+			coex_sta->cnt_ReInit++;
+
+		if (coex_sta->bt_info_ext & BIT(2)) {
+			coex_sta->cnt_setupLink++;
+			coex_sta->is_setupLink = true;
+		} else
+			coex_sta->is_setupLink = false;
+
+		if (coex_sta->bt_info_ext & BIT(3))
+			coex_sta->cnt_IgnWlanAct++;
+
+		if (coex_sta->bt_info_ext & BIT(6))
+			coex_sta->cnt_RoleSwitch++;
+
+		if (coex_sta->bt_create_connection) {
+			coex_sta->cnt_Page++;
+
+			btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY,
+					   &wifi_busy);
+
+			btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_SCAN, &wifi_scan);
+			btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_LINK, &wifi_link);
+			btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_ROAM, &wifi_roam);
+
+			if ((wifi_link) || (wifi_roam) || (wifi_scan) ||
+			    (coex_sta->wifi_is_high_pri_task) || (wifi_busy)) {
+
+				is_scoreboard_scan = true;
+				halbtc8723d1ant_post_state_to_bt(btcoexist,
+					 BT_8723D_1ANT_SCOREBOARD_SCAN, true);
+
+			} else
+				halbtc8723d1ant_post_state_to_bt(btcoexist,
+					 BT_8723D_1ANT_SCOREBOARD_SCAN, false);
+
+		} else {
+				if (is_scoreboard_scan) {
+					halbtc8723d1ant_post_state_to_bt(btcoexist,
+						 BT_8723D_1ANT_SCOREBOARD_SCAN, false);
+					is_scoreboard_scan = false;
+				}
+		}
+
+		/* Here we need to resend some wifi info to BT */
+		/* because bt is reset and loss of the info. */
+
+		if ((!btcoexist->manual_control) &&
+		    (!btcoexist->stop_coex_dm)) {
+
+			btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED,
+					   &wifi_connected);
+
+			/*	Re-Init */
+			if ((coex_sta->bt_info_ext & BIT(1))) {
+				BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+					"[BTCoex], BT ext info bit1 check, send wifi BW&Chnl to BT!!\n");
+				BTC_TRACE(trace_buf);
+				if (wifi_connected)
+					halbtc8723d1ant_update_wifi_channel_info(
+						btcoexist, BTC_MEDIA_CONNECT);
+				else
+					halbtc8723d1ant_update_wifi_channel_info(
+						btcoexist,
+						BTC_MEDIA_DISCONNECT);
+			}
+
+
+	  /*	If Ignore_WLanAct && not SetUp_Link or Role_Switch */
+			if ((coex_sta->bt_info_ext & BIT(3)) &&
+				(!(coex_sta->bt_info_ext & BIT(2))) &&
+				(!(coex_sta->bt_info_ext & BIT(6)))) {
+
+				BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+					"[BTCoex], BT ext info bit3 check, set BT NOT to ignore Wlan active!!\n");
+				BTC_TRACE(trace_buf);
+				halbtc8723d1ant_ignore_wlan_act(btcoexist,
+							FORCE_EXEC, false);
+			} else {
+				if (coex_sta->bt_info_ext & BIT(2)) {
+					BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+					"[BTCoex], BT ignore Wlan active because Re-link!!\n");
+					BTC_TRACE(trace_buf);
+				} else if (coex_sta->bt_info_ext & BIT(6)) {
+					BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+					"[BTCoex], BT ignore Wlan active because Role-Switch!!\n");
+					BTC_TRACE(trace_buf);
+				}
+			}
+		}
+
+	}
+
+	if ((coex_sta->bt_info_ext & BIT(5))) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+					"[BTCoex], BT ext info bit4 check, query BLE Scan type!!\n");
+				BTC_TRACE(trace_buf);
+	coex_sta->bt_ble_scan_type = btcoexist->btc_get_ble_scan_type_from_bt(btcoexist);
+
+	if ((coex_sta->bt_ble_scan_type & 0x1) == 0x1)
+		coex_sta->bt_ble_scan_para[0]  = btcoexist->btc_get_ble_scan_para_from_bt(btcoexist, 0x1);
+	if ((coex_sta->bt_ble_scan_type & 0x2) == 0x2)
+		coex_sta->bt_ble_scan_para[1]  = btcoexist->btc_get_ble_scan_para_from_bt(btcoexist, 0x2);
+	if ((coex_sta->bt_ble_scan_type & 0x4) == 0x4)
+		coex_sta->bt_ble_scan_para[2]  = btcoexist->btc_get_ble_scan_para_from_bt(btcoexist, 0x4);
+	}
+
+	halbtc8723d1ant_update_bt_link_info(btcoexist);
+
+	halbtc8723d1ant_run_coexist_mechanism(btcoexist);
+}
+
+
+
+void ex_halbtc8723d1ant_rf_status_notify(IN struct btc_coexist *btcoexist,
+		IN u8 type)
+{
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], RF Status notify\n");
+	BTC_TRACE(trace_buf);
+
+	if (BTC_RF_ON == type) {
+
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], RF is turned ON!!\n");
+		BTC_TRACE(trace_buf);
+
+		btcoexist->stop_coex_dm = false;
+#if 0
+		halbtc8723d1ant_post_state_to_bt(btcoexist,
+					 BT_8723D_1ANT_SCOREBOARD_ACTIVE, true);
+		halbtc8723d1ant_post_state_to_bt(btcoexist,
+					 BT_8723D_1ANT_SCOREBOARD_ONOFF, true);
+#endif
+
+	} else if (BTC_RF_OFF == type) {
+
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], RF is turned OFF!!\n");
+		BTC_TRACE(trace_buf);
+
+		halbtc8723d1ant_post_state_to_bt(btcoexist,
+				BT_8723D_1ANT_SCOREBOARD_ACTIVE |
+				BT_8723D_1ANT_SCOREBOARD_ONOFF |
+				BT_8723D_1ANT_SCOREBOARD_SCAN |
+				BT_8723D_1ANT_SCOREBOARD_UNDERTEST,
+				false);
+
+		halbtc8723d1ant_ps_tdma(btcoexist, FORCE_EXEC, false, 0);
+
+		halbtc8723d1ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO,
+					     FORCE_EXEC,
+					     BT_8723D_1ANT_PHASE_WLAN_OFF);
+
+		btcoexist->stop_coex_dm = true;
+	}
+}
+
+void ex_halbtc8723d1ant_halt_notify(IN struct btc_coexist *btcoexist)
+{
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], Halt notify\n");
+	BTC_TRACE(trace_buf);
+
+	halbtc8723d1ant_post_state_to_bt(btcoexist,
+				BT_8723D_1ANT_SCOREBOARD_ACTIVE |
+				BT_8723D_1ANT_SCOREBOARD_ONOFF |
+				BT_8723D_1ANT_SCOREBOARD_SCAN |
+				BT_8723D_1ANT_SCOREBOARD_UNDERTEST,
+				false);
+
+	halbtc8723d1ant_ps_tdma(btcoexist, FORCE_EXEC, false, 0);
+
+	halbtc8723d1ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, FORCE_EXEC,
+				     BT_8723D_1ANT_PHASE_WLAN_OFF);
+
+	halbtc8723d1ant_ignore_wlan_act(btcoexist, FORCE_EXEC, true);
+
+	ex_halbtc8723d1ant_media_status_notify(btcoexist, BTC_MEDIA_DISCONNECT);
+
+	btcoexist->stop_coex_dm = true;
+}
+
+void ex_halbtc8723d1ant_pnp_notify(IN struct btc_coexist *btcoexist,
+				   IN u8 pnp_state)
+{
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], Pnp notify\n");
+	BTC_TRACE(trace_buf);
+
+	if ((BTC_WIFI_PNP_SLEEP == pnp_state) ||
+	    (BTC_WIFI_PNP_SLEEP_KEEP_ANT == pnp_state)) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], Pnp notify to SLEEP\n");
+		BTC_TRACE(trace_buf);
+
+		halbtc8723d1ant_post_state_to_bt(btcoexist,
+				BT_8723D_1ANT_SCOREBOARD_ACTIVE |
+				BT_8723D_1ANT_SCOREBOARD_ONOFF |
+				BT_8723D_1ANT_SCOREBOARD_SCAN |
+				BT_8723D_1ANT_SCOREBOARD_UNDERTEST,
+				false);
+
+		if (BTC_WIFI_PNP_SLEEP_KEEP_ANT == pnp_state) {
+
+			halbtc8723d1ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO,
+						     FORCE_EXEC,
+					     BT_8723D_1ANT_PHASE_2G_RUNTIME);
+		} else {
+
+			halbtc8723d1ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO,
+						     FORCE_EXEC,
+					     BT_8723D_1ANT_PHASE_WLAN_OFF);
+		}
+
+		btcoexist->stop_coex_dm = true;
+	} else if (BTC_WIFI_PNP_WAKE_UP == pnp_state) {
+
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], Pnp notify to WAKE UP\n");
+		BTC_TRACE(trace_buf);
+#if 0
+		halbtc8723d1ant_post_state_to_bt(btcoexist,
+					 BT_8723D_1ANT_SCOREBOARD_ACTIVE, true);
+		halbtc8723d1ant_post_state_to_bt(btcoexist,
+					 BT_8723D_1ANT_SCOREBOARD_ONOFF, true);
+#endif
+		btcoexist->stop_coex_dm = false;
+	}
+}
+
+
+void ex_halbtc8723d1ant_coex_dm_reset(IN struct btc_coexist *btcoexist)
+{
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+		"[BTCoex], *****************Coex DM Reset*****************\n");
+	BTC_TRACE(trace_buf);
+
+	halbtc8723d1ant_init_hw_config(btcoexist, false, false);
+	halbtc8723d1ant_init_coex_dm(btcoexist);
+}
+
+void ex_halbtc8723d1ant_periodical(IN struct btc_coexist *btcoexist)
+{
+
+	struct  btc_board_info	*board_info = &btcoexist->board_info;
+	boolean wifi_busy = false;
+	u4Byte	value = 0;
+	u32	bt_patch_ver;
+	static u8 cnt = 0;
+	boolean bt_relink_finish = false;
+
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+		    "[BTCoex], ************* Periodical *************\n");
+	BTC_TRACE(trace_buf);
+
+#if (BT_AUTO_REPORT_ONLY_8723D_1ANT == 0)
+	halbtc8723d1ant_query_bt_info(btcoexist);
+
+#endif
+
+	halbtc8723d1ant_monitor_bt_ctr(btcoexist);
+	halbtc8723d1ant_monitor_wifi_ctr(btcoexist);
+
+	halbtc8723d1ant_monitor_bt_enable_disable(btcoexist);
+
+#if 0
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy);
+
+	/* halbtc8723d1ant_read_score_board(btcoexist, &bt_scoreboard_val); */
+
+	if (wifi_busy) {
+		halbtc8723d1ant_post_state_to_bt(btcoexist,
+				BT_8723D_1ANT_SCOREBOARD_UNDERTEST, true);
+		/*
+		halbtc8723d1ant_post_state_to_bt(btcoexist,
+					 BT_8723D_1ANT_SCOREBOARD_WLBUSY, true);
+
+		if (bt_scoreboard_val & BIT(6))
+			halbtc8723d1ant_query_bt_info(btcoexist); */
+	} else {
+		halbtc8723d1ant_post_state_to_bt(btcoexist,
+					BT_8723D_1ANT_SCOREBOARD_UNDERTEST, false);
+		/*
+		halbtc8723d1ant_post_state_to_bt(btcoexist,
+					BT_8723D_1ANT_SCOREBOARD_WLBUSY,
+					false);  */
+	}
+#endif
+
+	if (coex_sta->bt_relink_downcount != 0) {
+		coex_sta->bt_relink_downcount--;
+
+		if (coex_sta->bt_relink_downcount == 0)
+			bt_relink_finish = true;
+	}
+
+	/* for 4-way, DHCP, EAPOL packet */
+	if (coex_sta->specific_pkt_period_cnt > 0) {
+
+		coex_sta->specific_pkt_period_cnt--;
+
+		if ((coex_sta->specific_pkt_period_cnt == 0) &&
+		    (coex_sta->wifi_is_high_pri_task))
+			coex_sta->wifi_is_high_pri_task = false;
+
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			"[BTCoex], ***************** Hi-Pri Task = %s*****************\n",
+			    (coex_sta->wifi_is_high_pri_task ? "Yes" :
+			     "No"));
+		BTC_TRACE(trace_buf);
+
+	}
+
+	if (!coex_sta->bt_disabled) {
+
+#if BT_8723D_1ANT_ANTDET_ENABLE
+
+		if (board_info->btdm_ant_det_finish) {
+			if ((psd_scan->ant_det_result == 12) &&
+			    (psd_scan->ant_det_psd_scan_peak_val == 0)
+			    && (!psd_scan->is_AntDet_running)) {
+				psd_scan->ant_det_psd_scan_peak_val =
+					btcoexist->btc_get_ant_det_val_from_bt(
+					btcoexist) * 100;
+
+				board_info->antdetval = psd_scan->ant_det_psd_scan_peak_val/100;
+				value = board_info->antdetval;
+
+#ifdef PLATFORM_WINDOWS
+				{
+					PWCHAR	registryName;
+
+					registryName = L"antdetval";
+					PlatformWriteCommonDwordRegistry(registryName, &value);
+				}
+#endif
+			}
+		}
+
+#endif
+	}
+
+	if (halbtc8723d1ant_is_wifibt_status_changed(btcoexist))
+		halbtc8723d1ant_run_coexist_mechanism(btcoexist);
+
+
+}
+
+void ex_halbtc8723d1ant_set_antenna_notify(IN struct btc_coexist *btcoexist,
+		IN u8 type)
+{
+	struct  btc_board_info	*board_info = &btcoexist->board_info;
+
+	if (btcoexist->manual_control || btcoexist->stop_coex_dm)
+		return;
+
+	if (type == 2) { /* two antenna */
+		board_info->ant_div_cfg = true;
+		halbtc8723d1ant_set_ant_path(btcoexist, BTC_ANT_PATH_WIFI,
+					     FORCE_EXEC,
+					     BT_8723D_1ANT_PHASE_2G_RUNTIME);
+	} else { /* one antenna */
+		halbtc8723d1ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO,
+					     FORCE_EXEC,
+					     BT_8723D_1ANT_PHASE_2G_RUNTIME);
+	}
+}
+
+#ifdef PLATFORM_WINDOWS
+#pragma optimize("", off)
+#endif
+void ex_halbtc8723d1ant_antenna_detection(IN struct btc_coexist *btcoexist,
+		IN u32 cent_freq, IN u32 offset, IN u32 span, IN u32 seconds)
+{
+
+	static u32 ant_det_count = 0, ant_det_fail_count = 0;
+	struct  btc_board_info	*board_info = &btcoexist->board_info;
+	u16		u16tmp;
+	u8			AntDetval = 0;
+
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+		    "xxxxxxxxxxxxxxxx Ext Call AntennaDetect()!!\n");
+	BTC_TRACE(trace_buf);
+
+#if BT_8723D_1ANT_ANTDET_ENABLE
+
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+		    "xxxxxxxxxxxxxxxx Call AntennaDetect()!!\n");
+	BTC_TRACE(trace_buf);
+
+	if (seconds == 0) {
+		psd_scan->ant_det_try_count	= 0;
+		psd_scan->ant_det_fail_count	= 0;
+		ant_det_count = 0;
+		ant_det_fail_count = 0;
+		board_info->btdm_ant_det_finish = false;
+		board_info->btdm_ant_num_by_ant_det = 1;
+		return;
+	}
+
+	if (!board_info->btdm_ant_det_finish) {
+		psd_scan->ant_det_inteval_count =
+			psd_scan->ant_det_inteval_count + 2;
+
+		if (psd_scan->ant_det_inteval_count >=
+		    BT_8723D_2ANT_ANTDET_RETRY_INTERVAL) {
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				"xxxxxxxxxxxxxxxx AntennaDetect(), Antenna Det Timer is up, Try Detect!!\n");
+			BTC_TRACE(trace_buf);
+
+			psd_scan->is_AntDet_running = true;
+
+			halbtc8723d1ant_read_score_board(btcoexist,	&u16tmp);
+
+			if (u16tmp & BIT(
+				2)) { /* Antenna detection is already done before last WL power on   */
+				board_info->btdm_ant_det_finish = true;
+				psd_scan->ant_det_try_count = 1;
+				psd_scan->ant_det_fail_count = 0;
+				board_info->btdm_ant_num_by_ant_det = (u16tmp &
+							       BIT(3)) ? 1 : 2;
+				psd_scan->ant_det_result = 12;
+
+				psd_scan->ant_det_psd_scan_peak_val =
+					btcoexist->btc_get_ant_det_val_from_bt(
+						btcoexist) * 100;
+
+				BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+					"xxxxxxxxxxxxxxxx AntennaDetect(), Antenna Det Result from BT (%d-Ant)\n",
+					board_info->btdm_ant_num_by_ant_det);
+				BTC_TRACE(trace_buf);
+			} else
+				board_info->btdm_ant_det_finish =
+					halbtc8723d1ant_psd_antenna_detection_check(
+						btcoexist);
+
+			board_info->ant_det_result = psd_scan->ant_det_result;
+			btcoexist->bdontenterLPS = false;
+
+			if (board_info->btdm_ant_det_finish) {
+
+				BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+					"xxxxxxxxxxxxxxxx AntennaDetect(), Antenna Det Success!!\n");
+				BTC_TRACE(trace_buf);
+
+				if (board_info->btdm_ant_num_by_ant_det == 2) {
+					board_info->ant_div_cfg = true;
+					halbtc8723d1ant_set_ant_path(btcoexist,
+						BTC_ANT_PATH_WIFI, FORCE_EXEC,
+						BT_8723D_1ANT_PHASE_2G_RUNTIME);
+				} else
+					halbtc8723d1ant_set_ant_path(btcoexist,
+						BTC_ANT_PATH_AUTO, FORCE_EXEC,
+						BT_8723D_1ANT_PHASE_2G_RUNTIME);
+
+				/*for 8723d, btc_set_bt_trx_mask is just used to
+					notify BT stop le tx and Ant Det Result , not set BT RF TRx Mask  */
+				if (psd_scan->ant_det_result != 12) {
+
+					AntDetval = (u8)(
+						psd_scan->ant_det_psd_scan_peak_val
+							    / 100) & 0x7f;
+
+					AntDetval =
+						(board_info->btdm_ant_num_by_ant_det
+						 == 1) ? (AntDetval | 0x80) :
+						AntDetval;
+					board_info->antdetval = AntDetval;
+
+					BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+						"xxxxxx AntennaDetect(), Ant Count = %d, PSD Val = %d\n",
+						    ((AntDetval &
+						      0x80) ? 1
+						     : 2), AntDetval
+						    & 0x7f);
+					BTC_TRACE(trace_buf);
+
+					if (btcoexist->btc_set_bt_trx_mask(
+						    btcoexist, AntDetval))
+						BTC_SPRINTF(trace_buf,
+							    BT_TMP_BUF_SIZE,
+							"xxxxxx AntennaDetect(), Notify BT stop le tx by set_bt_trx_mask ok!\n");
+					else
+						BTC_SPRINTF(trace_buf,
+							    BT_TMP_BUF_SIZE,
+							"xxxxxx AntennaDetect(), Notify BT stop le tx by set_bt_trx_mask fail!\n");
+
+					BTC_TRACE(trace_buf);
+				} else
+					board_info->antdetval =
+						psd_scan->ant_det_psd_scan_peak_val/100;
+
+				board_info->btdm_ant_det_complete_fail = false;
+
+			} else {
+				BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+					"xxxxxxxxxxxxxxxx AntennaDetect(), Antenna Det Fail!!\n");
+				BTC_TRACE(trace_buf);
+
+				board_info->btdm_ant_det_complete_fail = true;
+			}
+
+			psd_scan->ant_det_inteval_count = 0;
+			psd_scan->is_AntDet_running = false;
+			/* stimulate coex running */
+			halbtc8723d1ant_run_coexist_mechanism(
+				btcoexist);
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				"xxxxxxxxxxxxxxxx AntennaDetect(), Stimulate Coex running\n!!");
+			BTC_TRACE(trace_buf);
+
+		} else {
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				"xxxxxxxxxxxxxxxx AntennaDetect(), Antenna Det Timer is not up! (%d)\n",
+				    psd_scan->ant_det_inteval_count);
+			BTC_TRACE(trace_buf);
+
+			if (psd_scan->ant_det_inteval_count == 8)
+				btcoexist->bdontenterLPS = true;
+			else
+				btcoexist->bdontenterLPS = false;
+		}
+
+	}
+#endif
+
+
+}
+
+
+void ex_halbtc8723d1ant_display_ant_detection(IN struct btc_coexist *btcoexist)
+{
+#if BT_8723D_1ANT_ANTDET_ENABLE
+	struct  btc_board_info	*board_info = &btcoexist->board_info;
+
+	if (psd_scan->ant_det_try_count != 0)	{
+		halbtc8723d1ant_psd_show_antenna_detect_result(btcoexist);
+
+		if (board_info->btdm_ant_det_finish)
+			halbtc8723d1ant_psd_showdata(btcoexist);
+	}
+#endif
+
+}
+
+void ex_halbtc8723d1ant_antenna_isolation(IN struct btc_coexist *btcoexist,
+		IN u32 cent_freq, IN u32 offset, IN u32 span, IN u32 seconds)
+{
+
+
+}
+
+void ex_halbtc8723d1ant_psd_scan(IN struct btc_coexist *btcoexist,
+		 IN u32 cent_freq, IN u32 offset, IN u32 span, IN u32 seconds)
+{
+
+
+}
+
+
+#endif
+
+#endif	/* #if (BT_SUPPORT == 1 && COEX_SUPPORT == 1) */
+
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/btc/halbtc8723d1ant.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/btc/halbtc8723d1ant.h
--- linux-5.6.3/3rdparty/rtl8821ce/hal/btc/halbtc8723d1ant.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/btc/halbtc8723d1ant.h	2020-04-10 16:35:06.782658480 +0300
@@ -0,0 +1,413 @@
+
+#if (BT_SUPPORT == 1 && COEX_SUPPORT == 1)
+
+#if (RTL8723D_SUPPORT == 1)
+
+/* *******************************************
+ * The following is for 8723D 1ANT BT Co-exist definition
+ * ******************************************* */
+#define	BT_8723D_1ANT_COEX_DBG					0
+#define	BT_AUTO_REPORT_ONLY_8723D_1ANT				1
+
+#define	BT_INFO_8723D_1ANT_B_FTP						BIT(7)
+#define	BT_INFO_8723D_1ANT_B_A2DP					BIT(6)
+#define	BT_INFO_8723D_1ANT_B_HID						BIT(5)
+#define	BT_INFO_8723D_1ANT_B_SCO_BUSY				BIT(4)
+#define	BT_INFO_8723D_1ANT_B_ACL_BUSY				BIT(3)
+#define	BT_INFO_8723D_1ANT_B_INQ_PAGE				BIT(2)
+#define	BT_INFO_8723D_1ANT_B_SCO_ESCO				BIT(1)
+#define	BT_INFO_8723D_1ANT_B_CONNECTION				BIT(0)
+
+#define	BT_INFO_8723D_1ANT_A2DP_BASIC_RATE(_BT_INFO_EXT_)	\
+	(((_BT_INFO_EXT_&BIT(0))) ? true : false)
+
+#define	BTC_RSSI_COEX_THRESH_TOL_8723D_1ANT		2
+
+#define  BT_8723D_1ANT_WIFI_NOISY_THRESH							30   /* max: 255 */
+#define  BT_8723D_1ANT_DEFAULT_ISOLATION						15	 /*  unit: dB */
+
+
+/* for Antenna detection */
+#define	BT_8723D_1ANT_ANTDET_PSDTHRES_BACKGROUND					50
+#define	BT_8723D_1ANT_ANTDET_PSDTHRES_2ANT_BADISOLATION				70
+#define	BT_8723D_1ANT_ANTDET_PSDTHRES_2ANT_GOODISOLATION			55
+#define	BT_8723D_1ANT_ANTDET_PSDTHRES_1ANT							35
+#define	BT_8723D_1ANT_ANTDET_RETRY_INTERVAL							10	/* retry timer if ant det is fail, unit: second */
+#define	BT_8723D_1ANT_ANTDET_SWEEPPOINT_DELAY							60000
+#define	BT_8723D_1ANT_ANTDET_ENABLE									1
+#define	BT_8723D_1ANT_ANTDET_BTTXTIME									100
+#define	BT_8723D_1ANT_ANTDET_BTTXCHANNEL								39
+#define	BT_8723D_1ANT_ANTDET_PSD_SWWEEPCOUNT						50
+
+#define	BT_8723D_1ANT_LTECOEX_INDIRECTREG_ACCESS_TIMEOUT		30000
+
+enum bt_8723d_1ant_signal_state {
+	BT_8723D_1ANT_SIG_STA_SET_TO_LOW		= 0x0,
+	BT_8723D_1ANT_SIG_STA_SET_BY_HW		= 0x0,
+	BT_8723D_1ANT_SIG_STA_SET_TO_HIGH		= 0x1,
+	BT_8723D_1ANT_SIG_STA_MAX
+};
+
+enum bt_8723d_1ant_path_ctrl_owner {
+	BT_8723D_1ANT_PCO_BTSIDE		= 0x0,
+	BT_8723D_1ANT_PCO_WLSIDE	= 0x1,
+	BT_8723D_1ANT_PCO_MAX
+};
+
+enum bt_8723d_1ant_gnt_ctrl_type {
+	BT_8723D_1ANT_GNT_TYPE_CTRL_BY_PTA		= 0x0,
+	BT_8723D_1ANT_GNT_TYPE_CTRL_BY_SW		= 0x1,
+	BT_8723D_1ANT_GNT_TYPE_MAX
+};
+
+enum bt_8723d_1ant_gnt_ctrl_block {
+	BT_8723D_1ANT_GNT_BLOCK_RFC_BB		= 0x0,
+	BT_8723D_1ANT_GNT_BLOCK_RFC			= 0x1,
+	BT_8723D_1ANT_GNT_BLOCK_BB			= 0x2,
+	BT_8723D_1ANT_GNT_BLOCK_MAX
+};
+
+enum bt_8723d_1ant_lte_coex_table_type {
+	BT_8723D_1ANT_CTT_WL_VS_LTE			= 0x0,
+	BT_8723D_1ANT_CTT_BT_VS_LTE			= 0x1,
+	BT_8723D_1ANT_CTT_MAX
+};
+
+enum bt_8723d_1ant_lte_break_table_type {
+	BT_8723D_1ANT_LBTT_WL_BREAK_LTE			= 0x0,
+	BT_8723D_1ANT_LBTT_BT_BREAK_LTE				= 0x1,
+	BT_8723D_1ANT_LBTT_LTE_BREAK_WL			= 0x2,
+	BT_8723D_1ANT_LBTT_LTE_BREAK_BT				= 0x3,
+	BT_8723D_1ANT_LBTT_MAX
+};
+
+enum bt_info_src_8723d_1ant {
+	BT_INFO_SRC_8723D_1ANT_WIFI_FW			= 0x0,
+	BT_INFO_SRC_8723D_1ANT_BT_RSP				= 0x1,
+	BT_INFO_SRC_8723D_1ANT_BT_ACTIVE_SEND		= 0x2,
+	BT_INFO_SRC_8723D_1ANT_MAX
+};
+
+enum bt_8723d_1ant_bt_status {
+	BT_8723D_1ANT_BT_STATUS_NON_CONNECTED_IDLE	= 0x0,
+	BT_8723D_1ANT_BT_STATUS_CONNECTED_IDLE		= 0x1,
+	BT_8723D_1ANT_BT_STATUS_INQ_PAGE				= 0x2,
+	BT_8723D_1ANT_BT_STATUS_ACL_BUSY				= 0x3,
+	BT_8723D_1ANT_BT_STATUS_SCO_BUSY				= 0x4,
+	BT_8723D_1ANT_BT_STATUS_ACL_SCO_BUSY			= 0x5,
+	BT_8723D_1ANT_BT_STATUS_MAX
+};
+
+enum bt_8723d_1ant_wifi_status {
+	BT_8723D_1ANT_WIFI_STATUS_NON_CONNECTED_IDLE				= 0x0,
+	BT_8723D_1ANT_WIFI_STATUS_NON_CONNECTED_ASSO_AUTH_SCAN		= 0x1,
+	BT_8723D_1ANT_WIFI_STATUS_CONNECTED_SCAN					= 0x2,
+	BT_8723D_1ANT_WIFI_STATUS_CONNECTED_SPECIFIC_PKT				= 0x3,
+	BT_8723D_1ANT_WIFI_STATUS_CONNECTED_IDLE					= 0x4,
+	BT_8723D_1ANT_WIFI_STATUS_CONNECTED_BUSY					= 0x5,
+	BT_8723D_1ANT_WIFI_STATUS_MAX
+};
+
+enum bt_8723d_1ant_coex_algo {
+	BT_8723D_1ANT_COEX_ALGO_UNDEFINED			= 0x0,
+	BT_8723D_1ANT_COEX_ALGO_SCO				= 0x1,
+	BT_8723D_1ANT_COEX_ALGO_HID				= 0x2,
+	BT_8723D_1ANT_COEX_ALGO_A2DP				= 0x3,
+	BT_8723D_1ANT_COEX_ALGO_A2DP_PANHS		= 0x4,
+	BT_8723D_1ANT_COEX_ALGO_PANEDR			= 0x5,
+	BT_8723D_1ANT_COEX_ALGO_PANHS			= 0x6,
+	BT_8723D_1ANT_COEX_ALGO_PANEDR_A2DP		= 0x7,
+	BT_8723D_1ANT_COEX_ALGO_PANEDR_HID		= 0x8,
+	BT_8723D_1ANT_COEX_ALGO_HID_A2DP_PANEDR	= 0x9,
+	BT_8723D_1ANT_COEX_ALGO_HID_A2DP			= 0xa,
+	BT_8723D_1ANT_COEX_ALGO_MAX				= 0xb,
+};
+
+enum bt_8723d_1ant_phase {
+	BT_8723D_1ANT_PHASE_COEX_INIT								= 0x0,
+	BT_8723D_1ANT_PHASE_WLANONLY_INIT							= 0x1,
+	BT_8723D_1ANT_PHASE_WLAN_OFF								= 0x2,
+	BT_8723D_1ANT_PHASE_2G_RUNTIME								= 0x3,
+	BT_8723D_1ANT_PHASE_5G_RUNTIME								= 0x4,
+	BT_8723D_1ANT_PHASE_BTMPMODE								= 0x5,
+	BT_8723D_1ANT_PHASE_ANTENNA_DET								= 0x6,
+	BT_8723D_1ANT_PHASE_COEX_POWERON							= 0x7,
+	BT_8723D_1ANT_PHASE_MAX
+};
+
+enum bt_8723d_1ant_Scoreboard {
+	BT_8723D_1ANT_SCOREBOARD_ACTIVE								= BIT(0),
+	BT_8723D_1ANT_SCOREBOARD_ONOFF								= BIT(1),
+	BT_8723D_1ANT_SCOREBOARD_SCAN								= BIT(2),
+	BT_8723D_1ANT_SCOREBOARD_UNDERTEST							= BIT(3),
+	BT_8723D_1ANT_SCOREBOARD_WLBUSY								= BIT(6)
+};
+
+struct coex_dm_8723d_1ant {
+	/* hw setting */
+	u8		pre_ant_pos_type;
+	u8		cur_ant_pos_type;
+	/* fw mechanism */
+	boolean		cur_ignore_wlan_act;
+	boolean		pre_ignore_wlan_act;
+	u8		pre_ps_tdma;
+	u8		cur_ps_tdma;
+	u8		ps_tdma_para[5];
+	u8		ps_tdma_du_adj_type;
+	boolean		pre_ps_tdma_on;
+	boolean		cur_ps_tdma_on;
+	boolean		pre_bt_auto_report;
+	boolean		cur_bt_auto_report;
+	u8		pre_lps;
+	u8		cur_lps;
+	u8		pre_rpwm;
+	u8		cur_rpwm;
+
+	/* sw mechanism */
+	boolean	pre_low_penalty_ra;
+	boolean		cur_low_penalty_ra;
+	u32		pre_val0x6c0;
+	u32		cur_val0x6c0;
+	u32		pre_val0x6c4;
+	u32		cur_val0x6c4;
+	u32		pre_val0x6c8;
+	u32		cur_val0x6c8;
+	u8		pre_val0x6cc;
+	u8		cur_val0x6cc;
+	boolean		limited_dig;
+
+	u32		backup_arfr_cnt1;	/* Auto Rate Fallback Retry cnt */
+	u32		backup_arfr_cnt2;	/* Auto Rate Fallback Retry cnt */
+	u16		backup_retry_limit;
+	u8		backup_ampdu_max_time;
+
+	/* algorithm related */
+	u8		pre_algorithm;
+	u8		cur_algorithm;
+	u8		bt_status;
+	u8		wifi_chnl_info[3];
+
+	u32		pre_ra_mask;
+	u32		cur_ra_mask;
+	u8		pre_arfr_type;
+	u8		cur_arfr_type;
+	u8		pre_retry_limit_type;
+	u8		cur_retry_limit_type;
+	u8		pre_ampdu_time_type;
+	u8		cur_ampdu_time_type;
+	u32		arp_cnt;
+
+	u8		error_condition;
+};
+
+struct coex_sta_8723d_1ant {
+	boolean				bt_disabled;
+	boolean				bt_link_exist;
+	boolean				sco_exist;
+	boolean				a2dp_exist;
+	boolean				hid_exist;
+	boolean				pan_exist;
+	boolean				bt_hi_pri_link_exist;
+	u8					num_of_profile;
+
+	boolean				under_lps;
+	boolean				under_ips;
+	u32					specific_pkt_period_cnt;
+	u32					high_priority_tx;
+	u32					high_priority_rx;
+	u32					low_priority_tx;
+	u32					low_priority_rx;
+	boolean             is_hiPri_rx_overhead;
+	s8					bt_rssi;
+	boolean				bt_tx_rx_mask;
+	u8					pre_bt_rssi_state;
+	u8					pre_wifi_rssi_state[4];
+	u8					bt_info_c2h[BT_INFO_SRC_8723D_1ANT_MAX][10];
+	u32					bt_info_c2h_cnt[BT_INFO_SRC_8723D_1ANT_MAX];
+	boolean				bt_whck_test;
+	boolean				c2h_bt_inquiry_page;
+	boolean				c2h_bt_remote_name_req;
+	boolean				c2h_bt_page;				/* Add for win8.1 page out issue */
+	boolean				wifi_is_high_pri_task;		/* Add for win8.1 page out issue */
+	u8					bt_retry_cnt;
+	u8					bt_info_ext;
+	u8					bt_info_ext2;
+	u32					pop_event_cnt;
+	u8					scan_ap_num;
+
+	u32					crc_ok_cck;
+	u32					crc_ok_11g;
+	u32					crc_ok_11n;
+	u32					crc_ok_11n_vht;
+
+	u32					crc_err_cck;
+	u32					crc_err_11g;
+	u32					crc_err_11n;
+	u32					crc_err_11n_vht;
+
+	boolean				cck_lock;
+	boolean				pre_ccklock;
+	boolean				cck_ever_lock;
+	u8					coex_table_type;
+
+	boolean				force_lps_on;
+
+	boolean				concurrent_rx_mode_on;
+
+	u16					score_board;
+	u8					isolation_btween_wb;   /* 0~ 50 */
+
+	u8					a2dp_bit_pool;
+	u8					cut_version;
+	boolean				acl_busy;
+	boolean				bt_create_connection;
+
+	u32					bt_coex_supported_feature;
+	u32					bt_coex_supported_version;
+
+	u8					bt_ble_scan_type;
+	u32					bt_ble_scan_para[3];
+
+	boolean				run_time_state;
+	boolean				freeze_coexrun_by_btinfo;
+
+	boolean				is_A2DP_3M;
+	boolean				voice_over_HOGP;
+	u8                  bt_info;
+	boolean				is_autoslot;
+	u8					forbidden_slot;
+	u8					hid_busy_num;
+	u8					hid_pair_cnt;
+
+	u32					cnt_RemoteNameReq;
+	u32					cnt_setupLink;
+	u32					cnt_ReInit;
+	u32					cnt_IgnWlanAct;
+	u32					cnt_Page;
+	u32					cnt_RoleSwitch;
+
+	u16					bt_reg_vendor_ac;
+	u16					bt_reg_vendor_ae;
+
+	boolean				is_setupLink;
+	u8					wl_noisy_level;
+	u32                 gnt_error_cnt;
+
+	u8					bt_afh_map[10];
+	u8					bt_relink_downcount;
+	boolean				is_tdma_btautoslot;
+	boolean				is_tdma_btautoslot_hang;
+};
+
+#define  BT_8723D_1ANT_ANTDET_PSD_POINTS			256	/* MAX:1024 */
+#define  BT_8723D_1ANT_ANTDET_PSD_AVGNUM			1	/* MAX:3 */
+#define	BT_8723D_1ANT_ANTDET_BUF_LEN				16
+
+struct psdscan_sta_8723d_1ant {
+
+	u32			ant_det_bt_le_channel;  /* BT LE Channel ex:2412 */
+	u32			ant_det_bt_tx_time;
+	u32			ant_det_pre_psdscan_peak_val;
+	boolean			ant_det_is_ant_det_available;
+	u32			ant_det_psd_scan_peak_val;
+	boolean			ant_det_is_btreply_available;
+	u32			ant_det_psd_scan_peak_freq;
+
+	u8			ant_det_result;
+	u8			ant_det_peak_val[BT_8723D_1ANT_ANTDET_BUF_LEN];
+	u8			ant_det_peak_freq[BT_8723D_1ANT_ANTDET_BUF_LEN];
+	u32			ant_det_try_count;
+	u32			ant_det_fail_count;
+	u32			ant_det_inteval_count;
+	u32			ant_det_thres_offset;
+
+	u32			real_cent_freq;
+	s32			real_offset;
+	u32			real_span;
+
+	u32			psd_band_width;  /* unit: Hz */
+	u32			psd_point;		/* 128/256/512/1024 */
+	u32			psd_report[1024];  /* unit:dB (20logx), 0~255 */
+	u32			psd_report_max_hold[1024];  /* unit:dB (20logx), 0~255 */
+	u32			psd_start_point;
+	u32			psd_stop_point;
+	u32			psd_max_value_point;
+	u32			psd_max_value;
+	u32			psd_max_value2;
+	u32			psd_avg_value;   /* filter loop_max_value that below BT_8723D_1ANT_ANTDET_PSDTHRES_1ANT, and average the rest*/
+	u32			psd_loop_max_value[BT_8723D_1ANT_ANTDET_PSD_SWWEEPCOUNT];  /*max value in each loop */
+	u32			psd_start_base;
+	u32			psd_avg_num;	/* 1/8/16/32 */
+	u32			psd_gen_count;
+	boolean			is_AntDet_running;
+	boolean			is_psd_show_max_only;
+};
+
+/* *******************************************
+ * The following is interface which will notify coex module.
+ * ******************************************* */
+void ex_halbtc8723d1ant_power_on_setting(IN struct btc_coexist *btcoexist);
+void ex_halbtc8723d1ant_pre_load_firmware(IN struct btc_coexist *btcoexist);
+void ex_halbtc8723d1ant_init_hw_config(IN struct btc_coexist *btcoexist,
+				       IN boolean wifi_only);
+void ex_halbtc8723d1ant_init_coex_dm(IN struct btc_coexist *btcoexist);
+void ex_halbtc8723d1ant_ips_notify(IN struct btc_coexist *btcoexist,
+				   IN u8 type);
+void ex_halbtc8723d1ant_lps_notify(IN struct btc_coexist *btcoexist,
+				   IN u8 type);
+void ex_halbtc8723d1ant_scan_notify(IN struct btc_coexist *btcoexist,
+				    IN u8 type);
+void ex_halbtc8723d1ant_connect_notify(IN struct btc_coexist *btcoexist,
+				       IN u8 type);
+void ex_halbtc8723d1ant_media_status_notify(IN struct btc_coexist *btcoexist,
+		IN u8 type);
+void ex_halbtc8723d1ant_specific_packet_notify(IN struct btc_coexist *btcoexist,
+		IN u8 type);
+void ex_halbtc8723d1ant_bt_info_notify(IN struct btc_coexist *btcoexist,
+				       IN u8 *tmp_buf, IN u8 length);
+void ex_halbtc8723d1ant_rf_status_notify(IN struct btc_coexist *btcoexist,
+		IN u8 type);
+void ex_halbtc8723d1ant_halt_notify(IN struct btc_coexist *btcoexist);
+void ex_halbtc8723d1ant_pnp_notify(IN struct btc_coexist *btcoexist,
+				   IN u8 pnp_state);
+void ex_halbtc8723d1ant_coex_dm_reset(IN struct btc_coexist *btcoexist);
+void ex_halbtc8723d1ant_periodical(IN struct btc_coexist *btcoexist);
+void ex_halbtc8723d1ant_set_antenna_notify(IN struct btc_coexist *btcoexist,
+		IN u8 type);
+void ex_halbtc8723d1ant_display_coex_info(IN struct btc_coexist *btcoexist);
+void ex_halbtc8723d1ant_antenna_detection(IN struct btc_coexist *btcoexist,
+		IN u32 cent_freq, IN u32 offset, IN u32 span, IN u32 seconds);
+void ex_halbtc8723d1ant_antenna_isolation(IN struct btc_coexist *btcoexist,
+		IN u32 cent_freq, IN u32 offset, IN u32 span, IN u32 seconds);
+
+void ex_halbtc8723d1ant_psd_scan(IN struct btc_coexist *btcoexist,
+		 IN u32 cent_freq, IN u32 offset, IN u32 span, IN u32 seconds);
+void ex_halbtc8723d1ant_display_ant_detection(IN struct btc_coexist *btcoexist);
+
+#else
+#define	ex_halbtc8723d1ant_power_on_setting(btcoexist)
+#define	ex_halbtc8723d1ant_pre_load_firmware(btcoexist)
+#define	ex_halbtc8723d1ant_init_hw_config(btcoexist, wifi_only)
+#define	ex_halbtc8723d1ant_init_coex_dm(btcoexist)
+#define	ex_halbtc8723d1ant_ips_notify(btcoexist, type)
+#define	ex_halbtc8723d1ant_lps_notify(btcoexist, type)
+#define	ex_halbtc8723d1ant_scan_notify(btcoexist, type)
+#define	ex_halbtc8723d1ant_connect_notify(btcoexist, type)
+#define	ex_halbtc8723d1ant_media_status_notify(btcoexist, type)
+#define	ex_halbtc8723d1ant_specific_packet_notify(btcoexist, type)
+#define	ex_halbtc8723d1ant_bt_info_notify(btcoexist, tmp_buf, length)
+#define	ex_halbtc8723d1ant_rf_status_notify(btcoexist, type)
+#define	ex_halbtc8723d1ant_halt_notify(btcoexist)
+#define	ex_halbtc8723d1ant_pnp_notify(btcoexist, pnp_state)
+#define	ex_halbtc8723d1ant_coex_dm_reset(btcoexist)
+#define	ex_halbtc8723d1ant_periodical(btcoexist)
+#define	ex_halbtc8723d1ant_display_coex_info(btcoexist)
+#define	ex_halbtc8723d1ant_set_antenna_notify(btcoexist, type)
+#define	ex_halbtc8723d1ant_antenna_detection(btcoexist, cent_freq, offset, span, seconds)
+#define	ex_halbtc8723d1ant_antenna_isolation(btcoexist, cent_freq, offset, span, seconds)
+#define	ex_halbtc8723d1ant_psd_scan(btcoexist, cent_freq, offset, span, seconds)
+#define	ex_halbtc8723d1ant_display_ant_detection(btcoexist)
+#endif
+
+#endif
+
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/btc/halbtc8723d2ant.c linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/btc/halbtc8723d2ant.c
--- linux-5.6.3/3rdparty/rtl8821ce/hal/btc/halbtc8723d2ant.c	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/btc/halbtc8723d2ant.c	2020-04-10 16:35:06.783658527 +0300
@@ -0,0 +1,6838 @@
+/* ************************************************************
+ * Description:
+ *
+ * This file is for RTL8723D Co-exist mechanism
+ *
+ * History
+ * 2012/11/15 Cosa first check in.
+ *
+ * ************************************************************ */
+
+/* ************************************************************
+ * include files
+ * ************************************************************ */
+#include "mp_precomp.h"
+
+#if (BT_SUPPORT == 1 && COEX_SUPPORT == 1)
+
+#if (RTL8723D_SUPPORT == 1)
+/* ************************************************************
+ * Global variables, these are static variables
+ * ************************************************************ */
+static u8	*trace_buf = &gl_btc_trace_buf[0];
+static struct  coex_dm_8723d_2ant		glcoex_dm_8723d_2ant;
+static struct  coex_dm_8723d_2ant	*coex_dm = &glcoex_dm_8723d_2ant;
+static struct  coex_sta_8723d_2ant		glcoex_sta_8723d_2ant;
+static struct  coex_sta_8723d_2ant	*coex_sta = &glcoex_sta_8723d_2ant;
+static struct  psdscan_sta_8723d_2ant	gl_psd_scan_8723d_2ant;
+static struct  psdscan_sta_8723d_2ant *psd_scan = &gl_psd_scan_8723d_2ant;
+
+const char *const glbt_info_src_8723d_2ant[] = {
+	"BT Info[wifi fw]",
+	"BT Info[bt rsp]",
+	"BT Info[bt auto report]",
+};
+/* ************************************************************
+ * BtCoex Version Format:
+ * 1. date :			glcoex_ver_date_XXXXX_1ant
+ * 2. WifiCoexVersion : glcoex_ver_XXXX_1ant
+ * 3. BtCoexVersion :	glcoex_ver_btdesired_XXXXX_1ant
+ * 4. others :			glcoex_ver_XXXXXX_XXXXX_1ant
+ *
+ * Variable should be indicated IC and Antenna numbers !!!
+ * Please strictly follow this order and naming style !!!
+ *
+ * ************************************************************ */
+u32	glcoex_ver_date_8723d_2ant = 20161220;
+u32	glcoex_ver_8723d_2ant = 0x13;
+u32 glcoex_ver_btdesired_8723d_2ant = 0x10;
+
+
+/* ************************************************************
+ * local function proto type if needed
+ * ************************************************************
+ * ************************************************************
+ * local function start with halbtc8723d2ant_
+ * ************************************************************ */
+u8 halbtc8723d2ant_bt_rssi_state(u8 *ppre_bt_rssi_state, u8 level_num,
+				 u8 rssi_thresh, u8 rssi_thresh1)
+{
+	s32			bt_rssi = 0;
+	u8			bt_rssi_state = *ppre_bt_rssi_state;
+
+	bt_rssi = coex_sta->bt_rssi;
+
+	if (level_num == 2) {
+		if ((*ppre_bt_rssi_state == BTC_RSSI_STATE_LOW) ||
+		    (*ppre_bt_rssi_state == BTC_RSSI_STATE_STAY_LOW)) {
+			if (bt_rssi >= (rssi_thresh +
+					BTC_RSSI_COEX_THRESH_TOL_8723D_2ANT))
+				bt_rssi_state = BTC_RSSI_STATE_HIGH;
+			else
+				bt_rssi_state = BTC_RSSI_STATE_STAY_LOW;
+		} else {
+			if (bt_rssi < rssi_thresh)
+				bt_rssi_state = BTC_RSSI_STATE_LOW;
+			else
+				bt_rssi_state = BTC_RSSI_STATE_STAY_HIGH;
+		}
+	} else if (level_num == 3) {
+		if (rssi_thresh > rssi_thresh1) {
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				    "[BTCoex], BT Rssi thresh error!!\n");
+			BTC_TRACE(trace_buf);
+			return *ppre_bt_rssi_state;
+		}
+
+		if ((*ppre_bt_rssi_state == BTC_RSSI_STATE_LOW) ||
+		    (*ppre_bt_rssi_state == BTC_RSSI_STATE_STAY_LOW)) {
+			if (bt_rssi >= (rssi_thresh +
+					BTC_RSSI_COEX_THRESH_TOL_8723D_2ANT))
+				bt_rssi_state = BTC_RSSI_STATE_MEDIUM;
+			else
+				bt_rssi_state = BTC_RSSI_STATE_STAY_LOW;
+		} else if ((*ppre_bt_rssi_state == BTC_RSSI_STATE_MEDIUM) ||
+			(*ppre_bt_rssi_state == BTC_RSSI_STATE_STAY_MEDIUM)) {
+			if (bt_rssi >= (rssi_thresh1 +
+					BTC_RSSI_COEX_THRESH_TOL_8723D_2ANT))
+				bt_rssi_state = BTC_RSSI_STATE_HIGH;
+			else if (bt_rssi < rssi_thresh)
+				bt_rssi_state = BTC_RSSI_STATE_LOW;
+			else
+				bt_rssi_state = BTC_RSSI_STATE_STAY_MEDIUM;
+		} else {
+			if (bt_rssi < rssi_thresh1)
+				bt_rssi_state = BTC_RSSI_STATE_MEDIUM;
+			else
+				bt_rssi_state = BTC_RSSI_STATE_STAY_HIGH;
+		}
+	}
+
+	*ppre_bt_rssi_state = bt_rssi_state;
+
+	return bt_rssi_state;
+}
+
+u8 halbtc8723d2ant_wifi_rssi_state(IN struct btc_coexist *btcoexist,
+	   IN u8 *pprewifi_rssi_state, IN u8 level_num, IN u8 rssi_thresh,
+				   IN u8 rssi_thresh1)
+{
+	s32			wifi_rssi = 0;
+	u8			wifi_rssi_state = *pprewifi_rssi_state;
+
+	btcoexist->btc_get(btcoexist, BTC_GET_S4_WIFI_RSSI, &wifi_rssi);
+
+	if (level_num == 2) {
+		if ((*pprewifi_rssi_state == BTC_RSSI_STATE_LOW) ||
+		    (*pprewifi_rssi_state == BTC_RSSI_STATE_STAY_LOW)) {
+			if (wifi_rssi >= (rssi_thresh +
+					  BTC_RSSI_COEX_THRESH_TOL_8723D_2ANT))
+				wifi_rssi_state = BTC_RSSI_STATE_HIGH;
+			else
+				wifi_rssi_state = BTC_RSSI_STATE_STAY_LOW;
+		} else {
+			if (wifi_rssi < rssi_thresh)
+				wifi_rssi_state = BTC_RSSI_STATE_LOW;
+			else
+				wifi_rssi_state = BTC_RSSI_STATE_STAY_HIGH;
+		}
+	} else if (level_num == 3) {
+		if (rssi_thresh > rssi_thresh1) {
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				    "[BTCoex], wifi RSSI thresh error!!\n");
+			BTC_TRACE(trace_buf);
+			return *pprewifi_rssi_state;
+		}
+
+		if ((*pprewifi_rssi_state == BTC_RSSI_STATE_LOW) ||
+		    (*pprewifi_rssi_state == BTC_RSSI_STATE_STAY_LOW)) {
+			if (wifi_rssi >= (rssi_thresh +
+					  BTC_RSSI_COEX_THRESH_TOL_8723D_2ANT))
+				wifi_rssi_state = BTC_RSSI_STATE_MEDIUM;
+			else
+				wifi_rssi_state = BTC_RSSI_STATE_STAY_LOW;
+		} else if ((*pprewifi_rssi_state == BTC_RSSI_STATE_MEDIUM) ||
+			(*pprewifi_rssi_state == BTC_RSSI_STATE_STAY_MEDIUM)) {
+			if (wifi_rssi >= (rssi_thresh1 +
+					  BTC_RSSI_COEX_THRESH_TOL_8723D_2ANT))
+				wifi_rssi_state = BTC_RSSI_STATE_HIGH;
+			else if (wifi_rssi < rssi_thresh)
+				wifi_rssi_state = BTC_RSSI_STATE_LOW;
+			else
+				wifi_rssi_state = BTC_RSSI_STATE_STAY_MEDIUM;
+		} else {
+			if (wifi_rssi < rssi_thresh1)
+				wifi_rssi_state = BTC_RSSI_STATE_MEDIUM;
+			else
+				wifi_rssi_state = BTC_RSSI_STATE_STAY_HIGH;
+		}
+	}
+
+	*pprewifi_rssi_state = wifi_rssi_state;
+
+	return wifi_rssi_state;
+}
+
+void halbtc8723d2ant_coex_switch_threshold(IN struct btc_coexist *btcoexist,
+		IN u8 isolation_measuared)
+{
+	s8	interference_wl_tx = 0, interference_bt_tx = 0;
+
+
+	interference_wl_tx = BT_8723D_2ANT_WIFI_MAX_TX_POWER -
+			     isolation_measuared;
+	interference_bt_tx = BT_8723D_2ANT_BT_MAX_TX_POWER -
+			     isolation_measuared;
+
+
+
+	coex_sta->wifi_coex_thres		 = BT_8723D_2ANT_WIFI_RSSI_COEXSWITCH_THRES1;
+	coex_sta->wifi_coex_thres2	 = BT_8723D_2ANT_WIFI_RSSI_COEXSWITCH_THRES2;
+
+	coex_sta->bt_coex_thres		 = BT_8723D_2ANT_BT_RSSI_COEXSWITCH_THRES1;
+	coex_sta->bt_coex_thres2		 = BT_8723D_2ANT_BT_RSSI_COEXSWITCH_THRES2;
+
+
+	/*
+		coex_sta->wifi_coex_thres		= interference_wl_tx + BT_8723D_2ANT_WIFI_SIR_THRES1;
+		coex_sta->wifi_coex_thres2		= interference_wl_tx + BT_8723D_2ANT_WIFI_SIR_THRES2;
+
+		coex_sta->bt_coex_thres		= interference_bt_tx + BT_8723D_2ANT_BT_SIR_THRES1;
+		coex_sta->bt_coex_thres2		= interference_bt_tx + BT_8723D_2ANT_BT_SIR_THRES2;
+	*/
+
+
+
+
+
+	/*
+		if  ( BT_8723D_2ANT_WIFI_RSSI_COEXSWITCH_THRES1 < (isolation_measuared -
+					BT_8723D_2ANT_DEFAULT_ISOLATION) )
+			coex_sta->wifi_coex_thres	 = BT_8723D_2ANT_WIFI_RSSI_COEXSWITCH_THRES1;
+		else
+			coex_sta->wifi_coex_thres =  BT_8723D_2ANT_WIFI_RSSI_COEXSWITCH_THRES1 -  (isolation_measuared -
+					BT_8723D_2ANT_DEFAULT_ISOLATION);
+
+		if  ( BT_8723D_2ANT_BT_RSSI_COEXSWITCH_THRES1 < (isolation_measuared -
+					BT_8723D_2ANT_DEFAULT_ISOLATION) )
+			coex_sta->bt_coex_thres	 = BT_8723D_2ANT_BT_RSSI_COEXSWITCH_THRES1;
+		else
+			coex_sta->bt_coex_thres =  BT_8723D_2ANT_BT_RSSI_COEXSWITCH_THRES1 -  (isolation_measuared -
+					BT_8723D_2ANT_DEFAULT_ISOLATION);
+
+	*/
+}
+
+
+void halbtc8723d2ant_limited_rx(IN struct btc_coexist *btcoexist,
+			IN boolean force_exec, IN boolean rej_ap_agg_pkt,
+			IN boolean bt_ctrl_agg_buf_size, IN u8 agg_buf_size)
+{
+	boolean	reject_rx_agg = rej_ap_agg_pkt;
+	boolean	bt_ctrl_rx_agg_size = bt_ctrl_agg_buf_size;
+	u8	rx_agg_size = agg_buf_size;
+
+	/* ============================================ */
+	/*	Rx Aggregation related setting */
+	/* ============================================ */
+	btcoexist->btc_set(btcoexist, BTC_SET_BL_TO_REJ_AP_AGG_PKT,
+			   &reject_rx_agg);
+	/* decide BT control aggregation buf size or not */
+	btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_CTRL_AGG_SIZE,
+			   &bt_ctrl_rx_agg_size);
+	/* aggregation buf size, only work when BT control Rx aggregation size. */
+	btcoexist->btc_set(btcoexist, BTC_SET_U1_AGG_BUF_SIZE, &rx_agg_size);
+	/* real update aggregation setting */
+	btcoexist->btc_set(btcoexist, BTC_SET_ACT_AGGREGATE_CTRL, NULL);
+}
+
+void halbtc8723d2ant_query_bt_info(IN struct btc_coexist *btcoexist)
+{
+	u8			h2c_parameter[1] = {0};
+
+
+	h2c_parameter[0] |= BIT(0);	/* trigger */
+
+	btcoexist->btc_fill_h2c(btcoexist, 0x61, 1, h2c_parameter);
+}
+
+void halbtc8723d2ant_monitor_bt_ctr(IN struct btc_coexist *btcoexist)
+{
+	u32			reg_hp_txrx, reg_lp_txrx, u32tmp;
+	u32			reg_hp_tx = 0, reg_hp_rx = 0, reg_lp_tx = 0, reg_lp_rx = 0;
+	static u8		num_of_bt_counter_chk = 0, cnt_slave = 0, cnt_overhead = 0,
+				cnt_autoslot_hang = 0;
+
+	struct  btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
+
+	reg_hp_txrx = 0x770;
+	reg_lp_txrx = 0x774;
+
+	u32tmp = btcoexist->btc_read_4byte(btcoexist, reg_hp_txrx);
+	reg_hp_tx = u32tmp & MASKLWORD;
+	reg_hp_rx = (u32tmp & MASKHWORD) >> 16;
+
+	u32tmp = btcoexist->btc_read_4byte(btcoexist, reg_lp_txrx);
+	reg_lp_tx = u32tmp & MASKLWORD;
+	reg_lp_rx = (u32tmp & MASKHWORD) >> 16;
+
+	coex_sta->high_priority_tx = reg_hp_tx;
+	coex_sta->high_priority_rx = reg_hp_rx;
+	coex_sta->low_priority_tx = reg_lp_tx;
+	coex_sta->low_priority_rx = reg_lp_rx;
+
+	if (BT_8723D_2ANT_BT_STATUS_NON_CONNECTED_IDLE ==
+		coex_dm->bt_status) {
+
+			if (coex_sta->high_priority_rx >= 15) {
+					if (cnt_overhead < 3)
+						cnt_overhead++;
+
+					if (cnt_overhead == 3)
+						coex_sta->is_hiPri_rx_overhead = true;
+			 } else {
+					if (cnt_overhead > 0)
+						cnt_overhead--;
+
+					if (cnt_overhead == 0)
+						coex_sta->is_hiPri_rx_overhead = false;
+			}
+	} else
+		coex_sta->is_hiPri_rx_overhead = false;
+
+	/* reset counter */
+	btcoexist->btc_write_1byte(btcoexist, 0x76e, 0xc);
+
+	if ((coex_sta->low_priority_tx > 1050)  &&
+	    (!coex_sta->c2h_bt_inquiry_page))
+		coex_sta->pop_event_cnt++;
+
+	if ((coex_sta->low_priority_rx >= 950) &&
+	    (coex_sta->low_priority_rx >= coex_sta->low_priority_tx)
+	    && (!coex_sta->under_ips)  && (!coex_sta->c2h_bt_inquiry_page) &&
+	    (coex_sta->bt_link_exist))	{
+		if (cnt_slave >= 2) {
+			bt_link_info->slave_role = true;
+			cnt_slave = 2;
+		} else
+			cnt_slave++;
+	} else {
+		if (cnt_slave == 0)	{
+			bt_link_info->slave_role = false;
+			cnt_slave = 0;
+		} else
+			cnt_slave--;
+
+	}
+
+	if (coex_sta->is_tdma_btautoslot) {
+		if ((coex_sta->low_priority_tx >= 1300) &&
+			(coex_sta->low_priority_rx <= 150)) {
+			if (cnt_autoslot_hang >= 2) {
+				coex_sta->is_tdma_btautoslot_hang = true;
+				cnt_autoslot_hang = 2;
+			} else
+				cnt_autoslot_hang++;
+		} else {
+			if (cnt_autoslot_hang == 0)	{
+				coex_sta->is_tdma_btautoslot_hang = false;
+				cnt_autoslot_hang = 0;
+			} else
+				cnt_autoslot_hang--;
+		}
+	}
+
+	if (coex_sta->sco_exist) {
+		if ((coex_sta->high_priority_tx >= 400) &&
+		(coex_sta->high_priority_rx >= 400))
+			coex_sta->is_eSCO_mode = false;
+		else
+			coex_sta->is_eSCO_mode = true;
+	}
+
+	if (!coex_sta->bt_disabled) {
+
+		if ((coex_sta->high_priority_tx == 0) &&
+		    (coex_sta->high_priority_rx == 0) &&
+		    (coex_sta->low_priority_tx == 0) &&
+		    (coex_sta->low_priority_rx == 0)) {
+			num_of_bt_counter_chk++;
+			if (num_of_bt_counter_chk >= 3) {
+				halbtc8723d2ant_query_bt_info(btcoexist);
+				num_of_bt_counter_chk = 0;
+			}
+		}
+	}
+
+}
+
+void halbtc8723d2ant_monitor_wifi_ctr(IN struct btc_coexist *btcoexist)
+{
+#if 1
+		s32 wifi_rssi = 0;
+		boolean wifi_busy = false, wifi_under_b_mode = false,
+				wifi_scan = false;
+		boolean bt_idle = false, wl_idle = false;
+		static u8 cck_lock_counter = 0, wl_noisy_count0 = 0,
+				wl_noisy_count1 = 3, wl_noisy_count2 = 0;
+		u32 total_cnt, reg_val1, reg_val2, cck_cnt;
+
+		btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy);
+		btcoexist->btc_get(btcoexist, BTC_GET_S4_WIFI_RSSI, &wifi_rssi);
+		btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_B_MODE,
+				   &wifi_under_b_mode);
+
+		coex_sta->crc_ok_cck = btcoexist->btc_phydm_query_PHY_counter(
+								btcoexist, PHYDM_INFO_CRC32_OK_CCK);
+		coex_sta->crc_ok_11g = btcoexist->btc_phydm_query_PHY_counter(
+								btcoexist, PHYDM_INFO_CRC32_OK_LEGACY);
+		coex_sta->crc_ok_11n = btcoexist->btc_phydm_query_PHY_counter(
+								btcoexist, PHYDM_INFO_CRC32_OK_HT);
+		coex_sta->crc_ok_11n_vht = btcoexist->btc_phydm_query_PHY_counter(
+								btcoexist, PHYDM_INFO_CRC32_OK_VHT);
+
+		coex_sta->crc_err_cck = btcoexist->btc_phydm_query_PHY_counter(
+								btcoexist, PHYDM_INFO_CRC32_ERROR_CCK);
+		coex_sta->crc_err_11g =  btcoexist->btc_phydm_query_PHY_counter(
+								btcoexist, PHYDM_INFO_CRC32_ERROR_LEGACY);
+		coex_sta->crc_err_11n = btcoexist->btc_phydm_query_PHY_counter(
+								btcoexist, PHYDM_INFO_CRC32_ERROR_HT);
+		coex_sta->crc_err_11n_vht = btcoexist->btc_phydm_query_PHY_counter(
+								btcoexist, PHYDM_INFO_CRC32_ERROR_VHT);
+
+		cck_cnt = coex_sta->crc_ok_cck + coex_sta->crc_err_cck;
+
+		if (cck_cnt > 250) {
+			if (wl_noisy_count2 < 3)
+				wl_noisy_count2++;
+
+			if (wl_noisy_count2 == 3) {
+				wl_noisy_count0 = 0;
+				wl_noisy_count1 = 0;
+			}
+		} else if (cck_cnt < 50) {
+			if (wl_noisy_count0 < 3)
+				wl_noisy_count0++;
+
+			if (wl_noisy_count0 == 3) {
+				wl_noisy_count1 = 0;
+				wl_noisy_count2 = 0;
+			}
+		} else {
+			if (wl_noisy_count1 < 3)
+				wl_noisy_count1++;
+
+			if (wl_noisy_count1 == 3) {
+				wl_noisy_count0 = 0;
+				wl_noisy_count2 = 0;
+			}
+		}
+
+		if (wl_noisy_count2 == 3)
+			coex_sta->wl_noisy_level = 2;
+		else if (wl_noisy_count1 == 3)
+			coex_sta->wl_noisy_level = 1;
+		else
+			coex_sta->wl_noisy_level = 0;
+
+		if ((wifi_busy) && (wifi_rssi >= 30) && (!wifi_under_b_mode)) {
+			total_cnt = coex_sta->crc_ok_cck + coex_sta->crc_ok_11g +
+					coex_sta->crc_ok_11n + coex_sta->crc_ok_11n_vht;
+
+			if ((coex_dm->bt_status == BT_8723D_2ANT_BT_STATUS_ACL_BUSY) ||
+				(coex_dm->bt_status == BT_8723D_2ANT_BT_STATUS_ACL_SCO_BUSY) ||
+				(coex_dm->bt_status == BT_8723D_2ANT_BT_STATUS_SCO_BUSY)) {
+				if (coex_sta->crc_ok_cck > (total_cnt -
+								coex_sta->crc_ok_cck)) {
+					if (cck_lock_counter < 3)
+						cck_lock_counter++;
+				} else {
+					if (cck_lock_counter > 0)
+						cck_lock_counter--;
+				}
+
+			} else {
+				if (cck_lock_counter > 0)
+					cck_lock_counter--;
+			}
+		} else {
+			if (cck_lock_counter > 0)
+				cck_lock_counter--;
+		}
+
+		if (!coex_sta->pre_ccklock) {
+
+			if (cck_lock_counter >= 3)
+				coex_sta->cck_lock = true;
+			else
+				coex_sta->cck_lock = false;
+		} else {
+			if (cck_lock_counter == 0)
+				coex_sta->cck_lock = false;
+			else
+				coex_sta->cck_lock = true;
+		}
+
+		if (coex_sta->cck_lock)
+			coex_sta->cck_ever_lock = true;
+
+		coex_sta->pre_ccklock =  coex_sta->cck_lock;
+
+#endif
+}
+
+void halbtc8723d2ant_update_bt_link_info(IN struct btc_coexist *btcoexist)
+{
+	struct  btc_bt_link_info	*bt_link_info = &btcoexist->bt_link_info;
+	boolean			bt_hs_on = false;
+	boolean			bt_busy = false;
+
+
+	coex_sta->num_of_profile = 0;
+
+	/* set link exist status */
+	if (!(coex_sta->bt_info & BT_INFO_8723D_2ANT_B_CONNECTION)) {
+		coex_sta->bt_link_exist = false;
+		coex_sta->pan_exist = false;
+		coex_sta->a2dp_exist = false;
+		coex_sta->hid_exist = false;
+		coex_sta->sco_exist = false;
+	} else {	/* connection exists */
+		coex_sta->bt_link_exist = true;
+		if (coex_sta->bt_info & BT_INFO_8723D_2ANT_B_FTP) {
+			coex_sta->pan_exist = true;
+			coex_sta->num_of_profile++;
+		} else
+			coex_sta->pan_exist = false;
+
+		if (coex_sta->bt_info & BT_INFO_8723D_2ANT_B_A2DP) {
+			coex_sta->a2dp_exist = true;
+			coex_sta->num_of_profile++;
+		} else
+			coex_sta->a2dp_exist = false;
+
+		if (coex_sta->bt_info & BT_INFO_8723D_2ANT_B_HID) {
+			coex_sta->hid_exist = true;
+			coex_sta->num_of_profile++;
+		} else
+			coex_sta->hid_exist = false;
+
+		if (coex_sta->bt_info & BT_INFO_8723D_2ANT_B_SCO_ESCO) {
+			coex_sta->sco_exist = true;
+			coex_sta->num_of_profile++;
+		} else
+			coex_sta->sco_exist = false;
+
+	}
+
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on);
+
+	bt_link_info->bt_link_exist = coex_sta->bt_link_exist;
+	bt_link_info->sco_exist = coex_sta->sco_exist;
+	bt_link_info->a2dp_exist = coex_sta->a2dp_exist;
+	bt_link_info->pan_exist = coex_sta->pan_exist;
+	bt_link_info->hid_exist = coex_sta->hid_exist;
+	bt_link_info->acl_busy = coex_sta->acl_busy;
+
+	/* work around for HS mode. */
+	if (bt_hs_on) {
+		bt_link_info->pan_exist = true;
+		bt_link_info->bt_link_exist = true;
+	}
+
+	/* check if Sco only */
+	if (bt_link_info->sco_exist &&
+	    !bt_link_info->a2dp_exist &&
+	    !bt_link_info->pan_exist &&
+	    !bt_link_info->hid_exist)
+		bt_link_info->sco_only = true;
+	else
+		bt_link_info->sco_only = false;
+
+	/* check if A2dp only */
+	if (!bt_link_info->sco_exist &&
+	    bt_link_info->a2dp_exist &&
+	    !bt_link_info->pan_exist &&
+	    !bt_link_info->hid_exist)
+		bt_link_info->a2dp_only = true;
+	else
+		bt_link_info->a2dp_only = false;
+
+	/* check if Pan only */
+	if (!bt_link_info->sco_exist &&
+	    !bt_link_info->a2dp_exist &&
+	    bt_link_info->pan_exist &&
+	    !bt_link_info->hid_exist)
+		bt_link_info->pan_only = true;
+	else
+		bt_link_info->pan_only = false;
+
+	/* check if Hid only */
+	if (!bt_link_info->sco_exist &&
+	    !bt_link_info->a2dp_exist &&
+	    !bt_link_info->pan_exist &&
+	    bt_link_info->hid_exist)
+		bt_link_info->hid_only = true;
+	else
+		bt_link_info->hid_only = false;
+
+	if (coex_sta->bt_info & BT_INFO_8723D_2ANT_B_INQ_PAGE) {
+		coex_dm->bt_status = BT_8723D_2ANT_BT_STATUS_INQ_PAGE;
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			"[BTCoex], BtInfoNotify(), BT Inq/page!!!\n");
+	} else if (!(coex_sta->bt_info & BT_INFO_8723D_2ANT_B_CONNECTION)) {
+		coex_dm->bt_status = BT_8723D_2ANT_BT_STATUS_NON_CONNECTED_IDLE;
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			"[BTCoex], BtInfoNotify(), BT Non-Connected idle!!!\n");
+	} else if (coex_sta->bt_info == BT_INFO_8723D_2ANT_B_CONNECTION) {
+		/* connection exists but no busy */
+		coex_dm->bt_status = BT_8723D_2ANT_BT_STATUS_CONNECTED_IDLE;
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], BtInfoNotify(), BT Connected-idle!!!\n");
+	} else if (((coex_sta->bt_info & BT_INFO_8723D_2ANT_B_SCO_ESCO) ||
+		    (coex_sta->bt_info & BT_INFO_8723D_2ANT_B_SCO_BUSY)) &&
+		   (coex_sta->bt_info & BT_INFO_8723D_2ANT_B_ACL_BUSY)) {
+		coex_dm->bt_status = BT_8723D_2ANT_BT_STATUS_ACL_SCO_BUSY;
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], BtInfoNotify(), BT ACL SCO busy!!!\n");
+	} else if ((coex_sta->bt_info & BT_INFO_8723D_2ANT_B_SCO_ESCO) ||
+		   (coex_sta->bt_info & BT_INFO_8723D_2ANT_B_SCO_BUSY)) {
+		coex_dm->bt_status = BT_8723D_2ANT_BT_STATUS_SCO_BUSY;
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], BtInfoNotify(), BT SCO busy!!!\n");
+	} else if (coex_sta->bt_info & BT_INFO_8723D_2ANT_B_ACL_BUSY) {
+		coex_dm->bt_status = BT_8723D_2ANT_BT_STATUS_ACL_BUSY;
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], BtInfoNotify(), BT ACL busy!!!\n");
+	} else {
+		coex_dm->bt_status = BT_8723D_2ANT_BT_STATUS_MAX;
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			"[BTCoex], BtInfoNotify(), BT Non-Defined state!!!\n");
+	}
+
+	BTC_TRACE(trace_buf);
+
+	if ((BT_8723D_2ANT_BT_STATUS_ACL_BUSY == coex_dm->bt_status) ||
+	    (BT_8723D_2ANT_BT_STATUS_SCO_BUSY == coex_dm->bt_status) ||
+	    (BT_8723D_2ANT_BT_STATUS_ACL_SCO_BUSY == coex_dm->bt_status))
+		bt_busy = true;
+	else
+		bt_busy = false;
+
+	btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_TRAFFIC_BUSY, &bt_busy);
+}
+
+void halbtc8723d2ant_update_wifi_channel_info(IN struct btc_coexist *btcoexist,
+		IN u8 type)
+{
+	u8			h2c_parameter[3] = {0};
+	u32			wifi_bw;
+	u8			wifi_central_chnl;
+
+	/* only 2.4G we need to inform bt the chnl mask */
+	btcoexist->btc_get(btcoexist, BTC_GET_U1_WIFI_CENTRAL_CHNL,
+			   &wifi_central_chnl);
+	if ((BTC_MEDIA_CONNECT == type) &&
+	    (wifi_central_chnl <= 14)) {
+		h2c_parameter[0] =
+			0x1;  /* enable BT AFH skip WL channel for 8723d because BT Rx LO interference */
+		/* h2c_parameter[0] = 0x0; */
+		h2c_parameter[1] = wifi_central_chnl;
+		btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw);
+		if (BTC_WIFI_BW_HT40 == wifi_bw)
+			h2c_parameter[2] = 0x30;
+		else
+			h2c_parameter[2] = 0x20;
+	}
+
+	coex_dm->wifi_chnl_info[0] = h2c_parameter[0];
+	coex_dm->wifi_chnl_info[1] = h2c_parameter[1];
+	coex_dm->wifi_chnl_info[2] = h2c_parameter[2];
+
+	btcoexist->btc_fill_h2c(btcoexist, 0x66, 3, h2c_parameter);
+
+}
+
+void halbtc8723d2ant_set_fw_dac_swing_level(IN struct btc_coexist *btcoexist,
+		IN u8 dac_swing_lvl)
+{
+	u8			h2c_parameter[1] = {0};
+
+	/* There are several type of dacswing */
+	/* 0x18/ 0x10/ 0xc/ 0x8/ 0x4/ 0x6 */
+	h2c_parameter[0] = dac_swing_lvl;
+
+	btcoexist->btc_fill_h2c(btcoexist, 0x64, 1, h2c_parameter);
+}
+
+void halbtc8723d2ant_fw_dac_swing_lvl(IN struct btc_coexist *btcoexist,
+			      IN boolean force_exec, IN u8 fw_dac_swing_lvl)
+{
+	coex_dm->cur_fw_dac_swing_lvl = fw_dac_swing_lvl;
+
+	if (!force_exec) {
+		if (coex_dm->pre_fw_dac_swing_lvl ==
+		    coex_dm->cur_fw_dac_swing_lvl)
+			return;
+	}
+
+	halbtc8723d2ant_set_fw_dac_swing_level(btcoexist,
+					       coex_dm->cur_fw_dac_swing_lvl);
+
+	coex_dm->pre_fw_dac_swing_lvl = coex_dm->cur_fw_dac_swing_lvl;
+}
+
+void halbtc8723d2ant_set_fw_dec_bt_pwr(IN struct btc_coexist *btcoexist,
+				       IN u8 dec_bt_pwr_lvl)
+{
+	u8			h2c_parameter[1] = {0};
+
+	h2c_parameter[0] = dec_bt_pwr_lvl;
+
+	btcoexist->btc_fill_h2c(btcoexist, 0x62, 1, h2c_parameter);
+}
+
+void halbtc8723d2ant_dec_bt_pwr(IN struct btc_coexist *btcoexist,
+				IN boolean force_exec, IN u8 dec_bt_pwr_lvl)
+{
+	coex_dm->cur_bt_dec_pwr_lvl = dec_bt_pwr_lvl;
+
+	if (!force_exec) {
+		if (coex_dm->pre_bt_dec_pwr_lvl == coex_dm->cur_bt_dec_pwr_lvl)
+			return;
+	}
+	halbtc8723d2ant_set_fw_dec_bt_pwr(btcoexist,
+					  coex_dm->cur_bt_dec_pwr_lvl);
+
+	coex_dm->pre_bt_dec_pwr_lvl = coex_dm->cur_bt_dec_pwr_lvl;
+}
+
+void halbtc8723d2ant_set_fw_low_penalty_ra(IN struct btc_coexist
+		*btcoexist, IN boolean low_penalty_ra)
+{
+#if 1
+	u8			h2c_parameter[6] = {0};
+
+	h2c_parameter[0] = 0x6;	/* op_code, 0x6= Retry_Penalty */
+
+	if (low_penalty_ra) {
+		h2c_parameter[1] |= BIT(0);
+		h2c_parameter[2] =
+			0x00;  /* normal rate except MCS7/6/5, OFDM54/48/36 */
+		h2c_parameter[3] = 0xf7;  /* MCS7 or OFDM54 */
+		h2c_parameter[4] = 0xf8;  /* MCS6 or OFDM48 */
+		h2c_parameter[5] = 0xf9;	/* MCS5 or OFDM36	 */
+	}
+
+	btcoexist->btc_fill_h2c(btcoexist, 0x69, 6, h2c_parameter);
+#endif
+}
+
+void halbtc8723d2ant_low_penalty_ra(IN struct btc_coexist *btcoexist,
+			    IN boolean force_exec, IN boolean low_penalty_ra)
+{
+#if 1
+	coex_dm->cur_low_penalty_ra = low_penalty_ra;
+
+	if (!force_exec) {
+		if (coex_dm->pre_low_penalty_ra == coex_dm->cur_low_penalty_ra)
+			return;
+	}
+
+	halbtc8723d2ant_set_fw_low_penalty_ra(btcoexist,
+							  coex_dm->cur_low_penalty_ra);
+
+#if 0
+	if (low_penalty_ra)
+		btcoexist->btc_phydm_modify_RA_PCR_threshold(btcoexist, 0, 15);
+	else
+		btcoexist->btc_phydm_modify_RA_PCR_threshold(btcoexist, 0, 0);
+#endif
+	coex_dm->pre_low_penalty_ra = coex_dm->cur_low_penalty_ra;
+
+#endif
+}
+
+void halbtc8723d2ant_set_bt_auto_report(IN struct btc_coexist *btcoexist,
+					IN boolean enable_auto_report)
+{
+	u8			h2c_parameter[1] = {0};
+
+	h2c_parameter[0] = 0;
+
+	if (enable_auto_report)
+		h2c_parameter[0] |= BIT(0);
+
+	btcoexist->btc_fill_h2c(btcoexist, 0x68, 1, h2c_parameter);
+}
+
+void halbtc8723d2ant_bt_auto_report(IN struct btc_coexist *btcoexist,
+		    IN boolean force_exec, IN boolean enable_auto_report)
+{
+	coex_dm->cur_bt_auto_report = enable_auto_report;
+
+	if (!force_exec) {
+		if (coex_dm->pre_bt_auto_report == coex_dm->cur_bt_auto_report)
+			return;
+	}
+	halbtc8723d2ant_set_bt_auto_report(btcoexist,
+					   coex_dm->cur_bt_auto_report);
+
+	coex_dm->pre_bt_auto_report = coex_dm->cur_bt_auto_report;
+}
+
+void halbtc8723d2ant_write_score_board(
+	IN	struct  btc_coexist		*btcoexist,
+	IN	u16				bitpos,
+	IN	boolean		state
+)
+{
+
+	static u16 originalval = 0x8002;
+
+	if (state)
+		originalval = originalval | bitpos;
+	else
+		originalval = originalval & (~bitpos);
+
+
+	btcoexist->btc_write_2byte(btcoexist, 0xaa, originalval);
+
+}
+
+void halbtc8723d2ant_read_score_board(
+	IN	struct  btc_coexist		*btcoexist,
+	IN   u16				*score_board_val
+)
+{
+
+	*score_board_val = (btcoexist->btc_read_2byte(btcoexist,
+			    0xaa)) & 0x7fff;
+}
+
+
+void halbtc8723d2ant_post_state_to_bt(
+	IN	struct  btc_coexist		*btcoexist,
+	IN	u16						type,
+	IN  boolean                 state
+)
+{
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+		"[BTCoex], halbtc8723d2ant_post_state_to_bt: type = %d, state =%d\n",
+		type, state);
+	BTC_TRACE(trace_buf);
+
+	halbtc8723d2ant_write_score_board(btcoexist, (u16) type, state);
+
+}
+
+boolean halbtc8723d2ant_is_wifibt_status_changed(IN struct btc_coexist
+		*btcoexist)
+{
+
+	static boolean	pre_wifi_busy = false, pre_under_4way = false,
+		pre_bt_hs_on = false, pre_bt_off = false, pre_bt_slave = false;
+	static u8 pre_hid_busy_num = 0, pre_wl_noisy_level = 0;
+	boolean wifi_busy = false, under_4way = false, bt_hs_on = false;
+	boolean wifi_connected = false;
+	struct	btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
+
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED,
+			   &wifi_connected);
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy);
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on);
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_4_WAY_PROGRESS,
+			   &under_4way);
+
+	if (coex_sta->bt_disabled != pre_bt_off) {
+		pre_bt_off = coex_sta->bt_disabled;
+
+		if (coex_sta->bt_disabled)
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				    "[BTCoex], BT is disabled !!\n");
+		else
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				    "[BTCoex], BT is enabled !!\n");
+
+		BTC_TRACE(trace_buf);
+
+		coex_sta->bt_coex_supported_feature = 0;
+		coex_sta->bt_coex_supported_version = 0;
+		coex_sta->bt_ble_scan_type = 0;
+		coex_sta->bt_ble_scan_para[0] = 0;
+		coex_sta->bt_ble_scan_para[1] = 0;
+		coex_sta->bt_ble_scan_para[2] = 0;
+		coex_sta->bt_reg_vendor_ac = 0xffff;
+		coex_sta->bt_reg_vendor_ae = 0xffff;
+		return true;
+	}
+
+	if (wifi_connected) {
+		if (wifi_busy != pre_wifi_busy) {
+			pre_wifi_busy = wifi_busy;
+
+			if (wifi_busy)
+				halbtc8723d2ant_post_state_to_bt(btcoexist,
+						BT_8723D_2ANT_SCOREBOARD_UNDERTEST, true);
+			else
+				halbtc8723d2ant_post_state_to_bt(btcoexist,
+						BT_8723D_2ANT_SCOREBOARD_UNDERTEST, false);
+			return true;
+		}
+		if (under_4way != pre_under_4way) {
+			pre_under_4way = under_4way;
+			return true;
+		}
+		if (bt_hs_on != pre_bt_hs_on) {
+			pre_bt_hs_on = bt_hs_on;
+			return true;
+		}
+		if (coex_sta->wl_noisy_level != pre_wl_noisy_level) {
+			pre_wl_noisy_level = coex_sta->wl_noisy_level;
+			return true;
+		}
+	}
+
+	if (!coex_sta->bt_disabled) {
+		if (coex_sta->hid_busy_num != pre_hid_busy_num) {
+			pre_hid_busy_num = coex_sta->hid_busy_num;
+			return true;
+		}
+	}
+
+	if (bt_link_info->slave_role != pre_bt_slave) {
+		pre_bt_slave = bt_link_info->slave_role;
+		return true;
+	}
+
+	return false;
+}
+
+void halbtc8723d2ant_monitor_bt_enable_disable(IN struct btc_coexist *btcoexist)
+{
+	static u32		bt_disable_cnt = 0;
+	boolean			bt_active = true, bt_disabled = false;
+	u16			u16tmp;
+
+	/* This function check if bt is disabled */
+#if 0
+	if (coex_sta->high_priority_tx == 0 &&
+	    coex_sta->high_priority_rx == 0 &&
+	    coex_sta->low_priority_tx == 0 &&
+	    coex_sta->low_priority_rx == 0)
+		bt_active = false;
+	if (coex_sta->high_priority_tx == 0xffff &&
+	    coex_sta->high_priority_rx == 0xffff &&
+	    coex_sta->low_priority_tx == 0xffff &&
+	    coex_sta->low_priority_rx == 0xffff)
+		bt_active = false;
+
+
+#else
+
+	/* Read BT on/off status from scoreboard[1], enable this only if BT patch support this feature */
+	halbtc8723d2ant_read_score_board(btcoexist,	&u16tmp);
+
+	bt_active = u16tmp & BIT(1);
+
+
+#endif
+
+	if (bt_active) {
+		bt_disable_cnt = 0;
+		bt_disabled = false;
+		btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_DISABLE,
+				   &bt_disabled);
+	} else {
+
+		bt_disable_cnt++;
+		if (bt_disable_cnt >= 2) {
+			bt_disabled = true;
+			bt_disable_cnt = 2;
+		}
+
+		btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_DISABLE,
+				   &bt_disabled);
+	}
+
+	if (bt_disabled)
+		halbtc8723d2ant_low_penalty_ra(btcoexist, NORMAL_EXEC, false);
+	else
+		halbtc8723d2ant_low_penalty_ra(btcoexist, NORMAL_EXEC, true);
+
+	if (coex_sta->bt_disabled != bt_disabled) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], BT is from %s to %s!!\n",
+			    (coex_sta->bt_disabled ? "disabled" : "enabled"),
+			    (bt_disabled ? "disabled" : "enabled"));
+		BTC_TRACE(trace_buf);
+		coex_sta->bt_disabled = bt_disabled;
+	}
+
+}
+
+
+
+void halbtc8723d2ant_enable_gnt_to_gpio(IN struct btc_coexist *btcoexist,
+					boolean isenable)
+{
+#if BT_8723D_2ANT_COEX_DBG
+	if (isenable) {
+		btcoexist->btc_write_1byte_bitmask(btcoexist, 0x73, 0x8, 0x1);
+
+		/* enable GNT_BT to GPIO debug */
+		btcoexist->btc_write_1byte_bitmask(btcoexist, 0x4e, 0x40, 0x0);
+		btcoexist->btc_write_1byte_bitmask(btcoexist, 0x67, 0x1, 0x0);
+
+		/* 0x48[20] = 0  for GPIO14 =  GNT_WL*/
+		btcoexist->btc_write_1byte_bitmask(btcoexist, 0x4a, 0x10, 0x0);
+		/* 0x40[17] = 0  for GPIO14 =  GNT_WL*/
+		btcoexist->btc_write_1byte_bitmask(btcoexist, 0x42, 0x02, 0x0);
+
+		/* 0x66[9] = 0   for GPIO15 =  GNT_BT*/
+		btcoexist->btc_write_1byte_bitmask(btcoexist, 0x67, 0x02, 0x0);
+		/* 0x66[7] = 0
+		for GPIO15 =  GNT_BT*/
+		btcoexist->btc_write_1byte_bitmask(btcoexist, 0x66, 0x80, 0x0);
+		/* 0x8[8] = 0    for GPIO15 =  GNT_BT*/
+		btcoexist->btc_write_1byte_bitmask(btcoexist, 0x9, 0x1, 0x0);
+
+		/* BT Vendor Reg 0x76[0] = 0  for GPIO15 =  GNT_BT, this is not set here*/
+	} else {
+		btcoexist->btc_write_1byte_bitmask(btcoexist, 0x73, 0x8, 0x0);
+
+		/* Disable GNT_BT debug to GPIO, and enable chip_wakeup_host */
+		btcoexist->btc_write_1byte_bitmask(btcoexist, 0x4e, 0x40, 0x1);
+		btcoexist->btc_write_1byte_bitmask(btcoexist, 0x67, 0x1, 0x1);
+
+		/* 0x48[20] = 0  for GPIO14 =  GNT_WL*/
+		btcoexist->btc_write_1byte_bitmask(btcoexist, 0x4a, 0x10, 0x1);
+	}
+
+#endif
+}
+
+u32 halbtc8723d2ant_ltecoex_indirect_read_reg(IN struct btc_coexist *btcoexist,
+		IN u16 reg_addr)
+{
+	u32 j = 0, delay_count = 0;
+
+
+	/* wait for ready bit before access 0x7c0		 */
+	btcoexist->btc_write_4byte(btcoexist, 0x7c0, 0x800F0000 | reg_addr);
+
+	while (1) {
+		if ((btcoexist->btc_read_1byte(btcoexist, 0x7c3)&BIT(5)) == 0) {
+			delay_ms(50);
+			delay_count++;
+			if (delay_count >= 10) {
+				delay_count = 0;
+				break;
+			}
+		} else
+			break;
+	}
+
+	return btcoexist->btc_read_4byte(btcoexist,
+					 0x7c8);  /* get read data */
+
+}
+
+void halbtc8723d2ant_ltecoex_indirect_write_reg(IN struct btc_coexist
+		*btcoexist,
+		IN u16 reg_addr, IN u32 bit_mask, IN u32 reg_value)
+{
+	u32 val, i = 0, j = 0, bitpos = 0, delay_count = 0;
+
+
+	if (bit_mask == 0x0)
+		return;
+	if (bit_mask == 0xffffffff) {
+		btcoexist->btc_write_4byte(btcoexist, 0x7c4,
+					   reg_value); /* put write data */
+
+		/* wait for ready bit before access 0x7c0 */
+		while (1) {
+		if ((btcoexist->btc_read_1byte(btcoexist, 0x7c3)&BIT(5)) == 0) {
+			delay_ms(50);
+			delay_count++;
+			if (delay_count >= 10) {
+				delay_count = 0;
+				break;
+			}
+		} else
+			break;
+	}
+
+		btcoexist->btc_write_4byte(btcoexist, 0x7c0,
+					   0xc00F0000 | reg_addr);
+	} else {
+		for (i = 0; i <= 31; i++) {
+			if (((bit_mask >> i) & 0x1) == 0x1) {
+				bitpos = i;
+				break;
+			}
+		}
+
+		/* read back register value before write */
+		val = halbtc8723d2ant_ltecoex_indirect_read_reg(btcoexist,
+				reg_addr);
+		val = (val & (~bit_mask)) | (reg_value << bitpos);
+
+		btcoexist->btc_write_4byte(btcoexist, 0x7c4,
+					   val); /* put write data */
+
+		/* wait for ready bit before access 0x7c0		 */
+		while (1) {
+		if ((btcoexist->btc_read_1byte(btcoexist, 0x7c3)&BIT(5)) == 0) {
+			delay_ms(50);
+			delay_count++;
+			if (delay_count >= 10) {
+				delay_count = 0;
+				break;
+			}
+		} else
+			break;
+	}
+
+		btcoexist->btc_write_4byte(btcoexist, 0x7c0,
+					   0xc00F0000 | reg_addr);
+
+	}
+
+}
+
+void halbtc8723d2ant_ltecoex_enable(IN struct btc_coexist *btcoexist,
+				    IN boolean enable)
+{
+	u8 val;
+
+	val = (enable) ? 1 : 0;
+	halbtc8723d2ant_ltecoex_indirect_write_reg(btcoexist, 0x38, 0x80,
+			val);  /* 0x38[7] */
+
+}
+
+void halbtc8723d2ant_ltecoex_pathcontrol_owner(IN struct btc_coexist *btcoexist,
+		IN boolean wifi_control)
+{
+	u8 val;
+
+	val = (wifi_control) ? 1 : 0;
+	btcoexist->btc_write_1byte_bitmask(btcoexist, 0x73, 0x4,
+					   val); /* 0x70[26] */
+
+}
+
+void halbtc8723d2ant_ltecoex_set_gnt_bt(IN struct btc_coexist *btcoexist,
+			IN u8 control_block, IN boolean sw_control, IN u8 state)
+{
+	u32 val = 0, val_orig = 0;
+
+	if (!sw_control)
+		val = 0x0;
+	else if (state & 0x1)
+		val = 0x3;
+	else
+		val = 0x1;
+
+	val_orig = halbtc8723d2ant_ltecoex_indirect_read_reg(btcoexist,
+				0x38);
+
+	switch (control_block) {
+	case BT_8723D_2ANT_GNT_BLOCK_RFC_BB:
+	default:
+		val = ((val << 14) | (val << 10)) | (val_orig & 0xffff33ff);
+		break;
+	case BT_8723D_2ANT_GNT_BLOCK_RFC:
+		val = (val << 14) | (val_orig & 0xffff3fff);
+		break;
+	case BT_8723D_2ANT_GNT_BLOCK_BB:
+		val = (val << 10) | (val_orig & 0xfffff3ff);
+		break;
+	}
+
+	halbtc8723d2ant_ltecoex_indirect_write_reg(btcoexist,
+				0x38, 0xffffffff, val);
+}
+
+
+void halbtc8723d2ant_ltecoex_set_gnt_wl(IN struct btc_coexist *btcoexist,
+			IN u8 control_block, IN boolean sw_control, IN u8 state)
+{
+	u32 val = 0, val_orig = 0;
+
+	if (!sw_control)
+		val = 0x0;
+	else if (state & 0x1)
+		val = 0x3;
+	else
+		val = 0x1;
+
+	val_orig = halbtc8723d2ant_ltecoex_indirect_read_reg(btcoexist,
+				0x38);
+
+	switch (control_block) {
+	case BT_8723D_2ANT_GNT_BLOCK_RFC_BB:
+	default:
+		val = ((val << 12) | (val << 8)) | (val_orig & 0xffffccff);
+		break;
+	case BT_8723D_2ANT_GNT_BLOCK_RFC:
+		val = (val << 12) | (val_orig & 0xffffcfff);
+		break;
+	case BT_8723D_2ANT_GNT_BLOCK_BB:
+		val = (val << 8) | (val_orig & 0xfffffcff);
+		break;
+	}
+
+	halbtc8723d2ant_ltecoex_indirect_write_reg(btcoexist,
+				0x38, 0xffffffff, val);
+}
+
+void halbtc8723d2ant_ltecoex_set_coex_table(IN struct btc_coexist *btcoexist,
+		IN u8 table_type, IN u16 table_content)
+{
+	u16 reg_addr = 0x0000;
+
+	switch (table_type) {
+	case BT_8723D_2ANT_CTT_WL_VS_LTE:
+		reg_addr = 0xa0;
+		break;
+	case BT_8723D_2ANT_CTT_BT_VS_LTE:
+		reg_addr = 0xa4;
+		break;
+	}
+
+	if (reg_addr != 0x0000)
+		halbtc8723d2ant_ltecoex_indirect_write_reg(btcoexist, reg_addr,
+			0xffff, table_content); /* 0xa0[15:0] or 0xa4[15:0] */
+
+
+}
+
+
+void halbtc8723d2ant_ltecoex_set_break_table(IN struct btc_coexist *btcoexist,
+		IN u8 table_type, IN u8 table_content)
+{
+	u16 reg_addr = 0x0000;
+
+	switch (table_type) {
+	case BT_8723D_2ANT_LBTT_WL_BREAK_LTE:
+		reg_addr = 0xa8;
+		break;
+	case BT_8723D_2ANT_LBTT_BT_BREAK_LTE:
+		reg_addr = 0xac;
+		break;
+	case BT_8723D_2ANT_LBTT_LTE_BREAK_WL:
+		reg_addr = 0xb0;
+		break;
+	case BT_8723D_2ANT_LBTT_LTE_BREAK_BT:
+		reg_addr = 0xb4;
+		break;
+	}
+
+	if (reg_addr != 0x0000)
+		halbtc8723d2ant_ltecoex_indirect_write_reg(btcoexist, reg_addr,
+			0xff, table_content); /* 0xa8[15:0] or 0xb4[15:0] */
+
+
+}
+
+void halbtc8723d2ant_set_wltoggle_coex_table(IN struct btc_coexist *btcoexist,
+		IN boolean force_exec,  IN u8 interval,
+		IN u8 val0x6c4_b0, IN u8 val0x6c4_b1, IN u8 val0x6c4_b2,
+		IN u8 val0x6c4_b3)
+{
+	static u8 pre_h2c_parameter[6] = {0};
+	u8	cur_h2c_parameter[6] = {0};
+	u8 i, match_cnt = 0;
+
+	cur_h2c_parameter[0] = 0x7;	/* op_code, 0x7= wlan toggle slot*/
+
+	cur_h2c_parameter[1] = interval;
+	cur_h2c_parameter[2] = val0x6c4_b0;
+	cur_h2c_parameter[3] = val0x6c4_b1;
+	cur_h2c_parameter[4] = val0x6c4_b2;
+	cur_h2c_parameter[5] = val0x6c4_b3;
+
+	if (!force_exec) {
+		for (i = 1; i <= 5; i++) {
+			if (cur_h2c_parameter[i] != pre_h2c_parameter[i])
+				break;
+
+			match_cnt++;
+		}
+
+		if (match_cnt == 5)
+			return;
+	}
+
+	for (i = 1; i <= 5; i++)
+		pre_h2c_parameter[i] = cur_h2c_parameter[i];
+
+	btcoexist->btc_fill_h2c(btcoexist, 0x69, 6, cur_h2c_parameter);
+}
+
+void halbtc8723d2ant_set_coex_table(IN struct btc_coexist *btcoexist,
+	    IN u32 val0x6c0, IN u32 val0x6c4, IN u32 val0x6c8, IN u8 val0x6cc)
+{
+	btcoexist->btc_write_4byte(btcoexist, 0x6c0, val0x6c0);
+
+	btcoexist->btc_write_4byte(btcoexist, 0x6c4, val0x6c4);
+
+	btcoexist->btc_write_4byte(btcoexist, 0x6c8, val0x6c8);
+
+	btcoexist->btc_write_1byte(btcoexist, 0x6cc, val0x6cc);
+}
+
+void halbtc8723d2ant_coex_table(IN struct btc_coexist *btcoexist,
+			IN boolean force_exec, IN u32 val0x6c0, IN u32 val0x6c4,
+				IN u32 val0x6c8, IN u8 val0x6cc)
+{
+	coex_dm->cur_val0x6c0 = val0x6c0;
+	coex_dm->cur_val0x6c4 = val0x6c4;
+	coex_dm->cur_val0x6c8 = val0x6c8;
+	coex_dm->cur_val0x6cc = val0x6cc;
+
+	if (!force_exec) {
+		if ((coex_dm->pre_val0x6c0 == coex_dm->cur_val0x6c0) &&
+		    (coex_dm->pre_val0x6c4 == coex_dm->cur_val0x6c4) &&
+		    (coex_dm->pre_val0x6c8 == coex_dm->cur_val0x6c8) &&
+		    (coex_dm->pre_val0x6cc == coex_dm->cur_val0x6cc))
+			return;
+	}
+	halbtc8723d2ant_set_coex_table(btcoexist, val0x6c0, val0x6c4, val0x6c8,
+				       val0x6cc);
+
+	coex_dm->pre_val0x6c0 = coex_dm->cur_val0x6c0;
+	coex_dm->pre_val0x6c4 = coex_dm->cur_val0x6c4;
+	coex_dm->pre_val0x6c8 = coex_dm->cur_val0x6c8;
+	coex_dm->pre_val0x6cc = coex_dm->cur_val0x6cc;
+}
+
+void halbtc8723d2ant_coex_table_with_type(IN struct btc_coexist *btcoexist,
+		IN boolean force_exec, IN u8 type)
+{
+	u32	break_table;
+	u8	select_table;
+
+	coex_sta->coex_table_type = type;
+
+	if (coex_sta->concurrent_rx_mode_on == true) {
+		break_table = 0xf0ffffff;  /* set WL hi-pri can break BT */
+		select_table =
+			0xb;		/* set Tx response = Hi-Pri (ex: Transmitting ACK,BA,CTS) */
+	} else {
+		break_table = 0xffffff;
+		select_table = 0x3;
+	}
+
+		switch (type) {
+		case 0:
+			halbtc8723d2ant_coex_table(btcoexist, force_exec,
+				   0xffffffff, 0xffffffff, break_table, select_table);
+			break;
+		case 1:
+			halbtc8723d2ant_coex_table(btcoexist, force_exec,
+				   0x55555555, 0x5a5a5a5a, break_table, select_table);
+			break;
+		case 2:
+			halbtc8723d2ant_coex_table(btcoexist, force_exec,
+				   0x5a5a5a5a, 0x5a5a5a5a, break_table, select_table);
+			break;
+		case 3:
+			halbtc8723d2ant_coex_table(btcoexist, force_exec,
+				   0xaa555555, 0xaa5a5a5a, break_table, select_table);
+			break;
+		case 4:
+			halbtc8723d2ant_coex_table(btcoexist, force_exec,
+				   0x55555555, 0x5a5a5a5a, break_table, select_table);
+			break;
+		case 5:
+			halbtc8723d2ant_coex_table(btcoexist, force_exec,
+				   0x55555555, 0x55555555, break_table, select_table);
+			break;
+		case 6:
+			halbtc8723d2ant_coex_table(btcoexist, force_exec,
+				   0xa5555555, 0xfafafafa, break_table, select_table);
+			break;
+		case 7:
+			halbtc8723d2ant_coex_table(btcoexist, force_exec,
+				   0xa5555555, 0xaa5a5a5a, break_table, select_table);
+			break;
+		case 8:
+			halbtc8723d2ant_coex_table(btcoexist, force_exec,
+				   0xa5555555, 0xfafafafa, break_table, select_table);
+			break;
+		case 9:
+			halbtc8723d2ant_coex_table(btcoexist, force_exec,
+				   0x5a5a5a5a, 0xaaaa5aaa, break_table, select_table);
+			break;
+		default:
+			break;
+		}
+}
+
+void halbtc8723d2ant_set_fw_ignore_wlan_act(IN struct btc_coexist *btcoexist,
+		IN boolean enable)
+{
+	u8			h2c_parameter[1] = {0};
+
+	if (enable) {
+		h2c_parameter[0] |= BIT(0);		/* function enable */
+	}
+
+	btcoexist->btc_fill_h2c(btcoexist, 0x63, 1, h2c_parameter);
+}
+
+void halbtc8723d2ant_ignore_wlan_act(IN struct btc_coexist *btcoexist,
+				     IN boolean force_exec, IN boolean enable)
+{
+	coex_dm->cur_ignore_wlan_act = enable;
+
+	if (!force_exec) {
+		if (coex_dm->pre_ignore_wlan_act ==
+		    coex_dm->cur_ignore_wlan_act)
+			return;
+	}
+	halbtc8723d2ant_set_fw_ignore_wlan_act(btcoexist, enable);
+
+	coex_dm->pre_ignore_wlan_act = coex_dm->cur_ignore_wlan_act;
+}
+
+void halbtc8723d2ant_set_lps_rpwm(IN struct btc_coexist *btcoexist,
+				  IN u8 lps_val, IN u8 rpwm_val)
+{
+	u8	lps = lps_val;
+	u8	rpwm = rpwm_val;
+
+	btcoexist->btc_set(btcoexist, BTC_SET_U1_LPS_VAL, &lps);
+	btcoexist->btc_set(btcoexist, BTC_SET_U1_RPWM_VAL, &rpwm);
+}
+
+void halbtc8723d2ant_lps_rpwm(IN struct btc_coexist *btcoexist,
+		      IN boolean force_exec, IN u8 lps_val, IN u8 rpwm_val)
+{
+	coex_dm->cur_lps = lps_val;
+	coex_dm->cur_rpwm = rpwm_val;
+
+	if (!force_exec) {
+		if ((coex_dm->pre_lps == coex_dm->cur_lps) &&
+		    (coex_dm->pre_rpwm == coex_dm->cur_rpwm))
+			return;
+	}
+	halbtc8723d2ant_set_lps_rpwm(btcoexist, lps_val, rpwm_val);
+
+	coex_dm->pre_lps = coex_dm->cur_lps;
+	coex_dm->pre_rpwm = coex_dm->cur_rpwm;
+}
+
+void halbtc8723d2ant_ps_tdma_check_for_power_save_state(
+	IN struct btc_coexist *btcoexist, IN boolean new_ps_state)
+{
+	u8	lps_mode = 0x0;
+	u8	h2c_parameter[5] = {0, 0, 0, 0x40, 0};
+
+	btcoexist->btc_get(btcoexist, BTC_GET_U1_LPS_MODE, &lps_mode);
+
+	if (lps_mode) {	/* already under LPS state */
+		if (new_ps_state) {
+			/* keep state under LPS, do nothing. */
+		} else {
+			/* will leave LPS state, turn off psTdma first */
+			/*halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, false,
+						8); */
+			btcoexist->btc_fill_h2c(btcoexist, 0x60, 5,
+						h2c_parameter);
+		}
+	} else {					/* NO PS state */
+		if (new_ps_state) {
+			/* will enter LPS state, turn off psTdma first */
+			/*halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, false,
+						8);*/
+			btcoexist->btc_fill_h2c(btcoexist, 0x60, 5,
+						h2c_parameter);
+		} else {
+			/* keep state under NO PS state, do nothing. */
+		}
+	}
+}
+
+void halbtc8723d2ant_power_save_state(IN struct btc_coexist *btcoexist,
+			      IN u8 ps_type, IN u8 lps_val, IN u8 rpwm_val)
+{
+	boolean		low_pwr_disable = false;
+
+	switch (ps_type) {
+	case BTC_PS_WIFI_NATIVE:
+		/* recover to original 32k low power setting */
+		low_pwr_disable = false;
+		btcoexist->btc_set(btcoexist,
+				   BTC_SET_ACT_DISABLE_LOW_POWER,
+				   &low_pwr_disable);
+		btcoexist->btc_set(btcoexist, BTC_SET_ACT_NORMAL_LPS,
+				   NULL);
+		coex_sta->force_lps_on = false;
+		break;
+	case BTC_PS_LPS_ON:
+		halbtc8723d2ant_ps_tdma_check_for_power_save_state(
+			btcoexist, true);
+		halbtc8723d2ant_lps_rpwm(btcoexist, NORMAL_EXEC,
+					 lps_val, rpwm_val);
+		/* when coex force to enter LPS, do not enter 32k low power. */
+		low_pwr_disable = true;
+		btcoexist->btc_set(btcoexist,
+				   BTC_SET_ACT_DISABLE_LOW_POWER,
+				   &low_pwr_disable);
+		/* power save must executed before psTdma.			 */
+		btcoexist->btc_set(btcoexist, BTC_SET_ACT_ENTER_LPS,
+				   NULL);
+		coex_sta->force_lps_on = true;
+		break;
+	case BTC_PS_LPS_OFF:
+		halbtc8723d2ant_ps_tdma_check_for_power_save_state(
+			btcoexist, false);
+		btcoexist->btc_set(btcoexist, BTC_SET_ACT_LEAVE_LPS,
+				   NULL);
+		coex_sta->force_lps_on = false;
+		break;
+	default:
+		break;
+	}
+}
+
+
+
+void halbtc8723d2ant_set_fw_pstdma(IN struct btc_coexist *btcoexist,
+	   IN u8 byte1, IN u8 byte2, IN u8 byte3, IN u8 byte4, IN u8 byte5)
+{
+	u8			h2c_parameter[5] = {0};
+	u8			real_byte1 = byte1, real_byte5 = byte5;
+	boolean			ap_enable = false;
+	struct  btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
+
+	if (byte5 & BIT(2))
+		coex_sta->is_tdma_btautoslot = true;
+	else
+		coex_sta->is_tdma_btautoslot = false;
+
+	/* release bt-auto slot for auto-slot hang is detected!! */
+	if (coex_sta->is_tdma_btautoslot)
+		if ((coex_sta->is_tdma_btautoslot_hang) ||
+			(bt_link_info->slave_role))
+			byte5 = byte5 & 0xfb;
+
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_AP_MODE_ENABLE,
+			   &ap_enable);
+
+	if (ap_enable) {
+		if (byte1 & BIT(4) && !(byte1 & BIT(5))) {
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				    "[BTCoex], FW for AP mode\n");
+			BTC_TRACE(trace_buf);
+			real_byte1 &= ~BIT(4);
+			real_byte1 |= BIT(5);
+
+			real_byte5 |= BIT(5);
+			real_byte5 &= ~BIT(6);
+
+			halbtc8723d2ant_power_save_state(btcoexist,
+						 BTC_PS_WIFI_NATIVE, 0x0,
+							 0x0);
+		}
+	} else if (byte1 & BIT(4) && !(byte1 & BIT(5))) {
+
+		halbtc8723d2ant_power_save_state(
+			btcoexist, BTC_PS_LPS_ON, 0x50,
+			0x4);
+	} else {
+		halbtc8723d2ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE,
+						 0x0,
+						 0x0);
+	}
+
+
+	h2c_parameter[0] = real_byte1;
+	h2c_parameter[1] = byte2;
+	h2c_parameter[2] = byte3;
+	h2c_parameter[3] = byte4;
+	h2c_parameter[4] = real_byte5;
+
+	coex_dm->ps_tdma_para[0] = real_byte1;
+	coex_dm->ps_tdma_para[1] = byte2;
+	coex_dm->ps_tdma_para[2] = byte3;
+	coex_dm->ps_tdma_para[3] = byte4;
+	coex_dm->ps_tdma_para[4] = real_byte5;
+
+	btcoexist->btc_fill_h2c(btcoexist, 0x60, 5, h2c_parameter);
+}
+
+void halbtc8723d2ant_ps_tdma(IN struct btc_coexist *btcoexist,
+		     IN boolean force_exec, IN boolean turn_on, IN u8 type)
+{
+
+	static u8			psTdmaByte4Modify = 0x0, pre_psTdmaByte4Modify = 0x0;
+	struct  btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
+
+
+	coex_dm->cur_ps_tdma_on = turn_on;
+	coex_dm->cur_ps_tdma = type;
+
+	/* 0x778 = 0x1 at wifi slot (no blocking BT Low-Pri pkts) */
+	if ((bt_link_info->slave_role) && (bt_link_info->a2dp_exist))
+		psTdmaByte4Modify = 0x1;
+	else
+		psTdmaByte4Modify = 0x0;
+
+	if (pre_psTdmaByte4Modify != psTdmaByte4Modify) {
+
+		force_exec = true;
+		pre_psTdmaByte4Modify = psTdmaByte4Modify;
+	}
+
+	if (!force_exec) {
+		if ((coex_dm->pre_ps_tdma_on == coex_dm->cur_ps_tdma_on) &&
+		    (coex_dm->pre_ps_tdma == coex_dm->cur_ps_tdma))
+			return;
+	}
+
+	if (coex_dm->cur_ps_tdma_on) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], ********** TDMA(on, %d) **********\n",
+			    coex_dm->cur_ps_tdma);
+		BTC_TRACE(trace_buf);
+
+		btcoexist->btc_write_1byte_bitmask(btcoexist, 0x550, 0x8,
+					   0x1);  /* enable TBTT nterrupt */
+	} else {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], ********** TDMA(off, %d) **********\n",
+			    coex_dm->cur_ps_tdma);
+		BTC_TRACE(trace_buf);
+	}
+
+
+	if (turn_on) {
+		switch (type) {
+		case 1:
+			halbtc8723d2ant_set_fw_pstdma(btcoexist, 0x61,
+								0x10, 0x03, 0x91,
+								0x54 | psTdmaByte4Modify);
+			break;
+		case 2:
+		default:
+			halbtc8723d2ant_set_fw_pstdma(btcoexist, 0x61,
+								0x35, 0x03, 0x11,
+								0x11 | psTdmaByte4Modify);
+			break;
+		case 3:
+			halbtc8723d2ant_set_fw_pstdma(btcoexist, 0x61,
+								0x3a, 0x3, 0x91,
+								0x10 | psTdmaByte4Modify);
+			break;
+		case 4:
+			halbtc8723d2ant_set_fw_pstdma(btcoexist, 0x61,
+								0x21, 0x3, 0x91,
+								0x10 | psTdmaByte4Modify);
+			break;
+		case 5:
+			halbtc8723d2ant_set_fw_pstdma(btcoexist, 0x61,
+								0x25, 0x3, 0x91,
+								0x10 | psTdmaByte4Modify);
+			break;
+		case 6:
+			halbtc8723d2ant_set_fw_pstdma(btcoexist, 0x61,
+								0x10, 0x3, 0x91,
+								0x10 | psTdmaByte4Modify);
+			break;
+		case 7:
+			halbtc8723d2ant_set_fw_pstdma(btcoexist, 0x61,
+								0x20, 0x3, 0x91,
+								0x10 | psTdmaByte4Modify);
+			break;
+		case 8:
+			halbtc8723d2ant_set_fw_pstdma(btcoexist, 0x61,
+								0x15, 0x03, 0x11,
+								0x11);
+			break;
+		case 10:
+			halbtc8723d2ant_set_fw_pstdma(btcoexist, 0x61,
+								0x30, 0x03, 0x11,
+								0x10);
+			break;
+		case 11:
+			halbtc8723d2ant_set_fw_pstdma(btcoexist, 0x61,
+								0x35, 0x03, 0x11,
+								0x10 | psTdmaByte4Modify);
+			break;
+		case 12:
+			halbtc8723d2ant_set_fw_pstdma(btcoexist, 0x61,
+								0x35, 0x03, 0x11, 0x11);
+			break;
+		case 13:
+			halbtc8723d2ant_set_fw_pstdma(btcoexist, 0x61,
+								0x1c, 0x03, 0x11,
+								0x10 | psTdmaByte4Modify);
+			break;
+		case 14:
+			halbtc8723d2ant_set_fw_pstdma(btcoexist, 0x61,
+								0x20, 0x03, 0x11,
+								0x11);
+			break;
+		case 15:
+			halbtc8723d2ant_set_fw_pstdma(btcoexist, 0x61,
+								0x10, 0x03, 0x11,
+								0x14);
+			break;
+		case 16:
+			halbtc8723d2ant_set_fw_pstdma(btcoexist, 0x61,
+								0x10, 0x03, 0x11,
+								0x15);
+			break;
+		case 21:
+			halbtc8723d2ant_set_fw_pstdma(btcoexist, 0x61,
+								0x30, 0x03, 0x11,
+								0x10);
+			break;
+		case 22:
+			halbtc8723d2ant_set_fw_pstdma(btcoexist, 0x61,
+								0x25, 0x03, 0x11,
+								0x10);
+			break;
+		case 23:
+			halbtc8723d2ant_set_fw_pstdma(btcoexist, 0x61,
+								0x10, 0x03, 0x11,
+								0x10);
+			break;
+		case 51:
+			halbtc8723d2ant_set_fw_pstdma(btcoexist, 0x61,
+								0x10, 0x03, 0x91,
+								0x10 | psTdmaByte4Modify);
+			break;
+		case 101:
+			halbtc8723d2ant_set_fw_pstdma(btcoexist, 0x51,
+								0x10, 0x03, 0x10,
+								0x54 | psTdmaByte4Modify);
+			break;
+		case 102:
+			halbtc8723d2ant_set_fw_pstdma(btcoexist, 0x61,
+								0x35, 0x03, 0x11,
+								0x11 | psTdmaByte4Modify);
+			break;
+		case 103:
+			halbtc8723d2ant_set_fw_pstdma(btcoexist, 0x51,
+								0x3a, 0x3, 0x10,
+								0x50 | psTdmaByte4Modify);
+			break;
+		case 104:
+			halbtc8723d2ant_set_fw_pstdma(btcoexist, 0x51,
+								0x21, 0x3, 0x10,
+								0x50 | psTdmaByte4Modify);
+			break;
+		case 105:
+			halbtc8723d2ant_set_fw_pstdma(btcoexist, 0x51,
+								0x25, 0x3, 0x10,
+								0x50 | psTdmaByte4Modify);
+			break;
+		case 106:
+			halbtc8723d2ant_set_fw_pstdma(btcoexist, 0x51,
+								0x10, 0x3, 0x10,
+								0x50 | psTdmaByte4Modify);
+			break;
+		case 107:
+			halbtc8723d2ant_set_fw_pstdma(btcoexist, 0x51,
+								0x20, 0x3, 0x10,
+								0x50 | psTdmaByte4Modify);
+			break;
+		case 108:
+			halbtc8723d2ant_set_fw_pstdma(btcoexist, 0x51,
+								0x30, 0x3, 0x10,
+								0x50 | psTdmaByte4Modify);
+			break;
+		case 109:
+			halbtc8723d2ant_set_fw_pstdma(btcoexist, 0x55,
+								0x10, 0x03, 0x10,
+								0x54 | psTdmaByte4Modify);
+			break;
+		case 110:
+			halbtc8723d2ant_set_fw_pstdma(btcoexist, 0x55,
+								0x30, 0x03, 0x10,
+								0x50 | psTdmaByte4Modify);
+			break;
+		case 111:
+			halbtc8723d2ant_set_fw_pstdma(btcoexist, 0x65,
+								0x25, 0x03, 0x11,
+								0x11 | psTdmaByte4Modify);
+			break;
+		case 151:
+			halbtc8723d2ant_set_fw_pstdma(btcoexist, 0x51,
+								0x10, 0x03, 0x10,
+								0x50 | psTdmaByte4Modify);
+			break;
+		}
+	} else {
+		/* disable PS tdma */
+		switch (type) {
+		case 0:
+			halbtc8723d2ant_set_fw_pstdma(btcoexist, 0x0,
+						      0x0, 0x0, 0x40, 0x0);
+			break;
+		case 1:
+			halbtc8723d2ant_set_fw_pstdma(btcoexist, 0x0,
+						      0x0, 0x0, 0x48, 0x0);
+			break;
+		default:
+			halbtc8723d2ant_set_fw_pstdma(btcoexist, 0x0,
+						      0x0, 0x0, 0x40, 0x0);
+			break;
+		}
+	}
+
+	/* update pre state */
+	coex_dm->pre_ps_tdma_on = coex_dm->cur_ps_tdma_on;
+	coex_dm->pre_ps_tdma = coex_dm->cur_ps_tdma;
+}
+
+void halbtc8723d2ant_set_ant_path(IN struct btc_coexist *btcoexist,
+				  IN u8 ant_pos_type, IN boolean force_exec,
+				  IN u8 phase)
+{
+	struct  btc_board_info *board_info = &btcoexist->board_info;
+	u32			u32tmp = 0;
+	boolean			pg_ext_switch = false,  is_hw_ant_div_on = false;
+	u8			h2c_parameter[2] = {0};
+	u32			cnt_bt_cal_chk = 0;
+	u8			u8tmp0 = 0, u8tmp1 = 0;
+	boolean			is_in_mp_mode = false;
+	u32				u32tmp0 = 0, u32tmp1 = 0, u32tmp2 = 0;
+	u16				u16tmp0 = 0,  u16tmp1 = 0;
+
+
+	u32tmp1 = halbtc8723d2ant_ltecoex_indirect_read_reg(btcoexist,
+			0x38);
+
+     /* To avoid indirect access fail   */
+	if (((u32tmp1 & 0xf000) >> 12) != ((u32tmp1 & 0x0f00) >> 8)) {
+		force_exec = true;
+		coex_sta->gnt_error_cnt++;
+	}
+
+
+#if BT_8723D_2ANT_COEX_DBG
+	u32tmp2 = halbtc8723d2ant_ltecoex_indirect_read_reg(btcoexist, 0x54);
+	u16tmp0 = btcoexist->btc_read_2byte(btcoexist, 0xaa);
+	u16tmp1 = btcoexist->btc_read_2byte(btcoexist, 0x948);
+	u8tmp1  = btcoexist->btc_read_1byte(btcoexist, 0x73);
+	u8tmp0 =  btcoexist->btc_read_1byte(btcoexist, 0x67);
+
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+		"[BTCoex], ********** 0x67 = 0x%x, 0x948 = 0x%x, 0x73 = 0x%x(Before Set Ant Pat)\n",
+		    u8tmp0, u16tmp1, u8tmp1);
+	BTC_TRACE(trace_buf);
+
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+		"[BTCoex], **********0x38= 0x%x, 0x54= 0x%x, 0xaa = 0x%x (Before Set Ant Path)\n",
+		    u32tmp1, u32tmp2, u16tmp0);
+	BTC_TRACE(trace_buf);
+#endif
+
+	coex_dm->cur_ant_pos_type = ant_pos_type;
+
+	if (!force_exec) {
+		if (coex_dm->cur_ant_pos_type == coex_dm->pre_ant_pos_type) {
+
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				"[BTCoex], ********** Skip Antenna Path Setup because no change!!**********\n");
+			BTC_TRACE(trace_buf);
+			return;
+		}
+	}
+
+	coex_dm->pre_ant_pos_type = coex_dm->cur_ant_pos_type;
+
+	switch (phase) {
+	case BT_8723D_2ANT_PHASE_COEX_POWERON:
+		/* Set Path control to WL */
+		btcoexist->btc_write_1byte_bitmask(btcoexist, 0x67,
+						   0x80, 0x0);
+
+		/* set Path control owner to WL at initial step */
+		halbtc8723d2ant_ltecoex_pathcontrol_owner(btcoexist,
+				BT_8723D_2ANT_PCO_BTSIDE);
+
+		/* set GNT_BT to SW high */
+		halbtc8723d2ant_ltecoex_set_gnt_bt(btcoexist,
+					   BT_8723D_2ANT_GNT_BLOCK_RFC_BB,
+					   BT_8723D_2ANT_GNT_TYPE_CTRL_BY_SW,
+					   BT_8723D_2ANT_SIG_STA_SET_TO_HIGH);
+		/* Set GNT_WL to SW low */
+		halbtc8723d2ant_ltecoex_set_gnt_wl(btcoexist,
+					   BT_8723D_2ANT_GNT_BLOCK_RFC_BB,
+					   BT_8723D_2ANT_GNT_TYPE_CTRL_BY_SW,
+					   BT_8723D_2ANT_SIG_STA_SET_TO_HIGH);
+
+		if (BTC_ANT_PATH_AUTO == ant_pos_type)
+			ant_pos_type = BTC_ANT_PATH_WIFI;
+
+		coex_sta->run_time_state = false;
+
+		break;
+	case BT_8723D_2ANT_PHASE_COEX_INIT:
+		/* Disable LTE Coex Function in WiFi side (this should be on if LTE coex is required) */
+		halbtc8723d2ant_ltecoex_enable(btcoexist, 0x0);
+
+		/* GNT_WL_LTE always = 1 (this should be config if LTE coex is required) */
+		halbtc8723d2ant_ltecoex_set_coex_table(
+			btcoexist,
+			BT_8723D_2ANT_CTT_WL_VS_LTE,
+			0xffff);
+
+		/* GNT_BT_LTE always = 1 (this should be config if LTE coex is required) */
+		halbtc8723d2ant_ltecoex_set_coex_table(
+			btcoexist,
+			BT_8723D_2ANT_CTT_BT_VS_LTE,
+			0xffff);
+
+		/* Wait If BT IQK running, because Path control owner is at BT during BT IQK (setup by WiFi firmware) */
+		while (cnt_bt_cal_chk <= 20) {
+			u8tmp0 = btcoexist->btc_read_1byte(
+					 btcoexist,
+					 0x49d);
+			cnt_bt_cal_chk++;
+			if (u8tmp0 & BIT(0)) {
+				BTC_SPRINTF(
+					trace_buf,
+					BT_TMP_BUF_SIZE,
+					"[BTCoex], ########### BT is calibrating (wait cnt=%d) ###########\n",
+					cnt_bt_cal_chk);
+				BTC_TRACE(
+					trace_buf);
+				delay_ms(50);
+			} else {
+				BTC_SPRINTF(
+					trace_buf,
+					BT_TMP_BUF_SIZE,
+					"[BTCoex], ********** BT is NOT calibrating (wait cnt=%d)**********\n",
+					cnt_bt_cal_chk);
+				BTC_TRACE(
+					trace_buf);
+				break;
+			}
+		}
+
+
+		/* Set Path control to WL */
+		btcoexist->btc_write_1byte_bitmask(btcoexist,
+						   0x67, 0x80, 0x1);
+
+		/* set Path control owner to WL at initial step */
+		halbtc8723d2ant_ltecoex_pathcontrol_owner(
+			btcoexist,
+			BT_8723D_2ANT_PCO_WLSIDE);
+
+		/* set GNT_BT to SW high */
+		halbtc8723d2ant_ltecoex_set_gnt_bt(btcoexist,
+					   BT_8723D_2ANT_GNT_BLOCK_RFC_BB,
+					   BT_8723D_2ANT_GNT_TYPE_CTRL_BY_SW,
+					   BT_8723D_2ANT_SIG_STA_SET_TO_HIGH);
+		/* Set GNT_WL to SW high */
+		halbtc8723d2ant_ltecoex_set_gnt_wl(btcoexist,
+					   BT_8723D_2ANT_GNT_BLOCK_RFC_BB,
+					   BT_8723D_2ANT_GNT_TYPE_CTRL_BY_SW,
+					   BT_8723D_2ANT_SIG_STA_SET_TO_HIGH);
+
+		coex_sta->run_time_state = false;
+
+		if (BTC_ANT_PATH_AUTO == ant_pos_type) {
+			if (board_info->btdm_ant_pos ==
+			    BTC_ANTENNA_AT_MAIN_PORT)
+				ant_pos_type =
+					BTC_ANT_WIFI_AT_MAIN;
+			else
+				ant_pos_type =
+					BTC_ANT_WIFI_AT_AUX;
+		}
+
+		break;
+	case BT_8723D_2ANT_PHASE_WLANONLY_INIT:
+		/* Disable LTE Coex Function in WiFi side (this should be on if LTE coex is required) */
+		halbtc8723d2ant_ltecoex_enable(btcoexist, 0x0);
+
+		/* GNT_WL_LTE always = 1 (this should be config if LTE coex is required) */
+		halbtc8723d2ant_ltecoex_set_coex_table(
+			btcoexist,
+			BT_8723D_2ANT_CTT_WL_VS_LTE,
+			0xffff);
+
+		/* GNT_BT_LTE always = 1 (this should be config if LTE coex is required) */
+		halbtc8723d2ant_ltecoex_set_coex_table(
+			btcoexist,
+			BT_8723D_2ANT_CTT_BT_VS_LTE,
+			0xffff);
+
+		/* Set Path control to WL */
+		btcoexist->btc_write_1byte_bitmask(btcoexist,
+						   0x67, 0x80, 0x1);
+
+		/* set Path control owner to WL at initial step */
+		halbtc8723d2ant_ltecoex_pathcontrol_owner(
+			btcoexist,
+			BT_8723D_2ANT_PCO_WLSIDE);
+
+		/* set GNT_BT to SW Low */
+		halbtc8723d2ant_ltecoex_set_gnt_bt(btcoexist,
+					   BT_8723D_2ANT_GNT_BLOCK_RFC_BB,
+					   BT_8723D_2ANT_GNT_TYPE_CTRL_BY_SW,
+					   BT_8723D_2ANT_SIG_STA_SET_TO_LOW);
+		/* Set GNT_WL to SW high */
+		halbtc8723d2ant_ltecoex_set_gnt_wl(btcoexist,
+					   BT_8723D_2ANT_GNT_BLOCK_RFC_BB,
+					   BT_8723D_2ANT_GNT_TYPE_CTRL_BY_SW,
+					   BT_8723D_2ANT_SIG_STA_SET_TO_HIGH);
+
+		coex_sta->run_time_state = false;
+
+		if (BTC_ANT_PATH_AUTO == ant_pos_type) {
+			if (board_info->btdm_ant_pos ==
+			    BTC_ANTENNA_AT_MAIN_PORT)
+				ant_pos_type =
+					BTC_ANT_WIFI_AT_MAIN;
+			else
+				ant_pos_type =
+					BTC_ANT_WIFI_AT_AUX;
+		}
+
+		break;
+	case BT_8723D_2ANT_PHASE_WLAN_OFF:
+		/* Disable LTE Coex Function in WiFi side */
+		halbtc8723d2ant_ltecoex_enable(btcoexist, 0x0);
+
+		/* Set Path control to BT */
+		btcoexist->btc_write_1byte_bitmask(btcoexist,
+						   0x67, 0x80, 0x0);
+
+		/* set Path control owner to BT */
+		halbtc8723d2ant_ltecoex_pathcontrol_owner(
+			btcoexist,
+			BT_8723D_2ANT_PCO_BTSIDE);
+
+		coex_sta->run_time_state = false;
+		break;
+	case BT_8723D_2ANT_PHASE_2G_RUNTIME:
+
+		/* wait for WL/BT IQK finish, keep 0x38 = 0xff00 for WL IQK */
+		while (cnt_bt_cal_chk <= 20) {
+			u8tmp0 = btcoexist->btc_read_1byte(
+					 btcoexist,
+					 0x1e6);
+
+			u8tmp1 = btcoexist->btc_read_1byte(
+					 btcoexist,
+					 0x49d);
+
+			cnt_bt_cal_chk++;
+			if ((u8tmp0 & BIT(0)) ||
+			    (u8tmp1 & BIT(0))) {
+				BTC_SPRINTF(trace_buf,
+					    BT_TMP_BUF_SIZE,
+					"[BTCoex], ########### WL or BT is IQK (wait cnt=%d)\n",
+					    cnt_bt_cal_chk);
+				BTC_TRACE(trace_buf);
+				delay_ms(50);
+			} else {
+				BTC_SPRINTF(trace_buf,
+					    BT_TMP_BUF_SIZE,
+					"[BTCoex], ********** WL and BT is NOT IQK (wait cnt=%d)\n",
+					    cnt_bt_cal_chk);
+				BTC_TRACE(trace_buf);
+				break;
+			}
+		}
+
+		/* Set Path control to WL */
+		/* btcoexist->btc_write_1byte_bitmask(btcoexist, 0x67, 0x80, 0x1);*/
+
+		/* set Path control owner to WL at runtime step */
+		halbtc8723d2ant_ltecoex_pathcontrol_owner(
+			btcoexist,
+			BT_8723D_2ANT_PCO_WLSIDE);
+
+
+		halbtc8723d2ant_ltecoex_set_gnt_bt(btcoexist,
+					   BT_8723D_2ANT_GNT_BLOCK_RFC_BB,
+					   BT_8723D_2ANT_GNT_TYPE_CTRL_BY_PTA,
+					   BT_8723D_2ANT_SIG_STA_SET_TO_HIGH);
+
+		/* Set GNT_WL to PTA */
+		halbtc8723d2ant_ltecoex_set_gnt_wl(btcoexist,
+					   BT_8723D_2ANT_GNT_BLOCK_RFC_BB,
+					   BT_8723D_2ANT_GNT_TYPE_CTRL_BY_PTA,
+					   BT_8723D_2ANT_SIG_STA_SET_BY_HW);
+
+		coex_sta->run_time_state = true;
+
+		if (BTC_ANT_PATH_AUTO == ant_pos_type) {
+			if (board_info->btdm_ant_pos ==
+			    BTC_ANTENNA_AT_MAIN_PORT)
+				ant_pos_type =
+					BTC_ANT_WIFI_AT_MAIN;
+			else
+				ant_pos_type =
+					BTC_ANT_WIFI_AT_AUX;
+		}
+
+		break;
+	case BT_8723D_2ANT_PHASE_BTMPMODE:
+		/* Disable LTE Coex Function in WiFi side */
+		halbtc8723d2ant_ltecoex_enable(btcoexist, 0x0);
+
+		/* Set Path control to WL */
+		btcoexist->btc_write_1byte_bitmask(btcoexist,
+						   0x67, 0x80, 0x1);
+
+		/* set Path control owner to WL */
+		halbtc8723d2ant_ltecoex_pathcontrol_owner(
+			btcoexist,
+			BT_8723D_2ANT_PCO_WLSIDE);
+
+		/* set GNT_BT to SW Hi */
+		halbtc8723d2ant_ltecoex_set_gnt_bt(btcoexist,
+					   BT_8723D_2ANT_GNT_BLOCK_RFC_BB,
+					   BT_8723D_2ANT_GNT_TYPE_CTRL_BY_SW,
+					   BT_8723D_2ANT_SIG_STA_SET_TO_HIGH);
+
+		/* Set GNT_WL to SW Lo */
+		halbtc8723d2ant_ltecoex_set_gnt_wl(btcoexist,
+					   BT_8723D_2ANT_GNT_BLOCK_RFC_BB,
+					   BT_8723D_2ANT_GNT_TYPE_CTRL_BY_SW,
+					   BT_8723D_2ANT_SIG_STA_SET_TO_LOW);
+
+		coex_sta->run_time_state = false;
+
+		if (BTC_ANT_PATH_AUTO == ant_pos_type) {
+			if (board_info->btdm_ant_pos ==
+			    BTC_ANTENNA_AT_MAIN_PORT)
+				ant_pos_type =
+					BTC_ANT_WIFI_AT_MAIN;
+			else
+				ant_pos_type =
+					BTC_ANT_WIFI_AT_AUX;
+		}
+
+		break;
+	case BT_8723D_2ANT_PHASE_ANTENNA_DET:
+
+		/* Set Path control to WL */
+		btcoexist->btc_write_1byte_bitmask(btcoexist, 0x67,
+						   0x80, 0x1);
+
+		/* set Path control owner to WL */
+		halbtc8723d2ant_ltecoex_pathcontrol_owner(btcoexist,
+				BT_8723D_2ANT_PCO_WLSIDE);
+
+		/* Set Antenna Path,  both GNT_WL/GNT_BT = 1, and control by SW */
+		/* set GNT_BT to SW high */
+		halbtc8723d2ant_ltecoex_set_gnt_bt(btcoexist,
+					   BT_8723D_2ANT_GNT_BLOCK_RFC_BB,
+					   BT_8723D_2ANT_GNT_TYPE_CTRL_BY_SW,
+					   BT_8723D_2ANT_SIG_STA_SET_TO_HIGH);
+
+		/* Set GNT_WL to SW high */
+		halbtc8723d2ant_ltecoex_set_gnt_wl(btcoexist,
+					   BT_8723D_2ANT_GNT_BLOCK_RFC_BB,
+					   BT_8723D_2ANT_GNT_TYPE_CTRL_BY_SW,
+					   BT_8723D_2ANT_SIG_STA_SET_TO_HIGH);
+
+		if (BTC_ANT_PATH_AUTO == ant_pos_type)
+			ant_pos_type = BTC_ANT_WIFI_AT_AUX;
+
+		coex_sta->run_time_state = false;
+
+		break;
+	}
+
+	is_hw_ant_div_on = board_info->ant_div_cfg;
+
+	if ((is_hw_ant_div_on) && (phase != BT_8723D_2ANT_PHASE_ANTENNA_DET))
+		btcoexist->btc_write_2byte(btcoexist, 0x948, 0x140);
+	else if ((is_hw_ant_div_on == false) &&
+		 (phase != BT_8723D_2ANT_PHASE_WLAN_OFF)) {
+
+		switch (ant_pos_type) {
+		case BTC_ANT_WIFI_AT_MAIN:
+
+			btcoexist->btc_write_2byte(btcoexist,
+						   0x948, 0x0);
+			break;
+		case BTC_ANT_WIFI_AT_AUX:
+
+			btcoexist->btc_write_2byte(btcoexist,
+						   0x948, 0x280);
+			break;
+		}
+	}
+
+
+#if BT_8723D_2ANT_COEX_DBG
+	u32tmp1 = halbtc8723d2ant_ltecoex_indirect_read_reg(btcoexist, 0x38);
+	u32tmp2 = halbtc8723d2ant_ltecoex_indirect_read_reg(btcoexist, 0x54);
+	u16tmp0 = btcoexist->btc_read_2byte(btcoexist, 0xaa);
+	u16tmp1 = btcoexist->btc_read_2byte(btcoexist, 0x948);
+	u8tmp1  = btcoexist->btc_read_1byte(btcoexist, 0x73);
+	u8tmp0 =  btcoexist->btc_read_1byte(btcoexist, 0x67);
+
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+		"[BTCoex], ********** 0x67 = 0x%x, 0x948 = 0x%x, 0x73 = 0x%x(After Set Ant Pat)\n",
+		    u8tmp0, u16tmp1, u8tmp1);
+	BTC_TRACE(trace_buf);
+
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+		"[BTCoex], **********0x38= 0x%x, 0x54= 0x%x, 0xaa= 0x%x (After Set Ant Path)\n",
+		    u32tmp1, u32tmp2, u16tmp0);
+	BTC_TRACE(trace_buf);
+#endif
+
+}
+
+u8 halbtc8723d2ant_action_algorithm(IN struct btc_coexist *btcoexist)
+{
+	struct  btc_bt_link_info	*bt_link_info = &btcoexist->bt_link_info;
+	boolean				bt_hs_on = false;
+	u8				algorithm = BT_8723D_2ANT_COEX_ALGO_UNDEFINED;
+	u8				num_of_diff_profile = 0;
+
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on);
+
+	if (!bt_link_info->bt_link_exist) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], No BT link exists!!!\n");
+		BTC_TRACE(trace_buf);
+		return algorithm;
+	}
+
+	if (bt_link_info->sco_exist)
+		num_of_diff_profile++;
+	if (bt_link_info->hid_exist)
+		num_of_diff_profile++;
+	if (bt_link_info->pan_exist)
+		num_of_diff_profile++;
+	if (bt_link_info->a2dp_exist)
+		num_of_diff_profile++;
+
+	if (num_of_diff_profile == 0) {
+
+		if (bt_link_info->acl_busy) {
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				    "[BTCoex], No-Profile busy\n");
+			BTC_TRACE(trace_buf);
+			algorithm = BT_8723D_2ANT_COEX_ALGO_NOPROFILEBUSY;
+		}
+	} else if (num_of_diff_profile == 1) {
+		if (bt_link_info->sco_exist) {
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				    "[BTCoex], SCO only\n");
+			BTC_TRACE(trace_buf);
+			algorithm = BT_8723D_2ANT_COEX_ALGO_SCO;
+		} else {
+			if (bt_link_info->hid_exist) {
+				BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+					    "[BTCoex], HID only\n");
+				BTC_TRACE(trace_buf);
+				algorithm = BT_8723D_2ANT_COEX_ALGO_HID;
+			} else if (bt_link_info->a2dp_exist) {
+				BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+					    "[BTCoex], A2DP only\n");
+				BTC_TRACE(trace_buf);
+				algorithm = BT_8723D_2ANT_COEX_ALGO_A2DP;
+			} else if (bt_link_info->pan_exist) {
+				if (bt_hs_on) {
+					BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+						    "[BTCoex], PAN(HS) only\n");
+					BTC_TRACE(trace_buf);
+					algorithm =
+						BT_8723D_2ANT_COEX_ALGO_PANHS;
+				} else {
+					BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+						"[BTCoex], PAN(EDR) only\n");
+					BTC_TRACE(trace_buf);
+					algorithm =
+						BT_8723D_2ANT_COEX_ALGO_PANEDR;
+				}
+			}
+		}
+	} else if (num_of_diff_profile == 2) {
+		if (bt_link_info->sco_exist) {
+			if (bt_link_info->hid_exist) {
+				BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+					    "[BTCoex], SCO + HID\n");
+				BTC_TRACE(trace_buf);
+				algorithm = BT_8723D_2ANT_COEX_ALGO_SCO;
+			} else if (bt_link_info->a2dp_exist) {
+				BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+					    "[BTCoex], SCO + A2DP ==> A2DP\n");
+				BTC_TRACE(trace_buf);
+				algorithm = BT_8723D_2ANT_COEX_ALGO_A2DP;
+			} else if (bt_link_info->pan_exist) {
+				if (bt_hs_on) {
+					BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+						"[BTCoex], SCO + PAN(HS)\n");
+					BTC_TRACE(trace_buf);
+					algorithm = BT_8723D_2ANT_COEX_ALGO_SCO;
+				} else {
+					BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+						"[BTCoex], SCO + PAN(EDR)\n");
+					BTC_TRACE(trace_buf);
+					algorithm =
+						BT_8723D_2ANT_COEX_ALGO_PANEDR;
+				}
+			}
+		} else {
+			if (bt_link_info->hid_exist &&
+			    bt_link_info->a2dp_exist) {
+				{
+					BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+						    "[BTCoex], HID + A2DP\n");
+					BTC_TRACE(trace_buf);
+					algorithm =
+						BT_8723D_2ANT_COEX_ALGO_HID_A2DP;
+				}
+			} else if (bt_link_info->hid_exist &&
+				   bt_link_info->pan_exist) {
+				if (bt_hs_on) {
+					BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+						"[BTCoex], HID + PAN(HS)\n");
+					BTC_TRACE(trace_buf);
+					algorithm = BT_8723D_2ANT_COEX_ALGO_HID;
+				} else {
+					BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+						"[BTCoex], HID + PAN(EDR)\n");
+					BTC_TRACE(trace_buf);
+					algorithm =
+						BT_8723D_2ANT_COEX_ALGO_PANEDR_HID;
+				}
+			} else if (bt_link_info->pan_exist &&
+				   bt_link_info->a2dp_exist) {
+				if (bt_hs_on) {
+					BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+						"[BTCoex], A2DP + PAN(HS)\n");
+					BTC_TRACE(trace_buf);
+					algorithm =
+						BT_8723D_2ANT_COEX_ALGO_A2DP_PANHS;
+				} else {
+					BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+						"[BTCoex], A2DP + PAN(EDR)\n");
+					BTC_TRACE(trace_buf);
+					algorithm =
+						BT_8723D_2ANT_COEX_ALGO_PANEDR_A2DP;
+				}
+			}
+		}
+	} else if (num_of_diff_profile == 3) {
+		if (bt_link_info->sco_exist) {
+			if (bt_link_info->hid_exist &&
+			    bt_link_info->a2dp_exist) {
+				BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+					"[BTCoex], SCO + HID + A2DP ==> HID + A2DP\n");
+				BTC_TRACE(trace_buf);
+				algorithm = BT_8723D_2ANT_COEX_ALGO_HID_A2DP;
+			} else if (bt_link_info->hid_exist &&
+				   bt_link_info->pan_exist) {
+				if (bt_hs_on) {
+					BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+						"[BTCoex], SCO + HID + PAN(HS)\n");
+					BTC_TRACE(trace_buf);
+					algorithm =
+						BT_8723D_2ANT_COEX_ALGO_PANEDR_HID;
+				} else {
+					BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+						"[BTCoex], SCO + HID + PAN(EDR)\n");
+					BTC_TRACE(trace_buf);
+					algorithm =
+						BT_8723D_2ANT_COEX_ALGO_PANEDR_HID;
+				}
+			} else if (bt_link_info->pan_exist &&
+				   bt_link_info->a2dp_exist) {
+				if (bt_hs_on) {
+					BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+						"[BTCoex], SCO + A2DP + PAN(HS)\n");
+					BTC_TRACE(trace_buf);
+					algorithm =
+						BT_8723D_2ANT_COEX_ALGO_PANEDR_A2DP;
+				} else {
+					BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+						"[BTCoex], SCO + A2DP + PAN(EDR) ==> HID\n");
+					BTC_TRACE(trace_buf);
+					algorithm =
+						BT_8723D_2ANT_COEX_ALGO_PANEDR_A2DP;
+				}
+			}
+		} else {
+			if (bt_link_info->hid_exist &&
+			    bt_link_info->pan_exist &&
+			    bt_link_info->a2dp_exist) {
+				if (bt_hs_on) {
+					BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+						"[BTCoex], HID + A2DP + PAN(HS)\n");
+					BTC_TRACE(trace_buf);
+					algorithm =
+						BT_8723D_2ANT_COEX_ALGO_HID_A2DP_PANEDR;
+				} else {
+					BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+						"[BTCoex], HID + A2DP + PAN(EDR)\n");
+					BTC_TRACE(trace_buf);
+					algorithm =
+						BT_8723D_2ANT_COEX_ALGO_HID_A2DP_PANEDR;
+				}
+			}
+		}
+	} else if (num_of_diff_profile >= 3) {
+		if (bt_link_info->sco_exist) {
+			if (bt_link_info->hid_exist &&
+			    bt_link_info->pan_exist &&
+			    bt_link_info->a2dp_exist) {
+				if (bt_hs_on) {
+					BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+						"[BTCoex], Error!!! SCO + HID + A2DP + PAN(HS)\n");
+					BTC_TRACE(trace_buf);
+					algorithm =
+						BT_8723D_2ANT_COEX_ALGO_HID_A2DP_PANEDR;
+				} else {
+					BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+						"[BTCoex], SCO + HID + A2DP + PAN(EDR)==>PAN(EDR)+HID\n");
+					BTC_TRACE(trace_buf);
+					algorithm =
+						BT_8723D_2ANT_COEX_ALGO_HID_A2DP_PANEDR;
+				}
+			}
+		}
+	}
+
+	return algorithm;
+}
+
+
+
+void halbtc8723d2ant_action_coex_all_off(IN struct btc_coexist *btcoexist)
+{
+
+	halbtc8723d2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0);
+
+	/* fw all off */
+	halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 0);
+
+	halbtc8723d2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0x18);
+	halbtc8723d2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);
+}
+
+void halbtc8723d2ant_action_bt_whql_test(IN struct btc_coexist *btcoexist)
+{
+	halbtc8723d2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0x18);
+	halbtc8723d2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);
+
+	halbtc8723d2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0);
+
+	halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 0);
+}
+
+void halbtc8723d2ant_action_bt_hs(IN struct btc_coexist *btcoexist)
+{
+	static u8	prewifi_rssi_state = BTC_RSSI_STATE_LOW;
+	static u8	pre_bt_rssi_state = BTC_RSSI_STATE_LOW;
+	u8		wifi_rssi_state, bt_rssi_state;
+
+	static u8	prewifi_rssi_state2 = BTC_RSSI_STATE_LOW;
+	static u8	pre_bt_rssi_state2 = BTC_RSSI_STATE_LOW;
+	u8		wifi_rssi_state2, bt_rssi_state2;
+	boolean wifi_busy = false, wifi_turbo = false;
+
+
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy);
+	btcoexist->btc_get(btcoexist, BTC_GET_U1_AP_NUM,
+			   &coex_sta->scan_ap_num);
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			"############# [BTCoex],  scan_ap_num = %d, wl_noisy = %d\n",
+			coex_sta->scan_ap_num, coex_sta->wl_noisy_level);
+	BTC_TRACE(trace_buf);
+
+#if 1
+	if ((wifi_busy) && (coex_sta->wl_noisy_level == 0))
+		wifi_turbo = true;
+#endif
+
+
+	wifi_rssi_state = halbtc8723d2ant_wifi_rssi_state(btcoexist,
+			  &prewifi_rssi_state, 2,
+			  coex_sta->wifi_coex_thres , 0);
+
+	wifi_rssi_state2 = halbtc8723d2ant_wifi_rssi_state(btcoexist,
+			   &prewifi_rssi_state2, 2,
+			   coex_sta->wifi_coex_thres2 , 0);
+
+	bt_rssi_state = halbtc8723d2ant_bt_rssi_state(&pre_bt_rssi_state, 2,
+			coex_sta->bt_coex_thres , 0);
+
+	bt_rssi_state2 = halbtc8723d2ant_bt_rssi_state(&pre_bt_rssi_state2, 2,
+			 coex_sta->bt_coex_thres2 , 0);
+
+	if (BTC_RSSI_HIGH(wifi_rssi_state) &&
+		BTC_RSSI_HIGH(bt_rssi_state)) {
+
+		halbtc8723d2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0x18);
+		halbtc8723d2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);
+
+		coex_dm->is_switch_to_1dot5_ant = false;
+
+		halbtc8723d2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0);
+
+		halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 0);
+	} else if (BTC_RSSI_HIGH(wifi_rssi_state2) &&
+		   BTC_RSSI_HIGH(bt_rssi_state2)) {
+
+		halbtc8723d2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0x6);
+		halbtc8723d2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2);
+
+		coex_dm->is_switch_to_1dot5_ant = false;
+
+		halbtc8723d2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0);
+
+		halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 0);
+
+
+	} else {
+
+		halbtc8723d2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0x18);
+		halbtc8723d2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);
+
+		coex_dm->is_switch_to_1dot5_ant = true;
+
+		halbtc8723d2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0);
+
+		halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 0);
+	}
+
+}
+
+
+void halbtc8723d2ant_action_bt_inquiry(IN struct btc_coexist *btcoexist)
+{
+
+	boolean wifi_connected = false;
+	boolean wifi_scan = false, wifi_link = false, wifi_roam = false;
+	boolean wifi_busy = false;
+	struct	btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
+
+
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy);
+
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED,
+			   &wifi_connected);
+
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_SCAN, &wifi_scan);
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_LINK, &wifi_link);
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_ROAM, &wifi_roam);
+
+	if ((coex_sta->bt_create_connection) && ((wifi_link) || (wifi_roam)
+		|| (wifi_scan) || (wifi_busy) || (coex_sta->wifi_is_high_pri_task))) {
+
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			"[BTCoex], Wifi link/roam/Scan/busy/hi-pri-task + BT Inq/Page!!\n");
+		BTC_TRACE(trace_buf);
+
+		halbtc8723d2ant_coex_table_with_type(btcoexist, NORMAL_EXEC,
+							 8);
+
+		if ((bt_link_info->a2dp_exist) && (!bt_link_info->pan_exist))
+			halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, true,
+						15);
+		else
+			halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, true,
+						11);
+	}  else if ((!wifi_connected) && (!wifi_scan)) {
+
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				"[BTCoex], Wifi no-link + no-scan + BT Inq/Page!!\n");
+		BTC_TRACE(trace_buf);
+
+		halbtc8723d2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0);
+
+		halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 0);
+	} else if (bt_link_info->pan_exist) {
+
+		halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 22);
+
+		halbtc8723d2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 8);
+
+	} else if (bt_link_info->a2dp_exist) {
+
+		halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 16);
+
+		halbtc8723d2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 8);
+	} else {
+
+		if ((wifi_link) || (wifi_roam) || (wifi_scan) || (wifi_busy)
+			|| (coex_sta->wifi_is_high_pri_task))
+			halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 21);
+		else
+			halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 23);
+
+		halbtc8723d2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 8);
+	}
+
+	halbtc8723d2ant_fw_dac_swing_lvl(btcoexist, FORCE_EXEC, 0x18);
+	halbtc8723d2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);
+}
+
+
+void halbtc8723d2ant_action_bt_relink(IN struct btc_coexist *btcoexist)
+{
+	halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 8);
+	halbtc8723d2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 1);
+
+	halbtc8723d2ant_fw_dac_swing_lvl(btcoexist, FORCE_EXEC, 0x18);
+	halbtc8723d2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);
+	coex_sta->bt_relink_downcount = 2;
+}
+
+void halbtc8723d2ant_action_bt_idle(IN struct btc_coexist *btcoexist)
+{
+	boolean wifi_busy = false;
+
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy);
+
+	if (!wifi_busy) {
+
+		halbtc8723d2ant_coex_table_with_type(btcoexist,
+						     NORMAL_EXEC, 8);
+
+		halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 14);
+	} else {  /* if wl busy */
+
+		if (BT_8723D_1ANT_BT_STATUS_NON_CONNECTED_IDLE ==
+			coex_dm->bt_status) {
+
+			halbtc8723d2ant_coex_table_with_type(btcoexist,
+								 NORMAL_EXEC, 0);
+
+			halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 0);
+	   } else {
+
+			halbtc8723d2ant_coex_table_with_type(btcoexist,
+									NORMAL_EXEC, 8);
+			halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, true,
+							12);
+		}
+	}
+
+	halbtc8723d2ant_fw_dac_swing_lvl(btcoexist, FORCE_EXEC, 0x18);
+	halbtc8723d2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);
+
+}
+
+
+
+/* SCO only or SCO+PAN(HS) */
+void halbtc8723d2ant_action_sco(IN struct btc_coexist *btcoexist)
+{
+	static u8	prewifi_rssi_state = BTC_RSSI_STATE_LOW;
+	static u8	pre_bt_rssi_state = BTC_RSSI_STATE_LOW;
+	u8	wifi_rssi_state, bt_rssi_state;
+
+	static u8	prewifi_rssi_state2 = BTC_RSSI_STATE_LOW;
+	static u8	pre_bt_rssi_state2 = BTC_RSSI_STATE_LOW;
+	u8	wifi_rssi_state2, bt_rssi_state2;
+	boolean	wifi_busy = false;
+	u32  wifi_bw = 1;
+
+	btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW,
+			   &wifi_bw);
+
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy);
+
+	wifi_rssi_state = halbtc8723d2ant_wifi_rssi_state(btcoexist,
+			  &prewifi_rssi_state, 2,
+			  coex_sta->wifi_coex_thres , 0);
+
+	wifi_rssi_state2 = halbtc8723d2ant_wifi_rssi_state(btcoexist,
+			   &prewifi_rssi_state2, 2,
+			   coex_sta->wifi_coex_thres2 , 0);
+
+	bt_rssi_state = halbtc8723d2ant_bt_rssi_state(&pre_bt_rssi_state, 2,
+			coex_sta->bt_coex_thres , 0);
+
+	bt_rssi_state2 = halbtc8723d2ant_bt_rssi_state(&pre_bt_rssi_state2, 2,
+			 coex_sta->bt_coex_thres2 , 0);
+
+
+	if (BTC_RSSI_HIGH(wifi_rssi_state) &&
+		BTC_RSSI_HIGH(bt_rssi_state)) {
+
+		halbtc8723d2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0x18);
+		halbtc8723d2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);
+
+		coex_dm->is_switch_to_1dot5_ant = false;
+
+		halbtc8723d2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0);
+
+		halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 0);
+	}  else {
+
+		halbtc8723d2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0x18);
+		halbtc8723d2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);
+
+		coex_dm->is_switch_to_1dot5_ant = false;
+
+		if (coex_sta->is_eSCO_mode)
+			halbtc8723d2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 1);
+		else  /* 2-Ant free run if eSCO mode */
+			halbtc8723d2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0);
+
+		halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 8);
+	}
+
+}
+
+
+void halbtc8723d2ant_action_hid(IN struct btc_coexist *btcoexist)
+{
+	static u8	prewifi_rssi_state = BTC_RSSI_STATE_LOW;
+	static u8	pre_bt_rssi_state = BTC_RSSI_STATE_LOW;
+	u8		wifi_rssi_state, bt_rssi_state;
+
+	static u8	prewifi_rssi_state2 = BTC_RSSI_STATE_LOW;
+	static u8	pre_bt_rssi_state2 = BTC_RSSI_STATE_LOW;
+	u8		wifi_rssi_state2, bt_rssi_state2;
+	boolean wifi_busy = false;
+	u32  wifi_bw = 1;
+
+
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy);
+	btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW,  &wifi_bw);
+
+	wifi_rssi_state = halbtc8723d2ant_wifi_rssi_state(btcoexist,
+			  &prewifi_rssi_state, 2,
+			  coex_sta->wifi_coex_thres , 0);
+
+	wifi_rssi_state2 = halbtc8723d2ant_wifi_rssi_state(btcoexist,
+			   &prewifi_rssi_state2, 2,
+			   coex_sta->wifi_coex_thres2 , 0);
+
+	bt_rssi_state = halbtc8723d2ant_bt_rssi_state(&pre_bt_rssi_state, 2,
+			coex_sta->bt_coex_thres , 0);
+
+	bt_rssi_state2 = halbtc8723d2ant_bt_rssi_state(&pre_bt_rssi_state2, 2,
+			 coex_sta->bt_coex_thres2 , 0);
+
+
+	if (BTC_RSSI_HIGH(wifi_rssi_state) &&
+		BTC_RSSI_HIGH(bt_rssi_state)) {
+
+		halbtc8723d2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0x18);
+		halbtc8723d2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);
+
+		coex_dm->is_switch_to_1dot5_ant = false;
+
+		halbtc8723d2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0);
+
+		halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 0);
+	}  else {
+
+		halbtc8723d2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0x18);
+		halbtc8723d2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);
+
+		coex_dm->is_switch_to_1dot5_ant = false;
+
+		/*for 4/18 hid */
+		if (coex_sta->hid_busy_num >= 2) {
+			if (wifi_bw == 0) {   /* if 11bg mode */
+
+				 halbtc8723d2ant_coex_table_with_type(btcoexist,
+								 NORMAL_EXEC, 8);
+				 halbtc8723d2ant_set_wltoggle_coex_table(btcoexist,
+								NORMAL_EXEC,
+								0x1, 0xaa,
+								0x5a, 0xaa,
+								0xaa);
+				 halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, true,
+							111);
+			} else {
+
+			  if (wifi_busy) {
+					  halbtc8723d2ant_coex_table_with_type(btcoexist,
+									 NORMAL_EXEC, 8);
+					  halbtc8723d2ant_set_wltoggle_coex_table(btcoexist,
+									 NORMAL_EXEC,
+									 0x2, 0xaa,
+									 0x5a, 0xaa,
+									 0xaa);
+					  halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, true,
+									 111);
+				} else {
+
+					  halbtc8723d2ant_coex_table_with_type(btcoexist, NORMAL_EXEC,
+								 3);
+					  halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 14);
+				}
+			}
+		} else {
+
+			halbtc8723d2ant_coex_table_with_type(btcoexist, NORMAL_EXEC,
+								 3);
+			halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 14);
+		}
+	}
+
+}
+
+
+/* A2DP only / PAN(EDR) only/ A2DP+PAN(HS) */
+void halbtc8723d2ant_action_a2dp(IN struct btc_coexist *btcoexist)
+{
+	static u8	prewifi_rssi_state = BTC_RSSI_STATE_LOW;
+	static u8	pre_bt_rssi_state = BTC_RSSI_STATE_LOW;
+	u8		wifi_rssi_state, bt_rssi_state;
+
+	static u8	prewifi_rssi_state2 = BTC_RSSI_STATE_LOW;
+	static u8	pre_bt_rssi_state2 = BTC_RSSI_STATE_LOW;
+	u8		wifi_rssi_state2, bt_rssi_state2;
+	boolean wifi_busy = false, wifi_turbo = false;
+
+
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy);
+	btcoexist->btc_get(btcoexist, BTC_GET_U1_AP_NUM,
+			   &coex_sta->scan_ap_num);
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			"############# [BTCoex],  scan_ap_num = %d, wl_noisy = %d\n",
+			coex_sta->scan_ap_num, coex_sta->wl_noisy_level);
+	BTC_TRACE(trace_buf);
+
+#if 1
+	if ((wifi_busy) && (coex_sta->wl_noisy_level == 0))
+		wifi_turbo = true;
+#endif
+
+	wifi_rssi_state = halbtc8723d2ant_wifi_rssi_state(btcoexist,
+			  &prewifi_rssi_state, 2,
+			  coex_sta->wifi_coex_thres , 0);
+
+	wifi_rssi_state2 = halbtc8723d2ant_wifi_rssi_state(btcoexist,
+			   &prewifi_rssi_state2, 2,
+			   coex_sta->wifi_coex_thres2 , 0);
+
+	bt_rssi_state = halbtc8723d2ant_bt_rssi_state(&pre_bt_rssi_state, 2,
+			coex_sta->bt_coex_thres , 0);
+
+	bt_rssi_state2 = halbtc8723d2ant_bt_rssi_state(&pre_bt_rssi_state2, 2,
+			 coex_sta->bt_coex_thres2 , 0);
+
+
+	if (BTC_RSSI_HIGH(wifi_rssi_state) &&
+		BTC_RSSI_HIGH(bt_rssi_state)) {
+
+		halbtc8723d2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0x18);
+		halbtc8723d2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);
+
+		coex_dm->is_switch_to_1dot5_ant = false;
+
+		halbtc8723d2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0);
+
+		halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 0);
+	} else if (BTC_RSSI_HIGH(wifi_rssi_state2) &&
+		   BTC_RSSI_HIGH(bt_rssi_state2)) {
+
+		halbtc8723d2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0x6);
+		halbtc8723d2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2);
+
+		coex_dm->is_switch_to_1dot5_ant = false;
+
+		halbtc8723d2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4);
+
+		if (wifi_busy)
+			halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC,
+							true, 1);
+		else
+			halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, true,
+						16);
+	} else {
+
+		halbtc8723d2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0x18);
+		halbtc8723d2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);
+
+		coex_dm->is_switch_to_1dot5_ant = true;
+
+		if ((coex_sta->bt_relink_downcount != 0)
+			&& (wifi_busy)) {
+
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				"############# [BTCoex],  BT Re-Link + A2DP + WL busy\n");
+			BTC_TRACE(trace_buf);
+
+			halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 0);
+			halbtc8723d2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 5);
+
+		} else {
+
+			if (wifi_turbo)
+				halbtc8723d2ant_coex_table_with_type(btcoexist,
+									 NORMAL_EXEC, 6);
+			else
+				halbtc8723d2ant_coex_table_with_type(btcoexist, NORMAL_EXEC,
+									 7);
+
+			if (wifi_busy)
+				halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC,
+								true, 101);
+			else
+				halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, true,
+							16);
+				/*halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, true,
+							102);*/
+		}
+
+	}
+
+}
+
+
+void halbtc8723d2ant_action_pan_edr(IN struct btc_coexist *btcoexist)
+{
+	static u8	prewifi_rssi_state = BTC_RSSI_STATE_LOW;
+	static u8	pre_bt_rssi_state = BTC_RSSI_STATE_LOW;
+	u8		wifi_rssi_state, bt_rssi_state;
+
+	static u8	prewifi_rssi_state2 = BTC_RSSI_STATE_LOW;
+	static u8	pre_bt_rssi_state2 = BTC_RSSI_STATE_LOW;
+	u8		wifi_rssi_state2, bt_rssi_state2;
+	boolean wifi_busy = false, wifi_turbo = false;
+
+
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy);
+	btcoexist->btc_get(btcoexist, BTC_GET_U1_AP_NUM,
+			   &coex_sta->scan_ap_num);
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			"############# [BTCoex],  scan_ap_num = %d, wl_noisy = %d\n",
+			coex_sta->scan_ap_num, coex_sta->wl_noisy_level);
+	BTC_TRACE(trace_buf);
+
+#if 1
+	if ((wifi_busy) && (coex_sta->wl_noisy_level == 0))
+		wifi_turbo = true;
+#endif
+
+	wifi_rssi_state = halbtc8723d2ant_wifi_rssi_state(btcoexist,
+			  &prewifi_rssi_state, 2,
+			  coex_sta->wifi_coex_thres , 0);
+
+	wifi_rssi_state2 = halbtc8723d2ant_wifi_rssi_state(btcoexist,
+			   &prewifi_rssi_state2, 2,
+			   coex_sta->wifi_coex_thres2 , 0);
+
+	bt_rssi_state = halbtc8723d2ant_bt_rssi_state(&pre_bt_rssi_state, 2,
+			coex_sta->bt_coex_thres , 0);
+
+	bt_rssi_state2 = halbtc8723d2ant_bt_rssi_state(&pre_bt_rssi_state2, 2,
+			 coex_sta->bt_coex_thres2 , 0);
+
+#if 0
+	halbtc8723d2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0x18);
+	halbtc8723d2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);
+
+	coex_dm->is_switch_to_1dot5_ant = false;
+
+	halbtc8723d2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0);
+
+	halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 0);
+#endif
+
+
+#if 1
+	if (BTC_RSSI_HIGH(wifi_rssi_state) &&
+		BTC_RSSI_HIGH(bt_rssi_state)) {
+
+		halbtc8723d2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0x18);
+		halbtc8723d2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);
+
+		coex_dm->is_switch_to_1dot5_ant = false;
+
+		halbtc8723d2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0);
+
+		halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 0);
+	} else if (BTC_RSSI_HIGH(wifi_rssi_state2) &&
+		   BTC_RSSI_HIGH(bt_rssi_state2)) {
+
+		halbtc8723d2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0x6);
+		halbtc8723d2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2);
+
+		coex_dm->is_switch_to_1dot5_ant = false;
+
+		halbtc8723d2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4);
+
+		if (wifi_busy)
+			halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, true,
+						3);
+		else
+			halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, true,
+						4);
+	} else {
+
+		halbtc8723d2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0x18);
+		halbtc8723d2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);
+
+		coex_dm->is_switch_to_1dot5_ant = true;
+
+		if (wifi_turbo)
+			halbtc8723d2ant_coex_table_with_type(btcoexist,
+								 NORMAL_EXEC, 6);
+		else
+			halbtc8723d2ant_coex_table_with_type(btcoexist, NORMAL_EXEC,
+								 7);
+
+		if (wifi_busy)
+			halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, true,
+						103);
+		else
+			halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, true,
+						104);
+
+	}
+
+#endif
+
+}
+
+void halbtc8723d2ant_action_hid_a2dp(IN struct btc_coexist *btcoexist)
+{
+	static u8	prewifi_rssi_state = BTC_RSSI_STATE_LOW;
+	static u8	pre_bt_rssi_state = BTC_RSSI_STATE_LOW;
+	u8		wifi_rssi_state, bt_rssi_state;
+
+	static u8	prewifi_rssi_state2 = BTC_RSSI_STATE_LOW;
+	static u8	pre_bt_rssi_state2 = BTC_RSSI_STATE_LOW;
+	u8		wifi_rssi_state2, bt_rssi_state2;
+	boolean wifi_busy = false;
+	u32 wifi_bw = 1;
+
+	btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW,
+			   &wifi_bw);
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy);
+
+	wifi_rssi_state = halbtc8723d2ant_wifi_rssi_state(btcoexist,
+			  &prewifi_rssi_state, 2,
+			  coex_sta->wifi_coex_thres , 0);
+
+	wifi_rssi_state2 = halbtc8723d2ant_wifi_rssi_state(btcoexist,
+			   &prewifi_rssi_state2, 2,
+			   coex_sta->wifi_coex_thres2 , 0);
+
+	bt_rssi_state = halbtc8723d2ant_bt_rssi_state(&pre_bt_rssi_state, 2,
+			coex_sta->bt_coex_thres , 0);
+
+	bt_rssi_state2 = halbtc8723d2ant_bt_rssi_state(&pre_bt_rssi_state2, 2,
+			 coex_sta->bt_coex_thres2 , 0);
+
+
+	if (BTC_RSSI_HIGH(wifi_rssi_state) &&
+		BTC_RSSI_HIGH(bt_rssi_state)) {
+
+		halbtc8723d2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0x18);
+		halbtc8723d2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);
+
+		coex_dm->is_switch_to_1dot5_ant = false;
+
+		halbtc8723d2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0);
+		halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 0);
+	} else if (BTC_RSSI_HIGH(wifi_rssi_state2) &&
+		   BTC_RSSI_HIGH(bt_rssi_state2)) {
+
+		halbtc8723d2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0x6);
+		halbtc8723d2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2);
+
+		coex_dm->is_switch_to_1dot5_ant = false;
+
+		halbtc8723d2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4);
+
+		if (wifi_busy)
+			halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC,
+							true, 1);
+		else
+			halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, true,
+						16);
+	} else {
+
+		halbtc8723d2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0x18);
+		halbtc8723d2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);
+
+		coex_dm->is_switch_to_1dot5_ant = true;
+
+		if ((coex_sta->bt_relink_downcount != 0)
+			&& (wifi_busy)) {
+
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				"############# [BTCoex],  BT Re-Link + A2DP + WL busy\n");
+			BTC_TRACE(trace_buf);
+
+			halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 0);
+			halbtc8723d2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 5);
+		} else if (wifi_busy) {
+			if (coex_sta->hid_busy_num >= 2) {
+				halbtc8723d2ant_coex_table_with_type(btcoexist,
+								 NORMAL_EXEC, 8);
+				if (wifi_bw == 0)  /*11bg mode */
+					halbtc8723d2ant_set_wltoggle_coex_table(btcoexist,
+								NORMAL_EXEC,
+								0x1, 0xaa,
+								0x5a, 0xaa,
+								0xaa);
+				else
+					halbtc8723d2ant_set_wltoggle_coex_table(btcoexist,
+								NORMAL_EXEC,
+								0x2, 0xaa,
+								0x5a, 0xaa,
+								0xaa);
+					halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, true,
+							109);
+			} else {
+				halbtc8723d2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 1);
+				halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC,
+							true, 101);
+			}
+		} else {
+			halbtc8723d2ant_coex_table_with_type(btcoexist, NORMAL_EXEC,
+								 1);
+			halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, true,
+						16);
+		}
+
+	}
+
+}
+
+
+void halbtc8723d2ant_action_a2dp_pan_hs(IN struct btc_coexist *btcoexist)
+{
+	static u8	prewifi_rssi_state = BTC_RSSI_STATE_LOW;
+	static u8	pre_bt_rssi_state = BTC_RSSI_STATE_LOW;
+	u8		wifi_rssi_state, bt_rssi_state;
+
+	static u8	prewifi_rssi_state2 = BTC_RSSI_STATE_LOW;
+	static u8	pre_bt_rssi_state2 = BTC_RSSI_STATE_LOW;
+	u8		wifi_rssi_state2, bt_rssi_state2;
+	boolean wifi_busy = false, wifi_turbo = false;
+
+
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy);
+	btcoexist->btc_get(btcoexist, BTC_GET_U1_AP_NUM,
+			   &coex_sta->scan_ap_num);
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			"############# [BTCoex],  scan_ap_num = %d, wl_noisy = %d\n",
+			coex_sta->scan_ap_num, coex_sta->wl_noisy_level);
+	BTC_TRACE(trace_buf);
+
+#if 1
+	if ((wifi_busy) && (coex_sta->wl_noisy_level == 0))
+		wifi_turbo = true;
+#endif
+
+
+	wifi_rssi_state = halbtc8723d2ant_wifi_rssi_state(btcoexist,
+			  &prewifi_rssi_state, 2,
+			  coex_sta->wifi_coex_thres , 0);
+
+	wifi_rssi_state2 = halbtc8723d2ant_wifi_rssi_state(btcoexist,
+			   &prewifi_rssi_state2, 2,
+			   coex_sta->wifi_coex_thres2 , 0);
+
+	bt_rssi_state = halbtc8723d2ant_bt_rssi_state(&pre_bt_rssi_state, 2,
+			coex_sta->bt_coex_thres , 0);
+
+	bt_rssi_state2 = halbtc8723d2ant_bt_rssi_state(&pre_bt_rssi_state2, 2,
+			 coex_sta->bt_coex_thres2 , 0);
+
+
+	if (BTC_RSSI_HIGH(wifi_rssi_state) &&
+		BTC_RSSI_HIGH(bt_rssi_state)) {
+
+		halbtc8723d2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0x18);
+		halbtc8723d2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);
+
+		coex_dm->is_switch_to_1dot5_ant = false;
+
+		halbtc8723d2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0);
+
+		halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 0);
+	} else if (BTC_RSSI_HIGH(wifi_rssi_state2) &&
+		   BTC_RSSI_HIGH(bt_rssi_state2)) {
+
+		halbtc8723d2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0x6);
+		halbtc8723d2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2);
+
+		coex_dm->is_switch_to_1dot5_ant = false;
+
+		halbtc8723d2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4);
+
+		if (wifi_busy) {
+
+			if ((coex_sta->a2dp_bit_pool > 40) &&
+				(coex_sta->a2dp_bit_pool < 255))
+				halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC,
+							true, 7);
+			else
+				halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC,
+							true, 5);
+		} else
+			halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, true,
+						6);
+
+	} else {
+
+		halbtc8723d2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0x18);
+		halbtc8723d2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);
+
+		coex_dm->is_switch_to_1dot5_ant = true;
+
+		if (wifi_turbo)
+			halbtc8723d2ant_coex_table_with_type(btcoexist,
+								 NORMAL_EXEC, 6);
+		else
+			halbtc8723d2ant_coex_table_with_type(btcoexist, NORMAL_EXEC,
+								 7);
+
+		if (wifi_busy) {
+
+			if ((coex_sta->a2dp_bit_pool > 40) &&
+				(coex_sta->a2dp_bit_pool < 255))
+				halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC,
+							true, 107);
+			else
+				halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC,
+							true, 105);
+		} else
+			halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, true,
+						106);
+
+	}
+
+}
+
+
+/* PAN(EDR)+A2DP */
+void halbtc8723d2ant_action_pan_edr_a2dp(IN struct btc_coexist *btcoexist)
+{
+	static u8	prewifi_rssi_state = BTC_RSSI_STATE_LOW;
+	static u8	pre_bt_rssi_state = BTC_RSSI_STATE_LOW;
+	u8		wifi_rssi_state, bt_rssi_state;
+
+	static u8	prewifi_rssi_state2 = BTC_RSSI_STATE_LOW;
+	static u8	pre_bt_rssi_state2 = BTC_RSSI_STATE_LOW;
+	u8		wifi_rssi_state2, bt_rssi_state2;
+	boolean wifi_busy = false, wifi_turbo = false;
+
+
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy);
+	btcoexist->btc_get(btcoexist, BTC_GET_U1_AP_NUM,
+			   &coex_sta->scan_ap_num);
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			"############# [BTCoex],  scan_ap_num = %d, wl_noisy = %d\n",
+			coex_sta->scan_ap_num, coex_sta->wl_noisy_level);
+	BTC_TRACE(trace_buf);
+
+#if 1
+	if ((wifi_busy) && (coex_sta->wl_noisy_level == 0))
+		wifi_turbo = true;
+#endif
+
+
+	wifi_rssi_state = halbtc8723d2ant_wifi_rssi_state(btcoexist,
+			  &prewifi_rssi_state, 2,
+			  coex_sta->wifi_coex_thres , 0);
+
+	wifi_rssi_state2 = halbtc8723d2ant_wifi_rssi_state(btcoexist,
+			   &prewifi_rssi_state2, 2,
+			   coex_sta->wifi_coex_thres2 , 0);
+
+	bt_rssi_state = halbtc8723d2ant_bt_rssi_state(&pre_bt_rssi_state, 2,
+			coex_sta->bt_coex_thres , 0);
+
+	bt_rssi_state2 = halbtc8723d2ant_bt_rssi_state(&pre_bt_rssi_state2, 2,
+			 coex_sta->bt_coex_thres2 , 0);
+
+	if (BTC_RSSI_HIGH(wifi_rssi_state) &&
+		BTC_RSSI_HIGH(bt_rssi_state)) {
+
+		halbtc8723d2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0x18);
+		halbtc8723d2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);
+
+		coex_dm->is_switch_to_1dot5_ant = false;
+
+		halbtc8723d2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0);
+		halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 0);
+	} else if (BTC_RSSI_HIGH(wifi_rssi_state2) &&
+		   BTC_RSSI_HIGH(bt_rssi_state2)) {
+
+		halbtc8723d2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0x6);
+		halbtc8723d2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2);
+
+		coex_dm->is_switch_to_1dot5_ant = false;
+
+		halbtc8723d2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4);
+
+		if (wifi_busy) {
+
+			if (((coex_sta->a2dp_bit_pool > 40) &&
+				 (coex_sta->a2dp_bit_pool < 255)) ||
+				(!coex_sta->is_A2DP_3M))
+				halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC,
+							true, 7);
+			else
+				halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC,
+							true, 5);
+		} else
+			halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, true,
+						6);
+	} else {
+
+		halbtc8723d2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0x18);
+		halbtc8723d2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);
+
+		coex_dm->is_switch_to_1dot5_ant = true;
+
+		if (wifi_turbo)
+			halbtc8723d2ant_coex_table_with_type(btcoexist,
+								 NORMAL_EXEC, 6);
+		else
+			halbtc8723d2ant_coex_table_with_type(btcoexist, NORMAL_EXEC,
+								 7);
+
+		if (wifi_busy) {
+
+			if ((coex_sta->a2dp_bit_pool > 40) &&
+				(coex_sta->a2dp_bit_pool < 255))
+				halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC,
+							true, 107);
+			else if (wifi_turbo)
+				halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC,
+							true, 108);
+			else
+				halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC,
+							true, 105);
+		} else
+			halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, true,
+						106);
+
+	}
+
+}
+
+
+void halbtc8723d2ant_action_pan_edr_hid(IN struct btc_coexist *btcoexist)
+{
+	static u8	prewifi_rssi_state = BTC_RSSI_STATE_LOW;
+	static u8	pre_bt_rssi_state = BTC_RSSI_STATE_LOW;
+	u8		wifi_rssi_state, bt_rssi_state;
+
+	static u8	prewifi_rssi_state2 = BTC_RSSI_STATE_LOW;
+	static u8	pre_bt_rssi_state2 = BTC_RSSI_STATE_LOW;
+	u8	wifi_rssi_state2, bt_rssi_state2;
+	boolean	wifi_busy = false;
+	u32 wifi_bw = 1;
+
+	btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW,
+			   &wifi_bw);
+
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy);
+
+	wifi_rssi_state = halbtc8723d2ant_wifi_rssi_state(btcoexist,
+			  &prewifi_rssi_state, 2,
+			  coex_sta->wifi_coex_thres , 0);
+
+	wifi_rssi_state2 = halbtc8723d2ant_wifi_rssi_state(btcoexist,
+			   &prewifi_rssi_state2, 2,
+			   coex_sta->wifi_coex_thres2 , 0);
+
+	bt_rssi_state = halbtc8723d2ant_bt_rssi_state(&pre_bt_rssi_state, 2,
+			coex_sta->bt_coex_thres , 0);
+
+	bt_rssi_state2 = halbtc8723d2ant_bt_rssi_state(&pre_bt_rssi_state2, 2,
+			 coex_sta->bt_coex_thres2 , 0);
+
+
+	if (BTC_RSSI_HIGH(wifi_rssi_state) &&
+		BTC_RSSI_HIGH(bt_rssi_state)) {
+
+		halbtc8723d2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0x18);
+		halbtc8723d2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);
+
+		coex_dm->is_switch_to_1dot5_ant = false;
+
+		halbtc8723d2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0);
+		halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 0);
+	} else if (BTC_RSSI_HIGH(wifi_rssi_state2) &&
+		   BTC_RSSI_HIGH(bt_rssi_state2)) {
+
+		halbtc8723d2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0x6);
+		halbtc8723d2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2);
+
+		coex_dm->is_switch_to_1dot5_ant = false;
+
+		halbtc8723d2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4);
+
+		if (wifi_busy)
+			halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, true,
+						3);
+		else
+			halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, true,
+						4);
+	} else {
+
+		halbtc8723d2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0x18);
+		halbtc8723d2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);
+
+		coex_dm->is_switch_to_1dot5_ant = true;
+
+		if (coex_sta->hid_busy_num >= 2) {
+
+			halbtc8723d2ant_coex_table_with_type(btcoexist,
+							 NORMAL_EXEC, 8);
+			if (wifi_bw == 0)  /*11bg mode */
+				halbtc8723d2ant_set_wltoggle_coex_table(btcoexist,
+								NORMAL_EXEC,
+								0x1, 0xaa,
+								0x5a, 0xaa,
+								0xaa);
+			else
+				halbtc8723d2ant_set_wltoggle_coex_table(btcoexist,
+								NORMAL_EXEC,
+								0x2, 0xaa,
+								0x5a, 0xaa,
+								0xaa);
+			halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, true,
+						110);
+		} else {
+
+			halbtc8723d2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 1);
+
+			if (wifi_busy)
+				halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, true,
+							103);
+			else
+				halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, true,
+							104);
+		}
+
+	}
+
+}
+
+
+/* HID+A2DP+PAN(EDR) */
+void halbtc8723d2ant_action_hid_a2dp_pan_edr(IN struct btc_coexist *btcoexist)
+{
+	static u8	prewifi_rssi_state = BTC_RSSI_STATE_LOW;
+	static u8	pre_bt_rssi_state = BTC_RSSI_STATE_LOW;
+	u8	wifi_rssi_state, bt_rssi_state;
+
+	static u8	prewifi_rssi_state2 = BTC_RSSI_STATE_LOW;
+	static u8	pre_bt_rssi_state2 = BTC_RSSI_STATE_LOW;
+	u8	wifi_rssi_state2, bt_rssi_state2;
+	boolean	wifi_busy = false;
+	u32 wifi_bw = 1;
+
+	btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW,
+			   &wifi_bw);
+
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy);
+
+	wifi_rssi_state = halbtc8723d2ant_wifi_rssi_state(btcoexist,
+			  &prewifi_rssi_state, 2,
+			  coex_sta->wifi_coex_thres , 0);
+
+	wifi_rssi_state2 = halbtc8723d2ant_wifi_rssi_state(btcoexist,
+			   &prewifi_rssi_state2, 2,
+			   coex_sta->wifi_coex_thres2 , 0);
+
+	bt_rssi_state = halbtc8723d2ant_bt_rssi_state(&pre_bt_rssi_state, 2,
+			coex_sta->bt_coex_thres , 0);
+
+	bt_rssi_state2 = halbtc8723d2ant_bt_rssi_state(&pre_bt_rssi_state2, 2,
+			 coex_sta->bt_coex_thres2 , 0);
+
+
+	if (BTC_RSSI_HIGH(wifi_rssi_state) &&
+		BTC_RSSI_HIGH(bt_rssi_state)) {
+
+		halbtc8723d2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0x18);
+		halbtc8723d2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);
+
+		coex_dm->is_switch_to_1dot5_ant = false;
+
+		halbtc8723d2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0);
+		halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 0);
+	} else if (BTC_RSSI_HIGH(wifi_rssi_state2) &&
+		   BTC_RSSI_HIGH(bt_rssi_state2)) {
+
+		halbtc8723d2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0x6);
+		halbtc8723d2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2);
+
+		coex_dm->is_switch_to_1dot5_ant = false;
+
+		halbtc8723d2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4);
+
+		if (wifi_busy) {
+
+			if (((coex_sta->a2dp_bit_pool > 40) &&
+				 (coex_sta->a2dp_bit_pool < 255)) ||
+				(!coex_sta->is_A2DP_3M))
+				halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC,
+							true, 7);
+			else
+				halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC,
+							true, 5);
+		} else
+			halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, true,
+						6);
+	} else {
+
+		halbtc8723d2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0x18);
+		halbtc8723d2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);
+
+		coex_dm->is_switch_to_1dot5_ant = true;
+
+		if (coex_sta->hid_busy_num >= 2) {
+			halbtc8723d2ant_coex_table_with_type(btcoexist,
+							 NORMAL_EXEC, 8);
+			if (wifi_bw == 0)  /*11bg mode */
+				halbtc8723d2ant_set_wltoggle_coex_table(btcoexist,
+								NORMAL_EXEC,
+								0x1, 0xaa,
+								0x5a, 0xaa,
+								0xaa);
+			else
+				halbtc8723d2ant_set_wltoggle_coex_table(btcoexist,
+								NORMAL_EXEC,
+								0x2, 0xaa,
+								0x5a, 0xaa,
+								0xaa);
+			halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, true,
+						110);
+		} else {
+			halbtc8723d2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 1);
+
+			if (wifi_busy) {
+
+				if ((coex_sta->a2dp_bit_pool > 40) &&
+					(coex_sta->a2dp_bit_pool < 255))
+					halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC,
+								true, 107);
+				else
+					halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC,
+								true, 105);
+			} else
+				halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, true,
+							106);
+		}
+	}
+
+}
+
+
+void halbtc8723d2ant_action_wifi_multi_port(IN struct btc_coexist *btcoexist)
+{
+	halbtc8723d2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0x18);
+	halbtc8723d2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);
+
+	/* hw all off */
+	halbtc8723d2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0);
+
+	halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 0);
+}
+
+void halbtc8723d2ant_action_wifi_linkscan_process(IN struct btc_coexist *btcoexist)
+{
+	struct	btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
+
+	halbtc8723d2ant_fw_dac_swing_lvl(btcoexist, FORCE_EXEC, 0x18);
+	halbtc8723d2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);
+
+	halbtc8723d2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 8);
+
+	if (bt_link_info->pan_exist) {
+
+		halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 22);
+
+		halbtc8723d2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 8);
+
+	} else if (bt_link_info->a2dp_exist) {
+
+		halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 16);
+
+		halbtc8723d2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 8);
+	} else {
+
+		halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 21);
+
+		halbtc8723d2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 8);
+	}
+
+}
+
+void halbtc8723d2ant_action_wifi_not_connected(IN struct btc_coexist *btcoexist)
+{
+	halbtc8723d2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0);
+
+	/* fw all off */
+	halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 0);
+
+	halbtc8723d2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0x18);
+	halbtc8723d2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);
+}
+
+void halbtc8723d2ant_action_wifi_connected(IN struct btc_coexist *btcoexist)
+{
+	switch (coex_dm->cur_algorithm) {
+
+	case BT_8723D_2ANT_COEX_ALGO_SCO:
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			"[BTCoex], Action 2-Ant, algorithm = SCO.\n");
+		BTC_TRACE(trace_buf);
+		halbtc8723d2ant_action_sco(btcoexist);
+		break;
+	case BT_8723D_2ANT_COEX_ALGO_HID:
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			"[BTCoex], Action 2-Ant, algorithm = HID.\n");
+		BTC_TRACE(trace_buf);
+		halbtc8723d2ant_action_hid(btcoexist);
+		break;
+	case BT_8723D_2ANT_COEX_ALGO_A2DP:
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			"[BTCoex], Action 2-Ant, algorithm = A2DP.\n");
+		BTC_TRACE(trace_buf);
+		halbtc8723d2ant_action_a2dp(btcoexist);
+		break;
+	case BT_8723D_2ANT_COEX_ALGO_A2DP_PANHS:
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			"[BTCoex], Action 2-Ant, algorithm = A2DP+PAN(HS).\n");
+		BTC_TRACE(trace_buf);
+		halbtc8723d2ant_action_a2dp_pan_hs(btcoexist);
+		break;
+	case BT_8723D_2ANT_COEX_ALGO_PANEDR:
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			"[BTCoex], Action 2-Ant, algorithm = PAN(EDR).\n");
+		BTC_TRACE(trace_buf);
+		halbtc8723d2ant_action_pan_edr(btcoexist);
+		break;
+	case BT_8723D_2ANT_COEX_ALGO_PANEDR_A2DP:
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			"[BTCoex], Action 2-Ant, algorithm = PAN+A2DP.\n");
+		BTC_TRACE(trace_buf);
+		halbtc8723d2ant_action_pan_edr_a2dp(btcoexist);
+		break;
+	case BT_8723D_2ANT_COEX_ALGO_PANEDR_HID:
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			"[BTCoex], Action 2-Ant, algorithm = PAN(EDR)+HID.\n");
+		BTC_TRACE(trace_buf);
+		halbtc8723d2ant_action_pan_edr_hid(btcoexist);
+		break;
+	case BT_8723D_2ANT_COEX_ALGO_HID_A2DP_PANEDR:
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			"[BTCoex], Action 2-Ant, algorithm = HID+A2DP+PAN.\n");
+		BTC_TRACE(trace_buf);
+		halbtc8723d2ant_action_hid_a2dp_pan_edr(
+			btcoexist);
+		break;
+	case BT_8723D_2ANT_COEX_ALGO_HID_A2DP:
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			"[BTCoex], Action 2-Ant, algorithm = HID+A2DP.\n");
+		BTC_TRACE(trace_buf);
+		halbtc8723d2ant_action_hid_a2dp(btcoexist);
+		break;
+	case BT_8723D_2ANT_COEX_ALGO_NOPROFILEBUSY:
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			"[BTCoex], Action 2-Ant, algorithm = No-Profile busy.\n");
+		BTC_TRACE(trace_buf);
+		halbtc8723d2ant_action_bt_idle(btcoexist);
+		break;
+	default:
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			"[BTCoex], Action 2-Ant, algorithm = coexist All Off!!\n");
+		BTC_TRACE(trace_buf);
+		halbtc8723d2ant_action_coex_all_off(btcoexist);
+		break;
+		}
+
+	 coex_dm->pre_algorithm = coex_dm->cur_algorithm;
+
+}
+
+
+void halbtc8723d2ant_run_coexist_mechanism(IN struct btc_coexist *btcoexist)
+{
+	u8	algorithm = 0;
+	u32	num_of_wifi_link = 0;
+	u32	wifi_link_status = 0;
+	struct	btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
+	boolean miracast_plus_bt = false;
+	boolean	scan = false, link = false, roam = false,
+			under_4way = false,
+			wifi_connected = false, wifi_under_5g = false,
+			bt_hs_on = false;
+
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_SCAN, &scan);
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_LINK, &link);
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_ROAM, &roam);
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_4_WAY_PROGRESS,
+			   &under_4way);
+
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			"[BTCoex], RunCoexistMechanism()===>\n");
+	BTC_TRACE(trace_buf);
+
+	if (btcoexist->manual_control) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			"[BTCoex], RunCoexistMechanism(), return for Manual CTRL <===\n");
+		BTC_TRACE(trace_buf);
+		return;
+	}
+
+	if (btcoexist->stop_coex_dm) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			"[BTCoex], RunCoexistMechanism(), return for Stop Coex DM <===\n");
+		BTC_TRACE(trace_buf);
+		return;
+	}
+
+	if (coex_sta->under_ips) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				"[BTCoex], wifi is under IPS !!!\n");
+		BTC_TRACE(trace_buf);
+		return;
+	}
+
+	if (!coex_sta->run_time_state) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			"[BTCoex], return for run_time_state = false !!!\n");
+		BTC_TRACE(trace_buf);
+		return;
+	}
+
+	if (coex_sta->freeze_coexrun_by_btinfo) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			"[BTCoex], BtInfoNotify(), return for freeze_coexrun_by_btinfo\n");
+		BTC_TRACE(trace_buf);
+		return;
+	}
+
+	if (coex_sta->bt_whck_test) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				"[BTCoex], BT is under WHCK TEST!!!\n");
+		BTC_TRACE(trace_buf);
+		halbtc8723d2ant_action_bt_whql_test(btcoexist);
+		return;
+	}
+
+	if (coex_sta->bt_disabled) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				 "[BTCoex], BT is disabled!!!\n");
+		BTC_TRACE(trace_buf);
+		halbtc8723d2ant_action_coex_all_off(btcoexist);
+		return;
+	}
+
+	if (coex_sta->c2h_bt_inquiry_page) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				"[BTCoex], BT is under inquiry/page scan !!\n");
+		BTC_TRACE(trace_buf);
+		halbtc8723d2ant_action_bt_inquiry(btcoexist);
+		return;
+	}
+
+	if (coex_sta->is_setupLink) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				 "[BTCoex], BT is re-link !!!\n");
+		halbtc8723d2ant_action_bt_relink(btcoexist);
+		return;
+	}
+
+	/* for P2P */
+	btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_LINK_STATUS,
+			   &wifi_link_status);
+	num_of_wifi_link = wifi_link_status >> 16;
+
+	if ((num_of_wifi_link >= 2) ||
+		(wifi_link_status & WIFI_P2P_GO_CONNECTED)) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			"############# [BTCoex],  Multi-Port num_of_wifi_link = %d, wifi_link_status = 0x%x\n",
+				num_of_wifi_link, wifi_link_status);
+		BTC_TRACE(trace_buf);
+
+		if (bt_link_info->bt_link_exist)
+			miracast_plus_bt = true;
+		else
+			miracast_plus_bt = false;
+
+		btcoexist->btc_set(btcoexist, BTC_SET_BL_MIRACAST_PLUS_BT,
+				   &miracast_plus_bt);
+
+		if (scan || link || roam || under_4way) {
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				"[BTCoex], scan = %d, link = %d, roam = %d 4way = %d!!!\n",
+				    scan, link, roam, under_4way);
+			BTC_TRACE(trace_buf);
+
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				"[BTCoex], wifi is under linkscan process + Multi-Port !!\n");
+			BTC_TRACE(trace_buf);
+
+			halbtc8723d2ant_action_wifi_linkscan_process(btcoexist);
+		} else
+
+			halbtc8723d2ant_action_wifi_multi_port(btcoexist);
+
+		return;
+	} else {
+		miracast_plus_bt = false;
+		btcoexist->btc_set(btcoexist, BTC_SET_BL_MIRACAST_PLUS_BT,
+				   &miracast_plus_bt);
+	}
+
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on);
+
+	if (bt_hs_on) {
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+					"############# [BTCoex],  BT Is hs\n");
+			BTC_TRACE(trace_buf);
+			halbtc8723d2ant_action_bt_hs(btcoexist);
+			return;
+	}
+
+	if ((BT_8723D_2ANT_BT_STATUS_NON_CONNECTED_IDLE ==
+			coex_dm->bt_status) ||
+		   (BT_8723D_2ANT_BT_STATUS_CONNECTED_IDLE ==
+			coex_dm->bt_status)) {
+
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				"[BTCoex], Action 2-Ant, bt idle!!.\n");
+		BTC_TRACE(trace_buf);
+
+		halbtc8723d2ant_action_bt_idle(btcoexist);
+		return;
+	}
+
+	algorithm = halbtc8723d2ant_action_algorithm(btcoexist);
+	coex_dm->cur_algorithm = algorithm;
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], Algorithm = %d\n",
+			coex_dm->cur_algorithm);
+	BTC_TRACE(trace_buf);
+
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED,
+			   &wifi_connected);
+
+	if (scan || link || roam || under_4way) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				"[BTCoex], WiFi is under Link Process !!\n");
+		BTC_TRACE(trace_buf);
+		halbtc8723d2ant_action_wifi_linkscan_process(btcoexist);
+	} else if (wifi_connected) {
+
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				"[BTCoex], Action 2-Ant, wifi connected!!.\n");
+		BTC_TRACE(trace_buf);
+		halbtc8723d2ant_action_wifi_connected(btcoexist);
+
+	} else {
+
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				"[BTCoex], Action 2-Ant, wifi not-connected!!.\n");
+		BTC_TRACE(trace_buf);
+		halbtc8723d2ant_action_wifi_not_connected(btcoexist);
+	}
+}
+
+
+void halbtc8723d2ant_init_coex_dm(IN struct btc_coexist *btcoexist)
+{
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+		    "[BTCoex], Coex Mechanism Init!!\n");
+	BTC_TRACE(trace_buf);
+
+	halbtc8723d2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0x18);
+	halbtc8723d2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);
+
+	/* sw all off */
+	halbtc8723d2ant_low_penalty_ra(btcoexist, NORMAL_EXEC, false);
+
+	coex_sta->pop_event_cnt = 0;
+	coex_sta->cnt_RemoteNameReq = 0;
+	coex_sta->cnt_ReInit = 0;
+	coex_sta->cnt_setupLink = 0;
+	coex_sta->cnt_IgnWlanAct = 0;
+	coex_sta->cnt_Page = 0;
+
+	halbtc8723d2ant_query_bt_info(btcoexist);
+}
+
+
+void halbtc8723d2ant_init_hw_config(IN struct btc_coexist *btcoexist,
+				    IN boolean wifi_only)
+{
+	u8	u8tmp0 = 0, u8tmp1 = 0;
+	u32	vendor;
+	u32	u32tmp0 = 0, u32tmp1 = 0, u32tmp2 = 0;
+	u16 u16tmp1 = 0;
+	u8 i = 0;
+
+
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+		    "[BTCoex], 2Ant Init HW Config!!\n");
+	BTC_TRACE(trace_buf);
+
+#if BT_8723D_2ANT_COEX_DBG
+	u32tmp1 = halbtc8723d2ant_ltecoex_indirect_read_reg(btcoexist,
+			0x38);
+	u32tmp2 = halbtc8723d2ant_ltecoex_indirect_read_reg(btcoexist,
+			0x54);
+	u16tmp1 = btcoexist->btc_read_2byte(btcoexist, 0x948);
+	u8tmp1	= btcoexist->btc_read_1byte(btcoexist, 0x73);
+	u8tmp0 =  btcoexist->btc_read_1byte(btcoexist, 0x67);
+
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+		"[BTCoex], ********** 0x67 = 0x%x, 0x948 = 0x%x, 0x73 = 0x%x(Before init_hw_config)\n",
+		    u8tmp0, u16tmp1, u8tmp1);
+	BTC_TRACE(trace_buf);
+
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+		"[BTCoex], **********0x38= 0x%x, 0x54= 0x%x (Before init_hw_config)\n",
+		    u32tmp1, u32tmp2);
+	BTC_TRACE(trace_buf);
+#endif
+
+
+	coex_sta->bt_coex_supported_feature = 0;
+	coex_sta->bt_coex_supported_version = 0;
+	coex_sta->bt_ble_scan_type = 0;
+	coex_sta->bt_ble_scan_para[0] = 0;
+	coex_sta->bt_ble_scan_para[1] = 0;
+	coex_sta->bt_ble_scan_para[2] = 0;
+	coex_sta->bt_reg_vendor_ac = 0xffff;
+	coex_sta->bt_reg_vendor_ae = 0xffff;
+	coex_sta->gnt_error_cnt = 0;
+	coex_sta->bt_relink_downcount = 0;
+
+	for (i = 0; i <= 9; i++)
+		coex_sta->bt_afh_map[i] = 0;
+
+#if 0
+	btcoexist->btc_get(btcoexist, BTC_GET_U4_VENDOR, &vendor);
+	if (vendor == BTC_VENDOR_LENOVO)
+		coex_dm->switch_thres_offset = 0;
+	else
+		coex_dm->switch_thres_offset = 20;
+#endif
+	/* 0xf0[15:12] --> Chip Cut information */
+	coex_sta->cut_version = (btcoexist->btc_read_1byte(btcoexist,
+				 0xf1) & 0xf0) >> 4;
+
+	coex_sta->dis_ver_info_cnt = 0;
+
+	/* default isolation = 15dB */
+	coex_sta->isolation_btween_wb = BT_8723D_2ANT_DEFAULT_ISOLATION;
+	halbtc8723d2ant_coex_switch_threshold(btcoexist,
+					      coex_sta->isolation_btween_wb);
+
+	btcoexist->btc_write_1byte_bitmask(btcoexist, 0x550, 0x8,
+					   0x1);  /* enable TBTT nterrupt */
+
+	/* BT report packet sample rate	 */
+	btcoexist->btc_write_1byte(btcoexist, 0x790, 0x5);
+
+	/* Init 0x778 = 0x1 for 2-Ant */
+	btcoexist->btc_write_1byte(btcoexist, 0x778, 0x1);
+
+	/* Enable PTA (3-wire function form BT side) */
+	btcoexist->btc_write_1byte_bitmask(btcoexist, 0x40, 0x20, 0x1);
+	btcoexist->btc_write_1byte_bitmask(btcoexist, 0x41, 0x02, 0x1);
+
+	/* Enable PTA (tx/rx signal form WiFi side) */
+	btcoexist->btc_write_1byte_bitmask(btcoexist, 0x4c6, 0x10, 0x1);
+
+	halbtc8723d2ant_enable_gnt_to_gpio(btcoexist, true);
+
+#if 0
+	/* check if WL firmware download ok */
+	if (btcoexist->btc_read_1byte(btcoexist, 0x80) == 0xc6)
+		halbtc8723d2ant_post_state_to_bt(btcoexist,
+					 BT_8723D_2ANT_SCOREBOARD_ONOFF, true);
+#endif
+
+	/* Enable counter statistics */
+	btcoexist->btc_write_1byte(btcoexist, 0x76e,
+			   0x4); /* 0x76e[3] =1, WLAN_Act control by PTA */
+
+	/* WLAN_Tx by GNT_WL  0x950[29] = 0 */
+	btcoexist->btc_write_1byte_bitmask(btcoexist, 0x953, 0x20, 0x0);
+
+	halbtc8723d2ant_coex_table_with_type(btcoexist, FORCE_EXEC, 0);
+
+	halbtc8723d2ant_ps_tdma(btcoexist, FORCE_EXEC, false, 0);
+
+	psd_scan->ant_det_is_ant_det_available = true;
+
+	if (wifi_only) {
+		coex_sta->concurrent_rx_mode_on = false;
+		/* Path config	 */
+		/* Set Antenna Path */
+		halbtc8723d2ant_set_ant_path(btcoexist,
+					     BTC_ANT_PATH_AUTO,
+					     FORCE_EXEC,
+					     BT_8723D_2ANT_PHASE_WLANONLY_INIT);
+
+		btcoexist->stop_coex_dm = true;
+	} else {
+		/*Set BT polluted packet on for Tx rate adaptive not including Tx retry break by PTA, 0x45c[19] =1 */
+		btcoexist->btc_write_1byte_bitmask(btcoexist, 0x45e, 0x8, 0x1);
+
+		coex_sta->concurrent_rx_mode_on = true;
+		/* btcoexist->btc_write_1byte_bitmask(btcoexist, 0x953, 0x2, 0x1); */
+
+		/* RF 0x1[0] = 0->Set GNT_WL_RF_Rx always = 1 for con-current Rx */
+		btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1, 0x1, 0x0);
+
+		/* Path config	 */
+		halbtc8723d2ant_set_ant_path(btcoexist,
+					     BTC_ANT_PATH_AUTO,
+					     FORCE_EXEC,
+					     BT_8723D_2ANT_PHASE_COEX_INIT);
+
+		btcoexist->stop_coex_dm = false;
+	}
+
+
+}
+
+u32 halbtc8723d2ant_psd_log2base(IN struct btc_coexist *btcoexist, IN u32 val)
+{
+	u8	j;
+	u32	tmp, tmp2, val_integerd_b = 0, tindex, shiftcount = 0;
+	u32	result, val_fractiond_b = 0, table_fraction[21] = {0, 432, 332, 274, 232, 200,
+				   174, 151, 132, 115, 100, 86, 74, 62, 51, 42,
+							   32, 23, 15, 7, 0
+							      };
+
+	if (val == 0)
+		return 0;
+
+	tmp = val;
+
+	while (1) {
+		if (tmp == 1)
+			break;
+		else {
+			tmp = (tmp >> 1);
+			shiftcount++;
+		}
+	}
+
+
+	val_integerd_b = shiftcount + 1;
+
+	tmp2 = 1;
+	for (j = 1; j <= val_integerd_b; j++)
+		tmp2 = tmp2 * 2;
+
+	tmp = (val * 100) / tmp2;
+	tindex = tmp / 5;
+
+	if (tindex > 20)
+		tindex = 20;
+
+	val_fractiond_b = table_fraction[tindex];
+
+	result = val_integerd_b * 100 - val_fractiond_b;
+
+	return result;
+
+
+}
+
+void halbtc8723d2ant_psd_show_antenna_detect_result(IN struct btc_coexist
+		*btcoexist)
+{
+	u8		*cli_buf = btcoexist->cli_buf;
+	struct  btc_board_info	*board_info = &btcoexist->board_info;
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+		   "\r\n============[Antenna Detection info]  ============\n");
+	CL_PRINTF(cli_buf);
+
+	if (psd_scan->ant_det_result == 12) { /* Get Ant Det from BT  */
+
+		if (board_info->btdm_ant_num_by_ant_det == 1)
+			CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+				   "\r\n %-35s = %s (%d~%d)",
+				   "Ant Det Result", "1-Antenna",
+				   BT_8723D_2ANT_ANTDET_PSDTHRES_1ANT,
+				BT_8723D_2ANT_ANTDET_PSDTHRES_2ANT_GOODISOLATION);
+		else {
+
+			if (psd_scan->ant_det_psd_scan_peak_val >
+			    (BT_8723D_2ANT_ANTDET_PSDTHRES_2ANT_BADISOLATION)
+			    * 100)
+				CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+					   "\r\n %-35s = %s (>%d)",
+					"Ant Det Result", "2-Antenna (Bad-Isolation)",
+					BT_8723D_2ANT_ANTDET_PSDTHRES_2ANT_BADISOLATION);
+			else
+				CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+					   "\r\n %-35s = %s (%d~%d)",
+					"Ant Det Result", "2-Antenna (Good-Isolation)",
+					BT_8723D_2ANT_ANTDET_PSDTHRES_2ANT_GOODISOLATION
+					   + psd_scan->ant_det_thres_offset,
+					BT_8723D_2ANT_ANTDET_PSDTHRES_2ANT_BADISOLATION);
+		}
+
+	} else if (psd_scan->ant_det_result == 1)
+		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s (>%d)",
+			   "Ant Det Result", "2-Antenna (Bad-Isolation)",
+			   BT_8723D_2ANT_ANTDET_PSDTHRES_2ANT_BADISOLATION);
+	else if (psd_scan->ant_det_result == 2)
+		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s (%d~%d)",
+			   "Ant Det Result", "2-Antenna (Good-Isolation)",
+			   BT_8723D_2ANT_ANTDET_PSDTHRES_2ANT_GOODISOLATION
+			   + psd_scan->ant_det_thres_offset,
+			   BT_8723D_2ANT_ANTDET_PSDTHRES_2ANT_BADISOLATION);
+	else
+		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s (%d~%d)",
+			   "Ant Det Result", "1-Antenna",
+			   BT_8723D_2ANT_ANTDET_PSDTHRES_1ANT,
+			   BT_8723D_2ANT_ANTDET_PSDTHRES_2ANT_GOODISOLATION
+			   + psd_scan->ant_det_thres_offset);
+
+	CL_PRINTF(cli_buf);
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s ",
+		   "Antenna Detection Finish",
+		   (board_info->btdm_ant_det_finish
+		    ? "Yes" : "No"));
+	CL_PRINTF(cli_buf);
+
+	switch (psd_scan->ant_det_result) {
+	case 0:
+		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+			   "(BT is not available)");
+		break;
+	case 1:  /* 2-Ant bad-isolation */
+		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+			   "(BT is available)");
+		break;
+	case 2:  /* 2-Ant good-isolation */
+		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+			   "(BT is available)");
+		break;
+	case 3:  /* 1-Ant */
+		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+			   "(BT is available)");
+		break;
+	case 4:
+		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+			   "(Uncertainty result)");
+		break;
+	case 5:
+		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "(Pre-Scan fai)");
+		break;
+	case 6:
+		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+			   "(WiFi is Scanning)");
+		break;
+	case 7:
+		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+			   "(BT is not idle)");
+		break;
+	case 8:
+		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+			   "(Abort by WiFi Scanning)");
+		break;
+	case 9:
+		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+			   "(Antenna Init is not ready)");
+		break;
+	case 10:
+		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+			   "(BT is Inquiry or page)");
+		break;
+	case 11:
+		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+			   "(BT is Disabled)");
+	case 12:
+		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+			   "(BT is available, result from BT");
+		break;
+	}
+	CL_PRINTF(cli_buf);
+
+	if (psd_scan->ant_det_result == 12) {
+		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d dB",
+			   "PSD Scan Peak Value",
+			   psd_scan->ant_det_psd_scan_peak_val / 100);
+		CL_PRINTF(cli_buf);
+		return;
+	}
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d",
+		   "Ant Detect Total Count", psd_scan->ant_det_try_count);
+	CL_PRINTF(cli_buf);
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d",
+		   "Ant Detect Fail Count", psd_scan->ant_det_fail_count);
+	CL_PRINTF(cli_buf);
+
+	if ((!board_info->btdm_ant_det_finish) &&
+	    (psd_scan->ant_det_result != 5))
+		return;
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s", "BT Response",
+		   (psd_scan->ant_det_result ? "ok" : "fail"));
+	CL_PRINTF(cli_buf);
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d ms", "BT Tx Time",
+		   psd_scan->ant_det_bt_tx_time);
+	CL_PRINTF(cli_buf);
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d", "BT Tx Ch",
+		   psd_scan->ant_det_bt_le_channel);
+	CL_PRINTF(cli_buf);
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d",
+		   "WiFi PSD Cent-Ch/Offset/Span",
+		   psd_scan->real_cent_freq, psd_scan->real_offset,
+		   psd_scan->real_span);
+	CL_PRINTF(cli_buf);
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d dB",
+		   "PSD Pre-Scan Peak Value",
+		   psd_scan->ant_det_pre_psdscan_peak_val / 100);
+	CL_PRINTF(cli_buf);
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s (<= %d)",
+		   "PSD Pre-Scan result",
+		   (psd_scan->ant_det_result != 5 ? "ok" : "fail"),
+		   BT_8723D_2ANT_ANTDET_PSDTHRES_BACKGROUND
+		   + psd_scan->ant_det_thres_offset);
+	CL_PRINTF(cli_buf);
+
+	if (psd_scan->ant_det_result == 5)
+		return;
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s dB",
+		   "PSD Scan Peak Value", psd_scan->ant_det_peak_val);
+	CL_PRINTF(cli_buf);
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s MHz",
+		   "PSD Scan Peak Freq", psd_scan->ant_det_peak_freq);
+	CL_PRINTF(cli_buf);
+
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s", "TFBGA Package",
+		   (board_info->tfbga_package) ?  "Yes" : "No");
+	CL_PRINTF(cli_buf);
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d",
+		   "PSD Threshold Offset", psd_scan->ant_det_thres_offset);
+	CL_PRINTF(cli_buf);
+
+}
+
+void halbtc8723d2ant_psd_showdata(IN struct btc_coexist *btcoexist)
+{
+	u8		*cli_buf = btcoexist->cli_buf;
+	u32		delta_freq_per_point;
+	u32		freq, freq1, freq2, n = 0, i = 0, j = 0, m = 0, psd_rep1, psd_rep2;
+
+	if (psd_scan->ant_det_result == 12)
+		return;
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+		   "\r\n\n============[PSD info]  (%d)============\n",
+		   psd_scan->psd_gen_count);
+	CL_PRINTF(cli_buf);
+
+	if (psd_scan->psd_gen_count == 0) {
+		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n No data !!\n");
+		CL_PRINTF(cli_buf);
+		return;
+	}
+
+	if (psd_scan->psd_point == 0)
+		delta_freq_per_point = 0;
+	else
+		delta_freq_per_point = psd_scan->psd_band_width /
+				       psd_scan->psd_point;
+
+	/* if (psd_scan->is_psd_show_max_only) */
+	if (0) {
+		psd_rep1 = psd_scan->psd_max_value / 100;
+		psd_rep2 = psd_scan->psd_max_value - psd_rep1 * 100;
+
+		freq = ((psd_scan->real_cent_freq - 20) * 1000000 +
+			psd_scan->psd_max_value_point * delta_freq_per_point);
+		freq1 = freq / 1000000;
+		freq2 = freq / 1000 - freq1 * 1000;
+
+		if (freq2 < 100)
+			CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+				   "\r\n Freq = %d.0%d MHz",
+				   freq1, freq2);
+		else
+			CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+				   "\r\n Freq = %d.%d MHz",
+				   freq1, freq2);
+
+		if (psd_rep2 < 10)
+			CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+				   ", Value = %d.0%d dB, (%d)\n",
+				   psd_rep1, psd_rep2, psd_scan->psd_max_value);
+		else
+			CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+				   ", Value = %d.%d dB, (%d)\n",
+				   psd_rep1, psd_rep2, psd_scan->psd_max_value);
+
+		CL_PRINTF(cli_buf);
+	} else {
+		m = psd_scan->psd_start_point;
+		n = psd_scan->psd_start_point;
+		i = 1;
+		j = 1;
+
+		while (1) {
+			do {
+				freq = ((psd_scan->real_cent_freq - 20) *
+					1000000 + m *
+					delta_freq_per_point);
+				freq1 = freq / 1000000;
+				freq2 = freq / 1000 - freq1 * 1000;
+
+				if (i == 1) {
+					if (freq2 == 0)
+						CL_SPRINTF(cli_buf,
+							   BT_TMP_BUF_SIZE,
+							   "\r\n Freq%6d.000",
+							   freq1);
+					else if (freq2 < 100)
+						CL_SPRINTF(cli_buf,
+							   BT_TMP_BUF_SIZE,
+							   "\r\n Freq%6d.0%2d",
+							   freq1,
+							   freq2);
+					else
+						CL_SPRINTF(cli_buf,
+							   BT_TMP_BUF_SIZE,
+							   "\r\n Freq%6d.%3d",
+							   freq1,
+							   freq2);
+				} else if ((i % 8 == 0) ||
+					   (m == psd_scan->psd_stop_point)) {
+					if (freq2 == 0)
+						CL_SPRINTF(cli_buf,
+							   BT_TMP_BUF_SIZE,
+							   "%6d.000\n", freq1);
+					else if (freq2 < 100)
+						CL_SPRINTF(cli_buf,
+							   BT_TMP_BUF_SIZE,
+							   "%6d.0%2d\n", freq1,
+							   freq2);
+					else
+						CL_SPRINTF(cli_buf,
+							   BT_TMP_BUF_SIZE,
+							   "%6d.%3d\n", freq1,
+							   freq2);
+				} else {
+					if (freq2 == 0)
+						CL_SPRINTF(cli_buf,
+							   BT_TMP_BUF_SIZE,
+							   "%6d.000", freq1);
+					else if (freq2 < 100)
+						CL_SPRINTF(cli_buf,
+							   BT_TMP_BUF_SIZE,
+							   "%6d.0%2d", freq1,
+							   freq2);
+					else
+						CL_SPRINTF(cli_buf,
+							   BT_TMP_BUF_SIZE,
+							   "%6d.%3d", freq1,
+							   freq2);
+				}
+
+				i++;
+				m++;
+				CL_PRINTF(cli_buf);
+
+			} while ((i <= 8) && (m <= psd_scan->psd_stop_point));
+
+
+			do {
+				psd_rep1 = psd_scan->psd_report_max_hold[n] /
+					   100;
+				psd_rep2 = psd_scan->psd_report_max_hold[n] -
+					   psd_rep1 *
+					   100;
+
+				if (j == 1) {
+					if (psd_rep2 < 10)
+						CL_SPRINTF(cli_buf,
+							   BT_TMP_BUF_SIZE,
+							   "\r\n Val %7d.0%d",
+							   psd_rep1,
+							   psd_rep2);
+					else
+						CL_SPRINTF(cli_buf,
+							   BT_TMP_BUF_SIZE,
+							   "\r\n Val %7d.%d",
+							   psd_rep1,
+							   psd_rep2);
+				} else if ((j % 8 == 0)  ||
+					   (n == psd_scan->psd_stop_point)) {
+					if (psd_rep2 < 10)
+						CL_SPRINTF(cli_buf,
+							   BT_TMP_BUF_SIZE,
+							"%7d.0%d\n", psd_rep1,
+							   psd_rep2);
+					else
+						CL_SPRINTF(cli_buf,
+							   BT_TMP_BUF_SIZE,
+							   "%7d.%d\n", psd_rep1,
+							   psd_rep2);
+				} else {
+					if (psd_rep2 < 10)
+						CL_SPRINTF(cli_buf,
+							   BT_TMP_BUF_SIZE,
+							   "%7d.0%d", psd_rep1,
+							   psd_rep2);
+					else
+						CL_SPRINTF(cli_buf,
+							   BT_TMP_BUF_SIZE,
+							   "%7d.%d", psd_rep1,
+							   psd_rep2);
+				}
+
+				j++;
+				n++;
+				CL_PRINTF(cli_buf);
+
+			} while ((j <= 8) && (n <= psd_scan->psd_stop_point));
+
+			if ((m > psd_scan->psd_stop_point) ||
+			    (n > psd_scan->psd_stop_point))
+				break;
+			else {
+				i = 1;
+				j = 1;
+			}
+
+		}
+	}
+
+
+}
+
+#ifdef PLATFORM_WINDOWS
+#pragma optimize("", off)
+#endif
+void halbtc8723d2ant_psd_maxholddata(IN struct btc_coexist *btcoexist,
+				     IN u32 gen_count)
+{
+	u32 i = 0;
+	u32 loop_i_max = 0, loop_val_max = 0;
+
+	if (gen_count == 1) {
+		memcpy(psd_scan->psd_report_max_hold,
+		       psd_scan->psd_report,
+		       BT_8723D_2ANT_ANTDET_PSD_POINTS * sizeof(u32));
+	}
+
+	for (i = psd_scan->psd_start_point;
+	     i <= psd_scan->psd_stop_point; i++) {
+
+		/* update max-hold value at each freq point */
+		if (psd_scan->psd_report[i] > psd_scan->psd_report_max_hold[i])
+			psd_scan->psd_report_max_hold[i] =
+				psd_scan->psd_report[i];
+
+		/*	search the max value in this seep */
+		if (psd_scan->psd_report[i] > loop_val_max) {
+			loop_val_max = psd_scan->psd_report[i];
+			loop_i_max = i;
+		}
+	}
+
+	if (gen_count <= BT_8723D_2ANT_ANTDET_PSD_SWWEEPCOUNT)
+		psd_scan->psd_loop_max_value[gen_count - 1] = loop_val_max;
+
+}
+
+
+#ifdef PLATFORM_WINDOWS
+#pragma optimize("", off)
+#endif
+u32 halbtc8723d2ant_psd_getdata(IN struct btc_coexist *btcoexist, IN u32 point)
+{
+	/* reg 0x808[9:0]: FFT data x */
+	/* reg 0x808[22]: 0-->1 to get 1 FFT data y */
+	/* reg 0x8b4[15:0]: FFT data y report */
+
+	u32 val = 0, psd_report = 0;
+	int k = 0;
+
+	val = btcoexist->btc_read_4byte(btcoexist, 0x808);
+
+	val &= 0xffbffc00;
+	val |= point;
+
+	btcoexist->btc_write_4byte(btcoexist, 0x808, val);
+
+	val |= 0x00400000;
+	btcoexist->btc_write_4byte(btcoexist, 0x808, val);
+
+	while (1) {
+		if (k++ > BT_8723D_2ANT_ANTDET_SWEEPPOINT_DELAY)
+			break;
+	}
+
+	val = btcoexist->btc_read_4byte(btcoexist, 0x8b4);
+
+	psd_report = val & 0x0000ffff;
+
+	return psd_report;
+}
+
+#ifdef PLATFORM_WINDOWS
+#pragma optimize("", off)
+#endif
+boolean halbtc8723d2ant_psd_sweep_point(IN struct btc_coexist *btcoexist,
+		IN u32 cent_freq, IN s32 offset, IN u32 span, IN u32 points,
+					IN u32 avgnum, IN u32 loopcnt)
+{
+	u32	 i = 0, val = 0, n = 0, k = 0, j, point_index = 0;
+	u32	points1 = 0, psd_report = 0;
+	u32	start_p = 0, stop_p = 0, delta_freq_per_point = 156250;
+	u32    psd_center_freq = 20 * 10 ^ 6;
+	boolean outloop = false, scan , roam, is_sweep_ok = true;
+	u8	 flag = 0;
+	u32	tmp = 0, u32tmp1 = 0;
+	u32	wifi_original_channel = 1;
+	u32 psd_sum = 0, avg_cnt = 0;
+	u32	i_max = 0, val_max = 0, val_max2 = 0;
+
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+		    "xxxxxxxxxxxxxxxx PSD Sweep Start!!\n");
+	BTC_TRACE(trace_buf);
+
+	do {
+		switch (flag) {
+		case 0:  /* Get PSD parameters */
+		default:
+
+			psd_scan->psd_band_width = 40 * 1000000;
+			psd_scan->psd_point = points;
+			psd_scan->psd_start_base = points / 2;
+			psd_scan->psd_avg_num = avgnum;
+			psd_scan->real_cent_freq = cent_freq;
+			psd_scan->real_offset = offset;
+			psd_scan->real_span = span;
+
+
+			points1 = psd_scan->psd_point;
+			delta_freq_per_point = psd_scan->psd_band_width /
+					       psd_scan->psd_point;
+
+			/* PSD point setup */
+			val = btcoexist->btc_read_4byte(btcoexist, 0x808);
+			val &= 0xffff0fff;
+
+			switch (psd_scan->psd_point) {
+			case 128:
+				val |= 0x0;
+				break;
+			case 256:
+			default:
+				val |= 0x00004000;
+				break;
+			case 512:
+				val |= 0x00008000;
+				break;
+			case 1024:
+				val |= 0x0000c000;
+				break;
+			}
+
+			switch (psd_scan->psd_avg_num) {
+			case 1:
+				val |= 0x0;
+				break;
+			case 8:
+				val |= 0x00001000;
+				break;
+			case 16:
+				val |= 0x00002000;
+				break;
+			case 32:
+			default:
+				val |= 0x00003000;
+				break;
+			}
+			btcoexist->btc_write_4byte(btcoexist, 0x808, val);
+
+			flag = 1;
+			break;
+		case 1:	  /* calculate the PSD point index from freq/offset/span */
+			psd_center_freq = psd_scan->psd_band_width / 2 +
+					  offset * (1000000);
+
+			start_p = psd_scan->psd_start_base + (psd_center_freq -
+				span * (1000000) / 2) / delta_freq_per_point;
+			psd_scan->psd_start_point = start_p -
+						    psd_scan->psd_start_base;
+
+			stop_p = psd_scan->psd_start_base + (psd_center_freq +
+				span * (1000000) / 2) / delta_freq_per_point;
+			psd_scan->psd_stop_point = stop_p -
+						   psd_scan->psd_start_base - 1;
+
+			flag = 2;
+			break;
+		case 2:  /* set RF channel/BW/Mode */
+
+			/* set 3-wire off */
+			val = btcoexist->btc_read_4byte(btcoexist, 0x88c);
+			val |= 0x00300000;
+			btcoexist->btc_write_4byte(btcoexist, 0x88c, val);
+
+			/* CCK off */
+			val = btcoexist->btc_read_4byte(btcoexist, 0x800);
+			val &= 0xfeffffff;
+			btcoexist->btc_write_4byte(btcoexist, 0x800, val);
+
+			/* Tx-pause on */
+			btcoexist->btc_write_1byte(btcoexist, 0x522, 0x6f);
+
+			/* store WiFi original channel */
+			wifi_original_channel = btcoexist->btc_get_rf_reg(
+					btcoexist, BTC_RF_A, 0x18, 0x3ff);
+
+			/* Set RF channel */
+			if (cent_freq == 2484)
+				btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A,
+							  0x18, 0x3ff, 0xe);
+			else
+				btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A,
+					  0x18, 0x3ff, (cent_freq - 2412) / 5 +
+						  1); /* WiFi TRx Mask on */
+
+			/* save original RCK value */
+			u32tmp1 =  btcoexist->btc_get_rf_reg(
+					   btcoexist, BTC_RF_A, 0x1d, 0xfffff);
+
+			/* Enter debug mode */
+			btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0xde,
+						  0x2, 0x1);
+
+			/* Set RF Rx filter corner */
+			btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1d,
+						  0xfffff, 0x2e);
+
+
+			/* Set  RF mode = Rx, RF Gain = 0x320a0 */
+			btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x0,
+						  0xfffff, 0x320a0);
+
+			while (1) {
+				if (k++ > BT_8723D_2ANT_ANTDET_SWEEPPOINT_DELAY)
+					break;
+			}
+			flag = 3;
+			break;
+		case 3:
+			psd_scan->psd_gen_count = 0;
+			for (j = 1; j <= loopcnt; j++) {
+
+				btcoexist->btc_get(btcoexist,
+						   BTC_GET_BL_WIFI_SCAN, &scan);
+				btcoexist->btc_get(btcoexist,
+						   BTC_GET_BL_WIFI_ROAM, &roam);
+
+				if (scan || roam) {
+					is_sweep_ok = false;
+					break;
+				}
+				memset(psd_scan->psd_report, 0,
+				       psd_scan->psd_point * sizeof(u32));
+				start_p = psd_scan->psd_start_point +
+					  psd_scan->psd_start_base;
+				stop_p = psd_scan->psd_stop_point +
+					 psd_scan->psd_start_base + 1;
+
+				i = start_p;
+				point_index = 0;
+
+				while (i < stop_p) {
+					if (i >= points1)
+						psd_report =
+							halbtc8723d2ant_psd_getdata(
+							btcoexist, i - points1);
+					else
+						psd_report =
+							halbtc8723d2ant_psd_getdata(
+								btcoexist, i);
+
+					if (psd_report == 0)
+						tmp = 0;
+					else
+						/* tmp =  20*log10((double)psd_report); */
+						/* 20*log2(x)/log2(10), log2Base return theresult of the psd_report*100 */
+						tmp = 6 * halbtc8723d2ant_psd_log2base(
+							btcoexist, psd_report);
+
+					n = i - psd_scan->psd_start_base;
+					psd_scan->psd_report[n] =  tmp;
+
+					BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+						"Point=%d, psd_dB_data = %d\n",
+						    i, psd_scan->psd_report[n]);
+					BTC_TRACE(trace_buf);
+
+					i++;
+
+				}
+
+				halbtc8723d2ant_psd_maxholddata(btcoexist, j);
+
+				psd_scan->psd_gen_count = j;
+
+				/*Accumulate Max PSD value in this loop if the value > threshold */
+				if (psd_scan->psd_loop_max_value[j - 1] >=
+				    4000) {
+					psd_sum = psd_sum +
+						psd_scan->psd_loop_max_value[j -
+								       1];
+					avg_cnt++;
+				}
+
+				BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+					    "Loop=%d, Max_dB_data = %d\n",
+					    j, psd_scan->psd_loop_max_value[j
+							    - 1]);
+				BTC_TRACE(trace_buf);
+
+			}
+
+			if (loopcnt == BT_8723D_2ANT_ANTDET_PSD_SWWEEPCOUNT) {
+
+				/* search the Max Value between each-freq-point-max-hold value of all sweep*/
+				for (i = 1;
+				     i <= BT_8723D_2ANT_ANTDET_PSD_SWWEEPCOUNT;
+				     i++) {
+
+					if (i == 1) {
+						i_max = i;
+						val_max = psd_scan->psd_loop_max_value[i
+								       - 1];
+						val_max2 =
+							psd_scan->psd_loop_max_value[i
+								     - 1];
+					} else if (
+						psd_scan->psd_loop_max_value[i -
+							     1] > val_max) {
+						val_max2 = val_max;
+						i_max = i;
+						val_max = psd_scan->psd_loop_max_value[i
+								       - 1];
+					} else if (
+						psd_scan->psd_loop_max_value[i -
+							     1] > val_max2)
+						val_max2 =
+							psd_scan->psd_loop_max_value[i
+								     - 1];
+
+					BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+						"i = %d, val_hold= %d, val_max = %d, val_max2 = %d\n",
+						i, psd_scan->psd_loop_max_value[i
+								    - 1],
+						    val_max, val_max2);
+
+					BTC_TRACE(trace_buf);
+				}
+
+				psd_scan->psd_max_value_point = i_max;
+				psd_scan->psd_max_value = val_max;
+				psd_scan->psd_max_value2 = val_max2;
+
+				BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+					    "val_max = %d, val_max2 = %d\n",
+					    psd_scan->psd_max_value,
+					    psd_scan->psd_max_value2);
+				BTC_TRACE(trace_buf);
+			}
+
+			if (avg_cnt != 0) {
+				psd_scan->psd_avg_value = (psd_sum / avg_cnt);
+				if ((psd_sum % avg_cnt) >= (avg_cnt / 2))
+					psd_scan->psd_avg_value++;
+			} else
+				psd_scan->psd_avg_value = 0;
+
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				    "AvgLoop=%d, Avg_dB_data = %d\n",
+				    avg_cnt, psd_scan->psd_avg_value);
+			BTC_TRACE(trace_buf);
+
+			flag = 100;
+			break;
+		case 99:	/* error */
+
+			outloop = true;
+			break;
+		case 100: /* recovery */
+
+			/* set 3-wire on */
+			val = btcoexist->btc_read_4byte(btcoexist, 0x88c);
+			val &= 0xffcfffff;
+			btcoexist->btc_write_4byte(btcoexist, 0x88c, val);
+
+			/* CCK on */
+			val = btcoexist->btc_read_4byte(btcoexist, 0x800);
+			val |= 0x01000000;
+			btcoexist->btc_write_4byte(btcoexist, 0x800, val);
+
+			/* Tx-pause off */
+			btcoexist->btc_write_1byte(btcoexist, 0x522, 0x0);
+
+			/* PSD off */
+			val = btcoexist->btc_read_4byte(btcoexist, 0x808);
+			val &= 0xffbfffff;
+			btcoexist->btc_write_4byte(btcoexist, 0x808, val);
+
+			/* restore RF Rx filter corner */
+			btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1d,
+						  0xfffff, u32tmp1);
+
+			/* Exit debug mode */
+			btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0xde,
+						  0x2, 0x0);
+
+			/* restore WiFi original channel */
+			btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x18,
+						  0x3ff, wifi_original_channel);
+
+			outloop = true;
+			break;
+
+		}
+
+	} while (!outloop);
+
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+		    "xxxxxxxxxxxxxxxx PSD Sweep Stop!!\n");
+	BTC_TRACE(trace_buf);
+	return is_sweep_ok;
+
+}
+
+#ifdef PLATFORM_WINDOWS
+#pragma optimize("", off)
+#endif
+boolean halbtc8723d2ant_psd_antenna_detection(IN struct btc_coexist
+		*btcoexist)
+{
+	u32	i = 0;
+	u32	wlpsd_cent_freq = 2484, wlpsd_span = 2;
+	s32	wlpsd_offset = -4;
+	u32 bt_tx_time, bt_le_channel;
+	u8	bt_le_ch[13] = {3, 6, 8, 11, 13, 16, 18, 21, 23, 26, 28, 31, 33};
+
+	u8	h2c_parameter[3] = {0}, u8tmpa, u8tmpb;
+
+	u8	state = 0;
+	boolean		outloop = false, bt_resp = false, ant_det_finish = false;
+	u32		freq, freq1, freq2, psd_rep1, psd_rep2, delta_freq_per_point,
+			u32tmp, u32tmp0, u32tmp1, u32tmp2 ;
+	struct  btc_board_info	*board_info = &btcoexist->board_info;
+
+	memset(psd_scan->ant_det_peak_val, 0, 16 * sizeof(u8));
+	memset(psd_scan->ant_det_peak_freq, 0, 16 * sizeof(u8));
+
+	psd_scan->ant_det_bt_tx_time =
+		BT_8723D_2ANT_ANTDET_BTTXTIME;	   /* 0.42ms*50 = 20ms (0.42ms = 1 PSD sweep) */
+	psd_scan->ant_det_bt_le_channel = BT_8723D_2ANT_ANTDET_BTTXCHANNEL;
+
+	bt_tx_time = psd_scan->ant_det_bt_tx_time;
+	bt_le_channel = psd_scan->ant_det_bt_le_channel;
+
+	if (board_info->tfbga_package) /* for TFBGA */
+		psd_scan->ant_det_thres_offset = 5;
+	else
+		psd_scan->ant_det_thres_offset = 0;
+
+	do {
+		switch (state) {
+		case 0:
+			if (bt_le_channel == 39)
+				wlpsd_cent_freq = 2484;
+			else {
+				for (i = 1; i <= 13; i++) {
+					if (bt_le_ch[i - 1] ==
+					    bt_le_channel) {
+						wlpsd_cent_freq = 2412
+								  + (i - 1) * 5;
+						break;
+					}
+				}
+
+				if (i == 14) {
+
+					BTC_SPRINTF(trace_buf,
+						    BT_TMP_BUF_SIZE,
+						"xxxxxxxxxxxxxxxx AntennaDetect(), Abort!!, Invalid LE channel = %d\n ",
+						    bt_le_channel);
+					BTC_TRACE(trace_buf);
+					outloop = true;
+					break;
+				}
+			}
+#if 0
+			wlpsd_sweep_count = bt_tx_time * 238 /
+					    100; /* bt_tx_time/0.42								 */
+			wlpsd_sweep_count = wlpsd_sweep_count / 5;
+
+			if (wlpsd_sweep_count % 5 != 0)
+				wlpsd_sweep_count = (wlpsd_sweep_count /
+						     5 + 1) * 5;
+#endif
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				"xxxxxxxxxxxxxxxx AntennaDetect(), BT_LETxTime=%d,  BT_LECh = %d\n",
+				    bt_tx_time, bt_le_channel);
+			BTC_TRACE(trace_buf);
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				"xxxxxxxxxxxxxxxx AntennaDetect(), wlpsd_cent_freq=%d,  wlpsd_offset = %d, wlpsd_span = %d, wlpsd_sweep_count = %d\n",
+				    wlpsd_cent_freq,
+				    wlpsd_offset,
+				    wlpsd_span,
+				    BT_8723D_2ANT_ANTDET_PSD_SWWEEPCOUNT);
+			BTC_TRACE(trace_buf);
+
+			state = 1;
+			break;
+		case 1: /* stop coex DM & set antenna path */
+			/* Stop Coex DM */
+			btcoexist->stop_coex_dm = true;
+
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				"xxxxxxxxxxxxxxxx AntennaDetect(), Stop Coex DM!!\n");
+			BTC_TRACE(trace_buf);
+
+			/* Set TDMA off,				 */
+			halbtc8723d2ant_ps_tdma(btcoexist, FORCE_EXEC,
+						false, 0);
+
+			/* Set coex table */
+			halbtc8723d2ant_coex_table_with_type(btcoexist,
+							     FORCE_EXEC, 0);
+
+			if (board_info->btdm_ant_pos ==
+			    BTC_ANTENNA_AT_MAIN_PORT) {
+				BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+					"xxxxxxxxxxxxxxxx AntennaDetect(), Antenna at Main Port\n");
+				BTC_TRACE(trace_buf);
+			} else {
+				BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+					"xxxxxxxxxxxxxxxx AntennaDetect(), Antenna at Aux Port\n");
+				BTC_TRACE(trace_buf);
+			}
+
+			/* Set Antenna path, switch WiFi to un-certain antenna port */
+			/* Set Antenna Path,  both GNT_WL/GNT_BT = 1, and control by SW */
+			halbtc8723d2ant_set_ant_path(btcoexist, BTC_ANT_PATH_BT,
+						     FORCE_EXEC,
+					     BT_8723D_2ANT_PHASE_ANTENNA_DET);
+
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				"xxxxxxxxxxxxxxxx AntennaDetect(), Set Antenna to BT!!\n");
+			BTC_TRACE(trace_buf);
+
+			/* Set AFH mask on at WiFi channel 2472MHz +/- 10MHz */
+			h2c_parameter[0] = 0x1;
+			h2c_parameter[1] = 0xd;
+			h2c_parameter[2] = 0x14;
+
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				"xxxxxxxxxxxxxxxx AntennaDetect(), Set AFH on, Cent-Ch= %d,  Mask=%d\n",
+				    h2c_parameter[1],
+				    h2c_parameter[2]);
+			BTC_TRACE(trace_buf);
+
+			btcoexist->btc_fill_h2c(btcoexist, 0x66, 3,
+						h2c_parameter);
+
+			u32tmp = btcoexist->btc_read_2byte(btcoexist, 0x948);
+			u32tmp0 = btcoexist->btc_read_4byte(btcoexist, 0x70);
+			u32tmp1 = halbtc8723d2ant_ltecoex_indirect_read_reg(
+					  btcoexist, 0x38);
+			u32tmp2 = halbtc8723d2ant_ltecoex_indirect_read_reg(
+					  btcoexist, 0x54);
+
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				"[BTCoex], ********** 0x948 = 0x%x, 0x70 = 0x%x, 0x38= 0x%x, 0x54= 0x%x (Before Ant Det)\n",
+				    u32tmp, u32tmp0, u32tmp1, u32tmp2);
+			BTC_TRACE(trace_buf);
+
+			state = 2;
+			break;
+		case 2:	/* Pre-sweep background psd */
+			if (!halbtc8723d2ant_psd_sweep_point(btcoexist,
+				     wlpsd_cent_freq, wlpsd_offset, wlpsd_span,
+					     BT_8723D_2ANT_ANTDET_PSD_POINTS,
+				     BT_8723D_2ANT_ANTDET_PSD_AVGNUM, 3)) {
+				ant_det_finish = false;
+				board_info->btdm_ant_num_by_ant_det = 1;
+				psd_scan->ant_det_result = 8;
+				state = 99;
+				break;
+			}
+
+			psd_scan->ant_det_pre_psdscan_peak_val =
+				psd_scan->psd_max_value;
+
+			if (psd_scan->ant_det_pre_psdscan_peak_val >
+			    (BT_8723D_2ANT_ANTDET_PSDTHRES_BACKGROUND
+			     + psd_scan->ant_det_thres_offset) * 100) {
+				BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+					"xxxxxxxxxxxxxxxx AntennaDetect(), Abort Antenna Detection!! becaus background = %d > thres (%d)\n",
+					psd_scan->ant_det_pre_psdscan_peak_val /
+					    100,
+					BT_8723D_2ANT_ANTDET_PSDTHRES_BACKGROUND
+					    + psd_scan->ant_det_thres_offset);
+				BTC_TRACE(trace_buf);
+				ant_det_finish = false;
+				board_info->btdm_ant_num_by_ant_det = 1;
+				psd_scan->ant_det_result = 5;
+				state = 99;
+			} else {
+				BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+					"xxxxxxxxxxxxxxxx AntennaDetect(), Start Antenna Detection!! becaus background = %d <= thres (%d)\n",
+					psd_scan->ant_det_pre_psdscan_peak_val /
+					    100,
+					BT_8723D_2ANT_ANTDET_PSDTHRES_BACKGROUND
+					    + psd_scan->ant_det_thres_offset);
+				BTC_TRACE(trace_buf);
+				state = 3;
+			}
+			break;
+		case 3:
+			bt_resp = btcoexist->btc_set_bt_ant_detection(
+					  btcoexist, (u8)(bt_tx_time & 0xff),
+					  (u8)(bt_le_channel & 0xff));
+
+			/* Sync WL Rx PSD with BT Tx time because H2C->Mailbox delay */
+			delay_ms(20);
+
+			if (!halbtc8723d2ant_psd_sweep_point(btcoexist,
+					     wlpsd_cent_freq, wlpsd_offset,
+							     wlpsd_span,
+					     BT_8723D_2ANT_ANTDET_PSD_POINTS,
+					     BT_8723D_2ANT_ANTDET_PSD_AVGNUM,
+				     BT_8723D_2ANT_ANTDET_PSD_SWWEEPCOUNT)) {
+				ant_det_finish = false;
+				board_info->btdm_ant_num_by_ant_det = 1;
+				psd_scan->ant_det_result = 8;
+				state = 99;
+				break;
+			}
+
+#if 1
+			psd_scan->ant_det_psd_scan_peak_val =
+				psd_scan->psd_max_value;
+#endif
+#if 0
+			psd_scan->ant_det_psd_scan_peak_val =
+				((psd_scan->psd_max_value - psd_scan->psd_avg_value) <
+				 800) ?
+				psd_scan->psd_max_value : ((
+						psd_scan->psd_max_value -
+					psd_scan->psd_max_value2 <= 300) ?
+						   psd_scan->psd_avg_value :
+						   psd_scan->psd_max_value2);
+#endif
+			psd_scan->ant_det_psd_scan_peak_freq =
+				psd_scan->psd_max_value_point;
+			state = 4;
+			break;
+		case 4:
+
+			if (psd_scan->psd_point == 0)
+				delta_freq_per_point = 0;
+			else
+				delta_freq_per_point =
+					psd_scan->psd_band_width /
+					psd_scan->psd_point;
+
+			psd_rep1 = psd_scan->ant_det_psd_scan_peak_val / 100;
+			psd_rep2 = psd_scan->ant_det_psd_scan_peak_val -
+				   psd_rep1 *
+				   100;
+
+			freq = ((psd_scan->real_cent_freq - 20) *
+				1000000 + psd_scan->psd_max_value_point
+				* delta_freq_per_point);
+			freq1 = freq / 1000000;
+			freq2 = freq / 1000 - freq1 * 1000;
+
+			if (freq2 < 100) {
+				BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+					"xxxxxxxxxxxxxxxx AntennaDetect(), Max Value: Freq = %d.0%d MHz",
+					    freq1, freq2);
+				BTC_TRACE(trace_buf);
+				CL_SPRINTF(psd_scan->ant_det_peak_freq,
+					   BT_8723D_2ANT_ANTDET_BUF_LEN,
+					   "%d.0%d", freq1, freq2);
+			} else {
+				BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+					"xxxxxxxxxxxxxxxx AntennaDetect(), Max Value: Freq = %d.%d MHz",
+					    freq1, freq2);
+				BTC_TRACE(trace_buf);
+				CL_SPRINTF(psd_scan->ant_det_peak_freq,
+					   BT_8723D_2ANT_ANTDET_BUF_LEN,
+					   "%d.%d", freq1, freq2);
+			}
+
+			if (psd_rep2 < 10) {
+				BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+					    ", Value = %d.0%d dB\n",
+					    psd_rep1, psd_rep2);
+				BTC_TRACE(trace_buf);
+				CL_SPRINTF(psd_scan->ant_det_peak_val,
+					   BT_8723D_2ANT_ANTDET_BUF_LEN,
+					   "%d.0%d", psd_rep1, psd_rep2);
+			} else {
+				BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+					    ", Value = %d.%d dB\n",
+					    psd_rep1, psd_rep2);
+				BTC_TRACE(trace_buf);
+				CL_SPRINTF(psd_scan->ant_det_peak_val,
+					   BT_8723D_2ANT_ANTDET_BUF_LEN,
+					   "%d.%d", psd_rep1, psd_rep2);
+			}
+
+			psd_scan->ant_det_is_btreply_available = true;
+
+			if (bt_resp == false) {
+				psd_scan->ant_det_is_btreply_available =
+					false;
+				psd_scan->ant_det_result = 0;
+				ant_det_finish = false;
+				board_info->btdm_ant_num_by_ant_det = 1;
+				BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+					"xxxxxxxxxxxxxxxx AntennaDetect(), BT Response = Fail\n ");
+				BTC_TRACE(trace_buf);
+			} else if (psd_scan->ant_det_psd_scan_peak_val >
+				(BT_8723D_2ANT_ANTDET_PSDTHRES_2ANT_BADISOLATION)
+				   * 100) {
+				psd_scan->ant_det_result = 1;
+				ant_det_finish = true;
+				board_info->btdm_ant_num_by_ant_det = 2;
+				coex_sta->isolation_btween_wb = (u8)(85 -
+					psd_scan->ant_det_psd_scan_peak_val /
+							     100) & 0xff;
+				BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+					"xxxxxxxxxxxxxxxx AntennaDetect(), Detect Result = 2-Ant, Bad-Isolation!!\n");
+				BTC_TRACE(trace_buf);
+			} else if (psd_scan->ant_det_psd_scan_peak_val >
+				(BT_8723D_2ANT_ANTDET_PSDTHRES_2ANT_GOODISOLATION
+				    + psd_scan->ant_det_thres_offset) * 100) {
+				psd_scan->ant_det_result = 2;
+				ant_det_finish = true;
+				board_info->btdm_ant_num_by_ant_det = 2;
+				coex_sta->isolation_btween_wb = (u8)(85 -
+					psd_scan->ant_det_psd_scan_peak_val /
+							     100) & 0xff;
+				BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+					"xxxxxxxxxxxxxxxx AntennaDetect(), Detect Result = 2-Ant, Good-Isolation!!\n");
+				BTC_TRACE(trace_buf);
+			} else if (psd_scan->ant_det_psd_scan_peak_val >
+				   (BT_8723D_2ANT_ANTDET_PSDTHRES_1ANT) *
+				   100) {
+				psd_scan->ant_det_result = 3;
+				ant_det_finish = true;
+				board_info->btdm_ant_num_by_ant_det = 1;
+				coex_sta->isolation_btween_wb = (u8)(85 -
+					psd_scan->ant_det_psd_scan_peak_val /
+							     100) & 0xff;
+				BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+					"xxxxxxxxxxxxxxxx AntennaDetect(), Detect Result = 1-Ant!!\n");
+				BTC_TRACE(trace_buf);
+			} else {
+				psd_scan->ant_det_result = 4;
+				ant_det_finish = false;
+				board_info->btdm_ant_num_by_ant_det = 1;
+				BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+					"xxxxxxxxxxxxxxxx AntennaDetect(), Detect Result = 1-Ant, un-certainity!!\n");
+				BTC_TRACE(trace_buf);
+			}
+
+			state = 99;
+			break;
+		case 99:  /* restore setup */
+
+			/* Set AFH mask off at WiFi channel 2472MHz +/- 10MHz */
+			h2c_parameter[0] = 0x0;
+			h2c_parameter[1] = 0x0;
+			h2c_parameter[2] = 0x0;
+
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				"xxxxxxxxxxxxxxxx AntennaDetect(), Set AFH on, Cent-Ch= %d,  Mask=%d\n",
+				    h2c_parameter[1], h2c_parameter[2]);
+			BTC_TRACE(trace_buf);
+
+			btcoexist->btc_fill_h2c(btcoexist, 0x66, 3,
+						h2c_parameter);
+
+			/* Set Antenna Path, GNT_WL/GNT_BT control by PTA */
+			/* Set Antenna path, switch WiFi to certain antenna port */
+			halbtc8723d2ant_set_ant_path(btcoexist,
+					     BTC_ANT_PATH_AUTO, FORCE_EXEC,
+					     BT_8723D_2ANT_PHASE_2G_RUNTIME);
+
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				"xxxxxxxxxxxxxxxx AntennaDetect(), Set Antenna to PTA\n!!");
+			BTC_TRACE(trace_buf);
+
+			btcoexist->stop_coex_dm = false;
+
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				"xxxxxxxxxxxxxxxx AntennaDetect(), Resume Coex DM\n!!");
+			BTC_TRACE(trace_buf);
+
+			outloop = true;
+			break;
+		}
+
+	} while (!outloop);
+
+	return ant_det_finish;
+
+}
+
+#ifdef PLATFORM_WINDOWS
+#pragma optimize("", off)
+#endif
+boolean halbtc8723d2ant_psd_antenna_detection_check(IN struct btc_coexist
+		*btcoexist)
+{
+	static u32 ant_det_count = 0, ant_det_fail_count = 0;
+	struct  btc_board_info	*board_info = &btcoexist->board_info;
+
+	boolean scan, roam, ant_det_finish = false;
+
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_SCAN, &scan);
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_ROAM, &roam);
+
+	ant_det_count++;
+
+	psd_scan->ant_det_try_count = ant_det_count;
+
+	if (scan || roam) {
+		ant_det_finish = false;
+		psd_scan->ant_det_result = 6;
+	} else if (coex_sta->bt_disabled) {
+		ant_det_finish = false;
+		psd_scan->ant_det_result = 11;
+	} else if (coex_sta->num_of_profile >= 1) {
+		ant_det_finish = false;
+		psd_scan->ant_det_result = 7;
+	} else if (
+		!psd_scan->ant_det_is_ant_det_available) { /* Antenna initial setup is not ready */
+		ant_det_finish = false;
+		psd_scan->ant_det_result = 9;
+	} else if (coex_sta->c2h_bt_inquiry_page) {
+		ant_det_finish = false;
+		psd_scan->ant_det_result = 10;
+	} else {
+
+		ant_det_finish = halbtc8723d2ant_psd_antenna_detection(
+					 btcoexist);
+
+		delay_ms(psd_scan->ant_det_bt_tx_time);
+	}
+
+
+	if (!ant_det_finish)
+		ant_det_fail_count++;
+
+	psd_scan->ant_det_fail_count = ant_det_fail_count;
+
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+		"xxxxxxxxxxxxxxxx AntennaDetect(), result = %d, fail_count = %d, finish = %s\n",
+		    psd_scan->ant_det_result,
+		    psd_scan->ant_det_fail_count,
+		    ant_det_finish == true ? "Yes" : "No");
+	BTC_TRACE(trace_buf);
+
+	return ant_det_finish;
+
+}
+
+
+/* ************************************************************
+ * work around function start with wa_halbtc8723d2ant_
+ * ************************************************************
+ * ************************************************************
+ * extern function start with ex_halbtc8723d2ant_
+ * ************************************************************ */
+void ex_halbtc8723d2ant_power_on_setting(IN struct btc_coexist *btcoexist)
+{
+	struct  btc_board_info	*board_info = &btcoexist->board_info;
+	u8 u8tmp = 0x0;
+	u16 u16tmp = 0x0;
+	u32	value = 0;
+
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+		"xxxxxxxxxxxxxxxx Execute 8723d 2-Ant PowerOn Setting xxxxxxxxxxxxxxxx!!\n");
+	BTC_TRACE(trace_buf);
+
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+		    "Ant Det Finish = %s, Ant Det Number  = %d\n",
+		    (board_info->btdm_ant_det_finish ? "Yes" : "No"),
+		    board_info->btdm_ant_num_by_ant_det);
+	BTC_TRACE(trace_buf);
+
+
+	btcoexist->stop_coex_dm = true;
+	psd_scan->ant_det_is_ant_det_available = false;
+
+	/* enable BB, REG_SYS_FUNC_EN such that we can write BB Register correctly. */
+	u16tmp = btcoexist->btc_read_2byte(btcoexist, 0x2);
+	btcoexist->btc_write_2byte(btcoexist, 0x2, u16tmp | BIT(0) | BIT(1));
+
+
+	/* Local setting bit define */
+	/*	BIT0: "0" for no antenna inverse; "1" for antenna inverse  */
+	/*	BIT1: "0" for internal switch; "1" for external switch */
+	/*	BIT2: "0" for one antenna; "1" for two antenna */
+	/* NOTE: here default all internal switch and 1-antenna ==> BIT1=0 and BIT2=0 */
+
+	/* Set path control to WL */
+	btcoexist->btc_write_1byte_bitmask(btcoexist, 0x67, 0x80, 0x1);
+	btcoexist->btc_write_2byte(btcoexist, 0x948, 0x0);
+
+	/* Check efuse 0xc3[6] for Single Antenna Path */
+	if (board_info->single_ant_path == 0) {
+		/* set to S1 */
+		board_info->btdm_ant_pos = BTC_ANTENNA_AT_MAIN_PORT;
+		u8tmp = 4;
+		value = 1;
+	} else if (board_info->single_ant_path == 1) {
+		/* set to S0 */
+		board_info->btdm_ant_pos = BTC_ANTENNA_AT_AUX_PORT;
+		u8tmp = 5;
+		value = 0;
+	}
+
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+		"[BTCoex], ********** (Power On) single_ant_path  = %d, btdm_ant_pos = %d **********\n",
+		    board_info->single_ant_path , board_info->btdm_ant_pos);
+	BTC_TRACE(trace_buf);
+
+	/* Set Antenna Path to BT side */
+	halbtc8723d2ant_set_ant_path(btcoexist,
+				     BTC_ANT_PATH_AUTO,
+				     FORCE_EXEC,
+				     BT_8723D_1ANT_PHASE_COEX_POWERON);
+
+	/* Write Single Antenna Position to Registry to tell BT for 872db. This line can be removed
+	since BT EFuse also add "single antenna position" in EFuse for 8723d*/
+	btcoexist->btc_set(btcoexist, BTC_SET_ACT_ANTPOSREGRISTRY_CTRL,
+			   &value);
+
+	/* Save"single antenna position" info in Local register setting for FW reading, because FW may not ready at  power on */
+	if (btcoexist->chip_interface == BTC_INTF_PCI)
+		btcoexist->btc_write_local_reg_1byte(btcoexist, 0x3e0, u8tmp);
+	else if (btcoexist->chip_interface == BTC_INTF_USB)
+		btcoexist->btc_write_local_reg_1byte(btcoexist, 0xfe08, u8tmp);
+	else if (btcoexist->chip_interface == BTC_INTF_SDIO)
+		btcoexist->btc_write_local_reg_1byte(btcoexist, 0x60, u8tmp);
+
+	/* enable GNT_WL/GNT_BT debug signal to GPIO14/15 */
+	halbtc8723d2ant_enable_gnt_to_gpio(btcoexist, true);
+
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+		"[BTCoex], **********  LTE coex Reg 0x38 (Power-On) = 0x%x**********\n",
+		    halbtc8723d2ant_ltecoex_indirect_read_reg(btcoexist, 0x38));
+	BTC_TRACE(trace_buf);
+
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+		"[BTCoex], **********  MAC Reg 0x70/ BB Reg 0x948 (Power-On) = 0x%x / 0x%x**********\n",
+		    btcoexist->btc_read_4byte(btcoexist, 0x70),
+		    btcoexist->btc_read_2byte(btcoexist, 0x948));
+	BTC_TRACE(trace_buf);
+}
+
+void ex_halbtc8723d2ant_pre_load_firmware(IN struct btc_coexist *btcoexist)
+{
+	struct  btc_board_info	*board_info = &btcoexist->board_info;
+	u8 u8tmp = 0x4; /* Set BIT2 by default since it's 2ant case */
+
+	/* */
+	/* S0 or S1 setting and Local register setting(By the setting fw can get ant number, S0/S1, ... info) */
+	/* Local setting bit define */
+	/*	BIT0: "0" for no antenna inverse; "1" for antenna inverse  */
+	/*	BIT1: "0" for internal switch; "1" for external switch */
+	/*	BIT2: "0" for one antenna; "1" for two antenna */
+	/* NOTE: here default all internal switch and 1-antenna ==> BIT1=0 and BIT2=0 */
+	if (btcoexist->chip_interface == BTC_INTF_USB) {
+		/* fixed at S0 for USB interface */
+		u8tmp |= 0x1;	/* antenna inverse */
+		btcoexist->btc_write_local_reg_1byte(btcoexist, 0xfe08, u8tmp);
+	} else {
+		/* for PCIE and SDIO interface, we check efuse 0xc3[6] */
+		if (board_info->single_ant_path == 0) {
+		} else if (board_info->single_ant_path == 1) {
+			/* set to S0 */
+			u8tmp |= 0x1;	/* antenna inverse */
+		}
+
+		if (btcoexist->chip_interface == BTC_INTF_PCI)
+			btcoexist->btc_write_local_reg_1byte(btcoexist, 0x3e0,
+							     u8tmp);
+		else if (btcoexist->chip_interface == BTC_INTF_SDIO)
+			btcoexist->btc_write_local_reg_1byte(btcoexist, 0x60,
+							     u8tmp);
+	}
+}
+
+
+void ex_halbtc8723d2ant_init_hw_config(IN struct btc_coexist *btcoexist,
+				       IN boolean wifi_only)
+{
+	halbtc8723d2ant_init_hw_config(btcoexist, wifi_only);
+}
+
+void ex_halbtc8723d2ant_init_coex_dm(IN struct btc_coexist *btcoexist)
+{
+
+	halbtc8723d2ant_init_coex_dm(btcoexist);
+}
+
+void ex_halbtc8723d2ant_display_coex_info(IN struct btc_coexist *btcoexist)
+{
+	struct  btc_board_info		*board_info = &btcoexist->board_info;
+	struct  btc_bt_link_info	*bt_link_info = &btcoexist->bt_link_info;
+	u8				*cli_buf = btcoexist->cli_buf;
+	u8				u8tmp[4], i, ps_tdma_case = 0;
+	u32				u32tmp[4];
+	u16				u16tmp[4];
+	u32				fa_ofdm, fa_cck, cca_ofdm, cca_cck, bt_coex_ver = 0;
+	u32				fw_ver = 0, bt_patch_ver = 0;
+	static u8			pop_report_in_10s = 0, cnt = 0;
+	u32			phyver = 0;
+	boolean			lte_coex_on = false;
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+		   "\r\n ============[BT Coexist info]============");
+	CL_PRINTF(cli_buf);
+
+	if (btcoexist->manual_control) {
+		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+			"\r\n ============[Under Manual Control]============");
+		CL_PRINTF(cli_buf);
+		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+			   "\r\n ==========================================");
+		CL_PRINTF(cli_buf);
+	}
+
+	if (!coex_sta->bt_disabled) {
+
+		if (coex_sta->bt_coex_supported_feature == 0)
+			btcoexist->btc_get(btcoexist, BTC_GET_U4_SUPPORTED_FEATURE,
+						&coex_sta->bt_coex_supported_feature);
+
+		if ((coex_sta->bt_coex_supported_version == 0) ||
+			 (coex_sta->bt_coex_supported_version == 0xffff))
+			btcoexist->btc_get(btcoexist, BTC_GET_U4_SUPPORTED_VERSION,
+						&coex_sta->bt_coex_supported_version);
+
+		if (coex_sta->bt_reg_vendor_ac == 0xffff)
+			coex_sta->bt_reg_vendor_ac = (u16)(
+						btcoexist->btc_get_bt_reg(btcoexist, 3,
+						0xac) & 0xffff);
+
+		if (coex_sta->bt_reg_vendor_ae == 0xffff)
+			coex_sta->bt_reg_vendor_ae = (u16)(
+						btcoexist->btc_get_bt_reg(btcoexist, 3,
+						0xae) & 0xffff);
+
+		btcoexist->btc_get(btcoexist, BTC_GET_U4_BT_PATCH_VER,
+						&bt_patch_ver);
+		btcoexist->bt_info.bt_get_fw_ver = bt_patch_ver;
+
+		if (coex_sta->num_of_profile > 0) {
+			cnt++;
+
+			if (cnt >= 3) {
+				btcoexist->btc_get_bt_afh_map_from_bt(btcoexist, 0,
+					&coex_sta->bt_afh_map[0]);
+				cnt = 0;
+			}
+		}
+	}
+
+	if (psd_scan->ant_det_try_count == 0) {
+		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %s",
+			   "Ant PG Num/ Mech/ Pos",
+			   board_info->pg_ant_num, board_info->btdm_ant_num,
+			   (board_info->btdm_ant_pos == 1 ? "S1" : "S0"));
+		CL_PRINTF(cli_buf);
+	} else {
+		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+			"\r\n %-35s = %d/ %d/ %s  (retry=%d/fail=%d/result=%d)",
+			   "Ant PG Num/ Mech(Ant_Det)/ Pos",
+			   board_info->pg_ant_num,
+			   board_info->btdm_ant_num_by_ant_det,
+			   (board_info->btdm_ant_pos == 1 ? "S1" : "S0"),
+			   psd_scan->ant_det_try_count,
+			   psd_scan->ant_det_fail_count,
+			   psd_scan->ant_det_result);
+		CL_PRINTF(cli_buf);
+
+		if (board_info->btdm_ant_det_finish) {
+
+			if (psd_scan->ant_det_result != 12)
+				CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+					   "\r\n %-35s = %s",
+					   "Ant Det PSD Value",
+					   psd_scan->ant_det_peak_val);
+			else
+				CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+					   "\r\n %-35s = %d",
+					   "Ant Det PSD Value",
+					   psd_scan->ant_det_psd_scan_peak_val
+					   / 100);
+			CL_PRINTF(cli_buf);
+		}
+	}
+
+	if (board_info->ant_det_result_five_complete) {
+		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+			   "\r\n %-35s = %d/ %d",
+			   "AntDet(Registry) Num/PSD Value",
+			   board_info->btdm_ant_num_by_ant_det,
+			   (board_info->antdetval & 0x7f));
+		CL_PRINTF(cli_buf);
+	}
+
+
+	bt_patch_ver = btcoexist->bt_info.bt_get_fw_ver;
+	btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_FW_VER, &fw_ver);
+	phyver = btcoexist->btc_get_bt_phydm_version(btcoexist);
+
+	bt_coex_ver = coex_sta->bt_coex_supported_version & 0xff;
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+				"\r\n %-35s = %d_%02x/ 0x%02x/ 0x%02x (%s)",
+				"CoexVer WL/  BT_Desired/ BT_Report",
+				glcoex_ver_date_8723d_2ant, glcoex_ver_8723d_2ant,
+				glcoex_ver_btdesired_8723d_2ant,
+				bt_coex_ver,
+				(bt_coex_ver == 0xff ? "Unknown" :
+				(coex_sta->bt_disabled ? "BT-disable" :
+				(bt_coex_ver >= glcoex_ver_btdesired_8723d_2ant ?
+				"Match" : "Mis-Match"))));
+	CL_PRINTF(cli_buf);
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+		   "\r\n %-35s = 0x%x/ 0x%x/ v%d/ %c",
+		   "W_FW/ B_FW/ Phy/ Kt",
+		   fw_ver, bt_patch_ver, phyver,
+		   coex_sta->cut_version + 65);
+	CL_PRINTF(cli_buf);
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %02x %02x %02x ",
+		   "Wifi channel informed to BT",
+		   coex_dm->wifi_chnl_info[0], coex_dm->wifi_chnl_info[1],
+		   coex_dm->wifi_chnl_info[2]);
+	CL_PRINTF(cli_buf);
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d / %d / %d ",
+		   "Isolation/WL_Thres/BT_Thres",
+		   coex_sta->isolation_btween_wb,
+		   coex_sta->wifi_coex_thres,
+		   coex_sta->bt_coex_thres);
+	CL_PRINTF(cli_buf);
+
+	/* wifi status */
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s",
+		   "============[Wifi Status]============");
+	CL_PRINTF(cli_buf);
+	btcoexist->btc_disp_dbg_msg(btcoexist, BTC_DBG_DISP_WIFI_STATUS);
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s",
+		   "============[BT Status]============");
+	CL_PRINTF(cli_buf);
+
+	pop_report_in_10s++;
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+		   "\r\n %-35s = [%s/ %d dBm/ %d/ %d] ",
+		   "BT [status/ rssi/ retryCnt/ popCnt]",
+		   ((coex_sta->bt_disabled) ? ("disabled") :	((
+			   coex_sta->c2h_bt_inquiry_page) ? ("inquiry/page")
+			   : ((BT_8723D_2ANT_BT_STATUS_NON_CONNECTED_IDLE ==
+			       coex_dm->bt_status) ? "non-connected idle" :
+		((BT_8723D_2ANT_BT_STATUS_CONNECTED_IDLE == coex_dm->bt_status)
+				       ? "connected-idle" : "busy")))),
+		   coex_sta->bt_rssi - 100, coex_sta->bt_retry_cnt,
+		   coex_sta->pop_event_cnt);
+	CL_PRINTF(cli_buf);
+
+	if (pop_report_in_10s >= 5) {
+		coex_sta->pop_event_cnt = 0;
+		pop_report_in_10s = 0;
+	}
+
+
+	if (coex_sta->num_of_profile != 0)
+		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+			   "\r\n %-35s = %s%s%s%s%s",
+			   "Profiles",
+			   ((bt_link_info->a2dp_exist) ? "A2DP," : ""),
+			   ((bt_link_info->sco_exist) ?  "SCO," : ""),
+			   ((bt_link_info->hid_exist) ?
+			    ((coex_sta->hid_busy_num >= 2) ? "HID(4/18)," :
+			     "HID(2/18),") : ""),
+			   ((bt_link_info->pan_exist) ?  "PAN," : ""),
+			   ((coex_sta->voice_over_HOGP) ? "Voice" : ""));
+	else
+		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+			   "\r\n %-35s = None",
+			   "Profiles");
+
+	CL_PRINTF(cli_buf);
+
+
+	if (bt_link_info->a2dp_exist) {
+		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s/ %d/ %s",
+			   "A2DP Rate/Bitpool/Auto_Slot",
+			   ((coex_sta->is_A2DP_3M) ? "3M" : "No_3M"),
+			   coex_sta->a2dp_bit_pool,
+			   ((coex_sta->is_autoslot) ? "On" : "Off")
+			  );
+		CL_PRINTF(cli_buf);
+	}
+
+	if (bt_link_info->hid_exist) {
+		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d",
+			   "HID PairNum/Forbid_Slot",
+			   coex_sta->hid_pair_cnt,
+			   coex_sta->forbidden_slot
+			  );
+		CL_PRINTF(cli_buf);
+	}
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s / %s/ 0x%x/ 0x%x",
+			"Role/IgnWlanAct/Feature/BLEScan",
+			((bt_link_info->slave_role) ? "Slave" : "Master"),
+			((coex_dm->cur_ignore_wlan_act) ? "Yes" : "No"),
+			coex_sta->bt_coex_supported_feature,
+			coex_sta->bt_ble_scan_type);
+	CL_PRINTF(cli_buf);
+
+	if ((coex_sta->bt_ble_scan_type & 0x7) != 0x0) {
+		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+			"\r\n %-35s = 0x%08x/ 0x%08x/ 0x%08x",
+			"BLEScan Intv-Win TV/Init/Ble",
+			(coex_sta->bt_ble_scan_type & 0x1 ?
+			coex_sta->bt_ble_scan_para[0] : 0x0),
+			(coex_sta->bt_ble_scan_type & 0x2 ?
+			coex_sta->bt_ble_scan_para[1] : 0x0),
+			(coex_sta->bt_ble_scan_type & 0x4 ?
+			coex_sta->bt_ble_scan_para[2] : 0x0));
+
+		CL_PRINTF(cli_buf);
+	}
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d/ %d/ %d",
+		   "ReInit/ReLink/IgnWlact/Page/NameReq",
+		   coex_sta->cnt_ReInit,
+		   coex_sta->cnt_setupLink,
+		   coex_sta->cnt_IgnWlanAct,
+		   coex_sta->cnt_Page,
+		   coex_sta->cnt_RemoteNameReq
+		  );
+	CL_PRINTF(cli_buf);
+
+	halbtc8723d2ant_read_score_board(btcoexist,	&u16tmp[0]);
+
+	if ((coex_sta->bt_reg_vendor_ae == 0xffff) ||
+	    (coex_sta->bt_reg_vendor_ac == 0xffff))
+		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = x/ x/ %04x",
+			   "0xae[4]/0xac[1:0]/Scoreboard", u16tmp[0]);
+	else
+		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+			   "\r\n %-35s = 0x%x/ 0x%x/ %04x",
+			   "0xae[4]/0xac[1:0]/Scoreboard",
+			   ((coex_sta->bt_reg_vendor_ae & BIT(4)) >> 4),
+			   coex_sta->bt_reg_vendor_ac & 0x3, u16tmp[0]);
+	CL_PRINTF(cli_buf);
+
+	if (coex_sta->num_of_profile > 0) {
+
+		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+			"\r\n %-35s = %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x",
+			"AFH MAP",
+			coex_sta->bt_afh_map[0],
+			coex_sta->bt_afh_map[1],
+			coex_sta->bt_afh_map[2],
+			coex_sta->bt_afh_map[3],
+			coex_sta->bt_afh_map[4],
+			coex_sta->bt_afh_map[5],
+			coex_sta->bt_afh_map[6],
+			coex_sta->bt_afh_map[7],
+			coex_sta->bt_afh_map[8],
+			coex_sta->bt_afh_map[9]
+			   );
+		CL_PRINTF(cli_buf);
+	}
+
+	for (i = 0; i < BT_INFO_SRC_8723D_2ANT_MAX; i++) {
+		if (coex_sta->bt_info_c2h_cnt[i]) {
+			CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+				"\r\n %-35s = %02x %02x %02x %02x %02x %02x %02x (%d)",
+				   glbt_info_src_8723d_2ant[i],
+				   coex_sta->bt_info_c2h[i][0],
+				   coex_sta->bt_info_c2h[i][1],
+				   coex_sta->bt_info_c2h[i][2],
+				   coex_sta->bt_info_c2h[i][3],
+				   coex_sta->bt_info_c2h[i][4],
+				   coex_sta->bt_info_c2h[i][5],
+				   coex_sta->bt_info_c2h[i][6],
+				   coex_sta->bt_info_c2h_cnt[i]);
+			CL_PRINTF(cli_buf);
+		}
+	}
+
+	/* Sw mechanism	 */
+	if (btcoexist->manual_control)
+		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s",
+			"============[mechanism] (before Manual)============");
+	else
+		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s",
+			   "============[Mechanism]============");
+
+	CL_PRINTF(cli_buf);
+
+
+	ps_tdma_case = coex_dm->cur_ps_tdma;
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+		   "\r\n %-35s = %02x %02x %02x %02x %02x (case-%d, %s, %s)",
+		   "TDMA",
+		   coex_dm->ps_tdma_para[0], coex_dm->ps_tdma_para[1],
+		   coex_dm->ps_tdma_para[2], coex_dm->ps_tdma_para[3],
+		   coex_dm->ps_tdma_para[4], ps_tdma_case,
+		   (coex_dm->cur_ps_tdma_on ? "TDMA On" : "TDMA Off"),
+		   (coex_dm->is_switch_to_1dot5_ant ? "1.5Ant" : "2Ant"));
+	CL_PRINTF(cli_buf);
+
+	u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x6c0);
+	u32tmp[1] = btcoexist->btc_read_4byte(btcoexist, 0x6c4);
+	u32tmp[2] = btcoexist->btc_read_4byte(btcoexist, 0x6c8);
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+		   "\r\n %-35s = %d/ 0x%x/ 0x%x/ 0x%x",
+		   "Table/0x6c0/0x6c4/0x6c8",
+		   coex_sta->coex_table_type, u32tmp[0], u32tmp[1], u32tmp[2]);
+	CL_PRINTF(cli_buf);
+
+	u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x778);
+	u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x6cc);
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+		   "\r\n %-35s = 0x%x/ 0x%x",
+		   "0x778/0x6cc",
+		   u8tmp[0], u32tmp[0]);
+	CL_PRINTF(cli_buf);
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s/ %s",
+		   "AntDiv/ ForceLPS",
+		   ((board_info->ant_div_cfg) ? "On" : "Off"),
+		   ((coex_sta->force_lps_on) ? "On" : "Off"));
+	CL_PRINTF(cli_buf);
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x",
+		   "WL_DACSwing/ BT_Dec_Pwr", coex_dm->cur_fw_dac_swing_lvl,
+		   coex_dm->cur_bt_dec_pwr_lvl);
+	CL_PRINTF(cli_buf);
+
+	u32tmp[0] = halbtc8723d2ant_ltecoex_indirect_read_reg(btcoexist, 0x38);
+	lte_coex_on = ((u32tmp[0] & BIT(7)) >> 7) ?  true : false;
+
+	if (lte_coex_on) {
+
+		u32tmp[0] = halbtc8723d2ant_ltecoex_indirect_read_reg(btcoexist,
+				0xa0);
+		u32tmp[1] = halbtc8723d2ant_ltecoex_indirect_read_reg(btcoexist,
+				0xa4);
+
+		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x",
+			   "LTE Coex  Table W_L/B_L",
+			   u32tmp[0] & 0xffff, u32tmp[1] & 0xffff);
+		CL_PRINTF(cli_buf);
+
+		u32tmp[0] = halbtc8723d2ant_ltecoex_indirect_read_reg(btcoexist,
+				0xa8);
+		u32tmp[1] = halbtc8723d2ant_ltecoex_indirect_read_reg(btcoexist,
+				0xac);
+		u32tmp[2] = halbtc8723d2ant_ltecoex_indirect_read_reg(btcoexist,
+				0xb0);
+		u32tmp[3] = halbtc8723d2ant_ltecoex_indirect_read_reg(btcoexist,
+				0xb4);
+
+		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+			   "\r\n %-35s = 0x%x/ 0x%x/ 0x%x/ 0x%x",
+			   "LTE Break Table W_L/B_L/L_W/L_B",
+			   u32tmp[0] & 0xffff, u32tmp[1] & 0xffff,
+			   u32tmp[2] & 0xffff, u32tmp[3] & 0xffff);
+		CL_PRINTF(cli_buf);
+
+	}
+
+	/* Hw setting		 */
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s",
+		   "============[Hw setting]============");
+	CL_PRINTF(cli_buf);
+	/*
+		u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x430);
+		u32tmp[1] = btcoexist->btc_read_4byte(btcoexist, 0x434);
+		u16tmp[0] = btcoexist->btc_read_2byte(btcoexist, 0x42a);
+		u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x456);
+		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/0x%x/0x%x/0x%x",
+			   "0x430/0x434/0x42a/0x456",
+			   u32tmp[0], u32tmp[1], u16tmp[0], u8tmp[0]);
+		CL_PRINTF(cli_buf);
+	*/
+	u32tmp[0] = halbtc8723d2ant_ltecoex_indirect_read_reg(btcoexist, 0x38);
+	u32tmp[1] = halbtc8723d2ant_ltecoex_indirect_read_reg(btcoexist, 0x54);
+	u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x73);
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s/ %s",
+		   "LTE Coex/Path Owner",
+		   ((lte_coex_on) ? "On" : "Off") ,
+		   ((u8tmp[0] & BIT(2)) ? "WL" : "BT"));
+	CL_PRINTF(cli_buf);
+
+	if (lte_coex_on) {
+		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+			   "\r\n %-35s = %d/ %d/ %d/ %d",
+			   "LTE 3Wire/OPMode/UART/UARTMode",
+			   (int)((u32tmp[0] & BIT(6)) >> 6),
+			   (int)((u32tmp[0] & (BIT(5) | BIT(4))) >> 4),
+			   (int)((u32tmp[0] & BIT(3)) >> 3),
+			   (int)(u32tmp[0] & (BIT(2) | BIT(1) | BIT(0))));
+		CL_PRINTF(cli_buf);
+
+		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d",
+			   "LTE_Busy/UART_Busy",
+			(int)((u32tmp[1] & BIT(1)) >> 1), (int)(u32tmp[1] & BIT(0)));
+		CL_PRINTF(cli_buf);
+	}
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+			   "\r\n %-35s = %s (BB:%s)/ %s (BB:%s)/ %s %d",
+			   "GNT_WL_Ctrl/GNT_BT_Ctrl/Dbg",
+			   ((u32tmp[0] & BIT(12)) ? "SW" : "HW"),
+			   ((u32tmp[0] & BIT(8)) ?	"SW" : "HW"),
+			   ((u32tmp[0] & BIT(14)) ? "SW" : "HW"),
+			   ((u32tmp[0] & BIT(10)) ?  "SW" : "HW"),
+			   ((u8tmp[0] & BIT(3)) ? "On" : "Off"),
+			   coex_sta->gnt_error_cnt);
+		CL_PRINTF(cli_buf);
+
+		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d",
+		   "GNT_WL/GNT_BT",
+		   (int)((u32tmp[1] & BIT(2)) >> 2),
+		   (int)((u32tmp[1] & BIT(3)) >> 3));
+	CL_PRINTF(cli_buf);
+
+	u16tmp[0] = btcoexist->btc_read_2byte(btcoexist, 0x948);
+	u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x67);
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x",
+		   "0x948/0x67[7]",
+		   u16tmp[0], (int)((u8tmp[0] & BIT(7)) >> 7));
+	CL_PRINTF(cli_buf);
+
+	u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x964);
+	u8tmp[1] = btcoexist->btc_read_1byte(btcoexist, 0x864);
+	u8tmp[2] = btcoexist->btc_read_1byte(btcoexist, 0xab7);
+	u8tmp[3] = btcoexist->btc_read_1byte(btcoexist, 0xa01);
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+		   "\r\n %-35s = 0x%x/ 0x%x/ 0x%x/ 0x%x",
+		   "0x964[1]/0x864[0]/0xab7[5]/0xa01[7]",
+		   (int)((u8tmp[0] & BIT(1)) >> 1), (int)((u8tmp[1] & BIT(0))),
+		   (int)((u8tmp[2] & BIT(3)) >> 3),
+		   (int)((u8tmp[3] & BIT(7)) >> 7));
+	CL_PRINTF(cli_buf);
+
+
+	u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x4c6);
+	u8tmp[1] = btcoexist->btc_read_1byte(btcoexist, 0x40);
+	u8tmp[2] = btcoexist->btc_read_1byte(btcoexist, 0x45e);
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x/ 0x%x",
+		   "0x4c6[4]/0x40[5]/0x45e[3](TxRetry)",
+		   (int)((u8tmp[0] & BIT(4)) >> 4),
+		   (int)((u8tmp[1] & BIT(5)) >> 5),
+		   (int)((u8tmp[2] & BIT(3)) >> 3));
+	CL_PRINTF(cli_buf);
+
+	u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x550);
+	u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x522);
+	u8tmp[1] = btcoexist->btc_read_1byte(btcoexist, 0x953);
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x/ %s",
+		   "0x550/0x522/4-RxAGC",
+		   u32tmp[0], u8tmp[0], (u8tmp[1] & 0x2) ? "On" : "Off");
+	CL_PRINTF(cli_buf);
+
+	fa_ofdm = btcoexist->btc_phydm_query_PHY_counter(btcoexist, PHYDM_INFO_FA_OFDM);
+	fa_cck = btcoexist->btc_phydm_query_PHY_counter(btcoexist, PHYDM_INFO_FA_CCK);
+	cca_ofdm = btcoexist->btc_phydm_query_PHY_counter(btcoexist, PHYDM_INFO_CCA_OFDM);
+	cca_cck = btcoexist->btc_phydm_query_PHY_counter(btcoexist, PHYDM_INFO_CCA_CCK);
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+		   "\r\n %-35s = 0x%x/ 0x%x/ 0x%x/ 0x%x",
+		   "CCK-CCA/CCK-FA/OFDM-CCA/OFDM-FA",
+		   cca_cck, fa_cck, cca_ofdm, fa_ofdm);
+	CL_PRINTF(cli_buf);
+
+#if 1
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d/ %d",
+		   "CRC_OK CCK/11g/11n/11n-agg",
+		   coex_sta->crc_ok_cck, coex_sta->crc_ok_11g,
+		   coex_sta->crc_ok_11n, coex_sta->crc_ok_11n_vht);
+	CL_PRINTF(cli_buf);
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d/ %d",
+		   "CRC_Err CCK/11g/11n/11n-agg",
+		   coex_sta->crc_err_cck, coex_sta->crc_err_11g,
+		   coex_sta->crc_err_11n, coex_sta->crc_err_11n_vht);
+	CL_PRINTF(cli_buf);
+#endif
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s/ %s/ %s/ %d",
+		   "WlHiPri/ Locking/ Locked/ Noisy",
+		   (coex_sta->wifi_is_high_pri_task ? "Yes" : "No"),
+		   (coex_sta->cck_lock ? "Yes" : "No"),
+		   (coex_sta->cck_ever_lock ? "Yes" : "No"),
+		   coex_sta->wl_noisy_level);
+	CL_PRINTF(cli_buf);
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d %s",
+		   "0x770(Hi-pri rx/tx)",
+		   coex_sta->high_priority_rx, coex_sta->high_priority_tx,
+		   (coex_sta->is_hiPri_rx_overhead ? "(scan overhead!!)" : ""));
+	CL_PRINTF(cli_buf);
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d %s",
+		   "0x774(Lo-pri rx/tx)",
+		   coex_sta->low_priority_rx, coex_sta->low_priority_tx,
+		   (bt_link_info->slave_role ? "(Slave!!)" : (
+		   coex_sta->is_tdma_btautoslot_hang ? "(auto-slot hang!!)" : "")));
+	CL_PRINTF(cli_buf);
+
+	btcoexist->btc_disp_dbg_msg(btcoexist, BTC_DBG_DISP_COEX_STATISTICS);
+}
+
+
+void ex_halbtc8723d2ant_ips_notify(IN struct btc_coexist *btcoexist, IN u8 type)
+{
+	if (btcoexist->manual_control ||	btcoexist->stop_coex_dm)
+		return;
+
+	if (BTC_IPS_ENTER == type) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], IPS ENTER notify\n");
+		BTC_TRACE(trace_buf);
+		coex_sta->under_ips = true;
+		coex_sta->under_lps = false;
+
+		halbtc8723d2ant_post_state_to_bt(btcoexist,
+				BT_8723D_2ANT_SCOREBOARD_ACTIVE |
+				BT_8723D_2ANT_SCOREBOARD_ONOFF |
+				BT_8723D_2ANT_SCOREBOARD_SCAN |
+				BT_8723D_2ANT_SCOREBOARD_UNDERTEST,
+				false);
+
+		halbtc8723d2ant_set_ant_path(btcoexist,
+					     BTC_ANT_PATH_AUTO,
+					     FORCE_EXEC,
+					     BT_8723D_2ANT_PHASE_WLAN_OFF);
+
+		halbtc8723d2ant_action_coex_all_off(btcoexist);
+	} else if (BTC_IPS_LEAVE == type) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], IPS LEAVE notify\n");
+		BTC_TRACE(trace_buf);
+		coex_sta->under_ips = false;
+#if 0
+		halbtc8723d2ant_post_state_to_bt(btcoexist,
+					 BT_8723D_2ANT_SCOREBOARD_ACTIVE, true);
+
+		halbtc8723d2ant_post_state_to_bt(btcoexist,
+					BT_8723D_2ANT_SCOREBOARD_ONOFF, true);
+#endif
+		halbtc8723d2ant_init_hw_config(btcoexist, false);
+		halbtc8723d2ant_init_coex_dm(btcoexist);
+		halbtc8723d2ant_query_bt_info(btcoexist);
+	}
+}
+
+void ex_halbtc8723d2ant_lps_notify(IN struct btc_coexist *btcoexist, IN u8 type)
+{
+	if (btcoexist->manual_control || btcoexist->stop_coex_dm)
+		return;
+
+	if (BTC_LPS_ENABLE == type) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], LPS ENABLE notify\n");
+		BTC_TRACE(trace_buf);
+		coex_sta->under_lps = true;
+		coex_sta->under_ips = false;
+
+		if (coex_sta->force_lps_on == true) { /* LPS No-32K */
+			/* Write WL "Active" in Score-board for PS-TDMA */
+			halbtc8723d2ant_post_state_to_bt(btcoexist,
+					 BT_8723D_2ANT_SCOREBOARD_ACTIVE, true);
+
+		} else { /* LPS-32K, need check if this h2c 0x71 can work?? (2015/08/28) */
+			/* Write WL "Non-Active" in Score-board for Native-PS */
+			halbtc8723d2ant_post_state_to_bt(btcoexist,
+				 BT_8723D_2ANT_SCOREBOARD_ACTIVE, false);
+		}
+
+
+	} else if (BTC_LPS_DISABLE == type) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], LPS DISABLE notify\n");
+		BTC_TRACE(trace_buf);
+		coex_sta->under_lps = false;
+
+		halbtc8723d2ant_post_state_to_bt(btcoexist,
+					 BT_8723D_2ANT_SCOREBOARD_ACTIVE, true);
+	}
+}
+
+void ex_halbtc8723d2ant_scan_notify(IN struct btc_coexist *btcoexist,
+				    IN u8 type)
+{
+	u32	u32tmp;
+	u8	u8tmpa, u8tmpb;
+	boolean	wifi_connected = false;
+
+
+	if (btcoexist->manual_control ||
+	    btcoexist->stop_coex_dm)
+		return;
+
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED,
+			   &wifi_connected);
+
+	/*  this can't be removed for RF off_on event, or BT would dis-connect */
+	halbtc8723d2ant_query_bt_info(btcoexist);
+
+	if (BTC_SCAN_START == type) {
+
+		if (!wifi_connected)
+			coex_sta->wifi_is_high_pri_task = true;
+
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], SCAN START notify\n");
+		BTC_TRACE(trace_buf);
+
+		halbtc8723d2ant_post_state_to_bt(btcoexist,
+					BT_8723D_2ANT_SCOREBOARD_ACTIVE |
+					BT_8723D_2ANT_SCOREBOARD_SCAN |
+					BT_8723D_2ANT_SCOREBOARD_ONOFF,
+					true);
+
+		halbtc8723d2ant_set_ant_path(btcoexist,
+					     BTC_ANT_PATH_AUTO,
+					     FORCE_EXEC,
+					     BT_8723D_2ANT_PHASE_2G_RUNTIME);
+
+		halbtc8723d2ant_run_coexist_mechanism(btcoexist);
+
+	} else if (BTC_SCAN_FINISH == type) {
+
+		coex_sta->wifi_is_high_pri_task = false;
+
+		btcoexist->btc_get(btcoexist, BTC_GET_U1_AP_NUM,
+				   &coex_sta->scan_ap_num);
+
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], SCAN FINISH notify  (Scan-AP = %d)\n",
+			    coex_sta->scan_ap_num);
+		BTC_TRACE(trace_buf);
+
+		halbtc8723d2ant_post_state_to_bt(btcoexist,
+					 BT_8723D_2ANT_SCOREBOARD_SCAN, false);
+
+		halbtc8723d2ant_run_coexist_mechanism(btcoexist);
+	}
+
+}
+
+void ex_halbtc8723d2ant_connect_notify(IN struct btc_coexist *btcoexist,
+				       IN u8 type)
+{
+	if (btcoexist->manual_control ||
+	    btcoexist->stop_coex_dm)
+		return;
+
+	if (BTC_ASSOCIATE_START == type) {
+
+		coex_sta->wifi_is_high_pri_task = true;
+
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], CONNECT START notify\n");
+		BTC_TRACE(trace_buf);
+
+		halbtc8723d2ant_post_state_to_bt(btcoexist,
+					 BT_8723D_2ANT_SCOREBOARD_ACTIVE |
+					 BT_8723D_2ANT_SCOREBOARD_SCAN |
+					 BT_8723D_2ANT_SCOREBOARD_ONOFF,
+					 true);
+
+		halbtc8723d2ant_set_ant_path(btcoexist,
+					     BTC_ANT_PATH_AUTO,
+					     FORCE_EXEC,
+					     BT_8723D_2ANT_PHASE_2G_RUNTIME);
+
+		halbtc8723d2ant_run_coexist_mechanism(btcoexist);
+		/* To keep TDMA case during connect process,
+		to avoid changed by Btinfo and runcoexmechanism */
+		coex_sta->freeze_coexrun_by_btinfo = true;
+
+		coex_dm->arp_cnt = 0;
+
+	} else if (BTC_ASSOCIATE_FINISH == type) {
+
+		coex_sta->wifi_is_high_pri_task = false;
+		coex_sta->freeze_coexrun_by_btinfo = false;
+
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], CONNECT FINISH notify\n");
+		BTC_TRACE(trace_buf);
+
+		halbtc8723d2ant_run_coexist_mechanism(btcoexist);
+	}
+}
+
+void ex_halbtc8723d2ant_media_status_notify(IN struct btc_coexist *btcoexist,
+		IN u8 type)
+{
+	u8			h2c_parameter[3] = {0};
+	u32			wifi_bw;
+	u8			wifi_central_chnl;
+	u8			ap_num = 0;
+	boolean		wifi_under_b_mode = false;
+
+	if (btcoexist->manual_control ||
+	    btcoexist->stop_coex_dm)
+		return;
+
+	if (BTC_MEDIA_CONNECT == type) {
+
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], MEDIA connect notify\n");
+		BTC_TRACE(trace_buf);
+
+		halbtc8723d2ant_post_state_to_bt(btcoexist,
+					 BT_8723D_2ANT_SCOREBOARD_ACTIVE |
+					 BT_8723D_2ANT_SCOREBOARD_ONOFF,
+					 true);
+
+		halbtc8723d2ant_set_ant_path(btcoexist,
+					     BTC_ANT_PATH_AUTO,
+					     FORCE_EXEC,
+					     BT_8723D_2ANT_PHASE_2G_RUNTIME);
+
+		btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_B_MODE,
+				   &wifi_under_b_mode);
+
+		/* Set CCK Tx/Rx high Pri except 11b mode */
+		if (wifi_under_b_mode) {
+			btcoexist->btc_write_1byte(btcoexist, 0x6cd,
+						   0x00); /* CCK Tx */
+			btcoexist->btc_write_1byte(btcoexist, 0x6cf,
+						   0x00); /* CCK Rx */
+		} else {
+
+			btcoexist->btc_write_1byte(btcoexist, 0x6cd,
+						   0x00); /* CCK Tx */
+			btcoexist->btc_write_1byte(btcoexist, 0x6cf,
+						   0x10); /* CCK Rx */
+		}
+
+	} else {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], MEDIA disconnect notify\n");
+		BTC_TRACE(trace_buf);
+
+		btcoexist->btc_write_1byte(btcoexist, 0x6cd, 0x0); /* CCK Tx */
+		btcoexist->btc_write_1byte(btcoexist, 0x6cf, 0x0); /* CCK Rx */
+
+		halbtc8723d2ant_post_state_to_bt(btcoexist,
+				 BT_8723D_2ANT_SCOREBOARD_ACTIVE, false);
+	}
+
+
+	halbtc8723d2ant_update_wifi_channel_info(btcoexist, type);
+}
+
+void ex_halbtc8723d2ant_specific_packet_notify(IN struct btc_coexist *btcoexist,
+		IN u8 type)
+{
+	boolean under_4way = false;
+
+	if (btcoexist->manual_control ||
+	    btcoexist->stop_coex_dm)
+		return;
+
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_4_WAY_PROGRESS,
+			   &under_4way);
+
+	if (under_4way) {
+
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], specific Packet ---- under_4way!!\n");
+		BTC_TRACE(trace_buf);
+
+		coex_sta->wifi_is_high_pri_task = true;
+		coex_sta->specific_pkt_period_cnt = 2;
+
+	} else if (BTC_PACKET_ARP == type) {
+
+		coex_dm->arp_cnt++;
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], specific Packet ARP notify -cnt = %d\n",
+			    coex_dm->arp_cnt);
+		BTC_TRACE(trace_buf);
+
+	} else {
+
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			"[BTCoex], specific Packet DHCP or EAPOL notify [Type = %d]\n",
+			    type);
+		BTC_TRACE(trace_buf);
+
+		coex_sta->wifi_is_high_pri_task = true;
+		coex_sta->specific_pkt_period_cnt = 2;
+	}
+
+	if (coex_sta->wifi_is_high_pri_task) {
+		halbtc8723d2ant_post_state_to_bt(btcoexist,
+					 BT_8723D_2ANT_SCOREBOARD_ACTIVE, true);
+		halbtc8723d2ant_run_coexist_mechanism(btcoexist);
+	}
+
+}
+
+void ex_halbtc8723d2ant_bt_info_notify(IN struct btc_coexist *btcoexist,
+				       IN u8 *tmp_buf, IN u8 length)
+{
+	u8			i, rsp_source = 0;
+	boolean		wifi_connected = false;
+	boolean	wifi_scan = false, wifi_link = false, wifi_roam = false,
+		    wifi_busy = false;
+	static boolean is_scoreboard_scan = false;
+
+	if (psd_scan->is_AntDet_running == true) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			"[BTCoex], bt_info_notify return for AntDet is running\n");
+		BTC_TRACE(trace_buf);
+		return;
+	}
+
+	rsp_source = tmp_buf[0] & 0xf;
+	if (rsp_source >= BT_INFO_SRC_8723D_2ANT_MAX)
+		rsp_source = BT_INFO_SRC_8723D_2ANT_WIFI_FW;
+	coex_sta->bt_info_c2h_cnt[rsp_source]++;
+
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+		    "[BTCoex], Bt_info[%d], len=%d, data=[", rsp_source,
+		    length);
+	BTC_TRACE(trace_buf);
+
+	for (i = 0; i < length; i++) {
+		coex_sta->bt_info_c2h[rsp_source][i] = tmp_buf[i];
+
+		if (i == length - 1) {
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "0x%02x]\n",
+				    tmp_buf[i]);
+			BTC_TRACE(trace_buf);
+		} else {
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "0x%02x, ",
+				    tmp_buf[i]);
+			BTC_TRACE(trace_buf);
+		}
+	}
+
+	coex_sta->bt_info = coex_sta->bt_info_c2h[rsp_source][1];
+	coex_sta->bt_info_ext = coex_sta->bt_info_c2h[rsp_source][4];
+	coex_sta->bt_info_ext2 = coex_sta->bt_info_c2h[rsp_source][5];
+
+	if (BT_INFO_SRC_8723D_2ANT_WIFI_FW != rsp_source) {
+
+		/* if 0xff, it means BT is under WHCK test */
+		coex_sta->bt_whck_test = ((coex_sta->bt_info == 0xff) ? true :
+					  false);
+
+		coex_sta->bt_create_connection = ((
+			coex_sta->bt_info_c2h[rsp_source][2] & 0x80) ? true :
+						  false);
+
+		/* unit: %, value-100 to translate to unit: dBm */
+		coex_sta->bt_rssi = coex_sta->bt_info_c2h[rsp_source][3] * 2 +
+				    10;
+
+		coex_sta->c2h_bt_remote_name_req = ((
+			coex_sta->bt_info_c2h[rsp_source][2] & 0x20) ? true :
+						    false);
+
+		coex_sta->is_A2DP_3M = ((coex_sta->bt_info_c2h[rsp_source][2] &
+					 0x10) ? true : false);
+
+		coex_sta->acl_busy = ((coex_sta->bt_info_c2h[rsp_source][1] &
+				       0x9) ? true : false);
+
+		coex_sta->voice_over_HOGP = ((coex_sta->bt_info_ext & 0x10) ?
+					     true : false);
+
+		coex_sta->c2h_bt_inquiry_page = ((coex_sta->bt_info &
+			  BT_INFO_8723D_2ANT_B_INQ_PAGE) ? true : false);
+
+		coex_sta->a2dp_bit_pool = (((
+			coex_sta->bt_info_c2h[rsp_source][1] & 0x49) == 0x49) ?
+				   coex_sta->bt_info_c2h[rsp_source][6] : 0);
+
+		coex_sta->bt_retry_cnt = coex_sta->bt_info_c2h[rsp_source][2] &
+					 0xf;
+
+		coex_sta->is_autoslot = coex_sta->bt_info_ext2 & 0x8;
+
+		coex_sta->forbidden_slot = coex_sta->bt_info_ext2 & 0x7;
+
+		coex_sta->hid_busy_num = (coex_sta->bt_info_ext2 & 0x30) >> 4;
+
+		coex_sta->hid_pair_cnt = (coex_sta->bt_info_ext2 & 0xc0) >> 6;
+
+		if (coex_sta->bt_retry_cnt >= 1)
+			coex_sta->pop_event_cnt++;
+
+		if (coex_sta->c2h_bt_remote_name_req)
+			coex_sta->cnt_RemoteNameReq++;
+
+		if (coex_sta->bt_info_ext & BIT(1))
+			coex_sta->cnt_ReInit++;
+
+		if (coex_sta->bt_info_ext & BIT(2)) {
+			coex_sta->cnt_setupLink++;
+			coex_sta->is_setupLink = true;
+		} else
+			coex_sta->is_setupLink = false;
+
+		if (coex_sta->bt_info_ext & BIT(3))
+			coex_sta->cnt_IgnWlanAct++;
+
+		if (coex_sta->bt_create_connection) {
+			coex_sta->cnt_Page++;
+
+			btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY,
+					   &wifi_busy);
+
+			btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_SCAN, &wifi_scan);
+			btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_LINK, &wifi_link);
+			btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_ROAM, &wifi_roam);
+
+			if ((wifi_link) || (wifi_roam) || (wifi_scan) ||
+			    (coex_sta->wifi_is_high_pri_task) || (wifi_busy)) {
+
+				is_scoreboard_scan = true;
+				halbtc8723d2ant_post_state_to_bt(btcoexist,
+					 BT_8723D_2ANT_SCOREBOARD_SCAN, true);
+
+			} else
+				halbtc8723d2ant_post_state_to_bt(btcoexist,
+					 BT_8723D_2ANT_SCOREBOARD_SCAN, false);
+
+		} else {
+				if (is_scoreboard_scan) {
+					halbtc8723d2ant_post_state_to_bt(btcoexist,
+						 BT_8723D_2ANT_SCOREBOARD_SCAN, false);
+					is_scoreboard_scan = false;
+				}
+		}
+
+		/* Here we need to resend some wifi info to BT */
+		/* because bt is reset and loss of the info. */
+
+		if ((!btcoexist->manual_control) &&
+		    (!btcoexist->stop_coex_dm)) {
+
+			btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED,
+					   &wifi_connected);
+
+			/*  Re-Init */
+			if ((coex_sta->bt_info_ext & BIT(1))) {
+				BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+					"[BTCoex], BT ext info bit1 check, send wifi BW&Chnl to BT!!\n");
+				BTC_TRACE(trace_buf);
+				if (wifi_connected)
+					halbtc8723d2ant_update_wifi_channel_info(
+						btcoexist, BTC_MEDIA_CONNECT);
+				else
+					halbtc8723d2ant_update_wifi_channel_info(
+						btcoexist,
+						BTC_MEDIA_DISCONNECT);
+			}
+
+
+			/*  If Ignore_WLanAct && not SetUp_Link or Role_Switch */
+			if ((coex_sta->bt_info_ext & BIT(3)) &&
+				(!(coex_sta->bt_info_ext & BIT(2))) &&
+				(!(coex_sta->bt_info_ext & BIT(6)))) {
+
+				BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+					"[BTCoex], BT ext info bit3 check, set BT NOT to ignore Wlan active!!\n");
+				BTC_TRACE(trace_buf);
+				halbtc8723d2ant_ignore_wlan_act(btcoexist,
+							FORCE_EXEC, false);
+			} else {
+				if (coex_sta->bt_info_ext & BIT(2)) {
+					BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+					"[BTCoex], BT ignore Wlan active because Re-link!!\n");
+					BTC_TRACE(trace_buf);
+				} else if (coex_sta->bt_info_ext & BIT(6)) {
+					BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+					"[BTCoex], BT ignore Wlan active because Role-Switch!!\n");
+					BTC_TRACE(trace_buf);
+				}
+			}
+		}
+
+	}
+
+	if ((coex_sta->bt_info_ext & BIT(5))) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+					"[BTCoex], BT ext info bit4 check, query BLE Scan type!!\n");
+		BTC_TRACE(trace_buf);
+		coex_sta->bt_ble_scan_type = btcoexist->btc_get_ble_scan_type_from_bt(btcoexist);
+
+		if ((coex_sta->bt_ble_scan_type & 0x1) == 0x1)
+			coex_sta->bt_ble_scan_para[0]  = btcoexist->btc_get_ble_scan_para_from_bt(btcoexist, 0x1);
+		if ((coex_sta->bt_ble_scan_type & 0x2) == 0x2)
+			coex_sta->bt_ble_scan_para[1]  = btcoexist->btc_get_ble_scan_para_from_bt(btcoexist, 0x2);
+		if ((coex_sta->bt_ble_scan_type & 0x4) == 0x4)
+			coex_sta->bt_ble_scan_para[2]  = btcoexist->btc_get_ble_scan_para_from_bt(btcoexist, 0x4);
+	}
+
+	halbtc8723d2ant_update_bt_link_info(btcoexist);
+
+	halbtc8723d2ant_run_coexist_mechanism(btcoexist);
+}
+
+void ex_halbtc8723d2ant_rf_status_notify(IN struct btc_coexist *btcoexist,
+		IN u8 type)
+{
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], RF Status notify\n");
+	BTC_TRACE(trace_buf);
+
+	if (BTC_RF_ON == type) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], RF is turned ON!!\n");
+		BTC_TRACE(trace_buf);
+
+		btcoexist->stop_coex_dm = false;
+#if 0
+		halbtc8723d2ant_post_state_to_bt(btcoexist,
+					 BT_8723D_2ANT_SCOREBOARD_ACTIVE, true);
+		halbtc8723d2ant_post_state_to_bt(btcoexist,
+					 BT_8723D_2ANT_SCOREBOARD_ONOFF, true);
+#endif
+	} else if (BTC_RF_OFF == type) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], RF is turned OFF!!\n");
+		BTC_TRACE(trace_buf);
+
+		halbtc8723d2ant_set_ant_path(btcoexist,
+					     BTC_ANT_PATH_AUTO,
+					     FORCE_EXEC,
+					     BT_8723D_2ANT_PHASE_WLAN_OFF);
+
+		halbtc8723d2ant_action_coex_all_off(btcoexist);
+
+		halbtc8723d2ant_post_state_to_bt(btcoexist,
+				BT_8723D_2ANT_SCOREBOARD_ACTIVE |
+				BT_8723D_2ANT_SCOREBOARD_ONOFF |
+				BT_8723D_2ANT_SCOREBOARD_SCAN |
+				BT_8723D_2ANT_SCOREBOARD_UNDERTEST,
+				false);
+
+		btcoexist->stop_coex_dm = true;
+
+	}
+}
+
+void ex_halbtc8723d2ant_halt_notify(IN struct btc_coexist *btcoexist)
+{
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], Halt notify\n");
+	BTC_TRACE(trace_buf);
+
+	halbtc8723d2ant_set_ant_path(btcoexist,
+				     BTC_ANT_PATH_AUTO,
+				     FORCE_EXEC,
+				     BT_8723D_2ANT_PHASE_WLAN_OFF);
+
+	ex_halbtc8723d2ant_media_status_notify(btcoexist, BTC_MEDIA_DISCONNECT);
+
+	halbtc8723d2ant_post_state_to_bt(btcoexist,
+				BT_8723D_2ANT_SCOREBOARD_ACTIVE |
+				BT_8723D_2ANT_SCOREBOARD_ONOFF |
+				BT_8723D_2ANT_SCOREBOARD_SCAN |
+				BT_8723D_2ANT_SCOREBOARD_UNDERTEST,
+				false);
+}
+
+void ex_halbtc8723d2ant_pnp_notify(IN struct btc_coexist *btcoexist,
+				   IN u8 pnp_state)
+{
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], Pnp notify\n");
+	BTC_TRACE(trace_buf);
+
+	if ((BTC_WIFI_PNP_SLEEP == pnp_state) ||
+	    (BTC_WIFI_PNP_SLEEP_KEEP_ANT == pnp_state)) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], Pnp notify to SLEEP\n");
+		BTC_TRACE(trace_buf);
+
+		/* Sinda 20150819, workaround for driver skip leave IPS/LPS to speed up sleep time. */
+		/* Driver do not leave IPS/LPS when driver is going to sleep, so BTCoexistence think wifi is still under IPS/LPS */
+		/* BT should clear UnderIPS/UnderLPS state to avoid mismatch state after wakeup. */
+		coex_sta->under_ips = false;
+		coex_sta->under_lps = false;
+
+		halbtc8723d2ant_post_state_to_bt(btcoexist,
+				BT_8723D_2ANT_SCOREBOARD_ACTIVE |
+				BT_8723D_2ANT_SCOREBOARD_ONOFF |
+				BT_8723D_2ANT_SCOREBOARD_SCAN |
+				BT_8723D_2ANT_SCOREBOARD_UNDERTEST,
+				false);
+
+		if (BTC_WIFI_PNP_SLEEP_KEEP_ANT == pnp_state) {
+
+			halbtc8723d2ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO,
+						     FORCE_EXEC,
+					     BT_8723D_2ANT_PHASE_2G_RUNTIME);
+		} else {
+
+			halbtc8723d2ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO,
+						     FORCE_EXEC,
+					     BT_8723D_2ANT_PHASE_WLAN_OFF);
+		}
+
+
+	} else if (BTC_WIFI_PNP_WAKE_UP == pnp_state) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], Pnp notify to WAKE UP\n");
+		BTC_TRACE(trace_buf);
+#if 0
+		halbtc8723d2ant_post_state_to_bt(btcoexist,
+					BT_8723D_2ANT_SCOREBOARD_ACTIVE, true);
+		halbtc8723d2ant_post_state_to_bt(btcoexist,
+					BT_8723D_2ANT_SCOREBOARD_ONOFF, true);
+#endif
+	}
+}
+
+void ex_halbtc8723d2ant_periodical(IN struct btc_coexist *btcoexist)
+{
+	struct  btc_board_info	*board_info = &btcoexist->board_info;
+	boolean wifi_busy = false;
+	u32	bt_patch_ver;
+	static u8 cnt = 0;
+	boolean bt_relink_finish = false;
+
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+		    "[BTCoex], ************* Periodical *************\n");
+	BTC_TRACE(trace_buf);
+
+#if (BT_AUTO_REPORT_ONLY_8723D_2ANT == 0)
+	halbtc8723d2ant_query_bt_info(btcoexist);
+#endif
+
+	halbtc8723d2ant_monitor_bt_ctr(btcoexist);
+	halbtc8723d2ant_monitor_wifi_ctr(btcoexist);
+	halbtc8723d2ant_monitor_bt_enable_disable(btcoexist);
+
+#if 0
+		btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy);
+
+		/* halbtc8723d2ant_read_score_board(btcoexist, &bt_scoreboard_val); */
+
+		if (wifi_busy) {
+			halbtc8723d2ant_post_state_to_bt(btcoexist,
+					BT_8723D_2ANT_SCOREBOARD_UNDERTEST, true);
+			/*
+			halbtc8723d2ant_post_state_to_bt(btcoexist,
+						 BT_8723D_2ANT_SCOREBOARD_WLBUSY, true);
+
+			if (bt_scoreboard_val & BIT(6))
+				halbtc8723d2ant_query_bt_info(btcoexist); */
+		} else {
+			halbtc8723d2ant_post_state_to_bt(btcoexist,
+						BT_8723D_2ANT_SCOREBOARD_UNDERTEST, false);
+			/*
+			halbtc8723d2ant_post_state_to_bt(btcoexist,
+						BT_8723D_2ANT_SCOREBOARD_WLBUSY,
+						false);  */
+		}
+#endif
+
+	if (coex_sta->bt_relink_downcount != 0) {
+		coex_sta->bt_relink_downcount--;
+
+		if (coex_sta->bt_relink_downcount == 0)
+			bt_relink_finish = true;
+	}
+
+	/* for 4-way, DHCP, EAPOL packet */
+	if (coex_sta->specific_pkt_period_cnt > 0) {
+
+		coex_sta->specific_pkt_period_cnt--;
+
+		if ((coex_sta->specific_pkt_period_cnt == 0) &&
+		    (coex_sta->wifi_is_high_pri_task))
+			coex_sta->wifi_is_high_pri_task = false;
+
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			"[BTCoex], ***************** Hi-Pri Task = %s*****************\n",
+			    (coex_sta->wifi_is_high_pri_task ? "Yes" :
+			     "No"));
+		BTC_TRACE(trace_buf);
+
+	}
+
+	if (!coex_sta->bt_disabled) {
+
+#if BT_8723D_2ANT_ANTDET_ENABLE
+
+		if (board_info->btdm_ant_det_finish) {
+			if ((psd_scan->ant_det_result == 12) &&
+			    (psd_scan->ant_det_psd_scan_peak_val == 0)
+			    && (!psd_scan->is_AntDet_running))
+				psd_scan->ant_det_psd_scan_peak_val =
+					btcoexist->btc_get_ant_det_val_from_bt(
+						btcoexist) * 100;
+		}
+
+#endif
+	}
+
+
+	if (halbtc8723d2ant_is_wifibt_status_changed(btcoexist))
+		halbtc8723d2ant_run_coexist_mechanism(btcoexist);
+}
+
+void ex_halbtc8723d2ant_set_antenna_notify(IN struct btc_coexist *btcoexist,
+		IN u8 type)
+{
+	struct  btc_board_info	*board_info = &btcoexist->board_info;
+
+	if (btcoexist->manual_control || btcoexist->stop_coex_dm)
+		return;
+
+	if (type == 2) { /* two antenna */
+		board_info->ant_div_cfg = true;
+
+		halbtc8723d2ant_set_ant_path(btcoexist, BTC_ANT_PATH_WIFI,
+					     FORCE_EXEC,
+					     BT_8723D_2ANT_PHASE_2G_RUNTIME);
+
+	} else { /* one antenna */
+
+		halbtc8723d2ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO,
+					     FORCE_EXEC,
+					     BT_8723D_2ANT_PHASE_2G_RUNTIME);
+
+	}
+}
+
+#ifdef PLATFORM_WINDOWS
+#pragma optimize("", off)
+#endif
+void ex_halbtc8723d2ant_antenna_detection(IN struct btc_coexist *btcoexist,
+		IN u32 cent_freq, IN u32 offset, IN u32 span, IN u32 seconds)
+{
+
+	static u32 ant_det_count = 0, ant_det_fail_count = 0;
+	struct  btc_board_info	*board_info = &btcoexist->board_info;
+	u16		u16tmp;
+	u8			AntDetval = 0;
+
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+		    "xxxxxxxxxxxxxxxx Ext Call AntennaDetect()!!\n");
+	BTC_TRACE(trace_buf);
+
+#if BT_8723D_2ANT_ANTDET_ENABLE
+
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+		    "xxxxxxxxxxxxxxxx Call AntennaDetect()!!\n");
+	BTC_TRACE(trace_buf);
+
+	if (seconds == 0) {
+		psd_scan->ant_det_try_count	= 0;
+		psd_scan->ant_det_fail_count	= 0;
+		ant_det_count = 0;
+		ant_det_fail_count = 0;
+		board_info->btdm_ant_det_finish = false;
+		board_info->btdm_ant_num_by_ant_det = 1;
+		return;
+	}
+
+	if (!board_info->btdm_ant_det_finish) {
+		psd_scan->ant_det_inteval_count =
+			psd_scan->ant_det_inteval_count + 2;
+
+		if (psd_scan->ant_det_inteval_count >=
+		    BT_8723D_2ANT_ANTDET_RETRY_INTERVAL) {
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				"xxxxxxxxxxxxxxxx AntennaDetect(), Antenna Det Timer is up, Try Detect!!\n");
+			BTC_TRACE(trace_buf);
+
+			psd_scan->is_AntDet_running = true;
+
+			halbtc8723d2ant_read_score_board(btcoexist,	&u16tmp);
+
+			if (u16tmp & BIT(
+				2)) { /* Antenna detection is already done before last WL power on   */
+				board_info->btdm_ant_det_finish = true;
+				psd_scan->ant_det_try_count = 1;
+				psd_scan->ant_det_fail_count = 0;
+				board_info->btdm_ant_num_by_ant_det = (u16tmp &
+							       BIT(3)) ? 1 : 2;
+				psd_scan->ant_det_result = 12;
+
+				psd_scan->ant_det_psd_scan_peak_val =
+					btcoexist->btc_get_ant_det_val_from_bt(
+						btcoexist) * 100;
+
+				BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+					"xxxxxxxxxxxxxxxx AntennaDetect(), Antenna Det Result from BT (%d-Ant)\n",
+					board_info->btdm_ant_num_by_ant_det);
+				BTC_TRACE(trace_buf);
+			} else
+				board_info->btdm_ant_det_finish =
+					halbtc8723d2ant_psd_antenna_detection_check(
+						btcoexist);
+
+			btcoexist->bdontenterLPS = false;
+
+			if (board_info->btdm_ant_det_finish) {
+				BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+					"xxxxxxxxxxxxxxxx AntennaDetect(), Antenna Det Success!!\n");
+				BTC_TRACE(trace_buf);
+
+				/*for 8723d, btc_set_bt_trx_mask is just used to
+					notify BT stop le tx and Ant Det Result , not set BT RF TRx Mask  */
+				if (psd_scan->ant_det_result != 12) {
+
+					AntDetval = (u8)(
+						psd_scan->ant_det_psd_scan_peak_val
+							    / 100) & 0x7f;
+
+					AntDetval =
+						(board_info->btdm_ant_num_by_ant_det
+						 == 1) ? (AntDetval | 0x80) :
+						AntDetval;
+
+					BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+						"xxxxxx AntennaDetect(), Ant Count = %d, PSD Val = %d\n",
+						    ((AntDetval &
+						      0x80) ? 1
+						     : 2), AntDetval
+						    & 0x7f);
+					BTC_TRACE(trace_buf);
+
+					if (btcoexist->btc_set_bt_trx_mask(
+						    btcoexist, AntDetval))
+						BTC_SPRINTF(trace_buf,
+							    BT_TMP_BUF_SIZE,
+							"xxxxxx AntennaDetect(), Notify BT stop le tx by set_bt_trx_mask ok!\n");
+					else
+						BTC_SPRINTF(trace_buf,
+							    BT_TMP_BUF_SIZE,
+							"xxxxxx AntennaDetect(), Notify BT stop le tx by set_bt_trx_mask fail!\n");
+
+					BTC_TRACE(trace_buf);
+				} else
+					board_info->antdetval =
+						psd_scan->ant_det_psd_scan_peak_val/100;
+				
+				board_info->btdm_ant_det_complete_fail = false;
+
+			} else {
+				BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+					"xxxxxxxxxxxxxxxx AntennaDetect(), Antenna Det Fail!!\n");
+				BTC_TRACE(trace_buf);
+			}
+
+			psd_scan->ant_det_inteval_count = 0;
+			psd_scan->is_AntDet_running = false;
+
+			/* stimulate coex running */
+			halbtc8723d2ant_run_coexist_mechanism(
+				btcoexist);
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				"xxxxxxxxxxxxxxxx AntennaDetect(), Stimulate Coex running\n!!");
+			BTC_TRACE(trace_buf);
+		} else {
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				"xxxxxxxxxxxxxxxx AntennaDetect(), Antenna Det Timer is not up! (%d)\n",
+				    psd_scan->ant_det_inteval_count);
+			BTC_TRACE(trace_buf);
+
+			if (psd_scan->ant_det_inteval_count == 8)
+				btcoexist->bdontenterLPS = true;
+			else
+				btcoexist->bdontenterLPS = false;
+		}
+
+	}
+#endif
+
+
+}
+
+
+void ex_halbtc8723d2ant_display_ant_detection(IN struct btc_coexist *btcoexist)
+{
+
+#if BT_8723D_2ANT_ANTDET_ENABLE
+	struct  btc_board_info	*board_info = &btcoexist->board_info;
+
+	if (psd_scan->ant_det_try_count != 0)	{
+		halbtc8723d2ant_psd_show_antenna_detect_result(btcoexist);
+
+		if (board_info->btdm_ant_det_finish)
+			halbtc8723d2ant_psd_showdata(btcoexist);
+	}
+#endif
+
+}
+
+
+#endif
+
+#endif	/*  #if (RTL8723D_SUPPORT == 1) */
+
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/btc/halbtc8723d2ant.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/btc/halbtc8723d2ant.h
--- linux-5.6.3/3rdparty/rtl8821ce/hal/btc/halbtc8723d2ant.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/btc/halbtc8723d2ant.h	2020-04-10 16:35:06.783658527 +0300
@@ -0,0 +1,420 @@
+
+#if (BT_SUPPORT == 1 && COEX_SUPPORT == 1)
+
+#if (RTL8723D_SUPPORT == 1)
+
+/* *******************************************
+ * The following is for 8723D 2Ant BT Co-exist definition
+ * ******************************************* */
+#define	BT_8723D_2ANT_COEX_DBG					0
+#define	BT_AUTO_REPORT_ONLY_8723D_2ANT				1
+
+
+#define	BT_INFO_8723D_2ANT_B_FTP						BIT(7)
+#define	BT_INFO_8723D_2ANT_B_A2DP					BIT(6)
+#define	BT_INFO_8723D_2ANT_B_HID						BIT(5)
+#define	BT_INFO_8723D_2ANT_B_SCO_BUSY				BIT(4)
+#define	BT_INFO_8723D_2ANT_B_ACL_BUSY				BIT(3)
+#define	BT_INFO_8723D_2ANT_B_INQ_PAGE				BIT(2)
+#define	BT_INFO_8723D_2ANT_B_SCO_ESCO				BIT(1)
+#define	BT_INFO_8723D_2ANT_B_CONNECTION				BIT(0)
+
+#define		BTC_RSSI_COEX_THRESH_TOL_8723D_2ANT		2
+
+
+#define	BT_8723D_2ANT_WIFI_RSSI_COEXSWITCH_THRES1				80  /* unit: % WiFi RSSI Threshold for   2-Ant free-run/2-Ant TDMA translation, default = 42 */
+#define	BT_8723D_2ANT_BT_RSSI_COEXSWITCH_THRES1				80 /*  unit: % BT RSSI Threshold for      2-Ant free-run/2-Ant TDMA translation, default = 46 */
+#define	BT_8723D_2ANT_WIFI_RSSI_COEXSWITCH_THRES2				80  /* unit: % WiFi RSSI Threshold for   1-Ant TDMA/1-Ant PS-TDMA translation, default = 42 */
+#define	BT_8723D_2ANT_BT_RSSI_COEXSWITCH_THRES2				80 /*  unit: % BT RSSI Threshold for      1-Ant TDMA/1-Ant PS-TDMA translation, default = 46 */
+#define	BT_8723D_2ANT_DEFAULT_ISOLATION						15	 /*  unit: dB */
+#define   BT_8723D_2ANT_WIFI_MAX_TX_POWER						15	 /*  unit: dBm */
+#define   BT_8723D_2ANT_BT_MAX_TX_POWER							3	 /*  unit: dBm */
+#define   BT_8723D_2ANT_WIFI_SIR_THRES1							-15  /*  unit: dB */
+#define   BT_8723D_2ANT_WIFI_SIR_THRES2							-30  /*  unit: dB */
+#define   BT_8723D_2ANT_BT_SIR_THRES1							-15		 /*  unit: dB */
+#define   BT_8723D_2ANT_BT_SIR_THRES2							-30		 /*  unit: dB */
+
+
+/* for Antenna detection */
+#define	BT_8723D_2ANT_ANTDET_PSDTHRES_BACKGROUND						50
+#define	BT_8723D_2ANT_ANTDET_PSDTHRES_2ANT_BADISOLATION				70
+#define	BT_8723D_2ANT_ANTDET_PSDTHRES_2ANT_GOODISOLATION			52
+#define	BT_8723D_2ANT_ANTDET_PSDTHRES_1ANT							40
+#define	BT_8723D_2ANT_ANTDET_RETRY_INTERVAL							10	/* retry timer if ant det is fail, unit: second */
+#define	BT_8723D_2ANT_ANTDET_SWEEPPOINT_DELAY							60000
+#define	BT_8723D_2ANT_ANTDET_ENABLE										1
+#define	BT_8723D_2ANT_ANTDET_BTTXTIME									100
+#define	BT_8723D_2ANT_ANTDET_BTTXCHANNEL								39
+#define	BT_8723D_2ANT_ANTDET_PSD_SWWEEPCOUNT						50
+
+
+#define	BT_8723D_2ANT_LTECOEX_INDIRECTREG_ACCESS_TIMEOUT		30000
+
+enum bt_8723d_2ant_signal_state {
+	BT_8723D_2ANT_SIG_STA_SET_TO_LOW		= 0x0,
+	BT_8723D_2ANT_SIG_STA_SET_BY_HW		= 0x0,
+	BT_8723D_2ANT_SIG_STA_SET_TO_HIGH		= 0x1,
+	BT_8723D_2ANT_SIG_STA_MAX
+};
+
+enum bt_8723d_2ant_path_ctrl_owner {
+	BT_8723D_2ANT_PCO_BTSIDE		= 0x0,
+	BT_8723D_2ANT_PCO_WLSIDE	= 0x1,
+	BT_8723D_2ANT_PCO_MAX
+};
+
+enum bt_8723d_2ant_gnt_ctrl_type {
+	BT_8723D_2ANT_GNT_TYPE_CTRL_BY_PTA		= 0x0,
+	BT_8723D_2ANT_GNT_TYPE_CTRL_BY_SW		= 0x1,
+	BT_8723D_2ANT_GNT_TYPE_MAX
+};
+
+enum bt_8723d_2ant_gnt_ctrl_block {
+	BT_8723D_2ANT_GNT_BLOCK_RFC_BB		= 0x0,
+	BT_8723D_2ANT_GNT_BLOCK_RFC			= 0x1,
+	BT_8723D_2ANT_GNT_BLOCK_BB			= 0x2,
+	BT_8723D_2ANT_GNT_BLOCK_MAX
+};
+
+enum bt_8723d_2ant_lte_coex_table_type {
+	BT_8723D_2ANT_CTT_WL_VS_LTE			= 0x0,
+	BT_8723D_2ANT_CTT_BT_VS_LTE			= 0x1,
+	BT_8723D_2ANT_CTT_MAX
+};
+
+enum bt_8723d_2ant_lte_break_table_type {
+	BT_8723D_2ANT_LBTT_WL_BREAK_LTE			= 0x0,
+	BT_8723D_2ANT_LBTT_BT_BREAK_LTE				= 0x1,
+	BT_8723D_2ANT_LBTT_LTE_BREAK_WL			= 0x2,
+	BT_8723D_2ANT_LBTT_LTE_BREAK_BT				= 0x3,
+	BT_8723D_2ANT_LBTT_MAX
+};
+
+enum bt_info_src_8723d_2ant {
+	BT_INFO_SRC_8723D_2ANT_WIFI_FW			= 0x0,
+	BT_INFO_SRC_8723D_2ANT_BT_RSP				= 0x1,
+	BT_INFO_SRC_8723D_2ANT_BT_ACTIVE_SEND		= 0x2,
+	BT_INFO_SRC_8723D_2ANT_MAX
+};
+
+enum bt_8723d_2ant_bt_status {
+	BT_8723D_2ANT_BT_STATUS_NON_CONNECTED_IDLE	= 0x0,
+	BT_8723D_2ANT_BT_STATUS_CONNECTED_IDLE		= 0x1,
+	BT_8723D_2ANT_BT_STATUS_INQ_PAGE				= 0x2,
+	BT_8723D_2ANT_BT_STATUS_ACL_BUSY				= 0x3,
+	BT_8723D_2ANT_BT_STATUS_SCO_BUSY				= 0x4,
+	BT_8723D_2ANT_BT_STATUS_ACL_SCO_BUSY			= 0x5,
+	BT_8723D_2ANT_BT_STATUS_MAX
+};
+
+enum bt_8723d_2ant_coex_algo {
+	BT_8723D_2ANT_COEX_ALGO_UNDEFINED			= 0x0,
+	BT_8723D_2ANT_COEX_ALGO_SCO				= 0x1,
+	BT_8723D_2ANT_COEX_ALGO_HID				= 0x2,
+	BT_8723D_2ANT_COEX_ALGO_A2DP				= 0x3,
+	BT_8723D_2ANT_COEX_ALGO_A2DP_PANHS		= 0x4,
+	BT_8723D_2ANT_COEX_ALGO_PANEDR			= 0x5,
+	BT_8723D_2ANT_COEX_ALGO_PANHS			= 0x6,
+	BT_8723D_2ANT_COEX_ALGO_PANEDR_A2DP		= 0x7,
+	BT_8723D_2ANT_COEX_ALGO_PANEDR_HID		= 0x8,
+	BT_8723D_2ANT_COEX_ALGO_HID_A2DP_PANEDR	= 0x9,
+	BT_8723D_2ANT_COEX_ALGO_HID_A2DP			= 0xa,
+	BT_8723D_2ANT_COEX_ALGO_NOPROFILEBUSY		= 0xb,
+	BT_8723D_2ANT_COEX_ALGO_MAX
+};
+
+enum bt_8723d_2ant_phase {
+	BT_8723D_2ANT_PHASE_COEX_INIT								= 0x0,
+	BT_8723D_2ANT_PHASE_WLANONLY_INIT							= 0x1,
+	BT_8723D_2ANT_PHASE_WLAN_OFF								= 0x2,
+	BT_8723D_2ANT_PHASE_2G_RUNTIME								= 0x3,
+	BT_8723D_2ANT_PHASE_5G_RUNTIME								= 0x4,
+	BT_8723D_2ANT_PHASE_BTMPMODE								= 0x5,
+	BT_8723D_2ANT_PHASE_ANTENNA_DET								= 0x6,
+	BT_8723D_2ANT_PHASE_COEX_POWERON							= 0x7,
+	BT_8723D_2ANT_PHASE_MAX
+};
+
+enum bt_8723d_2ant_Scoreboard {
+	BT_8723D_2ANT_SCOREBOARD_ACTIVE								= BIT(0),
+	BT_8723D_2ANT_SCOREBOARD_ONOFF								= BIT(1),
+	BT_8723D_2ANT_SCOREBOARD_SCAN								= BIT(2),
+	BT_8723D_2ANT_SCOREBOARD_UNDERTEST							= BIT(3),
+	BT_8723D_2ANT_SCOREBOARD_WLBUSY								= BIT(6)
+};
+
+
+
+struct coex_dm_8723d_2ant {
+	/* fw mechanism */
+	u8		pre_bt_dec_pwr_lvl;
+	u8		cur_bt_dec_pwr_lvl;
+	u8		pre_fw_dac_swing_lvl;
+	u8		cur_fw_dac_swing_lvl;
+	boolean		cur_ignore_wlan_act;
+	boolean		pre_ignore_wlan_act;
+	u8		pre_ps_tdma;
+	u8		cur_ps_tdma;
+	u8		ps_tdma_para[5];
+	u8		ps_tdma_du_adj_type;
+	boolean		reset_tdma_adjust;
+	boolean		pre_ps_tdma_on;
+	boolean		cur_ps_tdma_on;
+	boolean		pre_bt_auto_report;
+	boolean		cur_bt_auto_report;
+
+	/* sw mechanism */
+	boolean		pre_rf_rx_lpf_shrink;
+	boolean		cur_rf_rx_lpf_shrink;
+	u32		bt_rf_0x1e_backup;
+	boolean	pre_low_penalty_ra;
+	boolean		cur_low_penalty_ra;
+	boolean		pre_dac_swing_on;
+	u32		pre_dac_swing_lvl;
+	boolean		cur_dac_swing_on;
+	u32		cur_dac_swing_lvl;
+	boolean		pre_adc_back_off;
+	boolean		cur_adc_back_off;
+	boolean	pre_agc_table_en;
+	boolean		cur_agc_table_en;
+	u32		pre_val0x6c0;
+	u32		cur_val0x6c0;
+	u32		pre_val0x6c4;
+	u32		cur_val0x6c4;
+	u32		pre_val0x6c8;
+	u32		cur_val0x6c8;
+	u8		pre_val0x6cc;
+	u8		cur_val0x6cc;
+	boolean		limited_dig;
+
+	/* algorithm related */
+	u8		pre_algorithm;
+	u8		cur_algorithm;
+	u8		bt_status;
+	u8		wifi_chnl_info[3];
+
+	boolean		need_recover0x948;
+	u32		backup0x948;
+
+	u8		pre_lps;
+	u8		cur_lps;
+	u8		pre_rpwm;
+	u8		cur_rpwm;
+
+	boolean		is_switch_to_1dot5_ant;
+	u8		switch_thres_offset;
+	u32					arp_cnt;
+
+	u8		pre_ant_pos_type;
+	u8		cur_ant_pos_type;
+};
+
+struct coex_sta_8723d_2ant {
+	boolean				bt_disabled;
+	boolean				bt_link_exist;
+	boolean				sco_exist;
+	boolean				a2dp_exist;
+	boolean				hid_exist;
+	boolean				pan_exist;
+
+	boolean				under_lps;
+	boolean				under_ips;
+	u32					high_priority_tx;
+	u32					high_priority_rx;
+	u32					low_priority_tx;
+	u32					low_priority_rx;
+	boolean             is_hiPri_rx_overhead;
+	u8					bt_rssi;
+	boolean				bt_tx_rx_mask;
+	u8					pre_bt_rssi_state;
+	u8					pre_wifi_rssi_state[4];
+	u8					bt_info_c2h[BT_INFO_SRC_8723D_2ANT_MAX][10];
+	u32					bt_info_c2h_cnt[BT_INFO_SRC_8723D_2ANT_MAX];
+	boolean				bt_whck_test;
+	boolean				c2h_bt_inquiry_page;
+	boolean				c2h_bt_remote_name_req;
+	u8					bt_retry_cnt;
+	u8					bt_info_ext;
+	u8					bt_info_ext2;
+	u32					pop_event_cnt;
+	u8					scan_ap_num;
+
+	u32					crc_ok_cck;
+	u32					crc_ok_11g;
+	u32					crc_ok_11n;
+	u32					crc_ok_11n_vht;
+
+	u32					crc_err_cck;
+	u32					crc_err_11g;
+	u32					crc_err_11n;
+	u32					crc_err_11n_vht;
+
+	boolean				cck_lock;
+	boolean				pre_ccklock;
+	boolean				cck_ever_lock;
+	u8					coex_table_type;
+	boolean				force_lps_on;
+
+	u8					dis_ver_info_cnt;
+
+	u8					a2dp_bit_pool;
+	u8					cut_version;
+
+	boolean				concurrent_rx_mode_on;
+
+	u16					score_board;
+	u8					isolation_btween_wb;   /* 0~ 50 */
+	u8					wifi_coex_thres;
+	u8					bt_coex_thres;
+	u8					wifi_coex_thres2;
+	u8					bt_coex_thres2;
+
+	u8					num_of_profile;
+	boolean				acl_busy;
+	boolean				bt_create_connection;
+	boolean				wifi_is_high_pri_task;
+	u32					specific_pkt_period_cnt;
+	u32					bt_coex_supported_feature;
+	u32					bt_coex_supported_version;
+
+	u8					bt_ble_scan_type;
+	u32					bt_ble_scan_para[3];
+
+	boolean				run_time_state;
+	boolean				freeze_coexrun_by_btinfo;
+
+	boolean				is_A2DP_3M;
+	boolean				voice_over_HOGP;
+	u8                  bt_info;
+	boolean				is_autoslot;
+	u8					forbidden_slot;
+	u8					hid_busy_num;
+	u8					hid_pair_cnt;
+
+	u32					cnt_RemoteNameReq;
+	u32					cnt_setupLink;
+	u32					cnt_ReInit;
+	u32					cnt_IgnWlanAct;
+	u32					cnt_Page;
+	u32					cnt_RoleSwitch;
+
+	u16					bt_reg_vendor_ac;
+	u16					bt_reg_vendor_ae;
+
+	boolean				is_setupLink;
+	boolean				wl_noisy_level;
+	u32                 gnt_error_cnt;
+
+	u8					bt_afh_map[10];
+	u8					bt_relink_downcount;
+	boolean				is_tdma_btautoslot;
+	boolean				is_tdma_btautoslot_hang;
+
+	boolean             is_eSCO_mode;
+};
+
+#define BT_8723D_2ANT_ANTDET_PSD_POINTS			256	/* MAX:1024 */
+#define BT_8723D_2ANT_ANTDET_PSD_AVGNUM		1	/* MAX:3 */
+#define BT_8723D_2ANT_ANTDET_BUF_LEN			16
+
+struct psdscan_sta_8723d_2ant {
+
+	u32			ant_det_bt_le_channel;  /* BT LE Channel ex:2412 */
+	u32			ant_det_bt_tx_time;
+	u32			ant_det_pre_psdscan_peak_val;
+	boolean			ant_det_is_ant_det_available;
+	u32			ant_det_psd_scan_peak_val;
+	boolean			ant_det_is_btreply_available;
+	u32			ant_det_psd_scan_peak_freq;
+
+	u8			ant_det_result;
+	u8			ant_det_peak_val[BT_8723D_2ANT_ANTDET_BUF_LEN];
+	u8			ant_det_peak_freq[BT_8723D_2ANT_ANTDET_BUF_LEN];
+	u32			ant_det_try_count;
+	u32			ant_det_fail_count;
+	u32			ant_det_inteval_count;
+	u32			ant_det_thres_offset;
+
+	u32			real_cent_freq;
+	s32			real_offset;
+	u32			real_span;
+
+	u32			psd_band_width;  /* unit: Hz */
+	u32			psd_point;		/* 128/256/512/1024 */
+	u32			psd_report[1024];  /* unit:dB (20logx), 0~255 */
+	u32			psd_report_max_hold[1024];  /* unit:dB (20logx), 0~255 */
+	u32			psd_start_point;
+	u32			psd_stop_point;
+	u32			psd_max_value_point;
+	u32			psd_max_value;
+	u32			psd_max_value2;
+	u32			psd_avg_value;   /* filter loop_max_value that below BT_8723D_1ANT_ANTDET_PSDTHRES_1ANT, and average the rest*/
+	u32			psd_loop_max_value[BT_8723D_2ANT_ANTDET_PSD_SWWEEPCOUNT];  /*max value in each loop */
+	u32			psd_start_base;
+	u32			psd_avg_num;	/* 1/8/16/32 */
+	u32			psd_gen_count;
+	boolean			is_AntDet_running;
+	boolean			is_psd_show_max_only;
+};
+
+
+/* *******************************************
+ * The following is interface which will notify coex module.
+ * ******************************************* */
+void ex_halbtc8723d2ant_power_on_setting(IN struct btc_coexist *btcoexist);
+void ex_halbtc8723d2ant_pre_load_firmware(IN struct btc_coexist *btcoexist);
+void ex_halbtc8723d2ant_init_hw_config(IN struct btc_coexist *btcoexist,
+				       IN boolean wifi_only);
+void ex_halbtc8723d2ant_init_coex_dm(IN struct btc_coexist *btcoexist);
+void ex_halbtc8723d2ant_ips_notify(IN struct btc_coexist *btcoexist,
+				   IN u8 type);
+void ex_halbtc8723d2ant_lps_notify(IN struct btc_coexist *btcoexist,
+				   IN u8 type);
+void ex_halbtc8723d2ant_scan_notify(IN struct btc_coexist *btcoexist,
+				    IN u8 type);
+void ex_halbtc8723d2ant_connect_notify(IN struct btc_coexist *btcoexist,
+				       IN u8 type);
+void ex_halbtc8723d2ant_media_status_notify(IN struct btc_coexist *btcoexist,
+		IN u8 type);
+void ex_halbtc8723d2ant_specific_packet_notify(IN struct btc_coexist *btcoexist,
+		IN u8 type);
+void ex_halbtc8723d2ant_bt_info_notify(IN struct btc_coexist *btcoexist,
+				       IN u8 *tmp_buf, IN u8 length);
+void ex_halbtc8723d2ant_rf_status_notify(IN struct btc_coexist *btcoexist,
+		IN u8 type);
+void ex_halbtc8723d2ant_halt_notify(IN struct btc_coexist *btcoexist);
+void ex_halbtc8723d2ant_pnp_notify(IN struct btc_coexist *btcoexist,
+				   IN u8 pnp_state);
+void ex_halbtc8723d2ant_set_antenna_notify(IN struct btc_coexist *btcoexist,
+		IN u8 type);
+void ex_halbtc8723d2ant_periodical(IN struct btc_coexist *btcoexist);
+void ex_halbtc8723d2ant_display_coex_info(IN struct btc_coexist *btcoexist);
+void ex_halbtc8723d2ant_antenna_detection(IN struct btc_coexist *btcoexist,
+		IN u32 cent_freq, IN u32 offset, IN u32 span, IN u32 seconds);
+void ex_halbtc8723d2ant_display_ant_detection(IN struct btc_coexist *btcoexist);
+
+
+#else
+#define	ex_halbtc8723d2ant_power_on_setting(btcoexist)
+#define	ex_halbtc8723d2ant_pre_load_firmware(btcoexist)
+#define	ex_halbtc8723d2ant_init_hw_config(btcoexist, wifi_only)
+#define	ex_halbtc8723d2ant_init_coex_dm(btcoexist)
+#define	ex_halbtc8723d2ant_ips_notify(btcoexist, type)
+#define	ex_halbtc8723d2ant_lps_notify(btcoexist, type)
+#define	ex_halbtc8723d2ant_scan_notify(btcoexist, type)
+#define	ex_halbtc8723d2ant_connect_notify(btcoexist, type)
+#define	ex_halbtc8723d2ant_media_status_notify(btcoexist, type)
+#define	ex_halbtc8723d2ant_specific_packet_notify(btcoexist, type)
+#define	ex_halbtc8723d2ant_bt_info_notify(btcoexist, tmp_buf, length)
+#define	ex_halbtc8723d2ant_rf_status_notify(btcoexist, type)
+#define	ex_halbtc8723d2ant_halt_notify(btcoexist)
+#define	ex_halbtc8723d2ant_pnp_notify(btcoexist, pnp_state)
+#define	ex_halbtc8723d2ant_periodical(btcoexist)
+#define	ex_halbtc8723d2ant_display_coex_info(btcoexist)
+#define	ex_halbtc8723d2ant_set_antenna_notify(btcoexist, type)
+#define	ex_halbtc8723d2ant_display_ant_detection(btcoexist)
+#define	ex_halbtc8723d2ant_antenna_detection(btcoexist, cent_freq, offset, span, seconds)
+#endif
+
+#endif
+
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/btc/halbtc8812a1ant.c linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/btc/halbtc8812a1ant.c
--- linux-5.6.3/3rdparty/rtl8821ce/hal/btc/halbtc8812a1ant.c	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/btc/halbtc8812a1ant.c	2020-04-10 16:35:06.783658527 +0300
@@ -0,0 +1,3461 @@
+/* ************************************************************
+ * Description:
+ *
+ * This file is for RTL8812A Co-exist mechanism
+ *
+ * History
+ * 2012/11/15 Cosa first check in.
+ *
+ * ************************************************************ */
+
+/* ************************************************************
+ * include files
+ * ************************************************************ */
+#include "mp_precomp.h"
+
+#if (BT_SUPPORT == 1 && COEX_SUPPORT == 1)
+
+#if (RTL8812A_SUPPORT == 1)
+/* ************************************************************
+ * Global variables, these are static variables
+ * ************************************************************ */
+static u8	 *trace_buf = &gl_btc_trace_buf[0];
+static struct  coex_dm_8812a_1ant		glcoex_dm_8812a_1ant;
+static struct  coex_dm_8812a_1ant	*coex_dm = &glcoex_dm_8812a_1ant;
+static struct  coex_sta_8812a_1ant		glcoex_sta_8812a_1ant;
+static struct  coex_sta_8812a_1ant	*coex_sta = &glcoex_sta_8812a_1ant;
+
+const char *const glbt_info_src_8812a_1ant[] = {
+	"BT Info[wifi fw]",
+	"BT Info[bt rsp]",
+	"BT Info[bt auto report]",
+};
+
+u32	glcoex_ver_date_8812a_1ant = 20140708;
+u32	glcoex_ver_8812a_1ant = 0x52;
+
+/* ************************************************************
+ * local function proto type if needed
+ * ************************************************************
+ * ************************************************************
+ * local function start with halbtc8812a1ant_
+ * ************************************************************ */
+u8 halbtc8812a1ant_bt_rssi_state(u8 level_num, u8 rssi_thresh, u8 rssi_thresh1)
+{
+	s32			bt_rssi = 0;
+	u8			bt_rssi_state = coex_sta->pre_bt_rssi_state;
+
+	bt_rssi = coex_sta->bt_rssi;
+
+	if (level_num == 2) {
+		if ((coex_sta->pre_bt_rssi_state == BTC_RSSI_STATE_LOW) ||
+		    (coex_sta->pre_bt_rssi_state ==
+		     BTC_RSSI_STATE_STAY_LOW)) {
+			if (bt_rssi >= (rssi_thresh +
+					BTC_RSSI_COEX_THRESH_TOL_8812A_1ANT))
+				bt_rssi_state = BTC_RSSI_STATE_HIGH;
+			else
+				bt_rssi_state = BTC_RSSI_STATE_STAY_LOW;
+		} else {
+			if (bt_rssi < rssi_thresh)
+				bt_rssi_state = BTC_RSSI_STATE_LOW;
+			else
+				bt_rssi_state = BTC_RSSI_STATE_STAY_HIGH;
+		}
+	} else if (level_num == 3) {
+		if (rssi_thresh > rssi_thresh1) {
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				    "[BTCoex], BT Rssi thresh error!!\n");
+			BTC_TRACE(trace_buf);
+			return coex_sta->pre_bt_rssi_state;
+		}
+
+		if ((coex_sta->pre_bt_rssi_state == BTC_RSSI_STATE_LOW) ||
+		    (coex_sta->pre_bt_rssi_state ==
+		     BTC_RSSI_STATE_STAY_LOW)) {
+			if (bt_rssi >= (rssi_thresh +
+					BTC_RSSI_COEX_THRESH_TOL_8812A_1ANT))
+				bt_rssi_state = BTC_RSSI_STATE_MEDIUM;
+			else
+				bt_rssi_state = BTC_RSSI_STATE_STAY_LOW;
+		} else if ((coex_sta->pre_bt_rssi_state ==
+			    BTC_RSSI_STATE_MEDIUM) ||
+			   (coex_sta->pre_bt_rssi_state ==
+			    BTC_RSSI_STATE_STAY_MEDIUM)) {
+			if (bt_rssi >= (rssi_thresh1 +
+					BTC_RSSI_COEX_THRESH_TOL_8812A_1ANT))
+				bt_rssi_state = BTC_RSSI_STATE_HIGH;
+			else if (bt_rssi < rssi_thresh)
+				bt_rssi_state = BTC_RSSI_STATE_LOW;
+			else
+				bt_rssi_state = BTC_RSSI_STATE_STAY_MEDIUM;
+		} else {
+			if (bt_rssi < rssi_thresh1)
+				bt_rssi_state = BTC_RSSI_STATE_MEDIUM;
+			else
+				bt_rssi_state = BTC_RSSI_STATE_STAY_HIGH;
+		}
+	}
+
+	coex_sta->pre_bt_rssi_state = bt_rssi_state;
+
+	return bt_rssi_state;
+}
+
+u8 halbtc8812a1ant_wifi_rssi_state(IN struct btc_coexist *btcoexist,
+	   IN u8 index, IN u8 level_num, IN u8 rssi_thresh, IN u8 rssi_thresh1)
+{
+	s32			wifi_rssi = 0;
+	u8			wifi_rssi_state = coex_sta->pre_wifi_rssi_state[index];
+
+	btcoexist->btc_get(btcoexist, BTC_GET_S4_WIFI_RSSI, &wifi_rssi);
+
+	if (level_num == 2) {
+		if ((coex_sta->pre_wifi_rssi_state[index] == BTC_RSSI_STATE_LOW)
+		    ||
+		    (coex_sta->pre_wifi_rssi_state[index] ==
+		     BTC_RSSI_STATE_STAY_LOW)) {
+			if (wifi_rssi >= (rssi_thresh +
+					  BTC_RSSI_COEX_THRESH_TOL_8812A_1ANT))
+				wifi_rssi_state = BTC_RSSI_STATE_HIGH;
+			else
+				wifi_rssi_state = BTC_RSSI_STATE_STAY_LOW;
+		} else {
+			if (wifi_rssi < rssi_thresh)
+				wifi_rssi_state = BTC_RSSI_STATE_LOW;
+			else
+				wifi_rssi_state = BTC_RSSI_STATE_STAY_HIGH;
+		}
+	} else if (level_num == 3) {
+		if (rssi_thresh > rssi_thresh1) {
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				    "[BTCoex], wifi RSSI thresh error!!\n");
+			BTC_TRACE(trace_buf);
+			return coex_sta->pre_wifi_rssi_state[index];
+		}
+
+		if ((coex_sta->pre_wifi_rssi_state[index] == BTC_RSSI_STATE_LOW)
+		    ||
+		    (coex_sta->pre_wifi_rssi_state[index] ==
+		     BTC_RSSI_STATE_STAY_LOW)) {
+			if (wifi_rssi >= (rssi_thresh +
+					  BTC_RSSI_COEX_THRESH_TOL_8812A_1ANT))
+				wifi_rssi_state = BTC_RSSI_STATE_MEDIUM;
+			else
+				wifi_rssi_state = BTC_RSSI_STATE_STAY_LOW;
+		} else if ((coex_sta->pre_wifi_rssi_state[index] ==
+			    BTC_RSSI_STATE_MEDIUM) ||
+			   (coex_sta->pre_wifi_rssi_state[index] ==
+			    BTC_RSSI_STATE_STAY_MEDIUM)) {
+			if (wifi_rssi >= (rssi_thresh1 +
+					  BTC_RSSI_COEX_THRESH_TOL_8812A_1ANT))
+				wifi_rssi_state = BTC_RSSI_STATE_HIGH;
+			else if (wifi_rssi < rssi_thresh)
+				wifi_rssi_state = BTC_RSSI_STATE_LOW;
+			else
+				wifi_rssi_state = BTC_RSSI_STATE_STAY_MEDIUM;
+		} else {
+			if (wifi_rssi < rssi_thresh1)
+				wifi_rssi_state = BTC_RSSI_STATE_MEDIUM;
+			else
+				wifi_rssi_state = BTC_RSSI_STATE_STAY_HIGH;
+		}
+	}
+
+	coex_sta->pre_wifi_rssi_state[index] = wifi_rssi_state;
+
+	return wifi_rssi_state;
+}
+
+void halbtc8812a1ant_update_ra_mask(IN struct btc_coexist *btcoexist,
+				    IN boolean force_exec, IN u32 dis_rate_mask)
+{
+	coex_dm->cur_ra_mask = dis_rate_mask;
+
+	if (force_exec || (coex_dm->pre_ra_mask != coex_dm->cur_ra_mask))
+		btcoexist->btc_set(btcoexist, BTC_SET_ACT_UPDATE_RAMASK,
+				   &coex_dm->cur_ra_mask);
+	coex_dm->pre_ra_mask = coex_dm->cur_ra_mask;
+}
+
+/* to check 0x430/0x434 is correct?? */
+void halbtc8812a1ant_auto_rate_fallback_retry(IN struct btc_coexist *btcoexist,
+		IN boolean force_exec, IN u8 type)
+{
+	boolean	wifi_under_b_mode = false;
+
+	coex_dm->cur_arfr_type = type;
+
+	if (force_exec || (coex_dm->pre_arfr_type != coex_dm->cur_arfr_type)) {
+		switch (coex_dm->cur_arfr_type) {
+		case 0:	/* normal mode */
+			btcoexist->btc_write_4byte(btcoexist, 0x430,
+						   coex_dm->backup_arfr_cnt1);
+			btcoexist->btc_write_4byte(btcoexist, 0x434,
+						   coex_dm->backup_arfr_cnt2);
+			break;
+		case 1:
+			btcoexist->btc_get(btcoexist,
+					   BTC_GET_BL_WIFI_UNDER_B_MODE,
+					   &wifi_under_b_mode);
+			if (wifi_under_b_mode) {
+				btcoexist->btc_write_4byte(btcoexist,
+							   0x430, 0x0);
+				btcoexist->btc_write_4byte(btcoexist,
+							   0x434, 0x01010101);
+			} else {
+				btcoexist->btc_write_4byte(btcoexist,
+							   0x430, 0x0);
+				btcoexist->btc_write_4byte(btcoexist,
+							   0x434, 0x04030201);
+			}
+			break;
+		default:
+			break;
+		}
+	}
+
+	coex_dm->pre_arfr_type = coex_dm->cur_arfr_type;
+}
+
+/* to check 0x42a ?? */
+void halbtc8812a1ant_retry_limit(IN struct btc_coexist *btcoexist,
+				 IN boolean force_exec, IN u8 type)
+{
+	coex_dm->cur_retry_limit_type = type;
+
+	if (force_exec ||
+	    (coex_dm->pre_retry_limit_type !=
+	     coex_dm->cur_retry_limit_type)) {
+		switch (coex_dm->cur_retry_limit_type) {
+		case 0:	/* normal mode */
+			btcoexist->btc_write_2byte(btcoexist, 0x42a,
+						   coex_dm->backup_retry_limit);
+			break;
+		case 1:	/* retry limit=8 */
+			btcoexist->btc_write_2byte(btcoexist, 0x42a,
+						   0x0808);
+			break;
+		default:
+			break;
+		}
+	}
+
+	coex_dm->pre_retry_limit_type = coex_dm->cur_retry_limit_type;
+}
+
+/* to check 0x456?? */
+void halbtc8812a1ant_ampdu_max_time(IN struct btc_coexist *btcoexist,
+				    IN boolean force_exec, IN u8 type)
+{
+	coex_dm->cur_ampdu_time_type = type;
+
+	if (force_exec ||
+	    (coex_dm->pre_ampdu_time_type != coex_dm->cur_ampdu_time_type)) {
+		switch (coex_dm->cur_ampdu_time_type) {
+		case 0:	/* normal mode */
+			btcoexist->btc_write_1byte(btcoexist, 0x456,
+					   coex_dm->backup_ampdu_max_time);
+			break;
+		case 1:	/* AMPDU timw = 0x38 * 32us */
+			btcoexist->btc_write_1byte(btcoexist, 0x456,
+						   0x38);
+			break;
+		default:
+			break;
+		}
+	}
+
+	coex_dm->pre_ampdu_time_type = coex_dm->cur_ampdu_time_type;
+}
+
+void halbtc8812a1ant_limited_tx(IN struct btc_coexist *btcoexist,
+		IN boolean force_exec, IN u8 ra_mask_type, IN u8 arfr_type,
+				IN u8 retry_limit_type, IN u8 ampdu_time_type)
+{
+	switch (ra_mask_type) {
+	case 0:	/* normal mode */
+		halbtc8812a1ant_update_ra_mask(btcoexist, force_exec,
+					       0x0);
+		break;
+	case 1:	/* disable cck 1/2 */
+		halbtc8812a1ant_update_ra_mask(btcoexist, force_exec,
+					       0x00000003);
+		break;
+	case 2:	/* disable cck 1/2/5.5, ofdm 6/9/12/18/24, mcs 0/1/2/3/4 */
+		halbtc8812a1ant_update_ra_mask(btcoexist, force_exec,
+					       0x0001f1f7);
+		break;
+	default:
+		break;
+	}
+
+	halbtc8812a1ant_auto_rate_fallback_retry(btcoexist, force_exec,
+			arfr_type);
+	halbtc8812a1ant_retry_limit(btcoexist, force_exec, retry_limit_type);
+	halbtc8812a1ant_ampdu_max_time(btcoexist, force_exec, ampdu_time_type);
+}
+
+void halbtc8812a1ant_limited_rx(IN struct btc_coexist *btcoexist,
+			IN boolean force_exec, IN boolean rej_ap_agg_pkt,
+			IN boolean bt_ctrl_agg_buf_size, IN u8 agg_buf_size)
+{
+	boolean	reject_rx_agg = rej_ap_agg_pkt;
+	boolean	bt_ctrl_rx_agg_size = bt_ctrl_agg_buf_size;
+	u8	rx_agg_size = agg_buf_size;
+
+	/* ============================================ */
+	/*	Rx Aggregation related setting */
+	/* ============================================ */
+	btcoexist->btc_set(btcoexist, BTC_SET_BL_TO_REJ_AP_AGG_PKT,
+			   &reject_rx_agg);
+	/* decide BT control aggregation buf size or not */
+	btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_CTRL_AGG_SIZE,
+			   &bt_ctrl_rx_agg_size);
+	/* aggregation buf size, only work when BT control Rx aggregation size. */
+	btcoexist->btc_set(btcoexist, BTC_SET_U1_AGG_BUF_SIZE, &rx_agg_size);
+	/* real update aggregation setting */
+	btcoexist->btc_set(btcoexist, BTC_SET_ACT_AGGREGATE_CTRL, NULL);
+
+
+}
+
+void halbtc8812a1ant_query_bt_info(IN struct btc_coexist *btcoexist)
+{
+	u8	data_len = 3;
+	u8	buf[5] = {0};
+
+	if (!coex_sta->bt_disabled) {
+		if (!coex_sta->bt_info_query_cnt ||
+		    (coex_sta->bt_info_c2h_cnt[BT_INFO_SRC_8812A_1ANT_BT_RSP]
+		     - coex_sta->bt_info_query_cnt) > 2) {
+			buf[0] = data_len;
+			buf[1] = 0x1;	/* polling enable, 1=enable, 0=disable */
+			buf[2] = 0x2;	/* polling time in seconds */
+			buf[3] = 0x1;	/* auto report enable, 1=enable, 0=disable */
+
+			btcoexist->btc_set(btcoexist, BTC_SET_ACT_CTRL_BT_INFO,
+					   (void *)&buf[0]);
+		}
+	}
+	coex_sta->bt_info_query_cnt++;
+}
+
+void halbtc8812a1ant_monitor_bt_ctr(IN struct btc_coexist *btcoexist)
+{
+	u32			reg_hp_txrx, reg_lp_txrx, u32tmp;
+	u32			reg_hp_tx = 0, reg_hp_rx = 0, reg_lp_tx = 0, reg_lp_rx = 0;
+	static u8		num_of_bt_counter_chk = 0;
+
+	reg_hp_txrx = 0x770;
+	reg_lp_txrx = 0x774;
+
+	u32tmp = btcoexist->btc_read_4byte(btcoexist, reg_hp_txrx);
+	reg_hp_tx = u32tmp & MASKLWORD;
+	reg_hp_rx = (u32tmp & MASKHWORD) >> 16;
+
+	u32tmp = btcoexist->btc_read_4byte(btcoexist, reg_lp_txrx);
+	reg_lp_tx = u32tmp & MASKLWORD;
+	reg_lp_rx = (u32tmp & MASKHWORD) >> 16;
+
+	coex_sta->high_priority_tx = reg_hp_tx;
+	coex_sta->high_priority_rx = reg_hp_rx;
+	coex_sta->low_priority_tx = reg_lp_tx;
+	coex_sta->low_priority_rx = reg_lp_rx;
+
+	if ((coex_sta->low_priority_tx > 1150)  &&
+	    (!coex_sta->c2h_bt_inquiry_page))
+		coex_sta->pop_event_cnt++;
+
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+		    "[BTCoex], Hi-Pri Rx/Tx: %d/%d, Lo-Pri Rx/Tx: %d/%d\n",
+		    reg_hp_rx, reg_hp_tx, reg_lp_rx, reg_lp_tx);
+	BTC_TRACE(trace_buf);
+
+	/* reset counter */
+	btcoexist->btc_write_1byte(btcoexist, 0x76e, 0xc);
+
+	if ((reg_hp_tx == 0) && (reg_hp_rx == 0) && (reg_lp_tx == 0) &&
+	    (reg_lp_rx == 0)) {
+		num_of_bt_counter_chk++;
+		if (num_of_bt_counter_chk >= 3) {
+			halbtc8812a1ant_query_bt_info(btcoexist);
+			num_of_bt_counter_chk = 0;
+		}
+	}
+}
+
+/* to check registers */
+void halbtc8812a1ant_monitor_wifi_ctr(IN struct btc_coexist *btcoexist)
+{
+	s32	wifi_rssi = 0;
+	boolean wifi_busy = false, wifi_under_b_mode = false;
+	static u8 cck_lock_counter = 0;
+
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy);
+	btcoexist->btc_get(btcoexist, BTC_GET_S4_WIFI_RSSI, &wifi_rssi);
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_B_MODE,
+			   &wifi_under_b_mode);
+
+	if (coex_sta->under_ips) {
+		coex_sta->crc_ok_cck = 0;
+		coex_sta->crc_ok_11g = 0;
+		coex_sta->crc_ok_11n = 0;
+		coex_sta->crc_ok_11n_agg = 0;
+
+		coex_sta->crc_err_cck = 0;
+		coex_sta->crc_err_11g = 0;
+		coex_sta->crc_err_11n = 0;
+		coex_sta->crc_err_11n_agg = 0;
+	} else {
+		coex_sta->crc_ok_cck	= btcoexist->btc_read_2byte(btcoexist,
+					  0xf04);
+		coex_sta->crc_ok_11g	= btcoexist->btc_read_2byte(btcoexist,
+					  0xf14);
+		coex_sta->crc_ok_11n	= btcoexist->btc_read_2byte(btcoexist,
+					  0xf10);
+		coex_sta->crc_ok_11n_agg = btcoexist->btc_read_2byte(btcoexist,
+					   0xf40);
+
+		coex_sta->crc_err_cck	 = btcoexist->btc_read_2byte(btcoexist,
+					   0xf06);
+		coex_sta->crc_err_11g	 = btcoexist->btc_read_2byte(btcoexist,
+					   0xf16);
+		coex_sta->crc_err_11n	 = btcoexist->btc_read_2byte(btcoexist,
+					   0xf12);
+		coex_sta->crc_err_11n_agg = btcoexist->btc_read_2byte(btcoexist,
+					    0xf42);
+	}
+
+
+	/* reset counter */
+	btcoexist->btc_write_1byte_bitmask(btcoexist, 0xb58, 0x1, 0x1);
+	btcoexist->btc_write_1byte_bitmask(btcoexist, 0xb58, 0x1, 0x0);
+
+	if ((wifi_busy) && (wifi_rssi >= 30) && (!wifi_under_b_mode)) {
+		if ((coex_dm->bt_status == BT_8812A_1ANT_BT_STATUS_ACL_BUSY) ||
+		    (coex_dm->bt_status ==
+		     BT_8812A_1ANT_BT_STATUS_ACL_SCO_BUSY) ||
+		    (coex_dm->bt_status ==
+		     BT_8812A_1ANT_BT_STATUS_SCO_BUSY)) {
+			if (coex_sta->crc_ok_cck > (coex_sta->crc_ok_11g +
+						    coex_sta->crc_ok_11n +
+						    coex_sta->crc_ok_11n_agg)) {
+				if (cck_lock_counter < 5)
+					cck_lock_counter++;
+			} else {
+				if (cck_lock_counter > 0)
+					cck_lock_counter--;
+			}
+
+		} else {
+			if (cck_lock_counter > 0)
+				cck_lock_counter--;
+		}
+	} else {
+		if (cck_lock_counter > 0)
+			cck_lock_counter--;
+	}
+
+	if (!coex_sta->pre_ccklock) {
+
+		if (cck_lock_counter >= 5)
+			coex_sta->cck_lock = true;
+		else
+			coex_sta->cck_lock = false;
+	} else {
+		if (cck_lock_counter == 0)
+			coex_sta->cck_lock = false;
+		else
+			coex_sta->cck_lock = true;
+	}
+
+	coex_sta->pre_ccklock =  coex_sta->cck_lock;
+
+
+}
+
+boolean halbtc8812a1ant_is_wifi_status_changed(IN struct btc_coexist *btcoexist)
+{
+	static boolean	pre_wifi_busy = false, pre_under_4way = false,
+			pre_bt_hs_on = false;
+	boolean wifi_busy = false, under_4way = false, bt_hs_on = false;
+	boolean wifi_connected = false;
+
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED,
+			   &wifi_connected);
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy);
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on);
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_4_WAY_PROGRESS,
+			   &under_4way);
+
+	if (wifi_connected) {
+		if (wifi_busy != pre_wifi_busy) {
+			pre_wifi_busy = wifi_busy;
+			return true;
+		}
+		if (under_4way != pre_under_4way) {
+			pre_under_4way = under_4way;
+			return true;
+		}
+		if (bt_hs_on != pre_bt_hs_on) {
+			pre_bt_hs_on = bt_hs_on;
+			return true;
+		}
+	}
+
+	return false;
+}
+
+void halbtc8812a1ant_update_bt_link_info(IN struct btc_coexist *btcoexist)
+{
+	struct  btc_bt_link_info	*bt_link_info = &btcoexist->bt_link_info;
+	boolean				bt_hs_on = false;
+
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on);
+
+	bt_link_info->bt_link_exist = coex_sta->bt_link_exist;
+	bt_link_info->sco_exist = coex_sta->sco_exist;
+	bt_link_info->a2dp_exist = coex_sta->a2dp_exist;
+	bt_link_info->pan_exist = coex_sta->pan_exist;
+	bt_link_info->hid_exist = coex_sta->hid_exist;
+
+	/* work around for HS mode. */
+	if (bt_hs_on) {
+		bt_link_info->pan_exist = true;
+		bt_link_info->bt_link_exist = true;
+	}
+
+	/* check if Sco only */
+	if (bt_link_info->sco_exist &&
+	    !bt_link_info->a2dp_exist &&
+	    !bt_link_info->pan_exist &&
+	    !bt_link_info->hid_exist)
+		bt_link_info->sco_only = true;
+	else
+		bt_link_info->sco_only = false;
+
+	/* check if A2dp only */
+	if (!bt_link_info->sco_exist &&
+	    bt_link_info->a2dp_exist &&
+	    !bt_link_info->pan_exist &&
+	    !bt_link_info->hid_exist)
+		bt_link_info->a2dp_only = true;
+	else
+		bt_link_info->a2dp_only = false;
+
+	/* check if Pan only */
+	if (!bt_link_info->sco_exist &&
+	    !bt_link_info->a2dp_exist &&
+	    bt_link_info->pan_exist &&
+	    !bt_link_info->hid_exist)
+		bt_link_info->pan_only = true;
+	else
+		bt_link_info->pan_only = false;
+
+	/* check if Hid only */
+	if (!bt_link_info->sco_exist &&
+	    !bt_link_info->a2dp_exist &&
+	    !bt_link_info->pan_exist &&
+	    bt_link_info->hid_exist)
+		bt_link_info->hid_only = true;
+	else
+		bt_link_info->hid_only = false;
+}
+
+u8 halbtc8812a1ant_action_algorithm(IN struct btc_coexist *btcoexist)
+{
+	struct  btc_bt_link_info	*bt_link_info = &btcoexist->bt_link_info;
+	boolean				bt_hs_on = false;
+	u8				algorithm = BT_8812A_1ANT_COEX_ALGO_UNDEFINED;
+	u8				num_of_diff_profile = 0;
+
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on);
+
+	if (!bt_link_info->bt_link_exist) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], No BT link exists!!!\n");
+		BTC_TRACE(trace_buf);
+		return algorithm;
+	}
+
+	if (bt_link_info->sco_exist)
+		num_of_diff_profile++;
+	if (bt_link_info->hid_exist)
+		num_of_diff_profile++;
+	if (bt_link_info->pan_exist)
+		num_of_diff_profile++;
+	if (bt_link_info->a2dp_exist)
+		num_of_diff_profile++;
+
+	if (num_of_diff_profile == 1) {
+		if (bt_link_info->sco_exist) {
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				    "[BTCoex], BT Profile = SCO only\n");
+			BTC_TRACE(trace_buf);
+			algorithm = BT_8812A_1ANT_COEX_ALGO_SCO;
+		} else {
+			if (bt_link_info->hid_exist) {
+				BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+					"[BTCoex], BT Profile = HID only\n");
+				BTC_TRACE(trace_buf);
+				algorithm = BT_8812A_1ANT_COEX_ALGO_HID;
+			} else if (bt_link_info->a2dp_exist) {
+				BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+					"[BTCoex], BT Profile = A2DP only\n");
+				BTC_TRACE(trace_buf);
+				algorithm = BT_8812A_1ANT_COEX_ALGO_A2DP;
+			} else if (bt_link_info->pan_exist) {
+				if (bt_hs_on) {
+					BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+						"[BTCoex], BT Profile = PAN(HS) only\n");
+					BTC_TRACE(trace_buf);
+					algorithm =
+						BT_8812A_1ANT_COEX_ALGO_PANHS;
+				} else {
+					BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+						"[BTCoex], BT Profile = PAN(EDR) only\n");
+					BTC_TRACE(trace_buf);
+					algorithm =
+						BT_8812A_1ANT_COEX_ALGO_PANEDR;
+				}
+			}
+		}
+	} else if (num_of_diff_profile == 2) {
+		if (bt_link_info->sco_exist) {
+			if (bt_link_info->hid_exist) {
+				BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+					"[BTCoex], BT Profile = SCO + HID\n");
+				BTC_TRACE(trace_buf);
+				algorithm = BT_8812A_1ANT_COEX_ALGO_HID;
+			} else if (bt_link_info->a2dp_exist) {
+				BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+					"[BTCoex], BT Profile = SCO + A2DP ==> SCO\n");
+				BTC_TRACE(trace_buf);
+				algorithm = BT_8812A_1ANT_COEX_ALGO_SCO;
+			} else if (bt_link_info->pan_exist) {
+				if (bt_hs_on) {
+					BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+						"[BTCoex], BT Profile = SCO + PAN(HS)\n");
+					BTC_TRACE(trace_buf);
+					algorithm = BT_8812A_1ANT_COEX_ALGO_SCO;
+				} else {
+					BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+						"[BTCoex], BT Profile = SCO + PAN(EDR)\n");
+					BTC_TRACE(trace_buf);
+					algorithm =
+						BT_8812A_1ANT_COEX_ALGO_PANEDR_HID;
+				}
+			}
+		} else {
+			if (bt_link_info->hid_exist &&
+			    bt_link_info->a2dp_exist) {
+				BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+					"[BTCoex], BT Profile = HID + A2DP\n");
+				BTC_TRACE(trace_buf);
+				algorithm = BT_8812A_1ANT_COEX_ALGO_HID_A2DP;
+			} else if (bt_link_info->hid_exist &&
+				   bt_link_info->pan_exist) {
+				if (bt_hs_on) {
+					BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+						"[BTCoex], BT Profile = HID + PAN(HS)\n");
+					BTC_TRACE(trace_buf);
+					algorithm =
+						BT_8812A_1ANT_COEX_ALGO_HID_A2DP;
+				} else {
+					BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+						"[BTCoex], BT Profile = HID + PAN(EDR)\n");
+					BTC_TRACE(trace_buf);
+					algorithm =
+						BT_8812A_1ANT_COEX_ALGO_PANEDR_HID;
+				}
+			} else if (bt_link_info->pan_exist &&
+				   bt_link_info->a2dp_exist) {
+				if (bt_hs_on) {
+					BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+						"[BTCoex], BT Profile = A2DP + PAN(HS)\n");
+					BTC_TRACE(trace_buf);
+					algorithm =
+						BT_8812A_1ANT_COEX_ALGO_A2DP_PANHS;
+				} else {
+					BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+						"[BTCoex], BT Profile = A2DP + PAN(EDR)\n");
+					BTC_TRACE(trace_buf);
+					algorithm =
+						BT_8812A_1ANT_COEX_ALGO_PANEDR_A2DP;
+				}
+			}
+		}
+	} else if (num_of_diff_profile == 3) {
+		if (bt_link_info->sco_exist) {
+			if (bt_link_info->hid_exist &&
+			    bt_link_info->a2dp_exist) {
+				BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+					"[BTCoex], BT Profile = SCO + HID + A2DP ==> HID\n");
+				BTC_TRACE(trace_buf);
+				algorithm = BT_8812A_1ANT_COEX_ALGO_HID;
+			} else if (bt_link_info->hid_exist &&
+				   bt_link_info->pan_exist) {
+				if (bt_hs_on) {
+					BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+						"[BTCoex], BT Profile = SCO + HID + PAN(HS)\n");
+					BTC_TRACE(trace_buf);
+					algorithm =
+						BT_8812A_1ANT_COEX_ALGO_HID_A2DP;
+				} else {
+					BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+						"[BTCoex], BT Profile = SCO + HID + PAN(EDR)\n");
+					BTC_TRACE(trace_buf);
+					algorithm =
+						BT_8812A_1ANT_COEX_ALGO_PANEDR_HID;
+				}
+			} else if (bt_link_info->pan_exist &&
+				   bt_link_info->a2dp_exist) {
+				if (bt_hs_on) {
+					BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+						"[BTCoex], BT Profile = SCO + A2DP + PAN(HS)\n");
+					BTC_TRACE(trace_buf);
+					algorithm = BT_8812A_1ANT_COEX_ALGO_SCO;
+				} else {
+					BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+						"[BTCoex], BT Profile = SCO + A2DP + PAN(EDR) ==> HID\n");
+					BTC_TRACE(trace_buf);
+					algorithm =
+						BT_8812A_1ANT_COEX_ALGO_PANEDR_HID;
+				}
+			}
+		} else {
+			if (bt_link_info->hid_exist &&
+			    bt_link_info->pan_exist &&
+			    bt_link_info->a2dp_exist) {
+				if (bt_hs_on) {
+					BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+						"[BTCoex], BT Profile = HID + A2DP + PAN(HS)\n");
+					BTC_TRACE(trace_buf);
+					algorithm =
+						BT_8812A_1ANT_COEX_ALGO_HID_A2DP;
+				} else {
+					BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+						"[BTCoex], BT Profile = HID + A2DP + PAN(EDR)\n");
+					BTC_TRACE(trace_buf);
+					algorithm =
+						BT_8812A_1ANT_COEX_ALGO_HID_A2DP_PANEDR;
+				}
+			}
+		}
+	} else if (num_of_diff_profile >= 3) {
+		if (bt_link_info->sco_exist) {
+			if (bt_link_info->hid_exist &&
+			    bt_link_info->pan_exist &&
+			    bt_link_info->a2dp_exist) {
+				if (bt_hs_on) {
+					BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+						"[BTCoex], Error!!! BT Profile = SCO + HID + A2DP + PAN(HS)\n");
+					BTC_TRACE(trace_buf);
+
+				} else {
+					BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+						"[BTCoex], BT Profile = SCO + HID + A2DP + PAN(EDR)==>PAN(EDR)+HID\n");
+					BTC_TRACE(trace_buf);
+					algorithm =
+						BT_8812A_1ANT_COEX_ALGO_PANEDR_HID;
+				}
+			}
+		}
+	}
+
+	return algorithm;
+}
+
+void halbtc8812a1ant_set_bt_auto_report(IN struct btc_coexist *btcoexist,
+					IN boolean enable_auto_report)
+{
+	u8			h2c_parameter[1] = {0};
+
+	h2c_parameter[0] = 0;
+
+	if (enable_auto_report)
+		h2c_parameter[0] |= BIT(0);
+
+	btcoexist->btc_fill_h2c(btcoexist, 0x68, 1, h2c_parameter);
+}
+
+void halbtc8812a1ant_bt_auto_report(IN struct btc_coexist *btcoexist,
+		    IN boolean force_exec, IN boolean enable_auto_report)
+{
+	coex_dm->cur_bt_auto_report = enable_auto_report;
+
+	if (!force_exec) {
+		if (coex_dm->pre_bt_auto_report == coex_dm->cur_bt_auto_report)
+			return;
+	}
+	halbtc8812a1ant_set_bt_auto_report(btcoexist,
+					   coex_dm->cur_bt_auto_report);
+
+	coex_dm->pre_bt_auto_report = coex_dm->cur_bt_auto_report;
+}
+
+/* to check */
+void halbtc8812a1ant_set_sw_penalty_tx_rate_adaptive(IN struct btc_coexist
+		*btcoexist, IN boolean low_penalty_ra)
+{
+	u8	tmp_u1;
+
+	tmp_u1 = btcoexist->btc_read_1byte(btcoexist, 0x4fd);
+	tmp_u1 |= BIT(0);
+	if (low_penalty_ra) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], Tx rate adaptive, set low penalty!!\n");
+		BTC_TRACE(trace_buf);
+		tmp_u1 &= ~BIT(2);
+	} else {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], Tx rate adaptive, set normal!!\n");
+		BTC_TRACE(trace_buf);
+		tmp_u1 |= BIT(2);
+	}
+
+	btcoexist->btc_write_1byte(btcoexist, 0x4fd, tmp_u1);
+}
+
+void halbtc8812a1ant_low_penalty_ra(IN struct btc_coexist *btcoexist,
+			    IN boolean force_exec, IN boolean low_penalty_ra)
+{
+	coex_dm->cur_low_penalty_ra = low_penalty_ra;
+
+	if (!force_exec) {
+		if (coex_dm->pre_low_penalty_ra == coex_dm->cur_low_penalty_ra)
+			return;
+	}
+	halbtc8812a1ant_set_sw_penalty_tx_rate_adaptive(btcoexist,
+			coex_dm->cur_low_penalty_ra);
+
+	coex_dm->pre_low_penalty_ra = coex_dm->cur_low_penalty_ra;
+}
+
+void halbtc8812a1ant_set_coex_table(IN struct btc_coexist *btcoexist,
+	    IN u32 val0x6c0, IN u32 val0x6c4, IN u32 val0x6c8, IN u8 val0x6cc)
+{
+	btcoexist->btc_write_4byte(btcoexist, 0x6c0, val0x6c0);
+
+	btcoexist->btc_write_4byte(btcoexist, 0x6c4, val0x6c4);
+
+	btcoexist->btc_write_4byte(btcoexist, 0x6c8, val0x6c8);
+
+	btcoexist->btc_write_1byte(btcoexist, 0x6cc, val0x6cc);
+}
+
+void halbtc8812a1ant_coex_table(IN struct btc_coexist *btcoexist,
+			IN boolean force_exec, IN u32 val0x6c0, IN u32 val0x6c4,
+				IN u32 val0x6c8, IN u8 val0x6cc)
+{
+	coex_dm->cur_val0x6c0 = val0x6c0;
+	coex_dm->cur_val0x6c4 = val0x6c4;
+	coex_dm->cur_val0x6c8 = val0x6c8;
+	coex_dm->cur_val0x6cc = val0x6cc;
+
+	if (!force_exec) {
+		if ((coex_dm->pre_val0x6c0 == coex_dm->cur_val0x6c0) &&
+		    (coex_dm->pre_val0x6c4 == coex_dm->cur_val0x6c4) &&
+		    (coex_dm->pre_val0x6c8 == coex_dm->cur_val0x6c8) &&
+		    (coex_dm->pre_val0x6cc == coex_dm->cur_val0x6cc))
+			return;
+	}
+	halbtc8812a1ant_set_coex_table(btcoexist, val0x6c0, val0x6c4, val0x6c8,
+				       val0x6cc);
+
+	coex_dm->pre_val0x6c0 = coex_dm->cur_val0x6c0;
+	coex_dm->pre_val0x6c4 = coex_dm->cur_val0x6c4;
+	coex_dm->pre_val0x6c8 = coex_dm->cur_val0x6c8;
+	coex_dm->pre_val0x6cc = coex_dm->cur_val0x6cc;
+}
+
+void halbtc8812a1ant_coex_table_with_type(IN struct btc_coexist *btcoexist,
+		IN boolean force_exec, IN u8 type)
+{
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+		    "[BTCoex], ********** CoexTable(%d) **********\n", type);
+	BTC_TRACE(trace_buf);
+
+	coex_sta->coex_table_type = type;
+
+	switch (type) {
+	case 0:
+		halbtc8812a1ant_coex_table(btcoexist, force_exec,
+				   0x55555555, 0x55555555, 0xffffff, 0x3);
+		break;
+	case 1:
+		halbtc8812a1ant_coex_table(btcoexist, force_exec,
+				   0x55555555, 0x5a5a5a5a, 0xffffff, 0x3);
+		break;
+	case 2:
+		halbtc8812a1ant_coex_table(btcoexist, force_exec,
+				   0x5a5a5a5a, 0x5a5a5a5a, 0xffffff, 0x3);
+		break;
+	case 3:
+		halbtc8812a1ant_coex_table(btcoexist, force_exec,
+				   0x55555555, 0x5a5a5a5a, 0xffffff, 0x3);
+		break;
+	case 4:
+		halbtc8812a1ant_coex_table(btcoexist, force_exec,
+				   0x55555555, 0xaaaa5a5a, 0xffffff, 0x3);
+		break;
+	case 5:
+		halbtc8812a1ant_coex_table(btcoexist, force_exec,
+				   0x5a5a5a5a, 0xaa5a5a5a, 0xffffff, 0x3);
+		break;
+	case 6:
+		halbtc8812a1ant_coex_table(btcoexist, force_exec,
+				   0x55555555, 0xaaaaaaaa, 0xffffff, 0x3);
+		break;
+	case 7:
+		halbtc8812a1ant_coex_table(btcoexist, force_exec,
+				   0xaaaaaaaa, 0xaaaaaaaa, 0xffffff, 0x3);
+		break;
+	default:
+		break;
+	}
+}
+
+void halbtc8812a1ant_set_fw_ignore_wlan_act(IN struct btc_coexist *btcoexist,
+		IN boolean enable)
+{
+	u8	data_len = 3;
+	u8	buf[5] = {0};
+
+	buf[0] = data_len;
+	buf[1] = 0x1;			/* OP_Code */
+	buf[2] = 0x1;			/* OP_Code_Length */
+	if (enable)
+		buf[3] = 0x1;		/* OP_Code_Content */
+	else
+		buf[3] = 0x0;
+
+	btcoexist->btc_set(btcoexist, BTC_SET_ACT_CTRL_BT_COEX,
+			   (void *)&buf[0]);
+}
+
+void halbtc8812a1ant_ignore_wlan_act(IN struct btc_coexist *btcoexist,
+				     IN boolean force_exec, IN boolean enable)
+{
+	coex_dm->cur_ignore_wlan_act = enable;
+
+	if (!force_exec) {
+		if (coex_dm->pre_ignore_wlan_act ==
+		    coex_dm->cur_ignore_wlan_act)
+			return;
+	}
+	halbtc8812a1ant_set_fw_ignore_wlan_act(btcoexist, enable);
+
+	coex_dm->pre_ignore_wlan_act = coex_dm->cur_ignore_wlan_act;
+}
+
+void halbtc8812a1ant_set_lps_rpwm(IN struct btc_coexist *btcoexist,
+				  IN u8 lps_val, IN u8 rpwm_val)
+{
+	u8	lps = lps_val;
+	u8	rpwm = rpwm_val;
+
+	btcoexist->btc_set(btcoexist, BTC_SET_U1_LPS_VAL, &lps);
+	btcoexist->btc_set(btcoexist, BTC_SET_U1_RPWM_VAL, &rpwm);
+}
+
+void halbtc8812a1ant_lps_rpwm(IN struct btc_coexist *btcoexist,
+		      IN boolean force_exec, IN u8 lps_val, IN u8 rpwm_val)
+{
+	coex_dm->cur_lps = lps_val;
+	coex_dm->cur_rpwm = rpwm_val;
+
+	if (!force_exec) {
+		if ((coex_dm->pre_lps == coex_dm->cur_lps) &&
+		    (coex_dm->pre_rpwm == coex_dm->cur_rpwm))
+			return;
+	}
+	halbtc8812a1ant_set_lps_rpwm(btcoexist, lps_val, rpwm_val);
+
+	coex_dm->pre_lps = coex_dm->cur_lps;
+	coex_dm->pre_rpwm = coex_dm->cur_rpwm;
+}
+
+void halbtc8812a1ant_sw_mechanism(IN struct btc_coexist *btcoexist,
+				  IN boolean low_penalty_ra)
+{
+	halbtc8812a1ant_low_penalty_ra(btcoexist, NORMAL_EXEC, low_penalty_ra);
+}
+
+/* to check force_exec */
+void halbtc8812a1ant_set_ant_path(IN struct btc_coexist *btcoexist,
+	  IN u8 ant_pos_type, IN boolean force_exec, IN boolean init_hwcfg,
+				  IN boolean wifi_off)
+{
+	u8			u8tmp = 0;
+
+	coex_dm->cur_ant_pos_type = ant_pos_type;
+
+	if (init_hwcfg) {
+		btcoexist->btc_write_1byte(btcoexist, 0xcb3, 0x77);
+		btcoexist->btc_write_4byte(btcoexist, 0x900, 0x00000400);
+		btcoexist->btc_write_1byte(btcoexist, 0x76d, 0x1);
+	} else if (wifi_off) {
+		btcoexist->btc_write_1byte(btcoexist, 0xcb3, 0x77);
+		u8tmp = btcoexist->btc_read_1byte(btcoexist, 0xcb7);
+		u8tmp &= ~BIT(3);
+		u8tmp |= BIT(2);
+		btcoexist->btc_write_1byte(btcoexist, 0xcb7, u8tmp);
+	}
+
+	if (force_exec ||
+	    (coex_dm->cur_ant_pos_type != coex_dm->pre_ant_pos_type)) {
+		/* ext switch setting */
+		switch (ant_pos_type) {
+		case BTC_ANT_PATH_WIFI:
+			u8tmp = btcoexist->btc_read_1byte(btcoexist,
+							  0xcb7);
+			u8tmp |= BIT(3);
+			u8tmp &= ~BIT(2);
+			btcoexist->btc_write_1byte(btcoexist, 0xcb7,
+						   u8tmp);
+			break;
+		case BTC_ANT_PATH_BT:
+			u8tmp = btcoexist->btc_read_1byte(btcoexist,
+							  0xcb7);
+			u8tmp &= ~BIT(3);
+			u8tmp |= BIT(2);
+			btcoexist->btc_write_1byte(btcoexist, 0xcb7,
+						   u8tmp);
+			break;
+		default:
+		case BTC_ANT_PATH_PTA:
+			u8tmp = btcoexist->btc_read_1byte(btcoexist,
+							  0xcb7);
+			u8tmp |= BIT(3);
+			u8tmp &= ~BIT(2);
+			btcoexist->btc_write_1byte(btcoexist, 0xcb7,
+						   u8tmp);
+			break;
+		}
+	}
+
+	coex_dm->pre_ant_pos_type = coex_dm->cur_ant_pos_type;
+}
+
+void halbtc8812a1ant_set_fw_pstdma(IN struct btc_coexist *btcoexist,
+	   IN u8 byte1, IN u8 byte2, IN u8 byte3, IN u8 byte4, IN u8 byte5)
+{
+	u8			h2c_parameter[5] = {0};
+	u8			real_byte1 = byte1, real_byte5 = byte5;
+	boolean			ap_enable = false;
+
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_AP_MODE_ENABLE,
+			   &ap_enable);
+
+	if (ap_enable) {
+		if (byte1 & BIT(4) && !(byte1 & BIT(5))) {
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				    "[BTCoex], FW for 1Ant AP mode\n");
+			BTC_TRACE(trace_buf);
+			real_byte1 &= ~BIT(4);
+			real_byte1 |= BIT(5);
+
+			real_byte5 |= BIT(5);
+			real_byte5 &= ~BIT(6);
+		}
+	}
+
+	h2c_parameter[0] = real_byte1;
+	h2c_parameter[1] = byte2;
+	h2c_parameter[2] = byte3;
+	h2c_parameter[3] = byte4;
+	h2c_parameter[4] = real_byte5;
+
+	coex_dm->ps_tdma_para[0] = real_byte1;
+	coex_dm->ps_tdma_para[1] = byte2;
+	coex_dm->ps_tdma_para[2] = byte3;
+	coex_dm->ps_tdma_para[3] = byte4;
+	coex_dm->ps_tdma_para[4] = real_byte5;
+
+	btcoexist->btc_fill_h2c(btcoexist, 0x60, 5, h2c_parameter);
+}
+
+
+void halbtc8812a1ant_ps_tdma(IN struct btc_coexist *btcoexist,
+		     IN boolean force_exec, IN boolean turn_on, IN u8 type)
+{
+	struct  btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
+	boolean			wifi_busy = false;
+	u8			rssi_adjust_val = 0;
+	u8			ps_tdma_byte4_val = 0x50, ps_tdma_byte0_val = 0x51,
+				ps_tdma_byte3_val =  0x10;
+	s8			wifi_duration_adjust = 0x0;
+	static boolean	 pre_wifi_busy = false;
+
+	coex_dm->cur_ps_tdma_on = turn_on;
+	coex_dm->cur_ps_tdma = type;
+
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy);
+
+	if (wifi_busy != pre_wifi_busy) {
+		force_exec = true;
+		pre_wifi_busy = wifi_busy;
+	}
+
+	if (coex_dm->cur_ps_tdma_on) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], ********** TDMA(on, %d) **********\n",
+			    coex_dm->cur_ps_tdma);
+		BTC_TRACE(trace_buf);
+	} else {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], ********** TDMA(off, %d) **********\n",
+			    coex_dm->cur_ps_tdma);
+		BTC_TRACE(trace_buf);
+	}
+
+	if (!force_exec) {
+		if ((coex_dm->pre_ps_tdma_on == coex_dm->cur_ps_tdma_on) &&
+		    (coex_dm->pre_ps_tdma == coex_dm->cur_ps_tdma))
+			return;
+	}
+
+	if (coex_sta->scan_ap_num <= 5)
+		wifi_duration_adjust = 2;
+	else if (coex_sta->scan_ap_num >= 40)
+		wifi_duration_adjust = -15;
+	else if (coex_sta->scan_ap_num >= 20)
+		wifi_duration_adjust = -10;
+
+	if (!coex_sta->force_lps_on) { /* only for A2DP-only case 1/2/9/11 while wifi noisy threshold > 30 */
+		ps_tdma_byte0_val = 0x61;  /* no null-pkt */
+		ps_tdma_byte3_val = 0x11; /* no tx-pause at BT-slot */
+		ps_tdma_byte4_val = 0x10; /* 0x778 = d/1 toggle */
+	}
+
+	if ((type == 3) || (type == 13) || (type == 14)) {
+		ps_tdma_byte4_val = ps_tdma_byte4_val &
+			    0xbf;  /* no dynamic slot for multi-profile */
+
+		if (!wifi_busy)
+			ps_tdma_byte4_val = ps_tdma_byte4_val |
+				0x1;  /* 0x778 = 0x1 at wifi slot (no blocking BT Low-Pri pkts) */
+	}
+
+	if (bt_link_info->slave_role == true)
+		ps_tdma_byte4_val = ps_tdma_byte4_val |
+			0x1;  /* 0x778 = 0x1 at wifi slot (no blocking BT Low-Pri pkts) */
+
+	if (turn_on) {
+		switch (type) {
+		default:
+			halbtc8812a1ant_set_fw_pstdma(btcoexist, 0x51,
+				      0x1a, 0x1a, 0x0, ps_tdma_byte4_val);
+			break;
+		case 1:
+			halbtc8812a1ant_set_fw_pstdma(btcoexist,
+						      ps_tdma_byte0_val, 0x3a +
+					      wifi_duration_adjust, 0x03,
+				      ps_tdma_byte3_val, ps_tdma_byte4_val);
+			break;
+		case 2:
+			halbtc8812a1ant_set_fw_pstdma(btcoexist,
+						      ps_tdma_byte0_val, 0x2d +
+					      wifi_duration_adjust, 0x03,
+				      ps_tdma_byte3_val, ps_tdma_byte4_val);
+			break;
+		case 3:
+			halbtc8812a1ant_set_fw_pstdma(btcoexist, 0x51,
+				      0x1d, 0x1d, 0x0, ps_tdma_byte4_val);
+			break;
+		case 4:
+			halbtc8812a1ant_set_fw_pstdma(btcoexist, 0x93,
+						      0x15, 0x3, 0x14, 0x0);
+			break;
+		case 5:
+			halbtc8812a1ant_set_fw_pstdma(btcoexist, 0x61,
+						      0x15, 0x3, 0x11, 0x11);
+			break;
+		case 6:
+			halbtc8812a1ant_set_fw_pstdma(btcoexist, 0x61,
+						      0x20, 0x3, 0x11, 0x11);
+			break;
+		case 7:
+			halbtc8812a1ant_set_fw_pstdma(btcoexist, 0x13,
+						      0xc, 0x5, 0x0, 0x0);
+			break;
+		case 8:
+			halbtc8812a1ant_set_fw_pstdma(btcoexist, 0x93,
+						      0x25, 0x3, 0x10, 0x0);
+			break;
+		case 9:
+			halbtc8812a1ant_set_fw_pstdma(btcoexist,
+					      ps_tdma_byte0_val, 0x21, 0x3,
+				      ps_tdma_byte3_val, ps_tdma_byte4_val);
+			break;
+		case 10:
+			halbtc8812a1ant_set_fw_pstdma(btcoexist, 0x13,
+						      0xa, 0xa, 0x0, 0x40);
+			break;
+		case 11:
+			halbtc8812a1ant_set_fw_pstdma(btcoexist,
+					      ps_tdma_byte0_val, 0x21, 0x03,
+				      ps_tdma_byte3_val, ps_tdma_byte4_val);
+			break;
+		case 12:
+			halbtc8812a1ant_set_fw_pstdma(btcoexist, 0x51,
+						      0x0a, 0x0a, 0x0, 0x50);
+			break;
+		case 13:
+			halbtc8812a1ant_set_fw_pstdma(btcoexist, 0x51,
+				      0x12, 0x12, 0x0, ps_tdma_byte4_val);
+			break;
+		case 14:
+			halbtc8812a1ant_set_fw_pstdma(btcoexist, 0x51,
+				      0x21, 0x3, 0x10, ps_tdma_byte4_val);
+			break;
+		case 15:
+			halbtc8812a1ant_set_fw_pstdma(btcoexist, 0x13,
+						      0xa, 0x3, 0x8, 0x0);
+			break;
+		case 16:
+			halbtc8812a1ant_set_fw_pstdma(btcoexist, 0x93,
+						      0x15, 0x3, 0x10, 0x0);
+			break;
+		case 18:
+			halbtc8812a1ant_set_fw_pstdma(btcoexist, 0x93,
+						      0x25, 0x3, 0x10, 0x0);
+			break;
+		case 20:
+			halbtc8812a1ant_set_fw_pstdma(btcoexist, 0x61,
+						      0x3f, 0x03, 0x11, 0x10);
+			break;
+		case 21:
+			halbtc8812a1ant_set_fw_pstdma(btcoexist, 0x61,
+						      0x25, 0x03, 0x11, 0x11);
+			break;
+		case 22:
+			halbtc8812a1ant_set_fw_pstdma(btcoexist, 0x61,
+						      0x25, 0x03, 0x11, 0x10);
+			break;
+		case 23:
+			halbtc8812a1ant_set_fw_pstdma(btcoexist, 0xe3,
+						      0x25, 0x3, 0x31, 0x18);
+			break;
+		case 24:
+			halbtc8812a1ant_set_fw_pstdma(btcoexist, 0xe3,
+						      0x15, 0x3, 0x31, 0x18);
+			break;
+		case 25:
+			halbtc8812a1ant_set_fw_pstdma(btcoexist, 0xe3,
+						      0xa, 0x3, 0x31, 0x18);
+			break;
+		case 26:
+			halbtc8812a1ant_set_fw_pstdma(btcoexist, 0xe3,
+						      0xa, 0x3, 0x31, 0x18);
+			break;
+		case 27:
+			halbtc8812a1ant_set_fw_pstdma(btcoexist, 0xe3,
+						      0x25, 0x3, 0x31, 0x98);
+			break;
+		case 28:
+			halbtc8812a1ant_set_fw_pstdma(btcoexist, 0x69,
+						      0x25, 0x3, 0x31, 0x0);
+			break;
+		case 29:
+			halbtc8812a1ant_set_fw_pstdma(btcoexist, 0xab,
+						      0x1a, 0x1a, 0x1, 0x10);
+			break;
+		case 30:
+			halbtc8812a1ant_set_fw_pstdma(btcoexist, 0x51,
+						      0x30, 0x3, 0x10, 0x10);
+			break;
+		case 31:
+			halbtc8812a1ant_set_fw_pstdma(btcoexist, 0xd3,
+						      0x1a, 0x1a, 0, 0x58);
+			break;
+		case 32:
+			halbtc8812a1ant_set_fw_pstdma(btcoexist, 0x61,
+						      0x35, 0x3, 0x11, 0x11);
+			break;
+		case 33:
+			halbtc8812a1ant_set_fw_pstdma(btcoexist, 0xa3,
+						      0x25, 0x3, 0x30, 0x90);
+			break;
+		case 34:
+			halbtc8812a1ant_set_fw_pstdma(btcoexist, 0x53,
+						      0x1a, 0x1a, 0x0, 0x10);
+			break;
+		case 35:
+			halbtc8812a1ant_set_fw_pstdma(btcoexist, 0x63,
+						      0x1a, 0x1a, 0x0, 0x10);
+			break;
+		case 36:
+			halbtc8812a1ant_set_fw_pstdma(btcoexist, 0xd3,
+						      0x12, 0x3, 0x14, 0x50);
+			break;
+		case 40: /* SoftAP only with no sta associated,BT disable ,TDMA mode for power saving */
+			/* here softap mode screen off will cost 70-80mA for phone */
+			halbtc8812a1ant_set_fw_pstdma(btcoexist, 0x23,
+						      0x18, 0x00, 0x10, 0x24);
+			break;
+		}
+	} else {
+
+		/* disable PS tdma */
+		switch (type) {
+		case 8: /* PTA Control */
+			halbtc8812a1ant_set_fw_pstdma(btcoexist, 0x8,
+						      0x0, 0x0, 0x0, 0x0);
+			break;
+		case 0:
+		default:  /* Software control, Antenna at BT side */
+			halbtc8812a1ant_set_fw_pstdma(btcoexist, 0x0,
+						      0x0, 0x0, 0x0, 0x0);
+			break;
+		}
+	}
+	rssi_adjust_val = 0;
+	btcoexist->btc_set(btcoexist,
+		BTC_SET_U1_RSSI_ADJ_VAL_FOR_1ANT_COEX_TYPE, &rssi_adjust_val);
+
+
+	/* update pre state */
+	coex_dm->pre_ps_tdma_on = coex_dm->cur_ps_tdma_on;
+	coex_dm->pre_ps_tdma = coex_dm->cur_ps_tdma;
+}
+
+boolean halbtc8812a1ant_is_common_action(IN struct btc_coexist *btcoexist)
+{
+	boolean			common = false, wifi_connected = false, wifi_busy = false;
+
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED,
+			   &wifi_connected);
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy);
+
+	if (!wifi_connected &&
+	    BT_8812A_1ANT_BT_STATUS_NON_CONNECTED_IDLE ==
+	    coex_dm->bt_status) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			"[BTCoex], Wifi non connected-idle + BT non connected-idle!!\n");
+		BTC_TRACE(trace_buf);
+
+		/* halbtc8812a1ant_sw_mechanism(btcoexist, false); */
+
+		common = true;
+	} else if (wifi_connected &&
+		   (BT_8812A_1ANT_BT_STATUS_NON_CONNECTED_IDLE ==
+		    coex_dm->bt_status)) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			"[BTCoex], Wifi connected + BT non connected-idle!!\n");
+		BTC_TRACE(trace_buf);
+
+		/* halbtc8812a1ant_sw_mechanism(btcoexist, false); */
+
+		common = true;
+	} else if (!wifi_connected &&
+		(BT_8812A_1ANT_BT_STATUS_CONNECTED_IDLE == coex_dm->bt_status)) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			"[BTCoex], Wifi non connected-idle + BT connected-idle!!\n");
+		BTC_TRACE(trace_buf);
+
+		/* halbtc8812a1ant_sw_mechanism(btcoexist, false); */
+
+		common = true;
+	} else if (wifi_connected &&
+		(BT_8812A_1ANT_BT_STATUS_CONNECTED_IDLE == coex_dm->bt_status)) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], Wifi connected + BT connected-idle!!\n");
+		BTC_TRACE(trace_buf);
+
+		/* halbtc8812a1ant_sw_mechanism(btcoexist, false); */
+
+		common = true;
+	} else if (!wifi_connected &&
+		(BT_8812A_1ANT_BT_STATUS_CONNECTED_IDLE != coex_dm->bt_status)) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], Wifi non connected-idle + BT Busy!!\n");
+		BTC_TRACE(trace_buf);
+
+		/* halbtc8812a1ant_sw_mechanism(btcoexist, false); */
+
+		common = true;
+	} else {
+		if (wifi_busy) {
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				"[BTCoex], Wifi Connected-Busy + BT Busy!!\n");
+			BTC_TRACE(trace_buf);
+		} else {
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				"[BTCoex], Wifi Connected-Idle + BT Busy!!\n");
+			BTC_TRACE(trace_buf);
+		}
+
+		common = false;
+	}
+
+	return common;
+}
+
+
+void halbtc8812a1ant_tdma_duration_adjust_for_acl(IN struct btc_coexist
+		*btcoexist, IN u8 wifi_status)
+{
+	static s32		up, dn, m, n, wait_count;
+	s32			result;   /* 0: no change, +1: increase WiFi duration, -1: decrease WiFi duration */
+	u8			retry_count = 0, bt_info_ext;
+	boolean			wifi_busy = false;
+
+	if (BT_8812A_1ANT_WIFI_STATUS_CONNECTED_BUSY == wifi_status)
+		wifi_busy = true;
+	else
+		wifi_busy = false;
+
+	if ((BT_8812A_1ANT_WIFI_STATUS_NON_CONNECTED_ASSO_AUTH_SCAN ==
+	     wifi_status) ||
+	    (BT_8812A_1ANT_WIFI_STATUS_CONNECTED_SCAN == wifi_status) ||
+	    (BT_8812A_1ANT_WIFI_STATUS_CONNECTED_SPECIFIC_PKT ==
+	     wifi_status)) {
+		if (coex_dm->cur_ps_tdma != 1 &&
+		    coex_dm->cur_ps_tdma != 2 &&
+		    coex_dm->cur_ps_tdma != 3 &&
+		    coex_dm->cur_ps_tdma != 9) {
+			halbtc8812a1ant_ps_tdma(btcoexist, NORMAL_EXEC, true,
+						9);
+			coex_dm->ps_tdma_du_adj_type = 9;
+
+			up = 0;
+			dn = 0;
+			m = 1;
+			n = 3;
+			result = 0;
+			wait_count = 0;
+		}
+		return;
+	}
+
+	if (!coex_dm->auto_tdma_adjust) {
+		coex_dm->auto_tdma_adjust = true;
+
+		halbtc8812a1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 2);
+		coex_dm->ps_tdma_du_adj_type = 2;
+		/* ============ */
+		up = 0;
+		dn = 0;
+		m = 1;
+		n = 3;
+		result = 0;
+		wait_count = 0;
+	} else {
+		/* acquire the BT TRx retry count from BT_Info byte2 */
+		retry_count = coex_sta->bt_retry_cnt;
+		bt_info_ext = coex_sta->bt_info_ext;
+
+		if ((coex_sta->low_priority_tx) > 1150 ||
+		    (coex_sta->low_priority_rx) > 1250)
+			retry_count++;
+
+		result = 0;
+		wait_count++;
+
+		if (retry_count ==
+		    0) { /* no retry in the last 2-second duration */
+			up++;
+			dn--;
+
+			if (dn <= 0)
+				dn = 0;
+
+			if (up >= n) {	/* if retry count during continuous n*2 seconds is 0, enlarge WiFi duration */
+				wait_count = 0;
+				n = 3;
+				up = 0;
+				dn = 0;
+				result = 1;
+			}
+		} else if (retry_count <=
+			   3) {	/* <=3 retry in the last 2-second duration */
+			up--;
+			dn++;
+
+			if (up <= 0)
+				up = 0;
+
+			if (dn == 2) {	/* if continuous 2 retry count(every 2 seconds) >0 and < 3, reduce WiFi duration */
+				if (wait_count <= 2)
+					m++; /* to avoid loop between the two levels */
+				else
+					m = 1;
+
+				if (m >= 20)  /* maximum of m = 20 ' will recheck if need to adjust wifi duration in maximum time interval 120 seconds */
+					m = 20;
+
+				n = 3 * m;
+				up = 0;
+				dn = 0;
+				wait_count = 0;
+				result = -1;
+			}
+		} else { /* retry count > 3, once retry count > 3, to reduce WiFi duration */
+			if (wait_count == 1)
+				m++; /* to avoid loop between the two levels */
+			else
+				m = 1;
+
+			if (m >= 20)  /* maximum of m = 20 ' will recheck if need to adjust wifi duration in maximum time interval 120 seconds */
+				m = 20;
+
+			n = 3 * m;
+			up = 0;
+			dn = 0;
+			wait_count = 0;
+			result = -1;
+		}
+
+		if (result == -1) {
+			if ((BT_INFO_8812A_1ANT_A2DP_BASIC_RATE(bt_info_ext)) &&
+			    ((coex_dm->cur_ps_tdma == 1) ||
+			     (coex_dm->cur_ps_tdma == 2))) {
+				halbtc8812a1ant_ps_tdma(btcoexist, NORMAL_EXEC,
+							true, 9);
+				coex_dm->ps_tdma_du_adj_type = 9;
+			} else if (coex_dm->cur_ps_tdma == 1) {
+				halbtc8812a1ant_ps_tdma(btcoexist, NORMAL_EXEC,
+							true, 2);
+				coex_dm->ps_tdma_du_adj_type = 2;
+			} else if (coex_dm->cur_ps_tdma == 2) {
+				halbtc8812a1ant_ps_tdma(btcoexist, NORMAL_EXEC,
+							true, 9);
+				coex_dm->ps_tdma_du_adj_type = 9;
+			} else if (coex_dm->cur_ps_tdma == 9) {
+				halbtc8812a1ant_ps_tdma(btcoexist, NORMAL_EXEC,
+							true, 11);
+				coex_dm->ps_tdma_du_adj_type = 11;
+			}
+		} else if (result == 1) {
+			if ((BT_INFO_8812A_1ANT_A2DP_BASIC_RATE(bt_info_ext)) &&
+			    ((coex_dm->cur_ps_tdma == 1) ||
+			     (coex_dm->cur_ps_tdma == 2))) {
+				halbtc8812a1ant_ps_tdma(btcoexist, NORMAL_EXEC,
+							true, 9);
+				coex_dm->ps_tdma_du_adj_type = 9;
+			} else if (coex_dm->cur_ps_tdma == 11) {
+				halbtc8812a1ant_ps_tdma(btcoexist, NORMAL_EXEC,
+							true, 9);
+				coex_dm->ps_tdma_du_adj_type = 9;
+			} else if (coex_dm->cur_ps_tdma == 9) {
+				halbtc8812a1ant_ps_tdma(btcoexist, NORMAL_EXEC,
+							true, 2);
+				coex_dm->ps_tdma_du_adj_type = 2;
+			} else if (coex_dm->cur_ps_tdma == 2) {
+				halbtc8812a1ant_ps_tdma(btcoexist, NORMAL_EXEC,
+							true, 1);
+				coex_dm->ps_tdma_du_adj_type = 1;
+			}
+		} else { /* no change */
+			/* Bryant Modify
+			if(wifi_busy != pre_wifi_busy)
+			{
+				pre_wifi_busy = wifi_busy;
+				halbtc8812a1ant_ps_tdma(btcoexist, FORCE_EXEC, true, coex_dm->cur_ps_tdma);
+			}
+			*/
+
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				"[BTCoex], ********** TDMA(on, %d) **********\n",
+				    coex_dm->cur_ps_tdma);
+			BTC_TRACE(trace_buf);
+		}
+
+		if (coex_dm->cur_ps_tdma != 1 &&
+		    coex_dm->cur_ps_tdma != 2 &&
+		    coex_dm->cur_ps_tdma != 9 &&
+		    coex_dm->cur_ps_tdma != 11) {
+			/* recover to previous adjust type */
+			halbtc8812a1ant_ps_tdma(btcoexist, NORMAL_EXEC, true,
+						coex_dm->ps_tdma_du_adj_type);
+		}
+	}
+}
+
+void halbtc8812a1ant_ps_tdma_check_for_power_save_state(
+	IN struct btc_coexist *btcoexist, IN boolean new_ps_state)
+{
+	u8	lps_mode = 0x0;
+
+	btcoexist->btc_get(btcoexist, BTC_GET_U1_LPS_MODE, &lps_mode);
+
+	if (lps_mode) {	/* already under LPS state */
+		if (new_ps_state) {
+			/* keep state under LPS, do nothing. */
+		} else {
+			/* will leave LPS state, turn off psTdma first */
+			halbtc8812a1ant_ps_tdma(btcoexist, NORMAL_EXEC, false,
+						8);
+		}
+	} else {					/* NO PS state */
+		if (new_ps_state) {
+			/* will enter LPS state, turn off psTdma first */
+			halbtc8812a1ant_ps_tdma(btcoexist, NORMAL_EXEC, false,
+						8);
+		} else {
+			/* keep state under NO PS state, do nothing. */
+		}
+	}
+}
+
+void halbtc8812a1ant_power_save_state(IN struct btc_coexist *btcoexist,
+			      IN u8 ps_type, IN u8 lps_val, IN u8 rpwm_val)
+{
+	boolean		low_pwr_disable = false;
+
+	switch (ps_type) {
+	case BTC_PS_WIFI_NATIVE:
+		/* recover to original 32k low power setting */
+		low_pwr_disable = false;
+		btcoexist->btc_set(btcoexist,
+				   BTC_SET_ACT_DISABLE_LOW_POWER,
+				   &low_pwr_disable);
+		btcoexist->btc_set(btcoexist, BTC_SET_ACT_NORMAL_LPS,
+				   NULL);
+		coex_sta->force_lps_on = false;
+		break;
+	case BTC_PS_LPS_ON:
+		halbtc8812a1ant_ps_tdma_check_for_power_save_state(
+			btcoexist, true);
+		halbtc8812a1ant_lps_rpwm(btcoexist, NORMAL_EXEC,
+					 lps_val, rpwm_val);
+		/* when coex force to enter LPS, do not enter 32k low power. */
+		low_pwr_disable = true;
+		btcoexist->btc_set(btcoexist,
+				   BTC_SET_ACT_DISABLE_LOW_POWER,
+				   &low_pwr_disable);
+		/* power save must executed before psTdma.			 */
+		btcoexist->btc_set(btcoexist, BTC_SET_ACT_ENTER_LPS,
+				   NULL);
+		coex_sta->force_lps_on = true;
+		break;
+	case BTC_PS_LPS_OFF:
+		halbtc8812a1ant_ps_tdma_check_for_power_save_state(
+			btcoexist, false);
+		btcoexist->btc_set(btcoexist, BTC_SET_ACT_LEAVE_LPS,
+				   NULL);
+		coex_sta->force_lps_on = false;
+		break;
+	default:
+		break;
+	}
+}
+
+void halbtc8812a1ant_action_wifi_only(IN struct btc_coexist *btcoexist)
+{
+	halbtc8812a1ant_coex_table_with_type(btcoexist, FORCE_EXEC, 0);
+	halbtc8812a1ant_ps_tdma(btcoexist, FORCE_EXEC, false, 8);
+	halbtc8812a1ant_set_ant_path(btcoexist, BTC_ANT_PATH_PTA, FORCE_EXEC,
+				     false, false);
+}
+
+void halbtc8812a1ant_monitor_bt_enable_disable(IN struct btc_coexist *btcoexist)
+{
+	static u32		bt_disable_cnt = 0;
+	boolean			bt_active = true, bt_disabled = false;
+
+	/* This function check if bt is disabled */
+
+	if (coex_sta->high_priority_tx == 0 &&
+	    coex_sta->high_priority_rx == 0 &&
+	    coex_sta->low_priority_tx == 0 &&
+	    coex_sta->low_priority_rx == 0)
+		bt_active = false;
+	if (coex_sta->high_priority_tx == 0xffff &&
+	    coex_sta->high_priority_rx == 0xffff &&
+	    coex_sta->low_priority_tx == 0xffff &&
+	    coex_sta->low_priority_rx == 0xffff)
+		bt_active = false;
+	if (bt_active) {
+		bt_disable_cnt = 0;
+		bt_disabled = false;
+		btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_DISABLE,
+				   &bt_disabled);
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], BT is enabled !!\n");
+		BTC_TRACE(trace_buf);
+	} else {
+		bt_disable_cnt++;
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], bt all counters=0, %d times!!\n",
+			    bt_disable_cnt);
+		BTC_TRACE(trace_buf);
+		if (bt_disable_cnt >= 2) {
+			bt_disabled = true;
+			btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_DISABLE,
+					   &bt_disabled);
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				    "[BTCoex], BT is disabled !!\n");
+			BTC_TRACE(trace_buf);
+			halbtc8812a1ant_action_wifi_only(btcoexist);
+		}
+	}
+	if (coex_sta->bt_disabled != bt_disabled) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], BT is from %s to %s!!\n",
+			    (coex_sta->bt_disabled ? "disabled" : "enabled"),
+			    (bt_disabled ? "disabled" : "enabled"));
+		BTC_TRACE(trace_buf);
+		coex_sta->bt_disabled = bt_disabled;
+		if (!bt_disabled) {
+		} else {
+			btcoexist->btc_set(btcoexist, BTC_SET_ACT_LEAVE_LPS,
+					   NULL);
+			btcoexist->btc_set(btcoexist, BTC_SET_ACT_NORMAL_LPS,
+					   NULL);
+		}
+	}
+}
+
+/* *********************************************
+ *
+ *	Software Coex Mechanism start
+ *
+ * ********************************************* */
+
+/* SCO only or SCO+PAN(HS) */
+
+/*
+void halbtc8812a1ant_action_sco(IN struct btc_coexist* btcoexist)
+{
+	halbtc8812a1ant_sw_mechanism(btcoexist, true);
+}
+
+
+void halbtc8812a1ant_action_hid(IN struct btc_coexist* btcoexist)
+{
+	halbtc8812a1ant_sw_mechanism(btcoexist, true);
+}
+
+
+void halbtc8812a1ant_action_a2dp(IN struct btc_coexist* btcoexist)
+{
+	halbtc8812a1ant_sw_mechanism(btcoexist, false);
+}
+
+void halbtc8812a1ant_action_a2dp_pan_hs(IN struct btc_coexist* btcoexist)
+{
+	halbtc8812a1ant_sw_mechanism(btcoexist, false);
+}
+
+void halbtc8812a1ant_action_pan_edr(IN struct btc_coexist* btcoexist)
+{
+	halbtc8812a1ant_sw_mechanism(btcoexist, false);
+}
+
+
+void halbtc8812a1ant_action_pan_hs(IN struct btc_coexist* btcoexist)
+{
+	halbtc8812a1ant_sw_mechanism(btcoexist, false);
+}
+
+
+void halbtc8812a1ant_action_pan_edr_a2dp(IN struct btc_coexist* btcoexist)
+{
+	halbtc8812a1ant_sw_mechanism(btcoexist, false);
+}
+
+void halbtc8812a1ant_action_pan_edr_hid(IN struct btc_coexist* btcoexist)
+{
+	halbtc8812a1ant_sw_mechanism(btcoexist, true);
+}
+
+
+void halbtc8812a1ant_action_hid_a2dp_pan_edr(IN struct btc_coexist* btcoexist)
+{
+	halbtc8812a1ant_sw_mechanism(btcoexist, true);
+}
+
+void halbtc8812a1ant_action_hid_a2dp(IN struct btc_coexist* btcoexist)
+{
+	halbtc8812a1ant_sw_mechanism(btcoexist, true);
+}
+
+*/
+
+/* *********************************************
+ *
+ *	Non-Software Coex Mechanism start
+ *
+ * ********************************************* */
+void halbtc8812a1ant_action_wifi_multi_port(IN struct btc_coexist *btcoexist)
+{
+	halbtc8812a1ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, 0x0,
+					 0x0);
+
+	halbtc8812a1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 8);
+	halbtc8812a1ant_set_ant_path(btcoexist, BTC_ANT_PATH_PTA, NORMAL_EXEC,
+				     false, false);
+	halbtc8812a1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 2);
+}
+
+void halbtc8812a1ant_action_hs(IN struct btc_coexist *btcoexist)
+{
+	halbtc8812a1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 5);
+	halbtc8812a1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 2);
+}
+
+void halbtc8812a1ant_action_bt_inquiry(IN struct btc_coexist *btcoexist)
+{
+	struct  btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
+	boolean			wifi_connected = false, ap_enable = false, wifi_busy = false,
+				bt_busy = false;
+
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_AP_MODE_ENABLE,
+			   &ap_enable);
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED,
+			   &wifi_connected);
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy);
+	btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_TRAFFIC_BUSY, &bt_busy);
+
+	if ((!wifi_connected) && (!coex_sta->wifi_is_high_pri_task)) {
+		halbtc8812a1ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE,
+						 0x0, 0x0);
+		halbtc8812a1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 8);
+		halbtc8812a1ant_set_ant_path(btcoexist, BTC_ANT_PATH_PTA,
+					     NORMAL_EXEC, false, false);
+		halbtc8812a1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0);
+	} else if ((bt_link_info->sco_exist) || (bt_link_info->hid_exist) ||
+		   (bt_link_info->a2dp_exist)) {
+		/* SCO/HID/A2DP  busy */
+		halbtc8812a1ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE,
+						 0x0, 0x0);
+		halbtc8812a1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 32);
+
+		halbtc8812a1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4);
+	} else if ((bt_link_info->pan_exist) || (wifi_busy)) {
+		halbtc8812a1ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE,
+						 0x0, 0x0);
+		halbtc8812a1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 20);
+
+		halbtc8812a1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4);
+	} else {
+		halbtc8812a1ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE,
+						 0x0, 0x0);
+		halbtc8812a1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 8);
+		halbtc8812a1ant_set_ant_path(btcoexist, BTC_ANT_PATH_PTA,
+					     NORMAL_EXEC, false, false);
+		halbtc8812a1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 7);
+	}
+}
+
+void halbtc8812a1ant_action_bt_sco_hid_only_busy(IN struct btc_coexist
+		*btcoexist, IN u8 wifi_status)
+{
+	struct  btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
+	boolean	wifi_connected = false;
+
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED,
+			   &wifi_connected);
+
+	/* tdma and coex table */
+
+	if (bt_link_info->sco_exist) {
+		halbtc8812a1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 5);
+		halbtc8812a1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 5);
+	} else { /* HID */
+		halbtc8812a1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 6);
+		halbtc8812a1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 5);
+	}
+}
+
+void halbtc8812a1ant_action_wifi_connected_bt_acl_busy(IN struct btc_coexist
+		*btcoexist, IN u8 wifi_status)
+{
+	u8		bt_rssi_state;
+
+	struct  btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
+
+	bt_rssi_state = halbtc8812a1ant_bt_rssi_state(2, 28, 0);
+
+	if ((coex_sta->low_priority_rx >= 950)  && (!coex_sta->under_ips))
+		bt_link_info->slave_role = true;
+	else
+		bt_link_info->slave_role = false;
+
+	if (bt_link_info->hid_only) { /* HID */
+		halbtc8812a1ant_action_bt_sco_hid_only_busy(btcoexist,
+				wifi_status);
+		coex_dm->auto_tdma_adjust = false;
+		return;
+	} else if (bt_link_info->a2dp_only) { /* A2DP		 */
+		if (BT_8812A_1ANT_WIFI_STATUS_CONNECTED_IDLE == wifi_status) {
+			halbtc8812a1ant_ps_tdma(btcoexist, NORMAL_EXEC, true,
+						32);
+			halbtc8812a1ant_coex_table_with_type(btcoexist,
+							     NORMAL_EXEC, 4);
+			coex_dm->auto_tdma_adjust = false;
+		} else {
+			halbtc8812a1ant_tdma_duration_adjust_for_acl(btcoexist,
+					wifi_status);
+			halbtc8812a1ant_coex_table_with_type(btcoexist,
+							     NORMAL_EXEC, 4);
+			coex_dm->auto_tdma_adjust = true;
+		}
+	} else if (((bt_link_info->a2dp_exist) && (bt_link_info->pan_exist)) ||
+		   (bt_link_info->hid_exist && bt_link_info->a2dp_exist &&
+		bt_link_info->pan_exist)) { /* A2DP+PAN(OPP,FTP), HID+A2DP+PAN(OPP,FTP) */
+		halbtc8812a1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 13);
+		halbtc8812a1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4);
+		coex_dm->auto_tdma_adjust = false;
+	} else if (bt_link_info->hid_exist &&
+		   bt_link_info->a2dp_exist) { /* HID+A2DP */
+		halbtc8812a1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 14);
+		coex_dm->auto_tdma_adjust = false;
+
+		halbtc8812a1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 3);
+	} else if ((bt_link_info->pan_only) || (bt_link_info->hid_exist &&
+		bt_link_info->pan_exist)) { /* PAN(OPP,FTP), HID+PAN(OPP,FTP)			 */
+		halbtc8812a1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 3);
+		halbtc8812a1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4);
+		coex_dm->auto_tdma_adjust = false;
+	} else {
+		/* BT no-profile busy (0x9) */
+		halbtc8812a1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 32);
+		halbtc8812a1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4);
+		coex_dm->auto_tdma_adjust = false;
+	}
+}
+
+void halbtc8812a1ant_action_wifi_not_connected(IN struct btc_coexist *btcoexist)
+{
+	/* power save state */
+	halbtc8812a1ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, 0x0,
+					 0x0);
+
+	/* tdma and coex table */
+	halbtc8812a1ant_ps_tdma(btcoexist, FORCE_EXEC, false, 8);
+	halbtc8812a1ant_set_ant_path(btcoexist, BTC_ANT_PATH_PTA, NORMAL_EXEC,
+				     false, false);
+	halbtc8812a1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0);
+}
+
+void halbtc8812a1ant_action_wifi_not_connected_scan(IN struct btc_coexist
+		*btcoexist)
+{
+	struct  btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
+
+	halbtc8812a1ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, 0x0,
+					 0x0);
+
+	/* tdma and coex table */
+	if (BT_8812A_1ANT_BT_STATUS_ACL_BUSY == coex_dm->bt_status) {
+		if (bt_link_info->a2dp_exist) {
+			halbtc8812a1ant_ps_tdma(btcoexist, NORMAL_EXEC, true,
+						32);
+			halbtc8812a1ant_coex_table_with_type(btcoexist,
+							     NORMAL_EXEC, 4);
+		} else if (bt_link_info->a2dp_exist &&
+			   bt_link_info->pan_exist) {
+			halbtc8812a1ant_ps_tdma(btcoexist, NORMAL_EXEC, true,
+						22);
+			halbtc8812a1ant_coex_table_with_type(btcoexist,
+							     NORMAL_EXEC, 4);
+		} else {
+			halbtc8812a1ant_ps_tdma(btcoexist, NORMAL_EXEC, true,
+						20);
+			halbtc8812a1ant_coex_table_with_type(btcoexist,
+							     NORMAL_EXEC, 4);
+		}
+	} else if ((BT_8812A_1ANT_BT_STATUS_SCO_BUSY == coex_dm->bt_status) ||
+		   (BT_8812A_1ANT_BT_STATUS_ACL_SCO_BUSY ==
+		    coex_dm->bt_status)) {
+		halbtc8812a1ant_action_bt_sco_hid_only_busy(btcoexist,
+				BT_8812A_1ANT_WIFI_STATUS_CONNECTED_SCAN);
+	} else {
+		/* Bryant Add */
+		halbtc8812a1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 8);
+		halbtc8812a1ant_set_ant_path(btcoexist, BTC_ANT_PATH_PTA,
+					     NORMAL_EXEC, false, false);
+		halbtc8812a1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 2);
+	}
+}
+
+void halbtc8812a1ant_action_wifi_not_connected_asso_auth(
+	IN struct btc_coexist *btcoexist)
+{
+	struct  btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
+
+	halbtc8812a1ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, 0x0,
+					 0x0);
+
+	/* tdma and coex table */
+	if ((bt_link_info->sco_exist)  || (bt_link_info->hid_exist) ||
+	    (bt_link_info->a2dp_exist)) {
+		halbtc8812a1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 32);
+		halbtc8812a1ant_coex_table_with_type(btcoexist, FORCE_EXEC, 4);
+	} else if (bt_link_info->pan_exist) {
+		halbtc8812a1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 20);
+		halbtc8812a1ant_coex_table_with_type(btcoexist, FORCE_EXEC, 4);
+	} else {
+		halbtc8812a1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 8);
+		halbtc8812a1ant_set_ant_path(btcoexist, BTC_ANT_PATH_PTA,
+					     NORMAL_EXEC, false, false);
+		halbtc8812a1ant_coex_table_with_type(btcoexist, FORCE_EXEC, 2);
+	}
+}
+
+void halbtc8812a1ant_action_wifi_connected_scan(IN struct btc_coexist
+		*btcoexist)
+{
+	struct  btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
+
+	halbtc8812a1ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, 0x0,
+					 0x0);
+
+	/* tdma and coex table */
+	if (BT_8812A_1ANT_BT_STATUS_ACL_BUSY == coex_dm->bt_status) {
+		if (bt_link_info->a2dp_exist) {
+			halbtc8812a1ant_ps_tdma(btcoexist, NORMAL_EXEC, true,
+						32);
+			halbtc8812a1ant_coex_table_with_type(btcoexist,
+							     NORMAL_EXEC, 4);
+		} else if (bt_link_info->a2dp_exist &&
+			   bt_link_info->pan_exist) {
+			halbtc8812a1ant_ps_tdma(btcoexist, NORMAL_EXEC, true,
+						22);
+			halbtc8812a1ant_coex_table_with_type(btcoexist,
+							     NORMAL_EXEC, 4);
+		} else {
+			halbtc8812a1ant_ps_tdma(btcoexist, NORMAL_EXEC, true,
+						20);
+			halbtc8812a1ant_coex_table_with_type(btcoexist,
+							     NORMAL_EXEC, 4);
+		}
+	} else if ((BT_8812A_1ANT_BT_STATUS_SCO_BUSY == coex_dm->bt_status) ||
+		   (BT_8812A_1ANT_BT_STATUS_ACL_SCO_BUSY ==
+		    coex_dm->bt_status)) {
+		halbtc8812a1ant_action_bt_sco_hid_only_busy(btcoexist,
+				BT_8812A_1ANT_WIFI_STATUS_CONNECTED_SCAN);
+	} else {
+		/* Bryant Add */
+		halbtc8812a1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 8);
+		halbtc8812a1ant_set_ant_path(btcoexist, BTC_ANT_PATH_PTA,
+					     NORMAL_EXEC, false, false);
+		halbtc8812a1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 2);
+	}
+}
+
+void halbtc8812a1ant_action_wifi_connected_specific_packet(
+	IN struct btc_coexist *btcoexist)
+{
+	struct  btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
+
+	halbtc8812a1ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, 0x0,
+					 0x0);
+
+	/* tdma and coex table */
+	if ((bt_link_info->sco_exist) || (bt_link_info->hid_exist) ||
+	    (bt_link_info->a2dp_exist)) {
+		halbtc8812a1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 32);
+		halbtc8812a1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4);
+	} else if (bt_link_info->pan_exist) {
+		halbtc8812a1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 20);
+		halbtc8812a1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4);
+	} else {
+		halbtc8812a1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 8);
+		halbtc8812a1ant_set_ant_path(btcoexist, BTC_ANT_PATH_PTA,
+					     NORMAL_EXEC, false, false);
+		halbtc8812a1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 2);
+	}
+}
+
+void halbtc8812a1ant_action_wifi_connected(IN struct btc_coexist *btcoexist)
+{
+	boolean	wifi_busy = false;
+	boolean		scan = false, link = false, roam = false;
+	boolean		under_4way = false, ap_enable = false;
+
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+		    "[BTCoex], CoexForWifiConnect()===>\n");
+	BTC_TRACE(trace_buf);
+
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_4_WAY_PROGRESS,
+			   &under_4way);
+	if (under_4way) {
+		halbtc8812a1ant_action_wifi_connected_specific_packet(btcoexist);
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			"[BTCoex], CoexForWifiConnect(), return for wifi is under 4way<===\n");
+		BTC_TRACE(trace_buf);
+		return;
+	}
+
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_SCAN, &scan);
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_LINK, &link);
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_ROAM, &roam);
+	if (scan || link || roam) {
+		if (scan)
+			halbtc8812a1ant_action_wifi_connected_scan(btcoexist);
+		else
+			halbtc8812a1ant_action_wifi_connected_specific_packet(
+				btcoexist);
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			"[BTCoex], CoexForWifiConnect(), return for wifi is under scan<===\n");
+		BTC_TRACE(trace_buf);
+		return;
+	}
+
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_AP_MODE_ENABLE,
+			   &ap_enable);
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy);
+
+	/* power save state */
+	if (!ap_enable &&
+	    BT_8812A_1ANT_BT_STATUS_ACL_BUSY == coex_dm->bt_status &&
+	    !btcoexist->bt_link_info.hid_only) {
+		if (btcoexist->bt_link_info.a2dp_only) {	/* A2DP */
+			if (!wifi_busy)
+				halbtc8812a1ant_power_save_state(btcoexist,
+						 BTC_PS_WIFI_NATIVE, 0x0, 0x0);
+			else { /* busy */
+				if (coex_sta->scan_ap_num >=
+				    BT_8812A_1ANT_WIFI_NOISY_THRESH)  /* no force LPS, no PS-TDMA, use pure TDMA */
+					halbtc8812a1ant_power_save_state(
+						btcoexist, BTC_PS_WIFI_NATIVE,
+						0x0, 0x0);
+				else
+					halbtc8812a1ant_power_save_state(
+						btcoexist, BTC_PS_LPS_ON, 0x50,
+						0x4);
+			}
+		} else if ((coex_sta->pan_exist == false) &&
+			   (coex_sta->a2dp_exist == false) &&
+			   (coex_sta->hid_exist == false))
+			halbtc8812a1ant_power_save_state(btcoexist,
+						 BTC_PS_WIFI_NATIVE, 0x0, 0x0);
+		else
+			halbtc8812a1ant_power_save_state(btcoexist,
+						 BTC_PS_LPS_ON, 0x50, 0x4);
+	} else
+		halbtc8812a1ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE,
+						 0x0, 0x0);
+
+	/* tdma and coex table */
+	if (!wifi_busy) {
+		if (BT_8812A_1ANT_BT_STATUS_ACL_BUSY == coex_dm->bt_status) {
+			halbtc8812a1ant_action_wifi_connected_bt_acl_busy(
+				btcoexist,
+				BT_8812A_1ANT_WIFI_STATUS_CONNECTED_IDLE);
+		} else if ((BT_8812A_1ANT_BT_STATUS_SCO_BUSY ==
+			    coex_dm->bt_status) ||
+			   (BT_8812A_1ANT_BT_STATUS_ACL_SCO_BUSY ==
+			    coex_dm->bt_status)) {
+			halbtc8812a1ant_action_bt_sco_hid_only_busy(btcoexist,
+				BT_8812A_1ANT_WIFI_STATUS_CONNECTED_IDLE);
+		} else {
+			halbtc8812a1ant_ps_tdma(btcoexist, NORMAL_EXEC, false,
+						8);
+			halbtc8812a1ant_set_ant_path(btcoexist,
+				BTC_ANT_PATH_PTA, NORMAL_EXEC, false, false);
+			if ((coex_sta->high_priority_tx) +
+			    (coex_sta->high_priority_rx) <= 60)
+				halbtc8812a1ant_coex_table_with_type(btcoexist,
+							     NORMAL_EXEC, 2);
+			else
+				halbtc8812a1ant_coex_table_with_type(btcoexist,
+							     NORMAL_EXEC, 7);
+		}
+	} else {
+		if (BT_8812A_1ANT_BT_STATUS_ACL_BUSY == coex_dm->bt_status) {
+			halbtc8812a1ant_action_wifi_connected_bt_acl_busy(
+				btcoexist,
+				BT_8812A_1ANT_WIFI_STATUS_CONNECTED_BUSY);
+		} else if ((BT_8812A_1ANT_BT_STATUS_SCO_BUSY ==
+			    coex_dm->bt_status) ||
+			   (BT_8812A_1ANT_BT_STATUS_ACL_SCO_BUSY ==
+			    coex_dm->bt_status)) {
+			halbtc8812a1ant_action_bt_sco_hid_only_busy(btcoexist,
+				BT_8812A_1ANT_WIFI_STATUS_CONNECTED_BUSY);
+		} else {
+			halbtc8812a1ant_ps_tdma(btcoexist, NORMAL_EXEC, false,
+						8);
+			halbtc8812a1ant_set_ant_path(btcoexist,
+				BTC_ANT_PATH_PTA, NORMAL_EXEC, false, false);
+			if ((coex_sta->high_priority_tx) +
+			    (coex_sta->high_priority_rx) <= 60)
+				halbtc8812a1ant_coex_table_with_type(btcoexist,
+							     NORMAL_EXEC, 2);
+			else
+				halbtc8812a1ant_coex_table_with_type(btcoexist,
+							     NORMAL_EXEC, 7);
+		}
+	}
+}
+
+void halbtc8812a1ant_run_sw_coexist_mechanism(IN struct btc_coexist *btcoexist)
+{
+	u8				algorithm = 0;
+
+	algorithm = halbtc8812a1ant_action_algorithm(btcoexist);
+	coex_dm->cur_algorithm = algorithm;
+
+	if (halbtc8812a1ant_is_common_action(btcoexist)) {
+
+	} else {
+		switch (coex_dm->cur_algorithm) {
+		case BT_8812A_1ANT_COEX_ALGO_SCO:
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				    "[BTCoex], Action algorithm = SCO.\n");
+			BTC_TRACE(trace_buf);
+			/* halbtc8812a1ant_action_sco(btcoexist); */
+			break;
+		case BT_8812A_1ANT_COEX_ALGO_HID:
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				    "[BTCoex], Action algorithm = HID.\n");
+			BTC_TRACE(trace_buf);
+			/* halbtc8812a1ant_action_hid(btcoexist); */
+			break;
+		case BT_8812A_1ANT_COEX_ALGO_A2DP:
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				    "[BTCoex], Action algorithm = A2DP.\n");
+			BTC_TRACE(trace_buf);
+			/* halbtc8812a1ant_action_a2dp(btcoexist); */
+			break;
+		case BT_8812A_1ANT_COEX_ALGO_A2DP_PANHS:
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				"[BTCoex], Action algorithm = A2DP+PAN(HS).\n");
+			BTC_TRACE(trace_buf);
+			/* halbtc8812a1ant_action_a2dp_pan_hs(btcoexist); */
+			break;
+		case BT_8812A_1ANT_COEX_ALGO_PANEDR:
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				    "[BTCoex], Action algorithm = PAN(EDR).\n");
+			BTC_TRACE(trace_buf);
+			/* halbtc8812a1ant_action_pan_edr(btcoexist); */
+			break;
+		case BT_8812A_1ANT_COEX_ALGO_PANHS:
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				    "[BTCoex], Action algorithm = HS mode.\n");
+			BTC_TRACE(trace_buf);
+			/* halbtc8812a1ant_action_pan_hs(btcoexist); */
+			break;
+		case BT_8812A_1ANT_COEX_ALGO_PANEDR_A2DP:
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				    "[BTCoex], Action algorithm = PAN+A2DP.\n");
+			BTC_TRACE(trace_buf);
+			/* halbtc8812a1ant_action_pan_edr_a2dp(btcoexist); */
+			break;
+		case BT_8812A_1ANT_COEX_ALGO_PANEDR_HID:
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				"[BTCoex], Action algorithm = PAN(EDR)+HID.\n");
+			BTC_TRACE(trace_buf);
+			/* halbtc8812a1ant_action_pan_edr_hid(btcoexist); */
+			break;
+		case BT_8812A_1ANT_COEX_ALGO_HID_A2DP_PANEDR:
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				"[BTCoex], Action algorithm = HID+A2DP+PAN.\n");
+			BTC_TRACE(trace_buf);
+			/* halbtc8812a1ant_action_hid_a2dp_pan_edr(btcoexist); */
+			break;
+		case BT_8812A_1ANT_COEX_ALGO_HID_A2DP:
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				    "[BTCoex], Action algorithm = HID+A2DP.\n");
+			BTC_TRACE(trace_buf);
+			/* halbtc8812a1ant_action_hid_a2dp(btcoexist); */
+			break;
+		default:
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				"[BTCoex], Action algorithm = coexist All Off!!\n");
+			BTC_TRACE(trace_buf);
+			/* halbtc8812a1ant_coex_all_off(btcoexist); */
+			break;
+		}
+		coex_dm->pre_algorithm = coex_dm->cur_algorithm;
+	}
+}
+
+void halbtc8812a1ant_run_coexist_mechanism(IN struct btc_coexist *btcoexist)
+{
+	struct  btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
+	boolean	wifi_connected = false, bt_hs_on = false;
+	boolean	increase_scan_dev_num = false;
+	boolean	bt_ctrl_agg_buf_size = false;
+	boolean	miracast_plus_bt = false;
+	u8	agg_buf_size = 5;
+	u32	wifi_link_status = 0;
+	u32	num_of_wifi_link = 0, wifi_bw;
+
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+		    "[BTCoex], RunCoexistMechanism()===>\n");
+	BTC_TRACE(trace_buf);
+
+	if (btcoexist->manual_control) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			"[BTCoex], RunCoexistMechanism(), return for Manual CTRL <===\n");
+		BTC_TRACE(trace_buf);
+		return;
+	}
+
+	if (btcoexist->stop_coex_dm) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			"[BTCoex], RunCoexistMechanism(), return for Stop Coex DM <===\n");
+		BTC_TRACE(trace_buf);
+		return;
+	}
+
+	if (coex_sta->under_ips) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], wifi is under IPS !!!\n");
+		BTC_TRACE(trace_buf);
+		return;
+	}
+
+	if ((BT_8812A_1ANT_BT_STATUS_ACL_BUSY == coex_dm->bt_status) ||
+	    (BT_8812A_1ANT_BT_STATUS_SCO_BUSY == coex_dm->bt_status) ||
+	    (BT_8812A_1ANT_BT_STATUS_ACL_SCO_BUSY == coex_dm->bt_status))
+		increase_scan_dev_num = true;
+
+	btcoexist->btc_set(btcoexist, BTC_SET_BL_INC_SCAN_DEV_NUM,
+			   &increase_scan_dev_num);
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED,
+			   &wifi_connected);
+
+	btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_LINK_STATUS,
+			   &wifi_link_status);
+	num_of_wifi_link = wifi_link_status >> 16;
+
+	if ((num_of_wifi_link >= 2) ||
+	    (wifi_link_status & WIFI_P2P_GO_CONNECTED)) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			"############# [BTCoex],  Multi-Port num_of_wifi_link = %d, wifi_link_status = 0x%x\n",
+			    num_of_wifi_link, wifi_link_status);
+		BTC_TRACE(trace_buf);
+
+		if (bt_link_info->bt_link_exist) {
+			halbtc8812a1ant_limited_tx(btcoexist, NORMAL_EXEC, 1, 1,
+						   0, 1);
+			miracast_plus_bt = true;
+		} else {
+			halbtc8812a1ant_limited_tx(btcoexist, NORMAL_EXEC, 0, 0,
+						   0, 0);
+			miracast_plus_bt = false;
+		}
+		btcoexist->btc_set(btcoexist, BTC_SET_BL_MIRACAST_PLUS_BT,
+				   &miracast_plus_bt);
+		halbtc8812a1ant_limited_rx(btcoexist, NORMAL_EXEC, false,
+					   bt_ctrl_agg_buf_size, agg_buf_size);
+
+		if ((bt_link_info->a2dp_exist) &&
+		    (coex_sta->c2h_bt_inquiry_page)) {
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				"############# [BTCoex],  BT Is Inquirying\n");
+			BTC_TRACE(trace_buf);
+			halbtc8812a1ant_action_bt_inquiry(btcoexist);
+		} else
+			halbtc8812a1ant_action_wifi_multi_port(btcoexist);
+
+		return;
+	}
+
+	miracast_plus_bt = false;
+	btcoexist->btc_set(btcoexist, BTC_SET_BL_MIRACAST_PLUS_BT,
+			   &miracast_plus_bt);
+
+	btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw);
+
+	if ((bt_link_info->bt_link_exist) && (wifi_connected)) {
+		halbtc8812a1ant_limited_tx(btcoexist, NORMAL_EXEC, 1, 1, 0, 1);
+
+		if (bt_link_info->sco_exist)
+			halbtc8812a1ant_limited_rx(btcoexist, NORMAL_EXEC, true,
+						   false, 0x5);
+		else {
+			if (BTC_WIFI_BW_HT40 == wifi_bw)
+				halbtc8812a1ant_limited_rx(btcoexist, NORMAL_EXEC,
+							   false, true, 0x10);
+			else
+				halbtc8812a1ant_limited_rx(btcoexist, NORMAL_EXEC,
+							   false, true, 0x8);
+		}
+
+		halbtc8812a1ant_sw_mechanism(btcoexist, true);
+		halbtc8812a1ant_run_sw_coexist_mechanism(
+			btcoexist);  /* just print debug message */
+	} else {
+		halbtc8812a1ant_limited_tx(btcoexist, NORMAL_EXEC, 0, 0, 0, 0);
+
+		halbtc8812a1ant_limited_rx(btcoexist, NORMAL_EXEC, false, false,
+					   0x5);
+
+		halbtc8812a1ant_sw_mechanism(btcoexist, false);
+		halbtc8812a1ant_run_sw_coexist_mechanism(
+			btcoexist); /* //just print debug message */
+	}
+
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on);
+	if (coex_sta->c2h_bt_inquiry_page) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "############# [BTCoex],  BT Is Inquirying\n");
+		BTC_TRACE(trace_buf);
+		halbtc8812a1ant_action_bt_inquiry(btcoexist);
+		return;
+	} else if (bt_hs_on) {
+		halbtc8812a1ant_action_hs(btcoexist);
+		return;
+	}
+
+
+	if (!wifi_connected) {
+		boolean	scan = false, link = false, roam = false;
+
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], wifi is non connected-idle !!!\n");
+		BTC_TRACE(trace_buf);
+
+		btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_SCAN, &scan);
+		btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_LINK, &link);
+		btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_ROAM, &roam);
+
+		if (scan || link || roam) {
+			if (scan)
+				halbtc8812a1ant_action_wifi_not_connected_scan(
+					btcoexist);
+			else
+				halbtc8812a1ant_action_wifi_not_connected_asso_auth(
+					btcoexist);
+		} else
+			halbtc8812a1ant_action_wifi_not_connected(btcoexist);
+	} else	/* wifi LPS/Busy */
+		halbtc8812a1ant_action_wifi_connected(btcoexist);
+}
+
+void halbtc8812a1ant_init_coex_dm(IN struct btc_coexist *btcoexist)
+{
+	/* force to reset coex mechanism */
+
+	/* sw all off */
+	halbtc8812a1ant_sw_mechanism(btcoexist, false);
+
+	/* halbtc8812a1ant_ps_tdma(btcoexist, FORCE_EXEC, false, 8); */
+	/* halbtc8812a1ant_coex_table_with_type(btcoexist, FORCE_EXEC, 0); */
+
+	coex_sta->pop_event_cnt = 0;
+}
+
+void halbtc8812a1ant_init_hw_config(IN struct btc_coexist *btcoexist,
+				    IN boolean back_up, IN boolean wifi_only)
+{
+	u8	u8tmp = 0;
+
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+		    "[BTCoex], 1Ant Init HW Config!!\n");
+	BTC_TRACE(trace_buf);
+
+	/* ant sw control to BT */
+	halbtc8812a1ant_set_ant_path(btcoexist, BTC_ANT_PATH_BT, FORCE_EXEC,
+				     true, false);
+
+	/* 0x790[5:0]=0x5 */
+	u8tmp = btcoexist->btc_read_1byte(btcoexist, 0x790);
+	u8tmp &= 0xc0;
+	u8tmp |= 0x5;
+	btcoexist->btc_write_1byte(btcoexist, 0x790, u8tmp);
+
+	/* PTA parameter */
+	btcoexist->btc_write_1byte(btcoexist, 0x6cc, 0x0);
+	btcoexist->btc_write_4byte(btcoexist, 0x6c8, 0xffff);
+	btcoexist->btc_write_4byte(btcoexist, 0x6c4, 0x55555555);
+	btcoexist->btc_write_4byte(btcoexist, 0x6c0, 0x55555555);
+
+	/* coex parameters */
+	btcoexist->btc_write_1byte(btcoexist, 0x778, 0x1);
+
+	/* enable counter statistics */
+	btcoexist->btc_write_1byte(btcoexist, 0x76e, 0x4);
+
+	/* enable PTA */
+	btcoexist->btc_write_1byte(btcoexist, 0x40, 0x20);
+
+	/* bt clock related */
+	u8tmp = btcoexist->btc_read_1byte(btcoexist, 0x4);
+	u8tmp |= BIT(7);
+	btcoexist->btc_write_1byte(btcoexist, 0x4, u8tmp);
+
+	/* bt clock related */
+	u8tmp = btcoexist->btc_read_1byte(btcoexist, 0x7);
+	u8tmp |= BIT(1);
+	btcoexist->btc_write_1byte(btcoexist, 0x7, u8tmp);
+}
+
+/* ************************************************************
+ * work around function start with wa_halbtc8812a1ant_
+ * ************************************************************
+ * ************************************************************
+ * extern function start with ex_halbtc8812a1ant_
+ * ************************************************************ */
+void ex_halbtc8812a1ant_power_on_setting(IN struct btc_coexist *btcoexist)
+{
+}
+
+void ex_halbtc8812a1ant_pre_load_firmware(IN struct btc_coexist *btcoexist)
+{
+}
+
+void ex_halbtc8812a1ant_init_hw_config(IN struct btc_coexist *btcoexist,
+				       IN boolean wifi_only)
+{
+	halbtc8812a1ant_init_hw_config(btcoexist, true, wifi_only);
+	btcoexist->stop_coex_dm = false;
+}
+
+void ex_halbtc8812a1ant_init_coex_dm(IN struct btc_coexist *btcoexist)
+{
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+		    "[BTCoex], Coex Mechanism Init!!\n");
+	BTC_TRACE(trace_buf);
+
+	btcoexist->stop_coex_dm = false;
+
+	halbtc8812a1ant_init_coex_dm(btcoexist);
+
+	halbtc8812a1ant_query_bt_info(btcoexist);
+}
+
+void ex_halbtc8812a1ant_display_coex_info(IN struct btc_coexist *btcoexist)
+{
+	struct  btc_board_info	*board_info = &btcoexist->board_info;
+	struct  btc_bt_link_info	*bt_link_info = &btcoexist->bt_link_info;
+	u8			*cli_buf = btcoexist->cli_buf;
+	u8				u8tmp[4], i, bt_info_ext, ps_tdma_case = 0;
+	u32				u32tmp[4];
+	u32				fw_ver = 0, bt_patch_ver = 0;
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+		   "\r\n ============[BT Coexist info]============");
+	CL_PRINTF(cli_buf);
+
+	if (btcoexist->manual_control) {
+		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+			"\r\n ============[Under Manual Control]============");
+		CL_PRINTF(cli_buf);
+		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+			   "\r\n ==========================================");
+		CL_PRINTF(cli_buf);
+	}
+	if (btcoexist->stop_coex_dm) {
+		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+			   "\r\n ============[Coex is STOPPED]============");
+		CL_PRINTF(cli_buf);
+		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+			   "\r\n ==========================================");
+		CL_PRINTF(cli_buf);
+	}
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d ",
+		   "Ant PG number/ Ant mechanism:",
+		   board_info->pg_ant_num, board_info->btdm_ant_num);
+	CL_PRINTF(cli_buf);
+
+	btcoexist->btc_get(btcoexist, BTC_GET_U4_BT_PATCH_VER, &bt_patch_ver);
+	btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_FW_VER, &fw_ver);
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+		   "\r\n %-35s = %d_%d/ 0x%x/ 0x%x(%d)",
+		   "CoexVer/ FwVer/ PatchVer",
+		   glcoex_ver_date_8812a_1ant, glcoex_ver_8812a_1ant, fw_ver,
+		   bt_patch_ver, bt_patch_ver);
+	CL_PRINTF(cli_buf);
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %02x %02x %02x ",
+		   "Wifi channel informed to BT",
+		   coex_dm->wifi_chnl_info[0], coex_dm->wifi_chnl_info[1],
+		   coex_dm->wifi_chnl_info[2]);
+	CL_PRINTF(cli_buf);
+
+	/* wifi status */
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s",
+		   "============[Wifi Status]============");
+	CL_PRINTF(cli_buf);
+	btcoexist->btc_disp_dbg_msg(btcoexist, BTC_DBG_DISP_WIFI_STATUS);
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s",
+		   "============[BT Status]============");
+	CL_PRINTF(cli_buf);
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = [%s/ %d/ %d] ",
+		   "BT [status/ rssi/ retryCnt]",
+		   ((coex_sta->bt_disabled) ? ("disabled") :	((
+		   coex_sta->c2h_bt_inquiry_page) ? ("inquiry/page scan")
+			   : ((BT_8812A_1ANT_BT_STATUS_NON_CONNECTED_IDLE ==
+			       coex_dm->bt_status) ? "non-connected idle" :
+		((BT_8812A_1ANT_BT_STATUS_CONNECTED_IDLE == coex_dm->bt_status)
+				       ? "connected-idle" : "busy")))),
+		   coex_sta->bt_rssi, coex_sta->bt_retry_cnt);
+	CL_PRINTF(cli_buf);
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d / %d / %d / %d",
+		   "SCO/HID/PAN/A2DP",
+		   bt_link_info->sco_exist, bt_link_info->hid_exist,
+		   bt_link_info->pan_exist, bt_link_info->a2dp_exist);
+	CL_PRINTF(cli_buf);
+	btcoexist->btc_disp_dbg_msg(btcoexist, BTC_DBG_DISP_BT_LINK_INFO);
+
+	bt_info_ext = coex_sta->bt_info_ext;
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s",
+		   "BT Info A2DP rate",
+		   (bt_info_ext & BIT(0)) ? "Basic rate" : "EDR rate");
+	CL_PRINTF(cli_buf);
+
+	for (i = 0; i < BT_INFO_SRC_8812A_1ANT_MAX; i++) {
+		if (coex_sta->bt_info_c2h_cnt[i]) {
+			CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+				"\r\n %-35s = %02x %02x %02x %02x %02x %02x %02x(%d)",
+				   glbt_info_src_8812a_1ant[i],
+				   coex_sta->bt_info_c2h[i][0],
+				   coex_sta->bt_info_c2h[i][1],
+				   coex_sta->bt_info_c2h[i][2],
+				   coex_sta->bt_info_c2h[i][3],
+				   coex_sta->bt_info_c2h[i][4],
+				   coex_sta->bt_info_c2h[i][5],
+				   coex_sta->bt_info_c2h[i][6],
+				   coex_sta->bt_info_c2h_cnt[i]);
+			CL_PRINTF(cli_buf);
+		}
+	}
+
+	if (!btcoexist->manual_control) {
+		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s",
+			   "============[mechanisms]============");
+		CL_PRINTF(cli_buf);
+
+		ps_tdma_case = coex_dm->cur_ps_tdma;
+		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+			   "\r\n %-35s = %02x %02x %02x %02x %02x case-%d",
+			   "PS TDMA",
+			   coex_dm->ps_tdma_para[0], coex_dm->ps_tdma_para[1],
+			   coex_dm->ps_tdma_para[2], coex_dm->ps_tdma_para[3],
+			   coex_dm->ps_tdma_para[4], ps_tdma_case);
+		CL_PRINTF(cli_buf);
+
+		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x ",
+			   "Latest error condition(should be 0)",
+			   coex_dm->error_condition);
+		CL_PRINTF(cli_buf);
+
+		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d ",
+			   "IgnWlanAct",
+			   coex_dm->cur_ignore_wlan_act);
+		CL_PRINTF(cli_buf);
+	}
+
+	/* Hw setting		 */
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s",
+		   "============[Hw setting]============");
+	CL_PRINTF(cli_buf);
+
+	u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x778);
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x", "0x778",
+		   u8tmp[0]);
+	CL_PRINTF(cli_buf);
+
+	u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0xcb3);
+	u8tmp[1] = btcoexist->btc_read_1byte(btcoexist, 0xcb7);
+	u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x900);
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x/ 0x%x",
+		   "0xcb3/0xcb7/0x900",
+		   u8tmp[0], u8tmp[1], u32tmp[0]);
+	CL_PRINTF(cli_buf);
+
+	u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x40);
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x", "0x40",
+		   u8tmp[0]);
+	CL_PRINTF(cli_buf);
+
+	u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x550);
+	u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x522);
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x",
+		   "0x550(bcn ctrl)/0x522",
+		   u32tmp[0], u8tmp[0]);
+	CL_PRINTF(cli_buf);
+
+	u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0xc50);
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x", "0xc50(dig)",
+		   u32tmp[0]);
+	CL_PRINTF(cli_buf);
+
+	u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x6c0);
+	u32tmp[1] = btcoexist->btc_read_4byte(btcoexist, 0x6c4);
+	u32tmp[2] = btcoexist->btc_read_4byte(btcoexist, 0x6c8);
+	u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x6cc);
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+		   "\r\n %-35s = 0x%x/ 0x%x/ 0x%x/ 0x%x",
+		   "0x6c0/0x6c4/0x6c8/0x6cc(coexTable)",
+		   u32tmp[0], u32tmp[1], u32tmp[2], u8tmp[0]);
+	CL_PRINTF(cli_buf);
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d",
+		   "0x770(hp rx[31:16]/tx[15:0])",
+		   coex_sta->high_priority_rx, coex_sta->high_priority_tx);
+	CL_PRINTF(cli_buf);
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d",
+		   "0x774(lp rx[31:16]/tx[15:0])",
+		   coex_sta->low_priority_rx, coex_sta->low_priority_tx);
+	CL_PRINTF(cli_buf);
+
+	btcoexist->btc_disp_dbg_msg(btcoexist, BTC_DBG_DISP_COEX_STATISTICS);
+}
+
+
+
+void ex_halbtc8812a1ant_ips_notify(IN struct btc_coexist *btcoexist, IN u8 type)
+{
+	if (btcoexist->manual_control ||	btcoexist->stop_coex_dm)
+		return;
+
+	if (BTC_IPS_ENTER == type) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], IPS ENTER notify\n");
+		BTC_TRACE(trace_buf);
+		coex_sta->under_ips = true;
+
+		halbtc8812a1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 0);
+		halbtc8812a1ant_set_ant_path(btcoexist, BTC_ANT_PATH_BT,
+					     FORCE_EXEC, false, true);
+		halbtc8812a1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0);
+	} else if (BTC_IPS_LEAVE == type) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], IPS LEAVE notify\n");
+		BTC_TRACE(trace_buf);
+
+		halbtc8812a1ant_init_hw_config(btcoexist, false, false);
+		halbtc8812a1ant_init_coex_dm(btcoexist);
+		halbtc8812a1ant_query_bt_info(btcoexist);
+
+		coex_sta->under_ips = false;
+	}
+}
+
+void ex_halbtc8812a1ant_lps_notify(IN struct btc_coexist *btcoexist, IN u8 type)
+{
+	if (btcoexist->manual_control || btcoexist->stop_coex_dm)
+		return;
+
+	if (BTC_LPS_ENABLE == type) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], LPS ENABLE notify\n");
+		BTC_TRACE(trace_buf);
+		coex_sta->under_lps = true;
+	} else if (BTC_LPS_DISABLE == type) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], LPS DISABLE notify\n");
+		BTC_TRACE(trace_buf);
+		coex_sta->under_lps = false;
+	}
+}
+
+void ex_halbtc8812a1ant_scan_notify(IN struct btc_coexist *btcoexist,
+				    IN u8 type)
+{
+	boolean wifi_connected = false, bt_hs_on = false;
+	u32	wifi_link_status = 0;
+	u32	num_of_wifi_link = 0;
+	boolean	bt_ctrl_agg_buf_size = false;
+	u8	agg_buf_size = 5;
+
+	if (btcoexist->manual_control ||
+	    btcoexist->stop_coex_dm)
+		return;
+
+	if (BTC_SCAN_START == type) {
+		coex_sta->wifi_is_high_pri_task = true;
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], SCAN START notify\n");
+		BTC_TRACE(trace_buf);
+
+		halbtc8812a1ant_ps_tdma(btcoexist, FORCE_EXEC, false,
+			8);  /* Force antenna setup for no scan result issue */
+		halbtc8812a1ant_set_ant_path(btcoexist, BTC_ANT_PATH_PTA,
+					     FORCE_EXEC, false, false);
+	} else {
+		coex_sta->wifi_is_high_pri_task = false;
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], SCAN FINISH notify\n");
+		BTC_TRACE(trace_buf);
+
+		btcoexist->btc_get(btcoexist, BTC_GET_U1_AP_NUM,
+				   &coex_sta->scan_ap_num);
+	}
+
+	if (coex_sta->bt_disabled)
+		return;
+
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on);
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED,
+			   &wifi_connected);
+
+	halbtc8812a1ant_query_bt_info(btcoexist);
+
+	btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_LINK_STATUS,
+			   &wifi_link_status);
+	num_of_wifi_link = wifi_link_status >> 16;
+	if (num_of_wifi_link >= 2) {
+		halbtc8812a1ant_limited_tx(btcoexist, NORMAL_EXEC, 0, 0, 0, 0);
+		halbtc8812a1ant_limited_rx(btcoexist, NORMAL_EXEC, false,
+					   bt_ctrl_agg_buf_size, agg_buf_size);
+		halbtc8812a1ant_action_wifi_multi_port(btcoexist);
+		return;
+	}
+
+	if (coex_sta->c2h_bt_inquiry_page) {
+		halbtc8812a1ant_action_bt_inquiry(btcoexist);
+		return;
+	} else if (bt_hs_on) {
+		halbtc8812a1ant_action_hs(btcoexist);
+		return;
+	}
+
+	if (BTC_SCAN_START == type) {
+		if (!wifi_connected)	/* non-connected scan */
+			halbtc8812a1ant_action_wifi_not_connected_scan(
+				btcoexist);
+		else	/* wifi is connected */
+			halbtc8812a1ant_action_wifi_connected_scan(btcoexist);
+	} else if (BTC_SCAN_FINISH == type) {
+		if (!wifi_connected)	/* non-connected scan */
+			halbtc8812a1ant_action_wifi_not_connected(btcoexist);
+		else
+			halbtc8812a1ant_action_wifi_connected(btcoexist);
+	}
+}
+
+void ex_halbtc8812a1ant_connect_notify(IN struct btc_coexist *btcoexist,
+				       IN u8 type)
+{
+	boolean	wifi_connected = false, bt_hs_on = false;
+	u32	wifi_link_status = 0;
+	u32	num_of_wifi_link = 0;
+	boolean	bt_ctrl_agg_buf_size = false;
+	u8	agg_buf_size = 5;
+
+	if (btcoexist->manual_control ||
+	    btcoexist->stop_coex_dm ||
+	    coex_sta->bt_disabled)
+		return;
+
+	if (BTC_ASSOCIATE_START == type) {
+		coex_sta->wifi_is_high_pri_task = true;
+		halbtc8812a1ant_ps_tdma(btcoexist, FORCE_EXEC, false,
+			8);  /* Force antenna setup for no scan result issue */
+		halbtc8812a1ant_set_ant_path(btcoexist, BTC_ANT_PATH_PTA,
+					     FORCE_EXEC, false, false);
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], CONNECT START notify\n");
+		BTC_TRACE(trace_buf);
+		coex_dm->arp_cnt = 0;
+	} else {
+		coex_sta->wifi_is_high_pri_task = false;
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], CONNECT FINISH notify\n");
+		BTC_TRACE(trace_buf);
+		/* coex_dm->arp_cnt = 0; */
+	}
+
+	btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_LINK_STATUS,
+			   &wifi_link_status);
+	num_of_wifi_link = wifi_link_status >> 16;
+	if (num_of_wifi_link >= 2) {
+		halbtc8812a1ant_limited_tx(btcoexist, NORMAL_EXEC, 0, 0, 0, 0);
+		halbtc8812a1ant_limited_rx(btcoexist, NORMAL_EXEC, false,
+					   bt_ctrl_agg_buf_size, agg_buf_size);
+		halbtc8812a1ant_action_wifi_multi_port(btcoexist);
+		return;
+	}
+
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on);
+	if (coex_sta->c2h_bt_inquiry_page) {
+		halbtc8812a1ant_action_bt_inquiry(btcoexist);
+		return;
+	} else if (bt_hs_on) {
+		halbtc8812a1ant_action_hs(btcoexist);
+		return;
+	}
+
+	if (BTC_ASSOCIATE_START == type)
+		halbtc8812a1ant_action_wifi_not_connected_asso_auth(btcoexist);
+	else if (BTC_ASSOCIATE_FINISH == type) {
+
+		btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED,
+				   &wifi_connected);
+		if (!wifi_connected) /* non-connected scan */
+			halbtc8812a1ant_action_wifi_not_connected(btcoexist);
+		else
+			halbtc8812a1ant_action_wifi_connected(btcoexist);
+	}
+}
+
+/* to check registers... */
+void ex_halbtc8812a1ant_media_status_notify(IN struct btc_coexist *btcoexist,
+		IN u8 type)
+{
+	u8			data_len = 5;
+	u8			buf[6] = {0};
+	u8			h2c_parameter[3] = {0};
+	u32			wifi_bw;
+	u8			wifi_central_chnl;
+	boolean			wifi_under_b_mode = false;
+
+	if (btcoexist->manual_control ||
+	    btcoexist->stop_coex_dm ||
+	    coex_sta->bt_disabled)
+		return;
+
+	if (BTC_MEDIA_CONNECT == type) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], MEDIA connect notify\n");
+		BTC_TRACE(trace_buf);
+		halbtc8812a1ant_ps_tdma(btcoexist, FORCE_EXEC, false,
+			8);  /* Force antenna setup for no scan result issue */
+		halbtc8812a1ant_set_ant_path(btcoexist, BTC_ANT_PATH_PTA,
+					     FORCE_EXEC, false, false);
+		btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_B_MODE,
+				   &wifi_under_b_mode);
+#if 0
+		/* Set CCK Tx/Rx high Pri except 11b mode */
+		if (wifi_under_b_mode) {
+			btcoexist->btc_write_1byte(btcoexist, 0x6cd,
+						   0x00); /* CCK Tx */
+			btcoexist->btc_write_1byte(btcoexist, 0x6cf,
+						   0x00); /* CCK Rx */
+		} else {
+			btcoexist->btc_write_1byte(btcoexist, 0x6cd,
+						   0x10); /* CCK Tx */
+			btcoexist->btc_write_1byte(btcoexist, 0x6cf,
+						   0x10); /* CCK Rx */
+		}
+#endif
+		coex_dm->backup_arfr_cnt1 = btcoexist->btc_read_4byte(btcoexist,
+					    0x430);
+		coex_dm->backup_arfr_cnt2 = btcoexist->btc_read_4byte(btcoexist,
+					    0x434);
+		coex_dm->backup_retry_limit = btcoexist->btc_read_2byte(
+						      btcoexist, 0x42a);
+		coex_dm->backup_ampdu_max_time = btcoexist->btc_read_1byte(
+				btcoexist, 0x456);
+	} else {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], MEDIA disconnect notify\n");
+		BTC_TRACE(trace_buf);
+		coex_dm->arp_cnt = 0;
+
+		btcoexist->btc_write_1byte(btcoexist, 0x6cd, 0x0); /* CCK Tx */
+		btcoexist->btc_write_1byte(btcoexist, 0x6cf, 0x0); /* CCK Rx */
+	}
+
+	/* only 2.4G we need to inform bt the chnl mask */
+	btcoexist->btc_get(btcoexist, BTC_GET_U1_WIFI_CENTRAL_CHNL,
+			   &wifi_central_chnl);
+	if ((BTC_MEDIA_CONNECT == type) &&
+	    (wifi_central_chnl <= 14)) {
+		/* h2c_parameter[0] = 0x1; */
+		h2c_parameter[0] = 0x0;
+		h2c_parameter[1] = wifi_central_chnl;
+		btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw);
+		if (BTC_WIFI_BW_HT40 == wifi_bw)
+			h2c_parameter[2] = 0x30;
+		else
+			h2c_parameter[2] = 0x20;
+	}
+
+	coex_dm->wifi_chnl_info[0] = h2c_parameter[0];
+	coex_dm->wifi_chnl_info[1] = h2c_parameter[1];
+	coex_dm->wifi_chnl_info[2] = h2c_parameter[2];
+
+	buf[0] = data_len;
+	buf[1] = 0x5;				/* OP_Code */
+	buf[2] = 0x3;				/* OP_Code_Length */
+	buf[3] = h2c_parameter[0];	/* OP_Code_Content */
+	buf[4] = h2c_parameter[1];
+	buf[5] = h2c_parameter[2];
+
+	btcoexist->btc_set(btcoexist, BTC_SET_ACT_CTRL_BT_COEX,
+			   (void *)&buf[0]);
+}
+
+void ex_halbtc8812a1ant_specific_packet_notify(IN struct btc_coexist *btcoexist,
+		IN u8 type)
+{
+	boolean	bt_hs_on = false;
+	u32	wifi_link_status = 0;
+	u32	num_of_wifi_link = 0;
+	boolean	bt_ctrl_agg_buf_size = false;
+	u8	agg_buf_size = 5;
+
+	if (btcoexist->manual_control ||
+	    btcoexist->stop_coex_dm ||
+	    coex_sta->bt_disabled)
+		return;
+
+	if (BTC_PACKET_DHCP == type ||
+	    BTC_PACKET_EAPOL == type ||
+	    BTC_PACKET_ARP == type) {
+		if (BTC_PACKET_ARP == type) {
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				    "[BTCoex], specific Packet ARP notify\n");
+			BTC_TRACE(trace_buf);
+
+			coex_dm->arp_cnt++;
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				    "[BTCoex], ARP Packet Count = %d\n",
+				    coex_dm->arp_cnt);
+			BTC_TRACE(trace_buf);
+
+			if (coex_dm->arp_cnt >=
+			    10) /* if APR PKT > 10 after connect, do not go to ActionWifiConnectedSpecificPacket(btcoexist) */
+				coex_sta->wifi_is_high_pri_task = false;
+			else
+				coex_sta->wifi_is_high_pri_task = true;
+		} else {
+			coex_sta->wifi_is_high_pri_task = true;
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				"[BTCoex], specific Packet DHCP or EAPOL notify\n");
+			BTC_TRACE(trace_buf);
+		}
+	} else {
+		coex_sta->wifi_is_high_pri_task = false;
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			"[BTCoex], specific Packet [Type = %d] notify\n", type);
+		BTC_TRACE(trace_buf);
+	}
+
+	coex_sta->specific_pkt_period_cnt = 0;
+
+	btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_LINK_STATUS,
+			   &wifi_link_status);
+	num_of_wifi_link = wifi_link_status >> 16;
+	if (num_of_wifi_link >= 2) {
+		halbtc8812a1ant_limited_tx(btcoexist, NORMAL_EXEC, 0, 0, 0, 0);
+		halbtc8812a1ant_limited_rx(btcoexist, NORMAL_EXEC, false,
+					   bt_ctrl_agg_buf_size, agg_buf_size);
+		halbtc8812a1ant_action_wifi_multi_port(btcoexist);
+		return;
+	}
+
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on);
+	if (coex_sta->c2h_bt_inquiry_page) {
+		halbtc8812a1ant_action_bt_inquiry(btcoexist);
+		return;
+	} else if (bt_hs_on) {
+		halbtc8812a1ant_action_hs(btcoexist);
+		return;
+	}
+
+	if (BTC_PACKET_DHCP == type ||
+	    BTC_PACKET_EAPOL == type ||
+	    ((BTC_PACKET_ARP == type) && (coex_sta->wifi_is_high_pri_task)))
+		halbtc8812a1ant_action_wifi_connected_specific_packet(btcoexist);
+}
+
+void ex_halbtc8812a1ant_bt_info_notify(IN struct btc_coexist *btcoexist,
+				       IN u8 *tmp_buf, IN u8 length)
+{
+	u8				bt_info = 0;
+	u8				i, rsp_source = 0;
+	boolean				wifi_connected = false;
+	boolean				bt_busy = false;
+
+	coex_sta->c2h_bt_info_req_sent = false;
+
+	rsp_source = tmp_buf[0] & 0xf;
+	if (rsp_source >= BT_INFO_SRC_8812A_1ANT_MAX)
+		rsp_source = BT_INFO_SRC_8812A_1ANT_WIFI_FW;
+	coex_sta->bt_info_c2h_cnt[rsp_source]++;
+
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+		    "[BTCoex], Bt info[%d], length=%d, hex data=[", rsp_source,
+		    length);
+	BTC_TRACE(trace_buf);
+	for (i = 0; i < length; i++) {
+		coex_sta->bt_info_c2h[rsp_source][i] = tmp_buf[i];
+		if (i == 1)
+			bt_info = tmp_buf[i];
+		if (i == length - 1) {
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "0x%02x]\n",
+				    tmp_buf[i]);
+			BTC_TRACE(trace_buf);
+		} else {
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "0x%02x, ",
+				    tmp_buf[i]);
+			BTC_TRACE(trace_buf);
+		}
+	}
+
+	if (BT_INFO_SRC_8812A_1ANT_WIFI_FW != rsp_source) {
+		coex_sta->bt_retry_cnt =	/* [3:0] */
+			coex_sta->bt_info_c2h[rsp_source][2] & 0xf;
+
+		if (coex_sta->bt_retry_cnt >= 1)
+			coex_sta->pop_event_cnt++;
+
+		if (coex_sta->bt_info_c2h[rsp_source][2] & 0x20)
+			coex_sta->c2h_bt_page = true;
+		else
+			coex_sta->c2h_bt_page = false;
+
+		coex_sta->bt_rssi =
+			coex_sta->bt_info_c2h[rsp_source][3] * 2 - 90;
+		/* coex_sta->bt_info_c2h[rsp_source][3]*2+10; */
+
+		coex_sta->bt_info_ext =
+			coex_sta->bt_info_c2h[rsp_source][4];
+
+		coex_sta->bt_tx_rx_mask = (coex_sta->bt_info_c2h[rsp_source][2]
+					   & 0x40);
+		btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_TX_RX_MASK,
+				   &coex_sta->bt_tx_rx_mask);
+		if (!coex_sta->bt_tx_rx_mask) {
+			/* BT into is responded by BT FW and BT RF REG 0x3C != 0x15 => Need to switch BT TRx Mask */
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				"[BTCoex], Switch BT TRx Mask since BT RF REG 0x3C != 0x15\n");
+			BTC_TRACE(trace_buf);
+			btcoexist->btc_set_bt_reg(btcoexist, BTC_BT_REG_RF,
+						  0x3c, 0x15);
+		}
+
+		/* Here we need to resend some wifi info to BT */
+		/* because bt is reset and loss of the info. */
+		if (coex_sta->bt_info_ext & BIT(1)) {
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				"[BTCoex], BT ext info bit1 check, send wifi BW&Chnl to BT!!\n");
+			BTC_TRACE(trace_buf);
+			btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED,
+					   &wifi_connected);
+			if (wifi_connected)
+				ex_halbtc8812a1ant_media_status_notify(
+					btcoexist, BTC_MEDIA_CONNECT);
+			else
+				ex_halbtc8812a1ant_media_status_notify(
+					btcoexist, BTC_MEDIA_DISCONNECT);
+		}
+
+		if (coex_sta->bt_info_ext & BIT(3)) {
+			if (!btcoexist->manual_control &&
+			    !btcoexist->stop_coex_dm) {
+				BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+					"[BTCoex], BT ext info bit3 check, set BT NOT to ignore Wlan active!!\n");
+				BTC_TRACE(trace_buf);
+				halbtc8812a1ant_ignore_wlan_act(btcoexist,
+							FORCE_EXEC, false);
+			}
+		} else {
+			/* BT already NOT ignore Wlan active, do nothing here. */
+		}
+#if (BT_AUTO_REPORT_ONLY_8812A_1ANT == 0)
+		if ((coex_sta->bt_info_ext & BIT(4))) {
+			/* BT auto report already enabled, do nothing */
+		} else
+			halbtc8812a1ant_bt_auto_report(btcoexist, FORCE_EXEC,
+						       true);
+#endif
+	}
+
+	/* check BIT2 first ==> check if bt is under inquiry or page scan */
+	if (bt_info & BT_INFO_8812A_1ANT_B_INQ_PAGE)
+		coex_sta->c2h_bt_inquiry_page = true;
+	else
+		coex_sta->c2h_bt_inquiry_page = false;
+
+	/* set link exist status */
+	if (!(bt_info & BT_INFO_8812A_1ANT_B_CONNECTION)) {
+		coex_sta->bt_link_exist = false;
+		coex_sta->pan_exist = false;
+		coex_sta->a2dp_exist = false;
+		coex_sta->hid_exist = false;
+		coex_sta->sco_exist = false;
+	} else {	/* connection exists */
+		coex_sta->bt_link_exist = true;
+		if (bt_info & BT_INFO_8812A_1ANT_B_FTP)
+			coex_sta->pan_exist = true;
+		else
+			coex_sta->pan_exist = false;
+		if (bt_info & BT_INFO_8812A_1ANT_B_A2DP)
+			coex_sta->a2dp_exist = true;
+		else
+			coex_sta->a2dp_exist = false;
+		if (bt_info & BT_INFO_8812A_1ANT_B_HID)
+			coex_sta->hid_exist = true;
+		else
+			coex_sta->hid_exist = false;
+		if (bt_info & BT_INFO_8812A_1ANT_B_SCO_ESCO)
+			coex_sta->sco_exist = true;
+		else
+			coex_sta->sco_exist = false;
+	}
+
+	halbtc8812a1ant_update_bt_link_info(btcoexist);
+
+	bt_info = bt_info &
+		0x1f;  /* mask profile bit for connect-ilde identification ( for CSR case: A2DP idle --> 0x41) */
+
+	if (!(bt_info & BT_INFO_8812A_1ANT_B_CONNECTION)) {
+		coex_dm->bt_status = BT_8812A_1ANT_BT_STATUS_NON_CONNECTED_IDLE;
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			"[BTCoex], BtInfoNotify(), BT Non-Connected idle!!!\n");
+		BTC_TRACE(trace_buf);
+	} else if (bt_info ==
+		BT_INFO_8812A_1ANT_B_CONNECTION) {	/* connection exists but no busy */
+		coex_dm->bt_status = BT_8812A_1ANT_BT_STATUS_CONNECTED_IDLE;
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], BtInfoNotify(), BT Connected-idle!!!\n");
+		BTC_TRACE(trace_buf);
+	} else if ((bt_info & BT_INFO_8812A_1ANT_B_SCO_ESCO) ||
+		   (bt_info & BT_INFO_8812A_1ANT_B_SCO_BUSY)) {
+		coex_dm->bt_status = BT_8812A_1ANT_BT_STATUS_SCO_BUSY;
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], BtInfoNotify(), BT SCO busy!!!\n");
+		BTC_TRACE(trace_buf);
+	} else if (bt_info & BT_INFO_8812A_1ANT_B_ACL_BUSY) {
+		if (BT_8812A_1ANT_BT_STATUS_ACL_BUSY != coex_dm->bt_status)
+			coex_dm->auto_tdma_adjust = false;
+		coex_dm->bt_status = BT_8812A_1ANT_BT_STATUS_ACL_BUSY;
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], BtInfoNotify(), BT ACL busy!!!\n");
+		BTC_TRACE(trace_buf);
+	} else {
+		coex_dm->bt_status = BT_8812A_1ANT_BT_STATUS_MAX;
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			"[BTCoex], BtInfoNotify(), BT Non-Defined state!!!\n");
+		BTC_TRACE(trace_buf);
+	}
+
+	if ((BT_8812A_1ANT_BT_STATUS_ACL_BUSY == coex_dm->bt_status) ||
+	    (BT_8812A_1ANT_BT_STATUS_SCO_BUSY == coex_dm->bt_status) ||
+	    (BT_8812A_1ANT_BT_STATUS_ACL_SCO_BUSY == coex_dm->bt_status))
+		bt_busy = true;
+	else
+		bt_busy = false;
+	btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_TRAFFIC_BUSY, &bt_busy);
+
+	halbtc8812a1ant_run_coexist_mechanism(btcoexist);
+}
+
+void ex_halbtc8812a1ant_rf_status_notify(IN struct btc_coexist *btcoexist,
+		IN u8 type)
+{
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], RF Status notify\n");
+	BTC_TRACE(trace_buf);
+
+	if (BTC_RF_ON == type) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], RF is turned ON!!\n");
+		BTC_TRACE(trace_buf);
+		btcoexist->stop_coex_dm = false;
+	} else if (BTC_RF_OFF == type) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], RF is turned OFF!!\n");
+		BTC_TRACE(trace_buf);
+
+		halbtc8812a1ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE,
+						 0x0, 0x0);
+		halbtc8812a1ant_ps_tdma(btcoexist, FORCE_EXEC, false, 0);
+		halbtc8812a1ant_set_ant_path(btcoexist, BTC_ANT_PATH_BT,
+					     FORCE_EXEC, false, true);
+
+		halbtc8812a1ant_ignore_wlan_act(btcoexist, FORCE_EXEC, true);
+		btcoexist->stop_coex_dm = true;
+	}
+}
+
+void ex_halbtc8812a1ant_halt_notify(IN struct btc_coexist *btcoexist)
+{
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], Halt notify\n");
+	BTC_TRACE(trace_buf);
+
+	halbtc8812a1ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, 0x0,
+					 0x0);
+	halbtc8812a1ant_ps_tdma(btcoexist, FORCE_EXEC, false, 0);
+	halbtc8812a1ant_set_ant_path(btcoexist, BTC_ANT_PATH_BT, FORCE_EXEC,
+				     false, true);
+
+	halbtc8812a1ant_ignore_wlan_act(btcoexist, FORCE_EXEC, true);
+
+	ex_halbtc8812a1ant_media_status_notify(btcoexist, BTC_MEDIA_DISCONNECT);
+
+	btcoexist->stop_coex_dm = true;
+}
+
+void ex_halbtc8812a1ant_pnp_notify(IN struct btc_coexist *btcoexist,
+				   IN u8 pnp_state)
+{
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], Pnp notify\n");
+	BTC_TRACE(trace_buf);
+
+	if (BTC_WIFI_PNP_SLEEP == pnp_state) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], Pnp notify to SLEEP\n");
+		BTC_TRACE(trace_buf);
+
+		halbtc8812a1ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE,
+						 0x0, 0x0);
+		halbtc8812a1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 0);
+		halbtc8812a1ant_set_ant_path(btcoexist, BTC_ANT_PATH_BT,
+					     FORCE_EXEC, false, true);
+		halbtc8812a1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 2);
+
+		/* Sinda 20150819, workaround for driver skip leave IPS/LPS to speed up sleep time. */
+		/* Driver do not leave IPS/LPS when driver is going to sleep, so BTCoexistence think wifi is still under IPS/LPS */
+		/* BT should clear UnderIPS/UnderLPS state to avoid mismatch state after wakeup. */
+		coex_sta->under_ips = false;
+		coex_sta->under_lps = false;
+		btcoexist->stop_coex_dm = true;
+	} else if (BTC_WIFI_PNP_WAKE_UP == pnp_state) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], Pnp notify to WAKE UP\n");
+		BTC_TRACE(trace_buf);
+		btcoexist->stop_coex_dm = false;
+		halbtc8812a1ant_init_hw_config(btcoexist, false, false);
+		halbtc8812a1ant_init_coex_dm(btcoexist);
+		halbtc8812a1ant_query_bt_info(btcoexist);
+	}
+}
+
+void ex_halbtc8812a1ant_coex_dm_reset(IN struct btc_coexist *btcoexist)
+{
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+		"[BTCoex], *****************Coex DM Reset*****************\n");
+	BTC_TRACE(trace_buf);
+
+	halbtc8812a1ant_init_hw_config(btcoexist, false, false);
+	halbtc8812a1ant_init_coex_dm(btcoexist);
+}
+
+void ex_halbtc8812a1ant_periodical(IN struct btc_coexist *btcoexist)
+{
+#if (BT_AUTO_REPORT_ONLY_8812A_1ANT == 0)
+	halbtc8812a1ant_query_bt_info(btcoexist);
+	halbtc8812a1ant_monitor_bt_enable_disable(btcoexist);
+#else
+	halbtc8812a1ant_monitor_bt_ctr(btcoexist);
+	halbtc8812a1ant_monitor_wifi_ctr(btcoexist);
+
+	if (halbtc8812a1ant_is_wifi_status_changed(btcoexist) ||
+	    coex_dm->auto_tdma_adjust)
+		halbtc8812a1ant_run_coexist_mechanism(btcoexist);
+
+	coex_sta->specific_pkt_period_cnt++;
+#endif
+}
+
+void ex_halbtc8812a1ant_dbg_control(IN struct btc_coexist *btcoexist,
+				    IN u8 op_code, IN u8 op_len, IN u8 *pdata)
+{
+	switch (op_code) {
+	case BTC_DBG_SET_COEX_NORMAL:
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], Set CoexMode to Normal\n");
+		BTC_TRACE(trace_buf);
+		btcoexist->manual_control = false;
+		halbtc8812a1ant_init_coex_dm(btcoexist);
+		break;
+	case BTC_DBG_SET_COEX_WIFI_ONLY:
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], Set CoexMode to Wifi Only\n");
+		BTC_TRACE(trace_buf);
+		btcoexist->manual_control = true;
+		halbtc8812a1ant_power_save_state(btcoexist,
+						 BTC_PS_WIFI_NATIVE, 0x0, 0x0);
+		halbtc8812a1ant_ps_tdma(btcoexist, NORMAL_EXEC, false,
+					9);
+		break;
+	case BTC_DBG_SET_COEX_BT_ONLY:
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], Set CoexMode to BT only\n");
+		BTC_TRACE(trace_buf);
+		btcoexist->manual_control = true;
+		halbtc8812a1ant_power_save_state(btcoexist,
+						 BTC_PS_WIFI_NATIVE, 0x0, 0x0);
+		halbtc8812a1ant_ps_tdma(btcoexist, NORMAL_EXEC, false,
+					0);
+		break;
+	case BTC_DBG_SET_COEX_DEC_BT_PWR:
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], Set Dec BT power\n");
+		BTC_TRACE(trace_buf);
+		{
+			u8	data_len = 4;
+			u8	buf[6] = {0};
+			u8	dec_bt_pwr = 0, pwr_level = 0;
+
+			if (op_len == 2) {
+				dec_bt_pwr = pdata[0];
+				pwr_level = pdata[1];
+
+				buf[0] = data_len;
+				buf[1] = 0x3;		/* OP_Code */
+				buf[2] = 0x2;		/* OP_Code_Length */
+
+				buf[3] = dec_bt_pwr;	/* OP_Code_Content */
+				buf[4] = pwr_level;
+				BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+					"[BTCoex], Set Dec BT power=%d, pwr_level=%d\n",
+					    dec_bt_pwr, pwr_level);
+				BTC_TRACE(trace_buf);
+				btcoexist->btc_set(btcoexist,
+						   BTC_SET_ACT_CTRL_BT_COEX,
+						   (void *)&buf[0]);
+			}
+		}
+		break;
+
+	case BTC_DBG_SET_COEX_BT_AFH_MAP:
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], Set BT AFH Map\n");
+		BTC_TRACE(trace_buf);
+		{
+			u8	data_len = 5;
+			u8	buf[6] = {0};
+
+			if (op_len == 3) {
+				buf[0] = data_len;
+				buf[1] = 0x5;				/* OP_Code */
+				buf[2] = 0x3;				/* OP_Code_Length */
+
+				buf[3] = pdata[0];			/* OP_Code_Content */
+				buf[4] = pdata[1];
+				buf[5] = pdata[2];
+
+				BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+					"[BTCoex], Set BT AFH Map = %02x %02x %02x\n",
+					    pdata[0], pdata[1], pdata[2]);
+				BTC_TRACE(trace_buf);
+				btcoexist->btc_set(btcoexist,
+						   BTC_SET_ACT_CTRL_BT_COEX,
+						   (void *)&buf[0]);
+			}
+		}
+		break;
+
+	case BTC_DBG_SET_COEX_BT_IGNORE_WLAN_ACT:
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], Set BT Ignore Wlan Active\n");
+		BTC_TRACE(trace_buf);
+		{
+			u8	data_len = 3;
+			u8	buf[6] = {0};
+
+			if (op_len == 1) {
+				buf[0] = data_len;
+				buf[1] = 0x1;			/* OP_Code */
+				buf[2] = 0x1;			/* OP_Code_Length */
+
+				buf[3] = pdata[0];		/* OP_Code_Content */
+				BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+					"[BTCoex], Set BT Ignore Wlan Active = 0x%x\n",
+					    pdata[0]);
+				BTC_TRACE(trace_buf);
+
+				btcoexist->btc_set(btcoexist,
+						   BTC_SET_ACT_CTRL_BT_COEX,
+						   (void *)&buf[0]);
+			}
+		}
+		break;
+	default:
+		break;
+	}
+}
+
+#endif
+
+#endif	/* #if (BT_SUPPORT == 1 && COEX_SUPPORT == 1) */
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/btc/halbtc8812a1ant.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/btc/halbtc8812a1ant.h
--- linux-5.6.3/3rdparty/rtl8821ce/hal/btc/halbtc8812a1ant.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/btc/halbtc8812a1ant.h	2020-04-10 16:35:06.783658527 +0300
@@ -0,0 +1,230 @@
+
+#if (BT_SUPPORT == 1 && COEX_SUPPORT == 1)
+
+#if (RTL8812A_SUPPORT == 1)
+
+/* *******************************************
+ * The following is for 8812A 1ANT BT Co-exist definition
+ * ******************************************* */
+#define	BT_AUTO_REPORT_ONLY_8812A_1ANT				1
+
+#define	BT_INFO_8812A_1ANT_B_FTP						BIT(7)
+#define	BT_INFO_8812A_1ANT_B_A2DP					BIT(6)
+#define	BT_INFO_8812A_1ANT_B_HID						BIT(5)
+#define	BT_INFO_8812A_1ANT_B_SCO_BUSY				BIT(4)
+#define	BT_INFO_8812A_1ANT_B_ACL_BUSY				BIT(3)
+#define	BT_INFO_8812A_1ANT_B_INQ_PAGE				BIT(2)
+#define	BT_INFO_8812A_1ANT_B_SCO_ESCO				BIT(1)
+#define	BT_INFO_8812A_1ANT_B_CONNECTION				BIT(0)
+
+#define	BT_INFO_8812A_1ANT_A2DP_BASIC_RATE(_BT_INFO_EXT_)	\
+		(((_BT_INFO_EXT_&BIT(0))) ? true : false)
+
+#define	BTC_RSSI_COEX_THRESH_TOL_8812A_1ANT		2
+
+#define  BT_8812A_1ANT_WIFI_NOISY_THRESH								30   /* max: 255 */
+
+enum bt_info_src_8812a_1ant {
+	BT_INFO_SRC_8812A_1ANT_WIFI_FW			= 0x0,
+	BT_INFO_SRC_8812A_1ANT_BT_RSP				= 0x1,
+	BT_INFO_SRC_8812A_1ANT_BT_ACTIVE_SEND		= 0x2,
+	BT_INFO_SRC_8812A_1ANT_MAX
+};
+
+enum bt_8812a_1ant_bt_status {
+	BT_8812A_1ANT_BT_STATUS_NON_CONNECTED_IDLE	= 0x0,
+	BT_8812A_1ANT_BT_STATUS_CONNECTED_IDLE		= 0x1,
+	BT_8812A_1ANT_BT_STATUS_INQ_PAGE				= 0x2,
+	BT_8812A_1ANT_BT_STATUS_ACL_BUSY				= 0x3,
+	BT_8812A_1ANT_BT_STATUS_SCO_BUSY				= 0x4,
+	BT_8812A_1ANT_BT_STATUS_ACL_SCO_BUSY			= 0x5,
+	BT_8812A_1ANT_BT_STATUS_MAX
+};
+
+enum bt_8812a_1ant_wifi_status {
+	BT_8812A_1ANT_WIFI_STATUS_NON_CONNECTED_IDLE				= 0x0,
+	BT_8812A_1ANT_WIFI_STATUS_NON_CONNECTED_ASSO_AUTH_SCAN		= 0x1,
+	BT_8812A_1ANT_WIFI_STATUS_CONNECTED_SCAN					= 0x2,
+	BT_8812A_1ANT_WIFI_STATUS_CONNECTED_SPECIFIC_PKT				= 0x3,
+	BT_8812A_1ANT_WIFI_STATUS_CONNECTED_IDLE					= 0x4,
+	BT_8812A_1ANT_WIFI_STATUS_CONNECTED_BUSY					= 0x5,
+	BT_8812A_1ANT_WIFI_STATUS_MAX
+};
+
+enum bt_8812a_1ant_coex_algo {
+	BT_8812A_1ANT_COEX_ALGO_UNDEFINED			= 0x0,
+	BT_8812A_1ANT_COEX_ALGO_SCO				= 0x1,
+	BT_8812A_1ANT_COEX_ALGO_HID				= 0x2,
+	BT_8812A_1ANT_COEX_ALGO_A2DP				= 0x3,
+	BT_8812A_1ANT_COEX_ALGO_A2DP_PANHS		= 0x4,
+	BT_8812A_1ANT_COEX_ALGO_PANEDR			= 0x5,
+	BT_8812A_1ANT_COEX_ALGO_PANHS			= 0x6,
+	BT_8812A_1ANT_COEX_ALGO_PANEDR_A2DP		= 0x7,
+	BT_8812A_1ANT_COEX_ALGO_PANEDR_HID		= 0x8,
+	BT_8812A_1ANT_COEX_ALGO_HID_A2DP_PANEDR	= 0x9,
+	BT_8812A_1ANT_COEX_ALGO_HID_A2DP			= 0xa,
+	BT_8812A_1ANT_COEX_ALGO_MAX				= 0xb,
+};
+
+struct coex_dm_8812a_1ant {
+	/* hw setting */
+	u8		pre_ant_pos_type;
+	u8		cur_ant_pos_type;
+	/* fw mechanism */
+	boolean		cur_ignore_wlan_act;
+	boolean		pre_ignore_wlan_act;
+	u8		pre_ps_tdma;
+	u8		cur_ps_tdma;
+	u8		ps_tdma_para[5];
+	u8		ps_tdma_du_adj_type;
+	boolean		auto_tdma_adjust;
+	boolean		pre_ps_tdma_on;
+	boolean		cur_ps_tdma_on;
+	boolean		pre_bt_auto_report;
+	boolean		cur_bt_auto_report;
+	u8		pre_lps;
+	u8		cur_lps;
+	u8		pre_rpwm;
+	u8		cur_rpwm;
+
+	/* sw mechanism */
+	boolean	pre_low_penalty_ra;
+	boolean		cur_low_penalty_ra;
+	u32		pre_val0x6c0;
+	u32		cur_val0x6c0;
+	u32		pre_val0x6c4;
+	u32		cur_val0x6c4;
+	u32		pre_val0x6c8;
+	u32		cur_val0x6c8;
+	u8		pre_val0x6cc;
+	u8		cur_val0x6cc;
+	boolean		limited_dig;
+
+	u32		backup_arfr_cnt1;	/* Auto Rate Fallback Retry cnt */
+	u32		backup_arfr_cnt2;	/* Auto Rate Fallback Retry cnt */
+	u16		backup_retry_limit;
+	u8		backup_ampdu_max_time;
+
+	/* algorithm related */
+	u8		pre_algorithm;
+	u8		cur_algorithm;
+	u8		bt_status;
+	u8		wifi_chnl_info[3];
+
+	u32		pre_ra_mask;
+	u32		cur_ra_mask;
+	u8		pre_arfr_type;
+	u8		cur_arfr_type;
+	u8		pre_retry_limit_type;
+	u8		cur_retry_limit_type;
+	u8		pre_ampdu_time_type;
+	u8		cur_ampdu_time_type;
+	u32		arp_cnt;
+
+	u8		error_condition;
+};
+
+struct coex_sta_8812a_1ant {
+	boolean					bt_disabled;
+	boolean					bt_link_exist;
+	boolean					sco_exist;
+	boolean					a2dp_exist;
+	boolean					hid_exist;
+	boolean					pan_exist;
+
+	boolean					under_lps;
+	boolean					under_ips;
+	u32					specific_pkt_period_cnt;
+	u32					high_priority_tx;
+	u32					high_priority_rx;
+	u32					low_priority_tx;
+	u32					low_priority_rx;
+	s8					bt_rssi;
+	boolean					bt_tx_rx_mask;
+	u8					pre_bt_rssi_state;
+	u8					pre_wifi_rssi_state[4];
+	boolean					c2h_bt_info_req_sent;
+	u8					bt_info_c2h[BT_INFO_SRC_8812A_1ANT_MAX][10];
+	u32					bt_info_c2h_cnt[BT_INFO_SRC_8812A_1ANT_MAX];
+	u32					bt_info_query_cnt;
+	boolean					c2h_bt_inquiry_page;
+	boolean					c2h_bt_page;				/* Add for win8.1 page out issue */
+	boolean					wifi_is_high_pri_task;		/* Add for win8.1 page out issue */
+	u8					bt_retry_cnt;
+	u8					bt_info_ext;
+	u32					pop_event_cnt;
+	u8					scan_ap_num;
+
+	u32					crc_ok_cck;
+	u32					crc_ok_11g;
+	u32					crc_ok_11n;
+	u32					crc_ok_11n_agg;
+
+	u32					crc_err_cck;
+	u32					crc_err_11g;
+	u32					crc_err_11n;
+	u32					crc_err_11n_agg;
+
+	boolean					cck_lock;
+	boolean					pre_ccklock;
+	u8					coex_table_type;
+
+	boolean					force_lps_on;
+};
+
+/* *******************************************
+ * The following is interface which will notify coex module.
+ * ******************************************* */
+void ex_halbtc8812a1ant_power_on_setting(IN struct btc_coexist *btcoexist);
+void ex_halbtc8812a1ant_pre_load_firmware(IN struct btc_coexist *btcoexist);
+void ex_halbtc8812a1ant_init_hw_config(IN struct btc_coexist *btcoexist,
+				       IN boolean wifi_only);
+void ex_halbtc8812a1ant_init_coex_dm(IN struct btc_coexist *btcoexist);
+void ex_halbtc8812a1ant_ips_notify(IN struct btc_coexist *btcoexist,
+				   IN u8 type);
+void ex_halbtc8812a1ant_lps_notify(IN struct btc_coexist *btcoexist,
+				   IN u8 type);
+void ex_halbtc8812a1ant_scan_notify(IN struct btc_coexist *btcoexist,
+				    IN u8 type);
+void ex_halbtc8812a1ant_connect_notify(IN struct btc_coexist *btcoexist,
+				       IN u8 type);
+void ex_halbtc8812a1ant_media_status_notify(IN struct btc_coexist *btcoexist,
+		IN u8 type);
+void ex_halbtc8812a1ant_specific_packet_notify(IN struct btc_coexist *btcoexist,
+		IN u8 type);
+void ex_halbtc8812a1ant_bt_info_notify(IN struct btc_coexist *btcoexist,
+				       IN u8 *tmp_buf, IN u8 length);
+void ex_halbtc8812a1ant_rf_status_notify(IN struct btc_coexist *btcoexist,
+		IN u8 type);
+void ex_halbtc8812a1ant_halt_notify(IN struct btc_coexist *btcoexist);
+void ex_halbtc8812a1ant_pnp_notify(IN struct btc_coexist *btcoexist,
+				   IN u8 pnp_state);
+void ex_halbtc8812a1ant_coex_dm_reset(IN struct btc_coexist *btcoexist);
+void ex_halbtc8812a1ant_periodical(IN struct btc_coexist *btcoexist);
+void ex_halbtc8812a1ant_dbg_control(IN struct btc_coexist *btcoexist,
+				    IN u8 op_code, IN u8 op_len, IN u8 *pdata);
+void ex_halbtc8812a1ant_display_coex_info(IN struct btc_coexist *btcoexist);
+
+#else
+#define	ex_halbtc8812a1ant_power_on_setting(btcoexist)
+#define	ex_halbtc8812a1ant_pre_load_firmware(btcoexist)
+#define	ex_halbtc8812a1ant_init_hw_config(btcoexist, wifi_only)
+#define	ex_halbtc8812a1ant_init_coex_dm(btcoexist)
+#define	ex_halbtc8812a1ant_ips_notify(btcoexist, type)
+#define	ex_halbtc8812a1ant_lps_notify(btcoexist, type)
+#define	ex_halbtc8812a1ant_scan_notify(btcoexist, type)
+#define	ex_halbtc8812a1ant_connect_notify(btcoexist, type)
+#define	ex_halbtc8812a1ant_media_status_notify(btcoexist, type)
+#define	ex_halbtc8812a1ant_specific_packet_notify(btcoexist, type)
+#define	ex_halbtc8812a1ant_bt_info_notify(btcoexist, tmp_buf, length)
+#define	ex_halbtc8812a1ant_rf_status_notify(btcoexist, type)
+#define	ex_halbtc8812a1ant_halt_notify(btcoexist)
+#define	ex_halbtc8812a1ant_pnp_notify(btcoexist, pnp_state)
+#define	ex_halbtc8812a1ant_coex_dm_reset(btcoexist)
+#define	ex_halbtc8812a1ant_periodical(btcoexist)
+#define	ex_halbtc8812a1ant_dbg_control(btcoexist, op_code, op_len, pdata)
+#define	ex_halbtc8812a1ant_display_coex_info(btcoexist)
+
+#endif
+
+#endif
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/btc/halbtc8812a2ant.c linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/btc/halbtc8812a2ant.c
--- linux-5.6.3/3rdparty/rtl8821ce/hal/btc/halbtc8812a2ant.c	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/btc/halbtc8812a2ant.c	2020-04-10 16:35:06.783658527 +0300
@@ -0,0 +1,5624 @@
+/* ************************************************************
+ * Description:
+ *
+ * This file is for RTL8812A Co-exist mechanism
+ *
+ * History
+ * 2012/08/22 Cosa first check in.
+ * 2012/11/14 Cosa Revise for 8812A 2Ant out sourcing.
+ *
+ * ************************************************************ */
+
+/* ************************************************************
+ * include files
+ * ************************************************************ */
+#include "mp_precomp.h"
+
+#if (BT_SUPPORT == 1 && COEX_SUPPORT == 1)
+
+
+#if (RTL8812A_SUPPORT == 1)
+/* ************************************************************
+ * Global variables, these are static variables
+ * ************************************************************ */
+static u8	 *trace_buf = &gl_btc_trace_buf[0];
+static struct  coex_dm_8812a_2ant	glcoex_dm_8812a_2ant;
+static struct  coex_dm_8812a_2ant	*coex_dm = &glcoex_dm_8812a_2ant;
+static struct  coex_sta_8812a_2ant	glcoex_sta_8812a_2ant;
+static struct  coex_sta_8812a_2ant	*coex_sta = &glcoex_sta_8812a_2ant;
+
+const char *const glbt_info_src_8812a_2ant[] = {
+	"BT Info[wifi fw]",
+	"BT Info[bt rsp]",
+	"BT Info[bt auto report]",
+};
+/* ************************************************************
+ * BtCoex Version Format:
+ * 1. date :			glcoex_ver_date_XXXXX_1ant
+ * 2. WifiCoexVersion : glcoex_ver_XXXX_1ant
+ * 3. BtCoexVersion :	glcoex_ver_btdesired_XXXXX_1ant
+ * 4. others :			glcoex_ver_XXXXXX_XXXXX_1ant
+ *
+ * Variable should be indicated IC and Antenna numbers !!!
+ * Please strictly follow this order and naming style !!!
+ *
+ * ************************************************************ */
+u32	glcoex_ver_date_8812a_2ant = 20160818;
+u32	glcoex_ver_8812a_2ant = 0x3c;
+u32	glcoex_ver_btdesired_8812a_2ant = 0x3c;
+/*1. add coex. log for wifi/BT coex. version*/
+
+/* ************************************************************
+* local function proto type if needed
+* ************************************************************
+* ************************************************************
+* local function start with halbtc8812a2ant_
+* ************************************************************ */
+u8 halbtc8812a2ant_bt_rssi_state(u8 level_num, u8 rssi_thresh, u8 rssi_thresh1)
+{
+	s32			bt_rssi = 0;
+	u8			bt_rssi_state = coex_sta->pre_bt_rssi_state;
+
+	bt_rssi = coex_sta->bt_rssi;
+
+	if (level_num == 2) {
+		if ((coex_sta->pre_bt_rssi_state == BTC_RSSI_STATE_LOW) ||
+		    (coex_sta->pre_bt_rssi_state ==
+		     BTC_RSSI_STATE_STAY_LOW)) {
+			if (bt_rssi >= (rssi_thresh +
+					BTC_RSSI_COEX_THRESH_TOL_8812A_2ANT))
+				bt_rssi_state = BTC_RSSI_STATE_HIGH;
+			else
+				bt_rssi_state = BTC_RSSI_STATE_STAY_LOW;
+		} else {
+			if (bt_rssi < rssi_thresh)
+				bt_rssi_state = BTC_RSSI_STATE_LOW;
+			else
+				bt_rssi_state = BTC_RSSI_STATE_STAY_HIGH;
+		}
+	} else if (level_num == 3) {
+		if (rssi_thresh > rssi_thresh1) {
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				    "[BTCoex], BT Rssi thresh error!!\n");
+			BTC_TRACE(trace_buf);
+			return coex_sta->pre_bt_rssi_state;
+		}
+
+		if ((coex_sta->pre_bt_rssi_state == BTC_RSSI_STATE_LOW) ||
+		    (coex_sta->pre_bt_rssi_state ==
+		     BTC_RSSI_STATE_STAY_LOW)) {
+			if (bt_rssi >= (rssi_thresh +
+					BTC_RSSI_COEX_THRESH_TOL_8812A_2ANT))
+				bt_rssi_state = BTC_RSSI_STATE_MEDIUM;
+			else
+				bt_rssi_state = BTC_RSSI_STATE_STAY_LOW;
+		} else if ((coex_sta->pre_bt_rssi_state ==
+			    BTC_RSSI_STATE_MEDIUM) ||
+			   (coex_sta->pre_bt_rssi_state ==
+			    BTC_RSSI_STATE_STAY_MEDIUM)) {
+			if (bt_rssi >= (rssi_thresh1 +
+					BTC_RSSI_COEX_THRESH_TOL_8812A_2ANT))
+				bt_rssi_state = BTC_RSSI_STATE_HIGH;
+			else if (bt_rssi < rssi_thresh)
+				bt_rssi_state = BTC_RSSI_STATE_LOW;
+			else
+				bt_rssi_state = BTC_RSSI_STATE_STAY_MEDIUM;
+		} else {
+			if (bt_rssi < rssi_thresh1)
+				bt_rssi_state = BTC_RSSI_STATE_MEDIUM;
+			else
+				bt_rssi_state = BTC_RSSI_STATE_STAY_HIGH;
+		}
+	}
+
+	coex_sta->pre_bt_rssi_state = bt_rssi_state;
+
+	return bt_rssi_state;
+}
+
+
+u8 halbtc8812a2ant_wifi_rssi_state(IN struct btc_coexist *btcoexist,
+	   IN u8 index, IN u8 level_num, IN u8 rssi_thresh, IN u8 rssi_thresh1)
+{
+	s32			wifi_rssi = 0;
+	u8			wifi_rssi_state = coex_sta->pre_wifi_rssi_state[index];
+
+	btcoexist->btc_get(btcoexist, BTC_GET_S4_WIFI_RSSI, &wifi_rssi);
+
+	if (level_num == 2) {
+		if ((coex_sta->pre_wifi_rssi_state[index] == BTC_RSSI_STATE_LOW)
+		    ||
+		    (coex_sta->pre_wifi_rssi_state[index] ==
+		     BTC_RSSI_STATE_STAY_LOW)) {
+			if (wifi_rssi >= (rssi_thresh +
+					  BTC_RSSI_COEX_THRESH_TOL_8812A_2ANT))
+				wifi_rssi_state = BTC_RSSI_STATE_HIGH;
+			else
+				wifi_rssi_state = BTC_RSSI_STATE_STAY_LOW;
+		} else {
+			if (wifi_rssi < rssi_thresh)
+				wifi_rssi_state = BTC_RSSI_STATE_LOW;
+			else
+				wifi_rssi_state = BTC_RSSI_STATE_STAY_HIGH;
+		}
+	} else if (level_num == 3) {
+		if (rssi_thresh > rssi_thresh1) {
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				    "[BTCoex], wifi RSSI thresh error!!\n");
+			BTC_TRACE(trace_buf);
+			return coex_sta->pre_wifi_rssi_state[index];
+		}
+
+		if ((coex_sta->pre_wifi_rssi_state[index] == BTC_RSSI_STATE_LOW)
+		    ||
+		    (coex_sta->pre_wifi_rssi_state[index] ==
+		     BTC_RSSI_STATE_STAY_LOW)) {
+			if (wifi_rssi >= (rssi_thresh +
+					  BTC_RSSI_COEX_THRESH_TOL_8812A_2ANT))
+				wifi_rssi_state = BTC_RSSI_STATE_MEDIUM;
+			else
+				wifi_rssi_state = BTC_RSSI_STATE_STAY_LOW;
+		} else if ((coex_sta->pre_wifi_rssi_state[index] ==
+			    BTC_RSSI_STATE_MEDIUM) ||
+			   (coex_sta->pre_wifi_rssi_state[index] ==
+			    BTC_RSSI_STATE_STAY_MEDIUM)) {
+			if (wifi_rssi >= (rssi_thresh1 +
+					  BTC_RSSI_COEX_THRESH_TOL_8812A_2ANT))
+				wifi_rssi_state = BTC_RSSI_STATE_HIGH;
+			else if (wifi_rssi < rssi_thresh)
+				wifi_rssi_state = BTC_RSSI_STATE_LOW;
+			else
+				wifi_rssi_state = BTC_RSSI_STATE_STAY_MEDIUM;
+		} else {
+			if (wifi_rssi < rssi_thresh1)
+				wifi_rssi_state = BTC_RSSI_STATE_MEDIUM;
+			else
+				wifi_rssi_state = BTC_RSSI_STATE_STAY_HIGH;
+		}
+	}
+
+	coex_sta->pre_wifi_rssi_state[index] = wifi_rssi_state;
+
+	return wifi_rssi_state;
+}
+
+
+void halbtc8812a2ant_set_enable_pta(IN struct btc_coexist *btcoexist,
+				    IN boolean enablePTA)
+{
+	if (enablePTA) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], PTA is enable!\n");
+		BTC_TRACE(trace_buf);
+		btcoexist->btc_write_1byte(btcoexist, 0x40, 0x20);
+
+	} else {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], PTA is disable!\n");
+		BTC_TRACE(trace_buf);
+		btcoexist->btc_write_1byte(btcoexist, 0x40, 0x00);
+
+	}
+}
+
+void halbtc8812a2ant_enable_pta(IN struct btc_coexist *btcoexist,
+				IN boolean force_exec, IN boolean enable)
+{
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+		    "[BTCoex], %s turn Enable PTA %s\n",
+		    (force_exec ? "force to" : ""), (enable ? "ON" : "OFF"));
+	BTC_TRACE(trace_buf);
+	coex_dm->cur_enable_pta = enable;
+
+	if (!force_exec) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			"[BTCoex], pre_enable_pta = %d, cur_enable_pta = %d!!\n",
+			    coex_dm->pre_enable_pta, coex_dm->cur_enable_pta);
+		BTC_TRACE(trace_buf);
+
+		if (coex_dm->pre_enable_pta == coex_dm->cur_enable_pta)
+			return;
+	}
+	halbtc8812a2ant_set_enable_pta(btcoexist, enable);
+
+
+	coex_dm->pre_enable_pta = coex_dm->cur_enable_pta;
+}
+
+u32 halbtc8812a2ant_decide_ra_mask(IN struct btc_coexist *btcoexist,
+				   IN u32 ra_mask_type)
+{
+	u32	dis_ra_mask = 0x0;
+
+	switch (ra_mask_type) {
+	case 0: /* normal mode */
+		dis_ra_mask = 0x0;
+		break;
+	case 1: /* disable cck 1/2 */
+		dis_ra_mask = 0x00000003;
+		break;
+	case 2: /* disable cck 1/2/5.5, ofdm 6/9/12/18/24, mcs 0/1/2/3/4			 */
+		dis_ra_mask = 0x0001f1f7;
+		break;
+	default:
+		break;
+	}
+
+	return dis_ra_mask;
+}
+
+void halbtc8812a2ant_update_ra_mask(IN struct btc_coexist *btcoexist,
+				    IN boolean force_exec, IN u32 dis_rate_mask)
+{
+	coex_dm->cur_ra_mask = dis_rate_mask;
+
+	if (force_exec || (coex_dm->pre_ra_mask != coex_dm->cur_ra_mask))
+		btcoexist->btc_set(btcoexist, BTC_SET_ACT_UPDATE_RAMASK,
+				   &coex_dm->cur_ra_mask);
+	coex_dm->pre_ra_mask = coex_dm->cur_ra_mask;
+}
+
+void halbtc8812a2ant_auto_rate_fallback_retry(IN struct btc_coexist *btcoexist,
+		IN boolean force_exec, IN u8 type)
+{
+	boolean	wifi_under_b_mode = false;
+
+	coex_dm->cur_arfr_type = type;
+
+	if (force_exec || (coex_dm->pre_arfr_type != coex_dm->cur_arfr_type)) {
+		switch (coex_dm->cur_arfr_type) {
+		case 0:	/* normal mode */
+			btcoexist->btc_write_4byte(btcoexist, 0x430,
+						   coex_dm->backup_arfr_cnt1);
+			btcoexist->btc_write_4byte(btcoexist, 0x434,
+						   coex_dm->backup_arfr_cnt2);
+			break;
+		case 1:
+			btcoexist->btc_get(btcoexist,
+					   BTC_GET_BL_WIFI_UNDER_B_MODE,
+					   &wifi_under_b_mode);
+			if (wifi_under_b_mode) {
+				btcoexist->btc_write_4byte(btcoexist,
+							   0x430, 0x0);
+				btcoexist->btc_write_4byte(btcoexist,
+							   0x434, 0x01010101);
+			} else {
+				btcoexist->btc_write_4byte(btcoexist,
+							   0x430, 0x0);
+				btcoexist->btc_write_4byte(btcoexist,
+							   0x434, 0x04030201);
+			}
+			break;
+		default:
+			break;
+		}
+	}
+
+	coex_dm->pre_arfr_type = coex_dm->cur_arfr_type;
+}
+
+void halbtc8812a2ant_retry_limit(IN struct btc_coexist *btcoexist,
+				 IN boolean force_exec, IN u8 type)
+{
+	coex_dm->cur_retry_limit_type = type;
+
+	if (force_exec ||
+	    (coex_dm->pre_retry_limit_type !=
+	     coex_dm->cur_retry_limit_type)) {
+		switch (coex_dm->cur_retry_limit_type) {
+		case 0:	/* normal mode */
+			btcoexist->btc_write_2byte(btcoexist, 0x42a,
+						   coex_dm->backup_retry_limit);
+			break;
+		case 1:	/* retry limit=8 */
+			btcoexist->btc_write_2byte(btcoexist, 0x42a,
+						   0x0808);
+			break;
+		default:
+			break;
+		}
+	}
+
+	coex_dm->pre_retry_limit_type = coex_dm->cur_retry_limit_type;
+}
+
+void halbtc8812a2ant_ampdu_max_time(IN struct btc_coexist *btcoexist,
+				    IN boolean force_exec, IN u8 type)
+{
+	coex_dm->cur_ampdu_time_type = type;
+
+	if (force_exec ||
+	    (coex_dm->pre_ampdu_time_type != coex_dm->cur_ampdu_time_type)) {
+		switch (coex_dm->cur_ampdu_time_type) {
+		case 0:	/* normal mode */
+			btcoexist->btc_write_1byte(btcoexist, 0x456,
+					   coex_dm->backup_ampdu_max_time);
+			break;
+		case 1:	/* AMPDU timw = 0x38 * 32us */
+			btcoexist->btc_write_1byte(btcoexist, 0x456,
+						   0x38);
+			break;
+		default:
+			break;
+		}
+	}
+
+	coex_dm->pre_ampdu_time_type = coex_dm->cur_ampdu_time_type;
+}
+
+void halbtc8812a2ant_limited_tx(IN struct btc_coexist *btcoexist,
+		IN boolean force_exec, IN u8 ra_mask_type, IN u8 arfr_type,
+				IN u8 retry_limit_type, IN u8 ampdu_time_type)
+{
+	u32	dis_ra_mask = 0x0;
+
+	coex_dm->cur_ra_mask_type = ra_mask_type;
+	dis_ra_mask = halbtc8812a2ant_decide_ra_mask(btcoexist, ra_mask_type);
+	halbtc8812a2ant_update_ra_mask(btcoexist, force_exec, dis_ra_mask);
+
+	halbtc8812a2ant_auto_rate_fallback_retry(btcoexist, force_exec,
+			arfr_type);
+	halbtc8812a2ant_retry_limit(btcoexist, force_exec, retry_limit_type);
+	halbtc8812a2ant_ampdu_max_time(btcoexist, force_exec, ampdu_time_type);
+}
+
+void halbtc8812a2ant_limited_rx(IN struct btc_coexist *btcoexist,
+			IN boolean force_exec, IN boolean rej_ap_agg_pkt,
+			IN boolean bt_ctrl_agg_buf_size, IN u8 agg_buf_size)
+{
+	boolean	reject_rx_agg = rej_ap_agg_pkt;
+	boolean	bt_ctrl_rx_agg_size = bt_ctrl_agg_buf_size;
+	u8	rx_agg_size = agg_buf_size;
+
+	/* ============================================ */
+	/*	Rx Aggregation related setting */
+	/* ============================================ */
+	btcoexist->btc_set(btcoexist, BTC_SET_BL_TO_REJ_AP_AGG_PKT,
+			   &reject_rx_agg);
+	/* decide BT control aggregation buf size or not */
+	btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_CTRL_AGG_SIZE,
+			   &bt_ctrl_rx_agg_size);
+	/* aggregation buf size, only work when BT control Rx aggregation size. */
+	btcoexist->btc_set(btcoexist, BTC_SET_U1_AGG_BUF_SIZE, &rx_agg_size);
+	/* real update aggregation setting */
+	btcoexist->btc_set(btcoexist, BTC_SET_ACT_AGGREGATE_CTRL, NULL);
+
+
+}
+
+void halbtc8812a2ant_monitor_bt_ctr(IN struct btc_coexist *btcoexist)
+{
+	u32			reg_hp_txrx, reg_lp_txrx, u32tmp;
+	u32			reg_hp_tx = 0, reg_hp_rx = 0, reg_lp_tx = 0, reg_lp_rx = 0;
+
+	reg_hp_txrx = 0x770;
+	reg_lp_txrx = 0x774;
+
+	u32tmp = btcoexist->btc_read_4byte(btcoexist, reg_hp_txrx);
+	reg_hp_tx = u32tmp & MASKLWORD;
+	reg_hp_rx = (u32tmp & MASKHWORD) >> 16;
+
+	u32tmp = btcoexist->btc_read_4byte(btcoexist, reg_lp_txrx);
+	reg_lp_tx = u32tmp & MASKLWORD;
+	reg_lp_rx = (u32tmp & MASKHWORD) >> 16;
+
+	coex_sta->high_priority_tx = reg_hp_tx;
+	coex_sta->high_priority_rx = reg_hp_rx;
+	coex_sta->low_priority_tx = reg_lp_tx;
+	coex_sta->low_priority_rx = reg_lp_rx;
+
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+		"[BTCoex], High Priority Tx/Rx (reg 0x%x)=0x%x(%d)/0x%x(%d)\n",
+		    reg_hp_txrx, reg_hp_tx, reg_hp_tx, reg_hp_rx, reg_hp_rx);
+	BTC_TRACE(trace_buf);
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+		"[BTCoex], Low Priority Tx/Rx (reg 0x%x)=0x%x(%d)/0x%x(%d)\n",
+		    reg_lp_txrx, reg_lp_tx, reg_lp_tx, reg_lp_rx, reg_lp_rx);
+	BTC_TRACE(trace_buf);
+
+	/* reset counter */
+	btcoexist->btc_write_1byte(btcoexist, 0x76e, 0xc);
+}
+
+
+void halbtc8812a2ant_monitor_wifi_ctr(IN struct btc_coexist *btcoexist)
+{
+#if 1
+
+	coex_sta->crc_ok_cck =
+		btcoexist->btc_phydm_query_PHY_counter(
+			btcoexist,
+			PHYDM_INFO_CRC32_OK_CCK);
+	coex_sta->crc_ok_11g =
+		btcoexist->btc_phydm_query_PHY_counter(
+			btcoexist,
+			PHYDM_INFO_CRC32_OK_LEGACY);
+	coex_sta->crc_ok_11n =
+		btcoexist->btc_phydm_query_PHY_counter(
+			btcoexist,
+			PHYDM_INFO_CRC32_OK_HT);
+	coex_sta->crc_ok_11n_vht =
+		btcoexist->btc_phydm_query_PHY_counter(
+			btcoexist,
+			PHYDM_INFO_CRC32_OK_VHT);
+
+	coex_sta->crc_err_cck =
+		btcoexist->btc_phydm_query_PHY_counter(
+			btcoexist,
+			PHYDM_INFO_CRC32_ERROR_CCK);
+	coex_sta->crc_err_11g =
+		btcoexist->btc_phydm_query_PHY_counter(
+			btcoexist,
+			PHYDM_INFO_CRC32_ERROR_LEGACY);
+	coex_sta->crc_err_11n =
+		btcoexist->btc_phydm_query_PHY_counter(
+			btcoexist,
+			PHYDM_INFO_CRC32_ERROR_HT);
+	coex_sta->crc_err_11n_vht =
+		btcoexist->btc_phydm_query_PHY_counter(
+			btcoexist,
+			PHYDM_INFO_CRC32_ERROR_VHT);
+#endif
+}
+
+
+void halbtc8812a2ant_query_bt_info(IN struct btc_coexist *btcoexist)
+{
+	u8	data_len = 3;
+	u8	buf[5] = {0};
+	/* 8812a watch btifo to check BT enable/disable
+	 *	if(!btcoexist->bt_info.bt_disabled) */
+	{
+		if (!coex_sta->bt_info_query_cnt ||
+		    (coex_sta->bt_info_c2h_cnt[BT_INFO_SRC_8812A_2ANT_BT_RSP]
+		     - coex_sta->bt_info_query_cnt) > 2) {
+			buf[0] = data_len;
+			buf[1] = 0x1;	/* polling enable, 1=enable, 0=disable */
+			buf[2] = 0x2;	/* polling time in seconds */
+			buf[3] = 0x1;	/* auto report enable, 1=enable, 0=disable */
+
+			btcoexist->btc_set(btcoexist, BTC_SET_ACT_CTRL_BT_INFO,
+					   (void *)&buf[0]);
+		}
+	}
+	coex_sta->bt_info_query_cnt++;
+}
+
+boolean halbtc8812a2ant_is_wifi_status_changed(IN struct btc_coexist *btcoexist)
+{
+	static boolean	pre_wifi_busy = false, pre_under_4way = false,
+			pre_bt_hs_on = false;
+	boolean	wifi_busy = false, under_4way = false, bt_hs_on = false;
+	boolean	wifi_connected = false;
+
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED,
+			   &wifi_connected);
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy);
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on);
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_4_WAY_PROGRESS,
+			   &under_4way);
+
+	if (wifi_connected) {
+		if (wifi_busy != pre_wifi_busy) {
+			pre_wifi_busy = wifi_busy;
+			return true;
+		}
+		if (under_4way != pre_under_4way) {
+			pre_under_4way = under_4way;
+			return true;
+		}
+		if (bt_hs_on != pre_bt_hs_on) {
+			pre_bt_hs_on = bt_hs_on;
+			return true;
+		}
+	}
+
+	return false;
+}
+
+void halbtc8812a2ant_update_bt_link_info(IN struct btc_coexist *btcoexist)
+{
+	struct  btc_bt_link_info	*bt_link_info = &btcoexist->bt_link_info;
+	boolean				bt_hs_on = false;
+
+#if 1/* (BT_AUTO_REPORT_ONLY_8812A_2ANT == 1)	/ profile from bt patch */
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on);
+
+	bt_link_info->bt_link_exist = coex_sta->bt_link_exist;
+	bt_link_info->sco_exist = coex_sta->sco_exist;
+	bt_link_info->a2dp_exist = coex_sta->a2dp_exist;
+	bt_link_info->pan_exist = coex_sta->pan_exist;
+	bt_link_info->hid_exist = coex_sta->hid_exist;
+	bt_link_info->acl_busy = coex_sta->acl_busy;
+
+	/* work around for HS mode. */
+	if (bt_hs_on) {
+		bt_link_info->pan_exist = true;
+		bt_link_info->bt_link_exist = true;
+	}
+#else	/* profile from bt stack */
+	bt_link_info->bt_link_exist = stack_info->bt_link_exist;
+	bt_link_info->sco_exist = stack_info->sco_exist;
+	bt_link_info->a2dp_exist = stack_info->a2dp_exist;
+	bt_link_info->pan_exist = stack_info->pan_exist;
+	bt_link_info->hid_exist = stack_info->hid_exist;
+
+	/* for win-8 stack HID report error */
+	if (!stack_info->hid_exist)
+		stack_info->hid_exist =
+			coex_sta->hid_exist;  /* sync  BTInfo with BT firmware and stack */
+	/* when stack HID report error, here we use the info from bt fw. */
+	if (!stack_info->bt_link_exist)
+		stack_info->bt_link_exist = coex_sta->bt_link_exist;
+#endif
+	/* check if Sco only */
+	if (bt_link_info->sco_exist &&
+	    !bt_link_info->a2dp_exist &&
+	    !bt_link_info->pan_exist &&
+	    !bt_link_info->hid_exist)
+		bt_link_info->sco_only = true;
+	else
+		bt_link_info->sco_only = false;
+
+	/* check if A2dp only */
+	if (!bt_link_info->sco_exist &&
+	    bt_link_info->a2dp_exist &&
+	    !bt_link_info->pan_exist &&
+	    !bt_link_info->hid_exist)
+		bt_link_info->a2dp_only = true;
+	else
+		bt_link_info->a2dp_only = false;
+
+	/* check if Pan only */
+	if (!bt_link_info->sco_exist &&
+	    !bt_link_info->a2dp_exist &&
+	    bt_link_info->pan_exist &&
+	    !bt_link_info->hid_exist)
+		bt_link_info->pan_only = true;
+	else
+		bt_link_info->pan_only = false;
+
+	/* check if Hid only */
+	if (!bt_link_info->sco_exist &&
+	    !bt_link_info->a2dp_exist &&
+	    !bt_link_info->pan_exist &&
+	    bt_link_info->hid_exist)
+		bt_link_info->hid_only = true;
+	else
+		bt_link_info->hid_only = false;
+}
+
+u8 halbtc8812a2ant_action_algorithm(IN struct btc_coexist *btcoexist)
+{
+	struct  btc_bt_link_info	*bt_link_info = &btcoexist->bt_link_info;
+	struct  btc_stack_info	*stack_info = &btcoexist->stack_info;
+	boolean				bt_hs_on = false;
+	u8				algorithm = BT_8812A_2ANT_COEX_ALGO_UNDEFINED;
+	u8				num_of_diff_profile = 0;
+
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on);
+
+	if (!bt_link_info->bt_link_exist) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], No BT link exists!!!\n");
+		BTC_TRACE(trace_buf);
+		return algorithm;
+	}
+
+	if (bt_link_info->sco_exist)
+		num_of_diff_profile++;
+	if (bt_link_info->hid_exist)
+		num_of_diff_profile++;
+	if (bt_link_info->pan_exist)
+		num_of_diff_profile++;
+	if (bt_link_info->a2dp_exist)
+		num_of_diff_profile++;
+
+	if (num_of_diff_profile == 0) {
+		if (bt_link_info->acl_busy) {
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				    "[BTCoex], ACL Busy only\n");
+			BTC_TRACE(trace_buf);
+			algorithm = BT_8812A_2ANT_COEX_ALGO_PANEDR;
+		}
+	} else if (num_of_diff_profile == 1) {
+		if (bt_link_info->sco_exist) {
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				    "[BTCoex], SCO only\n");
+			BTC_TRACE(trace_buf);
+			algorithm = BT_8812A_2ANT_COEX_ALGO_SCO;
+		} else {
+			if (bt_link_info->hid_exist) {
+				BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+					    "[BTCoex], HID only\n");
+				BTC_TRACE(trace_buf);
+				algorithm = BT_8812A_2ANT_COEX_ALGO_HID;
+			} else if (bt_link_info->a2dp_exist) {
+				BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+					    "[BTCoex], A2DP only\n");
+				BTC_TRACE(trace_buf);
+				algorithm = BT_8812A_2ANT_COEX_ALGO_A2DP;
+			} else if (bt_link_info->pan_exist) {
+				if (bt_hs_on) {
+					BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+						    "[BTCoex], PAN(HS) only\n");
+					BTC_TRACE(trace_buf);
+					algorithm =
+						BT_8812A_2ANT_COEX_ALGO_PANHS;
+				} else {
+					BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+						"[BTCoex], PAN(EDR) only\n");
+					BTC_TRACE(trace_buf);
+					algorithm =
+						BT_8812A_2ANT_COEX_ALGO_PANEDR;
+				}
+			}
+		}
+	} else if (num_of_diff_profile == 2) {
+		if (bt_link_info->sco_exist) {
+			if (bt_link_info->hid_exist) {
+				BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+					    "[BTCoex], SCO + HID\n");
+				BTC_TRACE(trace_buf);
+				algorithm = BT_8812A_2ANT_COEX_ALGO_SCO_HID;
+			} else if (bt_link_info->a2dp_exist) {
+				BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+					    "[BTCoex], SCO + A2DP ==> SCO\n");
+				BTC_TRACE(trace_buf);
+				algorithm = BT_8812A_2ANT_COEX_ALGO_PANEDR_HID;
+			} else if (bt_link_info->pan_exist) {
+				if (bt_hs_on) {
+					BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+						"[BTCoex], SCO + PAN(HS)\n");
+					BTC_TRACE(trace_buf);
+					algorithm = BT_8812A_2ANT_COEX_ALGO_SCO;
+				} else {
+					BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+						"[BTCoex], SCO + PAN(EDR)\n");
+					BTC_TRACE(trace_buf);
+					algorithm = BT_8812A_2ANT_COEX_ALGO_SCO;
+				}
+			}
+		} else {
+			if (bt_link_info->hid_exist &&
+			    bt_link_info->a2dp_exist) {
+				if (stack_info->num_of_hid >= 2) {
+					BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+						    "[BTCoex], HID*2 + A2DP\n");
+					BTC_TRACE(trace_buf);
+					algorithm =
+						BT_8812A_2ANT_COEX_ALGO_HID_A2DP_PANEDR;
+				} else {
+					BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+						    "[BTCoex], HID + A2DP\n");
+					BTC_TRACE(trace_buf);
+					algorithm =
+						BT_8812A_2ANT_COEX_ALGO_HID_A2DP;
+				}
+			} else if (bt_link_info->hid_exist &&
+				   bt_link_info->pan_exist) {
+				if (bt_hs_on) {
+					BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+						"[BTCoex], HID + PAN(HS)\n");
+					BTC_TRACE(trace_buf);
+					algorithm =
+						BT_8812A_2ANT_COEX_ALGO_HID;
+				} else {
+					BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+						"[BTCoex], HID + PAN(EDR)\n");
+					BTC_TRACE(trace_buf);
+					algorithm =
+						BT_8812A_2ANT_COEX_ALGO_PANEDR_HID;
+				}
+			} else if (bt_link_info->pan_exist &&
+				   bt_link_info->a2dp_exist) {
+				if (bt_hs_on) {
+					BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+						"[BTCoex], A2DP + PAN(HS)\n");
+					BTC_TRACE(trace_buf);
+					algorithm =
+						BT_8812A_2ANT_COEX_ALGO_A2DP_PANHS;
+				} else {
+					BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+						"[BTCoex], A2DP + PAN(EDR)\n");
+					BTC_TRACE(trace_buf);
+					algorithm =
+						BT_8812A_2ANT_COEX_ALGO_PANEDR_A2DP;
+				}
+			}
+		}
+	} else if (num_of_diff_profile == 3) {
+		if (bt_link_info->sco_exist) {
+			if (bt_link_info->hid_exist &&
+			    bt_link_info->a2dp_exist) {
+				BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+					"[BTCoex], SCO + HID + A2DP ==> HID\n");
+				BTC_TRACE(trace_buf);
+				algorithm = BT_8812A_2ANT_COEX_ALGO_PANEDR_HID;
+			} else if (bt_link_info->hid_exist &&
+				   bt_link_info->pan_exist) {
+				if (bt_hs_on) {
+					BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+						"[BTCoex], SCO + HID + PAN(HS)\n");
+					BTC_TRACE(trace_buf);
+					algorithm =
+						BT_8812A_2ANT_COEX_ALGO_SCO_HID;
+				} else {
+					BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+						"[BTCoex], SCO + HID + PAN(EDR)\n");
+					BTC_TRACE(trace_buf);
+					algorithm =
+						BT_8812A_2ANT_COEX_ALGO_SCO_HID;
+				}
+			} else if (bt_link_info->pan_exist &&
+				   bt_link_info->a2dp_exist) {
+				if (bt_hs_on) {
+					BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+						"[BTCoex], SCO + A2DP + PAN(HS)\n");
+					BTC_TRACE(trace_buf);
+					algorithm = BT_8812A_2ANT_COEX_ALGO_SCO;
+				} else {
+					BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+						"[BTCoex], SCO + A2DP + PAN(EDR) ==> HID\n");
+					BTC_TRACE(trace_buf);
+					algorithm =
+						BT_8812A_2ANT_COEX_ALGO_PANEDR_HID;
+				}
+			}
+		} else {
+			if (bt_link_info->hid_exist &&
+			    bt_link_info->pan_exist &&
+			    bt_link_info->a2dp_exist) {
+				if (bt_hs_on) {
+					BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+						"[BTCoex], HID + A2DP + PAN(HS)\n");
+					BTC_TRACE(trace_buf);
+					algorithm =
+						BT_8812A_2ANT_COEX_ALGO_HID_A2DP_PANHS;
+				} else {
+					BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+						"[BTCoex], HID + A2DP + PAN(EDR)\n");
+					BTC_TRACE(trace_buf);
+					algorithm =
+						BT_8812A_2ANT_COEX_ALGO_HID_A2DP_PANEDR;
+				}
+			}
+		}
+	} else if (num_of_diff_profile >= 3) {
+		if (bt_link_info->sco_exist) {
+			if (bt_link_info->hid_exist &&
+			    bt_link_info->pan_exist &&
+			    bt_link_info->a2dp_exist) {
+				if (bt_hs_on) {
+					BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+						"[BTCoex], Error!!! SCO + HID + A2DP + PAN(HS)\n");
+					BTC_TRACE(trace_buf);
+				} else {
+					BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+						"[BTCoex], SCO + HID + A2DP + PAN(EDR)==>PAN(EDR)+HID\n");
+					BTC_TRACE(trace_buf);
+					algorithm =
+						BT_8812A_2ANT_COEX_ALGO_PANEDR_HID;
+				}
+			}
+		}
+	}
+
+	return algorithm;
+}
+
+void halbtc8812a2ant_set_fw_dac_swing_level(IN struct btc_coexist *btcoexist,
+		IN u8 dac_swing_lvl)
+{
+	u8			h2c_parameter[1] = {0};
+
+	/* There are several type of dacswing */
+	/* 0x18/ 0x10/ 0xc/ 0x8/ 0x4/ 0x6 */
+	h2c_parameter[0] = dac_swing_lvl;
+
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+		    "[BTCoex], Set Dac Swing Level=0x%x\n",
+		    dac_swing_lvl);
+	BTC_TRACE(trace_buf);
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+		    "[BTCoex], FW write 0x64=0x%x\n",
+		    h2c_parameter[0]);
+	BTC_TRACE(trace_buf);
+
+	btcoexist->btc_fill_h2c(btcoexist, 0x64, 1, h2c_parameter);
+}
+
+void halbtc8812a2ant_set_fw_dec_bt_pwr(IN struct btc_coexist *btcoexist,
+				       IN u8 dec_bt_pwr_lvl)
+{
+	u8	data_len = 4;
+	u8	buf[6] = {0};
+
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+		    "[BTCoex], decrease Bt Power level = %d\n",
+		    dec_bt_pwr_lvl);
+	BTC_TRACE(trace_buf);
+
+	buf[0] = data_len;
+	buf[1] = 0x3;		/* OP_Code */
+	buf[2] = 0x2;		/* OP_Code_Length */
+	if (dec_bt_pwr_lvl)
+		buf[3] = 0x1;	/* OP_Code_Content */
+	else
+		buf[3] = 0x0;
+	buf[4] = dec_bt_pwr_lvl;/* pwr_level */
+
+	btcoexist->btc_set(btcoexist, BTC_SET_ACT_CTRL_BT_COEX,
+			   (void *)&buf[0]);
+}
+
+void halbtc8812a2ant_dec_bt_pwr(IN struct btc_coexist *btcoexist,
+				IN boolean force_exec, IN u8 dec_bt_pwr_lvl)
+{
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+		    "[BTCoex], %s Dec BT power level = %d\n",
+		    (force_exec ? "force to" : ""), dec_bt_pwr_lvl);
+	BTC_TRACE(trace_buf);
+
+	coex_dm->cur_bt_dec_pwr_lvl = dec_bt_pwr_lvl;
+
+	if (!force_exec) {
+		if (coex_dm->pre_bt_dec_pwr_lvl == coex_dm->cur_bt_dec_pwr_lvl)
+			return;
+	}
+	halbtc8812a2ant_set_fw_dec_bt_pwr(btcoexist,
+					  coex_dm->cur_bt_dec_pwr_lvl);
+
+	coex_dm->pre_bt_dec_pwr_lvl = coex_dm->cur_bt_dec_pwr_lvl;
+}
+
+void halbtc8812a2ant_fw_dac_swing_lvl(IN struct btc_coexist *btcoexist,
+			      IN boolean force_exec, IN u8 fw_dac_swing_lvl)
+{
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+		    "[BTCoex], %s set FW Dac Swing level = %d\n",
+		    (force_exec ? "force to" : ""), fw_dac_swing_lvl);
+	BTC_TRACE(trace_buf);
+	coex_dm->cur_fw_dac_swing_lvl = fw_dac_swing_lvl;
+
+	if (!force_exec) {
+		if (coex_dm->pre_fw_dac_swing_lvl ==
+		    coex_dm->cur_fw_dac_swing_lvl)
+			return;
+	}
+
+	halbtc8812a2ant_set_fw_dac_swing_level(btcoexist,
+					       coex_dm->cur_fw_dac_swing_lvl);
+
+	coex_dm->pre_fw_dac_swing_lvl = coex_dm->cur_fw_dac_swing_lvl;
+}
+
+void halbtc8812a2ant_set_sw_rf_rx_lpf_corner(IN struct btc_coexist *btcoexist,
+		IN boolean rx_rf_shrink_on)
+{
+	if (rx_rf_shrink_on) {
+		/* Shrink RF Rx LPF corner */
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], Shrink RF Rx LPF corner!!\n");
+		BTC_TRACE(trace_buf);
+		btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1e, 0xfffff,
+					  0xffffc);
+	} else {
+		/* Resume RF Rx LPF corner */
+		/* After initialized, we can use coex_dm->bt_rf_0x1e_backup */
+		if (btcoexist->initilized) {
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				    "[BTCoex], Resume RF Rx LPF corner!!\n");
+			BTC_TRACE(trace_buf);
+			btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1e,
+					  0xfffff, coex_dm->bt_rf_0x1e_backup);
+		}
+	}
+}
+
+void halbtc8812a2ant_rf_shrink(IN struct btc_coexist *btcoexist,
+		       IN boolean force_exec, IN boolean rx_rf_shrink_on)
+{
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+		    "[BTCoex], %s turn Rx RF Shrink = %s\n",
+		    (force_exec ? "force to" : ""),
+		    ((rx_rf_shrink_on) ? "ON" : "OFF"));
+	BTC_TRACE(trace_buf);
+	coex_dm->cur_rf_rx_lpf_shrink = rx_rf_shrink_on;
+
+	if (!force_exec) {
+		if (coex_dm->pre_rf_rx_lpf_shrink ==
+		    coex_dm->cur_rf_rx_lpf_shrink)
+			return;
+	}
+	halbtc8812a2ant_set_sw_rf_rx_lpf_corner(btcoexist,
+						coex_dm->cur_rf_rx_lpf_shrink);
+
+	coex_dm->pre_rf_rx_lpf_shrink = coex_dm->cur_rf_rx_lpf_shrink;
+}
+
+void halbtc8812a2ant_set_sw_penalty_tx_rate_adaptive(IN struct btc_coexist
+		*btcoexist, IN boolean low_penalty_ra)
+{
+	u8	tmp_u1;
+
+	tmp_u1 = btcoexist->btc_read_1byte(btcoexist, 0x4fd);
+	tmp_u1 |= BIT(0);
+	if (low_penalty_ra) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], Tx rate adaptive, set low penalty!!\n");
+		BTC_TRACE(trace_buf);
+		tmp_u1 &= ~BIT(2);
+	} else {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], Tx rate adaptive, set normal!!\n");
+		BTC_TRACE(trace_buf);
+		tmp_u1 |= BIT(2);
+	}
+
+	btcoexist->btc_write_1byte(btcoexist, 0x4fd, tmp_u1);
+}
+
+void halbtc8812a2ant_low_penalty_ra(IN struct btc_coexist *btcoexist,
+			    IN boolean force_exec, IN boolean low_penalty_ra)
+{
+	return;
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+		    "[BTCoex], %s turn LowPenaltyRA = %s\n",
+		    (force_exec ? "force to" : ""),
+		    ((low_penalty_ra) ? "ON" : "OFF"));
+	BTC_TRACE(trace_buf);
+	coex_dm->cur_low_penalty_ra = low_penalty_ra;
+
+	if (!force_exec) {
+		if (coex_dm->pre_low_penalty_ra == coex_dm->cur_low_penalty_ra)
+			return;
+	}
+	halbtc8812a2ant_set_sw_penalty_tx_rate_adaptive(btcoexist,
+			coex_dm->cur_low_penalty_ra);
+
+	coex_dm->pre_low_penalty_ra = coex_dm->cur_low_penalty_ra;
+}
+
+void halbtc8812a2ant_set_dac_swing_reg(IN struct btc_coexist *btcoexist,
+				       IN u32 level)
+{
+	u8	val = (u8)level;
+
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+		    "[BTCoex], Write SwDacSwing = 0x%x\n",
+		    level);
+	BTC_TRACE(trace_buf);
+	btcoexist->btc_write_1byte_bitmask(btcoexist, 0xc5b, 0x3e, val);
+}
+
+void halbtc8812a2ant_set_sw_full_time_dac_swing(IN struct btc_coexist
+		*btcoexist, IN boolean sw_dac_swing_on, IN u32 sw_dac_swing_lvl)
+{
+	if (sw_dac_swing_on)
+		halbtc8812a2ant_set_dac_swing_reg(btcoexist, sw_dac_swing_lvl);
+	else
+		halbtc8812a2ant_set_dac_swing_reg(btcoexist, 0x18);
+}
+
+
+void halbtc8812a2ant_dac_swing(IN struct btc_coexist *btcoexist,
+	IN boolean force_exec, IN boolean dac_swing_on, IN u32 dac_swing_lvl)
+{
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+		    "[BTCoex], %s turn DacSwing=%s, dac_swing_lvl=0x%x\n",
+		(force_exec ? "force to" : ""), ((dac_swing_on) ? "ON" : "OFF"),
+		    dac_swing_lvl);
+	BTC_TRACE(trace_buf);
+	coex_dm->cur_dac_swing_on = dac_swing_on;
+	coex_dm->cur_dac_swing_lvl = dac_swing_lvl;
+
+	if (!force_exec) {
+		if ((coex_dm->pre_dac_swing_on == coex_dm->cur_dac_swing_on) &&
+		    (coex_dm->pre_dac_swing_lvl ==
+		     coex_dm->cur_dac_swing_lvl))
+			return;
+	}
+	delay_ms(30);
+	halbtc8812a2ant_set_sw_full_time_dac_swing(btcoexist, dac_swing_on,
+			dac_swing_lvl);
+
+	coex_dm->pre_dac_swing_on = coex_dm->cur_dac_swing_on;
+	coex_dm->pre_dac_swing_lvl = coex_dm->cur_dac_swing_lvl;
+}
+
+void halbtc8812a2ant_set_adc_back_off(IN struct btc_coexist *btcoexist,
+				      IN boolean adc_back_off)
+{
+	if (adc_back_off) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], BB BackOff Level On!\n");
+		BTC_TRACE(trace_buf);
+		btcoexist->btc_write_1byte_bitmask(btcoexist, 0x8db, 0x60, 0x3);
+	} else {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], BB BackOff Level Off!\n");
+		BTC_TRACE(trace_buf);
+		btcoexist->btc_write_1byte_bitmask(btcoexist, 0x8db, 0x60, 0x1);
+	}
+}
+
+void halbtc8812a2ant_adc_back_off(IN struct btc_coexist *btcoexist,
+			  IN boolean force_exec, IN boolean adc_back_off)
+{
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+		    "[BTCoex], %s turn AdcBackOff = %s\n",
+		    (force_exec ? "force to" : ""),
+		    ((adc_back_off) ? "ON" : "OFF"));
+	BTC_TRACE(trace_buf);
+
+	coex_dm->cur_adc_back_off = adc_back_off;
+
+	if (!force_exec) {
+		if (coex_dm->pre_adc_back_off == coex_dm->cur_adc_back_off)
+			return;
+	}
+	halbtc8812a2ant_set_adc_back_off(btcoexist, coex_dm->cur_adc_back_off);
+
+	coex_dm->pre_adc_back_off = coex_dm->cur_adc_back_off;
+}
+
+void halbtc8812a2ant_set_agc_table(IN struct btc_coexist *btcoexist,
+				   IN boolean agc_table_en)
+{
+	u8		rssi_adjust_val = 0;
+
+	btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0xef, 0xfffff, 0x02000);
+	if (agc_table_en) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], Agc Table On!\n");
+		BTC_TRACE(trace_buf);
+		btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x3b, 0xfffff,
+					  0x28F4B);
+		btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x3b, 0xfffff,
+					  0x10AB2);
+		rssi_adjust_val = 8;
+	} else {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], Agc Table Off!\n");
+		BTC_TRACE(trace_buf);
+		btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x3b, 0xfffff,
+					  0x2884B);
+		btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x3b, 0xfffff,
+					  0x104B2);
+	}
+	btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0xef, 0xfffff, 0x0);
+
+	/* set rssi_adjust_val for wifi module. */
+	btcoexist->btc_set(btcoexist, BTC_SET_U1_RSSI_ADJ_VAL_FOR_AGC_TABLE_ON,
+			   &rssi_adjust_val);
+}
+
+void halbtc8812a2ant_agc_table(IN struct btc_coexist *btcoexist,
+			       IN boolean force_exec, IN boolean agc_table_en)
+{
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], %s %s Agc Table\n",
+		    (force_exec ? "force to" : ""),
+		    ((agc_table_en) ? "Enable" : "Disable"));
+	BTC_TRACE(trace_buf);
+	coex_dm->cur_agc_table_en = agc_table_en;
+
+	if (!force_exec) {
+		if (coex_dm->pre_agc_table_en == coex_dm->cur_agc_table_en)
+			return;
+	}
+	halbtc8812a2ant_set_agc_table(btcoexist, agc_table_en);
+
+	coex_dm->pre_agc_table_en = coex_dm->cur_agc_table_en;
+}
+
+void halbtc8812a2ant_set_coex_table(IN struct btc_coexist *btcoexist,
+	    IN u32 val0x6c0, IN u32 val0x6c4, IN u32 val0x6c8, IN u8 val0x6cc)
+{
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+		    "[BTCoex], set coex table, set 0x6c0=0x%x\n", val0x6c0);
+	BTC_TRACE(trace_buf);
+	btcoexist->btc_write_4byte(btcoexist, 0x6c0, val0x6c0);
+
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+		    "[BTCoex], set coex table, set 0x6c4=0x%x\n", val0x6c4);
+	BTC_TRACE(trace_buf);
+	btcoexist->btc_write_4byte(btcoexist, 0x6c4, val0x6c4);
+
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+		    "[BTCoex], set coex table, set 0x6c8=0x%x\n", val0x6c8);
+	BTC_TRACE(trace_buf);
+	btcoexist->btc_write_4byte(btcoexist, 0x6c8, val0x6c8);
+
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+		    "[BTCoex], set coex table, set 0x6cc=0x%x\n", val0x6cc);
+	BTC_TRACE(trace_buf);
+	btcoexist->btc_write_1byte(btcoexist, 0x6cc, val0x6cc);
+}
+
+void halbtc8812a2ant_coex_table(IN struct btc_coexist *btcoexist,
+			IN boolean force_exec, IN u32 val0x6c0, IN u32 val0x6c4,
+				IN u32 val0x6c8, IN u8 val0x6cc)
+{
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+		"[BTCoex], %s write Coex Table 0x6c0=0x%x, 0x6c4=0x%x, 0x6c8=0x%x, 0x6cc=0x%x\n",
+		(force_exec ? "force to" : ""), val0x6c0, val0x6c4, val0x6c8,
+		    val0x6cc);
+	BTC_TRACE(trace_buf);
+	coex_dm->cur_val0x6c0 = val0x6c0;
+	coex_dm->cur_val0x6c4 = val0x6c4;
+	coex_dm->cur_val0x6c8 = val0x6c8;
+	coex_dm->cur_val0x6cc = val0x6cc;
+
+	if (!force_exec) {
+		if ((coex_dm->pre_val0x6c0 == coex_dm->cur_val0x6c0) &&
+		    (coex_dm->pre_val0x6c4 == coex_dm->cur_val0x6c4) &&
+		    (coex_dm->pre_val0x6c8 == coex_dm->cur_val0x6c8) &&
+		    (coex_dm->pre_val0x6cc == coex_dm->cur_val0x6cc))
+			return;
+	}
+	halbtc8812a2ant_set_coex_table(btcoexist, val0x6c0, val0x6c4, val0x6c8,
+				       val0x6cc);
+
+	coex_dm->pre_val0x6c0 = coex_dm->cur_val0x6c0;
+	coex_dm->pre_val0x6c4 = coex_dm->cur_val0x6c4;
+	coex_dm->pre_val0x6c8 = coex_dm->cur_val0x6c8;
+	coex_dm->pre_val0x6cc = coex_dm->cur_val0x6cc;
+}
+
+void halbtc8812a2ant_coex_table_with_type(IN struct btc_coexist *btcoexist,
+		IN boolean force_exec, IN u8 type)
+{
+	switch (type) {
+	case 0:
+		halbtc8812a2ant_coex_table(btcoexist, force_exec,
+				   0x55555555, 0x5a5a5a5a, 0xffffff, 0x3);
+		break;
+	case 1:
+		halbtc8812a2ant_coex_table(btcoexist, force_exec,
+				   0x5a5a5a5a, 0x5a5a5a5a, 0xffffff, 0x3);
+		break;
+	case 2:
+		halbtc8812a2ant_coex_table(btcoexist, force_exec,
+				   0x55555555, 0x5ffb5ffb, 0xffffff, 0x3);
+		break;
+	case 3:
+		halbtc8812a2ant_coex_table(btcoexist, force_exec,
+				   0x5fdf5fdf, 0x5fdb5fdb, 0xffffff, 0x3);
+		break;
+	case 4:
+		halbtc8812a2ant_coex_table(btcoexist, force_exec,
+				   0xdfffdfff, 0x5fdb5fdb, 0xffffff, 0x3);
+		break;
+	case 5:
+		halbtc8812a2ant_coex_table(btcoexist, force_exec,
+				   0x5ddd5ddd, 0x5fdb5fdb, 0xffffff, 0x3);
+		break;
+	case 6:
+		halbtc8812a2ant_coex_table(btcoexist, force_exec,
+				   0x5fff5fff, 0x5a5a5a5a, 0xffffff, 0x3);
+		break;
+	case 7:
+		if (coex_sta->scan_ap_num <= 5)
+			halbtc8812a2ant_coex_table(btcoexist,
+					   force_exec, 0xffffffff, 0xfafafafa,
+						   0xffffff, 0x3);
+		else
+			halbtc8812a2ant_coex_table(btcoexist,
+					   force_exec, 0xffffffff, 0x5a5a5a5a,
+						   0xffffff, 0x3);
+		break;
+	case 8:
+		halbtc8812a2ant_coex_table(btcoexist, force_exec,
+				   0x5f5f5f5f, 0x5a5a5a5a, 0xffffff, 0x3);
+		break;
+
+	default:
+		break;
+	}
+}
+
+void halbtc8812a2ant_set_fw_ignore_wlan_act(IN struct btc_coexist *btcoexist,
+		IN boolean enable)
+{
+	u8	data_len = 3;
+	u8	buf[5] = {0};
+
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+		    "[BTCoex], %s BT Ignore Wlan_Act\n",
+		    (enable ? "Enable" : "Disable"));
+	BTC_TRACE(trace_buf);
+
+	buf[0] = data_len;
+	buf[1] = 0x1;			/* OP_Code */
+	buf[2] = 0x1;			/* OP_Code_Length */
+	if (enable)
+		buf[3] = 0x1;		/* OP_Code_Content */
+	else
+		buf[3] = 0x0;
+
+	btcoexist->btc_set(btcoexist, BTC_SET_ACT_CTRL_BT_COEX,
+			   (void *)&buf[0]);
+}
+
+void halbtc8812a2ant_ignore_wlan_act(IN struct btc_coexist *btcoexist,
+				     IN boolean force_exec, IN boolean enable)
+{
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+		    "[BTCoex], %s turn Ignore WlanAct %s\n",
+		    (force_exec ? "force to" : ""), (enable ? "ON" : "OFF"));
+	BTC_TRACE(trace_buf);
+	coex_dm->cur_ignore_wlan_act = enable;
+
+	if (!force_exec) {
+		if (coex_dm->pre_ignore_wlan_act ==
+		    coex_dm->cur_ignore_wlan_act)
+			return;
+	}
+	halbtc8812a2ant_set_fw_ignore_wlan_act(btcoexist, enable);
+
+	coex_dm->pre_ignore_wlan_act = coex_dm->cur_ignore_wlan_act;
+}
+
+void halbtc8812a2ant_set_fw_pstdma(IN struct btc_coexist *btcoexist,
+	   IN u8 byte1, IN u8 byte2, IN u8 byte3, IN u8 byte4, IN u8 byte5)
+{
+	u8			h2c_parameter[5] = {0};
+	u8			real_byte1 = byte1, real_byte5 = byte5;
+	boolean			ap_enable = false;
+
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_AP_MODE_ENABLE,
+			   &ap_enable);
+
+	if (ap_enable) {
+		if (byte1 & BIT(4) && !(byte1 & BIT(5))) {
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				    "[BTCoex], FW for 1Ant AP mode\n");
+			BTC_TRACE(trace_buf);
+			real_byte1 &= ~BIT(4);
+			real_byte1 |= BIT(5);
+
+			real_byte5 |= BIT(5);
+			real_byte5 &= ~BIT(6);
+		}
+	}
+
+	h2c_parameter[0] = real_byte1;
+	h2c_parameter[1] = byte2;
+	h2c_parameter[2] = byte3;
+	h2c_parameter[3] = byte4;
+	h2c_parameter[4] = real_byte5;
+
+
+	coex_dm->ps_tdma_para[0] = real_byte1;
+	coex_dm->ps_tdma_para[1] = byte2;
+	coex_dm->ps_tdma_para[2] = byte3;
+	coex_dm->ps_tdma_para[3] = byte4;
+	coex_dm->ps_tdma_para[4] = real_byte5;
+
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+		    "[BTCoex], PS-TDMA H2C cmd =0x%x%08x\n",
+		    h2c_parameter[0],
+		    h2c_parameter[1] << 24 | h2c_parameter[2] << 16 |
+		    h2c_parameter[3] << 8 | h2c_parameter[4]);
+
+	BTC_TRACE(trace_buf);
+	btcoexist->btc_fill_h2c(btcoexist, 0x60, 5, h2c_parameter);
+}
+
+void halbtc8812a2ant_set_lps_rpwm(IN struct btc_coexist *btcoexist,
+				  IN u8 lps_val, IN u8 rpwm_val)
+{
+	u8	lps = lps_val;
+	u8	rpwm = rpwm_val;
+
+	btcoexist->btc_set(btcoexist, BTC_SET_U1_LPS_VAL, &lps);
+	btcoexist->btc_set(btcoexist, BTC_SET_U1_RPWM_VAL, &rpwm);
+}
+
+void halbtc8812a2ant_lps_rpwm(IN struct btc_coexist *btcoexist,
+		      IN boolean force_exec, IN u8 lps_val, IN u8 rpwm_val)
+{
+	coex_dm->cur_lps = lps_val;
+	coex_dm->cur_rpwm = rpwm_val;
+
+	if (!force_exec) {
+		if ((coex_dm->pre_lps == coex_dm->cur_lps) &&
+		    (coex_dm->pre_rpwm == coex_dm->cur_rpwm))
+			return;
+	}
+	halbtc8812a2ant_set_lps_rpwm(btcoexist, lps_val, rpwm_val);
+
+	coex_dm->pre_lps = coex_dm->cur_lps;
+	coex_dm->pre_rpwm = coex_dm->cur_rpwm;
+}
+
+void halbtc8812a2ant_sw_mechanism1(IN struct btc_coexist *btcoexist,
+			   IN boolean shrink_rx_lpf, IN boolean low_penalty_ra,
+			   IN boolean limited_dig, IN boolean bt_lna_constrain)
+{
+	/*
+	u32	wifi_bw;
+
+	btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw);
+
+	if(BTC_WIFI_BW_HT40 != wifi_bw)
+	{
+		if (shrink_rx_lpf)
+			shrink_rx_lpf = false;
+	}
+	*/
+
+	halbtc8812a2ant_rf_shrink(btcoexist, NORMAL_EXEC, shrink_rx_lpf);
+	/* halbtc8812a2ant_low_penalty_ra(btcoexist, NORMAL_EXEC, low_penalty_ra); */
+}
+
+void halbtc8812a2ant_sw_mechanism2(IN struct btc_coexist *btcoexist,
+			   IN boolean agc_table_shift, IN boolean adc_back_off,
+			   IN boolean sw_dac_swing, IN u32 dac_swing_lvl)
+{
+	/* halbtc8812a2ant_agc_table(btcoexist, NORMAL_EXEC, agc_table_shift); */
+	halbtc8812a2ant_adc_back_off(btcoexist, NORMAL_EXEC, adc_back_off);
+	halbtc8812a2ant_dac_swing(btcoexist, NORMAL_EXEC, sw_dac_swing,
+				  dac_swing_lvl);
+}
+
+void halbtc8812a2ant_set_ant_path(IN struct btc_coexist *btcoexist,
+	  IN u8 ant_pos_type, IN boolean init_hwcfg, IN boolean wifi_off)
+{
+	u8			u8tmp = 0;
+
+	if (init_hwcfg) {
+		btcoexist->btc_write_4byte(btcoexist, 0x900, 0x00000400);
+		btcoexist->btc_write_1byte(btcoexist, 0x76d, 0x1);
+	} else if (wifi_off) {
+
+		}
+
+	/* ext switch setting */
+	switch (ant_pos_type) {
+	case BTC_ANT_WIFI_AT_CPL_MAIN:
+		u8tmp = btcoexist->btc_read_1byte(btcoexist, 0xcb7);
+		u8tmp &= ~BIT(2);
+		u8tmp |= BIT(3);
+		btcoexist->btc_write_1byte(btcoexist, 0xcb7, u8tmp);
+		break;
+	case BTC_ANT_WIFI_AT_CPL_AUX:
+		u8tmp = btcoexist->btc_read_1byte(btcoexist, 0xcb7);
+		u8tmp &= ~BIT(3);
+		u8tmp |= BIT(2);
+		btcoexist->btc_write_1byte(btcoexist, 0xcb7, u8tmp);
+		break;
+	default:
+		break;
+	}
+}
+
+void halbtc8812a2ant_ps_tdma(IN struct btc_coexist *btcoexist,
+		     IN boolean force_exec, IN boolean turn_on, IN u8 type)
+{
+	s8			wifi_duration_adjust = 0x0;
+
+	coex_dm->cur_ps_tdma_on = turn_on;
+	coex_dm->cur_ps_tdma = type;
+
+	if (!force_exec) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			"[BTCoex], pre_ps_tdma_on = %d, cur_ps_tdma_on = %d!!\n",
+			    coex_dm->pre_ps_tdma_on, coex_dm->cur_ps_tdma_on);
+		BTC_TRACE(trace_buf);
+
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], pre_ps_tdma = %d, cur_ps_tdma = %d!!\n",
+			    coex_dm->pre_ps_tdma, coex_dm->cur_ps_tdma);
+		BTC_TRACE(trace_buf);
+
+		if ((coex_dm->pre_ps_tdma_on == coex_dm->cur_ps_tdma_on) &&
+		    (coex_dm->pre_ps_tdma == coex_dm->cur_ps_tdma))
+			return;
+	}
+
+	if (coex_sta->scan_ap_num >= 40)
+		wifi_duration_adjust = -15;
+	else if (coex_sta->scan_ap_num >= 20)
+		wifi_duration_adjust = -10;
+
+	/*
+		if (!coex_sta->force_lps_on)
+		{
+			ps_tdma_byte0_val = 0x61;
+			ps_tdma_byte3_val = 0x11;
+			ps_tdma_byte4_val = 0x10;
+		}
+
+
+		if (  (type == 3) || (type == 13) || (type == 14) )
+		{
+			ps_tdma_byte4_val = ps_tdma_byte4_val & 0xbf;
+
+			if (!wifi_busy)
+			 ps_tdma_byte4_val = ps_tdma_byte4_val | 0x1;
+		}
+
+		if (bt_link_info->slave_role == true)
+			ps_tdma_byte4_val = ps_tdma_byte4_val | 0x1;
+
+	*/
+	if (turn_on) {
+		switch (type) {
+		case 1:
+		default:	/* d1,wb */
+			halbtc8812a2ant_set_fw_pstdma(btcoexist, 0xe3,
+						      0x3c, 0x03, 0x11, 0x10);
+			break;
+		case 2:
+			halbtc8812a2ant_set_fw_pstdma(btcoexist, 0xe3,
+						      0x32, 0x03, 0x11, 0x10);
+			break;
+		case 3:
+			halbtc8812a2ant_set_fw_pstdma(btcoexist, 0xe3,
+						      0x28, 0x03, 0x11, 0x10);
+			break;
+		case 4:
+			halbtc8812a2ant_set_fw_pstdma(btcoexist, 0xe3,
+						      0x1e, 0x03, 0x11, 0x10);
+			break;
+		case 5:		/* d1,pb,TXpause */
+			halbtc8812a2ant_set_fw_pstdma(btcoexist, 0x63,
+						      0x3c, 0x03, 0x90, 0x10);
+			break;
+		case 6:
+			halbtc8812a2ant_set_fw_pstdma(btcoexist, 0x63,
+						      0x32, 0x03, 0x90, 0x10);
+			break;
+		case 7:
+			halbtc8812a2ant_set_fw_pstdma(btcoexist, 0x63,
+						      0x28, 0x03, 0x90, 0x10);
+			break;
+		case 8:
+			halbtc8812a2ant_set_fw_pstdma(btcoexist, 0x63,
+						      0x1e, 0x03, 0x90, 0x10);
+			break;
+		case 9:		/* d1,bb */
+			halbtc8812a2ant_set_fw_pstdma(btcoexist, 0xe3,
+						      0x3c, 0x03, 0x31, 0x10);
+			break;
+		case 10:
+			halbtc8812a2ant_set_fw_pstdma(btcoexist, 0xe3,
+						      0x32, 0x03, 0x31, 0x10);
+			break;
+		case 11:
+			halbtc8812a2ant_set_fw_pstdma(btcoexist, 0xe3,
+						      0x28, 0x03, 0x31, 0x10);
+			break;
+		case 12:
+			halbtc8812a2ant_set_fw_pstdma(btcoexist, 0xe3,
+						      0x1e, 0x03, 0x31, 0x10);
+			break;
+		case 13:	/* d1,bb,TXpause */
+			halbtc8812a2ant_set_fw_pstdma(btcoexist, 0xe3,
+						      0x3c, 0x03, 0x30, 0x10);
+			break;
+		case 14:
+			halbtc8812a2ant_set_fw_pstdma(btcoexist, 0xe3,
+						      0x32, 0x03, 0x30, 0x10);
+			break;
+		case 15:
+			halbtc8812a2ant_set_fw_pstdma(btcoexist, 0xe3,
+						      0x28, 0x03, 0x30, 0x10);
+			break;
+		case 16:
+			halbtc8812a2ant_set_fw_pstdma(btcoexist, 0xe3,
+						      0x1e, 0x03, 0x30, 0x10);
+			break;
+		case 17:
+			halbtc8812a2ant_set_fw_pstdma(btcoexist, 0x61,
+						      0x35, 0x3, 0x11, 0x11);
+			break;
+		case 18:
+			halbtc8812a2ant_set_fw_pstdma(btcoexist, 0xe3,
+						      0x5, 0x5, 0xe1, 0x90);
+			break;
+		case 19:
+			halbtc8812a2ant_set_fw_pstdma(btcoexist, 0xe3,
+						      0x25, 0x25, 0xe1, 0x90);
+			break;
+		case 20:
+			halbtc8812a2ant_set_fw_pstdma(btcoexist, 0xe3,
+						      0x25, 0x25, 0x60, 0x90);
+			break;
+		case 21:
+			halbtc8812a2ant_set_fw_pstdma(btcoexist, 0xe3,
+						      0x15, 0x3, 0x70, 0x90);
+			break;
+		case 22:
+			halbtc8812a2ant_set_fw_pstdma(btcoexist, 0x61,
+						      0x1a, 0x1a, 0x21, 0x10);
+			break;
+		case 23:
+			halbtc8812a2ant_set_fw_pstdma(btcoexist, 0xe3,
+						      0x1c, 0x03, 0x31, 0x10);
+			break;
+
+		case 71:
+			halbtc8812a2ant_set_fw_pstdma(btcoexist, 0xe3,
+						      0x1a, 0x1a, 0xe1, 0x90);
+			break;
+
+		/* following cases is for wifi rssi low, started from 81 */
+		case 80:
+			halbtc8812a2ant_set_fw_pstdma(btcoexist, 0x53,
+						      0x3c, 0x3, 0x90, 0x50);
+			break;
+		case 81:
+			halbtc8812a2ant_set_fw_pstdma(btcoexist, 0x53,
+				      0x3a + wifi_duration_adjust, 0x3, 0x90,
+						      0x50);
+			break;
+		case 82:
+			halbtc8812a2ant_set_fw_pstdma(btcoexist, 0x53,
+				      0x30 + wifi_duration_adjust, 0x03, 0x90,
+						      0x50);
+			break;
+		case 83:
+			halbtc8812a2ant_set_fw_pstdma(btcoexist, 0x53,
+						      0x21, 0x03, 0x90, 0x50);
+			break;
+		case 84:
+			halbtc8812a2ant_set_fw_pstdma(btcoexist, 0x53,
+						      0x15, 0x3, 0x90, 0x50);
+			break;
+		case 85:
+			halbtc8812a2ant_set_fw_pstdma(btcoexist, 0x53,
+						      0x1d, 0x1d, 0x80, 0x50);
+			break;
+		case 86:
+			halbtc8812a2ant_set_fw_pstdma(btcoexist, 0x53,
+						      0x15, 0x15, 0x80, 0x50);
+			break;
+		}
+	} else {
+		/* disable PS tdma */
+		switch (type) {
+		case 0: /* ANT2PTA, 0x778=0x1 */
+			halbtc8812a2ant_set_fw_pstdma(btcoexist, 0x8,
+						      0x0, 0x0, 0x0, 0x0);
+			break;
+		case 1: /* ANT2BT, 0x778=3 */
+			halbtc8812a2ant_set_fw_pstdma(btcoexist, 0x0,
+						      0x0, 0x0, 0x8, 0x0);
+			delay_ms(5);
+			halbtc8812a2ant_set_ant_path(btcoexist,
+				     BTC_ANT_WIFI_AT_CPL_AUX, false, false);
+			break;
+		case 2: /* ANT2BT, 0x778=3 */
+			halbtc8812a2ant_set_fw_pstdma(btcoexist, 0x0,
+						      0x0, 0x0, 0x8, 0x0);
+			delay_ms(5);
+			halbtc8812a2ant_set_ant_path(btcoexist,
+				     BTC_ANT_WIFI_AT_CPL_MAIN, false, false);
+			break;
+		default:
+			halbtc8812a2ant_set_fw_pstdma(btcoexist, 0x0,
+						      0x0, 0x0, 0x0, 0x0);
+			break;
+		}
+	}
+
+	/* update pre state */
+	coex_dm->pre_ps_tdma_on = coex_dm->cur_ps_tdma_on;
+	coex_dm->pre_ps_tdma = coex_dm->cur_ps_tdma;
+}
+
+
+void halbtc8812a2ant_ps_tdma_check_for_power_save_state(
+	IN struct btc_coexist *btcoexist, IN boolean new_ps_state)
+{
+	u8	lps_mode = 0x0;
+
+	btcoexist->btc_get(btcoexist, BTC_GET_U1_LPS_MODE, &lps_mode);
+
+	if (lps_mode) {	/* already under LPS state */
+		if (new_ps_state) {
+			/* keep state under LPS, do nothing. */
+		} else {
+			/* will leave LPS state, turn off psTdma first */
+			halbtc8812a2ant_ps_tdma(btcoexist, NORMAL_EXEC, false,
+						0);
+		}
+	} else {					/* NO PS state */
+		if (new_ps_state) {
+			/* will enter LPS state, turn off psTdma first */
+			halbtc8812a2ant_ps_tdma(btcoexist, NORMAL_EXEC, false,
+						0);
+		} else {
+			/* keep state under NO PS state, do nothing. */
+		}
+	}
+}
+
+
+void halbtc8812a2ant_power_save_state(IN struct btc_coexist *btcoexist,
+			      IN u8 ps_type, IN u8 lps_val, IN u8 rpwm_val)
+{
+	boolean		low_pwr_disable = false;
+	boolean	ap_enable = false;
+
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_AP_MODE_ENABLE,
+			   &ap_enable);
+
+	if (ap_enable) {
+		ps_type = BTC_PS_WIFI_NATIVE;
+		lps_val = 0x0;
+		rpwm_val = 0x0;
+	}
+	switch (ps_type) {
+	case BTC_PS_WIFI_NATIVE:
+		/* recover to original 32k low power setting */
+		low_pwr_disable = true;
+		btcoexist->btc_set(btcoexist,
+				   BTC_SET_ACT_DISABLE_LOW_POWER,
+				   &low_pwr_disable);
+		btcoexist->btc_set(btcoexist, BTC_SET_ACT_NORMAL_LPS,
+				   NULL);
+		coex_sta->force_lps_on = false;
+		break;
+	case BTC_PS_LPS_ON:
+		halbtc8812a2ant_ps_tdma_check_for_power_save_state(
+			btcoexist, true);
+		halbtc8812a2ant_lps_rpwm(btcoexist, NORMAL_EXEC,
+					 lps_val, rpwm_val);
+		/* when coex force to enter LPS, do not enter 32k low power. */
+		low_pwr_disable = true;
+		btcoexist->btc_set(btcoexist,
+				   BTC_SET_ACT_DISABLE_LOW_POWER,
+				   &low_pwr_disable);
+		/* power save must executed before psTdma. */
+		btcoexist->btc_set(btcoexist, BTC_SET_ACT_ENTER_LPS,
+				   NULL);
+		coex_sta->force_lps_on = true;
+		break;
+	case BTC_PS_LPS_OFF:
+		halbtc8812a2ant_ps_tdma_check_for_power_save_state(
+			btcoexist, false);
+		btcoexist->btc_set(btcoexist, BTC_SET_ACT_LEAVE_LPS,
+				   NULL);
+		coex_sta->force_lps_on = false;
+		break;
+	default:
+		break;
+	}
+}
+
+void halbtc8812a2ant_coex_all_off(IN struct btc_coexist *btcoexist)
+{
+	/* fw all off */
+	halbtc8812a2ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, 0x0,
+					 0x0);
+	halbtc8812a2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 1);
+	halbtc8812a2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6);
+	halbtc8812a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);
+
+	/* sw all off */
+	halbtc8812a2ant_sw_mechanism1(btcoexist, false, false, false, false);
+	halbtc8812a2ant_sw_mechanism2(btcoexist, false, false, false, 0x18);
+
+	/* hw all off */
+	halbtc8812a2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0);
+}
+
+void halbtc8812a2ant_init_coex_dm(IN struct btc_coexist *btcoexist)
+{
+	/* force to reset coex mechanism */
+	halbtc8812a2ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, 0x0,
+					 0x0);
+	halbtc8812a2ant_ps_tdma(btcoexist, FORCE_EXEC, false, 1);
+	halbtc8812a2ant_fw_dac_swing_lvl(btcoexist, FORCE_EXEC, 6);
+	halbtc8812a2ant_dec_bt_pwr(btcoexist, FORCE_EXEC, 0);
+
+	halbtc8812a2ant_coex_table_with_type(btcoexist, FORCE_EXEC, 0);
+
+	halbtc8812a2ant_sw_mechanism1(btcoexist, false, false, false, false);
+	halbtc8812a2ant_sw_mechanism2(btcoexist, false, false, false, 0x18);
+}
+
+void halbtc8812a2ant_monitor_bt_enable_disable(IN struct btc_coexist *btcoexist)
+{
+	struct  btc_stack_info	*stack_info = &btcoexist->stack_info;
+	static u32	bt_disable_cnt = 0;
+	boolean			bt_active = true, bt_disabled = false;
+
+	/* This function check if bt is disabled */
+
+	/* only 8812a need to consider if core stack is installed. */
+	/*if (!stack_info->hci_version)*/
+	/*bt_active = false;*/
+
+	bt_disabled = btcoexist->bt_info.bt_disabled;
+
+	if (coex_sta->pre_bt_disabled != bt_disabled) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], BT is from %s to %s!!\n",
+			(coex_sta->pre_bt_disabled ? "disabled" : "enabled"),
+			    (bt_disabled ? "disabled" : "enabled"));
+		BTC_TRACE(trace_buf);
+		coex_sta->pre_bt_disabled = bt_disabled;
+
+		if (bt_disabled) {
+			halbtc8812a2ant_power_save_state(btcoexist,
+						 BTC_PS_WIFI_NATIVE, 0x0, 0x0);
+			halbtc8812a2ant_ps_tdma(btcoexist, FORCE_EXEC, false,
+						2);
+			halbtc8812a2ant_coex_table_with_type(btcoexist,
+							     NORMAL_EXEC, 0);
+		}
+	}
+}
+
+
+void halbtc8812a2ant_action_bt_inquiry(IN struct btc_coexist *btcoexist)
+{
+	halbtc8812a2ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, 0x0,
+					 0x0);
+
+	halbtc8812a2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 2);
+	halbtc8812a2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 3);
+	halbtc8812a2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6);
+	halbtc8812a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);
+
+	halbtc8812a2ant_sw_mechanism1(btcoexist, false, false, false, false);
+	halbtc8812a2ant_sw_mechanism2(btcoexist, false, false, false, 0x18);
+}
+
+
+boolean halbtc8812a2ant_is_common_action(IN struct btc_coexist *btcoexist)
+{
+	struct  btc_bt_link_info	*bt_link_info = &btcoexist->bt_link_info;
+	boolean				common = false, wifi_connected = false, wifi_busy = false;
+	boolean				bt_hs_on = false;
+
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on);
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED,
+			   &wifi_connected);
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy);
+
+
+	if (coex_sta->c2h_bt_inquiry_page) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], BT is under inquiry/page scan !!\n");
+		BTC_TRACE(trace_buf);
+		halbtc8812a2ant_action_bt_inquiry(btcoexist);
+		return true;
+	}
+
+	if (bt_link_info->sco_exist || bt_link_info->hid_exist)
+		halbtc8812a2ant_limited_tx(btcoexist, NORMAL_EXEC, 1, 0, 0, 0);
+	else
+		halbtc8812a2ant_limited_tx(btcoexist, NORMAL_EXEC, 0, 0, 0, 0);
+
+	if (!wifi_connected) {
+		halbtc8812a2ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE,
+						 0x0, 0x0);
+		halbtc8812a2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false,
+					   0x8);
+
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], Wifi non-connected idle!!\n");
+		BTC_TRACE(trace_buf);
+
+		if ((BT_8812A_2ANT_BT_STATUS_NON_CONNECTED_IDLE ==
+		     coex_dm->bt_status) ||
+		    (BT_8812A_2ANT_BT_STATUS_CONNECTED_IDLE ==
+		     coex_dm->bt_status)) {
+			halbtc8812a2ant_coex_table_with_type(btcoexist,
+							     NORMAL_EXEC, 1);
+			halbtc8812a2ant_ps_tdma(btcoexist, NORMAL_EXEC, false,
+						0);
+		} else {
+			halbtc8812a2ant_coex_table_with_type(btcoexist,
+							     NORMAL_EXEC, 0);
+			halbtc8812a2ant_ps_tdma(btcoexist, NORMAL_EXEC, false,
+						1);
+		}
+
+		halbtc8812a2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6);
+		halbtc8812a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);
+
+		halbtc8812a2ant_sw_mechanism1(btcoexist, false, false, false,
+					      false);
+		halbtc8812a2ant_sw_mechanism2(btcoexist, false, false, false,
+					      0x18);
+
+		common = true;
+	} else {
+		if (BT_8812A_2ANT_BT_STATUS_NON_CONNECTED_IDLE ==
+		    coex_dm->bt_status) {
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				"[BTCoex], Wifi connected + BT non connected-idle!!\n");
+			BTC_TRACE(trace_buf);
+			halbtc8812a2ant_power_save_state(btcoexist,
+						 BTC_PS_WIFI_NATIVE, 0x0, 0x0);
+			halbtc8812a2ant_limited_rx(btcoexist, NORMAL_EXEC,
+						   false, false, 0x8);
+
+			halbtc8812a2ant_coex_table_with_type(btcoexist,
+							     NORMAL_EXEC, 0);
+			halbtc8812a2ant_ps_tdma(btcoexist, NORMAL_EXEC, false,
+						0);
+			halbtc8812a2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC,
+							 6);
+			halbtc8812a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);
+
+			halbtc8812a2ant_sw_mechanism1(btcoexist, false, false,
+						      false, false);
+			halbtc8812a2ant_sw_mechanism2(btcoexist, false, false,
+						      false, 0x18);
+
+			common = true;
+		} else if (BT_8812A_2ANT_BT_STATUS_CONNECTED_IDLE ==
+			   coex_dm->bt_status) {
+			if (bt_hs_on)
+				return false;
+
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				"[BTCoex], Wifi connected + BT connected-idle!!\n");
+			BTC_TRACE(trace_buf);
+			halbtc8812a2ant_power_save_state(btcoexist,
+						 BTC_PS_WIFI_NATIVE, 0x0, 0x0);
+			halbtc8812a2ant_limited_rx(btcoexist, NORMAL_EXEC,
+						   false, false, 0x8);
+
+			halbtc8812a2ant_coex_table_with_type(btcoexist,
+							     NORMAL_EXEC, 0);
+			halbtc8812a2ant_ps_tdma(btcoexist, NORMAL_EXEC, false,
+						0);
+			halbtc8812a2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC,
+							 6);
+			halbtc8812a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);
+
+			halbtc8812a2ant_sw_mechanism1(btcoexist, true, false,
+						      false, false);
+			halbtc8812a2ant_sw_mechanism2(btcoexist, false, false,
+						      false, 0x18);
+
+			common = true;
+		} else {
+			if (wifi_busy) {
+				BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+					"[BTCoex], Wifi Connected-Busy + BT Busy!!\n");
+				BTC_TRACE(trace_buf);
+				common = false;
+			} else {
+				BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+					"[BTCoex], Wifi Connected-Idle + BT Busy!!\n");
+				BTC_TRACE(trace_buf);
+
+				halbtc8812a2ant_power_save_state(btcoexist,
+						 BTC_PS_WIFI_NATIVE, 0x0, 0x0);
+
+				halbtc8812a2ant_limited_rx(btcoexist,
+					   NORMAL_EXEC, false, false, 0x8);
+
+				halbtc8812a2ant_coex_table_with_type(btcoexist,
+							     NORMAL_EXEC, 0);
+
+				halbtc8812a2ant_ps_tdma(btcoexist, NORMAL_EXEC,
+							true, 17);
+
+				halbtc8812a2ant_fw_dac_swing_lvl(btcoexist,
+							 NORMAL_EXEC, 6);
+				halbtc8812a2ant_dec_bt_pwr(btcoexist,
+							   NORMAL_EXEC, 0);
+				halbtc8812a2ant_sw_mechanism1(btcoexist, false,
+						      false, false, false);
+				halbtc8812a2ant_sw_mechanism2(btcoexist, false,
+						      false, false, 0x18);
+				common = true;
+			}
+		}
+	}
+
+	return common;
+}
+
+void halbtc8812a2ant_tdma_duration_adjust(IN struct btc_coexist *btcoexist,
+		IN boolean sco_hid, IN boolean tx_pause, IN u8 max_interval)
+{
+	static s32		up, dn, m, n, wait_count;
+	s32			result;   /* 0: no change, +1: increase WiFi duration, -1: decrease WiFi duration */
+	u8			retry_count = 0;
+
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+		    "[BTCoex], TdmaDurationAdjust()\n");
+	BTC_TRACE(trace_buf);
+
+	coex_dm->auto_tdma_adjust_low_rssi = false;
+
+	if (!coex_dm->auto_tdma_adjust) {
+		coex_dm->auto_tdma_adjust = true;
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], first run TdmaDurationAdjust()!!\n");
+		BTC_TRACE(trace_buf);
+		{
+			if (sco_hid) {
+				if (tx_pause) {
+					if (max_interval == 1) {
+						halbtc8812a2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 13);
+						coex_dm->ps_tdma_du_adj_type =
+							13;
+					} else if (max_interval == 2) {
+						halbtc8812a2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 14);
+						coex_dm->ps_tdma_du_adj_type =
+							14;
+					} else if (max_interval == 3) {
+						halbtc8812a2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 15);
+						coex_dm->ps_tdma_du_adj_type =
+							15;
+					} else {
+						halbtc8812a2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 15);
+						coex_dm->ps_tdma_du_adj_type =
+							15;
+					}
+				} else {
+					if (max_interval == 1) {
+						halbtc8812a2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 9);
+						coex_dm->ps_tdma_du_adj_type =
+							9;
+					} else if (max_interval == 2) {
+						halbtc8812a2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 10);
+						coex_dm->ps_tdma_du_adj_type =
+							10;
+					} else if (max_interval == 3) {
+						halbtc8812a2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 11);
+						coex_dm->ps_tdma_du_adj_type =
+							11;
+					} else {
+						halbtc8812a2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 11);
+						coex_dm->ps_tdma_du_adj_type =
+							11;
+					}
+				}
+			} else {
+				if (tx_pause) {
+					if (max_interval == 1) {
+						halbtc8812a2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 5);
+						coex_dm->ps_tdma_du_adj_type =
+							5;
+					} else if (max_interval == 2) {
+						halbtc8812a2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 6);
+						coex_dm->ps_tdma_du_adj_type =
+							6;
+					} else if (max_interval == 3) {
+						halbtc8812a2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 7);
+						coex_dm->ps_tdma_du_adj_type =
+							7;
+					} else {
+						halbtc8812a2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 7);
+						coex_dm->ps_tdma_du_adj_type =
+							7;
+					}
+				} else {
+					if (max_interval == 1) {
+						halbtc8812a2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 1);
+						coex_dm->ps_tdma_du_adj_type =
+							1;
+					} else if (max_interval == 2) {
+						halbtc8812a2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 2);
+						coex_dm->ps_tdma_du_adj_type =
+							2;
+					} else if (max_interval == 3) {
+						halbtc8812a2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 3);
+						coex_dm->ps_tdma_du_adj_type =
+							3;
+					} else {
+						halbtc8812a2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 3);
+						coex_dm->ps_tdma_du_adj_type =
+							3;
+					}
+				}
+			}
+		}
+		/* ============ */
+		up = 0;
+		dn = 0;
+		m = 1;
+		n = 3;
+		result = 0;
+		wait_count = 0;
+	} else {
+		/* acquire the BT TRx retry count from BT_Info byte2 */
+		retry_count = coex_sta->bt_retry_cnt;
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], retry_count = %d\n",
+			    retry_count);
+		BTC_TRACE(trace_buf);
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			"[BTCoex], up=%d, dn=%d, m=%d, n=%d, wait_count=%d\n",
+			    up, dn, m, n, wait_count);
+		BTC_TRACE(trace_buf);
+
+		result = 0;
+		wait_count++;
+
+		if (retry_count ==
+		    0) { /* no retry in the last 2-second duration */
+			up++;
+			dn--;
+
+			if (dn <= 0)
+				dn = 0;
+
+			if (up >= n) {	/* if �s�� n ��2�� retry count��0, �h�ռeWiFi duration */
+				wait_count = 0;
+				n = 3;
+				up = 0;
+				dn = 0;
+				result = 1;
+				BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+					"[BTCoex], Increase wifi duration!!\n");
+				BTC_TRACE(trace_buf);
+			}
+		} else if (retry_count <=
+			   3) {	/* <=3 retry in the last 2-second duration */
+			up--;
+			dn++;
+
+			if (up <= 0)
+				up = 0;
+
+			if (dn == 2) {	/* if �s�� 2 ��2�� retry count< 3, �h�կ�WiFi duration */
+				if (wait_count <= 2)
+					m++; /* �קK�@���b���level���Ӧ^ */
+				else
+					m = 1;
+
+				if (m >= 20)  /* m �̤j�� = 20 ' �̤j120�� recheck�O�_�վ� WiFi duration. */
+					m = 20;
+
+				n = 3 * m;
+				up = 0;
+				dn = 0;
+				wait_count = 0;
+				result = -1;
+				BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+					"[BTCoex], Decrease wifi duration for retry_counter<3!!\n");
+				BTC_TRACE(trace_buf);
+			}
+		} else { /* retry count > 3, �u�n1�� retry count > 3, �h�կ�WiFi duration */
+			if (wait_count == 1)
+				m++; /* �קK�@���b���level���Ӧ^ */
+			else
+				m = 1;
+
+			if (m >= 20)  /* m �̤j�� = 20 ' �̤j120�� recheck�O�_�վ� WiFi duration. */
+				m = 20;
+
+			n = 3 * m;
+			up = 0;
+			dn = 0;
+			wait_count = 0;
+			result = -1;
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				"[BTCoex], Decrease wifi duration for retry_counter>3!!\n");
+			BTC_TRACE(trace_buf);
+		}
+
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], max Interval = %d\n",
+			    max_interval);
+		BTC_TRACE(trace_buf);
+
+		if (max_interval == 1) {
+			if (tx_pause) {
+				BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+					    "[BTCoex], TxPause = 1\n");
+				BTC_TRACE(trace_buf);
+
+				if (coex_dm->cur_ps_tdma == 1) {
+					halbtc8812a2ant_ps_tdma(btcoexist,
+							NORMAL_EXEC, true, 5);
+					coex_dm->ps_tdma_du_adj_type = 5;
+				} else if (coex_dm->cur_ps_tdma == 2) {
+					halbtc8812a2ant_ps_tdma(btcoexist,
+							NORMAL_EXEC, true, 6);
+					coex_dm->ps_tdma_du_adj_type = 6;
+				} else if (coex_dm->cur_ps_tdma == 3) {
+					halbtc8812a2ant_ps_tdma(btcoexist,
+							NORMAL_EXEC, true, 7);
+					coex_dm->ps_tdma_du_adj_type = 7;
+				} else if (coex_dm->cur_ps_tdma == 4) {
+					halbtc8812a2ant_ps_tdma(btcoexist,
+							NORMAL_EXEC, true, 8);
+					coex_dm->ps_tdma_du_adj_type = 8;
+				}
+				if (coex_dm->cur_ps_tdma == 9) {
+					halbtc8812a2ant_ps_tdma(btcoexist,
+							NORMAL_EXEC, true, 13);
+					coex_dm->ps_tdma_du_adj_type = 13;
+				} else if (coex_dm->cur_ps_tdma == 10) {
+					halbtc8812a2ant_ps_tdma(btcoexist,
+							NORMAL_EXEC, true, 14);
+					coex_dm->ps_tdma_du_adj_type = 14;
+				} else if (coex_dm->cur_ps_tdma == 11) {
+					halbtc8812a2ant_ps_tdma(btcoexist,
+							NORMAL_EXEC, true, 15);
+					coex_dm->ps_tdma_du_adj_type = 15;
+				} else if (coex_dm->cur_ps_tdma == 12) {
+					halbtc8812a2ant_ps_tdma(btcoexist,
+							NORMAL_EXEC, true, 16);
+					coex_dm->ps_tdma_du_adj_type = 16;
+				}
+
+				if (result == -1) {
+					if (coex_dm->cur_ps_tdma == 5) {
+						halbtc8812a2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 6);
+						coex_dm->ps_tdma_du_adj_type =
+							6;
+					} else if (coex_dm->cur_ps_tdma == 6) {
+						halbtc8812a2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 7);
+						coex_dm->ps_tdma_du_adj_type =
+							7;
+					} else if (coex_dm->cur_ps_tdma == 7) {
+						halbtc8812a2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 8);
+						coex_dm->ps_tdma_du_adj_type =
+							8;
+					} else if (coex_dm->cur_ps_tdma == 13) {
+						halbtc8812a2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 14);
+						coex_dm->ps_tdma_du_adj_type =
+							14;
+					} else if (coex_dm->cur_ps_tdma == 14) {
+						halbtc8812a2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 15);
+						coex_dm->ps_tdma_du_adj_type =
+							15;
+					} else if (coex_dm->cur_ps_tdma == 15) {
+						halbtc8812a2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 16);
+						coex_dm->ps_tdma_du_adj_type =
+							16;
+					}
+				} else if (result == 1) {
+					if (coex_dm->cur_ps_tdma == 8) {
+						halbtc8812a2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 7);
+						coex_dm->ps_tdma_du_adj_type =
+							7;
+					} else if (coex_dm->cur_ps_tdma == 7) {
+						halbtc8812a2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 6);
+						coex_dm->ps_tdma_du_adj_type =
+							6;
+					} else if (coex_dm->cur_ps_tdma == 6) {
+						halbtc8812a2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 5);
+						coex_dm->ps_tdma_du_adj_type =
+							5;
+					} else if (coex_dm->cur_ps_tdma == 16) {
+						halbtc8812a2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 15);
+						coex_dm->ps_tdma_du_adj_type =
+							15;
+					} else if (coex_dm->cur_ps_tdma == 15) {
+						halbtc8812a2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 14);
+						coex_dm->ps_tdma_du_adj_type =
+							14;
+					} else if (coex_dm->cur_ps_tdma == 14) {
+						halbtc8812a2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 13);
+						coex_dm->ps_tdma_du_adj_type =
+							13;
+					}
+				}
+			} else {
+				BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+					    "[BTCoex], TxPause = 0\n");
+				BTC_TRACE(trace_buf);
+
+				if (coex_dm->cur_ps_tdma == 5) {
+					halbtc8812a2ant_ps_tdma(btcoexist,
+							NORMAL_EXEC, true, 1);
+					coex_dm->ps_tdma_du_adj_type = 1;
+				} else if (coex_dm->cur_ps_tdma == 6) {
+					halbtc8812a2ant_ps_tdma(btcoexist,
+							NORMAL_EXEC, true, 2);
+					coex_dm->ps_tdma_du_adj_type = 2;
+				} else if (coex_dm->cur_ps_tdma == 7) {
+					halbtc8812a2ant_ps_tdma(btcoexist,
+							NORMAL_EXEC, true, 3);
+					coex_dm->ps_tdma_du_adj_type = 3;
+				} else if (coex_dm->cur_ps_tdma == 8) {
+					halbtc8812a2ant_ps_tdma(btcoexist,
+							NORMAL_EXEC, true, 4);
+					coex_dm->ps_tdma_du_adj_type = 4;
+				}
+				if (coex_dm->cur_ps_tdma == 13) {
+					halbtc8812a2ant_ps_tdma(btcoexist,
+							NORMAL_EXEC, true, 9);
+					coex_dm->ps_tdma_du_adj_type = 9;
+				} else if (coex_dm->cur_ps_tdma == 14) {
+					halbtc8812a2ant_ps_tdma(btcoexist,
+							NORMAL_EXEC, true, 10);
+					coex_dm->ps_tdma_du_adj_type = 10;
+				} else if (coex_dm->cur_ps_tdma == 15) {
+					halbtc8812a2ant_ps_tdma(btcoexist,
+							NORMAL_EXEC, true, 11);
+					coex_dm->ps_tdma_du_adj_type = 11;
+				} else if (coex_dm->cur_ps_tdma == 16) {
+					halbtc8812a2ant_ps_tdma(btcoexist,
+							NORMAL_EXEC, true, 12);
+					coex_dm->ps_tdma_du_adj_type = 12;
+				}
+
+				if (result == -1) {
+					if (coex_dm->cur_ps_tdma == 1) {
+						halbtc8812a2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 2);
+						coex_dm->ps_tdma_du_adj_type =
+							2;
+					} else if (coex_dm->cur_ps_tdma == 2) {
+						halbtc8812a2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 3);
+						coex_dm->ps_tdma_du_adj_type =
+							3;
+					} else if (coex_dm->cur_ps_tdma == 3) {
+						halbtc8812a2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 4);
+						coex_dm->ps_tdma_du_adj_type =
+							4;
+					} else if (coex_dm->cur_ps_tdma == 9) {
+						halbtc8812a2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 10);
+						coex_dm->ps_tdma_du_adj_type =
+							10;
+					} else if (coex_dm->cur_ps_tdma == 10) {
+						halbtc8812a2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 11);
+						coex_dm->ps_tdma_du_adj_type =
+							11;
+					} else if (coex_dm->cur_ps_tdma == 11) {
+						halbtc8812a2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 12);
+						coex_dm->ps_tdma_du_adj_type =
+							12;
+					}
+				} else if (result == 1) {
+					if (coex_dm->cur_ps_tdma == 4) {
+						halbtc8812a2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 3);
+						coex_dm->ps_tdma_du_adj_type =
+							3;
+					} else if (coex_dm->cur_ps_tdma == 3) {
+						halbtc8812a2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 2);
+						coex_dm->ps_tdma_du_adj_type =
+							2;
+					} else if (coex_dm->cur_ps_tdma == 2) {
+						halbtc8812a2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 1);
+						coex_dm->ps_tdma_du_adj_type =
+							1;
+					} else if (coex_dm->cur_ps_tdma == 12) {
+						halbtc8812a2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 11);
+						coex_dm->ps_tdma_du_adj_type =
+							11;
+					} else if (coex_dm->cur_ps_tdma == 11) {
+						halbtc8812a2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 10);
+						coex_dm->ps_tdma_du_adj_type =
+							10;
+					} else if (coex_dm->cur_ps_tdma == 10) {
+						halbtc8812a2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 9);
+						coex_dm->ps_tdma_du_adj_type =
+							9;
+					}
+				}
+			}
+		} else if (max_interval == 2) {
+			if (tx_pause) {
+				BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+					    "[BTCoex], TxPause = 1\n");
+				BTC_TRACE(trace_buf);
+
+				if (coex_dm->cur_ps_tdma == 1) {
+					halbtc8812a2ant_ps_tdma(btcoexist,
+							NORMAL_EXEC, true, 6);
+					coex_dm->ps_tdma_du_adj_type = 6;
+				} else if (coex_dm->cur_ps_tdma == 2) {
+					halbtc8812a2ant_ps_tdma(btcoexist,
+							NORMAL_EXEC, true, 6);
+					coex_dm->ps_tdma_du_adj_type = 6;
+				} else if (coex_dm->cur_ps_tdma == 3) {
+					halbtc8812a2ant_ps_tdma(btcoexist,
+							NORMAL_EXEC, true, 7);
+					coex_dm->ps_tdma_du_adj_type = 7;
+				} else if (coex_dm->cur_ps_tdma == 4) {
+					halbtc8812a2ant_ps_tdma(btcoexist,
+							NORMAL_EXEC, true, 8);
+					coex_dm->ps_tdma_du_adj_type = 8;
+				}
+				if (coex_dm->cur_ps_tdma == 9) {
+					halbtc8812a2ant_ps_tdma(btcoexist,
+							NORMAL_EXEC, true, 14);
+					coex_dm->ps_tdma_du_adj_type = 14;
+				} else if (coex_dm->cur_ps_tdma == 10) {
+					halbtc8812a2ant_ps_tdma(btcoexist,
+							NORMAL_EXEC, true, 14);
+					coex_dm->ps_tdma_du_adj_type = 14;
+				} else if (coex_dm->cur_ps_tdma == 11) {
+					halbtc8812a2ant_ps_tdma(btcoexist,
+							NORMAL_EXEC, true, 15);
+					coex_dm->ps_tdma_du_adj_type = 15;
+				} else if (coex_dm->cur_ps_tdma == 12) {
+					halbtc8812a2ant_ps_tdma(btcoexist,
+							NORMAL_EXEC, true, 16);
+					coex_dm->ps_tdma_du_adj_type = 16;
+				}
+				if (result == -1) {
+					if (coex_dm->cur_ps_tdma == 5) {
+						halbtc8812a2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 6);
+						coex_dm->ps_tdma_du_adj_type =
+							6;
+					} else if (coex_dm->cur_ps_tdma == 6) {
+						halbtc8812a2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 7);
+						coex_dm->ps_tdma_du_adj_type =
+							7;
+					} else if (coex_dm->cur_ps_tdma == 7) {
+						halbtc8812a2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 8);
+						coex_dm->ps_tdma_du_adj_type =
+							8;
+					} else if (coex_dm->cur_ps_tdma == 13) {
+						halbtc8812a2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 14);
+						coex_dm->ps_tdma_du_adj_type =
+							14;
+					} else if (coex_dm->cur_ps_tdma == 14) {
+						halbtc8812a2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 15);
+						coex_dm->ps_tdma_du_adj_type =
+							15;
+					} else if (coex_dm->cur_ps_tdma == 15) {
+						halbtc8812a2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 16);
+						coex_dm->ps_tdma_du_adj_type =
+							16;
+					}
+				} else if (result == 1) {
+					if (coex_dm->cur_ps_tdma == 8) {
+						halbtc8812a2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 7);
+						coex_dm->ps_tdma_du_adj_type =
+							7;
+					} else if (coex_dm->cur_ps_tdma == 7) {
+						halbtc8812a2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 6);
+						coex_dm->ps_tdma_du_adj_type =
+							6;
+					} else if (coex_dm->cur_ps_tdma == 6) {
+						halbtc8812a2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 6);
+						coex_dm->ps_tdma_du_adj_type =
+							6;
+					} else if (coex_dm->cur_ps_tdma == 16) {
+						halbtc8812a2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 15);
+						coex_dm->ps_tdma_du_adj_type =
+							15;
+					} else if (coex_dm->cur_ps_tdma == 15) {
+						halbtc8812a2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 14);
+						coex_dm->ps_tdma_du_adj_type =
+							14;
+					} else if (coex_dm->cur_ps_tdma == 14) {
+						halbtc8812a2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 14);
+						coex_dm->ps_tdma_du_adj_type =
+							14;
+					}
+				}
+			} else {
+				BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+					    "[BTCoex], TxPause = 0\n");
+				BTC_TRACE(trace_buf);
+
+				if (coex_dm->cur_ps_tdma == 5) {
+					halbtc8812a2ant_ps_tdma(btcoexist,
+							NORMAL_EXEC, true, 2);
+					coex_dm->ps_tdma_du_adj_type = 2;
+				} else if (coex_dm->cur_ps_tdma == 6) {
+					halbtc8812a2ant_ps_tdma(btcoexist,
+							NORMAL_EXEC, true, 2);
+					coex_dm->ps_tdma_du_adj_type = 2;
+				} else if (coex_dm->cur_ps_tdma == 7) {
+					halbtc8812a2ant_ps_tdma(btcoexist,
+							NORMAL_EXEC, true, 3);
+					coex_dm->ps_tdma_du_adj_type = 3;
+				} else if (coex_dm->cur_ps_tdma == 8) {
+					halbtc8812a2ant_ps_tdma(btcoexist,
+							NORMAL_EXEC, true, 4);
+					coex_dm->ps_tdma_du_adj_type = 4;
+				}
+				if (coex_dm->cur_ps_tdma == 13) {
+					halbtc8812a2ant_ps_tdma(btcoexist,
+							NORMAL_EXEC, true, 10);
+					coex_dm->ps_tdma_du_adj_type = 10;
+				} else if (coex_dm->cur_ps_tdma == 14) {
+					halbtc8812a2ant_ps_tdma(btcoexist,
+							NORMAL_EXEC, true, 10);
+					coex_dm->ps_tdma_du_adj_type = 10;
+				} else if (coex_dm->cur_ps_tdma == 15) {
+					halbtc8812a2ant_ps_tdma(btcoexist,
+							NORMAL_EXEC, true, 11);
+					coex_dm->ps_tdma_du_adj_type = 11;
+				} else if (coex_dm->cur_ps_tdma == 16) {
+					halbtc8812a2ant_ps_tdma(btcoexist,
+							NORMAL_EXEC, true, 12);
+					coex_dm->ps_tdma_du_adj_type = 12;
+				}
+				if (result == -1) {
+					if (coex_dm->cur_ps_tdma == 1) {
+						halbtc8812a2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 2);
+						coex_dm->ps_tdma_du_adj_type =
+							2;
+					} else if (coex_dm->cur_ps_tdma == 2) {
+						halbtc8812a2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 3);
+						coex_dm->ps_tdma_du_adj_type =
+							3;
+					} else if (coex_dm->cur_ps_tdma == 3) {
+						halbtc8812a2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 4);
+						coex_dm->ps_tdma_du_adj_type =
+							4;
+					} else if (coex_dm->cur_ps_tdma == 9) {
+						halbtc8812a2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 10);
+						coex_dm->ps_tdma_du_adj_type =
+							10;
+					} else if (coex_dm->cur_ps_tdma == 10) {
+						halbtc8812a2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 11);
+						coex_dm->ps_tdma_du_adj_type =
+							11;
+					} else if (coex_dm->cur_ps_tdma == 11) {
+						halbtc8812a2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 12);
+						coex_dm->ps_tdma_du_adj_type =
+							12;
+					}
+				} else if (result == 1) {
+					if (coex_dm->cur_ps_tdma == 4) {
+						halbtc8812a2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 3);
+						coex_dm->ps_tdma_du_adj_type =
+							3;
+					} else if (coex_dm->cur_ps_tdma == 3) {
+						halbtc8812a2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 2);
+						coex_dm->ps_tdma_du_adj_type =
+							2;
+					} else if (coex_dm->cur_ps_tdma == 2) {
+						halbtc8812a2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 2);
+						coex_dm->ps_tdma_du_adj_type =
+							2;
+					} else if (coex_dm->cur_ps_tdma == 12) {
+						halbtc8812a2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 11);
+						coex_dm->ps_tdma_du_adj_type =
+							11;
+					} else if (coex_dm->cur_ps_tdma == 11) {
+						halbtc8812a2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 10);
+						coex_dm->ps_tdma_du_adj_type =
+							10;
+					} else if (coex_dm->cur_ps_tdma == 10) {
+						halbtc8812a2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 10);
+						coex_dm->ps_tdma_du_adj_type =
+							10;
+					}
+				}
+			}
+		} else if (max_interval == 3) {
+			if (tx_pause) {
+				BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+					    "[BTCoex], TxPause = 1\n");
+				BTC_TRACE(trace_buf);
+
+				if (coex_dm->cur_ps_tdma == 1) {
+					halbtc8812a2ant_ps_tdma(btcoexist,
+							NORMAL_EXEC, true, 7);
+					coex_dm->ps_tdma_du_adj_type = 7;
+				} else if (coex_dm->cur_ps_tdma == 2) {
+					halbtc8812a2ant_ps_tdma(btcoexist,
+							NORMAL_EXEC, true, 7);
+					coex_dm->ps_tdma_du_adj_type = 7;
+				} else if (coex_dm->cur_ps_tdma == 3) {
+					halbtc8812a2ant_ps_tdma(btcoexist,
+							NORMAL_EXEC, true, 7);
+					coex_dm->ps_tdma_du_adj_type = 7;
+				} else if (coex_dm->cur_ps_tdma == 4) {
+					halbtc8812a2ant_ps_tdma(btcoexist,
+							NORMAL_EXEC, true, 8);
+					coex_dm->ps_tdma_du_adj_type = 8;
+				}
+				if (coex_dm->cur_ps_tdma == 9) {
+					halbtc8812a2ant_ps_tdma(btcoexist,
+							NORMAL_EXEC, true, 15);
+					coex_dm->ps_tdma_du_adj_type = 15;
+				} else if (coex_dm->cur_ps_tdma == 10) {
+					halbtc8812a2ant_ps_tdma(btcoexist,
+							NORMAL_EXEC, true, 15);
+					coex_dm->ps_tdma_du_adj_type = 15;
+				} else if (coex_dm->cur_ps_tdma == 11) {
+					halbtc8812a2ant_ps_tdma(btcoexist,
+							NORMAL_EXEC, true, 15);
+					coex_dm->ps_tdma_du_adj_type = 15;
+				} else if (coex_dm->cur_ps_tdma == 12) {
+					halbtc8812a2ant_ps_tdma(btcoexist,
+							NORMAL_EXEC, true, 16);
+					coex_dm->ps_tdma_du_adj_type = 16;
+				}
+				if (result == -1) {
+					if (coex_dm->cur_ps_tdma == 5) {
+						halbtc8812a2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 7);
+						coex_dm->ps_tdma_du_adj_type =
+							7;
+					} else if (coex_dm->cur_ps_tdma == 6) {
+						halbtc8812a2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 7);
+						coex_dm->ps_tdma_du_adj_type =
+							7;
+					} else if (coex_dm->cur_ps_tdma == 7) {
+						halbtc8812a2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 8);
+						coex_dm->ps_tdma_du_adj_type =
+							8;
+					} else if (coex_dm->cur_ps_tdma == 13) {
+						halbtc8812a2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 15);
+						coex_dm->ps_tdma_du_adj_type =
+							15;
+					} else if (coex_dm->cur_ps_tdma == 14) {
+						halbtc8812a2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 15);
+						coex_dm->ps_tdma_du_adj_type =
+							15;
+					} else if (coex_dm->cur_ps_tdma == 15) {
+						halbtc8812a2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 16);
+						coex_dm->ps_tdma_du_adj_type =
+							16;
+					}
+				} else if (result == 1) {
+					if (coex_dm->cur_ps_tdma == 8) {
+						halbtc8812a2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 7);
+						coex_dm->ps_tdma_du_adj_type =
+							7;
+					} else if (coex_dm->cur_ps_tdma == 7) {
+						halbtc8812a2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 7);
+						coex_dm->ps_tdma_du_adj_type =
+							7;
+					} else if (coex_dm->cur_ps_tdma == 6) {
+						halbtc8812a2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 7);
+						coex_dm->ps_tdma_du_adj_type =
+							7;
+					} else if (coex_dm->cur_ps_tdma == 16) {
+						halbtc8812a2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 15);
+						coex_dm->ps_tdma_du_adj_type =
+							15;
+					} else if (coex_dm->cur_ps_tdma == 15) {
+						halbtc8812a2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 15);
+						coex_dm->ps_tdma_du_adj_type =
+							15;
+					} else if (coex_dm->cur_ps_tdma == 14) {
+						halbtc8812a2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 15);
+						coex_dm->ps_tdma_du_adj_type =
+							15;
+					}
+				}
+			} else {
+				BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+					    "[BTCoex], TxPause = 0\n");
+				BTC_TRACE(trace_buf);
+
+				if (coex_dm->cur_ps_tdma == 5) {
+					halbtc8812a2ant_ps_tdma(btcoexist,
+							NORMAL_EXEC, true, 3);
+					coex_dm->ps_tdma_du_adj_type = 3;
+				} else if (coex_dm->cur_ps_tdma == 6) {
+					halbtc8812a2ant_ps_tdma(btcoexist,
+							NORMAL_EXEC, true, 3);
+					coex_dm->ps_tdma_du_adj_type = 3;
+				} else if (coex_dm->cur_ps_tdma == 7) {
+					halbtc8812a2ant_ps_tdma(btcoexist,
+							NORMAL_EXEC, true, 3);
+					coex_dm->ps_tdma_du_adj_type = 3;
+				} else if (coex_dm->cur_ps_tdma == 8) {
+					halbtc8812a2ant_ps_tdma(btcoexist,
+							NORMAL_EXEC, true, 4);
+					coex_dm->ps_tdma_du_adj_type = 4;
+				}
+				if (coex_dm->cur_ps_tdma == 13) {
+					halbtc8812a2ant_ps_tdma(btcoexist,
+							NORMAL_EXEC, true, 11);
+					coex_dm->ps_tdma_du_adj_type = 11;
+				} else if (coex_dm->cur_ps_tdma == 14) {
+					halbtc8812a2ant_ps_tdma(btcoexist,
+							NORMAL_EXEC, true, 11);
+					coex_dm->ps_tdma_du_adj_type = 11;
+				} else if (coex_dm->cur_ps_tdma == 15) {
+					halbtc8812a2ant_ps_tdma(btcoexist,
+							NORMAL_EXEC, true, 11);
+					coex_dm->ps_tdma_du_adj_type = 11;
+				} else if (coex_dm->cur_ps_tdma == 16) {
+					halbtc8812a2ant_ps_tdma(btcoexist,
+							NORMAL_EXEC, true, 12);
+					coex_dm->ps_tdma_du_adj_type = 12;
+				}
+				if (result == -1) {
+					if (coex_dm->cur_ps_tdma == 1) {
+						halbtc8812a2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 3);
+						coex_dm->ps_tdma_du_adj_type =
+							3;
+					} else if (coex_dm->cur_ps_tdma == 2) {
+						halbtc8812a2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 3);
+						coex_dm->ps_tdma_du_adj_type =
+							3;
+					} else if (coex_dm->cur_ps_tdma == 3) {
+						halbtc8812a2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 4);
+						coex_dm->ps_tdma_du_adj_type =
+							4;
+					} else if (coex_dm->cur_ps_tdma == 9) {
+						halbtc8812a2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 11);
+						coex_dm->ps_tdma_du_adj_type =
+							11;
+					} else if (coex_dm->cur_ps_tdma == 10) {
+						halbtc8812a2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 11);
+						coex_dm->ps_tdma_du_adj_type =
+							11;
+					} else if (coex_dm->cur_ps_tdma == 11) {
+						halbtc8812a2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 12);
+						coex_dm->ps_tdma_du_adj_type =
+							12;
+					}
+				} else if (result == 1) {
+					if (coex_dm->cur_ps_tdma == 4) {
+						halbtc8812a2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 3);
+						coex_dm->ps_tdma_du_adj_type =
+							3;
+					} else if (coex_dm->cur_ps_tdma == 3) {
+						halbtc8812a2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 3);
+						coex_dm->ps_tdma_du_adj_type =
+							3;
+					} else if (coex_dm->cur_ps_tdma == 2) {
+						halbtc8812a2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 3);
+						coex_dm->ps_tdma_du_adj_type =
+							3;
+					} else if (coex_dm->cur_ps_tdma == 12) {
+						halbtc8812a2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 11);
+						coex_dm->ps_tdma_du_adj_type =
+							11;
+					} else if (coex_dm->cur_ps_tdma == 11) {
+						halbtc8812a2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 11);
+						coex_dm->ps_tdma_du_adj_type =
+							11;
+					} else if (coex_dm->cur_ps_tdma == 10) {
+						halbtc8812a2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 11);
+						coex_dm->ps_tdma_du_adj_type =
+							11;
+					}
+				}
+			}
+		}
+	}
+
+	/* if current PsTdma not match with the recorded one (when scan, dhcp...), */
+	/* then we have to adjust it back to the previous record one. */
+	if (coex_dm->cur_ps_tdma != coex_dm->ps_tdma_du_adj_type) {
+		boolean	scan = false, link = false, roam = false;
+
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			"[BTCoex], PsTdma type dismatch!!!, cur_ps_tdma=%d, recordPsTdma=%d\n",
+			    coex_dm->cur_ps_tdma, coex_dm->ps_tdma_du_adj_type);
+		BTC_TRACE(trace_buf);
+
+		btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_SCAN, &scan);
+		btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_LINK, &link);
+		btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_ROAM, &roam);
+
+		if (!scan && !link && !roam)
+			halbtc8812a2ant_ps_tdma(btcoexist, NORMAL_EXEC, true,
+						coex_dm->ps_tdma_du_adj_type);
+		else {
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				"[BTCoex], roaming/link/scan is under progress, will adjust next time!!!\n");
+			BTC_TRACE(trace_buf);
+		}
+	}
+}
+
+/* ******************
+ * pstdma for wifi rssi low
+ * ****************** */
+void halbtc8812a2ant_tdma_duration_adjust_for_wifi_rssi_low(
+	IN struct btc_coexist *btcoexist/* , */ /* IN u8 wifi_status */)
+{
+	static s32		up, dn, m, n, wait_count;
+	s32			result;   /* 0: no change, +1: increase WiFi duration, -1: decrease WiFi duration */
+	u8			retry_count = 0, bt_info_ext;
+
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+		"[BTCoex], halbtc8812a2ant_tdma_duration_adjust_for_wifi_rssi_low()\n");
+	BTC_TRACE(trace_buf);
+#if 0
+	if ((BT_8812A_2ANT_WIFI_STATUS_NON_CONNECTED_ASSO_AUTH_SCAN ==
+	     wifi_status) ||
+	    (BT_8812A_2ANT_WIFI_STATUS_CONNECTED_SCAN == wifi_status) ||
+	    (BT_8812A_2ANT_WIFI_STATUS_CONNECTED_SPECIAL_PKT ==
+	     wifi_status)) {
+		if (coex_dm->cur_ps_tdma != 81 &&
+		    coex_dm->cur_ps_tdma != 82 &&
+		    coex_dm->cur_ps_tdma != 83 &&
+		    coex_dm->cur_ps_tdma != 84) {
+			halbtc8812a2ant_ps_tdma(btcoexist, NORMAL_EXEC, true,
+						82);
+			coex_dm->ps_tdma_du_adj_type = 82;
+
+			up = 0;
+			dn = 0;
+			m = 1;
+			n = 3;
+			result = 0;
+			wait_count = 0;
+		}
+		return;
+	}
+#endif
+	coex_dm->auto_tdma_adjust = false;
+
+	retry_count = coex_sta->bt_retry_cnt;
+	bt_info_ext = coex_sta->bt_info_ext;
+
+	if (!coex_dm->auto_tdma_adjust_low_rssi) {
+		coex_dm->auto_tdma_adjust_low_rssi = true;
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			"[BTCoex], first run TdmaDurationAdjustForWifiRssiLow()!!\n");
+		BTC_TRACE(trace_buf);
+
+		if (BT_INFO_8812A_2ANT_A2DP_BASIC_RATE(bt_info_ext)) {
+			halbtc8812a2ant_ps_tdma(btcoexist, NORMAL_EXEC, true,
+						83);
+			coex_dm->ps_tdma_du_adj_type = 83;
+		} else {
+			halbtc8812a2ant_ps_tdma(btcoexist, NORMAL_EXEC, true,
+						82);
+			coex_dm->ps_tdma_du_adj_type = 82;
+		}
+		/* ============ */
+		up = 0;
+		dn = 0;
+		m = 1;
+		n = 3;
+		result = 0;
+		wait_count = 0;
+	} else {
+		/* acquire the BT TRx retry count from BT_Info byte2
+		*		retry_count = coex_sta->bt_retry_cnt;
+		*		bt_info_ext = coex_sta->bt_info_ext; */
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], retry_count = %d\n",
+			    retry_count);
+		BTC_TRACE(trace_buf);
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			"[BTCoex], up=%d, dn=%d, m=%d, n=%d, wait_count=%d\n",
+			    up, dn, m, n, wait_count);
+		BTC_TRACE(trace_buf);
+		result = 0;
+		wait_count++;
+
+		if ((coex_sta->low_priority_tx) > 1050 ||
+		    (coex_sta->low_priority_rx) > 1250)
+			retry_count++;
+
+		if (retry_count ==
+		    0) { /* no retry in the last 2-second duration */
+			up++;
+			dn--;
+
+			if (dn <= 0)
+				dn = 0;
+
+			if (up >= n) {	/* if �s�� n ��2�� retry count��0, �h�ռeWiFi duration */
+				wait_count = 0;
+				n = 3;
+				up = 0;
+				dn = 0;
+				result = 1;
+				BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+					"[BTCoex], Increase wifi duration!!\n");
+				BTC_TRACE(trace_buf);
+			}
+		} else if (retry_count <=
+			   3) {	/* <=3 retry in the last 2-second duration */
+			up--;
+			dn++;
+
+			if (up <= 0)
+				up = 0;
+
+			if (dn == 2) {	/* if �s�� 2 ��2�� retry count< 3, �h�կ�WiFi duration */
+				if (wait_count <= 2)
+					m++; /* �קK�@���b���level���Ӧ^ */
+				else
+					m = 1;
+
+				if (m >= 20)  /* m �̤j�� = 20 ' �̤j120�� recheck�O�_�վ� WiFi duration. */
+					m = 20;
+
+				n = 3 * m;
+				up = 0;
+				dn = 0;
+				wait_count = 0;
+				result = -1;
+				BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+					"[BTCoex], Decrease wifi duration for retry_counter<3!!\n");
+				BTC_TRACE(trace_buf);
+			}
+		} else { /* retry count > 3, �u�n1�� retry count > 3, �h�կ�WiFi duration */
+			if (wait_count == 1)
+				m++; /* �קK�@���b���level���Ӧ^ */
+			else
+				m = 1;
+
+			if (m >= 20)  /* m �̤j�� = 20 ' �̤j120�� recheck�O�_�վ� WiFi duration. */
+				m = 20;
+
+			n = 3 * m;
+			up = 0;
+			dn = 0;
+			wait_count = 0;
+			result = -1;
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				"[BTCoex], Decrease wifi duration for retry_counter>3!!\n");
+			BTC_TRACE(trace_buf);
+		}
+
+		if (result == -1) {
+			/*
+						if( (BT_INFO_8812A_2ANT_A2DP_BASIC_RATE(bt_info_ext)) &&
+							((coex_dm->cur_ps_tdma == 81) ||(coex_dm->cur_ps_tdma == 82)) )
+						{
+							halbtc8812a2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 84);
+							coex_dm->ps_tdma_du_adj_type = 84;
+						}
+			*/
+			if (coex_dm->cur_ps_tdma == 80) {
+				halbtc8812a2ant_ps_tdma(btcoexist, NORMAL_EXEC,
+							true, 82);
+				coex_dm->ps_tdma_du_adj_type = 82;
+			} else if (coex_dm->cur_ps_tdma == 81) {
+				halbtc8812a2ant_ps_tdma(btcoexist, NORMAL_EXEC,
+							true, 82);
+				coex_dm->ps_tdma_du_adj_type = 82;
+			} else if (coex_dm->cur_ps_tdma == 82) {
+				halbtc8812a2ant_ps_tdma(btcoexist, NORMAL_EXEC,
+							true, 83);
+				coex_dm->ps_tdma_du_adj_type = 83;
+			} else if (coex_dm->cur_ps_tdma == 83) {
+				halbtc8812a2ant_ps_tdma(btcoexist, NORMAL_EXEC,
+							true, 84);
+				coex_dm->ps_tdma_du_adj_type = 84;
+			}
+		} else if (result == 1) {
+			/*
+						if( (BT_INFO_8812A_2ANT_A2DP_BASIC_RATE(bt_info_ext)) &&
+							((coex_dm->cur_ps_tdma == 81) ||(coex_dm->cur_ps_tdma == 82)) )
+						{
+							halbtc8812a2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 83);
+							coex_dm->ps_tdma_du_adj_type = 83;
+						}
+			*/
+			if (coex_dm->cur_ps_tdma == 84) {
+				halbtc8812a2ant_ps_tdma(btcoexist, NORMAL_EXEC,
+							true, 83);
+				coex_dm->ps_tdma_du_adj_type = 83;
+			} else if (coex_dm->cur_ps_tdma == 83) {
+				halbtc8812a2ant_ps_tdma(btcoexist, NORMAL_EXEC,
+							true, 82);
+				coex_dm->ps_tdma_du_adj_type = 82;
+			} else if (coex_dm->cur_ps_tdma == 82) {
+				halbtc8812a2ant_ps_tdma(btcoexist, NORMAL_EXEC,
+							true, 81);
+				coex_dm->ps_tdma_du_adj_type = 81;
+			} else if ((coex_dm->cur_ps_tdma == 81) &&
+				   ((coex_sta->scan_ap_num <= 5))) {
+				halbtc8812a2ant_ps_tdma(btcoexist, NORMAL_EXEC,
+							true, 81);
+				coex_dm->ps_tdma_du_adj_type = 81;
+			}
+		}
+
+		if (coex_dm->cur_ps_tdma != 80 &&
+		    coex_dm->cur_ps_tdma != 81 &&
+		    coex_dm->cur_ps_tdma != 82 &&
+		    coex_dm->cur_ps_tdma != 83 &&
+		    coex_dm->cur_ps_tdma != 84) {
+			/* recover to previous adjust type */
+			halbtc8812a2ant_ps_tdma(btcoexist, NORMAL_EXEC, true,
+						coex_dm->ps_tdma_du_adj_type);
+		}
+	}
+}
+
+void halbtc8812a2ant_get_bt_rssi_threshold(IN struct btc_coexist *btcoexist,
+		IN u8 *pThres0, IN u8 *pThres1)
+{
+	u8 ant_type;
+
+	btcoexist->btc_get(btcoexist, BTC_GET_U1_ANT_TYPE, &ant_type);
+
+
+	switch (ant_type) {
+	case BTC_ANT_TYPE_0:
+		*pThres0 = 100;
+		*pThres1 = 100;
+		break;
+	case BTC_ANT_TYPE_1:
+		*pThres0 = 34;
+		*pThres1 = 42;
+		break;
+	case BTC_ANT_TYPE_2:
+		*pThres0 = 34;
+		*pThres1 = 42;
+		break;
+	case BTC_ANT_TYPE_3:
+		*pThres0 = 34;
+		*pThres1 = 42;
+		break;
+	case BTC_ANT_TYPE_4:
+		*pThres0 = 34;
+		*pThres1 = 42;
+		break;
+	default:
+		break;
+	}
+}
+
+
+
+void halbtc8812a2ant_action_sco(IN struct btc_coexist *btcoexist)
+{
+	u8		wifi_rssi_state = BTC_RSSI_STATE_HIGH,
+			bt_rssi_state = BTC_RSSI_STATE_HIGH;
+	u32		wifi_bw;
+	u8		bt_thresh0 = 0, bt_thresh1 = 0;
+
+
+	/*	halbtc8812a2ant_get_bt_rssi_threshold(btcoexist, &bt_thresh0, &bt_thresh1); */
+	bt_rssi_state = halbtc8812a2ant_bt_rssi_state(3, bt_thresh0,
+			bt_thresh1);
+
+	wifi_rssi_state = halbtc8812a2ant_wifi_rssi_state(btcoexist, 0, 2, 34,
+			  0);
+	bt_rssi_state = halbtc8812a2ant_bt_rssi_state(3, 34, 42);
+
+	/* power save state */
+	halbtc8812a2ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, 0x0,
+					 0x0);
+
+	/* coex table */
+	if (BTC_RSSI_LOW(bt_rssi_state))
+		halbtc8812a2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 5);
+	else
+		halbtc8812a2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4);
+
+	/* pstdma */
+	if (BTC_RSSI_LOW(bt_rssi_state))
+		halbtc8812a2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 13);
+	else
+		halbtc8812a2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 9);
+
+	/* decrease BT power */
+	if (BTC_RSSI_LOW(bt_rssi_state))
+		halbtc8812a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);
+	else if (BTC_RSSI_MEDIUM(bt_rssi_state))
+		halbtc8812a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2);
+	else
+		halbtc8812a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 4);
+
+	/* limited Rx */
+	halbtc8812a2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, 0x8);
+
+	/* fw dac swing level */
+	halbtc8812a2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6);
+
+
+	btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw);
+	/* sw mechanism */
+	if (BTC_WIFI_BW_HT40 == wifi_bw) {
+		if (BTC_RSSI_HIGH(wifi_rssi_state)) {
+			halbtc8812a2ant_sw_mechanism1(btcoexist, true, true,
+						      false, false);
+			halbtc8812a2ant_sw_mechanism2(btcoexist, true, false,
+						      true, 0x6);
+		} else {
+			halbtc8812a2ant_sw_mechanism1(btcoexist, true, true,
+						      false, false);
+			halbtc8812a2ant_sw_mechanism2(btcoexist, false, false,
+						      true, 0x6);
+		}
+	} else {
+		if (BTC_RSSI_HIGH(wifi_rssi_state)) {
+			halbtc8812a2ant_sw_mechanism1(btcoexist, false, true,
+						      false, false);
+			halbtc8812a2ant_sw_mechanism2(btcoexist, true, false,
+						      true, 0x6);
+		} else {
+			halbtc8812a2ant_sw_mechanism1(btcoexist, false, true,
+						      false, false);
+			halbtc8812a2ant_sw_mechanism2(btcoexist, false, false,
+						      true, 0x6);
+		}
+	}
+}
+
+void halbtc8812a2ant_action_sco_hid(IN struct btc_coexist *btcoexist)
+{
+	u8		wifi_rssi_state = BTC_RSSI_STATE_HIGH,
+			bt_rssi_state = BTC_RSSI_STATE_HIGH;
+	u32		wifi_bw;
+	u8		bt_thresh0 = 0, bt_thresh1 = 0;
+
+	/*	halbtc8812a2ant_get_bt_rssi_threshold(btcoexist, &bt_thresh0, &bt_thresh1); */
+	bt_rssi_state = halbtc8812a2ant_bt_rssi_state(3, bt_thresh0,
+			bt_thresh1);
+
+	wifi_rssi_state = halbtc8812a2ant_wifi_rssi_state(btcoexist, 0, 2, 34,
+			  0);
+	bt_rssi_state = halbtc8812a2ant_bt_rssi_state(3, 34, 42);
+
+	/* power save state */
+	halbtc8812a2ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, 0x0,
+					 0x0);
+
+	/* coex table */
+	halbtc8812a2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4);
+
+	/* pstdma */
+	if (BTC_RSSI_LOW(bt_rssi_state))
+		halbtc8812a2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 13);
+	else
+		halbtc8812a2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 9);
+
+	/* decrease BT power	 */
+	if (BTC_RSSI_LOW(bt_rssi_state))
+		halbtc8812a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);
+	else if (BTC_RSSI_MEDIUM(bt_rssi_state))
+		halbtc8812a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2);
+	else
+		halbtc8812a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 4);
+
+	/* limited Rx */
+	halbtc8812a2ant_limited_rx(btcoexist, NORMAL_EXEC, false, true, 0x8);
+
+	/* fw dac swing level */
+	halbtc8812a2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6);
+
+
+	btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw);
+	/* sw mechanism */
+	if (BTC_WIFI_BW_HT40 == wifi_bw) {
+		if (BTC_RSSI_HIGH(wifi_rssi_state)) {
+			halbtc8812a2ant_sw_mechanism1(btcoexist, true, true,
+						      false, false);
+			halbtc8812a2ant_sw_mechanism2(btcoexist, true, false,
+						      false, 0x6);
+		} else {
+			halbtc8812a2ant_sw_mechanism1(btcoexist, true, true,
+						      false, false);
+			halbtc8812a2ant_sw_mechanism2(btcoexist, false, false,
+						      false, 0x6);
+		}
+	} else {
+		if (BTC_RSSI_HIGH(wifi_rssi_state)) {
+			halbtc8812a2ant_sw_mechanism1(btcoexist, false, true,
+						      false, false);
+			halbtc8812a2ant_sw_mechanism2(btcoexist, true, false,
+						      false, 0x6);
+		} else {
+			halbtc8812a2ant_sw_mechanism1(btcoexist, false, true,
+						      false, false);
+			halbtc8812a2ant_sw_mechanism2(btcoexist, false, false,
+						      false, 0x6);
+		}
+	}
+}
+
+void halbtc8812a2ant_action_hid(IN struct btc_coexist *btcoexist)
+{
+	u8		wifi_rssi_state = BTC_RSSI_STATE_HIGH,
+			bt_rssi_state = BTC_RSSI_STATE_HIGH;
+	u32		wifi_bw;
+	u8		anttype = 0;
+
+
+	btcoexist->btc_get(btcoexist, BTC_GET_U1_ANT_TYPE, &anttype);
+
+
+	/*	halbtc8812a2ant_get_bt_rssi_threshold(btcoexist, &bt_thresh0, &bt_thresh1);
+	 *	bt_rssi_state = halbtc8812a2ant_bt_rssi_state(3, bt_thresh0, bt_thresh1); */
+
+	wifi_rssi_state = halbtc8812a2ant_wifi_rssi_state(btcoexist, 0, 2, 34,
+			  0);
+	bt_rssi_state = halbtc8812a2ant_bt_rssi_state(3, 34, 42);
+
+
+	if (anttype == 0) { /* ANTTYPE = 0   92E 2ant with SPDT */
+		/* power save state & pstdma & coex table */
+		coex_dm->auto_tdma_adjust = false;
+		coex_dm->auto_tdma_adjust_low_rssi = false;
+		halbtc8812a2ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE,
+						 0x0, 0x0);
+		halbtc8812a2ant_ps_tdma(btcoexist, FORCE_EXEC, false, 0);
+		halbtc8812a2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0);
+	} else if (anttype ==
+		1) { /* 92E 2ant with coupler and bad ant. isolation, 92E 3ant with bad ant. isolation */
+		/* power save state & pstdma & coex table */
+		coex_dm->auto_tdma_adjust = false;
+		coex_dm->auto_tdma_adjust_low_rssi = false;
+		halbtc8812a2ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE,
+						 0x0, 0x0);
+		halbtc8812a2ant_ps_tdma(btcoexist, FORCE_EXEC, false, 0);
+		halbtc8812a2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0);
+	} else if (anttype ==
+		2) { /* ANTTYPE = 2, 92E 2ant with coupler and normal/good ant. isolation, 92E 3ant with normal ant. isolation */
+		/* power save state & pstdma & coex table */
+		if (BTC_RSSI_HIGH(wifi_rssi_state) &&
+		    (!BTC_RSSI_LOW(bt_rssi_state)) &&
+		    (coex_sta->scan_ap_num < NOISY_AP_NUM_THRESH_8812A)) {
+			/* WIFI RSSI = high & BT RSSI = high & shielding room */
+			halbtc8812a2ant_power_save_state(btcoexist,
+						 BTC_PS_WIFI_NATIVE, 0x0, 0x0);
+			halbtc8812a2ant_ps_tdma(btcoexist, FORCE_EXEC, true, 9);
+			halbtc8812a2ant_coex_table_with_type(btcoexist,
+							     NORMAL_EXEC, 3);
+		} else if (BTC_RSSI_HIGH(wifi_rssi_state) &&
+			   (!BTC_RSSI_LOW(bt_rssi_state)) &&
+			(coex_sta->scan_ap_num > NOISY_AP_NUM_THRESH_8812A)) {
+			/* WIFI RSSI = high & BT RSSI = high & noisy environment */
+			halbtc8812a2ant_power_save_state(btcoexist,
+						 BTC_PS_WIFI_NATIVE, 0x0, 0x0);
+			halbtc8812a2ant_ps_tdma(btcoexist, FORCE_EXEC, true, 9);
+			halbtc8812a2ant_coex_table_with_type(btcoexist,
+							     NORMAL_EXEC, 3);
+		} else {	/* WIFI RSSI || BT RSSI == low */
+			halbtc8812a2ant_power_save_state(btcoexist,
+						 BTC_PS_WIFI_NATIVE, 0x0, 0x0);
+			halbtc8812a2ant_ps_tdma(btcoexist, FORCE_EXEC, true, 9);
+			halbtc8812a2ant_coex_table_with_type(btcoexist,
+							     NORMAL_EXEC, 3);
+		}
+	} else if (anttype ==
+		   3) {	/* ANTTYPE = 3,  92E 3ant with good ant. isolation */
+		/* power save state & pstdma & coex table */
+		if (BTC_RSSI_HIGH(wifi_rssi_state) &&
+		    (!BTC_RSSI_LOW(bt_rssi_state)) &&
+		    (coex_sta->scan_ap_num < NOISY_AP_NUM_THRESH_8812A)) {
+			/* WIFI RSSI = high & BT RSSI = high & shielding room */
+			coex_dm->auto_tdma_adjust = false;
+			coex_dm->auto_tdma_adjust_low_rssi = false;
+			halbtc8812a2ant_power_save_state(btcoexist,
+						 BTC_PS_WIFI_NATIVE, 0x0, 0x0);
+			halbtc8812a2ant_ps_tdma(btcoexist, FORCE_EXEC, false,
+						1);
+			halbtc8812a2ant_coex_table_with_type(btcoexist,
+							     NORMAL_EXEC, 0);
+
+		} else if (BTC_RSSI_HIGH(wifi_rssi_state) &&
+			   (!BTC_RSSI_LOW(bt_rssi_state)) &&
+			(coex_sta->scan_ap_num > NOISY_AP_NUM_THRESH_8812A)) {
+			/* WIFI RSSI = high & BT RSSI = high & noisy environment */
+			coex_dm->auto_tdma_adjust = false;
+			coex_dm->auto_tdma_adjust_low_rssi = false;
+			halbtc8812a2ant_power_save_state(btcoexist,
+						 BTC_PS_WIFI_NATIVE, 0x0, 0x0);
+			halbtc8812a2ant_ps_tdma(btcoexist, FORCE_EXEC, false,
+						1);
+			halbtc8812a2ant_coex_table_with_type(btcoexist,
+							     NORMAL_EXEC, 0);
+
+		} else {	/* WIFI RSSI || BT RSSI == low */
+			coex_dm->auto_tdma_adjust = false;
+			coex_dm->auto_tdma_adjust_low_rssi = false;
+			halbtc8812a2ant_power_save_state(btcoexist,
+						 BTC_PS_WIFI_NATIVE, 0x0, 0x0);
+			halbtc8812a2ant_ps_tdma(btcoexist, FORCE_EXEC, false,
+						1);
+			halbtc8812a2ant_coex_table_with_type(btcoexist,
+							     NORMAL_EXEC, 0);
+		}
+	} else {	/* ANTTYPE = 4 for test */
+		/* power save state & pstdma & coex table */
+		if (BTC_RSSI_HIGH(wifi_rssi_state) &&
+		    (!BTC_RSSI_LOW(bt_rssi_state)) &&
+		    (coex_sta->scan_ap_num < NOISY_AP_NUM_THRESH_8812A)) {
+			/* WIFI RSSI = high & BT RSSI = high & shielding room */
+			halbtc8812a2ant_power_save_state(btcoexist,
+						 BTC_PS_LPS_ON, 0x50, 0x4);
+			halbtc8812a2ant_tdma_duration_adjust_for_wifi_rssi_low(
+				btcoexist);
+			halbtc8812a2ant_coex_table_with_type(btcoexist,
+							     NORMAL_EXEC, 7);
+		} else if (BTC_RSSI_HIGH(wifi_rssi_state) &&
+			   (!BTC_RSSI_LOW(bt_rssi_state)) &&
+			(coex_sta->scan_ap_num > NOISY_AP_NUM_THRESH_8812A)) {
+			/* WIFI RSSI = high & BT RSSI = high & noisy environment */
+			halbtc8812a2ant_power_save_state(btcoexist,
+						 BTC_PS_LPS_ON, 0x50, 0x4);
+			halbtc8812a2ant_tdma_duration_adjust_for_wifi_rssi_low(
+				btcoexist);
+			halbtc8812a2ant_coex_table_with_type(btcoexist,
+							     NORMAL_EXEC, 7);
+		} else {	/* WIFI RSSI || BT RSSI == low */
+			halbtc8812a2ant_power_save_state(btcoexist,
+						 BTC_PS_LPS_ON, 0x50, 0x4);
+			halbtc8812a2ant_tdma_duration_adjust_for_wifi_rssi_low(
+				btcoexist);
+			halbtc8812a2ant_coex_table_with_type(btcoexist,
+							     NORMAL_EXEC, 7);
+		}
+	}
+
+
+	/* power save state */
+	halbtc8812a2ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, 0x0,
+					 0x0);
+
+	/* coex table */
+	halbtc8812a2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0);
+
+	/* pstdma */
+	halbtc8812a2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 0);
+
+	/* decrease BT power */
+	halbtc8812a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);
+
+	/* limited Rx */
+	halbtc8812a2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, 0x8);
+
+	/* fw dac swing level */
+	halbtc8812a2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6);
+
+	btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw);
+	/* sw mechanism */
+	if (BTC_WIFI_BW_HT40 == wifi_bw) {
+		if (BTC_RSSI_HIGH(wifi_rssi_state)) {
+			halbtc8812a2ant_sw_mechanism1(btcoexist, true, true,
+						      false, false);
+			halbtc8812a2ant_sw_mechanism2(btcoexist, true, false,
+						      false, 0x18);
+		} else {
+			halbtc8812a2ant_sw_mechanism1(btcoexist, true, true,
+						      false, false);
+			halbtc8812a2ant_sw_mechanism2(btcoexist, false, false,
+						      false, 0x18);
+		}
+	} else {
+		if (BTC_RSSI_HIGH(wifi_rssi_state)) {
+			halbtc8812a2ant_sw_mechanism1(btcoexist, false, true,
+						      false, false);
+			halbtc8812a2ant_sw_mechanism2(btcoexist, true, false,
+						      false, 0x18);
+		} else {
+			halbtc8812a2ant_sw_mechanism1(btcoexist, false, true,
+						      false, false);
+			halbtc8812a2ant_sw_mechanism2(btcoexist, false, false,
+						      false, 0x18);
+		}
+	}
+}
+
+/* A2DP only / PAN(EDR) only/ A2DP+PAN(HS) */
+void halbtc8812a2ant_action_a2dp(IN struct btc_coexist *btcoexist)
+{
+	u8		wifi_rssi_state = BTC_RSSI_STATE_HIGH,
+			bt_rssi_state = BTC_RSSI_STATE_HIGH;
+	u32		wifi_bw;
+	u8		anttype = 0;
+	boolean			ap_enable = false;
+
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_AP_MODE_ENABLE,
+			   &ap_enable);
+
+	btcoexist->btc_get(btcoexist, BTC_GET_U1_ANT_TYPE, &anttype);
+
+	/*	halbtc8812a2ant_get_bt_rssi_threshold(btcoexist, &bt_thresh0, &bt_thresh1);
+	 *	bt_rssi_state = halbtc8812a2ant_bt_rssi_state(3, bt_thresh0, bt_thresh1); */
+
+	wifi_rssi_state = halbtc8812a2ant_wifi_rssi_state(btcoexist, 0, 2, 34,
+			  0);
+	bt_rssi_state = halbtc8812a2ant_bt_rssi_state(3, 34, 42);
+
+	/*	anttype = 4; */
+
+	if (anttype == 0) { /* ANTTYPE = 0   92E 2ant with SPDT */
+
+		if (coex_sta->scan_ap_num > NOISY_AP_NUM_THRESH_8812A) {
+			coex_dm->auto_tdma_adjust = false;
+			coex_dm->auto_tdma_adjust_low_rssi = false;
+			halbtc8812a2ant_power_save_state(btcoexist,
+						 BTC_PS_WIFI_NATIVE, 0x0, 0x0);
+			halbtc8812a2ant_ps_tdma(btcoexist, FORCE_EXEC, false,
+						0);
+			halbtc8812a2ant_coex_table_with_type(btcoexist,
+							     NORMAL_EXEC, 0);
+		} else {
+			if (BTC_RSSI_HIGH(wifi_rssi_state) &&
+			    (!BTC_RSSI_LOW(bt_rssi_state))) {
+				/* WIFI RSSI = high & BT RSSI = high & shielding room */
+				halbtc8812a2ant_power_save_state(btcoexist,
+						 BTC_PS_LPS_ON, 0x50, 0x4);
+				halbtc8812a2ant_tdma_duration_adjust_for_wifi_rssi_low(
+					btcoexist);
+				halbtc8812a2ant_coex_table_with_type(btcoexist,
+							     NORMAL_EXEC, 7);
+			} else {	/* WIFI RSSI || BT RSSI == low */
+				halbtc8812a2ant_power_save_state(btcoexist,
+						 BTC_PS_LPS_ON, 0x50, 0x4);
+				halbtc8812a2ant_tdma_duration_adjust_for_wifi_rssi_low(
+					btcoexist);
+				halbtc8812a2ant_coex_table_with_type(btcoexist,
+							     NORMAL_EXEC, 7);
+			}
+		}
+
+		/* power save state & pstdma & coex table
+		*
+		if(BTC_RSSI_HIGH(wifi_rssi_state) &&	(!BTC_RSSI_LOW(bt_rssi_state)) && (coex_sta->scan_ap_num < NOISY_AP_NUM_THRESH_8812A))
+		{
+			halbtc8812a2ant_power_save_state(btcoexist, BTC_PS_LPS_ON, 0x50, 0x4);
+			halbtc8812a2ant_tdma_duration_adjust_for_wifi_rssi_low(btcoexist);
+			halbtc8812a2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 7);
+		}
+		else if (BTC_RSSI_HIGH(wifi_rssi_state)&&(!BTC_RSSI_LOW(bt_rssi_state)) && (coex_sta->scan_ap_num > NOISY_AP_NUM_THRESH_8812A))
+		{
+		coex_dm->auto_tdma_adjust = false;
+			coex_dm->auto_tdma_adjust_low_rssi = false;
+			halbtc8812a2ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, 0x0, 0x0);
+			halbtc8812a2ant_ps_tdma(btcoexist, FORCE_EXEC, false, 0);
+			halbtc8812a2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0);
+		}
+		else
+		{
+			halbtc8812a2ant_power_save_state(btcoexist, BTC_PS_LPS_ON, 0x50, 0x4);
+			halbtc8812a2ant_tdma_duration_adjust_for_wifi_rssi_low(btcoexist);
+			halbtc8812a2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 7);
+		}
+		*/
+	} else if (anttype ==
+		1) { /* 92E 2ant with coupler and bad ant. isolation, 92E 3ant with bad ant. isolation */
+		/* power save state & pstdma & coex table */
+		if (BTC_RSSI_HIGH(wifi_rssi_state) &&
+		    (!BTC_RSSI_LOW(bt_rssi_state)) &&
+		    (coex_sta->scan_ap_num < NOISY_AP_NUM_THRESH_8812A)) {
+			/* WIFI RSSI = high & BT RSSI = high & shielding room */
+			halbtc8812a2ant_power_save_state(btcoexist,
+						 BTC_PS_WIFI_NATIVE, 0x0, 0x0);
+			halbtc8812a2ant_tdma_duration_adjust(btcoexist, false,
+					     false, 1);	/* shielding room */
+			halbtc8812a2ant_coex_table_with_type(btcoexist,
+							     NORMAL_EXEC, 0);
+		} else if (BTC_RSSI_HIGH(wifi_rssi_state) &&
+			   (!BTC_RSSI_LOW(bt_rssi_state)) &&
+			(coex_sta->scan_ap_num > NOISY_AP_NUM_THRESH_8812A)) {
+			/* WIFI RSSI = high & BT RSSI = high & noisy environment */
+			coex_dm->auto_tdma_adjust = false;
+			coex_dm->auto_tdma_adjust_low_rssi = false;
+			halbtc8812a2ant_power_save_state(btcoexist,
+						 BTC_PS_WIFI_NATIVE, 0x0, 0x0);
+			halbtc8812a2ant_ps_tdma(btcoexist, FORCE_EXEC, false,
+						1);
+			halbtc8812a2ant_coex_table_with_type(btcoexist,
+							     NORMAL_EXEC, 0);
+		} else {	/* WIFI RSSI || BT RSSI == low */
+			halbtc8812a2ant_power_save_state(btcoexist,
+						 BTC_PS_LPS_ON, 0x50, 0x4);
+			halbtc8812a2ant_tdma_duration_adjust_for_wifi_rssi_low(
+				btcoexist);
+			halbtc8812a2ant_coex_table_with_type(btcoexist,
+							     NORMAL_EXEC, 7);
+		}
+
+	} else if (anttype ==
+		2) { /* ANTTYPE = 2, 92E 2ant with coupler and normal/good ant. isolation, 92E 3ant with normal ant. isolation */
+		/* power save state & pstdma & coex table */
+		if (BTC_RSSI_HIGH(wifi_rssi_state) &&
+		    (!BTC_RSSI_LOW(bt_rssi_state)) &&
+		    (coex_sta->scan_ap_num < NOISY_AP_NUM_THRESH_8812A)) {
+			/* WIFI RSSI = high & BT RSSI = high & shielding room */
+			halbtc8812a2ant_power_save_state(btcoexist,
+						 BTC_PS_WIFI_NATIVE, 0x0, 0x0);
+			halbtc8812a2ant_tdma_duration_adjust(btcoexist, false,
+							     false, 1);
+			halbtc8812a2ant_coex_table_with_type(btcoexist,
+							     NORMAL_EXEC, 5);
+		} else if (BTC_RSSI_HIGH(wifi_rssi_state) &&
+			   (!BTC_RSSI_LOW(bt_rssi_state)) &&
+			(coex_sta->scan_ap_num > NOISY_AP_NUM_THRESH_8812A)) {
+			/* WIFI RSSI = high & BT RSSI = high & noisy environment */
+			coex_dm->auto_tdma_adjust = false;
+			coex_dm->auto_tdma_adjust_low_rssi = false;
+			halbtc8812a2ant_power_save_state(btcoexist,
+						 BTC_PS_WIFI_NATIVE, 0x0, 0x0);
+			halbtc8812a2ant_ps_tdma(btcoexist, FORCE_EXEC, false,
+						1);
+			halbtc8812a2ant_coex_table_with_type(btcoexist,
+							     NORMAL_EXEC, 0);
+		} else {	/* WIFI RSSI || BT RSSI == low */
+			halbtc8812a2ant_power_save_state(btcoexist,
+						 BTC_PS_LPS_ON, 0x50, 0x4);
+			halbtc8812a2ant_tdma_duration_adjust_for_wifi_rssi_low(
+				btcoexist);
+			halbtc8812a2ant_coex_table_with_type(btcoexist,
+							     NORMAL_EXEC, 7);
+		}
+	} else if (anttype ==
+		   3) {	/* ANTTYPE = 3,  92E 3ant with good ant. isolation */
+		/* power save state & pstdma & coex table */
+		if (BTC_RSSI_HIGH(wifi_rssi_state) &&
+		    (!BTC_RSSI_LOW(bt_rssi_state)) &&
+		    (coex_sta->scan_ap_num < NOISY_AP_NUM_THRESH_8812A)) {
+			/* WIFI RSSI = high & BT RSSI = high & shielding room */
+			coex_dm->auto_tdma_adjust = false;
+			coex_dm->auto_tdma_adjust_low_rssi = false;
+			halbtc8812a2ant_power_save_state(btcoexist,
+						 BTC_PS_WIFI_NATIVE, 0x0, 0x0);
+			halbtc8812a2ant_ps_tdma(btcoexist, FORCE_EXEC, false,
+						1);
+			halbtc8812a2ant_coex_table_with_type(btcoexist,
+							     NORMAL_EXEC, 0);
+
+		} else if (BTC_RSSI_HIGH(wifi_rssi_state) &&
+			   (!BTC_RSSI_LOW(bt_rssi_state)) &&
+			(coex_sta->scan_ap_num > NOISY_AP_NUM_THRESH_8812A)) {
+			/* WIFI RSSI = high & BT RSSI = high & noisy environment */
+			coex_dm->auto_tdma_adjust = false;
+			coex_dm->auto_tdma_adjust_low_rssi = false;
+			halbtc8812a2ant_power_save_state(btcoexist,
+						 BTC_PS_WIFI_NATIVE, 0x0, 0x0);
+			halbtc8812a2ant_ps_tdma(btcoexist, FORCE_EXEC, false,
+						1);
+			halbtc8812a2ant_coex_table_with_type(btcoexist,
+							     NORMAL_EXEC, 0);
+
+		} else {	/* WIFI RSSI || BT RSSI == low */
+			coex_dm->auto_tdma_adjust = false;
+			coex_dm->auto_tdma_adjust_low_rssi = false;
+			halbtc8812a2ant_power_save_state(btcoexist,
+						 BTC_PS_WIFI_NATIVE, 0x0, 0x0);
+			halbtc8812a2ant_ps_tdma(btcoexist, FORCE_EXEC, false,
+						1);
+			halbtc8812a2ant_coex_table_with_type(btcoexist,
+							     NORMAL_EXEC, 0);
+		}
+	} else {	/* ANTTYPE = 4 for test */
+		/* power save state & pstdma & coex table */
+		if (BTC_RSSI_HIGH(wifi_rssi_state) &&
+		    (!BTC_RSSI_LOW(bt_rssi_state)) &&
+		    (coex_sta->scan_ap_num < NOISY_AP_NUM_THRESH_8812A)) {
+			/* WIFI RSSI = high & BT RSSI = high & shielding room */
+			halbtc8812a2ant_power_save_state(btcoexist,
+						 BTC_PS_LPS_ON, 0x50, 0x4);
+			halbtc8812a2ant_tdma_duration_adjust_for_wifi_rssi_low(
+				btcoexist);
+			halbtc8812a2ant_coex_table_with_type(btcoexist,
+							     NORMAL_EXEC, 7);
+		} else if (BTC_RSSI_HIGH(wifi_rssi_state) &&
+			   (!BTC_RSSI_LOW(bt_rssi_state)) &&
+			(coex_sta->scan_ap_num > NOISY_AP_NUM_THRESH_8812A)) {
+			/* WIFI RSSI = high & BT RSSI = high & noisy environment */
+			halbtc8812a2ant_power_save_state(btcoexist,
+						 BTC_PS_LPS_ON, 0x50, 0x4);
+			halbtc8812a2ant_tdma_duration_adjust_for_wifi_rssi_low(
+				btcoexist);
+			halbtc8812a2ant_coex_table_with_type(btcoexist,
+							     NORMAL_EXEC, 7);
+		} else {	/* WIFI RSSI || BT RSSI == low */
+			halbtc8812a2ant_power_save_state(btcoexist,
+						 BTC_PS_LPS_ON, 0x50, 0x4);
+			halbtc8812a2ant_tdma_duration_adjust_for_wifi_rssi_low(
+				btcoexist);
+			halbtc8812a2ant_coex_table_with_type(btcoexist,
+							     NORMAL_EXEC, 7);
+		}
+	}
+
+	/* decrease BT power */
+	halbtc8812a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);
+
+	/* decrease BT power
+	*
+	if(BTC_RSSI_LOW(bt_rssi_state))
+		halbtc8812a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);
+	else if(BTC_RSSI_MEDIUM(bt_rssi_state))
+		halbtc8812a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2);
+	else if (coex_sta->scan_ap_num < NOISY_AP_NUM_THRESH_8812A)
+		halbtc8812a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 4);
+	*/
+	/* limited Rx */
+	halbtc8812a2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, 0x8);
+
+	/* fw dac swing level */
+	halbtc8812a2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6);
+
+
+	/* sw mechanism */
+	btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw);
+	if (BTC_WIFI_BW_HT40 == wifi_bw) {
+		if (BTC_RSSI_HIGH(wifi_rssi_state)) {
+			halbtc8812a2ant_sw_mechanism1(btcoexist, true, false,
+						      false, false);
+			halbtc8812a2ant_sw_mechanism2(btcoexist, true, false,
+						      false, 0x18);
+		} else {
+			halbtc8812a2ant_sw_mechanism1(btcoexist, true, false,
+						      false, false);
+			halbtc8812a2ant_sw_mechanism2(btcoexist, false, false,
+						      false, 0x18);
+		}
+	} else {
+		if (BTC_RSSI_HIGH(wifi_rssi_state)) {
+			halbtc8812a2ant_sw_mechanism1(btcoexist, false, false,
+						      false, false);
+			halbtc8812a2ant_sw_mechanism2(btcoexist, true, false,
+						      false, 0x18);
+		} else {
+			halbtc8812a2ant_sw_mechanism1(btcoexist, false, false,
+						      false, false);
+			halbtc8812a2ant_sw_mechanism2(btcoexist, false, false,
+						      false, 0x18);
+		}
+	}
+}
+
+void halbtc8812a2ant_action_a2dp_pan_hs(IN struct btc_coexist *btcoexist)
+{
+	u8		wifi_rssi_state = BTC_RSSI_STATE_HIGH,
+			bt_rssi_state = BTC_RSSI_STATE_HIGH;
+	u32		wifi_bw;
+	u8		bt_thresh0 = 0, bt_thresh1 = 0;
+
+	/*	halbtc8812a2ant_get_bt_rssi_threshold(btcoexist, &bt_thresh0, &bt_thresh1); */
+	bt_rssi_state = halbtc8812a2ant_bt_rssi_state(3, bt_thresh0,
+			bt_thresh1);
+
+	wifi_rssi_state = halbtc8812a2ant_wifi_rssi_state(btcoexist, 0, 2, 34,
+			  0);
+	bt_rssi_state = halbtc8812a2ant_bt_rssi_state(3, 34, 42);
+
+	/* power save state */
+	halbtc8812a2ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, 0x0,
+					 0x0);
+
+	/* coex table	 */
+	if (BTC_RSSI_HIGH(wifi_rssi_state) && (!BTC_RSSI_LOW(bt_rssi_state)))
+		halbtc8812a2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 2);
+	else
+		halbtc8812a2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 5);
+
+	/* pstdma	 */
+	if (BTC_RSSI_HIGH(wifi_rssi_state) && (!BTC_RSSI_LOW(bt_rssi_state)))
+		halbtc8812a2ant_tdma_duration_adjust(btcoexist, false, false,
+						     2);
+	else
+		halbtc8812a2ant_tdma_duration_adjust(btcoexist, false, true, 2);
+
+	/* decrease BT power */
+	halbtc8812a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);
+	/*
+
+		if(BTC_RSSI_LOW(bt_rssi_state))
+			halbtc8812a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);
+		else if(BTC_RSSI_MEDIUM(bt_rssi_state))
+			halbtc8812a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2);
+		else
+			halbtc8812a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 4);
+	*/
+	/* limited Rx */
+	halbtc8812a2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, 0x8);
+
+	/* fw dac swing level */
+	halbtc8812a2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6);
+
+
+	/* sw mechanism */
+	btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw);
+	if (BTC_WIFI_BW_HT40 == wifi_bw) {
+		if (BTC_RSSI_HIGH(wifi_rssi_state)) {
+			halbtc8812a2ant_sw_mechanism1(btcoexist, true, false,
+						      false, false);
+			halbtc8812a2ant_sw_mechanism2(btcoexist, true, false,
+						      true, 0x6);
+		} else {
+			halbtc8812a2ant_sw_mechanism1(btcoexist, true, false,
+						      false, false);
+			halbtc8812a2ant_sw_mechanism2(btcoexist, false, false,
+						      true, 0x6);
+		}
+	} else {
+		if (BTC_RSSI_HIGH(wifi_rssi_state)) {
+			halbtc8812a2ant_sw_mechanism1(btcoexist, false, false,
+						      false, false);
+			halbtc8812a2ant_sw_mechanism2(btcoexist, true, false,
+						      true, 0x6);
+		} else {
+			halbtc8812a2ant_sw_mechanism1(btcoexist, false, false,
+						      false, false);
+			halbtc8812a2ant_sw_mechanism2(btcoexist, false, false,
+						      true, 0x6);
+		}
+	}
+}
+
+void halbtc8812a2ant_action_pan_edr(IN struct btc_coexist *btcoexist)
+{
+	u8		wifi_rssi_state = BTC_RSSI_STATE_HIGH,
+			bt_rssi_state = BTC_RSSI_STATE_HIGH;
+	u32		wifi_bw;
+	u8		bt_thresh0 = 0, bt_thresh1 = 0;
+
+
+
+	halbtc8812a2ant_get_bt_rssi_threshold(btcoexist, &bt_thresh0,
+					      &bt_thresh1);
+	bt_rssi_state = halbtc8812a2ant_bt_rssi_state(3, bt_thresh0,
+			bt_thresh1);
+
+	wifi_rssi_state = halbtc8812a2ant_wifi_rssi_state(btcoexist, 0, 2, 34,
+			  0);
+	/*	bt_rssi_state = halbtc8812a2ant_bt_rssi_state(3, 34, 42); */
+
+	/* power save state */
+	if (BTC_RSSI_HIGH(wifi_rssi_state) && (!BTC_RSSI_LOW(bt_rssi_state)))
+		halbtc8812a2ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE,
+						 0x0, 0x0);
+	else
+		halbtc8812a2ant_power_save_state(btcoexist, BTC_PS_LPS_ON, 0x50,
+						 0x4);
+
+	/* coex table */
+	if (BTC_RSSI_HIGH(wifi_rssi_state) && (!BTC_RSSI_LOW(bt_rssi_state)))
+		halbtc8812a2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 2);
+	else
+		halbtc8812a2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0);
+
+	/* pstdma */
+	if (BTC_RSSI_HIGH(wifi_rssi_state) && (!BTC_RSSI_LOW(bt_rssi_state)))
+		halbtc8812a2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 1);
+	else
+		halbtc8812a2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 85);
+
+	/* decrease BT power */
+	halbtc8812a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);
+
+	/* limited Rx */
+	halbtc8812a2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, 0x8);
+
+	/* fw dac swing level */
+	halbtc8812a2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6);
+
+
+	/* sw mechanism */
+	btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw);
+	if (BTC_WIFI_BW_HT40 == wifi_bw) {
+		if (BTC_RSSI_HIGH(wifi_rssi_state)) {
+			halbtc8812a2ant_sw_mechanism1(btcoexist, true, false,
+						      false, false);
+			halbtc8812a2ant_sw_mechanism2(btcoexist, true, false,
+						      false, 0x18);
+		} else {
+			halbtc8812a2ant_sw_mechanism1(btcoexist, true, false,
+						      false, false);
+			halbtc8812a2ant_sw_mechanism2(btcoexist, false, false,
+						      false, 0x18);
+		}
+	} else {
+		if (BTC_RSSI_HIGH(wifi_rssi_state)) {
+			halbtc8812a2ant_sw_mechanism1(btcoexist, false, false,
+						      false, false);
+			halbtc8812a2ant_sw_mechanism2(btcoexist, true, false,
+						      false, 0x18);
+		} else {
+			halbtc8812a2ant_sw_mechanism1(btcoexist, false, false,
+						      false, false);
+			halbtc8812a2ant_sw_mechanism2(btcoexist, false, false,
+						      false, 0x18);
+		}
+	}
+}
+
+/* PAN(HS) only */
+void halbtc8812a2ant_action_pan_hs(IN struct btc_coexist *btcoexist)
+{
+	u8		wifi_rssi_state = BTC_RSSI_STATE_HIGH,
+			bt_rssi_state = BTC_RSSI_STATE_HIGH;
+	u32		wifi_bw;
+
+	wifi_rssi_state = halbtc8812a2ant_wifi_rssi_state(btcoexist, 0, 2, 34,
+			  0);
+	bt_rssi_state = halbtc8812a2ant_bt_rssi_state(3, 34, 42);
+
+	/* power save state */
+	halbtc8812a2ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, 0x0,
+					 0x0);
+
+	/* coex table */
+	halbtc8812a2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 2);
+
+	/* pstdma */
+	halbtc8812a2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 1);
+
+	/* decrease BT power */
+	halbtc8812a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);
+
+	/*
+
+		if(BTC_RSSI_LOW(bt_rssi_state))
+			halbtc8812a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);
+		else if(BTC_RSSI_MEDIUM(bt_rssi_state))
+			halbtc8812a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2);
+		else
+			halbtc8812a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 4);
+	*/
+	/* limited Rx */
+	halbtc8812a2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, 0x8);
+
+	/* fw dac swing level */
+	halbtc8812a2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6);
+
+
+	btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw);
+	if (BTC_WIFI_BW_HT40 == wifi_bw) {
+		if (BTC_RSSI_HIGH(wifi_rssi_state)) {
+			halbtc8812a2ant_sw_mechanism1(btcoexist, true, false,
+						      false, false);
+			halbtc8812a2ant_sw_mechanism2(btcoexist, true, false,
+						      false, 0x18);
+		} else {
+			halbtc8812a2ant_sw_mechanism1(btcoexist, true, false,
+						      false, false);
+			halbtc8812a2ant_sw_mechanism2(btcoexist, false, false,
+						      false, 0x18);
+		}
+	} else {
+		if (BTC_RSSI_HIGH(wifi_rssi_state)) {
+			halbtc8812a2ant_sw_mechanism1(btcoexist, false, false,
+						      false, false);
+			halbtc8812a2ant_sw_mechanism2(btcoexist, true, false,
+						      false, 0x18);
+		} else {
+			halbtc8812a2ant_sw_mechanism1(btcoexist, false, false,
+						      false, false);
+			halbtc8812a2ant_sw_mechanism2(btcoexist, false, false,
+						      false, 0x18);
+		}
+	}
+}
+
+/* PAN(EDR)+A2DP */
+void halbtc8812a2ant_action_pan_edr_a2dp(IN struct btc_coexist *btcoexist)
+{
+	u8		wifi_rssi_state = BTC_RSSI_STATE_HIGH,
+			bt_rssi_state = BTC_RSSI_STATE_HIGH;
+	u32		wifi_bw;
+	u8		bt_thresh0 = 0, bt_thresh1 = 0;
+
+	halbtc8812a2ant_get_bt_rssi_threshold(btcoexist, &bt_thresh0,
+					      &bt_thresh1);
+	bt_rssi_state = halbtc8812a2ant_bt_rssi_state(3, bt_thresh0,
+			bt_thresh1);
+
+	wifi_rssi_state = halbtc8812a2ant_wifi_rssi_state(btcoexist, 0, 2, 34,
+			  0);
+	/*	bt_rssi_state = halbtc8812a2ant_bt_rssi_state(3, 34, 42); */
+
+	/* power save state */
+	if (BTC_RSSI_HIGH(wifi_rssi_state) &&	(!BTC_RSSI_LOW(bt_rssi_state)))
+		halbtc8812a2ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE,
+						 0x0, 0x0);
+	else
+		halbtc8812a2ant_power_save_state(btcoexist, BTC_PS_LPS_ON, 0x50,
+						 0x4);
+
+	/* coex table */
+	if (BTC_RSSI_HIGH(wifi_rssi_state) &&	(!BTC_RSSI_LOW(bt_rssi_state)))
+		halbtc8812a2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 2);
+	else
+		halbtc8812a2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0);
+
+	/* pstdma */
+	if (BTC_RSSI_HIGH(wifi_rssi_state) &&	(!BTC_RSSI_LOW(bt_rssi_state)))
+		halbtc8812a2ant_tdma_duration_adjust(btcoexist, false, false,
+						     3);
+	else {
+		coex_dm->auto_tdma_adjust = false;
+		coex_dm->auto_tdma_adjust_low_rssi = false;
+		halbtc8812a2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 86);
+	}
+
+	/* decrease BT power */
+	halbtc8812a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);
+
+	/* limited Rx */
+	halbtc8812a2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, 0x8);
+
+	/* fw dac swing level */
+	halbtc8812a2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6);
+
+	btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw);
+	/* sw mechanism */
+	if (BTC_WIFI_BW_HT40 == wifi_bw) {
+		if (BTC_RSSI_HIGH(wifi_rssi_state)) {
+			halbtc8812a2ant_sw_mechanism1(btcoexist, true, false,
+						      false, false);
+			halbtc8812a2ant_sw_mechanism2(btcoexist, true, false,
+						      false, 0x18);
+		} else {
+			halbtc8812a2ant_sw_mechanism1(btcoexist, true, false,
+						      false, false);
+			halbtc8812a2ant_sw_mechanism2(btcoexist, false, false,
+						      false, 0x18);
+		}
+	} else {
+		if (BTC_RSSI_HIGH(wifi_rssi_state)) {
+			halbtc8812a2ant_sw_mechanism1(btcoexist, false, false,
+						      false, false);
+			halbtc8812a2ant_sw_mechanism2(btcoexist, true, false,
+						      false, 0x18);
+		} else {
+			halbtc8812a2ant_sw_mechanism1(btcoexist, false, false,
+						      false, false);
+			halbtc8812a2ant_sw_mechanism2(btcoexist, false, false,
+						      false, 0x18);
+		}
+	}
+}
+
+
+void halbtc8812a2ant_action_pan_edr_hid(IN struct btc_coexist *btcoexist)
+{
+	u8		wifi_rssi_state = BTC_RSSI_STATE_HIGH,
+			bt_rssi_state = BTC_RSSI_STATE_HIGH;
+	u32		wifi_bw;
+	u8		bt_thresh0 = 0, bt_thresh1 = 0;
+
+
+	halbtc8812a2ant_get_bt_rssi_threshold(btcoexist, &bt_thresh0,
+					      &bt_thresh1);
+	bt_rssi_state = halbtc8812a2ant_bt_rssi_state(3, bt_thresh0,
+			bt_thresh1);
+
+	wifi_rssi_state = halbtc8812a2ant_wifi_rssi_state(btcoexist, 0, 2, 34,
+			  0);
+	/*	bt_rssi_state = halbtc8812a2ant_bt_rssi_state(3, 34, 42); */
+
+	/* power save state */
+	if (BTC_RSSI_HIGH(wifi_rssi_state) && (!BTC_RSSI_LOW(bt_rssi_state)))
+		halbtc8812a2ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE,
+						 0x0, 0x0);
+	else if (BTC_RSSI_LOW(wifi_rssi_state) &&
+		 (!BTC_RSSI_LOW(bt_rssi_state)))
+		halbtc8812a2ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE,
+						 0x0, 0x0);
+	else
+		halbtc8812a2ant_power_save_state(btcoexist, BTC_PS_LPS_ON, 0x50,
+						 0x4);
+
+	/* coex table */
+	if (BTC_RSSI_HIGH(wifi_rssi_state) && (!BTC_RSSI_LOW(bt_rssi_state)))
+		halbtc8812a2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 3);
+	else if (BTC_RSSI_LOW(wifi_rssi_state) &&
+		 (!BTC_RSSI_LOW(bt_rssi_state)))
+		halbtc8812a2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 5);
+	else
+		halbtc8812a2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0);
+
+	/* pstdma */
+	if (BTC_RSSI_HIGH(wifi_rssi_state) && (!BTC_RSSI_LOW(bt_rssi_state)))
+		halbtc8812a2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 10);
+	else if (BTC_RSSI_LOW(wifi_rssi_state) &&
+		 (!BTC_RSSI_LOW(bt_rssi_state)))
+		halbtc8812a2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 14);
+	else
+		halbtc8812a2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 85);
+
+	/* decrease BT power */
+	halbtc8812a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);
+
+	/*
+
+		if(BTC_RSSI_LOW(bt_rssi_state))
+			halbtc8812a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);
+		else if(BTC_RSSI_MEDIUM(bt_rssi_state))
+			halbtc8812a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2);
+		else
+			halbtc8812a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 4);
+	*/
+	/* limited Rx */
+	if (BTC_RSSI_HIGH(wifi_rssi_state) && (!BTC_RSSI_LOW(bt_rssi_state)))
+		halbtc8812a2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false,
+					   0x8);
+	else if (BTC_RSSI_LOW(wifi_rssi_state) &&
+		 (!BTC_RSSI_LOW(bt_rssi_state)))
+		halbtc8812a2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false,
+					   0x8);
+	else
+		halbtc8812a2ant_limited_rx(btcoexist, NORMAL_EXEC, false, true,
+					   0x8);
+
+	/* fw dac swing level */
+	halbtc8812a2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6);
+
+
+	btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw);
+	/* sw mechanism */
+	if (BTC_WIFI_BW_HT40 == wifi_bw) {
+		if (BTC_RSSI_HIGH(wifi_rssi_state)) {
+			halbtc8812a2ant_sw_mechanism1(btcoexist, true, true,
+						      false, false);
+			halbtc8812a2ant_sw_mechanism2(btcoexist, true, false,
+						      false, 0x18);
+		} else {
+			halbtc8812a2ant_sw_mechanism1(btcoexist, true, true,
+						      false, false);
+			halbtc8812a2ant_sw_mechanism2(btcoexist, false, false,
+						      false, 0x18);
+		}
+	} else {
+		if (BTC_RSSI_HIGH(wifi_rssi_state)) {
+			halbtc8812a2ant_sw_mechanism1(btcoexist, false, true,
+						      false, false);
+			halbtc8812a2ant_sw_mechanism2(btcoexist, true, false,
+						      false, 0x18);
+		} else {
+			halbtc8812a2ant_sw_mechanism1(btcoexist, false, true,
+						      false, false);
+			halbtc8812a2ant_sw_mechanism2(btcoexist, false, false,
+						      false, 0x18);
+		}
+	}
+}
+
+/* HID+A2DP+PAN(EDR) */
+void halbtc8812a2ant_action_hid_a2dp_pan_edr(IN struct btc_coexist *btcoexist)
+{
+	u8		wifi_rssi_state = BTC_RSSI_STATE_HIGH,
+			bt_rssi_state = BTC_RSSI_STATE_HIGH;
+	u32		wifi_bw;
+	u8		bt_thresh0 = 0, bt_thresh1 = 0;
+
+	halbtc8812a2ant_get_bt_rssi_threshold(btcoexist, &bt_thresh0,
+					      &bt_thresh1);
+	bt_rssi_state = halbtc8812a2ant_bt_rssi_state(3, bt_thresh0,
+			bt_thresh1);
+
+	wifi_rssi_state = halbtc8812a2ant_wifi_rssi_state(btcoexist, 0, 2, 34,
+			  0);
+	/*	bt_rssi_state = halbtc8812a2ant_bt_rssi_state(3, 34, 42); */
+
+	/* power save state */
+	if (BTC_RSSI_HIGH(wifi_rssi_state) && (!BTC_RSSI_LOW(bt_rssi_state)))
+		halbtc8812a2ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE,
+						 0x0, 0x0);
+	else if (BTC_RSSI_LOW(wifi_rssi_state) &&
+		 (!BTC_RSSI_LOW(bt_rssi_state)))
+		halbtc8812a2ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE,
+						 0x0, 0x0);
+	else
+		halbtc8812a2ant_power_save_state(btcoexist, BTC_PS_LPS_ON, 0x50,
+						 0x4);
+
+	/* coex table */
+	if (BTC_RSSI_HIGH(wifi_rssi_state) && (!BTC_RSSI_LOW(bt_rssi_state)))
+		halbtc8812a2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 3);
+	else if (BTC_RSSI_LOW(wifi_rssi_state) &&
+		 (!BTC_RSSI_LOW(bt_rssi_state)))
+		halbtc8812a2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 5);
+	else
+		halbtc8812a2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0);
+
+	/* pstdma */
+	if (BTC_RSSI_HIGH(wifi_rssi_state) && (!BTC_RSSI_LOW(bt_rssi_state)))
+		halbtc8812a2ant_tdma_duration_adjust(btcoexist, true, false, 3);
+	else if (BTC_RSSI_LOW(wifi_rssi_state) &&
+		 (!BTC_RSSI_LOW(bt_rssi_state)))
+		halbtc8812a2ant_tdma_duration_adjust(btcoexist, true, true, 3);
+	else {
+		coex_dm->auto_tdma_adjust = false;
+		halbtc8812a2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 86);
+	}
+
+	/* decrease BT power */
+	halbtc8812a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);
+	/*
+
+		if(BTC_RSSI_LOW(bt_rssi_state))
+			halbtc8812a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);
+		else if(BTC_RSSI_MEDIUM(bt_rssi_state))
+			halbtc8812a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2);
+		else
+			halbtc8812a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 4);
+	*/
+	/* limited Rx */
+	if (BTC_RSSI_HIGH(wifi_rssi_state) && (!BTC_RSSI_LOW(bt_rssi_state)))
+		halbtc8812a2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false,
+					   0x8);
+	else if (BTC_RSSI_LOW(wifi_rssi_state) &&
+		 (!BTC_RSSI_LOW(bt_rssi_state)))
+		halbtc8812a2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false,
+					   0x8);
+	else
+		halbtc8812a2ant_limited_rx(btcoexist, NORMAL_EXEC, false, true,
+					   0x8);
+
+
+	/* fw dac swing level */
+	halbtc8812a2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6);
+
+	btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw);
+	/* sw mechanism */
+	if (BTC_WIFI_BW_HT40 == wifi_bw) {
+		if (BTC_RSSI_HIGH(wifi_rssi_state)) {
+			halbtc8812a2ant_sw_mechanism1(btcoexist, true, true,
+						      false, false);
+			halbtc8812a2ant_sw_mechanism2(btcoexist, true, false,
+						      false, 0x18);
+		} else {
+			halbtc8812a2ant_sw_mechanism1(btcoexist, true, true,
+						      false, false);
+			halbtc8812a2ant_sw_mechanism2(btcoexist, false, false,
+						      false, 0x18);
+		}
+	} else {
+		if (BTC_RSSI_HIGH(wifi_rssi_state)) {
+			halbtc8812a2ant_sw_mechanism1(btcoexist, false, true,
+						      false, false);
+			halbtc8812a2ant_sw_mechanism2(btcoexist, true, false,
+						      false, 0x18);
+		} else {
+			halbtc8812a2ant_sw_mechanism1(btcoexist, false, true,
+						      false, false);
+			halbtc8812a2ant_sw_mechanism2(btcoexist, false, false,
+						      false, 0x18);
+		}
+	}
+}
+
+void halbtc8812a2ant_action_hid_a2dp_pan_hs(IN struct btc_coexist *btcoexist)
+{
+	u8		wifi_rssi_state = BTC_RSSI_STATE_HIGH,
+			bt_rssi_state = BTC_RSSI_STATE_HIGH;
+	u32		wifi_bw;
+	u8		bt_thresh0 = 0, bt_thresh1 = 0;
+
+	halbtc8812a2ant_get_bt_rssi_threshold(btcoexist, &bt_thresh0,
+					      &bt_thresh1);
+	bt_rssi_state = halbtc8812a2ant_bt_rssi_state(3, bt_thresh0,
+			bt_thresh1);
+
+
+	wifi_rssi_state = halbtc8812a2ant_wifi_rssi_state(btcoexist, 0, 2, 34,
+			  0);
+	/*	bt_rssi_state = halbtc8812a2ant_bt_rssi_state(3, 34, 42); */
+
+	/* power save state */
+	halbtc8812a2ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, 0x0,
+					 0x0);
+
+	/* coex table */
+	if (BTC_RSSI_HIGH(wifi_rssi_state) && (!BTC_RSSI_LOW(bt_rssi_state)))
+		halbtc8812a2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 3);
+	else if (BTC_RSSI_LOW(wifi_rssi_state) &&
+		 (!BTC_RSSI_LOW(bt_rssi_state)))
+		halbtc8812a2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 5);
+	else
+		halbtc8812a2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0);
+
+	/* pstdma */
+	if (BTC_RSSI_HIGH(wifi_rssi_state) && (!BTC_RSSI_LOW(bt_rssi_state)))
+		halbtc8812a2ant_tdma_duration_adjust(btcoexist, true, false, 2);
+	else if (BTC_RSSI_LOW(wifi_rssi_state) &&
+		 (!BTC_RSSI_LOW(bt_rssi_state)))
+		halbtc8812a2ant_tdma_duration_adjust(btcoexist, true, true, 2);
+	else
+		halbtc8812a2ant_tdma_duration_adjust(btcoexist, true, true, 2);
+
+	/* decrease BT power */
+	halbtc8812a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);
+
+	/*
+
+		if(BTC_RSSI_LOW(bt_rssi_state))
+			halbtc8812a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);
+		else if(BTC_RSSI_MEDIUM(bt_rssi_state))
+			halbtc8812a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2);
+		else
+			halbtc8812a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 4);
+	*/
+	/* limited Rx */
+	if (BTC_RSSI_HIGH(wifi_rssi_state) && (!BTC_RSSI_LOW(bt_rssi_state)))
+		halbtc8812a2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false,
+					   0x8);
+	else if (BTC_RSSI_LOW(wifi_rssi_state) &&
+		 (!BTC_RSSI_LOW(bt_rssi_state)))
+		halbtc8812a2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false,
+					   0x8);
+	else
+		halbtc8812a2ant_limited_rx(btcoexist, NORMAL_EXEC, false, true,
+					   0x8);
+
+	/* fw dac swing level */
+	halbtc8812a2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6);
+
+
+	btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw);
+	/* sw mechanism */
+	if (BTC_WIFI_BW_HT40 == wifi_bw) {
+		if (BTC_RSSI_HIGH(wifi_rssi_state)) {
+			halbtc8812a2ant_sw_mechanism1(btcoexist, true, true,
+						      false, false);
+			halbtc8812a2ant_sw_mechanism2(btcoexist, true, false,
+						      false, 0x18);
+		} else {
+			halbtc8812a2ant_sw_mechanism1(btcoexist, true, true,
+						      false, false);
+			halbtc8812a2ant_sw_mechanism2(btcoexist, false, false,
+						      false, 0x18);
+		}
+	} else {
+		if (BTC_RSSI_HIGH(wifi_rssi_state)) {
+			halbtc8812a2ant_sw_mechanism1(btcoexist, false, true,
+						      false, false);
+			halbtc8812a2ant_sw_mechanism2(btcoexist, true, false,
+						      false, 0x18);
+		} else {
+			halbtc8812a2ant_sw_mechanism1(btcoexist, false, true,
+						      false, false);
+			halbtc8812a2ant_sw_mechanism2(btcoexist, false, false,
+						      false, 0x18);
+		}
+	}
+}
+
+void halbtc8812a2ant_action_hid_a2dp(IN struct btc_coexist *btcoexist)
+{
+	u8		wifi_rssi_state = BTC_RSSI_STATE_HIGH,
+			bt_rssi_state = BTC_RSSI_STATE_HIGH;
+	u32		wifi_bw;
+	u8		anttype = 0;
+
+	btcoexist->btc_get(btcoexist, BTC_GET_U1_ANT_TYPE, &anttype);
+
+
+	/*	halbtc8812a2ant_get_bt_rssi_threshold(btcoexist, &bt_thresh0, &bt_thresh1);
+	 *	bt_rssi_state = halbtc8812a2ant_bt_rssi_state(3, bt_thresh0, bt_thresh1); */
+
+	wifi_rssi_state = halbtc8812a2ant_wifi_rssi_state(btcoexist, 0, 2, 34,
+			  0);
+	bt_rssi_state = halbtc8812a2ant_bt_rssi_state(3, 34, 42);
+
+	if (anttype == 0) { /* ANTTYPE = 0	92E 2ant with SPDT */
+		/* power save state & pstdma & coex table */
+		if (BTC_RSSI_HIGH(wifi_rssi_state) &&
+		    (!BTC_RSSI_LOW(bt_rssi_state)) &&
+		    (coex_sta->scan_ap_num < NOISY_AP_NUM_THRESH_8812A)) {
+			halbtc8812a2ant_power_save_state(btcoexist,
+						 BTC_PS_LPS_ON, 0x50, 0x4);
+			halbtc8812a2ant_ps_tdma(btcoexist, FORCE_EXEC, true,
+						83);
+			halbtc8812a2ant_coex_table_with_type(btcoexist,
+							     NORMAL_EXEC, 8);
+
+		} else if (BTC_RSSI_HIGH(wifi_rssi_state) &&
+			   (!BTC_RSSI_LOW(bt_rssi_state)) &&
+			(coex_sta->scan_ap_num > NOISY_AP_NUM_THRESH_8812A)) {
+			coex_dm->auto_tdma_adjust = false;
+			coex_dm->auto_tdma_adjust_low_rssi = false;
+			halbtc8812a2ant_power_save_state(btcoexist,
+						 BTC_PS_WIFI_NATIVE, 0x0, 0x0);
+			halbtc8812a2ant_ps_tdma(btcoexist, FORCE_EXEC, false,
+						0);
+			halbtc8812a2ant_coex_table_with_type(btcoexist,
+							     NORMAL_EXEC, 0);
+		} else {
+			halbtc8812a2ant_power_save_state(btcoexist,
+						 BTC_PS_LPS_ON, 0x50, 0x4);
+			halbtc8812a2ant_ps_tdma(btcoexist, FORCE_EXEC, true,
+						83);
+			halbtc8812a2ant_coex_table_with_type(btcoexist,
+							     NORMAL_EXEC, 8);
+		}
+	} else if (anttype ==
+		1) { /* 92E 2ant with coupler and bad ant. isolation, 92E 3ant with bad ant. isolation */
+		/* power save state & pstdma & coex table */
+		if (BTC_RSSI_HIGH(wifi_rssi_state) &&
+		    (!BTC_RSSI_LOW(bt_rssi_state)) &&
+		    (coex_sta->scan_ap_num < NOISY_AP_NUM_THRESH_8812A)) {
+			halbtc8812a2ant_power_save_state(btcoexist,
+						 BTC_PS_WIFI_NATIVE, 0x0, 0x0);
+			halbtc8812a2ant_tdma_duration_adjust(btcoexist, true,
+							     true, 2);
+			halbtc8812a2ant_coex_table_with_type(btcoexist,
+							     NORMAL_EXEC, 8);
+		} else if (BTC_RSSI_HIGH(wifi_rssi_state) &&
+			   (!BTC_RSSI_LOW(bt_rssi_state)) &&
+			(coex_sta->scan_ap_num > NOISY_AP_NUM_THRESH_8812A)) {
+			coex_dm->auto_tdma_adjust = false;
+			coex_dm->auto_tdma_adjust_low_rssi = false;
+			halbtc8812a2ant_power_save_state(btcoexist,
+						 BTC_PS_WIFI_NATIVE, 0x0, 0x0);
+			halbtc8812a2ant_ps_tdma(btcoexist, FORCE_EXEC, false,
+						0);
+			halbtc8812a2ant_coex_table_with_type(btcoexist,
+							     NORMAL_EXEC, 0);
+		} else {
+			halbtc8812a2ant_power_save_state(btcoexist,
+						 BTC_PS_LPS_ON, 0x50, 0x4);
+			halbtc8812a2ant_ps_tdma(btcoexist, FORCE_EXEC, true,
+						83);
+			halbtc8812a2ant_coex_table_with_type(btcoexist,
+							     NORMAL_EXEC, 8);
+		}
+	} else if (anttype ==
+		2) { /* ANTTYPE = 2, 92E 2ant with coupler and normal/good ant. isolation, 92E 3ant with normal ant. isolation */
+		/* power save state & pstdma & coex table */
+		if (BTC_RSSI_HIGH(wifi_rssi_state) &&
+		    (!BTC_RSSI_LOW(bt_rssi_state)) &&
+		    (coex_sta->scan_ap_num < NOISY_AP_NUM_THRESH_8812A)) {
+			/* WIFI RSSI = high & BT RSSI = high & shielding room */
+			halbtc8812a2ant_power_save_state(btcoexist,
+						 BTC_PS_WIFI_NATIVE, 0x0, 0x0);
+			halbtc8812a2ant_tdma_duration_adjust(btcoexist, true,
+							     true, 2);
+			halbtc8812a2ant_coex_table_with_type(btcoexist,
+							     NORMAL_EXEC, 8);
+		} else if (BTC_RSSI_HIGH(wifi_rssi_state) &&
+			   (!BTC_RSSI_LOW(bt_rssi_state)) &&
+			(coex_sta->scan_ap_num > NOISY_AP_NUM_THRESH_8812A)) {
+			/* WIFI RSSI = high & BT RSSI = high & noisy environment */
+			coex_dm->auto_tdma_adjust = false;
+			coex_dm->auto_tdma_adjust_low_rssi = false;
+			halbtc8812a2ant_power_save_state(btcoexist,
+						 BTC_PS_WIFI_NATIVE, 0x0, 0x0);
+			halbtc8812a2ant_ps_tdma(btcoexist, FORCE_EXEC, false,
+						0);
+			halbtc8812a2ant_coex_table_with_type(btcoexist,
+							     NORMAL_EXEC, 8);
+		} else {	/* WIFI RSSI || BT RSSI == low */
+			halbtc8812a2ant_power_save_state(btcoexist,
+						 BTC_PS_LPS_ON, 0x50, 0x4);
+			halbtc8812a2ant_ps_tdma(btcoexist, FORCE_EXEC, true,
+						83);
+			halbtc8812a2ant_coex_table_with_type(btcoexist,
+							     NORMAL_EXEC, 8);
+		}
+	} else if (anttype ==
+		   3) {	/* ANTTYPE = 3,  92E 3ant with good ant. isolation */
+		/* power save state & pstdma & coex table */
+		if (BTC_RSSI_HIGH(wifi_rssi_state) &&
+		    (!BTC_RSSI_LOW(bt_rssi_state)) &&
+		    (coex_sta->scan_ap_num < NOISY_AP_NUM_THRESH_8812A)) {
+			/* WIFI RSSI = high & BT RSSI = high & shielding room */
+			coex_dm->auto_tdma_adjust = false;
+			coex_dm->auto_tdma_adjust_low_rssi = false;
+			halbtc8812a2ant_power_save_state(btcoexist,
+						 BTC_PS_WIFI_NATIVE, 0x0, 0x0);
+			halbtc8812a2ant_ps_tdma(btcoexist, FORCE_EXEC, false,
+						1);
+			halbtc8812a2ant_coex_table_with_type(btcoexist,
+							     NORMAL_EXEC, 0);
+
+		} else if (BTC_RSSI_HIGH(wifi_rssi_state) &&
+			   (!BTC_RSSI_LOW(bt_rssi_state)) &&
+			(coex_sta->scan_ap_num > NOISY_AP_NUM_THRESH_8812A)) {
+			/* WIFI RSSI = high & BT RSSI = high & noisy environment */
+			coex_dm->auto_tdma_adjust = false;
+			coex_dm->auto_tdma_adjust_low_rssi = false;
+			halbtc8812a2ant_power_save_state(btcoexist,
+						 BTC_PS_WIFI_NATIVE, 0x0, 0x0);
+			halbtc8812a2ant_ps_tdma(btcoexist, FORCE_EXEC, false,
+						1);
+			halbtc8812a2ant_coex_table_with_type(btcoexist,
+							     NORMAL_EXEC, 0);
+
+		} else {	/* WIFI RSSI || BT RSSI == low */
+			coex_dm->auto_tdma_adjust = false;
+			coex_dm->auto_tdma_adjust_low_rssi = false;
+			halbtc8812a2ant_power_save_state(btcoexist,
+						 BTC_PS_WIFI_NATIVE, 0x0, 0x0);
+			halbtc8812a2ant_ps_tdma(btcoexist, FORCE_EXEC, false,
+						1);
+			halbtc8812a2ant_coex_table_with_type(btcoexist,
+							     NORMAL_EXEC, 0);
+		}
+	} else {	/* ANTTYPE = 4 for test */
+		/* power save state & pstdma & coex table */
+		if (BTC_RSSI_HIGH(wifi_rssi_state) &&
+		    (!BTC_RSSI_LOW(bt_rssi_state)) &&
+		    (coex_sta->scan_ap_num < NOISY_AP_NUM_THRESH_8812A)) {
+			/* WIFI RSSI = high & BT RSSI = high & shielding room */
+			halbtc8812a2ant_power_save_state(btcoexist,
+						 BTC_PS_LPS_ON, 0x50, 0x4);
+			halbtc8812a2ant_tdma_duration_adjust_for_wifi_rssi_low(
+				btcoexist);
+			halbtc8812a2ant_coex_table_with_type(btcoexist,
+							     NORMAL_EXEC, 7);
+		} else if (BTC_RSSI_HIGH(wifi_rssi_state) &&
+			   (!BTC_RSSI_LOW(bt_rssi_state)) &&
+			(coex_sta->scan_ap_num > NOISY_AP_NUM_THRESH_8812A)) {
+			/* WIFI RSSI = high & BT RSSI = high & noisy environment */
+			halbtc8812a2ant_power_save_state(btcoexist,
+						 BTC_PS_LPS_ON, 0x50, 0x4);
+			halbtc8812a2ant_tdma_duration_adjust_for_wifi_rssi_low(
+				btcoexist);
+			halbtc8812a2ant_coex_table_with_type(btcoexist,
+							     NORMAL_EXEC, 7);
+		} else {	/* WIFI RSSI || BT RSSI == low */
+			halbtc8812a2ant_power_save_state(btcoexist,
+						 BTC_PS_LPS_ON, 0x50, 0x4);
+			halbtc8812a2ant_tdma_duration_adjust_for_wifi_rssi_low(
+				btcoexist);
+			halbtc8812a2ant_coex_table_with_type(btcoexist,
+							     NORMAL_EXEC, 7);
+		}
+	}
+
+	/* decrease BT power */
+	halbtc8812a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);
+
+	/*
+
+		if(BTC_RSSI_LOW(bt_rssi_state))
+			halbtc8812a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);
+		else if(BTC_RSSI_MEDIUM(bt_rssi_state))
+			halbtc8812a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2);
+		else if (coex_sta->scan_ap_num < NOISY_AP_NUM_THRESH_8812A)
+			halbtc8812a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 4);
+	*/
+	/* limited Rx */
+	halbtc8812a2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, 0x8);
+
+	/* fw dac swing level */
+	halbtc8812a2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6);
+
+
+	btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw);
+	/* sw mechanism */
+	if (BTC_WIFI_BW_HT40 == wifi_bw) {
+		if (BTC_RSSI_HIGH(wifi_rssi_state)) {
+			halbtc8812a2ant_sw_mechanism1(btcoexist, true, true,
+						      false, false);
+			halbtc8812a2ant_sw_mechanism2(btcoexist, true, false,
+						      false, 0x18);
+		} else {
+			halbtc8812a2ant_sw_mechanism1(btcoexist, true, true,
+						      false, false);
+			halbtc8812a2ant_sw_mechanism2(btcoexist, false, false,
+						      false, 0x18);
+		}
+	} else {
+		if (BTC_RSSI_HIGH(wifi_rssi_state)) {
+			halbtc8812a2ant_sw_mechanism1(btcoexist, false, true,
+						      false, false);
+			halbtc8812a2ant_sw_mechanism2(btcoexist, true, false,
+						      false, 0x18);
+		} else {
+			halbtc8812a2ant_sw_mechanism1(btcoexist, false, true,
+						      false, false);
+			halbtc8812a2ant_sw_mechanism2(btcoexist, false, false,
+						      false, 0x18);
+		}
+	}
+}
+
+void halbtc8812a2ant_coex_under_5g(IN struct btc_coexist *btcoexist)
+{
+	halbtc8812a2ant_coex_all_off(btcoexist);
+
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+		"[BTCoex], Under 5G, force set BT to ignore Wlan active!!\n");
+	BTC_TRACE(trace_buf);
+	halbtc8812a2ant_ignore_wlan_act(btcoexist, NORMAL_EXEC, true);
+}
+/* **************************************************** */
+void halbtc8812a2ant_run_coexist_mechanism(IN struct btc_coexist *btcoexist)
+{
+	boolean				wifi_under_5g = false;
+	u8				algorithm = 0;
+
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+		    "[BTCoex], RunCoexistMechanism()===>\n");
+	BTC_TRACE(trace_buf);
+
+	if (btcoexist->manual_control) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			"[BTCoex], RunCoexistMechanism(), return for Manual CTRL <===\n");
+		BTC_TRACE(trace_buf);
+		return;
+	}
+
+	if (coex_sta->under_ips) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], wifi is under IPS !!!\n");
+		BTC_TRACE(trace_buf);
+		return;
+	}
+
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_5G, &wifi_under_5g);
+	if (wifi_under_5g) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			"[BTCoex], RunCoexistMechanism(), run 5G coex setting!!<===\n");
+		BTC_TRACE(trace_buf);
+		halbtc8812a2ant_coex_under_5g(btcoexist);
+		return;
+	}
+
+
+	algorithm = halbtc8812a2ant_action_algorithm(btcoexist);
+	if (coex_sta->c2h_bt_inquiry_page &&
+	    (BT_8812A_2ANT_COEX_ALGO_PANHS != algorithm)) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], BT is under inquiry/page scan !!\n");
+		BTC_TRACE(trace_buf);
+		halbtc8812a2ant_action_bt_inquiry(btcoexist);
+		return;
+	}
+
+	coex_dm->cur_algorithm = algorithm;
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], Algorithm = %d\n",
+		    coex_dm->cur_algorithm);
+	BTC_TRACE(trace_buf);
+
+	if (halbtc8812a2ant_is_common_action(btcoexist)) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], Action 2-Ant common.\n");
+		BTC_TRACE(trace_buf);
+		coex_dm->auto_tdma_adjust = false;
+		coex_dm->auto_tdma_adjust_low_rssi = false;
+	} else {
+		if (coex_dm->cur_algorithm != coex_dm->pre_algorithm) {
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				"[BTCoex], pre_algorithm=%d, cur_algorithm=%d\n",
+				coex_dm->pre_algorithm, coex_dm->cur_algorithm);
+			BTC_TRACE(trace_buf);
+			coex_dm->auto_tdma_adjust = false;
+			coex_dm->auto_tdma_adjust_low_rssi = false;
+		}
+		switch (coex_dm->cur_algorithm) {
+		case BT_8812A_2ANT_COEX_ALGO_SCO:
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				"[BTCoex], Action 2-Ant, algorithm = SCO.\n");
+			BTC_TRACE(trace_buf);
+			halbtc8812a2ant_action_sco(btcoexist);
+			break;
+		case BT_8812A_2ANT_COEX_ALGO_SCO_HID:
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				"[BTCoex], Action 2-Ant, algorithm = SCO+HID.\n");
+			BTC_TRACE(trace_buf);
+			halbtc8812a2ant_action_sco_hid(btcoexist);
+			break;
+		case BT_8812A_2ANT_COEX_ALGO_HID:
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				"[BTCoex], Action 2-Ant, algorithm = HID.\n");
+			BTC_TRACE(trace_buf);
+			halbtc8812a2ant_action_hid(btcoexist);
+			break;
+		case BT_8812A_2ANT_COEX_ALGO_A2DP:
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				"[BTCoex], Action 2-Ant, algorithm = A2DP.\n");
+			BTC_TRACE(trace_buf);
+			halbtc8812a2ant_action_a2dp(btcoexist);
+			break;
+		case BT_8812A_2ANT_COEX_ALGO_A2DP_PANHS:
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				"[BTCoex], Action 2-Ant, algorithm = A2DP+PAN(HS).\n");
+			BTC_TRACE(trace_buf);
+			halbtc8812a2ant_action_a2dp_pan_hs(btcoexist);
+			break;
+		case BT_8812A_2ANT_COEX_ALGO_PANEDR:
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				"[BTCoex], Action 2-Ant, algorithm = PAN(EDR).\n");
+			BTC_TRACE(trace_buf);
+			halbtc8812a2ant_action_pan_edr(btcoexist);
+			break;
+		case BT_8812A_2ANT_COEX_ALGO_PANHS:
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				"[BTCoex], Action 2-Ant, algorithm = HS mode.\n");
+			BTC_TRACE(trace_buf);
+			halbtc8812a2ant_action_pan_hs(btcoexist);
+			break;
+		case BT_8812A_2ANT_COEX_ALGO_PANEDR_A2DP:
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				"[BTCoex], Action 2-Ant, algorithm = PAN+A2DP.\n");
+			BTC_TRACE(trace_buf);
+			halbtc8812a2ant_action_pan_edr_a2dp(btcoexist);
+			break;
+		case BT_8812A_2ANT_COEX_ALGO_PANEDR_HID:
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				"[BTCoex], Action 2-Ant, algorithm = PAN(EDR)+HID.\n");
+			BTC_TRACE(trace_buf);
+			halbtc8812a2ant_action_pan_edr_hid(btcoexist);
+			break;
+		case BT_8812A_2ANT_COEX_ALGO_HID_A2DP_PANEDR:
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				"[BTCoex], Action 2-Ant, algorithm = HID+A2DP+PAN.\n");
+			BTC_TRACE(trace_buf);
+			halbtc8812a2ant_action_hid_a2dp_pan_edr(
+				btcoexist);
+			break;
+		case BT_8812A_2ANT_COEX_ALGO_HID_A2DP_PANHS:
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				"[BTCoex], Action 2-Ant, algorithm = HID+A2DP+PAN(HS).\n");
+			BTC_TRACE(trace_buf);
+			halbtc8812a2ant_action_hid_a2dp_pan_hs(
+				btcoexist);
+			break;
+		case BT_8812A_2ANT_COEX_ALGO_HID_A2DP:
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				"[BTCoex], Action 2-Ant, algorithm = HID+A2DP.\n");
+			BTC_TRACE(trace_buf);
+			halbtc8812a2ant_action_hid_a2dp(btcoexist);
+			break;
+		default:
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				"[BTCoex], Action 2-Ant, algorithm = coexist All Off!!\n");
+			BTC_TRACE(trace_buf);
+			halbtc8812a2ant_coex_all_off(btcoexist);
+			break;
+		}
+		coex_dm->pre_algorithm = coex_dm->cur_algorithm;
+	}
+
+}
+
+void halbtc8812a2ant_init_hw_config(IN struct btc_coexist *btcoexist,
+				    IN boolean back_up)
+{
+	u8	u8tmp = 0;
+
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+		    "[BTCoex], 2Ant Init HW Config!!\n");
+	BTC_TRACE(trace_buf);
+
+	if (back_up) {
+		/* backup rf 0x1e value */
+		coex_dm->bt_rf_0x1e_backup =
+			btcoexist->btc_get_rf_reg(btcoexist, BTC_RF_A, 0x1e,
+						  0xfffff);
+
+		coex_dm->backup_arfr_cnt1 = btcoexist->btc_read_4byte(btcoexist,
+					    0x430);
+		coex_dm->backup_arfr_cnt2 = btcoexist->btc_read_4byte(btcoexist,
+					    0x434);
+		coex_dm->backup_retry_limit = btcoexist->btc_read_2byte(
+						      btcoexist, 0x42a);
+		coex_dm->backup_ampdu_max_time = btcoexist->btc_read_1byte(
+				btcoexist, 0x456);
+	}
+
+	/* ant sw control to BT */
+	halbtc8812a2ant_set_ant_path(btcoexist, BTC_ANT_WIFI_AT_CPL_AUX, true,
+				     false);
+
+	/* 0x790[5:0]=0x5 */
+	u8tmp = btcoexist->btc_read_1byte(btcoexist, 0x790);
+	u8tmp &= 0xc0;
+	u8tmp |= 0x5;
+	btcoexist->btc_write_1byte(btcoexist, 0x790, u8tmp);
+
+	/* PTA parameter */
+	btcoexist->btc_write_1byte(btcoexist, 0x6cc, 0x0);
+	btcoexist->btc_write_4byte(btcoexist, 0x6c8, 0xffff);
+	btcoexist->btc_write_4byte(btcoexist, 0x6c4, 0x55555555);
+	btcoexist->btc_write_4byte(btcoexist, 0x6c0, 0x55555555);
+
+	/* coex parameters */
+	btcoexist->btc_write_1byte(btcoexist, 0x778, 0x1);
+
+	/* enable counter statistics */
+	btcoexist->btc_write_1byte(btcoexist, 0x76e, 0x4);
+
+	/* disable PTA to avoid BT insn't on */
+	btcoexist->btc_write_1byte(btcoexist, 0x40, 0x00);
+
+	/* bt clock related */
+	u8tmp = btcoexist->btc_read_1byte(btcoexist, 0x4);
+	u8tmp |= BIT(7);
+	btcoexist->btc_write_1byte(btcoexist, 0x4, u8tmp);
+
+	/* bt clock related */
+	u8tmp = btcoexist->btc_read_1byte(btcoexist, 0x7);
+	u8tmp |= BIT(1);
+	btcoexist->btc_write_1byte(btcoexist, 0x7, u8tmp);
+
+	/* Give bt_coex_supported_version the default value */
+	coex_sta->bt_coex_supported_version = 0;
+
+}
+
+/* ************************************************************
+ * work around function start with wa_halbtc8812a2ant_
+ * ************************************************************
+ * ************************************************************
+ * extern function start with ex_halbtc8812a2ant_
+ * ************************************************************ */
+void ex_halbtc8812a2ant_power_on_setting(IN struct btc_coexist *btcoexist)
+{
+}
+
+void ex_halbtc8812a2ant_init_hw_config(IN struct btc_coexist *btcoexist,
+				       IN boolean wifi_only)
+{
+	halbtc8812a2ant_init_hw_config(btcoexist, true);
+}
+
+void ex_halbtc8812a2ant_init_coex_dm(IN struct btc_coexist *btcoexist)
+{
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+		    "[BTCoex], Coex Mechanism Init!!\n");
+	BTC_TRACE(trace_buf);
+
+	halbtc8812a2ant_init_coex_dm(btcoexist);
+}
+
+
+void ex_halbtc8812a2ant_pta_off_on_notify(IN struct btc_coexist *btcoexist,
+		IN u8 bt_status)
+{
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], BToff/on notify\n");
+	BTC_TRACE(trace_buf);
+
+	if (BTC_BT_OFF == bt_status) {
+		/* PTA off */
+		btcoexist->bt_info.bt_disabled = true;
+		halbtc8812a2ant_enable_pta(btcoexist, FORCE_EXEC, false);
+
+	} else {
+		/* PTA on */
+		btcoexist->bt_info.bt_disabled = false;
+		halbtc8812a2ant_enable_pta(btcoexist, FORCE_EXEC, true);
+	}
+
+}
+
+
+void ex_halbtc8812a2ant_display_coex_info(IN struct btc_coexist *btcoexist)
+{
+	struct  btc_board_info		*board_info = &btcoexist->board_info;
+	struct  btc_stack_info		*stack_info = &btcoexist->stack_info;
+	struct  btc_bt_link_info	*bt_link_info = &btcoexist->bt_link_info;
+	u8				*cli_buf = btcoexist->cli_buf;
+	u8				u8tmp[4], i, bt_info_ext, ps_tdma_case = 0;
+	u16				u16tmp[4];
+	u32				u32tmp[4];
+	u32				fa_ofdm, fa_cck, cca_ofdm, cca_cck;
+	u32				fw_ver = 0, bt_patch_ver = 0, bt_coex_ver = 0;
+	u32				phyver = 0;
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+		   "\r\n ============[BT Coexist info]============");
+	CL_PRINTF(cli_buf);
+
+	if (btcoexist->manual_control) {
+		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+			"\r\n ============[Under Manual Control]============");
+		CL_PRINTF(cli_buf);
+		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+			   "\r\n ==========================================");
+		CL_PRINTF(cli_buf);
+	}
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d ",
+		   "Ant PG number/ Ant mechanism:",
+		   board_info->pg_ant_num, board_info->btdm_ant_num);
+	CL_PRINTF(cli_buf);
+
+#if 0
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d", "Antenna type:",
+		   board_info->ant_type);
+	CL_PRINTF(cli_buf);
+#endif
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s / %d",
+		   "BT stack/ hci ext ver",
+		   ((stack_info->profile_notified) ? "Yes" : "No"),
+		   stack_info->hci_version);
+	CL_PRINTF(cli_buf);
+
+	bt_patch_ver = btcoexist->bt_info.bt_get_fw_ver;
+	btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_FW_VER, &fw_ver);
+	phyver = btcoexist->btc_get_bt_phydm_version(btcoexist);
+	bt_coex_ver = coex_sta->bt_coex_supported_version & 0xff;
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+		   "\r\n %-35s = %d_%02x/ 0x%02x/ 0x%02x (%s)",
+		   "CoexVer WL/  BT_Desired/ BT_Report",
+		   glcoex_ver_date_8812a_2ant, glcoex_ver_8812a_2ant,
+		   glcoex_ver_btdesired_8812a_2ant, bt_coex_ver,
+		   (bt_coex_ver == 0xff ? "Unknown" : (bt_coex_ver >=
+				   glcoex_ver_btdesired_8812a_2ant ? "Match" :
+				   "Mis-Match")));
+	CL_PRINTF(cli_buf);
+
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+		   "\r\n %-35s = 0x%x/ 0x%x/ v%d",
+		   "W_FW/ B_FW/ Phy",
+		   fw_ver, bt_patch_ver, phyver);
+	CL_PRINTF(cli_buf);
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %02x %02x %02x ",
+		   "Wifi channel informed to BT",
+		   coex_dm->wifi_chnl_info[0], coex_dm->wifi_chnl_info[1],
+		   coex_dm->wifi_chnl_info[2]);
+	CL_PRINTF(cli_buf);
+
+	/* wifi status */
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s",
+		   "============[Wifi Status]============");
+	CL_PRINTF(cli_buf);
+	btcoexist->btc_disp_dbg_msg(btcoexist, BTC_DBG_DISP_WIFI_STATUS);
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s",
+		   "============[BT Status]============");
+	CL_PRINTF(cli_buf);
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = [%s/ %d/ %d] ",
+		   "BT [status/ rssi/ retryCnt]",
+		   ((btcoexist->bt_info.bt_disabled) ? ("disabled") :	((
+		   coex_sta->c2h_bt_inquiry_page) ? ("inquiry/page scan")
+			   : ((BT_8812A_2ANT_BT_STATUS_NON_CONNECTED_IDLE ==
+			       coex_dm->bt_status) ? "non-connected idle" :
+		((BT_8812A_2ANT_BT_STATUS_CONNECTED_IDLE == coex_dm->bt_status)
+				       ? "connected-idle" : "busy")))),
+		   coex_sta->bt_rssi, coex_sta->bt_retry_cnt);
+	CL_PRINTF(cli_buf);
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d / %d / %d / %d",
+		   "SCO/HID/PAN/A2DP",
+		   bt_link_info->sco_exist, bt_link_info->hid_exist,
+		   bt_link_info->pan_exist, bt_link_info->a2dp_exist);
+	CL_PRINTF(cli_buf);
+	btcoexist->btc_disp_dbg_msg(btcoexist, BTC_DBG_DISP_BT_LINK_INFO);
+
+	bt_info_ext = coex_sta->bt_info_ext;
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s",
+		   "BT Info A2DP rate",
+		   (bt_info_ext & BIT(0)) ? "Basic rate" : "EDR rate");
+	CL_PRINTF(cli_buf);
+
+	for (i = 0; i < BT_INFO_SRC_8812A_2ANT_MAX; i++) {
+		if (coex_sta->bt_info_c2h_cnt[i]) {
+			CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+				"\r\n %-35s = %02x %02x %02x %02x %02x %02x %02x(%d)",
+				   glbt_info_src_8812a_2ant[i],
+				   coex_sta->bt_info_c2h[i][0],
+				   coex_sta->bt_info_c2h[i][1],
+				   coex_sta->bt_info_c2h[i][2],
+				   coex_sta->bt_info_c2h[i][3],
+				   coex_sta->bt_info_c2h[i][4],
+				   coex_sta->bt_info_c2h[i][5],
+				   coex_sta->bt_info_c2h[i][6],
+				   coex_sta->bt_info_c2h_cnt[i]);
+			CL_PRINTF(cli_buf);
+		}
+	}
+
+	/* Sw mechanism	 */
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s",
+		   "============[Sw mechanism]============");
+	CL_PRINTF(cli_buf);
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d ",
+		   "SM1[ShRf/ LpRA/ LimDig]",
+		   coex_dm->cur_rf_rx_lpf_shrink, coex_dm->cur_low_penalty_ra,
+		   coex_dm->limited_dig);
+	CL_PRINTF(cli_buf);
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d(0x%x) ",
+		   "SM2[AgcT/ AdcB/ SwDacSwing(lvl)]",
+		   coex_dm->cur_agc_table_en, coex_dm->cur_adc_back_off,
+		   coex_dm->cur_dac_swing_on, coex_dm->cur_dac_swing_lvl);
+	CL_PRINTF(cli_buf);
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x ", "Rate Mask",
+		   btcoexist->bt_info.ra_mask);
+	CL_PRINTF(cli_buf);
+
+	/* Fw mechanism		 */
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s",
+		   "============[Fw mechanism]============");
+	CL_PRINTF(cli_buf);
+
+	ps_tdma_case = coex_dm->cur_ps_tdma;
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+		   "\r\n %-35s = %02x %02x %02x %02x %02x case-%d (auto:%d/%d)",
+		   "PS TDMA",
+		   coex_dm->ps_tdma_para[0], coex_dm->ps_tdma_para[1],
+		   coex_dm->ps_tdma_para[2], coex_dm->ps_tdma_para[3],
+		   coex_dm->ps_tdma_para[4], ps_tdma_case,
+		   coex_dm->auto_tdma_adjust,
+		   coex_dm->auto_tdma_adjust_low_rssi);
+	CL_PRINTF(cli_buf);
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d ",
+		   "DecBtPwr/ IgnWlanAct",
+		   coex_dm->cur_bt_dec_pwr_lvl, coex_dm->cur_ignore_wlan_act);
+	CL_PRINTF(cli_buf);
+
+	/* Hw setting		 */
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s",
+		   "============[Hw setting]============");
+	CL_PRINTF(cli_buf);
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x",
+		   "RF-A, 0x1e initVal",
+		   coex_dm->bt_rf_0x1e_backup);
+	CL_PRINTF(cli_buf);
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/0x%x/0x%x/0x%x",
+		   "backup ARFR1/ARFR2/RL/AMaxTime",
+		   coex_dm->backup_arfr_cnt1, coex_dm->backup_arfr_cnt2,
+		   coex_dm->backup_retry_limit,
+		   coex_dm->backup_ampdu_max_time);
+	CL_PRINTF(cli_buf);
+
+	u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x430);
+	u32tmp[1] = btcoexist->btc_read_4byte(btcoexist, 0x434);
+	u16tmp[0] = btcoexist->btc_read_2byte(btcoexist, 0x42a);
+	u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x456);
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/0x%x/0x%x/0x%x",
+		   "0x430/0x434/0x42a/0x456",
+		   u32tmp[0], u32tmp[1], u16tmp[0], u8tmp[0]);
+	CL_PRINTF(cli_buf);
+
+	u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x778);
+	u8tmp[1] = btcoexist->btc_read_1byte(btcoexist, 0x6cc);
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x ",
+		   "0x778 (W_Act)/ 0x6cc (CoTab Sel)",
+		   u8tmp[0], u8tmp[1]);
+	CL_PRINTF(cli_buf);
+
+	u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x8db);
+	u8tmp[1] = btcoexist->btc_read_1byte(btcoexist, 0xc5b);
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x",
+		   "0x8db(ADC)/0xc5b[29:25](DAC)",
+		   ((u8tmp[0] & 0x60) >> 5), ((u8tmp[1] & 0x3e) >> 1));
+	CL_PRINTF(cli_buf);
+
+	u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0xcb3);
+	u8tmp[1] = btcoexist->btc_read_1byte(btcoexist, 0xcb7);
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x",
+		   "0xcb3/ 0xcb7",
+		   u8tmp[0], u8tmp[1]);
+	CL_PRINTF(cli_buf);
+
+	u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x40);
+	u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x4c);
+	u32tmp[1] = btcoexist->btc_read_4byte(btcoexist, 0x974);
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x/ 0x%x",
+		   "0x40/ 0x4c[24:23]/ 0x974",
+		   u8tmp[0], ((u32tmp[0] & 0x01800000) >> 23), u32tmp[1]);
+	CL_PRINTF(cli_buf);
+
+	u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x550);
+	u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x522);
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x",
+		   "0x550(bcn ctrl)/0x522",
+		   u32tmp[0], u8tmp[0]);
+	CL_PRINTF(cli_buf);
+
+	u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0xc50);
+	u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0xa0a);
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x",
+		   "0xc50(DIG)/0xa0a(CCK-TH)",
+		   u32tmp[0], u8tmp[0]);
+	CL_PRINTF(cli_buf);
+
+	fa_ofdm = btcoexist->btc_phydm_query_PHY_counter(btcoexist,
+			PHYDM_INFO_FA_OFDM);
+	fa_cck = btcoexist->btc_phydm_query_PHY_counter(btcoexist,
+			PHYDM_INFO_FA_CCK);
+	cca_ofdm = btcoexist->btc_phydm_query_PHY_counter(btcoexist,
+			PHYDM_INFO_CCA_OFDM);
+	cca_cck = btcoexist->btc_phydm_query_PHY_counter(btcoexist,
+			PHYDM_INFO_CCA_CCK);
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+		   "\r\n %-35s = 0x%x/ 0x%x/ 0x%x/ 0x%x",
+		   "CCK-CCA/CCK-FA/OFDM-CCA/OFDM-FA",
+		   cca_cck, fa_cck, cca_ofdm, fa_ofdm);
+	CL_PRINTF(cli_buf);
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d/ %d",
+		   "CRC_OK CCK/11g/11n/11n-agg",
+		   coex_sta->crc_ok_cck, coex_sta->crc_ok_11g,
+		   coex_sta->crc_ok_11n, coex_sta->crc_ok_11n_vht);
+	CL_PRINTF(cli_buf);
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d/ %d",
+		   "CRC_Err CCK/11g/11n/11n-agg",
+		   coex_sta->crc_err_cck, coex_sta->crc_err_11g,
+		   coex_sta->crc_err_11n, coex_sta->crc_err_11n_vht);
+	CL_PRINTF(cli_buf);
+
+	u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x6c0);
+	u32tmp[1] = btcoexist->btc_read_4byte(btcoexist, 0x6c4);
+	u32tmp[2] = btcoexist->btc_read_4byte(btcoexist, 0x6c8);
+	u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x6cc);
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+		   "\r\n %-35s = 0x%x/ 0x%x/ 0x%x/ 0x%x",
+		   "0x6c0/0x6c4/0x6c8/0x6cc(coexTable)",
+		   u32tmp[0], u32tmp[1], u32tmp[2], u8tmp[0]);
+	CL_PRINTF(cli_buf);
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d",
+		   "0x770(high-pri rx/tx)",
+		   coex_sta->high_priority_rx, coex_sta->high_priority_tx);
+	CL_PRINTF(cli_buf);
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d",
+		   "0x774(low-pri rx/tx)",
+		   coex_sta->low_priority_rx, coex_sta->low_priority_tx);
+	CL_PRINTF(cli_buf);
+#if (BT_AUTO_REPORT_ONLY_8812A_2ANT == 1)
+	halbtc8812a2ant_monitor_bt_ctr(btcoexist);
+#endif
+	btcoexist->btc_disp_dbg_msg(btcoexist, BTC_DBG_DISP_COEX_STATISTICS);
+}
+
+
+void ex_halbtc8812a2ant_ips_notify(IN struct btc_coexist *btcoexist, IN u8 type)
+{
+	boolean	wifi_under_5g = false;
+
+	if (BTC_IPS_ENTER == type) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], IPS ENTER notify\n");
+		BTC_TRACE(trace_buf);
+
+		coex_sta->under_ips = true;
+		halbtc8812a2ant_coex_all_off(btcoexist);
+		halbtc8812a2ant_set_ant_path(btcoexist, BTC_ANT_WIFI_AT_CPL_AUX,
+					     false, true);
+
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			"[BTCoex], IPS notify, force set BT to ignore Wlan active!!\n");
+		BTC_TRACE(trace_buf);
+
+		halbtc8812a2ant_ignore_wlan_act(btcoexist, FORCE_EXEC, true);
+		ex_halbtc8812a2ant_media_status_notify(btcoexist,
+						       BTC_MEDIA_DISCONNECT);
+	} else if (BTC_IPS_LEAVE == type) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], IPS LEAVE notify\n");
+		BTC_TRACE(trace_buf);
+
+		coex_sta->under_ips = false;
+
+		btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_5G,
+				   &wifi_under_5g);
+		if (!wifi_under_5g) {
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				"[BTCoex], IPS notify, force set BT NOT to ignore Wlan active!!\n");
+			BTC_TRACE(trace_buf);
+
+			halbtc8812a2ant_ignore_wlan_act(btcoexist, FORCE_EXEC,
+							false);
+		}
+	}
+}
+
+void ex_halbtc8812a2ant_lps_notify(IN struct btc_coexist *btcoexist, IN u8 type)
+{
+	if (BTC_LPS_ENABLE == type) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], LPS ENABLE notify\n");
+		BTC_TRACE(trace_buf);
+
+		coex_sta->under_lps = true;
+	} else if (BTC_LPS_DISABLE == type) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], LPS DISABLE notify\n");
+		BTC_TRACE(trace_buf);
+
+		coex_sta->under_lps = false;
+	}
+}
+
+void ex_halbtc8812a2ant_scan_notify(IN struct btc_coexist *btcoexist,
+				    IN u8 type)
+{
+	if (BTC_SCAN_START == type) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], SCAN START notify\n");
+		BTC_TRACE(trace_buf);
+	} else if (BTC_SCAN_FINISH == type) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], SCAN FINISH notify\n");
+		BTC_TRACE(trace_buf);
+
+		btcoexist->btc_get(btcoexist, BTC_GET_U1_AP_NUM,
+				   &coex_sta->scan_ap_num);
+	}
+}
+
+void ex_halbtc8812a2ant_connect_notify(IN struct btc_coexist *btcoexist,
+				       IN u8 type)
+{
+	if (BTC_ASSOCIATE_START == type) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], CONNECT START notify\n");
+		BTC_TRACE(trace_buf);
+	} else if (BTC_ASSOCIATE_FINISH == type) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], CONNECT FINISH notify\n");
+		BTC_TRACE(trace_buf);
+	}
+}
+
+void ex_halbtc8812a2ant_media_status_notify(IN struct btc_coexist *btcoexist,
+		IN u8 type)
+{
+	u8			data_len = 5;
+	u8			buf[6] = {0};
+	u8			h2c_parameter[3] = {0};
+	u32			wifi_bw;
+	u8			wifi_central_chnl;
+
+	if (btcoexist->manual_control ||
+	    btcoexist->stop_coex_dm ||
+	    btcoexist->bt_info.bt_disabled)
+		return;
+
+	if (BTC_MEDIA_CONNECT == type) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], MEDIA connect notify\n");
+		BTC_TRACE(trace_buf);
+	} else {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], MEDIA disconnect notify\n");
+		BTC_TRACE(trace_buf);
+	}
+
+	/* only 2.4G we need to inform bt the chnl mask */
+	btcoexist->btc_get(btcoexist, BTC_GET_U1_WIFI_CENTRAL_CHNL,
+			   &wifi_central_chnl);
+	if ((BTC_MEDIA_CONNECT == type) &&
+	    (wifi_central_chnl <= 14)) {
+		h2c_parameter[0] = 0x1;
+		h2c_parameter[1] = wifi_central_chnl;
+		btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw);
+		if (BTC_WIFI_BW_HT40 == wifi_bw)
+			h2c_parameter[2] = 0x30;
+		else
+			h2c_parameter[2] = 0x20;
+	}
+
+	coex_dm->wifi_chnl_info[0] = h2c_parameter[0];
+	coex_dm->wifi_chnl_info[1] = h2c_parameter[1];
+	coex_dm->wifi_chnl_info[2] = h2c_parameter[2];
+
+	buf[0] = data_len;
+	buf[1] = 0x5;				/* OP_Code */
+	buf[2] = 0x3;				/* OP_Code_Length */
+	buf[3] = h2c_parameter[0];	/* OP_Code_Content */
+	buf[4] = h2c_parameter[1];
+	buf[5] = h2c_parameter[2];
+
+	btcoexist->btc_set(btcoexist, BTC_SET_ACT_CTRL_BT_COEX,
+			   (void *)&buf[0]);
+}
+
+void ex_halbtc8812a2ant_specific_packet_notify(IN struct btc_coexist *btcoexist,
+		IN u8 type)
+{
+	if (type == BTC_PACKET_DHCP) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], DHCP Packet notify\n");
+		BTC_TRACE(trace_buf);
+	}
+}
+
+void ex_halbtc8812a2ant_bt_info_notify(IN struct btc_coexist *btcoexist,
+				       IN u8 *tmp_buf, IN u8 length)
+{
+	u8			bt_info = 0;
+	u8			i, rsp_source = 0;
+	boolean			bt_busy = false, limited_dig = false;
+	boolean			wifi_connected = false, wifi_under_5g = false;
+
+	coex_sta->c2h_bt_info_req_sent = false;
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_5G, &wifi_under_5g);
+
+	rsp_source = tmp_buf[0] & 0xf;
+	if (rsp_source >= BT_INFO_SRC_8812A_2ANT_MAX)
+		rsp_source = BT_INFO_SRC_8812A_2ANT_WIFI_FW;
+	coex_sta->bt_info_c2h_cnt[rsp_source]++;
+
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+		    "[BTCoex], Bt info[%d], length=%d, hex data=[", rsp_source,
+		    length);
+	BTC_TRACE(trace_buf);
+
+	for (i = 0; i < length; i++) {
+		coex_sta->bt_info_c2h[rsp_source][i] = tmp_buf[i];
+		if (i == 1)
+			bt_info = tmp_buf[i];
+		if (i == length - 1) {
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "0x%02x]\n",
+				    tmp_buf[i]);
+			BTC_TRACE(trace_buf);
+		} else {
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "0x%02x, ",
+				    tmp_buf[i]);
+			BTC_TRACE(trace_buf);
+		}
+	}
+
+	if (BT_INFO_SRC_8812A_2ANT_WIFI_FW != rsp_source) {
+		coex_sta->bt_retry_cnt =	/* [3:0] */
+			coex_sta->bt_info_c2h[rsp_source][2] & 0xf;
+
+		coex_sta->bt_rssi =
+			coex_sta->bt_info_c2h[rsp_source][3] * 2 + 10;
+
+		coex_sta->bt_info_ext =
+			coex_sta->bt_info_c2h[rsp_source][4];
+
+		/* Here we need to resend some wifi info to BT */
+		/* because bt is reset and loss of the info. */
+		if ((coex_sta->bt_info_ext & BIT(1))) {
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				"[BTCoex], BT ext info bit1 check, send wifi BW&Chnl to BT!!\n");
+			BTC_TRACE(trace_buf);
+
+			btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED,
+					   &wifi_connected);
+			if (wifi_connected)
+				ex_halbtc8812a2ant_media_status_notify(
+					btcoexist, BTC_MEDIA_CONNECT);
+			else
+				ex_halbtc8812a2ant_media_status_notify(
+					btcoexist, BTC_MEDIA_DISCONNECT);
+		}
+
+		if ((coex_sta->bt_info_ext & BIT(3)) && !wifi_under_5g) {
+			/* BT already ignored WlanAct */
+			if (!btcoexist->manual_control &&
+			    !btcoexist->stop_coex_dm) {
+				if (!coex_sta->under_ips) {
+					BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+						"[BTCoex], BT ext info bit3 check, set BT NOT to ignore Wlan active!!\n");
+					BTC_TRACE(trace_buf);
+					halbtc8812a2ant_ignore_wlan_act(
+						btcoexist, FORCE_EXEC, false);
+				}
+			}
+		} else {
+			/* BT already NOT ignore Wlan active, do nothing here. */
+
+			if (coex_sta->under_ips) {
+				/* work around for 8812a combo hw bug => when IPS, wlanAct is always high. */
+				BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+					"[BTCoex], wifi is under IPS, set BT to ignore Wlan active!!\n");
+				BTC_TRACE(trace_buf);
+				halbtc8812a2ant_ignore_wlan_act(btcoexist,
+							FORCE_EXEC, true);
+			}
+		}
+	}
+
+	/* check BIT2 first ==> check if bt is under inquiry or page scan */
+	if (bt_info & BT_INFO_8812A_2ANT_B_INQ_PAGE)
+		coex_sta->c2h_bt_inquiry_page = true;
+	else
+		coex_sta->c2h_bt_inquiry_page = false;
+
+	/* set link exist status */
+	if (!(bt_info & BT_INFO_8812A_2ANT_B_CONNECTION)) {
+		coex_sta->bt_link_exist = false;
+		coex_sta->pan_exist = false;
+		coex_sta->a2dp_exist = false;
+		coex_sta->hid_exist = false;
+		coex_sta->sco_exist = false;
+		coex_sta->acl_busy = false;
+	} else {	/* connection exists */
+		coex_sta->bt_link_exist = true;
+		if (bt_info & BT_INFO_8812A_2ANT_B_FTP)
+			coex_sta->pan_exist = true;
+		else
+			coex_sta->pan_exist = false;
+		if (bt_info & BT_INFO_8812A_2ANT_B_A2DP)
+			coex_sta->a2dp_exist = true;
+		else
+			coex_sta->a2dp_exist = false;
+		if (bt_info & BT_INFO_8812A_2ANT_B_HID)
+			coex_sta->hid_exist = true;
+		else
+			coex_sta->hid_exist = false;
+		if (bt_info & BT_INFO_8812A_2ANT_B_SCO_ESCO)
+			coex_sta->sco_exist = true;
+		else
+			coex_sta->sco_exist = false;
+		if (bt_info & BT_INFO_8812A_2ANT_B_ACL_BUSY)
+			coex_sta->acl_busy = true;
+		else
+			coex_sta->acl_busy = false;
+
+	}
+
+	halbtc8812a2ant_update_bt_link_info(btcoexist);
+
+	if (!(bt_info & BT_INFO_8812A_2ANT_B_CONNECTION)) {
+		coex_dm->bt_status = BT_8812A_2ANT_BT_STATUS_NON_CONNECTED_IDLE;
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			"[BTCoex], BtInfoNotify(), BT Non-Connected idle!!!\n");
+		BTC_TRACE(trace_buf);
+	} else if (bt_info ==
+		BT_INFO_8812A_2ANT_B_CONNECTION) {	/* connection exists but no busy */
+		coex_dm->bt_status = BT_8812A_2ANT_BT_STATUS_CONNECTED_IDLE;
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], BtInfoNotify(), BT Connected-idle!!!\n");
+		BTC_TRACE(trace_buf);
+	} else if ((bt_info & BT_INFO_8812A_2ANT_B_SCO_ESCO) ||
+		   (bt_info & BT_INFO_8812A_2ANT_B_SCO_BUSY)) {
+		coex_dm->bt_status = BT_8812A_2ANT_BT_STATUS_SCO_BUSY;
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], BtInfoNotify(), BT SCO busy!!!\n");
+		BTC_TRACE(trace_buf);
+	} else if (bt_info & BT_INFO_8812A_2ANT_B_ACL_BUSY) {
+		coex_dm->bt_status = BT_8812A_2ANT_BT_STATUS_ACL_BUSY;
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], BtInfoNotify(), BT ACL busy!!!\n");
+		BTC_TRACE(trace_buf);
+	} else {
+		coex_dm->bt_status = BT_8812A_2ANT_BT_STATUS_MAX;
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			"[BTCoex], BtInfoNotify(), BT Non-Defined state!!!\n");
+		BTC_TRACE(trace_buf);
+	}
+
+	if ((BT_8812A_2ANT_BT_STATUS_ACL_BUSY == coex_dm->bt_status) ||
+	    (BT_8812A_2ANT_BT_STATUS_SCO_BUSY == coex_dm->bt_status) ||
+	    (BT_8812A_2ANT_BT_STATUS_ACL_SCO_BUSY == coex_dm->bt_status)) {
+		bt_busy = true;
+		if (!wifi_under_5g)
+			limited_dig = true;
+	} else {
+		bt_busy = false;
+		limited_dig = false;
+	}
+
+	btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_TRAFFIC_BUSY, &bt_busy);
+
+	coex_dm->limited_dig = limited_dig;
+	btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_LIMITED_DIG, &limited_dig);
+
+	halbtc8812a2ant_run_coexist_mechanism(btcoexist);
+}
+
+void ex_halbtc8812a2ant_halt_notify(IN struct btc_coexist *btcoexist)
+{
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], Halt notify\n");
+	BTC_TRACE(trace_buf);
+
+	halbtc8812a2ant_set_ant_path(btcoexist, BTC_ANT_WIFI_AT_CPL_AUX, false,
+				     true);
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+		"[BTCoex], Halt notify, force set BT to ignore Wlan active!!\n");
+	BTC_TRACE(trace_buf);
+
+	halbtc8812a2ant_ignore_wlan_act(btcoexist, FORCE_EXEC, true);
+	ex_halbtc8812a2ant_media_status_notify(btcoexist, BTC_MEDIA_DISCONNECT);
+
+	/* 0x522=0xff, pause tx */
+	btcoexist->btc_write_1byte(btcoexist, 0x522, 0xff);
+	/* 0x40[7:6]=2'b01, modify BT mode. */
+	btcoexist->btc_write_1byte_bitmask(btcoexist, 0x40, 0xc0, 0x2);
+	/* PTA off. */
+#ifndef CONFIG_PCI_HCI
+	btcoexist->btc_write_1byte_bitmask(btcoexist, 0x40, 0x20, 0x0);
+#endif
+}
+
+void ex_halbtc8812a2ant_periodical(IN struct btc_coexist *btcoexist)
+{
+	static u8		dis_ver_info_cnt = 0;
+	u32				fw_ver = 0, bt_patch_ver = 0;
+	struct  btc_board_info		*board_info = &btcoexist->board_info;
+	struct  btc_stack_info		*stack_info = &btcoexist->stack_info;
+
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+		"[BTCoex], ==========================Periodical===========================\n");
+	BTC_TRACE(trace_buf);
+
+	if (dis_ver_info_cnt <= 5) {
+		dis_ver_info_cnt += 1;
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			"[BTCoex], ****************************************************************\n");
+		BTC_TRACE(trace_buf);
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			"[BTCoex], Ant PG Num/ Ant Mech/ Ant Pos = %d/ %d/ %d\n",
+			    board_info->pg_ant_num, board_info->btdm_ant_num,
+			    board_info->btdm_ant_pos);
+		BTC_TRACE(trace_buf);
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], BT stack/ hci ext ver = %s / %d\n",
+			    ((stack_info->profile_notified) ? "Yes" : "No"),
+			    stack_info->hci_version);
+		BTC_TRACE(trace_buf);
+
+		btcoexist->btc_get(btcoexist, BTC_GET_U4_BT_PATCH_VER,
+				   &bt_patch_ver);
+		btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_FW_VER, &fw_ver);
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			"[BTCoex], CoexVer/ FwVer/ PatchVer = %d_%x/ 0x%x/ 0x%x(%d)\n",
+			    glcoex_ver_date_8812a_2ant, glcoex_ver_8812a_2ant,
+			    fw_ver, bt_patch_ver, bt_patch_ver);
+		BTC_TRACE(trace_buf);
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			"[BTCoex], ****************************************************************\n");
+		BTC_TRACE(trace_buf);
+	}
+
+	if ((coex_sta->bt_coex_supported_version == 0) ||
+	    (coex_sta->bt_coex_supported_version == 0xffff))
+		coex_sta->bt_coex_supported_version =
+			btcoexist->btc_get_bt_coex_supported_version(btcoexist);
+
+#if (BT_AUTO_REPORT_ONLY_8812A_2ANT == 0)
+	halbtc8812a2ant_query_bt_info(btcoexist);
+	halbtc8812a2ant_monitor_bt_ctr(btcoexist);
+	halbtc8812a2ant_monitor_wifi_ctr(btcoexist);
+	halbtc8812a2ant_monitor_bt_enable_disable(btcoexist);
+#else
+	halbtc8812a2ant_monitor_wifi_ctr(btcoexist);
+
+	if (halbtc8812a2ant_is_wifi_status_changed(btcoexist) ||
+	    coex_dm->auto_tdma_adjust ||
+	    coex_dm->auto_tdma_adjust_low_rssi)
+		halbtc8812a2ant_run_coexist_mechanism(btcoexist);
+#endif
+}
+
+void ex_halbtc8812a2ant_dbg_control(IN struct btc_coexist *btcoexist,
+				    IN u8 op_code, IN u8 op_len, IN u8 *pdata)
+{
+	switch (op_code) {
+	case BTC_DBG_SET_COEX_DEC_BT_PWR:
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], Set Dec BT power\n");
+		BTC_TRACE(trace_buf);
+
+		{
+			u8	data_len = 4;
+			u8	buf[6] = {0};
+			u8	dec_bt_pwr = 0, pwr_level = 0;
+
+			if (op_len == 2) {
+				dec_bt_pwr = pdata[0];
+				pwr_level = pdata[1];
+
+				buf[0] = data_len;
+				buf[1] = 0x3;		/* OP_Code */
+				buf[2] = 0x2;		/* OP_Code_Length */
+
+				buf[3] = dec_bt_pwr;	/* OP_Code_Content */
+				buf[4] = pwr_level;
+				BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+					"[BTCoex], Set Dec BT power=%d, pwr_level=%d\n",
+					    dec_bt_pwr, pwr_level);
+				BTC_TRACE(trace_buf);
+
+				btcoexist->btc_set(btcoexist,
+						   BTC_SET_ACT_CTRL_BT_COEX,
+						   (void *)&buf[0]);
+			}
+		}
+		break;
+
+	case BTC_DBG_SET_COEX_BT_AFH_MAP:
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], Set BT AFH Map\n");
+		BTC_TRACE(trace_buf);
+		{
+			u8	data_len = 5;
+			u8	buf[6] = {0};
+
+			if (op_len == 3) {
+				buf[0] = data_len;
+				buf[1] = 0x5;				/* OP_Code */
+				buf[2] = 0x3;				/* OP_Code_Length */
+
+				buf[3] = pdata[0];			/* OP_Code_Content */
+				buf[4] = pdata[1];
+				buf[5] = pdata[2];
+
+				BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+					"[BTCoex], Set BT AFH Map = %02x %02x %02x\n",
+					    pdata[0], pdata[1], pdata[2]);
+				BTC_TRACE(trace_buf);
+				btcoexist->btc_set(btcoexist,
+						   BTC_SET_ACT_CTRL_BT_COEX,
+						   (void *)&buf[0]);
+			}
+		}
+		break;
+
+	case BTC_DBG_SET_COEX_BT_IGNORE_WLAN_ACT:
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], Set BT Ignore Wlan Active\n");
+		BTC_TRACE(trace_buf);
+		{
+			u8	data_len = 3;
+			u8	buf[6] = {0};
+
+			if (op_len == 1) {
+				buf[0] = data_len;
+				buf[1] = 0x1;			/* OP_Code */
+				buf[2] = 0x1;			/* OP_Code_Length */
+
+				buf[3] = pdata[0];		/* OP_Code_Content */
+				BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+					"[BTCoex], Set BT Ignore Wlan Active = 0x%x\n",
+					    pdata[0]);
+				BTC_TRACE(trace_buf);
+
+				btcoexist->btc_set(btcoexist,
+						   BTC_SET_ACT_CTRL_BT_COEX,
+						   (void *)&buf[0]);
+			}
+		}
+		break;
+
+	default:
+		break;
+	}
+}
+
+#endif
+
+#endif	/* #if (BT_SUPPORT == 1 && COEX_SUPPORT == 1) */
+
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/btc/halbtc8812a2ant.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/btc/halbtc8812a2ant.h
--- linux-5.6.3/3rdparty/rtl8821ce/hal/btc/halbtc8812a2ant.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/btc/halbtc8812a2ant.h	2020-04-10 16:35:06.783658527 +0300
@@ -0,0 +1,227 @@
+
+#if (BT_SUPPORT == 1 && COEX_SUPPORT == 1)
+
+#if (RTL8812A_SUPPORT == 1)
+
+/* *******************************************
+ * The following is for 8812A 2Ant BT Co-exist definition
+ * ******************************************* */
+#define	BT_AUTO_REPORT_ONLY_8812A_2ANT				0
+
+#define	BT_INFO_8812A_2ANT_B_FTP						BIT(7)
+#define	BT_INFO_8812A_2ANT_B_A2DP					BIT(6)
+#define	BT_INFO_8812A_2ANT_B_HID						BIT(5)
+#define	BT_INFO_8812A_2ANT_B_SCO_BUSY				BIT(4)
+#define	BT_INFO_8812A_2ANT_B_ACL_BUSY				BIT(3)
+#define	BT_INFO_8812A_2ANT_B_INQ_PAGE				BIT(2)
+#define	BT_INFO_8812A_2ANT_B_SCO_ESCO				BIT(1)
+#define	BT_INFO_8812A_2ANT_B_CONNECTION				BIT(0)
+
+#define	BT_INFO_8812A_2ANT_A2DP_BASIC_RATE(_BT_INFO_EXT_)	\
+		(((_BT_INFO_EXT_&BIT(0))) ? true : false)
+
+#define		BTC_RSSI_COEX_THRESH_TOL_8812A_2ANT		2
+#define	NOISY_AP_NUM_THRESH_8812A						50
+
+enum bt_info_src_8812a_2ant {
+	BT_INFO_SRC_8812A_2ANT_WIFI_FW			= 0x0,
+	BT_INFO_SRC_8812A_2ANT_BT_RSP				= 0x1,
+	BT_INFO_SRC_8812A_2ANT_BT_ACTIVE_SEND		= 0x2,
+	BT_INFO_SRC_8812A_2ANT_MAX
+};
+
+enum bt_8812a_2ant_bt_status {
+	BT_8812A_2ANT_BT_STATUS_NON_CONNECTED_IDLE	= 0x0,
+	BT_8812A_2ANT_BT_STATUS_CONNECTED_IDLE		= 0x1,
+	BT_8812A_2ANT_BT_STATUS_INQ_PAGE				= 0x2,
+	BT_8812A_2ANT_BT_STATUS_ACL_BUSY				= 0x3,
+	BT_8812A_2ANT_BT_STATUS_SCO_BUSY				= 0x4,
+	BT_8812A_2ANT_BT_STATUS_ACL_SCO_BUSY			= 0x5,
+	BT_8812A_2ANT_BT_STATUS_MAX
+};
+
+enum bt_8812a_2ant_coex_algo {
+	BT_8812A_2ANT_COEX_ALGO_UNDEFINED		= 0x0,
+	BT_8812A_2ANT_COEX_ALGO_SCO				= 0x1,
+	BT_8812A_2ANT_COEX_ALGO_SCO_HID		= 0x2,
+	BT_8812A_2ANT_COEX_ALGO_HID				= 0x3,
+	BT_8812A_2ANT_COEX_ALGO_A2DP			= 0x4,
+	BT_8812A_2ANT_COEX_ALGO_A2DP_PANHS		= 0x5,
+	BT_8812A_2ANT_COEX_ALGO_PANEDR			= 0x6,
+	BT_8812A_2ANT_COEX_ALGO_PANHS			= 0x7,
+	BT_8812A_2ANT_COEX_ALGO_PANEDR_A2DP		= 0x8,
+	BT_8812A_2ANT_COEX_ALGO_PANEDR_HID		= 0x9,
+	BT_8812A_2ANT_COEX_ALGO_HID_A2DP_PANEDR	= 0xa,
+	BT_8812A_2ANT_COEX_ALGO_HID_A2DP_PANHS	= 0xb,
+	BT_8812A_2ANT_COEX_ALGO_HID_A2DP		= 0xc,
+	BT_8812A_2ANT_COEX_ALGO_MAX				= 0xd
+};
+
+struct coex_dm_8812a_2ant {
+	/* fw mechanism */
+	u8		pre_bt_dec_pwr_lvl;
+	u8		cur_bt_dec_pwr_lvl;
+	u8		pre_fw_dac_swing_lvl;
+	u8		cur_fw_dac_swing_lvl;
+	boolean		cur_ignore_wlan_act;
+	boolean		pre_ignore_wlan_act;
+	u8		pre_ps_tdma;
+	u8		cur_ps_tdma;
+	u8		ps_tdma_para[5];
+	u8		ps_tdma_du_adj_type;
+	boolean		auto_tdma_adjust;
+	boolean		auto_tdma_adjust_low_rssi;
+	boolean		pre_ps_tdma_on;
+	boolean		cur_ps_tdma_on;
+	boolean		pre_bt_auto_report;
+	boolean		cur_bt_auto_report;
+	u8		pre_lps;
+	u8		cur_lps;
+	u8		pre_rpwm;
+	u8		cur_rpwm;
+
+	/* sw mechanism */
+	boolean		pre_rf_rx_lpf_shrink;
+	boolean		cur_rf_rx_lpf_shrink;
+	u32		bt_rf_0x1e_backup;
+	boolean	pre_low_penalty_ra;
+	boolean		cur_low_penalty_ra;
+	boolean		pre_dac_swing_on;
+	u32		pre_dac_swing_lvl;
+	boolean		cur_dac_swing_on;
+	u32		cur_dac_swing_lvl;
+	boolean		pre_adc_back_off;
+	boolean		cur_adc_back_off;
+	boolean	pre_agc_table_en;
+	boolean		cur_agc_table_en;
+	u32		pre_val0x6c0;
+	u32		cur_val0x6c0;
+	u32		pre_val0x6c4;
+	u32		cur_val0x6c4;
+	u32		pre_val0x6c8;
+	u32		cur_val0x6c8;
+	u8		pre_val0x6cc;
+	u8		cur_val0x6cc;
+	boolean		limited_dig;
+	u32		backup_arfr_cnt1;	/* Auto Rate Fallback Retry cnt */
+	u32		backup_arfr_cnt2;	/* Auto Rate Fallback Retry cnt */
+	u16		backup_retry_limit;
+	u8		backup_ampdu_max_time;
+
+	/* algorithm related */
+	u8		pre_algorithm;
+	u8		cur_algorithm;
+	u8		bt_status;
+	u8		wifi_chnl_info[3];
+
+	u32		pre_ra_mask;
+	u32		cur_ra_mask;
+	u8		cur_ra_mask_type;
+	u8		pre_arfr_type;
+	u8		cur_arfr_type;
+	u8		pre_retry_limit_type;
+	u8		cur_retry_limit_type;
+	u8		pre_ampdu_time_type;
+	u8		cur_ampdu_time_type;
+
+	boolean	cur_enable_pta;
+	boolean	pre_enable_pta;
+};
+
+struct coex_sta_8812a_2ant {
+	boolean					bt_disabled;
+	boolean					bt_link_exist;
+	boolean					sco_exist;
+	boolean					a2dp_exist;
+	boolean					hid_exist;
+	boolean					pan_exist;
+	boolean					acl_busy;
+
+	boolean					under_lps;
+	boolean					under_ips;
+	u32					high_priority_tx;
+	u32					high_priority_rx;
+	u32					low_priority_tx;
+	u32					low_priority_rx;
+	u8					bt_rssi;
+	u8					pre_bt_rssi_state;
+	u8					pre_wifi_rssi_state[4];
+	boolean					c2h_bt_info_req_sent;
+	u8					bt_info_c2h[BT_INFO_SRC_8812A_2ANT_MAX][10];
+	u32					bt_info_c2h_cnt[BT_INFO_SRC_8812A_2ANT_MAX];
+	u32					bt_info_query_cnt;
+	boolean					c2h_bt_inquiry_page;
+	u8					bt_retry_cnt;
+	u8					bt_info_ext;
+	u8					scan_ap_num;
+	boolean				pre_bt_disabled;
+	u32					pre_bt_info_c2h_cnt_bt_rsp;
+	u32					pre_bt_info_c2h_cnt_bt_send;
+	boolean				force_lps_on;
+	u32				bt_coex_supported_version;
+
+	u32				crc_ok_cck;
+	u32				crc_ok_11g;
+	u32				crc_ok_11n;
+	u32				crc_ok_11n_vht;
+
+	u32				crc_err_cck;
+	u32				crc_err_11g;
+	u32				crc_err_11n;
+	u32				crc_err_11n_vht;
+};
+
+/* *******************************************
+ * The following is interface which will notify coex module.
+ * ******************************************* */
+void ex_halbtc8812a2ant_power_on_setting(IN struct btc_coexist *btcoexist);
+void ex_halbtc8812a2ant_init_hw_config(IN struct btc_coexist *btcoexist,
+				       IN boolean wifi_only);
+void ex_halbtc8812a2ant_init_coex_dm(IN struct btc_coexist *btcoexist);
+void ex_halbtc8812a2ant_ips_notify(IN struct btc_coexist *btcoexist,
+				   IN u8 type);
+void ex_halbtc8812a2ant_lps_notify(IN struct btc_coexist *btcoexist,
+				   IN u8 type);
+void ex_halbtc8812a2ant_scan_notify(IN struct btc_coexist *btcoexist,
+				    IN u8 type);
+void ex_halbtc8812a2ant_connect_notify(IN struct btc_coexist *btcoexist,
+				       IN u8 type);
+void ex_halbtc8812a2ant_media_status_notify(IN struct btc_coexist *btcoexist,
+		IN u8 type);
+void ex_halbtc8812a2ant_specific_packet_notify(IN struct btc_coexist *btcoexist,
+		IN u8 type);
+void ex_halbtc8812a2ant_bt_info_notify(IN struct btc_coexist *btcoexist,
+				       IN u8 *tmp_buf, IN u8 length);
+void ex_halbtc8812a2ant_rf_status_notify(IN struct btc_coexist *btcoexist,
+		IN u8 type);
+
+void ex_halbtc8812a2ant_halt_notify(IN struct btc_coexist *btcoexist);
+void ex_halbtc8812a2ant_periodical(IN struct btc_coexist *btcoexist);
+void ex_halbtc8812a2ant_display_coex_info(IN struct btc_coexist *btcoexist);
+void ex_halbtc8812a2ant_dbg_control(IN struct btc_coexist *btcoexist,
+				    IN u8 op_code, IN u8 op_len, IN u8 *pdata);
+void ex_halbtc8812a2ant_pta_off_on_notify(IN struct btc_coexist *btcoexist,
+		IN u8 bt_status);
+
+#else
+#define	ex_halbtc8812a2ant_power_on_setting(btcoexist)
+#define	ex_halbtc8812a2ant_init_hw_config(btcoexist, wifi_only)
+#define	ex_halbtc8812a2ant_init_coex_dm(btcoexist)
+#define	ex_halbtc8812a2ant_ips_notify(btcoexist, type)
+#define	ex_halbtc8812a2ant_lps_notify(btcoexist, type)
+#define	ex_halbtc8812a2ant_scan_notify(btcoexist, type)
+#define	ex_halbtc8812a2ant_connect_notify(btcoexist, type)
+#define	ex_halbtc8812a2ant_media_status_notify(btcoexist, type)
+#define	ex_halbtc8812a2ant_specific_packet_notify(btcoexist, type)
+#define	ex_halbtc8812a2ant_bt_info_notify(btcoexist, tmp_buf, length)
+#define	ex_halbtc8812a2ant_rf_status_notify(btcoexist, type)
+#define	ex_halbtc8812a2ant_halt_notify(btcoexist)
+#define	ex_halbtc8812a2ant_periodical(btcoexist)
+#define	ex_halbtc8812a2ant_display_coex_info(btcoexist)
+#define	ex_halbtc8812a2ant_dbg_control(btcoexist, op_code, op_len, pdata)
+#define ex_halbtc8812a2ant_pta_off_on_notify(btcoexist, bt_status)
+
+#endif
+
+#endif
+
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/btc/halbtc8821a1ant.c linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/btc/halbtc8821a1ant.c
--- linux-5.6.3/3rdparty/rtl8821ce/hal/btc/halbtc8821a1ant.c	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/btc/halbtc8821a1ant.c	2020-04-10 16:35:06.784658573 +0300
@@ -0,0 +1,3256 @@
+/* ************************************************************
+ * Description:
+ *
+ * This file is for 8821A_1ANT Co-exist mechanism
+ *
+ * History
+ * 2012/11/15 Cosa first check in.
+ *
+ * ************************************************************
+ * SY modify 2015/04/27
+ * ************************************************************
+ * include files
+ * ************************************************************ */
+#include "mp_precomp.h"
+
+#if (BT_SUPPORT == 1 && COEX_SUPPORT == 1)
+
+#if (RTL8821A_SUPPORT == 1)
+/* ************************************************************
+ * Global variables, these are static variables
+ * ************************************************************ */
+static u8	 *trace_buf = &gl_btc_trace_buf[0];
+static struct  coex_dm_8821a_1ant		glcoex_dm_8821a_1ant;
+static struct  coex_dm_8821a_1ant	*coex_dm = &glcoex_dm_8821a_1ant;
+static struct  coex_sta_8821a_1ant		glcoex_sta_8821a_1ant;
+static struct  coex_sta_8821a_1ant	*coex_sta = &glcoex_sta_8821a_1ant;
+
+const char *const glbt_info_src_8821a_1ant[] = {
+	"BT Info[wifi fw]",
+	"BT Info[bt rsp]",
+	"BT Info[bt auto report]",
+};
+
+u32	glcoex_ver_date_8821a_1ant = 20161128;
+u32	glcoex_ver_8821a_1ant = 0x64;
+u32	glcoex_ver_btdesired_8821a_1ant = 0x62;
+
+/* ************************************************************
+ * local function proto type if needed
+ * ************************************************************
+ * ************************************************************
+ * local function start with halbtc8821a1ant_
+ * ************************************************************ */
+u8 halbtc8821a1ant_bt_rssi_state(u8 level_num, u8 rssi_thresh, u8 rssi_thresh1)
+{
+	s32			bt_rssi = 0;
+	u8			bt_rssi_state = coex_sta->pre_bt_rssi_state;
+
+	bt_rssi = coex_sta->bt_rssi;
+
+	if (level_num == 2) {
+		if ((coex_sta->pre_bt_rssi_state == BTC_RSSI_STATE_LOW) ||
+		    (coex_sta->pre_bt_rssi_state ==
+		     BTC_RSSI_STATE_STAY_LOW)) {
+			if (bt_rssi >= (rssi_thresh +
+					BTC_RSSI_COEX_THRESH_TOL_8821A_1ANT))
+				bt_rssi_state = BTC_RSSI_STATE_HIGH;
+			else
+				bt_rssi_state = BTC_RSSI_STATE_STAY_LOW;
+		} else {
+			if (bt_rssi < rssi_thresh)
+				bt_rssi_state = BTC_RSSI_STATE_LOW;
+			else
+				bt_rssi_state = BTC_RSSI_STATE_STAY_HIGH;
+		}
+	} else if (level_num == 3) {
+		if (rssi_thresh > rssi_thresh1) {
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				    "[BTCoex], BT Rssi thresh error!!\n");
+			BTC_TRACE(trace_buf);
+			return coex_sta->pre_bt_rssi_state;
+		}
+
+		if ((coex_sta->pre_bt_rssi_state == BTC_RSSI_STATE_LOW) ||
+		    (coex_sta->pre_bt_rssi_state ==
+		     BTC_RSSI_STATE_STAY_LOW)) {
+			if (bt_rssi >= (rssi_thresh +
+					BTC_RSSI_COEX_THRESH_TOL_8821A_1ANT))
+				bt_rssi_state = BTC_RSSI_STATE_MEDIUM;
+			else
+				bt_rssi_state = BTC_RSSI_STATE_STAY_LOW;
+		} else if ((coex_sta->pre_bt_rssi_state ==
+			    BTC_RSSI_STATE_MEDIUM) ||
+			   (coex_sta->pre_bt_rssi_state ==
+			    BTC_RSSI_STATE_STAY_MEDIUM)) {
+			if (bt_rssi >= (rssi_thresh1 +
+					BTC_RSSI_COEX_THRESH_TOL_8821A_1ANT))
+				bt_rssi_state = BTC_RSSI_STATE_HIGH;
+			else if (bt_rssi < rssi_thresh)
+				bt_rssi_state = BTC_RSSI_STATE_LOW;
+			else
+				bt_rssi_state = BTC_RSSI_STATE_STAY_MEDIUM;
+		} else {
+			if (bt_rssi < rssi_thresh1)
+				bt_rssi_state = BTC_RSSI_STATE_MEDIUM;
+			else
+				bt_rssi_state = BTC_RSSI_STATE_STAY_HIGH;
+		}
+	}
+
+	coex_sta->pre_bt_rssi_state = bt_rssi_state;
+
+	return bt_rssi_state;
+}
+
+u8 halbtc8821a1ant_wifi_rssi_state(IN struct btc_coexist *btcoexist,
+	   IN u8 index, IN u8 level_num, IN u8 rssi_thresh, IN u8 rssi_thresh1)
+{
+	s32			wifi_rssi = 0;
+	u8			wifi_rssi_state = coex_sta->pre_wifi_rssi_state[index];
+
+	btcoexist->btc_get(btcoexist, BTC_GET_S4_WIFI_RSSI, &wifi_rssi);
+
+	if (level_num == 2) {
+		if ((coex_sta->pre_wifi_rssi_state[index] == BTC_RSSI_STATE_LOW)
+		    ||
+		    (coex_sta->pre_wifi_rssi_state[index] ==
+		     BTC_RSSI_STATE_STAY_LOW)) {
+			if (wifi_rssi >= (rssi_thresh +
+					  BTC_RSSI_COEX_THRESH_TOL_8821A_1ANT))
+				wifi_rssi_state = BTC_RSSI_STATE_HIGH;
+			else
+				wifi_rssi_state = BTC_RSSI_STATE_STAY_LOW;
+		} else {
+			if (wifi_rssi < rssi_thresh)
+				wifi_rssi_state = BTC_RSSI_STATE_LOW;
+			else
+				wifi_rssi_state = BTC_RSSI_STATE_STAY_HIGH;
+		}
+	} else if (level_num == 3) {
+		if (rssi_thresh > rssi_thresh1) {
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				    "[BTCoex], wifi RSSI thresh error!!\n");
+			BTC_TRACE(trace_buf);
+			return coex_sta->pre_wifi_rssi_state[index];
+		}
+
+		if ((coex_sta->pre_wifi_rssi_state[index] == BTC_RSSI_STATE_LOW)
+		    ||
+		    (coex_sta->pre_wifi_rssi_state[index] ==
+		     BTC_RSSI_STATE_STAY_LOW)) {
+			if (wifi_rssi >= (rssi_thresh +
+					  BTC_RSSI_COEX_THRESH_TOL_8821A_1ANT))
+				wifi_rssi_state = BTC_RSSI_STATE_MEDIUM;
+			else
+				wifi_rssi_state = BTC_RSSI_STATE_STAY_LOW;
+		} else if ((coex_sta->pre_wifi_rssi_state[index] ==
+			    BTC_RSSI_STATE_MEDIUM) ||
+			   (coex_sta->pre_wifi_rssi_state[index] ==
+			    BTC_RSSI_STATE_STAY_MEDIUM)) {
+			if (wifi_rssi >= (rssi_thresh1 +
+					  BTC_RSSI_COEX_THRESH_TOL_8821A_1ANT))
+				wifi_rssi_state = BTC_RSSI_STATE_HIGH;
+			else if (wifi_rssi < rssi_thresh)
+				wifi_rssi_state = BTC_RSSI_STATE_LOW;
+			else
+				wifi_rssi_state = BTC_RSSI_STATE_STAY_MEDIUM;
+		} else {
+			if (wifi_rssi < rssi_thresh1)
+				wifi_rssi_state = BTC_RSSI_STATE_MEDIUM;
+			else
+				wifi_rssi_state = BTC_RSSI_STATE_STAY_HIGH;
+		}
+	}
+
+	coex_sta->pre_wifi_rssi_state[index] = wifi_rssi_state;
+
+	return wifi_rssi_state;
+}
+
+void halbtc8821a1ant_update_ra_mask(IN struct btc_coexist *btcoexist,
+				    IN boolean force_exec, IN u32 dis_rate_mask)
+{
+	coex_dm->cur_ra_mask = dis_rate_mask;
+
+	if (force_exec || (coex_dm->pre_ra_mask != coex_dm->cur_ra_mask))
+		btcoexist->btc_set(btcoexist, BTC_SET_ACT_UPDATE_RAMASK,
+				   &coex_dm->cur_ra_mask);
+	coex_dm->pre_ra_mask = coex_dm->cur_ra_mask;
+}
+
+void halbtc8821a1ant_auto_rate_fallback_retry(IN struct btc_coexist *btcoexist,
+		IN boolean force_exec, IN u8 type)
+{
+	boolean	wifi_under_b_mode = false;
+
+	coex_dm->cur_arfr_type = type;
+
+	if (force_exec || (coex_dm->pre_arfr_type != coex_dm->cur_arfr_type)) {
+		switch (coex_dm->cur_arfr_type) {
+		case 0:	/* normal mode */
+			btcoexist->btc_write_4byte(btcoexist, 0x430,
+						   coex_dm->backup_arfr_cnt1);
+			btcoexist->btc_write_4byte(btcoexist, 0x434,
+						   coex_dm->backup_arfr_cnt2);
+			break;
+		case 1:
+			btcoexist->btc_get(btcoexist,
+					   BTC_GET_BL_WIFI_UNDER_B_MODE,
+					   &wifi_under_b_mode);
+			if (wifi_under_b_mode) {
+				btcoexist->btc_write_4byte(btcoexist,
+							   0x430, 0x0);
+				btcoexist->btc_write_4byte(btcoexist,
+							   0x434, 0x01010101);
+			} else {
+				btcoexist->btc_write_4byte(btcoexist,
+							   0x430, 0x0);
+				btcoexist->btc_write_4byte(btcoexist,
+							   0x434, 0x04030201);
+			}
+			break;
+		default:
+			break;
+		}
+	}
+
+	coex_dm->pre_arfr_type = coex_dm->cur_arfr_type;
+}
+
+void halbtc8821a1ant_retry_limit(IN struct btc_coexist *btcoexist,
+				 IN boolean force_exec, IN u8 type)
+{
+	coex_dm->cur_retry_limit_type = type;
+
+	if (force_exec ||
+	    (coex_dm->pre_retry_limit_type !=
+	     coex_dm->cur_retry_limit_type)) {
+		switch (coex_dm->cur_retry_limit_type) {
+		case 0:	/* normal mode */
+			btcoexist->btc_write_2byte(btcoexist, 0x42a,
+						   coex_dm->backup_retry_limit);
+			break;
+		case 1:	/* retry limit=8 */
+			btcoexist->btc_write_2byte(btcoexist, 0x42a,
+						   0x0808);
+			break;
+		default:
+			break;
+		}
+	}
+
+	coex_dm->pre_retry_limit_type = coex_dm->cur_retry_limit_type;
+}
+
+void halbtc8821a1ant_ampdu_max_time(IN struct btc_coexist *btcoexist,
+				    IN boolean force_exec, IN u8 type)
+{
+	coex_dm->cur_ampdu_time_type = type;
+
+	if (force_exec ||
+	    (coex_dm->pre_ampdu_time_type != coex_dm->cur_ampdu_time_type)) {
+		switch (coex_dm->cur_ampdu_time_type) {
+		case 0:	/* normal mode */
+			btcoexist->btc_write_1byte(btcoexist, 0x456,
+					   coex_dm->backup_ampdu_max_time);
+			break;
+		case 1:	/* AMPDU timw = 0x38 * 32us */
+			btcoexist->btc_write_1byte(btcoexist, 0x456,
+						   0x38);
+			break;
+		default:
+			break;
+		}
+	}
+
+	coex_dm->pre_ampdu_time_type = coex_dm->cur_ampdu_time_type;
+}
+
+void halbtc8821a1ant_limited_tx(IN struct btc_coexist *btcoexist,
+		IN boolean force_exec, IN u8 ra_mask_type, IN u8 arfr_type,
+				IN u8 retry_limit_type, IN u8 ampdu_time_type)
+{
+	switch (ra_mask_type) {
+	case 0:	/* normal mode */
+		halbtc8821a1ant_update_ra_mask(btcoexist, force_exec,
+					       0x0);
+		break;
+	case 1:	/* disable cck 1/2 */
+		halbtc8821a1ant_update_ra_mask(btcoexist, force_exec,
+					       0x00000003);
+		break;
+	case 2:	/* disable cck 1/2/5.5, ofdm 6/9/12/18/24, mcs 0/1/2/3/4 */
+		halbtc8821a1ant_update_ra_mask(btcoexist, force_exec,
+					       0x0001f1f7);
+		break;
+	default:
+		break;
+	}
+
+	halbtc8821a1ant_auto_rate_fallback_retry(btcoexist, force_exec,
+			arfr_type);
+	halbtc8821a1ant_retry_limit(btcoexist, force_exec, retry_limit_type);
+	halbtc8821a1ant_ampdu_max_time(btcoexist, force_exec, ampdu_time_type);
+}
+
+
+/* true/xxxx/x:1
+ * false/false/x: 64
+ * false/true/x:x */
+void halbtc8821a1ant_limited_rx(IN struct btc_coexist *btcoexist,
+			IN boolean force_exec, IN boolean rej_ap_agg_pkt,
+			IN boolean bt_ctrl_agg_buf_size, IN u8 agg_buf_size)
+{
+	boolean	reject_rx_agg = rej_ap_agg_pkt;
+	boolean	bt_ctrl_rx_agg_size = bt_ctrl_agg_buf_size;
+	u8	rx_agg_size = agg_buf_size;
+
+	/* ============================================ */
+	/*	Rx Aggregation related setting */
+	/* ============================================ */
+	btcoexist->btc_set(btcoexist, BTC_SET_BL_TO_REJ_AP_AGG_PKT,
+			   &reject_rx_agg);
+	/* decide BT control aggregation buf size or not */
+	btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_CTRL_AGG_SIZE,
+			   &bt_ctrl_rx_agg_size);
+	/* aggregation buf size, only work when BT control Rx aggregation size. */
+	btcoexist->btc_set(btcoexist, BTC_SET_U1_AGG_BUF_SIZE, &rx_agg_size);
+	/* real update aggregation setting */
+	btcoexist->btc_set(btcoexist, BTC_SET_ACT_AGGREGATE_CTRL, NULL);
+
+
+}
+
+void halbtc8821a1ant_monitor_bt_ctr(IN struct btc_coexist *btcoexist)
+{
+	u32			reg_hp_txrx, reg_lp_txrx, u32tmp;
+	u32			reg_hp_tx = 0, reg_hp_rx = 0, reg_lp_tx = 0, reg_lp_rx = 0;
+#if 0
+	/* to avoid 0x76e[3] = 1 (WLAN_Act control by PTA) during IPS */
+	if (!(btcoexist->btc_read_1byte(btcoexist, 0x76e) & 0x8)) {
+		coex_sta->high_priority_tx = 65535;
+		coex_sta->high_priority_rx = 65535;
+		coex_sta->low_priority_tx = 65535;
+		coex_sta->low_priority_rx = 65535;
+		return;
+	}
+#endif
+	reg_hp_txrx = 0x770;
+	reg_lp_txrx = 0x774;
+
+	u32tmp = btcoexist->btc_read_4byte(btcoexist, reg_hp_txrx);
+	reg_hp_tx = u32tmp & MASKLWORD;
+	reg_hp_rx = (u32tmp & MASKHWORD) >> 16;
+
+	u32tmp = btcoexist->btc_read_4byte(btcoexist, reg_lp_txrx);
+	reg_lp_tx = u32tmp & MASKLWORD;
+	reg_lp_rx = (u32tmp & MASKHWORD) >> 16;
+
+	coex_sta->high_priority_tx = reg_hp_tx;
+	coex_sta->high_priority_rx = reg_hp_rx;
+	coex_sta->low_priority_tx = reg_lp_tx;
+	coex_sta->low_priority_rx = reg_lp_rx;
+
+	/* reset counter */
+	btcoexist->btc_write_1byte(btcoexist, 0x76e, 0xc);
+}
+
+void halbtc8821a1ant_monitor_wifi_ctr(IN struct btc_coexist *btcoexist)
+{
+#if 1
+
+	coex_sta->crc_ok_cck = btcoexist->btc_phydm_query_PHY_counter(
+				       btcoexist,
+				       PHYDM_INFO_CRC32_OK_CCK);
+	coex_sta->crc_ok_11g = btcoexist->btc_phydm_query_PHY_counter(
+				       btcoexist,
+				       PHYDM_INFO_CRC32_OK_LEGACY);
+	coex_sta->crc_ok_11n = btcoexist->btc_phydm_query_PHY_counter(
+				       btcoexist,
+				       PHYDM_INFO_CRC32_OK_HT);
+	coex_sta->crc_ok_11n_vht =
+		btcoexist->btc_phydm_query_PHY_counter(
+			btcoexist,
+			PHYDM_INFO_CRC32_OK_VHT);
+
+	coex_sta->crc_err_cck = btcoexist->btc_phydm_query_PHY_counter(
+					btcoexist,
+					PHYDM_INFO_CRC32_ERROR_CCK);
+	coex_sta->crc_err_11g =  btcoexist->btc_phydm_query_PHY_counter(
+					 btcoexist,
+					 PHYDM_INFO_CRC32_ERROR_LEGACY);
+	coex_sta->crc_err_11n = btcoexist->btc_phydm_query_PHY_counter(
+					btcoexist,
+					PHYDM_INFO_CRC32_ERROR_HT);
+	coex_sta->crc_err_11n_vht =
+		btcoexist->btc_phydm_query_PHY_counter(
+			btcoexist,
+			PHYDM_INFO_CRC32_ERROR_VHT);
+
+#endif
+}
+
+
+void halbtc8821a1ant_query_bt_info(IN struct btc_coexist *btcoexist)
+{
+	u8			h2c_parameter[1] = {0};
+
+	coex_sta->c2h_bt_info_req_sent = true;
+
+	h2c_parameter[0] |= BIT(0);	/* trigger */
+
+	btcoexist->btc_fill_h2c(btcoexist, 0x61, 1, h2c_parameter);
+}
+
+boolean halbtc8821a1ant_is_wifi_status_changed(IN struct btc_coexist *btcoexist)
+{
+	static boolean	pre_wifi_busy = false, pre_under_4way = false,
+			pre_bt_hs_on = false;
+	boolean wifi_busy = false, under_4way = false, bt_hs_on = false;
+	boolean wifi_connected = false;
+
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED,
+			   &wifi_connected);
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy);
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on);
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_4_WAY_PROGRESS,
+			   &under_4way);
+
+	if (wifi_connected) {
+		if (wifi_busy != pre_wifi_busy) {
+			pre_wifi_busy = wifi_busy;
+			return true;
+		}
+		if (under_4way != pre_under_4way) {
+			pre_under_4way = under_4way;
+			return true;
+		}
+		if (bt_hs_on != pre_bt_hs_on) {
+			pre_bt_hs_on = bt_hs_on;
+			return true;
+		}
+	}
+
+	return false;
+}
+
+void halbtc8821a1ant_update_bt_link_info(IN struct btc_coexist *btcoexist)
+{
+	struct  btc_bt_link_info	*bt_link_info = &btcoexist->bt_link_info;
+	boolean				bt_hs_on = false;
+
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on);
+
+	bt_link_info->bt_link_exist = coex_sta->bt_link_exist;
+	bt_link_info->sco_exist = coex_sta->sco_exist;
+	bt_link_info->a2dp_exist = coex_sta->a2dp_exist;
+	bt_link_info->pan_exist = coex_sta->pan_exist;
+	bt_link_info->hid_exist = coex_sta->hid_exist;
+
+	/* work around for HS mode. */
+	if (bt_hs_on) {
+		bt_link_info->pan_exist = true;
+		bt_link_info->bt_link_exist = true;
+	}
+
+	/* check if Sco only */
+	if (bt_link_info->sco_exist &&
+	    !bt_link_info->a2dp_exist &&
+	    !bt_link_info->pan_exist &&
+	    !bt_link_info->hid_exist)
+		bt_link_info->sco_only = true;
+	else
+		bt_link_info->sco_only = false;
+
+	/* check if A2dp only */
+	if (!bt_link_info->sco_exist &&
+	    bt_link_info->a2dp_exist &&
+	    !bt_link_info->pan_exist &&
+	    !bt_link_info->hid_exist)
+		bt_link_info->a2dp_only = true;
+	else
+		bt_link_info->a2dp_only = false;
+
+	/* check if Pan only */
+	if (!bt_link_info->sco_exist &&
+	    !bt_link_info->a2dp_exist &&
+	    bt_link_info->pan_exist &&
+	    !bt_link_info->hid_exist)
+		bt_link_info->pan_only = true;
+	else
+		bt_link_info->pan_only = false;
+
+	/* check if Hid only */
+	if (!bt_link_info->sco_exist &&
+	    !bt_link_info->a2dp_exist &&
+	    !bt_link_info->pan_exist &&
+	    bt_link_info->hid_exist)
+		bt_link_info->hid_only = true;
+	else
+		bt_link_info->hid_only = false;
+}
+
+u8 halbtc8821a1ant_action_algorithm(IN struct btc_coexist *btcoexist)
+{
+	struct  btc_bt_link_info	*bt_link_info = &btcoexist->bt_link_info;
+	boolean				bt_hs_on = false;
+	u8				algorithm = BT_8821A_1ANT_COEX_ALGO_UNDEFINED;
+	u8				num_of_diff_profile = 0;
+
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on);
+
+	if (!bt_link_info->bt_link_exist) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], No BT link exists!!!\n");
+		BTC_TRACE(trace_buf);
+		return algorithm;
+	}
+
+	if (bt_link_info->sco_exist)
+		num_of_diff_profile++;
+	if (bt_link_info->hid_exist)
+		num_of_diff_profile++;
+	if (bt_link_info->pan_exist)
+		num_of_diff_profile++;
+	if (bt_link_info->a2dp_exist)
+		num_of_diff_profile++;
+
+	if (num_of_diff_profile == 1) {
+		if (bt_link_info->sco_exist) {
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				    "[BTCoex], BT Profile = SCO only\n");
+			BTC_TRACE(trace_buf);
+			algorithm = BT_8821A_1ANT_COEX_ALGO_SCO;
+		} else {
+			if (bt_link_info->hid_exist) {
+				BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+					"[BTCoex], BT Profile = HID only\n");
+				BTC_TRACE(trace_buf);
+				algorithm = BT_8821A_1ANT_COEX_ALGO_HID;
+			} else if (bt_link_info->a2dp_exist) {
+				BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+					"[BTCoex], BT Profile = A2DP only\n");
+				BTC_TRACE(trace_buf);
+				algorithm = BT_8821A_1ANT_COEX_ALGO_A2DP;
+			} else if (bt_link_info->pan_exist) {
+				if (bt_hs_on) {
+					BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+						"[BTCoex], BT Profile = PAN(HS) only\n");
+					BTC_TRACE(trace_buf);
+					algorithm =
+						BT_8821A_1ANT_COEX_ALGO_PANHS;
+				} else {
+					BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+						"[BTCoex], BT Profile = PAN(EDR) only\n");
+					BTC_TRACE(trace_buf);
+					algorithm =
+						BT_8821A_1ANT_COEX_ALGO_PANEDR;
+				}
+			}
+		}
+	} else if (num_of_diff_profile == 2) {
+		if (bt_link_info->sco_exist) {
+			if (bt_link_info->hid_exist) {
+				BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+					"[BTCoex], BT Profile = SCO + HID\n");
+				BTC_TRACE(trace_buf);
+				algorithm = BT_8821A_1ANT_COEX_ALGO_HID;
+			} else if (bt_link_info->a2dp_exist) {
+				BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+					"[BTCoex], BT Profile = SCO + A2DP ==> SCO\n");
+				BTC_TRACE(trace_buf);
+				algorithm = BT_8821A_1ANT_COEX_ALGO_SCO;
+			} else if (bt_link_info->pan_exist) {
+				if (bt_hs_on) {
+					BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+						"[BTCoex], BT Profile = SCO + PAN(HS)\n");
+					BTC_TRACE(trace_buf);
+					algorithm = BT_8821A_1ANT_COEX_ALGO_SCO;
+				} else {
+					BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+						"[BTCoex], BT Profile = SCO + PAN(EDR)\n");
+					BTC_TRACE(trace_buf);
+					algorithm =
+						BT_8821A_1ANT_COEX_ALGO_PANEDR_HID;
+				}
+			}
+		} else {
+			if (bt_link_info->hid_exist &&
+			    bt_link_info->a2dp_exist) {
+				BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+					"[BTCoex], BT Profile = HID + A2DP\n");
+				BTC_TRACE(trace_buf);
+				algorithm = BT_8821A_1ANT_COEX_ALGO_HID_A2DP;
+			} else if (bt_link_info->hid_exist &&
+				   bt_link_info->pan_exist) {
+				if (bt_hs_on) {
+					BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+						"[BTCoex], BT Profile = HID + PAN(HS)\n");
+					BTC_TRACE(trace_buf);
+					algorithm =
+						BT_8821A_1ANT_COEX_ALGO_HID_A2DP;
+				} else {
+					BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+						"[BTCoex], BT Profile = HID + PAN(EDR)\n");
+					BTC_TRACE(trace_buf);
+					algorithm =
+						BT_8821A_1ANT_COEX_ALGO_PANEDR_HID;
+				}
+			} else if (bt_link_info->pan_exist &&
+				   bt_link_info->a2dp_exist) {
+				if (bt_hs_on) {
+					BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+						"[BTCoex], BT Profile = A2DP + PAN(HS)\n");
+					BTC_TRACE(trace_buf);
+					algorithm =
+						BT_8821A_1ANT_COEX_ALGO_A2DP_PANHS;
+				} else {
+					BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+						"[BTCoex], BT Profile = A2DP + PAN(EDR)\n");
+					BTC_TRACE(trace_buf);
+					algorithm =
+						BT_8821A_1ANT_COEX_ALGO_PANEDR_A2DP;
+				}
+			}
+		}
+	} else if (num_of_diff_profile == 3) {
+		if (bt_link_info->sco_exist) {
+			if (bt_link_info->hid_exist &&
+			    bt_link_info->a2dp_exist) {
+				BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+					"[BTCoex], BT Profile = SCO + HID + A2DP ==> HID\n");
+				BTC_TRACE(trace_buf);
+				algorithm = BT_8821A_1ANT_COEX_ALGO_HID;
+			} else if (bt_link_info->hid_exist &&
+				   bt_link_info->pan_exist) {
+				if (bt_hs_on) {
+					BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+						"[BTCoex], BT Profile = SCO + HID + PAN(HS)\n");
+					BTC_TRACE(trace_buf);
+					algorithm =
+						BT_8821A_1ANT_COEX_ALGO_HID_A2DP;
+				} else {
+					BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+						"[BTCoex], BT Profile = SCO + HID + PAN(EDR)\n");
+					BTC_TRACE(trace_buf);
+					algorithm =
+						BT_8821A_1ANT_COEX_ALGO_PANEDR_HID;
+				}
+			} else if (bt_link_info->pan_exist &&
+				   bt_link_info->a2dp_exist) {
+				if (bt_hs_on) {
+					BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+						"[BTCoex], BT Profile = SCO + A2DP + PAN(HS)\n");
+					BTC_TRACE(trace_buf);
+					algorithm = BT_8821A_1ANT_COEX_ALGO_SCO;
+				} else {
+					BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+						"[BTCoex], BT Profile = SCO + A2DP + PAN(EDR) ==> HID\n");
+					BTC_TRACE(trace_buf);
+					algorithm =
+						BT_8821A_1ANT_COEX_ALGO_PANEDR_HID;
+				}
+			}
+		} else {
+			if (bt_link_info->hid_exist &&
+			    bt_link_info->pan_exist &&
+			    bt_link_info->a2dp_exist) {
+				if (bt_hs_on) {
+					BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+						"[BTCoex], BT Profile = HID + A2DP + PAN(HS)\n");
+					BTC_TRACE(trace_buf);
+					algorithm =
+						BT_8821A_1ANT_COEX_ALGO_HID_A2DP;
+				} else {
+					BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+						"[BTCoex], BT Profile = HID + A2DP + PAN(EDR)\n");
+					BTC_TRACE(trace_buf);
+					algorithm =
+						BT_8821A_1ANT_COEX_ALGO_HID_A2DP_PANEDR;
+				}
+			}
+		}
+	} else if (num_of_diff_profile >= 3) {
+		if (bt_link_info->sco_exist) {
+			if (bt_link_info->hid_exist &&
+			    bt_link_info->pan_exist &&
+			    bt_link_info->a2dp_exist) {
+				if (bt_hs_on) {
+					BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+						"[BTCoex], Error!!! BT Profile = SCO + HID + A2DP + PAN(HS)\n");
+					BTC_TRACE(trace_buf);
+
+				} else {
+					BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+						"[BTCoex], BT Profile = SCO + HID + A2DP + PAN(EDR)==>PAN(EDR)+HID\n");
+					BTC_TRACE(trace_buf);
+					algorithm =
+						BT_8821A_1ANT_COEX_ALGO_PANEDR_HID;
+				}
+			}
+		}
+	}
+
+	return algorithm;
+}
+
+void halbtc8821a1ant_set_bt_auto_report(IN struct btc_coexist *btcoexist,
+					IN boolean enable_auto_report)
+{
+	u8			h2c_parameter[1] = {0};
+
+	h2c_parameter[0] = 0;
+
+	if (enable_auto_report)
+		h2c_parameter[0] |= BIT(0);
+
+	btcoexist->btc_fill_h2c(btcoexist, 0x68, 1, h2c_parameter);
+}
+
+void halbtc8821a1ant_bt_auto_report(IN struct btc_coexist *btcoexist,
+		    IN boolean force_exec, IN boolean enable_auto_report)
+{
+	coex_dm->cur_bt_auto_report = enable_auto_report;
+
+	if (!force_exec) {
+		if (coex_dm->pre_bt_auto_report == coex_dm->cur_bt_auto_report)
+			return;
+	}
+	halbtc8821a1ant_set_bt_auto_report(btcoexist,
+					   coex_dm->cur_bt_auto_report);
+
+	coex_dm->pre_bt_auto_report = coex_dm->cur_bt_auto_report;
+}
+
+void halbtc8821a1ant_set_sw_penalty_tx_rate_adaptive(IN struct btc_coexist
+		*btcoexist, IN boolean low_penalty_ra)
+{
+	u8			h2c_parameter[6] = {0};
+
+	h2c_parameter[0] = 0x6;	/* op_code, 0x6= Retry_Penalty */
+
+	if (low_penalty_ra) {
+		h2c_parameter[1] |= BIT(0);
+		h2c_parameter[2] =
+			0x00;  /* normal rate except MCS7/6/5, OFDM54/48/36 */
+		h2c_parameter[3] = 0xf5;  /* MCS7 or OFDM54 */
+		h2c_parameter[4] = 0xa0;  /* MCS6 or OFDM48 */
+		h2c_parameter[5] = 0xa0; /* MCS5 or OFDM36	 */
+	}
+
+	btcoexist->btc_fill_h2c(btcoexist, 0x69, 6, h2c_parameter);
+}
+
+void halbtc8821a1ant_low_penalty_ra(IN struct btc_coexist *btcoexist,
+			    IN boolean force_exec, IN boolean low_penalty_ra)
+{
+	coex_dm->cur_low_penalty_ra = low_penalty_ra;
+
+	if (!force_exec) {
+		if (coex_dm->pre_low_penalty_ra == coex_dm->cur_low_penalty_ra)
+			return;
+	}
+	halbtc8821a1ant_set_sw_penalty_tx_rate_adaptive(btcoexist,
+			coex_dm->cur_low_penalty_ra);
+
+	coex_dm->pre_low_penalty_ra = coex_dm->cur_low_penalty_ra;
+}
+
+void halbtc8821a1ant_sw_mechanism(IN struct btc_coexist *btcoexist,
+				  IN boolean low_penalty_ra)
+{
+	halbtc8821a1ant_low_penalty_ra(btcoexist, NORMAL_EXEC, low_penalty_ra);
+}
+
+void halbtc8821a1ant_set_coex_table(IN struct btc_coexist *btcoexist,
+	    IN u32 val0x6c0, IN u32 val0x6c4, IN u32 val0x6c8, IN u8 val0x6cc)
+{
+	btcoexist->btc_write_4byte(btcoexist, 0x6c0, val0x6c0);
+
+	btcoexist->btc_write_4byte(btcoexist, 0x6c4, val0x6c4);
+
+	btcoexist->btc_write_4byte(btcoexist, 0x6c8, val0x6c8);
+
+	btcoexist->btc_write_1byte(btcoexist, 0x6cc, val0x6cc);
+}
+
+void halbtc8821a1ant_coex_table(IN struct btc_coexist *btcoexist,
+			IN boolean force_exec, IN u32 val0x6c0, IN u32 val0x6c4,
+				IN u32 val0x6c8, IN u8 val0x6cc)
+{
+	coex_dm->cur_val0x6c0 = val0x6c0;
+	coex_dm->cur_val0x6c4 = val0x6c4;
+	coex_dm->cur_val0x6c8 = val0x6c8;
+	coex_dm->cur_val0x6cc = val0x6cc;
+
+	if (!force_exec) {
+		if ((coex_dm->pre_val0x6c0 == coex_dm->cur_val0x6c0) &&
+		    (coex_dm->pre_val0x6c4 == coex_dm->cur_val0x6c4) &&
+		    (coex_dm->pre_val0x6c8 == coex_dm->cur_val0x6c8) &&
+		    (coex_dm->pre_val0x6cc == coex_dm->cur_val0x6cc))
+			return;
+	}
+	halbtc8821a1ant_set_coex_table(btcoexist, val0x6c0, val0x6c4, val0x6c8,
+				       val0x6cc);
+
+	coex_dm->pre_val0x6c0 = coex_dm->cur_val0x6c0;
+	coex_dm->pre_val0x6c4 = coex_dm->cur_val0x6c4;
+	coex_dm->pre_val0x6c8 = coex_dm->cur_val0x6c8;
+	coex_dm->pre_val0x6cc = coex_dm->cur_val0x6cc;
+}
+
+void halbtc8821a1ant_coex_table_with_type(IN struct btc_coexist *btcoexist,
+		IN boolean force_exec, IN u8 type)
+{
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+		    "[BTCoex], ********** CoexTable(%d) **********\n", type);
+	BTC_TRACE(trace_buf);
+
+	switch (type) {
+	case 0:
+		halbtc8821a1ant_coex_table(btcoexist, force_exec,
+				   0x55555555, 0x55555555, 0xffffff, 0x3);
+		break;
+	case 1:
+		halbtc8821a1ant_coex_table(btcoexist, force_exec,
+				   0x55555555, 0x5a5a5a5a, 0xffffff, 0x3);
+		break;
+	case 2:
+		halbtc8821a1ant_coex_table(btcoexist, force_exec,
+				   0x5a5a5a5a, 0x5a5a5a5a, 0xffffff, 0x3);
+		break;
+	case 3:
+		halbtc8821a1ant_coex_table(btcoexist, force_exec,
+				   0x5a5a5a5a, 0xaaaaaaaa, 0xffffff, 0x3);
+		break;
+	case 4:
+		halbtc8821a1ant_coex_table(btcoexist, force_exec,
+				   0x55555555, 0x5a5a5a5a, 0xffffff, 0x3);
+		break;
+	case 5:
+		halbtc8821a1ant_coex_table(btcoexist, force_exec,
+				   0x5a5a5a5a, 0xaaaa5a5a, 0xffffff, 0x3);
+		break;
+	case 6:
+		halbtc8821a1ant_coex_table(btcoexist, force_exec,
+				   0x55555555, 0xaaaa5a5a, 0xffffff, 0x3);
+		break;
+	case 7:
+		halbtc8821a1ant_coex_table(btcoexist, force_exec,
+				   0xaaaaaaaa, 0xaaaaaaaa, 0xffffff, 0x3);
+		break;
+	default:
+		break;
+	}
+}
+
+void halbtc8821a1ant_set_fw_ignore_wlan_act(IN struct btc_coexist *btcoexist,
+		IN boolean enable)
+{
+	u8			h2c_parameter[1] = {0};
+
+	if (enable)
+		h2c_parameter[0] |= BIT(0);		/* function enable */
+
+	btcoexist->btc_fill_h2c(btcoexist, 0x63, 1, h2c_parameter);
+}
+
+void halbtc8821a1ant_ignore_wlan_act(IN struct btc_coexist *btcoexist,
+				     IN boolean force_exec, IN boolean enable)
+{
+	coex_dm->cur_ignore_wlan_act = enable;
+
+	if (!force_exec) {
+		if (coex_dm->pre_ignore_wlan_act ==
+		    coex_dm->cur_ignore_wlan_act)
+			return;
+	}
+	halbtc8821a1ant_set_fw_ignore_wlan_act(btcoexist, enable);
+
+	coex_dm->pre_ignore_wlan_act = coex_dm->cur_ignore_wlan_act;
+}
+
+void halbtc8821a1ant_set_lps_rpwm(IN struct btc_coexist *btcoexist,
+				  IN u8 lps_val, IN u8 rpwm_val)
+{
+	u8	lps = lps_val;
+	u8	rpwm = rpwm_val;
+
+	btcoexist->btc_set(btcoexist, BTC_SET_U1_LPS_VAL, &lps);
+	btcoexist->btc_set(btcoexist, BTC_SET_U1_RPWM_VAL, &rpwm);
+}
+
+void halbtc8821a1ant_lps_rpwm(IN struct btc_coexist *btcoexist,
+		      IN boolean force_exec, IN u8 lps_val, IN u8 rpwm_val)
+{
+	coex_dm->cur_lps = lps_val;
+	coex_dm->cur_rpwm = rpwm_val;
+
+	if (!force_exec) {
+		if ((coex_dm->pre_lps == coex_dm->cur_lps) &&
+		    (coex_dm->pre_rpwm == coex_dm->cur_rpwm))
+			return;
+	}
+	halbtc8821a1ant_set_lps_rpwm(btcoexist, lps_val, rpwm_val);
+
+	coex_dm->pre_lps = coex_dm->cur_lps;
+	coex_dm->pre_rpwm = coex_dm->cur_rpwm;
+}
+
+void halbtc8821a1ant_set_ant_path(IN struct btc_coexist *btcoexist,
+	  IN u8 ant_pos_type, IN boolean init_hwcfg, IN boolean wifi_off)
+{
+	struct  btc_board_info *board_info = &btcoexist->board_info;
+	u32			u32tmp = 0;
+	u8			h2c_parameter[2] = {0};
+
+	if (init_hwcfg) {
+		/* 0x4c[23]=0, 0x4c[24]=1  Antenna control by WL/BT */
+		u32tmp = btcoexist->btc_read_4byte(btcoexist, 0x4c);
+		u32tmp &= ~BIT(23);
+		u32tmp |= BIT(24);
+		btcoexist->btc_write_4byte(btcoexist, 0x4c, u32tmp);
+
+		/* 0x765 = 0x18 */
+		btcoexist->btc_write_1byte_bitmask(btcoexist, 0x765, 0x18, 0x3);
+
+		if (board_info->btdm_ant_pos == BTC_ANTENNA_AT_MAIN_PORT) {
+			/* tell firmware "antenna inverse"  ==> WRONG firmware antenna control code.==>need fw to fix */
+			h2c_parameter[0] = 1;
+			h2c_parameter[1] = 1;
+			btcoexist->btc_fill_h2c(btcoexist, 0x65, 2,
+						h2c_parameter);
+
+			/* btcoexist->btc_write_1byte_bitmask(btcoexist, 0x64, 0x1, 0x1); */ /*Main Ant to  BT for IPS case 0x4c[23]=1 */
+		} else {
+			/* tell firmware "no antenna inverse" ==> WRONG firmware antenna control code.==>need fw to fix */
+			h2c_parameter[0] = 0;
+			h2c_parameter[1] = 1;
+			btcoexist->btc_fill_h2c(btcoexist, 0x65, 2,
+						h2c_parameter);
+
+			/* btcoexist->btc_write_1byte_bitmask(btcoexist, 0x64, 0x1, 0x0); */ /*Aux Ant to  BT for IPS case 0x4c[23]=1 */
+		}
+	} else if (wifi_off) {
+		/* 0x4c[24:23]=00, Set Antenna control by BT_RFE_CTRL	BT Vendor 0xac=0xf002 */
+		u32tmp = btcoexist->btc_read_4byte(btcoexist, 0x4c);
+		u32tmp &= ~BIT(23);
+		u32tmp &= ~BIT(24);
+		btcoexist->btc_write_4byte(btcoexist, 0x4c, u32tmp);
+
+		/* 0x765 = 0x18 */
+		btcoexist->btc_write_1byte_bitmask(btcoexist, 0x765, 0x18, 0x3);
+	} else {
+		/* 0x765 = 0x0 */
+		btcoexist->btc_write_1byte_bitmask(btcoexist, 0x765, 0x18, 0x0);
+	}
+
+	/* ext switch setting */
+	switch (ant_pos_type) {
+	case BTC_ANT_PATH_WIFI:
+		btcoexist->btc_write_1byte(btcoexist, 0xcb4, 0x77);
+		if (board_info->btdm_ant_pos ==
+		    BTC_ANTENNA_AT_MAIN_PORT)
+			btcoexist->btc_write_1byte_bitmask(btcoexist,
+							   0xcb7, 0x30, 0x1);
+		else
+			btcoexist->btc_write_1byte_bitmask(btcoexist,
+							   0xcb7, 0x30, 0x2);
+		break;
+	case BTC_ANT_PATH_BT:
+		btcoexist->btc_write_1byte(btcoexist, 0xcb4, 0x77);
+		if (board_info->btdm_ant_pos ==
+		    BTC_ANTENNA_AT_MAIN_PORT)
+			btcoexist->btc_write_1byte_bitmask(btcoexist,
+							   0xcb7, 0x30, 0x2);
+		else
+			btcoexist->btc_write_1byte_bitmask(btcoexist,
+							   0xcb7, 0x30, 0x1);
+		break;
+	default:
+	case BTC_ANT_PATH_PTA:
+		btcoexist->btc_write_1byte(btcoexist, 0xcb4, 0x66);
+		if (board_info->btdm_ant_pos ==
+		    BTC_ANTENNA_AT_MAIN_PORT)
+			btcoexist->btc_write_1byte_bitmask(btcoexist,
+							   0xcb7, 0x30, 0x1);
+		else
+			btcoexist->btc_write_1byte_bitmask(btcoexist,
+							   0xcb7, 0x30, 0x2);
+		break;
+	}
+}
+
+
+void halbtc8821a1ant_ps_tdma_check_for_power_save_state(
+	IN struct btc_coexist *btcoexist, IN boolean new_ps_state)
+{
+	u8	lps_mode = 0x0;
+	u8	h2c_parameter[5] = {0x8, 0, 0, 0, 0};
+
+	btcoexist->btc_get(btcoexist, BTC_GET_U1_LPS_MODE, &lps_mode);
+
+	if (lps_mode) {	/* already under LPS state */
+		if (new_ps_state) {
+			/* keep state under LPS, do nothing. */
+		} else {
+			/* will leave LPS state, turn off psTdma first */
+/* halbtc8821a1ant_ps_tdma(btcoexist, NORMAL_EXEC, false,8); */
+			btcoexist->btc_fill_h2c(btcoexist, 0x60, 5,
+				h2c_parameter);
+		}
+	} else {					/* NO PS state */
+		if (new_ps_state) {
+			/* will enter LPS state, turn off psTdma first */
+/* halbtc8821a1ant_ps_tdma(btcoexist, NORMAL_EXEC, false,8); */
+			btcoexist->btc_fill_h2c(btcoexist, 0x60, 5,
+				h2c_parameter);
+		} else {
+			/* keep state under NO PS state, do nothing. */
+		}
+	}
+}
+
+void halbtc8821a1ant_power_save_state(IN struct btc_coexist *btcoexist,
+			      IN u8 ps_type, IN u8 lps_val, IN u8 rpwm_val)
+{
+	boolean		low_pwr_disable = false;
+
+	switch (ps_type) {
+	case BTC_PS_WIFI_NATIVE:
+		/* recover to original 32k low power setting */
+		low_pwr_disable = false;
+		btcoexist->btc_set(btcoexist,
+				   BTC_SET_ACT_DISABLE_LOW_POWER,
+				   &low_pwr_disable);
+		btcoexist->btc_set(btcoexist, BTC_SET_ACT_NORMAL_LPS,
+				   NULL);
+		break;
+	case BTC_PS_LPS_ON:
+		halbtc8821a1ant_ps_tdma_check_for_power_save_state(
+			btcoexist, true);
+		halbtc8821a1ant_lps_rpwm(btcoexist, NORMAL_EXEC,
+					 lps_val, rpwm_val);
+		/* when coex force to enter LPS, do not enter 32k low power. */
+		low_pwr_disable = true;
+		btcoexist->btc_set(btcoexist,
+				   BTC_SET_ACT_DISABLE_LOW_POWER,
+				   &low_pwr_disable);
+		/* power save must executed before psTdma. */
+		btcoexist->btc_set(btcoexist, BTC_SET_ACT_ENTER_LPS,
+				   NULL);
+		break;
+	case BTC_PS_LPS_OFF:
+		halbtc8821a1ant_ps_tdma_check_for_power_save_state(
+			btcoexist, false);
+		btcoexist->btc_set(btcoexist, BTC_SET_ACT_LEAVE_LPS,
+				   NULL);
+		break;
+	default:
+		break;
+	}
+}
+
+void halbtc8821a1ant_set_fw_pstdma(IN struct btc_coexist *btcoexist,
+	   IN u8 byte1, IN u8 byte2, IN u8 byte3, IN u8 byte4, IN u8 byte5)
+{
+	u8			h2c_parameter[5] = {0};
+	u8			real_byte1 = byte1, real_byte5 = byte5;
+	boolean			ap_enable = false;
+
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_AP_MODE_ENABLE,
+			   &ap_enable);
+
+	if (ap_enable) {
+		if (byte1 & BIT(4) && !(byte1 & BIT(5))) {
+			real_byte1 &= ~BIT(4);
+			real_byte1 |= BIT(5);
+
+			real_byte5 |= BIT(5);
+			real_byte5 &= ~BIT(6);
+
+			halbtc8821a1ant_power_save_state(btcoexist,
+				BTC_PS_WIFI_NATIVE, 0x0, 0x0);
+		}
+} else if (byte1 & BIT(4) && !(byte1 & BIT(5))) {
+halbtc8821a1ant_power_save_state(btcoexist, BTC_PS_LPS_ON, 0x50, 0x4);
+
+	} else  {
+			halbtc8821a1ant_power_save_state(btcoexist,
+				BTC_PS_WIFI_NATIVE, 0x0, 0x0);
+	}
+
+	h2c_parameter[0] = real_byte1;
+	h2c_parameter[1] = byte2;
+	h2c_parameter[2] = byte3;
+	h2c_parameter[3] = byte4;
+	h2c_parameter[4] = real_byte5;
+
+	coex_dm->ps_tdma_para[0] = real_byte1;
+	coex_dm->ps_tdma_para[1] = byte2;
+	coex_dm->ps_tdma_para[2] = byte3;
+	coex_dm->ps_tdma_para[3] = byte4;
+	coex_dm->ps_tdma_para[4] = real_byte5;
+
+	btcoexist->btc_fill_h2c(btcoexist, 0x60, 5, h2c_parameter);
+}
+
+void halbtc8821a1ant_ps_tdma(IN struct btc_coexist *btcoexist,
+		     IN boolean force_exec, IN boolean turn_on, IN u8 type)
+{
+	u8			rssi_adjust_val = 0;
+	/* u32			fw_ver=0; */
+
+	coex_dm->cur_ps_tdma_on = turn_on;
+	coex_dm->cur_ps_tdma = type;
+
+	if (coex_dm->cur_ps_tdma_on) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], ********** TDMA(on, %d) **********\n",
+			    coex_dm->cur_ps_tdma);
+		BTC_TRACE(trace_buf);
+	} else {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], ********** TDMA(off, %d) **********\n",
+			    coex_dm->cur_ps_tdma);
+		BTC_TRACE(trace_buf);
+	}
+
+	if (!force_exec) {
+		if ((coex_dm->pre_ps_tdma_on == coex_dm->cur_ps_tdma_on) &&
+		    (coex_dm->pre_ps_tdma == coex_dm->cur_ps_tdma))
+			return;
+	}
+	if (turn_on) {
+		switch (type) {
+		default:
+			halbtc8821a1ant_set_fw_pstdma(btcoexist, 0x51,
+						      0x1a, 0x1a, 0x0, 0x50);
+			break;
+		case 1:
+			halbtc8821a1ant_set_fw_pstdma(btcoexist, 0x51,
+						      0x3a, 0x03, 0x10, 0x50);
+			rssi_adjust_val = 11;
+			break;
+		case 2:
+			halbtc8821a1ant_set_fw_pstdma(btcoexist, 0x51,
+						      0x2b, 0x03, 0x10, 0x50);
+			rssi_adjust_val = 14;
+			break;
+		case 3:
+			halbtc8821a1ant_set_fw_pstdma(btcoexist, 0x51,
+						      0x1d, 0x1d, 0x0, 0x52);
+			break;
+		case 4:
+			halbtc8821a1ant_set_fw_pstdma(btcoexist, 0x93,
+						      0x15, 0x3, 0x14, 0x0);
+			rssi_adjust_val = 17;
+			break;
+		case 5:
+			halbtc8821a1ant_set_fw_pstdma(btcoexist, 0x61,
+						      0x15, 0x3, 0x11, 0x10);
+			break;
+		case 6:
+			halbtc8821a1ant_set_fw_pstdma(btcoexist, 0x61,
+						      0x20, 0x3, 0x11, 0x13);
+			break;
+		case 7:
+			halbtc8821a1ant_set_fw_pstdma(btcoexist, 0x13,
+						      0xc, 0x5, 0x0, 0x0);
+			break;
+		case 8:
+			halbtc8821a1ant_set_fw_pstdma(btcoexist, 0x93,
+						      0x25, 0x3, 0x10, 0x0);
+			break;
+		case 9:
+			halbtc8821a1ant_set_fw_pstdma(btcoexist, 0x51,
+						      0x21, 0x3, 0x10, 0x50);
+			rssi_adjust_val = 18;
+			break;
+		case 10:
+			halbtc8821a1ant_set_fw_pstdma(btcoexist, 0x13,
+						      0xa, 0xa, 0x0, 0x40);
+			break;
+		case 11:
+			halbtc8821a1ant_set_fw_pstdma(btcoexist, 0x51,
+						      0x15, 0x03, 0x10, 0x50);
+			rssi_adjust_val = 20;
+			break;
+		case 12:
+			halbtc8821a1ant_set_fw_pstdma(btcoexist, 0x51,
+						      0x0a, 0x0a, 0x0, 0x50);
+			break;
+		case 13:
+			if (coex_sta->scan_ap_num <= 5)
+				halbtc8821a1ant_set_fw_pstdma(btcoexist, 0x51,
+						      0x40, 0x3, 0x10, 0x50);
+			else
+				halbtc8821a1ant_set_fw_pstdma(btcoexist, 0x51,
+						      0x12, 0x12, 0x0, 0x50);
+			break;
+		case 14:
+			if (coex_sta->scan_ap_num <= 5)
+				halbtc8821a1ant_set_fw_pstdma(btcoexist, 0x51,
+						      0x30, 0x3, 0x10, 0x50);
+			else
+				halbtc8821a1ant_set_fw_pstdma(btcoexist, 0x51,
+						      0x1e, 0x3, 0x10, 0x14);
+			break;
+		case 15:
+			halbtc8821a1ant_set_fw_pstdma(btcoexist, 0x13,
+						      0xa, 0x3, 0x8, 0x0);
+			break;
+		case 16:
+			halbtc8821a1ant_set_fw_pstdma(btcoexist, 0x93,
+						      0x15, 0x3, 0x10, 0x0);
+			rssi_adjust_val = 18;
+			break;
+		case 18:
+			halbtc8821a1ant_set_fw_pstdma(btcoexist, 0x93,
+						      0x25, 0x3, 0x10, 0x0);
+			rssi_adjust_val = 14;
+			break;
+		case 20:
+			halbtc8821a1ant_set_fw_pstdma(btcoexist, 0x61,
+						      0x35, 0x03, 0x11, 0x10);
+			break;
+		case 21:
+			halbtc8821a1ant_set_fw_pstdma(btcoexist, 0x61,
+						      0x25, 0x03, 0x11, 0x11);
+			break;
+		case 22:
+			halbtc8821a1ant_set_fw_pstdma(btcoexist, 0x61,
+						      0x25, 0x03, 0x11, 0x10);
+			break;
+		case 23:
+			halbtc8821a1ant_set_fw_pstdma(btcoexist, 0xe3,
+						      0x25, 0x3, 0x31, 0x18);
+			rssi_adjust_val = 22;
+			break;
+		case 24:
+			halbtc8821a1ant_set_fw_pstdma(btcoexist, 0xe3,
+						      0x15, 0x3, 0x31, 0x18);
+			rssi_adjust_val = 22;
+			break;
+		case 25:
+			halbtc8821a1ant_set_fw_pstdma(btcoexist, 0xe3,
+						      0xa, 0x3, 0x31, 0x18);
+			rssi_adjust_val = 22;
+			break;
+		case 26:
+			halbtc8821a1ant_set_fw_pstdma(btcoexist, 0xe3,
+						      0xa, 0x3, 0x31, 0x18);
+			rssi_adjust_val = 22;
+			break;
+		case 27:
+			halbtc8821a1ant_set_fw_pstdma(btcoexist, 0xe3,
+						      0x25, 0x3, 0x31, 0x98);
+			rssi_adjust_val = 22;
+			break;
+		case 28:
+			halbtc8821a1ant_set_fw_pstdma(btcoexist, 0x69,
+						      0x25, 0x3, 0x31, 0x0);
+			break;
+		case 29:
+			halbtc8821a1ant_set_fw_pstdma(btcoexist, 0xab,
+						      0x1a, 0x1a, 0x1, 0x10);
+			break;
+		case 30:
+			halbtc8821a1ant_set_fw_pstdma(btcoexist, 0x51,
+						      0x30, 0x3, 0x10, 0x10);
+			break;
+		case 31:
+			halbtc8821a1ant_set_fw_pstdma(btcoexist, 0xd3,
+						      0x1a, 0x1a, 0, 0x58);
+			break;
+		case 32:
+			halbtc8821a1ant_set_fw_pstdma(btcoexist, 0x61,
+						      0x35, 0x3, 0x11, 0x11);
+			break;
+		case 33:
+			halbtc8821a1ant_set_fw_pstdma(btcoexist, 0xa3,
+						      0x25, 0x3, 0x30, 0x90);
+			break;
+		case 34:
+			halbtc8821a1ant_set_fw_pstdma(btcoexist, 0x53,
+						      0x1a, 0x1a, 0x0, 0x10);
+			break;
+		case 35:
+			halbtc8821a1ant_set_fw_pstdma(btcoexist, 0x63,
+						      0x1a, 0x1a, 0x0, 0x10);
+			break;
+		case 36:
+			halbtc8821a1ant_set_fw_pstdma(btcoexist, 0xd3,
+						      0x12, 0x3, 0x14, 0x50);
+			break;
+		case 40: /* SoftAP only with no sta associated,BT disable ,TDMA mode for power saving */
+			/* here softap mode screen off will cost 70-80mA for phone */
+			halbtc8821a1ant_set_fw_pstdma(btcoexist, 0x23,
+						      0x18, 0x00, 0x10, 0x24);
+			break;
+		case 41:
+			halbtc8821a1ant_set_fw_pstdma(btcoexist, 0x51,
+						      0x15, 0x3, 0x11, 0x11);
+			break;
+		case 42:
+			halbtc8821a1ant_set_fw_pstdma(btcoexist, 0x51,
+						      0x20, 0x3, 0x11, 0x11);
+			break;
+		case 43:
+			halbtc8821a1ant_set_fw_pstdma(btcoexist, 0x51,
+						      0x30, 0x3, 0x10, 0x11);
+			break;
+		}
+	} else {
+		/* disable PS tdma */
+		switch (type) {
+		case 8: /* PTA Control */
+			halbtc8821a1ant_set_fw_pstdma(btcoexist, 0x8,
+						      0x0, 0x0, 0x0, 0x0);
+			halbtc8821a1ant_set_ant_path(btcoexist,
+					     BTC_ANT_PATH_PTA, false, false);
+			break;
+		case 0:
+		default:  /* Software control, Antenna at BT side */
+			halbtc8821a1ant_set_fw_pstdma(btcoexist, 0x0,
+						      0x0, 0x0, 0x0, 0x0);
+			halbtc8821a1ant_set_ant_path(btcoexist,
+					     BTC_ANT_PATH_BT, false, false);
+			break;
+		case 9:   /* Software control, Antenna at WiFi side */
+			halbtc8821a1ant_set_fw_pstdma(btcoexist, 0x0,
+						      0x0, 0x0, 0x0, 0x0);
+			halbtc8821a1ant_set_ant_path(btcoexist,
+					     BTC_ANT_PATH_WIFI, false, false);
+			break;
+		case 10:	/* under 5G */
+			halbtc8821a1ant_set_fw_pstdma(btcoexist, 0x0,
+						      0x0, 0x0, 0x8, 0x0);
+			halbtc8821a1ant_set_ant_path(btcoexist,
+					     BTC_ANT_PATH_BT, false, false);
+			break;
+		}
+	}
+	rssi_adjust_val = 0;
+	btcoexist->btc_set(btcoexist,
+		BTC_SET_U1_RSSI_ADJ_VAL_FOR_1ANT_COEX_TYPE, &rssi_adjust_val);
+
+	/* update pre state */
+	coex_dm->pre_ps_tdma_on = coex_dm->cur_ps_tdma_on;
+	coex_dm->pre_ps_tdma = coex_dm->cur_ps_tdma;
+}
+
+void halbtc8821a1ant_coex_all_off(IN struct btc_coexist *btcoexist)
+{
+	/* sw all off */
+	halbtc8821a1ant_sw_mechanism(btcoexist, false);
+
+	/* hw all off */
+	halbtc8821a1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0);
+}
+
+boolean halbtc8821a1ant_is_common_action(IN struct btc_coexist *btcoexist)
+{
+	boolean			common = false, wifi_connected = false, wifi_busy = false;
+
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED,
+			   &wifi_connected);
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy);
+
+	if (!wifi_connected &&
+	    BT_8821A_1ANT_BT_STATUS_NON_CONNECTED_IDLE ==
+	    coex_dm->bt_status) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			"[BTCoex], Wifi non connected-idle + BT non connected-idle!!\n");
+		BTC_TRACE(trace_buf);
+		halbtc8821a1ant_sw_mechanism(btcoexist, false);
+
+		common = true;
+	} else if (wifi_connected &&
+		   (BT_8821A_1ANT_BT_STATUS_NON_CONNECTED_IDLE ==
+		    coex_dm->bt_status)) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			"[BTCoex], Wifi connected + BT non connected-idle!!\n");
+		BTC_TRACE(trace_buf);
+		halbtc8821a1ant_sw_mechanism(btcoexist, false);
+
+		common = true;
+	} else if (!wifi_connected &&
+		   (BT_8821A_1ANT_BT_STATUS_CONNECTED_IDLE ==
+		    coex_dm->bt_status)) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			"[BTCoex], Wifi non connected-idle + BT connected-idle!!\n");
+		BTC_TRACE(trace_buf);
+		halbtc8821a1ant_sw_mechanism(btcoexist, false);
+
+		common = true;
+	} else if (wifi_connected &&
+		   (BT_8821A_1ANT_BT_STATUS_CONNECTED_IDLE ==
+		    coex_dm->bt_status)) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], Wifi connected + BT connected-idle!!\n");
+		BTC_TRACE(trace_buf);
+		halbtc8821a1ant_sw_mechanism(btcoexist, false);
+
+		common = true;
+	} else if (!wifi_connected &&
+		   (BT_8821A_1ANT_BT_STATUS_CONNECTED_IDLE !=
+		    coex_dm->bt_status)) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], Wifi non connected-idle + BT Busy!!\n");
+		BTC_TRACE(trace_buf);
+		halbtc8821a1ant_sw_mechanism(btcoexist, false);
+
+		common = true;
+	} else {
+		if (wifi_busy) {
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				"[BTCoex], Wifi Connected-Busy + BT Busy!!\n");
+			BTC_TRACE(trace_buf);
+		} else {
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				"[BTCoex], Wifi Connected-Idle + BT Busy!!\n");
+			BTC_TRACE(trace_buf);
+		}
+
+		common = false;
+	}
+
+	return common;
+}
+
+/* *********************************************
+ *
+ *	Software Coex Mechanism start
+ *
+ * ********************************************* */
+
+void halbtc8821a1ant_action_bt_whck_test(IN struct btc_coexist *btcoexist)
+{
+
+	halbtc8821a1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 8);
+	/* halbtc8821a1ant_set_ant_path(btcoexist, BTC_ANT_PATH_PTA, NORMAL_EXEC, false, false); */
+	halbtc8821a1ant_set_ant_path(btcoexist, BTC_ANT_PATH_PTA, false, false);
+	halbtc8821a1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0);
+}
+/* SCO only or SCO+PAN(HS) */
+void halbtc8821a1ant_action_sco(IN struct btc_coexist *btcoexist)
+{
+	halbtc8821a1ant_sw_mechanism(btcoexist, true);
+}
+
+void halbtc8821a1ant_action_hid(IN struct btc_coexist *btcoexist)
+{
+	halbtc8821a1ant_sw_mechanism(btcoexist, true);
+}
+
+/* A2DP only / PAN(EDR) only/ A2DP+PAN(HS) */
+void halbtc8821a1ant_action_a2dp(IN struct btc_coexist *btcoexist)
+{
+	halbtc8821a1ant_sw_mechanism(btcoexist, false);
+}
+
+void halbtc8821a1ant_action_a2dp_pan_hs(IN struct btc_coexist *btcoexist)
+{
+	halbtc8821a1ant_sw_mechanism(btcoexist, false);
+}
+
+void halbtc8821a1ant_action_pan_edr(IN struct btc_coexist *btcoexist)
+{
+	halbtc8821a1ant_sw_mechanism(btcoexist, false);
+}
+
+/* PAN(HS) only */
+void halbtc8821a1ant_action_pan_hs(IN struct btc_coexist *btcoexist)
+{
+	halbtc8821a1ant_sw_mechanism(btcoexist, false);
+}
+
+/* PAN(EDR)+A2DP */
+void halbtc8821a1ant_action_pan_edr_a2dp(IN struct btc_coexist *btcoexist)
+{
+	halbtc8821a1ant_sw_mechanism(btcoexist, false);
+}
+
+void halbtc8821a1ant_action_pan_edr_hid(IN struct btc_coexist *btcoexist)
+{
+	halbtc8821a1ant_sw_mechanism(btcoexist, true);
+}
+
+/* HID+A2DP+PAN(EDR) */
+void halbtc8821a1ant_action_hid_a2dp_pan_edr(IN struct btc_coexist *btcoexist)
+{
+	halbtc8821a1ant_sw_mechanism(btcoexist, true);
+}
+
+void halbtc8821a1ant_action_hid_a2dp(IN struct btc_coexist *btcoexist)
+{
+	halbtc8821a1ant_sw_mechanism(btcoexist, true);
+}
+
+/* *********************************************
+ *
+ *	Non-Software Coex Mechanism start
+ *
+ * ********************************************* */
+void halbtc8821a1ant_action_hs(IN struct btc_coexist *btcoexist)
+{
+	halbtc8821a1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 5);
+	halbtc8821a1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 2);
+}
+
+void halbtc8821a1ant_action_bt_inquiry(IN struct btc_coexist *btcoexist)
+{
+	struct  btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
+	boolean			wifi_connected = false, ap_enable = false, wifi_busy = false,
+				bt_busy = false;
+
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_AP_MODE_ENABLE,
+			   &ap_enable);
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED,
+			   &wifi_connected);
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy);
+	btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_TRAFFIC_BUSY, &bt_busy);
+
+	if ((!wifi_connected) && (!coex_sta->wifi_is_high_pri_task)) {
+		halbtc8821a1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 8);
+
+		halbtc8821a1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0);
+	}
+
+	/* sy modify	 */
+	else if ((bt_link_info->sco_exist) || (bt_link_info->hid_exist) ||
+		 (bt_link_info->a2dp_exist)) {
+		/* SCO/HID/A2DP  busy */
+
+		halbtc8821a1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 32);
+
+		halbtc8821a1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4);
+	}
+
+	/* sy modify */
+
+	else if ((bt_link_info->a2dp_exist) &&
+		 (bt_link_info->hid_exist)) {
+		/* A2DP+HID	busy */
+
+		halbtc8821a1ant_ps_tdma(btcoexist, NORMAL_EXEC, true,
+					14);
+
+		halbtc8821a1ant_coex_table_with_type(btcoexist,
+						     NORMAL_EXEC, 1);
+	}
+
+
+	else if ((bt_link_info->pan_exist) || (wifi_busy)) {
+		halbtc8821a1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 20);
+
+		halbtc8821a1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4);
+	} else {
+		halbtc8821a1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 8);
+
+		halbtc8821a1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 7);
+	}
+}
+
+void halbtc8821a1ant_action_bt_sco_hid_only_busy(IN struct btc_coexist
+		*btcoexist, IN u8 wifi_status)
+{
+	struct  btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
+	boolean	wifi_connected = false;
+
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED,
+			   &wifi_connected);
+
+	/* tdma and coex table */
+
+	if (bt_link_info->sco_exist) {
+		halbtc8821a1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 41);
+		halbtc8821a1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 2);
+	} else { /* HID */
+		halbtc8821a1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 42);
+		halbtc8821a1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 2);
+	}
+}
+
+void halbtc8821a1ant_coex_under_5g(IN struct btc_coexist *btcoexist)
+{
+
+	halbtc8821a1ant_ignore_wlan_act(btcoexist, NORMAL_EXEC, true);
+
+	halbtc8821a1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 10);
+
+	halbtc8821a1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0);
+
+	halbtc8821a1ant_limited_tx(btcoexist, NORMAL_EXEC, 0, 0, 0, 0);
+
+	halbtc8821a1ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, 5);
+}
+
+void halbtc8821a1ant_action_wifi_only(IN struct btc_coexist *btcoexist)
+{
+	halbtc8821a1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0);
+	halbtc8821a1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 9);
+}
+
+void halbtc8821a1ant_monitor_bt_enable_disable(IN struct btc_coexist *btcoexist)
+{
+	static u32		bt_disable_cnt = 0;
+	boolean			bt_active = true, bt_disabled = false;
+
+	/* This function check if bt is disabled */
+
+	if (coex_sta->high_priority_tx == 0 &&
+	    coex_sta->high_priority_rx == 0 &&
+	    coex_sta->low_priority_tx == 0 &&
+	    coex_sta->low_priority_rx == 0)
+		bt_active = false;
+	if (coex_sta->high_priority_tx == 0xffff &&
+	    coex_sta->high_priority_rx == 0xffff &&
+	    coex_sta->low_priority_tx == 0xffff &&
+	    coex_sta->low_priority_rx == 0xffff)
+		bt_active = false;
+	if (bt_active) {
+		bt_disable_cnt = 0;
+		bt_disabled = false;
+		btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_DISABLE,
+				   &bt_disabled);
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], BT is enabled !!\n");
+		BTC_TRACE(trace_buf);
+	} else {
+		bt_disable_cnt++;
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], bt all counters=0, %d times!!\n",
+			    bt_disable_cnt);
+		BTC_TRACE(trace_buf);
+		if (bt_disable_cnt >= 10) {
+			bt_disabled = true;
+			btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_DISABLE,
+					   &bt_disabled);
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				    "[BTCoex], BT is disabled !!\n");
+			BTC_TRACE(trace_buf);
+			halbtc8821a1ant_action_wifi_only(btcoexist);
+		}
+	}
+	if (coex_sta->bt_disabled != bt_disabled) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], BT is from %s to %s!!\n",
+			    (coex_sta->bt_disabled ? "disabled" : "enabled"),
+			    (bt_disabled ? "disabled" : "enabled"));
+		BTC_TRACE(trace_buf);
+		coex_sta->bt_disabled = bt_disabled;
+		if (!bt_disabled) {
+		} else {
+			btcoexist->btc_set(btcoexist, BTC_SET_ACT_LEAVE_LPS,
+					   NULL);
+			btcoexist->btc_set(btcoexist, BTC_SET_ACT_NORMAL_LPS,
+					   NULL);
+		}
+	}
+}
+
+void halbtc8821a1ant_action_wifi_multi_port(IN struct btc_coexist *btcoexist)
+{
+
+	halbtc8821a1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 8);
+	halbtc8821a1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 2);
+}
+
+
+void halbtc8821a1ant_action_wifi_connected_bt_acl_busy(IN struct btc_coexist
+		*btcoexist, IN u8 wifi_status)
+{
+	u8		bt_rssi_state;
+
+	struct  btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
+
+	bt_rssi_state = halbtc8821a1ant_bt_rssi_state(2, 28, 0);
+
+	if (bt_link_info->hid_only) { /* HID */
+		halbtc8821a1ant_action_bt_sco_hid_only_busy(btcoexist,
+				wifi_status);
+		coex_dm->auto_tdma_adjust = false;
+		return;
+	} else if (bt_link_info->a2dp_only) { /* A2DP		 */
+		if (BT_8821A_1ANT_WIFI_STATUS_CONNECTED_IDLE == wifi_status) {
+			/* halbtc8821a1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 8); */
+			/* halbtc8821a1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 2); */
+			halbtc8821a1ant_ps_tdma(btcoexist, NORMAL_EXEC, true,
+						32);
+			halbtc8821a1ant_coex_table_with_type(btcoexist,
+							     NORMAL_EXEC, 1);
+			coex_dm->auto_tdma_adjust = false;
+		} else if ((bt_rssi_state == BTC_RSSI_STATE_HIGH) ||
+			   (bt_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
+			/* halbtc8821a1ant_tdma_duration_adjust_for_acl(btcoexist, wifi_status); */
+			halbtc8821a1ant_ps_tdma(btcoexist, NORMAL_EXEC, true,
+						14);
+			halbtc8821a1ant_coex_table_with_type(btcoexist,
+							     NORMAL_EXEC, 1);
+		} else { /* for low BT RSSI */
+			halbtc8821a1ant_ps_tdma(btcoexist, NORMAL_EXEC, true,
+						14);
+			halbtc8821a1ant_coex_table_with_type(btcoexist,
+							     NORMAL_EXEC, 1);
+			coex_dm->auto_tdma_adjust = false;
+		}
+	} else if (bt_link_info->hid_exist &&
+		   bt_link_info->a2dp_exist) { /* HID+A2DP */
+		if ((bt_rssi_state == BTC_RSSI_STATE_HIGH) ||
+		    (bt_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
+			halbtc8821a1ant_ps_tdma(btcoexist, NORMAL_EXEC, true,
+						14);
+			coex_dm->auto_tdma_adjust = false;
+		} else { /* for low BT RSSI */
+			halbtc8821a1ant_ps_tdma(btcoexist, NORMAL_EXEC, true,
+						14);
+			coex_dm->auto_tdma_adjust = false;
+		}
+
+		halbtc8821a1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 1);
+	} else if ((bt_link_info->pan_only) || (bt_link_info->hid_exist &&
+		bt_link_info->pan_exist)) { /* PAN(OPP,FTP), HID+PAN(OPP,FTP)			 */
+		halbtc8821a1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 3);
+		halbtc8821a1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 6);
+		coex_dm->auto_tdma_adjust = false;
+	} else if (((bt_link_info->a2dp_exist) && (bt_link_info->pan_exist)) ||
+		   (bt_link_info->hid_exist && bt_link_info->a2dp_exist &&
+		bt_link_info->pan_exist)) { /* A2DP+PAN(OPP,FTP), HID+A2DP+PAN(OPP,FTP) */
+		halbtc8821a1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 43);
+		halbtc8821a1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 1);
+		coex_dm->auto_tdma_adjust = false;
+	} else {
+		halbtc8821a1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 11);
+		halbtc8821a1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 1);
+		coex_dm->auto_tdma_adjust = false;
+	}
+}
+
+void halbtc8821a1ant_action_wifi_not_connected(IN struct btc_coexist *btcoexist)
+{
+
+	/* tdma and coex table	 */
+	halbtc8821a1ant_ps_tdma(btcoexist, FORCE_EXEC, false, 8);
+	halbtc8821a1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0);
+}
+
+void halbtc8821a1ant_action_wifi_not_connected_scan(IN struct btc_coexist
+		*btcoexist)
+{
+	struct  btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
+
+
+	/* tdma and coex table */
+	if (BT_8821A_1ANT_BT_STATUS_ACL_BUSY == coex_dm->bt_status) {
+		if (bt_link_info->a2dp_exist) {
+			/* sy modify */
+			halbtc8821a1ant_ps_tdma(btcoexist, NORMAL_EXEC, true,
+						14);
+			halbtc8821a1ant_coex_table_with_type(btcoexist,
+							     NORMAL_EXEC, 1);
+		} else if (bt_link_info->a2dp_exist &&
+			   bt_link_info->pan_exist) {
+			halbtc8821a1ant_ps_tdma(btcoexist, NORMAL_EXEC, true,
+						22);
+			halbtc8821a1ant_coex_table_with_type(btcoexist,
+							     NORMAL_EXEC, 4);
+		} else {
+			halbtc8821a1ant_ps_tdma(btcoexist, NORMAL_EXEC, true,
+						20);
+			halbtc8821a1ant_coex_table_with_type(btcoexist,
+							     NORMAL_EXEC, 4);
+		}
+	} else if ((BT_8821A_1ANT_BT_STATUS_SCO_BUSY == coex_dm->bt_status) ||
+		   (BT_8821A_1ANT_BT_STATUS_ACL_SCO_BUSY ==
+		    coex_dm->bt_status)) {
+		halbtc8821a1ant_action_bt_sco_hid_only_busy(btcoexist,
+				BT_8821A_1ANT_WIFI_STATUS_CONNECTED_SCAN);
+	} else {
+		/* halbtc8821a1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 20); */
+		/* halbtc8821a1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 1); */
+
+		/* Bryant Add */
+		halbtc8821a1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 8);
+		halbtc8821a1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 2);
+	}
+}
+
+void halbtc8821a1ant_action_wifi_not_connected_asso_auth(
+	IN struct btc_coexist *btcoexist)
+{
+	struct  btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
+
+	/* tdma and coex table */
+	if ((bt_link_info->sco_exist)  || (bt_link_info->hid_exist)) {
+		/* sy modify */
+		halbtc8821a1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 14);
+		halbtc8821a1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 1);
+	} else if ((bt_link_info->a2dp_exist)  || (bt_link_info->pan_exist)) {
+		halbtc8821a1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 20);
+		halbtc8821a1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4);
+	} else {
+		halbtc8821a1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 8);
+		halbtc8821a1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 2);
+	}
+}
+
+void halbtc8821a1ant_action_wifi_connected_scan(IN struct btc_coexist
+		*btcoexist)
+{
+	struct  btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
+
+	/* tdma and coex table */
+	if (BT_8821A_1ANT_BT_STATUS_ACL_BUSY == coex_dm->bt_status) {
+		if (bt_link_info->a2dp_exist) {
+			/* sy modify */
+			halbtc8821a1ant_ps_tdma(btcoexist, NORMAL_EXEC, true,
+						14);
+			halbtc8821a1ant_coex_table_with_type(btcoexist,
+							     NORMAL_EXEC, 1);
+		} else if (bt_link_info->a2dp_exist &&
+			   bt_link_info->pan_exist) {
+			halbtc8821a1ant_ps_tdma(btcoexist, NORMAL_EXEC, true,
+						22);
+			halbtc8821a1ant_coex_table_with_type(btcoexist,
+							     NORMAL_EXEC, 4);
+		} else {
+			halbtc8821a1ant_ps_tdma(btcoexist, NORMAL_EXEC, true,
+						20);
+			halbtc8821a1ant_coex_table_with_type(btcoexist,
+							     NORMAL_EXEC, 4);
+		}
+	} else if ((BT_8821A_1ANT_BT_STATUS_SCO_BUSY == coex_dm->bt_status) ||
+		   (BT_8821A_1ANT_BT_STATUS_ACL_SCO_BUSY ==
+		    coex_dm->bt_status)) {
+		halbtc8821a1ant_action_bt_sco_hid_only_busy(btcoexist,
+				BT_8821A_1ANT_WIFI_STATUS_CONNECTED_SCAN);
+	} else {
+		/* halbtc8821a1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 20); */
+		/* halbtc8821a1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 1); */
+
+		/* Bryant Add */
+		halbtc8821a1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 8);
+		halbtc8821a1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 2);
+	}
+}
+
+void halbtc8821a1ant_action_wifi_connected_specific_packet(
+	IN struct btc_coexist *btcoexist)
+{
+	struct  btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
+
+	/* tdma and coex table */
+	/* sy modify */
+	if ((bt_link_info->sco_exist) || (bt_link_info->hid_exist) ||
+	    (bt_link_info->a2dp_exist)) {
+		halbtc8821a1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 32);
+		halbtc8821a1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4);
+	}
+
+	if ((bt_link_info->hid_exist) && (bt_link_info->a2dp_exist)) {
+		halbtc8821a1ant_ps_tdma(btcoexist, NORMAL_EXEC, true,
+					14);
+		halbtc8821a1ant_coex_table_with_type(btcoexist,
+						     NORMAL_EXEC, 1);
+	}
+
+
+	else if (bt_link_info->pan_exist) {
+		halbtc8821a1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 20);
+		halbtc8821a1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4);
+	} else {
+		halbtc8821a1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 8);
+		halbtc8821a1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 2);
+	}
+}
+
+void halbtc8821a1ant_action_wifi_connected(IN struct btc_coexist *btcoexist)
+{
+	boolean	wifi_busy = false;
+	boolean	scan = false, link = false, roam = false;
+	boolean		under_4way = false, ap_enable = false;
+
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+		    "[BTCoex], CoexForWifiConnect()===>\n");
+	BTC_TRACE(trace_buf);
+
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_4_WAY_PROGRESS,
+			   &under_4way);
+	if (under_4way) {
+		halbtc8821a1ant_action_wifi_connected_specific_packet(
+			btcoexist);
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			"[BTCoex], CoexForWifiConnect(), return for wifi is under 4way<===\n");
+		BTC_TRACE(trace_buf);
+		return;
+	}
+
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_SCAN, &scan);
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_LINK, &link);
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_ROAM, &roam);
+	if (scan || link || roam) {
+		if (scan)
+			halbtc8821a1ant_action_wifi_connected_scan(btcoexist);
+		else
+			halbtc8821a1ant_action_wifi_connected_specific_packet(
+				btcoexist);
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			"[BTCoex], CoexForWifiConnect(), return for wifi is under scan<===\n");
+		BTC_TRACE(trace_buf);
+		return;
+	}
+
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_AP_MODE_ENABLE,
+			   &ap_enable);
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy);
+
+	/* tdma and coex table */
+	if (!wifi_busy) {
+		if (BT_8821A_1ANT_BT_STATUS_ACL_BUSY == coex_dm->bt_status) {
+			halbtc8821a1ant_action_wifi_connected_bt_acl_busy(
+				btcoexist,
+				BT_8821A_1ANT_WIFI_STATUS_CONNECTED_IDLE);
+		} else if ((BT_8821A_1ANT_BT_STATUS_SCO_BUSY ==
+			    coex_dm->bt_status) ||
+			   (BT_8821A_1ANT_BT_STATUS_ACL_SCO_BUSY ==
+			    coex_dm->bt_status)) {
+			halbtc8821a1ant_action_bt_sco_hid_only_busy(btcoexist,
+				BT_8821A_1ANT_WIFI_STATUS_CONNECTED_IDLE);
+		} else {
+			halbtc8821a1ant_ps_tdma(btcoexist, NORMAL_EXEC, false,
+						8);
+			halbtc8821a1ant_coex_table_with_type(btcoexist,
+							     NORMAL_EXEC, 2);
+		}
+	} else {
+		if (BT_8821A_1ANT_BT_STATUS_ACL_BUSY == coex_dm->bt_status) {
+			halbtc8821a1ant_action_wifi_connected_bt_acl_busy(
+				btcoexist,
+				BT_8821A_1ANT_WIFI_STATUS_CONNECTED_BUSY);
+		} else if ((BT_8821A_1ANT_BT_STATUS_SCO_BUSY ==
+			    coex_dm->bt_status) ||
+			   (BT_8821A_1ANT_BT_STATUS_ACL_SCO_BUSY ==
+			    coex_dm->bt_status)) {
+			halbtc8821a1ant_action_bt_sco_hid_only_busy(btcoexist,
+				BT_8821A_1ANT_WIFI_STATUS_CONNECTED_BUSY);
+		} else {
+			halbtc8821a1ant_ps_tdma(btcoexist, NORMAL_EXEC, false,
+						8);
+			halbtc8821a1ant_coex_table_with_type(btcoexist,
+							     NORMAL_EXEC, 2);
+		}
+	}
+}
+
+void halbtc8821a1ant_run_sw_coexist_mechanism(IN struct btc_coexist *btcoexist)
+{
+	u8	algorithm = 0;
+
+	algorithm = halbtc8821a1ant_action_algorithm(btcoexist);
+	coex_dm->cur_algorithm = algorithm;
+
+	if (halbtc8821a1ant_is_common_action(btcoexist)) {
+
+	} else {
+		switch (coex_dm->cur_algorithm) {
+		case BT_8821A_1ANT_COEX_ALGO_SCO:
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				    "[BTCoex], Action algorithm = SCO.\n");
+			BTC_TRACE(trace_buf);
+			halbtc8821a1ant_action_sco(btcoexist);
+			break;
+		case BT_8821A_1ANT_COEX_ALGO_HID:
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				    "[BTCoex], Action algorithm = HID.\n");
+			BTC_TRACE(trace_buf);
+			halbtc8821a1ant_action_hid(btcoexist);
+			break;
+		case BT_8821A_1ANT_COEX_ALGO_A2DP:
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				    "[BTCoex], Action algorithm = A2DP.\n");
+			BTC_TRACE(trace_buf);
+			halbtc8821a1ant_action_a2dp(btcoexist);
+			break;
+		case BT_8821A_1ANT_COEX_ALGO_A2DP_PANHS:
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				"[BTCoex], Action algorithm = A2DP+PAN(HS).\n");
+			BTC_TRACE(trace_buf);
+			halbtc8821a1ant_action_a2dp_pan_hs(btcoexist);
+			break;
+		case BT_8821A_1ANT_COEX_ALGO_PANEDR:
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				    "[BTCoex], Action algorithm = PAN(EDR).\n");
+			BTC_TRACE(trace_buf);
+			halbtc8821a1ant_action_pan_edr(btcoexist);
+			break;
+		case BT_8821A_1ANT_COEX_ALGO_PANHS:
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				    "[BTCoex], Action algorithm = HS mode.\n");
+			BTC_TRACE(trace_buf);
+			halbtc8821a1ant_action_pan_hs(btcoexist);
+			break;
+		case BT_8821A_1ANT_COEX_ALGO_PANEDR_A2DP:
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				    "[BTCoex], Action algorithm = PAN+A2DP.\n");
+			BTC_TRACE(trace_buf);
+			halbtc8821a1ant_action_pan_edr_a2dp(btcoexist);
+			break;
+		case BT_8821A_1ANT_COEX_ALGO_PANEDR_HID:
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				"[BTCoex], Action algorithm = PAN(EDR)+HID.\n");
+			BTC_TRACE(trace_buf);
+			halbtc8821a1ant_action_pan_edr_hid(btcoexist);
+			break;
+		case BT_8821A_1ANT_COEX_ALGO_HID_A2DP_PANEDR:
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				"[BTCoex], Action algorithm = HID+A2DP+PAN.\n");
+			BTC_TRACE(trace_buf);
+			halbtc8821a1ant_action_hid_a2dp_pan_edr(
+				btcoexist);
+			break;
+		case BT_8821A_1ANT_COEX_ALGO_HID_A2DP:
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				    "[BTCoex], Action algorithm = HID+A2DP.\n");
+			BTC_TRACE(trace_buf);
+			halbtc8821a1ant_action_hid_a2dp(btcoexist);
+			break;
+		default:
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				"[BTCoex], Action algorithm = coexist All Off!!\n");
+			BTC_TRACE(trace_buf);
+			/* halbtc8821a1ant_coex_all_off(btcoexist); */
+			break;
+		}
+		coex_dm->pre_algorithm = coex_dm->cur_algorithm;
+	}
+}
+
+void halbtc8821a1ant_run_coexist_mechanism(IN struct btc_coexist *btcoexist)
+{
+	struct  btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
+	boolean	wifi_connected = false, bt_hs_on = false;
+	boolean	increase_scan_dev_num = false;
+	boolean	bt_ctrl_agg_buf_size = false;
+	u8	agg_buf_size = 5;
+	u8	wifi_rssi_state = BTC_RSSI_STATE_HIGH;
+	u32	wifi_link_status = 0;
+	u32	num_of_wifi_link = 0;
+	boolean	wifi_under_5g = false;
+
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+		    "[BTCoex], RunCoexistMechanism()===>\n");
+	BTC_TRACE(trace_buf);
+
+	if (btcoexist->manual_control) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			"[BTCoex], RunCoexistMechanism(), return for Manual CTRL <===\n");
+		BTC_TRACE(trace_buf);
+		return;
+	}
+
+	if (btcoexist->stop_coex_dm) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			"[BTCoex], RunCoexistMechanism(), return for Stop Coex DM <===\n");
+		BTC_TRACE(trace_buf);
+		return;
+	}
+
+	if (coex_sta->under_ips) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], wifi is under IPS !!!\n");
+		BTC_TRACE(trace_buf);
+		return;
+	}
+
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_5G, &wifi_under_5g);
+	if (wifi_under_5g) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			"[BTCoex], RunCoexistMechanism(), return for 5G <===\n");
+		BTC_TRACE(trace_buf);
+		halbtc8821a1ant_coex_under_5g(btcoexist);
+		return;
+	}
+	if (coex_sta->bt_whck_test) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], BT is under WHCK TEST!!!\n");
+		BTC_TRACE(trace_buf);
+		halbtc8821a1ant_action_bt_whck_test(btcoexist);
+		return;
+	}
+
+	if ((BT_8821A_1ANT_BT_STATUS_ACL_BUSY == coex_dm->bt_status) ||
+	    (BT_8821A_1ANT_BT_STATUS_SCO_BUSY == coex_dm->bt_status) ||
+	    (BT_8821A_1ANT_BT_STATUS_ACL_SCO_BUSY == coex_dm->bt_status))
+		increase_scan_dev_num = true;
+
+	btcoexist->btc_set(btcoexist, BTC_SET_BL_INC_SCAN_DEV_NUM,
+			   &increase_scan_dev_num);
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED,
+			   &wifi_connected);
+
+	btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_LINK_STATUS,
+			   &wifi_link_status);
+	num_of_wifi_link = wifi_link_status >> 16;
+	if ((num_of_wifi_link >= 2) ||
+	    (wifi_link_status & WIFI_P2P_GO_CONNECTED)) {
+		halbtc8821a1ant_limited_tx(btcoexist, NORMAL_EXEC, 0, 0, 0, 0);
+		halbtc8821a1ant_limited_rx(btcoexist, NORMAL_EXEC, false,
+					   bt_ctrl_agg_buf_size, agg_buf_size);
+		halbtc8821a1ant_action_wifi_multi_port(btcoexist);
+		return;
+	}
+
+	if (!bt_link_info->sco_exist && !bt_link_info->hid_exist)
+		halbtc8821a1ant_limited_tx(btcoexist, NORMAL_EXEC, 0, 0, 0, 0);
+	else {
+		if (wifi_connected) {
+			wifi_rssi_state = halbtc8821a1ant_wifi_rssi_state(
+						  btcoexist, 1, 2, 30, 0);
+			if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) ||
+			    (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
+				/* halbtc8821a1ant_limited_tx(btcoexist, NORMAL_EXEC, 1, 1, 1, 1); */
+				halbtc8821a1ant_limited_tx(btcoexist,
+						   NORMAL_EXEC, 1, 1, 0, 1);
+			} else {
+				/* halbtc8821a1ant_limited_tx(btcoexist, NORMAL_EXEC, 1, 1, 1, 1); */
+				halbtc8821a1ant_limited_tx(btcoexist,
+						   NORMAL_EXEC, 1, 1, 0, 1);
+			}
+		} else
+			halbtc8821a1ant_limited_tx(btcoexist, NORMAL_EXEC, 0, 0,
+						   0, 0);
+
+	}
+
+	if (bt_link_info->sco_exist) {
+		bt_ctrl_agg_buf_size = true;
+		agg_buf_size = 0x3;
+	} else if (bt_link_info->hid_exist) {
+		bt_ctrl_agg_buf_size = true;
+		agg_buf_size = 0x5;
+	} else if (bt_link_info->a2dp_exist || bt_link_info->pan_exist) {
+		bt_ctrl_agg_buf_size = true;
+		agg_buf_size = 0x8;
+	}
+	halbtc8821a1ant_limited_rx(btcoexist, NORMAL_EXEC, false,
+				   bt_ctrl_agg_buf_size, agg_buf_size);
+
+	halbtc8821a1ant_run_sw_coexist_mechanism(btcoexist);
+
+	/* low pelnaty ra in pcr ra */
+	btcoexist->btc_phydm_modify_RA_PCR_threshold(btcoexist, 0, 25);
+
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on);
+	if (coex_sta->c2h_bt_inquiry_page) {
+		halbtc8821a1ant_action_bt_inquiry(btcoexist);
+		return;
+	} else if (bt_hs_on) {
+		halbtc8821a1ant_action_hs(btcoexist);
+		return;
+	}
+
+
+	if (!wifi_connected) {
+		boolean	scan = false, link = false, roam = false;
+
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], wifi is non connected-idle !!!\n");
+		BTC_TRACE(trace_buf);
+
+		btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_SCAN, &scan);
+		btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_LINK, &link);
+		btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_ROAM, &roam);
+
+		if (scan || link || roam) {
+			if (scan)
+				halbtc8821a1ant_action_wifi_not_connected_scan(
+					btcoexist);
+			else
+				halbtc8821a1ant_action_wifi_not_connected_asso_auth(
+					btcoexist);
+		} else
+			halbtc8821a1ant_action_wifi_not_connected(btcoexist);
+	} else	/* wifi LPS/Busy */
+		halbtc8821a1ant_action_wifi_connected(btcoexist);
+}
+
+void halbtc8821a1ant_init_coex_dm(IN struct btc_coexist *btcoexist)
+{
+	/* force to reset coex mechanism */
+	/* sw all off */
+	halbtc8821a1ant_sw_mechanism(btcoexist, false);
+
+	/* halbtc8821a1ant_ps_tdma(btcoexist, FORCE_EXEC, false, 8); */
+	halbtc8821a1ant_coex_table_with_type(btcoexist, FORCE_EXEC, 0);
+}
+
+void halbtc8821a1ant_init_hw_config(IN struct btc_coexist *btcoexist,
+				    IN boolean back_up, IN boolean wifi_only)
+{
+	u8	u8tmp = 0;
+	boolean			wifi_under_5g = false;
+
+
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+		    "[BTCoex], 1Ant Init HW Config!!\n");
+	BTC_TRACE(trace_buf);
+
+	if (wifi_only)
+		return;
+
+	if (back_up) {
+		coex_dm->backup_arfr_cnt1 = btcoexist->btc_read_4byte(btcoexist,
+					    0x430);
+		coex_dm->backup_arfr_cnt2 = btcoexist->btc_read_4byte(btcoexist,
+					    0x434);
+		coex_dm->backup_retry_limit = btcoexist->btc_read_2byte(
+						      btcoexist, 0x42a);
+		coex_dm->backup_ampdu_max_time = btcoexist->btc_read_1byte(
+				btcoexist, 0x456);
+	}
+
+	/* 0x790[5:0]=0x5 */
+	u8tmp = btcoexist->btc_read_1byte(btcoexist, 0x790);
+	u8tmp &= 0xc0;
+	u8tmp |= 0x5;
+	btcoexist->btc_write_1byte(btcoexist, 0x790, u8tmp);
+
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_5G, &wifi_under_5g);
+
+	/* Give bt_coex_supported_version the default value */
+	coex_sta->bt_coex_supported_version = 0;
+
+	/* 0xf0[15:12] --> Chip Cut information */
+	coex_sta->cut_version = (btcoexist->btc_read_1byte(btcoexist,
+				 0xf1) & 0xf0) >> 4;
+
+	/* Antenna config */
+	if (wifi_under_5g)
+		halbtc8821a1ant_set_ant_path(btcoexist, BTC_ANT_PATH_BT, true,
+					     false);
+	else
+		halbtc8821a1ant_set_ant_path(btcoexist, BTC_ANT_PATH_PTA, true,
+					     false);
+
+	/* PTA parameter */
+	halbtc8821a1ant_coex_table_with_type(btcoexist, FORCE_EXEC, 0);
+
+	/* Enable counter statistics */
+	btcoexist->btc_write_1byte(btcoexist, 0x76e,
+			   0xc); /* 0x76e[3] =1, WLAN_Act control by PTA */
+	btcoexist->btc_write_1byte(btcoexist, 0x778, 0x3);
+	btcoexist->btc_write_1byte_bitmask(btcoexist, 0x40, 0x20, 0x1);
+}
+
+/* ************************************************************
+ * work around function start with wa_halbtc8821a1ant_
+ * ************************************************************
+ * ************************************************************
+ * extern function start with ex_halbtc8821a1ant_
+ * ************************************************************ */
+void ex_halbtc8821a1ant_power_on_setting(IN struct btc_coexist *btcoexist)
+{
+}
+
+void ex_halbtc8821a1ant_init_hw_config(IN struct btc_coexist *btcoexist,
+				       IN boolean wifi_only)
+{
+	halbtc8821a1ant_init_hw_config(btcoexist, true, wifi_only);
+}
+
+void ex_halbtc8821a1ant_init_coex_dm(IN struct btc_coexist *btcoexist)
+{
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+		    "[BTCoex], Coex Mechanism Init!!\n");
+	BTC_TRACE(trace_buf);
+
+	btcoexist->stop_coex_dm = false;
+
+	halbtc8821a1ant_init_coex_dm(btcoexist);
+
+	halbtc8821a1ant_query_bt_info(btcoexist);
+}
+
+void ex_halbtc8821a1ant_display_coex_info(IN struct btc_coexist *btcoexist)
+{
+	struct  btc_board_info		*board_info = &btcoexist->board_info;
+	struct  btc_bt_link_info	*bt_link_info = &btcoexist->bt_link_info;
+	u8				*cli_buf = btcoexist->cli_buf;
+	u8				u8tmp[4], i, bt_info_ext, ps_tdma_case = 0;
+	u16				u16tmp[4];
+	u32				u32tmp[4];
+	u32				fw_ver = 0, bt_patch_ver = 0;
+	u32				bt_coex_ver = 0;
+	u32				fa_ofdm, fa_cck, cca_ofdm, cca_cck;
+	u32				phyver = 0;
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+		   "\r\n ============[BT Coexist info]============");
+	CL_PRINTF(cli_buf);
+
+	if (btcoexist->manual_control) {
+		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+			"\r\n ============[Under Manual Control]============");
+		CL_PRINTF(cli_buf);
+		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+			   "\r\n ==========================================");
+		CL_PRINTF(cli_buf);
+	}
+	if (btcoexist->stop_coex_dm) {
+		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+			   "\r\n ============[Coex is STOPPED]============");
+		CL_PRINTF(cli_buf);
+		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+			   "\r\n ==========================================");
+		CL_PRINTF(cli_buf);
+	}
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d",
+		   "Ant PG Num/ Ant Mech/ Ant Pos:",
+		   board_info->pg_ant_num, board_info->btdm_ant_num,
+		   board_info->btdm_ant_pos);
+	CL_PRINTF(cli_buf);
+
+	/* btcoexist->btc_get(btcoexist, BTC_GET_U4_BT_PATCH_VER, &bt_patch_ver); */
+	bt_patch_ver = btcoexist->bt_info.bt_get_fw_ver;
+	btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_FW_VER, &fw_ver);
+	phyver = btcoexist->btc_get_bt_phydm_version(btcoexist);
+	bt_coex_ver = ((coex_sta->bt_coex_supported_version & 0xff00) >> 8);
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+		   "\r\n %-35s = %d_%02x/ 0x%02x/ 0x%02x (%s)",
+		   "CoexVer WL/  BT_Desired/ BT_Report",
+		   glcoex_ver_date_8821a_1ant, glcoex_ver_8821a_1ant,
+		   glcoex_ver_btdesired_8821a_1ant,
+		   bt_coex_ver,
+		   (bt_coex_ver == 0xff ? "Unknown" :
+		    (bt_coex_ver >= glcoex_ver_btdesired_8821a_1ant ?
+		     "Match" : "Mis-Match")));
+	CL_PRINTF(cli_buf);
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+		   "\r\n %-35s = 0x%x/ 0x%x/ v%d/ %c",
+		   "W_FW/ B_FW/ Phy/ Kt",
+		   fw_ver, bt_patch_ver, phyver,
+		   coex_sta->cut_version + 65);
+	CL_PRINTF(cli_buf);
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %02x %02x %02x ",
+		   "Wifi channel informed to BT",
+		   coex_dm->wifi_chnl_info[0], coex_dm->wifi_chnl_info[1],
+		   coex_dm->wifi_chnl_info[2]);
+	CL_PRINTF(cli_buf);
+
+	/* wifi status */
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s",
+		   "============[Wifi Status]============");
+	CL_PRINTF(cli_buf);
+	btcoexist->btc_disp_dbg_msg(btcoexist, BTC_DBG_DISP_WIFI_STATUS);
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s",
+		   "============[BT Status]============");
+	CL_PRINTF(cli_buf);
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = [%s/ %d/ %d] ",
+		   "BT [status/ rssi/ retryCnt]",
+		   ((coex_sta->bt_disabled) ? ("disabled") :	((
+		   coex_sta->c2h_bt_inquiry_page) ? ("inquiry/page scan")
+			   : ((BT_8821A_1ANT_BT_STATUS_NON_CONNECTED_IDLE ==
+			       coex_dm->bt_status) ? "non-connected idle" :
+		((BT_8821A_1ANT_BT_STATUS_CONNECTED_IDLE == coex_dm->bt_status)
+				       ? "connected-idle" : "busy")))),
+		   coex_sta->bt_rssi, coex_sta->bt_retry_cnt);
+	CL_PRINTF(cli_buf);
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d / %d / %d / %d",
+		   "SCO/HID/PAN/A2DP",
+		   bt_link_info->sco_exist, bt_link_info->hid_exist,
+		   bt_link_info->pan_exist, bt_link_info->a2dp_exist);
+	CL_PRINTF(cli_buf);
+	btcoexist->btc_disp_dbg_msg(btcoexist, BTC_DBG_DISP_BT_LINK_INFO);
+
+	bt_info_ext = coex_sta->bt_info_ext;
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s",
+		   "BT Info A2DP rate",
+		   (bt_info_ext & BIT(0)) ? "Basic rate" : "EDR rate");
+	CL_PRINTF(cli_buf);
+
+	for (i = 0; i < BT_INFO_SRC_8821A_1ANT_MAX; i++) {
+		if (coex_sta->bt_info_c2h_cnt[i]) {
+			CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+				"\r\n %-35s = %02x %02x %02x %02x %02x %02x %02x(%d)",
+				   glbt_info_src_8821a_1ant[i],
+				   coex_sta->bt_info_c2h[i][0],
+				   coex_sta->bt_info_c2h[i][1],
+				   coex_sta->bt_info_c2h[i][2],
+				   coex_sta->bt_info_c2h[i][3],
+				   coex_sta->bt_info_c2h[i][4],
+				   coex_sta->bt_info_c2h[i][5],
+				   coex_sta->bt_info_c2h[i][6],
+				   coex_sta->bt_info_c2h_cnt[i]);
+			CL_PRINTF(cli_buf);
+		}
+	}
+
+	if (!btcoexist->manual_control) {
+		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d",
+			   "SM[LowPenaltyRA]",
+			   coex_dm->cur_low_penalty_ra);
+		CL_PRINTF(cli_buf);
+
+		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s",
+			   "============[mechanisms]============");
+		CL_PRINTF(cli_buf);
+
+		ps_tdma_case = coex_dm->cur_ps_tdma;
+		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+			"\r\n %-35s = %02x %02x %02x %02x %02x case-%d (auto:%d)",
+			   "PS TDMA",
+			   coex_dm->ps_tdma_para[0], coex_dm->ps_tdma_para[1],
+			   coex_dm->ps_tdma_para[2], coex_dm->ps_tdma_para[3],
+			   coex_dm->ps_tdma_para[4], ps_tdma_case,
+			   coex_dm->auto_tdma_adjust);
+		CL_PRINTF(cli_buf);
+
+		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d ",
+			   "IgnWlanAct",
+			   coex_dm->cur_ignore_wlan_act);
+		CL_PRINTF(cli_buf);
+
+		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x ",
+			   "Latest error condition(should be 0)",
+			   coex_dm->error_condition);
+		CL_PRINTF(cli_buf);
+	}
+
+	/* Hw setting		 */
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s",
+		   "============[Hw setting]============");
+	CL_PRINTF(cli_buf);
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/0x%x/0x%x/0x%x",
+		   "backup ARFR1/ARFR2/RL/AMaxTime",
+		   coex_dm->backup_arfr_cnt1, coex_dm->backup_arfr_cnt2,
+		   coex_dm->backup_retry_limit,
+		   coex_dm->backup_ampdu_max_time);
+	CL_PRINTF(cli_buf);
+
+	u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x430);
+	u32tmp[1] = btcoexist->btc_read_4byte(btcoexist, 0x434);
+	u16tmp[0] = btcoexist->btc_read_2byte(btcoexist, 0x42a);
+	u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x456);
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/0x%x/0x%x/0x%x",
+		   "0x430/0x434/0x42a/0x456",
+		   u32tmp[0], u32tmp[1], u16tmp[0], u8tmp[0]);
+	CL_PRINTF(cli_buf);
+
+	u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x778);
+	u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0xc58);
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x",
+		   "0x778/ 0xc58[29:25]",
+		   u8tmp[0], (u32tmp[0] & 0x3e000000) >> 25);
+	CL_PRINTF(cli_buf);
+
+	u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x8db);
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x", "0x8db[6:5]",
+		   ((u8tmp[0] & 0x60) >> 5));
+	CL_PRINTF(cli_buf);
+
+	u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x975);
+	u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0xcb4);
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x/ 0x%x",
+		   "0xcb4[29:28]/0xcb4[7:0]/0x974[9:8]",
+		   (u32tmp[0] & 0x30000000) >> 28, u32tmp[0] & 0xff,
+		   u8tmp[0] & 0x3);
+	CL_PRINTF(cli_buf);
+
+
+	u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x40);
+	u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x4c);
+	u8tmp[1] = btcoexist->btc_read_1byte(btcoexist, 0x64);
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x/ 0x%x",
+		   "0x40/0x4c[24:23]/0x64[0]",
+		   u8tmp[0], ((u32tmp[0] & 0x01800000) >> 23), u8tmp[1] & 0x1);
+	CL_PRINTF(cli_buf);
+
+	u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x550);
+	u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x522);
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x",
+		   "0x550(bcn ctrl)/0x522",
+		   u32tmp[0], u8tmp[0]);
+	CL_PRINTF(cli_buf);
+
+	u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0xc50);
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x", "0xc50(dig)",
+		   u32tmp[0] & 0xff);
+	CL_PRINTF(cli_buf);
+
+	fa_ofdm = btcoexist->btc_phydm_query_PHY_counter(btcoexist,
+			PHYDM_INFO_FA_OFDM);
+	fa_cck = btcoexist->btc_phydm_query_PHY_counter(btcoexist,
+			PHYDM_INFO_FA_CCK);
+	cca_ofdm = btcoexist->btc_phydm_query_PHY_counter(btcoexist,
+			PHYDM_INFO_CCA_OFDM);
+	cca_cck = btcoexist->btc_phydm_query_PHY_counter(btcoexist,
+			PHYDM_INFO_CCA_CCK);
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+		   "\r\n %-35s = 0x%x/ 0x%x/ 0x%x/ 0x%x",
+		   "CCK-CCA/CCK-FA/OFDM-CCA/OFDM-FA",
+		   cca_cck, fa_cck, cca_ofdm, fa_ofdm);
+	CL_PRINTF(cli_buf);
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d/ %d",
+		   "CRC_OK CCK/11g/11n/11n-agg",
+		   coex_sta->crc_ok_cck, coex_sta->crc_ok_11g,
+		   coex_sta->crc_ok_11n, coex_sta->crc_ok_11n_vht);
+	CL_PRINTF(cli_buf);
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d/ %d",
+		   "CRC_Err CCK/11g/11n/11n-agg",
+		   coex_sta->crc_err_cck, coex_sta->crc_err_11g,
+		   coex_sta->crc_err_11n, coex_sta->crc_err_11n_vht);
+	CL_PRINTF(cli_buf);
+
+
+	u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x6c0);
+	u32tmp[1] = btcoexist->btc_read_4byte(btcoexist, 0x6c4);
+	u32tmp[2] = btcoexist->btc_read_4byte(btcoexist, 0x6c8);
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x/ 0x%x",
+		   "0x6c0/0x6c4/0x6c8(coexTable)",
+		   u32tmp[0], u32tmp[1], u32tmp[2]);
+	CL_PRINTF(cli_buf);
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d",
+		   "0x770(high-pri rx/tx)",
+		   coex_sta->high_priority_rx, coex_sta->high_priority_tx);
+	CL_PRINTF(cli_buf);
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d",
+		   "0x774(low-pri rx/tx)",
+		   coex_sta->low_priority_rx, coex_sta->low_priority_tx);
+	CL_PRINTF(cli_buf);
+#if (BT_AUTO_REPORT_ONLY_8821A_1ANT == 1)
+	halbtc8821a1ant_monitor_bt_ctr(btcoexist);
+#endif
+	btcoexist->btc_disp_dbg_msg(btcoexist, BTC_DBG_DISP_COEX_STATISTICS);
+}
+
+
+void ex_halbtc8821a1ant_ips_notify(IN struct btc_coexist *btcoexist, IN u8 type)
+{
+	boolean	wifi_under_5g = false;
+
+	if (btcoexist->manual_control ||	btcoexist->stop_coex_dm)
+		return;
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_5G,
+			   &wifi_under_5g);
+	if (wifi_under_5g) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			"[BTCoex], RunCoexistMechanism(), return for 5G <===\n");
+		BTC_TRACE(trace_buf);
+		halbtc8821a1ant_coex_under_5g(btcoexist);
+		return;
+	}
+
+	if (BTC_IPS_ENTER == type) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], IPS ENTER notify\n");
+		BTC_TRACE(trace_buf);
+		coex_sta->under_ips = true;
+
+		halbtc8821a1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 0);
+		halbtc8821a1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0);
+		halbtc8821a1ant_set_ant_path(btcoexist, BTC_ANT_PATH_BT, false,
+					     true);
+		/* halbtc8821a1ant_set_ant_path_d_cut(btcoexist, false, false, false, BTC_ANT_PATH_BT, BTC_WIFI_STAT_NORMAL_OFF); */
+	} else if (BTC_IPS_LEAVE == type) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], IPS LEAVE notify\n");
+		BTC_TRACE(trace_buf);
+		coex_sta->under_ips = false;
+
+		halbtc8821a1ant_init_hw_config(btcoexist, false, false);
+		halbtc8821a1ant_init_coex_dm(btcoexist);
+		halbtc8821a1ant_query_bt_info(btcoexist);
+	}
+}
+
+void ex_halbtc8821a1ant_lps_notify(IN struct btc_coexist *btcoexist, IN u8 type)
+{
+
+
+	if (BTC_LPS_ENABLE == type) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], LPS ENABLE notify\n");
+		BTC_TRACE(trace_buf);
+		coex_sta->under_lps = true;
+	} else if (BTC_LPS_DISABLE == type) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], LPS DISABLE notify\n");
+		BTC_TRACE(trace_buf);
+		coex_sta->under_lps = false;
+	}
+}
+
+void ex_halbtc8821a1ant_scan_notify(IN struct btc_coexist *btcoexist,
+				    IN u8 type)
+{
+	boolean wifi_connected = false, bt_hs_on = false;
+	u32	wifi_link_status = 0;
+	u32	num_of_wifi_link = 0;
+	boolean	bt_ctrl_agg_buf_size = false;
+	u8	agg_buf_size = 5;
+	boolean	wifi_under_5g = false;
+
+	if (btcoexist->manual_control ||
+	    btcoexist->stop_coex_dm)
+		return;
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_5G, &wifi_under_5g);
+	if (wifi_under_5g) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			"[BTCoex], RunCoexistMechanism(), return for 5G <===\n");
+		BTC_TRACE(trace_buf);
+		halbtc8821a1ant_coex_under_5g(btcoexist);
+		return;
+	}
+
+	if (BTC_SCAN_START == type) {
+		coex_sta->wifi_is_high_pri_task = true;
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], SCAN START notify\n");
+		BTC_TRACE(trace_buf);
+
+		halbtc8821a1ant_ps_tdma(btcoexist, FORCE_EXEC, false,
+			8);  /* Force antenna setup for no scan result issue */
+	} else {
+		coex_sta->wifi_is_high_pri_task = false;
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], SCAN FINISH notify\n");
+		BTC_TRACE(trace_buf);
+	}
+
+	if (coex_sta->bt_disabled)
+		return;
+
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on);
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED,
+			   &wifi_connected);
+
+	halbtc8821a1ant_query_bt_info(btcoexist);
+
+	btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_LINK_STATUS,
+			   &wifi_link_status);
+	num_of_wifi_link = wifi_link_status >> 16;
+	if (num_of_wifi_link >= 2) {
+		halbtc8821a1ant_limited_tx(btcoexist, NORMAL_EXEC, 0, 0, 0, 0);
+		halbtc8821a1ant_limited_rx(btcoexist, NORMAL_EXEC, false,
+					   bt_ctrl_agg_buf_size, agg_buf_size);
+		halbtc8821a1ant_action_wifi_multi_port(btcoexist);
+		return;
+	}
+
+	if (coex_sta->c2h_bt_inquiry_page) {
+		halbtc8821a1ant_action_bt_inquiry(btcoexist);
+		return;
+	} else if (bt_hs_on) {
+		halbtc8821a1ant_action_hs(btcoexist);
+		return;
+	}
+
+	if (BTC_SCAN_START == type) {
+		if (!wifi_connected)	/* non-connected scan */
+			halbtc8821a1ant_action_wifi_not_connected_scan(
+				btcoexist);
+		else	/* wifi is connected */
+			halbtc8821a1ant_action_wifi_connected_scan(btcoexist);
+	} else if (BTC_SCAN_FINISH == type) {
+		if (!wifi_connected)	/* non-connected scan */
+			halbtc8821a1ant_action_wifi_not_connected(btcoexist);
+		else
+			halbtc8821a1ant_action_wifi_connected(btcoexist);
+	}
+}
+
+/* copy scan notify content to switch band notify */
+void ex_halbtc8821a1ant_switchband_notify(IN struct btc_coexist *btcoexist,
+		IN u8 type)
+{
+	boolean wifi_connected = false, bt_hs_on = false;
+	u32	wifi_link_status = 0;
+	u32	num_of_wifi_link = 0;
+	boolean	bt_ctrl_agg_buf_size = false;
+	u8	agg_buf_size = 5;
+	boolean	wifi_under_5g = false;
+
+	if (btcoexist->manual_control ||
+	    btcoexist->stop_coex_dm)
+		return;
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_5G, &wifi_under_5g);
+	if (wifi_under_5g) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			"[BTCoex], RunCoexistMechanism(), return for 5G <===\n");
+		BTC_TRACE(trace_buf);
+		halbtc8821a1ant_coex_under_5g(btcoexist);
+		return;
+	}
+
+	if (BTC_SCAN_START == type) {
+		coex_sta->wifi_is_high_pri_task = true;
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], SCAN START notify\n");
+		BTC_TRACE(trace_buf);
+
+		halbtc8821a1ant_ps_tdma(btcoexist, FORCE_EXEC, false,
+			8);  /* Force antenna setup for no scan result issue */
+	} else {
+		coex_sta->wifi_is_high_pri_task = false;
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], SCAN FINISH notify\n");
+		BTC_TRACE(trace_buf);
+	}
+
+	if (coex_sta->bt_disabled)
+		return;
+
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on);
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED,
+			   &wifi_connected);
+
+	halbtc8821a1ant_query_bt_info(btcoexist);
+
+	btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_LINK_STATUS,
+			   &wifi_link_status);
+	num_of_wifi_link = wifi_link_status >> 16;
+	if (num_of_wifi_link >= 2) {
+		halbtc8821a1ant_limited_tx(btcoexist, NORMAL_EXEC, 0, 0, 0, 0);
+		halbtc8821a1ant_limited_rx(btcoexist, NORMAL_EXEC, false,
+					   bt_ctrl_agg_buf_size, agg_buf_size);
+		halbtc8821a1ant_action_wifi_multi_port(btcoexist);
+		return;
+	}
+
+	if (coex_sta->c2h_bt_inquiry_page) {
+		halbtc8821a1ant_action_bt_inquiry(btcoexist);
+		return;
+	} else if (bt_hs_on) {
+		halbtc8821a1ant_action_hs(btcoexist);
+		return;
+	}
+
+	if (BTC_SCAN_START == type) {
+		if (!wifi_connected)	/* non-connected scan */
+			halbtc8821a1ant_action_wifi_not_connected_scan(
+				btcoexist);
+		else	/* wifi is connected */
+			halbtc8821a1ant_action_wifi_connected_scan(btcoexist);
+	} else if (BTC_SCAN_FINISH == type) {
+		if (!wifi_connected)	/* non-connected scan */
+			halbtc8821a1ant_action_wifi_not_connected(btcoexist);
+		else
+			halbtc8821a1ant_action_wifi_connected(btcoexist);
+	}
+}
+void ex_halbtc8821a1ant_connect_notify(IN struct btc_coexist *btcoexist,
+				       IN u8 type)
+{
+	boolean	wifi_connected = false, bt_hs_on = false;
+	u32	wifi_link_status = 0;
+	u32	num_of_wifi_link = 0;
+	boolean	bt_ctrl_agg_buf_size = false;
+	u8	agg_buf_size = 5;
+	boolean	wifi_under_5g = false;
+
+	if (btcoexist->manual_control ||
+	    btcoexist->stop_coex_dm ||
+	    coex_sta->bt_disabled)
+		return;
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_5G, &wifi_under_5g);
+	if (wifi_under_5g) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			"[BTCoex], RunCoexistMechanism(), return for 5G <===\n");
+		BTC_TRACE(trace_buf);
+		halbtc8821a1ant_coex_under_5g(btcoexist);
+		return;
+	}
+
+	if (BTC_ASSOCIATE_START == type) {
+		coex_sta->wifi_is_high_pri_task = true;
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], CONNECT START notify\n");
+		BTC_TRACE(trace_buf);
+		coex_dm->arp_cnt = 0;
+	} else {
+		coex_sta->wifi_is_high_pri_task = false;
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], CONNECT FINISH notify\n");
+		BTC_TRACE(trace_buf);
+		coex_dm->arp_cnt = 0;
+	}
+
+	btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_LINK_STATUS,
+			   &wifi_link_status);
+	num_of_wifi_link = wifi_link_status >> 16;
+	if (num_of_wifi_link >= 2) {
+		halbtc8821a1ant_limited_tx(btcoexist, NORMAL_EXEC, 0, 0, 0, 0);
+		halbtc8821a1ant_limited_rx(btcoexist, NORMAL_EXEC, false,
+					   bt_ctrl_agg_buf_size, agg_buf_size);
+		halbtc8821a1ant_action_wifi_multi_port(btcoexist);
+		return;
+	}
+
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on);
+	if (coex_sta->c2h_bt_inquiry_page) {
+		halbtc8821a1ant_action_bt_inquiry(btcoexist);
+		return;
+	} else if (bt_hs_on) {
+		halbtc8821a1ant_action_hs(btcoexist);
+		return;
+	}
+
+	if (BTC_ASSOCIATE_START == type)
+		halbtc8821a1ant_action_wifi_not_connected_asso_auth(btcoexist);
+	else if (BTC_ASSOCIATE_FINISH == type) {
+		btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED,
+				   &wifi_connected);
+		if (!wifi_connected) /* non-connected scan */
+			halbtc8821a1ant_action_wifi_not_connected(btcoexist);
+		else
+			halbtc8821a1ant_action_wifi_connected(btcoexist);
+	}
+}
+
+void ex_halbtc8821a1ant_media_status_notify(IN struct btc_coexist *btcoexist,
+		IN u8 type)
+{
+	u8			h2c_parameter[3] = {0};
+	u32			wifi_bw;
+	u8			wifi_central_chnl;
+	boolean	wifi_under_5g = false;
+
+	if (btcoexist->manual_control ||
+	    btcoexist->stop_coex_dm ||
+	    coex_sta->bt_disabled)
+		return;
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_5G, &wifi_under_5g);
+	if (wifi_under_5g) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			"[BTCoex], RunCoexistMechanism(), return for 5G <===\n");
+		BTC_TRACE(trace_buf);
+		halbtc8821a1ant_coex_under_5g(btcoexist);
+		return;
+	}
+
+	if (BTC_MEDIA_CONNECT == type) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], MEDIA connect notify\n");
+		BTC_TRACE(trace_buf);
+	} else {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], MEDIA disconnect notify\n");
+		BTC_TRACE(trace_buf);
+		coex_dm->arp_cnt = 0;
+	}
+
+	/* only 2.4G we need to inform bt the chnl mask */
+	btcoexist->btc_get(btcoexist, BTC_GET_U1_WIFI_CENTRAL_CHNL,
+			   &wifi_central_chnl);
+	if ((BTC_MEDIA_CONNECT == type) &&
+	    (wifi_central_chnl <= 14)) {
+		/* h2c_parameter[0] = 0x1; */
+		h2c_parameter[0] = 0x0;
+		h2c_parameter[1] = wifi_central_chnl;
+		btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw);
+		if (BTC_WIFI_BW_HT40 == wifi_bw)
+			h2c_parameter[2] = 0x30;
+		else
+			h2c_parameter[2] = 0x20;
+	}
+
+	coex_dm->wifi_chnl_info[0] = h2c_parameter[0];
+	coex_dm->wifi_chnl_info[1] = h2c_parameter[1];
+	coex_dm->wifi_chnl_info[2] = h2c_parameter[2];
+
+	btcoexist->btc_fill_h2c(btcoexist, 0x66, 3, h2c_parameter);
+}
+
+void ex_halbtc8821a1ant_specific_packet_notify(IN struct btc_coexist *btcoexist,
+		IN u8 type)
+{
+	boolean	bt_hs_on = false;
+	u32	wifi_link_status = 0;
+	u32	num_of_wifi_link = 0;
+	boolean	bt_ctrl_agg_buf_size = false;
+	u8	agg_buf_size = 5;
+	boolean	wifi_under_5g = false;
+
+	if (btcoexist->manual_control ||
+	    btcoexist->stop_coex_dm ||
+	    coex_sta->bt_disabled)
+		return;
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_5G, &wifi_under_5g);
+	if (wifi_under_5g) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			"[BTCoex], RunCoexistMechanism(), return for 5G <===\n");
+		BTC_TRACE(trace_buf);
+		halbtc8821a1ant_coex_under_5g(btcoexist);
+		return;
+	}
+
+	if (BTC_PACKET_DHCP == type ||
+	    BTC_PACKET_EAPOL == type ||
+	    BTC_PACKET_ARP == type) {
+		coex_sta->wifi_is_high_pri_task = true;
+
+		if (BTC_PACKET_ARP == type) {
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				    "[BTCoex], specific Packet ARP notify\n");
+			BTC_TRACE(trace_buf);
+		} else {
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				"[BTCoex], specific Packet DHCP or EAPOL notify\n");
+			BTC_TRACE(trace_buf);
+		}
+	} else {
+		coex_sta->wifi_is_high_pri_task = false;
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			"[BTCoex], specific Packet [Type = %d] notify\n", type);
+		BTC_TRACE(trace_buf);
+	}
+
+	coex_sta->specific_pkt_period_cnt = 0;
+
+	btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_LINK_STATUS,
+			   &wifi_link_status);
+	num_of_wifi_link = wifi_link_status >> 16;
+	if (num_of_wifi_link >= 2) {
+		halbtc8821a1ant_limited_tx(btcoexist, NORMAL_EXEC, 0, 0, 0, 0);
+		halbtc8821a1ant_limited_rx(btcoexist, NORMAL_EXEC, false,
+					   bt_ctrl_agg_buf_size, agg_buf_size);
+		halbtc8821a1ant_action_wifi_multi_port(btcoexist);
+		return;
+	}
+
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on);
+	if (coex_sta->c2h_bt_inquiry_page) {
+		halbtc8821a1ant_action_bt_inquiry(btcoexist);
+		return;
+	} else if (bt_hs_on) {
+		halbtc8821a1ant_action_hs(btcoexist);
+		return;
+	}
+
+	if (BTC_PACKET_DHCP == type ||
+	    BTC_PACKET_EAPOL == type ||
+	    BTC_PACKET_ARP == type) {
+		if (BTC_PACKET_ARP == type) {
+			coex_dm->arp_cnt++;
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				    "[BTCoex], ARP Packet Count = %d\n",
+				    coex_dm->arp_cnt);
+			BTC_TRACE(trace_buf);
+			if (coex_dm->arp_cnt >=
+			    10) /* if APR PKT > 10 after connect, do not go to ActionWifiConnectedSpecificPacket(btcoexist) */
+				return;
+		}
+
+		halbtc8821a1ant_action_wifi_connected_specific_packet(
+			btcoexist);
+	}
+}
+
+void ex_halbtc8821a1ant_bt_info_notify(IN struct btc_coexist *btcoexist,
+				       IN u8 *tmp_buf, IN u8 length)
+{
+	u8				bt_info = 0;
+	u8				i, rsp_source = 0;
+	boolean				wifi_connected = false;
+	boolean				bt_busy = false;
+	boolean				wifi_under_5g = false;
+
+
+	coex_sta->c2h_bt_info_req_sent = false;
+
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_5G, &wifi_under_5g);
+
+	rsp_source = tmp_buf[0] & 0xf;
+	if (rsp_source >= BT_INFO_SRC_8821A_1ANT_MAX)
+		rsp_source = BT_INFO_SRC_8821A_1ANT_WIFI_FW;
+	coex_sta->bt_info_c2h_cnt[rsp_source]++;
+
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+		    "[BTCoex], Bt info[%d], length=%d, hex data=[", rsp_source,
+		    length);
+	BTC_TRACE(trace_buf);
+	for (i = 0; i < length; i++) {
+		coex_sta->bt_info_c2h[rsp_source][i] = tmp_buf[i];
+		if (i == 1)
+			bt_info = tmp_buf[i];
+		if (i == length - 1) {
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "0x%02x]\n",
+				    tmp_buf[i]);
+			BTC_TRACE(trace_buf);
+		} else {
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "0x%02x, ",
+				    tmp_buf[i]);
+			BTC_TRACE(trace_buf);
+		}
+	}
+	/* if 0xff, it means BT is under WHCK test */
+	if (bt_info == 0xff)
+		coex_sta->bt_whck_test = true;
+	else
+		coex_sta->bt_whck_test = false;
+
+	if (BT_INFO_SRC_8821A_1ANT_WIFI_FW != rsp_source) {
+		coex_sta->bt_retry_cnt =	/* [3:0] */
+			coex_sta->bt_info_c2h[rsp_source][2] & 0xf;
+
+		if (coex_sta->bt_info_c2h[rsp_source][2] & 0x20)
+			coex_sta->c2h_bt_page = true;
+		else
+			coex_sta->c2h_bt_page = false;
+
+		coex_sta->bt_rssi =
+			coex_sta->bt_info_c2h[rsp_source][3] * 2 + 10;
+
+		coex_sta->bt_info_ext =
+			coex_sta->bt_info_c2h[rsp_source][4];
+
+		coex_sta->bt_tx_rx_mask = (coex_sta->bt_info_c2h[rsp_source][2]
+					   & 0x40);
+		btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_TX_RX_MASK,
+				   &coex_sta->bt_tx_rx_mask);
+		if (!coex_sta->bt_tx_rx_mask) {
+			/* BT into is responded by BT FW and BT RF REG 0x3C != 0x15 => Need to switch BT TRx Mask */
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				"[BTCoex], Switch BT TRx Mask since BT RF REG 0x3C != 0x15\n");
+			BTC_TRACE(trace_buf);
+			btcoexist->btc_set_bt_reg(btcoexist, BTC_BT_REG_RF,
+						  0x3c, 0x15);
+		}
+
+		/* Here we need to resend some wifi info to BT */
+		/* because bt is reset and loss of the info. */
+		if (coex_sta->bt_info_ext & BIT(1)) {
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				"[BTCoex], BT ext info bit1 check, send wifi BW&Chnl to BT!!\n");
+			BTC_TRACE(trace_buf);
+			btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED,
+					   &wifi_connected);
+			if (wifi_connected)
+				ex_halbtc8821a1ant_media_status_notify(
+					btcoexist, BTC_MEDIA_CONNECT);
+			else
+				ex_halbtc8821a1ant_media_status_notify(
+					btcoexist, BTC_MEDIA_DISCONNECT);
+		}
+
+		if ((coex_sta->bt_info_ext & BIT(3)) && !wifi_under_5g) {
+			if (!btcoexist->manual_control &&
+			    !btcoexist->stop_coex_dm) {
+				BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+					"[BTCoex], BT ext info bit3 check, set BT NOT to ignore Wlan active!!\n");
+				BTC_TRACE(trace_buf);
+				halbtc8821a1ant_ignore_wlan_act(btcoexist,
+							FORCE_EXEC, false);
+			}
+		} else {
+			/* BT already NOT ignore Wlan active, do nothing here. */
+		}
+#if (BT_AUTO_REPORT_ONLY_8821A_1ANT == 0)
+		if ((coex_sta->bt_info_ext & BIT(4))) {
+			/* BT auto report already enabled, do nothing */
+		} else
+			halbtc8821a1ant_bt_auto_report(btcoexist, FORCE_EXEC,
+						       true);
+#endif
+	}
+
+	/* check BIT2 first ==> check if bt is under inquiry or page scan */
+	if (bt_info & BT_INFO_8821A_1ANT_B_INQ_PAGE)
+		coex_sta->c2h_bt_inquiry_page = true;
+	else
+		coex_sta->c2h_bt_inquiry_page = false;
+
+	/* set link exist status */
+	if (!(bt_info & BT_INFO_8821A_1ANT_B_CONNECTION)) {
+		coex_sta->bt_link_exist = false;
+		coex_sta->pan_exist = false;
+		coex_sta->a2dp_exist = false;
+		coex_sta->hid_exist = false;
+		coex_sta->sco_exist = false;
+	} else {	/* connection exists */
+		coex_sta->bt_link_exist = true;
+		if (bt_info & BT_INFO_8821A_1ANT_B_FTP)
+			coex_sta->pan_exist = true;
+		else
+			coex_sta->pan_exist = false;
+		if (bt_info & BT_INFO_8821A_1ANT_B_A2DP)
+			coex_sta->a2dp_exist = true;
+		else
+			coex_sta->a2dp_exist = false;
+		if (bt_info & BT_INFO_8821A_1ANT_B_HID)
+			coex_sta->hid_exist = true;
+		else
+			coex_sta->hid_exist = false;
+		if (bt_info & BT_INFO_8821A_1ANT_B_SCO_ESCO)
+			coex_sta->sco_exist = true;
+		else
+			coex_sta->sco_exist = false;
+	}
+
+	halbtc8821a1ant_update_bt_link_info(btcoexist);
+
+	bt_info = bt_info &
+		0x1f;  /* mask profile bit for connect-ilde identification ( for CSR case: A2DP idle --> 0x41) */
+
+	if (!(bt_info & BT_INFO_8821A_1ANT_B_CONNECTION)) {
+		coex_dm->bt_status = BT_8821A_1ANT_BT_STATUS_NON_CONNECTED_IDLE;
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			"[BTCoex], BtInfoNotify(), BT Non-Connected idle!!!\n");
+		BTC_TRACE(trace_buf);
+	} else if (bt_info ==
+		BT_INFO_8821A_1ANT_B_CONNECTION) {	/* connection exists but no busy */
+		coex_dm->bt_status = BT_8821A_1ANT_BT_STATUS_CONNECTED_IDLE;
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], BtInfoNotify(), BT Connected-idle!!!\n");
+		BTC_TRACE(trace_buf);
+	} else if ((bt_info & BT_INFO_8821A_1ANT_B_SCO_ESCO) ||
+		   (bt_info & BT_INFO_8821A_1ANT_B_SCO_BUSY)) {
+		coex_dm->bt_status = BT_8821A_1ANT_BT_STATUS_SCO_BUSY;
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], BtInfoNotify(), BT SCO busy!!!\n");
+		BTC_TRACE(trace_buf);
+	} else if (bt_info & BT_INFO_8821A_1ANT_B_ACL_BUSY) {
+		if (BT_8821A_1ANT_BT_STATUS_ACL_BUSY != coex_dm->bt_status)
+			coex_dm->auto_tdma_adjust = false;
+		coex_dm->bt_status = BT_8821A_1ANT_BT_STATUS_ACL_BUSY;
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], BtInfoNotify(), BT ACL busy!!!\n");
+		BTC_TRACE(trace_buf);
+	} else {
+		coex_dm->bt_status = BT_8821A_1ANT_BT_STATUS_MAX;
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			"[BTCoex], BtInfoNotify(), BT Non-Defined state!!!\n");
+		BTC_TRACE(trace_buf);
+	}
+
+	if ((BT_8821A_1ANT_BT_STATUS_ACL_BUSY == coex_dm->bt_status) ||
+	    (BT_8821A_1ANT_BT_STATUS_SCO_BUSY == coex_dm->bt_status) ||
+	    (BT_8821A_1ANT_BT_STATUS_ACL_SCO_BUSY == coex_dm->bt_status))
+		bt_busy = true;
+	else
+		bt_busy = false;
+	btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_TRAFFIC_BUSY, &bt_busy);
+
+	halbtc8821a1ant_run_coexist_mechanism(btcoexist);
+}
+
+void ex_halbtc8821a1ant_halt_notify(IN struct btc_coexist *btcoexist)
+{
+	boolean	wifi_under_5g = false;
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_5G, &wifi_under_5g);
+	if (wifi_under_5g) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			"[BTCoex], RunCoexistMechanism(), return for 5G <===\n");
+		BTC_TRACE(trace_buf);
+		halbtc8821a1ant_coex_under_5g(btcoexist);
+		return;
+	}
+
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], Halt notify\n");
+	BTC_TRACE(trace_buf);
+
+	halbtc8821a1ant_ps_tdma(btcoexist, FORCE_EXEC, false, 0);
+	halbtc8821a1ant_set_ant_path(btcoexist, BTC_ANT_PATH_BT, false, true);
+	/* halbtc8821a1ant_set_ant_path_d_cut(btcoexist, false, false, false, BTC_ANT_PATH_BT, BTC_WIFI_STAT_NORMAL_OFF); */
+
+	halbtc8821a1ant_ignore_wlan_act(btcoexist, FORCE_EXEC, true);
+
+	ex_halbtc8821a1ant_media_status_notify(btcoexist, BTC_MEDIA_DISCONNECT);
+
+	btcoexist->stop_coex_dm = true;
+}
+
+void ex_halbtc8821a1ant_pnp_notify(IN struct btc_coexist *btcoexist,
+				   IN u8 pnp_state)
+{
+	boolean wifi_under_5g = false;
+
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_5G, &wifi_under_5g);
+	if (wifi_under_5g) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			"[BTCoex], RunCoexistMechanism(), return for 5G <===\n");
+		BTC_TRACE(trace_buf);
+		halbtc8821a1ant_coex_under_5g(btcoexist);
+		return;
+	}
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], Pnp notify\n");
+	BTC_TRACE(trace_buf);
+
+	if (BTC_WIFI_PNP_SLEEP == pnp_state) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], Pnp notify to SLEEP\n");
+		BTC_TRACE(trace_buf);
+
+		halbtc8821a1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 0);
+		halbtc8821a1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 2);
+		halbtc8821a1ant_set_ant_path(btcoexist, BTC_ANT_PATH_BT, false,
+					     true);
+		/* halbtc8821a1ant_set_ant_path_d_cut(btcoexist, false, false, false, BTC_ANT_PATH_BT, BTC_WIFI_STAT_NORMAL_OFF); */
+
+		/* Sinda 20150819, workaround for driver skip leave IPS/LPS to speed up sleep time. */
+		/* Driver do not leave IPS/LPS when driver is going to sleep, so BTCoexistence think wifi is still under IPS/LPS */
+		/* BT should clear UnderIPS/UnderLPS state to avoid mismatch state after wakeup. */
+		coex_sta->under_ips = false;
+		coex_sta->under_lps = false;
+		btcoexist->stop_coex_dm = true;
+	} else if (BTC_WIFI_PNP_WAKE_UP == pnp_state) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], Pnp notify to WAKE UP\n");
+		BTC_TRACE(trace_buf);
+		btcoexist->stop_coex_dm = false;
+		halbtc8821a1ant_init_hw_config(btcoexist, false, false);
+		halbtc8821a1ant_init_coex_dm(btcoexist);
+		halbtc8821a1ant_query_bt_info(btcoexist);
+	}
+}
+
+void ex_halbtc8821a1ant_periodical(IN struct btc_coexist *btcoexist)
+{
+	u32 bt_patch_ver;
+
+	if (((coex_sta->bt_coex_supported_version == 0) ||
+	     (coex_sta->bt_coex_supported_version == 0xffff)) && (!coex_sta->bt_disabled))
+		btcoexist->btc_get(btcoexist, BTC_GET_U4_SUPPORTED_VERSION, &coex_sta->bt_coex_supported_version);
+
+	btcoexist->btc_get(btcoexist, BTC_GET_U4_BT_PATCH_VER, &bt_patch_ver);
+	btcoexist->bt_info.bt_get_fw_ver = bt_patch_ver;
+
+#if (BT_AUTO_REPORT_ONLY_8821A_1ANT == 0)
+	halbtc8821a1ant_query_bt_info(btcoexist);
+	halbtc8821a1ant_monitor_bt_enable_disable(btcoexist);
+#else
+	halbtc8821a1ant_monitor_bt_ctr(btcoexist);
+	halbtc8821a1ant_monitor_wifi_ctr(btcoexist);
+	halbtc8821a1ant_monitor_bt_enable_disable(btcoexist);
+	if (halbtc8821a1ant_is_wifi_status_changed(btcoexist) ||
+	    coex_dm->auto_tdma_adjust) {
+		/* if(coex_sta->specific_pkt_period_cnt > 2) */
+		/* { */
+		halbtc8821a1ant_run_coexist_mechanism(btcoexist);
+		/* } */
+	}
+
+	coex_sta->specific_pkt_period_cnt++;
+#endif
+}
+
+#endif
+
+#endif	/* #if (BT_SUPPORT == 1 && COEX_SUPPORT == 1) */
+
+
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/btc/halbtc8821a1ant.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/btc/halbtc8821a1ant.h
--- linux-5.6.3/3rdparty/rtl8821ce/hal/btc/halbtc8821a1ant.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/btc/halbtc8821a1ant.h	2020-04-10 16:35:06.784658573 +0300
@@ -0,0 +1,214 @@
+
+#if (BT_SUPPORT == 1 && COEX_SUPPORT == 1)
+
+#if (RTL8821A_SUPPORT == 1)
+
+/* *******************************************
+ * The following is for 8821A 1ANT BT Co-exist definition
+ * ******************************************* */
+#define	BT_AUTO_REPORT_ONLY_8821A_1ANT				1
+
+#define	BT_INFO_8821A_1ANT_B_FTP						BIT(7)
+#define	BT_INFO_8821A_1ANT_B_A2DP					BIT(6)
+#define	BT_INFO_8821A_1ANT_B_HID						BIT(5)
+#define	BT_INFO_8821A_1ANT_B_SCO_BUSY				BIT(4)
+#define	BT_INFO_8821A_1ANT_B_ACL_BUSY				BIT(3)
+#define	BT_INFO_8821A_1ANT_B_INQ_PAGE				BIT(2)
+#define	BT_INFO_8821A_1ANT_B_SCO_ESCO				BIT(1)
+#define	BT_INFO_8821A_1ANT_B_CONNECTION				BIT(0)
+
+#define	BT_INFO_8821A_1ANT_A2DP_BASIC_RATE(_BT_INFO_EXT_)	\
+		(((_BT_INFO_EXT_&BIT(0))) ? true : false)
+
+#define	BTC_RSSI_COEX_THRESH_TOL_8821A_1ANT		2
+
+enum bt_info_src_8821a_1ant {
+	BT_INFO_SRC_8821A_1ANT_WIFI_FW			= 0x0,
+	BT_INFO_SRC_8821A_1ANT_BT_RSP				= 0x1,
+	BT_INFO_SRC_8821A_1ANT_BT_ACTIVE_SEND		= 0x2,
+	BT_INFO_SRC_8821A_1ANT_MAX
+};
+
+enum bt_8821a_1ant_bt_status {
+	BT_8821A_1ANT_BT_STATUS_NON_CONNECTED_IDLE	= 0x0,
+	BT_8821A_1ANT_BT_STATUS_CONNECTED_IDLE		= 0x1,
+	BT_8821A_1ANT_BT_STATUS_INQ_PAGE				= 0x2,
+	BT_8821A_1ANT_BT_STATUS_ACL_BUSY				= 0x3,
+	BT_8821A_1ANT_BT_STATUS_SCO_BUSY				= 0x4,
+	BT_8821A_1ANT_BT_STATUS_ACL_SCO_BUSY			= 0x5,
+	BT_8821A_1ANT_BT_STATUS_MAX
+};
+
+enum bt_8821a_1ant_wifi_status {
+	BT_8821A_1ANT_WIFI_STATUS_NON_CONNECTED_IDLE				= 0x0,
+	BT_8821A_1ANT_WIFI_STATUS_NON_CONNECTED_ASSO_AUTH_SCAN		= 0x1,
+	BT_8821A_1ANT_WIFI_STATUS_CONNECTED_SCAN					= 0x2,
+	BT_8821A_1ANT_WIFI_STATUS_CONNECTED_SPECIFIC_PKT				= 0x3,
+	BT_8821A_1ANT_WIFI_STATUS_CONNECTED_IDLE					= 0x4,
+	BT_8821A_1ANT_WIFI_STATUS_CONNECTED_BUSY					= 0x5,
+	BT_8821A_1ANT_WIFI_STATUS_MAX
+};
+
+enum bt_8821a_1ant_coex_algo {
+	BT_8821A_1ANT_COEX_ALGO_UNDEFINED			= 0x0,
+	BT_8821A_1ANT_COEX_ALGO_SCO				= 0x1,
+	BT_8821A_1ANT_COEX_ALGO_HID				= 0x2,
+	BT_8821A_1ANT_COEX_ALGO_A2DP				= 0x3,
+	BT_8821A_1ANT_COEX_ALGO_A2DP_PANHS		= 0x4,
+	BT_8821A_1ANT_COEX_ALGO_PANEDR			= 0x5,
+	BT_8821A_1ANT_COEX_ALGO_PANHS			= 0x6,
+	BT_8821A_1ANT_COEX_ALGO_PANEDR_A2DP		= 0x7,
+	BT_8821A_1ANT_COEX_ALGO_PANEDR_HID		= 0x8,
+	BT_8821A_1ANT_COEX_ALGO_HID_A2DP_PANEDR	= 0x9,
+	BT_8821A_1ANT_COEX_ALGO_HID_A2DP			= 0xa,
+	BT_8821A_1ANT_COEX_ALGO_MAX				= 0xb,
+};
+
+struct coex_dm_8821a_1ant {
+	/* fw mechanism */
+	boolean		cur_ignore_wlan_act;
+	boolean		pre_ignore_wlan_act;
+	u8		pre_ps_tdma;
+	u8		cur_ps_tdma;
+	u8		ps_tdma_para[5];
+	u8		ps_tdma_du_adj_type;
+	boolean		auto_tdma_adjust;
+	boolean		pre_ps_tdma_on;
+	boolean		cur_ps_tdma_on;
+	boolean		pre_bt_auto_report;
+	boolean		cur_bt_auto_report;
+	u8		pre_lps;
+	u8		cur_lps;
+	u8		pre_rpwm;
+	u8		cur_rpwm;
+
+	/* sw mechanism */
+	boolean	pre_low_penalty_ra;
+	boolean		cur_low_penalty_ra;
+	u32		pre_val0x6c0;
+	u32		cur_val0x6c0;
+	u32		pre_val0x6c4;
+	u32		cur_val0x6c4;
+	u32		pre_val0x6c8;
+	u32		cur_val0x6c8;
+	u8		pre_val0x6cc;
+	u8		cur_val0x6cc;
+
+	u32		backup_arfr_cnt1;	/* Auto Rate Fallback Retry cnt */
+	u32		backup_arfr_cnt2;	/* Auto Rate Fallback Retry cnt */
+	u16		backup_retry_limit;
+	u8		backup_ampdu_max_time;
+
+	/* algorithm related */
+	u8		pre_algorithm;
+	u8		cur_algorithm;
+	u8		bt_status;
+	u8		wifi_chnl_info[3];
+
+	u32		pre_ra_mask;
+	u32		cur_ra_mask;
+	u8		pre_arfr_type;
+	u8		cur_arfr_type;
+	u8		pre_retry_limit_type;
+	u8		cur_retry_limit_type;
+	u8		pre_ampdu_time_type;
+	u8		cur_ampdu_time_type;
+	u32		arp_cnt;
+
+	u8		error_condition;
+};
+
+struct coex_sta_8821a_1ant {
+	boolean					bt_disabled;
+	boolean					bt_link_exist;
+	boolean					sco_exist;
+	boolean					a2dp_exist;
+	boolean					hid_exist;
+	boolean					pan_exist;
+
+	boolean					under_lps;
+	boolean					under_ips;
+	u32					specific_pkt_period_cnt;
+	u32					high_priority_tx;
+	u32					high_priority_rx;
+	u32					low_priority_tx;
+	u32					low_priority_rx;
+
+	u32					crc_ok_cck;
+	u32					crc_ok_11g;
+	u32					crc_ok_11n;
+	u32					crc_ok_11n_vht;
+
+	u32					crc_err_cck;
+	u32					crc_err_11g;
+	u32					crc_err_11n;
+	u32					crc_err_11n_vht;
+
+	u32					bt_coex_supported_version;
+	u8					cut_version;
+	u8					bt_rssi;
+	u8					scan_ap_num;
+	boolean					bt_tx_rx_mask;
+	u8					pre_bt_rssi_state;
+	u8					pre_wifi_rssi_state[4];
+	boolean					c2h_bt_info_req_sent;
+	u8					bt_info_c2h[BT_INFO_SRC_8821A_1ANT_MAX][10];
+	u32					bt_info_c2h_cnt[BT_INFO_SRC_8821A_1ANT_MAX];
+	boolean					c2h_bt_inquiry_page;
+	boolean					c2h_bt_page;				/* Add for win8.1 page out issue */
+	boolean					wifi_is_high_pri_task;		/* Add for win8.1 page out issue */
+	u8					bt_retry_cnt;
+	u8					bt_info_ext;
+	boolean				bt_whck_test;	/* Add for ASUS WHQL TEST that enable wifi test bt */
+};
+
+/* *******************************************
+ * The following is interface which will notify coex module.
+ * ******************************************* */
+void ex_halbtc8821a1ant_power_on_setting(IN struct btc_coexist *btcoexist);
+void ex_halbtc8821a1ant_init_hw_config(IN struct btc_coexist *btcoexist,
+				       IN boolean wifi_only);
+void ex_halbtc8821a1ant_init_coex_dm(IN struct btc_coexist *btcoexist);
+void ex_halbtc8821a1ant_ips_notify(IN struct btc_coexist *btcoexist,
+				   IN u8 type);
+void ex_halbtc8821a1ant_lps_notify(IN struct btc_coexist *btcoexist,
+				   IN u8 type);
+void ex_halbtc8821a1ant_scan_notify(IN struct btc_coexist *btcoexist,
+				    IN u8 type);
+void ex_halbtc8821a1ant_switchband_notify(IN struct btc_coexist *btcoexist,
+		IN u8 type);
+void ex_halbtc8821a1ant_connect_notify(IN struct btc_coexist *btcoexist,
+				       IN u8 type);
+void ex_halbtc8821a1ant_media_status_notify(IN struct btc_coexist *btcoexist,
+		IN u8 type);
+void ex_halbtc8821a1ant_specific_packet_notify(IN struct btc_coexist *btcoexist,
+		IN u8 type);
+void ex_halbtc8821a1ant_bt_info_notify(IN struct btc_coexist *btcoexist,
+				       IN u8 *tmp_buf, IN u8 length);
+void ex_halbtc8821a1ant_halt_notify(IN struct btc_coexist *btcoexist);
+void ex_halbtc8821a1ant_pnp_notify(IN struct btc_coexist *btcoexist,
+				   IN u8 pnp_state);
+void ex_halbtc8821a1ant_periodical(IN struct btc_coexist *btcoexist);
+void ex_halbtc8821a1ant_display_coex_info(IN struct btc_coexist *btcoexist);
+
+#else
+#define	ex_halbtc8821a1ant_power_on_setting(btcoexist)
+#define	ex_halbtc8821a1ant_init_hw_config(btcoexist, wifi_only)
+#define	ex_halbtc8821a1ant_init_coex_dm(btcoexist)
+#define	ex_halbtc8821a1ant_ips_notify(btcoexist, type)
+#define	ex_halbtc8821a1ant_lps_notify(btcoexist, type)
+#define	ex_halbtc8821a1ant_scan_notify(btcoexist, type)
+#define	ex_halbtc8821a1ant_switchband_notify(btcoexist, type)
+#define	ex_halbtc8821a1ant_connect_notify(btcoexist, type)
+#define	ex_halbtc8821a1ant_media_status_notify(btcoexist, type)
+#define	ex_halbtc8821a1ant_specific_packet_notify(btcoexist, type)
+#define	ex_halbtc8821a1ant_bt_info_notify(btcoexist, tmp_buf, length)
+#define	ex_halbtc8821a1ant_halt_notify(btcoexist)
+#define	ex_halbtc8821a1ant_pnp_notify(btcoexist, pnp_state)
+#define	ex_halbtc8821a1ant_periodical(btcoexist)
+#define	ex_halbtc8821a1ant_display_coex_info(btcoexist)
+
+#endif
+
+#endif
+
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/btc/halbtc8821a2ant.c linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/btc/halbtc8821a2ant.c
--- linux-5.6.3/3rdparty/rtl8821ce/hal/btc/halbtc8821a2ant.c	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/btc/halbtc8821a2ant.c	2020-04-10 16:35:06.784658573 +0300
@@ -0,0 +1,4584 @@
+/* ************************************************************
+ * Description:
+ *
+ * This file is for RTL8821A Co-exist mechanism
+ *
+ * History
+ * 2012/11/15 Cosa first check in.
+ *
+ * ************************************************************ */
+
+/* ************************************************************
+ * include files
+ * ************************************************************ */
+#include "mp_precomp.h"
+
+#if (BT_SUPPORT == 1 && COEX_SUPPORT == 1)
+
+#if (RTL8821A_SUPPORT == 1)
+/* ************************************************************
+ * Global variables, these are static variables
+ * ************************************************************ */
+static u8	 *trace_buf = &gl_btc_trace_buf[0];
+static struct  coex_dm_8821a_2ant		glcoex_dm_8821a_2ant;
+static struct  coex_dm_8821a_2ant	*coex_dm = &glcoex_dm_8821a_2ant;
+static struct  coex_sta_8821a_2ant		glcoex_sta_8821a_2ant;
+static struct  coex_sta_8821a_2ant	*coex_sta = &glcoex_sta_8821a_2ant;
+
+const char *const glbt_info_src_8821a_2ant[] = {
+	"BT Info[wifi fw]",
+	"BT Info[bt rsp]",
+	"BT Info[bt auto report]",
+};
+
+u32	glcoex_ver_date_8821a_2ant = 20161128;
+u32	glcoex_ver_8821a_2ant = 0x60;
+u32	glcoex_ver_btdesired_8821a_2ant = 0x5c;
+
+/* modify 20140903v43 a2dpandhid tdmaonoff a2dp glitch _ tdma off 778=3(case1)->778=1(case0)
+ * and to improve tp while a2dphid case23->case25 , case123->case125 for asus spec
+ * and modify for asus bt WHQL test _ tdma off_ 778=3->1_
+ * ************************************************************
+ * local function proto type if needed
+ * ************************************************************
+ * ************************************************************
+ * local function start with halbtc8821a2ant_
+ * ************************************************************ */
+u8 halbtc8821a2ant_bt_rssi_state(u8 level_num, u8 rssi_thresh, u8 rssi_thresh1)
+{
+	s32			bt_rssi = 0;
+	u8			bt_rssi_state = coex_sta->pre_bt_rssi_state;
+
+	bt_rssi = coex_sta->bt_rssi;
+
+	if (level_num == 2) {
+		if ((coex_sta->pre_bt_rssi_state == BTC_RSSI_STATE_LOW) ||
+		    (coex_sta->pre_bt_rssi_state ==
+		     BTC_RSSI_STATE_STAY_LOW)) {
+			if (bt_rssi >= (rssi_thresh +
+					BTC_RSSI_COEX_THRESH_TOL_8821A_2ANT))
+				bt_rssi_state = BTC_RSSI_STATE_HIGH;
+			else
+				bt_rssi_state = BTC_RSSI_STATE_STAY_LOW;
+		} else {
+			if (bt_rssi < rssi_thresh)
+				bt_rssi_state = BTC_RSSI_STATE_LOW;
+			else
+				bt_rssi_state = BTC_RSSI_STATE_STAY_HIGH;
+		}
+	} else if (level_num == 3) {
+		if (rssi_thresh > rssi_thresh1) {
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				    "[BTCoex], BT Rssi thresh error!!\n");
+			BTC_TRACE(trace_buf);
+			return coex_sta->pre_bt_rssi_state;
+		}
+
+		if ((coex_sta->pre_bt_rssi_state == BTC_RSSI_STATE_LOW) ||
+		    (coex_sta->pre_bt_rssi_state ==
+		     BTC_RSSI_STATE_STAY_LOW)) {
+			if (bt_rssi >= (rssi_thresh +
+					BTC_RSSI_COEX_THRESH_TOL_8821A_2ANT))
+				bt_rssi_state = BTC_RSSI_STATE_MEDIUM;
+			else
+				bt_rssi_state = BTC_RSSI_STATE_STAY_LOW;
+		} else if ((coex_sta->pre_bt_rssi_state ==
+			    BTC_RSSI_STATE_MEDIUM) ||
+			   (coex_sta->pre_bt_rssi_state ==
+			    BTC_RSSI_STATE_STAY_MEDIUM)) {
+			if (bt_rssi >= (rssi_thresh1 +
+					BTC_RSSI_COEX_THRESH_TOL_8821A_2ANT))
+				bt_rssi_state = BTC_RSSI_STATE_HIGH;
+			else if (bt_rssi < rssi_thresh)
+				bt_rssi_state = BTC_RSSI_STATE_LOW;
+			else
+				bt_rssi_state = BTC_RSSI_STATE_STAY_MEDIUM;
+		} else {
+			if (bt_rssi < rssi_thresh1)
+				bt_rssi_state = BTC_RSSI_STATE_MEDIUM;
+			else
+				bt_rssi_state = BTC_RSSI_STATE_STAY_HIGH;
+		}
+	}
+
+	coex_sta->pre_bt_rssi_state = bt_rssi_state;
+
+	return bt_rssi_state;
+}
+
+u8 halbtc8821a2ant_wifi_rssi_state(IN struct btc_coexist *btcoexist,
+	   IN u8 index, IN u8 level_num, IN u8 rssi_thresh, IN u8 rssi_thresh1)
+{
+	s32			wifi_rssi = 0;
+	u8			wifi_rssi_state = coex_sta->pre_wifi_rssi_state[index];
+
+	btcoexist->btc_get(btcoexist, BTC_GET_S4_WIFI_RSSI, &wifi_rssi);
+
+	if (level_num == 2) {
+		if ((coex_sta->pre_wifi_rssi_state[index] == BTC_RSSI_STATE_LOW)
+		    ||
+		    (coex_sta->pre_wifi_rssi_state[index] ==
+		     BTC_RSSI_STATE_STAY_LOW)) {
+			if (wifi_rssi >= (rssi_thresh +
+					  BTC_RSSI_COEX_THRESH_TOL_8821A_2ANT))
+				wifi_rssi_state = BTC_RSSI_STATE_HIGH;
+			else
+				wifi_rssi_state = BTC_RSSI_STATE_STAY_LOW;
+		} else {
+			if (wifi_rssi < rssi_thresh)
+				wifi_rssi_state = BTC_RSSI_STATE_LOW;
+			else
+				wifi_rssi_state = BTC_RSSI_STATE_STAY_HIGH;
+		}
+	} else if (level_num == 3) {
+		if (rssi_thresh > rssi_thresh1) {
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				    "[BTCoex], wifi RSSI thresh error!!\n");
+			BTC_TRACE(trace_buf);
+			return coex_sta->pre_wifi_rssi_state[index];
+		}
+
+		if ((coex_sta->pre_wifi_rssi_state[index] == BTC_RSSI_STATE_LOW)
+		    ||
+		    (coex_sta->pre_wifi_rssi_state[index] ==
+		     BTC_RSSI_STATE_STAY_LOW)) {
+			if (wifi_rssi >= (rssi_thresh +
+					  BTC_RSSI_COEX_THRESH_TOL_8821A_2ANT))
+				wifi_rssi_state = BTC_RSSI_STATE_MEDIUM;
+			else
+				wifi_rssi_state = BTC_RSSI_STATE_STAY_LOW;
+		} else if ((coex_sta->pre_wifi_rssi_state[index] ==
+			    BTC_RSSI_STATE_MEDIUM) ||
+			   (coex_sta->pre_wifi_rssi_state[index] ==
+			    BTC_RSSI_STATE_STAY_MEDIUM)) {
+			if (wifi_rssi >= (rssi_thresh1 +
+					  BTC_RSSI_COEX_THRESH_TOL_8821A_2ANT))
+				wifi_rssi_state = BTC_RSSI_STATE_HIGH;
+			else if (wifi_rssi < rssi_thresh)
+				wifi_rssi_state = BTC_RSSI_STATE_LOW;
+			else
+				wifi_rssi_state = BTC_RSSI_STATE_STAY_MEDIUM;
+		} else {
+			if (wifi_rssi < rssi_thresh1)
+				wifi_rssi_state = BTC_RSSI_STATE_MEDIUM;
+			else
+				wifi_rssi_state = BTC_RSSI_STATE_STAY_HIGH;
+		}
+	}
+
+	coex_sta->pre_wifi_rssi_state[index] = wifi_rssi_state;
+
+	return wifi_rssi_state;
+}
+
+
+void halbtc8821a2ant_limited_rx(IN struct btc_coexist *btcoexist,
+			IN boolean force_exec, IN boolean rej_ap_agg_pkt,
+			IN boolean bt_ctrl_agg_buf_size, IN u8 agg_buf_size)
+{
+	boolean	reject_rx_agg = rej_ap_agg_pkt;
+	boolean	bt_ctrl_rx_agg_size = bt_ctrl_agg_buf_size;
+	u8	rx_agg_size = agg_buf_size;
+
+	/* ============================================ */
+	/*	Rx Aggregation related setting */
+	/* ============================================ */
+	btcoexist->btc_set(btcoexist, BTC_SET_BL_TO_REJ_AP_AGG_PKT,
+			   &reject_rx_agg);
+	/* decide BT control aggregation buf size or not */
+	btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_CTRL_AGG_SIZE,
+			   &bt_ctrl_rx_agg_size);
+	/* aggregation buf size, only work when BT control Rx aggregation size. */
+	btcoexist->btc_set(btcoexist, BTC_SET_U1_AGG_BUF_SIZE, &rx_agg_size);
+	/* real update aggregation setting */
+	btcoexist->btc_set(btcoexist, BTC_SET_ACT_AGGREGATE_CTRL, NULL);
+}
+
+void halbtc8821a2ant_monitor_bt_ctr(IN struct btc_coexist *btcoexist)
+{
+	u32			reg_hp_txrx, reg_lp_txrx, u32tmp;
+	u32			reg_hp_tx = 0, reg_hp_rx = 0, reg_lp_tx = 0, reg_lp_rx = 0;
+
+	struct  btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
+
+	reg_hp_txrx = 0x770;
+	reg_lp_txrx = 0x774;
+
+	u32tmp = btcoexist->btc_read_4byte(btcoexist, reg_hp_txrx);
+	reg_hp_tx = u32tmp & MASKLWORD;
+	reg_hp_rx = (u32tmp & MASKHWORD) >> 16;
+
+	u32tmp = btcoexist->btc_read_4byte(btcoexist, reg_lp_txrx);
+	reg_lp_tx = u32tmp & MASKLWORD;
+	reg_lp_rx = (u32tmp & MASKHWORD) >> 16;
+
+	coex_sta->high_priority_tx = reg_hp_tx;
+	coex_sta->high_priority_rx = reg_hp_rx;
+	coex_sta->low_priority_tx = reg_lp_tx;
+	coex_sta->low_priority_rx = reg_lp_rx;
+
+	if ((coex_sta->low_priority_rx >= 950)  &&
+	    (coex_sta->low_priority_rx >= coex_sta->low_priority_tx) &&
+	    (!coex_sta->under_ips))
+		bt_link_info->slave_role = true;
+	else
+		bt_link_info->slave_role = false;
+
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+		"[BTCoex], High Priority Tx/Rx (reg 0x%x)=0x%x(%d)/0x%x(%d)\n",
+		    reg_hp_txrx, reg_hp_tx, reg_hp_tx, reg_hp_rx, reg_hp_rx);
+	BTC_TRACE(trace_buf);
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+		"[BTCoex], Low Priority Tx/Rx (reg 0x%x)=0x%x(%d)/0x%x(%d)\n",
+		    reg_lp_txrx, reg_lp_tx, reg_lp_tx, reg_lp_rx, reg_lp_rx);
+	BTC_TRACE(trace_buf);
+
+	/* reset counter */
+	btcoexist->btc_write_1byte(btcoexist, 0x76e, 0xc);
+}
+
+void halbtc8821a2ant_monitor_wifi_ctr(IN struct btc_coexist *btcoexist)
+{
+#if 1
+
+	coex_sta->crc_ok_cck = btcoexist->btc_phydm_query_PHY_counter(
+				       btcoexist,
+				       PHYDM_INFO_CRC32_OK_CCK);
+	coex_sta->crc_ok_11g = btcoexist->btc_phydm_query_PHY_counter(
+				       btcoexist,
+				       PHYDM_INFO_CRC32_OK_LEGACY);
+	coex_sta->crc_ok_11n = btcoexist->btc_phydm_query_PHY_counter(
+				       btcoexist,
+				       PHYDM_INFO_CRC32_OK_HT);
+	coex_sta->crc_ok_11n_vht =
+		btcoexist->btc_phydm_query_PHY_counter(
+			btcoexist,
+			PHYDM_INFO_CRC32_OK_VHT);
+
+	coex_sta->crc_err_cck = btcoexist->btc_phydm_query_PHY_counter(
+					btcoexist,
+					PHYDM_INFO_CRC32_ERROR_CCK);
+	coex_sta->crc_err_11g =  btcoexist->btc_phydm_query_PHY_counter(
+					 btcoexist,
+					 PHYDM_INFO_CRC32_ERROR_LEGACY);
+	coex_sta->crc_err_11n = btcoexist->btc_phydm_query_PHY_counter(
+					btcoexist,
+					PHYDM_INFO_CRC32_ERROR_HT);
+	coex_sta->crc_err_11n_vht =
+		btcoexist->btc_phydm_query_PHY_counter(
+			btcoexist,
+			PHYDM_INFO_CRC32_ERROR_VHT);
+
+#endif
+}
+
+void halbtc8821a2ant_query_bt_info(IN struct btc_coexist *btcoexist)
+{
+	u8			h2c_parameter[1] = {0};
+
+	coex_sta->c2h_bt_info_req_sent = true;
+
+	h2c_parameter[0] |= BIT(0);	/* trigger */
+
+	btcoexist->btc_fill_h2c(btcoexist, 0x61, 1, h2c_parameter);
+}
+
+boolean halbtc8821a2ant_is_wifi_status_changed(IN struct btc_coexist *btcoexist)
+{
+	static boolean	pre_wifi_busy = false, pre_under_4way = false,
+			pre_bt_hs_on = false;
+	boolean			wifi_busy = false, under_4way = false, bt_hs_on = false;
+	boolean			wifi_connected = false;
+	u8			wifi_rssi_state = BTC_RSSI_STATE_HIGH;
+
+
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED,
+			   &wifi_connected);
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy);
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on);
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_4_WAY_PROGRESS,
+			   &under_4way);
+
+	if (wifi_connected) {
+		if (wifi_busy != pre_wifi_busy) {
+			pre_wifi_busy = wifi_busy;
+			return true;
+		}
+		if (under_4way != pre_under_4way) {
+			pre_under_4way = under_4way;
+			return true;
+		}
+		if (bt_hs_on != pre_bt_hs_on) {
+			pre_bt_hs_on = bt_hs_on;
+			return true;
+		}
+
+
+		wifi_rssi_state = halbtc8821a2ant_wifi_rssi_state(btcoexist, 3,
+			  2, BT_8821A_2ANT_WIFI_RSSI_COEXSWITCH_THRES, 0);
+
+		if ((BTC_RSSI_STATE_HIGH == wifi_rssi_state) ||
+		    (BTC_RSSI_STATE_LOW == wifi_rssi_state))
+			return true;
+
+	}
+
+	return false;
+}
+
+void halbtc8821a2ant_monitor_bt_enable_disable(IN struct btc_coexist *btcoexist)
+{
+	static u32	bt_disable_cnt = 0;
+	boolean			bt_active = true, bt_disabled = false;
+
+	/* This function check if bt is disabled */
+
+	if (coex_sta->high_priority_tx == 0 &&
+	    coex_sta->high_priority_rx == 0 &&
+	    coex_sta->low_priority_tx == 0 &&
+	    coex_sta->low_priority_rx == 0)
+		bt_active = false;
+	if (coex_sta->high_priority_tx == 0xffff &&
+	    coex_sta->high_priority_rx == 0xffff &&
+	    coex_sta->low_priority_tx == 0xffff &&
+	    coex_sta->low_priority_rx == 0xffff)
+		bt_active = false;
+	if (bt_active) {
+		bt_disable_cnt = 0;
+		bt_disabled = false;
+		btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_DISABLE,
+				   &bt_disabled);
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], BT is enabled !!\n");
+		BTC_TRACE(trace_buf);
+	} else {
+		bt_disable_cnt++;
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], bt all counters=0, %d times!!\n",
+			    bt_disable_cnt);
+		BTC_TRACE(trace_buf);
+		if (bt_disable_cnt >= 10) {
+			bt_disabled = true;
+			btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_DISABLE,
+					   &bt_disabled);
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				    "[BTCoex], BT is disabled !!\n");
+			BTC_TRACE(trace_buf);
+		}
+	}
+	if (coex_sta->bt_disabled != bt_disabled) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], BT is from %s to %s!!\n",
+			    (coex_sta->bt_disabled ? "disabled" : "enabled"),
+			    (bt_disabled ? "disabled" : "enabled"));
+		BTC_TRACE(trace_buf);
+		coex_sta->bt_disabled = bt_disabled;
+		/* if (!bt_disabled) {} else {} */
+	}
+}
+
+void halbtc8821a2ant_update_bt_link_info(IN struct btc_coexist *btcoexist)
+{
+	struct  btc_bt_link_info	*bt_link_info = &btcoexist->bt_link_info;
+	boolean				bt_hs_on = false;
+
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on);
+
+	bt_link_info->bt_link_exist = coex_sta->bt_link_exist;
+	bt_link_info->sco_exist = coex_sta->sco_exist;
+	bt_link_info->a2dp_exist = coex_sta->a2dp_exist;
+	bt_link_info->pan_exist = coex_sta->pan_exist;
+	bt_link_info->hid_exist = coex_sta->hid_exist;
+
+	/* work around for HS mode. */
+	if (bt_hs_on) {
+		bt_link_info->pan_exist = true;
+		bt_link_info->bt_link_exist = true;
+	}
+
+	/* check if Sco only */
+	if (bt_link_info->sco_exist &&
+	    !bt_link_info->a2dp_exist &&
+	    !bt_link_info->pan_exist &&
+	    !bt_link_info->hid_exist)
+		bt_link_info->sco_only = true;
+	else
+		bt_link_info->sco_only = false;
+
+	/* check if A2dp only */
+	if (!bt_link_info->sco_exist &&
+	    bt_link_info->a2dp_exist &&
+	    !bt_link_info->pan_exist &&
+	    !bt_link_info->hid_exist)
+		bt_link_info->a2dp_only = true;
+	else
+		bt_link_info->a2dp_only = false;
+
+	/* check if Pan only */
+	if (!bt_link_info->sco_exist &&
+	    !bt_link_info->a2dp_exist &&
+	    bt_link_info->pan_exist &&
+	    !bt_link_info->hid_exist)
+		bt_link_info->pan_only = true;
+	else
+		bt_link_info->pan_only = false;
+
+	/* check if Hid only */
+	if (!bt_link_info->sco_exist &&
+	    !bt_link_info->a2dp_exist &&
+	    !bt_link_info->pan_exist &&
+	    bt_link_info->hid_exist)
+		bt_link_info->hid_only = true;
+	else
+		bt_link_info->hid_only = false;
+}
+
+u8 halbtc8821a2ant_action_algorithm(IN struct btc_coexist *btcoexist)
+{
+	struct  btc_bt_link_info	*bt_link_info = &btcoexist->bt_link_info;
+	boolean				bt_hs_on = false;
+	u8				algorithm = BT_8821A_2ANT_COEX_ALGO_UNDEFINED;
+	u8				num_of_diff_profile = 0;
+
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on);
+
+	if (!bt_link_info->bt_link_exist) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], No BT link exists!!!\n");
+		BTC_TRACE(trace_buf);
+		return algorithm;
+	}
+
+	if (bt_link_info->sco_exist)
+		num_of_diff_profile++;
+	if (bt_link_info->hid_exist)
+		num_of_diff_profile++;
+	if (bt_link_info->pan_exist)
+		num_of_diff_profile++;
+	if (bt_link_info->a2dp_exist)
+		num_of_diff_profile++;
+
+	if (num_of_diff_profile == 1) {
+		if (bt_link_info->sco_exist) {
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				    "[BTCoex], SCO only\n");
+			BTC_TRACE(trace_buf);
+			algorithm = BT_8821A_2ANT_COEX_ALGO_SCO;
+		} else {
+			if (bt_link_info->hid_exist) {
+				BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+					    "[BTCoex], HID only\n");
+				BTC_TRACE(trace_buf);
+				algorithm = BT_8821A_2ANT_COEX_ALGO_HID;
+			} else if (bt_link_info->a2dp_exist) {
+				BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+					    "[BTCoex], A2DP only\n");
+				BTC_TRACE(trace_buf);
+				algorithm = BT_8821A_2ANT_COEX_ALGO_A2DP;
+			} else if (bt_link_info->pan_exist) {
+				if (bt_hs_on) {
+					BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+						    "[BTCoex], PAN(HS) only\n");
+					BTC_TRACE(trace_buf);
+					algorithm =
+						BT_8821A_2ANT_COEX_ALGO_PANHS;
+				} else {
+					BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+						"[BTCoex], PAN(EDR) only\n");
+					BTC_TRACE(trace_buf);
+					algorithm =
+						BT_8821A_2ANT_COEX_ALGO_PANEDR;
+				}
+			}
+		}
+	} else if (num_of_diff_profile == 2) {
+		if (bt_link_info->sco_exist) {
+			if (bt_link_info->hid_exist) {
+				BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+					    "[BTCoex], SCO + HID\n");
+				BTC_TRACE(trace_buf);
+				algorithm = BT_8821A_2ANT_COEX_ALGO_SCO;
+			} else if (bt_link_info->a2dp_exist) {
+				BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+					    "[BTCoex], SCO + A2DP ==> SCO\n");
+				BTC_TRACE(trace_buf);
+				algorithm = BT_8821A_2ANT_COEX_ALGO_SCO;
+			} else if (bt_link_info->pan_exist) {
+				if (bt_hs_on) {
+					BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+						"[BTCoex], SCO + PAN(HS)\n");
+					BTC_TRACE(trace_buf);
+					algorithm = BT_8821A_2ANT_COEX_ALGO_SCO;
+				} else {
+					BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+						"[BTCoex], SCO + PAN(EDR)\n");
+					BTC_TRACE(trace_buf);
+					algorithm = BT_8821A_2ANT_COEX_ALGO_SCO;
+				}
+			}
+		} else {
+			if (bt_link_info->hid_exist &&
+			    bt_link_info->a2dp_exist) {
+				{
+					BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+						    "[BTCoex], HID + A2DP\n");
+					BTC_TRACE(trace_buf);
+					algorithm =
+						BT_8821A_2ANT_COEX_ALGO_HID_A2DP;
+				}
+			} else if (bt_link_info->hid_exist &&
+				   bt_link_info->pan_exist) {
+				if (bt_hs_on) {
+					BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+						"[BTCoex], HID + PAN(HS)\n");
+					BTC_TRACE(trace_buf);
+					algorithm = BT_8821A_2ANT_COEX_ALGO_HID;
+				} else {
+					BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+						"[BTCoex], HID + PAN(EDR)\n");
+					BTC_TRACE(trace_buf);
+					algorithm =
+						BT_8821A_2ANT_COEX_ALGO_PANEDR_HID;
+				}
+			} else if (bt_link_info->pan_exist &&
+				   bt_link_info->a2dp_exist) {
+				if (bt_hs_on) {
+					BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+						"[BTCoex], A2DP + PAN(HS)\n");
+					BTC_TRACE(trace_buf);
+					algorithm =
+						BT_8821A_2ANT_COEX_ALGO_A2DP_PANHS;
+				} else {
+					BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+						"[BTCoex], A2DP + PAN(EDR)\n");
+					BTC_TRACE(trace_buf);
+					algorithm =
+						BT_8821A_2ANT_COEX_ALGO_PANEDR_A2DP;
+				}
+			}
+		}
+	} else if (num_of_diff_profile == 3) {
+		if (bt_link_info->sco_exist) {
+			if (bt_link_info->hid_exist &&
+			    bt_link_info->a2dp_exist) {
+				BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+					"[BTCoex], SCO + HID + A2DP ==> SCO\n");
+				BTC_TRACE(trace_buf);
+				algorithm = BT_8821A_2ANT_COEX_ALGO_SCO;
+			} else if (bt_link_info->hid_exist &&
+				   bt_link_info->pan_exist) {
+				if (bt_hs_on) {
+					BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+						"[BTCoex], SCO + HID + PAN(HS) ==> SCO\n");
+					BTC_TRACE(trace_buf);
+					algorithm = BT_8821A_2ANT_COEX_ALGO_SCO;
+				} else {
+					BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+						"[BTCoex], SCO + HID + PAN(EDR) ==> SCO\n");
+					BTC_TRACE(trace_buf);
+					algorithm = BT_8821A_2ANT_COEX_ALGO_SCO;
+				}
+			} else if (bt_link_info->pan_exist &&
+				   bt_link_info->a2dp_exist) {
+				if (bt_hs_on) {
+					BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+						"[BTCoex], SCO + A2DP + PAN(HS)\n");
+					BTC_TRACE(trace_buf);
+					algorithm = BT_8821A_2ANT_COEX_ALGO_SCO;
+				} else {
+					BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+						"[BTCoex], SCO + A2DP + PAN(EDR) ==> HID\n");
+					BTC_TRACE(trace_buf);
+					algorithm = BT_8821A_2ANT_COEX_ALGO_SCO;
+				}
+			}
+		} else {
+			if (bt_link_info->hid_exist &&
+			    bt_link_info->pan_exist &&
+			    bt_link_info->a2dp_exist) {
+				if (bt_hs_on) {
+					BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+						"[BTCoex], HID + A2DP + PAN(HS)\n");
+					BTC_TRACE(trace_buf);
+					algorithm =
+						BT_8821A_2ANT_COEX_ALGO_HID_A2DP;
+				} else {
+					BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+						"[BTCoex], HID + A2DP + PAN(EDR)\n");
+					BTC_TRACE(trace_buf);
+					algorithm =
+						BT_8821A_2ANT_COEX_ALGO_HID_A2DP_PANEDR;
+				}
+			}
+		}
+	} else if (num_of_diff_profile >= 3) {
+		if (bt_link_info->sco_exist) {
+			if (bt_link_info->hid_exist &&
+			    bt_link_info->pan_exist &&
+			    bt_link_info->a2dp_exist) {
+				if (bt_hs_on) {
+					BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+						"[BTCoex], Error!!! SCO + HID + A2DP + PAN(HS)\n");
+					BTC_TRACE(trace_buf);
+
+				} else {
+					BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+						"[BTCoex], SCO + HID + A2DP + PAN(EDR)==>PAN(EDR)+HID\n");
+					BTC_TRACE(trace_buf);
+					algorithm = BT_8821A_2ANT_COEX_ALGO_SCO;
+				}
+			}
+		}
+	}
+
+	return algorithm;
+}
+
+void halbtc8821a2ant_set_fw_dac_swing_level(IN struct btc_coexist *btcoexist,
+		IN u8 dac_swing_lvl)
+{
+	u8			h2c_parameter[1] = {0};
+
+	/* There are several type of dacswing */
+	/* 0x18/ 0x10/ 0xc/ 0x8/ 0x4/ 0x6 */
+	h2c_parameter[0] = dac_swing_lvl;
+
+	btcoexist->btc_fill_h2c(btcoexist, 0x64, 1, h2c_parameter);
+}
+
+void halbtc8821a2ant_set_fw_dec_bt_pwr(IN struct btc_coexist *btcoexist,
+				       IN u8 dec_bt_pwr_lvl)
+{
+	u8			h2c_parameter[1] = {0};
+
+	h2c_parameter[0] = dec_bt_pwr_lvl;
+
+	btcoexist->btc_fill_h2c(btcoexist, 0x62, 1, h2c_parameter);
+}
+
+void halbtc8821a2ant_dec_bt_pwr(IN struct btc_coexist *btcoexist,
+				IN boolean force_exec, IN u8 dec_bt_pwr_lvl)
+{
+	coex_dm->cur_bt_dec_pwr_lvl = dec_bt_pwr_lvl;
+
+	if (!force_exec) {
+		if (coex_dm->pre_bt_dec_pwr_lvl == coex_dm->cur_bt_dec_pwr_lvl)
+			return;
+	}
+	halbtc8821a2ant_set_fw_dec_bt_pwr(btcoexist,
+					  coex_dm->cur_bt_dec_pwr_lvl);
+
+	coex_dm->pre_bt_dec_pwr_lvl = coex_dm->cur_bt_dec_pwr_lvl;
+}
+
+void halbtc8821a2ant_set_bt_auto_report(IN struct btc_coexist *btcoexist,
+					IN boolean enable_auto_report)
+{
+	u8			h2c_parameter[1] = {0};
+
+	h2c_parameter[0] = 0;
+
+	if (enable_auto_report)
+		h2c_parameter[0] |= BIT(0);
+
+	btcoexist->btc_fill_h2c(btcoexist, 0x68, 1, h2c_parameter);
+}
+
+void halbtc8821a2ant_bt_auto_report(IN struct btc_coexist *btcoexist,
+		    IN boolean force_exec, IN boolean enable_auto_report)
+{
+	coex_dm->cur_bt_auto_report = enable_auto_report;
+
+	if (!force_exec) {
+		if (coex_dm->pre_bt_auto_report == coex_dm->cur_bt_auto_report)
+			return;
+	}
+	halbtc8821a2ant_set_bt_auto_report(btcoexist,
+					   coex_dm->cur_bt_auto_report);
+
+	coex_dm->pre_bt_auto_report = coex_dm->cur_bt_auto_report;
+}
+
+void halbtc8821a2ant_fw_dac_swing_lvl(IN struct btc_coexist *btcoexist,
+			      IN boolean force_exec, IN u8 fw_dac_swing_lvl)
+{
+	coex_dm->cur_fw_dac_swing_lvl = fw_dac_swing_lvl;
+
+	if (!force_exec) {
+		if (coex_dm->pre_fw_dac_swing_lvl ==
+		    coex_dm->cur_fw_dac_swing_lvl)
+			return;
+	}
+
+	halbtc8821a2ant_set_fw_dac_swing_level(btcoexist,
+					       coex_dm->cur_fw_dac_swing_lvl);
+
+	coex_dm->pre_fw_dac_swing_lvl = coex_dm->cur_fw_dac_swing_lvl;
+}
+
+void halbtc8821a2ant_set_sw_rf_rx_lpf_corner(IN struct btc_coexist *btcoexist,
+		IN boolean rx_rf_shrink_on)
+{
+	if (rx_rf_shrink_on) {
+		/* Shrink RF Rx LPF corner */
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], Shrink RF Rx LPF corner!!\n");
+		BTC_TRACE(trace_buf);
+		btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1e, 0xfffff,
+					  0xffffc);
+	} else {
+		/* Resume RF Rx LPF corner */
+		/* After initialized, we can use coex_dm->bt_rf_0x1e_backup */
+		if (btcoexist->initilized) {
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				    "[BTCoex], Resume RF Rx LPF corner!!\n");
+			BTC_TRACE(trace_buf);
+			btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1e,
+					  0xfffff, coex_dm->bt_rf_0x1e_backup);
+		}
+	}
+}
+
+void halbtc8821a2ant_rf_shrink(IN struct btc_coexist *btcoexist,
+		       IN boolean force_exec, IN boolean rx_rf_shrink_on)
+{
+	coex_dm->cur_rf_rx_lpf_shrink = rx_rf_shrink_on;
+
+	if (!force_exec) {
+		if (coex_dm->pre_rf_rx_lpf_shrink ==
+		    coex_dm->cur_rf_rx_lpf_shrink)
+			return;
+	}
+	halbtc8821a2ant_set_sw_rf_rx_lpf_corner(btcoexist,
+						coex_dm->cur_rf_rx_lpf_shrink);
+
+	coex_dm->pre_rf_rx_lpf_shrink = coex_dm->cur_rf_rx_lpf_shrink;
+}
+
+void halbtc8821a2ant_set_sw_penalty_tx_rate_adaptive(IN struct btc_coexist
+		*btcoexist, IN boolean low_penalty_ra)
+{
+	u8			h2c_parameter[6] = {0};
+
+	h2c_parameter[0] = 0x6;	/* op_code, 0x6= Retry_Penalty */
+
+	if (low_penalty_ra) {
+		h2c_parameter[1] |= BIT(0);
+		h2c_parameter[2] =
+			0x00;  /* normal rate except MCS7/6/5, OFDM54/48/36 */
+		h2c_parameter[3] = 0xf3;  /* MCS7 or OFDM54 */
+		h2c_parameter[4] = 0xa0;  /* MCS6 or OFDM48 */
+		h2c_parameter[5] = 0xa0;	/* MCS5 or OFDM36 */
+		/* h2c_parameter[3] = 0xf7; */ /*MCS7 or OFDM54 */
+		/* h2c_parameter[4] = 0xf8; */ /*MCS6 or OFDM48 */
+		/* h2c_parameter[5] = 0xf9;	/MCS5 or OFDM36	 */
+	}
+
+	btcoexist->btc_fill_h2c(btcoexist, 0x69, 6, h2c_parameter);
+}
+
+void halbtc8821a2ant_low_penalty_ra(IN struct btc_coexist *btcoexist,
+			    IN boolean force_exec, IN boolean low_penalty_ra)
+{
+	coex_dm->cur_low_penalty_ra = low_penalty_ra;
+
+	if (!force_exec) {
+		if (coex_dm->pre_low_penalty_ra == coex_dm->cur_low_penalty_ra)
+			return;
+	}
+	halbtc8821a2ant_set_sw_penalty_tx_rate_adaptive(btcoexist,
+			coex_dm->cur_low_penalty_ra);
+
+	coex_dm->pre_low_penalty_ra = coex_dm->cur_low_penalty_ra;
+}
+
+void halbtc8821a2ant_set_dac_swing_reg(IN struct btc_coexist *btcoexist,
+				       IN u32 level)
+{
+	u8	val = (u8)level;
+
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+		    "[BTCoex], Write SwDacSwing = 0x%x\n", level);
+	BTC_TRACE(trace_buf);
+	btcoexist->btc_write_1byte_bitmask(btcoexist, 0xc5b, 0x3e, val);
+}
+
+void halbtc8821a2ant_set_sw_full_time_dac_swing(IN struct btc_coexist
+		*btcoexist, IN boolean sw_dac_swing_on, IN u32 sw_dac_swing_lvl)
+{
+	if (sw_dac_swing_on)
+		halbtc8821a2ant_set_dac_swing_reg(btcoexist, sw_dac_swing_lvl);
+	else
+		halbtc8821a2ant_set_dac_swing_reg(btcoexist, 0x18);
+}
+
+
+void halbtc8821a2ant_dac_swing(IN struct btc_coexist *btcoexist,
+	IN boolean force_exec, IN boolean dac_swing_on, IN u32 dac_swing_lvl)
+{
+	coex_dm->cur_dac_swing_on = dac_swing_on;
+	coex_dm->cur_dac_swing_lvl = dac_swing_lvl;
+
+	if (!force_exec) {
+		if ((coex_dm->pre_dac_swing_on == coex_dm->cur_dac_swing_on) &&
+		    (coex_dm->pre_dac_swing_lvl ==
+		     coex_dm->cur_dac_swing_lvl))
+			return;
+	}
+	delay_ms(30);
+	halbtc8821a2ant_set_sw_full_time_dac_swing(btcoexist, dac_swing_on,
+			dac_swing_lvl);
+
+	coex_dm->pre_dac_swing_on = coex_dm->cur_dac_swing_on;
+	coex_dm->pre_dac_swing_lvl = coex_dm->cur_dac_swing_lvl;
+}
+
+void halbtc8821a2ant_set_adc_back_off(IN struct btc_coexist *btcoexist,
+				      IN boolean adc_back_off)
+{
+	if (adc_back_off) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], BB BackOff Level On!\n");
+		BTC_TRACE(trace_buf);
+		btcoexist->btc_write_1byte_bitmask(btcoexist, 0x8db, 0x60, 0x3);
+	} else {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], BB BackOff Level Off!\n");
+		BTC_TRACE(trace_buf);
+		btcoexist->btc_write_1byte_bitmask(btcoexist, 0x8db, 0x60, 0x1);
+	}
+}
+
+void halbtc8821a2ant_adc_back_off(IN struct btc_coexist *btcoexist,
+			  IN boolean force_exec, IN boolean adc_back_off)
+{
+	coex_dm->cur_adc_back_off = adc_back_off;
+
+	if (!force_exec) {
+		if (coex_dm->pre_adc_back_off == coex_dm->cur_adc_back_off)
+			return;
+	}
+	halbtc8821a2ant_set_adc_back_off(btcoexist, coex_dm->cur_adc_back_off);
+
+	coex_dm->pre_adc_back_off = coex_dm->cur_adc_back_off;
+}
+
+void halbtc8821a2ant_set_agc_table(IN struct btc_coexist *btcoexist,
+				   IN boolean agc_table_en)
+{
+	u8		rssi_adjust_val = 0;
+
+	/* =================BB AGC Gain Table */
+	if (agc_table_en) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], BB Agc Table On!\n");
+		BTC_TRACE(trace_buf);
+		btcoexist->btc_write_4byte(btcoexist, 0xc78, 0x6e1A0001);
+		btcoexist->btc_write_4byte(btcoexist, 0xc78, 0x6d1B0001);
+		btcoexist->btc_write_4byte(btcoexist, 0xc78, 0x6c1C0001);
+		btcoexist->btc_write_4byte(btcoexist, 0xc78, 0x6b1D0001);
+		btcoexist->btc_write_4byte(btcoexist, 0xc78, 0x6a1E0001);
+		btcoexist->btc_write_4byte(btcoexist, 0xc78, 0x691F0001);
+		btcoexist->btc_write_4byte(btcoexist, 0xc78, 0x68200001);
+	} else {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], BB Agc Table Off!\n");
+		BTC_TRACE(trace_buf);
+		btcoexist->btc_write_4byte(btcoexist, 0xc78, 0xaa1A0001);
+		btcoexist->btc_write_4byte(btcoexist, 0xc78, 0xa91B0001);
+		btcoexist->btc_write_4byte(btcoexist, 0xc78, 0xa81C0001);
+		btcoexist->btc_write_4byte(btcoexist, 0xc78, 0xa71D0001);
+		btcoexist->btc_write_4byte(btcoexist, 0xc78, 0xa61E0001);
+		btcoexist->btc_write_4byte(btcoexist, 0xc78, 0xa51F0001);
+		btcoexist->btc_write_4byte(btcoexist, 0xc78, 0xa4200001);
+	}
+
+
+	/* =================RF Gain */
+	btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0xef, 0xfffff, 0x02000);
+	if (agc_table_en) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], Agc Table On!\n");
+		BTC_TRACE(trace_buf);
+		btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x3b, 0xfffff,
+					  0x38fff);
+		btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x3b, 0xfffff,
+					  0x38ffe);
+	} else {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], Agc Table Off!\n");
+		BTC_TRACE(trace_buf);
+		btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x3b, 0xfffff,
+					  0x380c3);
+		btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x3b, 0xfffff,
+					  0x28ce6);
+	}
+	btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0xef, 0xfffff, 0x0);
+
+	btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0xed, 0xfffff, 0x1);
+	if (agc_table_en) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], Agc Table On!\n");
+		BTC_TRACE(trace_buf);
+		btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x40, 0xfffff,
+					  0x38fff);
+		btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x40, 0xfffff,
+					  0x38ffe);
+	} else {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], Agc Table Off!\n");
+		BTC_TRACE(trace_buf);
+		btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x40, 0xfffff,
+					  0x380c3);
+		btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x40, 0xfffff,
+					  0x28ce6);
+	}
+	btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0xed, 0xfffff, 0x0);
+
+	/* set rssi_adjust_val for wifi module. */
+	if (agc_table_en)
+		rssi_adjust_val = 8;
+	btcoexist->btc_set(btcoexist, BTC_SET_U1_RSSI_ADJ_VAL_FOR_AGC_TABLE_ON,
+			   &rssi_adjust_val);
+}
+
+void halbtc8821a2ant_agc_table(IN struct btc_coexist *btcoexist,
+			       IN boolean force_exec, IN boolean agc_table_en)
+{
+	coex_dm->cur_agc_table_en = agc_table_en;
+
+	if (!force_exec) {
+		if (coex_dm->pre_agc_table_en == coex_dm->cur_agc_table_en)
+			return;
+	}
+	halbtc8821a2ant_set_agc_table(btcoexist, agc_table_en);
+
+	coex_dm->pre_agc_table_en = coex_dm->cur_agc_table_en;
+}
+
+void halbtc8821a2ant_sw_mechanism1(IN struct btc_coexist *btcoexist,
+			   IN boolean shrink_rx_lpf, IN boolean low_penalty_ra,
+			   IN boolean limited_dig, IN boolean bt_lna_constrain)
+{
+
+
+	/* halbtc8821a2ant_rf_shrink(btcoexist, NORMAL_EXEC, shrink_rx_lpf); */
+	halbtc8821a2ant_low_penalty_ra(btcoexist, NORMAL_EXEC, low_penalty_ra);
+}
+
+void halbtc8821a2ant_sw_mechanism2(IN struct btc_coexist *btcoexist,
+			   IN boolean agc_table_shift, IN boolean adc_back_off,
+			   IN boolean sw_dac_swing, IN u32 dac_swing_lvl)
+{
+
+	halbtc8821a2ant_dac_swing(btcoexist, NORMAL_EXEC, sw_dac_swing,
+				  dac_swing_lvl);
+}
+
+void halbtc8821a2ant_set_coex_table(IN struct btc_coexist *btcoexist,
+	    IN u32 val0x6c0, IN u32 val0x6c4, IN u32 val0x6c8, IN u8 val0x6cc)
+{
+	btcoexist->btc_write_4byte(btcoexist, 0x6c0, val0x6c0);
+
+	btcoexist->btc_write_4byte(btcoexist, 0x6c4, val0x6c4);
+
+	btcoexist->btc_write_4byte(btcoexist, 0x6c8, val0x6c8);
+
+	btcoexist->btc_write_1byte(btcoexist, 0x6cc, val0x6cc);
+}
+
+void halbtc8821a2ant_coex_table(IN struct btc_coexist *btcoexist,
+			IN boolean force_exec, IN u32 val0x6c0, IN u32 val0x6c4,
+				IN u32 val0x6c8, IN u8 val0x6cc)
+{
+	coex_dm->cur_val0x6c0 = val0x6c0;
+	coex_dm->cur_val0x6c4 = val0x6c4;
+	coex_dm->cur_val0x6c8 = val0x6c8;
+	coex_dm->cur_val0x6cc = val0x6cc;
+
+	if (!force_exec) {
+		if ((coex_dm->pre_val0x6c0 == coex_dm->cur_val0x6c0) &&
+		    (coex_dm->pre_val0x6c4 == coex_dm->cur_val0x6c4) &&
+		    (coex_dm->pre_val0x6c8 == coex_dm->cur_val0x6c8) &&
+		    (coex_dm->pre_val0x6cc == coex_dm->cur_val0x6cc))
+			return;
+	}
+	halbtc8821a2ant_set_coex_table(btcoexist, val0x6c0, val0x6c4, val0x6c8,
+				       val0x6cc);
+
+	coex_dm->pre_val0x6c0 = coex_dm->cur_val0x6c0;
+	coex_dm->pre_val0x6c4 = coex_dm->cur_val0x6c4;
+	coex_dm->pre_val0x6c8 = coex_dm->cur_val0x6c8;
+	coex_dm->pre_val0x6cc = coex_dm->cur_val0x6cc;
+}
+
+void halbtc8821a2ant_coex_table_with_type(IN struct btc_coexist *btcoexist,
+		IN boolean force_exec, IN u8 type)
+{
+	coex_sta->coex_table_type = type;
+
+	switch (type) {
+	case 0:
+		halbtc8821a2ant_coex_table(btcoexist, force_exec,
+				   0x55555555, 0x55555555, 0xffffff, 0x3);
+		break;
+	case 1:
+		halbtc8821a2ant_coex_table(btcoexist, force_exec,
+				   0x55555555, 0x5afa5afa, 0xffffff, 0x3);
+		break;
+	case 2:
+		halbtc8821a2ant_coex_table(btcoexist, force_exec,
+				   0x5ada5ada, 0x5ada5ada, 0xffffff, 0x3);
+		break;
+	case 3:
+		halbtc8821a2ant_coex_table(btcoexist, force_exec,
+				   0xaaaaaaaa, 0xaaaaaaaa, 0xffffff, 0x3);
+		break;
+	case 4:
+		halbtc8821a2ant_coex_table(btcoexist, force_exec,
+				   0xffffffff, 0xffffffff, 0xffffff, 0x3);
+		break;
+	case 5:
+		halbtc8821a2ant_coex_table(btcoexist, force_exec,
+				   0x5fff5fff, 0x5fff5fff, 0xffffff, 0x3);
+		break;
+	case 6:
+		halbtc8821a2ant_coex_table(btcoexist, force_exec,
+				   0x55ff55ff, 0x5a5a5a5a, 0xffffff, 0x3);
+		break;
+	case 7:
+		halbtc8821a2ant_coex_table(btcoexist, force_exec,
+				   0x55dd55dd, 0x5ada5ada, 0xffffff, 0x3);
+		break;
+	case 8:
+		halbtc8821a2ant_coex_table(btcoexist, force_exec,
+				   0x55dd55dd, 0x5ada5ada, 0xffffff, 0x3);
+		break;
+	case 9:
+		halbtc8821a2ant_coex_table(btcoexist, force_exec,
+				   0x55dd55dd, 0x5ada5ada, 0xffffff, 0x3);
+		break;
+	case 10:
+		halbtc8821a2ant_coex_table(btcoexist, force_exec,
+				   0x55dd55dd, 0x5ada5ada, 0xffffff, 0x3);
+		break;
+	case 11:
+		halbtc8821a2ant_coex_table(btcoexist, force_exec,
+				   0x55dd55dd, 0x5ada5ada, 0xffffff, 0x3);
+		break;
+	case 12:
+		halbtc8821a2ant_coex_table(btcoexist, force_exec,
+				   0x55dd55dd, 0x5ada5ada, 0xffffff, 0x3);
+		break;
+	case 13:
+		halbtc8821a2ant_coex_table(btcoexist, force_exec,
+				   0x5fff5fff, 0xaaaaaaaa, 0xffffff, 0x3);
+		break;
+	case 14:
+		halbtc8821a2ant_coex_table(btcoexist, force_exec,
+				   0x5fff5fff, 0x5ada5ada, 0xffffff, 0x3);
+		break;
+	case 15:
+		halbtc8821a2ant_coex_table(btcoexist, force_exec,
+				   0x55dd55dd, 0xaaaaaaaa, 0xffffff, 0x3);
+		break;
+	case 16:
+		halbtc8821a2ant_coex_table(btcoexist, force_exec,
+				   0x5fdf5fdf, 0x5fdb5fdb, 0xffffff, 0x3);
+		break;
+	case 17:
+		halbtc8821a2ant_coex_table(btcoexist, force_exec,
+				   0xfafafafa, 0xfafafafa, 0xffffff, 0x3);
+		break;
+	case 18:
+		halbtc8821a2ant_coex_table(btcoexist, force_exec,
+				   0x5555555f, 0x5ada5ada, 0xffffff, 0x3);
+		break;
+	default:
+		break;
+	}
+}
+
+void halbtc8821a2ant_set_fw_ignore_wlan_act(IN struct btc_coexist *btcoexist,
+		IN boolean enable)
+{
+	u8			h2c_parameter[1] = {0};
+
+	if (enable)
+		h2c_parameter[0] |= BIT(0);		/* function enable */
+
+	btcoexist->btc_fill_h2c(btcoexist, 0x63, 1, h2c_parameter);
+}
+
+void halbtc8821a2ant_ignore_wlan_act(IN struct btc_coexist *btcoexist,
+				     IN boolean force_exec, IN boolean enable)
+{
+	coex_dm->cur_ignore_wlan_act = enable;
+
+	if (!force_exec) {
+		if (coex_dm->pre_ignore_wlan_act ==
+		    coex_dm->cur_ignore_wlan_act)
+			return;
+	}
+	halbtc8821a2ant_set_fw_ignore_wlan_act(btcoexist, enable);
+
+	coex_dm->pre_ignore_wlan_act = coex_dm->cur_ignore_wlan_act;
+}
+
+
+void halbtc8821a2ant_set_lps_rpwm(IN struct btc_coexist *btcoexist,
+				  IN u8 lps_val, IN u8 rpwm_val)
+{
+	u8	lps = lps_val;
+	u8	rpwm = rpwm_val;
+
+	btcoexist->btc_set(btcoexist, BTC_SET_U1_LPS_VAL, &lps);
+	btcoexist->btc_set(btcoexist, BTC_SET_U1_RPWM_VAL, &rpwm);
+}
+
+void halbtc8821a2ant_lps_rpwm(IN struct btc_coexist *btcoexist,
+		      IN boolean force_exec, IN u8 lps_val, IN u8 rpwm_val)
+{
+	coex_dm->cur_lps = lps_val;
+	coex_dm->cur_rpwm = rpwm_val;
+
+	if (!force_exec) {
+		if ((coex_dm->pre_lps == coex_dm->cur_lps) &&
+		    (coex_dm->pre_rpwm == coex_dm->cur_rpwm))
+			return;
+	}
+	halbtc8821a2ant_set_lps_rpwm(btcoexist, lps_val, rpwm_val);
+
+	coex_dm->pre_lps = coex_dm->cur_lps;
+	coex_dm->pre_rpwm = coex_dm->cur_rpwm;
+}
+
+void halbtc8821a2ant_ps_tdma_check_for_power_save_state(
+	IN struct btc_coexist *btcoexist, IN boolean new_ps_state)
+{
+	u8	lps_mode = 0x0;
+	u8	h2c_parameter[5] = {0x0, 0, 0, 48, 0};
+
+	btcoexist->btc_get(btcoexist, BTC_GET_U1_LPS_MODE, &lps_mode);
+
+	if (lps_mode) {	/* already under LPS state */
+		if (new_ps_state) {
+			/* keep state under LPS, do nothing. */
+		} else {
+
+			btcoexist->btc_fill_h2c(btcoexist, 0x60, 5,
+				h2c_parameter);
+		}
+	} else {					/* NO PS state */
+		if (new_ps_state) {
+
+			btcoexist->btc_fill_h2c(btcoexist, 0x60, 5,
+				h2c_parameter);
+		} else {
+		}
+	}
+}
+
+void halbtc8821a2ant_power_save_state(IN struct btc_coexist *btcoexist,
+			      IN u8 ps_type, IN u8 lps_val, IN u8 rpwm_val)
+{
+	boolean		low_pwr_disable = false;
+
+	switch (ps_type) {
+	case BTC_PS_WIFI_NATIVE:
+		/* recover to original 32k low power setting */
+		low_pwr_disable = false;
+		btcoexist->btc_set(btcoexist,
+				   BTC_SET_ACT_DISABLE_LOW_POWER,
+				   &low_pwr_disable);
+		btcoexist->btc_set(btcoexist, BTC_SET_ACT_NORMAL_LPS,
+				   NULL);
+		coex_sta->force_lps_on = false;
+		break;
+	case BTC_PS_LPS_ON:
+		halbtc8821a2ant_ps_tdma_check_for_power_save_state(
+			btcoexist, true);
+		halbtc8821a2ant_lps_rpwm(btcoexist, NORMAL_EXEC,
+					 lps_val, rpwm_val);
+		/* when coex force to enter LPS, do not enter 32k low power. */
+		low_pwr_disable = true;
+		btcoexist->btc_set(btcoexist,
+				   BTC_SET_ACT_DISABLE_LOW_POWER,
+				   &low_pwr_disable);
+		/*power save must executed before psTdma*/
+		btcoexist->btc_set(btcoexist, BTC_SET_ACT_ENTER_LPS,
+				   NULL);
+		coex_sta->force_lps_on = true;
+		break;
+	case BTC_PS_LPS_OFF:
+		halbtc8821a2ant_ps_tdma_check_for_power_save_state(
+			btcoexist, false);
+		btcoexist->btc_set(btcoexist, BTC_SET_ACT_LEAVE_LPS,
+				   NULL);
+		coex_sta->force_lps_on = false;
+		break;
+	default:
+		break;
+	}
+}
+
+
+void halbtc8821a2ant_set_fw_pstdma(IN struct btc_coexist *btcoexist,
+	   IN u8 byte1, IN u8 byte2, IN u8 byte3, IN u8 byte4, IN u8 byte5)
+{
+	u8			h2c_parameter[5] = {0};
+	u8			real_byte1 = byte1, real_byte5 = byte5;
+	boolean		ap_enable = false;
+
+
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_AP_MODE_ENABLE,
+			   &ap_enable);
+
+	if (ap_enable) {
+		if (byte1 & BIT(4) && !(byte1 & BIT(5))) {
+			real_byte1 &= ~BIT(4);
+			real_byte1 |= BIT(5);
+
+			real_byte5 |= BIT(5);
+			real_byte5 &= ~BIT(6);
+
+			halbtc8821a2ant_power_save_state(btcoexist,
+				BTC_PS_WIFI_NATIVE, 0x0, 0x0);
+		}
+} else if (byte1 & BIT(4) && !(byte1 & BIT(5))) {
+halbtc8821a2ant_power_save_state(btcoexist, BTC_PS_LPS_ON, 0x50, 0x4);
+
+	} else {
+			halbtc8821a2ant_power_save_state(btcoexist,
+				BTC_PS_WIFI_NATIVE, 0x0, 0x0);
+	}
+
+	h2c_parameter[0] = byte1;
+	h2c_parameter[1] = byte2;
+	h2c_parameter[2] = byte3;
+	h2c_parameter[3] = byte4;
+	h2c_parameter[4] = byte5;
+
+	coex_dm->ps_tdma_para[0] = byte1;
+	coex_dm->ps_tdma_para[1] = byte2;
+	coex_dm->ps_tdma_para[2] = byte3;
+	coex_dm->ps_tdma_para[3] = byte4;
+	coex_dm->ps_tdma_para[4] = byte5;
+
+	btcoexist->btc_fill_h2c(btcoexist, 0x60, 5, h2c_parameter);
+}
+
+void halbtc8821a2ant_ps_tdma(IN struct btc_coexist *btcoexist,
+		     IN boolean force_exec, IN boolean turn_on, IN u8 type)
+{
+	u8			wifi_rssi_state1, bt_rssi_state;
+
+
+	wifi_rssi_state1 = halbtc8821a2ant_wifi_rssi_state(btcoexist, 1, 2,
+			   BT_8821A_2ANT_WIFI_RSSI_COEXSWITCH_THRES, 0);
+	bt_rssi_state = halbtc8821a2ant_bt_rssi_state(2,
+			BT_8821A_2ANT_BT_RSSI_COEXSWITCH_THRES, 0);
+
+	if (!(BTC_RSSI_HIGH(wifi_rssi_state1) &&
+	      BTC_RSSI_HIGH(bt_rssi_state)) && turn_on) {
+		type = type + 100; /* for WiFi RSSI low or BT RSSI low */
+	}
+
+	coex_dm->cur_ps_tdma_on = turn_on;
+	coex_dm->cur_ps_tdma = type;
+
+	if (!force_exec) {
+		if ((coex_dm->pre_ps_tdma_on == coex_dm->cur_ps_tdma_on) &&
+		    (coex_dm->pre_ps_tdma == coex_dm->cur_ps_tdma))
+			return;
+	}
+	if (turn_on) {
+		switch (type) {
+		case 1:
+		default:
+			/* halbtc8821a2ant_set_fw_pstdma(btcoexist, 0xe3, 0x1a, 0x1a, 0xe1, 0x90); */
+			halbtc8821a2ant_set_fw_pstdma(btcoexist, 0xe3,
+						      0x3c, 0x03, 0xf1, 0x90);
+			break;
+		case 2:
+			/* halbtc8821a2ant_set_fw_pstdma(btcoexist, 0xe3, 0x12, 0x12, 0xe1, 0x90); */
+			halbtc8821a2ant_set_fw_pstdma(btcoexist, 0xe3,
+						      0x2d, 0x03, 0xf1, 0x90);
+			break;
+		case 3:
+			halbtc8821a2ant_set_fw_pstdma(btcoexist, 0xe3,
+						      0x1c, 0x3, 0xf1, 0x90);
+			break;
+		case 4:
+			halbtc8821a2ant_set_fw_pstdma(btcoexist, 0xe3,
+						      0x10, 0x03, 0xf1, 0x90);
+			break;
+		case 5:
+			/* halbtc8821a2ant_set_fw_pstdma(btcoexist, 0xe3, 0x1a, 0x1a, 0x60, 0x90); */
+			halbtc8821a2ant_set_fw_pstdma(btcoexist, 0xe3,
+						      0x3c, 0x3, 0x70, 0x90);
+			break;
+		case 6:
+			/* halbtc8821a2ant_set_fw_pstdma(btcoexist, 0xe3, 0x12, 0x12, 0x60, 0x90); */
+			halbtc8821a2ant_set_fw_pstdma(btcoexist, 0xe3,
+						      0x2d, 0x3, 0x70, 0x90);
+			break;
+		case 7:
+			halbtc8821a2ant_set_fw_pstdma(btcoexist, 0xe3,
+						      0x1c, 0x3, 0x70, 0x90);
+			break;
+		case 8:
+			halbtc8821a2ant_set_fw_pstdma(btcoexist, 0xa3,
+						      0x10, 0x3, 0x70, 0x90);
+			break;
+		case 9:
+			/* halbtc8821a2ant_set_fw_pstdma(btcoexist, 0xe3, 0x1a, 0x1a, 0xe1, 0x90); */
+			halbtc8821a2ant_set_fw_pstdma(btcoexist, 0xe3,
+						      0x3c, 0x03, 0xf1, 0x90);
+			break;
+		case 10:
+			/* halbtc8821a2ant_set_fw_pstdma(btcoexist, 0xe3, 0x12, 0x12, 0xe1, 0x90); */
+			halbtc8821a2ant_set_fw_pstdma(btcoexist, 0xe3,
+						      0x2d, 0x03, 0xf1, 0x90);
+			break;
+		case 11:
+			/* halbtc8821a2ant_set_fw_pstdma(btcoexist, 0xe3, 0xa, 0xa, 0xe1, 0x90); */
+			halbtc8821a2ant_set_fw_pstdma(btcoexist, 0xe3,
+						      0x1c, 0x3, 0xf1, 0x90);
+			break;
+		case 12:
+			/* halbtc8821a2ant_set_fw_pstdma(btcoexist, 0xe3, 0x5, 0x5, 0xe1, 0x90); */
+			halbtc8821a2ant_set_fw_pstdma(btcoexist, 0xe3,
+						      0x10, 0x3, 0xf1, 0x90);
+			break;
+		case 13:
+			/* halbtc8821a2ant_set_fw_pstdma(btcoexist, 0xe3, 0x1a, 0x1a, 0x60, 0x90); */
+			halbtc8821a2ant_set_fw_pstdma(btcoexist, 0xe3,
+						      0x3c, 0x3, 0x70, 0x90);
+			break;
+		case 14:
+			/* halbtc8821a2ant_set_fw_pstdma(btcoexist, 0xe3, 0x12, 0x12, 0x60, 0x90); */
+			halbtc8821a2ant_set_fw_pstdma(btcoexist, 0xe3,
+						      0x2d, 0x3, 0x70, 0x90);
+			break;
+		case 15:
+			/* halbtc8821a2ant_set_fw_pstdma(btcoexist, 0xe3, 0xa, 0xa, 0x60, 0x90); */
+			halbtc8821a2ant_set_fw_pstdma(btcoexist, 0xe3,
+						      0x1c, 0x3, 0x70, 0x90);
+			break;
+		case 16:
+			/* halbtc8821a2ant_set_fw_pstdma(btcoexist, 0xe3, 0x5, 0x5, 0x60, 0x90); */
+			halbtc8821a2ant_set_fw_pstdma(btcoexist, 0xe3,
+						      0x10, 0x3, 0x70, 0x90);
+			break;
+		case 17:
+			halbtc8821a2ant_set_fw_pstdma(btcoexist, 0xa3,
+						      0x2f, 0x2f, 0x60, 0x90);
+			break;
+		case 18:
+			halbtc8821a2ant_set_fw_pstdma(btcoexist, 0xe3,
+						      0x5, 0x5, 0xe1, 0x90);
+			break;
+		case 19:
+			halbtc8821a2ant_set_fw_pstdma(btcoexist, 0xe3,
+						      0x25, 0x25, 0xe1, 0x90);
+			break;
+		case 20:
+			halbtc8821a2ant_set_fw_pstdma(btcoexist, 0xe3,
+						      0x25, 0x25, 0x60, 0x90);
+			break;
+		case 21:
+			halbtc8821a2ant_set_fw_pstdma(btcoexist, 0xe3,
+						      0x15, 0x03, 0x70, 0x90);
+			break;
+		case 23:
+			halbtc8821a2ant_set_fw_pstdma(btcoexist, 0xe3,
+						      0x1e, 0x03, 0xf1, 0x94);
+			break;
+		case 24:
+		case 124:
+			halbtc8821a2ant_set_fw_pstdma(btcoexist, 0xd3,
+						      0x3c, 0x03, 0x70, 0x50);
+			break;
+		/* case25/case125 : for lenovo bt pan tp degrade<30% while wifi downlink */
+		case 25:
+			halbtc8821a2ant_set_fw_pstdma(btcoexist, 0xe3,
+						      0x14, 0x03, 0xf1, 0x90);
+			break;
+		case 26:
+			halbtc8821a2ant_set_fw_pstdma(btcoexist, 0xe3,
+						      0x30, 0x03, 0xf1, 0x90);
+			break;
+		case 27:
+			halbtc8821a2ant_set_fw_pstdma(btcoexist, 0xd3,
+						      0x23, 0x03, 0x70, 0x50);
+			break;
+		case 28:
+			halbtc8821a2ant_set_fw_pstdma(btcoexist, 0xe3,
+						      0x1e, 0x03, 0xf1, 0x94);
+			break;
+		case 71:
+			/* halbtc8821a2ant_set_fw_pstdma(btcoexist, 0xe3, 0x1a, 0x1a, 0xe1, 0x90); */
+
+			halbtc8821a2ant_set_fw_pstdma(btcoexist, 0xe3,
+						      0x3c, 0x03, 0xf1, 0x90);
+			break;
+		case 101:
+		case 105:
+		case 171:
+			halbtc8821a2ant_set_fw_pstdma(btcoexist, 0xd3,
+						      0x3a, 0x03, 0x70, 0x50);
+			break;
+		case 102:
+		case 106:
+		case 110:
+		case 114:
+			halbtc8821a2ant_set_fw_pstdma(btcoexist, 0xd3,
+						      0x2d, 0x03, 0x70, 0x50);
+			break;
+		case 103:
+		case 107:
+		case 111:
+		case 115:
+			halbtc8821a2ant_set_fw_pstdma(btcoexist, 0xd3,
+						      0x1c, 0x03, 0x70, 0x50);
+			break;
+		case 104:
+		case 108:
+		case 112:
+		case 116:
+			halbtc8821a2ant_set_fw_pstdma(btcoexist, 0xd3,
+						      0x10, 0x03, 0x70, 0x50);
+			break;
+		case 109:
+			halbtc8821a2ant_set_fw_pstdma(btcoexist, 0xe3,
+						      0x3c, 0x03, 0xf1, 0x90);
+			break;
+		case 113:
+			halbtc8821a2ant_set_fw_pstdma(btcoexist, 0xe3,
+						      0x3c, 0x03, 0x70, 0x90);
+			break;
+		case 121:
+			halbtc8821a2ant_set_fw_pstdma(btcoexist, 0xe3,
+						      0x15, 0x03, 0x70, 0x90);
+			break;
+		case 22:
+		case 122:
+			halbtc8821a2ant_set_fw_pstdma(btcoexist, 0xe3,
+						      0x35, 0x03, 0x71, 0x11);
+			break;
+		case 123:
+			halbtc8821a2ant_set_fw_pstdma(btcoexist, 0xd3,
+						      0x1e, 0x03, 0x70, 0x54);
+			break;
+		/* case25/case125 : for lenovo bt pan tp degrade<30% while wifi downlink */
+		case 125:
+			halbtc8821a2ant_set_fw_pstdma(btcoexist, 0xd3,
+						      0x14, 0x03, 0x70, 0x50);
+			break;
+		case 126:
+			halbtc8821a2ant_set_fw_pstdma(btcoexist, 0xd3,
+						      0x30, 0x03, 0x70, 0x50);
+			break;
+		case 127:
+			halbtc8821a2ant_set_fw_pstdma(btcoexist, 0xd3,
+						      0x28, 0x03, 0x70, 0x50);
+			break;
+		case 128:
+			halbtc8821a2ant_set_fw_pstdma(btcoexist, 0xd3,
+						      0x1e, 0x03, 0x70, 0x54);
+			break;
+		}
+	} else {
+		/* disable PS tdma */
+		switch (type) {
+		case 0:
+			halbtc8821a2ant_set_fw_pstdma(btcoexist, 0x0,
+						      0x0, 0x0, 0x40, 0x0);
+			break;
+		case 1:
+			halbtc8821a2ant_set_fw_pstdma(btcoexist, 0x0,
+						      0x0, 0x0, 0x48, 0x0);
+			break;
+		default:
+			halbtc8821a2ant_set_fw_pstdma(btcoexist, 0x0,
+						      0x0, 0x0, 0x40, 0x0);
+			break;
+		}
+	}
+
+	/* update pre state */
+	coex_dm->pre_ps_tdma_on = coex_dm->cur_ps_tdma_on;
+	coex_dm->pre_ps_tdma = coex_dm->cur_ps_tdma;
+}
+
+
+void halbtc8821a2ant_set_ant_path(IN struct btc_coexist *btcoexist,
+	  IN u8 ant_pos_type, IN boolean init_hwcfg, IN boolean wifi_off)
+{
+	struct  btc_board_info	*board_info = &btcoexist->board_info;
+	u32				u32tmp = 0;
+	u8				h2c_parameter[2] = {0};
+
+	if (init_hwcfg) {
+		/* 0x4c[23]=0, 0x4c[24]=1  Antenna control by WL/BT */
+		u32tmp = btcoexist->btc_read_4byte(btcoexist, 0x4c);
+		u32tmp &= ~BIT(23);
+		u32tmp |= BIT(24);
+		btcoexist->btc_write_4byte(btcoexist, 0x4c, u32tmp);
+
+		btcoexist->btc_write_4byte(btcoexist, 0x974, 0x3ff);
+		/* btcoexist->btc_write_1byte(btcoexist, 0xcb4, 0x77); */
+
+		if (board_info->btdm_ant_pos == BTC_ANTENNA_AT_MAIN_PORT) {
+
+			h2c_parameter[0] = 1;
+			h2c_parameter[1] = 1;
+			btcoexist->btc_fill_h2c(btcoexist, 0x65, 2,
+						h2c_parameter);
+		} else {
+
+			h2c_parameter[0] = 0;
+			h2c_parameter[1] = 1;
+			btcoexist->btc_fill_h2c(btcoexist, 0x65, 2,
+						h2c_parameter);
+		}
+	}
+
+	/* ext switch setting */
+	switch (ant_pos_type) {
+	case BTC_ANT_WIFI_AT_MAIN:
+		btcoexist->btc_write_1byte_bitmask(btcoexist, 0xcb7,
+						   0x30, 0x1);
+		break;
+	case BTC_ANT_WIFI_AT_AUX:
+		btcoexist->btc_write_1byte_bitmask(btcoexist, 0xcb7,
+						   0x30, 0x2);
+		break;
+	}
+}
+
+void halbtc8821a2ant_coex_all_off(IN struct btc_coexist *btcoexist)
+{
+	/* fw all off */
+	halbtc8821a2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 1);
+	halbtc8821a2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6);
+	halbtc8821a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);
+
+	/* sw all off */
+	halbtc8821a2ant_sw_mechanism1(btcoexist, false, false, false, false);
+	halbtc8821a2ant_sw_mechanism2(btcoexist, false, false, false, 0x18);
+
+	/* hw all off */
+	/* btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1, 0xfffff, 0x0); */
+	halbtc8821a2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0);
+}
+
+void halbtc8821a2ant_coex_under_5g(IN struct btc_coexist *btcoexist)
+{
+	halbtc8821a2ant_coex_all_off(btcoexist);
+
+	halbtc8821a2ant_ignore_wlan_act(btcoexist, NORMAL_EXEC, true);
+}
+
+void halbtc8821a2ant_action_bt_inquiry(IN struct btc_coexist *btcoexist)
+{
+	u8		wifi_rssi_state, wifi_rssi_state1, bt_rssi_state;
+	boolean	wifi_connected = false;
+	boolean	low_pwr_disable = true;
+	boolean		scan = false, link = false, roam = false;
+
+
+	wifi_rssi_state = halbtc8821a2ant_wifi_rssi_state(btcoexist, 0, 2, 15,
+			  0);
+	wifi_rssi_state1 = halbtc8821a2ant_wifi_rssi_state(btcoexist, 1, 2,
+			   BT_8821A_2ANT_WIFI_RSSI_COEXSWITCH_THRES, 0);
+	bt_rssi_state = halbtc8821a2ant_bt_rssi_state(2,
+			BT_8821A_2ANT_BT_RSSI_COEXSWITCH_THRES, 0);
+
+	btcoexist->btc_set(btcoexist, BTC_SET_ACT_DISABLE_LOW_POWER,
+			   &low_pwr_disable);
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED,
+			   &wifi_connected);
+
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_SCAN, &scan);
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_LINK, &link);
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_ROAM, &roam);
+
+	if (scan || link || roam) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], Wifi link process + BT Inq/Page!!\n");
+		BTC_TRACE(trace_buf);
+		halbtc8821a2ant_coex_table_with_type(btcoexist, NORMAL_EXEC,
+						     7);
+		halbtc8821a2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 22);
+	} else if (wifi_connected) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], Wifi connected + BT Inq/Page!!\n");
+		BTC_TRACE(trace_buf);
+		halbtc8821a2ant_coex_table_with_type(btcoexist, NORMAL_EXEC,
+						     7);
+		halbtc8821a2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 22);
+	} else {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], Wifi no-link + BT Inq/Page!!\n");
+		BTC_TRACE(trace_buf);
+		halbtc8821a2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0);
+		halbtc8821a2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 1);
+	}
+
+	halbtc8821a2ant_fw_dac_swing_lvl(btcoexist, FORCE_EXEC, 6);
+	halbtc8821a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);
+
+	halbtc8821a2ant_sw_mechanism1(btcoexist, false, false, false, false);
+	halbtc8821a2ant_sw_mechanism2(btcoexist, false, false, false, 0x18);
+
+}
+
+
+void halbtc8821a2ant_action_wifi_link_process(IN struct btc_coexist *btcoexist)
+{
+	u8	u8tmpa, u8tmpb;
+
+	halbtc8821a2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 7);
+	halbtc8821a2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 22);
+
+	halbtc8821a2ant_sw_mechanism1(btcoexist, false, false, false, false);
+	halbtc8821a2ant_sw_mechanism2(btcoexist, false, false, false, 0x18);
+
+
+
+	u8tmpa = btcoexist->btc_read_1byte(btcoexist, 0x765);
+	u8tmpb = btcoexist->btc_read_1byte(btcoexist, 0x76e);
+
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+		    "############# [BTCoex], 0x765=0x%x, 0x76e=0x%x\n", u8tmpa,
+		    u8tmpb);
+	BTC_TRACE(trace_buf);
+}
+
+boolean halbtc8821a2ant_action_wifi_idle_process(IN struct btc_coexist
+		*btcoexist)
+{
+	u8		wifi_rssi_state, wifi_rssi_state1, bt_rssi_state;
+	u8		ap_num = 0;
+
+	wifi_rssi_state = halbtc8821a2ant_wifi_rssi_state(btcoexist, 0, 2, 15,
+			  0);
+	/* wifi_rssi_state1 = halbtc8821a2ant_wifi_rssi_state(btcoexist, 1, 2, BT_8821A_2ANT_WIFI_RSSI_COEXSWITCH_THRES, 0); */
+	wifi_rssi_state1 = halbtc8821a2ant_wifi_rssi_state(btcoexist, 1, 2,
+			   BT_8821A_2ANT_WIFI_RSSI_COEXSWITCH_THRES - 20, 0);
+	bt_rssi_state = halbtc8821a2ant_bt_rssi_state(2,
+			BT_8821A_2ANT_BT_RSSI_COEXSWITCH_THRES, 0);
+
+	btcoexist->btc_get(btcoexist, BTC_GET_U1_AP_NUM, &ap_num);
+
+	/* define the office environment */
+	if (BTC_RSSI_HIGH(wifi_rssi_state1) &&
+	    (coex_sta->hid_exist == true) &&
+	    (coex_sta->a2dp_exist == true)) {
+
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			"[BTCoex], Wifi  idle process for BT HID+A2DP exist!!\n");
+		BTC_TRACE(trace_buf);
+
+		halbtc8821a2ant_dac_swing(btcoexist, NORMAL_EXEC, true, 0x6);
+		halbtc8821a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);
+
+		/* sw all off */
+		halbtc8821a2ant_sw_mechanism1(btcoexist, false, false, false,
+					      false);
+		halbtc8821a2ant_sw_mechanism2(btcoexist, false, false, false,
+					      0x18);
+
+		halbtc8821a2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0);
+
+		halbtc8821a2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 1);
+
+		return true;
+	}
+
+	/* */
+	else if (coex_sta->pan_exist == true) {
+
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			"[BTCoex], Wifi  idle process for BT PAN exist!!\n");
+		BTC_TRACE(trace_buf);
+
+		halbtc8821a2ant_dac_swing(btcoexist, NORMAL_EXEC, true, 0x6);
+		halbtc8821a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);
+
+		/* sw all off */
+		halbtc8821a2ant_sw_mechanism1(btcoexist, false, false, false,
+					      false);
+		halbtc8821a2ant_sw_mechanism2(btcoexist, false, false, false,
+					      0x18);
+
+		halbtc8821a2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0);
+
+		halbtc8821a2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 1);
+
+		return true;
+	}
+
+	else {
+		halbtc8821a2ant_dac_swing(btcoexist, NORMAL_EXEC, true, 0x18);
+		return false;
+	}
+
+
+}
+
+
+
+boolean halbtc8821a2ant_is_common_action(IN struct btc_coexist *btcoexist)
+{
+	boolean			common = false, wifi_connected = false, wifi_busy = false;
+	boolean			bt_hs_on = false, low_pwr_disable = false;
+
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on);
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED,
+			   &wifi_connected);
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy);
+
+	if (!wifi_connected) {
+		low_pwr_disable = false;
+		btcoexist->btc_set(btcoexist, BTC_SET_ACT_DISABLE_LOW_POWER,
+				   &low_pwr_disable);
+		halbtc8821a2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false,
+					   0x8);
+
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], Wifi non-connected idle!!\n");
+		BTC_TRACE(trace_buf);
+
+		btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1, 0xfffff,
+					  0x0);
+		halbtc8821a2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0);
+
+		halbtc8821a2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 1);
+		halbtc8821a2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6);
+		halbtc8821a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);
+
+		halbtc8821a2ant_sw_mechanism1(btcoexist, false, false, false,
+					      false);
+		halbtc8821a2ant_sw_mechanism2(btcoexist, false, false, false,
+					      0x18);
+
+		common = true;
+	} else {
+		if (BT_8821A_2ANT_BT_STATUS_NON_CONNECTED_IDLE ==
+		    coex_dm->bt_status) {
+			low_pwr_disable = false;
+			btcoexist->btc_set(btcoexist,
+					   BTC_SET_ACT_DISABLE_LOW_POWER,
+					   &low_pwr_disable);
+			halbtc8821a2ant_limited_rx(btcoexist, NORMAL_EXEC,
+						   false, false, 0x8);
+
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				"[BTCoex], Wifi connected + BT non connected-idle!!\n");
+			BTC_TRACE(trace_buf);
+
+			btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1,
+						  0xfffff, 0x0);
+			halbtc8821a2ant_coex_table_with_type(btcoexist,
+							     NORMAL_EXEC, 0);
+
+			halbtc8821a2ant_ps_tdma(btcoexist, NORMAL_EXEC, false,
+						1);
+			halbtc8821a2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC,
+							 0xb);
+			halbtc8821a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);
+
+			halbtc8821a2ant_sw_mechanism1(btcoexist, false, false,
+						      false,
+						      false);
+			halbtc8821a2ant_sw_mechanism2(btcoexist, false, false,
+						      false, 0x18);
+
+			common = true;
+		} else if (BT_8821A_2ANT_BT_STATUS_CONNECTED_IDLE ==
+			   coex_dm->bt_status) {
+			low_pwr_disable = true;
+			btcoexist->btc_set(btcoexist,
+					   BTC_SET_ACT_DISABLE_LOW_POWER,
+					   &low_pwr_disable);
+
+			if (bt_hs_on)
+				return false;
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				"[BTCoex], Wifi connected + BT connected-idle!!\n");
+			BTC_TRACE(trace_buf);
+			halbtc8821a2ant_limited_rx(btcoexist, NORMAL_EXEC,
+						   false, false, 0x8);
+
+			btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1,
+						  0xfffff, 0x0);
+			halbtc8821a2ant_coex_table_with_type(btcoexist,
+							     NORMAL_EXEC, 0);
+
+			halbtc8821a2ant_ps_tdma(btcoexist, NORMAL_EXEC, false,
+						1);
+			halbtc8821a2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC,
+							 0xb);
+			halbtc8821a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);
+
+			halbtc8821a2ant_sw_mechanism1(btcoexist, true, false,
+						      false, false);
+			halbtc8821a2ant_sw_mechanism2(btcoexist, false, false,
+						      false, 0x18);
+
+			common = true;
+		} else {
+			low_pwr_disable = true;
+			btcoexist->btc_set(btcoexist,
+					   BTC_SET_ACT_DISABLE_LOW_POWER,
+					   &low_pwr_disable);
+
+			if (wifi_busy) {
+				BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+					"[BTCoex], Wifi Connected-Busy + BT Busy!!\n");
+				BTC_TRACE(trace_buf);
+				common = false;
+				/* common = halbtc8821a2ant_action_wifi_idle_process(btcoexist);	 */
+			} else {
+				BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+					"[BTCoex], Wifi Connected-Idle + BT Busy!!\n");
+				BTC_TRACE(trace_buf);
+				/* common = false;	 */
+				common = halbtc8821a2ant_action_wifi_idle_process(
+						 btcoexist);
+			}
+		}
+	}
+
+	return common;
+}
+void halbtc8821a2ant_tdma_duration_adjust(IN struct btc_coexist *btcoexist,
+		IN boolean sco_hid, IN boolean tx_pause, IN u8 max_interval)
+{
+	static s32		up, dn, m, n, wait_count;
+	s32			result;   /* 0: no change, +1: increase WiFi duration, -1: decrease WiFi duration */
+	u8			retry_count = 0;
+
+	if (!coex_dm->auto_tdma_adjust) {
+		coex_dm->auto_tdma_adjust = true;
+		{
+			if (sco_hid) {
+				if (tx_pause) {
+					if (max_interval == 1) {
+						halbtc8821a2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 13);
+						coex_dm->ps_tdma_du_adj_type =
+							13;
+					} else if (max_interval == 2) {
+						halbtc8821a2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 14);
+						coex_dm->ps_tdma_du_adj_type =
+							14;
+					} else if (max_interval == 3) {
+						halbtc8821a2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 15);
+						coex_dm->ps_tdma_du_adj_type =
+							15;
+					} else {
+						halbtc8821a2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 15);
+						coex_dm->ps_tdma_du_adj_type =
+							15;
+					}
+				} else {
+					if (max_interval == 1) {
+						halbtc8821a2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 9);
+						coex_dm->ps_tdma_du_adj_type =
+							9;
+					} else if (max_interval == 2) {
+						halbtc8821a2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 10);
+						coex_dm->ps_tdma_du_adj_type =
+							10;
+					} else if (max_interval == 3) {
+						halbtc8821a2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 11);
+						coex_dm->ps_tdma_du_adj_type =
+							11;
+					} else {
+						halbtc8821a2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 11);
+						coex_dm->ps_tdma_du_adj_type =
+							11;
+					}
+				}
+			} else {
+				if (tx_pause) {
+					if (max_interval == 1) {
+						halbtc8821a2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 5);
+						coex_dm->ps_tdma_du_adj_type =
+							5;
+					} else if (max_interval == 2) {
+						halbtc8821a2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 6);
+						coex_dm->ps_tdma_du_adj_type =
+							6;
+					} else if (max_interval == 3) {
+						halbtc8821a2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 7);
+						coex_dm->ps_tdma_du_adj_type =
+							7;
+					} else {
+						halbtc8821a2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 7);
+						coex_dm->ps_tdma_du_adj_type =
+							7;
+					}
+				} else {
+					if (max_interval == 1) {
+						halbtc8821a2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 1);
+						coex_dm->ps_tdma_du_adj_type =
+							1;
+					} else if (max_interval == 2) {
+						halbtc8821a2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 2);
+						coex_dm->ps_tdma_du_adj_type =
+							2;
+					} else if (max_interval == 3) {
+						halbtc8821a2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 3);
+						coex_dm->ps_tdma_du_adj_type =
+							3;
+					} else {
+						halbtc8821a2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 3);
+						coex_dm->ps_tdma_du_adj_type =
+							3;
+					}
+				}
+			}
+		}
+		/* ============ */
+		up = 0;
+		dn = 0;
+		m = 1;
+		n = 3;
+		result = 0;
+		wait_count = 0;
+	} else {
+		/* acquire the BT TRx retry count from BT_Info byte2 */
+		retry_count = coex_sta->bt_retry_cnt;
+		result = 0;
+		wait_count++;
+
+		if (retry_count ==
+		    0) { /* no retry in the last 2-second duration */
+			up++;
+			dn--;
+
+			if (dn <= 0)
+				dn = 0;
+
+			if (up >= n) {	/* if �s�� n ��2�� retry count��0, �h�ռeWiFi duration */
+				wait_count = 0;
+				n = 3;
+				up = 0;
+				dn = 0;
+				result = 1;
+			}
+		} else if (retry_count <=
+			   3) {	/* <=3 retry in the last 2-second duration */
+			up--;
+			dn++;
+
+			if (up <= 0)
+				up = 0;
+
+			if (dn == 2) {	/* if �s�� 2 ��2�� retry count< 3, �h�կ�WiFi duration */
+				if (wait_count <= 2)
+					m++; /* �קK�@���b���level���Ӧ^ */
+				else
+					m = 1;
+
+				if (m >= 20)  /* m �̤j�� = 20 ' �̤j120�� recheck�O�_�վ� WiFi duration. */
+					m = 20;
+
+				n = 3 * m;
+				up = 0;
+				dn = 0;
+				wait_count = 0;
+				result = -1;
+			}
+		} else { /* retry count > 3, �u�n1�� retry count > 3, �h�կ�WiFi duration */
+			if (wait_count == 1)
+				m++; /* �קK�@���b���level���Ӧ^ */
+			else
+				m = 1;
+
+			if (m >= 20)  /* m �̤j�� = 20 ' �̤j120�� recheck�O�_�վ� WiFi duration. */
+				m = 20;
+
+			n = 3 * m;
+			up = 0;
+			dn = 0;
+			wait_count = 0;
+			result = -1;
+		}
+
+		if (max_interval == 1) {
+			if (tx_pause) {
+				if (coex_dm->cur_ps_tdma == 71) {
+					halbtc8821a2ant_ps_tdma(btcoexist,
+							NORMAL_EXEC, true, 5);
+					coex_dm->ps_tdma_du_adj_type = 5;
+				} else if (coex_dm->cur_ps_tdma == 1) {
+					halbtc8821a2ant_ps_tdma(btcoexist,
+							NORMAL_EXEC, true, 5);
+					coex_dm->ps_tdma_du_adj_type = 5;
+				} else if (coex_dm->cur_ps_tdma == 2) {
+					halbtc8821a2ant_ps_tdma(btcoexist,
+							NORMAL_EXEC, true, 6);
+					coex_dm->ps_tdma_du_adj_type = 6;
+				} else if (coex_dm->cur_ps_tdma == 3) {
+					halbtc8821a2ant_ps_tdma(btcoexist,
+							NORMAL_EXEC, true, 7);
+					coex_dm->ps_tdma_du_adj_type = 7;
+				} else if (coex_dm->cur_ps_tdma == 4) {
+					halbtc8821a2ant_ps_tdma(btcoexist,
+							NORMAL_EXEC, true, 8);
+					coex_dm->ps_tdma_du_adj_type = 8;
+				}
+				if (coex_dm->cur_ps_tdma == 9) {
+					halbtc8821a2ant_ps_tdma(btcoexist,
+							NORMAL_EXEC, true, 13);
+					coex_dm->ps_tdma_du_adj_type = 13;
+				} else if (coex_dm->cur_ps_tdma == 10) {
+					halbtc8821a2ant_ps_tdma(btcoexist,
+							NORMAL_EXEC, true, 14);
+					coex_dm->ps_tdma_du_adj_type = 14;
+				} else if (coex_dm->cur_ps_tdma == 11) {
+					halbtc8821a2ant_ps_tdma(btcoexist,
+							NORMAL_EXEC, true, 15);
+					coex_dm->ps_tdma_du_adj_type = 15;
+				} else if (coex_dm->cur_ps_tdma == 12) {
+					halbtc8821a2ant_ps_tdma(btcoexist,
+							NORMAL_EXEC, true, 16);
+					coex_dm->ps_tdma_du_adj_type = 16;
+				}
+
+				if (result == -1) {
+					if (coex_dm->cur_ps_tdma == 5) {
+						halbtc8821a2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 6);
+						coex_dm->ps_tdma_du_adj_type =
+							6;
+					} else if (coex_dm->cur_ps_tdma == 6) {
+						halbtc8821a2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 7);
+						coex_dm->ps_tdma_du_adj_type =
+							7;
+					} else if (coex_dm->cur_ps_tdma == 7) {
+						halbtc8821a2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 8);
+						coex_dm->ps_tdma_du_adj_type =
+							8;
+					} else if (coex_dm->cur_ps_tdma == 13) {
+						halbtc8821a2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 14);
+						coex_dm->ps_tdma_du_adj_type =
+							14;
+					} else if (coex_dm->cur_ps_tdma == 14) {
+						halbtc8821a2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 15);
+						coex_dm->ps_tdma_du_adj_type =
+							15;
+					} else if (coex_dm->cur_ps_tdma == 15) {
+						halbtc8821a2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 16);
+						coex_dm->ps_tdma_du_adj_type =
+							16;
+					}
+				} else if (result == 1) {
+					if (coex_dm->cur_ps_tdma == 8) {
+						halbtc8821a2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 7);
+						coex_dm->ps_tdma_du_adj_type =
+							7;
+					} else if (coex_dm->cur_ps_tdma == 7) {
+						halbtc8821a2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 6);
+						coex_dm->ps_tdma_du_adj_type =
+							6;
+					} else if (coex_dm->cur_ps_tdma == 6) {
+						halbtc8821a2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 5);
+						coex_dm->ps_tdma_du_adj_type =
+							5;
+					} else if (coex_dm->cur_ps_tdma == 16) {
+						halbtc8821a2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 15);
+						coex_dm->ps_tdma_du_adj_type =
+							15;
+					} else if (coex_dm->cur_ps_tdma == 15) {
+						halbtc8821a2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 14);
+						coex_dm->ps_tdma_du_adj_type =
+							14;
+					} else if (coex_dm->cur_ps_tdma == 14) {
+						halbtc8821a2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 13);
+						coex_dm->ps_tdma_du_adj_type =
+							13;
+					}
+				}
+			} else {
+				if (coex_dm->cur_ps_tdma == 5) {
+					halbtc8821a2ant_ps_tdma(btcoexist,
+							NORMAL_EXEC, true, 71);
+					coex_dm->ps_tdma_du_adj_type = 71;
+				} else if (coex_dm->cur_ps_tdma == 6) {
+					halbtc8821a2ant_ps_tdma(btcoexist,
+							NORMAL_EXEC, true, 2);
+					coex_dm->ps_tdma_du_adj_type = 2;
+				} else if (coex_dm->cur_ps_tdma == 7) {
+					halbtc8821a2ant_ps_tdma(btcoexist,
+							NORMAL_EXEC, true, 3);
+					coex_dm->ps_tdma_du_adj_type = 3;
+				} else if (coex_dm->cur_ps_tdma == 8) {
+					halbtc8821a2ant_ps_tdma(btcoexist,
+							NORMAL_EXEC, true, 4);
+					coex_dm->ps_tdma_du_adj_type = 4;
+				}
+				if (coex_dm->cur_ps_tdma == 13) {
+					halbtc8821a2ant_ps_tdma(btcoexist,
+							NORMAL_EXEC, true, 9);
+					coex_dm->ps_tdma_du_adj_type = 9;
+				} else if (coex_dm->cur_ps_tdma == 14) {
+					halbtc8821a2ant_ps_tdma(btcoexist,
+							NORMAL_EXEC, true, 10);
+					coex_dm->ps_tdma_du_adj_type = 10;
+				} else if (coex_dm->cur_ps_tdma == 15) {
+					halbtc8821a2ant_ps_tdma(btcoexist,
+							NORMAL_EXEC, true, 11);
+					coex_dm->ps_tdma_du_adj_type = 11;
+				} else if (coex_dm->cur_ps_tdma == 16) {
+					halbtc8821a2ant_ps_tdma(btcoexist,
+							NORMAL_EXEC, true, 12);
+					coex_dm->ps_tdma_du_adj_type = 12;
+				}
+
+				if (result == -1) {
+					if (coex_dm->cur_ps_tdma == 71) {
+						halbtc8821a2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 1);
+						coex_dm->ps_tdma_du_adj_type =
+							1;
+					} else if (coex_dm->cur_ps_tdma == 1) {
+						halbtc8821a2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 2);
+						coex_dm->ps_tdma_du_adj_type =
+							2;
+					} else if (coex_dm->cur_ps_tdma == 2) {
+						halbtc8821a2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 3);
+						coex_dm->ps_tdma_du_adj_type =
+							3;
+					} else if (coex_dm->cur_ps_tdma == 3) {
+						halbtc8821a2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 4);
+						coex_dm->ps_tdma_du_adj_type =
+							4;
+					} else if (coex_dm->cur_ps_tdma == 9) {
+						halbtc8821a2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 10);
+						coex_dm->ps_tdma_du_adj_type =
+							10;
+					} else if (coex_dm->cur_ps_tdma == 10) {
+						halbtc8821a2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 11);
+						coex_dm->ps_tdma_du_adj_type =
+							11;
+					} else if (coex_dm->cur_ps_tdma == 11) {
+						halbtc8821a2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 12);
+						coex_dm->ps_tdma_du_adj_type =
+							12;
+					}
+				} else if (result == 1) {
+					if (coex_dm->cur_ps_tdma == 4) {
+						halbtc8821a2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 3);
+						coex_dm->ps_tdma_du_adj_type =
+							3;
+					} else if (coex_dm->cur_ps_tdma == 3) {
+						halbtc8821a2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 2);
+						coex_dm->ps_tdma_du_adj_type =
+							2;
+					} else if (coex_dm->cur_ps_tdma == 2) {
+						halbtc8821a2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 1);
+						coex_dm->ps_tdma_du_adj_type =
+							1;
+					} else if (coex_dm->cur_ps_tdma == 1) {
+						halbtc8821a2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 71);
+						coex_dm->ps_tdma_du_adj_type =
+							71;
+					} else if (coex_dm->cur_ps_tdma == 12) {
+						halbtc8821a2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 11);
+						coex_dm->ps_tdma_du_adj_type =
+							11;
+					} else if (coex_dm->cur_ps_tdma == 11) {
+						halbtc8821a2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 10);
+						coex_dm->ps_tdma_du_adj_type =
+							10;
+					} else if (coex_dm->cur_ps_tdma == 10) {
+						halbtc8821a2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 9);
+						coex_dm->ps_tdma_du_adj_type =
+							9;
+					}
+				}
+			}
+		} else if (max_interval == 2) {
+			if (tx_pause) {
+				if (coex_dm->cur_ps_tdma == 1) {
+					halbtc8821a2ant_ps_tdma(btcoexist,
+							NORMAL_EXEC, true, 6);
+					coex_dm->ps_tdma_du_adj_type = 6;
+				} else if (coex_dm->cur_ps_tdma == 2) {
+					halbtc8821a2ant_ps_tdma(btcoexist,
+							NORMAL_EXEC, true, 6);
+					coex_dm->ps_tdma_du_adj_type = 6;
+				} else if (coex_dm->cur_ps_tdma == 3) {
+					halbtc8821a2ant_ps_tdma(btcoexist,
+							NORMAL_EXEC, true, 7);
+					coex_dm->ps_tdma_du_adj_type = 7;
+				} else if (coex_dm->cur_ps_tdma == 4) {
+					halbtc8821a2ant_ps_tdma(btcoexist,
+							NORMAL_EXEC, true, 8);
+					coex_dm->ps_tdma_du_adj_type = 8;
+				}
+				if (coex_dm->cur_ps_tdma == 9) {
+					halbtc8821a2ant_ps_tdma(btcoexist,
+							NORMAL_EXEC, true, 14);
+					coex_dm->ps_tdma_du_adj_type = 14;
+				} else if (coex_dm->cur_ps_tdma == 10) {
+					halbtc8821a2ant_ps_tdma(btcoexist,
+							NORMAL_EXEC, true, 14);
+					coex_dm->ps_tdma_du_adj_type = 14;
+				} else if (coex_dm->cur_ps_tdma == 11) {
+					halbtc8821a2ant_ps_tdma(btcoexist,
+							NORMAL_EXEC, true, 15);
+					coex_dm->ps_tdma_du_adj_type = 15;
+				} else if (coex_dm->cur_ps_tdma == 12) {
+					halbtc8821a2ant_ps_tdma(btcoexist,
+							NORMAL_EXEC, true, 16);
+					coex_dm->ps_tdma_du_adj_type = 16;
+				}
+				if (result == -1) {
+					if (coex_dm->cur_ps_tdma == 5) {
+						halbtc8821a2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 6);
+						coex_dm->ps_tdma_du_adj_type =
+							6;
+					} else if (coex_dm->cur_ps_tdma == 6) {
+						halbtc8821a2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 7);
+						coex_dm->ps_tdma_du_adj_type =
+							7;
+					} else if (coex_dm->cur_ps_tdma == 7) {
+						halbtc8821a2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 8);
+						coex_dm->ps_tdma_du_adj_type =
+							8;
+					} else if (coex_dm->cur_ps_tdma == 13) {
+						halbtc8821a2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 14);
+						coex_dm->ps_tdma_du_adj_type =
+							14;
+					} else if (coex_dm->cur_ps_tdma == 14) {
+						halbtc8821a2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 15);
+						coex_dm->ps_tdma_du_adj_type =
+							15;
+					} else if (coex_dm->cur_ps_tdma == 15) {
+						halbtc8821a2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 16);
+						coex_dm->ps_tdma_du_adj_type =
+							16;
+					}
+				} else if (result == 1) {
+					if (coex_dm->cur_ps_tdma == 8) {
+						halbtc8821a2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 7);
+						coex_dm->ps_tdma_du_adj_type =
+							7;
+					} else if (coex_dm->cur_ps_tdma == 7) {
+						halbtc8821a2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 6);
+						coex_dm->ps_tdma_du_adj_type =
+							6;
+					} else if (coex_dm->cur_ps_tdma == 6) {
+						halbtc8821a2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 6);
+						coex_dm->ps_tdma_du_adj_type =
+							6;
+					} else if (coex_dm->cur_ps_tdma == 16) {
+						halbtc8821a2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 15);
+						coex_dm->ps_tdma_du_adj_type =
+							15;
+					} else if (coex_dm->cur_ps_tdma == 15) {
+						halbtc8821a2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 14);
+						coex_dm->ps_tdma_du_adj_type =
+							14;
+					} else if (coex_dm->cur_ps_tdma == 14) {
+						halbtc8821a2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 14);
+						coex_dm->ps_tdma_du_adj_type =
+							14;
+					}
+				}
+			} else {
+				if (coex_dm->cur_ps_tdma == 5) {
+					halbtc8821a2ant_ps_tdma(btcoexist,
+							NORMAL_EXEC, true, 2);
+					coex_dm->ps_tdma_du_adj_type = 2;
+				} else if (coex_dm->cur_ps_tdma == 6) {
+					halbtc8821a2ant_ps_tdma(btcoexist,
+							NORMAL_EXEC, true, 2);
+					coex_dm->ps_tdma_du_adj_type = 2;
+				} else if (coex_dm->cur_ps_tdma == 7) {
+					halbtc8821a2ant_ps_tdma(btcoexist,
+							NORMAL_EXEC, true, 3);
+					coex_dm->ps_tdma_du_adj_type = 3;
+				} else if (coex_dm->cur_ps_tdma == 8) {
+					halbtc8821a2ant_ps_tdma(btcoexist,
+							NORMAL_EXEC, true, 4);
+					coex_dm->ps_tdma_du_adj_type = 4;
+				}
+				if (coex_dm->cur_ps_tdma == 13) {
+					halbtc8821a2ant_ps_tdma(btcoexist,
+							NORMAL_EXEC, true, 10);
+					coex_dm->ps_tdma_du_adj_type = 10;
+				} else if (coex_dm->cur_ps_tdma == 14) {
+					halbtc8821a2ant_ps_tdma(btcoexist,
+							NORMAL_EXEC, true, 10);
+					coex_dm->ps_tdma_du_adj_type = 10;
+				} else if (coex_dm->cur_ps_tdma == 15) {
+					halbtc8821a2ant_ps_tdma(btcoexist,
+							NORMAL_EXEC, true, 11);
+					coex_dm->ps_tdma_du_adj_type = 11;
+				} else if (coex_dm->cur_ps_tdma == 16) {
+					halbtc8821a2ant_ps_tdma(btcoexist,
+							NORMAL_EXEC, true, 12);
+					coex_dm->ps_tdma_du_adj_type = 12;
+				}
+				if (result == -1) {
+					if (coex_dm->cur_ps_tdma == 1) {
+						halbtc8821a2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 2);
+						coex_dm->ps_tdma_du_adj_type =
+							2;
+					} else if (coex_dm->cur_ps_tdma == 2) {
+						halbtc8821a2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 3);
+						coex_dm->ps_tdma_du_adj_type =
+							3;
+					} else if (coex_dm->cur_ps_tdma == 3) {
+						halbtc8821a2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 4);
+						coex_dm->ps_tdma_du_adj_type =
+							4;
+					} else if (coex_dm->cur_ps_tdma == 9) {
+						halbtc8821a2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 10);
+						coex_dm->ps_tdma_du_adj_type =
+							10;
+					} else if (coex_dm->cur_ps_tdma == 10) {
+						halbtc8821a2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 11);
+						coex_dm->ps_tdma_du_adj_type =
+							11;
+					} else if (coex_dm->cur_ps_tdma == 11) {
+						halbtc8821a2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 12);
+						coex_dm->ps_tdma_du_adj_type =
+							12;
+					}
+				} else if (result == 1) {
+					if (coex_dm->cur_ps_tdma == 4) {
+						halbtc8821a2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 3);
+						coex_dm->ps_tdma_du_adj_type =
+							3;
+					} else if (coex_dm->cur_ps_tdma == 3) {
+						halbtc8821a2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 2);
+						coex_dm->ps_tdma_du_adj_type =
+							2;
+					} else if (coex_dm->cur_ps_tdma == 2) {
+						halbtc8821a2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 2);
+						coex_dm->ps_tdma_du_adj_type =
+							2;
+					} else if (coex_dm->cur_ps_tdma == 12) {
+						halbtc8821a2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 11);
+						coex_dm->ps_tdma_du_adj_type =
+							11;
+					} else if (coex_dm->cur_ps_tdma == 11) {
+						halbtc8821a2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 10);
+						coex_dm->ps_tdma_du_adj_type =
+							10;
+					} else if (coex_dm->cur_ps_tdma == 10) {
+						halbtc8821a2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 10);
+						coex_dm->ps_tdma_du_adj_type =
+							10;
+					}
+				}
+			}
+		} else if (max_interval == 3) {
+			if (tx_pause) {
+				if (coex_dm->cur_ps_tdma == 1) {
+					halbtc8821a2ant_ps_tdma(btcoexist,
+							NORMAL_EXEC, true, 7);
+					coex_dm->ps_tdma_du_adj_type = 7;
+				} else if (coex_dm->cur_ps_tdma == 2) {
+					halbtc8821a2ant_ps_tdma(btcoexist,
+							NORMAL_EXEC, true, 7);
+					coex_dm->ps_tdma_du_adj_type = 7;
+				} else if (coex_dm->cur_ps_tdma == 3) {
+					halbtc8821a2ant_ps_tdma(btcoexist,
+							NORMAL_EXEC, true, 7);
+					coex_dm->ps_tdma_du_adj_type = 7;
+				} else if (coex_dm->cur_ps_tdma == 4) {
+					halbtc8821a2ant_ps_tdma(btcoexist,
+							NORMAL_EXEC, true, 8);
+					coex_dm->ps_tdma_du_adj_type = 8;
+				}
+				if (coex_dm->cur_ps_tdma == 9) {
+					halbtc8821a2ant_ps_tdma(btcoexist,
+							NORMAL_EXEC, true, 15);
+					coex_dm->ps_tdma_du_adj_type = 15;
+				} else if (coex_dm->cur_ps_tdma == 10) {
+					halbtc8821a2ant_ps_tdma(btcoexist,
+							NORMAL_EXEC, true, 15);
+					coex_dm->ps_tdma_du_adj_type = 15;
+				} else if (coex_dm->cur_ps_tdma == 11) {
+					halbtc8821a2ant_ps_tdma(btcoexist,
+							NORMAL_EXEC, true, 15);
+					coex_dm->ps_tdma_du_adj_type = 15;
+				} else if (coex_dm->cur_ps_tdma == 12) {
+					halbtc8821a2ant_ps_tdma(btcoexist,
+							NORMAL_EXEC, true, 16);
+					coex_dm->ps_tdma_du_adj_type = 16;
+				}
+				if (result == -1) {
+					if (coex_dm->cur_ps_tdma == 5) {
+						halbtc8821a2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 7);
+						coex_dm->ps_tdma_du_adj_type =
+							7;
+					} else if (coex_dm->cur_ps_tdma == 6) {
+						halbtc8821a2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 7);
+						coex_dm->ps_tdma_du_adj_type =
+							7;
+					} else if (coex_dm->cur_ps_tdma == 7) {
+						halbtc8821a2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 8);
+						coex_dm->ps_tdma_du_adj_type =
+							8;
+					} else if (coex_dm->cur_ps_tdma == 13) {
+						halbtc8821a2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 15);
+						coex_dm->ps_tdma_du_adj_type =
+							15;
+					} else if (coex_dm->cur_ps_tdma == 14) {
+						halbtc8821a2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 15);
+						coex_dm->ps_tdma_du_adj_type =
+							15;
+					} else if (coex_dm->cur_ps_tdma == 15) {
+						halbtc8821a2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 16);
+						coex_dm->ps_tdma_du_adj_type =
+							16;
+					}
+				} else if (result == 1) {
+					if (coex_dm->cur_ps_tdma == 8) {
+						halbtc8821a2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 7);
+						coex_dm->ps_tdma_du_adj_type =
+							7;
+					} else if (coex_dm->cur_ps_tdma == 7) {
+						halbtc8821a2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 7);
+						coex_dm->ps_tdma_du_adj_type =
+							7;
+					} else if (coex_dm->cur_ps_tdma == 6) {
+						halbtc8821a2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 7);
+						coex_dm->ps_tdma_du_adj_type =
+							7;
+					} else if (coex_dm->cur_ps_tdma == 16) {
+						halbtc8821a2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 15);
+						coex_dm->ps_tdma_du_adj_type =
+							15;
+					} else if (coex_dm->cur_ps_tdma == 15) {
+						halbtc8821a2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 15);
+						coex_dm->ps_tdma_du_adj_type =
+							15;
+					} else if (coex_dm->cur_ps_tdma == 14) {
+						halbtc8821a2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 15);
+						coex_dm->ps_tdma_du_adj_type =
+							15;
+					}
+				}
+			} else {
+				if (coex_dm->cur_ps_tdma == 5) {
+					halbtc8821a2ant_ps_tdma(btcoexist,
+							NORMAL_EXEC, true, 3);
+					coex_dm->ps_tdma_du_adj_type = 3;
+				} else if (coex_dm->cur_ps_tdma == 6) {
+					halbtc8821a2ant_ps_tdma(btcoexist,
+							NORMAL_EXEC, true, 3);
+					coex_dm->ps_tdma_du_adj_type = 3;
+				} else if (coex_dm->cur_ps_tdma == 7) {
+					halbtc8821a2ant_ps_tdma(btcoexist,
+							NORMAL_EXEC, true, 3);
+					coex_dm->ps_tdma_du_adj_type = 3;
+				} else if (coex_dm->cur_ps_tdma == 8) {
+					halbtc8821a2ant_ps_tdma(btcoexist,
+							NORMAL_EXEC, true, 4);
+					coex_dm->ps_tdma_du_adj_type = 4;
+				}
+				if (coex_dm->cur_ps_tdma == 13) {
+					halbtc8821a2ant_ps_tdma(btcoexist,
+							NORMAL_EXEC, true, 11);
+					coex_dm->ps_tdma_du_adj_type = 11;
+				} else if (coex_dm->cur_ps_tdma == 14) {
+					halbtc8821a2ant_ps_tdma(btcoexist,
+							NORMAL_EXEC, true, 11);
+					coex_dm->ps_tdma_du_adj_type = 11;
+				} else if (coex_dm->cur_ps_tdma == 15) {
+					halbtc8821a2ant_ps_tdma(btcoexist,
+							NORMAL_EXEC, true, 11);
+					coex_dm->ps_tdma_du_adj_type = 11;
+				} else if (coex_dm->cur_ps_tdma == 16) {
+					halbtc8821a2ant_ps_tdma(btcoexist,
+							NORMAL_EXEC, true, 12);
+					coex_dm->ps_tdma_du_adj_type = 12;
+				}
+				if (result == -1) {
+					if (coex_dm->cur_ps_tdma == 1) {
+						halbtc8821a2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 3);
+						coex_dm->ps_tdma_du_adj_type =
+							3;
+					} else if (coex_dm->cur_ps_tdma == 2) {
+						halbtc8821a2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 3);
+						coex_dm->ps_tdma_du_adj_type =
+							3;
+					} else if (coex_dm->cur_ps_tdma == 3) {
+						halbtc8821a2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 4);
+						coex_dm->ps_tdma_du_adj_type =
+							4;
+					} else if (coex_dm->cur_ps_tdma == 9) {
+						halbtc8821a2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 11);
+						coex_dm->ps_tdma_du_adj_type =
+							11;
+					} else if (coex_dm->cur_ps_tdma == 10) {
+						halbtc8821a2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 11);
+						coex_dm->ps_tdma_du_adj_type =
+							11;
+					} else if (coex_dm->cur_ps_tdma == 11) {
+						halbtc8821a2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 12);
+						coex_dm->ps_tdma_du_adj_type =
+							12;
+					}
+				} else if (result == 1) {
+					if (coex_dm->cur_ps_tdma == 4) {
+						halbtc8821a2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 3);
+						coex_dm->ps_tdma_du_adj_type =
+							3;
+					} else if (coex_dm->cur_ps_tdma == 3) {
+						halbtc8821a2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 3);
+						coex_dm->ps_tdma_du_adj_type =
+							3;
+					} else if (coex_dm->cur_ps_tdma == 2) {
+						halbtc8821a2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 3);
+						coex_dm->ps_tdma_du_adj_type =
+							3;
+					} else if (coex_dm->cur_ps_tdma == 12) {
+						halbtc8821a2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 11);
+						coex_dm->ps_tdma_du_adj_type =
+							11;
+					} else if (coex_dm->cur_ps_tdma == 11) {
+						halbtc8821a2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 11);
+						coex_dm->ps_tdma_du_adj_type =
+							11;
+					} else if (coex_dm->cur_ps_tdma == 10) {
+						halbtc8821a2ant_ps_tdma(
+							btcoexist, NORMAL_EXEC,
+							true, 11);
+						coex_dm->ps_tdma_du_adj_type =
+							11;
+					}
+				}
+			}
+		}
+	}
+
+	/* if current PsTdma not match with the recorded one (when scan, dhcp...), */
+	/* then we have to adjust it back to the previous record one. */
+	if (coex_dm->cur_ps_tdma != coex_dm->ps_tdma_du_adj_type) {
+		boolean	scan = false, link = false, roam = false;
+
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			"[BTCoex], PsTdma type dismatch!!!, cur_ps_tdma=%d, recordPsTdma=%d\n",
+			    coex_dm->cur_ps_tdma, coex_dm->ps_tdma_du_adj_type);
+		BTC_TRACE(trace_buf);
+
+		btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_SCAN, &scan);
+		btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_LINK, &link);
+		btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_ROAM, &roam);
+
+		if (!scan && !link && !roam)
+			halbtc8821a2ant_ps_tdma(btcoexist, NORMAL_EXEC, true,
+						coex_dm->ps_tdma_du_adj_type);
+		else {
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				"[BTCoex], roaming/link/scan is under progress, will adjust next time!!!\n");
+			BTC_TRACE(trace_buf);
+		}
+	}
+}
+
+/* SCO only or SCO+PAN(HS) */
+void halbtc8821a2ant_action_sco(IN struct btc_coexist *btcoexist)
+{
+	struct  btc_bt_link_info	*bt_link_info = &btcoexist->bt_link_info;
+	u8	wifi_rssi_state, bt_rssi_state;
+	u32	wifi_bw;
+
+	wifi_rssi_state = halbtc8821a2ant_wifi_rssi_state(btcoexist, 0, 2, 15,
+			  0);
+	bt_rssi_state = halbtc8821a2ant_bt_rssi_state(2,
+			BT_8821A_2ANT_BT_RSSI_COEXSWITCH_THRES, 0);
+
+	btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1, 0xfffff, 0x0);
+
+	halbtc8821a2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, 0x8);
+
+	halbtc8821a2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 4);
+
+	if (BTC_RSSI_HIGH(bt_rssi_state))
+		halbtc8821a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2);
+	else
+		halbtc8821a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);
+
+	btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw);
+
+	if (BTC_WIFI_BW_LEGACY == wifi_bw) /* for SCO quality at 11b/g mode */
+		halbtc8821a2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 2);
+	else { /* for SCO quality & wifi performance balance at 11n mode */
+		if (BTC_WIFI_BW_HT40 == wifi_bw)
+			halbtc8821a2ant_coex_table_with_type(btcoexist,
+							     NORMAL_EXEC, 8);
+		else {
+			if (bt_link_info->sco_only)
+				halbtc8821a2ant_coex_table_with_type(btcoexist,
+							     NORMAL_EXEC, 17);
+			else
+				halbtc8821a2ant_coex_table_with_type(btcoexist,
+							     NORMAL_EXEC, 12);
+		}
+	}
+
+	halbtc8821a2ant_ps_tdma(btcoexist, NORMAL_EXEC, false,
+				0); /* for voice quality */
+
+	/* sw mechanism */
+	if (BTC_WIFI_BW_HT40 == wifi_bw) {
+		if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) ||
+		    (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
+			halbtc8821a2ant_sw_mechanism1(btcoexist, true, true,
+						      false, false);
+			halbtc8821a2ant_sw_mechanism2(btcoexist, true, false,
+						      true, 0x18);
+		} else {
+			halbtc8821a2ant_sw_mechanism1(btcoexist, true, true,
+						      false, false);
+			halbtc8821a2ant_sw_mechanism2(btcoexist, false, false,
+						      true, 0x18);
+		}
+	} else {
+		if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) ||
+		    (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
+			halbtc8821a2ant_sw_mechanism1(btcoexist, false, true,
+						      false, false);
+			halbtc8821a2ant_sw_mechanism2(btcoexist, true, false,
+						      true, 0x18);
+		} else {
+			halbtc8821a2ant_sw_mechanism1(btcoexist, false, true,
+						      false, false);
+			halbtc8821a2ant_sw_mechanism2(btcoexist, false, false,
+						      true, 0x18);
+		}
+	}
+}
+
+
+void halbtc8821a2ant_action_hid(IN struct btc_coexist *btcoexist)
+{
+	u8	wifi_rssi_state, bt_rssi_state;
+	u32	wifi_bw;
+
+	btcoexist->btc_phydm_modify_RA_PCR_threshold(btcoexist, 0, 25);
+
+	wifi_rssi_state = halbtc8821a2ant_wifi_rssi_state(btcoexist, 0, 2, 15,
+			  0);
+	bt_rssi_state = halbtc8821a2ant_bt_rssi_state(2,
+			BT_8821A_2ANT_BT_RSSI_COEXSWITCH_THRES, 0);
+
+	btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1, 0xfffff, 0x0);
+
+	halbtc8821a2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, 0x8);
+
+	halbtc8821a2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6);
+
+	if (BTC_RSSI_HIGH(bt_rssi_state))
+		halbtc8821a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2);
+	else
+		halbtc8821a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);
+
+	btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw);
+
+	if (BTC_WIFI_BW_LEGACY == wifi_bw) /* for HID at 11b/g mode */
+		halbtc8821a2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 7);
+	else  /* for HID quality & wifi performance balance at 11n mode */
+		halbtc8821a2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 2);
+
+	halbtc8821a2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 24);
+
+	/* sw mechanism */
+	if (BTC_WIFI_BW_HT40 == wifi_bw) {
+		if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) ||
+		    (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
+			halbtc8821a2ant_sw_mechanism1(btcoexist, true, true,
+						      false, false);
+			halbtc8821a2ant_sw_mechanism2(btcoexist, true, false,
+						      false, 0x18);
+		} else {
+			halbtc8821a2ant_sw_mechanism1(btcoexist, true, true,
+						      false, false);
+			halbtc8821a2ant_sw_mechanism2(btcoexist, false, false,
+						      false, 0x18);
+		}
+	} else {
+		if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) ||
+		    (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
+			halbtc8821a2ant_sw_mechanism1(btcoexist, false, true,
+						      false, false);
+			halbtc8821a2ant_sw_mechanism2(btcoexist, true, false,
+						      false, 0x18);
+		} else {
+			halbtc8821a2ant_sw_mechanism1(btcoexist, false, true,
+						      false, false);
+			halbtc8821a2ant_sw_mechanism2(btcoexist, false, false,
+						      false, 0x18);
+		}
+	}
+}
+
+/* A2DP only / PAN(EDR) only/ A2DP+PAN(HS) */
+void halbtc8821a2ant_action_a2dp(IN struct btc_coexist *btcoexist)
+{
+	u8		wifi_rssi_state, wifi_rssi_state1, bt_rssi_state;
+	u32		wifi_bw;
+	u8		ap_num = 0;
+
+	wifi_rssi_state = halbtc8821a2ant_wifi_rssi_state(btcoexist, 0, 2, 15,
+			  0);
+	wifi_rssi_state1 = halbtc8821a2ant_wifi_rssi_state(btcoexist, 1, 2,
+			   BT_8821A_2ANT_WIFI_RSSI_COEXSWITCH_THRES, 0);
+	bt_rssi_state = halbtc8821a2ant_bt_rssi_state(2,
+			BT_8821A_2ANT_BT_RSSI_COEXSWITCH_THRES, 0);
+
+	btcoexist->btc_get(btcoexist, BTC_GET_U1_AP_NUM, &ap_num);
+
+	/* define the office environment */
+	if ((ap_num >= 10) && BTC_RSSI_HIGH(wifi_rssi_state1) &&
+	    BTC_RSSI_HIGH(bt_rssi_state)) {
+		/* dbg_print(" AP#>10(%d)\n", ap_num); */
+
+		btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1, 0xfffff,
+					  0x0);
+		halbtc8821a2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false,
+					   0x8);
+		halbtc8821a2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6);
+		halbtc8821a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2);
+
+		halbtc8821a2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0);
+
+		/* halbtc8821a2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 1); */
+		halbtc8821a2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 23);
+
+		/* sw mechanism */
+		btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw);
+		if (BTC_WIFI_BW_HT40 == wifi_bw) {
+			halbtc8821a2ant_sw_mechanism1(btcoexist, true, false,
+						      false, false);
+			halbtc8821a2ant_sw_mechanism2(btcoexist, true, false,
+						      true, 0x6);
+		} else {
+			halbtc8821a2ant_sw_mechanism1(btcoexist, false, false,
+						      false, false);
+			halbtc8821a2ant_sw_mechanism2(btcoexist, true, false,
+						      true, 0x6);
+		}
+		return;
+
+	}
+
+	btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1, 0xfffff, 0x0);
+	halbtc8821a2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, 0x8);
+
+	halbtc8821a2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6);
+
+	if (BTC_RSSI_HIGH(bt_rssi_state))
+		halbtc8821a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2);
+	else
+		halbtc8821a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);
+
+
+	if ((bt_rssi_state == BTC_RSSI_STATE_HIGH) ||
+	    (bt_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
+		/* halbtc8821a2ant_tdma_duration_adjust(btcoexist, false, false, 1); */
+		halbtc8821a2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 23);
+	} else {
+		/* halbtc8821a2ant_tdma_duration_adjust(btcoexist, false, true, 1); */
+		halbtc8821a2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 23);
+	}
+
+	/* sw mechanism */
+	btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw);
+	if (BTC_WIFI_BW_HT40 == wifi_bw) {
+		if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) ||
+		    (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
+			halbtc8821a2ant_sw_mechanism1(btcoexist, true, false,
+						      false, false);
+			halbtc8821a2ant_sw_mechanism2(btcoexist, true, false,
+						      false, 0x18);
+		} else {
+			halbtc8821a2ant_sw_mechanism1(btcoexist, true, false,
+						      false, false);
+			halbtc8821a2ant_sw_mechanism2(btcoexist, false, false,
+						      false, 0x18);
+		}
+	} else {
+		if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) ||
+		    (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
+			halbtc8821a2ant_sw_mechanism1(btcoexist, false, false,
+						      false, false);
+			halbtc8821a2ant_sw_mechanism2(btcoexist, true, false,
+						      false, 0x18);
+		} else {
+			halbtc8821a2ant_sw_mechanism1(btcoexist, false, false,
+						      false, false);
+			halbtc8821a2ant_sw_mechanism2(btcoexist, false, false,
+						      false, 0x18);
+		}
+	}
+}
+
+void halbtc8821a2ant_action_a2dp_pan_hs(IN struct btc_coexist *btcoexist)
+{
+	u8		wifi_rssi_state, wifi_rssi_state1, bt_rssi_state;
+	u32		wifi_bw;
+
+	wifi_rssi_state = halbtc8821a2ant_wifi_rssi_state(btcoexist, 0, 2, 15,
+			  0);
+	wifi_rssi_state1 = halbtc8821a2ant_wifi_rssi_state(btcoexist, 1, 2,
+			   BT_8821A_2ANT_WIFI_RSSI_COEXSWITCH_THRES, 0);
+	bt_rssi_state = halbtc8821a2ant_bt_rssi_state(2,
+			BT_8821A_2ANT_BT_RSSI_COEXSWITCH_THRES, 0);
+
+	btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1, 0xfffff, 0x0);
+
+	halbtc8821a2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, 0x8);
+
+	halbtc8821a2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6);
+
+	if (BTC_RSSI_HIGH(bt_rssi_state))
+		halbtc8821a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2);
+	else
+		halbtc8821a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);
+
+	if (BTC_RSSI_HIGH(wifi_rssi_state1) && BTC_RSSI_HIGH(bt_rssi_state)) {
+		halbtc8821a2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 7);
+	} else {
+		halbtc8821a2ant_coex_table_with_type(btcoexist, NORMAL_EXEC,
+						     13);
+	}
+
+	halbtc8821a2ant_tdma_duration_adjust(btcoexist, false, true, 2);
+
+	/* sw mechanism */
+	btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw);
+	if (BTC_WIFI_BW_HT40 == wifi_bw) {
+		if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) ||
+		    (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
+			halbtc8821a2ant_sw_mechanism1(btcoexist, true, false,
+						      false, false);
+			halbtc8821a2ant_sw_mechanism2(btcoexist, true, false,
+						      false, 0x18);
+		} else {
+			halbtc8821a2ant_sw_mechanism1(btcoexist, true, false,
+						      false, false);
+			halbtc8821a2ant_sw_mechanism2(btcoexist, false, false,
+						      false, 0x18);
+		}
+	} else {
+		if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) ||
+		    (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
+			halbtc8821a2ant_sw_mechanism1(btcoexist, false, false,
+						      false, false);
+			halbtc8821a2ant_sw_mechanism2(btcoexist, true, false,
+						      false, 0x18);
+		} else {
+			halbtc8821a2ant_sw_mechanism1(btcoexist, false, false,
+						      false, false);
+			halbtc8821a2ant_sw_mechanism2(btcoexist, false, false,
+						      false, 0x18);
+		}
+	}
+}
+
+void halbtc8821a2ant_action_pan_edr(IN struct btc_coexist *btcoexist)
+{
+	u8		wifi_rssi_state, wifi_rssi_state1, bt_rssi_state;
+	u32		wifi_bw;
+
+	wifi_rssi_state = halbtc8821a2ant_wifi_rssi_state(btcoexist, 0, 2, 15,
+			  0);
+	wifi_rssi_state1 = halbtc8821a2ant_wifi_rssi_state(btcoexist, 1, 2,
+			   BT_8821A_2ANT_WIFI_RSSI_COEXSWITCH_THRES, 0);
+	bt_rssi_state = halbtc8821a2ant_bt_rssi_state(2,
+			BT_8821A_2ANT_BT_RSSI_COEXSWITCH_THRES, 0);
+
+	btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1, 0xfffff, 0x0);
+
+	halbtc8821a2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, 0x8);
+
+	halbtc8821a2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6);
+
+	if (BTC_RSSI_HIGH(bt_rssi_state))
+		halbtc8821a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2);
+	else
+		halbtc8821a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);
+
+	if (BTC_RSSI_HIGH(wifi_rssi_state1) && BTC_RSSI_HIGH(bt_rssi_state)) {
+		halbtc8821a2ant_coex_table_with_type(btcoexist, NORMAL_EXEC,
+						     10);
+	} else {
+		halbtc8821a2ant_coex_table_with_type(btcoexist, NORMAL_EXEC,
+						     13);
+	}
+
+	if ((bt_rssi_state == BTC_RSSI_STATE_HIGH) ||
+	    (bt_rssi_state == BTC_RSSI_STATE_STAY_HIGH))
+		halbtc8821a2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 26);
+	else
+		halbtc8821a2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 26);
+
+	/* sw mechanism */
+	btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw);
+	if (BTC_WIFI_BW_HT40 == wifi_bw) {
+		if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) ||
+		    (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
+			halbtc8821a2ant_sw_mechanism1(btcoexist, true, false,
+						      false, false);
+			halbtc8821a2ant_sw_mechanism2(btcoexist, true, false,
+						      false, 0x18);
+		} else {
+			halbtc8821a2ant_sw_mechanism1(btcoexist, true, false,
+						      false, false);
+			halbtc8821a2ant_sw_mechanism2(btcoexist, false, false,
+						      false, 0x18);
+		}
+	} else {
+		if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) ||
+		    (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
+			halbtc8821a2ant_sw_mechanism1(btcoexist, false, false,
+						      false, false);
+			halbtc8821a2ant_sw_mechanism2(btcoexist, true, false,
+						      false, 0x18);
+		} else {
+			halbtc8821a2ant_sw_mechanism1(btcoexist, false, false,
+						      false, false);
+			halbtc8821a2ant_sw_mechanism2(btcoexist, false, false,
+						      false, 0x18);
+		}
+	}
+}
+
+
+/* PAN(HS) only */
+void halbtc8821a2ant_action_pan_hs(IN struct btc_coexist *btcoexist)
+{
+	u8		wifi_rssi_state, wifi_rssi_state1, bt_rssi_state;
+	u32		wifi_bw;
+
+	wifi_rssi_state = halbtc8821a2ant_wifi_rssi_state(btcoexist, 0, 2, 15,
+			  0);
+	wifi_rssi_state1 = halbtc8821a2ant_wifi_rssi_state(btcoexist, 1, 2,
+			   BT_8821A_2ANT_WIFI_RSSI_COEXSWITCH_THRES, 0);
+	bt_rssi_state = halbtc8821a2ant_bt_rssi_state(2,
+			BT_8821A_2ANT_BT_RSSI_COEXSWITCH_THRES, 0);
+
+	btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1, 0xfffff, 0x0);
+
+	halbtc8821a2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, 0x8);
+
+	halbtc8821a2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6);
+
+	if (BTC_RSSI_HIGH(bt_rssi_state))
+		halbtc8821a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2);
+	else
+		halbtc8821a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);
+
+	halbtc8821a2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 7);
+
+	halbtc8821a2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 1);
+
+	btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw);
+	if (BTC_WIFI_BW_HT40 == wifi_bw) {
+		if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) ||
+		    (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
+			halbtc8821a2ant_sw_mechanism1(btcoexist, true, false,
+						      false, false);
+			halbtc8821a2ant_sw_mechanism2(btcoexist, true, false,
+						      false, 0x18);
+		} else {
+			halbtc8821a2ant_sw_mechanism1(btcoexist, true, false,
+						      false, false);
+			halbtc8821a2ant_sw_mechanism2(btcoexist, false, false,
+						      false, 0x18);
+		}
+	} else {
+		if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) ||
+		    (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
+			halbtc8821a2ant_sw_mechanism1(btcoexist, false, false,
+						      false, false);
+			halbtc8821a2ant_sw_mechanism2(btcoexist, true, false,
+						      false, 0x18);
+		} else {
+			halbtc8821a2ant_sw_mechanism1(btcoexist, false, false,
+						      false, false);
+			halbtc8821a2ant_sw_mechanism2(btcoexist, false, false,
+						      false, 0x18);
+		}
+	}
+}
+
+/* PAN(EDR)+A2DP */
+void halbtc8821a2ant_action_pan_edr_a2dp(IN struct btc_coexist *btcoexist)
+{
+	u8		wifi_rssi_state, wifi_rssi_state1, bt_rssi_state;
+	u32		wifi_bw;
+
+	wifi_rssi_state = halbtc8821a2ant_wifi_rssi_state(btcoexist, 0, 2, 15,
+			  0);
+	wifi_rssi_state1 = halbtc8821a2ant_wifi_rssi_state(btcoexist, 1, 2,
+			   BT_8821A_2ANT_WIFI_RSSI_COEXSWITCH_THRES, 0);
+	bt_rssi_state = halbtc8821a2ant_bt_rssi_state(2,
+			BT_8821A_2ANT_BT_RSSI_COEXSWITCH_THRES, 0);
+
+	btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1, 0xfffff, 0x0);
+
+	halbtc8821a2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, 0x8);
+
+	halbtc8821a2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6);
+
+	if (BTC_RSSI_HIGH(bt_rssi_state))
+		halbtc8821a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2);
+	else
+		halbtc8821a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);
+
+	btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw);
+
+	if ((bt_rssi_state == BTC_RSSI_STATE_HIGH) ||
+	    (bt_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
+		halbtc8821a2ant_coex_table_with_type(btcoexist, NORMAL_EXEC,
+						     12);
+
+		if (BTC_WIFI_BW_HT40 == wifi_bw)
+			halbtc8821a2ant_tdma_duration_adjust(btcoexist, false,
+							     true, 3);
+		else
+			halbtc8821a2ant_tdma_duration_adjust(btcoexist, false,
+							     false, 3);
+	} else {
+		halbtc8821a2ant_coex_table_with_type(btcoexist, NORMAL_EXEC,
+						     13);
+		halbtc8821a2ant_tdma_duration_adjust(btcoexist, false, true, 3);
+	}
+
+	/* sw mechanism	 */
+	if (BTC_WIFI_BW_HT40 == wifi_bw) {
+		if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) ||
+		    (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
+			halbtc8821a2ant_sw_mechanism1(btcoexist, true, false,
+						      false, false);
+			halbtc8821a2ant_sw_mechanism2(btcoexist, true, false,
+						      false, 0x18);
+		} else {
+			halbtc8821a2ant_sw_mechanism1(btcoexist, true, false,
+						      false, false);
+			halbtc8821a2ant_sw_mechanism2(btcoexist, false, false,
+						      false, 0x18);
+		}
+	} else {
+		if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) ||
+		    (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
+			halbtc8821a2ant_sw_mechanism1(btcoexist, false, false,
+						      false, false);
+			halbtc8821a2ant_sw_mechanism2(btcoexist, true, false,
+						      false, 0x18);
+		} else {
+			halbtc8821a2ant_sw_mechanism1(btcoexist, false, false,
+						      false, false);
+			halbtc8821a2ant_sw_mechanism2(btcoexist, false, false,
+						      false, 0x18);
+		}
+	}
+}
+
+void halbtc8821a2ant_action_pan_edr_hid(IN struct btc_coexist *btcoexist)
+{
+	u8		wifi_rssi_state, wifi_rssi_state1, bt_rssi_state;
+	u32		wifi_bw;
+
+	btcoexist->btc_phydm_modify_RA_PCR_threshold(btcoexist, 0, 25);
+
+	wifi_rssi_state = halbtc8821a2ant_wifi_rssi_state(btcoexist, 0, 2, 15,
+			  0);
+	wifi_rssi_state1 = halbtc8821a2ant_wifi_rssi_state(btcoexist, 1, 2,
+			   BT_8821A_2ANT_WIFI_RSSI_COEXSWITCH_THRES, 0);
+	bt_rssi_state = halbtc8821a2ant_bt_rssi_state(2,
+			BT_8821A_2ANT_BT_RSSI_COEXSWITCH_THRES, 0);
+	btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw);
+
+	halbtc8821a2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, 0x8);
+
+	if (BTC_RSSI_HIGH(bt_rssi_state))
+		halbtc8821a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2);
+	else
+		halbtc8821a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);
+
+	if (BTC_RSSI_HIGH(wifi_rssi_state1) && BTC_RSSI_HIGH(bt_rssi_state)) {
+		halbtc8821a2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 7);
+	} else {
+		halbtc8821a2ant_coex_table_with_type(btcoexist, NORMAL_EXEC,
+						     14);
+	}
+
+	if ((bt_rssi_state == BTC_RSSI_STATE_HIGH) ||
+	    (bt_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
+		if (BTC_WIFI_BW_HT40 == wifi_bw) {
+			halbtc8821a2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC,
+							 3);
+			/* halbtc8821a2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 11); */
+			btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1,
+						  0xfffff, 0x780);
+		} else {
+			halbtc8821a2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC,
+							 6);
+			/* halbtc8821a2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 7); */
+			btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1,
+						  0xfffff, 0x0);
+		}
+		halbtc8821a2ant_tdma_duration_adjust(btcoexist, true, false, 2);
+	} else {
+		halbtc8821a2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6);
+		/* halbtc8821a2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 14); */
+		btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1, 0xfffff,
+					  0x0);
+		halbtc8821a2ant_tdma_duration_adjust(btcoexist, true, true, 2);
+	}
+
+	/* sw mechanism */
+	if (BTC_WIFI_BW_HT40 == wifi_bw) {
+		if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) ||
+		    (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
+			halbtc8821a2ant_sw_mechanism1(btcoexist, true, true,
+						      false, false);
+			halbtc8821a2ant_sw_mechanism2(btcoexist, true, false,
+						      false, 0x18);
+		} else {
+			halbtc8821a2ant_sw_mechanism1(btcoexist, true, true,
+						      false, false);
+			halbtc8821a2ant_sw_mechanism2(btcoexist, false, false,
+						      false, 0x18);
+		}
+	} else {
+		if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) ||
+		    (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
+			halbtc8821a2ant_sw_mechanism1(btcoexist, false, true,
+						      false, false);
+			halbtc8821a2ant_sw_mechanism2(btcoexist, true, false,
+						      false, 0x18);
+		} else {
+			halbtc8821a2ant_sw_mechanism1(btcoexist, false, true,
+						      false, false);
+			halbtc8821a2ant_sw_mechanism2(btcoexist, false, false,
+						      false, 0x18);
+		}
+	}
+}
+
+/* HID+A2DP+PAN(EDR) */
+void halbtc8821a2ant_action_hid_a2dp_pan_edr(IN struct btc_coexist *btcoexist)
+{
+	u8		wifi_rssi_state, wifi_rssi_state1,  bt_rssi_state;
+	u32		wifi_bw;
+
+	btcoexist->btc_phydm_modify_RA_PCR_threshold(btcoexist, 0, 25);
+
+	wifi_rssi_state = halbtc8821a2ant_wifi_rssi_state(btcoexist, 0, 2, 15,
+			  0);
+	wifi_rssi_state1 = halbtc8821a2ant_wifi_rssi_state(btcoexist, 1, 2,
+			   BT_8821A_2ANT_WIFI_RSSI_COEXSWITCH_THRES, 0);
+	bt_rssi_state = halbtc8821a2ant_bt_rssi_state(2,
+			BT_8821A_2ANT_BT_RSSI_COEXSWITCH_THRES, 0);
+
+	btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1, 0xfffff, 0x0);
+
+	halbtc8821a2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, 0x8);
+
+	halbtc8821a2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6);
+
+	if (BTC_RSSI_HIGH(bt_rssi_state))
+		halbtc8821a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2);
+	else
+		halbtc8821a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);
+
+	if (BTC_RSSI_HIGH(wifi_rssi_state1) && BTC_RSSI_HIGH(bt_rssi_state)) {
+		halbtc8821a2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 7);
+	} else {
+		halbtc8821a2ant_coex_table_with_type(btcoexist, NORMAL_EXEC,
+						     14);
+	}
+
+	btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw);
+
+	if ((bt_rssi_state == BTC_RSSI_STATE_HIGH) ||
+	    (bt_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
+		if (BTC_WIFI_BW_HT40 == wifi_bw)
+			halbtc8821a2ant_tdma_duration_adjust(btcoexist, true,
+							     true, 3);
+		else
+			halbtc8821a2ant_tdma_duration_adjust(btcoexist, true,
+							     false, 3);
+	} else
+		halbtc8821a2ant_tdma_duration_adjust(btcoexist, true, true, 3);
+
+	/* sw mechanism */
+	if (BTC_WIFI_BW_HT40 == wifi_bw) {
+		if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) ||
+		    (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
+			halbtc8821a2ant_sw_mechanism1(btcoexist, true, true,
+						      false, false);
+			halbtc8821a2ant_sw_mechanism2(btcoexist, true, false,
+						      false, 0x18);
+		} else {
+			halbtc8821a2ant_sw_mechanism1(btcoexist, true, true,
+						      false, false);
+			halbtc8821a2ant_sw_mechanism2(btcoexist, false, false,
+						      false, 0x18);
+		}
+	} else {
+		if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) ||
+		    (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
+			halbtc8821a2ant_sw_mechanism1(btcoexist, false, true,
+						      false, false);
+			halbtc8821a2ant_sw_mechanism2(btcoexist, true, false,
+						      false, 0x18);
+		} else {
+			halbtc8821a2ant_sw_mechanism1(btcoexist, false, true,
+						      false, false);
+			halbtc8821a2ant_sw_mechanism2(btcoexist, false, false,
+						      false, 0x18);
+		}
+	}
+}
+
+void halbtc8821a2ant_action_hid_a2dp(IN struct btc_coexist *btcoexist)
+{
+	u8		wifi_rssi_state, wifi_rssi_state1, bt_rssi_state;
+	u32		wifi_bw;
+	u8		ap_num = 0;
+
+	btcoexist->btc_phydm_modify_RA_PCR_threshold(btcoexist, 0, 25);
+
+	wifi_rssi_state = halbtc8821a2ant_wifi_rssi_state(btcoexist, 0, 2, 15,
+			  0);
+	/* bt_rssi_state = halbtc8821a2ant_bt_rssi_state(2, 29, 0); */
+	wifi_rssi_state1 = halbtc8821a2ant_wifi_rssi_state(btcoexist, 1, 2,
+			   BT_8821A_2ANT_WIFI_RSSI_COEXSWITCH_THRES, 0);
+	bt_rssi_state = halbtc8821a2ant_bt_rssi_state(3,
+			BT_8821A_2ANT_BT_RSSI_COEXSWITCH_THRES, 37);
+
+	btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1, 0xfffff, 0x0);
+
+	halbtc8821a2ant_limited_rx(btcoexist, NORMAL_EXEC, false, true, 0x6);
+
+	halbtc8821a2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6);
+
+	btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw);
+	if (BTC_WIFI_BW_LEGACY == wifi_bw) {
+		if (BTC_RSSI_HIGH(bt_rssi_state))
+			halbtc8821a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2);
+		else if (BTC_RSSI_MEDIUM(bt_rssi_state))
+			halbtc8821a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2);
+		else
+			halbtc8821a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);
+	} else {
+		/* only 802.11N mode we have to dec bt power to 4 degree */
+		if (BTC_RSSI_HIGH(bt_rssi_state)) {
+			btcoexist->btc_get(btcoexist, BTC_GET_U1_AP_NUM,
+					   &ap_num);
+			/* need to check ap Number of Not */
+			if (ap_num < 10)
+				halbtc8821a2ant_dec_bt_pwr(btcoexist,
+							   NORMAL_EXEC, 4);
+			else
+				halbtc8821a2ant_dec_bt_pwr(btcoexist,
+							   NORMAL_EXEC, 2);
+		} else if (BTC_RSSI_MEDIUM(bt_rssi_state))
+			halbtc8821a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2);
+		else
+			halbtc8821a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);
+	}
+
+	if (BTC_RSSI_HIGH(wifi_rssi_state1) && BTC_RSSI_HIGH(bt_rssi_state)) {
+		halbtc8821a2ant_coex_table_with_type(btcoexist, NORMAL_EXEC,
+						     18);
+	} else {
+		halbtc8821a2ant_coex_table_with_type(btcoexist, NORMAL_EXEC,
+						     18);
+	}
+
+	if ((bt_rssi_state == BTC_RSSI_STATE_HIGH) ||
+	    (bt_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
+		/* halbtc8821a2ant_tdma_duration_adjust(btcoexist, true, false, 3); */
+		halbtc8821a2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 28);
+	} else {
+		/* halbtc8821a2ant_tdma_duration_adjust(btcoexist, true, true, 3); */
+		halbtc8821a2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 28);
+	}
+
+	/* sw mechanism */
+	if (BTC_WIFI_BW_HT40 == wifi_bw) {
+		if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) ||
+		    (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
+			halbtc8821a2ant_sw_mechanism1(btcoexist, true, true,
+						      false, false);
+			halbtc8821a2ant_sw_mechanism2(btcoexist, true, false,
+						      false, 0x18);
+		} else {
+			halbtc8821a2ant_sw_mechanism1(btcoexist, true, true,
+						      false, false);
+			halbtc8821a2ant_sw_mechanism2(btcoexist, false, false,
+						      false, 0x18);
+		}
+	} else {
+		if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) ||
+		    (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
+			halbtc8821a2ant_sw_mechanism1(btcoexist, false, true,
+						      false, false);
+			halbtc8821a2ant_sw_mechanism2(btcoexist, true, false,
+						      false, 0x18);
+		} else {
+			halbtc8821a2ant_sw_mechanism1(btcoexist, false, true,
+						      false, false);
+			halbtc8821a2ant_sw_mechanism2(btcoexist, false, false,
+						      false, 0x18);
+		}
+	}
+}
+
+void halbtc8821a2ant_action_bt_whck_test(IN struct btc_coexist *btcoexist)
+{
+	halbtc8821a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);
+
+	/* sw all off */
+	halbtc8821a2ant_sw_mechanism1(btcoexist, false, false, false, false);
+	halbtc8821a2ant_sw_mechanism2(btcoexist, false, false, false, 0x18);
+
+	halbtc8821a2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 1);
+	halbtc8821a2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0);
+}
+
+void halbtc8821a2ant_action_wifi_multi_port(IN struct btc_coexist *btcoexist)
+{
+	halbtc8821a2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6);
+	halbtc8821a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);
+
+	/* sw all off */
+	halbtc8821a2ant_sw_mechanism1(btcoexist, false, false, false, false);
+	halbtc8821a2ant_sw_mechanism2(btcoexist, false, false, false, 0x18);
+
+	/* hw all off */
+	/* btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1, 0xfffff, 0x0); */
+	halbtc8821a2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0);
+
+	halbtc8821a2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 1);
+}
+
+void halbtc8821a2ant_run_coexist_mechanism(IN struct btc_coexist *btcoexist)
+{
+	boolean				wifi_under_5g = false;
+	u8				algorithm = 0;
+	u32				num_of_wifi_link = 0;
+	u32				wifi_link_status = 0;
+	struct  btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
+	boolean				miracast_plus_bt = false;
+	boolean				scan = false, link = false, roam = false;
+
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+		    "[BTCoex], RunCoexistMechanism()===>\n");
+	BTC_TRACE(trace_buf);
+
+	if (btcoexist->manual_control) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			"[BTCoex], RunCoexistMechanism(), return for Manual CTRL <===\n");
+		BTC_TRACE(trace_buf);
+		return;
+	}
+
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_5G, &wifi_under_5g);
+	if (wifi_under_5g) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			"[BTCoex], RunCoexistMechanism(), run 5G coex setting!!<===\n");
+		BTC_TRACE(trace_buf);
+		halbtc8821a2ant_coex_under_5g(btcoexist);
+		return;
+	}
+
+	if (coex_sta->under_ips) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], wifi is under IPS !!!\n");
+		BTC_TRACE(trace_buf);
+		return;
+	}
+
+	if (coex_sta->bt_whck_test) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], BT is under WHCK TEST!!!\n");
+		BTC_TRACE(trace_buf);
+		halbtc8821a2ant_action_bt_whck_test(btcoexist);
+		return;
+	}
+
+	algorithm = halbtc8821a2ant_action_algorithm(btcoexist);
+	if (coex_sta->c2h_bt_inquiry_page &&
+	    (BT_8821A_2ANT_COEX_ALGO_PANHS != algorithm)) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], BT is under inquiry/page scan !!\n");
+		BTC_TRACE(trace_buf);
+		halbtc8821a2ant_action_bt_inquiry(btcoexist);
+		return;
+	}
+
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_SCAN, &scan);
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_LINK, &link);
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_ROAM, &roam);
+
+	if (scan || link || roam) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], WiFi is under Link Process !!\n");
+		BTC_TRACE(trace_buf);
+		halbtc8821a2ant_action_wifi_link_process(btcoexist);
+		return;
+	}
+
+	/* for P2P */
+
+	btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_LINK_STATUS,
+			   &wifi_link_status);
+	num_of_wifi_link = wifi_link_status >> 16;
+
+	if ((num_of_wifi_link >= 2) ||
+	    (wifi_link_status & WIFI_P2P_GO_CONNECTED)) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			"############# [BTCoex],  Multi-Port num_of_wifi_link = %d, wifi_link_status = 0x%x\n",
+			    num_of_wifi_link, wifi_link_status);
+		BTC_TRACE(trace_buf);
+
+		if (bt_link_info->bt_link_exist)
+			miracast_plus_bt = true;
+		else
+			miracast_plus_bt = false;
+
+		btcoexist->btc_set(btcoexist, BTC_SET_BL_MIRACAST_PLUS_BT,
+				   &miracast_plus_bt);
+		halbtc8821a2ant_action_wifi_multi_port(btcoexist);
+
+		return;
+	}
+	miracast_plus_bt = false;
+	btcoexist->btc_set(btcoexist, BTC_SET_BL_MIRACAST_PLUS_BT,
+			   &miracast_plus_bt);
+
+	coex_dm->cur_algorithm = algorithm;
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], Algorithm = %d\n",
+		    coex_dm->cur_algorithm);
+	BTC_TRACE(trace_buf);
+
+	if (halbtc8821a2ant_is_common_action(btcoexist)) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], Action 2-Ant common.\n");
+		BTC_TRACE(trace_buf);
+		coex_dm->auto_tdma_adjust = false;
+	} else {
+		if (coex_dm->cur_algorithm != coex_dm->pre_algorithm) {
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				"[BTCoex], pre_algorithm=%d, cur_algorithm=%d\n",
+				coex_dm->pre_algorithm, coex_dm->cur_algorithm);
+			BTC_TRACE(trace_buf);
+			coex_dm->auto_tdma_adjust = false;
+		}
+		switch (coex_dm->cur_algorithm) {
+		case BT_8821A_2ANT_COEX_ALGO_SCO:
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				"[BTCoex], Action 2-Ant, algorithm = SCO.\n");
+			BTC_TRACE(trace_buf);
+			halbtc8821a2ant_action_sco(btcoexist);
+			break;
+		case BT_8821A_2ANT_COEX_ALGO_HID:
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				"[BTCoex], Action 2-Ant, algorithm = HID.\n");
+			BTC_TRACE(trace_buf);
+			halbtc8821a2ant_action_hid(btcoexist);
+			break;
+		case BT_8821A_2ANT_COEX_ALGO_A2DP:
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				"[BTCoex], Action 2-Ant, algorithm = A2DP.\n");
+			BTC_TRACE(trace_buf);
+			halbtc8821a2ant_action_a2dp(btcoexist);
+			break;
+		case BT_8821A_2ANT_COEX_ALGO_A2DP_PANHS:
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				"[BTCoex], Action 2-Ant, algorithm = A2DP+PAN(HS).\n");
+			BTC_TRACE(trace_buf);
+			halbtc8821a2ant_action_a2dp_pan_hs(btcoexist);
+			break;
+		case BT_8821A_2ANT_COEX_ALGO_PANEDR:
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				"[BTCoex], Action 2-Ant, algorithm = PAN(EDR).\n");
+			BTC_TRACE(trace_buf);
+			halbtc8821a2ant_action_pan_edr(btcoexist);
+			break;
+		case BT_8821A_2ANT_COEX_ALGO_PANHS:
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				"[BTCoex], Action 2-Ant, algorithm = HS mode.\n");
+			BTC_TRACE(trace_buf);
+			halbtc8821a2ant_action_pan_hs(btcoexist);
+			break;
+		case BT_8821A_2ANT_COEX_ALGO_PANEDR_A2DP:
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				"[BTCoex], Action 2-Ant, algorithm = PAN+A2DP.\n");
+			BTC_TRACE(trace_buf);
+			halbtc8821a2ant_action_pan_edr_a2dp(btcoexist);
+			break;
+		case BT_8821A_2ANT_COEX_ALGO_PANEDR_HID:
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				"[BTCoex], Action 2-Ant, algorithm = PAN(EDR)+HID.\n");
+			BTC_TRACE(trace_buf);
+			halbtc8821a2ant_action_pan_edr_hid(btcoexist);
+			break;
+		case BT_8821A_2ANT_COEX_ALGO_HID_A2DP_PANEDR:
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				"[BTCoex], Action 2-Ant, algorithm = HID+A2DP+PAN.\n");
+			BTC_TRACE(trace_buf);
+			halbtc8821a2ant_action_hid_a2dp_pan_edr(
+				btcoexist);
+			break;
+		case BT_8821A_2ANT_COEX_ALGO_HID_A2DP:
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				"[BTCoex], Action 2-Ant, algorithm = HID+A2DP.\n");
+			BTC_TRACE(trace_buf);
+			halbtc8821a2ant_action_hid_a2dp(btcoexist);
+			break;
+		default:
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				"[BTCoex], Action 2-Ant, algorithm = coexist All Off!!\n");
+			BTC_TRACE(trace_buf);
+			halbtc8821a2ant_coex_all_off(btcoexist);
+			break;
+		}
+		coex_dm->pre_algorithm = coex_dm->cur_algorithm;
+	}
+}
+
+void halbtc8821a2ant_wifi_off_hw_cfg(IN struct btc_coexist *btcoexist)
+{
+	u8 h2c_parameter[2] = {0};
+	u32 fw_ver = 0;
+
+	/* set wlan_act to low */
+	btcoexist->btc_write_1byte(btcoexist, 0x76e, 0x4);
+
+	btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1, 0xfffff,
+			  0x780); /* WiFi goto standby while GNT_BT 0-->1 */
+	btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_FW_VER, &fw_ver);
+	if (fw_ver >= 0x180000) {
+		/* Use H2C to set GNT_BT to HIGH */
+		h2c_parameter[0] = 1;
+		btcoexist->btc_fill_h2c(btcoexist, 0x6E, 1, h2c_parameter);
+	} else
+		btcoexist->btc_write_1byte(btcoexist, 0x765, 0x18);
+}
+
+void halbtc8821a2ant_init_coex_dm(IN struct btc_coexist *btcoexist)
+{
+	/* force to reset coex mechanism */
+	halbtc8821a2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0);
+
+	halbtc8821a2ant_ps_tdma(btcoexist, FORCE_EXEC, false, 1);
+	halbtc8821a2ant_fw_dac_swing_lvl(btcoexist, FORCE_EXEC, 6);
+	halbtc8821a2ant_dec_bt_pwr(btcoexist, FORCE_EXEC, 0);
+
+	halbtc8821a2ant_sw_mechanism1(btcoexist, false, false, false, false);
+	halbtc8821a2ant_sw_mechanism2(btcoexist, false, false, false, 0x18);
+}
+
+void halbtc8821a2ant_init_hw_config(IN struct btc_coexist *btcoexist,
+				    IN boolean back_up)
+{
+	u8	u8tmp = 0;
+
+
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+		    "[BTCoex], 2Ant Init HW Config!!\n");
+	BTC_TRACE(trace_buf);
+
+	/* Give bt_coex_supported_version the default value */
+	coex_sta->bt_coex_supported_version = 0;
+
+	/* 0xf0[15:12] --> Chip Cut information */
+	coex_sta->cut_version = (btcoexist->btc_read_1byte(btcoexist,
+				 0xf1) & 0xf0) >> 4;
+
+	/* backup rf 0x1e value */
+	coex_dm->bt_rf_0x1e_backup =
+		btcoexist->btc_get_rf_reg(btcoexist, BTC_RF_A, 0x1e, 0xfffff);
+
+	/* 0x790[5:0]=0x5 */
+	u8tmp = btcoexist->btc_read_1byte(btcoexist, 0x790);
+	u8tmp &= 0xc0;
+	u8tmp |= 0x5;
+	btcoexist->btc_write_1byte(btcoexist, 0x790, u8tmp);
+
+	/* Antenna config	 */
+	halbtc8821a2ant_set_ant_path(btcoexist, BTC_ANT_WIFI_AT_MAIN, true,
+				     false);
+	coex_sta->dis_ver_info_cnt = 0;
+
+	/* PTA parameter */
+	halbtc8821a2ant_coex_table_with_type(btcoexist, FORCE_EXEC, 0);
+
+	/* Enable counter statistics */
+	btcoexist->btc_write_1byte(btcoexist, 0x76e,
+			   0x4); /* 0x76e[3] =1, WLAN_Act control by PTA */
+	btcoexist->btc_write_1byte(btcoexist, 0x778, 0x3);
+	btcoexist->btc_write_1byte_bitmask(btcoexist, 0x40, 0x20, 0x1);
+}
+
+/* ************************************************************
+ * work around function start with wa_halbtc8821a2ant_
+ * ************************************************************
+ * ************************************************************
+ * extern function start with ex_halbtc8821a2ant_
+ * ************************************************************ */
+void ex_halbtc8821a2ant_power_on_setting(IN struct btc_coexist *btcoexist)
+{
+
+}
+
+void ex_halbtc8821a2ant_pre_load_firmware(IN struct btc_coexist *btcoexist)
+{
+	struct  btc_board_info	*board_info = &btcoexist->board_info;
+	u8 u8tmp = 0x4; /* Set BIT2 by default since it's 2ant case */
+
+	/* */
+	/* S0 or S1 setting and Local register setting(By the setting fw can get ant number, S0/S1, ... info) */
+	/* Local setting bit define */
+	/*	BIT0: "0" for no antenna inverse; "1" for antenna inverse  */
+	/*	BIT1: "0" for internal switch; "1" for external switch */
+	/*	BIT2: "0" for one antenna; "1" for two antenna */
+	/* NOTE: here default all internal switch and 1-antenna ==> BIT1=0 and BIT2=0 */
+	if (btcoexist->chip_interface == BTC_INTF_USB) {
+		/* fixed at S0 for USB interface */
+		u8tmp |= 0x1;	/* antenna inverse */
+		btcoexist->btc_write_local_reg_1byte(btcoexist, 0xfe08, u8tmp);
+	} else {
+		/* for PCIE and SDIO interface, we check efuse 0xc3[6] */
+		if (board_info->single_ant_path == 0) {
+		} else if (board_info->single_ant_path == 1) {
+			/* set to S0 */
+			u8tmp |= 0x1;	/* antenna inverse */
+		}
+
+		if (btcoexist->chip_interface == BTC_INTF_PCI)
+			btcoexist->btc_write_local_reg_1byte(btcoexist, 0x384,
+							     u8tmp);
+		else if (btcoexist->chip_interface == BTC_INTF_SDIO)
+			btcoexist->btc_write_local_reg_1byte(btcoexist, 0x60,
+							     u8tmp);
+	}
+}
+
+void ex_halbtc8821a2ant_init_hw_config(IN struct btc_coexist *btcoexist,
+				       IN boolean wifi_only)
+{
+	halbtc8821a2ant_init_hw_config(btcoexist, true);
+}
+
+void ex_halbtc8821a2ant_init_coex_dm(IN struct btc_coexist *btcoexist)
+{
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+		    "[BTCoex], Coex Mechanism Init!!\n");
+	BTC_TRACE(trace_buf);
+
+	halbtc8821a2ant_init_coex_dm(btcoexist);
+}
+
+void ex_halbtc8821a2ant_display_coex_info(IN struct btc_coexist *btcoexist)
+{
+	struct  btc_board_info		*board_info = &btcoexist->board_info;
+	struct  btc_bt_link_info	*bt_link_info = &btcoexist->bt_link_info;
+	u8				*cli_buf = btcoexist->cli_buf;
+	u8				u8tmp[4], i, bt_info_ext, ps_tdma_case = 0;
+	u32				u32tmp[4];
+	u32				fw_ver = 0, bt_patch_ver = 0;
+	u32				bt_coex_ver = 0;
+	u32				phyver = 0;
+	u32				fa_ofdm, fa_cck, cca_ofdm, cca_cck;
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+		   "\r\n ============[BT Coexist info]============");
+	CL_PRINTF(cli_buf);
+
+	if (btcoexist->manual_control) {
+		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+			"\r\n ============[Under Manual Control]============");
+		CL_PRINTF(cli_buf);
+		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+			   "\r\n ==========================================");
+		CL_PRINTF(cli_buf);
+	}
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d ",
+		   "Ant PG number/ Ant mechanism:",
+		   board_info->pg_ant_num, board_info->btdm_ant_num);
+	CL_PRINTF(cli_buf);
+
+	/* btcoexist->btc_get(btcoexist, BTC_GET_U4_BT_PATCH_VER, &bt_patch_ver); */
+	bt_patch_ver = btcoexist->bt_info.bt_get_fw_ver;
+	btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_FW_VER, &fw_ver);
+	phyver = btcoexist->btc_get_bt_phydm_version(btcoexist);
+	bt_coex_ver = coex_sta->bt_coex_supported_version & 0xff;
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+		   "\r\n %-35s = %d_%02x/ 0x%02x/ 0x%02x (%s)",
+		   "CoexVer WL/  BT_Desired/ BT_Report",
+		   glcoex_ver_date_8821a_2ant, glcoex_ver_8821a_2ant,
+		   glcoex_ver_btdesired_8821a_2ant,
+		   bt_coex_ver,
+		   (bt_coex_ver == 0xff ? "Unknown" :
+		    (bt_coex_ver >= glcoex_ver_btdesired_8821a_2ant ?
+		     "Match" : "Mis-Match")));
+	CL_PRINTF(cli_buf);
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+		   "\r\n %-35s = 0x%x/ 0x%x/ v%d/ %c",
+		   "W_FW/ B_FW/ Phy/ Kt",
+		   fw_ver, bt_patch_ver, phyver,
+		   coex_sta->cut_version + 65);
+	CL_PRINTF(cli_buf);
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %02x %02x %02x ",
+		   "Wifi channel informed to BT",
+		   coex_dm->wifi_chnl_info[0], coex_dm->wifi_chnl_info[1],
+		   coex_dm->wifi_chnl_info[2]);
+	CL_PRINTF(cli_buf);
+
+	/* wifi status */
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s",
+		   "============[Wifi Status]============");
+	CL_PRINTF(cli_buf);
+	btcoexist->btc_disp_dbg_msg(btcoexist, BTC_DBG_DISP_WIFI_STATUS);
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s",
+		   "============[BT Status]============");
+	CL_PRINTF(cli_buf);
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = [%s/ %ddBm/ %d] ",
+		   "BT [status/ rssi/ retryCnt]",
+		   ((coex_sta->bt_disabled) ? ("disabled") :	((
+		   coex_sta->c2h_bt_inquiry_page) ? ("inquiry/page scan")
+			   : ((BT_8821A_2ANT_BT_STATUS_NON_CONNECTED_IDLE ==
+			       coex_dm->bt_status) ? "non-connected idle" :
+		((BT_8821A_2ANT_BT_STATUS_CONNECTED_IDLE == coex_dm->bt_status)
+				       ? "connected-idle" : "busy")))),
+		   coex_sta->bt_rssi - 100, coex_sta->bt_retry_cnt);
+	CL_PRINTF(cli_buf);
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d / %d / %d / %d",
+		   "SCO/HID/PAN/A2DP",
+		   bt_link_info->sco_exist, bt_link_info->hid_exist,
+		   bt_link_info->pan_exist, bt_link_info->a2dp_exist);
+	CL_PRINTF(cli_buf);
+
+	{
+		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s",
+			   "BT Role",
+			   (bt_link_info->slave_role) ? "Slave" : "Master");
+		CL_PRINTF(cli_buf);
+	}
+
+	bt_info_ext = coex_sta->bt_info_ext;
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s",
+		   "BT Info A2DP rate",
+		   (bt_info_ext & BIT(0)) ? "Basic rate" : "EDR rate");
+	CL_PRINTF(cli_buf);
+
+	for (i = 0; i < BT_INFO_SRC_8821A_2ANT_MAX; i++) {
+		if (coex_sta->bt_info_c2h_cnt[i]) {
+			CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+				"\r\n %-35s = %02x %02x %02x %02x %02x %02x %02x(%d)",
+				   glbt_info_src_8821a_2ant[i],
+				   coex_sta->bt_info_c2h[i][0],
+				   coex_sta->bt_info_c2h[i][1],
+				   coex_sta->bt_info_c2h[i][2],
+				   coex_sta->bt_info_c2h[i][3],
+				   coex_sta->bt_info_c2h[i][4],
+				   coex_sta->bt_info_c2h[i][5],
+				   coex_sta->bt_info_c2h[i][6],
+				   coex_sta->bt_info_c2h_cnt[i]);
+			CL_PRINTF(cli_buf);
+		}
+	}
+
+	/* Sw mechanism	 */
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s",
+		   "============[Sw mechanism]============");
+	CL_PRINTF(cli_buf);
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d ",
+		   "SM1[ShRf/ LpRA/ LimDig]",
+		   coex_dm->cur_rf_rx_lpf_shrink, coex_dm->cur_low_penalty_ra,
+		   coex_dm->limited_dig);
+	CL_PRINTF(cli_buf);
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d(0x%x) ",
+		   "SM2[AgcT/ AdcB/ SwDacSwing(lvl)]",
+		   coex_dm->cur_agc_table_en, coex_dm->cur_adc_back_off,
+		   coex_dm->cur_dac_swing_on, coex_dm->cur_dac_swing_lvl);
+	CL_PRINTF(cli_buf);
+
+	/* Fw mechanism		 */
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s",
+		   "============[Fw mechanism]============");
+	CL_PRINTF(cli_buf);
+
+	ps_tdma_case = coex_dm->cur_ps_tdma;
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+		   "\r\n %-35s = %02x %02x %02x %02x %02x case-%d (auto:%d)",
+		   "PS TDMA",
+		   coex_dm->ps_tdma_para[0], coex_dm->ps_tdma_para[1],
+		   coex_dm->ps_tdma_para[2], coex_dm->ps_tdma_para[3],
+		   coex_dm->ps_tdma_para[4], ps_tdma_case,
+		   coex_dm->auto_tdma_adjust);
+	CL_PRINTF(cli_buf);
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d",
+		   "Coex Table Type",
+		   coex_sta->coex_table_type);
+	CL_PRINTF(cli_buf);
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d ",
+		   "DecBtPwr/ IgnWlanAct",
+		   coex_dm->cur_bt_dec_pwr_lvl, coex_dm->cur_ignore_wlan_act);
+	CL_PRINTF(cli_buf);
+
+	/* Hw setting		 */
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s",
+		   "============[Hw setting]============");
+	CL_PRINTF(cli_buf);
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x",
+		   "RF-A, 0x1e initVal",
+		   coex_dm->bt_rf_0x1e_backup);
+	CL_PRINTF(cli_buf);
+
+	u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x778);
+	u8tmp[1] = btcoexist->btc_read_1byte(btcoexist, 0xc5b);
+	u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x880);
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x/ 0x%x",
+		   "0x778/0x880[29:25]/0xc58[29:25]",
+		   u8tmp[0], (u32tmp[0] & 0x3e000000) >> 25,
+		   ((u8tmp[1] & 0x3e) >> 1));
+	CL_PRINTF(cli_buf);
+
+	u32tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x764);
+	u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x76e);
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x/ 0x%x",
+		   "0x764/ 0x765/ 0x76e",
+		   (u32tmp[0] & 0xff), (u32tmp[0] & 0xff00) >> 8, u8tmp[0]);
+	CL_PRINTF(cli_buf);
+
+	u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0xcb4);
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x",
+		   "0xcb4[7:0](ctrl)/ 0xcb4[29:28](val)",
+		   u32tmp[0] & 0xff, ((u32tmp[0] & 0x30000000) >> 28));
+	CL_PRINTF(cli_buf);
+
+	u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x40);
+	u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x4c);
+	u32tmp[1] = btcoexist->btc_read_4byte(btcoexist, 0x974);
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x/ 0x%x",
+		   "0x40/ 0x4c[24:23]/ 0x974",
+		   u8tmp[0], ((u32tmp[0] & 0x01800000) >> 23), u32tmp[1]);
+	CL_PRINTF(cli_buf);
+
+	u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x550);
+	u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x522);
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x",
+		   "0x550(bcn ctrl)/0x522",
+		   u32tmp[0], u8tmp[0]);
+	CL_PRINTF(cli_buf);
+
+	u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0xc50);
+	u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x49c);
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x",
+		   "0xc50(dig)/0x49c(null-drop)",
+		   u32tmp[0] & 0xff, u8tmp[0]);
+	CL_PRINTF(cli_buf);
+
+	fa_ofdm = btcoexist->btc_phydm_query_PHY_counter(btcoexist,
+			PHYDM_INFO_FA_OFDM);
+	fa_cck = btcoexist->btc_phydm_query_PHY_counter(btcoexist,
+			PHYDM_INFO_FA_CCK);
+	cca_ofdm = btcoexist->btc_phydm_query_PHY_counter(btcoexist,
+			PHYDM_INFO_CCA_OFDM);
+	cca_cck = btcoexist->btc_phydm_query_PHY_counter(btcoexist,
+			PHYDM_INFO_CCA_CCK);
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+		   "\r\n %-35s = 0x%x/ 0x%x/ 0x%x/ 0x%x",
+		   "CCK-CCA/CCK-FA/OFDM-CCA/OFDM-FA",
+		   cca_cck, fa_cck, cca_ofdm, fa_ofdm);
+	CL_PRINTF(cli_buf);
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d/ %d",
+		   "CRC_OK CCK/11g/11n/11n-agg",
+		   coex_sta->crc_ok_cck, coex_sta->crc_ok_11g,
+		   coex_sta->crc_ok_11n, coex_sta->crc_ok_11n_vht);
+	CL_PRINTF(cli_buf);
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d/ %d",
+		   "CRC_Err CCK/11g/11n/11n-agg",
+		   coex_sta->crc_err_cck, coex_sta->crc_err_11g,
+		   coex_sta->crc_err_11n, coex_sta->crc_err_11n_vht);
+	CL_PRINTF(cli_buf);
+
+	u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x6c0);
+	u32tmp[1] = btcoexist->btc_read_4byte(btcoexist, 0x6c4);
+	u32tmp[2] = btcoexist->btc_read_4byte(btcoexist, 0x6c8);
+	u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x6cc);
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+		   "\r\n %-35s = 0x%x/ 0x%x/ 0x%x/ 0x%x",
+		   "0x6c0/0x6c4/0x6c8/0x6cc(coexTable)",
+		   u32tmp[0], u32tmp[1], u32tmp[2], u8tmp[0]);
+	CL_PRINTF(cli_buf);
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d",
+		   "0x770(high-pri rx/tx)",
+		   coex_sta->high_priority_rx, coex_sta->high_priority_tx);
+	CL_PRINTF(cli_buf);
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d",
+		   "0x774(low-pri rx/tx)",
+		   coex_sta->low_priority_rx, coex_sta->low_priority_tx);
+	CL_PRINTF(cli_buf);
+#if (BT_AUTO_REPORT_ONLY_8821A_2ANT == 1)
+	/* halbtc8821a2ant_monitor_bt_ctr(btcoexist); */
+#endif
+	btcoexist->btc_disp_dbg_msg(btcoexist, BTC_DBG_DISP_COEX_STATISTICS);
+}
+
+
+void ex_halbtc8821a2ant_ips_notify(IN struct btc_coexist *btcoexist, IN u8 type)
+{
+	if (BTC_IPS_ENTER == type) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], IPS ENTER notify\n");
+		BTC_TRACE(trace_buf);
+		coex_sta->under_ips = true;
+		halbtc8821a2ant_wifi_off_hw_cfg(btcoexist);
+		halbtc8821a2ant_ignore_wlan_act(btcoexist, FORCE_EXEC, true);
+		halbtc8821a2ant_coex_all_off(btcoexist);
+	} else if (BTC_IPS_LEAVE == type) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], IPS LEAVE notify\n");
+		BTC_TRACE(trace_buf);
+		coex_sta->under_ips = false;
+		halbtc8821a2ant_init_hw_config(btcoexist, false);
+		halbtc8821a2ant_init_coex_dm(btcoexist);
+		halbtc8821a2ant_query_bt_info(btcoexist);
+	}
+}
+
+void ex_halbtc8821a2ant_lps_notify(IN struct btc_coexist *btcoexist, IN u8 type)
+{
+	if (BTC_LPS_ENABLE == type) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], LPS ENABLE notify\n");
+		BTC_TRACE(trace_buf);
+		coex_sta->under_lps = true;
+	} else if (BTC_LPS_DISABLE == type) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], LPS DISABLE notify\n");
+		BTC_TRACE(trace_buf);
+		coex_sta->under_lps = false;
+	}
+}
+
+void ex_halbtc8821a2ant_scan_notify(IN struct btc_coexist *btcoexist,
+				    IN u8 type)
+{
+	u8	u8tmpa, u8tmpb;
+
+	u8tmpa = btcoexist->btc_read_1byte(btcoexist, 0x765);
+	u8tmpb = btcoexist->btc_read_1byte(btcoexist, 0x76e);
+
+	if (BTC_SCAN_START == type) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], SCAN START notify\n");
+		BTC_TRACE(trace_buf);
+	} else if (BTC_SCAN_FINISH == type) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], SCAN FINISH notify\n");
+		BTC_TRACE(trace_buf);
+	}
+
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+		    "############# [BTCoex], 0x765=0x%x, 0x76e=0x%x\n", u8tmpa,
+		    u8tmpb);
+	BTC_TRACE(trace_buf);
+}
+
+/* copy scan notify content to switch band notify */
+void ex_halbtc8821a2ant_switchband_notify(IN struct btc_coexist *btcoexist,
+		IN u8 type)
+{
+	u8	u8tmpa, u8tmpb;
+
+	u8tmpa = btcoexist->btc_read_1byte(btcoexist, 0x765);
+	u8tmpb = btcoexist->btc_read_1byte(btcoexist, 0x76e);
+
+	if (BTC_SCAN_START == type) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], SCAN START notify\n");
+		BTC_TRACE(trace_buf);
+	} else if (BTC_SCAN_FINISH == type) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], SCAN FINISH notify\n");
+		BTC_TRACE(trace_buf);
+	}
+
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+		    "############# [BTCoex], 0x765=0x%x, 0x76e=0x%x\n", u8tmpa,
+		    u8tmpb);
+	BTC_TRACE(trace_buf);
+}
+
+void ex_halbtc8821a2ant_connect_notify(IN struct btc_coexist *btcoexist,
+				       IN u8 type)
+{
+	if (BTC_ASSOCIATE_START == type) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], CONNECT START notify\n");
+		BTC_TRACE(trace_buf);
+	} else if (BTC_ASSOCIATE_FINISH == type) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], CONNECT FINISH notify\n");
+		BTC_TRACE(trace_buf);
+	}
+}
+
+void ex_halbtc8821a2ant_media_status_notify(IN struct btc_coexist *btcoexist,
+		IN u8 type)
+{
+	u8			h2c_parameter[3] = {0};
+	u32			wifi_bw;
+	u8			wifi_central_chnl;
+	u8			ap_num = 0;
+
+	if (BTC_MEDIA_CONNECT == type) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], MEDIA connect notify\n");
+		BTC_TRACE(trace_buf);
+	} else {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], MEDIA disconnect notify\n");
+		BTC_TRACE(trace_buf);
+	}
+
+	/* only 2.4G we need to inform bt the chnl mask */
+	btcoexist->btc_get(btcoexist, BTC_GET_U1_WIFI_CENTRAL_CHNL,
+			   &wifi_central_chnl);
+	if ((BTC_MEDIA_CONNECT == type) &&
+	    (wifi_central_chnl <= 14)) {
+		h2c_parameter[0] = 0x1;
+		h2c_parameter[1] = wifi_central_chnl;
+		btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw);
+		if (BTC_WIFI_BW_HT40 == wifi_bw)
+			h2c_parameter[2] = 0x30;
+		else {
+			btcoexist->btc_get(btcoexist, BTC_GET_U1_AP_NUM,
+					   &ap_num);
+			if (ap_num < 10)
+				h2c_parameter[2] = 0x30;
+			else
+				h2c_parameter[2] = 0x20;
+		}
+	}
+
+	coex_dm->wifi_chnl_info[0] = h2c_parameter[0];
+	coex_dm->wifi_chnl_info[1] = h2c_parameter[1];
+	coex_dm->wifi_chnl_info[2] = h2c_parameter[2];
+
+	btcoexist->btc_fill_h2c(btcoexist, 0x66, 3, h2c_parameter);
+}
+
+void ex_halbtc8821a2ant_specific_packet_notify(IN struct btc_coexist *btcoexist,
+		IN u8 type)
+{
+	if (type == BTC_PACKET_DHCP) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], DHCP Packet notify\n");
+		BTC_TRACE(trace_buf);
+	}
+}
+
+void ex_halbtc8821a2ant_bt_info_notify(IN struct btc_coexist *btcoexist,
+				       IN u8 *tmp_buf, IN u8 length)
+{
+	u8			bt_info = 0;
+	u8			i, rsp_source = 0;
+	boolean			bt_busy = false, limited_dig = false;
+	boolean			wifi_connected = false, wifi_under_5g = false;
+
+	coex_sta->c2h_bt_info_req_sent = false;
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_5G, &wifi_under_5g);
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED,
+			   &wifi_connected);
+
+	rsp_source = tmp_buf[0] & 0xf;
+	if (rsp_source >= BT_INFO_SRC_8821A_2ANT_MAX)
+		rsp_source = BT_INFO_SRC_8821A_2ANT_WIFI_FW;
+	coex_sta->bt_info_c2h_cnt[rsp_source]++;
+
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+		    "[BTCoex], Bt info[%d], length=%d, hex data=[", rsp_source,
+		    length);
+	BTC_TRACE(trace_buf);
+	for (i = 0; i < length; i++) {
+		coex_sta->bt_info_c2h[rsp_source][i] = tmp_buf[i];
+		if (i == 1)
+			bt_info = tmp_buf[i];
+		if (i == length - 1) {
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "0x%02x]\n",
+				    tmp_buf[i]);
+			BTC_TRACE(trace_buf);
+		} else {
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "0x%02x, ",
+				    tmp_buf[i]);
+			BTC_TRACE(trace_buf);
+		}
+	}
+
+	if (btcoexist->manual_control) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			"[BTCoex], BtInfoNotify(), return for Manual CTRL<===\n");
+		BTC_TRACE(trace_buf);
+		return;
+	}
+
+	/* if 0xff, it means BT is under WHCK test */
+	if (bt_info == 0xff)
+		coex_sta->bt_whck_test = true;
+	else
+		coex_sta->bt_whck_test = false;
+
+	if (BT_INFO_SRC_8821A_2ANT_WIFI_FW != rsp_source) {
+		coex_sta->bt_retry_cnt =	/* [3:0] */
+			coex_sta->bt_info_c2h[rsp_source][2] & 0xf;
+
+		coex_sta->bt_rssi =
+			coex_sta->bt_info_c2h[rsp_source][3] * 2 + 10;
+
+		coex_sta->bt_info_ext =
+			coex_sta->bt_info_c2h[rsp_source][4];
+
+		coex_sta->bt_tx_rx_mask = (coex_sta->bt_info_c2h[rsp_source][2]
+					   & 0x40);
+		btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_TX_RX_MASK,
+				   &coex_sta->bt_tx_rx_mask);
+		if (coex_sta->bt_tx_rx_mask) {
+			/* BT into is responded by BT FW and BT RF REG 0x3C != 0x01 => Need to switch BT TRx Mask */
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				"[BTCoex], Switch BT TRx Mask since BT RF REG 0x3C != 0x01\n");
+			BTC_TRACE(trace_buf);
+			btcoexist->btc_set_bt_reg(btcoexist, BTC_BT_REG_RF,
+						  0x3c, 0x01);
+		}
+
+		/* Here we need to resend some wifi info to BT */
+		/* because bt is reset and loss of the info. */
+		if ((coex_sta->bt_info_ext & BIT(1))) {
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				"[BTCoex], BT ext info bit1 check, send wifi BW&Chnl to BT!!\n");
+			BTC_TRACE(trace_buf);
+			if (wifi_connected)
+				ex_halbtc8821a2ant_media_status_notify(
+					btcoexist, BTC_MEDIA_CONNECT);
+			else
+				ex_halbtc8821a2ant_media_status_notify(
+					btcoexist, BTC_MEDIA_DISCONNECT);
+		}
+
+
+		if (!btcoexist->manual_control && !wifi_under_5g) {
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				    "[BTCoex], BT ext info = 0x%x!!\n",
+				    coex_sta->bt_info_ext);
+			BTC_TRACE(trace_buf);
+			if ((coex_sta->bt_info_ext & BIT(3))) {
+				BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+					"[BTCoex], BT ext info bit3=1, wifi_connected=%d\n",
+					    wifi_connected);
+				BTC_TRACE(trace_buf);
+				if (wifi_connected) {
+					BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+						"[BTCoex], BT ext info bit3 check, set BT NOT to ignore Wlan active!!\n");
+					BTC_TRACE(trace_buf);
+					halbtc8821a2ant_ignore_wlan_act(
+						btcoexist, FORCE_EXEC, false);
+				}
+			} else {
+				BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+					"[BTCoex], BT ext info bit3=0, wifi_connected=%d\n",
+					    wifi_connected);
+				BTC_TRACE(trace_buf);
+				/* BT already NOT ignore Wlan active, do nothing here. */
+				if (!wifi_connected) {
+					BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+						"[BTCoex], BT ext info bit3 check, set BT to ignore Wlan active!!\n");
+					BTC_TRACE(trace_buf);
+					halbtc8821a2ant_ignore_wlan_act(
+						btcoexist, FORCE_EXEC, true);
+				}
+			}
+		}
+
+#if (BT_AUTO_REPORT_ONLY_8821A_2ANT == 0)
+		if ((coex_sta->bt_info_ext & BIT(4))) {
+			/* BT auto report already enabled, do nothing */
+		} else
+			halbtc8821a2ant_bt_auto_report(btcoexist, FORCE_EXEC,
+						       true);
+#endif
+	}
+
+	/* check BIT2 first ==> check if bt is under inquiry or page scan */
+	if (bt_info & BT_INFO_8821A_2ANT_B_INQ_PAGE)
+		coex_sta->c2h_bt_inquiry_page = true;
+	else
+		coex_sta->c2h_bt_inquiry_page = false;
+
+	/* set link exist status */
+	if (!(bt_info & BT_INFO_8821A_2ANT_B_CONNECTION)) {
+		coex_sta->bt_link_exist = false;
+		coex_sta->pan_exist = false;
+		coex_sta->a2dp_exist = false;
+		coex_sta->hid_exist = false;
+		coex_sta->sco_exist = false;
+	} else {	/* connection exists */
+		coex_sta->bt_link_exist = true;
+		if (bt_info & BT_INFO_8821A_2ANT_B_FTP)
+			coex_sta->pan_exist = true;
+		else
+			coex_sta->pan_exist = false;
+		if (bt_info & BT_INFO_8821A_2ANT_B_A2DP)
+			coex_sta->a2dp_exist = true;
+		else
+			coex_sta->a2dp_exist = false;
+		if (bt_info & BT_INFO_8821A_2ANT_B_HID)
+			coex_sta->hid_exist = true;
+		else
+			coex_sta->hid_exist = false;
+		if (bt_info & BT_INFO_8821A_2ANT_B_SCO_ESCO)
+			coex_sta->sco_exist = true;
+		else
+			coex_sta->sco_exist = false;
+
+		if ((coex_sta->hid_exist == false) &&
+		    (coex_sta->c2h_bt_inquiry_page == false) &&
+		    (coex_sta->sco_exist == false)) {
+			if (coex_sta->high_priority_tx  +
+			    coex_sta->high_priority_rx >= 160)
+				coex_sta->hid_exist = true;
+		}
+	}
+
+	halbtc8821a2ant_update_bt_link_info(btcoexist);
+
+	if (!(bt_info & BT_INFO_8821A_2ANT_B_CONNECTION)) {
+		coex_dm->bt_status = BT_8821A_2ANT_BT_STATUS_NON_CONNECTED_IDLE;
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			"[BTCoex], BtInfoNotify(), BT Non-Connected idle!!!\n");
+		BTC_TRACE(trace_buf);
+	} else if (bt_info ==
+		BT_INFO_8821A_2ANT_B_CONNECTION) {	/* connection exists but no busy */
+		coex_dm->bt_status = BT_8821A_2ANT_BT_STATUS_CONNECTED_IDLE;
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], BtInfoNotify(), BT Connected-idle!!!\n");
+		BTC_TRACE(trace_buf);
+	} else if ((bt_info & BT_INFO_8821A_2ANT_B_SCO_ESCO) ||
+		   (bt_info & BT_INFO_8821A_2ANT_B_SCO_BUSY)) {
+		coex_dm->bt_status = BT_8821A_2ANT_BT_STATUS_SCO_BUSY;
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], BtInfoNotify(), BT SCO busy!!!\n");
+		BTC_TRACE(trace_buf);
+	} else if (bt_info & BT_INFO_8821A_2ANT_B_ACL_BUSY) {
+		coex_dm->bt_status = BT_8821A_2ANT_BT_STATUS_ACL_BUSY;
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], BtInfoNotify(), BT ACL busy!!!\n");
+		BTC_TRACE(trace_buf);
+	} else {
+		coex_dm->bt_status = BT_8821A_2ANT_BT_STATUS_MAX;
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			"[BTCoex], BtInfoNotify(), BT Non-Defined state!!!\n");
+		BTC_TRACE(trace_buf);
+	}
+
+	if ((BT_8821A_2ANT_BT_STATUS_ACL_BUSY == coex_dm->bt_status) ||
+	    (BT_8821A_2ANT_BT_STATUS_SCO_BUSY == coex_dm->bt_status) ||
+	    (BT_8821A_2ANT_BT_STATUS_ACL_SCO_BUSY == coex_dm->bt_status)) {
+		bt_busy = true;
+		limited_dig = true;
+	} else {
+		bt_busy = false;
+		limited_dig = false;
+	}
+
+	btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_TRAFFIC_BUSY, &bt_busy);
+
+	coex_dm->limited_dig = limited_dig;
+	btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_LIMITED_DIG, &limited_dig);
+
+	halbtc8821a2ant_run_coexist_mechanism(btcoexist);
+}
+
+void ex_halbtc8821a2ant_halt_notify(IN struct btc_coexist *btcoexist)
+{
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], Halt notify\n");
+	BTC_TRACE(trace_buf);
+
+	halbtc8821a2ant_wifi_off_hw_cfg(btcoexist);
+	/* remove due to interrupt is disabled that polling c2h will fail and delay 100ms. */
+	/* btcoexist->btc_set_bt_reg(btcoexist, BTC_BT_REG_RF, 0x3c, 0x15); */ /*BT goto standby while GNT_BT 1-->0 */
+	halbtc8821a2ant_ignore_wlan_act(btcoexist, FORCE_EXEC, true);
+
+	ex_halbtc8821a2ant_media_status_notify(btcoexist, BTC_MEDIA_DISCONNECT);
+}
+
+void ex_halbtc8821a2ant_pnp_notify(IN struct btc_coexist *btcoexist,
+				   IN u8 pnp_state)
+{
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], Pnp notify\n");
+	BTC_TRACE(trace_buf);
+
+	if (BTC_WIFI_PNP_SLEEP == pnp_state) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], Pnp notify to SLEEP\n");
+		BTC_TRACE(trace_buf);
+	} else if (BTC_WIFI_PNP_WAKE_UP == pnp_state) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], Pnp notify to WAKE UP\n");
+		BTC_TRACE(trace_buf);
+		halbtc8821a2ant_init_hw_config(btcoexist, false);
+		halbtc8821a2ant_init_coex_dm(btcoexist);
+		halbtc8821a2ant_query_bt_info(btcoexist);
+	}
+}
+
+void ex_halbtc8821a2ant_periodical(IN struct btc_coexist *btcoexist)
+{
+	u32 bt_patch_ver;
+
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+		"[BTCoex], ==========================Periodical===========================\n");
+	BTC_TRACE(trace_buf);
+
+	if (coex_sta->dis_ver_info_cnt <= 5) {
+		coex_sta->dis_ver_info_cnt += 1;
+		if (coex_sta->dis_ver_info_cnt == 3) {
+			/* Antenna config to set 0x765 = 0x0 (GNT_BT control by PTA) after initial */
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				    "[BTCoex], Set GNT_BT control by PTA\n");
+			BTC_TRACE(trace_buf);
+			halbtc8821a2ant_set_ant_path(btcoexist,
+				     BTC_ANT_WIFI_AT_MAIN, false, false);
+		}
+	}
+
+	if (((coex_sta->bt_coex_supported_version == 0) ||
+	     (coex_sta->bt_coex_supported_version == 0xffff)) && (!coex_sta->bt_disabled))
+		btcoexist->btc_get(btcoexist, BTC_GET_U4_SUPPORTED_VERSION, &coex_sta->bt_coex_supported_version);
+
+	btcoexist->btc_get(btcoexist, BTC_GET_U4_BT_PATCH_VER, &bt_patch_ver);
+	btcoexist->bt_info.bt_get_fw_ver = bt_patch_ver;
+
+#if (BT_AUTO_REPORT_ONLY_8821A_2ANT == 0)
+	halbtc8821a2ant_query_bt_info(btcoexist);
+	halbtc8821a2ant_monitor_bt_enable_disable(btcoexist);
+#else
+	halbtc8821a2ant_monitor_bt_ctr(btcoexist);
+	halbtc8821a2ant_monitor_wifi_ctr(btcoexist);
+	halbtc8821a2ant_monitor_bt_enable_disable(btcoexist);
+
+	if (halbtc8821a2ant_is_wifi_status_changed(btcoexist) ||
+	    coex_dm->auto_tdma_adjust)
+		halbtc8821a2ant_run_coexist_mechanism(btcoexist);
+#endif
+}
+
+#endif
+
+#endif	/* #if (BT_SUPPORT == 1 && COEX_SUPPORT == 1) */
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/btc/halbtc8821a2ant.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/btc/halbtc8821a2ant.h
--- linux-5.6.3/3rdparty/rtl8821ce/hal/btc/halbtc8821a2ant.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/btc/halbtc8821a2ant.h	2020-04-10 16:35:06.784658573 +0300
@@ -0,0 +1,211 @@
+
+#if (BT_SUPPORT == 1 && COEX_SUPPORT == 1)
+
+#if (RTL8821A_SUPPORT == 1)
+
+/* *******************************************
+ * The following is for 8821A 2Ant BT Co-exist definition
+ * ******************************************* */
+#define	BT_AUTO_REPORT_ONLY_8821A_2ANT				1
+
+
+#define	BT_INFO_8821A_2ANT_B_FTP						BIT(7)
+#define	BT_INFO_8821A_2ANT_B_A2DP					BIT(6)
+#define	BT_INFO_8821A_2ANT_B_HID						BIT(5)
+#define	BT_INFO_8821A_2ANT_B_SCO_BUSY				BIT(4)
+#define	BT_INFO_8821A_2ANT_B_ACL_BUSY				BIT(3)
+#define	BT_INFO_8821A_2ANT_B_INQ_PAGE				BIT(2)
+#define	BT_INFO_8821A_2ANT_B_SCO_ESCO				BIT(1)
+#define	BT_INFO_8821A_2ANT_B_CONNECTION				BIT(0)
+
+#define		BTC_RSSI_COEX_THRESH_TOL_8821A_2ANT		2
+
+
+#define	BT_8821A_2ANT_WIFI_RSSI_COEXSWITCH_THRES				42  /* WiFi RSSI Threshold for 2-Ant TDMA/1-Ant PS-TDMA translation */
+#define	BT_8821A_2ANT_BT_RSSI_COEXSWITCH_THRES				46 /* BT RSSI Threshold for 2-Ant TDMA/1-Ant PS-TDMA translation */
+
+enum bt_info_src_8821a_2ant {
+	BT_INFO_SRC_8821A_2ANT_WIFI_FW			= 0x0,
+	BT_INFO_SRC_8821A_2ANT_BT_RSP				= 0x1,
+	BT_INFO_SRC_8821A_2ANT_BT_ACTIVE_SEND		= 0x2,
+	BT_INFO_SRC_8821A_2ANT_MAX
+};
+
+enum bt_8821a_2ant_bt_status {
+	BT_8821A_2ANT_BT_STATUS_NON_CONNECTED_IDLE	= 0x0,
+	BT_8821A_2ANT_BT_STATUS_CONNECTED_IDLE		= 0x1,
+	BT_8821A_2ANT_BT_STATUS_INQ_PAGE				= 0x2,
+	BT_8821A_2ANT_BT_STATUS_ACL_BUSY				= 0x3,
+	BT_8821A_2ANT_BT_STATUS_SCO_BUSY				= 0x4,
+	BT_8821A_2ANT_BT_STATUS_ACL_SCO_BUSY			= 0x5,
+	BT_8821A_2ANT_BT_STATUS_MAX
+};
+
+enum bt_8821a_2ant_coex_algo {
+	BT_8821A_2ANT_COEX_ALGO_UNDEFINED			= 0x0,
+	BT_8821A_2ANT_COEX_ALGO_SCO				= 0x1,
+	BT_8821A_2ANT_COEX_ALGO_HID				= 0x2,
+	BT_8821A_2ANT_COEX_ALGO_A2DP				= 0x3,
+	BT_8821A_2ANT_COEX_ALGO_A2DP_PANHS		= 0x4,
+	BT_8821A_2ANT_COEX_ALGO_PANEDR			= 0x5,
+	BT_8821A_2ANT_COEX_ALGO_PANHS			= 0x6,
+	BT_8821A_2ANT_COEX_ALGO_PANEDR_A2DP		= 0x7,
+	BT_8821A_2ANT_COEX_ALGO_PANEDR_HID		= 0x8,
+	BT_8821A_2ANT_COEX_ALGO_HID_A2DP_PANEDR	= 0x9,
+	BT_8821A_2ANT_COEX_ALGO_HID_A2DP			= 0xa,
+	BT_8821A_2ANT_COEX_ALGO_MAX				= 0xb,
+};
+
+struct coex_dm_8821a_2ant {
+	/* fw mechanism */
+	u8		pre_bt_dec_pwr_lvl;
+	u8		cur_bt_dec_pwr_lvl;
+	u8		pre_fw_dac_swing_lvl;
+	u8		cur_fw_dac_swing_lvl;
+	boolean		cur_ignore_wlan_act;
+	boolean		pre_ignore_wlan_act;
+	u8		pre_ps_tdma;
+	u8		cur_ps_tdma;
+	u8		ps_tdma_para[5];
+	u8		ps_tdma_du_adj_type;
+	boolean		reset_tdma_adjust;
+	boolean		auto_tdma_adjust;
+	boolean		pre_ps_tdma_on;
+	boolean		cur_ps_tdma_on;
+	boolean		pre_bt_auto_report;
+	boolean		cur_bt_auto_report;
+
+	/* sw mechanism */
+	boolean		pre_rf_rx_lpf_shrink;
+	boolean		cur_rf_rx_lpf_shrink;
+	u32		bt_rf_0x1e_backup;
+	boolean	pre_low_penalty_ra;
+	boolean		cur_low_penalty_ra;
+	boolean		pre_dac_swing_on;
+	u32		pre_dac_swing_lvl;
+	boolean		cur_dac_swing_on;
+	u32		cur_dac_swing_lvl;
+	boolean		pre_adc_back_off;
+	boolean		cur_adc_back_off;
+	boolean	pre_agc_table_en;
+	boolean		cur_agc_table_en;
+	u32		pre_val0x6c0;
+	u32		cur_val0x6c0;
+	u32		pre_val0x6c4;
+	u32		cur_val0x6c4;
+	u32		pre_val0x6c8;
+	u32		cur_val0x6c8;
+	u8		pre_val0x6cc;
+	u8		cur_val0x6cc;
+	boolean		limited_dig;
+
+	/* algorithm related */
+	u8		pre_algorithm;
+	u8		cur_algorithm;
+	u8		bt_status;
+	u8		wifi_chnl_info[3];
+
+	boolean		need_recover0x948;
+	u32		backup0x948;
+
+	u8		pre_lps;
+	u8		cur_lps;
+	u8		pre_rpwm;
+	u8		cur_rpwm;
+};
+
+struct coex_sta_8821a_2ant {
+	boolean					bt_disabled;
+	boolean					bt_link_exist;
+	boolean					sco_exist;
+	boolean					a2dp_exist;
+	boolean					hid_exist;
+	boolean					pan_exist;
+
+	boolean					under_lps;
+	boolean					under_ips;
+	u32					high_priority_tx;
+	u32					high_priority_rx;
+	u32					low_priority_tx;
+	u32					low_priority_rx;
+	u8					bt_rssi;
+	boolean					bt_tx_rx_mask;
+	u8					pre_bt_rssi_state;
+	u8					pre_wifi_rssi_state[4];
+	boolean					c2h_bt_info_req_sent;
+	u8					bt_info_c2h[BT_INFO_SRC_8821A_2ANT_MAX][10];
+	u32					bt_info_c2h_cnt[BT_INFO_SRC_8821A_2ANT_MAX];
+	boolean				bt_whck_test;
+	boolean					c2h_bt_inquiry_page;
+	u8					bt_retry_cnt;
+	u8					bt_info_ext;
+	u8					scan_ap_num;
+	u32					crc_ok_cck;
+	u32					crc_ok_11g;
+	u32					crc_ok_11n;
+	u32					crc_ok_11n_vht;
+
+	u32					crc_err_cck;
+	u32					crc_err_11g;
+	u32					crc_err_11n;
+	u32					crc_err_11n_vht;
+
+	u32					bt_coex_supported_version;
+	u8					cut_version;
+	u8					coex_table_type;
+	boolean					force_lps_on;
+
+	u8					dis_ver_info_cnt;
+};
+
+/* *******************************************
+ * The following is interface which will notify coex module.
+ * ******************************************* */
+void ex_halbtc8821a2ant_power_on_setting(IN struct btc_coexist *btcoexist);
+void ex_halbtc8821a2ant_pre_load_firmware(IN struct btc_coexist *btcoexist);
+void ex_halbtc8821a2ant_init_hw_config(IN struct btc_coexist *btcoexist,
+				       IN boolean wifi_only);
+void ex_halbtc8821a2ant_init_coex_dm(IN struct btc_coexist *btcoexist);
+void ex_halbtc8821a2ant_ips_notify(IN struct btc_coexist *btcoexist,
+				   IN u8 type);
+void ex_halbtc8821a2ant_lps_notify(IN struct btc_coexist *btcoexist,
+				   IN u8 type);
+void ex_halbtc8821a2ant_scan_notify(IN struct btc_coexist *btcoexist,
+				    IN u8 type);
+void ex_halbtc8821a2ant_switchband_notify(IN struct btc_coexist *btcoexist,
+		IN u8 type);
+void ex_halbtc8821a2ant_connect_notify(IN struct btc_coexist *btcoexist,
+				       IN u8 type);
+void ex_halbtc8821a2ant_media_status_notify(IN struct btc_coexist *btcoexist,
+		IN u8 type);
+void ex_halbtc8821a2ant_specific_packet_notify(IN struct btc_coexist *btcoexist,
+		IN u8 type);
+void ex_halbtc8821a2ant_bt_info_notify(IN struct btc_coexist *btcoexist,
+				       IN u8 *tmp_buf, IN u8 length);
+void ex_halbtc8821a2ant_halt_notify(IN struct btc_coexist *btcoexist);
+void ex_halbtc8821a2ant_pnp_notify(IN struct btc_coexist *btcoexist,
+				   IN u8 pnp_state);
+void ex_halbtc8821a2ant_periodical(IN struct btc_coexist *btcoexist);
+void ex_halbtc8821a2ant_display_coex_info(IN struct btc_coexist *btcoexist);
+
+#else
+#define	ex_halbtc8821a2ant_power_on_setting(btcoexist)
+#define	ex_halbtc8821a2ant_pre_load_firmware(btcoexist)
+#define	ex_halbtc8821a2ant_init_hw_config(btcoexist, wifi_only)
+#define	ex_halbtc8821a2ant_init_coex_dm(btcoexist)
+#define	ex_halbtc8821a2ant_ips_notify(btcoexist, type)
+#define	ex_halbtc8821a2ant_lps_notify(btcoexist, type)
+#define	ex_halbtc8821a2ant_scan_notify(btcoexist, type)
+#define	ex_halbtc8821a2ant_switchband_notify(btcoexist, type)
+#define	ex_halbtc8821a2ant_connect_notify(btcoexist, type)
+#define	ex_halbtc8821a2ant_media_status_notify(btcoexist, type)
+#define	ex_halbtc8821a2ant_specific_packet_notify(btcoexist, type)
+#define	ex_halbtc8821a2ant_bt_info_notify(btcoexist, tmp_buf, length)
+#define	ex_halbtc8821a2ant_halt_notify(btcoexist)
+#define	ex_halbtc8821a2ant_pnp_notify(btcoexist, pnp_state)
+#define	ex_halbtc8821a2ant_periodical(btcoexist)
+#define	ex_halbtc8821a2ant_display_coex_info(btcoexist)
+#endif
+
+#endif
+
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/btc/halbtc8821c1ant.c linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/btc/halbtc8821c1ant.c
--- linux-5.6.3/3rdparty/rtl8821ce/hal/btc/halbtc8821c1ant.c	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/btc/halbtc8821c1ant.c	2020-04-10 16:35:06.785658620 +0300
@@ -0,0 +1,5492 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2016 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#include "mp_precomp.h"
+
+#if (BT_SUPPORT == 1 && COEX_SUPPORT == 1)
+
+#if (RTL8821C_SUPPORT == 1)
+static u8	*trace_buf = &gl_btc_trace_buf[0];
+
+const char *const glbt_info_src_8821c_1ant[] = {
+	"BT Info[wifi fw]",
+	"BT Info[bt rsp]",
+	"BT Info[bt auto report]",
+};
+
+u32 glcoex_ver_date_8821c_1ant = 20180712;
+u32 glcoex_ver_8821c_1ant = 0x32;
+u32 glcoex_ver_btdesired_8821c_1ant = 0x28;
+
+#if 0
+static
+u8 halbtc8821c1ant_bt_rssi_state(struct btc_coexist *btc, u8 level_num,
+				 u8 rssi_thresh, u8 rssi_thresh1)
+{
+	struct coex_sta_8821c_1ant *coex_sta = &btc->coex_sta_8821c_1ant;
+	s32 bt_rssi = 0;
+	u8 bt_rssi_state = coex_sta->pre_bt_rssi_state;
+
+	bt_rssi = coex_sta->bt_rssi;
+
+	if (level_num == 2) {
+		if (coex_sta->pre_bt_rssi_state == BTC_RSSI_STATE_LOW ||
+		    coex_sta->pre_bt_rssi_state ==
+		     BTC_RSSI_STATE_STAY_LOW) {
+			if (bt_rssi >= (rssi_thresh +
+					BTC_RSSI_COEX_THRESH_TOL_8821C_1ANT))
+				bt_rssi_state = BTC_RSSI_STATE_HIGH;
+			else
+				bt_rssi_state = BTC_RSSI_STATE_STAY_LOW;
+		} else {
+			if (bt_rssi < rssi_thresh)
+				bt_rssi_state = BTC_RSSI_STATE_LOW;
+			else
+				bt_rssi_state = BTC_RSSI_STATE_STAY_HIGH;
+		}
+	} else if (level_num == 3) {
+		if (rssi_thresh > rssi_thresh1) {
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				    "[BTCoex], BT Rssi thresh error!!\n");
+			BTC_TRACE(trace_buf);
+			return coex_sta->pre_bt_rssi_state;
+		}
+
+		if (coex_sta->pre_bt_rssi_state == BTC_RSSI_STATE_LOW ||
+		    coex_sta->pre_bt_rssi_state ==
+		     BTC_RSSI_STATE_STAY_LOW) {
+			if (bt_rssi >= (rssi_thresh +
+					BTC_RSSI_COEX_THRESH_TOL_8821C_1ANT))
+				bt_rssi_state = BTC_RSSI_STATE_MEDIUM;
+			else
+				bt_rssi_state = BTC_RSSI_STATE_STAY_LOW;
+		} else if (coex_sta->pre_bt_rssi_state ==
+			   BTC_RSSI_STATE_MEDIUM ||
+			   coex_sta->pre_bt_rssi_state ==
+			    BTC_RSSI_STATE_STAY_MEDIUM) {
+			if (bt_rssi >= (rssi_thresh1 +
+					BTC_RSSI_COEX_THRESH_TOL_8821C_1ANT))
+				bt_rssi_state = BTC_RSSI_STATE_HIGH;
+			else if (bt_rssi < rssi_thresh)
+				bt_rssi_state = BTC_RSSI_STATE_LOW;
+			else
+				bt_rssi_state = BTC_RSSI_STATE_STAY_MEDIUM;
+		} else {
+			if (bt_rssi < rssi_thresh1)
+				bt_rssi_state = BTC_RSSI_STATE_MEDIUM;
+			else
+				bt_rssi_state = BTC_RSSI_STATE_STAY_HIGH;
+		}
+	}
+
+	coex_sta->pre_bt_rssi_state = bt_rssi_state;
+
+	return bt_rssi_state;
+}
+#endif
+
+#if 0
+static
+u8 halbtc8821c1ant_wifi_rssi_state(struct btc_coexist *btc, u8 index,
+				   u8 level_num, u8 rssi_thresh,
+				   u8 rssi_thresh1)
+{
+	struct coex_sta_8821c_1ant *coex_sta = &btc->coex_sta_8821c_1ant;
+	s32 wifi_rssi = 0;
+	u8 wifi_rssi_state = coex_sta->pre_wifi_rssi_state[index];
+
+	btc->btc_get(btc, BTC_GET_S4_WIFI_RSSI, &wifi_rssi);
+
+	if (level_num == 2) {
+		if (coex_sta->pre_wifi_rssi_state[index] ==
+		    BTC_RSSI_STATE_LOW ||
+		    coex_sta->pre_wifi_rssi_state[index] ==
+		    BTC_RSSI_STATE_STAY_LOW) {
+			if (wifi_rssi >= rssi_thresh +
+					  BTC_RSSI_COEX_THRESH_TOL_8821C_1ANT)
+				wifi_rssi_state = BTC_RSSI_STATE_HIGH;
+			else
+				wifi_rssi_state = BTC_RSSI_STATE_STAY_LOW;
+		} else {
+			if (wifi_rssi < rssi_thresh)
+				wifi_rssi_state = BTC_RSSI_STATE_LOW;
+			else
+				wifi_rssi_state = BTC_RSSI_STATE_STAY_HIGH;
+		}
+	} else if (level_num == 3) {
+		if (rssi_thresh > rssi_thresh1) {
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				    "[BTCoex], wifi RSSI thresh error!!\n");
+			BTC_TRACE(trace_buf);
+			return coex_sta->pre_wifi_rssi_state[index];
+		}
+
+		if (coex_sta->pre_wifi_rssi_state[index] ==
+		    BTC_RSSI_STATE_LOW ||
+		    coex_sta->pre_wifi_rssi_state[index] ==
+		    BTC_RSSI_STATE_STAY_LOW) {
+			if (wifi_rssi >= rssi_thresh +
+					  BTC_RSSI_COEX_THRESH_TOL_8821C_1ANT)
+				wifi_rssi_state = BTC_RSSI_STATE_MEDIUM;
+			else
+				wifi_rssi_state = BTC_RSSI_STATE_STAY_LOW;
+		} else if (coex_sta->pre_wifi_rssi_state[index] ==
+			    BTC_RSSI_STATE_MEDIUM ||
+			   coex_sta->pre_wifi_rssi_state[index] ==
+			    BTC_RSSI_STATE_STAY_MEDIUM) {
+			if (wifi_rssi >= rssi_thresh1 +
+					  BTC_RSSI_COEX_THRESH_TOL_8821C_1ANT)
+				wifi_rssi_state = BTC_RSSI_STATE_HIGH;
+			else if (wifi_rssi < rssi_thresh)
+				wifi_rssi_state = BTC_RSSI_STATE_LOW;
+			else
+				wifi_rssi_state = BTC_RSSI_STATE_STAY_MEDIUM;
+		} else {
+			if (wifi_rssi < rssi_thresh1)
+				wifi_rssi_state = BTC_RSSI_STATE_MEDIUM;
+			else
+				wifi_rssi_state = BTC_RSSI_STATE_STAY_HIGH;
+		}
+	}
+
+	coex_sta->pre_wifi_rssi_state[index] = wifi_rssi_state;
+
+	return wifi_rssi_state;
+}
+#endif
+
+static
+void halbtc8821c1ant_limited_rx(struct btc_coexist *btc, boolean force_exec,
+				boolean rej_ap_agg_pkt,
+				boolean bt_ctrl_agg_buf_size, u8 agg_buf_size)
+{
+	boolean	reject_rx_agg = rej_ap_agg_pkt;
+	boolean	bt_ctrl_rx_agg_size = bt_ctrl_agg_buf_size;
+	u8 rx_agg_size = agg_buf_size;
+
+	/* ============================================
+	 *	Rx Aggregation related setting
+	 * ============================================
+	 */
+	btc->btc_set(btc, BTC_SET_BL_TO_REJ_AP_AGG_PKT, &reject_rx_agg);
+	/* decide BT control aggregation buf size or not */
+	btc->btc_set(btc, BTC_SET_BL_BT_CTRL_AGG_SIZE, &bt_ctrl_rx_agg_size);
+	/* aggregation buf size, only work
+	 * when BT control Rx aggregation size
+	 */
+	btc->btc_set(btc, BTC_SET_U1_AGG_BUF_SIZE, &rx_agg_size);
+	/* real update aggregation setting */
+	btc->btc_set(btc, BTC_SET_ACT_AGGREGATE_CTRL, NULL);
+}
+
+static
+void halbtc8821c1ant_low_penalty_ra(struct btc_coexist *btc,
+				    boolean force_exec, boolean low_penalty_ra,
+				    u8 thres)
+{
+	struct coex_dm_8821c_1ant *coex_dm = &btc->coex_dm_8821c_1ant;
+	static u8 cur_thres;
+
+	if (!force_exec) {
+		if (low_penalty_ra == coex_dm->cur_low_penalty_ra &&
+		    thres == cur_thres)
+			return;
+	}
+
+	if (low_penalty_ra)
+		btc->btc_phydm_modify_RA_PCR_threshold(btc, 0, thres);
+	else
+		btc->btc_phydm_modify_RA_PCR_threshold(btc, 0, 0);
+
+	coex_dm->cur_low_penalty_ra = low_penalty_ra;
+	cur_thres = thres;
+}
+
+static
+void halbtc8821c1ant_write_scbd(struct  btc_coexist *btc, u16 bitpos,
+				boolean state)
+{
+	struct coex_sta_8821c_1ant *coex_sta = &btc->coex_sta_8821c_1ant;
+	static u16 originalval = 0x8002, preval;
+
+	if (state)
+		originalval = originalval | bitpos;
+	else
+		originalval = originalval & (~bitpos);
+
+	coex_sta->score_board_WB = originalval;
+
+	if (originalval != preval) {
+		preval = originalval;
+		btc->btc_write_2byte(btc, 0xaa, originalval);
+	} else {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], %s: return for nochange\n", __func__);
+		BTC_TRACE(trace_buf);
+	}
+}
+
+static
+void halbtc8821c1ant_read_scbd(struct  btc_coexist	*btc,
+			       u16 *score_board_val)
+{
+	*score_board_val = (btc->btc_read_2byte(btc, 0xaa)) & 0x7fff;
+}
+
+static
+void halbtc8821c1ant_query_bt_info(struct btc_coexist *btc)
+{
+	struct coex_sta_8821c_1ant *coex_sta = &btc->coex_sta_8821c_1ant;
+	u8 h2c_parameter[1] = {0};
+
+	if (coex_sta->bt_disabled) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], No query BT info because BT is disabled!\n");
+		BTC_TRACE(trace_buf);
+		return;
+	}
+
+
+	h2c_parameter[0] |= BIT(0);	/* trigger */
+
+	btc->btc_fill_h2c(btc, 0x61, 1, h2c_parameter);
+
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+		    "[BTCoex], WL query BT info!!\n");
+	BTC_TRACE(trace_buf);
+}
+
+static
+void halbtc8821c1ant_enable_gnt_to_gpio(struct btc_coexist *btc,
+					boolean isenable)
+{
+	static u8	bit_val[5] = {0, 0, 0, 0, 0};
+	static boolean state;
+
+	if (!btc->dbg_mode)
+		return;
+
+	if (state == isenable)
+		return;
+
+	state = isenable;
+
+	if (isenable) {
+		/* enable GNT_WL, GNT_BT to GPIO for debug */
+		btc->btc_write_1byte_bitmask(btc, 0x73, 0x8, 0x1);
+
+		/* store original value */
+		/*0x66[4] */
+		bit_val[0] = (btc->btc_read_1byte(btc, 0x66) & BIT(4)) >> 4;
+		/*0x66[8] */
+		bit_val[1] = (btc->btc_read_1byte(btc, 0x67) & BIT(0));
+		/*0x40[19] */
+		bit_val[2] = (btc->btc_read_1byte(btc, 0x42) & BIT(3)) >> 3;
+		/*0x64[15] */
+		bit_val[3] = (btc->btc_read_1byte(btc, 0x65) & BIT(7)) >> 7;
+		/*0x70[18] */
+		bit_val[4] = (btc->btc_read_1byte(btc, 0x72) & BIT(2)) >> 2;
+
+		/*  switch GPIO Mux */
+		/*0x66[4] = 0 */
+		btc->btc_write_1byte_bitmask(btc, 0x66, BIT(4), 0x0);
+		/*0x66[8] = 0 */
+		btc->btc_write_1byte_bitmask(btc, 0x67, BIT(0), 0x0);
+		/*0x40[19] = 0 */
+		btc->btc_write_1byte_bitmask(btc, 0x42, BIT(3), 0x0);
+		/*0x64[15] = 0 */
+		btc->btc_write_1byte_bitmask(btc, 0x65, BIT(7), 0x0);
+		 /*0x70[18] = 0 */
+		btc->btc_write_1byte_bitmask(btc, 0x72, BIT(2), 0x0);
+	} else {
+		btc->btc_write_1byte_bitmask(btc, 0x73, 0x8, 0x0);
+
+		/*  Restore original value */
+		/*  switch GPIO Mux */
+		/*0x66[4] = 0 */
+		btc->btc_write_1byte_bitmask(btc, 0x66, BIT(4), bit_val[0]);
+		/*0x66[8] = 0 */
+		btc->btc_write_1byte_bitmask(btc, 0x67, BIT(0), bit_val[1]);
+		/*0x40[19] = 0 */
+		btc->btc_write_1byte_bitmask(btc, 0x42, BIT(3), bit_val[2]);
+		/*0x64[15] = 0 */
+		btc->btc_write_1byte_bitmask(btc, 0x65, BIT(7), bit_val[3]);
+		/*0x70[18] = 0 */
+		btc->btc_write_1byte_bitmask(btc, 0x72, BIT(2), bit_val[4]);
+	}
+}
+
+static
+void halbtc8821c1ant_monitor_bt_ctr(struct btc_coexist *btc)
+{
+	struct coex_sta_8821c_1ant *coex_sta = &btc->coex_sta_8821c_1ant;
+	struct coex_dm_8821c_1ant *coex_dm = &btc->coex_dm_8821c_1ant;
+	u32 reg_hp_txrx, reg_lp_txrx, u32tmp;
+	u32 reg_hp_tx = 0, reg_hp_rx = 0, reg_lp_tx = 0, reg_lp_rx = 0;
+	static u8	num_of_bt_counter_chk, cnt_slave, cnt_overhead,
+		cnt_autoslot_hang;
+	struct  btc_bt_link_info *bt_link_info = &btc->bt_link_info;
+
+	/* to avoid 0x76e[3] = 1 (WLAN_Act control by PTA) during IPS */
+	/* if (! (btc->btc_read_1byte(btc, 0x76e) & 0x8) ) */
+
+	reg_hp_txrx = 0x770;
+	reg_lp_txrx = 0x774;
+
+	u32tmp = btc->btc_read_4byte(btc, reg_hp_txrx);
+	reg_hp_tx = u32tmp & MASKLWORD;
+	reg_hp_rx = (u32tmp & MASKHWORD) >> 16;
+
+	u32tmp = btc->btc_read_4byte(btc, reg_lp_txrx);
+	reg_lp_tx = u32tmp & MASKLWORD;
+	reg_lp_rx = (u32tmp & MASKHWORD) >> 16;
+
+	coex_sta->high_priority_tx = reg_hp_tx;
+	coex_sta->high_priority_rx = reg_hp_rx;
+	coex_sta->low_priority_tx = reg_lp_tx;
+	coex_sta->low_priority_rx = reg_lp_rx;
+
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+		    "[BTCoex], Hi-Pri Rx/Tx: %d/%d, Lo-Pri Rx/Tx: %d/%d\n",
+		    reg_hp_rx, reg_hp_tx, reg_lp_rx, reg_lp_tx);
+
+	BTC_TRACE(trace_buf);
+
+	if (coex_dm->bt_status == BT_8821C_1ANT_BSTATUS_NCON_IDLE) {
+
+		if (coex_sta->high_priority_rx >= 15) {
+			if (cnt_overhead < 3)
+				cnt_overhead++;
+
+			if (cnt_overhead == 3)
+				coex_sta->is_hi_pri_rx_overhead = TRUE;
+
+		} else {
+			if (cnt_overhead > 0)
+				cnt_overhead--;
+
+			if (cnt_overhead == 0)
+				coex_sta->is_hi_pri_rx_overhead = FALSE;
+		}
+	} else
+		coex_sta->is_hi_pri_rx_overhead = FALSE;
+
+	/* reset counter */
+	btc->btc_write_1byte(btc, 0x76e, 0xc);
+
+	if (coex_sta->low_priority_tx > 1150  && !coex_sta->c2h_bt_inquiry_page)
+		coex_sta->pop_event_cnt++;
+
+	if (coex_sta->low_priority_rx >= 1150 &&
+	    coex_sta->low_priority_rx >= coex_sta->low_priority_tx &&
+	    !coex_sta->under_ips && !coex_sta->c2h_bt_inquiry_page &&
+	    (bt_link_info->a2dp_exist || bt_link_info->pan_exist)) {
+		if (cnt_slave >= 2) {
+			bt_link_info->slave_role = TRUE;
+			cnt_slave = 2;
+		} else
+			cnt_slave++;
+	} else {
+		if (cnt_slave == 0) {
+			bt_link_info->slave_role = FALSE;
+			cnt_slave = 0;
+		} else
+			cnt_slave--;
+	}
+
+	if (coex_sta->is_tdma_btautoslot) {
+		if (coex_sta->low_priority_tx >= 1300 &&
+		    coex_sta->low_priority_rx <= 15) {
+			if (cnt_autoslot_hang >= 2) {
+				coex_sta->is_tdma_btautoslot_hang = TRUE;
+				cnt_autoslot_hang = 2;
+			} else
+				cnt_autoslot_hang++;
+		} else {
+			if (cnt_autoslot_hang == 0)	{
+				coex_sta->is_tdma_btautoslot_hang = FALSE;
+				cnt_autoslot_hang = 0;
+			} else
+				cnt_autoslot_hang--;
+		}
+	}
+
+	if (bt_link_info->hid_only) {
+		if (coex_sta->low_priority_tx > 100)
+			coex_sta->is_hid_low_pri_tx_overhead = true;
+		else
+			coex_sta->is_hid_low_pri_tx_overhead = false;
+	}
+
+	if (!coex_sta->bt_disabled) {
+		if ((coex_sta->high_priority_tx == 0) &&
+		    (coex_sta->high_priority_rx == 0) &&
+		    (coex_sta->low_priority_tx == 0) &&
+		    (coex_sta->low_priority_rx == 0)) {
+			num_of_bt_counter_chk++;
+			if (num_of_bt_counter_chk >= 3) {
+				halbtc8821c1ant_query_bt_info(btc);
+				num_of_bt_counter_chk = 0;
+			}
+		}
+	}
+}
+
+static
+void halbtc8821c1ant_monitor_wifi_ctr(struct btc_coexist *btc)
+{
+	struct coex_sta_8821c_1ant *coex_sta = &btc->coex_sta_8821c_1ant;
+	struct coex_dm_8821c_1ant *coex_dm = &btc->coex_dm_8821c_1ant;
+	boolean wifi_busy = FALSE, wifi_scan = FALSE;
+	static u8 wl_noisy_count0, wl_noisy_count1 = 3, wl_noisy_count2;
+	u32 cnt_cck;
+	static u8 cnt_ccklocking;
+	u8 h2c_parameter[1] = {0};
+	struct  btc_bt_link_info *bt_link_info = &btc->bt_link_info;
+
+	/* Only enable for windows becaus 8821cu
+	 * H2C 0x69 unknown fail @ linux
+	 */
+	if (btc->chip_interface != BTC_INTF_USB) {
+		/*send h2c to query WL FW dbg info  */
+		if ((coex_dm->cur_ps_tdma_on && coex_sta->force_lps_ctrl) ||
+		    (coex_sta->acl_busy && bt_link_info->a2dp_exist)) {
+			h2c_parameter[0] = 0x8;
+			btc->btc_fill_h2c(btc, 0x69, 1, h2c_parameter);
+		}
+	}
+
+	btc->btc_get(btc, BTC_GET_BL_WIFI_BUSY, &wifi_busy);
+	btc->btc_get(btc, BTC_GET_BL_WIFI_SCAN, &wifi_scan);
+
+	coex_sta->crc_ok_cck =
+		btc->btc_phydm_query_PHY_counter(btc, PHYDM_INFO_CRC32_OK_CCK);
+	coex_sta->crc_ok_11g =
+	    btc->btc_phydm_query_PHY_counter(btc, PHYDM_INFO_CRC32_OK_LEGACY);
+	coex_sta->crc_ok_11n =
+		btc->btc_phydm_query_PHY_counter(btc, PHYDM_INFO_CRC32_OK_HT);
+	coex_sta->crc_ok_11n_vht =
+		btc->btc_phydm_query_PHY_counter(btc, PHYDM_INFO_CRC32_OK_VHT);
+
+	coex_sta->crc_err_cck =
+	    btc->btc_phydm_query_PHY_counter(btc, PHYDM_INFO_CRC32_ERROR_CCK);
+	coex_sta->crc_err_11g =
+	  btc->btc_phydm_query_PHY_counter(btc, PHYDM_INFO_CRC32_ERROR_LEGACY);
+	coex_sta->crc_err_11n =
+	    btc->btc_phydm_query_PHY_counter(btc, PHYDM_INFO_CRC32_ERROR_HT);
+	coex_sta->crc_err_11n_vht =
+	    btc->btc_phydm_query_PHY_counter(btc, PHYDM_INFO_CRC32_ERROR_VHT);
+
+	/* CCK lock identification */
+	if (coex_sta->cck_lock)
+		cnt_ccklocking++;
+	else if	(cnt_ccklocking != 0)
+		cnt_ccklocking--;
+
+	if (cnt_ccklocking >= 3) {
+		cnt_ccklocking = 3;
+		coex_sta->cck_lock_ever = TRUE;
+	}
+
+	/* WiFi environment noisy identification */
+	cnt_cck = coex_sta->crc_ok_cck + coex_sta->crc_err_cck;
+
+	if (!wifi_busy && !coex_sta->cck_lock) {
+		if (cnt_cck > 250) {
+			if (wl_noisy_count2 < 3)
+				wl_noisy_count2++;
+
+			if (wl_noisy_count2 == 3) {
+				wl_noisy_count0 = 0;
+				wl_noisy_count1 = 0;
+			}
+
+		} else if (cnt_cck < 100) {
+			if (wl_noisy_count0 < 3)
+				wl_noisy_count0++;
+
+			if (wl_noisy_count0 == 3) {
+				wl_noisy_count1 = 0;
+				wl_noisy_count2 = 0;
+			}
+
+		} else {
+			if (wl_noisy_count1 < 3)
+				wl_noisy_count1++;
+
+			if (wl_noisy_count1 == 3) {
+				wl_noisy_count0 = 0;
+				wl_noisy_count2 = 0;
+			}
+	}
+
+		if (wl_noisy_count2 == 3)
+			coex_sta->wl_noisy_level = 2;
+		else if (wl_noisy_count1 == 3)
+			coex_sta->wl_noisy_level = 1;
+		else
+			coex_sta->wl_noisy_level = 0;
+	}
+}
+
+static
+void halbtc8821c1ant_monitor_bt_enable(struct btc_coexist *btc)
+{
+	struct coex_sta_8821c_1ant *coex_sta = &btc->coex_sta_8821c_1ant;
+	static u32	bt_disable_cnt;
+	boolean	bt_active = TRUE, bt_disabled = FALSE;
+	u16 u16tmp;
+
+	/* Read BT on/off status from scoreboard[1],
+	 * enable this only if BT patch support this feature
+	 */
+	halbtc8821c1ant_read_scbd(btc,	&u16tmp);
+
+	bt_active = u16tmp & BIT(1);
+
+	if (bt_active) {
+		bt_disable_cnt = 0;
+		bt_disabled = FALSE;
+		btc->btc_set(btc, BTC_SET_BL_BT_DISABLE, &bt_disabled);
+	} else {
+		bt_disable_cnt++;
+		if (bt_disable_cnt >= 2) {
+			bt_disabled = TRUE;
+			bt_disable_cnt = 2;
+		}
+
+		btc->btc_set(btc, BTC_SET_BL_BT_DISABLE, &bt_disabled);
+	}
+
+	if (coex_sta->bt_disabled != bt_disabled) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], BT is from %s to %s!!\n",
+			    (coex_sta->bt_disabled ? "disabled" : "enabled"),
+			    (bt_disabled ? "disabled" : "enabled"));
+		BTC_TRACE(trace_buf);
+		coex_sta->bt_disabled = bt_disabled;
+
+		/*for win10 BT disable->enable trigger wifi scan issue   */
+		if (!coex_sta->bt_disabled) {
+			coex_sta->is_bt_reenable = TRUE;
+			coex_sta->cnt_bt_reenable = 15;
+		} else {
+			coex_sta->is_bt_reenable = FALSE;
+			coex_sta->cnt_bt_reenable = 0;
+		}
+	}
+}
+
+static
+boolean halbtc8821c1ant_moniter_wifibt_status(struct btc_coexist *btc)
+{
+	struct coex_sta_8821c_1ant *coex_sta = &btc->coex_sta_8821c_1ant;
+	struct rfe_type_8821c_1ant *rfe_type = &btc->rfe_type_8821c_1ant;
+	struct wifi_link_info_8821c_1ant *wifi_link_info_ext =
+					 &btc->wifi_link_info_8821c_1ant;
+	static boolean pre_wifi_busy, pre_under_4way,
+		     pre_bt_off,
+		     pre_bt_slave, pre_hid_low_pri_tx_overhead,
+		     pre_wifi_under_lps, pre_bt_setup_link,
+		     pre_cck_lock, pre_cck_lock_warn;
+	static u8 pre_hid_busy_num, pre_wl_noisy_level;
+	boolean wifi_busy = FALSE, under_4way = FALSE;
+	boolean wifi_connected = FALSE;
+	struct  btc_bt_link_info *bt_link_info = &btc->bt_link_info;
+	static u8 cnt_wifi_busytoidle;
+	u32 num_of_wifi_link = 0, wifi_link_mode = 0;
+	static u32 pre_num_of_wifi_link, pre_wifi_link_mode;
+	boolean miracast_plus_bt = FALSE;
+	u8 lna_lvl = 1;
+
+	btc->btc_get(btc, BTC_GET_BL_WIFI_CONNECTED, &wifi_connected);
+	btc->btc_get(btc, BTC_GET_BL_WIFI_BUSY, &wifi_busy);
+	btc->btc_get(btc, BTC_GET_BL_WIFI_4_WAY_PROGRESS, &under_4way);
+
+	if (wifi_busy) {
+		coex_sta->gl_wifi_busy = TRUE;
+		cnt_wifi_busytoidle = 6;
+	} else {
+		if (coex_sta->gl_wifi_busy && cnt_wifi_busytoidle > 0)
+			cnt_wifi_busytoidle--;
+		else if (cnt_wifi_busytoidle == 0)
+			coex_sta->gl_wifi_busy = FALSE;
+	}
+
+	if (coex_sta->bt_disabled != pre_bt_off) {
+		pre_bt_off = coex_sta->bt_disabled;
+
+		if (coex_sta->bt_disabled)
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				    "[BTCoex], BT is disabled !!\n");
+		else
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				    "[BTCoex], BT is enabled !!\n");
+
+		BTC_TRACE(trace_buf);
+
+		coex_sta->bt_coex_supported_feature = 0;
+		coex_sta->bt_coex_supported_version = 0;
+		coex_sta->bt_ble_scan_type = 0;
+		coex_sta->bt_ble_scan_para[0] = 0;
+		coex_sta->bt_ble_scan_para[1] = 0;
+		coex_sta->bt_ble_scan_para[2] = 0;
+		coex_sta->bt_reg_vendor_ac = 0xffff;
+		coex_sta->bt_reg_vendor_ae = 0xffff;
+		coex_sta->legacy_forbidden_slot = 0;
+		coex_sta->le_forbidden_slot = 0;
+		coex_sta->bt_a2dp_vendor_id = 0;
+		coex_sta->bt_a2dp_device_name = 0;
+		return TRUE;
+	}
+
+	num_of_wifi_link = wifi_link_info_ext->num_of_active_port;
+
+	if (num_of_wifi_link != pre_num_of_wifi_link) {
+		pre_num_of_wifi_link = num_of_wifi_link;
+
+		if (wifi_link_info_ext->is_p2p_connected) {
+			if (bt_link_info->bt_link_exist)
+				miracast_plus_bt = TRUE;
+			else
+				miracast_plus_bt = FALSE;
+
+			btc->btc_set(btc, BTC_SET_BL_MIRACAST_PLUS_BT,
+				     &miracast_plus_bt);
+		}
+		return TRUE;
+	}
+
+	wifi_link_mode = btc->wifi_link_info.link_mode;
+	if (wifi_link_mode != pre_wifi_link_mode) {
+		pre_wifi_link_mode = wifi_link_mode;
+		return TRUE;
+	}
+
+	if (wifi_connected) {
+		if (wifi_busy != pre_wifi_busy) {
+			pre_wifi_busy = wifi_busy;
+			return TRUE;
+		}
+		if (under_4way != pre_under_4way) {
+			pre_under_4way = under_4way;
+			return TRUE;
+		}
+		if (coex_sta->wl_noisy_level != pre_wl_noisy_level) {
+			pre_wl_noisy_level = coex_sta->wl_noisy_level;
+			return TRUE;
+		}
+		if (coex_sta->under_lps != pre_wifi_under_lps) {
+			pre_wifi_under_lps = coex_sta->under_lps;
+			if (coex_sta->under_lps)
+				return TRUE;
+		}
+		if (coex_sta->cck_lock != pre_cck_lock) {
+			pre_cck_lock = coex_sta->cck_lock;
+			return TRUE;
+		}
+		if (coex_sta->cck_lock_warn != pre_cck_lock_warn) {
+			pre_cck_lock_warn = coex_sta->cck_lock_warn;
+			return TRUE;
+		}
+	}
+
+	if (!coex_sta->bt_disabled) {
+#if 0
+		if (coex_sta->acl_busy != pre_bt_acl_busy) {
+			pre_bt_acl_busy = coex_sta->acl_busy;
+			btc->btc_set(btc, BTC_SET_BL_BT_LNA_CONSTRAIN_LEVEL,
+				     &lna_lvl);
+			return TRUE;
+		}
+#endif
+		if (coex_sta->hid_busy_num != pre_hid_busy_num) {
+			pre_hid_busy_num = coex_sta->hid_busy_num;
+			return TRUE;
+		}
+
+		if (bt_link_info->slave_role != pre_bt_slave) {
+			pre_bt_slave = bt_link_info->slave_role;
+			return TRUE;
+		}
+
+		if (pre_hid_low_pri_tx_overhead !=
+				coex_sta->is_hid_low_pri_tx_overhead) {
+			pre_hid_low_pri_tx_overhead =
+				coex_sta->is_hid_low_pri_tx_overhead;
+			return TRUE;
+		}
+
+		if (pre_bt_setup_link != coex_sta->is_setup_link) {
+			pre_bt_setup_link = coex_sta->is_setup_link;
+			return TRUE;
+		}
+	}
+	return FALSE;
+}
+
+static
+void halbtc8821c1ant_update_wifi_link_info(struct btc_coexist *btc, u8 reason)
+{
+	struct coex_sta_8821c_1ant *coex_sta = &btc->coex_sta_8821c_1ant;
+	struct wifi_link_info_8821c_1ant *wifi_link_info_ext =
+					 &btc->wifi_link_info_8821c_1ant;
+	struct btc_wifi_link_info wifi_link_info;
+	u8 wifi_central_chnl = 0, num_of_wifi_link = 0;
+	boolean isunder5G = FALSE, ismcc25g = FALSE, isp2pconnected = FALSE;
+	u32 wifi_link_status = 0;
+
+	btc->btc_get(btc, BTC_GET_U4_WIFI_LINK_STATUS, &wifi_link_status);
+	wifi_link_info_ext->port_connect_status = wifi_link_status & 0xffff;
+
+	btc->btc_get(btc, BTC_GET_BL_WIFI_LINK_INFO, &wifi_link_info);
+	btc->wifi_link_info = wifi_link_info;
+
+	btc->btc_get(btc, BTC_GET_U1_WIFI_CENTRAL_CHNL, &wifi_central_chnl);
+	coex_sta->wl_center_channel = wifi_central_chnl;
+
+	/* Check scan/connect/special-pkt action first  */
+	switch (reason) {
+	case BT_8821C_1ANT_RSN_5GSCANSTART:
+	case BT_8821C_1ANT_RSN_5GSWITCHBAND:
+	case BT_8821C_1ANT_RSN_5GCONSTART:
+		isunder5G = TRUE;
+		break;
+	case BT_8821C_1ANT_RSN_2GSCANSTART:
+	case BT_8821C_1ANT_RSN_2GSWITCHBAND:
+	case BT_8821C_1ANT_RSN_2GCONSTART:
+		isunder5G = FALSE;
+		break;
+	case BT_8821C_1ANT_RSN_2GCONFINISH:
+	case BT_8821C_1ANT_RSN_5GCONFINISH:
+	case BT_8821C_1ANT_RSN_2GMEDIA:
+	case BT_8821C_1ANT_RSN_5GMEDIA:
+	case BT_8821C_1ANT_RSN_BTINFO:
+	case BT_8821C_1ANT_RSN_PERIODICAL:
+	case BT_8821C_1ANT_RSN_5GSPECIALPKT:
+	case BT_8821C_1ANT_RSN_2GSPECIALPKT:
+	default:
+		switch (wifi_link_info.link_mode) {
+		case BTC_LINK_5G_MCC_GO_STA:
+		case BTC_LINK_5G_MCC_GC_STA:
+		case BTC_LINK_5G_SCC_GO_STA:
+		case BTC_LINK_5G_SCC_GC_STA:
+			isunder5G = TRUE;
+			break;
+		case BTC_LINK_2G_MCC_GO_STA:
+		case BTC_LINK_2G_MCC_GC_STA:
+		case BTC_LINK_2G_SCC_GO_STA:
+		case BTC_LINK_2G_SCC_GC_STA:
+			isunder5G = FALSE;
+			break;
+		case BTC_LINK_25G_MCC_GO_STA:
+		case BTC_LINK_25G_MCC_GC_STA:
+			isunder5G = FALSE;
+			ismcc25g = TRUE;
+			break;
+		case BTC_LINK_ONLY_STA:
+			if (wifi_link_info.sta_center_channel > 14)
+				isunder5G = TRUE;
+			else
+				isunder5G = FALSE;
+			break;
+		case BTC_LINK_ONLY_GO:
+		case BTC_LINK_ONLY_GC:
+		case BTC_LINK_ONLY_AP:
+		default:
+			if (wifi_link_info.p2p_center_channel > 14)
+				isunder5G = TRUE;
+			else
+				isunder5G = FALSE;
+
+			break;
+		}
+		break;
+	}
+
+	wifi_link_info_ext->is_all_under_5g = isunder5G;
+	wifi_link_info_ext->is_mcc_25g = ismcc25g;
+
+	if (wifi_link_status & WIFI_STA_CONNECTED)
+		num_of_wifi_link++;
+
+	if (wifi_link_status & WIFI_AP_CONNECTED)
+		num_of_wifi_link++;
+
+	if (wifi_link_status & WIFI_P2P_GO_CONNECTED) {
+		num_of_wifi_link++;
+		isp2pconnected = TRUE;
+	}
+
+	if (wifi_link_status & WIFI_P2P_GC_CONNECTED) {
+		num_of_wifi_link++;
+		isp2pconnected = TRUE;
+	}
+
+	wifi_link_info_ext->num_of_active_port = num_of_wifi_link;
+	wifi_link_info_ext->is_p2p_connected = isp2pconnected;
+
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+		    "[BTCoex], wifi_link_info: link_mode=%d, STA_Ch=%d, P2P_Ch=%d, AnyClient_Join_Go=%d !\n",
+		    btc->wifi_link_info.link_mode,
+		    btc->wifi_link_info.sta_center_channel,
+		    btc->wifi_link_info.p2p_center_channel,
+		    btc->wifi_link_info.bany_client_join_go);
+	BTC_TRACE(trace_buf);
+
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+		    "[BTCoex], wifi_link_info: center_ch=%d, is_all_under_5g=%d, is_mcc_25g=%d!\n",
+		    coex_sta->wl_center_channel,
+		    wifi_link_info_ext->is_all_under_5g,
+		    wifi_link_info_ext->is_mcc_25g);
+	BTC_TRACE(trace_buf);
+
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+		    "[BTCoex], wifi_link_info: port_connect_status=0x%x, active_port_cnt=%d, P2P_Connect=%d!\n",
+		    wifi_link_info_ext->port_connect_status,
+		    wifi_link_info_ext->num_of_active_port,
+		    wifi_link_info_ext->is_p2p_connected);
+	BTC_TRACE(trace_buf);
+
+	switch (reason) {
+	case BT_8821C_1ANT_RSN_2GSCANSTART:
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], Update reason = %s\n", "2GSCANSTART");
+		break;
+	case BT_8821C_1ANT_RSN_5GSCANSTART:
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], Update reason = %s\n", "5GSCANSTART");
+		break;
+	case BT_8821C_1ANT_RSN_SCANFINISH:
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], Update reason = %s\n", "SCANFINISH");
+		break;
+	case BT_8821C_1ANT_RSN_2GSWITCHBAND:
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], Update reason = %s\n", "2GSWITCHBAND");
+		break;
+	case BT_8821C_1ANT_RSN_5GSWITCHBAND:
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], Update reason = %s\n", "5GSWITCHBAND");
+		break;
+	case BT_8821C_1ANT_RSN_2GCONSTART:
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], Update reason = %s\n", "2GCONNECTSTART");
+		break;
+	case BT_8821C_1ANT_RSN_5GCONSTART:
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], Update reason = %s\n", "5GCONNECTSTART");
+		break;
+	case BT_8821C_1ANT_RSN_2GCONFINISH:
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], Update reason = %s\n",
+			    "2GCONNECTFINISH");
+		break;
+	case BT_8821C_1ANT_RSN_5GCONFINISH:
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], Update reason = %s\n",
+			    "5GCONNECTFINISH");
+		break;
+	case BT_8821C_1ANT_RSN_2GMEDIA:
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], Update reason = %s\n", "2GMEDIASTATUS");
+		break;
+	case BT_8821C_1ANT_RSN_5GMEDIA:
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], Update reason = %s\n", "5GMEDIASTATUS");
+		break;
+	case BT_8821C_1ANT_RSN_MEDIADISCON:
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], Update reason = %s\n",
+			    "MEDIADISCONNECT");
+		break;
+	case BT_8821C_1ANT_RSN_2GSPECIALPKT:
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], Update reason = %s\n", "2GSPECIALPKT");
+		break;
+	case BT_8821C_1ANT_RSN_5GSPECIALPKT:
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], Update reason = %s\n", "5GSPECIALPKT");
+		break;
+	case BT_8821C_1ANT_RSN_BTINFO:
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], Update reason = %s\n", "BTINFO");
+		break;
+	case BT_8821C_1ANT_RSN_PERIODICAL:
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], Update reason = %s\n", "PERIODICAL");
+		break;
+	case BT_8821C_1ANT_RSN_PNP:
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], Update reason = %s\n", "PNPNotify");
+		break;
+	default:
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], Update reason = %s\n", "UNKNOWN");
+		break;
+	}
+
+	BTC_TRACE(trace_buf);
+
+	if (wifi_link_info_ext->is_all_under_5g ||
+	    coex_sta->num_of_profile == 0)
+		halbtc8821c1ant_low_penalty_ra(btc, NM_EXCU, FALSE, 0);
+	else if (wifi_link_info_ext->is_p2p_connected)
+		halbtc8821c1ant_low_penalty_ra(btc, NM_EXCU, TRUE, 30);
+	else
+		halbtc8821c1ant_low_penalty_ra(btc, NM_EXCU, TRUE, 15);
+}
+
+static
+void halbtc8821c1ant_update_bt_link_info(struct btc_coexist *btc)
+{
+	struct coex_sta_8821c_1ant *coex_sta = &btc->coex_sta_8821c_1ant;
+	struct coex_dm_8821c_1ant *coex_dm = &btc->coex_dm_8821c_1ant;
+	struct  btc_bt_link_info *bt_link_info = &btc->bt_link_info;
+	boolean	bt_busy = FALSE, increase_scan_dev_num = FALSE;
+	u32 val = 0;
+	static u8 pre_num_of_profile, cur_num_of_profile, cnt, ble_cnt;
+
+	if (++ble_cnt >= 3)
+		ble_cnt = 0;
+
+	if (coex_sta->is_ble_scan_en && ble_cnt == 0) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], BT ext info bit4 check, query BLE Scan type!!\n");
+		BTC_TRACE(trace_buf);
+		coex_sta->bt_ble_scan_type =
+				btc->btc_get_ble_scan_type_from_bt(btc);
+
+		if ((coex_sta->bt_ble_scan_type & 0x1) == 0x1)
+			coex_sta->bt_ble_scan_para[0]  =
+				btc->btc_get_ble_scan_para_from_bt(btc, 0x1);
+		if ((coex_sta->bt_ble_scan_type & 0x2) == 0x2)
+			coex_sta->bt_ble_scan_para[1]  =
+				btc->btc_get_ble_scan_para_from_bt(btc, 0x2);
+		if ((coex_sta->bt_ble_scan_type & 0x4) == 0x4)
+			coex_sta->bt_ble_scan_para[2]  =
+				btc->btc_get_ble_scan_para_from_bt(btc, 0x4);
+	}
+
+	coex_sta->num_of_profile = 0;
+
+	/* set link exist status */
+	if (!(coex_sta->bt_info & BT_INFO_8821C_1ANT_B_CONNECTION)) {
+		coex_sta->bt_link_exist = FALSE;
+		coex_sta->pan_exist = FALSE;
+		coex_sta->a2dp_exist = FALSE;
+		coex_sta->hid_exist = FALSE;
+		coex_sta->sco_exist = FALSE;
+		coex_sta->msft_mr_exist = FALSE;
+	} else {	/* connection exists */
+		coex_sta->bt_link_exist = TRUE;
+		if (coex_sta->bt_info & BT_INFO_8821C_1ANT_B_FTP) {
+			coex_sta->pan_exist = TRUE;
+			coex_sta->num_of_profile++;
+		} else
+			coex_sta->pan_exist = FALSE;
+
+		if (coex_sta->bt_info & BT_INFO_8821C_1ANT_B_A2DP) {
+			coex_sta->a2dp_exist = TRUE;
+			coex_sta->num_of_profile++;
+		} else
+			coex_sta->a2dp_exist = FALSE;
+
+		if (coex_sta->bt_info & BT_INFO_8821C_1ANT_B_HID) {
+			coex_sta->hid_exist = TRUE;
+			coex_sta->num_of_profile++;
+		} else
+			coex_sta->hid_exist = FALSE;
+
+		if (coex_sta->bt_info & BT_INFO_8821C_1ANT_B_SCO_ESCO) {
+			coex_sta->sco_exist = TRUE;
+			coex_sta->num_of_profile++;
+		} else
+			coex_sta->sco_exist = FALSE;
+
+		if (coex_sta->hid_busy_num == 0 &&
+		    coex_sta->hid_pair_cnt > 0 &&
+		    coex_sta->low_priority_tx > 1000 &&
+		    coex_sta->low_priority_rx > 1000 &&
+		    !coex_sta->c2h_bt_inquiry_page)
+			coex_sta->msft_mr_exist = true;
+		else
+			coex_sta->msft_mr_exist = false;
+	}
+
+	bt_link_info->bt_link_exist = coex_sta->bt_link_exist;
+	bt_link_info->sco_exist = coex_sta->sco_exist;
+	bt_link_info->a2dp_exist = coex_sta->a2dp_exist;
+	bt_link_info->pan_exist = coex_sta->pan_exist;
+	bt_link_info->hid_exist = coex_sta->hid_exist;
+	bt_link_info->acl_busy = coex_sta->acl_busy;
+
+	/* check if Sco only */
+	if (bt_link_info->sco_exist &&
+	    !bt_link_info->a2dp_exist &&
+	    !bt_link_info->pan_exist &&
+	    !bt_link_info->hid_exist)
+		bt_link_info->sco_only = TRUE;
+	else
+		bt_link_info->sco_only = FALSE;
+
+	/* check if A2dp only */
+	if (!bt_link_info->sco_exist &&
+	    bt_link_info->a2dp_exist &&
+	    !bt_link_info->pan_exist &&
+	    !bt_link_info->hid_exist)
+		bt_link_info->a2dp_only = TRUE;
+	else
+		bt_link_info->a2dp_only = FALSE;
+
+	/* check if Pan only */
+	if (!bt_link_info->sco_exist &&
+	    !bt_link_info->a2dp_exist &&
+	    bt_link_info->pan_exist &&
+	    !bt_link_info->hid_exist)
+		bt_link_info->pan_only = TRUE;
+	else
+		bt_link_info->pan_only = FALSE;
+
+	/* check if Hid only */
+	if (!bt_link_info->sco_exist &&
+	    !bt_link_info->a2dp_exist &&
+	    !bt_link_info->pan_exist &&
+	    bt_link_info->hid_exist)
+		bt_link_info->hid_only = TRUE;
+	else
+		bt_link_info->hid_only = FALSE;
+
+	if (coex_sta->bt_info & BT_INFO_8821C_1ANT_B_INQ_PAGE) {
+		coex_dm->bt_status = BT_8821C_1ANT_BSTATUS_INQ_PAGE;
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], BtInfoNotify(), BT Inq/page!!!\n");
+	} else if (!(coex_sta->bt_info & BT_INFO_8821C_1ANT_B_CONNECTION)) {
+		coex_dm->bt_status = BT_8821C_1ANT_BSTATUS_NCON_IDLE;
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], BtInfoNotify(), BT Non-Connected idle!!!\n");
+	} else if (coex_sta->bt_info == BT_INFO_8821C_1ANT_B_CONNECTION) {
+		/* connection exists but no busy */
+
+		if (coex_sta->msft_mr_exist) {
+			coex_dm->bt_status = BT_8821C_1ANT_BSTATUS_ACL_BUSY;
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				    "[BTCoex], BtInfoNotify(),  BT ACL busy!!\n");
+		} else {
+			coex_dm->bt_status = BT_8821C_1ANT_BSTATUS_CON_IDLE;
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				    "[BTCoex], BtInfoNotify(), BT Connected-idle!!!\n");
+		}
+	} else if (((coex_sta->bt_info & BT_INFO_8821C_1ANT_B_SCO_ESCO) ||
+		    (coex_sta->bt_info & BT_INFO_8821C_1ANT_B_SCO_BUSY)) &&
+		   (coex_sta->bt_info & BT_INFO_8821C_1ANT_B_ACL_BUSY)) {
+		coex_dm->bt_status = BT_8821C_1ANT_BSTATUS_ACL_SCO_BUSY;
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], BtInfoNotify(), BT ACL SCO busy!!!\n");
+	} else if ((coex_sta->bt_info & BT_INFO_8821C_1ANT_B_SCO_ESCO) ||
+		   (coex_sta->bt_info & BT_INFO_8821C_1ANT_B_SCO_BUSY)) {
+		coex_dm->bt_status = BT_8821C_1ANT_BSTATUS_SCO_BUSY;
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], BtInfoNotify(), BT SCO busy!!!\n");
+	} else if (coex_sta->bt_info & BT_INFO_8821C_1ANT_B_ACL_BUSY) {
+		coex_dm->bt_status = BT_8821C_1ANT_BSTATUS_ACL_BUSY;
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], BtInfoNotify(), BT ACL busy!!!\n");
+	} else {
+		coex_dm->bt_status = BT_8821C_1ANT_BSTATUS_MAX;
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			"[BTCoex], BtInfoNotify(), BT Non-Defined state!!!\n");
+	}
+
+	BTC_TRACE(trace_buf);
+
+	if (coex_dm->bt_status == BT_8821C_1ANT_BSTATUS_ACL_BUSY ||
+	    coex_dm->bt_status == BT_8821C_1ANT_BSTATUS_SCO_BUSY ||
+	    coex_dm->bt_status == BT_8821C_1ANT_BSTATUS_ACL_SCO_BUSY) {
+		bt_busy = TRUE;
+		increase_scan_dev_num = TRUE;
+	} else {
+		bt_busy = FALSE;
+		increase_scan_dev_num = FALSE;
+	}
+
+	btc->btc_set(btc, BTC_SET_BL_BT_TRAFFIC_BUSY, &bt_busy);
+	btc->btc_set(btc, BTC_SET_BL_INC_SCAN_DEV_NUM, &increase_scan_dev_num);
+
+	cur_num_of_profile = coex_sta->num_of_profile;
+
+	if (cur_num_of_profile != pre_num_of_profile)
+		cnt = 2;
+
+	if (bt_link_info->a2dp_exist && (cnt > 0)) {
+		cnt--;
+		if (coex_sta->bt_a2dp_vendor_id == 0 &&
+		    coex_sta->bt_a2dp_device_name == 0) {
+			btc->btc_get(btc, BTC_GET_U4_BT_DEVICE_INFO, &val);
+
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				    "[BTCoex], BtInfoNotify(), get BT DEVICE_INFO = %x\n",
+				    val);
+			BTC_TRACE(trace_buf);
+
+			coex_sta->bt_a2dp_vendor_id = (u8)(val & 0xff);
+			coex_sta->bt_a2dp_device_name = (val & 0xffffff00) >> 8;
+		}
+
+		if (coex_sta->legacy_forbidden_slot == 0 &&
+		    coex_sta->le_forbidden_slot == 0) {
+			btc->btc_get(btc, BTC_GET_U4_BT_FORBIDDEN_SLOT_VAL,
+				     &val);
+
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				    "[BTCoex], BtInfoNotify(), get BT FORBIDDEN_SLOT_VAL = %x\n",
+				    val);
+			BTC_TRACE(trace_buf);
+
+			coex_sta->legacy_forbidden_slot = (u16)(val & 0xffff);
+			coex_sta->le_forbidden_slot =
+						(u16)((val & 0xffff0000) >> 16);
+		}
+	}
+
+	pre_num_of_profile = coex_sta->num_of_profile;
+}
+
+static
+void halbtc8821c1ant_update_wifi_ch_info(struct btc_coexist *btc, u8 type)
+{
+	struct coex_sta_8821c_1ant *coex_sta = &btc->coex_sta_8821c_1ant;
+	struct coex_dm_8821c_1ant *coex_dm = &btc->coex_dm_8821c_1ant;
+	struct wifi_link_info_8821c_1ant *wifi_link_info_ext =
+					 &btc->wifi_link_info_8821c_1ant;
+	u8 h2c_parameter[3] = {0}, i;
+	u32 wifi_bw;
+	u8 wifi_central_chnl = 0;
+	u8 wifi_5g_chnl[19] = {120, 124, 128, 132, 136, 140, 144, 149, 153, 157,
+			       118, 126, 134, 142, 151, 159, 122, 138, 155};
+	u8 bt_skip_cneter_chanl[19] = {2, 8, 17, 26, 34, 42, 51, 62, 71, 77, 2,
+				       12, 29, 46, 66, 76, 10, 37, 68};
+	u8 bt_skip_span[19] = {4, 8, 8, 10, 8, 10, 8, 8, 10, 4, 4, 16, 16, 16,
+			       16, 4, 20, 34, 20};
+	boolean is_any_connected = FALSE;
+
+	if (btc->manual_control)
+		return;
+
+	btc->btc_get(btc, BTC_GET_U4_WIFI_BW, &wifi_bw);
+
+	if (btc->stop_coex_dm || coex_sta->is_rf_state_off) {
+		is_any_connected = FALSE;
+		wifi_central_chnl = 0;
+	} else if (type != BTC_MEDIA_DISCONNECT ||
+		  (type == BTC_MEDIA_DISCONNECT &&
+		  wifi_link_info_ext->num_of_active_port > 0)) {
+		if (wifi_link_info_ext->num_of_active_port == 1) {
+			if (wifi_link_info_ext->is_p2p_connected)
+				wifi_central_chnl =
+					btc->wifi_link_info
+						.p2p_center_channel;
+			else
+				wifi_central_chnl =
+					btc->wifi_link_info
+						.sta_center_channel;
+		} else { /* port > 2 */
+			if ((btc->wifi_link_info
+				     .p2p_center_channel > 14) &&
+			    (btc->wifi_link_info
+				     .sta_center_channel > 14))
+				wifi_central_chnl =
+					btc->wifi_link_info
+						.p2p_center_channel;
+			else if (btc->wifi_link_info
+					 .p2p_center_channel <= 14)
+				wifi_central_chnl =
+					btc->wifi_link_info
+						.p2p_center_channel;
+			else if (btc->wifi_link_info
+					 .sta_center_channel <= 14)
+				wifi_central_chnl =
+					btc->wifi_link_info
+						.sta_center_channel;
+		}
+	}
+
+	if (wifi_central_chnl > 0)
+		is_any_connected = TRUE;
+
+	if (is_any_connected) {
+		if (wifi_central_chnl <= 14) {
+			h2c_parameter[0] = 0x1;
+			h2c_parameter[1] = wifi_central_chnl;
+
+			if (wifi_bw == BTC_WIFI_BW_HT40)
+				h2c_parameter[2] = 0x36;
+			else
+				h2c_parameter[2] = 0x24;
+		} else {  /* for 5G  */
+			for (i = 0; i <= 18; i++) {
+				if (wifi_central_chnl == wifi_5g_chnl[i])
+					break;
+			}
+
+			if (i <= 18) {
+				h2c_parameter[0] = 0x3;
+				h2c_parameter[1] = bt_skip_cneter_chanl[i];
+				h2c_parameter[2] = bt_skip_span[i];
+			}
+		}
+	}
+
+	coex_dm->wifi_chnl_info[0] = h2c_parameter[0];
+	coex_dm->wifi_chnl_info[1] = h2c_parameter[1];
+	coex_dm->wifi_chnl_info[2] = h2c_parameter[2];
+
+	btc->btc_fill_h2c(btc, 0x66, 3, h2c_parameter);
+
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+		    "[BTCoex], para[0:2] = 0x%x 0x%x 0x%x\n",
+		    h2c_parameter[0], h2c_parameter[1], h2c_parameter[2]);
+	BTC_TRACE(trace_buf);
+}
+
+static
+u32 halbtc8821c1ant_read_indirect_reg(struct btc_coexist *btc, u16 reg_addr)
+{
+	u32 j = 0, delay_count = 0;
+
+	/* wait for ready bit before access 0x1700 */
+	while (1) {
+		if ((btc->btc_read_1byte(btc, 0x1703) & BIT(5)) == 0) {
+			delay_ms(10);
+			delay_count++;
+			if (delay_count >= 10) {
+				delay_count = 0;
+				break;
+			}
+		} else
+			break;
+	}
+
+	btc->btc_write_4byte(btc, 0x1700, 0x800F0000 | reg_addr);
+
+	return btc->btc_read_4byte(btc,
+					 0x1708);  /* get read data */
+}
+
+static
+void halbtc8821c1ant_write_indirect_reg(struct btc_coexist *btc, u16 reg_addr,
+					u32 bit_mask, u32 reg_value)
+{
+	u32 val, i = 0, j = 0, bitpos = 0, delay_count = 0;
+
+	if (bit_mask == 0x0)
+		return;
+
+	if (bit_mask == 0xffffffff) {
+		/* wait for ready bit before access 0x1700/0x1704 */
+		while (1) {
+			if ((btc->btc_read_1byte(btc, 0x1703) & BIT(5)) == 0) {
+				delay_ms(10);
+				delay_count++;
+				if (delay_count >= 10) {
+					delay_count = 0;
+					break;
+				}
+			} else
+				break;
+		}
+
+		/* put write data */
+		btc->btc_write_4byte(btc, 0x1704, reg_value);
+
+		btc->btc_write_4byte(btc, 0x1700, 0xc00F0000 | reg_addr);
+	} else {
+		for (i = 0; i <= 31; i++) {
+			if (((bit_mask >> i) & 0x1) == 0x1) {
+				bitpos = i;
+				break;
+			}
+		}
+
+		/* read back register value before write */
+		val = halbtc8821c1ant_read_indirect_reg(btc, reg_addr);
+		val = (val & (~bit_mask)) | (reg_value << bitpos);
+
+		/* wait for ready bit before access 0x1700/0x1704 */
+		while (1) {
+			if ((btc->btc_read_1byte(btc, 0x1703) & BIT(5)) == 0) {
+				delay_ms(10);
+				delay_count++;
+				if (delay_count >= 10) {
+					delay_count = 0;
+					break;
+				}
+			} else
+				break;
+		}
+
+		/* put write data */
+		btc->btc_write_4byte(btc, 0x1704, val);
+
+		btc->btc_write_4byte(btc, 0x1700, 0xc00F0000 | reg_addr);
+	}
+}
+
+static
+void halbtc8821c1ant_ltecoex_enable(struct btc_coexist *btc, boolean enable)
+{
+	u8 val;
+
+	/* 0x38[7] */
+	val = (enable) ? 1 : 0;
+	halbtc8821c1ant_write_indirect_reg(btc, 0x38, 0x80, val);
+}
+
+static
+void halbtc8821c1ant_ltecoex_table(struct btc_coexist *btc, u8 table_type,
+				   u16 table_content)
+{
+	u16 reg_addr = 0x0000;
+
+	switch (table_type) {
+	case BT_8821C_1ANT_CTT_WL_VS_LTE:
+		reg_addr = 0xa0;
+		break;
+	case BT_8821C_1ANT_CTT_BT_VS_LTE:
+		reg_addr = 0xa4;
+		break;
+	}
+
+	/* 0xa0[15:0] or 0xa4[15:0] */
+	if (reg_addr != 0x0000)
+		halbtc8821c1ant_write_indirect_reg(btc, reg_addr, 0xffff,
+						   table_content);
+}
+
+static
+void halbtc8821c1ant_coex_ctrl_owner(struct btc_coexist *btc,
+				     boolean wifi_control)
+{
+	u8 val;
+
+	/* 0x70[26] */
+	val = (wifi_control) ? 1 : 0;
+	btc->btc_write_1byte_bitmask(btc, 0x73, 0x4, val);
+}
+
+static
+void halbtc8821c1ant_set_gnt_bt(struct btc_coexist *btc, u8 control_block,
+				boolean sw_control,  u8 state)
+{
+	u32 val = 0, val_orig = 0;
+
+	if (!sw_control)
+		val = 0x0;
+	else if (state & 0x1)
+		val = 0x3;
+	else
+		val = 0x1;
+
+	val_orig = halbtc8821c1ant_read_indirect_reg(btc, 0x38);
+
+	switch (control_block) {
+	case BT_8821C_1ANT_GNT_BLOCK_RFC_BB:
+	default:
+		val = ((val << 14) | (val << 10)) | (val_orig & 0xffff33ff);
+		break;
+	case BT_8821C_1ANT_GNT_BLOCK_RFC:
+		val = (val << 14) | (val_orig & 0xffff3fff);
+		break;
+	case BT_8821C_1ANT_GNT_BLOCK_BB:
+		val = (val << 10) | (val_orig & 0xfffff3ff);
+		break;
+	}
+
+	halbtc8821c1ant_write_indirect_reg(btc, 0x38, 0xffffffff, val);
+}
+
+static
+void halbtc8821c1ant_set_gnt_wl(struct btc_coexist *btc, u8 control_block,
+				boolean sw_control, u8 state)
+{
+	u32 val = 0, val_orig = 0;
+
+	if (!sw_control)
+		val = 0x0;
+	else if (state & 0x1)
+		val = 0x3;
+	else
+		val = 0x1;
+
+	val_orig = halbtc8821c1ant_read_indirect_reg(btc, 0x38);
+
+	switch (control_block) {
+	case BT_8821C_1ANT_GNT_BLOCK_RFC_BB:
+	default:
+		val = ((val << 12) | (val << 8)) | (val_orig & 0xffffccff);
+		break;
+	case BT_8821C_1ANT_GNT_BLOCK_RFC:
+		val = (val << 12) | (val_orig & 0xffffcfff);
+		break;
+	case BT_8821C_1ANT_GNT_BLOCK_BB:
+		val = (val << 8) | (val_orig & 0xfffffcff);
+		break;
+	}
+
+	halbtc8821c1ant_write_indirect_reg(btc, 0x38, 0xffffffff, val);
+}
+
+#if 0
+static
+void halbtc8821c1ant_ltecoex_set_break_table(struct btc_coexist *btc,
+					     u8 table_type, u8 table_content)
+{
+	u16 reg_addr = 0x0000;
+
+	switch (table_type) {
+	case BT_8821C_1ANT_LBTT_WL_BREAK_LTE:
+		reg_addr = 0xa8;
+		break;
+	case BT_8821C_1ANT_LBTT_BT_BREAK_LTE:
+		reg_addr = 0xac;
+		break;
+	case BT_8821C_1ANT_LBTT_LTE_BREAK_WL:
+		reg_addr = 0xb0;
+		break;
+	case BT_8821C_1ANT_LBTT_LTE_BREAK_BT:
+		reg_addr = 0xb4;
+		break;
+	}
+
+	/* 0xa8[15:0] or 0xb4[15:0] */
+	if (reg_addr != 0x0000)
+		halbtc8821c1ant_write_indirect_reg(btc, reg_addr, 0xff,
+						   table_content);
+}
+#endif
+
+#if 0
+static
+void halbtc8821c1ant_set_wltoggle_coex_table(struct btc_coexist *btc,
+					     boolean force_exec, u8 interval,
+					     u8 val0x6c4_b0, u8 val0x6c4_b1,
+					     u8 val0x6c4_b2, u8 val0x6c4_b3)
+{
+	static u8 pre_h2c_parameter[6] = {0};
+	u8 cur_h2c_parameter[6] = {0};
+	u8 i, match_cnt = 0;
+
+	cur_h2c_parameter[0] = 0x7; /* op_code, 0x7= wlan toggle slot*/
+
+	cur_h2c_parameter[1] = interval;
+	cur_h2c_parameter[2] = val0x6c4_b0;
+	cur_h2c_parameter[3] = val0x6c4_b1;
+	cur_h2c_parameter[4] = val0x6c4_b2;
+	cur_h2c_parameter[5] = val0x6c4_b3;
+
+	if (!force_exec) {
+		for (i = 1; i <= 5; i++) {
+			if (cur_h2c_parameter[i] != pre_h2c_parameter[i])
+				break;
+
+			match_cnt++;
+		}
+
+		if (match_cnt == 5)
+			return;
+	}
+
+	for (i = 1; i <= 5; i++)
+		pre_h2c_parameter[i] = cur_h2c_parameter[i];
+
+	btc->btc_fill_h2c(btc, 0x69, 6, cur_h2c_parameter);
+}
+#endif
+
+static
+void halbtc8821c1ant_set_table(struct btc_coexist *btc, boolean force_exec,
+			       u32 val0x6c0, u32 val0x6c4, u32 val0x6c8,
+			       u8 val0x6cc)
+{
+	struct coex_dm_8821c_1ant *coex_dm = &btc->coex_dm_8821c_1ant;
+
+	if (!force_exec) {
+		if (val0x6c0 == coex_dm->cur_val0x6c0 &&
+		    val0x6c4 == coex_dm->cur_val0x6c4 &&
+		    val0x6c8 == coex_dm->cur_val0x6c8 &&
+		    val0x6cc == coex_dm->cur_val0x6cc)
+			return;
+	}
+
+	btc->btc_write_4byte(btc, 0x6c0, val0x6c0);
+	btc->btc_write_4byte(btc, 0x6c4, val0x6c4);
+	btc->btc_write_4byte(btc, 0x6c8, val0x6c8);
+	btc->btc_write_1byte(btc, 0x6cc, val0x6cc);
+
+	coex_dm->cur_val0x6c0 = val0x6c0;
+	coex_dm->cur_val0x6c4 = val0x6c4;
+	coex_dm->cur_val0x6c8 = val0x6c8;
+	coex_dm->cur_val0x6cc = val0x6cc;
+}
+
+static
+void halbtc8821c1ant_table(struct btc_coexist *btc, boolean force_exec, u8 type)
+{
+	struct coex_sta_8821c_1ant *coex_sta = &btc->coex_sta_8821c_1ant;
+	u32 break_table;
+	u8 select_table;
+
+	coex_sta->coex_table_type = type;
+
+	if (coex_sta->concurrent_rx_mode_on == TRUE) {
+		 /* set WL hi-pri can break BT */
+		break_table = 0xf0ffffff;
+		 /* set Tx response = Hi-Pri (ex: Transmitting ACK,BA,CTS) */
+		select_table = 0x1b;
+	} else {
+		break_table = 0xffffff;
+		select_table = 0x13;
+	}
+
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+		    "[BTCoex], ********** Table-%d **********\n",
+		    coex_sta->coex_table_type);
+	BTC_TRACE(trace_buf);
+
+	switch (type) {
+	case 0:
+		halbtc8821c1ant_set_table(btc, force_exec, 0x65555555,
+					  0x65555555, break_table,
+					  select_table);
+		break;
+	case 1:
+		halbtc8821c1ant_set_table(btc, force_exec, 0x65555555,
+					  0x5a5a5a5a, break_table,
+					  select_table);
+		break;
+	case 2:
+		halbtc8821c1ant_set_table(btc, force_exec, 0x65555555,
+					  0xaaaaaaaa, break_table,
+					  select_table);
+		break;
+	case 3: /* not use  */
+		halbtc8821c1ant_set_table(btc, force_exec, 0x65555555,
+					  0x5a5a5a5a, break_table,
+					  select_table);
+		break;
+	case 4:
+		halbtc8821c1ant_set_table(btc, force_exec, 0x65555555,
+					  0x5a5a5a5a, break_table,
+					  select_table);
+		break;
+	case 5:
+		halbtc8821c1ant_set_table(btc, force_exec, 0x6a5a5a5a,
+					  0x5a5a5a5a, break_table,
+					  select_table);
+		break;
+	case 6: /* not use  */
+		halbtc8821c1ant_set_table(btc, force_exec, 0x65555555,
+					  0x5a5a5a5a, break_table,
+					  select_table);
+		break;
+	case 7:
+		halbtc8821c1ant_set_table(btc, force_exec, 0x65555555,
+					  0xaaaa5aaa, break_table,
+					  select_table);
+		break;
+	case 8:
+		halbtc8821c1ant_set_table(btc, force_exec, 0x65555555,
+					  0x6aaa6aaa, break_table,
+					  select_table);
+		break;
+	case 9:
+		halbtc8821c1ant_set_table(btc, force_exec, 0x65555555,
+					  0xaaaaaaaa, break_table,
+					  select_table);
+		break;
+	case 10:
+		halbtc8821c1ant_set_table(btc, force_exec, 0xaa5555aa,
+					  0xaaaaaaaa, break_table,
+					  select_table);
+		break;
+	case 11:
+		halbtc8821c1ant_set_table(btc, force_exec, 0x65a55555,
+					  0x5aaa5a5a, break_table,
+					  select_table);
+		break;
+	case 12:
+		halbtc8821c1ant_set_table(btc, force_exec, 0x65555555,
+					  0x5aaa5a5a, break_table,
+					  select_table);
+		break;
+	case 13:
+		halbtc8821c1ant_set_table(btc, force_exec, 0xaa5555aa,
+					  0x5a5a5a5a, break_table,
+					  select_table);
+		break;
+	case 14:
+		halbtc8821c1ant_set_table(btc, force_exec, 0xaa5555aa,
+					  0x5a5a5a5a, break_table,
+					  select_table);
+		break;
+	case 15:
+		halbtc8821c1ant_set_table(btc, force_exec, 0xffffffff,
+					  0x5a5a5a5a, break_table,
+					  select_table);
+		break;
+	default:
+		break;
+	}
+}
+
+static
+void halbtc8821c1ant_ignore_wlan_act(struct btc_coexist *btc,
+				     boolean force_exec, boolean enable)
+{
+	struct coex_dm_8821c_1ant *coex_dm = &btc->coex_dm_8821c_1ant;
+	u8 h2c_parameter[1] = {0};
+
+	if (btc->manual_control || btc->stop_coex_dm)
+		return;
+
+	if (!force_exec) {
+		if (enable == coex_dm->cur_ignore_wlan_act)
+			return;
+	}
+
+	if (enable)
+		h2c_parameter[0] |= BIT(0); /* function enable */
+
+	btc->btc_fill_h2c(btc, 0x63, 1, h2c_parameter);
+
+	coex_dm->cur_ignore_wlan_act = enable;
+}
+
+static
+void halbtc8821c1ant_lps_rpwm(struct btc_coexist *btc, boolean force_exec,
+			      u8 lps_val, u8 rpwm_val)
+{
+	struct coex_dm_8821c_1ant *coex_dm = &btc->coex_dm_8821c_1ant;
+
+	if (!force_exec) {
+		if (lps_val == coex_dm->cur_lps &&
+		    rpwm_val == coex_dm->cur_rpwm)
+			return;
+	}
+
+	btc->btc_set(btc, BTC_SET_U1_LPS_VAL, &lps_val);
+	btc->btc_set(btc, BTC_SET_U1_RPWM_VAL, &rpwm_val);
+
+	coex_dm->cur_lps = lps_val;
+	coex_dm->cur_rpwm = rpwm_val;
+}
+
+static
+void halbtc8821c1ant_multiport_tdma(struct btc_coexist *btc, u8 multi_port_mode)
+{
+#if 0
+	struct btc_multi_port_tdma_info multiport_tdma_para;
+	static u8 pre_state = BTC_MULTI_PORT_TDMA_MODE_NONE;
+
+	if (multi_port_mode == pre_state)
+		return;
+
+	multiport_tdma_para.btc_multi_port_tdma_mode = multi_port_mode;
+
+	switch (multi_port_mode) {
+	case BTC_MULTI_PORT_TDMA_MODE_NONE:
+		multiport_tdma_para.start_time_from_bcn = 0;
+		multiport_tdma_para.bt_time = 0;
+		break;
+	case BTC_MULTI_PORT_TDMA_MODE_2G_SCC_GO:
+		multiport_tdma_para.start_time_from_bcn = 65;
+		multiport_tdma_para.bt_time = 35;
+		break;
+	case BTC_MULTI_PORT_TDMA_MODE_2G_P2P_GO:
+		multiport_tdma_para.start_time_from_bcn = 55;
+		multiport_tdma_para.bt_time = 45;
+		break;
+	}
+
+	btc->btc_set(btc, BTC_SET_WIFI_BT_COEX_MODE, &multiport_tdma_para);
+
+	pre_state = multi_port_mode;
+#endif
+}
+
+static
+void halbtc8821c1ant_tdma_check(struct btc_coexist *btc, boolean new_ps_state)
+{
+	u8 lps_mode = 0x0;
+	u8 h2c_parameter[5] = {0x8, 0, 0, 0, 0};
+
+	btc->btc_get(btc, BTC_GET_U1_LPS_MODE, &lps_mode);
+
+	if (lps_mode) {	/* already under LPS state */
+		if (new_ps_state) {
+			/* keep state under LPS, do nothing. */
+		} else {
+			/* will leave LPS state, turn off psTdma first */
+			btc->btc_fill_h2c(btc, 0x60, 5, h2c_parameter);
+		}
+	} else {					/* NO PS state */
+		if (new_ps_state) {
+			/* will enter LPS state, turn off psTdma first */
+			btc->btc_fill_h2c(btc, 0x60, 5, h2c_parameter);
+		} else {
+			/* keep state under NO PS state, do nothing. */
+		}
+	}
+}
+
+static
+boolean halbtc8821c1ant_power_save_state(struct btc_coexist *btc, u8 ps_type,
+					 u8 lps_val,  u8 rpwm_val)
+{
+	struct coex_sta_8821c_1ant *coex_sta = &btc->coex_sta_8821c_1ant;
+	boolean	low_pwr_disable = FALSE, result = TRUE;
+
+	switch (ps_type) {
+	case BTC_PS_WIFI_NATIVE:
+		/* recover to original 32k low power setting */
+		coex_sta->force_lps_ctrl = FALSE;
+		low_pwr_disable = FALSE;
+		/* btc->btc_set(btc, BTC_SET_ACT_DISABLE_LOW_POWER,
+		 * &low_pwr_disable);
+		 */
+		btc->btc_set(btc, BTC_SET_ACT_PRE_NORMAL_LPS, NULL);
+		break;
+	case BTC_PS_LPS_ON:
+		coex_sta->force_lps_ctrl = TRUE;
+		halbtc8821c1ant_tdma_check(btc, TRUE);
+		halbtc8821c1ant_lps_rpwm(btc, NM_EXCU, lps_val, rpwm_val);
+		/* when coex force to enter LPS, do not enter 32k low power. */
+		low_pwr_disable = TRUE;
+		btc->btc_set(btc, BTC_SET_ACT_DISABLE_LOW_POWER,
+			     &low_pwr_disable);
+		/* power save must executed before psTdma.*/
+		btc->btc_set(btc, BTC_SET_ACT_ENTER_LPS, NULL);
+		break;
+	case BTC_PS_LPS_OFF:
+		coex_sta->force_lps_ctrl = TRUE;
+		halbtc8821c1ant_tdma_check(btc, FALSE);
+		result = btc->btc_set(btc, BTC_SET_ACT_LEAVE_LPS, NULL);
+		break;
+	default:
+		break;
+	}
+
+	return result;
+}
+
+static
+void halbtc8821c1ant_set_tdma(struct btc_coexist *btc, u8 byte1, u8 byte2,
+			      u8 byte3, u8 byte4, u8 byte5)
+{
+	struct coex_sta_8821c_1ant *coex_sta = &btc->coex_sta_8821c_1ant;
+	struct coex_dm_8821c_1ant *coex_dm = &btc->coex_dm_8821c_1ant;
+	u8 h2c_parameter[5] = {0};
+	u8 real_byte1 = byte1, real_byte5 = byte5;
+	boolean	ap_enable = FALSE, result = FALSE;
+	struct  btc_bt_link_info *bt_link_info = &btc->bt_link_info;
+	u8 ps_type = BTC_PS_WIFI_NATIVE;
+
+	if (byte5 & BIT(2))
+		coex_sta->is_tdma_btautoslot = TRUE;
+	else
+		coex_sta->is_tdma_btautoslot = FALSE;
+
+	/* release bt-auto slot for auto-slot hang is detected!! */
+	if (coex_sta->is_tdma_btautoslot)
+		if (coex_sta->is_tdma_btautoslot_hang ||
+		    bt_link_info->slave_role)
+			byte5 = byte5 & 0xfb;
+
+#if 1
+	btc->btc_get(btc, BTC_GET_BL_WIFI_AP_MODE_ENABLE, &ap_enable);
+#else
+	if  (btc->wifi_link_info.link_mode == BTC_LINK_ONLY_GO &&
+	     btc->wifi_link_info.bhotspot &&
+	     btc->wifi_link_info.bany_client_join_go)
+		ap_enable = TRUE;
+#endif
+
+	if ((ap_enable) && (byte1 & BIT(4) && !(byte1 & BIT(5)))) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], %s == FW for 1Ant AP mode\n", __func__);
+		BTC_TRACE(trace_buf);
+		real_byte1 &= ~BIT(4);
+		real_byte1 |= BIT(5);
+
+		real_byte5 |= BIT(5);
+		real_byte5 &= ~BIT(6);
+
+		ps_type = BTC_PS_WIFI_NATIVE;
+		halbtc8821c1ant_power_save_state(btc, ps_type, 0x0, 0x0);
+	} else if (byte1 & BIT(4) && !(byte1 & BIT(5))) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], %s == Force LPS (byte1 = 0x%x)\n",
+			    __func__, byte1);
+		BTC_TRACE(trace_buf);
+
+		ps_type = BTC_PS_LPS_OFF;
+		if (!halbtc8821c1ant_power_save_state(btc, ps_type, 0x50, 0x4))
+			result = TRUE;
+	} else {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], %s == native power save (byte1 = 0x%x)\n",
+			    __func__, byte1);
+		BTC_TRACE(trace_buf);
+
+		ps_type = BTC_PS_WIFI_NATIVE;
+		halbtc8821c1ant_power_save_state(btc, ps_type, 0x0, 0x0);
+	}
+
+	coex_sta->is_set_ps_state_fail = result;
+
+	if (!coex_sta->is_set_ps_state_fail) {
+		h2c_parameter[0] = real_byte1;
+		h2c_parameter[1] = byte2;
+		h2c_parameter[2] = byte3;
+		h2c_parameter[3] = byte4;
+		h2c_parameter[4] = real_byte5;
+
+		coex_dm->ps_tdma_para[0] = real_byte1;
+		coex_dm->ps_tdma_para[1] = byte2;
+		coex_dm->ps_tdma_para[2] = byte3;
+		coex_dm->ps_tdma_para[3] = byte4;
+		coex_dm->ps_tdma_para[4] = real_byte5;
+
+		btc->btc_fill_h2c(btc, 0x60, 5, h2c_parameter);
+	} else {
+		coex_sta->cnt_set_ps_state_fail++;
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], %s == Force Leave LPS Fail (cnt = %d)\n",
+			    __func__, coex_sta->cnt_set_ps_state_fail);
+		BTC_TRACE(trace_buf);
+	}
+
+	if (ps_type == BTC_PS_WIFI_NATIVE)
+		btc->btc_set(btc, BTC_SET_ACT_POST_NORMAL_LPS, NULL);
+}
+
+static
+void halbtc8821c1ant_tdma(struct btc_coexist *btc, boolean force_exec,
+			  boolean turn_on, u8 type)
+{
+	struct coex_sta_8821c_1ant *coex_sta = &btc->coex_sta_8821c_1ant;
+	struct coex_dm_8821c_1ant *coex_dm = &btc->coex_dm_8821c_1ant;
+	struct btc_bt_link_info *bt_link_info = &btc->bt_link_info;
+	struct btc_board_info	*board_info = &btc->board_info;
+	boolean	wifi_busy = FALSE;
+	static u8 tdma_byte4_modify, pre_tdma_byte4_modify;
+	static boolean pre_wifi_busy;
+	u8 multiport_pstdma = BTC_MULTI_PORT_TDMA_MODE_NONE;
+
+	btc->btc_set_atomic(btc, &coex_dm->setting_tdma, TRUE);
+
+	btc->btc_get(btc, BTC_GET_BL_WIFI_BUSY, &wifi_busy);
+
+	if (wifi_busy != pre_wifi_busy) {
+		force_exec = TRUE;
+		pre_wifi_busy = wifi_busy;
+	}
+
+	/* 0x778 = 0x1 at wifi slot (no blocking BT Low-Pri pkts) */
+	if ((bt_link_info->slave_role) && (bt_link_info->a2dp_exist))
+		tdma_byte4_modify = 0x1;
+	else
+		tdma_byte4_modify = 0x0;
+
+	if (pre_tdma_byte4_modify != tdma_byte4_modify) {
+		force_exec = TRUE;
+		pre_tdma_byte4_modify = tdma_byte4_modify;
+	}
+
+	if (!force_exec) {
+		if (turn_on == coex_dm->cur_ps_tdma_on &&
+		    type == coex_dm->cur_ps_tdma) {
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				    "[BTCoex], Skip TDMA because no change TDMA(%s, %d)\n",
+				    (coex_dm->cur_ps_tdma_on ? "on" : "off"),
+				    coex_dm->cur_ps_tdma);
+			BTC_TRACE(trace_buf);
+
+			btc->btc_set_atomic(btc, &coex_dm->setting_tdma, FALSE);
+			return;
+		}
+	}
+
+	if (turn_on) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], ********** TDMA(on, %d) **********\n",
+			    type);
+		BTC_TRACE(trace_buf);
+
+		/* enable TBTT nterrupt */
+		btc->btc_write_1byte_bitmask(btc, 0x550, 0x8, 0x1);
+
+		switch (type) {
+		default:
+			halbtc8821c1ant_set_tdma(btc, 0x61, 0x35, 0x03, 0x11,
+						 0x11);
+			break;
+		case 3:
+			halbtc8821c1ant_set_tdma(btc, 0x51, 0x30, 0x03, 0x10,
+						 0x50);
+			break;
+		case 4:
+			halbtc8821c1ant_set_tdma(btc, 0x51, 0x21, 0x03, 0x10,
+						 0x50);
+			break;
+		case 5:
+			halbtc8821c1ant_set_tdma(btc, 0x61, 0x3a, 0x03, 0x11,
+						 0x11);
+			break;
+		case 6:
+			halbtc8821c1ant_set_tdma(btc, 0x61, 0x20, 0x03, 0x11,
+						 0x11);
+			break;
+		case 7:
+			halbtc8821c1ant_set_tdma(btc, 0x51, 0x08, 0x03, 0x10,
+						 0x54 | tdma_byte4_modify);
+			break;
+		case 8:
+			halbtc8821c1ant_set_tdma(btc, 0x51, 0x08, 0x03, 0x10,
+						 0x54 | tdma_byte4_modify);
+			break;
+		case 9: /* not use */
+			halbtc8821c1ant_set_tdma(btc, 0x51, 0x10, 0x03, 0x10,
+						 0x54 | tdma_byte4_modify);
+			break;
+		case 10:
+			halbtc8821c1ant_set_tdma(btc, 0x51, 0x08, 0x07, 0x10,
+						 0x55);
+			break;
+		case 11:
+			halbtc8821c1ant_set_tdma(btc, 0x61, 0x25, 0x03, 0x11,
+						 0x11);
+			break;
+		case 12:
+			halbtc8821c1ant_set_tdma(btc, 0x51, 0x35, 0x03, 0x10,
+						 0x50 | tdma_byte4_modify);
+			break;
+		case 13:
+			halbtc8821c1ant_set_tdma(btc, 0x51, 0x08, 0x07, 0x10,
+						 0x54 | tdma_byte4_modify);
+			break;
+		case 14:
+			halbtc8821c1ant_set_tdma(btc, 0x51, 0x15, 0x03, 0x10,
+						 0x50 | tdma_byte4_modify);
+			break;
+		case 15: /* not use */
+			halbtc8821c1ant_set_tdma(btc, 0x51, 0x20, 0x03, 0x10,
+						 0x50 | tdma_byte4_modify);
+			break;
+		case 16: /* not use */
+			halbtc8821c1ant_set_tdma(btc, 0x61, 0x10, 0x03, 0x11,
+						 0x11 | tdma_byte4_modify);
+			break;
+		case 17:
+			halbtc8821c1ant_set_tdma(btc, 0x61, 0x08, 0x03, 0x11,
+						 0x14 | tdma_byte4_modify);
+			break;
+		case 18:
+			halbtc8821c1ant_set_tdma(btc, 0x51, 0x30, 0x03, 0x10,
+						 0x50 | tdma_byte4_modify);
+			break;
+		case 19: /* not use */
+			halbtc8821c1ant_set_tdma(btc, 0x61, 0x15, 0x03, 0x11,
+						 0x10);
+			break;
+		case 20: /* not use */
+			halbtc8821c1ant_set_tdma(btc, 0x61, 0x30, 0x03, 0x11,
+						 0x10);
+			break;
+		case 21:
+			halbtc8821c1ant_set_tdma(btc, 0x61, 0x30, 0x03, 0x11,
+						 0x10);
+			break;
+		case 22:
+			halbtc8821c1ant_set_tdma(btc, 0x61, 0x25, 0x03, 0x11,
+						 0x10);
+			break;
+		case 23:
+			halbtc8821c1ant_set_tdma(btc, 0x61, 0x10, 0x03, 0x11,
+						 0x10);
+			break;
+		case 24:
+			halbtc8821c1ant_set_tdma(btc, 0x51, 0x08, 0x03, 0x10,
+						 0x54 | tdma_byte4_modify);
+			break;
+		case 25:
+			halbtc8821c1ant_set_tdma(btc, 0x51, 0x3a, 0x03, 0x11,
+						 0x50);
+			break;
+		case 26:
+			halbtc8821c1ant_set_tdma(btc, 0x51, 0x08, 0x03, 0x10,
+						 0x55);
+			break;
+		case 27:
+			halbtc8821c1ant_set_tdma(btc, 0x61, 0x08, 0x03, 0x11,
+						 0x15);
+			break;
+		case 28:
+			halbtc8821c1ant_set_tdma(btc, 0x51, 0x08, 0x0b, 0x10,
+						 0x54);
+			break;
+		case 32:
+			halbtc8821c1ant_set_tdma(btc, 0x61, 0x35, 0x03, 0x11,
+						 0x11);
+			break;
+		case 33:
+			halbtc8821c1ant_set_tdma(btc, 0x61, 0x35, 0x03, 0x11,
+						 0x10);
+			break;
+		case 36:
+			halbtc8821c1ant_set_tdma(btc, 0x61, 0x50, 0x03, 0x11,
+						 0x10);
+			break;
+		case 37:
+			halbtc8821c1ant_set_tdma(btc, 0x61, 0x3c, 0x03, 0x11,
+						 0x10);
+			break;
+		case 201:
+			multiport_pstdma = BTC_MULTI_PORT_TDMA_MODE_2G_SCC_GO;
+			halbtc8821c1ant_set_tdma(btc, 0x51, 0x3f, 0x3, 0x10,
+						 0x50);
+			break;
+		case 202:
+			multiport_pstdma = BTC_MULTI_PORT_TDMA_MODE_2G_P2P_GO;
+			halbtc8821c1ant_set_tdma(btc, 0x51, 0x35, 0x3, 0x10,
+						 0x50);
+			break;
+		}
+	} else {
+
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], ********** TDMA(off, %d) **********\n",
+			    type);
+		BTC_TRACE(trace_buf);
+
+		/* disable PS tdma */
+		switch (type) {
+		case 8: /* PTA Control */
+			halbtc8821c1ant_set_tdma(btc, 0x8, 0x0, 0x0, 0x0, 0x0);
+			break;
+		case 0:
+		default:  /* Software control, Antenna at BT side */
+			halbtc8821c1ant_set_tdma(btc, 0x0, 0x0, 0x0, 0x0, 0x0);
+			break;
+		case 1: /* 2-Ant, 0x778=3, antenna control
+			 * by antenna diversity
+			 */
+			halbtc8821c1ant_set_tdma(btc, 0x0, 0x0, 0x0, 0x48, 0x0);
+			break;
+		}
+	}
+
+	halbtc8821c1ant_multiport_tdma(btc, multiport_pstdma);
+
+	if (!coex_sta->is_set_ps_state_fail) {
+		/* update pre state */
+		coex_dm->cur_ps_tdma_on = turn_on;
+		coex_dm->cur_ps_tdma = type;
+	}
+
+	btc->btc_set_atomic(btc, &coex_dm->setting_tdma, FALSE);
+}
+
+static
+void halbtc8821c1ant_set_ant_switch(struct btc_coexist *btc,
+				    boolean force_exec, u8 ctrl_type,
+				    u8 pos_type)
+{
+	struct coex_dm_8821c_1ant *coex_dm = &btc->coex_dm_8821c_1ant;
+	struct rfe_type_8821c_1ant *rfe_type = &btc->rfe_type_8821c_1ant;
+	struct  btc_board_info	*board_info = &btc->board_info;
+	boolean	polarity_inverse = FALSE;
+	u8 regval = 0;
+	u32 u32tmp1 = 0, u32tmp2 = 0, u32tmp3 = 0;
+
+	if (!rfe_type->ext_ant_switch_exist)
+		return;
+
+	if (!force_exec) {
+		if (((ctrl_type << 8) + pos_type) ==
+				coex_dm->cur_ext_ant_switch_status)
+			return;
+	}
+
+	coex_dm->cur_ext_ant_switch_status = (ctrl_type << 8)  + pos_type;
+
+	/* swap control polarity if use different switch control polarity
+	 * Normal switch polarity for DPDT,
+	 * 0xcb4[29:28] = 2b'01 => BTG to Main, WLG to Aux,
+	 * 0xcb4[29:28] = 2b'10 => BTG to Aux, WLG to Main
+	 * Normal switch polarity for SPDT,
+	 * 0xcb4[29:28] = 2b'01 => Ant to BTG,
+	 * 0xcb4[29:28] = 2b'10 => Ant to WLG
+	 */
+	if (rfe_type->ext_ant_switch_ctrl_polarity)
+		polarity_inverse =  !polarity_inverse;
+
+	/* swap control polarity if 1-Ant at Aux */
+	if (rfe_type->ant_at_main_port == FALSE)
+		polarity_inverse =  !polarity_inverse;
+
+	switch (pos_type) {
+	default:
+	case BT_8821C_1ANT_TO_BT:
+	case BT_8821C_1ANT_TO_NOCARE:
+	case BT_8821C_1ANT_TO_WLA:
+
+		break;
+	case BT_8821C_1ANT_TO_WLG:
+		if (!rfe_type->wlg_locate_at_btg)
+			polarity_inverse =  !polarity_inverse;
+		break;
+	}
+
+	if (board_info->ant_div_cfg)
+		ctrl_type = BT_8821C_1ANT_CTRL_BY_ANTDIV;
+
+
+	switch (ctrl_type) {
+	default:
+	case BT_8821C_1ANT_CTRL_BY_BBSW:
+		/*  0x4c[23] = 0 */
+		btc->btc_write_1byte_bitmask(btc, 0x4e, 0x80, 0x0);
+		/* 0x4c[24] = 1 */
+		btc->btc_write_1byte_bitmask(btc, 0x4f, 0x01, 0x1);
+		/* BB SW, DPDT use RFE_ctrl8 and RFE_ctrl9 as control pin */
+		btc->btc_write_1byte_bitmask(btc, 0xcb4, 0xff, 0x77);
+		/* 0xcb4[29:28] = 2b'01 for no switch_polarity_inverse,
+		 * DPDT_SEL_N =1, DPDT_SEL_P =0
+		 */
+		regval = (!polarity_inverse ? 0x1 : 0x2);
+		btc->btc_write_1byte_bitmask(btc, 0xcb7, 0x30, regval);
+		break;
+	case BT_8821C_1ANT_CTRL_BY_PTA:
+		/* 0x4c[23] = 0 */
+		btc->btc_write_1byte_bitmask(btc, 0x4e, 0x80, 0x0);
+		/* 0x4c[24] = 1 */
+		btc->btc_write_1byte_bitmask(btc, 0x4f, 0x01, 0x1);
+		/* PTA,  DPDT use RFE_ctrl8 and RFE_ctrl9 as control pin */
+		btc->btc_write_1byte_bitmask(btc, 0xcb4, 0xff, 0x66);
+		/* 0xcb4[29:28] = 2b'10 for no switch_polatiry_inverse,
+		 * DPDT_SEL_N =1, DPDT_SEL_P =0  @ GNT_BT=1
+		 */
+		regval = (!polarity_inverse ? 0x2 : 0x1);
+		btc->btc_write_1byte_bitmask(btc, 0xcb7, 0x30, regval);
+		break;
+	case BT_8821C_1ANT_CTRL_BY_ANTDIV:
+		/* 0x4c[23] = 0 */
+		btc->btc_write_1byte_bitmask(btc, 0x4e, 0x80, 0x0);
+		/* 0x4c[24] = 1 */
+		btc->btc_write_1byte_bitmask(btc, 0x4f, 0x01, 0x1);
+		btc->btc_write_1byte_bitmask(btc, 0xcb4, 0xff, 0x88);
+
+		/* no regval_0xcb7 setup required, because antenna switch
+		 *  control value by antenna diversity
+		 */
+		break;
+	case BT_8821C_1ANT_CTRL_BY_MAC:
+		/*  0x4c[23] = 1 */
+		btc->btc_write_1byte_bitmask(btc, 0x4e, 0x80, 0x1);
+		/* 0x64[0] = 1b'0 for no switch_polarity_inverse,
+		 * DPDT_SEL_N =1, DPDT_SEL_P =0
+		 */
+		regval = (!polarity_inverse ?  0x0 : 0x1);
+		btc->btc_write_1byte_bitmask(btc, 0x64, 0x1, regval);
+		break;
+	case BT_8821C_1ANT_CTRL_BY_FW:
+		/* 0x4c[23] = 0 */
+		btc->btc_write_1byte_bitmask(btc, 0x4e, 0x80, 0x0);
+		/* 0x4c[24] = 1 */
+		btc->btc_write_1byte_bitmask(btc, 0x4f, 0x01, 0x1);
+		break;
+	case BT_8821C_1ANT_CTRL_BY_BT:
+		/* 0x4c[23] = 0 */
+		btc->btc_write_1byte_bitmask(btc, 0x4e, 0x80, 0x0);
+		/* 0x4c[24] = 0 */
+		btc->btc_write_1byte_bitmask(btc, 0x4f, 0x01, 0x0);
+		/* no  setup required, because  antenna switch control value
+		 * by BT vendor 0xac[1:0]
+		 */
+		break;
+	}
+
+	/* PAPE, LNA_ON control by BT  while WLAN off for current leakage issue */
+	if (ctrl_type == BT_8821C_1ANT_CTRL_BY_BT) {
+		/* PAPE   0x64[29] = 0 */
+		btc->btc_write_1byte_bitmask(btc, 0x67, 0x20, 0x0);
+		/* LNA_ON 0x64[28] = 0 */
+		btc->btc_write_1byte_bitmask(btc, 0x67, 0x10, 0x0);
+	} else {
+		/* PAPE   0x64[29] = 1 */
+		btc->btc_write_1byte_bitmask(btc, 0x67, 0x20, 0x1);
+		/* LNA_ON 0x64[28] = 1 */
+		btc->btc_write_1byte_bitmask(btc, 0x67, 0x10, 0x1);
+	}
+}
+
+static
+void halbtc8821c1ant_set_rfe_type(struct btc_coexist *btc)
+{
+	struct btc_board_info *board_info = &btc->board_info;
+	struct rfe_type_8821c_1ant *rfe_type = &btc->rfe_type_8821c_1ant;
+
+	/* the following setup should be got from Efuse in the future */
+	rfe_type->rfe_module_type = board_info->rfe_type & 0x1f;
+
+	rfe_type->ext_ant_switch_ctrl_polarity = 0;
+
+	switch (rfe_type->rfe_module_type) {
+	case 0:
+	case 8:
+	default: /*2-Ant, DPDT, WLG*/
+		rfe_type->ext_ant_switch_exist = TRUE;
+		rfe_type->ext_ant_switch_type = BT_8821C_1ANT_USE_DPDT;
+		rfe_type->wlg_locate_at_btg = FALSE;
+		rfe_type->ant_at_main_port = TRUE;
+		break;
+	case 1:
+	case 9:  /*1-Ant, Main, WLG */
+		rfe_type->ext_ant_switch_exist = TRUE;
+		rfe_type->ext_ant_switch_type = BT_8821C_1ANT_USE_SPDT;
+		rfe_type->wlg_locate_at_btg = FALSE;
+		rfe_type->ant_at_main_port = TRUE;
+		break;
+	case 2:
+	case 10:  /*1-Ant, Main, BTG */
+		rfe_type->ext_ant_switch_exist = TRUE;
+		rfe_type->ext_ant_switch_type = BT_8821C_1ANT_USE_SPDT;
+		rfe_type->wlg_locate_at_btg = TRUE;
+		rfe_type->ant_at_main_port = TRUE;
+		break;
+	case 3:
+	case 11: /*1-Ant, Aux, WLG */
+		rfe_type->ext_ant_switch_exist = TRUE;
+		rfe_type->ext_ant_switch_type = BT_8821C_1ANT_USE_DPDT;
+		rfe_type->wlg_locate_at_btg = FALSE;
+		rfe_type->ant_at_main_port = FALSE;
+		break;
+	case 4:
+	case 12: /*1-Ant, Aux, BTG */
+		rfe_type->ext_ant_switch_exist = TRUE;
+		rfe_type->ext_ant_switch_type = BT_8821C_1ANT_USE_DPDT;
+		rfe_type->wlg_locate_at_btg = TRUE;
+		rfe_type->ant_at_main_port = FALSE;
+		break;
+	case 5:
+	case 13: /*2-Ant, no switch, WLG*/
+		rfe_type->ext_ant_switch_exist = FALSE;
+		rfe_type->ext_ant_switch_type = BT_8821C_1ANT_SWITCH_NONE;
+		rfe_type->wlg_locate_at_btg = FALSE;
+		rfe_type->ant_at_main_port = TRUE;
+		break;
+	case 6:
+	case 14: /*2-Ant, no antenna switch, WLG*/
+		rfe_type->ext_ant_switch_exist = FALSE;
+		rfe_type->ext_ant_switch_type = BT_8821C_1ANT_SWITCH_NONE;
+		rfe_type->wlg_locate_at_btg = FALSE;
+		rfe_type->ant_at_main_port = TRUE;
+		break;
+	case 7:
+	case 15: /*2-Ant, DPDT, BTG*/
+		rfe_type->ext_ant_switch_exist = TRUE;
+		rfe_type->ext_ant_switch_type = BT_8821C_1ANT_USE_DPDT;
+		rfe_type->wlg_locate_at_btg = TRUE;
+		rfe_type->ant_at_main_port = TRUE;
+		break;
+	}
+}
+
+static
+void halbtc8821c1ant_set_ant_path(struct btc_coexist *btc,
+				  u8 ant_pos_type, boolean force_exec,
+				  u8 phase)
+{
+	struct coex_sta_8821c_1ant *coex_sta = &btc->coex_sta_8821c_1ant;
+	struct coex_dm_8821c_1ant *coex_dm = &btc->coex_dm_8821c_1ant;
+	struct rfe_type_8821c_1ant *rfe_type = &btc->rfe_type_8821c_1ant;
+	u32 cnt_bt_cal_chk = 0, u32tmp1 = 0, u32tmp2 = 0;
+	u8 u8tmp = 0, ctrl_type, pos_type;
+
+	if (!force_exec) {
+		if (coex_dm->cur_ant_pos_type == ((ant_pos_type << 8)  + phase))
+			return;
+	}
+
+	coex_dm->cur_ant_pos_type = (ant_pos_type << 8)  + phase;
+
+	if (btc->dbg_mode) {
+		u32tmp1 = btc->btc_read_4byte(btc, 0xcbc);
+		u32tmp2 = btc->btc_read_4byte(btc, 0xcb4);
+		u8tmp  = btc->btc_read_1byte(btc, 0x73);
+
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], (Before Ant Setup) 0xcb4 = 0x%x, 0xcbc = 0x%x, 0x73 = 0x%x\n",
+			    u32tmp1, u32tmp2, u8tmp);
+		BTC_TRACE(trace_buf);
+	}
+
+	switch (phase) {
+	case BT_8821C_1ANT_PHASE_POWERON:
+
+		/* set Path control owner to BT at power-on step */
+		halbtc8821c1ant_coex_ctrl_owner(btc, BT_8821C_1ANT_PCO_BTSIDE);
+
+		if (ant_pos_type == BTC_ANT_PATH_AUTO)
+			ant_pos_type = BTC_ANT_PATH_BT;
+
+		coex_sta->run_time_state = FALSE;
+		break;
+	case BT_8821C_1ANT_PHASE_INIT:
+		/* Disable LTE Coex Function in WiFi side (
+		 * this should be on if LTE coex is required)
+		 */
+		halbtc8821c1ant_ltecoex_enable(btc, 0x0);
+
+		/* GNT_WL_LTE always = 1
+		 * (this should be config if LTE coex is required)
+		 */
+		halbtc8821c1ant_ltecoex_table(btc, BT_8821C_1ANT_CTT_WL_VS_LTE,
+					      0xffff);
+
+		/* GNT_BT_LTE always = 1
+		 * (this should be config if LTE coex is required)
+		 */
+		halbtc8821c1ant_ltecoex_table(btc, BT_8821C_1ANT_CTT_BT_VS_LTE,
+					      0xffff);
+
+		/* Wait If BT IQK running, because Path control owner is at
+		 * BT during BT IQK (setup by WiFi firmware)
+		 */
+		while (cnt_bt_cal_chk <= 20) {
+			u8tmp = btc->btc_read_1byte(btc, 0x49c);
+			cnt_bt_cal_chk++;
+			if (u8tmp & BIT(1)) {
+				BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+					    "[BTCoex], ########### BT is calibrating (wait cnt=%d) ###########\n",
+					    cnt_bt_cal_chk);
+				BTC_TRACE(trace_buf);
+				delay_ms(10);
+			} else {
+				BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+					    "[BTCoex], ********** BT is NOT calibrating (wait cnt=%d)**********\n",
+					    cnt_bt_cal_chk);
+				BTC_TRACE(trace_buf);
+				break;
+			}
+		}
+
+		/* set Path control owner to WL at initial step */
+		halbtc8821c1ant_coex_ctrl_owner(btc, BT_8821C_1ANT_PCO_WLSIDE);
+
+		/* set GNT_BT to SW high */
+		halbtc8821c1ant_set_gnt_bt(btc,
+					   BT_8821C_1ANT_GNT_BLOCK_RFC_BB,
+					   BT_8821C_1ANT_GNT_TYPE_CTRL_BY_SW,
+					   BT_8821C_1ANT_GNT_SET_TO_HIGH);
+		/* Set GNT_WL to SW low */
+		halbtc8821c1ant_set_gnt_wl(btc,
+					   BT_8821C_1ANT_GNT_BLOCK_RFC_BB,
+					   BT_8821C_1ANT_GNT_TYPE_CTRL_BY_SW,
+					   BT_8821C_1ANT_GNT_SET_TO_LOW);
+
+		coex_sta->run_time_state = FALSE;
+
+		if (ant_pos_type == BTC_ANT_PATH_AUTO)
+			ant_pos_type = BTC_ANT_PATH_BT;
+		break;
+	case BT_8821C_1ANT_PHASE_WONLY:
+		/* Disable LTE Coex Function in WiFi side
+		 *(this should be on if LTE coex is required)
+		 */
+		halbtc8821c1ant_ltecoex_enable(btc, 0x0);
+
+		/* GNT_WL_LTE always = 1
+		 *(this should be config if LTE coex is required)
+		 */
+		halbtc8821c1ant_ltecoex_table(btc, BT_8821C_1ANT_CTT_WL_VS_LTE,
+					      0xffff);
+
+		/* GNT_BT_LTE always = 1
+		 *(this should be config if LTE coex is required)
+		 */
+		halbtc8821c1ant_ltecoex_table(btc, BT_8821C_1ANT_CTT_BT_VS_LTE,
+					      0xffff);
+
+		/* set Path control owner to WL at initial step */
+		halbtc8821c1ant_coex_ctrl_owner(btc, BT_8821C_1ANT_PCO_WLSIDE);
+
+		/* set GNT_BT to SW Low */
+		halbtc8821c1ant_set_gnt_bt(btc, BT_8821C_1ANT_GNT_BLOCK_RFC_BB,
+					   BT_8821C_1ANT_GNT_TYPE_CTRL_BY_SW,
+					   BT_8821C_1ANT_GNT_SET_TO_LOW);
+		/* Set GNT_WL to SW high */
+		halbtc8821c1ant_set_gnt_wl(btc, BT_8821C_1ANT_GNT_BLOCK_RFC_BB,
+					   BT_8821C_1ANT_GNT_TYPE_CTRL_BY_SW,
+					   BT_8821C_1ANT_GNT_SET_TO_HIGH);
+
+		coex_sta->run_time_state = FALSE;
+
+		if (ant_pos_type == BTC_ANT_PATH_AUTO)
+			ant_pos_type = BTC_ANT_PATH_WIFI;
+		break;
+	case BT_8821C_1ANT_PHASE_WOFF:
+		/* Disable LTE Coex Function in WiFi side */
+		halbtc8821c1ant_ltecoex_enable(btc, 0x0);
+
+		/* set Path control owner to BT */
+		halbtc8821c1ant_coex_ctrl_owner(btc,
+						BT_8821C_1ANT_PCO_BTSIDE);
+
+		coex_sta->run_time_state = FALSE;
+		break;
+	case BT_8821C_1ANT_PHASE_2G:
+		while (cnt_bt_cal_chk <= 20) {
+			/* 0x49c[0]=1 WL IQK, 0x49c[1]=1 BT IQK*/
+			u8tmp = btc->btc_read_1byte(btc, 0x49c);
+
+			cnt_bt_cal_chk++;
+			if (u8tmp & BIT(0)) {
+				BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+					    "[BTCoex], ########### WL is IQK (wait cnt=%d)\n",
+					    cnt_bt_cal_chk);
+				BTC_TRACE(trace_buf);
+				delay_ms(10);
+			} else if (u8tmp & BIT(1)) {
+				BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+					    "[BTCoex], ########### BT is IQK (wait cnt=%d)\n",
+					    cnt_bt_cal_chk);
+				BTC_TRACE(trace_buf);
+				delay_ms(10);
+			} else {
+				BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+					    "[BTCoex], ********** WL and BT is NOT IQK (wait cnt=%d)\n",
+					    cnt_bt_cal_chk);
+				BTC_TRACE(trace_buf);
+				break;
+			}
+		}
+
+		/* set Path control owner to WL at runtime step */
+		halbtc8821c1ant_coex_ctrl_owner(btc, BT_8821C_1ANT_PCO_WLSIDE);
+
+		/* set GNT_BT to PTA */
+		halbtc8821c1ant_set_gnt_bt(btc, BT_8821C_1ANT_GNT_BLOCK_RFC_BB,
+					   BT_8821C_1ANT_GNT_TYPE_CTRL_BY_PTA,
+					   BT_8821C_1ANT_GNT_SET_BY_HW);
+
+		halbtc8821c1ant_set_gnt_wl(btc, BT_8821C_1ANT_GNT_BLOCK_RFC_BB,
+					   BT_8821C_1ANT_GNT_TYPE_CTRL_BY_PTA,
+					   BT_8821C_1ANT_GNT_SET_BY_HW);
+
+		coex_sta->run_time_state = TRUE;
+
+		if (ant_pos_type == BTC_ANT_PATH_AUTO) {
+			if (rfe_type->wlg_locate_at_btg)
+				ant_pos_type = BTC_ANT_PATH_WIFI;
+			else
+				ant_pos_type = BTC_ANT_PATH_PTA;
+		}
+		break;
+	case BT_8821C_1ANT_PHASE_5G:
+
+		/* set Path control owner to WL at runtime step */
+		halbtc8821c1ant_coex_ctrl_owner(btc, BT_8821C_1ANT_PCO_WLSIDE);
+
+		/* set GNT_BT to SW Hi */
+		halbtc8821c1ant_set_gnt_bt(btc, BT_8821C_1ANT_GNT_BLOCK_RFC_BB,
+					   BT_8821C_1ANT_GNT_TYPE_CTRL_BY_PTA,
+					   BT_8821C_1ANT_GNT_SET_BY_HW);
+
+		/* Set GNT_WL to SW Hi */
+		halbtc8821c1ant_set_gnt_wl(btc, BT_8821C_1ANT_GNT_BLOCK_RFC_BB,
+					   BT_8821C_1ANT_GNT_TYPE_CTRL_BY_SW,
+					   BT_8821C_1ANT_GNT_SET_TO_HIGH);
+
+		coex_sta->run_time_state = TRUE;
+
+		if (ant_pos_type == BTC_ANT_PATH_AUTO)
+			ant_pos_type = BTC_ANT_PATH_WIFI5G;
+		break;
+	case BT_8821C_1ANT_PHASE_BTMP:
+		/* Disable LTE Coex Function in WiFi side */
+		halbtc8821c1ant_ltecoex_enable(btc, 0x0);
+
+		/* set Path control owner to WL */
+		halbtc8821c1ant_coex_ctrl_owner(btc, BT_8821C_1ANT_PCO_WLSIDE);
+
+		/* set GNT_BT to SW Hi */
+		halbtc8821c1ant_set_gnt_bt(btc, BT_8821C_1ANT_GNT_BLOCK_RFC_BB,
+					   BT_8821C_1ANT_GNT_TYPE_CTRL_BY_SW,
+					   BT_8821C_1ANT_GNT_SET_TO_HIGH);
+
+		/* Set GNT_WL to SW Lo */
+		halbtc8821c1ant_set_gnt_wl(btc, BT_8821C_1ANT_GNT_BLOCK_RFC_BB,
+					   BT_8821C_1ANT_GNT_TYPE_CTRL_BY_SW,
+					   BT_8821C_1ANT_GNT_SET_TO_LOW);
+
+		coex_sta->run_time_state = FALSE;
+
+		/* Set Ext Ant Switch to BT side at BT MP mode */
+		if (ant_pos_type == BTC_ANT_PATH_AUTO)
+			ant_pos_type = BTC_ANT_PATH_BT;
+		break;
+	case BT_8821C_1ANT_PHASE_ANTDET:
+		halbtc8821c1ant_coex_ctrl_owner(btc, BT_8821C_1ANT_PCO_WLSIDE);
+
+		/* set GNT_BT to high */
+		halbtc8821c1ant_set_gnt_bt(btc, BT_8821C_1ANT_GNT_BLOCK_RFC_BB,
+					   BT_8821C_1ANT_GNT_TYPE_CTRL_BY_SW,
+					   BT_8821C_1ANT_GNT_SET_TO_HIGH);
+		/* Set GNT_WL to high */
+		halbtc8821c1ant_set_gnt_wl(btc, BT_8821C_1ANT_GNT_BLOCK_RFC_BB,
+					   BT_8821C_1ANT_GNT_TYPE_CTRL_BY_SW,
+					   BT_8821C_1ANT_GNT_SET_TO_HIGH);
+
+		if (ant_pos_type == BTC_ANT_PATH_AUTO)
+			ant_pos_type = BTC_ANT_PATH_BT;
+
+		coex_sta->run_time_state = FALSE;
+		break;
+	case BT_8821C_1ANT_PHASE_MCC:
+		/* set Path control owner to WL at runtime step */
+		halbtc8821c1ant_coex_ctrl_owner(btc, BT_8821C_1ANT_PCO_WLSIDE);
+
+		/* set GNT_BT to PTA */
+		halbtc8821c1ant_set_gnt_bt(btc, BT_8821C_1ANT_GNT_BLOCK_RFC_BB,
+					   BT_8821C_1ANT_GNT_TYPE_CTRL_BY_PTA,
+					   BT_8821C_1ANT_GNT_SET_BY_HW);
+
+		halbtc8821c1ant_set_gnt_wl(btc, BT_8821C_1ANT_GNT_BLOCK_RFC_BB,
+					   BT_8821C_1ANT_GNT_TYPE_CTRL_BY_PTA,
+					   BT_8821C_1ANT_GNT_SET_BY_HW);
+
+		coex_sta->run_time_state = TRUE;
+
+		if (ant_pos_type == BTC_ANT_PATH_AUTO)
+			ant_pos_type = BTC_ANT_PATH_BT;
+		break;
+	}
+
+	if (phase == BT_8821C_1ANT_PHASE_WOFF) {
+		/* Set Ext Ant Switch to BT control at wifi off step */
+		ctrl_type = BT_8821C_1ANT_CTRL_BY_BT;
+		pos_type = BT_8821C_1ANT_TO_NOCARE;
+	} else if (phase == BT_8821C_1ANT_PHASE_MCC) {
+		ctrl_type = BT_8821C_1ANT_CTRL_BY_FW;
+		pos_type = BT_8821C_1ANT_TO_NOCARE;
+	} else {
+		switch (ant_pos_type) {
+		case BTC_ANT_PATH_WIFI:
+			ctrl_type = BT_8821C_1ANT_CTRL_BY_BBSW;
+			pos_type = BT_8821C_1ANT_TO_WLG;
+			break;
+		case BTC_ANT_PATH_WIFI5G:
+			ctrl_type = BT_8821C_1ANT_CTRL_BY_BBSW;
+			pos_type = BT_8821C_1ANT_TO_WLA;
+			break;
+		case BTC_ANT_PATH_BT:
+			ctrl_type = BT_8821C_1ANT_CTRL_BY_BBSW;
+			pos_type = BT_8821C_1ANT_TO_BT;
+			break;
+		default:
+		case BTC_ANT_PATH_PTA:
+			ctrl_type = BT_8821C_1ANT_CTRL_BY_PTA;
+			pos_type = BT_8821C_1ANT_TO_NOCARE;
+			break;
+		}
+	}
+
+	halbtc8821c1ant_set_ant_switch(btc, force_exec, ctrl_type, pos_type);
+
+	if (btc->dbg_mode) {
+		u32tmp1 = btc->btc_read_4byte(btc, 0xcbc);
+		u32tmp2 = btc->btc_read_4byte(btc, 0xcb4);
+		u8tmp  = btc->btc_read_1byte(btc, 0x73);
+
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], (After Ant Setup) 0xcb4 = 0x%x, 0xcbc = 0x%x, 0x73 = 0x%x\n",
+			    u32tmp1, u32tmp2, u8tmp);
+		BTC_TRACE(trace_buf);
+	}
+}
+
+/* *********************************************
+ *
+ *	Software Coex Mechanism start
+ *
+ * *********************************************
+ */
+
+
+
+/* *********************************************
+ *
+ *	Non-Software Coex Mechanism start
+ *
+ * *********************************************
+ */
+static
+u8 halbtc8821c1ant_action_algorithm(struct btc_coexist *btc)
+{
+	struct btc_bt_link_info *bt_link_info = &btc->bt_link_info;
+	u8 algorithm = BT_8821C_1ANT_COEX_UNDEFINED;
+	u8 profile_map = 0;
+
+	if (bt_link_info->sco_exist)
+		profile_map = profile_map | BIT(0);
+
+	if (bt_link_info->hid_exist)
+		profile_map = profile_map | BIT(1);
+
+	if (bt_link_info->a2dp_exist)
+		profile_map = profile_map | BIT(2);
+
+	if (bt_link_info->pan_exist)
+		profile_map = profile_map | BIT(3);
+
+	switch (profile_map) {
+	default:
+	case 0:
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], No BT link exists!!!\n");
+		BTC_TRACE(trace_buf);
+		algorithm = BT_8821C_1ANT_COEX_UNDEFINED;
+		break;
+	case 1:
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], BT Profile = SCO only\n");
+		BTC_TRACE(trace_buf);
+		algorithm = BT_8821C_1ANT_COEX_SCO;
+		break;
+	case 2:
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], BT Profile = HID only\n");
+		BTC_TRACE(trace_buf);
+		algorithm = BT_8821C_1ANT_COEX_HID;
+		break;
+	case 3:
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], BT Profile = SCO + HID ==> HID\n");
+		BTC_TRACE(trace_buf);
+		algorithm = BT_8821C_1ANT_COEX_HID;
+		break;
+	case 4:
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				    "[BTCoex], BT Profile = A2DP only\n");
+		BTC_TRACE(trace_buf);
+		algorithm = BT_8821C_1ANT_COEX_A2DP;
+		break;
+	case 5:
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], BT Profile = SCO + A2DP ==> HID + A2DP\n");
+		BTC_TRACE(trace_buf);
+		algorithm = BT_8821C_1ANT_COEX_HID_A2DP;
+		break;
+	case 6:
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], BT Profile = HID + A2DP\n");
+		BTC_TRACE(trace_buf);
+		algorithm = BT_8821C_1ANT_COEX_HID_A2DP;
+		break;
+	case 7:
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], BT Profile = SCO + HID + A2DP ==> HID + A2DP\n");
+		BTC_TRACE(trace_buf);
+		algorithm = BT_8821C_1ANT_COEX_HID_A2DP;
+		break;
+	case 8:
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], BT Profile = PAN(EDR) only\n");
+		BTC_TRACE(trace_buf);
+		algorithm = BT_8821C_1ANT_COEX_PAN;
+		break;
+	case 9:
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], BT Profile = SCO + PAN(EDR) ==> HID + PAN(EDR)\n");
+		BTC_TRACE(trace_buf);
+		algorithm = BT_8821C_1ANT_COEX_PAN_HID;
+		break;
+	case 10:
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], BT Profile = HID + PAN(EDR)\n");
+		BTC_TRACE(trace_buf);
+		algorithm = BT_8821C_1ANT_COEX_PAN_HID;
+		break;
+	case 11:
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], BT Profile = SCO + HID + PAN(EDR) ==> HID + PAN(EDR)\n");
+		BTC_TRACE(trace_buf);
+		algorithm = BT_8821C_1ANT_COEX_PAN_HID;
+		break;
+	case 12:
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], BT Profile = A2DP + PAN(EDR)\n");
+		BTC_TRACE(trace_buf);
+		algorithm = BT_8821C_1ANT_COEX_PAN_A2DP;
+		break;
+	case 13:
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], BT Profile = SCO + A2DP + PAN(EDR) ==> A2DP + PAN(EDR)\n");
+		BTC_TRACE(trace_buf);
+		algorithm = BT_8821C_1ANT_COEX_PAN_A2DP;
+		break;
+	case 14:
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], BT Profile = HID + A2DP + PAN(EDR) ==> A2DP + PAN(EDR)\n");
+		BTC_TRACE(trace_buf);
+		algorithm = BT_8821C_1ANT_COEX_PAN_A2DP;
+		break;
+	case 15:
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], BT Profile = SCO + HID + A2DP + PAN(EDR) ==> A2DP + PAN(EDR)\n");
+		BTC_TRACE(trace_buf);
+		algorithm = BT_8821C_1ANT_COEX_PAN_A2DP;
+		break;
+	}
+
+	return algorithm;
+}
+
+static
+void halbtc8821c1ant_action_coex_all_off(struct btc_coexist *btc)
+{
+	halbtc8821c1ant_table(btc, NM_EXCU, 0);
+	halbtc8821c1ant_tdma(btc, NM_EXCU, FALSE, 0);
+}
+
+static
+void halbtc8821c1ant_action_bt_whql_test(struct btc_coexist *btc)
+{
+	halbtc8821c1ant_set_ant_path(btc, BTC_ANT_PATH_AUTO, NM_EXCU,
+				     BT_8821C_1ANT_PHASE_2G);
+	halbtc8821c1ant_table(btc, NM_EXCU, 0);
+	halbtc8821c1ant_tdma(btc, NM_EXCU, FALSE, 8);
+}
+
+static
+void halbtc8821c1ant_action_bt_relink(struct btc_coexist *btc)
+{
+	struct coex_sta_8821c_1ant *coex_sta = &btc->coex_sta_8821c_1ant;
+	struct  btc_bt_link_info *bt_link_info = &btc->bt_link_info;
+
+	if ((!coex_sta->is_bt_multi_link && !bt_link_info->pan_exist) ||
+	    (bt_link_info->a2dp_exist && bt_link_info->hid_exist)) {
+		halbtc8821c1ant_table(btc, NM_EXCU, 0);
+		halbtc8821c1ant_tdma(btc, NM_EXCU, FALSE, 8);
+	}
+}
+
+static
+void halbtc8821c1ant_action_bt_idle(struct btc_coexist *btc)
+{
+	struct coex_sta_8821c_1ant *coex_sta = &btc->coex_sta_8821c_1ant;
+	struct coex_dm_8821c_1ant *coex_dm = &btc->coex_dm_8821c_1ant;
+	boolean wifi_busy = FALSE;
+	u32 wifi_link_status = 0;
+
+	btc->btc_get(btc, BTC_GET_BL_WIFI_BUSY, &wifi_busy);
+	btc->btc_get(btc, BTC_GET_U4_WIFI_LINK_STATUS, &wifi_link_status);
+
+	if (!wifi_busy) {
+		halbtc8821c1ant_table(btc, NM_EXCU, 7);
+		halbtc8821c1ant_tdma(btc, NM_EXCU, TRUE, 32);
+	} else { /* if wl busy */
+		/*for initiator scan on*/
+		if ((coex_sta->bt_ble_scan_type & 0x2) &&
+		    BT_8821C_1ANT_BSTATUS_NCON_IDLE ==
+		    coex_dm->bt_status) {
+			halbtc8821c1ant_table(btc, NM_EXCU, 2);
+			halbtc8821c1ant_tdma(btc, NM_EXCU, TRUE, 36);
+		} else {
+			halbtc8821c1ant_table(btc, NM_EXCU, 2);
+			halbtc8821c1ant_tdma(btc, NM_EXCU, TRUE, 33);
+		}
+	}
+}
+
+static
+void halbtc8821c1ant_action_bt_inquiry(struct btc_coexist *btc)
+{
+	struct coex_sta_8821c_1ant *coex_sta = &btc->coex_sta_8821c_1ant;
+	struct  btc_bt_link_info *bt_link_info = &btc->bt_link_info;
+	boolean	wifi_connected = FALSE, wifi_busy = FALSE;
+
+	btc->btc_get(btc, BTC_GET_BL_WIFI_CONNECTED, &wifi_connected);
+	btc->btc_get(btc, BTC_GET_BL_WIFI_BUSY, &wifi_busy);
+
+	if (coex_sta->is_wifi_linkscan_process ||
+	    coex_sta->wifi_high_pri_task1 ||
+	    coex_sta->wifi_high_pri_task2) {
+
+		if (coex_sta->bt_create_connection) {
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				    "[BTCoex], bt page +  wifi hi-pri task\n");
+			BTC_TRACE(trace_buf);
+
+			halbtc8821c1ant_table(btc, NM_EXCU, 1);
+
+			if (bt_link_info->a2dp_exist &&
+			    !bt_link_info->pan_exist)
+				halbtc8821c1ant_tdma(btc, NM_EXCU, TRUE, 17);
+			else if (coex_sta->wifi_high_pri_task1)
+				halbtc8821c1ant_tdma(btc, NM_EXCU, TRUE, 36);
+			else
+				halbtc8821c1ant_tdma(btc, NM_EXCU, TRUE, 33);
+		} else {
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				    "[BTCoex], bt inquiry +  wifi hi-pri task\n");
+			BTC_TRACE(trace_buf);
+
+			halbtc8821c1ant_table(btc, NM_EXCU, 1);
+			halbtc8821c1ant_tdma(btc, NM_EXCU, TRUE, 21);
+		}
+	} else if (wifi_busy) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], bt inq/page +  wifi busy\n");
+		BTC_TRACE(trace_buf);
+
+		halbtc8821c1ant_table(btc, NM_EXCU, 1);
+		/* for android 6.0  remote name request */
+		halbtc8821c1ant_tdma(btc, NM_EXCU, TRUE, 23);
+	} else if (wifi_connected) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], bt inq/page +  wifi connected\n");
+		BTC_TRACE(trace_buf);
+
+		halbtc8821c1ant_table(btc, NM_EXCU, 1);
+		halbtc8821c1ant_tdma(btc, NM_EXCU, TRUE, 23);
+	} else {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], bt inq/page +  wifi not-connected\n");
+		BTC_TRACE(trace_buf);
+		halbtc8821c1ant_table(btc, NM_EXCU, 0);
+		halbtc8821c1ant_tdma(btc, NM_EXCU, FALSE, 8);
+	}
+}
+
+static
+void halbtc8821c1ant_action_bt_sco_hid_busy(struct btc_coexist *btc)
+{
+	struct coex_sta_8821c_1ant *coex_sta = &btc->coex_sta_8821c_1ant;
+	struct  btc_bt_link_info *bt_link_info = &btc->bt_link_info;
+	boolean	wifi_connected = FALSE, wifi_busy = FALSE,
+		wifi_cckdeadlock_ap = FALSE;
+	u32  wifi_bw = 1;
+	u8 iot_peer = BTC_IOT_PEER_UNKNOWN;
+
+	btc->btc_get(btc, BTC_GET_BL_WIFI_CONNECTED, &wifi_connected);
+	btc->btc_get(btc, BTC_GET_U4_WIFI_BW, &wifi_bw);
+	btc->btc_get(btc, BTC_GET_BL_WIFI_BUSY, &wifi_busy);
+	btc->btc_get(btc, BTC_GET_U1_IOT_PEER, &iot_peer);
+
+	if (!wifi_busy)
+		wifi_busy = coex_sta->gl_wifi_busy;
+
+	if (iot_peer == BTC_IOT_PEER_ATHEROS && coex_sta->cck_lock_ever)
+		wifi_cckdeadlock_ap = TRUE;
+
+	if (bt_link_info->sco_exist) {
+		if (coex_sta->is_bt_multi_link) {
+			halbtc8821c1ant_table(btc, NM_EXCU, 1);
+			halbtc8821c1ant_tdma(btc, NM_EXCU, TRUE, 25);
+		} else {
+			halbtc8821c1ant_table(btc, NM_EXCU, 1);
+			halbtc8821c1ant_tdma(btc, NM_EXCU, TRUE, 5);
+		}
+	} else if (coex_sta->is_hid_rcu) {
+		if (coex_sta->voice_over_HOGP) { /* voice by RCU */
+			/* change coex table if slave latency support or not */
+			if (!wifi_busy)
+				halbtc8821c1ant_table(btc, NM_EXCU, 7);
+			else if (coex_sta->bt_coex_supported_feature & BIT(11))
+				halbtc8821c1ant_table(btc, NM_EXCU, 1);
+			else
+				halbtc8821c1ant_table(btc, NM_EXCU, 2);
+
+			if (wifi_busy)
+				halbtc8821c1ant_tdma(btc, NM_EXCU, TRUE, 37);
+			else
+				halbtc8821c1ant_tdma(btc, NM_EXCU, TRUE, 6);
+		} else { /* RCU */
+			if (!wifi_busy)
+				halbtc8821c1ant_table(btc, NM_EXCU, 7);
+			else if (coex_sta->bt_coex_supported_feature & BIT(11))
+				halbtc8821c1ant_table(btc, NM_EXCU, 1);
+			else
+				halbtc8821c1ant_table(btc, NM_EXCU, 2);
+
+			if (wifi_busy && coex_sta->wl_noisy_level == 0)
+				halbtc8821c1ant_tdma(btc, NM_EXCU, TRUE, 36);
+			else if (wifi_busy)
+				halbtc8821c1ant_tdma(btc, NM_EXCU, TRUE, 37);
+			else
+				halbtc8821c1ant_tdma(btc, NM_EXCU, TRUE, 6);
+		}
+	} else {
+		/* for HID exist */
+		if (wifi_cckdeadlock_ap &&
+		    coex_sta->is_hid_low_pri_tx_overhead) {
+			halbtc8821c1ant_table(btc, NM_EXCU, 13);
+			halbtc8821c1ant_tdma(btc, NM_EXCU, TRUE, 18);
+		} else if (coex_sta->is_hid_low_pri_tx_overhead) {
+			halbtc8821c1ant_table(btc, NM_EXCU, 1);
+			halbtc8821c1ant_tdma(btc, NM_EXCU, TRUE, 18);
+		} else if (wifi_bw == 0) { /* if 11bg mode */
+			halbtc8821c1ant_table(btc, NM_EXCU, 11);
+			halbtc8821c1ant_tdma(btc, NM_EXCU, TRUE, 11);
+		} else {
+			halbtc8821c1ant_table(btc, NM_EXCU, 1);
+			halbtc8821c1ant_tdma(btc, NM_EXCU, TRUE, 11);
+		}
+	}
+}
+
+static
+void halbtc8821c1ant_action_bt_acl_busy(struct btc_coexist *btc)
+{
+	struct coex_sta_8821c_1ant *coex_sta = &btc->coex_sta_8821c_1ant;
+	struct btc_bt_link_info *bt_link_info = &btc->bt_link_info;
+	boolean	wifi_busy = FALSE, wifi_turbo = FALSE,
+		wifi_cckdeadlock_ap = FALSE, bt_slave_latency = FALSE,
+		ap_enable = FALSE;
+	u32 wifi_bw = 1;
+	u8 iot_peer = BTC_IOT_PEER_UNKNOWN;
+
+	btc->btc_get(btc, BTC_GET_U4_WIFI_BW, &wifi_bw);
+	btc->btc_get(btc, BTC_GET_BL_WIFI_BUSY, &wifi_busy);
+	btc->btc_get(btc, BTC_GET_U1_AP_NUM, &coex_sta->scan_ap_num);
+	btc->btc_get(btc, BTC_GET_U1_IOT_PEER, &iot_peer);
+	btc->btc_get(btc, BTC_GET_BL_WIFI_AP_MODE_ENABLE, &ap_enable);
+
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+		    "############# [BTCoex],  scan_ap_num = %d, wl_noisy_level = %d\n",
+		    coex_sta->scan_ap_num, coex_sta->wl_noisy_level);
+	BTC_TRACE(trace_buf);
+
+	if (!wifi_busy)
+		wifi_busy = coex_sta->gl_wifi_busy;
+
+	if (wifi_busy && coex_sta->wl_noisy_level == 0)
+		wifi_turbo = TRUE;
+
+	if (iot_peer == BTC_IOT_PEER_ATHEROS && coex_sta->cck_lock_ever)
+		wifi_cckdeadlock_ap = TRUE;
+
+	if (coex_sta->bt_coex_supported_feature & BIT(11))
+		bt_slave_latency = TRUE;
+	else
+		bt_slave_latency = FALSE;
+
+	if (bt_link_info->a2dp_exist && coex_sta->is_bt_a2dp_sink) {
+		if (ap_enable)
+			halbtc8821c1ant_table(btc, NM_EXCU, 0);
+		else if (coex_sta->wl_noisy_level == 0 && wifi_cckdeadlock_ap)
+			halbtc8821c1ant_table(btc, NM_EXCU, 13);
+		else
+			halbtc8821c1ant_table(btc, NM_EXCU, 1);
+
+		if (ap_enable)
+			halbtc8821c1ant_tdma(btc, NM_EXCU, FALSE, 8);
+		else
+			halbtc8821c1ant_tdma(btc, NM_EXCU, TRUE, 12);
+	} else if (bt_link_info->a2dp_only) { /* A2DP */
+		if (wifi_busy && (coex_sta->bt_ble_scan_type & 0x2)) {
+			if (coex_sta->wl_noisy_level == 0 &&
+			    wifi_cckdeadlock_ap)
+				halbtc8821c1ant_table(btc, NM_EXCU, 10);
+			else if (coex_sta->wl_noisy_level == 0 &&
+				 !wifi_cckdeadlock_ap)
+				halbtc8821c1ant_table(btc, NM_EXCU, 9);
+			else
+				halbtc8821c1ant_table(btc, NM_EXCU, 1);
+		} else if (wifi_busy && !(coex_sta->bt_ble_scan_type & 0x2)) {
+			if (coex_sta->wl_noisy_level == 0 &&
+			    wifi_cckdeadlock_ap)
+				halbtc8821c1ant_table(btc, NM_EXCU, 13);
+			else
+				halbtc8821c1ant_table(btc, NM_EXCU, 1);
+		} else { /* wifi idle  */
+			halbtc8821c1ant_table(btc, NM_EXCU, 7);
+		}
+
+		if (coex_sta->connect_ap_period_cnt > 0 || !wifi_busy)
+			halbtc8821c1ant_tdma(btc, NM_EXCU, TRUE, 26);
+		else
+			halbtc8821c1ant_tdma(btc, NM_EXCU, TRUE, 7);
+	} else if ((bt_link_info->a2dp_exist && bt_link_info->pan_exist) ||
+		   (bt_link_info->hid_exist && bt_link_info->a2dp_exist &&
+		    bt_link_info->pan_exist)) {
+		    /* A2DP+PAN(OPP,FTP), HID+A2DP+PAN(OPP,FTP) */
+		if (coex_sta->wl_noisy_level == 0 && wifi_cckdeadlock_ap)
+			halbtc8821c1ant_table(btc, NM_EXCU, 13);
+		else if (bt_link_info->hid_exist)
+			halbtc8821c1ant_table(btc, NM_EXCU, 1);
+		else if (wifi_turbo)
+			halbtc8821c1ant_table(btc, NM_EXCU, 8);
+		else
+			halbtc8821c1ant_table(btc, NM_EXCU, 4);
+
+		if (wifi_busy)
+			halbtc8821c1ant_tdma(btc, NM_EXCU, TRUE, 13);
+		else
+			halbtc8821c1ant_tdma(btc, NM_EXCU, TRUE, 14);
+	} else if (bt_link_info->hid_exist && coex_sta->is_hid_rcu &&
+		coex_sta->voice_over_HOGP && bt_link_info->a2dp_exist) {
+		/* RCU voice + A2DP */
+		/* change coex table if slave latency support or not */
+		if (wifi_busy && !bt_slave_latency) {
+			if (coex_sta->wl_noisy_level == 0 &&
+			    wifi_cckdeadlock_ap)
+				halbtc8821c1ant_table(btc, NM_EXCU, 10);
+			else if (coex_sta->wl_noisy_level == 0 &&
+				 !wifi_cckdeadlock_ap)
+				halbtc8821c1ant_table(btc, NM_EXCU, 9);
+			else
+				halbtc8821c1ant_table(btc, NM_EXCU, 1);
+		} else if (wifi_busy && bt_slave_latency) {
+			if (coex_sta->wl_noisy_level == 0 &&
+			    wifi_cckdeadlock_ap)
+				halbtc8821c1ant_table(btc, NM_EXCU, 13);
+			else
+				halbtc8821c1ant_table(btc, NM_EXCU, 1);
+		} else { /* wifi idle  */
+			halbtc8821c1ant_table(btc, NM_EXCU, 7);
+		}
+
+		if (coex_sta->connect_ap_period_cnt > 0 || !wifi_busy)
+			halbtc8821c1ant_tdma(btc, NM_EXCU, TRUE, 10);
+		else
+			halbtc8821c1ant_tdma(btc, NM_EXCU, TRUE, 13);
+	} else if (bt_link_info->hid_exist && coex_sta->is_hid_rcu &&
+		   bt_link_info->a2dp_exist) {
+		/* RCU + A2DP */
+		/* change coex table if slave latency support or not */
+		if (wifi_busy && !bt_slave_latency) {
+			if (coex_sta->wl_noisy_level == 0 &&
+			    wifi_cckdeadlock_ap)
+				halbtc8821c1ant_table(btc, NM_EXCU, 10);
+			else if (coex_sta->wl_noisy_level == 0 &&
+				 !wifi_cckdeadlock_ap)
+				halbtc8821c1ant_table(btc, NM_EXCU, 9);
+			else
+				halbtc8821c1ant_table(btc, NM_EXCU, 1);
+		} else if (wifi_busy && bt_slave_latency) {
+			if (coex_sta->wl_noisy_level == 0 &&
+			    wifi_cckdeadlock_ap)
+				halbtc8821c1ant_table(btc, NM_EXCU, 13);
+			else
+				halbtc8821c1ant_table(btc, NM_EXCU, 1);
+		} else { /* wifi idle  */
+			halbtc8821c1ant_table(btc, NM_EXCU, 7);
+		}
+
+		if (coex_sta->connect_ap_period_cnt > 0 || !wifi_busy)
+			halbtc8821c1ant_tdma(btc, NM_EXCU, TRUE, 26);
+		else
+			halbtc8821c1ant_tdma(btc, NM_EXCU, TRUE, 7);
+	} else if (bt_link_info->hid_exist && bt_link_info->a2dp_exist) {
+		/* HID+A2DP */
+		if (coex_sta->wl_noisy_level == 0 && wifi_cckdeadlock_ap)
+			halbtc8821c1ant_table(btc, NM_EXCU, 13);
+		else if (wifi_bw == 0)/* if 11bg mode */
+			halbtc8821c1ant_table(btc, NM_EXCU, 12);
+		else
+			halbtc8821c1ant_table(btc, NM_EXCU, 1);
+
+		if (coex_sta->connect_ap_period_cnt > 0 || !wifi_busy)
+			halbtc8821c1ant_tdma(btc, NM_EXCU, TRUE, 26);
+		else
+			halbtc8821c1ant_tdma(btc, NM_EXCU, TRUE, 7);
+	} else if (bt_link_info->pan_only ||
+		   (bt_link_info->hid_exist && bt_link_info->pan_exist)) {
+			/* PAN(OPP,FTP), HID+PAN(OPP,FTP) */
+		if (coex_sta->wl_noisy_level == 0 && wifi_cckdeadlock_ap)
+			halbtc8821c1ant_table(btc, NM_EXCU, 13);
+		else if (bt_link_info->hid_exist)
+			halbtc8821c1ant_table(btc, NM_EXCU, 1);
+		else if (wifi_turbo || iot_peer == BTC_IOT_PEER_CISCO)
+			halbtc8821c1ant_table(btc, NM_EXCU, 8);
+		else
+			halbtc8821c1ant_table(btc, NM_EXCU, 4);
+
+		if (!wifi_busy)
+			halbtc8821c1ant_tdma(btc, NM_EXCU, TRUE, 4);
+		else
+			halbtc8821c1ant_tdma(btc, NM_EXCU, TRUE, 3);
+	} else {
+		/* BT no-profile busy (0x9) */
+		halbtc8821c1ant_table(btc, NM_EXCU, 4);
+		halbtc8821c1ant_tdma(btc, NM_EXCU, TRUE, 33);
+	}
+}
+
+static
+void halbtc8821c1ant_action_bt_mr(struct btc_coexist *btc)
+{
+	struct wifi_link_info_8821c_1ant *wifi_link_info_ext =
+					 &btc->wifi_link_info_8821c_1ant;
+
+	if (!wifi_link_info_ext->is_all_under_5g) {
+		halbtc8821c1ant_set_ant_path(btc, BTC_ANT_PATH_AUTO, NM_EXCU,
+					     BT_8821C_1ANT_PHASE_2G);
+
+		halbtc8821c1ant_table(btc, NM_EXCU, 8);
+		halbtc8821c1ant_tdma(btc, NM_EXCU, TRUE, 32);
+	} else {
+		halbtc8821c1ant_set_ant_path(btc, BTC_ANT_PATH_AUTO, NM_EXCU,
+					     BT_8821C_1ANT_PHASE_5G);
+
+		halbtc8821c1ant_table(btc, NM_EXCU, 0);
+		halbtc8821c1ant_tdma(btc, NM_EXCU, FALSE, 8);
+	}
+}
+
+static
+void halbtc8821c1ant_action_wifi_under5g(struct btc_coexist *btc)
+{
+	halbtc8821c1ant_set_ant_path(btc, BTC_ANT_PATH_AUTO, NM_EXCU,
+				     BT_8821C_1ANT_PHASE_5G);
+	halbtc8821c1ant_table(btc, NM_EXCU, 0);
+	halbtc8821c1ant_tdma(btc, NM_EXCU, FALSE, 8);
+}
+
+static
+void halbtc8821c1ant_action_wifi_only(struct btc_coexist *btc)
+{
+	halbtc8821c1ant_table(btc, FC_EXCU, 10);
+	halbtc8821c1ant_tdma(btc, FC_EXCU, FALSE, 8);
+}
+
+static
+void halbtc8821c1ant_action_wifi_native_lps(struct btc_coexist *btc)
+{
+	halbtc8821c1ant_table(btc, NM_EXCU, 5);
+	halbtc8821c1ant_tdma(btc, NM_EXCU, FALSE, 8);
+}
+
+#if 0
+static
+void halbtc8821c1ant_action_wifi_cck_dead_lock(struct btc_coexist *btc)
+{
+	struct  btc_bt_link_info *bt_link_info = &btc->bt_link_info;
+
+	if (bt_link_info->hid_exis && bt_link_info->a2dp_exist &&
+	    !bt_link_info->pan_exist) {
+
+		if (coex_sta->cck_lock || coex_sta->cck_lock_warn) {
+			halbtc8821c1ant_table(btc, NM_EXCU, 13);
+			halbtc8821c1ant_tdma(btc, NM_EXCU, TRUE, 28);
+		} else {
+			halbtc8821c1ant_table(btc, NM_EXCU, 13);
+			halbtc8821c1ant_tdma(btc, NM_EXCU, TRUE, 8);
+		}
+	}
+}
+#endif
+
+static
+void halbtc8821c1ant_action_wifi_linkscan(struct btc_coexist *btc)
+{
+	struct  btc_bt_link_info *bt_link_info = &btc->bt_link_info;
+
+	if (bt_link_info->pan_exist) {
+		halbtc8821c1ant_table(btc, NM_EXCU, 4);
+		halbtc8821c1ant_tdma(btc, NM_EXCU, TRUE, 22);
+	} else if (bt_link_info->a2dp_exist) {
+		halbtc8821c1ant_table(btc, NM_EXCU, 4);
+		halbtc8821c1ant_tdma(btc, NM_EXCU, TRUE, 27);
+	} else {
+		halbtc8821c1ant_table(btc, NM_EXCU, 4);
+		halbtc8821c1ant_tdma(btc, NM_EXCU, TRUE, 21);
+	}
+}
+
+static
+void halbtc8821c1ant_action_wifi_not_connected(struct btc_coexist *btc)
+{
+	/* tdma and coex table */
+	halbtc8821c1ant_table(btc, NM_EXCU, 0);
+	halbtc8821c1ant_tdma(btc, FC_EXCU, FALSE, 8);
+}
+
+static
+void halbtc8821c1ant_action_wifi_connected(struct btc_coexist *btc)
+{
+	struct  btc_bt_link_info *bt_link_info = &btc->bt_link_info;
+	struct coex_dm_8821c_1ant *coex_dm = &btc->coex_dm_8821c_1ant;
+	u32 wifi_bw;
+	u8 iot_peer = BTC_IOT_PEER_UNKNOWN, algorithm;
+
+	btc->btc_get(btc, BTC_GET_U4_WIFI_BW, &wifi_bw);
+
+	if (bt_link_info->bt_link_exist) {
+		btc->btc_get(btc, BTC_GET_U1_IOT_PEER, &iot_peer);
+
+		if (iot_peer == BTC_IOT_PEER_CISCO) {
+			if (wifi_bw == BTC_WIFI_BW_HT40)
+				halbtc8821c1ant_limited_rx(btc, NM_EXCU, FALSE,
+							   TRUE, 0x10);
+			else
+				halbtc8821c1ant_limited_rx(btc, NM_EXCU, FALSE,
+							   TRUE, 0x8);
+		}
+	}
+
+	algorithm = halbtc8821c1ant_action_algorithm(btc);
+
+	coex_dm->cur_algorithm = algorithm;
+
+	if (coex_dm->bt_status == BT_8821C_1ANT_BSTATUS_ACL_BUSY ||
+	    coex_dm->bt_status == BT_8821C_1ANT_BSTATUS_ACL_SCO_BUSY) {
+
+		if (bt_link_info->hid_only)  /* HID only */
+			halbtc8821c1ant_action_bt_sco_hid_busy(btc);
+		else
+			halbtc8821c1ant_action_bt_acl_busy(btc);
+
+	} else if (coex_dm->bt_status == BT_8821C_1ANT_BSTATUS_SCO_BUSY) {
+		halbtc8821c1ant_action_bt_sco_hid_busy(btc);
+	} else {
+		halbtc8821c1ant_action_bt_idle(btc);
+	}
+}
+
+static
+void halbtc8821c1ant_action_wifi_multiport25g(struct btc_coexist *btc)
+{
+	struct coex_sta_8821c_1ant *coex_sta = &btc->coex_sta_8821c_1ant;
+	struct btc_bt_link_info *bt_link_info = &btc->bt_link_info;
+
+	halbtc8821c1ant_set_ant_path(btc, BTC_ANT_PATH_AUTO, NM_EXCU,
+				     BT_8821C_1ANT_PHASE_MCC);
+
+	halbtc8821c1ant_write_scbd(btc, BT_8821C_1ANT_SCBD_BTCQDDR, TRUE);
+
+	if (coex_sta->is_setup_link || coex_sta->bt_relink_downcount != 0) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], wifi_multiport25g(), BT Relink!!\n");
+		BTC_TRACE(trace_buf);
+
+		halbtc8821c1ant_table(btc, NM_EXCU, 15);
+		halbtc8821c1ant_tdma(btc, NM_EXCU, FALSE, 8);
+	} else if (coex_sta->c2h_bt_inquiry_page) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], wifi_multiport25g(), BT Inq-Page!!\n");
+		BTC_TRACE(trace_buf);
+
+		halbtc8821c1ant_table(btc, NM_EXCU, 15);
+		halbtc8821c1ant_tdma(btc, NM_EXCU, FALSE, 8);
+	} else {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], wifi_multiport25g(), BT idle or busy!!\n");
+		BTC_TRACE(trace_buf);
+
+		halbtc8821c1ant_table(btc, NM_EXCU, 15);
+		halbtc8821c1ant_tdma(btc, NM_EXCU, FALSE, 8);
+	}
+}
+
+static
+void halbtc8821c1ant_action_wifi_multiport2g(struct btc_coexist *btc)
+{
+	struct coex_sta_8821c_1ant *coex_sta = &btc->coex_sta_8821c_1ant;
+	struct  btc_bt_link_info *bt_link_info = &btc->bt_link_info;
+	struct btc_multi_port_tdma_info multiport_tdma_para;
+	u32 traffic_dir;
+
+	halbtc8821c1ant_write_scbd(btc, BT_8821C_1ANT_SCBD_BTCQDDR, TRUE);
+	btc->btc_get(btc, BTC_GET_U4_WIFI_TRAFFIC_DIRECTION, &traffic_dir);
+
+	if (coex_sta->is_setup_link || coex_sta->bt_relink_downcount != 0) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], wifi_multiport2g, BT Relink!!\n");
+		BTC_TRACE(trace_buf);
+
+		halbtc8821c1ant_set_ant_path(btc, BTC_ANT_PATH_AUTO, NM_EXCU,
+					     BT_8821C_1ANT_PHASE_2G);
+
+		halbtc8821c1ant_table(btc, NM_EXCU, 0);
+		halbtc8821c1ant_tdma(btc, NM_EXCU, FALSE, 8);
+	} else if (coex_sta->c2h_bt_inquiry_page) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], wifi_multiport2g, BT Inq-Page!!\n");
+		BTC_TRACE(trace_buf);
+
+		halbtc8821c1ant_set_ant_path(btc, BTC_ANT_PATH_AUTO, NM_EXCU,
+					     BT_8821C_1ANT_PHASE_2G);
+
+		halbtc8821c1ant_table(btc, NM_EXCU, 1);
+		halbtc8821c1ant_tdma(btc, NM_EXCU, TRUE, 33);
+	} else if (coex_sta->num_of_profile == 0) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			"[BTCoex], wifi_multiport2g, BT idle!!\n");
+		BTC_TRACE(trace_buf);
+
+		halbtc8821c1ant_set_ant_path(btc, BTC_ANT_PATH_AUTO, NM_EXCU,
+					     BT_8821C_1ANT_PHASE_2G);
+
+		/* for P2P-GO only A2DP sink */
+		if (btc->wifi_link_info.link_mode == BTC_LINK_ONLY_GO &&
+		    traffic_dir == BTC_WIFI_TRAFFIC_RX) {
+			halbtc8821c1ant_table(btc, NM_EXCU, 2);
+			halbtc8821c1ant_tdma(btc, NM_EXCU, TRUE, 33);
+		} else {
+			halbtc8821c1ant_table(btc, NM_EXCU, 0);
+			halbtc8821c1ant_tdma(btc, NM_EXCU, FALSE, 8);
+		}
+	} else if (coex_sta->is_wifi_linkscan_process) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], wifi_multiport2g, WL scan!!\n");
+		BTC_TRACE(trace_buf);
+
+		halbtc8821c1ant_set_ant_path(btc, BTC_ANT_PATH_AUTO, NM_EXCU,
+					     BT_8821C_1ANT_PHASE_2G);
+		halbtc8821c1ant_action_wifi_linkscan(btc);
+	} else {
+
+		halbtc8821c1ant_set_ant_path(btc, BTC_ANT_PATH_AUTO, NM_EXCU,
+					     BT_8821C_1ANT_PHASE_2G);
+
+		if (!coex_sta->is_bt_multi_link &&
+		    (bt_link_info->sco_exist || bt_link_info->hid_exist ||
+		    coex_sta->is_hid_rcu)) {
+
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				    "[BTCoex], wifi_multiport2g, 2G multi-port + BT HID/HFP/RCU!!\n");
+			BTC_TRACE(trace_buf);
+
+			halbtc8821c1ant_table(btc, NM_EXCU, 0);
+			halbtc8821c1ant_tdma(btc, NM_EXCU, FALSE, 8);
+		} else {
+			switch (btc->wifi_link_info.link_mode) {
+			#if 0
+			case BTC_LINK_2G_SCC_GO_STA:
+				BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+					    "[BTCoex], wifi_multiport2g, 2G_SCC_GO_STA + BT busy!!\n");
+				BTC_TRACE(trace_buf);
+
+				halbtc8821c1ant_table(btc, NM_EXCU, 4);
+				halbtc8821c1ant_tdma(btc, NM_EXCU, TRUE, 201);
+				break;
+			case BTC_LINK_ONLY_GO:
+				BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+					    "[BTCoex], wifi_singleport2g, Only_P2PGO with client-join + BT busy!!\n");
+				BTC_TRACE(trace_buf);
+				halbtc8821c1ant_table(btc, NM_EXCU, 4);
+				halbtc8821c1ant_tdma(btc, NM_EXCU, TRUE, 202);
+				break;
+			#endif
+			default:
+				BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+					    "[BTCoex], wifi_multiport2g, Other multi-port + BT busy!!\n");
+				BTC_TRACE(trace_buf);
+
+				if (bt_link_info->a2dp_exist)
+					halbtc8821c1ant_table(btc, NM_EXCU, 0);
+				else
+					halbtc8821c1ant_table(btc, NM_EXCU, 5);
+
+				halbtc8821c1ant_tdma(btc, NM_EXCU, FALSE, 8);
+				break;
+			}
+		}
+	}
+}
+
+static
+void halbtc8821c1ant_run_coex(struct btc_coexist *btc, u8 reason)
+{
+	struct coex_sta_8821c_1ant *coex_sta = &btc->coex_sta_8821c_1ant;
+	struct coex_dm_8821c_1ant *coex_dm = &btc->coex_dm_8821c_1ant;
+	struct wifi_link_info_8821c_1ant *wifi_link_info_ext =
+					 &btc->wifi_link_info_8821c_1ant;
+	boolean	wifi_connected = FALSE, wifi_32k = FALSE;
+	boolean	scan = FALSE, link = FALSE, roam = FALSE, under_4way = FALSE;
+
+	btc->btc_get(btc, BTC_GET_BL_WIFI_SCAN, &scan);
+	btc->btc_get(btc, BTC_GET_BL_WIFI_LINK, &link);
+	btc->btc_get(btc, BTC_GET_BL_WIFI_ROAM, &roam);
+	btc->btc_get(btc, BTC_GET_BL_WIFI_4_WAY_PROGRESS, &under_4way);
+	btc->btc_get(btc, BTC_GET_BL_WIFI_CONNECTED, &wifi_connected);
+	btc->btc_get(btc, BTC_GET_BL_WIFI_LW_PWR_STATE, &wifi_32k);
+
+	if (scan || link || roam || under_4way ||
+	    reason == BT_8821C_1ANT_RSN_2GSCANSTART ||
+	    reason == BT_8821C_1ANT_RSN_2GSWITCHBAND ||
+	    reason == BT_8821C_1ANT_RSN_2GCONSTART ||
+	    reason == BT_8821C_1ANT_RSN_2GSPECIALPKT) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], scan = %d, link = %d, roam = %d 4way = %d!!!\n",
+			    scan, link, roam, under_4way);
+		BTC_TRACE(trace_buf);
+		coex_sta->is_wifi_linkscan_process = TRUE;
+	} else {
+		coex_sta->is_wifi_linkscan_process = FALSE;
+	}
+
+	/* update wifi_link_info variable */
+	halbtc8821c1ant_update_wifi_link_info(btc, reason);
+
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+		    "[BTCoex], RunCoexistMechanism()===> reason = %d\n",
+		    reason);
+	BTC_TRACE(trace_buf);
+
+	if (btc->manual_control) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], RunCoexistMechanism(), return for Manual CTRL <===\n");
+		BTC_TRACE(trace_buf);
+		return;
+	}
+
+	if (btc->stop_coex_dm) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], RunCoexistMechanism(), return for Stop Coex DM <===\n");
+		BTC_TRACE(trace_buf);
+		return;
+	}
+
+	if (coex_sta->under_ips) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], RunCoexistMechanism(), return for wifi is under IPS !!!\n");
+		BTC_TRACE(trace_buf);
+		return;
+	}
+
+	if (coex_sta->under_lps && wifi_32k) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], RunCoexistMechanism(), return for wifi is under LPS-32K !!!\n");
+		BTC_TRACE(trace_buf);
+		return;
+	}
+
+	if (!coex_sta->run_time_state) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], return for run_time_state = FALSE !!!\n");
+		BTC_TRACE(trace_buf);
+		return;
+	}
+
+	if (coex_sta->freeze_coexrun_by_btinfo && !coex_sta->is_setup_link) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], return for freeze_coexrun_by_btinfo\n");
+		BTC_TRACE(trace_buf);
+		return;
+	}
+
+	coex_sta->coex_run_cnt++;
+
+	if (coex_sta->msft_mr_exist && wifi_connected) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], RunCoexistMechanism(), microsoft MR!!\n");
+		BTC_TRACE(trace_buf);
+
+		coex_sta->wl_coex_mode = BT_8821C_1ANT_WLINK_BTMR;
+		halbtc8821c1ant_action_bt_mr(btc);
+		return;
+	}
+
+	if (wifi_link_info_ext->is_all_under_5g) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], WiFi is under 5G!!!\n");
+		BTC_TRACE(trace_buf);
+
+		coex_sta->wl_coex_mode = BT_8821C_1ANT_WLINK_5G;
+		halbtc8821c1ant_action_wifi_under5g(btc);
+		return;
+	}
+
+	if (wifi_link_info_ext->is_mcc_25g) { /* not iclude scan action */
+
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], WiFi is under mcc dual-band!!!\n");
+		BTC_TRACE(trace_buf);
+
+		coex_sta->wl_coex_mode = BT_8821C_1ANT_WLINK_25GMPORT;
+		halbtc8821c1ant_action_wifi_multiport25g(btc);
+		return;
+	}
+
+	if (wifi_link_info_ext->num_of_active_port > 1 ||
+	    (btc->wifi_link_info.link_mode == BTC_LINK_ONLY_GO &&
+	    !btc->wifi_link_info.bhotspot &&
+	    btc->wifi_link_info.bany_client_join_go)) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				"[BTCoex], WiFi is under scc-2g/mcc-2g/p2pGO-only!!!\n");
+		BTC_TRACE(trace_buf);
+
+		if (btc->wifi_link_info.link_mode ==
+							BTC_LINK_ONLY_GO)
+			coex_sta->wl_coex_mode = BT_8821C_1ANT_WLINK_2GGO;
+		else
+			coex_sta->wl_coex_mode = BT_8821C_1ANT_WLINK_2GMPORT;
+		halbtc8821c1ant_action_wifi_multiport2g(btc);
+		return;
+	}
+
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+		    "[BTCoex], WiFi is single-port 2G!!!\n");
+	BTC_TRACE(trace_buf);
+
+	coex_sta->wl_coex_mode = BT_8821C_1ANT_WLINK_2G1PORT;
+
+	halbtc8821c1ant_set_ant_path(btc, BTC_ANT_PATH_AUTO, NM_EXCU,
+				     BT_8821C_1ANT_PHASE_2G);
+
+	halbtc8821c1ant_write_scbd(btc, BT_8821C_1ANT_SCBD_BTCQDDR, TRUE);
+
+	if (coex_sta->bt_disabled) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], BT is disabled !!!\n");
+		BTC_TRACE(trace_buf);
+		halbtc8821c1ant_action_wifi_only(btc);
+		return;
+	}
+
+	if (coex_sta->under_lps && !coex_sta->force_lps_ctrl &&
+	    !coex_sta->acl_busy) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], RunCoexistMechanism(), wifi is under LPS !!!\n");
+		BTC_TRACE(trace_buf);
+		halbtc8821c1ant_action_wifi_native_lps(btc);
+		return;
+	}
+
+	if (coex_sta->bt_whck_test) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], BT is under WHCK TEST!!!\n");
+		BTC_TRACE(trace_buf);
+		halbtc8821c1ant_action_bt_whql_test(btc);
+		return;
+	}
+
+	if (coex_sta->is_setup_link || coex_sta->bt_relink_downcount != 0) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], BT is re-link !!!\n");
+		BTC_TRACE(trace_buf);
+		halbtc8821c1ant_action_bt_relink(btc);
+		return;
+	}
+
+	if (coex_sta->c2h_bt_inquiry_page) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], BT is under inquiry/page scan !!\n");
+		BTC_TRACE(trace_buf);
+		halbtc8821c1ant_action_bt_inquiry(btc);
+		return;
+	}
+
+	if (coex_dm->bt_status == BT_8821C_1ANT_BSTATUS_NCON_IDLE ||
+	    coex_dm->bt_status == BT_8821C_1ANT_BSTATUS_CON_IDLE) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				"############# [BTCoex],  BT Is idle\n");
+		BTC_TRACE(trace_buf);
+		halbtc8821c1ant_action_bt_idle(btc);
+		return;
+	}
+
+	if (coex_sta->is_wifi_linkscan_process) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], wifi is under linkscan process!!\n");
+		BTC_TRACE(trace_buf);
+		halbtc8821c1ant_action_wifi_linkscan(btc);
+		return;
+	}
+
+	if (wifi_connected) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], wifi is under connected!!\n");
+		BTC_TRACE(trace_buf);
+
+		halbtc8821c1ant_action_wifi_connected(btc);
+	} else {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], wifi is under not-connected!!\n");
+		BTC_TRACE(trace_buf);
+
+		halbtc8821c1ant_action_wifi_not_connected(btc);
+	}
+}
+
+static
+void halbtc8821c1ant_init_coex_dm(struct btc_coexist *btc)
+{
+	struct coex_sta_8821c_1ant *coex_sta = &btc->coex_sta_8821c_1ant;
+	struct coex_dm_8821c_1ant *coex_dm = &btc->coex_dm_8821c_1ant;
+
+	/* force to reset coex mechanism */
+	halbtc8821c1ant_low_penalty_ra(btc, FC_EXCU, FALSE, 0);
+
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+		    "[BTCoex], Coex Mechanism Init!!\n");
+	BTC_TRACE(trace_buf);
+
+	coex_sta->pop_event_cnt = 0;
+	coex_sta->cnt_remote_name_req = 0;
+	coex_sta->cnt_reinit = 0;
+	coex_sta->cnt_setup_link = 0;
+	coex_sta->cnt_ign_wlan_act = 0;
+	coex_sta->cnt_page = 0;
+	coex_sta->cnt_role_switch = 0;
+	coex_sta->switch_band_notify_to = BTC_NOT_SWITCH;
+	coex_dm->setting_tdma = FALSE;
+
+	halbtc8821c1ant_query_bt_info(btc);
+}
+
+static
+void halbtc8821c1ant_init_hw_config(struct btc_coexist *btc, boolean back_up,
+				    boolean wifi_only)
+{
+	struct coex_sta_8821c_1ant *coex_sta = &btc->coex_sta_8821c_1ant;
+	u32 u32tmp1 = 0, u32tmp2 = 0, u32tmp3 = 0;
+	u16 u16tmp1 = 0;
+	u8 i;
+	struct  btc_board_info *board_info = &btc->board_info;
+
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+		    "[BTCoex], 1Ant Init HW Config!!\n");
+	BTC_TRACE(trace_buf);
+
+	u32tmp3 = btc->btc_read_4byte(btc, 0xcb4);
+	u32tmp1 = halbtc8821c1ant_read_indirect_reg(btc, 0x38);
+	u32tmp2 = halbtc8821c1ant_read_indirect_reg(btc, 0x54);
+
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+		    "[BTCoex],(Before Init HW config) 0xcb4 = 0x%x, 0x38= 0x%x, 0x54= 0x%x\n",
+		    u32tmp3, u32tmp1, u32tmp2);
+	BTC_TRACE(trace_buf);
+
+#if 0
+	coex_sta->bt_coex_supported_feature = 0;
+	coex_sta->bt_coex_supported_version = 0;
+	coex_sta->bt_ble_scan_type = 0;
+	coex_sta->bt_ble_scan_para[0] = 0;
+	coex_sta->bt_ble_scan_para[1] = 0;
+	coex_sta->bt_ble_scan_para[2] = 0;
+#endif
+	coex_sta->bt_reg_vendor_ac = 0xffff;
+	coex_sta->bt_reg_vendor_ae = 0xffff;
+	coex_sta->isolation_btween_wb = BT_8821C_1ANT_DEFAULT_ISOLATION;
+	coex_sta->gnt_error_cnt = 0;
+	coex_sta->bt_relink_downcount = 0;
+	coex_sta->is_set_ps_state_fail = FALSE;
+	coex_sta->cnt_set_ps_state_fail = 0;
+	coex_sta->wl_rx_rate = BTC_UNKNOWN;
+	coex_sta->wl_rts_rx_rate = BTC_UNKNOWN;
+	coex_sta->wl_center_channel = 0;
+	coex_sta->coex_run_cnt = 0;
+
+	for (i = 0; i <= 9; i++)
+		coex_sta->bt_afh_map[i] = 0;
+
+	/* Setup RF front end type */
+	halbtc8821c1ant_set_rfe_type(btc);
+
+	/* 0xf0[15:12] --> Chip Cut information */
+	coex_sta->cut_version = (btc->btc_read_1byte(btc, 0xf1) & 0xf0) >> 4;
+
+	 /* enable TBTT nterrupt */
+	btc->btc_write_1byte_bitmask(btc, 0x550, 0x8, 0x1);
+
+	/* BT report packet sample rate	 */
+	btc->btc_write_1byte(btc, 0x790, 0x5);
+
+	/* Init 0x778 = 0x1 for 1-Ant */
+	btc->btc_write_1byte(btc, 0x778, 0x1);
+
+	/* Enable PTA (3-wire function form BT side) */
+	btc->btc_write_1byte_bitmask(btc, 0x40, 0x20, 0x1);
+	btc->btc_write_1byte_bitmask(btc, 0x41, 0x02, 0x1);
+
+	/* Enable PTA (tx/rx signal form WiFi side) */
+	btc->btc_write_1byte_bitmask(btc, 0x4c6, 0x10, 0x1);
+
+	/* set GNT_BT=1 for coex table select both */
+	btc->btc_write_1byte_bitmask(btc, 0x763, 0x10, 0x1);
+
+	halbtc8821c1ant_enable_gnt_to_gpio(btc, TRUE);
+
+#if 0
+	/* check if WL firmware download ok */
+	/*if (btc->btc_read_1byte(btc, 0x80) == 0xc6)*/
+	 halbtc8821c1ant_write_scbd(btc, BT_8821C_1ANT_SCBD_ONOFF, TRUE);
+#endif
+
+	/* PTA parameter */
+	halbtc8821c1ant_table(btc, FC_EXCU, 0);
+	halbtc8821c1ant_tdma(btc, FC_EXCU, FALSE, 8);
+
+	/* Antenna config */
+	if (coex_sta->is_rf_state_off) {
+		halbtc8821c1ant_set_ant_path(btc, BTC_ANT_PATH_AUTO, FC_EXCU,
+					     BT_8821C_1ANT_PHASE_WOFF);
+
+		btc->stop_coex_dm = TRUE;
+
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], **********  %s (RF Off)**********\n",
+			    __func__);
+		BTC_TRACE(trace_buf);
+	} else if (wifi_only) {
+		coex_sta->concurrent_rx_mode_on = FALSE;
+		halbtc8821c1ant_set_ant_path(btc, BTC_ANT_PATH_WIFI, FC_EXCU,
+					     BT_8821C_1ANT_PHASE_WONLY);
+
+		btc->stop_coex_dm = TRUE;
+	} else {
+		/*Set BT polluted packet on for Tx rate adaptive not including Tx retry break by PTA, 0x45c[19] =1 */
+		btc->btc_write_1byte_bitmask(btc, 0x45e, 0x8, 0x1);
+
+		coex_sta->concurrent_rx_mode_on = TRUE;
+		btc->btc_set_rf_reg(btc, BTC_RF_A, 0x1, 0x2, 0x0);
+
+		halbtc8821c1ant_set_ant_path(btc, BTC_ANT_PATH_AUTO, FC_EXCU,
+					     BT_8821C_1ANT_PHASE_INIT);
+
+		btc->stop_coex_dm = FALSE;
+	}
+
+	u32tmp3 = btc->btc_read_4byte(btc, 0xcb4);
+	u32tmp1 = halbtc8821c1ant_read_indirect_reg(btc, 0x38);
+	u32tmp2 = halbtc8821c1ant_read_indirect_reg(btc, 0x54);
+
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+		    "[BTCoex], (After Init HW config) 0xcb4 = 0x%x, 0x38= 0x%x, 0x54= 0x%x\n",
+		    u32tmp3, u32tmp1, u32tmp2);
+	BTC_TRACE(trace_buf);
+}
+
+
+/* ************************************************************
+ * work around function start with wa_halbtc8821c1ant_
+ * ************************************************************
+ * ************************************************************
+ * extern function start with ex_halbtc8821c1ant_
+ * ************************************************************ */
+void ex_halbtc8821c1ant_power_on_setting(struct btc_coexist *btc)
+{
+	struct coex_sta_8821c_1ant *coex_sta = &btc->coex_sta_8821c_1ant;
+	struct  btc_board_info	*board_info = &btc->board_info;
+	u8 u8tmp = 0x0;
+	u16 u16tmp = 0x0;
+	u32 value = 0;
+
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+		    "[BTCoex], Execute %s !!\n", __func__);
+	BTC_TRACE(trace_buf);
+
+	btc->stop_coex_dm = TRUE;
+	coex_sta->is_rf_state_off = FALSE;
+
+	/* enable BB, REG_SYS_FUNC_EN such that we can write BB Register correctly. */
+	u16tmp = btc->btc_read_2byte(btc, 0x2);
+	btc->btc_write_2byte(btc, 0x2, u16tmp | BIT(0) | BIT(1));
+
+	/* Local setting bit define
+	 *	BIT0: "0" for no antenna inverse; "1" for antenna inverse
+	 *	BIT1: "0" for internal switch; "1" for external switch
+	 *	BIT2: "0" for one antenna; "1" for two antenna
+	 * NOTE: here default all internal switch
+	 * and 1-antenna ==> BIT1=0 and BIT2=0
+	 */
+
+	/* Set Antenna Path to BT side */
+	/* Check efuse 0xc3[6] for Single Antenna Path */
+	if (board_info->single_ant_path == 0) {
+		board_info->btdm_ant_pos = BTC_ANTENNA_AT_AUX_PORT;
+		u8tmp = 1;
+	} else if (board_info->single_ant_path == 1) {
+		board_info->btdm_ant_pos = BTC_ANTENNA_AT_MAIN_PORT;
+		u8tmp = 0;
+	}
+
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+		    "[BTCoex], (Power On) single_ant_path  = %d, btdm_ant_pos = %d\n",
+		    board_info->single_ant_path , board_info->btdm_ant_pos);
+	BTC_TRACE(trace_buf);
+
+	/* Setup RF front end type */
+	halbtc8821c1ant_set_rfe_type(btc);
+
+	/* Set Antenna Path to BT side */
+	halbtc8821c1ant_set_ant_path(btc, BTC_ANT_PATH_AUTO, FC_EXCU,
+				     BT_8821C_1ANT_PHASE_POWERON);
+
+	/* Save"single antenna position" info in Local register setting for
+	 * FW reading, because FW may not ready at  power on
+	 */
+	if (btc->chip_interface == BTC_INTF_PCI)
+		btc->btc_write_local_reg_1byte(btc, 0x3e0, u8tmp);
+	else if (btc->chip_interface == BTC_INTF_USB)
+		btc->btc_write_local_reg_1byte(btc, 0xfe08, u8tmp);
+	else if (btc->chip_interface == BTC_INTF_SDIO)
+		btc->btc_write_local_reg_1byte(btc, 0x60, u8tmp);
+
+	/* enable GNT_WL/GNT_BT debug signal to GPIO14/15 */
+	halbtc8821c1ant_enable_gnt_to_gpio(btc, TRUE);
+
+	if (btc->dbg_mode) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], LTE coex Reg 0x38 (Power-On) = 0x%x\n",
+			    halbtc8821c1ant_read_indirect_reg(btc, 0x38));
+		BTC_TRACE(trace_buf);
+
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], MACReg 0x70/ BBReg 0xcb4 (Power-On) = 0x%x/ 0x%x\n",
+			    btc->btc_read_4byte(btc, 0x70),
+			    btc->btc_read_4byte(btc, 0xcb4));
+		BTC_TRACE(trace_buf);
+	}
+}
+
+void ex_halbtc8821c1ant_pre_load_firmware(struct btc_coexist *btc)
+{
+}
+
+void ex_halbtc8821c1ant_init_hw_config(struct btc_coexist *btc,
+				       boolean wifi_only)
+{
+	halbtc8821c1ant_init_hw_config(btc, TRUE, wifi_only);
+}
+
+void ex_halbtc8821c1ant_init_coex_dm(struct btc_coexist *btc)
+{
+	btc->stop_coex_dm = FALSE;
+	btc->auto_report = TRUE;
+	btc->dbg_mode = FALSE;
+	halbtc8821c1ant_init_coex_dm(btc);
+}
+
+void ex_halbtc8821c1ant_display_simple_coex_info(struct btc_coexist *btc)
+{
+	struct coex_sta_8821c_1ant *coex_sta = &btc->coex_sta_8821c_1ant;
+	struct coex_dm_8821c_1ant *coex_dm = &btc->coex_dm_8821c_1ant;
+	struct btc_board_info *board_info = &btc->board_info;
+	struct btc_bt_link_info *bt_link_info = &btc->bt_link_info;
+
+	u8 *cli_buf = btc->cli_buf;
+	u32 bt_patch_ver = 0, bt_coex_ver = 0;
+	static u8	cnt;
+	u8 * const p = &coex_sta->bt_afh_map[0];
+
+	if (!coex_sta->bt_disabled &&
+	    (coex_sta->bt_coex_supported_version == 0 ||
+	    coex_sta->bt_coex_supported_version == 0xffff) &&
+	    cnt == 0) {
+		btc->btc_get(btc, BTC_GET_U4_SUPPORTED_FEATURE,
+			     &coex_sta->bt_coex_supported_feature);
+
+		btc->btc_get(btc, BTC_GET_U4_SUPPORTED_VERSION,
+			     &coex_sta->bt_coex_supported_version);
+
+		coex_sta->bt_reg_vendor_ac = (u16)(btc->btc_get_bt_reg(btc, 3,
+								       0xac) &
+						   0xffff);
+
+		coex_sta->bt_reg_vendor_ae = (u16)(btc->btc_get_bt_reg(btc, 3,
+								       0xae) &
+						   0xffff);
+
+		btc->btc_get(btc, BTC_GET_U4_BT_PATCH_VER, &bt_patch_ver);
+		btc->bt_info.bt_get_fw_ver = bt_patch_ver;
+
+		if (coex_sta->num_of_profile > 0)
+			btc->btc_get_bt_afh_map_from_bt(btc, 0, p);
+	}
+
+	if (++cnt >= 3)
+		cnt = 0;
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+		   "\r\n _____[BT Coexist info]____");
+	CL_PRINTF(cli_buf);
+
+	if (btc->manual_control) {
+		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+			   "\r\n __[Under Manual Control]_");
+	CL_PRINTF(cli_buf);
+		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+			   "\r\n _________________________");
+		CL_PRINTF(cli_buf);
+	}
+
+	if (btc->stop_coex_dm) {
+		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+			   "\r\n ____[Coex is STOPPED]____");
+		CL_PRINTF(cli_buf);
+		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+			   "\r\n _________________________");
+		CL_PRINTF(cli_buf);
+	}
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+		   "\r\n %-35s = %d/ %d/ %s / 0x%x",
+		   "Ant PG Num/ Mech/ Pos/ RFE",
+		   board_info->pg_ant_num, board_info->btdm_ant_num,
+		   (board_info->btdm_ant_pos == BTC_ANTENNA_AT_MAIN_PORT
+		    ? "Main" : "Aux"),
+		   board_info->rfe_type);
+	CL_PRINTF(cli_buf);
+
+	bt_coex_ver = ((coex_sta->bt_coex_supported_version & 0xff00) >> 8);
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+		   "\r\n %-35s = %d_%02x/ 0x%02x/ 0x%02x (%s)",
+		   "CoexVer WL/  BT_Desired/ BT_Report",
+		   glcoex_ver_date_8821c_1ant, glcoex_ver_8821c_1ant,
+		   glcoex_ver_btdesired_8821c_1ant,
+		   bt_coex_ver,
+		   (bt_coex_ver == 0xff ? "Unknown" :
+		   (coex_sta->bt_disabled ? "BT-disable" :
+		   (bt_coex_ver >= glcoex_ver_btdesired_8821c_1ant ?
+		   "Match" : "Mis-Match"))));
+	CL_PRINTF(cli_buf);
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s ", "BT status",
+		   ((coex_sta->bt_disabled) ? ("disabled") :
+		   ((coex_sta->c2h_bt_inquiry_page) ? ("inquiry/page")
+		    : ((BT_8821C_1ANT_BSTATUS_NCON_IDLE ==
+		    coex_dm->bt_status) ? "non-connected idle" :
+		    ((BT_8821C_1ANT_BSTATUS_CON_IDLE ==
+		    coex_dm->bt_status) ? "connected-idle" : "busy")))));
+	CL_PRINTF(cli_buf);
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d",
+		   "0x770(Hi-pri rx/tx)",
+		   coex_sta->high_priority_rx, coex_sta->high_priority_tx);
+	CL_PRINTF(cli_buf);
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d %s",
+		   "0x774(Lo-pri rx/tx)",
+		   coex_sta->low_priority_rx, coex_sta->low_priority_tx,
+		   (bt_link_info->slave_role ? "(Slave!!)" :
+		   (coex_sta->is_tdma_btautoslot_hang ?
+		   "(auto-slot hang!!)" : "")));
+	CL_PRINTF(cli_buf);
+}
+
+void ex_halbtc8821c1ant_display_coex_info(struct btc_coexist *btc)
+{
+	struct coex_sta_8821c_1ant *coex_sta = &btc->coex_sta_8821c_1ant;
+	struct coex_dm_8821c_1ant *coex_dm = &btc->coex_dm_8821c_1ant;
+	struct  btc_board_info *board_info = &btc->board_info;
+	struct  btc_bt_link_info *bt_link_info = &btc->bt_link_info;
+
+	u8 *cli_buf = btc->cli_buf;
+	u8 u8tmp[4], i, bt_info_ext, ps_tdma_case = 0;
+	u16 u16tmp[4];
+	u32 u32tmp[4];
+	u32 fa_ofdm, fa_cck, cca_ofdm, cca_cck;
+	u32 fw_ver = 0, bt_patch_ver = 0, bt_coex_ver = 0;
+	static u8	pop_report_in_10s;
+	u32 phyver = 0;
+	boolean	lte_coex_on = FALSE;
+	static u8 cnt;
+	u8 * const p = &coex_sta->bt_afh_map[0];
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+		   "\r\n ============[BT Coexist info 8821C]============");
+	CL_PRINTF(cli_buf);
+
+	if (btc->manual_control) {
+		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+			   "\r\n ============[Under Manual Control]============");
+		CL_PRINTF(cli_buf);
+		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+			   "\r\n ==========================================");
+		CL_PRINTF(cli_buf);
+	} else if (btc->stop_coex_dm) {
+		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+			   "\r\n ============[Coex is STOPPED]============");
+		CL_PRINTF(cli_buf);
+		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+			   "\r\n ==========================================");
+		CL_PRINTF(cli_buf);
+	} else if (!coex_sta->run_time_state) {
+		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+			   "\r\n ============[Run Time State = False]============");
+		CL_PRINTF(cli_buf);
+		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+			   "\r\n ==========================================");
+		CL_PRINTF(cli_buf);
+	} else if (coex_sta->freeze_coexrun_by_btinfo) {
+		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+			   "\r\n ============[freeze_coexrun_by_btinfo]============");
+		CL_PRINTF(cli_buf);
+		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+			   "\r\n ==========================================");
+		CL_PRINTF(cli_buf);
+	}
+
+	if (!coex_sta->bt_disabled &&
+	    (coex_sta->bt_coex_supported_version == 0 ||
+	    coex_sta->bt_coex_supported_version == 0xffff) &&
+	    cnt == 0) {
+		btc->btc_get(btc, BTC_GET_U4_SUPPORTED_FEATURE,
+			     &coex_sta->bt_coex_supported_feature);
+
+		btc->btc_get(btc, BTC_GET_U4_SUPPORTED_VERSION,
+			     &coex_sta->bt_coex_supported_version);
+
+		coex_sta->bt_reg_vendor_ac = (u16)(btc->btc_get_bt_reg(btc, 3,
+								       0xac) &
+						   0xffff);
+
+		coex_sta->bt_reg_vendor_ae = (u16)(btc->btc_get_bt_reg(btc, 3,
+								       0xae) &
+						   0xffff);
+
+		btc->btc_get(btc, BTC_GET_U4_BT_PATCH_VER, &bt_patch_ver);
+		btc->bt_info.bt_get_fw_ver = bt_patch_ver;
+
+		if (coex_sta->num_of_profile > 0)
+			btc->btc_get_bt_afh_map_from_bt(btc, 0, p);
+	}
+
+	if (++cnt >= 3)
+		cnt = 0;
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+		   "\r\n %-35s = %d/ %s/ %s / 0x%x",
+		   "Ant PG Num/ Mech/ Pos/ RFE",
+		   board_info->pg_ant_num,
+		   (board_info->btdm_ant_num == 1 ? "Shared" : "Non-Shared"),
+		   (board_info->btdm_ant_pos == BTC_ANTENNA_AT_MAIN_PORT
+		    ? "Main" : "Aux"),
+		   board_info->rfe_type);
+	CL_PRINTF(cli_buf);
+
+	bt_patch_ver = btc->bt_info.bt_get_fw_ver;
+	btc->btc_get(btc, BTC_GET_U4_WIFI_FW_VER, &fw_ver);
+	phyver = btc->btc_get_bt_phydm_version(btc);
+	bt_coex_ver = ((coex_sta->bt_coex_supported_version & 0xff00) >> 8);
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+		   "\r\n %-35s = %d_%02x/ 0x%02x/ 0x%02x (%s)",
+		   "CoexVer WL/  BT_Desired/ BT_Report",
+		   glcoex_ver_date_8821c_1ant, glcoex_ver_8821c_1ant,
+		   glcoex_ver_btdesired_8821c_1ant,
+		   bt_coex_ver,
+		   (bt_coex_ver == 0xff ? "Unknown" :
+		    (coex_sta->bt_disabled ? "BT-disable" :
+		     (bt_coex_ver >= glcoex_ver_btdesired_8821c_1ant ?
+		      "Match" : "Mis-Match"))));
+	CL_PRINTF(cli_buf);
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+		   "\r\n %-35s = 0x%x/ 0x%x/ v%d/ %c",
+		   "W_FW/ B_FW/ Phy/ Kt",
+		   fw_ver, bt_patch_ver, phyver,
+		   coex_sta->cut_version + 65);
+	CL_PRINTF(cli_buf);
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+		   "\r\n %-35s = %02x %02x %02x (RF-Ch = %d)",
+		   "AFH Map to BT",
+		   coex_dm->wifi_chnl_info[0], coex_dm->wifi_chnl_info[1],
+		   coex_dm->wifi_chnl_info[2], coex_sta->wl_center_channel);
+	CL_PRINTF(cli_buf);
+
+	/* wifi status */
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s",
+		   "============[Wifi Status]============");
+	CL_PRINTF(cli_buf);
+	btc->btc_disp_dbg_msg(btc, BTC_DBG_DISP_WIFI_STATUS);
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s",
+		   "============[BT Status]============");
+	CL_PRINTF(cli_buf);
+
+	pop_report_in_10s++;
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+			"\r\n %-35s = %s/ %ddBm/ %d/ %d",
+			"BT status/ rssi/ retryCnt/ popCnt",
+			((coex_sta->bt_disabled) ? ("disabled") :
+			((coex_sta->c2h_bt_inquiry_page) ? ("inquiry-page") :
+			((coex_dm->bt_status == BT_8821C_1ANT_BSTATUS_NCON_IDLE)
+			? "non-connected-idle" :
+			((coex_dm->bt_status == BT_8821C_1ANT_BSTATUS_CON_IDLE)
+			? "connected-idle" : "busy")))),
+			coex_sta->bt_rssi - 100, coex_sta->bt_retry_cnt,
+			coex_sta->pop_event_cnt);
+	CL_PRINTF(cli_buf);
+
+	if (pop_report_in_10s >= 5) {
+		coex_sta->pop_event_cnt = 0;
+		pop_report_in_10s = 0;
+	}
+
+	if (coex_sta->num_of_profile != 0)
+		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+			   "\r\n %-35s = %s%s%s%s%s%s (multilink = %d)",
+			   "Profiles", ((bt_link_info->a2dp_exist) ?
+						((coex_sta->is_bt_a2dp_sink) ?
+							 "A2DP sink," :
+							 "A2DP,") :
+						""),
+			   ((bt_link_info->sco_exist) ? "HFP," : ""),
+			   ((bt_link_info->hid_exist) ?
+				    ((coex_sta->is_hid_rcu) ?
+					     "HID(RCU)" :
+					     ((coex_sta->hid_busy_num >= 2) ?
+						      "HID(4/18)," :
+						      "HID(2/18),")) :
+				    ""),
+			   ((bt_link_info->pan_exist) ?
+				    ((coex_sta->is_bt_opp_exist) ? "OPP," :
+								   "PAN,") :
+				    ""),
+			   ((coex_sta->voice_over_HOGP) ? "Voice," : ""),
+			   ((coex_sta->msft_mr_exist) ? "MR" : ""),
+			   coex_sta->is_bt_multi_link);
+	else
+		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s",
+			   "Profiles",
+			   (coex_sta->msft_mr_exist) ? "MR" : "None");
+
+	CL_PRINTF(cli_buf);
+
+	if (bt_link_info->a2dp_exist) {
+		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s/ %d/ %s",
+			   "CQDDR/Bitpool/Auto_Slot",
+			   ((coex_sta->is_A2DP_3M) ? "On" : "Off"),
+			   coex_sta->a2dp_bit_pool,
+			   ((coex_sta->is_autoslot) ? "On" : "Off")
+			  );
+		CL_PRINTF(cli_buf);
+
+		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+			   "\r\n %-35s = 0x%x/ 0x%x/ %d/ %d",
+			   "V_ID/D_name/FBSlot_Legacy/FBSlot_Le",
+			   coex_sta->bt_a2dp_vendor_id,
+			   coex_sta->bt_a2dp_device_name,
+			   coex_sta->legacy_forbidden_slot,
+			   coex_sta->le_forbidden_slot
+			  );
+		CL_PRINTF(cli_buf);
+	}
+
+	if (bt_link_info->hid_exist) {
+		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d",
+			   "HID PairNum",
+			   coex_sta->hid_pair_cnt);
+		CL_PRINTF(cli_buf);
+	}
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s/ %d/ %s/ 0x%x",
+		   "Role/RoleSwCnt/IgnWlact/Feature",
+		   (bt_link_info->slave_role ? "Slave" : "Master"),
+		   coex_sta->cnt_role_switch,
+		   (coex_dm->cur_ignore_wlan_act ? "Yes" : "No"),
+		   coex_sta->bt_coex_supported_feature);
+	CL_PRINTF(cli_buf);
+
+	if (coex_sta->is_ble_scan_en) {
+		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+			   "\r\n %-35s = 0x%x/ 0x%x/ 0x%x/ 0x%x",
+			   "BLEScan Type/TV/Init/Ble",
+			   coex_sta->bt_ble_scan_type,
+			   (coex_sta->bt_ble_scan_type & 0x1 ?
+			   coex_sta->bt_ble_scan_para[0] : 0x0),
+			   (coex_sta->bt_ble_scan_type & 0x2 ?
+			   coex_sta->bt_ble_scan_para[1] : 0x0),
+			   (coex_sta->bt_ble_scan_type & 0x4 ?
+			   coex_sta->bt_ble_scan_para[2] : 0x0));
+		CL_PRINTF(cli_buf);
+	}
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+		   "\r\n %-35s = %d/ %d/ %d/ %d/ %d %s",
+		   "ReInit/ReLink/IgnWlact/Page/NameReq",
+		   coex_sta->cnt_reinit,
+		   coex_sta->cnt_setup_link,
+		   coex_sta->cnt_ign_wlan_act,
+		   coex_sta->cnt_page,
+		   coex_sta->cnt_remote_name_req,
+		   (coex_sta->is_setup_link ? "(Relink!!)" : ""));
+	CL_PRINTF(cli_buf);
+
+	halbtc8821c1ant_read_scbd(btc,	&u16tmp[0]);
+
+	if (coex_sta->bt_reg_vendor_ae == 0xffff ||
+	    coex_sta->bt_reg_vendor_ac == 0xffff)
+		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+			   "\r\n %-35s = x/ x/ 0x%04x",
+			   "0xae[4]/0xac[1:0]/ScBd(B->W)", u16tmp[0]);
+	else
+		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+			   "\r\n %-35s = 0x%x/ 0x%x/ 0x%04x",
+			   "0xae[4]/0xac[1:0]/ScBd(B->W)",
+			   (int)((coex_sta->bt_reg_vendor_ae & BIT(4)) >> 4),
+			   coex_sta->bt_reg_vendor_ac & 0x3, u16tmp[0]);
+	CL_PRINTF(cli_buf);
+
+	if (coex_sta->num_of_profile > 0) {
+		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+			   "\r\n %-35s = %02x%02x%02x%02x %02x%02x%02x%02x %02x%02x",
+			   "AFH MAP",
+			   coex_sta->bt_afh_map[0],
+			   coex_sta->bt_afh_map[1],
+			   coex_sta->bt_afh_map[2],
+			   coex_sta->bt_afh_map[3],
+			   coex_sta->bt_afh_map[4],
+			   coex_sta->bt_afh_map[5],
+			   coex_sta->bt_afh_map[6],
+			   coex_sta->bt_afh_map[7],
+			   coex_sta->bt_afh_map[8],
+			   coex_sta->bt_afh_map[9]);
+		CL_PRINTF(cli_buf);
+	}
+
+	for (i = 0; i < BT_8821C_1ANT_INFO_SRC_MAX; i++) {
+		if (coex_sta->bt_info_c2h_cnt[i]) {
+			CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+				   "\r\n %-35s = %02x %02x %02x %02x %02x %02x %02x (%d)",
+				   glbt_info_src_8821c_1ant[i],
+				   coex_sta->bt_info_c2h[i][0],
+				   coex_sta->bt_info_c2h[i][1],
+				   coex_sta->bt_info_c2h[i][2],
+				   coex_sta->bt_info_c2h[i][3],
+				   coex_sta->bt_info_c2h[i][4],
+				   coex_sta->bt_info_c2h[i][5],
+				   coex_sta->bt_info_c2h[i][6],
+				   coex_sta->bt_info_c2h_cnt[i]);
+			CL_PRINTF(cli_buf);
+		}
+	}
+
+
+	if (btc->manual_control)
+		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s",
+			"============[mechanisms] (before Manual)============");
+	else
+		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s",
+			   "============[Mechanisms]============");
+
+	CL_PRINTF(cli_buf);
+
+	ps_tdma_case = coex_dm->cur_ps_tdma;
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+		   "\r\n %-35s = %02x %02x %02x %02x %02x (case-%d, %s)",
+		   "TDMA",
+		   coex_dm->ps_tdma_para[0], coex_dm->ps_tdma_para[1],
+		   coex_dm->ps_tdma_para[2], coex_dm->ps_tdma_para[3],
+		   coex_dm->ps_tdma_para[4], ps_tdma_case,
+		   (coex_dm->cur_ps_tdma_on ? "TDMA-On" : "TDMA-Off"));
+	CL_PRINTF(cli_buf);
+
+	switch (coex_sta->wl_coex_mode) {
+	case BT_8821C_1ANT_WLINK_2G1PORT:
+	default:
+		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+			   "\r\n %-35s = %s", "Coex_Mode", "2G-SP");
+		break;
+	case BT_8821C_1ANT_WLINK_2GMPORT:
+		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+			   "\r\n %-35s = %s", "Coex_Mode", "2G-MP");
+		break;
+	case BT_8821C_1ANT_WLINK_25GMPORT:
+		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+			   "\r\n %-35s = %s", "Coex_Mode", "25G-MP");
+		break;
+	case BT_8821C_1ANT_WLINK_5G:
+		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+			   "\r\n %-35s = %s", "Coex_Mode", "5G");
+		break;
+	case BT_8821C_1ANT_WLINK_2GGO:
+		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+			   "\r\n %-35s = %s", "Coex_Mode", "2G-P2P");
+		break;
+	case BT_8821C_1ANT_WLINK_BTMR:
+		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+			   "\r\n %-35s = %s", "Coex_Mode", "BT-MR");
+		break;
+	}
+	CL_PRINTF(cli_buf);
+
+	u32tmp[0] = btc->btc_read_4byte(btc, 0x6c0);
+	u32tmp[1] = btc->btc_read_4byte(btc, 0x6c4);
+	u32tmp[2] = btc->btc_read_4byte(btc, 0x6c8);
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+		   "\r\n %-35s = %d/ 0x%x/ 0x%x/ 0x%x",
+		   "Table/0x6c0/0x6c4/0x6c8",
+		   coex_sta->coex_table_type, u32tmp[0], u32tmp[1], u32tmp[2]);
+	CL_PRINTF(cli_buf);
+
+	u8tmp[0] = btc->btc_read_1byte(btc, 0x778);
+	u32tmp[0] = btc->btc_read_4byte(btc, 0x6cc);
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+		   "\r\n %-35s = 0x%x/ 0x%x/ 0x%04x/ %d",
+		   "0x778/0x6cc/ScBd(W->B)/RunCnt", u8tmp[0], u32tmp[0],
+		   coex_sta->score_board_WB, coex_sta->coex_run_cnt);
+	CL_PRINTF(cli_buf);
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s/ %s/ %s/ %d/ %d",
+		   "AntDiv/BtCtrlLPS/LPRA/PsFail/g_busy",
+		   (board_info->ant_div_cfg ? "On" : "Off"),
+		   (coex_sta->force_lps_ctrl ? "On" : "Off"),
+		   (coex_dm->cur_low_penalty_ra ? "On" : "Off"),
+		   coex_sta->cnt_set_ps_state_fail,
+		   coex_sta->gl_wifi_busy);
+	CL_PRINTF(cli_buf);
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d/ %d/ %d",
+		   "Null All/Retry/Ack/BT_Empty/BT_Late",
+		   coex_sta->wl_fw_dbg_info[1],
+		   coex_sta->wl_fw_dbg_info[2],
+		   coex_sta->wl_fw_dbg_info[3],
+		   coex_sta->wl_fw_dbg_info[4],
+		   coex_sta->wl_fw_dbg_info[5]);
+	CL_PRINTF(cli_buf);
+
+	u32tmp[0] = halbtc8821c1ant_read_indirect_reg(btc, 0x38);
+	lte_coex_on = ((u32tmp[0] & BIT(7)) >> 7) ?  TRUE : FALSE;
+
+	if (lte_coex_on) {
+		u32tmp[0] = halbtc8821c1ant_read_indirect_reg(btc, 0xa0);
+		u32tmp[1] = halbtc8821c1ant_read_indirect_reg(btc, 0xa4);
+
+		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x",
+			   "LTE Coex Table W_L/B_L", u32tmp[0] & 0xffff,
+			   u32tmp[1] & 0xffff);
+		CL_PRINTF(cli_buf);
+
+		u32tmp[0] = halbtc8821c1ant_read_indirect_reg(btc, 0xa8);
+		u32tmp[1] = halbtc8821c1ant_read_indirect_reg(btc, 0xac);
+		u32tmp[2] = halbtc8821c1ant_read_indirect_reg(btc, 0xb0);
+		u32tmp[3] = halbtc8821c1ant_read_indirect_reg(btc, 0xb4);
+
+		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+			   "\r\n %-35s = 0x%x/ 0x%x/ 0x%x/ 0x%x",
+			   "LTE Break Table W_L/B_L/L_W/L_B",
+			   u32tmp[0] & 0xffff, u32tmp[1] & 0xffff,
+			   u32tmp[2] & 0xffff, u32tmp[3] & 0xffff);
+		CL_PRINTF(cli_buf);
+	}
+
+	/* Hw setting		 */
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s",
+		   "============[Hw setting]============");
+	CL_PRINTF(cli_buf);
+
+	u32tmp[0] = halbtc8821c1ant_read_indirect_reg(btc, 0x38);
+	u32tmp[1] = halbtc8821c1ant_read_indirect_reg(btc, 0x54);
+	u8tmp[0] = btc->btc_read_1byte(btc, 0x73);
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s/ %s",
+		   "LTE Coex/Path Owner",
+		   ((lte_coex_on) ? "On" : "Off") ,
+		   ((u8tmp[0] & BIT(2)) ? "WL" : "BT"));
+	CL_PRINTF(cli_buf);
+
+	if (lte_coex_on) {
+		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+			   "\r\n %-35s = %d/ %d/ %d/ %d",
+			   "LTE 3Wire/OPMode/UART/UARTMode",
+			   (int)((u32tmp[0] & BIT(6)) >> 6),
+			   (int)((u32tmp[0] & (BIT(5) | BIT(4))) >> 4),
+			   (int)((u32tmp[0] & BIT(3)) >> 3),
+			   (int)(u32tmp[0] & (BIT(2) | BIT(1) | BIT(0))));
+		CL_PRINTF(cli_buf);
+
+		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d",
+			   "LTE_Busy/UART_Busy",
+			   (int)((u32tmp[1] & BIT(1)) >> 1),
+			   (int)(u32tmp[1] & BIT(0)));
+		CL_PRINTF(cli_buf);
+	}
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+		   "\r\n %-35s = %s (BB:%s)/ %s (BB:%s)/ %s (gnt_err = %d)",
+		   "GNT_WL_Ctrl/GNT_BT_Ctrl/Dbg",
+		   ((u32tmp[0] & BIT(12)) ? "SW" : "HW"),
+		   ((u32tmp[0] & BIT(8)) ?  "SW" : "HW"),
+		   ((u32tmp[0] & BIT(14)) ? "SW" : "HW"),
+		   ((u32tmp[0] & BIT(10)) ?  "SW" : "HW"),
+		   ((u8tmp[0] & BIT(3)) ? "On" : "Off"),
+		   coex_sta->gnt_error_cnt);
+	CL_PRINTF(cli_buf);
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ 0x%x",
+		   "GNT_WL/GNT_BT/ RF_0x1",
+		   (int)((u32tmp[1] & BIT(2)) >> 2),
+		   (int)((u32tmp[1] & BIT(3)) >> 3),
+		   btc->btc_get_rf_reg(btc, BTC_RF_A, 0x1, 0xfffff));
+	CL_PRINTF(cli_buf);
+
+
+	u32tmp[0] = btc->btc_read_4byte(btc, 0xcb0);
+	u32tmp[1] = btc->btc_read_4byte(btc, 0xcb4);
+	u8tmp[0] = btc->btc_read_1byte(btc, 0xcba);
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+		   "\r\n %-35s = 0x%04x/ 0x%04x/ 0x%02x %s",
+		   "0xcb0/0xcb4/0xcb8[23:16]",
+		   u32tmp[0], u32tmp[1], u8tmp[0],
+		   ((u8tmp[0] & 0x1) == 0x1 ?  "(BTG)" :   "(WL_A+G)"));
+	CL_PRINTF(cli_buf);
+
+	u32tmp[0] = btc->btc_read_4byte(btc, 0x4c);
+	u8tmp[2] = btc->btc_read_1byte(btc, 0x64);
+	u8tmp[0] = btc->btc_read_1byte(btc, 0x4c6);
+	u8tmp[1] = btc->btc_read_1byte(btc, 0x40);
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+		   "\r\n %-35s = 0x%x/ 0x%x/ 0x%x/ 0x%x",
+		   "4c[24:23]/64[0]/4c6[4]/40[5]",
+		   (int)(u32tmp[0] & (BIT(24) | BIT(23))) >> 23,
+		    u8tmp[2] & 0x1, (int)((u8tmp[0] & BIT(4)) >> 4),
+		   (int)((u8tmp[1] & BIT(5)) >> 5));
+	CL_PRINTF(cli_buf);
+
+	u32tmp[0] = btc->btc_read_4byte(btc, 0x550);
+	u8tmp[0] = btc->btc_read_1byte(btc, 0x522);
+	u8tmp[1] = btc->btc_read_1byte(btc, 0x953);
+	u8tmp[2] = btc->btc_read_1byte(btc, 0xc50);
+	u8tmp[3] = btc->btc_read_1byte(btc, 0x60a);
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+		   "\r\n %-35s = 0x%x/ 0x%x/ %s/ 0x%x/ 0x%x",
+		   "0x550/0x522/4-RxAGC/0xc50/0x60a",
+		   u32tmp[0], u8tmp[0], (u8tmp[1] & 0x2) ? "On" : "Off",
+		   u8tmp[2], u8tmp[3]);
+	CL_PRINTF(cli_buf);
+
+	fa_ofdm = btc->btc_phydm_query_PHY_counter(btc, PHYDM_INFO_FA_OFDM);
+	fa_cck = btc->btc_phydm_query_PHY_counter(btc, PHYDM_INFO_FA_CCK);
+	cca_ofdm = btc->btc_phydm_query_PHY_counter(btc, PHYDM_INFO_CCA_OFDM);
+	cca_cck = btc->btc_phydm_query_PHY_counter(btc, PHYDM_INFO_CCA_CCK);
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+		   "\r\n %-35s = 0x%x/ 0x%x/ 0x%x/ 0x%x",
+		   "CCK-CCA/CCK-FA/OFDM-CCA/OFDM-FA",
+		   cca_cck, fa_cck, cca_ofdm, fa_ofdm);
+	CL_PRINTF(cli_buf);
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d/ %d",
+		   "CRC_OK CCK/11g/11n/11ac",
+		   coex_sta->crc_ok_cck, coex_sta->crc_ok_11g,
+		   coex_sta->crc_ok_11n, coex_sta->crc_ok_11n_vht);
+	CL_PRINTF(cli_buf);
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d/ %d",
+		   "CRC_Err CCK/11g/11n/11ac",
+		   coex_sta->crc_err_cck, coex_sta->crc_err_11g,
+		   coex_sta->crc_err_11n, coex_sta->crc_err_11n_vht);
+	CL_PRINTF(cli_buf);
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+		   "\r\n %-35s = %d/ %d/ %s-%d/ %d (Tx macid: %d)",
+		   "Rate RxD/RxRTS/TxD/TxRetry_ratio",
+		   coex_sta->wl_rx_rate, coex_sta->wl_rts_rx_rate,
+		   (coex_sta->wl_tx_rate & 0x80 ? "SGI" : "LGI"),
+		   coex_sta->wl_tx_rate & 0x7f,
+		   coex_sta->wl_tx_retry_ratio,
+		   coex_sta->wl_tx_macid);
+	CL_PRINTF(cli_buf);
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s/ %s/ %s/ %s/ %d",
+		   "HiPr/ Locking/ warn/ Locked/ Noisy",
+		   (coex_sta->wifi_high_pri_task1 ? "Yes" : "No"),
+		   (coex_sta->cck_lock ? "Yes" : "No"),
+		   (coex_sta->cck_lock_warn ? "Yes" : "No"),
+		   (coex_sta->cck_lock_ever ? "Yes" : "No"),
+		   coex_sta->wl_noisy_level);
+	CL_PRINTF(cli_buf);
+
+	u8tmp[0] = btc->btc_read_1byte(btc, 0xf8e);
+	u8tmp[1] = btc->btc_read_1byte(btc, 0xf8f);
+	u8tmp[2] = btc->btc_read_1byte(btc, 0xd14);
+	u8tmp[3] = btc->btc_read_1byte(btc, 0xd54);
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d/ %d",
+		   "EVM_A/ EVM_B/ SNR_A/ SNR_B",
+		   (u8tmp[0] > 127 ? u8tmp[0] - 256 : u8tmp[0]),
+		   (u8tmp[1] > 127 ? u8tmp[1] - 256 : u8tmp[1]),
+		   (u8tmp[2] > 127 ? u8tmp[2] - 256 : u8tmp[2]),
+		   (u8tmp[3] > 127 ? u8tmp[3] - 256 : u8tmp[3]));
+	CL_PRINTF(cli_buf);
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d",
+		   "0x770(Hi-pri rx/tx)",
+		   coex_sta->high_priority_rx, coex_sta->high_priority_tx);
+	CL_PRINTF(cli_buf);
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d %s",
+		   "0x774(Lo-pri rx/tx)",
+		   coex_sta->low_priority_rx, coex_sta->low_priority_tx,
+		   (bt_link_info->slave_role ? "(Slave!!)" : (
+		   coex_sta->is_tdma_btautoslot_hang ? "(auto-slot hang!!)" : "")));
+	CL_PRINTF(cli_buf);
+
+	btc->btc_disp_dbg_msg(btc, BTC_DBG_DISP_COEX_STATISTICS);
+}
+
+void ex_halbtc8821c1ant_ips_notify(struct btc_coexist *btc, u8 type)
+{
+	struct coex_sta_8821c_1ant *coex_sta = &btc->coex_sta_8821c_1ant;
+
+	if (btc->manual_control || btc->stop_coex_dm)
+		return;
+
+	if (type == BTC_IPS_ENTER) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], IPS ENTER notify\n");
+		BTC_TRACE(trace_buf);
+		coex_sta->under_ips = TRUE;
+
+		/* Write WL "Active" in Score-board for LPS off */
+		halbtc8821c1ant_write_scbd(btc, BT_8821C_1ANT_SCBD_ACTIVE |
+					   BT_8821C_1ANT_SCBD_ONOFF |
+					   BT_8821C_1ANT_SCBD_SCAN |
+					   BT_8821C_1ANT_SCBD_UNDERTEST,
+					   FALSE);
+
+		halbtc8821c1ant_set_ant_path(btc, BTC_ANT_PATH_AUTO, FC_EXCU,
+					     BT_8821C_1ANT_PHASE_WOFF);
+		halbtc8821c1ant_action_coex_all_off(btc);
+	} else if (type == BTC_IPS_LEAVE) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], IPS LEAVE notify\n");
+		BTC_TRACE(trace_buf);
+
+		halbtc8821c1ant_init_hw_config(btc, FALSE, FALSE);
+		halbtc8821c1ant_init_coex_dm(btc);
+
+		coex_sta->under_ips = FALSE;
+	}
+}
+
+void ex_halbtc8821c1ant_lps_notify(struct btc_coexist *btc, u8 type)
+{
+	struct coex_sta_8821c_1ant *coex_sta = &btc->coex_sta_8821c_1ant;
+	static boolean  pre_force_lps_on = FALSE;
+
+	if (btc->manual_control || btc->stop_coex_dm)
+		return;
+
+	if (type == BTC_LPS_ENABLE) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], LPS ENABLE notify\n");
+		BTC_TRACE(trace_buf);
+		coex_sta->under_lps = TRUE;
+
+		if (coex_sta->force_lps_ctrl == TRUE) { /* LPS No-32K */
+			/* Write WL "Active" in Score-board for PS-TDMA */
+			pre_force_lps_on = TRUE;
+			halbtc8821c1ant_write_scbd(btc,
+						   BT_8821C_1ANT_SCBD_ACTIVE,
+						   TRUE);
+		} else { /* LPS-32K, need check if this h2c 0x71 can work??
+			  *(2015/08/28)
+			  * Write WL "Non-Active" in Score-board for Native-PS
+			  */
+			pre_force_lps_on = FALSE;
+			halbtc8821c1ant_write_scbd(btc,
+						   BT_8821C_1ANT_SCBD_ACTIVE,
+						   FALSE);
+
+			halbtc8821c1ant_action_wifi_native_lps(btc);
+		}
+	} else if (type == BTC_LPS_DISABLE) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], LPS DISABLE notify\n");
+		BTC_TRACE(trace_buf);
+		coex_sta->under_lps = FALSE;
+
+		/* Write WL "Active" in Score-board for LPS off */
+		halbtc8821c1ant_write_scbd(btc, BT_8821C_1ANT_SCBD_ACTIVE,
+					   TRUE);
+
+		if (!pre_force_lps_on && !coex_sta->force_lps_ctrl)
+			halbtc8821c1ant_query_bt_info(btc);
+	}
+}
+
+void ex_halbtc8821c1ant_scan_notify(struct btc_coexist *btc,
+				    u8 type)
+{
+	struct coex_sta_8821c_1ant *coex_sta = &btc->coex_sta_8821c_1ant;
+	boolean wifi_connected = FALSE;
+
+	if (btc->manual_control ||
+	    btc->stop_coex_dm)
+		return;
+
+	coex_sta->freeze_coexrun_by_btinfo = FALSE;
+
+	btc->btc_get(btc, BTC_GET_BL_WIFI_CONNECTED, &wifi_connected);
+
+	if (wifi_connected)
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			"[BTCoex], ********** WL connected before SCAN\n");
+	else
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			"[BTCoex], **********  WL is not connected before SCAN\n");
+
+	BTC_TRACE(trace_buf);
+
+	if (type != BTC_SCAN_FINISH) {
+
+		halbtc8821c1ant_write_scbd(btc, BT_8821C_1ANT_SCBD_ACTIVE |
+					   BT_8821C_1ANT_SCBD_SCAN |
+					   BT_8821C_1ANT_SCBD_ONOFF,
+					   TRUE);
+	}
+
+	if (type == BTC_SCAN_START_5G) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], SCAN START notify (5G)\n");
+		BTC_TRACE(trace_buf);
+
+		halbtc8821c1ant_set_ant_path(btc, BTC_ANT_PATH_AUTO, FC_EXCU,
+					     BT_8821C_1ANT_PHASE_5G);
+
+		halbtc8821c1ant_run_coex(btc, BT_8821C_1ANT_RSN_5GSCANSTART);
+	} else if (type == BTC_SCAN_START_2G || type == BTC_SCAN_START) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], SCAN START notify (2G)\n");
+		BTC_TRACE(trace_buf);
+
+		if (!wifi_connected)
+			coex_sta->wifi_high_pri_task2 = TRUE;
+
+		/* Force antenna setup for no scan result issue */
+		halbtc8821c1ant_set_ant_path(btc, BTC_ANT_PATH_AUTO, FC_EXCU,
+					     BT_8821C_1ANT_PHASE_2G);
+
+		halbtc8821c1ant_run_coex(btc, BT_8821C_1ANT_RSN_2GSCANSTART);
+	} else {
+		btc->btc_get(btc, BTC_GET_U1_AP_NUM, &coex_sta->scan_ap_num);
+
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], SCAN FINISH notify  (Scan-AP = %d)\n",
+			    coex_sta->scan_ap_num);
+		BTC_TRACE(trace_buf);
+
+		coex_sta->wifi_high_pri_task2 = FALSE;
+
+		halbtc8821c1ant_run_coex(btc, BT_8821C_1ANT_RSN_SCANFINISH);
+	}
+}
+
+void ex_halbtc8821c1ant_switchband_notify(struct btc_coexist *btc, u8 type)
+{
+	struct coex_sta_8821c_1ant *coex_sta = &btc->coex_sta_8821c_1ant;
+
+	if (btc->manual_control || btc->stop_coex_dm)
+		return;
+
+	coex_sta->switch_band_notify_to = type;
+
+	if (type == BTC_SWITCH_TO_5G) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], switchband_notify ---  switch to 5G\n");
+		BTC_TRACE(trace_buf);
+
+		halbtc8821c1ant_run_coex(btc, BT_8821C_1ANT_RSN_5GSWITCHBAND);
+
+	} else if (type == BTC_SWITCH_TO_24G_NOFORSCAN) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			"[BTCoex], switchband_notify --- BTC_SWITCH_TO_2G (no for scan)\n");
+		BTC_TRACE(trace_buf);
+
+		halbtc8821c1ant_run_coex(btc, BT_8821C_1ANT_RSN_2GSWITCHBAND);
+
+	} else {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], switchband_notify ---  switch to 2G\n");
+		BTC_TRACE(trace_buf);
+
+		ex_halbtc8821c1ant_scan_notify(btc, BTC_SCAN_START_2G);
+	}
+
+	coex_sta->switch_band_notify_to = BTC_NOT_SWITCH;
+}
+
+void ex_halbtc8821c1ant_connect_notify(struct btc_coexist *btc, u8 type)
+{
+	struct coex_sta_8821c_1ant *coex_sta = &btc->coex_sta_8821c_1ant;
+	struct coex_dm_8821c_1ant *coex_dm = &btc->coex_dm_8821c_1ant;
+
+	if (btc->manual_control || btc->stop_coex_dm)
+		return;
+
+	halbtc8821c1ant_write_scbd(btc, BT_8821C_1ANT_SCBD_ACTIVE |
+				   BT_8821C_1ANT_SCBD_SCAN |
+				   BT_8821C_1ANT_SCBD_ONOFF,
+				   TRUE);
+
+	if (type == BTC_ASSOCIATE_5G_START ||
+	    type == BTC_ASSOCIATE_5G_FINISH) {
+		halbtc8821c1ant_set_ant_path(btc, BTC_ANT_PATH_AUTO, FC_EXCU,
+					     BT_8821C_1ANT_PHASE_5G);
+
+		if (type == BTC_ASSOCIATE_5G_START) {
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+					"[BTCoex], CONNECT START notify (5G)\n");
+			BTC_TRACE(trace_buf);
+
+			halbtc8821c1ant_run_coex(btc,
+						 BT_8821C_1ANT_RSN_5GCONSTART);
+		} else {
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				    "[BTCoex], CONNECT FINISH notify (5G)\n");
+			BTC_TRACE(trace_buf);
+
+			halbtc8821c1ant_run_coex(btc,
+						 BT_8821C_1ANT_RSN_5GCONFINISH);
+		}
+
+	} else if (type == BTC_ASSOCIATE_START) {
+		coex_sta->wifi_high_pri_task1 = TRUE;
+		coex_dm->arp_cnt = 0;
+		coex_sta->connect_ap_period_cnt = 2;
+
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], CONNECT START notify (2G)\n");
+		BTC_TRACE(trace_buf);
+
+		/* Force antenna setup for no scan result issue */
+		halbtc8821c1ant_set_ant_path(btc, BTC_ANT_PATH_AUTO, FC_EXCU,
+					     BT_8821C_1ANT_PHASE_2G);
+
+		halbtc8821c1ant_run_coex(btc, BT_8821C_1ANT_RSN_2GCONSTART);
+
+		/* To keep TDMA case during connect process,
+		 * to avoid changed by Btinfo and runcoexmechanism
+		 */
+		coex_sta->freeze_coexrun_by_btinfo = TRUE;
+	} else {
+		coex_sta->wifi_high_pri_task1 = FALSE;
+		coex_sta->freeze_coexrun_by_btinfo = FALSE;
+
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], CONNECT FINISH notify (2G)\n");
+		BTC_TRACE(trace_buf);
+
+		halbtc8821c1ant_run_coex(btc, BT_8821C_1ANT_RSN_2GCONFINISH);
+	}
+}
+
+void ex_halbtc8821c1ant_media_status_notify(struct btc_coexist *btc, u8 type)
+{
+	struct coex_sta_8821c_1ant *coex_sta = &btc->coex_sta_8821c_1ant;
+	boolean	wifi_under_b_mode = FALSE;
+	u16 ap_beacon_interval = 100;
+	u8 h2c_parameter[3] = {0};
+
+	if (btc->manual_control || btc->stop_coex_dm)
+		return;
+
+	if (type == BTC_MEDIA_CONNECT || type == BTC_MEDIA_CONNECT_5G) {
+
+		halbtc8821c1ant_write_scbd(btc,
+					   BT_8821C_1ANT_SCBD_ACTIVE |
+					   BT_8821C_1ANT_SCBD_ONOFF,
+					    TRUE);
+
+		if (type == BTC_MEDIA_CONNECT_5G) {
+
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				    "[BTCoex], media_status_notify --- 5G\n");
+			BTC_TRACE(trace_buf);
+
+			halbtc8821c1ant_set_ant_path(btc, BTC_ANT_PATH_AUTO,
+						     FC_EXCU,
+						     BT_8821C_1ANT_PHASE_5G);
+
+			halbtc8821c1ant_run_coex(btc,
+						 BT_8821C_1ANT_RSN_5GMEDIA);
+		} else {
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+							"[BTCoex], media_status_notify --- 2G\n");
+			BTC_TRACE(trace_buf);
+
+			/* Force antenna setup for no scan result issue */
+			halbtc8821c1ant_set_ant_path(btc, BTC_ANT_PATH_AUTO,
+						     FC_EXCU,
+						     BT_8821C_1ANT_PHASE_2G);
+
+			btc->btc_get(btc, BTC_GET_BL_WIFI_UNDER_B_MODE,
+					   &wifi_under_b_mode);
+
+			/* Set CCK Tx/Rx high Pri except 11b mode */
+			if (wifi_under_b_mode) {
+				/* CCK Tx */
+				btc->btc_write_1byte(btc, 0x6cd, 0x00);
+				/* CCK Rx */
+				btc->btc_write_1byte(btc, 0x6cf, 0x00);
+			} else {
+				/* CCK Tx */
+				btc->btc_write_1byte(btc, 0x6cd, 0x00);
+				/* CCK Rx */
+				btc->btc_write_1byte(btc, 0x6cf, 0x10);
+			}
+
+			btc->btc_get(btc, BTC_GET_U2_BEACON_PERIOD,
+				     &ap_beacon_interval);
+
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				    "[BTCoex], AP beacon interval = %d\n",
+				    ap_beacon_interval);
+			BTC_TRACE(trace_buf);
+
+			/* set TDMA waiting BI if BI is not equal to 100 */
+			if (ap_beacon_interval < 80 && ap_beacon_interval > 0) {
+				h2c_parameter[0] = 0xb;
+				h2c_parameter[1] = (100 / ap_beacon_interval);
+
+				if (100 % ap_beacon_interval != 0)
+					h2c_parameter[1] = h2c_parameter[1] + 1;
+
+			} else if (ap_beacon_interval >= 180) {
+				h2c_parameter[0] = 0xb;
+				h2c_parameter[1] = (ap_beacon_interval / 100);
+
+				if (ap_beacon_interval % 100 <= 80)
+					h2c_parameter[1] = h2c_parameter[1] - 1;
+
+				h2c_parameter[1] = h2c_parameter[1] | 0x80;
+
+			} else {
+				h2c_parameter[0] = 0xb;
+				h2c_parameter[1] = 0x1;
+			}
+
+			btc->btc_fill_h2c(btc, 0x69, 2, h2c_parameter);
+
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				    "[BTCoex], TDMA waiting BI = 0x%x\n",
+				    h2c_parameter[1]);
+			BTC_TRACE(trace_buf);
+
+			halbtc8821c1ant_run_coex(btc,
+						 BT_8821C_1ANT_RSN_2GMEDIA);
+		}
+	} else {
+
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], media disconnect notify\n");
+		BTC_TRACE(trace_buf);
+
+		halbtc8821c1ant_write_scbd(btc, BT_8821C_1ANT_SCBD_ACTIVE,
+					   FALSE);
+
+		btc->btc_write_1byte(btc, 0x6cd, 0x0); /* CCK Tx */
+		btc->btc_write_1byte(btc, 0x6cf, 0x0); /* CCK Rx */
+
+		coex_sta->cck_lock_ever = FALSE;
+		coex_sta->cck_lock_warn = FALSE;
+		coex_sta->cck_lock = FALSE;
+		halbtc8821c1ant_run_coex(btc, BT_8821C_1ANT_RSN_MEDIADISCON);
+	}
+
+	halbtc8821c1ant_update_wifi_ch_info(btc, type);
+}
+
+void ex_halbtc8821c1ant_specific_packet_notify(struct btc_coexist *btc, u8 type)
+{
+	struct coex_sta_8821c_1ant *coex_sta = &btc->coex_sta_8821c_1ant;
+	struct coex_dm_8821c_1ant *coex_dm = &btc->coex_dm_8821c_1ant;
+	boolean	under_4way = FALSE;
+
+	if (btc->manual_control || btc->stop_coex_dm)
+		return;
+
+	if (type & BTC_5G_BAND) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], 5g special packet notify\n");
+		BTC_TRACE(trace_buf);
+
+		halbtc8821c1ant_run_coex(btc, BT_8821C_1ANT_RSN_5GSPECIALPKT);
+		return;
+	}
+
+	btc->btc_get(btc, BTC_GET_BL_WIFI_4_WAY_PROGRESS, &under_4way);
+
+	if (under_4way) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], specific Packet ---- under_4way!!\n");
+		BTC_TRACE(trace_buf);
+
+		coex_sta->wifi_high_pri_task1 = TRUE;
+		coex_sta->specific_pkt_period_cnt = 2;
+	} else if (type == BTC_PACKET_ARP) {
+		coex_dm->arp_cnt++;
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], specific Packet ARP notify -cnt = %d\n",
+			    coex_dm->arp_cnt);
+		BTC_TRACE(trace_buf);
+
+	} else {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], specific Packet DHCP or EAPOL notify [Type = %d]\n",
+			    type);
+		BTC_TRACE(trace_buf);
+
+		coex_sta->wifi_high_pri_task1 = TRUE;
+		coex_sta->specific_pkt_period_cnt = 2;
+	}
+
+	if (coex_sta->wifi_high_pri_task1) {
+		halbtc8821c1ant_write_scbd(btc, BT_8821C_1ANT_SCBD_SCAN, TRUE);
+		halbtc8821c1ant_run_coex(btc, BT_8821C_1ANT_RSN_2GSPECIALPKT);
+	}
+}
+
+void ex_halbtc8821c1ant_bt_info_notify(struct btc_coexist *btc, u8 *tmp_buf,
+				       u8 length)
+{
+	struct coex_sta_8821c_1ant *coex_sta = &btc->coex_sta_8821c_1ant;
+	u8 i, rsp_source = 0;
+	boolean	wifi_connected = FALSE;
+	boolean	wifi_busy = FALSE;
+	static boolean is_scoreboard_scan;
+	const u16 type_is_scan = BT_8821C_1ANT_SCBD_SCAN;
+	u8 type;
+
+	rsp_source = tmp_buf[0] & 0xf;
+	if (rsp_source >= BT_8821C_1ANT_INFO_SRC_MAX)
+		rsp_source = BT_8821C_1ANT_INFO_SRC_WIFI_FW;
+	coex_sta->bt_info_c2h_cnt[rsp_source]++;
+
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+		    "[BTCoex], Bt_info[%d], len=%d, data=[", rsp_source,
+		    length);
+	BTC_TRACE(trace_buf);
+
+	if (rsp_source == BT_8821C_1ANT_INFO_SRC_BT_RSP ||
+	    rsp_source == BT_8821C_1ANT_INFO_SRC_BT_ACT) {
+		if (coex_sta->bt_disabled) {
+			coex_sta->bt_disabled = FALSE;
+			coex_sta->is_bt_reenable = TRUE;
+			coex_sta->cnt_bt_reenable = 15;
+
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				    "[BTCoex], BT enable detected by bt_info\n");
+			BTC_TRACE(trace_buf);
+		}
+	}
+
+	for (i = 0; i < length; i++) {
+		coex_sta->bt_info_c2h[rsp_source][i] = tmp_buf[i];
+
+		if (i == length - 1) {
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "0x%02x]\n",
+				    tmp_buf[i]);
+			BTC_TRACE(trace_buf);
+		} else {
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "0x%02x, ",
+				    tmp_buf[i]);
+			BTC_TRACE(trace_buf);
+		}
+	}
+
+	coex_sta->bt_info = coex_sta->bt_info_c2h[rsp_source][1];
+	coex_sta->bt_info_ext = coex_sta->bt_info_c2h[rsp_source][4];
+	coex_sta->bt_info_ext2 = coex_sta->bt_info_c2h[rsp_source][5];
+
+	if (rsp_source != BT_8821C_1ANT_INFO_SRC_WIFI_FW) {
+		/* if 0xff, it means BT is under WHCK test */
+		coex_sta->bt_whck_test =
+			((coex_sta->bt_info == 0xff) ? TRUE : FALSE);
+
+		coex_sta->bt_create_connection =
+			((coex_sta->bt_info_c2h[rsp_source][2] & 0x80) ? TRUE :
+									 FALSE);
+
+		/* unit: %, value-100 to translate to unit: dBm */
+		coex_sta->bt_rssi =
+			coex_sta->bt_info_c2h[rsp_source][3] * 2 + 10;
+
+		coex_sta->c2h_bt_remote_name_req =
+			((coex_sta->bt_info_c2h[rsp_source][2] & 0x20) ? TRUE :
+									 FALSE);
+
+		coex_sta->is_A2DP_3M =
+			((coex_sta->bt_info_c2h[rsp_source][2] & 0x10) ? TRUE :
+									 FALSE);
+
+		coex_sta->acl_busy =
+			((coex_sta->bt_info_c2h[rsp_source][1] & 0x8) ? TRUE :
+									FALSE);
+
+		coex_sta->voice_over_HOGP =
+			((coex_sta->bt_info_ext & 0x10) ? TRUE : FALSE);
+
+		coex_sta->c2h_bt_inquiry_page =
+			((coex_sta->bt_info & BT_INFO_8821C_1ANT_B_INQ_PAGE) ?
+				 TRUE :
+				 FALSE);
+
+		coex_sta->a2dp_bit_pool =
+			(((coex_sta->bt_info_c2h[rsp_source][1] & 0x49) ==
+			  0x49) ?
+				 (coex_sta->bt_info_c2h[rsp_source][6] & 0x7f) :
+				 0);
+
+		coex_sta->is_bt_a2dp_sink =
+			(coex_sta->bt_info_c2h[rsp_source][6] & 0x80) ? TRUE :
+									FALSE;
+
+		coex_sta->bt_retry_cnt =
+			coex_sta->bt_info_c2h[rsp_source][2] & 0xf;
+
+		coex_sta->is_autoslot = coex_sta->bt_info_ext2 & 0x8;
+
+		coex_sta->forbidden_slot = coex_sta->bt_info_ext2 & 0x7;
+
+		coex_sta->hid_busy_num = (coex_sta->bt_info_ext2 & 0x30) >> 4;
+
+		coex_sta->hid_pair_cnt = (coex_sta->bt_info_ext2 & 0xc0) >> 6;
+
+		coex_sta->is_bt_opp_exist =
+			(coex_sta->bt_info_ext2 & 0x1) ? TRUE : FALSE;
+
+		if (coex_sta->bt_retry_cnt >= 1)
+			coex_sta->pop_event_cnt++;
+
+		if (coex_sta->c2h_bt_remote_name_req)
+			coex_sta->cnt_remote_name_req++;
+
+		if (coex_sta->bt_info_ext & BIT(1))
+			coex_sta->cnt_reinit++;
+
+		if ((coex_sta->bt_info_ext & BIT(2)) ||
+		    (coex_sta->bt_create_connection &&
+		     coex_sta->wl_pnp_wakeup_downcnt > 0)) {
+			coex_sta->cnt_setup_link++;
+			coex_sta->is_setup_link = TRUE;
+
+			if (coex_sta->is_bt_reenable)
+				coex_sta->bt_relink_downcount = 6;
+			else
+				coex_sta->bt_relink_downcount = 2;
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				     "[BTCoex], Re-Link start in BT info!!\n");
+			BTC_TRACE(trace_buf);
+		} else {
+			coex_sta->is_setup_link = FALSE;
+			if (!coex_sta->is_bt_reenable)
+				coex_sta->bt_relink_downcount = 0;
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				    "[BTCoex], Re-Link stop in BT info!!\n");
+			BTC_TRACE(trace_buf);
+		}
+
+		if (coex_sta->bt_info_ext & BIT(3))
+			coex_sta->cnt_ign_wlan_act++;
+
+		if (coex_sta->bt_info_ext & BIT(6))
+			coex_sta->cnt_role_switch++;
+
+		if (coex_sta->bt_info_ext & BIT(7))
+			coex_sta->is_bt_multi_link = TRUE;
+		else
+			coex_sta->is_bt_multi_link = FALSE;
+
+		if (coex_sta->bt_info_ext & BIT(0))
+			coex_sta->is_hid_rcu = TRUE;
+		else
+			coex_sta->is_hid_rcu = FALSE;
+
+		if (coex_sta->bt_info_ext & BIT(5))
+			coex_sta->is_ble_scan_en = TRUE;
+		else
+			coex_sta->is_ble_scan_en = FALSE;
+
+		if (coex_sta->bt_create_connection) {
+			coex_sta->cnt_page++;
+
+			btc->btc_get(btc, BTC_GET_BL_WIFI_BUSY, &wifi_busy);
+
+			if (coex_sta->is_wifi_linkscan_process ||
+			    coex_sta->wifi_high_pri_task1 ||
+			    coex_sta->wifi_high_pri_task2 ||
+			    wifi_busy) {
+
+				is_scoreboard_scan = TRUE;
+				halbtc8821c1ant_write_scbd(btc, type_is_scan,
+							   TRUE);
+
+			} else
+				halbtc8821c1ant_write_scbd(btc, type_is_scan,
+							   FALSE);
+
+		} else {
+			if (is_scoreboard_scan) {
+				halbtc8821c1ant_write_scbd(btc, type_is_scan,
+							   FALSE);
+				is_scoreboard_scan = FALSE;
+			}
+		}
+
+		/* Here we need to resend some wifi info to BT */
+		/* because bt is reset and loss of the info. */
+		btc->btc_get(btc, BTC_GET_BL_WIFI_CONNECTED, &wifi_connected);
+
+		/*  Re-Init */
+		if ((coex_sta->bt_info_ext & BIT(1))) {
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				    "[BTCoex], BT ext info bit1 check, send wifi BW&Chnl to BT!!\n");
+			BTC_TRACE(trace_buf);
+			if (wifi_connected)
+				type = BTC_MEDIA_CONNECT;
+			else
+				type = BTC_MEDIA_DISCONNECT;
+			halbtc8821c1ant_update_wifi_ch_info(btc, type);
+		}
+
+		/*  If Ignore_WLanAct && not SetUp_Link */
+		if ((coex_sta->bt_info_ext & BIT(3)) &&
+		    (!(coex_sta->bt_info_ext & BIT(2)))) {
+
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				    "[BTCoex], BT ext info bit3 check, set BT NOT to ignore Wlan active!!\n");
+			BTC_TRACE(trace_buf);
+			halbtc8821c1ant_ignore_wlan_act(btc, FC_EXCU, FALSE);
+		}
+	}
+
+	halbtc8821c1ant_update_bt_link_info(btc);
+
+	halbtc8821c1ant_run_coex(btc, BT_8821C_1ANT_RSN_BTINFO);
+}
+
+void ex_halbtc8821c1ant_wl_fwdbginfo_notify(struct btc_coexist *btc,
+					    u8 *tmp_buf, u8 length)
+{
+	struct coex_sta_8821c_1ant *coex_sta = &btc->coex_sta_8821c_1ant;
+	u8 i = 0;
+	static u8 tmp_buf_pre[10] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
+
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+		    "[BTCoex], WiFi Fw Dbg info = %d %d %d %d %d %d (len = %d)\n",
+		    tmp_buf[0], tmp_buf[1], tmp_buf[2], tmp_buf[3], tmp_buf[4],
+		    tmp_buf[5], length);
+	BTC_TRACE(trace_buf);
+
+	if (tmp_buf[0] == 0x8) {
+		for (i = 1; i <= 5; i++) {
+			coex_sta->wl_fw_dbg_info[i] =
+				(tmp_buf[i] >= tmp_buf_pre[i]) ?
+				(tmp_buf[i] - tmp_buf_pre[i]) :
+				(255 - tmp_buf_pre[i] + tmp_buf[i]);
+
+			tmp_buf_pre[i] = tmp_buf[i];
+		}
+	}
+}
+
+void ex_halbtc8821c1ant_rx_rate_change_notify(struct btc_coexist *btc,
+					      BOOLEAN is_data_frame,
+					      u8 btc_rate_id)
+{
+	struct coex_sta_8821c_1ant *coex_sta = &btc->coex_sta_8821c_1ant;
+	struct coex_dm_8821c_1ant *coex_dm = &btc->coex_dm_8821c_1ant;
+	BOOLEAN wifi_connected = FALSE;
+
+	btc->btc_get(btc, BTC_GET_BL_WIFI_CONNECTED, &wifi_connected);
+
+	if (is_data_frame) {
+		coex_sta->wl_rx_rate = btc_rate_id;
+
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], rx_rate_change_notify data rate id = %d, RTS_Rate = %d\n",
+			    coex_sta->wl_rx_rate, coex_sta->wl_rts_rx_rate);
+		BTC_TRACE(trace_buf);
+	} else {
+		coex_sta->wl_rts_rx_rate = btc_rate_id;
+
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], rts_rate_change_notify RTS rate id = %d, RTS_Rate = %d\n",
+			    coex_sta->wl_rts_rx_rate, coex_sta->wl_rts_rx_rate);
+		BTC_TRACE(trace_buf);
+	}
+
+	if (wifi_connected &&
+	    (coex_dm->bt_status == BT_8821C_1ANT_BSTATUS_ACL_BUSY ||
+	     coex_dm->bt_status == BT_8821C_1ANT_BSTATUS_ACL_SCO_BUSY ||
+	     coex_dm->bt_status == BT_8821C_1ANT_BSTATUS_SCO_BUSY)) {
+		if (coex_sta->wl_rx_rate == BTC_CCK_5_5 ||
+		    coex_sta->wl_rx_rate == BTC_OFDM_6 ||
+		    coex_sta->wl_rx_rate == BTC_MCS_0) {
+			coex_sta->cck_lock_warn = TRUE;
+
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				    "[BTCoex], cck lock warning...\n");
+			BTC_TRACE(trace_buf);
+		} else if (coex_sta->wl_rx_rate == BTC_CCK_1 ||
+			   coex_sta->wl_rx_rate == BTC_CCK_2 ||
+			   coex_sta->wl_rts_rx_rate == BTC_CCK_1 ||
+			   coex_sta->wl_rts_rx_rate == BTC_CCK_2) {
+			coex_sta->cck_lock = TRUE;
+
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				    "[BTCoex], cck locking...\n");
+			BTC_TRACE(trace_buf);
+		} else {
+			coex_sta->cck_lock_warn = FALSE;
+			coex_sta->cck_lock = FALSE;
+
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				    "[BTCoex], cck unlock...\n");
+			BTC_TRACE(trace_buf);
+		}
+	} else {
+		if (coex_dm->bt_status == BT_8821C_1ANT_BSTATUS_CON_IDLE ||
+		    coex_dm->bt_status == BT_8821C_1ANT_BSTATUS_NCON_IDLE) {
+			coex_sta->cck_lock_warn = FALSE;
+			coex_sta->cck_lock = FALSE;
+		}
+	}
+}
+
+void ex_halbtc8821c1ant_tx_rate_change_notify(struct btc_coexist *btc,
+					      u8 tx_rate, u8 tx_retry_ratio,
+					      u8 macid)
+{
+	struct coex_sta_8821c_1ant *coex_sta = &btc->coex_sta_8821c_1ant;
+
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+		    "[BTCoex], tx_rate_change_notify Tx_Rate = %d, Tx_Retry_Ratio = %d, macid =%d\n",
+		    tx_rate, tx_retry_ratio, macid);
+	BTC_TRACE(trace_buf);
+
+	coex_sta->wl_tx_rate = tx_rate;
+	coex_sta->wl_tx_retry_ratio = tx_retry_ratio;
+	coex_sta->wl_tx_macid = macid;
+}
+
+void ex_halbtc8821c1ant_rf_status_notify(struct btc_coexist *btc, u8 type)
+{
+	struct coex_sta_8821c_1ant *coex_sta = &btc->coex_sta_8821c_1ant;
+
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], RF Status notify\n");
+	BTC_TRACE(trace_buf);
+
+	if (type == BTC_RF_ON) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], RF is turned ON!!\n");
+		BTC_TRACE(trace_buf);
+
+		btc->stop_coex_dm = FALSE;
+		coex_sta->is_rf_state_off = FALSE;
+	} else if (type == BTC_RF_OFF) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], RF is turned OFF!!\n");
+		BTC_TRACE(trace_buf);
+
+		halbtc8821c1ant_write_scbd(btc, BT_8821C_1ANT_SCBD_ACTIVE |
+					   BT_8821C_1ANT_SCBD_ONOFF |
+					   BT_8821C_1ANT_SCBD_SCAN |
+					   BT_8821C_1ANT_SCBD_UNDERTEST,
+					   FALSE);
+
+		halbtc8821c1ant_set_ant_path(btc, BTC_ANT_PATH_AUTO, FC_EXCU,
+					     BT_8821C_1ANT_PHASE_WOFF);
+
+		halbtc8821c1ant_action_coex_all_off(btc);
+
+		btc->stop_coex_dm = TRUE;
+		coex_sta->is_rf_state_off = TRUE;
+
+		/* must place in the last step */
+		halbtc8821c1ant_update_wifi_ch_info(btc, BTC_MEDIA_DISCONNECT);
+	}
+}
+
+void ex_halbtc8821c1ant_halt_notify(struct btc_coexist *btc)
+{
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], Halt notify\n");
+	BTC_TRACE(trace_buf);
+
+	halbtc8821c1ant_write_scbd(btc, BT_8821C_1ANT_SCBD_ACTIVE |
+				   BT_8821C_1ANT_SCBD_ONOFF |
+				   BT_8821C_1ANT_SCBD_SCAN |
+				   BT_8821C_1ANT_SCBD_UNDERTEST,
+				   FALSE);
+
+	halbtc8821c1ant_set_ant_path(btc, BTC_ANT_PATH_AUTO, FC_EXCU,
+				     BT_8821C_1ANT_PHASE_WOFF);
+
+	halbtc8821c1ant_action_coex_all_off(btc);
+
+	btc->stop_coex_dm = TRUE;
+
+	/* must place in the last step */
+	halbtc8821c1ant_update_wifi_ch_info(btc, BTC_MEDIA_DISCONNECT);
+}
+
+void ex_halbtc8821c1ant_pnp_notify(struct btc_coexist *btc, u8 pnp_state)
+{
+	struct coex_sta_8821c_1ant *coex_sta = &btc->coex_sta_8821c_1ant;
+	struct wifi_link_info_8821c_1ant *wifi_link_info_ext =
+					 &btc->wifi_link_info_8821c_1ant;
+	static u8 pre_pnp_state;
+	u8 phase;
+
+	if (pnp_state == BTC_WIFI_PNP_SLEEP ||
+	    pnp_state == BTC_WIFI_PNP_SLEEP_KEEP_ANT) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], Pnp notify to SLEEP\n");
+		BTC_TRACE(trace_buf);
+
+		halbtc8821c1ant_write_scbd(btc, BT_8821C_1ANT_SCBD_ACTIVE |
+					   BT_8821C_1ANT_SCBD_ONOFF |
+					   BT_8821C_1ANT_SCBD_SCAN |
+					   BT_8821C_1ANT_SCBD_UNDERTEST,
+					   FALSE);
+
+		if (pnp_state == BTC_WIFI_PNP_SLEEP_KEEP_ANT) {
+			if (wifi_link_info_ext->is_all_under_5g)
+				phase = BT_8821C_1ANT_PHASE_5G;
+			else
+				phase = BT_8821C_1ANT_PHASE_2G;
+		} else {
+			phase = BT_8821C_1ANT_PHASE_WOFF;
+		}
+
+		halbtc8821c1ant_set_ant_path(btc, BTC_ANT_PATH_AUTO, FC_EXCU,
+					     phase);
+		btc->stop_coex_dm = TRUE;
+	} else {
+
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], Pnp notify to WAKE UP\n");
+		BTC_TRACE(trace_buf);
+		coex_sta->wl_pnp_wakeup_downcnt = 3;
+
+		/*WoWLAN*/
+		if (pre_pnp_state == BTC_WIFI_PNP_SLEEP_KEEP_ANT ||
+		    pnp_state == BTC_WIFI_PNP_WOWLAN) {
+			coex_sta->run_time_state = TRUE;
+			btc->stop_coex_dm = FALSE;
+			halbtc8821c1ant_run_coex(btc, BT_8821C_1ANT_RSN_PNP);
+		}
+	}
+	pre_pnp_state = pnp_state;
+}
+
+void ex_halbtc8821c1ant_coex_dm_reset(struct btc_coexist *btc)
+{
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+		"[BTCoex], *****************Coex DM Reset*****************\n");
+	BTC_TRACE(trace_buf);
+
+	halbtc8821c1ant_init_hw_config(btc, FALSE, FALSE);
+	halbtc8821c1ant_init_coex_dm(btc);
+}
+
+void ex_halbtc8821c1ant_periodical(struct btc_coexist *btc)
+{
+	struct coex_sta_8821c_1ant *coex_sta = &btc->coex_sta_8821c_1ant;
+	struct  btc_board_info	*board_info = &btc->board_info;
+	boolean wifi_busy = FALSE;
+	u16 bt_scoreboard_val = 0;
+	boolean bt_relink_finish = FALSE, is_defreeze = FALSE;
+	static u8 freeze_cnt;
+
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+		    "[BTCoex], ************* Periodical *************\n");
+	BTC_TRACE(trace_buf);
+
+	if (!btc->auto_report)
+		halbtc8821c1ant_query_bt_info(btc);
+
+	halbtc8821c1ant_monitor_bt_ctr(btc);
+	halbtc8821c1ant_monitor_wifi_ctr(btc);
+	halbtc8821c1ant_update_wifi_link_info(btc,
+					      BT_8821C_1ANT_RSN_PERIODICAL);
+	halbtc8821c1ant_monitor_bt_enable(btc);
+
+	if (coex_sta->bt_relink_downcount != 0) {
+		coex_sta->bt_relink_downcount--;
+
+		if (coex_sta->bt_relink_downcount == 0) {
+			coex_sta->is_setup_link = FALSE;
+			bt_relink_finish = TRUE;
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				    "[BTCoex], Re-Link stop by periodical count-down!!\n");
+			BTC_TRACE(trace_buf);
+		}
+	}
+
+	if (coex_sta->freeze_coexrun_by_btinfo) {
+		freeze_cnt++;
+
+		if (freeze_cnt >= 5) {
+			freeze_cnt = 0;
+			coex_sta->freeze_coexrun_by_btinfo = FALSE;
+			is_defreeze = TRUE;
+		}
+	} else {
+		freeze_cnt = 0;
+	}
+
+	/* for 4-way, DHCP, EAPOL packet */
+	if (coex_sta->specific_pkt_period_cnt > 0) {
+		coex_sta->specific_pkt_period_cnt--;
+
+		if (!coex_sta->freeze_coexrun_by_btinfo &&
+		    coex_sta->specific_pkt_period_cnt == 0)
+			coex_sta->wifi_high_pri_task1 = FALSE;
+
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], Hi-Pri Task = %s\n",
+			    (coex_sta->wifi_high_pri_task1 ? "Yes" : "No"));
+		BTC_TRACE(trace_buf);
+	}
+
+	/*for A2DP glitch during connecting AP*/
+	if (coex_sta->connect_ap_period_cnt > 0)
+		coex_sta->connect_ap_period_cnt--;
+
+	if (coex_sta->wl_pnp_wakeup_downcnt > 0) {
+		coex_sta->wl_pnp_wakeup_downcnt--;
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], wl_pnp_wakeup_downcnt = %d!!\n",
+			    coex_sta->wl_pnp_wakeup_downcnt);
+		BTC_TRACE(trace_buf);
+	}
+
+	if (coex_sta->cnt_bt_reenable > 0) {
+		coex_sta->cnt_bt_reenable--;
+		if (coex_sta->cnt_bt_reenable == 0) {
+			coex_sta->is_bt_reenable = FALSE;
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				    "[BTCoex], BT renable 30s finish!!\n");
+			BTC_TRACE(trace_buf);
+		}
+	}
+
+	if (halbtc8821c1ant_moniter_wifibt_status(btc) || bt_relink_finish ||
+	    coex_sta->is_set_ps_state_fail || is_defreeze)
+		halbtc8821c1ant_run_coex(btc, BT_8821C_1ANT_RSN_PERIODICAL);
+}
+
+/*#pragma optimize( "", off )*/
+#endif
+
+#endif	/* #if (BT_SUPPORT == 1 && COEX_SUPPORT == 1) */
+
+
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/btc/halbtc8821c1ant.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/btc/halbtc8821c1ant.h
--- linux-5.6.3/3rdparty/rtl8821ce/hal/btc/halbtc8821c1ant.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/btc/halbtc8821c1ant.h	2020-04-10 16:35:06.785658620 +0300
@@ -0,0 +1,474 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2016 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+
+#if (BT_SUPPORT == 1 && COEX_SUPPORT == 1)
+
+#if (RTL8821C_SUPPORT == 1)
+
+/* *******************************************
+ * The following is for 8821C 1ANT BT Co-exist definition
+ * ******************************************* */
+#define	BT_8821C_1ANT_COEX_DBG					0
+#define	BT_AUTO_REPORT_ONLY_8821C_1ANT				1
+
+#define	BT_INFO_8821C_1ANT_B_FTP				BIT(7)
+#define	BT_INFO_8821C_1ANT_B_A2DP				BIT(6)
+#define	BT_INFO_8821C_1ANT_B_HID				BIT(5)
+#define	BT_INFO_8821C_1ANT_B_SCO_BUSY				BIT(4)
+#define	BT_INFO_8821C_1ANT_B_ACL_BUSY				BIT(3)
+#define	BT_INFO_8821C_1ANT_B_INQ_PAGE				BIT(2)
+#define	BT_INFO_8821C_1ANT_B_SCO_ESCO				BIT(1)
+#define	BT_INFO_8821C_1ANT_B_CONNECTION				BIT(0)
+
+#define	BTC_RSSI_COEX_THRESH_TOL_8821C_1ANT		2
+
+#define  BT_8821C_1ANT_WIFI_NOISY_THRESH			30
+#define  BT_8821C_1ANT_DEFAULT_ISOLATION			15
+
+enum bt_8821c_1ant_signal_state {
+	BT_8821C_1ANT_GNT_SET_TO_LOW		= 0x0,
+	BT_8821C_1ANT_GNT_SET_TO_HIGH		= 0x1,
+	BT_8821C_1ANT_GNT_SET_BY_HW		= 0x2,
+	BT_8821C_1ANT_GNT_SET_MAX
+};
+
+enum bt_8821c_1ant_path_ctrl_owner {
+	BT_8821C_1ANT_PCO_BTSIDE		= 0x0,
+	BT_8821C_1ANT_PCO_WLSIDE		= 0x1,
+	BT_8821C_1ANT_PCO_MAX
+};
+
+enum bt_8821c_1ant_gnt_ctrl_type {
+	BT_8821C_1ANT_GNT_TYPE_CTRL_BY_PTA	= 0x0,
+	BT_8821C_1ANT_GNT_TYPE_CTRL_BY_SW	= 0x1,
+	BT_8821C_1ANT_GNT_TYPE_MAX
+};
+
+enum bt_8821c_1ant_gnt_ctrl_block {
+	BT_8821C_1ANT_GNT_BLOCK_RFC_BB		= 0x0,
+	BT_8821C_1ANT_GNT_BLOCK_RFC		= 0x1,
+	BT_8821C_1ANT_GNT_BLOCK_BB		= 0x2,
+	BT_8821C_1ANT_GNT_BLOCK_MAX
+};
+
+enum bt_8821c_1ant_lte_coex_table_type {
+	BT_8821C_1ANT_CTT_WL_VS_LTE		= 0x0,
+	BT_8821C_1ANT_CTT_BT_VS_LTE		= 0x1,
+	BT_8821C_1ANT_CTT_MAX
+};
+
+enum bt_8821c_1ant_lte_break_table_type {
+	BT_8821C_1ANT_LBTT_WL_BREAK_LTE		= 0x0,
+	BT_8821C_1ANT_LBTT_BT_BREAK_LTE		= 0x1,
+	BT_8821C_1ANT_LBTT_LTE_BREAK_WL		= 0x2,
+	BT_8821C_1ANT_LBTT_LTE_BREAK_BT		= 0x3,
+	BT_8821C_1ANT_LBTT_MAX
+};
+
+enum bt_info_src_8821c_1ant {
+	BT_8821C_1ANT_INFO_SRC_WIFI_FW		= 0x0,
+	BT_8821C_1ANT_INFO_SRC_BT_RSP		= 0x1,
+	BT_8821C_1ANT_INFO_SRC_BT_ACT		= 0x2,
+	BT_8821C_1ANT_INFO_SRC_MAX
+};
+
+enum bt_8821c_1ant_bt_status {
+	BT_8821C_1ANT_BSTATUS_NCON_IDLE		= 0x0,
+	BT_8821C_1ANT_BSTATUS_CON_IDLE		= 0x1,
+	BT_8821C_1ANT_BSTATUS_INQ_PAGE		= 0x2,
+	BT_8821C_1ANT_BSTATUS_ACL_BUSY		= 0x3,
+	BT_8821C_1ANT_BSTATUS_SCO_BUSY		= 0x4,
+	BT_8821C_1ANT_BSTATUS_ACL_SCO_BUSY	= 0x5,
+	BT_8821C_1ANT_BSTATUS_MAX
+};
+
+enum bt_8821c_1ant_wifi_status {
+	BT_8821C_1ANT_WSTATUS_NCON_IDLE		= 0x0,
+	BT_8821C_1ANT_WSTATUS_NCON_SCAN		= 0x1,
+	BT_8821C_1ANT_WSTATUS_CON_SCAN		= 0x2,
+	BT_8821C_1ANT_WSTATUS_CON_SPECPKT	= 0x3,
+	BT_8821C_1ANT_WSTATUS_CON_IDLE		= 0x4,
+	BT_8821C_1ANT_WSTATUS_CON_BUSY		= 0x5,
+	BT_8821C_1ANT_WSTATUS_MAX
+};
+
+enum bt_8821c_1ant_coex_algo {
+	BT_8821C_1ANT_COEX_UNDEFINED		= 0x0,
+	BT_8821C_1ANT_COEX_SCO			= 0x1,
+	BT_8821C_1ANT_COEX_HID			= 0x2,
+	BT_8821C_1ANT_COEX_A2DP			= 0x3,
+	BT_8821C_1ANT_COEX_A2DP_PANHS		= 0x4,
+	BT_8821C_1ANT_COEX_PAN			= 0x5,
+	BT_8821C_1ANT_COEX_PANHS		= 0x6,
+	BT_8821C_1ANT_COEX_PAN_A2DP		= 0x7,
+	BT_8821C_1ANT_COEX_PAN_HID		= 0x8,
+	BT_8821C_1ANT_COEX_HID_A2DP_PAN		= 0x9,
+	BT_8821C_1ANT_COEX_HID_A2DP		= 0xa,
+	BT_8821C_1ANT_COEX_MAX			= 0xb,
+};
+
+enum bt_8821c_1ant_ext_ant_switch_type {
+	BT_8821C_1ANT_USE_DPDT		= 0x0,
+	BT_8821C_1ANT_USE_SPDT		= 0x1,
+	BT_8821C_1ANT_SWITCH_NONE	= 0x2,
+	BT_8821C_1ANT_SWITCH_MAX
+};
+
+
+enum bt_8821c_1ant_ext_ant_switch_ctrl_type {
+	BT_8821C_1ANT_CTRL_BY_BBSW	= 0x0,
+	BT_8821C_1ANT_CTRL_BY_PTA	= 0x1,
+	BT_8821C_1ANT_CTRL_BY_ANTDIV	= 0x2,
+	BT_8821C_1ANT_CTRL_BY_MAC	= 0x3,
+	BT_8821C_1ANT_CTRL_BY_BT	= 0x4,
+	BT_8821C_1ANT_CTRL_BY_FW	= 0x5,
+	BT_8821C_1ANT_CTRL_MAX
+};
+
+enum bt_8821c_1ant_ext_ant_switch_pos_type {
+	BT_8821C_1ANT_TO_BT		= 0x0,
+	BT_8821C_1ANT_TO_WLG		= 0x1,
+	BT_8821C_1ANT_TO_WLA		= 0x2,
+	BT_8821C_1ANT_TO_NOCARE		= 0x3,
+	BT_8821C_1ANT_TO_MAX
+};
+
+enum bt_8821c_1ant_phase {
+	BT_8821C_1ANT_PHASE_INIT	= 0x0,
+	BT_8821C_1ANT_PHASE_WONLY	= 0x1,
+	BT_8821C_1ANT_PHASE_WOFF	= 0x2,
+	BT_8821C_1ANT_PHASE_2G		= 0x3,
+	BT_8821C_1ANT_PHASE_5G		= 0x4,
+	BT_8821C_1ANT_PHASE_BTMP	= 0x5,
+	BT_8821C_1ANT_PHASE_ANTDET	= 0x6,
+	BT_8821C_1ANT_PHASE_POWERON	= 0x7,
+	BT_8821C_1ANT_PHASE_MCC		= 0x8,
+	BT_8821C_1ANT_PHASE_MAX
+};
+
+enum bt_8821c_1ant_scoreboard {
+	BT_8821C_1ANT_SCBD_ACTIVE	= BIT(0),
+	BT_8821C_1ANT_SCBD_ONOFF	= BIT(1),
+	BT_8821C_1ANT_SCBD_SCAN		= BIT(2),
+	BT_8821C_1ANT_SCBD_UNDERTEST	= BIT(3),
+	BT_8821C_1ANT_SCBD_WLBUSY	= BIT(6),
+	BT_8821C_1ANT_SCBD_BTCQDDR	= BIT(10)
+};
+
+enum bt_8821c_1ant_RUNREASON {
+	BT_8821C_1ANT_RSN_2GSCANSTART	= 0x0,
+	BT_8821C_1ANT_RSN_5GSCANSTART	= 0x1,
+	BT_8821C_1ANT_RSN_SCANFINISH	= 0x2,
+	BT_8821C_1ANT_RSN_2GSWITCHBAND	= 0x3,
+	BT_8821C_1ANT_RSN_5GSWITCHBAND	= 0x4,
+	BT_8821C_1ANT_RSN_2GCONSTART	= 0x5,
+	BT_8821C_1ANT_RSN_5GCONSTART	= 0x6,
+	BT_8821C_1ANT_RSN_2GCONFINISH	= 0x7,
+	BT_8821C_1ANT_RSN_5GCONFINISH	= 0x8,
+	BT_8821C_1ANT_RSN_2GMEDIA	= 0x9,
+	BT_8821C_1ANT_RSN_5GMEDIA	= 0xa,
+	BT_8821C_1ANT_RSN_MEDIADISCON	= 0xb,
+	BT_8821C_1ANT_RSN_2GSPECIALPKT	= 0xc,
+	BT_8821C_1ANT_RSN_5GSPECIALPKT	= 0xd,
+	BT_8821C_1ANT_RSN_BTINFO	= 0xe,
+	BT_8821C_1ANT_RSN_PERIODICAL	= 0xf,
+	BT_8821C_1ANT_RSN_PNP		= 0x10,
+	BT_8821C_1ANT_RSN_MAX
+};
+
+enum bt_8821c_1ant_WL_LINK_MODE {
+	BT_8821C_1ANT_WLINK_2G1PORT	= 0x0,
+	BT_8821C_1ANT_WLINK_2GMPORT	= 0x1,
+	BT_8821C_1ANT_WLINK_25GMPORT	= 0x2,
+	BT_8821C_1ANT_WLINK_5G		= 0x3,
+	BT_8821C_1ANT_WLINK_2GGO	= 0x4,
+	BT_8821C_1ANT_WLINK_BTMR	= 0x5,
+	BT_8821C_1ANT_WLINK_MAX
+};
+
+struct coex_dm_8821c_1ant {
+	/* hw setting */
+	u32		cur_ant_pos_type;
+
+	/* fw mechanism */
+	boolean		cur_ignore_wlan_act;
+
+	u8		cur_ps_tdma;
+	u8		ps_tdma_para[5];
+	boolean		cur_ps_tdma_on;
+
+	boolean		cur_bt_auto_report;
+	u8		cur_lps;
+	u8		cur_rpwm;
+
+	/* sw mechanism */
+	boolean		cur_low_penalty_ra;
+
+	u32		cur_val0x6c0;
+	u32		cur_val0x6c4;
+	u32		cur_val0x6c8;
+	u8		cur_val0x6cc;
+
+	/* algorithm related */
+	u8		cur_algorithm;
+	u8		bt_status;
+	u8		wifi_chnl_info[3];
+
+	u32		arp_cnt;
+
+	u32		cur_ext_ant_switch_status;
+	u32		setting_tdma;
+};
+
+struct coex_sta_8821c_1ant {
+	boolean			bt_disabled;
+	boolean			bt_link_exist;
+	boolean			sco_exist;
+	boolean			a2dp_exist;
+	boolean			hid_exist;
+	boolean			pan_exist;
+	boolean			msft_mr_exist;
+	u8			num_of_profile;
+
+	boolean			under_lps;
+	boolean			under_ips;
+	u32			specific_pkt_period_cnt;
+	u32			high_priority_tx;
+	u32			high_priority_rx;
+	u32			low_priority_tx;
+	u32			low_priority_rx;
+	boolean			is_hi_pri_rx_overhead;
+	s8			bt_rssi;
+	u8			pre_bt_rssi_state;
+	u8			pre_wifi_rssi_state[4];
+	u8			bt_info_c2h[BT_8821C_1ANT_INFO_SRC_MAX][10];
+	u32			bt_info_c2h_cnt[BT_8821C_1ANT_INFO_SRC_MAX];
+	boolean			bt_whck_test;
+	boolean			c2h_bt_inquiry_page;
+	boolean			c2h_bt_remote_name_req;
+	boolean			c2h_bt_page;
+
+	boolean			wifi_high_pri_task1;
+	boolean			wifi_high_pri_task2;
+
+	u8			bt_info_ext;
+	u8			bt_info_ext2;
+	u32			pop_event_cnt;
+	u8			scan_ap_num;
+	u8			bt_retry_cnt;
+
+	u32			crc_ok_cck;
+	u32			crc_ok_11g;
+	u32			crc_ok_11n;
+	u32			crc_ok_11n_vht;
+
+	u32			crc_err_cck;
+	u32			crc_err_11g;
+	u32			crc_err_11n;
+	u32			crc_err_11n_vht;
+
+	boolean			cck_lock;
+	boolean			cck_lock_ever;
+	boolean			cck_lock_warn;
+
+	u8			coex_table_type;
+	boolean			force_lps_ctrl;
+	boolean			concurrent_rx_mode_on;
+	u16			score_board;
+	u8			isolation_btween_wb;   /* 0~ 50 */
+
+	u8			a2dp_bit_pool;
+	u8			cut_version;
+	boolean			acl_busy;
+	boolean			bt_create_connection;
+
+	u32			bt_coex_supported_feature;
+	u32			bt_coex_supported_version;
+
+	u8			bt_ble_scan_type;
+	u32			bt_ble_scan_para[3];
+
+	boolean			run_time_state;
+	boolean			freeze_coexrun_by_btinfo;
+
+	boolean			is_A2DP_3M;
+	boolean			voice_over_HOGP;
+	u8			bt_info;
+	boolean			is_autoslot;
+	u8			forbidden_slot;
+	u8			hid_busy_num;
+	u8			hid_pair_cnt;
+
+	u32			cnt_remote_name_req;
+	u32			cnt_setup_link;
+	u32			cnt_reinit;
+	u32			cnt_ign_wlan_act;
+	u32			cnt_page;
+	u32			cnt_role_switch;
+
+	u16			bt_reg_vendor_ac;
+	u16			bt_reg_vendor_ae;
+
+	boolean			is_setup_link;
+	u8			wl_noisy_level;
+	u32			gnt_error_cnt;
+
+	u8			bt_afh_map[10];
+	u8			bt_relink_downcount;
+	boolean			is_tdma_btautoslot;
+	boolean			is_tdma_btautoslot_hang;
+
+	u8			switch_band_notify_to;
+	boolean			is_rf_state_off;
+
+	boolean			is_hid_low_pri_tx_overhead;
+	boolean			is_bt_multi_link;
+	boolean			is_bt_a2dp_sink;
+	boolean			is_set_ps_state_fail;
+	u8			cnt_set_ps_state_fail;
+
+	u8			wl_fw_dbg_info[10];
+	u8			wl_rx_rate;
+	u8			wl_tx_rate;
+	u8			wl_rts_rx_rate;
+	u8			wl_center_channel;
+	u8			wl_tx_macid;
+	u8			wl_tx_retry_ratio;
+
+	u16			score_board_WB;
+	boolean			is_hid_rcu;
+	u16			legacy_forbidden_slot;
+	u16			le_forbidden_slot;
+	u8			bt_a2dp_vendor_id;
+	u32			bt_a2dp_device_name;
+	boolean			is_ble_scan_en;
+
+	boolean			is_bt_opp_exist;
+	boolean			gl_wifi_busy;
+	u8			connect_ap_period_cnt;
+
+	boolean			is_bt_reenable;
+	u8			cnt_bt_reenable;
+	boolean			is_wifi_linkscan_process;
+	u8			wl_coex_mode;
+	u8			wl_pnp_wakeup_downcnt;
+	u32			coex_run_cnt;
+};
+
+
+#define  BT_8821C_1ANT_EXT_BAND_SWITCH_USE_DPDT	0
+#define  BT_8821C_1ANT_EXT_BAND_SWITCH_USE_SPDT	1
+
+struct rfe_type_8821c_1ant {
+	u8 rfe_module_type;
+	boolean ext_ant_switch_exist;
+	/* 0:DPDT, 1:SPDT */
+	u8 ext_ant_switch_type;
+	/*  iF 0: DPDT_P=0, DPDT_N=1 => BTG to Main, WL_A+G to Aux */
+	u8 ext_ant_switch_ctrl_polarity;
+
+	boolean ext_band_switch_exist;
+	/* 0:DPDT, 1:SPDT */
+	u8 ext_band_switch_type;
+	u8 ext_band_switch_ctrl_polarity;
+	boolean ant_at_main_port;
+
+	/*  If TRUE:  WLG at BTG, If FALSE: WLG at WLAG */
+	boolean wlg_locate_at_btg;
+
+	/* If diversity on */
+	boolean ext_ant_switch_diversity;
+};
+
+struct wifi_link_info_8821c_1ant {
+	u8				num_of_active_port;
+	u32				port_connect_status;
+	boolean				is_all_under_5g;
+	boolean				is_mcc_25g;
+	boolean				is_p2p_connected;
+};
+
+/* *******************************************
+ * The following is interface which will notify coex module.
+ * ******************************************* */
+void ex_halbtc8821c1ant_power_on_setting(struct btc_coexist *btc);
+void ex_halbtc8821c1ant_pre_load_firmware(struct btc_coexist *btc);
+void ex_halbtc8821c1ant_init_hw_config(struct btc_coexist *btc,
+				       boolean wifi_only);
+void ex_halbtc8821c1ant_init_coex_dm(struct btc_coexist *btc);
+void ex_halbtc8821c1ant_ips_notify(struct btc_coexist *btc,
+				   u8 type);
+void ex_halbtc8821c1ant_lps_notify(struct btc_coexist *btc,
+				   u8 type);
+void ex_halbtc8821c1ant_scan_notify(struct btc_coexist *btc,
+				    u8 type);
+void ex_halbtc8821c1ant_switchband_notify(struct btc_coexist *btc,
+					  u8 type);
+void ex_halbtc8821c1ant_connect_notify(struct btc_coexist *btc,
+				       u8 type);
+void ex_halbtc8821c1ant_media_status_notify(struct btc_coexist *btc,
+					    u8 type);
+void ex_halbtc8821c1ant_specific_packet_notify(struct btc_coexist *btc,
+					       u8 type);
+void ex_halbtc8821c1ant_bt_info_notify(struct btc_coexist *btc,
+				       u8 *tmp_buf,  u8 length);
+void ex_halbtc8821c1ant_wl_fwdbginfo_notify(struct btc_coexist *btc,
+					    u8 *tmp_buf, u8 length);
+void ex_halbtc8821c1ant_rx_rate_change_notify(struct btc_coexist *btc,
+					      BOOLEAN is_data_frame,
+					      u8 btc_rate_id);
+void ex_halbtc8821c1ant_tx_rate_change_notify(struct btc_coexist *btc,
+					      u8 tx_rate,
+					      u8 tx_retry_ratio, u8 macid);
+void ex_halbtc8821c1ant_rf_status_notify(struct btc_coexist *btc,
+					 u8 type);
+void ex_halbtc8821c1ant_halt_notify(struct btc_coexist *btc);
+void ex_halbtc8821c1ant_pnp_notify(struct btc_coexist *btc,
+				   u8 pnp_state);
+void ex_halbtc8821c1ant_coex_dm_reset(struct btc_coexist *btc);
+void ex_halbtc8821c1ant_periodical(struct btc_coexist *btc);
+void ex_halbtc8821c1ant_display_simple_coex_info(struct btc_coexist *btc);
+void ex_halbtc8821c1ant_display_coex_info(struct btc_coexist *btc);
+
+#else
+#define ex_halbtc8821c1ant_power_on_setting(btc)
+#define ex_halbtc8821c1ant_pre_load_firmware(btc)
+#define ex_halbtc8821c1ant_init_hw_config(btc, wifi_only)
+#define ex_halbtc8821c1ant_init_coex_dm(btc)
+#define ex_halbtc8821c1ant_ips_notify(btc, type)
+#define ex_halbtc8821c1ant_lps_notify(btc, type)
+#define ex_halbtc8821c1ant_scan_notify(btc, type)
+#define ex_halbtc8821c1ant_switchband_notify(btc, type)
+#define ex_halbtc8821c1ant_connect_notify(btc, type)
+#define ex_halbtc8821c1ant_media_status_notify(btc, type)
+#define ex_halbtc8821c1ant_specific_packet_notify(btc, type)
+#define ex_halbtc8821c1ant_bt_info_notify(btc, tmp_buf, length)
+#define ex_halbtc8821c1ant_wl_fwdbginfo_notify(btc, tmp_buf, length)
+#define ex_halbtc8821c1ant_rx_rate_change_notify(btc, is_data_frame,     \
+						 btc_rate_id)
+#define ex_halbtc8821c1ant_tx_rate_change_notify(btcoexist, tx_rate,     \
+						tx_retry_ratio, macid)
+#define ex_halbtc8821c1ant_rf_status_notify(btc, type)
+#define ex_halbtc8821c1ant_halt_notify(btc)
+#define ex_halbtc8821c1ant_pnp_notify(btc, pnp_state)
+#define ex_halbtc8821c1ant_coex_dm_reset(btc)
+#define ex_halbtc8821c1ant_periodical(btc)
+#define ex_halbtc8821c1ant_display_simple_coex_info(btc)
+#define ex_halbtc8821c1ant_display_coex_info(btc)
+#endif
+
+#endif
+
+
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/btc/halbtc8821c2ant.c linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/btc/halbtc8821c2ant.c
--- linux-5.6.3/3rdparty/rtl8821ce/hal/btc/halbtc8821c2ant.c	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/btc/halbtc8821c2ant.c	2020-04-10 16:35:06.785658620 +0300
@@ -0,0 +1,6191 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2016 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+
+#include "mp_precomp.h"
+
+#if (BT_SUPPORT == 1 && COEX_SUPPORT == 1)
+
+#if (RTL8821C_SUPPORT == 1)
+static u8	*trace_buf = &gl_btc_trace_buf[0];
+
+const char *const glbt_info_src_8821c_2ant[] = {
+	"BT Info[wifi fw]",
+	"BT Info[bt rsp]",
+	"BT Info[bt auto report]",
+};
+
+u32 glcoex_ver_date_8821c_2ant = 20180712;
+u32 glcoex_ver_8821c_2ant = 0x32;
+u32 glcoex_ver_btdesired_8821c_2ant = 0x28;
+
+static
+u8 halbtc8821c2ant_bt_rssi_state(struct btc_coexist *btc,
+				 u8 *ppre_bt_rssi_state, u8 level_num,
+				 u8 rssi_thresh, u8 rssi_thresh1)
+{
+	struct coex_sta_8821c_2ant *coex_sta = &btc->coex_sta_8821c_2ant;
+	s32 bt_rssi = 0;
+	u8 bt_rssi_state = *ppre_bt_rssi_state;
+
+	bt_rssi = coex_sta->bt_rssi;
+
+	if (level_num == 2) {
+		if ((*ppre_bt_rssi_state == BTC_RSSI_STATE_LOW) ||
+		    (*ppre_bt_rssi_state == BTC_RSSI_STATE_STAY_LOW)) {
+			if (bt_rssi >= (rssi_thresh +
+					BTC_RSSI_COEX_THRESH_TOL_8821C_2ANT))
+				bt_rssi_state = BTC_RSSI_STATE_HIGH;
+			else
+				bt_rssi_state = BTC_RSSI_STATE_STAY_LOW;
+		} else {
+			if (bt_rssi < rssi_thresh)
+				bt_rssi_state = BTC_RSSI_STATE_LOW;
+			else
+				bt_rssi_state = BTC_RSSI_STATE_STAY_HIGH;
+		}
+	} else if (level_num == 3) {
+		if (rssi_thresh > rssi_thresh1) {
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				    "[BTCoex], BT Rssi thresh error!!\n");
+			BTC_TRACE(trace_buf);
+			return *ppre_bt_rssi_state;
+		}
+
+		if ((*ppre_bt_rssi_state == BTC_RSSI_STATE_LOW) ||
+		    (*ppre_bt_rssi_state == BTC_RSSI_STATE_STAY_LOW)) {
+			if (bt_rssi >= (rssi_thresh +
+					BTC_RSSI_COEX_THRESH_TOL_8821C_2ANT))
+				bt_rssi_state = BTC_RSSI_STATE_MEDIUM;
+			else
+				bt_rssi_state = BTC_RSSI_STATE_STAY_LOW;
+		} else if ((*ppre_bt_rssi_state == BTC_RSSI_STATE_MEDIUM) ||
+			(*ppre_bt_rssi_state == BTC_RSSI_STATE_STAY_MEDIUM)) {
+			if (bt_rssi >= (rssi_thresh1 +
+					BTC_RSSI_COEX_THRESH_TOL_8821C_2ANT))
+				bt_rssi_state = BTC_RSSI_STATE_HIGH;
+			else if (bt_rssi < rssi_thresh)
+				bt_rssi_state = BTC_RSSI_STATE_LOW;
+			else
+				bt_rssi_state = BTC_RSSI_STATE_STAY_MEDIUM;
+		} else {
+			if (bt_rssi < rssi_thresh1)
+				bt_rssi_state = BTC_RSSI_STATE_MEDIUM;
+			else
+				bt_rssi_state = BTC_RSSI_STATE_STAY_HIGH;
+		}
+	}
+
+	*ppre_bt_rssi_state = bt_rssi_state;
+
+	return bt_rssi_state;
+}
+
+static
+u8 halbtc8821c2ant_wifi_rssi_state(struct btc_coexist *btc,
+				   u8 *pprewifi_rssi_state,
+				   u8 level_num,
+				   u8 rssi_thresh, u8 rssi_thresh1)
+{
+	s32 wifi_rssi = 0;
+	u8 wifi_rssi_state = *pprewifi_rssi_state;
+
+	btc->btc_get(btc, BTC_GET_S4_WIFI_RSSI, &wifi_rssi);
+
+	if (level_num == 2) {
+		if ((*pprewifi_rssi_state == BTC_RSSI_STATE_LOW) ||
+		    (*pprewifi_rssi_state == BTC_RSSI_STATE_STAY_LOW)) {
+			if (wifi_rssi >= (rssi_thresh +
+					  BTC_RSSI_COEX_THRESH_TOL_8821C_2ANT))
+				wifi_rssi_state = BTC_RSSI_STATE_HIGH;
+			else
+				wifi_rssi_state = BTC_RSSI_STATE_STAY_LOW;
+		} else {
+			if (wifi_rssi < rssi_thresh)
+				wifi_rssi_state = BTC_RSSI_STATE_LOW;
+			else
+				wifi_rssi_state = BTC_RSSI_STATE_STAY_HIGH;
+		}
+	} else if (level_num == 3) {
+		if (rssi_thresh > rssi_thresh1) {
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				    "[BTCoex], wifi RSSI thresh error!!\n");
+			BTC_TRACE(trace_buf);
+			return *pprewifi_rssi_state;
+		}
+
+		if ((*pprewifi_rssi_state == BTC_RSSI_STATE_LOW) ||
+		    (*pprewifi_rssi_state == BTC_RSSI_STATE_STAY_LOW)) {
+			if (wifi_rssi >= (rssi_thresh +
+					  BTC_RSSI_COEX_THRESH_TOL_8821C_2ANT))
+				wifi_rssi_state = BTC_RSSI_STATE_MEDIUM;
+			else
+				wifi_rssi_state = BTC_RSSI_STATE_STAY_LOW;
+		} else if ((*pprewifi_rssi_state == BTC_RSSI_STATE_MEDIUM) ||
+			(*pprewifi_rssi_state == BTC_RSSI_STATE_STAY_MEDIUM)) {
+			if (wifi_rssi >= (rssi_thresh1 +
+					  BTC_RSSI_COEX_THRESH_TOL_8821C_2ANT))
+				wifi_rssi_state = BTC_RSSI_STATE_HIGH;
+			else if (wifi_rssi < rssi_thresh)
+				wifi_rssi_state = BTC_RSSI_STATE_LOW;
+			else
+				wifi_rssi_state = BTC_RSSI_STATE_STAY_MEDIUM;
+		} else {
+			if (wifi_rssi < rssi_thresh1)
+				wifi_rssi_state = BTC_RSSI_STATE_MEDIUM;
+			else
+				wifi_rssi_state = BTC_RSSI_STATE_STAY_HIGH;
+		}
+	}
+
+	*pprewifi_rssi_state = wifi_rssi_state;
+
+	return wifi_rssi_state;
+}
+
+static
+void halbtc8821c2ant_coex_switch_thres(struct btc_coexist *btc,
+				       u8 isolation_measuared)
+{
+	struct coex_sta_8821c_2ant *coex_sta = &btc->coex_sta_8821c_2ant;
+	s8	interference_wl_tx = 0, interference_bt_tx = 0;
+
+	interference_wl_tx = BT_8821C_2ANT_WIFI_MAX_TX_POWER -
+						isolation_measuared;
+	interference_bt_tx = BT_8821C_2ANT_BT_MAX_TX_POWER -
+						isolation_measuared;
+
+	coex_sta->wifi_coex_thres = BT_8821C_2ANT_WIFI_RSSI_COEXSWITCH_THRES1;
+	coex_sta->wifi_coex_thres2 =  BT_8821C_2ANT_WIFI_RSSI_COEXSWITCH_THRES2;
+
+	coex_sta->bt_coex_thres	= BT_8821C_2ANT_BT_RSSI_COEXSWITCH_THRES1;
+	coex_sta->bt_coex_thres2 = BT_8821C_2ANT_BT_RSSI_COEXSWITCH_THRES2;
+
+#if 0
+	coex_sta->wifi_coex_thres =
+		interference_wl_tx + BT_8821C_2ANT_WIFI_SIR_THRES1;
+	coex_sta->wifi_coex_thres2 =
+		interference_wl_tx + BT_8821C_2ANT_WIFI_SIR_THRES2;
+
+	coex_sta->bt_coex_thres	=
+		interference_bt_tx + BT_8821C_2ANT_BT_SIR_THRES1;
+	coex_sta->bt_coex_thres2 =
+		interference_bt_tx + BT_8821C_2ANT_BT_SIR_THRES2;
+
+	if  (BT_8821C_2ANT_WIFI_RSSI_COEXSWITCH_THRES1 <
+		(isolation_measuared - BT_8821C_2ANT_DEFAULT_ISOLATION))
+		coex_sta->wifi_coex_thres =
+				BT_8821C_2ANT_WIFI_RSSI_COEXSWITCH_THRES1;
+	else
+		coex_sta->wifi_coex_thres =
+		BT_8821C_2ANT_WIFI_RSSI_COEXSWITCH_THRES1 -
+		  (isolation_measuared - BT_8821C_2ANT_DEFAULT_ISOLATION);
+
+	if  (BT_8821C_2ANT_BT_RSSI_COEXSWITCH_THRES1 <
+		(isolation_measuared - BT_8821C_2ANT_DEFAULT_ISOLATION))
+		coex_sta->bt_coex_thres	=
+				 BT_8821C_2ANT_BT_RSSI_COEXSWITCH_THRES1;
+	else
+		coex_sta->bt_coex_thres =
+		BT_8821C_2ANT_BT_RSSI_COEXSWITCH_THRES1 -
+		 (isolation_measuared - BT_8821C_2ANT_DEFAULT_ISOLATION);
+
+#endif
+}
+
+static
+void halbtc8821c2ant_low_penalty_ra(struct btc_coexist *btc,
+				    boolean force_exec, boolean low_penalty_ra,
+				    u8 thres)
+{
+	struct coex_dm_8821c_2ant *coex_dm = &btc->coex_dm_8821c_2ant;
+	static u8 cur_thres;
+
+	if (!force_exec) {
+		if (low_penalty_ra == coex_dm->cur_low_penalty_ra &&
+		    thres == cur_thres)
+			return;
+	}
+
+	if (low_penalty_ra)
+		btc->btc_phydm_modify_RA_PCR_threshold(btc, 0, thres);
+	else
+		btc->btc_phydm_modify_RA_PCR_threshold(btc, 0, 0);
+
+	coex_dm->cur_low_penalty_ra = low_penalty_ra;
+	cur_thres = thres;
+}
+
+static
+void halbtc8821c2ant_set_antdiv_hwsw(struct btc_coexist *btc,
+				     boolean force_exec, boolean is_hw_div)
+{
+	struct coex_dm_8821c_2ant *coex_dm = &btc->coex_dm_8821c_2ant;
+	static u8 pre_antdiv_type;
+
+	coex_dm->cur_antdiv_type =  ((is_hw_div) ? 1 : 0);
+
+	if (!force_exec) {
+		if (coex_dm->cur_antdiv_type == pre_antdiv_type)
+			return;
+	}
+
+	btc->btc_phydm_modify_antdiv_hwsw(btc, coex_dm->cur_antdiv_type);
+
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+		    "[BTCoex], %s = %d!!\n", __func__,
+		    coex_dm->cur_antdiv_type);
+	BTC_TRACE(trace_buf);
+
+	pre_antdiv_type = coex_dm->cur_antdiv_type;
+}
+
+static
+void halbtc8821c2ant_write_scbd(struct btc_coexist *btc, u16 bitpos,
+				boolean state)
+{
+	struct coex_sta_8821c_2ant *coex_sta = &btc->coex_sta_8821c_2ant;
+	static u16 originalval = 0x8002, preval;
+
+	if (state)
+		originalval = originalval | bitpos;
+	else
+		originalval = originalval & (~bitpos);
+
+	coex_sta->score_board_WB = originalval;
+
+	if (originalval != preval) {
+		preval = originalval;
+		btc->btc_write_2byte(btc, 0xaa, originalval);
+	} else {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], %s: return for nochange\n", __func__);
+		BTC_TRACE(trace_buf);
+	}
+}
+
+static
+void halbtc8821c2ant_read_scbd(struct btc_coexist *btc, u16 *score_board_val)
+{
+	*score_board_val = (btc->btc_read_2byte(btc, 0xaa)) & 0x7fff;
+}
+
+static
+void halbtc8821c2ant_query_bt_info(struct btc_coexist *btc)
+{
+	struct coex_sta_8821c_2ant *coex_sta = &btc->coex_sta_8821c_2ant;
+	u8 h2c_parameter[1] = {0};
+
+	if (coex_sta->bt_disabled) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			"[BTCoex], No query BT info because BT is disabled!\n");
+		BTC_TRACE(trace_buf);
+		return;
+	}
+
+	h2c_parameter[0] |= BIT(0);	/* trigger */
+
+	btc->btc_fill_h2c(btc, 0x61, 1, h2c_parameter);
+}
+
+static
+void halbtc8821c2ant_enable_gnt_to_gpio(struct btc_coexist *btc,
+					boolean isenable)
+{
+	static u8	bit_val[5] = {0, 0, 0, 0, 0};
+	static boolean state;
+
+	if (!btc->dbg_mode)
+		return;
+
+	if (state == isenable)
+		return;
+
+	state = isenable;
+
+	if (isenable) {
+		/* enable GNT_WL, GNT_BT to GPIO for debug */
+		btc->btc_write_1byte_bitmask(btc, 0x73, 0x8, 0x1);
+
+		/* store original value */
+		/*0x66[4] */
+		bit_val[0] = (btc->btc_read_1byte(btc, 0x66) & BIT(4)) >> 4;
+		/*0x66[8] */
+		bit_val[1] = (btc->btc_read_1byte(btc, 0x67) & BIT(0));
+		/*0x40[19] */
+		bit_val[2] = (btc->btc_read_1byte(btc, 0x42) & BIT(3)) >> 3;
+		/*0x64[15] */
+		bit_val[3] = (btc->btc_read_1byte(btc, 0x65) & BIT(7)) >> 7;
+		/*0x70[18] */
+		bit_val[4] = (btc->btc_read_1byte(btc, 0x72) & BIT(2)) >> 2;
+
+		/*  switch GPIO Mux */
+		/*0x66[4] = 0 */
+		btc->btc_write_1byte_bitmask(btc, 0x66, BIT(4), 0x0);
+		/*0x66[8] = 0 */
+		btc->btc_write_1byte_bitmask(btc, 0x67, BIT(0), 0x0);
+		/*0x40[19] = 0 */
+		btc->btc_write_1byte_bitmask(btc, 0x42, BIT(3), 0x0);
+		/*0x64[15] = 0 */
+		btc->btc_write_1byte_bitmask(btc, 0x65, BIT(7), 0x0);
+		 /*0x70[18] = 0 */
+		btc->btc_write_1byte_bitmask(btc, 0x72, BIT(2), 0x0);
+	} else {
+		btc->btc_write_1byte_bitmask(btc, 0x73, 0x8, 0x0);
+
+		/*  Restore original value */
+		/*  switch GPIO Mux */
+		/*0x66[4] = 0 */
+		btc->btc_write_1byte_bitmask(btc, 0x66, BIT(4), bit_val[0]);
+		/*0x66[8] = 0 */
+		btc->btc_write_1byte_bitmask(btc, 0x67, BIT(0), bit_val[1]);
+		/*0x40[19] = 0 */
+		btc->btc_write_1byte_bitmask(btc, 0x42, BIT(3), bit_val[2]);
+		/*0x64[15] = 0 */
+		btc->btc_write_1byte_bitmask(btc, 0x65, BIT(7), bit_val[3]);
+		/*0x70[18] = 0 */
+		btc->btc_write_1byte_bitmask(btc, 0x72, BIT(2), bit_val[4]);
+	}
+}
+
+static
+void halbtc8821c2ant_monitor_bt_ctr(struct btc_coexist *btc)
+{
+	struct coex_sta_8821c_2ant *coex_sta = &btc->coex_sta_8821c_2ant;
+	struct coex_dm_8821c_2ant *coex_dm = &btc->coex_dm_8821c_2ant;
+	u32 reg_hp_txrx, reg_lp_txrx, u32tmp;
+	u32 reg_hp_tx = 0, reg_hp_rx = 0, reg_lp_tx = 0, reg_lp_rx = 0;
+	static u8	num_of_bt_counter_chk, cnt_slave, cnt_overhead,
+		cnt_autoslot_hang;
+	struct  btc_bt_link_info *bt_link_info = &btc->bt_link_info;
+
+	reg_hp_txrx = 0x770;
+	reg_lp_txrx = 0x774;
+
+	u32tmp = btc->btc_read_4byte(btc, reg_hp_txrx);
+	reg_hp_tx = u32tmp & MASKLWORD;
+	reg_hp_rx = (u32tmp & MASKHWORD) >> 16;
+
+	u32tmp = btc->btc_read_4byte(btc, reg_lp_txrx);
+	reg_lp_tx = u32tmp & MASKLWORD;
+	reg_lp_rx = (u32tmp & MASKHWORD) >> 16;
+
+	coex_sta->high_priority_tx = reg_hp_tx;
+	coex_sta->high_priority_rx = reg_hp_rx;
+	coex_sta->low_priority_tx = reg_lp_tx;
+	coex_sta->low_priority_rx = reg_lp_rx;
+
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+		    "[BTCoex], Hi-Pri Rx/Tx: %d/%d, Lo-Pri Rx/Tx: %d/%d\n",
+		    reg_hp_rx, reg_hp_tx, reg_lp_rx, reg_lp_tx);
+
+	BTC_TRACE(trace_buf);
+
+	if (coex_dm->bt_status == BT_8821C_2ANT_BSTATUS_NCON_IDLE) {
+
+		if (coex_sta->high_priority_rx >= 15) {
+			if (cnt_overhead < 3)
+				cnt_overhead++;
+
+			if (cnt_overhead == 3)
+				coex_sta->is_hi_pri_rx_overhead = TRUE;
+
+		} else {
+			if (cnt_overhead > 0)
+				cnt_overhead--;
+
+			if (cnt_overhead == 0)
+				coex_sta->is_hi_pri_rx_overhead = FALSE;
+		}
+	} else
+		coex_sta->is_hi_pri_rx_overhead = FALSE;
+
+	/* reset counter */
+	btc->btc_write_1byte(btc, 0x76e, 0xc);
+
+	if (coex_sta->low_priority_tx > 1150 &&
+	    !coex_sta->c2h_bt_inquiry_page)
+		coex_sta->pop_event_cnt++;
+
+	if (coex_sta->low_priority_rx >= 1150 &&
+	    coex_sta->low_priority_rx >= coex_sta->low_priority_tx &&
+	    !coex_sta->under_ips && !coex_sta->c2h_bt_inquiry_page &&
+	    (bt_link_info->a2dp_exist || bt_link_info->pan_exist)) {
+		if (cnt_slave >= 2) {
+			bt_link_info->slave_role = TRUE;
+			cnt_slave = 2;
+		} else
+			cnt_slave++;
+	} else {
+		if (cnt_slave == 0)	{
+			bt_link_info->slave_role = FALSE;
+			cnt_slave = 0;
+		} else
+			cnt_slave--;
+	}
+
+	if (coex_sta->is_tdma_btautoslot) {
+		if (coex_sta->low_priority_tx >= 1300 &&
+		    coex_sta->low_priority_rx <= 150) {
+			if (cnt_autoslot_hang >= 2) {
+				coex_sta->is_tdma_btautoslot_hang = TRUE;
+				cnt_autoslot_hang = 2;
+			} else
+				cnt_autoslot_hang++;
+		} else {
+			if (cnt_autoslot_hang == 0)	{
+				coex_sta->is_tdma_btautoslot_hang = FALSE;
+				cnt_autoslot_hang = 0;
+			} else
+				cnt_autoslot_hang--;
+		}
+	}
+
+	if (coex_sta->sco_exist) {
+		if (coex_sta->high_priority_tx >= 400 &&
+		    coex_sta->high_priority_rx >= 400)
+			coex_sta->is_esco_mode = FALSE;
+		else
+			coex_sta->is_esco_mode = TRUE;
+	}
+
+	if (bt_link_info->hid_only) {
+		if (coex_sta->low_priority_tx > 100)
+			coex_sta->is_hid_low_pri_tx_overhead = true;
+		else
+			coex_sta->is_hid_low_pri_tx_overhead = false;
+	}
+
+	if (!coex_sta->bt_disabled) {
+		if (coex_sta->high_priority_tx == 0 &&
+		    coex_sta->high_priority_rx == 0 &&
+		    coex_sta->low_priority_tx == 0 &&
+		    coex_sta->low_priority_rx == 0) {
+			num_of_bt_counter_chk++;
+			if (num_of_bt_counter_chk >= 3) {
+				halbtc8821c2ant_query_bt_info(btc);
+				num_of_bt_counter_chk = 0;
+			}
+		}
+	}
+}
+
+static
+void halbtc8821c2ant_monitor_wifi_ctr(struct btc_coexist *btc)
+{
+	struct coex_sta_8821c_2ant *coex_sta = &btc->coex_sta_8821c_2ant;
+	struct coex_dm_8821c_2ant *coex_dm = &btc->coex_dm_8821c_2ant;
+	boolean wifi_busy = FALSE, wifi_scan = FALSE;
+	static u8 wl_noisy_count0, wl_noisy_count1 = 3, wl_noisy_count2;
+	u32 cnt_cck;
+	static u8 cnt_ccklocking;
+	u8 h2c_parameter[1] = {0};
+	struct  btc_bt_link_info *bt_link_info = &btc->bt_link_info;
+
+	/* Only enable for windows becaus 8821cu
+	 * H2C 0x69 unknown fail @ linux
+	 */
+	if (btc->chip_interface != BTC_INTF_USB) {
+		/*send h2c to query WL FW dbg info  */
+		if ((coex_dm->cur_ps_tdma_on && coex_sta->force_lps_ctrl) ||
+		    (coex_sta->acl_busy && bt_link_info->a2dp_exist)) {
+			h2c_parameter[0] = 0x8;
+			btc->btc_fill_h2c(btc, 0x69, 1, h2c_parameter);
+		}
+	}
+
+	btc->btc_get(btc, BTC_GET_BL_WIFI_BUSY, &wifi_busy);
+	btc->btc_get(btc, BTC_GET_BL_WIFI_SCAN, &wifi_scan);
+
+	coex_sta->crc_ok_cck =
+		btc->btc_phydm_query_PHY_counter(btc, PHYDM_INFO_CRC32_OK_CCK);
+	coex_sta->crc_ok_11g =
+	    btc->btc_phydm_query_PHY_counter(btc, PHYDM_INFO_CRC32_OK_LEGACY);
+	coex_sta->crc_ok_11n =
+		btc->btc_phydm_query_PHY_counter(btc, PHYDM_INFO_CRC32_OK_HT);
+	coex_sta->crc_ok_11n_vht =
+		btc->btc_phydm_query_PHY_counter(btc, PHYDM_INFO_CRC32_OK_VHT);
+
+	coex_sta->crc_err_cck =
+	    btc->btc_phydm_query_PHY_counter(btc, PHYDM_INFO_CRC32_ERROR_CCK);
+	coex_sta->crc_err_11g =
+	  btc->btc_phydm_query_PHY_counter(btc, PHYDM_INFO_CRC32_ERROR_LEGACY);
+	coex_sta->crc_err_11n =
+	    btc->btc_phydm_query_PHY_counter(btc, PHYDM_INFO_CRC32_ERROR_HT);
+	coex_sta->crc_err_11n_vht =
+	    btc->btc_phydm_query_PHY_counter(btc, PHYDM_INFO_CRC32_ERROR_VHT);
+
+	/* CCK lock identification */
+	if (coex_sta->cck_lock)
+		cnt_ccklocking++;
+	else if	(cnt_ccklocking != 0)
+		cnt_ccklocking--;
+
+	if (cnt_ccklocking >= 3) {
+		cnt_ccklocking = 3;
+		coex_sta->cck_lock_ever = TRUE;
+	}
+
+	/* WiFi environment noisy identification */
+	cnt_cck = coex_sta->crc_ok_cck + coex_sta->crc_err_cck;
+
+	if (!wifi_busy && !coex_sta->cck_lock) {
+		if (cnt_cck > 250) {
+			if (wl_noisy_count2 < 3)
+				wl_noisy_count2++;
+
+			if (wl_noisy_count2 == 3) {
+				wl_noisy_count0 = 0;
+				wl_noisy_count1 = 0;
+			}
+
+		} else if (cnt_cck < 100) {
+			if (wl_noisy_count0 < 3)
+				wl_noisy_count0++;
+
+			if (wl_noisy_count0 == 3) {
+				wl_noisy_count1 = 0;
+				wl_noisy_count2 = 0;
+			}
+
+		} else {
+			if (wl_noisy_count1 < 3)
+				wl_noisy_count1++;
+
+			if (wl_noisy_count1 == 3) {
+				wl_noisy_count0 = 0;
+				wl_noisy_count2 = 0;
+			}
+		}
+
+		if (wl_noisy_count2 == 3)
+			coex_sta->wl_noisy_level = 2;
+		else if (wl_noisy_count1 == 3)
+			coex_sta->wl_noisy_level = 1;
+		else
+			coex_sta->wl_noisy_level = 0;
+	}
+}
+
+static
+void halbtc8821c2ant_monitor_bt_enable(struct btc_coexist *btc)
+{
+	struct coex_sta_8821c_2ant *coex_sta = &btc->coex_sta_8821c_2ant;
+	static u32 bt_disable_cnt;
+	boolean	bt_active = TRUE, bt_disabled = FALSE;
+	u16 u16tmp;
+
+	/* Read BT on/off status from scoreboard[1],
+	 * enable this only if BT patch support this feature
+	 */
+	halbtc8821c2ant_read_scbd(btc, &u16tmp);
+
+	bt_active = u16tmp & BIT(1);
+
+	if (bt_active) {
+		bt_disable_cnt = 0;
+		bt_disabled = FALSE;
+		btc->btc_set(btc, BTC_SET_BL_BT_DISABLE, &bt_disabled);
+	} else {
+		bt_disable_cnt++;
+		if (bt_disable_cnt >= 2) {
+			bt_disabled = TRUE;
+			bt_disable_cnt = 2;
+		}
+
+		btc->btc_set(btc, BTC_SET_BL_BT_DISABLE, &bt_disabled);
+	}
+
+	if (coex_sta->bt_disabled != bt_disabled) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], BT is from %s to %s!!\n",
+			    (coex_sta->bt_disabled ? "disabled" : "enabled"),
+			    (bt_disabled ? "disabled" : "enabled"));
+		BTC_TRACE(trace_buf);
+		coex_sta->bt_disabled = bt_disabled;
+
+		/*for win10 BT disable->enable trigger wifi scan issue   */
+		if (!coex_sta->bt_disabled) {
+			coex_sta->is_bt_reenable = TRUE;
+			coex_sta->cnt_bt_reenable = 15;
+		} else {
+			coex_sta->is_bt_reenable = FALSE;
+			coex_sta->cnt_bt_reenable = 0;
+		}
+	}
+}
+
+static
+boolean halbtc8821c2ant_moniter_wifibt_status(struct btc_coexist
+		*btc)
+{
+	struct coex_sta_8821c_2ant *coex_sta = &btc->coex_sta_8821c_2ant;
+	struct wifi_link_info_8821c_2ant *wifi_link_info_ext =
+					 &btc->wifi_link_info_8821c_2ant;
+	static boolean pre_wifi_busy, pre_under_4way,
+		     pre_bt_off, pre_bt_slave, pre_hid_low_pri_tx_overhead,
+		     pre_wifi_under_lps, pre_bt_setup_link,
+		     pre_cck_lock, pre_cck_lock_warn;
+	static u8 pre_hid_busy_num, pre_wl_noisy_level;
+	boolean wifi_busy = FALSE, under_4way = FALSE;
+	boolean wifi_connected = FALSE;
+	struct	btc_bt_link_info *bt_link_info = &btc->bt_link_info;
+	static u8 cnt_wifi_busytoidle;
+	u32 num_of_wifi_link = 0, wifi_link_mode = 0;
+	static u32 pre_num_of_wifi_link, pre_wifi_link_mode;
+	boolean miracast_plus_bt = FALSE;
+
+	btc->btc_get(btc, BTC_GET_BL_WIFI_CONNECTED, &wifi_connected);
+	btc->btc_get(btc, BTC_GET_BL_WIFI_BUSY, &wifi_busy);
+	btc->btc_get(btc, BTC_GET_BL_WIFI_4_WAY_PROGRESS, &under_4way);
+
+	if (wifi_busy) {
+		coex_sta->gl_wifi_busy = TRUE;
+		cnt_wifi_busytoidle = 6;
+	} else {
+		if (coex_sta->gl_wifi_busy && cnt_wifi_busytoidle > 0)
+			cnt_wifi_busytoidle--;
+		else if (cnt_wifi_busytoidle == 0)
+			coex_sta->gl_wifi_busy = FALSE;
+	}
+
+	if (coex_sta->bt_disabled != pre_bt_off) {
+		pre_bt_off = coex_sta->bt_disabled;
+
+		if (coex_sta->bt_disabled)
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				    "[BTCoex], BT is disabled !!\n");
+		else
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				    "[BTCoex], BT is enabled !!\n");
+
+		BTC_TRACE(trace_buf);
+
+		coex_sta->bt_coex_supported_feature = 0;
+		coex_sta->bt_coex_supported_version = 0;
+		coex_sta->bt_ble_scan_type = 0;
+		coex_sta->bt_ble_scan_para[0] = 0;
+		coex_sta->bt_ble_scan_para[1] = 0;
+		coex_sta->bt_ble_scan_para[2] = 0;
+		coex_sta->bt_reg_vendor_ac = 0xffff;
+		coex_sta->bt_reg_vendor_ae = 0xffff;
+		coex_sta->legacy_forbidden_slot = 0;
+		coex_sta->le_forbidden_slot = 0;
+		coex_sta->bt_a2dp_vendor_id = 0;
+		coex_sta->bt_a2dp_device_name = 0;
+		return TRUE;
+	}
+
+	num_of_wifi_link = wifi_link_info_ext->num_of_active_port;
+
+	if (num_of_wifi_link != pre_num_of_wifi_link) {
+		pre_num_of_wifi_link = num_of_wifi_link;
+
+		if (wifi_link_info_ext->is_p2p_connected) {
+			if (bt_link_info->bt_link_exist)
+				miracast_plus_bt = TRUE;
+			else
+				miracast_plus_bt = FALSE;
+
+			btc->btc_set(btc, BTC_SET_BL_MIRACAST_PLUS_BT,
+				     &miracast_plus_bt);
+		}
+		return TRUE;
+	}
+
+	wifi_link_mode = btc->wifi_link_info.link_mode;
+	if (wifi_link_mode != pre_wifi_link_mode) {
+		pre_wifi_link_mode = wifi_link_mode;
+		return TRUE;
+	}
+
+	if (wifi_connected) {
+		if (wifi_busy != pre_wifi_busy) {
+			pre_wifi_busy = wifi_busy;
+			return TRUE;
+		}
+		if (under_4way != pre_under_4way) {
+			pre_under_4way = under_4way;
+			return TRUE;
+		}
+
+		if (coex_sta->wl_noisy_level != pre_wl_noisy_level) {
+			pre_wl_noisy_level = coex_sta->wl_noisy_level;
+			return TRUE;
+		}
+		if (coex_sta->under_lps != pre_wifi_under_lps) {
+			pre_wifi_under_lps = coex_sta->under_lps;
+			if (coex_sta->under_lps)
+				return TRUE;
+		}
+		if (coex_sta->cck_lock != pre_cck_lock) {
+			pre_cck_lock = coex_sta->cck_lock;
+			return TRUE;
+		}
+		if (coex_sta->cck_lock_warn != pre_cck_lock_warn) {
+			pre_cck_lock_warn = coex_sta->cck_lock_warn;
+			return TRUE;
+		}
+	}
+
+	if (!coex_sta->bt_disabled) {
+#if 0
+		if (coex_sta->acl_busy != pre_bt_acl_busy) {
+			pre_bt_acl_busy = coex_sta->acl_busy;
+			btc->btc_set(btc, BTC_SET_BL_BT_LNA_CONSTRAIN_LEVEL,
+				     &lna_lvl);
+			return TRUE;
+		}
+#endif
+		if (coex_sta->hid_busy_num != pre_hid_busy_num) {
+			pre_hid_busy_num = coex_sta->hid_busy_num;
+			return TRUE;
+		}
+
+		if (bt_link_info->slave_role != pre_bt_slave) {
+			pre_bt_slave = bt_link_info->slave_role;
+			return TRUE;
+		}
+
+		if (pre_hid_low_pri_tx_overhead !=
+				coex_sta->is_hid_low_pri_tx_overhead) {
+			pre_hid_low_pri_tx_overhead =
+				coex_sta->is_hid_low_pri_tx_overhead;
+			return TRUE;
+		}
+
+		if (pre_bt_setup_link != coex_sta->is_setup_link) {
+			pre_bt_setup_link = coex_sta->is_setup_link;
+			return TRUE;
+		}
+	}
+
+	return FALSE;
+}
+
+static
+void halbtc8821c2ant_update_wifi_link_info(struct btc_coexist *btc, u8 reason)
+{
+	struct coex_sta_8821c_2ant *coex_sta = &btc->coex_sta_8821c_2ant;
+	struct wifi_link_info_8821c_2ant *wifi_link_info_ext =
+					 &btc->wifi_link_info_8821c_2ant;
+	struct btc_wifi_link_info wifi_link_info;
+	u8 wifi_central_chnl = 0, num_of_wifi_link = 0;
+	boolean isunder5G = FALSE, ismcc25g = FALSE, isp2pconnected = FALSE;
+	u32 wifi_link_status = 0;
+
+	btc->btc_get(btc, BTC_GET_U4_WIFI_LINK_STATUS, &wifi_link_status);
+	wifi_link_info_ext->port_connect_status = wifi_link_status & 0xffff;
+
+	btc->btc_get(btc, BTC_GET_BL_WIFI_LINK_INFO, &wifi_link_info);
+	btc->wifi_link_info = wifi_link_info;
+
+	btc->btc_get(btc, BTC_GET_U1_WIFI_CENTRAL_CHNL, &wifi_central_chnl);
+	coex_sta->wl_center_channel = wifi_central_chnl;
+
+	/* Check scan/connect/special-pkt action first  */
+	switch (reason) {
+	case BT_8821C_2ANT_RSN_5GSCANSTART:
+	case BT_8821C_2ANT_RSN_5GSWITCHBAND:
+	case BT_8821C_2ANT_RSN_5GCONSTART:
+		isunder5G = TRUE;
+		break;
+	case BT_8821C_2ANT_RSN_2GSCANSTART:
+	case BT_8821C_2ANT_RSN_2GSWITCHBAND:
+	case BT_8821C_2ANT_RSN_2GCONSTART:
+		isunder5G = FALSE;
+		break;
+	case BT_8821C_2ANT_RSN_2GCONFINISH:
+	case BT_8821C_2ANT_RSN_5GCONFINISH:
+	case BT_8821C_2ANT_RSN_2GMEDIA:
+	case BT_8821C_2ANT_RSN_5GMEDIA:
+	case BT_8821C_2ANT_RSN_BTINFO:
+	case BT_8821C_2ANT_RSN_PERIODICAL:
+	case BT_8821C_2ANT_RSN_2GSPECIALPKT:
+	case BT_8821C_2ANT_RSN_5GSPECIALPKT:
+	default:
+		switch (wifi_link_info.link_mode) {
+		case BTC_LINK_5G_MCC_GO_STA:
+		case BTC_LINK_5G_MCC_GC_STA:
+		case BTC_LINK_5G_SCC_GO_STA:
+		case BTC_LINK_5G_SCC_GC_STA:
+			isunder5G = TRUE;
+			break;
+		case BTC_LINK_2G_MCC_GO_STA:
+		case BTC_LINK_2G_MCC_GC_STA:
+		case BTC_LINK_2G_SCC_GO_STA:
+		case BTC_LINK_2G_SCC_GC_STA:
+			isunder5G = FALSE;
+			break;
+		case BTC_LINK_25G_MCC_GO_STA:
+		case BTC_LINK_25G_MCC_GC_STA:
+			isunder5G = FALSE;
+			ismcc25g = TRUE;
+			break;
+		case BTC_LINK_ONLY_STA:
+			if (wifi_link_info.sta_center_channel > 14)
+				isunder5G = TRUE;
+			else
+				isunder5G = FALSE;
+			break;
+		case BTC_LINK_ONLY_GO:
+		case BTC_LINK_ONLY_GC:
+		case BTC_LINK_ONLY_AP:
+		default:
+			if (wifi_link_info.p2p_center_channel > 14)
+				isunder5G = TRUE;
+			else
+				isunder5G = FALSE;
+
+			break;
+		}
+		break;
+	}
+
+	wifi_link_info_ext->is_all_under_5g = isunder5G;
+	wifi_link_info_ext->is_mcc_25g = ismcc25g;
+
+	if (wifi_link_status & WIFI_STA_CONNECTED)
+		num_of_wifi_link++;
+
+	if (wifi_link_status & WIFI_AP_CONNECTED)
+		num_of_wifi_link++;
+
+	if (wifi_link_status & WIFI_P2P_GO_CONNECTED) {
+		num_of_wifi_link++;
+		isp2pconnected = TRUE;
+	}
+
+	if (wifi_link_status & WIFI_P2P_GC_CONNECTED) {
+		num_of_wifi_link++;
+		isp2pconnected = TRUE;
+	}
+
+	wifi_link_info_ext->num_of_active_port = num_of_wifi_link;
+	wifi_link_info_ext->is_p2p_connected = isp2pconnected;
+
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+		    "[BTCoex], wifi_link_info: link_mode=%d, STA_Ch=%d, P2P_Ch=%d, AnyClient_Join_Go=%d !\n",
+		    btc->wifi_link_info.link_mode,
+		    btc->wifi_link_info.sta_center_channel,
+		    btc->wifi_link_info.p2p_center_channel,
+		    btc->wifi_link_info.bany_client_join_go);
+	BTC_TRACE(trace_buf);
+
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+		    "[BTCoex], wifi_link_info: center_ch=%d, is_all_under_5g=%d, is_mcc_25g=%d!\n",
+		    coex_sta->wl_center_channel,
+		    wifi_link_info_ext->is_all_under_5g,
+		    wifi_link_info_ext->is_mcc_25g);
+	BTC_TRACE(trace_buf);
+
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+		    "[BTCoex], wifi_link_info: port_connect_status=0x%x, active_port_cnt=%d, P2P_Connect=%d!\n",
+		    wifi_link_info_ext->port_connect_status,
+		    wifi_link_info_ext->num_of_active_port,
+		    wifi_link_info_ext->is_p2p_connected);
+	BTC_TRACE(trace_buf);
+
+	switch (reason) {
+	case BT_8821C_2ANT_RSN_2GSCANSTART:
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], Update reason = %s\n", "2GSCANSTART");
+		break;
+	case BT_8821C_2ANT_RSN_5GSCANSTART:
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], Update reason = %s\n", "5GSCANSTART");
+		break;
+	case BT_8821C_2ANT_RSN_SCANFINISH:
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], Update reason = %s\n", "SCANFINISH");
+		break;
+	case BT_8821C_2ANT_RSN_2GSWITCHBAND:
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], Update reason = %s\n", "2GSWITCHBAND");
+		break;
+	case BT_8821C_2ANT_RSN_5GSWITCHBAND:
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], Update reason = %s\n", "5GSWITCHBAND");
+		break;
+	case BT_8821C_2ANT_RSN_2GCONSTART:
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], Update reason = %s\n", "2GCONNECTSTART");
+		break;
+	case BT_8821C_2ANT_RSN_5GCONSTART:
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], Update reason = %s\n", "5GCONNECTSTART");
+		break;
+	case BT_8821C_2ANT_RSN_2GCONFINISH:
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], Update reason = %s\n",
+			    "2GCONNECTFINISH");
+		break;
+	case BT_8821C_2ANT_RSN_5GCONFINISH:
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], Update reason = %s\n",
+			    "5GCONNECTFINISH");
+		break;
+	case BT_8821C_2ANT_RSN_2GMEDIA:
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], Update reason = %s\n", "2GMEDIASTATUS");
+		break;
+	case BT_8821C_2ANT_RSN_5GMEDIA:
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], Update reason = %s\n", "5GMEDIASTATUS");
+		break;
+	case BT_8821C_2ANT_RSN_MEDIADISCON:
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], Update reason = %s\n",
+			    "MEDIADISCONNECT");
+		break;
+	case BT_8821C_2ANT_RSN_2GSPECIALPKT:
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], Update reason = %s\n", "2GSPECIALPKT");
+		break;
+	case BT_8821C_2ANT_RSN_5GSPECIALPKT:
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], Update reason = %s\n", "5GSPECIALPKT");
+		break;
+	case BT_8821C_2ANT_RSN_BTINFO:
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], Update reason = %s\n", "BTINFO");
+		break;
+	case BT_8821C_2ANT_RSN_PERIODICAL:
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], Update reason = %s\n", "PERIODICAL");
+		break;
+	case BT_8821C_2ANT_RSN_PNP:
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], Update reason = %s\n", "PNPNotify");
+		break;
+	default:
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], Update reason = %s\n", "UNKNOWN");
+		break;
+	}
+
+	BTC_TRACE(trace_buf);
+
+	if (wifi_link_info_ext->is_all_under_5g ||
+	    coex_sta->num_of_profile == 0)
+		halbtc8821c2ant_low_penalty_ra(btc, NM_EXCU, FALSE, 0);
+	else if (wifi_link_info_ext->is_p2p_connected)
+		halbtc8821c2ant_low_penalty_ra(btc, NM_EXCU, TRUE, 30);
+	else
+		halbtc8821c2ant_low_penalty_ra(btc, NM_EXCU, TRUE, 15);
+}
+
+static
+void halbtc8821c2ant_update_bt_link_info(struct btc_coexist *btc)
+{
+	struct coex_sta_8821c_2ant *coex_sta = &btc->coex_sta_8821c_2ant;
+	struct coex_dm_8821c_2ant *coex_dm = &btc->coex_dm_8821c_2ant;
+	struct	btc_bt_link_info *bt_link_info = &btc->bt_link_info;
+	boolean	bt_busy = FALSE, increase_scan_dev_num = FALSE;
+	u32 val = 0;
+	static u8 pre_num_of_profile, cur_num_of_profile, cnt, ble_cnt;
+
+	if (++ble_cnt >= 3)
+		ble_cnt = 0;
+
+	if (coex_sta->is_ble_scan_en && ble_cnt == 0) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], BT ext info bit4 check, query BLE Scan type!!\n");
+		BTC_TRACE(trace_buf);
+		coex_sta->bt_ble_scan_type =
+			btc->btc_get_ble_scan_type_from_bt(btc);
+
+		if ((coex_sta->bt_ble_scan_type & 0x1) == 0x1)
+			coex_sta->bt_ble_scan_para[0]  =
+				btc->btc_get_ble_scan_para_from_bt(btc, 0x1);
+		if ((coex_sta->bt_ble_scan_type & 0x2) == 0x2)
+			coex_sta->bt_ble_scan_para[1]  =
+				btc->btc_get_ble_scan_para_from_bt(btc, 0x2);
+		if ((coex_sta->bt_ble_scan_type & 0x4) == 0x4)
+			coex_sta->bt_ble_scan_para[2]  =
+				btc->btc_get_ble_scan_para_from_bt(btc, 0x4);
+	}
+
+	coex_sta->num_of_profile = 0;
+
+	/* set link exist status */
+	if (!(coex_sta->bt_info & BT_INFO_8821C_2ANT_B_CONNECTION)) {
+		coex_sta->bt_link_exist = FALSE;
+		coex_sta->pan_exist = FALSE;
+		coex_sta->a2dp_exist = FALSE;
+		coex_sta->hid_exist = FALSE;
+		coex_sta->sco_exist = FALSE;
+		coex_sta->msft_mr_exist = FALSE;
+	} else {	/* connection exists */
+		coex_sta->bt_link_exist = TRUE;
+		if (coex_sta->bt_info & BT_INFO_8821C_2ANT_B_FTP) {
+			coex_sta->pan_exist = TRUE;
+			coex_sta->num_of_profile++;
+		} else {
+			coex_sta->pan_exist = FALSE;
+		}
+
+		if (coex_sta->bt_info & BT_INFO_8821C_2ANT_B_A2DP) {
+			coex_sta->a2dp_exist = TRUE;
+			coex_sta->num_of_profile++;
+		} else {
+			coex_sta->a2dp_exist = FALSE;
+		}
+
+		if (coex_sta->bt_info & BT_INFO_8821C_2ANT_B_HID) {
+			coex_sta->hid_exist = TRUE;
+			coex_sta->num_of_profile++;
+		} else {
+			coex_sta->hid_exist = FALSE;
+		}
+
+		if (coex_sta->bt_info & BT_INFO_8821C_2ANT_B_SCO_ESCO) {
+			coex_sta->sco_exist = TRUE;
+			coex_sta->num_of_profile++;
+		} else {
+			coex_sta->sco_exist = FALSE;
+		}
+
+		if (coex_sta->hid_busy_num == 0 &&
+		    coex_sta->hid_pair_cnt > 0 &&
+		    coex_sta->low_priority_tx > 1000 &&
+		    coex_sta->low_priority_rx > 1000 &&
+		    !coex_sta->c2h_bt_inquiry_page)
+			coex_sta->msft_mr_exist = true;
+		else
+			coex_sta->msft_mr_exist = false;
+	}
+
+	bt_link_info->bt_link_exist = coex_sta->bt_link_exist;
+	bt_link_info->sco_exist = coex_sta->sco_exist;
+	bt_link_info->a2dp_exist = coex_sta->a2dp_exist;
+	bt_link_info->pan_exist = coex_sta->pan_exist;
+	bt_link_info->hid_exist = coex_sta->hid_exist;
+	bt_link_info->acl_busy = coex_sta->acl_busy;
+
+	/* check if Sco only */
+	if (bt_link_info->sco_exist &&
+	    !bt_link_info->a2dp_exist &&
+	    !bt_link_info->pan_exist &&
+	    !bt_link_info->hid_exist)
+		bt_link_info->sco_only = TRUE;
+	else
+		bt_link_info->sco_only = FALSE;
+
+	/* check if A2dp only */
+	if (!bt_link_info->sco_exist &&
+	    bt_link_info->a2dp_exist &&
+	    !bt_link_info->pan_exist &&
+	    !bt_link_info->hid_exist)
+		bt_link_info->a2dp_only = TRUE;
+	else
+		bt_link_info->a2dp_only = FALSE;
+
+	/* check if Pan only */
+	if (!bt_link_info->sco_exist &&
+	    !bt_link_info->a2dp_exist &&
+	    bt_link_info->pan_exist &&
+	    !bt_link_info->hid_exist)
+		bt_link_info->pan_only = TRUE;
+	else
+		bt_link_info->pan_only = FALSE;
+
+	/* check if Hid only */
+	if (!bt_link_info->sco_exist &&
+	    !bt_link_info->a2dp_exist &&
+	    !bt_link_info->pan_exist &&
+	    bt_link_info->hid_exist)
+		bt_link_info->hid_only = TRUE;
+	else
+		bt_link_info->hid_only = FALSE;
+
+	if (coex_sta->bt_info & BT_INFO_8821C_2ANT_B_INQ_PAGE) {
+		coex_dm->bt_status = BT_8821C_2ANT_BSTATUS_INQ_PAGE;
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], BtInfoNotify(), BT Inq/page!!!\n");
+	} else if (!(coex_sta->bt_info & BT_INFO_8821C_2ANT_B_CONNECTION)) {
+		coex_dm->bt_status = BT_8821C_2ANT_BSTATUS_NCON_IDLE;
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], BtInfoNotify(), BT Non-Connected idle!!!\n");
+	} else if (coex_sta->bt_info == BT_INFO_8821C_2ANT_B_CONNECTION) {
+		/* connection exists but no busy */
+		if (coex_sta->msft_mr_exist) {
+			coex_dm->bt_status = BT_8821C_2ANT_BSTATUS_ACL_BUSY;
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				    "[BTCoex], BtInfoNotify(),  BT ACL busy!!\n");
+		} else {
+			coex_dm->bt_status = BT_8821C_2ANT_BSTATUS_CON_IDLE;
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				    "[BTCoex], BtInfoNotify(), BT Connected-idle!!!\n");
+		}
+	} else if (((coex_sta->bt_info & BT_INFO_8821C_2ANT_B_SCO_ESCO) ||
+		    (coex_sta->bt_info & BT_INFO_8821C_2ANT_B_SCO_BUSY)) &&
+		   (coex_sta->bt_info & BT_INFO_8821C_2ANT_B_ACL_BUSY)) {
+		coex_dm->bt_status = BT_8821C_2ANT_BSTATUS_ACL_SCO_BUSY;
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], BtInfoNotify(), BT ACL SCO busy!!!\n");
+	} else if ((coex_sta->bt_info & BT_INFO_8821C_2ANT_B_SCO_ESCO) ||
+		   (coex_sta->bt_info & BT_INFO_8821C_2ANT_B_SCO_BUSY)) {
+		coex_dm->bt_status = BT_8821C_2ANT_BSTATUS_SCO_BUSY;
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], BtInfoNotify(), BT SCO busy!!!\n");
+	} else if (coex_sta->bt_info & BT_INFO_8821C_2ANT_B_ACL_BUSY) {
+		coex_dm->bt_status = BT_8821C_2ANT_BSTATUS_ACL_BUSY;
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], BtInfoNotify(), BT ACL busy!!!\n");
+	} else {
+		coex_dm->bt_status = BT_8821C_2ANT_BSTATUS_MAX;
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], BtInfoNotify(), BT Non-Defined state!!!\n");
+	}
+
+	BTC_TRACE(trace_buf);
+
+	if (coex_dm->bt_status == BT_8821C_2ANT_BSTATUS_ACL_BUSY ||
+	    coex_dm->bt_status == BT_8821C_2ANT_BSTATUS_SCO_BUSY ||
+	    coex_dm->bt_status == BT_8821C_2ANT_BSTATUS_ACL_SCO_BUSY) {
+		bt_busy = TRUE;
+		increase_scan_dev_num = TRUE;
+	} else {
+		bt_busy = FALSE;
+		increase_scan_dev_num = FALSE;
+	}
+
+	btc->btc_set(btc, BTC_SET_BL_BT_TRAFFIC_BUSY, &bt_busy);
+	btc->btc_set(btc, BTC_SET_BL_INC_SCAN_DEV_NUM, &increase_scan_dev_num);
+
+	cur_num_of_profile = coex_sta->num_of_profile;
+
+	if (cur_num_of_profile != pre_num_of_profile)
+		cnt = 2;
+
+	if (btc->board_info.customer_id == RT_CID_LENOVO_CHINA) {
+		if (cur_num_of_profile > 0)
+			halbtc8821c2ant_set_antdiv_hwsw(btc, NM_EXCU, TRUE);
+		else
+			halbtc8821c2ant_set_antdiv_hwsw(btc, NM_EXCU, FALSE);
+	}
+
+	if (bt_link_info->a2dp_exist && (cnt > 0)) {
+		cnt--;
+		if (coex_sta->bt_a2dp_vendor_id == 0 &&
+		    coex_sta->bt_a2dp_device_name == 0) {
+			btc->btc_get(btc, BTC_GET_U4_BT_DEVICE_INFO, &val);
+
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				    "[BTCoex], BtInfoNotify(), get BT DEVICE_INFO = %x\n",
+				    val);
+			BTC_TRACE(trace_buf);
+
+			coex_sta->bt_a2dp_vendor_id = (u8)(val & 0xff);
+			coex_sta->bt_a2dp_device_name = (val & 0xffffff00) >> 8;
+		}
+
+		if (coex_sta->legacy_forbidden_slot == 0 &&
+		    coex_sta->le_forbidden_slot == 0) {
+			btc->btc_get(btc, BTC_GET_U4_BT_FORBIDDEN_SLOT_VAL,
+				     &val);
+
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				    "[BTCoex], BtInfoNotify(), get BT FORBIDDEN_SLOT_VAL = %x\n",
+				    val);
+			BTC_TRACE(trace_buf);
+
+			coex_sta->legacy_forbidden_slot = (u16)(val & 0xffff);
+			coex_sta->le_forbidden_slot =
+						(u16)((val & 0xffff0000) >> 16);
+		}
+	}
+
+	pre_num_of_profile = coex_sta->num_of_profile;
+}
+
+static
+void halbtc8821c2ant_update_wifi_ch_info(struct btc_coexist *btc, u8 type)
+{
+	struct coex_sta_8821c_2ant *coex_sta = &btc->coex_sta_8821c_2ant;
+	struct coex_dm_8821c_2ant *coex_dm = &btc->coex_dm_8821c_2ant;
+	struct wifi_link_info_8821c_2ant *wifi_link_info_ext =
+					 &btc->wifi_link_info_8821c_2ant;
+	u8 h2c_parameter[3] = {0}, i;
+	u32 wifi_bw;
+	u8 wifi_central_chnl = 0;
+	u8 wifi_5g_chnl[19] = {120, 124, 128, 132, 136, 140, 144, 149, 153, 157,
+			       118, 126, 134, 142, 151, 159, 122, 138, 155};
+	u8 bt_skip_cneter_chanl[19] = {2, 8, 17, 26, 34, 42, 51, 62, 71, 77, 2,
+				       12, 29, 46, 66, 76, 10, 37, 68};
+	u8 bt_skip_span[19] = {4, 8, 8, 10, 8, 10, 8, 8, 10, 4, 4, 16, 16, 16,
+			       16, 4, 20, 34, 20};
+	boolean is_any_connected = FALSE;
+
+	if (btc->manual_control)
+		return;
+
+	btc->btc_get(btc, BTC_GET_U4_WIFI_BW, &wifi_bw);
+
+	if (btc->stop_coex_dm || coex_sta->is_rf_state_off) {
+		is_any_connected = FALSE;
+		wifi_central_chnl = 0;
+	} else if (type != BTC_MEDIA_DISCONNECT ||
+		  (type == BTC_MEDIA_DISCONNECT &&
+		   wifi_link_info_ext->num_of_active_port > 0)) {
+		if (wifi_link_info_ext->num_of_active_port == 1) {
+			if (wifi_link_info_ext->is_p2p_connected)
+				wifi_central_chnl =
+					btc->wifi_link_info
+						.p2p_center_channel;
+			else
+				wifi_central_chnl =
+					btc->wifi_link_info
+						.sta_center_channel;
+		} else { /* port > 2 */
+			if ((btc->wifi_link_info
+				     .p2p_center_channel > 14) &&
+			    (btc->wifi_link_info
+				     .sta_center_channel > 14))
+				wifi_central_chnl =
+					btc->wifi_link_info
+						.p2p_center_channel;
+			else if (btc->wifi_link_info
+					 .p2p_center_channel <= 14)
+				wifi_central_chnl =
+					btc->wifi_link_info
+						.p2p_center_channel;
+			else if (btc->wifi_link_info
+					 .sta_center_channel <= 14)
+				wifi_central_chnl =
+					btc->wifi_link_info
+						.sta_center_channel;
+		}
+	}
+
+	if (wifi_central_chnl > 0)
+		is_any_connected = TRUE;
+
+	if (is_any_connected) {
+		if (wifi_central_chnl <= 14) {
+			h2c_parameter[0] = 0x1;
+			h2c_parameter[1] = wifi_central_chnl;
+
+			if (wifi_bw == BTC_WIFI_BW_HT40)
+				h2c_parameter[2] = 0x36;
+			else
+				h2c_parameter[2] = 0x24;
+		} else {  /* for 5G  */
+			for (i = 0; i <= 18; i++) {
+				if (wifi_central_chnl == wifi_5g_chnl[i])
+					break;
+			}
+
+			if (i <= 18) {
+				h2c_parameter[0] = 0x3;
+				h2c_parameter[1] = bt_skip_cneter_chanl[i];
+				h2c_parameter[2] = bt_skip_span[i];
+			}
+		}
+	}
+
+	coex_dm->wifi_chnl_info[0] = h2c_parameter[0];
+	coex_dm->wifi_chnl_info[1] = h2c_parameter[1];
+	coex_dm->wifi_chnl_info[2] = h2c_parameter[2];
+
+	btc->btc_fill_h2c(btc, 0x66, 3, h2c_parameter);
+
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+		    "[BTCoex], para[0:2] = 0x%x 0x%x 0x%x\n",
+		    h2c_parameter[0], h2c_parameter[1], h2c_parameter[2]);
+	BTC_TRACE(trace_buf);
+}
+
+static
+void halbtc8821c2ant_set_wl_tx_power(struct btc_coexist *btc,
+				     boolean force_exec,  u8 wl_pwr_lvl)
+{
+	struct coex_dm_8821c_2ant *coex_dm = &btc->coex_dm_8821c_2ant;
+
+	if (!force_exec) {
+		if (wl_pwr_lvl == coex_dm->cur_wl_pwr_lvl)
+			return;
+	}
+
+	/* btc->btc_write_1byte_bitmask(btc, 0xc5b, 0xff, wl_pwr_lvl); */
+	coex_dm->cur_wl_pwr_lvl = wl_pwr_lvl;
+}
+
+static
+void halbtc8821c2ant_set_bt_tx_power(struct btc_coexist *btc,
+				     boolean force_exec,  u8 bt_pwr_lvl)
+{
+	struct coex_dm_8821c_2ant *coex_dm = &btc->coex_dm_8821c_2ant;
+	u8 h2c_parameter[1] = {0};
+
+	if (!force_exec) {
+		if (bt_pwr_lvl == coex_dm->cur_bt_pwr_lvl)
+			return;
+	}
+
+	h2c_parameter[0] = 0 - bt_pwr_lvl;
+	btc->btc_fill_h2c(btc, 0x62, 1, h2c_parameter);
+
+	coex_dm->cur_bt_pwr_lvl = bt_pwr_lvl;
+}
+
+#if 0
+static
+void halbtc8821c2ant_set_wl_rx_gain(struct btc_coexist *btc,
+				    boolean force_exec,  boolean agc_table_en)
+{
+	struct coex_dm_8821c_2ant *coex_dm = &btc->coex_dm_8821c_2ant;
+
+	u32 rx_gain_value_enable[] = {0xff000003,
+	0xbd120003, 0xbe100003, 0xbf080003, 0xbf060003, 0xbf050003,
+	0xbc140003, 0xbb160003, 0xba180003, 0xb91a0003, 0xb81c0003,
+	0xb71e0003, 0xb4200003, 0xb5220003, 0xb4240003, 0xb3260003,
+	0xb2280003, 0xb12a0003, 0xb02c0003, 0xaf2e0003, 0xae300003,
+	0xad320003, 0xac340003, 0xab360003, 0x8d380003, 0x8c3a0003,
+	0x8b3c0003, 0x8a3e0003, 0x6e400003, 0x6d420003, 0x6c440003,
+	0x6b460003, 0x6a480003, 0x694a0003, 0x684c0003, 0x674e0003,
+	0x66500003, 0x65520003, 0x64540003, 0x64560003, 0x007e0403};
+
+	u32 rx_gain_value_disable[] = {0xff000003,
+	0xf4120003, 0xf5100003, 0xf60e0003, 0xf70c0003, 0xf80a0003,
+	0xf3140003, 0xf2160003, 0xf1180003, 0xf01a0003, 0xef1c0003,
+	0xee1e0003, 0xed200003, 0xec220003, 0xeb240003, 0xea260003,
+	0xe9280003, 0xe82a0003, 0xe72c0003, 0xe62e0003, 0xe5300003,
+	0xc8320003, 0xc7340003, 0xc6360003, 0xc5380003, 0xc43a0003,
+	0xc33c0003, 0xc23e0003, 0xc1400003, 0xc0420003, 0xa5440003,
+	0xa4460003, 0xa3480003, 0xa24a0003, 0xa14c0003, 0x834e0003,
+	0x82500003, 0x81520003, 0x80540003, 0x65560003, 0x007e0403};
+
+	u8 i;
+
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+		    "[BTCoex], *************wl rx gain*************\n");
+	BTC_TRACE(trace_buf);
+
+	if (!force_exec) {
+		if (agc_table_en == coex_dm->cur_agc_table_en)
+			return;
+	}
+
+		if (agc_table_en) {
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				    "[BTCoex], BB Agc Table On!\n");
+			BTC_TRACE(trace_buf);
+
+			for (i = 0; i <= 100; i++) {
+				btc->btc_write_4byte(btc,
+					0x81c, rx_gain_value_enable[i]);
+
+				if (rx_gain_value_enable[i] == 0x007e0403)
+					break;
+			}
+
+			/* set Rx filter corner RCK offset */
+			btc->btc_set_rf_reg(btc, BTC_RF_A, 0xde, 0x2, 0x1);
+			btc->btc_set_rf_reg(btc, BTC_RF_A, 0x1d, 0x3f, 0x3f);
+
+			/* ADC clock 80M
+			 * btc->btc_write_1byte_bitmask(btc, 0x8ad, 0x3, 0x3);
+			 */
+
+		} else {
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				    "[BTCoex], BB Agc Table Off!\n");
+			BTC_TRACE(trace_buf);
+
+			for (i = 0; i <= 100; i++) {
+				btc->btc_write_4byte(btc,
+					0x81c, rx_gain_value_disable[i]);
+
+				if (rx_gain_value_disable[i] == 0x007e0403)
+					break;
+			}
+
+			/* set Rx filter corner RCK offset */
+			btc->btc_set_rf_reg(btc, BTC_RF_A, 0x1d, 0x3f, 0x4);
+			btc->btc_set_rf_reg(btc, BTC_RF_A, 0xde, 0x2, 0x0);
+
+			/* ADC clock 160M
+			 * btc->btc_write_1byte_bitmask(btc, 0x8ad, 0x3, 0x0);
+			 */
+		}
+
+	coex_dm->cur_agc_table_en = agc_table_en;
+}
+
+static
+void halbtc8821c2ant_set_bt_rx_gain(struct btc_coexist *btc,
+				    boolean force_exec,  boolean rx_gain_en)
+{
+	u8 lna_constrain_level = 0;
+
+	/* use scoreboard[4] to notify BT Rx gain table change   */
+	halbtc8821c2ant_write_scbd(btc, BT_8821C_2ANT_SCBD_RXGAIN,
+				   rx_gain_en);
+
+	if (rx_gain_en)
+		lna_constrain_level = 1;
+	else
+		lna_constrain_level = 7;
+
+	btc->btc_set(btc, BTC_SET_BL_BT_LNA_CONSTRAIN_LEVEL,
+		     &lna_constrain_level);
+}
+#endif
+
+static
+void halbtc8821c2ant_bt_auto_report(struct btc_coexist *btc,
+				    boolean force_exec,
+				    boolean enable_auto_report)
+{
+	struct coex_dm_8821c_2ant *coex_dm = &btc->coex_dm_8821c_2ant;
+	u8			h2c_parameter[1] = {0};
+
+	if (!force_exec) {
+		if (enable_auto_report == coex_dm->cur_bt_auto_report)
+			return;
+	}
+
+	if (enable_auto_report)
+		h2c_parameter[0] |= BIT(0);
+
+	btc->btc_fill_h2c(btc, 0x68, 1, h2c_parameter);
+
+	coex_dm->cur_bt_auto_report = enable_auto_report;
+}
+
+static
+u32 halbtc8821c2ant_read_indirect_reg(struct btc_coexist *btc, u16 reg_addr)
+{
+	u32 j = 0, delay_count = 0;
+
+	while (1) {
+		if ((btc->btc_read_1byte(btc, 0x1703) & BIT(5)) == 0) {
+			delay_ms(10);
+			delay_count++;
+			if (delay_count >= 10) {
+				delay_count = 0;
+				break;
+			}
+		} else
+			break;
+	}
+
+	/* wait for ready bit before access 0x1700 */
+	btc->btc_write_4byte(btc, 0x1700, 0x800F0000 | reg_addr);
+
+	return btc->btc_read_4byte(btc, 0x1708);  /* get read data */
+}
+
+static
+void halbtc8821c2ant_write_indirect_reg(struct btc_coexist *btc, u16 reg_addr,
+					u32 bit_mask, u32 reg_value)
+{
+	u32 val, i = 0, j = 0, bitpos = 0, delay_count = 0;
+
+	if (bit_mask == 0x0)
+		return;
+	if (bit_mask == 0xffffffff) {
+		/* wait for ready bit before access 0x1700/0x1704 */
+		while (1) {
+			if ((btc->btc_read_1byte(btc, 0x1703) & BIT(5)) == 0) {
+				delay_ms(10);
+				delay_count++;
+				if (delay_count >= 10) {
+					delay_count = 0;
+					break;
+				}
+			} else
+				break;
+		}
+
+		/* put write data */
+		btc->btc_write_4byte(btc, 0x1704, reg_value);
+		btc->btc_write_4byte(btc, 0x1700, 0xc00F0000 | reg_addr);
+	} else {
+		for (i = 0; i <= 31; i++) {
+			if (((bit_mask >> i) & 0x1) == 0x1) {
+				bitpos = i;
+				break;
+			}
+		}
+
+		/* read back register value before write */
+		val = halbtc8821c2ant_read_indirect_reg(btc, reg_addr);
+		val = (val & (~bit_mask)) | (reg_value << bitpos);
+
+		/* wait for ready bit before access 0x1700/0x1704 */
+		while (1) {
+			if ((btc->btc_read_1byte(btc, 0x1703) & BIT(5)) == 0) {
+				delay_ms(10);
+				delay_count++;
+				if (delay_count >= 10) {
+					delay_count = 0;
+					break;
+				}
+			} else
+				break;
+		}
+
+		/* put write data */
+		btc->btc_write_4byte(btc, 0x1704, val);
+		btc->btc_write_4byte(btc, 0x1700, 0xc00F0000 | reg_addr);
+	}
+}
+
+static
+void halbtc8821c2ant_ltecoex_enable(struct btc_coexist *btc, boolean enable)
+{
+	u8 val;
+
+	/* 0x38[7] */
+	val = (enable) ? 1 : 0;
+	halbtc8821c2ant_write_indirect_reg(btc, 0x38, 0x80, val);
+}
+
+static
+void halbtc8821c2ant_ltecoex_table(struct btc_coexist *btc, u8 table_type,
+				   u16 table_content)
+{
+	u16 reg_addr = 0x0000;
+
+	switch (table_type) {
+	case BT_8821C_2ANT_CTT_WL_VS_LTE:
+		reg_addr = 0xa0;
+		break;
+	case BT_8821C_2ANT_CTT_BT_VS_LTE:
+		reg_addr = 0xa4;
+		break;
+	}
+
+	 /* 0xa0[15:0] or 0xa4[15:0] */
+	if (reg_addr != 0x0000)
+		halbtc8821c2ant_write_indirect_reg(btc, reg_addr, 0xffff,
+						   table_content);
+}
+
+static
+void halbtc8821c2ant_coex_ctrl_owner(struct btc_coexist *btc,
+				     boolean wifi_control)
+{
+	u8 val;
+
+	/* 0x70[26] */
+	val = (wifi_control) ? 1 : 0;
+	btc->btc_write_1byte_bitmask(btc, 0x73, 0x4, val);
+}
+
+static
+void halbtc8821c2ant_set_gnt_bt(struct btc_coexist *btc, u8 control_block,
+				boolean sw_control, u8 state)
+{
+	u32 val = 0, val_orig = 0;
+
+	if (!sw_control)
+		val = 0x0;
+	else if (state & 0x1)
+		val = 0x3;
+	else
+		val = 0x1;
+
+	val_orig = halbtc8821c2ant_read_indirect_reg(btc, 0x38);
+
+	switch (control_block) {
+	case BT_8821C_2ANT_GNT_BLOCK_RFC_BB:
+	default:
+		val = ((val << 14) | (val << 10)) | (val_orig & 0xffff33ff);
+		break;
+	case BT_8821C_2ANT_GNT_BLOCK_RFC:
+		val = (val << 14) | (val_orig & 0xffff3fff);
+		break;
+	case BT_8821C_2ANT_GNT_BLOCK_BB:
+		val = (val << 10) | (val_orig & 0xfffff3ff);
+		break;
+	}
+
+	halbtc8821c2ant_write_indirect_reg(btc, 0x38, 0xffffffff, val);
+}
+
+static
+void halbtc8821c2ant_set_gnt_wl(struct btc_coexist *btc, u8 control_block,
+				boolean sw_control, u8 state)
+{
+	u32 val = 0, val_orig = 0;
+
+	if (!sw_control)
+		val = 0x0;
+	else if (state & 0x1)
+		val = 0x3;
+	else
+		val = 0x1;
+
+	val_orig = halbtc8821c2ant_read_indirect_reg(btc, 0x38);
+
+	switch (control_block) {
+	case BT_8821C_2ANT_GNT_BLOCK_RFC_BB:
+	default:
+		val = ((val << 12) | (val << 8)) | (val_orig & 0xffffccff);
+		break;
+	case BT_8821C_2ANT_GNT_BLOCK_RFC:
+		val = (val << 12) | (val_orig & 0xffffcfff);
+		break;
+	case BT_8821C_2ANT_GNT_BLOCK_BB:
+		val = (val << 8) | (val_orig & 0xfffffcff);
+		break;
+	}
+
+	halbtc8821c2ant_write_indirect_reg(btc, 0x38, 0xffffffff, val);
+}
+
+#if 0
+static
+void halbtc8821c2ant_ltecoex_set_break_table(struct btc_coexist *btc,
+					     u8 table_type, u8 table_content)
+{
+	u16 reg_addr = 0x0000;
+
+	switch (table_type) {
+	case BT_8821C_2ANT_LBTT_WL_BREAK_LTE:
+		reg_addr = 0xa8;
+		break;
+	case BT_8821C_2ANT_LBTT_BT_BREAK_LTE:
+		reg_addr = 0xac;
+		break;
+	case BT_8821C_2ANT_LBTT_LTE_BREAK_WL:
+		reg_addr = 0xb0;
+		break;
+	case BT_8821C_2ANT_LBTT_LTE_BREAK_BT:
+		reg_addr = 0xb4;
+		break;
+	}
+
+	/* 0xa8[15:0] or 0xb4[15:0] */
+	if (reg_addr != 0x0000)
+		halbtc8821c2ant_write_indirect_reg(btc, reg_addr, 0xff,
+						   table_content);
+}
+#endif
+
+#if 0
+static
+void halbtc8821c2ant_set_wltoggle_coex_table(struct btc_coexist *btc,
+					     boolean force_exec, u8 interval,
+					     u8 val0x6c4_b0, u8 val0x6c4_b1,
+					     u8 val0x6c4_b2, u8 val0x6c4_b3)
+{
+	static u8 pre_h2c_parameter[6] = {0};
+	u8	cur_h2c_parameter[6] = {0};
+	u8 i, match_cnt = 0;
+
+	cur_h2c_parameter[0] = 0x7;	/* op_code, 0x7= wlan toggle slot*/
+
+	cur_h2c_parameter[1] = interval;
+	cur_h2c_parameter[2] = val0x6c4_b0;
+	cur_h2c_parameter[3] = val0x6c4_b1;
+	cur_h2c_parameter[4] = val0x6c4_b2;
+	cur_h2c_parameter[5] = val0x6c4_b3;
+
+	if (!force_exec) {
+		for (i = 1; i <= 5; i++) {
+			if (cur_h2c_parameter[i] != pre_h2c_parameter[i])
+				break;
+
+			match_cnt++;
+		}
+
+		if (match_cnt == 5)
+			return;
+	}
+
+	for (i = 1; i <= 5; i++)
+		pre_h2c_parameter[i] = cur_h2c_parameter[i];
+
+	btc->btc_fill_h2c(btc, 0x69, 6, cur_h2c_parameter);
+}
+#endif
+
+static
+void halbtc8821c2ant_coex_table(struct btc_coexist *btc,
+				boolean force_exec, u32 val0x6c0,
+				u32 val0x6c4, u32 val0x6c8,
+				u8 val0x6cc)
+{
+	struct coex_dm_8821c_2ant *coex_dm = &btc->coex_dm_8821c_2ant;
+
+	if (!force_exec) {
+		if (val0x6c0 == coex_dm->cur_val0x6c0 &&
+		    val0x6c4 == coex_dm->cur_val0x6c4 &&
+		    val0x6c8 == coex_dm->cur_val0x6c8 &&
+		    val0x6cc == coex_dm->cur_val0x6cc)
+			return;
+	}
+
+	btc->btc_write_4byte(btc, 0x6c0, val0x6c0);
+	btc->btc_write_4byte(btc, 0x6c4, val0x6c4);
+	btc->btc_write_4byte(btc, 0x6c8, val0x6c8);
+	btc->btc_write_1byte(btc, 0x6cc, val0x6cc);
+
+	coex_dm->cur_val0x6c0 = val0x6c0;
+	coex_dm->cur_val0x6c4 = val0x6c4;
+	coex_dm->cur_val0x6c8 = val0x6c8;
+	coex_dm->cur_val0x6cc = val0x6cc;
+}
+
+void halbtc8821c2ant_table(struct btc_coexist *btc, boolean force_exec, u8 type)
+{
+	struct coex_sta_8821c_2ant *coex_sta = &btc->coex_sta_8821c_2ant;
+	u32	break_table;
+	u8	select_table;
+
+	coex_sta->coex_table_type = type;
+
+	if (coex_sta->concurrent_rx_mode_on == TRUE) {
+		/* set WL hi-pri can break BT */
+		break_table = 0xf0ffffff;
+		/* set Tx response = Hi-Pri (ex: Transmitting ACK,BA,CTS) */
+		select_table = 0x1b;
+	} else {
+		break_table = 0xffffff;
+		select_table = 0x13;
+	}
+
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+		    "[BTCoex], ********** Table-%d **********\n",
+		    coex_sta->coex_table_type);
+	BTC_TRACE(trace_buf);
+
+	switch (type) {
+	case 0:
+		halbtc8821c2ant_coex_table(btc, force_exec, 0xffffffff,
+					   0xffffffff, break_table,
+					   select_table);
+		break;
+	case 1:
+		halbtc8821c2ant_coex_table(btc, force_exec, 0x55555555,
+					   0xfafafafa, break_table,
+					   select_table);
+		break;
+	case 2:
+		halbtc8821c2ant_coex_table(btc, force_exec, 0x5a5a5a5a,
+					   0x5a5a5a5a, break_table,
+					   select_table);
+		break;
+	case 3:
+		halbtc8821c2ant_coex_table(btc, force_exec, 0x55555555,
+					   0x5a5a5a5a, break_table,
+					   select_table);
+		break;
+	case 4:
+		halbtc8821c2ant_coex_table(btc, force_exec, 0xffff55ff,
+					   0xfafafafa, break_table,
+					   select_table);
+		break;
+	case 5:
+		halbtc8821c2ant_coex_table(btc, force_exec, 0x55555555,
+					   0x55555555, break_table,
+					   select_table);
+		break;
+	case 6:
+		halbtc8821c2ant_coex_table(btc, force_exec, 0xaaffffaa,
+					   0x5afa5afa, break_table,
+					   select_table);
+		break;
+	case 7:
+		halbtc8821c2ant_coex_table(btc, force_exec, 0xaaffffaa,
+					   0xfafafafa, break_table,
+					   select_table);
+		break;
+	case 8:
+		halbtc8821c2ant_coex_table(btc, force_exec, 0xffff55ff,
+					   0xfafafafa, break_table,
+					   select_table);
+		break;
+	case 9:
+		halbtc8821c2ant_coex_table(btc, force_exec, 0x5a5a5a5a,
+					   0xaaaa5aaa, break_table,
+					   select_table);
+		break;
+	case 10:
+		halbtc8821c2ant_coex_table(btc, force_exec, 0xaaaaaaaa,
+					   0xaaaaaaaa, break_table,
+					   select_table);
+		break;
+	case 11:
+		halbtc8821c2ant_coex_table(btc, force_exec, 0xffffffff,
+					   0xfafafafa, break_table,
+					   select_table);
+		break;
+	case 12:
+		halbtc8821c2ant_coex_table(btc, force_exec, 0xffff55ff,
+					   0x5afa5afa, break_table,
+					   select_table);
+		break;
+	case 14:
+		halbtc8821c2ant_coex_table(btc, force_exec, 0xffff55ff,
+					   0xaaaaaaaa, break_table,
+					   select_table);
+		break;
+	case 15:
+		halbtc8821c2ant_coex_table(btc, force_exec, 0x65555555,
+					   0xaaaaaaaa, break_table,
+					   select_table);
+		break;
+	default:
+		break;
+	}
+}
+
+static
+void halbtc8821c2ant_ignore_wlan_act(struct btc_coexist *btc,
+				     boolean force_exec, boolean enable)
+{
+	struct coex_dm_8821c_2ant *coex_dm = &btc->coex_dm_8821c_2ant;
+	u8	h2c_parameter[1] = {0};
+
+	if (btc->manual_control || btc->stop_coex_dm)
+		return;
+
+	if (!force_exec) {
+		if (enable == coex_dm->cur_ignore_wlan_act)
+			return;
+	}
+
+	if (enable)
+		h2c_parameter[0] |= BIT(0); /* function enable */
+
+	btc->btc_fill_h2c(btc, 0x63, 1, h2c_parameter);
+
+	coex_dm->cur_ignore_wlan_act = enable;
+}
+
+static
+void halbtc8821c2ant_lps_rpwm(struct btc_coexist *btc, boolean force_exec,
+			      u8 lps_val, u8 rpwm_val)
+{
+	struct coex_dm_8821c_2ant *coex_dm = &btc->coex_dm_8821c_2ant;
+
+	if (!force_exec) {
+		if (lps_val == coex_dm->cur_lps &&
+		    rpwm_val == coex_dm->cur_rpwm)
+			return;
+	}
+
+	btc->btc_set(btc, BTC_SET_U1_LPS_VAL, &lps_val);
+	btc->btc_set(btc, BTC_SET_U1_RPWM_VAL, &rpwm_val);
+
+	coex_dm->cur_lps = lps_val;
+	coex_dm->cur_rpwm = rpwm_val;
+}
+
+static
+void halbtc8821c2ant_tdma_check(struct btc_coexist *btc, boolean new_ps_state)
+{
+	u8 lps_mode = 0x0;
+	u8 h2c_parameter[5] = {0, 0, 0, 0x40, 0};
+
+	btc->btc_get(btc, BTC_GET_U1_LPS_MODE, &lps_mode);
+
+	if (lps_mode) {	/* already under LPS state */
+		if (new_ps_state) {
+			/* keep state under LPS, do nothing. */
+		} else {
+			/* will leave LPS state, turn off psTdma first */
+			btc->btc_fill_h2c(btc, 0x60, 5, h2c_parameter);
+		}
+	} else {					/* NO PS state */
+		if (new_ps_state) {
+			/* will enter LPS state, turn off psTdma first */
+			btc->btc_fill_h2c(btc, 0x60, 5, h2c_parameter);
+		} else {
+			/* keep state under NO PS state, do nothing. */
+		}
+	}
+}
+
+static
+boolean halbtc8821c2ant_power_save_state(struct btc_coexist *btc, u8 ps_type,
+					 u8 lps_val, u8 rpwm_val)
+{
+	struct coex_sta_8821c_2ant *coex_sta = &btc->coex_sta_8821c_2ant;
+	boolean	low_pwr_disable = FALSE, result = TRUE;
+
+	switch (ps_type) {
+	case BTC_PS_WIFI_NATIVE:
+		coex_sta->force_lps_ctrl = FALSE;
+		/* recover to original 32k low power setting */
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], %s == BTC_PS_WIFI_NATIVE\n", __func__);
+		BTC_TRACE(trace_buf);
+
+		low_pwr_disable = FALSE;
+		/* btc->btc_set(btc, BTC_SET_ACT_DISABLE_LOW_POWER,
+		 * &low_pwr_disable);
+		 */
+		btc->btc_set(btc, BTC_SET_ACT_PRE_NORMAL_LPS, NULL);
+		break;
+	case BTC_PS_LPS_ON:
+		coex_sta->force_lps_ctrl = TRUE;
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], %s == BTC_PS_LPS_ON\n", __func__);
+		BTC_TRACE(trace_buf);
+
+		halbtc8821c2ant_tdma_check(btc, TRUE);
+		halbtc8821c2ant_lps_rpwm(btc, NM_EXCU, lps_val, rpwm_val);
+		/* when coex force to enter LPS, do not enter 32k low power. */
+		low_pwr_disable = TRUE;
+		btc->btc_set(btc, BTC_SET_ACT_DISABLE_LOW_POWER,
+			     &low_pwr_disable);
+		/* power save must executed before psTdma.*/
+		btc->btc_set(btc, BTC_SET_ACT_ENTER_LPS, NULL);
+		break;
+	case BTC_PS_LPS_OFF:
+		coex_sta->force_lps_ctrl = TRUE;
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], %s == BTC_PS_LPS_OFF\n", __func__);
+		BTC_TRACE(trace_buf);
+
+		halbtc8821c2ant_tdma_check(btc, FALSE);
+		result = btc->btc_set(btc, BTC_SET_ACT_LEAVE_LPS, NULL);
+		break;
+	default:
+		break;
+	}
+
+	return result;
+}
+
+static
+void halbtc8821c2ant_set_tdma(struct btc_coexist *btc, u8 byte1, u8 byte2,
+			      u8 byte3, u8 byte4, u8 byte5)
+{
+	struct coex_sta_8821c_2ant *coex_sta = &btc->coex_sta_8821c_2ant;
+	struct coex_dm_8821c_2ant *coex_dm = &btc->coex_dm_8821c_2ant;
+	u8 h2c_parameter[5] = {0};
+	u8 real_byte1 = byte1, real_byte5 = byte5;
+	boolean	ap_enable = FALSE, result = FALSE;
+	struct btc_bt_link_info *bt_link_info = &btc->bt_link_info;
+	u8 ps_type = BTC_PS_WIFI_NATIVE;
+
+	if (byte5 & BIT(2))
+		coex_sta->is_tdma_btautoslot = TRUE;
+	else
+		coex_sta->is_tdma_btautoslot = FALSE;
+
+	/* release bt-auto slot for auto-slot hang is detected!! */
+	if (coex_sta->is_tdma_btautoslot)
+		if (coex_sta->is_tdma_btautoslot_hang ||
+		    bt_link_info->slave_role)
+			byte5 = byte5 & 0xfb;
+
+#if 1
+	btc->btc_get(btc, BTC_GET_BL_WIFI_AP_MODE_ENABLE, &ap_enable);
+#else
+	if (btc->wifi_link_info.link_mode == BTC_LINK_ONLY_GO &&
+	    btc->wifi_link_info.bhotspot &&
+	    btc->wifi_link_info.bany_client_join_go)
+		ap_enable = TRUE;
+#endif
+
+	if ((ap_enable) && (byte1 & BIT(4) && !(byte1 & BIT(5)))) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], %s == FW for AP mode\n", __func__);
+		BTC_TRACE(trace_buf);
+
+		real_byte1 &= ~BIT(4);
+		real_byte1 |= BIT(5);
+
+		real_byte5 |= BIT(5);
+		real_byte5 &= ~BIT(6);
+
+		ps_type = BTC_PS_WIFI_NATIVE;
+		halbtc8821c2ant_power_save_state(btc, ps_type, 0x0, 0x0);
+	} else if (byte1 & BIT(4) && !(byte1 & BIT(5))) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], %s == Force LPS (byte1 = 0x%x)\n",
+			    __func__, byte1);
+		BTC_TRACE(trace_buf);
+
+		ps_type = BTC_PS_LPS_OFF;
+		if (!halbtc8821c2ant_power_save_state(btc, ps_type, 0x50, 0x4))
+			result = TRUE;
+	} else {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], %s == Native LPS (byte1 = 0x%x)\n",
+			    __func__, byte1);
+		BTC_TRACE(trace_buf);
+
+		ps_type = BTC_PS_WIFI_NATIVE;
+		halbtc8821c2ant_power_save_state(btc, ps_type, 0x0, 0x0);
+	}
+
+	coex_sta->is_set_ps_state_fail = result;
+
+	if (!coex_sta->is_set_ps_state_fail) {
+		h2c_parameter[0] = real_byte1;
+		h2c_parameter[1] = byte2;
+		h2c_parameter[2] = byte3;
+		h2c_parameter[3] = byte4;
+		h2c_parameter[4] = real_byte5;
+
+		coex_dm->ps_tdma_para[0] = real_byte1;
+		coex_dm->ps_tdma_para[1] = byte2;
+		coex_dm->ps_tdma_para[2] = byte3;
+		coex_dm->ps_tdma_para[3] = byte4;
+		coex_dm->ps_tdma_para[4] = real_byte5;
+
+		btc->btc_fill_h2c(btc, 0x60, 5, h2c_parameter);
+	} else {
+		coex_sta->cnt_set_ps_state_fail++;
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], %s == Force Leave LPS Fail (cnt = %d)\n",
+			    __func__, coex_sta->cnt_set_ps_state_fail);
+		BTC_TRACE(trace_buf);
+	}
+
+	if (ps_type == BTC_PS_WIFI_NATIVE)
+		btc->btc_set(btc, BTC_SET_ACT_POST_NORMAL_LPS, NULL);
+}
+
+static
+void halbtc8821c2ant_tdma(struct btc_coexist *btc,
+			  boolean force_exec, boolean turn_on, u8 type)
+{
+	struct coex_sta_8821c_2ant *coex_sta = &btc->coex_sta_8821c_2ant;
+	struct coex_dm_8821c_2ant *coex_dm = &btc->coex_dm_8821c_2ant;
+	static u8 tdma_byte4_modify, pre_tdma_byte4_modify;
+	struct btc_bt_link_info *bt_link_info = &btc->bt_link_info;
+
+	btc->btc_set_atomic(btc, &coex_dm->setting_tdma, TRUE);
+
+	/* 0x778 = 0x1 at wifi slot (no blocking BT Low-Pri pkts) */
+	if (bt_link_info->slave_role && bt_link_info->a2dp_exist)
+		tdma_byte4_modify = 0x1;
+	else
+		tdma_byte4_modify = 0x0;
+
+	if (pre_tdma_byte4_modify != tdma_byte4_modify) {
+		force_exec = TRUE;
+		pre_tdma_byte4_modify = tdma_byte4_modify;
+	}
+
+	if (!force_exec) {
+		if (turn_on == coex_dm->cur_ps_tdma_on &&
+		    type == coex_dm->cur_ps_tdma) {
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				    "[BTCoex], Skip TDMA because no change TDMA(%s, %d)\n",
+				    (coex_dm->cur_ps_tdma_on ? "on" : "off"),
+				    coex_dm->cur_ps_tdma);
+			BTC_TRACE(trace_buf);
+
+			btc->btc_set_atomic(btc, &coex_dm->setting_tdma, FALSE);
+			return;
+		}
+	}
+
+	if (turn_on) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], ********** TDMA(on, %d) **********\n",
+			    type);
+		BTC_TRACE(trace_buf);
+
+		/* enable TBTT nterrupt */
+		btc->btc_write_1byte_bitmask(btc, 0x550, 0x8, 0x1);
+
+		switch (type) {
+		case 1:
+			halbtc8821c2ant_set_tdma(btc, 0x61, 0x10, 0x03, 0x91,
+						 0x50 | tdma_byte4_modify);
+			break;
+		case 2:
+		default:
+			halbtc8821c2ant_set_tdma(btc, 0x61, 0x35, 0x03, 0x11,
+						 0x11 | tdma_byte4_modify);
+			break;
+		case 3:
+			halbtc8821c2ant_set_tdma(btc, 0x61, 0x30, 0x3, 0x91,
+						 0x10 | tdma_byte4_modify);
+			break;
+		case 4:
+			halbtc8821c2ant_set_tdma(btc, 0x61, 0x21, 0x3, 0x91,
+						 0x10 | tdma_byte4_modify);
+			break;
+		case 5:
+			halbtc8821c2ant_set_tdma(btc, 0x61, 0x25, 0x3, 0x91,
+						 0x10 | tdma_byte4_modify);
+			break;
+		case 6:
+			halbtc8821c2ant_set_tdma(btc, 0x61, 0x10, 0x3, 0x91,
+						 0x10 | tdma_byte4_modify);
+			break;
+		case 7:
+			halbtc8821c2ant_set_tdma(btc, 0x61, 0x20, 0x3, 0x91,
+						 0x10 | tdma_byte4_modify);
+			break;
+		case 8:
+			halbtc8821c2ant_set_tdma(btc, 0x61, 0x15, 0x03, 0x11,
+						 0x11);
+			break;
+		case 10:
+			halbtc8821c2ant_set_tdma(btc, 0x61, 0x30, 0x03, 0x11,
+						 0x10);
+			break;
+		case 11:
+			halbtc8821c2ant_set_tdma(btc, 0x61, 0x35, 0x03, 0x11,
+						 0x10 | tdma_byte4_modify);
+			break;
+		case 12:
+			halbtc8821c2ant_set_tdma(btc, 0x61, 0x35, 0x03, 0x11,
+						 0x11);
+			break;
+		case 13:
+			halbtc8821c2ant_set_tdma(btc, 0x61, 0x1c, 0x03, 0x11,
+						 0x10 | tdma_byte4_modify);
+			break;
+		case 14:
+			halbtc8821c2ant_set_tdma(btc, 0x61, 0x20, 0x03, 0x11,
+						 0x11);
+			break;
+		case 15:
+			halbtc8821c2ant_set_tdma(btc, 0x61, 0x10, 0x03, 0x11,
+						 0x10);
+			break;
+		case 16:
+			halbtc8821c2ant_set_tdma(btc, 0x61, 0x10, 0x03, 0x11,
+						 0x11);
+			break;
+		case 17:
+			halbtc8821c2ant_set_tdma(btc, 0x61, 0x08, 0x03, 0x11,
+						 0x14 | tdma_byte4_modify);
+			break;
+		case 21:
+			halbtc8821c2ant_set_tdma(btc, 0x61, 0x30, 0x03, 0x11,
+						 0x10);
+			break;
+		case 22:
+			halbtc8821c2ant_set_tdma(btc, 0x61, 0x25, 0x03, 0x11,
+						 0x10);
+			break;
+		case 23:
+			halbtc8821c2ant_set_tdma(btc, 0x61, 0x10, 0x03, 0x11,
+						 0x10);
+			break;
+		case 25:
+			halbtc8821c2ant_set_tdma(btc, 0x51, 0x3a, 0x3, 0x11,
+						 0x50);
+			break;
+		case 51:
+			halbtc8821c2ant_set_tdma(btc, 0x61, 0x10, 0x03, 0x91,
+						 0x10 | tdma_byte4_modify);
+			break;
+		case 101:
+			halbtc8821c2ant_set_tdma(btc, 0x51, 0x08, 0x03, 0x10,
+						 0x54 | tdma_byte4_modify);
+			break;
+		case 102:
+			halbtc8821c2ant_set_tdma(btc, 0x61, 0x35, 0x03, 0x11,
+						 0x11 | tdma_byte4_modify);
+			break;
+		case 103:
+			halbtc8821c2ant_set_tdma(btc, 0x51, 0x30, 0x3, 0x10,
+						 0x50 | tdma_byte4_modify);
+			break;
+		case 104:
+			halbtc8821c2ant_set_tdma(btc, 0x51, 0x21, 0x3, 0x10,
+						 0x50 | tdma_byte4_modify);
+			break;
+		case 105:
+			halbtc8821c2ant_set_tdma(btc, 0x51, 0x45, 0x3, 0x10,
+						 0x50);
+			break;
+		case 106:
+			halbtc8821c2ant_set_tdma(btc, 0x51, 0x1a, 0x3, 0x10,
+						 0x50 | tdma_byte4_modify);
+			break;
+		case 107:
+			halbtc8821c2ant_set_tdma(btc, 0x51, 0x08, 0x7, 0x10,
+						 0x54);
+			break;
+		case 108:
+			halbtc8821c2ant_set_tdma(btc, 0x51, 0x30, 0x3, 0x10,
+						 0x50 | tdma_byte4_modify);
+			break;
+		case 109:
+			halbtc8821c2ant_set_tdma(btc, 0x51, 0x08, 0x03, 0x10,
+						 0x54 | tdma_byte4_modify);
+			break;
+		case 110:
+			halbtc8821c2ant_set_tdma(btc, 0x51, 0x30, 0x03, 0x10,
+						 0x50);
+			break;
+		case 111:
+			halbtc8821c2ant_set_tdma(btc, 0x61, 0x25, 0x03, 0x11,
+						 0x11);
+			break;
+		case 112:
+			halbtc8821c2ant_set_tdma(btc, 0x51, 0x4a, 0x3, 0x10,
+						 0x50);
+			break;
+		case 113:
+			halbtc8821c2ant_set_tdma(btc, 0x61, 0x48, 0x03, 0x11,
+						 0x10);
+			break;
+		case 115:
+			halbtc8821c2ant_set_tdma(btc, 0x51, 0x30, 0x03, 0x10,
+						 0x50);
+			break;
+		case 116: /* Not use  */
+			halbtc8821c2ant_set_tdma(btc, 0x51, 0x08, 0x03, 0x10,
+						 0x54 | tdma_byte4_modify);
+			break;
+		case 117: /* Not use  */
+			halbtc8821c2ant_set_tdma(btc, 0x61, 0x08, 0x03, 0x10,
+						 0x10 | tdma_byte4_modify);
+			break;
+		case 119:
+			halbtc8821c2ant_set_tdma(btc, 0x61, 0x08, 0x03, 0x10,
+						 0x14 | tdma_byte4_modify);
+			break;
+		case 151:
+			halbtc8821c2ant_set_tdma(btc, 0x51, 0x10, 0x03, 0x10,
+						 0x50 | tdma_byte4_modify);
+			break;
+		}
+	} else {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], ********** TDMA(off, %d) **********\n",
+			    type);
+		BTC_TRACE(trace_buf);
+
+		/* disable PS tdma */
+		switch (type) {
+		case 0:
+			halbtc8821c2ant_set_tdma(btc, 0x0, 0x0, 0x0, 0x40, 0x0);
+			break;
+		case 1:
+			halbtc8821c2ant_set_tdma(btc, 0x0, 0x0, 0x0, 0x48, 0x0);
+			break;
+		default:
+			halbtc8821c2ant_set_tdma(btc, 0x0, 0x0, 0x0, 0x40, 0x0);
+			break;
+		}
+	}
+
+	if (!coex_sta->is_set_ps_state_fail) {
+		/* update pre state */
+		coex_dm->cur_ps_tdma_on = turn_on;
+		coex_dm->cur_ps_tdma = type;
+	}
+
+	btc->btc_set_atomic(btc, &coex_dm->setting_tdma, FALSE);
+}
+
+static
+void halbtc8821c2ant_set_ant_switch(struct btc_coexist *btc,
+				    boolean force_exec, u8 ctrl_type,
+				    u8 pos_type)
+{
+	struct coex_dm_8821c_2ant *coex_dm = &btc->coex_dm_8821c_2ant;
+	struct rfe_type_8821c_2ant *rfe_type = &btc->rfe_type_8821c_2ant;
+	struct  btc_board_info	*board_info = &btc->board_info;
+	boolean	polarity_inverse = FALSE;
+	u8 regval = 0;
+	u32 u32tmp1 = 0, u32tmp2 = 0, u32tmp3 = 0;
+
+	if (!rfe_type->ext_ant_switch_exist)
+		return;
+
+	if (!force_exec) {
+		if (((ctrl_type << 8) + pos_type) ==
+					coex_dm->cur_ext_ant_switch_status)
+			return;
+	}
+
+	coex_dm->cur_ext_ant_switch_status = (ctrl_type << 8)  + pos_type;
+
+	/* swap control polarity if use different switch control polarity
+	 * Normal switch polarity for DPDT,
+	 * 0xcb4[29:28] = 2b'01 => BTG to Main, WLG to Aux,
+	 * 0xcb4[29:28] = 2b'10 => BTG to Aux, WLG to Main
+	 * Normal switch polarity for SPDT,
+	 * 0xcb4[29:28] = 2b'01 => Ant to BTG,
+	 * 0xcb4[29:28] = 2b'10 => Ant to WLG
+	 */
+	if (rfe_type->ext_ant_switch_ctrl_polarity)
+		polarity_inverse =  !polarity_inverse;
+
+	/* swap control polarity if 1-Ant at Aux */
+	if (rfe_type->ant_at_main_port == FALSE)
+		polarity_inverse =  !polarity_inverse;
+
+	switch (pos_type) {
+	default:
+	case BT_8821C_2ANT_TO_BT:
+	case BT_8821C_2ANT_TO_NOCARE:
+	case BT_8821C_2ANT_TO_WLA:
+
+		break;
+	case BT_8821C_2ANT_TO_WLG:
+		if (!rfe_type->wlg_locate_at_btg)
+			polarity_inverse =  !polarity_inverse;
+
+		break;
+	}
+
+	if (board_info->ant_div_cfg)
+		ctrl_type = BT_8821C_2ANT_CTRL_BY_ANTDIV;
+
+
+	switch (ctrl_type) {
+	default:
+	case BT_8821C_2ANT_CTRL_BY_BBSW:
+		/*  0x4c[23] = 0 */
+		btc->btc_write_1byte_bitmask(btc, 0x4e, 0x80, 0x0);
+		/* 0x4c[24] = 1 */
+		btc->btc_write_1byte_bitmask(btc, 0x4f, 0x01, 0x1);
+		/* BB SW, DPDT use RFE_ctrl8 and RFE_ctrl9 as control pin */
+		btc->btc_write_1byte_bitmask(btc, 0xcb4, 0xff, 0x77);
+		/* 0xcb4[29:28] = 2b'01 for no switch_polarity_inverse,
+		 * DPDT_SEL_N =1, DPDT_SEL_P =0
+		 */
+		regval = (!polarity_inverse ? 0x1 : 0x2);
+		btc->btc_write_1byte_bitmask(btc, 0xcb7, 0x30, regval);
+		break;
+	case BT_8821C_2ANT_CTRL_BY_PTA:
+		/* 0x4c[23] = 0 */
+		btc->btc_write_1byte_bitmask(btc, 0x4e, 0x80, 0x0);
+		/* 0x4c[24] = 1 */
+		btc->btc_write_1byte_bitmask(btc, 0x4f, 0x01, 0x1);
+		/* PTA,  DPDT use RFE_ctrl8 and RFE_ctrl9 as control pin */
+		btc->btc_write_1byte_bitmask(btc, 0xcb4, 0xff, 0x66);
+		/* 0xcb4[29:28] = 2b'10 for no switch_polatiry_inverse,
+		 * DPDT_SEL_N =1, DPDT_SEL_P =0  @ GNT_BT=1
+		 */
+		regval = (!polarity_inverse ? 0x2 : 0x1);
+		btc->btc_write_1byte_bitmask(btc, 0xcb7, 0x30, regval);
+		break;
+	case BT_8821C_2ANT_CTRL_BY_ANTDIV:
+		/* 0x4c[23] = 0 */
+		btc->btc_write_1byte_bitmask(btc, 0x4e, 0x80, 0x0);
+		/* 0x4c[24] = 1 */
+		btc->btc_write_1byte_bitmask(btc, 0x4f, 0x01, 0x1);
+		btc->btc_write_1byte_bitmask(btc, 0xcb4, 0xff, 0x88);
+
+		/* no regval_0xcb7 setup required, because antenna switch
+		 * control value by antenna diversity
+		 */
+		break;
+	case BT_8821C_2ANT_CTRL_BY_MAC:
+		/*  0x4c[23] = 1 */
+		btc->btc_write_1byte_bitmask(btc, 0x4e, 0x80, 0x1);
+		/* 0x64[0] = 1b'0 for no switch_polarity_inverse,
+		 * DPDT_SEL_N =1, DPDT_SEL_P =0
+		 */
+		regval = (!polarity_inverse ?  0x0 : 0x1);
+		btc->btc_write_1byte_bitmask(btc, 0x64, 0x1, regval);
+		break;
+	case BT_8821C_2ANT_CTRL_BY_FW:
+		/* 0x4c[23] = 0 */
+		btc->btc_write_1byte_bitmask(btc, 0x4e, 0x80, 0x0);
+		/* 0x4c[24] = 1 */
+		btc->btc_write_1byte_bitmask(btc, 0x4f, 0x01, 0x1);
+		break;
+	case BT_8821C_2ANT_CTRL_BY_BT:
+		/* 0x4c[23] = 0 */
+		btc->btc_write_1byte_bitmask(btc, 0x4e, 0x80, 0x0);
+		/* 0x4c[24] = 0 */
+		btc->btc_write_1byte_bitmask(btc, 0x4f, 0x01, 0x0);
+		/* no  setup required, because  antenna switch control value
+		 * by BT vendor 0xac[1:0]
+		 */
+		break;
+	}
+
+	/* PAPE, LNA_ON control by BT  while WLAN off
+	 * for current leakage issue
+	 */
+	if (ctrl_type == BT_8821C_2ANT_CTRL_BY_BT) {
+		/* PAPE   0x64[29] = 0 */
+		btc->btc_write_1byte_bitmask(btc, 0x67, 0x20, 0x0);
+		/* LNA_ON 0x64[28] = 0 */
+		btc->btc_write_1byte_bitmask(btc, 0x67, 0x10, 0x0);
+	} else {
+		/* PAPE   0x64[29] = 1 */
+		btc->btc_write_1byte_bitmask(btc, 0x67, 0x20, 0x1);
+		/* LNA_ON 0x64[28] = 1 */
+		btc->btc_write_1byte_bitmask(btc, 0x67, 0x10, 0x1);
+	}
+}
+
+static
+void halbtc8821c2ant_set_rfe_type(struct btc_coexist *btc)
+{
+	struct rfe_type_8821c_2ant *rfe_type = &btc->rfe_type_8821c_2ant;
+	struct  btc_board_info *board_info = &btc->board_info;
+
+	/* the following setup should be got from Efuse in the future */
+	rfe_type->rfe_module_type = board_info->rfe_type & 0x1f;
+
+	rfe_type->ext_ant_switch_ctrl_polarity = 0;
+
+	switch (rfe_type->rfe_module_type) {
+	case 0:
+	case 8:
+	default: /*2-Ant, DPDT, WLG*/
+		rfe_type->ext_ant_switch_exist = TRUE;
+		rfe_type->ext_ant_switch_type = BT_8821C_2ANT_USE_DPDT;
+		rfe_type->wlg_locate_at_btg = FALSE;
+		rfe_type->ant_at_main_port = TRUE;
+		break;
+	case 1:
+	case 9:  /*1-Ant, Main, WLG */
+		rfe_type->ext_ant_switch_exist = TRUE;
+		rfe_type->ext_ant_switch_type = BT_8821C_2ANT_USE_SPDT;
+		rfe_type->wlg_locate_at_btg = FALSE;
+		rfe_type->ant_at_main_port = TRUE;
+		break;
+	case 2:
+	case 10:  /*1-Ant, Main, BTG */
+		rfe_type->ext_ant_switch_exist = TRUE;
+		rfe_type->ext_ant_switch_type = BT_8821C_2ANT_USE_SPDT;
+		rfe_type->wlg_locate_at_btg = TRUE;
+		rfe_type->ant_at_main_port = TRUE;
+		break;
+	case 3:
+	case 11: /*1-Ant, Aux, WLG */
+		rfe_type->ext_ant_switch_exist = TRUE;
+		rfe_type->ext_ant_switch_type = BT_8821C_2ANT_USE_DPDT;
+		rfe_type->wlg_locate_at_btg = FALSE;
+		rfe_type->ant_at_main_port = FALSE;
+		break;
+	case 4:
+	case 12: /*1-Ant, Aux, BTG */
+		rfe_type->ext_ant_switch_exist = TRUE;
+		rfe_type->ext_ant_switch_type = BT_8821C_2ANT_USE_DPDT;
+		rfe_type->wlg_locate_at_btg = TRUE;
+		rfe_type->ant_at_main_port = FALSE;
+		break;
+	case 5:
+	case 13: /*2-Ant, no switch, WLG*/
+		rfe_type->ext_ant_switch_exist = FALSE;
+		rfe_type->ext_ant_switch_type = BT_8821C_2ANT_SWITCH_NONE;
+		rfe_type->wlg_locate_at_btg = FALSE;
+		rfe_type->ant_at_main_port = TRUE;
+		break;
+	case 6:
+	case 14: /*2-Ant, no antenna switch, WLG*/
+		rfe_type->ext_ant_switch_exist = FALSE;
+		rfe_type->ext_ant_switch_type = BT_8821C_2ANT_SWITCH_NONE;
+		rfe_type->wlg_locate_at_btg = FALSE;
+		rfe_type->ant_at_main_port = TRUE;
+		break;
+	case 7:
+	case 15: /*2-Ant, DPDT, BTG*/
+		rfe_type->ext_ant_switch_exist = TRUE;
+		rfe_type->ext_ant_switch_type = BT_8821C_2ANT_USE_DPDT;
+		rfe_type->wlg_locate_at_btg = TRUE;
+		rfe_type->ant_at_main_port = TRUE;
+		break;
+	}
+}
+
+static
+void halbtc8821c2ant_set_ant_path(struct btc_coexist *btc,
+				  u8 ant_pos_type,  boolean force_exec,
+				  u8 phase)
+{
+	struct coex_sta_8821c_2ant *coex_sta = &btc->coex_sta_8821c_2ant;
+	struct coex_dm_8821c_2ant *coex_dm = &btc->coex_dm_8821c_2ant;
+	struct btc_board_info *board_info = &btc->board_info;
+	u32 cnt_bt_cal_chk = 0, u32tmp1 = 0, u32tmp2 = 0;
+	u8 u8tmp = 0, ctrl_type, pos_type;
+
+	if (!force_exec) {
+		if (coex_dm->cur_ant_pos_type == ((ant_pos_type << 8)  + phase))
+			return;
+	}
+
+	coex_dm->cur_ant_pos_type = (ant_pos_type << 8)  + phase;
+
+	if (btc->dbg_mode) {
+		u32tmp1 = btc->btc_read_4byte(btc, 0xcbc);
+		u32tmp2 = btc->btc_read_4byte(btc, 0xcb4);
+		u8tmp  = btc->btc_read_1byte(btc, 0x73);
+
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], (Before Ant Setup) 0xcb4 = 0x%x, 0xcbc = 0x%x, 0x73 = 0x%x\n",
+			    u32tmp1, u32tmp2, u8tmp);
+		BTC_TRACE(trace_buf);
+	}
+
+	switch (phase) {
+	case BT_8821C_2ANT_PHASE_POWERON:
+		/* set Path control owner to WL at initial step */
+		halbtc8821c2ant_coex_ctrl_owner(btc, BT_8821C_2ANT_PCO_BTSIDE);
+
+		if (ant_pos_type == BTC_ANT_PATH_AUTO) {
+			if (board_info->btdm_ant_pos ==
+			    BTC_ANTENNA_AT_MAIN_PORT)
+				ant_pos_type = BTC_ANT_WIFI_AT_MAIN;
+			else
+				ant_pos_type = BTC_ANT_WIFI_AT_AUX;
+		}
+
+		coex_sta->run_time_state = FALSE;
+		break;
+	case BT_8821C_2ANT_PHASE_INIT:
+		/* Disable LTE Coex Function in WiFi side
+		 * (this should be on if LTE coex is required)
+		 */
+		halbtc8821c2ant_ltecoex_enable(btc, 0x0);
+
+		/* GNT_WL_LTE always = 1
+		 * (this should be config if LTE coex is required)
+		 */
+		halbtc8821c2ant_ltecoex_table(btc, BT_8821C_2ANT_CTT_WL_VS_LTE,
+					      0xffff);
+
+		/* GNT_BT_LTE always = 1
+		 * (this should be config if LTE coex is required)
+		 */
+		halbtc8821c2ant_ltecoex_table(btc, BT_8821C_2ANT_CTT_BT_VS_LTE,
+					      0xffff);
+
+		/* Wait If BT IQK running, because Path control owner
+		 * is at BT during BT IQK (setup by WiFi firmware)
+		 */
+		while (cnt_bt_cal_chk <= 20) {
+			u8tmp = btc->btc_read_1byte(btc, 0x49c);
+			cnt_bt_cal_chk++;
+
+			if (u8tmp & BIT(1)) {
+				BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+					    "[BTCoex], ########### BT is calibrating (wait cnt=%d)\n",
+					    cnt_bt_cal_chk);
+				BTC_TRACE(trace_buf);
+				delay_ms(10);
+			} else {
+				BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+					    "[BTCoex], ********** BT is NOT calibrating (wait cnt=%d)\n",
+					    cnt_bt_cal_chk);
+				BTC_TRACE(trace_buf);
+				break;
+			}
+		}
+
+		/* set Path control owner to WL at initial step */
+		halbtc8821c2ant_coex_ctrl_owner(btc, BT_8821C_2ANT_PCO_WLSIDE);
+
+		/* set GNT_BT to SW high */
+		halbtc8821c2ant_set_gnt_bt(btc, BT_8821C_2ANT_GNT_BLOCK_RFC_BB,
+					   BT_8821C_2ANT_GNT_TYPE_CTRL_BY_SW,
+					   BT_8821C_2ANT_GNT_SET_TO_HIGH);
+		/* Set GNT_WL to SW high */
+		halbtc8821c2ant_set_gnt_wl(btc, BT_8821C_2ANT_GNT_BLOCK_RFC_BB,
+					   BT_8821C_2ANT_GNT_TYPE_CTRL_BY_SW,
+					   BT_8821C_2ANT_GNT_SET_TO_HIGH);
+
+		coex_sta->run_time_state = FALSE;
+
+		if (ant_pos_type == BTC_ANT_PATH_AUTO) {
+			if (board_info->btdm_ant_pos ==
+			    BTC_ANTENNA_AT_MAIN_PORT)
+				ant_pos_type = BTC_ANT_WIFI_AT_MAIN;
+			else
+				ant_pos_type = BTC_ANT_WIFI_AT_AUX;
+		}
+		break;
+	case BT_8821C_2ANT_PHASE_WONLY:
+		/* Disable LTE Coex Function in WiFi side
+		 * (this should be on if LTE coex is required)
+		 */
+		halbtc8821c2ant_ltecoex_enable(btc, 0x0);
+
+		/* GNT_WL_LTE always = 1
+		 * (this should be config if LTE coex is required)
+		 */
+		halbtc8821c2ant_ltecoex_table(btc, BT_8821C_2ANT_CTT_WL_VS_LTE,
+					      0xffff);
+
+		/* GNT_BT_LTE always = 1
+		 * (this should be config if LTE coex is required)
+		 */
+		halbtc8821c2ant_ltecoex_table(btc, BT_8821C_2ANT_CTT_BT_VS_LTE,
+					      0xffff);
+
+		/* set Path control owner to WL at initial step */
+		halbtc8821c2ant_coex_ctrl_owner(btc, BT_8821C_2ANT_PCO_WLSIDE);
+
+		/* set GNT_BT to SW Low */
+		halbtc8821c2ant_set_gnt_bt(btc, BT_8821C_2ANT_GNT_BLOCK_RFC_BB,
+					   BT_8821C_2ANT_GNT_TYPE_CTRL_BY_SW,
+					   BT_8821C_2ANT_GNT_SET_TO_LOW);
+		/* Set GNT_WL to SW high */
+		halbtc8821c2ant_set_gnt_wl(btc, BT_8821C_2ANT_GNT_BLOCK_RFC_BB,
+					   BT_8821C_2ANT_GNT_TYPE_CTRL_BY_SW,
+					   BT_8821C_2ANT_GNT_SET_TO_HIGH);
+
+		coex_sta->run_time_state = FALSE;
+
+		if (ant_pos_type == BTC_ANT_PATH_AUTO) {
+			if (board_info->btdm_ant_pos ==
+			    BTC_ANTENNA_AT_MAIN_PORT)
+				ant_pos_type = BTC_ANT_WIFI_AT_MAIN;
+			else
+				ant_pos_type = BTC_ANT_WIFI_AT_AUX;
+		}
+
+		break;
+	case BT_8821C_2ANT_PHASE_WOFF:
+		/* Disable LTE Coex Function in WiFi side */
+		halbtc8821c2ant_ltecoex_enable(btc, 0x0);
+
+		/* set Path control owner to BT */
+		halbtc8821c2ant_coex_ctrl_owner(btc, BT_8821C_2ANT_PCO_BTSIDE);
+
+		coex_sta->run_time_state = FALSE;
+		break;
+	case BT_8821C_2ANT_PHASE_2G:
+		while (cnt_bt_cal_chk <= 20) {
+			/* 0x49c[0]=1 WL IQK, 0x49c[1]=1 BT IQK*/
+			u8tmp = btc->btc_read_1byte(btc, 0x49c);
+
+			cnt_bt_cal_chk++;
+			if (u8tmp & BIT(0)) {
+				BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+					    "[BTCoex], ########### WL is IQK (wait cnt=%d)\n",
+					    cnt_bt_cal_chk);
+				BTC_TRACE(trace_buf);
+				delay_ms(10);
+			} else if (u8tmp & BIT(1)) {
+				BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+					    "[BTCoex], ########### BT is IQK (wait cnt=%d)\n",
+					    cnt_bt_cal_chk);
+				BTC_TRACE(trace_buf);
+				delay_ms(10);
+			} else {
+				BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+					    "[BTCoex], ********** WL and BT is NOT IQK (wait cnt=%d)\n",
+					    cnt_bt_cal_chk);
+				BTC_TRACE(trace_buf);
+				break;
+			}
+		}
+
+		/* set Path control owner to WL at runtime step */
+		halbtc8821c2ant_coex_ctrl_owner(btc, BT_8821C_2ANT_PCO_WLSIDE);
+
+		/* set GNT_BT to PTA */
+		halbtc8821c2ant_set_gnt_bt(btc, BT_8821C_2ANT_GNT_BLOCK_RFC_BB,
+					   BT_8821C_2ANT_GNT_TYPE_CTRL_BY_PTA,
+					   BT_8821C_2ANT_GNT_SET_BY_HW);
+
+		/* Set GNT_WL to PTA */
+		halbtc8821c2ant_set_gnt_wl(btc, BT_8821C_2ANT_GNT_BLOCK_RFC_BB,
+					   BT_8821C_2ANT_GNT_TYPE_CTRL_BY_PTA,
+					   BT_8821C_2ANT_GNT_SET_BY_HW);
+
+		coex_sta->run_time_state = TRUE;
+
+		if (ant_pos_type == BTC_ANT_PATH_AUTO) {
+			if (board_info->btdm_ant_pos ==
+			    BTC_ANTENNA_AT_MAIN_PORT)
+				ant_pos_type = BTC_ANT_WIFI_AT_MAIN;
+			else
+				ant_pos_type = BTC_ANT_WIFI_AT_AUX;
+		}
+
+		break;
+	case BT_8821C_2ANT_PHASE_5G:
+		/* set Path control owner to WL at runtime step */
+		halbtc8821c2ant_coex_ctrl_owner(btc, BT_8821C_2ANT_PCO_WLSIDE);
+
+		/* set GNT_BT to SW Hi */
+		halbtc8821c2ant_set_gnt_bt(btc, BT_8821C_2ANT_GNT_BLOCK_RFC_BB,
+					   BT_8821C_2ANT_GNT_TYPE_CTRL_BY_PTA,
+					   BT_8821C_2ANT_GNT_SET_BY_HW);
+
+		/* Set GNT_WL to SW Hi */
+		halbtc8821c2ant_set_gnt_wl(btc, BT_8821C_2ANT_GNT_BLOCK_RFC_BB,
+					   BT_8821C_2ANT_GNT_TYPE_CTRL_BY_SW,
+					   BT_8821C_2ANT_GNT_SET_TO_HIGH);
+
+		coex_sta->run_time_state = TRUE;
+
+		if (ant_pos_type == BTC_ANT_PATH_AUTO) {
+			if (board_info->btdm_ant_pos ==
+			    BTC_ANTENNA_AT_MAIN_PORT)
+				ant_pos_type = BTC_ANT_WIFI_AT_MAIN;
+			else
+				ant_pos_type = BTC_ANT_WIFI_AT_AUX;
+		}
+
+		break;
+	case BT_8821C_2ANT_PHASE_BTMP:
+		/* Disable LTE Coex Function in WiFi side */
+		halbtc8821c2ant_ltecoex_enable(btc, 0x0);
+
+		/* set Path control owner to WL */
+		halbtc8821c2ant_coex_ctrl_owner(btc, BT_8821C_2ANT_PCO_WLSIDE);
+
+		/* set GNT_BT to SW Hi */
+		halbtc8821c2ant_set_gnt_bt(btc, BT_8821C_2ANT_GNT_BLOCK_RFC_BB,
+					   BT_8821C_2ANT_GNT_TYPE_CTRL_BY_SW,
+					   BT_8821C_2ANT_GNT_SET_TO_HIGH);
+
+		/* Set GNT_WL to SW Lo */
+		halbtc8821c2ant_set_gnt_wl(btc, BT_8821C_2ANT_GNT_BLOCK_RFC_BB,
+					   BT_8821C_2ANT_GNT_TYPE_CTRL_BY_SW,
+					   BT_8821C_2ANT_GNT_SET_TO_LOW);
+
+		coex_sta->run_time_state = FALSE;
+
+		if (ant_pos_type == BTC_ANT_PATH_AUTO) {
+			if (board_info->btdm_ant_pos ==
+			    BTC_ANTENNA_AT_MAIN_PORT)
+				ant_pos_type = BTC_ANT_WIFI_AT_MAIN;
+			else
+				ant_pos_type = BTC_ANT_WIFI_AT_AUX;
+		}
+
+		break;
+	case BT_8821C_2ANT_PHASE_ANTDET:
+		halbtc8821c2ant_coex_ctrl_owner(btc, BT_8821C_2ANT_PCO_WLSIDE);
+
+		/* set GNT_BT to high */
+		halbtc8821c2ant_set_gnt_bt(btc, BT_8821C_2ANT_GNT_BLOCK_RFC_BB,
+					   BT_8821C_2ANT_GNT_TYPE_CTRL_BY_SW,
+					   BT_8821C_2ANT_GNT_SET_TO_HIGH);
+		/* Set GNT_WL to high */
+		halbtc8821c2ant_set_gnt_wl(btc, BT_8821C_2ANT_GNT_BLOCK_RFC_BB,
+					   BT_8821C_2ANT_GNT_TYPE_CTRL_BY_SW,
+					   BT_8821C_2ANT_GNT_SET_TO_HIGH);
+
+		if (ant_pos_type == BTC_ANT_PATH_AUTO) {
+			if (board_info->btdm_ant_pos ==
+			    BTC_ANTENNA_AT_MAIN_PORT)
+				ant_pos_type = BTC_ANT_WIFI_AT_MAIN;
+			else
+				ant_pos_type = BTC_ANT_WIFI_AT_AUX;
+		}
+
+		coex_sta->run_time_state = FALSE;
+		break;
+	}
+
+	if (phase != BT_8821C_2ANT_PHASE_WOFF) {
+		/* Set Ext Ant Switch to BT control at wifi off step */
+		ctrl_type = BT_8821C_2ANT_CTRL_BY_BT;
+		pos_type = BT_8821C_2ANT_TO_NOCARE;
+	} else {
+		switch (ant_pos_type) {
+		default:
+		case BTC_ANT_WIFI_AT_MAIN:
+			ctrl_type = BT_8821C_2ANT_CTRL_BY_BBSW;
+			pos_type = BT_8821C_2ANT_TO_WLG;
+			break;
+		case BTC_ANT_WIFI_AT_AUX:
+			ctrl_type = BT_8821C_2ANT_CTRL_BY_BBSW;
+			pos_type = BT_8821C_2ANT_TO_BT;
+			break;
+		case BTC_ANT_WIFI_AT_DIVERSITY:
+			ctrl_type = BT_8821C_2ANT_CTRL_BY_ANTDIV;
+			pos_type = BT_8821C_2ANT_TO_NOCARE;
+			break;
+		}
+	}
+
+	halbtc8821c2ant_set_ant_switch(btc, force_exec, ctrl_type, pos_type);
+
+	if (btc->dbg_mode) {
+		u32tmp1 = btc->btc_read_4byte(btc, 0xcbc);
+		u32tmp2 = btc->btc_read_4byte(btc, 0xcb4);
+		u8tmp  = btc->btc_read_1byte(btc, 0x73);
+
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], (After Ant Setup) 0xcb4 = 0x%x, 0xcbc = 0x%x, 0x73 = 0x%x\n",
+			    u32tmp1, u32tmp2, u8tmp);
+		BTC_TRACE(trace_buf);
+	}
+}
+
+static
+u8 halbtc8821c2ant_action_algorithm(struct btc_coexist *btc)
+{
+	struct btc_bt_link_info *bt_link_info = &btc->bt_link_info;
+	u8 algorithm = BT_8821C_2ANT_COEX_UNDEFINED;
+	u8 profile_map = 0;
+
+	if (bt_link_info->sco_exist)
+		profile_map = profile_map | BIT(0);
+
+	if (bt_link_info->hid_exist)
+		profile_map = profile_map | BIT(1);
+
+	if (bt_link_info->a2dp_exist)
+		profile_map = profile_map | BIT(2);
+
+	if (bt_link_info->pan_exist)
+		profile_map = profile_map | BIT(3);
+
+	switch (profile_map) {
+	default:
+	case 0:
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], No BT link exists!!!\n");
+		BTC_TRACE(trace_buf);
+		algorithm = BT_8821C_2ANT_COEX_UNDEFINED;
+		break;
+	case 1:
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], BT Profile = SCO only\n");
+		BTC_TRACE(trace_buf);
+		algorithm = BT_8821C_2ANT_COEX_SCO;
+		break;
+	case 2:
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], BT Profile = HID only\n");
+		BTC_TRACE(trace_buf);
+		algorithm = BT_8821C_2ANT_COEX_HID;
+		break;
+	case 3:
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], BT Profile = SCO + HID ==> HID\n");
+		BTC_TRACE(trace_buf);
+		algorithm = BT_8821C_2ANT_COEX_HID;
+		break;
+	case 4:
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				    "[BTCoex], BT Profile = A2DP only\n");
+		BTC_TRACE(trace_buf);
+		algorithm = BT_8821C_2ANT_COEX_A2DP;
+		break;
+	case 5:
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], BT Profile = SCO + A2DP ==> HID + A2DP\n");
+		BTC_TRACE(trace_buf);
+		algorithm = BT_8821C_2ANT_COEX_HID_A2DP;
+		break;
+	case 6:
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], BT Profile = HID + A2DP\n");
+		BTC_TRACE(trace_buf);
+		algorithm = BT_8821C_2ANT_COEX_HID_A2DP;
+		break;
+	case 7:
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], BT Profile = SCO + HID + A2DP ==> HID + A2DP\n");
+		BTC_TRACE(trace_buf);
+		algorithm = BT_8821C_2ANT_COEX_HID_A2DP;
+		break;
+	case 8:
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], BT Profile = PAN(EDR) only\n");
+		BTC_TRACE(trace_buf);
+		algorithm = BT_8821C_2ANT_COEX_PAN;
+		break;
+	case 9:
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], BT Profile = SCO + PAN(EDR) ==> HID + PAN(EDR)\n");
+		BTC_TRACE(trace_buf);
+		algorithm = BT_8821C_2ANT_COEX_PAN_HID;
+		break;
+	case 10:
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], BT Profile = HID + PAN(EDR)\n");
+		BTC_TRACE(trace_buf);
+		algorithm = BT_8821C_2ANT_COEX_PAN_HID;
+		break;
+	case 11:
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], BT Profile = SCO + HID + PAN(EDR) ==> HID + PAN(EDR)\n");
+		BTC_TRACE(trace_buf);
+		algorithm = BT_8821C_2ANT_COEX_PAN_HID;
+		break;
+	case 12:
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], BT Profile = A2DP + PAN(EDR)\n");
+		BTC_TRACE(trace_buf);
+		algorithm = BT_8821C_2ANT_COEX_PAN_A2DP;
+		break;
+	case 13:
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], BT Profile = SCO + A2DP + PAN(EDR) ==> A2DP + PAN(EDR)\n");
+		BTC_TRACE(trace_buf);
+		algorithm = BT_8821C_2ANT_COEX_PAN_A2DP;
+		break;
+	case 14:
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], BT Profile = HID + A2DP + PAN(EDR) ==> A2DP + PAN(EDR)\n");
+		BTC_TRACE(trace_buf);
+		algorithm = BT_8821C_2ANT_COEX_PAN_A2DP;
+		break;
+	case 15:
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], BT Profile = SCO + HID + A2DP + PAN(EDR) ==> A2DP + PAN(EDR)\n");
+		BTC_TRACE(trace_buf);
+		algorithm = BT_8821C_2ANT_COEX_PAN_A2DP;
+		break;
+	}
+
+	return algorithm;
+}
+
+
+static
+void halbtc8821c2ant_action_coex_all_off(struct btc_coexist *btc)
+{
+	halbtc8821c2ant_set_wl_tx_power(btc, NM_EXCU, 0xd8);
+	halbtc8821c2ant_set_bt_tx_power(btc, NM_EXCU, 0);
+
+	halbtc8821c2ant_table(btc, NM_EXCU, 0);
+	halbtc8821c2ant_tdma(btc, NM_EXCU, FALSE, 0);
+}
+
+static
+void halbtc8821c2ant_action_bt_whql_test(struct btc_coexist *btc)
+{
+	halbtc8821c2ant_set_wl_tx_power(btc, NM_EXCU, 0xd8);
+	halbtc8821c2ant_set_bt_tx_power(btc, NM_EXCU, 0);
+
+	halbtc8821c2ant_table(btc, NM_EXCU, 0);
+	halbtc8821c2ant_tdma(btc, NM_EXCU, FALSE, 0);
+}
+
+static
+void halbtc8821c2ant_action_bt_inquiry(struct btc_coexist *btc)
+{
+	struct coex_sta_8821c_2ant *coex_sta = &btc->coex_sta_8821c_2ant;
+	struct  btc_bt_link_info *bt_link_info = &btc->bt_link_info;
+	boolean	wifi_connected = FALSE, wifi_busy = FALSE;
+
+	halbtc8821c2ant_set_wl_tx_power(btc, FC_EXCU, 0xd8);
+	halbtc8821c2ant_set_bt_tx_power(btc, NM_EXCU, 0);
+
+	btc->btc_get(btc, BTC_GET_BL_WIFI_CONNECTED, &wifi_connected);
+	btc->btc_get(btc, BTC_GET_BL_WIFI_BUSY, &wifi_busy);
+
+	if (coex_sta->is_wifi_linkscan_process ||
+	    coex_sta->wifi_high_pri_task1 ||
+	    coex_sta->wifi_high_pri_task2) {
+
+		if (coex_sta->bt_create_connection) {
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				    "[BTCoex], bt page +  wifi hi-pri task\n");
+			BTC_TRACE(trace_buf);
+
+			halbtc8821c2ant_table(btc, NM_EXCU, 8);
+
+			if (bt_link_info->a2dp_exist &&
+			    !bt_link_info->pan_exist)
+				halbtc8821c2ant_tdma(btc, NM_EXCU, TRUE, 17);
+			else if (coex_sta->wifi_high_pri_task1)
+				halbtc8821c2ant_tdma(btc, NM_EXCU, TRUE, 113);
+			else
+				halbtc8821c2ant_tdma(btc, NM_EXCU, TRUE, 21);
+		} else {
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				    "[BTCoex], bt inquiry +  wifi hi-pri task\n");
+			BTC_TRACE(trace_buf);
+
+			halbtc8821c2ant_table(btc, NM_EXCU, 8);
+			halbtc8821c2ant_tdma(btc, NM_EXCU, TRUE, 21);
+		}
+	} else if (wifi_busy) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], bt inq/page +  wifi busy\n");
+		BTC_TRACE(trace_buf);
+
+		halbtc8821c2ant_table(btc, NM_EXCU, 8);
+		halbtc8821c2ant_tdma(btc, NM_EXCU, TRUE, 23);
+	} else if (wifi_connected) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], bt inq/page +  wifi connected\n");
+		BTC_TRACE(trace_buf);
+
+		halbtc8821c2ant_table(btc, NM_EXCU, 8);
+		halbtc8821c2ant_tdma(btc, NM_EXCU, TRUE, 23);
+	} else {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], bt inq/page +  wifi not-connected\n");
+		BTC_TRACE(trace_buf);
+		halbtc8821c2ant_table(btc, NM_EXCU, 0);
+		halbtc8821c2ant_tdma(btc, NM_EXCU, FALSE, 0);
+	}
+}
+
+static
+void halbtc8821c2ant_action_bt_relink(struct btc_coexist *btc)
+{
+	struct coex_sta_8821c_2ant *coex_sta = &btc->coex_sta_8821c_2ant;
+	struct  btc_bt_link_info *bt_link_info = &btc->bt_link_info;
+
+	if ((!coex_sta->is_bt_multi_link && !bt_link_info->pan_exist) ||
+	    (bt_link_info->a2dp_exist && bt_link_info->hid_exist)) {
+		halbtc8821c2ant_table(btc, NM_EXCU, 5);
+		halbtc8821c2ant_tdma(btc, NM_EXCU, FALSE, 0);
+	}
+}
+
+static
+void halbtc8821c2ant_action_bt_idle(struct btc_coexist *btc)
+{
+	struct coex_sta_8821c_2ant *coex_sta = &btc->coex_sta_8821c_2ant;
+	struct coex_dm_8821c_2ant *coex_dm = &btc->coex_dm_8821c_2ant;
+	boolean	wifi_busy = FALSE;
+
+	btc->btc_get(btc, BTC_GET_BL_WIFI_BUSY, &wifi_busy);
+
+	if (!wifi_busy) {
+		halbtc8821c2ant_table(btc, NM_EXCU, 8);
+		halbtc8821c2ant_tdma(btc, NM_EXCU, TRUE, 14);
+	} else {  /* if wl busy */
+		if ((coex_sta->bt_ble_scan_type & 0x2) &&
+		    BT_8821C_2ANT_BSTATUS_NCON_IDLE ==
+		    coex_dm->bt_status) {
+			halbtc8821c2ant_table(btc, NM_EXCU, 14);
+			halbtc8821c2ant_tdma(btc, NM_EXCU, TRUE, 12);
+		} else {
+			halbtc8821c2ant_table(btc, NM_EXCU, 8);
+			halbtc8821c2ant_tdma(btc, NM_EXCU, TRUE, 12);
+		}
+	}
+
+	halbtc8821c2ant_set_wl_tx_power(btc, FC_EXCU, 0xd8);
+	halbtc8821c2ant_set_bt_tx_power(btc, NM_EXCU, 0);
+}
+
+static
+void halbtc8821c2ant_action_bt_mr(struct btc_coexist *btc)
+{
+	struct wifi_link_info_8821c_2ant *wifi_link_info_ext =
+					 &btc->wifi_link_info_8821c_2ant;
+
+	if (!wifi_link_info_ext->is_all_under_5g) {
+		halbtc8821c2ant_set_ant_path(btc, BTC_ANT_PATH_AUTO, NM_EXCU,
+					     BT_8821C_2ANT_PHASE_2G);
+
+		halbtc8821c2ant_table(btc, NM_EXCU, 0);
+		halbtc8821c2ant_tdma(btc, NM_EXCU, FALSE, 0);
+	} else {
+		halbtc8821c2ant_set_ant_path(btc, BTC_ANT_PATH_AUTO, NM_EXCU,
+					     BT_8821C_2ANT_PHASE_5G);
+
+		halbtc8821c2ant_table(btc, NM_EXCU, 0);
+		halbtc8821c2ant_tdma(btc, NM_EXCU, FALSE, 0);
+	}
+}
+
+/* SCO only or SCO+PAN(HS) */
+static
+void halbtc8821c2ant_action_sco(struct btc_coexist *btc)
+{
+	struct coex_sta_8821c_2ant *coex_sta = &btc->coex_sta_8821c_2ant;
+	struct coex_dm_8821c_2ant *coex_dm = &btc->coex_dm_8821c_2ant;
+	static u8	prewifi_rssi_state = BTC_RSSI_STATE_LOW;
+	static u8	pre_bt_rssi_state = BTC_RSSI_STATE_LOW;
+	u8 wifi_rssi_state, bt_rssi_state;
+
+	wifi_rssi_state =
+		halbtc8821c2ant_wifi_rssi_state(btc, &prewifi_rssi_state, 2,
+						coex_sta->wifi_coex_thres, 0);
+
+	bt_rssi_state =
+		halbtc8821c2ant_bt_rssi_state(btc, &pre_bt_rssi_state, 2,
+					      coex_sta->bt_coex_thres, 0);
+
+	if (BTC_RSSI_HIGH(wifi_rssi_state) && BTC_RSSI_HIGH(bt_rssi_state)) {
+		halbtc8821c2ant_set_wl_tx_power(btc, NM_EXCU, 0xd8);
+		halbtc8821c2ant_set_bt_tx_power(btc, NM_EXCU, 0);
+
+		coex_dm->is_switch_to_1dot5_ant = FALSE;
+
+		halbtc8821c2ant_table(btc, NM_EXCU, 0);
+
+		halbtc8821c2ant_tdma(btc, NM_EXCU, FALSE, 0);
+	}  else {
+		halbtc8821c2ant_set_wl_tx_power(btc, NM_EXCU, 0xd8);
+		halbtc8821c2ant_set_bt_tx_power(btc, NM_EXCU, 0);
+
+		coex_dm->is_switch_to_1dot5_ant = FALSE;
+
+		if (coex_sta->is_bt_multi_link) {
+			halbtc8821c2ant_table(btc, NM_EXCU, 7);
+			halbtc8821c2ant_tdma(btc, NM_EXCU, TRUE, 25);
+		} else {
+			if (coex_sta->is_esco_mode)
+				halbtc8821c2ant_table(btc, NM_EXCU, 1);
+			else  /* 2-Ant free run if SCO mode */
+				halbtc8821c2ant_table(btc, NM_EXCU, 0);
+
+			halbtc8821c2ant_tdma(btc, NM_EXCU, TRUE, 8);
+		}
+	}
+}
+
+static
+void halbtc8821c2ant_action_hid(struct btc_coexist *btc)
+{
+	struct coex_sta_8821c_2ant *coex_sta = &btc->coex_sta_8821c_2ant;
+	struct coex_dm_8821c_2ant *coex_dm = &btc->coex_dm_8821c_2ant;
+	static u8	prewifi_rssi_state = BTC_RSSI_STATE_LOW;
+	static u8	pre_bt_rssi_state = BTC_RSSI_STATE_LOW;
+	u8 wifi_rssi_state, bt_rssi_state;
+	boolean	wifi_busy = FALSE;
+	u32  wifi_bw = 1;
+
+	btc->btc_get(btc, BTC_GET_BL_WIFI_BUSY, &wifi_busy);
+	btc->btc_get(btc, BTC_GET_U4_WIFI_BW,  &wifi_bw);
+
+	wifi_rssi_state =
+		halbtc8821c2ant_wifi_rssi_state(btc, &prewifi_rssi_state, 2,
+						coex_sta->wifi_coex_thres, 0);
+
+	bt_rssi_state =
+		halbtc8821c2ant_bt_rssi_state(btc, &pre_bt_rssi_state, 2,
+					      coex_sta->bt_coex_thres, 0);
+
+	if (BTC_RSSI_HIGH(wifi_rssi_state) &&
+	    BTC_RSSI_HIGH(bt_rssi_state)) {
+		halbtc8821c2ant_set_wl_tx_power(btc, NM_EXCU, 0xd8);
+		halbtc8821c2ant_set_bt_tx_power(btc, NM_EXCU, 0);
+
+		coex_dm->is_switch_to_1dot5_ant = FALSE;
+
+		halbtc8821c2ant_table(btc, NM_EXCU, 0);
+
+		halbtc8821c2ant_tdma(btc, NM_EXCU, FALSE, 0);
+	}  else {
+		halbtc8821c2ant_set_wl_tx_power(btc, NM_EXCU, 0xd8);
+		halbtc8821c2ant_set_bt_tx_power(btc, NM_EXCU, 0);
+
+		coex_dm->is_switch_to_1dot5_ant = FALSE;
+
+		if (coex_sta->is_hid_low_pri_tx_overhead) {
+			halbtc8821c2ant_table(btc, NM_EXCU, 12);
+			halbtc8821c2ant_tdma(btc, NM_EXCU, TRUE, 108);
+		}  else if (coex_sta->is_hid_rcu) {
+			halbtc8821c2ant_table(btc, NM_EXCU, 12);
+
+			if (wifi_busy)
+				halbtc8821c2ant_tdma(btc, NM_EXCU, TRUE, 113);
+			else
+				halbtc8821c2ant_tdma(btc, NM_EXCU, TRUE, 111);
+		} else {
+			halbtc8821c2ant_table(btc, NM_EXCU, 12);
+			halbtc8821c2ant_tdma(btc, NM_EXCU, TRUE, 111);
+		}
+	}
+}
+
+static
+void halbtc8821c2ant_action_a2dpsink(struct btc_coexist *btc)
+{
+	struct coex_sta_8821c_2ant *coex_sta = &btc->coex_sta_8821c_2ant;
+	struct coex_dm_8821c_2ant *coex_dm = &btc->coex_dm_8821c_2ant;
+	static u8	prewifi_rssi_state = BTC_RSSI_STATE_LOW;
+	static u8	pre_bt_rssi_state = BTC_RSSI_STATE_LOW;
+	u8 wifi_rssi_state, bt_rssi_state;
+
+	static u8	prewifi_rssi_state2 = BTC_RSSI_STATE_LOW;
+	static u8	pre_bt_rssi_state2 = BTC_RSSI_STATE_LOW;
+	u8 wifi_rssi_state2, bt_rssi_state2;
+	boolean wifi_busy = FALSE;
+	struct	btc_bt_link_info *bt_link_info = &btc->bt_link_info;
+	boolean ap_enable = FALSE;
+
+	btc->btc_get(btc, BTC_GET_BL_WIFI_AP_MODE_ENABLE, &ap_enable);
+	btc->btc_get(btc, BTC_GET_BL_WIFI_BUSY, &wifi_busy);
+
+	wifi_rssi_state =
+		halbtc8821c2ant_wifi_rssi_state(btc, &prewifi_rssi_state, 2,
+						coex_sta->wifi_coex_thres, 0);
+
+	wifi_rssi_state2 =
+		halbtc8821c2ant_wifi_rssi_state(btc, &prewifi_rssi_state2, 2,
+						coex_sta->wifi_coex_thres2, 0);
+
+	bt_rssi_state =
+		halbtc8821c2ant_bt_rssi_state(btc, &pre_bt_rssi_state, 2,
+					      coex_sta->bt_coex_thres, 0);
+
+	bt_rssi_state2 =
+		halbtc8821c2ant_bt_rssi_state(btc, &pre_bt_rssi_state2, 2,
+					      coex_sta->bt_coex_thres2, 0);
+
+	if (BTC_RSSI_HIGH(wifi_rssi_state) &&
+		BTC_RSSI_HIGH(bt_rssi_state)) {
+		halbtc8821c2ant_set_wl_tx_power(btc, NM_EXCU, 0xd8);
+		halbtc8821c2ant_set_bt_tx_power(btc, NM_EXCU, 0);
+
+		coex_dm->is_switch_to_1dot5_ant = FALSE;
+
+		halbtc8821c2ant_table(btc, NM_EXCU, 0);
+
+		halbtc8821c2ant_tdma(btc, NM_EXCU, FALSE, 0);
+	} else if (BTC_RSSI_HIGH(wifi_rssi_state2) &&
+		   BTC_RSSI_HIGH(bt_rssi_state2)) {
+		halbtc8821c2ant_set_wl_tx_power(btc, NM_EXCU, 0xc8);
+		halbtc8821c2ant_set_bt_tx_power(btc, NM_EXCU, 2);
+
+		coex_dm->is_switch_to_1dot5_ant = FALSE;
+
+		halbtc8821c2ant_table(btc, NM_EXCU, 4);
+
+		if (wifi_busy)
+			halbtc8821c2ant_tdma(btc, NM_EXCU, TRUE, 1);
+		else
+			halbtc8821c2ant_tdma(btc, NM_EXCU, TRUE, 16);
+	} else {
+		halbtc8821c2ant_set_wl_tx_power(btc, NM_EXCU, 0xd8);
+		halbtc8821c2ant_set_bt_tx_power(btc, NM_EXCU, 0);
+
+		coex_dm->is_switch_to_1dot5_ant = TRUE;
+
+		if (ap_enable) {
+			halbtc8821c2ant_table(btc, NM_EXCU, 0);
+			halbtc8821c2ant_tdma(btc, NM_EXCU, FALSE, 0);
+		} else {
+			halbtc8821c2ant_table(btc, NM_EXCU, 8);
+			halbtc8821c2ant_tdma(btc, NM_EXCU, TRUE, 115);
+		}
+	}
+}
+
+/* A2DP only / PAN(EDR) only/ A2DP+PAN(HS) */
+static
+void halbtc8821c2ant_action_a2dp(struct btc_coexist *btc)
+{
+	struct coex_sta_8821c_2ant *coex_sta = &btc->coex_sta_8821c_2ant;
+	struct coex_dm_8821c_2ant *coex_dm = &btc->coex_dm_8821c_2ant;
+	static u8	prewifi_rssi_state = BTC_RSSI_STATE_LOW;
+	static u8	pre_bt_rssi_state = BTC_RSSI_STATE_LOW;
+	u8 wifi_rssi_state, bt_rssi_state;
+
+	static u8	prewifi_rssi_state2 = BTC_RSSI_STATE_LOW;
+	static u8	pre_bt_rssi_state2 = BTC_RSSI_STATE_LOW;
+	u8 wifi_rssi_state2, bt_rssi_state2;
+
+	static u8	prewifi_rssi_state3 = BTC_RSSI_STATE_LOW;
+	static u8	pre_bt_rssi_state3 = BTC_RSSI_STATE_LOW;
+	u8 wifi_rssi_state3, bt_rssi_state3;
+
+	boolean	wifi_busy = FALSE;
+	u8 iot_peer = BTC_IOT_PEER_UNKNOWN;
+
+	btc->btc_get(btc, BTC_GET_BL_WIFI_BUSY, &wifi_busy);
+
+	wifi_rssi_state =
+		halbtc8821c2ant_wifi_rssi_state(btc, &prewifi_rssi_state, 2,
+						coex_sta->wifi_coex_thres, 0);
+
+	wifi_rssi_state2 =
+		halbtc8821c2ant_wifi_rssi_state(btc, &prewifi_rssi_state2, 2,
+						coex_sta->wifi_coex_thres2, 0);
+
+	wifi_rssi_state3 =
+		halbtc8821c2ant_wifi_rssi_state(btc, &prewifi_rssi_state3, 2,
+						45, 0);
+
+	bt_rssi_state =
+		halbtc8821c2ant_bt_rssi_state(btc, &pre_bt_rssi_state, 2,
+					      coex_sta->bt_coex_thres, 0);
+
+	bt_rssi_state2 =
+		halbtc8821c2ant_bt_rssi_state(btc, &pre_bt_rssi_state2, 2,
+					      coex_sta->bt_coex_thres2, 0);
+
+	bt_rssi_state3 =
+		halbtc8821c2ant_bt_rssi_state(btc, &pre_bt_rssi_state3, 2,
+					      50, 0);
+
+	if (BTC_RSSI_HIGH(wifi_rssi_state) &&
+	    BTC_RSSI_HIGH(bt_rssi_state)) {
+		halbtc8821c2ant_set_wl_tx_power(btc, NM_EXCU, 0xd8);
+		halbtc8821c2ant_set_bt_tx_power(btc, NM_EXCU, 0);
+
+		coex_dm->is_switch_to_1dot5_ant = FALSE;
+
+		halbtc8821c2ant_table(btc, NM_EXCU, 0);
+
+		halbtc8821c2ant_tdma(btc, NM_EXCU, FALSE, 0);
+	} else if (BTC_RSSI_HIGH(wifi_rssi_state2) &&
+		   BTC_RSSI_HIGH(bt_rssi_state2)) {
+		halbtc8821c2ant_set_wl_tx_power(btc, NM_EXCU, 0xc8);
+		halbtc8821c2ant_set_bt_tx_power(btc, NM_EXCU, 2);
+
+		coex_dm->is_switch_to_1dot5_ant = FALSE;
+
+		halbtc8821c2ant_table(btc, NM_EXCU, 4);
+
+		if (wifi_busy)
+			halbtc8821c2ant_tdma(btc, NM_EXCU, TRUE, 1);
+		else
+			halbtc8821c2ant_tdma(btc, NM_EXCU, TRUE, 16);
+	} else {
+		coex_dm->is_switch_to_1dot5_ant = TRUE;
+		halbtc8821c2ant_set_wl_tx_power(btc, NM_EXCU, 0xd8);
+		halbtc8821c2ant_set_bt_tx_power(btc, NM_EXCU, 0);
+
+		halbtc8821c2ant_table(btc, NM_EXCU, 8);
+
+		if (BTC_RSSI_HIGH(wifi_rssi_state3))
+			halbtc8821c2ant_tdma(btc, NM_EXCU, TRUE, 119);
+		else
+			halbtc8821c2ant_tdma(btc, NM_EXCU, TRUE, 101);
+	}
+}
+
+static
+void halbtc8821c2ant_action_pan(struct btc_coexist *btc)
+{
+	struct coex_sta_8821c_2ant *coex_sta = &btc->coex_sta_8821c_2ant;
+	struct coex_dm_8821c_2ant *coex_dm = &btc->coex_dm_8821c_2ant;
+	static u8	prewifi_rssi_state = BTC_RSSI_STATE_LOW;
+	static u8	pre_bt_rssi_state = BTC_RSSI_STATE_LOW;
+	u8 wifi_rssi_state, bt_rssi_state;
+
+	static u8	prewifi_rssi_state2 = BTC_RSSI_STATE_LOW;
+	static u8	pre_bt_rssi_state2 = BTC_RSSI_STATE_LOW;
+	u8 wifi_rssi_state2, bt_rssi_state2;
+	boolean	wifi_busy = FALSE;
+
+	static u8	prewifi_rssi_state3 = BTC_RSSI_STATE_LOW;
+	static u8	pre_bt_rssi_state3 = BTC_RSSI_STATE_LOW;
+	u8 wifi_rssi_state3, bt_rssi_state3;
+
+	btc->btc_get(btc, BTC_GET_BL_WIFI_BUSY, &wifi_busy);
+
+	wifi_rssi_state =
+		halbtc8821c2ant_wifi_rssi_state(btc, &prewifi_rssi_state, 2,
+						coex_sta->wifi_coex_thres, 0);
+
+	wifi_rssi_state2 =
+		halbtc8821c2ant_wifi_rssi_state(btc, &prewifi_rssi_state2, 2,
+						coex_sta->wifi_coex_thres2, 0);
+
+	wifi_rssi_state3 =
+		halbtc8821c2ant_wifi_rssi_state(btc, &prewifi_rssi_state3, 2,
+						58, 0);
+
+	bt_rssi_state =
+		halbtc8821c2ant_bt_rssi_state(btc, &pre_bt_rssi_state, 2,
+					      coex_sta->bt_coex_thres, 0);
+
+	bt_rssi_state2 =
+		halbtc8821c2ant_bt_rssi_state(btc, &pre_bt_rssi_state2, 2,
+					      coex_sta->bt_coex_thres2, 0);
+
+	bt_rssi_state3 =
+		halbtc8821c2ant_bt_rssi_state(btc, &pre_bt_rssi_state3, 2,
+					      47, 0);
+#if 0
+	halbtc8821c2ant_set_wl_tx_power(btc, NM_EXCU, 0xd8);
+	halbtc8821c2ant_set_bt_tx_power(btc, NM_EXCU, 0);
+
+	coex_dm->is_switch_to_1dot5_ant = FALSE;
+
+	halbtc8821c2ant_table(btc, NM_EXCU, 8);
+
+	halbtc8821c2ant_tdma(btc, NM_EXCU, TRUE, 21);
+#endif
+
+#if 1
+	if (BTC_RSSI_HIGH(wifi_rssi_state) &&
+	    BTC_RSSI_HIGH(bt_rssi_state)) {
+		halbtc8821c2ant_set_wl_tx_power(btc, NM_EXCU, 0xd8);
+		halbtc8821c2ant_set_bt_tx_power(btc, NM_EXCU, 0);
+
+		coex_dm->is_switch_to_1dot5_ant = FALSE;
+
+		halbtc8821c2ant_table(btc, NM_EXCU, 0);
+
+		halbtc8821c2ant_tdma(btc, NM_EXCU, FALSE, 0);
+	} else if (BTC_RSSI_HIGH(wifi_rssi_state2) &&
+		   BTC_RSSI_HIGH(bt_rssi_state2)) {
+		halbtc8821c2ant_set_wl_tx_power(btc, NM_EXCU, 0xc8);
+		halbtc8821c2ant_set_bt_tx_power(btc, NM_EXCU, 2);
+
+		coex_dm->is_switch_to_1dot5_ant = FALSE;
+
+		halbtc8821c2ant_table(btc, NM_EXCU, 4);
+
+		if (wifi_busy)
+			halbtc8821c2ant_tdma(btc, NM_EXCU, TRUE, 3);
+		else
+			halbtc8821c2ant_tdma(btc, NM_EXCU, TRUE, 4);
+	} else {
+		halbtc8821c2ant_set_wl_tx_power(btc, NM_EXCU, 0xd8);
+		halbtc8821c2ant_set_bt_tx_power(btc, NM_EXCU, 0);
+
+		coex_dm->is_switch_to_1dot5_ant = TRUE;
+
+		/* for Lenovo CPT_For_WiFi OPP test  */
+		if (btc->board_info.customer_id == RT_CID_LENOVO_CHINA &&
+		    BTC_RSSI_HIGH(wifi_rssi_state3) && wifi_busy) {
+			halbtc8821c2ant_table(btc, NM_EXCU, 7);
+
+			halbtc8821c2ant_tdma(btc, NM_EXCU, TRUE, 103);
+		} else {
+			halbtc8821c2ant_table(btc, NM_EXCU, 7);
+
+			if (wifi_busy)
+				halbtc8821c2ant_tdma(btc, NM_EXCU, TRUE, 103);
+			else
+				halbtc8821c2ant_tdma(btc, NM_EXCU, TRUE, 104);
+		}
+	}
+#endif
+}
+
+static
+void halbtc8821c2ant_action_hid_a2dp(struct btc_coexist *btc)
+{
+	struct coex_sta_8821c_2ant *coex_sta = &btc->coex_sta_8821c_2ant;
+	struct coex_dm_8821c_2ant *coex_dm = &btc->coex_dm_8821c_2ant;
+	static u8	prewifi_rssi_state = BTC_RSSI_STATE_LOW;
+	static u8	pre_bt_rssi_state = BTC_RSSI_STATE_LOW;
+	u8 wifi_rssi_state, bt_rssi_state;
+
+	static u8	prewifi_rssi_state2 = BTC_RSSI_STATE_LOW;
+	static u8	pre_bt_rssi_state2 = BTC_RSSI_STATE_LOW;
+	u8 wifi_rssi_state2, bt_rssi_state2;
+	static u8	prewifi_rssi_state3 = BTC_RSSI_STATE_LOW;
+	u8 wifi_rssi_state3;
+	boolean	wifi_busy = FALSE;
+
+	btc->btc_get(btc, BTC_GET_BL_WIFI_BUSY, &wifi_busy);
+
+	wifi_rssi_state =
+		halbtc8821c2ant_wifi_rssi_state(btc, &prewifi_rssi_state, 2,
+						coex_sta->wifi_coex_thres, 0);
+
+	wifi_rssi_state2 =
+		halbtc8821c2ant_wifi_rssi_state(btc, &prewifi_rssi_state2, 2,
+						coex_sta->wifi_coex_thres2, 0);
+
+	wifi_rssi_state3 =
+		halbtc8821c2ant_wifi_rssi_state(btc, &prewifi_rssi_state3, 2,
+						45, 0);
+
+	bt_rssi_state =
+		halbtc8821c2ant_bt_rssi_state(btc, &pre_bt_rssi_state, 2,
+					      coex_sta->bt_coex_thres, 0);
+
+	bt_rssi_state2 =
+		halbtc8821c2ant_bt_rssi_state(btc, &pre_bt_rssi_state2, 2,
+					      coex_sta->bt_coex_thres2, 0);
+
+	if (BTC_RSSI_HIGH(wifi_rssi_state) &&
+	    BTC_RSSI_HIGH(bt_rssi_state)) {
+		halbtc8821c2ant_set_wl_tx_power(btc, NM_EXCU, 0xd8);
+		halbtc8821c2ant_set_bt_tx_power(btc, NM_EXCU, 0);
+
+		coex_dm->is_switch_to_1dot5_ant = FALSE;
+
+		halbtc8821c2ant_table(btc, NM_EXCU, 0);
+		halbtc8821c2ant_tdma(btc, NM_EXCU, FALSE, 0);
+	} else if (BTC_RSSI_HIGH(wifi_rssi_state2) &&
+		   BTC_RSSI_HIGH(bt_rssi_state2)) {
+		halbtc8821c2ant_set_wl_tx_power(btc, NM_EXCU, 0xc8);
+		halbtc8821c2ant_set_bt_tx_power(btc, NM_EXCU, 2);
+
+		coex_dm->is_switch_to_1dot5_ant = FALSE;
+
+		halbtc8821c2ant_table(btc, NM_EXCU, 4);
+
+		if (wifi_busy)
+			halbtc8821c2ant_tdma(btc, NM_EXCU, TRUE, 1);
+		else
+			halbtc8821c2ant_tdma(btc, NM_EXCU, TRUE, 16);
+	} else {
+		halbtc8821c2ant_set_wl_tx_power(btc, NM_EXCU, 0xd8);
+		halbtc8821c2ant_set_bt_tx_power(btc, NM_EXCU, 0);
+
+		coex_dm->is_switch_to_1dot5_ant = TRUE;
+
+		halbtc8821c2ant_table(btc, NM_EXCU, 12);
+
+		if (BTC_RSSI_HIGH(wifi_rssi_state3))
+			halbtc8821c2ant_tdma(btc, NM_EXCU, TRUE, 119);
+		else
+			halbtc8821c2ant_tdma(btc, NM_EXCU, TRUE, 109);
+	}
+}
+
+static
+void halbtc8821c2ant_action_a2dp_pan_hs(struct btc_coexist *btc)
+{
+	struct coex_sta_8821c_2ant *coex_sta = &btc->coex_sta_8821c_2ant;
+	struct coex_dm_8821c_2ant *coex_dm = &btc->coex_dm_8821c_2ant;
+	static u8	prewifi_rssi_state = BTC_RSSI_STATE_LOW;
+	static u8	pre_bt_rssi_state = BTC_RSSI_STATE_LOW;
+	u8 wifi_rssi_state, bt_rssi_state;
+
+	static u8	prewifi_rssi_state2 = BTC_RSSI_STATE_LOW;
+	static u8	pre_bt_rssi_state2 = BTC_RSSI_STATE_LOW;
+	u8 wifi_rssi_state2, bt_rssi_state2;
+	boolean	wifi_busy = FALSE;
+
+	btc->btc_get(btc, BTC_GET_BL_WIFI_BUSY, &wifi_busy);
+
+	wifi_rssi_state =
+		halbtc8821c2ant_wifi_rssi_state(btc, &prewifi_rssi_state, 2,
+						coex_sta->wifi_coex_thres, 0);
+
+	wifi_rssi_state2 =
+		halbtc8821c2ant_wifi_rssi_state(btc, &prewifi_rssi_state2, 2,
+						coex_sta->wifi_coex_thres2, 0);
+
+	bt_rssi_state =
+		halbtc8821c2ant_bt_rssi_state(btc, &pre_bt_rssi_state, 2,
+					      coex_sta->bt_coex_thres, 0);
+
+	bt_rssi_state2 =
+		halbtc8821c2ant_bt_rssi_state(btc, &pre_bt_rssi_state2, 2,
+					      coex_sta->bt_coex_thres2, 0);
+
+	if (BTC_RSSI_HIGH(wifi_rssi_state) &&
+	    BTC_RSSI_HIGH(bt_rssi_state)) {
+		halbtc8821c2ant_set_wl_tx_power(btc, NM_EXCU, 0xd8);
+		halbtc8821c2ant_set_bt_tx_power(btc, NM_EXCU, 0);
+
+		coex_dm->is_switch_to_1dot5_ant = FALSE;
+
+		halbtc8821c2ant_table(btc, NM_EXCU, 0);
+
+		halbtc8821c2ant_tdma(btc, NM_EXCU, FALSE, 0);
+	} else if (BTC_RSSI_HIGH(wifi_rssi_state2) &&
+		   BTC_RSSI_HIGH(bt_rssi_state2)) {
+		halbtc8821c2ant_set_wl_tx_power(btc, NM_EXCU, 0xc8);
+		halbtc8821c2ant_set_bt_tx_power(btc, NM_EXCU, 2);
+
+		coex_dm->is_switch_to_1dot5_ant = FALSE;
+
+		halbtc8821c2ant_table(btc, NM_EXCU, 4);
+
+		if (wifi_busy) {
+
+			if ((coex_sta->a2dp_bit_pool > 40) &&
+			    (coex_sta->a2dp_bit_pool < 255))
+				halbtc8821c2ant_tdma(btc, NM_EXCU, TRUE, 7);
+			else
+				halbtc8821c2ant_tdma(btc, NM_EXCU, TRUE, 5);
+		} else
+			halbtc8821c2ant_tdma(btc, NM_EXCU, TRUE, 6);
+
+	} else {
+		halbtc8821c2ant_set_wl_tx_power(btc, NM_EXCU, 0xd8);
+		halbtc8821c2ant_set_bt_tx_power(btc, NM_EXCU, 0);
+
+		coex_dm->is_switch_to_1dot5_ant = TRUE;
+
+		halbtc8821c2ant_table(btc, NM_EXCU, 8);
+		if (wifi_busy) {
+			if ((coex_sta->a2dp_bit_pool > 40) &&
+			    (coex_sta->a2dp_bit_pool < 255))
+				halbtc8821c2ant_tdma(btc, NM_EXCU, TRUE, 107);
+			else
+				halbtc8821c2ant_tdma(btc, NM_EXCU, TRUE, 105);
+		} else
+			halbtc8821c2ant_tdma(btc, NM_EXCU, TRUE, 106);
+	}
+}
+
+/* PAN(EDR)+A2DP */
+static
+void halbtc8821c2ant_action_pan_a2dp(struct btc_coexist *btc)
+{
+	struct coex_sta_8821c_2ant *coex_sta = &btc->coex_sta_8821c_2ant;
+	struct coex_dm_8821c_2ant *coex_dm = &btc->coex_dm_8821c_2ant;
+	static u8	prewifi_rssi_state3 = BTC_RSSI_STATE_LOW;
+	static u8	pre_bt_rssi_state3 = BTC_RSSI_STATE_LOW;
+	u8 wifi_rssi_state3, bt_rssi_state3;
+
+	boolean	wifi_busy = FALSE;
+	u8 iot_peer = BTC_IOT_PEER_UNKNOWN;
+
+	struct	btc_bt_link_info *bt_link_info = &btc->bt_link_info;
+
+	btc->btc_get(btc, BTC_GET_BL_WIFI_BUSY, &wifi_busy);
+	btc->btc_get(btc, BTC_GET_U1_IOT_PEER, &iot_peer);
+
+	if (!wifi_busy)
+		wifi_busy = coex_sta->gl_wifi_busy;
+
+	wifi_rssi_state3 =
+		halbtc8821c2ant_wifi_rssi_state(btc, &prewifi_rssi_state3, 2,
+						42, 0);
+	bt_rssi_state3 =
+		halbtc8821c2ant_bt_rssi_state(btc, &pre_bt_rssi_state3, 2,
+					      45, 0);
+
+	halbtc8821c2ant_set_wl_tx_power(btc, NM_EXCU, 0xd8);
+
+	coex_dm->is_switch_to_1dot5_ant = TRUE;
+
+	/* for Lenovo coex test case    */
+	if (btc->board_info.customer_id == RT_CID_LENOVO_CHINA &&
+	    coex_sta->scan_ap_num <= 10 &&
+	    iot_peer == BTC_IOT_PEER_ATHEROS) {
+		/* for CPT_for_WiFi   */
+		if (BTC_RSSI_LOW(wifi_rssi_state3)) {
+			halbtc8821c2ant_set_bt_tx_power(btc, NM_EXCU, 20);
+			if (wifi_busy) {
+				halbtc8821c2ant_table(btc, NM_EXCU, 7);
+				halbtc8821c2ant_tdma(btc, NM_EXCU, TRUE, 105);
+			} else {
+				halbtc8821c2ant_table(btc, NM_EXCU, 7);
+				halbtc8821c2ant_tdma(btc, NM_EXCU, TRUE, 107);
+			}
+		} else {  /* for CPT_for_BT   */
+			halbtc8821c2ant_set_bt_tx_power(btc, NM_EXCU, 0);
+			halbtc8821c2ant_table(btc, NM_EXCU, 8);
+			halbtc8821c2ant_tdma(btc, NM_EXCU, TRUE, 107);
+		}
+	} else {
+		halbtc8821c2ant_set_bt_tx_power(btc, NM_EXCU, 0);
+		halbtc8821c2ant_table(btc, NM_EXCU, 8);
+
+		if (wifi_busy)
+			halbtc8821c2ant_tdma(btc, NM_EXCU, TRUE, 107);
+		else
+			halbtc8821c2ant_tdma(btc, NM_EXCU, TRUE, 106);
+	}
+}
+
+static
+void halbtc8821c2ant_action_pan_hid(struct btc_coexist *btc)
+{
+	struct coex_sta_8821c_2ant *coex_sta = &btc->coex_sta_8821c_2ant;
+	struct coex_dm_8821c_2ant *coex_dm = &btc->coex_dm_8821c_2ant;
+	static u8	prewifi_rssi_state = BTC_RSSI_STATE_LOW;
+	static u8	pre_bt_rssi_state = BTC_RSSI_STATE_LOW;
+	u8 wifi_rssi_state, bt_rssi_state;
+
+	static u8	prewifi_rssi_state2 = BTC_RSSI_STATE_LOW;
+	static u8	pre_bt_rssi_state2 = BTC_RSSI_STATE_LOW;
+	u8 wifi_rssi_state2, bt_rssi_state2;
+	boolean	wifi_busy = FALSE;
+
+	btc->btc_get(btc, BTC_GET_BL_WIFI_BUSY, &wifi_busy);
+
+	wifi_rssi_state =
+		halbtc8821c2ant_wifi_rssi_state(btc, &prewifi_rssi_state, 2,
+						coex_sta->wifi_coex_thres, 0);
+
+	wifi_rssi_state2 =
+		halbtc8821c2ant_wifi_rssi_state(btc, &prewifi_rssi_state2, 2,
+						coex_sta->wifi_coex_thres2, 0);
+
+	bt_rssi_state =
+		halbtc8821c2ant_bt_rssi_state(btc, &pre_bt_rssi_state, 2,
+					      coex_sta->bt_coex_thres, 0);
+
+	bt_rssi_state2 =
+		halbtc8821c2ant_bt_rssi_state(btc, &pre_bt_rssi_state2, 2,
+					      coex_sta->bt_coex_thres2, 0);
+
+	if (BTC_RSSI_HIGH(wifi_rssi_state) &&
+	    BTC_RSSI_HIGH(bt_rssi_state)) {
+		halbtc8821c2ant_set_wl_tx_power(btc, NM_EXCU, 0xd8);
+		halbtc8821c2ant_set_bt_tx_power(btc, NM_EXCU, 0);
+
+		coex_dm->is_switch_to_1dot5_ant = FALSE;
+
+		halbtc8821c2ant_table(btc, NM_EXCU, 0);
+		halbtc8821c2ant_tdma(btc, NM_EXCU, FALSE, 0);
+	} else if (BTC_RSSI_HIGH(wifi_rssi_state2) &&
+		   BTC_RSSI_HIGH(bt_rssi_state2)) {
+		halbtc8821c2ant_set_wl_tx_power(btc, NM_EXCU, 0xc8);
+		halbtc8821c2ant_set_bt_tx_power(btc, NM_EXCU, 2);
+
+		coex_dm->is_switch_to_1dot5_ant = FALSE;
+
+		halbtc8821c2ant_table(btc, NM_EXCU, 4);
+
+		if (wifi_busy)
+			halbtc8821c2ant_tdma(btc, NM_EXCU, TRUE, 3);
+		else
+			halbtc8821c2ant_tdma(btc, NM_EXCU, TRUE, 4);
+	} else {
+		halbtc8821c2ant_set_wl_tx_power(btc, NM_EXCU, 0xd8);
+		halbtc8821c2ant_set_bt_tx_power(btc, NM_EXCU, 0);
+
+		coex_dm->is_switch_to_1dot5_ant = TRUE;
+
+		halbtc8821c2ant_table(btc, NM_EXCU, 6);
+
+		if (wifi_busy)
+			halbtc8821c2ant_tdma(btc, NM_EXCU, TRUE, 103);
+		else
+			halbtc8821c2ant_tdma(btc, NM_EXCU, TRUE, 104);
+	}
+}
+
+/* HID+A2DP+PAN(EDR) */
+static
+void halbtc8821c2ant_action_hid_a2dp_pan(struct btc_coexist *btc)
+{
+	struct coex_sta_8821c_2ant *coex_sta = &btc->coex_sta_8821c_2ant;
+	struct coex_dm_8821c_2ant *coex_dm = &btc->coex_dm_8821c_2ant;
+	static u8	prewifi_rssi_state = BTC_RSSI_STATE_LOW;
+	static u8	pre_bt_rssi_state = BTC_RSSI_STATE_LOW;
+	u8 wifi_rssi_state, bt_rssi_state;
+
+	static u8	prewifi_rssi_state2 = BTC_RSSI_STATE_LOW;
+	static u8	pre_bt_rssi_state2 = BTC_RSSI_STATE_LOW;
+	u8 wifi_rssi_state2, bt_rssi_state2;
+	boolean	wifi_busy = FALSE;
+
+	btc->btc_get(btc, BTC_GET_BL_WIFI_BUSY, &wifi_busy);
+
+	wifi_rssi_state =
+		halbtc8821c2ant_wifi_rssi_state(btc, &prewifi_rssi_state, 2,
+						coex_sta->wifi_coex_thres, 0);
+
+	wifi_rssi_state2 =
+		halbtc8821c2ant_wifi_rssi_state(btc, &prewifi_rssi_state2, 2,
+						coex_sta->wifi_coex_thres2, 0);
+
+	bt_rssi_state =
+		halbtc8821c2ant_bt_rssi_state(btc, &pre_bt_rssi_state, 2,
+					      coex_sta->bt_coex_thres, 0);
+
+	bt_rssi_state2 =
+		halbtc8821c2ant_bt_rssi_state(btc, &pre_bt_rssi_state2, 2,
+					      coex_sta->bt_coex_thres2, 0);
+
+	if (BTC_RSSI_HIGH(wifi_rssi_state) &&
+	    BTC_RSSI_HIGH(bt_rssi_state)) {
+		halbtc8821c2ant_set_wl_tx_power(btc, NM_EXCU, 0xd8);
+		halbtc8821c2ant_set_bt_tx_power(btc, NM_EXCU, 0);
+
+		coex_dm->is_switch_to_1dot5_ant = FALSE;
+
+		halbtc8821c2ant_table(btc, NM_EXCU, 0);
+		halbtc8821c2ant_tdma(btc, NM_EXCU, FALSE, 0);
+	} else if (BTC_RSSI_HIGH(wifi_rssi_state2) &&
+		   BTC_RSSI_HIGH(bt_rssi_state2)) {
+		halbtc8821c2ant_set_wl_tx_power(btc, NM_EXCU, 0xc8);
+		halbtc8821c2ant_set_bt_tx_power(btc, NM_EXCU, 2);
+
+		coex_dm->is_switch_to_1dot5_ant = FALSE;
+
+		halbtc8821c2ant_table(btc, NM_EXCU, 4);
+
+		if (wifi_busy) {
+			if ((coex_sta->a2dp_bit_pool > 40 &&
+			     coex_sta->a2dp_bit_pool < 255) ||
+			    !coex_sta->is_A2DP_3M)
+				halbtc8821c2ant_tdma(btc, NM_EXCU, TRUE, 7);
+			else
+				halbtc8821c2ant_tdma(btc, NM_EXCU, TRUE, 5);
+		} else
+			halbtc8821c2ant_tdma(btc, NM_EXCU, TRUE, 6);
+	} else {
+		halbtc8821c2ant_set_wl_tx_power(btc, NM_EXCU, 0xd8);
+		halbtc8821c2ant_set_bt_tx_power(btc, NM_EXCU, 0);
+
+		coex_dm->is_switch_to_1dot5_ant = TRUE;
+
+		halbtc8821c2ant_table(btc, NM_EXCU, 12);
+
+		if (wifi_busy)
+			halbtc8821c2ant_tdma(btc, NM_EXCU, TRUE, 107);
+		else
+			halbtc8821c2ant_tdma(btc, NM_EXCU, TRUE, 106);
+	}
+}
+
+static
+void halbtc8821c2ant_action_wifi_under5g(struct btc_coexist *btc)
+{
+	halbtc8821c2ant_set_wl_tx_power(btc, NM_EXCU, 0xd8);
+	halbtc8821c2ant_set_bt_tx_power(btc, NM_EXCU, 0);
+
+	halbtc8821c2ant_set_ant_path(btc, BTC_ANT_PATH_AUTO, NM_EXCU,
+				     BT_8821C_2ANT_PHASE_5G);
+	/* fw all off */
+	halbtc8821c2ant_table(btc, NM_EXCU, 0);
+	halbtc8821c2ant_tdma(btc, NM_EXCU, FALSE, 0);
+}
+
+static
+void halbtc8821c2ant_action_wifi_native_lps(struct btc_coexist *btc)
+{
+	halbtc8821c2ant_table(btc, NM_EXCU, 2);
+	halbtc8821c2ant_tdma(btc, NM_EXCU, FALSE, 0);
+}
+
+static
+void halbtc8821c2ant_action_wifi_linkscan(struct btc_coexist *btc)
+{
+	struct  btc_bt_link_info *bt_link_info = &btc->bt_link_info;
+
+	halbtc8821c2ant_set_wl_tx_power(btc, FC_EXCU, 0xd8);
+	halbtc8821c2ant_set_bt_tx_power(btc, NM_EXCU, 0);
+
+	halbtc8821c2ant_table(btc, NM_EXCU, 8);
+
+	if (bt_link_info->pan_exist)
+		halbtc8821c2ant_tdma(btc, NM_EXCU, TRUE, 22);
+	else if (bt_link_info->a2dp_exist)
+		halbtc8821c2ant_tdma(btc, NM_EXCU, TRUE, 16);
+	else
+		halbtc8821c2ant_tdma(btc, NM_EXCU, TRUE, 21);
+}
+
+static
+void halbtc8821c2ant_action_wifi_not_connected(struct btc_coexist *btc)
+{
+	halbtc8821c2ant_set_wl_tx_power(btc, NM_EXCU, 0xd8);
+	halbtc8821c2ant_set_bt_tx_power(btc, NM_EXCU, 0);
+
+	halbtc8821c2ant_table(btc, NM_EXCU, 0);
+	halbtc8821c2ant_tdma(btc, NM_EXCU, FALSE, 0);
+}
+
+static
+void halbtc8821c2ant_action_wifi_connected(struct btc_coexist *btc)
+{
+	struct coex_sta_8821c_2ant *coex_sta = &btc->coex_sta_8821c_2ant;
+	struct coex_dm_8821c_2ant *coex_dm = &btc->coex_dm_8821c_2ant;
+	u8 algorithm = 0;
+	struct  btc_bt_link_info *bt_link_info = &btc->bt_link_info;
+
+	algorithm = halbtc8821c2ant_action_algorithm(btc);
+
+	switch (algorithm) {
+
+	case BT_8821C_2ANT_COEX_SCO:
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], Action 2-Ant, algorithm = SCO.\n");
+		BTC_TRACE(trace_buf);
+		halbtc8821c2ant_action_sco(btc);
+		break;
+	case BT_8821C_2ANT_COEX_HID:
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], Action 2-Ant, algorithm = HID.\n");
+		BTC_TRACE(trace_buf);
+		halbtc8821c2ant_action_hid(btc);
+		break;
+	case BT_8821C_2ANT_COEX_A2DP:
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], Action 2-Ant, algorithm = A2DP.\n");
+		BTC_TRACE(trace_buf);
+
+		/* for A2DP + OPP test but BTinfo is
+		 * A2DP only in Lenovo test case
+		 */
+		if (coex_sta->is_bt_multi_link && coex_sta->hid_pair_cnt == 0)
+			halbtc8821c2ant_action_pan_a2dp(btc);
+		else
+			halbtc8821c2ant_action_a2dp(btc);
+		break;
+	case BT_8821C_2ANT_COEX_A2DPSINK:
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], Action 2-Ant, algorithm = A2DP Sink.\n");
+		BTC_TRACE(trace_buf);
+		halbtc8821c2ant_action_a2dpsink(btc);
+		break;
+	case BT_8821C_2ANT_COEX_A2DP_PANHS:
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], Action 2-Ant, algorithm = A2DP+PAN(HS).\n");
+		BTC_TRACE(trace_buf);
+		halbtc8821c2ant_action_a2dp_pan_hs(btc);
+		break;
+	case BT_8821C_2ANT_COEX_PAN:
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], Action 2-Ant, algorithm = PAN(EDR).\n");
+		BTC_TRACE(trace_buf);
+		halbtc8821c2ant_action_pan(btc);
+		break;
+	case BT_8821C_2ANT_COEX_PAN_A2DP:
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], Action 2-Ant, algorithm = PAN+A2DP.\n");
+		BTC_TRACE(trace_buf);
+		halbtc8821c2ant_action_pan_a2dp(btc);
+		break;
+	case BT_8821C_2ANT_COEX_PAN_HID:
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], Action 2-Ant, algorithm = PAN(EDR)+HID.\n");
+		BTC_TRACE(trace_buf);
+		halbtc8821c2ant_action_pan_hid(btc);
+		break;
+	case BT_8821C_2ANT_COEX_HID_A2DP_PAN:
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], Action 2-Ant, algorithm = HID+A2DP+PAN.\n");
+		BTC_TRACE(trace_buf);
+		halbtc8821c2ant_action_hid_a2dp_pan(btc);
+		break;
+	case BT_8821C_2ANT_COEX_HID_A2DP:
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], Action 2-Ant, algorithm = HID+A2DP.\n");
+		BTC_TRACE(trace_buf);
+		halbtc8821c2ant_action_hid_a2dp(btc);
+		break;
+	case BT_8821C_2ANT_COEX_NOPROFILEBUSY:
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], Action 2-Ant, algorithm = No-Profile busy.\n");
+		BTC_TRACE(trace_buf);
+		halbtc8821c2ant_action_bt_idle(btc);
+		break;
+	default:
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], Action 2-Ant, algorithm = coexist All Off!!\n");
+		BTC_TRACE(trace_buf);
+		halbtc8821c2ant_action_coex_all_off(btc);
+		break;
+	}
+
+	coex_dm->cur_algorithm = algorithm;
+}
+
+static
+void halbtc8821c2ant_action_wifi_multiport25g(struct btc_coexist *btc)
+{
+	struct coex_sta_8821c_2ant *coex_sta = &btc->coex_sta_8821c_2ant;
+	struct  btc_bt_link_info *bt_link_info = &btc->bt_link_info;
+
+	halbtc8821c2ant_set_wl_tx_power(btc, NM_EXCU, 0xd8);
+	halbtc8821c2ant_set_bt_tx_power(btc, NM_EXCU, 0);
+
+	halbtc8821c2ant_write_scbd(btc, BT_8821C_2ANT_SCBD_BTCQDDR, TRUE);
+
+	if (coex_sta->is_setup_link || coex_sta->bt_relink_downcount != 0) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], wifi_multiport25g(), BT Relink!!\n");
+		BTC_TRACE(trace_buf);
+
+		halbtc8821c2ant_table(btc, NM_EXCU, 0);
+		halbtc8821c2ant_tdma(btc, NM_EXCU, FALSE, 0);
+	} else if (coex_sta->c2h_bt_inquiry_page) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], wifi_multiport25g(), BT Inq-Page!!\n");
+		BTC_TRACE(trace_buf);
+
+		halbtc8821c2ant_table(btc, NM_EXCU, 11);
+		halbtc8821c2ant_tdma(btc, NM_EXCU, FALSE, 0);
+	} else {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], wifi_multiport25g(), BT idle or busy!!\n");
+		BTC_TRACE(trace_buf);
+
+		halbtc8821c2ant_table(btc, NM_EXCU, 11);
+		halbtc8821c2ant_tdma(btc, NM_EXCU, FALSE, 0);
+	}
+}
+
+static
+void halbtc8821c2ant_action_wifi_multiport2g(struct btc_coexist *btc)
+{
+	struct coex_sta_8821c_2ant *coex_sta = &btc->coex_sta_8821c_2ant;
+	struct  btc_bt_link_info *bt_link_info = &btc->bt_link_info;
+	struct btc_multi_port_tdma_info multiport_tdma_para;
+	u32 traffic_dir;
+
+	btc->btc_get(btc, BTC_GET_U4_WIFI_TRAFFIC_DIRECTION, &traffic_dir);
+
+	halbtc8821c2ant_set_wl_tx_power(btc, NM_EXCU, 0xd8);
+	halbtc8821c2ant_set_bt_tx_power(btc, NM_EXCU, 0);
+
+	halbtc8821c2ant_write_scbd(btc, BT_8821C_2ANT_SCBD_BTCQDDR, TRUE);
+
+	if (coex_sta->is_setup_link || coex_sta->bt_relink_downcount != 0) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], wifi_multiport2g, BT Relink!!\n");
+		BTC_TRACE(trace_buf);
+
+		halbtc8821c2ant_table(btc, NM_EXCU, 0);
+		halbtc8821c2ant_tdma(btc, NM_EXCU, FALSE, 0);
+	} else if (coex_sta->c2h_bt_inquiry_page) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], wifi_multiport2g, BT Inq-Page!!\n");
+		BTC_TRACE(trace_buf);
+
+		halbtc8821c2ant_table(btc, NM_EXCU, 0);
+		halbtc8821c2ant_tdma(btc, NM_EXCU, FALSE, 0);
+	} else if (coex_sta->num_of_profile == 0) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], wifi_multiport2g, BT idle!!\n");
+		BTC_TRACE(trace_buf);
+
+		/* for P2P-GO only A2DP sink */
+		if (btc->wifi_link_info.link_mode == BTC_LINK_ONLY_GO &&
+		    traffic_dir == BTC_WIFI_TRAFFIC_RX) {
+			halbtc8821c2ant_table(btc, NM_EXCU, 15);
+			halbtc8821c2ant_tdma(btc, NM_EXCU, TRUE, 11);
+		} else {
+			halbtc8821c2ant_table(btc, NM_EXCU, 5);
+			halbtc8821c2ant_tdma(btc, NM_EXCU, FALSE, 0);
+		}
+	} else if (coex_sta->is_wifi_linkscan_process) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], wifi_multiport2g, WL scan!!\n");
+		BTC_TRACE(trace_buf);
+
+		halbtc8821c2ant_action_wifi_linkscan(btc);
+	} else {
+		if (!coex_sta->is_bt_multi_link &&
+		    (bt_link_info->sco_exist || bt_link_info->hid_exist ||
+		     coex_sta->is_hid_rcu)) {
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				    "[BTCoex], wifi_multiport2g, 2G multi-port + BT HID/HFP/RCU!!\n");
+			BTC_TRACE(trace_buf);
+
+			halbtc8821c2ant_table(btc, NM_EXCU, 5);
+			halbtc8821c2ant_tdma(btc, NM_EXCU, FALSE, 0);
+		} else {
+			switch (btc->wifi_link_info.link_mode) {
+			#if 0
+			case BTC_LINK_2G_SCC_GO_STA:
+				BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+					    "[BTCoex], wifi_multiport2g, 2G_SCC_GO_STA + BT busy!!\n");
+				BTC_TRACE(trace_buf);
+
+				halbtc8821c2ant_table(btc, NM_EXCU, 0);
+				halbtc8821c2ant_tdma(btc, NM_EXCU, FALSE, 0);
+				break;
+			case BTC_LINK_ONLY_GO:
+				BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+					    "[BTCoex], wifi_singleport2g, Only_P2PGO with client-join + BT busy!!\n");
+				BTC_TRACE(trace_buf);
+
+				halbtc8821c2ant_table(btc, NM_EXCU, 0);
+				halbtc8821c2ant_tdma(btc, NM_EXCU, FALSE, 0);
+				break;
+			#endif
+			default:
+				BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+					    "[BTCoex], wifi_multiport2g, Other multi-port + BT busy!!\n");
+				BTC_TRACE(trace_buf);
+
+				halbtc8821c2ant_table(btc, NM_EXCU, 0);
+				halbtc8821c2ant_tdma(btc, NM_EXCU, FALSE, 0);
+				break;
+			}
+		}
+	}
+}
+
+static
+void halbtc8821c2ant_run_coex(struct btc_coexist *btc,  u8 reason)
+{
+	struct coex_sta_8821c_2ant *coex_sta = &btc->coex_sta_8821c_2ant;
+	struct coex_dm_8821c_2ant *coex_dm = &btc->coex_dm_8821c_2ant;
+	struct wifi_link_info_8821c_2ant *wifi_link_info_ext =
+					 &btc->wifi_link_info_8821c_2ant;
+	boolean wifi_connected = FALSE, wifi_32k = FALSE;
+	boolean scan = FALSE, link = FALSE, roam = FALSE, under_4way = FALSE;
+
+	btc->btc_get(btc, BTC_GET_BL_WIFI_SCAN, &scan);
+	btc->btc_get(btc, BTC_GET_BL_WIFI_LINK, &link);
+	btc->btc_get(btc, BTC_GET_BL_WIFI_ROAM, &roam);
+	btc->btc_get(btc, BTC_GET_BL_WIFI_4_WAY_PROGRESS, &under_4way);
+	btc->btc_get(btc, BTC_GET_BL_WIFI_CONNECTED, &wifi_connected);
+	btc->btc_get(btc, BTC_GET_BL_WIFI_LW_PWR_STATE, &wifi_32k);
+
+	if (scan || link || roam || under_4way ||
+	    reason == BT_8821C_2ANT_RSN_2GSCANSTART ||
+	    reason == BT_8821C_2ANT_RSN_2GSWITCHBAND ||
+	    reason == BT_8821C_2ANT_RSN_2GCONSTART ||
+	    reason == BT_8821C_2ANT_RSN_2GSPECIALPKT) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], scan = %d, link = %d, roam = %d 4way = %d!!!\n",
+			    scan, link, roam, under_4way);
+		BTC_TRACE(trace_buf);
+		coex_sta->is_wifi_linkscan_process = TRUE;
+	} else {
+		coex_sta->is_wifi_linkscan_process = FALSE;
+	}
+
+	/* update wifi_link_info_ext variable */
+	halbtc8821c2ant_update_wifi_link_info(btc, reason);
+
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+		    "[BTCoex], RunCoexistMechanism()===> reason = %d\n",
+		    reason);
+	BTC_TRACE(trace_buf);
+
+	if (btc->manual_control) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], RunCoexistMechanism(), return for Manual CTRL <===\n");
+		BTC_TRACE(trace_buf);
+		return;
+	}
+
+	if (btc->stop_coex_dm) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			   "[BTCoex], RunCoexistMechanism(), return for Stop Coex DM <===\n");
+		BTC_TRACE(trace_buf);
+		return;
+	}
+
+	if (coex_sta->under_ips) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], RunCoexistMechanism(), return for wifi is under IPS !!!\n");
+		BTC_TRACE(trace_buf);
+		return;
+	}
+
+	if (coex_sta->under_lps && wifi_32k) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], RunCoexistMechanism(), return for wifi is under LPS-32K !!!\n");
+		BTC_TRACE(trace_buf);
+		return;
+	}
+
+	if (!coex_sta->run_time_state) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], return for run_time_state = FALSE !!!\n");
+		BTC_TRACE(trace_buf);
+		return;
+	}
+
+	if (coex_sta->freeze_coexrun_by_btinfo && !coex_sta->is_setup_link) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], return for freeze_coexrun_by_btinfo\n");
+		BTC_TRACE(trace_buf);
+		return;
+	}
+
+	coex_sta->coex_run_cnt++;
+
+	if (coex_sta->msft_mr_exist && wifi_connected) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], RunCoexistMechanism(), microsoft MR!!\n");
+		BTC_TRACE(trace_buf);
+
+		coex_sta->wl_coex_mode = BT_8821C_2ANT_WLINK_BTMR;
+		halbtc8821c2ant_action_bt_mr(btc);
+		return;
+	}
+
+	if (wifi_link_info_ext->is_all_under_5g) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], WiFi is under 5G!!!\n");
+		BTC_TRACE(trace_buf);
+
+		coex_sta->wl_coex_mode = BT_8821C_2ANT_WLINK_5G;
+		halbtc8821c2ant_action_wifi_under5g(btc);
+		return;
+	}
+
+	if (wifi_link_info_ext->is_mcc_25g) { /* not iclude scan action */
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], WiFi is under mcc dual-band!!!\n");
+		BTC_TRACE(trace_buf);
+
+		coex_sta->wl_coex_mode = BT_8821C_2ANT_WLINK_25GMPORT;
+		halbtc8821c2ant_action_wifi_multiport25g(btc);
+		return;
+	}
+
+	if (wifi_link_info_ext->num_of_active_port > 1 ||
+	    (btc->wifi_link_info.link_mode == BTC_LINK_ONLY_GO &&
+	    !btc->wifi_link_info.bhotspot &&
+	    btc->wifi_link_info.bany_client_join_go)) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], WiFi is under scc-2g/mcc-2g/p2pGO-only!!!\n");
+		BTC_TRACE(trace_buf);
+
+		if (btc->wifi_link_info.link_mode ==
+							BTC_LINK_ONLY_GO)
+			coex_sta->wl_coex_mode = BT_8821C_2ANT_WLINK_2GGO;
+		else
+			coex_sta->wl_coex_mode = BT_8821C_2ANT_WLINK_2GMPORT;
+		halbtc8821c2ant_action_wifi_multiport2g(btc);
+		return;
+	}
+
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+		    "[BTCoex], WiFi is single-port 2G!!!\n");
+	BTC_TRACE(trace_buf);
+
+	coex_sta->wl_coex_mode = BT_8821C_2ANT_WLINK_2G1PORT;
+
+	halbtc8821c2ant_set_ant_path(btc, BTC_ANT_PATH_AUTO, NM_EXCU,
+				     BT_8821C_2ANT_PHASE_2G);
+
+	halbtc8821c2ant_write_scbd(btc, BT_8821C_2ANT_SCBD_BTCQDDR, TRUE);
+
+	if (coex_sta->bt_disabled) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], BT is disabled !!!\n");
+		BTC_TRACE(trace_buf);
+		halbtc8821c2ant_action_coex_all_off(btc);
+		return;
+	}
+
+	if (coex_sta->under_lps && !coex_sta->force_lps_ctrl &&
+	    !coex_sta->acl_busy) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], RunCoexistMechanism(), wifi is under LPS !!!\n");
+		BTC_TRACE(trace_buf);
+		halbtc8821c2ant_action_wifi_native_lps(btc);
+		return;
+	}
+
+	if (coex_sta->bt_whck_test) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], BT is under WHCK TEST!!!\n");
+		BTC_TRACE(trace_buf);
+		halbtc8821c2ant_action_bt_whql_test(btc);
+		return;
+	}
+
+	if (coex_sta->is_setup_link || coex_sta->bt_relink_downcount != 0) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], BT is re-link !!!\n");
+		BTC_TRACE(trace_buf);
+		halbtc8821c2ant_action_bt_relink(btc);
+		return;
+	}
+
+	if (coex_sta->c2h_bt_inquiry_page) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], BT is under inquiry/page scan !!\n");
+		BTC_TRACE(trace_buf);
+		halbtc8821c2ant_action_bt_inquiry(btc);
+		return;
+	}
+
+	if (coex_dm->bt_status == BT_8821C_2ANT_BSTATUS_NCON_IDLE ||
+	    coex_dm->bt_status == BT_8821C_2ANT_BSTATUS_CON_IDLE) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "############# [BTCoex],  BT Is idle\n");
+		BTC_TRACE(trace_buf);
+		halbtc8821c2ant_action_bt_idle(btc);
+		return;
+	}
+
+	if (coex_sta->is_wifi_linkscan_process) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], wifi is under linkscan process!!\n");
+		BTC_TRACE(trace_buf);
+		halbtc8821c2ant_action_wifi_linkscan(btc);
+		return;
+	}
+
+	if (wifi_connected) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], wifi is under connected!!\n");
+		BTC_TRACE(trace_buf);
+
+		halbtc8821c2ant_action_wifi_connected(btc);
+	} else {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], wifi is under not-connected!!\n");
+		BTC_TRACE(trace_buf);
+
+		halbtc8821c2ant_action_wifi_not_connected(btc);
+	}
+}
+
+static
+void halbtc8821c2ant_init_coex_dm(struct btc_coexist *btc)
+{
+	struct coex_sta_8821c_2ant *coex_sta = &btc->coex_sta_8821c_2ant;
+	struct coex_dm_8821c_2ant *coex_dm = &btc->coex_dm_8821c_2ant;
+
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+		    "[BTCoex], Coex Mechanism Init!!\n");
+	BTC_TRACE(trace_buf);
+
+	halbtc8821c2ant_low_penalty_ra(btc, NM_EXCU, FALSE, 0);
+
+	halbtc8821c2ant_set_wl_tx_power(btc, NM_EXCU, 0xd8);
+	halbtc8821c2ant_set_bt_tx_power(btc, NM_EXCU, 0);
+
+	coex_sta->pop_event_cnt = 0;
+	coex_sta->cnt_remote_name_req = 0;
+	coex_sta->cnt_reinit = 0;
+	coex_sta->cnt_setup_link = 0;
+	coex_sta->cnt_ign_wlan_act = 0;
+	coex_sta->cnt_page = 0;
+	coex_sta->cnt_role_switch = 0;
+	coex_sta->switch_band_notify_to = BTC_NOT_SWITCH;
+	coex_dm->setting_tdma = FALSE;
+
+	halbtc8821c2ant_table(btc, NM_EXCU, 0);
+
+	/* fw all off */
+	halbtc8821c2ant_tdma(btc, NM_EXCU, FALSE, 0);
+
+	halbtc8821c2ant_query_bt_info(btc);
+}
+
+static
+void halbtc8821c2ant_init_hw_config(struct btc_coexist *btc, boolean wifi_only)
+{
+	struct coex_sta_8821c_2ant *coex_sta = &btc->coex_sta_8821c_2ant;
+	u8 u8tmp = 0;
+	u32 vendor;
+	u32 u32tmp0 = 0, u32tmp1 = 0, u32tmp2 = 0, u32tmp3 = 0;
+	u8 i;
+
+	u32tmp3 = btc->btc_read_4byte(btc, 0xcb4);
+	u32tmp1 = halbtc8821c2ant_read_indirect_reg(btc, 0x38);
+	u32tmp2 = halbtc8821c2ant_read_indirect_reg(btc, 0x54);
+
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+		    "[BTCoex], (Before Init HW config) 0xcb4 = 0x%x, 0x38= 0x%x, 0x54= 0x%x\n",
+		    u32tmp3, u32tmp1, u32tmp2);
+	BTC_TRACE(trace_buf);;
+
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+		    "[BTCoex], 2Ant Init HW Config!!\n");
+	BTC_TRACE(trace_buf);
+
+#if 0
+	coex_sta->bt_coex_supported_feature = 0;
+	coex_sta->bt_coex_supported_version = 0;
+	coex_sta->bt_ble_scan_type = 0;
+	coex_sta->bt_ble_scan_para[0] = 0;
+	coex_sta->bt_ble_scan_para[1] = 0;
+	coex_sta->bt_ble_scan_para[2] = 0;
+#endif
+	coex_sta->bt_reg_vendor_ac = 0xffff;
+	coex_sta->bt_reg_vendor_ae = 0xffff;
+	coex_sta->isolation_btween_wb = BT_8821C_2ANT_DEFAULT_ISOLATION;
+	coex_sta->gnt_error_cnt = 0;
+	coex_sta->bt_relink_downcount = 0;
+	coex_sta->is_set_ps_state_fail = FALSE;
+	coex_sta->cnt_set_ps_state_fail = 0;
+	coex_sta->wl_rx_rate = BTC_UNKNOWN;
+	coex_sta->coex_run_cnt = 0;
+
+	for (i = 0; i <= 9; i++)
+		coex_sta->bt_afh_map[i] = 0;
+
+	/* 0xf0[15:12] --> Chip Cut information */
+	coex_sta->cut_version = (btc->btc_read_1byte(btc, 0xf1) & 0xf0) >> 4;
+
+	coex_sta->dis_ver_info_cnt = 0;
+
+#if 0  /* HW antenna diversity for test */
+	halbtc8821c2ant_set_antdiv_hwsw(btc, NM_EXCU, TRUE);
+#endif
+
+	halbtc8821c2ant_coex_switch_thres(btc, coex_sta->isolation_btween_wb);
+	 /* enable TBTT nterrupt */
+	btc->btc_write_1byte_bitmask(btc, 0x550, 0x8, 0x1);
+
+	/* BT report packet sample rate	 */
+	btc->btc_write_1byte(btc, 0x790, 0x5);
+
+	/* Init 0x778 = 0x1 for 2-Ant */
+	btc->btc_write_1byte(btc, 0x778, 0x1);
+
+	/* Enable PTA (3-wire function form BT side) */
+	btc->btc_write_1byte_bitmask(btc, 0x40, 0x20, 0x1);
+	btc->btc_write_1byte_bitmask(btc, 0x41, 0x02, 0x1);
+
+	/* Enable PTA (tx/rx signal form WiFi side) */
+	btc->btc_write_1byte_bitmask(btc, 0x4c6, 0x10, 0x1);
+
+	/* set GNT_BT=1 for coex table select both */
+	btc->btc_write_1byte_bitmask(btc, 0x763, 0x10, 0x1);
+
+	halbtc8821c2ant_enable_gnt_to_gpio(btc, TRUE);
+
+#if 0
+	/* check if WL firmware download ok */
+	/*if (btc->btc_read_1byte(btc, 0x80) == 0xc6)*/
+	halbtc8821c2ant_write_scbd(btc, BT_8821C_2ANT_SCBD_ONOFF, TRUE);
+#endif
+
+	/* Enable counter statistics */
+	/* 0x76e[3] =1, WLAN_Act control by PTA */
+	btc->btc_write_1byte(btc, 0x76e, 0x4);
+
+	/* WLAN_Tx by GNT_WL  0x950[29] = 0 */
+	/* btc->btc_write_1byte_bitmask(btc, 0x953, 0x20, 0x0); */
+
+	if (coex_sta->is_rf_state_off) {
+		halbtc8821c2ant_set_ant_path(btc, BTC_ANT_PATH_AUTO, FC_EXCU,
+					     BT_8821C_2ANT_PHASE_WOFF);
+
+		btc->stop_coex_dm = TRUE;
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], **********  %s (RF Off)\n", __func__);
+		BTC_TRACE(trace_buf);
+	} else if (wifi_only) {
+		coex_sta->concurrent_rx_mode_on = FALSE;
+		/* Path config	 */
+		/* Set Antenna Path */
+		halbtc8821c2ant_set_ant_path(btc, BTC_ANT_PATH_AUTO, FC_EXCU,
+					     BT_8821C_2ANT_PHASE_WONLY);
+		btc->stop_coex_dm = TRUE;
+	} else {
+		/* Set BT polluted packet on for Tx rate adaptive not
+		 * including Tx retry break by PTA, 0x45c[19] =1
+		 */
+		btc->btc_write_1byte_bitmask(btc, 0x45e, 0x8, 0x1);
+
+		coex_sta->concurrent_rx_mode_on = TRUE;
+		/* btc->btc_write_1byte_bitmask(btc, 0x953, 0x2, 0x1); */
+
+		/* RF 0x1[1] = 0->Set GNT_WL_RF_Rx always = 1
+		 * for con-current Rx, mask Tx only
+		 */
+		btc->btc_set_rf_reg(btc, BTC_RF_A, 0x1, 0x2, 0x0);
+
+		/* Set Antenna Path */
+		halbtc8821c2ant_set_ant_path(btc, BTC_ANT_PATH_AUTO, FC_EXCU,
+					     BT_8821C_2ANT_PHASE_INIT);
+
+		btc->stop_coex_dm = FALSE;
+	}
+	halbtc8821c2ant_table(btc, FC_EXCU, 0);
+	halbtc8821c2ant_tdma(btc, FC_EXCU, FALSE, 0);
+}
+
+/* ************************************************************
+ * work around function start with wa_halbtc8821c2ant_
+ * ************************************************************
+ * ************************************************************
+ * extern function start with ex_halbtc8821c2ant_
+ * ************************************************************ */
+void ex_halbtc8821c2ant_power_on_setting(struct btc_coexist *btc)
+{
+	struct coex_sta_8821c_2ant *coex_sta = &btc->coex_sta_8821c_2ant;
+	struct  btc_board_info *board_info = &btc->board_info;
+	u8 u8tmp = 0x0;
+	u16 u16tmp = 0x0;
+
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+		    "[BTCoex], Execute %s !!\n", __func__);
+	BTC_TRACE(trace_buf);
+
+	btc->stop_coex_dm = TRUE;
+	coex_sta->is_rf_state_off = FALSE;
+
+	/* enable BB, REG_SYS_FUNC_EN such that
+	 * we can write BB Register correctly.
+	 */
+	u16tmp = btc->btc_read_2byte(btc, 0x2);
+	btc->btc_write_2byte(btc, 0x2, u16tmp | BIT(0) | BIT(1));
+
+	/* Local setting bit define
+	 *	BIT0: "0" for no antenna inverse; "1" for antenna inverse
+	 *	BIT1: "0" for internal switch; "1" for external switch
+	 *	BIT2: "0" for one antenna; "1" for two antenna
+	 * NOTE: here default all internal switch and 1-antenna
+	 * ==> BIT1=0 and BIT2=0
+	 */
+
+	/* Check efuse 0xc3[6] for Single Antenna Path */
+	if (board_info->single_ant_path == 0) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], Single Antenna, Antenna at Aux Port\n");
+		BTC_TRACE(trace_buf);
+
+		board_info->btdm_ant_pos = BTC_ANTENNA_AT_AUX_PORT;
+		u8tmp = 7;
+	} else if (board_info->single_ant_path == 1) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], Single Antenna, Antenna at Main Port\n");
+		BTC_TRACE(trace_buf);
+
+		board_info->btdm_ant_pos = BTC_ANTENNA_AT_MAIN_PORT;
+		u8tmp = 6;
+	}
+
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+		    "[BTCoex], (Power On) single_ant_path  = %d, btdm_ant_pos = %d\n",
+		    board_info->single_ant_path , board_info->btdm_ant_pos);
+	BTC_TRACE(trace_buf);
+
+	/* Setup RF front end type */
+	halbtc8821c2ant_set_rfe_type(btc);
+
+	/* Set Antenna Path to BT side */
+	halbtc8821c2ant_set_ant_path(btc, BTC_ANT_PATH_AUTO, FC_EXCU,
+				     BT_8821C_2ANT_PHASE_POWERON);
+
+	/* Save"single antenna position" info in Local register setting
+	 * for FW reading, because FW may not ready at  power on
+	 */
+	if (btc->chip_interface == BTC_INTF_PCI)
+		btc->btc_write_local_reg_1byte(btc, 0x3e0, u8tmp);
+	else if (btc->chip_interface == BTC_INTF_USB)
+		btc->btc_write_local_reg_1byte(btc, 0xfe08, u8tmp);
+	else if (btc->chip_interface == BTC_INTF_SDIO)
+		btc->btc_write_local_reg_1byte(btc, 0x60, u8tmp);
+
+	/* enable GNT_WL/GNT_BT debug signal to GPIO14/15 */
+	halbtc8821c2ant_enable_gnt_to_gpio(btc, TRUE);
+
+	if (btc->dbg_mode) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], LTE coex Reg 0x38 (Power-On) = 0x%x\n",
+			    halbtc8821c2ant_read_indirect_reg(btc, 0x38));
+		BTC_TRACE(trace_buf);
+
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], MACReg 0x70/ BBReg 0xcb4 (Power-On) = 0x%x/ 0x%x\n",
+			    btc->btc_read_4byte(btc, 0x70),
+			    btc->btc_read_4byte(btc, 0xcb4));
+		BTC_TRACE(trace_buf);
+	}
+}
+
+void ex_halbtc8821c2ant_pre_load_firmware(struct btc_coexist *btc)
+{
+	struct  btc_board_info	*board_info = &btc->board_info;
+	u8 u8tmp = 0x4; /* Set BIT2 by default since it's 2ant case */
+
+	/* S0 or S1 setting and Local register setting
+	 *(By the setting fw can get ant number, S0/S1, ... info)
+	 * Local setting bit define
+	 *	BIT0: "0" for no antenna inverse; "1" for antenna inverse
+	 *	BIT1: "0" for internal switch; "1" for external switch
+	 *	BIT2: "0" for one antenna; "1" for two antenna
+	 * NOTE: here default all internal switch
+	 * and 1-antenna ==> BIT1=0 and BIT2=0
+	 */
+	if (btc->chip_interface == BTC_INTF_USB) {
+		/* fixed at S0 for USB interface */
+		u8tmp |= 0x1;	/* antenna inverse */
+		btc->btc_write_local_reg_1byte(btc, 0xfe08, u8tmp);
+	} else {
+		/* for PCIE and SDIO interface, we check efuse 0xc3[6] */
+		if (board_info->single_ant_path == 0) {
+		} else if (board_info->single_ant_path == 1) {
+			/* set to S0 */
+			u8tmp |= 0x1;	/* antenna inverse */
+		}
+
+		if (btc->chip_interface == BTC_INTF_PCI)
+			btc->btc_write_local_reg_1byte(btc, 0x3e0, u8tmp);
+		else if (btc->chip_interface == BTC_INTF_SDIO)
+			btc->btc_write_local_reg_1byte(btc, 0x60, u8tmp);
+	}
+}
+
+
+void ex_halbtc8821c2ant_init_hw_config(struct btc_coexist *btc,
+				       boolean wifi_only)
+{
+	halbtc8821c2ant_init_hw_config(btc, wifi_only);
+}
+
+void ex_halbtc8821c2ant_init_coex_dm(struct btc_coexist *btc)
+{
+	btc->stop_coex_dm = FALSE;
+	btc->auto_report = TRUE;
+	btc->dbg_mode = FALSE;
+	halbtc8821c2ant_init_coex_dm(btc);
+}
+
+void ex_halbtc8821c2ant_display_simple_coex_info(struct btc_coexist *btc)
+{
+	struct coex_sta_8821c_2ant *coex_sta = &btc->coex_sta_8821c_2ant;
+	struct coex_dm_8821c_2ant *coex_dm = &btc->coex_dm_8821c_2ant;
+	struct btc_board_info *board_info   = &btc->board_info;
+	struct btc_bt_link_info	*bt_link_info = &btc->bt_link_info;
+
+	u8 *cli_buf = btc->cli_buf;
+	u32 bt_patch_ver = 0, bt_coex_ver = 0;
+	static u8	cnt;
+	u8 * const p = &coex_sta->bt_afh_map[0];
+
+	if (!coex_sta->bt_disabled &&
+	    (coex_sta->bt_coex_supported_version == 0 ||
+	    coex_sta->bt_coex_supported_version == 0xffff) &&
+	    cnt == 0) {
+		btc->btc_get(btc, BTC_GET_U4_SUPPORTED_FEATURE,
+			     &coex_sta->bt_coex_supported_feature);
+
+		btc->btc_get(btc, BTC_GET_U4_SUPPORTED_VERSION,
+			     &coex_sta->bt_coex_supported_version);
+
+		coex_sta->bt_reg_vendor_ac = (u16)(btc->btc_get_bt_reg(btc, 3,
+								       0xac) &
+						   0xffff);
+
+		coex_sta->bt_reg_vendor_ae = (u16)(btc->btc_get_bt_reg(btc, 3,
+								       0xae) &
+						   0xffff);
+
+		btc->btc_get(btc, BTC_GET_U4_BT_PATCH_VER, &bt_patch_ver);
+		btc->bt_info.bt_get_fw_ver = bt_patch_ver;
+
+		if (coex_sta->num_of_profile > 0)
+			btc->btc_get_bt_afh_map_from_bt(btc, 0, p);
+	}
+
+	if (++cnt >= 3)
+		cnt = 0;
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+		   "\r\n _____[BT Coexist info]____");
+	CL_PRINTF(cli_buf);
+
+	if (btc->manual_control) {
+		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+			   "\r\n __[Under Manual Control]_");
+	CL_PRINTF(cli_buf);
+		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+			   "\r\n _________________________");
+		CL_PRINTF(cli_buf);
+	}
+
+	if (btc->stop_coex_dm) {
+		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+			   "\r\n ____[Coex is STOPPED]____");
+		CL_PRINTF(cli_buf);
+		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+			   "\r\n _________________________");
+		CL_PRINTF(cli_buf);
+	}
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+		   "\r\n %-35s = %d/ %d/ %s / 0x%x",
+		   "Ant PG Num/ Mech/ Pos/ RFE",
+		   board_info->pg_ant_num, board_info->btdm_ant_num,
+		   (board_info->btdm_ant_pos == BTC_ANTENNA_AT_MAIN_PORT
+		    ? "Main" : "Aux"),
+		   board_info->rfe_type);
+	CL_PRINTF(cli_buf);
+
+	bt_coex_ver = (coex_sta->bt_coex_supported_version & 0xff);
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+		   "\r\n %-35s = %d_%02x/ 0x%02x/ 0x%02x (%s)",
+		   "CoexVer WL/  BT_Desired/ BT_Report",
+		   glcoex_ver_date_8821c_2ant, glcoex_ver_8821c_2ant,
+		   glcoex_ver_btdesired_8821c_2ant,
+		   bt_coex_ver,
+		   (bt_coex_ver == 0xff ? "Unknown" :
+		   (coex_sta->bt_disabled ? "BT-disable" :
+		   (bt_coex_ver >= glcoex_ver_btdesired_8821c_2ant ?
+		   "Match" : "Mis-Match"))));
+	CL_PRINTF(cli_buf);
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s ", "BT status",
+		   ((coex_sta->bt_disabled) ? ("disabled") :
+		   ((coex_sta->c2h_bt_inquiry_page) ? ("inquiry/page")
+		    : ((BT_8821C_2ANT_BSTATUS_NCON_IDLE ==
+		    coex_dm->bt_status) ? "non-connected idle" :
+		    ((BT_8821C_2ANT_BSTATUS_CON_IDLE ==
+		    coex_dm->bt_status) ? "connected-idle" : "busy")))));
+	CL_PRINTF(cli_buf);
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d",
+		   "0x770(Hi-pri rx/tx)",
+		   coex_sta->high_priority_rx, coex_sta->high_priority_tx);
+	CL_PRINTF(cli_buf);
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d %s",
+		   "0x774(Lo-pri rx/tx)",
+		   coex_sta->low_priority_rx, coex_sta->low_priority_tx,
+		   (bt_link_info->slave_role ? "(Slave!!)" :
+		   (coex_sta->is_tdma_btautoslot_hang ?
+		   "(auto-slot hang!!)" : "")));
+	CL_PRINTF(cli_buf);
+}
+
+void ex_halbtc8821c2ant_display_coex_info(struct btc_coexist *btc)
+{
+	struct coex_sta_8821c_2ant *coex_sta = &btc->coex_sta_8821c_2ant;
+	struct coex_dm_8821c_2ant *coex_dm = &btc->coex_dm_8821c_2ant;
+	struct  btc_board_info *board_info = &btc->board_info;
+	struct  btc_bt_link_info *bt_link_info = &btc->bt_link_info;
+
+	u8 *cli_buf = btc->cli_buf;
+	u8 u8tmp[4], i, ps_tdma_case = 0;
+	u32 u32tmp[4];
+	u16 u16tmp[4];
+	u32 fa_ofdm, fa_cck, cca_ofdm, cca_cck;
+	u32 fw_ver = 0, bt_patch_ver = 0, bt_coex_ver = 0;
+	static u8 pop_report_in_10s;
+	u32 phyver = 0;
+	boolean lte_coex_on = FALSE;
+	static u8 cnt;
+	u32 ratio_crc, cnt_ok, cnt_err;
+	u8 * const p = &coex_sta->bt_afh_map[0];
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+		   "\r\n ============[BT Coexist info 8821C]============");
+	CL_PRINTF(cli_buf);
+
+	if (btc->manual_control) {
+		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+			   "\r\n ============[Under Manual Control]============");
+		CL_PRINTF(cli_buf);
+		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+			   "\r\n ==========================================");
+		CL_PRINTF(cli_buf);
+	} else if (btc->stop_coex_dm) {
+		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+			   "\r\n ============[Coex is STOPPED]============");
+		CL_PRINTF(cli_buf);
+		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+			   "\r\n ==========================================");
+		CL_PRINTF(cli_buf);
+	} else if (!coex_sta->run_time_state) {
+		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+			   "\r\n ============[Run Time State = False]============");
+		CL_PRINTF(cli_buf);
+		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+			   "\r\n ==========================================");
+		CL_PRINTF(cli_buf);
+	} else if (coex_sta->freeze_coexrun_by_btinfo) {
+		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+			   "\r\n ============[freeze_coexrun_by_btinfo]============");
+		CL_PRINTF(cli_buf);
+		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+			   "\r\n ==========================================");
+		CL_PRINTF(cli_buf);
+	}
+
+	if (!coex_sta->bt_disabled &&
+	    (coex_sta->bt_coex_supported_version == 0 ||
+	    coex_sta->bt_coex_supported_version == 0xffff) &&
+	    cnt == 0) {
+		btc->btc_get(btc, BTC_GET_U4_SUPPORTED_FEATURE,
+			     &coex_sta->bt_coex_supported_feature);
+
+		btc->btc_get(btc, BTC_GET_U4_SUPPORTED_VERSION,
+			     &coex_sta->bt_coex_supported_version);
+
+		coex_sta->bt_reg_vendor_ac = (u16)(btc->btc_get_bt_reg(btc, 3,
+								       0xac) &
+						   0xffff);
+
+		coex_sta->bt_reg_vendor_ae = (u16)(btc->btc_get_bt_reg(btc, 3,
+								       0xae) &
+						   0xffff);
+
+		btc->btc_get(btc, BTC_GET_U4_BT_PATCH_VER, &bt_patch_ver);
+		btc->bt_info.bt_get_fw_ver = bt_patch_ver;
+
+		if (coex_sta->num_of_profile > 0)
+			btc->btc_get_bt_afh_map_from_bt(btc, 0, p);
+	}
+
+	if (++cnt >= 3)
+		cnt = 0;
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+		   "\r\n %-35s = %d/ %s/ %s / 0x%x",
+		   "Ant PG Num/ Mech/ Pos/ RFE",
+		   board_info->pg_ant_num,
+		   (board_info->btdm_ant_num == 1 ? "Shared" : "Non-Shared"),
+		   (board_info->btdm_ant_pos == BTC_ANTENNA_AT_MAIN_PORT
+		    ? "Main" : "Aux"),
+		   board_info->rfe_type);
+	CL_PRINTF(cli_buf);
+
+	bt_patch_ver = btc->bt_info.bt_get_fw_ver;
+	btc->btc_get(btc, BTC_GET_U4_WIFI_FW_VER, &fw_ver);
+	phyver = btc->btc_get_bt_phydm_version(btc);
+	bt_coex_ver = (coex_sta->bt_coex_supported_version & 0xff);
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+		   "\r\n %-35s = %d_%02x/ 0x%02x/ 0x%02x (%s)",
+		   "CoexVer WL/  BT_Desired/ BT_Report",
+		   glcoex_ver_date_8821c_2ant, glcoex_ver_8821c_2ant,
+		   glcoex_ver_btdesired_8821c_2ant,
+		   bt_coex_ver,
+		   (bt_coex_ver == 0xff ? "Unknown" :
+		   (coex_sta->bt_disabled ? "BT-disable" :
+		   (bt_coex_ver >= glcoex_ver_btdesired_8821c_2ant ?
+		    "Match" : "Mis-Match"))));
+	CL_PRINTF(cli_buf);
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+		   "\r\n %-35s = 0x%x/ 0x%x/ v%d/ %c",
+		   "W_FW/ B_FW/ Phy/ Kt",
+		   fw_ver, bt_patch_ver, phyver,
+		   coex_sta->cut_version + 65);
+	CL_PRINTF(cli_buf);
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+		   "\r\n %-35s = %02x %02x %02x (RF-Ch = %d)",
+		   "AFH Map to BT",
+		   coex_dm->wifi_chnl_info[0], coex_dm->wifi_chnl_info[1],
+		   coex_dm->wifi_chnl_info[2], coex_sta->wl_center_channel);
+	CL_PRINTF(cli_buf);
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d / %d / %d ",
+		   "Isolation/WL_Thres/BT_Thres",
+		   coex_sta->isolation_btween_wb,
+		   coex_sta->wifi_coex_thres,
+		   coex_sta->bt_coex_thres);
+	CL_PRINTF(cli_buf);
+
+	/* wifi status */
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s",
+		   "============[Wifi Status]============");
+	CL_PRINTF(cli_buf);
+	btc->btc_disp_dbg_msg(btc, BTC_DBG_DISP_WIFI_STATUS);
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s",
+		   "============[BT Status]============");
+	CL_PRINTF(cli_buf);
+
+	pop_report_in_10s++;
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+		   "\r\n %-35s = %s/ %ddBm/ %d/ %d",
+		   "BT status/ rssi/ retryCnt/ popCnt",
+		   ((coex_sta->bt_disabled) ? ("disabled") :	((
+		    coex_sta->c2h_bt_inquiry_page) ? ("inquiry-page")
+		    : ((BT_8821C_2ANT_BSTATUS_NCON_IDLE ==
+			       coex_dm->bt_status) ? "non-connected-idle" :
+		   ((coex_dm->bt_status == BT_8821C_2ANT_BSTATUS_CON_IDLE)
+		   ? "connected-idle" : "busy")))),
+		   coex_sta->bt_rssi - 100, coex_sta->bt_retry_cnt,
+		   coex_sta->pop_event_cnt);
+	CL_PRINTF(cli_buf);
+
+	if (pop_report_in_10s >= 5) {
+		coex_sta->pop_event_cnt = 0;
+		pop_report_in_10s = 0;
+	}
+
+	if (coex_sta->num_of_profile != 0)
+		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+			    "\r\n %-35s = %s%s%s%s%s%s (multilink = %d)",
+			    "Profiles",
+			    ((bt_link_info->a2dp_exist) ?
+			    ((coex_sta->is_bt_a2dp_sink) ? "A2DP sink," :
+			    "A2DP,") : ""),
+			    ((bt_link_info->sco_exist) ?  "HFP," : ""),
+			    ((bt_link_info->hid_exist) ?
+			    ((coex_sta->is_hid_rcu) ? "HID(RCU)" :
+			    ((coex_sta->hid_busy_num >= 2) ? "HID(4/18)," :
+			    "HID(2/18),")) : ""),
+			    ((bt_link_info->pan_exist) ?
+			    ((coex_sta->is_bt_opp_exist) ? "OPP," : "PAN,") :
+			    ""),
+			    ((coex_sta->voice_over_HOGP) ? "Voice," : ""),
+			    ((coex_sta->msft_mr_exist) ? "MR" : ""),
+			    coex_sta->is_bt_multi_link);
+	else
+		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+			   "\r\n %-35s = %s", "Profiles",
+			   (coex_sta->msft_mr_exist) ? "MR" : "None");
+
+	CL_PRINTF(cli_buf);
+
+	if (bt_link_info->a2dp_exist) {
+		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s/ %d/ %s",
+			   "CQDDR/Bitpool/Auto_Slot",
+			   ((coex_sta->is_A2DP_3M) ? "On" : "Off"),
+			   coex_sta->a2dp_bit_pool,
+			   ((coex_sta->is_autoslot) ? "On" : "Off")
+			  );
+		CL_PRINTF(cli_buf);
+
+		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+			   "\r\n %-35s = 0x%x/ 0x%x/ %d/ %d",
+			   "V_ID/D_name/FBSlot_Legacy/FBSlot_Le",
+			   coex_sta->bt_a2dp_vendor_id,
+			   coex_sta->bt_a2dp_device_name,
+			   coex_sta->legacy_forbidden_slot,
+			   coex_sta->le_forbidden_slot
+			  );
+		CL_PRINTF(cli_buf);
+	}
+
+	if (bt_link_info->hid_exist) {
+		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d",
+			   "HID PairNum",
+			   coex_sta->hid_pair_cnt);
+		CL_PRINTF(cli_buf);
+	}
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s/ %d/ %s/ 0x%x",
+		    "Role/RoleSwCnt/IgnWlact/Feature",
+		    ((bt_link_info->slave_role) ? "Slave" : "Master"),
+		    coex_sta->cnt_role_switch,
+		    ((coex_dm->cur_ignore_wlan_act) ? "Yes" : "No"),
+		    coex_sta->bt_coex_supported_feature);
+	CL_PRINTF(cli_buf);
+
+	if (coex_sta->is_ble_scan_en) {
+		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+			   "\r\n %-35s = 0x%x/ 0x%x/ 0x%x/ 0x%x",
+			   "BLEScan Type/TV/Init/Ble",
+			   coex_sta->bt_ble_scan_type,
+			   (coex_sta->bt_ble_scan_type & 0x1 ?
+			   coex_sta->bt_ble_scan_para[0] : 0x0),
+			   (coex_sta->bt_ble_scan_type & 0x2 ?
+			   coex_sta->bt_ble_scan_para[1] : 0x0),
+			   (coex_sta->bt_ble_scan_type & 0x4 ?
+			   coex_sta->bt_ble_scan_para[2] : 0x0));
+		CL_PRINTF(cli_buf);
+	}
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+		   "\r\n %-35s = %d/ %d/ %d/ %d/ %d %s",
+		   "ReInit/ReLink/IgnWlact/Page/NameReq", coex_sta->cnt_reinit,
+		   coex_sta->cnt_setup_link, coex_sta->cnt_ign_wlan_act,
+		   coex_sta->cnt_page, coex_sta->cnt_remote_name_req,
+		   (coex_sta->is_setup_link ? "(Relink!!)" : ""));
+	CL_PRINTF(cli_buf);
+
+	halbtc8821c2ant_read_scbd(btc,	&u16tmp[0]);
+
+	if (coex_sta->bt_reg_vendor_ae == 0xffff ||
+	    coex_sta->bt_reg_vendor_ac == 0xffff)
+		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+			   "\r\n %-35s = x/ x/ 0x%04x",
+			   "0xae[4]/0xac[1:0]/ScBd(B->W)", u16tmp[0]);
+	else
+		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+			   "\r\n %-35s = 0x%x/ 0x%x/ 0x%04x",
+			   "0xae[4]/0xac[1:0]/ScBd(B->W)",
+			   (int)((coex_sta->bt_reg_vendor_ae & BIT(4)) >> 4),
+			   coex_sta->bt_reg_vendor_ac & 0x3, u16tmp[0]);
+	CL_PRINTF(cli_buf);
+
+	if (coex_sta->num_of_profile > 0) {
+		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+			   "\r\n %-35s = %02x%02x%02x%02x %02x%02x%02x%02x %02x%02x",
+			   "AFH MAP",
+			   coex_sta->bt_afh_map[0],
+			   coex_sta->bt_afh_map[1],
+			   coex_sta->bt_afh_map[2],
+			   coex_sta->bt_afh_map[3],
+			   coex_sta->bt_afh_map[4],
+			   coex_sta->bt_afh_map[5],
+			   coex_sta->bt_afh_map[6],
+			   coex_sta->bt_afh_map[7],
+			   coex_sta->bt_afh_map[8],
+			   coex_sta->bt_afh_map[9]);
+		CL_PRINTF(cli_buf);
+	}
+
+	for (i = 0; i < BT_8821C_2ANT_INFO_SRC_MAX; i++) {
+		if (coex_sta->bt_info_c2h_cnt[i]) {
+			CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+				   "\r\n %-35s = %02x %02x %02x %02x %02x %02x %02x (%d)",
+				   glbt_info_src_8821c_2ant[i],
+				   coex_sta->bt_info_c2h[i][0],
+				   coex_sta->bt_info_c2h[i][1],
+				   coex_sta->bt_info_c2h[i][2],
+				   coex_sta->bt_info_c2h[i][3],
+				   coex_sta->bt_info_c2h[i][4],
+				   coex_sta->bt_info_c2h[i][5],
+				   coex_sta->bt_info_c2h[i][6],
+				   coex_sta->bt_info_c2h_cnt[i]);
+			CL_PRINTF(cli_buf);
+		}
+	}
+
+	/* Sw mechanism	 */
+	if (btc->manual_control)
+		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s",
+			"============[mechanism] (before Manual)============");
+	else
+		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s",
+			   "============[Mechanism]============");
+
+	CL_PRINTF(cli_buf);
+
+	ps_tdma_case = coex_dm->cur_ps_tdma;
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+		   "\r\n %-35s = %02x %02x %02x %02x %02x (case-%d, %s)",
+		   "TDMA",
+		   coex_dm->ps_tdma_para[0], coex_dm->ps_tdma_para[1],
+		   coex_dm->ps_tdma_para[2], coex_dm->ps_tdma_para[3],
+		   coex_dm->ps_tdma_para[4], ps_tdma_case,
+		   (coex_dm->cur_ps_tdma_on ? "TDMA-On" : "TDMA-Off"));
+	CL_PRINTF(cli_buf);
+
+	switch (coex_sta->wl_coex_mode) {
+	case BT_8821C_2ANT_WLINK_2G1PORT:
+	default:
+		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+			   "\r\n %-35s = %s", "Coex_Mode", "2G-SP");
+		break;
+	case BT_8821C_2ANT_WLINK_2GMPORT:
+		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+			   "\r\n %-35s = %s", "Coex_Mode", "2G-MP");
+		break;
+	case BT_8821C_2ANT_WLINK_25GMPORT:
+		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+			   "\r\n %-35s = %s", "Coex_Mode", "25G-MP");
+		break;
+	case BT_8821C_2ANT_WLINK_5G:
+		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+			   "\r\n %-35s = %s", "Coex_Mode", "5G");
+		break;
+	case BT_8821C_2ANT_WLINK_2GGO:
+		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+			   "\r\n %-35s = %s", "Coex_Mode", "2G-P2P");
+		break;
+	case BT_8821C_2ANT_WLINK_BTMR:
+		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+			   "\r\n %-35s = %s", "Coex_Mode", "BT-MR");
+		break;
+	}
+	CL_PRINTF(cli_buf);
+
+	u32tmp[0] = btc->btc_read_4byte(btc, 0x6c0);
+	u32tmp[1] = btc->btc_read_4byte(btc, 0x6c4);
+	u32tmp[2] = btc->btc_read_4byte(btc, 0x6c8);
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+		   "\r\n %-35s = %d/ 0x%x/ 0x%x/ 0x%x",
+		   "Table/0x6c0/0x6c4/0x6c8",
+		   coex_sta->coex_table_type, u32tmp[0], u32tmp[1], u32tmp[2]);
+	CL_PRINTF(cli_buf);
+
+	u8tmp[0] = btc->btc_read_1byte(btc, 0x778);
+	u32tmp[0] = btc->btc_read_4byte(btc, 0x6cc);
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+		   "\r\n %-35s = 0x%x/ 0x%x/ 0x%04x/ %d",
+		   "0x778/0x6cc/ScBd(W->B)/RunCnt", u8tmp[0], u32tmp[0],
+		   coex_sta->score_board_WB, coex_sta->coex_run_cnt);
+	CL_PRINTF(cli_buf);
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s/ %s/ %s/ %d/ %d",
+		   "AntDiv/BtCtrlLPS/LPRA/PsFail/g_busy",
+		   ((board_info->ant_div_cfg) ?
+		   ((coex_dm->cur_antdiv_type) ? "On(Hw)" : "On(Sw)") : "Off"),
+		   ((coex_sta->force_lps_ctrl) ? "On" : "Off"),
+		   ((coex_dm->cur_low_penalty_ra) ? "On" : "Off"),
+		   coex_sta->cnt_set_ps_state_fail,
+		   coex_sta->gl_wifi_busy);
+	CL_PRINTF(cli_buf);
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x",
+		   "WL_Pwr/ BT_Pwr", coex_dm->cur_wl_pwr_lvl,
+		   coex_dm->cur_bt_pwr_lvl);
+	CL_PRINTF(cli_buf);
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d/ %d/ %d",
+		   "Null All/Retry/Ack/BT_Empty/BT_Late",
+		   coex_sta->wl_fw_dbg_info[1],
+		   coex_sta->wl_fw_dbg_info[2],
+		   coex_sta->wl_fw_dbg_info[3],
+		   coex_sta->wl_fw_dbg_info[4],
+		   coex_sta->wl_fw_dbg_info[5]);
+	CL_PRINTF(cli_buf);
+
+	u32tmp[0] = halbtc8821c2ant_read_indirect_reg(btc, 0x38);
+	lte_coex_on = ((u32tmp[0] & BIT(7)) >> 7) ?  TRUE : FALSE;
+
+	if (lte_coex_on) {
+
+		u32tmp[0] = halbtc8821c2ant_read_indirect_reg(btc, 0xa0);
+		u32tmp[1] = halbtc8821c2ant_read_indirect_reg(btc, 0xa4);
+		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x",
+			   "LTE Coex Table W_L/B_L", u32tmp[0] & 0xffff,
+			   u32tmp[1] & 0xffff);
+		CL_PRINTF(cli_buf);
+
+		u32tmp[0] = halbtc8821c2ant_read_indirect_reg(btc, 0xa8);
+		u32tmp[1] = halbtc8821c2ant_read_indirect_reg(btc, 0xac);
+		u32tmp[2] = halbtc8821c2ant_read_indirect_reg(btc, 0xb0);
+		u32tmp[3] = halbtc8821c2ant_read_indirect_reg(btc, 0xb4);
+		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+			   "\r\n %-35s = 0x%x/ 0x%x/ 0x%x/ 0x%x",
+			   "LTE Break Table W_L/B_L/L_W/L_B",
+			   u32tmp[0] & 0xffff, u32tmp[1] & 0xffff,
+			   u32tmp[2] & 0xffff, u32tmp[3] & 0xffff);
+		CL_PRINTF(cli_buf);
+	}
+
+	/* Hw setting		 */
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s",
+		   "============[Hw setting]============");
+	CL_PRINTF(cli_buf);
+
+	u32tmp[0] = halbtc8821c2ant_read_indirect_reg(btc, 0x38);
+	u32tmp[1] = halbtc8821c2ant_read_indirect_reg(btc, 0x54);
+	u8tmp[0] = btc->btc_read_1byte(btc, 0x73);
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s/ %s",
+		   "LTE Coex/Path Owner",
+		   ((lte_coex_on) ? "On" : "Off") ,
+		   ((u8tmp[0] & BIT(2)) ? "WL" : "BT"));
+	CL_PRINTF(cli_buf);
+
+	if (lte_coex_on) {
+		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+			   "\r\n %-35s = %d/ %d/ %d/ %d",
+			   "LTE 3Wire/OPMode/UART/UARTMode",
+			   (int)((u32tmp[0] & BIT(6)) >> 6),
+			   (int)((u32tmp[0] & (BIT(5) | BIT(4))) >> 4),
+			   (int)((u32tmp[0] & BIT(3)) >> 3),
+			   (int)(u32tmp[0] & (BIT(2) | BIT(1) | BIT(0))));
+		CL_PRINTF(cli_buf);
+
+		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d",
+			   "LTE_Busy/UART_Busy",
+			   (int)((u32tmp[1] & BIT(1)) >> 1),
+			   (int)(u32tmp[1] & BIT(0)));
+		CL_PRINTF(cli_buf);
+	}
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+		   "\r\n %-35s = %s (BB:%s)/ %s (BB:%s)/ %s (gnt_err = %d)",
+		   "GNT_WL_Ctrl/GNT_BT_Ctrl/Dbg",
+		   ((u32tmp[0] & BIT(12)) ? "SW" : "HW"),
+		   ((u32tmp[0] & BIT(8)) ?  "SW" : "HW"),
+		   ((u32tmp[0] & BIT(14)) ? "SW" : "HW"),
+		   ((u32tmp[0] & BIT(10)) ?  "SW" : "HW"),
+		   ((u8tmp[0] & BIT(3)) ? "On" : "Off"),
+		   coex_sta->gnt_error_cnt);
+	CL_PRINTF(cli_buf);
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ 0x%x",
+		   "GNT_WL/GNT_BT/ RF_0x1",
+		   (int)((u32tmp[1] & BIT(2)) >> 2),
+		   (int)((u32tmp[1] & BIT(3)) >> 3),
+		   btc->btc_get_rf_reg(btc, BTC_RF_A, 0x1, 0xfffff));
+	CL_PRINTF(cli_buf);
+
+	u32tmp[0] = btc->btc_read_4byte(btc, 0xcb0);
+	u32tmp[1] = btc->btc_read_4byte(btc, 0xcb4);
+	u8tmp[0] = btc->btc_read_1byte(btc, 0xcba);
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+		   "\r\n %-35s = 0x%04x/ 0x%04x/ 0x%02x %s",
+		   "0xcb0/0xcb4/0xcb8[23:16]",
+		   u32tmp[0], u32tmp[1], u8tmp[0],
+		   ((u8tmp[0] & 0x1) == 0x1 ?  "(BTG)" : "(WL_A+G)"));
+	CL_PRINTF(cli_buf);
+
+	u32tmp[0] = btc->btc_read_4byte(btc, 0x4c);
+	u8tmp[2] = btc->btc_read_1byte(btc, 0x64);
+	u8tmp[0] = btc->btc_read_1byte(btc, 0x4c6);
+	u8tmp[1] = btc->btc_read_1byte(btc, 0x40);
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+		   "\r\n %-35s = 0x%x/ 0x%x/ 0x%x/ 0x%x",
+		   "4c[24:23]/64[0]/4c6[4]/40[5]",
+		   (int)(u32tmp[0] & (BIT(24) | BIT(23))) >> 23,
+		    u8tmp[2] & 0x1, (int)((u8tmp[0] & BIT(4)) >> 4),
+		   (int)((u8tmp[1] & BIT(5)) >> 5));
+	CL_PRINTF(cli_buf);
+
+	u32tmp[0] = btc->btc_read_4byte(btc, 0x550);
+	u8tmp[0] = btc->btc_read_1byte(btc, 0x522);
+	u8tmp[1] = btc->btc_read_1byte(btc, 0x953);
+	u8tmp[2] = btc->btc_read_1byte(btc, 0xc50);
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+		   "\r\n %-35s = 0x%x/ 0x%x/ %s/ 0x%x",
+		   "0x550/0x522/4-RxAGC/0xc50", u32tmp[0], u8tmp[0],
+		   (u8tmp[1] & 0x2) ? "On" : "Off", u8tmp[2]);
+	CL_PRINTF(cli_buf);
+
+	fa_ofdm = btc->btc_phydm_query_PHY_counter(btc, PHYDM_INFO_FA_OFDM);
+	fa_cck = btc->btc_phydm_query_PHY_counter(btc, PHYDM_INFO_FA_CCK);
+	cca_ofdm = btc->btc_phydm_query_PHY_counter(btc, PHYDM_INFO_CCA_OFDM);
+	cca_cck = btc->btc_phydm_query_PHY_counter(btc, PHYDM_INFO_CCA_CCK);
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+		   "\r\n %-35s = 0x%x/ 0x%x/ 0x%x/ 0x%x",
+		   "CCK-CCA/CCK-FA/OFDM-CCA/OFDM-FA",
+		   cca_cck, fa_cck, cca_ofdm, fa_ofdm);
+	CL_PRINTF(cli_buf);
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d/ %d",
+		   "CRC_OK CCK/11g/11n/11ac",
+		   coex_sta->crc_ok_cck, coex_sta->crc_ok_11g,
+		   coex_sta->crc_ok_11n, coex_sta->crc_ok_11n_vht);
+	CL_PRINTF(cli_buf);
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d/ %d",
+		   "CRC_Err CCK/11g/11n/11ac",
+		   coex_sta->crc_err_cck, coex_sta->crc_err_11g,
+		   coex_sta->crc_err_11n, coex_sta->crc_err_11n_vht);
+	CL_PRINTF(cli_buf);
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+		   "\r\n %-35s = %d/ %d/ %s-%d/ %d (Tx macid: %d)",
+		   "Rate RxD/RxRTS/TxD/TxRetry_ratio",
+		   coex_sta->wl_rx_rate, coex_sta->wl_rts_rx_rate,
+		   (coex_sta->wl_tx_rate & 0x80 ? "SGI" : "LGI"),
+		   coex_sta->wl_tx_rate & 0x7f,
+		   coex_sta->wl_tx_retry_ratio,
+		   coex_sta->wl_tx_macid);
+	CL_PRINTF(cli_buf);
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s/ %s/ %s/ %s/ %d",
+		   "HiPr/ Locking/ warn/ Locked/ Noisy",
+		   (coex_sta->wifi_high_pri_task1 ? "Yes" : "No"),
+		   (coex_sta->cck_lock ? "Yes" : "No"),
+		   (coex_sta->cck_lock_warn ? "Yes" : "No"),
+		   (coex_sta->cck_lock_ever ? "Yes" : "No"),
+		   coex_sta->wl_noisy_level);
+	CL_PRINTF(cli_buf);
+
+	u8tmp[0] = btc->btc_read_1byte(btc, 0xf8e);
+	u8tmp[1] = btc->btc_read_1byte(btc, 0xf8f);
+	u8tmp[2] = btc->btc_read_1byte(btc, 0xd14);
+	u8tmp[3] = btc->btc_read_1byte(btc, 0xd54);
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d/ %d",
+		   "EVM_A/ EVM_B/ SNR_A/ SNR_B",
+		   (u8tmp[0] > 127 ? u8tmp[0] - 256 : u8tmp[0]),
+		   (u8tmp[1] > 127 ? u8tmp[1] - 256 : u8tmp[1]),
+		   (u8tmp[2] > 127 ? u8tmp[2] - 256 : u8tmp[2]),
+		   (u8tmp[3] > 127 ? u8tmp[3] - 256 : u8tmp[3]));
+	CL_PRINTF(cli_buf);
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d",
+		   "0x770(Hi-pri rx/tx)",
+		   coex_sta->high_priority_rx, coex_sta->high_priority_tx);
+	CL_PRINTF(cli_buf);
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d %s",
+		   "0x774(Lo-pri rx/tx)",
+		   coex_sta->low_priority_rx, coex_sta->low_priority_tx,
+		   (bt_link_info->slave_role ? "(Slave!!)" : (
+		   coex_sta->is_tdma_btautoslot_hang ?
+		   "(auto-slot hang!!)" : "")));
+	CL_PRINTF(cli_buf);
+
+	btc->btc_disp_dbg_msg(btc, BTC_DBG_DISP_COEX_STATISTICS);
+}
+
+void ex_halbtc8821c2ant_ips_notify(struct btc_coexist *btc, u8 type)
+{
+	struct coex_sta_8821c_2ant *coex_sta = &btc->coex_sta_8821c_2ant;
+
+	if (btc->manual_control || btc->stop_coex_dm)
+		return;
+
+	if (type == BTC_IPS_ENTER) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], IPS ENTER notify\n");
+		BTC_TRACE(trace_buf);
+		coex_sta->under_ips = TRUE;
+		coex_sta->under_lps = FALSE;
+
+		halbtc8821c2ant_write_scbd(btc, BT_8821C_2ANT_SCBD_ACTIVE |
+					   BT_8821C_2ANT_SCBD_ONOFF |
+					   BT_8821C_2ANT_SCBD_SCAN |
+					   BT_8821C_2ANT_SCBD_UNDERTEST,
+					   FALSE);
+
+		halbtc8821c2ant_set_ant_path(btc, BTC_ANT_PATH_AUTO, FC_EXCU,
+					     BT_8821C_2ANT_PHASE_WOFF);
+
+		halbtc8821c2ant_action_coex_all_off(btc);
+	} else if (type == BTC_IPS_LEAVE) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], IPS LEAVE notify\n");
+		BTC_TRACE(trace_buf);
+		coex_sta->under_ips = FALSE;
+
+		halbtc8821c2ant_init_hw_config(btc, FALSE);
+		halbtc8821c2ant_init_coex_dm(btc);
+		halbtc8821c2ant_query_bt_info(btc);
+	}
+}
+
+void ex_halbtc8821c2ant_lps_notify(struct btc_coexist *btc, u8 type)
+{
+	struct coex_sta_8821c_2ant *coex_sta = &btc->coex_sta_8821c_2ant;
+	static boolean  pre_force_lps_on = FALSE;
+
+	if (btc->manual_control || btc->stop_coex_dm)
+		return;
+
+	if (type == BTC_LPS_ENABLE) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], LPS ENABLE notify\n");
+		BTC_TRACE(trace_buf);
+		coex_sta->under_lps = TRUE;
+		coex_sta->under_ips = FALSE;
+
+		if (coex_sta->force_lps_ctrl == TRUE) { /* LPS No-32K */
+			/* Write WL "Active" in Score-board for PS-TDMA */
+			pre_force_lps_on = TRUE;
+			halbtc8821c2ant_write_scbd(btc,
+						   BT_8821C_2ANT_SCBD_ACTIVE,
+						   TRUE);
+
+		} else { /* LPS-32K, need check if this h2c 0x71 can work?? (2015/08/28) */
+			/* Write WL "Non-Active" in Score-board for Native-PS */
+			pre_force_lps_on = FALSE;
+			halbtc8821c2ant_write_scbd(btc,
+						   BT_8821C_2ANT_SCBD_ACTIVE,
+						   FALSE);
+
+			halbtc8821c2ant_action_wifi_native_lps(btc);
+		}
+
+	} else if (type == BTC_LPS_DISABLE) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], LPS DISABLE notify\n");
+		BTC_TRACE(trace_buf);
+		coex_sta->under_lps = FALSE;
+
+		halbtc8821c2ant_write_scbd(btc, BT_8821C_2ANT_SCBD_ACTIVE,
+					   TRUE);
+
+		if (!pre_force_lps_on && !coex_sta->force_lps_ctrl)
+			halbtc8821c2ant_query_bt_info(btc);
+	}
+}
+
+void ex_halbtc8821c2ant_scan_notify(struct btc_coexist *btc, u8 type)
+{
+	struct coex_sta_8821c_2ant *coex_sta = &btc->coex_sta_8821c_2ant;
+	boolean	wifi_connected = FALSE;
+
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+		    "[BTCoex], SCAN notify()\n");
+	BTC_TRACE(trace_buf);
+
+	if (btc->manual_control || btc->stop_coex_dm)
+		return;
+
+	btc->btc_get(btc, BTC_GET_BL_WIFI_CONNECTED, &wifi_connected);
+
+	if (wifi_connected)
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], ********** WL connected before SCAN\n");
+	else
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], **********  WL is not connected before SCAN\n");
+
+	BTC_TRACE(trace_buf);
+
+	/*  this can't be removed for RF off_on event,
+	 * r BT would dis-connect
+	 */
+	if (type != BTC_SCAN_FINISH) {
+		halbtc8821c2ant_write_scbd(btc, BT_8821C_2ANT_SCBD_ACTIVE |
+					   BT_8821C_2ANT_SCBD_SCAN |
+					   BT_8821C_2ANT_SCBD_ONOFF, TRUE);
+	}
+
+	if (type == BTC_SCAN_START_5G) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], SCAN START notify (5G)\n");
+		BTC_TRACE(trace_buf);
+
+		halbtc8821c2ant_set_ant_path(btc, BTC_ANT_PATH_AUTO,
+					     FC_EXCU, BT_8821C_2ANT_PHASE_5G);
+
+		halbtc8821c2ant_run_coex(btc, BT_8821C_2ANT_RSN_5GSCANSTART);
+	} else if (type == BTC_SCAN_START_2G || type == BTC_SCAN_START) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], SCAN START notify (2G)\n");
+		BTC_TRACE(trace_buf);
+
+		if (!wifi_connected)
+			coex_sta->wifi_high_pri_task2 = TRUE;
+
+		halbtc8821c2ant_set_ant_path(btc, BTC_ANT_PATH_AUTO, FC_EXCU,
+					     BT_8821C_2ANT_PHASE_2G);
+
+		halbtc8821c2ant_run_coex(btc, BT_8821C_2ANT_RSN_2GSCANSTART);
+	} else if (type == BTC_SCAN_FINISH) {
+		btc->btc_get(btc, BTC_GET_U1_AP_NUM, &coex_sta->scan_ap_num);
+
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], SCAN FINISH notify  (Scan-AP = %d)\n",
+			    coex_sta->scan_ap_num);
+		BTC_TRACE(trace_buf);
+
+		coex_sta->wifi_high_pri_task2 = FALSE;
+
+		halbtc8821c2ant_run_coex(btc, BT_8821C_2ANT_RSN_SCANFINISH);
+	}
+}
+
+void ex_halbtc8821c2ant_switchband_notify(struct btc_coexist *btc, u8 type)
+{
+	struct coex_sta_8821c_2ant *coex_sta = &btc->coex_sta_8821c_2ant;
+
+	if (btc->manual_control || btc->stop_coex_dm)
+		return;
+
+	coex_sta->switch_band_notify_to = type;
+
+	if (type == BTC_SWITCH_TO_5G) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], switchband_notify ---  switch to 5G\n");
+		BTC_TRACE(trace_buf);
+
+		halbtc8821c2ant_run_coex(btc, BT_8821C_2ANT_RSN_5GSWITCHBAND);
+	} else if (type == BTC_SWITCH_TO_24G_NOFORSCAN) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			"[BTCoex], switchband_notify --- BTC_SWITCH_TO_2G (no for scan)\n");
+		BTC_TRACE(trace_buf);
+
+		halbtc8821c2ant_run_coex(btc, BT_8821C_2ANT_RSN_2GSWITCHBAND);
+	} else {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], switchband_notify ---  switch to 2G\n");
+		BTC_TRACE(trace_buf);
+
+		ex_halbtc8821c2ant_scan_notify(btc, BTC_SCAN_START_2G);
+	}
+
+	coex_sta->switch_band_notify_to = BTC_NOT_SWITCH;
+}
+
+void ex_halbtc8821c2ant_connect_notify(struct btc_coexist *btc,
+				       u8 type)
+{
+	struct coex_sta_8821c_2ant *coex_sta = &btc->coex_sta_8821c_2ant;
+	struct coex_dm_8821c_2ant *coex_dm = &btc->coex_dm_8821c_2ant;
+
+	if (btc->manual_control || btc->stop_coex_dm)
+		return;
+
+	halbtc8821c2ant_write_scbd(btc, BT_8821C_2ANT_SCBD_ACTIVE |
+				   BT_8821C_2ANT_SCBD_SCAN |
+				   BT_8821C_2ANT_SCBD_ONOFF, TRUE);
+
+	if (type == BTC_ASSOCIATE_5G_START ||
+	    type == BTC_ASSOCIATE_5G_FINISH) {
+		halbtc8821c2ant_set_ant_path(btc, BTC_ANT_PATH_AUTO, FC_EXCU,
+					     BT_8821C_2ANT_PHASE_5G);
+
+		if (type == BTC_ASSOCIATE_5G_START) {
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+					"[BTCoex], CONNECT START notify (5G)\n");
+			BTC_TRACE(trace_buf);
+
+			halbtc8821c2ant_run_coex(btc,
+						 BT_8821C_2ANT_RSN_5GCONSTART);
+		} else {
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				"[BTCoex], CONNECT FINISH notify (5G)\n");
+			BTC_TRACE(trace_buf);
+
+			halbtc8821c2ant_run_coex(btc,
+						 BT_8821C_2ANT_RSN_5GCONFINISH);
+		}
+	} else if (type == BTC_ASSOCIATE_START) {
+		coex_sta->wifi_high_pri_task1 = TRUE;
+
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], CONNECT START notify (2G)\n");
+		BTC_TRACE(trace_buf);
+
+		halbtc8821c2ant_set_ant_path(btc, BTC_ANT_PATH_AUTO, FC_EXCU,
+					     BT_8821C_2ANT_PHASE_2G);
+
+		halbtc8821c2ant_run_coex(btc, BT_8821C_2ANT_RSN_2GCONSTART);
+
+		/* To keep TDMA case during connect process,
+		to avoid changed by Btinfo and runcoexmechanism */
+		coex_sta->freeze_coexrun_by_btinfo = TRUE;
+		coex_dm->arp_cnt = 0;
+	} else if (type == BTC_ASSOCIATE_FINISH) {
+		coex_sta->wifi_high_pri_task1 = FALSE;
+		coex_sta->freeze_coexrun_by_btinfo = FALSE;
+
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], CONNECT FINISH notify (2G)\n");
+		BTC_TRACE(trace_buf);
+
+		halbtc8821c2ant_run_coex(btc, BT_8821C_2ANT_RSN_2GCONFINISH);
+	}
+}
+
+void ex_halbtc8821c2ant_media_status_notify(struct btc_coexist *btc, u8 type)
+{
+	struct coex_sta_8821c_2ant *coex_sta = &btc->coex_sta_8821c_2ant;
+	u8 h2c_parameter[3] = {0};
+	boolean	wifi_under_b_mode = FALSE;
+	u16 ap_beacon_interval = 100;
+
+	if (btc->manual_control || btc->stop_coex_dm)
+		return;
+
+	if (type == BTC_MEDIA_CONNECT || type == BTC_MEDIA_CONNECT_5G) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], MEDIA connect notify\n");
+		BTC_TRACE(trace_buf);
+
+		halbtc8821c2ant_write_scbd(btc, BT_8821C_2ANT_SCBD_ACTIVE |
+					   BT_8821C_2ANT_SCBD_ONOFF, TRUE);
+
+		if (type == BTC_MEDIA_CONNECT_5G) {
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				    "[BTCoex], WiFi is under 5G!!!\n");
+			BTC_TRACE(trace_buf);
+
+			halbtc8821c2ant_set_ant_path(btc, BTC_ANT_PATH_AUTO,
+						     FC_EXCU,
+						     BT_8821C_2ANT_PHASE_5G);
+
+			halbtc8821c2ant_run_coex(btc,
+						 BT_8821C_2ANT_RSN_5GMEDIA);
+		} else {
+			halbtc8821c2ant_set_ant_path(btc, BTC_ANT_PATH_AUTO,
+						     FC_EXCU,
+						     BT_8821C_2ANT_PHASE_2G);
+
+			btc->btc_get(btc, BTC_GET_BL_WIFI_UNDER_B_MODE,
+				     &wifi_under_b_mode);
+
+			/* Set CCK Tx/Rx high Pri except 11b mode */
+			if (wifi_under_b_mode) {
+				/* CCK Tx */
+				btc->btc_write_1byte(btc, 0x6cd, 0x00);
+				/* CCK Rx */
+				btc->btc_write_1byte(btc, 0x6cf, 0x00);
+			} else {
+				/* CCK Tx */
+				btc->btc_write_1byte(btc, 0x6cd, 0x00);
+				/* CCK Rx */
+				btc->btc_write_1byte(btc, 0x6cf, 0x10);
+			}
+
+			btc->btc_get(btc, BTC_GET_U2_BEACON_PERIOD,
+				     &ap_beacon_interval);
+
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				    "[BTCoex], AP beacon interval = %d\n",
+				    ap_beacon_interval);
+			BTC_TRACE(trace_buf);
+
+			/* set TDMA waiting BI if BI is not equal to 100 */
+			if (ap_beacon_interval < 80 && ap_beacon_interval > 0) {
+				h2c_parameter[0] = 0xb;
+				h2c_parameter[1] = (100 / ap_beacon_interval);
+
+				if (100 % ap_beacon_interval != 0)
+					h2c_parameter[1] = h2c_parameter[1] + 1;
+			} else if (ap_beacon_interval >= 180) {
+				h2c_parameter[0] = 0xb;
+				h2c_parameter[1] = (ap_beacon_interval / 100);
+
+				if (ap_beacon_interval % 100 <= 80)
+					h2c_parameter[1] = h2c_parameter[1] - 1;
+
+				h2c_parameter[1] = h2c_parameter[1] | 0x80;
+			} else {
+				h2c_parameter[0] = 0xb;
+				h2c_parameter[1] = 0x1;
+			}
+
+			btc->btc_fill_h2c(btc, 0x69, 2, h2c_parameter);
+
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				    "[BTCoex], TDMA waiting BI = 0x%x\n",
+				    h2c_parameter[1]);
+			BTC_TRACE(trace_buf);
+
+			halbtc8821c2ant_run_coex(btc,
+						 BT_8821C_2ANT_RSN_2GMEDIA);
+		}
+	} else {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], MEDIA disconnect notify\n");
+		BTC_TRACE(trace_buf);
+
+		btc->btc_write_1byte(btc, 0x6cd, 0x0); /* CCK Tx */
+		btc->btc_write_1byte(btc, 0x6cf, 0x0); /* CCK Rx */
+
+		halbtc8821c2ant_write_scbd(btc, BT_8821C_2ANT_SCBD_ACTIVE,
+					   FALSE);
+
+		coex_sta->cck_lock_ever = FALSE;
+		coex_sta->cck_lock_warn = FALSE;
+		coex_sta->cck_lock = FALSE;
+
+		halbtc8821c2ant_run_coex(btc, BT_8821C_2ANT_RSN_MEDIADISCON);
+	}
+
+	halbtc8821c2ant_update_wifi_ch_info(btc, type);
+}
+
+void ex_halbtc8821c2ant_specific_packet_notify(struct btc_coexist *btc, u8 type)
+{
+	struct coex_sta_8821c_2ant *coex_sta = &btc->coex_sta_8821c_2ant;
+	struct coex_dm_8821c_2ant *coex_dm = &btc->coex_dm_8821c_2ant;
+	boolean under_4way = FALSE;
+
+	if (btc->manual_control || btc->stop_coex_dm)
+		return;
+
+	if (type & BTC_5G_BAND) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], 5g special packet notify\n");
+		BTC_TRACE(trace_buf);
+
+		halbtc8821c2ant_run_coex(btc, BT_8821C_2ANT_RSN_5GSPECIALPKT);
+		return;
+	}
+
+	btc->btc_get(btc, BTC_GET_BL_WIFI_4_WAY_PROGRESS, &under_4way);
+
+	if (under_4way) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], specific Packet ---- under_4way!!\n");
+		BTC_TRACE(trace_buf);
+
+		coex_sta->wifi_high_pri_task1 = TRUE;
+		coex_sta->specific_pkt_period_cnt = 2;
+	} else if (type == BTC_PACKET_ARP) {
+		coex_dm->arp_cnt++;
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], specific Packet ARP notify -cnt = %d\n",
+			    coex_dm->arp_cnt);
+		BTC_TRACE(trace_buf);
+	} else {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], specific Packet DHCP or EAPOL notify [Type = %d]\n",
+			    type);
+		BTC_TRACE(trace_buf);
+
+		coex_sta->wifi_high_pri_task1 = TRUE;
+		coex_sta->specific_pkt_period_cnt = 2;
+	}
+
+	if (coex_sta->wifi_high_pri_task1) {
+		halbtc8821c2ant_write_scbd(btc, BT_8821C_2ANT_SCBD_SCAN, TRUE);
+		halbtc8821c2ant_run_coex(btc, BT_8821C_2ANT_RSN_2GSPECIALPKT);
+	}
+}
+
+void ex_halbtc8821c2ant_bt_info_notify(struct btc_coexist *btc, u8 *tmp_buf,
+				       u8 length)
+{
+	struct coex_sta_8821c_2ant *coex_sta = &btc->coex_sta_8821c_2ant;
+	u8 i, rsp_source = 0;
+	boolean	wifi_connected = FALSE;
+	boolean	wifi_busy = FALSE;
+	static boolean is_scoreboard_scan;
+	const u16 type_is_scan = BT_8821C_2ANT_SCBD_SCAN;
+	u8 type;
+
+	rsp_source = tmp_buf[0] & 0xf;
+	if (rsp_source >= BT_8821C_2ANT_INFO_SRC_MAX)
+		rsp_source = BT_8821C_2ANT_INFO_SRC_WIFI_FW;
+	coex_sta->bt_info_c2h_cnt[rsp_source]++;
+
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+		    "[BTCoex], Bt_info[%d], len=%d, data=[", rsp_source,
+		    length);
+	BTC_TRACE(trace_buf);
+
+	if (rsp_source == BT_8821C_2ANT_INFO_SRC_BT_RSP ||
+	    rsp_source == BT_8821C_2ANT_INFO_SRC_BT_ACT) {
+		if (coex_sta->bt_disabled) {
+			coex_sta->bt_disabled = FALSE;
+			coex_sta->is_bt_reenable = TRUE;
+			coex_sta->cnt_bt_reenable = 15;
+
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				    "[BTCoex], BT enable detected by bt_info\n");
+			BTC_TRACE(trace_buf);
+		}
+	}
+
+	for (i = 0; i < length; i++) {
+		coex_sta->bt_info_c2h[rsp_source][i] = tmp_buf[i];
+
+		if (i == length - 1) {
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "0x%02x]\n",
+				    tmp_buf[i]);
+			BTC_TRACE(trace_buf);
+		} else {
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "0x%02x, ",
+				    tmp_buf[i]);
+			BTC_TRACE(trace_buf);
+		}
+	}
+
+	coex_sta->bt_info = coex_sta->bt_info_c2h[rsp_source][1];
+	coex_sta->bt_info_ext = coex_sta->bt_info_c2h[rsp_source][4];
+	coex_sta->bt_info_ext2 = coex_sta->bt_info_c2h[rsp_source][5];
+
+	if (rsp_source != BT_8821C_2ANT_INFO_SRC_WIFI_FW) {
+		/* if 0xff, it means BT is under WHCK test */
+		coex_sta->bt_whck_test = ((coex_sta->bt_info == 0xff) ? TRUE :
+					  FALSE);
+
+		coex_sta->bt_create_connection = ((
+			coex_sta->bt_info_c2h[rsp_source][2] & 0x80) ? TRUE :
+						  FALSE);
+
+		/* unit: %, value-100 to translate to unit: dBm */
+		coex_sta->bt_rssi = coex_sta->bt_info_c2h[rsp_source][3] * 2 +
+				    10;
+
+		coex_sta->c2h_bt_remote_name_req = ((
+			coex_sta->bt_info_c2h[rsp_source][2] & 0x20) ? TRUE :
+						    FALSE);
+
+		coex_sta->is_A2DP_3M = ((coex_sta->bt_info_c2h[rsp_source][2] &
+					 0x10) ? TRUE : FALSE);
+
+		coex_sta->acl_busy = ((coex_sta->bt_info_c2h[rsp_source][1] &
+				       0x8) ? TRUE : FALSE);
+
+		coex_sta->voice_over_HOGP = ((coex_sta->bt_info_ext & 0x10) ?
+					     TRUE : FALSE);
+
+		coex_sta->c2h_bt_inquiry_page = ((coex_sta->bt_info &
+			  BT_INFO_8821C_2ANT_B_INQ_PAGE) ? TRUE : FALSE);
+
+		coex_sta->a2dp_bit_pool = (((
+			coex_sta->bt_info_c2h[rsp_source][1] & 0x49) == 0x49) ?
+			(coex_sta->bt_info_c2h[rsp_source][6] & 0x7f) : 0);
+
+		coex_sta->is_bt_a2dp_sink =
+			(coex_sta->bt_info_c2h[rsp_source][6] & 0x80) ?
+			TRUE : FALSE;
+
+		coex_sta->bt_retry_cnt = coex_sta->bt_info_c2h[rsp_source][2] &
+					 0xf;
+
+		coex_sta->is_autoslot = coex_sta->bt_info_ext2 & 0x8;
+
+		coex_sta->forbidden_slot = coex_sta->bt_info_ext2 & 0x7;
+
+		coex_sta->hid_busy_num = (coex_sta->bt_info_ext2 & 0x30) >> 4;
+
+		coex_sta->hid_pair_cnt = (coex_sta->bt_info_ext2 & 0xc0) >> 6;
+
+		coex_sta->is_bt_opp_exist =
+				(coex_sta->bt_info_ext2 & 0x1) ? TRUE : FALSE;
+
+		if (coex_sta->bt_retry_cnt >= 1)
+			coex_sta->pop_event_cnt++;
+
+		if (coex_sta->c2h_bt_remote_name_req)
+			coex_sta->cnt_remote_name_req++;
+
+		if (coex_sta->bt_info_ext & BIT(1))
+			coex_sta->cnt_reinit++;
+
+		if (coex_sta->bt_info_ext & BIT(2) ||
+		    (coex_sta->bt_create_connection &&
+		    coex_sta->wl_pnp_wakeup_downcnt > 0)) {
+			coex_sta->cnt_setup_link++;
+			coex_sta->is_setup_link = TRUE;
+			if (coex_sta->is_bt_reenable)
+				coex_sta->bt_relink_downcount = 6;
+			else
+				coex_sta->bt_relink_downcount = 2;
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				"[BTCoex], Re-Link start in BT info!!\n");
+			BTC_TRACE(trace_buf);
+		} else {
+			coex_sta->is_setup_link = FALSE;
+			if (!coex_sta->is_bt_reenable)
+				coex_sta->bt_relink_downcount = 0;
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				    "[BTCoex], Re-Link stop in BT info!!\n");
+			BTC_TRACE(trace_buf);
+		}
+
+		if (coex_sta->bt_info_ext & BIT(3))
+			coex_sta->cnt_ign_wlan_act++;
+
+		if (coex_sta->bt_info_ext & BIT(6))
+			coex_sta->cnt_role_switch++;
+
+		if (coex_sta->bt_info_ext & BIT(7))
+			coex_sta->is_bt_multi_link = TRUE;
+		else
+			coex_sta->is_bt_multi_link = FALSE;
+
+		if (coex_sta->bt_info_ext & BIT(0))
+			coex_sta->is_hid_rcu = TRUE;
+		else
+			coex_sta->is_hid_rcu = FALSE;
+
+		if (coex_sta->bt_info_ext & BIT(5))
+			coex_sta->is_ble_scan_en = TRUE;
+		else
+			coex_sta->is_ble_scan_en = FALSE;
+
+		if (coex_sta->bt_create_connection) {
+			coex_sta->cnt_page++;
+
+			btc->btc_get(btc, BTC_GET_BL_WIFI_BUSY, &wifi_busy);
+
+			if (coex_sta->is_wifi_linkscan_process ||
+			    coex_sta->wifi_high_pri_task1 ||
+			    coex_sta->wifi_high_pri_task2 ||
+			    wifi_busy) {
+				is_scoreboard_scan = TRUE;
+				halbtc8821c2ant_write_scbd(btc, type_is_scan,
+							   TRUE);
+
+			} else
+				halbtc8821c2ant_write_scbd(btc, type_is_scan,
+							   FALSE);
+
+		} else {
+			if (is_scoreboard_scan) {
+				halbtc8821c2ant_write_scbd(btc, type_is_scan,
+							   FALSE);
+				is_scoreboard_scan = FALSE;
+			}
+		}
+
+		/* Here we need to resend some wifi info to BT */
+		/* because bt is reset and loss of the info. */
+		btc->btc_get(btc, BTC_GET_BL_WIFI_CONNECTED, &wifi_connected);
+
+		/*  Re-Init */
+		if ((coex_sta->bt_info_ext & BIT(1))) {
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				    "[BTCoex], BT ext info bit1 check, send wifi BW&Chnl to BT!!\n");
+			BTC_TRACE(trace_buf);
+			if (wifi_connected)
+				type = BTC_MEDIA_CONNECT;
+			else
+				type = BTC_MEDIA_DISCONNECT;
+			halbtc8821c2ant_update_wifi_ch_info(btc, type);
+		}
+
+		/*  If Ignore_WLanAct && not SetUp_Link */
+		if ((coex_sta->bt_info_ext & BIT(3)) &&
+		    (!(coex_sta->bt_info_ext & BIT(2))) &&
+		    (!(coex_sta->bt_info_ext & BIT(6)))) {
+
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				    "[BTCoex], BT ext info bit3 check, set BT NOT to ignore Wlan active!!\n");
+			BTC_TRACE(trace_buf);
+			halbtc8821c2ant_ignore_wlan_act(btc, FC_EXCU, FALSE);
+		} else {
+			if (coex_sta->bt_info_ext & BIT(2)) {
+				BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+					    "[BTCoex], BT ignore Wlan active because Re-link!!\n");
+				BTC_TRACE(trace_buf);
+			} else if (coex_sta->bt_info_ext & BIT(6)) {
+				BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+					    "[BTCoex], BT ignore Wlan active because Role-Switch!!\n");
+				BTC_TRACE(trace_buf);
+			}
+		}
+	}
+
+	halbtc8821c2ant_update_bt_link_info(btc);
+	halbtc8821c2ant_run_coex(btc, BT_8821C_2ANT_RSN_BTINFO);
+}
+
+void ex_halbtc8821c2ant_wl_fwdbginfo_notify(struct btc_coexist *btc,
+					    u8 *tmp_buf, u8 length)
+{
+	struct coex_sta_8821c_2ant *coex_sta = &btc->coex_sta_8821c_2ant;
+	u8 i = 0;
+	static u8 tmp_buf_pre[10] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
+
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+		    "[BTCoex], WiFi Fw Dbg info = %d %d %d %d %d %d (len = %d)\n",
+		    tmp_buf[0], tmp_buf[1], tmp_buf[2], tmp_buf[3], tmp_buf[4],
+		    tmp_buf[5], length);
+	BTC_TRACE(trace_buf);
+
+	if (tmp_buf[0] == 0x8) {
+		for (i = 1; i <= 5; i++) {
+			coex_sta->wl_fw_dbg_info[i] =
+				(tmp_buf[i] >= tmp_buf_pre[i]) ?
+				(tmp_buf[i] - tmp_buf_pre[i]) :
+				(255 - tmp_buf_pre[i] + tmp_buf[i]);
+
+			tmp_buf_pre[i] = tmp_buf[i];
+		}
+	}
+}
+
+void ex_halbtc8821c2ant_rx_rate_change_notify(struct btc_coexist *btc,
+					      BOOLEAN is_data_frame,
+					      u8 btc_rate_id)
+{
+	struct coex_sta_8821c_2ant *coex_sta = &btc->coex_sta_8821c_2ant;
+	struct coex_dm_8821c_2ant *coex_dm = &btc->coex_dm_8821c_2ant;
+	BOOLEAN wifi_connected = FALSE;
+
+	btc->btc_get(btc, BTC_GET_BL_WIFI_CONNECTED, &wifi_connected);
+
+	if (is_data_frame) {
+		coex_sta->wl_rx_rate = btc_rate_id;
+
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], rx_rate_change_notify data rate id = %d, RTS_Rate = %d\n",
+			    coex_sta->wl_rx_rate, coex_sta->wl_rts_rx_rate);
+		BTC_TRACE(trace_buf);
+	} else {
+		coex_sta->wl_rts_rx_rate = btc_rate_id;
+
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], rts_rate_change_notify RTS rate id = %d, RTS_Rate = %d\n",
+			    coex_sta->wl_rts_rx_rate, coex_sta->wl_rts_rx_rate);
+		BTC_TRACE(trace_buf);
+	}
+
+	if (wifi_connected &&
+	    (coex_dm->bt_status == BT_8821C_2ANT_BSTATUS_ACL_BUSY ||
+	     coex_dm->bt_status == BT_8821C_2ANT_BSTATUS_ACL_SCO_BUSY ||
+	     coex_dm->bt_status == BT_8821C_2ANT_BSTATUS_SCO_BUSY)) {
+		if (coex_sta->wl_rx_rate == BTC_CCK_5_5 ||
+		    coex_sta->wl_rx_rate == BTC_OFDM_6 ||
+		    coex_sta->wl_rx_rate == BTC_MCS_0) {
+			coex_sta->cck_lock_warn = TRUE;
+
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				    "[BTCoex], cck lock warning...\n");
+			BTC_TRACE(trace_buf);
+		} else if (coex_sta->wl_rx_rate == BTC_CCK_1 ||
+			   coex_sta->wl_rx_rate == BTC_CCK_2 ||
+			   coex_sta->wl_rts_rx_rate == BTC_CCK_1 ||
+			   coex_sta->wl_rts_rx_rate == BTC_CCK_2) {
+			coex_sta->cck_lock = TRUE;
+
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				    "[BTCoex], cck locking...\n");
+			BTC_TRACE(trace_buf);
+		} else {
+			coex_sta->cck_lock_warn = FALSE;
+			coex_sta->cck_lock = FALSE;
+
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				    "[BTCoex], cck unlock...\n");
+			BTC_TRACE(trace_buf);
+		}
+	} else {
+		if (coex_dm->bt_status == BT_8821C_2ANT_BSTATUS_CON_IDLE ||
+		    coex_dm->bt_status == BT_8821C_2ANT_BSTATUS_NCON_IDLE) {
+			coex_sta->cck_lock_warn = FALSE;
+			coex_sta->cck_lock = FALSE;
+		}
+	}
+}
+
+void ex_halbtc8821c2ant_tx_rate_change_notify(struct btc_coexist *btc,
+					      u8 tx_rate, u8 tx_retry_ratio,
+					      u8 macid)
+{
+	struct coex_sta_8821c_2ant *coex_sta = &btc->coex_sta_8821c_2ant;
+
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+		    "[BTCoex], tx_rate_change_notify Tx_Rate = %d, Tx_Retry_Ratio = %d, macid =%d\n",
+		    tx_rate, tx_retry_ratio, macid);
+	BTC_TRACE(trace_buf);
+
+	coex_sta->wl_tx_rate = tx_rate;
+	coex_sta->wl_tx_retry_ratio = tx_retry_ratio;
+	coex_sta->wl_tx_macid = macid;
+}
+
+void ex_halbtc8821c2ant_rf_status_notify(struct btc_coexist *btc, u8 type)
+{
+	struct coex_sta_8821c_2ant *coex_sta = &btc->coex_sta_8821c_2ant;
+
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], RF Status notify\n");
+	BTC_TRACE(trace_buf);
+
+	if (type == BTC_RF_ON) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], RF is turned ON!!\n");
+		BTC_TRACE(trace_buf);
+
+		btc->stop_coex_dm = FALSE;
+		coex_sta->is_rf_state_off = FALSE;
+	} else if (type == BTC_RF_OFF) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], RF is turned OFF!!\n");
+		BTC_TRACE(trace_buf);
+
+		halbtc8821c2ant_write_scbd(btc, BT_8821C_2ANT_SCBD_ACTIVE |
+					   BT_8821C_2ANT_SCBD_ONOFF |
+					   BT_8821C_2ANT_SCBD_SCAN |
+					   BT_8821C_2ANT_SCBD_UNDERTEST,
+					   FALSE);
+
+		halbtc8821c2ant_set_ant_path(btc, BTC_ANT_PATH_AUTO, FC_EXCU,
+					     BT_8821C_2ANT_PHASE_WOFF);
+
+		halbtc8821c2ant_action_coex_all_off(btc);
+
+		btc->stop_coex_dm = TRUE;
+		coex_sta->is_rf_state_off = TRUE;
+		/* must place in the last step */
+		halbtc8821c2ant_update_wifi_ch_info(btc, BTC_MEDIA_DISCONNECT);
+	}
+}
+
+void ex_halbtc8821c2ant_halt_notify(struct btc_coexist *btc)
+{
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], Halt notify\n");
+	BTC_TRACE(trace_buf);
+
+	halbtc8821c2ant_write_scbd(btc, BT_8821C_2ANT_SCBD_ACTIVE |
+				   BT_8821C_2ANT_SCBD_ONOFF |
+				   BT_8821C_2ANT_SCBD_SCAN |
+				   BT_8821C_2ANT_SCBD_UNDERTEST,
+				   FALSE);
+
+	halbtc8821c2ant_set_ant_path(btc, BTC_ANT_PATH_AUTO, FC_EXCU,
+				     BT_8821C_2ANT_PHASE_WOFF);
+
+	halbtc8821c2ant_action_coex_all_off(btc);
+
+	btc->stop_coex_dm = TRUE;
+
+	/* must place in the last step */
+	halbtc8821c2ant_update_wifi_ch_info(btc, BTC_MEDIA_DISCONNECT);
+}
+
+void ex_halbtc8821c2ant_pnp_notify(struct btc_coexist *btc, u8 pnp_state)
+{
+	struct coex_sta_8821c_2ant *coex_sta = &btc->coex_sta_8821c_2ant;
+	struct wifi_link_info_8821c_2ant *wifi_link_info_ext =
+					 &btc->wifi_link_info_8821c_2ant;
+	static u8 pre_pnp_state;
+	u8 phase;
+
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], Pnp notify\n");
+	BTC_TRACE(trace_buf);
+
+	if (pnp_state == BTC_WIFI_PNP_SLEEP ||
+	    pnp_state == BTC_WIFI_PNP_SLEEP_KEEP_ANT) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], Pnp notify to SLEEP\n");
+		BTC_TRACE(trace_buf);
+
+		/* Sinda 20150819, workaround for driver skip
+		 * leave IPS/LPS to speed up sleep time.
+		 * Driver do not leave IPS/LPS when driver is going to sleep,
+		 * so BTCoexistence think wifi is still under IPS/LPS
+		 * BT should clear UnderIPS/UnderLPS state to avoid mismatch
+		 * state after wakeup.
+		 */
+		coex_sta->under_ips = FALSE;
+		coex_sta->under_lps = FALSE;
+
+		halbtc8821c2ant_write_scbd(btc, BT_8821C_2ANT_SCBD_ACTIVE |
+					   BT_8821C_2ANT_SCBD_ONOFF |
+					   BT_8821C_2ANT_SCBD_SCAN |
+					   BT_8821C_2ANT_SCBD_UNDERTEST,
+					   FALSE);
+
+		if (pnp_state == BTC_WIFI_PNP_SLEEP_KEEP_ANT) {
+			if (wifi_link_info_ext->is_all_under_5g)
+				phase = BT_8821C_2ANT_PHASE_5G;
+			else
+				phase = BT_8821C_2ANT_PHASE_2G;
+		} else {
+			phase = BT_8821C_2ANT_PHASE_WOFF;
+		}
+
+		halbtc8821c2ant_set_ant_path(btc, BTC_ANT_PATH_AUTO, FC_EXCU,
+					     phase);
+		btc->stop_coex_dm = TRUE;
+	} else {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], Pnp notify to WAKE UP\n");
+		BTC_TRACE(trace_buf);
+		coex_sta->wl_pnp_wakeup_downcnt = 3;
+
+		/*WoWLAN*/
+		if (pre_pnp_state == BTC_WIFI_PNP_SLEEP_KEEP_ANT ||
+		    pnp_state == BTC_WIFI_PNP_WOWLAN) {
+			coex_sta->run_time_state = TRUE;
+			btc->stop_coex_dm = FALSE;
+			halbtc8821c2ant_run_coex(btc, BT_8821C_2ANT_RSN_PNP);
+		}
+	}
+
+	pre_pnp_state = pnp_state;
+}
+
+void ex_halbtc8821c2ant_periodical(struct btc_coexist *btc)
+{
+	struct coex_sta_8821c_2ant *coex_sta = &btc->coex_sta_8821c_2ant;
+	struct  btc_board_info	*board_info = &btc->board_info;
+	boolean bt_relink_finish = FALSE, is_defreeze = FALSE;
+	static u8 freeze_cnt;
+
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+		    "[BTCoex], ************* Periodical *************\n");
+	BTC_TRACE(trace_buf);
+
+	if (!btc->auto_report)
+		halbtc8821c2ant_query_bt_info(btc);
+
+	halbtc8821c2ant_monitor_bt_ctr(btc);
+	halbtc8821c2ant_monitor_wifi_ctr(btc);
+	halbtc8821c2ant_update_wifi_link_info(btc,
+					      BT_8821C_2ANT_RSN_PERIODICAL);
+	halbtc8821c2ant_monitor_bt_enable(btc);
+
+	if (coex_sta->bt_relink_downcount != 0) {
+		coex_sta->bt_relink_downcount--;
+		if (coex_sta->bt_relink_downcount == 0) {
+			coex_sta->is_setup_link = FALSE;
+			bt_relink_finish = TRUE;
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				    "[BTCoex], Re-Link stop by periodical count-down!!\n");
+			BTC_TRACE(trace_buf);
+		}
+	}
+
+	if (coex_sta->freeze_coexrun_by_btinfo) {
+		freeze_cnt++;
+
+		if (freeze_cnt >= 5) {
+			freeze_cnt = 0;
+			coex_sta->freeze_coexrun_by_btinfo = FALSE;
+			is_defreeze = TRUE;
+		}
+	} else {
+		freeze_cnt = 0;
+	}
+
+	/* for 4-way, DHCP, EAPOL packet */
+	if (coex_sta->specific_pkt_period_cnt > 0) {
+		coex_sta->specific_pkt_period_cnt--;
+
+		if (!coex_sta->freeze_coexrun_by_btinfo &&
+		    coex_sta->specific_pkt_period_cnt == 0)
+			coex_sta->wifi_high_pri_task1 = FALSE;
+
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], Hi-Pri Task = %s\n",
+			    (coex_sta->wifi_high_pri_task1 ? "Yes" : "No"));
+		BTC_TRACE(trace_buf);
+	}
+
+	if (coex_sta->wl_pnp_wakeup_downcnt > 0) {
+		coex_sta->wl_pnp_wakeup_downcnt--;
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], wl_pnp_wakeup_downcnt = %d!!\n",
+			    coex_sta->wl_pnp_wakeup_downcnt);
+		BTC_TRACE(trace_buf);
+	}
+
+	if (coex_sta->cnt_bt_reenable > 0) {
+		coex_sta->cnt_bt_reenable--;
+		if (coex_sta->cnt_bt_reenable == 0) {
+			coex_sta->is_bt_reenable = FALSE;
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				    "[BTCoex], BT renable 30s finish!!\n");
+			BTC_TRACE(trace_buf);
+		}
+	}
+
+	if (halbtc8821c2ant_moniter_wifibt_status(btc) || bt_relink_finish ||
+	    coex_sta->is_set_ps_state_fail || is_defreeze)
+		halbtc8821c2ant_run_coex(btc, BT_8821C_2ANT_RSN_PERIODICAL);
+}
+/*#pragma optimize( "", off )*/
+
+#endif
+
+#endif	/*  #if (RTL8821C_SUPPORT == 1) */
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/btc/halbtc8821c2ant.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/btc/halbtc8821c2ant.h
--- linux-5.6.3/3rdparty/rtl8821ce/hal/btc/halbtc8821c2ant.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/btc/halbtc8821c2ant.h	2020-04-10 16:35:06.785658620 +0300
@@ -0,0 +1,488 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2016 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+
+#if (BT_SUPPORT == 1 && COEX_SUPPORT == 1)
+
+#if (RTL8821C_SUPPORT == 1)
+
+/* *******************************************
+ * The following is for 8821C 2Ant BT Co-exist definition
+ * ******************************************* */
+#define	BT_8821C_2ANT_COEX_DBG				0
+#define	BT_AUTO_REPORT_ONLY_8821C_2ANT			1
+
+#define	BT_INFO_8821C_2ANT_B_FTP			BIT(7)
+#define	BT_INFO_8821C_2ANT_B_A2DP			BIT(6)
+#define	BT_INFO_8821C_2ANT_B_HID			BIT(5)
+#define	BT_INFO_8821C_2ANT_B_SCO_BUSY			BIT(4)
+#define	BT_INFO_8821C_2ANT_B_ACL_BUSY			BIT(3)
+#define	BT_INFO_8821C_2ANT_B_INQ_PAGE			BIT(2)
+#define	BT_INFO_8821C_2ANT_B_SCO_ESCO			BIT(1)
+#define	BT_INFO_8821C_2ANT_B_CONNECTION			BIT(0)
+
+#define	BTC_RSSI_COEX_THRESH_TOL_8821C_2ANT		2
+
+#define	BT_8821C_2ANT_WIFI_RSSI_COEXSWITCH_THRES1	80
+#define	BT_8821C_2ANT_BT_RSSI_COEXSWITCH_THRES1		80
+#define	BT_8821C_2ANT_WIFI_RSSI_COEXSWITCH_THRES2	80
+#define	BT_8821C_2ANT_BT_RSSI_COEXSWITCH_THRES2		80
+#define	BT_8821C_2ANT_DEFAULT_ISOLATION			15
+#define   BT_8821C_2ANT_WIFI_MAX_TX_POWER			15
+#define   BT_8821C_2ANT_BT_MAX_TX_POWER			3
+#define   BT_8821C_2ANT_WIFI_SIR_THRES1			-15
+#define   BT_8821C_2ANT_WIFI_SIR_THRES2			-30
+#define   BT_8821C_2ANT_BT_SIR_THRES1			-15
+#define   BT_8821C_2ANT_BT_SIR_THRES2			-30
+
+enum bt_8821c_2ant_signal_state {
+	BT_8821C_2ANT_GNT_SET_TO_LOW	= 0x0,
+	BT_8821C_2ANT_GNT_SET_TO_HIGH	= 0x1,
+	BT_8821C_2ANT_GNT_SET_BY_HW	= 0x2,
+	BT_8821C_2ANT_GNT_SET_MAX
+};
+
+enum bt_8821c_2ant_path_ctrl_owner {
+	BT_8821C_2ANT_PCO_BTSIDE		= 0x0,
+	BT_8821C_2ANT_PCO_WLSIDE		= 0x1,
+	BT_8821C_2ANT_PCO_MAX
+};
+
+enum bt_8821c_2ant_gnt_ctrl_type {
+	BT_8821C_2ANT_GNT_TYPE_CTRL_BY_PTA	= 0x0,
+	BT_8821C_2ANT_GNT_TYPE_CTRL_BY_SW	= 0x1,
+	BT_8821C_2ANT_GNT_TYPE_MAX
+};
+
+enum bt_8821c_2ant_gnt_ctrl_block {
+	BT_8821C_2ANT_GNT_BLOCK_RFC_BB		= 0x0,
+	BT_8821C_2ANT_GNT_BLOCK_RFC		= 0x1,
+	BT_8821C_2ANT_GNT_BLOCK_BB		= 0x2,
+	BT_8821C_2ANT_GNT_BLOCK_MAX
+};
+
+enum bt_8821c_2ant_lte_coex_table_type {
+	BT_8821C_2ANT_CTT_WL_VS_LTE		= 0x0,
+	BT_8821C_2ANT_CTT_BT_VS_LTE		= 0x1,
+	BT_8821C_2ANT_CTT_MAX
+};
+
+enum bt_8821c_2ant_lte_break_table_type {
+	BT_8821C_2ANT_LBTT_WL_BREAK_LTE		= 0x0,
+	BT_8821C_2ANT_LBTT_BT_BREAK_LTE		= 0x1,
+	BT_8821C_2ANT_LBTT_LTE_BREAK_WL		= 0x2,
+	BT_8821C_2ANT_LBTT_LTE_BREAK_BT		= 0x3,
+	BT_8821C_2ANT_LBTT_MAX
+};
+
+enum bt_info_src_8821c_2ant {
+	BT_8821C_2ANT_INFO_SRC_WIFI_FW		= 0x0,
+	BT_8821C_2ANT_INFO_SRC_BT_RSP		= 0x1,
+	BT_8821C_2ANT_INFO_SRC_BT_ACT		= 0x2,
+	BT_8821C_2ANT_INFO_SRC_MAX
+};
+
+enum bt_8821c_2ant_bt_status {
+	BT_8821C_2ANT_BSTATUS_NCON_IDLE		= 0x0,
+	BT_8821C_2ANT_BSTATUS_CON_IDLE		= 0x1,
+	BT_8821C_2ANT_BSTATUS_INQ_PAGE		= 0x2,
+	BT_8821C_2ANT_BSTATUS_ACL_BUSY		= 0x3,
+	BT_8821C_2ANT_BSTATUS_SCO_BUSY		= 0x4,
+	BT_8821C_2ANT_BSTATUS_ACL_SCO_BUSY	= 0x5,
+	BT_8821C_2ANT_BSTATUS_MAX
+};
+
+enum bt_8821c_2ant_coex_algo {
+	BT_8821C_2ANT_COEX_UNDEFINED		= 0x0,
+	BT_8821C_2ANT_COEX_SCO			= 0x1,
+	BT_8821C_2ANT_COEX_HID			= 0x2,
+	BT_8821C_2ANT_COEX_A2DP			= 0x3,
+	BT_8821C_2ANT_COEX_A2DP_PANHS		= 0x4,
+	BT_8821C_2ANT_COEX_PAN			= 0x5,
+	BT_8821C_2ANT_COEX_PANHS		= 0x6,
+	BT_8821C_2ANT_COEX_PAN_A2DP		= 0x7,
+	BT_8821C_2ANT_COEX_PAN_HID		= 0x8,
+	BT_8821C_2ANT_COEX_HID_A2DP_PAN		= 0x9,
+	BT_8821C_2ANT_COEX_HID_A2DP		= 0xa,
+	BT_8821C_2ANT_COEX_NOPROFILEBUSY	= 0xb,
+	BT_8821C_2ANT_COEX_A2DPSINK		= 0xc,
+	BT_8821C_2ANT_COEX_MAX
+};
+
+enum bt_8821c_2ant_ext_ant_switch_type {
+	BT_8821C_2ANT_USE_DPDT		= 0x0,
+	BT_8821C_2ANT_USE_SPDT		= 0x1,
+	BT_8821C_2ANT_SWITCH_NONE	= 0x2,
+	BT_8821C_2ANT_SWITCH_MAX
+};
+
+enum bt_8821c_2ant_ext_ant_switch_ctrl_type {
+	BT_8821C_2ANT_CTRL_BY_BBSW	= 0x0,
+	BT_8821C_2ANT_CTRL_BY_PTA	= 0x1,
+	BT_8821C_2ANT_CTRL_BY_ANTDIV	= 0x2,
+	BT_8821C_2ANT_CTRL_BY_MAC	= 0x3,
+	BT_8821C_2ANT_CTRL_BY_BT	= 0x4,
+	BT_8821C_2ANT_CTRL_BY_FW	= 0x5,
+	BT_8821C_2ANT_CTRL_MAX
+};
+
+enum bt_8821c_2ant_ext_ant_switch_pos_type {
+	BT_8821C_2ANT_TO_BT		= 0x0,
+	BT_8821C_2ANT_TO_WLG		= 0x1,
+	BT_8821C_2ANT_TO_WLA		= 0x2,
+	BT_8821C_2ANT_TO_NOCARE		= 0x3,
+	BT_8821C_2ANT_TO_MAX
+};
+
+enum bt_8821c_2ant_phase {
+	BT_8821C_2ANT_PHASE_INIT		= 0x0,
+	BT_8821C_2ANT_PHASE_WONLY		= 0x1,
+	BT_8821C_2ANT_PHASE_WOFF		= 0x2,
+	BT_8821C_2ANT_PHASE_2G			= 0x3,
+	BT_8821C_2ANT_PHASE_5G			= 0x4,
+	BT_8821C_2ANT_PHASE_BTMP		= 0x5,
+	BT_8821C_2ANT_PHASE_ANTDET		= 0x6,
+	BT_8821C_2ANT_PHASE_POWERON		= 0x7,
+	BT_8821C_2ANT_PHASE_MAX
+};
+
+enum bt_8821c_2ant_scoreboard {
+	BT_8821C_2ANT_SCBD_ACTIVE		= BIT(0),
+	BT_8821C_2ANT_SCBD_ONOFF		= BIT(1),
+	BT_8821C_2ANT_SCBD_SCAN			= BIT(2),
+	BT_8821C_2ANT_SCBD_UNDERTEST		= BIT(3),
+	BT_8821C_2ANT_SCBD_RXGAIN		= BIT(4),
+	BT_8821C_2ANT_SCBD_WLBUSY		= BIT(6),
+	BT_8821C_2ANT_SCBD_BTCQDDR		= BIT(10)
+};
+
+enum bt_8821c_2ant_RUNREASON {
+	BT_8821C_2ANT_RSN_2GSCANSTART		= 0x0,
+	BT_8821C_2ANT_RSN_5GSCANSTART		= 0x1,
+	BT_8821C_2ANT_RSN_SCANFINISH		= 0x2,
+	BT_8821C_2ANT_RSN_2GSWITCHBAND		= 0x3,
+	BT_8821C_2ANT_RSN_5GSWITCHBAND		= 0x4,
+	BT_8821C_2ANT_RSN_2GCONSTART		= 0x5,
+	BT_8821C_2ANT_RSN_5GCONSTART		= 0x6,
+	BT_8821C_2ANT_RSN_2GCONFINISH		= 0x7,
+	BT_8821C_2ANT_RSN_5GCONFINISH		= 0x8,
+	BT_8821C_2ANT_RSN_2GMEDIA		= 0x9,
+	BT_8821C_2ANT_RSN_5GMEDIA		= 0xa,
+	BT_8821C_2ANT_RSN_MEDIADISCON		= 0xb,
+	BT_8821C_2ANT_RSN_2GSPECIALPKT		= 0xc,
+	BT_8821C_2ANT_RSN_5GSPECIALPKT		= 0xd,
+	BT_8821C_2ANT_RSN_BTINFO		= 0xe,
+	BT_8821C_2ANT_RSN_PERIODICAL		= 0xf,
+	BT_8821C_2ANT_RSN_PNP			= 0x10,
+	BT_8821C_2ANT_RSN_MAX
+};
+
+enum bt_8821c_2ant_WL_LINK_MODE {
+	BT_8821C_2ANT_WLINK_2G1PORT		= 0x0,
+	BT_8821C_2ANT_WLINK_2GMPORT		= 0x1,
+	BT_8821C_2ANT_WLINK_25GMPORT		= 0x2,
+	BT_8821C_2ANT_WLINK_5G			= 0x3,
+	BT_8821C_2ANT_WLINK_2GGO		= 0x4,
+	BT_8821C_2ANT_WLINK_BTMR		= 0x5,
+	BT_8821C_2ANT_WLINK_MAX
+};
+
+struct coex_dm_8821c_2ant {
+	/* hw setting */
+	u32		cur_ant_pos_type;
+	/* fw mechanism */
+
+	u8		cur_bt_pwr_lvl;
+	u8		cur_wl_pwr_lvl;
+
+	boolean		cur_ignore_wlan_act;
+
+	u8		cur_ps_tdma;
+	u8		ps_tdma_para[5];
+	boolean		reset_tdma_adjust;
+	boolean		cur_ps_tdma_on;
+	boolean		cur_bt_auto_report;
+
+	/* sw mechanism */
+	boolean		cur_low_penalty_ra;
+
+	u32		cur_val0x6c0;
+	u32		cur_val0x6c4;
+	u32		cur_val0x6c8;
+	u8		cur_val0x6cc;
+
+	/* algorithm related */
+	u8		cur_algorithm;
+	u8		bt_status;
+	u8		wifi_chnl_info[3];
+
+	u8		cur_lps;
+	u8		cur_rpwm;
+
+	boolean		is_switch_to_1dot5_ant;
+	u32		arp_cnt;
+
+	u32		cur_ext_ant_switch_status;
+
+	u8		cur_antdiv_type;
+	u32		setting_tdma;
+};
+
+struct coex_sta_8821c_2ant {
+	boolean			bt_disabled;
+	boolean			bt_link_exist;
+	boolean			sco_exist;
+	boolean			a2dp_exist;
+	boolean			hid_exist;
+	boolean			pan_exist;
+	boolean			msft_mr_exist;
+
+	boolean			under_lps;
+	boolean			under_ips;
+	u32			high_priority_tx;
+	u32			high_priority_rx;
+	u32			low_priority_tx;
+	u32			low_priority_rx;
+	boolean			is_hi_pri_rx_overhead;
+	u8			bt_rssi;
+	u8			pre_bt_rssi_state;
+	u8			pre_wifi_rssi_state[4];
+	u8			bt_info_c2h[BT_8821C_2ANT_INFO_SRC_MAX][10];
+	u32			bt_info_c2h_cnt[BT_8821C_2ANT_INFO_SRC_MAX];
+	boolean			bt_whck_test;
+	boolean			c2h_bt_inquiry_page;
+	boolean			c2h_bt_remote_name_req;
+
+	u8			bt_info_ext;
+	u8			bt_info_ext2;
+	u32			pop_event_cnt;
+	u8			scan_ap_num;
+	u8			bt_retry_cnt;
+
+	u32			crc_ok_cck;
+	u32			crc_ok_11g;
+	u32			crc_ok_11n;
+	u32			crc_ok_11n_vht;
+	u32			crc_err_cck;
+	u32			crc_err_11g;
+	u32			crc_err_11n;
+	u32			crc_err_11n_vht;
+	u32			cnt_crcok_max_in_10s;
+
+	boolean			cck_lock;
+	boolean			cck_lock_ever;
+	boolean			cck_lock_warn;
+
+	u8			coex_table_type;
+	boolean			force_lps_ctrl;
+
+	u8			dis_ver_info_cnt;
+
+	u8			a2dp_bit_pool;
+	u8			cut_version;
+
+	boolean			concurrent_rx_mode_on;
+
+	u16			score_board;
+	u8			isolation_btween_wb;   /* 0~ 50 */
+	u8			wifi_coex_thres;
+	u8			bt_coex_thres;
+	u8			wifi_coex_thres2;
+	u8			bt_coex_thres2;
+
+	u8			num_of_profile;
+	boolean			acl_busy;
+	boolean			bt_create_connection;
+
+	boolean			wifi_high_pri_task1;
+	boolean			wifi_high_pri_task2;
+
+	u32			specific_pkt_period_cnt;
+	u32			bt_coex_supported_feature;
+	u32			bt_coex_supported_version;
+
+	u8			bt_ble_scan_type;
+	u32			bt_ble_scan_para[3];
+
+	boolean			run_time_state;
+	boolean			freeze_coexrun_by_btinfo;
+
+	boolean			is_A2DP_3M;
+	boolean			voice_over_HOGP;
+	u8			bt_info;
+	boolean			is_autoslot;
+	u8			forbidden_slot;
+	u8			hid_busy_num;
+	u8			hid_pair_cnt;
+
+	u32			cnt_remote_name_req;
+	u32			cnt_setup_link;
+	u32			cnt_reinit;
+	u32			cnt_ign_wlan_act;
+	u32			cnt_page;
+	u32			cnt_role_switch;
+
+	u16			bt_reg_vendor_ac;
+	u16			bt_reg_vendor_ae;
+
+	boolean			is_setup_link;
+	u8			wl_noisy_level;
+	u32			gnt_error_cnt;
+
+	u8			bt_afh_map[10];
+	u8			bt_relink_downcount;
+	boolean			is_tdma_btautoslot;
+	boolean			is_tdma_btautoslot_hang;
+
+	boolean			is_esco_mode;
+	u8			switch_band_notify_to;
+	boolean			is_rf_state_off;
+
+	boolean			is_hid_low_pri_tx_overhead;
+	boolean			is_bt_multi_link;
+	boolean			is_bt_a2dp_sink;
+	boolean			is_set_ps_state_fail;
+	u8			cnt_set_ps_state_fail;
+
+	u8			wl_fw_dbg_info[10];
+	u8			wl_rx_rate;
+	u8			wl_tx_rate;
+	u8			wl_rts_rx_rate;
+	u8			wl_center_channel;
+	u8			wl_tx_macid;
+	u8			wl_tx_retry_ratio;
+
+	u16			score_board_WB;
+	boolean			is_hid_rcu;
+	u16			legacy_forbidden_slot;
+	u16			le_forbidden_slot;
+	u8			bt_a2dp_vendor_id;
+	u32			bt_a2dp_device_name;
+	boolean			is_ble_scan_en;
+
+	boolean			is_bt_opp_exist;
+	boolean			gl_wifi_busy;
+	u8			connect_ap_period_cnt;
+
+	boolean			is_bt_reenable;
+	u8			cnt_bt_reenable;
+	boolean			is_wifi_linkscan_process;
+	u8			wl_coex_mode;
+	u8			wl_pnp_wakeup_downcnt;
+	u32			coex_run_cnt;
+};
+
+#define  BT_8821C_2ANT_EXT_BAND_SWITCH_USE_DPDT	0
+#define  BT_8821C_2ANT_EXT_BAND_SWITCH_USE_SPDT	1
+
+struct rfe_type_8821c_2ant {
+	u8		rfe_module_type;
+	boolean		ext_ant_switch_exist;
+	/* 0:DPDT, 1:SPDT */
+	u8		ext_ant_switch_type;
+	/*  iF 0: DPDT_P=0, DPDT_N=1 => BTG to Main, WL_A+G to Aux */
+	u8		ext_ant_switch_ctrl_polarity;
+
+	boolean		ext_band_switch_exist;
+	/* 0:DPDT, 1:SPDT */
+	u8		ext_band_switch_type;
+	u8		ext_band_switch_ctrl_polarity;
+
+	boolean		ant_at_main_port;
+
+	/*  If TRUE:  WLG at BTG, If FALSE: WLG at WLAG */
+	boolean		wlg_locate_at_btg;
+
+	/* If diversity on */
+	boolean		ext_ant_switch_diversity;
+};
+
+struct wifi_link_info_8821c_2ant {
+	u8				num_of_active_port;
+	u32				port_connect_status;
+	boolean				is_all_under_5g;
+	boolean				is_mcc_25g;
+	boolean				is_p2p_connected;
+};
+
+/* *******************************************
+ * The following is interface which will notify coex module.
+ * ******************************************* */
+void ex_halbtc8821c2ant_power_on_setting(struct btc_coexist *btc);
+void ex_halbtc8821c2ant_pre_load_firmware(struct btc_coexist *btc);
+void ex_halbtc8821c2ant_init_hw_config(struct btc_coexist *btc,
+				       boolean wifi_only);
+void ex_halbtc8821c2ant_init_coex_dm(struct btc_coexist *btc);
+void ex_halbtc8821c2ant_ips_notify(struct btc_coexist *btc,
+				   u8 type);
+void ex_halbtc8821c2ant_lps_notify(struct btc_coexist *btc,
+				   u8 type);
+void ex_halbtc8821c2ant_scan_notify(struct btc_coexist *btc,
+				    u8 type);
+void ex_halbtc8821c2ant_switchband_notify(struct btc_coexist *btc,
+					  u8 type);
+void ex_halbtc8821c2ant_connect_notify(struct btc_coexist *btc,
+				       u8 type);
+void ex_halbtc8821c2ant_media_status_notify(struct btc_coexist *btc,
+					    u8 type);
+void ex_halbtc8821c2ant_specific_packet_notify(struct btc_coexist *btc,
+					       u8 type);
+void ex_halbtc8821c2ant_bt_info_notify(struct btc_coexist *btc,
+				       u8 *tmp_buf,  u8 length);
+void ex_halbtc8821c2ant_wl_fwdbginfo_notify(struct btc_coexist *btc,
+					    u8 *tmp_buf, u8 length);
+void ex_halbtc8821c2ant_rx_rate_change_notify(struct btc_coexist *btc,
+					      BOOLEAN is_data_frame,
+					      u8 btc_rate_id);
+void ex_halbtc8821c2ant_tx_rate_change_notify(struct btc_coexist *btc,
+					      u8 tx_rate,
+					      u8 tx_retry_ratio, u8 macid);
+void ex_halbtc8821c2ant_rf_status_notify(struct btc_coexist *btc,
+					 u8 type);
+void ex_halbtc8821c2ant_halt_notify(struct btc_coexist *btc);
+void ex_halbtc8821c2ant_pnp_notify(struct btc_coexist *btc,
+				   u8 pnp_state);
+void ex_halbtc8821c2ant_periodical(struct btc_coexist *btc);
+void ex_halbtc8821c2ant_display_simple_coex_info(struct btc_coexist *btc);
+void ex_halbtc8821c2ant_display_coex_info(struct btc_coexist *btc);
+
+#else
+#define ex_halbtc8821c2ant_power_on_setting(btc)
+#define ex_halbtc8821c2ant_pre_load_firmware(btc)
+#define ex_halbtc8821c2ant_init_hw_config(btc, wifi_only)
+#define ex_halbtc8821c2ant_init_coex_dm(btc)
+#define ex_halbtc8821c2ant_ips_notify(btc, type)
+#define ex_halbtc8821c2ant_lps_notify(btc, type)
+#define ex_halbtc8821c2ant_scan_notify(btc, type)
+#define ex_halbtc8821c2ant_switchband_notify(btc, type)
+#define ex_halbtc8821c2ant_connect_notify(btc, type)
+#define ex_halbtc8821c2ant_media_status_notify(btc, type)
+#define ex_halbtc8821c2ant_specific_packet_notify(btc, type)
+#define ex_halbtc8821c2ant_bt_info_notify(btc, tmp_buf, length)
+#define ex_halbtc8821c2ant_wl_fwdbginfo_notify(btc, tmp_buf, length)
+#define ex_halbtc8821c2ant_rx_rate_change_notify(btc, is_data_frame,     \
+						 btc_rate_id)
+#define ex_halbtc8821c2ant_tx_rate_change_notify(btcoexist, tx_rate,     \
+						tx_retry_ratio, macid)
+#define ex_halbtc8821c2ant_rf_status_notify(btc, type)
+#define ex_halbtc8821c2ant_halt_notify(btc)
+#define ex_halbtc8821c2ant_pnp_notify(btc, pnp_state)
+#define ex_halbtc8821c2ant_periodical(btc)
+#define ex_halbtc8821c2ant_display_simple_coex_info(btc)
+#define ex_halbtc8821c2ant_display_coex_info(btc)
+#endif
+
+#endif
+
+
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/btc/halbtc8821cwifionly.c linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/btc/halbtc8821cwifionly.c
--- linux-5.6.3/3rdparty/rtl8821ce/hal/btc/halbtc8821cwifionly.c	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/btc/halbtc8821cwifionly.c	2020-04-10 16:35:06.785658620 +0300
@@ -0,0 +1,213 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2016 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#include "mp_precomp.h"
+
+static struct	rfe_type_8821c_wifi_only	gl_rfe_type_8821c_1ant;
+static struct	rfe_type_8821c_wifi_only	*rfe_type = &gl_rfe_type_8821c_1ant;
+
+
+
+VOID hal8821c_wifi_only_switch_antenna(
+	IN struct wifi_only_cfg *pwifionlycfg,
+	IN u1Byte is_5g
+	)
+{
+	boolean switch_polatiry_inverse = false;
+	u8	regval_0xcb7 = 0;
+	u8	pos_type, ctrl_type;
+
+	if (!rfe_type->ext_ant_switch_exist)
+		return;
+
+	/* swap control polarity if use different switch control polarity*/
+	/*	Normal switch polarity for DPDT, 0xcb4[29:28] = 2b'01 => BTG to Main, WLG to Aux,  0xcb4[29:28] = 2b'10 => BTG to Aux, WLG to Main */
+	/*	Normal switch polarity for SPDT, 0xcb4[29:28] = 2b'01 => Ant to BTG,  0xcb4[29:28] = 2b'10 => Ant to WLG */
+	if (rfe_type->ext_ant_switch_ctrl_polarity)
+		switch_polatiry_inverse =  !switch_polatiry_inverse;
+
+	/* swap control polarity if 1-Ant at Aux */
+	if (rfe_type->ant_at_main_port == false)
+		switch_polatiry_inverse =  !switch_polatiry_inverse;
+
+	if (is_5g)
+		pos_type = BT_8821C_WIFI_ONLY_EXT_ANT_SWITCH_TO_WLA;
+	else
+		pos_type = BT_8821C_WIFI_ONLY_EXT_ANT_SWITCH_TO_WLG;
+
+	switch (pos_type) {
+	default:
+	case BT_8821C_WIFI_ONLY_EXT_ANT_SWITCH_TO_WLA:
+
+		break;
+	case BT_8821C_WIFI_ONLY_EXT_ANT_SWITCH_TO_WLG:
+		if (!rfe_type->wlg_Locate_at_btg)
+			switch_polatiry_inverse =  !switch_polatiry_inverse;
+		break;
+	}
+
+	if (pwifionlycfg->haldata_info.ant_div_cfg)
+		ctrl_type = BT_8821C_WIFI_ONLY_EXT_ANT_SWITCH_CTRL_BY_ANTDIV;
+	else
+		ctrl_type = BT_8821C_WIFI_ONLY_EXT_ANT_SWITCH_CTRL_BY_BBSW;
+
+
+	switch (ctrl_type) {
+	default:
+	case BT_8821C_WIFI_ONLY_EXT_ANT_SWITCH_CTRL_BY_BBSW:
+		halwifionly_phy_set_bb_reg(pwifionlycfg, 0x4c,  0x01800000, 0x2);
+
+		/* BB SW, DPDT use RFE_ctrl8 and RFE_ctrl9 as control pin */
+		halwifionly_phy_set_bb_reg(pwifionlycfg, 0xcb4, 0x000000ff,	0x77);
+
+		regval_0xcb7 = (switch_polatiry_inverse == false ? 0x1 : 0x2);
+
+		/* 0xcb4[29:28] = 2b'01 for no switch_polatiry_inverse, DPDT_SEL_N =1, DPDT_SEL_P =0 */
+		halwifionly_phy_set_bb_reg(pwifionlycfg, 0xcb4, 0x30000000,	regval_0xcb7);
+		break;
+
+	case BT_8821C_WIFI_ONLY_EXT_ANT_SWITCH_CTRL_BY_ANTDIV:
+		halwifionly_phy_set_bb_reg(pwifionlycfg, 0x4c,  0x01800000, 0x2);
+
+		/* BB SW, DPDT use RFE_ctrl8 and RFE_ctrl9 as control pin */
+		halwifionly_phy_set_bb_reg(pwifionlycfg, 0xcb4, 0x000000ff,	0x88);
+
+		/* no regval_0xcb7 setup required, because	antenna switch control value by antenna diversity */
+
+		break;
+
+	}
+
+}
+
+
+VOID halbtc8821c_wifi_only_set_rfe_type(
+	IN struct wifi_only_cfg *pwifionlycfg
+	)
+{
+
+	/* the following setup should be got from Efuse in the future */
+	rfe_type->rfe_module_type = (pwifionlycfg->haldata_info.rfe_type) & 0x1f;
+
+	rfe_type->ext_ant_switch_ctrl_polarity = 0;
+
+	switch (rfe_type->rfe_module_type) {
+	case 0:
+	default:
+		rfe_type->ext_ant_switch_exist = true;
+		rfe_type->ext_ant_switch_type =
+			BT_8821C_WIFI_ONLY_EXT_ANT_SWITCH_USE_DPDT;          /*2-Ant, DPDT, WLG*/
+		rfe_type->wlg_Locate_at_btg = false;
+		rfe_type->ant_at_main_port = true;
+		break;
+	case 1:
+		rfe_type->ext_ant_switch_exist = true;
+		rfe_type->ext_ant_switch_type =
+			BT_8821C_WIFI_ONLY_EXT_ANT_SWITCH_USE_SPDT;          /*1-Ant, Main, DPDT or SPDT, WLG */
+		rfe_type->wlg_Locate_at_btg = false;
+		rfe_type->ant_at_main_port = true;
+		break;
+	case 2:
+		rfe_type->ext_ant_switch_exist = true;
+		rfe_type->ext_ant_switch_type =
+			BT_8821C_WIFI_ONLY_EXT_ANT_SWITCH_USE_SPDT;            /*1-Ant, Main, DPDT or SPDT, BTG */
+		rfe_type->wlg_Locate_at_btg = true;
+		rfe_type->ant_at_main_port = true;
+		break;
+	case 3:
+		rfe_type->ext_ant_switch_exist = true;
+		rfe_type->ext_ant_switch_type =
+			BT_8821C_WIFI_ONLY_EXT_ANT_SWITCH_USE_DPDT;          /*1-Ant, Aux, DPDT, WLG */
+		rfe_type->wlg_Locate_at_btg = false;
+		rfe_type->ant_at_main_port = false;
+		break;
+	case 4:
+		rfe_type->ext_ant_switch_exist = true;
+		rfe_type->ext_ant_switch_type =
+			BT_8821C_WIFI_ONLY_EXT_ANT_SWITCH_USE_DPDT;          /*1-Ant, Aux, DPDT, BTG */
+		rfe_type->wlg_Locate_at_btg = true;
+		rfe_type->ant_at_main_port = false;
+		break;
+	case 5:
+		rfe_type->ext_ant_switch_exist = false;					 /*2-Ant, no antenna switch, WLG*/
+		rfe_type->ext_ant_switch_type =
+			BT_8821C_WIFI_ONLY_EXT_ANT_SWITCH_NONE;
+		rfe_type->wlg_Locate_at_btg = false;
+		rfe_type->ant_at_main_port = true;
+		break;
+	case 6:
+		rfe_type->ext_ant_switch_exist = false;				 /*2-Ant, no antenna switch, WLG*/
+		rfe_type->ext_ant_switch_type =
+			BT_8821C_WIFI_ONLY_EXT_ANT_SWITCH_NONE;
+		rfe_type->wlg_Locate_at_btg = false;
+		rfe_type->ant_at_main_port = true;
+		break;
+	case 7:
+		rfe_type->ext_ant_switch_exist = true;				/*2-Ant, DPDT, BTG*/
+		rfe_type->ext_ant_switch_type =
+			BT_8821C_WIFI_ONLY_EXT_ANT_SWITCH_USE_DPDT;
+		rfe_type->wlg_Locate_at_btg = true;
+		rfe_type->ant_at_main_port = true;
+		break;
+	}
+
+}
+
+
+VOID
+ex_hal8821c_wifi_only_hw_config(
+	IN struct wifi_only_cfg *pwifionlycfg
+	)
+{
+	halbtc8821c_wifi_only_set_rfe_type(pwifionlycfg);
+
+	/* set gnt_wl, gnt_bt control owner to WL*/
+	halwifionly_phy_set_bb_reg(pwifionlycfg, 0x70, 0x400000, 0x1);
+
+	/*gnt_wl=1 , gnt_bt=0*/
+	halwifionly_phy_set_bb_reg(pwifionlycfg, 0x1704, 0xffffffff, 0x7700);
+	halwifionly_phy_set_bb_reg(pwifionlycfg, 0x1700, 0xffffffff, 0xc00f0038);
+
+	halwifionly_phy_set_bb_reg(pwifionlycfg, 0x6c0, 0xffffffff, 0xaaaaaaaa);
+	halwifionly_phy_set_bb_reg(pwifionlycfg, 0x6c4, 0xffffffff, 0xaaaaaaaa);
+}
+
+VOID
+ex_hal8821c_wifi_only_scannotify(
+	IN struct wifi_only_cfg *pwifionlycfg,
+	IN u1Byte  is_5g
+	)
+{
+	hal8821c_wifi_only_switch_antenna(pwifionlycfg, is_5g);
+}
+
+VOID
+ex_hal8821c_wifi_only_switchbandnotify(
+	IN struct wifi_only_cfg *pwifionlycfg,
+	IN u1Byte  is_5g
+	)
+{
+	hal8821c_wifi_only_switch_antenna(pwifionlycfg, is_5g);
+}
+
+VOID
+ex_hal8821c_wifi_only_connectnotify(
+	IN struct wifi_only_cfg *pwifionlycfg,
+	IN u1Byte  is_5g
+	)
+{
+	hal8821c_wifi_only_switch_antenna(pwifionlycfg, is_5g);
+}
+
+
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/btc/halbtc8821cwifionly.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/btc/halbtc8821cwifionly.h
--- linux-5.6.3/3rdparty/rtl8821ce/hal/btc/halbtc8821cwifionly.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/btc/halbtc8821cwifionly.h	2020-04-10 16:35:06.785658620 +0300
@@ -0,0 +1,89 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2016 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#ifndef __INC_HAL8821CWIFIONLYHWCFG_H
+#define __INC_HAL8821CWIFIONLYHWCFG_H
+
+
+struct rfe_type_8821c_wifi_only {
+
+	u8			rfe_module_type;
+	boolean		ext_ant_switch_exist;
+	u8			ext_ant_switch_type;			/* 0:DPDT, 1:SPDT */
+	u8			ext_ant_switch_ctrl_polarity;		/*  iF 0: DPDT_P=0, DPDT_N=1 => BTG to Main, WL_A+G to Aux */
+
+	boolean		ant_at_main_port;
+
+	boolean		wlg_Locate_at_btg;				/*  If true:  WLG at BTG, If false: WLG at WLAG */
+
+	boolean		ext_ant_switch_diversity;		/* If diversity on */
+};
+
+enum bt_8821c_wifi_only_ext_ant_switch_type {
+	BT_8821C_WIFI_ONLY_EXT_ANT_SWITCH_USE_DPDT		= 0x0,
+	BT_8821C_WIFI_ONLY_EXT_ANT_SWITCH_USE_SPDT		= 0x1,
+	BT_8821C_WIFI_ONLY_EXT_ANT_SWITCH_NONE			= 0x2,
+	BT_8821C_WIFI_ONLY_EXT_ANT_SWITCH_MAX
+};
+
+enum bt_8821c_wifi_only_ext_ant_switch_ctrl_type {
+	BT_8821C_WIFI_ONLY_EXT_ANT_SWITCH_CTRL_BY_BBSW		= 0x0,
+	BT_8821C_WIFI_ONLY_EXT_ANT_SWITCH_CTRL_BY_PTA		= 0x1,
+	BT_8821C_WIFI_ONLY_EXT_ANT_SWITCH_CTRL_BY_ANTDIV	= 0x2,
+	BT_8821C_WIFI_ONLY_EXT_ANT_SWITCH_CTRL_BY_MAC		= 0x3,
+	BT_8821C_WIFI_ONLY_EXT_ANT_SWITCH_CTRL_BY_BT		= 0x4,
+	BT_8821C_WIFI_ONLY_EXT_ANT_SWITCH_CTRL_MAX
+};
+
+enum bt_8821c_wifi_only_ext_ant_switch_pos_type {
+	BT_8821C_WIFI_ONLY_EXT_ANT_SWITCH_TO_BT				= 0x0,
+	BT_8821C_WIFI_ONLY_EXT_ANT_SWITCH_TO_WLG			= 0x1,
+	BT_8821C_WIFI_ONLY_EXT_ANT_SWITCH_TO_WLA			= 0x2,
+	BT_8821C_WIFI_ONLY_EXT_ANT_SWITCH_TO_NOCARE			= 0x3,
+	BT_8821C_WIFI_ONLY_EXT_ANT_SWITCH_TO_MAX
+};
+
+
+VOID
+hal8821c_wifi_only_switch_antenna(
+	IN struct wifi_only_cfg *pwifionlycfg,
+	IN u1Byte  is_5g
+	);
+
+VOID
+halbtc8821c_wifi_only_set_rfe_type(
+	IN struct wifi_only_cfg *pwifionlycfg
+	);
+
+
+VOID
+ex_hal8821c_wifi_only_hw_config(
+	IN struct wifi_only_cfg *pwifionlycfg
+	);
+VOID
+ex_hal8821c_wifi_only_scannotify(
+	IN struct wifi_only_cfg *pwifionlycfg,
+	IN u1Byte  is_5g
+	);
+VOID
+ex_hal8821c_wifi_only_connectnotify(
+	IN struct wifi_only_cfg *pwifionlycfg,
+	IN u1Byte  is_5g
+	);
+VOID
+ex_hal8821c_wifi_only_switchbandnotify(
+	IN struct wifi_only_cfg *pwifionlycfg,
+	IN u1Byte  is_5g
+	);
+#endif
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/btc/halbtc8822b1ant.c linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/btc/halbtc8822b1ant.c
--- linux-5.6.3/3rdparty/rtl8821ce/hal/btc/halbtc8822b1ant.c	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/btc/halbtc8822b1ant.c	2020-04-10 16:35:06.786658667 +0300
@@ -0,0 +1,7002 @@
+/* ************************************************************
+ * Description:
+ *
+ * This file is for RTL8822B Co-exist mechanism
+ *
+ * History
+ * 2012/11/15 Cosa first check in.
+ *
+ * ************************************************************ */
+
+/* ************************************************************
+ * include files
+ * ************************************************************ */
+/*only for rf4ce*/
+#include "mp_precomp.h"
+
+/*#include "mp_precomp.h" */
+
+
+#if (BT_SUPPORT == 1 && COEX_SUPPORT == 1)
+
+#if (RTL8822B_SUPPORT == 1)
+/* ************************************************************
+ * Global variables, these are static variables
+ * ************************************************************ */
+static u8	 *trace_buf = &gl_btc_trace_buf[0];
+static struct  coex_dm_8822b_1ant		glcoex_dm_8822b_1ant;
+static struct  coex_dm_8822b_1ant	*coex_dm = &glcoex_dm_8822b_1ant;
+static struct  coex_sta_8822b_1ant		glcoex_sta_8822b_1ant;
+static struct  coex_sta_8822b_1ant	*coex_sta = &glcoex_sta_8822b_1ant;
+static struct  psdscan_sta_8822b_1ant	gl_psd_scan_8822b_1ant;
+static struct  psdscan_sta_8822b_1ant *psd_scan = &gl_psd_scan_8822b_1ant;
+static struct	rfe_type_8822b_1ant		gl_rfe_type_8822b_1ant;
+static struct	rfe_type_8822b_1ant		*rfe_type = &gl_rfe_type_8822b_1ant;
+
+
+
+const char *const glbt_info_src_8822b_1ant[] = {
+	"BT Info[wifi fw]",
+	"BT Info[bt rsp]",
+	"BT Info[bt auto report]",
+};
+
+u32	glcoex_ver_date_8822b_1ant = 20161124;
+u32	glcoex_ver_8822b_1ant = 0x3f;
+u32	glcoex_ver_btdesired_8822b_1ant = 0x28;
+
+
+/* ************************************************************
+ * local function proto type if needed
+ * ************************************************************
+ * ************************************************************
+ * local function start with halbtc8822b1ant_
+ * ************************************************************ */
+u8 halbtc8822b1ant_bt_rssi_state(u8 level_num, u8 rssi_thresh, u8 rssi_thresh1)
+{
+	s32			bt_rssi = 0;
+	u8			bt_rssi_state = coex_sta->pre_bt_rssi_state;
+
+	bt_rssi = coex_sta->bt_rssi;
+
+	if (level_num == 2) {
+		if ((coex_sta->pre_bt_rssi_state == BTC_RSSI_STATE_LOW) ||
+		    (coex_sta->pre_bt_rssi_state ==
+		     BTC_RSSI_STATE_STAY_LOW)) {
+			if (bt_rssi >= (rssi_thresh +
+					BTC_RSSI_COEX_THRESH_TOL_8822B_1ANT))
+				bt_rssi_state = BTC_RSSI_STATE_HIGH;
+			else
+				bt_rssi_state = BTC_RSSI_STATE_STAY_LOW;
+		} else {
+			if (bt_rssi < rssi_thresh)
+				bt_rssi_state = BTC_RSSI_STATE_LOW;
+			else
+				bt_rssi_state = BTC_RSSI_STATE_STAY_HIGH;
+		}
+	} else if (level_num == 3) {
+		if (rssi_thresh > rssi_thresh1) {
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				    "[BTCoex], BT Rssi thresh error!!\n");
+			BTC_TRACE(trace_buf);
+			return coex_sta->pre_bt_rssi_state;
+		}
+
+		if ((coex_sta->pre_bt_rssi_state == BTC_RSSI_STATE_LOW) ||
+		    (coex_sta->pre_bt_rssi_state ==
+		     BTC_RSSI_STATE_STAY_LOW)) {
+			if (bt_rssi >= (rssi_thresh +
+					BTC_RSSI_COEX_THRESH_TOL_8822B_1ANT))
+				bt_rssi_state = BTC_RSSI_STATE_MEDIUM;
+			else
+				bt_rssi_state = BTC_RSSI_STATE_STAY_LOW;
+		} else if ((coex_sta->pre_bt_rssi_state ==
+			    BTC_RSSI_STATE_MEDIUM) ||
+			   (coex_sta->pre_bt_rssi_state ==
+			    BTC_RSSI_STATE_STAY_MEDIUM)) {
+			if (bt_rssi >= (rssi_thresh1 +
+					BTC_RSSI_COEX_THRESH_TOL_8822B_1ANT))
+				bt_rssi_state = BTC_RSSI_STATE_HIGH;
+			else if (bt_rssi < rssi_thresh)
+				bt_rssi_state = BTC_RSSI_STATE_LOW;
+			else
+				bt_rssi_state = BTC_RSSI_STATE_STAY_MEDIUM;
+		} else {
+			if (bt_rssi < rssi_thresh1)
+				bt_rssi_state = BTC_RSSI_STATE_MEDIUM;
+			else
+				bt_rssi_state = BTC_RSSI_STATE_STAY_HIGH;
+		}
+	}
+
+	coex_sta->pre_bt_rssi_state = bt_rssi_state;
+
+	return bt_rssi_state;
+}
+
+u8 halbtc8822b1ant_wifi_rssi_state(IN struct btc_coexist *btcoexist,
+	   IN u8 index, IN u8 level_num, IN u8 rssi_thresh, IN u8 rssi_thresh1)
+{
+	s32			wifi_rssi = 0;
+	u8			wifi_rssi_state = coex_sta->pre_wifi_rssi_state[index];
+
+	btcoexist->btc_get(btcoexist, BTC_GET_S4_WIFI_RSSI, &wifi_rssi);
+
+	if (level_num == 2) {
+		if ((coex_sta->pre_wifi_rssi_state[index] == BTC_RSSI_STATE_LOW)
+		    ||
+		    (coex_sta->pre_wifi_rssi_state[index] ==
+		     BTC_RSSI_STATE_STAY_LOW)) {
+			if (wifi_rssi >= (rssi_thresh +
+					  BTC_RSSI_COEX_THRESH_TOL_8822B_1ANT))
+				wifi_rssi_state = BTC_RSSI_STATE_HIGH;
+			else
+				wifi_rssi_state = BTC_RSSI_STATE_STAY_LOW;
+		} else {
+			if (wifi_rssi < rssi_thresh)
+				wifi_rssi_state = BTC_RSSI_STATE_LOW;
+			else
+				wifi_rssi_state = BTC_RSSI_STATE_STAY_HIGH;
+		}
+	} else if (level_num == 3) {
+		if (rssi_thresh > rssi_thresh1) {
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				    "[BTCoex], wifi RSSI thresh error!!\n");
+			BTC_TRACE(trace_buf);
+			return coex_sta->pre_wifi_rssi_state[index];
+		}
+
+		if ((coex_sta->pre_wifi_rssi_state[index] == BTC_RSSI_STATE_LOW)
+		    ||
+		    (coex_sta->pre_wifi_rssi_state[index] ==
+		     BTC_RSSI_STATE_STAY_LOW)) {
+			if (wifi_rssi >= (rssi_thresh +
+					  BTC_RSSI_COEX_THRESH_TOL_8822B_1ANT))
+				wifi_rssi_state = BTC_RSSI_STATE_MEDIUM;
+			else
+				wifi_rssi_state = BTC_RSSI_STATE_STAY_LOW;
+		} else if ((coex_sta->pre_wifi_rssi_state[index] ==
+			    BTC_RSSI_STATE_MEDIUM) ||
+			   (coex_sta->pre_wifi_rssi_state[index] ==
+			    BTC_RSSI_STATE_STAY_MEDIUM)) {
+			if (wifi_rssi >= (rssi_thresh1 +
+					  BTC_RSSI_COEX_THRESH_TOL_8822B_1ANT))
+				wifi_rssi_state = BTC_RSSI_STATE_HIGH;
+			else if (wifi_rssi < rssi_thresh)
+				wifi_rssi_state = BTC_RSSI_STATE_LOW;
+			else
+				wifi_rssi_state = BTC_RSSI_STATE_STAY_MEDIUM;
+		} else {
+			if (wifi_rssi < rssi_thresh1)
+				wifi_rssi_state = BTC_RSSI_STATE_MEDIUM;
+			else
+				wifi_rssi_state = BTC_RSSI_STATE_STAY_HIGH;
+		}
+	}
+
+	coex_sta->pre_wifi_rssi_state[index] = wifi_rssi_state;
+
+	return wifi_rssi_state;
+}
+
+void halbtc8822b1ant_update_ra_mask(IN struct btc_coexist *btcoexist,
+				    IN boolean force_exec, IN u32 dis_rate_mask)
+{
+	coex_dm->cur_ra_mask = dis_rate_mask;
+
+	if (force_exec || (coex_dm->pre_ra_mask != coex_dm->cur_ra_mask))
+		btcoexist->btc_set(btcoexist, BTC_SET_ACT_UPDATE_RAMASK,
+				   &coex_dm->cur_ra_mask);
+	coex_dm->pre_ra_mask = coex_dm->cur_ra_mask;
+}
+
+void halbtc8822b1ant_auto_rate_fallback_retry(IN struct btc_coexist *btcoexist,
+		IN boolean force_exec, IN u8 type)
+{
+	boolean	wifi_under_b_mode = false;
+
+	coex_dm->cur_arfr_type = type;
+
+	if (force_exec || (coex_dm->pre_arfr_type != coex_dm->cur_arfr_type)) {
+		switch (coex_dm->cur_arfr_type) {
+		case 0:	/* normal mode */
+			btcoexist->btc_write_4byte(btcoexist, 0x430,
+						   coex_dm->backup_arfr_cnt1);
+			btcoexist->btc_write_4byte(btcoexist, 0x434,
+						   coex_dm->backup_arfr_cnt2);
+			break;
+		case 1:
+			btcoexist->btc_get(btcoexist,
+					   BTC_GET_BL_WIFI_UNDER_B_MODE,
+					   &wifi_under_b_mode);
+			if (wifi_under_b_mode) {
+				btcoexist->btc_write_4byte(btcoexist,
+							   0x430, 0x0);
+				btcoexist->btc_write_4byte(btcoexist,
+							   0x434, 0x01010101);
+			} else {
+				btcoexist->btc_write_4byte(btcoexist,
+							   0x430, 0x0);
+				btcoexist->btc_write_4byte(btcoexist,
+							   0x434, 0x04030201);
+			}
+			break;
+		default:
+			break;
+		}
+	}
+
+	coex_dm->pre_arfr_type = coex_dm->cur_arfr_type;
+}
+
+void halbtc8822b1ant_retry_limit(IN struct btc_coexist *btcoexist,
+				 IN boolean force_exec, IN u8 type)
+{
+	coex_dm->cur_retry_limit_type = type;
+
+	if (force_exec ||
+	    (coex_dm->pre_retry_limit_type !=
+	     coex_dm->cur_retry_limit_type)) {
+		switch (coex_dm->cur_retry_limit_type) {
+		case 0:	/* normal mode */
+			btcoexist->btc_write_2byte(btcoexist, 0x42a,
+						   coex_dm->backup_retry_limit);
+			break;
+		case 1:	/* retry limit=8 */
+			btcoexist->btc_write_2byte(btcoexist, 0x42a,
+						   0x0808);
+			break;
+		default:
+			break;
+		}
+	}
+
+	coex_dm->pre_retry_limit_type = coex_dm->cur_retry_limit_type;
+}
+
+void halbtc8822b1ant_ampdu_max_time(IN struct btc_coexist *btcoexist,
+				    IN boolean force_exec, IN u8 type)
+{
+	coex_dm->cur_ampdu_time_type = type;
+
+	if (force_exec ||
+	    (coex_dm->pre_ampdu_time_type != coex_dm->cur_ampdu_time_type)) {
+		switch (coex_dm->cur_ampdu_time_type) {
+		case 0:	/* normal mode */
+			btcoexist->btc_write_1byte(btcoexist, 0x456,
+					   coex_dm->backup_ampdu_max_time);
+			break;
+		case 1:	/* AMPDU timw = 0x38 * 32us */
+			btcoexist->btc_write_1byte(btcoexist, 0x456,
+						   0x38);
+			break;
+		default:
+			break;
+		}
+	}
+
+	coex_dm->pre_ampdu_time_type = coex_dm->cur_ampdu_time_type;
+}
+
+void halbtc8822b1ant_limited_tx(IN struct btc_coexist *btcoexist,
+		IN boolean force_exec, IN u8 ra_mask_type, IN u8 arfr_type,
+				IN u8 retry_limit_type, IN u8 ampdu_time_type)
+{
+	switch (ra_mask_type) {
+	case 0:	/* normal mode */
+		halbtc8822b1ant_update_ra_mask(btcoexist, force_exec,
+					       0x0);
+		break;
+	case 1:	/* disable cck 1/2 */
+		halbtc8822b1ant_update_ra_mask(btcoexist, force_exec,
+					       0x00000003);
+		break;
+	case 2:	/* disable cck 1/2/5.5, ofdm 6/9/12/18/24, mcs 0/1/2/3/4 */
+		halbtc8822b1ant_update_ra_mask(btcoexist, force_exec,
+					       0x0001f1f7);
+		break;
+	default:
+		break;
+	}
+
+	halbtc8822b1ant_auto_rate_fallback_retry(btcoexist, force_exec,
+			arfr_type);
+	halbtc8822b1ant_retry_limit(btcoexist, force_exec, retry_limit_type);
+	halbtc8822b1ant_ampdu_max_time(btcoexist, force_exec, ampdu_time_type);
+}
+
+/*
+rx agg size setting :
+1:      true / don't care / don't care
+max: false / false / don't care
+7:     false / true / 7
+*/
+
+void halbtc8822b1ant_limited_rx(IN struct btc_coexist *btcoexist,
+			IN boolean force_exec, IN boolean rej_ap_agg_pkt,
+			IN boolean bt_ctrl_agg_buf_size, IN u8 agg_buf_size)
+{
+	boolean	reject_rx_agg = rej_ap_agg_pkt;
+	boolean	bt_ctrl_rx_agg_size = bt_ctrl_agg_buf_size;
+	u8	rx_agg_size = agg_buf_size;
+
+	/* ============================================ */
+	/*	Rx Aggregation related setting */
+	/* ============================================ */
+	btcoexist->btc_set(btcoexist, BTC_SET_BL_TO_REJ_AP_AGG_PKT,
+			   &reject_rx_agg);
+	/* decide BT control aggregation buf size or not */
+	btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_CTRL_AGG_SIZE,
+			   &bt_ctrl_rx_agg_size);
+	/* aggregation buf size, only work when BT control Rx aggregation size. */
+	btcoexist->btc_set(btcoexist, BTC_SET_U1_AGG_BUF_SIZE, &rx_agg_size);
+	/* real update aggregation setting */
+	btcoexist->btc_set(btcoexist, BTC_SET_ACT_AGGREGATE_CTRL, NULL);
+
+
+}
+
+void halbtc8822b1ant_query_bt_info(IN struct btc_coexist *btcoexist)
+{
+	u8			h2c_parameter[1] = {0};
+
+	coex_sta->c2h_bt_info_req_sent = true;
+
+	h2c_parameter[0] |= BIT(0);	/* trigger */
+
+	btcoexist->btc_fill_h2c(btcoexist, 0x61, 1, h2c_parameter);
+}
+
+void halbtc8822b1ant_monitor_bt_ctr(IN struct btc_coexist *btcoexist)
+{
+	u32			reg_hp_txrx, reg_lp_txrx, u32tmp;
+	u32			reg_hp_tx = 0, reg_hp_rx = 0, reg_lp_tx = 0, reg_lp_rx = 0;
+	static u8		num_of_bt_counter_chk = 0, cnt_slave = 0;
+	struct  btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
+
+	/* to avoid 0x76e[3] = 1 (WLAN_Act control by PTA) during IPS */
+	/* if (! (btcoexist->btc_read_1byte(btcoexist, 0x76e) & 0x8) ) */
+
+	if (coex_sta->under_ips) {
+		/* coex_sta->high_priority_tx = 65535; */
+		/* coex_sta->high_priority_rx = 65535; */
+		/* coex_sta->low_priority_tx = 65535; */
+		/* coex_sta->low_priority_rx = 65535; */
+		/* return; */
+	}
+
+	reg_hp_txrx = 0x770;
+	reg_lp_txrx = 0x774;
+
+	u32tmp = btcoexist->btc_read_4byte(btcoexist, reg_hp_txrx);
+	reg_hp_tx = u32tmp & MASKLWORD;
+	reg_hp_rx = (u32tmp & MASKHWORD) >> 16;
+
+	u32tmp = btcoexist->btc_read_4byte(btcoexist, reg_lp_txrx);
+	reg_lp_tx = u32tmp & MASKLWORD;
+	reg_lp_rx = (u32tmp & MASKHWORD) >> 16;
+
+	coex_sta->high_priority_tx = reg_hp_tx;
+	coex_sta->high_priority_rx = reg_hp_rx;
+	coex_sta->low_priority_tx = reg_lp_tx;
+	coex_sta->low_priority_rx = reg_lp_rx;
+
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+		    "[BTCoex], Hi-Pri Rx/Tx: %d/%d, Lo-Pri Rx/Tx: %d/%d\n",
+		    reg_hp_rx, reg_hp_tx, reg_lp_rx, reg_lp_tx);
+	BTC_TRACE(trace_buf);
+
+	/* reset counter */
+	btcoexist->btc_write_1byte(btcoexist, 0x76e, 0xc);
+
+	if ((coex_sta->low_priority_tx > 1150)  &&
+	    (!coex_sta->c2h_bt_inquiry_page))
+		coex_sta->pop_event_cnt++;
+
+	if ((coex_sta->low_priority_rx >= 1150) &&
+	    (coex_sta->low_priority_rx >= coex_sta->low_priority_tx)
+	    && (!coex_sta->under_ips)  &&
+	    (!coex_sta->c2h_bt_inquiry_page) &&
+	    (coex_sta->bt_link_exist))	{
+		if (cnt_slave >= 3) {
+			bt_link_info->slave_role = true;
+			cnt_slave = 3;
+		} else
+			cnt_slave++;
+	} else {
+		if (cnt_slave == 0)	{
+			bt_link_info->slave_role = false;
+			cnt_slave = 0;
+		} else
+			cnt_slave--;
+
+	}
+
+	if ((coex_sta->high_priority_tx == 0) &&
+	    (coex_sta->high_priority_rx == 0) &&
+	    (coex_sta->low_priority_tx == 0) &&
+	    (coex_sta->low_priority_rx == 0)) {
+		num_of_bt_counter_chk++;
+
+		if (num_of_bt_counter_chk >= 3) {
+			halbtc8822b1ant_query_bt_info(
+				btcoexist);
+			num_of_bt_counter_chk = 0;
+		}
+	}
+#if 0
+	/* Add Hi-Pri Tx/Rx counter to avoid false detection */
+	if (((coex_sta->hid_exist) || (coex_sta->sco_exist)) &&
+	    (coex_sta->high_priority_tx + coex_sta->high_priority_rx
+	     >= 160)
+	    && (!coex_sta->c2h_bt_inquiry_page))
+		coex_sta->bt_hi_pri_link_exist = true;
+	else
+		coex_sta->bt_hi_pri_link_exist = false;
+
+	if ((coex_sta->acl_busy) &&
+	    (coex_sta->num_of_profile == 0)) {
+		if (coex_sta->low_priority_tx +
+		    coex_sta->low_priority_rx >= 160) {
+			coex_sta->pan_exist = true;
+			coex_sta->num_of_profile++;
+			coex_sta->wrong_profile_notification++;
+		}
+	}
+#endif
+
+}
+
+
+void halbtc8822b1ant_monitor_wifi_ctr(IN struct btc_coexist *btcoexist)
+{
+	s32 wifi_rssi = 0;
+	boolean wifi_busy = false, wifi_under_b_mode = false;
+	static u8 cck_lock_counter = 0;
+	u32 total_cnt;
+
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy);
+	btcoexist->btc_get(btcoexist, BTC_GET_S4_WIFI_RSSI, &wifi_rssi);
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_B_MODE,
+			   &wifi_under_b_mode);
+
+	if (coex_sta->under_ips) {
+		coex_sta->crc_ok_cck = 0;
+		coex_sta->crc_ok_11g = 0;
+		coex_sta->crc_ok_11n = 0;
+		coex_sta->crc_ok_11n_agg = 0;
+
+		coex_sta->crc_err_cck = 0;
+		coex_sta->crc_err_11g = 0;
+		coex_sta->crc_err_11n = 0;
+		coex_sta->crc_err_11n_agg = 0;
+	} else {
+		coex_sta->crc_ok_cck	= btcoexist->btc_read_2byte(
+						  btcoexist,
+						  0xf04);
+		coex_sta->crc_ok_11g	= btcoexist->btc_read_2byte(
+						  btcoexist,
+						  0xf14);
+		coex_sta->crc_ok_11n	= btcoexist->btc_read_2byte(
+						  btcoexist,
+						  0xf10);
+		coex_sta->crc_ok_11n_agg = btcoexist->btc_read_2byte(
+						   btcoexist,
+						   0xf0c);
+
+		coex_sta->crc_err_cck	 = btcoexist->btc_read_2byte(
+			   btcoexist, 0xf00) +  btcoexist->btc_read_2byte(
+						   btcoexist, 0xf06);
+
+		coex_sta->crc_err_11g	 = btcoexist->btc_read_2byte(
+						   btcoexist,
+						   0xf16);
+		coex_sta->crc_err_11n	 = btcoexist->btc_read_2byte(
+						   btcoexist,
+						   0xf12);
+		coex_sta->crc_err_11n_agg = btcoexist->btc_read_2byte(
+						    btcoexist,
+						    0xf0e);
+	}
+
+
+	/* reset counter */
+	btcoexist->btc_write_1byte_bitmask(btcoexist, 0xb58, 0x1, 0x1);
+	btcoexist->btc_write_1byte_bitmask(btcoexist, 0xb58, 0x1, 0x0);
+
+	if ((wifi_busy) && (wifi_rssi >= 30) && (!wifi_under_b_mode)) {
+		total_cnt = coex_sta->crc_ok_cck + coex_sta->crc_ok_11g
+			    +
+			    coex_sta->crc_ok_11n +
+			    coex_sta->crc_ok_11n_agg;
+
+		if ((coex_dm->bt_status ==
+		     BT_8822B_1ANT_BT_STATUS_ACL_BUSY) ||
+		    (coex_dm->bt_status ==
+		     BT_8822B_1ANT_BT_STATUS_ACL_SCO_BUSY) ||
+		    (coex_dm->bt_status ==
+		     BT_8822B_1ANT_BT_STATUS_SCO_BUSY)) {
+			if (coex_sta->crc_ok_cck > (total_cnt -
+						    coex_sta->crc_ok_cck)) {
+				if (cck_lock_counter < 3)
+					cck_lock_counter++;
+			} else {
+				if (cck_lock_counter > 0)
+					cck_lock_counter--;
+			}
+
+		} else {
+			if (cck_lock_counter > 0)
+				cck_lock_counter--;
+		}
+	} else {
+		if (cck_lock_counter > 0)
+			cck_lock_counter--;
+	}
+
+	if (!coex_sta->pre_ccklock) {
+
+		if (cck_lock_counter >= 3)
+			coex_sta->cck_lock = true;
+		else
+			coex_sta->cck_lock = false;
+	} else {
+		if (cck_lock_counter == 0)
+			coex_sta->cck_lock = false;
+		else
+			coex_sta->cck_lock = true;
+	}
+
+	if (coex_sta->cck_lock)
+		coex_sta->cck_ever_lock = true;
+
+	coex_sta->pre_ccklock =  coex_sta->cck_lock;
+
+
+}
+
+
+boolean halbtc8822b1ant_is_wifi_status_changed(IN struct btc_coexist *btcoexist)
+{
+	static boolean	pre_wifi_busy = false, pre_under_4way = false,
+			pre_bt_hs_on = false, pre_rf4ce_enabled = false, pre_bt_off = false;
+	boolean wifi_busy = false, under_4way = false, bt_hs_on = false, rf4ce_enabled = false;
+	boolean wifi_connected = false;
+
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED,
+			   &wifi_connected);
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy);
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on);
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_4_WAY_PROGRESS,
+			   &under_4way);
+
+	if (coex_sta->bt_disabled != pre_bt_off) {
+		pre_bt_off = coex_sta->bt_disabled;
+
+		if (coex_sta->bt_disabled)
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				    "[BTCoex], BT is disabled !!\n");
+		else
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				    "[BTCoex], BT is enabled !!\n");
+
+		BTC_TRACE(trace_buf);
+
+		coex_sta->bt_coex_supported_feature = 0;
+		coex_sta->bt_coex_supported_version = 0;
+		return true;
+	}
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_RF4CE_CONNECTED, &rf4ce_enabled);
+
+		if (rf4ce_enabled != pre_rf4ce_enabled) {
+		pre_rf4ce_enabled = rf4ce_enabled;
+
+		if (rf4ce_enabled)
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				    "[BTCoex], rf4ce is enabled !!\n");
+		else
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				    "[BTCoex], rf4ce is disabled !!\n");
+
+		BTC_TRACE(trace_buf);
+
+
+		return true;
+	}
+
+	if (wifi_connected) {
+		if (wifi_busy != pre_wifi_busy) {
+			pre_wifi_busy = wifi_busy;
+			return true;
+		}
+		if (under_4way != pre_under_4way) {
+			pre_under_4way = under_4way;
+			return true;
+		}
+		if (bt_hs_on != pre_bt_hs_on) {
+			pre_bt_hs_on = bt_hs_on;
+			return true;
+		}
+	}
+
+	return false;
+}
+
+void halbtc8822b1ant_update_bt_link_info(IN struct btc_coexist *btcoexist)
+{
+	struct  btc_bt_link_info	*bt_link_info = &btcoexist->bt_link_info;
+	boolean				bt_hs_on = false;
+
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on);
+
+	bt_link_info->bt_link_exist = coex_sta->bt_link_exist;
+	bt_link_info->sco_exist = coex_sta->sco_exist;
+	bt_link_info->a2dp_exist = coex_sta->a2dp_exist;
+	bt_link_info->pan_exist = coex_sta->pan_exist;
+	bt_link_info->hid_exist = coex_sta->hid_exist;
+	bt_link_info->bt_hi_pri_link_exist = coex_sta->bt_hi_pri_link_exist;
+	bt_link_info->acl_busy = coex_sta->acl_busy;
+
+	/* work around for HS mode. */
+	if (bt_hs_on) {
+		bt_link_info->pan_exist = true;
+		bt_link_info->bt_link_exist = true;
+	}
+
+	/* check if Sco only */
+	if (bt_link_info->sco_exist &&
+	    !bt_link_info->a2dp_exist &&
+	    !bt_link_info->pan_exist &&
+	    !bt_link_info->hid_exist)
+		bt_link_info->sco_only = true;
+	else
+		bt_link_info->sco_only = false;
+
+	/* check if A2dp only */
+	if (!bt_link_info->sco_exist &&
+	    bt_link_info->a2dp_exist &&
+	    !bt_link_info->pan_exist &&
+	    !bt_link_info->hid_exist)
+		bt_link_info->a2dp_only = true;
+	else
+		bt_link_info->a2dp_only = false;
+
+	/* check if Pan only */
+	if (!bt_link_info->sco_exist &&
+	    !bt_link_info->a2dp_exist &&
+	    bt_link_info->pan_exist &&
+	    !bt_link_info->hid_exist)
+		bt_link_info->pan_only = true;
+	else
+		bt_link_info->pan_only = false;
+
+	/* check if Hid only */
+	if (!bt_link_info->sco_exist &&
+	    !bt_link_info->a2dp_exist &&
+	    !bt_link_info->pan_exist &&
+	    bt_link_info->hid_exist)
+		bt_link_info->hid_only = true;
+	else
+		bt_link_info->hid_only = false;
+}
+
+void halbtc8822b1ant_update_wifi_channel_info(IN struct btc_coexist *btcoexist,
+		IN u8 type)
+{
+	u8			h2c_parameter[3] = {0};
+	u32			wifi_bw;
+	u8			wifi_central_chnl;
+
+	/* only 2.4G we need to inform bt the chnl mask */
+	btcoexist->btc_get(btcoexist, BTC_GET_U1_WIFI_CENTRAL_CHNL,
+			   &wifi_central_chnl);
+	if ((BTC_MEDIA_CONNECT == type) &&
+	    (wifi_central_chnl <= 14)) {
+
+		h2c_parameter[0] =
+			0x1;  /* enable BT AFH skip WL channel for 8822b because BT Rx LO interference */
+		h2c_parameter[1] = wifi_central_chnl;
+
+		btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw);
+
+		if (BTC_WIFI_BW_HT40 == wifi_bw)
+			h2c_parameter[2] = 0x30;
+		else
+			h2c_parameter[2] = 0x20;
+	}
+
+	coex_dm->wifi_chnl_info[0] = h2c_parameter[0];
+	coex_dm->wifi_chnl_info[1] = h2c_parameter[1];
+	coex_dm->wifi_chnl_info[2] = h2c_parameter[2];
+
+	btcoexist->btc_fill_h2c(btcoexist, 0x66, 3, h2c_parameter);
+
+}
+
+u8 halbtc8822b1ant_action_algorithm(IN struct btc_coexist *btcoexist)
+{
+	struct  btc_bt_link_info	*bt_link_info = &btcoexist->bt_link_info;
+	boolean				bt_hs_on = false;
+	u8				algorithm = BT_8822B_1ANT_COEX_ALGO_UNDEFINED;
+	u8				num_of_diff_profile = 0;
+
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on);
+
+	if (!bt_link_info->bt_link_exist) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], No BT link exists!!!\n");
+		BTC_TRACE(trace_buf);
+		return algorithm;
+	}
+
+	if (bt_link_info->sco_exist)
+		num_of_diff_profile++;
+	if (bt_link_info->hid_exist)
+		num_of_diff_profile++;
+	if (bt_link_info->pan_exist)
+		num_of_diff_profile++;
+	if (bt_link_info->a2dp_exist)
+		num_of_diff_profile++;
+
+	if (num_of_diff_profile == 1) {
+		if (bt_link_info->sco_exist) {
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				    "[BTCoex], BT Profile = SCO only\n");
+			BTC_TRACE(trace_buf);
+			algorithm = BT_8822B_1ANT_COEX_ALGO_SCO;
+		} else {
+			if (bt_link_info->hid_exist) {
+				BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+					"[BTCoex], BT Profile = HID only\n");
+				BTC_TRACE(trace_buf);
+				algorithm = BT_8822B_1ANT_COEX_ALGO_HID;
+			} else if (bt_link_info->a2dp_exist) {
+				BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+					"[BTCoex], BT Profile = A2DP only\n");
+				BTC_TRACE(trace_buf);
+				algorithm = BT_8822B_1ANT_COEX_ALGO_A2DP;
+			} else if (bt_link_info->pan_exist) {
+				if (bt_hs_on) {
+					BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+						"[BTCoex], BT Profile = PAN(HS) only\n");
+					BTC_TRACE(trace_buf);
+					algorithm =
+						BT_8822B_1ANT_COEX_ALGO_PANHS;
+				} else {
+					BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+						"[BTCoex], BT Profile = PAN(EDR) only\n");
+					BTC_TRACE(trace_buf);
+					algorithm =
+						BT_8822B_1ANT_COEX_ALGO_PANEDR;
+				}
+			}
+		}
+	} else if (num_of_diff_profile == 2) {
+		if (bt_link_info->sco_exist) {
+			if (bt_link_info->hid_exist) {
+				BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+					"[BTCoex], BT Profile = SCO + HID\n");
+				BTC_TRACE(trace_buf);
+				algorithm = BT_8822B_1ANT_COEX_ALGO_HID;
+			} else if (bt_link_info->a2dp_exist) {
+				BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+					"[BTCoex], BT Profile = SCO + A2DP ==> SCO\n");
+				BTC_TRACE(trace_buf);
+				algorithm = BT_8822B_1ANT_COEX_ALGO_SCO;
+			} else if (bt_link_info->pan_exist) {
+				if (bt_hs_on) {
+					BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+						"[BTCoex], BT Profile = SCO + PAN(HS)\n");
+					BTC_TRACE(trace_buf);
+					algorithm = BT_8822B_1ANT_COEX_ALGO_SCO;
+				} else {
+					BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+						"[BTCoex], BT Profile = SCO + PAN(EDR)\n");
+					BTC_TRACE(trace_buf);
+					algorithm =
+						BT_8822B_1ANT_COEX_ALGO_PANEDR_HID;
+				}
+			}
+		} else {
+			if (bt_link_info->hid_exist &&
+			    bt_link_info->a2dp_exist) {
+				BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+					"[BTCoex], BT Profile = HID + A2DP\n");
+				BTC_TRACE(trace_buf);
+				algorithm = BT_8822B_1ANT_COEX_ALGO_HID_A2DP;
+			} else if (bt_link_info->hid_exist &&
+				   bt_link_info->pan_exist) {
+				if (bt_hs_on) {
+					BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+						"[BTCoex], BT Profile = HID + PAN(HS)\n");
+					BTC_TRACE(trace_buf);
+					algorithm =
+						BT_8822B_1ANT_COEX_ALGO_HID_A2DP;
+				} else {
+					BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+						"[BTCoex], BT Profile = HID + PAN(EDR)\n");
+					BTC_TRACE(trace_buf);
+					algorithm =
+						BT_8822B_1ANT_COEX_ALGO_PANEDR_HID;
+				}
+			} else if (bt_link_info->pan_exist &&
+				   bt_link_info->a2dp_exist) {
+				if (bt_hs_on) {
+					BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+						"[BTCoex], BT Profile = A2DP + PAN(HS)\n");
+					BTC_TRACE(trace_buf);
+					algorithm =
+						BT_8822B_1ANT_COEX_ALGO_A2DP_PANHS;
+				} else {
+					BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+						"[BTCoex], BT Profile = A2DP + PAN(EDR)\n");
+					BTC_TRACE(trace_buf);
+					algorithm =
+						BT_8822B_1ANT_COEX_ALGO_PANEDR_A2DP;
+				}
+			}
+		}
+	} else if (num_of_diff_profile == 3) {
+		if (bt_link_info->sco_exist) {
+			if (bt_link_info->hid_exist &&
+			    bt_link_info->a2dp_exist) {
+				BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+					"[BTCoex], BT Profile = SCO + HID + A2DP ==> HID\n");
+				BTC_TRACE(trace_buf);
+				algorithm = BT_8822B_1ANT_COEX_ALGO_HID;
+			} else if (bt_link_info->hid_exist &&
+				   bt_link_info->pan_exist) {
+				if (bt_hs_on) {
+					BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+						"[BTCoex], BT Profile = SCO + HID + PAN(HS)\n");
+					BTC_TRACE(trace_buf);
+					algorithm =
+						BT_8822B_1ANT_COEX_ALGO_HID_A2DP;
+				} else {
+					BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+						"[BTCoex], BT Profile = SCO + HID + PAN(EDR)\n");
+					BTC_TRACE(trace_buf);
+					algorithm =
+						BT_8822B_1ANT_COEX_ALGO_PANEDR_HID;
+				}
+			} else if (bt_link_info->pan_exist &&
+				   bt_link_info->a2dp_exist) {
+				if (bt_hs_on) {
+					BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+						"[BTCoex], BT Profile = SCO + A2DP + PAN(HS)\n");
+					BTC_TRACE(trace_buf);
+					algorithm = BT_8822B_1ANT_COEX_ALGO_SCO;
+				} else {
+					BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+						"[BTCoex], BT Profile = SCO + A2DP + PAN(EDR) ==> HID\n");
+					BTC_TRACE(trace_buf);
+					algorithm =
+						BT_8822B_1ANT_COEX_ALGO_PANEDR_HID;
+				}
+			}
+		} else {
+			if (bt_link_info->hid_exist &&
+			    bt_link_info->pan_exist &&
+			    bt_link_info->a2dp_exist) {
+				if (bt_hs_on) {
+					BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+						"[BTCoex], BT Profile = HID + A2DP + PAN(HS)\n");
+					BTC_TRACE(trace_buf);
+					algorithm =
+						BT_8822B_1ANT_COEX_ALGO_HID_A2DP;
+				} else {
+					BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+						"[BTCoex], BT Profile = HID + A2DP + PAN(EDR)\n");
+					BTC_TRACE(trace_buf);
+					algorithm =
+						BT_8822B_1ANT_COEX_ALGO_HID_A2DP_PANEDR;
+				}
+			}
+		}
+	} else if (num_of_diff_profile >= 3) {
+		if (bt_link_info->sco_exist) {
+			if (bt_link_info->hid_exist &&
+			    bt_link_info->pan_exist &&
+			    bt_link_info->a2dp_exist) {
+				if (bt_hs_on) {
+					BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+						"[BTCoex], Error!!! BT Profile = SCO + HID + A2DP + PAN(HS)\n");
+					BTC_TRACE(trace_buf);
+
+				} else {
+					BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+						"[BTCoex], BT Profile = SCO + HID + A2DP + PAN(EDR)==>PAN(EDR)+HID\n");
+					BTC_TRACE(trace_buf);
+					algorithm =
+						BT_8822B_1ANT_COEX_ALGO_PANEDR_HID;
+				}
+			}
+		}
+	}
+
+	return algorithm;
+}
+
+void halbtc8822b1ant_set_bt_auto_report(IN struct btc_coexist *btcoexist,
+					IN boolean enable_auto_report)
+{
+	u8			h2c_parameter[1] = {0};
+
+	h2c_parameter[0] = 0;
+
+	if (enable_auto_report)
+		h2c_parameter[0] |= BIT(0);
+
+	btcoexist->btc_fill_h2c(btcoexist, 0x68, 1, h2c_parameter);
+}
+
+void halbtc8822b1ant_bt_auto_report(IN struct btc_coexist *btcoexist,
+		    IN boolean force_exec, IN boolean enable_auto_report)
+{
+	coex_dm->cur_bt_auto_report = enable_auto_report;
+
+	if (!force_exec) {
+		if (coex_dm->pre_bt_auto_report == coex_dm->cur_bt_auto_report)
+			return;
+	}
+	halbtc8822b1ant_set_bt_auto_report(btcoexist,
+					   coex_dm->cur_bt_auto_report);
+
+	coex_dm->pre_bt_auto_report = coex_dm->cur_bt_auto_report;
+}
+
+
+
+void halbtc8822b1ant_set_sw_penalty_tx_rate_adaptive(IN struct btc_coexist
+		*btcoexist, IN boolean low_penalty_ra)
+{
+	u8			h2c_parameter[6] = {0};
+
+	h2c_parameter[0] = 0x6;	/* op_code, 0x6= Retry_Penalty */
+
+	if (low_penalty_ra) {
+		h2c_parameter[1] |= BIT(0);
+		h2c_parameter[2] =
+			0x00;  /* normal rate except MCS7/6/5, OFDM54/48/36 */
+		h2c_parameter[3] = 0xf7;  /* MCS7 or OFDM54 */
+		h2c_parameter[4] = 0xf8;  /* MCS6 or OFDM48 */
+		h2c_parameter[5] = 0xf9;	/* MCS5 or OFDM36	 */
+	}
+
+	btcoexist->btc_fill_h2c(btcoexist, 0x69, 6, h2c_parameter);
+}
+
+void halbtc8822b1ant_low_penalty_ra(IN struct btc_coexist *btcoexist,
+			    IN boolean force_exec, IN boolean low_penalty_ra)
+{
+#if 1
+	coex_dm->cur_low_penalty_ra = low_penalty_ra;
+
+	if (!force_exec) {
+		if (coex_dm->pre_low_penalty_ra ==
+		    coex_dm->cur_low_penalty_ra)
+			return;
+	}
+
+	if (low_penalty_ra)
+		btcoexist->btc_phydm_modify_RA_PCR_threshold(btcoexist, 0, 25);
+	else
+		btcoexist->btc_phydm_modify_RA_PCR_threshold(btcoexist, 0, 0);
+
+	coex_dm->pre_low_penalty_ra = coex_dm->cur_low_penalty_ra;
+
+#endif
+}
+
+void halbtc8822b1ant_write_score_board(
+	IN	struct  btc_coexist		*btcoexist,
+	IN	u16				bitpos,
+	IN	boolean		state
+)
+{
+
+	static u16 originalval = 0x8002;
+
+	if (state)
+		originalval = originalval | bitpos;
+	else
+		originalval = originalval & (~bitpos);
+
+	btcoexist->btc_write_2byte(btcoexist, 0xaa, originalval);
+}
+
+void halbtc8822b1ant_read_score_board(
+	IN	struct  btc_coexist		*btcoexist,
+	IN   u16				*score_board_val
+)
+{
+
+	*score_board_val = (btcoexist->btc_read_2byte(btcoexist,
+			    0xaa)) & 0x7fff;
+}
+
+void halbtc8822b1ant_post_state_to_bt(
+	IN	struct  btc_coexist		*btcoexist,
+	IN	u16						type,
+	IN  boolean                 state
+)
+{
+
+	halbtc8822b1ant_write_score_board(btcoexist, (u16) type, state);
+
+}
+
+
+void halbtc8822b1ant_monitor_bt_enable_disable(IN struct btc_coexist *btcoexist)
+{
+	static u32		bt_disable_cnt = 0;
+	boolean			bt_active = true, bt_disabled = false,
+				wifi_under_5g = false;
+	u16		u16tmp;
+
+	/* This function check if bt is disabled */
+#if 0
+	if (coex_sta->high_priority_tx == 0 &&
+	    coex_sta->high_priority_rx == 0 &&
+	    coex_sta->low_priority_tx == 0 &&
+	    coex_sta->low_priority_rx == 0)
+		bt_active = false;
+	if (coex_sta->high_priority_tx == 0xffff &&
+	    coex_sta->high_priority_rx == 0xffff &&
+	    coex_sta->low_priority_tx == 0xffff &&
+	    coex_sta->low_priority_rx == 0xffff)
+		bt_active = false;
+
+
+#else
+
+	/* Read BT on/off status from scoreboard[1], enable this only if BT patch support this feature */
+	halbtc8822b1ant_read_score_board(btcoexist, &u16tmp);
+
+	bt_active = u16tmp & BIT(1);
+
+
+#endif
+
+	if (bt_active) {
+		bt_disable_cnt = 0;
+		bt_disabled = false;
+		btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_DISABLE,
+				   &bt_disabled);
+	} else {
+
+		bt_disable_cnt++;
+		if (bt_disable_cnt >= 2) {
+			bt_disabled = true;
+			bt_disable_cnt = 2;
+		}
+
+		btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_DISABLE,
+				   &bt_disabled);
+	}
+
+
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_5G,
+			   &wifi_under_5g);
+
+	if ((wifi_under_5g) || (bt_disabled))
+		halbtc8822b1ant_low_penalty_ra(btcoexist,
+					       NORMAL_EXEC, false);
+	else
+		halbtc8822b1ant_low_penalty_ra(btcoexist,
+					       NORMAL_EXEC, true);
+
+
+	if (coex_sta->bt_disabled != bt_disabled) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], BT is from %s to %s!!\n",
+			    (coex_sta->bt_disabled ? "disabled" :
+			     "enabled"),
+			    (bt_disabled ? "disabled" : "enabled"));
+		BTC_TRACE(trace_buf);
+		coex_sta->bt_disabled = bt_disabled;
+	}
+
+}
+
+
+
+void halbtc8822b1ant_enable_gnt_to_gpio(IN struct btc_coexist *btcoexist,
+					boolean isenable)
+{
+	static u8			bitVal[5] = {0, 0, 0, 0, 0};
+	static boolean		state = false;
+
+	if (state == isenable)
+		return;
+
+	state = isenable;
+
+	if (isenable) {
+
+		/* enable GNT_WL, GNT_BT to GPIO for debug */
+		btcoexist->btc_write_1byte_bitmask(btcoexist, 0x73, 0x8, 0x1);
+
+		/* store original value */
+		bitVal[0] = (btcoexist->btc_read_1byte(btcoexist,
+				       0x66) & BIT(4)) >> 4;	/*0x66[4] */
+		bitVal[1] = (btcoexist->btc_read_1byte(btcoexist,
+					       0x67) & BIT(0));		/*0x66[8] */
+		bitVal[2] = (btcoexist->btc_read_1byte(btcoexist,
+				       0x42) & BIT(3)) >> 3;  /*0x40[19] */
+		bitVal[3] = (btcoexist->btc_read_1byte(btcoexist,
+				       0x65) & BIT(7)) >> 7;  /*0x64[15] */
+		bitVal[4] = (btcoexist->btc_read_1byte(btcoexist,
+				       0x72) & BIT(2)) >> 2;  /*0x70[18] */
+
+		/*  switch GPIO Mux */
+		btcoexist->btc_write_1byte_bitmask(btcoexist, 0x66, BIT(4),
+						   0x0);  /*0x66[4] = 0 */
+		btcoexist->btc_write_1byte_bitmask(btcoexist, 0x67, BIT(0),
+						   0x0);  /*0x66[8] = 0 */
+		btcoexist->btc_write_1byte_bitmask(btcoexist, 0x42, BIT(3),
+						   0x0);  /*0x40[19] = 0 */
+		btcoexist->btc_write_1byte_bitmask(btcoexist, 0x65, BIT(7),
+						   0x0);  /*0x64[15] = 0 */
+		btcoexist->btc_write_1byte_bitmask(btcoexist, 0x72, BIT(2),
+						   0x0);  /*0x70[18] = 0 */
+
+
+	} else {
+		btcoexist->btc_write_1byte_bitmask(btcoexist, 0x73, 0x8, 0x0);
+
+		/*  Restore original value  */
+		/*  switch GPIO Mux */
+		btcoexist->btc_write_1byte_bitmask(btcoexist, 0x66, BIT(4),
+						   bitVal[0]);  /*0x66[4] = 0 */
+		btcoexist->btc_write_1byte_bitmask(btcoexist, 0x67, BIT(0),
+						   bitVal[1]);  /*0x66[8] = 0 */
+		btcoexist->btc_write_1byte_bitmask(btcoexist, 0x42, BIT(3),
+					   bitVal[2]);  /*0x40[19] = 0 */
+		btcoexist->btc_write_1byte_bitmask(btcoexist, 0x65, BIT(7),
+					   bitVal[3]);  /*0x64[15] = 0 */
+		btcoexist->btc_write_1byte_bitmask(btcoexist, 0x72, BIT(2),
+					   bitVal[4]);  /*0x70[18] = 0 */
+	}
+
+}
+
+
+u32 halbtc8822b1ant_ltecoex_indirect_read_reg(IN struct btc_coexist *btcoexist,
+		IN u16 reg_addr)
+{
+	u32 j = 0, delay_count = 0;
+
+
+	/* wait for ready bit before access 0x1700		 */
+	btcoexist->btc_write_4byte(btcoexist, 0x1700, 0x800F0000 | reg_addr);
+#if 0
+	do {
+		j++;
+	} while (((btcoexist->btc_read_1byte(btcoexist,
+					     0x1703) & BIT(5)) == 0) &&
+		 (j < BT_8822B_1ANT_LTECOEX_INDIRECTREG_ACCESS_TIMEOUT));
+#endif
+	while (1) {
+		if ((btcoexist->btc_read_1byte(btcoexist, 0x1703)&BIT(5)) == 0) {
+			delay_ms(50);
+			delay_count++;
+			if (delay_count >= 10) {
+				delay_count = 0;
+				break;
+			}
+		} else
+			break;
+	}
+	return btcoexist->btc_read_4byte(btcoexist,
+					 0x1708);  /* get read data */
+
+}
+
+void halbtc8822b1ant_ltecoex_indirect_write_reg(IN struct btc_coexist
+		*btcoexist,
+		IN u16 reg_addr, IN u32 bit_mask, IN u32 reg_value)
+{
+	u32 val, i = 0, j = 0, bitpos = 0, delay_count = 0;
+
+
+	if (bit_mask == 0x0)
+		return;
+	if (bit_mask == 0xffffffff) {
+		btcoexist->btc_write_4byte(btcoexist, 0x1704,
+					   reg_value); /* put write data */
+
+		/* wait for ready bit before access 0x1700 */
+#if 0
+		do {
+			j++;
+		} while (((btcoexist->btc_read_1byte(btcoexist,
+						     0x1703) & BIT(5)) == 0) &&
+			(j < BT_8822B_1ANT_LTECOEX_INDIRECTREG_ACCESS_TIMEOUT));
+#endif
+
+		while (1) {
+			if ((btcoexist->btc_read_1byte(btcoexist, 0x1703)&BIT(5)) == 0) {
+				delay_ms(50);
+				delay_count++;
+				if (delay_count >= 10)	{
+					delay_count = 0;
+					break;
+}
+			} else
+				break;
+		}
+		btcoexist->btc_write_4byte(btcoexist, 0x1700,
+					   0xc00F0000 | reg_addr);
+	} else {
+		for (i = 0; i <= 31; i++) {
+			if (((bit_mask >> i) & 0x1) == 0x1) {
+				bitpos = i;
+				break;
+			}
+		}
+
+		/* read back register value before write */
+		val = halbtc8822b1ant_ltecoex_indirect_read_reg(btcoexist,
+				reg_addr);
+		val = (val & (~bit_mask)) | (reg_value << bitpos);
+
+		/* put write data value */
+		btcoexist->btc_write_4byte(btcoexist, 0x1704,
+					   val); /* put write data */
+
+		/* wait for ready bit before access 0x1700		 */
+#if	0
+		do {
+			j++;
+		} while (((btcoexist->btc_read_1byte(btcoexist,
+						     0x1703) & BIT(5)) == 0) &&
+			(j < BT_8822B_1ANT_LTECOEX_INDIRECTREG_ACCESS_TIMEOUT));
+#endif
+
+		while (1) {
+			if ((btcoexist->btc_read_1byte(btcoexist, 0x1703)&BIT(5)) == 0) {
+				delay_ms(50);
+				delay_count++;
+				if (delay_count >= 10)	{
+					delay_count = 0;
+					break;
+				}
+			} else
+				break;
+		}
+
+
+
+		btcoexist->btc_write_4byte(btcoexist, 0x1700,
+					   0xc00F0000 | reg_addr);
+
+	}
+
+}
+
+void halbtc8822b1ant_ltecoex_enable(IN struct btc_coexist *btcoexist,
+				    IN boolean enable)
+{
+	u8 val;
+
+	val = (enable) ? 1 : 0;
+	/* 0x38[7] */
+	halbtc8822b1ant_ltecoex_indirect_write_reg(btcoexist, 0x38, 0x80,
+			val);  /* 0x38[7] */
+
+}
+
+
+void halbtc8822b1ant_ltecoex_pathcontrol_owner(IN struct btc_coexist *btcoexist,
+		IN boolean wifi_control)
+{
+	u8 val;
+
+	val = (wifi_control) ? 1 : 0;
+	/* 0x70[26] */
+	btcoexist->btc_write_1byte_bitmask(btcoexist, 0x73, 0x4,
+					   val); /* 0x70[26] */
+
+}
+
+void halbtc8822b1ant_ltecoex_set_gnt_bt(IN struct btc_coexist *btcoexist,
+			IN u8 control_block, IN boolean sw_control, IN u8 state)
+{
+	u32 val = 0, bit_mask;
+
+	state = state & 0x1;
+	/*LTE indirect 0x38=0xccxx (sw : gnt_wl=1,sw gnt_bt=1)
+	0x38=0xddxx (sw : gnt_bt=1 , sw gnt_wl=0)
+	0x38=0x55xx(hw pta :gnt_wl /gnt_bt ) */
+	val = (sw_control) ? ((state << 1) | 0x1) : 0;
+
+	switch (control_block) {
+	case BT_8822B_1ANT_GNT_BLOCK_RFC_BB:
+	default:
+		bit_mask = 0xc000;
+		halbtc8822b1ant_ltecoex_indirect_write_reg(btcoexist,
+				0x38, bit_mask, val); /* 0x38[15:14] */
+		bit_mask = 0x0c00;
+		halbtc8822b1ant_ltecoex_indirect_write_reg(btcoexist,
+				0x38, bit_mask, val); /* 0x38[11:10]						 */
+		break;
+	case BT_8822B_1ANT_GNT_BLOCK_RFC:
+		bit_mask = 0xc000;
+		halbtc8822b1ant_ltecoex_indirect_write_reg(btcoexist,
+				0x38, bit_mask, val); /* 0x38[15:14] */
+		break;
+	case BT_8822B_1ANT_GNT_BLOCK_BB:
+		bit_mask = 0x0c00;
+		halbtc8822b1ant_ltecoex_indirect_write_reg(btcoexist,
+				0x38, bit_mask, val); /* 0x38[11:10] */
+		break;
+
+	}
+
+}
+
+void halbtc8822b1ant_ltecoex_set_gnt_wl(IN struct btc_coexist *btcoexist,
+			IN u8 control_block, IN boolean sw_control, IN u8 state)
+{
+	u32 val = 0, bit_mask;
+	/*LTE indirect 0x38=0xccxx (sw : gnt_wl=1,sw gnt_bt=1)
+	0x38=0xddxx (sw : gnt_bt=1 , sw gnt_wl=0)
+	0x38=0x55xx(hw pta :gnt_wl /gnt_bt ) */
+
+	state = state & 0x1;
+	val = (sw_control) ? ((state << 1) | 0x1) : 0;
+
+	switch (control_block) {
+	case BT_8822B_1ANT_GNT_BLOCK_RFC_BB:
+	default:
+		bit_mask = 0x3000;
+		halbtc8822b1ant_ltecoex_indirect_write_reg(btcoexist,
+				0x38, bit_mask, val); /* 0x38[13:12] */
+		bit_mask = 0x0300;
+		halbtc8822b1ant_ltecoex_indirect_write_reg(btcoexist,
+				0x38, bit_mask, val); /* 0x38[9:8]						 */
+		break;
+	case BT_8822B_1ANT_GNT_BLOCK_RFC:
+		bit_mask = 0x3000;
+		halbtc8822b1ant_ltecoex_indirect_write_reg(btcoexist,
+				0x38, bit_mask, val); /* 0x38[13:12] */
+		break;
+	case BT_8822B_1ANT_GNT_BLOCK_BB:
+		bit_mask = 0x0300;
+		halbtc8822b1ant_ltecoex_indirect_write_reg(btcoexist,
+				0x38, bit_mask, val); /* 0x38[9:8] */
+		break;
+
+	}
+
+}
+
+void halbtc8822b1ant_ltecoex_set_coex_table(IN struct btc_coexist *btcoexist,
+		IN u8 table_type, IN u16 table_content)
+{
+	u16 reg_addr = 0x0000;
+
+	switch (table_type) {
+	case BT_8822B_1ANT_CTT_WL_VS_LTE:
+		reg_addr = 0xa0;
+		break;
+	case BT_8822B_1ANT_CTT_BT_VS_LTE:
+		reg_addr = 0xa4;
+		break;
+	}
+
+	if (reg_addr != 0x0000)
+		halbtc8822b1ant_ltecoex_indirect_write_reg(btcoexist, reg_addr,
+			0xffff, table_content); /* 0xa0[15:0] or 0xa4[15:0] */
+
+
+}
+
+
+void halbtc8822b1ant_ltcoex_set_break_table(IN struct btc_coexist *btcoexist,
+		IN u8 table_type, IN u8 table_content)
+{
+	u16 reg_addr = 0x0000;
+
+	switch (table_type) {
+	case BT_8822B_1ANT_LBTT_WL_BREAK_LTE:
+		reg_addr = 0xa8;
+		break;
+	case BT_8822B_1ANT_LBTT_BT_BREAK_LTE:
+		reg_addr = 0xac;
+		break;
+	case BT_8822B_1ANT_LBTT_LTE_BREAK_WL:
+		reg_addr = 0xb0;
+		break;
+	case BT_8822B_1ANT_LBTT_LTE_BREAK_BT:
+		reg_addr = 0xb4;
+		break;
+	}
+
+	if (reg_addr != 0x0000)
+		halbtc8822b1ant_ltecoex_indirect_write_reg(btcoexist, reg_addr,
+			0xff, table_content); /* 0xa8[15:0] or 0xb4[15:0] */
+
+
+}
+
+void halbtc8822b1ant_set_wltoggle_coex_table(IN struct btc_coexist *btcoexist,
+		IN boolean force_exec,  IN u8 interval,
+		IN u8 val0x6c4_b0, IN u8 val0x6c4_b1, IN u8 val0x6c4_b2,
+		IN u8 val0x6c4_b3)
+{
+	static u8 pre_h2c_parameter[6] = {0};
+	u8	cur_h2c_parameter[6] = {0};
+	u8 i, match_cnt = 0;
+
+	cur_h2c_parameter[0] = 0x7;	/* op_code, 0x7= wlan toggle slot*/
+
+	cur_h2c_parameter[1] = interval;
+	cur_h2c_parameter[2] = val0x6c4_b0;
+	cur_h2c_parameter[3] = val0x6c4_b1;
+	cur_h2c_parameter[4] = val0x6c4_b2;
+	cur_h2c_parameter[5] = val0x6c4_b3;
+
+	if (!force_exec) {
+		for (i = 1; i <= 5; i++) {
+			if (cur_h2c_parameter[i] != pre_h2c_parameter[i])
+				break;
+
+			match_cnt++;
+		}
+
+		if (match_cnt == 5)
+			return;
+	}
+
+	for (i = 1; i <= 5; i++)
+		pre_h2c_parameter[i] = cur_h2c_parameter[i];
+
+	btcoexist->btc_fill_h2c(btcoexist, 0x69, 6, cur_h2c_parameter);
+}
+
+void halbtc8822b1ant_set_coex_table(IN struct btc_coexist *btcoexist,
+	    IN u32 val0x6c0, IN u32 val0x6c4, IN u32 val0x6c8, IN u8 val0x6cc)
+{
+	btcoexist->btc_write_4byte(btcoexist, 0x6c0, val0x6c0);
+
+	btcoexist->btc_write_4byte(btcoexist, 0x6c4, val0x6c4);
+
+	btcoexist->btc_write_4byte(btcoexist, 0x6c8, val0x6c8);
+
+	btcoexist->btc_write_1byte(btcoexist, 0x6cc, val0x6cc);
+}
+
+void halbtc8822b1ant_coex_table(IN struct btc_coexist *btcoexist,
+			IN boolean force_exec, IN u32 val0x6c0, IN u32 val0x6c4,
+				IN u32 val0x6c8, IN u8 val0x6cc)
+{
+	coex_dm->cur_val0x6c0 = val0x6c0;
+	coex_dm->cur_val0x6c4 = val0x6c4;
+	coex_dm->cur_val0x6c8 = val0x6c8;
+	coex_dm->cur_val0x6cc = val0x6cc;
+
+
+
+	if (!force_exec) {
+		if ((coex_dm->pre_val0x6c0 == coex_dm->cur_val0x6c0) &&
+		    (coex_dm->pre_val0x6c4 == coex_dm->cur_val0x6c4) &&
+		    (coex_dm->pre_val0x6c8 == coex_dm->cur_val0x6c8) &&
+		    (coex_dm->pre_val0x6cc == coex_dm->cur_val0x6cc))
+			return;
+	}
+	halbtc8822b1ant_set_coex_table(btcoexist, val0x6c0, val0x6c4, val0x6c8,
+				       val0x6cc);
+
+	coex_dm->pre_val0x6c0 = coex_dm->cur_val0x6c0;
+	coex_dm->pre_val0x6c4 = coex_dm->cur_val0x6c4;
+	coex_dm->pre_val0x6c8 = coex_dm->cur_val0x6c8;
+	coex_dm->pre_val0x6cc = coex_dm->cur_val0x6cc;
+}
+
+void halbtc8822b1ant_coex_table_with_type(IN struct btc_coexist *btcoexist,
+		IN boolean force_exec, IN u8 type)
+{
+	u32	break_table;
+	u8	select_table;
+
+
+
+	coex_sta->coex_table_type = type;
+
+	if (coex_sta->concurrent_rx_mode_on == true) {
+		break_table = 0xf0ffffff;	/* set WL hi-pri can break BT */
+		select_table = 0x3;		/* set Tx response = Hi-Pri (ex: Transmitting ACK,BA,CTS) */
+	} else {
+		break_table = 0xffffff;
+		select_table = 0x3;
+	}
+
+	switch (type) {
+	case 0:
+		halbtc8822b1ant_coex_table(btcoexist, force_exec,
+					   0x55555555, 0x55555555, break_table,
+					   select_table);
+		break;
+	case 1:
+		halbtc8822b1ant_coex_table(btcoexist, force_exec,
+					   0x55555555, 0x5a5a5a5a, break_table,
+					   select_table);
+		break;
+	case 2:
+		halbtc8822b1ant_coex_table(btcoexist, force_exec,
+					   0xaa5a5a5a, 0xaa5a5a5a, break_table,
+					   select_table);
+		break;
+	case 3:
+		halbtc8822b1ant_coex_table(btcoexist, force_exec,
+					   0x55555555, 0xaa5a5a5a, break_table,
+					   select_table);
+		break;
+	case 4:
+		halbtc8822b1ant_coex_table(btcoexist,
+					   force_exec, 0xaa555555, 0xaa5a5a5a,
+					   break_table, select_table);
+		break;
+	case 5:
+		halbtc8822b1ant_coex_table(btcoexist,
+					   force_exec, 0x5a5a5a5a, 0x5a5a5a5a,
+					   break_table, select_table);
+		break;
+	case 6:
+		halbtc8822b1ant_coex_table(btcoexist, force_exec,
+					   0x55555555, 0xaaaaaaaa, break_table,
+					   select_table);
+		break;
+	case 7:
+		halbtc8822b1ant_coex_table(btcoexist, force_exec,
+					   0xaaaaaaaa, 0xaaaaaaaa, break_table,
+					   select_table);
+		break;
+	case 8:
+		halbtc8822b1ant_coex_table(btcoexist, force_exec,
+					   0xffffffff, 0xffffffff, break_table,
+					   select_table);
+		break;
+	case 9:
+		halbtc8822b1ant_coex_table(btcoexist, force_exec,
+					   0x5a5a5555, 0xaaaa5a5a, break_table,
+					   select_table);
+		break;
+	case 10:
+		halbtc8822b1ant_coex_table(btcoexist, force_exec,
+					   0xaaaa5aaa, 0xaaaa5aaa, break_table,
+					   select_table);
+		break;
+	case 11:
+		halbtc8822b1ant_coex_table(btcoexist, force_exec,
+					   0xaaaaa5aa, 0xaaaaaaaa, break_table,
+					   select_table);
+		break;
+	case 12:
+		halbtc8822b1ant_coex_table(btcoexist, force_exec,
+					   0xaaaaa5aa, 0xaaaaa5aa, break_table,
+					   select_table);
+		break;
+	case 13:
+		halbtc8822b1ant_coex_table(btcoexist, force_exec,
+					   0x55555555, 0xaaaa5a5a, break_table,
+					   select_table);
+		break;
+	case 14:
+		halbtc8822b1ant_coex_table(btcoexist, force_exec,
+					   0x5a5a555a, 0xaaaa5a5a, break_table,
+					   select_table);
+		break;
+	case 15:
+		halbtc8822b1ant_coex_table(btcoexist, force_exec,
+					   0x55555555, 0xaaaa55aa, break_table,
+					   select_table);
+		break;
+	case 16:
+		halbtc8822b1ant_coex_table(btcoexist, force_exec,
+					   0x5a5a555a, 0x5a5a555a, break_table,
+					   select_table);
+		break;
+	case 17:
+		halbtc8822b1ant_coex_table(btcoexist, force_exec,
+					   0xaaaa55aa, 0xaaaa55aa, break_table,
+					   select_table);
+		break;
+
+	default:
+		break;
+	}
+}
+
+void halbtc8822b1ant_set_fw_ignore_wlan_act(IN struct btc_coexist *btcoexist,
+		IN boolean enable)
+{
+
+
+	u8			h2c_parameter[1] = {0};
+
+	if (enable)
+		h2c_parameter[0] |= BIT(0);		/* function enable */
+
+	btcoexist->btc_fill_h2c(btcoexist, 0x63, 1, h2c_parameter);
+}
+
+void halbtc8822b1ant_ignore_wlan_act(IN struct btc_coexist *btcoexist,
+				     IN boolean force_exec, IN boolean enable)
+{
+
+	coex_dm->cur_ignore_wlan_act = enable;
+
+	if (!force_exec) {
+		if (coex_dm->pre_ignore_wlan_act ==
+		    coex_dm->cur_ignore_wlan_act) {
+
+			coex_dm->pre_ignore_wlan_act =
+				coex_dm->cur_ignore_wlan_act;
+			return;
+		}
+	}
+
+	halbtc8822b1ant_set_fw_ignore_wlan_act(btcoexist, enable);
+
+	coex_dm->pre_ignore_wlan_act = coex_dm->cur_ignore_wlan_act;
+}
+
+void halbtc8822b1ant_set_lps_rpwm(IN struct btc_coexist *btcoexist,
+				  IN u8 lps_val, IN u8 rpwm_val)
+{
+	u8	lps = lps_val;
+	u8	rpwm = rpwm_val;
+
+	btcoexist->btc_set(btcoexist, BTC_SET_U1_LPS_VAL, &lps);
+	btcoexist->btc_set(btcoexist, BTC_SET_U1_RPWM_VAL, &rpwm);
+}
+
+void halbtc8822b1ant_lps_rpwm(IN struct btc_coexist *btcoexist,
+		      IN boolean force_exec, IN u8 lps_val, IN u8 rpwm_val)
+{
+	coex_dm->cur_lps = lps_val;
+	coex_dm->cur_rpwm = rpwm_val;
+
+	if (!force_exec) {
+		if ((coex_dm->pre_lps == coex_dm->cur_lps) &&
+		    (coex_dm->pre_rpwm == coex_dm->cur_rpwm))
+			return;
+	}
+	halbtc8822b1ant_set_lps_rpwm(btcoexist, lps_val, rpwm_val);
+
+	coex_dm->pre_lps = coex_dm->cur_lps;
+	coex_dm->pre_rpwm = coex_dm->cur_rpwm;
+}
+
+void halbtc8822b1ant_ps_tdma_check_for_power_save_state(
+	IN struct btc_coexist *btcoexist, IN boolean new_ps_state)
+{
+	u8	lps_mode = 0x0;
+	u8	h2c_parameter[5] = {0x8, 0, 0, 0, 0};
+
+	btcoexist->btc_get(btcoexist, BTC_GET_U1_LPS_MODE, &lps_mode);
+
+	if (lps_mode) { /* already under LPS state */
+		if (new_ps_state) {
+			/* keep state under LPS, do nothing. */
+		} else {
+			/* will leave LPS state, turn off psTdma first */
+
+			btcoexist->btc_fill_h2c(btcoexist, 0x60, 5,
+						h2c_parameter);
+		}
+	} else {					/* NO PS state */
+		if (new_ps_state) {
+			/* will enter LPS state, turn off psTdma first */
+
+			btcoexist->btc_fill_h2c(btcoexist, 0x60, 5,
+						h2c_parameter);
+		} else {
+			/* keep state under NO PS state, do nothing. */
+		}
+	}
+}
+
+
+void halbtc8822b1ant_power_save_state(IN struct btc_coexist *btcoexist,
+			      IN u8 ps_type, IN u8 lps_val, IN u8 rpwm_val)
+{
+	boolean		low_pwr_disable = false;
+
+	switch (ps_type) {
+	case BTC_PS_WIFI_NATIVE:
+		/* recover to original 32k low power setting */
+		coex_sta->force_lps_on = false;
+		low_pwr_disable = false;
+		btcoexist->btc_set(btcoexist,
+				   BTC_SET_ACT_DISABLE_LOW_POWER,
+				   &low_pwr_disable);
+		btcoexist->btc_set(btcoexist, BTC_SET_ACT_NORMAL_LPS,
+				   NULL);
+		coex_sta->force_lps_on = false;
+		break;
+	case BTC_PS_LPS_ON:
+
+		coex_sta->force_lps_on = true;
+		halbtc8822b1ant_ps_tdma_check_for_power_save_state(
+			btcoexist, true);
+		halbtc8822b1ant_lps_rpwm(btcoexist, NORMAL_EXEC,
+					 lps_val, rpwm_val);
+		/* when coex force to enter LPS, do not enter 32k low power. */
+		low_pwr_disable = true;
+		btcoexist->btc_set(btcoexist,
+				   BTC_SET_ACT_DISABLE_LOW_POWER,
+				   &low_pwr_disable);
+		/* power save must executed before psTdma.			 */
+		btcoexist->btc_set(btcoexist, BTC_SET_ACT_ENTER_LPS,
+				   NULL);
+		coex_sta->force_lps_on = true;
+		break;
+	case BTC_PS_LPS_OFF:
+
+		coex_sta->force_lps_on = false;
+		halbtc8822b1ant_ps_tdma_check_for_power_save_state(
+			btcoexist, false);
+		btcoexist->btc_set(btcoexist, BTC_SET_ACT_LEAVE_LPS,
+				   NULL);
+		coex_sta->force_lps_on = false;
+		break;
+	default:
+		break;
+	}
+}
+
+
+void halbtc8822b1ant_set_fw_pstdma(IN struct btc_coexist *btcoexist,
+	   IN u8 byte1, IN u8 byte2, IN u8 byte3, IN u8 byte4, IN u8 byte5)
+{
+	u8			h2c_parameter[5] = {0};
+	u8			real_byte1 = byte1, real_byte5 = byte5;
+	boolean		ap_enable = false;
+
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_AP_MODE_ENABLE,
+			   &ap_enable);
+
+	if (ap_enable) {
+		if (byte1 & BIT(4) && !(byte1 & BIT(5))) {
+
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				    "[BTCoex], FW for 1Ant AP mode\n");
+			BTC_TRACE(trace_buf);
+
+			real_byte1 &= ~BIT(4);
+			real_byte1 |= BIT(5);
+
+			real_byte5 |= BIT(5);
+			real_byte5 &= ~BIT(6);
+
+			halbtc8822b1ant_power_save_state(btcoexist,
+						 BTC_PS_WIFI_NATIVE, 0x0,
+							 0x0);
+		}
+	} else if (byte1 & BIT(4) && !(byte1 & BIT(5))) {
+
+		halbtc8822b1ant_power_save_state(btcoexist,
+						 BTC_PS_LPS_ON, 0x50,
+						 0x4);
+	} else {
+		halbtc8822b1ant_power_save_state(btcoexist,
+						 BTC_PS_WIFI_NATIVE, 0x0,
+						 0x0);
+	}
+
+
+	h2c_parameter[0] = real_byte1;
+	h2c_parameter[1] = byte2;
+	h2c_parameter[2] = byte3;
+	h2c_parameter[3] = byte4;
+	h2c_parameter[4] = real_byte5;
+
+	coex_dm->ps_tdma_para[0] = real_byte1;
+	coex_dm->ps_tdma_para[1] = byte2;
+	coex_dm->ps_tdma_para[2] = byte3;
+	coex_dm->ps_tdma_para[3] = byte4;
+	coex_dm->ps_tdma_para[4] = real_byte5;
+
+	btcoexist->btc_fill_h2c(btcoexist, 0x60, 5, h2c_parameter);
+}
+
+void halbtc8822b1ant_ps_tdma(IN struct btc_coexist *btcoexist,
+		     IN boolean force_exec, IN boolean turn_on, IN u8 type)
+{
+	struct  btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
+	struct  btc_board_info	*board_info = &btcoexist->board_info;
+	boolean			wifi_busy = false;
+	static u8			psTdmaByte4Modify = 0x0, pre_psTdmaByte4Modify = 0x0;
+	static boolean	 pre_wifi_busy = false;
+
+	coex_dm->cur_ps_tdma_on = turn_on;
+	coex_dm->cur_ps_tdma = type;
+
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy);
+
+	if (wifi_busy != pre_wifi_busy) {
+		force_exec = true;
+		pre_wifi_busy = wifi_busy;
+	}
+
+	/* 0x778 = 0x1 at wifi slot (no blocking BT Low-Pri pkts) */
+	if ((bt_link_info->slave_role) && (bt_link_info->a2dp_exist))
+		psTdmaByte4Modify = 0x1;
+	else
+		psTdmaByte4Modify = 0x0;
+
+	if (pre_psTdmaByte4Modify != psTdmaByte4Modify) {
+
+		force_exec = true;
+		pre_psTdmaByte4Modify = psTdmaByte4Modify;
+	}
+
+	if (coex_dm->cur_ps_tdma_on) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], ********TDMA(on, %d) **********\n",
+			    coex_dm->cur_ps_tdma);
+		BTC_TRACE(trace_buf);
+	} else {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], **********TDMA(off, %d) **********\n",
+			    coex_dm->cur_ps_tdma);
+		BTC_TRACE(trace_buf);
+	}
+
+	if (!force_exec) {
+		if ((coex_dm->pre_ps_tdma_on == coex_dm->cur_ps_tdma_on) &&
+		    (coex_dm->pre_ps_tdma == coex_dm->cur_ps_tdma)) {
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				"[BTCoex], return for no-TDMA case change\n");
+			BTC_TRACE(trace_buf);
+
+			return;
+		}
+	}
+
+
+	if (turn_on) {
+
+		btcoexist->btc_write_1byte_bitmask(btcoexist, 0x550, 0x8,
+					   0x1);  /* enable TBTT nterrupt */
+
+		switch (type) {
+		default:
+			halbtc8822b1ant_set_fw_pstdma(btcoexist,
+					      0x51, 0x1a, 0x1a, 0x0, 0x10);
+			break;
+		case 1:
+			halbtc8822b1ant_set_fw_pstdma(btcoexist,
+					      0x61, 0x3a, 0x03, 0x11, 0x10);
+			break;
+		case 3:
+			halbtc8822b1ant_set_fw_pstdma(btcoexist,
+					      0x51, 0x3a, 0x03, 0x10, 0x10);
+			break;
+		case 4:
+			halbtc8822b1ant_set_fw_pstdma(btcoexist,
+					      0x51, 0x21, 0x03, 0x10, 0x10);
+			break;
+		case 5:
+			halbtc8822b1ant_set_fw_pstdma(btcoexist,
+					      0x61, 0x15, 0x3, 0x11, 0x11);
+			break;
+		case 7:
+			halbtc8822b1ant_set_fw_pstdma(btcoexist,
+					      0x61, 0x10, 0x03, 0x10,  0x14 |
+						      psTdmaByte4Modify);
+			break;
+		case 8:
+			halbtc8822b1ant_set_fw_pstdma(btcoexist,
+					      0x51, 0x10, 0x03, 0x10,  0x14 |
+						      psTdmaByte4Modify);
+			break;
+		case 13:
+			halbtc8822b1ant_set_fw_pstdma(btcoexist,
+					      0x51, 0x25, 0x03, 0x10,  0x10 |
+						      psTdmaByte4Modify);
+			break;
+		case 14:
+			halbtc8822b1ant_set_fw_pstdma(btcoexist,
+					      0x51, 0x15, 0x03, 0x10,  0x10 |
+						      psTdmaByte4Modify);
+			break;
+		case 15:
+			halbtc8822b1ant_set_fw_pstdma(btcoexist,
+					      0x51, 0x20, 0x03, 0x10,  0x10 |
+						      psTdmaByte4Modify);
+			break;
+		case 17:
+			halbtc8822b1ant_set_fw_pstdma(btcoexist,
+					      0x61, 0x10, 0x03, 0x11,  0x14 |
+						      psTdmaByte4Modify);
+			break;
+
+		case 20:
+			halbtc8822b1ant_set_fw_pstdma(btcoexist,
+					      0x61, 0x30, 0x03, 0x11, 0x10);
+			break;
+		case 22:
+			halbtc8822b1ant_set_fw_pstdma(btcoexist,
+					      0x61, 0x25, 0x03, 0x11, 0x10);
+			break;
+		case 32:
+			halbtc8822b1ant_set_fw_pstdma(btcoexist,
+					      0x61, 0x35, 0x3, 0x11, 0x11);
+			break;
+		case 33:
+			halbtc8822b1ant_set_fw_pstdma(btcoexist,
+					      0x61, 0x35, 0x03, 0x11, 0x10);
+			break;
+		case 41:
+			halbtc8822b1ant_set_fw_pstdma(btcoexist,
+					      0x51, 0x45, 0x3, 0x11, 0x11);
+			break;
+		case 42:
+			halbtc8822b1ant_set_fw_pstdma(btcoexist,
+					      0x51, 0x1e, 0x3, 0x10, 0x14 |
+						      psTdmaByte4Modify);
+			break;
+		case 43:
+			halbtc8822b1ant_set_fw_pstdma(btcoexist,
+					      0x51, 0x45, 0x3, 0x10, 0x14);
+			break;
+		case 44:
+			halbtc8822b1ant_set_fw_pstdma(btcoexist,
+					      0x51, 0x25, 0x3, 0x10, 0x10);
+			break;
+		case 45:
+			halbtc8822b1ant_set_fw_pstdma(btcoexist,
+					      0x51, 0x29, 0x3, 0x10, 0x10);
+			break;
+		case 46:
+			halbtc8822b1ant_set_fw_pstdma(btcoexist,
+					      0x51, 0x1a, 0x3, 0x10, 0x10);
+			break;
+		case 47:
+			halbtc8822b1ant_set_fw_pstdma(btcoexist,
+					      0x51, 0x32, 0x3, 0x10, 0x10);
+			break;
+		case 48:
+			halbtc8822b1ant_set_fw_pstdma(btcoexist,
+					      0x51, 0x29, 0x3, 0x10, 0x10);
+			break;
+		case 49:
+			halbtc8822b1ant_set_fw_pstdma(btcoexist,
+					      0x55, 0x1e, 0x3, 0x10, 0x54);
+			break;
+		case 50:
+			halbtc8822b1ant_set_fw_pstdma(btcoexist,
+					      0x51, 0x4a, 0x3, 0x10, 0x10);
+			break;
+
+		}
+	} else {
+
+		switch (type) {
+		case 0:
+		default:  /* Software control, Antenna at BT side */
+			halbtc8822b1ant_set_fw_pstdma(btcoexist,
+						      0x0, 0x0, 0x0, 0x0, 0x0);
+			/*
+			halbtc8822b1ant_set_ant_path(btcoexist,
+					     BTC_ANT_PATH_BT, FORCE_EXEC, false,
+						     false); */
+			break;
+		case 8: /* PTA Control */
+			halbtc8822b1ant_set_fw_pstdma(btcoexist,
+						      0x8, 0x0, 0x0, 0x0, 0x0);
+			/*
+			halbtc8822b1ant_set_ant_path(btcoexist,
+				     BTC_ANT_PATH_PTA, FORCE_EXEC,  false,
+				     false);  */
+			break;
+		case 9:   /* Software control, Antenna at WiFi side */
+			halbtc8822b1ant_set_fw_pstdma(btcoexist,
+						      0x0, 0x0, 0x0, 0x0, 0x0);
+			/*
+			halbtc8822b1ant_set_ant_path(btcoexist,
+					     BTC_ANT_PATH_WIFI, FORCE_EXEC,false,false); */
+			break;
+		case 10:	/* under 5G , 0x778=1*/
+			halbtc8822b1ant_set_fw_pstdma(btcoexist,
+						      0x0, 0x0, 0x0, 0x0, 0x0);
+
+			/*
+			halbtc8822b1ant_set_ant_path(btcoexist,
+					     BTC_ANT_PATH_WIFI5G, FORCE_EXEC, false,
+						     false);	*/
+
+			break;
+		}
+	}
+
+
+	/* update pre state */
+	coex_dm->pre_ps_tdma_on = coex_dm->cur_ps_tdma_on;
+	coex_dm->pre_ps_tdma = coex_dm->cur_ps_tdma;
+}
+
+
+void halbtc8822b1ant_sw_mechanism(IN struct btc_coexist *btcoexist,
+				  IN boolean low_penalty_ra)
+{
+	halbtc8822b1ant_low_penalty_ra(btcoexist, NORMAL_EXEC, low_penalty_ra);
+}
+/*rf4 type by efuse , and for ant at main aux inverse use , because is 2x2 ,and control types are the same ,does not need */
+
+void halbtc8822b1ant_set_rfe_type(IN struct btc_coexist *btcoexist)
+{
+	struct  btc_board_info *board_info = &btcoexist->board_info;
+
+	/* Ext switch buffer mux */
+		btcoexist->btc_write_1byte(btcoexist, 0x974, 0xff);
+		btcoexist->btc_write_1byte_bitmask(btcoexist, 0x1991, 0x3, 0x0);
+		btcoexist->btc_write_1byte_bitmask(btcoexist, 0xcbe, 0x8, 0x0);
+
+	/* the following setup should be got from Efuse in the future */
+	rfe_type->rfe_module_type = board_info->rfe_type;
+
+	rfe_type->ext_ant_switch_ctrl_polarity = 0;
+
+	switch (rfe_type->rfe_module_type) {
+	case 0:
+	default:
+		rfe_type->ext_ant_switch_exist = true;
+		rfe_type->ext_ant_switch_type =
+			BT_8822B_1ANT_EXT_ANT_SWITCH_USE_SPDT;
+		break;
+	case 1:
+		rfe_type->ext_ant_switch_exist = true;
+		rfe_type->ext_ant_switch_type =
+			BT_8822B_1ANT_EXT_ANT_SWITCH_USE_SPDT;
+		break;
+	case 2:
+		rfe_type->ext_ant_switch_exist = true;
+		rfe_type->ext_ant_switch_type =
+			BT_8822B_1ANT_EXT_ANT_SWITCH_USE_SPDT;
+		break;
+	case 3:
+		rfe_type->ext_ant_switch_exist = true;
+		rfe_type->ext_ant_switch_type =
+			BT_8822B_1ANT_EXT_ANT_SWITCH_USE_SPDT;
+		break;
+	case 4:
+		rfe_type->ext_ant_switch_exist = true;
+		rfe_type->ext_ant_switch_type =
+BT_8822B_1ANT_EXT_ANT_SWITCH_USE_SPDT;
+		break;
+	case 5:
+		rfe_type->ext_ant_switch_exist = true;
+		rfe_type->ext_ant_switch_type =
+BT_8822B_1ANT_EXT_ANT_SWITCH_USE_SPDT;
+		break;
+	case 6:
+		rfe_type->ext_ant_switch_exist = true;
+		rfe_type->ext_ant_switch_type =
+BT_8822B_1ANT_EXT_ANT_SWITCH_USE_SPDT;
+		break;
+	case 7:
+		rfe_type->ext_ant_switch_exist = true;
+		rfe_type->ext_ant_switch_type =
+BT_8822B_1ANT_EXT_ANT_SWITCH_USE_SPDT;
+		break;
+	}
+
+
+}
+
+/*anttenna control by bb mac bt antdiv pta to write 0x4c 0xcb4,0xcbd*/
+
+void halbtc8822b1ant_set_ext_ant_switch(IN struct btc_coexist *btcoexist,
+			IN boolean force_exec, IN u8 ctrl_type, IN u8 pos_type)
+{
+	struct  btc_board_info	*board_info = &btcoexist->board_info;
+	boolean	switch_polatiry_inverse = false;
+	u8		regval_0xcbd = 0, regval_0x64;
+	u32		u32tmp1 = 0, u32tmp2 = 0, u32tmp3 = 0;
+	/* Ext switch buffer mux */
+		btcoexist->btc_write_1byte(btcoexist, 0x974, 0xff);
+		btcoexist->btc_write_1byte_bitmask(btcoexist, 0x1991, 0x3, 0x0);
+		btcoexist->btc_write_1byte_bitmask(btcoexist, 0xcbe, 0x8, 0x0);
+
+	if (!rfe_type->ext_ant_switch_exist)
+		return;
+
+	coex_dm->cur_ext_ant_switch_status = (ctrl_type << 8)  + pos_type;
+
+	if (!force_exec) {
+		if (coex_dm->pre_ext_ant_switch_status ==
+		    coex_dm->cur_ext_ant_switch_status)
+			return;
+	}
+
+	coex_dm->pre_ext_ant_switch_status = coex_dm->cur_ext_ant_switch_status;
+
+	/* swap control polarity if use different switch control polarity*/
+	/*  Normal switch polarity for SPDT, 0xcbd[1:0] = 2b'01 => Ant to BTG,  0xcbd[1:0] = 2b'10 => Ant to WLG */
+	switch_polatiry_inverse = (rfe_type->ext_ant_switch_ctrl_polarity == 1 ?
+			   ~switch_polatiry_inverse : switch_polatiry_inverse);
+
+
+	switch (pos_type) {
+	default:
+	case BT_8822B_1ANT_EXT_ANT_SWITCH_TO_BT:
+	case BT_8822B_1ANT_EXT_ANT_SWITCH_TO_NOCARE:
+
+		break;
+	case BT_8822B_1ANT_EXT_ANT_SWITCH_TO_WLG:
+		break;
+	case BT_8822B_1ANT_EXT_ANT_SWITCH_TO_WLA:
+		break;
+	}
+
+
+	if (rfe_type->ext_ant_switch_type ==
+	    BT_8822B_1ANT_EXT_ANT_SWITCH_USE_SPDT) {
+		switch (ctrl_type) {
+		default:
+		case BT_8822B_1ANT_EXT_ANT_SWITCH_CTRL_BY_BBSW:
+			btcoexist->btc_write_1byte_bitmask(
+				btcoexist, 0x4e, 0x80,
+				0x0);  /*  0x4c[23] = 0 */
+			btcoexist->btc_write_1byte_bitmask(
+				btcoexist, 0x4f, 0x01,
+				0x1);  /* 0x4c[24] = 1 */
+			btcoexist->btc_write_1byte_bitmask(
+				btcoexist, 0xcb4, 0xff,
+				0x77);	/* BB SW, DPDT use RFE_ctrl8 and RFE_ctrl9 as conctrol pin */
+
+			regval_0xcbd = (switch_polatiry_inverse
+					== false ?  0x1 :
+				0x2);    /* 0xcbd[1:0] = 2b'01 for no switch_polatiry_inverse, ANTSWB =1, ANTSW =0  */
+			btcoexist->btc_write_1byte_bitmask(
+				btcoexist, 0xcbd, 0x3,
+				regval_0xcbd);
+
+			break;
+		case BT_8822B_1ANT_EXT_ANT_SWITCH_CTRL_BY_PTA:
+			btcoexist->btc_write_1byte_bitmask(
+				btcoexist, 0x4e, 0x80,
+				0x0);  /* 0x4c[23] = 0 */
+			btcoexist->btc_write_1byte_bitmask(
+				btcoexist, 0x4f, 0x01,
+				0x1);  /* 0x4c[24] = 1 */
+			btcoexist->btc_write_1byte_bitmask(
+				btcoexist, 0xcb4, 0xff,
+				0x66);	/* PTA,  DPDT use RFE_ctrl8 and RFE_ctrl9 as conctrol pin */
+
+			regval_0xcbd = (switch_polatiry_inverse
+					== false ?  0x2 :
+				0x1);    /* 0xcbd[1:0] = 2b'10 for no switch_polatiry_inverse, ANTSWB =1, ANTSW =0  @ GNT_BT=1 */
+			btcoexist->btc_write_1byte_bitmask(
+				btcoexist, 0xcbd, 0x3,
+				regval_0xcbd);
+
+			break;
+		case BT_8822B_1ANT_EXT_ANT_SWITCH_CTRL_BY_ANTDIV
+				:
+			btcoexist->btc_write_1byte_bitmask(
+				btcoexist, 0x4e, 0x80,
+				0x0);  /* 0x4c[23] = 0 */
+			btcoexist->btc_write_1byte_bitmask(
+				btcoexist, 0x4f, 0x01,
+				0x1);  /* 0x4c[24] = 1 */
+			btcoexist->btc_write_1byte_bitmask(
+				btcoexist, 0xcb4, 0xff,
+				0x88);  /* */
+
+			/* no regval_0xcbd setup required, because  antenna switch control value by antenna diversity */
+
+			break;
+		case BT_8822B_1ANT_EXT_ANT_SWITCH_CTRL_BY_MAC:
+			btcoexist->btc_write_1byte_bitmask(
+				btcoexist, 0x4e, 0x80,
+				0x1);  /*  0x4c[23] = 1 */
+
+			regval_0x64 = (switch_polatiry_inverse
+				       == false ?  0x0 :
+				0x1);    /* 0x64[0] = 1b'0 for no switch_polatiry_inverse, DPDT_SEL_N =1, DPDT_SEL_P =0 */
+			btcoexist->btc_write_1byte_bitmask(
+				btcoexist, 0x64, 0x1,
+				regval_0x64);
+			break;
+		case BT_8822B_1ANT_EXT_ANT_SWITCH_CTRL_BY_BT:
+			btcoexist->btc_write_1byte_bitmask(
+				btcoexist, 0x4e, 0x80,
+				0x0);  /* 0x4c[23] = 0 */
+			btcoexist->btc_write_1byte_bitmask(
+				btcoexist, 0x4f, 0x01,
+				0x0);  /* 0x4c[24] = 0 */
+
+			/* no  setup required, because  antenna switch control value by BT vendor 0xac[1:0] */
+			break;
+		}
+	}
+
+	u32tmp1 = btcoexist->btc_read_4byte(btcoexist, 0xcbc);
+	u32tmp2 = btcoexist->btc_read_4byte(btcoexist, 0x4c);
+	u32tmp3 = btcoexist->btc_read_4byte(btcoexist, 0x64) & 0xff;
+
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+		"[BTCoex], ********** (After Ext Ant switch setup) 0xcbc = 0x%08x, 0x4c = 0x%08x, 0x64= 0x%02x**********\n",
+		    u32tmp1, u32tmp2, u32tmp3);
+	BTC_TRACE(trace_buf);
+
+
+}
+
+/*set gnt_wl gnt_bt control by sw high low , or hwpta while in power on,ini,wlan off,wlan only ,wl2g non-currrent ,wl2g current,wl5g*/
+
+void halbtc8822b1ant_set_ant_path(IN struct btc_coexist *btcoexist,
+				  IN u8 ant_pos_type, IN boolean force_exec,
+				  IN u8 phase)
+
+{
+	struct  btc_board_info *board_info = &btcoexist->board_info;
+	u8			u8tmp = 0;
+	u32			u32tmp1 = 0, u32tmp2 = 0, u32tmp3 = 0;
+	/* Ext switch buffer mux */
+		btcoexist->btc_write_1byte(btcoexist, 0x974, 0xff);
+		btcoexist->btc_write_1byte_bitmask(btcoexist, 0x1991, 0x3, 0x0);
+		btcoexist->btc_write_1byte_bitmask(btcoexist, 0xcbe, 0x8, 0x0);
+
+	coex_dm->cur_ant_pos_type = (ant_pos_type << 8)  + phase;
+
+	if (!force_exec) {
+		if (coex_dm->cur_ant_pos_type ==
+		    coex_dm->pre_ant_pos_type)
+			return;
+	}
+
+	coex_dm->pre_ant_pos_type = coex_dm->cur_ant_pos_type;
+
+#if 1
+	u32tmp1 = halbtc8822b1ant_ltecoex_indirect_read_reg(btcoexist,
+			0x38);
+	u32tmp2 = halbtc8822b1ant_ltecoex_indirect_read_reg(btcoexist,
+			0x54);
+	u32tmp3 = btcoexist->btc_read_4byte(btcoexist, 0xcb4);
+
+	u8tmp  = btcoexist->btc_read_1byte(btcoexist, 0x73);
+
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+		"[BTCoex], ********** (Before Ant Setup) 0xcb4 = 0x%x, 0x73 = 0x%x, 0x38= 0x%x, 0x54= 0x%x**********\n",
+		    u32tmp3, u8tmp, u32tmp1, u32tmp2);
+	BTC_TRACE(trace_buf);
+#endif
+
+	switch (phase) {
+	case BT_8822B_1ANT_PHASE_COEX_INIT:
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			"[BTCoex], ********** (set_ant_path - 1ANT_PHASE_COEX_INIT) **********\n");
+		BTC_TRACE(trace_buf);
+
+		/* Disable LTE Coex Function in WiFi side (this should be on if LTE coex is required) */
+		halbtc8822b1ant_ltecoex_enable(btcoexist, 0x0);
+
+		/* GNT_WL_LTE always = 1 (this should be config if LTE coex is required) */
+		halbtc8822b1ant_ltecoex_set_coex_table(btcoexist,
+					       BT_8822B_1ANT_CTT_WL_VS_LTE,
+						       0xffff);
+
+		/* GNT_BT_LTE always = 1 (this should be config if LTE coex is required) */
+		halbtc8822b1ant_ltecoex_set_coex_table(btcoexist,
+					       BT_8822B_1ANT_CTT_BT_VS_LTE,
+						       0xffff);
+
+		/* set GNT_BT to SW high */
+		halbtc8822b1ant_ltecoex_set_gnt_bt(btcoexist,
+					   BT_8822B_1ANT_GNT_BLOCK_RFC_BB,
+						   BT_8822B_1ANT_GNT_CTRL_BY_SW,
+					   BT_8822B_1ANT_SIG_STA_SET_TO_HIGH);
+
+		/* set GNT_WL to SW low */
+		halbtc8822b1ant_ltecoex_set_gnt_wl(btcoexist,
+					   BT_8822B_1ANT_GNT_BLOCK_RFC_BB,
+						   BT_8822B_1ANT_GNT_CTRL_BY_SW,
+					   BT_8822B_1ANT_SIG_STA_SET_TO_LOW);
+
+		/* set Path control owner to WL at initial step */
+		halbtc8822b1ant_ltecoex_pathcontrol_owner(btcoexist,
+				BT_8822B_1ANT_PCO_WLSIDE);
+
+		coex_sta->run_time_state = false;
+
+		/* Ext switch buffer mux */
+		btcoexist->btc_write_1byte(btcoexist, 0x974, 0xff);
+		btcoexist->btc_write_1byte_bitmask(btcoexist, 0x1991,
+						   0x3, 0x0);
+		btcoexist->btc_write_1byte_bitmask(btcoexist, 0xcbe,
+						   0x8, 0x0);
+
+		if (BTC_ANT_PATH_AUTO == ant_pos_type)
+			ant_pos_type = BTC_ANT_PATH_BT;
+
+		break;
+	case BT_8822B_1ANT_PHASE_WLANONLY_INIT:
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			"[BTCoex], ********** (set_ant_path - 1ANT_PHASE_WLANONLY_INIT) **********\n");
+		BTC_TRACE(trace_buf);
+
+		/* Disable LTE Coex Function in WiFi side (this should be on if LTE coex is required) */
+		halbtc8822b1ant_ltecoex_enable(btcoexist, 0x0);
+
+		/* GNT_WL_LTE always = 1 (this should be config if LTE coex is required) */
+		halbtc8822b1ant_ltecoex_set_coex_table(btcoexist,
+					       BT_8822B_1ANT_CTT_WL_VS_LTE,
+						       0xffff);
+
+		/* GNT_BT_LTE always = 1 (this should be config if LTE coex is required) */
+		halbtc8822b1ant_ltecoex_set_coex_table(btcoexist,
+					       BT_8822B_1ANT_CTT_BT_VS_LTE,
+						       0xffff);
+
+		/* set GNT_BT to SW Low */
+		halbtc8822b1ant_ltecoex_set_gnt_bt(btcoexist,
+					   BT_8822B_1ANT_GNT_BLOCK_RFC_BB,
+						   BT_8822B_1ANT_GNT_CTRL_BY_SW,
+					   BT_8822B_1ANT_SIG_STA_SET_TO_LOW);
+
+		/* Set GNT_WL to SW high */
+		halbtc8822b1ant_ltecoex_set_gnt_wl(btcoexist,
+					   BT_8822B_1ANT_GNT_BLOCK_RFC_BB,
+						   BT_8822B_1ANT_GNT_CTRL_BY_SW,
+					   BT_8822B_1ANT_SIG_STA_SET_TO_HIGH);
+
+		/* set Path control owner to WL at initial step */
+		halbtc8822b1ant_ltecoex_pathcontrol_owner(btcoexist,
+				BT_8822B_1ANT_PCO_WLSIDE);
+
+		coex_sta->run_time_state = false;
+
+		/* Ext switch buffer mux */
+		btcoexist->btc_write_1byte(btcoexist, 0x974, 0xff);
+		btcoexist->btc_write_1byte_bitmask(btcoexist, 0x1991,
+						   0x3, 0x0);
+		btcoexist->btc_write_1byte_bitmask(btcoexist, 0xcbe,
+						   0x8, 0x0);
+
+		if (BTC_ANT_PATH_AUTO == ant_pos_type)
+			ant_pos_type = BTC_ANT_PATH_WIFI;
+
+		break;
+	case BT_8822B_1ANT_PHASE_WLAN_OFF:
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			"[BTCoex], ********** (set_ant_path - 1ANT_PHASE_WLAN_OFF) **********\n");
+		BTC_TRACE(trace_buf);
+
+		/* Disable LTE Coex Function in WiFi side */
+		halbtc8822b1ant_ltecoex_enable(btcoexist, 0x0);
+
+		/* set Path control owner to BT */
+		halbtc8822b1ant_ltecoex_pathcontrol_owner(btcoexist,
+				BT_8822B_1ANT_PCO_BTSIDE);
+
+		/* Set Ext Ant Switch to BT control at wifi off step */
+		halbtc8822b1ant_set_ext_ant_switch(btcoexist,
+						   FORCE_EXEC,
+				   BT_8822B_1ANT_EXT_ANT_SWITCH_CTRL_BY_BT,
+				   BT_8822B_1ANT_EXT_ANT_SWITCH_TO_NOCARE);
+
+		coex_sta->run_time_state = false;
+
+		break;
+	case BT_8822B_1ANT_PHASE_2G_RUNTIME:
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			"[BTCoex], ********** (set_ant_path - 1ANT_PHASE_2G_RUNTIME) **********\n");
+		BTC_TRACE(trace_buf);
+
+		/* set GNT_BT to PTA */
+		halbtc8822b1ant_ltecoex_set_gnt_bt(btcoexist,
+					   BT_8822B_1ANT_GNT_BLOCK_RFC_BB,
+					   BT_8822B_1ANT_GNT_CTRL_BY_PTA,
+					   BT_8822B_1ANT_SIG_STA_SET_BY_HW);
+
+		/* Set GNT_WL to PTA */
+		halbtc8822b1ant_ltecoex_set_gnt_wl(btcoexist,
+					   BT_8822B_1ANT_GNT_BLOCK_RFC_BB,
+					   BT_8822B_1ANT_GNT_CTRL_BY_PTA,
+					   BT_8822B_1ANT_SIG_STA_SET_BY_HW);
+
+		/* set Path control owner to WL at runtime step */
+		halbtc8822b1ant_ltecoex_pathcontrol_owner(btcoexist,
+				BT_8822B_1ANT_PCO_WLSIDE);
+
+		coex_sta->run_time_state = true;
+
+		if (BTC_ANT_PATH_AUTO == ant_pos_type)
+			ant_pos_type = BTC_ANT_PATH_PTA;
+
+		break;
+	case BT_8822B_1ANT_PHASE_5G_RUNTIME:
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			"[BTCoex], ********** (set_ant_path - 1ANT_PHASE_5G_RUNTIME) **********\n");
+		BTC_TRACE(trace_buf);
+
+		/* set GNT_BT to SW Hi */
+		halbtc8822b1ant_ltecoex_set_gnt_bt(btcoexist,
+					   BT_8822B_1ANT_GNT_BLOCK_RFC_BB,
+						   BT_8822B_1ANT_GNT_CTRL_BY_SW,
+					   BT_8822B_1ANT_SIG_STA_SET_TO_HIGH);
+
+		/* Set GNT_WL to SW Hi */
+		halbtc8822b1ant_ltecoex_set_gnt_wl(btcoexist,
+					   BT_8822B_1ANT_GNT_BLOCK_RFC_BB,
+						   BT_8822B_1ANT_GNT_CTRL_BY_SW,
+					   BT_8822B_1ANT_SIG_STA_SET_TO_HIGH);
+
+		/* set Path control owner to WL at runtime step */
+		halbtc8822b1ant_ltecoex_pathcontrol_owner(btcoexist,
+				BT_8822B_1ANT_PCO_WLSIDE);
+
+		coex_sta->run_time_state = true;
+
+		if (BTC_ANT_PATH_AUTO == ant_pos_type)
+			ant_pos_type =
+				BTC_ANT_PATH_WIFI5G;
+
+		break;
+	case BT_8822B_1ANT_PHASE_BTMPMODE:
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			"[BTCoex], ********** (set_ant_path - 1ANT_PHASE_BTMPMODE) **********\n");
+		BTC_TRACE(trace_buf);
+
+		/* Disable LTE Coex Function in WiFi side */
+		halbtc8822b1ant_ltecoex_enable(btcoexist, 0x0);
+
+		/* set GNT_BT to SW Hi */
+		halbtc8822b1ant_ltecoex_set_gnt_bt(btcoexist,
+					   BT_8822B_1ANT_GNT_BLOCK_RFC_BB,
+						   BT_8822B_1ANT_GNT_CTRL_BY_SW,
+					   BT_8822B_1ANT_SIG_STA_SET_TO_HIGH);
+
+		/* Set GNT_WL to SW Lo */
+		halbtc8822b1ant_ltecoex_set_gnt_wl(btcoexist,
+					   BT_8822B_1ANT_GNT_BLOCK_RFC_BB,
+						   BT_8822B_1ANT_GNT_CTRL_BY_SW,
+					   BT_8822B_1ANT_SIG_STA_SET_TO_LOW);
+
+		/* set Path control owner to WL */
+		halbtc8822b1ant_ltecoex_pathcontrol_owner(btcoexist,
+				BT_8822B_1ANT_PCO_WLSIDE);
+
+		coex_sta->run_time_state = false;
+
+		/* Set Ext Ant Switch to BT side at BT MP mode */
+		if (BTC_ANT_PATH_AUTO == ant_pos_type)
+			ant_pos_type = BTC_ANT_PATH_BT;
+
+		break;
+	}
+
+
+	if (phase != BT_8822B_1ANT_PHASE_WLAN_OFF) {
+		switch (ant_pos_type) {
+		case BTC_ANT_PATH_WIFI:
+			halbtc8822b1ant_set_ext_ant_switch(
+				btcoexist,
+				force_exec,
+				BT_8822B_1ANT_EXT_ANT_SWITCH_CTRL_BY_BBSW,
+				BT_8822B_1ANT_EXT_ANT_SWITCH_TO_WLG);
+			break;
+		case BTC_ANT_PATH_WIFI5G
+				:
+			halbtc8822b1ant_set_ext_ant_switch(
+				btcoexist,
+				force_exec,
+				BT_8822B_1ANT_EXT_ANT_SWITCH_CTRL_BY_BBSW,
+				BT_8822B_1ANT_EXT_ANT_SWITCH_TO_WLA);
+			break;
+		case BTC_ANT_PATH_BT:
+			halbtc8822b1ant_set_ext_ant_switch(
+				btcoexist,
+				force_exec,
+				BT_8822B_1ANT_EXT_ANT_SWITCH_CTRL_BY_BBSW,
+				BT_8822B_1ANT_EXT_ANT_SWITCH_TO_BT);
+			break;
+		default:
+		case BTC_ANT_PATH_PTA:
+			halbtc8822b1ant_set_ext_ant_switch(
+				btcoexist,
+				force_exec,
+				BT_8822B_1ANT_EXT_ANT_SWITCH_CTRL_BY_PTA,
+				BT_8822B_1ANT_EXT_ANT_SWITCH_TO_NOCARE);
+			break;
+		}
+
+	}
+#if 1
+	u32tmp1 = halbtc8822b1ant_ltecoex_indirect_read_reg(btcoexist, 0x38);
+	u32tmp2 = halbtc8822b1ant_ltecoex_indirect_read_reg(btcoexist, 0x54);
+	u32tmp3 = btcoexist->btc_read_4byte(btcoexist, 0xcb4);
+
+	u8tmp  = btcoexist->btc_read_1byte(btcoexist, 0x73);
+
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+		"[BTCoex], ********** (After Ant Setup) 0xcb4 = 0x%x, 0x73 = 0x%x, 0x38= 0x%x, 0x54= 0x%x**********\n",
+		    u32tmp3, u8tmp, u32tmp1, u32tmp2);
+	BTC_TRACE(trace_buf);
+
+#endif
+
+}
+
+
+void halbtc8822b1ant_coex_all_off(IN struct btc_coexist *btcoexist)
+{
+	/* sw all off */
+	halbtc8822b1ant_sw_mechanism(btcoexist, false);
+
+	/* hw all off */
+	halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0);
+}
+boolean halbtc8822b1ant_is_common_action(IN struct btc_coexist *btcoexist)
+{
+	boolean			common = false, wifi_connected = false, wifi_busy = false;
+
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED,
+			   &wifi_connected);
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy);
+
+	if (!wifi_connected &&
+	    BT_8822B_1ANT_BT_STATUS_NON_CONNECTED_IDLE ==
+	    coex_dm->bt_status) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			"[BTCoex], Wifi non connected-idle + BT non connected-idle!!\n");
+		BTC_TRACE(trace_buf);
+
+		/* halbtc8822b1ant_sw_mechanism(btcoexist, false); */
+
+		common = true;
+	} else if (wifi_connected &&
+		   (BT_8822B_1ANT_BT_STATUS_NON_CONNECTED_IDLE ==
+		    coex_dm->bt_status)) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			"[BTCoex], Wifi connected + BT non connected-idle!!\n");
+		BTC_TRACE(trace_buf);
+
+		/* halbtc8822b1ant_sw_mechanism(btcoexist, false); */
+
+		common = true;
+	} else if (!wifi_connected &&
+		   (BT_8822B_1ANT_BT_STATUS_CONNECTED_IDLE ==
+		    coex_dm->bt_status)) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			"[BTCoex], Wifi non connected-idle + BT connected-idle!!\n");
+		BTC_TRACE(trace_buf);
+
+		/* halbtc8822b1ant_sw_mechanism(btcoexist, false); */
+
+		common = true;
+	} else if (wifi_connected &&
+		   (BT_8822B_1ANT_BT_STATUS_CONNECTED_IDLE ==
+		    coex_dm->bt_status)) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], Wifi connected + BT connected-idle!!\n");
+		BTC_TRACE(trace_buf);
+
+		/* halbtc8822b1ant_sw_mechanism(btcoexist, false); */
+
+		common = true;
+	} else if (!wifi_connected &&
+		   (BT_8822B_1ANT_BT_STATUS_CONNECTED_IDLE !=
+		    coex_dm->bt_status)) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], Wifi non connected-idle + BT Busy!!\n");
+		BTC_TRACE(trace_buf);
+
+		/* halbtc8822b1ant_sw_mechanism(btcoexist, false); */
+
+		common = true;
+	} else {
+		if (wifi_busy) {
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				"[BTCoex], Wifi Connected-Busy + BT Busy!!\n");
+			BTC_TRACE(trace_buf);
+		} else {
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				"[BTCoex], Wifi Connected-Idle + BT Busy!!\n");
+			BTC_TRACE(trace_buf);
+		}
+
+		common = false;
+	}
+
+	return common;
+}
+
+void halbtc8822b1ant_action_wifi_under5g(IN struct btc_coexist *btcoexist)
+{
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+		    "[BTCoex], under 5g start\n");
+	BTC_TRACE(trace_buf);
+	/* for test : s3 bt disappear , fail rate 1/600*/
+/*
+	halbtc8822b1ant_ignore_wlan_act(btcoexist, NORMAL_EXEC, true);
+*/
+/*set sw gnt wl bt  high*/
+	halbtc8822b1ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, FORCE_EXEC,
+							 BT_8822B_1ANT_PHASE_5G_RUNTIME);
+
+	halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 8);
+	halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0);
+	btcoexist->btc_write_1byte_bitmask(btcoexist, 0xcbd,
+						   0x3, 1);
+/*
+	halbtc8822b1ant_limited_tx(btcoexist, NORMAL_EXEC, 0, 0, 0, 0);
+
+	halbtc8822b1ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, 5);
+*/
+}
+
+
+
+void halbtc8822b1ant_action_wifi_only(IN struct btc_coexist *btcoexist)
+{
+	boolean wifi_under_5g = false, rf4ce_enabled = false;
+
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_5G, &wifi_under_5g);
+	if (wifi_under_5g) {
+		halbtc8822b1ant_action_wifi_under5g(btcoexist);
+
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			"[BTCoex], ********** (wlan only -- under 5g ) **********\n");
+		BTC_TRACE(trace_buf);
+		return;
+	}
+
+	if (rf4ce_enabled) {
+				btcoexist->btc_write_1byte_bitmask(
+					btcoexist, 0x45e, 0x8, 0x1);
+
+				halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC,
+							true,
+							50);
+
+				halbtc8822b1ant_coex_table_with_type(btcoexist,
+				NORMAL_EXEC, 1);
+		return;
+		}
+	halbtc8822b1ant_coex_table_with_type(btcoexist, FORCE_EXEC, 0);
+	halbtc8822b1ant_ps_tdma(btcoexist, FORCE_EXEC, false, 8);
+
+	halbtc8822b1ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, FORCE_EXEC,
+				     BT_8822B_1ANT_PHASE_2G_RUNTIME);
+
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+		"[BTCoex], ********** (wlan only -- under 2g ) **********\n");
+	BTC_TRACE(trace_buf);
+
+}
+
+/* *********************************************
+ *
+ *	Software Coex Mechanism start
+ *
+ * ********************************************* */
+
+/* SCO only or SCO+PAN(HS) */
+
+/*
+void halbtc8822b1ant_action_sco(IN struct btc_coexist* btcoexist)
+{
+	halbtc8822b1ant_sw_mechanism(btcoexist, true);
+}
+
+
+void halbtc8822b1ant_action_hid(IN struct btc_coexist* btcoexist)
+{
+	halbtc8822b1ant_sw_mechanism(btcoexist, true);
+}
+
+
+void halbtc8822b1ant_action_a2dp(IN struct btc_coexist* btcoexist)
+{
+	halbtc8822b1ant_sw_mechanism(btcoexist, false);
+}
+
+void halbtc8822b1ant_action_a2dp_pan_hs(IN struct btc_coexist* btcoexist)
+{
+	halbtc8822b1ant_sw_mechanism(btcoexist, false);
+}
+
+void halbtc8822b1ant_action_pan_edr(IN struct btc_coexist* btcoexist)
+{
+	halbtc8822b1ant_sw_mechanism(btcoexist, false);
+}
+
+
+void halbtc8822b1ant_action_pan_hs(IN struct btc_coexist* btcoexist)
+{
+	halbtc8822b1ant_sw_mechanism(btcoexist, false);
+}
+
+
+void halbtc8822b1ant_action_pan_edr_a2dp(IN struct btc_coexist* btcoexist)
+{
+	halbtc8822b1ant_sw_mechanism(btcoexist, false);
+}
+
+void halbtc8822b1ant_action_pan_edr_hid(IN struct btc_coexist* btcoexist)
+{
+	halbtc8822b1ant_sw_mechanism(btcoexist, true);
+}
+
+
+void halbtc8822b1ant_action_hid_a2dp_pan_edr(IN struct btc_coexist* btcoexist)
+{
+	halbtc8822b1ant_sw_mechanism(btcoexist, true);
+}
+
+void halbtc8822b1ant_action_hid_a2dp(IN struct btc_coexist* btcoexist)
+{
+	halbtc8822b1ant_sw_mechanism(btcoexist, true);
+}
+
+*/
+
+/* *********************************************
+ *
+ *	Non-Software Coex Mechanism start
+ *
+ * ********************************************* */
+void halbtc8822b1ant_action_bt_whck_test(IN struct btc_coexist *btcoexist)
+{
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+		    "[BTCoex],action_bt_whck_test\n");
+	BTC_TRACE(trace_buf);
+
+	halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 8);
+
+	halbtc8822b1ant_set_ant_path(btcoexist,
+				     BTC_ANT_PATH_AUTO,
+				     NORMAL_EXEC,
+				     BT_8822B_1ANT_PHASE_2G_RUNTIME);
+
+	halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0);
+}
+
+void halbtc8822b1ant_action_wifi_multi_port(IN struct btc_coexist *btcoexist)
+{
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+		    "[BTCoex],action_wifi_multi_port\n");
+	BTC_TRACE(trace_buf);
+
+	halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 8);
+
+	halbtc8822b1ant_set_ant_path(btcoexist,
+				     BTC_ANT_PATH_AUTO,
+				     NORMAL_EXEC,
+				     BT_8822B_1ANT_PHASE_2G_RUNTIME);
+
+	halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0);
+}
+
+void halbtc8822b1ant_action_hs(IN struct btc_coexist *btcoexist)
+{
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+		    "[BTCoex], action_hs\n");
+	BTC_TRACE(trace_buf);
+
+	halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 5);
+
+	halbtc8822b1ant_set_ant_path(btcoexist,
+				     BTC_ANT_PATH_AUTO,
+				     NORMAL_EXEC,
+				     BT_8822B_1ANT_PHASE_2G_RUNTIME);
+
+	halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 5);
+}
+
+/*"""bt inquiry"""" + wifi any + bt any*/
+void halbtc8822b1ant_action_bt_inquiry(IN struct btc_coexist *btcoexist)
+{
+
+	struct  btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
+	boolean			wifi_connected = false, ap_enable = false, wifi_busy = false,
+				bt_busy = false, rf4ce_enabled = false;
+
+
+	boolean		wifi_scan = false, link = false, roam = false;
+
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+		    "[BTCoex], ********** (bt inquiry) **********\n");
+	BTC_TRACE(trace_buf);
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_AP_MODE_ENABLE,
+			   &ap_enable);
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED,
+			   &wifi_connected);
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy);
+	btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_TRAFFIC_BUSY, &bt_busy);
+
+
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_SCAN, &wifi_scan);
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_LINK, &link);
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_ROAM, &roam);
+
+
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+		"[BTCoex], ********** scan = %d,  link =%d, roam = %d**********\n",
+		    wifi_scan, link, roam);
+	BTC_TRACE(trace_buf);
+
+	if ((link) || (roam) || (coex_sta->wifi_is_high_pri_task)) {
+
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			"[BTCoex], ********** (bt inquiry wifi  connect or scan ) **********\n");
+		BTC_TRACE(trace_buf);
+
+		halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 1);
+
+		halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 6);
+
+	} else if ((wifi_scan) && (coex_sta->bt_create_connection)) {
+
+		halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 22);
+		halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 6);
+
+	} else if ((!wifi_connected) && (!wifi_scan)) {
+
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			"[BTCoex], ********** (bt inquiry wifi non connect) **********\n");
+		BTC_TRACE(trace_buf);
+
+		halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 8);
+
+		halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0);
+
+	} else if ((bt_link_info->a2dp_exist) && (bt_link_info->pan_exist)) {
+
+		halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 22);
+		halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4);
+	} else if (bt_link_info->a2dp_exist) {
+
+		halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 32);
+
+		halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 3);
+	} else if (wifi_scan) {
+
+		halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 20);
+
+		halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4);
+	} else if (wifi_busy) {
+
+		/* for BT inquiry/page fail after S4 resume */
+		/* halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 20);		 */
+		halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 32);
+/*aaaa->55aa for bt connect while wl busy*/
+		halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC,
+						     15);
+	if (rf4ce_enabled) {
+				btcoexist->btc_write_1byte_bitmask(
+					btcoexist, 0x45e, 0x8, 0x1);
+
+				halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC,
+							true,
+							50);
+
+				halbtc8822b1ant_coex_table_with_type(btcoexist,
+				NORMAL_EXEC, 0);
+
+		}
+	} else {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			"[BTCoex], ********** (bt inquiry wifi connect) **********\n");
+		BTC_TRACE(trace_buf);
+
+		halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 22);
+
+		halbtc8822b1ant_set_ant_path(btcoexist,
+					     BTC_ANT_PATH_AUTO,
+					     NORMAL_EXEC,
+					     BT_8822B_1ANT_PHASE_2G_RUNTIME);
+
+		halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC,
+						     4);
+	}
+
+	/*
+		if ((wifi_link) || (wifi_roam) || (coex_sta->wifi_is_high_pri_task)) {
+
+			halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 33);
+			halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 6);
+
+		} else if ((wifi_scan) && (coex_sta->bt_create_connection)) {
+
+			halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 22);
+			halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 6);
+
+		} else if ((!wifi_connected) && (!wifi_scan)) {
+
+			halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 8);
+
+			halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0);
+		} else if ((bt_link_info->a2dp_exist) && (bt_link_info->pan_exist)) {
+
+			halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 22);
+			halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4);
+
+		} else if (bt_link_info->a2dp_exist) {
+
+			halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 32);
+
+			halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4);
+		} else if (wifi_scan) {
+
+			halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 20);
+
+			halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4);
+
+		} else if (wifi_busy) {
+			halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 21);
+
+			halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4);
+		} else {
+			halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 19);
+
+			halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4);
+		}
+	*/
+}
+
+void halbtc8822b1ant_action_bt_sco_hid_only_busy(IN struct btc_coexist
+		*btcoexist, IN u8 wifi_status)
+{
+
+	struct  btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
+
+	btcoexist->btc_write_1byte_bitmask(btcoexist, 0x45e, 0x8, 0x1);
+
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+		    "[BTCoex], ********** (bt sco hid only busy) **********\n");
+	BTC_TRACE(trace_buf);
+
+	/*SCO  + wifi connected idle or busy / 0x778=1@wifi slot*/
+	if (bt_link_info->sco_exist) {
+
+		btcoexist->btc_write_1byte_bitmask(btcoexist, 0x45e, 0x8, 0x1);
+		halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 5);
+		/*case16 for connect SCO first then connect a2sp fail issue*/
+		halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 16);
+
+	} else { /* HID  + wifi connected idle or busy / 0x778=1@wifi slot */
+
+		btcoexist->btc_write_1byte_bitmask(btcoexist, 0x45e, 0x8, 0x1);
+
+		halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 5);
+		/*case16 for connect HID first then connect a2sp fail issue*/
+		halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 16);
+
+	}
+}
+
+/*wifi connected + bt acl busy*/
+void halbtc8822b1ant_action_wifi_connected_bt_acl_busy(IN struct btc_coexist
+		*btcoexist, IN u8 wifi_status)
+{
+
+	u8		bt_rssi_state;
+	struct	btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
+	boolean	wifi_busy = false, wifi_turbo = false;
+	u32  wifi_bw = 1;
+
+	btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW,
+				   &wifi_bw);
+btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy);
+	btcoexist->btc_get(btcoexist, BTC_GET_U1_AP_NUM,
+				   &coex_sta->scan_ap_num);
+	bt_rssi_state = halbtc8822b1ant_bt_rssi_state(2, 28, 0);
+
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+"[BTCoex], ********** (wifi connect acl busy) **********\n");
+	BTC_TRACE(trace_buf);
+
+
+
+	if (bt_link_info->hid_only) { /* HID  + wifi connected idle or busy / 0x778=1@wifi slot */
+
+
+
+
+		btcoexist->btc_write_1byte_bitmask(
+			btcoexist, 0x45e, 0x8, 0x1);
+
+
+
+		halbtc8822b1ant_action_bt_sco_hid_only_busy(btcoexist,
+				wifi_status);
+		return;
+	} else if (
+		bt_link_info->a2dp_only) { /* A2DP  + wifi connected idle or busy */
+		if (BT_8822B_1ANT_WIFI_STATUS_CONNECTED_IDLE == wifi_status) {
+
+
+			btcoexist->btc_write_1byte_bitmask(btcoexist, 0x45e,
+							   0x8, 0x1);
+
+			halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true,
+						32);
+			halbtc8822b1ant_coex_table_with_type(btcoexist,
+							     NORMAL_EXEC, 0);
+		} else {
+			if (coex_sta->scan_ap_num >=
+			    BT_8822B_1ANT_WIFI_NOISY_THRESH)  {
+				halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC,
+							true,
+							17);
+			}	else {
+
+
+
+
+				btcoexist->btc_write_1byte_bitmask(
+					btcoexist, 0x45e, 0x8, 0x1);
+
+				halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC,
+							true,
+							42);
+
+				halbtc8822b1ant_coex_table_with_type(btcoexist,
+				NORMAL_EXEC, 1);
+		}
+/*
+			halbtc8822b1ant_coex_table_with_type(btcoexist,
+							     NORMAL_EXEC, 1);
+*/
+			coex_dm->auto_tdma_adjust = true;
+		}
+
+		/* A2DP+PAN(OPP,FTP), HID+A2DP+PAN(OPP,FTP) */
+	} else if (((bt_link_info->a2dp_exist) && (bt_link_info->pan_exist)) ||
+		   (bt_link_info->hid_exist && bt_link_info->a2dp_exist &&
+		bt_link_info->pan_exist)) { /* A2DP+PAN(OPP,FTP), HID+A2DP+PAN(OPP,FTP) */
+
+		btcoexist->btc_write_1byte_bitmask(btcoexist, 0x45e, 0x8, 0x1);
+		halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 47);
+		halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC,
+						     6);
+	} else if (bt_link_info->hid_exist &&
+		   bt_link_info->a2dp_exist) { /* HID+A2DP */
+
+		btcoexist->btc_write_1byte_bitmask(
+			btcoexist, 0x45e, 0x8, 0x1);
+		if (!wifi_busy) {
+/*a2dp glitch while wl idle , change the 0x6c0=5a5a5a5a->5555or aaaa55aa*/
+		halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0);
+		halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC,
+								true,
+								32);
+			} else if (wifi_bw == 0) { /* 11bg mode */
+			halbtc8822b1ant_coex_table_with_type(btcoexist,
+										 NORMAL_EXEC, 1);
+
+		halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC,
+								true,
+								42);
+		} else {
+		/*if in open space , and ask wl tp , 0x60=6135031111,55555555,aaaa55aa*/
+		halbtc8822b1ant_coex_table_with_type(btcoexist,
+										 NORMAL_EXEC, 1);
+		halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 42);
+}
+		/*
+				halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC,
+								     1);
+		*/
+
+
+
+
+	} else if ((bt_link_info->pan_only) || (bt_link_info->hid_exist &&
+		bt_link_info->pan_exist)) { /* PAN(OPP,FTP), HID+PAN(OPP,FTP)*/
+		/*
+		if (BT_8723D_1ANT_WIFI_STATUS_CONNECTED_IDLE == wifi_status)
+			halbtc8723d1ant_ps_tdma(btcoexist, NORMAL_EXEC, true,
+						4);
+		else
+		*/
+
+		btcoexist->btc_write_1byte_bitmask(btcoexist, 0x45e, 0x8, 0x1);
+		halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 47);
+		halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC,
+						     1);
+	} else {
+		/* BT no-profile busy (0x9) */
+
+		btcoexist->btc_write_1byte_bitmask(btcoexist, 0x45e, 0x8, 0x1);
+		halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 33);
+		halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC,
+						     1);
+	}
+}
+
+/*wifi not connected + bt action*/
+void halbtc8822b1ant_action_wifi_not_connected(IN struct btc_coexist *btcoexist)
+{
+	boolean wifi_under_5g = false, rf4ce_enabled = false;
+
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+		    "[BTCoex], ********** (wifi not connect) **********\n");
+	BTC_TRACE(trace_buf);
+
+	/* tdma and coex table */
+	if (rf4ce_enabled) {
+				btcoexist->btc_write_1byte_bitmask(
+					btcoexist, 0x45e, 0x8, 0x1);
+
+				halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC,
+							true,
+							50);
+
+				halbtc8822b1ant_coex_table_with_type(btcoexist,
+				NORMAL_EXEC, 1);
+		return;
+		}
+	halbtc8822b1ant_ps_tdma(btcoexist, FORCE_EXEC, false, 8);
+
+	halbtc8822b1ant_set_ant_path(btcoexist,
+				     BTC_ANT_PATH_AUTO,
+				     NORMAL_EXEC,
+				     BT_8822B_1ANT_PHASE_2G_RUNTIME);
+
+	halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0);
+}
+
+/*""""wl not connected scan"""" + bt action*/
+void halbtc8822b1ant_action_wifi_not_connected_scan(IN struct btc_coexist
+		*btcoexist)
+{
+
+	struct  btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
+	boolean wifi_connected = false, bt_hs_on = false;
+	u32	wifi_link_status = 0;
+	u32	num_of_wifi_link = 0;
+	boolean	bt_ctrl_agg_buf_size = false;
+	u8	agg_buf_size = 5;
+
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+		"[BTCoex], ********** (wifi non connect scan) **********\n");
+	BTC_TRACE(trace_buf);
+
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on);
+	btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_LINK_STATUS,
+			   &wifi_link_status);
+
+	num_of_wifi_link = wifi_link_status >> 16;
+
+	if (num_of_wifi_link >= 2) {
+		halbtc8822b1ant_limited_tx(btcoexist, NORMAL_EXEC, 0, 0, 0, 0);
+		halbtc8822b1ant_limited_rx(btcoexist, NORMAL_EXEC, false,
+					   bt_ctrl_agg_buf_size, agg_buf_size);
+
+		if (coex_sta->c2h_bt_inquiry_page) {
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				"############# [BTCoex],  BT Is Inquirying\n");
+			BTC_TRACE(trace_buf);
+			halbtc8822b1ant_action_bt_inquiry(btcoexist);
+		} else
+			halbtc8822b1ant_action_wifi_multi_port(btcoexist);
+		return;
+	}
+
+	if (coex_sta->c2h_bt_inquiry_page) {
+		halbtc8822b1ant_action_bt_inquiry(btcoexist);
+		return;
+	} else if (bt_hs_on) {
+		halbtc8822b1ant_action_hs(btcoexist);
+		return;
+	}
+
+	/* tdma and coex table */
+	if (BT_8822B_1ANT_BT_STATUS_ACL_BUSY == coex_dm->bt_status) {
+		if (bt_link_info->a2dp_exist) {
+			halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true,
+						32);
+			halbtc8822b1ant_coex_table_with_type(btcoexist,
+							     NORMAL_EXEC, 1);
+		} else if (bt_link_info->a2dp_exist &&
+			   bt_link_info->pan_exist) {
+			halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true,
+						22);
+			halbtc8822b1ant_coex_table_with_type(btcoexist,
+							     NORMAL_EXEC, 1);
+		} else {
+			halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true,
+						20);
+			halbtc8822b1ant_coex_table_with_type(btcoexist,
+							     NORMAL_EXEC, 1);
+		}
+	} else if ((BT_8822B_1ANT_BT_STATUS_SCO_BUSY == coex_dm->bt_status) ||
+		   (BT_8822B_1ANT_BT_STATUS_ACL_SCO_BUSY ==
+		    coex_dm->bt_status)) {
+		halbtc8822b1ant_action_bt_sco_hid_only_busy(btcoexist,
+				BT_8822B_1ANT_WIFI_STATUS_CONNECTED_SCAN);
+	} else {
+
+		halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 8);
+
+		halbtc8822b1ant_set_ant_path(btcoexist,
+					     BTC_ANT_PATH_AUTO,
+					     NORMAL_EXEC,
+					     BT_8822B_1ANT_PHASE_2G_RUNTIME);
+
+		halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC,
+						     5);
+	}
+}
+
+/*""""wl not connected asso"""" + bt action*/
+void halbtc8822b1ant_action_wifi_not_connected_asso_auth(
+	IN struct btc_coexist *btcoexist)
+{
+
+	struct	btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
+	boolean wifi_connected = false, bt_hs_on = false;
+	u32 wifi_link_status = 0;
+	u32 num_of_wifi_link = 0;
+	boolean bt_ctrl_agg_buf_size = false;
+	u8	agg_buf_size = 5;
+
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+		"[BTCoex], ********** (wifi non connect asso_auth) **********\n");
+	BTC_TRACE(trace_buf);
+
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on);
+	btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_LINK_STATUS,
+			   &wifi_link_status);
+
+	num_of_wifi_link = wifi_link_status >> 16;
+
+	if (num_of_wifi_link >= 2) {
+
+		halbtc8822b1ant_limited_tx(btcoexist, NORMAL_EXEC, 0, 0, 0, 0);
+		halbtc8822b1ant_limited_rx(btcoexist, NORMAL_EXEC, false,
+					   bt_ctrl_agg_buf_size,
+					   agg_buf_size);
+
+		if (coex_sta->c2h_bt_inquiry_page) {
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				"############# [BTCoex],  BT Is Inquirying\n");
+			BTC_TRACE(trace_buf);
+			halbtc8822b1ant_action_bt_inquiry(btcoexist);
+		} else
+			halbtc8822b1ant_action_wifi_multi_port(
+				btcoexist);
+		return;
+	}
+
+	if (coex_sta->c2h_bt_inquiry_page) {
+		halbtc8822b1ant_action_bt_inquiry(btcoexist);
+		return;
+	} else if (bt_hs_on) {
+		halbtc8822b1ant_action_hs(btcoexist);
+		return;
+	}
+
+
+	/* tdma and coex table */
+	if ((bt_link_info->sco_exist)  || (bt_link_info->hid_exist) ||
+	    (bt_link_info->a2dp_exist)) {
+
+		halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 32);
+		halbtc8822b1ant_coex_table_with_type(btcoexist, FORCE_EXEC, 4);
+	} else if (bt_link_info->pan_exist) {
+		halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 20);
+		halbtc8822b1ant_coex_table_with_type(btcoexist, FORCE_EXEC, 4);
+	} else {
+
+		halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 8);
+
+		halbtc8822b1ant_set_ant_path(btcoexist,
+					     BTC_ANT_PATH_AUTO,
+					     NORMAL_EXEC,
+					     BT_8822B_1ANT_PHASE_2G_RUNTIME);
+
+		halbtc8822b1ant_coex_table_with_type(btcoexist, FORCE_EXEC, 2);
+	}
+}
+
+/*""""wl  connected scan"""" + bt action*/
+void halbtc8822b1ant_action_wifi_connected_scan(IN struct btc_coexist
+		*btcoexist)
+{
+
+	struct  btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
+	boolean wifi_connected = false, bt_hs_on = false;
+	u32	wifi_link_status = 0;
+	u32	num_of_wifi_link = 0;
+	boolean	bt_ctrl_agg_buf_size = false;
+	u8	agg_buf_size = 5;
+
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+		    "[BTCoex], ********** (wifi connect scan) **********\n");
+	BTC_TRACE(trace_buf);
+
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on);
+	btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_LINK_STATUS,
+			   &wifi_link_status);
+
+	num_of_wifi_link = wifi_link_status >> 16;
+
+	if (num_of_wifi_link >= 2) {
+		halbtc8822b1ant_limited_tx(btcoexist, NORMAL_EXEC, 0, 0, 0, 0);
+		halbtc8822b1ant_limited_rx(btcoexist, NORMAL_EXEC, false,
+					   bt_ctrl_agg_buf_size, agg_buf_size);
+
+		if (coex_sta->c2h_bt_inquiry_page) {
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				"############# [BTCoex],  BT Is Inquirying\n");
+			BTC_TRACE(trace_buf);
+			halbtc8822b1ant_action_bt_inquiry(btcoexist);
+		} else
+			halbtc8822b1ant_action_wifi_multi_port(btcoexist);
+		return;
+	}
+
+	if (coex_sta->c2h_bt_inquiry_page) {
+		halbtc8822b1ant_action_bt_inquiry(btcoexist);
+		return;
+	} else if (bt_hs_on) {
+		halbtc8822b1ant_action_hs(btcoexist);
+		return;
+	}
+
+	/* tdma and coex table */
+	if (BT_8822B_1ANT_BT_STATUS_ACL_BUSY == coex_dm->bt_status) {
+		if (bt_link_info->a2dp_exist) {
+			halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true,
+						32);
+			halbtc8822b1ant_coex_table_with_type(btcoexist,
+							     NORMAL_EXEC, 1);
+		} else if (bt_link_info->a2dp_exist &&
+			   bt_link_info->pan_exist) {
+			halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true,
+						22);
+			halbtc8822b1ant_coex_table_with_type(btcoexist,
+							     NORMAL_EXEC, 1);
+		} else {
+			halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true,
+						20);
+			halbtc8822b1ant_coex_table_with_type(btcoexist,
+							     NORMAL_EXEC, 1);
+		}
+	} else if ((BT_8822B_1ANT_BT_STATUS_SCO_BUSY == coex_dm->bt_status) ||
+		   (BT_8822B_1ANT_BT_STATUS_ACL_SCO_BUSY ==
+		    coex_dm->bt_status)) {
+		halbtc8822b1ant_action_bt_sco_hid_only_busy(btcoexist,
+				BT_8822B_1ANT_WIFI_STATUS_CONNECTED_SCAN);
+	} else {
+
+		halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 8);
+
+		halbtc8822b1ant_set_ant_path(btcoexist,
+					     BTC_ANT_PATH_AUTO,
+					     NORMAL_EXEC,
+					     BT_8822B_1ANT_PHASE_2G_RUNTIME);
+
+		halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC,
+						     6);
+	}
+}
+
+/*""""wl  connected specific packet"""" + bt action*/
+void halbtc8822b1ant_action_wifi_connected_specific_packet(
+	IN struct btc_coexist *btcoexist)
+{
+
+	struct  btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
+	boolean wifi_connected = false, bt_hs_on = false;
+	u32	wifi_link_status = 0;
+	u32	num_of_wifi_link = 0;
+	boolean	bt_ctrl_agg_buf_size = false;
+	u8	agg_buf_size = 5;
+	boolean wifi_busy = false;
+
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+		"[BTCoex], ********** (wifi connect specific packet) **********\n");
+	BTC_TRACE(trace_buf);
+
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on);
+	btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_LINK_STATUS,
+			   &wifi_link_status);
+
+	num_of_wifi_link = wifi_link_status >> 16;
+
+	if (num_of_wifi_link >= 2) {
+		halbtc8822b1ant_limited_tx(btcoexist, NORMAL_EXEC, 0, 0, 0, 0);
+		halbtc8822b1ant_limited_rx(btcoexist, NORMAL_EXEC, false,
+					   bt_ctrl_agg_buf_size, agg_buf_size);
+
+		if (coex_sta->c2h_bt_inquiry_page) {
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				"############# [BTCoex],  BT Is Inquirying\n");
+			BTC_TRACE(trace_buf);
+			halbtc8822b1ant_action_bt_inquiry(btcoexist);
+		} else
+			halbtc8822b1ant_action_wifi_multi_port(btcoexist);
+		return;
+	}
+
+	if (coex_sta->c2h_bt_inquiry_page) {
+		halbtc8822b1ant_action_bt_inquiry(btcoexist);
+		return;
+	} else if (bt_hs_on) {
+		halbtc8822b1ant_action_hs(btcoexist);
+		return;
+	}
+
+
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy);
+
+	/* no specific packet process for both WiFi and BT very busy */
+	if ((wifi_busy) && ((bt_link_info->pan_exist) ||
+			    (coex_sta->num_of_profile >= 2)))
+		return;
+
+	/* tdma and coex table */
+	if ((bt_link_info->sco_exist) || (bt_link_info->hid_exist)) {
+		halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 32);
+		halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 5);
+	} else if (bt_link_info->a2dp_exist) {
+		halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 32);
+		/*for a2dp glitch,change from 1 to 15*/
+		halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC,
+						     15);
+	} else if (bt_link_info->pan_exist) {
+		halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 20);
+		halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC,
+						     1);
+	} else {
+
+		halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 8);
+
+		halbtc8822b1ant_set_ant_path(btcoexist,
+					     BTC_ANT_PATH_AUTO,
+					     NORMAL_EXEC,
+					     BT_8822B_1ANT_PHASE_2G_RUNTIME);
+
+		halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC,
+						     5);
+	}
+}
+
+/*wifi connected input point : to set different ps and tdma case (+bt different case)*/
+void halbtc8822b1ant_action_wifi_connected(IN struct btc_coexist *btcoexist)
+{
+
+	boolean	wifi_busy = false, rf4ce_enabled = false;
+	boolean		scan = false, link = false, roam = false;
+	boolean		under_4way = false, ap_enable = false, wifi_under_5g = false;
+	u8 wifi_rssi_state;
+
+
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+		    "[BTCoex], CoexForWifiConnect()===>\n");
+	BTC_TRACE(trace_buf);
+
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_5G, &wifi_under_5g);
+
+	if (wifi_under_5g) {
+
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			"[BTCoex], CoexForWifiConnect(), return for wifi is under 5g<===\n");
+		BTC_TRACE(trace_buf);
+
+		halbtc8822b1ant_action_wifi_under5g(btcoexist);
+
+		return;
+	}
+
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+		"[BTCoex], CoexForWifiConnect(), return for wifi is under 2g<===\n");
+	BTC_TRACE(trace_buf);
+
+	halbtc8822b1ant_set_ant_path(btcoexist,
+				     BTC_ANT_PATH_AUTO,
+				     NORMAL_EXEC,
+				     BT_8822B_1ANT_PHASE_2G_RUNTIME);
+
+
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_4_WAY_PROGRESS,
+			   &under_4way);
+
+	if (under_4way) {
+		halbtc8822b1ant_action_wifi_connected_specific_packet(
+			btcoexist);
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			"[BTCoex], CoexForWifiConnect(), return for wifi is under 4way<===\n");
+		BTC_TRACE(trace_buf);
+		return;
+	}
+
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_SCAN, &scan);
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_LINK, &link);
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_ROAM, &roam);
+	if (scan || link || roam) {
+		if (scan)
+			halbtc8822b1ant_action_wifi_connected_scan(btcoexist);
+		else
+			halbtc8822b1ant_action_wifi_connected_specific_packet(
+				btcoexist);
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			"[BTCoex], CoexForWifiConnect(), return for wifi is under scan<===\n");
+		BTC_TRACE(trace_buf);
+		return;
+	}
+
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_AP_MODE_ENABLE,
+			   &ap_enable);
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy);
+
+	/* tdma and coex table */
+	if (!wifi_busy) {
+		if (BT_8822B_1ANT_BT_STATUS_ACL_BUSY == coex_dm->bt_status) {
+			halbtc8822b1ant_action_wifi_connected_bt_acl_busy(
+				btcoexist,
+				BT_8822B_1ANT_WIFI_STATUS_CONNECTED_IDLE);
+		} else if ((BT_8822B_1ANT_BT_STATUS_SCO_BUSY ==
+			    coex_dm->bt_status) ||
+			   (BT_8822B_1ANT_BT_STATUS_ACL_SCO_BUSY ==
+			    coex_dm->bt_status)) {
+			halbtc8822b1ant_action_bt_sco_hid_only_busy(btcoexist,
+				BT_8822B_1ANT_WIFI_STATUS_CONNECTED_IDLE);
+		} else {
+
+			halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, false,
+						8);
+
+			halbtc8822b1ant_set_ant_path(btcoexist,
+						     BTC_ANT_PATH_AUTO,
+						     NORMAL_EXEC,
+					     BT_8822B_1ANT_PHASE_2G_RUNTIME);
+
+			if ((coex_sta->high_priority_tx) +
+			    (coex_sta->high_priority_rx) <= 60)
+				/*sy modify case16 -> case17*/
+				halbtc8822b1ant_coex_table_with_type(btcoexist,
+							     NORMAL_EXEC, 1);
+			else
+				halbtc8822b1ant_coex_table_with_type(btcoexist,
+							     NORMAL_EXEC, 1);
+		}
+	} else {
+		if (BT_8822B_1ANT_BT_STATUS_ACL_BUSY == coex_dm->bt_status) {
+			halbtc8822b1ant_action_wifi_connected_bt_acl_busy(
+				btcoexist,
+				BT_8822B_1ANT_WIFI_STATUS_CONNECTED_BUSY);
+		} else if ((BT_8822B_1ANT_BT_STATUS_SCO_BUSY ==
+			    coex_dm->bt_status) ||
+			   (BT_8822B_1ANT_BT_STATUS_ACL_SCO_BUSY ==
+			    coex_dm->bt_status)) {
+			halbtc8822b1ant_action_bt_sco_hid_only_busy(btcoexist,
+				BT_8822B_1ANT_WIFI_STATUS_CONNECTED_BUSY);
+		} else {
+				if (rf4ce_enabled) {
+				btcoexist->btc_write_1byte_bitmask(
+					btcoexist, 0x45e, 0x8, 0x1);
+
+				halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC,
+							true,
+							50);
+
+				halbtc8822b1ant_coex_table_with_type(btcoexist,
+				NORMAL_EXEC, 1);
+		return;
+		}
+
+
+
+			halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, false,
+						8);
+
+			halbtc8822b1ant_set_ant_path(btcoexist,
+						     BTC_ANT_PATH_AUTO,
+						     NORMAL_EXEC,
+					     BT_8822B_1ANT_PHASE_2G_RUNTIME);
+
+			/*
+
+						halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true,
+											32);
+
+						halbtc8822b1ant_set_ant_path(btcoexist,
+						BTC_ANT_PATH_AUTO, NORMAL_EXEC, BT_8822B_1ANT_PHASE_2G_RUNTIME);
+			*/
+
+
+
+			wifi_rssi_state = halbtc8822b1ant_wifi_rssi_state(
+						  btcoexist, 1, 2, 25, 0);
+
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				"[BTCoex], ********** before  **********\n");
+			BTC_TRACE(trace_buf);
+/*
+			if ((BT_8822B_1ANT_BT_STATUS_NON_CONNECTED_IDLE ==
+			     coex_dm->bt_status)  &&
+			    (coex_sta->scan_ap_num <= 3) &&
+			    (wifi_rssi_state == BTC_RSSI_STATE_LOW ||
+			     wifi_rssi_state == BTC_RSSI_STATE_STAY_LOW)) {
+*/
+			if (BT_8822B_1ANT_BT_STATUS_NON_CONNECTED_IDLE ==
+			coex_dm->bt_status) {
+					if (rf4ce_enabled) {
+				btcoexist->btc_write_1byte_bitmask(
+					btcoexist, 0x45e, 0x8, 0x1);
+
+				halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC,
+							true,
+							50);
+
+				halbtc8822b1ant_coex_table_with_type(btcoexist,
+				NORMAL_EXEC, 1);
+		return;
+		}
+
+
+				halbtc8822b1ant_coex_table_with_type(btcoexist,
+							     NORMAL_EXEC, 7);
+			} else
+
+				halbtc8822b1ant_coex_table_with_type(btcoexist,
+							     NORMAL_EXEC, 1);
+
+
+
+			/*
+						else if ((coex_sta->high_priority_tx +
+										 coex_sta->high_priority_rx) <= 60)
+							halbtc8822b1ant_coex_table_with_type(btcoexist,
+										     NORMAL_EXEC, 1);
+						else
+							halbtc8822b1ant_coex_table_with_type(btcoexist,
+										     NORMAL_EXEC, 4);
+			*/
+		}
+	}
+}
+
+void halbtc8822b1ant_run_sw_coexist_mechanism(IN struct btc_coexist *btcoexist)
+{
+
+	u8				algorithm = 0;
+
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+		    "[BTCoex], ********** (runswcoexmech) **********\n");
+	BTC_TRACE(trace_buf);
+	algorithm = halbtc8822b1ant_action_algorithm(btcoexist);
+	coex_dm->cur_algorithm = algorithm;
+
+	if (halbtc8822b1ant_is_common_action(btcoexist)) {
+
+	} else {
+		switch (coex_dm->cur_algorithm) {
+		case BT_8822B_1ANT_COEX_ALGO_SCO:
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				    "[BTCoex], Action algorithm = SCO.\n");
+			BTC_TRACE(trace_buf);
+			/* halbtc8822b1ant_action_sco(btcoexist); */
+			break;
+		case BT_8822B_1ANT_COEX_ALGO_HID:
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				    "[BTCoex], Action algorithm = HID.\n");
+			BTC_TRACE(trace_buf);
+			/* halbtc8822b1ant_action_hid(btcoexist); */
+			break;
+		case BT_8822B_1ANT_COEX_ALGO_A2DP:
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				    "[BTCoex], Action algorithm = A2DP.\n");
+			BTC_TRACE(trace_buf);
+			/* halbtc8822b1ant_action_a2dp(btcoexist); */
+			break;
+		case BT_8822B_1ANT_COEX_ALGO_A2DP_PANHS:
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				"[BTCoex], Action algorithm = A2DP+PAN(HS).\n");
+			BTC_TRACE(trace_buf);
+			/* halbtc8822b1ant_action_a2dp_pan_hs(btcoexist); */
+			break;
+		case BT_8822B_1ANT_COEX_ALGO_PANEDR:
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				    "[BTCoex], Action algorithm = PAN(EDR).\n");
+			BTC_TRACE(trace_buf);
+			/* halbtc8822b1ant_action_pan_edr(btcoexist); */
+			break;
+		case BT_8822B_1ANT_COEX_ALGO_PANHS:
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				    "[BTCoex], Action algorithm = HS mode.\n");
+			BTC_TRACE(trace_buf);
+			/* halbtc8822b1ant_action_pan_hs(btcoexist); */
+			break;
+		case BT_8822B_1ANT_COEX_ALGO_PANEDR_A2DP:
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				    "[BTCoex], Action algorithm = PAN+A2DP.\n");
+			BTC_TRACE(trace_buf);
+			/* halbtc8822b1ant_action_pan_edr_a2dp(btcoexist); */
+			break;
+		case BT_8822B_1ANT_COEX_ALGO_PANEDR_HID:
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				"[BTCoex], Action algorithm = PAN(EDR)+HID.\n");
+			BTC_TRACE(trace_buf);
+			/* halbtc8822b1ant_action_pan_edr_hid(btcoexist); */
+			break;
+		case BT_8822B_1ANT_COEX_ALGO_HID_A2DP_PANEDR:
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				"[BTCoex], Action algorithm = HID+A2DP+PAN.\n");
+			BTC_TRACE(trace_buf);
+			/* halbtc8822b1ant_action_hid_a2dp_pan_edr(btcoexist); */
+			break;
+		case BT_8822B_1ANT_COEX_ALGO_HID_A2DP:
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				    "[BTCoex], Action algorithm = HID+A2DP.\n");
+			BTC_TRACE(trace_buf);
+			/* halbtc8822b1ant_action_hid_a2dp(btcoexist); */
+			break;
+		default:
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				"[BTCoex], Action algorithm = coexist All Off!!\n");
+			BTC_TRACE(trace_buf);
+			/* halbtc8822b1ant_coex_all_off(btcoexist); */
+			break;
+		}
+		coex_dm->pre_algorithm = coex_dm->cur_algorithm;
+	}
+}
+
+void halbtc8822b1ant_run_coexist_mechanism(IN struct btc_coexist *btcoexist)
+{
+
+	struct  btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
+	boolean	wifi_connected = false, bt_hs_on = false;
+	boolean	increase_scan_dev_num = false;
+	boolean	bt_ctrl_agg_buf_size = false;
+	boolean	miracast_plus_bt = false;
+	u8	agg_buf_size = 5;
+	u32	wifi_link_status = 0;
+	u32	num_of_wifi_link = 0, wifi_bw;
+	u8	iot_peer = BTC_IOT_PEER_UNKNOWN;
+	boolean wifi_under_5g = false;
+
+
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+		    "[BTCoex], RunCoexistMechanism()===>\n");
+	BTC_TRACE(trace_buf);
+
+	if (btcoexist->manual_control) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			"[BTCoex], RunCoexistMechanism(), return for Manual CTRL <===\n");
+		BTC_TRACE(trace_buf);
+		return;
+	}
+
+	if (btcoexist->stop_coex_dm) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			"[BTCoex], RunCoexistMechanism(), return for Stop Coex DM <===\n");
+		BTC_TRACE(trace_buf);
+		return;
+	}
+
+
+
+	if (coex_sta->under_ips) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], wifi is under IPS !!!\n");
+		BTC_TRACE(trace_buf);
+		return;
+	}
+
+	if (!coex_sta->run_time_state) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			"[BTCoex], return for run_time_state = false !!!\n");
+		BTC_TRACE(trace_buf);
+		return;
+	}
+
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_5G, &wifi_under_5g);
+	if (wifi_under_5g) {
+		halbtc8822b1ant_action_wifi_under5g(btcoexist);
+
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], WiFi is under 5G!!!\n");
+		BTC_TRACE(trace_buf);
+		return;
+	}
+
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+		    "[BTCoex], WiFi is under 2G!!!\n");
+	BTC_TRACE(trace_buf);
+
+	halbtc8822b1ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO,
+				     NORMAL_EXEC,
+				     BT_8822B_1ANT_PHASE_2G_RUNTIME);
+
+	if (coex_sta->bt_whck_test) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], BT is under WHCK TEST!!!\n");
+		BTC_TRACE(trace_buf);
+		halbtc8822b1ant_action_bt_whck_test(btcoexist);
+		return;
+	}
+
+	if (coex_sta->bt_disabled) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], BT is disabled !!!\n");
+		halbtc8822b1ant_action_wifi_only(btcoexist);
+		return;
+	}
+
+	if ((BT_8822B_1ANT_BT_STATUS_ACL_BUSY == coex_dm->bt_status) ||
+	    (BT_8822B_1ANT_BT_STATUS_SCO_BUSY == coex_dm->bt_status) ||
+	    (BT_8822B_1ANT_BT_STATUS_ACL_SCO_BUSY == coex_dm->bt_status))
+		increase_scan_dev_num = true;
+
+	btcoexist->btc_set(btcoexist, BTC_SET_BL_INC_SCAN_DEV_NUM,
+			   &increase_scan_dev_num);
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED,
+			   &wifi_connected);
+
+	btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_LINK_STATUS,
+			   &wifi_link_status);
+	num_of_wifi_link = wifi_link_status >> 16;
+
+	if ((num_of_wifi_link >= 2) ||
+	    (wifi_link_status & WIFI_P2P_GO_CONNECTED)) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			"############# [BTCoex],  Multi-Port num_of_wifi_link = %d, wifi_link_status = 0x%x\n",
+			    num_of_wifi_link, wifi_link_status);
+		BTC_TRACE(trace_buf);
+
+		if (bt_link_info->bt_link_exist) {
+			halbtc8822b1ant_limited_tx(btcoexist, NORMAL_EXEC, 1, 1,
+						   0, 1);
+			miracast_plus_bt = true;
+		} else {
+			halbtc8822b1ant_limited_tx(btcoexist, NORMAL_EXEC, 0, 0,
+						   0, 0);
+			miracast_plus_bt = false;
+		}
+		btcoexist->btc_set(btcoexist, BTC_SET_BL_MIRACAST_PLUS_BT,
+				   &miracast_plus_bt);
+		halbtc8822b1ant_limited_rx(btcoexist, NORMAL_EXEC, false,
+					   bt_ctrl_agg_buf_size, agg_buf_size);
+
+		if ((bt_link_info->a2dp_exist) &&
+		    (coex_sta->c2h_bt_inquiry_page)) {
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				"############# [BTCoex],  BT Is Inquirying\n");
+			BTC_TRACE(trace_buf);
+			halbtc8822b1ant_action_bt_inquiry(btcoexist);
+		} else
+			halbtc8822b1ant_action_wifi_multi_port(btcoexist);
+
+		return;
+	}
+
+	miracast_plus_bt = false;
+	btcoexist->btc_set(btcoexist, BTC_SET_BL_MIRACAST_PLUS_BT,
+			   &miracast_plus_bt);
+
+	btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw);
+
+	if ((bt_link_info->bt_link_exist) && (wifi_connected)) {
+		halbtc8822b1ant_limited_tx(btcoexist, NORMAL_EXEC, 1, 1, 0, 1);
+
+		btcoexist->btc_get(btcoexist, BTC_GET_U1_IOT_PEER, &iot_peer);
+
+		if (BTC_IOT_PEER_CISCO != iot_peer) {
+			if (bt_link_info->sco_exist) /* if (bt_link_info->bt_hi_pri_link_exist) */
+				halbtc8822b1ant_limited_rx(btcoexist,
+					   NORMAL_EXEC, true, false, 0x5);
+			else
+				halbtc8822b1ant_limited_rx(btcoexist,
+					   NORMAL_EXEC, false, false, 0x5);
+		} else {
+			if (bt_link_info->sco_exist)
+				halbtc8822b1ant_limited_rx(btcoexist,
+					   NORMAL_EXEC, true, false, 0x5);
+			else {
+				if (BTC_WIFI_BW_HT40 == wifi_bw)
+					halbtc8822b1ant_limited_rx(btcoexist,
+						NORMAL_EXEC, false, true, 0x10);
+				else
+					halbtc8822b1ant_limited_rx(btcoexist,
+						NORMAL_EXEC, false, true, 0x8);
+			}
+		}
+
+		halbtc8822b1ant_sw_mechanism(btcoexist, true);
+		halbtc8822b1ant_run_sw_coexist_mechanism(
+			btcoexist);  /* just print debug message */
+	} else {
+		halbtc8822b1ant_limited_tx(btcoexist, NORMAL_EXEC, 0, 0, 0, 0);
+
+		halbtc8822b1ant_limited_rx(btcoexist, NORMAL_EXEC, false, false,
+					   0x5);
+
+		halbtc8822b1ant_sw_mechanism(btcoexist, false);
+		halbtc8822b1ant_run_sw_coexist_mechanism(
+			btcoexist); /* just print debug message */
+	}
+
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on);
+	if (coex_sta->c2h_bt_inquiry_page) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "############# [BTCoex],  BT Is Inquirying\n");
+		BTC_TRACE(trace_buf);
+		halbtc8822b1ant_action_bt_inquiry(btcoexist);
+		return;
+	} else if (bt_hs_on) {
+		halbtc8822b1ant_action_hs(btcoexist);
+		return;
+	}
+
+
+	if (!wifi_connected) {
+		boolean	scan = false, link = false, roam = false;
+
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], wifi is non connected-idle !!!\n");
+		BTC_TRACE(trace_buf);
+
+		btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_SCAN, &scan);
+		btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_LINK, &link);
+		btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_ROAM, &roam);
+
+		if (scan || link || roam) {
+			if (scan)
+				halbtc8822b1ant_action_wifi_not_connected_scan(
+					btcoexist);
+			else
+				halbtc8822b1ant_action_wifi_not_connected_asso_auth(
+					btcoexist);
+		} else
+			halbtc8822b1ant_action_wifi_not_connected(btcoexist);
+	} else	/* wifi LPS/Busy */
+		halbtc8822b1ant_action_wifi_connected(btcoexist);
+}
+
+u32 halbtc8822b1ant_psd_log2base(IN struct btc_coexist *btcoexist, IN u32 val)
+{
+	u8	j;
+	u32	tmp, tmp2, val_integerd_b = 0, tindex, shiftcount = 0;
+	u32	result, val_fractiond_b = 0, table_fraction[21] = {0, 432, 332, 274, 232, 200,
+				   174, 151, 132, 115, 100, 86, 74, 62, 51, 42,
+							   32, 23, 15, 7, 0
+							      };
+
+	if (val == 0)
+		return 0;
+
+	tmp = val;
+
+	while (1) {
+		if (tmp == 1)
+			break;
+
+		tmp = (tmp >> 1);
+		shiftcount++;
+	}
+
+
+	val_integerd_b = shiftcount + 1;
+
+	tmp2 = 1;
+	for (j = 1; j <= val_integerd_b; j++)
+		tmp2 = tmp2 * 2;
+
+	tmp = (val * 100) / tmp2;
+	tindex = tmp / 5;
+
+	if (tindex > 20)
+		tindex = 20;
+
+	val_fractiond_b = table_fraction[tindex];
+
+	result = val_integerd_b * 100 - val_fractiond_b;
+
+	return result;
+
+
+}
+
+void halbtc8822b1ant_init_coex_dm(IN struct btc_coexist *btcoexist)
+{
+	/* force to reset coex mechanism */
+
+	halbtc8822b1ant_low_penalty_ra(btcoexist, NORMAL_EXEC, false);
+
+	/* sw all off */
+	halbtc8822b1ant_sw_mechanism(btcoexist, false);
+
+	/* halbtc8822b1ant_ps_tdma(btcoexist, FORCE_EXEC, false, 8); */
+	/* halbtc8822b1ant_coex_table_with_type(btcoexist, FORCE_EXEC, 0); */
+
+	coex_sta->pop_event_cnt = 0;
+}
+
+void halbtc8822b1ant_init_hw_config(IN struct btc_coexist *btcoexist,
+				    IN boolean back_up, IN boolean wifi_only)
+{
+
+	u8	u8tmp = 0;
+	boolean			wifi_under_5g = false;
+	u32				u32tmp1 = 0, u32tmp2 = 0, u32tmp3 = 0;
+
+
+	u32tmp3 = btcoexist->btc_read_4byte(btcoexist, 0xcb4);
+	u32tmp1 = halbtc8822b1ant_ltecoex_indirect_read_reg(btcoexist, 0x38);
+	u32tmp2 = halbtc8822b1ant_ltecoex_indirect_read_reg(btcoexist, 0x54);
+
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+		"[BTCoex], ********** (Before Init HW config) 0xcb4 = 0x%x, 0x38= 0x%x, 0x54= 0x%x**********\n",
+		    u32tmp3, u32tmp1, u32tmp2);
+	BTC_TRACE(trace_buf);
+
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+		    "[BTCoex], 1Ant Init HW Config!!\n");
+	BTC_TRACE(trace_buf);
+
+	coex_sta->bt_coex_supported_feature = 0;
+	coex_sta->bt_coex_supported_version = 0;
+
+	/* Setup RF front end type */
+	halbtc8822b1ant_set_rfe_type(btcoexist);
+
+	/* 0xf0[15:12] --> Chip Cut information */
+	coex_sta->cut_version = (btcoexist->btc_read_1byte(btcoexist,
+				 0xf1) & 0xf0) >> 4;
+
+	btcoexist->btc_write_1byte_bitmask(btcoexist, 0x550, 0x8,
+					   0x1);  /* enable TBTT nterrupt */
+
+	/* BT report packet sample rate	 */
+	/* 0x790[5:0]=0x5 */
+	u8tmp = btcoexist->btc_read_1byte(btcoexist, 0x790);
+	u8tmp &= 0xc0;
+	u8tmp |= 0x5;
+	btcoexist->btc_write_1byte(btcoexist, 0x790, u8tmp);
+
+	/* Enable BT counter statistics */
+	btcoexist->btc_write_1byte(btcoexist, 0x778, 0x1);
+
+	/* Enable PTA (3-wire function form BT side) */
+	btcoexist->btc_write_1byte_bitmask(btcoexist, 0x40, 0x20, 0x1);
+	btcoexist->btc_write_1byte_bitmask(btcoexist, 0x41, 0x02, 0x1);
+
+	/* Enable PTA (tx/rx signal form WiFi side) */
+	btcoexist->btc_write_1byte_bitmask(btcoexist, 0x4c6, 0x10, 0x1);
+	/*GNT_BT=1 while select both */
+	btcoexist->btc_write_1byte_bitmask(btcoexist, 0x763, 0x10, 0x1);
+
+	/* enable GNT_WL/GNT_BT debug signal to GPIO14/15 */
+	/*btcoexist->btc_write_1byte_bitmask(btcoexist, 0x73, 0x8, 0x1);*/
+
+	/* enable GNT_WL */
+	btcoexist->btc_write_1byte_bitmask(btcoexist, 0x4e, 0x40, 0x0);
+	btcoexist->btc_write_1byte_bitmask(btcoexist, 0x67, 0x1, 0x0);
+
+	if (btcoexist->btc_read_1byte(btcoexist, 0x80) == 0xc6)
+		halbtc8822b1ant_post_state_to_bt(btcoexist,
+					 BT_8822B_1ANT_SCOREBOARD_ONOFF, true);
+
+	/* Antenna config */
+	if (wifi_only) {
+
+		coex_sta->concurrent_rx_mode_on = false;
+		halbtc8822b1ant_set_ant_path(btcoexist,
+					     BTC_ANT_PATH_WIFI,
+					     FORCE_EXEC,
+					     BT_8822B_1ANT_PHASE_WLANONLY_INIT);
+	} else {
+
+		coex_sta->concurrent_rx_mode_on = true;
+
+		halbtc8822b1ant_set_ant_path(btcoexist,
+					     BTC_ANT_PATH_AUTO,
+					     FORCE_EXEC,
+					     BT_8822B_1ANT_PHASE_COEX_INIT);
+	}
+
+
+	/* PTA parameter */
+	halbtc8822b1ant_coex_table_with_type(btcoexist, FORCE_EXEC, 0);
+
+	halbtc8822b1ant_enable_gnt_to_gpio(btcoexist, true);
+
+}
+
+
+void halbtc8822b1ant_init_hw_config_without_bt(IN struct btc_coexist *btcoexist,
+		IN boolean back_up, IN boolean wifi_only)
+{
+
+	u8	u8tmp = 0;
+	boolean		wifi_under_5g = false;
+	u32			u32tmp1 = 0, u32tmp2 = 0, u32tmp3 = 0;
+
+
+	/* 0xf0[15:12] --> Chip Cut information */
+	coex_sta->cut_version = (btcoexist->btc_read_1byte(btcoexist,
+				 0xf1) & 0xf0) >> 4;
+
+	/* enable TBTT interrupt */
+	btcoexist->btc_write_1byte_bitmask(btcoexist, 0x550, 0x8,
+					   0x1);
+
+	/* enable GNT_WL */
+	btcoexist->btc_write_1byte_bitmask(btcoexist, 0x4e, 0x40, 0x0);
+	btcoexist->btc_write_1byte_bitmask(btcoexist, 0x67, 0x1, 0x0);
+
+	/* Antenna config */
+	btcoexist->btc_write_1byte_bitmask(btcoexist, 0x4e, 0x80,
+					   0x0);  /*  0x4c[23] = 0 */
+	btcoexist->btc_write_1byte_bitmask(btcoexist, 0x4f, 0x01,
+					   0x1);  /* 0x4c[24] = 1 */
+	btcoexist->btc_write_1byte_bitmask(btcoexist, 0xcb4, 0xff,
+		0x77);	/* BB SW, DPDT use RFE_ctrl8 and RFE_ctrl9 as conctrol pin */
+
+
+	/* Ext switch buffer mux */
+	btcoexist->btc_write_1byte(btcoexist, 0x974, 0xff);
+	btcoexist->btc_write_1byte_bitmask(btcoexist, 0x1991, 0x3, 0x0);
+	btcoexist->btc_write_1byte_bitmask(btcoexist, 0xcbe, 0x8, 0x0);
+
+	/*enable sw control gnt_wl=1 / gnt_bt=1 */
+	btcoexist->btc_write_1byte(btcoexist, 0x73, 0x0e);
+
+	btcoexist->btc_write_4byte(btcoexist, 0x1704, 0x0000ff00);
+
+	btcoexist->btc_write_4byte(btcoexist, 0x1700, 0xc00f0038);
+
+
+	/* ant switch WL2G or WL5G*/
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_5G,
+			   &wifi_under_5g);
+	if (wifi_under_5g)
+
+		btcoexist->btc_write_1byte_bitmask(btcoexist, 0xcbd,
+						   0x3, 1);
+
+	else
+
+		btcoexist->btc_write_1byte_bitmask(btcoexist, 0xcbd,
+						   0x3, 2);
+
+}
+
+void halbtc8822b1ant_psd_showdata(IN struct btc_coexist *btcoexist)
+{
+	u8		*cli_buf = btcoexist->cli_buf;
+	u32		delta_freq_per_point;
+	u32		freq, freq1, freq2, n = 0, i = 0, j = 0, m = 0, psd_rep1, psd_rep2;
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+		   "\r\n\n============[PSD info]  (%d)============\n",
+		   psd_scan->psd_gen_count);
+	CL_PRINTF(cli_buf);
+
+	if (psd_scan->psd_gen_count == 0) {
+		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n No data !!\n");
+		CL_PRINTF(cli_buf);
+		return;
+	}
+
+	if (psd_scan->psd_point == 0)
+		delta_freq_per_point = 0;
+	else
+		delta_freq_per_point = psd_scan->psd_band_width /
+				       psd_scan->psd_point;
+
+	/* if (psd_scan->is_psd_show_max_only) */
+	if (0) {
+		psd_rep1 = psd_scan->psd_max_value / 100;
+		psd_rep2 = psd_scan->psd_max_value - psd_rep1 * 100;
+
+		freq = ((psd_scan->real_cent_freq - 20) * 1000000 +
+			psd_scan->psd_max_value_point * delta_freq_per_point);
+		freq1 = freq / 1000000;
+		freq2 = freq / 1000 - freq1 * 1000;
+
+		if (freq2 < 100)
+			CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+				   "\r\n Freq = %d.0%d MHz",
+				   freq1, freq2);
+		else
+			CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+				   "\r\n Freq = %d.%d MHz",
+				   freq1, freq2);
+
+		if (psd_rep2 < 10)
+			CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+				   ", Value = %d.0%d dB, (%d)\n",
+				   psd_rep1, psd_rep2, psd_scan->psd_max_value);
+		else
+			CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+				   ", Value = %d.%d dB, (%d)\n",
+				   psd_rep1, psd_rep2, psd_scan->psd_max_value);
+
+		CL_PRINTF(cli_buf);
+	} else {
+		m = psd_scan->psd_start_point;
+		n = psd_scan->psd_start_point;
+		i = 1;
+		j = 1;
+
+		while (1) {
+			do {
+				freq = ((psd_scan->real_cent_freq - 20) *
+					1000000 + m *
+					delta_freq_per_point);
+				freq1 = freq / 1000000;
+				freq2 = freq / 1000 - freq1 * 1000;
+
+				if (i == 1) {
+					if (freq2 == 0)
+						CL_SPRINTF(cli_buf,
+							   BT_TMP_BUF_SIZE,
+							   "\r\n Freq%6d.000",
+							   freq1);
+					else if (freq2 < 100)
+						CL_SPRINTF(cli_buf,
+							   BT_TMP_BUF_SIZE,
+							   "\r\n Freq%6d.0%2d",
+							   freq1,
+							   freq2);
+					else
+						CL_SPRINTF(cli_buf,
+							   BT_TMP_BUF_SIZE,
+							   "\r\n Freq%6d.%3d",
+							   freq1,
+							   freq2);
+				} else if ((i % 8 == 0) ||
+					   (m == psd_scan->psd_stop_point)) {
+					if (freq2 == 0)
+						CL_SPRINTF(cli_buf,
+							   BT_TMP_BUF_SIZE,
+							   "%6d.000\n", freq1);
+					else if (freq2 < 100)
+						CL_SPRINTF(cli_buf,
+							   BT_TMP_BUF_SIZE,
+							   "%6d.0%2d\n", freq1,
+							   freq2);
+					else
+						CL_SPRINTF(cli_buf,
+							   BT_TMP_BUF_SIZE,
+							   "%6d.%3d\n", freq1,
+							   freq2);
+				} else {
+					if (freq2 == 0)
+						CL_SPRINTF(cli_buf,
+							   BT_TMP_BUF_SIZE,
+							   "%6d.000", freq1);
+					else if (freq2 < 100)
+						CL_SPRINTF(cli_buf,
+							   BT_TMP_BUF_SIZE,
+							   "%6d.0%2d", freq1,
+							   freq2);
+					else
+						CL_SPRINTF(cli_buf,
+							   BT_TMP_BUF_SIZE,
+							   "%6d.%3d", freq1,
+							   freq2);
+				}
+
+				i++;
+				m++;
+				CL_PRINTF(cli_buf);
+
+			} while ((i <= 8) && (m <= psd_scan->psd_stop_point));
+
+
+			do {
+				psd_rep1 = psd_scan->psd_report_max_hold[n] /
+					   100;
+				psd_rep2 = psd_scan->psd_report_max_hold[n] -
+					   psd_rep1 *
+					   100;
+
+				if (j == 1) {
+					if (psd_rep2 < 10)
+						CL_SPRINTF(cli_buf,
+							   BT_TMP_BUF_SIZE,
+							   "\r\n Val %7d.0%d",
+							   psd_rep1,
+							   psd_rep2);
+					else
+						CL_SPRINTF(cli_buf,
+							   BT_TMP_BUF_SIZE,
+							   "\r\n Val %7d.%d",
+							   psd_rep1,
+							   psd_rep2);
+				} else if ((j % 8 == 0)  ||
+					   (n == psd_scan->psd_stop_point)) {
+					if (psd_rep2 < 10)
+						CL_SPRINTF(cli_buf,
+							   BT_TMP_BUF_SIZE,
+							"%7d.0%d\n", psd_rep1,
+							   psd_rep2);
+					else
+						CL_SPRINTF(cli_buf,
+							   BT_TMP_BUF_SIZE,
+							   "%7d.%d\n", psd_rep1,
+							   psd_rep2);
+				} else {
+					if (psd_rep2 < 10)
+						CL_SPRINTF(cli_buf,
+							   BT_TMP_BUF_SIZE,
+							   "%7d.0%d", psd_rep1,
+							   psd_rep2);
+					else
+						CL_SPRINTF(cli_buf,
+							   BT_TMP_BUF_SIZE,
+							   "%7d.%d", psd_rep1,
+							   psd_rep2);
+				}
+
+				j++;
+				n++;
+				CL_PRINTF(cli_buf);
+
+			} while ((j <= 8) && (n <= psd_scan->psd_stop_point));
+
+			if ((m > psd_scan->psd_stop_point) ||
+			    (n > psd_scan->psd_stop_point))
+				break;
+
+			i = 1;
+			j = 1;
+
+		}
+	}
+
+
+}
+
+void halbtc8822b1ant_psd_max_holddata(IN struct btc_coexist *btcoexist,
+				      IN u32 gen_count)
+{
+	u32	i = 0, i_max = 0, val_max = 0;
+
+	if (gen_count == 1) {
+		memcpy(psd_scan->psd_report_max_hold,
+		       psd_scan->psd_report,
+		       BT_8822B_1ANT_ANTDET_PSD_POINTS * sizeof(u32));
+
+		for (i = psd_scan->psd_start_point;
+		     i <= psd_scan->psd_stop_point; i++) {
+
+		}
+
+		psd_scan->psd_max_value_point = 0;
+		psd_scan->psd_max_value = 0;
+
+	} else {
+		for (i = psd_scan->psd_start_point;
+		     i <= psd_scan->psd_stop_point; i++) {
+			if (psd_scan->psd_report[i] >
+			    psd_scan->psd_report_max_hold[i])
+				psd_scan->psd_report_max_hold[i] =
+					psd_scan->psd_report[i];
+
+			/* search Max Value */
+			if (i == psd_scan->psd_start_point) {
+				i_max = i;
+				val_max = psd_scan->psd_report_max_hold[i];
+			} else {
+				if (psd_scan->psd_report_max_hold[i] >
+				    val_max) {
+					i_max = i;
+					val_max = psd_scan->psd_report_max_hold[i];
+				}
+			}
+
+
+
+		}
+
+		psd_scan->psd_max_value_point = i_max;
+		psd_scan->psd_max_value = val_max;
+
+	}
+
+
+}
+
+u32 halbtc8822b1ant_psd_getdata(IN struct btc_coexist *btcoexist, IN u32 point)
+{
+	/* reg 0x808[9:0]: FFT data x */
+	/* reg 0x808[22]: 0-->1 to get 1 FFT data y */
+	/* reg 0x8b4[15:0]: FFT data y report */
+
+	u32 val = 0, psd_report = 0;
+
+	val = btcoexist->btc_read_4byte(btcoexist, 0x808);
+
+	val &= 0xffbffc00;
+	val |= point;
+
+	btcoexist->btc_write_4byte(btcoexist, 0x808, val);
+
+	val |= 0x00400000;
+	btcoexist->btc_write_4byte(btcoexist, 0x808, val);
+
+
+	val = btcoexist->btc_read_4byte(btcoexist, 0x8b4);
+
+	psd_report = val & 0x0000ffff;
+
+	return psd_report;
+}
+
+
+void halbtc8822b1ant_psd_sweep_point(IN struct btc_coexist *btcoexist,
+	     IN u32 cent_freq, IN s32 offset, IN u32 span, IN u32 points,
+				     IN u32 avgnum)
+{
+	u32	 i, val, n, k = 0;
+	u32	points1 = 0, psd_report = 0;
+	u32	start_p = 0, stop_p = 0, delta_freq_per_point = 156250;
+	u32    psd_center_freq = 20 * 10 ^ 6, freq, freq1, freq2;
+	boolean outloop = false;
+	u8	 flag = 0;
+	u32	tmp, psd_rep1, psd_rep2;
+	u32	wifi_original_channel = 1;
+
+	psd_scan->is_psd_running = true;
+
+	do {
+		switch (flag) {
+		case 0:  /* Get PSD parameters */
+		default:
+
+			psd_scan->psd_band_width = 40 * 1000000;
+			psd_scan->psd_point = points;
+			psd_scan->psd_start_base = points / 2;
+			psd_scan->psd_avg_num = avgnum;
+			psd_scan->real_cent_freq = cent_freq;
+			psd_scan->real_offset = offset;
+			psd_scan->real_span = span;
+
+
+			points1 = psd_scan->psd_point;
+			delta_freq_per_point = psd_scan->psd_band_width /
+					       psd_scan->psd_point;
+
+			/* PSD point setup */
+			val = btcoexist->btc_read_4byte(btcoexist, 0x808);
+			val &= 0xffff0fff;
+
+			switch (psd_scan->psd_point) {
+			case 128:
+				val |= 0x0;
+				break;
+			case 256:
+			default:
+				val |= 0x00004000;
+				break;
+			case 512:
+				val |= 0x00008000;
+				break;
+			case 1024:
+				val |= 0x0000c000;
+				break;
+			}
+
+			switch (psd_scan->psd_avg_num) {
+			case 1:
+				val |= 0x0;
+				break;
+			case 8:
+				val |= 0x00001000;
+				break;
+			case 16:
+				val |= 0x00002000;
+				break;
+			case 32:
+			default:
+				val |= 0x00003000;
+				break;
+			}
+			btcoexist->btc_write_4byte(btcoexist, 0x808, val);
+
+			flag = 1;
+			break;
+		case 1:	  /* calculate the PSD point index from freq/offset/span */
+			psd_center_freq = psd_scan->psd_band_width / 2 +
+					  offset * (1000000);
+
+			start_p = psd_scan->psd_start_base + (psd_center_freq -
+				span * (1000000) / 2) / delta_freq_per_point;
+			psd_scan->psd_start_point = start_p -
+						    psd_scan->psd_start_base;
+
+			stop_p = psd_scan->psd_start_base + (psd_center_freq +
+				span * (1000000) / 2) / delta_freq_per_point;
+			psd_scan->psd_stop_point = stop_p -
+						   psd_scan->psd_start_base - 1;
+
+			flag = 2;
+			break;
+		case 2:  /* set RF channel/BW/Mode */
+
+			/* set 3-wire off */
+			val = btcoexist->btc_read_4byte(btcoexist, 0x88c);
+			val |= 0x00300000;
+			btcoexist->btc_write_4byte(btcoexist, 0x88c, val);
+
+			/* CCK off */
+			val = btcoexist->btc_read_4byte(btcoexist, 0x800);
+			val &= 0xfeffffff;
+			btcoexist->btc_write_4byte(btcoexist, 0x800, val);
+
+			/* store WiFi original channel */
+			wifi_original_channel = btcoexist->btc_get_rf_reg(
+					btcoexist, BTC_RF_A, 0x18, 0x3ff);
+
+			/* Set RF channel */
+			if (cent_freq == 2484)
+				btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A,
+							  0x18, 0x3ff, 0xe);
+			else
+				btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A,
+					  0x18, 0x3ff, (cent_freq - 2412) / 5 +
+						  1); /* WiFi TRx Mask on */
+
+			/* Set  RF mode = Rx, RF Gain = 0x8a0 */
+			btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x0,
+						  0xfffff, 0x308a0);
+
+			/* Set RF Rx filter corner */
+			btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1e,
+						  0xfffff, 0x3e4);
+
+			/* Set TRx mask off */
+			/* un-lock TRx Mask setup */
+			btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0xdd,
+						  0x80, 0x1);
+			btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0xdf,
+						  0x1, 0x1);
+
+			btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1,
+						  0xfffff, 0x0);
+
+			flag = 3;
+			break;
+		case 3:
+			memset(psd_scan->psd_report, 0,
+			       psd_scan->psd_point * sizeof(u32));
+			start_p = psd_scan->psd_start_point +
+				  psd_scan->psd_start_base;
+			stop_p = psd_scan->psd_stop_point +
+				 psd_scan->psd_start_base + 1;
+
+			i = start_p;
+
+			while (i < stop_p) {
+				if (i >= points1)
+					psd_report =
+						halbtc8822b1ant_psd_getdata(
+							btcoexist, i - points1);
+				else
+					psd_report =
+						halbtc8822b1ant_psd_getdata(
+							btcoexist, i);
+
+				if (psd_report == 0)
+					tmp = 0;
+				else
+					/* tmp =  20*log10((double)psd_report); */
+					/* 20*log2(x)/log2(10), log2Base return theresult of the psd_report*100 */
+					tmp = 6 * halbtc8822b1ant_psd_log2base(
+						      btcoexist, psd_report);
+
+				n = i - psd_scan->psd_start_base;
+				psd_scan->psd_report[n] =  tmp;
+				psd_rep1 = psd_scan->psd_report[n] / 100;
+				psd_rep2 = psd_scan->psd_report[n] - psd_rep1 *
+					   100;
+
+				freq = ((cent_freq - 20) * 1000000 + n *
+					delta_freq_per_point);
+				freq1 = freq / 1000000;
+				freq2 = freq / 1000 - freq1 * 1000;
+
+				i++;
+
+				k = 0;
+
+				/* Add Delay between PSD point */
+				while (1) {
+					if (k++ > 20000)
+						break;
+				}
+
+			}
+
+			flag = 100;
+			break;
+		case 99:	/* error */
+
+			outloop = true;
+			break;
+		case 100: /* recovery */
+
+			/* set 3-wire on */
+			val = btcoexist->btc_read_4byte(btcoexist, 0x88c);
+			val &= 0xffcfffff;
+			btcoexist->btc_write_4byte(btcoexist, 0x88c, val);
+
+			/* CCK on */
+			val = btcoexist->btc_read_4byte(btcoexist, 0x800);
+			val |= 0x01000000;
+			btcoexist->btc_write_4byte(btcoexist, 0x800, val);
+
+			/* PSD off */
+			val = btcoexist->btc_read_4byte(btcoexist, 0x808);
+			val &= 0xffbfffff;
+			btcoexist->btc_write_4byte(btcoexist, 0x808, val);
+
+			/* TRx Mask on */
+			btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1,
+						  0xfffff, 0x780);
+
+			/* lock TRx Mask setup */
+			btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0xdd,
+						  0x80, 0x0);
+			btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0xdf,
+						  0x1, 0x0);
+
+			/* Set RF Rx filter corner */
+			btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1e,
+						  0xfffff, 0x0);
+
+			/* restore WiFi original channel */
+			btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x18,
+						  0x3ff, wifi_original_channel);
+
+			outloop = true;
+			break;
+
+		}
+
+	} while (!outloop);
+
+
+
+	psd_scan->is_psd_running = false;
+
+
+}
+
+#if (BTC_COEX_OFFLOAD == 1)
+void halbtc8822b1ant_wifi_info_notify(IN struct btc_coexist *btcoexist)
+{
+	u8			h2c_para[4] = {0};
+	u8			opcode_ver = 0;
+	u8			ap_num = 0;
+	s32			wifi_rssi = 0;
+	boolean			wifi_busy = false;
+
+	btcoexist->btc_get(btcoexist, BTC_GET_S4_WIFI_RSSI, &wifi_rssi);
+	btcoexist->btc_get(btcoexist, BTC_GET_U1_AP_NUM, &ap_num);
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy);
+
+	h2c_para[0] = ap_num;					/* AP number */
+	h2c_para[1] = (u8)wifi_busy;		/* Busy */
+	h2c_para[2] = (u8)wifi_rssi;			/* RSSI */
+
+	btcoexist->btc_coex_h2c_process(btcoexist, COL_OP_WIFI_INFO_NOTIFY,
+					opcode_ver, &h2c_para[0], 3);
+}
+
+void halbtc8822b1ant_setManual(IN struct btc_coexist *btcoexist,
+			       IN boolean manual)
+{
+	u8			h2c_para[4] = {0};
+	u8			opcode_ver = 0;
+	u8			set_type = 0;
+
+	if (manual)
+		set_type = 1;
+	else
+		set_type = 0;
+
+	h2c_para[0] = set_type;				/* set_type */
+
+	btcoexist->btc_coex_h2c_process(btcoexist, COL_OP_SET_CONTROL,
+					opcode_ver,
+					&h2c_para[0], 1);
+}
+
+/* ************************************************************
+ * work around function start with wa_halbtc8822b1ant_
+ * ************************************************************
+ * ************************************************************
+ * extern function start with ex_halbtc8822b1ant_
+ * ************************************************************ */
+
+void ex_halbtc8822b1ant_power_on_setting(IN struct btc_coexist *btcoexist)
+{}
+void ex_halbtc8822b1ant_pre_load_firmware(IN struct btc_coexist *btcoexist)
+{}
+void ex_halbtc8822b1ant_init_hw_config(IN struct btc_coexist *btcoexist,
+				       IN boolean wifi_only)
+{}
+void ex_halbtc8822b1ant_init_coex_dm(IN struct btc_coexist *btcoexist)
+{}
+void ex_halbtc8822b1ant_ips_notify(IN struct btc_coexist *btcoexist, IN u8 type)
+{
+	u8			h2c_para[4] = {0};
+	u8			opcode_ver = 0;
+	u8			ips_notify = 0;
+
+	if (BTC_IPS_ENTER == type) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], IPS ENTER notify\n");
+		BTC_TRACE(trace_buf);
+		ips_notify = 1;
+	} else if (BTC_IPS_LEAVE == type) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], IPS LEAVE notify\n");
+		BTC_TRACE(trace_buf);
+	}
+
+	h2c_para[0] = ips_notify;		/* IPS notify */
+	h2c_para[1] = 0xff;			/* LPS notify */
+	h2c_para[2] = 0xff;			/* RF state notify */
+	h2c_para[3] = 0xff;			/* pnp notify */
+
+	btcoexist->btc_coex_h2c_process(btcoexist,
+					COL_OP_WIFI_POWER_STATE_NOTIFY,
+					opcode_ver, &h2c_para[0], 4);
+}
+void ex_halbtc8822b1ant_lps_notify(IN struct btc_coexist *btcoexist, IN u8 type)
+{
+	u8			h2c_para[4] = {0};
+	u8			opcode_ver = 0;
+	u8			lps_notify = 0;
+
+	if (BTC_LPS_ENABLE == type) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], LPS ENABLE notify\n");
+		BTC_TRACE(trace_buf);
+		lps_notify = 1;
+	} else if (BTC_LPS_DISABLE == type) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], LPS DISABLE notify\n");
+		BTC_TRACE(trace_buf);
+	}
+
+	h2c_para[0] = 0xff;			/* IPS notify */
+	h2c_para[1] = lps_notify;		/* LPS notify */
+	h2c_para[2] = 0xff;			/* RF state notify */
+	h2c_para[3] = 0xff;			/* pnp notify */
+
+	btcoexist->btc_coex_h2c_process(btcoexist,
+					COL_OP_WIFI_POWER_STATE_NOTIFY,
+					opcode_ver, &h2c_para[0], 4);
+}
+
+void ex_halbtc8822b1ant_scan_notify(IN struct btc_coexist *btcoexist,
+				    IN u8 type)
+{
+	u8			h2c_para[4] = {0};
+	u8			opcode_ver = 0;
+	u8			scan_start = 0;
+	boolean			under_4way = false;
+
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_4_WAY_PROGRESS,
+			   &under_4way);
+	if (BTC_SCAN_START == type) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], SCAN START notify\n");
+		BTC_TRACE(trace_buf);
+		scan_start = 1;
+	} else {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], SCAN FINISH notify\n");
+		BTC_TRACE(trace_buf);
+	}
+
+	h2c_para[0] = scan_start;		/* scan notify */
+	h2c_para[1] = 0xff;			/* connect notify */
+	h2c_para[2] = 0xff;			/* specific packet notify */
+	if (under_4way)
+		h2c_para[3] = 1;			/* under 4way progress */
+	else
+		h2c_para[3] = 0;
+
+	btcoexist->btc_coex_h2c_process(btcoexist, COL_OP_WIFI_PROGRESS_NOTIFY,
+					opcode_ver, &h2c_para[0], 4);
+}
+
+void ex_halbtc8822b1ant_connect_notify(IN struct btc_coexist *btcoexist,
+				       IN u8 type)
+{
+	u8			h2c_para[4] = {0};
+	u8			opcode_ver = 0;
+	u8			connect_start = 0;
+	boolean			under_4way = false;
+
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_4_WAY_PROGRESS,
+			   &under_4way);
+	if (BTC_ASSOCIATE_START == type) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], CONNECT START notify\n");
+		BTC_TRACE(trace_buf);
+		connect_start = 1;
+	} else {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], CONNECT FINISH notify\n");
+		BTC_TRACE(trace_buf);
+	}
+
+	h2c_para[0] = 0xff;			/* scan notify */
+	h2c_para[1] = connect_start;	/* connect notify */
+	h2c_para[2] = 0xff;			/* specific packet notify */
+	if (under_4way)
+		h2c_para[3] = 1;			/* under 4way progress */
+	else
+		h2c_para[3] = 0;
+
+	btcoexist->btc_coex_h2c_process(btcoexist, COL_OP_WIFI_PROGRESS_NOTIFY,
+					opcode_ver, &h2c_para[0], 4);
+}
+
+void ex_halbtc8822b1ant_media_status_notify(IN struct btc_coexist *btcoexist,
+		IN u8 type)
+{
+	u32			wifi_bw;
+	u8			wifi_central_chnl;
+	u8			h2c_para[5] = {0};
+	u8			opcode_ver = 0;
+	u8			port = 0, connected = 0, freq = 0, bandwidth = 0, iot_peer = 0;
+	boolean			wifi_under_5g = false;
+
+	if (BTC_MEDIA_CONNECT == type)
+		connected = 1;
+
+	btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw);
+	bandwidth = (u8)wifi_bw;
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_5G, &wifi_under_5g);
+	if (wifi_under_5g)
+		freq = 1;
+	else
+		freq = 0;
+	btcoexist->btc_get(btcoexist, BTC_GET_U1_WIFI_CENTRAL_CHNL,
+			   &wifi_central_chnl);
+	btcoexist->btc_get(btcoexist, BTC_GET_U1_IOT_PEER, &iot_peer);
+
+	h2c_para[0] = (connected << 4) |
+		port;	/* port need to be implemented in the future (p2p port, ...) */
+	h2c_para[1] = (freq << 4) | bandwidth;
+	h2c_para[2] = wifi_central_chnl;
+	h2c_para[3] = iot_peer;
+	btcoexist->btc_coex_h2c_process(btcoexist, COL_OP_WIFI_STATUS_NOTIFY,
+					opcode_ver, &h2c_para[0], 4);
+}
+
+void ex_halbtc8822b1ant_specific_packet_notify(IN struct btc_coexist *btcoexist,
+		IN u8 type)
+{
+	u8			h2c_para[4] = {0};
+	u8			opcode_ver = 0;
+	u8			connect_start = 0;
+	boolean			under_4way = false;
+
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_4_WAY_PROGRESS,
+			   &under_4way);
+
+	h2c_para[0] = 0xff;			/* scan notify */
+	h2c_para[1] = 0xff;			/* connect notify */
+	h2c_para[2] = type;			/* specific packet notify */
+	if (under_4way)
+		h2c_para[3] = 1;			/* under 4way progress */
+	else
+		h2c_para[3] = 0;
+
+	btcoexist->btc_coex_h2c_process(btcoexist, COL_OP_WIFI_PROGRESS_NOTIFY,
+					opcode_ver, &h2c_para[0], 4);
+}
+
+void ex_halbtc8822b1ant_bt_info_notify(IN struct btc_coexist *btcoexist,
+				       IN u8 *tmp_buf, IN u8 length)
+{}
+void ex_halbtc8822b1ant_rf_status_notify(IN struct btc_coexist *btcoexist,
+		IN u8 type)
+{
+	u8			h2c_para[4] = {0};
+	u8			opcode_ver = 0;
+	u8			rfstate_notify = 0;
+
+	if (BTC_RF_ON == type) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], RF is turned ON!!\n");
+		BTC_TRACE(trace_buf);
+		rfstate_notify = 1;
+	} else if (BTC_RF_OFF == type) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], RF is turned OFF!!\n");
+		BTC_TRACE(trace_buf);
+	}
+
+	h2c_para[0] = 0xff;			/* IPS notify */
+	h2c_para[1] = 0xff;			/* LPS notify */
+	h2c_para[2] = rfstate_notify;	/* RF state notify */
+	h2c_para[3] = 0xff;			/* pnp notify */
+
+	btcoexist->btc_coex_h2c_process(btcoexist,
+					COL_OP_WIFI_POWER_STATE_NOTIFY,
+					opcode_ver, &h2c_para[0], 4);
+}
+
+void ex_halbtc8822b1ant_halt_notify(IN struct btc_coexist *btcoexist)
+{}
+void ex_halbtc8822b1ant_pnp_notify(IN struct btc_coexist *btcoexist,
+				   IN u8 pnp_state)
+{
+	u8			h2c_para[4] = {0};
+	u8			opcode_ver = 0;
+	u8			pnp_notify = 0;
+
+	if (BTC_WIFI_PNP_SLEEP == pnp_state) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], Pnp notify to SLEEP\n");
+		BTC_TRACE(trace_buf);
+		pnp_notify = 1;
+	} else if (BTC_WIFI_PNP_WAKE_UP == pnp_state) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], Pnp notify to WAKE UP\n");
+		BTC_TRACE(trace_buf);
+	}
+
+	h2c_para[0] = 0xff;			/* IPS notify */
+	h2c_para[1] = 0xff;			/* LPS notify */
+	h2c_para[2] = 0xff;			/* RF state notify */
+	h2c_para[3] = pnp_notify;		/* pnp notify */
+
+	btcoexist->btc_coex_h2c_process(btcoexist,
+					COL_OP_WIFI_POWER_STATE_NOTIFY,
+					opcode_ver, &h2c_para[0], 4);
+}
+
+void ex_halbtc8822b1ant_coex_dm_reset(IN struct btc_coexist *btcoexist)
+{}
+void ex_halbtc8822b1ant_periodical(IN struct btc_coexist *btcoexist)
+{
+
+	halbtc8822b1ant_wifi_info_notify(btcoexist);
+}
+
+void ex_halbtc8822b1ant_display_coex_info(IN struct btc_coexist *btcoexist)
+{
+	struct  btc_board_info		*board_info = &btcoexist->board_info;
+	struct  btc_stack_info		*stack_info = &btcoexist->stack_info;
+	struct  btc_bt_link_info	*bt_link_info = &btcoexist->bt_link_info;
+	u8				*cli_buf = btcoexist->cli_buf;
+	u8				u8tmp[4], i, bt_info_ext, ps_tdma_case = 0;
+	u16				u16tmp[4];
+	u32				u32tmp[4];
+	u32				fa_ofdm, fa_cck, cca_ofdm, cca_cck;
+	u32				fw_ver = 0, bt_patch_ver = 0, bt_coex_ver = 0;
+	static u8			pop_report_in_10s = 0;
+	u32			phyver = 0;
+	boolean			lte_coex_on = false;
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+		   "\r\n ============[BT Coexist info]============");
+	CL_PRINTF(cli_buf);
+
+	if (btcoexist->manual_control) {
+		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+			"\r\n ============[Under Manual Control]============");
+		CL_PRINTF(cli_buf);
+		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+			   "\r\n ==========================================");
+		CL_PRINTF(cli_buf);
+	}
+	if (btcoexist->stop_coex_dm) {
+		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+			   "\r\n ============[Coex is STOPPED]============");
+		CL_PRINTF(cli_buf);
+		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+			   "\r\n ==========================================");
+		CL_PRINTF(cli_buf);
+	}
+
+	if (psd_scan->ant_det_try_count == 0) {
+		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+			   "\r\n %-35s = %d/ %d/ %s / %d",
+			   "Ant PG Num/ Mech/ Pos/ RFE",
+			   board_info->pg_ant_num, board_info->btdm_ant_num,
+			   (board_info->btdm_ant_pos == BTC_ANTENNA_AT_MAIN_PORT
+			    ? "Main" : "Aux"),
+			   rfe_type->rfe_module_type);
+		CL_PRINTF(cli_buf);
+	} else {
+		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+			   "\r\n %-35s = %d/ %d/ %s/ %d  (%d/%d/%d)",
+			   "Ant PG Num/ Mech(Ant_Det)/ Pos/ RFE",
+			   board_info->pg_ant_num,
+			   board_info->btdm_ant_num_by_ant_det,
+			   (board_info->btdm_ant_pos == BTC_ANTENNA_AT_MAIN_PORT
+			    ? "Main" : "Aux"),
+			   rfe_type->rfe_module_type,
+			   psd_scan->ant_det_try_count,
+			   psd_scan->ant_det_fail_count,
+			   psd_scan->ant_det_result);
+		CL_PRINTF(cli_buf);
+
+		if (board_info->btdm_ant_det_finish) {
+			if (psd_scan->ant_det_result != 12)
+				CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s",
+					"Ant Det PSD Value",
+					psd_scan->ant_det_peak_val);
+			else
+				CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+					"\r\n %-35s = %d",
+					"Ant Det PSD Value",
+				psd_scan->ant_det_psd_scan_peak_val / 100);
+
+			CL_PRINTF(cli_buf);
+		}
+	}
+
+	btcoexist->btc_get(btcoexist, BTC_GET_U4_BT_PATCH_VER, &bt_patch_ver);
+	btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_FW_VER, &fw_ver);
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+		   "\r\n %-35s = %d_%x/ 0x%x/ 0x%x(%d)",
+		   "CoexVer/ FwVer/ PatchVer",
+		   glcoex_ver_date_8822b_1ant, glcoex_ver_8822b_1ant, fw_ver,
+		   bt_patch_ver, bt_patch_ver);
+	CL_PRINTF(cli_buf);
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %02x %02x %02x ",
+		   "Wifi channel informed to BT",
+		   coex_dm->wifi_chnl_info[0], coex_dm->wifi_chnl_info[1],
+		   coex_dm->wifi_chnl_info[2]);
+	CL_PRINTF(cli_buf);
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s/ %s/ %s",
+		   "WifibHiPri/ Ccklock/ CckEverLock",
+		   (coex_sta->wifi_is_high_pri_task ? "Yes" : "No"),
+		   (coex_sta->cck_lock ? "Yes" : "No"),
+		   (coex_sta->cck_ever_lock ? "Yes" : "No"));
+	CL_PRINTF(cli_buf);
+
+	/* wifi status */
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s",
+		   "============[Wifi Status]============");
+	CL_PRINTF(cli_buf);
+	btcoexist->btc_disp_dbg_msg(btcoexist, BTC_DBG_DISP_WIFI_STATUS);
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s",
+		   "============[BT Status]============");
+	CL_PRINTF(cli_buf);
+
+	pop_report_in_10s++;
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = [%s/ %d/ %d/ %d] ",
+		   "BT [status/ rssi/ retryCnt/ popCnt]",
+		   ((coex_sta->bt_disabled) ? ("disabled") :	((
+		   coex_sta->c2h_bt_inquiry_page) ? ("inquiry/page scan")
+			   : ((BT_8822B_1ANT_BT_STATUS_NON_CONNECTED_IDLE ==
+			       coex_dm->bt_status) ? "non-connected idle" :
+		((BT_8822B_1ANT_BT_STATUS_CONNECTED_IDLE == coex_dm->bt_status)
+				       ? "connected-idle" : "busy")))),
+		   coex_sta->bt_rssi - 100, coex_sta->bt_retry_cnt,
+		   coex_sta->pop_event_cnt);
+	CL_PRINTF(cli_buf);
+
+	if (pop_report_in_10s >= 5) {
+		coex_sta->pop_event_cnt = 0;
+		pop_report_in_10s = 0;
+	}
+
+	if (coex_sta->num_of_profile != 0)
+		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+			"\r\n %-35s = %s%s%s%s%s",
+			"Profiles",
+			((bt_link_info->a2dp_exist) ? "A2DP," : ""),
+			((bt_link_info->sco_exist) ?  "SCO," : ""),
+			((bt_link_info->hid_exist) ?
+			((coex_sta->hid_busy_num >= 2) ? "HID(4/18)," : "HID(2/18),") : ""),
+			((bt_link_info->pan_exist) ?  "PAN," : ""),
+			((coex_sta->voice_over_HOGP) ? "Voice" : ""));
+	else
+		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+			"\r\n %-35s = None", "Profiles");
+
+	CL_PRINTF(cli_buf);
+
+	if (bt_link_info->a2dp_exist) {
+		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s/ %d/ %s",
+			"A2DP Rate/Bitpool/Auto_Slot",
+			((coex_sta->is_A2DP_3M) ? "3M" : "No_3M"),
+			coex_sta->a2dp_bit_pool,
+			((coex_sta->is_autoslot) ? "On" : "Off"));
+		CL_PRINTF(cli_buf);
+	}
+
+	if (bt_link_info->hid_exist) {
+		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d",
+			   "HID PairNum/Forbid_Slot",
+			 coex_sta->hid_pair_cnt,
+			 coex_sta->forbidden_slot
+			 );
+		CL_PRINTF(cli_buf);
+	}
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s / %s/ 0x%x/ 0x%x",
+		"Role/IgnWlanAct/Feature/BLEScan",
+		((bt_link_info->slave_role) ? "Slave" : "Master"),
+		((coex_dm->cur_ignore_wlan_act) ? "Yes":"No"),
+		coex_sta->bt_coex_supported_feature,
+		coex_sta->bt_ble_scan_type);
+	CL_PRINTF(cli_buf);
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d/ %d/ %d",
+				   "ReInit/ReLink/IgnWlact/Page/NameReq",
+			 coex_sta->cnt_ReInit,
+		   coex_sta->cnt_setupLink,
+			 coex_sta->cnt_IgnWlanAct,
+				 coex_sta->cnt_Page,
+			 coex_sta->cnt_RemoteNameReq
+			 );
+		CL_PRINTF(cli_buf);
+
+	halbtc8822b1ant_read_score_board(btcoexist,	&u16tmp[0]);
+
+	if ((coex_sta->bt_reg_vendor_ae == 0xffff) ||
+	    (coex_sta->bt_reg_vendor_ac == 0xffff))
+		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = x/ x/ %04x",
+			   "0xae[4]/0xac[1:0]/Scoreboard", u16tmp[0]);
+	else
+		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+			   "\r\n %-35s = 0x%x/ 0x%x/ %04x",
+			   "0xae[4]/0xac[1:0]/Scoreboard",
+			 ((coex_sta->bt_reg_vendor_ae & BIT(4))>>4),
+			   coex_sta->bt_reg_vendor_ac & 0x3, u16tmp[0]);
+	CL_PRINTF(cli_buf);
+
+	for (i = 0; i < BT_INFO_SRC_8822B_1ANT_MAX; i++) {
+		if (coex_sta->bt_info_c2h_cnt[i]) {
+			CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+				"\r\n %-35s = %02x %02x %02x %02x %02x %02x %02x(%d)",
+				   glbt_info_src_8822b_1ant[i],
+				   coex_sta->bt_info_c2h[i][0],
+				   coex_sta->bt_info_c2h[i][1],
+				   coex_sta->bt_info_c2h[i][2],
+				   coex_sta->bt_info_c2h[i][3],
+				   coex_sta->bt_info_c2h[i][4],
+				   coex_sta->bt_info_c2h[i][5],
+				   coex_sta->bt_info_c2h[i][6],
+				   coex_sta->bt_info_c2h_cnt[i]);
+			CL_PRINTF(cli_buf);
+		}
+	}
+
+
+	if (btcoexist->manual_control)
+		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s",
+			"============[mechanisms] (before Manual)============");
+	else
+		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s",
+			   "============[mechanisms]============");
+	CL_PRINTF(cli_buf);
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d",
+		   "SM[LowPenaltyRA]",
+		   coex_dm->cur_low_penalty_ra);
+	CL_PRINTF(cli_buf);
+
+	ps_tdma_case = coex_dm->cur_ps_tdma;
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+		   "\r\n %-35s = %02x %02x %02x %02x %02x case-%d (%s,%s)",
+		   "PS TDMA",
+		   coex_dm->ps_tdma_para[0], coex_dm->ps_tdma_para[1],
+		   coex_dm->ps_tdma_para[2], coex_dm->ps_tdma_para[3],
+		   coex_dm->ps_tdma_para[4], ps_tdma_case,
+		   (coex_dm->cur_ps_tdma_on ? "On" : "Off"),
+		   (coex_dm->auto_tdma_adjust ? "Adj" : "Fix"));
+
+	CL_PRINTF(cli_buf);
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d",
+		   "WL/BT Coex Table Type",
+		   coex_sta->coex_table_type);
+	CL_PRINTF(cli_buf);
+
+	u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x6c0);
+	u32tmp[1] = btcoexist->btc_read_4byte(btcoexist, 0x6c4);
+	u32tmp[2] = btcoexist->btc_read_4byte(btcoexist, 0x6c8);
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+		   "\r\n %-35s = 0x%x/ 0x%x/ 0x%x",
+		   "0x6c0/0x6c4/0x6c8(coexTable)",
+		   u32tmp[0], u32tmp[1], u32tmp[2]);
+	CL_PRINTF(cli_buf);
+
+	u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x778);
+	u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x6cc);
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+		   "\r\n %-35s = 0x%x/ 0x%x/ 0x%x",
+		   "0x778/0x6cc/IgnWlanAct",
+		   u8tmp[0], u32tmp[0],  coex_dm->cur_ignore_wlan_act);
+	CL_PRINTF(cli_buf);
+
+	u32tmp[0] = halbtc8822b1ant_ltecoex_indirect_read_reg(btcoexist,
+			0xa0);
+	u32tmp[1] = halbtc8822b1ant_ltecoex_indirect_read_reg(btcoexist,
+			0xa4);
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x",
+		   "LTE Coex Table W_L/B_L",
+		   u32tmp[0] & 0xffff, u32tmp[1] & 0xffff);
+	CL_PRINTF(cli_buf);
+
+	u32tmp[0] = halbtc8822b1ant_ltecoex_indirect_read_reg(btcoexist,
+			0xa8);
+	u32tmp[1] = halbtc8822b1ant_ltecoex_indirect_read_reg(btcoexist,
+			0xac);
+	u32tmp[2] = halbtc8822b1ant_ltecoex_indirect_read_reg(btcoexist,
+			0xb0);
+	u32tmp[3] = halbtc8822b1ant_ltecoex_indirect_read_reg(btcoexist,
+			0xb4);
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+		   "\r\n %-35s = 0x%x/ 0x%x/ 0x%x/ 0x%x",
+		   "LTE Break Table W_L/B_L/L_W/L_B",
+		   u32tmp[0] & 0xffff, u32tmp[1] & 0xffff,
+		   u32tmp[2] & 0xffff, u32tmp[3] & 0xffff);
+	CL_PRINTF(cli_buf);
+
+	/* Hw setting		 */
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s",
+		   "============[Hw setting]============");
+	CL_PRINTF(cli_buf);
+/*
+	u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x430);
+	u32tmp[1] = btcoexist->btc_read_4byte(btcoexist, 0x434);
+	u16tmp[0] = btcoexist->btc_read_2byte(btcoexist, 0x42a);
+	u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x456);
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/0x%x/0x%x/0x%x",
+		   "0x430/0x434/0x42a/0x456",
+		   u32tmp[0], u32tmp[1], u16tmp[0], u8tmp[0]);
+	CL_PRINTF(cli_buf);
+*/
+
+	u32tmp[0] = halbtc8822b1ant_ltecoex_indirect_read_reg(btcoexist, 0x38);
+	u32tmp[1] = halbtc8822b1ant_ltecoex_indirect_read_reg(btcoexist, 0x54);
+	u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x73);
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %s",
+		   "LTE CoexOn/Path Ctrl Owner",
+		   (int)((u32tmp[0]&BIT(7)) >> 7),
+		   ((u8tmp[0]&BIT(2)) ? "WL" : "BT"));
+	CL_PRINTF(cli_buf);
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d/ %d",
+		   "LTE 3Wire/OPMode/UART/UARTMode",
+		   (int)((u32tmp[0]&BIT(6)) >> 6),
+		   (int)((u32tmp[0] & (BIT(5) | BIT(4))) >> 4),
+		   (int)((u32tmp[0]&BIT(3)) >> 3),
+		   (int)(u32tmp[0] & (BIT(2) | BIT(1) | BIT(0))));
+	CL_PRINTF(cli_buf);
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %s",
+		   "GNT_WL_SWCtrl/GNT_BT_SWCtrl/Dbg",
+		   (int)((u32tmp[0]&BIT(12)) >> 12),
+		   (int)((u32tmp[0]&BIT(14)) >> 14),
+		   ((u8tmp[0]&BIT(3)) ? "On" : "Off"));
+	CL_PRINTF(cli_buf);
+
+	u32tmp[0] = halbtc8822b1ant_ltecoex_indirect_read_reg(btcoexist, 0x54);
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d/ %d",
+		   "GNT_WL/GNT_BT/LTE_Busy/UART_Busy",
+		   (int)((u32tmp[0]&BIT(2)) >> 2),
+		   (int)((u32tmp[0]&BIT(3)) >> 3),
+		   (int)((u32tmp[0]&BIT(1)) >> 1), (int)(u32tmp[0]&BIT(0)));
+	CL_PRINTF(cli_buf);
+
+
+	u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x4c6);
+	u8tmp[1] = btcoexist->btc_read_1byte(btcoexist, 0x40);
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x",
+		   "0x4c6[4]/0x40[5] (WL/BT PTA)",
+		   (int)((u8tmp[0] & BIT(4)) >> 4),
+		   (int)((u8tmp[1] & BIT(5)) >> 5));
+	CL_PRINTF(cli_buf);
+
+	u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x550);
+	u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x522);
+	u8tmp[1] = btcoexist->btc_read_1byte(btcoexist, 0x953);
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x/ %s",
+		   "0x550(bcn ctrl)/0x522/4-RxAGC",
+		   u32tmp[0], u8tmp[0], (u8tmp[1] & 0x2) ? "On" : "Off");
+	CL_PRINTF(cli_buf);
+
+	u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0xda0);
+	u32tmp[1] = btcoexist->btc_read_4byte(btcoexist, 0xda4);
+	u32tmp[2] = btcoexist->btc_read_4byte(btcoexist, 0xda8);
+	u32tmp[3] = btcoexist->btc_read_4byte(btcoexist, 0xcf0);
+
+	u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0xa5b);
+	u8tmp[1] = btcoexist->btc_read_1byte(btcoexist, 0xa5c);
+
+	fa_ofdm = ((u32tmp[0] & 0xffff0000) >> 16) + ((u32tmp[1] & 0xffff0000)
+			>> 16) + (u32tmp[1] & 0xffff) + (u32tmp[2] & 0xffff) +
+		   ((u32tmp[3] & 0xffff0000) >> 16) + (u32tmp[3] &
+				   0xffff);
+	fa_cck = (u8tmp[0] << 8) + u8tmp[1];
+
+	u32tmp[1] = btcoexist->btc_read_4byte(btcoexist, 0xc50);
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+		   "\r\n %-35s = 0x%x/ 0x%x/ 0x%x/ 0x%x",
+		   "0xc50/OFDM-CCA/OFDM-FA/CCK-FA",
+		   u32tmp[1] & 0xff, u32tmp[0] & 0xffff, fa_ofdm, fa_cck);
+	CL_PRINTF(cli_buf);
+
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d/ %d",
+		   "CRC_OK CCK/11g/11n/11n-Agg",
+		   coex_sta->crc_ok_cck, coex_sta->crc_ok_11g,
+		   coex_sta->crc_ok_11n, coex_sta->crc_ok_11n_agg);
+	CL_PRINTF(cli_buf);
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d/ %d",
+		   "CRC_Err CCK/11g/11n/11n-Agg",
+		   coex_sta->crc_err_cck, coex_sta->crc_err_11g,
+		   coex_sta->crc_err_11n, coex_sta->crc_err_11n_agg);
+	CL_PRINTF(cli_buf);
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d",
+		   "0x770(high-pri rx/tx)",
+		   coex_sta->high_priority_rx, coex_sta->high_priority_tx);
+	CL_PRINTF(cli_buf);
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d",
+		   "0x774(low-pri rx/tx)",
+		   coex_sta->low_priority_rx, coex_sta->low_priority_tx);
+	CL_PRINTF(cli_buf);
+#if (BT_AUTO_REPORT_ONLY_8822B_1ANT == 1)
+	/* halbtc8822b1ant_monitor_bt_ctr(btcoexist); */
+#endif
+	btcoexist->btc_disp_dbg_msg(btcoexist, BTC_DBG_DISP_COEX_STATISTICS);
+}
+void ex_halbtc8822b1ant_antenna_detection(IN struct btc_coexist *btcoexist,
+		IN u32 cent_freq, IN u32 offset, IN u32 span, IN u32 seconds)
+{}
+void ex_halbtc8822b1ant_display_ant_detection(IN struct btc_coexist *btcoexist)
+{}
+void ex_halbtc8822b1ant_dbg_control(IN struct btc_coexist *btcoexist,
+				    IN u8 op_code, IN u8 op_len, IN u8 *pdata)
+{
+	switch (op_code) {
+	case BTC_DBG_SET_COEX_MANUAL_CTRL: {
+		boolean		manual = (boolean) *pdata;
+
+		halbtc8822b1ant_setManual(btcoexist, manual);
+	}
+	break;
+	default:
+		break;
+	}
+}
+
+#else
+void ex_halbtc8822b1ant_power_on_setting(IN struct btc_coexist *btcoexist)
+{
+	struct  btc_board_info	*board_info = &btcoexist->board_info;
+	u8 u8tmp = 0x0;
+	u16 u16tmp = 0x0;
+
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+		"xxxxxxxxxxxxxxxx Execute 8822b 1-Ant PowerOn Setting!! xxxxxxxxxxxxxxxx\n");
+	BTC_TRACE(trace_buf);
+
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+		    "Ant Det Finish = %s, Ant Det Number  = %d\n",
+		    board_info->btdm_ant_det_finish ? "Yes" : "No",
+		    board_info->btdm_ant_num_by_ant_det);
+	BTC_TRACE(trace_buf);
+
+	btcoexist->stop_coex_dm = true;
+
+	/* enable BB, REG_SYS_FUNC_EN such that we can write 0x948 correctly. */
+	u16tmp = btcoexist->btc_read_2byte(btcoexist, 0x2);
+	btcoexist->btc_write_2byte(btcoexist, 0x2, u16tmp | BIT(0) | BIT(1));
+
+	/* set Path control owner to WiFi */
+	halbtc8822b1ant_ltecoex_pathcontrol_owner(btcoexist,
+			BT_8822B_1ANT_PCO_WLSIDE);
+
+	/* set GNT_BT to high */
+	halbtc8822b1ant_ltecoex_set_gnt_bt(btcoexist,
+					   BT_8822B_1ANT_GNT_BLOCK_RFC_BB,
+					   BT_8822B_1ANT_GNT_CTRL_BY_SW,
+					   BT_8822B_1ANT_SIG_STA_SET_TO_HIGH);
+	/* Set GNT_WL to low */
+	halbtc8822b1ant_ltecoex_set_gnt_wl(btcoexist,
+					   BT_8822B_1ANT_GNT_BLOCK_RFC_BB,
+					   BT_8822B_1ANT_GNT_CTRL_BY_SW,
+					   BT_8822B_1ANT_SIG_STA_SET_TO_LOW);
+
+	/* set WLAN_ACT = 0 */
+	/* btcoexist->btc_write_1byte(btcoexist, 0x76e, 0x4); */
+
+	/* SD1 Chunchu red x issue */
+	btcoexist->btc_write_1byte(btcoexist, 0xff1a, 0x0);
+
+	halbtc8822b1ant_enable_gnt_to_gpio(btcoexist, true);
+
+	/* */
+	/* S0 or S1 setting and Local register setting(By the setting fw can get ant number, S0/S1, ... info) */
+	/* Local setting bit define */
+	/*	BIT0: "0" for no antenna inverse; "1" for antenna inverse  */
+	/*	BIT1: "0" for internal switch; "1" for external switch */
+	/*	BIT2: "0" for one antenna; "1" for two antenna */
+	/* NOTE: here default all internal switch and 1-antenna ==> BIT1=0 and BIT2=0 */
+
+	u8tmp = 0;
+	board_info->btdm_ant_pos = BTC_ANTENNA_AT_MAIN_PORT;
+
+	if (btcoexist->chip_interface == BTC_INTF_USB)
+		btcoexist->btc_write_local_reg_1byte(btcoexist, 0xfe08, u8tmp);
+	else if (btcoexist->chip_interface == BTC_INTF_SDIO)
+		btcoexist->btc_write_local_reg_1byte(btcoexist, 0x60, u8tmp);
+
+	BTC_TRACE(trace_buf);
+
+
+}
+
+void ex_halbtc8822b1ant_power_on_setting_without_bt(IN struct btc_coexist
+		*btcoexist)
+{
+	struct  btc_board_info	*board_info = &btcoexist->board_info;
+	u8 u8tmp = 0x0;
+	u16 u16tmp = 0x0;
+
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+		    " 8822b 1-Ant PowerOn Setting without bt\n");
+	BTC_TRACE(trace_buf);
+
+	btcoexist->stop_coex_dm = true;
+
+	/* enable BB, REG_SYS_FUNC_EN such that we can write 0x948 correctly. */
+	u16tmp = btcoexist->btc_read_2byte(btcoexist, 0x2);
+	btcoexist->btc_write_2byte(btcoexist, 0x2, u16tmp | BIT(0) | BIT(1));
+
+
+	/* SD1 Chunchu red x issue */
+	btcoexist->btc_write_1byte(btcoexist, 0xff1a, 0x0);
+
+	u8tmp = 0;
+	board_info->btdm_ant_pos = BTC_ANTENNA_AT_MAIN_PORT;
+
+	if (btcoexist->chip_interface == BTC_INTF_USB)
+		btcoexist->btc_write_local_reg_1byte(btcoexist, 0xfe08, u8tmp);
+	else if (btcoexist->chip_interface == BTC_INTF_SDIO)
+		btcoexist->btc_write_local_reg_1byte(btcoexist, 0x60, u8tmp);
+
+
+
+}
+
+
+void ex_halbtc8822b1ant_pre_load_firmware(IN struct btc_coexist *btcoexist)
+{
+}
+
+void ex_halbtc8822b1ant_init_hw_config(IN struct btc_coexist *btcoexist,
+				       IN boolean wifi_only)
+{
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+		    "[BTCoex], ********** (ini hw config) **********\n");
+
+	halbtc8822b1ant_init_hw_config(btcoexist, true, wifi_only);
+	btcoexist->stop_coex_dm = false;
+}
+
+void ex_halbtc8822b1ant_init_hw_config_without_bt(IN struct btc_coexist
+		*btcoexist,
+		IN boolean wifi_only)
+{
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+		    "[BTCoex], ********** (ini hw config) **********\n");
+
+	halbtc8822b1ant_init_hw_config_without_bt(btcoexist, true, wifi_only);
+	btcoexist->stop_coex_dm = true;
+}
+
+void ex_halbtc8822b1ant_antenna_switch_without_bt(IN struct btc_coexist
+		*btcoexist)
+{
+
+	boolean wifi_under_5g = false;
+
+
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_5G, &wifi_under_5g);
+
+	if (wifi_under_5g)
+
+		btcoexist->btc_write_1byte_bitmask(btcoexist, 0xcbd,
+						   0x3, 1);
+
+	else
+		btcoexist->btc_write_1byte_bitmask(btcoexist,
+						   0xcbd, 0x3, 2);
+
+
+}
+
+void ex_halbtc8822b1ant_init_coex_dm(IN struct btc_coexist *btcoexist)
+{
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+		    "[BTCoex], Coex Mechanism Init!!\n");
+	BTC_TRACE(trace_buf);
+
+	btcoexist->stop_coex_dm = false;
+
+	halbtc8822b1ant_init_coex_dm(btcoexist);
+
+	halbtc8822b1ant_query_bt_info(btcoexist);
+}
+
+void ex_halbtc8822b1ant_display_coex_info(IN struct btc_coexist *btcoexist)
+{
+
+	struct  btc_board_info		*board_info = &btcoexist->board_info;
+	struct  btc_bt_link_info	*bt_link_info = &btcoexist->bt_link_info;
+	u8				*cli_buf = btcoexist->cli_buf;
+	u8				u8tmp[4], i, bt_info_ext, ps_tdma_case = 0;
+	u16				u16tmp[4];
+	u32				fa_ofdm, fa_cck, cca_ofdm, cca_cck;
+	u32				u32tmp[4];
+	u32				fa_of_dm;
+	u32				fw_ver = 0, bt_patch_ver = 0;
+	static u8			pop_report_in_10s = 0;
+	u32                       phyver = 0;
+	 /*u32 pnp_wake_cnt=0;*/
+
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+		    "[BTCoex], ********** (display coexinfo) **********\n");
+	BTC_TRACE(trace_buf);
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+		"[BTCoex], ********** displaycoexinfostart, 0xcb4/0xcbd = 0x%x/0x%x\n",
+		    btcoexist->btc_read_1byte(btcoexist, 0xcb4),
+		    btcoexist->btc_read_1byte(btcoexist, 0xcbd));
+	BTC_TRACE(trace_buf);
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+		   "\r\n ============[BT Coexist info]============");
+	CL_PRINTF(cli_buf);
+
+	if (btcoexist->manual_control) {
+		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+			"\r\n ============[Under Manual Control]============");
+		CL_PRINTF(cli_buf);
+		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+			   "\r\n ==========================================");
+		CL_PRINTF(cli_buf);
+	}
+
+	if (btcoexist->stop_coex_dm) {
+		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+			   "\r\n ============[Coex is STOPPED]============");
+		CL_PRINTF(cli_buf);
+		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+			   "\r\n ==========================================");
+		CL_PRINTF(cli_buf);
+	}
+
+	if (psd_scan->ant_det_try_count == 0) {
+		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+			   "\r\n %-35s = %d/ %d/ %d/ %d",
+			   "Ant PG Num/ Mech/ Pos/ RFE",
+			   board_info->pg_ant_num, board_info->btdm_ant_num,
+			   board_info->btdm_ant_pos,
+			   rfe_type->rfe_module_type);
+		CL_PRINTF(cli_buf);
+	} else {
+		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+			   "\r\n %-35s = %d/ %d/ %d/ %d  (%d/%d/%d)",
+			   "Ant PG Num/ Mech(Ant_Det)/ Pos/ RFE",
+			   board_info->pg_ant_num,
+			   board_info->btdm_ant_num_by_ant_det,
+			   board_info->btdm_ant_pos,
+			   rfe_type->rfe_module_type,
+			   psd_scan->ant_det_try_count,
+			   psd_scan->ant_det_fail_count,
+			   psd_scan->ant_det_result);
+		CL_PRINTF(cli_buf);
+
+		if (board_info->btdm_ant_det_finish) {
+			CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s",
+				   "Ant Det PSD Value",
+				   psd_scan->ant_det_peak_val);
+			CL_PRINTF(cli_buf);
+		}
+	}
+	/*btcoexist->btc_get(btcoexist, BTC_GET_U4_BT_PATCH_VER, &bt_patch_ver);*/
+	bt_patch_ver = btcoexist->bt_info.bt_get_fw_ver;
+	btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_FW_VER, &fw_ver);
+	phyver = btcoexist->btc_get_bt_phydm_version(btcoexist);
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+		   "\r\n %-35s = %d_%02x/ 0x%02x/ 0x%02x (%s)",
+		   "CoexVer WL/  BT_Desired/ BT_Report",
+		   glcoex_ver_date_8822b_1ant, glcoex_ver_8822b_1ant,
+		   glcoex_ver_btdesired_8822b_1ant,
+		   ((coex_sta->bt_coex_supported_version & 0xff00) >>
+		    8),
+		   (((coex_sta->bt_coex_supported_version & 0xff00) >>
+		     8) >=
+		    glcoex_ver_btdesired_8822b_1ant ? "Match" :
+		    "Mis-Match"));
+	CL_PRINTF(cli_buf);
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+		   "\r\n %-35s = 0x%x/ 0x%x/ v%d/ %c",
+		   "W_FW/ B_FW/ Phy/ Kt",
+		   fw_ver, bt_patch_ver, phyver,
+		   coex_sta->cut_version + 65);
+	CL_PRINTF(cli_buf);
+
+
+
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %02x %02x %02x ",
+		   "Wifi channel informed to BT",
+		   coex_dm->wifi_chnl_info[0], coex_dm->wifi_chnl_info[1],
+		   coex_dm->wifi_chnl_info[2]);
+	CL_PRINTF(cli_buf);
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s/ %s/ %s",
+		   "WifibHiPri/ Ccklock/ CckEverLock",
+		   (coex_sta->wifi_is_high_pri_task ? "Yes" : "No"),
+		   (coex_sta->cck_lock ? "Yes" : "No"),
+		   (coex_sta->cck_ever_lock ? "Yes" : "No"));
+	CL_PRINTF(cli_buf);
+
+	/* wifi status */
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s",
+		   "============[Wifi Status]============");
+	CL_PRINTF(cli_buf);
+	btcoexist->btc_disp_dbg_msg(btcoexist, BTC_DBG_DISP_WIFI_STATUS);
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s",
+		   "============[BT Status]============");
+	CL_PRINTF(cli_buf);
+
+	pop_report_in_10s++;
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = [%s/ %d/ %d/ %d] ",
+		   "BT [status/ rssi/ retryCnt/ popCnt]",
+		   ((coex_sta->bt_disabled) ? ("disabled") :	((
+		   coex_sta->c2h_bt_inquiry_page) ? ("inquiry/page scan")
+			   : ((BT_8822B_1ANT_BT_STATUS_NON_CONNECTED_IDLE ==
+			       coex_dm->bt_status) ? "non-connected idle" :
+		((BT_8822B_1ANT_BT_STATUS_CONNECTED_IDLE == coex_dm->bt_status)
+				       ? "connected-idle" : "busy")))),
+		   coex_sta->bt_rssi - 100, coex_sta->bt_retry_cnt,
+		   coex_sta->pop_event_cnt);
+	CL_PRINTF(cli_buf);
+	/*bt rssi */
+	/*bt pop_even_cnt : bt retry*/
+
+	if (pop_report_in_10s >= 5) {
+		coex_sta->pop_event_cnt = 0;
+		pop_report_in_10s = 0;
+	}
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+		   "\r\n %-35s = %d / %d / %d / %d / %d",
+		   "SCO/HID/PAN/A2DP/Hi-Pri",
+		   bt_link_info->sco_exist, bt_link_info->hid_exist,
+		   bt_link_info->pan_exist, bt_link_info->a2dp_exist,
+		   bt_link_info->bt_hi_pri_link_exist);
+	CL_PRINTF(cli_buf);
+
+	{
+		bt_info_ext = coex_sta->bt_info_ext;
+
+		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+			   "\r\n %-35s = %s / %s / %d/ %x/ %02x",
+			   "Role/A2DP Rate/Bitpool/Feature/Ver",
+			   ((bt_link_info->slave_role) ? "Slave" : "Master"),
+			   (bt_info_ext & BIT(0)) ? "BR" : "EDR",
+			   coex_sta->a2dp_bit_pool,
+			   coex_sta->bt_coex_supported_feature,
+			((coex_sta->bt_coex_supported_version & 0xff00) >> 8));
+		CL_PRINTF(cli_buf);
+	}
+
+	/*bt info*/
+	for (i = 0; i < BT_INFO_SRC_8822B_1ANT_MAX; i++) {
+		if (coex_sta->bt_info_c2h_cnt[i]) {
+			CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+				"\r\n %-35s = %02x %02x %02x %02x %02x %02x %02x(%d)",
+				   glbt_info_src_8822b_1ant[i],
+				   coex_sta->bt_info_c2h[i][0],
+				   coex_sta->bt_info_c2h[i][1],
+				   coex_sta->bt_info_c2h[i][2],
+				   coex_sta->bt_info_c2h[i][3],
+				   coex_sta->bt_info_c2h[i][4],
+				   coex_sta->bt_info_c2h[i][5],
+				   coex_sta->bt_info_c2h[i][6],
+				   coex_sta->bt_info_c2h_cnt[i]);
+			CL_PRINTF(cli_buf);
+		}
+	}
+
+
+	if (btcoexist->manual_control)
+		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s",
+			"============[mechanisms] (before Manual)============");
+	else
+		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s",
+			   "============[mechanisms]============");
+	CL_PRINTF(cli_buf);
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d",
+		   "SM[LowPenaltyRA]",
+		   coex_dm->cur_low_penalty_ra);
+	CL_PRINTF(cli_buf);
+
+	/*(ps)tdma*/
+	ps_tdma_case = coex_dm->cur_ps_tdma;
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+		   "\r\n %-35s = %02x %02x %02x %02x %02x case-%d (%s,%s)",
+		   "PS TDMA",
+		   coex_dm->ps_tdma_para[0], coex_dm->ps_tdma_para[1],
+		   coex_dm->ps_tdma_para[2], coex_dm->ps_tdma_para[3],
+		   coex_dm->ps_tdma_para[4], ps_tdma_case,
+		   (coex_dm->cur_ps_tdma_on ? "On" : "Off"),
+		   (coex_dm->auto_tdma_adjust ? "Adj" : "Fix"));
+
+	CL_PRINTF(cli_buf);
+
+	/*coex table type*/
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d",
+		   "WL/BT Coex Table Type",
+		   coex_sta->coex_table_type);
+	CL_PRINTF(cli_buf);
+
+	/*coex table :0x6c0 0x6c4 , break table: 0x6c8*/
+	u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x6c0);
+	u32tmp[1] = btcoexist->btc_read_4byte(btcoexist, 0x6c4);
+	u32tmp[2] = btcoexist->btc_read_4byte(btcoexist, 0x6c8);
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+		   "\r\n %-35s = 0x%x/ 0x%x/ 0x%x",
+		   "0x6c0/0x6c4/0x6c8(coexTable)",
+		   u32tmp[0], u32tmp[1], u32tmp[2]);
+	CL_PRINTF(cli_buf);
+
+	/*PTA : 0x778=1/3/d , WL BA,RTS,CTS :0x6cc  H/L pri */
+	u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x778);
+	u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x6cc);
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+		   "\r\n %-35s = 0x%x/ 0x%x/ 0x%x",
+		   "0x778/0x6cc/IgnWlanAct",
+		   u8tmp[0], u32tmp[0],  coex_dm->cur_ignore_wlan_act);
+	CL_PRINTF(cli_buf);
+
+
+	/*LTE : WL/LTE coex table : 0xa0 */
+
+	u32tmp[0] = halbtc8822b1ant_ltecoex_indirect_read_reg(btcoexist,
+			0xa0);
+
+	/*LTE : BT/LTE coex table : 0xa4 */
+	u32tmp[1] = halbtc8822b1ant_ltecoex_indirect_read_reg(btcoexist,
+			0xa4);
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x",
+		   "LTE Coex Table W_L/B_L",
+		   u32tmp[0] & 0xffff, u32tmp[1] & 0xffff);
+	CL_PRINTF(cli_buf);
+
+	/*LTE : WL/LTE break table : 0xa8 */
+	u32tmp[0] = halbtc8822b1ant_ltecoex_indirect_read_reg(btcoexist,
+			0xa8);
+	/*LTE : WL/LTE break table : 0xac */
+	u32tmp[1] = halbtc8822b1ant_ltecoex_indirect_read_reg(btcoexist,
+			0xac);
+	/*LTE : LTE/WL break table : 0xb0 */
+	u32tmp[2] = halbtc8822b1ant_ltecoex_indirect_read_reg(btcoexist,
+			0xb0);
+	/*LTE : LTE/BT break table : 0xb4 */
+	u32tmp[3] = halbtc8822b1ant_ltecoex_indirect_read_reg(btcoexist,
+			0xb4);
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+		   "\r\n %-35s = 0x%x/ 0x%x/ 0x%x/ 0x%x",
+		   "LTE Break Table W_L/B_L/L_W/L_B",
+		   u32tmp[0] & 0xffff, u32tmp[1] & 0xffff,
+		   u32tmp[2] & 0xffff, u32tmp[3] & 0xffff);
+	CL_PRINTF(cli_buf);
+
+	/* Hw setting		 */
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s",
+		   "============[Hw setting]============");
+	CL_PRINTF(cli_buf);
+
+
+	u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x430);
+	u32tmp[1] = btcoexist->btc_read_4byte(btcoexist, 0x434);
+	u16tmp[0] = btcoexist->btc_read_2byte(btcoexist, 0x42a);
+	u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x456);
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/0x%x/0x%x/0x%x",
+		   "0x430/0x434/0x42a/0x456",
+		   u32tmp[0], u32tmp[1], u16tmp[0], u8tmp[0]);
+	CL_PRINTF(cli_buf);
+
+	/*ANT setting*/
+	u8tmp[1] = btcoexist->btc_read_1byte(btcoexist, 0xcb4);
+	u8tmp[2] = btcoexist->btc_read_1byte(btcoexist, 0xcbd);
+	u8tmp[3] = btcoexist->btc_read_1byte(btcoexist, 0x1991);
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x/ 0x%x",
+		   "0xcb4/0xcbd/0x1991",
+		   u8tmp[1], u8tmp[2], u8tmp[3]);
+	CL_PRINTF(cli_buf);
+
+	/*LTE on/off , Path ctrl owner*/
+	/*sy add*/
+	u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x4c);
+	u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x73);
+	u8tmp[1] = btcoexist->btc_read_1byte(btcoexist, 0x64);
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x/ 0x%x",
+		   "0x73/ 0x4c/ 0x64[0]", u8tmp[0],
+		   (u32tmp[0] & (BIT(24) | BIT(23))) >> 23,
+		   u8tmp[1] & 0x1);
+	CL_PRINTF(cli_buf);
+
+
+	u32tmp[0] = halbtc8822b1ant_ltecoex_indirect_read_reg(btcoexist, 0x38);
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %s",
+		   "LTE CoexOn/Path Ctrl Owner",
+		   (int)((u32tmp[0]&BIT(7)) >> 7),
+		   ((u8tmp[0]&BIT(2)) ? "WL" : "BT"));
+	CL_PRINTF(cli_buf);
+
+	/*LTE mode*/
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d/ %d",
+		   "LTE 3Wire/OPMode/UART/UARTMode",
+		   (int)((u32tmp[0]&BIT(6)) >> 6),
+		   (int)((u32tmp[0] & (BIT(5) | BIT(4))) >> 4),
+		   (int)((u32tmp[0]&BIT(3)) >> 3),
+		   (int)(u32tmp[0] & (BIT(2) | BIT(1) | BIT(0))));
+	CL_PRINTF(cli_buf);
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %s",
+		   "GNT_WL_SWCtrl/GNT_BT_SWCtrl/Dbg",
+		   (int)((u32tmp[0]&BIT(12)) >> 12),
+		   (int)((u32tmp[0]&BIT(14)) >> 14),
+		   ((u8tmp[0]&BIT(3)) ? "On" : "Off"));
+	CL_PRINTF(cli_buf);
+
+	u32tmp[0] = halbtc8822b1ant_ltecoex_indirect_read_reg(btcoexist, 0x54);
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d/ %d",
+		   "GNT_WL/GNT_BT/LTE_Busy/UART_Busy",
+		   (int)((u32tmp[0]&BIT(2)) >> 2),
+		   (int)((u32tmp[0]&BIT(3)) >> 3),
+		   (int)((u32tmp[0]&BIT(1)) >> 1), (int)(u32tmp[0]&BIT(0)));
+	CL_PRINTF(cli_buf);
+
+
+	u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x4c6);
+	u8tmp[1] = btcoexist->btc_read_1byte(btcoexist, 0x40);
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x",
+		   "0x4c6[4]/0x40[5] (WL/BT PTA)",
+		   (int)((u8tmp[0] & BIT(4)) >> 4),
+		   (int)((u8tmp[1] & BIT(5)) >> 5));
+	CL_PRINTF(cli_buf);
+
+	u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x550);
+	u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x522);
+	u8tmp[1] = btcoexist->btc_read_1byte(btcoexist, 0x953);
+	u8tmp[2] = btcoexist->btc_read_1byte(btcoexist, 0xc50);
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+		   "\r\n %-35s = 0x%x/ 0x%x/ %s/ 0x%x",
+		   "0x550/0x522/4-RxAGC/0xc50",
+		u32tmp[0], u8tmp[0], (u8tmp[1] & 0x2) ? "On" : "Off", u8tmp[2]);
+	CL_PRINTF(cli_buf);
+
+#if 0 /* phydm v008 doesn't support this feature */
+	fa_ofdm = btcoexist->btc_phydm_query_PHY_counter(btcoexist,
+			PHYDM_INFO_FA_OFDM);
+	fa_cck = btcoexist->btc_phydm_query_PHY_counter(btcoexist,
+			PHYDM_INFO_FA_CCK);
+	cca_ofdm = btcoexist->btc_phydm_query_PHY_counter(btcoexist,
+			PHYDM_INFO_CCA_OFDM);
+	cca_cck = btcoexist->btc_phydm_query_PHY_counter(btcoexist,
+			PHYDM_INFO_CCA_CCK);
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+		   "\r\n %-35s = 0x%x/ 0x%x/ 0x%x/ 0x%x",
+		   "CCK-CCA/CCK-FA/OFDM-CCA/OFDM-FA",
+		   cca_cck, fa_cck, cca_ofdm, fa_ofdm);
+	CL_PRINTF(cli_buf);
+#endif
+
+
+#if 1
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d/ %d",
+		   "CRC_OK CCK/11g/11n/11ac",
+		   coex_sta->crc_ok_cck, coex_sta->crc_ok_11g,
+		   coex_sta->crc_ok_11n, coex_sta->crc_ok_11n_vht);
+	CL_PRINTF(cli_buf);
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d/ %d",
+		   "CRC_Err CCK/11g/11n/11ac",
+		   coex_sta->crc_err_cck, coex_sta->crc_err_11g,
+		   coex_sta->crc_err_11n, coex_sta->crc_err_11n_vht);
+	CL_PRINTF(cli_buf);
+#endif
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s/ %s/ %s",
+		   "Wifi-HiPri/ Ccklock/ CckEverLock",
+		   (coex_sta->wifi_is_high_pri_task ? "Yes" : "No"),
+		   (coex_sta->cck_lock ? "Yes" : "No"),
+		   (coex_sta->cck_ever_lock ? "Yes" : "No"));
+	CL_PRINTF(cli_buf);
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d",
+		   "0x770(high-pri rx/tx)",
+		   coex_sta->high_priority_rx, coex_sta->high_priority_tx);
+	CL_PRINTF(cli_buf);
+	/*0x774:bt low pri trx*/
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d",
+		   "0x774(low-pri rx/tx)",
+		   coex_sta->low_priority_rx, coex_sta->low_priority_tx);
+	CL_PRINTF(cli_buf);
+
+	halbtc8822b1ant_read_score_board(btcoexist,	&u16tmp[0]);
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %04x",
+		   "ScoreBoard[14:0] (from BT)", u16tmp[0]);
+
+	btcoexist->btc_disp_dbg_msg(btcoexist, BTC_DBG_DISP_COEX_STATISTICS);
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+		"[BTCoex], ********** displaycoexinfo end, 0xcb4/0xcbd = 0x%x/0x%x\n",
+		    btcoexist->btc_read_1byte(btcoexist, 0xcb4),
+		    btcoexist->btc_read_1byte(btcoexist, 0xcbd));
+	BTC_TRACE(trace_buf);
+	/*
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			"[BTCoex], ********** pnp_wake_cnt = %d\n", pnp_wake_cnt);
+	BTC_TRACE(trace_buf);
+	*/
+}
+
+
+void ex_halbtc8822b1ant_ips_notify(IN struct btc_coexist *btcoexist, IN u8 type)
+{
+
+	if (btcoexist->manual_control ||	btcoexist->stop_coex_dm)
+		return;
+
+
+	if (BTC_IPS_ENTER == type) {
+
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], IPS ENTER notify\n");
+		BTC_TRACE(trace_buf);
+		coex_sta->under_ips = true;
+
+		/* Write WL "Active" in Score-board for LPS off */
+		halbtc8822b1ant_post_state_to_bt(btcoexist,
+				BT_8822B_1ANT_SCOREBOARD_ACTIVE, false);
+
+		halbtc8822b1ant_post_state_to_bt(btcoexist,
+				BT_8822B_1ANT_SCOREBOARD_ONOFF, false);
+
+		halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 0);
+
+		halbtc8822b1ant_set_ant_path(btcoexist,
+					     BTC_ANT_PATH_AUTO,
+					     FORCE_EXEC,
+					     BT_8822B_1ANT_PHASE_WLAN_OFF);
+
+		halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0);
+	} else if (BTC_IPS_LEAVE == type) {
+
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], IPS LEAVE notify\n");
+		BTC_TRACE(trace_buf);
+		halbtc8822b1ant_post_state_to_bt(btcoexist,
+				BT_8822B_1ANT_SCOREBOARD_ACTIVE, true);
+
+		halbtc8822b1ant_post_state_to_bt(btcoexist,
+				BT_8822B_1ANT_SCOREBOARD_ONOFF, true);
+
+		/*leave IPS : run ini hw config (exclude wifi only)*/
+		halbtc8822b1ant_init_hw_config(btcoexist, false, false);
+		/*sw all off*/
+		halbtc8822b1ant_init_coex_dm(btcoexist);
+		/*leave IPS : Query bt info*/
+		halbtc8822b1ant_query_bt_info(btcoexist);
+
+		coex_sta->under_ips = false;
+	}
+}
+
+void ex_halbtc8822b1ant_lps_notify(IN struct btc_coexist *btcoexist, IN u8 type)
+{
+	if (btcoexist->manual_control || btcoexist->stop_coex_dm)
+		return;
+
+	if (BTC_LPS_ENABLE == type) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], LPS ENABLE notify\n");
+		BTC_TRACE(trace_buf);
+		coex_sta->under_lps = true;
+
+		if (coex_sta->force_lps_on == true) { /* LPS No-32K */
+			/* Write WL "Active" in Score-board for PS-TDMA */
+			halbtc8822b1ant_post_state_to_bt(btcoexist,
+					 BT_8822B_1ANT_SCOREBOARD_ACTIVE, true);
+
+		} else { /* LPS-32K, need check if this h2c 0x71 can work?? (2015/08/28) */
+			/* Write WL "Non-Active" in Score-board for Native-PS */
+			halbtc8822b1ant_post_state_to_bt(btcoexist,
+				 BT_8822B_1ANT_SCOREBOARD_ACTIVE, false);
+
+		}
+	} else if (BTC_LPS_DISABLE == type) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], LPS DISABLE notify\n");
+		BTC_TRACE(trace_buf);
+		coex_sta->under_lps = false;
+
+		/* Write WL "Active" in Score-board for LPS off */
+		halbtc8822b1ant_post_state_to_bt(btcoexist,
+					 BT_8822B_1ANT_SCOREBOARD_ACTIVE, true);
+
+	}
+}
+
+
+void ex_halbtc8822b1ant_scan_notify(IN struct btc_coexist *btcoexist,
+				    IN u8 type)
+{
+	boolean	wifi_connected = false;
+	boolean wifi_under_5g = false;
+
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+		    "[BTCoex], SCAN notify()\n");
+	BTC_TRACE(trace_buf);
+
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED,
+			   &wifi_connected);
+
+
+
+	if (btcoexist->manual_control ||
+	    btcoexist->stop_coex_dm)
+		return;
+
+	if (BTC_SCAN_START == type) {
+		btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_5G, &wifi_under_5g);
+
+		if (wifi_under_5g) {
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				"[BTCoex], ********** (scan_notify_5g_scan_start) **********\n");
+			BTC_TRACE(trace_buf);
+			halbtc8822b1ant_action_wifi_under5g(btcoexist);
+			return;
+		}
+
+		/* under 2.4G */
+		coex_sta->wifi_is_high_pri_task = true;
+
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			"[BTCoex], ********** (scan_notify_2g_scan_start) **********\n");
+		BTC_TRACE(trace_buf);
+
+		if (!wifi_connected) {	/* non-connected scan */
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				"[BTCoex], ********** wifi is not connected scan **********\n");
+			BTC_TRACE(trace_buf);
+			halbtc8822b1ant_action_wifi_not_connected_scan(
+				btcoexist);
+		} else {	/* wifi is connected */
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				"[BTCoex], ********** wifi is connected scan **********\n");
+			BTC_TRACE(trace_buf);
+			halbtc8822b1ant_action_wifi_connected_scan(
+				btcoexist);
+		}
+
+		return;
+	}
+
+	if (BTC_SCAN_START_2G == type) {
+		coex_sta->wifi_is_high_pri_task = true;
+
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			"[BTCoex], ********** (scan_notify_2g_sacn_start_for_switch_band_used) **********\n");
+		BTC_TRACE(trace_buf);
+
+		if (!wifi_connected) {	/* non-connected scan */
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				"[BTCoex], ********** wifi is not connected **********\n");
+			BTC_TRACE(trace_buf);
+
+			halbtc8822b1ant_action_wifi_not_connected_scan(
+				btcoexist);
+		} else	{ /* wifi is connected */
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				"[BTCoex], ********** wifi is connected **********\n");
+			BTC_TRACE(trace_buf);
+			halbtc8822b1ant_action_wifi_connected_scan(btcoexist);
+		}
+	} else {
+		coex_sta->wifi_is_high_pri_task = false;
+
+		/*WL scan finish , then get and update sacn ap numbers */
+		btcoexist->btc_get(btcoexist, BTC_GET_U1_AP_NUM,
+				   &coex_sta->scan_ap_num);
+
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			"[BTCoex], ********** (scan_finish_notify) **********\n");
+		BTC_TRACE(trace_buf);
+
+		if (!wifi_connected)	/* non-connected scan */
+			halbtc8822b1ant_action_wifi_not_connected(btcoexist);
+		else {
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				"[BTCoex], ********** scan_finish_notify wifi is connected **********\n");
+			BTC_TRACE(trace_buf);
+			halbtc8822b1ant_action_wifi_connected(btcoexist);
+		}
+	}
+}
+
+
+
+void ex_halbtc8822b1ant_scan_notify_without_bt(IN struct btc_coexist *btcoexist,
+		IN u8 type)
+{
+
+	boolean wifi_under_5g = false;
+
+	if (BTC_SCAN_START == type) {
+		btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_5G, &wifi_under_5g);
+
+		if (wifi_under_5g) {
+			btcoexist->btc_write_1byte_bitmask(btcoexist, 0xcbd,
+							   0x3, 1);
+			return;
+		}
+
+		/* under 2.4G */
+		btcoexist->btc_write_1byte_bitmask(btcoexist, 0xcbd,
+						   0x3, 2);
+		return;
+	}
+	if (BTC_SCAN_START_2G == type)
+		btcoexist->btc_write_1byte_bitmask(btcoexist, 0xcbd, 0x3, 2);
+}
+
+void ex_halbtc8822b1ant_switchband_notify(IN struct btc_coexist *btcoexist,
+		IN u8 type)
+{
+
+	boolean wifi_connected = false;
+
+
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+		    "[BTCoex], ********** (switchband_notify) **********\n");
+	BTC_TRACE(trace_buf);
+
+	if (btcoexist->manual_control ||
+	    btcoexist->stop_coex_dm)
+		return;
+
+
+	if (type == BTC_SWITCH_TO_5G) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			"[BTCoex], ********** (switchband_notify BTC_SWITCH_TO_5G) **********\n");
+		BTC_TRACE(trace_buf);
+
+		halbtc8822b1ant_action_wifi_under5g(btcoexist);
+		return;
+	} else if (type == BTC_SWITCH_TO_24G_NOFORSCAN) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			"[BTCoex], ********** (switchband_notify BTC_SWITCH_TO_2G (no for scan)) **********\n");
+		BTC_TRACE(trace_buf);
+
+		halbtc8822b1ant_run_coexist_mechanism(btcoexist);
+
+	} else {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			"[BTCoex], ********** (switchband_notify BTC_SWITCH_TO_2G) **********\n");
+		BTC_TRACE(trace_buf);
+
+		ex_halbtc8822b1ant_scan_notify(btcoexist,
+					       BTC_SCAN_START_2G);
+	}
+
+}
+
+
+void ex_halbtc8822b1ant_switchband_notify_without_bt(IN struct btc_coexist
+		*btcoexist,
+		IN u8 type)
+{
+	boolean wifi_under_5g = false;
+
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_5G, &wifi_under_5g);
+
+	if (type == BTC_SWITCH_TO_5G) {
+
+		btcoexist->btc_write_1byte_bitmask(btcoexist, 0xcbd,
+						   0x3, 1);
+		return;
+	} else if (type == BTC_SWITCH_TO_24G_NOFORSCAN) {
+
+		if (wifi_under_5g)
+
+			btcoexist->btc_write_1byte_bitmask(btcoexist, 0xcbd,
+							   0x3, 1);
+
+		else
+			btcoexist->btc_write_1byte_bitmask(btcoexist,
+							   0xcbd, 0x3, 2);
+	} else {
+
+		ex_halbtc8822b1ant_scan_notify_without_bt(btcoexist,
+				BTC_SCAN_START_2G);
+	}
+
+}
+
+void ex_halbtc8822b1ant_connect_notify(IN struct btc_coexist *btcoexist,
+				       IN u8 type)
+{
+	boolean	wifi_connected = false;
+
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+		    "[BTCoex], ********** (connect notify) **********\n");
+	BTC_TRACE(trace_buf);
+
+	halbtc8822b1ant_post_state_to_bt(btcoexist,
+					 BT_8822B_1ANT_SCOREBOARD_SCAN, true);
+
+	if (btcoexist->manual_control ||
+	    btcoexist->stop_coex_dm)
+		return;
+
+
+	if ((BTC_ASSOCIATE_5G_START == type) ||
+	    (BTC_ASSOCIATE_5G_FINISH == type)) {
+
+		if (BTC_ASSOCIATE_5G_START == type) {
+
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				"[BTCoex], ********** (5G associate start notify) **********\n");
+			BTC_TRACE(trace_buf);
+
+			halbtc8822b1ant_action_wifi_under5g(btcoexist);
+
+		} else if (BTC_ASSOCIATE_5G_FINISH == type) {
+
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				"[BTCoex], ********** (5G associate finish notify) **********\n");
+			BTC_TRACE(trace_buf);
+
+		}
+
+		return;
+
+	}
+
+
+	if (BTC_ASSOCIATE_START == type) {
+
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], 2G CONNECT START notify\n");
+		BTC_TRACE(trace_buf);
+
+		coex_sta->wifi_is_high_pri_task = true;
+
+		halbtc8822b1ant_set_ant_path(btcoexist,
+					     BTC_ANT_PATH_AUTO,
+					     FORCE_EXEC,
+					     BT_8822B_1ANT_PHASE_2G_RUNTIME);
+
+		coex_dm->arp_cnt = 0;
+
+		halbtc8822b1ant_action_wifi_not_connected_asso_auth(btcoexist);
+
+	} else {
+
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], 2G CONNECT Finish notify\n");
+		BTC_TRACE(trace_buf);
+		coex_sta->wifi_is_high_pri_task = false;
+
+		btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED,
+				   &wifi_connected);
+
+		if (!wifi_connected) /* non-connected scan */
+			halbtc8822b1ant_action_wifi_not_connected(btcoexist);
+		else
+			halbtc8822b1ant_action_wifi_connected(btcoexist);
+	}
+
+}
+
+void ex_halbtc8822b1ant_media_status_notify(IN struct btc_coexist *btcoexist,
+		IN u8 type)
+{
+	boolean			wifi_under_b_mode = false;
+	boolean wifi_under_5g = false;
+	u32			cnt_bt_cal_chk = 0;
+	boolean			is_in_mp_mode = false;
+	u8			u8tmp = 0;
+	u32			u32tmp1 = 0, u32tmp2 = 0;
+
+
+	if (btcoexist->manual_control ||
+	    btcoexist->stop_coex_dm)
+		return;
+
+
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_5G, &wifi_under_5g);
+
+
+
+
+	if (BTC_MEDIA_CONNECT == type) {
+
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], 2g media connect notify");
+		BTC_TRACE(trace_buf);
+
+		halbtc8822b1ant_post_state_to_bt(btcoexist,
+					 BT_8822B_1ANT_SCOREBOARD_ACTIVE, true);
+
+		if (wifi_under_5g) {
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				    "[BTCoex], 5g media notify\n");
+BTC_TRACE(trace_buf);
+
+			halbtc8822b1ant_action_wifi_under5g(btcoexist);
+			return;
+		}
+		/* Force antenna setup for no scan result issue */
+		halbtc8822b1ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO,
+					     FORCE_EXEC,
+					     BT_8822B_1ANT_PHASE_2G_RUNTIME);
+
+		btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_B_MODE,
+				   &wifi_under_b_mode);
+
+		/* Set CCK Tx/Rx high Pri except 11b mode */
+		if (wifi_under_b_mode) {
+
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				"[BTCoex], ********** (media status notity under b mode) **********\n");
+			BTC_TRACE(trace_buf);
+			btcoexist->btc_write_1byte(btcoexist, 0x6cd,
+						   0x00); /* CCK Tx */
+			btcoexist->btc_write_1byte(btcoexist, 0x6cf,
+						   0x00); /* CCK Rx */
+		} else {
+			/* btcoexist->btc_write_1byte(btcoexist, 0x6cd, 0x10); */ /*CCK Tx */
+			/* btcoexist->btc_write_1byte(btcoexist, 0x6cf, 0x10); */ /*CCK Rx */
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				"[BTCoex], ********** (media status notity not under b mode) **********\n");
+			BTC_TRACE(trace_buf);
+			btcoexist->btc_write_1byte(btcoexist, 0x6cd,
+						   0x00); /* CCK Tx */
+			btcoexist->btc_write_1byte(btcoexist, 0x6cf,
+						   0x10); /* CCK Rx */
+		}
+
+		coex_dm->backup_arfr_cnt1 = btcoexist->btc_read_4byte(btcoexist,
+					    0x430);
+		coex_dm->backup_arfr_cnt2 = btcoexist->btc_read_4byte(btcoexist,
+					    0x434);
+		coex_dm->backup_retry_limit = btcoexist->btc_read_2byte(
+						      btcoexist, 0x42a);
+		coex_dm->backup_ampdu_max_time = btcoexist->btc_read_1byte(
+				btcoexist, 0x456);
+	} else {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], 2g media disconnect notify\n");
+		BTC_TRACE(trace_buf);
+		coex_dm->arp_cnt = 0;
+
+		halbtc8822b1ant_post_state_to_bt(btcoexist,
+				 BT_8822B_1ANT_SCOREBOARD_ACTIVE, false);
+
+		btcoexist->btc_write_1byte(btcoexist, 0x6cd, 0x0); /* CCK Tx */
+		btcoexist->btc_write_1byte(btcoexist, 0x6cf, 0x0); /* CCK Rx */
+
+		coex_sta->cck_ever_lock = false;
+	}
+
+	halbtc8822b1ant_update_wifi_channel_info(btcoexist, type);
+
+}
+
+void ex_halbtc8822b1ant_specific_packet_notify(IN struct btc_coexist *btcoexist,
+		IN u8 type)
+{
+	boolean	under_4way = false, wifi_under_5g = false;
+
+	if (btcoexist->manual_control ||
+	    btcoexist->stop_coex_dm)
+		return;
+
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_5G, &wifi_under_5g);
+	if (wifi_under_5g) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], 5g special packet notify\n");
+		BTC_TRACE(trace_buf);
+
+		halbtc8822b1ant_action_wifi_under5g(btcoexist);
+		return;
+	}
+
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_4_WAY_PROGRESS,
+			   &under_4way);
+
+	if (under_4way) {
+
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], specific Packet ---- under_4way!!\n");
+		BTC_TRACE(trace_buf);
+
+		coex_sta->wifi_is_high_pri_task = true;
+		coex_sta->specific_pkt_period_cnt = 2;
+	} else if (BTC_PACKET_ARP == type) {
+
+		coex_dm->arp_cnt++;
+
+		if (coex_sta->wifi_is_high_pri_task) {
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				"[BTCoex], specific Packet ARP notify -cnt = %d\n",
+				    coex_dm->arp_cnt);
+			BTC_TRACE(trace_buf);
+		}
+
+	} else {
+
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			"[BTCoex], specific Packet DHCP or EAPOL notify [Type = %d]\n",
+			    type);
+		BTC_TRACE(trace_buf);
+
+		coex_sta->wifi_is_high_pri_task = true;
+		coex_sta->specific_pkt_period_cnt = 2;
+	}
+
+	if (coex_sta->wifi_is_high_pri_task)
+		halbtc8822b1ant_action_wifi_connected_specific_packet(
+			btcoexist);
+
+}
+
+void ex_halbtc8822b1ant_bt_info_notify(IN struct btc_coexist *btcoexist,
+				       IN u8 *tmp_buf, IN u8 length)
+{
+	u8				bt_info = 0;
+	u8				i, rsp_source = 0;
+	boolean				bt_busy = false;
+	boolean				wifi_connected = false;
+	boolean wifi_under_5g = false;
+
+
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_5G, &wifi_under_5g);
+
+	coex_sta->c2h_bt_info_req_sent = false;
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+		    "[BTCoex], ********** (BtInfo Notify) **********\n");
+	BTC_TRACE(trace_buf);
+
+	rsp_source = tmp_buf[0] & 0xf;
+	if (rsp_source >= BT_INFO_SRC_8822B_1ANT_MAX)
+		rsp_source = BT_INFO_SRC_8822B_1ANT_WIFI_FW;
+	coex_sta->bt_info_c2h_cnt[rsp_source]++;
+
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+		    "[BTCoex], Bt info[%d], length=%d, hex data=[", rsp_source,
+		    length);
+	BTC_TRACE(trace_buf);
+
+	for (i = 0; i < length; i++) {
+		coex_sta->bt_info_c2h[rsp_source][i] = tmp_buf[i];
+		if (i == 1)
+			bt_info = tmp_buf[i];
+		if (i == length - 1) {
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "0x%02x]\n",
+				    tmp_buf[i]);
+			BTC_TRACE(trace_buf);
+		} else {
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "0x%02x, ",
+				    tmp_buf[i]);
+			BTC_TRACE(trace_buf);
+		}
+	}
+
+
+	if (BT_INFO_SRC_8822B_1ANT_WIFI_FW != rsp_source) {
+
+		/* if 0xff, it means BT is under WHCK test */
+		if (bt_info == 0xff)
+			coex_sta->bt_whck_test = true;
+		else
+			coex_sta->bt_whck_test = false;
+
+		coex_sta->bt_retry_cnt =	/* [3:0] */
+			coex_sta->bt_info_c2h[rsp_source][2] & 0xf;
+
+		if (coex_sta->bt_retry_cnt >= 1)
+			coex_sta->pop_event_cnt++;
+
+		if (coex_sta->bt_info_c2h[rsp_source][2] & 0x20)
+			coex_sta->c2h_bt_page = true;
+		else
+			coex_sta->c2h_bt_page = false;
+
+		if (coex_sta->bt_info_c2h[rsp_source][2] & 0x80)
+			coex_sta->bt_create_connection = true;
+		else
+			coex_sta->bt_create_connection = false;
+
+		/* unit: %, value-100 to translate to unit: dBm */
+		coex_sta->bt_rssi = coex_sta->bt_info_c2h[rsp_source][3] * 2 +
+				    10;
+
+		/* coex_sta->bt_info_c2h[rsp_source][3] * 2 - 90; */
+
+		if ((coex_sta->bt_info_c2h[rsp_source][1] & 0x49) == 0x49) {
+			coex_sta->a2dp_bit_pool =
+				coex_sta->bt_info_c2h[rsp_source][6];
+		} else
+			coex_sta->a2dp_bit_pool = 0;
+
+		if (coex_sta->bt_info_c2h[rsp_source][1] & 0x9)
+			coex_sta->acl_busy = true;
+		else
+			coex_sta->acl_busy = false;
+
+		coex_sta->bt_info_ext =
+			coex_sta->bt_info_c2h[rsp_source][4];
+
+		/* Here we need to resend some wifi info to BT */
+		/* because bt is reset and loss of the info. */
+
+		if ((!btcoexist->manual_control) &&
+		    (!btcoexist->stop_coex_dm)) {
+
+			/*	Re-Init */
+			if (coex_sta->bt_info_ext & BIT(1)) {
+				BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+					"[BTCoex], BT ext info bit1 check, send wifi BW&Chnl to BT!!\n");
+				BTC_TRACE(trace_buf);
+				btcoexist->btc_get(btcoexist,
+						   BTC_GET_BL_WIFI_CONNECTED,
+						   &wifi_connected);
+				if (wifi_connected)
+					halbtc8822b1ant_update_wifi_channel_info(
+						btcoexist,
+						BTC_MEDIA_CONNECT);
+				else
+					halbtc8822b1ant_update_wifi_channel_info(
+						btcoexist,
+						BTC_MEDIA_DISCONNECT);
+			}
+
+			/*	If Ignore_WLanAct && not SetUp_Link */
+			if ((coex_sta->bt_info_ext & BIT(3)) &&
+			    (!(coex_sta->bt_info_ext & BIT(2)))) {
+
+				BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+					"[BTCoex], BT ext info bit3 check, set BT NOT to ignore Wlan active!!\n");
+				BTC_TRACE(trace_buf);
+				halbtc8822b1ant_ignore_wlan_act(btcoexist,
+								FORCE_EXEC,
+								false);
+			}
+		}
+		/* check BIT2 first ==> check if bt is under inquiry or page scan */
+		if (bt_info & BT_INFO_8822B_1ANT_B_INQ_PAGE)
+			coex_sta->c2h_bt_inquiry_page = true;
+		else
+			coex_sta->c2h_bt_inquiry_page = false;
+	}
+
+	coex_sta->num_of_profile = 0;
+
+	/* set link exist status */
+	if (!(bt_info & BT_INFO_8822B_1ANT_B_CONNECTION)) {
+		coex_sta->bt_link_exist = false;
+		coex_sta->pan_exist = false;
+		coex_sta->a2dp_exist = false;
+		coex_sta->hid_exist = false;
+		coex_sta->sco_exist = false;
+
+		coex_sta->bt_hi_pri_link_exist = false;
+	} else {	/* connection exists */
+		coex_sta->bt_link_exist = true;
+		if (bt_info & BT_INFO_8822B_1ANT_B_FTP) {
+			coex_sta->pan_exist = true;
+			coex_sta->num_of_profile++;
+		} else
+			coex_sta->pan_exist = false;
+		if (bt_info & BT_INFO_8822B_1ANT_B_A2DP) {
+			coex_sta->a2dp_exist = true;
+			coex_sta->num_of_profile++;
+		} else
+			coex_sta->a2dp_exist = false;
+		if (bt_info & BT_INFO_8822B_1ANT_B_HID) {
+			coex_sta->hid_exist = true;
+			coex_sta->num_of_profile++;
+		} else
+			coex_sta->hid_exist = false;
+		if (bt_info & BT_INFO_8822B_1ANT_B_SCO_ESCO) {
+			coex_sta->sco_exist = true;
+			coex_sta->num_of_profile++;
+		} else
+			coex_sta->sco_exist = false;
+
+	}
+
+	halbtc8822b1ant_update_bt_link_info(btcoexist);
+
+	bt_info = bt_info &
+		0x1f;  /* mask profile bit for connect-ilde identification ( for CSR case: A2DP idle --> 0x41) */
+
+	if (!(bt_info & BT_INFO_8822B_1ANT_B_CONNECTION)) {
+		coex_dm->bt_status = BT_8822B_1ANT_BT_STATUS_NON_CONNECTED_IDLE;
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			"[BTCoex], BtInfoNotify(), BT Non-Connected idle!!!\n");
+		BTC_TRACE(trace_buf);
+	} else if (bt_info ==
+		BT_INFO_8822B_1ANT_B_CONNECTION) {	/* connection exists but no busy */
+		coex_dm->bt_status = BT_8822B_1ANT_BT_STATUS_CONNECTED_IDLE;
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], BtInfoNotify(), BT Connected-idle!!!\n");
+		BTC_TRACE(trace_buf);
+	} else if ((bt_info & BT_INFO_8822B_1ANT_B_SCO_ESCO) ||
+		   (bt_info & BT_INFO_8822B_1ANT_B_SCO_BUSY)) {
+		coex_dm->bt_status = BT_8822B_1ANT_BT_STATUS_SCO_BUSY;
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], BtInfoNotify(), BT SCO busy!!!\n");
+		BTC_TRACE(trace_buf);
+	} else if (bt_info & BT_INFO_8822B_1ANT_B_ACL_BUSY) {
+		if (BT_8822B_1ANT_BT_STATUS_ACL_BUSY != coex_dm->bt_status)
+			coex_dm->bt_status = BT_8822B_1ANT_BT_STATUS_ACL_BUSY;
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], BtInfoNotify(), BT ACL busy!!!\n");
+		BTC_TRACE(trace_buf);
+	} else {
+		coex_dm->bt_status = BT_8822B_1ANT_BT_STATUS_MAX;
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			"[BTCoex], BtInfoNotify(), BT Non-Defined state!!!\n");
+		BTC_TRACE(trace_buf);
+	}
+
+	if ((BT_8822B_1ANT_BT_STATUS_ACL_BUSY == coex_dm->bt_status) ||
+	    (BT_8822B_1ANT_BT_STATUS_SCO_BUSY == coex_dm->bt_status) ||
+	    (BT_8822B_1ANT_BT_STATUS_ACL_SCO_BUSY == coex_dm->bt_status))
+		bt_busy = true;
+	else
+		bt_busy = false;
+
+	btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_TRAFFIC_BUSY, &bt_busy);
+
+	halbtc8822b1ant_run_coexist_mechanism(btcoexist);
+}
+
+void ex_halbtc8822b1ant_rf_status_notify(IN struct btc_coexist *btcoexist,
+		IN u8 type)
+{
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], RF Status notify\n");
+	BTC_TRACE(trace_buf);
+
+	if (BTC_RF_ON == type) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], RF is turned ON!!\n");
+		BTC_TRACE(trace_buf);
+		btcoexist->stop_coex_dm = false;
+
+		halbtc8822b1ant_post_state_to_bt(btcoexist,
+					 BT_8822B_1ANT_SCOREBOARD_ACTIVE, true);
+		halbtc8822b1ant_post_state_to_bt(btcoexist,
+					 BT_8822B_1ANT_SCOREBOARD_ONOFF, true);
+
+	} else if (BTC_RF_OFF == type) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], RF is turned OFF!!\n");
+		BTC_TRACE(trace_buf);
+
+		halbtc8822b1ant_post_state_to_bt(btcoexist,
+				 BT_8822B_1ANT_SCOREBOARD_ACTIVE, false);
+		halbtc8822b1ant_post_state_to_bt(btcoexist,
+					 BT_8822B_1ANT_SCOREBOARD_ONOFF, false);
+		halbtc8822b1ant_ps_tdma(btcoexist, FORCE_EXEC, false, 0);
+
+		halbtc8822b1ant_set_ant_path(btcoexist,
+					     BTC_ANT_PATH_AUTO,
+					     FORCE_EXEC,
+					     BT_8822B_1ANT_PHASE_WLAN_OFF);
+		/* for test : s3 bt disppear , fail rate 1/600*/
+
+		halbtc8822b1ant_ignore_wlan_act(btcoexist, FORCE_EXEC, true);
+
+		btcoexist->stop_coex_dm = true;
+	}
+}
+
+void ex_halbtc8822b1ant_halt_notify(IN struct btc_coexist *btcoexist)
+{
+
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], Halt notify\n");
+	BTC_TRACE(trace_buf);
+
+	halbtc8822b1ant_post_state_to_bt(btcoexist,
+				 BT_8822B_1ANT_SCOREBOARD_ACTIVE, false);
+	halbtc8822b1ant_post_state_to_bt(btcoexist,
+					 BT_8822B_1ANT_SCOREBOARD_ONOFF, false);
+
+	halbtc8822b1ant_ps_tdma(btcoexist, FORCE_EXEC, false, 0);
+
+	halbtc8822b1ant_set_ant_path(btcoexist,
+				     BTC_ANT_PATH_AUTO,
+				     FORCE_EXEC,
+				     BT_8822B_1ANT_PHASE_WLAN_OFF);
+	/* for test : s3 bt disppear , fail rate 1/600*/
+
+	halbtc8822b1ant_ignore_wlan_act(btcoexist, FORCE_EXEC, true);
+
+	ex_halbtc8822b1ant_media_status_notify(btcoexist, BTC_MEDIA_DISCONNECT);
+
+	halbtc8822b1ant_enable_gnt_to_gpio(btcoexist, false);
+
+	btcoexist->stop_coex_dm = true;
+}
+
+
+void ex_halbtc8822b1ant_pnp_notify(IN struct btc_coexist *btcoexist,
+				   IN u8 pnp_state)
+{
+	boolean wifi_under_5g = false;
+
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], Pnp notify\n");
+	BTC_TRACE(trace_buf);
+
+btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_5G, &wifi_under_5g);
+	if (BTC_WIFI_PNP_SLEEP == pnp_state) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], Pnp notify to SLEEP\n");
+		BTC_TRACE(trace_buf);
+
+		halbtc8822b1ant_post_state_to_bt(btcoexist,
+				 BT_8822B_1ANT_SCOREBOARD_ACTIVE, false);
+		halbtc8822b1ant_post_state_to_bt(btcoexist,
+					 BT_8822B_1ANT_SCOREBOARD_ONOFF, false);
+		/*
+				halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 0);
+
+				halbtc8822b1ant_set_ant_path(btcoexist,
+									BTC_ANT_PATH_AUTO,
+								FORCE_EXEC,
+								BT_8822B_1ANT_PHASE_WLAN_OFF);
+
+				halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC,
+								     5);
+
+				halbtc8822b1ant_enable_gnt_to_gpio(btcoexist, false);
+		*/
+		btcoexist->stop_coex_dm = true;
+	} else if (BTC_WIFI_PNP_WAKE_UP == pnp_state) {
+		/*pnp_wake_cnt++;*/
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], Pnp notify to WAKE UP\n");
+		BTC_TRACE(trace_buf);
+
+		halbtc8822b1ant_post_state_to_bt(btcoexist,
+					 BT_8822B_1ANT_SCOREBOARD_ACTIVE, true);
+		halbtc8822b1ant_post_state_to_bt(btcoexist,
+					 BT_8822B_1ANT_SCOREBOARD_ONOFF, true);
+
+		btcoexist->stop_coex_dm = false;
+	}
+}
+
+void ex_halbtc8822b1ant_coex_dm_reset(IN struct btc_coexist *btcoexist)
+{
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+		"[BTCoex], *****************Coex DM Reset*****************\n");
+	BTC_TRACE(trace_buf);
+
+	halbtc8822b1ant_init_hw_config(btcoexist, false, false);
+	halbtc8822b1ant_init_coex_dm(btcoexist);
+}
+
+void ex_halbtc8822b1ant_periodical(IN struct btc_coexist *btcoexist)
+{
+
+	struct  btc_board_info	*board_info = &btcoexist->board_info;
+	boolean wifi_busy = false;
+	u16 bt_scoreboard_val = 0;
+	u32 bt_patch_ver;
+	static u8 cnt = 0;
+	boolean bt_relink_finish = false;
+	boolean rf4ce_connected = false;
+
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+		"[BTCoex], ==========================Periodical===========================\n");
+	BTC_TRACE(trace_buf);
+
+#if (BT_AUTO_REPORT_ONLY_8822B_1ANT == 0)
+	halbtc8822b1ant_query_bt_info(btcoexist);
+#endif
+
+	halbtc8822b1ant_monitor_bt_ctr(btcoexist);
+	halbtc8822b1ant_monitor_wifi_ctr(btcoexist);
+
+	halbtc8822b1ant_monitor_bt_enable_disable(btcoexist);
+
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy);
+	halbtc8822b1ant_read_score_board(btcoexist, &bt_scoreboard_val);
+
+	/*RF4CE for arris , rf4ce always on*/
+	/*
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_RF4CE_CONNECTED, &rf4ce_connected);
+	if (rf4ce_connected){
+		btcoexist->btc_write_1byte_bitmask(
+					btcoexist, 0x45e, 0x8, 0x1);
+
+				halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC,
+							true,
+							50);
+
+				halbtc8822b1ant_coex_table_with_type(btcoexist,
+				NORMAL_EXEC, 1);
+				return;
+		}
+		*/
+
+	if (wifi_busy) {
+		/*WL scoreboard to BT,BT see WL Ccoreboard bit[6]=1 WL BUSY*/
+		halbtc8822b1ant_post_state_to_bt(btcoexist,
+			BT_8822B_1ANT_SCOREBOARD_WLBUSY, true);
+		/*BT scoreboard to WL  , let WL see BT scoreboard bit[6]=1*/
+		if (bt_scoreboard_val & BIT(6))
+			/*btcoexist->btc_set_bt_wake(btcoexist, 45, 1);*/
+			halbtc8822b1ant_query_bt_info(btcoexist);
+	} else {
+		halbtc8822b1ant_post_state_to_bt(btcoexist,
+			BT_8822B_1ANT_SCOREBOARD_WLBUSY, false);
+	}
+
+	/* for 4-way, DHCP, EAPOL packet */
+	if (coex_sta->specific_pkt_period_cnt > 0) {
+
+		coex_sta->specific_pkt_period_cnt--;
+
+		if ((coex_sta->specific_pkt_period_cnt == 0) &&
+		    (coex_sta->wifi_is_high_pri_task))
+			coex_sta->wifi_is_high_pri_task = false;
+
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			"[BTCoex], ***************** Hi-Pri Task = %s*****************\n",
+			    (coex_sta->wifi_is_high_pri_task ? "Yes" :
+			     "No"));
+		BTC_TRACE(trace_buf);
+	}
+
+	if (!coex_sta->bt_disabled) {
+		if (coex_sta->bt_coex_supported_feature == 0)
+			btcoexist->btc_get(btcoexist, BTC_GET_U4_SUPPORTED_FEATURE, &coex_sta->bt_coex_supported_feature);
+
+		if ((coex_sta->bt_coex_supported_version == 0) ||
+			(coex_sta->bt_coex_supported_version == 0xffff))
+			btcoexist->btc_get(btcoexist, BTC_GET_U4_SUPPORTED_VERSION, &coex_sta->bt_coex_supported_version);
+
+		btcoexist->btc_get(btcoexist, BTC_GET_U4_BT_PATCH_VER, &bt_patch_ver);
+		btcoexist->bt_info.bt_get_fw_ver = bt_patch_ver;
+
+		if (halbtc8822b1ant_is_wifi_status_changed(btcoexist))
+			halbtc8822b1ant_run_coexist_mechanism(btcoexist);
+
+	}
+}
+
+void ex_halbtc8822b1ant_antenna_detection(IN struct btc_coexist *btcoexist,
+		IN u32 cent_freq, IN u32 offset, IN u32 span, IN u32 seconds)
+{
+}
+
+void ex_halbtc8822b1ant_antenna_isolation(IN struct btc_coexist *btcoexist,
+		IN u32 cent_freq, IN u32 offset, IN u32 span, IN u32 seconds)
+{
+
+
+}
+
+void ex_halbtc8822b1ant_psd_scan(IN struct btc_coexist *btcoexist,
+		 IN u32 cent_freq, IN u32 offset, IN u32 span, IN u32 seconds)
+{
+
+
+}
+
+void ex_halbtc8822b1ant_display_ant_detection(IN struct btc_coexist *btcoexist)
+{
+
+}
+
+void ex_halbtc8822b1ant_dbg_control(IN struct btc_coexist *btcoexist,
+				    IN u8 op_code, IN u8 op_len, IN u8 *pdata)
+{}
+#endif	/*  #if(BTC_COEX_OFFLOAD == 1) */
+
+#endif
+
+#else
+
+void ex_halbtc8822b1ant_switch_band_without_bt(IN struct btc_coexist *btcoexist,
+		IN boolean wifi_only_5g)
+{
+	/* ant switch WL2G or WL5G*/
+	if (wifi_only_5g)
+
+		btcoexist->btc_write_1byte_bitmask(btcoexist, 0xcbd, 0x3, 1);
+
+	else
+
+		btcoexist->btc_write_1byte_bitmask(btcoexist, 0xcbd, 0x3, 2);
+
+}
+
+void ex_halbtc8822b1ant_init_hw_config_without_bt(IN struct btc_coexist
+		*btcoexist)
+{
+	/* enable GNT_WL */
+
+	btcoexist->btc_write_1byte_bitmask(btcoexist, 0x67, 0x1,
+					   0x0);
+
+	/* Antenna config */
+	btcoexist->btc_write_1byte_bitmask(btcoexist, 0x4e,
+					   0x80, 0x0);  /*  0x4c[23] = 0 */
+	btcoexist->btc_write_1byte_bitmask(btcoexist, 0x4f,
+					   0x01, 0x1);  /* 0x4c[24] = 1 */
+	btcoexist->btc_write_1byte_bitmask(btcoexist, 0xcb4,
+		0xff, 0x77);	/* BB SW, DPDT use RFE_ctrl8 and RFE_ctrl9 as conctrol pin */
+
+
+	/* Ext switch buffer mux */
+	btcoexist->btc_write_1byte(btcoexist, 0x974, 0xff);
+	btcoexist->btc_write_1byte_bitmask(btcoexist, 0x1991,
+					   0x3, 0x0);
+	btcoexist->btc_write_1byte_bitmask(btcoexist, 0xcbe,
+					   0x8, 0x0);
+
+	/*enable sw control gnt_wl=1 / gnt_bt=1 */
+	btcoexist->btc_write_1byte(btcoexist, 0x73, 0x0e);
+
+	btcoexist->btc_write_4byte(btcoexist, 0x1704,
+				   0x0000ff00);
+
+	btcoexist->btc_write_4byte(btcoexist, 0x1700,
+				   0xc00f0038);
+}
+
+#endif	/* #if (BT_SUPPORT == 1 && COEX_SUPPORT == 1) */
+
+
+
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/btc/halbtc8822b1ant.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/btc/halbtc8822b1ant.h
--- linux-5.6.3/3rdparty/rtl8821ce/hal/btc/halbtc8822b1ant.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/btc/halbtc8822b1ant.h	2020-04-10 16:35:06.786658667 +0300
@@ -0,0 +1,434 @@
+
+#if (BT_SUPPORT == 1 && COEX_SUPPORT == 1)
+
+#if (RTL8822B_SUPPORT == 1)
+
+/* *******************************************
+ * The following is for 8822B 1ANT BT Co-exist definition
+ * ******************************************* */
+#define	BT_AUTO_REPORT_ONLY_8822B_1ANT				1
+
+#define	BT_INFO_8822B_1ANT_B_FTP						BIT(7)
+#define	BT_INFO_8822B_1ANT_B_A2DP					BIT(6)
+#define	BT_INFO_8822B_1ANT_B_HID						BIT(5)
+#define	BT_INFO_8822B_1ANT_B_SCO_BUSY				BIT(4)
+#define	BT_INFO_8822B_1ANT_B_ACL_BUSY				BIT(3)
+#define	BT_INFO_8822B_1ANT_B_INQ_PAGE				BIT(2)
+#define	BT_INFO_8822B_1ANT_B_SCO_ESCO				BIT(1)
+#define	BT_INFO_8822B_1ANT_B_CONNECTION				BIT(0)
+
+#define	BT_INFO_8822B_1ANT_A2DP_BASIC_RATE(_BT_INFO_EXT_)	\
+		(((_BT_INFO_EXT_&BIT(0))) ? true : false)
+
+#define	BTC_RSSI_COEX_THRESH_TOL_8822B_1ANT		2
+
+#define  BT_8822B_1ANT_WIFI_NOISY_THRESH							150  /* max: 255 */
+
+/* for Antenna detection */
+#define	BT_8822B_1ANT_ANTDET_PSDTHRES_BACKGROUND					50
+#define	BT_8822B_1ANT_ANTDET_PSDTHRES_2ANT_BADISOLATION				70
+#define	BT_8822B_1ANT_ANTDET_PSDTHRES_2ANT_GOODISOLATION			55
+#define	BT_8822B_1ANT_ANTDET_PSDTHRES_1ANT							35
+#define	BT_8822B_1ANT_ANTDET_RETRY_INTERVAL							10	/* retry timer if ant det is fail, unit: second */
+#define	BT_8822B_1ANT_ANTDET_ENABLE									0
+#define	BT_8822B_1ANT_ANTDET_COEXMECHANISMSWITCH_ENABLE				0
+
+#define	BT_8822B_1ANT_LTECOEX_INDIRECTREG_ACCESS_TIMEOUT		30000
+
+
+
+enum bt_8822b_1ant_signal_state {
+	BT_8822B_1ANT_SIG_STA_SET_TO_LOW		= 0x0,
+	BT_8822B_1ANT_SIG_STA_SET_BY_HW		= 0x0,
+	BT_8822B_1ANT_SIG_STA_SET_TO_HIGH		= 0x1,
+	BT_8822B_1ANT_SIG_STA_MAX
+};
+
+enum bt_8822b_1ant_path_ctrl_owner {
+	BT_8822B_1ANT_PCO_BTSIDE		= 0x0,
+	BT_8822B_1ANT_PCO_WLSIDE	= 0x1,
+	BT_8822B_1ANT_PCO_MAX
+};
+
+enum bt_8822b_1ant_gnt_ctrl_type {
+	BT_8822B_1ANT_GNT_CTRL_BY_PTA		= 0x0,
+	BT_8822B_1ANT_GNT_CTRL_BY_SW		= 0x1,
+	BT_8822B_1ANT_GNT_CTRL_MAX
+};
+
+enum bt_8822b_1ant_gnt_ctrl_block {
+	BT_8822B_1ANT_GNT_BLOCK_RFC_BB		= 0x0,
+	BT_8822B_1ANT_GNT_BLOCK_RFC			= 0x1,
+	BT_8822B_1ANT_GNT_BLOCK_BB			= 0x2,
+	BT_8822B_1ANT_GNT_BLOCK_MAX
+};
+
+enum bt_8822b_1ant_lte_coex_table_type {
+	BT_8822B_1ANT_CTT_WL_VS_LTE			= 0x0,
+	BT_8822B_1ANT_CTT_BT_VS_LTE			= 0x1,
+	BT_8822B_1ANT_CTT_MAX
+};
+
+enum bt_8822b_1ant_lte_break_table_type {
+	BT_8822B_1ANT_LBTT_WL_BREAK_LTE			= 0x0,
+	BT_8822B_1ANT_LBTT_BT_BREAK_LTE				= 0x1,
+	BT_8822B_1ANT_LBTT_LTE_BREAK_WL			= 0x2,
+	BT_8822B_1ANT_LBTT_LTE_BREAK_BT				= 0x3,
+	BT_8822B_1ANT_LBTT_MAX
+};
+
+enum bt_info_src_8822b_1ant {
+	BT_INFO_SRC_8822B_1ANT_WIFI_FW			= 0x0,
+	BT_INFO_SRC_8822B_1ANT_BT_RSP				= 0x1,
+	BT_INFO_SRC_8822B_1ANT_BT_ACTIVE_SEND		= 0x2,
+	BT_INFO_SRC_8822B_1ANT_MAX
+};
+
+enum bt_8822b_1ant_bt_status {
+	BT_8822B_1ANT_BT_STATUS_NON_CONNECTED_IDLE	= 0x0,
+	BT_8822B_1ANT_BT_STATUS_CONNECTED_IDLE		= 0x1,
+	BT_8822B_1ANT_BT_STATUS_INQ_PAGE				= 0x2,
+	BT_8822B_1ANT_BT_STATUS_ACL_BUSY				= 0x3,
+	BT_8822B_1ANT_BT_STATUS_SCO_BUSY				= 0x4,
+	BT_8822B_1ANT_BT_STATUS_ACL_SCO_BUSY			= 0x5,
+	BT_8822B_1ANT_BT_STATUS_MAX
+};
+
+enum bt_8822b_1ant_wifi_status {
+	BT_8822B_1ANT_WIFI_STATUS_NON_CONNECTED_IDLE				= 0x0,
+	BT_8822B_1ANT_WIFI_STATUS_NON_CONNECTED_ASSO_AUTH_SCAN		= 0x1,
+	BT_8822B_1ANT_WIFI_STATUS_CONNECTED_SCAN					= 0x2,
+	BT_8822B_1ANT_WIFI_STATUS_CONNECTED_SPECIFIC_PKT				= 0x3,
+	BT_8822B_1ANT_WIFI_STATUS_CONNECTED_IDLE					= 0x4,
+	BT_8822B_1ANT_WIFI_STATUS_CONNECTED_BUSY					= 0x5,
+	BT_8822B_1ANT_WIFI_STATUS_MAX
+};
+
+enum bt_8822b_1ant_coex_algo {
+	BT_8822B_1ANT_COEX_ALGO_UNDEFINED			= 0x0,
+	BT_8822B_1ANT_COEX_ALGO_SCO				= 0x1,
+	BT_8822B_1ANT_COEX_ALGO_HID				= 0x2,
+	BT_8822B_1ANT_COEX_ALGO_A2DP				= 0x3,
+	BT_8822B_1ANT_COEX_ALGO_A2DP_PANHS		= 0x4,
+	BT_8822B_1ANT_COEX_ALGO_PANEDR			= 0x5,
+	BT_8822B_1ANT_COEX_ALGO_PANHS			= 0x6,
+	BT_8822B_1ANT_COEX_ALGO_PANEDR_A2DP		= 0x7,
+	BT_8822B_1ANT_COEX_ALGO_PANEDR_HID		= 0x8,
+	BT_8822B_1ANT_COEX_ALGO_HID_A2DP_PANEDR	= 0x9,
+	BT_8822B_1ANT_COEX_ALGO_HID_A2DP			= 0xa,
+	BT_8822B_1ANT_COEX_ALGO_MAX				= 0xb,
+};
+
+enum bt_8822b_1ant_ext_ant_switch_type {
+	BT_8822B_1ANT_EXT_ANT_SWITCH_USE_SPDT		= 0x0,
+	BT_8822B_1ANT_EXT_ANT_SWITCH_USE_SP3T		= 0x1,
+	BT_8822B_1ANT_EXT_ANT_SWITCH_MAX
+};
+
+enum bt_8822b_1ant_ext_ant_switch_ctrl_type {
+	BT_8822B_1ANT_EXT_ANT_SWITCH_CTRL_BY_BBSW	= 0x0,
+	BT_8822B_1ANT_EXT_ANT_SWITCH_CTRL_BY_PTA	= 0x1,
+	BT_8822B_1ANT_EXT_ANT_SWITCH_CTRL_BY_ANTDIV	= 0x2,
+	BT_8822B_1ANT_EXT_ANT_SWITCH_CTRL_BY_MAC	= 0x3,
+	BT_8822B_1ANT_EXT_ANT_SWITCH_CTRL_BY_BT		= 0x4,
+	BT_8822B_1ANT_EXT_ANT_SWITCH_CTRL_MAX
+};
+
+enum bt_8822b_1ant_ext_ant_switch_pos_type {
+	BT_8822B_1ANT_EXT_ANT_SWITCH_TO_BT			= 0x0,
+	BT_8822B_1ANT_EXT_ANT_SWITCH_TO_WLG			= 0x1,
+	BT_8822B_1ANT_EXT_ANT_SWITCH_TO_WLA			= 0x2,
+	BT_8822B_1ANT_EXT_ANT_SWITCH_TO_NOCARE		= 0x3,
+	BT_8822B_1ANT_EXT_ANT_SWITCH_TO_MAX
+};
+
+enum bt_8822b_1ant_phase {
+	BT_8822B_1ANT_PHASE_COEX_INIT				= 0x0,
+	BT_8822B_1ANT_PHASE_WLANONLY_INIT			= 0x1,
+	BT_8822B_1ANT_PHASE_WLAN_OFF				= 0x2,
+	BT_8822B_1ANT_PHASE_2G_RUNTIME				= 0x3,
+	BT_8822B_1ANT_PHASE_5G_RUNTIME				= 0x4,
+	BT_8822B_1ANT_PHASE_BTMPMODE				= 0x5,
+	BT_8822B_1ANT_PHASE_MAX
+};
+
+/*ADD SCOREBOARD TO FIX BT LPS 32K ISSUE WHILE WL BUSY*/
+enum bt_8822b_1ant_Scoreboard {
+	BT_8822B_1ANT_SCOREBOARD_ACTIVE                            = BIT(0),
+	BT_8822B_1ANT_SCOREBOARD_ONOFF                             = BIT(1),
+	BT_8822B_1ANT_SCOREBOARD_SCAN                               = BIT(2),
+	BT_8822B_1ANT_SCOREBOARD_UNDERTEST							= BIT(3),
+	BT_8822B_1ANT_SCOREBOARD_WLBUSY                          = BIT(6)
+};
+
+struct coex_dm_8822b_1ant {
+	/* hw setting */
+	u32		pre_ant_pos_type;
+	u32		cur_ant_pos_type;
+	/* fw mechanism */
+	boolean		cur_ignore_wlan_act;
+	boolean		pre_ignore_wlan_act;
+	u8		pre_ps_tdma;
+	u8		cur_ps_tdma;
+	u8		ps_tdma_para[5];
+	u8		ps_tdma_du_adj_type;
+	boolean		auto_tdma_adjust;
+	boolean		pre_ps_tdma_on;
+	boolean		cur_ps_tdma_on;
+	boolean		pre_bt_auto_report;
+	boolean		cur_bt_auto_report;
+	u8		pre_lps;
+	u8		cur_lps;
+	u8		pre_rpwm;
+	u8		cur_rpwm;
+
+	/* sw mechanism */
+	boolean	pre_low_penalty_ra;
+	boolean		cur_low_penalty_ra;
+	u32		pre_val0x6c0;
+	u32		cur_val0x6c0;
+	u32		pre_val0x6c4;
+	u32		cur_val0x6c4;
+	u32		pre_val0x6c8;
+	u32		cur_val0x6c8;
+	u8		pre_val0x6cc;
+	u8		cur_val0x6cc;
+	boolean		limited_dig;
+
+	u32		backup_arfr_cnt1;	/* Auto Rate Fallback Retry cnt */
+	u32		backup_arfr_cnt2;	/* Auto Rate Fallback Retry cnt */
+	u16		backup_retry_limit;
+	u8		backup_ampdu_max_time;
+
+	/* algorithm related */
+	u8		pre_algorithm;
+	u8		cur_algorithm;
+	u8		bt_status;
+	u8		wifi_chnl_info[3];
+
+	u32		pre_ra_mask;
+	u32		cur_ra_mask;
+	u8		pre_arfr_type;
+	u8		cur_arfr_type;
+	u8		pre_retry_limit_type;
+	u8		cur_retry_limit_type;
+	u8		pre_ampdu_time_type;
+	u8		cur_ampdu_time_type;
+	u32		arp_cnt;
+
+	u32		pre_ext_ant_switch_status;
+	u32		cur_ext_ant_switch_status;
+
+	u8		error_condition;
+};
+
+struct coex_sta_8822b_1ant {
+	boolean					bt_disabled;
+	boolean					bt_link_exist;
+	boolean					sco_exist;
+	boolean					a2dp_exist;
+	boolean					hid_exist;
+	boolean					pan_exist;
+	boolean					bt_hi_pri_link_exist;
+	u8					num_of_profile;
+
+	boolean					under_lps;
+	boolean					under_ips;
+	u32					specific_pkt_period_cnt;
+	u32					high_priority_tx;
+	u32					high_priority_rx;
+	u32					low_priority_tx;
+	u32					low_priority_rx;
+	s8					bt_rssi;
+	boolean					bt_tx_rx_mask;
+	u8					pre_bt_rssi_state;
+	u8					pre_wifi_rssi_state[4];
+	boolean					c2h_bt_info_req_sent;
+	u8					bt_info_c2h[BT_INFO_SRC_8822B_1ANT_MAX][10];
+	u32					bt_info_c2h_cnt[BT_INFO_SRC_8822B_1ANT_MAX];
+	boolean					bt_whck_test;
+	boolean					c2h_bt_inquiry_page;
+	boolean					c2h_bt_page;				/* Add for win8.1 page out issue */
+	boolean					wifi_is_high_pri_task;		/* Add for win8.1 page out issue */
+	u8					bt_retry_cnt;
+	u8					bt_info_ext;
+	u32					pop_event_cnt;
+	u8					scan_ap_num;
+
+	u32					crc_ok_cck;
+	u32					crc_ok_11g;
+	u32					crc_ok_11n;
+	u32					crc_ok_11n_agg;
+	u32					crc_ok_11n_vht;
+
+	u32					crc_err_cck;
+	u32					crc_err_11g;
+	u32					crc_err_11n;
+	u32					crc_err_11n_agg;
+	u32					crc_err_11n_vht;
+
+	boolean					cck_lock;
+	boolean					pre_ccklock;
+	boolean					cck_ever_lock;
+	u8					coex_table_type;
+
+	boolean					force_lps_on;
+	u32					wrong_profile_notification;
+
+	boolean					concurrent_rx_mode_on;
+
+	u32					special_pkt_period_cnt;
+
+	u16					score_board;
+
+	u8					a2dp_bit_pool;
+	u8					cut_version;
+	boolean				acl_busy;
+	boolean				wl_rf_off_on_event;
+	boolean				bt_create_connection;
+	boolean				run_time_state;
+
+	u32					bt_coex_supported_feature;
+	u32					bt_coex_supported_version;
+	boolean                               rf4ce_enabled;
+};
+
+struct rfe_type_8822b_1ant {
+
+	u8			rfe_module_type;
+	boolean		ext_ant_switch_exist;
+	u8			ext_ant_switch_type;
+	u8			ext_ant_switch_ctrl_polarity;		/*  iF 0: ANTSW(rfe_sel9)=0, ANTSWB(rfe_sel8)=1 =>  Ant to BT/5G */
+};
+
+
+#define  BT_8822B_1ANT_ANTDET_PSD_POINTS			256	/* MAX:1024 */
+#define  BT_8822B_1ANT_ANTDET_PSD_AVGNUM			1	/* MAX:3 */
+#define	BT_8822B_1ANT_ANTDET_BUF_LEN				16
+
+struct psdscan_sta_8822b_1ant {
+
+	u32			ant_det_bt_le_channel;  /* BT LE Channel ex:2412 */
+	u32			ant_det_bt_tx_time;
+	u32			ant_det_pre_psdscan_peak_val;
+	boolean			ant_det_is_ant_det_available;
+	u32			ant_det_psd_scan_peak_val;
+	boolean			ant_det_is_btreply_available;
+	u32			ant_det_psd_scan_peak_freq;
+
+	u8			ant_det_result;
+	u8			ant_det_peak_val[BT_8822B_1ANT_ANTDET_BUF_LEN];
+	u8			ant_det_peak_freq[BT_8822B_1ANT_ANTDET_BUF_LEN];
+	u32			ant_det_try_count;
+	u32			ant_det_fail_count;
+	u32			ant_det_inteval_count;
+	u32			ant_det_thres_offset;
+
+	u32			real_cent_freq;
+	s32			real_offset;
+	u32			real_span;
+
+	u32			psd_band_width;  /* unit: Hz */
+	u32			psd_point;		/* 128/256/512/1024 */
+	u32			psd_report[1024];  /* unit:dB (20logx), 0~255 */
+	u32			psd_report_max_hold[1024];  /* unit:dB (20logx), 0~255 */
+	u32			psd_start_point;
+	u32			psd_stop_point;
+	u32			psd_max_value_point;
+	u32			psd_max_value;
+	u32			psd_start_base;
+	u32			psd_avg_num;	/* 1/8/16/32 */
+	u32			psd_gen_count;
+	boolean			is_psd_running;
+	boolean			is_psd_show_max_only;
+};
+
+/* *******************************************
+ * The following is interface which will notify coex module.
+ * ******************************************* */
+void ex_halbtc8822b1ant_power_on_setting(IN struct btc_coexist *btcoexist);
+void ex_halbtc8822b1ant_pre_load_firmware(IN struct btc_coexist *btcoexist);
+void ex_halbtc8822b1ant_init_hw_config(IN struct btc_coexist *btcoexist,
+				       IN boolean wifi_only);
+void ex_halbtc8822b1ant_init_coex_dm(IN struct btc_coexist *btcoexist);
+void ex_halbtc8822b1ant_ips_notify(IN struct btc_coexist *btcoexist,
+				   IN u8 type);
+void ex_halbtc8822b1ant_lps_notify(IN struct btc_coexist *btcoexist,
+				   IN u8 type);
+void ex_halbtc8822b1ant_scan_notify(IN struct btc_coexist *btcoexist,
+				    IN u8 type);
+void ex_halbtc8822b1ant_scan_notify_without_bt(IN struct btc_coexist *btcoexist,
+		IN u8 type);
+void ex_halbtc8822b1ant_switchband_notify(IN struct btc_coexist *btcoexist,
+		IN u8 type);
+void ex_halbtc8822b1ant_switchband_notify_without_bt(IN struct btc_coexist
+		*btcoexist,
+		IN u8 type);
+void ex_halbtc8822b1ant_connect_notify(IN struct btc_coexist *btcoexist,
+				       IN u8 type);
+void ex_halbtc8822b1ant_media_status_notify(IN struct btc_coexist *btcoexist,
+		IN u8 type);
+void ex_halbtc8822b1ant_specific_packet_notify(IN struct btc_coexist *btcoexist,
+		IN u8 type);
+void ex_halbtc8822b1ant_bt_info_notify(IN struct btc_coexist *btcoexist,
+				       IN u8 *tmp_buf, IN u8 length);
+void ex_halbtc8822b1ant_rf_status_notify(IN struct btc_coexist *btcoexist,
+		IN u8 type);
+void ex_halbtc8822b1ant_halt_notify(IN struct btc_coexist *btcoexist);
+void ex_halbtc8822b1ant_pnp_notify(IN struct btc_coexist *btcoexist,
+				   IN u8 pnp_state);
+void ex_halbtc8822b1ant_ScoreBoardStatusNotify(IN struct btc_coexist *btcoexist,
+		IN u8 *tmp_buf, IN u8 length);
+void ex_halbtc8822b1ant_coex_dm_reset(IN struct btc_coexist *btcoexist);
+void ex_halbtc8822b1ant_periodical(IN struct btc_coexist *btcoexist);
+void ex_halbtc8822b1ant_display_coex_info(IN struct btc_coexist *btcoexist);
+void ex_halbtc8822b1ant_antenna_detection(IN struct btc_coexist *btcoexist,
+		IN u32 cent_freq, IN u32 offset, IN u32 span, IN u32 seconds);
+void ex_halbtc8822b1ant_antenna_isolation(IN struct btc_coexist *btcoexist,
+		IN u32 cent_freq, IN u32 offset, IN u32 span, IN u32 seconds);
+
+void ex_halbtc8822b1ant_psd_scan(IN struct btc_coexist *btcoexist,
+		 IN u32 cent_freq, IN u32 offset, IN u32 span, IN u32 seconds);
+void ex_halbtc8822b1ant_display_ant_detection(IN struct btc_coexist *btcoexist);
+
+void ex_halbtc8822b1ant_dbg_control(IN struct btc_coexist *btcoexist,
+				    IN u8 op_code, IN u8 op_len, IN u8 *pdata);
+
+#else
+#define	ex_halbtc8822b1ant_power_on_setting(btcoexist)
+#define	ex_halbtc8822b1ant_pre_load_firmware(btcoexist)
+#define	ex_halbtc8822b1ant_init_hw_config(btcoexist, wifi_only)
+#define	ex_halbtc8822b1ant_init_coex_dm(btcoexist)
+#define	ex_halbtc8822b1ant_ips_notify(btcoexist, type)
+#define	ex_halbtc8822b1ant_lps_notify(btcoexist, type)
+#define	ex_halbtc8822b1ant_scan_notify(btcoexist, type)
+#define	ex_halbtc8822b1ant_scan_notify_without_bt(btcoexist, type)
+#define	ex_halbtc8822b1ant_switchband_notify(btcoexist, type)
+#define	ex_halbtc8822b1ant_switchband_notify_without_bt(btcoexist, type)
+#define	ex_halbtc8822b1ant_connect_notify(btcoexist, type)
+#define	ex_halbtc8822b1ant_media_status_notify(btcoexist, type)
+#define	ex_halbtc8822b1ant_specific_packet_notify(btcoexist, type)
+#define	ex_halbtc8822b1ant_bt_info_notify(btcoexist, tmp_buf, length)
+#define	ex_halbtc8822b1ant_rf_status_notify(btcoexist, type)
+#define	ex_halbtc8822b1ant_halt_notify(btcoexist)
+#define	ex_halbtc8822b1ant_pnp_notify(btcoexist, pnp_state)
+#define	ex_halbtc8822b1ant_ScoreBoardStatusNotify(btcoexist, tmp_buf, length)
+#define	ex_halbtc8822b1ant_coex_dm_reset(btcoexist)
+#define	ex_halbtc8822b1ant_periodical(btcoexist)
+#define	ex_halbtc8822b1ant_display_coex_info(btcoexist)
+#define	ex_halbtc8822b1ant_antenna_detection(btcoexist, cent_freq, offset, span, seconds)
+#define	ex_halbtc8822b1ant_antenna_isolation(btcoexist, cent_freq, offset, span, seconds)
+#define	ex_halbtc8822b1ant_psd_scan(btcoexist, cent_freq, offset, span, seconds)
+#define	ex_halbtc8822b1ant_display_ant_detection(btcoexist)
+#define	ex_halbtc8822b1ant_dbg_control(btcoexist, op_code, op_len, pdata)
+#endif
+#else
+
+void ex_halbtc8822b1ant_init_hw_config_without_bt(IN struct btc_coexist
+		*btcoexist);
+void ex_halbtc8822b1ant_switch_band_without_bt(IN struct btc_coexist *btcoexist,
+		IN boolean wifi_only_5g);
+
+
+#endif
+
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/btc/halbtc8822b2ant.c linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/btc/halbtc8822b2ant.c
--- linux-5.6.3/3rdparty/rtl8821ce/hal/btc/halbtc8822b2ant.c	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/btc/halbtc8822b2ant.c	2020-04-10 16:35:06.786658667 +0300
@@ -0,0 +1,5583 @@
+/* ************************************************************
+ * Description:
+ *
+ * This file is for RTL8822B Co-exist mechanism
+ *
+ * History
+ * 2012/11/15 Cosa first check in.
+ *
+ * ************************************************************ */
+
+/* ************************************************************
+ * include files
+ * ************************************************************ */
+#include "mp_precomp.h"
+
+#if (BT_SUPPORT == 1 && COEX_SUPPORT == 1)
+
+#if (RTL8822B_SUPPORT == 1)
+/* ************************************************************
+ * Global variables, these are static variables
+ * ************************************************************ */
+static u8	*trace_buf = &gl_btc_trace_buf[0];
+static struct  coex_dm_8822b_2ant		glcoex_dm_8822b_2ant;
+static struct  coex_dm_8822b_2ant	*coex_dm = &glcoex_dm_8822b_2ant;
+static struct  coex_sta_8822b_2ant		glcoex_sta_8822b_2ant;
+static struct  coex_sta_8822b_2ant	*coex_sta = &glcoex_sta_8822b_2ant;
+static struct  psdscan_sta_8822b_2ant	gl_psd_scan_8822b_2ant;
+static struct  psdscan_sta_8822b_2ant *psd_scan = &gl_psd_scan_8822b_2ant;
+static struct	rfe_type_8822b_2ant		gl_rfe_type_8822b_2ant;
+static struct	rfe_type_8822b_2ant		*rfe_type = &gl_rfe_type_8822b_2ant;
+
+const char *const glbt_info_src_8822b_2ant[] = {
+	"BT Info[wifi fw]",
+	"BT Info[bt rsp]",
+	"BT Info[bt auto report]",
+};
+
+u32	glcoex_ver_date_8822b_2ant = 20161124;
+u32	glcoex_ver_8822b_2ant = 0x3f;
+u32 glcoex_ver_btdesired_8822b_2ant = 0x28;
+
+/* ************************************************************
+ * local function proto type if needed
+ * ************************************************************
+ * ************************************************************
+ * local function start with halbtc8822b2ant_
+ * ************************************************************ */
+u8 halbtc8822b2ant_bt_rssi_state(u8 *ppre_bt_rssi_state, u8 level_num,
+				 u8 rssi_thresh, u8 rssi_thresh1)
+{
+	s32			bt_rssi = 0;
+	u8			bt_rssi_state = *ppre_bt_rssi_state;
+
+	bt_rssi = coex_sta->bt_rssi;
+
+	if (level_num == 2) {
+		if ((*ppre_bt_rssi_state == BTC_RSSI_STATE_LOW) ||
+		    (*ppre_bt_rssi_state == BTC_RSSI_STATE_STAY_LOW)) {
+			if (bt_rssi >= (rssi_thresh +
+					BTC_RSSI_COEX_THRESH_TOL_8822B_2ANT))
+				bt_rssi_state = BTC_RSSI_STATE_HIGH;
+			else
+				bt_rssi_state = BTC_RSSI_STATE_STAY_LOW;
+		} else {
+			if (bt_rssi < rssi_thresh)
+				bt_rssi_state = BTC_RSSI_STATE_LOW;
+			else
+				bt_rssi_state = BTC_RSSI_STATE_STAY_HIGH;
+		}
+	} else if (level_num == 3) {
+		if (rssi_thresh > rssi_thresh1) {
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				    "[BTCoex], BT Rssi thresh error!!\n");
+			BTC_TRACE(trace_buf);
+			return *ppre_bt_rssi_state;
+		}
+
+		if ((*ppre_bt_rssi_state == BTC_RSSI_STATE_LOW) ||
+		    (*ppre_bt_rssi_state == BTC_RSSI_STATE_STAY_LOW)) {
+			if (bt_rssi >= (rssi_thresh +
+					BTC_RSSI_COEX_THRESH_TOL_8822B_2ANT))
+				bt_rssi_state = BTC_RSSI_STATE_MEDIUM;
+			else
+				bt_rssi_state = BTC_RSSI_STATE_STAY_LOW;
+		} else if ((*ppre_bt_rssi_state == BTC_RSSI_STATE_MEDIUM) ||
+			(*ppre_bt_rssi_state == BTC_RSSI_STATE_STAY_MEDIUM)) {
+			if (bt_rssi >= (rssi_thresh1 +
+					BTC_RSSI_COEX_THRESH_TOL_8822B_2ANT))
+				bt_rssi_state = BTC_RSSI_STATE_HIGH;
+			else if (bt_rssi < rssi_thresh)
+				bt_rssi_state = BTC_RSSI_STATE_LOW;
+			else
+				bt_rssi_state = BTC_RSSI_STATE_STAY_MEDIUM;
+		} else {
+			if (bt_rssi < rssi_thresh1)
+				bt_rssi_state = BTC_RSSI_STATE_MEDIUM;
+			else
+				bt_rssi_state = BTC_RSSI_STATE_STAY_HIGH;
+		}
+	}
+
+	*ppre_bt_rssi_state = bt_rssi_state;
+
+	return bt_rssi_state;
+}
+
+u8 halbtc8822b2ant_wifi_rssi_state(IN struct btc_coexist *btcoexist,
+	   IN u8 *pprewifi_rssi_state, IN u8 level_num, IN u8 rssi_thresh,
+				   IN u8 rssi_thresh1)
+{
+	s32			wifi_rssi = 0;
+	u8			wifi_rssi_state = *pprewifi_rssi_state;
+
+	btcoexist->btc_get(btcoexist, BTC_GET_S4_WIFI_RSSI, &wifi_rssi);
+
+	if (level_num == 2) {
+		if ((*pprewifi_rssi_state == BTC_RSSI_STATE_LOW) ||
+		    (*pprewifi_rssi_state == BTC_RSSI_STATE_STAY_LOW)) {
+			if (wifi_rssi >= (rssi_thresh +
+					  BTC_RSSI_COEX_THRESH_TOL_8822B_2ANT))
+				wifi_rssi_state = BTC_RSSI_STATE_HIGH;
+			else
+				wifi_rssi_state = BTC_RSSI_STATE_STAY_LOW;
+		} else {
+			if (wifi_rssi < rssi_thresh)
+				wifi_rssi_state = BTC_RSSI_STATE_LOW;
+			else
+				wifi_rssi_state = BTC_RSSI_STATE_STAY_HIGH;
+		}
+	} else if (level_num == 3) {
+		if (rssi_thresh > rssi_thresh1) {
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				    "[BTCoex], wifi RSSI thresh error!!\n");
+			BTC_TRACE(trace_buf);
+			return *pprewifi_rssi_state;
+		}
+
+		if ((*pprewifi_rssi_state == BTC_RSSI_STATE_LOW) ||
+		    (*pprewifi_rssi_state == BTC_RSSI_STATE_STAY_LOW)) {
+			if (wifi_rssi >= (rssi_thresh +
+					  BTC_RSSI_COEX_THRESH_TOL_8822B_2ANT))
+				wifi_rssi_state = BTC_RSSI_STATE_MEDIUM;
+			else
+				wifi_rssi_state = BTC_RSSI_STATE_STAY_LOW;
+		} else if ((*pprewifi_rssi_state == BTC_RSSI_STATE_MEDIUM) ||
+			(*pprewifi_rssi_state == BTC_RSSI_STATE_STAY_MEDIUM)) {
+			if (wifi_rssi >= (rssi_thresh1 +
+					  BTC_RSSI_COEX_THRESH_TOL_8822B_2ANT))
+				wifi_rssi_state = BTC_RSSI_STATE_HIGH;
+			else if (wifi_rssi < rssi_thresh)
+				wifi_rssi_state = BTC_RSSI_STATE_LOW;
+			else
+				wifi_rssi_state = BTC_RSSI_STATE_STAY_MEDIUM;
+		} else {
+			if (wifi_rssi < rssi_thresh1)
+				wifi_rssi_state = BTC_RSSI_STATE_MEDIUM;
+			else
+				wifi_rssi_state = BTC_RSSI_STATE_STAY_HIGH;
+		}
+	}
+
+	*pprewifi_rssi_state = wifi_rssi_state;
+
+	return wifi_rssi_state;
+}
+
+void halbtc8822b2ant_coex_switch_threshold(IN struct btc_coexist *btcoexist,
+		IN u8 isolation_measuared)
+{
+	s8	interference_wl_tx = 0, interference_bt_tx = 0;
+
+
+	interference_wl_tx = BT_8822B_2ANT_WIFI_MAX_TX_POWER -
+			     isolation_measuared;
+	interference_bt_tx = BT_8822B_2ANT_BT_MAX_TX_POWER -
+			     isolation_measuared;
+
+
+
+	coex_sta->wifi_coex_thres		 = BT_8822B_2ANT_WIFI_RSSI_COEXSWITCH_THRES1;
+	coex_sta->wifi_coex_thres2	 = BT_8822B_2ANT_WIFI_RSSI_COEXSWITCH_THRES2;
+
+	coex_sta->bt_coex_thres		 = BT_8822B_2ANT_BT_RSSI_COEXSWITCH_THRES1;
+	coex_sta->bt_coex_thres2		 = BT_8822B_2ANT_BT_RSSI_COEXSWITCH_THRES2;
+
+
+	/*
+		coex_sta->wifi_coex_thres		= interference_wl_tx + BT_8822B_2ANT_WIFI_SIR_THRES1;
+		coex_sta->wifi_coex_thres2		= interference_wl_tx + BT_8822B_2ANT_WIFI_SIR_THRES2;
+
+		coex_sta->bt_coex_thres		= interference_bt_tx + BT_8822B_2ANT_BT_SIR_THRES1;
+		coex_sta->bt_coex_thres2		= interference_bt_tx + BT_8822B_2ANT_BT_SIR_THRES2;
+	*/
+
+
+
+
+
+	/*
+		if  ( BT_8822B_2ANT_WIFI_RSSI_COEXSWITCH_THRES1 < (isolation_measuared -
+					BT_8822B_2ANT_DEFAULT_ISOLATION) )
+			coex_sta->wifi_coex_thres	 = BT_8822B_2ANT_WIFI_RSSI_COEXSWITCH_THRES1;
+		else
+			coex_sta->wifi_coex_thres =  BT_8822B_2ANT_WIFI_RSSI_COEXSWITCH_THRES1 -  (isolation_measuared -
+					BT_8822B_2ANT_DEFAULT_ISOLATION);
+
+		if  ( BT_8822B_2ANT_BT_RSSI_COEXSWITCH_THRES1 < (isolation_measuared -
+					BT_8822B_2ANT_DEFAULT_ISOLATION) )
+			coex_sta->bt_coex_thres	 = BT_8822B_2ANT_BT_RSSI_COEXSWITCH_THRES1;
+		else
+			coex_sta->bt_coex_thres =  BT_8822B_2ANT_BT_RSSI_COEXSWITCH_THRES1 -  (isolation_measuared -
+					BT_8822B_2ANT_DEFAULT_ISOLATION);
+
+	*/
+}
+
+
+void halbtc8822b2ant_limited_rx(IN struct btc_coexist *btcoexist,
+			IN boolean force_exec, IN boolean rej_ap_agg_pkt,
+			IN boolean bt_ctrl_agg_buf_size, IN u8 agg_buf_size)
+{
+	boolean	reject_rx_agg = rej_ap_agg_pkt;
+	boolean	bt_ctrl_rx_agg_size = bt_ctrl_agg_buf_size;
+	u8	rx_agg_size = agg_buf_size;
+
+	/* ============================================ */
+	/*	Rx Aggregation related setting */
+	/* ============================================ */
+	btcoexist->btc_set(btcoexist, BTC_SET_BL_TO_REJ_AP_AGG_PKT,
+			   &reject_rx_agg);
+	/* decide BT control aggregation buf size or not */
+	btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_CTRL_AGG_SIZE,
+			   &bt_ctrl_rx_agg_size);
+	/* aggregation buf size, only work when BT control Rx aggregation size. */
+	btcoexist->btc_set(btcoexist, BTC_SET_U1_AGG_BUF_SIZE, &rx_agg_size);
+	/* real update aggregation setting */
+	btcoexist->btc_set(btcoexist, BTC_SET_ACT_AGGREGATE_CTRL, NULL);
+}
+
+void halbtc8822b2ant_query_bt_info(IN struct btc_coexist *btcoexist)
+{
+	u8			h2c_parameter[1] = {0};
+	boolean		RTL97F_8822B = false;
+
+	if (RTL97F_8822B == true)
+		return;
+
+	coex_sta->c2h_bt_info_req_sent = true;
+
+	h2c_parameter[0] |= BIT(0);	/* trigger */
+
+	btcoexist->btc_fill_h2c(btcoexist, 0x61, 1, h2c_parameter);
+}
+
+void halbtc8822b2ant_monitor_bt_ctr(IN struct btc_coexist *btcoexist)
+{
+	u32			reg_hp_txrx, reg_lp_txrx, u32tmp;
+	u32			reg_hp_tx = 0, reg_hp_rx = 0, reg_lp_tx = 0, reg_lp_rx = 0;
+	static u8		num_of_bt_counter_chk = 0, cnt_slave = 0;
+
+	struct  btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
+
+	reg_hp_txrx = 0x770;
+	reg_lp_txrx = 0x774;
+
+	u32tmp = btcoexist->btc_read_4byte(btcoexist, reg_hp_txrx);
+	reg_hp_tx = u32tmp & MASKLWORD;
+	reg_hp_rx = (u32tmp & MASKHWORD) >> 16;
+
+	u32tmp = btcoexist->btc_read_4byte(btcoexist, reg_lp_txrx);
+	reg_lp_tx = u32tmp & MASKLWORD;
+	reg_lp_rx = (u32tmp & MASKHWORD) >> 16;
+
+	coex_sta->high_priority_tx = reg_hp_tx;
+	coex_sta->high_priority_rx = reg_hp_rx;
+	coex_sta->low_priority_tx = reg_lp_tx;
+	coex_sta->low_priority_rx = reg_lp_rx;
+
+
+	/* reset counter */
+	btcoexist->btc_write_1byte(btcoexist, 0x76e, 0xc);
+
+	if ((coex_sta->low_priority_tx > 1050)  &&
+	    (!coex_sta->c2h_bt_inquiry_page))
+		coex_sta->pop_event_cnt++;
+
+	if ((coex_sta->low_priority_rx >= 950) &&
+	    (coex_sta->low_priority_rx >= coex_sta->low_priority_tx)
+	    && (!coex_sta->under_ips)  && (!coex_sta->c2h_bt_inquiry_page) &&
+	    (coex_sta->bt_link_exist))	{
+		if (cnt_slave >= 2) {
+			bt_link_info->slave_role = true;
+			cnt_slave = 2;
+		} else
+			cnt_slave++;
+	} else {
+		if (cnt_slave == 0)	{
+			bt_link_info->slave_role = false;
+			cnt_slave = 0;
+		} else
+			cnt_slave--;
+
+	}
+
+	if ((coex_sta->high_priority_tx == 0) &&
+	    (coex_sta->high_priority_rx == 0) &&
+	    (coex_sta->low_priority_tx == 0) &&
+	    (coex_sta->low_priority_rx == 0)) {
+		num_of_bt_counter_chk++;
+		if (num_of_bt_counter_chk >= 3) {
+			halbtc8822b2ant_query_bt_info(btcoexist);
+			num_of_bt_counter_chk = 0;
+		}
+	}
+
+}
+
+void halbtc8822b2ant_monitor_wifi_ctr(IN struct btc_coexist *btcoexist)
+{
+#if 0
+	s32 wifi_rssi = 0;
+	boolean wifi_busy = false, wifi_under_b_mode = false;
+	static u8 cck_lock_counter = 0;
+	u32 total_cnt, reg_val1, reg_val2;
+
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy);
+	btcoexist->btc_get(btcoexist, BTC_GET_S4_WIFI_RSSI, &wifi_rssi);
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_B_MODE,
+			   &wifi_under_b_mode);
+
+	if (coex_sta->under_ips) {
+		coex_sta->crc_ok_cck = 0;
+		coex_sta->crc_ok_11g = 0;
+		coex_sta->crc_ok_11n = 0;
+		coex_sta->crc_ok_11n_agg = 0;
+
+		coex_sta->crc_err_cck = 0;
+		coex_sta->crc_err_11g = 0;
+		coex_sta->crc_err_11n = 0;
+		coex_sta->crc_err_11n_agg = 0;
+	} else {
+
+		reg_val1 = btcoexist->btc_read_4byte(btcoexist, 0xf00);
+		reg_val2 = btcoexist->btc_read_4byte(btcoexist, 0xf04);
+		coex_sta->crc_ok_cck = reg_val2 & 0xffff;
+		coex_sta->crc_err_cck = (reg_val1 & 0xffff) + ((reg_val2
+					& 0xffff0000) >> 16);
+
+		reg_val1 = btcoexist->btc_read_4byte(btcoexist, 0xf0c);
+		coex_sta->crc_ok_11n_agg = reg_val1 & 0xffff;
+		coex_sta->crc_err_11n_agg = (reg_val1 & 0xffff0000) >>
+					    16;
+
+		reg_val1 = btcoexist->btc_read_4byte(btcoexist, 0xf10);
+		coex_sta->crc_ok_11n = reg_val1 & 0xffff;
+		coex_sta->crc_err_11n = (reg_val1 & 0xffff0000) >> 16;
+
+		reg_val1 = btcoexist->btc_read_4byte(btcoexist, 0xf14);
+		coex_sta->crc_ok_11g = reg_val1 & 0xffff;
+		coex_sta->crc_err_11n = (reg_val1 & 0xffff0000) >> 16;
+	}
+
+
+	/* reset counter */
+	/*btcoexist->btc_write_1byte_bitmask(btcoexist, 0xb58, 0x1, 0x1);*/
+	/*btcoexist->btc_write_1byte_bitmask(btcoexist, 0xb58, 0x1, 0x0);*/
+
+	if ((wifi_busy) && (wifi_rssi >= 30) && (!wifi_under_b_mode)) {
+		total_cnt = coex_sta->crc_ok_cck + coex_sta->crc_ok_11g
+			    +
+			    coex_sta->crc_ok_11n +
+			    coex_sta->crc_ok_11n_agg;
+
+		if ((coex_dm->bt_status ==
+		     BT_8822B_2ANT_BT_STATUS_ACL_BUSY) ||
+		    (coex_dm->bt_status ==
+		     BT_8822B_2ANT_BT_STATUS_ACL_SCO_BUSY) ||
+		    (coex_dm->bt_status ==
+		     BT_8822B_2ANT_BT_STATUS_SCO_BUSY)) {
+			if (coex_sta->crc_ok_cck > (total_cnt -
+						    coex_sta->crc_ok_cck)) {
+				if (cck_lock_counter < 3)
+					cck_lock_counter++;
+			} else {
+				if (cck_lock_counter > 0)
+					cck_lock_counter--;
+			}
+
+		} else {
+			if (cck_lock_counter > 0)
+				cck_lock_counter--;
+		}
+	} else {
+		if (cck_lock_counter > 0)
+			cck_lock_counter--;
+	}
+
+	if (!coex_sta->pre_ccklock) {
+
+		if (cck_lock_counter >= 3)
+			coex_sta->cck_lock = true;
+		else
+			coex_sta->cck_lock = false;
+	} else {
+		if (cck_lock_counter == 0)
+			coex_sta->cck_lock = false;
+		else
+			coex_sta->cck_lock = true;
+	}
+
+	if (coex_sta->cck_lock)
+		coex_sta->cck_ever_lock = true;
+
+	coex_sta->pre_ccklock =  coex_sta->cck_lock;
+
+#endif
+}
+
+boolean halbtc8822b2ant_is_wifibt_status_changed(IN struct btc_coexist
+		*btcoexist)
+{
+	static boolean	pre_wifi_busy = false, pre_under_4way = false,
+			pre_bt_hs_on = false, pre_bt_off = false;
+	static u8 pre_hid_busy_num = 0;
+	boolean wifi_busy = false, under_4way = false, bt_hs_on = false;
+	boolean wifi_connected = false;
+
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED,
+			   &wifi_connected);
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy);
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on);
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_4_WAY_PROGRESS,
+			   &under_4way);
+
+	if (coex_sta->bt_disabled != pre_bt_off) {
+		pre_bt_off = coex_sta->bt_disabled;
+
+		if (coex_sta->bt_disabled)
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				    "[BTCoex], BT is disabled !!\n");
+		else
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				    "[BTCoex], BT is enabled !!\n");
+
+		BTC_TRACE(trace_buf);
+
+		coex_sta->bt_coex_supported_feature = 0;
+		coex_sta->bt_coex_supported_version = 0;
+		coex_sta->bt_ble_scan_type = 0;
+		coex_sta->bt_ble_scan_para[0] = 0;
+		coex_sta->bt_ble_scan_para[1] = 0;
+		coex_sta->bt_ble_scan_para[2] = 0;
+		coex_sta->bt_reg_vendor_ac = 0xffff;
+		coex_sta->bt_reg_vendor_ae = 0xffff;
+		return true;
+	}
+
+
+	if (wifi_connected) {
+		if (wifi_busy != pre_wifi_busy) {
+			pre_wifi_busy = wifi_busy;
+			return true;
+		}
+		if (under_4way != pre_under_4way) {
+			pre_under_4way = under_4way;
+			return true;
+		}
+		if (bt_hs_on != pre_bt_hs_on) {
+			pre_bt_hs_on = bt_hs_on;
+			return true;
+		}
+
+		if (!coex_sta->bt_disabled) {
+
+			if (coex_sta->hid_busy_num != pre_hid_busy_num) {
+				pre_hid_busy_num = coex_sta->hid_busy_num;
+				return true;
+			}
+		}
+	}
+
+	return false;
+}
+
+
+void halbtc8822b2ant_update_bt_link_info(IN struct btc_coexist *btcoexist)
+{
+
+	struct	btc_bt_link_info	*bt_link_info = &btcoexist->bt_link_info;
+	boolean			bt_hs_on = false;
+	boolean		bt_busy = false;
+
+	coex_sta->num_of_profile = 0;
+
+	/* set link exist status */
+	if (!(coex_sta->bt_info & BT_INFO_8822B_1ANT_B_CONNECTION)) {
+		coex_sta->bt_link_exist = false;
+		coex_sta->pan_exist = false;
+		coex_sta->a2dp_exist = false;
+		coex_sta->hid_exist = false;
+		coex_sta->sco_exist = false;
+	} else {	/* connection exists */
+		coex_sta->bt_link_exist = true;
+		if (coex_sta->bt_info & BT_INFO_8822B_1ANT_B_FTP) {
+			coex_sta->pan_exist = true;
+			coex_sta->num_of_profile++;
+		} else
+			coex_sta->pan_exist = false;
+
+		if (coex_sta->bt_info & BT_INFO_8822B_1ANT_B_A2DP) {
+			coex_sta->a2dp_exist = true;
+			coex_sta->num_of_profile++;
+		} else
+			coex_sta->a2dp_exist = false;
+
+		if (coex_sta->bt_info & BT_INFO_8822B_1ANT_B_HID) {
+			coex_sta->hid_exist = true;
+			coex_sta->num_of_profile++;
+		} else
+			coex_sta->hid_exist = false;
+
+		if (coex_sta->bt_info & BT_INFO_8822B_1ANT_B_SCO_ESCO) {
+			coex_sta->sco_exist = true;
+			coex_sta->num_of_profile++;
+		} else
+			coex_sta->sco_exist = false;
+
+	}
+
+
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on);
+
+	bt_link_info->bt_link_exist = coex_sta->bt_link_exist;
+	bt_link_info->sco_exist = coex_sta->sco_exist;
+	bt_link_info->a2dp_exist = coex_sta->a2dp_exist;
+	bt_link_info->pan_exist = coex_sta->pan_exist;
+	bt_link_info->hid_exist = coex_sta->hid_exist;
+	bt_link_info->acl_busy = coex_sta->acl_busy;
+
+	/* work around for HS mode. */
+	if (bt_hs_on) {
+		bt_link_info->pan_exist = true;
+		bt_link_info->bt_link_exist = true;
+	}
+
+	/* check if Sco only */
+	if (bt_link_info->sco_exist &&
+	    !bt_link_info->a2dp_exist &&
+	    !bt_link_info->pan_exist &&
+	    !bt_link_info->hid_exist)
+		bt_link_info->sco_only = true;
+	else
+		bt_link_info->sco_only = false;
+
+	/* check if A2dp only */
+	if (!bt_link_info->sco_exist &&
+	    bt_link_info->a2dp_exist &&
+	    !bt_link_info->pan_exist &&
+	    !bt_link_info->hid_exist)
+		bt_link_info->a2dp_only = true;
+	else
+		bt_link_info->a2dp_only = false;
+
+	/* check if Pan only */
+	if (!bt_link_info->sco_exist &&
+	    !bt_link_info->a2dp_exist &&
+	    bt_link_info->pan_exist &&
+	    !bt_link_info->hid_exist)
+		bt_link_info->pan_only = true;
+	else
+		bt_link_info->pan_only = false;
+
+	/* check if Hid only */
+	if (!bt_link_info->sco_exist &&
+	    !bt_link_info->a2dp_exist &&
+	    !bt_link_info->pan_exist &&
+	    bt_link_info->hid_exist)
+		bt_link_info->hid_only = true;
+	else
+		bt_link_info->hid_only = false;
+
+	if (!(coex_sta->bt_info & BT_INFO_8822B_2ANT_B_CONNECTION)) {
+		coex_dm->bt_status = BT_8822B_2ANT_BT_STATUS_NON_CONNECTED_IDLE;
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			"[BTCoex], BtInfoNotify(), BT Non-Connected idle!!!\n");
+	} else if (coex_sta->bt_info == BT_INFO_8822B_2ANT_B_CONNECTION) {
+		/* connection exists but no busy */
+		coex_dm->bt_status = BT_8822B_2ANT_BT_STATUS_CONNECTED_IDLE;
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], BtInfoNotify(), BT Connected-idle!!!\n");
+	} else if (((coex_sta->bt_info & BT_INFO_8822B_2ANT_B_SCO_ESCO) ||
+		    (coex_sta->bt_info & BT_INFO_8822B_2ANT_B_SCO_BUSY)) &&
+		   (coex_sta->bt_info & BT_INFO_8822B_2ANT_B_ACL_BUSY)) {
+		coex_dm->bt_status = BT_8822B_2ANT_BT_STATUS_ACL_SCO_BUSY;
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], BtInfoNotify(), BT ACL SCO busy!!!\n");
+	} else if ((coex_sta->bt_info & BT_INFO_8822B_2ANT_B_SCO_ESCO) ||
+		   (coex_sta->bt_info & BT_INFO_8822B_2ANT_B_SCO_BUSY)) {
+		coex_dm->bt_status = BT_8822B_2ANT_BT_STATUS_SCO_BUSY;
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], BtInfoNotify(), BT SCO busy!!!\n");
+	} else if (coex_sta->bt_info & BT_INFO_8822B_2ANT_B_ACL_BUSY) {
+		coex_dm->bt_status = BT_8822B_2ANT_BT_STATUS_ACL_BUSY;
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], BtInfoNotify(), BT ACL busy!!!\n");
+	} else {
+		coex_dm->bt_status = BT_8822B_2ANT_BT_STATUS_MAX;
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			"[BTCoex], BtInfoNotify(), BT Non-Defined state!!!\n");
+	}
+
+	BTC_TRACE(trace_buf);
+
+	if ((BT_8822B_2ANT_BT_STATUS_ACL_BUSY == coex_dm->bt_status) ||
+	    (BT_8822B_2ANT_BT_STATUS_SCO_BUSY == coex_dm->bt_status) ||
+	    (BT_8822B_2ANT_BT_STATUS_ACL_SCO_BUSY == coex_dm->bt_status))
+		bt_busy = true;
+	else
+		bt_busy = false;
+
+	btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_TRAFFIC_BUSY, &bt_busy);
+}
+
+void halbtc8822b2ant_update_wifi_channel_info(IN struct btc_coexist *btcoexist,
+		IN u8 type)
+{
+	u8	h2c_parameter[3] = {0};
+	u32	wifi_bw;
+	u8	wifi_central_chnl;
+	u32	RTL97F_8822B = 0;
+
+	if (RTL97F_8822B == true)
+		return;
+
+	/* only 2.4G we need to inform bt the chnl mask */
+	btcoexist->btc_get(btcoexist, BTC_GET_U1_WIFI_CENTRAL_CHNL,
+			   &wifi_central_chnl);
+	if ((BTC_MEDIA_CONNECT == type) &&
+	    (wifi_central_chnl <= 14)) {
+		h2c_parameter[0] =
+			0x1;  /* enable BT AFH skip WL channel for 8822b because BT Rx LO interference */
+		/* h2c_parameter[0] = 0x0; */
+		h2c_parameter[1] = wifi_central_chnl;
+		btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw);
+		if (BTC_WIFI_BW_HT40 == wifi_bw)
+			h2c_parameter[2] = 0x30;
+		else
+			h2c_parameter[2] = 0x20;
+	}
+
+	coex_dm->wifi_chnl_info[0] = h2c_parameter[0];
+	coex_dm->wifi_chnl_info[1] = h2c_parameter[1];
+	coex_dm->wifi_chnl_info[2] = h2c_parameter[2];
+
+	btcoexist->btc_fill_h2c(btcoexist, 0x66, 3, h2c_parameter);
+
+}
+
+void halbtc8822b2ant_set_fw_dac_swing_level(IN struct btc_coexist *btcoexist,
+		IN u8 dac_swing_lvl)
+{
+	u8	h2c_parameter[1] = {0};
+	u32	RTL97F_8822B = 0;
+
+	if (RTL97F_8822B == true)
+			return;
+
+	/* There are several type of dacswing */
+	/* 0x18/ 0x10/ 0xc/ 0x8/ 0x4/ 0x6 */
+	h2c_parameter[0] = dac_swing_lvl;
+
+	btcoexist->btc_fill_h2c(btcoexist, 0x64, 1, h2c_parameter);
+}
+
+void halbtc8822b2ant_fw_dac_swing_lvl(IN struct btc_coexist *btcoexist,
+			      IN boolean force_exec, IN u8 fw_dac_swing_lvl)
+{
+	u32	RTL97F_8822B = 0;
+
+	if (RTL97F_8822B == true)
+		return;
+
+	coex_dm->cur_fw_dac_swing_lvl = fw_dac_swing_lvl;
+
+	if (!force_exec) {
+		if (coex_dm->pre_fw_dac_swing_lvl ==
+		    coex_dm->cur_fw_dac_swing_lvl)
+			return;
+	}
+
+	halbtc8822b2ant_set_fw_dac_swing_level(btcoexist,
+					       coex_dm->cur_fw_dac_swing_lvl);
+
+	coex_dm->pre_fw_dac_swing_lvl = coex_dm->cur_fw_dac_swing_lvl;
+}
+
+void halbtc8822b2ant_set_fw_dec_bt_pwr(IN struct btc_coexist *btcoexist,
+				       IN u8 dec_bt_pwr_lvl)
+{
+	u32	RTL97F_8822B = 0;
+	u8	h2c_parameter[1] = {0};
+
+	if (RTL97F_8822B == true)
+		return;
+
+	h2c_parameter[0] = dec_bt_pwr_lvl;
+
+	btcoexist->btc_fill_h2c(btcoexist, 0x62, 1, h2c_parameter);
+}
+
+void halbtc8822b2ant_dec_bt_pwr(IN struct btc_coexist *btcoexist,
+				IN boolean force_exec, IN u8 dec_bt_pwr_lvl)
+{
+	coex_dm->cur_bt_dec_pwr_lvl = dec_bt_pwr_lvl;
+
+	if (!force_exec) {
+		if (coex_dm->pre_bt_dec_pwr_lvl == coex_dm->cur_bt_dec_pwr_lvl)
+			return;
+	}
+	halbtc8822b2ant_set_fw_dec_bt_pwr(btcoexist,
+					  coex_dm->cur_bt_dec_pwr_lvl);
+
+	coex_dm->pre_bt_dec_pwr_lvl = coex_dm->cur_bt_dec_pwr_lvl;
+}
+
+
+void halbtc8822b2ant_low_penalty_ra(IN struct btc_coexist *btcoexist,
+			    IN boolean force_exec, IN boolean low_penalty_ra)
+{
+
+#if 1
+	coex_dm->cur_low_penalty_ra = low_penalty_ra;
+
+	if (!force_exec) {
+		if (coex_dm->pre_low_penalty_ra ==
+		    coex_dm->cur_low_penalty_ra)
+			return;
+	}
+
+	if (low_penalty_ra)
+		btcoexist->btc_phydm_modify_RA_PCR_threshold(btcoexist, 0, 50);
+	else
+		btcoexist->btc_phydm_modify_RA_PCR_threshold(btcoexist, 0, 0);
+
+	coex_dm->pre_low_penalty_ra = coex_dm->cur_low_penalty_ra;
+
+#endif
+
+}
+
+
+void halbtc8822b2ant_set_bt_auto_report(IN struct btc_coexist *btcoexist,
+					IN boolean enable_auto_report)
+{
+	u8	h2c_parameter[1] = {0};
+	u32	RTL97F_8822B = 0;
+
+	if (RTL97F_8822B == true)
+		return;
+
+	h2c_parameter[0] = 0;
+
+	if (enable_auto_report)
+		h2c_parameter[0] |= BIT(0);
+
+	btcoexist->btc_fill_h2c(btcoexist, 0x68, 1, h2c_parameter);
+}
+
+void halbtc8822b2ant_bt_auto_report(IN struct btc_coexist *btcoexist,
+		    IN boolean force_exec, IN boolean enable_auto_report)
+{
+	coex_dm->cur_bt_auto_report = enable_auto_report;
+
+	if (!force_exec) {
+		if (coex_dm->pre_bt_auto_report == coex_dm->cur_bt_auto_report)
+			return;
+	}
+	halbtc8822b2ant_set_bt_auto_report(btcoexist,
+					   coex_dm->cur_bt_auto_report);
+
+	coex_dm->pre_bt_auto_report = coex_dm->cur_bt_auto_report;
+}
+
+void halbtc8822b2ant_write_score_board(
+	IN	struct  btc_coexist		*btcoexist,
+	IN	u16				bitpos,
+	IN	boolean		state
+)
+{
+
+	static u16 originalval = 0x8002;
+
+	if (state)
+		originalval = originalval | bitpos;
+	else
+		originalval = originalval & (~bitpos);
+
+
+	btcoexist->btc_write_2byte(btcoexist, 0xaa, originalval);
+
+}
+
+void halbtc8822b2ant_read_score_board(
+	IN	struct  btc_coexist		*btcoexist,
+	IN   u16				*score_board_val
+)
+{
+
+	*score_board_val = (btcoexist->btc_read_2byte(btcoexist,
+			    0xaa)) & 0x7fff;
+}
+
+void halbtc8822b2ant_post_state_to_bt(
+	IN	struct  btc_coexist		*btcoexist,
+	IN	u16						type,
+	IN  BOOLEAN                 state
+)
+{
+
+	halbtc8822b2ant_write_score_board(btcoexist, (u16) type, state);
+
+}
+
+
+
+void halbtc8822b2ant_monitor_bt_enable_disable(IN struct btc_coexist *btcoexist)
+{
+	static u32		bt_disable_cnt = 0;
+	boolean			bt_active = true, bt_disabled = false, wifi_under_5g = false;
+	u16			u16tmp;
+
+	/* This function check if bt is disabled */
+#if 0
+	if (coex_sta->high_priority_tx == 0 &&
+	    coex_sta->high_priority_rx == 0 &&
+	    coex_sta->low_priority_tx == 0 &&
+	    coex_sta->low_priority_rx == 0)
+		bt_active = false;
+	if (coex_sta->high_priority_tx == 0xffff &&
+	    coex_sta->high_priority_rx == 0xffff &&
+	    coex_sta->low_priority_tx == 0xffff &&
+	    coex_sta->low_priority_rx == 0xffff)
+		bt_active = false;
+
+
+#else
+
+	/* Read BT on/off status from scoreboard[1], enable this only if BT patch support this feature */
+	halbtc8822b2ant_read_score_board(btcoexist,	&u16tmp);
+
+	bt_active = u16tmp & BIT(1);
+
+
+#endif
+
+	if (bt_active) {
+		bt_disable_cnt = 0;
+		bt_disabled = false;
+		btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_DISABLE,
+				   &bt_disabled);
+	} else {
+
+		bt_disable_cnt++;
+		if (bt_disable_cnt >= 10) {
+			bt_disabled = true;
+			bt_disable_cnt = 10;
+		}
+
+		btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_DISABLE,
+				   &bt_disabled);
+	}
+
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_5G, &wifi_under_5g);
+
+	if ((wifi_under_5g) || (bt_disabled))
+		halbtc8822b2ant_low_penalty_ra(btcoexist, NORMAL_EXEC, false);
+	else
+		halbtc8822b2ant_low_penalty_ra(btcoexist, NORMAL_EXEC, true);
+
+
+	if (coex_sta->bt_disabled != bt_disabled) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], BT is from %s to %s!!\n",
+			    (coex_sta->bt_disabled ? "disabled" : "enabled"),
+			    (bt_disabled ? "disabled" : "enabled"));
+		BTC_TRACE(trace_buf);
+		coex_sta->bt_disabled = bt_disabled;
+	}
+
+}
+
+void halbtc8822b2ant_enable_gnt_to_gpio(IN struct btc_coexist *btcoexist,
+					boolean isenable)
+{
+#if BT_8822B_2ANT_COEX_DBG
+	static u8			bitVal[5] = {0, 0, 0, 0, 0};
+	static boolean		state = false;
+	/*
+		if (state ==isenable)
+			return;
+		else
+			state = isenable;
+	*/
+	if (isenable) {
+
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], enable_gnt_to_gpio!!\n");
+		BTC_TRACE(trace_buf);
+
+		/* enable GNT_WL, GNT_BT to GPIO for debug */
+		btcoexist->btc_write_1byte_bitmask(btcoexist, 0x73, 0x8, 0x1);
+
+		/* store original value */
+		bitVal[0] = (btcoexist->btc_read_1byte(btcoexist,
+				       0x66) & BIT(4)) >> 4;	/*0x66[4] */
+		bitVal[1] = (btcoexist->btc_read_1byte(btcoexist,
+					       0x67) & BIT(0));		/*0x66[8] */
+		bitVal[2] = (btcoexist->btc_read_1byte(btcoexist,
+				       0x42) & BIT(3)) >> 3;  /*0x40[19] */
+		bitVal[3] = (btcoexist->btc_read_1byte(btcoexist,
+				       0x65) & BIT(7)) >> 7;  /*0x64[15] */
+		bitVal[4] = (btcoexist->btc_read_1byte(btcoexist,
+				       0x72) & BIT(2)) >> 2;  /*0x70[18] */
+
+		/*  switch GPIO Mux */
+		btcoexist->btc_write_1byte_bitmask(btcoexist, 0x66, BIT(4),
+						   0x0);  /*0x66[4] = 0 */
+		btcoexist->btc_write_1byte_bitmask(btcoexist, 0x67, BIT(0),
+						   0x0);  /*0x66[8] = 0 */
+		btcoexist->btc_write_1byte_bitmask(btcoexist, 0x42, BIT(3),
+						   0x0);  /*0x40[19] = 0 */
+		btcoexist->btc_write_1byte_bitmask(btcoexist, 0x65, BIT(7),
+						   0x0);  /*0x64[15] = 0 */
+		btcoexist->btc_write_1byte_bitmask(btcoexist, 0x72, BIT(2),
+						   0x0);  /*0x70[18] = 0 */
+
+
+	} else {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], disable_gnt_to_gpio!!\n");
+		BTC_TRACE(trace_buf);
+
+		btcoexist->btc_write_1byte_bitmask(btcoexist, 0x73, 0x8, 0x0);
+
+		/*  Restore original value  */
+		/*  switch GPIO Mux */
+		btcoexist->btc_write_1byte_bitmask(btcoexist, 0x66, BIT(4),
+						   bitVal[0]);  /*0x66[4] = 0 */
+		btcoexist->btc_write_1byte_bitmask(btcoexist, 0x67, BIT(0),
+						   bitVal[1]);  /*0x66[8] = 0 */
+		btcoexist->btc_write_1byte_bitmask(btcoexist, 0x42, BIT(3),
+					   bitVal[2]);  /*0x40[19] = 0 */
+		btcoexist->btc_write_1byte_bitmask(btcoexist, 0x65, BIT(7),
+					   bitVal[3]);  /*0x64[15] = 0 */
+		btcoexist->btc_write_1byte_bitmask(btcoexist, 0x72, BIT(2),
+					   bitVal[4]);  /*0x70[18] = 0 */
+	}
+
+#endif
+}
+
+u32 halbtc8822b2ant_ltecoex_indirect_read_reg(IN struct btc_coexist *btcoexist,
+		IN u16 reg_addr)
+{
+	u32 j = 0, delay_count = 0;
+
+
+	/* wait for ready bit before access 0x1700		 */
+	btcoexist->btc_write_4byte(btcoexist, 0x1700, 0x800F0000 | reg_addr);
+#if 0
+	do {
+		j++;
+	} while (((btcoexist->btc_read_1byte(btcoexist,
+					     0x1703)&BIT(5)) == 0) &&
+		 (j < BT_8822B_2ANT_LTECOEX_INDIRECTREG_ACCESS_TIMEOUT));
+#endif
+	while (1) {
+		if ((btcoexist->btc_read_1byte(btcoexist, 0x1703)&BIT(5)) == 0) {
+			delay_ms(50);
+			delay_count++;
+			if (delay_count >= 10) {
+				delay_count = 0;
+				break;
+			}
+		} else
+			break;
+	}
+
+
+	return btcoexist->btc_read_4byte(btcoexist,
+					 0x1708);  /* get read data */
+
+}
+
+void halbtc8822b2ant_ltecoex_indirect_write_reg(IN struct btc_coexist
+		*btcoexist,
+		IN u16 reg_addr, IN u32 bit_mask, IN u32 reg_value)
+{
+	u32 val, i = 0, j = 0, bitpos = 0, delay_count = 0;
+
+
+	if (bit_mask == 0x0)
+		return;
+	if (bit_mask == 0xffffffff) {
+		btcoexist->btc_write_4byte(btcoexist, 0x1704,
+					   reg_value); /* put write data */
+
+		/* wait for ready bit before access 0x1700 */
+#if 0
+		do {
+			j++;
+		} while (((btcoexist->btc_read_1byte(btcoexist,
+						     0x1703)&BIT(5)) == 0) &&
+			(j < BT_8822B_2ANT_LTECOEX_INDIRECTREG_ACCESS_TIMEOUT));
+#endif
+
+		while (1) {
+			if ((btcoexist->btc_read_1byte(btcoexist, 0x1703)&BIT(5)) == 0) {
+				delay_ms(50);
+				delay_count++;
+				if (delay_count >= 10) {
+					delay_count = 0;
+					break;
+}
+			} else
+				break;
+		}
+		btcoexist->btc_write_4byte(btcoexist, 0x1700,
+					   0xc00F0000 | reg_addr);
+	} else {
+		for (i = 0; i <= 31; i++) {
+			if (((bit_mask >> i) & 0x1) == 0x1) {
+				bitpos = i;
+				break;
+			}
+		}
+
+		/* read back register value before write */
+		val = halbtc8822b2ant_ltecoex_indirect_read_reg(btcoexist,
+				reg_addr);
+		val = (val & (~bit_mask)) | (reg_value << bitpos);
+
+		btcoexist->btc_write_4byte(btcoexist, 0x1704,
+					   val); /* put write data */
+
+		/* wait for ready bit before access 0x7c0		 */
+#if 0
+		do {
+			j++;
+		} while (((btcoexist->btc_read_1byte(btcoexist,
+						     0x1703)&BIT(5)) == 0) &&
+			(j < BT_8822B_2ANT_LTECOEX_INDIRECTREG_ACCESS_TIMEOUT));
+#endif
+
+		while (1) {
+			if ((btcoexist->btc_read_1byte(btcoexist, 0x1703)&BIT(5)) == 0) {
+				delay_ms(50);
+				delay_count++;
+				if (delay_count >= 10) {
+					delay_count = 0;
+					break;
+				}
+			} else
+				break;
+		}
+		btcoexist->btc_write_4byte(btcoexist, 0x1700,
+					   0xc00F0000 | reg_addr);
+
+	}
+
+}
+
+void halbtc8822b2ant_ltecoex_enable(IN struct btc_coexist *btcoexist,
+				    IN boolean enable)
+{
+	u8 val;
+
+	val = (enable) ? 1 : 0;
+	halbtc8822b2ant_ltecoex_indirect_write_reg(btcoexist, 0x38, 0x80,
+			val);  /* 0x38[7] */
+
+}
+
+void halbtc8822b2ant_ltecoex_pathcontrol_owner(IN struct btc_coexist *btcoexist,
+		IN boolean wifi_control)
+{
+	u8 val;
+
+	val = (wifi_control) ? 1 : 0;
+	btcoexist->btc_write_1byte_bitmask(btcoexist, 0x73, 0x4,
+					   val); /* 0x70[26] */
+
+}
+
+void halbtc8822b2ant_ltecoex_set_gnt_bt(IN struct btc_coexist *btcoexist,
+			IN u8 control_block, IN boolean sw_control, IN u8 state)
+{
+	u32 val = 0, bit_mask;
+
+	state = state & 0x1;
+	val = (sw_control) ? ((state << 1) | 0x1) : 0;
+
+	switch (control_block) {
+	case BT_8822B_2ANT_GNT_BLOCK_RFC_BB:
+	default:
+		bit_mask = 0xc000;
+		halbtc8822b2ant_ltecoex_indirect_write_reg(btcoexist,
+				0x38, bit_mask, val); /* 0x38[15:14] */
+		bit_mask = 0x0c00;
+		halbtc8822b2ant_ltecoex_indirect_write_reg(btcoexist,
+				0x38, bit_mask, val); /* 0x38[11:10]						 */
+		break;
+	case BT_8822B_2ANT_GNT_BLOCK_RFC:
+		bit_mask = 0xc000;
+		halbtc8822b2ant_ltecoex_indirect_write_reg(btcoexist,
+				0x38, bit_mask, val); /* 0x38[15:14] */
+		break;
+	case BT_8822B_2ANT_GNT_BLOCK_BB:
+		bit_mask = 0x0c00;
+		halbtc8822b2ant_ltecoex_indirect_write_reg(btcoexist,
+				0x38, bit_mask, val); /* 0x38[11:10] */
+		break;
+
+	}
+
+}
+
+void halbtc8822b2ant_ltecoex_set_gnt_wl(IN struct btc_coexist *btcoexist,
+			IN u8 control_block, IN boolean sw_control, IN u8 state)
+{
+	u32 val = 0, bit_mask;
+
+	state = state & 0x1;
+	val = (sw_control) ? ((state << 1) | 0x1) : 0;
+
+	switch (control_block) {
+	case BT_8822B_2ANT_GNT_BLOCK_RFC_BB:
+	default:
+		bit_mask = 0x3000;
+		halbtc8822b2ant_ltecoex_indirect_write_reg(btcoexist,
+				0x38, bit_mask, val); /* 0x38[13:12] */
+		bit_mask = 0x0300;
+		halbtc8822b2ant_ltecoex_indirect_write_reg(btcoexist,
+				0x38, bit_mask, val); /* 0x38[9:8]						 */
+		break;
+	case BT_8822B_2ANT_GNT_BLOCK_RFC:
+		bit_mask = 0x3000;
+		halbtc8822b2ant_ltecoex_indirect_write_reg(btcoexist,
+				0x38, bit_mask, val); /* 0x38[13:12] */
+		break;
+	case BT_8822B_2ANT_GNT_BLOCK_BB:
+		bit_mask = 0x0300;
+		halbtc8822b2ant_ltecoex_indirect_write_reg(btcoexist,
+				0x38, bit_mask, val); /* 0x38[9:8] */
+		break;
+
+	}
+
+}
+
+void halbtc8822b2ant_ltecoex_set_coex_table(IN struct btc_coexist *btcoexist,
+		IN u8 table_type, IN u16 table_content)
+{
+	u16 reg_addr = 0x0000;
+
+	switch (table_type) {
+	case BT_8822B_2ANT_CTT_WL_VS_LTE:
+		reg_addr = 0xa0;
+		break;
+	case BT_8822B_2ANT_CTT_BT_VS_LTE:
+		reg_addr = 0xa4;
+		break;
+	}
+
+	if (reg_addr != 0x0000)
+		halbtc8822b2ant_ltecoex_indirect_write_reg(btcoexist, reg_addr,
+			0xffff, table_content); /* 0xa0[15:0] or 0xa4[15:0] */
+
+
+}
+
+
+void halbtc8822b2ant_ltecoex_set_break_table(IN struct btc_coexist *btcoexist,
+		IN u8 table_type, IN u8 table_content)
+{
+	u16 reg_addr = 0x0000;
+
+	switch (table_type) {
+	case BT_8822B_2ANT_LBTT_WL_BREAK_LTE:
+		reg_addr = 0xa8;
+		break;
+	case BT_8822B_2ANT_LBTT_BT_BREAK_LTE:
+		reg_addr = 0xac;
+		break;
+	case BT_8822B_2ANT_LBTT_LTE_BREAK_WL:
+		reg_addr = 0xb0;
+		break;
+	case BT_8822B_2ANT_LBTT_LTE_BREAK_BT:
+		reg_addr = 0xb4;
+		break;
+	}
+
+	if (reg_addr != 0x0000)
+		halbtc8822b2ant_ltecoex_indirect_write_reg(btcoexist, reg_addr,
+			0xff, table_content); /* 0xa8[15:0] or 0xb4[15:0] */
+
+
+}
+
+
+void halbtc8822b2ant_set_coex_table(IN struct btc_coexist *btcoexist,
+	    IN u32 val0x6c0, IN u32 val0x6c4, IN u32 val0x6c8, IN u8 val0x6cc)
+{
+	btcoexist->btc_write_4byte(btcoexist, 0x6c0, val0x6c0);
+
+	btcoexist->btc_write_4byte(btcoexist, 0x6c4, val0x6c4);
+
+	btcoexist->btc_write_4byte(btcoexist, 0x6c8, val0x6c8);
+
+	btcoexist->btc_write_1byte(btcoexist, 0x6cc, val0x6cc);
+}
+
+void halbtc8822b2ant_coex_table(IN struct btc_coexist *btcoexist,
+			IN boolean force_exec, IN u32 val0x6c0, IN u32 val0x6c4,
+				IN u32 val0x6c8, IN u8 val0x6cc)
+{
+	coex_dm->cur_val0x6c0 = val0x6c0;
+	coex_dm->cur_val0x6c4 = val0x6c4;
+	coex_dm->cur_val0x6c8 = val0x6c8;
+	coex_dm->cur_val0x6cc = val0x6cc;
+
+	if (!force_exec) {
+		if ((coex_dm->pre_val0x6c0 == coex_dm->cur_val0x6c0) &&
+		    (coex_dm->pre_val0x6c4 == coex_dm->cur_val0x6c4) &&
+		    (coex_dm->pre_val0x6c8 == coex_dm->cur_val0x6c8) &&
+		    (coex_dm->pre_val0x6cc == coex_dm->cur_val0x6cc))
+			return;
+	}
+	halbtc8822b2ant_set_coex_table(btcoexist, val0x6c0, val0x6c4, val0x6c8,
+				       val0x6cc);
+
+	coex_dm->pre_val0x6c0 = coex_dm->cur_val0x6c0;
+	coex_dm->pre_val0x6c4 = coex_dm->cur_val0x6c4;
+	coex_dm->pre_val0x6c8 = coex_dm->cur_val0x6c8;
+	coex_dm->pre_val0x6cc = coex_dm->cur_val0x6cc;
+}
+
+void halbtc8822b2ant_coex_table_with_type(IN struct btc_coexist *btcoexist,
+		IN boolean force_exec, IN u8 type)
+{
+	u32	break_table;
+	u8	select_table;
+
+	coex_sta->coex_table_type = type;
+
+	if (coex_sta->concurrent_rx_mode_on == true) {
+		break_table = 0xf0ffffff;  /* set WL hi-pri can break BT */
+		select_table =
+			0x3;		/* 0xb/0x3,set Tx response = Hi-Pri/LO-Pri (ex: Transmitting ACK,BA,CTS) */
+	} else {
+		break_table = 0xffffff;
+		select_table = 0x3;
+	}
+
+	switch (type) {
+	case 0:
+		halbtc8822b2ant_coex_table(btcoexist, force_exec,
+			   0x55555555, 0x55555555, break_table, select_table);
+		break;
+	case 1:
+		halbtc8822b2ant_coex_table(btcoexist, force_exec,
+			   0x55555555, 0x5a5a5a5a, break_table, select_table);
+		break;
+	case 2:
+		halbtc8822b2ant_coex_table(btcoexist, force_exec,
+			   0x5a5a5a5a, 0x5a5a5a5a, break_table, select_table);
+		break;
+	case 3:
+		halbtc8822b2ant_coex_table(btcoexist, force_exec,
+			   0x5a5a5a5a, 0x5a5a5a5a, break_table, select_table);
+		break;
+	case 4:
+		halbtc8822b2ant_coex_table(btcoexist, force_exec,
+			   0x55555555, 0x5a5a5a5a, break_table, select_table);
+		break;
+	case 5:
+		halbtc8822b2ant_coex_table(btcoexist, force_exec,
+			   0x55555555, 0x5a5a5a5a, break_table, select_table);
+		break;
+	case 6:
+		halbtc8822b2ant_coex_table(btcoexist, force_exec,
+			   0x55555555, 0xaaaa5aaa, break_table, select_table);
+		break;
+	case 7:
+		halbtc8822b2ant_coex_table(btcoexist, force_exec,
+			   0xa5555555, 0xaa5a5a5a, break_table, select_table);
+		break;
+	case 8:
+		halbtc8822b2ant_coex_table(btcoexist, force_exec,
+			   0x55555555, 0x5a5a5a5a, break_table, select_table);
+		break;
+	case 9:
+		halbtc8822b2ant_coex_table(btcoexist, force_exec,
+			   0x55555555, 0xaaaa555a, break_table, select_table);
+		break;
+	case 10:
+		halbtc8822b2ant_coex_table(btcoexist, force_exec,
+			   0x55555555, 0xaaaa5aaa, break_table, select_table);
+		break;
+	case 11:
+		halbtc8822b2ant_coex_table(btcoexist, force_exec,
+			   0x55555555, 0xaaaaa5aa, break_table, select_table);
+		break;
+	case 12:
+		halbtc8822b2ant_coex_table(btcoexist, force_exec,
+			   0x55555555, 0xaaaa55aa, break_table, select_table);
+		break;
+	default:
+		break;
+	}
+}
+
+void halbtc8822b2ant_set_fw_ignore_wlan_act(IN struct btc_coexist *btcoexist,
+		IN boolean enable)
+{
+	u8			h2c_parameter[1] = {0};
+	u32	RTL97F_8822B = 0;
+
+	if (RTL97F_8822B == true)
+			return;
+
+	if (enable)
+		h2c_parameter[0] |= BIT(0);		/* function enable */
+
+	btcoexist->btc_fill_h2c(btcoexist, 0x63, 1, h2c_parameter);
+}
+
+void halbtc8822b2ant_ignore_wlan_act(IN struct btc_coexist *btcoexist,
+				     IN boolean force_exec, IN boolean enable)
+{
+	coex_dm->cur_ignore_wlan_act = enable;
+
+	if (!force_exec) {
+		if (coex_dm->pre_ignore_wlan_act ==
+		    coex_dm->cur_ignore_wlan_act)
+			return;
+	}
+	halbtc8822b2ant_set_fw_ignore_wlan_act(btcoexist, enable);
+
+	coex_dm->pre_ignore_wlan_act = coex_dm->cur_ignore_wlan_act;
+}
+
+void halbtc8822b2ant_set_lps_rpwm(IN struct btc_coexist *btcoexist,
+				  IN u8 lps_val, IN u8 rpwm_val)
+{
+	u8	lps = lps_val;
+	u8	rpwm = rpwm_val;
+
+	btcoexist->btc_set(btcoexist, BTC_SET_U1_LPS_VAL, &lps);
+	btcoexist->btc_set(btcoexist, BTC_SET_U1_RPWM_VAL, &rpwm);
+}
+
+void halbtc8822b2ant_lps_rpwm(IN struct btc_coexist *btcoexist,
+		      IN boolean force_exec, IN u8 lps_val, IN u8 rpwm_val)
+{
+	coex_dm->cur_lps = lps_val;
+	coex_dm->cur_rpwm = rpwm_val;
+
+	if (!force_exec) {
+		if ((coex_dm->pre_lps == coex_dm->cur_lps) &&
+		    (coex_dm->pre_rpwm == coex_dm->cur_rpwm))
+			return;
+	}
+	halbtc8822b2ant_set_lps_rpwm(btcoexist, lps_val, rpwm_val);
+
+	coex_dm->pre_lps = coex_dm->cur_lps;
+	coex_dm->pre_rpwm = coex_dm->cur_rpwm;
+}
+
+void halbtc8822b2ant_ps_tdma_check_for_power_save_state(
+	IN struct btc_coexist *btcoexist, IN boolean new_ps_state)
+{
+	u8	lps_mode = 0x0;
+	u8	h2c_parameter[5] = {0, 0, 0, 0x40, 0};
+	u32	RTL97F_8822B = 0;
+
+	if (RTL97F_8822B == true)
+		return;
+
+	btcoexist->btc_get(btcoexist, BTC_GET_U1_LPS_MODE, &lps_mode);
+
+	if (lps_mode) {	/* already under LPS state */
+		if (new_ps_state) {
+			/* keep state under LPS, do nothing. */
+		} else {
+			/* will leave LPS state, turn off psTdma first */
+			/*halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, false,
+						8); */
+			btcoexist->btc_fill_h2c(btcoexist, 0x60, 5,
+						h2c_parameter);
+		}
+	} else {					/* NO PS state */
+		if (new_ps_state) {
+			/* will enter LPS state, turn off psTdma first */
+			/*halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, false,
+						8);*/
+			btcoexist->btc_fill_h2c(btcoexist, 0x60, 5,
+						h2c_parameter);
+		} else {
+			/* keep state under NO PS state, do nothing. */
+		}
+	}
+}
+
+void halbtc8822b2ant_power_save_state(IN struct btc_coexist *btcoexist,
+			      IN u8 ps_type, IN u8 lps_val, IN u8 rpwm_val)
+{
+	boolean		low_pwr_disable = false;
+
+	switch (ps_type) {
+	case BTC_PS_WIFI_NATIVE:
+		/* recover to original 32k low power setting */
+		low_pwr_disable = false;
+		btcoexist->btc_set(btcoexist,
+				   BTC_SET_ACT_DISABLE_LOW_POWER,
+				   &low_pwr_disable);
+		btcoexist->btc_set(btcoexist, BTC_SET_ACT_NORMAL_LPS,
+				   NULL);
+		coex_sta->force_lps_on = false;
+		break;
+	case BTC_PS_LPS_ON:
+		halbtc8822b2ant_ps_tdma_check_for_power_save_state(
+			btcoexist, true);
+		halbtc8822b2ant_lps_rpwm(btcoexist, NORMAL_EXEC,
+					 lps_val, rpwm_val);
+		/* when coex force to enter LPS, do not enter 32k low power. */
+		low_pwr_disable = true;
+		btcoexist->btc_set(btcoexist,
+				   BTC_SET_ACT_DISABLE_LOW_POWER,
+				   &low_pwr_disable);
+		/* power save must executed before psTdma.			 */
+		btcoexist->btc_set(btcoexist, BTC_SET_ACT_ENTER_LPS,
+				   NULL);
+		coex_sta->force_lps_on = true;
+		break;
+	case BTC_PS_LPS_OFF:
+		halbtc8822b2ant_ps_tdma_check_for_power_save_state(
+			btcoexist, false);
+		btcoexist->btc_set(btcoexist, BTC_SET_ACT_LEAVE_LPS,
+				   NULL);
+		coex_sta->force_lps_on = false;
+		break;
+	default:
+		break;
+	}
+}
+
+
+
+void halbtc8822b2ant_set_fw_pstdma(IN struct btc_coexist *btcoexist,
+	   IN u8 byte1, IN u8 byte2, IN u8 byte3, IN u8 byte4, IN u8 byte5)
+{
+	u8			h2c_parameter[5] = {0};
+	u8			real_byte1 = byte1, real_byte5 = byte5;
+	boolean			ap_enable = false;
+
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_AP_MODE_ENABLE,
+			   &ap_enable);
+
+	if (ap_enable) {
+		if (byte1 & BIT(4) && !(byte1 & BIT(5))) {
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				    "[BTCoex], FW for AP mode\n");
+			BTC_TRACE(trace_buf);
+			real_byte1 &= ~BIT(4);
+			real_byte1 |= BIT(5);
+
+			real_byte5 |= BIT(5);
+			real_byte5 &= ~BIT(6);
+
+			halbtc8822b2ant_power_save_state(btcoexist,
+						 BTC_PS_WIFI_NATIVE, 0x0,
+							 0x0);
+		}
+	} else if (byte1 & BIT(4) && !(byte1 & BIT(5))) {
+
+		halbtc8822b2ant_power_save_state(
+			btcoexist, BTC_PS_LPS_ON, 0x50,
+			0x4);
+	} else {
+		halbtc8822b2ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE,
+						 0x0,
+						 0x0);
+	}
+
+
+	h2c_parameter[0] = real_byte1;
+	h2c_parameter[1] = byte2;
+	h2c_parameter[2] = byte3;
+	h2c_parameter[3] = byte4;
+	h2c_parameter[4] = real_byte5;
+
+	coex_dm->ps_tdma_para[0] = real_byte1;
+	coex_dm->ps_tdma_para[1] = byte2;
+	coex_dm->ps_tdma_para[2] = byte3;
+	coex_dm->ps_tdma_para[3] = byte4;
+	coex_dm->ps_tdma_para[4] = real_byte5;
+
+	btcoexist->btc_fill_h2c(btcoexist, 0x60, 5, h2c_parameter);
+}
+
+void halbtc8822b2ant_ps_tdma(IN struct btc_coexist *btcoexist,
+		     IN boolean force_exec, IN boolean turn_on, IN u8 type)
+{
+
+	static u8			psTdmaByte4Modify = 0x0, pre_psTdmaByte4Modify = 0x0;
+	struct  btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
+
+
+	coex_dm->cur_ps_tdma_on = turn_on;
+	coex_dm->cur_ps_tdma = type;
+
+	/* 0x778 = 0x1 at wifi slot (no blocking BT Low-Pri pkts) */
+	if ((bt_link_info->slave_role) && (bt_link_info->a2dp_exist))
+		psTdmaByte4Modify = 0x1;
+	else
+		psTdmaByte4Modify = 0x0;
+
+	if (pre_psTdmaByte4Modify != psTdmaByte4Modify) {
+
+		force_exec = true;
+		pre_psTdmaByte4Modify = psTdmaByte4Modify;
+	}
+
+	if (!force_exec) {
+		if ((coex_dm->pre_ps_tdma_on == coex_dm->cur_ps_tdma_on) &&
+		    (coex_dm->pre_ps_tdma == coex_dm->cur_ps_tdma))
+			return;
+	}
+
+	if (coex_dm->cur_ps_tdma_on) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], ********** TDMA(on, %d) **********\n",
+			    coex_dm->cur_ps_tdma);
+		BTC_TRACE(trace_buf);
+
+		btcoexist->btc_write_1byte_bitmask(btcoexist, 0x550, 0x8,
+					   0x1);  /* enable TBTT nterrupt */
+	} else {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], ********** TDMA(off, %d) **********\n",
+			    coex_dm->cur_ps_tdma);
+		BTC_TRACE(trace_buf);
+	}
+
+
+	if (turn_on) {
+		switch (type) {
+		case 1:
+			halbtc8822b2ant_set_fw_pstdma(btcoexist, 0xe3,
+						      0x10, 0x03, 0xf1,
+						      0x54 | psTdmaByte4Modify);
+			break;
+		case 2:
+		default:
+			halbtc8822b2ant_set_fw_pstdma(btcoexist, 0xe3,
+						      0x35, 0x03, 0x71,
+						      0x11 | psTdmaByte4Modify);
+			break;
+		case 3:
+			halbtc8822b2ant_set_fw_pstdma(btcoexist, 0xe3,
+						      0x3a, 0x3, 0xf1,
+						      0x10 | psTdmaByte4Modify);
+			break;
+		case 4:
+			halbtc8822b2ant_set_fw_pstdma(btcoexist, 0xe3,
+						      0x21, 0x3, 0xf1,
+						      0x10 | psTdmaByte4Modify);
+			break;
+		case 5:
+			halbtc8822b2ant_set_fw_pstdma(btcoexist, 0xe3,
+						      0x25, 0x3, 0xf1,
+						      0x10 | psTdmaByte4Modify);
+			break;
+		case 6:
+			halbtc8822b2ant_set_fw_pstdma(btcoexist, 0xe3,
+						      0x10, 0x3, 0xf1,
+						      0x10 | psTdmaByte4Modify);
+			break;
+		case 7:
+			halbtc8822b2ant_set_fw_pstdma(btcoexist, 0xe3,
+						      0x20, 0x3, 0xf1,
+						      0x10 | psTdmaByte4Modify);
+			break;
+		case 11:
+			halbtc8822b2ant_set_fw_pstdma(btcoexist, 0xe3,
+						      0x30, 0x03, 0x71,
+						      0x10 | psTdmaByte4Modify);
+			break;
+		case 12:
+			halbtc8822b2ant_set_fw_pstdma(btcoexist, 0xe3,
+						      0x21, 0x03, 0x71,
+						      0x11 | psTdmaByte4Modify);
+			break;
+		case 13:
+			halbtc8822b2ant_set_fw_pstdma(btcoexist, 0xe3,
+						      0x1c, 0x03, 0x71,
+						      0x10 | psTdmaByte4Modify);
+			break;
+		case 14:
+			halbtc8822b2ant_set_fw_pstdma(btcoexist, 0xe3,
+						      0x30, 0x03, 0x71,
+						      0x11);
+			break;
+		case 51:
+			halbtc8822b2ant_set_fw_pstdma(btcoexist, 0xe3,
+						      0x10, 0x03, 0xf1,
+						      0x10 | psTdmaByte4Modify);
+			break;
+		case 101:
+			halbtc8822b2ant_set_fw_pstdma(btcoexist, 0xd3,
+						      0x10, 0x03, 0x70,
+						      0x54 | psTdmaByte4Modify);
+			break;
+		case 102:
+			halbtc8822b2ant_set_fw_pstdma(btcoexist, 0xe3,
+						      0x35, 0x03, 0x71,
+						      0x11 | psTdmaByte4Modify);
+			break;
+		case 103:
+			halbtc8822b2ant_set_fw_pstdma(btcoexist, 0xd3,
+						      0x3a, 0x3, 0x70,
+						      0x50 | psTdmaByte4Modify);
+			break;
+		case 104:
+			halbtc8822b2ant_set_fw_pstdma(btcoexist, 0xd3,
+						      0x21, 0x3, 0x70,
+						      0x50 | psTdmaByte4Modify);
+			break;
+		case 105:
+			halbtc8822b2ant_set_fw_pstdma(btcoexist, 0xd3,
+						      0x25, 0x3, 0x70,
+						      0x50 | psTdmaByte4Modify);
+			break;
+		case 106:
+			halbtc8822b2ant_set_fw_pstdma(btcoexist, 0xd3,
+						      0x10, 0x3, 0x70,
+						      0x50 | psTdmaByte4Modify);
+			break;
+		case 107:
+			halbtc8822b2ant_set_fw_pstdma(btcoexist, 0xd3,
+						      0x20, 0x3, 0x70,
+						      0x50 | psTdmaByte4Modify);
+			break;
+		case 151:
+			halbtc8822b2ant_set_fw_pstdma(btcoexist, 0xd3,
+						      0x10, 0x03, 0x70,
+						      0x50 | psTdmaByte4Modify);
+			break;
+		}
+	} else {
+		/* disable PS tdma */
+		switch (type) {
+		case 0:
+			halbtc8822b2ant_set_fw_pstdma(btcoexist, 0x0,
+						      0x0, 0x0, 0x40, 0x0);
+			break;
+		case 1:
+			halbtc8822b2ant_set_fw_pstdma(btcoexist, 0x0,
+						      0x0, 0x0, 0x48, 0x0);
+			break;
+		default:
+			halbtc8822b2ant_set_fw_pstdma(btcoexist, 0x0,
+						      0x0, 0x0, 0x40, 0x0);
+			break;
+		}
+	}
+
+	/* update pre state */
+	coex_dm->pre_ps_tdma_on = coex_dm->cur_ps_tdma_on;
+	coex_dm->pre_ps_tdma = coex_dm->cur_ps_tdma;
+}
+
+void halbtc8822b2ant_set_ext_band_switch(IN struct btc_coexist *btcoexist,
+		IN boolean force_exec, IN u8 pos_type)
+{
+
+#if 0
+	boolean	switch_polatiry_inverse = false;
+	u8		regval_0xcb6;
+	u32		u32tmp1 = 0, u32tmp2 = 0;
+
+	if (!rfe_type->ext_band_switch_exist)
+		return;
+
+	coex_dm->cur_ext_band_switch_status = pos_type;
+
+	if (!force_exec) {
+		if (coex_dm->pre_ext_band_switch_status ==
+		    coex_dm->cur_ext_band_switch_status)
+			return;
+	}
+
+	coex_dm->pre_ext_band_switch_status =
+		coex_dm->cur_ext_band_switch_status;
+
+	/* swap control polarity if use different switch control polarity*/
+	switch_polatiry_inverse = (rfe_type->ext_band_switch_ctrl_polarity == 1
+		   ? ~switch_polatiry_inverse : switch_polatiry_inverse);
+
+	/*swap control polarity for WL_A, default polarity 0xcb4[21] = 0 && 0xcb4[23] = 1 is for WL_G */
+	switch_polatiry_inverse = (pos_type ==
+		BT_8822B_2ANT_EXT_BAND_SWITCH_TO_WLA ? ~switch_polatiry_inverse
+				   : switch_polatiry_inverse);
+
+	regval_0xcb6 =  btcoexist->btc_read_1byte(btcoexist, 0xcb6);
+
+	/* for normal switch polrity, 0xcb4[21] =1 && 0xcb4[23] = 0 for WL_A, vice versa */
+	regval_0xcb6 = (switch_polatiry_inverse == 1 ? ((regval_0xcb6 & (~(BIT(
+		7)))) | BIT(5)) : ((regval_0xcb6 & (~(BIT(5)))) | BIT(7)));
+
+	btcoexist->btc_write_1byte_bitmask(btcoexist, 0xcb6, 0xff,
+					   regval_0xcb6);
+
+	u32tmp1 = btcoexist->btc_read_4byte(btcoexist, 0xcb0);
+	u32tmp2 = btcoexist->btc_read_4byte(btcoexist, 0xcb4);
+
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+		"[BTCoex], ********** (After Ext Band switch setup) 0xcb0 = 0x%08x, 0xcb4 = 0x%08x**********\n",
+		    u32tmp1, u32tmp2);
+	BTC_TRACE(trace_buf);
+#endif
+
+}
+
+/*anttenna control by bb mac bt antdiv pta to write 0x4c 0xcb4,0xcbd*/
+void halbtc8822b2ant_set_ext_ant_switch(IN struct btc_coexist *btcoexist,
+			IN boolean force_exec, IN u8 ctrl_type, IN u8 pos_type)
+{
+
+	struct  btc_board_info	*board_info = &btcoexist->board_info;
+	boolean	switch_polatiry_inverse = false;
+	u8		regval_0xcbc = 0, regval_0x64;
+	u32		u32tmp1 = 0, u32tmp2 = 0, u32tmp3 = 0;
+
+	if (!rfe_type->ext_ant_switch_exist)
+		return;
+
+	coex_dm->cur_ext_ant_switch_status = (ctrl_type << 8)  + pos_type;
+
+	if (!force_exec) {
+		if (coex_dm->pre_ext_ant_switch_status ==
+		    coex_dm->cur_ext_ant_switch_status)
+			return;
+}
+	coex_dm->pre_ext_ant_switch_status = coex_dm->cur_ext_ant_switch_status;
+	/*
+	switch (pos_type) {
+	default:
+	case BT_8822B_2ANT_EXT_ANT_SWITCH_MAIN_TO_BT:
+	case BT_8822B_2ANT_EXT_ANT_SWITCH_MAIN_TO_NOCARE:
+		break;
+	case BT_8822B_2ANT_EXT_ANT_SWITCH_MAIN_TO_WLG:
+		break;
+	case BT_8822B_2ANT_EXT_ANT_SWITCH_MAIN_TO_WLA:
+		break;
+	}
+*/
+	if (board_info->ant_div_cfg)
+		/*ctrl_type = BT_8822B_2ANT_EXT_ANT_SWITCH_CTRL_BY_ANTDIV;*/
+
+	/* Ext switch buffer mux */
+		btcoexist->btc_write_1byte(btcoexist, 0x974, 0xff);
+		btcoexist->btc_write_1byte_bitmask(btcoexist, 0x1991, 0x3, 0x0);
+		btcoexist->btc_write_1byte_bitmask(btcoexist, 0xcbe, 0x8, 0x0);
+
+
+	switch (ctrl_type) {
+	default:
+	case BT_8822B_2ANT_EXT_ANT_SWITCH_CTRL_BY_BBSW:
+		btcoexist->btc_write_1byte_bitmask(btcoexist, 0x4e,
+					   0x80, 0x0);  /*  0x4c[23] = 0 */
+		btcoexist->btc_write_1byte_bitmask(btcoexist, 0x4f,
+					   0x01, 0x1);  /* 0x4c[24] = 1 */
+		btcoexist->btc_write_1byte_bitmask(btcoexist, 0xcb4,
+			0xff, 0x77);	/* BB SW, DPDT use RFE_ctrl8 and RFE_ctrl9 as conctrol pin */
+
+		btcoexist->btc_write_1byte_bitmask(btcoexist, 0xcbd,
+						   0x03, 01);
+
+		break;
+	case BT_8822B_2ANT_EXT_ANT_SWITCH_CTRL_BY_PTA:
+		btcoexist->btc_write_1byte_bitmask(btcoexist, 0x4e,
+					   0x80, 0x0);  /* 0x4c[23] = 0 */
+		btcoexist->btc_write_1byte_bitmask(btcoexist, 0x4f,
+					   0x01, 0x1);  /* 0x4c[24] = 1 */
+		btcoexist->btc_write_1byte_bitmask(btcoexist, 0xcb4,
+			0xff, 0x66);	/* PTA,  DPDT use RFE_ctrl8 and RFE_ctrl9 as conctrol pin */
+
+		regval_0xcbc = (switch_polatiry_inverse == false ?
+			0x2 : 0x1);     /* 0xcb4[29:28] = 2b'10 for no switch_polatiry_inverse, DPDT_SEL_N =1, DPDT_SEL_P =0  @ GNT_BT=1 */
+		btcoexist->btc_write_1byte_bitmask(btcoexist, 0xcbc,
+						   0x03, regval_0xcbc);
+
+		break;
+	case BT_8822B_2ANT_EXT_ANT_SWITCH_CTRL_BY_ANTDIV:
+		btcoexist->btc_write_1byte_bitmask(btcoexist, 0x4e,
+					   0x80, 0x0);  /* 0x4c[23] = 0 */
+		btcoexist->btc_write_1byte_bitmask(btcoexist, 0x4f,
+					   0x01, 0x1);/* 0x4c[24] = 1 */
+btcoexist->btc_write_1byte_bitmask(btcoexist, 0xcb4, 0xff, 0x88);
+break;
+	case BT_8822B_2ANT_EXT_ANT_SWITCH_CTRL_BY_MAC:
+		btcoexist->btc_write_1byte_bitmask(btcoexist, 0x4e,
+					   0x80, 0x1);  /*  0x4c[23] = 1 */
+
+		regval_0x64 = (switch_polatiry_inverse == false ?  0x0 :
+			0x1);     /* 0x64[0] = 1b'0 for no switch_polatiry_inverse, DPDT_SEL_N =1, DPDT_SEL_P =0 */
+		btcoexist->btc_write_1byte_bitmask(btcoexist, 0x64, 0x1,
+						   regval_0x64);
+		break;
+	case BT_8822B_2ANT_EXT_ANT_SWITCH_CTRL_BY_BT:
+		btcoexist->btc_write_1byte_bitmask(btcoexist, 0x4e,
+					   0x80, 0x0);  /* 0x4c[23] = 0 */
+		btcoexist->btc_write_1byte_bitmask(btcoexist, 0x4f,
+					   0x01, 0x0);  /* 0x4c[24] = 0 */
+
+		/* no  setup required, because  antenna switch control value by BT vendor 0x1c[1:0] */
+		break;
+	}
+
+	/* PAPE, LNA_ON control by BT  while WLAN off for current leakage issue */
+	if (ctrl_type == BT_8822B_2ANT_EXT_ANT_SWITCH_CTRL_BY_BT) {
+		btcoexist->btc_write_1byte_bitmask(btcoexist, 0x67, 0x20,
+					   0x0);  /* PAPE   0x64[29] = 0 */
+		btcoexist->btc_write_1byte_bitmask(btcoexist, 0x67, 0x10,
+					   0x0);  /* LNA_ON 0x64[28] = 0 */
+	} else {
+		btcoexist->btc_write_1byte_bitmask(btcoexist, 0x67, 0x20,
+					   0x1);  /* PAPE   0x64[29] = 1 */
+		btcoexist->btc_write_1byte_bitmask(btcoexist, 0x67, 0x10,
+					   0x1);  /* LNA_ON 0x64[28] = 1 */
+	}
+
+#if BT_8822B_2ANT_COEX_DBG
+
+	u32tmp1 = btcoexist->btc_read_4byte(btcoexist, 0xcb4);
+	u32tmp2 = btcoexist->btc_read_4byte(btcoexist, 0x4c);
+	u32tmp3 = btcoexist->btc_read_4byte(btcoexist, 0x64) & 0xff;
+
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+		"[BTCoex], (After Ext Ant switch setup) 0xcb4 = 0x%08x, 0x4c = 0x%08x, 0x64= 0x%02x\n",
+		    u32tmp1, u32tmp2, u32tmp3);
+	BTC_TRACE(trace_buf);
+#endif
+
+
+
+}
+/*rf4 type by efuse , and for ant at main aux inverse use , because is 2x2 ,and control types are the same ,does not need */
+void halbtc8822b2ant_set_rfe_type(IN struct btc_coexist *btcoexist)
+{
+
+	struct  btc_board_info *board_info = &btcoexist->board_info;
+
+
+	rfe_type->ext_band_switch_exist = false;
+	rfe_type->ext_band_switch_type =
+		BT_8822B_2ANT_EXT_BAND_SWITCH_USE_SPDT;     /* SPDT; */
+	rfe_type->ext_band_switch_ctrl_polarity = 0;
+	/* Ext switch buffer mux */
+		btcoexist->btc_write_1byte(btcoexist, 0x974, 0xff);
+		btcoexist->btc_write_1byte_bitmask(btcoexist, 0x1991, 0x3, 0x0);
+		btcoexist->btc_write_1byte_bitmask(btcoexist, 0xcbe, 0x8, 0x0);
+
+	if (rfe_type->ext_band_switch_exist) {
+
+		/* band switch use RFE_ctrl1 (pin name: PAPE_A) and RFE_ctrl3 (pin name: LNAON_A) */
+
+		/* set RFE_ctrl1 as software control */
+		btcoexist->btc_write_1byte_bitmask(btcoexist, 0xcb0, 0xf0, 0x7);
+
+		/* set RFE_ctrl3 as software control */
+		btcoexist->btc_write_1byte_bitmask(btcoexist, 0xcb1, 0xf0, 0x7);
+
+	}
+
+
+	/* the following setup should be got from Efuse in the future */
+	rfe_type->rfe_module_type = board_info->rfe_type;
+
+	rfe_type->ext_ant_switch_ctrl_polarity = 0;
+
+	switch (rfe_type->rfe_module_type) {
+	case 0:
+	default:
+		rfe_type->ext_ant_switch_exist = true;
+		rfe_type->ext_ant_switch_type = BT_8822B_2ANT_EXT_ANT_SWITCH_USE_SPDT;
+		break;
+	case 1:
+		rfe_type->ext_ant_switch_exist = true;
+		rfe_type->ext_ant_switch_type = BT_8822B_2ANT_EXT_ANT_SWITCH_USE_SPDT;
+		break;
+	case 2:
+		rfe_type->ext_ant_switch_exist = true;
+		rfe_type->ext_ant_switch_type = BT_8822B_2ANT_EXT_ANT_SWITCH_USE_SPDT;
+		break;
+	case 3:
+		rfe_type->ext_ant_switch_exist = true;
+		rfe_type->ext_ant_switch_type = BT_8822B_2ANT_EXT_ANT_SWITCH_USE_SPDT;
+		break;
+	case 4:
+		rfe_type->ext_ant_switch_exist = true;
+		rfe_type->ext_ant_switch_type =
+	BT_8822B_2ANT_EXT_ANT_SWITCH_USE_SPDT;
+		break;
+	case 5:
+		rfe_type->ext_ant_switch_exist = true;
+		rfe_type->ext_ant_switch_type = BT_8822B_2ANT_EXT_ANT_SWITCH_USE_SPDT;
+		break;
+	case 6:
+		rfe_type->ext_ant_switch_exist = true;
+		rfe_type->ext_ant_switch_type = BT_8822B_2ANT_EXT_ANT_SWITCH_USE_SPDT;
+		break;
+	case 7:
+		rfe_type->ext_ant_switch_exist = true;
+rfe_type->ext_ant_switch_type = BT_8822B_2ANT_EXT_ANT_SWITCH_USE_SPDT;
+		break;
+	}
+
+#if 0
+
+	if (rfe_type->wlg_Locate_at_btg)
+		halbtc8822b2ant_set_int_block(btcoexist, FORCE_EXEC,
+			      BT_8822B_2ANT_INT_BLOCK_SWITCH_TO_WLG_OF_BTG);
+	else
+		halbtc8822b2ant_set_int_block(btcoexist, FORCE_EXEC,
+			      BT_8822B_2ANT_INT_BLOCK_SWITCH_TO_WLG_OF_WLAG);
+#endif
+
+}
+
+/*set gnt_wl gnt_bt control by sw high low , or hwpta while in power on,ini,wlan off,wlan only ,wl2g non-currrent ,wl2g current,wl5g*/
+void halbtc8822b2ant_set_ant_path(IN struct btc_coexist *btcoexist,
+				  IN u8 ant_pos_type, IN boolean force_exec,
+				  IN u8 phase)
+{
+	struct  btc_board_info *board_info = &btcoexist->board_info;
+	u32			cnt_bt_cal_chk = 0;
+	boolean			is_in_mp_mode = false;
+	u8			u8tmp = 0;
+	u32			u32tmp1 = 0, u32tmp2 = 0, u32tmp3 = 0;
+	u16			u16tmp1 = 0;
+	/* Ext switch buffer mux */
+		btcoexist->btc_write_1byte(btcoexist, 0x974, 0xff);
+		btcoexist->btc_write_1byte_bitmask(btcoexist, 0x1991, 0x3, 0x0);
+		btcoexist->btc_write_1byte_bitmask(btcoexist, 0xcbe, 0x8, 0x0);
+		btcoexist->btc_write_1byte_bitmask(btcoexist, 0x4e,
+					   0x80, 0x0);  /*  0x4c[23] = 0 */
+		btcoexist->btc_write_1byte_bitmask(btcoexist, 0x4f,
+					   0x01, 0x1);  /* 0x4c[24] = 1 */
+
+	coex_dm->cur_ant_pos_type = (ant_pos_type << 8)  + phase;
+
+	if (!force_exec) {
+		if (coex_dm->cur_ant_pos_type == coex_dm->pre_ant_pos_type)
+			return;
+	}
+
+	coex_dm->pre_ant_pos_type = coex_dm->cur_ant_pos_type;
+
+#if BT_8822B_2ANT_COEX_DBG
+	u32tmp1 = halbtc8822b2ant_ltecoex_indirect_read_reg(btcoexist,
+			0x38);
+	u32tmp2 = halbtc8822b2ant_ltecoex_indirect_read_reg(btcoexist,
+			0x54);
+	u8tmp  = btcoexist->btc_read_1byte(btcoexist, 0x73);
+
+	u32tmp3 = btcoexist->btc_read_4byte(btcoexist, 0xcb4);
+
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+		"[BTCoex], (Before Ant Setup) 0xcb4 = 0x%x, 0x73 = 0x%x, 0x38= 0x%x, 0x54= 0x%x\n",
+		    u32tmp3, u8tmp, u32tmp1, u32tmp2);
+	BTC_TRACE(trace_buf);
+#endif
+
+	switch (phase) {
+	case BT_8822B_2ANT_PHASE_COEX_POWERON:
+
+		/* set Path control owner to WL at initial step */
+		halbtc8822b2ant_ltecoex_pathcontrol_owner(btcoexist,
+				BT_8822B_2ANT_PCO_BTSIDE);
+
+		/* set GNT_BT to SW high */
+		halbtc8822b2ant_ltecoex_set_gnt_bt(btcoexist,
+					   BT_8822B_2ANT_GNT_BLOCK_RFC_BB,
+					   BT_8822B_2ANT_GNT_TYPE_CTRL_BY_SW,
+					   BT_8822B_2ANT_SIG_STA_SET_TO_HIGH);
+		/* Set GNT_WL to SW high */
+		halbtc8822b2ant_ltecoex_set_gnt_wl(btcoexist,
+					   BT_8822B_2ANT_GNT_BLOCK_RFC_BB,
+					   BT_8822B_2ANT_GNT_TYPE_CTRL_BY_SW,
+					   BT_8822B_2ANT_SIG_STA_SET_TO_HIGH);
+
+		coex_sta->run_time_state = false;
+
+		break;
+	case BT_8822B_2ANT_PHASE_COEX_INIT:
+		btcoexist->btc_write_1byte_bitmask(btcoexist, 0x4e,
+					   0x80, 0x0);  /*  0x4c[23] = 0 */
+		btcoexist->btc_write_1byte_bitmask(btcoexist, 0x4f,
+					   0x01, 0x1);  /* 0x4c[24] = 1 */
+		/* Disable LTE Coex Function in WiFi side (this should be on if LTE coex is required) */
+		halbtc8822b2ant_ltecoex_enable(btcoexist, 0x0);
+
+		/* GNT_WL_LTE always = 1 (this should be config if LTE coex is required) */
+		halbtc8822b2ant_ltecoex_set_coex_table(
+			btcoexist,
+			BT_8822B_2ANT_CTT_WL_VS_LTE,
+			0xffff);
+
+		/* GNT_BT_LTE always = 1 (this should be config if LTE coex is required) */
+		halbtc8822b2ant_ltecoex_set_coex_table(
+			btcoexist,
+			BT_8822B_2ANT_CTT_BT_VS_LTE,
+			0xffff);
+
+		/* set Path control owner to WL at initial step */
+		halbtc8822b2ant_ltecoex_pathcontrol_owner(
+			btcoexist,
+			BT_8822B_2ANT_PCO_WLSIDE);
+
+		/* set GNT_BT to SW high */
+		halbtc8822b2ant_ltecoex_set_gnt_bt(btcoexist,
+					   BT_8822B_2ANT_GNT_BLOCK_RFC_BB,
+					   BT_8822B_2ANT_GNT_TYPE_CTRL_BY_SW,
+					   BT_8822B_2ANT_SIG_STA_SET_TO_HIGH);
+		/* Set GNT_WL to SW high */
+		halbtc8822b2ant_ltecoex_set_gnt_wl(btcoexist,
+					   BT_8822B_2ANT_GNT_BLOCK_RFC_BB,
+					   BT_8822B_2ANT_GNT_TYPE_CTRL_BY_SW,
+					   BT_8822B_2ANT_SIG_STA_SET_TO_HIGH);
+
+		coex_sta->run_time_state = false;
+
+		break;
+	case BT_8822B_2ANT_PHASE_WLANONLY_INIT:
+		/* Disable LTE Coex Function in WiFi side (this should be on if LTE coex is required) */
+		halbtc8822b2ant_ltecoex_enable(btcoexist, 0x0);
+
+		/* GNT_WL_LTE always = 1 (this should be config if LTE coex is required) */
+		halbtc8822b2ant_ltecoex_set_coex_table(
+			btcoexist,
+			BT_8822B_2ANT_CTT_WL_VS_LTE,
+			0xffff);
+
+		/* GNT_BT_LTE always = 1 (this should be config if LTE coex is required) */
+		halbtc8822b2ant_ltecoex_set_coex_table(
+			btcoexist,
+			BT_8822B_2ANT_CTT_BT_VS_LTE,
+			0xffff);
+
+		/* set Path control owner to WL at initial step */
+		halbtc8822b2ant_ltecoex_pathcontrol_owner(
+			btcoexist,
+			BT_8822B_2ANT_PCO_WLSIDE);
+
+		/* set GNT_BT to SW Low */
+		halbtc8822b2ant_ltecoex_set_gnt_bt(btcoexist,
+					   BT_8822B_2ANT_GNT_BLOCK_RFC_BB,
+					   BT_8822B_2ANT_GNT_TYPE_CTRL_BY_SW,
+					   BT_8822B_2ANT_SIG_STA_SET_TO_LOW);
+		/* Set GNT_WL to SW high */
+		halbtc8822b2ant_ltecoex_set_gnt_wl(btcoexist,
+					   BT_8822B_2ANT_GNT_BLOCK_RFC_BB,
+					   BT_8822B_2ANT_GNT_TYPE_CTRL_BY_SW,
+					   BT_8822B_2ANT_SIG_STA_SET_TO_HIGH);
+
+		coex_sta->run_time_state = false;
+
+
+		break;
+	case BT_8822B_2ANT_PHASE_WLAN_OFF:
+		btcoexist->btc_write_1byte_bitmask(btcoexist, 0x4e,
+					   0x80, 0x0);  /* 0x4c[23] = 0 */
+		btcoexist->btc_write_1byte_bitmask(btcoexist, 0x4f,
+					   0x01, 0x0);  /* 0x4c[24] = 0 */
+		/* Disable LTE Coex Function in WiFi side */
+		halbtc8822b2ant_ltecoex_enable(btcoexist, 0x0);
+
+		/* set Path control owner to BT */
+		halbtc8822b2ant_ltecoex_pathcontrol_owner(
+			btcoexist,
+			BT_8822B_2ANT_PCO_BTSIDE);
+
+		/* Set Ext Ant Switch to BT control at wifi off step */
+		halbtc8822b2ant_set_ext_ant_switch(btcoexist,
+						   FORCE_EXEC,
+				   BT_8822B_2ANT_EXT_ANT_SWITCH_CTRL_BY_BT,
+				   BT_8822B_2ANT_EXT_ANT_SWITCH_MAIN_TO_NOCARE);
+		coex_sta->run_time_state = false;
+		break;
+	case BT_8822B_2ANT_PHASE_2G_RUNTIME:
+	case BT_8822B_2ANT_PHASE_2G_RUNTIME_CONCURRENT:
+
+		/* set Path control owner to WL at runtime step */
+		halbtc8822b2ant_ltecoex_pathcontrol_owner(
+			btcoexist,
+			BT_8822B_2ANT_PCO_WLSIDE);
+
+		if (phase ==
+		    BT_8822B_2ANT_PHASE_2G_RUNTIME_CONCURRENT) {
+			/* set GNT_BT to PTA */
+			halbtc8822b2ant_ltecoex_set_gnt_bt(
+				btcoexist,
+				BT_8822B_2ANT_GNT_BLOCK_RFC_BB,
+				BT_8822B_2ANT_GNT_TYPE_CTRL_BY_PTA,
+				BT_8822B_2ANT_SIG_STA_SET_BY_HW);
+
+			/* Set GNT_WL to SW High */
+			halbtc8822b2ant_ltecoex_set_gnt_wl(
+				btcoexist,
+				BT_8822B_2ANT_GNT_BLOCK_RFC_BB,
+				BT_8822B_2ANT_GNT_TYPE_CTRL_BY_SW,
+				BT_8822B_2ANT_SIG_STA_SET_TO_HIGH);
+
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				"[BTCoex], ************* under2g 0xcbd setting =2 *************\n");
+		BTC_TRACE(trace_buf);
+
+	btcoexist->btc_write_1byte_bitmask(btcoexist, 0xcbd,
+							   0x03, 02);
+		} else {
+			/* set GNT_BT to PTA */
+			halbtc8822b2ant_ltecoex_set_gnt_bt(
+				btcoexist,
+				BT_8822B_2ANT_GNT_BLOCK_RFC_BB,
+				BT_8822B_2ANT_GNT_TYPE_CTRL_BY_PTA,
+				BT_8822B_2ANT_SIG_STA_SET_BY_HW);
+
+			/* Set GNT_WL to PTA */
+			halbtc8822b2ant_ltecoex_set_gnt_wl(
+				btcoexist,
+				BT_8822B_2ANT_GNT_BLOCK_RFC_BB,
+				BT_8822B_2ANT_GNT_TYPE_CTRL_BY_PTA,
+				BT_8822B_2ANT_SIG_STA_SET_BY_HW);
+		}
+		coex_sta->run_time_state = true;
+
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				"[BTCoex], ************* under2g 0xcbd setting =2 *************\n");
+		BTC_TRACE(trace_buf);
+
+btcoexist->btc_write_1byte_bitmask(btcoexist, 0xcbd, 0x03, 02);
+		break;
+	case BT_8822B_2ANT_PHASE_5G_RUNTIME:
+
+		/* set Path control owner to WL at runtime step */
+		halbtc8822b2ant_ltecoex_pathcontrol_owner(
+			btcoexist,
+			BT_8822B_2ANT_PCO_WLSIDE);
+
+		/* set GNT_BT to SW Hi */
+		halbtc8822b2ant_ltecoex_set_gnt_bt(btcoexist,
+					   BT_8822B_2ANT_GNT_BLOCK_RFC_BB,
+					   BT_8822B_2ANT_GNT_TYPE_CTRL_BY_SW,
+					   BT_8822B_2ANT_SIG_STA_SET_TO_HIGH);
+		/* Set GNT_WL to SW Hi */
+		halbtc8822b2ant_ltecoex_set_gnt_wl(btcoexist,
+					   BT_8822B_2ANT_GNT_BLOCK_RFC_BB,
+					   BT_8822B_2ANT_GNT_TYPE_CTRL_BY_SW,
+					   BT_8822B_2ANT_SIG_STA_SET_TO_HIGH);
+		coex_sta->run_time_state = true;
+
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				"[BTCoex], ************* under5g 0xcbd setting =1 *************\n");
+		BTC_TRACE(trace_buf);
+
+	btcoexist->btc_write_1byte_bitmask(btcoexist, 0xcbd,
+							   0x03, 01);
+
+		break;
+	case BT_8822B_2ANT_PHASE_BTMPMODE:
+		/* Disable LTE Coex Function in WiFi side */
+		halbtc8822b2ant_ltecoex_enable(btcoexist, 0x0);
+
+		/* set Path control owner to WL */
+		halbtc8822b2ant_ltecoex_pathcontrol_owner(
+			btcoexist,
+			BT_8822B_2ANT_PCO_WLSIDE);
+
+		/* set GNT_BT to SW Hi */
+		halbtc8822b2ant_ltecoex_set_gnt_bt(btcoexist,
+					   BT_8822B_2ANT_GNT_BLOCK_RFC_BB,
+					   BT_8822B_2ANT_GNT_TYPE_CTRL_BY_SW,
+					   BT_8822B_2ANT_SIG_STA_SET_TO_HIGH);
+
+		/* Set GNT_WL to SW Lo */
+		halbtc8822b2ant_ltecoex_set_gnt_wl(btcoexist,
+					   BT_8822B_2ANT_GNT_BLOCK_RFC_BB,
+					   BT_8822B_2ANT_GNT_TYPE_CTRL_BY_SW,
+					   BT_8822B_2ANT_SIG_STA_SET_TO_LOW);
+
+coex_sta->run_time_state = false;
+		break;
+	}
+#if BT_8822B_2ANT_COEX_DBG
+	u32tmp1 = halbtc8822b2ant_ltecoex_indirect_read_reg(btcoexist, 0x38);
+	u32tmp2 = halbtc8822b2ant_ltecoex_indirect_read_reg(btcoexist, 0x54);
+	u32tmp3 = btcoexist->btc_read_4byte(btcoexist, 0xcb4);
+	u8tmp  = btcoexist->btc_read_1byte(btcoexist, 0x73);
+
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+		"[BTCoex], (After Ant-Setup phase---%d) 0xcb4 = 0x%x, 0x73 = 0x%x, 0x38= 0x%x, 0x54= 0x%x\n",
+		    phase, u32tmp3, u8tmp, u32tmp1, u32tmp2);
+
+	BTC_TRACE(trace_buf);
+#endif
+
+}
+
+
+u8 halbtc8822b2ant_action_algorithm(IN struct btc_coexist *btcoexist)
+{
+	struct  btc_bt_link_info	*bt_link_info = &btcoexist->bt_link_info;
+	boolean				bt_hs_on = false;
+	u8				algorithm = BT_8822B_2ANT_COEX_ALGO_UNDEFINED;
+	u8				num_of_diff_profile = 0;
+
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on);
+
+	if (!bt_link_info->bt_link_exist) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], No BT link exists!!!\n");
+		BTC_TRACE(trace_buf);
+		return algorithm;
+	}
+
+	if (bt_link_info->sco_exist)
+		num_of_diff_profile++;
+	if (bt_link_info->hid_exist)
+		num_of_diff_profile++;
+	if (bt_link_info->pan_exist)
+		num_of_diff_profile++;
+	if (bt_link_info->a2dp_exist)
+		num_of_diff_profile++;
+
+	if (num_of_diff_profile == 0) {
+
+		if (bt_link_info->acl_busy) {
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				    "[BTCoex], No-Profile busy\n");
+			BTC_TRACE(trace_buf);
+			algorithm = BT_8822B_2ANT_COEX_ALGO_NOPROFILEBUSY;
+		}
+	} else if (num_of_diff_profile == 1) {
+		if (bt_link_info->sco_exist) {
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				    "[BTCoex], SCO only\n");
+			BTC_TRACE(trace_buf);
+			algorithm = BT_8822B_2ANT_COEX_ALGO_SCO;
+		} else {
+			if (bt_link_info->hid_exist) {
+				BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+					    "[BTCoex], HID only\n");
+				BTC_TRACE(trace_buf);
+				algorithm = BT_8822B_2ANT_COEX_ALGO_HID;
+			} else if (bt_link_info->a2dp_exist) {
+				BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+					    "[BTCoex], A2DP only\n");
+				BTC_TRACE(trace_buf);
+				algorithm = BT_8822B_2ANT_COEX_ALGO_A2DP;
+			} else if (bt_link_info->pan_exist) {
+				if (bt_hs_on) {
+					BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+						    "[BTCoex], PAN(HS) only\n");
+					BTC_TRACE(trace_buf);
+					algorithm =
+						BT_8822B_2ANT_COEX_ALGO_PANHS;
+				} else {
+					BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+						"[BTCoex], PAN(EDR) only\n");
+					BTC_TRACE(trace_buf);
+					algorithm =
+						BT_8822B_2ANT_COEX_ALGO_PANEDR;
+				}
+			}
+		}
+	} else if (num_of_diff_profile == 2) {
+		if (bt_link_info->sco_exist) {
+			if (bt_link_info->hid_exist) {
+				BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+					    "[BTCoex], SCO + HID\n");
+				BTC_TRACE(trace_buf);
+				algorithm = BT_8822B_2ANT_COEX_ALGO_SCO;
+			} else if (bt_link_info->a2dp_exist) {
+				BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+					    "[BTCoex], SCO + A2DP ==> A2DP\n");
+				BTC_TRACE(trace_buf);
+				algorithm = BT_8822B_2ANT_COEX_ALGO_A2DP;
+			} else if (bt_link_info->pan_exist) {
+				if (bt_hs_on) {
+					BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+						"[BTCoex], SCO + PAN(HS)\n");
+					BTC_TRACE(trace_buf);
+					algorithm = BT_8822B_2ANT_COEX_ALGO_SCO;
+				} else {
+					BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+						"[BTCoex], SCO + PAN(EDR)\n");
+					BTC_TRACE(trace_buf);
+					algorithm =
+						BT_8822B_2ANT_COEX_ALGO_PANEDR;
+				}
+			}
+		} else {
+			if (bt_link_info->hid_exist &&
+			    bt_link_info->a2dp_exist) {
+				{
+					BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+						    "[BTCoex], HID + A2DP\n");
+					BTC_TRACE(trace_buf);
+					algorithm =
+						BT_8822B_2ANT_COEX_ALGO_HID_A2DP;
+				}
+			} else if (bt_link_info->hid_exist &&
+				   bt_link_info->pan_exist) {
+				if (bt_hs_on) {
+					BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+						"[BTCoex], HID + PAN(HS)\n");
+					BTC_TRACE(trace_buf);
+					algorithm = BT_8822B_2ANT_COEX_ALGO_HID;
+				} else {
+					BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+						"[BTCoex], HID + PAN(EDR)\n");
+					BTC_TRACE(trace_buf);
+					algorithm =
+						BT_8822B_2ANT_COEX_ALGO_PANEDR_HID;
+				}
+			} else if (bt_link_info->pan_exist &&
+				   bt_link_info->a2dp_exist) {
+				if (bt_hs_on) {
+					BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+						"[BTCoex], A2DP + PAN(HS)\n");
+					BTC_TRACE(trace_buf);
+					algorithm =
+						BT_8822B_2ANT_COEX_ALGO_A2DP_PANHS;
+				} else {
+					BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+						"[BTCoex], A2DP + PAN(EDR)\n");
+					BTC_TRACE(trace_buf);
+					algorithm =
+						BT_8822B_2ANT_COEX_ALGO_PANEDR_A2DP;
+				}
+			}
+		}
+	} else if (num_of_diff_profile == 3) {
+		if (bt_link_info->sco_exist) {
+			if (bt_link_info->hid_exist &&
+			    bt_link_info->a2dp_exist) {
+				BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+					"[BTCoex], SCO + HID + A2DP ==> HID + A2DP\n");
+				BTC_TRACE(trace_buf);
+				algorithm = BT_8822B_2ANT_COEX_ALGO_HID_A2DP;
+			} else if (bt_link_info->hid_exist &&
+				   bt_link_info->pan_exist) {
+				if (bt_hs_on) {
+					BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+						"[BTCoex], SCO + HID + PAN(HS)\n");
+					BTC_TRACE(trace_buf);
+					algorithm =
+						BT_8822B_2ANT_COEX_ALGO_PANEDR_HID;
+				} else {
+					BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+						"[BTCoex], SCO + HID + PAN(EDR)\n");
+					BTC_TRACE(trace_buf);
+					algorithm =
+						BT_8822B_2ANT_COEX_ALGO_PANEDR_HID;
+				}
+			} else if (bt_link_info->pan_exist &&
+				   bt_link_info->a2dp_exist) {
+				if (bt_hs_on) {
+					BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+						"[BTCoex], SCO + A2DP + PAN(HS)\n");
+					BTC_TRACE(trace_buf);
+					algorithm =
+						BT_8822B_2ANT_COEX_ALGO_PANEDR_A2DP;
+				} else {
+					BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+						"[BTCoex], SCO + A2DP + PAN(EDR) ==> HID\n");
+					BTC_TRACE(trace_buf);
+					algorithm =
+						BT_8822B_2ANT_COEX_ALGO_PANEDR_A2DP;
+				}
+			}
+		} else {
+			if (bt_link_info->hid_exist &&
+			    bt_link_info->pan_exist &&
+			    bt_link_info->a2dp_exist) {
+				if (bt_hs_on) {
+					BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+						"[BTCoex], HID + A2DP + PAN(HS)\n");
+					BTC_TRACE(trace_buf);
+					algorithm =
+						BT_8822B_2ANT_COEX_ALGO_HID_A2DP_PANEDR;
+				} else {
+					BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+						"[BTCoex], HID + A2DP + PAN(EDR)\n");
+					BTC_TRACE(trace_buf);
+					algorithm =
+						BT_8822B_2ANT_COEX_ALGO_HID_A2DP_PANEDR;
+				}
+			}
+		}
+	} else if (num_of_diff_profile >= 3) {
+		if (bt_link_info->sco_exist) {
+			if (bt_link_info->hid_exist &&
+			    bt_link_info->pan_exist &&
+			    bt_link_info->a2dp_exist) {
+				if (bt_hs_on) {
+					BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+						"[BTCoex], Error!!! SCO + HID + A2DP + PAN(HS)\n");
+					BTC_TRACE(trace_buf);
+					algorithm =
+						BT_8822B_2ANT_COEX_ALGO_HID_A2DP_PANEDR;
+				} else {
+					BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+						"[BTCoex], SCO + HID + A2DP + PAN(EDR)==>PAN(EDR)+HID\n");
+					BTC_TRACE(trace_buf);
+					algorithm =
+						BT_8822B_2ANT_COEX_ALGO_HID_A2DP_PANEDR;
+				}
+			}
+		}
+	}
+
+	return algorithm;
+}
+
+
+
+void halbtc8822b2ant_action_coex_all_off(IN struct btc_coexist *btcoexist)
+{
+
+	halbtc8822b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0);
+
+	halbtc8822b2ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, NORMAL_EXEC,
+				     BT_8822B_2ANT_PHASE_2G_RUNTIME_CONCURRENT);
+
+	/* fw all off */
+	halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 0);
+
+	halbtc8822b2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xd8);
+	halbtc8822b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);
+
+}
+
+void halbtc8822b2ant_action_wifi_under5g(IN struct btc_coexist *btcoexist)
+{
+
+	/* fw all off */
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+		    "[BTCoex], ************* under5g *************\n");
+	BTC_TRACE(trace_buf);
+	halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 0);
+	halbtc8822b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0);
+
+	halbtc8822b2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xd8);
+	halbtc8822b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);
+
+	halbtc8822b2ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, FORCE_EXEC,
+				     BT_8822B_2ANT_PHASE_5G_RUNTIME);
+}
+
+
+void halbtc8822b2ant_action_bt_inquiry(IN struct btc_coexist *btcoexist)
+{
+
+	boolean	wifi_connected = false;
+	boolean		scan = false, link = false, roam = false;
+	boolean			wifi_busy = false;
+	struct  btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
+
+
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy);
+
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED,
+			   &wifi_connected);
+
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_SCAN, &scan);
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_LINK, &link);
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_ROAM, &roam);
+
+	if (link || roam || coex_sta->wifi_is_high_pri_task) {
+
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			"[BTCoex], Wifi link/roam/hi-pri-task process + BT Inq/Page!!\n");
+		BTC_TRACE(trace_buf);
+
+		halbtc8822b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC,
+						     8);
+		halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 11);
+
+	} else if (scan) {
+
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], Wifi scan process + BT Inq/Page!!\n");
+		BTC_TRACE(trace_buf);
+
+		halbtc8822b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC,
+						     8);
+
+		if (coex_sta->bt_create_connection)
+			halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, true,
+						12);
+		else
+			halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, true,
+						11);
+
+	}  else if (wifi_connected) {
+
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], Wifi connected + BT Inq/Page!!\n");
+		BTC_TRACE(trace_buf);
+
+		halbtc8822b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC,
+						     8);
+
+		if (wifi_busy) {
+
+			if ((bt_link_info->a2dp_exist) &&
+			    (bt_link_info->acl_busy))
+				halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC,
+							true, 13);
+			else
+				halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC,
+							true, 11);
+
+		} else
+			halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, true,
+						13);
+
+	} else {
+
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], Wifi no-link + BT Inq/Page!!\n");
+		BTC_TRACE(trace_buf);
+
+		halbtc8822b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0);
+		halbtc8822b2ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO,
+					     NORMAL_EXEC,
+				     BT_8822B_2ANT_PHASE_2G_RUNTIME_CONCURRENT);
+
+		halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 0);
+	}
+
+	halbtc8822b2ant_fw_dac_swing_lvl(btcoexist, FORCE_EXEC, 0xd8);
+	halbtc8822b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);
+}
+
+void halbtc8822b2ant_action_wifi_link_process(IN struct btc_coexist *btcoexist)
+{
+	u32	u32tmp, u32tmpb;
+	u8	u8tmpa;
+	struct  btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
+
+	halbtc8822b2ant_fw_dac_swing_lvl(btcoexist, FORCE_EXEC, 0xd8);
+	halbtc8822b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);
+
+	halbtc8822b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 7);
+
+	if ((bt_link_info->a2dp_exist) && (bt_link_info->acl_busy))
+		halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 14);
+	else
+		halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 11);
+
+}
+
+
+void halbtc8822b2ant_action_wifi_nonconnected(IN struct btc_coexist *btcoexist)
+{
+	halbtc8822b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0);
+	halbtc8822b2ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, NORMAL_EXEC,
+				     BT_8822B_2ANT_PHASE_2G_RUNTIME_CONCURRENT);
+
+	/* fw all off */
+	halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 0);
+
+	halbtc8822b2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xd8);
+	halbtc8822b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);
+}
+
+void halbtc8822b2ant_action_bt_idle(IN struct btc_coexist *btcoexist)
+{
+	static u8	prewifi_rssi_state = BTC_RSSI_STATE_LOW;
+	static u8	pre_bt_rssi_state = BTC_RSSI_STATE_LOW;
+	u8		wifi_rssi_state, bt_rssi_state;
+
+	static u8	prewifi_rssi_state2 = BTC_RSSI_STATE_LOW;
+	static u8	pre_bt_rssi_state2 = BTC_RSSI_STATE_LOW;
+	u8		wifi_rssi_state2, bt_rssi_state2;
+
+	boolean	wifi_connected = false;
+	boolean		scan = false, link = false, roam = false;
+	boolean			wifi_busy = false;
+
+	wifi_rssi_state = halbtc8822b2ant_wifi_rssi_state(btcoexist,
+			  &prewifi_rssi_state, 2,
+			  coex_sta->wifi_coex_thres , 0);
+
+	wifi_rssi_state2 = halbtc8822b2ant_wifi_rssi_state(btcoexist,
+			   &prewifi_rssi_state2, 2,
+			   coex_sta->wifi_coex_thres2 , 0);
+
+	bt_rssi_state = halbtc8822b2ant_bt_rssi_state(&pre_bt_rssi_state, 2,
+			coex_sta->bt_coex_thres , 0);
+
+	bt_rssi_state2 = halbtc8822b2ant_bt_rssi_state(&pre_bt_rssi_state2, 2,
+			 coex_sta->bt_coex_thres2 , 0);
+
+
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy);
+
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED,
+			   &wifi_connected);
+
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_SCAN, &scan);
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_LINK, &link);
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_ROAM, &roam);
+
+	if (scan || link || roam) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], Wifi link process + BT Idle!!\n");
+		BTC_TRACE(trace_buf);
+
+		halbtc8822b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC,
+						     7);
+
+		halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 11);
+	} else if (wifi_connected) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], Wifi connected + BT Idle!!\n");
+		BTC_TRACE(trace_buf);
+
+		if (wifi_busy) {
+			halbtc8822b2ant_coex_table_with_type(btcoexist,
+							     NORMAL_EXEC, 0);
+			halbtc8822b2ant_set_ant_path(btcoexist,
+					     BTC_ANT_PATH_AUTO, NORMAL_EXEC,
+				     BT_8822B_2ANT_PHASE_2G_RUNTIME_CONCURRENT);
+			/*
+						if (!BTC_RSSI_HIGH(bt_rssi_state2))
+							halbtc8822b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 2);
+						else {
+							halbtc8822b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0);
+							halbtc8822b2ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, NORMAL_EXEC,
+						      BT_8822B_2ANT_PHASE_2G_RUNTIME_CONCURRENT);
+
+						}
+			*/
+		} else {
+			halbtc8822b2ant_coex_table_with_type(btcoexist,
+							     NORMAL_EXEC, 0);
+			halbtc8822b2ant_set_ant_path(btcoexist,
+					     BTC_ANT_PATH_AUTO, NORMAL_EXEC,
+				     BT_8822B_2ANT_PHASE_2G_RUNTIME_CONCURRENT);
+		}
+
+		halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 0);
+
+	} else {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], Wifi no-link + BT Idle!!\n");
+		BTC_TRACE(trace_buf);
+
+		halbtc8822b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0);
+		halbtc8822b2ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO,
+					     NORMAL_EXEC,
+				     BT_8822B_2ANT_PHASE_2G_RUNTIME_CONCURRENT);
+
+		halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 0);
+	}
+
+	halbtc8822b2ant_fw_dac_swing_lvl(btcoexist, FORCE_EXEC, 0xd8);
+	halbtc8822b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);
+
+}
+
+
+/* SCO only or SCO+PAN(HS) */
+void halbtc8822b2ant_action_sco(IN struct btc_coexist *btcoexist)
+{
+	static u8	prewifi_rssi_state = BTC_RSSI_STATE_LOW;
+	static u8	pre_bt_rssi_state = BTC_RSSI_STATE_LOW;
+	u8		wifi_rssi_state, bt_rssi_state;
+
+	static u8	prewifi_rssi_state2 = BTC_RSSI_STATE_LOW;
+	static u8	pre_bt_rssi_state2 = BTC_RSSI_STATE_LOW;
+	u8		wifi_rssi_state2, bt_rssi_state2;
+	boolean			wifi_busy = false;
+
+
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy);
+
+	wifi_rssi_state = halbtc8822b2ant_wifi_rssi_state(btcoexist,
+			  &prewifi_rssi_state, 2,
+			  coex_sta->wifi_coex_thres , 0);
+
+	wifi_rssi_state2 = halbtc8822b2ant_wifi_rssi_state(btcoexist,
+			   &prewifi_rssi_state2, 2,
+			   coex_sta->wifi_coex_thres2 , 0);
+
+	bt_rssi_state = halbtc8822b2ant_bt_rssi_state(&pre_bt_rssi_state, 2,
+			coex_sta->bt_coex_thres , 0);
+
+	bt_rssi_state2 = halbtc8822b2ant_bt_rssi_state(&pre_bt_rssi_state2, 2,
+			 coex_sta->bt_coex_thres2 , 0);
+
+
+	if (BTC_RSSI_HIGH(wifi_rssi_state) &&
+	    BTC_RSSI_HIGH(bt_rssi_state)) {
+
+		halbtc8822b2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xd8);
+		halbtc8822b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);
+
+		coex_dm->is_switch_to_1dot5_ant = false;
+
+		halbtc8822b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0);
+		halbtc8822b2ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO,
+					     NORMAL_EXEC,
+				     BT_8822B_2ANT_PHASE_2G_RUNTIME_CONCURRENT);
+
+		halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 0);
+	}  else {
+
+		halbtc8822b2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xd8);
+		halbtc8822b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);
+
+		coex_dm->is_switch_to_1dot5_ant = false;
+
+		halbtc8822b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 3);
+
+		halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 0);
+	}
+
+}
+
+
+void halbtc8822b2ant_action_hid(IN struct btc_coexist *btcoexist)
+{
+	static u8	prewifi_rssi_state = BTC_RSSI_STATE_LOW;
+	static u8	pre_bt_rssi_state = BTC_RSSI_STATE_LOW;
+	u8		wifi_rssi_state, bt_rssi_state;
+
+	static u8	prewifi_rssi_state2 = BTC_RSSI_STATE_LOW;
+	static u8	pre_bt_rssi_state2 = BTC_RSSI_STATE_LOW;
+	u8		wifi_rssi_state2, bt_rssi_state2;
+	boolean			wifi_busy = false;
+
+
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy);
+
+	wifi_rssi_state = halbtc8822b2ant_wifi_rssi_state(btcoexist,
+			  &prewifi_rssi_state, 2,
+			  coex_sta->wifi_coex_thres , 0);
+
+	wifi_rssi_state2 = halbtc8822b2ant_wifi_rssi_state(btcoexist,
+			   &prewifi_rssi_state2, 2,
+			   coex_sta->wifi_coex_thres2 , 0);
+
+	bt_rssi_state = halbtc8822b2ant_bt_rssi_state(&pre_bt_rssi_state, 2,
+			coex_sta->bt_coex_thres , 0);
+
+	bt_rssi_state2 = halbtc8822b2ant_bt_rssi_state(&pre_bt_rssi_state2, 2,
+			 coex_sta->bt_coex_thres2 , 0);
+
+
+	if (BTC_RSSI_HIGH(wifi_rssi_state) &&
+	    BTC_RSSI_HIGH(bt_rssi_state)) {
+
+		halbtc8822b2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xd8);
+		halbtc8822b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);
+
+		coex_dm->is_switch_to_1dot5_ant = false;
+
+		halbtc8822b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0);
+		halbtc8822b2ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO,
+					     NORMAL_EXEC,
+				     BT_8822B_2ANT_PHASE_2G_RUNTIME_CONCURRENT);
+
+		halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 0);
+	}  else {
+
+		halbtc8822b2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xd8);
+		halbtc8822b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);
+
+		coex_dm->is_switch_to_1dot5_ant = false;
+/*
+		halbtc8822b2ant_coex_table_with_type(btcoexist,
+										 NORMAL_EXEC, 0);
+					halbtc8822b2ant_set_ant_path(btcoexist,
+								 BTC_ANT_PATH_AUTO, NORMAL_EXEC,
+							 BT_8822B_2ANT_PHASE_2G_RUNTIME_CONCURRENT);
+*/
+		halbtc8822b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 3);
+
+/*
+	halbtc8822b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 10);
+*/
+		halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 0);
+	}
+
+}
+
+/* A2DP only / PAN(EDR) only/ A2DP+PAN(HS) */
+void halbtc8822b2ant_action_a2dp(IN struct btc_coexist *btcoexist)
+{
+	static u8	prewifi_rssi_state = BTC_RSSI_STATE_LOW;
+	static u8	pre_bt_rssi_state = BTC_RSSI_STATE_LOW;
+	u8		wifi_rssi_state, bt_rssi_state;
+
+	static u8	prewifi_rssi_state2 = BTC_RSSI_STATE_LOW;
+	static u8	pre_bt_rssi_state2 = BTC_RSSI_STATE_LOW;
+	u8		wifi_rssi_state2, bt_rssi_state2;
+	boolean	wifi_busy = false, wifi_turbo = false;
+
+
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy);
+	btcoexist->btc_get(btcoexist, BTC_GET_U1_AP_NUM,
+			   &coex_sta->scan_ap_num);
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+		    "############# [BTCoex],  scan_ap_num = %d\n",
+		    coex_sta->scan_ap_num);
+	BTC_TRACE(trace_buf);
+
+#if 1
+	if ((wifi_busy) && (coex_sta->scan_ap_num <= 4))
+		wifi_turbo = true;
+#endif
+
+	wifi_rssi_state = halbtc8822b2ant_wifi_rssi_state(btcoexist,
+			  &prewifi_rssi_state, 2,
+			  coex_sta->wifi_coex_thres , 0);
+
+	wifi_rssi_state2 = halbtc8822b2ant_wifi_rssi_state(btcoexist,
+			   &prewifi_rssi_state2, 2,
+			   coex_sta->wifi_coex_thres2 , 0);
+
+	bt_rssi_state = halbtc8822b2ant_bt_rssi_state(&pre_bt_rssi_state, 2,
+			coex_sta->bt_coex_thres , 0);
+
+	bt_rssi_state2 = halbtc8822b2ant_bt_rssi_state(&pre_bt_rssi_state2, 2,
+			 coex_sta->bt_coex_thres2 , 0);
+
+
+	if (BTC_RSSI_HIGH(wifi_rssi_state) &&
+	    BTC_RSSI_HIGH(bt_rssi_state)) {
+
+		halbtc8822b2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xd8);
+		halbtc8822b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);
+
+		coex_dm->is_switch_to_1dot5_ant = false;
+
+		halbtc8822b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0);
+		halbtc8822b2ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO,
+					     NORMAL_EXEC,
+				     BT_8822B_2ANT_PHASE_2G_RUNTIME_CONCURRENT);
+
+		halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 0);
+	} else if (BTC_RSSI_HIGH(wifi_rssi_state2) &&
+		   BTC_RSSI_HIGH(bt_rssi_state2)) {
+
+		halbtc8822b2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xc8);
+		halbtc8822b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2);
+
+		coex_dm->is_switch_to_1dot5_ant = false;
+
+
+
+		halbtc8822b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4);
+
+		if (wifi_busy) {
+			if (coex_sta->is_setupLink)
+				halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC,
+							true, 51);
+			else {
+				halbtc8822b2ant_coex_table_with_type(btcoexist,
+						NORMAL_EXEC, 12);
+				halbtc8822b2ant_set_ant_path(btcoexist,
+						BTC_ANT_PATH_AUTO, NORMAL_EXEC,
+						BT_8822B_2ANT_PHASE_2G_RUNTIME_CONCURRENT);
+				halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC,
+						true, 1);
+			}
+		} else
+
+			halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, true,
+						2);
+	} else {
+
+		halbtc8822b2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xd8);
+		halbtc8822b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);
+
+		coex_dm->is_switch_to_1dot5_ant = true;
+
+		if (wifi_turbo)
+			halbtc8822b2ant_coex_table_with_type(btcoexist,
+							     NORMAL_EXEC, 6);
+		else
+			halbtc8822b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC,
+							     7);
+
+		if (wifi_busy) {
+			if (coex_sta->is_setupLink)
+				halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC,
+							true, 151);
+			else
+				halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC,
+							true, 101);
+		} else
+			halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, true,
+						102);
+
+	}
+
+}
+
+void halbtc8822b2ant_action_pan_edr(IN struct btc_coexist *btcoexist)
+{
+	static u8	prewifi_rssi_state = BTC_RSSI_STATE_LOW;
+	static u8	pre_bt_rssi_state = BTC_RSSI_STATE_LOW;
+	u8		wifi_rssi_state, bt_rssi_state;
+
+	static u8	prewifi_rssi_state2 = BTC_RSSI_STATE_LOW;
+	static u8	pre_bt_rssi_state2 = BTC_RSSI_STATE_LOW;
+	u8		wifi_rssi_state2, bt_rssi_state2;
+	boolean	wifi_busy = false, wifi_turbo = false;
+
+
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy);
+	btcoexist->btc_get(btcoexist, BTC_GET_U1_AP_NUM,
+			   &coex_sta->scan_ap_num);
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+		    "############# [BTCoex],  scan_ap_num = %d\n",
+		    coex_sta->scan_ap_num);
+	BTC_TRACE(trace_buf);
+
+#if 1
+	if ((wifi_busy) && (coex_sta->scan_ap_num <= 4))
+		wifi_turbo = true;
+#endif
+
+	wifi_rssi_state = halbtc8822b2ant_wifi_rssi_state(btcoexist,
+			  &prewifi_rssi_state, 2,
+			  coex_sta->wifi_coex_thres , 0);
+
+	wifi_rssi_state2 = halbtc8822b2ant_wifi_rssi_state(btcoexist,
+			   &prewifi_rssi_state2, 2,
+			   coex_sta->wifi_coex_thres2 , 0);
+
+	bt_rssi_state = halbtc8822b2ant_bt_rssi_state(&pre_bt_rssi_state, 2,
+			coex_sta->bt_coex_thres , 0);
+
+	bt_rssi_state2 = halbtc8822b2ant_bt_rssi_state(&pre_bt_rssi_state2, 2,
+			 coex_sta->bt_coex_thres2 , 0);
+
+#if 0
+	halbtc8822b2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xd8);
+	halbtc8822b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);
+
+	coex_dm->is_switch_to_1dot5_ant = false;
+
+	halbtc8822b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0);
+	halbtc8822b2ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, FORCE_EXEC,
+				     BT_8822B_2ANT_PHASE_2G_RUNTIME_CONCURRENT);
+
+	halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 0);
+#endif
+
+
+#if 1
+	if (BTC_RSSI_HIGH(wifi_rssi_state) &&
+	    BTC_RSSI_HIGH(bt_rssi_state)) {
+
+		halbtc8822b2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xd8);
+		halbtc8822b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);
+
+		coex_dm->is_switch_to_1dot5_ant = false;
+
+		halbtc8822b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0);
+		halbtc8822b2ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO,
+					     NORMAL_EXEC,
+				     BT_8822B_2ANT_PHASE_2G_RUNTIME_CONCURRENT);
+
+		halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 0);
+	} else if (BTC_RSSI_HIGH(wifi_rssi_state2) &&
+		   BTC_RSSI_HIGH(bt_rssi_state2)) {
+
+		halbtc8822b2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xc8);
+		halbtc8822b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2);
+
+		coex_dm->is_switch_to_1dot5_ant = false;
+
+		halbtc8822b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4);
+
+		if (wifi_busy) {
+			halbtc8822b2ant_coex_table_with_type(btcoexist,
+					NORMAL_EXEC, 0);
+			halbtc8822b2ant_set_ant_path(btcoexist,
+					BTC_ANT_PATH_AUTO, NORMAL_EXEC,
+					BT_8822B_2ANT_PHASE_2G_RUNTIME_CONCURRENT);
+
+			halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, true,
+						3);
+		} else
+			halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, true,
+						4);
+	} else {
+
+		halbtc8822b2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xd8);
+		halbtc8822b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);
+
+		coex_dm->is_switch_to_1dot5_ant = true;
+
+		if (wifi_turbo)
+			halbtc8822b2ant_coex_table_with_type(btcoexist,
+							     NORMAL_EXEC, 6);
+		else
+			halbtc8822b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC,
+							     7);
+
+		if (wifi_busy)
+			halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, true,
+						103);
+		else
+			halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, true,
+						104);
+
+	}
+
+#endif
+
+}
+
+
+/* PAN(HS) only */
+void halbtc8822b2ant_action_pan_hs(IN struct btc_coexist *btcoexist)
+{
+	static u8	prewifi_rssi_state = BTC_RSSI_STATE_LOW;
+	static u8	pre_bt_rssi_state = BTC_RSSI_STATE_LOW;
+	u8		wifi_rssi_state, bt_rssi_state;
+
+	static u8	prewifi_rssi_state2 = BTC_RSSI_STATE_LOW;
+	static u8	pre_bt_rssi_state2 = BTC_RSSI_STATE_LOW;
+	u8		wifi_rssi_state2, bt_rssi_state2;
+	boolean	wifi_busy = false, wifi_turbo = false;
+
+
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy);
+	btcoexist->btc_get(btcoexist, BTC_GET_U1_AP_NUM,
+			   &coex_sta->scan_ap_num);
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+		    "############# [BTCoex],  scan_ap_num = %d\n",
+		    coex_sta->scan_ap_num);
+	BTC_TRACE(trace_buf);
+
+#if 1
+	if ((wifi_busy) && (coex_sta->scan_ap_num <= 4))
+		wifi_turbo = true;
+#endif
+
+
+	wifi_rssi_state = halbtc8822b2ant_wifi_rssi_state(btcoexist,
+			  &prewifi_rssi_state, 2,
+			  coex_sta->wifi_coex_thres , 0);
+
+	wifi_rssi_state2 = halbtc8822b2ant_wifi_rssi_state(btcoexist,
+			   &prewifi_rssi_state2, 2,
+			   coex_sta->wifi_coex_thres2 , 0);
+
+	bt_rssi_state = halbtc8822b2ant_bt_rssi_state(&pre_bt_rssi_state, 2,
+			coex_sta->bt_coex_thres , 0);
+
+	bt_rssi_state2 = halbtc8822b2ant_bt_rssi_state(&pre_bt_rssi_state2, 2,
+			 coex_sta->bt_coex_thres2 , 0);
+
+	if (BTC_RSSI_HIGH(wifi_rssi_state) &&
+	    BTC_RSSI_HIGH(bt_rssi_state)) {
+
+		halbtc8822b2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xd8);
+		halbtc8822b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);
+
+		coex_dm->is_switch_to_1dot5_ant = false;
+
+		halbtc8822b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0);
+		halbtc8822b2ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO,
+					     NORMAL_EXEC,
+				     BT_8822B_2ANT_PHASE_2G_RUNTIME_CONCURRENT);
+
+		halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 0);
+	} else if (BTC_RSSI_HIGH(wifi_rssi_state2) &&
+		   BTC_RSSI_HIGH(bt_rssi_state2)) {
+
+		halbtc8822b2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xc8);
+		halbtc8822b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2);
+
+		coex_dm->is_switch_to_1dot5_ant = false;
+
+		halbtc8822b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0);
+		halbtc8822b2ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO,
+					     NORMAL_EXEC,
+				     BT_8822B_2ANT_PHASE_2G_RUNTIME_CONCURRENT);
+
+		halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 0);
+
+
+	} else {
+
+		halbtc8822b2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xd8);
+		halbtc8822b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);
+
+		coex_dm->is_switch_to_1dot5_ant = true;
+
+		halbtc8822b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0);
+		halbtc8822b2ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO,
+					     NORMAL_EXEC,
+				     BT_8822B_2ANT_PHASE_2G_RUNTIME_CONCURRENT);
+
+		halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 0);
+	}
+
+}
+
+
+void halbtc8822b2ant_action_hid_a2dp(IN struct btc_coexist *btcoexist)
+{
+	static u8	prewifi_rssi_state = BTC_RSSI_STATE_LOW;
+	static u8	pre_bt_rssi_state = BTC_RSSI_STATE_LOW;
+	u8		wifi_rssi_state, bt_rssi_state;
+
+	static u8	prewifi_rssi_state2 = BTC_RSSI_STATE_LOW;
+	static u8	pre_bt_rssi_state2 = BTC_RSSI_STATE_LOW;
+	u8		wifi_rssi_state2, bt_rssi_state2;
+	boolean			wifi_busy = false;
+
+
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy);
+
+	wifi_rssi_state = halbtc8822b2ant_wifi_rssi_state(btcoexist,
+			  &prewifi_rssi_state, 2,
+			  coex_sta->wifi_coex_thres , 0);
+
+	wifi_rssi_state2 = halbtc8822b2ant_wifi_rssi_state(btcoexist,
+			   &prewifi_rssi_state2, 2,
+			   coex_sta->wifi_coex_thres2 , 0);
+
+	bt_rssi_state = halbtc8822b2ant_bt_rssi_state(&pre_bt_rssi_state, 2,
+			coex_sta->bt_coex_thres , 0);
+
+	bt_rssi_state2 = halbtc8822b2ant_bt_rssi_state(&pre_bt_rssi_state2, 2,
+			 coex_sta->bt_coex_thres2 , 0);
+
+
+	if (BTC_RSSI_HIGH(wifi_rssi_state) &&
+	    BTC_RSSI_HIGH(bt_rssi_state)) {
+
+		halbtc8822b2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xd8);
+		halbtc8822b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);
+
+		coex_dm->is_switch_to_1dot5_ant = false;
+
+		halbtc8822b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0);
+		halbtc8822b2ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO,
+					     NORMAL_EXEC,
+				     BT_8822B_2ANT_PHASE_2G_RUNTIME_CONCURRENT);
+
+		halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 0);
+	} else if (BTC_RSSI_HIGH(wifi_rssi_state2) &&
+		   BTC_RSSI_HIGH(bt_rssi_state2)) {
+
+		halbtc8822b2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xc8);
+		halbtc8822b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2);
+
+		coex_dm->is_switch_to_1dot5_ant = false;
+
+		halbtc8822b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4);
+
+
+
+
+		if (wifi_busy) {
+			if (coex_sta->is_setupLink)
+				halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC,
+							true, 51);
+			else
+				halbtc8822b2ant_coex_table_with_type(btcoexist,
+							     NORMAL_EXEC, 12);
+			halbtc8822b2ant_set_ant_path(btcoexist,
+					     BTC_ANT_PATH_AUTO, NORMAL_EXEC,
+				     BT_8822B_2ANT_PHASE_2G_RUNTIME_CONCURRENT);
+			/*
+							halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 1);
+			*/
+		} else
+			halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, true,
+						2);
+
+
+	} else {
+
+		halbtc8822b2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xd8);
+		halbtc8822b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);
+
+		coex_dm->is_switch_to_1dot5_ant = true;
+
+		if ((wifi_busy) && (coex_sta->hid_busy_num >= 2))
+			halbtc8822b2ant_coex_table_with_type(btcoexist,
+							     NORMAL_EXEC, 6);
+		else
+			/*
+			halbtc8822b2ant_coex_table_with_type(btcoexist,
+							     NORMAL_EXEC, 9);
+							     */
+			halbtc8822b2ant_coex_table_with_type(btcoexist,
+							     NORMAL_EXEC, 4);
+
+		if (wifi_busy) {
+			if (coex_sta->is_setupLink)
+				halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC,
+							true, 151);
+			else
+				halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC,
+							true, 101);
+		} else
+			halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, true,
+						102);
+
+	}
+
+}
+
+
+void halbtc8822b2ant_action_a2dp_pan_hs(IN struct btc_coexist *btcoexist)
+{
+	static u8	prewifi_rssi_state = BTC_RSSI_STATE_LOW;
+	static u8	pre_bt_rssi_state = BTC_RSSI_STATE_LOW;
+	u8		wifi_rssi_state, bt_rssi_state;
+
+	static u8	prewifi_rssi_state2 = BTC_RSSI_STATE_LOW;
+	static u8	pre_bt_rssi_state2 = BTC_RSSI_STATE_LOW;
+	u8		wifi_rssi_state2, bt_rssi_state2;
+	boolean	wifi_busy = false, wifi_turbo = false;
+
+
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy);
+	btcoexist->btc_get(btcoexist, BTC_GET_U1_AP_NUM,
+			   &coex_sta->scan_ap_num);
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+		    "############# [BTCoex],  scan_ap_num = %d\n",
+		    coex_sta->scan_ap_num);
+	BTC_TRACE(trace_buf);
+
+#if 1
+	if ((wifi_busy) && (coex_sta->scan_ap_num <= 4))
+		wifi_turbo = true;
+#endif
+
+
+	wifi_rssi_state = halbtc8822b2ant_wifi_rssi_state(btcoexist,
+			  &prewifi_rssi_state, 2,
+			  coex_sta->wifi_coex_thres , 0);
+
+	wifi_rssi_state2 = halbtc8822b2ant_wifi_rssi_state(btcoexist,
+			   &prewifi_rssi_state2, 2,
+			   coex_sta->wifi_coex_thres2 , 0);
+
+	bt_rssi_state = halbtc8822b2ant_bt_rssi_state(&pre_bt_rssi_state, 2,
+			coex_sta->bt_coex_thres , 0);
+
+	bt_rssi_state2 = halbtc8822b2ant_bt_rssi_state(&pre_bt_rssi_state2, 2,
+			 coex_sta->bt_coex_thres2 , 0);
+
+
+	if (BTC_RSSI_HIGH(wifi_rssi_state) &&
+	    BTC_RSSI_HIGH(bt_rssi_state)) {
+
+		halbtc8822b2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xd8);
+		halbtc8822b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);
+
+		coex_dm->is_switch_to_1dot5_ant = false;
+
+		halbtc8822b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0);
+		halbtc8822b2ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO,
+					     NORMAL_EXEC,
+				     BT_8822B_2ANT_PHASE_2G_RUNTIME_CONCURRENT);
+
+		halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 0);
+	} else if (BTC_RSSI_HIGH(wifi_rssi_state2) &&
+		   BTC_RSSI_HIGH(bt_rssi_state2)) {
+
+		halbtc8822b2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xc8);
+		halbtc8822b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2);
+
+		coex_dm->is_switch_to_1dot5_ant = false;
+
+		halbtc8822b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4);
+
+		if (wifi_busy) {
+
+			if ((coex_sta->a2dp_bit_pool > 40) &&
+			    (coex_sta->a2dp_bit_pool < 255))
+				halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC,
+							true, 7);
+			else
+				halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC,
+							true, 5);
+		} else
+			halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, true,
+						6);
+
+	} else {
+
+		halbtc8822b2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xd8);
+		halbtc8822b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);
+
+		coex_dm->is_switch_to_1dot5_ant = true;
+
+		if (wifi_turbo)
+			halbtc8822b2ant_coex_table_with_type(btcoexist,
+							     NORMAL_EXEC, 6);
+		else
+			halbtc8822b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC,
+							     7);
+
+		if (wifi_busy) {
+
+			if ((coex_sta->a2dp_bit_pool > 40) &&
+			    (coex_sta->a2dp_bit_pool < 255))
+				halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC,
+							true, 107);
+			else
+				halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC,
+							true, 105);
+		} else
+			halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, true,
+						106);
+
+	}
+
+}
+
+
+
+/* PAN(EDR)+A2DP */
+void halbtc8822b2ant_action_pan_edr_a2dp(IN struct btc_coexist *btcoexist)
+{
+	static u8	prewifi_rssi_state = BTC_RSSI_STATE_LOW;
+	static u8	pre_bt_rssi_state = BTC_RSSI_STATE_LOW;
+	u8		wifi_rssi_state, bt_rssi_state;
+
+	static u8	prewifi_rssi_state2 = BTC_RSSI_STATE_LOW;
+	static u8	pre_bt_rssi_state2 = BTC_RSSI_STATE_LOW;
+	u8		wifi_rssi_state2, bt_rssi_state2;
+	boolean	wifi_busy = false, wifi_turbo = false;
+
+
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy);
+	btcoexist->btc_get(btcoexist, BTC_GET_U1_AP_NUM,
+			   &coex_sta->scan_ap_num);
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+		    "############# [BTCoex],  scan_ap_num = %d\n",
+		    coex_sta->scan_ap_num);
+	BTC_TRACE(trace_buf);
+
+#if 1
+	if ((wifi_busy) && (coex_sta->scan_ap_num <= 4))
+		wifi_turbo = true;
+#endif
+
+
+	wifi_rssi_state = halbtc8822b2ant_wifi_rssi_state(btcoexist,
+			  &prewifi_rssi_state, 2,
+			  coex_sta->wifi_coex_thres , 0);
+
+	wifi_rssi_state2 = halbtc8822b2ant_wifi_rssi_state(btcoexist,
+			   &prewifi_rssi_state2, 2,
+			   coex_sta->wifi_coex_thres2 , 0);
+
+	bt_rssi_state = halbtc8822b2ant_bt_rssi_state(&pre_bt_rssi_state, 2,
+			coex_sta->bt_coex_thres , 0);
+
+	bt_rssi_state2 = halbtc8822b2ant_bt_rssi_state(&pre_bt_rssi_state2, 2,
+			 coex_sta->bt_coex_thres2 , 0);
+
+	if (BTC_RSSI_HIGH(wifi_rssi_state) &&
+	    BTC_RSSI_HIGH(bt_rssi_state)) {
+
+		halbtc8822b2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xd8);
+		halbtc8822b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);
+
+		coex_dm->is_switch_to_1dot5_ant = false;
+
+		halbtc8822b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0);
+		halbtc8822b2ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO,
+					     NORMAL_EXEC,
+				     BT_8822B_2ANT_PHASE_2G_RUNTIME_CONCURRENT);
+
+		halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 0);
+	} else if (BTC_RSSI_HIGH(wifi_rssi_state2) &&
+		   BTC_RSSI_HIGH(bt_rssi_state2)) {
+
+		halbtc8822b2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xc8);
+		halbtc8822b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2);
+
+		coex_dm->is_switch_to_1dot5_ant = false;
+
+		halbtc8822b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4);
+
+		if (wifi_busy) {
+
+			if (((coex_sta->a2dp_bit_pool > 40) &&
+			     (coex_sta->a2dp_bit_pool < 255)) ||
+			    (!coex_sta->is_A2DP_3M))
+				halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC,
+							true, 7);
+			else
+				halbtc8822b2ant_coex_table_with_type(btcoexist,
+											 NORMAL_EXEC, 0);
+			halbtc8822b2ant_set_ant_path(btcoexist,
+						BTC_ANT_PATH_AUTO, NORMAL_EXEC,
+						BT_8822B_2ANT_PHASE_2G_RUNTIME_CONCURRENT);
+				halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC,
+							true, 5);
+		} else
+			halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, true,
+						6);
+	} else {
+
+		halbtc8822b2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xd8);
+		halbtc8822b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);
+
+		coex_dm->is_switch_to_1dot5_ant = true;
+
+		if (wifi_turbo)
+			halbtc8822b2ant_coex_table_with_type(btcoexist,
+							     NORMAL_EXEC, 6);
+		else
+			halbtc8822b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC,
+							     7);
+
+		if (wifi_busy) {
+
+			if ((coex_sta->a2dp_bit_pool > 40) &&
+			    (coex_sta->a2dp_bit_pool < 255))
+				halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC,
+							true, 107);
+			else
+				halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC,
+							true, 105);
+		} else
+			halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, true,
+						106);
+
+	}
+
+}
+
+void halbtc8822b2ant_action_pan_edr_hid(IN struct btc_coexist *btcoexist)
+{
+	static u8	prewifi_rssi_state = BTC_RSSI_STATE_LOW;
+	static u8	pre_bt_rssi_state = BTC_RSSI_STATE_LOW;
+	u8		wifi_rssi_state, bt_rssi_state;
+
+	static u8	prewifi_rssi_state2 = BTC_RSSI_STATE_LOW;
+	static u8	pre_bt_rssi_state2 = BTC_RSSI_STATE_LOW;
+	u8		wifi_rssi_state2, bt_rssi_state2;
+	boolean			wifi_busy = false;
+
+
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy);
+
+	wifi_rssi_state = halbtc8822b2ant_wifi_rssi_state(btcoexist,
+			  &prewifi_rssi_state, 2,
+			  coex_sta->wifi_coex_thres , 0);
+
+	wifi_rssi_state2 = halbtc8822b2ant_wifi_rssi_state(btcoexist,
+			   &prewifi_rssi_state2, 2,
+			   coex_sta->wifi_coex_thres2 , 0);
+
+	bt_rssi_state = halbtc8822b2ant_bt_rssi_state(&pre_bt_rssi_state, 2,
+			coex_sta->bt_coex_thres , 0);
+
+	bt_rssi_state2 = halbtc8822b2ant_bt_rssi_state(&pre_bt_rssi_state2, 2,
+			 coex_sta->bt_coex_thres2 , 0);
+
+
+	if (BTC_RSSI_HIGH(wifi_rssi_state) &&
+	    BTC_RSSI_HIGH(bt_rssi_state)) {
+
+		halbtc8822b2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xd8);
+		halbtc8822b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);
+
+		coex_dm->is_switch_to_1dot5_ant = false;
+
+		halbtc8822b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0);
+		halbtc8822b2ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO,
+					     NORMAL_EXEC,
+				     BT_8822B_2ANT_PHASE_2G_RUNTIME_CONCURRENT);
+
+		halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 0);
+	} else if (BTC_RSSI_HIGH(wifi_rssi_state2) &&
+		   BTC_RSSI_HIGH(bt_rssi_state2)) {
+
+		halbtc8822b2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xc8);
+		halbtc8822b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2);
+
+		coex_dm->is_switch_to_1dot5_ant = false;
+
+		halbtc8822b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4);
+
+		if (wifi_busy)
+
+			halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, true,
+						3);
+		else
+
+			halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, true,
+						4);
+
+
+	} else {
+
+		halbtc8822b2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xd8);
+		halbtc8822b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);
+
+		coex_dm->is_switch_to_1dot5_ant = true;
+
+		halbtc8822b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 1);
+
+		if (wifi_busy)
+
+			halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, true,
+						103);
+		else
+
+			halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, true,
+						104);
+
+	}
+
+}
+
+/* HID+A2DP+PAN(EDR) */
+void halbtc8822b2ant_action_hid_a2dp_pan_edr(IN struct btc_coexist *btcoexist)
+{
+	static u8	prewifi_rssi_state = BTC_RSSI_STATE_LOW;
+	static u8	pre_bt_rssi_state = BTC_RSSI_STATE_LOW;
+	u8		wifi_rssi_state, bt_rssi_state;
+
+	static u8	prewifi_rssi_state2 = BTC_RSSI_STATE_LOW;
+	static u8	pre_bt_rssi_state2 = BTC_RSSI_STATE_LOW;
+	u8		wifi_rssi_state2, bt_rssi_state2;
+	boolean			wifi_busy = false;
+
+
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy);
+
+	wifi_rssi_state = halbtc8822b2ant_wifi_rssi_state(btcoexist,
+			  &prewifi_rssi_state, 2,
+			  coex_sta->wifi_coex_thres , 0);
+
+	wifi_rssi_state2 = halbtc8822b2ant_wifi_rssi_state(btcoexist,
+			   &prewifi_rssi_state2, 2,
+			   coex_sta->wifi_coex_thres2 , 0);
+
+	bt_rssi_state = halbtc8822b2ant_bt_rssi_state(&pre_bt_rssi_state, 2,
+			coex_sta->bt_coex_thres , 0);
+
+	bt_rssi_state2 = halbtc8822b2ant_bt_rssi_state(&pre_bt_rssi_state2, 2,
+			 coex_sta->bt_coex_thres2 , 0);
+
+
+	if (BTC_RSSI_HIGH(wifi_rssi_state) &&
+	    BTC_RSSI_HIGH(bt_rssi_state)) {
+
+		halbtc8822b2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xd8);
+		halbtc8822b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);
+
+		coex_dm->is_switch_to_1dot5_ant = false;
+
+		halbtc8822b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0);
+		halbtc8822b2ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO,
+					     NORMAL_EXEC,
+				     BT_8822B_2ANT_PHASE_2G_RUNTIME_CONCURRENT);
+
+		halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 0);
+	} else if (BTC_RSSI_HIGH(wifi_rssi_state2) &&
+		   BTC_RSSI_HIGH(bt_rssi_state2)) {
+
+		halbtc8822b2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xc8);
+		halbtc8822b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2);
+
+		coex_dm->is_switch_to_1dot5_ant = false;
+
+		halbtc8822b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4);
+
+		if (wifi_busy) {
+
+			if (((coex_sta->a2dp_bit_pool > 40) &&
+			     (coex_sta->a2dp_bit_pool < 255)) ||
+			    (!coex_sta->is_A2DP_3M))
+				halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC,
+							true, 7);
+			else
+				halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC,
+							true, 5);
+		} else
+			halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, true,
+						6);
+	} else {
+
+		halbtc8822b2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xd8);
+		halbtc8822b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);
+
+		coex_dm->is_switch_to_1dot5_ant = true;
+
+		halbtc8822b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 1);
+
+		if (wifi_busy) {
+
+			if ((coex_sta->a2dp_bit_pool > 40) &&
+			    (coex_sta->a2dp_bit_pool < 255))
+				halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC,
+							true, 107);
+			else
+				halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC,
+							true, 105);
+		} else
+			halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, true,
+						106);
+	}
+
+}
+
+
+
+void halbtc8822b2ant_action_bt_whck_test(IN struct btc_coexist *btcoexist)
+{
+	halbtc8822b2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xd8);
+	halbtc8822b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);
+
+	halbtc8822b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0);
+	halbtc8822b2ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, NORMAL_EXEC,
+				     BT_8822B_2ANT_PHASE_2G_RUNTIME_CONCURRENT);
+
+	halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 0);
+}
+
+void halbtc8822b2ant_action_wifi_multi_port(IN struct btc_coexist *btcoexist)
+{
+	halbtc8822b2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xd8);
+	halbtc8822b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);
+
+	/* hw all off */
+	halbtc8822b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0);
+	halbtc8822b2ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, NORMAL_EXEC,
+				     BT_8822B_2ANT_PHASE_2G_RUNTIME_CONCURRENT);
+
+	halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 0);
+}
+
+void halbtc8822b2ant_run_coexist_mechanism(IN struct btc_coexist *btcoexist)
+{
+	u8				algorithm = 0;
+	u32				num_of_wifi_link = 0;
+	u32				wifi_link_status = 0;
+	struct  btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
+	boolean				miracast_plus_bt = false;
+	boolean				scan = false, link = false, roam = false,
+				wifi_connected = false, wifi_under_5g = false;
+
+
+
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+		    "[BTCoex], RunCoexistMechanism()===>\n");
+	BTC_TRACE(trace_buf);
+
+	if (btcoexist->manual_control) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			"[BTCoex], RunCoexistMechanism(), return for Manual CTRL <===\n");
+		BTC_TRACE(trace_buf);
+		return;
+	}
+
+	if (btcoexist->stop_coex_dm) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			"[BTCoex], RunCoexistMechanism(), return for Stop Coex DM <===\n");
+		BTC_TRACE(trace_buf);
+		return;
+	}
+
+	if (coex_sta->under_ips) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], wifi is under IPS !!!\n");
+		BTC_TRACE(trace_buf);
+		return;
+	}
+
+	if (!coex_sta->run_time_state) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			"[BTCoex], return for run_time_state = false !!!\n");
+		BTC_TRACE(trace_buf);
+		return;
+	}
+
+	if (coex_sta->freeze_coexrun_by_btinfo) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			"[BTCoex], BtInfoNotify(), return for freeze_coexrun_by_btinfo\n");
+		BTC_TRACE(trace_buf);
+		return;
+	}
+
+
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_5G, &wifi_under_5g);
+
+	if (wifi_under_5g) {
+
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], WiFi is under 5G!!!\n");
+		BTC_TRACE(trace_buf);
+
+		halbtc8822b2ant_action_wifi_under5g(btcoexist);
+		return;
+	}
+
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+		    "[BTCoex], WiFi is under 2G!!!\n");
+	BTC_TRACE(trace_buf);
+
+	halbtc8822b2ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO,
+				     NORMAL_EXEC,
+				     BT_8822B_2ANT_PHASE_2G_RUNTIME);
+
+
+	if (coex_sta->bt_whck_test) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], BT is under WHCK TEST!!!\n");
+		BTC_TRACE(trace_buf);
+		halbtc8822b2ant_action_bt_whck_test(btcoexist);
+		return;
+	}
+
+	if (coex_sta->bt_disabled) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], BT is disabled!!!\n");
+		BTC_TRACE(trace_buf);
+		halbtc8822b2ant_action_coex_all_off(btcoexist);
+		return;
+	}
+
+	if (coex_sta->c2h_bt_inquiry_page) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], BT is under inquiry/page scan !!\n");
+		BTC_TRACE(trace_buf);
+		halbtc8822b2ant_action_bt_inquiry(btcoexist);
+		return;
+	}
+
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_SCAN, &scan);
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_LINK, &link);
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_ROAM, &roam);
+
+	if (scan || link || roam) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], WiFi is under Link Process !!\n");
+		BTC_TRACE(trace_buf);
+		halbtc8822b2ant_action_wifi_link_process(btcoexist);
+		return;
+	}
+
+	/* for P2P */
+	btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_LINK_STATUS,
+			   &wifi_link_status);
+	num_of_wifi_link = wifi_link_status >> 16;
+
+	if ((num_of_wifi_link >= 2) ||
+	    (wifi_link_status & WIFI_P2P_GO_CONNECTED)) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			"############# [BTCoex],  Multi-Port num_of_wifi_link = %d, wifi_link_status = 0x%x\n",
+			    num_of_wifi_link, wifi_link_status);
+		BTC_TRACE(trace_buf);
+
+		if (bt_link_info->bt_link_exist)
+			miracast_plus_bt = true;
+		else
+			miracast_plus_bt = false;
+
+		btcoexist->btc_set(btcoexist, BTC_SET_BL_MIRACAST_PLUS_BT,
+				   &miracast_plus_bt);
+		halbtc8822b2ant_action_wifi_multi_port(btcoexist);
+
+		return;
+	}
+
+	miracast_plus_bt = false;
+	btcoexist->btc_set(btcoexist, BTC_SET_BL_MIRACAST_PLUS_BT,
+			   &miracast_plus_bt);
+
+
+	algorithm = halbtc8822b2ant_action_algorithm(btcoexist);
+	coex_dm->cur_algorithm = algorithm;
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], Algorithm = %d\n",
+		    coex_dm->cur_algorithm);
+	BTC_TRACE(trace_buf);
+
+
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED,
+			   &wifi_connected);
+
+	if (!wifi_connected) {
+
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], Action 2-Ant, wifi non-connected!!.\n");
+		BTC_TRACE(trace_buf);
+		halbtc8822b2ant_action_wifi_nonconnected(btcoexist);
+
+	} else if ((BT_8822B_2ANT_BT_STATUS_NON_CONNECTED_IDLE ==
+		    coex_dm->bt_status) ||
+		   (BT_8822B_2ANT_BT_STATUS_CONNECTED_IDLE ==
+		    coex_dm->bt_status)) {
+
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], Action 2-Ant, bt idle!!.\n");
+		BTC_TRACE(trace_buf);
+
+		halbtc8822b2ant_action_bt_idle(btcoexist);
+
+	} else {
+
+		if (coex_dm->cur_algorithm != coex_dm->pre_algorithm) {
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				"[BTCoex], pre_algorithm=%d, cur_algorithm=%d\n",
+				coex_dm->pre_algorithm, coex_dm->cur_algorithm);
+			BTC_TRACE(trace_buf);
+		}
+
+		switch (coex_dm->cur_algorithm) {
+
+		case BT_8822B_2ANT_COEX_ALGO_SCO:
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				"[BTCoex], Action 2-Ant, algorithm = SCO.\n");
+			BTC_TRACE(trace_buf);
+			halbtc8822b2ant_action_sco(btcoexist);
+			break;
+		case BT_8822B_2ANT_COEX_ALGO_HID:
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				"[BTCoex], Action 2-Ant, algorithm = HID.\n");
+			BTC_TRACE(trace_buf);
+			halbtc8822b2ant_action_hid(btcoexist);
+			break;
+		case BT_8822B_2ANT_COEX_ALGO_A2DP:
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				"[BTCoex], Action 2-Ant, algorithm = A2DP.\n");
+			BTC_TRACE(trace_buf);
+			halbtc8822b2ant_action_a2dp(btcoexist);
+			break;
+		case BT_8822B_2ANT_COEX_ALGO_A2DP_PANHS:
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				"[BTCoex], Action 2-Ant, algorithm = A2DP+PAN(HS).\n");
+			BTC_TRACE(trace_buf);
+			halbtc8822b2ant_action_a2dp_pan_hs(btcoexist);
+			break;
+		case BT_8822B_2ANT_COEX_ALGO_PANEDR:
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				"[BTCoex], Action 2-Ant, algorithm = PAN(EDR).\n");
+			BTC_TRACE(trace_buf);
+			halbtc8822b2ant_action_pan_edr(btcoexist);
+			break;
+		case BT_8822B_2ANT_COEX_ALGO_PANHS:
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				"[BTCoex], Action 2-Ant, algorithm = HS mode.\n");
+			BTC_TRACE(trace_buf);
+			halbtc8822b2ant_action_pan_hs(btcoexist);
+			break;
+		case BT_8822B_2ANT_COEX_ALGO_PANEDR_A2DP:
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				"[BTCoex], Action 2-Ant, algorithm = PAN+A2DP.\n");
+			BTC_TRACE(trace_buf);
+			halbtc8822b2ant_action_pan_edr_a2dp(btcoexist);
+			break;
+		case BT_8822B_2ANT_COEX_ALGO_PANEDR_HID:
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				"[BTCoex], Action 2-Ant, algorithm = PAN(EDR)+HID.\n");
+			BTC_TRACE(trace_buf);
+			halbtc8822b2ant_action_pan_edr_hid(btcoexist);
+			break;
+		case BT_8822B_2ANT_COEX_ALGO_HID_A2DP_PANEDR:
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				"[BTCoex], Action 2-Ant, algorithm = HID+A2DP+PAN.\n");
+			BTC_TRACE(trace_buf);
+			halbtc8822b2ant_action_hid_a2dp_pan_edr(
+				btcoexist);
+			break;
+		case BT_8822B_2ANT_COEX_ALGO_HID_A2DP:
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				"[BTCoex], Action 2-Ant, algorithm = HID+A2DP.\n");
+			BTC_TRACE(trace_buf);
+			halbtc8822b2ant_action_hid_a2dp(btcoexist);
+			break;
+		case BT_8822B_2ANT_COEX_ALGO_NOPROFILEBUSY:
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				"[BTCoex], Action 2-Ant, algorithm = No-Profile busy.\n");
+			BTC_TRACE(trace_buf);
+			halbtc8822b2ant_action_bt_idle(btcoexist);
+			break;
+		default:
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				"[BTCoex], Action 2-Ant, algorithm = coexist All Off!!\n");
+			BTC_TRACE(trace_buf);
+			halbtc8822b2ant_action_coex_all_off(btcoexist);
+			break;
+		}
+		coex_dm->pre_algorithm = coex_dm->cur_algorithm;
+	}
+}
+
+void halbtc8822b2ant_init_coex_dm(IN struct btc_coexist *btcoexist)
+{
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+		    "[BTCoex], Coex Mechanism Init!!\n");
+	BTC_TRACE(trace_buf);
+
+	halbtc8822b2ant_low_penalty_ra(btcoexist, NORMAL_EXEC, false);
+
+	halbtc8822b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0);
+	halbtc8822b2ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, NORMAL_EXEC,
+				     BT_8822B_2ANT_PHASE_2G_RUNTIME_CONCURRENT);
+
+	/* fw all off */
+	halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 0);
+
+	halbtc8822b2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xd8);
+	halbtc8822b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);
+
+	coex_sta->pop_event_cnt = 0;
+	coex_sta->cnt_RemoteNameReq = 0;
+	coex_sta->cnt_ReInit = 0;
+	coex_sta->cnt_setupLink = 0;
+	coex_sta->cnt_IgnWlanAct = 0;
+	coex_sta->cnt_Page = 0;
+
+	halbtc8822b2ant_query_bt_info(btcoexist);
+}
+
+
+void halbtc8822b2ant_init_hw_config(IN struct btc_coexist *btcoexist,
+				    IN boolean wifi_only)
+{
+	u8	u8tmp = 0;
+	u32	 vendor;
+	u32				u32tmp0 = 0, u32tmp1 = 0, u32tmp2 = 0, u32tmp3 = 0;
+	u32	RTL97F_8822B = 0;
+
+
+	u32tmp3 = btcoexist->btc_read_4byte(btcoexist, 0xcb4);
+	u32tmp1 = halbtc8822b2ant_ltecoex_indirect_read_reg(btcoexist, 0x38);
+	u32tmp2 = halbtc8822b2ant_ltecoex_indirect_read_reg(btcoexist, 0x54);
+
+	if (RTL97F_8822B == true) {
+		btcoexist->btc_write_1byte_bitmask(btcoexist, 0x66, 0x04, 0x0);
+		btcoexist->btc_write_1byte_bitmask(btcoexist, 0x41, 0x02, 0x0);
+
+		/* set GNT_BT to SW high */
+		halbtc8822b2ant_ltecoex_set_gnt_bt(btcoexist,
+					   BT_8822B_2ANT_GNT_BLOCK_RFC_BB,
+					   BT_8822B_2ANT_GNT_TYPE_CTRL_BY_SW,
+					   BT_8822B_2ANT_SIG_STA_SET_TO_HIGH);
+		/* Set GNT_WL to SW high */
+		halbtc8822b2ant_ltecoex_set_gnt_wl(btcoexist,
+					   BT_8822B_2ANT_GNT_BLOCK_RFC_BB,
+					   BT_8822B_2ANT_GNT_TYPE_CTRL_BY_SW,
+					   BT_8822B_2ANT_SIG_STA_SET_TO_HIGH);
+		 return;
+	}
+
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+		"[BTCoex], (Before Init HW config) 0xcb4 = 0x%x, 0x38= 0x%x, 0x54= 0x%x\n",
+		    u32tmp3, u32tmp1, u32tmp2);
+	BTC_TRACE(trace_buf);
+
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+		    "[BTCoex], 2Ant Init HW Config!!\n");
+	BTC_TRACE(trace_buf);
+
+	coex_sta->bt_coex_supported_feature = 0;
+	coex_sta->bt_coex_supported_version = 0;
+	coex_sta->bt_ble_scan_type = 0;
+	coex_sta->bt_ble_scan_para[0] = 0;
+	coex_sta->bt_ble_scan_para[1] = 0;
+	coex_sta->bt_ble_scan_para[2] = 0;
+	coex_sta->bt_reg_vendor_ac = 0xffff;
+	coex_sta->bt_reg_vendor_ae = 0xffff;
+	coex_sta->isolation_btween_wb = BT_8822B_2ANT_DEFAULT_ISOLATION;
+
+	/* 0xf0[15:12] --> Chip Cut information */
+	coex_sta->cut_version = (btcoexist->btc_read_1byte(btcoexist,
+				 0xf1) & 0xf0) >> 4;
+
+	coex_sta->dis_ver_info_cnt = 0;
+
+	halbtc8822b2ant_coex_switch_threshold(btcoexist,
+					      coex_sta->isolation_btween_wb);
+
+	btcoexist->btc_write_1byte_bitmask(btcoexist, 0x550, 0x8,
+					   0x1);  /* enable TBTT nterrupt */
+
+	/* BT report packet sample rate	 */
+	btcoexist->btc_write_1byte(btcoexist, 0x790, 0x5);
+
+	/* Init 0x778 = 0x1 for 2-Ant */
+	btcoexist->btc_write_1byte(btcoexist, 0x778, 0x1);
+
+	/* Enable PTA (3-wire function form BT side) */
+	btcoexist->btc_write_1byte_bitmask(btcoexist, 0x40, 0x20, 0x1);
+	btcoexist->btc_write_1byte_bitmask(btcoexist, 0x41, 0x02, 0x1);
+
+	/* Enable PTA (tx/rx signal form WiFi side) */
+	btcoexist->btc_write_1byte_bitmask(btcoexist, 0x4c6, 0x10, 0x1);
+
+	halbtc8822b2ant_enable_gnt_to_gpio(btcoexist, true);
+
+	/*GNT_BT=1 while select both */
+	btcoexist->btc_write_1byte_bitmask(btcoexist, 0x763, 0x10, 0x1);
+
+
+	/* check if WL firmware download ok */
+	/*if (btcoexist->btc_read_1byte(btcoexist, 0x80) == 0xc6)*/
+	halbtc8822b2ant_post_state_to_bt(btcoexist,
+					 BT_8822B_2ANT_SCOREBOARD_ONOFF, true);
+
+	/* Enable counter statistics */
+	btcoexist->btc_write_1byte(btcoexist, 0x76e,
+			   0x4); /* 0x76e[3] =1, WLAN_Act control by PTA */
+
+	/* WLAN_Tx by GNT_WL  0x950[29] = 0 */
+	/* btcoexist->btc_write_1byte_bitmask(btcoexist, 0x953, 0x20, 0x0); */
+
+	halbtc8822b2ant_coex_table_with_type(btcoexist, FORCE_EXEC, 0);
+
+	halbtc8822b2ant_ps_tdma(btcoexist, FORCE_EXEC, false, 0);
+
+	psd_scan->ant_det_is_ant_det_available = true;
+
+	if (wifi_only) {
+		coex_sta->concurrent_rx_mode_on = false;
+		/* Path config	 */
+		/* Set Antenna Path */
+		halbtc8822b2ant_set_ant_path(btcoexist,	BTC_ANT_PATH_AUTO,
+					     FORCE_EXEC,
+					     BT_8822B_2ANT_PHASE_WLANONLY_INIT);
+
+		btcoexist->stop_coex_dm = true;
+	} else {
+		/*Set BT polluted packet on for Tx rate adaptive not including Tx retry break by PTA, 0x45c[19] =1 */
+		btcoexist->btc_write_1byte_bitmask(btcoexist, 0x45e, 0x8, 0x1);
+
+		coex_sta->concurrent_rx_mode_on = true;
+		/* btcoexist->btc_write_1byte_bitmask(btcoexist, 0x953, 0x2, 0x1); */
+
+		/* RF 0x1[1] = 0->Set GNT_WL_RF_Rx always = 1 for con-current Rx, mask Tx only */
+		btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1, 0x2, 0x0);
+
+		/* Set Antenna Path */
+		halbtc8822b2ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO,
+					     FORCE_EXEC,
+					     BT_8822B_2ANT_PHASE_COEX_INIT);
+
+		btcoexist->stop_coex_dm = false;
+	}
+}
+
+
+
+/* ************************************************************
+ * work around function start with wa_halbtc8822b2ant_
+ * ************************************************************
+ * ************************************************************
+ * extern function start with ex_halbtc8822b2ant_
+ * ************************************************************ */
+void ex_halbtc8822b2ant_power_on_setting(IN struct btc_coexist *btcoexist)
+{
+	struct  btc_board_info	*board_info = &btcoexist->board_info;
+	u8 u8tmp = 0x0;
+	u16 u16tmp = 0x0;
+	u32	value = 0;
+
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+		"xxxxxxxxxxxxxxxx Execute 8822b 2-Ant PowerOn Setting xxxxxxxxxxxxxxxx!!\n");
+	BTC_TRACE(trace_buf);
+
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+		    "Ant Det Finish = %s, Ant Det Number  = %d\n",
+		    (board_info->btdm_ant_det_finish ? "Yes" : "No"),
+		    board_info->btdm_ant_num_by_ant_det);
+	BTC_TRACE(trace_buf);
+
+
+	btcoexist->stop_coex_dm = true;
+	psd_scan->ant_det_is_ant_det_available = false;
+
+	/* enable BB, REG_SYS_FUNC_EN such that we can write BB Register correctly. */
+	u16tmp = btcoexist->btc_read_2byte(btcoexist, 0x2);
+	btcoexist->btc_write_2byte(btcoexist, 0x2, u16tmp | BIT(0) | BIT(1));
+
+
+	/* Local setting bit define */
+	/*	BIT0: "0" for no antenna inverse; "1" for antenna inverse  */
+	/*	BIT1: "0" for internal switch; "1" for external switch */
+	/*	BIT2: "0" for one antenna; "1" for two antenna */
+	/* NOTE: here default all internal switch and 1-antenna ==> BIT1=0 and BIT2=0 */
+
+	/* Check efuse 0xc3[6] for Single Antenna Path */
+	if (board_info->single_ant_path == 0) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			"[BTCoex], **********  Single Antenna, Antenna at Aux Port\n");
+		BTC_TRACE(trace_buf);
+
+		board_info->btdm_ant_pos = BTC_ANTENNA_AT_AUX_PORT;
+
+		u8tmp = 7;
+	} else if (board_info->single_ant_path == 1) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			"[BTCoex], **********  Single Antenna, Antenna at Main Port\n");
+		BTC_TRACE(trace_buf);
+
+		board_info->btdm_ant_pos = BTC_ANTENNA_AT_MAIN_PORT;
+
+		u8tmp = 6;
+	}
+
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+		"[BTCoex], ********** (Power On) single_ant_path  = %d, btdm_ant_pos = %d\n",
+		    board_info->single_ant_path , board_info->btdm_ant_pos);
+	BTC_TRACE(trace_buf);
+
+	/* Setup RF front end type */
+	halbtc8822b2ant_set_rfe_type(btcoexist);
+
+	/* Set Antenna Path to BT side */
+	halbtc8822b2ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, FORCE_EXEC,
+				     BT_8822B_2ANT_PHASE_COEX_POWERON);
+
+	/* Save"single antenna position" info in Local register setting for FW reading, because FW may not ready at  power on */
+	if (btcoexist->chip_interface == BTC_INTF_PCI)
+		btcoexist->btc_write_local_reg_1byte(btcoexist, 0x3e0, u8tmp);
+	else if (btcoexist->chip_interface == BTC_INTF_USB)
+		btcoexist->btc_write_local_reg_1byte(btcoexist, 0xfe08, u8tmp);
+	else if (btcoexist->chip_interface == BTC_INTF_SDIO)
+		btcoexist->btc_write_local_reg_1byte(btcoexist, 0x60, u8tmp);
+
+	/* enable GNT_WL/GNT_BT debug signal to GPIO14/15 */
+	halbtc8822b2ant_enable_gnt_to_gpio(btcoexist, true);
+
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+		"[BTCoex], **********  LTE coex Reg 0x38 (Power-On) = 0x%x**********\n",
+		    halbtc8822b2ant_ltecoex_indirect_read_reg(btcoexist, 0x38));
+	BTC_TRACE(trace_buf);
+
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+		"[BTCoex], **********  MAC Reg 0x70/ BB Reg 0xcb4 (Power-On) = 0x%x / 0x%x\n",
+		    btcoexist->btc_read_4byte(btcoexist, 0x70),
+		    btcoexist->btc_read_4byte(btcoexist, 0xcb4));
+	BTC_TRACE(trace_buf);
+
+}
+
+void ex_halbtc8822b2ant_pre_load_firmware(IN struct btc_coexist *btcoexist)
+{
+	struct  btc_board_info	*board_info = &btcoexist->board_info;
+	u8 u8tmp = 0x4; /* Set BIT2 by default since it's 2ant case */
+
+	/* */
+	/* S0 or S1 setting and Local register setting(By the setting fw can get ant number, S0/S1, ... info) */
+	/* Local setting bit define */
+	/*	BIT0: "0" for no antenna inverse; "1" for antenna inverse  */
+	/*	BIT1: "0" for internal switch; "1" for external switch */
+	/*	BIT2: "0" for one antenna; "1" for two antenna */
+	/* NOTE: here default all internal switch and 1-antenna ==> BIT1=0 and BIT2=0 */
+	if (btcoexist->chip_interface == BTC_INTF_USB) {
+		/* fixed at S0 for USB interface */
+		u8tmp |= 0x1;	/* antenna inverse */
+		btcoexist->btc_write_local_reg_1byte(btcoexist, 0xfe08, u8tmp);
+	} else {
+		/* for PCIE and SDIO interface, we check efuse 0xc3[6] */
+		if (board_info->single_ant_path == 0) {
+		} else if (board_info->single_ant_path == 1) {
+			/* set to S0 */
+			u8tmp |= 0x1;	/* antenna inverse */
+		}
+
+		if (btcoexist->chip_interface == BTC_INTF_PCI)
+			btcoexist->btc_write_local_reg_1byte(btcoexist, 0x3e0,
+							     u8tmp);
+		else if (btcoexist->chip_interface == BTC_INTF_SDIO)
+			btcoexist->btc_write_local_reg_1byte(btcoexist, 0x60,
+							     u8tmp);
+	}
+}
+
+
+void ex_halbtc8822b2ant_init_hw_config(IN struct btc_coexist *btcoexist,
+				       IN boolean wifi_only)
+{
+	halbtc8822b2ant_init_hw_config(btcoexist, wifi_only);
+}
+
+void ex_halbtc8822b2ant_init_coex_dm(IN struct btc_coexist *btcoexist)
+{
+
+	halbtc8822b2ant_init_coex_dm(btcoexist);
+}
+
+void ex_halbtc8822b2ant_display_coex_info(IN struct btc_coexist *btcoexist)
+{
+	struct  btc_board_info		*board_info = &btcoexist->board_info;
+	struct  btc_bt_link_info	*bt_link_info = &btcoexist->bt_link_info;
+
+	u8				*cli_buf = btcoexist->cli_buf;
+	u8				u8tmp[4], i, ps_tdma_case = 0;
+	u32				u32tmp[4];
+	u16				u16tmp[4];
+	u32				fa_ofdm, fa_cck, cca_ofdm, cca_cck;
+	u32				fw_ver = 0, bt_patch_ver = 0, bt_coex_ver = 0;
+	static u8			pop_report_in_10s = 0;
+	u32			phyver = 0;
+	boolean			lte_coex_on = false;
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+		   "\r\n ============[BT Coexist info]============");
+	CL_PRINTF(cli_buf);
+
+	if (btcoexist->manual_control) {
+		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+			"\r\n ============[Under Manual Control]============");
+		CL_PRINTF(cli_buf);
+		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+			   "\r\n ==========================================");
+		CL_PRINTF(cli_buf);
+	}
+
+	if (psd_scan->ant_det_try_count == 0) {
+		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+			   "\r\n %-35s = %d/ %d/ %s / %d",
+			   "Ant PG Num/ Mech/ Pos/ RFE",
+			   board_info->pg_ant_num, board_info->btdm_ant_num,
+			   (board_info->btdm_ant_pos == BTC_ANTENNA_AT_MAIN_PORT
+			    ? "Main" : "Aux"),
+			   rfe_type->rfe_module_type);
+		CL_PRINTF(cli_buf);
+	} else {
+		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+			   "\r\n %-35s = %d/ %d/ %s/ %d  (%d/%d/%d)",
+			   "Ant PG Num/ Mech(Ant_Det)/ Pos/ RFE",
+			   board_info->pg_ant_num,
+			   board_info->btdm_ant_num_by_ant_det,
+			   (board_info->btdm_ant_pos == BTC_ANTENNA_AT_MAIN_PORT
+			    ? "Main" : "Aux"),
+			   rfe_type->rfe_module_type,
+			   psd_scan->ant_det_try_count,
+			   psd_scan->ant_det_fail_count,
+			   psd_scan->ant_det_result);
+		CL_PRINTF(cli_buf);
+
+
+		if (board_info->btdm_ant_det_finish) {
+
+			if (psd_scan->ant_det_result != 12)
+				CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s",
+					   "Ant Det PSD Value",
+					   psd_scan->ant_det_peak_val);
+			else
+				CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+					   "\r\n %-35s = %d",
+					   "Ant Det PSD Value",
+					   psd_scan->ant_det_psd_scan_peak_val
+					   / 100);
+			CL_PRINTF(cli_buf);
+		}
+	}
+
+
+	/*bt_patch_ver = btcoexist->bt_info.bt_get_fw_ver;*/
+	bt_patch_ver = btcoexist->bt_info.bt_get_fw_ver;
+	btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_FW_VER, &fw_ver);
+	phyver = btcoexist->btc_get_bt_phydm_version(btcoexist);
+
+	bt_coex_ver = (coex_sta->bt_coex_supported_version & 0xff);
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+		   "\r\n %-35s = %d_%02x/ 0x%02x/ 0x%02x (%s)",
+		   "CoexVer WL/  BT_Desired/ BT_Report",
+		   glcoex_ver_date_8822b_2ant, glcoex_ver_8822b_2ant,
+		   glcoex_ver_btdesired_8822b_2ant,
+		   bt_coex_ver,
+		   (bt_coex_ver == 0xff ? "Unknown" :
+		    (bt_coex_ver >= glcoex_ver_btdesired_8822b_2ant ?
+		     "Match" : "Mis-Match")));
+	CL_PRINTF(cli_buf);
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+		   "\r\n %-35s = 0x%x/ 0x%x/ v%d/ %c",
+		   "W_FW/ B_FW/ Phy/ Kt",
+		   fw_ver, bt_patch_ver, phyver,
+		   coex_sta->cut_version + 65);
+	CL_PRINTF(cli_buf);
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %02x %02x %02x ",
+		   "AFH Map to BT",
+		   coex_dm->wifi_chnl_info[0], coex_dm->wifi_chnl_info[1],
+		   coex_dm->wifi_chnl_info[2]);
+	CL_PRINTF(cli_buf);
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d / %d / %d ",
+		   "Isolation/WL_Thres/BT_Thres",
+		   coex_sta->isolation_btween_wb,
+		   coex_sta->wifi_coex_thres,
+		   coex_sta->bt_coex_thres);
+	CL_PRINTF(cli_buf);
+
+	/* wifi status */
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s",
+		   "============[Wifi Status]============");
+	CL_PRINTF(cli_buf);
+	btcoexist->btc_disp_dbg_msg(btcoexist, BTC_DBG_DISP_WIFI_STATUS);
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s",
+		   "============[BT Status]============");
+	CL_PRINTF(cli_buf);
+
+	pop_report_in_10s++;
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+		   "\r\n %-35s = [%s/ %d dBm/ %d/ %d] ",
+		   "BT [status/ rssi/ retryCnt/ popCnt]",
+		   ((coex_sta->bt_disabled) ? ("disabled") :	((
+			   coex_sta->c2h_bt_inquiry_page) ? ("inquiry/page")
+			   : ((BT_8822B_2ANT_BT_STATUS_NON_CONNECTED_IDLE ==
+			       coex_dm->bt_status) ? "non-connected idle" :
+		((BT_8822B_2ANT_BT_STATUS_CONNECTED_IDLE == coex_dm->bt_status)
+				       ? "connected-idle" : "busy")))),
+		   coex_sta->bt_rssi - 100, coex_sta->bt_retry_cnt,
+		   coex_sta->pop_event_cnt);
+	CL_PRINTF(cli_buf);
+
+	if (pop_report_in_10s >= 5) {
+		coex_sta->pop_event_cnt = 0;
+		pop_report_in_10s = 0;
+	}
+
+
+	if (coex_sta->num_of_profile != 0)
+		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+			   "\r\n %-35s = %s%s%s%s%s",
+			   "Profiles",
+			   ((bt_link_info->a2dp_exist) ? "A2DP," : ""),
+			   ((bt_link_info->sco_exist) ?  "SCO," : ""),
+			   ((bt_link_info->hid_exist) ?
+			    ((coex_sta->hid_busy_num >= 2) ? "HID(4/18)," :
+			     "HID(2/18),") : ""),
+			   ((bt_link_info->pan_exist) ?  "PAN," : ""),
+			   ((coex_sta->voice_over_HOGP) ? "Voice" : ""));
+	else
+		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+			   "\r\n %-35s = None", "Profiles");
+
+	CL_PRINTF(cli_buf);
+
+
+	if (bt_link_info->a2dp_exist) {
+		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s/ %d/ %s",
+			   "A2DP Rate/Bitpool/Auto_Slot",
+			   ((coex_sta->is_A2DP_3M) ? "3M" : "No_3M"),
+			   coex_sta->a2dp_bit_pool,
+			   ((coex_sta->is_autoslot) ? "On" : "Off")
+			   );
+		CL_PRINTF(cli_buf);
+	}
+
+	if (bt_link_info->hid_exist) {
+		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d",
+			   "HID PairNum/Forbid_Slot",
+			   coex_sta->hid_pair_cnt,
+			   coex_sta->forbidden_slot
+			  );
+		CL_PRINTF(cli_buf);
+	}
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s / %s/ 0x%x",
+		   "Role/IgnWlanAct/Feature",
+		   ((bt_link_info->slave_role) ? "Slave" : "Master"),
+		   ((coex_dm->cur_ignore_wlan_act) ? "Yes" : "No"),
+		   coex_sta->bt_coex_supported_feature);
+	CL_PRINTF(cli_buf);
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d/ %d/ %d",
+		   "ReInit/ReLink/IgnWlact/Page/NameReq",
+		   coex_sta->cnt_ReInit,
+		   coex_sta->cnt_setupLink,
+		   coex_sta->cnt_IgnWlanAct,
+		   coex_sta->cnt_Page,
+		   coex_sta->cnt_RemoteNameReq
+		  );
+	CL_PRINTF(cli_buf);
+
+	halbtc8822b2ant_read_score_board(btcoexist,	&u16tmp[0]);
+
+	if ((coex_sta->bt_reg_vendor_ae == 0xffff) ||
+	    (coex_sta->bt_reg_vendor_ac == 0xffff))
+		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = x/ x/ %04x",
+			   "0xae[4]/0xac[1:0]/Scoreboard", u16tmp[0]);
+	else
+		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+			   "\r\n %-35s = 0x%x/ 0x%x/ %04x",
+			   "0xae[4]/0xac[1:0]/Scoreboard",
+			   ((coex_sta->bt_reg_vendor_ae & BIT(4)) >> 4),
+			   coex_sta->bt_reg_vendor_ac & 0x3, u16tmp[0]);
+	CL_PRINTF(cli_buf);
+
+	for (i = 0; i < BT_INFO_SRC_8822B_2ANT_MAX; i++) {
+		if (coex_sta->bt_info_c2h_cnt[i]) {
+			CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+				"\r\n %-35s = %02x %02x %02x %02x %02x %02x %02x(%d)",
+				   glbt_info_src_8822b_2ant[i],
+				   coex_sta->bt_info_c2h[i][0],
+				   coex_sta->bt_info_c2h[i][1],
+				   coex_sta->bt_info_c2h[i][2],
+				   coex_sta->bt_info_c2h[i][3],
+				   coex_sta->bt_info_c2h[i][4],
+				   coex_sta->bt_info_c2h[i][5],
+				   coex_sta->bt_info_c2h[i][6],
+				   coex_sta->bt_info_c2h_cnt[i]);
+			CL_PRINTF(cli_buf);
+		}
+	}
+
+	/* Sw mechanism	 */
+	if (btcoexist->manual_control)
+		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s",
+			"============[mechanism] (before Manual)============");
+	else
+		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s",
+			   "============[Mechanism]============");
+
+	CL_PRINTF(cli_buf);
+
+
+	ps_tdma_case = coex_dm->cur_ps_tdma;
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+		   "\r\n %-35s = %02x %02x %02x %02x %02x (case-%d, %s, %s)",
+		   "TDMA",
+		   coex_dm->ps_tdma_para[0], coex_dm->ps_tdma_para[1],
+		   coex_dm->ps_tdma_para[2], coex_dm->ps_tdma_para[3],
+		   coex_dm->ps_tdma_para[4], ps_tdma_case,
+		   (coex_dm->cur_ps_tdma_on ? "TDMA On" : "TDMA Off"),
+		   (coex_dm->is_switch_to_1dot5_ant ? "1.5Ant" : "2Ant"));
+	CL_PRINTF(cli_buf);
+
+	u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x6c0);
+	u32tmp[1] = btcoexist->btc_read_4byte(btcoexist, 0x6c4);
+	u32tmp[2] = btcoexist->btc_read_4byte(btcoexist, 0x6c8);
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+		   "\r\n %-35s = %d/ 0x%x/ 0x%x/ 0x%x",
+		   "Table/0x6c0/0x6c4/0x6c8",
+		   coex_sta->coex_table_type, u32tmp[0], u32tmp[1], u32tmp[2]);
+	CL_PRINTF(cli_buf);
+
+	u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x778);
+	u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x6cc);
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+		   "\r\n %-35s = 0x%x/ 0x%x",
+		   "0x778/0x6cc",
+		   u8tmp[0], u32tmp[0]);
+	CL_PRINTF(cli_buf);
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s/ %s/ %s",
+		   "AntDiv/ForceLPS/LPRA",
+		   ((board_info->ant_div_cfg) ? "On" : "Off"),
+		   ((coex_sta->force_lps_on) ? "On" : "Off"),
+		   ((coex_dm->cur_low_penalty_ra) ? "On" : "Off"));
+	CL_PRINTF(cli_buf);
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x",
+		   "WL_DACSwing/ BT_Dec_Pwr", coex_dm->cur_fw_dac_swing_lvl,
+		   coex_dm->cur_bt_dec_pwr_lvl);
+	CL_PRINTF(cli_buf);
+
+	u32tmp[0] = halbtc8822b2ant_ltecoex_indirect_read_reg(btcoexist, 0x38);
+	lte_coex_on = ((u32tmp[0] & BIT(7)) >> 7) ?  true : false;
+
+	if (lte_coex_on) {
+
+		u32tmp[0] = halbtc8822b2ant_ltecoex_indirect_read_reg(btcoexist,
+				0xa0);
+		u32tmp[1] = halbtc8822b2ant_ltecoex_indirect_read_reg(btcoexist,
+				0xa4);
+		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x",
+			   "LTE Coex Table W_L/B_L",
+			   u32tmp[0] & 0xffff, u32tmp[1] & 0xffff);
+		CL_PRINTF(cli_buf);
+
+
+		u32tmp[0] = halbtc8822b2ant_ltecoex_indirect_read_reg(btcoexist,
+				0xa8);
+		u32tmp[1] = halbtc8822b2ant_ltecoex_indirect_read_reg(btcoexist,
+				0xac);
+		u32tmp[2] = halbtc8822b2ant_ltecoex_indirect_read_reg(btcoexist,
+				0xb0);
+		u32tmp[3] = halbtc8822b2ant_ltecoex_indirect_read_reg(btcoexist,
+				0xb4);
+		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+			   "\r\n %-35s = 0x%x/ 0x%x/ 0x%x/ 0x%x",
+			   "LTE Break Table W_L/B_L/L_W/L_B",
+			   u32tmp[0] & 0xffff, u32tmp[1] & 0xffff,
+			   u32tmp[2] & 0xffff, u32tmp[3] & 0xffff);
+		CL_PRINTF(cli_buf);
+
+	}
+
+	/* Hw setting		 */
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s",
+		   "============[Hw setting]============");
+	CL_PRINTF(cli_buf);
+	/*
+		u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x430);
+		u32tmp[1] = btcoexist->btc_read_4byte(btcoexist, 0x434);
+		u16tmp[0] = btcoexist->btc_read_2byte(btcoexist, 0x42a);
+		u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x456);
+		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/0x%x/0x%x/0x%x",
+			   "0x430/0x434/0x42a/0x456",
+			   u32tmp[0], u32tmp[1], u16tmp[0], u8tmp[0]);
+		CL_PRINTF(cli_buf);
+	*/
+	u32tmp[0] = halbtc8822b2ant_ltecoex_indirect_read_reg(btcoexist, 0x38);
+	u32tmp[1] = halbtc8822b2ant_ltecoex_indirect_read_reg(btcoexist, 0x54);
+	u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x73);
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s/ %s",
+		   "LTE Coex/Path Owner",
+		   ((lte_coex_on) ? "On" : "Off") ,
+		   ((u8tmp[0] & BIT(2)) ? "WL" : "BT"));
+	CL_PRINTF(cli_buf);
+
+	if (lte_coex_on) {
+		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d/ %d",
+			   "LTE 3Wire/OPMode/UART/UARTMode",
+			   (int)((u32tmp[0] & BIT(6)) >> 6),
+			   (int)((u32tmp[0] & (BIT(5) | BIT(4))) >> 4),
+			   (int)((u32tmp[0] & BIT(3)) >> 3),
+			   (int)(u32tmp[0] & (BIT(2) | BIT(1) | BIT(0))));
+		CL_PRINTF(cli_buf);
+
+		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d",
+			   "LTE_Busy/UART_Busy",
+			(int)((u32tmp[1] & BIT(1)) >> 1), (int)(u32tmp[1] & BIT(0)));
+		CL_PRINTF(cli_buf);
+	}
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+		   "\r\n %-35s = %s (BB:%s)/ %s (BB:%s)/ %s",
+		   "GNT_WL_Ctrl/GNT_BT_Ctrl/Dbg",
+		   ((u32tmp[0] & BIT(12)) ? "SW" : "HW"),
+		   ((u32tmp[0] & BIT(8)) ?  "SW" : "HW"),
+		   ((u32tmp[0] & BIT(14)) ? "SW" : "HW"),
+		   ((u32tmp[0] & BIT(10)) ?  "SW" : "HW"),
+		   ((u8tmp[0] & BIT(3)) ? "On" : "Off"));
+	CL_PRINTF(cli_buf);
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d",
+		   "GNT_WL/GNT_BT",
+		   (int)((u32tmp[1] & BIT(2)) >> 2),
+		   (int)((u32tmp[1] & BIT(3)) >> 3));
+	CL_PRINTF(cli_buf);
+
+	u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0xcb0);
+	u32tmp[1] = btcoexist->btc_read_4byte(btcoexist, 0xcb4);
+	u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0xcbd);
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+		   "\r\n %-35s = 0x%04x/ 0x%04x/ 0x%x",
+		   "0xcb0/0xcb4/0xcbd",
+		   u32tmp[0], u32tmp[1], u8tmp[0]);
+	CL_PRINTF(cli_buf);
+
+	u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x4c);
+	u8tmp[2] = btcoexist->btc_read_1byte(btcoexist, 0x64);
+	u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x4c6);
+	u8tmp[1] = btcoexist->btc_read_1byte(btcoexist, 0x40);
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+		   "\r\n %-35s = 0x%x/ 0x%x/ 0x%x/ 0x%x",
+		   "0x4c[24:23]/0x64[0]/x4c6[4]/0x40[5]",
+		   (u32tmp[0] & (BIT(24) | BIT(23))) >> 23 , u8tmp[2] & 0x1 ,
+		   (int)((u8tmp[0] & BIT(4)) >> 4),
+		   (int)((u8tmp[1] & BIT(5)) >> 5));
+	CL_PRINTF(cli_buf);
+
+	u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x550);
+	u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x522);
+	u8tmp[1] = btcoexist->btc_read_1byte(btcoexist, 0x953);
+	u8tmp[2] = btcoexist->btc_read_1byte(btcoexist, 0xc50);
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+		   "\r\n %-35s = 0x%x/ 0x%x/ %s/ 0x%x",
+		   "0x550/0x522/4-RxAGC/0xc50",
+		u32tmp[0], u8tmp[0], (u8tmp[1] & 0x2) ? "On" : "Off", u8tmp[2]);
+	CL_PRINTF(cli_buf);
+
+	fa_ofdm = btcoexist->btc_phydm_query_PHY_counter(btcoexist,
+			PHYDM_INFO_FA_OFDM);
+	fa_cck = btcoexist->btc_phydm_query_PHY_counter(btcoexist,
+			PHYDM_INFO_FA_CCK);
+	cca_ofdm = btcoexist->btc_phydm_query_PHY_counter(btcoexist,
+			PHYDM_INFO_CCA_OFDM);
+	cca_cck = btcoexist->btc_phydm_query_PHY_counter(btcoexist,
+			PHYDM_INFO_CCA_CCK);
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+		   "\r\n %-35s = 0x%x/ 0x%x/ 0x%x/ 0x%x",
+		   "CCK-CCA/CCK-FA/OFDM-CCA/OFDM-FA",
+		   cca_cck, fa_cck, cca_ofdm, fa_ofdm);
+	CL_PRINTF(cli_buf);
+
+#if 1
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d/ %d",
+		   "CRC_OK CCK/11g/11n/11ac",
+		   coex_sta->crc_ok_cck, coex_sta->crc_ok_11g,
+		   coex_sta->crc_ok_11n, coex_sta->crc_ok_11n_vht);
+	CL_PRINTF(cli_buf);
+
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d/ %d",
+		   "CRC_Err CCK/11g/11n/11ac",
+		   coex_sta->crc_err_cck, coex_sta->crc_err_11g,
+		   coex_sta->crc_err_11n, coex_sta->crc_err_11n_vht);
+	CL_PRINTF(cli_buf);
+#endif
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d",
+		   "0x770(Hi-pri rx/tx)",
+		   coex_sta->high_priority_rx, coex_sta->high_priority_tx);
+	CL_PRINTF(cli_buf);
+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d",
+		   "0x774(Lo-pri rx/tx)",
+		   coex_sta->low_priority_rx, coex_sta->low_priority_tx);
+	CL_PRINTF(cli_buf);
+
+	btcoexist->btc_disp_dbg_msg(btcoexist, BTC_DBG_DISP_COEX_STATISTICS);
+}
+
+
+void ex_halbtc8822b2ant_ips_notify(IN struct btc_coexist *btcoexist, IN u8 type)
+{
+	if (btcoexist->manual_control ||	btcoexist->stop_coex_dm)
+		return;
+
+	if (BTC_IPS_ENTER == type) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], IPS ENTER notify\n");
+		BTC_TRACE(trace_buf);
+		coex_sta->under_ips = true;
+		coex_sta->under_lps = false;
+
+		halbtc8822b2ant_post_state_to_bt(btcoexist,
+				 BT_8822B_2ANT_SCOREBOARD_ACTIVE, false);
+
+		halbtc8822b2ant_post_state_to_bt(btcoexist,
+				 BT_8822B_2ANT_SCOREBOARD_ONOFF, false);
+
+		halbtc8822b2ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO,
+					     FORCE_EXEC,
+					     BT_8822B_2ANT_PHASE_WLAN_OFF);
+
+		halbtc8822b2ant_action_coex_all_off(btcoexist);
+	} else if (BTC_IPS_LEAVE == type) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], IPS LEAVE notify\n");
+		BTC_TRACE(trace_buf);
+		coex_sta->under_ips = false;
+
+		halbtc8822b2ant_post_state_to_bt(btcoexist,
+					 BT_8822B_2ANT_SCOREBOARD_ACTIVE, true);
+		halbtc8822b2ant_post_state_to_bt(btcoexist,
+				 BT_8822B_2ANT_SCOREBOARD_ONOFF, true);
+		halbtc8822b2ant_init_hw_config(btcoexist, false);
+		halbtc8822b2ant_init_coex_dm(btcoexist);
+		halbtc8822b2ant_query_bt_info(btcoexist);
+	}
+}
+
+void ex_halbtc8822b2ant_lps_notify(IN struct btc_coexist *btcoexist, IN u8 type)
+{
+	if (btcoexist->manual_control || btcoexist->stop_coex_dm)
+		return;
+
+	if (BTC_LPS_ENABLE == type) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], LPS ENABLE notify\n");
+		BTC_TRACE(trace_buf);
+		coex_sta->under_lps = true;
+		coex_sta->under_ips = false;
+
+		if (coex_sta->force_lps_on == true) { /* LPS No-32K */
+			/* Write WL "Active" in Score-board for PS-TDMA */
+			halbtc8822b2ant_post_state_to_bt(btcoexist,
+					 BT_8822B_2ANT_SCOREBOARD_ACTIVE, true);
+
+		} else { /* LPS-32K, need check if this h2c 0x71 can work?? (2015/08/28) */
+			/* Write WL "Non-Active" in Score-board for Native-PS */
+			halbtc8822b2ant_post_state_to_bt(btcoexist,
+				 BT_8822B_2ANT_SCOREBOARD_ACTIVE, false);
+		}
+
+
+	} else if (BTC_LPS_DISABLE == type) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], LPS DISABLE notify\n");
+		BTC_TRACE(trace_buf);
+		coex_sta->under_lps = false;
+
+		halbtc8822b2ant_post_state_to_bt(btcoexist,
+					 BT_8822B_2ANT_SCOREBOARD_ACTIVE, true);
+	}
+}
+
+void ex_halbtc8822b2ant_scan_notify(IN struct btc_coexist *btcoexist,
+				    IN u8 type)
+{
+	boolean	wifi_connected = false;
+	boolean wifi_under_5g = false;
+
+
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+		    "[BTCoex], SCAN notify()\n");
+	BTC_TRACE(trace_buf);
+
+	halbtc8822b2ant_post_state_to_bt(btcoexist,
+					 BT_8822B_2ANT_SCOREBOARD_ACTIVE, true);
+
+	if (btcoexist->manual_control ||
+	    btcoexist->stop_coex_dm)
+		return;
+
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED,
+			   &wifi_connected);
+
+	/*  this can't be removed for RF off_on event, or BT would dis-connect */
+	halbtc8822b2ant_query_bt_info(btcoexist);
+
+	if (BTC_SCAN_START == type) {
+
+		btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_5G,
+				   &wifi_under_5g);
+
+		if (wifi_under_5g) {
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				"[BTCoex], ********** SCAN START notify (5g)\n");
+			BTC_TRACE(trace_buf);
+
+			halbtc8822b2ant_action_wifi_under5g(btcoexist);
+			return;
+		}
+
+		coex_sta->wifi_is_high_pri_task = true;
+
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			"[BTCoex], ********** SCAN START notify (2g)\n");
+		BTC_TRACE(trace_buf);
+
+		halbtc8822b2ant_run_coexist_mechanism(
+			btcoexist);
+
+		return;
+	}
+
+
+	if (BTC_SCAN_START_2G == type) {
+
+		if (!wifi_connected)
+			coex_sta->wifi_is_high_pri_task = true;
+
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], SCAN START notify (2G)\n");
+		BTC_TRACE(trace_buf);
+
+		halbtc8822b2ant_post_state_to_bt(btcoexist,
+					 BT_8822B_2ANT_SCOREBOARD_SCAN, true);
+		halbtc8822b2ant_post_state_to_bt(btcoexist,
+					 BT_8822B_2ANT_SCOREBOARD_ACTIVE, true);
+
+		halbtc8822b2ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO,
+					     FORCE_EXEC,
+					     BT_8822B_2ANT_PHASE_2G_RUNTIME);
+
+		halbtc8822b2ant_run_coexist_mechanism(btcoexist);
+
+	} else if (BTC_SCAN_FINISH == type) {
+
+		coex_sta->wifi_is_high_pri_task = false;
+
+		btcoexist->btc_get(btcoexist, BTC_GET_U1_AP_NUM,
+				   &coex_sta->scan_ap_num);
+
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], SCAN FINISH notify  (Scan-AP = %d)\n",
+			    coex_sta->scan_ap_num);
+		BTC_TRACE(trace_buf);
+
+		halbtc8822b2ant_post_state_to_bt(btcoexist,
+					 BT_8822B_2ANT_SCOREBOARD_SCAN, false);
+
+		halbtc8822b2ant_run_coexist_mechanism(btcoexist);
+	}
+
+}
+
+void ex_halbtc8822b2ant_switchband_notify(IN struct btc_coexist *btcoexist,
+		IN u8 type)
+{
+
+	boolean wifi_connected = false, bt_hs_on = false;
+	u32	wifi_link_status = 0;
+	u32	num_of_wifi_link = 0;
+	boolean	bt_ctrl_agg_buf_size = false;
+	u8	agg_buf_size = 5;
+
+
+	if (btcoexist->manual_control ||
+	    btcoexist->stop_coex_dm)
+		return;
+
+	if (type == BTC_SWITCH_TO_5G) {
+
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], switchband_notify ---  switch to 5G\n");
+		BTC_TRACE(trace_buf);
+
+		halbtc8822b2ant_action_wifi_under5g(btcoexist);
+
+	} else if (type == BTC_SWITCH_TO_24G_NOFORSCAN) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			"[BTCoex], ********** switchband_notify BTC_SWITCH_TO_2G (no for scan)\n");
+		BTC_TRACE(trace_buf);
+
+		halbtc8822b2ant_run_coexist_mechanism(btcoexist);
+
+	} else {
+
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], switchband_notify ---  switch to 2G\n");
+		BTC_TRACE(trace_buf);
+
+		ex_halbtc8822b2ant_scan_notify(btcoexist,
+					       BTC_SCAN_START_2G);
+	}
+}
+
+
+void ex_halbtc8822b2ant_connect_notify(IN struct btc_coexist *btcoexist,
+				       IN u8 type)
+{
+
+	halbtc8822b2ant_post_state_to_bt(btcoexist,
+					 BT_8822B_2ANT_SCOREBOARD_ACTIVE, true);
+	if (btcoexist->manual_control ||
+	    btcoexist->stop_coex_dm)
+		return;
+
+	if ((BTC_ASSOCIATE_5G_START == type) ||
+	    (BTC_ASSOCIATE_5G_FINISH == type)) {
+
+		if (BTC_ASSOCIATE_5G_START == type)
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				    "[BTCoex], connect_notify ---  5G start\n");
+		else
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				"[BTCoex], connect_notify ---  5G finish\n");
+
+		BTC_TRACE(trace_buf);
+
+		halbtc8822b2ant_action_wifi_under5g(btcoexist);
+		return;
+	}
+
+
+	if (BTC_ASSOCIATE_START == type) {
+
+		coex_sta->wifi_is_high_pri_task = true;
+
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], CONNECT START notify (2G)\n");
+		BTC_TRACE(trace_buf);
+
+		halbtc8822b2ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO,
+					     FORCE_EXEC,
+					     BT_8822B_2ANT_PHASE_2G_RUNTIME);
+
+		halbtc8822b2ant_action_wifi_link_process(btcoexist);
+
+		/* To keep TDMA case during connect process,
+		to avoid changed by Btinfo and runcoexmechanism */
+		coex_sta->freeze_coexrun_by_btinfo = true;
+
+		coex_dm->arp_cnt = 0;
+
+	} else if (BTC_ASSOCIATE_FINISH == type) {
+
+		coex_sta->wifi_is_high_pri_task = false;
+		coex_sta->freeze_coexrun_by_btinfo = false;
+
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], CONNECT FINISH notify	(2G)\n");
+		BTC_TRACE(trace_buf);
+
+		halbtc8822b2ant_run_coexist_mechanism(btcoexist);
+	}
+}
+
+void ex_halbtc8822b2ant_media_status_notify(IN struct btc_coexist *btcoexist,
+		IN u8 type)
+{
+	u8			h2c_parameter[3] = {0};
+	u32			wifi_bw;
+	u8			wifi_central_chnl;
+	u8			ap_num = 0;
+	boolean		wifi_under_b_mode = false, wifi_under_5g = false;
+
+
+	if (btcoexist->manual_control ||
+	    btcoexist->stop_coex_dm)
+		return;
+
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_5G, &wifi_under_5g);
+
+	if (BTC_MEDIA_CONNECT == type) {
+
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], MEDIA connect notify\n");
+		BTC_TRACE(trace_buf);
+
+		halbtc8822b2ant_post_state_to_bt(btcoexist,
+					 BT_8822B_2ANT_SCOREBOARD_ACTIVE, true);
+
+		if (wifi_under_5g) {
+
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				    "[BTCoex], WiFi is under 5G!!!\n");
+			BTC_TRACE(trace_buf);
+
+			halbtc8822b2ant_action_wifi_under5g(btcoexist);
+			return;
+		}
+
+		halbtc8822b2ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO,
+					     FORCE_EXEC,
+					     BT_8822B_2ANT_PHASE_2G_RUNTIME);
+
+		btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_B_MODE,
+				   &wifi_under_b_mode);
+
+		/* Set CCK Tx/Rx high Pri except 11b mode */
+		if (wifi_under_b_mode) {
+			btcoexist->btc_write_1byte(btcoexist, 0x6cd,
+						   0x00); /* CCK Tx */
+			btcoexist->btc_write_1byte(btcoexist, 0x6cf,
+						   0x00); /* CCK Rx */
+		} else {
+
+			btcoexist->btc_write_1byte(btcoexist, 0x6cd,
+						   0x00); /* CCK Tx */
+			btcoexist->btc_write_1byte(btcoexist, 0x6cf,
+						   0x10); /* CCK Rx */
+		}
+
+	} else {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], MEDIA disconnect notify\n");
+		BTC_TRACE(trace_buf);
+
+		btcoexist->btc_write_1byte(btcoexist, 0x6cd, 0x0); /* CCK Tx */
+		btcoexist->btc_write_1byte(btcoexist, 0x6cf, 0x0); /* CCK Rx */
+
+		halbtc8822b2ant_post_state_to_bt(btcoexist,
+				 BT_8822B_2ANT_SCOREBOARD_ACTIVE, false);
+	}
+
+
+	halbtc8822b2ant_update_wifi_channel_info(btcoexist, type);
+}
+
+void ex_halbtc8822b2ant_specific_packet_notify(IN struct btc_coexist *btcoexist,
+		IN u8 type)
+{
+	boolean under_4way = false, wifi_under_5g = false;
+
+	if (btcoexist->manual_control ||
+	    btcoexist->stop_coex_dm)
+		return;
+
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_5G, &wifi_under_5g);
+
+	if (wifi_under_5g) {
+
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], WiFi is under 5G!!!\n");
+		BTC_TRACE(trace_buf);
+
+		halbtc8822b2ant_action_wifi_under5g(btcoexist);
+		return;
+	}
+
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_4_WAY_PROGRESS,
+			   &under_4way);
+
+	if (under_4way) {
+
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], specific Packet ---- under_4way!!\n");
+		BTC_TRACE(trace_buf);
+
+		coex_sta->wifi_is_high_pri_task = true;
+		coex_sta->specific_pkt_period_cnt = 2;
+
+	} else if (BTC_PACKET_ARP == type) {
+
+		coex_dm->arp_cnt++;
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], specific Packet ARP notify -cnt = %d\n",
+			    coex_dm->arp_cnt);
+		BTC_TRACE(trace_buf);
+
+	} else {
+
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			"[BTCoex], specific Packet DHCP or EAPOL notify [Type = %d]\n",
+			    type);
+		BTC_TRACE(trace_buf);
+
+		coex_sta->wifi_is_high_pri_task = true;
+		coex_sta->specific_pkt_period_cnt = 2;
+	}
+
+	if (coex_sta->wifi_is_high_pri_task)
+		halbtc8822b2ant_run_coexist_mechanism(btcoexist);
+
+}
+
+void ex_halbtc8822b2ant_bt_info_notify(IN struct btc_coexist *btcoexist,
+				       IN u8 *tmp_buf, IN u8 length)
+{
+	u8			i, rsp_source = 0;
+	boolean			wifi_connected = false;
+
+	if (psd_scan->is_AntDet_running == true) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			"[BTCoex], bt_info_notify return for AntDet is running\n");
+		BTC_TRACE(trace_buf);
+		return;
+	}
+
+	rsp_source = tmp_buf[0] & 0xf;
+	if (rsp_source >= BT_INFO_SRC_8822B_2ANT_MAX)
+		rsp_source = BT_INFO_SRC_8822B_2ANT_WIFI_FW;
+	coex_sta->bt_info_c2h_cnt[rsp_source]++;
+
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+		    "[BTCoex], Bt_info[%d], len=%d, data=[", rsp_source,
+		    length);
+	BTC_TRACE(trace_buf);
+
+	for (i = 0; i < length; i++) {
+		coex_sta->bt_info_c2h[rsp_source][i] = tmp_buf[i];
+
+		if (i == length - 1) {
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "0x%02x]\n",
+				    tmp_buf[i]);
+			BTC_TRACE(trace_buf);
+		} else {
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "0x%02x, ",
+				    tmp_buf[i]);
+			BTC_TRACE(trace_buf);
+		}
+	}
+
+	coex_sta->bt_info = coex_sta->bt_info_c2h[rsp_source][1];
+	coex_sta->bt_info_ext = coex_sta->bt_info_c2h[rsp_source][4];
+	coex_sta->bt_info_ext2 = coex_sta->bt_info_c2h[rsp_source][5];
+
+	if (BT_INFO_SRC_8822B_2ANT_WIFI_FW != rsp_source) {
+
+		/* if 0xff, it means BT is under WHCK test */
+		coex_sta->bt_whck_test = ((coex_sta->bt_info == 0xff) ? true :
+					  false);
+
+		coex_sta->bt_create_connection = ((
+			coex_sta->bt_info_c2h[rsp_source][2] & 0x80) ? true :
+						  false);
+
+		/* unit: %, value-100 to translate to unit: dBm */
+		coex_sta->bt_rssi = coex_sta->bt_info_c2h[rsp_source][3] * 2 +
+				    10;
+
+		coex_sta->c2h_bt_remote_name_req = ((
+			coex_sta->bt_info_c2h[rsp_source][2] & 0x20) ? true :
+						    false);
+
+		coex_sta->is_A2DP_3M = ((coex_sta->bt_info_c2h[rsp_source][2] &
+					 0x10) ? true : false);
+
+		coex_sta->acl_busy = ((coex_sta->bt_info_c2h[rsp_source][1] &
+				       0x9) ? true : false);
+
+		coex_sta->voice_over_HOGP = ((coex_sta->bt_info_ext & 0x10) ?
+					     true : false);
+
+		coex_sta->c2h_bt_inquiry_page = ((coex_sta->bt_info &
+			  BT_INFO_8822B_2ANT_B_INQ_PAGE) ? true : false);
+
+		coex_sta->a2dp_bit_pool = (((
+			coex_sta->bt_info_c2h[rsp_source][1] & 0x49) == 0x49) ?
+				   coex_sta->bt_info_c2h[rsp_source][6] : 0);
+
+		coex_sta->bt_retry_cnt = coex_sta->bt_info_c2h[rsp_source][2] &
+					 0xf;
+
+		coex_sta->is_autoslot = coex_sta->bt_info_ext2 & 0x8;
+
+		coex_sta->forbidden_slot = coex_sta->bt_info_ext2 & 0x7;
+
+		coex_sta->hid_busy_num = (coex_sta->bt_info_ext2 & 0x30) >> 4;
+
+		coex_sta->hid_pair_cnt = (coex_sta->bt_info_ext2 & 0xc0) >> 6;
+
+		if (coex_sta->bt_retry_cnt >= 1)
+			coex_sta->pop_event_cnt++;
+
+		if (coex_sta->c2h_bt_remote_name_req)
+			coex_sta->cnt_RemoteNameReq++;
+
+		if (coex_sta->bt_info_ext & BIT(1))
+			coex_sta->cnt_ReInit++;
+
+		if (coex_sta->bt_info_ext & BIT(2)) {
+			coex_sta->cnt_setupLink++;
+			coex_sta->is_setupLink = true;
+		} else
+			coex_sta->is_setupLink = false;
+
+		if (coex_sta->bt_info_ext & BIT(3))
+			coex_sta->cnt_IgnWlanAct++;
+
+		if (coex_sta->bt_create_connection)
+			coex_sta->cnt_Page++;
+
+		/* Here we need to resend some wifi info to BT */
+		/* because bt is reset and loss of the info. */
+
+		if ((!btcoexist->manual_control) &&
+		    (!btcoexist->stop_coex_dm)) {
+
+			btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED,
+					   &wifi_connected);
+
+			/*  Re-Init */
+			if ((coex_sta->bt_info_ext & BIT(1))) {
+				BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+					"[BTCoex], BT ext info bit1 check, send wifi BW&Chnl to BT!!\n");
+				BTC_TRACE(trace_buf);
+				if (wifi_connected)
+					halbtc8822b2ant_update_wifi_channel_info(
+						btcoexist, BTC_MEDIA_CONNECT);
+				else
+					halbtc8822b2ant_update_wifi_channel_info(
+						btcoexist,
+						BTC_MEDIA_DISCONNECT);
+			}
+
+
+			/*  If Ignore_WLanAct && not SetUp_Link */
+			if ((coex_sta->bt_info_ext & BIT(3)) &&
+			    (!(coex_sta->bt_info_ext & BIT(2)))) {
+
+				BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+					"[BTCoex], BT ext info bit3 check, set BT NOT to ignore Wlan active!!\n");
+				BTC_TRACE(trace_buf);
+				halbtc8822b2ant_ignore_wlan_act(btcoexist,
+							FORCE_EXEC, false);
+			}
+		}
+
+	}
+
+
+	halbtc8822b2ant_update_bt_link_info(btcoexist);
+
+	if (btcoexist->manual_control) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			"[BTCoex], BtInfoNotify(), No run_coexist_mechanism for Manual CTRL\n");
+		BTC_TRACE(trace_buf);
+		return;
+	}
+
+	if (btcoexist->stop_coex_dm) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			"[BTCoex], BtInfoNotify(),  No run_coexist_mechanism for Stop Coex DM\n");
+		BTC_TRACE(trace_buf);
+		return;
+	}
+
+	coex_sta->c2h_bt_info_req_sent = false;
+
+	halbtc8822b2ant_run_coexist_mechanism(btcoexist);
+}
+
+void ex_halbtc8822b2ant_rf_status_notify(IN struct btc_coexist *btcoexist,
+		IN u8 type)
+{
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], RF Status notify\n");
+	BTC_TRACE(trace_buf);
+
+	if (BTC_RF_ON == type) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], RF is turned ON!!\n");
+		BTC_TRACE(trace_buf);
+
+		coex_sta->wl_rf_off_on_event = true;
+		btcoexist->stop_coex_dm = false;
+
+		halbtc8822b2ant_post_state_to_bt(btcoexist,
+					 BT_8822B_2ANT_SCOREBOARD_ACTIVE, true);
+		halbtc8822b2ant_post_state_to_bt(btcoexist,
+					 BT_8822B_2ANT_SCOREBOARD_ONOFF, true);
+	} else if (BTC_RF_OFF == type) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], RF is turned OFF!!\n");
+		BTC_TRACE(trace_buf);
+
+		halbtc8822b2ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO,
+					     FORCE_EXEC,
+					     BT_8822B_2ANT_PHASE_WLAN_OFF);
+
+		halbtc8822b2ant_action_coex_all_off(btcoexist);
+
+		halbtc8822b2ant_post_state_to_bt(btcoexist,
+				 BT_8822B_2ANT_SCOREBOARD_ACTIVE, false);
+		halbtc8822b2ant_post_state_to_bt(btcoexist,
+					 BT_8822B_2ANT_SCOREBOARD_ONOFF, false);
+		btcoexist->stop_coex_dm = true;
+		coex_sta->wl_rf_off_on_event = false;
+
+	}
+}
+
+void ex_halbtc8822b2ant_halt_notify(IN struct btc_coexist *btcoexist)
+{
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], Halt notify\n");
+	BTC_TRACE(trace_buf);
+
+	halbtc8822b2ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, FORCE_EXEC,
+				     BT_8822B_2ANT_PHASE_WLAN_OFF);
+
+	ex_halbtc8822b2ant_media_status_notify(btcoexist, BTC_MEDIA_DISCONNECT);
+
+	halbtc8822b2ant_post_state_to_bt(btcoexist,
+				 BT_8822B_2ANT_SCOREBOARD_ACTIVE, false);
+	halbtc8822b2ant_post_state_to_bt(btcoexist,
+					 BT_8822B_2ANT_SCOREBOARD_ONOFF, false);
+}
+
+void ex_halbtc8822b2ant_pnp_notify(IN struct btc_coexist *btcoexist,
+				   IN u8 pnp_state)
+{
+	boolean wifi_under_5g = false;
+
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], Pnp notify\n");
+	BTC_TRACE(trace_buf);
+
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_5G, &wifi_under_5g);
+
+	if ((BTC_WIFI_PNP_SLEEP == pnp_state) ||
+	    (BTC_WIFI_PNP_SLEEP_KEEP_ANT == pnp_state)) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], Pnp notify to SLEEP\n");
+		BTC_TRACE(trace_buf);
+
+		/* Sinda 20150819, workaround for driver skip leave IPS/LPS to speed up sleep time. */
+		/* Driver do not leave IPS/LPS when driver is going to sleep, so BTCoexistence think wifi is still under IPS/LPS */
+		/* BT should clear UnderIPS/UnderLPS state to avoid mismatch state after wakeup. */
+		coex_sta->under_ips = false;
+		coex_sta->under_lps = false;
+
+		halbtc8822b2ant_post_state_to_bt(btcoexist,
+				 BT_8822B_2ANT_SCOREBOARD_ACTIVE, false);
+		halbtc8822b2ant_post_state_to_bt(btcoexist,
+					 BT_8822B_2ANT_SCOREBOARD_ONOFF, false);
+
+
+		if (BTC_WIFI_PNP_SLEEP_KEEP_ANT == pnp_state) {
+
+			if (wifi_under_5g)
+				halbtc8822b2ant_set_ant_path(btcoexist,
+					     BTC_ANT_PATH_AUTO, FORCE_EXEC,
+					     BT_8822B_2ANT_PHASE_5G_RUNTIME);
+			else
+				halbtc8822b2ant_set_ant_path(btcoexist,
+					     BTC_ANT_PATH_AUTO, FORCE_EXEC,
+					     BT_8822B_2ANT_PHASE_2G_RUNTIME);
+		} else {
+
+			halbtc8822b2ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO,
+						     FORCE_EXEC,
+					     BT_8822B_2ANT_PHASE_WLAN_OFF);
+		}
+	} else if (BTC_WIFI_PNP_WAKE_UP == pnp_state) {
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			    "[BTCoex], Pnp notify to WAKE UP\n");
+		BTC_TRACE(trace_buf);
+
+		halbtc8822b2ant_post_state_to_bt(btcoexist,
+					 BT_8822B_2ANT_SCOREBOARD_ACTIVE, true);
+		halbtc8822b2ant_post_state_to_bt(btcoexist,
+					 BT_8822B_2ANT_SCOREBOARD_ONOFF, true);
+	}
+}
+
+void ex_halbtc8822b2ant_periodical(IN struct btc_coexist *btcoexist)
+{
+	struct  btc_board_info	*board_info = &btcoexist->board_info;
+	boolean wifi_busy = false;
+	u32 bt_patch_ver;
+	u16 bt_scoreboard_val = 0;
+	static u8 cnt = 0;
+	boolean bt_relink_finish = false;
+
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+		    "[BTCoex], ************* Periodical *************\n");
+	BTC_TRACE(trace_buf);
+
+#if (BT_AUTO_REPORT_ONLY_8822B_2ANT == 0)
+	halbtc8822b2ant_query_bt_info(btcoexist);
+#endif
+
+	halbtc8822b2ant_monitor_bt_ctr(btcoexist);
+	halbtc8822b2ant_monitor_wifi_ctr(btcoexist);
+	halbtc8822b2ant_monitor_bt_enable_disable(btcoexist);
+
+#if 1
+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy);
+	halbtc8822b2ant_read_score_board(btcoexist, &bt_scoreboard_val);
+
+	if (wifi_busy) {
+		halbtc8822b2ant_post_state_to_bt(btcoexist,
+				BT_8822B_2ANT_SCOREBOARD_UNDERTEST, true);
+		/*for bt lps32 clock offset*/
+		if (bt_scoreboard_val & BIT(6))
+			halbtc8822b2ant_query_bt_info(btcoexist);
+	} else {
+		halbtc8822b2ant_post_state_to_bt(btcoexist,
+			BT_8822B_2ANT_SCOREBOARD_UNDERTEST, false);
+		/*
+		halbtc8822b2ant_post_state_to_bt(btcoexist,
+			BT_8822B_2ANT_SCOREBOARD_WLBUSY,
+				false);  */
+	}
+#endif
+
+	if (coex_sta->bt_relink_downcount != 0) {
+		coex_sta->bt_relink_downcount--;
+
+		if (coex_sta->bt_relink_downcount == 0)
+			bt_relink_finish = true;
+	}
+
+	/* for 4-way, DHCP, EAPOL packet */
+	if (coex_sta->specific_pkt_period_cnt > 0) {
+
+		coex_sta->specific_pkt_period_cnt--;
+
+		if ((coex_sta->specific_pkt_period_cnt == 0) &&
+		    (coex_sta->wifi_is_high_pri_task))
+			coex_sta->wifi_is_high_pri_task = false;
+
+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+			"[BTCoex], ***************** Hi-Pri Task = %s*****************\n",
+			    (coex_sta->wifi_is_high_pri_task ? "Yes" :
+			     "No"));
+		BTC_TRACE(trace_buf);
+
+	}
+
+	if (!coex_sta->bt_disabled) {
+		if (coex_sta->bt_coex_supported_feature == 0)
+			btcoexist->btc_get(btcoexist, BTC_GET_U4_SUPPORTED_FEATURE, &coex_sta->bt_coex_supported_feature);
+
+		if ((coex_sta->bt_coex_supported_version == 0) ||
+			(coex_sta->bt_coex_supported_version == 0xffff))
+			btcoexist->btc_get(btcoexist, BTC_GET_U4_SUPPORTED_VERSION, &coex_sta->bt_coex_supported_version);
+
+		/*coex_sta->bt_ble_scan_type = btcoexist->btc_get_ble_scan_type_from_bt(btcoexist);*/
+		btcoexist->btc_get(btcoexist, BTC_GET_U4_BT_PATCH_VER, &bt_patch_ver);
+		btcoexist->bt_info.bt_get_fw_ver = bt_patch_ver;
+
+		if (coex_sta->bt_reg_vendor_ac == 0xffff)
+			coex_sta->bt_reg_vendor_ac = (u16)(
+				     btcoexist->btc_get_bt_reg(btcoexist, 3,
+							     0xac) & 0xffff);
+
+		if (coex_sta->bt_reg_vendor_ae == 0xffff)
+			coex_sta->bt_reg_vendor_ae = (u16)(
+				     btcoexist->btc_get_bt_reg(btcoexist, 3,
+							     0xae) & 0xffff);
+		}
+	if (halbtc8822b2ant_is_wifibt_status_changed(btcoexist))
+		halbtc8822b2ant_run_coexist_mechanism(btcoexist);
+}
+
+
+/*#pragma optimize( "", off )*/
+void ex_halbtc8822b2ant_antenna_detection(IN struct btc_coexist *btcoexist,
+		IN u32 cent_freq, IN u32 offset, IN u32 span, IN u32 seconds)
+{
+#if 0
+	static u32 ant_det_count = 0, ant_det_fail_count = 0;
+	struct  btc_board_info	*board_info = &btcoexist->board_info;
+	u16		u16tmp;
+	u8			AntDetval = 0;
+
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+		    "xxxxxxxxxxxxxxxx Ext Call AntennaDetect()!!\n");
+	BTC_TRACE(trace_buf);
+
+#if BT_8822B_2ANT_ANTDET_ENABLE
+
+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+		    "xxxxxxxxxxxxxxxx Call AntennaDetect()!!\n");
+	BTC_TRACE(trace_buf);
+
+	if (seconds == 0) {
+		psd_scan->ant_det_try_count	= 0;
+		psd_scan->ant_det_fail_count	= 0;
+		ant_det_count = 0;
+		ant_det_fail_count = 0;
+		board_info->btdm_ant_det_finish = false;
+		board_info->btdm_ant_num_by_ant_det = 1;
+		return;
+	}
+
+	if (!board_info->btdm_ant_det_finish) {
+		psd_scan->ant_det_inteval_count =
+			psd_scan->ant_det_inteval_count + 2;
+
+		if (psd_scan->ant_det_inteval_count >=
+		    BT_8822B_2ANT_ANTDET_RETRY_INTERVAL) {
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				"xxxxxxxxxxxxxxxx AntennaDetect(), Antenna Det Timer is up, Try Detect!!\n");
+			BTC_TRACE(trace_buf);
+
+			psd_scan->is_AntDet_running = true;
+
+			halbtc8822b2ant_read_score_board(btcoexist,	&u16tmp);
+
+			if (u16tmp & BIT(
+				2)) { /* Antenna detection is already done before last WL power on   */
+				board_info->btdm_ant_det_finish = true;
+				psd_scan->ant_det_try_count = 1;
+				psd_scan->ant_det_fail_count = 0;
+				board_info->btdm_ant_num_by_ant_det = (u16tmp &
+							       BIT(3)) ? 1 : 2;
+				psd_scan->ant_det_result = 12;
+
+				psd_scan->ant_det_psd_scan_peak_val =
+					btcoexist->btc_get_ant_det_val_from_bt(
+						btcoexist) * 100;
+
+				BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+					"xxxxxxxxxxxxxxxx AntennaDetect(), Antenna Det Result from BT (%d-Ant)\n",
+					board_info->btdm_ant_num_by_ant_det);
+				BTC_TRACE(trace_buf);
+			} else
+				board_info->btdm_ant_det_finish =
+					halbtc8822b2ant_psd_antenna_detection_check(
+						btcoexist);
+
+			btcoexist->bdontenterLPS = false;
+
+			if (board_info->btdm_ant_det_finish) {
+				BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+					"xxxxxxxxxxxxxxxx AntennaDetect(), Antenna Det Success!!\n");
+				BTC_TRACE(trace_buf);
+
+				/*for 8822b, btc_set_bt_trx_mask is just used to
+				notify BT stop le tx and Ant Det Result , not set BT RF TRx Mask  */
+				if (psd_scan->ant_det_result != 12) {
+
+					AntDetval = (u8)((
+						psd_scan->ant_det_psd_scan_peak_val
+								 / 100) & 0x7f);
+
+					AntDetval =
+						(board_info->btdm_ant_num_by_ant_det
+						 == 1) ? (AntDetval | 0x80) :
+						AntDetval;
+
+					BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+						"xxxxxx AntennaDetect(), Ant Count = %d, PSD Val = %d\n",
+						    ((AntDetval &
+						      0x80) ? 1
+						     : 2), AntDetval
+						    & 0x7f);
+					BTC_TRACE(trace_buf);
+
+					if (btcoexist->btc_set_bt_trx_mask(
+						    btcoexist, AntDetval))
+						BTC_SPRINTF(trace_buf,
+							    BT_TMP_BUF_SIZE,
+							"xxxxxx AntennaDetect(), Notify BT stop le tx by set_bt_trx_mask ok!\n");
+					else
+						BTC_SPRINTF(trace_buf,
+							    BT_TMP_BUF_SIZE,
+							"xxxxxx AntennaDetect(), Notify BT stop le tx by set_bt_trx_mask fail!\n");
+
+					BTC_TRACE(trace_buf);
+				}
+
+			} else {
+				BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+					"xxxxxxxxxxxxxxxx AntennaDetect(), Antenna Det Fail!!\n");
+				BTC_TRACE(trace_buf);
+			}
+
+			psd_scan->ant_det_inteval_count = 0;
+			psd_scan->is_AntDet_running = false;
+
+			/* stimulate coex running */
+			halbtc8822b2ant_run_coexist_mechanism(
+				btcoexist);
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				"xxxxxxxxxxxxxxxx AntennaDetect(), Stimulate Coex running\n!!");
+			BTC_TRACE(trace_buf);
+		} else {
+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+				"xxxxxxxxxxxxxxxx AntennaDetect(), Antenna Det Timer is not up! (%d)\n",
+				    psd_scan->ant_det_inteval_count);
+			BTC_TRACE(trace_buf);
+
+			if (psd_scan->ant_det_inteval_count == 8)
+				btcoexist->bdontenterLPS = true;
+			else
+				btcoexist->bdontenterLPS = false;
+		}
+
+	}
+#endif
+#endif
+
+}
+
+
+void ex_halbtc8822b2ant_display_ant_detection(IN struct btc_coexist *btcoexist)
+{
+#if 0
+#if BT_8822B_2ANT_ANTDET_ENABLE
+	struct  btc_board_info	*board_info = &btcoexist->board_info;
+
+	if (psd_scan->ant_det_try_count != 0)	{
+		halbtc8822b2ant_psd_show_antenna_detect_result(btcoexist);
+
+		if (board_info->btdm_ant_det_finish)
+			halbtc8822b2ant_psd_showdata(btcoexist);
+	}
+#endif
+#endif
+}
+
+
+#endif
+
+#endif	/*  #if (RTL8822B_SUPPORT == 1) */
+
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/btc/halbtc8822b2ant.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/btc/halbtc8822b2ant.h
--- linux-5.6.3/3rdparty/rtl8821ce/hal/btc/halbtc8822b2ant.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/btc/halbtc8822b2ant.h	2020-04-10 16:35:06.786658667 +0300
@@ -0,0 +1,493 @@
+
+#if (BT_SUPPORT == 1 && COEX_SUPPORT == 1)
+
+#if (RTL8822B_SUPPORT == 1)
+
+/* *******************************************
+ * The following is for 8822B 2Ant BT Co-exist definition
+ * ******************************************* */
+#define	BT_8822B_2ANT_COEX_DBG					1
+#define	BT_AUTO_REPORT_ONLY_8822B_2ANT			1
+
+
+
+
+#define	BT_INFO_8822B_2ANT_B_FTP						BIT(7)
+#define	BT_INFO_8822B_2ANT_B_A2DP					BIT(6)
+#define	BT_INFO_8822B_2ANT_B_HID						BIT(5)
+#define	BT_INFO_8822B_2ANT_B_SCO_BUSY				BIT(4)
+#define	BT_INFO_8822B_2ANT_B_ACL_BUSY				BIT(3)
+#define	BT_INFO_8822B_2ANT_B_INQ_PAGE				BIT(2)
+#define	BT_INFO_8822B_2ANT_B_SCO_ESCO				BIT(1)
+#define	BT_INFO_8822B_2ANT_B_CONNECTION				BIT(0)
+
+#define		BTC_RSSI_COEX_THRESH_TOL_8822B_2ANT		2
+
+
+#define	BT_8822B_2ANT_WIFI_RSSI_COEXSWITCH_THRES1				60  /* unit: % WiFi RSSI Threshold for   2-Ant free-run/2-Ant TDMA translation, default = 42 */
+#define	BT_8822B_2ANT_BT_RSSI_COEXSWITCH_THRES1				50 /*  unit: % BT RSSI Threshold for      2-Ant free-run/2-Ant TDMA translation, default = 46 */
+#define	BT_8822B_2ANT_WIFI_RSSI_COEXSWITCH_THRES2				40 /* unit: % WiFi RSSI Threshold for   1-Ant TDMA/1-Ant PS-TDMA translation, default = 42 */
+#define	BT_8822B_2ANT_BT_RSSI_COEXSWITCH_THRES2				35 /*  unit: % BT RSSI Threshold for      1-Ant TDMA/1-Ant PS-TDMA translation, default = 46 */
+#define	BT_8822B_2ANT_DEFAULT_ISOLATION						15	 /*  unit: dB */
+#define   BT_8822B_2ANT_WIFI_MAX_TX_POWER						15	 /*  unit: dBm */
+#define   BT_8822B_2ANT_BT_MAX_TX_POWER							3	 /*  unit: dBm */
+#define   BT_8822B_2ANT_WIFI_SIR_THRES1							-15  /*  unit: dB */
+#define   BT_8822B_2ANT_WIFI_SIR_THRES2							-30  /*  unit: dB */
+#define   BT_8822B_2ANT_BT_SIR_THRES1							-15		 /*  unit: dB */
+#define   BT_8822B_2ANT_BT_SIR_THRES2							-30		 /*  unit: dB */
+
+
+/* for Antenna detection */
+#define	BT_8822B_2ANT_ANTDET_PSDTHRES_BACKGROUND						50
+#define	BT_8822B_2ANT_ANTDET_PSDTHRES_2ANT_BADISOLATION				70
+#define	BT_8822B_2ANT_ANTDET_PSDTHRES_2ANT_GOODISOLATION			52
+#define	BT_8822B_2ANT_ANTDET_PSDTHRES_1ANT							40
+#define	BT_8822B_2ANT_ANTDET_RETRY_INTERVAL							10	/* retry timer if ant det is fail, unit: second */
+#define	BT_8822B_2ANT_ANTDET_SWEEPPOINT_DELAY							60000
+#define	BT_8822B_2ANT_ANTDET_ENABLE										0
+#define	BT_8822B_2ANT_ANTDET_BTTXTIME									100
+#define	BT_8822B_2ANT_ANTDET_BTTXCHANNEL								39
+#define	BT_8822B_2ANT_ANTDET_PSD_SWWEEPCOUNT						50
+
+
+#define	BT_8822B_2ANT_LTECOEX_INDIRECTREG_ACCESS_TIMEOUT		30000
+
+enum bt_8822b_2ant_signal_state {
+	BT_8822B_2ANT_SIG_STA_SET_TO_LOW		= 0x0,
+	BT_8822B_2ANT_SIG_STA_SET_BY_HW		= 0x0,
+	BT_8822B_2ANT_SIG_STA_SET_TO_HIGH		= 0x1,
+	BT_8822B_2ANT_SIG_STA_MAX
+};
+
+enum bt_8822b_2ant_path_ctrl_owner {
+	BT_8822B_2ANT_PCO_BTSIDE		= 0x0,
+	BT_8822B_2ANT_PCO_WLSIDE	= 0x1,
+	BT_8822B_2ANT_PCO_MAX
+};
+
+enum bt_8822b_2ant_gnt_ctrl_type {
+	BT_8822B_2ANT_GNT_TYPE_CTRL_BY_PTA		= 0x0,
+	BT_8822B_2ANT_GNT_TYPE_CTRL_BY_SW		= 0x1,
+	BT_8822B_2ANT_GNT_TYPE_MAX
+};
+
+enum bt_8822b_2ant_gnt_ctrl_block {
+	BT_8822B_2ANT_GNT_BLOCK_RFC_BB		= 0x0,
+	BT_8822B_2ANT_GNT_BLOCK_RFC			= 0x1,
+	BT_8822B_2ANT_GNT_BLOCK_BB			= 0x2,
+	BT_8822B_2ANT_GNT_BLOCK_MAX
+};
+
+enum bt_8822b_2ant_lte_coex_table_type {
+	BT_8822B_2ANT_CTT_WL_VS_LTE			= 0x0,
+	BT_8822B_2ANT_CTT_BT_VS_LTE			= 0x1,
+	BT_8822B_2ANT_CTT_MAX
+};
+
+enum bt_8822b_2ant_lte_break_table_type {
+	BT_8822B_2ANT_LBTT_WL_BREAK_LTE			= 0x0,
+	BT_8822B_2ANT_LBTT_BT_BREAK_LTE				= 0x1,
+	BT_8822B_2ANT_LBTT_LTE_BREAK_WL			= 0x2,
+	BT_8822B_2ANT_LBTT_LTE_BREAK_BT				= 0x3,
+	BT_8822B_2ANT_LBTT_MAX
+};
+
+enum bt_info_src_8822b_2ant {
+	BT_INFO_SRC_8822B_2ANT_WIFI_FW			= 0x0,
+	BT_INFO_SRC_8822B_2ANT_BT_RSP				= 0x1,
+	BT_INFO_SRC_8822B_2ANT_BT_ACTIVE_SEND		= 0x2,
+	BT_INFO_SRC_8822B_2ANT_MAX
+};
+
+enum bt_8822b_2ant_bt_status {
+	BT_8822B_2ANT_BT_STATUS_NON_CONNECTED_IDLE	= 0x0,
+	BT_8822B_2ANT_BT_STATUS_CONNECTED_IDLE		= 0x1,
+	BT_8822B_2ANT_BT_STATUS_INQ_PAGE				= 0x2,
+	BT_8822B_2ANT_BT_STATUS_ACL_BUSY				= 0x3,
+	BT_8822B_2ANT_BT_STATUS_SCO_BUSY				= 0x4,
+	BT_8822B_2ANT_BT_STATUS_ACL_SCO_BUSY			= 0x5,
+	BT_8822B_2ANT_BT_STATUS_MAX
+};
+
+enum bt_8822b_2ant_coex_algo {
+	BT_8822B_2ANT_COEX_ALGO_UNDEFINED			= 0x0,
+	BT_8822B_2ANT_COEX_ALGO_SCO				= 0x1,
+	BT_8822B_2ANT_COEX_ALGO_HID				= 0x2,
+	BT_8822B_2ANT_COEX_ALGO_A2DP				= 0x3,
+	BT_8822B_2ANT_COEX_ALGO_A2DP_PANHS		= 0x4,
+	BT_8822B_2ANT_COEX_ALGO_PANEDR			= 0x5,
+	BT_8822B_2ANT_COEX_ALGO_PANHS			= 0x6,
+	BT_8822B_2ANT_COEX_ALGO_PANEDR_A2DP		= 0x7,
+	BT_8822B_2ANT_COEX_ALGO_PANEDR_HID		= 0x8,
+	BT_8822B_2ANT_COEX_ALGO_HID_A2DP_PANEDR	= 0x9,
+	BT_8822B_2ANT_COEX_ALGO_HID_A2DP			= 0xa,
+	BT_8822B_2ANT_COEX_ALGO_NOPROFILEBUSY		= 0xb,
+	BT_8822B_2ANT_COEX_ALGO_MAX
+};
+
+enum bt_8822b_2ant_ext_ant_switch_type {
+	BT_8822B_2ANT_EXT_ANT_SWITCH_USE_DPDT		= 0x0,
+	BT_8822B_2ANT_EXT_ANT_SWITCH_USE_SPDT		= 0x1,
+	BT_8822B_2ANT_EXT_ANT_SWITCH_NONE			= 0x2,
+	BT_8822B_2ANT_EXT_ANT_SWITCH_MAX
+};
+
+enum bt_8822b_2ant_ext_ant_switch_ctrl_type {
+	BT_8822B_2ANT_EXT_ANT_SWITCH_CTRL_BY_BBSW	= 0x0,
+	BT_8822B_2ANT_EXT_ANT_SWITCH_CTRL_BY_PTA		= 0x1,
+	BT_8822B_2ANT_EXT_ANT_SWITCH_CTRL_BY_ANTDIV	= 0x2,
+	BT_8822B_2ANT_EXT_ANT_SWITCH_CTRL_BY_MAC		= 0x3,
+	BT_8822B_2ANT_EXT_ANT_SWITCH_CTRL_BY_BT		= 0x4,
+	BT_8822B_2ANT_EXT_ANT_SWITCH_CTRL_MAX
+};
+
+enum bt_8822b_2ant_ext_ant_switch_pos_type {
+	BT_8822B_2ANT_EXT_ANT_SWITCH_MAIN_TO_BT			= 0x0,
+	BT_8822B_2ANT_EXT_ANT_SWITCH_MAIN_TO_WLG			= 0x1,
+	BT_8822B_2ANT_EXT_ANT_SWITCH_MAIN_TO_WLA			= 0x2,
+	BT_8822B_2ANT_EXT_ANT_SWITCH_MAIN_TO_NOCARE		= 0x3,
+	BT_8822B_2ANT_EXT_ANT_SWITCH_MAIN_TO_MAX
+};
+
+enum bt_8822b_2ant_ext_band_switch_pos_type {
+	BT_8822B_2ANT_EXT_BAND_SWITCH_TO_WLG			= 0x0,
+	BT_8822B_2ANT_EXT_BAND_SWITCH_TO_WLA			= 0x1,
+	BT_8822B_2ANT_EXT_BAND_SWITCH_TO_MAX
+};
+
+enum bt_8822b_2ant_int_block {
+	BT_8822B_2ANT_INT_BLOCK_SWITCH_TO_WLG_OF_BTG			= 0x0,
+	BT_8822B_2ANT_INT_BLOCK_SWITCH_TO_WLG_OF_WLAG		= 0x1,
+	BT_8822B_2ANT_INT_BLOCK_SWITCH_TO_WLA_OF_WLAG		= 0x2,
+	BT_8822B_2ANT_INT_BLOCK_SWITCH_TO_MAX
+};
+
+enum bt_8822b_2ant_phase {
+	BT_8822B_2ANT_PHASE_COEX_INIT								= 0x0,
+	BT_8822B_2ANT_PHASE_WLANONLY_INIT							= 0x1,
+	BT_8822B_2ANT_PHASE_WLAN_OFF								= 0x2,
+	BT_8822B_2ANT_PHASE_2G_RUNTIME								= 0x3,
+	BT_8822B_2ANT_PHASE_5G_RUNTIME								= 0x4,
+	BT_8822B_2ANT_PHASE_BTMPMODE								= 0x5,
+	BT_8822B_2ANT_PHASE_ANTENNA_DET								= 0x6,
+	BT_8822B_2ANT_PHASE_COEX_POWERON							= 0x7,
+	BT_8822B_2ANT_PHASE_2G_RUNTIME_CONCURRENT					= 0x8,
+	BT_8822B_2ANT_PHASE_MAX
+};
+
+/*ADD SCOREBOARD TO FIX BT LPS 32K ISSUE WHILE WL BUSY*/
+
+enum bt_8822b_2ant_Scoreboard {
+	BT_8822B_2ANT_SCOREBOARD_ACTIVE								= BIT(0),
+	BT_8822B_2ANT_SCOREBOARD_ONOFF								= BIT(1),
+	BT_8822B_2ANT_SCOREBOARD_SCAN								= BIT(2),
+	BT_8822B_2ANT_SCOREBOARD_UNDERTEST							= BIT(3),
+	BT_8822B_2ANT_SCOREBOARD_WLBUSY                                                              = BIT(6)
+};
+
+
+
+
+
+struct coex_dm_8822b_2ant {
+	/* hw setting */
+	u32		pre_ant_pos_type;
+	u32		cur_ant_pos_type;
+	/* fw mechanism */
+	u8		pre_bt_dec_pwr_lvl;
+	u8		cur_bt_dec_pwr_lvl;
+	u8		pre_fw_dac_swing_lvl;
+	u8		cur_fw_dac_swing_lvl;
+	boolean		cur_ignore_wlan_act;
+	boolean		pre_ignore_wlan_act;
+	u8		pre_ps_tdma;
+	u8		cur_ps_tdma;
+	u8		ps_tdma_para[5];
+	u8		ps_tdma_du_adj_type;
+	boolean		reset_tdma_adjust;
+	boolean		pre_ps_tdma_on;
+	boolean		cur_ps_tdma_on;
+	boolean		pre_bt_auto_report;
+	boolean		cur_bt_auto_report;
+
+	/* sw mechanism */
+	boolean		pre_rf_rx_lpf_shrink;
+	boolean		cur_rf_rx_lpf_shrink;
+	u32		bt_rf_0x1e_backup;
+	boolean	pre_low_penalty_ra;
+	boolean		cur_low_penalty_ra;
+	boolean		pre_dac_swing_on;
+	u32		pre_dac_swing_lvl;
+	boolean		cur_dac_swing_on;
+	u32		cur_dac_swing_lvl;
+	boolean		pre_adc_back_off;
+	boolean		cur_adc_back_off;
+	boolean	pre_agc_table_en;
+	boolean		cur_agc_table_en;
+	u32		pre_val0x6c0;
+	u32		cur_val0x6c0;
+	u32		pre_val0x6c4;
+	u32		cur_val0x6c4;
+	u32		pre_val0x6c8;
+	u32		cur_val0x6c8;
+	u8		pre_val0x6cc;
+	u8		cur_val0x6cc;
+	boolean		limited_dig;
+
+	/* algorithm related */
+	u8		pre_algorithm;
+	u8		cur_algorithm;
+	u8		bt_status;
+	u8		wifi_chnl_info[3];
+
+	boolean		need_recover0x948;
+	u32		backup0x948;
+
+	u8		pre_lps;
+	u8		cur_lps;
+	u8		pre_rpwm;
+	u8		cur_rpwm;
+
+	boolean		is_switch_to_1dot5_ant;
+	u8		switch_thres_offset;
+	u32					arp_cnt;
+
+	u32		pre_ext_ant_switch_status;
+	u32		cur_ext_ant_switch_status;
+
+	u8		pre_ext_band_switch_status;
+	u8		cur_ext_band_switch_status;
+
+	u8		pre_int_block_status;
+	u8		cur_int_block_status;
+};
+
+struct coex_sta_8822b_2ant {
+	boolean					bt_disabled;
+	boolean					bt_link_exist;
+	boolean					sco_exist;
+	boolean					a2dp_exist;
+	boolean					hid_exist;
+	boolean					pan_exist;
+
+	boolean					under_lps;
+	boolean					under_ips;
+	u32					high_priority_tx;
+	u32					high_priority_rx;
+	u32					low_priority_tx;
+	u32					low_priority_rx;
+	u8					bt_rssi;
+	boolean					bt_tx_rx_mask;
+	u8					pre_bt_rssi_state;
+	u8					pre_wifi_rssi_state[4];
+	boolean					c2h_bt_info_req_sent;
+	u8					bt_info_c2h[BT_INFO_SRC_8822B_2ANT_MAX][10];
+	u32					bt_info_c2h_cnt[BT_INFO_SRC_8822B_2ANT_MAX];
+	boolean				bt_whck_test;
+	boolean					c2h_bt_inquiry_page;
+	boolean					c2h_bt_remote_name_req;
+	u8					bt_retry_cnt;
+	u8					bt_info_ext;
+	u8					bt_info_ext2;
+	u32					pop_event_cnt;
+	u8					scan_ap_num;
+
+	u32					crc_ok_cck;
+	u32					crc_ok_11g;
+	u32					crc_ok_11n;
+	u32					crc_ok_11n_agg;
+	u32					crc_ok_11n_vht;
+
+	u32					crc_err_cck;
+	u32					crc_err_11g;
+	u32					crc_err_11n;
+	u32					crc_err_11n_agg;
+	u32					crc_err_11n_vht;
+
+	boolean					cck_lock;
+	boolean					pre_ccklock;
+	boolean					cck_ever_lock;
+
+	u8					coex_table_type;
+	boolean					force_lps_on;
+
+	u8					dis_ver_info_cnt;
+
+	u8					a2dp_bit_pool;
+	u8					cut_version;
+
+	boolean					concurrent_rx_mode_on;
+
+	u16					score_board;
+	u8					isolation_btween_wb;   /* 0~ 50 */
+	u8					wifi_coex_thres;
+	u8					bt_coex_thres;
+	u8					wifi_coex_thres2;
+	u8					bt_coex_thres2;
+
+	u8					num_of_profile;
+	boolean				acl_busy;
+	boolean				wl_rf_off_on_event;
+	boolean				bt_create_connection;
+	boolean				wifi_is_high_pri_task;
+	u32					specific_pkt_period_cnt;
+	u32					bt_coex_supported_feature;
+	u32					bt_coex_supported_version;
+
+	u8					bt_ble_scan_type;
+	u8					bt_ble_scan_para[3];
+
+	boolean				run_time_state;
+	boolean				freeze_coexrun_by_btinfo;
+
+	boolean				is_A2DP_3M;
+	boolean				voice_over_HOGP;
+	u8                  bt_info;
+	boolean				is_autoslot;
+	u8					forbidden_slot;
+	u8					hid_busy_num;
+	u8					hid_pair_cnt;
+
+	u32					cnt_RemoteNameReq;
+	u32					cnt_setupLink;
+	u32					cnt_ReInit;
+	u32					cnt_IgnWlanAct;
+	u32					cnt_Page;
+
+	u16					bt_reg_vendor_ac;
+	u16					bt_reg_vendor_ae;
+
+	boolean				is_setupLink;
+	u8				    wl_noisy_level;
+	u32                 gnt_error_cnt;
+
+	u8					bt_afh_map[10];
+	u8					bt_relink_downcount;
+};
+
+
+#define  BT_8822B_2ANT_EXT_BAND_SWITCH_USE_DPDT	0
+#define  BT_8822B_2ANT_EXT_BAND_SWITCH_USE_SPDT	1
+
+
+struct rfe_type_8822b_2ant {
+
+	u8			rfe_module_type;
+	boolean		ext_ant_switch_exist;
+	u8			ext_ant_switch_type;			/* 0:DPDT, 1:SPDT */
+	u8			ext_ant_switch_ctrl_polarity;		/*  iF 0: DPDT_P=0, DPDT_N=1 => BTG to Main, WL_A+G to Aux */
+
+	boolean		ext_band_switch_exist;
+	u8			ext_band_switch_type;			/* 0:DPDT, 1:SPDT */
+	u8			ext_band_switch_ctrl_polarity;
+
+	boolean		wlg_Locate_at_btg;				/*  If true:  WLG at BTG, If false: WLG at WLAG */
+
+	boolean		ext_ant_switch_diversity;		/* If diversity on */
+};
+
+#define BT_8822B_2ANT_ANTDET_PSD_POINTS			256	/* MAX:1024 */
+#define BT_8822B_2ANT_ANTDET_PSD_AVGNUM		1	/* MAX:3 */
+#define BT_8822B_2ANT_ANTDET_BUF_LEN			16
+
+struct psdscan_sta_8822b_2ant {
+
+	u32			ant_det_bt_le_channel;  /* BT LE Channel ex:2412 */
+	u32			ant_det_bt_tx_time;
+	u32			ant_det_pre_psdscan_peak_val;
+	boolean			ant_det_is_ant_det_available;
+	u32			ant_det_psd_scan_peak_val;
+	boolean			ant_det_is_btreply_available;
+	u32			ant_det_psd_scan_peak_freq;
+
+	u8			ant_det_result;
+	u8			ant_det_peak_val[BT_8822B_2ANT_ANTDET_BUF_LEN];
+	u8			ant_det_peak_freq[BT_8822B_2ANT_ANTDET_BUF_LEN];
+	u32			ant_det_try_count;
+	u32			ant_det_fail_count;
+	u32			ant_det_inteval_count;
+	u32			ant_det_thres_offset;
+
+	u32			real_cent_freq;
+	s32			real_offset;
+	u32			real_span;
+
+	u32			psd_band_width;  /* unit: Hz */
+	u32			psd_point;		/* 128/256/512/1024 */
+	u32			psd_report[1024];  /* unit:dB (20logx), 0~255 */
+	u32			psd_report_max_hold[1024];  /* unit:dB (20logx), 0~255 */
+	u32			psd_start_point;
+	u32			psd_stop_point;
+	u32			psd_max_value_point;
+	u32			psd_max_value;
+	u32			psd_max_value2;
+	u32			psd_avg_value;   /* filter loop_max_value that below BT_8822B_1ANT_ANTDET_PSDTHRES_1ANT, and average the rest*/
+	u32			psd_loop_max_value[BT_8822B_2ANT_ANTDET_PSD_SWWEEPCOUNT];  /*max value in each loop */
+	u32			psd_start_base;
+	u32			psd_avg_num;	/* 1/8/16/32 */
+	u32			psd_gen_count;
+	boolean			is_AntDet_running;
+	boolean			is_psd_show_max_only;
+};
+
+
+/* *******************************************
+ * The following is interface which will notify coex module.
+ * ******************************************* */
+void ex_halbtc8822b2ant_power_on_setting(IN struct btc_coexist *btcoexist);
+void ex_halbtc8822b2ant_pre_load_firmware(IN struct btc_coexist *btcoexist);
+void ex_halbtc8822b2ant_init_hw_config(IN struct btc_coexist *btcoexist,
+				       IN boolean wifi_only);
+void ex_halbtc8822b2ant_init_coex_dm(IN struct btc_coexist *btcoexist);
+void ex_halbtc8822b2ant_ips_notify(IN struct btc_coexist *btcoexist,
+				   IN u8 type);
+void ex_halbtc8822b2ant_lps_notify(IN struct btc_coexist *btcoexist,
+				   IN u8 type);
+void ex_halbtc8822b2ant_scan_notify(IN struct btc_coexist *btcoexist,
+				    IN u8 type);
+void ex_halbtc8822b2ant_switchband_notify(IN struct btc_coexist *btcoexist,
+		IN u8 type);
+void ex_halbtc8822b2ant_connect_notify(IN struct btc_coexist *btcoexist,
+				       IN u8 type);
+void ex_halbtc8822b2ant_media_status_notify(IN struct btc_coexist *btcoexist,
+		IN u8 type);
+void ex_halbtc8822b2ant_specific_packet_notify(IN struct btc_coexist *btcoexist,
+		IN u8 type);
+void ex_halbtc8822b2ant_bt_info_notify(IN struct btc_coexist *btcoexist,
+				       IN u8 *tmp_buf, IN u8 length);
+void ex_halbtc8822b2ant_rf_status_notify(IN struct btc_coexist *btcoexist,
+		IN u8 type);
+void ex_halbtc8822b2ant_halt_notify(IN struct btc_coexist *btcoexist);
+void ex_halbtc8822b2ant_pnp_notify(IN struct btc_coexist *btcoexist,
+				   IN u8 pnp_state);
+void ex_halbtc8822b2ant_periodical(IN struct btc_coexist *btcoexist);
+void ex_halbtc8822b2ant_display_coex_info(IN struct btc_coexist *btcoexist);
+void ex_halbtc8822b2ant_antenna_detection(IN struct btc_coexist *btcoexist,
+		IN u32 cent_freq, IN u32 offset, IN u32 span, IN u32 seconds);
+void ex_halbtc8822b2ant_display_ant_detection(IN struct btc_coexist *btcoexist);
+
+
+#else
+#define	ex_halbtc8822b2ant_power_on_setting(btcoexist)
+#define	ex_halbtc8822b2ant_pre_load_firmware(btcoexist)
+#define	ex_halbtc8822b2ant_init_hw_config(btcoexist, wifi_only)
+#define	ex_halbtc8822b2ant_init_coex_dm(btcoexist)
+#define	ex_halbtc8822b2ant_ips_notify(btcoexist, type)
+#define	ex_halbtc8822b2ant_lps_notify(btcoexist, type)
+#define	ex_halbtc8822b2ant_scan_notify(btcoexist, type)
+#define   ex_halbtc8822b2ant_switchband_notify(btcoexist, type)
+#define	ex_halbtc8822b2ant_connect_notify(btcoexist, type)
+#define	ex_halbtc8822b2ant_media_status_notify(btcoexist, type)
+#define	ex_halbtc8822b2ant_specific_packet_notify(btcoexist, type)
+#define	ex_halbtc8822b2ant_bt_info_notify(btcoexist, tmp_buf, length)
+#define	ex_halbtc8822b2ant_rf_status_notify(btcoexist, type)
+#define	ex_halbtc8822b2ant_halt_notify(btcoexist)
+#define	ex_halbtc8822b2ant_pnp_notify(btcoexist, pnp_state)
+#define	ex_halbtc8822b2ant_periodical(btcoexist)
+#define	ex_halbtc8822b2ant_display_coex_info(btcoexist)
+#define	ex_halbtc8822b2ant_display_ant_detection(btcoexist)
+#define	ex_halbtc8822b2ant_antenna_detection(btcoexist, cent_freq, offset, span, seconds)
+#endif
+
+#endif
+
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/btc/halbtc8822bwifionly.c linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/btc/halbtc8822bwifionly.c
--- linux-5.6.3/3rdparty/rtl8821ce/hal/btc/halbtc8822bwifionly.c	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/btc/halbtc8822bwifionly.c	2020-04-10 16:35:06.786658667 +0300
@@ -0,0 +1,54 @@
+#include "mp_precomp.h"
+
+
+VOID
+ex_hal8822b_wifi_only_hw_config(
+	IN struct wifi_only_cfg *pwifionlycfg
+	)
+{
+	/*BB control*/
+	halwifionly_phy_set_bb_reg(pwifionlycfg, 0x4c, 0x01800000, 0x2);
+	/*SW control*/
+	halwifionly_phy_set_bb_reg(pwifionlycfg, 0xcb4, 0xff, 0x77);
+	/*antenna mux switch */
+	halwifionly_phy_set_bb_reg(pwifionlycfg, 0x974, 0x300, 0x3);
+
+	halwifionly_phy_set_bb_reg(pwifionlycfg, 0x1990, 0x300, 0x0);
+
+	halwifionly_phy_set_bb_reg(pwifionlycfg, 0xcbc, 0x80000, 0x0);
+	/*switch to WL side controller and gnt_wl gnt_bt debug signal */
+	halwifionly_phy_set_bb_reg(pwifionlycfg, 0x70, 0xff000000, 0x0e);
+	/*gnt_wl=1 , gnt_bt=0*/
+	halwifionly_phy_set_bb_reg(pwifionlycfg, 0x1704, 0xffffffff, 0x7700);
+	halwifionly_phy_set_bb_reg(pwifionlycfg, 0x1700, 0xffffffff, 0xc00f0038);
+}
+
+VOID
+ex_hal8822b_wifi_only_scannotify(
+	IN struct wifi_only_cfg *pwifionlycfg,
+	IN u1Byte  is_5g
+	)
+{
+	hal8822b_wifi_only_switch_antenna(pwifionlycfg, is_5g);
+}
+
+VOID
+ex_hal8822b_wifi_only_switchbandnotify(
+	IN struct wifi_only_cfg *pwifionlycfg,
+	IN u1Byte  is_5g
+	)
+{
+	hal8822b_wifi_only_switch_antenna(pwifionlycfg, is_5g);
+}
+
+VOID
+hal8822b_wifi_only_switch_antenna(IN struct wifi_only_cfg *pwifionlycfg,
+	IN u1Byte  is_5g
+	)
+{
+
+	if (is_5g)
+		halwifionly_phy_set_bb_reg(pwifionlycfg, 0xcbc, 0x300, 0x1);
+	else
+		halwifionly_phy_set_bb_reg(pwifionlycfg, 0xcbc, 0x300, 0x2);
+}
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/btc/halbtc8822bwifionly.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/btc/halbtc8822bwifionly.h
--- linux-5.6.3/3rdparty/rtl8821ce/hal/btc/halbtc8822bwifionly.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/btc/halbtc8822bwifionly.h	2020-04-10 16:35:06.786658667 +0300
@@ -0,0 +1,22 @@
+#ifndef __INC_HAL8822BWIFIONLYHWCFG_H
+#define __INC_HAL8822BWIFIONLYHWCFG_H
+
+VOID
+ex_hal8822b_wifi_only_hw_config(
+	IN struct wifi_only_cfg *pwifionlycfg
+	);
+VOID
+ex_hal8822b_wifi_only_scannotify(
+	IN struct wifi_only_cfg *pwifionlycfg,
+	IN u1Byte  is_5g
+	);
+VOID
+ex_hal8822b_wifi_only_switchbandnotify(
+	IN struct wifi_only_cfg *pwifionlycfg,
+	IN u1Byte  is_5g
+	);
+VOID
+hal8822b_wifi_only_switch_antenna(IN struct wifi_only_cfg *pwifionlycfg,
+	IN u1Byte  is_5g
+	);
+#endif
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/btc/halbtcoutsrc.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/btc/halbtcoutsrc.h
--- linux-5.6.3/3rdparty/rtl8821ce/hal/btc/halbtcoutsrc.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/btc/halbtcoutsrc.h	2020-04-10 16:35:06.786658667 +0300
@@ -0,0 +1,1276 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2016 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#ifndef	__HALBTC_OUT_SRC_H__
+#define __HALBTC_OUT_SRC_H__
+
+enum {
+	BTC_CCK_1,
+	BTC_CCK_2,
+	BTC_CCK_5_5,
+	BTC_CCK_11,
+	BTC_OFDM_6,
+	BTC_OFDM_9,
+	BTC_OFDM_12,
+	BTC_OFDM_18,
+	BTC_OFDM_24,
+	BTC_OFDM_36,
+	BTC_OFDM_48,
+	BTC_OFDM_54,
+	BTC_MCS_0,
+	BTC_MCS_1,
+	BTC_MCS_2,
+	BTC_MCS_3,
+	BTC_MCS_4,
+	BTC_MCS_5,
+	BTC_MCS_6,
+	BTC_MCS_7,
+	BTC_MCS_8,
+	BTC_MCS_9,
+	BTC_MCS_10,
+	BTC_MCS_11,
+	BTC_MCS_12,
+	BTC_MCS_13,
+	BTC_MCS_14,
+	BTC_MCS_15,
+	BTC_MCS_16,
+	BTC_MCS_17,
+	BTC_MCS_18,
+	BTC_MCS_19,
+	BTC_MCS_20,
+	BTC_MCS_21,
+	BTC_MCS_22,
+	BTC_MCS_23,
+	BTC_MCS_24,
+	BTC_MCS_25,
+	BTC_MCS_26,
+	BTC_MCS_27,
+	BTC_MCS_28,
+	BTC_MCS_29,
+	BTC_MCS_30,
+	BTC_MCS_31,
+	BTC_VHT_1SS_MCS_0,
+	BTC_VHT_1SS_MCS_1,
+	BTC_VHT_1SS_MCS_2,
+	BTC_VHT_1SS_MCS_3,
+	BTC_VHT_1SS_MCS_4,
+	BTC_VHT_1SS_MCS_5,
+	BTC_VHT_1SS_MCS_6,
+	BTC_VHT_1SS_MCS_7,
+	BTC_VHT_1SS_MCS_8,
+	BTC_VHT_1SS_MCS_9,
+	BTC_VHT_2SS_MCS_0,
+	BTC_VHT_2SS_MCS_1,
+	BTC_VHT_2SS_MCS_2,
+	BTC_VHT_2SS_MCS_3,
+	BTC_VHT_2SS_MCS_4,
+	BTC_VHT_2SS_MCS_5,
+	BTC_VHT_2SS_MCS_6,
+	BTC_VHT_2SS_MCS_7,
+	BTC_VHT_2SS_MCS_8,
+	BTC_VHT_2SS_MCS_9,
+	BTC_VHT_3SS_MCS_0,
+	BTC_VHT_3SS_MCS_1,
+	BTC_VHT_3SS_MCS_2,
+	BTC_VHT_3SS_MCS_3,
+	BTC_VHT_3SS_MCS_4,
+	BTC_VHT_3SS_MCS_5,
+	BTC_VHT_3SS_MCS_6,
+	BTC_VHT_3SS_MCS_7,
+	BTC_VHT_3SS_MCS_8,
+	BTC_VHT_3SS_MCS_9,
+	BTC_VHT_4SS_MCS_0,
+	BTC_VHT_4SS_MCS_1,
+	BTC_VHT_4SS_MCS_2,
+	BTC_VHT_4SS_MCS_3,
+	BTC_VHT_4SS_MCS_4,
+	BTC_VHT_4SS_MCS_5,
+	BTC_VHT_4SS_MCS_6,
+	BTC_VHT_4SS_MCS_7,
+	BTC_VHT_4SS_MCS_8,
+	BTC_VHT_4SS_MCS_9,
+	BTC_MCS_32,
+	BTC_UNKNOWN,
+	BTC_PKT_MGNT,
+	BTC_PKT_CTRL,
+	BTC_PKT_UNKNOWN,
+	BTC_PKT_NOT_FOR_ME,
+	BTC_RATE_MAX
+};
+
+enum {
+	BTC_MULTIPORT_SCC,
+	BTC_MULTIPORT_MCC_DUAL_CHANNEL,
+	BTC_MULTIPORT_MCC_DUAL_BAND,
+	BTC_MULTIPORT_MAX
+};
+
+#define		BTC_COEX_OFFLOAD			0
+#define		BTC_TMP_BUF_SHORT		20
+
+extern u1Byte	gl_btc_trace_buf[];
+#define		BTC_SPRINTF			rsprintf
+#define		BTC_TRACE(_MSG_)\
+do {\
+	if (GLBtcDbgType[COMP_COEX] & BIT(DBG_LOUD)) {\
+		RTW_INFO("%s", _MSG_);\
+	} \
+} while (0)
+#define		BT_PrintData(adapter, _MSG_, len, data)	RTW_DBG_DUMP((_MSG_), data, len)
+
+
+#define		NORMAL_EXEC					FALSE
+#define		FORCE_EXEC						TRUE
+
+#define		NM_EXCU						FALSE
+#define		FC_EXCU						TRUE
+
+#define		BTC_RF_OFF					0x0
+#define		BTC_RF_ON					0x1
+
+#define		BTC_RF_A					0x0
+#define		BTC_RF_B					0x1
+#define		BTC_RF_C					0x2
+#define		BTC_RF_D					0x3
+
+#define		BTC_SMSP				SINGLEMAC_SINGLEPHY
+#define		BTC_DMDP				DUALMAC_DUALPHY
+#define		BTC_DMSP				DUALMAC_SINGLEPHY
+#define		BTC_MP_UNKNOWN		0xff
+
+#define		BT_COEX_ANT_TYPE_PG			0
+#define		BT_COEX_ANT_TYPE_ANTDIV		1
+#define		BT_COEX_ANT_TYPE_DETECTED	2
+
+#define		BTC_MIMO_PS_STATIC			0	/* 1ss */
+#define		BTC_MIMO_PS_DYNAMIC			1	/* 2ss */
+
+#define		BTC_RATE_DISABLE			0
+#define		BTC_RATE_ENABLE				1
+
+/* single Antenna definition */
+#define		BTC_ANT_PATH_WIFI			0
+#define		BTC_ANT_PATH_BT				1
+#define		BTC_ANT_PATH_PTA			2
+#define		BTC_ANT_PATH_WIFI5G			3
+#define		BTC_ANT_PATH_AUTO			4
+/* dual Antenna definition */
+#define		BTC_ANT_WIFI_AT_MAIN		0
+#define		BTC_ANT_WIFI_AT_AUX			1
+#define		BTC_ANT_WIFI_AT_DIVERSITY	2
+/* coupler Antenna definition */
+#define		BTC_ANT_WIFI_AT_CPL_MAIN	0
+#define		BTC_ANT_WIFI_AT_CPL_AUX		1
+
+typedef enum _BTC_POWERSAVE_TYPE {
+	BTC_PS_WIFI_NATIVE			= 0,	/* wifi original power save behavior */
+	BTC_PS_LPS_ON				= 1,
+	BTC_PS_LPS_OFF				= 2,
+	BTC_PS_MAX
+} BTC_POWERSAVE_TYPE, *PBTC_POWERSAVE_TYPE;
+
+typedef enum _BTC_BT_REG_TYPE {
+	BTC_BT_REG_RF						= 0,
+	BTC_BT_REG_MODEM					= 1,
+	BTC_BT_REG_BLUEWIZE					= 2,
+	BTC_BT_REG_VENDOR					= 3,
+	BTC_BT_REG_LE						= 4,
+	BTC_BT_REG_MAX
+} BTC_BT_REG_TYPE, *PBTC_BT_REG_TYPE;
+
+typedef enum _BTC_CHIP_INTERFACE {
+	BTC_INTF_UNKNOWN	= 0,
+	BTC_INTF_PCI			= 1,
+	BTC_INTF_USB			= 2,
+	BTC_INTF_SDIO		= 3,
+	BTC_INTF_MAX
+} BTC_CHIP_INTERFACE, *PBTC_CHIP_INTERFACE;
+
+typedef enum _BTC_CHIP_TYPE {
+	BTC_CHIP_UNDEF		= 0,
+	BTC_CHIP_CSR_BC4		= 1,
+	BTC_CHIP_CSR_BC8		= 2,
+	BTC_CHIP_RTL8723A		= 3,
+	BTC_CHIP_RTL8821		= 4,
+	BTC_CHIP_RTL8723B		= 5,
+	BTC_CHIP_MAX
+} BTC_CHIP_TYPE, *PBTC_CHIP_TYPE;
+
+/* following is for wifi link status */
+#define		WIFI_STA_CONNECTED				BIT0
+#define		WIFI_AP_CONNECTED				BIT1
+#define		WIFI_HS_CONNECTED				BIT2
+#define		WIFI_P2P_GO_CONNECTED			BIT3
+#define		WIFI_P2P_GC_CONNECTED			BIT4
+
+/* following is for command line utility */
+#define	CL_SPRINTF	rsprintf
+#define	CL_PRINTF	DCMD_Printf
+#define CL_STRNCAT(dst, dst_size, src, src_size) rstrncat(dst, src, src_size)
+
+struct btc_board_info {
+	/* The following is some board information */
+	u8				bt_chip_type;
+	u8				pg_ant_num;	/* pg ant number */
+	u8				btdm_ant_num;	/* ant number for btdm */
+	u8				btdm_ant_num_by_ant_det;	/* ant number for btdm after antenna detection */
+	u8				btdm_ant_pos;		/* Bryant Add to indicate Antenna Position for (pg_ant_num = 2) && (btdm_ant_num =1)  (DPDT+1Ant case) */
+	u8				single_ant_path;	/* current used for 8723b only, 1=>s0,  0=>s1 */
+	boolean			tfbga_package;    /* for Antenna detect threshold */
+	boolean			btdm_ant_det_finish;
+	boolean			btdm_ant_det_already_init_phydm;
+	u8				ant_type;
+	u8				rfe_type;
+	u8				ant_div_cfg;
+	boolean			btdm_ant_det_complete_fail;
+	u8				ant_det_result;
+	boolean			ant_det_result_five_complete;
+	u32				antdetval;
+	u8				customerID;
+	u8				customer_id;
+};
+
+typedef enum _BTC_DBG_OPCODE {
+	BTC_DBG_SET_COEX_NORMAL				= 0x0,
+	BTC_DBG_SET_COEX_WIFI_ONLY				= 0x1,
+	BTC_DBG_SET_COEX_BT_ONLY				= 0x2,
+	BTC_DBG_SET_COEX_DEC_BT_PWR				= 0x3,
+	BTC_DBG_SET_COEX_BT_AFH_MAP				= 0x4,
+	BTC_DBG_SET_COEX_BT_IGNORE_WLAN_ACT		= 0x5,
+	BTC_DBG_SET_COEX_MANUAL_CTRL				= 0x6,
+	BTC_DBG_MAX
+} BTC_DBG_OPCODE, *PBTC_DBG_OPCODE;
+
+typedef enum _BTC_RSSI_STATE {
+	BTC_RSSI_STATE_HIGH						= 0x0,
+	BTC_RSSI_STATE_MEDIUM					= 0x1,
+	BTC_RSSI_STATE_LOW						= 0x2,
+	BTC_RSSI_STATE_STAY_HIGH					= 0x3,
+	BTC_RSSI_STATE_STAY_MEDIUM				= 0x4,
+	BTC_RSSI_STATE_STAY_LOW					= 0x5,
+	BTC_RSSI_MAX
+} BTC_RSSI_STATE, *PBTC_RSSI_STATE;
+#define	BTC_RSSI_HIGH(_rssi_)	((_rssi_ == BTC_RSSI_STATE_HIGH || _rssi_ == BTC_RSSI_STATE_STAY_HIGH) ? TRUE:FALSE)
+#define	BTC_RSSI_MEDIUM(_rssi_)	((_rssi_ == BTC_RSSI_STATE_MEDIUM || _rssi_ == BTC_RSSI_STATE_STAY_MEDIUM) ? TRUE:FALSE)
+#define	BTC_RSSI_LOW(_rssi_)	((_rssi_ == BTC_RSSI_STATE_LOW || _rssi_ == BTC_RSSI_STATE_STAY_LOW) ? TRUE:FALSE)
+
+typedef enum _BTC_WIFI_ROLE {
+	BTC_ROLE_STATION						= 0x0,
+	BTC_ROLE_AP								= 0x1,
+	BTC_ROLE_IBSS							= 0x2,
+	BTC_ROLE_HS_MODE						= 0x3,
+	BTC_ROLE_MAX
+} BTC_WIFI_ROLE, *PBTC_WIFI_ROLE;
+
+typedef enum _BTC_WIRELESS_FREQ {
+	BTC_FREQ_2_4G					= 0x0,
+	BTC_FREQ_5G						= 0x1,
+	BTC_FREQ_25G					= 0x2,
+	BTC_FREQ_MAX
+} BTC_WIRELESS_FREQ, *PBTC_WIRELESS_FREQ;
+
+typedef enum _BTC_WIFI_BW_MODE {
+	BTC_WIFI_BW_LEGACY					= 0x0,
+	BTC_WIFI_BW_HT20					= 0x1,
+	BTC_WIFI_BW_HT40					= 0x2,
+	BTC_WIFI_BW_HT80					= 0x3,
+	BTC_WIFI_BW_HT160					= 0x4,
+	BTC_WIFI_BW_MAX
+} BTC_WIFI_BW_MODE, *PBTC_WIFI_BW_MODE;
+
+typedef enum _BTC_WIFI_TRAFFIC_DIR {
+	BTC_WIFI_TRAFFIC_TX					= 0x0,
+	BTC_WIFI_TRAFFIC_RX					= 0x1,
+	BTC_WIFI_TRAFFIC_MAX
+} BTC_WIFI_TRAFFIC_DIR, *PBTC_WIFI_TRAFFIC_DIR;
+
+typedef enum _BTC_WIFI_PNP {
+	BTC_WIFI_PNP_WAKE_UP					= 0x0,
+	BTC_WIFI_PNP_SLEEP						= 0x1,
+	BTC_WIFI_PNP_SLEEP_KEEP_ANT				= 0x2,
+	BTC_WIFI_PNP_WOWLAN					= 0x3,
+	BTC_WIFI_PNP_MAX
+} BTC_WIFI_PNP, *PBTC_WIFI_PNP;
+
+typedef enum _BTC_IOT_PEER {
+	BTC_IOT_PEER_UNKNOWN = 0,
+	BTC_IOT_PEER_REALTEK = 1,
+	BTC_IOT_PEER_REALTEK_92SE = 2,
+	BTC_IOT_PEER_BROADCOM = 3,
+	BTC_IOT_PEER_RALINK = 4,
+	BTC_IOT_PEER_ATHEROS = 5,
+	BTC_IOT_PEER_CISCO = 6,
+	BTC_IOT_PEER_MERU = 7,
+	BTC_IOT_PEER_MARVELL = 8,
+	BTC_IOT_PEER_REALTEK_SOFTAP = 9, /* peer is RealTek SOFT_AP, by Bohn, 2009.12.17 */
+	BTC_IOT_PEER_SELF_SOFTAP = 10, /* Self is SoftAP */
+	BTC_IOT_PEER_AIRGO = 11,
+	BTC_IOT_PEER_INTEL				= 12,
+	BTC_IOT_PEER_RTK_APCLIENT		= 13,
+	BTC_IOT_PEER_REALTEK_81XX		= 14,
+	BTC_IOT_PEER_REALTEK_WOW		= 15,
+	BTC_IOT_PEER_REALTEK_JAGUAR_BCUTAP = 16,
+	BTC_IOT_PEER_REALTEK_JAGUAR_CCUTAP = 17,
+	BTC_IOT_PEER_MAX,
+} BTC_IOT_PEER, *PBTC_IOT_PEER;
+
+/* for 8723b-d cut large current issue */
+typedef enum _BTC_WIFI_COEX_STATE {
+	BTC_WIFI_STAT_INIT,
+	BTC_WIFI_STAT_IQK,
+	BTC_WIFI_STAT_NORMAL_OFF,
+	BTC_WIFI_STAT_MP_OFF,
+	BTC_WIFI_STAT_NORMAL,
+	BTC_WIFI_STAT_ANT_DIV,
+	BTC_WIFI_STAT_MAX
+} BTC_WIFI_COEX_STATE, *PBTC_WIFI_COEX_STATE;
+
+typedef enum _BTC_ANT_TYPE {
+	BTC_ANT_TYPE_0,
+	BTC_ANT_TYPE_1,
+	BTC_ANT_TYPE_2,
+	BTC_ANT_TYPE_3,
+	BTC_ANT_TYPE_4,
+	BTC_ANT_TYPE_MAX
+} BTC_ANT_TYPE, *PBTC_ANT_TYPE;
+
+typedef enum _BTC_VENDOR {
+	BTC_VENDOR_LENOVO,
+	BTC_VENDOR_ASUS,
+	BTC_VENDOR_OTHER
+} BTC_VENDOR, *PBTC_VENDOR;
+
+
+/* defined for BFP_BTC_GET */
+typedef enum _BTC_GET_TYPE {
+	/* type BOOLEAN */
+	BTC_GET_BL_HS_OPERATION,
+	BTC_GET_BL_HS_CONNECTING,
+	BTC_GET_BL_WIFI_FW_READY,
+	BTC_GET_BL_WIFI_CONNECTED,
+	BTC_GET_BL_WIFI_DUAL_BAND_CONNECTED,
+	BTC_GET_BL_WIFI_LINK_INFO,
+	BTC_GET_BL_WIFI_BUSY,
+	BTC_GET_BL_WIFI_SCAN,
+	BTC_GET_BL_WIFI_LINK,
+	BTC_GET_BL_WIFI_ROAM,
+	BTC_GET_BL_WIFI_4_WAY_PROGRESS,
+	BTC_GET_BL_WIFI_UNDER_5G,
+	BTC_GET_BL_WIFI_AP_MODE_ENABLE,
+	BTC_GET_BL_WIFI_ENABLE_ENCRYPTION,
+	BTC_GET_BL_WIFI_UNDER_B_MODE,
+	BTC_GET_BL_EXT_SWITCH,
+	BTC_GET_BL_WIFI_IS_IN_MP_MODE,
+	BTC_GET_BL_IS_ASUS_8723B,
+	BTC_GET_BL_RF4CE_CONNECTED,
+	BTC_GET_BL_WIFI_LW_PWR_STATE,
+
+	/* type s4Byte */
+	BTC_GET_S4_WIFI_RSSI,
+	BTC_GET_S4_HS_RSSI,
+
+	/* type u4Byte */
+	BTC_GET_U4_WIFI_BW,
+	BTC_GET_U4_WIFI_TRAFFIC_DIRECTION,
+	BTC_GET_U4_WIFI_FW_VER,
+	BTC_GET_U4_WIFI_LINK_STATUS,
+	BTC_GET_U4_BT_PATCH_VER,
+	BTC_GET_U4_VENDOR,
+	BTC_GET_U4_SUPPORTED_VERSION,
+	BTC_GET_U4_SUPPORTED_FEATURE,
+	BTC_GET_U4_BT_DEVICE_INFO,
+	BTC_GET_U4_BT_FORBIDDEN_SLOT_VAL,
+	BTC_GET_U4_WIFI_IQK_TOTAL,
+	BTC_GET_U4_WIFI_IQK_OK,
+	BTC_GET_U4_WIFI_IQK_FAIL,
+
+	/* type u1Byte */
+	BTC_GET_U1_WIFI_DOT11_CHNL,
+	BTC_GET_U1_WIFI_CENTRAL_CHNL,
+	BTC_GET_U1_WIFI_HS_CHNL,
+	BTC_GET_U1_WIFI_P2P_CHNL,
+	BTC_GET_U1_MAC_PHY_MODE,
+	BTC_GET_U1_AP_NUM,
+	BTC_GET_U1_ANT_TYPE,
+	BTC_GET_U1_IOT_PEER,
+
+	/* type u2Byte */
+	BTC_GET_U2_BEACON_PERIOD,
+
+	/*===== for 1Ant ======*/
+	BTC_GET_U1_LPS_MODE,
+
+	BTC_GET_MAX
+} BTC_GET_TYPE, *PBTC_GET_TYPE;
+
+/* defined for BFP_BTC_SET */
+typedef enum _BTC_SET_TYPE {
+	/* type BOOLEAN */
+	BTC_SET_BL_BT_DISABLE,
+	BTC_SET_BL_BT_ENABLE_DISABLE_CHANGE,
+	BTC_SET_BL_BT_TRAFFIC_BUSY,
+	BTC_SET_BL_BT_LIMITED_DIG,
+	BTC_SET_BL_FORCE_TO_ROAM,
+	BTC_SET_BL_TO_REJ_AP_AGG_PKT,
+	BTC_SET_BL_BT_CTRL_AGG_SIZE,
+	BTC_SET_BL_INC_SCAN_DEV_NUM,
+	BTC_SET_BL_BT_TX_RX_MASK,
+	BTC_SET_BL_MIRACAST_PLUS_BT,
+	BTC_SET_BL_BT_LNA_CONSTRAIN_LEVEL,
+
+	/* type u1Byte */
+	BTC_SET_U1_RSSI_ADJ_VAL_FOR_AGC_TABLE_ON,
+	BTC_SET_U1_AGG_BUF_SIZE,
+
+	/* type trigger some action */
+	BTC_SET_ACT_GET_BT_RSSI,
+	BTC_SET_ACT_AGGREGATE_CTRL,
+	BTC_SET_ACT_ANTPOSREGRISTRY_CTRL,
+
+	// for mimo ps mode setting
+	BTC_SET_MIMO_PS_MODE,
+	/*===== for 1Ant ======*/
+	/* type BOOLEAN */
+
+	/* type u1Byte */
+	BTC_SET_U1_RSSI_ADJ_VAL_FOR_1ANT_COEX_TYPE,
+	BTC_SET_U1_LPS_VAL,
+	BTC_SET_U1_RPWM_VAL,
+	/* type trigger some action */
+	BTC_SET_ACT_LEAVE_LPS,
+	BTC_SET_ACT_ENTER_LPS,
+	BTC_SET_ACT_NORMAL_LPS,
+	BTC_SET_ACT_PRE_NORMAL_LPS,
+	BTC_SET_ACT_POST_NORMAL_LPS,
+	BTC_SET_ACT_DISABLE_LOW_POWER,
+	BTC_SET_ACT_UPDATE_RAMASK,
+	BTC_SET_ACT_SEND_MIMO_PS,
+	/* BT Coex related */
+	BTC_SET_ACT_CTRL_BT_INFO,
+	BTC_SET_ACT_CTRL_BT_COEX,
+	BTC_SET_ACT_CTRL_8723B_ANT,
+	/*=================*/
+	BTC_SET_MAX
+} BTC_SET_TYPE, *PBTC_SET_TYPE;
+
+typedef enum _BTC_DBG_DISP_TYPE {
+	BTC_DBG_DISP_COEX_STATISTICS				= 0x0,
+	BTC_DBG_DISP_BT_LINK_INFO				= 0x1,
+	BTC_DBG_DISP_WIFI_STATUS				= 0x2,
+	BTC_DBG_DISP_MAX
+} BTC_DBG_DISP_TYPE, *PBTC_DBG_DISP_TYPE;
+
+typedef enum _BTC_NOTIFY_TYPE_IPS {
+	BTC_IPS_LEAVE							= 0x0,
+	BTC_IPS_ENTER							= 0x1,
+	BTC_IPS_MAX
+} BTC_NOTIFY_TYPE_IPS, *PBTC_NOTIFY_TYPE_IPS;
+typedef enum _BTC_NOTIFY_TYPE_LPS {
+	BTC_LPS_DISABLE							= 0x0,
+	BTC_LPS_ENABLE							= 0x1,
+	BTC_LPS_MAX
+} BTC_NOTIFY_TYPE_LPS, *PBTC_NOTIFY_TYPE_LPS;
+typedef enum _BTC_NOTIFY_TYPE_SCAN {
+	BTC_SCAN_FINISH							= 0x0,
+	BTC_SCAN_START							= 0x1,
+	BTC_SCAN_START_2G						= 0x2,
+	BTC_SCAN_START_5G						= 0x3,
+	BTC_SCAN_MAX
+} BTC_NOTIFY_TYPE_SCAN, *PBTC_NOTIFY_TYPE_SCAN;
+typedef enum _BTC_NOTIFY_TYPE_SWITCHBAND {
+	BTC_NOT_SWITCH							= 0x0,
+	BTC_SWITCH_TO_24G						= 0x1,
+	BTC_SWITCH_TO_5G						= 0x2,
+	BTC_SWITCH_TO_24G_NOFORSCAN				= 0x3,
+	BTC_SWITCH_MAX
+} BTC_NOTIFY_TYPE_SWITCHBAND, *PBTC_NOTIFY_TYPE_SWITCHBAND;
+typedef enum _BTC_NOTIFY_TYPE_ASSOCIATE {
+	BTC_ASSOCIATE_FINISH						= 0x0,
+	BTC_ASSOCIATE_START						= 0x1,
+	BTC_ASSOCIATE_5G_FINISH						= 0x2,
+	BTC_ASSOCIATE_5G_START						= 0x3,
+	BTC_ASSOCIATE_MAX
+} BTC_NOTIFY_TYPE_ASSOCIATE, *PBTC_NOTIFY_TYPE_ASSOCIATE;
+typedef enum _BTC_NOTIFY_TYPE_MEDIA_STATUS {
+	BTC_MEDIA_DISCONNECT					= 0x0,
+	BTC_MEDIA_CONNECT						= 0x1,
+	BTC_MEDIA_CONNECT_5G					= 0x02,
+	BTC_MEDIA_MAX
+} BTC_NOTIFY_TYPE_MEDIA_STATUS, *PBTC_NOTIFY_TYPE_MEDIA_STATUS;
+typedef enum _BTC_NOTIFY_TYPE_SPECIFIC_PACKET {
+	BTC_PACKET_UNKNOWN					= 0x0,
+	BTC_PACKET_DHCP							= 0x1,
+	BTC_PACKET_ARP							= 0x2,
+	BTC_PACKET_EAPOL						= 0x3,
+	BTC_PACKET_MAX
+} BTC_NOTIFY_TYPE_SPECIFIC_PACKET, *PBTC_NOTIFY_TYPE_SPECIFIC_PACKET;
+typedef enum _BTC_NOTIFY_TYPE_STACK_OPERATION {
+	BTC_STACK_OP_NONE					= 0x0,
+	BTC_STACK_OP_INQ_PAGE_PAIR_START		= 0x1,
+	BTC_STACK_OP_INQ_PAGE_PAIR_FINISH	= 0x2,
+	BTC_STACK_OP_MAX
+} BTC_NOTIFY_TYPE_STACK_OPERATION, *PBTC_NOTIFY_TYPE_STACK_OPERATION;
+
+/* Bryant Add */
+typedef enum _BTC_ANTENNA_POS {
+	BTC_ANTENNA_AT_MAIN_PORT				= 0x1,
+	BTC_ANTENNA_AT_AUX_PORT				= 0x2,
+} BTC_ANTENNA_POS, *PBTC_ANTENNA_POS;
+
+/* Bryant Add */
+typedef enum _BTC_BT_OFFON {
+	BTC_BT_OFF				= 0x0,
+	BTC_BT_ON				= 0x1,
+} BTC_BTOFFON, *PBTC_BT_OFFON;
+
+#define BTC_5G_BAND 0x80
+
+/*==================================================
+For following block is for coex offload
+==================================================*/
+typedef struct _COL_H2C {
+	u1Byte	opcode;
+	u1Byte	opcode_ver:4;
+	u1Byte	req_num:4;
+	u1Byte	buf[1];
+} COL_H2C, *PCOL_H2C;
+
+#define	COL_C2H_ACK_HDR_LEN	3
+typedef struct _COL_C2H_ACK {
+	u1Byte	status;
+	u1Byte	opcode_ver:4;
+	u1Byte	req_num:4;
+	u1Byte	ret_len;
+	u1Byte	buf[1];
+} COL_C2H_ACK, *PCOL_C2H_ACK;
+
+#define	COL_C2H_IND_HDR_LEN	3
+typedef struct _COL_C2H_IND {
+	u1Byte	type;
+	u1Byte	version;
+	u1Byte	length;
+	u1Byte	data[1];
+} COL_C2H_IND, *PCOL_C2H_IND;
+
+/*============================================
+NOTE: for debug message, the following define should match
+the strings in coexH2cResultString.
+============================================*/
+typedef enum _COL_H2C_STATUS {
+	/* c2h status */
+	COL_STATUS_C2H_OK								= 0x00, /* Wifi received H2C request and check content ok. */
+	COL_STATUS_C2H_UNKNOWN							= 0x01,	/* Not handled routine */
+	COL_STATUS_C2H_UNKNOWN_OPCODE					= 0x02,	/* Invalid OP code, It means that wifi firmware received an undefiend OP code. */
+	COL_STATUS_C2H_OPCODE_VER_MISMATCH			= 0x03, /* Wifi firmware and wifi driver mismatch, need to update wifi driver or wifi or. */
+	COL_STATUS_C2H_PARAMETER_ERROR				= 0x04, /* Error paraneter.(ex: parameters = NULL but it should have values) */
+	COL_STATUS_C2H_PARAMETER_OUT_OF_RANGE		= 0x05, /* Wifi firmware needs to check the parameters from H2C request and return the status.(ex: ch = 500, it's wrong) */
+	/* other COL status start from here */
+	COL_STATUS_C2H_REQ_NUM_MISMATCH			, /* c2h req_num mismatch, means this c2h is not we expected. */
+	COL_STATUS_H2C_HALMAC_FAIL					, /* HALMAC return fail. */
+	COL_STATUS_H2C_TIMTOUT						, /* not received the c2h response from fw */
+	COL_STATUS_INVALID_C2H_LEN					, /* invalid coex offload c2h ack length, must >= 3 */
+	COL_STATUS_COEX_DATA_OVERFLOW				, /* coex returned length over the c2h ack length. */
+	COL_STATUS_MAX
+} COL_H2C_STATUS, *PCOL_H2C_STATUS;
+
+#define	COL_MAX_H2C_REQ_NUM		16
+
+#define	COL_H2C_BUF_LEN			20
+typedef enum _COL_OPCODE {
+	COL_OP_WIFI_STATUS_NOTIFY					= 0x0,
+	COL_OP_WIFI_PROGRESS_NOTIFY					= 0x1,
+	COL_OP_WIFI_INFO_NOTIFY						= 0x2,
+	COL_OP_WIFI_POWER_STATE_NOTIFY				= 0x3,
+	COL_OP_SET_CONTROL							= 0x4,
+	COL_OP_GET_CONTROL							= 0x5,
+	COL_OP_WIFI_OPCODE_MAX
+} COL_OPCODE, *PCOL_OPCODE;
+
+typedef enum _COL_IND_TYPE {
+	COL_IND_BT_INFO								= 0x0,
+	COL_IND_PSTDMA								= 0x1,
+	COL_IND_LIMITED_TX_RX						= 0x2,
+	COL_IND_COEX_TABLE							= 0x3,
+	COL_IND_REQ									= 0x4,
+	COL_IND_MAX
+} COL_IND_TYPE, *PCOL_IND_TYPE;
+
+typedef struct _COL_SINGLE_H2C_RECORD {
+	u1Byte					h2c_buf[COL_H2C_BUF_LEN];	/* the latest sent h2c buffer */
+	u4Byte					h2c_len;
+	u1Byte					c2h_ack_buf[COL_H2C_BUF_LEN];	/* the latest received c2h buffer */
+	u4Byte					c2h_ack_len;
+	u4Byte					count;									/* the total number of the sent h2c command */
+	u4Byte					status[COL_STATUS_MAX];					/* the c2h status for the sent h2c command */
+} COL_SINGLE_H2C_RECORD, *PCOL_SINGLE_H2C_RECORD;
+
+typedef struct _COL_SINGLE_C2H_IND_RECORD {
+	u1Byte					ind_buf[COL_H2C_BUF_LEN];	/* the latest received c2h indication buffer */
+	u4Byte					ind_len;
+	u4Byte					count;									/* the total number of the rcvd c2h indication */
+	u4Byte					status[COL_STATUS_MAX];					/* the c2h indication verified status */
+} COL_SINGLE_C2H_IND_RECORD, *PCOL_SINGLE_C2H_IND_RECORD;
+
+typedef struct _BTC_OFFLOAD {
+	/* H2C command related */
+	u1Byte					h2c_req_num;
+	u4Byte					cnt_h2c_sent;
+	COL_SINGLE_H2C_RECORD	h2c_record[COL_OP_WIFI_OPCODE_MAX];
+
+	/* C2H Ack related */
+	u4Byte					cnt_c2h_ack;
+	u4Byte					status[COL_STATUS_MAX];
+	struct completion		c2h_event[COL_MAX_H2C_REQ_NUM];	/* for req_num = 1~COL_MAX_H2C_REQ_NUM */
+	u1Byte					c2h_ack_buf[COL_MAX_H2C_REQ_NUM][COL_H2C_BUF_LEN];
+	u1Byte					c2h_ack_len[COL_MAX_H2C_REQ_NUM];
+
+	/* C2H Indication related */
+	u4Byte						cnt_c2h_ind;
+	COL_SINGLE_C2H_IND_RECORD	c2h_ind_record[COL_IND_MAX];
+	u4Byte						c2h_ind_status[COL_STATUS_MAX];
+	u1Byte						c2h_ind_buf[COL_H2C_BUF_LEN];
+	u1Byte						c2h_ind_len;
+} BTC_OFFLOAD, *PBTC_OFFLOAD;
+extern BTC_OFFLOAD				gl_coex_offload;
+/*==================================================*/
+
+/* BTC_LINK_MODE same as WIFI_LINK_MODE */
+typedef enum _BTC_LINK_MODE{
+	BTC_LINK_NONE=0,
+	BTC_LINK_ONLY_GO,
+	BTC_LINK_ONLY_GC,
+	BTC_LINK_ONLY_STA,
+	BTC_LINK_ONLY_AP,
+	BTC_LINK_2G_MCC_GO_STA,
+	BTC_LINK_5G_MCC_GO_STA,
+	BTC_LINK_25G_MCC_GO_STA,
+	BTC_LINK_2G_MCC_GC_STA,
+	BTC_LINK_5G_MCC_GC_STA,
+	BTC_LINK_25G_MCC_GC_STA,
+	BTC_LINK_2G_SCC_GO_STA,
+	BTC_LINK_5G_SCC_GO_STA,
+	BTC_LINK_2G_SCC_GC_STA,
+	BTC_LINK_5G_SCC_GC_STA,
+	BTC_LINK_MAX=30
+}BTC_LINK_MODE, *PBTC_LINK_MODE;
+
+
+struct btc_wifi_link_info {
+	BTC_LINK_MODE link_mode; /* LinkMode */
+	u1Byte sta_center_channel; /* StaCenterChannel */
+	u1Byte p2p_center_channel; /* P2PCenterChannel	*/
+	BOOLEAN bany_client_join_go;
+	BOOLEAN benable_noa;
+	BOOLEAN bhotspot;
+};
+
+typedef enum _BTC_MULTI_PORT_TDMA_MODE {
+	BTC_MULTI_PORT_TDMA_MODE_NONE=0,
+	BTC_MULTI_PORT_TDMA_MODE_2G_SCC_GO,
+	BTC_MULTI_PORT_TDMA_MODE_2G_P2P_GO,
+	BTC_MULTI_PORT_TDMA_MODE_2G_HOTSPOT_GO
+} BTC_MULTI_PORT_TDMA_MODE, *PBTC_MULTI_PORT_TDMA_MODE;
+
+typedef struct btc_multi_port_tdma_info {
+	BTC_MULTI_PORT_TDMA_MODE btc_multi_port_tdma_mode;
+	u1Byte start_time_from_bcn;
+	u1Byte bt_time;
+} BTC_MULTI_PORT_TDMA_INFO, *PBTC_MULTI_PORT_TDMA_INFO;
+
+typedef u1Byte
+(*BFP_BTC_R1)(
+	IN	PVOID			pBtcContext,
+	IN	u4Byte			RegAddr
+	);
+typedef u2Byte
+(*BFP_BTC_R2)(
+	IN	PVOID			pBtcContext,
+	IN	u4Byte			RegAddr
+	);
+typedef u4Byte
+(*BFP_BTC_R4)(
+	IN	PVOID			pBtcContext,
+	IN	u4Byte			RegAddr
+	);
+typedef VOID
+(*BFP_BTC_W1)(
+	IN	PVOID			pBtcContext,
+	IN	u4Byte			RegAddr,
+	IN	u1Byte			Data
+	);
+typedef VOID
+(*BFP_BTC_W1_BIT_MASK)(
+	IN	PVOID			pBtcContext,
+	IN	u4Byte			regAddr,
+	IN	u1Byte			bitMask,
+	IN	u1Byte			data1b
+	);
+typedef VOID
+(*BFP_BTC_W2)(
+	IN	PVOID			pBtcContext,
+	IN	u4Byte			RegAddr,
+	IN	u2Byte			Data
+	);
+typedef VOID
+(*BFP_BTC_W4)(
+	IN	PVOID			pBtcContext,
+	IN	u4Byte			RegAddr,
+	IN	u4Byte			Data
+	);
+typedef VOID
+(*BFP_BTC_LOCAL_REG_W1)(
+	IN	PVOID			pBtcContext,
+	IN	u4Byte			RegAddr,
+	IN	u1Byte			Data
+	);
+typedef VOID
+(*BFP_BTC_SET_BB_REG)(
+	IN	PVOID			pBtcContext,
+	IN	u4Byte			RegAddr,
+	IN	u4Byte			BitMask,
+	IN	u4Byte			Data
+	);
+typedef u4Byte
+(*BFP_BTC_GET_BB_REG)(
+	IN	PVOID			pBtcContext,
+	IN	u4Byte			RegAddr,
+	IN	u4Byte			BitMask
+	);
+typedef VOID
+(*BFP_BTC_SET_RF_REG)(
+	IN	PVOID			pBtcContext,
+	IN	enum rf_path		eRFPath,
+	IN	u4Byte			RegAddr,
+	IN	u4Byte			BitMask,
+	IN	u4Byte			Data
+	);
+typedef u4Byte
+(*BFP_BTC_GET_RF_REG)(
+	IN	PVOID			pBtcContext,
+	IN	enum rf_path		eRFPath,
+	IN	u4Byte			RegAddr,
+	IN	u4Byte			BitMask
+	);
+typedef VOID
+(*BFP_BTC_FILL_H2C)(
+	IN	PVOID			pBtcContext,
+	IN	u1Byte			elementId,
+	IN	u4Byte			cmdLen,
+	IN	pu1Byte			pCmdBuffer
+	);
+
+typedef	BOOLEAN
+(*BFP_BTC_GET)(
+	IN	PVOID			pBtCoexist,
+	IN	u1Byte			getType,
+	OUT	PVOID			pOutBuf
+	);
+
+typedef	BOOLEAN
+(*BFP_BTC_SET)(
+	IN	PVOID			pBtCoexist,
+	IN	u1Byte			setType,
+	OUT	PVOID			pInBuf
+	);
+typedef u2Byte
+(*BFP_BTC_SET_BT_REG)(
+	IN	PVOID			pBtcContext,
+	IN	u1Byte			regType,
+	IN	u4Byte			offset,
+	IN	u4Byte			value
+	);
+typedef BOOLEAN
+(*BFP_BTC_SET_BT_ANT_DETECTION)(
+	IN	PVOID			pBtcContext,
+	IN	u1Byte			txTime,
+	IN	u1Byte			btChnl
+	);
+
+typedef BOOLEAN
+(*BFP_BTC_SET_BT_TRX_MASK)(
+	IN	PVOID			pBtcContext,
+	IN	u1Byte			bt_trx_mask
+	);
+
+typedef u4Byte
+(*BFP_BTC_GET_BT_REG)(
+	IN	PVOID			pBtcContext,
+	IN	u1Byte			regType,
+	IN	u4Byte			offset
+	);
+typedef VOID
+(*BFP_BTC_DISP_DBG_MSG)(
+	IN	PVOID			pBtCoexist,
+	IN	u1Byte			dispType
+	);
+
+typedef COL_H2C_STATUS
+(*BFP_BTC_COEX_H2C_PROCESS)(
+	IN	PVOID			pBtCoexist,
+	IN	u1Byte			opcode,
+	IN	u1Byte			opcode_ver,
+	IN	pu1Byte			ph2c_par,
+	IN	u1Byte			h2c_par_len
+	);
+
+typedef u4Byte
+(*BFP_BTC_GET_BT_COEX_SUPPORTED_FEATURE)(
+	IN	PVOID			pBtcContext
+	);
+
+typedef u4Byte
+(*BFP_BTC_GET_BT_COEX_SUPPORTED_VERSION)(
+	IN	PVOID			pBtcContext
+	);
+
+typedef u4Byte
+(*BFP_BTC_GET_PHYDM_VERSION)(
+	IN	PVOID			pBtcContext
+	);
+
+typedef u4Byte
+(*BFP_BTC_SET_ATOMIC) 	(
+	IN	PVOID			pBtcContext,
+	IN	pu4Byte 		target,
+	IN	u4Byte			val
+	);
+
+
+typedef VOID
+(*BTC_PHYDM_MODIFY_RA_PCR_THRESHLOD)(
+	IN	PVOID		pDM_Odm,
+	IN	u1Byte		RA_offset_direction,
+	IN	u1Byte		RA_threshold_offset
+	);
+
+typedef u4Byte
+(*BTC_PHYDM_CMNINFOQUERY)(
+	IN		PVOID	pDM_Odm,
+	IN		u1Byte	info_type
+	);
+
+typedef VOID
+(*BTC_PHYDM_MODIFY_ANTDIV_HWSW)(
+	IN		PVOID	pDM_Odm,
+	IN		u1Byte	type
+	);
+
+typedef u1Byte
+(*BFP_BTC_GET_ANT_DET_VAL_FROM_BT)(
+
+	IN	PVOID			pBtcContext
+	);
+
+typedef u1Byte
+(*BFP_BTC_GET_BLE_SCAN_TYPE_FROM_BT)(
+	IN	PVOID			pBtcContext
+	);
+
+typedef u4Byte
+(*BFP_BTC_GET_BLE_SCAN_PARA_FROM_BT)(
+	IN	PVOID			pBtcContext,
+	IN  u1Byte			scanType
+	);
+
+typedef BOOLEAN
+(*BFP_BTC_GET_BT_AFH_MAP_FROM_BT)(
+	IN	PVOID			pBtcContext,
+	IN	u1Byte			mapType,
+	OUT	pu1Byte			afhMap
+	);
+
+struct  btc_bt_info {
+	boolean					bt_disabled;
+	boolean				bt_enable_disable_change;
+	u8					rssi_adjust_for_agc_table_on;
+	u8					rssi_adjust_for_1ant_coex_type;
+	boolean					pre_bt_ctrl_agg_buf_size;
+	boolean					bt_ctrl_agg_buf_size;
+	boolean					pre_reject_agg_pkt;
+	boolean					reject_agg_pkt;
+	boolean					increase_scan_dev_num;
+	boolean					bt_tx_rx_mask;
+	u8					pre_agg_buf_size;
+	u8					agg_buf_size;
+	boolean					bt_busy;
+	boolean					limited_dig;
+	u16					bt_hci_ver;
+	u16					bt_real_fw_ver;
+	u8					bt_fw_ver;
+	u32					get_bt_fw_ver_cnt;
+	u32					bt_get_fw_ver;
+	boolean					miracast_plus_bt;
+
+	boolean					bt_disable_low_pwr;
+
+	boolean					bt_ctrl_lps;
+	boolean					bt_lps_on;
+	boolean					force_to_roam;	/* for 1Ant solution */
+	u8					lps_val;
+	u8					rpwm_val;
+	u32					ra_mask;
+};
+
+struct btc_stack_info {
+	boolean					profile_notified;
+	u16					hci_version;	/* stack hci version */
+	u8					num_of_link;
+	boolean					bt_link_exist;
+	boolean					sco_exist;
+	boolean					acl_exist;
+	boolean					a2dp_exist;
+	boolean					hid_exist;
+	u8					num_of_hid;
+	boolean					pan_exist;
+	boolean					unknown_acl_exist;
+	s8					min_bt_rssi;
+};
+
+struct btc_bt_link_info {
+	boolean					bt_link_exist;
+	boolean					bt_hi_pri_link_exist;
+	boolean					sco_exist;
+	boolean					sco_only;
+	boolean					a2dp_exist;
+	boolean					a2dp_only;
+	boolean					hid_exist;
+	boolean					hid_only;
+	boolean					pan_exist;
+	boolean					pan_only;
+	boolean					slave_role;
+	boolean					acl_busy;
+};
+
+#ifdef CONFIG_RF4CE_COEXIST
+struct btc_rf4ce_info {
+	u8					link_state;
+};
+#endif
+
+struct btc_statistics {
+	u32					cnt_bind;
+	u32					cnt_power_on;
+	u32					cnt_pre_load_firmware;
+	u32					cnt_init_hw_config;
+	u32					cnt_init_coex_dm;
+	u32					cnt_ips_notify;
+	u32					cnt_lps_notify;
+	u32					cnt_scan_notify;
+	u32					cnt_connect_notify;
+	u32					cnt_media_status_notify;
+	u32					cnt_specific_packet_notify;
+	u32					cnt_bt_info_notify;
+	u32					cnt_rf_status_notify;
+	u32					cnt_periodical;
+	u32					cnt_coex_dm_switch;
+	u32					cnt_stack_operation_notify;
+	u32					cnt_dbg_ctrl;
+	u32					cnt_rate_id_notify;
+	u32					cnt_halt_notify;
+	u32					cnt_pnp_notify;
+};
+
+struct btc_coexist {
+	BOOLEAN				bBinded;		/*make sure only one adapter can bind the data context*/
+	PVOID				Adapter;		/*default adapter*/
+	struct  btc_board_info		board_info;
+	struct  btc_bt_info			bt_info;		/*some bt info referenced by non-bt module*/
+	struct  btc_stack_info		stack_info;
+	struct  btc_bt_link_info		bt_link_info;
+	struct btc_wifi_link_info	wifi_link_info;
+
+#ifdef CONFIG_RF4CE_COEXIST
+	struct  btc_rf4ce_info		rf4ce_info;
+#endif
+	BTC_CHIP_INTERFACE		chip_interface;
+	PVOID					odm_priv;
+
+	BOOLEAN					initilized;
+	BOOLEAN					stop_coex_dm;
+	BOOLEAN					manual_control;
+	BOOLEAN					bdontenterLPS;
+	pu1Byte					cli_buf;
+	struct btc_statistics		statistics;
+	u1Byte				pwrModeVal[10];
+	BOOLEAN dbg_mode;
+	BOOLEAN auto_report;
+
+	/* function pointers */
+	/* io related */
+	BFP_BTC_R1			btc_read_1byte;
+	BFP_BTC_W1			btc_write_1byte;
+	BFP_BTC_W1_BIT_MASK	btc_write_1byte_bitmask;
+	BFP_BTC_R2			btc_read_2byte;
+	BFP_BTC_W2			btc_write_2byte;
+	BFP_BTC_R4			btc_read_4byte;
+	BFP_BTC_W4			btc_write_4byte;
+	BFP_BTC_LOCAL_REG_W1	btc_write_local_reg_1byte;
+	/* read/write bb related */
+	BFP_BTC_SET_BB_REG	btc_set_bb_reg;
+	BFP_BTC_GET_BB_REG	btc_get_bb_reg;
+
+	/* read/write rf related */
+	BFP_BTC_SET_RF_REG	btc_set_rf_reg;
+	BFP_BTC_GET_RF_REG	btc_get_rf_reg;
+
+	/* fill h2c related */
+	BFP_BTC_FILL_H2C		btc_fill_h2c;
+	/* other */
+	BFP_BTC_DISP_DBG_MSG	btc_disp_dbg_msg;
+	/* normal get/set related */
+	BFP_BTC_GET			btc_get;
+	BFP_BTC_SET			btc_set;
+
+	BFP_BTC_GET_BT_REG	btc_get_bt_reg;
+	BFP_BTC_SET_BT_REG	btc_set_bt_reg;
+
+	BFP_BTC_SET_BT_ANT_DETECTION	btc_set_bt_ant_detection;
+
+	BFP_BTC_COEX_H2C_PROCESS	btc_coex_h2c_process;
+	BFP_BTC_SET_BT_TRX_MASK		btc_set_bt_trx_mask;
+	BFP_BTC_GET_BT_COEX_SUPPORTED_FEATURE btc_get_bt_coex_supported_feature;
+	BFP_BTC_GET_BT_COEX_SUPPORTED_VERSION btc_get_bt_coex_supported_version;
+	BFP_BTC_GET_PHYDM_VERSION		btc_get_bt_phydm_version;
+	BFP_BTC_SET_ATOMIC			btc_set_atomic;
+	BTC_PHYDM_MODIFY_RA_PCR_THRESHLOD	btc_phydm_modify_RA_PCR_threshold;
+	BTC_PHYDM_CMNINFOQUERY				btc_phydm_query_PHY_counter;
+	BTC_PHYDM_MODIFY_ANTDIV_HWSW		btc_phydm_modify_antdiv_hwsw;
+	BFP_BTC_GET_ANT_DET_VAL_FROM_BT		btc_get_ant_det_val_from_bt;
+	BFP_BTC_GET_BLE_SCAN_TYPE_FROM_BT	btc_get_ble_scan_type_from_bt;
+	BFP_BTC_GET_BLE_SCAN_PARA_FROM_BT	btc_get_ble_scan_para_from_bt;
+	BFP_BTC_GET_BT_AFH_MAP_FROM_BT		btc_get_bt_afh_map_from_bt;
+
+	union {
+		#ifdef CONFIG_RTL8822B
+		struct coex_dm_8822b_1ant	coex_dm_8822b_1ant;
+		struct coex_dm_8822b_2ant	coex_dm_8822b_2ant;
+		#endif /* 8822B */
+		#ifdef CONFIG_RTL8821C
+		struct coex_dm_8821c_1ant	coex_dm_8821c_1ant;
+		struct coex_dm_8821c_2ant	coex_dm_8821c_2ant;
+		#endif /* 8821C */
+	};
+
+	union {
+		#ifdef CONFIG_RTL8822B
+		struct coex_sta_8822b_1ant	coex_sta_8822b_1ant;
+		struct coex_sta_8822b_2ant	coex_sta_8822b_2ant;
+		#endif /* 8822B */
+		#ifdef CONFIG_RTL8821C
+		struct coex_sta_8821c_1ant	coex_sta_8821c_1ant;
+		struct coex_sta_8821c_2ant	coex_sta_8821c_2ant;
+		#endif /* 8821C */
+	};
+
+	union {
+		#ifdef CONFIG_RTL8822B
+		struct rfe_type_8822b_1ant	rfe_type_8822b_1ant;
+		struct rfe_type_8822b_2ant	rfe_type_8822b_2ant;
+		#endif /* 8822B */
+		#ifdef CONFIG_RTL8821C
+		struct rfe_type_8821c_1ant	rfe_type_8821c_1ant;
+		struct rfe_type_8821c_2ant	rfe_type_8821c_2ant;
+		#endif /* 8821C */
+	};
+
+	union {
+		#ifdef CONFIG_RTL8822B
+		struct wifi_link_info_8822b_1ant	wifi_link_info_8822b_1ant;
+		struct wifi_link_info_8822b_2ant	wifi_link_info_8822b_2ant;
+		#endif /* 8822B */
+		#ifdef CONFIG_RTL8821C
+		struct wifi_link_info_8821c_1ant	wifi_link_info_8821c_1ant;
+		struct wifi_link_info_8821c_2ant	wifi_link_info_8821c_2ant;
+		#endif /* 8821C */
+	};
+
+};
+typedef struct btc_coexist *PBTC_COEXIST;
+
+extern struct btc_coexist	GLBtCoexist;
+
+BOOLEAN
+EXhalbtcoutsrc_InitlizeVariables(
+	IN	PVOID		Adapter
+	);
+VOID
+EXhalbtcoutsrc_PowerOnSetting(
+	IN	PBTC_COEXIST		pBtCoexist
+	);
+VOID
+EXhalbtcoutsrc_PreLoadFirmware(
+	IN	PBTC_COEXIST		pBtCoexist
+	);
+VOID
+EXhalbtcoutsrc_InitHwConfig(
+	IN	PBTC_COEXIST		pBtCoexist,
+	IN	BOOLEAN				bWifiOnly
+	);
+VOID
+EXhalbtcoutsrc_InitCoexDm(
+	IN	PBTC_COEXIST		pBtCoexist
+	);
+VOID
+EXhalbtcoutsrc_IpsNotify(
+	IN	PBTC_COEXIST		pBtCoexist,
+	IN	u1Byte			type
+	);
+VOID
+EXhalbtcoutsrc_LpsNotify(
+	IN	PBTC_COEXIST		pBtCoexist,
+	IN	u1Byte			type
+	);
+VOID
+EXhalbtcoutsrc_ScanNotify(
+	IN	PBTC_COEXIST		pBtCoexist,
+	IN	u1Byte			type
+	);
+VOID
+EXhalbtcoutsrc_SetAntennaPathNotify(
+	IN	PBTC_COEXIST	pBtCoexist,
+	IN	u1Byte			type
+	);
+VOID
+EXhalbtcoutsrc_ConnectNotify(
+	IN	PBTC_COEXIST		pBtCoexist,
+	IN	u1Byte			action
+	);
+VOID
+EXhalbtcoutsrc_MediaStatusNotify(
+	IN	PBTC_COEXIST		pBtCoexist,
+	IN	RT_MEDIA_STATUS	mediaStatus
+	);
+VOID
+EXhalbtcoutsrc_SpecificPacketNotify(
+	IN	PBTC_COEXIST		pBtCoexist,
+	IN	u1Byte			pktType
+	);
+VOID
+EXhalbtcoutsrc_BtInfoNotify(
+	IN	PBTC_COEXIST		pBtCoexist,
+	IN	pu1Byte			tmpBuf,
+	IN	u1Byte			length
+	);
+VOID
+EXhalbtcoutsrc_RfStatusNotify(
+	IN	PBTC_COEXIST		pBtCoexist,
+	IN	u1Byte				type
+	);
+VOID
+EXhalbtcoutsrc_WlFwDbgInfoNotify(
+	IN	PBTC_COEXIST		pBtCoexist,
+	IN	pu1Byte			tmpBuf,
+	IN	u1Byte			length
+	);
+VOID
+EXhalbtcoutsrc_rx_rate_change_notify(
+	IN	PBTC_COEXIST	pBtCoexist,
+	IN 	BOOLEAN			is_data_frame,
+	IN	u1Byte			btc_rate_id
+	);
+VOID
+EXhalbtcoutsrc_StackOperationNotify(
+	IN	PBTC_COEXIST		pBtCoexist,
+	IN	u1Byte			type
+	);
+VOID
+EXhalbtcoutsrc_HaltNotify(
+	IN	PBTC_COEXIST		pBtCoexist
+	);
+VOID
+EXhalbtcoutsrc_PnpNotify(
+	IN	PBTC_COEXIST		pBtCoexist,
+	IN	u1Byte			pnpState
+	);
+VOID
+EXhalbtcoutsrc_CoexDmSwitch(
+	IN	PBTC_COEXIST		pBtCoexist
+	);
+VOID
+EXhalbtcoutsrc_Periodical(
+	IN	PBTC_COEXIST		pBtCoexist
+	);
+VOID
+EXhalbtcoutsrc_DbgControl(
+	IN	PBTC_COEXIST			pBtCoexist,
+	IN	u1Byte				opCode,
+	IN	u1Byte				opLen,
+	IN	pu1Byte				pData
+	);
+VOID
+EXhalbtcoutsrc_AntennaDetection(
+	IN	PBTC_COEXIST			pBtCoexist,
+	IN	u4Byte					centFreq,
+	IN	u4Byte					offset,
+	IN	u4Byte					span,
+	IN	u4Byte					seconds
+	);
+VOID
+EXhalbtcoutsrc_StackUpdateProfileInfo(
+	VOID
+	);
+VOID
+EXhalbtcoutsrc_SetHciVersion(
+	IN	u2Byte	hciVersion
+	);
+VOID
+EXhalbtcoutsrc_SetBtPatchVersion(
+	IN	u2Byte	btHciVersion,
+	IN	u2Byte	btPatchVersion
+	);
+VOID
+EXhalbtcoutsrc_UpdateMinBtRssi(
+	IN	s1Byte	btRssi
+	);
+#if 0
+VOID
+EXhalbtcoutsrc_SetBtExist(
+	IN	BOOLEAN		bBtExist
+	);
+#endif
+VOID
+EXhalbtcoutsrc_SetChipType(
+	IN	u1Byte		chipType
+	);
+VOID
+EXhalbtcoutsrc_SetAntNum(
+	IN	u1Byte		type,
+	IN	u1Byte		antNum
+	);
+VOID
+EXhalbtcoutsrc_SetSingleAntPath(
+	IN	u1Byte		singleAntPath
+	);
+VOID
+EXhalbtcoutsrc_DisplayBtCoexInfo(
+	IN	PBTC_COEXIST		pBtCoexist
+	);
+VOID
+EXhalbtcoutsrc_DisplayAntDetection(
+	IN	PBTC_COEXIST		pBtCoexist
+	);
+
+#define	MASKBYTE0		0xff
+#define	MASKBYTE1		0xff00
+#define	MASKBYTE2		0xff0000
+#define	MASKBYTE3		0xff000000
+#define	MASKHWORD	0xffff0000
+#define	MASKLWORD		0x0000ffff
+#define	MASKDWORD	0xffffffff
+#define	MASK12BITS		0xfff
+#define	MASKH4BITS		0xf0000000
+#define	MASKOFDM_D	0xffc00000
+#define	MASKCCK		0x3f3f3f3f
+
+#endif
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/btc/mp_precomp.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/btc/mp_precomp.h
--- linux-5.6.3/3rdparty/rtl8821ce/hal/btc/mp_precomp.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/btc/mp_precomp.h	2020-04-10 16:35:06.786658667 +0300
@@ -0,0 +1,131 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2013 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#ifndef __MP_PRECOMP_H__
+#define __MP_PRECOMP_H__
+
+#include <drv_types.h>
+#include <hal_data.h>
+
+#define BT_TMP_BUF_SIZE	100
+
+#ifdef PLATFORM_LINUX
+#define rsprintf snprintf
+#define rstrncat(dst, src, src_size) strncat(dst, src, src_size)
+#elif defined(PLATFORM_WINDOWS)
+#define rsprintf sprintf_s
+#endif
+
+#define DCMD_Printf			DBG_BT_INFO
+
+#define delay_ms(ms)		rtw_mdelay_os(ms)
+
+#ifdef bEnable
+#undef bEnable
+#endif
+
+#define WPP_SOFTWARE_TRACE 0
+
+typedef enum _BTC_MSG_COMP_TYPE {
+	COMP_COEX		= 0,
+	COMP_MAX
+} BTC_MSG_COMP_TYPE;
+extern u4Byte GLBtcDbgType[];
+
+#define DBG_OFF			0
+#define DBG_SEC			1
+#define DBG_SERIOUS		2
+#define DBG_WARNING		3
+#define DBG_LOUD		4
+#define DBG_TRACE		5
+
+#ifdef CONFIG_BT_COEXIST
+#define BT_SUPPORT		1
+#define COEX_SUPPORT	1
+#define HS_SUPPORT		1
+#else
+#define BT_SUPPORT		0
+#define COEX_SUPPORT	0
+#define HS_SUPPORT		0
+#endif
+
+/* for wifi only mode */
+#include "hal_btcoex_wifionly.h"
+
+#ifdef CONFIG_BT_COEXIST
+
+struct wifi_only_cfg;
+struct btc_coexist;
+
+#ifdef CONFIG_RTL8192E
+#include "halbtc8192e1ant.h"
+#include "halbtc8192e2ant.h"
+#endif
+
+#ifdef CONFIG_RTL8723B
+#include "halbtc8723bwifionly.h"
+#include "halbtc8723b1ant.h"
+#include "halbtc8723b2ant.h"
+#endif
+
+#ifdef CONFIG_RTL8812A
+#include "halbtc8812a1ant.h"
+#include "halbtc8812a2ant.h"
+#endif
+
+#ifdef CONFIG_RTL8821A
+#include "halbtc8821a1ant.h"
+#include "halbtc8821a2ant.h"
+#endif
+
+#ifdef CONFIG_RTL8703B
+#include "halbtc8703b1ant.h"
+#endif
+
+#ifdef CONFIG_RTL8723D
+#include "halbtc8723d1ant.h"
+#include "halbtc8723d2ant.h"
+#endif
+
+#ifdef CONFIG_RTL8822B
+#include "halbtc8822bwifionly.h"
+#include "halbtc8822b1ant.h"
+#include "halbtc8822b2ant.h"
+#endif
+
+#ifdef CONFIG_RTL8821C
+#include "halbtc8821cwifionly.h"
+#include "halbtc8821c1ant.h"
+#include "halbtc8821c2ant.h"
+#endif
+
+#include "halbtcoutsrc.h"
+
+#else /* CONFIG_BT_COEXIST */
+
+#ifdef CONFIG_RTL8723B
+#include "halbtc8723bwifionly.h"
+#endif
+
+#ifdef CONFIG_RTL8822B
+#include "halbtc8822bwifionly.h"
+#endif
+
+#ifdef CONFIG_RTL8821C
+#include "halbtc8821cwifionly.h"
+#endif
+
+#endif /* CONFIG_BT_COEXIST */
+
+#endif /*  __MP_PRECOMP_H__ */
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/efuse/efuse_mask.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/efuse/efuse_mask.h
--- linux-5.6.3/3rdparty/rtl8821ce/hal/efuse/efuse_mask.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/efuse/efuse_mask.h	2020-04-10 16:35:06.786658667 +0300
@@ -0,0 +1,164 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2016 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+
+#ifdef CONFIG_USB_HCI
+
+	#if defined(CONFIG_RTL8188E)
+		#include "rtl8188e/HalEfuseMask8188E_USB.h"
+	#endif
+
+	#if defined(CONFIG_RTL8812A)
+		#include "rtl8812a/HalEfuseMask8812A_USB.h"
+	#endif
+
+	#if defined(CONFIG_RTL8821A)
+		#include "rtl8812a/HalEfuseMask8821A_USB.h"
+	#endif
+
+	#if defined(CONFIG_RTL8192E)
+		#include "rtl8192e/HalEfuseMask8192E_USB.h"
+	#endif
+
+	#if defined(CONFIG_RTL8723B)
+		#include "rtl8723b/HalEfuseMask8723B_USB.h"
+	#endif
+
+	#if defined(CONFIG_RTL8814A)
+		#include "rtl8814a/HalEfuseMask8814A_USB.h"
+	#endif
+
+	#if defined(CONFIG_RTL8703B)
+		#include "rtl8703b/HalEfuseMask8703B_USB.h"
+	#endif
+
+	#if defined(CONFIG_RTL8723D)
+		#include "rtl8723d/HalEfuseMask8723D_USB.h"
+	#endif
+
+	#if defined(CONFIG_RTL8188F)
+		#include "rtl8188f/HalEfuseMask8188F_USB.h"
+	#endif
+
+	#if defined(CONFIG_RTL8188GTV)
+		#include "rtl8188gtv/HalEfuseMask8188GTV_USB.h"
+	#endif
+
+	#if defined(CONFIG_RTL8822B)
+		#include "rtl8822b/HalEfuseMask8822B_USB.h"
+	#endif
+
+	#if defined(CONFIG_RTL8821C)
+		#include "rtl8821c/HalEfuseMask8821C_USB.h"
+	#endif
+	
+	#if defined(CONFIG_RTL8710B)
+		#include "rtl8710b/HalEfuseMask8710B_USB.h"
+	#endif
+	
+	#if defined(CONFIG_RTL8192F)
+		#include "rtl8192f/HalEfuseMask8192F_USB.h"
+	#endif
+#endif /*CONFIG_USB_HCI*/
+
+#ifdef CONFIG_PCI_HCI
+
+	#if defined(CONFIG_RTL8188E)
+		#include "rtl8188e/HalEfuseMask8188E_PCIE.h"
+	#endif
+
+	#if defined(CONFIG_RTL8812A)
+		#include "rtl8812a/HalEfuseMask8812A_PCIE.h"
+	#endif
+
+	#if defined(CONFIG_RTL8821A)
+		#include "rtl8812a/HalEfuseMask8821A_PCIE.h"
+	#endif
+
+	#if defined(CONFIG_RTL8192E)
+		#include "rtl8192e/HalEfuseMask8192E_PCIE.h"
+	#endif
+
+	#if defined(CONFIG_RTL8723B)
+		#include "rtl8723b/HalEfuseMask8723B_PCIE.h"
+	#endif
+
+	#if defined(CONFIG_RTL8814A)
+		#include "rtl8814a/HalEfuseMask8814A_PCIE.h"
+	#endif
+
+	#if defined(CONFIG_RTL8703B)
+		#include "rtl8703b/HalEfuseMask8703B_PCIE.h"
+	#endif
+
+	#if defined(CONFIG_RTL8822B)
+		#include "rtl8822b/HalEfuseMask8822B_PCIE.h"
+	#endif
+	#if defined(CONFIG_RTL8723D)
+		#include "rtl8723d/HalEfuseMask8723D_PCIE.h"
+	#endif
+	#if defined(CONFIG_RTL8821C)
+		#include "rtl8821c/HalEfuseMask8821C_PCIE.h"
+	#endif
+
+	#if defined(CONFIG_RTL8192F)
+		#include "rtl8192f/HalEfuseMask8192F_PCIE.h"
+	#endif
+#endif /*CONFIG_PCI_HCI*/
+#ifdef CONFIG_SDIO_HCI
+	#if defined(CONFIG_RTL8723B)
+		#include "rtl8723b/HalEfuseMask8723B_SDIO.h"
+	#endif
+
+	#if defined(CONFIG_RTL8188E)
+		#include "rtl8188e/HalEfuseMask8188E_SDIO.h"
+	#endif
+
+	#if defined(CONFIG_RTL8703B)
+		#include "rtl8703b/HalEfuseMask8703B_SDIO.h"
+	#endif
+
+	#if defined(CONFIG_RTL8188F)
+		#include "rtl8188f/HalEfuseMask8188F_SDIO.h"
+	#endif
+
+	#if defined(CONFIG_RTL8188GTV)
+		#include "rtl8188gtv/HalEfuseMask8188GTV_SDIO.h"
+	#endif
+
+	#if defined(CONFIG_RTL8723D)
+		#include "rtl8723d/HalEfuseMask8723D_SDIO.h"
+	#endif
+
+	#if defined(CONFIG_RTL8192E)
+		#include "rtl8192e/HalEfuseMask8192E_SDIO.h"
+	#endif
+
+	#if defined(CONFIG_RTL8821A)
+		#include "rtl8812a/HalEfuseMask8821A_SDIO.h"
+	#endif
+
+	#if defined(CONFIG_RTL8821C)
+		#include "rtl8821c/HalEfuseMask8821C_SDIO.h"
+	#endif
+
+	#if defined(CONFIG_RTL8822B)
+		#include "rtl8822b/HalEfuseMask8822B_SDIO.h"
+	#endif
+
+	#if defined(CONFIG_RTL8192F)
+		#include "rtl8192f/HalEfuseMask8192F_SDIO.h"
+	#endif
+
+#endif /*CONFIG_SDIO_HCI*/
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/efuse/rtl8821c/HalEfuseMask8821C_PCIE.c linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/efuse/rtl8821c/HalEfuseMask8821C_PCIE.c
--- linux-5.6.3/3rdparty/rtl8821ce/hal/efuse/rtl8821c/HalEfuseMask8821C_PCIE.c	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/efuse/rtl8821c/HalEfuseMask8821C_PCIE.c	2020-04-10 16:35:06.786658667 +0300
@@ -0,0 +1,95 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+
+/* #include "Mp_Precomp.h" */
+/* #include "../odm_precomp.h" */
+
+#include <drv_types.h>
+#include "HalEfuseMask8821C_PCIE.h"
+
+
+
+/******************************************************************************
+*                           MPCIE.TXT
+******************************************************************************/
+
+u1Byte Array_MP_8821C_MPCIE[] = {
+	0xFF,
+	0xF3,
+	0xEF,
+	0x9E,
+	0x70,
+	0x00,
+	0x00,
+	0x00,
+	0x00,
+	0x00,
+	0x00,
+	0x03,
+	0xF7,
+	0xFF,
+	0xFF,
+	0xFF,
+	0xFF,
+	0xFF,
+	0xF1,
+	0x00,
+	0x00,
+	0x00,
+	0x00,
+	0x00,
+	0x00,
+	0x00,
+	0x00,
+	0x00,
+	0x00,
+	0x00,
+	0x00,
+	0x00,
+
+};
+
+u2Byte
+EFUSE_GetArrayLen_MP_8821C_MPCIE(VOID)
+{
+	return sizeof(Array_MP_8821C_MPCIE) / sizeof(u1Byte);
+}
+
+VOID
+EFUSE_GetMaskArray_MP_8821C_MPCIE(
+	IN	OUT pu1Byte Array
+)
+{
+	u2Byte len = EFUSE_GetArrayLen_MP_8821C_MPCIE(), i = 0;
+
+	for (i = 0; i < len; ++i)
+		Array[i] = Array_MP_8821C_MPCIE[i];
+}
+BOOLEAN
+EFUSE_IsAddressMasked_MP_8821C_MPCIE(
+	IN   u2Byte  Offset
+)
+{
+	int r = Offset / 16;
+	int c = (Offset % 16) / 2;
+	int result = 0;
+
+	if (c < 4) /* Upper double word */
+		result = (Array_MP_8821C_MPCIE[r] & (0x10 << c));
+	else
+		result = (Array_MP_8821C_MPCIE[r] & (0x01 << (c - 4)));
+
+	return (result > 0) ? 0 : 1;
+}
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/efuse/rtl8821c/HalEfuseMask8821C_PCIE.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/efuse/rtl8821c/HalEfuseMask8821C_PCIE.h
--- linux-5.6.3/3rdparty/rtl8821ce/hal/efuse/rtl8821c/HalEfuseMask8821C_PCIE.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/efuse/rtl8821c/HalEfuseMask8821C_PCIE.h	2020-04-10 16:35:06.786658667 +0300
@@ -0,0 +1,34 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+
+
+
+/******************************************************************************
+*                           MPCIE.TXT
+******************************************************************************/
+
+
+u2Byte
+EFUSE_GetArrayLen_MP_8821C_MPCIE(VOID);
+
+VOID
+EFUSE_GetMaskArray_MP_8821C_MPCIE(
+	IN	OUT pu1Byte Array
+);
+
+BOOLEAN
+EFUSE_IsAddressMasked_MP_8821C_MPCIE(/* TC: Test Chip, MP: MP Chip */
+	IN   u2Byte  Offset
+);
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/efuse/rtl8821c/HalEfuseMask8821C_SDIO.c linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/efuse/rtl8821c/HalEfuseMask8821C_SDIO.c
--- linux-5.6.3/3rdparty/rtl8821ce/hal/efuse/rtl8821c/HalEfuseMask8821C_SDIO.c	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/efuse/rtl8821c/HalEfuseMask8821C_SDIO.c	2020-04-10 16:35:06.786658667 +0300
@@ -0,0 +1,95 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+
+/* #include "Mp_Precomp.h" */
+/* #include "../odm_precomp.h" */
+
+#include <drv_types.h>
+#include "HalEfuseMask8821C_SDIO.h"
+
+
+
+/******************************************************************************
+*                           MSDIO.TXT
+******************************************************************************/
+
+u1Byte Array_MP_8821C_MSDIO[] = {
+	0xFF,
+	0xF3,
+	0xEF,
+	0x9E,
+	0x70,
+	0x00,
+	0x00,
+	0x00,
+	0x00,
+	0x00,
+	0x00,
+	0x03,
+	0xF7,
+	0xFF,
+	0xFF,
+	0xFF,
+	0xFF,
+	0xFF,
+	0x00,
+	0x00,
+	0x00,
+	0x00,
+	0x00,
+	0x00,
+	0x00,
+	0x00,
+	0x00,
+	0x00,
+	0x00,
+	0x00,
+	0x00,
+	0x00,
+
+};
+
+u2Byte
+EFUSE_GetArrayLen_MP_8821C_MSDIO(VOID)
+{
+	return sizeof(Array_MP_8821C_MSDIO) / sizeof(u1Byte);
+}
+
+VOID
+EFUSE_GetMaskArray_MP_8821C_MSDIO(
+	IN	OUT pu1Byte Array
+)
+{
+	u2Byte len = EFUSE_GetArrayLen_MP_8821C_MSDIO(), i = 0;
+
+	for (i = 0; i < len; ++i)
+		Array[i] = Array_MP_8821C_MSDIO[i];
+}
+BOOLEAN
+EFUSE_IsAddressMasked_MP_8821C_MSDIO(
+	IN   u2Byte  Offset
+)
+{
+	int r = Offset / 16;
+	int c = (Offset % 16) / 2;
+	int result = 0;
+
+	if (c < 4) /* Upper double word */
+		result = (Array_MP_8821C_MSDIO[r] & (0x10 << c));
+	else
+		result = (Array_MP_8821C_MSDIO[r] & (0x01 << (c - 4)));
+
+	return (result > 0) ? 0 : 1;
+}
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/efuse/rtl8821c/HalEfuseMask8821C_SDIO.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/efuse/rtl8821c/HalEfuseMask8821C_SDIO.h
--- linux-5.6.3/3rdparty/rtl8821ce/hal/efuse/rtl8821c/HalEfuseMask8821C_SDIO.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/efuse/rtl8821c/HalEfuseMask8821C_SDIO.h	2020-04-10 16:35:06.786658667 +0300
@@ -0,0 +1,34 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+
+
+
+/******************************************************************************
+*                           MSDIO.TXT
+******************************************************************************/
+
+
+u2Byte
+EFUSE_GetArrayLen_MP_8821C_MSDIO(VOID);
+
+VOID
+EFUSE_GetMaskArray_MP_8821C_MSDIO(
+	IN	OUT pu1Byte Array
+);
+
+BOOLEAN
+EFUSE_IsAddressMasked_MP_8821C_MSDIO(/* TC: Test Chip, MP: MP Chip */
+	IN   u2Byte  Offset
+);
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/efuse/rtl8821c/HalEfuseMask8821C_USB.c linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/efuse/rtl8821c/HalEfuseMask8821C_USB.c
--- linux-5.6.3/3rdparty/rtl8821ce/hal/efuse/rtl8821c/HalEfuseMask8821C_USB.c	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/efuse/rtl8821c/HalEfuseMask8821C_USB.c	2020-04-10 16:35:06.786658667 +0300
@@ -0,0 +1,95 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+
+/* #include "Mp_Precomp.h" */
+/* #include "../odm_precomp.h" */
+
+#include <drv_types.h>
+#include "HalEfuseMask8821C_USB.h"
+
+
+
+/******************************************************************************
+*                           MUSB.TXT
+******************************************************************************/
+
+u1Byte Array_MP_8821C_MUSB[] = {
+		0xFF,
+		0xF3,
+		0xEF,
+		0x9E,
+		0x70,
+		0x00,
+		0x00,
+		0x00,
+		0x00,
+		0x00,
+		0x00,
+		0x03,
+		0xF7,
+		0x00,
+		0x00,
+		0x00,
+		0xFF,
+		0xFF,
+		0xFF,
+		0xFF,
+		0xC0,
+		0x00,
+		0x00,
+		0x00,
+		0x00,
+		0x00,
+		0x00,
+		0x00,
+		0x00,
+		0x00,
+		0x00,
+		0x00,
+
+};
+
+u2Byte
+EFUSE_GetArrayLen_MP_8821C_MUSB(VOID)
+{
+	return sizeof(Array_MP_8821C_MUSB) / sizeof(u1Byte);
+}
+
+VOID
+EFUSE_GetMaskArray_MP_8821C_MUSB(
+	IN	OUT pu1Byte Array
+)
+{
+	u2Byte len = EFUSE_GetArrayLen_MP_8821C_MUSB(), i = 0;
+
+	for (i = 0; i < len; ++i)
+		Array[i] = Array_MP_8821C_MUSB[i];
+}
+BOOLEAN
+EFUSE_IsAddressMasked_MP_8821C_MUSB(
+	IN   u2Byte  Offset
+)
+{
+	int r = Offset / 16;
+	int c = (Offset % 16) / 2;
+	int result = 0;
+
+	if (c < 4) /* Upper double word */
+		result = (Array_MP_8821C_MUSB[r] & (0x10 << c));
+	else
+		result = (Array_MP_8821C_MUSB[r] & (0x01 << (c - 4)));
+
+	return (result > 0) ? 0 : 1;
+}
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/efuse/rtl8821c/HalEfuseMask8821C_USB.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/efuse/rtl8821c/HalEfuseMask8821C_USB.h
--- linux-5.6.3/3rdparty/rtl8821ce/hal/efuse/rtl8821c/HalEfuseMask8821C_USB.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/efuse/rtl8821c/HalEfuseMask8821C_USB.h	2020-04-10 16:35:06.786658667 +0300
@@ -0,0 +1,34 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+
+
+
+/******************************************************************************
+*                           MUSB.TXT
+******************************************************************************/
+
+
+u2Byte
+EFUSE_GetArrayLen_MP_8821C_MUSB(VOID);
+
+VOID
+EFUSE_GetMaskArray_MP_8821C_MUSB(
+	IN	OUT pu1Byte Array
+);
+
+BOOLEAN
+EFUSE_IsAddressMasked_MP_8821C_MUSB(/* TC: Test Chip, MP: MP Chip */
+	IN   u2Byte  Offset
+);
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/hal_btcoex.c linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/hal_btcoex.c
--- linux-5.6.3/3rdparty/rtl8821ce/hal/hal_btcoex.c	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/hal_btcoex.c	2020-04-10 16:35:06.787658714 +0300
@@ -0,0 +1,5699 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2013 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#define __HAL_BTCOEX_C__
+
+#ifdef CONFIG_BT_COEXIST
+
+#include <hal_data.h>
+#include <hal_btcoex.h>
+#include "btc/mp_precomp.h"
+
+/* ************************************
+ *		Global variables
+ * ************************************ */
+const char *const BtProfileString[] = {
+	"NONE",
+	"A2DP",
+	"PAN",
+	"HID",
+	"SCO",
+};
+
+const char *const BtSpecString[] = {
+	"1.0b",
+	"1.1",
+	"1.2",
+	"2.0+EDR",
+	"2.1+EDR",
+	"3.0+HS",
+	"4.0",
+};
+
+const char *const BtLinkRoleString[] = {
+	"Master",
+	"Slave",
+};
+
+const char *const h2cStaString[] = {
+	"successful",
+	"h2c busy",
+	"rf off",
+	"fw not read",
+};
+
+const char *const ioStaString[] = {
+	"success",
+	"can not IO",
+	"rf off",
+	"fw not read",
+	"wait io timeout",
+	"invalid len",
+	"idle Q empty",
+	"insert waitQ fail",
+	"unknown fail",
+	"wrong level",
+	"h2c stopped",
+};
+
+const char *const GLBtcWifiBwString[] = {
+	"11bg",
+	"HT20",
+	"HT40",
+	"VHT80",
+	"VHT160"
+};
+
+const char *const GLBtcWifiFreqString[] = {
+	"2.4G",
+	"5G",
+	"2.4G+5G"
+};
+
+const char *const GLBtcIotPeerString[] = {
+	"UNKNOWN",
+	"REALTEK",
+	"REALTEK_92SE",
+	"BROADCOM",
+	"RALINK",
+	"ATHEROS",
+	"CISCO",
+	"MERU",
+	"MARVELL",
+	"REALTEK_SOFTAP", /* peer is RealTek SOFT_AP, by Bohn, 2009.12.17 */
+	"SELF_SOFTAP", /* Self is SoftAP */
+	"AIRGO",
+	"INTEL",
+	"RTK_APCLIENT",
+	"REALTEK_81XX",
+	"REALTEK_WOW",
+	"REALTEK_JAGUAR_BCUTAP",
+	"REALTEK_JAGUAR_CCUTAP"
+};
+
+const char *const coexOpcodeString[] = {
+	"Wifi status notify",
+	"Wifi progress",
+	"Wifi info",
+	"Power state",
+	"Set Control",
+	"Get Control"
+};
+
+const char *const coexIndTypeString[] = {
+	"bt info",
+	"pstdma",
+	"limited tx/rx",
+	"coex table",
+	"request"
+};
+
+const char *const coexH2cResultString[] = {
+	"ok",
+	"unknown",
+	"un opcode",
+	"opVer MM",
+	"par Err",
+	"par OoR",
+	"reqNum MM",
+	"halMac Fail",
+	"h2c TimeOut",
+	"Invalid c2h Len",
+	"data overflow"
+};
+
+#define HALBTCOUTSRC_AGG_CHK_WINDOW_IN_MS	8000
+
+struct btc_coexist GLBtCoexist;
+BTC_OFFLOAD gl_coex_offload;
+u8 GLBtcWiFiInScanState;
+u8 GLBtcWiFiInIQKState;
+u8 GLBtcWiFiInIPS;
+u8 GLBtcWiFiInLPS;
+u8 GLBtcBtCoexAliveRegistered;
+
+/*
+ * BT control H2C/C2H
+ */
+/* EXT_EID */
+typedef enum _bt_ext_eid {
+	C2H_WIFI_FW_ACTIVE_RSP	= 0,
+	C2H_TRIG_BY_BT_FW
+} BT_EXT_EID;
+
+/* C2H_STATUS */
+typedef enum _bt_c2h_status {
+	BT_STATUS_OK = 0,
+	BT_STATUS_VERSION_MISMATCH,
+	BT_STATUS_UNKNOWN_OPCODE,
+	BT_STATUS_ERROR_PARAMETER
+} BT_C2H_STATUS;
+
+/* C2H BT OP CODES */
+typedef enum _bt_op_code {
+	BT_OP_GET_BT_VERSION					= 0x00,
+	BT_OP_WRITE_REG_ADDR					= 0x0c,
+	BT_OP_WRITE_REG_VALUE					= 0x0d,
+
+	BT_OP_READ_REG							= 0x11,
+
+	BT_LO_OP_GET_AFH_MAP_L					= 0x1e,
+	BT_LO_OP_GET_AFH_MAP_M					= 0x1f,
+	BT_LO_OP_GET_AFH_MAP_H					= 0x20,
+
+	BT_OP_GET_BT_COEX_SUPPORTED_FEATURE		= 0x2a,
+	BT_OP_GET_BT_COEX_SUPPORTED_VERSION		= 0x2b,
+	BT_OP_GET_BT_ANT_DET_VAL				= 0x2c,
+	BT_OP_GET_BT_BLE_SCAN_TYPE				= 0x2d,
+	BT_OP_GET_BT_BLE_SCAN_PARA				= 0x2e,
+	BT_OP_GET_BT_DEVICE_INFO				= 0x30,
+	BT_OP_GET_BT_FORBIDDEN_SLOT_VAL			= 0x31,
+	BT_OP_SET_BT_LANCONSTRAIN_LEVEL			= 0x32,
+	BT_OP_MAX
+} BT_OP_CODE;
+
+#define BTC_MPOPER_TIMEOUT	50	/* unit: ms */
+
+#define C2H_MAX_SIZE		16
+u8 GLBtcBtMpOperSeq;
+_mutex GLBtcBtMpOperLock;
+_timer GLBtcBtMpOperTimer;
+_sema GLBtcBtMpRptSema;
+u8 GLBtcBtMpRptSeq;
+u8 GLBtcBtMpRptStatus;
+u8 GLBtcBtMpRptRsp[C2H_MAX_SIZE];
+u8 GLBtcBtMpRptRspSize;
+u8 GLBtcBtMpRptWait;
+u8 GLBtcBtMpRptWiFiOK;
+u8 GLBtcBtMpRptBTOK;
+
+/*
+ * Debug
+ */
+u32 GLBtcDbgType[COMP_MAX];
+u8 GLBtcDbgBuf[BT_TMP_BUF_SIZE];
+u1Byte	gl_btc_trace_buf[BT_TMP_BUF_SIZE];
+
+typedef struct _btcoexdbginfo {
+	u8 *info;
+	u32 size; /* buffer total size */
+	u32 len; /* now used length */
+} BTCDBGINFO, *PBTCDBGINFO;
+
+BTCDBGINFO GLBtcDbgInfo;
+
+#define	BT_Operation(Adapter)						_FALSE
+
+static void DBG_BT_INFO_INIT(PBTCDBGINFO pinfo, u8 *pbuf, u32 size)
+{
+	if (NULL == pinfo)
+		return;
+
+	_rtw_memset(pinfo, 0, sizeof(BTCDBGINFO));
+
+	if (pbuf && size) {
+		pinfo->info = pbuf;
+		pinfo->size = size;
+	}
+}
+
+void DBG_BT_INFO(u8 *dbgmsg)
+{
+	PBTCDBGINFO pinfo;
+	u32 msglen, buflen;
+	u8 *pbuf;
+
+
+	pinfo = &GLBtcDbgInfo;
+
+	if (NULL == pinfo->info)
+		return;
+
+	msglen = strlen(dbgmsg);
+	if (pinfo->len + msglen > pinfo->size)
+		return;
+
+	pbuf = pinfo->info + pinfo->len;
+	_rtw_memcpy(pbuf, dbgmsg, msglen);
+	pinfo->len += msglen;
+}
+
+/* ************************************
+ *		Debug related function
+ * ************************************ */
+static u8 halbtcoutsrc_IsBtCoexistAvailable(PBTC_COEXIST pBtCoexist)
+{
+	if (!pBtCoexist->bBinded ||
+	    NULL == pBtCoexist->Adapter)
+		return _FALSE;
+	return _TRUE;
+}
+
+static void halbtcoutsrc_DbgInit(void)
+{
+	u8	i;
+
+	for (i = 0; i < COMP_MAX; i++)
+		GLBtcDbgType[i] = 0;
+}
+
+static u8 halbtcoutsrc_IsCsrBtCoex(PBTC_COEXIST pBtCoexist)
+{
+	if (pBtCoexist->board_info.bt_chip_type == BTC_CHIP_CSR_BC4
+	    || pBtCoexist->board_info.bt_chip_type == BTC_CHIP_CSR_BC8
+	   )
+		return _TRUE;
+	return _FALSE;
+}
+
+static void halbtcoutsrc_EnterPwrLock(PBTC_COEXIST pBtCoexist)
+{
+	struct dvobj_priv *dvobj = adapter_to_dvobj((PADAPTER)pBtCoexist->Adapter);
+	struct pwrctrl_priv *pwrpriv = dvobj_to_pwrctl(dvobj);
+
+	_enter_pwrlock(&pwrpriv->lock);
+}
+
+static void halbtcoutsrc_ExitPwrLock(PBTC_COEXIST pBtCoexist)
+{
+	struct dvobj_priv *dvobj = adapter_to_dvobj((PADAPTER)pBtCoexist->Adapter);
+	struct pwrctrl_priv *pwrpriv = dvobj_to_pwrctl(dvobj);
+
+	_exit_pwrlock(&pwrpriv->lock);
+}
+
+static u8 halbtcoutsrc_IsHwMailboxExist(PBTC_COEXIST pBtCoexist)
+{
+	if (pBtCoexist->board_info.bt_chip_type == BTC_CHIP_CSR_BC4
+	    || pBtCoexist->board_info.bt_chip_type == BTC_CHIP_CSR_BC8
+	   )
+		return _FALSE;
+	else if (IS_HARDWARE_TYPE_8812(pBtCoexist->Adapter))
+		return _FALSE;
+	else
+		return _TRUE;
+}
+
+static u8 halbtcoutsrc_LeaveLps(PBTC_COEXIST pBtCoexist)
+{
+	PADAPTER padapter;
+
+
+	padapter = pBtCoexist->Adapter;
+
+	pBtCoexist->bt_info.bt_ctrl_lps = _TRUE;
+	pBtCoexist->bt_info.bt_lps_on = _FALSE;
+
+	return rtw_btcoex_LPS_Leave(padapter);
+}
+
+void halbtcoutsrc_EnterLps(PBTC_COEXIST pBtCoexist)
+{
+	PADAPTER padapter;
+
+
+	padapter = pBtCoexist->Adapter;
+
+	if (pBtCoexist->bdontenterLPS == _FALSE) {
+		pBtCoexist->bt_info.bt_ctrl_lps = _TRUE;
+		pBtCoexist->bt_info.bt_lps_on = _TRUE;
+
+		rtw_btcoex_LPS_Enter(padapter);
+	}
+}
+
+void halbtcoutsrc_NormalLps(PBTC_COEXIST pBtCoexist)
+{
+	PADAPTER padapter;
+
+
+
+	padapter = pBtCoexist->Adapter;
+
+	if (pBtCoexist->bt_info.bt_ctrl_lps) {
+		pBtCoexist->bt_info.bt_lps_on = _FALSE;
+		rtw_btcoex_LPS_Leave(padapter);
+		pBtCoexist->bt_info.bt_ctrl_lps = _FALSE;
+
+		/* recover the LPS state to the original */
+#if 0
+		padapter->hal_func.UpdateLPSStatusHandler(
+			padapter,
+			pPSC->RegLeisurePsMode,
+			pPSC->RegPowerSaveMode);
+#endif
+	}
+}
+
+void halbtcoutsrc_Pre_NormalLps(PBTC_COEXIST pBtCoexist)
+{
+	PADAPTER padapter;
+
+	padapter = pBtCoexist->Adapter;
+
+	if (pBtCoexist->bt_info.bt_ctrl_lps) {
+		pBtCoexist->bt_info.bt_lps_on = _FALSE;
+		rtw_btcoex_LPS_Leave(padapter);
+	}
+}
+
+void halbtcoutsrc_Post_NormalLps(PBTC_COEXIST pBtCoexist)
+{
+	if (pBtCoexist->bt_info.bt_ctrl_lps)
+		pBtCoexist->bt_info.bt_ctrl_lps = _FALSE;
+}
+
+/*
+ *  Constraint:
+ *	   1. this function will request pwrctrl->lock
+ */
+void halbtcoutsrc_LeaveLowPower(PBTC_COEXIST pBtCoexist)
+{
+#ifdef CONFIG_LPS_LCLK
+	PADAPTER padapter;
+	PHAL_DATA_TYPE pHalData;
+	struct pwrctrl_priv *pwrctrl;
+	s32 ready;
+	systime stime;
+	s32 utime;
+	u32 timeout; /* unit: ms */
+
+
+	padapter = pBtCoexist->Adapter;
+	pHalData = GET_HAL_DATA(padapter);
+	pwrctrl = adapter_to_pwrctl(padapter);
+	ready = _FAIL;
+#ifdef LPS_RPWM_WAIT_MS
+	timeout = LPS_RPWM_WAIT_MS;
+#else /* !LPS_RPWM_WAIT_MS */
+	timeout = 30;
+#endif /* !LPS_RPWM_WAIT_MS */
+
+	if (GLBtcBtCoexAliveRegistered == _TRUE)
+		return;
+
+	stime = rtw_get_current_time();
+	do {
+		ready = rtw_register_task_alive(padapter, BTCOEX_ALIVE);
+		if (_SUCCESS == ready)
+			break;
+
+		utime = rtw_get_passing_time_ms(stime);
+		if (utime > timeout)
+			break;
+
+		rtw_msleep_os(1);
+	} while (1);
+
+	GLBtcBtCoexAliveRegistered = _TRUE;
+#endif /* CONFIG_LPS_LCLK */
+}
+
+/*
+ *  Constraint:
+ *	   1. this function will request pwrctrl->lock
+ */
+void halbtcoutsrc_NormalLowPower(PBTC_COEXIST pBtCoexist)
+{
+#ifdef CONFIG_LPS_LCLK
+	PADAPTER padapter;
+
+	if (GLBtcBtCoexAliveRegistered == _FALSE)
+		return;
+
+	padapter = pBtCoexist->Adapter;
+	rtw_unregister_task_alive(padapter, BTCOEX_ALIVE);
+
+	GLBtcBtCoexAliveRegistered = _FALSE;
+#endif /* CONFIG_LPS_LCLK */
+}
+
+void halbtcoutsrc_DisableLowPower(PBTC_COEXIST pBtCoexist, u8 bLowPwrDisable)
+{
+	pBtCoexist->bt_info.bt_disable_low_pwr = bLowPwrDisable;
+	if (bLowPwrDisable)
+		halbtcoutsrc_LeaveLowPower(pBtCoexist);		/* leave 32k low power. */
+	else
+		halbtcoutsrc_NormalLowPower(pBtCoexist);	/* original 32k low power behavior. */
+}
+
+void halbtcoutsrc_AggregationCheck(PBTC_COEXIST pBtCoexist)
+{
+	PADAPTER padapter;
+	BOOLEAN bNeedToAct = _FALSE;
+	static u32 preTime = 0;
+	u32 curTime = 0;
+
+	padapter = pBtCoexist->Adapter;
+
+	/* ===================================== */
+	/* To void continuous deleteBA=>addBA=>deleteBA=>addBA */
+	/* This function is not allowed to continuous called. */
+	/* It can only be called after 8 seconds. */
+	/* ===================================== */
+
+	curTime = rtw_systime_to_ms(rtw_get_current_time());
+	if ((curTime - preTime) < HALBTCOUTSRC_AGG_CHK_WINDOW_IN_MS)	/* over 8 seconds you can execute this function again. */
+		return;
+	else
+		preTime = curTime;
+
+	if (pBtCoexist->bt_info.reject_agg_pkt) {
+		bNeedToAct = _TRUE;
+		pBtCoexist->bt_info.pre_reject_agg_pkt = pBtCoexist->bt_info.reject_agg_pkt;
+	} else {
+		if (pBtCoexist->bt_info.pre_reject_agg_pkt) {
+			bNeedToAct = _TRUE;
+			pBtCoexist->bt_info.pre_reject_agg_pkt = pBtCoexist->bt_info.reject_agg_pkt;
+		}
+
+		if (pBtCoexist->bt_info.pre_bt_ctrl_agg_buf_size !=
+		    pBtCoexist->bt_info.bt_ctrl_agg_buf_size) {
+			bNeedToAct = _TRUE;
+			pBtCoexist->bt_info.pre_bt_ctrl_agg_buf_size = pBtCoexist->bt_info.bt_ctrl_agg_buf_size;
+		}
+
+		if (pBtCoexist->bt_info.bt_ctrl_agg_buf_size) {
+			if (pBtCoexist->bt_info.pre_agg_buf_size !=
+			    pBtCoexist->bt_info.agg_buf_size)
+				bNeedToAct = _TRUE;
+			pBtCoexist->bt_info.pre_agg_buf_size = pBtCoexist->bt_info.agg_buf_size;
+		}
+	}
+
+	if (bNeedToAct)
+		rtw_btcoex_rx_ampdu_apply(padapter);
+}
+
+u8 halbtcoutsrc_is_autoload_fail(PBTC_COEXIST pBtCoexist)
+{
+	PADAPTER padapter;
+	PHAL_DATA_TYPE pHalData;
+
+	padapter = pBtCoexist->Adapter;
+	pHalData = GET_HAL_DATA(padapter);
+
+	return pHalData->bautoload_fail_flag;
+}
+
+u8 halbtcoutsrc_is_fw_ready(PBTC_COEXIST pBtCoexist)
+{
+	PADAPTER padapter;
+
+	padapter = pBtCoexist->Adapter;
+
+	return GET_HAL_DATA(padapter)->bFWReady;
+}
+
+u8 halbtcoutsrc_IsDualBandConnected(PADAPTER padapter)
+{
+	u8 ret = BTC_MULTIPORT_SCC;
+
+#ifdef CONFIG_MCC_MODE
+	if (MCC_EN(padapter) && (rtw_hal_check_mcc_status(padapter, MCC_STATUS_DOING_MCC))) {
+		struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
+		struct mcc_obj_priv *mccobjpriv = &(dvobj->mcc_objpriv);
+		u8 band0 = mccobjpriv->iface[0]->mlmeextpriv.cur_channel > 14 ? BAND_ON_5G : BAND_ON_2_4G;
+		u8 band1 = mccobjpriv->iface[1]->mlmeextpriv.cur_channel > 14 ? BAND_ON_5G : BAND_ON_2_4G;
+
+		if (band0 != band1)
+			ret = BTC_MULTIPORT_MCC_DUAL_BAND;
+		else
+			ret = BTC_MULTIPORT_MCC_DUAL_CHANNEL;
+	}
+#endif
+
+	return ret;
+}
+
+u8 halbtcoutsrc_IsWifiBusy(PADAPTER padapter)
+{
+	if (rtw_mi_check_status(padapter, MI_AP_ASSOC))
+		return _TRUE;
+	if (rtw_mi_busy_traffic_check(padapter, _FALSE))
+		return _TRUE;
+
+	return _FALSE;
+}
+
+static u32 _halbtcoutsrc_GetWifiLinkStatus(PADAPTER padapter)
+{
+	struct mlme_priv *pmlmepriv;
+	u8 bp2p;
+	u32 portConnectedStatus;
+
+
+	pmlmepriv = &padapter->mlmepriv;
+	bp2p = _FALSE;
+	portConnectedStatus = 0;
+
+#ifdef CONFIG_P2P
+	if (!rtw_p2p_chk_state(&padapter->wdinfo, P2P_STATE_NONE))
+		bp2p = _TRUE;
+#endif /* CONFIG_P2P */
+
+	if (check_fwstate(pmlmepriv, WIFI_ASOC_STATE) == _TRUE) {
+		if (check_fwstate(pmlmepriv, WIFI_AP_STATE) == _TRUE) {
+			if (_TRUE == bp2p)
+				portConnectedStatus |= WIFI_P2P_GO_CONNECTED;
+			else
+				portConnectedStatus |= WIFI_AP_CONNECTED;
+		} else {
+			if (_TRUE == bp2p)
+				portConnectedStatus |= WIFI_P2P_GC_CONNECTED;
+			else
+				portConnectedStatus |= WIFI_STA_CONNECTED;
+		}
+	}
+
+	return portConnectedStatus;
+}
+
+u32 halbtcoutsrc_GetWifiLinkStatus(PBTC_COEXIST pBtCoexist)
+{
+	/* ================================= */
+	/* return value: */
+	/* [31:16]=> connected port number */
+	/* [15:0]=> port connected bit define */
+	/* ================================ */
+
+	PADAPTER padapter;
+	u32 retVal;
+	u32 portConnectedStatus, numOfConnectedPort;
+	struct dvobj_priv *dvobj;
+	_adapter *iface;
+	int i;
+
+	padapter = pBtCoexist->Adapter;
+	retVal = 0;
+	portConnectedStatus = 0;
+	numOfConnectedPort = 0;
+	dvobj = adapter_to_dvobj(padapter);
+
+	for (i = 0; i < dvobj->iface_nums; i++) {
+		iface = dvobj->padapters[i];
+		if ((iface) && rtw_is_adapter_up(iface)) {
+			retVal = _halbtcoutsrc_GetWifiLinkStatus(iface);
+			if (retVal) {
+				portConnectedStatus |= retVal;
+				numOfConnectedPort++;
+			}
+		}
+	}
+	retVal = (numOfConnectedPort << 16) | portConnectedStatus;
+
+	return retVal;
+}
+
+struct btc_wifi_link_info halbtcoutsrc_getwifilinkinfo(PBTC_COEXIST pBtCoexist)
+{
+	u8 n_assoc_iface = 0, i =0, mcc_en = _FALSE;
+	PADAPTER adapter = NULL;
+	PADAPTER iface = NULL;
+	PADAPTER sta_iface = NULL, p2p_iface = NULL, ap_iface = NULL;
+	BTC_LINK_MODE btc_link_moe = BTC_LINK_MAX;
+	struct dvobj_priv *dvobj = NULL;
+	struct mlme_ext_priv *mlmeext = NULL;
+	struct btc_wifi_link_info wifi_link_info;
+
+	adapter = (PADAPTER)pBtCoexist->Adapter;
+	dvobj = adapter_to_dvobj(adapter);
+	n_assoc_iface = rtw_mi_get_assoc_if_num(adapter);
+
+	/* init value */
+	wifi_link_info.link_mode = BTC_LINK_NONE;
+	wifi_link_info.sta_center_channel = 0;
+	wifi_link_info.p2p_center_channel = 0;
+	wifi_link_info.bany_client_join_go = _FALSE;
+	wifi_link_info.benable_noa = _FALSE;
+	wifi_link_info.bhotspot = _FALSE;
+
+	for (i = 0; i < dvobj->iface_nums; i++) {
+		iface = dvobj->padapters[i];
+		if (!iface)
+			continue;
+		
+		mlmeext = &iface->mlmeextpriv;
+		if (MLME_IS_GO(iface)) {
+			wifi_link_info.link_mode = BTC_LINK_ONLY_GO;
+			wifi_link_info.p2p_center_channel =
+				rtw_get_center_ch(mlmeext->cur_channel, mlmeext->cur_bwmode, mlmeext->cur_ch_offset);
+			p2p_iface	 = iface;
+			if (rtw_linked_check(iface))
+				wifi_link_info.bany_client_join_go = _TRUE;
+		} else if (MLME_IS_GC(iface)) {
+			wifi_link_info.link_mode = BTC_LINK_ONLY_GC;
+			wifi_link_info.p2p_center_channel =
+				rtw_get_center_ch(mlmeext->cur_channel, mlmeext->cur_bwmode, mlmeext->cur_ch_offset);
+			p2p_iface = iface;
+		} else if (MLME_IS_AP(iface)) {
+			wifi_link_info.link_mode = BTC_LINK_ONLY_AP;
+			ap_iface = iface;
+			wifi_link_info.p2p_center_channel =
+				rtw_get_center_ch(mlmeext->cur_channel, mlmeext->cur_bwmode, mlmeext->cur_ch_offset);
+		} else if (MLME_IS_STA(iface) && rtw_linked_check(iface)) {
+			wifi_link_info.link_mode = BTC_LINK_ONLY_STA;
+			wifi_link_info.sta_center_channel =
+				rtw_get_center_ch(mlmeext->cur_channel, mlmeext->cur_bwmode, mlmeext->cur_ch_offset);
+			sta_iface = iface;
+		}
+	}
+
+#ifdef CONFIG_MCC_MODE
+	if (MCC_EN(adapter)) {
+		if (rtw_hal_check_mcc_status(adapter, MCC_STATUS_DOING_MCC))
+			mcc_en = _TRUE;
+	}
+#endif/* CONFIG_MCC_MODE */
+
+	if (n_assoc_iface == 0) {
+		wifi_link_info.link_mode = BTC_LINK_NONE;
+	} else if (n_assoc_iface == 1) {
+		/* by pass */
+	} else if (n_assoc_iface == 2) {	
+		if (sta_iface && p2p_iface) {
+			u8 band_sta = sta_iface->mlmeextpriv.cur_channel > 14 ? BAND_ON_5G : BAND_ON_2_4G;
+			u8 band_p2p = p2p_iface->mlmeextpriv.cur_channel > 14 ? BAND_ON_5G : BAND_ON_2_4G;
+			if (band_sta == band_p2p) {
+				switch (band_sta) {
+				case BAND_ON_2_4G:
+					if (MLME_IS_GO(p2p_iface))
+						wifi_link_info.link_mode =
+							mcc_en == _TRUE ?  BTC_LINK_2G_MCC_GO_STA : BTC_LINK_2G_SCC_GO_STA;
+					else if (MLME_IS_GC(p2p_iface))
+						wifi_link_info.link_mode =
+							mcc_en == _TRUE ?  BTC_LINK_2G_MCC_GC_STA : BTC_LINK_2G_SCC_GC_STA;
+					break;
+				case BAND_ON_5G:
+					if (MLME_IS_GO(p2p_iface))
+						wifi_link_info.link_mode =
+							mcc_en == _TRUE ?  BTC_LINK_5G_MCC_GO_STA : BTC_LINK_5G_SCC_GO_STA;
+					else if (MLME_IS_GC(p2p_iface))
+						wifi_link_info.link_mode =
+							mcc_en == _TRUE ?  BTC_LINK_5G_MCC_GC_STA : BTC_LINK_5G_SCC_GC_STA;
+					break;
+				default:
+					break;
+				}
+			} else {
+				if (MLME_IS_GO(p2p_iface))
+					wifi_link_info.link_mode = BTC_LINK_25G_MCC_GO_STA;
+				else if (MLME_IS_GC(p2p_iface))
+					wifi_link_info.link_mode = BTC_LINK_25G_MCC_GC_STA;
+			}
+		}
+	} else {
+		if (pBtCoexist->board_info.btdm_ant_num == 1)
+			RTW_ERR("%s do not support n_assoc_iface > 2 (ant_num == 1)", __func__);
+	}
+
+	return wifi_link_info;
+}
+
+
+static void _btmpoper_timer_hdl(void *p)
+{
+	if (GLBtcBtMpRptWait == _TRUE) {
+		GLBtcBtMpRptWait = _FALSE;
+		_rtw_up_sema(&GLBtcBtMpRptSema);
+	}
+}
+
+/*
+ * !IMPORTANT!
+ *	Before call this function, caller should acquire "GLBtcBtMpOperLock"!
+ *	Othrewise there will be racing problem and something may go wrong.
+ */
+static u8 _btmpoper_cmd(PBTC_COEXIST pBtCoexist, u8 opcode, u8 opcodever, u8 *cmd, u8 size)
+{
+	PADAPTER padapter;
+	u8 buf[H2C_BTMP_OPER_LEN] = {0};
+	u8 buflen;
+	u8 seq;
+	s32 ret;
+
+
+	if (!cmd && size)
+		size = 0;
+	if ((size + 2) > H2C_BTMP_OPER_LEN)
+		return BT_STATUS_H2C_LENGTH_EXCEEDED;
+	buflen = size + 2;
+
+	seq = GLBtcBtMpOperSeq & 0xF;
+	GLBtcBtMpOperSeq++;
+
+	buf[0] = (opcodever & 0xF) | (seq << 4);
+	buf[1] = opcode;
+	if (cmd && size)
+		_rtw_memcpy(buf + 2, cmd, size);
+
+	GLBtcBtMpRptWait = _TRUE;
+	GLBtcBtMpRptWiFiOK = _FALSE;
+	GLBtcBtMpRptBTOK = _FALSE;
+	GLBtcBtMpRptStatus = 0;
+	padapter = pBtCoexist->Adapter;
+	_set_timer(&GLBtcBtMpOperTimer, BTC_MPOPER_TIMEOUT);
+	if (rtw_hal_fill_h2c_cmd(padapter, H2C_BT_MP_OPER, buflen, buf) == _FAIL) {
+		_cancel_timer_ex(&GLBtcBtMpOperTimer);
+		ret = BT_STATUS_H2C_FAIL;
+		goto exit;
+	}
+
+	_rtw_down_sema(&GLBtcBtMpRptSema);
+	/* GLBtcBtMpRptWait should be _FALSE here*/
+
+	if (GLBtcBtMpRptWiFiOK == _FALSE) {
+		RTW_ERR("%s: Didn't get H2C Rsp Event!\n", __FUNCTION__);
+		ret = BT_STATUS_H2C_TIMTOUT;
+		goto exit;
+	}
+	if (GLBtcBtMpRptBTOK == _FALSE) {
+		RTW_DBG("%s: Didn't get BT response!\n", __FUNCTION__);
+		ret = BT_STATUS_H2C_BT_NO_RSP;
+		goto exit;
+	}
+
+	if (seq != GLBtcBtMpRptSeq) {
+		RTW_ERR("%s: Sequence number not match!(%d!=%d)!\n",
+			 __FUNCTION__, seq, GLBtcBtMpRptSeq);
+		ret = BT_STATUS_C2H_REQNUM_MISMATCH;
+		goto exit;
+	}
+
+	switch (GLBtcBtMpRptStatus) {
+	/* Examine the status reported from C2H */
+	case BT_STATUS_OK:
+		ret = BT_STATUS_BT_OP_SUCCESS;
+		RTW_DBG("%s: C2H status = BT_STATUS_BT_OP_SUCCESS\n", __FUNCTION__);
+		break;
+	case BT_STATUS_VERSION_MISMATCH:
+		ret = BT_STATUS_OPCODE_L_VERSION_MISMATCH;
+		RTW_DBG("%s: C2H status = BT_STATUS_OPCODE_L_VERSION_MISMATCH\n", __FUNCTION__);
+		break;
+	case BT_STATUS_UNKNOWN_OPCODE:
+		ret = BT_STATUS_UNKNOWN_OPCODE_L;
+		RTW_DBG("%s: C2H status = MP_BT_STATUS_UNKNOWN_OPCODE_L\n", __FUNCTION__);
+		break;
+	case BT_STATUS_ERROR_PARAMETER:
+		ret = BT_STATUS_PARAMETER_FORMAT_ERROR_L;
+		RTW_DBG("%s: C2H status = MP_BT_STATUS_PARAMETER_FORMAT_ERROR_L\n", __FUNCTION__);
+		break;
+	default:
+		ret = BT_STATUS_UNKNOWN_STATUS_L;
+		RTW_DBG("%s: C2H status = MP_BT_STATUS_UNKNOWN_STATUS_L\n", __FUNCTION__);
+		break;
+	}
+
+exit:
+	return ret;
+}
+
+u32 halbtcoutsrc_GetBtPatchVer(PBTC_COEXIST pBtCoexist)
+{
+	if (pBtCoexist->bt_info.get_bt_fw_ver_cnt <= 5) {
+		if (halbtcoutsrc_IsHwMailboxExist(pBtCoexist) == _TRUE) {
+			_irqL irqL;
+			u8 ret;
+
+			_enter_critical_mutex(&GLBtcBtMpOperLock, &irqL);
+
+			ret = _btmpoper_cmd(pBtCoexist, BT_OP_GET_BT_VERSION, 0, NULL, 0);
+			if (BT_STATUS_BT_OP_SUCCESS == ret) {
+				pBtCoexist->bt_info.bt_real_fw_ver = le16_to_cpu(*(u16 *)GLBtcBtMpRptRsp);
+				pBtCoexist->bt_info.bt_fw_ver = *(GLBtcBtMpRptRsp + 2);
+				pBtCoexist->bt_info.get_bt_fw_ver_cnt++;
+			}
+
+			_exit_critical_mutex(&GLBtcBtMpOperLock, &irqL);
+		} else {
+#ifdef CONFIG_BT_COEXIST_SOCKET_TRX
+			u1Byte dataLen = 2;
+			u1Byte buf[4] = {0};
+
+			buf[0] = 0x0;	/* OP_Code */
+			buf[1] = 0x0;	/* OP_Code_Length */
+			BT_SendEventExtBtCoexControl(pBtCoexist->Adapter, _FALSE, dataLen, &buf[0]);
+#endif /* !CONFIG_BT_COEXIST_SOCKET_TRX */
+		}
+	}
+
+exit:
+	return pBtCoexist->bt_info.bt_real_fw_ver;
+}
+
+s32 halbtcoutsrc_GetWifiRssi(PADAPTER padapter)
+{
+	return rtw_phydm_get_min_rssi(padapter);
+}
+
+u32 halbtcoutsrc_GetBtCoexSupportedFeature(void *pBtcContext)
+{
+	PBTC_COEXIST pBtCoexist;
+	u32 ret = BT_STATUS_BT_OP_SUCCESS;
+	u32 data = 0;
+
+	pBtCoexist = (PBTC_COEXIST)pBtcContext;
+
+	if (halbtcoutsrc_IsHwMailboxExist(pBtCoexist) == _TRUE) {
+		u8 buf[3] = {0};
+		_irqL irqL;
+		u8 op_code;
+		u8 status;
+
+		_enter_critical_mutex(&GLBtcBtMpOperLock, &irqL);
+
+		op_code = BT_OP_GET_BT_COEX_SUPPORTED_FEATURE;
+		status = _btmpoper_cmd(pBtCoexist, op_code, 0, buf, 0);
+		if (status == BT_STATUS_BT_OP_SUCCESS)
+			data = le16_to_cpu(*(u16 *)GLBtcBtMpRptRsp);
+		else
+			ret = SET_BT_MP_OPER_RET(op_code, status);
+
+		_exit_critical_mutex(&GLBtcBtMpOperLock, &irqL);
+
+	} else
+		ret = BT_STATUS_NOT_IMPLEMENT;
+
+	return data;
+}
+
+u32 halbtcoutsrc_GetBtCoexSupportedVersion(void *pBtcContext)
+{
+	PBTC_COEXIST pBtCoexist;
+	u32 ret = BT_STATUS_BT_OP_SUCCESS;
+	u32 data = 0xFFFF;
+
+	pBtCoexist = (PBTC_COEXIST)pBtcContext;
+
+	if (halbtcoutsrc_IsHwMailboxExist(pBtCoexist) == _TRUE) {
+		u8 buf[3] = {0};
+		_irqL irqL;
+		u8 op_code;
+		u8 status;
+
+		_enter_critical_mutex(&GLBtcBtMpOperLock, &irqL);
+
+		op_code = BT_OP_GET_BT_COEX_SUPPORTED_VERSION;
+		status = _btmpoper_cmd(pBtCoexist, op_code, 0, buf, 0);
+		if (status == BT_STATUS_BT_OP_SUCCESS)
+			data = le16_to_cpu(*(u16 *)GLBtcBtMpRptRsp);
+		else
+			ret = SET_BT_MP_OPER_RET(op_code, status);
+
+		_exit_critical_mutex(&GLBtcBtMpOperLock, &irqL);
+
+	} else
+		ret = BT_STATUS_NOT_IMPLEMENT;
+
+	return data;
+}
+
+u32 halbtcoutsrc_GetBtDeviceInfo(void *pBtcContext)
+{
+	PBTC_COEXIST pBtCoexist;
+	u32 ret = BT_STATUS_BT_OP_SUCCESS;
+	u32 btDeviceInfo = 0;
+
+	pBtCoexist = (PBTC_COEXIST)pBtcContext;
+
+	if (halbtcoutsrc_IsHwMailboxExist(pBtCoexist) == _TRUE) {
+		u8 buf[3] = {0};
+		_irqL irqL;
+		u8 op_code;
+		u8 status;
+
+		_enter_critical_mutex(&GLBtcBtMpOperLock, &irqL);
+
+		op_code = BT_OP_GET_BT_DEVICE_INFO;
+		status = _btmpoper_cmd(pBtCoexist, op_code, 0, buf, 0);
+		if (status == BT_STATUS_BT_OP_SUCCESS)
+			btDeviceInfo = le32_to_cpu(*(u32 *)GLBtcBtMpRptRsp);
+		else
+			ret = SET_BT_MP_OPER_RET(op_code, status);
+
+		_exit_critical_mutex(&GLBtcBtMpOperLock, &irqL);
+
+	} else
+		ret = BT_STATUS_NOT_IMPLEMENT;
+
+	return btDeviceInfo;
+}
+
+u32 halbtcoutsrc_GetBtForbiddenSlotVal(void *pBtcContext)
+{
+	PBTC_COEXIST pBtCoexist;
+	u32 ret = BT_STATUS_BT_OP_SUCCESS;
+	u32 btForbiddenSlotVal = 0;
+
+	pBtCoexist = (PBTC_COEXIST)pBtcContext;
+
+	if (halbtcoutsrc_IsHwMailboxExist(pBtCoexist) == _TRUE) {
+		u8 buf[3] = {0};
+		_irqL irqL;
+		u8 op_code;
+		u8 status;
+
+		_enter_critical_mutex(&GLBtcBtMpOperLock, &irqL);
+
+		op_code = BT_OP_GET_BT_FORBIDDEN_SLOT_VAL;
+		status = _btmpoper_cmd(pBtCoexist, op_code, 0, buf, 0);
+		if (status == BT_STATUS_BT_OP_SUCCESS)
+			btForbiddenSlotVal = le32_to_cpu(*(u32 *)GLBtcBtMpRptRsp);
+		else
+			ret = SET_BT_MP_OPER_RET(op_code, status);
+
+		_exit_critical_mutex(&GLBtcBtMpOperLock, &irqL);
+
+	} else
+		ret = BT_STATUS_NOT_IMPLEMENT;
+
+	return btForbiddenSlotVal;
+}
+
+static u8 halbtcoutsrc_GetWifiScanAPNum(PADAPTER padapter)
+{
+	struct mlme_priv *pmlmepriv;
+	struct mlme_ext_priv *pmlmeext;
+	static u8 scan_AP_num = 0;
+
+
+	pmlmepriv = &padapter->mlmepriv;
+	pmlmeext = &padapter->mlmeextpriv;
+
+	if (GLBtcWiFiInScanState == _FALSE) {
+		if (pmlmepriv->num_of_scanned > 0xFF)
+			scan_AP_num = 0xFF;
+		else
+			scan_AP_num = (u8)pmlmepriv->num_of_scanned;
+	}
+
+	return scan_AP_num;
+}
+
+u8 halbtcoutsrc_Get(void *pBtcContext, u8 getType, void *pOutBuf)
+{
+	PBTC_COEXIST pBtCoexist;
+	PADAPTER padapter;
+	PHAL_DATA_TYPE pHalData;
+	struct mlme_ext_priv *mlmeext;
+	struct btc_wifi_link_info *wifi_link_info;
+	u8 bSoftApExist, bVwifiExist;
+	u8 *pu8;
+	s32 *pS4Tmp;
+	u32 *pU4Tmp;
+	u8 *pU1Tmp;
+	u16 *pU2Tmp;
+	u8 ret;
+
+
+	pBtCoexist = (PBTC_COEXIST)pBtcContext;
+	if (!halbtcoutsrc_IsBtCoexistAvailable(pBtCoexist))
+		return _FALSE;
+
+	padapter = pBtCoexist->Adapter;
+	pHalData = GET_HAL_DATA(padapter);
+	mlmeext = &padapter->mlmeextpriv;
+	bSoftApExist = _FALSE;
+	bVwifiExist = _FALSE;
+	pu8 = (u8 *)pOutBuf;
+	pS4Tmp = (s32 *)pOutBuf;
+	pU4Tmp = (u32 *)pOutBuf;
+	pU1Tmp = (u8 *)pOutBuf;
+	pU2Tmp = (u16*)pOutBuf;
+	wifi_link_info = (struct btc_wifi_link_info *)pOutBuf;
+	ret = _TRUE;
+
+	switch (getType) {
+	case BTC_GET_BL_HS_OPERATION:
+		*pu8 = _FALSE;
+		ret = _FALSE;
+		break;
+
+	case BTC_GET_BL_HS_CONNECTING:
+		*pu8 = _FALSE;
+		ret = _FALSE;
+		break;
+
+	case BTC_GET_BL_WIFI_FW_READY:
+		*pu8 = halbtcoutsrc_is_fw_ready(pBtCoexist);
+		break;
+
+	case BTC_GET_BL_WIFI_CONNECTED:
+		*pu8 = (rtw_mi_check_status(padapter, MI_LINKED)) ? _TRUE : _FALSE;
+		break;
+
+	case BTC_GET_BL_WIFI_DUAL_BAND_CONNECTED:
+		*pu8 = halbtcoutsrc_IsDualBandConnected(padapter);
+		break;
+
+	case BTC_GET_BL_WIFI_BUSY:
+		*pu8 = halbtcoutsrc_IsWifiBusy(padapter);
+		break;
+
+	case BTC_GET_BL_WIFI_SCAN:
+#if 0
+		*pu8 = (rtw_mi_check_fwstate(padapter, WIFI_SITE_MONITOR)) ? _TRUE : _FALSE;
+#else
+		/* Use the value of the new variable GLBtcWiFiInScanState to judge whether WiFi is in scan state or not, since the originally used flag
+			WIFI_SITE_MONITOR in fwstate may not be cleared in time */
+		*pu8 = GLBtcWiFiInScanState;
+#endif
+		break;
+
+	case BTC_GET_BL_WIFI_LINK:
+		*pu8 = (rtw_mi_check_status(padapter, MI_STA_LINKING)) ? _TRUE : _FALSE;
+		break;
+
+	case BTC_GET_BL_WIFI_ROAM:
+		*pu8 = (rtw_mi_check_status(padapter, MI_STA_LINKING)) ? _TRUE : _FALSE;
+		break;
+
+	case BTC_GET_BL_WIFI_4_WAY_PROGRESS:
+		*pu8 = _FALSE;
+		break;
+
+	case BTC_GET_BL_WIFI_UNDER_5G:
+		*pu8 = (pHalData->current_band_type == BAND_ON_5G) ? _TRUE : _FALSE;
+		break;
+
+	case BTC_GET_BL_WIFI_AP_MODE_ENABLE:
+		*pu8 = (rtw_mi_check_status(padapter, MI_AP_MODE)) ? _TRUE : _FALSE;
+		break;
+
+	case BTC_GET_BL_WIFI_ENABLE_ENCRYPTION:
+		*pu8 = padapter->securitypriv.dot11PrivacyAlgrthm == 0 ? _FALSE : _TRUE;
+		break;
+
+	case BTC_GET_BL_WIFI_UNDER_B_MODE:
+		if (mlmeext->cur_wireless_mode == WIRELESS_11B)
+			*pu8 = _TRUE;
+		else
+			*pu8 = _FALSE;
+		break;
+
+	case BTC_GET_BL_WIFI_IS_IN_MP_MODE:
+		if (padapter->registrypriv.mp_mode == 0)
+			*pu8 = _FALSE;
+		else
+			*pu8 = _TRUE;
+		break;
+
+	case BTC_GET_BL_EXT_SWITCH:
+		*pu8 = _FALSE;
+		break;
+	case BTC_GET_BL_IS_ASUS_8723B:
+		/* Always return FALSE in linux driver since this case is added only for windows driver */
+		*pu8 = _FALSE;
+		break;
+
+	case BTC_GET_BL_RF4CE_CONNECTED:
+#ifdef CONFIG_RF4CE_COEXIST
+		if (hal_btcoex_get_rf4ce_link_state() == 0)
+			*pu8 = FALSE;
+		else
+			*pu8 = TRUE;
+#else
+		*pu8 = FALSE;
+#endif
+		break;
+
+	case BTC_GET_BL_WIFI_LW_PWR_STATE:
+		/* return false due to coex do not run during 32K */
+		*pu8 = FALSE;
+		break;
+
+	case BTC_GET_S4_WIFI_RSSI:
+		*pS4Tmp = halbtcoutsrc_GetWifiRssi(padapter);
+		break;
+
+	case BTC_GET_S4_HS_RSSI:
+		*pS4Tmp = 0;
+		ret = _FALSE;
+		break;
+
+	case BTC_GET_U4_WIFI_BW:
+		if (IsLegacyOnly(mlmeext->cur_wireless_mode))
+			*pU4Tmp = BTC_WIFI_BW_LEGACY;
+		else {
+			switch (pHalData->current_channel_bw) {
+			case CHANNEL_WIDTH_20:
+				*pU4Tmp = BTC_WIFI_BW_HT20;
+				break;
+			case CHANNEL_WIDTH_40:
+				*pU4Tmp = BTC_WIFI_BW_HT40;
+				break;
+			case CHANNEL_WIDTH_80:
+				*pU4Tmp = BTC_WIFI_BW_HT80;
+				break;
+			case CHANNEL_WIDTH_160:
+				*pU4Tmp = BTC_WIFI_BW_HT160;
+				break;
+			default:
+				RTW_INFO("[BTCOEX] unknown bandwidth(%d)\n", pHalData->current_channel_bw);
+				*pU4Tmp = BTC_WIFI_BW_HT40;
+				break;
+			}
+
+		}
+		break;
+
+	case BTC_GET_U4_WIFI_TRAFFIC_DIRECTION: {
+		PRT_LINK_DETECT_T plinkinfo;
+		plinkinfo = &padapter->mlmepriv.LinkDetectInfo;
+
+		if (plinkinfo->NumTxOkInPeriod > plinkinfo->NumRxOkInPeriod)
+			*pU4Tmp = BTC_WIFI_TRAFFIC_TX;
+		else
+			*pU4Tmp = BTC_WIFI_TRAFFIC_RX;
+	}
+		break;
+
+	case BTC_GET_U4_WIFI_FW_VER:
+		*pU4Tmp = pHalData->firmware_version << 16;
+		*pU4Tmp |= pHalData->firmware_sub_version;
+		break;
+
+	case BTC_GET_U4_WIFI_LINK_STATUS:
+		*pU4Tmp = halbtcoutsrc_GetWifiLinkStatus(pBtCoexist);
+		break;
+	case BTC_GET_BL_WIFI_LINK_INFO:
+		*wifi_link_info = halbtcoutsrc_getwifilinkinfo(pBtCoexist);
+		break;
+	case BTC_GET_U4_BT_PATCH_VER:
+		*pU4Tmp = halbtcoutsrc_GetBtPatchVer(pBtCoexist);
+		break;
+
+	case BTC_GET_U4_VENDOR:
+		*pU4Tmp = BTC_VENDOR_OTHER;
+		break;
+
+	case BTC_GET_U4_SUPPORTED_VERSION:
+		*pU4Tmp = halbtcoutsrc_GetBtCoexSupportedVersion(pBtCoexist);
+		break;
+	case BTC_GET_U4_SUPPORTED_FEATURE:
+		*pU4Tmp = halbtcoutsrc_GetBtCoexSupportedFeature(pBtCoexist);
+		break;
+
+	case BTC_GET_U4_BT_DEVICE_INFO:
+		*pU4Tmp = halbtcoutsrc_GetBtDeviceInfo(pBtCoexist);
+		break;
+
+	case BTC_GET_U4_BT_FORBIDDEN_SLOT_VAL:
+		*pU4Tmp = halbtcoutsrc_GetBtForbiddenSlotVal(pBtCoexist);
+		break;
+
+	case BTC_GET_U4_WIFI_IQK_TOTAL:
+		*pU4Tmp = pHalData->odmpriv.n_iqk_cnt;
+		break;
+
+	case BTC_GET_U4_WIFI_IQK_OK:
+		*pU4Tmp = pHalData->odmpriv.n_iqk_ok_cnt;
+		break;
+
+	case BTC_GET_U4_WIFI_IQK_FAIL:
+		*pU4Tmp = pHalData->odmpriv.n_iqk_fail_cnt;
+		break;
+
+	case BTC_GET_U1_WIFI_DOT11_CHNL:
+		*pU1Tmp = padapter->mlmeextpriv.cur_channel;
+		break;
+
+	case BTC_GET_U1_WIFI_CENTRAL_CHNL:
+		*pU1Tmp = pHalData->current_channel;
+		break;
+
+	case BTC_GET_U1_WIFI_HS_CHNL:
+		*pU1Tmp = 0;
+		ret = _FALSE;
+		break;
+
+	case BTC_GET_U1_WIFI_P2P_CHNL:
+#ifdef CONFIG_P2P
+		{
+			struct wifidirect_info *pwdinfo = &(padapter->wdinfo);
+			
+			*pU1Tmp = pwdinfo->operating_channel;
+		}
+#else
+		*pU1Tmp = 0;
+#endif
+		break;
+
+	case BTC_GET_U1_MAC_PHY_MODE:
+		/*			*pU1Tmp = BTC_SMSP;
+		 *			*pU1Tmp = BTC_DMSP;
+		 *			*pU1Tmp = BTC_DMDP;
+		 *			*pU1Tmp = BTC_MP_UNKNOWN; */
+		break;
+
+	case BTC_GET_U1_AP_NUM:
+		*pU1Tmp = halbtcoutsrc_GetWifiScanAPNum(padapter);
+		break;
+	case BTC_GET_U1_ANT_TYPE:
+		switch (pHalData->bt_coexist.btAntisolation) {
+		case 0:
+			*pU1Tmp = (u1Byte)BTC_ANT_TYPE_0;
+			pBtCoexist->board_info.ant_type = (u1Byte)BTC_ANT_TYPE_0;
+			break;
+		case 1:
+			*pU1Tmp = (u1Byte)BTC_ANT_TYPE_1;
+			pBtCoexist->board_info.ant_type = (u1Byte)BTC_ANT_TYPE_1;
+			break;
+		case 2:
+			*pU1Tmp = (u1Byte)BTC_ANT_TYPE_2;
+			pBtCoexist->board_info.ant_type = (u1Byte)BTC_ANT_TYPE_2;
+			break;
+		case 3:
+			*pU1Tmp = (u1Byte)BTC_ANT_TYPE_3;
+			pBtCoexist->board_info.ant_type = (u1Byte)BTC_ANT_TYPE_3;
+			break;
+		case 4:
+			*pU1Tmp = (u1Byte)BTC_ANT_TYPE_4;
+			pBtCoexist->board_info.ant_type = (u1Byte)BTC_ANT_TYPE_4;
+			break;
+		}
+		break;
+	case BTC_GET_U1_IOT_PEER:
+		*pU1Tmp = mlmeext->mlmext_info.assoc_AP_vendor;
+		break;
+
+	/* =======1Ant=========== */
+	case BTC_GET_U1_LPS_MODE:
+		*pU1Tmp = padapter->dvobj->pwrctl_priv.pwr_mode;
+		break;
+
+	case BTC_GET_U2_BEACON_PERIOD:
+		*pU2Tmp = mlmeext->mlmext_info.bcn_interval;
+		break;
+
+	default:
+		ret = _FALSE;
+		break;
+	}
+
+	return ret;
+}
+
+u16 halbtcoutsrc_LnaConstrainLvl(void *pBtcContext, u8 *lna_constrain_level)
+{
+	PBTC_COEXIST pBtCoexist;
+	u16 ret = BT_STATUS_BT_OP_SUCCESS;
+
+	pBtCoexist = (PBTC_COEXIST)pBtcContext;
+
+	if (halbtcoutsrc_IsHwMailboxExist(pBtCoexist) == _TRUE) {
+		_irqL irqL;
+		u8 op_code;
+
+		_enter_critical_mutex(&GLBtcBtMpOperLock, &irqL);
+
+		ret = _btmpoper_cmd(pBtCoexist, BT_OP_SET_BT_LANCONSTRAIN_LEVEL, 0, lna_constrain_level, 1);
+
+		_exit_critical_mutex(&GLBtcBtMpOperLock, &irqL);
+	} else { 
+		ret = BT_STATUS_NOT_IMPLEMENT;
+		RTW_INFO("%s halbtcoutsrc_IsHwMailboxExist(pBtCoexist) == FALSE\n", __func__);
+	}
+
+	return ret;
+}
+
+u8 halbtcoutsrc_Set(void *pBtcContext, u8 setType, void *pInBuf)
+{
+	PBTC_COEXIST pBtCoexist;
+	PADAPTER padapter;
+	PHAL_DATA_TYPE pHalData;
+	u8 *pu8;
+	u8 *pU1Tmp;
+	u32	*pU4Tmp;
+	u8 ret;
+	u8 result = _TRUE;
+
+
+	pBtCoexist = (PBTC_COEXIST)pBtcContext;
+	padapter = pBtCoexist->Adapter;
+	pHalData = GET_HAL_DATA(padapter);
+	pu8 = (u8 *)pInBuf;
+	pU1Tmp = (u8 *)pInBuf;
+	pU4Tmp = (u32 *)pInBuf;
+	ret = _TRUE;
+
+	if (!halbtcoutsrc_IsBtCoexistAvailable(pBtCoexist))
+		return _FALSE;
+
+	switch (setType) {
+	/* set some u8 type variables. */
+	case BTC_SET_BL_BT_DISABLE:
+		pBtCoexist->bt_info.bt_disabled = *pu8;
+		break;
+
+	case BTC_SET_BL_BT_ENABLE_DISABLE_CHANGE:
+		pBtCoexist->bt_info.bt_enable_disable_change = *pu8;
+		break;
+
+	case BTC_SET_BL_BT_TRAFFIC_BUSY:
+		pBtCoexist->bt_info.bt_busy = *pu8;
+		break;
+
+	case BTC_SET_BL_BT_LIMITED_DIG:
+		pBtCoexist->bt_info.limited_dig = *pu8;
+		break;
+
+	case BTC_SET_BL_FORCE_TO_ROAM:
+		pBtCoexist->bt_info.force_to_roam = *pu8;
+		break;
+
+	case BTC_SET_BL_TO_REJ_AP_AGG_PKT:
+		pBtCoexist->bt_info.reject_agg_pkt = *pu8;
+		break;
+
+	case BTC_SET_BL_BT_CTRL_AGG_SIZE:
+		pBtCoexist->bt_info.bt_ctrl_agg_buf_size = *pu8;
+		break;
+
+	case BTC_SET_BL_INC_SCAN_DEV_NUM:
+		pBtCoexist->bt_info.increase_scan_dev_num = *pu8;
+		break;
+
+	case BTC_SET_BL_BT_TX_RX_MASK:
+		pBtCoexist->bt_info.bt_tx_rx_mask = *pu8;
+		break;
+
+	case BTC_SET_BL_MIRACAST_PLUS_BT:
+		pBtCoexist->bt_info.miracast_plus_bt = *pu8;
+		break;
+
+	/* set some u8 type variables. */
+	case BTC_SET_U1_RSSI_ADJ_VAL_FOR_AGC_TABLE_ON:
+		pBtCoexist->bt_info.rssi_adjust_for_agc_table_on = *pU1Tmp;
+		break;
+
+	case BTC_SET_U1_AGG_BUF_SIZE:
+		pBtCoexist->bt_info.agg_buf_size = *pU1Tmp;
+		break;
+
+	/* the following are some action which will be triggered */
+	case BTC_SET_ACT_GET_BT_RSSI:
+#if 0
+		BT_SendGetBtRssiEvent(padapter);
+#else
+		ret = _FALSE;
+#endif
+		break;
+
+	case BTC_SET_ACT_AGGREGATE_CTRL:
+		halbtcoutsrc_AggregationCheck(pBtCoexist);
+		break;
+
+	/* =======1Ant=========== */
+	/* set some u8 type variables. */
+	case BTC_SET_U1_RSSI_ADJ_VAL_FOR_1ANT_COEX_TYPE:
+		pBtCoexist->bt_info.rssi_adjust_for_1ant_coex_type = *pU1Tmp;
+		break;
+
+	case BTC_SET_U1_LPS_VAL:
+		pBtCoexist->bt_info.lps_val = *pU1Tmp;
+		break;
+
+	case BTC_SET_U1_RPWM_VAL:
+		pBtCoexist->bt_info.rpwm_val = *pU1Tmp;
+		break;
+
+	/* the following are some action which will be triggered */
+	case BTC_SET_ACT_LEAVE_LPS:
+		result = halbtcoutsrc_LeaveLps(pBtCoexist);
+		break;
+
+	case BTC_SET_ACT_ENTER_LPS:
+		halbtcoutsrc_EnterLps(pBtCoexist);
+		break;
+
+	case BTC_SET_ACT_NORMAL_LPS:
+		halbtcoutsrc_NormalLps(pBtCoexist);
+		break;
+
+	case BTC_SET_ACT_PRE_NORMAL_LPS:
+		halbtcoutsrc_Pre_NormalLps(pBtCoexist);
+		break;
+
+	case BTC_SET_ACT_POST_NORMAL_LPS:
+		halbtcoutsrc_Post_NormalLps(pBtCoexist);
+		break;
+
+	case BTC_SET_ACT_DISABLE_LOW_POWER:
+		halbtcoutsrc_DisableLowPower(pBtCoexist, *pu8);
+		break;
+
+	case BTC_SET_ACT_UPDATE_RAMASK:
+		/*
+		pBtCoexist->bt_info.ra_mask = *pU4Tmp;
+
+		if (check_fwstate(&padapter->mlmepriv, WIFI_ASOC_STATE) == _TRUE) {
+			struct sta_info *psta;
+			PWLAN_BSSID_EX cur_network;
+
+			cur_network = &padapter->mlmeextpriv.mlmext_info.network;
+			psta = rtw_get_stainfo(&padapter->stapriv, cur_network->MacAddress);
+			rtw_hal_update_ra_mask(psta);
+		}
+		*/
+		break;
+
+	case BTC_SET_ACT_SEND_MIMO_PS: {
+		u8 newMimoPsMode = 3;
+		struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv);
+		struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
+
+		/* *pU1Tmp = 0 use SM_PS static type */
+		/* *pU1Tmp = 1 disable SM_PS */
+		if (*pU1Tmp == 0)
+			newMimoPsMode = WLAN_HT_CAP_SM_PS_STATIC;
+		else if (*pU1Tmp == 1)
+			newMimoPsMode = WLAN_HT_CAP_SM_PS_DISABLED;
+
+		if (check_fwstate(&padapter->mlmepriv , WIFI_ASOC_STATE) == _TRUE) {
+			/* issue_action_SM_PS(padapter, get_my_bssid(&(pmlmeinfo->network)), newMimoPsMode); */
+			issue_action_SM_PS_wait_ack(padapter , get_my_bssid(&(pmlmeinfo->network)) , newMimoPsMode, 3 , 1);
+		}
+	}
+	break;
+
+	case BTC_SET_ACT_CTRL_BT_INFO:
+#ifdef CONFIG_BT_COEXIST_SOCKET_TRX
+		{
+			u8 dataLen = *pU1Tmp;
+			u8 tmpBuf[BTC_TMP_BUF_SHORT];
+			if (dataLen)
+				_rtw_memcpy(tmpBuf, pU1Tmp + 1, dataLen);
+			BT_SendEventExtBtInfoControl(padapter, dataLen, &tmpBuf[0]);
+		}
+#else /* !CONFIG_BT_COEXIST_SOCKET_TRX */
+		ret = _FALSE;
+#endif /* CONFIG_BT_COEXIST_SOCKET_TRX */
+		break;
+
+	case BTC_SET_ACT_CTRL_BT_COEX:
+#ifdef CONFIG_BT_COEXIST_SOCKET_TRX
+		{
+			u8 dataLen = *pU1Tmp;
+			u8 tmpBuf[BTC_TMP_BUF_SHORT];
+			if (dataLen)
+				_rtw_memcpy(tmpBuf, pU1Tmp + 1, dataLen);
+			BT_SendEventExtBtCoexControl(padapter, _FALSE, dataLen, &tmpBuf[0]);
+		}
+#else /* !CONFIG_BT_COEXIST_SOCKET_TRX */
+		ret = _FALSE;
+#endif /* CONFIG_BT_COEXIST_SOCKET_TRX */
+		break;
+	case BTC_SET_ACT_CTRL_8723B_ANT:
+#if 0
+		{
+			u1Byte	dataLen = *pU1Tmp;
+			u1Byte	tmpBuf[BTC_TMP_BUF_SHORT];
+			if (dataLen)
+				PlatformMoveMemory(&tmpBuf[0], pU1Tmp + 1, dataLen);
+			BT_Set8723bAnt(Adapter, dataLen, &tmpBuf[0]);
+		}
+#else
+		ret = _FALSE;
+#endif
+		break;
+	case BTC_SET_BL_BT_LNA_CONSTRAIN_LEVEL:
+		halbtcoutsrc_LnaConstrainLvl(pBtCoexist, pu8);
+		break;
+	/* ===================== */
+	default:
+		ret = _FALSE;
+		break;
+	}
+
+	return result;
+}
+
+u8 halbtcoutsrc_UnderIps(PBTC_COEXIST pBtCoexist)
+{
+	PADAPTER padapter;
+	struct pwrctrl_priv *pwrpriv;
+	u8 bMacPwrCtrlOn;
+
+	padapter = pBtCoexist->Adapter;
+	pwrpriv = &padapter->dvobj->pwrctl_priv;
+	bMacPwrCtrlOn = _FALSE;
+
+	if ((_TRUE == pwrpriv->bips_processing)
+	    && (IPS_NONE != pwrpriv->ips_mode_req)
+	   )
+		return _TRUE;
+
+	if (rf_off == pwrpriv->rf_pwrstate)
+		return _TRUE;
+
+	rtw_hal_get_hwreg(padapter, HW_VAR_APFM_ON_MAC, &bMacPwrCtrlOn);
+	if (_FALSE == bMacPwrCtrlOn)
+		return _TRUE;
+
+	return _FALSE;
+}
+
+u8 halbtcoutsrc_UnderLps(PBTC_COEXIST pBtCoexist)
+{
+	return GLBtcWiFiInLPS;
+}
+
+u8 halbtcoutsrc_Under32K(PBTC_COEXIST pBtCoexist)
+{
+	/* todo: the method to check whether wifi is under 32K or not */
+	return _FALSE;
+}
+
+void halbtcoutsrc_DisplayCoexStatistics(PBTC_COEXIST pBtCoexist)
+{
+#if 0
+	PADAPTER padapter = (PADAPTER)pBtCoexist->Adapter;
+	PBT_MGNT pBtMgnt = &padapter->MgntInfo.BtInfo.BtMgnt;
+	PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter);
+	u8 *cliBuf = pBtCoexist->cliBuf;
+	u1Byte			i, j;
+	u1Byte			tmpbuf[BTC_TMP_BUF_SHORT];
+
+
+	if (gl_coex_offload.cnt_h2c_sent) {
+		CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s", "============[Coex h2c notify]============");
+		CL_PRINTF(cliBuf);
+
+		CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = H2c(%d)/Ack(%d)", "Coex h2c/c2h overall statistics",
+			gl_coex_offload.cnt_h2c_sent, gl_coex_offload.cnt_c2h_ack);
+		for (j = 0; j < COL_STATUS_MAX; j++) {
+			if (gl_coex_offload.status[j]) {
+				CL_SPRINTF(tmpbuf, BTC_TMP_BUF_SHORT, ", %s:%d", coexH2cResultString[j], gl_coex_offload.status[j]);
+				CL_STRNCAT(cliBuf, BT_TMP_BUF_SIZE, tmpbuf, BTC_TMP_BUF_SHORT);
+			}
+		}
+		CL_PRINTF(cliBuf);
+	}
+	for (i = 0; i < COL_OP_WIFI_OPCODE_MAX; i++) {
+		if (gl_coex_offload.h2c_record[i].count) {
+			/*==========================================*/
+			/*	H2C result statistics*/
+			/*==========================================*/
+			CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = total:%d", coexOpcodeString[i], gl_coex_offload.h2c_record[i].count);
+			for (j = 0; j < COL_STATUS_MAX; j++) {
+				if (gl_coex_offload.h2c_record[i].status[j]) {
+					CL_SPRINTF(tmpbuf, BTC_TMP_BUF_SHORT, ", %s:%d", coexH2cResultString[j], gl_coex_offload.h2c_record[i].status[j]);
+					CL_STRNCAT(cliBuf, BT_TMP_BUF_SIZE, tmpbuf, BTC_TMP_BUF_SHORT);
+				}
+			}
+			CL_PRINTF(cliBuf);
+			/*==========================================*/
+			/*	H2C/C2H content*/
+			/*==========================================*/
+			CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = ", "H2C / C2H content");
+			for (j = 0; j < gl_coex_offload.h2c_record[i].h2c_len; j++) {
+				CL_SPRINTF(tmpbuf, BTC_TMP_BUF_SHORT, "%02x ", gl_coex_offload.h2c_record[i].h2c_buf[j]);
+				CL_STRNCAT(cliBuf, BT_TMP_BUF_SIZE, tmpbuf, 3);
+			}
+			if (gl_coex_offload.h2c_record[i].c2h_ack_len) {
+				CL_STRNCAT(cliBuf, BT_TMP_BUF_SIZE, "/ ", 2);
+				for (j = 0; j < gl_coex_offload.h2c_record[i].c2h_ack_len; j++) {
+					CL_SPRINTF(tmpbuf, BTC_TMP_BUF_SHORT, "%02x ", gl_coex_offload.h2c_record[i].c2h_ack_buf[j]);
+					CL_STRNCAT(cliBuf, BT_TMP_BUF_SIZE, tmpbuf, 3);
+				}
+			}
+			CL_PRINTF(cliBuf);
+			/*==========================================*/
+		}
+	}
+
+	if (gl_coex_offload.cnt_c2h_ind) {
+		CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s", "============[Coex c2h indication]============");
+		CL_PRINTF(cliBuf);
+
+		CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = Ind(%d)", "C2H indication statistics",
+			   gl_coex_offload.cnt_c2h_ind);
+		for (j = 0; j < COL_STATUS_MAX; j++) {
+			if (gl_coex_offload.c2h_ind_status[j]) {
+				CL_SPRINTF(tmpbuf, BTC_TMP_BUF_SHORT, ", %s:%d", coexH2cResultString[j], gl_coex_offload.c2h_ind_status[j]);
+				CL_STRNCAT(cliBuf, BT_TMP_BUF_SIZE, tmpbuf, BTC_TMP_BUF_SHORT);
+			}
+		}
+		CL_PRINTF(cliBuf);
+	}
+	for (i = 0; i < COL_IND_MAX; i++) {
+		if (gl_coex_offload.c2h_ind_record[i].count) {
+			/*==========================================*/
+			/*	H2C result statistics*/
+			/*==========================================*/
+			CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = total:%d", coexIndTypeString[i], gl_coex_offload.c2h_ind_record[i].count);
+			for (j = 0; j < COL_STATUS_MAX; j++) {
+				if (gl_coex_offload.c2h_ind_record[i].status[j]) {
+					CL_SPRINTF(tmpbuf, BTC_TMP_BUF_SHORT, ", %s:%d", coexH2cResultString[j], gl_coex_offload.c2h_ind_record[i].status[j]);
+					CL_STRNCAT(cliBuf, BT_TMP_BUF_SIZE, tmpbuf, BTC_TMP_BUF_SHORT);
+				}
+			}
+			CL_PRINTF(cliBuf);
+			/*==========================================*/
+			/*	content*/
+			/*==========================================*/
+			CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = ", "C2H indication content");
+			for (j = 0; j < gl_coex_offload.c2h_ind_record[i].ind_len; j++) {
+				CL_SPRINTF(tmpbuf, BTC_TMP_BUF_SHORT, "%02x ", gl_coex_offload.c2h_ind_record[i].ind_buf[j]);
+				CL_STRNCAT(cliBuf, BT_TMP_BUF_SIZE, tmpbuf, 3);
+			}
+			CL_PRINTF(cliBuf);
+			/*==========================================*/
+		}
+	}
+
+	CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s", "============[Statistics]============");
+	CL_PRINTF(cliBuf);
+
+#if (H2C_USE_IO_THREAD != 1)
+	for (i = 0; i < H2C_STATUS_MAX; i++) {
+		if (pHalData->h2cStatistics[i]) {
+			CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = [%s] = %d", "H2C statistics", \
+				   h2cStaString[i], pHalData->h2cStatistics[i]);
+			CL_PRINTF(cliBuf);
+		}
+	}
+#else
+	for (i = 0; i < IO_STATUS_MAX; i++) {
+		if (Adapter->ioComStr.ioH2cStatistics[i]) {
+			CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = [%s] = %d", "H2C statistics", \
+				ioStaString[i], Adapter->ioComStr.ioH2cStatistics[i]);
+			CL_PRINTF(cliBuf);
+		}
+	}
+#endif
+#if 0
+	CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x", "lastHMEBoxNum", \
+		   pHalData->LastHMEBoxNum);
+	CL_PRINTF(cliBuf);
+	CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x / 0x%x", "LastOkH2c/FirstFailH2c(fwNotRead)", \
+		   pHalData->lastSuccessH2cEid, pHalData->firstFailedH2cEid);
+	CL_PRINTF(cliBuf);
+
+	CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d/ %d/ %d", "c2hIsr/c2hIntr/clr1AF/noRdy/noBuf", \
+		pHalData->InterruptLog.nIMR_C2HCMD, DBG_Var.c2hInterruptCnt, DBG_Var.c2hClrReadC2hCnt,
+		   DBG_Var.c2hNotReadyCnt, DBG_Var.c2hBufAlloFailCnt);
+	CL_PRINTF(cliBuf);
+
+	CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d", "c2hPacket", \
+		   DBG_Var.c2hPacketCnt);
+	CL_PRINTF(cliBuf);
+#endif
+	CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d", "Periodical/ DbgCtrl", \
+		pBtCoexist->statistics.cntPeriodical, pBtCoexist->statistics.cntDbgCtrl);
+	CL_PRINTF(cliBuf);
+	CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d/ %d", "PowerOn/InitHw/InitCoexDm/RfStatus", \
+		pBtCoexist->statistics.cntPowerOn, pBtCoexist->statistics.cntInitHwConfig, pBtCoexist->statistics.cntInitCoexDm,
+		   pBtCoexist->statistics.cntRfStatusNotify);
+	CL_PRINTF(cliBuf);
+	CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d/ %d/ %d", "Ips/Lps/Scan/Connect/Mstatus", \
+		pBtCoexist->statistics.cntIpsNotify, pBtCoexist->statistics.cntLpsNotify,
+		pBtCoexist->statistics.cntScanNotify, pBtCoexist->statistics.cntConnectNotify,
+		   pBtCoexist->statistics.cntMediaStatusNotify);
+	CL_PRINTF(cliBuf);
+	CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d", "Special pkt/Bt info/ bind",
+		pBtCoexist->statistics.cntSpecialPacketNotify, pBtCoexist->statistics.cntBtInfoNotify,
+		   pBtCoexist->statistics.cntBind);
+	CL_PRINTF(cliBuf);
+#endif
+	PADAPTER		padapter = pBtCoexist->Adapter;
+	PHAL_DATA_TYPE	pHalData = GET_HAL_DATA(padapter);
+	u8				*cliBuf = pBtCoexist->cli_buf;
+
+	if (pHalData->EEPROMBluetoothCoexist == 1) {
+		CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s", "============[Coex Status]============");
+		CL_PRINTF(cliBuf);
+		CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d ", "IsBtDisabled", rtw_btcoex_IsBtDisabled(padapter));
+		CL_PRINTF(cliBuf);
+		CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d ", "IsBtControlLps", rtw_btcoex_IsBtControlLps(padapter));
+		CL_PRINTF(cliBuf);
+	}
+}
+
+void halbtcoutsrc_DisplayBtLinkInfo(PBTC_COEXIST pBtCoexist)
+{
+#if 0
+	PADAPTER padapter = (PADAPTER)pBtCoexist->Adapter;
+	PBT_MGNT pBtMgnt = &padapter->MgntInfo.BtInfo.BtMgnt;
+	u8 *cliBuf = pBtCoexist->cliBuf;
+	u8 i;
+
+
+	if (pBtCoexist->stack_info.profile_notified) {
+		for (i = 0; i < pBtMgnt->ExtConfig.NumberOfACL; i++) {
+			if (pBtMgnt->ExtConfig.HCIExtensionVer >= 1) {
+				CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s/ %s/ %s", "Bt link type/spec/role", \
+					BtProfileString[pBtMgnt->ExtConfig.aclLink[i].BTProfile],
+					BtSpecString[pBtMgnt->ExtConfig.aclLink[i].BTCoreSpec],
+					BtLinkRoleString[pBtMgnt->ExtConfig.aclLink[i].linkRole]);
+				CL_PRINTF(cliBuf);
+			} else {
+				CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s/ %s", "Bt link type/spec", \
+					BtProfileString[pBtMgnt->ExtConfig.aclLink[i].BTProfile],
+					BtSpecString[pBtMgnt->ExtConfig.aclLink[i].BTCoreSpec]);
+				CL_PRINTF(cliBuf);
+			}
+		}
+	}
+#endif
+}
+
+void halbtcoutsrc_DisplayWifiStatus(PBTC_COEXIST pBtCoexist)
+{
+	PADAPTER	padapter = pBtCoexist->Adapter;
+	struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter);
+	u8			*cliBuf = pBtCoexist->cli_buf;
+	s32			wifiRssi = 0, btHsRssi = 0;
+	BOOLEAN	bScan = _FALSE, bLink = _FALSE, bRoam = _FALSE, bWifiBusy = _FALSE, bWifiUnderBMode = _FALSE;
+	u32			wifiBw = BTC_WIFI_BW_HT20, wifiTrafficDir = BTC_WIFI_TRAFFIC_TX, wifiFreq = BTC_FREQ_2_4G;
+	u32			wifiLinkStatus = 0x0;
+	BOOLEAN	bBtHsOn = _FALSE, bLowPower = _FALSE;
+	u8			wifiChnl = 0, wifiP2PChnl = 0, nScanAPNum = 0, FwPSState;
+	u32			iqk_cnt_total = 0, iqk_cnt_ok = 0, iqk_cnt_fail = 0;
+	u16			wifiBcnInterval = 0;
+	PHAL_DATA_TYPE hal = GET_HAL_DATA(padapter);
+	struct btc_wifi_link_info wifi_link_info;
+
+	wifi_link_info = halbtcoutsrc_getwifilinkinfo(pBtCoexist);
+
+	switch (wifi_link_info.link_mode) {
+		case BTC_LINK_NONE:
+			CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s/ %d/ %d/ %d", "WifiLinkMode/HotSpa/Noa/ClientJoin",
+					"None", wifi_link_info.bhotspot, wifi_link_info.benable_noa, wifi_link_info.bany_client_join_go);
+			wifiFreq = hal->current_channel > 14 ?  BTC_FREQ_5G : BTC_FREQ_2_4G;
+			break;
+		case BTC_LINK_ONLY_GO:
+			CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s/ %d/ %d/ %d", "WifiLinkMode/HotSpa/Noa/ClientJoin",
+					"ONLY_GO", wifi_link_info.bhotspot, wifi_link_info.benable_noa, wifi_link_info.bany_client_join_go);
+			wifiFreq = hal->current_channel > 14 ?  BTC_FREQ_5G : BTC_FREQ_2_4G;
+			break;
+		case BTC_LINK_ONLY_GC:
+			CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s/ %d/ %d/ %d", "WifiLinkMode/HotSpa/Noa/ClientJoin",
+					"ONLY_GC", wifi_link_info.bhotspot, wifi_link_info.benable_noa, wifi_link_info.bany_client_join_go);
+			wifiFreq = hal->current_channel > 14 ?  BTC_FREQ_5G : BTC_FREQ_2_4G;
+			break;
+		case BTC_LINK_ONLY_STA:
+			CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s/ %d/ %d/ %d", "WifiLinkMode/HotSpa/Noa/ClientJoin",
+					"ONLY_STA", wifi_link_info.bhotspot, wifi_link_info.benable_noa, wifi_link_info.bany_client_join_go);
+			wifiFreq = hal->current_channel > 14 ?  BTC_FREQ_5G : BTC_FREQ_2_4G;
+			break;
+		case BTC_LINK_ONLY_AP:
+			CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s/ %d/ %d/ %d", "WifiLinkMode/HotSpa/Noa/ClientJoin",
+					"ONLY_AP", wifi_link_info.bhotspot, wifi_link_info.benable_noa, wifi_link_info.bany_client_join_go);
+			wifiFreq = hal->current_channel > 14 ?  BTC_FREQ_5G : BTC_FREQ_2_4G;
+			break;
+		case BTC_LINK_2G_MCC_GO_STA:
+			CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s/ %d/ %d/ %d", "WifiLinkMode/HotSpa/Noa/ClientJoin",
+					"24G_MCC_GO_STA", wifi_link_info.bhotspot, wifi_link_info.benable_noa, wifi_link_info.bany_client_join_go);
+			wifiFreq = BTC_FREQ_2_4G;
+			break;
+		case BTC_LINK_5G_MCC_GO_STA:
+			CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s/ %d/ %d/ %d", "WifiLinkMode/HotSpa/Noa/ClientJoin",
+					"5G_MCC_GO_STA", wifi_link_info.bhotspot, wifi_link_info.benable_noa, wifi_link_info.bany_client_join_go);
+			wifiFreq = BTC_FREQ_5G;
+			break;
+		case BTC_LINK_25G_MCC_GO_STA:
+			CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s/ %d/ %d/ %d", "WifiLinkMode/HotSpa/Noa/ClientJoin",
+					"2BANDS_MCC_GO_STA", wifi_link_info.bhotspot, wifi_link_info.benable_noa, wifi_link_info.bany_client_join_go);
+			wifiFreq = BTC_FREQ_25G;
+			break;
+		case BTC_LINK_2G_MCC_GC_STA:
+			CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s/ %d/ %d/ %d", "WifiLinkMode/HotSpa/Noa/ClientJoin",
+					"24G_MCC_GC_STA", wifi_link_info.bhotspot, wifi_link_info.benable_noa, wifi_link_info.bany_client_join_go);
+			wifiFreq = BTC_FREQ_2_4G;
+			break;
+		case BTC_LINK_5G_MCC_GC_STA:
+			CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s/ %d/ %d/ %d", "WifiLinkMode/HotSpa/Noa/ClientJoin",
+					"5G_MCC_GC_STA", wifi_link_info.bhotspot, wifi_link_info.benable_noa, wifi_link_info.bany_client_join_go);
+			wifiFreq = BTC_FREQ_5G;
+			break;
+		case BTC_LINK_25G_MCC_GC_STA:
+			CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s/ %d/ %d/ %d", "WifiLinkMode/HotSpa/Noa/ClientJoin",
+					"2BANDS_MCC_GC_STA", wifi_link_info.bhotspot, wifi_link_info.benable_noa, wifi_link_info.bany_client_join_go);
+			wifiFreq = BTC_FREQ_25G;
+			break;
+		case BTC_LINK_2G_SCC_GO_STA:
+			CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s/ %d/ %d/ %d", "WifiLinkMode/HotSpa/Noa/ClientJoin",
+					"24G_SCC_GO_STA", wifi_link_info.bhotspot, wifi_link_info.benable_noa, wifi_link_info.bany_client_join_go);
+			wifiFreq = BTC_FREQ_2_4G;
+			break;
+		case BTC_LINK_5G_SCC_GO_STA:
+			CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s/ %d/ %d/ %d", "WifiLinkMode/HotSpa/Noa/ClientJoin",
+					"5G_SCC_GO_STA", wifi_link_info.bhotspot, wifi_link_info.benable_noa, wifi_link_info.bany_client_join_go);
+			wifiFreq = BTC_FREQ_5G;
+			break;
+		case BTC_LINK_2G_SCC_GC_STA:
+			CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s/ %d/ %d/ %d", "WifiLinkMode/HotSpa/Noa/ClientJoin",
+					"24G_SCC_GC_STA", wifi_link_info.bhotspot, wifi_link_info.benable_noa, wifi_link_info.bany_client_join_go);
+			wifiFreq = BTC_FREQ_2_4G;
+			break;
+		case BTC_LINK_5G_SCC_GC_STA:
+			CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s/ %d/ %d/ %d", "WifiLinkMode/HotSpa/Noa/ClientJoin",
+					"5G_SCC_GC_STA", wifi_link_info.bhotspot, wifi_link_info.benable_noa, wifi_link_info.bany_client_join_go);
+			wifiFreq = BTC_FREQ_5G;
+			break;
+		default:
+			CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s/ %d/ %d/ %d", "WifiLinkMode/HotSpa/Noa/ClientJoin",
+					"UNKNOWN", wifi_link_info.bhotspot, wifi_link_info.benable_noa, wifi_link_info.bany_client_join_go);
+			wifiFreq = hal->current_channel > 14 ?  BTC_FREQ_5G : BTC_FREQ_2_4G;
+			break;
+	}
+
+	CL_PRINTF(cliBuf);
+
+	wifiLinkStatus = halbtcoutsrc_GetWifiLinkStatus(pBtCoexist);
+	CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d/ %d/ %d", "STA/vWifi/HS/p2pGo/p2pGc",
+		((wifiLinkStatus & WIFI_STA_CONNECTED) ? 1 : 0), ((wifiLinkStatus & WIFI_AP_CONNECTED) ? 1 : 0),
+		((wifiLinkStatus & WIFI_HS_CONNECTED) ? 1 : 0), ((wifiLinkStatus & WIFI_P2P_GO_CONNECTED) ? 1 : 0),
+		((wifiLinkStatus & WIFI_P2P_GC_CONNECTED) ? 1 : 0));
+	CL_PRINTF(cliBuf);
+
+	pBtCoexist->btc_get(pBtCoexist, BTC_GET_BL_WIFI_SCAN, &bScan);
+	pBtCoexist->btc_get(pBtCoexist, BTC_GET_BL_WIFI_LINK, &bLink);
+	pBtCoexist->btc_get(pBtCoexist, BTC_GET_BL_WIFI_ROAM, &bRoam);
+	CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d ", "Link/ Roam/ Scan",
+		bLink, bRoam, bScan);
+	CL_PRINTF(cliBuf);	
+
+	pBtCoexist->btc_get(pBtCoexist, BTC_GET_U4_WIFI_IQK_TOTAL, &iqk_cnt_total);
+	pBtCoexist->btc_get(pBtCoexist, BTC_GET_U4_WIFI_IQK_OK, &iqk_cnt_ok);
+	pBtCoexist->btc_get(pBtCoexist, BTC_GET_U4_WIFI_IQK_FAIL, &iqk_cnt_fail);
+	CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d %s %s",
+		"IQK All/ OK/ Fail/AutoLoad/FWDL", iqk_cnt_total, iqk_cnt_ok, iqk_cnt_fail,
+		((halbtcoutsrc_is_autoload_fail(pBtCoexist) == _TRUE) ? "fail":"ok"), ((halbtcoutsrc_is_fw_ready(pBtCoexist) == _TRUE) ? "ok":"fail"));
+	CL_PRINTF(cliBuf);
+	
+	if (wifiLinkStatus & WIFI_STA_CONNECTED) {
+		CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s", "IOT Peer", GLBtcIotPeerString[padapter->mlmeextpriv.mlmext_info.assoc_AP_vendor]);
+		CL_PRINTF(cliBuf);
+	}
+
+	pBtCoexist->btc_get(pBtCoexist, BTC_GET_S4_WIFI_RSSI, &wifiRssi);
+	pBtCoexist->btc_get(pBtCoexist, BTC_GET_U2_BEACON_PERIOD, &wifiBcnInterval);
+	wifiChnl = wifi_link_info.sta_center_channel;
+	wifiP2PChnl = wifi_link_info.p2p_center_channel;
+
+	CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d dBm/ %d/ %d/ %d", "RSSI/ STA_Chnl/ P2P_Chnl/ BI",
+		wifiRssi-100, wifiChnl, wifiP2PChnl, wifiBcnInterval);
+	CL_PRINTF(cliBuf);
+
+	pBtCoexist->btc_get(pBtCoexist, BTC_GET_U4_WIFI_BW, &wifiBw);
+	pBtCoexist->btc_get(pBtCoexist, BTC_GET_BL_WIFI_BUSY, &bWifiBusy);
+	pBtCoexist->btc_get(pBtCoexist, BTC_GET_U4_WIFI_TRAFFIC_DIRECTION, &wifiTrafficDir);
+	pBtCoexist->btc_get(pBtCoexist, BTC_GET_BL_WIFI_UNDER_B_MODE, &bWifiUnderBMode);
+	pBtCoexist->btc_get(pBtCoexist, BTC_GET_U1_AP_NUM, &nScanAPNum);
+	CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s / %s/ %s/ %d ", "Band/ BW/ Traffic/ APCnt",
+		GLBtcWifiFreqString[wifiFreq], ((bWifiUnderBMode) ? "11b" : GLBtcWifiBwString[wifiBw]),
+		((!bWifiBusy) ? "idle" : ((BTC_WIFI_TRAFFIC_TX == wifiTrafficDir) ? "uplink" : "downlink")),
+		   nScanAPNum);
+	CL_PRINTF(cliBuf);
+
+	/* power status */
+	CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s%s%s", "Power Status", \
+		((halbtcoutsrc_UnderIps(pBtCoexist) == _TRUE) ? "IPS ON" : "IPS OFF"),
+		((halbtcoutsrc_UnderLps(pBtCoexist) == _TRUE) ? ", LPS ON" : ", LPS OFF"),
+		((halbtcoutsrc_Under32K(pBtCoexist) == _TRUE) ? ", 32k" : ""));
+	CL_PRINTF(cliBuf);
+
+	CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %02x %02x %02x %02x %02x %02x (0x%x/0x%x)", "Power mode cmd(lps/rpwm)",
+		   pBtCoexist->pwrModeVal[0], pBtCoexist->pwrModeVal[1],
+		   pBtCoexist->pwrModeVal[2], pBtCoexist->pwrModeVal[3],
+		   pBtCoexist->pwrModeVal[4], pBtCoexist->pwrModeVal[5],
+		   pBtCoexist->bt_info.lps_val,
+		   pBtCoexist->bt_info.rpwm_val);
+	CL_PRINTF(cliBuf);
+}
+
+void halbtcoutsrc_DisplayDbgMsg(void *pBtcContext, u8 dispType)
+{
+	PBTC_COEXIST pBtCoexist;
+
+
+	pBtCoexist = (PBTC_COEXIST)pBtcContext;
+	switch (dispType) {
+	case BTC_DBG_DISP_COEX_STATISTICS:
+		halbtcoutsrc_DisplayCoexStatistics(pBtCoexist);
+		break;
+	case BTC_DBG_DISP_BT_LINK_INFO:
+		halbtcoutsrc_DisplayBtLinkInfo(pBtCoexist);
+		break;
+	case BTC_DBG_DISP_WIFI_STATUS:
+		halbtcoutsrc_DisplayWifiStatus(pBtCoexist);
+		break;
+	default:
+		break;
+	}
+}
+
+/* ************************************
+ *		IO related function
+ * ************************************ */
+u8 halbtcoutsrc_Read1Byte(void *pBtcContext, u32 RegAddr)
+{
+	PBTC_COEXIST pBtCoexist;
+	PADAPTER padapter;
+
+
+	pBtCoexist = (PBTC_COEXIST)pBtcContext;
+	padapter = pBtCoexist->Adapter;
+
+	return rtw_read8(padapter, RegAddr);
+}
+
+u16 halbtcoutsrc_Read2Byte(void *pBtcContext, u32 RegAddr)
+{
+	PBTC_COEXIST pBtCoexist;
+	PADAPTER padapter;
+
+
+	pBtCoexist = (PBTC_COEXIST)pBtcContext;
+	padapter = pBtCoexist->Adapter;
+
+	return	rtw_read16(padapter, RegAddr);
+}
+
+u32 halbtcoutsrc_Read4Byte(void *pBtcContext, u32 RegAddr)
+{
+	PBTC_COEXIST pBtCoexist;
+	PADAPTER padapter;
+
+
+	pBtCoexist = (PBTC_COEXIST)pBtcContext;
+	padapter = pBtCoexist->Adapter;
+
+	return	rtw_read32(padapter, RegAddr);
+}
+
+void halbtcoutsrc_Write1Byte(void *pBtcContext, u32 RegAddr, u8 Data)
+{
+	PBTC_COEXIST pBtCoexist;
+	PADAPTER padapter;
+
+
+	pBtCoexist = (PBTC_COEXIST)pBtcContext;
+	padapter = pBtCoexist->Adapter;
+
+	rtw_write8(padapter, RegAddr, Data);
+}
+
+void halbtcoutsrc_BitMaskWrite1Byte(void *pBtcContext, u32 regAddr, u8 bitMask, u8 data1b)
+{
+	PBTC_COEXIST pBtCoexist;
+	PADAPTER padapter;
+	u8 originalValue, bitShift;
+	u8 i;
+
+
+	pBtCoexist = (PBTC_COEXIST)pBtcContext;
+	padapter = pBtCoexist->Adapter;
+	originalValue = 0;
+	bitShift = 0;
+
+	if (bitMask != 0xff) {
+		originalValue = rtw_read8(padapter, regAddr);
+
+		for (i = 0; i <= 7; i++) {
+			if ((bitMask >> i) & 0x1)
+				break;
+		}
+		bitShift = i;
+
+		data1b = (originalValue & ~bitMask) | ((data1b << bitShift) & bitMask);
+	}
+
+	rtw_write8(padapter, regAddr, data1b);
+}
+
+void halbtcoutsrc_Write2Byte(void *pBtcContext, u32 RegAddr, u16 Data)
+{
+	PBTC_COEXIST pBtCoexist;
+	PADAPTER padapter;
+
+
+	pBtCoexist = (PBTC_COEXIST)pBtcContext;
+	padapter = pBtCoexist->Adapter;
+
+	rtw_write16(padapter, RegAddr, Data);
+}
+
+void halbtcoutsrc_Write4Byte(void *pBtcContext, u32 RegAddr, u32 Data)
+{
+	PBTC_COEXIST pBtCoexist;
+	PADAPTER padapter;
+
+
+	pBtCoexist = (PBTC_COEXIST)pBtcContext;
+	padapter = pBtCoexist->Adapter;
+
+	rtw_write32(padapter, RegAddr, Data);
+}
+
+void halbtcoutsrc_WriteLocalReg1Byte(void *pBtcContext, u32 RegAddr, u8 Data)
+{
+	PBTC_COEXIST		pBtCoexist = (PBTC_COEXIST)pBtcContext;
+	PADAPTER			Adapter = pBtCoexist->Adapter;
+
+	if (BTC_INTF_SDIO == pBtCoexist->chip_interface)
+		rtw_write8(Adapter, SDIO_LOCAL_BASE | RegAddr, Data);
+	else
+		rtw_write8(Adapter, RegAddr, Data);
+}
+
+void halbtcoutsrc_SetBbReg(void *pBtcContext, u32 RegAddr, u32 BitMask, u32 Data)
+{
+	PBTC_COEXIST pBtCoexist;
+	PADAPTER padapter;
+
+
+	pBtCoexist = (PBTC_COEXIST)pBtcContext;
+	padapter = pBtCoexist->Adapter;
+
+	phy_set_bb_reg(padapter, RegAddr, BitMask, Data);
+}
+
+
+u32 halbtcoutsrc_GetBbReg(void *pBtcContext, u32 RegAddr, u32 BitMask)
+{
+	PBTC_COEXIST pBtCoexist;
+	PADAPTER padapter;
+
+
+	pBtCoexist = (PBTC_COEXIST)pBtcContext;
+	padapter = pBtCoexist->Adapter;
+
+	return phy_query_bb_reg(padapter, RegAddr, BitMask);
+}
+
+void halbtcoutsrc_SetRfReg(void *pBtcContext, enum rf_path eRFPath, u32 RegAddr, u32 BitMask, u32 Data)
+{
+	PBTC_COEXIST pBtCoexist;
+	PADAPTER padapter;
+
+
+	pBtCoexist = (PBTC_COEXIST)pBtcContext;
+	padapter = pBtCoexist->Adapter;
+
+	phy_set_rf_reg(padapter, eRFPath, RegAddr, BitMask, Data);
+}
+
+u32 halbtcoutsrc_GetRfReg(void *pBtcContext, enum rf_path eRFPath, u32 RegAddr, u32 BitMask)
+{
+	PBTC_COEXIST pBtCoexist;
+	PADAPTER padapter;
+
+
+	pBtCoexist = (PBTC_COEXIST)pBtcContext;
+	padapter = pBtCoexist->Adapter;
+
+	return phy_query_rf_reg(padapter, eRFPath, RegAddr, BitMask);
+}
+
+u16 halbtcoutsrc_SetBtReg(void *pBtcContext, u8 RegType, u32 RegAddr, u32 Data)
+{
+	PBTC_COEXIST pBtCoexist;
+	u16 ret = BT_STATUS_BT_OP_SUCCESS;
+
+	pBtCoexist = (PBTC_COEXIST)pBtcContext;
+
+	if (halbtcoutsrc_IsHwMailboxExist(pBtCoexist) == _TRUE) {
+		u8 buf[3] = {0};
+		_irqL irqL;
+		u8 op_code;
+		u8 status;
+
+		_enter_critical_mutex(&GLBtcBtMpOperLock, &irqL);
+
+		Data = cpu_to_le32(Data);
+		op_code = BT_OP_WRITE_REG_VALUE;
+		status = _btmpoper_cmd(pBtCoexist, op_code, 0, (u8 *)&Data, 3);
+		if (status != BT_STATUS_BT_OP_SUCCESS)
+			ret = SET_BT_MP_OPER_RET(op_code, status);
+		else {
+			buf[0] = RegType;
+			*(u16 *)(buf + 1) = cpu_to_le16((u16)RegAddr);
+			op_code = BT_OP_WRITE_REG_ADDR;
+			status = _btmpoper_cmd(pBtCoexist, op_code, 0, buf, 3);
+			if (status != BT_STATUS_BT_OP_SUCCESS)
+				ret = SET_BT_MP_OPER_RET(op_code, status);
+		}
+
+		_exit_critical_mutex(&GLBtcBtMpOperLock, &irqL);
+	} else
+		ret = BT_STATUS_NOT_IMPLEMENT;
+
+	return ret;
+}
+
+u8 halbtcoutsrc_SetBtAntDetection(void *pBtcContext, u8 txTime, u8 btChnl)
+{
+	/* Always return _FALSE since we don't implement this yet */
+#if 0
+	PBTC_COEXIST		pBtCoexist = (PBTC_COEXIST)pBtcContext;
+	PADAPTER			Adapter = pBtCoexist->Adapter;
+	u1Byte				btCanTx = 0;
+	BOOLEAN			bStatus = FALSE;
+
+	bStatus = NDBG_SetBtAntDetection(Adapter, txTime, btChnl, &btCanTx);
+	if (bStatus && btCanTx)
+		return _TRUE;
+	else
+		return _FALSE;
+#else
+	return _FALSE;
+#endif
+}
+
+BOOLEAN
+halbtcoutsrc_SetBtTRXMASK(
+	IN	PVOID			pBtcContext,
+	IN	u1Byte			bt_trx_mask
+	)
+{
+	/* Always return _FALSE since we don't implement this yet */
+#if 0
+	struct btc_coexist *pBtCoexist = (struct btc_coexist *)pBtcContext;
+	PADAPTER			Adapter = pBtCoexist->Adapter;
+	BOOLEAN				bStatus = FALSE;
+	u1Byte				btCanTx = 0;
+
+	if (IS_HARDWARE_TYPE_8723B(pBtCoexist->Adapter) || IS_HARDWARE_TYPE_8723D(pBtCoexist->Adapter)
+			|| IS_HARDWARE_TYPE_8821C(pBtCoexist->Adapter)) {
+
+	if (IS_HARDWARE_TYPE_8723B(pBtCoexist->Adapter))
+		bStatus = NDBG_SetBtTRXMASK(Adapter, 1, bt_trx_mask, &btCanTx);
+	else
+		bStatus = NDBG_SetBtTRXMASK(Adapter, 2, bt_trx_mask, &btCanTx);
+	}
+
+	
+	if (bStatus)
+		return TRUE;
+	else
+		return FALSE;
+#else
+	return _FALSE;
+#endif
+}
+
+u16 halbtcoutsrc_GetBtReg_with_status(void *pBtcContext, u8 RegType, u32 RegAddr, u32 *data)
+{
+	PBTC_COEXIST pBtCoexist;
+	u16 ret = BT_STATUS_BT_OP_SUCCESS;
+
+	pBtCoexist = (PBTC_COEXIST)pBtcContext;
+
+	if (halbtcoutsrc_IsHwMailboxExist(pBtCoexist) == _TRUE) {
+		u8 buf[3] = {0};
+		_irqL irqL;
+		u8 op_code;
+		u8 status;
+
+		buf[0] = RegType;
+		*(u16 *)(buf + 1) = cpu_to_le16((u16)RegAddr);
+
+		_enter_critical_mutex(&GLBtcBtMpOperLock, &irqL);
+
+		op_code = BT_OP_READ_REG;
+		status = _btmpoper_cmd(pBtCoexist, op_code, 0, buf, 3);
+		if (status == BT_STATUS_BT_OP_SUCCESS)
+			*data = le16_to_cpu(*(u16 *)GLBtcBtMpRptRsp);
+		else
+			ret = SET_BT_MP_OPER_RET(op_code, status);
+
+		_exit_critical_mutex(&GLBtcBtMpOperLock, &irqL);
+
+	} else
+		ret = BT_STATUS_NOT_IMPLEMENT;
+
+	return ret;
+}
+
+u32 halbtcoutsrc_GetBtReg(void *pBtcContext, u8 RegType, u32 RegAddr)
+{
+	u32 regVal;
+	
+	return (BT_STATUS_BT_OP_SUCCESS == halbtcoutsrc_GetBtReg_with_status(pBtcContext, RegType, RegAddr, &regVal)) ? regVal : 0xffffffff;
+}
+
+void halbtcoutsrc_FillH2cCmd(void *pBtcContext, u8 elementId, u32 cmdLen, u8 *pCmdBuffer)
+{
+	PBTC_COEXIST pBtCoexist;
+	PADAPTER padapter;
+
+
+	pBtCoexist = (PBTC_COEXIST)pBtcContext;
+	padapter = pBtCoexist->Adapter;
+
+	rtw_hal_fill_h2c_cmd(padapter, elementId, cmdLen, pCmdBuffer);
+}
+
+static void halbtcoutsrc_coex_offload_init(void)
+{
+	u1Byte	i;
+
+	gl_coex_offload.h2c_req_num = 0;
+	gl_coex_offload.cnt_h2c_sent = 0;
+	gl_coex_offload.cnt_c2h_ack = 0;
+	gl_coex_offload.cnt_c2h_ind = 0;
+
+	for (i = 0; i < COL_MAX_H2C_REQ_NUM; i++)
+		init_completion(&gl_coex_offload.c2h_event[i]);
+}
+
+static COL_H2C_STATUS halbtcoutsrc_send_h2c(PADAPTER Adapter, PCOL_H2C pcol_h2c, u16 h2c_cmd_len)
+{
+	COL_H2C_STATUS		h2c_status = COL_STATUS_C2H_OK;
+	u8				i;
+
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 13, 0))
+	reinit_completion(&gl_coex_offload.c2h_event[pcol_h2c->req_num]);		/* set event to un signaled state */
+#else
+	INIT_COMPLETION(gl_coex_offload.c2h_event[pcol_h2c->req_num]);
+#endif
+
+	if (TRUE) {
+#if 0	/*(USE_HAL_MAC_API == 1) */
+		if (RT_STATUS_SUCCESS == HAL_MAC_Send_BT_COEX(&GET_HAL_MAC_INFO(Adapter), (pu1Byte)(pcol_h2c), (u4Byte)h2c_cmd_len, 1)) {
+			if (!wait_for_completion_timeout(&gl_coex_offload.c2h_event[pcol_h2c->req_num], 20)) {
+				h2c_status = COL_STATUS_H2C_TIMTOUT;
+			}
+		} else {
+			h2c_status = COL_STATUS_H2C_HALMAC_FAIL;
+		}
+#endif
+	}
+
+	return h2c_status;
+}
+
+static COL_H2C_STATUS halbtcoutsrc_check_c2h_ack(PADAPTER Adapter, PCOL_SINGLE_H2C_RECORD pH2cRecord)
+{
+	COL_H2C_STATUS	c2h_status = COL_STATUS_C2H_OK;
+	PCOL_H2C		p_h2c_cmd = (PCOL_H2C)&pH2cRecord->h2c_buf[0];
+	u8			req_num = p_h2c_cmd->req_num;
+	PCOL_C2H_ACK	p_c2h_ack = (PCOL_C2H_ACK)&gl_coex_offload.c2h_ack_buf[req_num];
+
+
+	if ((COL_C2H_ACK_HDR_LEN + p_c2h_ack->ret_len) > gl_coex_offload.c2h_ack_len[req_num]) {
+		c2h_status = COL_STATUS_COEX_DATA_OVERFLOW;
+		return c2h_status;
+	}
+	/* else */
+	{
+		_rtw_memmove(&pH2cRecord->c2h_ack_buf[0], &gl_coex_offload.c2h_ack_buf[req_num], gl_coex_offload.c2h_ack_len[req_num]);
+		pH2cRecord->c2h_ack_len = gl_coex_offload.c2h_ack_len[req_num];
+	}
+
+
+	if (p_c2h_ack->req_num != p_h2c_cmd->req_num) {
+		c2h_status = COL_STATUS_C2H_REQ_NUM_MISMATCH;
+	} else if (p_c2h_ack->opcode_ver != p_h2c_cmd->opcode_ver) {
+		c2h_status = COL_STATUS_C2H_OPCODE_VER_MISMATCH;
+	} else {
+		c2h_status = p_c2h_ack->status;
+	}
+
+	return c2h_status;
+}
+
+COL_H2C_STATUS halbtcoutsrc_CoexH2cProcess(void *pBtCoexist,
+		u8 opcode, u8 opcode_ver, u8 *ph2c_par, u8 h2c_par_len)
+{
+	PADAPTER			Adapter = ((struct btc_coexist *)pBtCoexist)->Adapter;
+	u8				H2C_Parameter[BTC_TMP_BUF_SHORT] = {0};
+	PCOL_H2C			pcol_h2c = (PCOL_H2C)&H2C_Parameter[0];
+	u16				paraLen = 0;
+	COL_H2C_STATUS		h2c_status = COL_STATUS_C2H_OK, c2h_status = COL_STATUS_C2H_OK;
+	COL_H2C_STATUS		ret_status = COL_STATUS_C2H_OK;
+	u16				i, col_h2c_len = 0;
+
+	pcol_h2c->opcode = opcode;
+	pcol_h2c->opcode_ver = opcode_ver;
+	pcol_h2c->req_num = gl_coex_offload.h2c_req_num;
+	gl_coex_offload.h2c_req_num++;
+	gl_coex_offload.h2c_req_num %= 16;
+
+	_rtw_memmove(&pcol_h2c->buf[0], ph2c_par, h2c_par_len);
+
+
+	col_h2c_len = h2c_par_len + 2;	/* 2=sizeof(OPCode, OPCode_version and  Request number) */
+	BT_PrintData(Adapter, "[COL], H2C cmd: ", col_h2c_len, H2C_Parameter);
+
+	gl_coex_offload.cnt_h2c_sent++;
+
+	gl_coex_offload.h2c_record[opcode].count++;
+	gl_coex_offload.h2c_record[opcode].h2c_len = col_h2c_len;
+	_rtw_memmove((PVOID)&gl_coex_offload.h2c_record[opcode].h2c_buf[0], (PVOID)pcol_h2c, col_h2c_len);
+
+	h2c_status = halbtcoutsrc_send_h2c(Adapter, pcol_h2c, col_h2c_len);
+
+	gl_coex_offload.h2c_record[opcode].c2h_ack_len = 0;
+
+	if (COL_STATUS_C2H_OK == h2c_status) {
+		/* if reach here, it means H2C get the correct c2h response, */
+		c2h_status = halbtcoutsrc_check_c2h_ack(Adapter, &gl_coex_offload.h2c_record[opcode]);
+		ret_status = c2h_status;
+	} else {
+		/* check h2c status error, return error status code to upper layer. */
+		ret_status = h2c_status;
+	}
+	gl_coex_offload.h2c_record[opcode].status[ret_status]++;
+	gl_coex_offload.status[ret_status]++;
+
+	return ret_status;
+}
+
+u8 halbtcoutsrc_GetAntDetValFromBt(void *pBtcContext)
+{
+	/* Always return 0 since we don't implement this yet */
+#if 0
+	struct btc_coexist *pBtCoexist = (struct btc_coexist *)pBtcContext;
+	PADAPTER			Adapter = pBtCoexist->Adapter;
+	u1Byte				AntDetVal = 0x0;
+	u1Byte				opcodeVer = 1;
+	BOOLEAN				status = false;
+
+	status = NDBG_GetAntDetValFromBt(Adapter, opcodeVer, &AntDetVal);
+
+	RT_TRACE(COMP_DBG, DBG_LOUD, ("$$$ halbtcoutsrc_GetAntDetValFromBt(): status = %d, feature = %x\n", status, AntDetVal));
+
+	return AntDetVal;
+#else
+	return 0;
+#endif
+}
+
+u8 halbtcoutsrc_GetBleScanTypeFromBt(void *pBtcContext)
+{
+	PBTC_COEXIST pBtCoexist;
+	u32 ret = BT_STATUS_BT_OP_SUCCESS;
+	u8 data = 0;
+
+	pBtCoexist = (PBTC_COEXIST)pBtcContext;
+
+	if (halbtcoutsrc_IsHwMailboxExist(pBtCoexist) == _TRUE) {
+		u8 buf[3] = {0};
+		_irqL irqL;
+		u8 op_code;
+		u8 status;
+
+
+		_enter_critical_mutex(&GLBtcBtMpOperLock, &irqL);
+
+		op_code = BT_OP_GET_BT_BLE_SCAN_TYPE;
+		status = _btmpoper_cmd(pBtCoexist, op_code, 0, buf, 0);
+		if (status == BT_STATUS_BT_OP_SUCCESS)
+			data = *(u8 *)GLBtcBtMpRptRsp;
+		else
+			ret = SET_BT_MP_OPER_RET(op_code, status);
+
+		_exit_critical_mutex(&GLBtcBtMpOperLock, &irqL);
+
+	} else
+		ret = BT_STATUS_NOT_IMPLEMENT;
+
+	return data;
+}
+
+u32 halbtcoutsrc_GetBleScanParaFromBt(void *pBtcContext, u8 scanType)
+{
+	PBTC_COEXIST pBtCoexist;
+	u32 ret = BT_STATUS_BT_OP_SUCCESS;
+	u32 data = 0;
+
+	pBtCoexist = (PBTC_COEXIST)pBtcContext;
+
+	if (halbtcoutsrc_IsHwMailboxExist(pBtCoexist) == _TRUE) {
+		u8 buf[3] = {0};
+		_irqL irqL;
+		u8 op_code;
+		u8 status;
+		
+		buf[0] = scanType;
+
+		_enter_critical_mutex(&GLBtcBtMpOperLock, &irqL);
+
+		op_code = BT_OP_GET_BT_BLE_SCAN_PARA;
+		status = _btmpoper_cmd(pBtCoexist, op_code, 0, buf, 1);
+		if (status == BT_STATUS_BT_OP_SUCCESS)
+			data = le32_to_cpu(*(u32 *)GLBtcBtMpRptRsp);
+		else
+			ret = SET_BT_MP_OPER_RET(op_code, status);
+
+		_exit_critical_mutex(&GLBtcBtMpOperLock, &irqL);
+
+	} else
+		ret = BT_STATUS_NOT_IMPLEMENT;
+
+	return data;
+}
+
+u8 halbtcoutsrc_GetBtAFHMapFromBt(void *pBtcContext, u8 mapType, u8 *afhMap)
+{
+	struct btc_coexist *pBtCoexist = (struct btc_coexist *)pBtcContext;
+	u8 buf[2] = {0};
+	_irqL irqL;
+	u8 op_code;
+	u32 *AfhMapL = (u32 *)&(afhMap[0]);
+	u32 *AfhMapM = (u32 *)&(afhMap[4]);
+	u16 *AfhMapH = (u16 *)&(afhMap[8]);
+	u8 status;
+	u32 ret = BT_STATUS_BT_OP_SUCCESS;
+
+	if (halbtcoutsrc_IsHwMailboxExist(pBtCoexist) == _FALSE)
+		return _FALSE;
+
+	buf[0] = 0;
+	buf[1] = mapType;
+
+	_enter_critical_mutex(&GLBtcBtMpOperLock, &irqL);
+
+	op_code = BT_LO_OP_GET_AFH_MAP_L;
+	status = _btmpoper_cmd(pBtCoexist, op_code, 0, buf, 0);
+	if (status == BT_STATUS_BT_OP_SUCCESS)
+		*AfhMapL = le32_to_cpu(*(u32 *)GLBtcBtMpRptRsp);
+	else {
+		ret = SET_BT_MP_OPER_RET(op_code, status);
+		goto exit;
+	}
+
+	op_code = BT_LO_OP_GET_AFH_MAP_M;
+	status = _btmpoper_cmd(pBtCoexist, op_code, 0, buf, 0);
+	if (status == BT_STATUS_BT_OP_SUCCESS)
+		*AfhMapM = le32_to_cpu(*(u32 *)GLBtcBtMpRptRsp);
+	else {
+		ret = SET_BT_MP_OPER_RET(op_code, status);
+		goto exit;
+	}
+
+	op_code = BT_LO_OP_GET_AFH_MAP_H;
+	status = _btmpoper_cmd(pBtCoexist, op_code, 0, buf, 0);
+	if (status == BT_STATUS_BT_OP_SUCCESS)
+		*AfhMapH = le16_to_cpu(*(u16 *)GLBtcBtMpRptRsp);
+	else {
+		ret = SET_BT_MP_OPER_RET(op_code, status);
+		goto exit;
+	}
+
+exit:
+
+	_exit_critical_mutex(&GLBtcBtMpOperLock, &irqL);
+
+	return (ret == BT_STATUS_BT_OP_SUCCESS) ? _TRUE : _FALSE;
+}
+
+u32 halbtcoutsrc_GetPhydmVersion(void *pBtcContext)
+{
+	struct btc_coexist *pBtCoexist = (struct btc_coexist *)pBtcContext;
+	PADAPTER		Adapter = pBtCoexist->Adapter;
+
+#ifdef CONFIG_RTL8192E
+	return RELEASE_VERSION_8192E;
+#endif
+
+#ifdef CONFIG_RTL8821A
+	return RELEASE_VERSION_8821A;
+#endif
+
+#ifdef CONFIG_RTL8723B
+	return RELEASE_VERSION_8723B;
+#endif
+
+#ifdef CONFIG_RTL8812A
+	return RELEASE_VERSION_8812A;
+#endif
+
+#ifdef CONFIG_RTL8703B
+	return RELEASE_VERSION_8703B;
+#endif
+
+#ifdef CONFIG_RTL8822B
+	return RELEASE_VERSION_8822B;
+#endif
+
+#ifdef CONFIG_RTL8723D
+	return RELEASE_VERSION_8723D;
+#endif
+
+#ifdef CONFIG_RTL8821C
+	return RELEASE_VERSION_8821C;
+#endif
+
+#ifdef CONFIG_RTL8192F
+	return RELEASE_VERSION_8192F;
+#endif
+}
+
+u32 halbtcoutsrc_SetAtomic (void *btc_ctx, u32 *target, u32 val)
+{
+	*target = val;
+	return _SUCCESS;
+}
+
+void halbtcoutsrc_phydm_modify_AntDiv_HwSw(void *pBtcContext, u8 is_hw)
+{
+	/* empty function since we don't need it */
+}
+
+void halbtcoutsrc_phydm_modify_RA_PCR_threshold(void *pBtcContext, u8 RA_offset_direction, u8 RA_threshold_offset)
+{
+	struct btc_coexist *pBtCoexist = (struct btc_coexist *)pBtcContext;
+
+/* switch to #if 0 in case the phydm version does not provide the function */
+#if 1
+	phydm_modify_RA_PCR_threshold(pBtCoexist->odm_priv, RA_offset_direction, RA_threshold_offset);
+#endif
+}
+
+u32 halbtcoutsrc_phydm_query_PHY_counter(void *pBtcContext, u8 info_type)
+{
+	struct btc_coexist *pBtCoexist = (struct btc_coexist *)pBtcContext;
+
+/* switch to #if 0 in case the phydm version does not provide the function */
+#if 1
+	return phydm_cmn_info_query((struct dm_struct *)pBtCoexist->odm_priv, (enum phydm_info_query)info_type);
+#else
+	return 0;
+#endif
+}
+
+#if 0
+static void BT_CoexOffloadRecordErrC2hAck(PADAPTER	Adapter)
+{
+	PADAPTER		pDefaultAdapter = GetDefaultAdapter(Adapter);
+
+	if (pDefaultAdapter != Adapter)
+		return;
+
+	if (!hal_btcoex_IsBtExist(Adapter))
+		return;
+
+	gl_coex_offload.cnt_c2h_ack++;
+
+	gl_coex_offload.status[COL_STATUS_INVALID_C2H_LEN]++;
+}
+
+static void BT_CoexOffloadC2hAckCheck(PADAPTER	Adapter, u8 *tmpBuf, u8 length)
+{
+	PADAPTER		pDefaultAdapter = GetDefaultAdapter(Adapter);
+	PCOL_C2H_ACK	p_c2h_ack = NULL;
+	u8			req_num = 0xff;
+
+	if (pDefaultAdapter != Adapter)
+		return;
+
+	if (!hal_btcoex_IsBtExist(Adapter))
+		return;
+
+	gl_coex_offload.cnt_c2h_ack++;
+
+	if (length < COL_C2H_ACK_HDR_LEN) {		/* c2h ack length must >= 3 (status, opcode_ver, req_num and ret_len) */
+		gl_coex_offload.status[COL_STATUS_INVALID_C2H_LEN]++;
+	} else {
+		BT_PrintData(Adapter, "[COL], c2h ack:", length, tmpBuf);
+
+		p_c2h_ack = (PCOL_C2H_ACK)tmpBuf;
+		req_num = p_c2h_ack->req_num;
+
+		_rtw_memmove(&gl_coex_offload.c2h_ack_buf[req_num][0], tmpBuf, length);
+		gl_coex_offload.c2h_ack_len[req_num] = length;
+
+		complete(&gl_coex_offload.c2h_event[req_num]);
+	}
+}
+
+static void BT_CoexOffloadC2hIndCheck(PADAPTER Adapter, u8 *tmpBuf, u8 length)
+{
+	PADAPTER		pDefaultAdapter = GetDefaultAdapter(Adapter);
+	PCOL_C2H_IND	p_c2h_ind = NULL;
+	u8			ind_type = 0, ind_version = 0, ind_length = 0;
+
+	if (pDefaultAdapter != Adapter)
+		return;
+
+	if (!hal_btcoex_IsBtExist(Adapter))
+		return;
+
+	gl_coex_offload.cnt_c2h_ind++;
+
+	if (length < COL_C2H_IND_HDR_LEN) {		/* c2h indication length must >= 3 (type, version and length) */
+		gl_coex_offload.c2h_ind_status[COL_STATUS_INVALID_C2H_LEN]++;
+	} else {
+		BT_PrintData(Adapter, "[COL], c2h indication:", length, tmpBuf);
+
+		p_c2h_ind = (PCOL_C2H_IND)tmpBuf;
+		ind_type = p_c2h_ind->type;
+		ind_version = p_c2h_ind->version;
+		ind_length = p_c2h_ind->length;
+
+		_rtw_memmove(&gl_coex_offload.c2h_ind_buf[0], tmpBuf, length);
+		gl_coex_offload.c2h_ind_len = length;
+
+		/* log */
+		gl_coex_offload.c2h_ind_record[ind_type].count++;
+		gl_coex_offload.c2h_ind_record[ind_type].status[COL_STATUS_C2H_OK]++;
+		_rtw_memmove(&gl_coex_offload.c2h_ind_record[ind_type].ind_buf[0], tmpBuf, length);
+		gl_coex_offload.c2h_ind_record[ind_type].ind_len = length;
+
+		gl_coex_offload.c2h_ind_status[COL_STATUS_C2H_OK]++;
+		/*TODO: need to check c2h indication length*/
+		/* TODO: Notification */
+	}
+}
+
+void BT_CoexOffloadC2hCheck(PADAPTER Adapter, u8 *Buffer, u8 Length)
+{
+#if 0 /*(USE_HAL_MAC_API == 1)*/
+	u8	c2hSubCmdId = 0, c2hAckLen = 0, h2cCmdId = 0, h2cSubCmdId = 0, c2hIndLen = 0;
+
+	BT_PrintData(Adapter, "[COL], c2h packet:", Length - 2, Buffer + 2);
+	c2hSubCmdId = (u1Byte)C2H_HDR_GET_C2H_SUB_CMD_ID(Buffer);
+
+	if (c2hSubCmdId == C2H_SUB_CMD_ID_H2C_ACK_HDR ||
+	    c2hSubCmdId == C2H_SUB_CMD_ID_BT_COEX_INFO) {
+		if (c2hSubCmdId == C2H_SUB_CMD_ID_H2C_ACK_HDR) {
+			/* coex c2h ack */
+			h2cCmdId = (u1Byte)H2C_ACK_HDR_GET_H2C_CMD_ID(Buffer);
+			h2cSubCmdId = (u1Byte)H2C_ACK_HDR_GET_H2C_SUB_CMD_ID(Buffer);
+			if (h2cCmdId == 0xff && h2cSubCmdId == 0x60) {
+				c2hAckLen = (u1Byte)C2H_HDR_GET_LEN(Buffer);
+				if (c2hAckLen >= 8)
+					BT_CoexOffloadC2hAckCheck(Adapter, &Buffer[12], (u1Byte)(c2hAckLen - 8));
+				else
+					BT_CoexOffloadRecordErrC2hAck(Adapter);
+			}
+		} else if (c2hSubCmdId == C2H_SUB_CMD_ID_BT_COEX_INFO) {
+			/* coex c2h indication */
+			c2hIndLen = (u1Byte)C2H_HDR_GET_LEN(Buffer);
+			BT_CoexOffloadC2hIndCheck(Adapter, &Buffer[4], (u1Byte)c2hIndLen);
+		}
+	}
+#endif
+}
+#endif
+
+/* ************************************
+ *		Extern functions called by other module
+ * ************************************ */
+u8 EXhalbtcoutsrc_BindBtCoexWithAdapter(void *padapter)
+{
+	PBTC_COEXIST		pBtCoexist = &GLBtCoexist;
+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA((PADAPTER)padapter);
+
+	if (pBtCoexist->bBinded)
+		return _FALSE;
+	else
+		pBtCoexist->bBinded = _TRUE;
+
+	pBtCoexist->statistics.cnt_bind++;
+
+	pBtCoexist->Adapter = padapter;
+	pBtCoexist->odm_priv = (PVOID)&(pHalData->odmpriv);
+
+	pBtCoexist->stack_info.profile_notified = _FALSE;
+
+	pBtCoexist->bt_info.bt_ctrl_agg_buf_size = _FALSE;
+	pBtCoexist->bt_info.agg_buf_size = 5;
+
+	pBtCoexist->bt_info.increase_scan_dev_num = _FALSE;
+	pBtCoexist->bt_info.miracast_plus_bt = _FALSE;
+
+	return _TRUE;
+}
+
+void EXhalbtcoutsrc_AntInfoSetting(void *padapter)
+{
+	PBTC_COEXIST		pBtCoexist = &GLBtCoexist;
+	u8	antNum = 1, singleAntPath = 0;
+
+	antNum = rtw_btcoex_get_pg_ant_num((PADAPTER)padapter);
+	EXhalbtcoutsrc_SetAntNum(BT_COEX_ANT_TYPE_PG, antNum);
+
+	if (antNum == 1) {
+		singleAntPath = rtw_btcoex_get_pg_single_ant_path((PADAPTER)padapter);
+		EXhalbtcoutsrc_SetSingleAntPath(singleAntPath);
+	}
+
+	pBtCoexist->board_info.customerID = RT_CID_DEFAULT;
+	pBtCoexist->board_info.customer_id = RT_CID_DEFAULT;
+
+	/* set default antenna position to main  port */
+	pBtCoexist->board_info.btdm_ant_pos = BTC_ANTENNA_AT_MAIN_PORT;
+
+	pBtCoexist->board_info.btdm_ant_det_finish = _FALSE;
+	pBtCoexist->board_info.btdm_ant_num_by_ant_det = 1;
+
+	pBtCoexist->board_info.tfbga_package = rtw_btcoex_is_tfbga_package_type((PADAPTER)padapter);
+
+	pBtCoexist->board_info.rfe_type = rtw_btcoex_get_pg_rfe_type((PADAPTER)padapter);
+
+	pBtCoexist->board_info.ant_div_cfg = rtw_btcoex_get_ant_div_cfg((PADAPTER)padapter);
+
+}
+
+u8 EXhalbtcoutsrc_InitlizeVariables(void *padapter)
+{
+	PBTC_COEXIST pBtCoexist = &GLBtCoexist;
+
+	/* pBtCoexist->statistics.cntBind++; */
+
+	halbtcoutsrc_DbgInit();
+
+	halbtcoutsrc_coex_offload_init();
+
+#ifdef CONFIG_PCI_HCI
+	pBtCoexist->chip_interface = BTC_INTF_PCI;
+#elif defined(CONFIG_USB_HCI)
+	pBtCoexist->chip_interface = BTC_INTF_USB;
+#elif defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
+	pBtCoexist->chip_interface = BTC_INTF_SDIO;
+#else
+	pBtCoexist->chip_interface = BTC_INTF_UNKNOWN;
+#endif
+
+	EXhalbtcoutsrc_BindBtCoexWithAdapter(padapter);
+
+	pBtCoexist->btc_read_1byte = halbtcoutsrc_Read1Byte;
+	pBtCoexist->btc_write_1byte = halbtcoutsrc_Write1Byte;
+	pBtCoexist->btc_write_1byte_bitmask = halbtcoutsrc_BitMaskWrite1Byte;
+	pBtCoexist->btc_read_2byte = halbtcoutsrc_Read2Byte;
+	pBtCoexist->btc_write_2byte = halbtcoutsrc_Write2Byte;
+	pBtCoexist->btc_read_4byte = halbtcoutsrc_Read4Byte;
+	pBtCoexist->btc_write_4byte = halbtcoutsrc_Write4Byte;
+	pBtCoexist->btc_write_local_reg_1byte = halbtcoutsrc_WriteLocalReg1Byte;
+
+	pBtCoexist->btc_set_bb_reg = halbtcoutsrc_SetBbReg;
+	pBtCoexist->btc_get_bb_reg = halbtcoutsrc_GetBbReg;
+
+	pBtCoexist->btc_set_rf_reg = halbtcoutsrc_SetRfReg;
+	pBtCoexist->btc_get_rf_reg = halbtcoutsrc_GetRfReg;
+
+	pBtCoexist->btc_fill_h2c = halbtcoutsrc_FillH2cCmd;
+	pBtCoexist->btc_disp_dbg_msg = halbtcoutsrc_DisplayDbgMsg;
+
+	pBtCoexist->btc_get = halbtcoutsrc_Get;
+	pBtCoexist->btc_set = halbtcoutsrc_Set;
+	pBtCoexist->btc_get_bt_reg = halbtcoutsrc_GetBtReg;
+	pBtCoexist->btc_set_bt_reg = halbtcoutsrc_SetBtReg;
+	pBtCoexist->btc_set_bt_ant_detection = halbtcoutsrc_SetBtAntDetection;
+	pBtCoexist->btc_set_bt_trx_mask = halbtcoutsrc_SetBtTRXMASK;
+	pBtCoexist->btc_coex_h2c_process = halbtcoutsrc_CoexH2cProcess;
+	pBtCoexist->btc_get_bt_coex_supported_feature = halbtcoutsrc_GetBtCoexSupportedFeature;
+	pBtCoexist->btc_get_bt_coex_supported_version= halbtcoutsrc_GetBtCoexSupportedVersion;
+	pBtCoexist->btc_get_ant_det_val_from_bt = halbtcoutsrc_GetAntDetValFromBt;
+	pBtCoexist->btc_get_ble_scan_type_from_bt = halbtcoutsrc_GetBleScanTypeFromBt;
+	pBtCoexist->btc_get_ble_scan_para_from_bt = halbtcoutsrc_GetBleScanParaFromBt;
+	pBtCoexist->btc_get_bt_afh_map_from_bt = halbtcoutsrc_GetBtAFHMapFromBt;
+	pBtCoexist->btc_get_bt_phydm_version = halbtcoutsrc_GetPhydmVersion;
+	pBtCoexist->btc_set_atomic= halbtcoutsrc_SetAtomic;
+	pBtCoexist->btc_phydm_modify_RA_PCR_threshold = halbtcoutsrc_phydm_modify_RA_PCR_threshold;
+	pBtCoexist->btc_phydm_query_PHY_counter = halbtcoutsrc_phydm_query_PHY_counter;
+	pBtCoexist->btc_phydm_modify_antdiv_hwsw = halbtcoutsrc_phydm_modify_AntDiv_HwSw;
+
+	pBtCoexist->cli_buf = &GLBtcDbgBuf[0];
+
+	GLBtcWiFiInScanState = _FALSE;
+
+	GLBtcWiFiInIQKState = _FALSE;
+
+	GLBtcWiFiInIPS = _FALSE;
+
+	GLBtcWiFiInLPS = _FALSE;
+
+	GLBtcBtCoexAliveRegistered = _FALSE;
+
+	/* BT Control H2C/C2H*/
+	GLBtcBtMpOperSeq = 0;
+	_rtw_mutex_init(&GLBtcBtMpOperLock);
+	rtw_init_timer(&GLBtcBtMpOperTimer, padapter, _btmpoper_timer_hdl, pBtCoexist);
+	_rtw_init_sema(&GLBtcBtMpRptSema, 0);
+	GLBtcBtMpRptSeq = 0;
+	GLBtcBtMpRptStatus = 0;
+	_rtw_memset(GLBtcBtMpRptRsp, 0, C2H_MAX_SIZE);
+	GLBtcBtMpRptRspSize = 0;
+	GLBtcBtMpRptWait = _FALSE;
+	GLBtcBtMpRptWiFiOK = _FALSE;
+	GLBtcBtMpRptBTOK = _FALSE;
+
+	return _TRUE;
+}
+
+void EXhalbtcoutsrc_PowerOnSetting(PBTC_COEXIST pBtCoexist)
+{
+	HAL_DATA_TYPE	*pHalData = NULL;
+
+	if (!halbtcoutsrc_IsBtCoexistAvailable(pBtCoexist))
+		return;
+
+	pHalData = GET_HAL_DATA((PADAPTER)pBtCoexist->Adapter);
+
+	if (IS_HARDWARE_TYPE_8723B(pBtCoexist->Adapter)) {
+#ifdef CONFIG_RTL8723B
+		if (pBtCoexist->board_info.btdm_ant_num == 2)
+			ex_halbtc8723b2ant_power_on_setting(pBtCoexist);
+		else if (pBtCoexist->board_info.btdm_ant_num == 1)
+			ex_halbtc8723b1ant_power_on_setting(pBtCoexist);
+#endif
+	}
+
+#ifdef CONFIG_RTL8703B
+	else if (IS_HARDWARE_TYPE_8703B(pBtCoexist->Adapter)) {
+		if (pBtCoexist->board_info.btdm_ant_num == 1)
+			ex_halbtc8703b1ant_power_on_setting(pBtCoexist);
+	}
+#endif
+
+#ifdef CONFIG_RTL8723D
+	else if (IS_HARDWARE_TYPE_8723D(pBtCoexist->Adapter)) {
+		if (pBtCoexist->board_info.btdm_ant_num == 2)
+			ex_halbtc8723d2ant_power_on_setting(pBtCoexist);
+		else if (pBtCoexist->board_info.btdm_ant_num == 1)
+			ex_halbtc8723d1ant_power_on_setting(pBtCoexist);
+	}
+#endif
+
+#ifdef CONFIG_RTL8821A
+	else if (IS_HARDWARE_TYPE_8821(pBtCoexist->Adapter)) {
+		if (pBtCoexist->board_info.btdm_ant_num == 1)
+			ex_halbtc8821a1ant_power_on_setting(pBtCoexist);
+		else if (pBtCoexist->board_info.btdm_ant_num == 2)
+			ex_halbtc8821a2ant_power_on_setting(pBtCoexist);
+	}
+#endif
+
+#ifdef CONFIG_RTL8822B
+	else if ((IS_HARDWARE_TYPE_8822B(pBtCoexist->Adapter)) && (pHalData->EEPROMBluetoothCoexist == _TRUE)) {
+		if (pBtCoexist->board_info.btdm_ant_num == 1)
+			ex_halbtc8822b1ant_power_on_setting(pBtCoexist);
+		else if (pBtCoexist->board_info.btdm_ant_num == 2)
+			ex_halbtc8822b2ant_power_on_setting(pBtCoexist);
+	}
+#endif
+
+#ifdef CONFIG_RTL8821C
+	else if ((IS_HARDWARE_TYPE_8821C(pBtCoexist->Adapter)) && (pHalData->EEPROMBluetoothCoexist == _TRUE)) {
+		if (pBtCoexist->board_info.btdm_ant_num == 2)
+			ex_halbtc8821c2ant_power_on_setting(pBtCoexist);
+		else if (pBtCoexist->board_info.btdm_ant_num == 1)
+			ex_halbtc8821c1ant_power_on_setting(pBtCoexist);
+	}
+#endif
+}
+
+void EXhalbtcoutsrc_PreLoadFirmware(PBTC_COEXIST pBtCoexist)
+{
+	if (!halbtcoutsrc_IsBtCoexistAvailable(pBtCoexist))
+		return;
+
+	pBtCoexist->statistics.cnt_pre_load_firmware++;
+
+	if (IS_HARDWARE_TYPE_8723B(pBtCoexist->Adapter)) {
+#ifdef CONFIG_RTL8723B
+		if (pBtCoexist->board_info.btdm_ant_num == 2)
+			ex_halbtc8723b2ant_pre_load_firmware(pBtCoexist);
+		else if (pBtCoexist->board_info.btdm_ant_num == 1)
+			ex_halbtc8723b1ant_pre_load_firmware(pBtCoexist);
+#endif
+	}
+
+#ifdef CONFIG_RTL8723D
+	else if (IS_HARDWARE_TYPE_8723D(pBtCoexist->Adapter)) {
+		if (pBtCoexist->board_info.btdm_ant_num == 2)
+			ex_halbtc8723d2ant_pre_load_firmware(pBtCoexist);
+		else if (pBtCoexist->board_info.btdm_ant_num == 1)
+			ex_halbtc8723d1ant_pre_load_firmware(pBtCoexist);
+	}
+#endif
+
+#ifdef CONFIG_RTL8821C
+	else if (IS_HARDWARE_TYPE_8821C(pBtCoexist->Adapter)) {
+		if (pBtCoexist->board_info.btdm_ant_num == 2)
+			ex_halbtc8821c2ant_pre_load_firmware(pBtCoexist);
+		else if (pBtCoexist->board_info.btdm_ant_num == 1)
+			ex_halbtc8821c1ant_pre_load_firmware(pBtCoexist);
+	}
+#endif
+}
+
+void EXhalbtcoutsrc_init_hw_config(PBTC_COEXIST pBtCoexist, u8 bWifiOnly)
+{
+	if (!halbtcoutsrc_IsBtCoexistAvailable(pBtCoexist))
+		return;
+
+	pBtCoexist->statistics.cnt_init_hw_config++;
+
+	if (IS_HARDWARE_TYPE_8821(pBtCoexist->Adapter)) {
+#ifdef CONFIG_RTL8821A
+		if (pBtCoexist->board_info.btdm_ant_num == 2)
+			ex_halbtc8821a2ant_init_hw_config(pBtCoexist, bWifiOnly);
+		else if (pBtCoexist->board_info.btdm_ant_num == 1)
+			ex_halbtc8821a1ant_init_hw_config(pBtCoexist, bWifiOnly);
+#endif
+	}
+
+#ifdef CONFIG_RTL8723B
+	else if (IS_HARDWARE_TYPE_8723B(pBtCoexist->Adapter)) {
+		if (pBtCoexist->board_info.btdm_ant_num == 2)
+			ex_halbtc8723b2ant_init_hw_config(pBtCoexist, bWifiOnly);
+		else if (pBtCoexist->board_info.btdm_ant_num == 1)
+			ex_halbtc8723b1ant_init_hw_config(pBtCoexist, bWifiOnly);
+	}
+#endif
+
+#ifdef CONFIG_RTL8703B
+	else if (IS_HARDWARE_TYPE_8703B(pBtCoexist->Adapter)) {
+		if (pBtCoexist->board_info.btdm_ant_num == 1)
+			ex_halbtc8703b1ant_init_hw_config(pBtCoexist, bWifiOnly);
+	}
+#endif
+
+#ifdef CONFIG_RTL8723D
+	else if (IS_HARDWARE_TYPE_8723D(pBtCoexist->Adapter)) {
+		if (pBtCoexist->board_info.btdm_ant_num == 2)
+			ex_halbtc8723d2ant_init_hw_config(pBtCoexist, bWifiOnly);
+		else if (pBtCoexist->board_info.btdm_ant_num == 1)
+			ex_halbtc8723d1ant_init_hw_config(pBtCoexist, bWifiOnly);
+	}
+#endif
+
+#ifdef CONFIG_RTL8192E
+	else if (IS_HARDWARE_TYPE_8192E(pBtCoexist->Adapter)) {
+		if (pBtCoexist->board_info.btdm_ant_num == 2)
+			ex_halbtc8192e2ant_init_hw_config(pBtCoexist, bWifiOnly);
+		else if (pBtCoexist->board_info.btdm_ant_num == 1)
+			ex_halbtc8192e1ant_init_hw_config(pBtCoexist, bWifiOnly);
+	}
+#endif
+
+#ifdef CONFIG_RTL8812A
+	else if (IS_HARDWARE_TYPE_8812(pBtCoexist->Adapter)) {
+		if (pBtCoexist->board_info.btdm_ant_num == 2)
+			ex_halbtc8812a2ant_init_hw_config(pBtCoexist, bWifiOnly);
+		else if (pBtCoexist->board_info.btdm_ant_num == 1)
+			ex_halbtc8812a1ant_init_hw_config(pBtCoexist, bWifiOnly);
+	}
+#endif
+
+#ifdef CONFIG_RTL8822B
+	else if (IS_HARDWARE_TYPE_8822B(pBtCoexist->Adapter)) {
+		if (pBtCoexist->board_info.btdm_ant_num == 1)
+			ex_halbtc8822b1ant_init_hw_config(pBtCoexist, bWifiOnly);
+		else if (pBtCoexist->board_info.btdm_ant_num == 2)
+			ex_halbtc8822b2ant_init_hw_config(pBtCoexist, bWifiOnly);
+	}
+#endif
+
+#ifdef CONFIG_RTL8821C
+	else if (IS_HARDWARE_TYPE_8821C(pBtCoexist->Adapter)) {
+		if (pBtCoexist->board_info.btdm_ant_num == 2)
+			ex_halbtc8821c2ant_init_hw_config(pBtCoexist, bWifiOnly);
+		else if (pBtCoexist->board_info.btdm_ant_num == 1)
+			ex_halbtc8821c1ant_init_hw_config(pBtCoexist, bWifiOnly);
+	}
+#endif
+}
+
+void EXhalbtcoutsrc_init_coex_dm(PBTC_COEXIST pBtCoexist)
+{
+	if (!halbtcoutsrc_IsBtCoexistAvailable(pBtCoexist))
+		return;
+
+	pBtCoexist->statistics.cnt_init_coex_dm++;
+
+	if (IS_HARDWARE_TYPE_8821(pBtCoexist->Adapter)) {
+#ifdef CONFIG_RTL8821A
+		if (pBtCoexist->board_info.btdm_ant_num == 2)
+			ex_halbtc8821a2ant_init_coex_dm(pBtCoexist);
+		else if (pBtCoexist->board_info.btdm_ant_num == 1)
+			ex_halbtc8821a1ant_init_coex_dm(pBtCoexist);
+#endif
+	}
+
+#ifdef CONFIG_RTL8723B
+	else if (IS_HARDWARE_TYPE_8723B(pBtCoexist->Adapter)) {
+		if (pBtCoexist->board_info.btdm_ant_num == 2)
+			ex_halbtc8723b2ant_init_coex_dm(pBtCoexist);
+		else if (pBtCoexist->board_info.btdm_ant_num == 1)
+			ex_halbtc8723b1ant_init_coex_dm(pBtCoexist);
+	}
+#endif
+
+#ifdef CONFIG_RTL8703B
+	else if (IS_HARDWARE_TYPE_8703B(pBtCoexist->Adapter)) {
+		if (pBtCoexist->board_info.btdm_ant_num == 1)
+			ex_halbtc8703b1ant_init_coex_dm(pBtCoexist);
+	}
+#endif
+
+#ifdef CONFIG_RTL8723D
+	else if (IS_HARDWARE_TYPE_8723D(pBtCoexist->Adapter)) {
+		if (pBtCoexist->board_info.btdm_ant_num == 2)
+			ex_halbtc8723d2ant_init_coex_dm(pBtCoexist);
+		else if (pBtCoexist->board_info.btdm_ant_num == 1)
+			ex_halbtc8723d1ant_init_coex_dm(pBtCoexist);
+	}
+#endif
+
+#ifdef CONFIG_RTL8192E
+	else if (IS_HARDWARE_TYPE_8192E(pBtCoexist->Adapter)) {
+		if (pBtCoexist->board_info.btdm_ant_num == 2)
+			ex_halbtc8192e2ant_init_coex_dm(pBtCoexist);
+		else if (pBtCoexist->board_info.btdm_ant_num == 1)
+			ex_halbtc8192e1ant_init_coex_dm(pBtCoexist);
+	}
+#endif
+
+#ifdef CONFIG_RTL8812A
+	else if (IS_HARDWARE_TYPE_8812(pBtCoexist->Adapter)) {
+		if (pBtCoexist->board_info.btdm_ant_num == 2)
+			ex_halbtc8812a2ant_init_coex_dm(pBtCoexist);
+		else if (pBtCoexist->board_info.btdm_ant_num == 1)
+			ex_halbtc8812a1ant_init_coex_dm(pBtCoexist);
+	}
+#endif
+
+#ifdef CONFIG_RTL8822B
+	else if (IS_HARDWARE_TYPE_8822B(pBtCoexist->Adapter)) {
+		if (pBtCoexist->board_info.btdm_ant_num == 1)
+			ex_halbtc8822b1ant_init_coex_dm(pBtCoexist);
+		else if (pBtCoexist->board_info.btdm_ant_num == 2)
+			ex_halbtc8822b2ant_init_coex_dm(pBtCoexist);
+	}
+#endif
+
+#ifdef CONFIG_RTL8821C
+	else if (IS_HARDWARE_TYPE_8821C(pBtCoexist->Adapter)) {
+		if (pBtCoexist->board_info.btdm_ant_num == 2)
+			ex_halbtc8821c2ant_init_coex_dm(pBtCoexist);
+		else if (pBtCoexist->board_info.btdm_ant_num == 1)
+			ex_halbtc8821c1ant_init_coex_dm(pBtCoexist);
+	}
+#endif
+
+	pBtCoexist->initilized = _TRUE;
+}
+
+void EXhalbtcoutsrc_ips_notify(PBTC_COEXIST pBtCoexist, u8 type)
+{
+	u8	ipsType;
+
+	if (!halbtcoutsrc_IsBtCoexistAvailable(pBtCoexist))
+		return;
+
+	pBtCoexist->statistics.cnt_ips_notify++;
+	if (pBtCoexist->manual_control)
+		return;
+
+	if (IPS_NONE == type) {
+		ipsType = BTC_IPS_LEAVE;
+		GLBtcWiFiInIPS = _FALSE;
+	} else {
+		ipsType = BTC_IPS_ENTER;
+		GLBtcWiFiInIPS = _TRUE;
+	}
+
+	/* All notify is called in cmd thread, don't need to leave low power again
+	*	halbtcoutsrc_LeaveLowPower(pBtCoexist); */
+
+	if (IS_HARDWARE_TYPE_8821(pBtCoexist->Adapter)) {
+#ifdef CONFIG_RTL8821A
+		if (pBtCoexist->board_info.btdm_ant_num == 2)
+			ex_halbtc8821a2ant_ips_notify(pBtCoexist, ipsType);
+		else if (pBtCoexist->board_info.btdm_ant_num == 1)
+			ex_halbtc8821a1ant_ips_notify(pBtCoexist, ipsType);
+#endif
+	}
+
+#ifdef CONFIG_RTL8723B
+	else if (IS_HARDWARE_TYPE_8723B(pBtCoexist->Adapter)) {
+		if (pBtCoexist->board_info.btdm_ant_num == 2)
+			ex_halbtc8723b2ant_ips_notify(pBtCoexist, ipsType);
+		else if (pBtCoexist->board_info.btdm_ant_num == 1)
+			ex_halbtc8723b1ant_ips_notify(pBtCoexist, ipsType);
+	}
+#endif
+
+#ifdef CONFIG_RTL8703B
+	else if (IS_HARDWARE_TYPE_8703B(pBtCoexist->Adapter)) {
+		if (pBtCoexist->board_info.btdm_ant_num == 1)
+			ex_halbtc8703b1ant_ips_notify(pBtCoexist, ipsType);
+	}
+#endif
+
+#ifdef CONFIG_RTL8723D
+	else if (IS_HARDWARE_TYPE_8723D(pBtCoexist->Adapter)) {
+		if (pBtCoexist->board_info.btdm_ant_num == 2)
+			ex_halbtc8723d2ant_ips_notify(pBtCoexist, ipsType);
+		else if (pBtCoexist->board_info.btdm_ant_num == 1)
+			ex_halbtc8723d1ant_ips_notify(pBtCoexist, ipsType);
+	}
+#endif
+
+#ifdef CONFIG_RTL8192E
+	else if (IS_HARDWARE_TYPE_8192E(pBtCoexist->Adapter)) {
+		if (pBtCoexist->board_info.btdm_ant_num == 2)
+			ex_halbtc8192e2ant_ips_notify(pBtCoexist, ipsType);
+		else if (pBtCoexist->board_info.btdm_ant_num == 1)
+			ex_halbtc8192e1ant_ips_notify(pBtCoexist, ipsType);
+	}
+#endif
+
+#ifdef CONFIG_RTL8812A
+	else if (IS_HARDWARE_TYPE_8812(pBtCoexist->Adapter)) {
+		if (pBtCoexist->board_info.btdm_ant_num == 2)
+			ex_halbtc8812a2ant_ips_notify(pBtCoexist, ipsType);
+		else if (pBtCoexist->board_info.btdm_ant_num == 1)
+			ex_halbtc8812a1ant_ips_notify(pBtCoexist, ipsType);
+	}
+#endif
+
+#ifdef CONFIG_RTL8822B
+	else if (IS_HARDWARE_TYPE_8822B(pBtCoexist->Adapter)) {
+		if (pBtCoexist->board_info.btdm_ant_num == 1)
+			ex_halbtc8822b1ant_ips_notify(pBtCoexist, ipsType);
+		else if (pBtCoexist->board_info.btdm_ant_num == 2)
+			ex_halbtc8822b2ant_ips_notify(pBtCoexist, ipsType);
+	}
+#endif
+
+#ifdef CONFIG_RTL8821C
+	else if (IS_HARDWARE_TYPE_8821C(pBtCoexist->Adapter)) {
+		if (pBtCoexist->board_info.btdm_ant_num == 2)
+			ex_halbtc8821c2ant_ips_notify(pBtCoexist, ipsType);
+		else if (pBtCoexist->board_info.btdm_ant_num == 1)
+			ex_halbtc8821c1ant_ips_notify(pBtCoexist, ipsType);
+	}
+#endif
+	/*	halbtcoutsrc_NormalLowPower(pBtCoexist); */
+}
+
+void EXhalbtcoutsrc_lps_notify(PBTC_COEXIST pBtCoexist, u8 type)
+{
+	u8 lpsType;
+
+
+	if (!halbtcoutsrc_IsBtCoexistAvailable(pBtCoexist))
+		return;
+
+	pBtCoexist->statistics.cnt_lps_notify++;
+	if (pBtCoexist->manual_control)
+		return;
+
+	if (PS_MODE_ACTIVE == type) {
+		lpsType = BTC_LPS_DISABLE;
+		GLBtcWiFiInLPS = _FALSE;
+	} else {
+		lpsType = BTC_LPS_ENABLE;
+		GLBtcWiFiInLPS = _TRUE;
+	}
+
+	if (IS_HARDWARE_TYPE_8821(pBtCoexist->Adapter)) {
+#ifdef CONFIG_RTL8821A
+		if (pBtCoexist->board_info.btdm_ant_num == 2)
+			ex_halbtc8821a2ant_lps_notify(pBtCoexist, lpsType);
+		else if (pBtCoexist->board_info.btdm_ant_num == 1)
+			ex_halbtc8821a1ant_lps_notify(pBtCoexist, lpsType);
+#endif
+	}
+
+#ifdef CONFIG_RTL8723B
+	else if (IS_HARDWARE_TYPE_8723B(pBtCoexist->Adapter)) {
+		if (pBtCoexist->board_info.btdm_ant_num == 2)
+			ex_halbtc8723b2ant_lps_notify(pBtCoexist, lpsType);
+		else if (pBtCoexist->board_info.btdm_ant_num == 1)
+			ex_halbtc8723b1ant_lps_notify(pBtCoexist, lpsType);
+	}
+#endif
+
+#ifdef CONFIG_RTL8703B
+	else if (IS_HARDWARE_TYPE_8703B(pBtCoexist->Adapter)) {
+		if (pBtCoexist->board_info.btdm_ant_num == 1)
+			ex_halbtc8703b1ant_lps_notify(pBtCoexist, lpsType);
+	}
+#endif
+
+#ifdef CONFIG_RTL8723D
+	else if (IS_HARDWARE_TYPE_8723D(pBtCoexist->Adapter)) {
+		if (pBtCoexist->board_info.btdm_ant_num == 2)
+			ex_halbtc8723d2ant_lps_notify(pBtCoexist, lpsType);
+		else if (pBtCoexist->board_info.btdm_ant_num == 1)
+			ex_halbtc8723d1ant_lps_notify(pBtCoexist, lpsType);
+	}
+#endif
+
+#ifdef CONFIG_RTL8192E
+	else if (IS_HARDWARE_TYPE_8192E(pBtCoexist->Adapter)) {
+		if (pBtCoexist->board_info.btdm_ant_num == 2)
+			ex_halbtc8192e2ant_lps_notify(pBtCoexist, lpsType);
+		else if (pBtCoexist->board_info.btdm_ant_num == 1)
+			ex_halbtc8192e1ant_lps_notify(pBtCoexist, lpsType);
+	}
+#endif
+
+#ifdef CONFIG_RTL8812A
+	else if (IS_HARDWARE_TYPE_8812(pBtCoexist->Adapter)) {
+		if (pBtCoexist->board_info.btdm_ant_num == 2)
+			ex_halbtc8812a2ant_lps_notify(pBtCoexist, lpsType);
+		else if (pBtCoexist->board_info.btdm_ant_num == 1)
+			ex_halbtc8812a1ant_lps_notify(pBtCoexist, lpsType);
+	}
+#endif
+
+#ifdef CONFIG_RTL8822B
+	else if (IS_HARDWARE_TYPE_8822B(pBtCoexist->Adapter)) {
+		if (pBtCoexist->board_info.btdm_ant_num == 1)
+			ex_halbtc8822b1ant_lps_notify(pBtCoexist, lpsType);
+		else if (pBtCoexist->board_info.btdm_ant_num == 2)
+			ex_halbtc8822b2ant_lps_notify(pBtCoexist, lpsType);
+	}
+#endif
+
+#ifdef CONFIG_RTL8821C
+	else if (IS_HARDWARE_TYPE_8821C(pBtCoexist->Adapter)) {
+		if (pBtCoexist->board_info.btdm_ant_num == 2)
+			ex_halbtc8821c2ant_lps_notify(pBtCoexist, lpsType);
+		else if (pBtCoexist->board_info.btdm_ant_num == 1)
+			ex_halbtc8821c1ant_lps_notify(pBtCoexist, lpsType);
+	}
+#endif
+}
+
+void EXhalbtcoutsrc_scan_notify(PBTC_COEXIST pBtCoexist, u8 type)
+{
+	u8	scanType;
+
+	if (!halbtcoutsrc_IsBtCoexistAvailable(pBtCoexist))
+		return;
+	pBtCoexist->statistics.cnt_scan_notify++;
+	if (pBtCoexist->manual_control)
+		return;
+
+	if (type) {
+		scanType = BTC_SCAN_START;
+		GLBtcWiFiInScanState = _TRUE;
+	} else {
+		scanType = BTC_SCAN_FINISH;
+		GLBtcWiFiInScanState = _FALSE;
+	}
+
+	/* All notify is called in cmd thread, don't need to leave low power again
+	*	halbtcoutsrc_LeaveLowPower(pBtCoexist); */
+
+	if (IS_HARDWARE_TYPE_8821(pBtCoexist->Adapter)) {
+#ifdef CONFIG_RTL8821A
+		if (pBtCoexist->board_info.btdm_ant_num == 2)
+			ex_halbtc8821a2ant_scan_notify(pBtCoexist, scanType);
+		else if (pBtCoexist->board_info.btdm_ant_num == 1)
+			ex_halbtc8821a1ant_scan_notify(pBtCoexist, scanType);
+#endif
+	}
+
+#ifdef CONFIG_RTL8723B
+	else if (IS_HARDWARE_TYPE_8723B(pBtCoexist->Adapter)) {
+		if (pBtCoexist->board_info.btdm_ant_num == 2)
+			ex_halbtc8723b2ant_scan_notify(pBtCoexist, scanType);
+		else if (pBtCoexist->board_info.btdm_ant_num == 1)
+			ex_halbtc8723b1ant_scan_notify(pBtCoexist, scanType);
+	}
+#endif
+
+#ifdef CONFIG_RTL8703B
+	else if (IS_HARDWARE_TYPE_8703B(pBtCoexist->Adapter)) {
+		if (pBtCoexist->board_info.btdm_ant_num == 1)
+			ex_halbtc8703b1ant_scan_notify(pBtCoexist, scanType);
+	}
+#endif
+
+#ifdef CONFIG_RTL8723D
+	else if (IS_HARDWARE_TYPE_8723D(pBtCoexist->Adapter)) {
+		if (pBtCoexist->board_info.btdm_ant_num == 2)
+			ex_halbtc8723d2ant_scan_notify(pBtCoexist, scanType);
+		else if (pBtCoexist->board_info.btdm_ant_num == 1)
+			ex_halbtc8723d1ant_scan_notify(pBtCoexist, scanType);
+	}
+#endif
+
+#ifdef CONFIG_RTL8192E
+	else if (IS_HARDWARE_TYPE_8192E(pBtCoexist->Adapter)) {
+		if (pBtCoexist->board_info.btdm_ant_num == 2)
+			ex_halbtc8192e2ant_scan_notify(pBtCoexist, scanType);
+		else if (pBtCoexist->board_info.btdm_ant_num == 1)
+			ex_halbtc8192e1ant_scan_notify(pBtCoexist, scanType);
+	}
+#endif
+
+#ifdef CONFIG_RTL8812A
+	else if (IS_HARDWARE_TYPE_8812(pBtCoexist->Adapter)) {
+		if (pBtCoexist->board_info.btdm_ant_num == 2)
+			ex_halbtc8812a2ant_scan_notify(pBtCoexist, scanType);
+		else if (pBtCoexist->board_info.btdm_ant_num == 1)
+			ex_halbtc8812a1ant_scan_notify(pBtCoexist, scanType);
+	}
+#endif
+
+#ifdef CONFIG_RTL8822B
+	else if (IS_HARDWARE_TYPE_8822B(pBtCoexist->Adapter)) {
+		if (pBtCoexist->board_info.btdm_ant_num == 1)
+			ex_halbtc8822b1ant_scan_notify(pBtCoexist, scanType);
+		else if (pBtCoexist->board_info.btdm_ant_num == 2)
+			ex_halbtc8822b2ant_scan_notify(pBtCoexist, scanType);
+	}
+#endif
+
+#ifdef CONFIG_RTL8821C
+	else if (IS_HARDWARE_TYPE_8821C(pBtCoexist->Adapter)) {
+		if (pBtCoexist->board_info.btdm_ant_num == 2)
+			ex_halbtc8821c2ant_scan_notify(pBtCoexist, scanType);
+		else if (pBtCoexist->board_info.btdm_ant_num == 1)
+			ex_halbtc8821c1ant_scan_notify(pBtCoexist, scanType);
+	}
+#endif
+
+	/*	halbtcoutsrc_NormalLowPower(pBtCoexist); */
+}
+
+void EXhalbtcoutsrc_SetAntennaPathNotify(PBTC_COEXIST pBtCoexist, u8 type)
+{
+#if 0
+	u8	switchType;
+
+	if (!halbtcoutsrc_IsBtCoexistAvailable(pBtCoexist))
+		return;
+
+	if (pBtCoexist->manual_control)
+		return;
+
+	halbtcoutsrc_LeaveLowPower(pBtCoexist);
+
+	switchType = type;
+
+	if (IS_HARDWARE_TYPE_8723B(pBtCoexist->Adapter)) {
+		if (pBtCoexist->board_info.btdm_ant_num == 1)
+			ex_halbtc8723b1ant_set_antenna_notify(pBtCoexist, type);
+	}
+	if (IS_HARDWARE_TYPE_8723D(pBtCoexist->Adapter)) {
+		if (pBtCoexist->board_info.btdm_ant_num == 1)
+			ex_halbtc8723d1ant_set_antenna_notify(pBtCoexist, type);
+		else if (pBtCoexist->board_info.btdm_ant_num == 2)
+			ex_halbtc8723d2ant_set_antenna_notify(pBtCoexist, type);
+	}
+
+	halbtcoutsrc_NormalLowPower(pBtCoexist);
+#endif
+}
+
+void EXhalbtcoutsrc_connect_notify(PBTC_COEXIST pBtCoexist, u8 assoType)
+{
+	if (!halbtcoutsrc_IsBtCoexistAvailable(pBtCoexist))
+		return;
+	pBtCoexist->statistics.cnt_connect_notify++;
+	if (pBtCoexist->manual_control)
+		return;
+	
+	/* All notify is called in cmd thread, don't need to leave low power again
+	*	halbtcoutsrc_LeaveLowPower(pBtCoexist); */
+	if (IS_HARDWARE_TYPE_8821(pBtCoexist->Adapter)) {
+#ifdef CONFIG_RTL8821A
+		if (pBtCoexist->board_info.btdm_ant_num == 2)
+			ex_halbtc8821a2ant_connect_notify(pBtCoexist, assoType);
+		else if (pBtCoexist->board_info.btdm_ant_num == 1)
+			ex_halbtc8821a1ant_connect_notify(pBtCoexist, assoType);
+#endif
+	}
+
+#ifdef CONFIG_RTL8723B
+	else if (IS_HARDWARE_TYPE_8723B(pBtCoexist->Adapter)) {
+		if (pBtCoexist->board_info.btdm_ant_num == 2)
+			ex_halbtc8723b2ant_connect_notify(pBtCoexist, assoType);
+		else if (pBtCoexist->board_info.btdm_ant_num == 1)
+			ex_halbtc8723b1ant_connect_notify(pBtCoexist, assoType);
+	}
+#endif
+
+#ifdef CONFIG_RTL8703B
+	else if (IS_HARDWARE_TYPE_8703B(pBtCoexist->Adapter)) {
+		if (pBtCoexist->board_info.btdm_ant_num == 1)
+			ex_halbtc8703b1ant_connect_notify(pBtCoexist, assoType);
+	}
+#endif
+
+#ifdef CONFIG_RTL8723D
+	else if (IS_HARDWARE_TYPE_8723D(pBtCoexist->Adapter)) {
+		if (pBtCoexist->board_info.btdm_ant_num == 2)
+			ex_halbtc8723d2ant_connect_notify(pBtCoexist, assoType);
+		else if (pBtCoexist->board_info.btdm_ant_num == 1)
+			ex_halbtc8723d1ant_connect_notify(pBtCoexist, assoType);
+	}
+#endif
+
+#ifdef CONFIG_RTL8192E
+	else if (IS_HARDWARE_TYPE_8192E(pBtCoexist->Adapter)) {
+		if (pBtCoexist->board_info.btdm_ant_num == 2)
+			ex_halbtc8192e2ant_connect_notify(pBtCoexist, assoType);
+		else if (pBtCoexist->board_info.btdm_ant_num == 1)
+			ex_halbtc8192e1ant_connect_notify(pBtCoexist, assoType);
+	}
+#endif
+
+#ifdef CONFIG_RTL8812A
+	else if (IS_HARDWARE_TYPE_8812(pBtCoexist->Adapter)) {
+		if (pBtCoexist->board_info.btdm_ant_num == 2)
+			ex_halbtc8812a2ant_connect_notify(pBtCoexist, assoType);
+		else if (pBtCoexist->board_info.btdm_ant_num == 1)
+			ex_halbtc8812a1ant_connect_notify(pBtCoexist, assoType);
+	}
+#endif
+
+#ifdef CONFIG_RTL8822B
+	else if (IS_HARDWARE_TYPE_8822B(pBtCoexist->Adapter)) {
+		if (pBtCoexist->board_info.btdm_ant_num == 1)
+			ex_halbtc8822b1ant_connect_notify(pBtCoexist, assoType);
+		else if (pBtCoexist->board_info.btdm_ant_num == 2)
+			ex_halbtc8822b2ant_connect_notify(pBtCoexist, assoType);
+	}
+#endif
+
+#ifdef CONFIG_RTL8821C
+	else if (IS_HARDWARE_TYPE_8821C(pBtCoexist->Adapter)) {
+		if (pBtCoexist->board_info.btdm_ant_num == 2)
+			ex_halbtc8821c2ant_connect_notify(pBtCoexist, assoType);
+		else if (pBtCoexist->board_info.btdm_ant_num == 1)
+			ex_halbtc8821c1ant_connect_notify(pBtCoexist, assoType);
+	}
+#endif
+
+	/*	halbtcoutsrc_NormalLowPower(pBtCoexist); */
+}
+
+void EXhalbtcoutsrc_media_status_notify(PBTC_COEXIST pBtCoexist, RT_MEDIA_STATUS mediaStatus)
+{
+	u8 mStatus = BTC_MEDIA_MAX;
+	PADAPTER adapter = (PADAPTER)pBtCoexist->Adapter;
+	HAL_DATA_TYPE *hal = GET_HAL_DATA(adapter);
+
+	if (!halbtcoutsrc_IsBtCoexistAvailable(pBtCoexist))
+		return;
+
+	pBtCoexist->statistics.cnt_media_status_notify++;
+	if (pBtCoexist->manual_control)
+		return;
+
+	if (RT_MEDIA_CONNECT == mediaStatus) {
+		if (hal->current_band_type == BAND_ON_2_4G)
+			mStatus = BTC_MEDIA_CONNECT;
+		else if (hal->current_band_type == BAND_ON_5G)
+			mStatus = BTC_MEDIA_CONNECT_5G;
+		else {
+			mStatus = BTC_MEDIA_CONNECT;
+			RTW_ERR("%s unknow band type\n", __func__);
+		}
+	} else
+		mStatus = BTC_MEDIA_DISCONNECT;
+
+	/* All notify is called in cmd thread, don't need to leave low power again
+	*	halbtcoutsrc_LeaveLowPower(pBtCoexist); */
+	if (IS_HARDWARE_TYPE_8821(pBtCoexist->Adapter)) {
+#ifdef CONFIG_RTL8821A
+		/* compatible for 8821A */
+		if (mStatus == BTC_MEDIA_CONNECT_5G)
+			mStatus = BTC_MEDIA_CONNECT;
+		if (pBtCoexist->board_info.btdm_ant_num == 2)
+			ex_halbtc8821a2ant_media_status_notify(pBtCoexist, mStatus);
+		else if (pBtCoexist->board_info.btdm_ant_num == 1)
+			ex_halbtc8821a1ant_media_status_notify(pBtCoexist, mStatus);
+#endif
+	}
+
+#ifdef CONFIG_RTL8723B
+	else if (IS_HARDWARE_TYPE_8723B(pBtCoexist->Adapter)) {
+		if (pBtCoexist->board_info.btdm_ant_num == 2)
+			ex_halbtc8723b2ant_media_status_notify(pBtCoexist, mStatus);
+		else if (pBtCoexist->board_info.btdm_ant_num == 1)
+			ex_halbtc8723b1ant_media_status_notify(pBtCoexist, mStatus);
+	}
+#endif
+
+#ifdef CONFIG_RTL8703B
+	else if (IS_HARDWARE_TYPE_8703B(pBtCoexist->Adapter)) {
+		if (pBtCoexist->board_info.btdm_ant_num == 1)
+			ex_halbtc8703b1ant_media_status_notify(pBtCoexist, mStatus);
+	}
+#endif
+
+#ifdef CONFIG_RTL8723D
+	else if (IS_HARDWARE_TYPE_8723D(pBtCoexist->Adapter)) {
+		if (pBtCoexist->board_info.btdm_ant_num == 2)
+			ex_halbtc8723d2ant_media_status_notify(pBtCoexist, mStatus);
+		else if (pBtCoexist->board_info.btdm_ant_num == 1)
+			ex_halbtc8723d1ant_media_status_notify(pBtCoexist, mStatus);
+	}
+#endif
+
+#ifdef CONFIG_RTL8192E
+	else if (IS_HARDWARE_TYPE_8192E(pBtCoexist->Adapter)) {
+		if (pBtCoexist->board_info.btdm_ant_num == 2)
+			ex_halbtc8192e2ant_media_status_notify(pBtCoexist, mStatus);
+		else if (pBtCoexist->board_info.btdm_ant_num == 1)
+			ex_halbtc8192e1ant_media_status_notify(pBtCoexist, mStatus);
+	}
+#endif
+
+#ifdef CONFIG_RTL8812A
+	else if (IS_HARDWARE_TYPE_8812(pBtCoexist->Adapter)) {
+		/* compatible for 8812A */
+		if (mStatus == BTC_MEDIA_CONNECT_5G)
+			mStatus = BTC_MEDIA_CONNECT;
+		if (pBtCoexist->board_info.btdm_ant_num == 2)
+			ex_halbtc8812a2ant_media_status_notify(pBtCoexist, mStatus);
+		else if (pBtCoexist->board_info.btdm_ant_num == 1)
+			ex_halbtc8812a1ant_media_status_notify(pBtCoexist, mStatus);
+	}
+#endif
+
+#ifdef CONFIG_RTL8822B
+	else if (IS_HARDWARE_TYPE_8822B(pBtCoexist->Adapter)) {
+		if (pBtCoexist->board_info.btdm_ant_num == 1)
+			ex_halbtc8822b1ant_media_status_notify(pBtCoexist, mStatus);
+		else if (pBtCoexist->board_info.btdm_ant_num == 2)
+			ex_halbtc8822b2ant_media_status_notify(pBtCoexist, mStatus);
+	}
+#endif
+
+#ifdef CONFIG_RTL8821C
+	else if (IS_HARDWARE_TYPE_8821C(pBtCoexist->Adapter)) {
+		if (pBtCoexist->board_info.btdm_ant_num == 2)
+			ex_halbtc8821c2ant_media_status_notify(pBtCoexist, mStatus);
+		else if (pBtCoexist->board_info.btdm_ant_num == 1)
+			ex_halbtc8821c1ant_media_status_notify(pBtCoexist, mStatus);
+	}
+#endif
+
+	/*	halbtcoutsrc_NormalLowPower(pBtCoexist); */
+}
+
+void EXhalbtcoutsrc_specific_packet_notify(PBTC_COEXIST pBtCoexist, u8 pktType)
+{
+	u8 packetType;
+	PADAPTER adapter = (PADAPTER)pBtCoexist->Adapter;
+	HAL_DATA_TYPE *hal = GET_HAL_DATA(adapter);
+
+	if (!halbtcoutsrc_IsBtCoexistAvailable(pBtCoexist))
+		return;
+	pBtCoexist->statistics.cnt_specific_packet_notify++;
+	if (pBtCoexist->manual_control)
+		return;
+
+	if (PACKET_DHCP == pktType)
+		packetType = BTC_PACKET_DHCP;
+	else if (PACKET_EAPOL == pktType)
+		packetType = BTC_PACKET_EAPOL;
+	else if (PACKET_ARP == pktType)
+		packetType = BTC_PACKET_ARP;
+	else {
+		packetType = BTC_PACKET_UNKNOWN;
+		return;
+	}
+
+	if (hal->current_band_type == BAND_ON_5G)
+		packetType |=  BTC_5G_BAND;
+
+	/* All notify is called in cmd thread, don't need to leave low power again
+	*	halbtcoutsrc_LeaveLowPower(pBtCoexist); */
+	if (IS_HARDWARE_TYPE_8821(pBtCoexist->Adapter)) {
+#ifdef CONFIG_RTL8821A
+		/* compatible for 8821A */
+		if (hal->current_band_type == BAND_ON_5G)
+			packetType &= ~BTC_5G_BAND;
+
+		if (pBtCoexist->board_info.btdm_ant_num == 2)
+			ex_halbtc8821a2ant_specific_packet_notify(pBtCoexist, packetType);
+		else if (pBtCoexist->board_info.btdm_ant_num == 1)
+			ex_halbtc8821a1ant_specific_packet_notify(pBtCoexist, packetType);
+#endif
+	}
+
+#ifdef CONFIG_RTL8723B
+	else if (IS_HARDWARE_TYPE_8723B(pBtCoexist->Adapter)) {
+		if (pBtCoexist->board_info.btdm_ant_num == 2)
+			ex_halbtc8723b2ant_specific_packet_notify(pBtCoexist, packetType);
+		else if (pBtCoexist->board_info.btdm_ant_num == 1)
+			ex_halbtc8723b1ant_specific_packet_notify(pBtCoexist, packetType);
+	}
+#endif
+
+#ifdef CONFIG_RTL8703B
+	else if (IS_HARDWARE_TYPE_8703B(pBtCoexist->Adapter)) {
+		if (pBtCoexist->board_info.btdm_ant_num == 1)
+			ex_halbtc8703b1ant_specific_packet_notify(pBtCoexist, packetType);
+	}
+#endif
+
+#ifdef CONFIG_RTL8723D
+	else if (IS_HARDWARE_TYPE_8723D(pBtCoexist->Adapter)) {
+		if (pBtCoexist->board_info.btdm_ant_num == 2)
+			ex_halbtc8723d2ant_specific_packet_notify(pBtCoexist, packetType);
+		else if (pBtCoexist->board_info.btdm_ant_num == 1)
+			ex_halbtc8723d1ant_specific_packet_notify(pBtCoexist, packetType);
+	}
+#endif
+
+#ifdef CONFIG_RTL8192E
+	else if (IS_HARDWARE_TYPE_8192E(pBtCoexist->Adapter)) {
+		if (pBtCoexist->board_info.btdm_ant_num == 2)
+			ex_halbtc8192e2ant_specific_packet_notify(pBtCoexist, packetType);
+		else if (pBtCoexist->board_info.btdm_ant_num == 1)
+			ex_halbtc8192e1ant_specific_packet_notify(pBtCoexist, packetType);
+	}
+#endif
+
+#ifdef CONFIG_RTL8812A
+	else if (IS_HARDWARE_TYPE_8812(pBtCoexist->Adapter)) {
+		/* compatible for 8812A */
+		if (hal->current_band_type == BAND_ON_5G)
+			packetType &= ~BTC_5G_BAND;
+		
+		if (pBtCoexist->board_info.btdm_ant_num == 2)
+			ex_halbtc8812a2ant_specific_packet_notify(pBtCoexist, packetType);
+		else if (pBtCoexist->board_info.btdm_ant_num == 1)
+			ex_halbtc8812a1ant_specific_packet_notify(pBtCoexist, packetType);
+	}
+#endif
+
+#ifdef CONFIG_RTL8822B
+	else if (IS_HARDWARE_TYPE_8822B(pBtCoexist->Adapter)) {
+		if (pBtCoexist->board_info.btdm_ant_num == 1)
+			ex_halbtc8822b1ant_specific_packet_notify(pBtCoexist, packetType);
+		else if (pBtCoexist->board_info.btdm_ant_num == 2)
+			ex_halbtc8822b2ant_specific_packet_notify(pBtCoexist, packetType);
+	}
+#endif
+
+#ifdef CONFIG_RTL8821C
+	else if (IS_HARDWARE_TYPE_8821C(pBtCoexist->Adapter)) {
+		if (pBtCoexist->board_info.btdm_ant_num == 2)
+			ex_halbtc8821c2ant_specific_packet_notify(pBtCoexist, packetType);
+		else if (pBtCoexist->board_info.btdm_ant_num == 1)
+			ex_halbtc8821c1ant_specific_packet_notify(pBtCoexist, packetType);
+	}
+#endif
+
+	/*	halbtcoutsrc_NormalLowPower(pBtCoexist); */
+}
+
+void EXhalbtcoutsrc_bt_info_notify(PBTC_COEXIST pBtCoexist, u8 *tmpBuf, u8 length)
+{
+	if (!halbtcoutsrc_IsBtCoexistAvailable(pBtCoexist))
+		return;
+
+	pBtCoexist->statistics.cnt_bt_info_notify++;
+
+	/* All notify is called in cmd thread, don't need to leave low power again
+	*	halbtcoutsrc_LeaveLowPower(pBtCoexist); */
+	if (IS_HARDWARE_TYPE_8821(pBtCoexist->Adapter)) {
+#ifdef CONFIG_RTL8821A
+		if (pBtCoexist->board_info.btdm_ant_num == 2)
+			ex_halbtc8821a2ant_bt_info_notify(pBtCoexist, tmpBuf, length);
+		else if (pBtCoexist->board_info.btdm_ant_num == 1)
+			ex_halbtc8821a1ant_bt_info_notify(pBtCoexist, tmpBuf, length);
+#endif
+	}
+
+#ifdef CONFIG_RTL8723B
+	else if (IS_HARDWARE_TYPE_8723B(pBtCoexist->Adapter)) {
+		if (pBtCoexist->board_info.btdm_ant_num == 2)
+			ex_halbtc8723b2ant_bt_info_notify(pBtCoexist, tmpBuf, length);
+		else if (pBtCoexist->board_info.btdm_ant_num == 1)
+			ex_halbtc8723b1ant_bt_info_notify(pBtCoexist, tmpBuf, length);
+	}
+#endif
+
+#ifdef CONFIG_RTL8703B
+	else if (IS_HARDWARE_TYPE_8703B(pBtCoexist->Adapter)) {
+		if (pBtCoexist->board_info.btdm_ant_num == 1)
+			ex_halbtc8703b1ant_bt_info_notify(pBtCoexist, tmpBuf, length);
+	}
+#endif
+
+#ifdef CONFIG_RTL8723D
+	else if (IS_HARDWARE_TYPE_8723D(pBtCoexist->Adapter)) {
+		if (pBtCoexist->board_info.btdm_ant_num == 2)
+			ex_halbtc8723d2ant_bt_info_notify(pBtCoexist, tmpBuf, length);
+		else if (pBtCoexist->board_info.btdm_ant_num == 1)
+			ex_halbtc8723d1ant_bt_info_notify(pBtCoexist, tmpBuf, length);
+	}
+#endif
+
+#ifdef CONFIG_RTL8192E
+	else if (IS_HARDWARE_TYPE_8192E(pBtCoexist->Adapter)) {
+		if (pBtCoexist->board_info.btdm_ant_num == 2)
+			ex_halbtc8192e2ant_bt_info_notify(pBtCoexist, tmpBuf, length);
+		else if (pBtCoexist->board_info.btdm_ant_num == 1)
+			ex_halbtc8192e1ant_bt_info_notify(pBtCoexist, tmpBuf, length);
+	}
+#endif
+
+#ifdef CONFIG_RTL8812A
+	else if (IS_HARDWARE_TYPE_8812(pBtCoexist->Adapter)) {
+		if (pBtCoexist->board_info.btdm_ant_num == 2)
+			ex_halbtc8812a2ant_bt_info_notify(pBtCoexist, tmpBuf, length);
+		else if (pBtCoexist->board_info.btdm_ant_num == 1)
+			ex_halbtc8812a1ant_bt_info_notify(pBtCoexist, tmpBuf, length);
+	}
+#endif
+
+#ifdef CONFIG_RTL8822B
+	else if (IS_HARDWARE_TYPE_8822B(pBtCoexist->Adapter)) {
+		if (pBtCoexist->board_info.btdm_ant_num == 1)
+			ex_halbtc8822b1ant_bt_info_notify(pBtCoexist, tmpBuf, length);
+		else if (pBtCoexist->board_info.btdm_ant_num == 2)
+			ex_halbtc8822b2ant_bt_info_notify(pBtCoexist, tmpBuf, length);
+	}
+#endif
+
+#ifdef CONFIG_RTL8821C
+	else if (IS_HARDWARE_TYPE_8821C(pBtCoexist->Adapter)) {
+		if (pBtCoexist->board_info.btdm_ant_num == 2)
+			ex_halbtc8821c2ant_bt_info_notify(pBtCoexist, tmpBuf, length);
+		else if (pBtCoexist->board_info.btdm_ant_num == 1)
+			ex_halbtc8821c1ant_bt_info_notify(pBtCoexist, tmpBuf, length);
+	}
+#endif
+
+	/*	halbtcoutsrc_NormalLowPower(pBtCoexist); */
+}
+
+void EXhalbtcoutsrc_WlFwDbgInfoNotify(PBTC_COEXIST pBtCoexist, u8* tmpBuf, u8 length)
+{
+	if (!halbtcoutsrc_IsBtCoexistAvailable(pBtCoexist))
+		return;
+
+	if (IS_HARDWARE_TYPE_8703B(pBtCoexist->Adapter)) {
+#ifdef CONFIG_RTL8703B
+		if (pBtCoexist->board_info.btdm_ant_num == 1)
+			ex_halbtc8703b1ant_wl_fwdbginfo_notify(pBtCoexist, tmpBuf, length);
+#endif
+	}
+
+#ifdef CONFIG_RTL8723D
+	else if (IS_HARDWARE_TYPE_8723D(pBtCoexist->Adapter)) {
+		if (pBtCoexist->board_info.btdm_ant_num == 1)
+			ex_halbtc8723d1ant_wl_fwdbginfo_notify(pBtCoexist, tmpBuf, length);
+		else if (pBtCoexist->board_info.btdm_ant_num == 2)
+			ex_halbtc8723d2ant_wl_fwdbginfo_notify(pBtCoexist, tmpBuf, length);
+	}
+#endif
+
+#ifdef CONFIG_RTL8821C
+	else if (IS_HARDWARE_TYPE_8821C(pBtCoexist->Adapter)) {
+		if (pBtCoexist->board_info.btdm_ant_num == 2)
+			ex_halbtc8821c2ant_wl_fwdbginfo_notify(pBtCoexist, tmpBuf, length);
+		else if (pBtCoexist->board_info.btdm_ant_num == 1)
+			ex_halbtc8821c1ant_wl_fwdbginfo_notify(pBtCoexist, tmpBuf, length);
+	}
+#endif
+}
+
+void EXhalbtcoutsrc_rx_rate_change_notify(PBTC_COEXIST pBtCoexist, u8 is_data_frame, u8 btc_rate_id)
+{
+	if (!halbtcoutsrc_IsBtCoexistAvailable(pBtCoexist))
+		return;
+
+	pBtCoexist->statistics.cnt_rate_id_notify++;
+
+	if (IS_HARDWARE_TYPE_8703B(pBtCoexist->Adapter)) {
+#ifdef CONFIG_RTL8703B
+		if (pBtCoexist->board_info.btdm_ant_num == 1)
+			ex_halbtc8703b1ant_rx_rate_change_notify(pBtCoexist, is_data_frame, btc_rate_id);
+#endif
+	}
+
+#ifdef CONFIG_RTL8723D
+	else if (IS_HARDWARE_TYPE_8723D(pBtCoexist->Adapter)) {
+		if (pBtCoexist->board_info.btdm_ant_num == 1)
+			ex_halbtc8723d1ant_rx_rate_change_notify(pBtCoexist, is_data_frame, btc_rate_id);
+		else if (pBtCoexist->board_info.btdm_ant_num == 2)
+			ex_halbtc8723d2ant_rx_rate_change_notify(pBtCoexist, is_data_frame, btc_rate_id);
+	}
+#endif
+
+#ifdef CONFIG_RTL8821C
+	else if (IS_HARDWARE_TYPE_8821C(pBtCoexist->Adapter)) {
+		if (pBtCoexist->board_info.btdm_ant_num == 1)
+			ex_halbtc8821c1ant_rx_rate_change_notify(pBtCoexist, is_data_frame, btc_rate_id);
+		else if (pBtCoexist->board_info.btdm_ant_num == 2)
+			ex_halbtc8821c2ant_rx_rate_change_notify(pBtCoexist, is_data_frame, btc_rate_id);
+	}
+#endif
+}
+
+VOID
+EXhalbtcoutsrc_RfStatusNotify(
+	IN	PBTC_COEXIST		pBtCoexist,
+	IN	u1Byte				type
+)
+{
+	if (!halbtcoutsrc_IsBtCoexistAvailable(pBtCoexist))
+		return;
+	pBtCoexist->statistics.cnt_rf_status_notify++;
+
+	if (IS_HARDWARE_TYPE_8723B(pBtCoexist->Adapter)) {
+#ifdef CONFIG_RTL8723B
+		if (pBtCoexist->board_info.btdm_ant_num == 1)
+			ex_halbtc8723b1ant_rf_status_notify(pBtCoexist, type);
+#endif
+	}
+
+#ifdef CONFIG_RTL8703B
+	else if (IS_HARDWARE_TYPE_8703B(pBtCoexist->Adapter)) {
+		if (pBtCoexist->board_info.btdm_ant_num == 1)
+			ex_halbtc8703b1ant_rf_status_notify(pBtCoexist, type);
+	}
+#endif
+
+#ifdef CONFIG_RTL8723D
+	else if (IS_HARDWARE_TYPE_8723D(pBtCoexist->Adapter)) {
+		if (pBtCoexist->board_info.btdm_ant_num == 1)
+			ex_halbtc8723d1ant_rf_status_notify(pBtCoexist, type);
+	}
+#endif
+
+#ifdef CONFIG_RTL8822B
+	else if (IS_HARDWARE_TYPE_8822B(pBtCoexist->Adapter)) {
+		if (pBtCoexist->board_info.btdm_ant_num == 1)
+			ex_halbtc8822b1ant_rf_status_notify(pBtCoexist, type);
+		else if (pBtCoexist->board_info.btdm_ant_num == 2)
+			ex_halbtc8822b2ant_rf_status_notify(pBtCoexist, type);
+	}
+#endif
+
+#ifdef CONFIG_RTL8821C
+	else if (IS_HARDWARE_TYPE_8821C(pBtCoexist->Adapter)) {
+		if (pBtCoexist->board_info.btdm_ant_num == 2)
+			ex_halbtc8821c2ant_rf_status_notify(pBtCoexist, type);
+		else if (pBtCoexist->board_info.btdm_ant_num == 1)
+			ex_halbtc8821c1ant_rf_status_notify(pBtCoexist, type);
+	}
+#endif
+}
+
+void EXhalbtcoutsrc_StackOperationNotify(PBTC_COEXIST pBtCoexist, u8 type)
+{
+#if 0
+	u8	stackOpType;
+
+	if (!halbtcoutsrc_IsBtCoexistAvailable(pBtCoexist))
+		return;
+	pBtCoexist->statistics.cntStackOperationNotify++;
+	if (pBtCoexist->manual_control)
+		return;
+
+	if ((HCI_BT_OP_INQUIRY_START == type) ||
+	    (HCI_BT_OP_PAGING_START == type) ||
+	    (HCI_BT_OP_PAIRING_START == type))
+		stackOpType = BTC_STACK_OP_INQ_PAGE_PAIR_START;
+	else if ((HCI_BT_OP_INQUIRY_FINISH == type) ||
+		 (HCI_BT_OP_PAGING_SUCCESS == type) ||
+		 (HCI_BT_OP_PAGING_UNSUCCESS == type) ||
+		 (HCI_BT_OP_PAIRING_FINISH == type))
+		stackOpType = BTC_STACK_OP_INQ_PAGE_PAIR_FINISH;
+	else
+		stackOpType = BTC_STACK_OP_NONE;
+
+#endif
+}
+
+void EXhalbtcoutsrc_halt_notify(PBTC_COEXIST pBtCoexist)
+{
+	if (!halbtcoutsrc_IsBtCoexistAvailable(pBtCoexist))
+		return;
+
+	pBtCoexist->statistics.cnt_halt_notify++;
+
+	if (IS_HARDWARE_TYPE_8821(pBtCoexist->Adapter)) {
+#ifdef CONFIG_RTL8821A
+		if (pBtCoexist->board_info.btdm_ant_num == 2)
+			ex_halbtc8821a2ant_halt_notify(pBtCoexist);
+		else if (pBtCoexist->board_info.btdm_ant_num == 1)
+			ex_halbtc8821a1ant_halt_notify(pBtCoexist);
+#endif
+	}
+
+#ifdef CONFIG_RTL8723B
+	else if (IS_HARDWARE_TYPE_8723B(pBtCoexist->Adapter)) {
+		if (pBtCoexist->board_info.btdm_ant_num == 2)
+			ex_halbtc8723b2ant_halt_notify(pBtCoexist);
+		else if (pBtCoexist->board_info.btdm_ant_num == 1)
+			ex_halbtc8723b1ant_halt_notify(pBtCoexist);
+	}
+#endif
+
+#ifdef CONFIG_RTL8703B
+	else if (IS_HARDWARE_TYPE_8703B(pBtCoexist->Adapter)) {
+		if (pBtCoexist->board_info.btdm_ant_num == 1)
+			ex_halbtc8703b1ant_halt_notify(pBtCoexist);
+	}
+#endif
+
+#ifdef CONFIG_RTL8723D
+	else if (IS_HARDWARE_TYPE_8723D(pBtCoexist->Adapter)) {
+		if (pBtCoexist->board_info.btdm_ant_num == 2)
+			ex_halbtc8723d2ant_halt_notify(pBtCoexist);
+		else if (pBtCoexist->board_info.btdm_ant_num == 1)
+			ex_halbtc8723d1ant_halt_notify(pBtCoexist);
+	}
+#endif
+
+#ifdef CONFIG_RTL8192E
+	else if (IS_HARDWARE_TYPE_8192E(pBtCoexist->Adapter)) {
+		if (pBtCoexist->board_info.btdm_ant_num == 2)
+			ex_halbtc8192e2ant_halt_notify(pBtCoexist);
+		else if (pBtCoexist->board_info.btdm_ant_num == 1)
+			ex_halbtc8192e1ant_halt_notify(pBtCoexist);
+	}
+#endif
+
+#ifdef CONFIG_RTL8812A
+	else if (IS_HARDWARE_TYPE_8812(pBtCoexist->Adapter)) {
+		if (pBtCoexist->board_info.btdm_ant_num == 2)
+			ex_halbtc8812a2ant_halt_notify(pBtCoexist);
+		else if (pBtCoexist->board_info.btdm_ant_num == 1)
+			ex_halbtc8812a1ant_halt_notify(pBtCoexist);
+	}
+#endif
+
+#ifdef CONFIG_RTL8822B
+	else if (IS_HARDWARE_TYPE_8822B(pBtCoexist->Adapter)) {
+		if (pBtCoexist->board_info.btdm_ant_num == 1)
+			ex_halbtc8822b1ant_halt_notify(pBtCoexist);
+		else if (pBtCoexist->board_info.btdm_ant_num == 2)
+			ex_halbtc8822b2ant_halt_notify(pBtCoexist);
+	}
+#endif
+
+#ifdef CONFIG_RTL8821C
+	else if (IS_HARDWARE_TYPE_8821C(pBtCoexist->Adapter)) {
+		if (pBtCoexist->board_info.btdm_ant_num == 2)
+			ex_halbtc8821c2ant_halt_notify(pBtCoexist);
+		else if (pBtCoexist->board_info.btdm_ant_num == 1)
+			ex_halbtc8821c1ant_halt_notify(pBtCoexist);
+	}
+#endif
+}
+
+void EXhalbtcoutsrc_SwitchBtTRxMask(PBTC_COEXIST pBtCoexist)
+{
+	if (IS_HARDWARE_TYPE_8723B(pBtCoexist->Adapter)) {
+		if (pBtCoexist->board_info.btdm_ant_num == 2) {
+			halbtcoutsrc_SetBtReg(pBtCoexist, 0, 0x3c, 0x01); /* BT goto standby while GNT_BT 1-->0 */
+		} else if (pBtCoexist->board_info.btdm_ant_num == 1) {
+			halbtcoutsrc_SetBtReg(pBtCoexist, 0, 0x3c, 0x15); /* BT goto standby while GNT_BT 1-->0 */
+		}
+	}
+}
+
+void EXhalbtcoutsrc_pnp_notify(PBTC_COEXIST pBtCoexist, u8 pnpState)
+{
+	if (!halbtcoutsrc_IsBtCoexistAvailable(pBtCoexist))
+		return;
+
+	pBtCoexist->statistics.cnt_pnp_notify++;
+
+	/*  */
+	/* currently only 1ant we have to do the notification, */
+	/* once pnp is notified to sleep state, we have to leave LPS that we can sleep normally. */
+	/*  */
+	if (IS_HARDWARE_TYPE_8723B(pBtCoexist->Adapter)) {
+#ifdef CONFIG_RTL8723B
+		if (pBtCoexist->board_info.btdm_ant_num == 1)
+			ex_halbtc8723b1ant_pnp_notify(pBtCoexist, pnpState);
+		else if (pBtCoexist->board_info.btdm_ant_num == 2)
+			ex_halbtc8723b2ant_pnp_notify(pBtCoexist, pnpState);
+#endif
+	}
+
+#ifdef CONFIG_RTL8703B
+	else if (IS_HARDWARE_TYPE_8703B(pBtCoexist->Adapter)) {
+		if (pBtCoexist->board_info.btdm_ant_num == 1)
+			ex_halbtc8703b1ant_pnp_notify(pBtCoexist, pnpState);
+	}
+#endif
+
+#ifdef CONFIG_RTL8723D
+	else if (IS_HARDWARE_TYPE_8723D(pBtCoexist->Adapter)) {
+		if (pBtCoexist->board_info.btdm_ant_num == 1)
+			ex_halbtc8723d1ant_pnp_notify(pBtCoexist, pnpState);
+		else if (pBtCoexist->board_info.btdm_ant_num == 2)
+			ex_halbtc8723d2ant_pnp_notify(pBtCoexist, pnpState);
+	}
+#endif
+
+#ifdef CONFIG_RTL8821A
+	else if (IS_HARDWARE_TYPE_8821(pBtCoexist->Adapter)) {
+		if (pBtCoexist->board_info.btdm_ant_num == 1)
+			ex_halbtc8821a1ant_pnp_notify(pBtCoexist, pnpState);
+		else if (pBtCoexist->board_info.btdm_ant_num == 2)
+			ex_halbtc8821a2ant_pnp_notify(pBtCoexist, pnpState);
+	}
+#endif
+
+#ifdef CONFIG_RTL8192E
+	else if (IS_HARDWARE_TYPE_8192E(pBtCoexist->Adapter)) {
+		if (pBtCoexist->board_info.btdm_ant_num == 1)
+			ex_halbtc8192e1ant_pnp_notify(pBtCoexist, pnpState);
+	}
+#endif
+
+#ifdef CONFIG_RTL8812A
+	else if (IS_HARDWARE_TYPE_8812(pBtCoexist->Adapter)) {
+		if (pBtCoexist->board_info.btdm_ant_num == 1)
+			ex_halbtc8812a1ant_pnp_notify(pBtCoexist, pnpState);
+	}
+#endif
+
+#ifdef CONFIG_RTL8822B
+	else if (IS_HARDWARE_TYPE_8822B(pBtCoexist->Adapter)) {
+		if (pBtCoexist->board_info.btdm_ant_num == 1)
+			ex_halbtc8822b1ant_pnp_notify(pBtCoexist, pnpState);
+		else if (pBtCoexist->board_info.btdm_ant_num == 2)
+			ex_halbtc8822b2ant_pnp_notify(pBtCoexist, pnpState);
+	}
+#endif
+
+#ifdef CONFIG_RTL8821C
+	else if (IS_HARDWARE_TYPE_8821C(pBtCoexist->Adapter)) {
+		if (pBtCoexist->board_info.btdm_ant_num == 2)
+			ex_halbtc8821c2ant_pnp_notify(pBtCoexist, pnpState);
+		else if (pBtCoexist->board_info.btdm_ant_num == 1)
+			ex_halbtc8821c1ant_pnp_notify(pBtCoexist, pnpState);
+	}
+#endif
+}
+
+void EXhalbtcoutsrc_CoexDmSwitch(PBTC_COEXIST pBtCoexist)
+{
+	if (!halbtcoutsrc_IsBtCoexistAvailable(pBtCoexist))
+		return;
+	pBtCoexist->statistics.cnt_coex_dm_switch++;
+
+	halbtcoutsrc_LeaveLowPower(pBtCoexist);
+
+	if (IS_HARDWARE_TYPE_8723B(pBtCoexist->Adapter)) {
+#ifdef CONFIG_RTL8723B
+		if (pBtCoexist->board_info.btdm_ant_num == 1) {
+			pBtCoexist->stop_coex_dm = TRUE;
+			ex_halbtc8723b1ant_coex_dm_reset(pBtCoexist);
+			EXhalbtcoutsrc_SetAntNum(BT_COEX_ANT_TYPE_DETECTED, 2);
+			ex_halbtc8723b2ant_init_hw_config(pBtCoexist, FALSE);
+			ex_halbtc8723b2ant_init_coex_dm(pBtCoexist);
+			pBtCoexist->stop_coex_dm = FALSE;
+		}
+#endif
+	}
+
+#ifdef CONFIG_RTL8723D
+	else if (IS_HARDWARE_TYPE_8723D(pBtCoexist->Adapter)) {
+		if (pBtCoexist->board_info.btdm_ant_num == 1) {
+			pBtCoexist->stop_coex_dm = TRUE;
+			ex_halbtc8723d1ant_coex_dm_reset(pBtCoexist);
+			EXhalbtcoutsrc_SetAntNum(BT_COEX_ANT_TYPE_DETECTED, 2);
+			ex_halbtc8723d2ant_init_hw_config(pBtCoexist, FALSE);
+			ex_halbtc8723d2ant_init_coex_dm(pBtCoexist);
+			pBtCoexist->stop_coex_dm = FALSE;
+		}
+	}
+#endif
+
+	halbtcoutsrc_NormalLowPower(pBtCoexist);
+}
+
+void EXhalbtcoutsrc_periodical(PBTC_COEXIST pBtCoexist)
+{
+	if (!halbtcoutsrc_IsBtCoexistAvailable(pBtCoexist))
+		return;
+	pBtCoexist->statistics.cnt_periodical++;
+
+	/* Periodical should be called in cmd thread, */
+	/* don't need to leave low power again
+	*	halbtcoutsrc_LeaveLowPower(pBtCoexist); */
+	if (IS_HARDWARE_TYPE_8821(pBtCoexist->Adapter)) {
+#ifdef CONFIG_RTL8821A
+		if (pBtCoexist->board_info.btdm_ant_num == 2)
+			ex_halbtc8821a2ant_periodical(pBtCoexist);
+		else if (pBtCoexist->board_info.btdm_ant_num == 1) {
+			if (!halbtcoutsrc_UnderIps(pBtCoexist))
+				ex_halbtc8821a1ant_periodical(pBtCoexist);
+		}
+#endif
+	}
+
+#ifdef CONFIG_RTL8723B
+	else if (IS_HARDWARE_TYPE_8723B(pBtCoexist->Adapter)) {
+		if (pBtCoexist->board_info.btdm_ant_num == 2)
+			ex_halbtc8723b2ant_periodical(pBtCoexist);
+		else if (pBtCoexist->board_info.btdm_ant_num == 1)
+			ex_halbtc8723b1ant_periodical(pBtCoexist);
+	}
+#endif
+
+#ifdef CONFIG_RTL8723D
+	else if (IS_HARDWARE_TYPE_8723D(pBtCoexist->Adapter)) {
+		if (pBtCoexist->board_info.btdm_ant_num == 2)
+			ex_halbtc8723d2ant_periodical(pBtCoexist);
+		else if (pBtCoexist->board_info.btdm_ant_num == 1)
+			ex_halbtc8723d1ant_periodical(pBtCoexist);
+	}
+#endif
+
+#ifdef CONFIG_RTL8703B
+	else if (IS_HARDWARE_TYPE_8703B(pBtCoexist->Adapter)) {
+		if (pBtCoexist->board_info.btdm_ant_num == 1)
+			ex_halbtc8703b1ant_periodical(pBtCoexist);
+	}
+#endif
+
+#ifdef CONFIG_RTL8192E
+	else if (IS_HARDWARE_TYPE_8192E(pBtCoexist->Adapter)) {
+		if (pBtCoexist->board_info.btdm_ant_num == 2)
+			ex_halbtc8192e2ant_periodical(pBtCoexist);
+		else if (pBtCoexist->board_info.btdm_ant_num == 1)
+			ex_halbtc8192e1ant_periodical(pBtCoexist);
+	}
+#endif
+
+#ifdef CONFIG_RTL8812A
+	else if (IS_HARDWARE_TYPE_8812(pBtCoexist->Adapter)) {
+		if (pBtCoexist->board_info.btdm_ant_num == 2)
+			ex_halbtc8812a2ant_periodical(pBtCoexist);
+		else if (pBtCoexist->board_info.btdm_ant_num == 1)
+			ex_halbtc8812a1ant_periodical(pBtCoexist);
+	}
+#endif
+
+#ifdef CONFIG_RTL8822B
+	else if (IS_HARDWARE_TYPE_8822B(pBtCoexist->Adapter)) {
+		if (pBtCoexist->board_info.btdm_ant_num == 1)
+			ex_halbtc8822b1ant_periodical(pBtCoexist);
+		else if (pBtCoexist->board_info.btdm_ant_num == 2)
+			ex_halbtc8822b2ant_periodical(pBtCoexist);
+	}
+#endif
+
+#ifdef CONFIG_RTL8821C
+	else if (IS_HARDWARE_TYPE_8821C(pBtCoexist->Adapter)) {
+		if (pBtCoexist->board_info.btdm_ant_num == 2)
+			ex_halbtc8821c2ant_periodical(pBtCoexist);
+		else if (pBtCoexist->board_info.btdm_ant_num == 1)
+			ex_halbtc8821c1ant_periodical(pBtCoexist);
+	}
+#endif
+
+	/*	halbtcoutsrc_NormalLowPower(pBtCoexist); */
+}
+
+void EXhalbtcoutsrc_dbg_control(PBTC_COEXIST pBtCoexist, u8 opCode, u8 opLen, u8 *pData)
+{
+	if (!halbtcoutsrc_IsBtCoexistAvailable(pBtCoexist))
+		return;
+
+	pBtCoexist->statistics.cnt_dbg_ctrl++;
+
+	/* This function doesn't be called yet, */
+	/* default no need to leave low power to avoid deadlock
+	*	halbtcoutsrc_LeaveLowPower(pBtCoexist); */
+	if (IS_HARDWARE_TYPE_8192E(pBtCoexist->Adapter)) {
+#ifdef CONFIG_RTL8192E
+		if (pBtCoexist->board_info.btdm_ant_num == 1)
+			ex_halbtc8192e1ant_dbg_control(pBtCoexist, opCode, opLen, pData);
+#endif
+	}
+
+#ifdef CONFIG_RTL8812A
+	else if (IS_HARDWARE_TYPE_8812(pBtCoexist->Adapter)) {
+		if (pBtCoexist->board_info.btdm_ant_num == 2)
+			ex_halbtc8812a2ant_dbg_control(pBtCoexist, opCode, opLen, pData);
+		else if (pBtCoexist->board_info.btdm_ant_num == 1)
+			ex_halbtc8812a1ant_dbg_control(pBtCoexist, opCode, opLen, pData);
+	}
+#endif
+
+#ifdef CONFIG_RTL8822B
+	else if (IS_HARDWARE_TYPE_8822B(pBtCoexist->Adapter))
+		if(pBtCoexist->board_info.btdm_ant_num == 1)
+			ex_halbtc8822b1ant_dbg_control(pBtCoexist, opCode, opLen, pData);
+#endif
+
+	/*	halbtcoutsrc_NormalLowPower(pBtCoexist); */
+}
+
+#if 0
+VOID
+EXhalbtcoutsrc_AntennaDetection(
+	IN	PBTC_COEXIST			pBtCoexist,
+	IN	u4Byte					centFreq,
+	IN	u4Byte					offset,
+	IN	u4Byte					span,
+	IN	u4Byte					seconds
+)
+{
+	if (!halbtcoutsrc_IsBtCoexistAvailable(pBtCoexist))
+		return;
+
+	/* Need to refine the following power save operations to enable this function in the future */
+#if 0
+	IPSDisable(pBtCoexist->Adapter, FALSE, 0);
+	LeisurePSLeave(pBtCoexist->Adapter, LPS_DISABLE_BT_COEX);
+#endif
+
+	if (IS_HARDWARE_TYPE_8723B(pBtCoexist->Adapter)) {
+		if (pBtCoexist->board_info.btdm_ant_num == 1)
+			ex_halbtc8723b1ant_AntennaDetection(pBtCoexist, centFreq, offset, span, seconds);
+	}
+
+	/* IPSReturn(pBtCoexist->Adapter, 0xff); */
+}
+#endif
+
+void EXhalbtcoutsrc_StackUpdateProfileInfo(void)
+{
+#ifdef CONFIG_BT_COEXIST_SOCKET_TRX
+	PBTC_COEXIST pBtCoexist = &GLBtCoexist;
+	PADAPTER padapter = (PADAPTER)GLBtCoexist.Adapter;
+	PBT_MGNT pBtMgnt = &padapter->coex_info.BtMgnt;
+	u8 i;
+
+	if (!halbtcoutsrc_IsBtCoexistAvailable(pBtCoexist))
+		return;
+
+	pBtCoexist->stack_info.profile_notified = _TRUE;
+
+	pBtCoexist->stack_info.num_of_link =
+		pBtMgnt->ExtConfig.NumberOfACL + pBtMgnt->ExtConfig.NumberOfSCO;
+
+	/* reset first */
+	pBtCoexist->stack_info.bt_link_exist = _FALSE;
+	pBtCoexist->stack_info.sco_exist = _FALSE;
+	pBtCoexist->stack_info.acl_exist = _FALSE;
+	pBtCoexist->stack_info.a2dp_exist = _FALSE;
+	pBtCoexist->stack_info.hid_exist = _FALSE;
+	pBtCoexist->stack_info.num_of_hid = 0;
+	pBtCoexist->stack_info.pan_exist = _FALSE;
+
+	if (!pBtMgnt->ExtConfig.NumberOfACL)
+		pBtCoexist->stack_info.min_bt_rssi = 0;
+
+	if (pBtCoexist->stack_info.num_of_link) {
+		pBtCoexist->stack_info.bt_link_exist = _TRUE;
+		if (pBtMgnt->ExtConfig.NumberOfSCO)
+			pBtCoexist->stack_info.sco_exist = _TRUE;
+		if (pBtMgnt->ExtConfig.NumberOfACL)
+			pBtCoexist->stack_info.acl_exist = _TRUE;
+	}
+
+	for (i = 0; i < pBtMgnt->ExtConfig.NumberOfACL; i++) {
+		if (BT_PROFILE_A2DP == pBtMgnt->ExtConfig.aclLink[i].BTProfile)
+			pBtCoexist->stack_info.a2dp_exist = _TRUE;
+		else if (BT_PROFILE_PAN == pBtMgnt->ExtConfig.aclLink[i].BTProfile)
+			pBtCoexist->stack_info.pan_exist = _TRUE;
+		else if (BT_PROFILE_HID == pBtMgnt->ExtConfig.aclLink[i].BTProfile) {
+			pBtCoexist->stack_info.hid_exist = _TRUE;
+			pBtCoexist->stack_info.num_of_hid++;
+		} else
+			pBtCoexist->stack_info.unknown_acl_exist = _TRUE;
+	}
+#endif /* CONFIG_BT_COEXIST_SOCKET_TRX */
+}
+
+void EXhalbtcoutsrc_UpdateMinBtRssi(s8 btRssi)
+{
+	PBTC_COEXIST pBtCoexist = &GLBtCoexist;
+
+	if (!halbtcoutsrc_IsBtCoexistAvailable(pBtCoexist))
+		return;
+
+	pBtCoexist->stack_info.min_bt_rssi = btRssi;
+}
+
+void EXhalbtcoutsrc_SetHciVersion(u16 hciVersion)
+{
+	PBTC_COEXIST pBtCoexist = &GLBtCoexist;
+
+	if (!halbtcoutsrc_IsBtCoexistAvailable(pBtCoexist))
+		return;
+
+	pBtCoexist->stack_info.hci_version = hciVersion;
+}
+
+void EXhalbtcoutsrc_SetBtPatchVersion(u16 btHciVersion, u16 btPatchVersion)
+{
+	PBTC_COEXIST pBtCoexist = &GLBtCoexist;
+
+	if (!halbtcoutsrc_IsBtCoexistAvailable(pBtCoexist))
+		return;
+
+	pBtCoexist->bt_info.bt_real_fw_ver = btPatchVersion;
+	pBtCoexist->bt_info.bt_hci_ver = btHciVersion;
+}
+
+#if 0
+void EXhalbtcoutsrc_SetBtExist(u8 bBtExist)
+{
+	GLBtCoexist.boardInfo.bBtExist = bBtExist;
+}
+#endif
+void EXhalbtcoutsrc_SetChipType(u8 chipType)
+{
+	switch (chipType) {
+	default:
+	case BT_2WIRE:
+	case BT_ISSC_3WIRE:
+	case BT_ACCEL:
+	case BT_RTL8756:
+		GLBtCoexist.board_info.bt_chip_type = BTC_CHIP_UNDEF;
+		break;
+	case BT_CSR_BC4:
+		GLBtCoexist.board_info.bt_chip_type = BTC_CHIP_CSR_BC4;
+		break;
+	case BT_CSR_BC8:
+		GLBtCoexist.board_info.bt_chip_type = BTC_CHIP_CSR_BC8;
+		break;
+	case BT_RTL8723A:
+		GLBtCoexist.board_info.bt_chip_type = BTC_CHIP_RTL8723A;
+		break;
+	case BT_RTL8821:
+		GLBtCoexist.board_info.bt_chip_type = BTC_CHIP_RTL8821;
+		break;
+	case BT_RTL8723B:
+		GLBtCoexist.board_info.bt_chip_type = BTC_CHIP_RTL8723B;
+		break;
+	}
+}
+
+void EXhalbtcoutsrc_SetAntNum(u8 type, u8 antNum)
+{
+	if (BT_COEX_ANT_TYPE_PG == type) {
+		GLBtCoexist.board_info.pg_ant_num = antNum;
+		GLBtCoexist.board_info.btdm_ant_num = antNum;
+#if 0
+		/* The antenna position: Main (default) or Aux for pgAntNum=2 && btdmAntNum =1 */
+		/* The antenna position should be determined by auto-detect mechanism */
+		/* The following is assumed to main, and those must be modified if y auto-detect mechanism is ready */
+		if ((GLBtCoexist.board_info.pg_ant_num == 2) && (GLBtCoexist.board_info.btdm_ant_num == 1))
+			GLBtCoexist.board_info.btdm_ant_pos = BTC_ANTENNA_AT_MAIN_PORT;
+		else
+			GLBtCoexist.board_info.btdm_ant_pos = BTC_ANTENNA_AT_MAIN_PORT;
+#endif
+	} else if (BT_COEX_ANT_TYPE_ANTDIV == type) {
+		GLBtCoexist.board_info.btdm_ant_num = antNum;
+		/* GLBtCoexist.boardInfo.btdmAntPos = BTC_ANTENNA_AT_MAIN_PORT;	 */
+	} else if (BT_COEX_ANT_TYPE_DETECTED == type) {
+		GLBtCoexist.board_info.btdm_ant_num = antNum;
+		/* GLBtCoexist.boardInfo.btdmAntPos = BTC_ANTENNA_AT_MAIN_PORT; */
+	}
+}
+
+/*
+ * Currently used by 8723b only, S0 or S1
+ *   */
+void EXhalbtcoutsrc_SetSingleAntPath(u8 singleAntPath)
+{
+	GLBtCoexist.board_info.single_ant_path = singleAntPath;
+}
+
+void EXhalbtcoutsrc_DisplayBtCoexInfo(PBTC_COEXIST pBtCoexist)
+{
+	if (!halbtcoutsrc_IsBtCoexistAvailable(pBtCoexist))
+		return;
+
+	halbtcoutsrc_LeaveLowPower(pBtCoexist);
+
+	/* To prevent the racing with IPS enter */
+	halbtcoutsrc_EnterPwrLock(pBtCoexist);
+
+	if (IS_HARDWARE_TYPE_8821(pBtCoexist->Adapter)) {
+#ifdef CONFIG_RTL8821A
+		if (pBtCoexist->board_info.btdm_ant_num == 2)
+			ex_halbtc8821a2ant_display_coex_info(pBtCoexist);
+		else if (pBtCoexist->board_info.btdm_ant_num == 1)
+			ex_halbtc8821a1ant_display_coex_info(pBtCoexist);
+#endif
+	}
+
+#ifdef CONFIG_RTL8723B
+	else if (IS_HARDWARE_TYPE_8723B(pBtCoexist->Adapter)) {
+		if (pBtCoexist->board_info.btdm_ant_num == 2)
+			ex_halbtc8723b2ant_display_coex_info(pBtCoexist);
+		else if (pBtCoexist->board_info.btdm_ant_num == 1)
+			ex_halbtc8723b1ant_display_coex_info(pBtCoexist);
+	}
+#endif
+
+#ifdef CONFIG_RTL8703B
+	else if (IS_HARDWARE_TYPE_8703B(pBtCoexist->Adapter)) {
+		if (pBtCoexist->board_info.btdm_ant_num == 1)
+			ex_halbtc8703b1ant_display_coex_info(pBtCoexist);
+	}
+#endif
+
+#ifdef CONFIG_RTL8723D
+	else if (IS_HARDWARE_TYPE_8723D(pBtCoexist->Adapter)) {
+		if (pBtCoexist->board_info.btdm_ant_num == 2)
+			ex_halbtc8723d2ant_display_coex_info(pBtCoexist);
+		else if (pBtCoexist->board_info.btdm_ant_num == 1)
+			ex_halbtc8723d1ant_display_coex_info(pBtCoexist);
+	}
+#endif
+
+#ifdef CONFIG_RTL8192E
+	else if (IS_HARDWARE_TYPE_8192E(pBtCoexist->Adapter)) {
+		if (pBtCoexist->board_info.btdm_ant_num == 2)
+			ex_halbtc8192e2ant_display_coex_info(pBtCoexist);
+		else if (pBtCoexist->board_info.btdm_ant_num == 1)
+			ex_halbtc8192e1ant_display_coex_info(pBtCoexist);
+	}
+#endif
+
+#ifdef CONFIG_RTL8812A
+	else if (IS_HARDWARE_TYPE_8812(pBtCoexist->Adapter)) {
+		if (pBtCoexist->board_info.btdm_ant_num == 2)
+			ex_halbtc8812a2ant_display_coex_info(pBtCoexist);
+		else if (pBtCoexist->board_info.btdm_ant_num == 1)
+			ex_halbtc8812a1ant_display_coex_info(pBtCoexist);
+	}
+#endif
+
+#ifdef CONFIG_RTL8822B
+	else if (IS_HARDWARE_TYPE_8822B(pBtCoexist->Adapter)) {
+		if (pBtCoexist->board_info.btdm_ant_num == 1)
+			ex_halbtc8822b1ant_display_coex_info(pBtCoexist);
+		else if (pBtCoexist->board_info.btdm_ant_num == 2)
+			ex_halbtc8822b2ant_display_coex_info(pBtCoexist);
+	}
+#endif
+
+#ifdef CONFIG_RTL8821C
+	else if (IS_HARDWARE_TYPE_8821C(pBtCoexist->Adapter)) {
+		if (pBtCoexist->board_info.btdm_ant_num == 2)
+			ex_halbtc8821c2ant_display_coex_info(pBtCoexist);
+		else if (pBtCoexist->board_info.btdm_ant_num == 1)
+			ex_halbtc8821c1ant_display_coex_info(pBtCoexist);
+	}
+#endif
+
+	halbtcoutsrc_ExitPwrLock(pBtCoexist);
+
+	halbtcoutsrc_NormalLowPower(pBtCoexist);
+}
+
+void EXhalbtcoutsrc_DisplayAntDetection(PBTC_COEXIST pBtCoexist)
+{
+	if (!halbtcoutsrc_IsBtCoexistAvailable(pBtCoexist))
+		return;
+
+	halbtcoutsrc_LeaveLowPower(pBtCoexist);
+
+	if (IS_HARDWARE_TYPE_8723B(pBtCoexist->Adapter)) {
+#ifdef CONFIG_RTL8723B
+		if (pBtCoexist->board_info.btdm_ant_num == 1)
+			ex_halbtc8723b1ant_display_ant_detection(pBtCoexist);
+#endif
+	}
+
+	halbtcoutsrc_NormalLowPower(pBtCoexist);
+}
+
+void ex_halbtcoutsrc_pta_off_on_notify(PBTC_COEXIST pBtCoexist, u8 bBTON)
+{
+#ifdef CONFIG_RTL8812A
+	if (IS_HARDWARE_TYPE_8812(pBtCoexist->Adapter)) {
+		if (pBtCoexist->board_info.btdm_ant_num == 2)
+			ex_halbtc8812a2ant_pta_off_on_notify(pBtCoexist, (bBTON == _TRUE) ? BTC_BT_ON : BTC_BT_OFF);
+	}
+#endif
+}
+
+void EXhalbtcoutsrc_set_rfe_type(u8 type)
+{
+	GLBtCoexist.board_info.rfe_type= type;
+}
+
+#ifdef CONFIG_RF4CE_COEXIST
+void EXhalbtcoutsrc_set_rf4ce_link_state(u8 state)
+{
+	GLBtCoexist.rf4ce_info.link_state = state;
+}
+
+u8 EXhalbtcoutsrc_get_rf4ce_link_state(void)
+{
+	return GLBtCoexist.rf4ce_info.link_state;
+}
+#endif
+
+void EXhalbtcoutsrc_switchband_notify(struct btc_coexist *pBtCoexist, u8 type)
+{
+	if(!halbtcoutsrc_IsBtCoexistAvailable(pBtCoexist))
+		return;
+	
+	if(pBtCoexist->manual_control)
+		return;
+
+	/* Driver should guarantee that the HW status isn't in low power mode */
+	/* halbtcoutsrc_LeaveLowPower(pBtCoexist); */
+
+	if(IS_HARDWARE_TYPE_8822B(pBtCoexist->Adapter)) {
+#ifdef CONFIG_RTL8822B
+		if(pBtCoexist->board_info.btdm_ant_num == 1)
+			ex_halbtc8822b1ant_switchband_notify(pBtCoexist, type);
+		else if(pBtCoexist->board_info.btdm_ant_num == 2)
+			ex_halbtc8822b2ant_switchband_notify(pBtCoexist, type);
+#endif
+	}
+
+#ifdef CONFIG_RTL8821C
+	else if (IS_HARDWARE_TYPE_8821C(pBtCoexist->Adapter)) {
+		if (pBtCoexist->board_info.btdm_ant_num == 2)
+			ex_halbtc8821c2ant_switchband_notify(pBtCoexist, type);
+		else if (pBtCoexist->board_info.btdm_ant_num == 1)
+			ex_halbtc8821c1ant_switchband_notify(pBtCoexist, type);
+	}
+#endif
+
+	/* halbtcoutsrc_NormalLowPower(pBtCoexist); */
+}
+
+u8 EXhalbtcoutsrc_rate_id_to_btc_rate_id(u8 rate_id)
+{
+	u8 btc_rate_id = BTC_UNKNOWN;
+
+	switch (rate_id) {
+		/* CCK rates */
+		case DESC_RATE1M:
+			btc_rate_id = BTC_CCK_1;
+			break;
+		case DESC_RATE2M:
+			btc_rate_id = BTC_CCK_2;
+			break;
+		case DESC_RATE5_5M:
+			btc_rate_id = BTC_CCK_5_5;
+			break;
+		case DESC_RATE11M:
+			btc_rate_id = BTC_CCK_11;
+			break;
+
+		/* OFDM rates */
+		case DESC_RATE6M:
+			btc_rate_id = BTC_OFDM_6;
+			break;
+		case DESC_RATE9M:
+			btc_rate_id = BTC_OFDM_9;
+			break;
+		case DESC_RATE12M:
+			btc_rate_id = BTC_OFDM_12;
+			break;
+		case DESC_RATE18M:
+			btc_rate_id = BTC_OFDM_18;
+			break;
+		case DESC_RATE24M:
+			btc_rate_id = BTC_OFDM_24;
+			break;
+		case DESC_RATE36M:
+			btc_rate_id = BTC_OFDM_36;
+			break;
+		case DESC_RATE48M:
+			btc_rate_id = BTC_OFDM_48;
+			break;
+		case DESC_RATE54M:
+			btc_rate_id = BTC_OFDM_54;
+			break;
+
+		/* MCS rates */
+		case DESC_RATEMCS0:
+			btc_rate_id = BTC_MCS_0;
+			break;
+		case DESC_RATEMCS1:
+			btc_rate_id = BTC_MCS_1;
+			break;
+		case DESC_RATEMCS2:
+			btc_rate_id = BTC_MCS_2;
+			break;
+		case DESC_RATEMCS3:
+			btc_rate_id = BTC_MCS_3;
+			break;
+		case DESC_RATEMCS4:
+			btc_rate_id = BTC_MCS_4;
+			break;
+		case DESC_RATEMCS5:
+			btc_rate_id = BTC_MCS_5;
+			break;
+		case DESC_RATEMCS6:
+			btc_rate_id = BTC_MCS_6;
+			break;
+		case DESC_RATEMCS7:
+			btc_rate_id = BTC_MCS_7;
+			break;
+		case DESC_RATEMCS8:
+			btc_rate_id = BTC_MCS_8;
+			break;
+		case DESC_RATEMCS9:
+			btc_rate_id = BTC_MCS_9;
+			break;
+		case DESC_RATEMCS10:
+			btc_rate_id = BTC_MCS_10;
+			break;
+		case DESC_RATEMCS11:
+			btc_rate_id = BTC_MCS_11;
+			break;
+		case DESC_RATEMCS12:
+			btc_rate_id = BTC_MCS_12;
+			break;
+		case DESC_RATEMCS13:
+			btc_rate_id = BTC_MCS_13;
+			break;
+		case DESC_RATEMCS14:
+			btc_rate_id = BTC_MCS_14;
+			break;
+		case DESC_RATEMCS15:
+			btc_rate_id = BTC_MCS_15;
+			break;
+		case DESC_RATEMCS16:
+			btc_rate_id = BTC_MCS_16;
+			break;
+		case DESC_RATEMCS17:
+			btc_rate_id = BTC_MCS_17;
+			break;
+		case DESC_RATEMCS18:
+			btc_rate_id = BTC_MCS_18;
+			break;
+		case DESC_RATEMCS19:
+			btc_rate_id = BTC_MCS_19;
+			break;
+		case DESC_RATEMCS20:
+			btc_rate_id = BTC_MCS_20;
+			break;
+		case DESC_RATEMCS21:
+			btc_rate_id = BTC_MCS_21;
+			break;
+		case DESC_RATEMCS22:
+			btc_rate_id = BTC_MCS_22;
+			break;
+		case DESC_RATEMCS23:
+			btc_rate_id = BTC_MCS_23;
+			break;
+		case DESC_RATEMCS24:
+			btc_rate_id = BTC_MCS_24;
+			break;
+		case DESC_RATEMCS25:
+			btc_rate_id = BTC_MCS_25;
+			break;
+		case DESC_RATEMCS26:
+			btc_rate_id = BTC_MCS_26;
+			break;
+		case DESC_RATEMCS27:
+			btc_rate_id = BTC_MCS_27;
+			break;
+		case DESC_RATEMCS28:
+			btc_rate_id = BTC_MCS_28;
+			break;
+		case DESC_RATEMCS29:
+			btc_rate_id = BTC_MCS_29;
+			break;
+		case DESC_RATEMCS30:
+			btc_rate_id = BTC_MCS_30;
+			break;
+		case DESC_RATEMCS31:
+			btc_rate_id = BTC_MCS_31;
+			break;
+			
+		case DESC_RATEVHTSS1MCS0:
+			btc_rate_id = BTC_VHT_1SS_MCS_0;
+			break;
+		case DESC_RATEVHTSS1MCS1:
+			btc_rate_id = BTC_VHT_1SS_MCS_1;
+			break;
+		case DESC_RATEVHTSS1MCS2:
+			btc_rate_id = BTC_VHT_1SS_MCS_2;
+			break;
+		case DESC_RATEVHTSS1MCS3:
+			btc_rate_id = BTC_VHT_1SS_MCS_3;
+			break;
+		case DESC_RATEVHTSS1MCS4:
+			btc_rate_id = BTC_VHT_1SS_MCS_4;
+			break;
+		case DESC_RATEVHTSS1MCS5:
+			btc_rate_id = BTC_VHT_1SS_MCS_5;
+			break;
+		case DESC_RATEVHTSS1MCS6:
+			btc_rate_id = BTC_VHT_1SS_MCS_6;
+			break;
+		case DESC_RATEVHTSS1MCS7:
+			btc_rate_id = BTC_VHT_1SS_MCS_7;
+			break;
+		case DESC_RATEVHTSS1MCS8:
+			btc_rate_id = BTC_VHT_1SS_MCS_8;
+			break;
+		case DESC_RATEVHTSS1MCS9:
+			btc_rate_id = BTC_VHT_1SS_MCS_9;
+			break;
+
+		case DESC_RATEVHTSS2MCS0:
+			btc_rate_id = BTC_VHT_2SS_MCS_0;
+			break;
+		case DESC_RATEVHTSS2MCS1:
+			btc_rate_id = BTC_VHT_2SS_MCS_1;
+			break;
+		case DESC_RATEVHTSS2MCS2:
+			btc_rate_id = BTC_VHT_2SS_MCS_2;
+			break;
+		case DESC_RATEVHTSS2MCS3:
+			btc_rate_id = BTC_VHT_2SS_MCS_3;
+			break;
+		case DESC_RATEVHTSS2MCS4:
+			btc_rate_id = BTC_VHT_2SS_MCS_4;
+			break;
+		case DESC_RATEVHTSS2MCS5:
+			btc_rate_id = BTC_VHT_2SS_MCS_5;
+			break;
+		case DESC_RATEVHTSS2MCS6:
+			btc_rate_id = BTC_VHT_2SS_MCS_6;
+			break;
+		case DESC_RATEVHTSS2MCS7:
+			btc_rate_id = BTC_VHT_2SS_MCS_7;
+			break;
+		case DESC_RATEVHTSS2MCS8:
+			btc_rate_id = BTC_VHT_2SS_MCS_8;
+			break;
+		case DESC_RATEVHTSS2MCS9:
+			btc_rate_id = BTC_VHT_2SS_MCS_9;
+			break;
+
+		case DESC_RATEVHTSS3MCS0:
+			btc_rate_id = BTC_VHT_3SS_MCS_0;
+			break;
+		case DESC_RATEVHTSS3MCS1:
+			btc_rate_id = BTC_VHT_3SS_MCS_1;
+			break;
+		case DESC_RATEVHTSS3MCS2:
+			btc_rate_id = BTC_VHT_3SS_MCS_2;
+			break;
+		case DESC_RATEVHTSS3MCS3:
+			btc_rate_id = BTC_VHT_3SS_MCS_3;
+			break;
+		case DESC_RATEVHTSS3MCS4:
+			btc_rate_id = BTC_VHT_3SS_MCS_4;
+			break;
+		case DESC_RATEVHTSS3MCS5:
+			btc_rate_id = BTC_VHT_3SS_MCS_5;
+			break;
+		case DESC_RATEVHTSS3MCS6:
+			btc_rate_id = BTC_VHT_3SS_MCS_6;
+			break;
+		case DESC_RATEVHTSS3MCS7:
+			btc_rate_id = BTC_VHT_3SS_MCS_7;
+			break;
+		case DESC_RATEVHTSS3MCS8:
+			btc_rate_id = BTC_VHT_3SS_MCS_8;
+			break;
+		case DESC_RATEVHTSS3MCS9:
+			btc_rate_id = BTC_VHT_3SS_MCS_9;
+			break;
+
+		case DESC_RATEVHTSS4MCS0:
+			btc_rate_id = BTC_VHT_4SS_MCS_0;
+			break;
+		case DESC_RATEVHTSS4MCS1:
+			btc_rate_id = BTC_VHT_4SS_MCS_1;
+			break;
+		case DESC_RATEVHTSS4MCS2:
+			btc_rate_id = BTC_VHT_4SS_MCS_2;
+			break;
+		case DESC_RATEVHTSS4MCS3:
+			btc_rate_id = BTC_VHT_4SS_MCS_3;
+			break;
+		case DESC_RATEVHTSS4MCS4:
+			btc_rate_id = BTC_VHT_4SS_MCS_4;
+			break;
+		case DESC_RATEVHTSS4MCS5:
+			btc_rate_id = BTC_VHT_4SS_MCS_5;
+			break;
+		case DESC_RATEVHTSS4MCS6:
+			btc_rate_id = BTC_VHT_4SS_MCS_6;
+			break;
+		case DESC_RATEVHTSS4MCS7:
+			btc_rate_id = BTC_VHT_4SS_MCS_7;
+			break;
+		case DESC_RATEVHTSS4MCS8:
+			btc_rate_id = BTC_VHT_4SS_MCS_8;
+			break;
+		case DESC_RATEVHTSS4MCS9:
+			btc_rate_id = BTC_VHT_4SS_MCS_9;
+			break;
+	}
+	
+	return btc_rate_id;
+}
+
+static void halbt_init_hw_config92C(PADAPTER padapter)
+{
+	PHAL_DATA_TYPE pHalData;
+	u8 u1Tmp;
+
+
+	pHalData = GET_HAL_DATA(padapter);
+	if ((pHalData->bt_coexist.btChipType == BT_CSR_BC4) ||
+	    (pHalData->bt_coexist.btChipType == BT_CSR_BC8)) {
+		if (pHalData->rf_type == RF_1T1R) {
+			/* Config to 1T1R */
+			u1Tmp = rtw_read8(padapter, rOFDM0_TRxPathEnable);
+			u1Tmp &= ~BIT(1);
+			rtw_write8(padapter, rOFDM0_TRxPathEnable, u1Tmp);
+			RT_DISP(FBT, BT_TRACE, ("[BTCoex], BT write 0xC04 = 0x%x\n", u1Tmp));
+
+			u1Tmp = rtw_read8(padapter, rOFDM1_TRxPathEnable);
+			u1Tmp &= ~BIT(1);
+			rtw_write8(padapter, rOFDM1_TRxPathEnable, u1Tmp);
+			RT_DISP(FBT, BT_TRACE, ("[BTCoex], BT write 0xD04 = 0x%x\n", u1Tmp));
+		}
+	}
+}
+
+static void halbt_init_hw_config92D(PADAPTER padapter)
+{
+	PHAL_DATA_TYPE pHalData;
+	u8 u1Tmp;
+
+	pHalData = GET_HAL_DATA(padapter);
+	if ((pHalData->bt_coexist.btChipType == BT_CSR_BC4) ||
+	    (pHalData->bt_coexist.btChipType == BT_CSR_BC8)) {
+		if (pHalData->rf_type == RF_1T1R) {
+			/* Config to 1T1R */
+			u1Tmp = rtw_read8(padapter, rOFDM0_TRxPathEnable);
+			u1Tmp &= ~BIT(1);
+			rtw_write8(padapter, rOFDM0_TRxPathEnable, u1Tmp);
+			RT_DISP(FBT, BT_TRACE, ("[BTCoex], BT write 0xC04 = 0x%x\n", u1Tmp));
+
+			u1Tmp = rtw_read8(padapter, rOFDM1_TRxPathEnable);
+			u1Tmp &= ~BIT(1);
+			rtw_write8(padapter, rOFDM1_TRxPathEnable, u1Tmp);
+			RT_DISP(FBT, BT_TRACE, ("[BTCoex], BT write 0xD04 = 0x%x\n", u1Tmp));
+		}
+	}
+}
+
+/*
+ * Description:
+ *	Run BT-Coexist mechansim or not
+ *
+ */
+void hal_btcoex_SetBTCoexist(PADAPTER padapter, u8 bBtExist)
+{
+	PHAL_DATA_TYPE	pHalData;
+
+
+	pHalData = GET_HAL_DATA(padapter);
+	pHalData->bt_coexist.bBtExist = bBtExist;
+}
+
+/*
+ * Dewcription:
+ *	Check is co-exist mechanism enabled or not
+ *
+ * Return:
+ *	_TRUE	Enable BT co-exist mechanism
+ *	_FALSE	Disable BT co-exist mechanism
+ */
+u8 hal_btcoex_IsBtExist(PADAPTER padapter)
+{
+	PHAL_DATA_TYPE	pHalData;
+
+
+	pHalData = GET_HAL_DATA(padapter);
+	return pHalData->bt_coexist.bBtExist;
+}
+
+u8 hal_btcoex_IsBtDisabled(PADAPTER padapter)
+{
+	if (!hal_btcoex_IsBtExist(padapter))
+		return _TRUE;
+
+	if (GLBtCoexist.bt_info.bt_disabled)
+		return _TRUE;
+	else
+		return _FALSE;
+}
+
+void hal_btcoex_SetChipType(PADAPTER padapter, u8 chipType)
+{
+	PHAL_DATA_TYPE	pHalData;
+
+	pHalData = GET_HAL_DATA(padapter);
+	pHalData->bt_coexist.btChipType = chipType;
+}
+
+void hal_btcoex_SetPgAntNum(PADAPTER padapter, u8 antNum)
+{
+	PHAL_DATA_TYPE	pHalData;
+
+	pHalData = GET_HAL_DATA(padapter);
+
+	pHalData->bt_coexist.btTotalAntNum = antNum;
+}
+
+u8 hal_btcoex_Initialize(PADAPTER padapter)
+{
+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(padapter);
+	u8 ret;
+
+	_rtw_memset(&GLBtCoexist, 0, sizeof(GLBtCoexist));
+
+	ret = EXhalbtcoutsrc_InitlizeVariables((void *)padapter);
+
+	return ret;
+}
+
+void hal_btcoex_PowerOnSetting(PADAPTER padapter)
+{
+	EXhalbtcoutsrc_PowerOnSetting(&GLBtCoexist);
+}
+
+void hal_btcoex_AntInfoSetting(PADAPTER padapter)
+{
+	hal_btcoex_SetBTCoexist(padapter, rtw_btcoex_get_bt_coexist(padapter));
+	hal_btcoex_SetChipType(padapter, rtw_btcoex_get_chip_type(padapter));
+	hal_btcoex_SetPgAntNum(padapter, rtw_btcoex_get_pg_ant_num(padapter));
+
+	EXhalbtcoutsrc_AntInfoSetting(padapter);
+}
+
+void hal_btcoex_PowerOffSetting(PADAPTER padapter)
+{
+	/* Clear the WiFi on/off bit in scoreboard reg. if necessary */
+	if (IS_HARDWARE_TYPE_8703B(padapter) || IS_HARDWARE_TYPE_8723D(padapter)
+		|| IS_HARDWARE_TYPE_8821C(padapter) || IS_HARDWARE_TYPE_8822B(padapter))
+		rtw_write16(padapter, 0xaa, 0x8000);
+}
+
+void hal_btcoex_PreLoadFirmware(PADAPTER padapter)
+{
+	EXhalbtcoutsrc_PreLoadFirmware(&GLBtCoexist);
+}
+
+void hal_btcoex_InitHwConfig(PADAPTER padapter, u8 bWifiOnly)
+{
+	if (!hal_btcoex_IsBtExist(padapter))
+		return;
+
+	EXhalbtcoutsrc_init_hw_config(&GLBtCoexist, bWifiOnly);
+	EXhalbtcoutsrc_init_coex_dm(&GLBtCoexist);
+}
+
+void hal_btcoex_IpsNotify(PADAPTER padapter, u8 type)
+{
+	EXhalbtcoutsrc_ips_notify(&GLBtCoexist, type);
+}
+
+void hal_btcoex_LpsNotify(PADAPTER padapter, u8 type)
+{
+	EXhalbtcoutsrc_lps_notify(&GLBtCoexist, type);
+}
+
+void hal_btcoex_ScanNotify(PADAPTER padapter, u8 type)
+{
+	EXhalbtcoutsrc_scan_notify(&GLBtCoexist, type);
+}
+
+void hal_btcoex_ConnectNotify(PADAPTER padapter, u8 action)
+{
+	u8 assoType = 0;
+	u8 is_5g_band = _FALSE;
+
+	is_5g_band = (padapter->mlmeextpriv.cur_channel > 14) ? _TRUE : _FALSE;
+
+	if (action == _TRUE) {
+		if (is_5g_band == _TRUE)
+			assoType = BTC_ASSOCIATE_5G_START;
+		else
+			assoType = BTC_ASSOCIATE_START;
+	}
+	else {
+		if (is_5g_band == _TRUE)
+			assoType = BTC_ASSOCIATE_5G_FINISH;
+		else
+			assoType = BTC_ASSOCIATE_FINISH;
+	}
+	
+	EXhalbtcoutsrc_connect_notify(&GLBtCoexist, assoType);
+}
+
+void hal_btcoex_MediaStatusNotify(PADAPTER padapter, u8 mediaStatus)
+{
+	EXhalbtcoutsrc_media_status_notify(&GLBtCoexist, mediaStatus);
+}
+
+void hal_btcoex_SpecialPacketNotify(PADAPTER padapter, u8 pktType)
+{
+	EXhalbtcoutsrc_specific_packet_notify(&GLBtCoexist, pktType);
+}
+
+void hal_btcoex_IQKNotify(PADAPTER padapter, u8 state)
+{
+	GLBtcWiFiInIQKState = state;
+}
+
+void hal_btcoex_BtInfoNotify(PADAPTER padapter, u8 length, u8 *tmpBuf)
+{
+	if (GLBtcWiFiInIQKState == _TRUE)
+		return;
+
+	EXhalbtcoutsrc_bt_info_notify(&GLBtCoexist, tmpBuf, length);
+}
+
+void hal_btcoex_BtMpRptNotify(PADAPTER padapter, u8 length, u8 *tmpBuf)
+{
+	u8 extid, status, len, seq;
+
+
+	if (GLBtcBtMpRptWait == _FALSE)
+		return;
+
+	if ((length < 3) || (!tmpBuf))
+		return;
+
+	extid = tmpBuf[0];
+	/* not response from BT FW then exit*/
+	switch (extid) {
+	case C2H_WIFI_FW_ACTIVE_RSP:
+		GLBtcBtMpRptWiFiOK = _TRUE;
+		break;
+
+	case C2H_TRIG_BY_BT_FW:
+		GLBtcBtMpRptBTOK = _TRUE;
+
+		status = tmpBuf[1] & 0xF;
+		len = length - 3;
+		seq = tmpBuf[2] >> 4;
+
+		GLBtcBtMpRptSeq = seq;
+		GLBtcBtMpRptStatus = status;
+		_rtw_memcpy(GLBtcBtMpRptRsp, tmpBuf + 3, len);
+		GLBtcBtMpRptRspSize = len;
+
+		break;
+
+	default:
+		return;
+	}
+
+	if ((GLBtcBtMpRptWiFiOK == _TRUE) && (GLBtcBtMpRptBTOK == _TRUE)) {
+		GLBtcBtMpRptWait = _FALSE;
+		_cancel_timer_ex(&GLBtcBtMpOperTimer);
+		_rtw_up_sema(&GLBtcBtMpRptSema);
+	}
+}
+
+void hal_btcoex_SuspendNotify(PADAPTER padapter, u8 state)
+{
+	switch (state) {
+	case BTCOEX_SUSPEND_STATE_SUSPEND:
+		EXhalbtcoutsrc_pnp_notify(&GLBtCoexist, BTC_WIFI_PNP_SLEEP);
+		break;
+	case BTCOEX_SUSPEND_STATE_SUSPEND_KEEP_ANT:
+		/* should switch to "#if 1" once all ICs' coex. revision are upgraded to support the KEEP_ANT case */
+#if 0
+		EXhalbtcoutsrc_pnp_notify(&GLBtCoexist, BTC_WIFI_PNP_SLEEP_KEEP_ANT);
+#else
+		EXhalbtcoutsrc_pnp_notify(&GLBtCoexist, BTC_WIFI_PNP_SLEEP);
+		EXhalbtcoutsrc_pnp_notify(&GLBtCoexist, BTC_WIFI_PNP_SLEEP_KEEP_ANT);
+#endif
+		break;
+	case BTCOEX_SUSPEND_STATE_RESUME:
+#ifdef CONFIG_FW_MULTI_PORT_SUPPORT
+		/* re-download FW after resume, inform WL FW port number */
+		rtw_hal_set_wifi_btc_port_id_cmd(GLBtCoexist.Adapter);
+#endif
+		EXhalbtcoutsrc_pnp_notify(&GLBtCoexist, BTC_WIFI_PNP_WAKE_UP);
+		break;
+	}
+}
+
+void hal_btcoex_HaltNotify(PADAPTER padapter, u8 do_halt)
+{
+	if (do_halt == 1)
+		EXhalbtcoutsrc_halt_notify(&GLBtCoexist);
+
+	GLBtCoexist.bBinded = _FALSE;
+	GLBtCoexist.Adapter = NULL;
+}
+
+void hal_btcoex_SwitchBtTRxMask(PADAPTER padapter)
+{
+	EXhalbtcoutsrc_SwitchBtTRxMask(&GLBtCoexist);
+}
+
+void hal_btcoex_Hanlder(PADAPTER padapter)
+{
+	u32	bt_patch_ver;
+
+	EXhalbtcoutsrc_periodical(&GLBtCoexist);
+
+	if (GLBtCoexist.bt_info.bt_get_fw_ver == 0) {
+		GLBtCoexist.btc_get(&GLBtCoexist, BTC_GET_U4_BT_PATCH_VER, &bt_patch_ver);
+		GLBtCoexist.bt_info.bt_get_fw_ver = bt_patch_ver;
+	}
+}
+
+s32 hal_btcoex_IsBTCoexRejectAMPDU(PADAPTER padapter)
+{
+	return (s32)GLBtCoexist.bt_info.reject_agg_pkt;
+}
+
+s32 hal_btcoex_IsBTCoexCtrlAMPDUSize(PADAPTER padapter)
+{
+	return (s32)GLBtCoexist.bt_info.bt_ctrl_agg_buf_size;
+}
+
+u32 hal_btcoex_GetAMPDUSize(PADAPTER padapter)
+{
+	return (u32)GLBtCoexist.bt_info.agg_buf_size;
+}
+
+void hal_btcoex_SetManualControl(PADAPTER padapter, u8 bmanual)
+{
+	GLBtCoexist.manual_control = bmanual;
+}
+
+u8 hal_btcoex_1Ant(PADAPTER padapter)
+{
+	if (hal_btcoex_IsBtExist(padapter) == _FALSE)
+		return _FALSE;
+
+	if (GLBtCoexist.board_info.btdm_ant_num == 1)
+		return _TRUE;
+
+	return _FALSE;
+}
+
+u8 hal_btcoex_IsBtControlLps(PADAPTER padapter)
+{
+	if (GLBtCoexist.bdontenterLPS == _TRUE)
+		return _TRUE;
+	
+	if (hal_btcoex_IsBtExist(padapter) == _FALSE)
+		return _FALSE;
+
+	if (GLBtCoexist.bt_info.bt_disabled)
+		return _FALSE;
+
+	if (GLBtCoexist.bt_info.bt_ctrl_lps)
+		return _TRUE;
+
+	return _FALSE;
+}
+
+u8 hal_btcoex_IsLpsOn(PADAPTER padapter)
+{
+	if (GLBtCoexist.bdontenterLPS == _TRUE)
+		return _FALSE;
+	
+	if (hal_btcoex_IsBtExist(padapter) == _FALSE)
+		return _FALSE;
+
+	if (GLBtCoexist.bt_info.bt_disabled)
+		return _FALSE;
+
+	if (GLBtCoexist.bt_info.bt_lps_on)
+		return _TRUE;
+
+	return _FALSE;
+}
+
+u8 hal_btcoex_RpwmVal(PADAPTER padapter)
+{
+	return GLBtCoexist.bt_info.rpwm_val;
+}
+
+u8 hal_btcoex_LpsVal(PADAPTER padapter)
+{
+	return GLBtCoexist.bt_info.lps_val;
+}
+
+u32 hal_btcoex_GetRaMask(PADAPTER padapter)
+{
+	if (!hal_btcoex_IsBtExist(padapter))
+		return 0;
+
+	if (GLBtCoexist.bt_info.bt_disabled)
+		return 0;
+
+	/* Modify by YiWei , suggest by Cosa and Jenyu
+	 * Remove the limit antenna number , because 2 antenna case (ex: 8192eu)also want to get BT coex report rate mask.
+	 */
+	/*if (GLBtCoexist.board_info.btdm_ant_num != 1)
+		return 0;*/
+
+	return GLBtCoexist.bt_info.ra_mask;
+}
+
+void hal_btcoex_RecordPwrMode(PADAPTER padapter, u8 *pCmdBuf, u8 cmdLen)
+{
+
+	_rtw_memcpy(GLBtCoexist.pwrModeVal, pCmdBuf, cmdLen);
+}
+
+void hal_btcoex_DisplayBtCoexInfo(PADAPTER padapter, u8 *pbuf, u32 bufsize)
+{
+	PBTCDBGINFO pinfo;
+
+
+	pinfo = &GLBtcDbgInfo;
+	DBG_BT_INFO_INIT(pinfo, pbuf, bufsize);
+	EXhalbtcoutsrc_DisplayBtCoexInfo(&GLBtCoexist);
+	DBG_BT_INFO_INIT(pinfo, NULL, 0);
+}
+
+void hal_btcoex_SetDBG(PADAPTER padapter, u32 *pDbgModule)
+{
+	u32 i;
+
+
+	if (NULL == pDbgModule)
+		return;
+
+	for (i = 0; i < COMP_MAX; i++)
+		GLBtcDbgType[i] = pDbgModule[i];
+}
+
+u32 hal_btcoex_GetDBG(PADAPTER padapter, u8 *pStrBuf, u32 bufSize)
+{
+	s32 count;
+	u8 *pstr;
+	u32 leftSize;
+
+
+	if ((NULL == pStrBuf) || (0 == bufSize))
+		return 0;
+
+	count = 0;
+	pstr = pStrBuf;
+	leftSize = bufSize;
+	/*	RTW_INFO(FUNC_ADPT_FMT ": bufsize=%d\n", FUNC_ADPT_ARG(padapter), bufSize); */
+
+	count = rtw_sprintf(pstr, leftSize, "#define DBG\t%d\n", DBG);
+	if ((count < 0) || (count >= leftSize))
+		goto exit;
+	pstr += count;
+	leftSize -= count;
+
+	count = rtw_sprintf(pstr, leftSize, "BTCOEX Debug Setting:\n");
+	if ((count < 0) || (count >= leftSize))
+		goto exit;
+	pstr += count;
+	leftSize -= count;
+
+	count = rtw_sprintf(pstr, leftSize,
+			    "COMP_COEX: 0x%08X\n\n",
+			    GLBtcDbgType[COMP_COEX]);
+	if ((count < 0) || (count >= leftSize))
+		goto exit;
+	pstr += count;
+	leftSize -= count;
+
+#if 0
+	count = rtw_sprintf(pstr, leftSize, "INTERFACE Debug Setting Definition:\n");
+	if ((count < 0) || (count >= leftSize))
+		goto exit;
+	pstr += count;
+	leftSize -= count;
+	count = rtw_sprintf(pstr, leftSize, "\tbit[0]=%d for INTF_INIT\n",
+		    GLBtcDbgType[BTC_MSG_INTERFACE] & INTF_INIT ? 1 : 0);
+	if ((count < 0) || (count >= leftSize))
+		goto exit;
+	pstr += count;
+	leftSize -= count;
+	count = rtw_sprintf(pstr, leftSize, "\tbit[2]=%d for INTF_NOTIFY\n\n",
+		    GLBtcDbgType[BTC_MSG_INTERFACE] & INTF_NOTIFY ? 1 : 0);
+	if ((count < 0) || (count >= leftSize))
+		goto exit;
+	pstr += count;
+	leftSize -= count;
+
+	count = rtw_sprintf(pstr, leftSize, "ALGORITHM Debug Setting Definition:\n");
+	if ((count < 0) || (count >= leftSize))
+		goto exit;
+	pstr += count;
+	leftSize -= count;
+	count = rtw_sprintf(pstr, leftSize, "\tbit[0]=%d for BT_RSSI_STATE\n",
+		GLBtcDbgType[BTC_MSG_ALGORITHM] & ALGO_BT_RSSI_STATE ? 1 : 0);
+	if ((count < 0) || (count >= leftSize))
+		goto exit;
+	pstr += count;
+	leftSize -= count;
+	count = rtw_sprintf(pstr, leftSize, "\tbit[1]=%d for WIFI_RSSI_STATE\n",
+		GLBtcDbgType[BTC_MSG_ALGORITHM] & ALGO_WIFI_RSSI_STATE ? 1 : 0);
+	if ((count < 0) || (count >= leftSize))
+		goto exit;
+	pstr += count;
+	leftSize -= count;
+	count = rtw_sprintf(pstr, leftSize, "\tbit[2]=%d for BT_MONITOR\n",
+		    GLBtcDbgType[BTC_MSG_ALGORITHM] & ALGO_BT_MONITOR ? 1 : 0);
+	if ((count < 0) || (count >= leftSize))
+		goto exit;
+	pstr += count;
+	leftSize -= count;
+	count = rtw_sprintf(pstr, leftSize, "\tbit[3]=%d for TRACE\n",
+		    GLBtcDbgType[BTC_MSG_ALGORITHM] & ALGO_TRACE ? 1 : 0);
+	if ((count < 0) || (count >= leftSize))
+		goto exit;
+	pstr += count;
+	leftSize -= count;
+	count = rtw_sprintf(pstr, leftSize, "\tbit[4]=%d for TRACE_FW\n",
+		    GLBtcDbgType[BTC_MSG_ALGORITHM] & ALGO_TRACE_FW ? 1 : 0);
+	if ((count < 0) || (count >= leftSize))
+		goto exit;
+	pstr += count;
+	leftSize -= count;
+	count = rtw_sprintf(pstr, leftSize, "\tbit[5]=%d for TRACE_FW_DETAIL\n",
+		GLBtcDbgType[BTC_MSG_ALGORITHM] & ALGO_TRACE_FW_DETAIL ? 1 : 0);
+	if ((count < 0) || (count >= leftSize))
+		goto exit;
+	pstr += count;
+	leftSize -= count;
+	count = rtw_sprintf(pstr, leftSize, "\tbit[6]=%d for TRACE_FW_EXEC\n",
+		GLBtcDbgType[BTC_MSG_ALGORITHM] & ALGO_TRACE_FW_EXEC ? 1 : 0);
+	if ((count < 0) || (count >= leftSize))
+		goto exit;
+	pstr += count;
+	leftSize -= count;
+	count = rtw_sprintf(pstr, leftSize, "\tbit[7]=%d for TRACE_SW\n",
+		    GLBtcDbgType[BTC_MSG_ALGORITHM] & ALGO_TRACE_SW ? 1 : 0);
+	if ((count < 0) || (count >= leftSize))
+		goto exit;
+	pstr += count;
+	leftSize -= count;
+	count = rtw_sprintf(pstr, leftSize, "\tbit[8]=%d for TRACE_SW_DETAIL\n",
+		GLBtcDbgType[BTC_MSG_ALGORITHM] & ALGO_TRACE_SW_DETAIL ? 1 : 0);
+	if ((count < 0) || (count >= leftSize))
+		goto exit;
+	pstr += count;
+	leftSize -= count;
+	count = rtw_sprintf(pstr, leftSize, "\tbit[9]=%d for TRACE_SW_EXEC\n",
+		GLBtcDbgType[BTC_MSG_ALGORITHM] & ALGO_TRACE_SW_EXEC ? 1 : 0);
+	if ((count < 0) || (count >= leftSize))
+		goto exit;
+	pstr += count;
+	leftSize -= count;
+#endif
+
+exit:
+	count = pstr - pStrBuf;
+	/*	RTW_INFO(FUNC_ADPT_FMT ": usedsize=%d\n", FUNC_ADPT_ARG(padapter), count); */
+
+	return count;
+}
+
+u8 hal_btcoex_IncreaseScanDeviceNum(PADAPTER padapter)
+{
+	if (!hal_btcoex_IsBtExist(padapter))
+		return _FALSE;
+
+	if (GLBtCoexist.bt_info.increase_scan_dev_num)
+		return _TRUE;
+
+	return _FALSE;
+}
+
+u8 hal_btcoex_IsBtLinkExist(PADAPTER padapter)
+{
+	if (GLBtCoexist.bt_link_info.bt_link_exist)
+		return _TRUE;
+
+	return _FALSE;
+}
+
+void hal_btcoex_SetBtPatchVersion(PADAPTER padapter, u16 btHciVer, u16 btPatchVer)
+{
+	EXhalbtcoutsrc_SetBtPatchVersion(btHciVer, btPatchVer);
+}
+
+void hal_btcoex_SetHciVersion(PADAPTER padapter, u16 hciVersion)
+{
+	EXhalbtcoutsrc_SetHciVersion(hciVersion);
+}
+
+void hal_btcoex_StackUpdateProfileInfo(void)
+{
+	EXhalbtcoutsrc_StackUpdateProfileInfo();
+}
+
+void hal_btcoex_pta_off_on_notify(PADAPTER padapter, u8 bBTON)
+{
+	ex_halbtcoutsrc_pta_off_on_notify(&GLBtCoexist, bBTON);
+}
+
+/*
+ *	Description:
+ *	Setting BT coex antenna isolation type .
+ *	coex mechanisn/ spital stream/ best throughput
+ *	anttype = 0	,	PSTDMA	/	2SS	/	0.5T	,	bad isolation , WiFi/BT ANT Distance<15cm , (<20dB) for 2,3 antenna
+ *	anttype = 1	,	PSTDMA	/	1SS	/	0.5T	,	normal isolaiton , 50cm>WiFi/BT ANT Distance>15cm , (>20dB) for 2 antenna
+ *	anttype = 2	,	TDMA	/	2SS	/	T ,		normal isolaiton , 50cm>WiFi/BT ANT Distance>15cm , (>20dB) for 3 antenna
+ *	anttype = 3	,	no TDMA	/	1SS	/	0.5T	,	good isolation , WiFi/BT ANT Distance >50cm , (>40dB) for 2 antenna
+ *	anttype = 4	,	no TDMA	/	2SS	/	T ,		good isolation , WiFi/BT ANT Distance >50cm , (>40dB) for 3 antenna
+ *	wifi only throughput ~ T
+ *	wifi/BT share one antenna with SPDT
+ */
+void hal_btcoex_SetAntIsolationType(PADAPTER padapter, u8 anttype)
+{
+	PHAL_DATA_TYPE pHalData;
+	PBTC_COEXIST	pBtCoexist = &GLBtCoexist;
+
+	/*RTW_INFO("####%s , anttype = %d  , %d\n" , __func__ , anttype , __LINE__); */
+	pHalData = GET_HAL_DATA(padapter);
+
+
+	pHalData->bt_coexist.btAntisolation = anttype;
+
+	switch (pHalData->bt_coexist.btAntisolation) {
+	case 0:
+		pBtCoexist->board_info.ant_type = (u1Byte)BTC_ANT_TYPE_0;
+		break;
+	case 1:
+		pBtCoexist->board_info.ant_type = (u1Byte)BTC_ANT_TYPE_1;
+		break;
+	case 2:
+		pBtCoexist->board_info.ant_type = (u1Byte)BTC_ANT_TYPE_2;
+		break;
+	case 3:
+		pBtCoexist->board_info.ant_type = (u1Byte)BTC_ANT_TYPE_3;
+		break;
+	case 4:
+		pBtCoexist->board_info.ant_type = (u1Byte)BTC_ANT_TYPE_4;
+		break;
+	}
+
+}
+
+#ifdef CONFIG_LOAD_PHY_PARA_FROM_FILE
+int
+hal_btcoex_ParseAntIsolationConfigFile(
+	PADAPTER		Adapter,
+	char			*buffer
+)
+{
+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(Adapter);
+	u32	i = 0 , j = 0;
+	char	*szLine , *ptmp;
+	int rtStatus = _SUCCESS;
+	char param_value_string[10];
+	u8 param_value;
+	u8 anttype = 4;
+
+	u8 ant_num = 3 , ant_distance = 50 , rfe_type = 1;
+
+	typedef struct ant_isolation {
+		char *param_name;  /* antenna isolation config parameter name */
+		u8 *value; /* antenna isolation config parameter value */
+	} ANT_ISOLATION;
+
+	ANT_ISOLATION ant_isolation_param[] = {
+		{"ANT_NUMBER" , &ant_num},
+		{"ANT_DISTANCE" , &ant_distance},
+		{"RFE_TYPE" , &rfe_type},
+		{NULL , 0}
+	};
+
+
+
+	/* RTW_INFO("===>Hal_ParseAntIsolationConfigFile()\n" ); */
+
+	ptmp = buffer;
+	for (szLine = GetLineFromBuffer(ptmp) ; szLine != NULL; szLine = GetLineFromBuffer(ptmp)) {
+		/* skip comment */
+		if (IsCommentString(szLine))
+			continue;
+
+		/* RTW_INFO("%s : szLine = %s , strlen(szLine) = %d\n" , __func__ , szLine , strlen(szLine));*/
+		for (j = 0 ; ant_isolation_param[j].param_name != NULL ; j++) {
+			if (strstr(szLine , ant_isolation_param[j].param_name) != NULL) {
+				i = 0;
+				while (i < strlen(szLine)) {
+					if (szLine[i] != '"')
+						++i;
+					else {
+						/* skip only has one " */
+						if (strpbrk(szLine , "\"") == strrchr(szLine , '"')) {
+							RTW_INFO("Fail to parse parameters , format error!\n");
+							break;
+						}
+						_rtw_memset((PVOID)param_value_string , 0 , 10);
+						if (!ParseQualifiedString(szLine , &i , param_value_string , '"' , '"')) {
+							RTW_INFO("Fail to parse parameters\n");
+							return _FAIL;
+						} else if (!GetU1ByteIntegerFromStringInDecimal(param_value_string , ant_isolation_param[j].value))
+							RTW_INFO("Fail to GetU1ByteIntegerFromStringInDecimal\n");
+
+						break;
+					}
+				}
+			}
+		}
+	}
+
+	/* YiWei 20140716 , for BT coex antenna isolation control */
+	/* rfe_type = 0 was SPDT , rfe_type = 1 was coupler */
+	if (ant_num == 3 && ant_distance >= 50)
+		anttype = 3;
+	else if (ant_num == 2 && ant_distance >= 50 && rfe_type == 1)
+		anttype = 2;
+	else if (ant_num == 3 && ant_distance >= 15 && ant_distance < 50)
+		anttype = 2;
+	else if (ant_num == 2 && ant_distance >= 15 && ant_distance < 50 && rfe_type == 1)
+		anttype = 2;
+	else if ((ant_num == 2 && ant_distance < 15 && rfe_type == 1) || (ant_num == 3 && ant_distance < 15))
+		anttype = 1;
+	else if (ant_num == 2 && rfe_type == 0)
+		anttype = 0;
+	else
+		anttype = 0;
+
+	hal_btcoex_SetAntIsolationType(Adapter, anttype);
+
+	RTW_INFO("%s : ant_num = %d\n" , __func__ , ant_num);
+	RTW_INFO("%s : ant_distance = %d\n" , __func__ , ant_distance);
+	RTW_INFO("%s : rfe_type = %d\n" , __func__ , rfe_type);
+	/* RTW_INFO("<===Hal_ParseAntIsolationConfigFile()\n"); */
+	return rtStatus;
+}
+
+
+int
+hal_btcoex_AntIsolationConfig_ParaFile(
+	IN	PADAPTER	Adapter,
+	IN	char		*pFileName
+)
+{
+	HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
+	int	rlen = 0 , rtStatus = _FAIL;
+
+	_rtw_memset(pHalData->para_file_buf , 0 , MAX_PARA_FILE_BUF_LEN);
+
+	rtw_get_phy_file_path(Adapter, pFileName);
+	if (rtw_is_file_readable(rtw_phy_para_file_path) == _TRUE) {
+		rlen = rtw_retrieve_from_file(rtw_phy_para_file_path, pHalData->para_file_buf, MAX_PARA_FILE_BUF_LEN);
+		if (rlen > 0)
+			rtStatus = _SUCCESS;
+	}
+
+
+	if (rtStatus == _SUCCESS) {
+		/*RTW_INFO("%s(): read %s ok\n", __func__ , pFileName);*/
+		rtStatus = hal_btcoex_ParseAntIsolationConfigFile(Adapter , pHalData->para_file_buf);
+	} else
+		RTW_INFO("%s(): No File %s, Load from *** Array!\n" , __func__ , pFileName);
+
+	return rtStatus;
+}
+#endif /* CONFIG_LOAD_PHY_PARA_FROM_FILE */
+
+u16 hal_btcoex_btreg_read(PADAPTER padapter, u8 type, u16 addr, u32 *data)
+{
+	u16 ret = 0;
+
+	halbtcoutsrc_LeaveLowPower(&GLBtCoexist);
+
+	ret = halbtcoutsrc_GetBtReg_with_status(&GLBtCoexist, type, addr, data);
+
+	halbtcoutsrc_NormalLowPower(&GLBtCoexist);
+
+	return ret;
+}
+
+u16 hal_btcoex_btreg_write(PADAPTER padapter, u8 type, u16 addr, u16 val)
+{
+	u16 ret = 0;
+
+	halbtcoutsrc_LeaveLowPower(&GLBtCoexist);
+
+	ret = halbtcoutsrc_SetBtReg(&GLBtCoexist, type, addr, val);
+
+	halbtcoutsrc_NormalLowPower(&GLBtCoexist);
+
+	return ret;
+}
+
+void hal_btcoex_set_rfe_type(u8 type)
+{
+	EXhalbtcoutsrc_set_rfe_type(type);
+}
+
+#ifdef CONFIG_RF4CE_COEXIST
+void hal_btcoex_set_rf4ce_link_state(u8 state)
+{
+	EXhalbtcoutsrc_set_rf4ce_link_state(state);
+}
+
+u8 hal_btcoex_get_rf4ce_link_state(void)
+{
+	return EXhalbtcoutsrc_get_rf4ce_link_state();
+}
+#endif /* CONFIG_RF4CE_COEXIST */
+
+void hal_btcoex_switchband_notify(u8 under_scan, u8 band_type)
+{
+	switch (band_type) {
+	case BAND_ON_2_4G:
+		if (under_scan)
+			EXhalbtcoutsrc_switchband_notify(&GLBtCoexist, BTC_SWITCH_TO_24G);
+		else
+			EXhalbtcoutsrc_switchband_notify(&GLBtCoexist, BTC_SWITCH_TO_24G_NOFORSCAN);
+		break;
+	case BAND_ON_5G:
+		EXhalbtcoutsrc_switchband_notify(&GLBtCoexist, BTC_SWITCH_TO_5G);
+		break;
+	default:
+		RTW_INFO("[BTCOEX] unkown switch band type\n");
+		break;
+	}
+}
+
+void hal_btcoex_WlFwDbgInfoNotify(PADAPTER padapter, u8* tmpBuf, u8 length)
+{
+	EXhalbtcoutsrc_WlFwDbgInfoNotify(&GLBtCoexist, tmpBuf, length);
+}
+
+void hal_btcoex_rx_rate_change_notify(PADAPTER padapter, u8 is_data_frame, u8 rate_id)
+{
+	EXhalbtcoutsrc_rx_rate_change_notify(&GLBtCoexist, is_data_frame, EXhalbtcoutsrc_rate_id_to_btc_rate_id(rate_id));
+}
+#endif /* CONFIG_BT_COEXIST */
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/hal_btcoex_wifionly.c linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/hal_btcoex_wifionly.c
--- linux-5.6.3/3rdparty/rtl8821ce/hal/hal_btcoex_wifionly.c	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/hal_btcoex_wifionly.c	2020-04-10 16:35:06.787658714 +0300
@@ -0,0 +1,224 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2016 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#include <hal_btcoex_wifionly.h>
+
+#if (CONFIG_BTCOEX_SUPPORT_WIFI_ONLY_CFG == 1)
+
+#include "btc/mp_precomp.h"
+
+struct  wifi_only_cfg GLBtCoexistWifiOnly;
+
+void halwifionly_write1byte(PVOID pwifionlyContext, u32 RegAddr, u8 Data)
+{
+	struct wifi_only_cfg *pwifionlycfg = (struct wifi_only_cfg *)pwifionlyContext;
+	PADAPTER		Adapter = pwifionlycfg->Adapter;
+
+	rtw_write8(Adapter, RegAddr, Data);
+}
+
+void halwifionly_write2byte(PVOID pwifionlyContext, u32 RegAddr, u16 Data)
+{
+	struct wifi_only_cfg *pwifionlycfg = (struct wifi_only_cfg *)pwifionlyContext;
+	PADAPTER		Adapter = pwifionlycfg->Adapter;
+
+	rtw_write16(Adapter, RegAddr, Data);
+}
+
+void halwifionly_write4byte(PVOID pwifionlyContext, u32 RegAddr, u32 Data)
+{
+	struct wifi_only_cfg *pwifionlycfg = (struct wifi_only_cfg *)pwifionlyContext;
+	PADAPTER		Adapter = pwifionlycfg->Adapter;
+
+	rtw_write32(Adapter, RegAddr, Data);
+}
+
+u8 halwifionly_read1byte(PVOID pwifionlyContext, u32 RegAddr)
+{
+	struct wifi_only_cfg *pwifionlycfg = (struct wifi_only_cfg *)pwifionlyContext;
+	PADAPTER		Adapter = pwifionlycfg->Adapter;
+
+	return rtw_read8(Adapter, RegAddr);
+}
+
+u16 halwifionly_read2byte(PVOID pwifionlyContext, u32 RegAddr)
+{
+	struct wifi_only_cfg *pwifionlycfg = (struct wifi_only_cfg *)pwifionlyContext;
+	PADAPTER		Adapter = pwifionlycfg->Adapter;
+
+	return rtw_read16(Adapter, RegAddr);
+}
+
+u32 halwifionly_read4byte(PVOID pwifionlyContext, u32 RegAddr)
+{
+	struct wifi_only_cfg *pwifionlycfg = (struct wifi_only_cfg *)pwifionlyContext;
+	PADAPTER		Adapter = pwifionlycfg->Adapter;
+
+	return rtw_read32(Adapter, RegAddr);
+}
+
+void halwifionly_bitmaskwrite1byte(PVOID pwifionlyContext, u32 regAddr, u8 bitMask, u8 data)
+{
+	u8 originalValue, bitShift = 0;
+	u8 i;
+
+	struct wifi_only_cfg *pwifionlycfg = (struct wifi_only_cfg *)pwifionlyContext;
+	PADAPTER		Adapter = pwifionlycfg->Adapter;
+
+	if (bitMask != 0xff) {
+		originalValue = rtw_read8(Adapter, regAddr);
+		for (i = 0; i <= 7; i++) {
+			if ((bitMask >> i) & 0x1)
+				break;
+		}
+		bitShift = i;
+		data = ((originalValue) & (~bitMask)) | (((data << bitShift)) & bitMask);
+	}
+	rtw_write8(Adapter, regAddr, data);
+}
+
+void halwifionly_phy_set_rf_reg(PVOID pwifionlyContext, enum rf_path eRFPath, u32 RegAddr, u32 BitMask, u32 Data)
+{
+	struct wifi_only_cfg *pwifionlycfg = (struct wifi_only_cfg *)pwifionlyContext;
+	PADAPTER		Adapter = pwifionlycfg->Adapter;
+
+	phy_set_rf_reg(Adapter, eRFPath, RegAddr, BitMask, Data);
+}
+
+void halwifionly_phy_set_bb_reg(PVOID pwifionlyContext, u32 RegAddr, u32 BitMask, u32 Data)
+{
+	struct wifi_only_cfg *pwifionlycfg = (struct wifi_only_cfg *)pwifionlyContext;
+	PADAPTER		Adapter = pwifionlycfg->Adapter;
+
+	phy_set_bb_reg(Adapter, RegAddr, BitMask, Data);
+}
+
+void hal_btcoex_wifionly_switchband_notify(PADAPTER padapter)
+{
+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(padapter);
+	u8 is_5g = _FALSE;
+
+	if (pHalData->current_band_type == BAND_ON_5G)
+		is_5g = _TRUE;
+
+	if (IS_HARDWARE_TYPE_8822B(padapter)) {
+#ifdef CONFIG_RTL8822B
+		ex_hal8822b_wifi_only_switchbandnotify(&GLBtCoexistWifiOnly, is_5g);
+#endif
+	}
+
+#ifdef CONFIG_RTL8821C
+	else if (IS_HARDWARE_TYPE_8821C(padapter))
+		ex_hal8821c_wifi_only_switchbandnotify(&GLBtCoexistWifiOnly, is_5g);
+#endif
+}
+
+void hal_btcoex_wifionly_scan_notify(PADAPTER padapter)
+{
+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(padapter);
+	u8 is_5g = _FALSE;
+
+	if (pHalData->current_band_type == BAND_ON_5G)
+		is_5g = _TRUE;
+
+	if (IS_HARDWARE_TYPE_8822B(padapter)) {
+#ifdef CONFIG_RTL8822B
+		ex_hal8822b_wifi_only_scannotify(&GLBtCoexistWifiOnly, is_5g);
+#endif
+	}
+
+#ifdef CONFIG_RTL8821C
+	else if (IS_HARDWARE_TYPE_8821C(padapter))
+		ex_hal8821c_wifi_only_scannotify(&GLBtCoexistWifiOnly, is_5g);
+#endif
+}
+
+void hal_btcoex_wifionly_connect_notify(PADAPTER padapter)
+{
+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(padapter);
+	u8 is_5g = _FALSE;
+
+	if (pHalData->current_band_type == BAND_ON_5G)
+		is_5g = _TRUE;
+
+	if (IS_HARDWARE_TYPE_8822B(padapter)) {
+#ifdef CONFIG_RTL8822B
+		ex_hal8822b_wifi_only_connectnotify(&GLBtCoexistWifiOnly, is_5g);
+#endif
+	}
+
+#ifdef CONFIG_RTL8821C
+	else if (IS_HARDWARE_TYPE_8821C(padapter))
+		ex_hal8821c_wifi_only_connectnotify(&GLBtCoexistWifiOnly, is_5g);
+#endif
+}
+
+void hal_btcoex_wifionly_hw_config(PADAPTER padapter)
+{
+	struct wifi_only_cfg *pwifionlycfg = &GLBtCoexistWifiOnly;
+
+	if (IS_HARDWARE_TYPE_8723B(padapter)) {
+#ifdef CONFIG_RTL8723B
+		ex_hal8723b_wifi_only_hw_config(pwifionlycfg);
+#endif
+	}
+
+#ifdef CONFIG_RTL8822B
+	else if (IS_HARDWARE_TYPE_8822B(padapter))
+		ex_hal8822b_wifi_only_hw_config(pwifionlycfg);
+#endif
+
+#ifdef CONFIG_RTL8821C
+	else if (IS_HARDWARE_TYPE_8821C(padapter))
+		ex_hal8821c_wifi_only_hw_config(pwifionlycfg);
+#endif
+}
+
+void hal_btcoex_wifionly_initlizevariables(PADAPTER padapter)
+{
+	struct wifi_only_cfg		*pwifionlycfg = &GLBtCoexistWifiOnly;
+	struct wifi_only_haldata	*pwifionly_haldata = &pwifionlycfg->haldata_info;
+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(padapter);
+
+	_rtw_memset(&GLBtCoexistWifiOnly, 0, sizeof(GLBtCoexistWifiOnly));
+
+	pwifionlycfg->Adapter = padapter;
+
+#ifdef CONFIG_PCI_HCI
+	pwifionlycfg->chip_interface = WIFIONLY_INTF_PCI;
+#elif defined(CONFIG_USB_HCI)
+	pwifionlycfg->chip_interface = WIFIONLY_INTF_USB;
+#elif defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
+	pwifionlycfg->chip_interface = WIFIONLY_INTF_SDIO;
+#else
+	pwifionlycfg->chip_interface = WIFIONLY_INTF_UNKNOWN;
+#endif
+
+	pwifionly_haldata->customer_id = CUSTOMER_NORMAL;
+}
+
+void hal_btcoex_wifionly_AntInfoSetting(PADAPTER padapter)
+{
+	struct wifi_only_cfg		*pwifionlycfg = &GLBtCoexistWifiOnly;
+	struct wifi_only_haldata	*pwifionly_haldata = &pwifionlycfg->haldata_info;
+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(padapter);
+
+	pwifionly_haldata->efuse_pg_antnum = pHalData->EEPROMBluetoothAntNum;
+	pwifionly_haldata->efuse_pg_antpath = pHalData->ant_path;
+	pwifionly_haldata->rfe_type = pHalData->rfe_type;
+	pwifionly_haldata->ant_div_cfg = pHalData->AntDivCfg;
+}
+
+#endif
+
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/hal_com.c linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/hal_com.c
--- linux-5.6.3/3rdparty/rtl8821ce/hal/hal_com.c	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/hal_com.c	2020-04-10 16:35:06.788658760 +0300
@@ -0,0 +1,14430 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#define _HAL_COM_C_
+
+#include <drv_types.h>
+#include "hal_com_h2c.h"
+
+#include "hal_data.h"
+
+#ifdef RTW_HALMAC
+#include "../../hal/hal_halmac.h"
+#endif
+
+void rtw_dump_fw_info(void *sel, _adapter *adapter)
+{
+	HAL_DATA_TYPE	*hal_data = NULL;
+
+	if (!adapter)
+		return;
+
+	hal_data = GET_HAL_DATA(adapter);
+	if (hal_data->bFWReady)
+		RTW_PRINT_SEL(sel, "FW VER -%d.%d\n", hal_data->firmware_version, hal_data->firmware_sub_version);
+	else
+		RTW_PRINT_SEL(sel, "FW not ready\n");
+}
+
+/* #define CONFIG_GTK_OL_DBG */
+
+/*#define DBG_SEC_CAM_MOVE*/
+#ifdef DBG_SEC_CAM_MOVE
+void rtw_hal_move_sta_gk_to_dk(_adapter *adapter)
+{
+	struct mlme_priv *pmlmepriv = &adapter->mlmepriv;
+	int cam_id, index = 0;
+	u8 *addr = NULL;
+
+	if (!MLME_IS_STA(adapter))
+		return;
+
+	addr = get_bssid(pmlmepriv);
+
+	if (addr == NULL) {
+		RTW_INFO("%s: get bssid MAC addr fail!!\n", __func__);
+		return;
+	}
+
+	rtw_clean_dk_section(adapter);
+
+	do {
+		cam_id = rtw_camid_search(adapter, addr, index, 1);
+
+		if (cam_id == -1)
+			RTW_INFO("%s: cam_id: %d, key_id:%d\n", __func__, cam_id, index);
+		else
+			rtw_sec_cam_swap(adapter, cam_id, index);
+
+		index++;
+	} while (index < 4);
+
+}
+
+void rtw_hal_read_sta_dk_key(_adapter *adapter, u8 key_id)
+{
+	struct security_priv *psecuritypriv = &adapter->securitypriv;
+	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
+	struct cam_ctl_t *cam_ctl = &dvobj->cam_ctl;
+	_irqL irqL;
+	u8 get_key[16];
+
+	_rtw_memset(get_key, 0, sizeof(get_key));
+
+	if (key_id > 4) {
+		RTW_INFO("%s [ERROR] gtk_keyindex:%d invalid\n", __func__, key_id);
+		rtw_warn_on(1);
+		return;
+	}
+	rtw_sec_read_cam_ent(adapter, key_id, NULL, NULL, get_key);
+
+	/*update key into related sw variable*/
+	_enter_critical_bh(&cam_ctl->lock, &irqL);
+	if (_rtw_camid_is_gk(adapter, key_id)) {
+		RTW_INFO("[HW KEY] -Key-id:%d "KEY_FMT"\n", key_id, KEY_ARG(get_key));
+		RTW_INFO("[cam_cache KEY] - Key-id:%d "KEY_FMT"\n", key_id, KEY_ARG(&dvobj->cam_cache[key_id].key));
+	}
+	_exit_critical_bh(&cam_ctl->lock, &irqL);
+
+}
+#endif
+
+
+#ifdef CONFIG_LOAD_PHY_PARA_FROM_FILE
+	char	rtw_phy_para_file_path[PATH_LENGTH_MAX];
+#endif
+
+void dump_chip_info(HAL_VERSION	ChipVersion)
+{
+	int cnt = 0;
+	u8 buf[128] = {0};
+
+	if (IS_8188E(ChipVersion))
+		cnt += sprintf((buf + cnt), "Chip Version Info: CHIP_8188E_");
+	else if (IS_8188F(ChipVersion))
+		cnt += sprintf((buf + cnt), "Chip Version Info: CHIP_8188F_");
+	else if (IS_8188GTV(ChipVersion))
+		cnt += sprintf((buf + cnt), "Chip Version Info: CHIP_8188GTV_");
+	else if (IS_8812_SERIES(ChipVersion))
+		cnt += sprintf((buf + cnt), "Chip Version Info: CHIP_8812_");
+	else if (IS_8192E(ChipVersion))
+		cnt += sprintf((buf + cnt), "Chip Version Info: CHIP_8192E_");
+	else if (IS_8821_SERIES(ChipVersion))
+		cnt += sprintf((buf + cnt), "Chip Version Info: CHIP_8821_");
+	else if (IS_8723B_SERIES(ChipVersion))
+		cnt += sprintf((buf + cnt), "Chip Version Info: CHIP_8723B_");
+	else if (IS_8703B_SERIES(ChipVersion))
+		cnt += sprintf((buf + cnt), "Chip Version Info: CHIP_8703B_");
+	else if (IS_8723D_SERIES(ChipVersion))
+		cnt += sprintf((buf + cnt), "Chip Version Info: CHIP_8723D_");
+	else if (IS_8814A_SERIES(ChipVersion))
+		cnt += sprintf((buf + cnt), "Chip Version Info: CHIP_8814A_");
+	else if (IS_8822B_SERIES(ChipVersion))
+		cnt += sprintf((buf + cnt), "Chip Version Info: CHIP_8822B_");
+	else if (IS_8821C_SERIES(ChipVersion))
+		cnt += sprintf((buf + cnt), "Chip Version Info: CHIP_8821C_");
+	else if (IS_8710B_SERIES(ChipVersion))
+		cnt += sprintf((buf + cnt), "Chip Version Info: CHIP_8710B_");
+	else if (IS_8192F_SERIES(ChipVersion))
+		cnt += sprintf((buf + cnt), "Chip Version Info: CHIP_8192F_");
+
+	else
+		cnt += sprintf((buf + cnt), "Chip Version Info: CHIP_UNKNOWN_");
+
+	cnt += sprintf((buf + cnt), "%s_", IS_NORMAL_CHIP(ChipVersion) ? "Normal_Chip" : "Test_Chip");
+	if (IS_CHIP_VENDOR_TSMC(ChipVersion))
+		cnt += sprintf((buf + cnt), "%s_", "TSMC");
+	else if (IS_CHIP_VENDOR_UMC(ChipVersion))
+		cnt += sprintf((buf + cnt), "%s_", "UMC");
+	else if (IS_CHIP_VENDOR_SMIC(ChipVersion))
+		cnt += sprintf((buf + cnt), "%s_", "SMIC");
+
+	if (IS_A_CUT(ChipVersion))
+		cnt += sprintf((buf + cnt), "A_CUT_");
+	else if (IS_B_CUT(ChipVersion))
+		cnt += sprintf((buf + cnt), "B_CUT_");
+	else if (IS_C_CUT(ChipVersion))
+		cnt += sprintf((buf + cnt), "C_CUT_");
+	else if (IS_D_CUT(ChipVersion))
+		cnt += sprintf((buf + cnt), "D_CUT_");
+	else if (IS_E_CUT(ChipVersion))
+		cnt += sprintf((buf + cnt), "E_CUT_");
+	else if (IS_F_CUT(ChipVersion))
+		cnt += sprintf((buf + cnt), "F_CUT_");
+	else if (IS_I_CUT(ChipVersion))
+		cnt += sprintf((buf + cnt), "I_CUT_");
+	else if (IS_J_CUT(ChipVersion))
+		cnt += sprintf((buf + cnt), "J_CUT_");
+	else if (IS_K_CUT(ChipVersion))
+		cnt += sprintf((buf + cnt), "K_CUT_");
+	else
+		cnt += sprintf((buf + cnt), "UNKNOWN_CUT(%d)_", ChipVersion.CUTVersion);
+
+	if (IS_1T1R(ChipVersion))
+		cnt += sprintf((buf + cnt), "1T1R_");
+	else if (IS_1T2R(ChipVersion))
+		cnt += sprintf((buf + cnt), "1T2R_");
+	else if (IS_2T2R(ChipVersion))
+		cnt += sprintf((buf + cnt), "2T2R_");
+	else if (IS_3T3R(ChipVersion))
+		cnt += sprintf((buf + cnt), "3T3R_");
+	else if (IS_3T4R(ChipVersion))
+		cnt += sprintf((buf + cnt), "3T4R_");
+	else if (IS_4T4R(ChipVersion))
+		cnt += sprintf((buf + cnt), "4T4R_");
+	else
+		cnt += sprintf((buf + cnt), "UNKNOWN_RFTYPE(%d)_", ChipVersion.RFType);
+
+	cnt += sprintf((buf + cnt), "RomVer(%d)\n", ChipVersion.ROMVer);
+
+	RTW_INFO("%s", buf);
+}
+
+u8 rtw_hal_get_port(_adapter *adapter)
+{
+	u8 hw_port = get_hw_port(adapter);
+#ifdef CONFIG_CLIENT_PORT_CFG
+	u8 clt_port = get_clt_port(adapter);
+
+	if (clt_port)
+		hw_port = clt_port;
+
+#ifdef DBG_HW_PORT
+	if (MLME_IS_STA(adapter) && (adapter->client_id != MAX_CLIENT_PORT_NUM)) {
+		if(hw_port == CLT_PORT_INVALID) {
+			RTW_ERR(ADPT_FMT" @@@@@ Client port == 0 @@@@@\n", ADPT_ARG(adapter));
+			rtw_warn_on(1);
+		}
+	}
+	else if (MLME_IS_AP(adapter) || MLME_IS_MESH(adapter)) {
+		if (hw_port != HW_PORT0) {
+			RTW_ERR(ADPT_FMT" @@@@@ AP / MESH port != 0 @@@@@\n", ADPT_ARG(adapter));
+			rtw_warn_on(1);
+		}
+	}
+	if (0)
+		RTW_INFO(ADPT_FMT" - HP:%d,CP:%d\n", ADPT_ARG(adapter), get_hw_port(adapter), get_clt_port(adapter));
+#endif /*DBG_HW_PORT*/
+
+#endif/*CONFIG_CLIENT_PORT_CFG*/
+
+	return hw_port;
+}
+
+void rtw_hal_config_rftype(PADAPTER  padapter)
+{
+	HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
+
+	if (IS_1T1R(pHalData->version_id)) {
+		pHalData->rf_type = RF_1T1R;
+		pHalData->NumTotalRFPath = 1;
+	} else if (IS_2T2R(pHalData->version_id)) {
+		pHalData->rf_type = RF_2T2R;
+		pHalData->NumTotalRFPath = 2;
+	} else if (IS_1T2R(pHalData->version_id)) {
+		pHalData->rf_type = RF_1T2R;
+		pHalData->NumTotalRFPath = 2;
+	} else if (IS_3T3R(pHalData->version_id)) {
+		pHalData->rf_type = RF_3T3R;
+		pHalData->NumTotalRFPath = 3;
+	} else if (IS_4T4R(pHalData->version_id)) {
+		pHalData->rf_type = RF_4T4R;
+		pHalData->NumTotalRFPath = 4;
+	} else {
+		pHalData->rf_type = RF_1T1R;
+		pHalData->NumTotalRFPath = 1;
+	}
+
+	RTW_INFO("%s RF_Type is %d TotalTxPath is %d\n", __FUNCTION__, pHalData->rf_type, pHalData->NumTotalRFPath);
+}
+
+#define	EEPROM_CHANNEL_PLAN_BY_HW_MASK	0x80
+
+/*
+ * Description:
+ *	Use hardware(efuse), driver parameter(registry) and default channel plan
+ *	to decide which one should be used.
+ *
+ * Parameters:
+ *	padapter			pointer of adapter
+ *	hw_alpha2		country code from HW (efuse/eeprom/mapfile)
+ *	hw_chplan		channel plan from HW (efuse/eeprom/mapfile)
+ *						BIT[7] software configure mode; 0:Enable, 1:disable
+ *						BIT[6:0] Channel Plan
+ *	sw_alpha2		country code from HW (registry/module param)
+ *	sw_chplan		channel plan from SW (registry/module param)
+ *	def_chplan		channel plan used when HW/SW both invalid
+ *	AutoLoadFail		efuse autoload fail or not
+ *
+ */
+void hal_com_config_channel_plan(
+	IN	PADAPTER padapter,
+	IN	char *hw_alpha2,
+	IN	u8 hw_chplan,
+	IN	char *sw_alpha2,
+	IN	u8 sw_chplan,
+	IN	u8 def_chplan,
+	IN	BOOLEAN AutoLoadFail
+)
+{
+	struct rf_ctl_t *rfctl = adapter_to_rfctl(padapter);
+	PHAL_DATA_TYPE	pHalData;
+	u8 force_hw_chplan = _FALSE;
+	int chplan = -1;
+	const struct country_chplan *country_ent = NULL, *ent;
+
+	pHalData = GET_HAL_DATA(padapter);
+
+	/* treat 0xFF as invalid value, bypass hw_chplan & force_hw_chplan parsing */
+	if (hw_chplan == 0xFF)
+		goto chk_hw_country_code;
+
+	if (AutoLoadFail == _TRUE)
+		goto chk_sw_config;
+
+#ifndef CONFIG_FORCE_SW_CHANNEL_PLAN
+	if (hw_chplan & EEPROM_CHANNEL_PLAN_BY_HW_MASK)
+		force_hw_chplan = _TRUE;
+#endif
+
+	hw_chplan &= (~EEPROM_CHANNEL_PLAN_BY_HW_MASK);
+
+chk_hw_country_code:
+	if (hw_alpha2 && !IS_ALPHA2_NO_SPECIFIED(hw_alpha2)) {
+		ent = rtw_get_chplan_from_country(hw_alpha2);
+		if (ent) {
+			/* get chplan from hw country code, by pass hw chplan setting */
+			country_ent = ent;
+			chplan = ent->chplan;
+			goto chk_sw_config;
+		} else
+			RTW_PRINT("%s unsupported hw_alpha2:\"%c%c\"\n", __func__, hw_alpha2[0], hw_alpha2[1]);
+	}
+
+	if (rtw_is_channel_plan_valid(hw_chplan))
+		chplan = hw_chplan;
+	else if (force_hw_chplan == _TRUE) {
+		RTW_PRINT("%s unsupported hw_chplan:0x%02X\n", __func__, hw_chplan);
+		/* hw infomaton invalid, refer to sw information */
+		force_hw_chplan = _FALSE;
+	}
+
+chk_sw_config:
+	if (force_hw_chplan == _TRUE)
+		goto done;
+
+	if (sw_alpha2 && !IS_ALPHA2_NO_SPECIFIED(sw_alpha2)) {
+		ent = rtw_get_chplan_from_country(sw_alpha2);
+		if (ent) {
+			/* get chplan from sw country code, by pass sw chplan setting */
+			country_ent = ent;
+			chplan = ent->chplan;
+			goto done;
+		} else
+			RTW_PRINT("%s unsupported sw_alpha2:\"%c%c\"\n", __func__, sw_alpha2[0], sw_alpha2[1]);
+	}
+
+	if (rtw_is_channel_plan_valid(sw_chplan)) {
+		/* cancel hw_alpha2 because chplan is specified by sw_chplan*/
+		country_ent = NULL;
+		chplan = sw_chplan;
+	} else if (sw_chplan != RTW_CHPLAN_UNSPECIFIED)
+		RTW_PRINT("%s unsupported sw_chplan:0x%02X\n", __func__, sw_chplan);
+
+done:
+	if (chplan == -1) {
+		RTW_PRINT("%s use def_chplan:0x%02X\n", __func__, def_chplan);
+		chplan = def_chplan;
+	} else if (country_ent) {
+		RTW_PRINT("%s country code:\"%c%c\" with chplan:0x%02X\n", __func__
+			, country_ent->alpha2[0], country_ent->alpha2[1], country_ent->chplan);
+	} else
+		RTW_PRINT("%s chplan:0x%02X\n", __func__, chplan);
+
+	rfctl->country_ent = country_ent;
+	rfctl->ChannelPlan = chplan;
+	pHalData->bDisableSWChannelPlan = force_hw_chplan;
+}
+
+BOOLEAN
+HAL_IsLegalChannel(
+	IN	PADAPTER	Adapter,
+	IN	u32			Channel
+)
+{
+	BOOLEAN bLegalChannel = _TRUE;
+
+	if (Channel > 14) {
+		if (is_supported_5g(Adapter->registrypriv.wireless_mode) == _FALSE) {
+			bLegalChannel = _FALSE;
+			RTW_INFO("Channel > 14 but wireless_mode do not support 5G\n");
+		}
+	} else if ((Channel <= 14) && (Channel >= 1)) {
+		if (IsSupported24G(Adapter->registrypriv.wireless_mode) == _FALSE) {
+			bLegalChannel = _FALSE;
+			RTW_INFO("(Channel <= 14) && (Channel >=1) but wireless_mode do not support 2.4G\n");
+		}
+	} else {
+		bLegalChannel = _FALSE;
+		RTW_INFO("Channel is Invalid !!!\n");
+	}
+
+	return bLegalChannel;
+}
+
+u8	MRateToHwRate(u8 rate)
+{
+	u8	ret = DESC_RATE1M;
+
+	switch (rate) {
+	case MGN_1M:
+		ret = DESC_RATE1M;
+		break;
+	case MGN_2M:
+		ret = DESC_RATE2M;
+		break;
+	case MGN_5_5M:
+		ret = DESC_RATE5_5M;
+		break;
+	case MGN_11M:
+		ret = DESC_RATE11M;
+		break;
+	case MGN_6M:
+		ret = DESC_RATE6M;
+		break;
+	case MGN_9M:
+		ret = DESC_RATE9M;
+		break;
+	case MGN_12M:
+		ret = DESC_RATE12M;
+		break;
+	case MGN_18M:
+		ret = DESC_RATE18M;
+		break;
+	case MGN_24M:
+		ret = DESC_RATE24M;
+		break;
+	case MGN_36M:
+		ret = DESC_RATE36M;
+		break;
+	case MGN_48M:
+		ret = DESC_RATE48M;
+		break;
+	case MGN_54M:
+		ret = DESC_RATE54M;
+		break;
+
+	case MGN_MCS0:
+		ret = DESC_RATEMCS0;
+		break;
+	case MGN_MCS1:
+		ret = DESC_RATEMCS1;
+		break;
+	case MGN_MCS2:
+		ret = DESC_RATEMCS2;
+		break;
+	case MGN_MCS3:
+		ret = DESC_RATEMCS3;
+		break;
+	case MGN_MCS4:
+		ret = DESC_RATEMCS4;
+		break;
+	case MGN_MCS5:
+		ret = DESC_RATEMCS5;
+		break;
+	case MGN_MCS6:
+		ret = DESC_RATEMCS6;
+		break;
+	case MGN_MCS7:
+		ret = DESC_RATEMCS7;
+		break;
+	case MGN_MCS8:
+		ret = DESC_RATEMCS8;
+		break;
+	case MGN_MCS9:
+		ret = DESC_RATEMCS9;
+		break;
+	case MGN_MCS10:
+		ret = DESC_RATEMCS10;
+		break;
+	case MGN_MCS11:
+		ret = DESC_RATEMCS11;
+		break;
+	case MGN_MCS12:
+		ret = DESC_RATEMCS12;
+		break;
+	case MGN_MCS13:
+		ret = DESC_RATEMCS13;
+		break;
+	case MGN_MCS14:
+		ret = DESC_RATEMCS14;
+		break;
+	case MGN_MCS15:
+		ret = DESC_RATEMCS15;
+		break;
+	case MGN_MCS16:
+		ret = DESC_RATEMCS16;
+		break;
+	case MGN_MCS17:
+		ret = DESC_RATEMCS17;
+		break;
+	case MGN_MCS18:
+		ret = DESC_RATEMCS18;
+		break;
+	case MGN_MCS19:
+		ret = DESC_RATEMCS19;
+		break;
+	case MGN_MCS20:
+		ret = DESC_RATEMCS20;
+		break;
+	case MGN_MCS21:
+		ret = DESC_RATEMCS21;
+		break;
+	case MGN_MCS22:
+		ret = DESC_RATEMCS22;
+		break;
+	case MGN_MCS23:
+		ret = DESC_RATEMCS23;
+		break;
+	case MGN_MCS24:
+		ret = DESC_RATEMCS24;
+		break;
+	case MGN_MCS25:
+		ret = DESC_RATEMCS25;
+		break;
+	case MGN_MCS26:
+		ret = DESC_RATEMCS26;
+		break;
+	case MGN_MCS27:
+		ret = DESC_RATEMCS27;
+		break;
+	case MGN_MCS28:
+		ret = DESC_RATEMCS28;
+		break;
+	case MGN_MCS29:
+		ret = DESC_RATEMCS29;
+		break;
+	case MGN_MCS30:
+		ret = DESC_RATEMCS30;
+		break;
+	case MGN_MCS31:
+		ret = DESC_RATEMCS31;
+		break;
+
+	case MGN_VHT1SS_MCS0:
+		ret = DESC_RATEVHTSS1MCS0;
+		break;
+	case MGN_VHT1SS_MCS1:
+		ret = DESC_RATEVHTSS1MCS1;
+		break;
+	case MGN_VHT1SS_MCS2:
+		ret = DESC_RATEVHTSS1MCS2;
+		break;
+	case MGN_VHT1SS_MCS3:
+		ret = DESC_RATEVHTSS1MCS3;
+		break;
+	case MGN_VHT1SS_MCS4:
+		ret = DESC_RATEVHTSS1MCS4;
+		break;
+	case MGN_VHT1SS_MCS5:
+		ret = DESC_RATEVHTSS1MCS5;
+		break;
+	case MGN_VHT1SS_MCS6:
+		ret = DESC_RATEVHTSS1MCS6;
+		break;
+	case MGN_VHT1SS_MCS7:
+		ret = DESC_RATEVHTSS1MCS7;
+		break;
+	case MGN_VHT1SS_MCS8:
+		ret = DESC_RATEVHTSS1MCS8;
+		break;
+	case MGN_VHT1SS_MCS9:
+		ret = DESC_RATEVHTSS1MCS9;
+		break;
+	case MGN_VHT2SS_MCS0:
+		ret = DESC_RATEVHTSS2MCS0;
+		break;
+	case MGN_VHT2SS_MCS1:
+		ret = DESC_RATEVHTSS2MCS1;
+		break;
+	case MGN_VHT2SS_MCS2:
+		ret = DESC_RATEVHTSS2MCS2;
+		break;
+	case MGN_VHT2SS_MCS3:
+		ret = DESC_RATEVHTSS2MCS3;
+		break;
+	case MGN_VHT2SS_MCS4:
+		ret = DESC_RATEVHTSS2MCS4;
+		break;
+	case MGN_VHT2SS_MCS5:
+		ret = DESC_RATEVHTSS2MCS5;
+		break;
+	case MGN_VHT2SS_MCS6:
+		ret = DESC_RATEVHTSS2MCS6;
+		break;
+	case MGN_VHT2SS_MCS7:
+		ret = DESC_RATEVHTSS2MCS7;
+		break;
+	case MGN_VHT2SS_MCS8:
+		ret = DESC_RATEVHTSS2MCS8;
+		break;
+	case MGN_VHT2SS_MCS9:
+		ret = DESC_RATEVHTSS2MCS9;
+		break;
+	case MGN_VHT3SS_MCS0:
+		ret = DESC_RATEVHTSS3MCS0;
+		break;
+	case MGN_VHT3SS_MCS1:
+		ret = DESC_RATEVHTSS3MCS1;
+		break;
+	case MGN_VHT3SS_MCS2:
+		ret = DESC_RATEVHTSS3MCS2;
+		break;
+	case MGN_VHT3SS_MCS3:
+		ret = DESC_RATEVHTSS3MCS3;
+		break;
+	case MGN_VHT3SS_MCS4:
+		ret = DESC_RATEVHTSS3MCS4;
+		break;
+	case MGN_VHT3SS_MCS5:
+		ret = DESC_RATEVHTSS3MCS5;
+		break;
+	case MGN_VHT3SS_MCS6:
+		ret = DESC_RATEVHTSS3MCS6;
+		break;
+	case MGN_VHT3SS_MCS7:
+		ret = DESC_RATEVHTSS3MCS7;
+		break;
+	case MGN_VHT3SS_MCS8:
+		ret = DESC_RATEVHTSS3MCS8;
+		break;
+	case MGN_VHT3SS_MCS9:
+		ret = DESC_RATEVHTSS3MCS9;
+		break;
+	case MGN_VHT4SS_MCS0:
+		ret = DESC_RATEVHTSS4MCS0;
+		break;
+	case MGN_VHT4SS_MCS1:
+		ret = DESC_RATEVHTSS4MCS1;
+		break;
+	case MGN_VHT4SS_MCS2:
+		ret = DESC_RATEVHTSS4MCS2;
+		break;
+	case MGN_VHT4SS_MCS3:
+		ret = DESC_RATEVHTSS4MCS3;
+		break;
+	case MGN_VHT4SS_MCS4:
+		ret = DESC_RATEVHTSS4MCS4;
+		break;
+	case MGN_VHT4SS_MCS5:
+		ret = DESC_RATEVHTSS4MCS5;
+		break;
+	case MGN_VHT4SS_MCS6:
+		ret = DESC_RATEVHTSS4MCS6;
+		break;
+	case MGN_VHT4SS_MCS7:
+		ret = DESC_RATEVHTSS4MCS7;
+		break;
+	case MGN_VHT4SS_MCS8:
+		ret = DESC_RATEVHTSS4MCS8;
+		break;
+	case MGN_VHT4SS_MCS9:
+		ret = DESC_RATEVHTSS4MCS9;
+		break;
+	default:
+		break;
+	}
+
+	return ret;
+}
+
+u8	hw_rate_to_m_rate(u8 rate)
+{
+	u8	ret_rate = MGN_1M;
+
+	switch (rate) {
+
+	case DESC_RATE1M:
+		ret_rate = MGN_1M;
+		break;
+	case DESC_RATE2M:
+		ret_rate = MGN_2M;
+		break;
+	case DESC_RATE5_5M:
+		ret_rate = MGN_5_5M;
+		break;
+	case DESC_RATE11M:
+		ret_rate = MGN_11M;
+		break;
+	case DESC_RATE6M:
+		ret_rate = MGN_6M;
+		break;
+	case DESC_RATE9M:
+		ret_rate = MGN_9M;
+		break;
+	case DESC_RATE12M:
+		ret_rate = MGN_12M;
+		break;
+	case DESC_RATE18M:
+		ret_rate = MGN_18M;
+		break;
+	case DESC_RATE24M:
+		ret_rate = MGN_24M;
+		break;
+	case DESC_RATE36M:
+		ret_rate = MGN_36M;
+		break;
+	case DESC_RATE48M:
+		ret_rate = MGN_48M;
+		break;
+	case DESC_RATE54M:
+		ret_rate = MGN_54M;
+		break;
+	case DESC_RATEMCS0:
+		ret_rate = MGN_MCS0;
+		break;
+	case DESC_RATEMCS1:
+		ret_rate = MGN_MCS1;
+		break;
+	case DESC_RATEMCS2:
+		ret_rate = MGN_MCS2;
+		break;
+	case DESC_RATEMCS3:
+		ret_rate = MGN_MCS3;
+		break;
+	case DESC_RATEMCS4:
+		ret_rate = MGN_MCS4;
+		break;
+	case DESC_RATEMCS5:
+		ret_rate = MGN_MCS5;
+		break;
+	case DESC_RATEMCS6:
+		ret_rate = MGN_MCS6;
+		break;
+	case DESC_RATEMCS7:
+		ret_rate = MGN_MCS7;
+		break;
+	case DESC_RATEMCS8:
+		ret_rate = MGN_MCS8;
+		break;
+	case DESC_RATEMCS9:
+		ret_rate = MGN_MCS9;
+		break;
+	case DESC_RATEMCS10:
+		ret_rate = MGN_MCS10;
+		break;
+	case DESC_RATEMCS11:
+		ret_rate = MGN_MCS11;
+		break;
+	case DESC_RATEMCS12:
+		ret_rate = MGN_MCS12;
+		break;
+	case DESC_RATEMCS13:
+		ret_rate = MGN_MCS13;
+		break;
+	case DESC_RATEMCS14:
+		ret_rate = MGN_MCS14;
+		break;
+	case DESC_RATEMCS15:
+		ret_rate = MGN_MCS15;
+		break;
+	case DESC_RATEMCS16:
+		ret_rate = MGN_MCS16;
+		break;
+	case DESC_RATEMCS17:
+		ret_rate = MGN_MCS17;
+		break;
+	case DESC_RATEMCS18:
+		ret_rate = MGN_MCS18;
+		break;
+	case DESC_RATEMCS19:
+		ret_rate = MGN_MCS19;
+		break;
+	case DESC_RATEMCS20:
+		ret_rate = MGN_MCS20;
+		break;
+	case DESC_RATEMCS21:
+		ret_rate = MGN_MCS21;
+		break;
+	case DESC_RATEMCS22:
+		ret_rate = MGN_MCS22;
+		break;
+	case DESC_RATEMCS23:
+		ret_rate = MGN_MCS23;
+		break;
+	case DESC_RATEMCS24:
+		ret_rate = MGN_MCS24;
+		break;
+	case DESC_RATEMCS25:
+		ret_rate = MGN_MCS25;
+		break;
+	case DESC_RATEMCS26:
+		ret_rate = MGN_MCS26;
+		break;
+	case DESC_RATEMCS27:
+		ret_rate = MGN_MCS27;
+		break;
+	case DESC_RATEMCS28:
+		ret_rate = MGN_MCS28;
+		break;
+	case DESC_RATEMCS29:
+		ret_rate = MGN_MCS29;
+		break;
+	case DESC_RATEMCS30:
+		ret_rate = MGN_MCS30;
+		break;
+	case DESC_RATEMCS31:
+		ret_rate = MGN_MCS31;
+		break;
+	case DESC_RATEVHTSS1MCS0:
+		ret_rate = MGN_VHT1SS_MCS0;
+		break;
+	case DESC_RATEVHTSS1MCS1:
+		ret_rate = MGN_VHT1SS_MCS1;
+		break;
+	case DESC_RATEVHTSS1MCS2:
+		ret_rate = MGN_VHT1SS_MCS2;
+		break;
+	case DESC_RATEVHTSS1MCS3:
+		ret_rate = MGN_VHT1SS_MCS3;
+		break;
+	case DESC_RATEVHTSS1MCS4:
+		ret_rate = MGN_VHT1SS_MCS4;
+		break;
+	case DESC_RATEVHTSS1MCS5:
+		ret_rate = MGN_VHT1SS_MCS5;
+		break;
+	case DESC_RATEVHTSS1MCS6:
+		ret_rate = MGN_VHT1SS_MCS6;
+		break;
+	case DESC_RATEVHTSS1MCS7:
+		ret_rate = MGN_VHT1SS_MCS7;
+		break;
+	case DESC_RATEVHTSS1MCS8:
+		ret_rate = MGN_VHT1SS_MCS8;
+		break;
+	case DESC_RATEVHTSS1MCS9:
+		ret_rate = MGN_VHT1SS_MCS9;
+		break;
+	case DESC_RATEVHTSS2MCS0:
+		ret_rate = MGN_VHT2SS_MCS0;
+		break;
+	case DESC_RATEVHTSS2MCS1:
+		ret_rate = MGN_VHT2SS_MCS1;
+		break;
+	case DESC_RATEVHTSS2MCS2:
+		ret_rate = MGN_VHT2SS_MCS2;
+		break;
+	case DESC_RATEVHTSS2MCS3:
+		ret_rate = MGN_VHT2SS_MCS3;
+		break;
+	case DESC_RATEVHTSS2MCS4:
+		ret_rate = MGN_VHT2SS_MCS4;
+		break;
+	case DESC_RATEVHTSS2MCS5:
+		ret_rate = MGN_VHT2SS_MCS5;
+		break;
+	case DESC_RATEVHTSS2MCS6:
+		ret_rate = MGN_VHT2SS_MCS6;
+		break;
+	case DESC_RATEVHTSS2MCS7:
+		ret_rate = MGN_VHT2SS_MCS7;
+		break;
+	case DESC_RATEVHTSS2MCS8:
+		ret_rate = MGN_VHT2SS_MCS8;
+		break;
+	case DESC_RATEVHTSS2MCS9:
+		ret_rate = MGN_VHT2SS_MCS9;
+		break;
+	case DESC_RATEVHTSS3MCS0:
+		ret_rate = MGN_VHT3SS_MCS0;
+		break;
+	case DESC_RATEVHTSS3MCS1:
+		ret_rate = MGN_VHT3SS_MCS1;
+		break;
+	case DESC_RATEVHTSS3MCS2:
+		ret_rate = MGN_VHT3SS_MCS2;
+		break;
+	case DESC_RATEVHTSS3MCS3:
+		ret_rate = MGN_VHT3SS_MCS3;
+		break;
+	case DESC_RATEVHTSS3MCS4:
+		ret_rate = MGN_VHT3SS_MCS4;
+		break;
+	case DESC_RATEVHTSS3MCS5:
+		ret_rate = MGN_VHT3SS_MCS5;
+		break;
+	case DESC_RATEVHTSS3MCS6:
+		ret_rate = MGN_VHT3SS_MCS6;
+		break;
+	case DESC_RATEVHTSS3MCS7:
+		ret_rate = MGN_VHT3SS_MCS7;
+		break;
+	case DESC_RATEVHTSS3MCS8:
+		ret_rate = MGN_VHT3SS_MCS8;
+		break;
+	case DESC_RATEVHTSS3MCS9:
+		ret_rate = MGN_VHT3SS_MCS9;
+		break;
+	case DESC_RATEVHTSS4MCS0:
+		ret_rate = MGN_VHT4SS_MCS0;
+		break;
+	case DESC_RATEVHTSS4MCS1:
+		ret_rate = MGN_VHT4SS_MCS1;
+		break;
+	case DESC_RATEVHTSS4MCS2:
+		ret_rate = MGN_VHT4SS_MCS2;
+		break;
+	case DESC_RATEVHTSS4MCS3:
+		ret_rate = MGN_VHT4SS_MCS3;
+		break;
+	case DESC_RATEVHTSS4MCS4:
+		ret_rate = MGN_VHT4SS_MCS4;
+		break;
+	case DESC_RATEVHTSS4MCS5:
+		ret_rate = MGN_VHT4SS_MCS5;
+		break;
+	case DESC_RATEVHTSS4MCS6:
+		ret_rate = MGN_VHT4SS_MCS6;
+		break;
+	case DESC_RATEVHTSS4MCS7:
+		ret_rate = MGN_VHT4SS_MCS7;
+		break;
+	case DESC_RATEVHTSS4MCS8:
+		ret_rate = MGN_VHT4SS_MCS8;
+		break;
+	case DESC_RATEVHTSS4MCS9:
+		ret_rate = MGN_VHT4SS_MCS9;
+		break;
+
+	default:
+		RTW_INFO("hw_rate_to_m_rate(): Non supported Rate [%x]!!!\n", rate);
+		break;
+	}
+
+	return ret_rate;
+}
+
+void	HalSetBrateCfg(
+	IN PADAPTER		Adapter,
+	IN u8			*mBratesOS,
+	OUT u16			*pBrateCfg)
+{
+	u8	i, is_brate, brate;
+
+	for (i = 0; i < NDIS_802_11_LENGTH_RATES_EX; i++) {
+		is_brate = mBratesOS[i] & IEEE80211_BASIC_RATE_MASK;
+		brate = mBratesOS[i] & 0x7f;
+
+		if (is_brate) {
+			switch (brate) {
+			case IEEE80211_CCK_RATE_1MB:
+				*pBrateCfg |= RATE_1M;
+				break;
+			case IEEE80211_CCK_RATE_2MB:
+				*pBrateCfg |= RATE_2M;
+				break;
+			case IEEE80211_CCK_RATE_5MB:
+				*pBrateCfg |= RATE_5_5M;
+				break;
+			case IEEE80211_CCK_RATE_11MB:
+				*pBrateCfg |= RATE_11M;
+				break;
+			case IEEE80211_OFDM_RATE_6MB:
+				*pBrateCfg |= RATE_6M;
+				break;
+			case IEEE80211_OFDM_RATE_9MB:
+				*pBrateCfg |= RATE_9M;
+				break;
+			case IEEE80211_OFDM_RATE_12MB:
+				*pBrateCfg |= RATE_12M;
+				break;
+			case IEEE80211_OFDM_RATE_18MB:
+				*pBrateCfg |= RATE_18M;
+				break;
+			case IEEE80211_OFDM_RATE_24MB:
+				*pBrateCfg |= RATE_24M;
+				break;
+			case IEEE80211_OFDM_RATE_36MB:
+				*pBrateCfg |= RATE_36M;
+				break;
+			case IEEE80211_OFDM_RATE_48MB:
+				*pBrateCfg |= RATE_48M;
+				break;
+			case IEEE80211_OFDM_RATE_54MB:
+				*pBrateCfg |= RATE_54M;
+				break;
+			}
+		}
+	}
+}
+
+static VOID
+_OneOutPipeMapping(
+	IN	PADAPTER	pAdapter
+)
+{
+	struct dvobj_priv	*pdvobjpriv = adapter_to_dvobj(pAdapter);
+
+	pdvobjpriv->Queue2Pipe[0] = pdvobjpriv->RtOutPipe[0];/* VO */
+	pdvobjpriv->Queue2Pipe[1] = pdvobjpriv->RtOutPipe[0];/* VI */
+	pdvobjpriv->Queue2Pipe[2] = pdvobjpriv->RtOutPipe[0];/* BE */
+	pdvobjpriv->Queue2Pipe[3] = pdvobjpriv->RtOutPipe[0];/* BK */
+
+	pdvobjpriv->Queue2Pipe[4] = pdvobjpriv->RtOutPipe[0];/* BCN */
+	pdvobjpriv->Queue2Pipe[5] = pdvobjpriv->RtOutPipe[0];/* MGT */
+	pdvobjpriv->Queue2Pipe[6] = pdvobjpriv->RtOutPipe[0];/* HIGH */
+	pdvobjpriv->Queue2Pipe[7] = pdvobjpriv->RtOutPipe[0];/* TXCMD */
+}
+
+static VOID
+_TwoOutPipeMapping(
+	IN	PADAPTER	pAdapter,
+	IN	BOOLEAN		bWIFICfg
+)
+{
+	struct dvobj_priv	*pdvobjpriv = adapter_to_dvobj(pAdapter);
+
+	if (bWIFICfg) { /* WMM */
+
+		/*	BK, 	BE, 	VI, 	VO, 	BCN,	CMD,MGT,HIGH,HCCA  */
+		/* {  0, 	1, 	0, 	1, 	0, 	0, 	0, 	0, 		0	}; */
+		/* 0:ep_0 num, 1:ep_1 num */
+
+		pdvobjpriv->Queue2Pipe[0] = pdvobjpriv->RtOutPipe[1];/* VO */
+		pdvobjpriv->Queue2Pipe[1] = pdvobjpriv->RtOutPipe[0];/* VI */
+		pdvobjpriv->Queue2Pipe[2] = pdvobjpriv->RtOutPipe[1];/* BE */
+		pdvobjpriv->Queue2Pipe[3] = pdvobjpriv->RtOutPipe[0];/* BK */
+
+		pdvobjpriv->Queue2Pipe[4] = pdvobjpriv->RtOutPipe[0];/* BCN */
+		pdvobjpriv->Queue2Pipe[5] = pdvobjpriv->RtOutPipe[0];/* MGT */
+		pdvobjpriv->Queue2Pipe[6] = pdvobjpriv->RtOutPipe[0];/* HIGH */
+		pdvobjpriv->Queue2Pipe[7] = pdvobjpriv->RtOutPipe[0];/* TXCMD */
+
+	} else { /* typical setting */
+
+
+		/* BK, 	BE, 	VI, 	VO, 	BCN,	CMD,MGT,HIGH,HCCA */
+		/* {  1, 	1, 	0, 	0, 	0, 	0, 	0, 	0, 		0	};			 */
+		/* 0:ep_0 num, 1:ep_1 num */
+
+		pdvobjpriv->Queue2Pipe[0] = pdvobjpriv->RtOutPipe[0];/* VO */
+		pdvobjpriv->Queue2Pipe[1] = pdvobjpriv->RtOutPipe[0];/* VI */
+		pdvobjpriv->Queue2Pipe[2] = pdvobjpriv->RtOutPipe[1];/* BE */
+		pdvobjpriv->Queue2Pipe[3] = pdvobjpriv->RtOutPipe[1];/* BK */
+
+		pdvobjpriv->Queue2Pipe[4] = pdvobjpriv->RtOutPipe[0];/* BCN */
+		pdvobjpriv->Queue2Pipe[5] = pdvobjpriv->RtOutPipe[0];/* MGT */
+		pdvobjpriv->Queue2Pipe[6] = pdvobjpriv->RtOutPipe[0];/* HIGH */
+		pdvobjpriv->Queue2Pipe[7] = pdvobjpriv->RtOutPipe[0];/* TXCMD	 */
+
+	}
+
+}
+
+static VOID _ThreeOutPipeMapping(
+	IN	PADAPTER	pAdapter,
+	IN	BOOLEAN		bWIFICfg
+)
+{
+	struct dvobj_priv	*pdvobjpriv = adapter_to_dvobj(pAdapter);
+
+	if (bWIFICfg) { /* for WMM */
+
+		/*	BK, 	BE, 	VI, 	VO, 	BCN,	CMD,MGT,HIGH,HCCA  */
+		/* {  1, 	2, 	1, 	0, 	0, 	0, 	0, 	0, 		0	}; */
+		/* 0:H, 1:N, 2:L */
+
+		pdvobjpriv->Queue2Pipe[0] = pdvobjpriv->RtOutPipe[0];/* VO */
+		pdvobjpriv->Queue2Pipe[1] = pdvobjpriv->RtOutPipe[1];/* VI */
+		pdvobjpriv->Queue2Pipe[2] = pdvobjpriv->RtOutPipe[2];/* BE */
+		pdvobjpriv->Queue2Pipe[3] = pdvobjpriv->RtOutPipe[1];/* BK */
+
+		pdvobjpriv->Queue2Pipe[4] = pdvobjpriv->RtOutPipe[0];/* BCN */
+		pdvobjpriv->Queue2Pipe[5] = pdvobjpriv->RtOutPipe[0];/* MGT */
+		pdvobjpriv->Queue2Pipe[6] = pdvobjpriv->RtOutPipe[0];/* HIGH */
+		pdvobjpriv->Queue2Pipe[7] = pdvobjpriv->RtOutPipe[0];/* TXCMD */
+
+	} else { /* typical setting */
+
+
+		/*	BK, 	BE, 	VI, 	VO, 	BCN,	CMD,MGT,HIGH,HCCA  */
+		/* {  2, 	2, 	1, 	0, 	0, 	0, 	0, 	0, 		0	};			 */
+		/* 0:H, 1:N, 2:L */
+
+		pdvobjpriv->Queue2Pipe[0] = pdvobjpriv->RtOutPipe[0];/* VO */
+		pdvobjpriv->Queue2Pipe[1] = pdvobjpriv->RtOutPipe[1];/* VI */
+		pdvobjpriv->Queue2Pipe[2] = pdvobjpriv->RtOutPipe[2];/* BE */
+		pdvobjpriv->Queue2Pipe[3] = pdvobjpriv->RtOutPipe[2];/* BK */
+
+		pdvobjpriv->Queue2Pipe[4] = pdvobjpriv->RtOutPipe[0];/* BCN */
+		pdvobjpriv->Queue2Pipe[5] = pdvobjpriv->RtOutPipe[0];/* MGT */
+		pdvobjpriv->Queue2Pipe[6] = pdvobjpriv->RtOutPipe[0];/* HIGH */
+		pdvobjpriv->Queue2Pipe[7] = pdvobjpriv->RtOutPipe[0];/* TXCMD	 */
+	}
+
+}
+static VOID _FourOutPipeMapping(
+	IN	PADAPTER	pAdapter,
+	IN	BOOLEAN		bWIFICfg
+)
+{
+	struct dvobj_priv	*pdvobjpriv = adapter_to_dvobj(pAdapter);
+
+	if (bWIFICfg) { /* for WMM */
+
+		/*	BK, 	BE, 	VI, 	VO, 	BCN,	CMD,MGT,HIGH,HCCA  */
+		/* {  1, 	2, 	1, 	0, 	0, 	0, 	0, 	0, 		0	}; */
+		/* 0:H, 1:N, 2:L ,3:E */
+
+		pdvobjpriv->Queue2Pipe[0] = pdvobjpriv->RtOutPipe[0];/* VO */
+		pdvobjpriv->Queue2Pipe[1] = pdvobjpriv->RtOutPipe[1];/* VI */
+		pdvobjpriv->Queue2Pipe[2] = pdvobjpriv->RtOutPipe[2];/* BE */
+		pdvobjpriv->Queue2Pipe[3] = pdvobjpriv->RtOutPipe[1];/* BK */
+
+		pdvobjpriv->Queue2Pipe[4] = pdvobjpriv->RtOutPipe[0];/* BCN */
+		pdvobjpriv->Queue2Pipe[5] = pdvobjpriv->RtOutPipe[0];/* MGT */
+		pdvobjpriv->Queue2Pipe[6] = pdvobjpriv->RtOutPipe[3];/* HIGH */
+		pdvobjpriv->Queue2Pipe[7] = pdvobjpriv->RtOutPipe[0];/* TXCMD */
+
+	} else { /* typical setting */
+
+
+		/*	BK, 	BE, 	VI, 	VO, 	BCN,	CMD,MGT,HIGH,HCCA  */
+		/* {  2, 	2, 	1, 	0, 	0, 	0, 	0, 	0, 		0	};			 */
+		/* 0:H, 1:N, 2:L */
+
+		pdvobjpriv->Queue2Pipe[0] = pdvobjpriv->RtOutPipe[0];/* VO */
+		pdvobjpriv->Queue2Pipe[1] = pdvobjpriv->RtOutPipe[1];/* VI */
+		pdvobjpriv->Queue2Pipe[2] = pdvobjpriv->RtOutPipe[2];/* BE */
+		pdvobjpriv->Queue2Pipe[3] = pdvobjpriv->RtOutPipe[2];/* BK */
+
+		pdvobjpriv->Queue2Pipe[4] = pdvobjpriv->RtOutPipe[0];/* BCN */
+		pdvobjpriv->Queue2Pipe[5] = pdvobjpriv->RtOutPipe[0];/* MGT */
+		pdvobjpriv->Queue2Pipe[6] = pdvobjpriv->RtOutPipe[3];/* HIGH */
+		pdvobjpriv->Queue2Pipe[7] = pdvobjpriv->RtOutPipe[0];/* TXCMD	 */
+	}
+
+}
+BOOLEAN
+Hal_MappingOutPipe(
+	IN	PADAPTER	pAdapter,
+	IN	u8		NumOutPipe
+)
+{
+	struct registry_priv *pregistrypriv = &pAdapter->registrypriv;
+
+	BOOLEAN	 bWIFICfg = (pregistrypriv->wifi_spec) ? _TRUE : _FALSE;
+
+	BOOLEAN result = _TRUE;
+
+	switch (NumOutPipe) {
+	case 2:
+		_TwoOutPipeMapping(pAdapter, bWIFICfg);
+		break;
+	case 3:
+	case 4:
+	case 5:
+	case 6:
+		_ThreeOutPipeMapping(pAdapter, bWIFICfg);
+		break;
+	case 1:
+		_OneOutPipeMapping(pAdapter);
+		break;
+	default:
+		result = _FALSE;
+		break;
+	}
+
+	return result;
+
+}
+
+void rtw_hal_reqtxrpt(_adapter *padapter, u8 macid)
+{
+	if (padapter->hal_func.reqtxrpt)
+		padapter->hal_func.reqtxrpt(padapter, macid);
+}
+
+void rtw_hal_dump_macaddr(void *sel, _adapter *adapter)
+{
+	int i;
+	_adapter *iface;
+	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
+	u8 mac_addr[ETH_ALEN];
+
+#ifdef CONFIG_MI_WITH_MBSSID_CAM
+	rtw_mbid_cam_dump(sel, __func__, adapter);
+#else
+	for (i = 0; i < dvobj->iface_nums; i++) {
+		iface = dvobj->padapters[i];
+		if (iface) {
+			rtw_hal_get_hwreg(iface, HW_VAR_MAC_ADDR, mac_addr);
+			RTW_PRINT_SEL(sel, ADPT_FMT"- hw port(%d) mac_addr ="MAC_FMT"\n",
+				ADPT_ARG(iface), iface->hw_port, MAC_ARG(mac_addr));
+		}
+	}
+#endif
+}
+
+#ifdef RTW_HALMAC
+void rtw_hal_hw_port_enable(_adapter *adapter)
+{
+#if 1
+	u8 port_enable = _TRUE;
+
+	rtw_hal_set_hwreg(adapter, HW_VAR_PORT_CFG, &port_enable);
+#else
+	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
+	struct rtw_halmac_bcn_ctrl bcn_ctrl;
+
+	_rtw_memset(&bcn_ctrl, 0, sizeof(struct rtw_halmac_bcn_ctrl));
+	bcn_ctrl.enable_bcn = 1;
+	bcn_ctrl.rx_bssid_fit = 1;
+	bcn_ctrl.rxbcn_rpt = 1;
+
+	/*rtw_halmac_get_bcn_ctrl(struct dvobj_priv *d, enum _hw_port hwport,
+				struct rtw_halmac_bcn_ctrl *bcn_ctrl)*/
+	if (rtw_halmac_set_bcn_ctrl(dvobj, get_hw_port(adapter), &bcn_ctrl) == -1) {
+		RTW_ERR(ADPT_FMT" - hw port(%d) enable fail!!\n", ADPT_ARG(adapter), get_hw_port(adapter));
+		rtw_warn_on(1);
+	}
+#endif
+}
+void rtw_hal_hw_port_disable(_adapter *adapter)
+{
+	u8 port_enable = _FALSE;
+
+	rtw_hal_set_hwreg(adapter, HW_VAR_PORT_CFG, &port_enable);
+}
+
+void rtw_restore_hw_port_cfg(_adapter *adapter)
+{
+#ifdef CONFIG_MI_WITH_MBSSID_CAM
+
+#else
+	int i;
+	_adapter *iface;
+	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
+
+	for (i = 0; i < dvobj->iface_nums; i++) {
+		iface = dvobj->padapters[i];
+		if (iface)
+			rtw_hal_hw_port_enable(iface);
+	}
+#endif
+}
+#endif
+
+void rtw_mi_set_mac_addr(_adapter *adapter)
+{
+#ifdef CONFIG_MI_WITH_MBSSID_CAM
+	rtw_mi_set_mbid_cam(adapter);
+#else
+	int i;
+	_adapter *iface;
+	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
+
+	for (i = 0; i < dvobj->iface_nums; i++) {
+		iface = dvobj->padapters[i];
+		if (iface)
+			rtw_hal_set_hwreg(iface, HW_VAR_MAC_ADDR, adapter_mac_addr(iface));
+	}
+#endif
+	if (1)
+		rtw_hal_dump_macaddr(RTW_DBGDUMP, adapter);
+}
+
+void rtw_init_hal_com_default_value(PADAPTER Adapter)
+{
+	PHAL_DATA_TYPE	pHalData = GET_HAL_DATA(Adapter);
+	struct registry_priv *regsty = adapter_to_regsty(Adapter);
+
+	pHalData->AntDetection = 1;
+	pHalData->antenna_test = _FALSE;
+	pHalData->RegIQKFWOffload = regsty->iqk_fw_offload;
+	pHalData->ch_switch_offload = regsty->ch_switch_offload;
+#ifdef RTW_REDUCE_SCAN_SWITCH_CH_TIME
+	if (pHalData->ch_switch_offload == 0)
+		pHalData->ch_switch_offload = 1;
+#endif
+}
+
+#ifdef CONFIG_FW_C2H_REG
+void c2h_evt_clear(_adapter *adapter)
+{
+	rtw_write8(adapter, REG_C2HEVT_CLEAR, C2H_EVT_HOST_CLOSE);
+}
+
+s32 c2h_evt_read_88xx(_adapter *adapter, u8 *buf)
+{
+	s32 ret = _FAIL;
+	int i;
+	u8 trigger;
+
+	if (buf == NULL)
+		goto exit;
+
+	trigger = rtw_read8(adapter, REG_C2HEVT_CLEAR);
+
+	if (trigger == C2H_EVT_HOST_CLOSE) {
+		goto exit; /* Not ready */
+	} else if (trigger != C2H_EVT_FW_CLOSE) {
+		goto clear_evt; /* Not a valid value */
+	}
+
+	_rtw_memset(buf, 0, C2H_REG_LEN);
+
+	/* Read ID, LEN, SEQ */
+	SET_C2H_ID_88XX(buf, rtw_read8(adapter, REG_C2HEVT_MSG_NORMAL));
+	SET_C2H_SEQ_88XX(buf, rtw_read8(adapter, REG_C2HEVT_CMD_SEQ_88XX));
+	SET_C2H_PLEN_88XX(buf, rtw_read8(adapter, REG_C2HEVT_CMD_LEN_88XX));
+
+	if (0) {
+		RTW_INFO("%s id=0x%02x, seq=%u, plen=%u, trigger=0x%02x\n", __func__
+			, C2H_ID_88XX(buf), C2H_SEQ_88XX(buf), C2H_PLEN_88XX(buf), trigger);
+	}
+
+	/* Read the content */
+	for (i = 0; i < C2H_PLEN_88XX(buf); i++)
+		*(C2H_PAYLOAD_88XX(buf) + i) = rtw_read8(adapter, REG_C2HEVT_MSG_NORMAL + 2 + i);
+
+	RTW_DBG_DUMP("payload: ", C2H_PAYLOAD_88XX(buf), C2H_PLEN_88XX(buf));
+
+	ret = _SUCCESS;
+
+clear_evt:
+	/*
+	* Clear event to notify FW we have read the command.
+	* If this field isn't clear, the FW won't update the next command message.
+	*/
+	c2h_evt_clear(adapter);
+
+exit:
+	return ret;
+}
+#endif /* CONFIG_FW_C2H_REG */
+
+#ifdef CONFIG_FW_C2H_PKT
+#ifndef DBG_C2H_PKT_PRE_HDL
+#define DBG_C2H_PKT_PRE_HDL 0
+#endif
+#ifndef DBG_C2H_PKT_HDL
+#define DBG_C2H_PKT_HDL 0
+#endif
+void rtw_hal_c2h_pkt_pre_hdl(_adapter *adapter, u8 *buf, u16 len)
+{
+#ifdef RTW_HALMAC
+	/* TODO: extract hal_mac IC's code here*/
+#else
+	u8 parse_fail = 0;
+	u8 hdl_here = 0;
+	s32 ret = _FAIL;
+	u8 id, seq, plen;
+	u8 *payload;
+
+	if (rtw_hal_c2h_pkt_hdr_parse(adapter, buf, len, &id, &seq, &plen, &payload) != _SUCCESS) {
+		parse_fail = 1;
+		goto exit;
+	}
+
+	hdl_here = rtw_hal_c2h_id_handle_directly(adapter, id, seq, plen, payload) == _TRUE ? 1 : 0;
+	if (hdl_here) 
+		ret = rtw_hal_c2h_handler(adapter, id, seq, plen, payload);
+	else
+		ret = rtw_c2h_packet_wk_cmd(adapter, buf, len);
+
+exit:
+	if (parse_fail)
+		RTW_ERR("%s parse fail, buf=%p, len=:%u\n", __func__, buf, len);
+	else if (ret != _SUCCESS || DBG_C2H_PKT_PRE_HDL > 0) {
+		RTW_PRINT("%s: id=0x%02x, seq=%u, plen=%u, %s %s\n", __func__, id, seq, plen
+			, hdl_here ? "handle" : "enqueue"
+			, ret == _SUCCESS ? "ok" : "fail"
+		);
+		if (DBG_C2H_PKT_PRE_HDL >= 2)
+			RTW_PRINT_DUMP("dump: ", buf, len);
+	}
+#endif
+}
+
+void rtw_hal_c2h_pkt_hdl(_adapter *adapter, u8 *buf, u16 len)
+{
+#ifdef RTW_HALMAC
+	adapter->hal_func.hal_mac_c2h_handler(adapter, buf, len);
+#else
+	u8 parse_fail = 0;
+	u8 bypass = 0;
+	s32 ret = _FAIL;
+	u8 id, seq, plen;
+	u8 *payload;
+
+	if (rtw_hal_c2h_pkt_hdr_parse(adapter, buf, len, &id, &seq, &plen, &payload) != _SUCCESS) {
+		parse_fail = 1;
+		goto exit;
+	}
+
+#ifdef CONFIG_WOWLAN
+	if (adapter_to_pwrctl(adapter)->wowlan_mode == _TRUE) {
+		bypass = 1;
+		ret = _SUCCESS;
+		goto exit;
+	}
+#endif
+
+	ret = rtw_hal_c2h_handler(adapter, id, seq, plen, payload);
+
+exit:
+	if (parse_fail)
+		RTW_ERR("%s parse fail, buf=%p, len=:%u\n", __func__, buf, len);
+	else if (ret != _SUCCESS || bypass || DBG_C2H_PKT_HDL > 0) {
+		RTW_PRINT("%s: id=0x%02x, seq=%u, plen=%u, %s %s\n", __func__, id, seq, plen
+			, !bypass ? "handle" : "bypass"
+			, ret == _SUCCESS ? "ok" : "fail"
+		);
+		if (DBG_C2H_PKT_HDL >= 2)
+			RTW_PRINT_DUMP("dump: ", buf, len);
+	}
+#endif
+}
+#endif /* CONFIG_FW_C2H_PKT */
+
+void c2h_iqk_offload(_adapter *adapter, u8 *data, u8 len)
+{
+	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
+	struct submit_ctx *iqk_sctx = &hal_data->iqk_sctx;
+
+	RTW_INFO("IQK offload finish in %dms\n", rtw_get_passing_time_ms(iqk_sctx->submit_time));
+	if (0)
+		RTW_INFO_DUMP("C2H_IQK_FINISH: ", data, len);
+
+	rtw_sctx_done(&iqk_sctx);
+}
+
+int c2h_iqk_offload_wait(_adapter *adapter, u32 timeout_ms)
+{
+	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
+	struct submit_ctx *iqk_sctx = &hal_data->iqk_sctx;
+
+	iqk_sctx->submit_time = rtw_get_current_time();
+	iqk_sctx->timeout_ms = timeout_ms;
+	iqk_sctx->status = RTW_SCTX_SUBMITTED;
+
+	return rtw_sctx_wait(iqk_sctx, __func__);
+}
+
+#define	GET_C2H_MAC_HIDDEN_RPT_UUID_X(_data)			LE_BITS_TO_1BYTE(((u8 *)(_data)) + 0, 0, 8)
+#define	GET_C2H_MAC_HIDDEN_RPT_UUID_Y(_data)			LE_BITS_TO_1BYTE(((u8 *)(_data)) + 1, 0, 8)
+#define	GET_C2H_MAC_HIDDEN_RPT_UUID_Z(_data)			LE_BITS_TO_1BYTE(((u8 *)(_data)) + 2, 0, 5)
+#define	GET_C2H_MAC_HIDDEN_RPT_UUID_CRC(_data)			LE_BITS_TO_2BYTE(((u8 *)(_data)) + 2, 5, 11)
+#define	GET_C2H_MAC_HIDDEN_RPT_HCI_TYPE(_data)			LE_BITS_TO_1BYTE(((u8 *)(_data)) + 4, 0, 4)
+#define	GET_C2H_MAC_HIDDEN_RPT_PACKAGE_TYPE(_data)		LE_BITS_TO_1BYTE(((u8 *)(_data)) + 4, 4, 3)
+#define	GET_C2H_MAC_HIDDEN_RPT_TR_SWITCH(_data)			LE_BITS_TO_1BYTE(((u8 *)(_data)) + 4, 7, 1)
+#define	GET_C2H_MAC_HIDDEN_RPT_WL_FUNC(_data)			LE_BITS_TO_1BYTE(((u8 *)(_data)) + 5, 0, 4)
+#define	GET_C2H_MAC_HIDDEN_RPT_HW_STYPE(_data)			LE_BITS_TO_1BYTE(((u8 *)(_data)) + 5, 4, 4)
+#define	GET_C2H_MAC_HIDDEN_RPT_BW(_data)				LE_BITS_TO_1BYTE(((u8 *)(_data)) + 6, 0, 3)
+#define	GET_C2H_MAC_HIDDEN_RPT_ANT_NUM(_data)			LE_BITS_TO_1BYTE(((u8 *)(_data)) + 6, 5, 3)
+#define	GET_C2H_MAC_HIDDEN_RPT_80211_PROTOCOL(_data)	LE_BITS_TO_1BYTE(((u8 *)(_data)) + 7, 2, 2)
+#define	GET_C2H_MAC_HIDDEN_RPT_NIC_ROUTER(_data)		LE_BITS_TO_1BYTE(((u8 *)(_data)) + 7, 6, 2)
+
+#ifndef DBG_C2H_MAC_HIDDEN_RPT_HANDLE
+#define DBG_C2H_MAC_HIDDEN_RPT_HANDLE 0
+#endif
+
+#ifdef CONFIG_RTW_MAC_HIDDEN_RPT
+int c2h_mac_hidden_rpt_hdl(_adapter *adapter, u8 *data, u8 len)
+{
+	HAL_DATA_TYPE	*hal_data = GET_HAL_DATA(adapter);
+	struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter);
+	int ret = _FAIL;
+
+	u32 uuid;
+	u8 uuid_x;
+	u8 uuid_y;
+	u8 uuid_z;
+	u16 uuid_crc;
+
+	u8 hci_type;
+	u8 package_type;
+	u8 tr_switch;
+	u8 wl_func;
+	u8 hw_stype;
+	u8 bw;
+	u8 ant_num;
+	u8 protocol;
+	u8 nic;
+
+	int i;
+
+	if (len < MAC_HIDDEN_RPT_LEN) {
+		RTW_WARN("%s len(%u) < %d\n", __func__, len, MAC_HIDDEN_RPT_LEN);
+		goto exit;
+	}
+
+	uuid_x = GET_C2H_MAC_HIDDEN_RPT_UUID_X(data);
+	uuid_y = GET_C2H_MAC_HIDDEN_RPT_UUID_Y(data);
+	uuid_z = GET_C2H_MAC_HIDDEN_RPT_UUID_Z(data);
+	uuid_crc = GET_C2H_MAC_HIDDEN_RPT_UUID_CRC(data);
+
+	hci_type = GET_C2H_MAC_HIDDEN_RPT_HCI_TYPE(data);
+	package_type = GET_C2H_MAC_HIDDEN_RPT_PACKAGE_TYPE(data);
+
+	tr_switch = GET_C2H_MAC_HIDDEN_RPT_TR_SWITCH(data);
+
+	wl_func = GET_C2H_MAC_HIDDEN_RPT_WL_FUNC(data);
+	hw_stype = GET_C2H_MAC_HIDDEN_RPT_HW_STYPE(data);
+
+	bw = GET_C2H_MAC_HIDDEN_RPT_BW(data);
+	ant_num = GET_C2H_MAC_HIDDEN_RPT_ANT_NUM(data);
+
+	protocol = GET_C2H_MAC_HIDDEN_RPT_80211_PROTOCOL(data);
+	nic = GET_C2H_MAC_HIDDEN_RPT_NIC_ROUTER(data);
+
+	if (DBG_C2H_MAC_HIDDEN_RPT_HANDLE) {
+		for (i = 0; i < len; i++)
+			RTW_PRINT("%s: 0x%02X\n", __func__, *(data + i));
+
+		RTW_PRINT("uuid x:0x%02x y:0x%02x z:0x%x crc:0x%x\n", uuid_x, uuid_y, uuid_z, uuid_crc);
+		RTW_PRINT("hci_type:0x%x\n", hci_type);
+		RTW_PRINT("package_type:0x%x\n", package_type);
+		RTW_PRINT("tr_switch:0x%x\n", tr_switch);
+		RTW_PRINT("wl_func:0x%x\n", wl_func);
+		RTW_PRINT("hw_stype:0x%x\n", hw_stype);
+		RTW_PRINT("bw:0x%x\n", bw);
+		RTW_PRINT("ant_num:0x%x\n", ant_num);
+		RTW_PRINT("protocol:0x%x\n", protocol);
+		RTW_PRINT("nic:0x%x\n", nic);
+	}
+
+	/*
+	* NOTICE:
+	* for now, the following is common info/format
+	* if there is any hal difference need to export
+	* some IC dependent code will need to be implement
+	*/
+	hal_data->PackageType = package_type;
+	hal_spec->wl_func &= mac_hidden_wl_func_to_hal_wl_func(wl_func);
+	hal_spec->bw_cap &= mac_hidden_max_bw_to_hal_bw_cap(bw);
+	hal_spec->tx_nss_num = rtw_min(hal_spec->tx_nss_num, ant_num);
+	hal_spec->rx_nss_num = rtw_min(hal_spec->rx_nss_num, ant_num);
+	hal_spec->proto_cap &= mac_hidden_proto_to_hal_proto_cap(protocol);
+	hal_spec->hci_type = hci_type;
+
+	/* TODO: tr_switch */
+
+	ret = _SUCCESS;
+
+exit:
+	return ret;
+}
+
+int c2h_mac_hidden_rpt_2_hdl(_adapter *adapter, u8 *data, u8 len)
+{
+	HAL_DATA_TYPE	*hal_data = GET_HAL_DATA(adapter);
+	struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter);
+	int ret = _FAIL;
+
+	int i;
+
+	if (len < MAC_HIDDEN_RPT_2_LEN) {
+		RTW_WARN("%s len(%u) < %d\n", __func__, len, MAC_HIDDEN_RPT_2_LEN);
+		goto exit;
+	}
+
+	if (DBG_C2H_MAC_HIDDEN_RPT_HANDLE) {
+		for (i = 0; i < len; i++)
+			RTW_PRINT("%s: 0x%02X\n", __func__, *(data + i));
+	}
+
+	#if defined(CONFIG_RTL8188F) || defined(CONFIG_RTL8188GTV)
+	if (IS_8188F(hal_data->version_id) || IS_8188GTV(hal_data->version_id)) {
+		#define GET_C2H_MAC_HIDDEN_RPT_IRV(_data)	LE_BITS_TO_1BYTE(((u8 *)(_data)) + 0, 0, 4)
+		u8 irv = GET_C2H_MAC_HIDDEN_RPT_IRV(data);
+
+		if (DBG_C2H_MAC_HIDDEN_RPT_HANDLE)
+			RTW_PRINT("irv:0x%x\n", irv);
+
+		if(irv != 0xf)
+			hal_data->version_id.CUTVersion = irv;
+	}
+	#endif
+
+	ret = _SUCCESS;
+
+exit:
+	return ret;
+}
+
+int hal_read_mac_hidden_rpt(_adapter *adapter)
+{
+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(adapter);
+	int ret = _FAIL;
+	int ret_fwdl;
+	u8 mac_hidden_rpt[MAC_HIDDEN_RPT_LEN + MAC_HIDDEN_RPT_2_LEN] = {0};
+	systime start = rtw_get_current_time();
+	u32 cnt = 0;
+	u32 timeout_ms = 800;
+	u32 min_cnt = 10;
+	u8 id = C2H_DEFEATURE_RSVD;
+	int i;
+
+#if defined(CONFIG_USB_HCI) || defined(CONFIG_PCI_HCI)
+	u8 hci_type = rtw_get_intf_type(adapter);
+
+	if ((hci_type == RTW_USB || hci_type == RTW_PCIE)
+		&& !rtw_is_hw_init_completed(adapter))
+		rtw_hal_power_on(adapter);
+#endif
+
+	/* inform FW mac hidden rpt from reg is needed */
+	rtw_write8(adapter, REG_C2HEVT_MSG_NORMAL, C2H_DEFEATURE_RSVD);
+
+	/* download FW */
+	pHalData->not_xmitframe_fw_dl = 1;
+	ret_fwdl = rtw_hal_fw_dl(adapter, _FALSE);
+	pHalData->not_xmitframe_fw_dl = 0;
+	if (ret_fwdl != _SUCCESS)
+		goto mac_hidden_rpt_hdl;
+
+	/* polling for data ready */
+	start = rtw_get_current_time();
+	do {
+		cnt++;
+		id = rtw_read8(adapter, REG_C2HEVT_MSG_NORMAL);
+		if (id == C2H_MAC_HIDDEN_RPT || RTW_CANNOT_IO(adapter))
+			break;
+		rtw_msleep_os(10);
+	} while (rtw_get_passing_time_ms(start) < timeout_ms || cnt < min_cnt);
+
+	if (id == C2H_MAC_HIDDEN_RPT) {
+		/* read data */
+		for (i = 0; i < MAC_HIDDEN_RPT_LEN + MAC_HIDDEN_RPT_2_LEN; i++)
+			mac_hidden_rpt[i] = rtw_read8(adapter, REG_C2HEVT_MSG_NORMAL + 2 + i);
+	}
+
+	/* inform FW mac hidden rpt has read */
+	rtw_write8(adapter, REG_C2HEVT_MSG_NORMAL, C2H_DBG);
+
+mac_hidden_rpt_hdl:
+	c2h_mac_hidden_rpt_hdl(adapter, mac_hidden_rpt, MAC_HIDDEN_RPT_LEN);
+	c2h_mac_hidden_rpt_2_hdl(adapter, mac_hidden_rpt + MAC_HIDDEN_RPT_LEN, MAC_HIDDEN_RPT_2_LEN);
+
+	if (ret_fwdl == _SUCCESS && id == C2H_MAC_HIDDEN_RPT)
+		ret = _SUCCESS;
+
+exit:
+
+#if defined(CONFIG_USB_HCI) || defined(CONFIG_PCI_HCI)
+	if ((hci_type == RTW_USB || hci_type == RTW_PCIE)
+		&& !rtw_is_hw_init_completed(adapter))
+		rtw_hal_power_off(adapter);
+#endif
+
+	RTW_INFO("%s %s! (%u, %dms), fwdl:%d, id:0x%02x\n", __func__
+		, (ret == _SUCCESS) ? "OK" : "Fail", cnt, rtw_get_passing_time_ms(start), ret_fwdl, id);
+
+	return ret;
+}
+#endif /* CONFIG_RTW_MAC_HIDDEN_RPT */
+
+int c2h_defeature_dbg_hdl(_adapter *adapter, u8 *data, u8 len)
+{
+	HAL_DATA_TYPE	*hal_data = GET_HAL_DATA(adapter);
+	struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter);
+	int ret = _FAIL;
+
+	int i;
+
+	if (len < DEFEATURE_DBG_LEN) {
+		RTW_WARN("%s len(%u) < %d\n", __func__, len, DEFEATURE_DBG_LEN);
+		goto exit;
+	}
+
+	for (i = 0; i < len; i++)
+		RTW_PRINT("%s: 0x%02X\n", __func__, *(data + i));
+
+	ret = _SUCCESS;
+	
+exit:
+	return ret;
+}
+
+#ifndef DBG_CUSTOMER_STR_RPT_HANDLE
+#define DBG_CUSTOMER_STR_RPT_HANDLE 0
+#endif
+
+#ifdef CONFIG_RTW_CUSTOMER_STR
+s32 rtw_hal_h2c_customer_str_req(_adapter *adapter)
+{
+	u8 h2c_data[H2C_CUSTOMER_STR_REQ_LEN] = {0};
+
+	SET_H2CCMD_CUSTOMER_STR_REQ_EN(h2c_data, 1);
+	return rtw_hal_fill_h2c_cmd(adapter, H2C_CUSTOMER_STR_REQ, H2C_CUSTOMER_STR_REQ_LEN, h2c_data);
+}
+
+#define	C2H_CUSTOMER_STR_RPT_BYTE0(_data)		((u8 *)(_data))
+#define	C2H_CUSTOMER_STR_RPT_2_BYTE8(_data)		((u8 *)(_data))
+
+int c2h_customer_str_rpt_hdl(_adapter *adapter, u8 *data, u8 len)
+{
+	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
+	int ret = _FAIL;
+	int i;
+
+	if (len < CUSTOMER_STR_RPT_LEN) {
+		RTW_WARN("%s len(%u) < %d\n", __func__, len, CUSTOMER_STR_RPT_LEN);
+		goto exit;
+	}
+
+	if (DBG_CUSTOMER_STR_RPT_HANDLE)
+		RTW_PRINT_DUMP("customer_str_rpt: ", data, CUSTOMER_STR_RPT_LEN);
+
+	_enter_critical_mutex(&dvobj->customer_str_mutex, NULL);
+
+	if (dvobj->customer_str_sctx != NULL) {
+		if (dvobj->customer_str_sctx->status != RTW_SCTX_SUBMITTED)
+			RTW_WARN("%s invalid sctx.status:%d\n", __func__, dvobj->customer_str_sctx->status);
+		_rtw_memcpy(dvobj->customer_str,  C2H_CUSTOMER_STR_RPT_BYTE0(data), CUSTOMER_STR_RPT_LEN);
+		dvobj->customer_str_sctx->status = RTX_SCTX_CSTR_WAIT_RPT2;
+	} else
+		RTW_WARN("%s sctx not set\n", __func__);
+
+	_exit_critical_mutex(&dvobj->customer_str_mutex, NULL);
+
+	ret = _SUCCESS;
+
+exit:
+	return ret;
+}
+
+int c2h_customer_str_rpt_2_hdl(_adapter *adapter, u8 *data, u8 len)
+{
+	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
+	int ret = _FAIL;
+	int i;
+
+	if (len < CUSTOMER_STR_RPT_2_LEN) {
+		RTW_WARN("%s len(%u) < %d\n", __func__, len, CUSTOMER_STR_RPT_2_LEN);
+		goto exit;
+	}
+
+	if (DBG_CUSTOMER_STR_RPT_HANDLE)
+		RTW_PRINT_DUMP("customer_str_rpt_2: ", data, CUSTOMER_STR_RPT_2_LEN);
+
+	_enter_critical_mutex(&dvobj->customer_str_mutex, NULL);
+
+	if (dvobj->customer_str_sctx != NULL) {
+		if (dvobj->customer_str_sctx->status != RTX_SCTX_CSTR_WAIT_RPT2)
+			RTW_WARN("%s rpt not ready\n", __func__);
+		_rtw_memcpy(dvobj->customer_str + CUSTOMER_STR_RPT_LEN,  C2H_CUSTOMER_STR_RPT_2_BYTE8(data), CUSTOMER_STR_RPT_2_LEN);
+		rtw_sctx_done(&dvobj->customer_str_sctx);
+	} else
+		RTW_WARN("%s sctx not set\n", __func__);
+
+	_exit_critical_mutex(&dvobj->customer_str_mutex, NULL);
+
+	ret = _SUCCESS;
+
+exit:
+	return ret;
+}
+
+/* read customer str */
+s32 rtw_hal_customer_str_read(_adapter *adapter, u8 *cs)
+{
+	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
+	struct submit_ctx sctx;
+	s32 ret = _SUCCESS;
+
+	_enter_critical_mutex(&dvobj->customer_str_mutex, NULL);
+	if (dvobj->customer_str_sctx != NULL)
+		ret = _FAIL;
+	else {
+		rtw_sctx_init(&sctx, 2 * 1000);
+		dvobj->customer_str_sctx = &sctx;
+	}
+	_exit_critical_mutex(&dvobj->customer_str_mutex, NULL);
+
+	if (ret == _FAIL) {
+		RTW_WARN("%s another handle ongoing\n", __func__);
+		goto exit;
+	}
+
+	ret = rtw_customer_str_req_cmd(adapter);
+	if (ret != _SUCCESS) {
+		RTW_WARN("%s read cmd fail\n", __func__);
+		_enter_critical_mutex(&dvobj->customer_str_mutex, NULL);
+		dvobj->customer_str_sctx = NULL;
+		_exit_critical_mutex(&dvobj->customer_str_mutex, NULL);
+		goto exit;
+	}
+
+	/* wait till rpt done or timeout */
+	rtw_sctx_wait(&sctx, __func__);
+
+	_enter_critical_mutex(&dvobj->customer_str_mutex, NULL);
+	dvobj->customer_str_sctx = NULL;
+	if (sctx.status == RTW_SCTX_DONE_SUCCESS)
+		_rtw_memcpy(cs, dvobj->customer_str, RTW_CUSTOMER_STR_LEN);
+	else
+		ret = _FAIL;
+	_exit_critical_mutex(&dvobj->customer_str_mutex, NULL);
+
+exit:
+	return ret;
+}
+
+s32 rtw_hal_h2c_customer_str_write(_adapter *adapter, const u8 *cs)
+{
+	u8 h2c_data_w1[H2C_CUSTOMER_STR_W1_LEN] = {0};
+	u8 h2c_data_w2[H2C_CUSTOMER_STR_W2_LEN] = {0};
+	u8 h2c_data_w3[H2C_CUSTOMER_STR_W3_LEN] = {0};
+	s32 ret;
+
+	SET_H2CCMD_CUSTOMER_STR_W1_EN(h2c_data_w1, 1);
+	_rtw_memcpy(H2CCMD_CUSTOMER_STR_W1_BYTE0(h2c_data_w1), cs, 6);
+
+	SET_H2CCMD_CUSTOMER_STR_W2_EN(h2c_data_w2, 1);
+	_rtw_memcpy(H2CCMD_CUSTOMER_STR_W2_BYTE6(h2c_data_w2), cs + 6, 6);
+
+	SET_H2CCMD_CUSTOMER_STR_W3_EN(h2c_data_w3, 1);
+	_rtw_memcpy(H2CCMD_CUSTOMER_STR_W3_BYTE12(h2c_data_w3), cs + 6 + 6, 4);
+
+	ret = rtw_hal_fill_h2c_cmd(adapter, H2C_CUSTOMER_STR_W1, H2C_CUSTOMER_STR_W1_LEN, h2c_data_w1);
+	if (ret != _SUCCESS) {
+		RTW_WARN("%s w1 fail\n", __func__);
+		goto exit;
+	}
+
+	ret = rtw_hal_fill_h2c_cmd(adapter, H2C_CUSTOMER_STR_W2, H2C_CUSTOMER_STR_W2_LEN, h2c_data_w2);
+	if (ret != _SUCCESS) {
+		RTW_WARN("%s w2 fail\n", __func__);
+		goto exit;
+	}
+
+	ret = rtw_hal_fill_h2c_cmd(adapter, H2C_CUSTOMER_STR_W3, H2C_CUSTOMER_STR_W3_LEN, h2c_data_w3);
+	if (ret != _SUCCESS) {
+		RTW_WARN("%s w3 fail\n", __func__);
+		goto exit;
+	}
+
+exit:
+	return ret;
+}
+
+/* write customer str and check if value reported is the same as requested */
+s32 rtw_hal_customer_str_write(_adapter *adapter, const u8 *cs)
+{
+	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
+	struct submit_ctx sctx;
+	s32 ret = _SUCCESS;
+
+	_enter_critical_mutex(&dvobj->customer_str_mutex, NULL);
+	if (dvobj->customer_str_sctx != NULL)
+		ret = _FAIL;
+	else {
+		rtw_sctx_init(&sctx, 2 * 1000);
+		dvobj->customer_str_sctx = &sctx;
+	}
+	_exit_critical_mutex(&dvobj->customer_str_mutex, NULL);
+
+	if (ret == _FAIL) {
+		RTW_WARN("%s another handle ongoing\n", __func__);
+		goto exit;
+	}
+
+	ret = rtw_customer_str_write_cmd(adapter, cs);
+	if (ret != _SUCCESS) {
+		RTW_WARN("%s write cmd fail\n", __func__);
+		_enter_critical_mutex(&dvobj->customer_str_mutex, NULL);
+		dvobj->customer_str_sctx = NULL;
+		_exit_critical_mutex(&dvobj->customer_str_mutex, NULL);
+		goto exit;
+	}
+
+	ret = rtw_customer_str_req_cmd(adapter);
+	if (ret != _SUCCESS) {
+		RTW_WARN("%s read cmd fail\n", __func__);
+		_enter_critical_mutex(&dvobj->customer_str_mutex, NULL);
+		dvobj->customer_str_sctx = NULL;
+		_exit_critical_mutex(&dvobj->customer_str_mutex, NULL);
+		goto exit;
+	}
+
+	/* wait till rpt done or timeout */
+	rtw_sctx_wait(&sctx, __func__);
+
+	_enter_critical_mutex(&dvobj->customer_str_mutex, NULL);
+	dvobj->customer_str_sctx = NULL;
+	if (sctx.status == RTW_SCTX_DONE_SUCCESS) {
+		if (_rtw_memcmp(cs, dvobj->customer_str, RTW_CUSTOMER_STR_LEN) != _TRUE) {
+			RTW_WARN("%s read back check fail\n", __func__);
+			RTW_INFO_DUMP("write req: ", cs, RTW_CUSTOMER_STR_LEN);
+			RTW_INFO_DUMP("read back: ", dvobj->customer_str, RTW_CUSTOMER_STR_LEN);
+			ret = _FAIL;
+		}
+	} else
+		ret = _FAIL;
+	_exit_critical_mutex(&dvobj->customer_str_mutex, NULL);
+
+exit:
+	return ret;
+}
+#endif /* CONFIG_RTW_CUSTOMER_STR */
+
+#ifdef RTW_PER_CMD_SUPPORT_FW
+#define H2C_REQ_PER_RPT_LEN 5
+#define SET_H2CCMD_REQ_PER_RPT_GROUP_MACID(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 4, __Value)
+#define SET_H2CCMD_REQ_PER_RPT_RPT_TYPE(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE(__pH2CCmd, 4, 4, __Value)
+#define SET_H2CCMD_REQ_PER_RPT_MACID_BMAP(__pH2CCmd, __Value)	SET_BITS_TO_LE_4BYTE(__pH2CCmd + 1, 0, 32, __Value)
+
+u8 rtw_hal_set_req_per_rpt_cmd(_adapter *adapter, u8 group_macid,
+				      u8 rpt_type, u32 macid_bitmap)
+{
+	u8 ret = _FAIL;
+	u8 cmd_buf[H2C_REQ_PER_RPT_LEN] = {0};
+
+	SET_H2CCMD_REQ_PER_RPT_GROUP_MACID(cmd_buf, group_macid);
+	SET_H2CCMD_REQ_PER_RPT_RPT_TYPE(cmd_buf, rpt_type);
+	SET_H2CCMD_REQ_PER_RPT_MACID_BMAP(cmd_buf, macid_bitmap);
+
+	ret = rtw_hal_fill_h2c_cmd(adapter, 
+				   H2C_REQ_PER_RPT, 
+				   H2C_REQ_PER_RPT_LEN, 
+				   cmd_buf);
+	return ret;
+}
+
+#define	GET_C2H_PER_RATE_RPT_TYPE0_MACID0(_data)	LE_BITS_TO_1BYTE(((u8 *)(_data)), 0, 8)
+#define	GET_C2H_PER_RATE_RPT_TYPE0_PER0(_data)		LE_BITS_TO_1BYTE(((u8 *)(_data)) + 1, 0, 8)
+#define	GET_C2H_PER_RATE_RPT_TYPE0_RATE0(_data)		LE_BITS_TO_1BYTE(((u8 *)(_data)) + 2, 0, 8)
+#define	GET_C2H_PER_RATE_RPT_TYPE0_BW0(_data)		LE_BITS_TO_1BYTE(((u8 *)(_data)) + 3, 0, 2)
+#define	GET_C2H_PER_RATE_RPT_TYPE0_TOTAL_PKT0(_data)	LE_BITS_TO_2BYTE(((u8 *)(_data)) + 4, 0, 16)
+#define	GET_C2H_PER_RATE_RPT_TYPE0_MACID1(_data)	LE_BITS_TO_1BYTE(((u8 *)(_data)) + 6, 0, 8)
+#define	GET_C2H_PER_RATE_RPT_TYPE0_PER1(_data)		LE_BITS_TO_1BYTE(((u8 *)(_data)) + 7, 0, 8)
+#define	GET_C2H_PER_RATE_RPT_TYPE0_RATE1(_data)		LE_BITS_TO_1BYTE(((u8 *)(_data)) + 8, 0, 8)
+#define	GET_C2H_PER_RATE_RPT_TYPE0_BW1(_data)		LE_BITS_TO_1BYTE(((u8 *)(_data)) + 9, 0, 2)
+#define	GET_C2H_PER_RATE_RPT_TYPE0_TOTAL_PKT1(_data)	LE_BITS_TO_2BYTE(((u8 *)(_data)) + 10, 0, 16)
+
+#define	GET_C2H_PER_RATE_RPT_TYPE1_MACID0(_data)	LE_BITS_TO_1BYTE(((u8 *)(_data)), 0, 8)
+#define	GET_C2H_PER_RATE_RPT_TYPE1_PER0(_data)		LE_BITS_TO_1BYTE(((u8 *)(_data)) + 1, 0, 8)
+#define	GET_C2H_PER_RATE_RPT_TYPE1_RATE0(_data)		LE_BITS_TO_1BYTE(((u8 *)(_data)) + 2, 0, 8)
+#define	GET_C2H_PER_RATE_RPT_TYPE1_BW0(_data)		LE_BITS_TO_1BYTE(((u8 *)(_data)) + 3, 0, 2)
+#define	GET_C2H_PER_RATE_RPT_TYPE1_MACID1(_data)	LE_BITS_TO_1BYTE(((u8 *)(_data)) + 4, 0, 8)
+#define	GET_C2H_PER_RATE_RPT_TYPE1_PER1(_data)		LE_BITS_TO_1BYTE(((u8 *)(_data)) + 5, 0, 8)
+#define	GET_C2H_PER_RATE_RPT_TYPE1_RATE1(_data)		LE_BITS_TO_1BYTE(((u8 *)(_data)) + 6, 0, 8)
+#define	GET_C2H_PER_RATE_RPT_TYPE1_BW1(_data)		LE_BITS_TO_1BYTE(((u8 *)(_data)) + 7, 0, 2)
+#define	GET_C2H_PER_RATE_RPT_TYPE1_MACID2(_data)	LE_BITS_TO_1BYTE(((u8 *)(_data)) + 8, 0, 8)
+#define	GET_C2H_PER_RATE_RPT_TYPE1_PER2(_data)		LE_BITS_TO_1BYTE(((u8 *)(_data)) + 9, 0, 8)
+#define	GET_C2H_PER_RATE_RPT_TYPE1_RATE2(_data)		LE_BITS_TO_1BYTE(((u8 *)(_data)) + 10, 0, 8)
+#define	GET_C2H_PER_RATE_RPT_TYPE1_BW2(_data)		LE_BITS_TO_1BYTE(((u8 *)(_data)) + 11, 0, 2)
+
+static void per_rate_rpt_update(_adapter *adapter, u8 mac_id,
+				u8 per, u8 rate,
+				u8 bw, u8 total_pkt)
+{
+#ifdef CONFIG_RTW_MESH
+	rtw_ieee80211s_update_metric(adapter, mac_id,
+				     per, rate,
+				     bw, total_pkt);
+#endif
+}
+
+int c2h_per_rate_rpt_hdl(_adapter *adapter, u8 *data, u8 len)
+{
+	/* Now only consider type0, since it covers all params in type1
+	 * type0: mac_id, per, rate, bw, total_pkt
+	 * type1: mac_id, per, rate, bw
+	 */
+	u8 mac_id[2] = {0}, per[2] = {0}, rate[2] = {0}, bw[2] = {0};
+	u16 total_pkt[2] = {0};
+	int ret = _FAIL, i, macid_cnt = 0;
+
+	/* type0:
+	 * 1 macid includes   6 bytes info + 1 byte 0xff
+	 * 2 macid includes 2*6 bytes info
+	 */
+	if (!(len == 7 || len == 12)) {
+		RTW_WARN("%s len(%u) != 7 or 12\n", __FUNCTION__, len);
+		goto exit;
+	}
+
+	macid_cnt++;
+	mac_id[0] = GET_C2H_PER_RATE_RPT_TYPE0_MACID0(data);
+	per[0] = GET_C2H_PER_RATE_RPT_TYPE0_PER0(data);
+	rate[0] = GET_C2H_PER_RATE_RPT_TYPE0_RATE0(data);
+	bw[0] = GET_C2H_PER_RATE_RPT_TYPE0_BW0(data);
+	total_pkt[0] = GET_C2H_PER_RATE_RPT_TYPE0_TOTAL_PKT0(data);
+
+	mac_id[1] = GET_C2H_PER_RATE_RPT_TYPE0_MACID1(data);
+	/* 0xff means no report anymore */
+	if (mac_id[1] == 0xff)
+		goto update_per;
+	if (len != 12) {
+		RTW_WARN("%s incorrect format\n", __FUNCTION__);
+		goto exit;
+	}
+	macid_cnt++;
+	per[1] = GET_C2H_PER_RATE_RPT_TYPE0_PER1(data);
+	rate[1] = GET_C2H_PER_RATE_RPT_TYPE0_RATE1(data);
+	bw[1] = GET_C2H_PER_RATE_RPT_TYPE0_BW1(data);
+	total_pkt[1] = GET_C2H_PER_RATE_RPT_TYPE0_TOTAL_PKT1(data);
+
+update_per:
+	for (i = 0; i < macid_cnt; i++) {
+		RTW_DBG("[%s] type0 rpt[%d]: macid = %u, per = %u, "
+			"rate = %u, bw = %u, total_pkt = %u\n",
+			__FUNCTION__, i, mac_id[i], per[i],
+			rate[i], bw[i], total_pkt[i]);
+		per_rate_rpt_update(adapter, mac_id[i],
+				    per[i], rate[i],
+				    bw[i], total_pkt[i]);
+	}
+	ret = _SUCCESS;
+exit:
+	return ret;
+}
+#endif /* RTW_PER_CMD_SUPPORT_FW */
+
+void rtw_hal_update_sta_wset(_adapter *adapter, struct sta_info *psta)
+{
+	u8 w_set = 0;
+
+	if (psta->wireless_mode & WIRELESS_11B)
+		w_set |= WIRELESS_CCK;
+
+	if ((psta->wireless_mode & WIRELESS_11G) || (psta->wireless_mode & WIRELESS_11A))
+		w_set |= WIRELESS_OFDM;
+
+	if (psta->wireless_mode & WIRELESS_11_24N)
+		w_set |= WIRELESS_HT;
+
+	if ((psta->wireless_mode & WIRELESS_11AC) || (psta->wireless_mode & WIRELESS_11_5N))
+		w_set |= WIRELESS_VHT;
+
+	psta->cmn.support_wireless_set = w_set;
+}
+
+void rtw_hal_update_sta_mimo_type(_adapter *adapter, struct sta_info *psta)
+{
+	s8 tx_nss, rx_nss;
+
+	tx_nss = rtw_get_sta_tx_nss(adapter, psta);
+	rx_nss =  rtw_get_sta_rx_nss(adapter, psta);
+	if ((tx_nss == 1) && (rx_nss == 1))
+		psta->cmn.mimo_type = RF_1T1R;
+	else if ((tx_nss == 1) && (rx_nss == 2))
+		psta->cmn.mimo_type = RF_1T2R;
+	else if ((tx_nss == 2) && (rx_nss == 2))
+		psta->cmn.mimo_type = RF_2T2R;
+	else if ((tx_nss == 2) && (rx_nss == 3))
+		psta->cmn.mimo_type = RF_2T3R;
+	else if ((tx_nss == 2) && (rx_nss == 4))
+		psta->cmn.mimo_type = RF_2T4R;
+	else if ((tx_nss == 3) && (rx_nss == 3))
+		psta->cmn.mimo_type = RF_3T3R;
+	else if ((tx_nss == 3) && (rx_nss == 4))
+		psta->cmn.mimo_type = RF_3T4R;
+	else if ((tx_nss == 4) && (rx_nss == 4))
+		psta->cmn.mimo_type = RF_4T4R;
+	else
+		rtw_warn_on(1);
+
+	RTW_INFO("STA - MAC_ID:%d, Tx - %d SS, Rx - %d SS\n",
+			psta->cmn.mac_id, tx_nss, rx_nss);
+}
+
+void rtw_hal_update_sta_smps_cap(_adapter *adapter, struct sta_info *psta)
+{
+	/*Spatial Multiplexing Power Save*/
+#if 0
+	if (check_fwstate(&adapter->mlmepriv, WIFI_AP_STATE) == _TRUE) {
+		#ifdef CONFIG_80211N_HT
+		if (psta->htpriv.ht_option) {
+			if (psta->htpriv.smps_cap == 0)
+				psta->cmn.sm_ps = SM_PS_STATIC;
+			else if (psta->htpriv.smps_cap == 1)
+				psta->cmn.sm_ps = SM_PS_DYNAMIC;
+			else
+				psta->cmn.sm_ps = SM_PS_DISABLE;
+		}
+		#endif /* CONFIG_80211N_HT */
+	} else
+#endif
+		psta->cmn.sm_ps = SM_PS_DISABLE;
+
+	RTW_INFO("STA - MAC_ID:%d, SM_PS %d\n",
+			psta->cmn.mac_id, psta->cmn.sm_ps);
+}
+
+u8 rtw_get_mgntframe_raid(_adapter *adapter, unsigned char network_type)
+{
+
+	u8 raid;
+	if (IS_NEW_GENERATION_IC(adapter)) {
+
+		raid = (network_type & WIRELESS_11B)	? RATEID_IDX_B
+		       : RATEID_IDX_G;
+	} else {
+		raid = (network_type & WIRELESS_11B)	? RATR_INX_WIRELESS_B
+		       : RATR_INX_WIRELESS_G;
+	}
+	return raid;
+}
+
+void rtw_hal_update_sta_rate_mask(PADAPTER padapter, struct sta_info *psta)
+{
+	struct hal_spec_t *hal_spec = GET_HAL_SPEC(padapter);
+	u8 i, rf_type, tx_nss;
+	u64 tx_ra_bitmap = 0, tmp64=0;
+
+	if (psta == NULL)
+		return;
+
+	/* b/g mode ra_bitmap  */
+	for (i = 0; i < sizeof(psta->bssrateset); i++) {
+		if (psta->bssrateset[i])
+			tx_ra_bitmap |= rtw_get_bit_value_from_ieee_value(psta->bssrateset[i] & 0x7f);
+	}
+
+#ifdef CONFIG_80211N_HT
+if (padapter->registrypriv.ht_enable && is_supported_ht(padapter->registrypriv.wireless_mode)) {
+	rtw_hal_get_hwreg(padapter, HW_VAR_RF_TYPE, (u8 *)(&rf_type));
+	tx_nss = rtw_min(rf_type_to_rf_tx_cnt(rf_type), hal_spec->tx_nss_num);
+#ifdef CONFIG_80211AC_VHT
+	if (psta->vhtpriv.vht_option) {
+		/* AC mode ra_bitmap */
+		tx_ra_bitmap |= (rtw_vht_mcs_map_to_bitmap(psta->vhtpriv.vht_mcs_map, tx_nss) << 12);
+	} else
+#endif /* CONFIG_80211AC_VHT */
+	if (psta->htpriv.ht_option) {
+		/* n mode ra_bitmap */
+
+		/* Handling SMPS mode for AP MODE only*/
+		if (check_fwstate(&padapter->mlmepriv, WIFI_AP_STATE) == _TRUE) {
+			/*0:static SMPS, 1:dynamic SMPS, 3:SMPS disabled, 2:reserved*/
+			if (psta->htpriv.smps_cap == 0 || psta->htpriv.smps_cap == 1) {
+				/*operate with only one active receive chain // 11n-MCS rate <= MSC7*/
+				tx_nss = rtw_min(tx_nss, 1);
+			}
+		}
+
+		tmp64 = rtw_ht_mcs_set_to_bitmap(psta->htpriv.ht_cap.supp_mcs_set, tx_nss);
+		tx_ra_bitmap |= (tmp64 << 12);
+	}
+}
+#endif /* CONFIG_80211N_HT */
+	psta->cmn.ra_info.ramask = tx_ra_bitmap;
+	psta->init_rate = get_highest_rate_idx(tx_ra_bitmap) & 0x3f;
+}
+
+void rtw_hal_update_sta_ra_info(PADAPTER padapter, struct sta_info *psta)
+{
+	rtw_hal_update_sta_mimo_type(padapter, psta);
+	rtw_hal_update_sta_smps_cap(padapter, psta);
+	rtw_hal_update_sta_rate_mask(padapter, psta);
+}
+
+static u32 hw_bcn_ctrl_addr(_adapter *adapter, u8 hw_port)
+{
+	struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter);
+
+	if (hw_port >= hal_spec->port_num) {
+		RTW_ERR(FUNC_ADPT_FMT" HW Port(%d) invalid\n", FUNC_ADPT_ARG(adapter), hw_port);
+		rtw_warn_on(1);
+		return 0;
+	}
+
+	switch (hw_port) {
+	case HW_PORT0:
+		return REG_BCN_CTRL;
+	case HW_PORT1:
+		return REG_BCN_CTRL_1;
+	}
+
+	return 0;
+}
+
+static void rtw_hal_get_msr(_adapter *adapter, u8 *net_type)
+{
+#ifdef RTW_HALMAC
+	rtw_halmac_get_network_type(adapter_to_dvobj(adapter),
+				adapter->hw_port, net_type);
+#else /* !RTW_HALMAC */
+	switch (adapter->hw_port) {
+	case HW_PORT0:
+		/*REG_CR - BIT[17:16]-Network Type for port 1*/
+		*net_type = rtw_read8(adapter, MSR) & 0x03;
+		break;
+	case HW_PORT1:
+		/*REG_CR - BIT[19:18]-Network Type for port 1*/
+		*net_type = (rtw_read8(adapter, MSR) & 0x0C) >> 2;
+		break;
+#if defined(CONFIG_RTL8814A)
+	case HW_PORT2:
+		/*REG_CR_EXT- BIT[1:0]-Network Type for port 2*/
+		*net_type = rtw_read8(adapter, MSR1) & 0x03;
+		break;
+	case HW_PORT3:
+		/*REG_CR_EXT- BIT[3:2]-Network Type for port 3*/
+		*net_type = (rtw_read8(adapter, MSR1) & 0x0C) >> 2;
+		break;
+	case HW_PORT4:
+		/*REG_CR_EXT- BIT[5:4]-Network Type for port 4*/
+		*net_type = (rtw_read8(adapter, MSR1) & 0x30) >> 4;
+		break;
+#endif /*#if defined(CONFIG_RTL8814A)*/
+	default:
+		RTW_INFO("[WARN] "ADPT_FMT"- invalid hw port -%d\n",
+			 ADPT_ARG(adapter), adapter->hw_port);
+		rtw_warn_on(1);
+		break;
+	}
+#endif /* !RTW_HALMAC */
+}
+
+#if defined(CONFIG_MI_WITH_MBSSID_CAM) && defined(CONFIG_MBSSID_CAM) /*For 2 hw ports - 88E/92E/8812/8821/8723B*/
+static u8 rtw_hal_net_type_decision(_adapter *adapter, u8 net_type)
+{
+	if ((adapter->hw_port == HW_PORT0) && (rtw_get_mbid_cam_entry_num(adapter))) {
+		if (net_type != _HW_STATE_NOLINK_)
+			return _HW_STATE_AP_;
+	}
+	return net_type;
+}
+#endif
+static void rtw_hal_set_msr(_adapter *adapter, u8 net_type)
+{
+#ifdef RTW_HALMAC
+	#if defined(CONFIG_MI_WITH_MBSSID_CAM) && defined(CONFIG_MBSSID_CAM)
+	net_type = rtw_hal_net_type_decision(adapter, net_type);
+	#endif
+	rtw_halmac_set_network_type(adapter_to_dvobj(adapter),
+				adapter->hw_port, net_type);
+#else /* !RTW_HALMAC */
+	u8 val8 = 0;
+
+	switch (adapter->hw_port) {
+	case HW_PORT0:
+		#if defined(CONFIG_MI_WITH_MBSSID_CAM) && defined(CONFIG_MBSSID_CAM)
+		net_type = rtw_hal_net_type_decision(adapter, net_type);
+		#endif
+		/*REG_CR - BIT[17:16]-Network Type for port 0*/
+		val8 = rtw_read8(adapter, MSR) & 0x0C;
+		val8 |= net_type;
+		rtw_write8(adapter, MSR, val8);
+		break;
+	case HW_PORT1:
+		/*REG_CR - BIT[19:18]-Network Type for port 1*/
+		val8 = rtw_read8(adapter, MSR) & 0x03;
+		val8 |= net_type << 2;
+		rtw_write8(adapter, MSR, val8);
+		break;
+#if defined(CONFIG_RTL8814A)
+	case HW_PORT2:
+		/*REG_CR_EXT- BIT[1:0]-Network Type for port 2*/
+		val8 = rtw_read8(adapter, MSR1) & 0xFC;
+		val8 |= net_type;
+		rtw_write8(adapter, MSR1, val8);
+		break;
+	case HW_PORT3:
+		/*REG_CR_EXT- BIT[3:2]-Network Type for port 3*/
+		val8 = rtw_read8(adapter, MSR1) & 0xF3;
+		val8 |= net_type << 2;
+		rtw_write8(adapter, MSR1, val8);
+		break;
+	case HW_PORT4:
+		/*REG_CR_EXT- BIT[5:4]-Network Type for port 4*/
+		val8 = rtw_read8(adapter, MSR1) & 0xCF;
+		val8 |= net_type << 4;
+		rtw_write8(adapter, MSR1, val8);
+		break;
+#endif /* CONFIG_RTL8814A */
+	default:
+		RTW_INFO("[WARN] "ADPT_FMT"- invalid hw port -%d\n",
+			 ADPT_ARG(adapter), adapter->hw_port);
+		rtw_warn_on(1);
+		break;
+	}
+#endif /* !RTW_HALMAC */
+}
+
+#ifndef SEC_CAM_ACCESS_TIMEOUT_MS
+	#define SEC_CAM_ACCESS_TIMEOUT_MS 200
+#endif
+
+#ifndef DBG_SEC_CAM_ACCESS
+	#define DBG_SEC_CAM_ACCESS 0
+#endif
+
+u32 rtw_sec_read_cam(_adapter *adapter, u8 addr)
+{
+	_mutex *mutex = &adapter_to_dvobj(adapter)->cam_ctl.sec_cam_access_mutex;
+	u32 rdata;
+	u32 cnt = 0;
+	systime start = 0, end = 0;
+	u8 timeout = 0;
+	u8 sr = 0;
+
+	_enter_critical_mutex(mutex, NULL);
+
+	rtw_write32(adapter, REG_CAMCMD, CAM_POLLINIG | addr);
+
+	start = rtw_get_current_time();
+	while (1) {
+		if (rtw_is_surprise_removed(adapter)) {
+			sr = 1;
+			break;
+		}
+
+		cnt++;
+		if (0 == (rtw_read32(adapter, REG_CAMCMD) & CAM_POLLINIG))
+			break;
+
+		if (rtw_get_passing_time_ms(start) > SEC_CAM_ACCESS_TIMEOUT_MS) {
+			timeout = 1;
+			break;
+		}
+	}
+	end = rtw_get_current_time();
+
+	rdata = rtw_read32(adapter, REG_CAMREAD);
+
+	_exit_critical_mutex(mutex, NULL);
+
+	if (DBG_SEC_CAM_ACCESS || timeout) {
+		RTW_INFO(FUNC_ADPT_FMT" addr:0x%02x, rdata:0x%08x, to:%u, polling:%u, %d ms\n"
+			, FUNC_ADPT_ARG(adapter), addr, rdata, timeout, cnt, rtw_get_time_interval_ms(start, end));
+	}
+
+	return rdata;
+}
+
+void rtw_sec_write_cam(_adapter *adapter, u8 addr, u32 wdata)
+{
+	_mutex *mutex = &adapter_to_dvobj(adapter)->cam_ctl.sec_cam_access_mutex;
+	u32 cnt = 0;
+	systime start = 0, end = 0;
+	u8 timeout = 0;
+	u8 sr = 0;
+
+	_enter_critical_mutex(mutex, NULL);
+
+	rtw_write32(adapter, REG_CAMWRITE, wdata);
+	rtw_write32(adapter, REG_CAMCMD, CAM_POLLINIG | CAM_WRITE | addr);
+
+	start = rtw_get_current_time();
+	while (1) {
+		if (rtw_is_surprise_removed(adapter)) {
+			sr = 1;
+			break;
+		}
+
+		cnt++;
+		if (0 == (rtw_read32(adapter, REG_CAMCMD) & CAM_POLLINIG))
+			break;
+
+		if (rtw_get_passing_time_ms(start) > SEC_CAM_ACCESS_TIMEOUT_MS) {
+			timeout = 1;
+			break;
+		}
+	}
+	end = rtw_get_current_time();
+
+	_exit_critical_mutex(mutex, NULL);
+
+	if (DBG_SEC_CAM_ACCESS || timeout) {
+		RTW_INFO(FUNC_ADPT_FMT" addr:0x%02x, wdata:0x%08x, to:%u, polling:%u, %d ms\n"
+			, FUNC_ADPT_ARG(adapter), addr, wdata, timeout, cnt, rtw_get_time_interval_ms(start, end));
+	}
+}
+
+void rtw_sec_read_cam_ent(_adapter *adapter, u8 id, u8 *ctrl, u8 *mac, u8 *key)
+{
+	unsigned int val, addr;
+	u8 i;
+	u32 rdata;
+	u8 begin = 0;
+	u8 end = 5; /* TODO: consider other key length accordingly */
+
+	if (!ctrl && !mac && !key) {
+		rtw_warn_on(1);
+		goto exit;
+	}
+
+	/* TODO: check id range */
+
+	if (!ctrl && !mac)
+		begin = 2; /* read from key */
+
+	if (!key && !mac)
+		end = 0; /* read to ctrl */
+	else if (!key)
+		end = 2; /* read to mac */
+
+	for (i = begin; i <= end; i++) {
+		rdata = rtw_sec_read_cam(adapter, (id << 3) | i);
+
+		switch (i) {
+		case 0:
+			if (ctrl)
+				_rtw_memcpy(ctrl, (u8 *)(&rdata), 2);
+			if (mac)
+				_rtw_memcpy(mac, ((u8 *)(&rdata)) + 2, 2);
+			break;
+		case 1:
+			if (mac)
+				_rtw_memcpy(mac + 2, (u8 *)(&rdata), 4);
+			break;
+		default:
+			if (key)
+				_rtw_memcpy(key + (i - 2) * 4, (u8 *)(&rdata), 4);
+			break;
+		}
+	}
+
+exit:
+	return;
+}
+
+
+void rtw_sec_write_cam_ent(_adapter *adapter, u8 id, u16 ctrl, u8 *mac, u8 *key)
+{
+	unsigned int i;
+	int j;
+	u8 addr, addr1 = 0;
+	u32 wdata, wdata1 = 0;
+
+	/* TODO: consider other key length accordingly */
+#if 0
+	switch ((ctrl & 0x1c) >> 2) {
+	case _WEP40_:
+	case _TKIP_:
+	case _AES_:
+	case _WEP104_:
+
+	}
+#else
+	j = 7;
+#endif
+
+	for (; j >= 0; j--) {
+		switch (j) {
+		case 0:
+			wdata = (ctrl | (mac[0] << 16) | (mac[1] << 24));
+			break;
+		case 1:
+			wdata = (mac[2] | (mac[3] << 8) | (mac[4] << 16) | (mac[5] << 24));
+			break;
+		case 6:
+		case 7:
+			wdata = 0;
+			break;
+		default:
+			i = (j - 2) << 2;
+			wdata = (key[i] | (key[i + 1] << 8) | (key[i + 2] << 16) | (key[i + 3] << 24));
+			break;
+		}
+
+		addr = (id << 3) + j;
+
+#if defined(CONFIG_RTL8192F)
+		if(j == 1) {
+			wdata1 = wdata;
+			addr1 = addr;
+			continue;
+		}
+#endif
+
+		rtw_sec_write_cam(adapter, addr, wdata);
+	}
+
+#if defined(CONFIG_RTL8192F)
+	rtw_sec_write_cam(adapter, addr1, wdata1);
+#endif
+}
+
+void rtw_sec_clr_cam_ent(_adapter *adapter, u8 id)
+{
+	u8 addr;
+
+	addr = (id << 3);
+	rtw_sec_write_cam(adapter, addr, 0);
+}
+
+bool rtw_sec_read_cam_is_gk(_adapter *adapter, u8 id)
+{
+	bool res;
+	u16 ctrl;
+
+	rtw_sec_read_cam_ent(adapter, id, (u8 *)&ctrl, NULL, NULL);
+
+	res = (ctrl & BIT6) ? _TRUE : _FALSE;
+	return res;
+}
+#ifdef CONFIG_MBSSID_CAM
+void rtw_mbid_cam_init(struct dvobj_priv *dvobj)
+{
+	struct mbid_cam_ctl_t *mbid_cam_ctl = &dvobj->mbid_cam_ctl;
+
+	_rtw_spinlock_init(&mbid_cam_ctl->lock);
+	mbid_cam_ctl->bitmap = 0;
+	ATOMIC_SET(&mbid_cam_ctl->mbid_entry_num, 0);
+	_rtw_memset(&dvobj->mbid_cam_cache, 0, sizeof(dvobj->mbid_cam_cache));
+}
+
+void rtw_mbid_cam_deinit(struct dvobj_priv *dvobj)
+{
+	struct mbid_cam_ctl_t *mbid_cam_ctl = &dvobj->mbid_cam_ctl;
+
+	_rtw_spinlock_free(&mbid_cam_ctl->lock);
+}
+
+void rtw_mbid_cam_reset(_adapter *adapter)
+{
+	_irqL irqL;
+	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
+	struct mbid_cam_ctl_t *mbid_cam_ctl = &dvobj->mbid_cam_ctl;
+
+	_enter_critical_bh(&mbid_cam_ctl->lock, &irqL);
+	mbid_cam_ctl->bitmap = 0;
+	_rtw_memset(&dvobj->mbid_cam_cache, 0, sizeof(dvobj->mbid_cam_cache));
+	_exit_critical_bh(&mbid_cam_ctl->lock, &irqL);
+
+	ATOMIC_SET(&mbid_cam_ctl->mbid_entry_num, 0);
+}
+static u8 _rtw_mbid_cam_search_by_macaddr(_adapter *adapter, u8 *mac_addr)
+{
+	u8 i;
+	u8 cam_id = INVALID_CAM_ID;
+	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
+
+	for (i = 0; i < TOTAL_MBID_CAM_NUM; i++) {
+		if (mac_addr && _rtw_memcmp(dvobj->mbid_cam_cache[i].mac_addr, mac_addr, ETH_ALEN) == _TRUE) {
+			cam_id = i;
+			break;
+		}
+	}
+
+	RTW_INFO("%s mac:"MAC_FMT" - cam_id:%d\n", __func__, MAC_ARG(mac_addr), cam_id);
+	return cam_id;
+}
+
+u8 rtw_mbid_cam_search_by_macaddr(_adapter *adapter, u8 *mac_addr)
+{
+	_irqL irqL;
+
+	u8 cam_id = INVALID_CAM_ID;
+	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
+	struct mbid_cam_ctl_t *mbid_cam_ctl = &dvobj->mbid_cam_ctl;
+
+	_enter_critical_bh(&mbid_cam_ctl->lock, &irqL);
+	cam_id = _rtw_mbid_cam_search_by_macaddr(adapter, mac_addr);
+	_exit_critical_bh(&mbid_cam_ctl->lock, &irqL);
+
+	return cam_id;
+}
+static u8 _rtw_mbid_cam_search_by_ifaceid(_adapter *adapter, u8 iface_id)
+{
+	u8 i;
+	u8 cam_id = INVALID_CAM_ID;
+	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
+
+	for (i = 0; i < TOTAL_MBID_CAM_NUM; i++) {
+		if (iface_id == dvobj->mbid_cam_cache[i].iface_id) {
+			cam_id = i;
+			break;
+		}
+	}
+	if (cam_id != INVALID_CAM_ID)
+		RTW_INFO("%s iface_id:%d mac:"MAC_FMT" - cam_id:%d\n",
+			__func__, iface_id, MAC_ARG(dvobj->mbid_cam_cache[cam_id].mac_addr), cam_id);
+
+	return cam_id;
+}
+
+u8 rtw_mbid_cam_search_by_ifaceid(_adapter *adapter, u8 iface_id)
+{
+	_irqL irqL;
+	u8 cam_id = INVALID_CAM_ID;
+	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
+	struct mbid_cam_ctl_t *mbid_cam_ctl = &dvobj->mbid_cam_ctl;
+
+	_enter_critical_bh(&mbid_cam_ctl->lock, &irqL);
+	cam_id = _rtw_mbid_cam_search_by_ifaceid(adapter, iface_id);
+	_exit_critical_bh(&mbid_cam_ctl->lock, &irqL);
+
+	return cam_id;
+}
+u8 rtw_get_max_mbid_cam_id(_adapter *adapter)
+{
+	_irqL irqL;
+	s8 i;
+	u8 cam_id = INVALID_CAM_ID;
+	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
+	struct mbid_cam_ctl_t *mbid_cam_ctl = &dvobj->mbid_cam_ctl;
+
+	_enter_critical_bh(&mbid_cam_ctl->lock, &irqL);
+	for (i = (TOTAL_MBID_CAM_NUM - 1); i >= 0; i--) {
+		if (mbid_cam_ctl->bitmap & BIT(i)) {
+			cam_id = i;
+			break;
+		}
+	}
+	_exit_critical_bh(&mbid_cam_ctl->lock, &irqL);
+	/*RTW_INFO("%s max cam_id:%d\n", __func__, cam_id);*/
+	return cam_id;
+}
+
+inline u8 rtw_get_mbid_cam_entry_num(_adapter *adapter)
+{
+	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
+	struct mbid_cam_ctl_t *mbid_cam_ctl = &dvobj->mbid_cam_ctl;
+
+	return ATOMIC_READ(&mbid_cam_ctl->mbid_entry_num);
+}
+
+static inline void mbid_cam_cache_init(_adapter *adapter, struct mbid_cam_cache *pmbid_cam, u8 *mac_addr)
+{
+	if (adapter && pmbid_cam && mac_addr) {
+		_rtw_memcpy(pmbid_cam->mac_addr, mac_addr, ETH_ALEN);
+		pmbid_cam->iface_id = adapter->iface_id;
+	}
+}
+static inline void mbid_cam_cache_clr(struct mbid_cam_cache *pmbid_cam)
+{
+	if (pmbid_cam) {
+		_rtw_memset(pmbid_cam->mac_addr, 0, ETH_ALEN);
+		pmbid_cam->iface_id = CONFIG_IFACE_NUMBER;
+	}
+}
+
+u8 rtw_mbid_camid_alloc(_adapter *adapter, u8 *mac_addr)
+{
+	_irqL irqL;
+	u8 cam_id = INVALID_CAM_ID, i;
+	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
+	struct mbid_cam_ctl_t *mbid_cam_ctl = &dvobj->mbid_cam_ctl;
+	u8 entry_num = ATOMIC_READ(&mbid_cam_ctl->mbid_entry_num);
+
+	if (INVALID_CAM_ID != rtw_mbid_cam_search_by_macaddr(adapter, mac_addr))
+		goto exit;
+
+	if (entry_num >= TOTAL_MBID_CAM_NUM) {
+		RTW_INFO(FUNC_ADPT_FMT" failed !! MBSSID number :%d over TOTAL_CAM_ENTRY(8)\n", FUNC_ADPT_ARG(adapter), entry_num);
+		rtw_warn_on(1);
+	}
+
+	_enter_critical_bh(&mbid_cam_ctl->lock, &irqL);
+	for (i = 0; i < TOTAL_MBID_CAM_NUM; i++) {
+		if (!(mbid_cam_ctl->bitmap & BIT(i))) {
+			mbid_cam_ctl->bitmap |= BIT(i);
+			cam_id = i;
+			break;
+		}
+	}
+	if ((cam_id != INVALID_CAM_ID) && (mac_addr))
+		mbid_cam_cache_init(adapter, &dvobj->mbid_cam_cache[cam_id], mac_addr);
+	_exit_critical_bh(&mbid_cam_ctl->lock, &irqL);
+
+	if (cam_id != INVALID_CAM_ID) {
+		ATOMIC_INC(&mbid_cam_ctl->mbid_entry_num);
+		RTW_INFO("%s mac:"MAC_FMT" - cam_id:%d\n", __func__, MAC_ARG(mac_addr), cam_id);
+#ifdef DBG_MBID_CAM_DUMP
+		rtw_mbid_cam_cache_dump(RTW_DBGDUMP, __func__, adapter);
+#endif
+	} else
+		RTW_INFO("%s [WARN] "MAC_FMT" - invalid cam_id:%d\n", __func__, MAC_ARG(mac_addr), cam_id);
+exit:
+	return cam_id;
+}
+
+u8 rtw_mbid_cam_info_change(_adapter *adapter, u8 *mac_addr)
+{
+	_irqL irqL;
+	u8 entry_id = INVALID_CAM_ID;
+	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
+	struct mbid_cam_ctl_t *mbid_cam_ctl = &dvobj->mbid_cam_ctl;
+
+	_enter_critical_bh(&mbid_cam_ctl->lock, &irqL);
+	entry_id = _rtw_mbid_cam_search_by_ifaceid(adapter, adapter->iface_id);
+	if (entry_id != INVALID_CAM_ID)
+		mbid_cam_cache_init(adapter, &dvobj->mbid_cam_cache[entry_id], mac_addr);
+
+	_exit_critical_bh(&mbid_cam_ctl->lock, &irqL);
+
+	return entry_id;
+}
+
+u8 rtw_mbid_cam_assign(_adapter *adapter, u8 *mac_addr, u8 camid)
+{
+	_irqL irqL;
+	u8 ret = _FALSE;
+	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
+	struct mbid_cam_ctl_t *mbid_cam_ctl = &dvobj->mbid_cam_ctl;
+
+	if ((camid >= TOTAL_MBID_CAM_NUM) || (camid == INVALID_CAM_ID)) {
+		RTW_INFO(FUNC_ADPT_FMT" failed !! invlaid mbid_canid :%d\n", FUNC_ADPT_ARG(adapter), camid);
+		rtw_warn_on(1);
+	}
+	if (INVALID_CAM_ID != rtw_mbid_cam_search_by_macaddr(adapter, mac_addr))
+		goto exit;
+
+	_enter_critical_bh(&mbid_cam_ctl->lock, &irqL);
+	if (!(mbid_cam_ctl->bitmap & BIT(camid))) {
+		if (mac_addr) {
+			mbid_cam_ctl->bitmap |= BIT(camid);
+			mbid_cam_cache_init(adapter, &dvobj->mbid_cam_cache[camid], mac_addr);
+			ret = _TRUE;
+		}
+	}
+	_exit_critical_bh(&mbid_cam_ctl->lock, &irqL);
+
+	if (ret == _TRUE) {
+		ATOMIC_INC(&mbid_cam_ctl->mbid_entry_num);
+		RTW_INFO("%s mac:"MAC_FMT" - cam_id:%d\n", __func__, MAC_ARG(mac_addr), camid);
+#ifdef DBG_MBID_CAM_DUMP
+		rtw_mbid_cam_cache_dump(RTW_DBGDUMP, __func__, adapter);
+#endif
+	} else
+		RTW_INFO("%s  [WARN] mac:"MAC_FMT" - cam_id:%d assigned failed\n", __func__, MAC_ARG(mac_addr), camid);
+
+exit:
+	return ret;
+}
+
+void rtw_mbid_camid_clean(_adapter *adapter, u8 mbss_canid)
+{
+	_irqL irqL;
+	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
+	struct mbid_cam_ctl_t *mbid_cam_ctl = &dvobj->mbid_cam_ctl;
+
+	if ((mbss_canid >= TOTAL_MBID_CAM_NUM) || (mbss_canid == INVALID_CAM_ID)) {
+		RTW_INFO(FUNC_ADPT_FMT" failed !! invlaid mbid_canid :%d\n", FUNC_ADPT_ARG(adapter), mbss_canid);
+		rtw_warn_on(1);
+	}
+	_enter_critical_bh(&mbid_cam_ctl->lock, &irqL);
+	mbid_cam_cache_clr(&dvobj->mbid_cam_cache[mbss_canid]);
+	mbid_cam_ctl->bitmap &= (~BIT(mbss_canid));
+	_exit_critical_bh(&mbid_cam_ctl->lock, &irqL);
+	ATOMIC_DEC(&mbid_cam_ctl->mbid_entry_num);
+	RTW_INFO("%s - cam_id:%d\n", __func__, mbss_canid);
+}
+int rtw_mbid_cam_cache_dump(void *sel, const char *fun_name, _adapter *adapter)
+{
+	_irqL irqL;
+	u8 i;
+	_adapter *iface;
+	u8 iface_id;
+	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
+	struct mbid_cam_ctl_t *mbid_cam_ctl = &dvobj->mbid_cam_ctl;
+	u8 entry_num = ATOMIC_READ(&mbid_cam_ctl->mbid_entry_num);
+	u8 max_cam_id = rtw_get_max_mbid_cam_id(adapter);
+
+	RTW_PRINT_SEL(sel, "== MBSSID CAM DUMP (%s)==\n", fun_name);
+
+	_enter_critical_bh(&mbid_cam_ctl->lock, &irqL);
+	RTW_PRINT_SEL(sel, "Entry numbers:%d, max_camid:%d, bitmap:0x%08x\n", entry_num, max_cam_id, mbid_cam_ctl->bitmap);
+	for (i = 0; i < TOTAL_MBID_CAM_NUM; i++) {
+		RTW_PRINT_SEL(sel, "CAM_ID = %d\t", i);
+
+		if (mbid_cam_ctl->bitmap & BIT(i)) {
+			iface_id = dvobj->mbid_cam_cache[i].iface_id;
+			_RTW_PRINT_SEL(sel, "IF_ID:%d\t", iface_id);
+			_RTW_PRINT_SEL(sel, "MAC Addr:"MAC_FMT"\t", MAC_ARG(dvobj->mbid_cam_cache[i].mac_addr));
+
+			iface = dvobj->padapters[iface_id];
+			if (iface) {
+				if (MLME_IS_STA(iface))
+					_RTW_PRINT_SEL(sel, "ROLE:%s\n", "STA");
+				else if (MLME_IS_AP(iface))
+					_RTW_PRINT_SEL(sel, "ROLE:%s\n", "AP");
+				else if (MLME_IS_MESH(iface))
+					_RTW_PRINT_SEL(sel, "ROLE:%s\n", "MESH");
+				else
+					_RTW_PRINT_SEL(sel, "ROLE:%s\n", "NONE");
+			}
+
+		} else
+			_RTW_PRINT_SEL(sel, "N/A\n");
+	}
+	_exit_critical_bh(&mbid_cam_ctl->lock, &irqL);
+	return 0;
+}
+
+static void read_mbssid_cam(_adapter *padapter, u8 cam_addr, u8 *mac)
+{
+	u8 poll = 1;
+	u8 cam_ready = _FALSE;
+	u32 cam_data1 = 0;
+	u16 cam_data2 = 0;
+
+	if (RTW_CANNOT_RUN(padapter))
+		return;
+
+	rtw_write32(padapter, REG_MBIDCAMCFG_2, BIT_MBIDCAM_POLL | ((cam_addr & MBIDCAM_ADDR_MASK) << MBIDCAM_ADDR_SHIFT));
+
+	do {
+		if (0 == (rtw_read32(padapter, REG_MBIDCAMCFG_2) & BIT_MBIDCAM_POLL)) {
+			cam_ready = _TRUE;
+			break;
+		}
+		poll++;
+	} while ((poll % 10) != 0 && !RTW_CANNOT_RUN(padapter));
+
+	if (cam_ready) {
+		cam_data1 = rtw_read32(padapter, REG_MBIDCAMCFG_1);
+		mac[0] = cam_data1 & 0xFF;
+		mac[1] = (cam_data1 >> 8) & 0xFF;
+		mac[2] = (cam_data1 >> 16) & 0xFF;
+		mac[3] = (cam_data1 >> 24) & 0xFF;
+
+		cam_data2 = rtw_read16(padapter, REG_MBIDCAMCFG_2);
+		mac[4] = cam_data2 & 0xFF;
+		mac[5] = (cam_data2 >> 8) & 0xFF;
+	}
+
+}
+int rtw_mbid_cam_dump(void *sel, const char *fun_name, _adapter *adapter)
+{
+	/*_irqL irqL;*/
+	u8 i;
+	u8 mac_addr[ETH_ALEN];
+
+	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
+	struct mbid_cam_ctl_t *mbid_cam_ctl = &dvobj->mbid_cam_ctl;
+
+	RTW_PRINT_SEL(sel, "\n== MBSSID HW-CAM DUMP (%s)==\n", fun_name);
+
+	/*_enter_critical_bh(&mbid_cam_ctl->lock, &irqL);*/
+	for (i = 0; i < TOTAL_MBID_CAM_NUM; i++) {
+		RTW_PRINT_SEL(sel, "CAM_ID = %d\t", i);
+		_rtw_memset(mac_addr, 0, ETH_ALEN);
+		read_mbssid_cam(adapter, i, mac_addr);
+		_RTW_PRINT_SEL(sel, "MAC Addr:"MAC_FMT"\n", MAC_ARG(mac_addr));
+	}
+	/*_exit_critical_bh(&mbid_cam_ctl->lock, &irqL);*/
+	return 0;
+}
+
+static void write_mbssid_cam(_adapter *padapter, u8 cam_addr, u8 *mac)
+{
+	u32	cam_val[2] = {0};
+
+	cam_val[0] = (mac[3] << 24) | (mac[2] << 16) | (mac[1] << 8) | mac[0];
+	cam_val[1] = ((cam_addr & MBIDCAM_ADDR_MASK) << MBIDCAM_ADDR_SHIFT)  | (mac[5] << 8) | mac[4];
+
+	rtw_hal_set_hwreg(padapter, HW_VAR_MBSSID_CAM_WRITE, (u8 *)cam_val);
+}
+
+static void clear_mbssid_cam(_adapter *padapter, u8 cam_addr)
+{
+	rtw_hal_set_hwreg(padapter, HW_VAR_MBSSID_CAM_CLEAR, &cam_addr);
+}
+
+void rtw_ap_set_mbid_num(_adapter *adapter, u8 ap_num)
+{
+	rtw_write8(adapter, REG_MBID_NUM,
+		((rtw_read8(adapter, REG_MBID_NUM) & 0xF8) | ((ap_num -1) & 0x07)));
+
+}
+void rtw_mbid_cam_enable(_adapter *adapter)
+{
+	/*enable MBSSID*/
+	rtw_hal_rcr_add(adapter, RCR_ENMBID);
+}
+void rtw_mi_set_mbid_cam(_adapter *adapter)
+{
+	u8 i;
+	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
+	struct mbid_cam_ctl_t *mbid_cam_ctl = &dvobj->mbid_cam_ctl;
+
+#ifdef DBG_MBID_CAM_DUMP
+	rtw_mbid_cam_cache_dump(RTW_DBGDUMP, __func__, adapter);
+#endif
+
+	for (i = 0; i < TOTAL_MBID_CAM_NUM; i++) {
+		if (mbid_cam_ctl->bitmap & BIT(i)) {
+			write_mbssid_cam(adapter, i, dvobj->mbid_cam_cache[i].mac_addr);
+			RTW_INFO("%s - cam_id:%d => mac:"MAC_FMT"\n", __func__, i, MAC_ARG(dvobj->mbid_cam_cache[i].mac_addr));
+		}
+	}
+	rtw_mbid_cam_enable(adapter);
+}
+#endif /*CONFIG_MBSSID_CAM*/
+
+#ifdef CONFIG_FW_HANDLE_TXBCN
+#define H2C_BCN_OFFLOAD_LEN	1
+
+#define SET_H2CCMD_BCN_OFFLOAD_EN(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 1, __Value)
+#define SET_H2CCMD_BCN_ROOT_TBTT_RPT(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE(__pH2CCmd, 1, 1, __Value)
+#define SET_H2CCMD_BCN_VAP1_TBTT_RPT(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE(__pH2CCmd, 2, 1, __Value)
+#define SET_H2CCMD_BCN_VAP2_TBTT_RPT(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE(__pH2CCmd, 3, 1, __Value)
+#define SET_H2CCMD_BCN_VAP3_TBTT_RPT(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE(__pH2CCmd, 4, 1, __Value)
+#define SET_H2CCMD_BCN_VAP4_TBTT_RPT(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE(__pH2CCmd, 5, 1, __Value)
+
+void rtw_hal_set_fw_ap_bcn_offload_cmd(_adapter *adapter, bool fw_bcn_en, u8 tbtt_rpt_map)
+{
+	u8 fw_bcn_offload[1] = {0};
+	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
+
+	if (fw_bcn_en)
+		SET_H2CCMD_BCN_OFFLOAD_EN(fw_bcn_offload, 1);
+
+	if (tbtt_rpt_map & BIT(0))
+		SET_H2CCMD_BCN_ROOT_TBTT_RPT(fw_bcn_offload, 1);
+	if (tbtt_rpt_map & BIT(1))
+		SET_H2CCMD_BCN_VAP1_TBTT_RPT(fw_bcn_offload, 1);
+	if (tbtt_rpt_map & BIT(2))
+		SET_H2CCMD_BCN_VAP2_TBTT_RPT(fw_bcn_offload, 1);
+	if (tbtt_rpt_map & BIT(3))
+			SET_H2CCMD_BCN_VAP3_TBTT_RPT(fw_bcn_offload, 1);
+
+	dvobj->vap_tbtt_rpt_map = tbtt_rpt_map;
+	dvobj->fw_bcn_offload = fw_bcn_en;
+	RTW_INFO("[FW BCN] Offload : %s\n", (dvobj->fw_bcn_offload) ? "EN" : "DIS");
+	RTW_INFO("[FW BCN] TBTT RPT map : 0x%02x\n", dvobj->vap_tbtt_rpt_map);
+
+	rtw_hal_fill_h2c_cmd(adapter, H2C_FW_BCN_OFFLOAD,
+					H2C_BCN_OFFLOAD_LEN, fw_bcn_offload);
+}
+
+void rtw_hal_set_bcn_rsvdpage_loc_cmd(_adapter *adapter)
+{
+	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
+	u8 ret, vap_id;
+	u32 page_size = 0;
+	u8 bcn_rsvdpage[H2C_BCN_RSVDPAGE_LEN] = {0};
+
+	rtw_hal_get_def_var(adapter, HAL_DEF_TX_PAGE_SIZE, (u8 *)&page_size);
+	#if 1
+	for (vap_id = 0; vap_id < CONFIG_LIMITED_AP_NUM; vap_id++) {
+		if (dvobj->vap_map & BIT(vap_id))
+			bcn_rsvdpage[vap_id] = vap_id * (MAX_BEACON_LEN / page_size);
+	}
+	#else
+#define SET_H2CCMD_BCN_RSVDPAGE_LOC_ROOT(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
+#define SET_H2CCMD_BCN_RSVDPAGE_LOC_VAP1(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE(__pH2CCmd, 1, 8, __Value)
+#define SET_H2CCMD_BCN_RSVDPAGE_LOC_VAP2(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE(__pH2CCmd, 2, 8, __Value)
+#define SET_H2CCMD_BCN_RSVDPAGE_LOC_VAP3(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE(__pH2CCmd, 3, 8, __Value)
+#define SET_H2CCMD_BCN_RSVDPAGE_LOC_VAP4(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE(__pH2CCmd, 4, 8, __Value)
+
+	if (dvobj->vap_map & BIT(0))
+ 		SET_H2CCMD_BCN_RSVDPAGE_LOC_ROOT(bcn_rsvdpage, 0);
+	if (dvobj->vap_map & BIT(1))
+		SET_H2CCMD_BCN_RSVDPAGE_LOC_VAP1(bcn_rsvdpage,
+					1 * (MAX_BEACON_LEN / page_size));
+	if (dvobj->vap_map & BIT(2))
+		SET_H2CCMD_BCN_RSVDPAGE_LOC_VAP2(bcn_rsvdpage,
+					2 * (MAX_BEACON_LEN / page_size));
+	if (dvobj->vap_map & BIT(3))
+		SET_H2CCMD_BCN_RSVDPAGE_LOC_VAP3(bcn_rsvdpage,
+					3 * (MAX_BEACON_LEN / page_size));
+	if (dvobj->vap_map & BIT(4))
+		SET_H2CCMD_BCN_RSVDPAGE_LOC_VAP4(bcn_rsvdpage,
+					4 * (MAX_BEACON_LEN / page_size));
+	#endif
+	if (1) {
+		RTW_INFO("[BCN_LOC] vap_map : 0x%02x\n", dvobj->vap_map);
+		RTW_INFO("[BCN_LOC] page_size :%d, @bcn_page_num :%d\n"
+			, page_size, (MAX_BEACON_LEN / page_size));
+		RTW_INFO("[BCN_LOC] root ap : 0x%02x\n", *bcn_rsvdpage);
+		RTW_INFO("[BCN_LOC] vap_1 : 0x%02x\n", *(bcn_rsvdpage + 1));
+		RTW_INFO("[BCN_LOC] vap_2 : 0x%02x\n", *(bcn_rsvdpage + 2));
+		RTW_INFO("[BCN_LOC] vap_3 : 0x%02x\n", *(bcn_rsvdpage + 3));
+		RTW_INFO("[BCN_LOC] vap_4 : 0x%02x\n", *(bcn_rsvdpage + 4));
+	}
+	ret = rtw_hal_fill_h2c_cmd(adapter, H2C_BCN_RSVDPAGE,
+					H2C_BCN_RSVDPAGE_LEN, bcn_rsvdpage);
+}
+
+void rtw_ap_multi_bcn_cfg(_adapter *adapter)
+{
+	u8 dft_bcn_space = DEFAULT_BCN_INTERVAL;
+	u8 sub_bcn_space = (DEFAULT_BCN_INTERVAL / CONFIG_LIMITED_AP_NUM);
+
+	/*enable to rx data frame*/
+	rtw_write16(adapter, REG_RXFLTMAP2, 0xFFFF);
+
+	/*Disable Port0's beacon function*/
+	rtw_write8(adapter, REG_BCN_CTRL, rtw_read8(adapter, REG_BCN_CTRL) & ~BIT_EN_BCN_FUNCTION);
+	/*Reset Port0's TSF*/
+	rtw_write8(adapter, REG_DUAL_TSF_RST, BIT_TSFTR_RST);
+
+	rtw_ap_set_mbid_num(adapter, CONFIG_LIMITED_AP_NUM);
+
+	/*BCN space & BCN sub-space 0x554[15:0] = 0x64,0x5BC[23:16] = 0x21*/
+	rtw_halmac_set_bcn_interval(adapter_to_dvobj(adapter), HW_PORT0, dft_bcn_space);
+	rtw_write8(adapter, REG_MBSSID_BCN_SPACE3 + 2, sub_bcn_space);
+
+	#if 0 /*setting in hw_var_set_opmode_mbid - ResumeTxBeacon*/
+	/*BCN hold time  0x540[19:8] = 0x80*/
+	rtw_write8(adapter, REG_TBTT_PROHIBIT + 1, TBTT_PROHIBIT_HOLD_TIME & 0xFF);
+	rtw_write8(adapter, REG_TBTT_PROHIBIT + 2,
+		(rtw_read8(adapter, REG_TBTT_PROHIBIT + 2) & 0xF0) | (TBTT_PROHIBIT_HOLD_TIME >> 8));
+	#endif
+
+	/*ATIM window -0x55A = 0x32, reg 0x570 = 0x32, reg 0x5A0 = 0x32 */
+	rtw_write8(adapter, REG_ATIMWND, 0x32);
+	rtw_write8(adapter, REG_ATIMWND1_V1, 0x32);
+	rtw_write8(adapter, REG_ATIMWND2, 0x32);
+	rtw_write8(adapter, REG_ATIMWND3, 0x32);
+	/*
+	rtw_write8(adapter, REG_ATIMWND4, 0x32);
+	rtw_write8(adapter, REG_ATIMWND5, 0x32);
+	rtw_write8(adapter, REG_ATIMWND6, 0x32);
+	rtw_write8(adapter, REG_ATIMWND7, 0x32);*/
+
+	/*no limit setting - 0x5A7 = 0xFF - Packet in Hi Queue Tx immediately*/
+	rtw_write8(adapter, REG_HIQ_NO_LMT_EN, 0xFF);
+
+	/*Mask all beacon*/
+	rtw_write8(adapter, REG_MBSSID_CTRL, 0);
+
+	/*BCN invalid bit setting 0x454[6] = 1*/
+	/*rtw_write8(adapter, REG_CCK_CHECK, rtw_read8(adapter, REG_CCK_CHECK) | BIT_EN_BCN_PKT_REL);*/
+
+	/*Enable Port0's beacon function*/
+	rtw_write8(adapter, REG_BCN_CTRL,
+	rtw_read8(adapter, REG_BCN_CTRL) | BIT_DIS_RX_BSSID_FIT | BIT_P0_EN_TXBCN_RPT | BIT_DIS_TSF_UDT  | BIT_EN_BCN_FUNCTION);
+
+	/* Enable HW seq for BCN
+	* 0x4FC[0]: EN_HWSEQ / 0x4FC[1]: EN_HWSEQEXT  */
+	 #ifdef CONFIG_RTL8822B
+	if (IS_HARDWARE_TYPE_8822B(adapter))
+		rtw_write8(adapter, REG_DUMMY_PAGE4_V1_8822B, 0x01);
+	#endif
+
+}
+static void _rtw_mbid_bcn_cfg(_adapter *adapter, bool mbcnq_en, u8 mbcnq_id)
+{
+	if (mbcnq_id >= CONFIG_LIMITED_AP_NUM) {
+		RTW_ERR(FUNC_ADPT_FMT"- mbid bcnq_id(%d) invalid\n", FUNC_ADPT_ARG(adapter), mbcnq_id);
+		rtw_warn_on(1);
+	}
+
+	if (mbcnq_en) {
+		rtw_write8(adapter, REG_MBSSID_CTRL,
+			rtw_read8(adapter, REG_MBSSID_CTRL) | BIT(mbcnq_id));
+		RTW_INFO(FUNC_ADPT_FMT"- mbid bcnq_id(%d) enabled\n", FUNC_ADPT_ARG(adapter), mbcnq_id);
+	} else {
+		rtw_write8(adapter, REG_MBSSID_CTRL,
+			rtw_read8(adapter, REG_MBSSID_CTRL) & (~BIT(mbcnq_id)));
+		RTW_INFO(FUNC_ADPT_FMT"- mbid bcnq_id(%d) disabled\n", FUNC_ADPT_ARG(adapter), mbcnq_id);
+	}
+}
+/*#define CONFIG_FW_TBTT_RPT*/
+void rtw_ap_mbid_bcn_en(_adapter *adapter, u8 ap_id)
+{
+	RTW_INFO(FUNC_ADPT_FMT"- ap_id(%d)\n", FUNC_ADPT_ARG(adapter), ap_id);
+
+	#ifdef CONFIG_FW_TBTT_RPT
+	if (rtw_ap_get_nums(adapter) >= 1) {
+		u8 tbtt_rpt_map = adapter_to_dvobj(adapter)->vap_tbtt_rpt_map;
+
+		rtw_hal_set_fw_ap_bcn_offload_cmd(adapter, _TRUE,
+			tbtt_rpt_map | BIT(ap_id));/*H2C-0xBA*/
+	}
+	#else
+	if (rtw_ap_get_nums(adapter) == 1)
+		rtw_hal_set_fw_ap_bcn_offload_cmd(adapter, _TRUE, 0);/*H2C-0xBA*/
+	#endif
+
+	rtw_hal_set_bcn_rsvdpage_loc_cmd(adapter);/*H2C-0x09*/
+
+	_rtw_mbid_bcn_cfg(adapter, _TRUE, ap_id);
+}
+void rtw_ap_mbid_bcn_dis(_adapter *adapter, u8 ap_id)
+{
+	RTW_INFO(FUNC_ADPT_FMT"- ap_id(%d)\n", FUNC_ADPT_ARG(adapter), ap_id);
+	_rtw_mbid_bcn_cfg(adapter, _FALSE, ap_id);
+
+	if (rtw_ap_get_nums(adapter) == 0)
+		rtw_hal_set_fw_ap_bcn_offload_cmd(adapter, _FALSE, 0);
+	#ifdef CONFIG_FW_TBTT_RPT
+	else if (rtw_ap_get_nums(adapter) >= 1) {
+		u8 tbtt_rpt_map = adapter_to_dvobj(adapter)->vap_tbtt_rpt_map;
+
+		rtw_hal_set_fw_ap_bcn_offload_cmd(adapter, _TRUE,
+			tbtt_rpt_map & ~BIT(ap_id));/*H2C-0xBA*/
+	}
+	#endif
+}
+#endif
+#ifdef CONFIG_SWTIMER_BASED_TXBCN
+void rtw_ap_multi_bcn_cfg(_adapter *adapter)
+{
+	#if defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C) || defined(CONFIG_RTL8822C)
+	rtw_write8(adapter, REG_BCN_CTRL, DIS_TSF_UDT);
+	#else
+	rtw_write8(adapter, REG_BCN_CTRL, DIS_TSF_UDT | DIS_BCNQ_SUB);
+	#endif
+	/*enable to rx data frame*/
+	rtw_write16(adapter, REG_RXFLTMAP2, 0xFFFF);
+
+	/*Beacon Control related register for first time*/
+	rtw_write8(adapter, REG_BCNDMATIM, 0x02); /* 2ms */
+
+	/*rtw_write8(Adapter, REG_BCN_MAX_ERR, 0xFF);*/
+	rtw_write8(adapter, REG_ATIMWND, 0x0c); /* 12ms */
+
+	#ifndef CONFIG_HW_P0_TSF_SYNC
+	rtw_write16(adapter, REG_TSFTR_SYN_OFFSET, 0x7fff);/* +32767 (~32ms) */
+	#endif
+
+	/*reset TSF*/
+	rtw_write8(adapter, REG_DUAL_TSF_RST, BIT(0));
+
+	/*enable BCN0 Function for if1*/
+	/*don't enable update TSF0 for if1 (due to TSF update when beacon,probe rsp are received)*/
+	#if defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C) || defined(CONFIG_RTL8822C)
+	rtw_write8(adapter, REG_BCN_CTRL, BIT_DIS_RX_BSSID_FIT | BIT_P0_EN_TXBCN_RPT | BIT_DIS_TSF_UDT |BIT_EN_BCN_FUNCTION);
+	#else
+	rtw_write8(adapter, REG_BCN_CTRL, (DIS_TSF_UDT | EN_BCN_FUNCTION | EN_TXBCN_RPT | DIS_BCNQ_SUB));
+	#endif
+	#ifdef CONFIG_BCN_XMIT_PROTECT
+	rtw_write8(adapter, REG_CCK_CHECK, rtw_read8(adapter, REG_CCK_CHECK) | BIT_EN_BCN_PKT_REL);
+	#endif
+
+	if (IS_HARDWARE_TYPE_8821(adapter) || IS_HARDWARE_TYPE_8192E(adapter))/* select BCN on port 0 for DualBeacon*/
+		rtw_write8(adapter, REG_CCK_CHECK, rtw_read8(adapter, REG_CCK_CHECK) & (~BIT_BCN_PORT_SEL));
+
+	/* Enable HW seq for BCN 
+	 * 0x4FC[0]: EN_HWSEQ / 0x4FC[1]: EN_HWSEQEXT  */
+	#ifdef CONFIG_RTL8822B
+	if (IS_HARDWARE_TYPE_8822B(adapter))
+		rtw_write8(adapter, REG_DUMMY_PAGE4_V1_8822B, 0x01);
+	#endif
+}
+#endif
+
+#ifdef CONFIG_MI_WITH_MBSSID_CAM
+void rtw_hal_set_macaddr_mbid(_adapter *adapter, u8 *mac_addr)
+{
+
+#if 0 /*TODO - modify for more flexible*/
+	u8 idx = 0;
+
+	if ((check_fwstate(&adapter->mlmepriv, WIFI_STATION_STATE) == _TRUE) &&
+	    (DEV_STA_NUM(adapter_to_dvobj(adapter)) == 1)) {
+		for (idx = 0; idx < 6; idx++)
+			rtw_write8(GET_PRIMARY_ADAPTER(adapter), (REG_MACID + idx), val[idx]);
+	}  else {
+		/*MBID entry_id = 0~7 ,0 for root AP, 1~7 for VAP*/
+		u8 entry_id;
+
+		if ((check_fwstate(&adapter->mlmepriv, WIFI_AP_STATE) == _TRUE) &&
+		    (DEV_AP_NUM(adapter_to_dvobj(adapter)) == 1)) {
+			entry_id = 0;
+			if (rtw_mbid_cam_assign(adapter, val, entry_id)) {
+				RTW_INFO(FUNC_ADPT_FMT" Root AP assigned success\n", FUNC_ADPT_ARG(adapter));
+				write_mbssid_cam(adapter, entry_id, val);
+			}
+		} else {
+			entry_id = rtw_mbid_camid_alloc(adapter, val);
+			if (entry_id != INVALID_CAM_ID)
+				write_mbssid_cam(adapter, entry_id, val);
+		}
+	}
+#else
+	{
+		/*
+			MBID entry_id = 0~7 ,for IFACE_ID0 ~ IFACE_IDx
+		*/
+		u8 entry_id = rtw_mbid_camid_alloc(adapter, mac_addr);
+
+
+		if (entry_id != INVALID_CAM_ID) {
+			write_mbssid_cam(adapter, entry_id, mac_addr);
+			RTW_INFO("%s "ADPT_FMT"- mbid(%d) mac_addr ="MAC_FMT"\n", __func__,
+				ADPT_ARG(adapter), entry_id, MAC_ARG(mac_addr));
+		}
+	}
+#endif
+}
+
+void rtw_hal_change_macaddr_mbid(_adapter *adapter, u8 *mac_addr)
+{
+	u8 idx = 0;
+	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
+	u8 entry_id;
+
+	if (!mac_addr) {
+		rtw_warn_on(1);
+		return;
+	}
+
+
+	entry_id = rtw_mbid_cam_info_change(adapter, mac_addr);
+
+	if (entry_id != INVALID_CAM_ID)
+		write_mbssid_cam(adapter, entry_id, mac_addr);
+}
+
+#ifdef CONFIG_SWTIMER_BASED_TXBCN
+u16 rtw_hal_bcn_interval_adjust(_adapter *adapter, u16 bcn_interval)
+{
+	if (adapter_to_dvobj(adapter)->inter_bcn_space != bcn_interval)
+		return adapter_to_dvobj(adapter)->inter_bcn_space;
+	else
+		return bcn_interval;
+}
+#endif/*CONFIG_SWTIMER_BASED_TXBCN*/
+
+#endif/*#ifdef CONFIG_MI_WITH_MBSSID_CAM*/
+
+static void rtw_hal_set_macaddr_port(_adapter *adapter, u8 *val)
+{
+	u8 idx = 0;
+	u32 reg_macid = 0;
+	enum _hw_port hwport;
+
+	if (val == NULL)
+		return;
+	hwport = get_hw_port(adapter);
+
+	RTW_INFO("%s "ADPT_FMT"- hw port(%d) mac_addr ="MAC_FMT"\n",  __func__,
+		 ADPT_ARG(adapter), hwport, MAC_ARG(val));
+
+#ifdef RTW_HALMAC
+	rtw_halmac_set_mac_address(adapter_to_dvobj(adapter), hwport, val);
+#else /* !RTW_HALMAC */
+	switch (hwport) {
+	case HW_PORT0:
+	default:
+		reg_macid = REG_MACID;
+		break;
+	case HW_PORT1:
+		reg_macid = REG_MACID1;
+		break;
+#if defined(CONFIG_RTL8814A)
+	case HW_PORT2:
+		reg_macid = REG_MACID2;
+		break;
+	case HW_PORT3:
+		reg_macid = REG_MACID3;
+		break;
+	case HW_PORT4:
+		reg_macid = REG_MACID4;
+		break;
+#endif/*defined(CONFIG_RTL8814A)*/
+	}
+
+	for (idx = 0; idx < ETH_ALEN; idx++)
+		rtw_write8(GET_PRIMARY_ADAPTER(adapter), (reg_macid + idx), val[idx]);
+#endif /* !RTW_HALMAC */
+}
+
+static void rtw_hal_get_macaddr_port(_adapter *adapter, u8 *mac_addr)
+{
+	u8 idx = 0;
+	u32 reg_macid = 0;
+
+	if (mac_addr == NULL)
+		return;
+
+	_rtw_memset(mac_addr, 0, ETH_ALEN);
+#ifdef RTW_HALMAC
+	rtw_halmac_get_mac_address(adapter_to_dvobj(adapter), adapter->hw_port, mac_addr);
+#else /* !RTW_HALMAC */
+	switch (adapter->hw_port) {
+	case HW_PORT0:
+	default:
+		reg_macid = REG_MACID;
+		break;
+	case HW_PORT1:
+		reg_macid = REG_MACID1;
+		break;
+#if defined(CONFIG_RTL8814A)
+	case HW_PORT2:
+		reg_macid = REG_MACID2;
+		break;
+	case HW_PORT3:
+		reg_macid = REG_MACID3;
+		break;
+	case HW_PORT4:
+		reg_macid = REG_MACID4;
+		break;
+#endif /*defined(CONFIG_RTL8814A)*/
+	}
+
+	for (idx = 0; idx < ETH_ALEN; idx++)
+		mac_addr[idx] = rtw_read8(GET_PRIMARY_ADAPTER(adapter), (reg_macid + idx));
+#endif /* !RTW_HALMAC */
+
+	RTW_INFO("%s "ADPT_FMT"- hw port(%d) mac_addr ="MAC_FMT"\n",  __func__,
+		 ADPT_ARG(adapter), adapter->hw_port, MAC_ARG(mac_addr));
+}
+
+static void rtw_hal_set_bssid(_adapter *adapter, u8 *val)
+{
+	u8 hw_port = rtw_hal_get_port(adapter);
+
+#ifdef RTW_HALMAC
+	rtw_halmac_set_bssid(adapter_to_dvobj(adapter), hw_port, val);
+#else /* !RTW_HALMAC */
+	u8	idx = 0;
+	u32 reg_bssid = 0;
+
+	switch (hw_port) {
+	case HW_PORT0:
+	default:
+		reg_bssid = REG_BSSID;
+		break;
+	case HW_PORT1:
+		reg_bssid = REG_BSSID1;
+		break;
+#if defined(CONFIG_RTL8814A)
+	case HW_PORT2:
+		reg_bssid = REG_BSSID2;
+		break;
+	case HW_PORT3:
+		reg_bssid = REG_BSSID3;
+		break;
+	case HW_PORT4:
+		reg_bssid = REG_BSSID4;
+		break;
+#endif/*defined(CONFIG_RTL8814A)*/
+	}
+
+	for (idx = 0 ; idx < ETH_ALEN; idx++)
+		rtw_write8(adapter, (reg_bssid + idx), val[idx]);
+#endif /* !RTW_HALMAC */
+
+	RTW_INFO("%s "ADPT_FMT"- hw port -%d BSSID: "MAC_FMT"\n",
+		__func__, ADPT_ARG(adapter), hw_port, MAC_ARG(val));
+}
+
+static void rtw_hal_set_tsf_update(_adapter *adapter, u8 en)
+{
+	u32 addr = 0;
+	u8 val8;
+
+	rtw_hal_get_hwreg(adapter, HW_VAR_BCN_CTRL_ADDR, (u8 *)&addr);
+	if (addr) {
+		val8 = rtw_read8(adapter, addr);
+		if (en && (val8 & DIS_TSF_UDT)) {
+			rtw_write8(adapter, addr, val8 & ~DIS_TSF_UDT);
+			#ifdef DBG_TSF_UPDATE
+			RTW_INFO("port%u("ADPT_FMT") enable TSF update\n", adapter->hw_port, ADPT_ARG(adapter));
+			#endif
+		}
+		if (!en && !(val8 & DIS_TSF_UDT)) {
+			rtw_write8(adapter, addr, val8 | DIS_TSF_UDT);
+			#ifdef DBG_TSF_UPDATE
+			RTW_INFO("port%u("ADPT_FMT") disable TSF update\n", adapter->hw_port, ADPT_ARG(adapter));
+			#endif
+		}
+	} else {
+		RTW_WARN("unknown port%d("ADPT_FMT") %s TSF update\n"
+			, adapter->hw_port, ADPT_ARG(adapter), en ? "enable" : "disable");
+		rtw_warn_on(1);
+	}
+}
+
+static void rtw_hal_set_hw_update_tsf(PADAPTER padapter)
+{
+	struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
+	struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
+
+#if defined(CONFIG_RTL8822B) || defined(CONFIG_MI_WITH_MBSSID_CAM)
+	RTW_INFO("[Warn] %s "ADPT_FMT" enter func\n", __func__, ADPT_ARG(padapter));
+	rtw_warn_on(1);
+	return;
+#endif
+
+	if (!pmlmeext->en_hw_update_tsf)
+		return;
+
+	/* check RCR */
+	if (!rtw_hal_rcr_check(padapter, RCR_CBSSID_BCN))
+		return;
+
+	if (pmlmeext->tsf_update_required) {
+		pmlmeext->tsf_update_pause_stime = 0;
+		rtw_hal_set_tsf_update(padapter, 1);
+	}
+
+	pmlmeext->en_hw_update_tsf = 0;
+}
+
+void rtw_iface_enable_tsf_update(_adapter *adapter)
+{
+	adapter->mlmeextpriv.tsf_update_pause_stime = 0;
+	adapter->mlmeextpriv.tsf_update_required = 1;
+#ifdef CONFIG_MI_WITH_MBSSID_CAM
+
+#else
+	rtw_hal_set_tsf_update(adapter, 1);
+#endif
+}
+
+void rtw_iface_disable_tsf_update(_adapter *adapter)
+{
+	adapter->mlmeextpriv.tsf_update_required = 0;
+	adapter->mlmeextpriv.tsf_update_pause_stime = 0;
+	adapter->mlmeextpriv.en_hw_update_tsf = 0;
+#ifdef CONFIG_MI_WITH_MBSSID_CAM
+
+#else
+	rtw_hal_set_tsf_update(adapter, 0);
+#endif
+}
+
+static void rtw_hal_tsf_update_pause(_adapter *adapter)
+{
+#ifdef CONFIG_MI_WITH_MBSSID_CAM
+
+#else
+	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
+	_adapter *iface;
+	int i;
+	u8 val8;
+
+	for (i = 0; i < dvobj->iface_nums; i++) {
+		iface = dvobj->padapters[i];
+		if (!iface)
+			continue;
+
+		rtw_hal_set_tsf_update(iface, 0);
+		if (iface->mlmeextpriv.tsf_update_required) {
+			iface->mlmeextpriv.tsf_update_pause_stime = rtw_get_current_time();
+			if (!iface->mlmeextpriv.tsf_update_pause_stime)
+				iface->mlmeextpriv.tsf_update_pause_stime++;
+		}
+		iface->mlmeextpriv.en_hw_update_tsf = 0;
+	}
+#endif
+}
+
+static void rtw_hal_tsf_update_restore(_adapter *adapter)
+{
+#ifdef CONFIG_MI_WITH_MBSSID_CAM
+
+#else
+	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
+	_adapter *iface;
+	int i;
+
+	for (i = 0; i < dvobj->iface_nums; i++) {
+		iface = dvobj->padapters[i];
+		if (!iface)
+			continue;
+
+		if (iface->mlmeextpriv.tsf_update_required) {
+			/* enable HW TSF update when recive beacon*/
+			iface->mlmeextpriv.en_hw_update_tsf = 1;
+			#ifdef DBG_TSF_UPDATE
+			RTW_INFO("port%d("ADPT_FMT") enabling TSF update...\n"
+				, iface->hw_port, ADPT_ARG(iface));
+			#endif
+		}
+	}
+#endif
+}
+
+void rtw_hal_periodic_tsf_update_chk(_adapter *adapter)
+{
+#ifdef CONFIG_MI_WITH_MBSSID_CAM
+
+#else
+	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
+	_adapter *iface;
+	struct mlme_ext_priv *mlmeext;
+	int i;
+	u32 restore_ms = 0;
+
+	if (dvobj->periodic_tsf_update_etime) {
+		if (rtw_time_after(rtw_get_current_time(), dvobj->periodic_tsf_update_etime)) {
+			/* end for restore status */
+			dvobj->periodic_tsf_update_etime = 0;
+			rtw_hal_rcr_set_chk_bssid(adapter, MLME_ACTION_NONE);
+		}
+		return;
+	}
+
+	if (dvobj->rf_ctl.offch_state != OFFCHS_NONE)
+		return;
+
+	/*
+	* all required ifaces can switch to restore status together
+	* loop all pause iface to get largest restore time required
+	*/
+	for (i = 0; i < dvobj->iface_nums; i++) {
+		iface = dvobj->padapters[i];
+		if (!iface)
+			continue;
+
+		mlmeext = &iface->mlmeextpriv;
+
+		if (mlmeext->tsf_update_required
+			&& mlmeext->tsf_update_pause_stime
+			&& rtw_get_passing_time_ms(mlmeext->tsf_update_pause_stime)
+				> mlmeext->mlmext_info.bcn_interval * mlmeext->tsf_update_pause_factor
+		) {
+			if (restore_ms < mlmeext->mlmext_info.bcn_interval * mlmeext->tsf_update_restore_factor)
+				restore_ms = mlmeext->mlmext_info.bcn_interval * mlmeext->tsf_update_restore_factor;
+		}
+	}
+
+	if (!restore_ms)
+		return;
+
+	dvobj->periodic_tsf_update_etime = rtw_get_current_time() + rtw_ms_to_systime(restore_ms);
+	if (!dvobj->periodic_tsf_update_etime)
+		dvobj->periodic_tsf_update_etime++;
+
+	rtw_hal_rcr_set_chk_bssid(adapter, MLME_ACTION_NONE);
+
+	/* set timer to end restore status */
+	_set_timer(&dvobj->periodic_tsf_update_end_timer, restore_ms);
+#endif
+}
+
+void rtw_hal_periodic_tsf_update_end_timer_hdl(void *ctx)
+{
+	struct dvobj_priv *dvobj = (struct dvobj_priv *)ctx;
+
+	if (dev_is_surprise_removed(dvobj) || dev_is_drv_stopped(dvobj))
+		return;
+
+	rtw_periodic_tsf_update_end_cmd(dvobj_get_primary_adapter(dvobj));
+}
+
+static inline u8 hw_var_rcr_config(_adapter *adapter, u32 rcr)
+{
+	int err;
+
+	err = rtw_write32(adapter, REG_RCR, rcr);
+	if (err == _SUCCESS)
+		GET_HAL_DATA(adapter)->ReceiveConfig = rcr;
+	return err;
+}
+
+static inline u8 hw_var_rcr_get(_adapter *adapter, u32 *rcr)
+{
+	u32 v32;
+
+	v32 = rtw_read32(adapter, REG_RCR);
+	if (rcr)
+		*rcr = v32;
+	GET_HAL_DATA(adapter)->ReceiveConfig = v32;
+	return _SUCCESS;
+}
+
+/* only check SW RCR variable */
+inline u8 rtw_hal_rcr_check(_adapter *adapter, u32 check_bit)
+{
+	PHAL_DATA_TYPE hal;
+	u32 rcr;
+
+	hal = GET_HAL_DATA(adapter);
+
+	rcr = hal->ReceiveConfig;
+	if ((rcr & check_bit) == check_bit)
+		return 1;
+
+	return 0;
+}
+
+inline u8 rtw_hal_rcr_add(_adapter *adapter, u32 add)
+{
+	PHAL_DATA_TYPE hal;
+	u32 rcr;
+	u8 ret = _SUCCESS;
+
+	hal = GET_HAL_DATA(adapter);
+
+	rtw_hal_get_hwreg(adapter, HW_VAR_RCR, (u8 *)&rcr);
+	rcr |= add;
+	if (rcr != hal->ReceiveConfig)
+		ret = rtw_hal_set_hwreg(adapter, HW_VAR_RCR, (u8 *)&rcr);
+
+	return ret;
+}
+
+inline u8 rtw_hal_rcr_clear(_adapter *adapter, u32 clear)
+{
+	PHAL_DATA_TYPE hal;
+	u32 rcr;
+	u8 ret = _SUCCESS;
+
+	hal = GET_HAL_DATA(adapter);
+
+	rtw_hal_get_hwreg(adapter, HW_VAR_RCR, (u8 *)&rcr);
+	rcr &= ~clear;
+	if (rcr != hal->ReceiveConfig)
+		ret = rtw_hal_set_hwreg(adapter, HW_VAR_RCR, (u8 *)&rcr);
+
+	return ret;
+}
+
+void rtw_hal_rcr_set_chk_bssid(_adapter *adapter, u8 self_action)
+{
+	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
+	struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter);
+	u32 rcr, rcr_new;
+	struct mi_state mstate, mstate_s;
+
+	rtw_hal_get_hwreg(adapter, HW_VAR_RCR, (u8 *)&rcr);
+	rcr_new = rcr;
+
+#if defined(CONFIG_MI_WITH_MBSSID_CAM) && !defined(CONFIG_CLIENT_PORT_CFG)
+	rcr_new &= ~(RCR_CBSSID_BCN | RCR_CBSSID_DATA);
+#else
+	rtw_mi_status_no_self(adapter, &mstate);
+	rtw_mi_status_no_others(adapter, &mstate_s);
+
+	/* only adjust parameters interested */
+	switch (self_action) {
+	case MLME_SCAN_ENTER:
+		mstate_s.scan_num = 1;
+		mstate_s.scan_enter_num = 1;
+		break;
+	case MLME_SCAN_DONE:
+		mstate_s.scan_enter_num = 0;
+		break;
+	case MLME_STA_CONNECTING:
+		mstate_s.lg_sta_num = 1;
+		mstate_s.ld_sta_num = 0;
+		break;
+	case MLME_STA_CONNECTED:
+		mstate_s.lg_sta_num = 0;
+		mstate_s.ld_sta_num = 1;
+		break;
+	case MLME_STA_DISCONNECTED:
+		mstate_s.lg_sta_num = 0;
+		mstate_s.ld_sta_num = 0;
+		break;
+#ifdef CONFIG_TDLS
+	case MLME_TDLS_LINKED:
+		mstate_s.ld_tdls_num = 1;
+		break;
+	case MLME_TDLS_NOLINK:
+		mstate_s.ld_tdls_num = 0;
+		break;
+#endif
+#ifdef CONFIG_AP_MODE
+	case MLME_AP_STARTED:
+		mstate_s.ap_num = 1;
+		break;
+	case MLME_AP_STOPPED:
+		mstate_s.ap_num = 0;
+		mstate_s.ld_ap_num = 0;
+		break;
+#endif
+#ifdef CONFIG_RTW_MESH
+	case MLME_MESH_STARTED:
+		mstate_s.mesh_num = 1;
+		break;
+	case MLME_MESH_STOPPED:
+		mstate_s.mesh_num = 0;
+		mstate_s.ld_mesh_num = 0;
+		break;
+#endif
+	case MLME_ACTION_NONE:
+	case MLME_ADHOC_STARTED:
+		/* caller without effect of decision */
+		break;
+	default:
+		rtw_warn_on(1);
+	};
+
+	rtw_mi_status_merge(&mstate, &mstate_s);
+
+	if (MSTATE_AP_NUM(&mstate) || MSTATE_MESH_NUM(&mstate) || MSTATE_TDLS_LD_NUM(&mstate)
+		#ifdef CONFIG_FIND_BEST_CHANNEL
+		|| MSTATE_SCAN_ENTER_NUM(&mstate)
+		#endif
+		|| hal_data->in_cta_test
+	)
+		rcr_new &= ~RCR_CBSSID_DATA;
+	else
+		rcr_new |= RCR_CBSSID_DATA;
+
+	if (MSTATE_SCAN_ENTER_NUM(&mstate) || hal_data->in_cta_test)
+		rcr_new &= ~RCR_CBSSID_BCN;
+	else if (MSTATE_STA_LG_NUM(&mstate)
+		|| adapter_to_dvobj(adapter)->periodic_tsf_update_etime
+	)
+		rcr_new |= RCR_CBSSID_BCN;
+	else if ((MSTATE_AP_NUM(&mstate) && adapter->registrypriv.wifi_spec) /* for 11n Logo 4.2.31/4.2.32 */
+		|| MSTATE_MESH_NUM(&mstate)
+	)
+		rcr_new &= ~RCR_CBSSID_BCN;	
+	else
+		rcr_new |= RCR_CBSSID_BCN;
+
+	#ifdef CONFIG_CLIENT_PORT_CFG
+	if (get_clt_num(adapter) > MAX_CLIENT_PORT_NUM)
+		rcr_new &= ~RCR_CBSSID_BCN;
+	#endif
+#endif /* CONFIG_MI_WITH_MBSSID_CAM */
+
+	if (rcr == rcr_new)
+		return;
+
+	if (!hal_spec->rx_tsf_filter
+		&& (rcr & RCR_CBSSID_BCN) && !(rcr_new & RCR_CBSSID_BCN))
+		rtw_hal_tsf_update_pause(adapter);
+
+	rtw_hal_set_hwreg(adapter, HW_VAR_RCR, (u8 *)&rcr_new);
+
+	if (!hal_spec->rx_tsf_filter
+		&& !(rcr & RCR_CBSSID_BCN) && (rcr_new & RCR_CBSSID_BCN)
+		&& self_action != MLME_STA_CONNECTING)
+		rtw_hal_tsf_update_restore(adapter);
+}
+
+static void hw_var_set_rcr_am(_adapter *adapter, u8 enable)
+{
+	u32 rcr = RCR_AM;
+
+	if (enable)
+		rtw_hal_rcr_add(adapter, rcr);
+	else
+		rtw_hal_rcr_clear(adapter, rcr);
+}
+
+static void hw_var_set_bcn_interval(_adapter *adapter, u16 interval)
+{
+#ifdef CONFIG_SWTIMER_BASED_TXBCN
+	interval = rtw_hal_bcn_interval_adjust(adapter, interval);
+#endif
+
+#ifdef RTW_HALMAC
+	rtw_halmac_set_bcn_interval(adapter_to_dvobj(adapter), adapter->hw_port, interval);
+#else
+	rtw_write16(adapter, REG_MBSSID_BCN_SPACE, interval);
+#endif
+
+#ifdef CONFIG_INTERRUPT_BASED_TXBCN_EARLY_INT
+	{
+		struct mlme_ext_priv	*pmlmeext = &adapter->mlmeextpriv;
+		struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
+
+		if ((pmlmeinfo->state & 0x03) == WIFI_FW_AP_STATE) {
+			RTW_INFO("%s==> bcn_interval:%d, eraly_int:%d\n", __func__, interval, interval >> 1);
+			rtw_write8(adapter, REG_DRVERLYINT, interval >> 1);
+		}
+	}
+#endif
+}
+
+void hw_var_port_switch(_adapter *adapter)
+{
+#ifdef CONFIG_CONCURRENT_MODE
+#ifdef CONFIG_RUNTIME_PORT_SWITCH
+	/*
+	0x102: MSR
+	0x550: REG_BCN_CTRL
+	0x551: REG_BCN_CTRL_1
+	0x55A: REG_ATIMWND
+	0x560: REG_TSFTR
+	0x568: REG_TSFTR1
+	0x570: REG_ATIMWND_1
+	0x610: REG_MACID
+	0x618: REG_BSSID
+	0x700: REG_MACID1
+	0x708: REG_BSSID1
+	*/
+
+	int i;
+	u8 msr;
+	u8 bcn_ctrl;
+	u8 bcn_ctrl_1;
+	u8 atimwnd[2];
+	u8 atimwnd_1[2];
+	u8 tsftr[8];
+	u8 tsftr_1[8];
+	u8 macid[6];
+	u8 bssid[6];
+	u8 macid_1[6];
+	u8 bssid_1[6];
+#if defined(CONFIG_RTL8192F)
+	u16 wlan_act_mask_ctrl = 0;
+	u16 en_port_mask = EN_PORT_0_FUNCTION | EN_PORT_1_FUNCTION;
+#endif
+
+	u8 hw_port;
+	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
+	_adapter *iface = NULL;
+
+	msr = rtw_read8(adapter, MSR);
+	bcn_ctrl = rtw_read8(adapter, REG_BCN_CTRL);
+	bcn_ctrl_1 = rtw_read8(adapter, REG_BCN_CTRL_1);
+#if defined(CONFIG_RTL8192F)
+	wlan_act_mask_ctrl = rtw_read16(adapter, REG_WLAN_ACT_MASK_CTRL_1);
+#endif
+
+	for (i = 0; i < 2; i++)
+		atimwnd[i] = rtw_read8(adapter, REG_ATIMWND + i);
+	for (i = 0; i < 2; i++)
+		atimwnd_1[i] = rtw_read8(adapter, REG_ATIMWND_1 + i);
+
+	for (i = 0; i < 8; i++)
+		tsftr[i] = rtw_read8(adapter, REG_TSFTR + i);
+	for (i = 0; i < 8; i++)
+		tsftr_1[i] = rtw_read8(adapter, REG_TSFTR1 + i);
+
+	for (i = 0; i < 6; i++)
+		macid[i] = rtw_read8(adapter, REG_MACID + i);
+
+	for (i = 0; i < 6; i++)
+		bssid[i] = rtw_read8(adapter, REG_BSSID + i);
+
+	for (i = 0; i < 6; i++)
+		macid_1[i] = rtw_read8(adapter, REG_MACID1 + i);
+
+	for (i = 0; i < 6; i++)
+		bssid_1[i] = rtw_read8(adapter, REG_BSSID1 + i);
+
+#ifdef DBG_RUNTIME_PORT_SWITCH
+	RTW_INFO(FUNC_ADPT_FMT" before switch\n"
+		 "msr:0x%02x\n"
+		 "bcn_ctrl:0x%02x\n"
+		 "bcn_ctrl_1:0x%02x\n"
+#if defined(CONFIG_RTL8192F)
+		 "wlan_act_mask_ctrl:0x%02x\n"
+#endif
+		 "atimwnd:0x%04x\n"
+		 "atimwnd_1:0x%04x\n"
+		 "tsftr:%llu\n"
+		 "tsftr1:%llu\n"
+		 "macid:"MAC_FMT"\n"
+		 "bssid:"MAC_FMT"\n"
+		 "macid_1:"MAC_FMT"\n"
+		 "bssid_1:"MAC_FMT"\n"
+		 , FUNC_ADPT_ARG(adapter)
+		 , msr
+		 , bcn_ctrl
+		 , bcn_ctrl_1
+#if defined(CONFIG_RTL8192F)
+		 , wlan_act_mask_ctrl
+#endif
+		 , *((u16 *)atimwnd)
+		 , *((u16 *)atimwnd_1)
+		 , *((u64 *)tsftr)
+		 , *((u64 *)tsftr_1)
+		 , MAC_ARG(macid)
+		 , MAC_ARG(bssid)
+		 , MAC_ARG(macid_1)
+		 , MAC_ARG(bssid_1)
+		);
+#endif /* DBG_RUNTIME_PORT_SWITCH */
+
+	/* disable bcn function, disable update TSF */
+	rtw_write8(adapter, REG_BCN_CTRL, (bcn_ctrl & (~EN_BCN_FUNCTION)) | DIS_TSF_UDT);
+	rtw_write8(adapter, REG_BCN_CTRL_1, (bcn_ctrl_1 & (~EN_BCN_FUNCTION)) | DIS_TSF_UDT);
+
+#if defined(CONFIG_RTL8192F)
+	rtw_write16(adapter, REG_WLAN_ACT_MASK_CTRL_1, wlan_act_mask_ctrl & ~en_port_mask);
+#endif
+
+	/* switch msr */
+	msr = (msr & 0xf0) | ((msr & 0x03) << 2) | ((msr & 0x0c) >> 2);
+	rtw_write8(adapter, MSR, msr);
+
+	/* write port0 */
+	rtw_write8(adapter, REG_BCN_CTRL, bcn_ctrl_1 & ~EN_BCN_FUNCTION);
+	for (i = 0; i < 2; i++)
+		rtw_write8(adapter, REG_ATIMWND + i, atimwnd_1[i]);
+	for (i = 0; i < 8; i++)
+		rtw_write8(adapter, REG_TSFTR + i, tsftr_1[i]);
+	for (i = 0; i < 6; i++)
+		rtw_write8(adapter, REG_MACID + i, macid_1[i]);
+	for (i = 0; i < 6; i++)
+		rtw_write8(adapter, REG_BSSID + i, bssid_1[i]);
+
+	/* write port1 */
+	rtw_write8(adapter, REG_BCN_CTRL_1, bcn_ctrl & ~EN_BCN_FUNCTION);
+	for (i = 0; i < 2; i++)
+		rtw_write8(adapter, REG_ATIMWND_1 + i, atimwnd[i]);
+	for (i = 0; i < 8; i++)
+		rtw_write8(adapter, REG_TSFTR1 + i, tsftr[i]);
+	for (i = 0; i < 6; i++)
+		rtw_write8(adapter, REG_MACID1 + i, macid[i]);
+	for (i = 0; i < 6; i++)
+		rtw_write8(adapter, REG_BSSID1 + i, bssid[i]);
+
+	/* write bcn ctl */
+#ifdef CONFIG_BT_COEXIST
+	/* always enable port0 beacon function for PSTDMA */
+	if (IS_HARDWARE_TYPE_8723B(adapter) || IS_HARDWARE_TYPE_8703B(adapter)
+	    || IS_HARDWARE_TYPE_8723D(adapter))
+		bcn_ctrl_1 |= EN_BCN_FUNCTION;
+	/* always disable port1 beacon function for PSTDMA */
+	if (IS_HARDWARE_TYPE_8723B(adapter) || IS_HARDWARE_TYPE_8703B(adapter))
+		bcn_ctrl &= ~EN_BCN_FUNCTION;
+#endif
+	rtw_write8(adapter, REG_BCN_CTRL, bcn_ctrl_1);
+	rtw_write8(adapter, REG_BCN_CTRL_1, bcn_ctrl);
+
+#if defined(CONFIG_RTL8192F)
+	/* if the setting of port0 and port1 are the same, it does not need to switch port setting*/
+	if(((wlan_act_mask_ctrl & en_port_mask) != 0) && ((wlan_act_mask_ctrl & en_port_mask)
+		!= (EN_PORT_0_FUNCTION | EN_PORT_1_FUNCTION)))
+		wlan_act_mask_ctrl ^= en_port_mask;
+	rtw_write16(adapter, REG_WLAN_ACT_MASK_CTRL_1, wlan_act_mask_ctrl);
+#endif
+
+	if (adapter->iface_id == IFACE_ID0)
+		iface = dvobj->padapters[IFACE_ID1];
+	else if (adapter->iface_id == IFACE_ID1)
+		iface = dvobj->padapters[IFACE_ID0];
+
+
+	if (adapter->hw_port == HW_PORT0) {
+		adapter->hw_port = HW_PORT1;
+		iface->hw_port = HW_PORT0;
+		RTW_PRINT("port switch - port0("ADPT_FMT"), port1("ADPT_FMT")\n",
+			  ADPT_ARG(iface), ADPT_ARG(adapter));
+	} else {
+		adapter->hw_port = HW_PORT0;
+		iface->hw_port = HW_PORT1;
+		RTW_PRINT("port switch - port0("ADPT_FMT"), port1("ADPT_FMT")\n",
+			  ADPT_ARG(adapter), ADPT_ARG(iface));
+	}
+
+#ifdef DBG_RUNTIME_PORT_SWITCH
+	msr = rtw_read8(adapter, MSR);
+	bcn_ctrl = rtw_read8(adapter, REG_BCN_CTRL);
+	bcn_ctrl_1 = rtw_read8(adapter, REG_BCN_CTRL_1);
+#if defined(CONFIG_RTL8192F)
+	wlan_act_mask_ctrl = rtw_read16(adapter, REG_WLAN_ACT_MASK_CTRL_1);
+#endif
+
+	for (i = 0; i < 2; i++)
+		atimwnd[i] = rtw_read8(adapter, REG_ATIMWND + i);
+	for (i = 0; i < 2; i++)
+		atimwnd_1[i] = rtw_read8(adapter, REG_ATIMWND_1 + i);
+
+	for (i = 0; i < 8; i++)
+		tsftr[i] = rtw_read8(adapter, REG_TSFTR + i);
+	for (i = 0; i < 8; i++)
+		tsftr_1[i] = rtw_read8(adapter, REG_TSFTR1 + i);
+
+	for (i = 0; i < 6; i++)
+		macid[i] = rtw_read8(adapter, REG_MACID + i);
+
+	for (i = 0; i < 6; i++)
+		bssid[i] = rtw_read8(adapter, REG_BSSID + i);
+
+	for (i = 0; i < 6; i++)
+		macid_1[i] = rtw_read8(adapter, REG_MACID1 + i);
+
+	for (i = 0; i < 6; i++)
+		bssid_1[i] = rtw_read8(adapter, REG_BSSID1 + i);
+
+	RTW_INFO(FUNC_ADPT_FMT" after switch\n"
+		 "msr:0x%02x\n"
+		 "bcn_ctrl:0x%02x\n"
+		 "bcn_ctrl_1:0x%02x\n"
+#if defined(CONFIG_RTL8192F)
+		 "wlan_act_mask_ctrl:0x%02x\n"
+#endif
+		 "atimwnd:%u\n"
+		 "atimwnd_1:%u\n"
+		 "tsftr:%llu\n"
+		 "tsftr1:%llu\n"
+		 "macid:"MAC_FMT"\n"
+		 "bssid:"MAC_FMT"\n"
+		 "macid_1:"MAC_FMT"\n"
+		 "bssid_1:"MAC_FMT"\n"
+		 , FUNC_ADPT_ARG(adapter)
+		 , msr
+		 , bcn_ctrl
+		 , bcn_ctrl_1
+#if defined(CONFIG_RTL8192F)
+		 , wlan_act_mask_ctrl
+#endif
+		 , *((u16 *)atimwnd)
+		 , *((u16 *)atimwnd_1)
+		 , *((u64 *)tsftr)
+		 , *((u64 *)tsftr_1)
+		 , MAC_ARG(macid)
+		 , MAC_ARG(bssid)
+		 , MAC_ARG(macid_1)
+		 , MAC_ARG(bssid_1)
+		);
+#endif /* DBG_RUNTIME_PORT_SWITCH */
+
+#endif /* CONFIG_RUNTIME_PORT_SWITCH */
+#endif /* CONFIG_CONCURRENT_MODE */
+}
+
+const char *const _h2c_msr_role_str[] = {
+	"RSVD",
+	"STA",
+	"AP",
+	"GC",
+	"GO",
+	"TDLS",
+	"ADHOC",
+	"MESH",
+	"INVALID",
+};
+
+#ifdef CONFIG_FW_MULTI_PORT_SUPPORT
+s32 rtw_hal_set_default_port_id_cmd(_adapter *adapter, u8 mac_id)
+{
+	s32 ret = _SUCCESS;
+	u8 parm[H2C_DEFAULT_PORT_ID_LEN] = {0};
+	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
+	u8 port_id = rtw_hal_get_port(adapter);
+
+	if ((dvobj->dft.port_id == port_id) && (dvobj->dft.mac_id == mac_id))
+		return ret;
+
+	SET_H2CCMD_DFTPID_PORT_ID(parm, port_id);
+	SET_H2CCMD_DFTPID_MAC_ID(parm, mac_id);
+
+	RTW_DBG_DUMP("DFT port id parm:", parm, H2C_DEFAULT_PORT_ID_LEN);
+	RTW_INFO("%s ("ADPT_FMT") port_id :%d, mad_id:%d\n",
+		__func__, ADPT_ARG(adapter), port_id, mac_id);
+
+	ret = rtw_hal_fill_h2c_cmd(adapter, H2C_DEFAULT_PORT_ID, H2C_DEFAULT_PORT_ID_LEN, parm);
+	dvobj->dft.port_id = port_id;
+	dvobj->dft.mac_id = mac_id;
+
+	return ret;
+}
+s32 rtw_set_default_port_id(_adapter *adapter)
+{
+	s32 ret = _SUCCESS;
+	struct sta_info		*psta;
+	struct mlme_priv *pmlmepriv = &adapter->mlmepriv;
+
+	if (is_client_associated_to_ap(adapter)) {
+		psta = rtw_get_stainfo(&adapter->stapriv, get_bssid(pmlmepriv));
+		if (psta)
+			ret = rtw_hal_set_default_port_id_cmd(adapter, psta->cmn.mac_id);
+	} else if (check_fwstate(pmlmepriv, WIFI_AP_STATE) == _TRUE) {
+
+	} else {
+	}
+
+	return ret;
+}
+s32 rtw_set_ps_rsvd_page(_adapter *adapter)
+{
+	s32 ret = _SUCCESS;
+	u16 media_status_rpt = RT_MEDIA_CONNECT;
+	struct pwrctrl_priv *pwrctl = adapter_to_pwrctl(adapter);
+
+	if (adapter->iface_id == pwrctl->fw_psmode_iface_id)
+		return ret;
+
+	rtw_hal_set_hwreg(adapter, HW_VAR_H2C_FW_JOINBSSRPT,
+			  (u8 *)&media_status_rpt);
+
+	return ret;
+}
+
+#if 0
+_adapter * _rtw_search_dp_iface(_adapter *adapter)
+{
+	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
+	_adapter *iface;
+	_adapter *target_iface = NULL;
+	int i;
+	u8 sta_num = 0, tdls_num = 0, ap_num = 0, mesh_num = 0, adhoc_num = 0;
+	u8 p2p_go_num = 0, p2p_gc_num = 0;
+	_adapter *sta_ifs[8];
+	_adapter *ap_ifs[8];
+	_adapter *mesh_ifs[8];
+	_adapter *gc_ifs[8];
+	_adapter *go_ifs[8];
+
+	for (i = 0; i < dvobj->iface_nums; i++) {
+		iface = dvobj->padapters[i];
+
+		if (check_fwstate(&iface->mlmepriv, WIFI_STATION_STATE) == _TRUE) {
+			if (check_fwstate(&iface->mlmepriv, _FW_LINKED) == _TRUE) {
+				sta_ifs[sta_num++] = iface;
+
+				#ifdef CONFIG_TDLS
+				if (iface->tdlsinfo.link_established == _TRUE)
+					tdls_num++;
+				#endif
+				#ifdef CONFIG_P2P
+				if (MLME_IS_GC(iface))
+					gc_ifs[p2p_gc_num++] = iface;
+				#endif
+			}
+#ifdef CONFIG_AP_MODE
+		} else if (check_fwstate(&iface->mlmepriv, WIFI_AP_STATE) == _TRUE ) {
+			if (check_fwstate(&iface->mlmepriv, _FW_LINKED) == _TRUE) {
+				ap_ifs[ap_num++] = iface;
+				#ifdef CONFIG_P2P
+				if (MLME_IS_GO(iface))
+					go_ifs[p2p_go_num++] = iface;
+				#endif
+			}
+#endif
+		} else if (check_fwstate(&iface->mlmepriv, WIFI_ADHOC_STATE | WIFI_ADHOC_MASTER_STATE) == _TRUE
+			&& check_fwstate(&iface->mlmepriv, _FW_LINKED) == _TRUE
+		) {
+			adhoc_num++;
+
+#ifdef CONFIG_RTW_MESH
+		} else if (check_fwstate(&iface->mlmepriv, WIFI_MESH_STATE) == _TRUE
+			&& check_fwstate(&iface->mlmepriv, _FW_LINKED) == _TRUE
+		) {
+			mesh_ifs[mesh_num++] = iface;
+#endif
+		}
+	}
+
+	if (p2p_gc_num) {
+		target_iface = gc_ifs[0];
+	}
+	else if (sta_num) {
+		if(sta_num == 1) {
+			target_iface = sta_ifs[0];
+		} else if (sta_num >= 2) {
+			/*TODO get target_iface by timestamp*/
+			target_iface = sta_ifs[0];
+		}
+	} else if (ap_num) {
+		target_iface = ap_ifs[0];
+	}
+
+	RTW_INFO("[IFS_ASSOC_STATUS] - STA :%d", sta_num);
+	RTW_INFO("[IFS_ASSOC_STATUS] - TDLS :%d", tdls_num);
+	RTW_INFO("[IFS_ASSOC_STATUS] - AP:%d", ap_num);
+	RTW_INFO("[IFS_ASSOC_STATUS] - MESH :%d", mesh_num);
+	RTW_INFO("[IFS_ASSOC_STATUS] - ADHOC :%d", adhoc_num);
+	RTW_INFO("[IFS_ASSOC_STATUS] - P2P-GC :%d", p2p_gc_num);
+	RTW_INFO("[IFS_ASSOC_STATUS] - P2P-GO :%d", p2p_go_num);
+
+	if (target_iface)
+		RTW_INFO("%s => target_iface ("ADPT_FMT")\n",
+			__func__, ADPT_ARG(target_iface));
+	else
+		RTW_INFO("%s => target_iface NULL\n", __func__);
+
+	return target_iface;
+}
+
+void rtw_search_default_port(_adapter *adapter)
+{
+	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
+	_adapter *adp_iface = NULL;
+#ifdef CONFIG_WOWLAN
+	struct pwrctrl_priv *pwrpriv = dvobj_to_pwrctl(dvobj);
+
+	if (pwrpriv->wowlan_mode == _TRUE) {
+		adp_iface = adapter;
+		goto exit;
+	}
+#endif
+	adp_iface = _rtw_search_dp_iface(adapter);
+
+exit :
+	if ((adp_iface != NULL) && (MLME_IS_STA(adp_iface)))
+		rtw_set_default_port_id(adp_iface);
+	else
+		rtw_hal_set_default_port_id_cmd(adapter, 0);
+
+	if (1) {
+		_adapter *tmp_adp;
+
+		tmp_adp = (adp_iface) ? adp_iface : adapter;
+
+		RTW_INFO("%s ("ADPT_FMT")=> hw_port :%d, default_port(%d)\n",
+			__func__, ADPT_ARG(adapter), get_hw_port(tmp_adp), get_dft_portid(tmp_adp));
+	}
+}
+#endif
+#endif /*CONFIG_FW_MULTI_PORT_SUPPORT*/
+
+#ifdef CONFIG_P2P_PS
+#ifdef RTW_HALMAC
+void rtw_set_p2p_ps_offload_cmd(_adapter *adapter, u8 p2p_ps_state)
+{
+	PHAL_DATA_TYPE hal = GET_HAL_DATA(adapter);
+	struct wifidirect_info *pwdinfo = &adapter->wdinfo;
+	struct mlme_ext_priv	*pmlmeext = &adapter->mlmeextpriv;
+	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
+	WLAN_BSSID_EX		*cur_network = &(pmlmeinfo->network);
+	struct sta_priv		*pstapriv = &adapter->stapriv;
+	struct sta_info		*psta;
+	HAL_P2P_PS_PARA p2p_ps_para;
+	int status = -1;
+	u8 i;
+	u8 hw_port = rtw_hal_get_port(adapter);
+
+	_rtw_memset(&p2p_ps_para, 0, sizeof(HAL_P2P_PS_PARA));
+	_rtw_memcpy((&p2p_ps_para) , &hal->p2p_ps_offload , sizeof(hal->p2p_ps_offload));
+
+	(&p2p_ps_para)->p2p_port_id = hw_port;
+	(&p2p_ps_para)->p2p_group = 0;
+	psta = rtw_get_stainfo(pstapriv, cur_network->MacAddress);
+	if (psta) {
+		(&p2p_ps_para)->p2p_macid = psta->cmn.mac_id;
+	} else {
+		if (p2p_ps_state != P2P_PS_DISABLE) {
+			RTW_ERR("%s , psta was NULL\n", __func__);
+			return;
+		}
+	}
+
+
+	switch (p2p_ps_state) {
+	case P2P_PS_DISABLE:
+		RTW_INFO("P2P_PS_DISABLE\n");
+		_rtw_memset(&p2p_ps_para , 0, sizeof(HAL_P2P_PS_PARA));
+		break;
+
+	case P2P_PS_ENABLE:
+		RTW_INFO("P2P_PS_ENABLE\n");
+		/* update CTWindow value. */
+		if (pwdinfo->ctwindow > 0) {
+			(&p2p_ps_para)->ctwindow_en = 1;
+			(&p2p_ps_para)->ctwindow_length = pwdinfo->ctwindow;
+			/*RTW_INFO("%s , ctwindow_length = %d\n" , __func__ , (&p2p_ps_para)->ctwindow_length);*/
+		}
+
+
+		if ((pwdinfo->opp_ps == 1) || (pwdinfo->noa_num > 0)) {
+			(&p2p_ps_para)->offload_en = 1;
+			if (pwdinfo->role == P2P_ROLE_GO) {
+				(&p2p_ps_para)->role = 1;
+				(&p2p_ps_para)->all_sta_sleep = 0;
+			} else
+				(&p2p_ps_para)->role = 0;
+
+			(&p2p_ps_para)->discovery = 0;
+		}
+		/* hw only support 2 set of NoA */
+		for (i = 0; i < pwdinfo->noa_num; i++) {
+			/* To control the register setting for which NOA */
+			(&p2p_ps_para)->noa_sel = i;
+			(&p2p_ps_para)->noa_en = 1;
+			/* config P2P NoA Descriptor Register */
+			/* config NOA duration */
+			(&p2p_ps_para)->noa_duration_para = pwdinfo->noa_duration[i];
+			/* config NOA interval */
+			(&p2p_ps_para)->noa_interval_para = pwdinfo->noa_interval[i];
+			/* config NOA start time */
+			(&p2p_ps_para)->noa_start_time_para = pwdinfo->noa_start_time[i];
+			/* config NOA count */
+			(&p2p_ps_para)->noa_count_para = pwdinfo->noa_count[i];
+			/*RTW_INFO("%s , noa_duration_para = %d , noa_interval_para = %d , noa_start_time_para = %d , noa_count_para = %d\n" , __func__ ,
+				(&p2p_ps_para)->noa_duration_para , (&p2p_ps_para)->noa_interval_para ,
+				(&p2p_ps_para)->noa_start_time_para , (&p2p_ps_para)->noa_count_para);*/
+			status = rtw_halmac_p2pps(adapter_to_dvobj(adapter) , (&p2p_ps_para));
+			if (status == -1)
+				RTW_ERR("%s , rtw_halmac_p2pps fail\n", __func__);
+		}
+
+		break;
+
+	case P2P_PS_SCAN:
+		/*This feature FW not ready 20161116 YiWei*/
+		return;
+		RTW_INFO("P2P_PS_SCAN\n");
+		(&p2p_ps_para)->discovery = 1;
+		/*
+		(&p2p_ps_para)->ctwindow_length = pwdinfo->ctwindow;
+		(&p2p_ps_para)->noa_duration_para = pwdinfo->noa_duration[0];
+		(&p2p_ps_para)->noa_interval_para = pwdinfo->noa_interval[0];
+		(&p2p_ps_para)->noa_start_time_para = pwdinfo->noa_start_time[0];
+		(&p2p_ps_para)->noa_count_para = pwdinfo->noa_count[0];
+		*/
+		break;
+
+	case P2P_PS_SCAN_DONE:
+		/*This feature FW not ready 20161116 YiWei*/
+		return;
+		RTW_INFO("P2P_PS_SCAN_DONE\n");
+		(&p2p_ps_para)->discovery = 0;
+		/*
+		pwdinfo->p2p_ps_state = P2P_PS_ENABLE;
+		(&p2p_ps_para)->ctwindow_length = pwdinfo->ctwindow;
+		(&p2p_ps_para)->noa_duration_para = pwdinfo->noa_duration[0];
+		(&p2p_ps_para)->noa_interval_para = pwdinfo->noa_interval[0];
+		(&p2p_ps_para)->noa_start_time_para = pwdinfo->noa_start_time[0];
+		(&p2p_ps_para)->noa_count_para = pwdinfo->noa_count[0];
+		*/
+		break;
+
+	default:
+		break;
+	}
+
+	if (p2p_ps_state != P2P_PS_ENABLE || (&p2p_ps_para)->noa_en == 0) {
+		status = rtw_halmac_p2pps(adapter_to_dvobj(adapter) , (&p2p_ps_para));
+		if (status == -1)
+			RTW_ERR("%s , rtw_halmac_p2pps fail\n", __func__);
+	}
+	_rtw_memcpy(&hal->p2p_ps_offload , (&p2p_ps_para) , sizeof(hal->p2p_ps_offload));
+
+}
+#endif /* RTW_HALMAC */
+#endif /* CONFIG_P2P */
+
+/*
+* rtw_hal_set_FwMediaStatusRpt_cmd -
+*
+* @adapter:
+* @opmode:  0:disconnect, 1:connect
+* @miracast: 0:it's not in miracast scenario. 1:it's in miracast scenario
+* @miracast_sink: 0:source. 1:sink
+* @role: The role of this macid. 0:rsvd. 1:STA. 2:AP. 3:GC. 4:GO. 5:TDLS
+* @macid:
+* @macid_ind:  0:update Media Status to macid.  1:update Media Status from macid to macid_end
+* @macid_end:
+*/
+s32 rtw_hal_set_FwMediaStatusRpt_cmd(_adapter *adapter, bool opmode, bool miracast, bool miracast_sink, u8 role, u8 macid, bool macid_ind, u8 macid_end)
+{
+	struct macid_ctl_t *macid_ctl = &adapter->dvobj->macid_ctl;
+	u8 parm[H2C_MEDIA_STATUS_RPT_LEN] = {0};
+	int i;
+	s32 ret;
+#ifdef CONFIG_FW_MULTI_PORT_SUPPORT
+	u8 hw_port = rtw_hal_get_port(adapter);
+#endif
+
+	SET_H2CCMD_MSRRPT_PARM_OPMODE(parm, opmode);
+	SET_H2CCMD_MSRRPT_PARM_MACID_IND(parm, macid_ind);
+	SET_H2CCMD_MSRRPT_PARM_MIRACAST(parm, miracast);
+	SET_H2CCMD_MSRRPT_PARM_MIRACAST_SINK(parm, miracast_sink);
+	SET_H2CCMD_MSRRPT_PARM_ROLE(parm, role);
+	SET_H2CCMD_MSRRPT_PARM_MACID(parm, macid);
+	SET_H2CCMD_MSRRPT_PARM_MACID_END(parm, macid_end);
+#ifdef CONFIG_FW_MULTI_PORT_SUPPORT
+	SET_H2CCMD_MSRRPT_PARM_PORT_NUM(parm, hw_port);
+#endif
+	RTW_DBG_DUMP("MediaStatusRpt parm:", parm, H2C_MEDIA_STATUS_RPT_LEN);
+
+	ret = rtw_hal_fill_h2c_cmd(adapter, H2C_MEDIA_STATUS_RPT, H2C_MEDIA_STATUS_RPT_LEN, parm);
+	if (ret != _SUCCESS)
+		goto exit;
+
+#if defined(CONFIG_RTL8188E)
+	if (rtw_get_chip_type(adapter) == RTL8188E) {
+		HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
+
+		/* 8188E FW doesn't set macid no link, driver does it by self */
+		if (opmode)
+			rtw_hal_set_hwreg(adapter, HW_VAR_MACID_LINK, &macid);
+		else
+			rtw_hal_set_hwreg(adapter, HW_VAR_MACID_NOLINK, &macid);
+
+		/* for 8188E RA */
+#if (RATE_ADAPTIVE_SUPPORT == 1)
+		if (hal_data->fw_ractrl == _FALSE) {
+			u8 max_macid;
+
+			max_macid = rtw_search_max_mac_id(adapter);
+			rtw_hal_set_hwreg(adapter, HW_VAR_TX_RPT_MAX_MACID, &max_macid);
+		}
+#endif
+	}
+#endif
+
+#if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A)
+	/* TODO: this should move to IOT issue area */
+	if (rtw_get_chip_type(adapter) == RTL8812
+		|| rtw_get_chip_type(adapter) == RTL8821
+	) {
+		if (MLME_IS_STA(adapter))
+			Hal_PatchwithJaguar_8812(adapter, opmode);
+	}
+#endif
+
+	SET_H2CCMD_MSRRPT_PARM_MACID_IND(parm, 0);
+	if (macid_ind == 0)
+		macid_end = macid;
+
+	for (i = macid; macid <= macid_end; macid++) {
+		rtw_macid_ctl_set_h2c_msr(macid_ctl, macid, parm[0]);
+		if (!opmode) {
+			rtw_macid_ctl_set_bw(macid_ctl, macid, CHANNEL_WIDTH_20);
+			rtw_macid_ctl_set_vht_en(macid_ctl, macid, 0);
+			rtw_macid_ctl_set_rate_bmp0(macid_ctl, macid, 0);
+			rtw_macid_ctl_set_rate_bmp1(macid_ctl, macid, 0);
+		}
+	}
+	if (!opmode)
+		rtw_update_tx_rate_bmp(adapter_to_dvobj(adapter));
+
+exit:
+	return ret;
+}
+
+inline s32 rtw_hal_set_FwMediaStatusRpt_single_cmd(_adapter *adapter, bool opmode, bool miracast, bool miracast_sink, u8 role, u8 macid)
+{
+	return rtw_hal_set_FwMediaStatusRpt_cmd(adapter, opmode, miracast, miracast_sink, role, macid, 0, 0);
+}
+
+inline s32 rtw_hal_set_FwMediaStatusRpt_range_cmd(_adapter *adapter, bool opmode, bool miracast, bool miracast_sink, u8 role, u8 macid, u8 macid_end)
+{
+	return rtw_hal_set_FwMediaStatusRpt_cmd(adapter, opmode, miracast, miracast_sink, role, macid, 1, macid_end);
+}
+
+void rtw_hal_set_FwRsvdPage_cmd(PADAPTER padapter, PRSVDPAGE_LOC rsvdpageloc)
+{
+	struct	hal_ops *pHalFunc = &padapter->hal_func;
+	u8	u1H2CRsvdPageParm[H2C_RSVDPAGE_LOC_LEN] = {0};
+	u8	ret = 0;
+
+	RTW_INFO("RsvdPageLoc: ProbeRsp=%d PsPoll=%d Null=%d QoSNull=%d BTNull=%d\n",
+		 rsvdpageloc->LocProbeRsp, rsvdpageloc->LocPsPoll,
+		 rsvdpageloc->LocNullData, rsvdpageloc->LocQosNull,
+		 rsvdpageloc->LocBTQosNull);
+
+	SET_H2CCMD_RSVDPAGE_LOC_PROBE_RSP(u1H2CRsvdPageParm, rsvdpageloc->LocProbeRsp);
+	SET_H2CCMD_RSVDPAGE_LOC_PSPOLL(u1H2CRsvdPageParm, rsvdpageloc->LocPsPoll);
+	SET_H2CCMD_RSVDPAGE_LOC_NULL_DATA(u1H2CRsvdPageParm, rsvdpageloc->LocNullData);
+	SET_H2CCMD_RSVDPAGE_LOC_QOS_NULL_DATA(u1H2CRsvdPageParm, rsvdpageloc->LocQosNull);
+	SET_H2CCMD_RSVDPAGE_LOC_BT_QOS_NULL_DATA(u1H2CRsvdPageParm, rsvdpageloc->LocBTQosNull);
+
+	ret = rtw_hal_fill_h2c_cmd(padapter,
+				   H2C_RSVD_PAGE,
+				   H2C_RSVDPAGE_LOC_LEN,
+				   u1H2CRsvdPageParm);
+
+}
+
+#ifdef CONFIG_GPIO_WAKEUP
+void rtw_hal_switch_gpio_wl_ctrl(_adapter *padapter, u8 index, u8 enable)
+{
+	PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter);
+
+	if (IS_8723D_SERIES(pHalData->version_id) || IS_8822B_SERIES(pHalData->version_id) || IS_8821C_SERIES(pHalData->version_id))
+		rtw_hal_set_hwreg(padapter, HW_SET_GPIO_WL_CTRL, (u8 *)(&enable));
+	/*
+	* Switch GPIO_13, GPIO_14 to wlan control, or pull GPIO_13,14 MUST fail.
+	* It happended at 8723B/8192E/8821A. New IC will check multi function GPIO,
+	* and implement HAL function.
+	* TODO: GPIO_8 multi function?
+	*/
+
+	if ((index == 13 || index == 14)
+		#if defined(CONFIG_RTL8821A) && defined(CONFIG_SDIO_HCI)
+		/* 8821A's LED2 circuit(used by HW_LED strategy) needs enable WL GPIO control of GPIO[14:13], can't disable */
+		&& (!IS_HW_LED_STRATEGY(rtw_led_get_strategy(padapter)) || enable)
+		#endif
+	)
+		rtw_hal_set_hwreg(padapter, HW_SET_GPIO_WL_CTRL, (u8 *)(&enable));
+}
+
+void rtw_hal_set_output_gpio(_adapter *padapter, u8 index, u8 outputval)
+{
+	if (index <= 7) {
+		/* config GPIO mode */
+		rtw_write8(padapter, REG_GPIO_PIN_CTRL + 3,
+			rtw_read8(padapter, REG_GPIO_PIN_CTRL + 3) & ~BIT(index));
+
+		/* config GPIO Sel */
+		/* 0: input */
+		/* 1: output */
+		rtw_write8(padapter, REG_GPIO_PIN_CTRL + 2,
+			rtw_read8(padapter, REG_GPIO_PIN_CTRL + 2) | BIT(index));
+
+		/* set output value */
+		if (outputval) {
+			rtw_write8(padapter, REG_GPIO_PIN_CTRL + 1,
+				rtw_read8(padapter, REG_GPIO_PIN_CTRL + 1) | BIT(index));
+		} else {
+			rtw_write8(padapter, REG_GPIO_PIN_CTRL + 1,
+				rtw_read8(padapter, REG_GPIO_PIN_CTRL + 1) & ~BIT(index));
+		}
+	} else if (index <= 15) {
+		/* 88C Series: */
+		/* index: 11~8 transform to 3~0 */
+		/* 8723 Series: */
+		/* index: 12~8 transform to 4~0 */
+
+		index -= 8;
+
+		/* config GPIO mode */
+		rtw_write8(padapter, REG_GPIO_PIN_CTRL_2 + 3,
+			rtw_read8(padapter, REG_GPIO_PIN_CTRL_2 + 3) & ~BIT(index));
+
+		/* config GPIO Sel */
+		/* 0: input */
+		/* 1: output */
+		rtw_write8(padapter, REG_GPIO_PIN_CTRL_2 + 2,
+			rtw_read8(padapter, REG_GPIO_PIN_CTRL_2 + 2) | BIT(index));
+
+		/* set output value */
+		if (outputval) {
+			rtw_write8(padapter, REG_GPIO_PIN_CTRL_2 + 1,
+				rtw_read8(padapter, REG_GPIO_PIN_CTRL_2 + 1) | BIT(index));
+		} else {
+			rtw_write8(padapter, REG_GPIO_PIN_CTRL_2 + 1,
+				rtw_read8(padapter, REG_GPIO_PIN_CTRL_2 + 1) & ~BIT(index));
+		}
+	} else {
+		RTW_INFO("%s: invalid GPIO%d=%d\n",
+			 __FUNCTION__, index, outputval);
+	}
+}
+void rtw_hal_set_input_gpio(_adapter *padapter, u8 index)
+{
+	if (index <= 7) {
+		/* config GPIO mode */
+		rtw_write8(padapter, REG_GPIO_PIN_CTRL + 3,
+			rtw_read8(padapter, REG_GPIO_PIN_CTRL + 3) & ~BIT(index));
+
+		/* config GPIO Sel */
+		/* 0: input */
+		/* 1: output */
+		rtw_write8(padapter, REG_GPIO_PIN_CTRL + 2,
+			rtw_read8(padapter, REG_GPIO_PIN_CTRL + 2) & ~BIT(index));
+
+	} else if (index <= 15) {
+		/* 88C Series: */
+		/* index: 11~8 transform to 3~0 */
+		/* 8723 Series: */
+		/* index: 12~8 transform to 4~0 */
+
+		index -= 8;
+
+		/* config GPIO mode */
+		rtw_write8(padapter, REG_GPIO_PIN_CTRL_2 + 3,
+			rtw_read8(padapter, REG_GPIO_PIN_CTRL_2 + 3) & ~BIT(index));
+
+		/* config GPIO Sel */
+		/* 0: input */
+		/* 1: output */
+		rtw_write8(padapter, REG_GPIO_PIN_CTRL_2 + 2,
+			rtw_read8(padapter, REG_GPIO_PIN_CTRL_2 + 2) & ~BIT(index));
+	} else
+		RTW_INFO("%s: invalid GPIO%d\n", __func__, index);
+
+}
+
+#endif
+
+void rtw_hal_set_FwAoacRsvdPage_cmd(PADAPTER padapter, PRSVDPAGE_LOC rsvdpageloc)
+{
+	struct	hal_ops *pHalFunc = &padapter->hal_func;
+	struct	pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter);
+	struct	mlme_priv *pmlmepriv = &padapter->mlmepriv;
+	u8	res = 0, count = 0, ret = 0;
+#ifdef CONFIG_WOWLAN
+	u8 u1H2CAoacRsvdPageParm[H2C_AOAC_RSVDPAGE_LOC_LEN] = {0};
+
+	RTW_INFO("%s: RWC: %d ArpRsp: %d NbrAdv: %d LocNDPInfo: %d\n",
+		 __func__, rsvdpageloc->LocRemoteCtrlInfo,
+		 rsvdpageloc->LocArpRsp, rsvdpageloc->LocNbrAdv,
+		 rsvdpageloc->LocNDPInfo);
+	RTW_INFO("%s:GtkRsp: %d GtkInfo: %d ProbeReq: %d NetworkList: %d\n",
+		 __func__, rsvdpageloc->LocGTKRsp, rsvdpageloc->LocGTKInfo,
+		 rsvdpageloc->LocProbeReq, rsvdpageloc->LocNetList);
+
+	if (check_fwstate(pmlmepriv, _FW_LINKED)) {
+		SET_H2CCMD_AOAC_RSVDPAGE_LOC_REMOTE_WAKE_CTRL_INFO(u1H2CAoacRsvdPageParm, rsvdpageloc->LocRemoteCtrlInfo);
+		SET_H2CCMD_AOAC_RSVDPAGE_LOC_ARP_RSP(u1H2CAoacRsvdPageParm, rsvdpageloc->LocArpRsp);
+		SET_H2CCMD_AOAC_RSVDPAGE_LOC_NEIGHBOR_ADV(u1H2CAoacRsvdPageParm,
+							rsvdpageloc->LocNbrAdv);
+		SET_H2CCMD_AOAC_RSVDPAGE_LOC_NDP_INFO(u1H2CAoacRsvdPageParm,
+						      rsvdpageloc->LocNDPInfo);
+#ifdef CONFIG_GTK_OL
+		SET_H2CCMD_AOAC_RSVDPAGE_LOC_GTK_RSP(u1H2CAoacRsvdPageParm, rsvdpageloc->LocGTKRsp);
+		SET_H2CCMD_AOAC_RSVDPAGE_LOC_GTK_INFO(u1H2CAoacRsvdPageParm, rsvdpageloc->LocGTKInfo);
+		SET_H2CCMD_AOAC_RSVDPAGE_LOC_GTK_EXT_MEM(u1H2CAoacRsvdPageParm, rsvdpageloc->LocGTKEXTMEM);
+#endif /* CONFIG_GTK_OL */
+		ret = rtw_hal_fill_h2c_cmd(padapter,
+					   H2C_AOAC_RSVD_PAGE,
+					   H2C_AOAC_RSVDPAGE_LOC_LEN,
+					   u1H2CAoacRsvdPageParm);
+
+		RTW_INFO("AOAC Report=%d\n", rsvdpageloc->LocAOACReport);
+		_rtw_memset(&u1H2CAoacRsvdPageParm, 0, sizeof(u1H2CAoacRsvdPageParm));
+		SET_H2CCMD_AOAC_RSVDPAGE_LOC_AOAC_REPORT(u1H2CAoacRsvdPageParm,
+					 rsvdpageloc->LocAOACReport);
+		ret = rtw_hal_fill_h2c_cmd(padapter,
+				   H2C_AOAC_RSVDPAGE3,
+				   H2C_AOAC_RSVDPAGE_LOC_LEN,
+				   u1H2CAoacRsvdPageParm);
+		pwrpriv->wowlan_aoac_rpt_loc = rsvdpageloc->LocAOACReport;
+	}
+#ifdef CONFIG_PNO_SUPPORT
+	else {
+
+		if (!pwrpriv->wowlan_in_resume) {
+			RTW_INFO("NLO_INFO=%d\n", rsvdpageloc->LocPNOInfo);
+			_rtw_memset(&u1H2CAoacRsvdPageParm, 0,
+				    sizeof(u1H2CAoacRsvdPageParm));
+			SET_H2CCMD_AOAC_RSVDPAGE_LOC_NLO_INFO(u1H2CAoacRsvdPageParm,
+						      rsvdpageloc->LocPNOInfo);
+			ret = rtw_hal_fill_h2c_cmd(padapter,
+						   H2C_AOAC_RSVDPAGE3,
+						   H2C_AOAC_RSVDPAGE_LOC_LEN,
+						   u1H2CAoacRsvdPageParm);
+		}
+	}
+#endif /* CONFIG_PNO_SUPPORT */
+#endif /* CONFIG_WOWLAN */
+}
+
+#ifdef DBG_FW_DEBUG_MSG_PKT
+void rtw_hal_set_fw_dbg_msg_pkt_rsvd_page_cmd(PADAPTER padapter, PRSVDPAGE_LOC rsvdpageloc)
+{
+	struct	hal_ops *pHalFunc = &padapter->hal_func;
+	u8	u1H2C_fw_dbg_msg_pkt_parm[H2C_FW_DBG_MSG_PKT_LEN] = {0};
+	u8	ret = 0;
+
+
+	RTW_INFO("RsvdPageLoc: loc_fw_dbg_msg_pkt =%d\n", rsvdpageloc->loc_fw_dbg_msg_pkt);
+
+	SET_H2CCMD_FW_DBG_MSG_PKT_EN(u1H2C_fw_dbg_msg_pkt_parm, 1);
+	SET_H2CCMD_RSVDPAGE_LOC_FW_DBG_MSG_PKT(u1H2C_fw_dbg_msg_pkt_parm, rsvdpageloc->loc_fw_dbg_msg_pkt);
+	ret = rtw_hal_fill_h2c_cmd(padapter,
+				   H2C_FW_DBG_MSG_PKT,
+				   H2C_FW_DBG_MSG_PKT_LEN,
+				   u1H2C_fw_dbg_msg_pkt_parm);
+
+}
+#endif /*DBG_FW_DEBUG_MSG_PKT*/
+
+/*#define DBG_GET_RSVD_PAGE*/
+int rtw_hal_get_rsvd_page(_adapter *adapter, u32 page_offset,
+	u32 page_num, u8 *buffer, u32 buffer_size)
+{
+	u32 addr = 0, size = 0, count = 0;
+	u32 page_size = 0, data_low = 0, data_high = 0;
+	u16 txbndy = 0, offset = 0;
+	u8 i = 0;
+	bool rst = _FALSE;
+
+#ifdef DBG_LA_MODE
+	struct registry_priv *registry_par = &adapter->registrypriv;
+
+	if(registry_par->la_mode_en == 1) {
+		RTW_INFO("%s LA debug mode can't dump rsvd pg \n", __func__);
+		return rst;
+	}
+#endif
+	rtw_hal_get_def_var(adapter, HAL_DEF_TX_PAGE_SIZE, &page_size);
+
+	addr = page_offset * page_size;
+	size = page_num * page_size;
+
+	if (buffer_size < size) {
+		RTW_ERR("%s buffer_size(%d) < get page total size(%d)\n",
+			__func__, buffer_size, size);
+		return rst;
+	}
+#ifdef RTW_HALMAC
+	if (rtw_halmac_dump_fifo(adapter_to_dvobj(adapter), 2, addr, size, buffer) < 0)
+		rst = _FALSE;
+	else
+		rst = _TRUE;
+#else
+	txbndy = rtw_read8(adapter, REG_TDECTRL + 1);
+
+	offset = (txbndy + page_offset) * page_size / 8;
+	count = (buffer_size / 8) + 1;
+
+	rtw_write8(adapter, REG_PKT_BUFF_ACCESS_CTRL, 0x69);
+
+	for (i = 0 ; i < count ; i++) {
+		rtw_write32(adapter, REG_PKTBUF_DBG_CTRL, offset + i);
+		data_low = rtw_read32(adapter, REG_PKTBUF_DBG_DATA_L);
+		data_high = rtw_read32(adapter, REG_PKTBUF_DBG_DATA_H);
+		_rtw_memcpy(buffer + (i * 8),
+			&data_low, sizeof(data_low));
+		_rtw_memcpy(buffer + ((i * 8) + 4),
+			&data_high, sizeof(data_high));
+	}
+	rtw_write8(adapter, REG_PKT_BUFF_ACCESS_CTRL, 0x0);
+	rst = _TRUE;
+#endif /*RTW_HALMAC*/
+
+#ifdef DBG_GET_RSVD_PAGE
+	RTW_INFO("%s [page_offset:%d , page_num:%d][start_addr:0x%04x , size:%d]\n",
+		 __func__, page_offset, page_num, addr, size);
+	RTW_INFO_DUMP("\n", buffer, size);
+	RTW_INFO(" ==================================================\n");
+#endif
+	return rst;
+}
+
+void rtw_dump_rsvd_page(void *sel, _adapter *adapter, u8 page_offset, u8 page_num)
+{
+	u32 page_size = 0;
+	u8 *buffer = NULL;
+	u32 buf_size = 0;
+
+	if (page_num == 0)
+		return;
+
+	RTW_PRINT_SEL(sel, "======= RSVD PAGE DUMP =======\n");
+	RTW_PRINT_SEL(sel, "page_offset:%d, page_num:%d\n", page_offset, page_num);
+
+	rtw_hal_get_def_var(adapter, HAL_DEF_TX_PAGE_SIZE, &page_size);
+	if (page_size) {
+		buf_size = page_size * page_num;
+		buffer = rtw_zvmalloc(buf_size);
+
+		if (buffer) {
+			rtw_hal_get_rsvd_page(adapter, page_offset, page_num, buffer, buf_size);
+			RTW_DUMP_SEL(sel, buffer, buf_size);
+			rtw_vmfree(buffer, buf_size);
+		} else
+			RTW_PRINT_SEL(sel, "ERROR - rsvd_buf mem allocate failed\n");
+	} else
+			RTW_PRINT_SEL(sel, "ERROR - Tx page size is zero ??\n");
+
+	RTW_PRINT_SEL(sel, "==========================\n");
+}
+
+#ifdef CONFIG_SUPPORT_FIFO_DUMP
+void rtw_dump_fifo(void *sel, _adapter *adapter, u8 fifo_sel, u32 fifo_addr, u32 fifo_size)
+{
+	u8 *buffer = NULL;
+	u32 buff_size = 0;
+	static const char * const fifo_sel_str[] = {
+		"TX", "RX", "RSVD_PAGE", "REPORT", "LLT", "RXBUF_FW"
+	};
+
+	if (fifo_sel > 5) {
+		RTW_ERR("fifo_sel:%d invalid\n", fifo_sel);
+		return;
+	}
+
+	RTW_PRINT_SEL(sel, "========= FIFO DUMP =========\n");
+	RTW_PRINT_SEL(sel, "%s FIFO DUMP [start_addr:0x%04x , size:%d]\n", fifo_sel_str[fifo_sel], fifo_addr, fifo_size);
+
+	if (fifo_size) {
+		buff_size = RND4(fifo_size);
+		buffer = rtw_zvmalloc(buff_size);
+		if (buffer == NULL)
+			buff_size = 0;
+	}
+
+	rtw_halmac_dump_fifo(adapter_to_dvobj(adapter), fifo_sel, fifo_addr, buff_size, buffer);
+
+	if (buffer) {
+		RTW_DUMP_SEL(sel, buffer, fifo_size);
+		rtw_vmfree(buffer, buff_size);
+	}
+
+	RTW_PRINT_SEL(sel, "==========================\n");
+}
+#endif
+
+#if defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN)
+static void rtw_hal_force_enable_rxdma(_adapter *adapter)
+{
+	RTW_INFO("%s: Set 0x690=0x00\n", __func__);
+	rtw_write8(adapter, REG_WOW_CTRL,
+		   (rtw_read8(adapter, REG_WOW_CTRL) & 0xf0));
+	RTW_PRINT("%s: Release RXDMA\n", __func__);
+	rtw_write32(adapter, REG_RXPKT_NUM,
+		    (rtw_read32(adapter, REG_RXPKT_NUM) & (~RW_RELEASE_EN)));
+}
+#if defined(CONFIG_RTL8188E)
+static void rtw_hal_disable_tx_report(_adapter *adapter)
+{
+	rtw_write8(adapter, REG_TX_RPT_CTRL,
+		   ((rtw_read8(adapter, REG_TX_RPT_CTRL) & ~BIT(1))) & ~BIT(5));
+	RTW_INFO("disable TXRPT:0x%02x\n", rtw_read8(adapter, REG_TX_RPT_CTRL));
+}
+
+static void rtw_hal_enable_tx_report(_adapter *adapter)
+{
+	rtw_write8(adapter, REG_TX_RPT_CTRL,
+		   ((rtw_read8(adapter, REG_TX_RPT_CTRL) | BIT(1))) | BIT(5));
+	RTW_INFO("enable TX_RPT:0x%02x\n", rtw_read8(adapter, REG_TX_RPT_CTRL));
+}
+#endif
+static void rtw_hal_release_rx_dma(_adapter *adapter)
+{
+	u32 val32 = 0;
+
+	val32 = rtw_read32(adapter, REG_RXPKT_NUM);
+
+	rtw_write32(adapter, REG_RXPKT_NUM, (val32 & (~RW_RELEASE_EN)));
+
+	RTW_INFO("%s, [0x%04x]: 0x%08x\n",
+		 __func__, REG_RXPKT_NUM, (val32 & (~RW_RELEASE_EN)));
+}
+
+static u8 rtw_hal_pause_rx_dma(_adapter *adapter)
+{
+	PHAL_DATA_TYPE hal = GET_HAL_DATA(adapter);
+	u8 ret = 0;
+	s8 trycnt = 100;
+	u32 tmp = 0;
+	int res = 0;
+	/* RX DMA stop */
+	RTW_PRINT("Pause DMA\n");
+	rtw_write32(adapter, REG_RXPKT_NUM,
+		    (rtw_read32(adapter, REG_RXPKT_NUM) | RW_RELEASE_EN));
+	do {
+		if ((rtw_read32(adapter, REG_RXPKT_NUM) & RXDMA_IDLE)) {
+#ifdef CONFIG_USB_HCI
+			/* stop interface before leave */
+			if (_TRUE == hal->usb_intf_start) {
+				rtw_intf_stop(adapter);
+				RTW_ENABLE_FUNC(adapter, DF_RX_BIT);
+				RTW_ENABLE_FUNC(adapter, DF_TX_BIT);
+			}
+#endif /* CONFIG_USB_HCI */
+
+			RTW_PRINT("RX_DMA_IDLE is true\n");
+			ret = _SUCCESS;
+			break;
+		}
+#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
+		else {
+			res = RecvOnePkt(adapter);
+			RTW_PRINT("RecvOnePkt Result: %d\n", res);
+		}
+#endif /* CONFIG_SDIO_HCI || CONFIG_GSPI_HCI */
+
+#ifdef CONFIG_USB_HCI
+		else {
+			/* to avoid interface start repeatedly  */
+			if (_FALSE == hal->usb_intf_start)
+				rtw_intf_start(adapter);
+		}
+#endif /* CONFIG_USB_HCI */
+	} while (trycnt--);
+
+	if (trycnt < 0) {
+		tmp = rtw_read16(adapter, REG_RXPKT_NUM + 2);
+
+		RTW_PRINT("Stop RX DMA failed......\n");
+		RTW_PRINT("%s, RXPKT_NUM: 0x%02x\n",
+			  __func__, ((tmp & 0xFF00) >> 8));
+
+		if (tmp & BIT(3))
+			RTW_PRINT("%s, RX DMA has req\n",
+				  __func__);
+		else
+			RTW_PRINT("%s, RX DMA no req\n",
+				  __func__);
+		ret = _FAIL;
+	}
+
+	return ret;
+}
+
+#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
+#ifndef RTW_HALMAC
+static u8 rtw_hal_enable_cpwm2(_adapter *adapter)
+{
+	u8 ret = 0;
+	int res = 0;
+	u32 tmp = 0;
+#ifdef CONFIG_GPIO_WAKEUP
+	return _SUCCESS;
+#else
+	RTW_PRINT("%s\n", __func__);
+
+	res = sdio_local_read(adapter, SDIO_REG_HIMR, 4, (u8 *)&tmp);
+	if (!res)
+		RTW_INFO("read SDIO_REG_HIMR: 0x%08x\n", tmp);
+	else
+		RTW_INFO("sdio_local_read fail\n");
+
+	tmp = SDIO_HIMR_CPWM2_MSK;
+
+	res = sdio_local_write(adapter, SDIO_REG_HIMR, 4, (u8 *)&tmp);
+
+	if (!res) {
+		res = sdio_local_read(adapter, SDIO_REG_HIMR, 4, (u8 *)&tmp);
+		RTW_INFO("read again SDIO_REG_HIMR: 0x%08x\n", tmp);
+		ret = _SUCCESS;
+	} else {
+		RTW_INFO("sdio_local_write fail\n");
+		ret = _FAIL;
+	}
+	return ret;
+#endif /* CONFIG_CPIO_WAKEUP */
+}
+#endif
+#endif /* CONFIG_SDIO_HCI, CONFIG_GSPI_HCI */
+#endif /* CONFIG_WOWLAN || CONFIG_AP_WOWLAN */
+
+#ifdef CONFIG_WOWLAN
+/*
+ * rtw_hal_check_wow_ctrl
+ * chk_type: _TRUE means to check enable, if 0x690 & bit1 (for 8051), WOW enable successful.
+ *									If 0x1C7 == 0 (for 3081), WOW enable successful.
+ *		     _FALSE means to check disable, if 0x690 & bit1 (for 8051), WOW disable fail.
+ *									If 0x120 & bit16 || 0x284 & bit18 (for 3081), WOW disable fail.
+ */
+static u8 rtw_hal_check_wow_ctrl(_adapter *adapter, u8 chk_type)
+{
+	u32 fe1_imr = 0xFF, rxpkt_num = 0xFF;
+	u8 mstatus = 0;
+	u8 reason = 0xFF;
+	u8 trycnt = 25;
+	u8 res = _FALSE;
+
+	if (IS_HARDWARE_TYPE_JAGUAR2(adapter)) {
+		if (chk_type) {
+			reason = rtw_read8(adapter, REG_WOWLAN_WAKE_REASON);
+			RTW_INFO("%s reason:0x%02x\n", __func__, reason);
+
+			while (reason && trycnt > 1) {
+				reason = rtw_read8(adapter, REG_WOWLAN_WAKE_REASON);
+				RTW_PRINT("Loop index: %d :0x%02x\n",
+					  trycnt, reason);
+				trycnt--;
+				rtw_msleep_os(20);
+			}
+			if (!reason)
+				res = _TRUE;
+			else
+				res = _FALSE;
+		} else {
+			/* Wait FW to cleare 0x120 bit16, 0x284 bit18 to 0 */
+			fe1_imr = rtw_read32(adapter, REG_FE1IMR); /* RxDone IMR for 3081 */
+			rxpkt_num = rtw_read32(adapter, REG_RXPKT_NUM); /* Release RXDMA */
+			RTW_PRINT("%s REG_FE1IMR (reg120): 0x%x, REG_RXPKT_NUM(reg284): 0x%x\n", __func__, fe1_imr, rxpkt_num);
+
+			while (((fe1_imr & BIT_FS_RXDONE_INT_EN) || (rxpkt_num & BIT_RW_RELEASE_EN)) && trycnt > 1) {
+				rtw_msleep_os(20);
+				fe1_imr = rtw_read32(adapter, REG_FE1IMR);
+				rxpkt_num = rtw_read32(adapter, REG_RXPKT_NUM);
+				RTW_PRINT("Loop index: %d :0x%x, 0x%x\n",
+					  trycnt, fe1_imr, rxpkt_num);
+				trycnt--;
+			}
+
+			if ((fe1_imr & BIT_FS_RXDONE_INT_EN) || (rxpkt_num & BIT_RW_RELEASE_EN))
+				res = _FALSE;
+			else
+				res = _TRUE;
+		}
+	} else {
+		mstatus = rtw_read8(adapter, REG_WOW_CTRL);
+		RTW_INFO("%s mstatus:0x%02x\n", __func__, mstatus);
+
+
+		if (chk_type) {
+			while (!(mstatus & BIT1) && trycnt > 1) {
+				mstatus = rtw_read8(adapter, REG_WOW_CTRL);
+				RTW_PRINT("Loop index: %d :0x%02x\n",
+					  trycnt, mstatus);
+				trycnt--;
+				rtw_msleep_os(20);
+			}
+			if (mstatus & BIT1)
+				res = _TRUE;
+			else
+				res = _FALSE;
+		} else {
+			while (mstatus & BIT1 && trycnt > 1) {
+				mstatus = rtw_read8(adapter, REG_WOW_CTRL);
+				RTW_PRINT("Loop index: %d :0x%02x\n",
+					  trycnt, mstatus);
+				trycnt--;
+				rtw_msleep_os(20);
+			}
+
+			if (mstatus & BIT1)
+				res = _FALSE;
+			else
+				res = _TRUE;
+		}
+	}
+
+	RTW_PRINT("%s check_type: %d res: %d trycnt: %d\n",
+		  __func__, chk_type, res, (25 - trycnt));
+	return res;
+}
+
+#ifdef CONFIG_PNO_SUPPORT
+static u8 rtw_hal_check_pno_enabled(_adapter *adapter)
+{
+	struct pwrctrl_priv *ppwrpriv = adapter_to_pwrctl(adapter);
+	u8 res = 0, count = 0;
+	u8 ret = _FALSE;
+
+	if (ppwrpriv->wowlan_pno_enable && ppwrpriv->wowlan_in_resume == _FALSE) {
+		res = rtw_read8(adapter, REG_PNO_STATUS);
+		while (!(res & BIT(7)) && count < 25) {
+			RTW_INFO("[%d] cmd: 0x81 REG_PNO_STATUS: 0x%02x\n",
+				 count, res);
+			res = rtw_read8(adapter, REG_PNO_STATUS);
+			count++;
+			rtw_msleep_os(2);
+		}
+		if (res & BIT(7))
+			ret = _TRUE;
+		else
+			ret = _FALSE;
+		RTW_INFO("cmd: 0x81 REG_PNO_STATUS: ret(%d)\n", ret);
+	}
+	return ret;
+}
+#endif
+
+static void rtw_hal_backup_rate(_adapter *adapter)
+{
+	RTW_INFO("%s\n", __func__);
+	/* backup data rate to register 0x8b for wowlan FW */
+	rtw_write8(adapter, 0x8d, 1);
+	rtw_write8(adapter, 0x8c, 0);
+	rtw_write8(adapter, 0x8f, 0x40);
+	rtw_write8(adapter, 0x8b, rtw_read8(adapter, 0x2f0));
+}
+
+#ifdef CONFIG_GTK_OL
+static void rtw_hal_fw_sync_cam_id(_adapter *adapter)
+{
+	struct mlme_priv *pmlmepriv = &adapter->mlmepriv;
+	int cam_id, index = 0;
+	u8 *addr = NULL;
+
+	if (!MLME_IS_STA(adapter))
+		return;
+
+	addr = get_bssid(pmlmepriv);
+
+	if (addr == NULL) {
+		RTW_INFO("%s: get bssid MAC addr fail!!\n", __func__);
+		return;
+	}
+
+	rtw_clean_dk_section(adapter);
+
+	do {
+		cam_id = rtw_camid_search(adapter, addr, index, 1);
+
+		if (cam_id == -1)
+			RTW_INFO("%s: cam_id: %d, key_id:%d\n", __func__, cam_id, index);
+		else
+			rtw_sec_cam_swap(adapter, cam_id, index);
+
+		index++;
+	} while (index < 4);
+
+	rtw_write8(adapter, REG_SECCFG, 0xcc);
+}
+
+static void rtw_hal_update_gtk_offload_info(_adapter *adapter)
+{
+	struct pwrctrl_priv *pwrctl = adapter_to_pwrctl(adapter);
+	struct aoac_report *paoac_rpt = &pwrctl->wowlan_aoac_rpt;
+	struct mlme_priv *pmlmepriv = &adapter->mlmepriv;
+	struct security_priv *psecuritypriv = &adapter->securitypriv;
+	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
+	struct cam_ctl_t *cam_ctl = &dvobj->cam_ctl;
+	_irqL irqL;
+	u8 get_key[16];
+	u8 gtk_id = 0, offset = 0, i = 0, sz = 0, aoac_rpt_ver = 0, has_rekey = _FALSE;
+	u64 replay_count = 0, tmp_iv_hdr = 0, pkt_pn = 0;
+
+	if (!MLME_IS_STA(adapter))
+		return;
+
+	_rtw_memset(get_key, 0, sizeof(get_key));
+	_rtw_memcpy(&replay_count,
+		paoac_rpt->replay_counter_eapol_key, 8);
+
+	/*read gtk key index*/
+	gtk_id = paoac_rpt->key_index;
+	aoac_rpt_ver = paoac_rpt->version_info;
+
+	if (aoac_rpt_ver == 0) {
+		/* initial verison */
+		if (gtk_id == 5)
+			has_rekey = _FALSE;
+		else
+			has_rekey = _TRUE;
+	} else if (aoac_rpt_ver >= 1) {
+		/* Add krack patch */
+		if (gtk_id == 5)
+			RTW_WARN("%s FW check iv fail\n", __func__);
+
+		if (aoac_rpt_ver == 1)
+			RTW_WARN("%s aoac report version should be update to v2\n", __func__);
+
+		/* Fix key id mismatch */
+		if (aoac_rpt_ver == 2)
+			has_rekey = paoac_rpt->rekey_ok == 1 ? _TRUE : _FALSE;
+	}
+
+	if (has_rekey == _FALSE) {
+		RTW_INFO("%s no rekey event happened.\n", __func__);
+	} else if (has_rekey == _TRUE) {
+		RTW_INFO("%s update security key.\n", __func__);
+		/*read key from sec-cam,for DK ,keyindex is equal to cam-id*/
+		rtw_sec_read_cam_ent(adapter, gtk_id,
+				     NULL, NULL, get_key);
+		rtw_clean_hw_dk_cam(adapter);
+
+		if (_rtw_camid_is_gk(adapter, gtk_id)) {
+			_enter_critical_bh(&cam_ctl->lock, &irqL);
+			_rtw_memcpy(&dvobj->cam_cache[gtk_id].key,
+				    get_key, 16);
+			_exit_critical_bh(&cam_ctl->lock, &irqL);
+		} else {
+			struct setkey_parm parm_gtk;
+
+			parm_gtk.algorithm = paoac_rpt->security_type;
+			parm_gtk.keyid = gtk_id;
+			_rtw_memcpy(parm_gtk.key, get_key, 16);
+			setkey_hdl(adapter, (u8 *)&parm_gtk);
+		}
+
+		/*update key into related sw variable and sec-cam cache*/
+		psecuritypriv->dot118021XGrpKeyid = gtk_id;
+		_rtw_memcpy(&psecuritypriv->dot118021XGrpKey[gtk_id],
+				get_key, 16);
+		/* update SW TKIP TX/RX MIC value */
+		if (psecuritypriv->dot118021XGrpPrivacy == _TKIP_) {
+			offset = RTW_KEK_LEN + RTW_TKIP_MIC_LEN;
+			_rtw_memcpy(
+				&psecuritypriv->dot118021XGrptxmickey[gtk_id],
+				&(paoac_rpt->group_key[offset]),
+				RTW_TKIP_MIC_LEN);
+
+			offset = RTW_KEK_LEN;
+			_rtw_memcpy(
+				&psecuritypriv->dot118021XGrprxmickey[gtk_id],
+				&(paoac_rpt->group_key[offset]),
+				RTW_TKIP_MIC_LEN);
+		}
+		RTW_PRINT("GTK (%d) "KEY_FMT"\n", gtk_id,
+			KEY_ARG(psecuritypriv->dot118021XGrpKey[gtk_id].skey));
+	}
+
+	/* Update broadcast RX IV */
+	if (psecuritypriv->dot118021XGrpPrivacy == _AES_) {
+		sz = sizeof(psecuritypriv->iv_seq[0]);
+		for (i = 0 ; i < 4 ; i++) {
+			_rtw_memcpy(&tmp_iv_hdr, paoac_rpt->rxgtk_iv[i], sz);
+			tmp_iv_hdr = le64_to_cpu(tmp_iv_hdr);
+			pkt_pn = CCMPH_2_PN(tmp_iv_hdr);
+			_rtw_memcpy(psecuritypriv->iv_seq[i], &pkt_pn, sz);
+		}
+	}
+
+	rtw_clean_dk_section(adapter);
+
+	rtw_write8(adapter, REG_SECCFG, 0x0c);
+
+	#ifdef CONFIG_GTK_OL_DBG
+	/* if (gtk_keyindex != 5) */
+	dump_sec_cam(RTW_DBGDUMP, adapter);
+	dump_sec_cam_cache(RTW_DBGDUMP, adapter);
+	#endif
+}
+#endif /*CONFIG_GTK_OL*/
+
+static void rtw_dump_aoac_rpt(_adapter *adapter)
+{
+	struct pwrctrl_priv *pwrctl = adapter_to_pwrctl(adapter);
+	struct aoac_report *paoac_rpt = &pwrctl->wowlan_aoac_rpt;
+	int i = 0;
+
+	RTW_INFO_DUMP("[AOAC-RPT] IV -", paoac_rpt->iv, 8);
+	RTW_INFO_DUMP("[AOAC-RPT] Replay counter of EAPOL key - ",
+		paoac_rpt->replay_counter_eapol_key, 8);
+	RTW_INFO_DUMP("[AOAC-RPT] Group key - ", paoac_rpt->group_key, 32);
+	RTW_INFO("[AOAC-RPT] Key Index - %d\n", paoac_rpt->key_index);
+	RTW_INFO("[AOAC-RPT] Security Type - %d\n", paoac_rpt->security_type);
+	RTW_INFO("[AOAC-RPT] wow_pattern_idx - %d\n",
+		 paoac_rpt->wow_pattern_idx);
+	RTW_INFO("[AOAC-RPT] version_info - %d\n", paoac_rpt->version_info);
+	RTW_INFO("[AOAC-RPT] rekey_ok - %d\n", paoac_rpt->rekey_ok);
+	RTW_INFO_DUMP("[AOAC-RPT] RX PTK IV-", paoac_rpt->rxptk_iv, 8);
+	RTW_INFO_DUMP("[AOAC-RPT] RX GTK[0] IV-", paoac_rpt->rxgtk_iv[0], 8);
+	RTW_INFO_DUMP("[AOAC-RPT] RX GTK[1] IV-", paoac_rpt->rxgtk_iv[1], 8);
+	RTW_INFO_DUMP("[AOAC-RPT] RX GTK[2] IV-", paoac_rpt->rxgtk_iv[2], 8);
+	RTW_INFO_DUMP("[AOAC-RPT] RX GTK[3] IV-", paoac_rpt->rxgtk_iv[3], 8);
+}
+
+static void rtw_hal_get_aoac_rpt(_adapter *adapter)
+{
+	struct pwrctrl_priv *pwrctl = adapter_to_pwrctl(adapter);
+	struct aoac_report *paoac_rpt = &pwrctl->wowlan_aoac_rpt;
+	u32 page_offset = 0, page_number = 0;
+	u32 page_size = 0, buf_size = 0;
+	u8 *buffer = NULL;
+	u8 i = 0, tmp = 0;
+	int ret = -1;
+
+	/* read aoac report from rsvd page */
+	page_offset = pwrctl->wowlan_aoac_rpt_loc;
+	page_number = 1;
+
+	rtw_hal_get_def_var(adapter, HAL_DEF_TX_PAGE_SIZE, &page_size);
+	buf_size = page_size * page_number;
+
+	buffer = rtw_zvmalloc(buf_size);
+
+	if (buffer == NULL) {
+		RTW_ERR("%s buffer allocate failed size(%d)\n",
+			__func__, buf_size);
+		return;
+	}
+
+	RTW_INFO("Get AOAC Report from rsvd page_offset:%d\n", page_offset);
+
+	ret = rtw_hal_get_rsvd_page(adapter, page_offset,
+		page_number, buffer, buf_size);
+
+	if (ret == _FALSE) {
+		RTW_ERR("%s get aoac report failed\n", __func__);
+		rtw_warn_on(1);
+		goto _exit;
+	}
+
+	_rtw_memset(paoac_rpt, 0, sizeof(struct aoac_report));
+	_rtw_memcpy(paoac_rpt, buffer, sizeof(struct aoac_report));
+
+	for (i = 0 ; i < 4 ; i++) {
+		tmp = paoac_rpt->replay_counter_eapol_key[i];
+		paoac_rpt->replay_counter_eapol_key[i] =
+			paoac_rpt->replay_counter_eapol_key[7 - i];
+		paoac_rpt->replay_counter_eapol_key[7 - i] = tmp;
+	}
+
+	rtw_dump_aoac_rpt(adapter);
+
+_exit:
+	if (buffer)
+		rtw_vmfree(buffer, buf_size);
+}
+
+static void rtw_hal_update_tx_iv(_adapter *adapter)
+{
+	struct pwrctrl_priv *pwrctl = adapter_to_pwrctl(adapter);
+	struct aoac_report *paoac_rpt = &pwrctl->wowlan_aoac_rpt;
+	struct sta_info	*psta;
+	struct mlme_ext_priv	*pmlmeext = &(adapter->mlmeextpriv);
+	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
+	struct security_priv	*psecpriv = &adapter->securitypriv;
+
+	u16 val16 = 0;
+	u32 val32 = 0;
+	u64 txiv = 0;
+	u8 *pval = NULL;
+
+	psta = rtw_get_stainfo(&adapter->stapriv,
+			       get_my_bssid(&pmlmeinfo->network));
+
+	/* Update TX iv data. */
+	pval = (u8 *)&paoac_rpt->iv;
+
+	if (psecpriv->dot11PrivacyAlgrthm == _TKIP_) {
+		val16 = ((u16)(paoac_rpt->iv[2]) << 0) +
+			((u16)(paoac_rpt->iv[0]) << 8);
+		val32 = ((u32)(paoac_rpt->iv[4]) << 0) +
+			((u32)(paoac_rpt->iv[5]) << 8) +
+			((u32)(paoac_rpt->iv[6]) << 16) +
+			((u32)(paoac_rpt->iv[7]) << 24);
+	} else if (psecpriv->dot11PrivacyAlgrthm == _AES_) {
+		val16 = ((u16)(paoac_rpt->iv[0]) << 0) +
+			((u16)(paoac_rpt->iv[1]) << 8);
+		val32 = ((u32)(paoac_rpt->iv[4]) << 0) +
+			((u32)(paoac_rpt->iv[5]) << 8) +
+			((u32)(paoac_rpt->iv[6]) << 16) +
+			((u32)(paoac_rpt->iv[7]) << 24);
+	}
+
+	if (psta) {
+		txiv = val16 + ((u64)val32 << 16);
+		if (txiv != 0)
+			psta->dot11txpn.val = txiv;
+	}
+}
+
+static void rtw_hal_update_sw_security_info(_adapter *adapter)
+{
+	struct security_priv *psecpriv = &adapter->securitypriv;
+	u8 sz = sizeof (psecpriv->iv_seq);
+
+	rtw_hal_update_tx_iv(adapter);
+#ifdef CONFIG_GTK_OL
+	if (psecpriv->binstallKCK_KEK == _TRUE &&
+	    psecpriv->ndisauthtype == Ndis802_11AuthModeWPA2PSK)
+		rtw_hal_update_gtk_offload_info(adapter);
+#else
+	_rtw_memset(psecpriv->iv_seq, 0, sz);
+#endif
+}
+
+static u8 rtw_hal_set_keep_alive_cmd(_adapter *adapter, u8 enable, u8 pkt_type)
+{
+	struct hal_ops *pHalFunc = &adapter->hal_func;
+
+	u8 u1H2CKeepAliveParm[H2C_KEEP_ALIVE_CTRL_LEN] = {0};
+	u8 adopt = 1, check_period = 5;
+	u8 ret = _FAIL;
+	u8 hw_port = rtw_hal_get_port(adapter);
+
+	SET_H2CCMD_KEEPALIVE_PARM_ENABLE(u1H2CKeepAliveParm, enable);
+	SET_H2CCMD_KEEPALIVE_PARM_ADOPT(u1H2CKeepAliveParm, adopt);
+	SET_H2CCMD_KEEPALIVE_PARM_PKT_TYPE(u1H2CKeepAliveParm, pkt_type);
+	SET_H2CCMD_KEEPALIVE_PARM_CHECK_PERIOD(u1H2CKeepAliveParm, check_period);
+#ifdef CONFIG_FW_MULTI_PORT_SUPPORT
+	SET_H2CCMD_KEEPALIVE_PARM_PORT_NUM(u1H2CKeepAliveParm, hw_port);
+	RTW_INFO("%s(): enable = %d, port = %d\n", __func__, enable, hw_port);
+#else
+	RTW_INFO("%s(): enable = %d\n", __func__, enable);
+#endif
+	ret = rtw_hal_fill_h2c_cmd(adapter,
+				   H2C_KEEP_ALIVE,
+				   H2C_KEEP_ALIVE_CTRL_LEN,
+				   u1H2CKeepAliveParm);
+
+	return ret;
+}
+
+static u8 rtw_hal_set_disconnect_decision_cmd(_adapter *adapter, u8 enable)
+{
+	struct hal_ops *pHalFunc = &adapter->hal_func;
+	u8 u1H2CDisconDecisionParm[H2C_DISCON_DECISION_LEN] = {0};
+	u8 adopt = 1, check_period = 30, trypkt_num = 5;
+	u8 ret = _FAIL;
+	u8 hw_port = rtw_hal_get_port(adapter);
+
+	SET_H2CCMD_DISCONDECISION_PARM_ENABLE(u1H2CDisconDecisionParm, enable);
+	SET_H2CCMD_DISCONDECISION_PARM_ADOPT(u1H2CDisconDecisionParm, adopt);
+	SET_H2CCMD_DISCONDECISION_PARM_CHECK_PERIOD(u1H2CDisconDecisionParm, check_period);
+	SET_H2CCMD_DISCONDECISION_PARM_TRY_PKT_NUM(u1H2CDisconDecisionParm, trypkt_num);
+#ifdef CONFIG_FW_MULTI_PORT_SUPPORT
+	SET_H2CCMD_DISCONDECISION_PORT_NUM(u1H2CDisconDecisionParm, hw_port);
+	RTW_INFO("%s(): enable = %d, port = %d\n", __func__, enable, hw_port);
+#else
+	RTW_INFO("%s(): enable = %d\n", __func__, enable);
+#endif
+
+	ret = rtw_hal_fill_h2c_cmd(adapter,
+				   H2C_DISCON_DECISION,
+				   H2C_DISCON_DECISION_LEN,
+				   u1H2CDisconDecisionParm);
+	return ret;
+}
+
+static u8 rtw_hal_set_wowlan_ctrl_cmd(_adapter *adapter, u8 enable, u8 change_unit)
+{
+	struct registry_priv  *registry_par = &adapter->registrypriv;
+	struct security_priv *psecpriv = &adapter->securitypriv;
+	struct pwrctrl_priv *ppwrpriv = adapter_to_pwrctl(adapter);
+	struct hal_ops *pHalFunc = &adapter->hal_func;
+
+	u8 u1H2CWoWlanCtrlParm[H2C_WOWLAN_LEN] = {0};
+	u8 discont_wake = 0, gpionum = 0, gpio_dur = 0;
+	u8 hw_unicast = 0, gpio_pulse_cnt = 0, gpio_pulse_en = 0;
+	u8 sdio_wakeup_enable = 1;
+	u8 gpio_high_active = 0;
+	u8 magic_pkt = 0;
+	u8 gpio_unit = 0; /*0: 64ns, 1: 8ms*/
+	u8 ret = _FAIL;
+#ifdef CONFIG_DIS_UPHY
+	u8 dis_uphy = 0, dis_uphy_unit = 0, dis_uphy_time = 0;
+#endif /* CONFIG_DIS_UPHY */
+
+#ifdef CONFIG_GPIO_WAKEUP
+	gpio_high_active = ppwrpriv->is_high_active;
+	gpionum = WAKEUP_GPIO_IDX;
+	sdio_wakeup_enable = 0;
+#endif /* CONFIG_GPIO_WAKEUP */
+
+	if (!ppwrpriv->wowlan_pno_enable &&
+	    registry_par->wakeup_event & BIT(0))
+		magic_pkt = enable;
+
+	if ((registry_par->wakeup_event & BIT(1)) &&
+	    (psecpriv->dot11PrivacyAlgrthm == _WEP40_ ||
+	     psecpriv->dot11PrivacyAlgrthm == _WEP104_))
+			hw_unicast = 1;
+
+	if (registry_par->wakeup_event & BIT(2))
+		discont_wake = enable;
+
+	RTW_INFO("%s(): enable=%d change_unit=%d\n", __func__,
+		 enable, change_unit);
+
+	/* time = (gpio_dur/2) * gpio_unit, default:256 ms */
+	if (enable && change_unit) {
+		gpio_dur = 0x40;
+		gpio_unit = 1;
+		gpio_pulse_en = 1;
+	}
+
+#ifdef CONFIG_PLATFORM_ARM_RK3188
+	if (enable) {
+		gpio_pulse_en = 1;
+		gpio_pulse_cnt = 0x04;
+	}
+#endif
+
+	SET_H2CCMD_WOWLAN_FUNC_ENABLE(u1H2CWoWlanCtrlParm, enable);
+	SET_H2CCMD_WOWLAN_PATTERN_MATCH_ENABLE(u1H2CWoWlanCtrlParm, enable);
+	SET_H2CCMD_WOWLAN_MAGIC_PKT_ENABLE(u1H2CWoWlanCtrlParm, magic_pkt);
+	SET_H2CCMD_WOWLAN_UNICAST_PKT_ENABLE(u1H2CWoWlanCtrlParm, hw_unicast);
+	SET_H2CCMD_WOWLAN_ALL_PKT_DROP(u1H2CWoWlanCtrlParm, 0);
+	SET_H2CCMD_WOWLAN_GPIO_ACTIVE(u1H2CWoWlanCtrlParm, gpio_high_active);
+
+#ifdef CONFIG_GTK_OL
+	if (psecpriv->binstallKCK_KEK == _TRUE &&
+	    psecpriv->ndisauthtype == Ndis802_11AuthModeWPA2PSK)
+		SET_H2CCMD_WOWLAN_REKEY_WAKE_UP(u1H2CWoWlanCtrlParm, 0);
+	else
+		SET_H2CCMD_WOWLAN_REKEY_WAKE_UP(u1H2CWoWlanCtrlParm, 1);
+#else
+	SET_H2CCMD_WOWLAN_REKEY_WAKE_UP(u1H2CWoWlanCtrlParm, enable);
+#endif
+	SET_H2CCMD_WOWLAN_DISCONNECT_WAKE_UP(u1H2CWoWlanCtrlParm, discont_wake);
+	SET_H2CCMD_WOWLAN_GPIONUM(u1H2CWoWlanCtrlParm, gpionum);
+	SET_H2CCMD_WOWLAN_DATAPIN_WAKE_UP(u1H2CWoWlanCtrlParm, sdio_wakeup_enable);
+
+	SET_H2CCMD_WOWLAN_GPIO_DURATION(u1H2CWoWlanCtrlParm, gpio_dur);
+	SET_H2CCMD_WOWLAN_CHANGE_UNIT(u1H2CWoWlanCtrlParm, gpio_unit);
+
+	SET_H2CCMD_WOWLAN_GPIO_PULSE_EN(u1H2CWoWlanCtrlParm, gpio_pulse_en);
+	SET_H2CCMD_WOWLAN_GPIO_PULSE_COUNT(u1H2CWoWlanCtrlParm, gpio_pulse_cnt);
+
+#ifdef CONFIG_WAKEUP_GPIO_INPUT_MODE
+	if (enable)
+		SET_H2CCMD_WOWLAN_GPIO_INPUT_EN(u1H2CWoWlanCtrlParm, 1);
+#endif
+
+#ifdef CONFIG_DIS_UPHY
+	if (enable) {
+		dis_uphy = 1;
+		/* time unit: 0 -> ms, 1 -> 256 ms*/
+		dis_uphy_unit = 1;
+		dis_uphy_time = 0x4;
+	}
+
+	SET_H2CCMD_WOWLAN_DISABLE_UPHY(u1H2CWoWlanCtrlParm, dis_uphy);
+	SET_H2CCMD_WOWLAN_UNIT_FOR_UPHY_DISABLE(u1H2CWoWlanCtrlParm, dis_uphy_unit);
+	SET_H2CCMD_WOWLAN_TIME_FOR_UPHY_DISABLE(u1H2CWoWlanCtrlParm, dis_uphy_time);
+	if (ppwrpriv->hst2dev_high_active == 1)
+		SET_H2CCMD_WOWLAN_RISE_HST2DEV(u1H2CWoWlanCtrlParm, 1);
+#ifdef CONFIG_RTW_ONE_PIN_GPIO
+	SET_H2CCMD_WOWLAN_GPIO_INPUT_EN(u1H2CWoWlanCtrlParm, 1);
+	SET_H2CCMD_WOWLAN_DEV2HST_EN(u1H2CWoWlanCtrlParm, 1);
+	SET_H2CCMD_WOWLAN_HST2DEV_EN(u1H2CWoWlanCtrlParm, 0);
+#else
+	SET_H2CCMD_WOWLAN_HST2DEV_EN(u1H2CWoWlanCtrlParm, 1);
+#endif /* CONFIG_RTW_ONE_PIN_GPIO */
+#endif /* CONFIG_DIS_UPHY */
+
+
+	ret = rtw_hal_fill_h2c_cmd(adapter,
+				   H2C_WOWLAN,
+				   H2C_WOWLAN_LEN,
+				   u1H2CWoWlanCtrlParm);
+	return ret;
+}
+
+static u8 rtw_hal_set_remote_wake_ctrl_cmd(_adapter *adapter, u8 enable)
+{
+	struct hal_ops *pHalFunc = &adapter->hal_func;
+	struct security_priv *psecuritypriv = &(adapter->securitypriv);
+	struct pwrctrl_priv *ppwrpriv = adapter_to_pwrctl(adapter);
+	struct registry_priv *pregistrypriv = &adapter->registrypriv;
+	u8 u1H2CRemoteWakeCtrlParm[H2C_REMOTE_WAKE_CTRL_LEN] = {0};
+	u8 ret = _FAIL, count = 0;
+
+	RTW_INFO("%s(): enable=%d\n", __func__, enable);
+
+	if (!ppwrpriv->wowlan_pno_enable) {
+		SET_H2CCMD_REMOTE_WAKECTRL_ENABLE(
+			u1H2CRemoteWakeCtrlParm, enable);
+		SET_H2CCMD_REMOTE_WAKE_CTRL_ARP_OFFLOAD_EN(
+			u1H2CRemoteWakeCtrlParm, 1);
+#ifdef CONFIG_GTK_OL
+		if (psecuritypriv->binstallKCK_KEK == _TRUE &&
+		    psecuritypriv->ndisauthtype == Ndis802_11AuthModeWPA2PSK) {
+			SET_H2CCMD_REMOTE_WAKE_CTRL_GTK_OFFLOAD_EN(
+				u1H2CRemoteWakeCtrlParm, 1);
+		} else {
+			RTW_INFO("no kck kek\n");
+			SET_H2CCMD_REMOTE_WAKE_CTRL_GTK_OFFLOAD_EN(
+				u1H2CRemoteWakeCtrlParm, 0);
+		}
+#endif /* CONFIG_GTK_OL */
+
+#ifdef CONFIG_IPV6
+		if (ppwrpriv->wowlan_ns_offload_en == _TRUE) {
+			RTW_INFO("enable NS offload\n");
+			SET_H2CCMD_REMOTE_WAKE_CTRL_NDP_OFFLOAD_EN(
+				u1H2CRemoteWakeCtrlParm, enable);
+		}
+
+		/*
+		 * filter NetBios name service pkt to avoid being waked-up
+		 * by this kind of unicast pkt this exceptional modification
+		 * is used for match competitor's behavior
+		 */
+
+		SET_H2CCMD_REMOTE_WAKE_CTRL_NBNS_FILTER_EN(
+			u1H2CRemoteWakeCtrlParm, enable);
+#endif /*CONFIG_IPV6*/
+
+#ifdef CONFIG_RTL8192F
+		if (IS_HARDWARE_TYPE_8192F(adapter)){
+			SET_H2CCMD_REMOTE_WAKE_CTRL_FW_UNICAST_EN(
+				u1H2CRemoteWakeCtrlParm, enable);
+		}
+#endif /* CONFIG_RTL8192F */
+
+		if ((psecuritypriv->dot11PrivacyAlgrthm == _AES_) ||
+			(psecuritypriv->dot11PrivacyAlgrthm == _TKIP_) ||
+			(psecuritypriv->dot11PrivacyAlgrthm == _NO_PRIVACY_)) {
+			SET_H2CCMD_REMOTE_WAKE_CTRL_ARP_ACTION(
+				u1H2CRemoteWakeCtrlParm, 0);
+		} else {
+			SET_H2CCMD_REMOTE_WAKE_CTRL_ARP_ACTION(
+				u1H2CRemoteWakeCtrlParm, 1);
+		}
+
+		if (psecuritypriv->dot11PrivacyAlgrthm == _TKIP_ &&
+		    psecuritypriv->ndisauthtype == Ndis802_11AuthModeWPA2PSK) {
+			SET_H2CCMD_REMOTE_WAKE_CTRL_TKIP_OFFLOAD_EN(
+					u1H2CRemoteWakeCtrlParm, enable);
+
+			if (IS_HARDWARE_TYPE_8188E(adapter) ||
+			    IS_HARDWARE_TYPE_8812(adapter)) {
+				SET_H2CCMD_REMOTE_WAKE_CTRL_TKIP_OFFLOAD_EN(
+					u1H2CRemoteWakeCtrlParm, 0);
+				SET_H2CCMD_REMOTE_WAKE_CTRL_ARP_ACTION(
+					u1H2CRemoteWakeCtrlParm, 1);
+			}
+		}
+
+		SET_H2CCMD_REMOTE_WAKE_CTRL_FW_PARSING_UNTIL_WAKEUP(
+			u1H2CRemoteWakeCtrlParm, 1);
+	}
+#ifdef CONFIG_PNO_SUPPORT
+	else {
+		SET_H2CCMD_REMOTE_WAKECTRL_ENABLE(
+			u1H2CRemoteWakeCtrlParm, enable);
+		SET_H2CCMD_REMOTE_WAKE_CTRL_NLO_OFFLOAD_EN(
+			u1H2CRemoteWakeCtrlParm, enable);
+	}
+#endif
+
+#ifdef CONFIG_P2P_WOWLAN
+	if (_TRUE == ppwrpriv->wowlan_p2p_mode) {
+		RTW_INFO("P2P OFFLOAD ENABLE\n");
+		SET_H2CCMD_REMOTE_WAKE_CTRL_P2P_OFFLAD_EN(u1H2CRemoteWakeCtrlParm, 1);
+	} else {
+		RTW_INFO("P2P OFFLOAD DISABLE\n");
+		SET_H2CCMD_REMOTE_WAKE_CTRL_P2P_OFFLAD_EN(u1H2CRemoteWakeCtrlParm, 0);
+	}
+#endif /* CONFIG_P2P_WOWLAN */
+
+
+	ret = rtw_hal_fill_h2c_cmd(adapter,
+				   H2C_REMOTE_WAKE_CTRL,
+				   H2C_REMOTE_WAKE_CTRL_LEN,
+				   u1H2CRemoteWakeCtrlParm);
+	return ret;
+}
+
+static u8 rtw_hal_set_global_info_cmd(_adapter *adapter, u8 group_alg, u8 pairwise_alg)
+{
+	struct hal_ops *pHalFunc = &adapter->hal_func;
+	u8 ret = _FAIL;
+	u8 u1H2CAOACGlobalInfoParm[H2C_AOAC_GLOBAL_INFO_LEN] = {0};
+
+	RTW_INFO("%s(): group_alg=%d pairwise_alg=%d\n",
+		 __func__, group_alg, pairwise_alg);
+	SET_H2CCMD_AOAC_GLOBAL_INFO_PAIRWISE_ENC_ALG(u1H2CAOACGlobalInfoParm,
+			pairwise_alg);
+	SET_H2CCMD_AOAC_GLOBAL_INFO_GROUP_ENC_ALG(u1H2CAOACGlobalInfoParm,
+			group_alg);
+
+	ret = rtw_hal_fill_h2c_cmd(adapter,
+				   H2C_AOAC_GLOBAL_INFO,
+				   H2C_AOAC_GLOBAL_INFO_LEN,
+				   u1H2CAOACGlobalInfoParm);
+
+	return ret;
+}
+
+#ifdef CONFIG_PNO_SUPPORT
+static u8 rtw_hal_set_scan_offload_info_cmd(_adapter *adapter,
+		PRSVDPAGE_LOC rsvdpageloc, u8 enable)
+{
+	struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(adapter);
+	struct hal_ops *pHalFunc = &adapter->hal_func;
+
+	u8 u1H2CScanOffloadInfoParm[H2C_SCAN_OFFLOAD_CTRL_LEN] = {0};
+	u8 res = 0, count = 0, ret = _FAIL;
+
+	RTW_INFO("%s: loc_probe_packet:%d, loc_scan_info: %d loc_ssid_info:%d\n",
+		 __func__, rsvdpageloc->LocProbePacket,
+		 rsvdpageloc->LocScanInfo, rsvdpageloc->LocSSIDInfo);
+
+	SET_H2CCMD_AOAC_NLO_FUN_EN(u1H2CScanOffloadInfoParm, enable);
+	SET_H2CCMD_AOAC_NLO_IPS_EN(u1H2CScanOffloadInfoParm, enable);
+	SET_H2CCMD_AOAC_RSVDPAGE_LOC_SCAN_INFO(u1H2CScanOffloadInfoParm,
+					       rsvdpageloc->LocScanInfo);
+	SET_H2CCMD_AOAC_RSVDPAGE_LOC_PROBE_PACKET(u1H2CScanOffloadInfoParm,
+			rsvdpageloc->LocProbePacket);
+	/*
+		SET_H2CCMD_AOAC_RSVDPAGE_LOC_SSID_INFO(u1H2CScanOffloadInfoParm,
+				rsvdpageloc->LocSSIDInfo);
+	*/
+	ret = rtw_hal_fill_h2c_cmd(adapter,
+				   H2C_D0_SCAN_OFFLOAD_INFO,
+				   H2C_SCAN_OFFLOAD_CTRL_LEN,
+				   u1H2CScanOffloadInfoParm);
+	return ret;
+}
+#endif /* CONFIG_PNO_SUPPORT */
+
+void rtw_hal_set_fw_wow_related_cmd(_adapter *padapter, u8 enable)
+{
+	struct security_priv *psecpriv = &padapter->securitypriv;
+	struct pwrctrl_priv *ppwrpriv = adapter_to_pwrctl(padapter);
+	struct mlme_priv	*pmlmepriv = &padapter->mlmepriv;
+	struct registry_priv *pregistry = &padapter->registrypriv;
+	struct sta_info *psta = NULL;
+	u16 media_status_rpt;
+	u8	pkt_type = 0;
+	u8 ret = _SUCCESS;
+
+	RTW_PRINT("+%s()+: enable=%d\n", __func__, enable);
+
+	rtw_hal_set_wowlan_ctrl_cmd(padapter, enable, _FALSE);
+
+	if (enable) {
+		rtw_hal_set_global_info_cmd(padapter,
+					    psecpriv->dot118021XGrpPrivacy,
+					    psecpriv->dot11PrivacyAlgrthm);
+
+		if (!(ppwrpriv->wowlan_pno_enable)) {
+			if (pregistry->wakeup_event & BIT(2))
+				rtw_hal_set_disconnect_decision_cmd(padapter,
+								    enable);
+#ifdef CONFIG_ARP_KEEP_ALIVE
+			if ((psecpriv->dot11PrivacyAlgrthm == _WEP40_) ||
+			    (psecpriv->dot11PrivacyAlgrthm == _WEP104_))
+				pkt_type = 0;
+			else
+				pkt_type = 1;
+#else
+			pkt_type = 0;
+#endif /* CONFIG_ARP_KEEP_ALIVE */
+			rtw_hal_set_keep_alive_cmd(padapter, enable, pkt_type);
+		}
+		rtw_hal_set_remote_wake_ctrl_cmd(padapter, enable);
+#ifdef CONFIG_PNO_SUPPORT
+		rtw_hal_check_pno_enabled(padapter);
+#endif /* CONFIG_PNO_SUPPORT */
+	} else {
+#if 0
+		{
+			u32 PageSize = 0;
+			rtw_hal_get_def_var(padapter, HAL_DEF_TX_PAGE_SIZE, (u8 *)&PageSize);
+			dump_TX_FIFO(padapter, 4, PageSize);
+		}
+#endif
+
+		rtw_hal_set_remote_wake_ctrl_cmd(padapter, enable);
+	}
+	RTW_PRINT("-%s()-\n", __func__);
+}
+#endif /* CONFIG_WOWLAN */
+
+#ifdef CONFIG_AP_WOWLAN
+static u8 rtw_hal_set_ap_wowlan_ctrl_cmd(_adapter *adapter, u8 enable)
+{
+	struct security_priv *psecpriv = &adapter->securitypriv;
+	struct pwrctrl_priv *ppwrpriv = adapter_to_pwrctl(adapter);
+	struct hal_ops *pHalFunc = &adapter->hal_func;
+
+	u8 u1H2CAPWoWlanCtrlParm[H2C_AP_WOW_GPIO_CTRL_LEN] = {0};
+	u8 gpionum = 0, gpio_dur = 0;
+	u8 gpio_pulse = enable;
+	u8 sdio_wakeup_enable = 1;
+	u8 gpio_high_active = 0;
+	u8 ret = _FAIL;
+
+#ifdef CONFIG_GPIO_WAKEUP
+	gpio_high_active = ppwrpriv->is_high_active;
+	gpionum = WAKEUP_GPIO_IDX;
+	sdio_wakeup_enable = 0;
+#endif /*CONFIG_GPIO_WAKEUP*/
+
+	RTW_INFO("%s(): enable=%d\n", __func__, enable);
+
+	SET_H2CCMD_AP_WOW_GPIO_CTRL_INDEX(u1H2CAPWoWlanCtrlParm,
+					  gpionum);
+	SET_H2CCMD_AP_WOW_GPIO_CTRL_PLUS(u1H2CAPWoWlanCtrlParm,
+					 gpio_pulse);
+	SET_H2CCMD_AP_WOW_GPIO_CTRL_HIGH_ACTIVE(u1H2CAPWoWlanCtrlParm,
+						gpio_high_active);
+	SET_H2CCMD_AP_WOW_GPIO_CTRL_EN(u1H2CAPWoWlanCtrlParm,
+				       enable);
+	SET_H2CCMD_AP_WOW_GPIO_CTRL_DURATION(u1H2CAPWoWlanCtrlParm,
+					     gpio_dur);
+
+	ret = rtw_hal_fill_h2c_cmd(adapter,
+				   H2C_AP_WOW_GPIO_CTRL,
+				   H2C_AP_WOW_GPIO_CTRL_LEN,
+				   u1H2CAPWoWlanCtrlParm);
+
+	return ret;
+}
+
+static u8 rtw_hal_set_ap_offload_ctrl_cmd(_adapter *adapter, u8 enable)
+{
+	struct hal_ops *pHalFunc = &adapter->hal_func;
+	u8 u1H2CAPOffloadCtrlParm[H2C_WOWLAN_LEN] = {0};
+	u8 ret = _FAIL;
+
+	RTW_INFO("%s(): bFuncEn=%d\n", __func__, enable);
+
+	SET_H2CCMD_AP_WOWLAN_EN(u1H2CAPOffloadCtrlParm, enable);
+
+	ret = rtw_hal_fill_h2c_cmd(adapter,
+				   H2C_AP_OFFLOAD,
+				   H2C_AP_OFFLOAD_LEN,
+				   u1H2CAPOffloadCtrlParm);
+
+	return ret;
+}
+
+static u8 rtw_hal_set_ap_ps_cmd(_adapter *adapter, u8 enable)
+{
+	struct hal_ops *pHalFunc = &adapter->hal_func;
+	u8 ap_ps_parm[H2C_AP_PS_LEN] = {0};
+	u8 ret = _FAIL;
+
+	RTW_INFO("%s(): enable=%d\n" , __func__ , enable);
+
+	SET_H2CCMD_AP_WOW_PS_EN(ap_ps_parm, enable);
+#ifndef CONFIG_USB_HCI
+	SET_H2CCMD_AP_WOW_PS_32K_EN(ap_ps_parm, enable);
+#endif /*CONFIG_USB_HCI*/
+	SET_H2CCMD_AP_WOW_PS_RF(ap_ps_parm, enable);
+
+	if (enable)
+		SET_H2CCMD_AP_WOW_PS_DURATION(ap_ps_parm, 0x32);
+	else
+		SET_H2CCMD_AP_WOW_PS_DURATION(ap_ps_parm, 0x0);
+
+	ret = rtw_hal_fill_h2c_cmd(adapter, H2C_SAP_PS_,
+				   H2C_AP_PS_LEN, ap_ps_parm);
+
+	return ret;
+}
+
+static void rtw_hal_set_ap_rsvdpage_loc_cmd(PADAPTER padapter,
+		PRSVDPAGE_LOC rsvdpageloc)
+{
+	struct hal_ops *pHalFunc = &padapter->hal_func;
+	u8 rsvdparm[H2C_AOAC_RSVDPAGE_LOC_LEN] = {0};
+	u8 ret = _FAIL, header = 0;
+
+	if (pHalFunc->fill_h2c_cmd == NULL) {
+		RTW_INFO("%s: Please hook fill_h2c_cmd first!\n", __func__);
+		return;
+	}
+
+	header = rtw_read8(padapter, REG_BCNQ_BDNY);
+
+	RTW_INFO("%s: beacon: %d, probeRsp: %d, header:0x%02x\n", __func__,
+		 rsvdpageloc->LocApOffloadBCN,
+		 rsvdpageloc->LocProbeRsp,
+		 header);
+
+	SET_H2CCMD_AP_WOWLAN_RSVDPAGE_LOC_BCN(rsvdparm,
+				      rsvdpageloc->LocApOffloadBCN + header);
+
+	ret = rtw_hal_fill_h2c_cmd(padapter, H2C_BCN_RSVDPAGE,
+				   H2C_BCN_RSVDPAGE_LEN, rsvdparm);
+
+	if (ret == _FAIL)
+		RTW_INFO("%s: H2C_BCN_RSVDPAGE cmd fail\n", __func__);
+
+	rtw_msleep_os(10);
+
+	_rtw_memset(&rsvdparm, 0, sizeof(rsvdparm));
+
+	SET_H2CCMD_AP_WOWLAN_RSVDPAGE_LOC_ProbeRsp(rsvdparm,
+			rsvdpageloc->LocProbeRsp + header);
+
+	ret = rtw_hal_fill_h2c_cmd(padapter, H2C_PROBERSP_RSVDPAGE,
+				   H2C_PROBERSP_RSVDPAGE_LEN, rsvdparm);
+
+	if (ret == _FAIL)
+		RTW_INFO("%s: H2C_PROBERSP_RSVDPAGE cmd fail\n", __func__);
+
+	rtw_msleep_os(10);
+}
+
+static void rtw_hal_set_fw_ap_wow_related_cmd(_adapter *padapter, u8 enable)
+{
+	rtw_hal_set_ap_offload_ctrl_cmd(padapter, enable);
+	rtw_hal_set_ap_wowlan_ctrl_cmd(padapter, enable);
+	rtw_hal_set_ap_ps_cmd(padapter, enable);
+}
+
+static void rtw_hal_ap_wow_enable(_adapter *padapter)
+{
+	struct pwrctrl_priv *pwrctl = adapter_to_pwrctl(padapter);
+	struct security_priv *psecuritypriv = &padapter->securitypriv;
+	struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
+	struct hal_ops *pHalFunc = &padapter->hal_func;
+	struct sta_info *psta = NULL;
+	PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter);
+#ifdef DBG_CHECK_FW_PS_STATE
+	struct dvobj_priv *psdpriv = padapter->dvobj;
+	struct debug_priv *pdbgpriv = &psdpriv->drv_dbg;
+#endif /*DBG_CHECK_FW_PS_STATE*/
+	int res;
+	u16 media_status_rpt;
+
+	RTW_INFO("%s, WOWLAN_AP_ENABLE\n", __func__);
+#ifdef DBG_CHECK_FW_PS_STATE
+	if (rtw_fw_ps_state(padapter) == _FAIL) {
+		pdbgpriv->dbg_enwow_dload_fw_fail_cnt++;
+		RTW_PRINT("wowlan enable no leave 32k\n");
+	}
+#endif /*DBG_CHECK_FW_PS_STATE*/
+
+	/* 1. Download WOWLAN FW*/
+	rtw_hal_fw_dl(padapter, _TRUE);
+
+	media_status_rpt = RT_MEDIA_CONNECT;
+	rtw_hal_set_hwreg(padapter, HW_VAR_H2C_FW_JOINBSSRPT,
+			  (u8 *)&media_status_rpt);
+
+	issue_beacon(padapter, 0);
+
+	rtw_msleep_os(2);
+	#if defined(CONFIG_RTL8188E)
+	if (IS_HARDWARE_TYPE_8188E(padapter))
+		rtw_hal_disable_tx_report(padapter);
+	#endif
+	/* RX DMA stop */
+	res = rtw_hal_pause_rx_dma(padapter);
+	if (res == _FAIL)
+		RTW_PRINT("[WARNING] pause RX DMA fail\n");
+
+#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
+	/* Enable CPWM2 only. */
+	res = rtw_hal_enable_cpwm2(padapter);
+	if (res == _FAIL)
+		RTW_PRINT("[WARNING] enable cpwm2 fail\n");
+#endif
+
+#ifdef CONFIG_GPIO_WAKEUP
+	rtw_hal_switch_gpio_wl_ctrl(padapter, WAKEUP_GPIO_IDX, _TRUE);
+#endif
+	/* 5. Set Enable WOWLAN H2C command. */
+	RTW_PRINT("Set Enable AP WOWLan cmd\n");
+	rtw_hal_set_fw_ap_wow_related_cmd(padapter, 1);
+
+	rtw_write8(padapter, REG_MCUTST_WOWLAN, 0);
+#ifdef CONFIG_USB_HCI
+	rtw_mi_intf_stop(padapter);
+#endif
+#if defined(CONFIG_USB_HCI) || defined(CONFIG_PCI_HCI)
+	/* Invoid SE0 reset signal during suspending*/
+	rtw_write8(padapter, REG_RSV_CTRL, 0x20);
+	if (IS_8188F(pHalData->version_id) == FALSE
+		&& IS_8188GTV(pHalData->version_id) == FALSE)
+		rtw_write8(padapter, REG_RSV_CTRL, 0x60);
+#endif
+}
+
+static void rtw_hal_ap_wow_disable(_adapter *padapter)
+{
+	struct pwrctrl_priv *pwrctl = adapter_to_pwrctl(padapter);
+	struct hal_ops *pHalFunc = &padapter->hal_func;
+#ifdef DBG_CHECK_FW_PS_STATE
+	struct dvobj_priv *psdpriv = padapter->dvobj;
+	struct debug_priv *pdbgpriv = &psdpriv->drv_dbg;
+#endif /*DBG_CHECK_FW_PS_STATE*/
+	u16 media_status_rpt;
+	u8 val8;
+
+	RTW_INFO("%s, WOWLAN_AP_DISABLE\n", __func__);
+	/* 1. Read wakeup reason*/
+	pwrctl->wowlan_wake_reason = rtw_read8(padapter, REG_MCUTST_WOWLAN);
+
+	RTW_PRINT("wakeup_reason: 0x%02x\n",
+		  pwrctl->wowlan_wake_reason);
+
+	rtw_hal_set_fw_ap_wow_related_cmd(padapter, 0);
+
+	rtw_msleep_os(2);
+#ifdef DBG_CHECK_FW_PS_STATE
+	if (rtw_fw_ps_state(padapter) == _FAIL) {
+		pdbgpriv->dbg_diswow_dload_fw_fail_cnt++;
+		RTW_PRINT("wowlan enable no leave 32k\n");
+	}
+#endif /*DBG_CHECK_FW_PS_STATE*/
+
+	#if defined(CONFIG_RTL8188E)
+	if (IS_HARDWARE_TYPE_8188E(padapter))
+		rtw_hal_enable_tx_report(padapter);
+	#endif
+
+	rtw_hal_force_enable_rxdma(padapter);
+
+	rtw_hal_fw_dl(padapter, _FALSE);
+
+#ifdef CONFIG_GPIO_WAKEUP
+#ifdef CONFIG_RTW_ONE_PIN_GPIO
+	rtw_hal_set_input_gpio(padapter, WAKEUP_GPIO_IDX);
+#else
+	#ifdef CONFIG_WAKEUP_GPIO_INPUT_MODE
+	if (pwrctl->is_high_active == 0)
+		rtw_hal_set_input_gpio(padapter, WAKEUP_GPIO_IDX);
+	else
+		rtw_hal_set_output_gpio(padapter, WAKEUP_GPIO_IDX, 0);
+	#else
+	val8 = (pwrctl->is_high_active == 0) ? 1 : 0;
+	RTW_PRINT("Set Wake GPIO to default(%d).\n", val8);
+	rtw_hal_set_output_gpio(padapter, WAKEUP_GPIO_IDX, val8);
+
+	rtw_hal_switch_gpio_wl_ctrl(padapter, WAKEUP_GPIO_IDX, _FALSE);
+	#endif/*CONFIG_WAKEUP_GPIO_INPUT_MODE*/
+#endif /* CONFIG_RTW_ONE_PIN_GPIO */
+#endif
+	media_status_rpt = RT_MEDIA_CONNECT;
+
+	rtw_hal_set_hwreg(padapter, HW_VAR_H2C_FW_JOINBSSRPT,
+			  (u8 *)&media_status_rpt);
+
+	issue_beacon(padapter, 0);
+}
+#endif /*CONFIG_AP_WOWLAN*/
+
+#ifdef CONFIG_P2P_WOWLAN
+static int update_hidden_ssid(u8 *ies, u32 ies_len, u8 hidden_ssid_mode)
+{
+	u8 *ssid_ie;
+	sint ssid_len_ori;
+	int len_diff = 0;
+
+	ssid_ie = rtw_get_ie(ies,  WLAN_EID_SSID, &ssid_len_ori, ies_len);
+
+	/* RTW_INFO("%s hidden_ssid_mode:%u, ssid_ie:%p, ssid_len_ori:%d\n", __FUNCTION__, hidden_ssid_mode, ssid_ie, ssid_len_ori); */
+
+	if (ssid_ie && ssid_len_ori > 0) {
+		switch (hidden_ssid_mode) {
+		case 1: {
+			u8 *next_ie = ssid_ie + 2 + ssid_len_ori;
+			u32 remain_len = 0;
+
+			remain_len = ies_len - (next_ie - ies);
+
+			ssid_ie[1] = 0;
+			_rtw_memcpy(ssid_ie + 2, next_ie, remain_len);
+			len_diff -= ssid_len_ori;
+
+			break;
+		}
+		case 2:
+			_rtw_memset(&ssid_ie[2], 0, ssid_len_ori);
+			break;
+		default:
+			break;
+		}
+	}
+
+	return len_diff;
+}
+
+static void rtw_hal_construct_P2PBeacon(_adapter *padapter, u8 *pframe, u32 *pLength)
+{
+	/* struct xmit_frame	*pmgntframe; */
+	/* struct pkt_attrib	*pattrib; */
+	/* unsigned char	*pframe; */
+	struct rtw_ieee80211_hdr *pwlanhdr;
+	unsigned short *fctrl;
+	unsigned int	rate_len;
+	struct xmit_priv	*pxmitpriv = &(padapter->xmitpriv);
+	u32	pktlen;
+	/* #if defined (CONFIG_AP_MODE) && defined (CONFIG_NATIVEAP_MLME) */
+	/*	_irqL irqL;
+	 *	struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
+	 * #endif */ /* #if defined (CONFIG_AP_MODE) && defined (CONFIG_NATIVEAP_MLME) */
+	struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
+	struct mlme_ext_priv	*pmlmeext = &(padapter->mlmeextpriv);
+	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
+	WLAN_BSSID_EX		*cur_network = &(pmlmeinfo->network);
+	u8	bc_addr[] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
+#ifdef CONFIG_P2P
+	struct wifidirect_info	*pwdinfo = &(padapter->wdinfo);
+#endif /* CONFIG_P2P */
+
+	/* for debug */
+	u8 *dbgbuf = pframe;
+	u8 dbgbufLen = 0, index = 0;
+
+	RTW_INFO("%s\n", __FUNCTION__);
+	/* #if defined (CONFIG_AP_MODE) && defined (CONFIG_NATIVEAP_MLME) */
+	/*	_enter_critical_bh(&pmlmepriv->bcn_update_lock, &irqL);
+	 * #endif */ /* #if defined (CONFIG_AP_MODE) && defined (CONFIG_NATIVEAP_MLME) */
+
+	pwlanhdr = (struct rtw_ieee80211_hdr *)pframe;
+
+
+	fctrl = &(pwlanhdr->frame_ctl);
+	*(fctrl) = 0;
+
+	_rtw_memcpy(pwlanhdr->addr1, bc_addr, ETH_ALEN);
+	_rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN);
+	_rtw_memcpy(pwlanhdr->addr3, get_my_bssid(cur_network), ETH_ALEN);
+
+	SetSeqNum(pwlanhdr, 0/*pmlmeext->mgnt_seq*/);
+	/* pmlmeext->mgnt_seq++; */
+	set_frame_sub_type(pframe, WIFI_BEACON);
+
+	pframe += sizeof(struct rtw_ieee80211_hdr_3addr);
+	pktlen = sizeof(struct rtw_ieee80211_hdr_3addr);
+
+	if ((pmlmeinfo->state & 0x03) == WIFI_FW_AP_STATE) {
+		/* RTW_INFO("ie len=%d\n", cur_network->IELength); */
+#ifdef CONFIG_P2P
+		/* for P2P : Primary Device Type & Device Name */
+		u32 wpsielen = 0, insert_len = 0;
+		u8 *wpsie = NULL;
+		wpsie = rtw_get_wps_ie(cur_network->IEs + _FIXED_IE_LENGTH_, cur_network->IELength - _FIXED_IE_LENGTH_, NULL, &wpsielen);
+
+		if (rtw_p2p_chk_role(pwdinfo, P2P_ROLE_GO) && wpsie && wpsielen > 0) {
+			uint wps_offset, remainder_ielen;
+			u8 *premainder_ie, *pframe_wscie;
+
+			wps_offset = (uint)(wpsie - cur_network->IEs);
+
+			premainder_ie = wpsie + wpsielen;
+
+			remainder_ielen = cur_network->IELength - wps_offset - wpsielen;
+
+#ifdef CONFIG_IOCTL_CFG80211
+			if (pwdinfo->driver_interface == DRIVER_CFG80211) {
+				if (pmlmepriv->wps_beacon_ie && pmlmepriv->wps_beacon_ie_len > 0) {
+					_rtw_memcpy(pframe, cur_network->IEs, wps_offset);
+					pframe += wps_offset;
+					pktlen += wps_offset;
+
+					_rtw_memcpy(pframe, pmlmepriv->wps_beacon_ie, pmlmepriv->wps_beacon_ie_len);
+					pframe += pmlmepriv->wps_beacon_ie_len;
+					pktlen += pmlmepriv->wps_beacon_ie_len;
+
+					/* copy remainder_ie to pframe */
+					_rtw_memcpy(pframe, premainder_ie, remainder_ielen);
+					pframe += remainder_ielen;
+					pktlen += remainder_ielen;
+				} else {
+					_rtw_memcpy(pframe, cur_network->IEs, cur_network->IELength);
+					pframe += cur_network->IELength;
+					pktlen += cur_network->IELength;
+				}
+			} else
+#endif /* CONFIG_IOCTL_CFG80211 */
+			{
+				pframe_wscie = pframe + wps_offset;
+				_rtw_memcpy(pframe, cur_network->IEs, wps_offset + wpsielen);
+				pframe += (wps_offset + wpsielen);
+				pktlen += (wps_offset + wpsielen);
+
+				/* now pframe is end of wsc ie, insert Primary Device Type & Device Name */
+				/*	Primary Device Type */
+				/*	Type: */
+				*(u16 *)(pframe + insert_len) = cpu_to_be16(WPS_ATTR_PRIMARY_DEV_TYPE);
+				insert_len += 2;
+
+				/*	Length: */
+				*(u16 *)(pframe + insert_len) = cpu_to_be16(0x0008);
+				insert_len += 2;
+
+				/*	Value: */
+				/*	Category ID */
+				*(u16 *)(pframe + insert_len) = cpu_to_be16(WPS_PDT_CID_MULIT_MEDIA);
+				insert_len += 2;
+
+				/*	OUI */
+				*(u32 *)(pframe + insert_len) = cpu_to_be32(WPSOUI);
+				insert_len += 4;
+
+				/*	Sub Category ID */
+				*(u16 *)(pframe + insert_len) = cpu_to_be16(WPS_PDT_SCID_MEDIA_SERVER);
+				insert_len += 2;
+
+
+				/*	Device Name */
+				/*	Type: */
+				*(u16 *)(pframe + insert_len) = cpu_to_be16(WPS_ATTR_DEVICE_NAME);
+				insert_len += 2;
+
+				/*	Length: */
+				*(u16 *)(pframe + insert_len) = cpu_to_be16(pwdinfo->device_name_len);
+				insert_len += 2;
+
+				/*	Value: */
+				_rtw_memcpy(pframe + insert_len, pwdinfo->device_name, pwdinfo->device_name_len);
+				insert_len += pwdinfo->device_name_len;
+
+
+				/* update wsc ie length */
+				*(pframe_wscie + 1) = (wpsielen - 2) + insert_len;
+
+				/* pframe move to end */
+				pframe += insert_len;
+				pktlen += insert_len;
+
+				/* copy remainder_ie to pframe */
+				_rtw_memcpy(pframe, premainder_ie, remainder_ielen);
+				pframe += remainder_ielen;
+				pktlen += remainder_ielen;
+			}
+		} else
+#endif /* CONFIG_P2P */
+		{
+			int len_diff;
+			_rtw_memcpy(pframe, cur_network->IEs, cur_network->IELength);
+			len_diff = update_hidden_ssid(
+					   pframe + _BEACON_IE_OFFSET_
+				   , cur_network->IELength - _BEACON_IE_OFFSET_
+					   , pmlmeinfo->hidden_ssid_mode
+				   );
+			pframe += (cur_network->IELength + len_diff);
+			pktlen += (cur_network->IELength + len_diff);
+		}
+#if 0
+		{
+			u8 *wps_ie;
+			uint wps_ielen;
+			u8 sr = 0;
+			wps_ie = rtw_get_wps_ie(pmgntframe->buf_addr + TXDESC_OFFSET + sizeof(struct rtw_ieee80211_hdr_3addr) + _BEACON_IE_OFFSET_,
+				pattrib->pktlen - sizeof(struct rtw_ieee80211_hdr_3addr) - _BEACON_IE_OFFSET_, NULL, &wps_ielen);
+			if (wps_ie && wps_ielen > 0)
+				rtw_get_wps_attr_content(wps_ie,  wps_ielen, WPS_ATTR_SELECTED_REGISTRAR, (u8 *)(&sr), NULL);
+			if (sr != 0)
+				set_fwstate(pmlmepriv, WIFI_UNDER_WPS);
+			else
+				_clr_fwstate_(pmlmepriv, WIFI_UNDER_WPS);
+		}
+#endif
+#ifdef CONFIG_P2P
+		if (rtw_p2p_chk_role(pwdinfo, P2P_ROLE_GO)) {
+			u32 len;
+#ifdef CONFIG_IOCTL_CFG80211
+			if (pwdinfo->driver_interface == DRIVER_CFG80211) {
+				len = pmlmepriv->p2p_beacon_ie_len;
+				if (pmlmepriv->p2p_beacon_ie && len > 0)
+					_rtw_memcpy(pframe, pmlmepriv->p2p_beacon_ie, len);
+			} else
+#endif /* CONFIG_IOCTL_CFG80211 */
+			{
+				len = build_beacon_p2p_ie(pwdinfo, pframe);
+			}
+
+			pframe += len;
+			pktlen += len;
+
+			#ifdef CONFIG_WFD
+			len = rtw_append_beacon_wfd_ie(padapter, pframe);
+			pframe += len;
+			pktlen += len;
+			#endif
+
+		}
+#endif /* CONFIG_P2P */
+
+		goto _issue_bcn;
+
+	}
+
+	/* below for ad-hoc mode */
+
+	/* timestamp will be inserted by hardware */
+	pframe += 8;
+	pktlen += 8;
+
+	/* beacon interval: 2 bytes */
+
+	_rtw_memcpy(pframe, (unsigned char *)(rtw_get_beacon_interval_from_ie(cur_network->IEs)), 2);
+
+	pframe += 2;
+	pktlen += 2;
+
+	/* capability info: 2 bytes */
+
+	_rtw_memcpy(pframe, (unsigned char *)(rtw_get_capability_from_ie(cur_network->IEs)), 2);
+
+	pframe += 2;
+	pktlen += 2;
+
+	/* SSID */
+	pframe = rtw_set_ie(pframe, _SSID_IE_, cur_network->Ssid.SsidLength, cur_network->Ssid.Ssid, &pktlen);
+
+	/* supported rates... */
+	rate_len = rtw_get_rateset_len(cur_network->SupportedRates);
+	pframe = rtw_set_ie(pframe, _SUPPORTEDRATES_IE_, ((rate_len > 8) ? 8 : rate_len), cur_network->SupportedRates, &pktlen);
+
+	/* DS parameter set */
+	pframe = rtw_set_ie(pframe, _DSSET_IE_, 1, (unsigned char *)&(cur_network->Configuration.DSConfig), &pktlen);
+
+	/* if( (pmlmeinfo->state&0x03) == WIFI_FW_ADHOC_STATE) */
+	{
+		u8 erpinfo = 0;
+		u32 ATIMWindow;
+		/* IBSS Parameter Set... */
+		/* ATIMWindow = cur->Configuration.ATIMWindow; */
+		ATIMWindow = 0;
+		pframe = rtw_set_ie(pframe, _IBSS_PARA_IE_, 2, (unsigned char *)(&ATIMWindow), &pktlen);
+
+		/* ERP IE */
+		pframe = rtw_set_ie(pframe, _ERPINFO_IE_, 1, &erpinfo, &pktlen);
+	}
+
+
+	/* EXTERNDED SUPPORTED RATE */
+	if (rate_len > 8)
+		pframe = rtw_set_ie(pframe, _EXT_SUPPORTEDRATES_IE_, (rate_len - 8), (cur_network->SupportedRates + 8), &pktlen);
+
+
+	/* todo:HT for adhoc */
+
+_issue_bcn:
+
+	/* #if defined (CONFIG_AP_MODE) && defined (CONFIG_NATIVEAP_MLME) */
+	/*	pmlmepriv->update_bcn = _FALSE;
+	 *
+	 *	_exit_critical_bh(&pmlmepriv->bcn_update_lock, &irqL);
+	 * #endif */ /* #if defined (CONFIG_AP_MODE) && defined (CONFIG_NATIVEAP_MLME) */
+
+	*pLength = pktlen;
+#if 0
+	/* printf dbg msg */
+	dbgbufLen = pktlen;
+	RTW_INFO("======> DBG MSG FOR CONSTRAUCT P2P BEACON\n");
+
+	for (index = 0; index < dbgbufLen; index++)
+		printk("%x ", *(dbgbuf + index));
+
+	printk("\n");
+	RTW_INFO("<====== DBG MSG FOR CONSTRAUCT P2P BEACON\n");
+
+#endif
+}
+
+static void rtw_hal_construct_P2PProbeRsp(_adapter *padapter, u8 *pframe, u32 *pLength)
+{
+	/* struct xmit_frame			*pmgntframe; */
+	/* struct pkt_attrib			*pattrib; */
+	/* unsigned char					*pframe; */
+	struct rtw_ieee80211_hdr	*pwlanhdr;
+	unsigned short				*fctrl;
+	unsigned char					*mac;
+	struct xmit_priv	*pxmitpriv = &(padapter->xmitpriv);
+	struct mlme_ext_priv	*pmlmeext = &(padapter->mlmeextpriv);
+	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
+	struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
+	/* WLAN_BSSID_EX 		*cur_network = &(pmlmeinfo->network); */
+	u16					beacon_interval = 100;
+	u16					capInfo = 0;
+	struct wifidirect_info	*pwdinfo = &(padapter->wdinfo);
+	u8					wpsie[255] = { 0x00 };
+	u32					wpsielen = 0, p2pielen = 0;
+	u32					pktlen;
+#ifdef CONFIG_WFD
+	u32					wfdielen = 0;
+#endif
+#ifdef CONFIG_INTEL_WIDI
+	u8 zero_array_check[L2SDTA_SERVICE_VE_LEN] = { 0x00 };
+#endif /* CONFIG_INTEL_WIDI */
+
+	/* for debug */
+	u8 *dbgbuf = pframe;
+	u8 dbgbufLen = 0, index = 0;
+
+	RTW_INFO("%s\n", __FUNCTION__);
+	pwlanhdr = (struct rtw_ieee80211_hdr *)pframe;
+
+	mac = adapter_mac_addr(padapter);
+
+	fctrl = &(pwlanhdr->frame_ctl);
+	*(fctrl) = 0;
+
+	/* DA filled by FW */
+	_rtw_memset(pwlanhdr->addr1, 0, ETH_ALEN);
+	_rtw_memcpy(pwlanhdr->addr2, mac, ETH_ALEN);
+
+	/*	Use the device address for BSSID field.	 */
+	_rtw_memcpy(pwlanhdr->addr3, mac, ETH_ALEN);
+
+	SetSeqNum(pwlanhdr, 0);
+	set_frame_sub_type(fctrl, WIFI_PROBERSP);
+
+	pktlen = sizeof(struct rtw_ieee80211_hdr_3addr);
+	pframe += pktlen;
+
+
+	/* timestamp will be inserted by hardware */
+	pframe += 8;
+	pktlen += 8;
+
+	/* beacon interval: 2 bytes */
+	_rtw_memcpy(pframe, (unsigned char *) &beacon_interval, 2);
+	pframe += 2;
+	pktlen += 2;
+
+	/*	capability info: 2 bytes */
+	/*	ESS and IBSS bits must be 0 (defined in the 3.1.2.1.1 of WiFi Direct Spec) */
+	capInfo |= cap_ShortPremble;
+	capInfo |= cap_ShortSlot;
+
+	_rtw_memcpy(pframe, (unsigned char *) &capInfo, 2);
+	pframe += 2;
+	pktlen += 2;
+
+
+	/* SSID */
+	pframe = rtw_set_ie(pframe, _SSID_IE_, 7, pwdinfo->p2p_wildcard_ssid, &pktlen);
+
+	/* supported rates... */
+	/*	Use the OFDM rate in the P2P probe response frame. ( 6(B), 9(B), 12, 18, 24, 36, 48, 54 ) */
+	pframe = rtw_set_ie(pframe, _SUPPORTEDRATES_IE_, 8, pwdinfo->support_rate, &pktlen);
+
+	/* DS parameter set */
+	pframe = rtw_set_ie(pframe, _DSSET_IE_, 1, (unsigned char *)&pwdinfo->listen_channel, &pktlen);
+
+#ifdef CONFIG_IOCTL_CFG80211
+	if (pwdinfo->driver_interface == DRIVER_CFG80211) {
+		if (pmlmepriv->wps_probe_resp_ie != NULL && pmlmepriv->p2p_probe_resp_ie != NULL) {
+			/* WPS IE */
+			_rtw_memcpy(pframe, pmlmepriv->wps_probe_resp_ie, pmlmepriv->wps_probe_resp_ie_len);
+			pktlen += pmlmepriv->wps_probe_resp_ie_len;
+			pframe += pmlmepriv->wps_probe_resp_ie_len;
+
+			/* P2P IE */
+			_rtw_memcpy(pframe, pmlmepriv->p2p_probe_resp_ie, pmlmepriv->p2p_probe_resp_ie_len);
+			pktlen += pmlmepriv->p2p_probe_resp_ie_len;
+			pframe += pmlmepriv->p2p_probe_resp_ie_len;
+		}
+	} else
+#endif /* CONFIG_IOCTL_CFG80211		 */
+	{
+
+		/*	Todo: WPS IE */
+		/*	Noted by Albert 20100907 */
+		/*	According to the WPS specification, all the WPS attribute is presented by Big Endian. */
+
+		wpsielen = 0;
+		/*	WPS OUI */
+		*(u32 *)(wpsie) = cpu_to_be32(WPSOUI);
+		wpsielen += 4;
+
+		/*	WPS version */
+		/*	Type: */
+		*(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_ATTR_VER1);
+		wpsielen += 2;
+
+		/*	Length: */
+		*(u16 *)(wpsie + wpsielen) = cpu_to_be16(0x0001);
+		wpsielen += 2;
+
+		/*	Value: */
+		wpsie[wpsielen++] = WPS_VERSION_1;	/*	Version 1.0 */
+
+#ifdef CONFIG_INTEL_WIDI
+		/*	Commented by Kurt */
+		/*	Appended WiDi info. only if we did issued_probereq_widi(), and then we saved ven. ext. in pmlmepriv->sa_ext. */
+		if (_rtw_memcmp(pmlmepriv->sa_ext, zero_array_check, L2SDTA_SERVICE_VE_LEN) == _FALSE
+		    || pmlmepriv->num_p2p_sdt != 0) {
+			/* Sec dev type */
+			*(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_ATTR_SEC_DEV_TYPE_LIST);
+			wpsielen += 2;
+
+			/*	Length: */
+			*(u16 *)(wpsie + wpsielen) = cpu_to_be16(0x0008);
+			wpsielen += 2;
+
+			/*	Value: */
+			/*	Category ID */
+			*(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_PDT_CID_DISPLAYS);
+			wpsielen += 2;
+
+			/*	OUI */
+			*(u32 *)(wpsie + wpsielen) = cpu_to_be32(INTEL_DEV_TYPE_OUI);
+			wpsielen += 4;
+
+			*(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_PDT_SCID_WIDI_CONSUMER_SINK);
+			wpsielen += 2;
+
+			if (_rtw_memcmp(pmlmepriv->sa_ext, zero_array_check, L2SDTA_SERVICE_VE_LEN) == _FALSE) {
+				/*	Vendor Extension */
+				_rtw_memcpy(wpsie + wpsielen, pmlmepriv->sa_ext, L2SDTA_SERVICE_VE_LEN);
+				wpsielen += L2SDTA_SERVICE_VE_LEN;
+			}
+		}
+#endif /* CONFIG_INTEL_WIDI */
+
+		/*	WiFi Simple Config State */
+		/*	Type: */
+		*(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_ATTR_SIMPLE_CONF_STATE);
+		wpsielen += 2;
+
+		/*	Length: */
+		*(u16 *)(wpsie + wpsielen) = cpu_to_be16(0x0001);
+		wpsielen += 2;
+
+		/*	Value: */
+		wpsie[wpsielen++] = WPS_WSC_STATE_NOT_CONFIG;	/*	Not Configured. */
+
+		/*	Response Type */
+		/*	Type: */
+		*(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_ATTR_RESP_TYPE);
+		wpsielen += 2;
+
+		/*	Length: */
+		*(u16 *)(wpsie + wpsielen) = cpu_to_be16(0x0001);
+		wpsielen += 2;
+
+		/*	Value: */
+		wpsie[wpsielen++] = WPS_RESPONSE_TYPE_8021X;
+
+		/*	UUID-E */
+		/*	Type: */
+		*(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_ATTR_UUID_E);
+		wpsielen += 2;
+
+		/*	Length: */
+		*(u16 *)(wpsie + wpsielen) = cpu_to_be16(0x0010);
+		wpsielen += 2;
+
+		/*	Value: */
+		if (pwdinfo->external_uuid == 0) {
+			_rtw_memset(wpsie + wpsielen, 0x0, 16);
+			_rtw_memcpy(wpsie + wpsielen, mac, ETH_ALEN);
+		} else
+			_rtw_memcpy(wpsie + wpsielen, pwdinfo->uuid, 0x10);
+		wpsielen += 0x10;
+
+		/*	Manufacturer */
+		/*	Type: */
+		*(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_ATTR_MANUFACTURER);
+		wpsielen += 2;
+
+		/*	Length: */
+		*(u16 *)(wpsie + wpsielen) = cpu_to_be16(0x0007);
+		wpsielen += 2;
+
+		/*	Value: */
+		_rtw_memcpy(wpsie + wpsielen, "Realtek", 7);
+		wpsielen += 7;
+
+		/*	Model Name */
+		/*	Type: */
+		*(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_ATTR_MODEL_NAME);
+		wpsielen += 2;
+
+		/*	Length: */
+		*(u16 *)(wpsie + wpsielen) = cpu_to_be16(0x0006);
+		wpsielen += 2;
+
+		/*	Value: */
+		_rtw_memcpy(wpsie + wpsielen, "8192CU", 6);
+		wpsielen += 6;
+
+		/*	Model Number */
+		/*	Type: */
+		*(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_ATTR_MODEL_NUMBER);
+		wpsielen += 2;
+
+		/*	Length: */
+		*(u16 *)(wpsie + wpsielen) = cpu_to_be16(0x0001);
+		wpsielen += 2;
+
+		/*	Value: */
+		wpsie[wpsielen++] = 0x31;		/*	character 1 */
+
+		/*	Serial Number */
+		/*	Type: */
+		*(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_ATTR_SERIAL_NUMBER);
+		wpsielen += 2;
+
+		/*	Length: */
+		*(u16 *)(wpsie + wpsielen) = cpu_to_be16(ETH_ALEN);
+		wpsielen += 2;
+
+		/*	Value: */
+		_rtw_memcpy(wpsie + wpsielen, "123456" , ETH_ALEN);
+		wpsielen += ETH_ALEN;
+
+		/*	Primary Device Type */
+		/*	Type: */
+		*(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_ATTR_PRIMARY_DEV_TYPE);
+		wpsielen += 2;
+
+		/*	Length: */
+		*(u16 *)(wpsie + wpsielen) = cpu_to_be16(0x0008);
+		wpsielen += 2;
+
+		/*	Value: */
+		/*	Category ID */
+		*(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_PDT_CID_MULIT_MEDIA);
+		wpsielen += 2;
+
+		/*	OUI */
+		*(u32 *)(wpsie + wpsielen) = cpu_to_be32(WPSOUI);
+		wpsielen += 4;
+
+		/*	Sub Category ID */
+		*(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_PDT_SCID_MEDIA_SERVER);
+		wpsielen += 2;
+
+		/*	Device Name */
+		/*	Type: */
+		*(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_ATTR_DEVICE_NAME);
+		wpsielen += 2;
+
+		/*	Length: */
+		*(u16 *)(wpsie + wpsielen) = cpu_to_be16(pwdinfo->device_name_len);
+		wpsielen += 2;
+
+		/*	Value: */
+		_rtw_memcpy(wpsie + wpsielen, pwdinfo->device_name, pwdinfo->device_name_len);
+		wpsielen += pwdinfo->device_name_len;
+
+		/*	Config Method */
+		/*	Type: */
+		*(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_ATTR_CONF_METHOD);
+		wpsielen += 2;
+
+		/*	Length: */
+		*(u16 *)(wpsie + wpsielen) = cpu_to_be16(0x0002);
+		wpsielen += 2;
+
+		/*	Value: */
+		*(u16 *)(wpsie + wpsielen) = cpu_to_be16(pwdinfo->supported_wps_cm);
+		wpsielen += 2;
+
+
+		pframe = rtw_set_ie(pframe, _VENDOR_SPECIFIC_IE_, wpsielen, (unsigned char *) wpsie, &pktlen);
+
+
+		p2pielen = build_probe_resp_p2p_ie(pwdinfo, pframe);
+		pframe += p2pielen;
+		pktlen += p2pielen;
+	}
+
+#ifdef CONFIG_WFD
+	wfdielen = rtw_append_probe_resp_wfd_ie(padapter, pframe);
+	pframe += wfdielen;
+	pktlen += wfdielen;
+#endif
+
+	*pLength = pktlen;
+
+#if 0
+	/* printf dbg msg */
+	dbgbufLen = pktlen;
+	RTW_INFO("======> DBG MSG FOR CONSTRAUCT P2P Probe Rsp\n");
+
+	for (index = 0; index < dbgbufLen; index++)
+		printk("%x ", *(dbgbuf + index));
+
+	printk("\n");
+	RTW_INFO("<====== DBG MSG FOR CONSTRAUCT P2P Probe Rsp\n");
+#endif
+}
+static void rtw_hal_construct_P2PNegoRsp(_adapter *padapter, u8 *pframe, u32 *pLength)
+{
+	struct p2p_channels *ch_list = &(adapter_to_rfctl(padapter)->channel_list);
+	unsigned char category = RTW_WLAN_CATEGORY_PUBLIC;
+	u8			action = P2P_PUB_ACTION_ACTION;
+	u32			p2poui = cpu_to_be32(P2POUI);
+	u8			oui_subtype = P2P_GO_NEGO_RESP;
+	u8			wpsie[255] = { 0x00 }, p2pie[255] = { 0x00 };
+	u8			p2pielen = 0, i;
+	uint			wpsielen = 0;
+	u16			wps_devicepassword_id = 0x0000;
+	uint			wps_devicepassword_id_len = 0;
+	u8			channel_cnt_24g = 0, channel_cnt_5gl = 0, channel_cnt_5gh;
+	u16			len_channellist_attr = 0;
+	u32			pktlen;
+	u8			dialogToken = 0;
+
+	/* struct xmit_frame			*pmgntframe; */
+	/* struct pkt_attrib			*pattrib; */
+	/* unsigned char					*pframe; */
+	struct rtw_ieee80211_hdr	*pwlanhdr;
+	unsigned short				*fctrl;
+	struct xmit_priv			*pxmitpriv = &(padapter->xmitpriv);
+	struct mlme_ext_priv	*pmlmeext = &(padapter->mlmeextpriv);
+	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
+	struct wifidirect_info	*pwdinfo = &(padapter->wdinfo);
+	/* WLAN_BSSID_EX 		*cur_network = &(pmlmeinfo->network); */
+
+#ifdef CONFIG_WFD
+	u32					wfdielen = 0;
+#endif
+
+	/* for debug */
+	u8 *dbgbuf = pframe;
+	u8 dbgbufLen = 0, index = 0;
+
+	RTW_INFO("%s\n", __FUNCTION__);
+	pwlanhdr = (struct rtw_ieee80211_hdr *)pframe;
+
+	fctrl = &(pwlanhdr->frame_ctl);
+	*(fctrl) = 0;
+
+	/* RA, filled by FW */
+	_rtw_memset(pwlanhdr->addr1, 0, ETH_ALEN);
+	_rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN);
+	_rtw_memcpy(pwlanhdr->addr3, adapter_mac_addr(padapter), ETH_ALEN);
+
+	SetSeqNum(pwlanhdr, 0);
+	set_frame_sub_type(pframe, WIFI_ACTION);
+
+	pktlen = sizeof(struct rtw_ieee80211_hdr_3addr);
+	pframe += pktlen;
+
+	pframe = rtw_set_fixed_ie(pframe, 1, &(category), &(pktlen));
+	pframe = rtw_set_fixed_ie(pframe, 1, &(action), &(pktlen));
+	pframe = rtw_set_fixed_ie(pframe, 4, (unsigned char *) &(p2poui), &(pktlen));
+	pframe = rtw_set_fixed_ie(pframe, 1, &(oui_subtype), &(pktlen));
+
+	/* dialog token, filled by FW */
+	pframe = rtw_set_fixed_ie(pframe, 1, &(dialogToken), &(pktlen));
+
+	_rtw_memset(wpsie, 0x00, 255);
+	wpsielen = 0;
+
+	/*	WPS Section */
+	wpsielen = 0;
+	/*	WPS OUI */
+	*(u32 *)(wpsie) = cpu_to_be32(WPSOUI);
+	wpsielen += 4;
+
+	/*	WPS version */
+	/*	Type: */
+	*(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_ATTR_VER1);
+	wpsielen += 2;
+
+	/*	Length: */
+	*(u16 *)(wpsie + wpsielen) = cpu_to_be16(0x0001);
+	wpsielen += 2;
+
+	/*	Value: */
+	wpsie[wpsielen++] = WPS_VERSION_1;	/*	Version 1.0 */
+
+	/*	Device Password ID */
+	/*	Type: */
+	*(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_ATTR_DEVICE_PWID);
+	wpsielen += 2;
+
+	/*	Length: */
+	*(u16 *)(wpsie + wpsielen) = cpu_to_be16(0x0002);
+	wpsielen += 2;
+
+	/*	Value: */
+	if (wps_devicepassword_id == WPS_DPID_USER_SPEC)
+		*(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_DPID_REGISTRAR_SPEC);
+	else if (wps_devicepassword_id == WPS_DPID_REGISTRAR_SPEC)
+		*(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_DPID_USER_SPEC);
+	else
+		*(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_DPID_PBC);
+	wpsielen += 2;
+
+	pframe = rtw_set_ie(pframe, _VENDOR_SPECIFIC_IE_, wpsielen, (unsigned char *) wpsie, &pktlen);
+
+
+	/*	P2P IE Section. */
+
+	/*	P2P OUI */
+	p2pielen = 0;
+	p2pie[p2pielen++] = 0x50;
+	p2pie[p2pielen++] = 0x6F;
+	p2pie[p2pielen++] = 0x9A;
+	p2pie[p2pielen++] = 0x09;	/*	WFA P2P v1.0 */
+
+	/*	Commented by Albert 20100908 */
+	/*	According to the P2P Specification, the group negoitation response frame should contain 9 P2P attributes */
+	/*	1. Status */
+	/*	2. P2P Capability */
+	/*	3. Group Owner Intent */
+	/*	4. Configuration Timeout */
+	/*	5. Operating Channel */
+	/*	6. Intended P2P Interface Address */
+	/*	7. Channel List */
+	/*	8. Device Info */
+	/*	9. Group ID	( Only GO ) */
+
+
+	/*	ToDo: */
+
+	/*	P2P Status */
+	/*	Type: */
+	p2pie[p2pielen++] = P2P_ATTR_STATUS;
+
+	/*	Length: */
+	*(u16 *)(p2pie + p2pielen) = cpu_to_le16(0x0001);
+	p2pielen += 2;
+
+	/*	Value, filled by FW */
+	p2pie[p2pielen++] = 1;
+
+	/*	P2P Capability */
+	/*	Type: */
+	p2pie[p2pielen++] = P2P_ATTR_CAPABILITY;
+
+	/*	Length: */
+	*(u16 *)(p2pie + p2pielen) = cpu_to_le16(0x0002);
+	p2pielen += 2;
+
+	/*	Value: */
+	/*	Device Capability Bitmap, 1 byte */
+
+	if (rtw_p2p_chk_role(pwdinfo, P2P_ROLE_CLIENT)) {
+		/*	Commented by Albert 2011/03/08 */
+		/*	According to the P2P specification */
+		/*	if the sending device will be client, the P2P Capability should be reserved of group negotation response frame */
+		p2pie[p2pielen++] = 0;
+	} else {
+		/*	Be group owner or meet the error case */
+		p2pie[p2pielen++] = DMP_P2P_DEVCAP_SUPPORT;
+	}
+
+	/*	Group Capability Bitmap, 1 byte */
+	if (pwdinfo->persistent_supported)
+		p2pie[p2pielen++] = P2P_GRPCAP_CROSS_CONN | P2P_GRPCAP_PERSISTENT_GROUP;
+	else
+		p2pie[p2pielen++] = P2P_GRPCAP_CROSS_CONN;
+
+	/*	Group Owner Intent */
+	/*	Type: */
+	p2pie[p2pielen++] = P2P_ATTR_GO_INTENT;
+
+	/*	Length: */
+	*(u16 *)(p2pie + p2pielen) = cpu_to_le16(0x0001);
+	p2pielen += 2;
+
+	/*	Value: */
+	if (pwdinfo->peer_intent & 0x01) {
+		/*	Peer's tie breaker bit is 1, our tie breaker bit should be 0 */
+		p2pie[p2pielen++] = (pwdinfo->intent << 1);
+	} else {
+		/*	Peer's tie breaker bit is 0, our tie breaker bit should be 1 */
+		p2pie[p2pielen++] = ((pwdinfo->intent << 1) | BIT(0));
+	}
+
+
+	/*	Configuration Timeout */
+	/*	Type: */
+	p2pie[p2pielen++] = P2P_ATTR_CONF_TIMEOUT;
+
+	/*	Length: */
+	*(u16 *)(p2pie + p2pielen) = cpu_to_le16(0x0002);
+	p2pielen += 2;
+
+	/*	Value: */
+	p2pie[p2pielen++] = 200;	/*	2 seconds needed to be the P2P GO */
+	p2pie[p2pielen++] = 200;	/*	2 seconds needed to be the P2P Client */
+
+	/*	Operating Channel */
+	/*	Type: */
+	p2pie[p2pielen++] = P2P_ATTR_OPERATING_CH;
+
+	/*	Length: */
+	*(u16 *)(p2pie + p2pielen) = cpu_to_le16(0x0005);
+	p2pielen += 2;
+
+	/*	Value: */
+	/*	Country String */
+	p2pie[p2pielen++] = 'X';
+	p2pie[p2pielen++] = 'X';
+
+	/*	The third byte should be set to 0x04. */
+	/*	Described in the "Operating Channel Attribute" section. */
+	p2pie[p2pielen++] = 0x04;
+
+	/*	Operating Class */
+	if (pwdinfo->operating_channel <= 14) {
+		/*	Operating Class */
+		p2pie[p2pielen++] = 0x51;
+	} else if ((pwdinfo->operating_channel >= 36) && (pwdinfo->operating_channel <= 48)) {
+		/*	Operating Class */
+		p2pie[p2pielen++] = 0x73;
+	} else {
+		/*	Operating Class */
+		p2pie[p2pielen++] = 0x7c;
+	}
+
+	/*	Channel Number */
+	p2pie[p2pielen++] = pwdinfo->operating_channel;	/*	operating channel number */
+
+	/*	Intended P2P Interface Address	 */
+	/*	Type: */
+	p2pie[p2pielen++] = P2P_ATTR_INTENDED_IF_ADDR;
+
+	/*	Length: */
+	*(u16 *)(p2pie + p2pielen) = cpu_to_le16(ETH_ALEN);
+	p2pielen += 2;
+
+	/*	Value: */
+	_rtw_memcpy(p2pie + p2pielen, adapter_mac_addr(padapter), ETH_ALEN);
+	p2pielen += ETH_ALEN;
+
+	/*	Channel List */
+	/*	Type: */
+	p2pie[p2pielen++] = P2P_ATTR_CH_LIST;
+
+	/* Country String(3) */
+	/* + ( Operating Class (1) + Number of Channels(1) ) * Operation Classes (?) */
+	/* + number of channels in all classes */
+	len_channellist_attr = 3
+		       + (1 + 1) * (u16)ch_list->reg_classes
+		       + get_reg_classes_full_count(ch_list);
+
+#ifdef CONFIG_CONCURRENT_MODE
+	if (rtw_mi_buddy_check_fwstate(padapter, _FW_LINKED))
+		*(u16 *)(p2pie + p2pielen) = cpu_to_le16(5 + 1);
+	else
+		*(u16 *)(p2pie + p2pielen) = cpu_to_le16(len_channellist_attr);
+
+#else
+
+	*(u16 *)(p2pie + p2pielen) = cpu_to_le16(len_channellist_attr);
+
+#endif
+	p2pielen += 2;
+
+	/*	Value: */
+	/*	Country String */
+	p2pie[p2pielen++] = 'X';
+	p2pie[p2pielen++] = 'X';
+
+	/*	The third byte should be set to 0x04. */
+	/*	Described in the "Operating Channel Attribute" section. */
+	p2pie[p2pielen++] = 0x04;
+
+	/*	Channel Entry List */
+
+#ifdef CONFIG_CONCURRENT_MODE
+	if (rtw_mi_check_status(padapter, MI_LINKED)) {
+		u8 union_ch = rtw_mi_get_union_chan(padapter);
+
+		/*	Operating Class */
+		if (union_ch > 14) {
+			if (union_ch >= 149)
+				p2pie[p2pielen++] = 0x7c;
+			else
+				p2pie[p2pielen++] = 0x73;
+		} else
+			p2pie[p2pielen++] = 0x51;
+
+
+		/*	Number of Channels */
+		/*	Just support 1 channel and this channel is AP's channel */
+		p2pie[p2pielen++] = 1;
+
+		/*	Channel List */
+		p2pie[p2pielen++] = union_ch;
+	} else
+#endif /* CONFIG_CONCURRENT_MODE */
+	{
+		int i, j;
+		for (j = 0; j < ch_list->reg_classes; j++) {
+			/*	Operating Class */
+			p2pie[p2pielen++] = ch_list->reg_class[j].reg_class;
+
+			/*	Number of Channels */
+			p2pie[p2pielen++] = ch_list->reg_class[j].channels;
+
+			/*	Channel List */
+			for (i = 0; i < ch_list->reg_class[j].channels; i++)
+				p2pie[p2pielen++] = ch_list->reg_class[j].channel[i];
+		}
+	}
+
+	/*	Device Info */
+	/*	Type: */
+	p2pie[p2pielen++] = P2P_ATTR_DEVICE_INFO;
+
+	/*	Length: */
+	/*	21->P2P Device Address (6bytes) + Config Methods (2bytes) + Primary Device Type (8bytes)  */
+	/*	+ NumofSecondDevType (1byte) + WPS Device Name ID field (2bytes) + WPS Device Name Len field (2bytes) */
+	*(u16 *)(p2pie + p2pielen) = cpu_to_le16(21 + pwdinfo->device_name_len);
+	p2pielen += 2;
+
+	/*	Value: */
+	/*	P2P Device Address */
+	_rtw_memcpy(p2pie + p2pielen, adapter_mac_addr(padapter), ETH_ALEN);
+	p2pielen += ETH_ALEN;
+
+	/*	Config Method */
+	/*	This field should be big endian. Noted by P2P specification. */
+
+	*(u16 *)(p2pie + p2pielen) = cpu_to_be16(pwdinfo->supported_wps_cm);
+
+	p2pielen += 2;
+
+	/*	Primary Device Type */
+	/*	Category ID */
+	*(u16 *)(p2pie + p2pielen) = cpu_to_be16(WPS_PDT_CID_MULIT_MEDIA);
+	p2pielen += 2;
+
+	/*	OUI */
+	*(u32 *)(p2pie + p2pielen) = cpu_to_be32(WPSOUI);
+	p2pielen += 4;
+
+	/*	Sub Category ID */
+	*(u16 *)(p2pie + p2pielen) = cpu_to_be16(WPS_PDT_SCID_MEDIA_SERVER);
+	p2pielen += 2;
+
+	/*	Number of Secondary Device Types */
+	p2pie[p2pielen++] = 0x00;	/*	No Secondary Device Type List */
+
+	/*	Device Name */
+	/*	Type: */
+	*(u16 *)(p2pie + p2pielen) = cpu_to_be16(WPS_ATTR_DEVICE_NAME);
+	p2pielen += 2;
+
+	/*	Length: */
+	*(u16 *)(p2pie + p2pielen) = cpu_to_be16(pwdinfo->device_name_len);
+	p2pielen += 2;
+
+	/*	Value: */
+	_rtw_memcpy(p2pie + p2pielen, pwdinfo->device_name , pwdinfo->device_name_len);
+	p2pielen += pwdinfo->device_name_len;
+
+	if (rtw_p2p_chk_role(pwdinfo, P2P_ROLE_GO)) {
+		/*	Group ID Attribute */
+		/*	Type: */
+		p2pie[p2pielen++] = P2P_ATTR_GROUP_ID;
+
+		/*	Length: */
+		*(u16 *)(p2pie + p2pielen) = cpu_to_le16(ETH_ALEN + pwdinfo->nego_ssidlen);
+		p2pielen += 2;
+
+		/*	Value: */
+		/*	p2P Device Address */
+		_rtw_memcpy(p2pie + p2pielen , pwdinfo->device_addr, ETH_ALEN);
+		p2pielen += ETH_ALEN;
+
+		/*	SSID */
+		_rtw_memcpy(p2pie + p2pielen, pwdinfo->nego_ssid, pwdinfo->nego_ssidlen);
+		p2pielen += pwdinfo->nego_ssidlen;
+
+	}
+
+	pframe = rtw_set_ie(pframe, _VENDOR_SPECIFIC_IE_, p2pielen, (unsigned char *) p2pie, &pktlen);
+
+#ifdef CONFIG_WFD
+	wfdielen = build_nego_resp_wfd_ie(pwdinfo, pframe);
+	pframe += wfdielen;
+	pktlen += wfdielen;
+#endif
+
+	*pLength = pktlen;
+#if 0
+	/* printf dbg msg */
+	dbgbufLen = pktlen;
+	RTW_INFO("======> DBG MSG FOR CONSTRAUCT Nego Rsp\n");
+
+	for (index = 0; index < dbgbufLen; index++)
+		printk("%x ", *(dbgbuf + index));
+
+	printk("\n");
+	RTW_INFO("<====== DBG MSG FOR CONSTRAUCT Nego Rsp\n");
+#endif
+}
+
+static void rtw_hal_construct_P2PInviteRsp(_adapter *padapter, u8 *pframe, u32 *pLength)
+{
+	unsigned char category = RTW_WLAN_CATEGORY_PUBLIC;
+	u8			action = P2P_PUB_ACTION_ACTION;
+	u32			p2poui = cpu_to_be32(P2POUI);
+	u8			oui_subtype = P2P_INVIT_RESP;
+	u8			p2pie[255] = { 0x00 };
+	u8			p2pielen = 0, i;
+	u8			channel_cnt_24g = 0, channel_cnt_5gl = 0, channel_cnt_5gh = 0;
+	u16			len_channellist_attr = 0;
+	u32			pktlen;
+	u8			dialogToken = 0;
+#ifdef CONFIG_WFD
+	u32					wfdielen = 0;
+#endif
+
+	/* struct xmit_frame			*pmgntframe; */
+	/* struct pkt_attrib			*pattrib; */
+	/* unsigned char					*pframe; */
+	struct rtw_ieee80211_hdr	*pwlanhdr;
+	unsigned short				*fctrl;
+	struct xmit_priv			*pxmitpriv = &(padapter->xmitpriv);
+	struct mlme_ext_priv	*pmlmeext = &(padapter->mlmeextpriv);
+	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
+	struct wifidirect_info	*pwdinfo = &(padapter->wdinfo);
+
+	/* for debug */
+	u8 *dbgbuf = pframe;
+	u8 dbgbufLen = 0, index = 0;
+
+
+	RTW_INFO("%s\n", __FUNCTION__);
+	pwlanhdr = (struct rtw_ieee80211_hdr *)pframe;
+
+	fctrl = &(pwlanhdr->frame_ctl);
+	*(fctrl) = 0;
+
+	/* RA fill by FW */
+	_rtw_memset(pwlanhdr->addr1, 0, ETH_ALEN);
+	_rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN);
+
+	/* BSSID fill by FW */
+	_rtw_memset(pwlanhdr->addr3, 0, ETH_ALEN);
+
+	SetSeqNum(pwlanhdr, 0);
+	set_frame_sub_type(pframe, WIFI_ACTION);
+
+	pframe += sizeof(struct rtw_ieee80211_hdr_3addr);
+	pktlen = sizeof(struct rtw_ieee80211_hdr_3addr);
+
+	pframe = rtw_set_fixed_ie(pframe, 1, &(category), &(pktlen));
+	pframe = rtw_set_fixed_ie(pframe, 1, &(action), &(pktlen));
+	pframe = rtw_set_fixed_ie(pframe, 4, (unsigned char *) &(p2poui), &(pktlen));
+	pframe = rtw_set_fixed_ie(pframe, 1, &(oui_subtype), &(pktlen));
+
+	/* dialog token, filled by FW */
+	pframe = rtw_set_fixed_ie(pframe, 1, &(dialogToken), &(pktlen));
+
+	/*	P2P IE Section. */
+
+	/*	P2P OUI */
+	p2pielen = 0;
+	p2pie[p2pielen++] = 0x50;
+	p2pie[p2pielen++] = 0x6F;
+	p2pie[p2pielen++] = 0x9A;
+	p2pie[p2pielen++] = 0x09;	/*	WFA P2P v1.0 */
+
+	/*	Commented by Albert 20101005 */
+	/*	According to the P2P Specification, the P2P Invitation response frame should contain 5 P2P attributes */
+	/*	1. Status */
+	/*	2. Configuration Timeout */
+	/*	3. Operating Channel	( Only GO ) */
+	/*	4. P2P Group BSSID	( Only GO ) */
+	/*	5. Channel List */
+
+	/*	P2P Status */
+	/*	Type: */
+	p2pie[p2pielen++] = P2P_ATTR_STATUS;
+
+	/*	Length: */
+	*(u16 *)(p2pie + p2pielen) = cpu_to_le16(0x0001);
+	p2pielen += 2;
+
+	/*	Value: filled by FW, defult value is FAIL INFO UNAVAILABLE */
+	p2pie[p2pielen++] = P2P_STATUS_FAIL_INFO_UNAVAILABLE;
+
+	/*	Configuration Timeout */
+	/*	Type: */
+	p2pie[p2pielen++] = P2P_ATTR_CONF_TIMEOUT;
+
+	/*	Length: */
+	*(u16 *)(p2pie + p2pielen) = cpu_to_le16(0x0002);
+	p2pielen += 2;
+
+	/*	Value: */
+	p2pie[p2pielen++] = 200;	/*	2 seconds needed to be the P2P GO */
+	p2pie[p2pielen++] = 200;	/*	2 seconds needed to be the P2P Client */
+
+	/* due to defult value is FAIL INFO UNAVAILABLE, so the following IE is not needed */
+#if 0
+	if (status_code == P2P_STATUS_SUCCESS) {
+		struct p2p_channels *ch_list = &(adapter_to_rfctl(padapter)->channel_list);
+
+		if (rtw_p2p_chk_role(pwdinfo, P2P_ROLE_GO)) {
+			/*	The P2P Invitation request frame asks this Wi-Fi device to be the P2P GO */
+			/*	In this case, the P2P Invitation response frame should carry the two more P2P attributes. */
+			/*	First one is operating channel attribute. */
+			/*	Second one is P2P Group BSSID attribute. */
+
+			/*	Operating Channel */
+			/*	Type: */
+			p2pie[p2pielen++] = P2P_ATTR_OPERATING_CH;
+
+			/*	Length: */
+			*(u16 *)(p2pie + p2pielen) = cpu_to_le16(0x0005);
+			p2pielen += 2;
+
+			/*	Value: */
+			/*	Country String */
+			p2pie[p2pielen++] = 'X';
+			p2pie[p2pielen++] = 'X';
+
+			/*	The third byte should be set to 0x04. */
+			/*	Described in the "Operating Channel Attribute" section. */
+			p2pie[p2pielen++] = 0x04;
+
+			/*	Operating Class */
+			p2pie[p2pielen++] = 0x51;	/*	Copy from SD7 */
+
+			/*	Channel Number */
+			p2pie[p2pielen++] = pwdinfo->operating_channel;	/*	operating channel number */
+
+
+			/*	P2P Group BSSID */
+			/*	Type: */
+			p2pie[p2pielen++] = P2P_ATTR_GROUP_BSSID;
+
+			/*	Length: */
+			*(u16 *)(p2pie + p2pielen) = cpu_to_le16(ETH_ALEN);
+			p2pielen += 2;
+
+			/*	Value: */
+			/*	P2P Device Address for GO */
+			_rtw_memcpy(p2pie + p2pielen, adapter_mac_addr(padapter), ETH_ALEN);
+			p2pielen += ETH_ALEN;
+
+		}
+
+		/*	Channel List */
+		/*	Type: */
+		p2pie[p2pielen++] = P2P_ATTR_CH_LIST;
+
+		/*	Length: */
+		/* Country String(3) */
+		/* + ( Operating Class (1) + Number of Channels(1) ) * Operation Classes (?) */
+		/* + number of channels in all classes */
+		len_channellist_attr = 3
+			+ (1 + 1) * (u16)ch_list->reg_classes
+			+ get_reg_classes_full_count(ch_list);
+
+#ifdef CONFIG_CONCURRENT_MODE
+		if (rtw_mi_check_status(padapter, MI_LINKED))
+			*(u16 *)(p2pie + p2pielen) = cpu_to_le16(5 + 1);
+		else
+			*(u16 *)(p2pie + p2pielen) = cpu_to_le16(len_channellist_attr);
+
+#else
+
+		*(u16 *)(p2pie + p2pielen) = cpu_to_le16(len_channellist_attr);
+
+#endif
+		p2pielen += 2;
+
+		/*	Value: */
+		/*	Country String */
+		p2pie[p2pielen++] = 'X';
+		p2pie[p2pielen++] = 'X';
+
+		/*	The third byte should be set to 0x04. */
+		/*	Described in the "Operating Channel Attribute" section. */
+		p2pie[p2pielen++] = 0x04;
+
+		/*	Channel Entry List */
+#ifdef CONFIG_CONCURRENT_MODE
+		if (rtw_mi_check_status(padapter, MI_LINKED)) {
+			u8 union_ch = rtw_mi_get_union_chan(padapter);
+
+			/*	Operating Class */
+			if (union_ch > 14) {
+				if (union_ch >= 149)
+					p2pie[p2pielen++] = 0x7c;
+				else
+					p2pie[p2pielen++] = 0x73;
+
+			} else
+				p2pie[p2pielen++] = 0x51;
+
+
+			/*	Number of Channels */
+			/*	Just support 1 channel and this channel is AP's channel */
+			p2pie[p2pielen++] = 1;
+
+			/*	Channel List */
+			p2pie[p2pielen++] = union_ch;
+		} else
+#endif /* CONFIG_CONCURRENT_MODE */
+		{
+			int i, j;
+			for (j = 0; j < ch_list->reg_classes; j++) {
+				/*	Operating Class */
+				p2pie[p2pielen++] = ch_list->reg_class[j].reg_class;
+
+				/*	Number of Channels */
+				p2pie[p2pielen++] = ch_list->reg_class[j].channels;
+
+				/*	Channel List */
+				for (i = 0; i < ch_list->reg_class[j].channels; i++)
+					p2pie[p2pielen++] = ch_list->reg_class[j].channel[i];
+			}
+		}
+	}
+#endif
+
+	pframe = rtw_set_ie(pframe, _VENDOR_SPECIFIC_IE_, p2pielen, (unsigned char *) p2pie, &pktlen);
+
+#ifdef CONFIG_WFD
+	wfdielen = build_invitation_resp_wfd_ie(pwdinfo, pframe);
+	pframe += wfdielen;
+	pktlen += wfdielen;
+#endif
+
+	*pLength = pktlen;
+
+#if 0
+	/* printf dbg msg */
+	dbgbufLen = pktlen;
+	RTW_INFO("======> DBG MSG FOR CONSTRAUCT Invite Rsp\n");
+
+	for (index = 0; index < dbgbufLen; index++)
+		printk("%x ", *(dbgbuf + index));
+
+	printk("\n");
+	RTW_INFO("<====== DBG MSG FOR CONSTRAUCT Invite Rsp\n");
+#endif
+}
+
+
+static void rtw_hal_construct_P2PProvisionDisRsp(_adapter *padapter, u8 *pframe, u32 *pLength)
+{
+	unsigned char category = RTW_WLAN_CATEGORY_PUBLIC;
+	u8			action = P2P_PUB_ACTION_ACTION;
+	u8			dialogToken = 0;
+	u32			p2poui = cpu_to_be32(P2POUI);
+	u8			oui_subtype = P2P_PROVISION_DISC_RESP;
+	u8			wpsie[100] = { 0x00 };
+	u8			wpsielen = 0;
+	u32			pktlen;
+#ifdef CONFIG_WFD
+	u32					wfdielen = 0;
+#endif
+
+	/* struct xmit_frame			*pmgntframe; */
+	/* struct pkt_attrib			*pattrib; */
+	/* unsigned char					*pframe; */
+	struct rtw_ieee80211_hdr	*pwlanhdr;
+	unsigned short				*fctrl;
+	struct xmit_priv			*pxmitpriv = &(padapter->xmitpriv);
+	struct mlme_ext_priv	*pmlmeext = &(padapter->mlmeextpriv);
+	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
+	struct wifidirect_info	*pwdinfo = &(padapter->wdinfo);
+
+	/* for debug */
+	u8 *dbgbuf = pframe;
+	u8 dbgbufLen = 0, index = 0;
+
+	RTW_INFO("%s\n", __FUNCTION__);
+
+	pwlanhdr = (struct rtw_ieee80211_hdr *)pframe;
+
+	fctrl = &(pwlanhdr->frame_ctl);
+	*(fctrl) = 0;
+
+	/* RA filled by FW */
+	_rtw_memset(pwlanhdr->addr1, 0, ETH_ALEN);
+	_rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN);
+	_rtw_memcpy(pwlanhdr->addr3, adapter_mac_addr(padapter), ETH_ALEN);
+
+	SetSeqNum(pwlanhdr, 0);
+	set_frame_sub_type(pframe, WIFI_ACTION);
+
+	pframe += sizeof(struct rtw_ieee80211_hdr_3addr);
+	pktlen = sizeof(struct rtw_ieee80211_hdr_3addr);
+
+	pframe = rtw_set_fixed_ie(pframe, 1, &(category), &(pktlen));
+	pframe = rtw_set_fixed_ie(pframe, 1, &(action), &(pktlen));
+	pframe = rtw_set_fixed_ie(pframe, 4, (unsigned char *) &(p2poui), &(pktlen));
+	pframe = rtw_set_fixed_ie(pframe, 1, &(oui_subtype), &(pktlen));
+	/* dialog token, filled by FW */
+	pframe = rtw_set_fixed_ie(pframe, 1, &(dialogToken), &(pktlen));
+
+	wpsielen = 0;
+	/*	WPS OUI */
+	/* *(u32*) ( wpsie ) = cpu_to_be32( WPSOUI ); */
+	RTW_PUT_BE32(wpsie, WPSOUI);
+	wpsielen += 4;
+
+#if 0
+	/*	WPS version */
+	/*	Type: */
+	*(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_ATTR_VER1);
+	wpsielen += 2;
+
+	/*	Length: */
+	*(u16 *)(wpsie + wpsielen) = cpu_to_be16(0x0001);
+	wpsielen += 2;
+
+	/*	Value: */
+	wpsie[wpsielen++] = WPS_VERSION_1;	/*	Version 1.0 */
+#endif
+
+	/*	Config Method */
+	/*	Type: */
+	/* *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( WPS_ATTR_CONF_METHOD ); */
+	RTW_PUT_BE16(wpsie + wpsielen, WPS_ATTR_CONF_METHOD);
+	wpsielen += 2;
+
+	/*	Length: */
+	/* *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( 0x0002 ); */
+	RTW_PUT_BE16(wpsie + wpsielen, 0x0002);
+	wpsielen += 2;
+
+	/*	Value: filled by FW, default value is PBC */
+	/* *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( config_method ); */
+	RTW_PUT_BE16(wpsie + wpsielen, WPS_CM_PUSH_BUTTON);
+	wpsielen += 2;
+
+	pframe = rtw_set_ie(pframe, _VENDOR_SPECIFIC_IE_, wpsielen, (unsigned char *) wpsie, &pktlen);
+
+#ifdef CONFIG_WFD
+	wfdielen = build_provdisc_resp_wfd_ie(pwdinfo, pframe);
+	pframe += wfdielen;
+	pktlen += wfdielen;
+#endif
+
+	*pLength = pktlen;
+
+	/* printf dbg msg */
+#if 0
+	dbgbufLen = pktlen;
+	RTW_INFO("======> DBG MSG FOR CONSTRAUCT  ProvisionDis Rsp\n");
+
+	for (index = 0; index < dbgbufLen; index++)
+		printk("%x ", *(dbgbuf + index));
+
+	printk("\n");
+	RTW_INFO("<====== DBG MSG FOR CONSTRAUCT ProvisionDis Rsp\n");
+#endif
+}
+
+u8 rtw_hal_set_FwP2PRsvdPage_cmd(_adapter *adapter, PRSVDPAGE_LOC rsvdpageloc)
+{
+	u8 u1H2CP2PRsvdPageParm[H2C_P2PRSVDPAGE_LOC_LEN] = {0};
+	struct hal_ops *pHalFunc = &adapter->hal_func;
+	u8 ret = _FAIL;
+
+	RTW_INFO("P2PRsvdPageLoc: P2PBeacon=%d P2PProbeRsp=%d NegoRsp=%d InviteRsp=%d PDRsp=%d\n",
+		 rsvdpageloc->LocP2PBeacon, rsvdpageloc->LocP2PProbeRsp,
+		 rsvdpageloc->LocNegoRsp, rsvdpageloc->LocInviteRsp,
+		 rsvdpageloc->LocPDRsp);
+
+	SET_H2CCMD_RSVDPAGE_LOC_P2P_BCN(u1H2CP2PRsvdPageParm, rsvdpageloc->LocProbeRsp);
+	SET_H2CCMD_RSVDPAGE_LOC_P2P_PROBE_RSP(u1H2CP2PRsvdPageParm, rsvdpageloc->LocPsPoll);
+	SET_H2CCMD_RSVDPAGE_LOC_P2P_NEGO_RSP(u1H2CP2PRsvdPageParm, rsvdpageloc->LocNullData);
+	SET_H2CCMD_RSVDPAGE_LOC_P2P_INVITE_RSP(u1H2CP2PRsvdPageParm, rsvdpageloc->LocQosNull);
+	SET_H2CCMD_RSVDPAGE_LOC_P2P_PD_RSP(u1H2CP2PRsvdPageParm, rsvdpageloc->LocBTQosNull);
+
+	/* FillH2CCmd8723B(padapter, H2C_8723B_P2P_OFFLOAD_RSVD_PAGE, H2C_P2PRSVDPAGE_LOC_LEN, u1H2CP2PRsvdPageParm); */
+	ret = rtw_hal_fill_h2c_cmd(adapter,
+				   H2C_P2P_OFFLOAD_RSVD_PAGE,
+				   H2C_P2PRSVDPAGE_LOC_LEN,
+				   u1H2CP2PRsvdPageParm);
+
+	return ret;
+}
+
+u8 rtw_hal_set_p2p_wowlan_offload_cmd(_adapter *adapter)
+{
+
+	u8 offload_cmd[H2C_P2P_OFFLOAD_LEN] = {0};
+	struct wifidirect_info	*pwdinfo = &(adapter->wdinfo);
+	struct P2P_WoWlan_Offload_t *p2p_wowlan_offload = (struct P2P_WoWlan_Offload_t *)offload_cmd;
+	struct hal_ops *pHalFunc = &adapter->hal_func;
+	u8 ret = _FAIL;
+
+	_rtw_memset(p2p_wowlan_offload, 0 , sizeof(struct P2P_WoWlan_Offload_t));
+	RTW_INFO("%s\n", __func__);
+	switch (pwdinfo->role) {
+	case P2P_ROLE_DEVICE:
+		RTW_INFO("P2P_ROLE_DEVICE\n");
+		p2p_wowlan_offload->role = 0;
+		break;
+	case P2P_ROLE_CLIENT:
+		RTW_INFO("P2P_ROLE_CLIENT\n");
+		p2p_wowlan_offload->role = 1;
+		break;
+	case P2P_ROLE_GO:
+		RTW_INFO("P2P_ROLE_GO\n");
+		p2p_wowlan_offload->role = 2;
+		break;
+	default:
+		RTW_INFO("P2P_ROLE_DISABLE\n");
+		break;
+	}
+	p2p_wowlan_offload->Wps_Config[0] = pwdinfo->supported_wps_cm >> 8;
+	p2p_wowlan_offload->Wps_Config[1] = pwdinfo->supported_wps_cm;
+	offload_cmd = (u8 *)p2p_wowlan_offload;
+	RTW_INFO("p2p_wowlan_offload: %x:%x:%x\n", offload_cmd[0], offload_cmd[1], offload_cmd[2]);
+
+	ret = rtw_hal_fill_h2c_cmd(adapter,
+				   H2C_P2P_OFFLOAD,
+				   H2C_P2P_OFFLOAD_LEN,
+				   offload_cmd);
+	return ret;
+
+	/* FillH2CCmd8723B(adapter, H2C_8723B_P2P_OFFLOAD, sizeof(struct P2P_WoWlan_Offload_t), (u8 *)p2p_wowlan_offload); */
+}
+#endif /* CONFIG_P2P_WOWLAN */
+
+void rtw_hal_construct_beacon(_adapter *padapter,
+				     u8 *pframe, u32 *pLength)
+{
+	struct rtw_ieee80211_hdr	*pwlanhdr;
+	u16					*fctrl;
+	u32					rate_len, pktlen;
+	struct mlme_ext_priv	*pmlmeext = &(padapter->mlmeextpriv);
+	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
+	WLAN_BSSID_EX		*cur_network = &(pmlmeinfo->network);
+	u8	bc_addr[] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
+
+
+	/* RTW_INFO("%s\n", __FUNCTION__); */
+
+	pwlanhdr = (struct rtw_ieee80211_hdr *)pframe;
+
+	fctrl = &(pwlanhdr->frame_ctl);
+	*(fctrl) = 0;
+
+	_rtw_memcpy(pwlanhdr->addr1, bc_addr, ETH_ALEN);
+	_rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN);
+	_rtw_memcpy(pwlanhdr->addr3, get_my_bssid(cur_network), ETH_ALEN);
+
+	SetSeqNum(pwlanhdr, 0/*pmlmeext->mgnt_seq*/);
+	/* pmlmeext->mgnt_seq++; */
+	set_frame_sub_type(pframe, WIFI_BEACON);
+
+	pframe += sizeof(struct rtw_ieee80211_hdr_3addr);
+	pktlen = sizeof(struct rtw_ieee80211_hdr_3addr);
+
+	/* timestamp will be inserted by hardware */
+	pframe += 8;
+	pktlen += 8;
+
+	/* beacon interval: 2 bytes */
+	_rtw_memcpy(pframe, (unsigned char *)(rtw_get_beacon_interval_from_ie(cur_network->IEs)), 2);
+
+	pframe += 2;
+	pktlen += 2;
+
+#if 0
+	/* capability info: 2 bytes */
+	_rtw_memcpy(pframe, (unsigned char *)(rtw_get_capability_from_ie(cur_network->IEs)), 2);
+
+	pframe += 2;
+	pktlen += 2;
+
+	if ((pmlmeinfo->state & 0x03) == WIFI_FW_AP_STATE) {
+		/* RTW_INFO("ie len=%d\n", cur_network->IELength); */
+		pktlen += cur_network->IELength - sizeof(NDIS_802_11_FIXED_IEs);
+		_rtw_memcpy(pframe, cur_network->IEs + sizeof(NDIS_802_11_FIXED_IEs), pktlen);
+
+		goto _ConstructBeacon;
+	}
+
+	/* below for ad-hoc mode */
+
+	/* SSID */
+	pframe = rtw_set_ie(pframe, _SSID_IE_, cur_network->Ssid.SsidLength, cur_network->Ssid.Ssid, &pktlen);
+
+	/* supported rates... */
+	rate_len = rtw_get_rateset_len(cur_network->SupportedRates);
+	pframe = rtw_set_ie(pframe, _SUPPORTEDRATES_IE_, ((rate_len > 8) ? 8 : rate_len), cur_network->SupportedRates, &pktlen);
+
+	/* DS parameter set */
+	pframe = rtw_set_ie(pframe, _DSSET_IE_, 1, (unsigned char *)&(cur_network->Configuration.DSConfig), &pktlen);
+
+	if ((pmlmeinfo->state & 0x03) == WIFI_FW_ADHOC_STATE) {
+		u32 ATIMWindow;
+		/* IBSS Parameter Set... */
+		/* ATIMWindow = cur->Configuration.ATIMWindow; */
+		ATIMWindow = 0;
+		pframe = rtw_set_ie(pframe, _IBSS_PARA_IE_, 2, (unsigned char *)(&ATIMWindow), &pktlen);
+	}
+
+
+	/* todo: ERP IE */
+
+
+	/* EXTERNDED SUPPORTED RATE */
+	if (rate_len > 8)
+		pframe = rtw_set_ie(pframe, _EXT_SUPPORTEDRATES_IE_, (rate_len - 8), (cur_network->SupportedRates + 8), &pktlen);
+
+	/* todo:HT for adhoc */
+#endif
+
+_ConstructBeacon:
+
+	if ((pktlen + TXDESC_SIZE) > MAX_BEACON_LEN) {
+		RTW_ERR("beacon frame too large ,len(%d,%d)\n",
+			(pktlen + TXDESC_SIZE), MAX_BEACON_LEN);
+		rtw_warn_on(1);
+		return;
+	}
+
+	*pLength = pktlen;
+
+	/* RTW_INFO("%s bcn_sz=%d\n", __FUNCTION__, pktlen); */
+
+}
+
+static void rtw_hal_construct_PSPoll(_adapter *padapter,
+				     u8 *pframe, u32 *pLength)
+{
+	struct rtw_ieee80211_hdr	*pwlanhdr;
+	u16					*fctrl;
+	u32					pktlen;
+	struct mlme_ext_priv	*pmlmeext = &(padapter->mlmeextpriv);
+	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
+
+	/* RTW_INFO("%s\n", __FUNCTION__); */
+
+	pwlanhdr = (struct rtw_ieee80211_hdr *)pframe;
+
+	/* Frame control. */
+	fctrl = &(pwlanhdr->frame_ctl);
+	*(fctrl) = 0;
+	SetPwrMgt(fctrl);
+	set_frame_sub_type(pframe, WIFI_PSPOLL);
+
+	/* AID. */
+	set_duration(pframe, (pmlmeinfo->aid | 0xc000));
+
+	/* BSSID. */
+	_rtw_memcpy(pwlanhdr->addr1, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN);
+
+	/* TA. */
+	_rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN);
+
+	*pLength = 16;
+}
+
+
+#ifdef DBG_FW_DEBUG_MSG_PKT
+void rtw_hal_construct_fw_dbg_msg_pkt(
+	PADAPTER padapter,
+	u8		*pframe,
+	u32		*plength)
+{
+	struct rtw_ieee80211_hdr	*pwlanhdr;
+	u16						*fctrl;
+	u32						pktlen;
+	struct mlme_priv		*pmlmepriv = &padapter->mlmepriv;
+	struct wlan_network		*cur_network = &pmlmepriv->cur_network;
+	struct mlme_ext_priv	*pmlmeext = &(padapter->mlmeextpriv);
+	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
+	u8	bc_addr[] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
+
+
+	/* RTW_INFO("%s:%d\n", __FUNCTION__, bForcePowerSave); */
+
+	pwlanhdr = (struct rtw_ieee80211_hdr *)pframe;
+
+	fctrl = &pwlanhdr->frame_ctl;
+	*(fctrl) = 0;
+
+	_rtw_memcpy(pwlanhdr->addr1, bc_addr, ETH_ALEN);
+	_rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN);
+	_rtw_memcpy(pwlanhdr->addr3, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN);
+
+	SetSeqNum(pwlanhdr, 0);
+
+	set_frame_sub_type(pframe, WIFI_DATA);
+
+	pktlen = sizeof(struct rtw_ieee80211_hdr_3addr);
+
+	*plength = pktlen;
+}
+#endif /*DBG_FW_DEBUG_MSG_PKT*/
+
+void rtw_hal_construct_NullFunctionData(
+	PADAPTER padapter,
+	u8		*pframe,
+	u32		*pLength,
+	u8		bQoS,
+	u8		AC,
+	u8		bEosp,
+	u8		bForcePowerSave)
+{
+	struct rtw_ieee80211_hdr	*pwlanhdr;
+	u16						*fctrl;
+	u32						pktlen;
+	struct mlme_priv		*pmlmepriv = &padapter->mlmepriv;
+	struct wlan_network		*cur_network = &pmlmepriv->cur_network;
+	struct mlme_ext_priv	*pmlmeext = &(padapter->mlmeextpriv);
+	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
+	u8 *sta_addr = NULL;
+	u8 bssid[ETH_ALEN] = {0};
+
+	/* RTW_INFO("%s:%d\n", __FUNCTION__, bForcePowerSave); */
+
+	pwlanhdr = (struct rtw_ieee80211_hdr *)pframe;
+
+	fctrl = &pwlanhdr->frame_ctl;
+	*(fctrl) = 0;
+	if (bForcePowerSave)
+		SetPwrMgt(fctrl);
+
+	sta_addr = get_my_bssid(&pmlmeinfo->network);
+	if (NULL == sta_addr) {
+		_rtw_memcpy(bssid, adapter_mac_addr(padapter), ETH_ALEN);
+		sta_addr = bssid;
+	}
+
+	switch (cur_network->network.InfrastructureMode) {
+	case Ndis802_11Infrastructure:
+		SetToDs(fctrl);
+		_rtw_memcpy(pwlanhdr->addr1, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN);
+		_rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN);
+		_rtw_memcpy(pwlanhdr->addr3, sta_addr, ETH_ALEN);
+		break;
+	case Ndis802_11APMode:
+		SetFrDs(fctrl);
+		_rtw_memcpy(pwlanhdr->addr1, sta_addr, ETH_ALEN);
+		_rtw_memcpy(pwlanhdr->addr2, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN);
+		_rtw_memcpy(pwlanhdr->addr3, adapter_mac_addr(padapter), ETH_ALEN);
+		break;
+	case Ndis802_11IBSS:
+	default:
+		_rtw_memcpy(pwlanhdr->addr1, sta_addr, ETH_ALEN);
+		_rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN);
+		_rtw_memcpy(pwlanhdr->addr3, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN);
+		break;
+	}
+
+	SetSeqNum(pwlanhdr, 0);
+	set_duration(pwlanhdr, 0);
+
+	if (bQoS == _TRUE) {
+		struct rtw_ieee80211_hdr_3addr_qos *pwlanqoshdr;
+
+		set_frame_sub_type(pframe, WIFI_QOS_DATA_NULL);
+
+		pwlanqoshdr = (struct rtw_ieee80211_hdr_3addr_qos *)pframe;
+		SetPriority(&pwlanqoshdr->qc, AC);
+		SetEOSP(&pwlanqoshdr->qc, bEosp);
+
+		pktlen = sizeof(struct rtw_ieee80211_hdr_3addr_qos);
+	} else {
+		set_frame_sub_type(pframe, WIFI_DATA_NULL);
+
+		pktlen = sizeof(struct rtw_ieee80211_hdr_3addr);
+	}
+
+	*pLength = pktlen;
+}
+
+void rtw_hal_construct_ProbeRsp(_adapter *padapter, u8 *pframe, u32 *pLength,
+				BOOLEAN bHideSSID)
+{
+	struct rtw_ieee80211_hdr	*pwlanhdr;
+	u16					*fctrl;
+	u8					*mac, *bssid, *sta_addr;
+	u32					pktlen;
+	struct mlme_ext_priv	*pmlmeext = &(padapter->mlmeextpriv);
+	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
+	WLAN_BSSID_EX  *cur_network = &(pmlmeinfo->network);
+
+	/*RTW_INFO("%s\n", __FUNCTION__);*/
+
+	pwlanhdr = (struct rtw_ieee80211_hdr *)pframe;
+
+	mac = adapter_mac_addr(padapter);
+	bssid = cur_network->MacAddress;
+	sta_addr = get_my_bssid(&pmlmeinfo->network);
+
+	fctrl = &(pwlanhdr->frame_ctl);
+	*(fctrl) = 0;
+	_rtw_memcpy(pwlanhdr->addr1, sta_addr, ETH_ALEN);
+	_rtw_memcpy(pwlanhdr->addr2, mac, ETH_ALEN);
+	_rtw_memcpy(pwlanhdr->addr3, bssid, ETH_ALEN);
+
+	SetSeqNum(pwlanhdr, 0);
+	set_frame_sub_type(fctrl, WIFI_PROBERSP);
+
+	pktlen = sizeof(struct rtw_ieee80211_hdr_3addr);
+	pframe += pktlen;
+
+	if (cur_network->IELength > MAX_IE_SZ)
+		return;
+
+	_rtw_memcpy(pframe, cur_network->IEs, cur_network->IELength);
+	pframe += cur_network->IELength;
+	pktlen += cur_network->IELength;
+
+	*pLength = pktlen;
+}
+
+#ifdef CONFIG_WOWLAN
+static void rtw_hal_append_tkip_mic(PADAPTER padapter,
+				    u8 *pframe, u32 offset)
+{
+	struct mlme_ext_priv	*pmlmeext = &(padapter->mlmeextpriv);
+	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
+	struct rtw_ieee80211_hdr	*pwlanhdr;
+	struct mic_data	micdata;
+	struct sta_info	*psta = NULL;
+	int res = 0;
+
+	u8	*payload = (u8 *)(pframe + offset);
+
+	u8	mic[8];
+	u8	priority[4] = {0x0};
+	u8	null_key[16] = {0x0};
+
+	RTW_INFO("%s(): Add MIC, offset: %d\n", __func__, offset);
+
+	pwlanhdr = (struct rtw_ieee80211_hdr *)pframe;
+
+	psta = rtw_get_stainfo(&padapter->stapriv,
+			get_my_bssid(&(pmlmeinfo->network)));
+	if (psta != NULL) {
+		res = _rtw_memcmp(&psta->dot11tkiptxmickey.skey[0],
+				  null_key, 16);
+		if (res == _TRUE)
+			RTW_INFO("%s(): STA dot11tkiptxmickey==0\n", __func__);
+		rtw_secmicsetkey(&micdata, &psta->dot11tkiptxmickey.skey[0]);
+	}
+
+	rtw_secmicappend(&micdata, pwlanhdr->addr3, 6);  /* DA */
+
+	rtw_secmicappend(&micdata, pwlanhdr->addr2, 6); /* SA */
+
+	priority[0] = 0;
+
+	rtw_secmicappend(&micdata, &priority[0], 4);
+
+	rtw_secmicappend(&micdata, payload, 36); /* payload length = 8 + 28 */
+
+	rtw_secgetmic(&micdata, &(mic[0]));
+
+	payload += 36;
+
+	_rtw_memcpy(payload, &(mic[0]), 8);
+}
+/*
+ * Description:
+ *	Construct the ARP response packet to support ARP offload.
+ *   */
+static void rtw_hal_construct_ARPRsp(
+	PADAPTER padapter,
+	u8			*pframe,
+	u32			*pLength,
+	u8			*pIPAddress
+)
+{
+	struct rtw_ieee80211_hdr	*pwlanhdr;
+	u16	*fctrl;
+	u32	pktlen;
+	struct mlme_priv	*pmlmepriv = &padapter->mlmepriv;
+	struct wlan_network	*cur_network = &pmlmepriv->cur_network;
+	struct mlme_ext_priv	*pmlmeext = &(padapter->mlmeextpriv);
+	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
+	struct security_priv	*psecuritypriv = &padapter->securitypriv;
+	static u8	ARPLLCHeader[8] = {0xAA, 0xAA, 0x03, 0x00, 0x00, 0x00, 0x08, 0x06};
+	u8	*pARPRspPkt = pframe;
+	/* for TKIP Cal MIC */
+	u8	*payload = pframe;
+	u8	EncryptionHeadOverhead = 0, arp_offset = 0;
+	/* RTW_INFO("%s:%d\n", __FUNCTION__, bForcePowerSave); */
+
+	pwlanhdr = (struct rtw_ieee80211_hdr *)pframe;
+
+	fctrl = &pwlanhdr->frame_ctl;
+	*(fctrl) = 0;
+
+	/* ------------------------------------------------------------------------- */
+	/* MAC Header. */
+	/* ------------------------------------------------------------------------- */
+	SetFrameType(fctrl, WIFI_DATA);
+	/* set_frame_sub_type(fctrl, 0); */
+	SetToDs(fctrl);
+	_rtw_memcpy(pwlanhdr->addr1, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN);
+	_rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN);
+	_rtw_memcpy(pwlanhdr->addr3, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN);
+
+	SetSeqNum(pwlanhdr, 0);
+	set_duration(pwlanhdr, 0);
+	/* SET_80211_HDR_FRAME_CONTROL(pARPRspPkt, 0); */
+	/* SET_80211_HDR_TYPE_AND_SUBTYPE(pARPRspPkt, Type_Data); */
+	/* SET_80211_HDR_TO_DS(pARPRspPkt, 1); */
+	/* SET_80211_HDR_ADDRESS1(pARPRspPkt, pMgntInfo->Bssid); */
+	/* SET_80211_HDR_ADDRESS2(pARPRspPkt, Adapter->CurrentAddress); */
+	/* SET_80211_HDR_ADDRESS3(pARPRspPkt, pMgntInfo->Bssid); */
+
+	/* SET_80211_HDR_DURATION(pARPRspPkt, 0); */
+	/* SET_80211_HDR_FRAGMENT_SEQUENCE(pARPRspPkt, 0); */
+#ifdef CONFIG_WAPI_SUPPORT
+	*pLength = sMacHdrLng;
+#else
+	*pLength = 24;
+#endif
+	switch (psecuritypriv->dot11PrivacyAlgrthm) {
+	case _WEP40_:
+	case _WEP104_:
+		EncryptionHeadOverhead = 4;
+		break;
+	case _TKIP_:
+		EncryptionHeadOverhead = 8;
+		break;
+	case _AES_:
+		EncryptionHeadOverhead = 8;
+		break;
+#ifdef CONFIG_WAPI_SUPPORT
+	case _SMS4_:
+		EncryptionHeadOverhead = 18;
+		break;
+#endif
+	default:
+		EncryptionHeadOverhead = 0;
+	}
+
+	if (EncryptionHeadOverhead > 0) {
+		_rtw_memset(&(pframe[*pLength]), 0, EncryptionHeadOverhead);
+		*pLength += EncryptionHeadOverhead;
+		/* SET_80211_HDR_WEP(pARPRspPkt, 1);  */ /* Suggested by CCW. */
+		SetPrivacy(fctrl);
+	}
+
+	/* ------------------------------------------------------------------------- */
+	/* Frame Body. */
+	/* ------------------------------------------------------------------------- */
+	arp_offset = *pLength;
+	pARPRspPkt = (u8 *)(pframe + arp_offset);
+	payload = pARPRspPkt; /* Get Payload pointer */
+	/* LLC header */
+	_rtw_memcpy(pARPRspPkt, ARPLLCHeader, 8);
+	*pLength += 8;
+
+	/* ARP element */
+	pARPRspPkt += 8;
+	SET_ARP_HTYPE(pARPRspPkt, 1);
+	SET_ARP_PTYPE(pARPRspPkt, ETH_P_IP);	/* IP protocol */
+	SET_ARP_HLEN(pARPRspPkt, ETH_ALEN);
+	SET_ARP_PLEN(pARPRspPkt, RTW_IP_ADDR_LEN);
+	SET_ARP_OPER(pARPRspPkt, 2);	/* ARP response */
+	SET_ARP_SENDER_MAC_ADDR(pARPRspPkt, adapter_mac_addr(padapter));
+	SET_ARP_SENDER_IP_ADDR(pARPRspPkt, pIPAddress);
+#ifdef CONFIG_ARP_KEEP_ALIVE
+	if (!is_zero_mac_addr(pmlmepriv->gw_mac_addr)) {
+		SET_ARP_TARGET_MAC_ADDR(pARPRspPkt, pmlmepriv->gw_mac_addr);
+		SET_ARP_TARGET_IP_ADDR(pARPRspPkt, pmlmepriv->gw_ip);
+	} else
+#endif
+	{
+		SET_ARP_TARGET_MAC_ADDR(pARPRspPkt,
+				    get_my_bssid(&(pmlmeinfo->network)));
+		SET_ARP_TARGET_IP_ADDR(pARPRspPkt,
+					   pIPAddress);
+		RTW_INFO("%s Target Mac Addr:" MAC_FMT "\n", __FUNCTION__,
+			 MAC_ARG(get_my_bssid(&(pmlmeinfo->network))));
+		RTW_INFO("%s Target IP Addr" IP_FMT "\n", __FUNCTION__,
+			 IP_ARG(pIPAddress));
+	}
+
+	*pLength += 28;
+
+	if (psecuritypriv->dot11PrivacyAlgrthm == _TKIP_) {
+		if (IS_HARDWARE_TYPE_8188E(padapter) ||
+		    IS_HARDWARE_TYPE_8812(padapter)) {
+			rtw_hal_append_tkip_mic(padapter, pframe, arp_offset);
+		}
+		*pLength += 8;
+	}
+}
+
+#ifdef CONFIG_IPV6
+/*
+ * Description: Neighbor Discovery Offload.
+ */
+static void rtw_hal_construct_na_message(_adapter *padapter,
+				     u8 *pframe, u32 *pLength)
+{
+	struct rtw_ieee80211_hdr *pwlanhdr = NULL;
+	struct mlme_priv	*pmlmepriv = &padapter->mlmepriv;
+	struct wlan_network	*cur_network = &pmlmepriv->cur_network;
+	struct mlme_ext_priv	*pmlmeext = &padapter->mlmeextpriv;
+	struct mlme_ext_info	*pmlmeinfo = &pmlmeext->mlmext_info;
+	struct security_priv	*psecuritypriv = &padapter->securitypriv;
+
+	u32 pktlen = 0;
+	u16 *fctrl = NULL;
+
+	u8 ns_hdr[8] = {0xAA, 0xAA, 0x03, 0x00, 0x00, 0x00, 0x86, 0xDD};
+	u8 ipv6_info[4] = {0x60, 0x00, 0x00, 0x00};
+	u8 ipv6_contx[4] = {0x00, 0x20, 0x3a, 0xff};
+	u8 icmpv6_hdr[8] = {0x88, 0x00, 0x00, 0x00, 0x60, 0x00, 0x00, 0x00};
+	u8 val8 = 0;
+
+	u8 *p_na_msg = pframe;
+	/* for TKIP Cal MIC */
+	u8 *payload = pframe;
+	u8 EncryptionHeadOverhead = 0, na_msg_offset = 0;
+	/* RTW_INFO("%s:%d\n", __FUNCTION__, bForcePowerSave); */
+
+	pwlanhdr = (struct rtw_ieee80211_hdr *)pframe;
+
+	fctrl = &pwlanhdr->frame_ctl;
+	*(fctrl) = 0;
+
+	/* ------------------------------------------------------------------------- */
+	/* MAC Header. */
+	/* ------------------------------------------------------------------------- */
+	SetFrameType(fctrl, WIFI_DATA);
+	SetToDs(fctrl);
+	_rtw_memcpy(pwlanhdr->addr1,
+		    get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN);
+	_rtw_memcpy(pwlanhdr->addr2,
+		    adapter_mac_addr(padapter), ETH_ALEN);
+	_rtw_memcpy(pwlanhdr->addr3,
+		    get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN);
+
+	SetSeqNum(pwlanhdr, 0);
+	set_duration(pwlanhdr, 0);
+
+#ifdef CONFIG_WAPI_SUPPORT
+	*pLength = sMacHdrLng;
+#else
+	*pLength = 24;
+#endif
+	switch (psecuritypriv->dot11PrivacyAlgrthm) {
+	case _WEP40_:
+	case _WEP104_:
+		EncryptionHeadOverhead = 4;
+		break;
+	case _TKIP_:
+		EncryptionHeadOverhead = 8;
+		break;
+	case _AES_:
+		EncryptionHeadOverhead = 8;
+		break;
+#ifdef CONFIG_WAPI_SUPPORT
+	case _SMS4_:
+		EncryptionHeadOverhead = 18;
+		break;
+#endif
+	default:
+		EncryptionHeadOverhead = 0;
+	}
+
+	if (EncryptionHeadOverhead > 0) {
+		_rtw_memset(&(pframe[*pLength]), 0, EncryptionHeadOverhead);
+		*pLength += EncryptionHeadOverhead;
+		/* SET_80211_HDR_WEP(pARPRspPkt, 1);  */ /* Suggested by CCW. */
+		SetPrivacy(fctrl);
+	}
+
+	/* ------------------------------------------------------------------------- */
+	/* Frame Body. */
+	/* ------------------------------------------------------------------------- */
+	na_msg_offset = *pLength;
+	p_na_msg = (u8 *)(pframe + na_msg_offset);
+	payload = p_na_msg; /* Get Payload pointer */
+
+	/* LLC header */
+	val8 = sizeof(ns_hdr);
+	_rtw_memcpy(p_na_msg, ns_hdr, val8);
+	*pLength += val8;
+	p_na_msg += val8;
+
+	/* IPv6 Header */
+	/* 1 . Information (4 bytes): 0x60 0x00 0x00 0x00 */
+	val8 = sizeof(ipv6_info);
+	_rtw_memcpy(p_na_msg, ipv6_info, val8);
+	*pLength += val8;
+	p_na_msg += val8;
+
+	/* 2 . playload : 0x00 0x20 , NextProt : 0x3a (ICMPv6) HopLim : 0xff */
+	val8 = sizeof(ipv6_contx);
+	_rtw_memcpy(p_na_msg, ipv6_contx, val8);
+	*pLength += val8;
+	p_na_msg += val8;
+
+	/* 3 . SA : 16 bytes , DA : 16 bytes ( Fw will filled ) */
+	_rtw_memset(&(p_na_msg[*pLength]), 0, 32);
+	*pLength += 32;
+	p_na_msg += 32;
+
+	/* ICMPv6 */
+	/* 1. Type : 0x88 (NA)
+	 * 2. Code : 0x00
+	 * 3. ChechSum : 0x00 0x00 (RSvd)
+	 * 4. NAFlag: 0x60 0x00 0x00 0x00 ( Solicited , Override)
+	 */
+	val8 = sizeof(icmpv6_hdr);
+	_rtw_memcpy(p_na_msg, icmpv6_hdr, val8);
+	*pLength += val8;
+	p_na_msg += val8;
+
+	/* TA: 16 bytes*/
+	_rtw_memset(&(p_na_msg[*pLength]), 0, 16);
+	*pLength += 16;
+	p_na_msg += 16;
+
+	/* ICMPv6 Target Link Layer Address */
+	p_na_msg[0] = 0x02; /* type */
+	p_na_msg[1] = 0x01; /* len 1 unit of 8 octes */
+	*pLength += 2;
+	p_na_msg += 2;
+
+	_rtw_memset(&(p_na_msg[*pLength]), 0, 6);
+	*pLength += 6;
+	p_na_msg += 6;
+
+	if (psecuritypriv->dot11PrivacyAlgrthm == _TKIP_) {
+		if (IS_HARDWARE_TYPE_8188E(padapter) ||
+		    IS_HARDWARE_TYPE_8812(padapter)) {
+			rtw_hal_append_tkip_mic(padapter, pframe,
+						na_msg_offset);
+		}
+		*pLength += 8;
+	}
+}
+/*
+ * Description: Neighbor Discovery Protocol Information.
+ */
+static void rtw_hal_construct_ndp_info(_adapter *padapter,
+				     u8 *pframe, u32 *pLength)
+{
+	struct mlme_ext_priv *pmlmeext = NULL;
+	struct mlme_ext_info *pmlmeinfo = NULL;
+	struct rtw_ndp_info ndp_info;
+	u8	*pndp_info = pframe;
+	u8	len = sizeof(struct rtw_ndp_info);
+
+	RTW_INFO("%s: len: %d\n", __func__, len);
+
+	pmlmeext =  &padapter->mlmeextpriv;
+	pmlmeinfo = &pmlmeext->mlmext_info;
+
+	_rtw_memset(pframe, 0, len);
+	_rtw_memset(&ndp_info, 0, len);
+
+	ndp_info.enable = 1;
+	ndp_info.check_remote_ip = 0;
+	ndp_info.num_of_target_ip = 1;
+
+	_rtw_memcpy(&ndp_info.target_link_addr, adapter_mac_addr(padapter),
+		    ETH_ALEN);
+	_rtw_memcpy(&ndp_info.target_ipv6_addr, pmlmeinfo->ip6_addr,
+		    RTW_IPv6_ADDR_LEN);
+
+	_rtw_memcpy(pndp_info, &ndp_info, len);
+}
+#endif /* CONFIG_IPV6 */
+
+#ifdef CONFIG_PNO_SUPPORT
+static void rtw_hal_construct_ProbeReq(_adapter *padapter, u8 *pframe,
+				       u32 *pLength, pno_ssid_t *ssid)
+{
+	struct rtw_ieee80211_hdr	*pwlanhdr;
+	u16				*fctrl;
+	u32				pktlen;
+	unsigned char			*mac;
+	unsigned char			bssrate[NumRates];
+	struct xmit_priv		*pxmitpriv = &(padapter->xmitpriv);
+	struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
+	struct mlme_ext_priv	*pmlmeext = &(padapter->mlmeextpriv);
+	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
+	int	bssrate_len = 0;
+	u8	bc_addr[] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
+
+	pwlanhdr = (struct rtw_ieee80211_hdr *)pframe;
+	mac = adapter_mac_addr(padapter);
+
+	fctrl = &(pwlanhdr->frame_ctl);
+	*(fctrl) = 0;
+
+	_rtw_memcpy(pwlanhdr->addr1, bc_addr, ETH_ALEN);
+	_rtw_memcpy(pwlanhdr->addr3, bc_addr, ETH_ALEN);
+
+	_rtw_memcpy(pwlanhdr->addr2, mac, ETH_ALEN);
+
+	SetSeqNum(pwlanhdr, 0);
+	set_frame_sub_type(pframe, WIFI_PROBEREQ);
+
+	pktlen = sizeof(struct rtw_ieee80211_hdr_3addr);
+	pframe += pktlen;
+
+	if (ssid == NULL)
+		pframe = rtw_set_ie(pframe, _SSID_IE_, 0, NULL, &pktlen);
+	else {
+		/* RTW_INFO("%s len:%d\n", ssid->SSID, ssid->SSID_len); */
+		pframe = rtw_set_ie(pframe, _SSID_IE_, ssid->SSID_len, ssid->SSID, &pktlen);
+	}
+
+	get_rate_set(padapter, bssrate, &bssrate_len);
+
+	if (bssrate_len > 8) {
+		pframe = rtw_set_ie(pframe, _SUPPORTEDRATES_IE_ , 8, bssrate, &pktlen);
+		pframe = rtw_set_ie(pframe, _EXT_SUPPORTEDRATES_IE_ , (bssrate_len - 8), (bssrate + 8), &pktlen);
+	} else
+		pframe = rtw_set_ie(pframe, _SUPPORTEDRATES_IE_ , bssrate_len , bssrate, &pktlen);
+
+	*pLength = pktlen;
+}
+
+static void rtw_hal_construct_PNO_info(_adapter *padapter,
+				       u8 *pframe, u32 *pLength)
+{
+	struct pwrctrl_priv *pwrctl = adapter_to_pwrctl(padapter);
+	int i;
+
+	u8	*pPnoInfoPkt = pframe;
+	pPnoInfoPkt = (u8 *)(pframe + *pLength);
+	_rtw_memcpy(pPnoInfoPkt, &pwrctl->pnlo_info->ssid_num, 1);
+
+	pPnoInfoPkt += 1;
+	_rtw_memcpy(pPnoInfoPkt, &pwrctl->pnlo_info->hidden_ssid_num, 1);
+
+	pPnoInfoPkt += 3;
+	_rtw_memcpy(pPnoInfoPkt, &pwrctl->pnlo_info->fast_scan_period, 1);
+
+	pPnoInfoPkt += 4;
+	_rtw_memcpy(pPnoInfoPkt, &pwrctl->pnlo_info->fast_scan_iterations, 4);
+
+	pPnoInfoPkt += 4;
+	_rtw_memcpy(pPnoInfoPkt, &pwrctl->pnlo_info->slow_scan_period, 4);
+
+	pPnoInfoPkt += 4;
+	_rtw_memcpy(pPnoInfoPkt, &pwrctl->pnlo_info->ssid_length, MAX_PNO_LIST_COUNT);
+
+	pPnoInfoPkt += MAX_PNO_LIST_COUNT;
+	_rtw_memcpy(pPnoInfoPkt, &pwrctl->pnlo_info->ssid_cipher_info, MAX_PNO_LIST_COUNT);
+
+	pPnoInfoPkt += MAX_PNO_LIST_COUNT;
+	_rtw_memcpy(pPnoInfoPkt, &pwrctl->pnlo_info->ssid_channel_info, MAX_PNO_LIST_COUNT);
+
+	pPnoInfoPkt += MAX_PNO_LIST_COUNT;
+	_rtw_memcpy(pPnoInfoPkt, &pwrctl->pnlo_info->loc_probe_req, MAX_HIDDEN_AP);
+
+	pPnoInfoPkt += MAX_HIDDEN_AP;
+
+	/*
+	SSID is located at 128th Byte in NLO info Page
+	*/
+
+	*pLength += 128;
+	pPnoInfoPkt = pframe + 128;
+
+	for (i = 0; i < pwrctl->pnlo_info->ssid_num ; i++) {
+		_rtw_memcpy(pPnoInfoPkt, &pwrctl->pno_ssid_list->node[i].SSID,
+			    pwrctl->pnlo_info->ssid_length[i]);
+		*pLength += WLAN_SSID_MAXLEN;
+		pPnoInfoPkt += WLAN_SSID_MAXLEN;
+	}
+}
+
+static void rtw_hal_construct_ssid_list(_adapter *padapter,
+					u8 *pframe, u32 *pLength)
+{
+	struct pwrctrl_priv *pwrctl = adapter_to_pwrctl(padapter);
+	u8 *pSSIDListPkt = pframe;
+	int i;
+
+	pSSIDListPkt = (u8 *)(pframe + *pLength);
+
+	for (i = 0; i < pwrctl->pnlo_info->ssid_num ; i++) {
+		_rtw_memcpy(pSSIDListPkt, &pwrctl->pno_ssid_list->node[i].SSID,
+			    pwrctl->pnlo_info->ssid_length[i]);
+
+		*pLength += WLAN_SSID_MAXLEN;
+		pSSIDListPkt += WLAN_SSID_MAXLEN;
+	}
+}
+
+static void rtw_hal_construct_scan_info(_adapter *padapter,
+					u8 *pframe, u32 *pLength)
+{
+	struct pwrctrl_priv *pwrctl = adapter_to_pwrctl(padapter);
+	u8 *pScanInfoPkt = pframe;
+	int i;
+
+	pScanInfoPkt = (u8 *)(pframe + *pLength);
+
+	_rtw_memcpy(pScanInfoPkt, &pwrctl->pscan_info->channel_num, 1);
+
+	*pLength += 1;
+	pScanInfoPkt += 1;
+	_rtw_memcpy(pScanInfoPkt, &pwrctl->pscan_info->orig_ch, 1);
+
+
+	*pLength += 1;
+	pScanInfoPkt += 1;
+	_rtw_memcpy(pScanInfoPkt, &pwrctl->pscan_info->orig_bw, 1);
+
+
+	*pLength += 1;
+	pScanInfoPkt += 1;
+	_rtw_memcpy(pScanInfoPkt, &pwrctl->pscan_info->orig_40_offset, 1);
+
+	*pLength += 1;
+	pScanInfoPkt += 1;
+	_rtw_memcpy(pScanInfoPkt, &pwrctl->pscan_info->orig_80_offset, 1);
+
+	*pLength += 1;
+	pScanInfoPkt += 1;
+	_rtw_memcpy(pScanInfoPkt, &pwrctl->pscan_info->periodScan, 1);
+
+	*pLength += 1;
+	pScanInfoPkt += 1;
+	_rtw_memcpy(pScanInfoPkt, &pwrctl->pscan_info->period_scan_time, 1);
+
+	*pLength += 1;
+	pScanInfoPkt += 1;
+	_rtw_memcpy(pScanInfoPkt, &pwrctl->pscan_info->enableRFE, 1);
+
+	*pLength += 1;
+	pScanInfoPkt += 1;
+	_rtw_memcpy(pScanInfoPkt, &pwrctl->pscan_info->rfe_type, 8);
+
+	*pLength += 8;
+	pScanInfoPkt += 8;
+
+	for (i = 0 ; i < MAX_SCAN_LIST_COUNT ; i++) {
+		_rtw_memcpy(pScanInfoPkt,
+			    &pwrctl->pscan_info->ssid_channel_info[i], 4);
+		*pLength += 4;
+		pScanInfoPkt += 4;
+	}
+}
+#endif /* CONFIG_PNO_SUPPORT */
+
+#ifdef CONFIG_GTK_OL
+static void rtw_hal_construct_GTKRsp(
+	PADAPTER	padapter,
+	u8		*pframe,
+	u32		*pLength
+)
+{
+	struct rtw_ieee80211_hdr	*pwlanhdr;
+	u16	*fctrl;
+	u32	pktlen;
+	struct mlme_priv	*pmlmepriv = &padapter->mlmepriv;
+	struct wlan_network	*cur_network = &pmlmepriv->cur_network;
+	struct mlme_ext_priv	*pmlmeext = &(padapter->mlmeextpriv);
+	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
+	struct security_priv	*psecuritypriv = &padapter->securitypriv;
+	static u8	LLCHeader[8] = {0xAA, 0xAA, 0x03, 0x00, 0x00, 0x00, 0x88, 0x8E};
+	static u8	GTKbody_a[11] = {0x01, 0x03, 0x00, 0x5F, 0x02, 0x03, 0x12, 0x00, 0x10, 0x42, 0x0B};
+	u8	*pGTKRspPkt = pframe;
+	u8	EncryptionHeadOverhead = 0;
+	/* RTW_INFO("%s:%d\n", __FUNCTION__, bForcePowerSave); */
+
+	pwlanhdr = (struct rtw_ieee80211_hdr *)pframe;
+
+	fctrl = &pwlanhdr->frame_ctl;
+	*(fctrl) = 0;
+
+	/* ------------------------------------------------------------------------- */
+	/* MAC Header. */
+	/* ------------------------------------------------------------------------- */
+	SetFrameType(fctrl, WIFI_DATA);
+	/* set_frame_sub_type(fctrl, 0); */
+	SetToDs(fctrl);
+
+	_rtw_memcpy(pwlanhdr->addr1,
+		    get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN);
+
+	_rtw_memcpy(pwlanhdr->addr2,
+		    adapter_mac_addr(padapter), ETH_ALEN);
+
+	_rtw_memcpy(pwlanhdr->addr3,
+		    get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN);
+
+	SetSeqNum(pwlanhdr, 0);
+	set_duration(pwlanhdr, 0);
+
+#ifdef CONFIG_WAPI_SUPPORT
+	*pLength = sMacHdrLng;
+#else
+	*pLength = 24;
+#endif /* CONFIG_WAPI_SUPPORT */
+
+	/* ------------------------------------------------------------------------- */
+	/* Security Header: leave space for it if necessary. */
+	/* ------------------------------------------------------------------------- */
+	switch (psecuritypriv->dot11PrivacyAlgrthm) {
+	case _WEP40_:
+	case _WEP104_:
+		EncryptionHeadOverhead = 4;
+		break;
+	case _TKIP_:
+		EncryptionHeadOverhead = 8;
+		break;
+	case _AES_:
+		EncryptionHeadOverhead = 8;
+		break;
+#ifdef CONFIG_WAPI_SUPPORT
+	case _SMS4_:
+		EncryptionHeadOverhead = 18;
+		break;
+#endif /* CONFIG_WAPI_SUPPORT */
+	default:
+		EncryptionHeadOverhead = 0;
+	}
+
+	if (EncryptionHeadOverhead > 0) {
+		_rtw_memset(&(pframe[*pLength]), 0, EncryptionHeadOverhead);
+		*pLength += EncryptionHeadOverhead;
+		/* SET_80211_HDR_WEP(pGTKRspPkt, 1);  */ /* Suggested by CCW. */
+		/* GTK's privacy bit is done by FW */
+		/* SetPrivacy(fctrl); */
+	}
+	/* ------------------------------------------------------------------------- */
+	/* Frame Body. */
+	/* ------------------------------------------------------------------------- */
+	pGTKRspPkt = (u8 *)(pframe + *pLength);
+	/* LLC header */
+	_rtw_memcpy(pGTKRspPkt, LLCHeader, 8);
+	*pLength += 8;
+
+	/* GTK element */
+	pGTKRspPkt += 8;
+
+	/* GTK frame body after LLC, part 1 */
+	/* TKIP key_length = 32, AES key_length = 16 */
+	if (psecuritypriv->dot118021XGrpPrivacy == _TKIP_)
+		GTKbody_a[8] = 0x20;
+
+	/* GTK frame body after LLC, part 1 */
+	_rtw_memcpy(pGTKRspPkt, GTKbody_a, 11);
+	*pLength += 11;
+	pGTKRspPkt += 11;
+	/* GTK frame body after LLC, part 2 */
+	_rtw_memset(&(pframe[*pLength]), 0, 88);
+	*pLength += 88;
+	pGTKRspPkt += 88;
+
+	if (psecuritypriv->dot118021XGrpPrivacy == _TKIP_)
+		*pLength += 8;
+}
+#endif /* CONFIG_GTK_OL */
+
+#define PN_2_CCMPH(ch,key_id)	((ch) & 0x000000000000ffff) \
+				| (((ch) & 0x0000ffffffff0000) << 16) \
+				| (((key_id) << 30)) \
+				| BIT(29)
+static void rtw_hal_construct_remote_control_info(_adapter *adapter,
+						  u8 *pframe, u32 *pLength)
+{
+	struct mlme_priv   *pmlmepriv = &adapter->mlmepriv;
+	struct sta_priv *pstapriv = &adapter->stapriv;
+	struct security_priv *psecuritypriv = &adapter->securitypriv;
+	struct mlme_ext_priv *pmlmeext = &adapter->mlmeextpriv;
+	struct mlme_ext_info *pmlmeinfo = &pmlmeext->mlmext_info;
+	struct sta_info *psta;
+	struct stainfo_rxcache *prxcache;
+	u8 cur_dot11rxiv[8], id = 0, tid_id = 0, i = 0;
+	size_t sz = 0, total = 0;
+	u64 ccmp_hdr = 0, tmp_key = 0;
+
+	psta = rtw_get_stainfo(pstapriv, get_bssid(pmlmepriv));
+
+	if (psta == NULL) {
+		rtw_warn_on(1);
+		return;
+	}
+
+	prxcache = &psta->sta_recvpriv.rxcache;
+	sz = sizeof(cur_dot11rxiv);
+
+	/* 3 SEC IV * 1 page */
+	rtw_get_sec_iv(adapter, cur_dot11rxiv,
+		       get_my_bssid(&pmlmeinfo->network));
+
+	_rtw_memcpy(pframe, cur_dot11rxiv, sz);
+	*pLength += sz;
+	pframe += sz;
+
+	_rtw_memset(&cur_dot11rxiv, 0, sz);
+
+	if (psecuritypriv->ndisauthtype == Ndis802_11AuthModeWPA2PSK) {
+		id = psecuritypriv->dot118021XGrpKeyid;
+		tid_id = prxcache->last_tid;
+		REMOTE_INFO_CTRL_SET_VALD_EN(cur_dot11rxiv, 0xdd);
+		REMOTE_INFO_CTRL_SET_PTK_EN(cur_dot11rxiv, 1);
+		REMOTE_INFO_CTRL_SET_GTK_EN(cur_dot11rxiv, 1);
+		REMOTE_INFO_CTRL_SET_GTK_IDX(cur_dot11rxiv, id);
+		_rtw_memcpy(pframe, cur_dot11rxiv, sz);
+		*pLength += sz;
+		pframe += sz;
+
+		_rtw_memcpy(pframe, prxcache->iv[tid_id], sz);
+		*pLength += sz;
+		pframe += sz;
+
+		total = sizeof(psecuritypriv->iv_seq);
+		total /= sizeof(psecuritypriv->iv_seq[0]);
+
+		for (i = 0 ; i < total ; i ++) {
+			ccmp_hdr =
+				le64_to_cpu(*(u64*)psecuritypriv->iv_seq[i]);
+			_rtw_memset(&cur_dot11rxiv, 0, sz);
+			if (ccmp_hdr != 0) {
+				tmp_key = i;
+				ccmp_hdr = PN_2_CCMPH(ccmp_hdr, tmp_key);
+				*(u64*)cur_dot11rxiv = cpu_to_le64(ccmp_hdr);
+				_rtw_memcpy(pframe, cur_dot11rxiv, sz);
+			}
+			*pLength += sz;
+			pframe += sz;
+		}
+	}
+}
+
+/*#define DBG_RSVD_PAGE_CFG*/
+#ifdef DBG_RSVD_PAGE_CFG
+#define RSVD_PAGE_CFG(ops, v1, v2, v3)	\
+	RTW_INFO("=== [RSVD][%s]-NeedPage:%d, TotalPageNum:%d TotalPacketLen:%d ===\n",	\
+		ops, v1, v2, v3)
+#endif
+void rtw_hal_set_wow_fw_rsvd_page(_adapter *adapter, u8 *pframe, u16 index,
+		  u8 tx_desc, u32 page_size, u8 *page_num, u32 *total_pkt_len,
+				  RSVDPAGE_LOC *rsvd_page_loc)
+{
+	struct security_priv *psecuritypriv = &adapter->securitypriv;
+	struct mlme_priv *pmlmepriv = &adapter->mlmepriv;
+	struct pwrctrl_priv *pwrctl = adapter_to_pwrctl(adapter);
+	struct mlme_ext_priv	*pmlmeext;
+	struct mlme_ext_info	*pmlmeinfo;
+	u32	ARPLength = 0, GTKLength = 0, PNOLength = 0, ScanInfoLength = 0;
+	u32     SSIDLegnth = 0, ProbeReqLength = 0, ns_len = 0, rc_len = 0;
+	u8 CurtPktPageNum = 0;
+
+#ifdef CONFIG_GTK_OL
+	struct sta_priv *pstapriv = &adapter->stapriv;
+	struct sta_info *psta;
+	struct security_priv *psecpriv = &adapter->securitypriv;
+	u8 kek[RTW_KEK_LEN];
+	u8 kck[RTW_KCK_LEN];
+#endif /* CONFIG_GTK_OL */
+#ifdef CONFIG_PNO_SUPPORT
+	int pno_index;
+	u8 ssid_num;
+#endif /* CONFIG_PNO_SUPPORT */
+
+	pmlmeext = &adapter->mlmeextpriv;
+	pmlmeinfo = &pmlmeext->mlmext_info;
+
+	if (pwrctl->wowlan_pno_enable == _FALSE) {
+		/* ARP RSP * 1 page */
+
+		rsvd_page_loc->LocArpRsp = *page_num;
+
+		RTW_INFO("LocArpRsp: %d\n", rsvd_page_loc->LocArpRsp);
+
+		rtw_hal_construct_ARPRsp(adapter, &pframe[index],
+					 &ARPLength, pmlmeinfo->ip_addr);
+
+		rtw_hal_fill_fake_txdesc(adapter,
+					 &pframe[index - tx_desc],
+					 ARPLength, _FALSE, _FALSE, _TRUE);
+
+		CurtPktPageNum = (u8)PageNum(tx_desc + ARPLength, page_size);
+
+		*page_num += CurtPktPageNum;
+
+		index += (CurtPktPageNum * page_size);
+		#ifdef DBG_RSVD_PAGE_CFG
+		RSVD_PAGE_CFG("WOW-ARPRsp", CurtPktPageNum, *page_num, 0);
+		#endif
+
+#ifdef CONFIG_IPV6
+		/* 2 NS offload and NDP Info*/
+		if (pwrctl->wowlan_ns_offload_en == _TRUE) {
+			rsvd_page_loc->LocNbrAdv = *page_num;
+			RTW_INFO("LocNbrAdv: %d\n", rsvd_page_loc->LocNbrAdv);
+			rtw_hal_construct_na_message(adapter,
+						     &pframe[index], &ns_len);
+			rtw_hal_fill_fake_txdesc(adapter,
+						 &pframe[index - tx_desc],
+						 ns_len, _FALSE,
+						 _FALSE, _TRUE);
+			CurtPktPageNum = (u8)PageNum(tx_desc + ns_len,
+						      page_size);
+			*page_num += CurtPktPageNum;
+			index += (CurtPktPageNum * page_size);
+			#ifdef DBG_RSVD_PAGE_CFG
+			RSVD_PAGE_CFG("WOW-NbrAdv", CurtPktPageNum, *page_num, 0);
+			#endif
+
+			rsvd_page_loc->LocNDPInfo = *page_num;
+			RTW_INFO("LocNDPInfo: %d\n",
+				 rsvd_page_loc->LocNDPInfo);
+
+			rtw_hal_construct_ndp_info(adapter,
+						   &pframe[index - tx_desc],
+						   &ns_len);
+			CurtPktPageNum =
+				(u8)PageNum(tx_desc + ns_len, page_size);
+			*page_num += CurtPktPageNum;
+			index += (CurtPktPageNum * page_size);
+			#ifdef DBG_RSVD_PAGE_CFG
+			RSVD_PAGE_CFG("WOW-NDPInfo", CurtPktPageNum, *page_num, 0);
+			#endif
+
+		}
+#endif /*CONFIG_IPV6*/
+		/* 3 Remote Control Info. * 1 page */
+		rsvd_page_loc->LocRemoteCtrlInfo = *page_num;
+		RTW_INFO("LocRemoteCtrlInfo: %d\n", rsvd_page_loc->LocRemoteCtrlInfo);
+		rtw_hal_construct_remote_control_info(adapter,
+						      &pframe[index - tx_desc],
+						      &rc_len);
+		CurtPktPageNum = (u8)PageNum(rc_len, page_size);
+		*page_num += CurtPktPageNum;
+		*total_pkt_len = index + rc_len;
+		#ifdef DBG_RSVD_PAGE_CFG
+		RSVD_PAGE_CFG("WOW-RCI", CurtPktPageNum, *page_num, *total_pkt_len);
+		#endif
+#ifdef CONFIG_GTK_OL
+		index += (CurtPktPageNum * page_size);
+
+		/* if the ap staion info. exists, get the kek, kck from staion info. */
+		psta = rtw_get_stainfo(pstapriv, get_bssid(pmlmepriv));
+		if (psta == NULL) {
+			_rtw_memset(kek, 0, RTW_KEK_LEN);
+			_rtw_memset(kck, 0, RTW_KCK_LEN);
+			RTW_INFO("%s, KEK, KCK download rsvd page all zero\n",
+				 __func__);
+		} else {
+			_rtw_memcpy(kek, psta->kek, RTW_KEK_LEN);
+			_rtw_memcpy(kck, psta->kck, RTW_KCK_LEN);
+		}
+
+		/* 3 KEK, KCK */
+		rsvd_page_loc->LocGTKInfo = *page_num;
+		RTW_INFO("LocGTKInfo: %d\n", rsvd_page_loc->LocGTKInfo);
+
+		if (IS_HARDWARE_TYPE_8188E(adapter) || IS_HARDWARE_TYPE_8812(adapter)) {
+			struct security_priv *psecpriv = NULL;
+
+			psecpriv = &adapter->securitypriv;
+			_rtw_memcpy(pframe + index - tx_desc,
+				    &psecpriv->dot11PrivacyAlgrthm, 1);
+			_rtw_memcpy(pframe + index - tx_desc + 1,
+				    &psecpriv->dot118021XGrpPrivacy, 1);
+			_rtw_memcpy(pframe + index - tx_desc + 2,
+				    kck, RTW_KCK_LEN);
+			_rtw_memcpy(pframe + index - tx_desc + 2 + RTW_KCK_LEN,
+				    kek, RTW_KEK_LEN);
+			CurtPktPageNum = (u8)PageNum(tx_desc + 2 + RTW_KCK_LEN + RTW_KEK_LEN, page_size);
+		} else {
+
+			_rtw_memcpy(pframe + index - tx_desc, kck, RTW_KCK_LEN);
+			_rtw_memcpy(pframe + index - tx_desc + RTW_KCK_LEN,
+				    kek, RTW_KEK_LEN);
+			GTKLength = tx_desc + RTW_KCK_LEN + RTW_KEK_LEN;
+
+			if (psta != NULL &&
+				psecuritypriv->dot118021XGrpPrivacy == _TKIP_) {
+				_rtw_memcpy(pframe + index - tx_desc + 56,
+					&psta->dot11tkiptxmickey, RTW_TKIP_MIC_LEN);
+				GTKLength += RTW_TKIP_MIC_LEN;
+			}
+			CurtPktPageNum = (u8)PageNum(GTKLength, page_size);
+		}
+#if 0
+		{
+			int i;
+			printk("\ntoFW KCK: ");
+			for (i = 0; i < 16; i++)
+				printk(" %02x ", kck[i]);
+			printk("\ntoFW KEK: ");
+			for (i = 0; i < 16; i++)
+				printk(" %02x ", kek[i]);
+			printk("\n");
+		}
+
+		RTW_INFO("%s(): HW_VAR_SET_TX_CMD: KEK KCK %p %d\n",
+			 __FUNCTION__, &pframe[index - tx_desc],
+			 (tx_desc + RTW_KCK_LEN + RTW_KEK_LEN));
+#endif
+
+		*page_num += CurtPktPageNum;
+
+		index += (CurtPktPageNum * page_size);
+		#ifdef DBG_RSVD_PAGE_CFG
+		RSVD_PAGE_CFG("WOW-GTKInfo", CurtPktPageNum, *page_num, 0);
+		#endif
+
+		/* 3 GTK Response */
+		rsvd_page_loc->LocGTKRsp = *page_num;
+		RTW_INFO("LocGTKRsp: %d\n", rsvd_page_loc->LocGTKRsp);
+		rtw_hal_construct_GTKRsp(adapter, &pframe[index], &GTKLength);
+
+		rtw_hal_fill_fake_txdesc(adapter, &pframe[index - tx_desc],
+					 GTKLength, _FALSE, _FALSE, _TRUE);
+#if 0
+		{
+			int gj;
+			printk("123GTK pkt=>\n");
+			for (gj = 0; gj < GTKLength + tx_desc; gj++) {
+				printk(" %02x ", pframe[index - tx_desc + gj]);
+				if ((gj + 1) % 16 == 0)
+					printk("\n");
+			}
+			printk(" <=end\n");
+		}
+
+		RTW_INFO("%s(): HW_VAR_SET_TX_CMD: GTK RSP %p %d\n",
+			 __FUNCTION__, &pframe[index - tx_desc],
+			 (tx_desc + GTKLength));
+#endif
+
+		CurtPktPageNum = (u8)PageNum(tx_desc + GTKLength, page_size);
+
+		*page_num += CurtPktPageNum;
+
+		index += (CurtPktPageNum * page_size);
+		#ifdef DBG_RSVD_PAGE_CFG
+		RSVD_PAGE_CFG("WOW-GTKRsp", CurtPktPageNum, *page_num, 0);
+		#endif
+
+		/* below page is empty for GTK extension memory */
+		/* 3(11) GTK EXT MEM */
+		rsvd_page_loc->LocGTKEXTMEM = *page_num;
+		RTW_INFO("LocGTKEXTMEM: %d\n", rsvd_page_loc->LocGTKEXTMEM);
+		CurtPktPageNum = 2;
+
+		if (page_size >= 256)
+			CurtPktPageNum = 1;
+
+		*page_num += CurtPktPageNum;
+		/* extension memory for FW */
+		*total_pkt_len = index + (page_size * CurtPktPageNum);
+		#ifdef DBG_RSVD_PAGE_CFG
+		RSVD_PAGE_CFG("WOW-GTKEXTMEM", CurtPktPageNum, *page_num, *total_pkt_len);
+		#endif
+#endif /* CONFIG_GTK_OL */
+
+		index += (CurtPktPageNum * page_size);
+
+		/*Reserve 1 page for AOAC report*/
+		rsvd_page_loc->LocAOACReport = *page_num;
+		RTW_INFO("LocAOACReport: %d\n", rsvd_page_loc->LocAOACReport);
+		*page_num += 1;
+		*total_pkt_len = index + (page_size * 1);
+		#ifdef DBG_RSVD_PAGE_CFG
+		RSVD_PAGE_CFG("WOW-AOAC", 1, *page_num, *total_pkt_len);
+		#endif
+	} else {
+#ifdef CONFIG_PNO_SUPPORT
+		if (pwrctl->wowlan_in_resume == _FALSE &&
+		    pwrctl->pno_inited == _TRUE) {
+
+			/* Broadcast Probe Request */
+			rsvd_page_loc->LocProbePacket = *page_num;
+
+			RTW_INFO("loc_probe_req: %d\n",
+				 rsvd_page_loc->LocProbePacket);
+
+			rtw_hal_construct_ProbeReq(
+				adapter,
+				&pframe[index],
+				&ProbeReqLength,
+				NULL);
+
+			rtw_hal_fill_fake_txdesc(adapter,
+						 &pframe[index - tx_desc],
+				 ProbeReqLength, _FALSE, _FALSE, _FALSE);
+
+			CurtPktPageNum =
+				(u8)PageNum(tx_desc + ProbeReqLength, page_size);
+
+			*page_num += CurtPktPageNum;
+
+			index += (CurtPktPageNum * page_size);
+			#ifdef DBG_RSVD_PAGE_CFG
+			RSVD_PAGE_CFG("WOW-ProbeReq", CurtPktPageNum, *page_num, 0);
+			#endif
+
+			/* Hidden SSID Probe Request */
+			ssid_num = pwrctl->pnlo_info->hidden_ssid_num;
+
+			for (pno_index = 0 ; pno_index < ssid_num ; pno_index++) {
+				pwrctl->pnlo_info->loc_probe_req[pno_index] =
+					*page_num;
+
+				rtw_hal_construct_ProbeReq(
+					adapter,
+					&pframe[index],
+					&ProbeReqLength,
+					&pwrctl->pno_ssid_list->node[pno_index]);
+
+				rtw_hal_fill_fake_txdesc(adapter,
+						 &pframe[index - tx_desc],
+					ProbeReqLength, _FALSE, _FALSE, _FALSE);
+
+				CurtPktPageNum =
+					(u8)PageNum(tx_desc + ProbeReqLength, page_size);
+
+				*page_num += CurtPktPageNum;
+
+				index += (CurtPktPageNum * page_size);
+				#ifdef DBG_RSVD_PAGE_CFG
+				RSVD_PAGE_CFG("WOW-ProbeReq", CurtPktPageNum, *page_num, 0);
+				#endif
+			}
+
+			/* PNO INFO Page */
+			rsvd_page_loc->LocPNOInfo = *page_num;
+			RTW_INFO("LocPNOInfo: %d\n", rsvd_page_loc->LocPNOInfo);
+			rtw_hal_construct_PNO_info(adapter,
+						   &pframe[index - tx_desc],
+						   &PNOLength);
+
+			CurtPktPageNum = (u8)PageNum(PNOLength, page_size);
+			*page_num += CurtPktPageNum;
+			index += (CurtPktPageNum * page_size);
+			#ifdef DBG_RSVD_PAGE_CFG
+			RSVD_PAGE_CFG("WOW-PNOInfo", CurtPktPageNum, *page_num, 0);
+			#endif
+
+			/* Scan Info Page */
+			rsvd_page_loc->LocScanInfo = *page_num;
+			RTW_INFO("LocScanInfo: %d\n", rsvd_page_loc->LocScanInfo);
+			rtw_hal_construct_scan_info(adapter,
+						    &pframe[index - tx_desc],
+						    &ScanInfoLength);
+
+			CurtPktPageNum = (u8)PageNum(ScanInfoLength, page_size);
+			*page_num += CurtPktPageNum;
+			*total_pkt_len = index + ScanInfoLength;
+			index += (CurtPktPageNum * page_size);
+			#ifdef DBG_RSVD_PAGE_CFG
+			RSVD_PAGE_CFG("WOW-ScanInfo", CurtPktPageNum, *page_num, *total_pkt_len);
+			#endif
+		}
+#endif /* CONFIG_PNO_SUPPORT */
+	}
+}
+
+static void rtw_hal_gate_bb(_adapter *adapter, bool stop)
+{
+	struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(adapter);
+	u8 i = 0, val8 = 0, empty = _FAIL;
+	u16 val16 = 0;
+
+	if (stop) {
+		/* checking TX queue status */
+		for (i = 0 ; i < 5 ; i++) {
+			rtw_hal_get_hwreg(adapter, HW_VAR_CHK_MGQ_CPU_EMPTY, &empty);
+			if (empty) {
+				break;
+			} else {
+				RTW_WARN("%s: MGQ_CPU is busy(%d)!\n",
+					 __func__, i);
+				rtw_mdelay_os(10);
+			}
+		}
+
+		if (val8 == 5)
+			RTW_ERR("%s: Polling MGQ_CPU empty fail!\n", __func__);
+
+		/* Pause TX*/
+		pwrpriv->wowlan_txpause_status = rtw_read8(adapter, REG_TXPAUSE);
+		rtw_write8(adapter, REG_TXPAUSE, 0xff);
+		val8 = rtw_read8(adapter, REG_SYS_FUNC_EN);
+		val8 &= ~BIT(0);
+		rtw_write8(adapter, REG_SYS_FUNC_EN, val8);
+		RTW_INFO("%s: BB gated: 0x%02x, store TXPAUSE: %02x\n",
+			 __func__,
+			 rtw_read8(adapter, REG_SYS_FUNC_EN),
+			 pwrpriv->wowlan_txpause_status);
+	} else {
+		val8 = rtw_read8(adapter, REG_SYS_FUNC_EN);
+		val8 |= BIT(0);
+		rtw_write8(adapter, REG_SYS_FUNC_EN, val8);
+		RTW_INFO("%s: BB release: 0x%02x, recover TXPAUSE:%02x\n",
+			 __func__, rtw_read8(adapter, REG_SYS_FUNC_EN),
+			 pwrpriv->wowlan_txpause_status);
+		/* release TX*/
+		rtw_write8(adapter, REG_TXPAUSE, pwrpriv->wowlan_txpause_status);
+	}
+}
+
+static void rtw_hal_reset_mac_rx(_adapter *adapter)
+{
+	u8 val8 = 0;
+	/* Set REG_CR bit1, bit3, bit7 to 0*/
+	val8 = rtw_read8(adapter, REG_CR);
+	val8 &= 0x75;
+	rtw_write8(adapter, REG_CR, val8);
+	val8 = rtw_read8(adapter, REG_CR);
+	/* Set REG_CR bit1, bit3, bit7 to 1*/
+	val8 |= 0x8a;
+	rtw_write8(adapter, REG_CR, val8);
+	RTW_INFO("0x%04x: %02x\n", REG_CR, rtw_read8(adapter, REG_CR));
+}
+
+static u8 rtw_hal_wow_pattern_generate(_adapter *adapter, u8 idx, struct rtl_wow_pattern *pwow_pattern)
+{
+	struct pwrctrl_priv *pwrctl = adapter_to_pwrctl(adapter);
+	 u8 *pattern;
+	 u8 len = 0;
+	 u8 *mask;
+
+	u8 mask_hw[MAX_WKFM_SIZE] = {0};
+	u8 content[MAX_WKFM_PATTERN_SIZE] = {0};
+	u8 broadcast_addr[6] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
+	u8 multicast_addr1[2] = {0x33, 0x33};
+	u8 multicast_addr2[3] = {0x01, 0x00, 0x5e};
+	u8 mask_len = 0;
+	u8 mac_addr[ETH_ALEN] = {0};
+	u16 count = 0;
+	int i, j;
+
+	if (pwrctl->wowlan_pattern_idx > MAX_WKFM_CAM_NUM) {
+		RTW_INFO("%s pattern_idx is more than MAX_FMC_NUM: %d\n",
+			 __func__, MAX_WKFM_CAM_NUM);
+		return _FAIL;
+	}
+
+	pattern = pwrctl->patterns[idx].content;
+	len = pwrctl->patterns[idx].len;
+	mask = pwrctl->patterns[idx].mask;
+
+	_rtw_memcpy(mac_addr, adapter_mac_addr(adapter), ETH_ALEN);
+	_rtw_memset(pwow_pattern, 0, sizeof(struct rtl_wow_pattern));
+
+	mask_len = DIV_ROUND_UP(len, 8);
+
+	/* 1. setup A1 table */
+	if (memcmp(pattern, broadcast_addr, ETH_ALEN) == 0)
+		pwow_pattern->type = PATTERN_BROADCAST;
+	else if (memcmp(pattern, multicast_addr1, 2) == 0)
+		pwow_pattern->type = PATTERN_MULTICAST;
+	else if (memcmp(pattern, multicast_addr2, 3) == 0)
+		pwow_pattern->type = PATTERN_MULTICAST;
+	else if (memcmp(pattern, mac_addr, ETH_ALEN) == 0)
+		pwow_pattern->type = PATTERN_UNICAST;
+	else
+		pwow_pattern->type = PATTERN_INVALID;
+
+	/* translate mask from os to mask for hw */
+
+	/******************************************************************************
+	 * pattern from OS uses 'ethenet frame', like this:
+
+		|    6   |    6   |   2  |     20    |  Variable  |  4  |
+		|--------+--------+------+-----------+------------+-----|
+		|    802.3 Mac Header    | IP Header | TCP Packet | FCS |
+		|   DA   |   SA   | Type |
+
+	 * BUT, packet catched by our HW is in '802.11 frame', begin from LLC,
+
+		|     24 or 30      |    6   |   2  |     20    |  Variable  |  4  |
+		|-------------------+--------+------+-----------+------------+-----|
+		| 802.11 MAC Header |       LLC     | IP Header | TCP Packet | FCS |
+				    | Others | Tpye |
+
+	 * Therefore, we need translate mask_from_OS to mask_to_hw.
+	 * We should left-shift mask by 6 bits, then set the new bit[0~5] = 0,
+	 * because new mask[0~5] means 'SA', but our HW packet begins from LLC,
+	 * bit[0~5] corresponds to first 6 Bytes in LLC, they just don't match.
+	 ******************************************************************************/
+	/* Shift 6 bits */
+	for (i = 0; i < mask_len - 1; i++) {
+		mask_hw[i] = mask[i] >> 6;
+		mask_hw[i] |= (mask[i + 1] & 0x3F) << 2;
+	}
+
+	mask_hw[i] = (mask[i] >> 6) & 0x3F;
+	/* Set bit 0-5 to zero */
+	mask_hw[0] &= 0xC0;
+
+	for (i = 0; i < (MAX_WKFM_SIZE / 4); i++) {
+		pwow_pattern->mask[i] = mask_hw[i * 4];
+		pwow_pattern->mask[i] |= (mask_hw[i * 4 + 1] << 8);
+		pwow_pattern->mask[i] |= (mask_hw[i * 4 + 2] << 16);
+		pwow_pattern->mask[i] |= (mask_hw[i * 4 + 3] << 24);
+	}
+
+	/* To get the wake up pattern from the mask.
+	 * We do not count first 12 bits which means
+	 * DA[6] and SA[6] in the pattern to match HW design. */
+	count = 0;
+	for (i = 12; i < len; i++) {
+		if ((mask[i / 8] >> (i % 8)) & 0x01) {
+			content[count] = pattern[i];
+			count++;
+		}
+	}
+
+	pwow_pattern->crc = rtw_calc_crc(content, count);
+
+	if (pwow_pattern->crc != 0) {
+		if (pwow_pattern->type == PATTERN_INVALID)
+			pwow_pattern->type = PATTERN_VALID;
+	}
+
+	return _SUCCESS;
+}
+
+#ifndef CONFIG_WOW_PATTERN_HW_CAM
+static void rtw_hal_set_wow_rxff_boundary(_adapter *adapter, bool wow_mode)
+{
+	u8 val8 = 0;
+	u16 rxff_bndy = 0;
+	u32 rx_dma_buff_sz = 0;
+
+	val8 = rtw_read8(adapter, REG_FIFOPAGE + 3);
+	if (val8 != 0)
+		RTW_INFO("%s:[%04x]some PKTs in TXPKTBUF\n",
+			 __func__, (REG_FIFOPAGE + 3));
+
+	rtw_hal_reset_mac_rx(adapter);
+
+	if (wow_mode) {
+		rtw_hal_get_def_var(adapter, HAL_DEF_RX_DMA_SZ_WOW,
+				    (u8 *)&rx_dma_buff_sz);
+		rxff_bndy = rx_dma_buff_sz - 1;
+
+		rtw_write16(adapter, (REG_TRXFF_BNDY + 2), rxff_bndy);
+		RTW_INFO("%s: wow mode, 0x%04x: 0x%04x\n", __func__,
+			 REG_TRXFF_BNDY + 2,
+			 rtw_read16(adapter, (REG_TRXFF_BNDY + 2)));
+	} else {
+		rtw_hal_get_def_var(adapter, HAL_DEF_RX_DMA_SZ,
+				    (u8 *)&rx_dma_buff_sz);
+		rxff_bndy = rx_dma_buff_sz - 1;
+		rtw_write16(adapter, (REG_TRXFF_BNDY + 2), rxff_bndy);
+		RTW_INFO("%s: normal mode, 0x%04x: 0x%04x\n", __func__,
+			 REG_TRXFF_BNDY + 2,
+			 rtw_read16(adapter, (REG_TRXFF_BNDY + 2)));
+	}
+}
+
+bool rtw_read_from_frame_mask(_adapter *adapter, u8 idx)
+{
+	u32 data_l = 0, data_h = 0, rx_dma_buff_sz = 0, page_sz = 0;
+	u16 offset, rx_buf_ptr = 0;
+	u16 cam_start_offset = 0;
+	u16 ctrl_l = 0, ctrl_h = 0;
+	u8 count = 0, tmp = 0;
+	int i = 0;
+	bool res = _TRUE;
+
+	if (idx > MAX_WKFM_CAM_NUM) {
+		RTW_INFO("[Error]: %s, pattern index is out of range\n",
+			 __func__);
+		return _FALSE;
+	}
+
+	rtw_hal_get_def_var(adapter, HAL_DEF_RX_DMA_SZ_WOW,
+			    (u8 *)&rx_dma_buff_sz);
+
+	if (rx_dma_buff_sz == 0) {
+		RTW_INFO("[Error]: %s, rx_dma_buff_sz is 0!!\n", __func__);
+		return _FALSE;
+	}
+
+	rtw_hal_get_def_var(adapter, HAL_DEF_RX_PAGE_SIZE, (u8 *)&page_sz);
+
+	if (page_sz == 0) {
+		RTW_INFO("[Error]: %s, page_sz is 0!!\n", __func__);
+		return _FALSE;
+	}
+
+	offset = (u16)PageNum(rx_dma_buff_sz, page_sz);
+	cam_start_offset = offset * page_sz;
+
+	ctrl_l = 0x0;
+	ctrl_h = 0x0;
+
+	/* Enable RX packet buffer access */
+	rtw_write8(adapter, REG_PKT_BUFF_ACCESS_CTRL, RXPKT_BUF_SELECT);
+
+	/* Read the WKFM CAM */
+	for (i = 0; i < (WKFMCAM_ADDR_NUM / 2); i++) {
+		/*
+		 * Set Rx packet buffer offset.
+		 * RxBufer pointer increases 1, we can access 8 bytes in Rx packet buffer.
+		 * CAM start offset (unit: 1 byte) =  Index*WKFMCAM_SIZE
+		 * RxBufer pointer addr = (CAM start offset + per entry offset of a WKFMCAM)/8
+		 * * Index: The index of the wake up frame mask
+		 * * WKFMCAM_SIZE: the total size of one WKFM CAM
+		 * * per entry offset of a WKFM CAM: Addr i * 4 bytes
+		 */
+		rx_buf_ptr =
+			(cam_start_offset + idx * WKFMCAM_SIZE + i * 8) >> 3;
+		rtw_write16(adapter, REG_PKTBUF_DBG_CTRL, rx_buf_ptr);
+
+		rtw_write16(adapter, REG_RXPKTBUF_CTRL, ctrl_l);
+		data_l = rtw_read32(adapter, REG_PKTBUF_DBG_DATA_L);
+		data_h = rtw_read32(adapter, REG_PKTBUF_DBG_DATA_H);
+
+		RTW_INFO("[%d]: %08x %08x\n", i, data_h, data_l);
+
+		count = 0;
+
+		do {
+			tmp = rtw_read8(adapter, REG_RXPKTBUF_CTRL);
+			rtw_udelay_os(2);
+			count++;
+		} while (!tmp && count < 100);
+
+		if (count >= 100) {
+			RTW_INFO("%s count:%d\n", __func__, count);
+			res = _FALSE;
+		}
+	}
+
+	/* Disable RX packet buffer access */
+	rtw_write8(adapter, REG_PKT_BUFF_ACCESS_CTRL,
+		   DISABLE_TRXPKT_BUF_ACCESS);
+	return res;
+}
+
+bool rtw_write_to_frame_mask(_adapter *adapter, u8 idx,
+			     struct  rtl_wow_pattern *context)
+{
+	u32 data = 0, rx_dma_buff_sz = 0, page_sz = 0;
+	u16 offset, rx_buf_ptr = 0;
+	u16 cam_start_offset = 0;
+	u16 ctrl_l = 0, ctrl_h = 0;
+	u8 count = 0, tmp = 0;
+	int res = 0, i = 0;
+
+	if (idx > MAX_WKFM_CAM_NUM) {
+		RTW_INFO("[Error]: %s, pattern index is out of range\n",
+			 __func__);
+		return _FALSE;
+	}
+
+	rtw_hal_get_def_var(adapter, HAL_DEF_RX_DMA_SZ_WOW,
+			    (u8 *)&rx_dma_buff_sz);
+
+	if (rx_dma_buff_sz == 0) {
+		RTW_INFO("[Error]: %s, rx_dma_buff_sz is 0!!\n", __func__);
+		return _FALSE;
+	}
+
+	rtw_hal_get_def_var(adapter, HAL_DEF_RX_PAGE_SIZE, (u8 *)&page_sz);
+
+	if (page_sz == 0) {
+		RTW_INFO("[Error]: %s, page_sz is 0!!\n", __func__);
+		return _FALSE;
+	}
+
+	offset = (u16)PageNum(rx_dma_buff_sz, page_sz);
+
+	cam_start_offset = offset * page_sz;
+
+	if (IS_HARDWARE_TYPE_8188E(adapter)) {
+		ctrl_l = 0x0001;
+		ctrl_h = 0x0001;
+	} else {
+		ctrl_l = 0x0f01;
+		ctrl_h = 0xf001;
+	}
+
+	/* Enable RX packet buffer access */
+	rtw_write8(adapter, REG_PKT_BUFF_ACCESS_CTRL, RXPKT_BUF_SELECT);
+
+	/* Write the WKFM CAM */
+	for (i = 0; i < WKFMCAM_ADDR_NUM; i++) {
+		/*
+		 * Set Rx packet buffer offset.
+		 * RxBufer pointer increases 1, we can access 8 bytes in Rx packet buffer.
+		 * CAM start offset (unit: 1 byte) =  Index*WKFMCAM_SIZE
+		 * RxBufer pointer addr = (CAM start offset + per entry offset of a WKFMCAM)/8
+		 * * Index: The index of the wake up frame mask
+		 * * WKFMCAM_SIZE: the total size of one WKFM CAM
+		 * * per entry offset of a WKFM CAM: Addr i * 4 bytes
+		 */
+		rx_buf_ptr =
+			(cam_start_offset + idx * WKFMCAM_SIZE + i * 4) >> 3;
+		rtw_write16(adapter, REG_PKTBUF_DBG_CTRL, rx_buf_ptr);
+
+		if (i == 0) {
+			if (context->type == PATTERN_VALID)
+				data = BIT(31);
+			else if (context->type == PATTERN_BROADCAST)
+				data = BIT(31) | BIT(26);
+			else if (context->type == PATTERN_MULTICAST)
+				data = BIT(31) | BIT(25);
+			else if (context->type == PATTERN_UNICAST)
+				data = BIT(31) | BIT(24);
+
+			if (context->crc != 0)
+				data |= context->crc;
+
+			rtw_write32(adapter, REG_PKTBUF_DBG_DATA_L, data);
+			rtw_write16(adapter, REG_RXPKTBUF_CTRL, ctrl_l);
+		} else if (i == 1) {
+			data = 0;
+			rtw_write32(adapter, REG_PKTBUF_DBG_DATA_H, data);
+			rtw_write16(adapter, REG_RXPKTBUF_CTRL, ctrl_h);
+		} else if (i == 2 || i == 4) {
+			data = context->mask[i - 2];
+			rtw_write32(adapter, REG_PKTBUF_DBG_DATA_L, data);
+			/* write to RX packet buffer*/
+			rtw_write16(adapter, REG_RXPKTBUF_CTRL, ctrl_l);
+		} else if (i == 3 || i == 5) {
+			data = context->mask[i - 2];
+			rtw_write32(adapter, REG_PKTBUF_DBG_DATA_H, data);
+			/* write to RX packet buffer*/
+			rtw_write16(adapter, REG_RXPKTBUF_CTRL, ctrl_h);
+		}
+
+		count = 0;
+		do {
+			tmp = rtw_read8(adapter, REG_RXPKTBUF_CTRL);
+			rtw_udelay_os(2);
+			count++;
+		} while (tmp && count < 100);
+
+		if (count >= 100)
+			res = _FALSE;
+		else
+			res = _TRUE;
+	}
+
+	/* Disable RX packet buffer access */
+	rtw_write8(adapter, REG_PKT_BUFF_ACCESS_CTRL,
+		   DISABLE_TRXPKT_BUF_ACCESS);
+
+	return res;
+}
+void rtw_clean_pattern(_adapter *adapter)
+{
+	struct pwrctrl_priv *pwrctl = adapter_to_pwrctl(adapter);
+	struct rtl_wow_pattern zero_pattern;
+	int i = 0;
+
+	_rtw_memset(&zero_pattern, 0, sizeof(struct rtl_wow_pattern));
+
+	zero_pattern.type = PATTERN_INVALID;
+
+	for (i = 0; i < MAX_WKFM_CAM_NUM; i++)
+		rtw_write_to_frame_mask(adapter, i, &zero_pattern);
+
+	rtw_write8(adapter, REG_WKFMCAM_NUM, 0);
+}
+static int rtw_hal_set_pattern(_adapter *adapter, u8 *pattern,
+			       u8 len, u8 *mask, u8 idx)
+{
+	struct pwrctrl_priv *pwrctl = adapter_to_pwrctl(adapter);
+	struct mlme_ext_priv *pmlmeext = NULL;
+	struct mlme_ext_info *pmlmeinfo = NULL;
+	struct rtl_wow_pattern wow_pattern;
+	u8 mask_hw[MAX_WKFM_SIZE] = {0};
+	u8 content[MAX_WKFM_PATTERN_SIZE] = {0};
+	u8 broadcast_addr[6] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
+	u8 multicast_addr1[2] = {0x33, 0x33};
+	u8 multicast_addr2[3] = {0x01, 0x00, 0x5e};
+	u8 res = _FALSE, index = 0, mask_len = 0;
+	u8 mac_addr[ETH_ALEN] = {0};
+	u16 count = 0;
+	int i, j;
+
+	if (pwrctl->wowlan_pattern_idx > MAX_WKFM_CAM_NUM) {
+		RTW_INFO("%s pattern_idx is more than MAX_FMC_NUM: %d\n",
+			 __func__, MAX_WKFM_CAM_NUM);
+		return _FALSE;
+	}
+
+	pmlmeext = &adapter->mlmeextpriv;
+	pmlmeinfo = &pmlmeext->mlmext_info;
+	_rtw_memcpy(mac_addr, adapter_mac_addr(adapter), ETH_ALEN);
+	_rtw_memset(&wow_pattern, 0, sizeof(struct rtl_wow_pattern));
+
+	mask_len = DIV_ROUND_UP(len, 8);
+
+	/* 1. setup A1 table */
+	if (memcmp(pattern, broadcast_addr, ETH_ALEN) == 0)
+		wow_pattern.type = PATTERN_BROADCAST;
+	else if (memcmp(pattern, multicast_addr1, 2) == 0)
+		wow_pattern.type = PATTERN_MULTICAST;
+	else if (memcmp(pattern, multicast_addr2, 3) == 0)
+		wow_pattern.type = PATTERN_MULTICAST;
+	else if (memcmp(pattern, mac_addr, ETH_ALEN) == 0)
+		wow_pattern.type = PATTERN_UNICAST;
+	else
+		wow_pattern.type = PATTERN_INVALID;
+
+	/* translate mask from os to mask for hw */
+
+/******************************************************************************
+ * pattern from OS uses 'ethenet frame', like this:
+
+	|    6   |    6   |   2  |     20    |  Variable  |  4  |
+	|--------+--------+------+-----------+------------+-----|
+	|    802.3 Mac Header    | IP Header | TCP Packet | FCS |
+	|   DA   |   SA   | Type |
+
+ * BUT, packet catched by our HW is in '802.11 frame', begin from LLC,
+
+	|     24 or 30      |    6   |   2  |     20    |  Variable  |  4  |
+	|-------------------+--------+------+-----------+------------+-----|
+	| 802.11 MAC Header |       LLC     | IP Header | TCP Packet | FCS |
+			    | Others | Tpye |
+
+ * Therefore, we need translate mask_from_OS to mask_to_hw.
+ * We should left-shift mask by 6 bits, then set the new bit[0~5] = 0,
+ * because new mask[0~5] means 'SA', but our HW packet begins from LLC,
+ * bit[0~5] corresponds to first 6 Bytes in LLC, they just don't match.
+ ******************************************************************************/
+	/* Shift 6 bits */
+	for (i = 0; i < mask_len - 1; i++) {
+		mask_hw[i] = mask[i] >> 6;
+		mask_hw[i] |= (mask[i + 1] & 0x3F) << 2;
+	}
+
+	mask_hw[i] = (mask[i] >> 6) & 0x3F;
+	/* Set bit 0-5 to zero */
+	mask_hw[0] &= 0xC0;
+
+	for (i = 0; i < (MAX_WKFM_SIZE / 4); i++) {
+		wow_pattern.mask[i] = mask_hw[i * 4];
+		wow_pattern.mask[i] |= (mask_hw[i * 4 + 1] << 8);
+		wow_pattern.mask[i] |= (mask_hw[i * 4 + 2] << 16);
+		wow_pattern.mask[i] |= (mask_hw[i * 4 + 3] << 24);
+	}
+
+	/* To get the wake up pattern from the mask.
+	 * We do not count first 12 bits which means
+	 * DA[6] and SA[6] in the pattern to match HW design. */
+	count = 0;
+	for (i = 12; i < len; i++) {
+		if ((mask[i / 8] >> (i % 8)) & 0x01) {
+			content[count] = pattern[i];
+			count++;
+		}
+	}
+
+	wow_pattern.crc = rtw_calc_crc(content, count);
+
+	if (wow_pattern.crc != 0) {
+		if (wow_pattern.type == PATTERN_INVALID)
+			wow_pattern.type = PATTERN_VALID;
+	}
+
+	index = idx;
+
+	if (!pwrctl->bInSuspend)
+		index += 2;
+
+	/* write pattern */
+	res = rtw_write_to_frame_mask(adapter, index, &wow_pattern);
+
+	if (res == _FALSE)
+		RTW_INFO("%s: ERROR!! idx: %d write_to_frame_mask_cam fail\n",
+			 __func__, idx);
+
+	return res;
+}
+void rtw_fill_pattern(_adapter *adapter)
+{
+	int i = 0, total = 0, index;
+	struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(adapter);
+	struct rtl_wow_pattern wow_pattern;
+
+	total = pwrpriv->wowlan_pattern_idx;
+
+	if (total > MAX_WKFM_CAM_NUM)
+		total = MAX_WKFM_CAM_NUM;
+
+	for (i = 0 ; i < total ; i++) {
+		if (_SUCCESS == rtw_hal_wow_pattern_generate(adapter, i, &wow_pattern)) {
+
+			index = i;
+			if (!pwrpriv->bInSuspend)
+				index += 2;
+
+			if (rtw_write_to_frame_mask(adapter, index, &wow_pattern) == _FALSE)
+				RTW_INFO("%s: ERROR!! idx: %d write_to_frame_mask_cam fail\n", __func__, i);
+		}
+
+	}
+	rtw_write8(adapter, REG_WKFMCAM_NUM, total);
+
+}
+
+#else /*CONFIG_WOW_PATTERN_HW_CAM*/
+
+#define WOW_CAM_ACCESS_TIMEOUT_MS	200
+#define WOW_VALID_BIT	BIT31
+#define WOW_BC_BIT		BIT26
+#define WOW_MC_BIT		BIT25
+#define WOW_UC_BIT		BIT24
+
+static u32 _rtw_wow_pattern_read_cam(_adapter *adapter, u8 addr)
+{
+	struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(adapter);
+	_mutex *mutex = &pwrpriv->wowlan_pattern_cam_mutex;
+
+	u32 rdata = 0;
+	u32 cnt = 0;
+	systime start = 0;
+	u8 timeout = 0;
+	u8 rst = _FALSE;
+
+	_enter_critical_mutex(mutex, NULL);
+
+	rtw_write32(adapter, REG_WKFMCAM_CMD, BIT_WKFCAM_POLLING_V1 | BIT_WKFCAM_ADDR_V2(addr));
+
+	start = rtw_get_current_time();
+	while (1) {
+		if (rtw_is_surprise_removed(adapter))
+			break;
+
+		cnt++;
+		if (0 == (rtw_read32(adapter, REG_WKFMCAM_CMD) & BIT_WKFCAM_POLLING_V1)) {
+			rst = _SUCCESS;
+			break;
+		}
+		if (rtw_get_passing_time_ms(start) > WOW_CAM_ACCESS_TIMEOUT_MS) {
+			timeout = 1;
+			break;
+		}
+	}
+
+	rdata = rtw_read32(adapter, REG_WKFMCAM_RWD);
+
+	_exit_critical_mutex(mutex, NULL);
+
+	/*RTW_INFO("%s ==> addr:0x%02x , rdata:0x%08x\n", __func__, addr, rdata);*/
+
+	if (timeout)
+		RTW_ERR(FUNC_ADPT_FMT" failed due to polling timeout\n", FUNC_ADPT_ARG(adapter));
+
+	return rdata;
+}
+void rtw_wow_pattern_read_cam_ent(_adapter *adapter, u8 id, struct  rtl_wow_pattern *context)
+{
+	int i;
+	u32 rdata;
+
+	_rtw_memset(context, 0, sizeof(struct  rtl_wow_pattern));
+
+	for (i = 4; i >= 0; i--) {
+		rdata = _rtw_wow_pattern_read_cam(adapter, (id << 3) | i);
+
+		switch (i) {
+		case 4:
+			if (rdata & WOW_BC_BIT)
+				context->type = PATTERN_BROADCAST;
+			else if (rdata & WOW_MC_BIT)
+				context->type = PATTERN_MULTICAST;
+			else if (rdata & WOW_UC_BIT)
+				context->type = PATTERN_UNICAST;
+			else
+				context->type = PATTERN_INVALID;
+
+			context->crc = rdata & 0xFFFF;
+			break;
+		default:
+			_rtw_memcpy(&context->mask[i], (u8 *)(&rdata), 4);
+			break;
+		}
+	}
+}
+
+static void _rtw_wow_pattern_write_cam(_adapter *adapter, u8 addr, u32 wdata)
+{
+	struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(adapter);
+	_mutex *mutex = &pwrpriv->wowlan_pattern_cam_mutex;
+	u32 cnt = 0;
+	systime start = 0, end = 0;
+	u8 timeout = 0;
+
+	/*RTW_INFO("%s ==> addr:0x%02x , wdata:0x%08x\n", __func__, addr, wdata);*/
+	_enter_critical_mutex(mutex, NULL);
+
+	rtw_write32(adapter, REG_WKFMCAM_RWD, wdata);
+	rtw_write32(adapter, REG_WKFMCAM_CMD, BIT_WKFCAM_POLLING_V1 | BIT_WKFCAM_WE | BIT_WKFCAM_ADDR_V2(addr));
+
+	start = rtw_get_current_time();
+	while (1) {
+		if (rtw_is_surprise_removed(adapter))
+			break;
+
+		cnt++;
+		if (0 == (rtw_read32(adapter, REG_WKFMCAM_CMD) & BIT_WKFCAM_POLLING_V1))
+			break;
+
+		if (rtw_get_passing_time_ms(start) > WOW_CAM_ACCESS_TIMEOUT_MS) {
+			timeout = 1;
+			break;
+		}
+	}
+	end = rtw_get_current_time();
+
+	_exit_critical_mutex(mutex, NULL);
+
+	if (timeout) {
+		RTW_ERR(FUNC_ADPT_FMT" addr:0x%02x, wdata:0x%08x, to:%u, polling:%u, %d ms\n"
+			, FUNC_ADPT_ARG(adapter), addr, wdata, timeout, cnt, rtw_get_time_interval_ms(start, end));
+	}
+}
+
+void rtw_wow_pattern_write_cam_ent(_adapter *adapter, u8 id, struct  rtl_wow_pattern *context)
+{
+	int j;
+	u8 addr;
+	u32 wdata = 0;
+
+	for (j = 4; j >= 0; j--) {
+		switch (j) {
+		case 4:
+			wdata = context->crc;
+
+			if (PATTERN_BROADCAST == context->type)
+				wdata |= WOW_BC_BIT;
+			if (PATTERN_MULTICAST == context->type)
+				wdata |= WOW_MC_BIT;
+			if (PATTERN_UNICAST == context->type)
+				wdata |= WOW_UC_BIT;
+			if (PATTERN_INVALID != context->type)
+				wdata |= WOW_VALID_BIT;
+			break;
+		default:
+			wdata = context->mask[j];
+			break;
+		}
+
+		addr = (id << 3) + j;
+
+		_rtw_wow_pattern_write_cam(adapter, addr, wdata);
+	}
+}
+
+static u8 _rtw_wow_pattern_clean_cam(_adapter *adapter)
+{
+	struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(adapter);
+	_mutex *mutex = &pwrpriv->wowlan_pattern_cam_mutex;
+	u32 cnt = 0;
+	systime start = 0;
+	u8 timeout = 0;
+	u8 rst = _FAIL;
+
+	_enter_critical_mutex(mutex, NULL);
+	rtw_write32(adapter, REG_WKFMCAM_CMD, BIT_WKFCAM_POLLING_V1 | BIT_WKFCAM_CLR_V1);
+
+	start = rtw_get_current_time();
+	while (1) {
+		if (rtw_is_surprise_removed(adapter))
+			break;
+
+		cnt++;
+		if (0 == (rtw_read32(adapter, REG_WKFMCAM_CMD) & BIT_WKFCAM_POLLING_V1)) {
+			rst = _SUCCESS;
+			break;
+		}
+		if (rtw_get_passing_time_ms(start) > WOW_CAM_ACCESS_TIMEOUT_MS) {
+			timeout = 1;
+			break;
+		}
+	}
+	_exit_critical_mutex(mutex, NULL);
+
+	if (timeout)
+		RTW_ERR(FUNC_ADPT_FMT" falied ,polling timeout\n", FUNC_ADPT_ARG(adapter));
+
+	return rst;
+}
+
+void rtw_clean_pattern(_adapter *adapter)
+{
+	if (_FAIL == _rtw_wow_pattern_clean_cam(adapter))
+		RTW_ERR("rtw_clean_pattern failed\n");
+}
+
+void rtw_dump_wow_pattern(void *sel, struct rtl_wow_pattern *pwow_pattern, u8 idx)
+{
+	int j;
+
+	RTW_PRINT_SEL(sel, "=======WOW CAM-ID[%d]=======\n", idx);
+	RTW_PRINT_SEL(sel, "[WOW CAM] type:%d\n", pwow_pattern->type);
+	RTW_PRINT_SEL(sel, "[WOW CAM] crc:0x%04x\n", pwow_pattern->crc);
+	for (j = 0; j < 4; j++)
+		RTW_PRINT_SEL(sel, "[WOW CAM] Mask:0x%08x\n", pwow_pattern->mask[j]);
+}
+
+void rtw_fill_pattern(_adapter *adapter)
+{
+	int i = 0, total = 0;
+	struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(adapter);
+	struct rtl_wow_pattern wow_pattern;
+
+	total = pwrpriv->wowlan_pattern_idx;
+
+	if (total > MAX_WKFM_CAM_NUM)
+		total = MAX_WKFM_CAM_NUM;
+
+	for (i = 0 ; i < total ; i++) {
+		if (_SUCCESS == rtw_hal_wow_pattern_generate(adapter, i, &wow_pattern)) {
+			rtw_dump_wow_pattern(RTW_DBGDUMP, &wow_pattern, i);
+			rtw_wow_pattern_write_cam_ent(adapter, i, &wow_pattern);
+		}
+	}
+}
+
+#endif
+void rtw_wow_pattern_cam_dump(_adapter *adapter)
+{
+
+#ifndef CONFIG_WOW_PATTERN_HW_CAM
+	int i;
+
+	for (i = 0 ; i < MAX_WKFM_CAM_NUM; i++) {
+		RTW_INFO("=======[%d]=======\n", i);
+		rtw_read_from_frame_mask(adapter, i);
+	}
+#else
+	struct  rtl_wow_pattern context;
+	int i;
+
+	for (i = 0 ; i < MAX_WKFM_CAM_NUM; i++) {
+		rtw_wow_pattern_read_cam_ent(adapter, i, &context);
+		rtw_dump_wow_pattern(RTW_DBGDUMP, &context, i);
+	}
+
+#endif
+}
+
+
+static void rtw_hal_dl_pattern(_adapter *adapter, u8 mode)
+{
+	struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(adapter);
+
+	switch (mode) {
+	case 0:
+		rtw_clean_pattern(adapter);
+		RTW_INFO("%s: total patterns: %d\n", __func__, pwrpriv->wowlan_pattern_idx);
+		break;
+	case 1:
+		rtw_set_default_pattern(adapter);
+		rtw_fill_pattern(adapter);
+		RTW_INFO("%s: pattern total: %d downloaded\n", __func__, pwrpriv->wowlan_pattern_idx);
+		break;
+	case 2:
+		rtw_clean_pattern(adapter);
+		rtw_wow_pattern_sw_reset(adapter);
+		RTW_INFO("%s: clean patterns\n", __func__);
+		break;
+	default:
+		RTW_INFO("%s: unknown mode\n", __func__);
+		break;
+	}
+}
+
+static void rtw_hal_wow_enable(_adapter *adapter)
+{
+	struct pwrctrl_priv *pwrctl = adapter_to_pwrctl(adapter);
+	struct security_priv *psecuritypriv = &adapter->securitypriv;
+	struct mlme_priv *pmlmepriv = &adapter->mlmepriv;
+	struct hal_ops *pHalFunc = &adapter->hal_func;
+	struct sta_info *psta = NULL;
+	PHAL_DATA_TYPE pHalData = GET_HAL_DATA(adapter);
+	int res;
+	u16 media_status_rpt;
+
+
+	RTW_PRINT(FUNC_ADPT_FMT " WOWLAN_ENABLE\n", FUNC_ADPT_ARG(adapter));
+	rtw_hal_gate_bb(adapter, _TRUE);
+#ifdef CONFIG_GTK_OL
+	if (psecuritypriv->binstallKCK_KEK == _TRUE)
+		rtw_hal_fw_sync_cam_id(adapter);
+#endif
+	if (IS_HARDWARE_TYPE_8723B(adapter))
+		rtw_hal_backup_rate(adapter);
+
+	rtw_hal_fw_dl(adapter, _TRUE);
+	media_status_rpt = RT_MEDIA_CONNECT;
+	rtw_hal_set_hwreg(adapter, HW_VAR_H2C_FW_JOINBSSRPT,
+			  (u8 *)&media_status_rpt);
+
+	/* RX DMA stop */
+	#if defined(CONFIG_RTL8188E)
+	if (IS_HARDWARE_TYPE_8188E(adapter))
+		rtw_hal_disable_tx_report(adapter);
+	#endif
+
+	res = rtw_hal_pause_rx_dma(adapter);
+	if (res == _FAIL)
+		RTW_PRINT("[WARNING] pause RX DMA fail\n");
+
+	#ifndef CONFIG_WOW_PATTERN_HW_CAM
+	/* Reconfig RX_FF Boundary */
+	rtw_hal_set_wow_rxff_boundary(adapter, _TRUE);
+	#endif
+
+	/* redownload wow pattern */
+	rtw_hal_dl_pattern(adapter, 1);
+
+	if (!pwrctl->wowlan_pno_enable) {
+		psta = rtw_get_stainfo(&adapter->stapriv, get_bssid(pmlmepriv));
+
+		if (psta != NULL) {
+			#ifdef CONFIG_FW_MULTI_PORT_SUPPORT
+			adapter_to_dvobj(adapter)->dft.port_id = 0xFF;
+			adapter_to_dvobj(adapter)->dft.mac_id = 0xFF;
+			rtw_hal_set_default_port_id_cmd(adapter, psta->cmn.mac_id);
+			#endif
+
+			rtw_sta_media_status_rpt(adapter, psta, 1);
+		}
+	}
+
+#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
+	/* Enable CPWM2 only. */
+	res = rtw_hal_enable_cpwm2(adapter);
+	if (res == _FAIL)
+		RTW_PRINT("[WARNING] enable cpwm2 fail\n");
+#endif
+#ifdef CONFIG_GPIO_WAKEUP
+	rtw_hal_switch_gpio_wl_ctrl(adapter, WAKEUP_GPIO_IDX, _TRUE);
+#endif
+	/* Set WOWLAN H2C command. */
+	RTW_PRINT("Set WOWLan cmd\n");
+	rtw_hal_set_fw_wow_related_cmd(adapter, 1);
+
+	res = rtw_hal_check_wow_ctrl(adapter, _TRUE);
+
+	if (res == _FALSE)
+		RTW_INFO("[Error]%s: set wowlan CMD fail!!\n", __func__);
+
+	pwrctl->wowlan_wake_reason =
+		rtw_read8(adapter, REG_WOWLAN_WAKE_REASON);
+
+	RTW_PRINT("wowlan_wake_reason: 0x%02x\n",
+		  pwrctl->wowlan_wake_reason);
+#ifdef CONFIG_GTK_OL_DBG
+	dump_sec_cam(RTW_DBGDUMP, adapter);
+	dump_sec_cam_cache(RTW_DBGDUMP, adapter);
+#endif
+#ifdef CONFIG_USB_HCI
+	/* free adapter's resource */
+	rtw_mi_intf_stop(adapter);
+
+#endif
+#if defined(CONFIG_USB_HCI) || defined(CONFIG_PCI_HCI)
+	/* Invoid SE0 reset signal during suspending*/
+	rtw_write8(adapter, REG_RSV_CTRL, 0x20);
+	if (IS_8188F(pHalData->version_id) == FALSE
+		&& IS_8188GTV(pHalData->version_id) == FALSE)
+		rtw_write8(adapter, REG_RSV_CTRL, 0x60);
+#endif
+
+	rtw_hal_gate_bb(adapter, _FALSE);
+}
+
+#define DBG_WAKEUP_REASON
+#ifdef DBG_WAKEUP_REASON
+void _dbg_wake_up_reason_string(_adapter *adapter, const char *srt_res)
+{
+	RTW_INFO(ADPT_FMT "- wake up reason - %s\n", ADPT_ARG(adapter), srt_res);
+}
+void _dbg_rtw_wake_up_reason(_adapter *adapter, u8 reason)
+{
+	if (RX_PAIRWISEKEY == reason)
+		_dbg_wake_up_reason_string(adapter, "Rx pairwise key");
+	else if (RX_GTK == reason)
+		_dbg_wake_up_reason_string(adapter, "Rx GTK");
+	else if (RX_FOURWAY_HANDSHAKE == reason)
+		_dbg_wake_up_reason_string(adapter, "Rx four way handshake");
+	else if (RX_DISASSOC == reason)
+		_dbg_wake_up_reason_string(adapter, "Rx disassoc");
+	else if (RX_DEAUTH == reason)
+		_dbg_wake_up_reason_string(adapter, "Rx deauth");
+	else if (RX_ARP_REQUEST == reason)
+		_dbg_wake_up_reason_string(adapter, "Rx ARP request");
+	else if (FW_DECISION_DISCONNECT == reason)
+		_dbg_wake_up_reason_string(adapter, "FW detect disconnect");
+	else if (RX_MAGIC_PKT == reason)
+		_dbg_wake_up_reason_string(adapter, "Rx magic packet");
+	else if (RX_UNICAST_PKT == reason)
+		_dbg_wake_up_reason_string(adapter, "Rx unicast packet");
+	else if (RX_PATTERN_PKT == reason)
+		_dbg_wake_up_reason_string(adapter, "Rx pattern packet");
+	else if (RTD3_SSID_MATCH == reason)
+		_dbg_wake_up_reason_string(adapter, "RTD3 SSID match");
+	else if (RX_REALWOW_V2_WAKEUP_PKT == reason)
+		_dbg_wake_up_reason_string(adapter, "Rx real WOW V2 wakeup packet");
+	else if (RX_REALWOW_V2_ACK_LOST == reason)
+		_dbg_wake_up_reason_string(adapter, "Rx real WOW V2 ack lost");
+	else if (ENABLE_FAIL_DMA_IDLE == reason)
+		_dbg_wake_up_reason_string(adapter, "enable fail DMA idle");
+	else if (ENABLE_FAIL_DMA_PAUSE == reason)
+		_dbg_wake_up_reason_string(adapter, "enable fail DMA pause");
+	else if (AP_OFFLOAD_WAKEUP == reason)
+		_dbg_wake_up_reason_string(adapter, "AP offload wakeup");
+	else if (CLK_32K_UNLOCK == reason)
+		_dbg_wake_up_reason_string(adapter, "clk 32k unlock");
+	else if (RTIME_FAIL_DMA_IDLE == reason)
+		_dbg_wake_up_reason_string(adapter, "RTIME fail DMA idle");
+	else if (CLK_32K_LOCK == reason)
+		_dbg_wake_up_reason_string(adapter, "clk 32k lock");
+	else
+		_dbg_wake_up_reason_string(adapter, "unknown reasoen");
+}
+#endif
+
+static void rtw_hal_wow_disable(_adapter *adapter)
+{
+	struct pwrctrl_priv *pwrctl = adapter_to_pwrctl(adapter);
+	struct security_priv *psecuritypriv = &adapter->securitypriv;
+	struct mlme_priv *pmlmepriv = &adapter->mlmepriv;
+	struct hal_ops *pHalFunc = &adapter->hal_func;
+	struct sta_info *psta = NULL;
+	int res;
+	u16 media_status_rpt;
+	u8 val8;
+
+	RTW_PRINT("%s, WOWLAN_DISABLE\n", __func__);
+
+	if (!pwrctl->wowlan_pno_enable) {
+		psta = rtw_get_stainfo(&adapter->stapriv, get_bssid(pmlmepriv));
+		if (psta != NULL)
+			rtw_sta_media_status_rpt(adapter, psta, 0);
+		else
+			RTW_INFO("%s: psta is null\n", __func__);
+	}
+
+	if (0) {
+		RTW_INFO("0x630:0x%02x\n", rtw_read8(adapter, 0x630));
+		RTW_INFO("0x631:0x%02x\n", rtw_read8(adapter, 0x631));
+		RTW_INFO("0x634:0x%02x\n", rtw_read8(adapter, 0x634));
+		RTW_INFO("0x1c7:0x%02x\n", rtw_read8(adapter, 0x1c7));
+	}
+
+	pwrctl->wowlan_wake_reason = rtw_read8(adapter, REG_WOWLAN_WAKE_REASON);
+
+	RTW_PRINT("wakeup_reason: 0x%02x\n",
+		  pwrctl->wowlan_wake_reason);
+	#ifdef DBG_WAKEUP_REASON
+	_dbg_rtw_wake_up_reason(adapter, pwrctl->wowlan_wake_reason);
+	#endif
+
+	rtw_hal_set_fw_wow_related_cmd(adapter, 0);
+
+	res = rtw_hal_check_wow_ctrl(adapter, _FALSE);
+
+	if (res == _FALSE) {
+		RTW_INFO("[Error]%s: disable WOW cmd fail\n!!", __func__);
+		rtw_hal_force_enable_rxdma(adapter);
+	}
+
+	rtw_hal_gate_bb(adapter, _TRUE);
+
+	res = rtw_hal_pause_rx_dma(adapter);
+	if (res == _FAIL)
+		RTW_PRINT("[WARNING] pause RX DMA fail\n");
+
+	/* clean HW pattern match */
+	rtw_hal_dl_pattern(adapter, 0);
+
+	#ifndef CONFIG_WOW_PATTERN_HW_CAM
+	/* config RXFF boundary to original */
+	rtw_hal_set_wow_rxff_boundary(adapter, _FALSE);
+	#endif
+	rtw_hal_release_rx_dma(adapter);
+
+	#if defined(CONFIG_RTL8188E)
+	if (IS_HARDWARE_TYPE_8188E(adapter))
+		rtw_hal_enable_tx_report(adapter);
+	#endif
+
+	if ((pwrctl->wowlan_wake_reason != RX_DISASSOC) &&
+		(pwrctl->wowlan_wake_reason != RX_DEAUTH) &&
+		(pwrctl->wowlan_wake_reason != FW_DECISION_DISCONNECT)) {
+		rtw_hal_get_aoac_rpt(adapter);
+		rtw_hal_update_sw_security_info(adapter);
+	}
+
+	rtw_hal_fw_dl(adapter, _FALSE);
+
+#ifdef CONFIG_GPIO_WAKEUP
+
+#ifdef CONFIG_RTW_ONE_PIN_GPIO
+	rtw_hal_set_input_gpio(adapter, WAKEUP_GPIO_IDX);
+#else
+#ifdef CONFIG_WAKEUP_GPIO_INPUT_MODE
+	if (pwrctl->is_high_active == 0)
+		rtw_hal_set_input_gpio(adapter, WAKEUP_GPIO_IDX);
+	else
+		rtw_hal_set_output_gpio(adapter, WAKEUP_GPIO_IDX, 0);
+#else
+	val8 = (pwrctl->is_high_active == 0) ? 1 : 0;
+	RTW_PRINT("Set Wake GPIO to default(%d).\n", val8);
+
+	rtw_hal_set_output_gpio(adapter, WAKEUP_GPIO_IDX, val8);
+	rtw_hal_switch_gpio_wl_ctrl(adapter, WAKEUP_GPIO_IDX, _FALSE);
+#endif
+#endif /* CONFIG_RTW_ONE_PIN_GPIO */
+#endif
+	if ((pwrctl->wowlan_wake_reason != FW_DECISION_DISCONNECT) &&
+	    (pwrctl->wowlan_wake_reason != RX_PAIRWISEKEY) &&
+	    (pwrctl->wowlan_wake_reason != RX_DISASSOC) &&
+	    (pwrctl->wowlan_wake_reason != RX_DEAUTH)) {
+
+		media_status_rpt = RT_MEDIA_CONNECT;
+		rtw_hal_set_hwreg(adapter, HW_VAR_H2C_FW_JOINBSSRPT,
+				  (u8 *)&media_status_rpt);
+
+		if (psta != NULL) {
+			#ifdef CONFIG_FW_MULTI_PORT_SUPPORT
+			adapter_to_dvobj(adapter)->dft.port_id = 0xFF;
+			adapter_to_dvobj(adapter)->dft.mac_id = 0xFF;
+			rtw_hal_set_default_port_id_cmd(adapter, psta->cmn.mac_id);
+			#endif
+			rtw_sta_media_status_rpt(adapter, psta, 1);
+		}
+	}
+	rtw_hal_gate_bb(adapter, _FALSE);
+}
+#endif /*CONFIG_WOWLAN*/
+
+#ifdef CONFIG_P2P_WOWLAN
+void rtw_hal_set_p2p_wow_fw_rsvd_page(_adapter *adapter, u8 *pframe, u16 index,
+	      u8 tx_desc, u32 page_size, u8 *page_num, u32 *total_pkt_len,
+				      RSVDPAGE_LOC *rsvd_page_loc)
+{
+	u32 P2PNegoRspLength = 0, P2PInviteRspLength = 0;
+	u32 P2PPDRspLength = 0, P2PProbeRspLength = 0, P2PBCNLength = 0;
+	u8 CurtPktPageNum = 0;
+
+	/* P2P Beacon */
+	rsvd_page_loc->LocP2PBeacon = *page_num;
+	rtw_hal_construct_P2PBeacon(adapter, &pframe[index], &P2PBCNLength);
+	rtw_hal_fill_fake_txdesc(adapter, &pframe[index - tx_desc],
+				 P2PBCNLength, _FALSE, _FALSE, _FALSE);
+
+#if 0
+	RTW_INFO("%s(): HW_VAR_SET_TX_CMD: PROBE RSP %p %d\n",
+		__FUNCTION__, &pframe[index - tx_desc], (P2PBCNLength + tx_desc));
+#endif
+
+	CurtPktPageNum = (u8)PageNum(tx_desc + P2PBCNLength, page_size);
+
+	*page_num += CurtPktPageNum;
+
+	index += (CurtPktPageNum * page_size);
+	#ifdef DBG_RSVD_PAGE_CFG
+	RSVD_PAGE_CFG("WOW-P2P-Beacon", CurtPktPageNum, *page_num, 0);
+	#endif
+
+	/* P2P Probe rsp */
+	rsvd_page_loc->LocP2PProbeRsp = *page_num;
+	rtw_hal_construct_P2PProbeRsp(adapter, &pframe[index],
+				      &P2PProbeRspLength);
+	rtw_hal_fill_fake_txdesc(adapter, &pframe[index - tx_desc],
+				 P2PProbeRspLength, _FALSE, _FALSE, _FALSE);
+
+	/* RTW_INFO("%s(): HW_VAR_SET_TX_CMD: PROBE RSP %p %d\n",  */
+	/*	__FUNCTION__, &pframe[index-tx_desc], (P2PProbeRspLength+tx_desc)); */
+
+	CurtPktPageNum = (u8)PageNum(tx_desc + P2PProbeRspLength, page_size);
+
+	*page_num += CurtPktPageNum;
+
+	index += (CurtPktPageNum * page_size);
+	#ifdef DBG_RSVD_PAGE_CFG
+	RSVD_PAGE_CFG("WOW-P2P-ProbeRsp", CurtPktPageNum, *page_num, 0);
+	#endif
+
+	/* P2P nego rsp */
+	rsvd_page_loc->LocNegoRsp = *page_num;
+	rtw_hal_construct_P2PNegoRsp(adapter, &pframe[index],
+				     &P2PNegoRspLength);
+	rtw_hal_fill_fake_txdesc(adapter, &pframe[index - tx_desc],
+				 P2PNegoRspLength, _FALSE, _FALSE, _FALSE);
+
+	/* RTW_INFO("%s(): HW_VAR_SET_TX_CMD: QOS NULL DATA %p %d\n",  */
+	/*	__FUNCTION__, &pframe[index-tx_desc], (NegoRspLength+tx_desc)); */
+
+	CurtPktPageNum = (u8)PageNum(tx_desc + P2PNegoRspLength, page_size);
+
+	*page_num += CurtPktPageNum;
+
+	index += (CurtPktPageNum * page_size);
+	#ifdef DBG_RSVD_PAGE_CFG
+	RSVD_PAGE_CFG("WOW-P2P-NegoRsp", CurtPktPageNum, *page_num, 0);
+	#endif
+
+	/* P2P invite rsp */
+	rsvd_page_loc->LocInviteRsp = *page_num;
+	rtw_hal_construct_P2PInviteRsp(adapter, &pframe[index],
+				       &P2PInviteRspLength);
+	rtw_hal_fill_fake_txdesc(adapter, &pframe[index - tx_desc],
+				 P2PInviteRspLength, _FALSE, _FALSE, _FALSE);
+
+	/* RTW_INFO("%s(): HW_VAR_SET_TX_CMD: QOS NULL DATA %p %d\n",  */
+	/* __FUNCTION__, &pframe[index-tx_desc], (InviteRspLength+tx_desc)); */
+
+	CurtPktPageNum = (u8)PageNum(tx_desc + P2PInviteRspLength, page_size);
+
+	*page_num += CurtPktPageNum;
+
+	index += (CurtPktPageNum * page_size);
+	#ifdef DBG_RSVD_PAGE_CFG
+	RSVD_PAGE_CFG("WOW-P2P-InviteRsp", CurtPktPageNum, *page_num, 0);
+	#endif
+
+	/* P2P provision discovery rsp */
+	rsvd_page_loc->LocPDRsp = *page_num;
+	rtw_hal_construct_P2PProvisionDisRsp(adapter,
+					     &pframe[index], &P2PPDRspLength);
+
+	rtw_hal_fill_fake_txdesc(adapter, &pframe[index - tx_desc],
+				 P2PPDRspLength, _FALSE, _FALSE, _FALSE);
+
+	/* RTW_INFO("%s(): HW_VAR_SET_TX_CMD: QOS NULL DATA %p %d\n",  */
+	/*	__FUNCTION__, &pframe[index-tx_desc], (PDRspLength+tx_desc)); */
+
+	CurtPktPageNum = (u8)PageNum(tx_desc + P2PPDRspLength, page_size);
+
+	*page_num += CurtPktPageNum;
+
+	*total_pkt_len = index + P2PPDRspLength;
+	#ifdef DBG_RSVD_PAGE_CFG
+	RSVD_PAGE_CFG("WOW-P2P-PDR", CurtPktPageNum, *page_num, *total_pkt_len);
+	#endif
+
+	index += (CurtPktPageNum * page_size);
+
+
+}
+#endif /* CONFIG_P2P_WOWLAN */
+
+#ifdef CONFIG_LPS_PG
+#include "hal_halmac.h"
+
+#define DBG_LPSPG_SEC_DUMP
+#define LPS_PG_INFO_RSVD_LEN	16
+#define LPS_PG_INFO_RSVD_PAGE_NUM	1
+
+#define DBG_LPSPG_INFO_DUMP
+static void rtw_hal_set_lps_pg_info_rsvd_page(_adapter *adapter)
+{
+	struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(adapter);
+	struct sta_info	*psta = rtw_get_stainfo(&adapter->stapriv, get_bssid(&adapter->mlmepriv));
+	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
+	PHAL_DATA_TYPE phal_data = GET_HAL_DATA(adapter);
+	u8 lps_pg_info[LPS_PG_INFO_RSVD_LEN] = {0};
+#ifdef CONFIG_MBSSID_CAM
+	u8 cam_id = INVALID_CAM_ID;
+#endif
+	u8 *psec_cam_id = lps_pg_info + 8;
+	u8 sec_cam_num = 0;
+	u8 drv_rsvdpage_num = 0;
+
+	if (!psta) {
+		RTW_ERR("%s [ERROR] sta is NULL\n", __func__);
+		rtw_warn_on(1);
+		return;
+	}
+
+	/*Byte 0 - used macid*/
+	LPSPG_RSVD_PAGE_SET_MACID(lps_pg_info, psta->cmn.mac_id);
+	RTW_INFO("[LPSPG-INFO] mac_id:%d\n", psta->cmn.mac_id);
+
+#ifdef CONFIG_MBSSID_CAM
+	/*Byte 1 - used BSSID CAM entry*/
+	cam_id = rtw_mbid_cam_search_by_ifaceid(adapter, adapter->iface_id);
+	if (cam_id != INVALID_CAM_ID)
+		LPSPG_RSVD_PAGE_SET_MBSSCAMID(lps_pg_info, cam_id);
+	RTW_INFO("[LPSPG-INFO] mbss_cam_id:%d\n", cam_id);
+#endif
+
+#ifdef CONFIG_WOWLAN /*&& pattern match cam used*/
+	/*Btye 2 - Max used Pattern Match CAM entry*/
+	if (pwrpriv->wowlan_mode == _TRUE &&
+	    check_fwstate(&adapter->mlmepriv, _FW_LINKED) == _TRUE) {
+		LPSPG_RSVD_PAGE_SET_PMC_NUM(lps_pg_info, pwrpriv->wowlan_pattern_idx);
+		RTW_INFO("[LPSPG-INFO] Max Pattern Match CAM entry :%d\n", pwrpriv->wowlan_pattern_idx);
+	}
+#endif
+#ifdef CONFIG_BEAMFORMING  /*&& MU BF*/
+	/*Btye 3 - Max MU rate table Group ID*/
+	LPSPG_RSVD_PAGE_SET_MU_RAID_GID(lps_pg_info, 0);
+	RTW_INFO("[LPSPG-INFO] Max MU rate table Group ID :%d\n", 0);
+#endif
+
+	/*Btye 8 ~15 - used Security CAM entry */
+	sec_cam_num = rtw_get_sec_camid(adapter, 8, psec_cam_id);
+
+	/*Btye 4 - used Security CAM entry number*/
+	if (sec_cam_num < 8)
+		LPSPG_RSVD_PAGE_SET_SEC_CAM_NUM(lps_pg_info, sec_cam_num);
+	RTW_INFO("[LPSPG-INFO] Security CAM entry number :%d\n", sec_cam_num);
+
+	/*Btye 5 - Txbuf used page number for fw offload*/
+	if (pwrpriv->wowlan_mode == _TRUE || pwrpriv->wowlan_ap_mode == _TRUE)
+		drv_rsvdpage_num = rtw_hal_get_txbuff_rsvd_page_num(adapter, _TRUE);
+	else
+		drv_rsvdpage_num = rtw_hal_get_txbuff_rsvd_page_num(adapter, _FALSE);
+	LPSPG_RSVD_PAGE_SET_DRV_RSVDPAGE_NUM(lps_pg_info, drv_rsvdpage_num);
+	RTW_INFO("[LPSPG-INFO] DRV's rsvd page numbers :%d\n", drv_rsvdpage_num);
+
+#ifdef DBG_LPSPG_SEC_DUMP
+	{
+		int i;
+
+		for (i = 0; i < sec_cam_num; i++)
+			RTW_INFO("%d = sec_cam_id:%d\n", i, psec_cam_id[i]);
+	}
+#endif
+
+#ifdef DBG_LPSPG_INFO_DUMP
+	RTW_INFO("==== DBG_LPSPG_INFO_RSVD_PAGE_DUMP====\n");
+	RTW_INFO("  %02X:%02X:%02X:%02X:%02X:%02X:%02X:%02X\n",
+		*(lps_pg_info), *(lps_pg_info + 1), *(lps_pg_info + 2), *(lps_pg_info + 3),
+		*(lps_pg_info + 4), *(lps_pg_info + 5), *(lps_pg_info + 6), *(lps_pg_info + 7));
+	RTW_INFO("  %02X:%02X:%02X:%02X:%02X:%02X:%02X:%02X\n",
+		*(lps_pg_info + 8), *(lps_pg_info + 9), *(lps_pg_info + 10), *(lps_pg_info + 11),
+		*(lps_pg_info + 12), *(lps_pg_info + 13), *(lps_pg_info + 14), *(lps_pg_info + 15));
+	RTW_INFO("==== DBG_LPSPG_INFO_RSVD_PAGE_DUMP====\n");
+#endif
+
+	rtw_halmac_download_rsvd_page(dvobj, pwrpriv->lpspg_rsvd_page_locate, lps_pg_info, LPS_PG_INFO_RSVD_LEN);
+
+#ifdef DBG_LPSPG_INFO_DUMP
+	RTW_INFO("Get LPS-PG INFO from rsvd page_offset:%d\n", pwrpriv->lpspg_rsvd_page_locate);
+	rtw_dump_rsvd_page(RTW_DBGDUMP, adapter, pwrpriv->lpspg_rsvd_page_locate, 1);
+#endif
+}
+
+
+static u8 rtw_hal_set_lps_pg_info_cmd(_adapter *adapter)
+{
+	struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(adapter);
+	struct mlme_priv *pmlmepriv = &adapter->mlmepriv;
+
+	u8 lpspg_info[H2C_LPS_PG_INFO_LEN] = {0};
+	u8 ret = _FAIL;
+
+	RTW_INFO("%s: loc_lpspg_info:%d\n", __func__, pwrpriv->lpspg_rsvd_page_locate);
+
+	if (_NO_PRIVACY_ != adapter->securitypriv.dot11PrivacyAlgrthm)
+		SET_H2CCMD_LPSPG_SEC_CAM_EN(lpspg_info, 1);	/*SecurityCAM_En*/
+#ifdef CONFIG_MBSSID_CAM
+	SET_H2CCMD_LPSPG_MBID_CAM_EN(lpspg_info, 1);		/*BSSIDCAM_En*/
+#endif
+
+#if defined(CONFIG_WOWLAN) && defined(CONFIG_WOW_PATTERN_HW_CAM)
+	if (pwrpriv->wowlan_mode == _TRUE &&
+	    check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE) {
+
+		SET_H2CCMD_LPSPG_PMC_CAM_EN(lpspg_info, 1);	/*PatternMatchCAM_En*/
+	}
+#endif
+
+#ifdef CONFIG_MACID_SEARCH
+	SET_H2CCMD_LPSPG_MACID_SEARCH_EN(lpspg_info, 1);	/*MACIDSearch_En*/
+#endif
+
+#ifdef CONFIG_TX_SC
+	SET_H2CCMD_LPSPG_TXSC_EN(lpspg_info, 1);	/*TXSC_En*/
+#endif
+
+#ifdef CONFIG_BEAMFORMING  /*&& MU BF*/
+	SET_H2CCMD_LPSPG_MU_RATE_TB_EN(lpspg_info, 1);	/*MURateTable_En*/
+#endif
+
+	SET_H2CCMD_LPSPG_LOC(lpspg_info, pwrpriv->lpspg_rsvd_page_locate);
+
+#ifdef DBG_LPSPG_INFO_DUMP
+	RTW_INFO("==== DBG_LPSPG_INFO_CMD_DUMP====\n");
+	RTW_INFO("  H2C_CMD: 0x%02x, H2C_LEN: %d\n", H2C_LPS_PG_INFO, H2C_LPS_PG_INFO_LEN);
+	RTW_INFO("  %02X:%02X\n", *(lpspg_info), *(lpspg_info + 1));
+	RTW_INFO("==== DBG_LPSPG_INFO_CMD_DUMP====\n");
+#endif
+
+	ret = rtw_hal_fill_h2c_cmd(adapter,
+				   H2C_LPS_PG_INFO,
+				   H2C_LPS_PG_INFO_LEN,
+				   lpspg_info);
+	return ret;
+}
+u8 rtw_hal_set_lps_pg_info(_adapter *adapter)
+{
+	u8 ret = _FAIL;
+	struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(adapter);
+
+	if (pwrpriv->lpspg_rsvd_page_locate == 0) {
+		RTW_ERR("%s [ERROR] lpspg_rsvd_page_locate = 0\n", __func__);
+		rtw_warn_on(1);
+		return ret;
+	}
+
+	rtw_hal_set_lps_pg_info_rsvd_page(adapter);
+	ret = rtw_hal_set_lps_pg_info_cmd(adapter);
+	if (_SUCCESS == ret)
+		pwrpriv->blpspg_info_up = _FALSE;
+
+	return ret;
+}
+
+void rtw_hal_lps_pg_rssi_lv_decide(_adapter *adapter, struct sta_info *sta)
+{
+#if 0
+	if (sta->cmn.ra_info.rssi_level >= 4)
+		sta->lps_pg_rssi_lv = 3;	/*RSSI High - 1SS_VHT_MCS7*/
+	else if (sta->cmn.ra_info.rssi_level >=  2)
+		sta->lps_pg_rssi_lv = 2;	/*RSSI Middle - 1SS_VHT_MCS3*/
+	else
+		sta->lps_pg_rssi_lv = 1;	/*RSSI Lower - Lowest_rate*/
+#else
+	sta->lps_pg_rssi_lv = 0;
+#endif
+	RTW_INFO("%s mac-id:%d, rssi:%d, rssi_level:%d, lps_pg_rssi_lv:%d\n",
+		__func__, sta->cmn.mac_id, sta->cmn.rssi_stat.rssi, sta->cmn.ra_info.rssi_level, sta->lps_pg_rssi_lv);
+}
+
+void rtw_hal_lps_pg_handler(_adapter *adapter, enum lps_pg_hdl_id hdl_id)
+{
+	struct mlme_ext_priv *pmlmeext = &adapter->mlmeextpriv;
+	struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
+	struct sta_priv *pstapriv = &adapter->stapriv;
+	struct sta_info *sta;
+
+	sta = rtw_get_stainfo(pstapriv, pmlmeinfo->network.MacAddress);
+
+	switch (hdl_id) {
+	case LPS_PG_INFO_CFG:
+		rtw_hal_set_lps_pg_info(adapter);
+		break;
+	case LPS_PG_REDLEMEM:
+		{
+			/*set xmit_block*/
+			rtw_set_xmit_block(adapter, XMIT_BLOCK_REDLMEM);
+			if (_FAIL == rtw_hal_fw_mem_dl(adapter, FW_EMEM))
+				rtw_warn_on(1);
+			/*clearn xmit_block*/
+			rtw_clr_xmit_block(adapter, XMIT_BLOCK_REDLMEM);
+		}
+		break;
+	case LPS_PG_PHYDM_DIS:/*Disable RA and PT by H2C*/
+		if (sta)
+			rtw_phydm_lps_pg_hdl(adapter, sta, _TRUE);
+		break;
+	case LPS_PG_PHYDM_EN:/*Enable RA and PT by H2C*/
+		{
+			if (sta) {
+				rtw_hal_lps_pg_rssi_lv_decide(adapter, sta);
+				rtw_phydm_lps_pg_hdl(adapter, sta, _FALSE);
+				sta->lps_pg_rssi_lv = 0;
+			}
+		}
+		break;
+
+	default:
+		break;
+	}
+}
+
+#endif /*CONFIG_LPS_PG*/
+
+static u8 _rtw_mi_assoc_if_num(_adapter *adapter)
+{
+	u8 mi_iface_num = 0;
+
+	if (0) {
+		RTW_INFO("[IFS_ASSOC_STATUS] - STA :%d", DEV_STA_LD_NUM(adapter_to_dvobj(adapter)));
+		RTW_INFO("[IFS_ASSOC_STATUS] - AP:%d", DEV_AP_NUM(adapter_to_dvobj(adapter)));
+		RTW_INFO("[IFS_ASSOC_STATUS] - AP starting :%d", DEV_AP_STARTING_NUM(adapter_to_dvobj(adapter)));
+		RTW_INFO("[IFS_ASSOC_STATUS] - MESH :%d", DEV_MESH_NUM(adapter_to_dvobj(adapter)));
+		RTW_INFO("[IFS_ASSOC_STATUS] - ADHOC :%d", DEV_ADHOC_NUM(adapter_to_dvobj(adapter)));
+		/*RTW_INFO("[IFS_ASSOC_STATUS] - P2P-GC :%d", DEV_P2P_GC_NUM(adapter_to_dvobj(adapter)));*/
+		/*RTW_INFO("[IFS_ASSOC_STATUS] - P2P-GO :%d", DEV_P2P_GO_NUM(adapter_to_dvobj(adapter)));*/
+	}
+
+	mi_iface_num = (DEV_STA_LD_NUM(adapter_to_dvobj(adapter)) +
+		DEV_AP_NUM(adapter_to_dvobj(adapter)) +
+		DEV_AP_STARTING_NUM(adapter_to_dvobj(adapter)));
+	return mi_iface_num;
+}
+
+static _adapter *_rtw_search_sta_iface(_adapter *adapter)
+{
+	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
+	_adapter *iface = NULL;
+	_adapter *sta_iface = NULL;
+	int i;
+
+	for (i = 0; i < dvobj->iface_nums; i++) {
+		iface = dvobj->padapters[i];
+		if (check_fwstate(&iface->mlmepriv, WIFI_STATION_STATE) == _TRUE) {
+			if (check_fwstate(&iface->mlmepriv, _FW_LINKED) == _TRUE) {
+				sta_iface = iface;
+				break;
+			}
+		}
+	}
+	return sta_iface;
+}
+#ifdef CONFIG_AP_MODE
+static _adapter *_rtw_search_ap_iface(_adapter *adapter)
+{
+	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
+	_adapter *iface = NULL;
+	_adapter *ap_iface = NULL;
+	int i;
+
+	for (i = 0; i < dvobj->iface_nums; i++) {
+		iface = dvobj->padapters[i];
+		if (check_fwstate(&iface->mlmepriv, WIFI_AP_STATE) == _TRUE ) {
+			ap_iface = iface;
+			break;
+		}
+	}
+	return ap_iface;
+}
+#endif
+
+/*
+ * Description: Fill the reserved packets that FW will use to RSVD page.
+ *			Now we just send 4 types packet to rsvd page.
+ *			(1)Beacon, (2)Ps-poll, (3)Null data, (4)ProbeRsp.
+ * Input:
+ * finished - FALSE:At the first time we will send all the packets as a large packet to Hw,
+ *		    so we need to set the packet length to total lengh.
+ *	      TRUE: At the second time, we should send the first packet (default:beacon)
+ *		    to Hw again and set the lengh in descriptor to the real beacon lengh.
+ * page_num - The amount of reserved page which driver need.
+ *	      If this is not NULL, this function doesn't real download reserved
+ *	      page, but just count the number of reserved page.
+ *
+ * 2009.10.15 by tynli.
+ * 2017.06.20 modified by Lucas.
+ *
+ * Page Size = 128: 8188e, 8723a/b, 8192c/d,
+ * Page Size = 256: 8192e, 8821a
+ * Page Size = 512: 8812a
+ */
+
+/*#define DBG_DUMP_SET_RSVD_PAGE*/
+static void _rtw_hal_set_fw_rsvd_page(_adapter *adapter, bool finished, u8 *page_num)
+{
+	PHAL_DATA_TYPE pHalData;
+	struct xmit_frame	*pcmdframe = NULL;
+	struct pkt_attrib	*pattrib;
+	struct xmit_priv	*pxmitpriv;
+	struct pwrctrl_priv *pwrctl;
+	struct mlme_priv *pmlmepriv = &adapter->mlmepriv;
+	struct hal_ops *pHalFunc = &adapter->hal_func;
+	u32	BeaconLength = 0, ProbeRspLength = 0, PSPollLength = 0;
+	u32	NullDataLength = 0, QosNullLength = 0, BTQosNullLength = 0;
+	u32	ProbeReqLength = 0, NullFunctionDataLength = 0;
+	u8	TxDescLen = TXDESC_SIZE, TxDescOffset = TXDESC_OFFSET;
+	u8	TotalPageNum = 0 , CurtPktPageNum = 0 , RsvdPageNum = 0;
+	u8	*ReservedPagePacket;
+	u16	BufIndex = 0;
+	u32	TotalPacketLen = 0, MaxRsvdPageBufSize = 0, PageSize = 0;
+	RSVDPAGE_LOC	RsvdPageLoc;
+
+#ifdef DBG_FW_DEBUG_MSG_PKT
+	u32	fw_dbg_msg_pkt_len = 0;
+#endif /*DBG_FW_DEBUG_MSG_PKT*/
+
+#ifdef DBG_CONFIG_ERROR_DETECT
+	struct sreset_priv *psrtpriv;
+#endif /* DBG_CONFIG_ERROR_DETECT */
+
+#ifdef CONFIG_MCC_MODE
+	u8 dl_mcc_page = _FAIL;
+#endif /* CONFIG_MCC_MODE */
+	u8 nr_assoc_if;
+
+	_adapter *sta_iface = NULL;
+	_adapter *ap_iface = NULL;
+
+	bool is_wow_mode = _FALSE;
+
+	pHalData = GET_HAL_DATA(adapter);
+#ifdef DBG_CONFIG_ERROR_DETECT
+	psrtpriv = &pHalData->srestpriv;
+#endif
+	pxmitpriv = &adapter->xmitpriv;
+	pwrctl = adapter_to_pwrctl(adapter);
+
+	rtw_hal_get_def_var(adapter, HAL_DEF_TX_PAGE_SIZE, (u8 *)&PageSize);
+
+	if (PageSize == 0) {
+		RTW_ERR("[Error]: %s, PageSize is zero!!\n", __func__);
+		return;
+	}
+	nr_assoc_if = _rtw_mi_assoc_if_num(adapter);
+
+	if ((pwrctl->wowlan_mode == _TRUE && pwrctl->wowlan_in_resume == _FALSE) ||
+		pwrctl->wowlan_ap_mode == _TRUE ||
+		pwrctl->wowlan_p2p_mode == _TRUE)
+		is_wow_mode = _TRUE;
+
+	/*page_num for init time to get rsvd page number*/
+	/* Prepare ReservedPagePacket */
+	if (page_num) {
+		ReservedPagePacket = rtw_zmalloc(MAX_CMDBUF_SZ);
+		if (!ReservedPagePacket) {
+			RTW_WARN("%s: alloc ReservedPagePacket fail!\n", __FUNCTION__);
+			*page_num = 0xFF;
+			return;
+		}
+		RTW_INFO(FUNC_ADPT_FMT" Get [ %s ] RsvdPageNUm  ==>\n",
+			FUNC_ADPT_ARG(adapter), (is_wow_mode) ? "WOW" : "NOR");
+
+	} else {
+		if (is_wow_mode)
+			RsvdPageNum = rtw_hal_get_txbuff_rsvd_page_num(adapter, _TRUE);
+		else
+			RsvdPageNum = rtw_hal_get_txbuff_rsvd_page_num(adapter, _FALSE);
+
+		RTW_INFO(FUNC_ADPT_FMT" PageSize: %d, [ %s ]-RsvdPageNUm: %d\n",
+			FUNC_ADPT_ARG(adapter), PageSize, (is_wow_mode) ? "WOW" : "NOR", RsvdPageNum);
+
+		MaxRsvdPageBufSize = RsvdPageNum * PageSize;
+		if (MaxRsvdPageBufSize > MAX_CMDBUF_SZ) {
+			RTW_ERR("%s MaxRsvdPageBufSize(%d) is larger than MAX_CMDBUF_SZ(%d)",
+				 __func__, MaxRsvdPageBufSize, MAX_CMDBUF_SZ);
+			rtw_warn_on(1);
+			return;
+		}
+
+		pcmdframe = rtw_alloc_cmdxmitframe(pxmitpriv);
+		if (pcmdframe == NULL) {
+			RTW_ERR("%s: alloc ReservedPagePacket fail!\n", __FUNCTION__);
+			return;
+		}
+
+		ReservedPagePacket = pcmdframe->buf_addr;
+	}
+
+	_rtw_memset(&RsvdPageLoc, 0, sizeof(RSVDPAGE_LOC));
+
+	BufIndex = TxDescOffset;
+
+	/*======== beacon content =======*/
+	rtw_hal_construct_beacon(adapter,
+				 &ReservedPagePacket[BufIndex], &BeaconLength);
+
+	/*
+	* When we count the first page size, we need to reserve description size for the RSVD
+	* packet, it will be filled in front of the packet in TXPKTBUF.
+	*/
+	BeaconLength = MAX_BEACON_LEN - TxDescLen;
+	CurtPktPageNum = (u8)PageNum((TxDescLen + BeaconLength), PageSize);
+
+#ifdef CONFIG_FW_HANDLE_TXBCN
+	CurtPktPageNum = CurtPktPageNum * CONFIG_LIMITED_AP_NUM;
+#endif
+	TotalPageNum += CurtPktPageNum;
+
+	BufIndex += (CurtPktPageNum * PageSize);
+
+	#ifdef DBG_RSVD_PAGE_CFG
+	RSVD_PAGE_CFG("Beacon", CurtPktPageNum, TotalPageNum, TotalPacketLen);
+	#endif
+
+	/*======== probe response content ========*/
+	if (pwrctl->wowlan_ap_mode == _TRUE) {/*WOW mode*/
+		#ifdef CONFIG_CONCURRENT_MODE
+		if (nr_assoc_if >= 2)
+			RTW_ERR("Not support > 2 net-interface in WOW\n");
+		#endif
+		/* (4) probe response*/
+		RsvdPageLoc.LocProbeRsp = TotalPageNum;
+		rtw_hal_construct_ProbeRsp(
+			adapter, &ReservedPagePacket[BufIndex],
+			&ProbeRspLength,
+			_FALSE);
+		rtw_hal_fill_fake_txdesc(adapter,
+				 &ReservedPagePacket[BufIndex - TxDescLen],
+				 ProbeRspLength, _FALSE, _FALSE, _FALSE);
+
+		CurtPktPageNum = (u8)PageNum(TxDescLen + ProbeRspLength, PageSize);
+		TotalPageNum += CurtPktPageNum;
+		TotalPacketLen = BufIndex + ProbeRspLength;
+		BufIndex += (CurtPktPageNum * PageSize);
+		#ifdef DBG_RSVD_PAGE_CFG
+		RSVD_PAGE_CFG("ProbeRsp", CurtPktPageNum, TotalPageNum, TotalPacketLen);
+		#endif
+		goto download_page;
+	}
+
+	/*======== ps-poll content * 1 page ========*/
+	sta_iface = adapter;
+	#ifdef CONFIG_CONCURRENT_MODE
+	if (!MLME_IS_STA(sta_iface) && DEV_STA_LD_NUM(adapter_to_dvobj(sta_iface))) {
+		sta_iface = _rtw_search_sta_iface(adapter);
+		RTW_INFO("get ("ADPT_FMT") to create PS-Poll/Null/QosNull\n", ADPT_ARG(sta_iface));
+	}
+	#endif
+
+	if (MLME_IS_STA(sta_iface) || (nr_assoc_if == 0)) {
+		RsvdPageLoc.LocPsPoll = TotalPageNum;
+		RTW_INFO("LocPsPoll: %d\n", RsvdPageLoc.LocPsPoll);
+		rtw_hal_construct_PSPoll(sta_iface,
+					 &ReservedPagePacket[BufIndex], &PSPollLength);
+		rtw_hal_fill_fake_txdesc(sta_iface,
+					 &ReservedPagePacket[BufIndex - TxDescLen],
+					 PSPollLength, _TRUE, _FALSE, _FALSE);
+
+		CurtPktPageNum = (u8)PageNum((TxDescLen + PSPollLength), PageSize);
+
+		TotalPageNum += CurtPktPageNum;
+
+		BufIndex += (CurtPktPageNum * PageSize);
+		#ifdef DBG_RSVD_PAGE_CFG
+		RSVD_PAGE_CFG("PSPoll", CurtPktPageNum, TotalPageNum, TotalPacketLen);
+		#endif
+	}
+
+#ifdef CONFIG_MCC_MODE
+	/*======== MCC * n page ======== */
+	if (MCC_EN(adapter)) {/*Normal mode*/
+		dl_mcc_page = rtw_hal_dl_mcc_fw_rsvd_page(adapter, ReservedPagePacket,
+				&BufIndex, TxDescLen, PageSize, &TotalPageNum, &RsvdPageLoc, page_num);
+	} else {
+		dl_mcc_page = _FAIL;
+	}
+
+	if (dl_mcc_page == _FAIL)
+#endif /* CONFIG_MCC_MODE */
+	{	/*======== null data * 1 page ======== */
+		if (MLME_IS_STA(sta_iface) || (nr_assoc_if == 0)) {
+			RsvdPageLoc.LocNullData = TotalPageNum;
+			RTW_INFO("LocNullData: %d\n", RsvdPageLoc.LocNullData);
+			rtw_hal_construct_NullFunctionData(
+				sta_iface,
+				&ReservedPagePacket[BufIndex],
+				&NullDataLength,
+				_FALSE, 0, 0, _FALSE);
+			rtw_hal_fill_fake_txdesc(sta_iface,
+				 &ReservedPagePacket[BufIndex - TxDescLen],
+				 NullDataLength, _FALSE, _FALSE, _FALSE);
+
+			CurtPktPageNum = (u8)PageNum(TxDescLen + NullDataLength, PageSize);
+
+			TotalPageNum += CurtPktPageNum;
+
+			BufIndex += (CurtPktPageNum * PageSize);
+			#ifdef DBG_RSVD_PAGE_CFG
+			RSVD_PAGE_CFG("NullData", CurtPktPageNum, TotalPageNum, TotalPacketLen);
+			#endif
+		}
+	}
+
+	/*======== Qos null data * 1 page ======== */
+	if (pwrctl->wowlan_mode == _FALSE ||
+		pwrctl->wowlan_in_resume == _TRUE) {/*Normal mode*/	
+		if (MLME_IS_STA(sta_iface) || (nr_assoc_if == 0)) {
+			RsvdPageLoc.LocQosNull = TotalPageNum;
+			RTW_INFO("LocQosNull: %d\n", RsvdPageLoc.LocQosNull);
+			rtw_hal_construct_NullFunctionData(sta_iface,
+						&ReservedPagePacket[BufIndex],
+						&QosNullLength,
+						_TRUE, 0, 0, _FALSE);
+			rtw_hal_fill_fake_txdesc(sta_iface,
+					 &ReservedPagePacket[BufIndex - TxDescLen],
+					 QosNullLength, _FALSE, _FALSE, _FALSE);
+
+			CurtPktPageNum = (u8)PageNum(TxDescLen + QosNullLength,
+						     PageSize);
+
+			TotalPageNum += CurtPktPageNum;
+
+			BufIndex += (CurtPktPageNum * PageSize);
+			#ifdef DBG_RSVD_PAGE_CFG
+			RSVD_PAGE_CFG("QosNull", CurtPktPageNum, TotalPageNum, TotalPacketLen);
+			#endif
+		}
+	}
+
+#ifdef CONFIG_BT_COEXIST
+	/*======== BT Qos null data * 1 page ======== */
+	if (pwrctl->wowlan_mode == _FALSE ||
+		pwrctl->wowlan_in_resume == _TRUE) {/*Normal mode*/
+
+		ap_iface = adapter;
+		#ifdef CONFIG_CONCURRENT_MODE
+		if (!MLME_IS_AP(ap_iface) && DEV_AP_NUM(adapter_to_dvobj(ap_iface))) {	/*DEV_AP_STARTING_NUM*/
+			ap_iface = _rtw_search_ap_iface(adapter);
+			RTW_INFO("get ("ADPT_FMT") to create BTQoSNull\n", ADPT_ARG(ap_iface));
+		}
+		#endif
+
+		if (MLME_IS_AP(ap_iface) || (nr_assoc_if == 0)) {
+			RsvdPageLoc.LocBTQosNull = TotalPageNum;
+
+			RTW_INFO("LocBTQosNull: %d\n", RsvdPageLoc.LocBTQosNull);
+
+			rtw_hal_construct_NullFunctionData(ap_iface,
+						&ReservedPagePacket[BufIndex],
+						&BTQosNullLength,
+						_TRUE, 0, 0, _FALSE);
+
+			rtw_hal_fill_fake_txdesc(ap_iface,
+					&ReservedPagePacket[BufIndex - TxDescLen],
+					BTQosNullLength, _FALSE, _TRUE, _FALSE);
+
+			CurtPktPageNum = (u8)PageNum(TxDescLen + BTQosNullLength,
+							 PageSize);
+
+			TotalPageNum += CurtPktPageNum;
+			BufIndex += (CurtPktPageNum * PageSize);
+
+			#ifdef DBG_RSVD_PAGE_CFG
+			RSVD_PAGE_CFG("BTQosNull", CurtPktPageNum, TotalPageNum, TotalPacketLen);
+			#endif
+		}
+	}
+#endif /* CONFIG_BT_COEXIT */
+
+	TotalPacketLen = BufIndex;
+
+#ifdef DBG_FW_DEBUG_MSG_PKT
+		/*======== FW DEBUG MSG * n page ======== */
+		RsvdPageLoc.loc_fw_dbg_msg_pkt = TotalPageNum;
+		RTW_INFO("loc_fw_dbg_msg_pkt: %d\n", RsvdPageLoc.loc_fw_dbg_msg_pkt);
+		rtw_hal_construct_fw_dbg_msg_pkt(
+			adapter,
+			&ReservedPagePacket[BufIndex],
+			&fw_dbg_msg_pkt_len);
+
+		rtw_hal_fill_fake_txdesc(adapter,
+				 &ReservedPagePacket[BufIndex - TxDescLen],
+				 fw_dbg_msg_pkt_len, _FALSE, _FALSE, _FALSE);
+
+		CurtPktPageNum = (u8)PageNum(TxDescLen + fw_dbg_msg_pkt_len, PageSize);
+
+		TotalPageNum += CurtPktPageNum;
+
+		TotalPacketLen = BufIndex + fw_dbg_msg_pkt_len;
+		BufIndex += (CurtPktPageNum * PageSize);
+#endif /*DBG_FW_DEBUG_MSG_PKT*/
+
+#ifdef CONFIG_WOWLAN
+	/*======== WOW * n page ======== */
+	if (pwrctl->wowlan_mode == _TRUE &&
+		pwrctl->wowlan_in_resume == _FALSE) {/*WOW mode*/
+		rtw_hal_set_wow_fw_rsvd_page(adapter, ReservedPagePacket,
+					     BufIndex, TxDescLen, PageSize,
+			     &TotalPageNum, &TotalPacketLen, &RsvdPageLoc);
+	}
+#endif /* CONFIG_WOWLAN */
+
+#ifdef CONFIG_P2P_WOWLAN
+	/*======== P2P WOW * n page ======== */
+	if (_TRUE == pwrctl->wowlan_p2p_mode) {/*WOW mode*/
+		rtw_hal_set_p2p_wow_fw_rsvd_page(adapter, ReservedPagePacket,
+						 BufIndex, TxDescLen, PageSize,
+				 &TotalPageNum, &TotalPacketLen, &RsvdPageLoc);
+	}
+#endif /* CONFIG_P2P_WOWLAN */
+
+#ifdef CONFIG_LPS_PG
+	/*======== LPS PG * 1 page ======== */
+	/* must reserved last 1 x page for LPS PG Info*/
+	pwrctl->lpspg_rsvd_page_locate = TotalPageNum;
+	pwrctl->blpspg_info_up = _TRUE;
+	if (page_num)
+		TotalPageNum += LPS_PG_INFO_RSVD_PAGE_NUM;
+
+	#ifdef DBG_RSVD_PAGE_CFG
+	RSVD_PAGE_CFG("LPS_PG", LPS_PG_INFO_RSVD_PAGE_NUM,
+		(page_num) ? TotalPageNum : (TotalPageNum + LPS_PG_INFO_RSVD_PAGE_NUM),
+		TotalPacketLen);
+	#endif
+
+#endif
+
+	/*Note:  BufIndex already add a TxDescOffset offset in first Beacon page
+	* The "TotalPacketLen" is calculate by BufIndex.
+	* We need to decrease TxDescOffset before doing length check. by yiwei
+	*/
+	TotalPacketLen = TotalPacketLen - TxDescOffset;
+
+download_page:
+	if (page_num) {
+		*page_num = TotalPageNum;
+		rtw_mfree(ReservedPagePacket, MAX_CMDBUF_SZ);
+		ReservedPagePacket = NULL;
+		RTW_INFO(FUNC_ADPT_FMT" Get [ %s ] RsvdPageNUm <==\n",
+			FUNC_ADPT_ARG(adapter), (is_wow_mode) ? "WOW" : "NOR");
+		return;
+	}
+
+	/* RTW_INFO("%s BufIndex(%d), TxDescLen(%d), PageSize(%d)\n",__func__, BufIndex, TxDescLen, PageSize);*/
+	RTW_INFO("%s PageNum(%d), pktlen(%d)\n",
+		 __func__, TotalPageNum, TotalPacketLen);
+
+#ifdef CONFIG_LPS_PG
+	if ((TotalPageNum + LPS_PG_INFO_RSVD_PAGE_NUM) > RsvdPageNum) {
+		pwrctl->lpspg_rsvd_page_locate = 0;
+		pwrctl->blpspg_info_up = _FALSE;
+
+		RTW_ERR("%s [LPS_PG] rsvd page %d  is not enough! need %d pages\n",
+			__func__, RsvdPageNum, (TotalPageNum + LPS_PG_INFO_RSVD_PAGE_NUM));
+		rtw_warn_on(1);
+	}
+#endif
+
+	if (TotalPacketLen > MaxRsvdPageBufSize) {
+		RTW_ERR("%s : rsvd page size is not enough!!TotalPacketLen %d, MaxRsvdPageBufSize %d\n",
+			 __FUNCTION__, TotalPacketLen, MaxRsvdPageBufSize);
+		rtw_warn_on(1);
+		goto error;
+	} else {
+		/* update attribute */
+		pattrib = &pcmdframe->attrib;
+		update_mgntframe_attrib(adapter, pattrib);
+		pattrib->qsel = QSLT_BEACON;
+		pattrib->pktlen = TotalPacketLen;
+		pattrib->last_txcmdsz = TotalPacketLen;
+#ifdef CONFIG_PCI_HCI
+		dump_mgntframe(adapter, pcmdframe);
+#else
+		dump_mgntframe_and_wait(adapter, pcmdframe, 100);
+#endif
+	}
+
+	RTW_INFO("%s: Set RSVD page location to Fw ,TotalPacketLen(%d), TotalPageNum(%d)\n",
+		 __func__, TotalPacketLen, TotalPageNum);
+#ifdef DBG_DUMP_SET_RSVD_PAGE
+	RTW_INFO(" ==================================================\n");
+	RTW_INFO_DUMP("\n", ReservedPagePacket, TotalPacketLen);
+	RTW_INFO(" ==================================================\n");
+#endif
+
+
+	if (check_fwstate(pmlmepriv, _FW_LINKED)
+		|| MLME_IS_AP(adapter) || MLME_IS_MESH(adapter)){
+		rtw_hal_set_FwRsvdPage_cmd(adapter, &RsvdPageLoc);
+#ifdef DBG_FW_DEBUG_MSG_PKT
+		rtw_hal_set_fw_dbg_msg_pkt_rsvd_page_cmd(adapter, &RsvdPageLoc);
+#endif /*DBG_FW_DEBUG_MSG_PKT*/
+#ifdef CONFIG_WOWLAN
+		if (pwrctl->wowlan_mode == _TRUE &&
+			pwrctl->wowlan_in_resume == _FALSE)
+			rtw_hal_set_FwAoacRsvdPage_cmd(adapter, &RsvdPageLoc);
+#endif /* CONFIG_WOWLAN */
+#ifdef CONFIG_AP_WOWLAN
+		if (pwrctl->wowlan_ap_mode == _TRUE)
+			rtw_hal_set_ap_rsvdpage_loc_cmd(adapter, &RsvdPageLoc);
+#endif /* CONFIG_AP_WOWLAN */
+	} else if (pwrctl->wowlan_pno_enable) {
+#ifdef CONFIG_PNO_SUPPORT
+		rtw_hal_set_FwAoacRsvdPage_cmd(adapter, &RsvdPageLoc);
+		if (pwrctl->wowlan_in_resume)
+			rtw_hal_set_scan_offload_info_cmd(adapter,
+							  &RsvdPageLoc, 0);
+		else
+			rtw_hal_set_scan_offload_info_cmd(adapter,
+							  &RsvdPageLoc, 1);
+#endif /* CONFIG_PNO_SUPPORT */
+	}
+
+#ifdef CONFIG_P2P_WOWLAN
+	if (_TRUE == pwrctl->wowlan_p2p_mode)
+		rtw_hal_set_FwP2PRsvdPage_cmd(adapter, &RsvdPageLoc);
+#endif /* CONFIG_P2P_WOWLAN */
+
+	return;
+error:
+	rtw_free_xmitframe(pxmitpriv, pcmdframe);
+}
+
+void rtw_hal_set_fw_rsvd_page(struct _ADAPTER *adapter, bool finished)
+{
+	if (finished)
+		rtw_mi_tx_beacon_hdl(adapter);
+	else
+		_rtw_hal_set_fw_rsvd_page(adapter, finished, NULL);
+}
+
+/**
+ * rtw_hal_get_rsvd_page_num() - Get needed reserved page number
+ * @adapter:	struct _ADAPTER*
+ *
+ * Caculate needed reserved page number.
+ * In different state would get different number, for example normal mode and
+ * WOW mode would need different reserved page size.
+ *
+ * Return the number of reserved page which driver need.
+ */
+u8 rtw_hal_get_rsvd_page_num(struct _ADAPTER *adapter)
+{
+	u8 num = 0;
+
+
+	_rtw_hal_set_fw_rsvd_page(adapter, _FALSE, &num);
+
+	return num;
+}
+
+static void hw_var_set_bcn_func(_adapter *adapter, u8 enable)
+{
+	u32 bcn_ctrl_reg;
+
+#ifdef CONFIG_CONCURRENT_MODE
+	if (adapter->hw_port == HW_PORT1)
+		bcn_ctrl_reg = REG_BCN_CTRL_1;
+	else
+#endif
+		bcn_ctrl_reg = REG_BCN_CTRL;
+
+	if (enable)
+		rtw_write8(adapter, bcn_ctrl_reg, (EN_BCN_FUNCTION | EN_TXBCN_RPT));
+	else {
+		u8 val8;
+
+		val8 = rtw_read8(adapter, bcn_ctrl_reg);
+		val8 &= ~(EN_BCN_FUNCTION | EN_TXBCN_RPT);
+
+#ifdef CONFIG_BT_COEXIST
+		if (GET_HAL_DATA(adapter)->EEPROMBluetoothCoexist == 1) {
+			/* Always enable port0 beacon function for PSTDMA */
+			if (REG_BCN_CTRL == bcn_ctrl_reg)
+				val8 |= EN_BCN_FUNCTION;
+		}
+#endif
+
+		rtw_write8(adapter, bcn_ctrl_reg, val8);
+	}
+
+#ifdef CONFIG_RTL8192F
+	if (IS_HARDWARE_TYPE_8192F(adapter)) {
+		u16 val16, val16_ori;
+
+		val16_ori = val16 = rtw_read16(adapter, REG_WLAN_ACT_MASK_CTRL_1);
+
+		#ifdef CONFIG_CONCURRENT_MODE
+		if (adapter->hw_port == HW_PORT1) {
+			if (enable)
+				val16 |= EN_PORT_1_FUNCTION;
+			else
+				val16 &= ~EN_PORT_1_FUNCTION;
+		} else
+		#endif
+		{
+			if (enable)
+				val16 |= EN_PORT_0_FUNCTION;
+			else
+				val16 &= ~EN_PORT_0_FUNCTION;
+
+			#ifdef CONFIG_BT_COEXIST
+			if (GET_HAL_DATA(adapter)->EEPROMBluetoothCoexist == 1)
+				val16 |= EN_PORT_0_FUNCTION;
+			#endif
+		}
+
+		if (val16 != val16_ori)
+			rtw_write16(adapter, REG_WLAN_ACT_MASK_CTRL_1,  val16);
+	}
+#endif
+}
+
+static void hw_var_set_mlme_disconnect(_adapter *adapter)
+{
+	u8 val8;
+
+	/* reject all data frames */
+#ifdef CONFIG_CONCURRENT_MODE
+	if (rtw_mi_check_status(adapter, MI_LINKED) == _FALSE)
+#endif
+		rtw_write16(adapter, REG_RXFLTMAP2, 0x0000);
+
+#ifdef CONFIG_CONCURRENT_MODE
+	if (adapter->hw_port == HW_PORT1) {
+		/* reset TSF1 */
+		rtw_write8(adapter, REG_DUAL_TSF_RST, BIT(1));
+
+		/* disable update TSF1 */
+		rtw_iface_disable_tsf_update(adapter);
+
+		if (!IS_HARDWARE_TYPE_8723D(adapter)
+			&& !IS_HARDWARE_TYPE_8192F(adapter)
+			&& !IS_HARDWARE_TYPE_8710B(adapter)
+		) {
+			/* disable Port1's beacon function */
+			val8 = rtw_read8(adapter, REG_BCN_CTRL_1);
+			val8 &= ~EN_BCN_FUNCTION;
+			rtw_write8(adapter, REG_BCN_CTRL_1, val8);
+		}
+	} else
+#endif
+	{
+		/* reset TSF */
+		rtw_write8(adapter, REG_DUAL_TSF_RST, BIT(0));
+
+		/* disable update TSF */
+		rtw_iface_disable_tsf_update(adapter);
+	}
+}
+
+static void hw_var_set_mlme_sitesurvey(_adapter *adapter, u8 enable)
+{
+	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
+	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
+	u16 value_rxfltmap2;
+	int i;
+	_adapter *iface;
+
+#ifdef DBG_IFACE_STATUS
+	DBG_IFACE_STATUS_DUMP(adapter);
+#endif
+
+#ifdef CONFIG_FIND_BEST_CHANNEL
+	/* Receive all data frames */
+	value_rxfltmap2 = 0xFFFF;
+#else
+	/* not to receive data frame */
+	value_rxfltmap2 = 0;
+#endif
+
+	if (enable) { /* under sitesurvey */
+		/*
+		* 1. configure REG_RXFLTMAP2
+		* 2. disable TSF update &  buddy TSF update to avoid updating wrong TSF due to clear RCR_CBSSID_BCN
+		* 3. config RCR to receive different BSSID BCN or probe rsp
+		*/
+		rtw_write16(adapter, REG_RXFLTMAP2, value_rxfltmap2);
+
+		rtw_hal_rcr_set_chk_bssid(adapter, MLME_SCAN_ENTER);
+
+		/* Save orignal RRSR setting. needed? */
+		hal_data->RegRRSR = rtw_read16(adapter, REG_RRSR);
+
+		#if defined(CONFIG_BEAMFORMING) && (defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A))
+		if (IS_8812_SERIES(hal_data->version_id) || IS_8821_SERIES(hal_data->version_id)) {
+			/* set 718[1:0]=2'b00 to avoid BF scan hang */
+			hal_data->backup_snd_ptcl_ctrl = rtw_read8(adapter, REG_SND_PTCL_CTRL_8812A);
+			rtw_write8(adapter, REG_SND_PTCL_CTRL_8812A, (hal_data->backup_snd_ptcl_ctrl & 0xfc));
+		}
+		#endif
+
+		if (rtw_mi_get_ap_num(adapter) || rtw_mi_get_mesh_num(adapter))
+			StopTxBeacon(adapter);
+	} else { /* sitesurvey done */
+		/*
+		* 1. enable rx data frame
+		* 2. config RCR not to receive different BSSID BCN or probe rsp
+		* 3. doesn't enable TSF update &  buddy TSF right now to avoid HW conflict
+		*	 so, we enable TSF update when rx first BCN after sitesurvey done
+		*/
+		if (rtw_mi_check_fwstate(adapter, _FW_LINKED | WIFI_AP_STATE | WIFI_MESH_STATE)) {
+			/* enable to rx data frame */
+			rtw_write16(adapter, REG_RXFLTMAP2, 0xFFFF);
+		}
+
+		rtw_hal_rcr_set_chk_bssid(adapter, MLME_SCAN_DONE);
+
+		/* Restore orignal RRSR setting. needed? */
+		rtw_write16(adapter, REG_RRSR, hal_data->RegRRSR);
+
+		#if defined(CONFIG_BEAMFORMING) && (defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A))
+		if (IS_8812_SERIES(hal_data->version_id) || IS_8821_SERIES(hal_data->version_id)) {
+			/* Restore orignal 0x718 setting*/
+			rtw_write8(adapter, REG_SND_PTCL_CTRL_8812A, hal_data->backup_snd_ptcl_ctrl);
+		}
+		#endif
+
+		if (rtw_mi_get_ap_num(adapter) || rtw_mi_get_mesh_num(adapter)) {
+			ResumeTxBeacon(adapter);
+			rtw_mi_tx_beacon_hdl(adapter);
+		}
+	}
+}
+
+static void hw_var_set_mlme_join(_adapter *adapter, u8 type)
+{
+	u8 val8;
+	u16 val16;
+	u32 val32;
+	u8 RetryLimit = RL_VAL_STA;
+	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
+	struct mlme_priv *pmlmepriv = &adapter->mlmepriv;
+
+#ifdef CONFIG_CONCURRENT_MODE
+	if (type == 0) {
+		/* prepare to join */
+		if (rtw_mi_get_ap_num(adapter) || rtw_mi_get_mesh_num(adapter))
+			StopTxBeacon(adapter);
+
+		/* enable to rx data frame.Accept all data frame */
+		rtw_write16(adapter, REG_RXFLTMAP2, 0xFFFF);
+
+		if (check_fwstate(pmlmepriv, WIFI_STATION_STATE) == _TRUE)
+			RetryLimit = (hal_data->CustomerID == RT_CID_CCX) ? RL_VAL_AP : RL_VAL_STA;
+		else /* Ad-hoc Mode */
+			RetryLimit = RL_VAL_AP;
+
+		rtw_iface_enable_tsf_update(adapter);
+
+	} else if (type == 1) {
+		/* joinbss_event call back when join res < 0 */
+		if (rtw_mi_check_status(adapter, MI_LINKED) == _FALSE)
+			rtw_write16(adapter, REG_RXFLTMAP2, 0x00);
+
+		rtw_iface_disable_tsf_update(adapter);
+
+		if (rtw_mi_get_ap_num(adapter) || rtw_mi_get_mesh_num(adapter)) {
+			ResumeTxBeacon(adapter);
+
+			/* reset TSF 1/2 after ResumeTxBeacon */
+			rtw_write8(adapter, REG_DUAL_TSF_RST, BIT(1) | BIT(0));
+		}
+
+	} else if (type == 2) {
+		/* sta add event call back */
+		if (check_fwstate(pmlmepriv, WIFI_ADHOC_STATE | WIFI_ADHOC_MASTER_STATE)) {
+			/* fixed beacon issue for 8191su........... */
+			rtw_write8(adapter, 0x542 , 0x02);
+			RetryLimit = RL_VAL_AP;
+		}
+
+		if (rtw_mi_get_ap_num(adapter) || rtw_mi_get_mesh_num(adapter)) {
+			ResumeTxBeacon(adapter);
+
+			/* reset TSF 1/2 after ResumeTxBeacon */
+			rtw_write8(adapter, REG_DUAL_TSF_RST, BIT(1) | BIT(0));
+		}
+	}
+
+	val16 = BIT_SRL(RetryLimit) | BIT_LRL(RetryLimit);
+	rtw_write16(adapter, REG_RETRY_LIMIT, val16);
+#else /* !CONFIG_CONCURRENT_MODE */
+	if (type == 0) { /* prepare to join */
+		/* enable to rx data frame.Accept all data frame */
+		rtw_write16(adapter, REG_RXFLTMAP2, 0xFFFF);
+
+		if (check_fwstate(pmlmepriv, WIFI_STATION_STATE) == _TRUE)
+			RetryLimit = (hal_data->CustomerID == RT_CID_CCX) ? RL_VAL_AP : RL_VAL_STA;
+		else /* Ad-hoc Mode */
+			RetryLimit = RL_VAL_AP;
+
+		rtw_iface_enable_tsf_update(adapter);
+
+	} else if (type == 1) { /* joinbss_event call back when join res < 0 */
+		rtw_write16(adapter, REG_RXFLTMAP2, 0x00);
+
+		rtw_iface_disable_tsf_update(adapter);
+
+	} else if (type == 2) { /* sta add event call back */
+		if (check_fwstate(pmlmepriv, WIFI_ADHOC_STATE | WIFI_ADHOC_MASTER_STATE))
+			RetryLimit = RL_VAL_AP;
+	}
+
+	val16 = BIT_SRL(RetryLimit) | BIT_LRL(RetryLimit);
+	rtw_write16(adapter, REG_RETRY_LIMIT, val16);
+#endif /* !CONFIG_CONCURRENT_MODE */
+}
+
+#ifdef CONFIG_TSF_RESET_OFFLOAD
+static int rtw_hal_h2c_reset_tsf(_adapter *adapter, u8 reset_port)
+{
+	u8 buf[2];
+	int ret;
+
+	if (reset_port == HW_PORT0) {
+		buf[0] = 0x1;
+		buf[1] = 0;
+	} else {
+		buf[0] = 0x0;
+		buf[1] = 0x1;
+	}
+
+	ret = rtw_hal_fill_h2c_cmd(adapter, H2C_RESET_TSF, 2, buf);
+
+	return ret;
+}
+
+int rtw_hal_reset_tsf(_adapter *adapter, u8 reset_port)
+{
+	u8 reset_cnt_before = 0, reset_cnt_after = 0, loop_cnt = 0;
+	u32 reg_reset_tsf_cnt = (reset_port == HW_PORT0) ?
+				REG_FW_RESET_TSF_CNT_0 : REG_FW_RESET_TSF_CNT_1;
+	int ret;
+
+	/* site survey will cause reset tsf fail */
+	rtw_mi_buddy_scan_abort(adapter, _FALSE);
+	reset_cnt_after = reset_cnt_before = rtw_read8(adapter, reg_reset_tsf_cnt);
+	ret = rtw_hal_h2c_reset_tsf(adapter, reset_port);
+	if (ret != _SUCCESS)
+		return ret;
+
+	while ((reset_cnt_after == reset_cnt_before) && (loop_cnt < 10)) {
+		rtw_msleep_os(100);
+		loop_cnt++;
+		reset_cnt_after = rtw_read8(adapter, reg_reset_tsf_cnt);
+	}
+
+	return (loop_cnt >= 10) ? _FAIL : _SUCCESS;
+}
+#endif /* CONFIG_TSF_RESET_OFFLOAD */
+
+#ifdef CONFIG_HW_P0_TSF_SYNC
+#ifdef CONFIG_CONCURRENT_MODE
+static void hw_port0_tsf_sync_sel(_adapter *adapter, u8 benable, u8 hw_port, u16 tr_offset)
+{
+	u8 val8;
+	u8 client_id = 0;
+	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
+
+#ifdef CONFIG_MCC_MODE
+	if (MCC_EN(adapter) && (rtw_hal_check_mcc_status(adapter, MCC_STATUS_DOING_MCC))) {
+		RTW_INFO("[MCC] do not set HW TSF sync\n");
+		return;
+	}
+#endif
+	/* check if port0 is already synced */
+	if (benable && dvobj->p0_tsf.sync_port != MAX_HW_PORT && dvobj->p0_tsf.sync_port == hw_port) {
+		RTW_WARN(FUNC_ADPT_FMT ": port0 already enable TSF sync(%d)\n",
+			FUNC_ADPT_ARG(adapter), dvobj->p0_tsf.sync_port);
+		return;
+	}
+
+	/* check if port0 already disable sync */
+	if (!benable && dvobj->p0_tsf.sync_port == MAX_HW_PORT) {
+		RTW_WARN(FUNC_ADPT_FMT ": port0 already disable TSF sync\n", FUNC_ADPT_ARG(adapter));
+		return;
+	}
+
+	/* check if port0 sync to port0 */
+	if (benable && hw_port == HW_PORT0) {
+		RTW_ERR(FUNC_ADPT_FMT ": hw_port is port0 under enable\n", FUNC_ADPT_ARG(adapter));
+		rtw_warn_on(1);
+		return;
+	}
+
+	/*0x5B4 [6:4] :SYNC_CLI_SEL - The selector for the CLINT port of sync tsft source for port 0*/
+	/*	Bit[5:4] : 0 for clint0, 1 for clint1, 2 for clint2, 3 for clint3.
+		Bit6 : 1= enable sync to port 0. 0=disable sync to port 0.*/
+
+	val8 = rtw_read8(adapter, REG_TIMER0_SRC_SEL);
+
+	if (benable) {
+		/*Disable Port0's beacon function*/
+		rtw_write8(adapter, REG_BCN_CTRL, rtw_read8(adapter, REG_BCN_CTRL) & ~BIT_EN_BCN_FUNCTION);
+
+		/*Reg 0x518[15:0]: TSFTR_SYN_OFFSET*/
+		if (tr_offset)
+			rtw_write16(adapter, REG_TSFTR_SYN_OFFSET, tr_offset);
+
+		/*reg 0x577[6]=1*/	/*auto sync by tbtt*/
+		rtw_write8(adapter, REG_MISC_CTRL, rtw_read8(adapter, REG_MISC_CTRL) | BIT_AUTO_SYNC_BY_TBTT);
+
+		if (HW_PORT1 == hw_port)
+			client_id = 0;
+		else if (HW_PORT2 == hw_port)
+			client_id = 1;
+		else if (HW_PORT3 == hw_port)
+			client_id = 2;
+		else if (HW_PORT4 == hw_port)
+			client_id = 3;
+
+		val8 &= 0x8F;
+		val8 |= (BIT(6) | (client_id << 4));
+
+		dvobj->p0_tsf.sync_port = hw_port;
+		dvobj->p0_tsf.offset = tr_offset;
+		rtw_write8(adapter, REG_TIMER0_SRC_SEL, val8);
+
+		/*Enable Port0's beacon function*/
+		rtw_write8(adapter, REG_BCN_CTRL, rtw_read8(adapter, REG_BCN_CTRL)  | BIT_EN_BCN_FUNCTION);
+		RTW_INFO("%s Port_%d TSF sync to P0, timer offset :%d\n", __func__, hw_port, tr_offset);
+	} else {
+		val8 &= ~BIT(6);
+
+		dvobj->p0_tsf.sync_port = MAX_HW_PORT;
+		dvobj->p0_tsf.offset = 0;
+		rtw_write8(adapter, REG_TIMER0_SRC_SEL, val8);
+		RTW_INFO("%s P0 TSF sync disable\n", __func__);
+	}
+}
+static _adapter * _search_ld_sta(_adapter *adapter, u8 include_self)
+{
+	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
+	u8 i;
+	_adapter *iface = NULL;
+
+	if (rtw_mi_get_assoced_sta_num(adapter) == 0) {
+		RTW_ERR("STA_LD_NUM == 0\n");
+		rtw_warn_on(1);
+	}
+
+	for (i = 0; i < dvobj->iface_nums; i++) {
+		iface = dvobj->padapters[i];
+		if (!iface)
+			continue;
+		if (include_self == _FALSE && adapter == iface)
+			continue;
+		if (is_client_associated_to_ap(iface))
+			break;
+	}
+	if (iface)
+		RTW_INFO("search STA iface -"ADPT_FMT"\n", ADPT_ARG(iface));
+	return iface;
+}
+#endif /*CONFIG_CONCURRENT_MODE*/
+/*Correct port0's TSF*/
+/*#define DBG_P0_TSF_SYNC*/
+void hw_var_set_correct_tsf(PADAPTER adapter, u8 mlme_state)
+{
+#ifdef CONFIG_CONCURRENT_MODE
+	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
+	u8 p0_tsfsync = _FALSE;
+	struct mlme_ext_priv *pmlmeext = &adapter->mlmeextpriv;
+	struct mlme_ext_info *pmlmeinfo = &pmlmeext->mlmext_info;
+	_adapter *sta_if = NULL;
+	u8 hw_port;
+
+	RTW_INFO(FUNC_ADPT_FMT "\n", FUNC_ADPT_ARG(adapter));
+	#ifdef DBG_P0_TSF_SYNC
+	RTW_INFO("[TSF_SYNC] AP_NUM = %d\n", rtw_mi_get_ap_num(adapter));
+	RTW_INFO("[TSF_SYNC] MESH_NUM = %d\n", rtw_mi_get_mesh_num(adapter));
+	RTW_INFO("[TSF_SYNC] LD_STA_NUM = %d\n", rtw_mi_get_assoced_sta_num(adapter));
+	if (dvobj->p0_tsf.sync_port == MAX_HW_PORT)
+		RTW_INFO("[TSF_SYNC] org p0 sync port = N/A\n");
+	else
+		RTW_INFO("[TSF_SYNC] org p0 sync port = %d\n", dvobj->p0_tsf.sync_port);
+	RTW_INFO("[TSF_SYNC] timer offset = %d\n", dvobj->p0_tsf.offset);
+	#endif
+	switch (mlme_state) {
+		case MLME_STA_CONNECTED :
+			{
+				hw_port = rtw_hal_get_port(adapter);
+
+				if (!MLME_IS_STA(adapter)) {
+					RTW_ERR("STA CON state,but iface("ADPT_FMT") is not STA\n", ADPT_ARG(adapter));
+					rtw_warn_on(1);
+				}
+
+				if ((dvobj->p0_tsf.sync_port != MAX_HW_PORT) && (hw_port == HW_PORT0)) {
+					RTW_ERR(ADPT_FMT" is STA with P0 connected => DIS P0_TSF_SYNC\n", ADPT_ARG(adapter));
+					rtw_warn_on(1);
+					hw_port0_tsf_sync_sel(adapter, _FALSE, 0, 0);
+				}
+
+				if ((dvobj->p0_tsf.sync_port == MAX_HW_PORT) &&
+					(rtw_mi_get_ap_num(adapter) || rtw_mi_get_mesh_num(adapter))) {
+					hw_port0_tsf_sync_sel(adapter, _TRUE, hw_port, 50);/*timer offset 50ms*/
+					#ifdef DBG_P0_TSF_SYNC
+					RTW_INFO("[TSF_SYNC] STA_LINKED => EN P0_TSF_SYNC\n");
+					#endif
+				}
+			}
+			break;
+		case MLME_STA_DISCONNECTED :
+			{
+				hw_port = rtw_hal_get_port(adapter);
+
+				if (!MLME_IS_STA(adapter)) {
+					RTW_ERR("STA DIS_CON state,but iface("ADPT_FMT") is not STA\n", ADPT_ARG(adapter));
+					rtw_warn_on(1);
+				}
+
+				if (dvobj->p0_tsf.sync_port == hw_port) {
+					if (rtw_mi_get_assoced_sta_num(adapter) >= 2) {
+						/* search next appropriate sta*/
+						sta_if = _search_ld_sta(adapter, _FALSE);
+						if (sta_if) {
+							hw_port = rtw_hal_get_port(sta_if);
+							hw_port0_tsf_sync_sel(adapter, _TRUE, hw_port, 50);/*timer offset 50ms*/
+							#ifdef DBG_P0_TSF_SYNC
+							RTW_INFO("[TSF_SYNC] STA_DIS_CON => CHANGE P0_TSF_SYNC\n");
+							#endif
+						}
+					} else if (rtw_mi_get_assoced_sta_num(adapter) == 1) {
+						hw_port0_tsf_sync_sel(adapter, _FALSE, 0, 0);
+						#ifdef DBG_P0_TSF_SYNC
+						RTW_INFO("[TSF_SYNC] STA_DIS_CON => DIS P0_TSF_SYNC\n");
+						#endif
+					}
+				}
+			}
+			break;
+		case MLME_AP_STARTED :
+		case MLME_MESH_STARTED :
+			{
+				if (!(MLME_IS_AP(adapter) || MLME_IS_MESH(adapter))) {
+					RTW_ERR("AP START state,but iface("ADPT_FMT") is not AP\n", ADPT_ARG(adapter));
+					rtw_warn_on(1);
+				}
+
+				if ((dvobj->p0_tsf.sync_port == MAX_HW_PORT) &&
+					rtw_mi_get_assoced_sta_num(adapter)) {
+					/* get port of sta */
+					sta_if = _search_ld_sta(adapter, _FALSE);
+					if (sta_if) {
+						hw_port = rtw_hal_get_port(sta_if);
+						hw_port0_tsf_sync_sel(adapter, _TRUE, hw_port, 50);/*timer offset 50ms*/
+						#ifdef DBG_P0_TSF_SYNC
+						RTW_INFO("[TSF_SYNC] AP_START => EN P0_TSF_SYNC\n");
+						#endif
+					}
+				}
+			}
+			break;
+		case MLME_AP_STOPPED :
+		case MLME_MESH_STOPPED :
+			{
+				if (!(MLME_IS_AP(adapter) || MLME_IS_MESH(adapter))) {
+					RTW_ERR("AP START state,but iface("ADPT_FMT") is not AP\n", ADPT_ARG(adapter));
+					rtw_warn_on(1);
+				}
+				/*stop ap mode*/
+				if ((rtw_mi_get_ap_num(adapter) + rtw_mi_get_mesh_num(adapter) == 1) &&
+					(dvobj->p0_tsf.sync_port != MAX_HW_PORT)) {
+					hw_port0_tsf_sync_sel(adapter, _FALSE, 0, 0);
+					#ifdef DBG_P0_TSF_SYNC
+					RTW_INFO("[TSF_SYNC] AP_STOP => DIS P0_TSF_SYNC\n");
+					#endif
+				}
+			}
+			break;
+		default :
+			RTW_ERR(FUNC_ADPT_FMT" unknow state(0x%02x)\n", FUNC_ADPT_ARG(adapter), mlme_state);
+			break;
+	}
+
+	/*#ifdef DBG_P0_TSF_SYNC*/
+	#if 1
+	if (dvobj->p0_tsf.sync_port == MAX_HW_PORT)
+		RTW_INFO("[TSF_SYNC] p0 sync port = N/A\n");
+	else
+		RTW_INFO("[TSF_SYNC] p0 sync port = %d\n", dvobj->p0_tsf.sync_port);
+	RTW_INFO("[TSF_SYNC] timer offset = %d\n", dvobj->p0_tsf.offset);
+	#endif
+#endif /*CONFIG_CONCURRENT_MODE*/
+}
+
+#else
+static void rtw_hal_correct_tsf(_adapter *padapter, u8 hw_port, u64 tsf)
+{
+	if (hw_port == HW_PORT0) {
+		/*disable related TSF function*/
+		rtw_write8(padapter, REG_BCN_CTRL, rtw_read8(padapter, REG_BCN_CTRL) & (~EN_BCN_FUNCTION));
+#if defined(CONFIG_RTL8192F)
+		rtw_write16(padapter, REG_WLAN_ACT_MASK_CTRL_1, rtw_read16(padapter,
+					REG_WLAN_ACT_MASK_CTRL_1) & ~EN_PORT_0_FUNCTION);
+#endif
+
+		rtw_write32(padapter, REG_TSFTR, tsf);
+		rtw_write32(padapter, REG_TSFTR + 4, tsf >> 32);
+
+		/*enable related TSF function*/
+		rtw_write8(padapter, REG_BCN_CTRL, rtw_read8(padapter, REG_BCN_CTRL) | EN_BCN_FUNCTION);
+#if defined(CONFIG_RTL8192F)
+		rtw_write16(padapter, REG_WLAN_ACT_MASK_CTRL_1, rtw_read16(padapter,
+					REG_WLAN_ACT_MASK_CTRL_1) | EN_PORT_0_FUNCTION);
+#endif
+	} else if (hw_port == HW_PORT1) {
+		/*disable related TSF function*/
+		rtw_write8(padapter, REG_BCN_CTRL_1, rtw_read8(padapter, REG_BCN_CTRL_1) & (~EN_BCN_FUNCTION));
+#if defined(CONFIG_RTL8192F)
+		rtw_write16(padapter, REG_WLAN_ACT_MASK_CTRL_1, rtw_read16(padapter,
+					REG_WLAN_ACT_MASK_CTRL_1) & ~EN_PORT_1_FUNCTION);
+#endif
+
+		rtw_write32(padapter, REG_TSFTR1, tsf);
+		rtw_write32(padapter, REG_TSFTR1 + 4, tsf >> 32);
+
+		/*enable related TSF function*/
+		rtw_write8(padapter, REG_BCN_CTRL_1, rtw_read8(padapter, REG_BCN_CTRL_1) | EN_BCN_FUNCTION);
+#if defined(CONFIG_RTL8192F)
+		rtw_write16(padapter, REG_WLAN_ACT_MASK_CTRL_1, rtw_read16(padapter,
+					REG_WLAN_ACT_MASK_CTRL_1) | EN_PORT_1_FUNCTION);
+#endif
+	} else
+		RTW_INFO("%s-[WARN] "ADPT_FMT" invalid hw_port:%d\n", __func__, ADPT_ARG(padapter), hw_port);
+}
+
+static void hw_var_set_correct_tsf(_adapter *adapter, u8 mlme_state)
+{
+#ifdef CONFIG_MI_WITH_MBSSID_CAM
+	/*do nothing*/
+#else
+	u64 tsf;
+	struct mlme_ext_priv *mlmeext = &adapter->mlmeextpriv;
+	struct mlme_ext_info *mlmeinfo = &(mlmeext->mlmext_info);
+
+	tsf = mlmeext->TSFValue - rtw_modular64(mlmeext->TSFValue, (mlmeinfo->bcn_interval * 1024)) - 1024; /*us*/
+
+	if ((mlmeinfo->state & 0x03) == WIFI_FW_ADHOC_STATE
+		|| (mlmeinfo->state & 0x03) == WIFI_FW_AP_STATE)
+		StopTxBeacon(adapter);
+
+	rtw_hal_correct_tsf(adapter, adapter->hw_port, tsf);
+
+#ifdef CONFIG_CONCURRENT_MODE
+	/* Update buddy port's TSF if it is SoftAP/Mesh for beacon TX issue! */
+	if ((mlmeinfo->state & 0x03) == WIFI_FW_STATION_STATE
+		&& (rtw_mi_get_ap_num(adapter) || rtw_mi_get_mesh_num(adapter))
+	) {
+		struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
+		int i;
+		_adapter *iface;
+
+		for (i = 0; i < dvobj->iface_nums; i++) {
+			iface = dvobj->padapters[i];
+			if (!iface)
+				continue;
+			if (iface == adapter)
+				continue;
+
+			if ((MLME_IS_AP(iface) || MLME_IS_MESH(iface))
+				&& check_fwstate(&iface->mlmepriv, WIFI_ASOC_STATE) == _TRUE
+			) {
+				rtw_hal_correct_tsf(iface, iface->hw_port, tsf);
+				#ifdef CONFIG_TSF_RESET_OFFLOAD
+				if (rtw_hal_reset_tsf(iface, iface->hw_port) == _FAIL)
+					RTW_INFO("%s-[ERROR] "ADPT_FMT" Reset port%d TSF fail\n"
+						, __func__, ADPT_ARG(iface), iface->hw_port);
+				#endif	/* CONFIG_TSF_RESET_OFFLOAD*/
+			}
+		}
+	}
+#endif /* CONFIG_CONCURRENT_MODE */
+
+	if ((mlmeinfo->state & 0x03) == WIFI_FW_ADHOC_STATE
+		|| (mlmeinfo->state & 0x03) == WIFI_FW_AP_STATE)
+		ResumeTxBeacon(adapter);
+
+#endif /*CONFIG_MI_WITH_MBSSID_CAM*/
+}
+#endif
+
+u64 rtw_hal_get_tsftr_by_port(_adapter *adapter, u8 port)
+{
+	struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter);
+	u64 tsftr = 0;
+
+	if (port >= hal_spec->port_num) {
+		RTW_ERR("%s invalid port(%d) \n", __func__, port);
+		goto exit;
+	}
+
+	switch (rtw_get_chip_type(adapter)) {
+#if defined(CONFIG_RTL8814A) || defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C)
+	case RTL8814A:
+	case RTL8822B:
+	case RTL8821C:
+	{
+		u8 val8;
+
+		/* 0x554[30:28] - BIT_BCN_TIMER_SEL_FWRD */
+		val8 = rtw_read8(adapter, REG_MBSSID_BCN_SPACE + 3);
+		val8 &= 0x8F;
+		val8 |= port << 4;
+		rtw_write8(adapter, REG_MBSSID_BCN_SPACE + 3, val8);
+
+		tsftr = rtw_read32(adapter, REG_TSFTR + 4);
+		tsftr = tsftr << 32;
+		tsftr |= rtw_read32(adapter, REG_TSFTR);
+
+		break;
+	}
+#endif
+#if defined(CONFIG_RTL8188E) || defined(CONFIG_RTL8188F) || defined(CONFIG_RTL8188GTV) \
+		|| defined(CONFIG_RTL8192E) || defined(CONFIG_RTL8192F) \
+		|| defined(CONFIG_RTL8723B) || defined(CONFIG_RTL8703B) || defined(CONFIG_RTL8723D) \
+		|| defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A) \
+		|| defined(CONFIG_RTL8710B)
+	case RTL8188E:
+	case RTL8188F:
+	case RTL8188GTV:
+	case RTL8192E:
+	case RTL8192F:
+	case RTL8723B:
+	case RTL8703B:
+	case RTL8723D:
+	case RTL8812:
+	case RTL8821:
+	case RTL8710B:
+	{
+		u32 addr;
+
+		if (port == HW_PORT0)
+			addr = REG_TSFTR;
+		else if (port == HW_PORT1)
+			addr = REG_TSFTR1;
+		else {
+			RTW_ERR("%s unknown port(%d) \n", __func__, port);
+			goto exit;
+		}
+
+		tsftr = rtw_read32(adapter, addr + 4);
+		tsftr = tsftr << 32;
+		tsftr |= rtw_read32(adapter, addr);
+
+		break;
+	}
+#endif
+	default:
+		RTW_ERR("%s unknow chip type\n", __func__);
+	}
+
+exit:
+	return tsftr;
+}
+
+#ifdef CONFIG_TDLS
+#ifdef CONFIG_TDLS_CH_SW
+s32 rtw_hal_ch_sw_oper_offload(_adapter *padapter, u8 channel, u8 channel_offset, u16 bwmode)
+{
+	PHAL_DATA_TYPE	pHalData =  GET_HAL_DATA(padapter);
+	u8 ch_sw_h2c_buf[4] = {0x00, 0x00, 0x00, 0x00};
+
+
+	SET_H2CCMD_CH_SW_OPER_OFFLOAD_CH_NUM(ch_sw_h2c_buf, channel);
+	SET_H2CCMD_CH_SW_OPER_OFFLOAD_BW_MODE(ch_sw_h2c_buf, bwmode);
+	switch (bwmode) {
+	case CHANNEL_WIDTH_40:
+		SET_H2CCMD_CH_SW_OPER_OFFLOAD_BW_40M_SC(ch_sw_h2c_buf, channel_offset);
+		break;
+	case CHANNEL_WIDTH_80:
+		SET_H2CCMD_CH_SW_OPER_OFFLOAD_BW_80M_SC(ch_sw_h2c_buf, channel_offset);
+		break;
+	case CHANNEL_WIDTH_20:
+	default:
+		break;
+	}
+	SET_H2CCMD_CH_SW_OPER_OFFLOAD_RFE_TYPE(ch_sw_h2c_buf, pHalData->rfe_type);
+
+	return rtw_hal_fill_h2c_cmd(padapter, H2C_CHNL_SWITCH_OPER_OFFLOAD, sizeof(ch_sw_h2c_buf), ch_sw_h2c_buf);
+}
+#endif
+#endif
+
+#ifdef CONFIG_WMMPS_STA
+void rtw_hal_update_uapsd_tid(_adapter *adapter)
+{
+	struct mlme_priv		*pmlmepriv = &adapter->mlmepriv;
+	struct qos_priv		*pqospriv = &pmlmepriv->qospriv;
+
+	/* write complement of pqospriv->uapsd_tid to mac register 0x693 because 
+	    it's designed  for "0" represents "enable" and "1" represents "disable" */
+	rtw_write8(adapter, REG_WMMPS_UAPSD_TID, (u8)(~pqospriv->uapsd_tid));
+}
+#endif /* CONFIG_WMMPS_STA */
+
+#if defined(CONFIG_BT_COEXIST) && defined(CONFIG_FW_MULTI_PORT_SUPPORT)
+/* For multi-port support, driver needs to inform the port ID to FW for btc operations */
+s32 rtw_hal_set_wifi_btc_port_id_cmd(_adapter *adapter)
+{
+	u8 h2c_buf[H2C_BTC_WL_PORT_ID_LEN] = {0};
+	u8 hw_port = rtw_hal_get_port(adapter);
+
+	SET_H2CCMD_BTC_WL_PORT_ID(h2c_buf, hw_port);
+	RTW_INFO("%s ("ADPT_FMT") - hw_port :%d\n", __func__, ADPT_ARG(adapter), hw_port);
+	return rtw_hal_fill_h2c_cmd(adapter, H2C_BTC_WL_PORT_ID, H2C_BTC_WL_PORT_ID_LEN, h2c_buf);
+}
+#endif
+
+#define LPS_ACTIVE_TIMEOUT	10 /*number of times*/
+void rtw_lps_state_chk(_adapter *adapter, u8 ps_mode)
+{
+	if (ps_mode == PS_MODE_ACTIVE) {
+		u8 ps_ready = _FALSE;
+		s8 leave_wait_count = LPS_ACTIVE_TIMEOUT;
+
+		do {
+			if ((rtw_read8(adapter, REG_TCR) & BIT_PWRBIT_OW_EN) == 0) {
+				ps_ready = _TRUE;
+				break;
+			}
+			rtw_msleep_os(1);
+		} while (leave_wait_count--);
+
+		if (ps_ready == _FALSE) {
+			RTW_ERR(FUNC_ADPT_FMT" PS_MODE_ACTIVE check failed\n", FUNC_ADPT_ARG(adapter));
+			rtw_warn_on(1);
+		}
+	}
+}
+
+u8 SetHwReg(_adapter *adapter, u8 variable, u8 *val)
+{
+	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
+	u8 ret = _SUCCESS;
+
+	switch (variable) {
+	case HW_VAR_MEDIA_STATUS: {
+		u8 net_type = *((u8 *)val);
+
+		rtw_hal_set_msr(adapter, net_type);
+	}
+	break;
+	case HW_VAR_DO_IQK:
+		if (*val)
+			hal_data->bNeedIQK = _TRUE;
+		else
+			hal_data->bNeedIQK = _FALSE;
+		break;
+	case HW_VAR_MAC_ADDR:
+#ifdef CONFIG_MI_WITH_MBSSID_CAM
+		rtw_hal_set_macaddr_mbid(adapter, val);
+#else
+		rtw_hal_set_macaddr_port(adapter, val);
+#endif
+		break;
+	case HW_VAR_BSSID:
+		rtw_hal_set_bssid(adapter, val);
+		break;
+	case HW_VAR_RCR:
+		ret = hw_var_rcr_config(adapter, *((u32 *)val));
+		break;
+	case HW_VAR_ON_RCR_AM:
+		hw_var_set_rcr_am(adapter, 1);
+		break;
+	case HW_VAR_OFF_RCR_AM:
+		hw_var_set_rcr_am(adapter, 0);
+		break;
+	case HW_VAR_BEACON_INTERVAL:
+		hw_var_set_bcn_interval(adapter, *(u16 *)val);
+		break;
+#ifdef CONFIG_MBSSID_CAM
+	case HW_VAR_MBSSID_CAM_WRITE: {
+		u32	cmd = 0;
+		u32	*cam_val = (u32 *)val;
+
+		rtw_write32(adapter, REG_MBIDCAMCFG_1, cam_val[0]);
+		cmd = BIT_MBIDCAM_POLL | BIT_MBIDCAM_WT_EN | BIT_MBIDCAM_VALID | cam_val[1];
+		rtw_write32(adapter, REG_MBIDCAMCFG_2, cmd);
+	}
+		break;
+	case HW_VAR_MBSSID_CAM_CLEAR: {
+		u32 cmd;
+		u8 entry_id = *(u8 *)val;
+
+		rtw_write32(adapter, REG_MBIDCAMCFG_1, 0);
+
+		cmd = BIT_MBIDCAM_POLL | BIT_MBIDCAM_WT_EN | ((entry_id & MBIDCAM_ADDR_MASK) << MBIDCAM_ADDR_SHIFT);
+		rtw_write32(adapter, REG_MBIDCAMCFG_2, cmd);
+	}
+		break;
+	case HW_VAR_RCR_MBSSID_EN:
+		if (*((u8 *)val))
+			rtw_hal_rcr_add(adapter, RCR_ENMBID);
+		else
+			rtw_hal_rcr_clear(adapter, RCR_ENMBID);
+		break;
+#endif
+	case HW_VAR_PORT_SWITCH:
+		hw_var_port_switch(adapter);
+		break;
+	case HW_VAR_INIT_RTS_RATE: {
+		u16 brate_cfg = *((u16 *)val);
+		u8 rate_index = 0;
+		HAL_VERSION *hal_ver = &hal_data->version_id;
+
+		if (IS_8188E(*hal_ver)) {
+
+			while (brate_cfg > 0x1) {
+				brate_cfg = (brate_cfg >> 1);
+				rate_index++;
+			}
+			rtw_write8(adapter, REG_INIRTS_RATE_SEL, rate_index);
+		} else
+			rtw_warn_on(1);
+	}
+		break;
+	case HW_VAR_SEC_CFG: {
+		u16 reg_scr_ori;
+		u16 reg_scr;
+
+		reg_scr = reg_scr_ori = rtw_read16(adapter, REG_SECCFG);
+		reg_scr |= (SCR_CHK_KEYID | SCR_RxDecEnable | SCR_TxEncEnable);
+
+		if (_rtw_camctl_chk_cap(adapter, SEC_CAP_CHK_BMC))
+			reg_scr |= SCR_CHK_BMC;
+
+		if (_rtw_camctl_chk_flags(adapter, SEC_STATUS_STA_PK_GK_CONFLICT_DIS_BMC_SEARCH))
+			reg_scr |= SCR_NoSKMC;
+
+		if (reg_scr != reg_scr_ori)
+			rtw_write16(adapter, REG_SECCFG, reg_scr);
+	}
+		break;
+	case HW_VAR_SEC_DK_CFG: {
+		struct security_priv *sec = &adapter->securitypriv;
+		u8 reg_scr = rtw_read8(adapter, REG_SECCFG);
+
+		if (val) { /* Enable default key related setting */
+			reg_scr |= SCR_TXBCUSEDK;
+			if (sec->dot11AuthAlgrthm != dot11AuthAlgrthm_8021X)
+				reg_scr |= (SCR_RxUseDK | SCR_TxUseDK);
+		} else /* Disable default key related setting */
+			reg_scr &= ~(SCR_RXBCUSEDK | SCR_TXBCUSEDK | SCR_RxUseDK | SCR_TxUseDK);
+
+		rtw_write8(adapter, REG_SECCFG, reg_scr);
+	}
+		break;
+
+	case HW_VAR_ASIX_IOT:
+		/* enable  ASIX IOT function */
+		if (*((u8 *)val) == _TRUE) {
+			/* 0xa2e[0]=0 (disable rake receiver) */
+			rtw_write8(adapter, rCCK0_FalseAlarmReport + 2,
+				rtw_read8(adapter, rCCK0_FalseAlarmReport + 2) & ~(BIT0));
+			/* 0xa1c=0xa0 (reset channel estimation if signal quality is bad) */
+			rtw_write8(adapter, rCCK0_DSPParameter2, 0xa0);
+		} else {
+			/* restore reg:0xa2e,   reg:0xa1c */
+			rtw_write8(adapter, rCCK0_FalseAlarmReport + 2,
+				rtw_read8(adapter, rCCK0_FalseAlarmReport + 2) | (BIT0));
+			rtw_write8(adapter, rCCK0_DSPParameter2, 0x00);
+		}
+		break;
+#if defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN)
+	case HW_VAR_WOWLAN: {
+		struct wowlan_ioctl_param *poidparam;
+
+		poidparam = (struct wowlan_ioctl_param *)val;
+		switch (poidparam->subcode) {
+#ifdef CONFIG_WOWLAN
+		case WOWLAN_PATTERN_CLEAN:
+			rtw_hal_dl_pattern(adapter, 2);
+			break;
+		case WOWLAN_ENABLE:
+			rtw_hal_wow_enable(adapter);
+			break;
+		case WOWLAN_DISABLE:
+			rtw_hal_wow_disable(adapter);
+			break;
+#endif /*CONFIG_WOWLAN*/
+#ifdef CONFIG_AP_WOWLAN
+		case WOWLAN_AP_ENABLE:
+			rtw_hal_ap_wow_enable(adapter);
+			break;
+		case WOWLAN_AP_DISABLE:
+			rtw_hal_ap_wow_disable(adapter);
+			break;
+#endif /*CONFIG_AP_WOWLAN*/
+		default:
+			break;
+		}
+	}
+		break;
+#endif /*defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN)*/
+
+	case HW_VAR_BCN_FUNC:
+		hw_var_set_bcn_func(adapter, *val);
+		break;
+
+	case HW_VAR_MLME_DISCONNECT:
+		hw_var_set_mlme_disconnect(adapter);
+		break;
+
+	case HW_VAR_MLME_SITESURVEY:
+		hw_var_set_mlme_sitesurvey(adapter, *val);
+		#ifdef CONFIG_BT_COEXIST
+		if (hal_data->EEPROMBluetoothCoexist == 1)
+			rtw_btcoex_ScanNotify(adapter, *val ? _TRUE : _FALSE);
+		#endif
+		break;
+
+	case HW_VAR_MLME_JOIN:
+		hw_var_set_mlme_join(adapter, *val);
+		#ifdef CONFIG_BT_COEXIST
+		if (hal_data->EEPROMBluetoothCoexist == 1) {
+			switch (*val) {
+			case 0:
+				/* Notify coex. mechanism before join */
+				rtw_btcoex_ConnectNotify(adapter, _TRUE);
+				break;
+			case 1:
+			case 2:
+				/* Notify coex. mechanism after join, whether successful or failed */
+				rtw_btcoex_ConnectNotify(adapter, _FALSE);
+				break;
+			}
+		}
+		#endif /* CONFIG_BT_COEXIST */
+		break;
+
+	case HW_VAR_EN_HW_UPDATE_TSF:
+		rtw_hal_set_hw_update_tsf(adapter);
+		break;
+	case HW_VAR_CORRECT_TSF:
+		hw_var_set_correct_tsf(adapter, *val);
+		break;
+
+#if defined(CONFIG_HW_P0_TSF_SYNC) && defined(CONFIG_CONCURRENT_MODE)
+	case HW_VAR_TSF_AUTO_SYNC:
+		if (*val == _TRUE)
+			hw_port0_tsf_sync_sel(adapter, _TRUE, adapter->hw_port, 50);
+		else
+			hw_port0_tsf_sync_sel(adapter, _FALSE, adapter->hw_port, 50);
+		break;
+#endif
+	case HW_VAR_APFM_ON_MAC:
+		hal_data->bMacPwrCtrlOn = *val;
+		RTW_INFO("%s: bMacPwrCtrlOn=%d\n", __func__, hal_data->bMacPwrCtrlOn);
+		break;
+#ifdef CONFIG_WMMPS_STA
+	case  HW_VAR_UAPSD_TID:
+		rtw_hal_update_uapsd_tid(adapter);
+		break;
+#endif /* CONFIG_WMMPS_STA */
+#ifdef CONFIG_LPS_PG
+	case HW_VAR_LPS_PG_HANDLE:
+		rtw_hal_lps_pg_handler(adapter, *val);
+		break;
+#endif
+#ifdef CONFIG_LPS_LCLK_WD_TIMER
+	case HW_VAR_DM_IN_LPS_LCLK:
+		rtw_phydm_wd_lps_lclk_hdl(adapter);
+		break;
+#endif
+	case HW_VAR_ENABLE_RX_BAR:
+		if (*val == _TRUE) {
+			/* enable RX BAR */
+			u16 val16 = rtw_read16(adapter, REG_RXFLTMAP1);
+
+			val16 |= BIT(8);
+			rtw_write16(adapter, REG_RXFLTMAP1, val16);
+		} else {
+			/* disable RX BAR */
+			u16 val16 = rtw_read16(adapter, REG_RXFLTMAP1);
+
+			val16 &= (~BIT(8));
+			rtw_write16(adapter, REG_RXFLTMAP1, val16);
+		}
+		RTW_INFO("[HW_VAR_ENABLE_RX_BAR] 0x%02X=0x%02X\n",
+			REG_RXFLTMAP1, rtw_read16(adapter, REG_RXFLTMAP1));
+		break;
+	case HW_VAR_HCI_SUS_STATE:
+		hal_data->hci_sus_state = *(u8 *)val;
+		RTW_INFO("%s: hci_sus_state=%u\n", __func__, hal_data->hci_sus_state);
+		break;
+#if defined(CONFIG_AP_MODE) && defined(CONFIG_FW_HANDLE_TXBCN) && defined(CONFIG_SUPPORT_MULTI_BCN)
+		case HW_VAR_BCN_HEAD_SEL:
+		{
+			u8 vap_id = *(u8 *)val;
+
+			if ((vap_id >= CONFIG_LIMITED_AP_NUM) && (vap_id != 0xFF)) {
+				RTW_ERR(ADPT_FMT " vap_id(%d:%d) is invalid\n", ADPT_ARG(adapter),vap_id, adapter->vap_id);
+				rtw_warn_on(1);
+			}
+			if (MLME_IS_AP(adapter) || MLME_IS_MESH(adapter)) {
+				u16 drv_pg_bndy = 0, bcn_addr = 0;
+				u32 page_size = 0;
+
+				/*rtw_hal_get_def_var(adapter, HAL_DEF_TX_PAGE_BOUNDARY, &drv_pg_bndy);*/
+				rtw_halmac_get_rsvd_drv_pg_bndy(adapter_to_dvobj(adapter), &drv_pg_bndy);
+				rtw_hal_get_def_var(adapter, HAL_DEF_TX_PAGE_SIZE, (u8 *)&page_size);
+
+				if (vap_id != 0xFF)
+					bcn_addr = drv_pg_bndy + (vap_id * (MAX_BEACON_LEN / page_size));
+				else
+					bcn_addr = drv_pg_bndy;
+				RTW_INFO(ADPT_FMT" vap_id(%d) change BCN HEAD to 0x%04x\n",
+					ADPT_ARG(adapter), vap_id, bcn_addr);
+				rtw_write16(adapter, REG_FIFOPAGE_CTRL_2,
+					(bcn_addr & BIT_MASK_BCN_HEAD_1_V1) | BIT_BCN_VALID_V1);
+			}
+		}
+		break;
+#endif
+	case HW_VAR_LPS_STATE_CHK :
+		rtw_lps_state_chk(adapter, *(u8 *)val);
+		break;
+	default:
+		if (0)
+			RTW_PRINT(FUNC_ADPT_FMT" variable(%d) not defined!\n",
+				  FUNC_ADPT_ARG(adapter), variable);
+		ret = _FAIL;
+		break;
+	}
+
+	return ret;
+}
+
+void GetHwReg(_adapter *adapter, u8 variable, u8 *val)
+{
+	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
+	u64 val64;
+
+
+	switch (variable) {
+	case HW_VAR_MAC_ADDR:
+		rtw_hal_get_macaddr_port(adapter, val);
+		break;
+	case HW_VAR_BASIC_RATE:
+		*((u16 *)val) = hal_data->BasicRateSet;
+		break;
+	case HW_VAR_RF_TYPE:
+		*((u8 *)val) = hal_data->rf_type;
+		break;
+	case HW_VAR_MEDIA_STATUS:
+		rtw_hal_get_msr(adapter, val);
+		break;
+	case HW_VAR_DO_IQK:
+		*val = hal_data->bNeedIQK;
+		break;
+	case HW_VAR_CH_SW_NEED_TO_TAKE_CARE_IQK_INFO:
+		if (hal_is_band_support(adapter, BAND_ON_5G))
+			*val = _TRUE;
+		else
+			*val = _FALSE;
+		break;
+	case HW_VAR_APFM_ON_MAC:
+		*val = hal_data->bMacPwrCtrlOn;
+		break;
+	case HW_VAR_RCR:
+		hw_var_rcr_get(adapter, (u32 *)val);
+		break;
+	case HW_VAR_FWLPS_RF_ON:
+		/* When we halt NIC, we should check if FW LPS is leave. */
+		if (rtw_is_surprise_removed(adapter)
+			|| (adapter_to_pwrctl(adapter)->rf_pwrstate == rf_off)
+		) {
+			/*
+			 * If it is in HW/SW Radio OFF or IPS state,
+			 * we do not check Fw LPS Leave,
+			 * because Fw is unload.
+			 */
+			*val = _TRUE;
+		} else {
+			u32 rcr = 0;
+
+			rtw_hal_get_hwreg(adapter, HW_VAR_RCR, (u8 *)&rcr);
+			if (rcr & (RCR_UC_MD_EN | RCR_BC_MD_EN | RCR_TIM_PARSER_EN))
+				*val = _FALSE;
+			else
+				*val = _TRUE;
+		}
+		break;
+
+	case HW_VAR_HCI_SUS_STATE:
+		*((u8 *)val) = hal_data->hci_sus_state;
+		break;
+
+	case HW_VAR_BCN_CTRL_ADDR:
+		*((u32 *)val) = hw_bcn_ctrl_addr(adapter, adapter->hw_port);
+		break;
+
+	default:
+		if (0)
+			RTW_PRINT(FUNC_ADPT_FMT" variable(%d) not defined!\n",
+				  FUNC_ADPT_ARG(adapter), variable);
+		break;
+	}
+
+}
+
+static u32 _get_page_size(struct _ADAPTER *a)
+{
+#ifdef RTW_HALMAC
+	struct dvobj_priv *d;
+	u32 size = 0;
+	int err = 0;
+
+
+	d = adapter_to_dvobj(a);
+
+	err = rtw_halmac_get_page_size(d, &size);
+	if (!err)
+		return size;
+
+	RTW_WARN(FUNC_ADPT_FMT ": Fail to get Page size!!(err=%d)\n",
+		 FUNC_ADPT_ARG(a), err);
+#endif /* RTW_HALMAC */
+
+	return PAGE_SIZE_128;
+}
+
+u8
+SetHalDefVar(_adapter *adapter, HAL_DEF_VARIABLE variable, void *value)
+{
+	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
+	u8 bResult = _SUCCESS;
+
+	switch (variable) {
+
+	case HAL_DEF_DBG_DUMP_RXPKT:
+		hal_data->bDumpRxPkt = *((u8 *)value);
+		break;
+	case HAL_DEF_DBG_DUMP_TXPKT:
+		hal_data->bDumpTxPkt = *((u8 *)value);
+		break;
+	case HAL_DEF_ANT_DETECT:
+		hal_data->AntDetection = *((u8 *)value);
+		break;
+	default:
+		RTW_PRINT("%s: [WARNING] HAL_DEF_VARIABLE(%d) not defined!\n", __FUNCTION__, variable);
+		bResult = _FAIL;
+		break;
+	}
+
+	return bResult;
+}
+
+#ifdef CONFIG_BEAMFORMING
+u8 rtw_hal_query_txbfer_rf_num(_adapter *adapter)
+{
+	struct registry_priv	*pregistrypriv = &adapter->registrypriv;
+	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
+
+	if ((pregistrypriv->beamformer_rf_num) && (IS_HARDWARE_TYPE_8814AE(adapter) || IS_HARDWARE_TYPE_8814AU(adapter) || IS_HARDWARE_TYPE_8822BU(adapter) || IS_HARDWARE_TYPE_8821C(adapter)))
+		return pregistrypriv->beamformer_rf_num;
+	else if (IS_HARDWARE_TYPE_8814AE(adapter)
+#if 0
+#if defined(CONFIG_USB_HCI)
+		|| (IS_HARDWARE_TYPE_8814AU(adapter) && (pUsbModeMech->CurUsbMode == 2 || pUsbModeMech->HubUsbMode == 2))  /* for USB3.0 */
+#endif
+#endif
+		) {
+		/*BF cap provided by Yu Chen, Sean, 2015, 01 */
+		if (hal_data->rf_type == RF_3T3R)
+			return 2;
+		else if (hal_data->rf_type == RF_4T4R)
+			return 3;
+		else
+			return 1;
+	} else
+		return 1;
+
+}
+u8 rtw_hal_query_txbfee_rf_num(_adapter *adapter)
+{
+	struct registry_priv		*pregistrypriv = &adapter->registrypriv;
+	struct mlme_ext_priv	*pmlmeext = &adapter->mlmeextpriv;
+	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
+
+	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
+
+	if ((pregistrypriv->beamformee_rf_num) && (IS_HARDWARE_TYPE_8814AE(adapter) || IS_HARDWARE_TYPE_8814AU(adapter) || IS_HARDWARE_TYPE_8822BU(adapter) || IS_HARDWARE_TYPE_8821C(adapter)))
+		return pregistrypriv->beamformee_rf_num;
+	else if (IS_HARDWARE_TYPE_8814AE(adapter) || IS_HARDWARE_TYPE_8814AU(adapter)) {
+		if (pmlmeinfo->assoc_AP_vendor == HT_IOT_PEER_BROADCOM)
+			return 2;
+		else
+			return 2;/*TODO: May be 3 in the future, by ChenYu. */
+	} else
+		return 1;
+
+}
+#ifdef RTW_BEAMFORMING_VERSION_2
+void rtw_hal_beamforming_config_csirate(PADAPTER adapter)
+{
+	struct dm_struct *p_dm_odm;
+	struct beamforming_info *bf_info;
+	u8 fix_rate_enable = 0;
+	u8 new_csi_rate_idx;
+
+	/* Acting as BFee */
+	if (IS_BEAMFORMEE(adapter)) {
+	#if 0
+		/* Do not enable now because it will affect MU performance and CTS/BA rate. 2016.07.19. by tynli. [PCIE-1660] */
+		if (IS_HARDWARE_TYPE_8821C(Adapter))
+			FixRateEnable = 1;	/* Support after 8821C */
+	#endif
+
+		p_dm_odm = adapter_to_phydm(adapter);
+		bf_info = GET_BEAMFORM_INFO(adapter);
+
+		rtw_halmac_bf_cfg_csi_rate(adapter_to_dvobj(adapter),
+				p_dm_odm->rssi_min,
+				bf_info->cur_csi_rpt_rate,
+				fix_rate_enable, &new_csi_rate_idx);
+
+		if (new_csi_rate_idx != bf_info->cur_csi_rpt_rate)
+			bf_info->cur_csi_rpt_rate = new_csi_rate_idx;
+	}
+}
+#endif
+#endif
+
+u8
+GetHalDefVar(_adapter *adapter, HAL_DEF_VARIABLE variable, void *value)
+{
+	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
+	u8 bResult = _SUCCESS;
+
+	switch (variable) {
+	case HAL_DEF_UNDERCORATEDSMOOTHEDPWDB: {
+		struct mlme_priv *pmlmepriv;
+		struct sta_priv *pstapriv;
+		struct sta_info *psta;
+
+		pmlmepriv = &adapter->mlmepriv;
+		pstapriv = &adapter->stapriv;
+		psta = rtw_get_stainfo(pstapriv, pmlmepriv->cur_network.network.MacAddress);
+		if (psta)
+			*((int *)value) = psta->cmn.rssi_stat.rssi;
+	}
+	break;
+	case HAL_DEF_DBG_DUMP_RXPKT:
+		*((u8 *)value) = hal_data->bDumpRxPkt;
+		break;
+	case HAL_DEF_DBG_DUMP_TXPKT:
+		*((u8 *)value) = hal_data->bDumpTxPkt;
+		break;
+	case HAL_DEF_ANT_DETECT:
+		*((u8 *)value) = hal_data->AntDetection;
+		break;
+	case HAL_DEF_TX_PAGE_SIZE:
+		*((u32 *)value) = _get_page_size(adapter);
+		break;
+	case HAL_DEF_EXPLICIT_BEAMFORMER:
+	case HAL_DEF_EXPLICIT_BEAMFORMEE:
+	case HAL_DEF_VHT_MU_BEAMFORMER:
+	case HAL_DEF_VHT_MU_BEAMFORMEE:
+		*(u8 *)value = _FALSE;
+		break;
+#ifdef CONFIG_BEAMFORMING
+	case HAL_DEF_BEAMFORMER_CAP:
+		*(u8 *)value = rtw_hal_query_txbfer_rf_num(adapter);
+		break;
+	case HAL_DEF_BEAMFORMEE_CAP:
+		*(u8 *)value = rtw_hal_query_txbfee_rf_num(adapter);
+		break;
+#endif
+	default:
+		RTW_PRINT("%s: [WARNING] HAL_DEF_VARIABLE(%d) not defined!\n", __FUNCTION__, variable);
+		bResult = _FAIL;
+		break;
+	}
+
+	return bResult;
+}
+
+
+BOOLEAN
+eqNByte(
+	u8	*str1,
+	u8	*str2,
+	u32	num
+)
+{
+	if (num == 0)
+		return _FALSE;
+	while (num > 0) {
+		num--;
+		if (str1[num] != str2[num])
+			return _FALSE;
+	}
+	return _TRUE;
+}
+
+/*
+ *	Description:
+ *		Translate a character to hex digit.
+ *   */
+u32
+MapCharToHexDigit(
+	IN		char		chTmp
+)
+{
+	if (chTmp >= '0' && chTmp <= '9')
+		return chTmp - '0';
+	else if (chTmp >= 'a' && chTmp <= 'f')
+		return 10 + (chTmp - 'a');
+	else if (chTmp >= 'A' && chTmp <= 'F')
+		return 10 + (chTmp - 'A');
+	else
+		return 0;
+}
+
+
+
+/*
+ *	Description:
+ *		Parse hex number from the string pucStr.
+ *   */
+BOOLEAN
+GetHexValueFromString(
+	IN		char			*szStr,
+	IN OUT	u32			*pu4bVal,
+	IN OUT	u32			*pu4bMove
+)
+{
+	char		*szScan = szStr;
+
+	/* Check input parameter. */
+	if (szStr == NULL || pu4bVal == NULL || pu4bMove == NULL) {
+		RTW_INFO("GetHexValueFromString(): Invalid inpur argumetns! szStr: %p, pu4bVal: %p, pu4bMove: %p\n", szStr, pu4bVal, pu4bMove);
+		return _FALSE;
+	}
+
+	/* Initialize output. */
+	*pu4bMove = 0;
+	*pu4bVal = 0;
+
+	/* Skip leading space. */
+	while (*szScan != '\0' &&
+	       (*szScan == ' ' || *szScan == '\t')) {
+		szScan++;
+		(*pu4bMove)++;
+	}
+
+	/* Skip leading '0x' or '0X'. */
+	if (*szScan == '0' && (*(szScan + 1) == 'x' || *(szScan + 1) == 'X')) {
+		szScan += 2;
+		(*pu4bMove) += 2;
+	}
+
+	/* Check if szScan is now pointer to a character for hex digit, */
+	/* if not, it means this is not a valid hex number. */
+	if (!IsHexDigit(*szScan))
+		return _FALSE;
+
+	/* Parse each digit. */
+	do {
+		(*pu4bVal) <<= 4;
+		*pu4bVal += MapCharToHexDigit(*szScan);
+
+		szScan++;
+		(*pu4bMove)++;
+	} while (IsHexDigit(*szScan));
+
+	return _TRUE;
+}
+
+BOOLEAN
+GetFractionValueFromString(
+	IN		char			*szStr,
+	IN OUT	u8				*pInteger,
+	IN OUT	u8				*pFraction,
+	IN OUT	u32			*pu4bMove
+)
+{
+	char	*szScan = szStr;
+
+	/* Initialize output. */
+	*pu4bMove = 0;
+	*pInteger = 0;
+	*pFraction = 0;
+
+	/* Skip leading space. */
+	while (*szScan != '\0' &&	(*szScan == ' ' || *szScan == '\t')) {
+		++szScan;
+		++(*pu4bMove);
+	}
+
+	if (*szScan < '0' || *szScan > '9')
+		return _FALSE;
+
+	/* Parse each digit. */
+	do {
+		(*pInteger) *= 10;
+		*pInteger += (*szScan - '0');
+
+		++szScan;
+		++(*pu4bMove);
+
+		if (*szScan == '.') {
+			++szScan;
+			++(*pu4bMove);
+
+			if (*szScan < '0' || *szScan > '9')
+				return _FALSE;
+
+			*pFraction += (*szScan - '0') * 10;
+			++szScan;
+			++(*pu4bMove);
+
+			if (*szScan >= '0' && *szScan <= '9') {
+				*pFraction += *szScan - '0';
+				++szScan;
+				++(*pu4bMove);
+			}
+			return _TRUE;
+		}
+	} while (*szScan >= '0' && *szScan <= '9');
+
+	return _TRUE;
+}
+
+/*
+ *	Description:
+ * Return TRUE if szStr is comment out with leading " */ /* ".
+ *   */
+BOOLEAN
+IsCommentString(
+	IN		char			*szStr
+)
+{
+	if (*szStr == '/' && *(szStr + 1) == '/')
+		return _TRUE;
+	else
+		return _FALSE;
+}
+
+BOOLEAN
+GetU1ByteIntegerFromStringInDecimal(
+	IN		char	*Str,
+	IN OUT	u8		*pInt
+)
+{
+	u16 i = 0;
+	*pInt = 0;
+
+	while (Str[i] != '\0') {
+		if (Str[i] >= '0' && Str[i] <= '9') {
+			*pInt *= 10;
+			*pInt += (Str[i] - '0');
+		} else
+			return _FALSE;
+		++i;
+	}
+
+	return _TRUE;
+}
+
+/* <20121004, Kordan> For example,
+ * ParseQualifiedString(inString, 0, outString, '[', ']') gets "Kordan" from a string "Hello [Kordan]".
+ * If RightQualifier does not exist, it will hang on in the while loop */
+BOOLEAN
+ParseQualifiedString(
+	IN		char	*In,
+	IN OUT	u32	*Start,
+	OUT		char	*Out,
+	IN		char		LeftQualifier,
+	IN		char		RightQualifier
+)
+{
+	u32	i = 0, j = 0;
+	char	c = In[(*Start)++];
+
+	if (c != LeftQualifier)
+		return _FALSE;
+
+	i = (*Start);
+	c = In[(*Start)++];
+	while (c != RightQualifier && c != '\0')
+		c = In[(*Start)++];
+
+	if (c == '\0')
+		return _FALSE;
+
+	j = (*Start) - 2;
+	strncpy((char *)Out, (const char *)(In + i), j - i + 1);
+
+	return _TRUE;
+}
+
+BOOLEAN
+isAllSpaceOrTab(
+	u8	*data,
+	u8	size
+)
+{
+	u8	cnt = 0, NumOfSpaceAndTab = 0;
+
+	while (size > cnt) {
+		if (data[cnt] == ' ' || data[cnt] == '\t' || data[cnt] == '\0')
+			++NumOfSpaceAndTab;
+
+		++cnt;
+	}
+
+	return size == NumOfSpaceAndTab;
+}
+
+
+void rtw_hal_check_rxfifo_full(_adapter *adapter)
+{
+	struct dvobj_priv *psdpriv = adapter->dvobj;
+	struct debug_priv *pdbgpriv = &psdpriv->drv_dbg;
+	HAL_DATA_TYPE *pHalData = GET_HAL_DATA(adapter);
+	struct registry_priv *regsty = &adapter->registrypriv;
+	int save_cnt = _FALSE;
+
+	if (regsty->check_hw_status == 1) {
+		/* switch counter to RX fifo */
+		if (IS_8188E(pHalData->version_id) ||
+		    IS_8188F(pHalData->version_id) ||
+		    IS_8188GTV(pHalData->version_id) ||
+		    IS_8812_SERIES(pHalData->version_id) ||
+		    IS_8821_SERIES(pHalData->version_id) ||
+		    IS_8723B_SERIES(pHalData->version_id) ||
+		    IS_8192E(pHalData->version_id) ||
+		    IS_8703B_SERIES(pHalData->version_id) ||
+		    IS_8723D_SERIES(pHalData->version_id) ||
+		    IS_8192F_SERIES(pHalData->version_id)) {
+			rtw_write8(adapter, REG_RXERR_RPT + 3, rtw_read8(adapter, REG_RXERR_RPT + 3) | 0xa0);
+			save_cnt = _TRUE;
+		} else {
+			/* todo: other chips */
+		}
+
+
+		if (save_cnt) {
+			pdbgpriv->dbg_rx_fifo_last_overflow = pdbgpriv->dbg_rx_fifo_curr_overflow;
+			pdbgpriv->dbg_rx_fifo_curr_overflow = rtw_read16(adapter, REG_RXERR_RPT);
+			pdbgpriv->dbg_rx_fifo_diff_overflow = pdbgpriv->dbg_rx_fifo_curr_overflow - pdbgpriv->dbg_rx_fifo_last_overflow;
+		} else {
+			/* special value to indicate no implementation */
+			pdbgpriv->dbg_rx_fifo_last_overflow = 1;
+			pdbgpriv->dbg_rx_fifo_curr_overflow = 1;
+			pdbgpriv->dbg_rx_fifo_diff_overflow = 1;
+		}
+	}
+}
+
+void linked_info_dump(_adapter *padapter, u8 benable)
+{
+	struct pwrctrl_priv *pwrctrlpriv = adapter_to_pwrctl(padapter);
+
+	if (padapter->bLinkInfoDump == benable)
+		return;
+
+	RTW_INFO("%s %s\n", __FUNCTION__, (benable) ? "enable" : "disable");
+
+	if (benable) {
+#ifdef CONFIG_LPS
+		pwrctrlpriv->org_power_mgnt = pwrctrlpriv->power_mgnt;/* keep org value */
+		rtw_pm_set_lps(padapter, PS_MODE_ACTIVE);
+#endif
+
+#ifdef CONFIG_IPS
+		pwrctrlpriv->ips_org_mode = pwrctrlpriv->ips_mode;/* keep org value */
+		rtw_pm_set_ips(padapter, IPS_NONE);
+#endif
+	} else {
+#ifdef CONFIG_IPS
+		rtw_pm_set_ips(padapter, pwrctrlpriv->ips_org_mode);
+#endif /* CONFIG_IPS */
+
+#ifdef CONFIG_LPS
+		rtw_pm_set_lps(padapter, pwrctrlpriv->org_power_mgnt);
+#endif /* CONFIG_LPS */
+	}
+	padapter->bLinkInfoDump = benable ;
+}
+
+#ifdef DBG_RX_SIGNAL_DISPLAY_RAW_DATA
+void rtw_get_raw_rssi_info(void *sel, _adapter *padapter)
+{
+	u8 isCCKrate, rf_path;
+	PHAL_DATA_TYPE	pHalData =  GET_HAL_DATA(padapter);
+	struct rx_raw_rssi *psample_pkt_rssi = &padapter->recvpriv.raw_rssi_info;
+	RTW_PRINT_SEL(sel, "RxRate = %s, PWDBALL = %d(%%), rx_pwr_all = %d(dBm)\n",
+		HDATA_RATE(psample_pkt_rssi->data_rate), psample_pkt_rssi->pwdball, psample_pkt_rssi->pwr_all);
+	isCCKrate = (psample_pkt_rssi->data_rate <= DESC_RATE11M) ? TRUE : FALSE;
+
+	if (isCCKrate)
+		psample_pkt_rssi->mimo_signal_strength[0] = psample_pkt_rssi->pwdball;
+
+	for (rf_path = 0; rf_path < pHalData->NumTotalRFPath; rf_path++) {
+		RTW_PRINT_SEL(sel, "RF_PATH_%d=>signal_strength:%d(%%),signal_quality:%d(%%)\n"
+			, rf_path, psample_pkt_rssi->mimo_signal_strength[rf_path], psample_pkt_rssi->mimo_signal_quality[rf_path]);
+
+		if (!isCCKrate) {
+			RTW_PRINT_SEL(sel, "\trx_ofdm_pwr:%d(dBm),rx_ofdm_snr:%d(dB)\n",
+				psample_pkt_rssi->ofdm_pwr[rf_path], psample_pkt_rssi->ofdm_snr[rf_path]);
+		}
+	}
+}
+
+void rtw_dump_raw_rssi_info(_adapter *padapter, void *sel)
+{
+	u8 isCCKrate, rf_path;
+	PHAL_DATA_TYPE	pHalData =  GET_HAL_DATA(padapter);
+	struct rx_raw_rssi *psample_pkt_rssi = &padapter->recvpriv.raw_rssi_info;
+	_RTW_PRINT_SEL(sel, "============ RAW Rx Info dump ===================\n");
+	_RTW_PRINT_SEL(sel, "RxRate = %s, PWDBALL = %d(%%), rx_pwr_all = %d(dBm)\n", HDATA_RATE(psample_pkt_rssi->data_rate), psample_pkt_rssi->pwdball, psample_pkt_rssi->pwr_all);
+
+	isCCKrate = (psample_pkt_rssi->data_rate <= DESC_RATE11M) ? TRUE : FALSE;
+
+	if (isCCKrate)
+		psample_pkt_rssi->mimo_signal_strength[0] = psample_pkt_rssi->pwdball;
+
+	for (rf_path = 0; rf_path < pHalData->NumTotalRFPath; rf_path++) {
+		_RTW_PRINT_SEL(sel , "RF_PATH_%d=>signal_strength:%d(%%),signal_quality:%d(%%)"
+			, rf_path, psample_pkt_rssi->mimo_signal_strength[rf_path], psample_pkt_rssi->mimo_signal_quality[rf_path]);
+
+		if (!isCCKrate)
+			_RTW_PRINT_SEL(sel , ",rx_ofdm_pwr:%d(dBm),rx_ofdm_snr:%d(dB)\n", psample_pkt_rssi->ofdm_pwr[rf_path], psample_pkt_rssi->ofdm_snr[rf_path]);
+		else
+			_RTW_PRINT_SEL(sel , "\n");
+
+	}
+}
+#endif
+
+#ifdef DBG_RX_DFRAME_RAW_DATA
+void rtw_dump_rx_dframe_info(_adapter *padapter, void *sel)
+{
+#define DBG_RX_DFRAME_RAW_DATA_UC		0
+#define DBG_RX_DFRAME_RAW_DATA_BMC		1
+#define DBG_RX_DFRAME_RAW_DATA_TYPES	2
+
+	_irqL irqL;
+	u8 isCCKrate, rf_path;
+	struct recv_priv *precvpriv = &(padapter->recvpriv);
+	PHAL_DATA_TYPE	pHalData =  GET_HAL_DATA(padapter);
+	struct sta_priv *pstapriv = &padapter->stapriv;
+	struct sta_info *psta;
+	struct sta_recv_dframe_info *psta_dframe_info;
+	int i, j;
+	_list	*plist, *phead;
+	u8 bc_addr[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
+	u8 null_addr[ETH_ALEN] = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00};
+
+	if (precvpriv->store_law_data_flag) {
+
+		_enter_critical_bh(&pstapriv->sta_hash_lock, &irqL);
+
+		for (i = 0; i < NUM_STA; i++) {
+			phead = &(pstapriv->sta_hash[i]);
+			plist = get_next(phead);
+
+			while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) {
+
+				psta = LIST_CONTAINOR(plist, struct sta_info, hash_list);
+				plist = get_next(plist);
+
+				if (psta) {
+					if ((_rtw_memcmp(psta->cmn.mac_addr, bc_addr, ETH_ALEN)  !=   _TRUE)
+					    && (_rtw_memcmp(psta->cmn.mac_addr, null_addr, ETH_ALEN)  !=  _TRUE)
+					    && (_rtw_memcmp(psta->cmn.mac_addr, adapter_mac_addr(padapter), ETH_ALEN)  !=  _TRUE)) {
+
+						RTW_PRINT_SEL(sel, "==============================\n");
+						RTW_PRINT_SEL(sel, "macaddr =" MAC_FMT "\n", MAC_ARG(psta->cmn.mac_addr));
+
+						for (j = 0; j < DBG_RX_DFRAME_RAW_DATA_TYPES; j++) {
+							if (j == DBG_RX_DFRAME_RAW_DATA_UC) {
+								psta_dframe_info = &psta->sta_dframe_info;
+								RTW_PRINT_SEL(sel, "\n");
+								RTW_PRINT_SEL(sel, "Unicast:\n");
+							} else if (j == DBG_RX_DFRAME_RAW_DATA_BMC) {
+								psta_dframe_info = &psta->sta_dframe_info_bmc;
+								RTW_PRINT_SEL(sel, "\n");
+								RTW_PRINT_SEL(sel, "Broadcast/Multicast:\n");
+							}
+
+							isCCKrate = (psta_dframe_info->sta_data_rate <= DESC_RATE11M) ? TRUE : FALSE;
+
+							RTW_PRINT_SEL(sel, "BW=%s, sgi =%d\n", ch_width_str(psta_dframe_info->sta_bw_mode), psta_dframe_info->sta_sgi);
+							RTW_PRINT_SEL(sel, "Rx_Data_Rate = %s\n", HDATA_RATE(psta_dframe_info->sta_data_rate));
+
+							for (rf_path = 0; rf_path < pHalData->NumTotalRFPath; rf_path++) {
+								if (!isCCKrate) {
+									RTW_PRINT_SEL(sel , "RF_PATH_%d RSSI:%d(dBm)", rf_path, psta_dframe_info->sta_RxPwr[rf_path]);
+									_RTW_PRINT_SEL(sel , ",rx_ofdm_snr:%d(dB)\n", psta_dframe_info->sta_ofdm_snr[rf_path]);
+								} else
+									RTW_PRINT_SEL(sel , "RF_PATH_%d RSSI:%d(dBm)\n", rf_path, (psta_dframe_info->sta_mimo_signal_strength[rf_path]) - 100);
+							}
+						}
+
+					}
+				}
+			}
+		}
+		_exit_critical_bh(&pstapriv->sta_hash_lock, &irqL);
+	}
+}
+#endif
+void rtw_store_phy_info(_adapter *padapter, union recv_frame *prframe)
+{
+	u8 isCCKrate, rf_path , dframe_type;
+	u8 *ptr;
+	u8	bc_addr[] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
+#ifdef DBG_RX_DFRAME_RAW_DATA
+	struct sta_recv_dframe_info *psta_dframe_info;
+#endif
+	struct recv_priv *precvpriv = &(padapter->recvpriv);
+	PHAL_DATA_TYPE	pHalData =  GET_HAL_DATA(padapter);
+	struct rx_pkt_attrib *pattrib = &prframe->u.hdr.attrib;
+	struct sta_info *psta = prframe->u.hdr.psta;
+	struct phydm_phyinfo_struct *p_phy_info = &pattrib->phy_info;
+	struct rx_raw_rssi *psample_pkt_rssi = &padapter->recvpriv.raw_rssi_info;
+	psample_pkt_rssi->data_rate = pattrib->data_rate;
+	ptr = prframe->u.hdr.rx_data;
+	dframe_type = GetFrameType(ptr);
+	/*RTW_INFO("=>%s\n", __FUNCTION__);*/
+
+
+	if (precvpriv->store_law_data_flag) {
+		isCCKrate = (pattrib->data_rate <= DESC_RATE11M) ? TRUE : FALSE;
+
+		psample_pkt_rssi->pwdball = p_phy_info->rx_pwdb_all;
+		psample_pkt_rssi->pwr_all = p_phy_info->recv_signal_power;
+
+		for (rf_path = 0; rf_path < pHalData->NumTotalRFPath; rf_path++) {
+			psample_pkt_rssi->mimo_signal_strength[rf_path] = p_phy_info->rx_mimo_signal_strength[rf_path];
+			psample_pkt_rssi->mimo_signal_quality[rf_path] = p_phy_info->rx_mimo_signal_quality[rf_path];
+			if (!isCCKrate) {
+				psample_pkt_rssi->ofdm_pwr[rf_path] = p_phy_info->rx_pwr[rf_path];
+				psample_pkt_rssi->ofdm_snr[rf_path] = p_phy_info->rx_snr[rf_path];
+			}
+		}
+#ifdef DBG_RX_DFRAME_RAW_DATA
+		if ((dframe_type == WIFI_DATA_TYPE) || (dframe_type == WIFI_QOS_DATA_TYPE) || (padapter->registrypriv.mp_mode == 1)) {
+
+			/*RTW_INFO("=>%s WIFI_DATA_TYPE or WIFI_QOS_DATA_TYPE\n", __FUNCTION__);*/
+			if (psta) {
+				if (IS_MCAST(get_ra(get_recvframe_data(prframe))))
+					psta_dframe_info = &psta->sta_dframe_info_bmc;
+				else
+					psta_dframe_info = &psta->sta_dframe_info;
+				/*RTW_INFO("=>%s psta->cmn.mac_addr="MAC_FMT" !\n",
+					__FUNCTION__, MAC_ARG(psta->cmn.mac_addr));*/
+				if ((_rtw_memcmp(psta->cmn.mac_addr, bc_addr, ETH_ALEN) != _TRUE) || (padapter->registrypriv.mp_mode == 1)) {
+					psta_dframe_info->sta_data_rate = pattrib->data_rate;
+					psta_dframe_info->sta_sgi = pattrib->sgi;
+					psta_dframe_info->sta_bw_mode = pattrib->bw;
+					for (rf_path = 0; rf_path < pHalData->NumTotalRFPath; rf_path++) {
+
+						psta_dframe_info->sta_mimo_signal_strength[rf_path] = (p_phy_info->rx_mimo_signal_strength[rf_path]);/*Percentage to dbm*/
+
+						if (!isCCKrate) {
+							psta_dframe_info->sta_ofdm_snr[rf_path] = p_phy_info->rx_snr[rf_path];
+							psta_dframe_info->sta_RxPwr[rf_path] = p_phy_info->rx_pwr[rf_path];
+						}
+					}
+				}
+			}
+		}
+#endif
+	}
+
+}
+
+int hal_efuse_macaddr_offset(_adapter *adapter)
+{
+	u8 interface_type = 0;
+	int addr_offset = -1;
+
+	interface_type = rtw_get_intf_type(adapter);
+
+	switch (rtw_get_chip_type(adapter)) {
+#ifdef CONFIG_RTL8723B
+	case RTL8723B:
+		if (interface_type == RTW_USB)
+			addr_offset = EEPROM_MAC_ADDR_8723BU;
+		else if (interface_type == RTW_SDIO)
+			addr_offset = EEPROM_MAC_ADDR_8723BS;
+		else if (interface_type == RTW_PCIE)
+			addr_offset = EEPROM_MAC_ADDR_8723BE;
+		break;
+#endif
+#ifdef CONFIG_RTL8703B
+	case RTL8703B:
+		if (interface_type == RTW_USB)
+			addr_offset = EEPROM_MAC_ADDR_8703BU;
+		else if (interface_type == RTW_SDIO)
+			addr_offset = EEPROM_MAC_ADDR_8703BS;
+		break;
+#endif
+#ifdef CONFIG_RTL8723D
+	case RTL8723D:
+		if (interface_type == RTW_USB)
+			addr_offset = EEPROM_MAC_ADDR_8723DU;
+		else if (interface_type == RTW_SDIO)
+			addr_offset = EEPROM_MAC_ADDR_8723DS;
+		else if (interface_type == RTW_PCIE)
+			addr_offset = EEPROM_MAC_ADDR_8723DE;
+		break;
+#endif
+
+#ifdef CONFIG_RTL8188E
+	case RTL8188E:
+		if (interface_type == RTW_USB)
+			addr_offset = EEPROM_MAC_ADDR_88EU;
+		else if (interface_type == RTW_SDIO)
+			addr_offset = EEPROM_MAC_ADDR_88ES;
+		else if (interface_type == RTW_PCIE)
+			addr_offset = EEPROM_MAC_ADDR_88EE;
+		break;
+#endif
+#ifdef CONFIG_RTL8188F
+	case RTL8188F:
+		if (interface_type == RTW_USB)
+			addr_offset = EEPROM_MAC_ADDR_8188FU;
+		else if (interface_type == RTW_SDIO)
+			addr_offset = EEPROM_MAC_ADDR_8188FS;
+		break;
+#endif
+#ifdef CONFIG_RTL8188GTV
+	case RTL8188GTV:
+		if (interface_type == RTW_USB)
+			addr_offset = EEPROM_MAC_ADDR_8188GTVU;
+		else if (interface_type == RTW_SDIO)
+			addr_offset = EEPROM_MAC_ADDR_8188GTVS;
+		break;
+#endif
+#ifdef CONFIG_RTL8812A
+	case RTL8812:
+		if (interface_type == RTW_USB)
+			addr_offset = EEPROM_MAC_ADDR_8812AU;
+		else if (interface_type == RTW_PCIE)
+			addr_offset = EEPROM_MAC_ADDR_8812AE;
+		break;
+#endif
+#ifdef CONFIG_RTL8821A
+	case RTL8821:
+		if (interface_type == RTW_USB)
+			addr_offset = EEPROM_MAC_ADDR_8821AU;
+		else if (interface_type == RTW_SDIO)
+			addr_offset = EEPROM_MAC_ADDR_8821AS;
+		else if (interface_type == RTW_PCIE)
+			addr_offset = EEPROM_MAC_ADDR_8821AE;
+		break;
+#endif
+#ifdef CONFIG_RTL8192E
+	case RTL8192E:
+		if (interface_type == RTW_USB)
+			addr_offset = EEPROM_MAC_ADDR_8192EU;
+		else if (interface_type == RTW_SDIO)
+			addr_offset = EEPROM_MAC_ADDR_8192ES;
+		else if (interface_type == RTW_PCIE)
+			addr_offset = EEPROM_MAC_ADDR_8192EE;
+		break;
+#endif
+#ifdef CONFIG_RTL8814A
+	case RTL8814A:
+		if (interface_type == RTW_USB)
+			addr_offset = EEPROM_MAC_ADDR_8814AU;
+		else if (interface_type == RTW_PCIE)
+			addr_offset = EEPROM_MAC_ADDR_8814AE;
+		break;
+#endif
+
+#ifdef CONFIG_RTL8822B
+	case RTL8822B:
+		if (interface_type == RTW_USB)
+			addr_offset = EEPROM_MAC_ADDR_8822BU;
+		else if (interface_type == RTW_SDIO)
+			addr_offset = EEPROM_MAC_ADDR_8822BS;
+		else if (interface_type == RTW_PCIE)
+			addr_offset = EEPROM_MAC_ADDR_8822BE;
+		break;
+#endif /* CONFIG_RTL8822B */
+
+#ifdef CONFIG_RTL8821C
+	case RTL8821C:
+		if (interface_type == RTW_USB)
+			addr_offset = EEPROM_MAC_ADDR_8821CU;
+		else if (interface_type == RTW_SDIO)
+			addr_offset = EEPROM_MAC_ADDR_8821CS;
+		else if (interface_type == RTW_PCIE)
+			addr_offset = EEPROM_MAC_ADDR_8821CE;
+		break;
+#endif /* CONFIG_RTL8821C */
+
+#ifdef CONFIG_RTL8710B
+	case RTL8710B:
+		if (interface_type == RTW_USB)
+			addr_offset = EEPROM_MAC_ADDR_8710B;
+		break;
+#endif
+
+#ifdef CONFIG_RTL8192F
+	case RTL8192F:
+		if (interface_type == RTW_USB)
+			addr_offset = EEPROM_MAC_ADDR_8192FU;
+		else if (interface_type == RTW_SDIO)
+			addr_offset = EEPROM_MAC_ADDR_8192FS;
+		else if (interface_type == RTW_PCIE)
+			addr_offset = EEPROM_MAC_ADDR_8192FE;
+		break;
+#endif /* CONFIG_RTL8192F */
+
+	}
+
+	if (addr_offset == -1) {
+		RTW_ERR("%s: unknown combination - chip_type:%u, interface:%u\n"
+			, __func__, rtw_get_chip_type(adapter), rtw_get_intf_type(adapter));
+	}
+
+	return addr_offset;
+}
+
+int Hal_GetPhyEfuseMACAddr(PADAPTER padapter, u8 *mac_addr)
+{
+	int ret = _FAIL;
+	int addr_offset;
+
+	addr_offset = hal_efuse_macaddr_offset(padapter);
+	if (addr_offset == -1)
+		goto exit;
+
+	ret = rtw_efuse_map_read(padapter, addr_offset, ETH_ALEN, mac_addr);
+
+exit:
+	return ret;
+}
+
+void rtw_dump_cur_efuse(PADAPTER padapter)
+{
+	int i =0;
+	int mapsize =0;
+	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(padapter);
+
+	EFUSE_GetEfuseDefinition(padapter, EFUSE_WIFI, TYPE_EFUSE_MAP_LEN , (void *)&mapsize, _FALSE);
+
+	if (mapsize <= 0 || mapsize > EEPROM_MAX_SIZE) {
+		RTW_ERR("wrong map size %d\n", mapsize);
+		return;
+	}
+
+#ifdef CONFIG_RTW_DEBUG
+	if (hal_data->efuse_file_status == EFUSE_FILE_LOADED)
+		RTW_MAP_DUMP_SEL(RTW_DBGDUMP, "EFUSE FILE", hal_data->efuse_eeprom_data, mapsize);
+	else
+		RTW_MAP_DUMP_SEL(RTW_DBGDUMP, "HW EFUSE", hal_data->efuse_eeprom_data, mapsize);
+#endif
+}
+
+
+#ifdef CONFIG_EFUSE_CONFIG_FILE
+u32 Hal_readPGDataFromConfigFile(PADAPTER padapter)
+{
+	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(padapter);
+	u32 ret = _FALSE;
+	u32 maplen = 0;
+
+	EFUSE_GetEfuseDefinition(padapter, EFUSE_WIFI, TYPE_EFUSE_MAP_LEN , (void *)&maplen, _FALSE);
+
+	if (maplen < 256 || maplen > EEPROM_MAX_SIZE) {
+		RTW_ERR("eFuse length error :%d\n", maplen);
+		return _FALSE;
+	}	
+
+	ret = rtw_read_efuse_from_file(EFUSE_MAP_PATH, hal_data->efuse_eeprom_data, maplen);
+
+	hal_data->efuse_file_status = ((ret == _FAIL) ? EFUSE_FILE_FAILED : EFUSE_FILE_LOADED);
+
+	if (hal_data->efuse_file_status == EFUSE_FILE_LOADED)
+		rtw_dump_cur_efuse(padapter);
+
+	return ret;
+}
+
+u32 Hal_ReadMACAddrFromFile(PADAPTER padapter, u8 *mac_addr)
+{
+	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(padapter);
+	u32 ret = _FAIL;
+
+	if (rtw_read_macaddr_from_file(WIFIMAC_PATH, mac_addr) == _SUCCESS
+		&& rtw_check_invalid_mac_address(mac_addr, _TRUE) == _FALSE
+	) {
+		hal_data->macaddr_file_status = MACADDR_FILE_LOADED;
+		ret = _SUCCESS;
+	} else
+		hal_data->macaddr_file_status = MACADDR_FILE_FAILED;
+
+	return ret;
+}
+#endif /* CONFIG_EFUSE_CONFIG_FILE */
+
+int hal_config_macaddr(_adapter *adapter, bool autoload_fail)
+{
+	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
+	u8 addr[ETH_ALEN];
+	int addr_offset = hal_efuse_macaddr_offset(adapter);
+	u8 *hw_addr = NULL;
+	int ret = _SUCCESS;
+#if defined(CONFIG_RTL8822B) && defined(CONFIG_USB_HCI)
+	u8 ft_mac_addr[ETH_ALEN] = {0x00, 0xff, 0xff, 0xff, 0xff, 0xff}; /* FT USB2 for 8822B */
+#endif
+
+	if (autoload_fail)
+		goto bypass_hw_pg;
+
+	if (addr_offset != -1)
+		hw_addr = &hal_data->efuse_eeprom_data[addr_offset];
+
+#ifdef CONFIG_EFUSE_CONFIG_FILE
+	/* if the hw_addr is written by efuse file, set to NULL */
+	if (hal_data->efuse_file_status == EFUSE_FILE_LOADED)
+		hw_addr = NULL;
+#endif
+
+	if (!hw_addr) {
+		/* try getting hw pg data */
+		if (Hal_GetPhyEfuseMACAddr(adapter, addr) == _SUCCESS)
+			hw_addr = addr;
+	}
+
+#if defined(CONFIG_RTL8822B) && defined(CONFIG_USB_HCI)
+	if (_rtw_memcmp(hw_addr, ft_mac_addr, ETH_ALEN))
+		hw_addr[0] = 0xff;
+#endif
+
+	/* check hw pg data */
+	if (hw_addr && rtw_check_invalid_mac_address(hw_addr, _TRUE) == _FALSE) {
+		_rtw_memcpy(hal_data->EEPROMMACAddr, hw_addr, ETH_ALEN);
+		goto exit;
+	}
+
+bypass_hw_pg:
+
+#ifdef CONFIG_EFUSE_CONFIG_FILE
+	/* check wifi mac file */
+	if (Hal_ReadMACAddrFromFile(adapter, addr) == _SUCCESS) {
+		_rtw_memcpy(hal_data->EEPROMMACAddr, addr, ETH_ALEN);
+		goto exit;
+	}
+#endif
+
+	_rtw_memset(hal_data->EEPROMMACAddr, 0, ETH_ALEN);
+	ret = _FAIL;
+
+exit:
+	return ret;
+}
+
+#ifdef CONFIG_RF_POWER_TRIM
+u32 Array_kfreemap[] = {
+	0x08, 0xe,
+	0x06, 0xc,
+	0x04, 0xa,
+	0x02, 0x8,
+	0x00, 0x6,
+	0x03, 0x4,
+	0x05, 0x2,
+	0x07, 0x0,
+	0x09, 0x0,
+	0x0c, 0x0,
+};
+
+void rtw_bb_rf_gain_offset(_adapter *padapter)
+{
+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(padapter);
+	struct registry_priv  *registry_par = &padapter->registrypriv;
+	struct kfree_data_t *kfree_data = &pHalData->kfree_data;
+	u8		value = pHalData->EEPROMRFGainOffset;
+	u8		tmp = 0x3e;
+	u32		res, i = 0;
+	u4Byte		ArrayLen	= sizeof(Array_kfreemap) / sizeof(u32);
+	pu4Byte		Array	= Array_kfreemap;
+	u4Byte		v1 = 0, v2 = 0, GainValue = 0, target = 0;
+
+	if (registry_par->RegPwrTrimEnable == 2) {
+		RTW_INFO("Registry kfree default force disable.\n");
+		return;
+	}
+
+#if defined(CONFIG_RTL8723B)
+	if (value & BIT4 && (registry_par->RegPwrTrimEnable == 1)) {
+		RTW_INFO("Offset RF Gain.\n");
+		RTW_INFO("Offset RF Gain.  pHalData->EEPROMRFGainVal=0x%x\n", pHalData->EEPROMRFGainVal);
+
+		if (pHalData->EEPROMRFGainVal != 0xff) {
+
+			if (pHalData->ant_path == RF_PATH_A)
+				GainValue = (pHalData->EEPROMRFGainVal & 0x0f);
+
+			else
+				GainValue = (pHalData->EEPROMRFGainVal & 0xf0) >> 4;
+			RTW_INFO("Ant PATH_%d GainValue Offset = 0x%x\n", (pHalData->ant_path == RF_PATH_A) ? (RF_PATH_A) : (RF_PATH_B), GainValue);
+
+			for (i = 0; i < ArrayLen; i += 2) {
+				/* RTW_INFO("ArrayLen in =%d ,Array 1 =0x%x ,Array2 =0x%x\n",i,Array[i],Array[i]+1); */
+				v1 = Array[i];
+				v2 = Array[i + 1];
+				if (v1 == GainValue) {
+					RTW_INFO("Offset RF Gain. got v1 =0x%x ,v2 =0x%x\n", v1, v2);
+					target = v2;
+					break;
+				}
+			}
+			RTW_INFO("pHalData->EEPROMRFGainVal=0x%x ,Gain offset Target Value=0x%x\n", pHalData->EEPROMRFGainVal, target);
+
+			res = rtw_hal_read_rfreg(padapter, RF_PATH_A, 0x7f, 0xffffffff);
+			RTW_INFO("Offset RF Gain. before reg 0x7f=0x%08x\n", res);
+			phy_set_rf_reg(padapter, RF_PATH_A, REG_RF_BB_GAIN_OFFSET, BIT18 | BIT17 | BIT16 | BIT15, target);
+			res = rtw_hal_read_rfreg(padapter, RF_PATH_A, 0x7f, 0xffffffff);
+
+			RTW_INFO("Offset RF Gain. After reg 0x7f=0x%08x\n", res);
+
+		} else
+
+			RTW_INFO("Offset RF Gain.  pHalData->EEPROMRFGainVal=0x%x	!= 0xff, didn't run Kfree\n", pHalData->EEPROMRFGainVal);
+	} else
+		RTW_INFO("Using the default RF gain.\n");
+
+#elif defined(CONFIG_RTL8188E)
+	if (value & BIT4 && (registry_par->RegPwrTrimEnable == 1)) {
+		RTW_INFO("8188ES Offset RF Gain.\n");
+		RTW_INFO("8188ES Offset RF Gain. EEPROMRFGainVal=0x%x\n",
+			 pHalData->EEPROMRFGainVal);
+
+		if (pHalData->EEPROMRFGainVal != 0xff) {
+			res = rtw_hal_read_rfreg(padapter, RF_PATH_A,
+					 REG_RF_BB_GAIN_OFFSET, 0xffffffff);
+
+			RTW_INFO("Offset RF Gain. reg 0x55=0x%x\n", res);
+			res &= 0xfff87fff;
+
+			res |= (pHalData->EEPROMRFGainVal & 0x0f) << 15;
+			RTW_INFO("Offset RF Gain. res=0x%x\n", res);
+
+			rtw_hal_write_rfreg(padapter, RF_PATH_A,
+					    REG_RF_BB_GAIN_OFFSET,
+					    RF_GAIN_OFFSET_MASK, res);
+		} else {
+			RTW_INFO("Offset RF Gain. EEPROMRFGainVal=0x%x == 0xff, didn't run Kfree\n",
+				 pHalData->EEPROMRFGainVal);
+		}
+	} else
+		RTW_INFO("Using the default RF gain.\n");
+#else
+	/* TODO: call this when channel switch */
+	if (kfree_data->flag & KFREE_FLAG_ON)
+		rtw_rf_apply_tx_gain_offset(padapter, 6); /* input ch6 to select BB_GAIN_2G */
+#endif
+
+}
+#endif /*CONFIG_RF_POWER_TRIM */
+
+bool kfree_data_is_bb_gain_empty(struct kfree_data_t *data)
+{
+#ifdef CONFIG_RF_POWER_TRIM
+	int i, j;
+
+	for (i = 0; i < BB_GAIN_NUM; i++)
+		for (j = 0; j < RF_PATH_MAX; j++)
+			if (data->bb_gain[i][j] != 0)
+				return 0;
+#endif
+	return 1;
+}
+
+#ifdef CONFIG_USB_RX_AGGREGATION
+void rtw_set_usb_agg_by_mode_normal(_adapter *padapter, u8 cur_wireless_mode)
+{
+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(padapter);
+	if (cur_wireless_mode < WIRELESS_11_24N
+	    && cur_wireless_mode > 0) { /* ABG mode */
+#ifdef CONFIG_PREALLOC_RX_SKB_BUFFER
+		u32 remainder = 0;
+		u8 quotient = 0;
+
+		remainder = MAX_RECVBUF_SZ % (4 * 1024);
+		quotient = (u8)(MAX_RECVBUF_SZ >> 12);
+
+		if (quotient > 5) {
+			pHalData->rxagg_usb_size = 0x6;
+			pHalData->rxagg_usb_timeout = 0x10;
+		} else {
+			if (remainder >= 2048) {
+				pHalData->rxagg_usb_size = quotient;
+				pHalData->rxagg_usb_timeout = 0x10;
+			} else {
+				pHalData->rxagg_usb_size = (quotient - 1);
+				pHalData->rxagg_usb_timeout = 0x10;
+			}
+		}
+#else /* !CONFIG_PREALLOC_RX_SKB_BUFFER */
+		if (0x6 != pHalData->rxagg_usb_size || 0x10 != pHalData->rxagg_usb_timeout) {
+			pHalData->rxagg_usb_size = 0x6;
+			pHalData->rxagg_usb_timeout = 0x10;
+			rtw_write16(padapter, REG_RXDMA_AGG_PG_TH,
+				pHalData->rxagg_usb_size | (pHalData->rxagg_usb_timeout << 8));
+		}
+#endif /* CONFIG_PREALLOC_RX_SKB_BUFFER */
+
+	} else if (cur_wireless_mode >= WIRELESS_11_24N
+		   && cur_wireless_mode <= WIRELESS_MODE_MAX) { /* N AC mode */
+#ifdef CONFIG_PREALLOC_RX_SKB_BUFFER
+		u32 remainder = 0;
+		u8 quotient = 0;
+
+		remainder = MAX_RECVBUF_SZ % (4 * 1024);
+		quotient = (u8)(MAX_RECVBUF_SZ >> 12);
+
+		if (quotient > 5) {
+			pHalData->rxagg_usb_size = 0x5;
+			pHalData->rxagg_usb_timeout = 0x20;
+		} else {
+			if (remainder >= 2048) {
+				pHalData->rxagg_usb_size = quotient;
+				pHalData->rxagg_usb_timeout = 0x10;
+			} else {
+				pHalData->rxagg_usb_size = (quotient - 1);
+				pHalData->rxagg_usb_timeout = 0x10;
+			}
+		}
+#else /* !CONFIG_PREALLOC_RX_SKB_BUFFER */
+		if ((0x5 != pHalData->rxagg_usb_size) || (0x20 != pHalData->rxagg_usb_timeout)) {
+			pHalData->rxagg_usb_size = 0x5;
+			pHalData->rxagg_usb_timeout = 0x20;
+			rtw_write16(padapter, REG_RXDMA_AGG_PG_TH,
+				pHalData->rxagg_usb_size | (pHalData->rxagg_usb_timeout << 8));
+		}
+#endif /* CONFIG_PREALLOC_RX_SKB_BUFFER */
+
+	} else {
+		/* RTW_INFO("%s: Unknow wireless mode(0x%x)\n",__func__,padapter->mlmeextpriv.cur_wireless_mode); */
+	}
+}
+
+void rtw_set_usb_agg_by_mode_customer(_adapter *padapter, u8 cur_wireless_mode, u8 UsbDmaSize, u8 Legacy_UsbDmaSize)
+{
+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(padapter);
+
+	if (cur_wireless_mode < WIRELESS_11_24N
+	    && cur_wireless_mode > 0) { /* ABG mode */
+		if (Legacy_UsbDmaSize != pHalData->rxagg_usb_size
+		    || 0x10 != pHalData->rxagg_usb_timeout) {
+			pHalData->rxagg_usb_size = Legacy_UsbDmaSize;
+			pHalData->rxagg_usb_timeout = 0x10;
+			rtw_write16(padapter, REG_RXDMA_AGG_PG_TH,
+				pHalData->rxagg_usb_size | (pHalData->rxagg_usb_timeout << 8));
+		}
+	} else if (cur_wireless_mode >= WIRELESS_11_24N
+		   && cur_wireless_mode <= WIRELESS_MODE_MAX) { /* N AC mode */
+		if (UsbDmaSize != pHalData->rxagg_usb_size
+		    || 0x20 != pHalData->rxagg_usb_timeout) {
+			pHalData->rxagg_usb_size = UsbDmaSize;
+			pHalData->rxagg_usb_timeout = 0x20;
+			rtw_write16(padapter, REG_RXDMA_AGG_PG_TH,
+				pHalData->rxagg_usb_size | (pHalData->rxagg_usb_timeout << 8));
+		}
+	} else {
+		/* RTW_INFO("%s: Unknown wireless mode(0x%x)\n",__func__,padapter->mlmeextpriv.cur_wireless_mode); */
+	}
+}
+
+void rtw_set_usb_agg_by_mode(_adapter *padapter, u8 cur_wireless_mode)
+{
+#ifdef CONFIG_PLATFORM_NOVATEK_NT72668
+	rtw_set_usb_agg_by_mode_customer(padapter, cur_wireless_mode, 0x3, 0x3);
+	return;
+#endif /* CONFIG_PLATFORM_NOVATEK_NT72668 */
+
+	rtw_set_usb_agg_by_mode_normal(padapter, cur_wireless_mode);
+}
+#endif /* CONFIG_USB_RX_AGGREGATION */
+
+/* To avoid RX affect TX throughput */
+void dm_DynamicUsbTxAgg(_adapter *padapter, u8 from_timer)
+{
+	struct dvobj_priv	*pdvobjpriv = adapter_to_dvobj(padapter);
+	struct mlme_priv		*pmlmepriv = &(padapter->mlmepriv);
+	struct registry_priv *registry_par = &padapter->registrypriv;
+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(padapter);
+	u8 cur_wireless_mode = WIRELESS_INVALID;
+
+#ifdef CONFIG_USB_RX_AGGREGATION
+	if (!registry_par->dynamic_agg_enable)
+		return;
+
+#ifdef RTW_HALMAC
+	if (IS_HARDWARE_TYPE_8822BU(padapter) || IS_HARDWARE_TYPE_8821CU(padapter))
+		rtw_hal_set_hwreg(padapter, HW_VAR_RXDMA_AGG_PG_TH, NULL);
+#else /* !RTW_HALMAC */
+	if (IS_HARDWARE_TYPE_8821U(padapter)) { /* || IS_HARDWARE_TYPE_8192EU(padapter)) */
+		/* This AGG_PH_TH only for UsbRxAggMode == USB_RX_AGG_USB */
+		if ((pHalData->rxagg_mode == RX_AGG_USB) && (check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE)) {
+			if (pdvobjpriv->traffic_stat.cur_tx_tp > 2 && pdvobjpriv->traffic_stat.cur_rx_tp < 30)
+				rtw_write16(padapter , REG_RXDMA_AGG_PG_TH , 0x1010);
+			else if (pdvobjpriv->traffic_stat.last_tx_bytes > 220000 && pdvobjpriv->traffic_stat.cur_rx_tp < 30)
+				rtw_write16(padapter , REG_RXDMA_AGG_PG_TH , 0x1006);
+			else
+				rtw_write16(padapter, REG_RXDMA_AGG_PG_TH, 0x2005); /* dmc agg th 20K */
+
+			/* RTW_INFO("TX_TP=%u, RX_TP=%u\n", pdvobjpriv->traffic_stat.cur_tx_tp, pdvobjpriv->traffic_stat.cur_rx_tp); */
+		}
+	} else if (IS_HARDWARE_TYPE_8812(padapter)) {
+#ifdef CONFIG_CONCURRENT_MODE
+		u8 i;
+		_adapter *iface;
+		u8 bassocaed = _FALSE;
+		struct mlme_ext_priv *mlmeext;
+
+		for (i = 0; i < pdvobjpriv->iface_nums; i++) {
+			iface = pdvobjpriv->padapters[i];
+			mlmeext = &iface->mlmeextpriv;
+			if (rtw_linked_check(iface) == _TRUE) {
+				if (mlmeext->cur_wireless_mode >= cur_wireless_mode)
+					cur_wireless_mode = mlmeext->cur_wireless_mode;
+				bassocaed = _TRUE;
+			}
+		}
+		if (bassocaed)
+#endif
+			rtw_set_usb_agg_by_mode(padapter, cur_wireless_mode);
+#ifdef CONFIG_PLATFORM_NOVATEK_NT72668
+	} else {
+		rtw_set_usb_agg_by_mode(padapter, cur_wireless_mode);
+#endif /* CONFIG_PLATFORM_NOVATEK_NT72668 */
+	}
+#endif /* RTW_HALMAC */
+#endif /* CONFIG_USB_RX_AGGREGATION */
+
+}
+
+/* bus-agg check for SoftAP mode */
+inline u8 rtw_hal_busagg_qsel_check(_adapter *padapter, u8 pre_qsel, u8 next_qsel)
+{
+	struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
+	u8 chk_rst = _SUCCESS;
+
+	if (!MLME_IS_AP(padapter) && !MLME_IS_MESH(padapter))
+		return chk_rst;
+
+	/* if((pre_qsel == 0xFF)||(next_qsel== 0xFF)) */
+	/*	return chk_rst; */
+
+	if (((pre_qsel == QSLT_HIGH) || ((next_qsel == QSLT_HIGH)))
+	    && (pre_qsel != next_qsel)) {
+		/* RTW_INFO("### bus-agg break cause of qsel misatch, pre_qsel=0x%02x,next_qsel=0x%02x ###\n", */
+		/*	pre_qsel,next_qsel); */
+		chk_rst = _FAIL;
+	}
+	return chk_rst;
+}
+
+/*
+ * Description:
+ * dump_TX_FIFO: This is only used to dump TX_FIFO for debug WoW mode offload
+ * contant.
+ *
+ * Input:
+ * adapter: adapter pointer.
+ * page_num: The max. page number that user want to dump.
+ * page_size: page size of each page. eg. 128 bytes, 256 bytes, 512byte.
+ */
+void dump_TX_FIFO(_adapter *padapter, u8 page_num, u16 page_size)
+{
+
+	int i;
+	u8 val = 0;
+	u8 base = 0;
+	u32 addr = 0;
+	u32 count = (page_size / 8);
+
+	if (page_num <= 0) {
+		RTW_INFO("!!%s: incorrect input page_num paramter!\n", __func__);
+		return;
+	}
+
+	if (page_size < 128 || page_size > 512) {
+		RTW_INFO("!!%s: incorrect input page_size paramter!\n", __func__);
+		return;
+	}
+
+	RTW_INFO("+%s+\n", __func__);
+	val = rtw_read8(padapter, 0x106);
+	rtw_write8(padapter, 0x106, 0x69);
+	RTW_INFO("0x106: 0x%02x\n", val);
+	base = rtw_read8(padapter, 0x209);
+	RTW_INFO("0x209: 0x%02x\n", base);
+
+	addr = ((base)*page_size) / 8;
+	for (i = 0 ; i < page_num * count ; i += 2) {
+		rtw_write32(padapter, 0x140, addr + i);
+		printk(" %08x %08x ", rtw_read32(padapter, 0x144), rtw_read32(padapter, 0x148));
+		rtw_write32(padapter, 0x140, addr + i + 1);
+		printk(" %08x %08x\n", rtw_read32(padapter, 0x144), rtw_read32(padapter, 0x148));
+	}
+}
+
+#ifdef CONFIG_GPIO_API
+u8 rtw_hal_get_gpio(_adapter *adapter, u8 gpio_num)
+{
+	u8 value = 0;
+	u8 direction = 0;
+	u32 gpio_pin_input_val = REG_GPIO_PIN_CTRL;
+	u32 gpio_pin_output_val = REG_GPIO_PIN_CTRL + 1;
+	u32 gpio_pin_output_en = REG_GPIO_PIN_CTRL + 2;
+	u8 gpio_num_to_set = gpio_num;
+	struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(adapter);
+
+	if (rtw_hal_gpio_func_check(adapter, gpio_num) == _FAIL)
+		return value;
+
+	rtw_ps_deny(adapter, PS_DENY_IOCTL);
+
+	RTW_INFO("rf_pwrstate=0x%02x\n", pwrpriv->rf_pwrstate);
+	LeaveAllPowerSaveModeDirect(adapter);
+
+	if (gpio_num > 7) {
+		gpio_pin_input_val = REG_GPIO_PIN_CTRL_2;
+		gpio_pin_output_val = REG_GPIO_PIN_CTRL_2 + 1;
+		gpio_pin_output_en = REG_GPIO_PIN_CTRL_2 + 2;
+		gpio_num_to_set = gpio_num - 8;
+	}
+
+	/* Read GPIO Direction */
+	direction = (rtw_read8(adapter, gpio_pin_output_en) & BIT(gpio_num_to_set)) >> gpio_num_to_set;
+
+	/* According the direction to read register value */
+	if (direction)
+		value =  (rtw_read8(adapter, gpio_pin_output_val) & BIT(gpio_num_to_set)) >> gpio_num_to_set;
+	else
+		value =  (rtw_read8(adapter, gpio_pin_input_val) & BIT(gpio_num_to_set)) >> gpio_num_to_set;
+
+	rtw_ps_deny_cancel(adapter, PS_DENY_IOCTL);
+	RTW_INFO("%s direction=%d value=%d\n", __FUNCTION__, direction, value);
+
+	return value;
+}
+
+int  rtw_hal_set_gpio_output_value(_adapter *adapter, u8 gpio_num, bool isHigh)
+{
+	u8 direction = 0;
+	u8 res = -1;
+	u32 gpio_pin_output_val = REG_GPIO_PIN_CTRL + 1;
+	u32 gpio_pin_output_en = REG_GPIO_PIN_CTRL + 2;
+	u8 gpio_num_to_set = gpio_num;
+
+	if (rtw_hal_gpio_func_check(adapter, gpio_num) == _FAIL)
+		return -1;
+
+	rtw_ps_deny(adapter, PS_DENY_IOCTL);
+
+	LeaveAllPowerSaveModeDirect(adapter);
+
+	if (gpio_num > 7) {
+		gpio_pin_output_val = REG_GPIO_PIN_CTRL_2 + 1;
+		gpio_pin_output_en = REG_GPIO_PIN_CTRL_2 + 2;
+		gpio_num_to_set = gpio_num - 8;
+	}
+
+	/* Read GPIO direction */
+	direction = (rtw_read8(adapter, gpio_pin_output_en) & BIT(gpio_num_to_set)) >> gpio_num_to_set;
+
+	/* If GPIO is output direction, setting value. */
+	if (direction) {
+		if (isHigh)
+			rtw_write8(adapter, gpio_pin_output_val, rtw_read8(adapter, gpio_pin_output_val) | BIT(gpio_num_to_set));
+		else
+			rtw_write8(adapter, gpio_pin_output_val, rtw_read8(adapter, gpio_pin_output_val) & ~BIT(gpio_num_to_set));
+
+		RTW_INFO("%s Set gpio %x[%d]=%d\n", __FUNCTION__, REG_GPIO_PIN_CTRL + 1, gpio_num, isHigh);
+		res = 0;
+	} else {
+		RTW_INFO("%s The gpio is input,not be set!\n", __FUNCTION__);
+		res = -1;
+	}
+
+	rtw_ps_deny_cancel(adapter, PS_DENY_IOCTL);
+	return res;
+}
+
+int rtw_hal_config_gpio(_adapter *adapter, u8 gpio_num, bool isOutput)
+{
+	u32 gpio_ctrl_reg_to_set = REG_GPIO_PIN_CTRL + 2;
+	u8 gpio_num_to_set = gpio_num;
+
+	if (rtw_hal_gpio_func_check(adapter, gpio_num) == _FAIL)
+		return -1;
+
+	RTW_INFO("%s gpio_num =%d direction=%d\n", __FUNCTION__, gpio_num, isOutput);
+
+	rtw_ps_deny(adapter, PS_DENY_IOCTL);
+
+	LeaveAllPowerSaveModeDirect(adapter);
+
+	rtw_hal_gpio_multi_func_reset(adapter, gpio_num);
+
+	if (gpio_num > 7) {
+		gpio_ctrl_reg_to_set = REG_GPIO_PIN_CTRL_2 + 2;
+		gpio_num_to_set = gpio_num - 8;
+	}
+
+	if (isOutput)
+		rtw_write8(adapter, gpio_ctrl_reg_to_set, rtw_read8(adapter, gpio_ctrl_reg_to_set) | BIT(gpio_num_to_set));
+	else
+		rtw_write8(adapter, gpio_ctrl_reg_to_set, rtw_read8(adapter, gpio_ctrl_reg_to_set) & ~BIT(gpio_num_to_set));
+
+	rtw_ps_deny_cancel(adapter, PS_DENY_IOCTL);
+
+	return 0;
+}
+int rtw_hal_register_gpio_interrupt(_adapter *adapter, int gpio_num, void(*callback)(u8 level))
+{
+	u8 value;
+	u8 direction;
+	PHAL_DATA_TYPE phal = GET_HAL_DATA(adapter);
+
+	if (IS_HARDWARE_TYPE_8188E(adapter)) {
+		if (gpio_num > 7 || gpio_num < 4) {
+			RTW_PRINT("%s The gpio number does not included 4~7.\n", __FUNCTION__);
+			return -1;
+		}
+	}
+
+	rtw_ps_deny(adapter, PS_DENY_IOCTL);
+
+	LeaveAllPowerSaveModeDirect(adapter);
+
+	/* Read GPIO direction */
+	direction = (rtw_read8(adapter, REG_GPIO_PIN_CTRL + 2) & BIT(gpio_num)) >> gpio_num;
+	if (direction) {
+		RTW_PRINT("%s Can't register output gpio as interrupt.\n", __FUNCTION__);
+		return -1;
+	}
+
+	/* Config GPIO Mode */
+	rtw_write8(adapter, REG_GPIO_PIN_CTRL + 3, rtw_read8(adapter, REG_GPIO_PIN_CTRL + 3) | BIT(gpio_num));
+
+	/* Register GPIO interrupt handler*/
+	adapter->gpiointpriv.callback[gpio_num] = callback;
+
+	/* Set GPIO interrupt mode, 0:positive edge, 1:negative edge */
+	value = rtw_read8(adapter, REG_GPIO_PIN_CTRL) & BIT(gpio_num);
+	adapter->gpiointpriv.interrupt_mode = rtw_read8(adapter, REG_HSIMR + 2) ^ value;
+	rtw_write8(adapter, REG_GPIO_INTM, adapter->gpiointpriv.interrupt_mode);
+
+	/* Enable GPIO interrupt */
+	adapter->gpiointpriv.interrupt_enable_mask = rtw_read8(adapter, REG_HSIMR + 2) | BIT(gpio_num);
+	rtw_write8(adapter, REG_HSIMR + 2, adapter->gpiointpriv.interrupt_enable_mask);
+
+	rtw_hal_update_hisr_hsisr_ind(adapter, 1);
+
+	rtw_ps_deny_cancel(adapter, PS_DENY_IOCTL);
+
+	return 0;
+}
+int rtw_hal_disable_gpio_interrupt(_adapter *adapter, int gpio_num)
+{
+	u8 value;
+	u8 direction;
+	PHAL_DATA_TYPE phal = GET_HAL_DATA(adapter);
+
+	if (IS_HARDWARE_TYPE_8188E(adapter)) {
+		if (gpio_num > 7 || gpio_num < 4) {
+			RTW_INFO("%s The gpio number does not included 4~7.\n", __FUNCTION__);
+			return -1;
+		}
+	}
+
+	rtw_ps_deny(adapter, PS_DENY_IOCTL);
+
+	LeaveAllPowerSaveModeDirect(adapter);
+
+	/* Config GPIO Mode */
+	rtw_write8(adapter, REG_GPIO_PIN_CTRL + 3, rtw_read8(adapter, REG_GPIO_PIN_CTRL + 3) & ~BIT(gpio_num));
+
+	/* Unregister GPIO interrupt handler*/
+	adapter->gpiointpriv.callback[gpio_num] = NULL;
+
+	/* Reset GPIO interrupt mode, 0:positive edge, 1:negative edge */
+	adapter->gpiointpriv.interrupt_mode = rtw_read8(adapter, REG_GPIO_INTM) & ~BIT(gpio_num);
+	rtw_write8(adapter, REG_GPIO_INTM, 0x00);
+
+	/* Disable GPIO interrupt */
+	adapter->gpiointpriv.interrupt_enable_mask = rtw_read8(adapter, REG_HSIMR + 2) & ~BIT(gpio_num);
+	rtw_write8(adapter, REG_HSIMR + 2, adapter->gpiointpriv.interrupt_enable_mask);
+
+	if (!adapter->gpiointpriv.interrupt_enable_mask)
+		rtw_hal_update_hisr_hsisr_ind(adapter, 0);
+
+	rtw_ps_deny_cancel(adapter, PS_DENY_IOCTL);
+
+	return 0;
+}
+#endif
+
+s8 rtw_hal_ch_sw_iqk_info_search(_adapter *padapter, u8 central_chnl, u8 bw_mode)
+{
+	HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
+	u8 i;
+
+	for (i = 0; i < MAX_IQK_INFO_BACKUP_CHNL_NUM; i++) {
+		if ((pHalData->iqk_reg_backup[i].central_chnl != 0)) {
+			if ((pHalData->iqk_reg_backup[i].central_chnl == central_chnl)
+			    && (pHalData->iqk_reg_backup[i].bw_mode == bw_mode))
+				return i;
+		}
+	}
+
+	return -1;
+}
+
+void rtw_hal_ch_sw_iqk_info_backup(_adapter *padapter)
+{
+	HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
+	s8 res;
+	u8 i;
+
+	/* If it's an existed record, overwrite it */
+	res = rtw_hal_ch_sw_iqk_info_search(padapter, pHalData->current_channel, pHalData->current_channel_bw);
+	if ((res >= 0) && (res < MAX_IQK_INFO_BACKUP_CHNL_NUM)) {
+		rtw_hal_set_hwreg(padapter, HW_VAR_CH_SW_IQK_INFO_BACKUP, (u8 *)&(pHalData->iqk_reg_backup[res]));
+		return;
+	}
+
+	/* Search for the empty record to use */
+	for (i = 0; i < MAX_IQK_INFO_BACKUP_CHNL_NUM; i++) {
+		if (pHalData->iqk_reg_backup[i].central_chnl == 0) {
+			rtw_hal_set_hwreg(padapter, HW_VAR_CH_SW_IQK_INFO_BACKUP, (u8 *)&(pHalData->iqk_reg_backup[i]));
+			return;
+		}
+	}
+
+	/* Else, overwrite the oldest record */
+	for (i = 1; i < MAX_IQK_INFO_BACKUP_CHNL_NUM; i++)
+		_rtw_memcpy(&(pHalData->iqk_reg_backup[i - 1]), &(pHalData->iqk_reg_backup[i]), sizeof(struct hal_iqk_reg_backup));
+
+	rtw_hal_set_hwreg(padapter, HW_VAR_CH_SW_IQK_INFO_BACKUP, (u8 *)&(pHalData->iqk_reg_backup[MAX_IQK_INFO_BACKUP_CHNL_NUM - 1]));
+}
+
+void rtw_hal_ch_sw_iqk_info_restore(_adapter *padapter, u8 ch_sw_use_case)
+{
+	rtw_hal_set_hwreg(padapter, HW_VAR_CH_SW_IQK_INFO_RESTORE, &ch_sw_use_case);
+}
+
+void rtw_dump_mac_rx_counters(_adapter *padapter, struct dbg_rx_counter *rx_counter)
+{
+	u32	mac_cck_ok = 0, mac_ofdm_ok = 0, mac_ht_ok = 0, mac_vht_ok = 0;
+	u32	mac_cck_err = 0, mac_ofdm_err = 0, mac_ht_err = 0, mac_vht_err = 0;
+	u32	mac_cck_fa = 0, mac_ofdm_fa = 0, mac_ht_fa = 0;
+	u32	DropPacket = 0;
+
+	if (!rx_counter) {
+		rtw_warn_on(1);
+		return;
+	}
+	if (IS_HARDWARE_TYPE_JAGUAR(padapter) || IS_HARDWARE_TYPE_JAGUAR2(padapter))
+		phy_set_mac_reg(padapter, REG_RXERR_RPT, BIT26, 0x0);/*clear bit-26*/
+
+	phy_set_mac_reg(padapter, REG_RXERR_RPT, BIT28 | BIT29 | BIT30 | BIT31, 0x3);
+	mac_cck_ok	= phy_query_mac_reg(padapter, REG_RXERR_RPT, bMaskLWord);/* [15:0]	  */
+	phy_set_mac_reg(padapter, REG_RXERR_RPT, BIT28 | BIT29 | BIT30 | BIT31, 0x0);
+	mac_ofdm_ok	= phy_query_mac_reg(padapter, REG_RXERR_RPT, bMaskLWord);/* [15:0]	 */
+	phy_set_mac_reg(padapter, REG_RXERR_RPT, BIT28 | BIT29 | BIT30 | BIT31, 0x6);
+	mac_ht_ok	= phy_query_mac_reg(padapter, REG_RXERR_RPT, bMaskLWord);/* [15:0]	 */
+	mac_vht_ok	= 0;
+	if (IS_HARDWARE_TYPE_JAGUAR(padapter) || IS_HARDWARE_TYPE_JAGUAR2(padapter)) {
+		phy_set_mac_reg(padapter, REG_RXERR_RPT, BIT28 | BIT29 | BIT30 | BIT31, 0x0);
+		phy_set_mac_reg(padapter, REG_RXERR_RPT, BIT26, 0x1);
+		mac_vht_ok	= phy_query_mac_reg(padapter, REG_RXERR_RPT, bMaskLWord);/* [15:0]*/
+		phy_set_mac_reg(padapter, REG_RXERR_RPT, BIT26, 0x0);/*clear bit-26*/
+	}
+
+	phy_set_mac_reg(padapter, REG_RXERR_RPT, BIT28 | BIT29 | BIT30 | BIT31, 0x4);
+	mac_cck_err	= phy_query_mac_reg(padapter, REG_RXERR_RPT, bMaskLWord);/* [15:0]	 */
+	phy_set_mac_reg(padapter, REG_RXERR_RPT, BIT28 | BIT29 | BIT30 | BIT31, 0x1);
+	mac_ofdm_err	= phy_query_mac_reg(padapter, REG_RXERR_RPT, bMaskLWord);/* [15:0]	 */
+	phy_set_mac_reg(padapter, REG_RXERR_RPT, BIT28 | BIT29 | BIT30 | BIT31, 0x7);
+	mac_ht_err	= phy_query_mac_reg(padapter, REG_RXERR_RPT, bMaskLWord);/* [15:0]		 */
+	mac_vht_err	= 0;
+	if (IS_HARDWARE_TYPE_JAGUAR(padapter) || IS_HARDWARE_TYPE_JAGUAR2(padapter)) {
+		phy_set_mac_reg(padapter, REG_RXERR_RPT, BIT28 | BIT29 | BIT30 | BIT31, 0x1);
+		phy_set_mac_reg(padapter, REG_RXERR_RPT, BIT26, 0x1);
+		mac_vht_err	= phy_query_mac_reg(padapter, REG_RXERR_RPT, bMaskLWord);/* [15:0]*/
+		phy_set_mac_reg(padapter, REG_RXERR_RPT, BIT26, 0x0);/*clear bit-26*/
+	}
+
+	phy_set_mac_reg(padapter, REG_RXERR_RPT, BIT28 | BIT29 | BIT30 | BIT31, 0x5);
+	mac_cck_fa	= phy_query_mac_reg(padapter, REG_RXERR_RPT, bMaskLWord);/* [15:0]	 */
+	phy_set_mac_reg(padapter, REG_RXERR_RPT, BIT28 | BIT29 | BIT30 | BIT31, 0x2);
+	mac_ofdm_fa	= phy_query_mac_reg(padapter, REG_RXERR_RPT, bMaskLWord);/* [15:0]	 */
+	phy_set_mac_reg(padapter, REG_RXERR_RPT, BIT28 | BIT29 | BIT30 | BIT31, 0x9);
+	mac_ht_fa	= phy_query_mac_reg(padapter, REG_RXERR_RPT, bMaskLWord);/* [15:0]		 */
+
+	/* Mac_DropPacket */
+	rtw_write32(padapter, REG_RXERR_RPT, (rtw_read32(padapter, REG_RXERR_RPT) & 0x0FFFFFFF) | Mac_DropPacket);
+	DropPacket = rtw_read32(padapter, REG_RXERR_RPT) & 0x0000FFFF;
+
+	rx_counter->rx_pkt_ok = mac_cck_ok + mac_ofdm_ok + mac_ht_ok + mac_vht_ok;
+	rx_counter->rx_pkt_crc_error = mac_cck_err + mac_ofdm_err + mac_ht_err + mac_vht_err;
+	rx_counter->rx_cck_fa = mac_cck_fa;
+	rx_counter->rx_ofdm_fa = mac_ofdm_fa;
+	rx_counter->rx_ht_fa = mac_ht_fa;
+	rx_counter->rx_pkt_drop = DropPacket;
+}
+void rtw_reset_mac_rx_counters(_adapter *padapter)
+{
+
+	/* If no packet rx, MaxRx clock be gating ,BIT_DISGCLK bit19 set 1 for fix*/
+	if (IS_HARDWARE_TYPE_8703B(padapter) ||
+		IS_HARDWARE_TYPE_8723D(padapter) ||
+		IS_HARDWARE_TYPE_8188F(padapter) ||
+		IS_HARDWARE_TYPE_8188GTV(padapter) ||
+		IS_HARDWARE_TYPE_8192F(padapter))
+		phy_set_mac_reg(padapter, REG_RCR, BIT19, 0x1);
+
+	/* reset mac counter */
+	phy_set_mac_reg(padapter, REG_RXERR_RPT, BIT27, 0x1);
+	phy_set_mac_reg(padapter, REG_RXERR_RPT, BIT27, 0x0);
+}
+
+void rtw_dump_phy_rx_counters(_adapter *padapter, struct dbg_rx_counter *rx_counter)
+{
+	u32 cckok = 0, cckcrc = 0, ofdmok = 0, ofdmcrc = 0, htok = 0, htcrc = 0, OFDM_FA = 0, CCK_FA = 0, vht_ok = 0, vht_err = 0;
+	if (!rx_counter) {
+		rtw_warn_on(1);
+		return;
+	}
+	if (IS_HARDWARE_TYPE_JAGUAR(padapter) || IS_HARDWARE_TYPE_JAGUAR2(padapter)) {
+		cckok	= phy_query_bb_reg(padapter, 0xF04, 0x3FFF);	     /* [13:0] */
+		ofdmok	= phy_query_bb_reg(padapter, 0xF14, 0x3FFF);	     /* [13:0] */
+		htok		= phy_query_bb_reg(padapter, 0xF10, 0x3FFF);     /* [13:0] */
+		vht_ok	= phy_query_bb_reg(padapter, 0xF0C, 0x3FFF);     /* [13:0] */
+		cckcrc	= phy_query_bb_reg(padapter, 0xF04, 0x3FFF0000); /* [29:16]	 */
+		ofdmcrc	= phy_query_bb_reg(padapter, 0xF14, 0x3FFF0000); /* [29:16] */
+		htcrc	= phy_query_bb_reg(padapter, 0xF10, 0x3FFF0000); /* [29:16] */
+		vht_err	= phy_query_bb_reg(padapter, 0xF0C, 0x3FFF0000); /* [29:16] */
+		CCK_FA	= phy_query_bb_reg(padapter, 0xA5C, bMaskLWord);
+		OFDM_FA	= phy_query_bb_reg(padapter, 0xF48, bMaskLWord);
+	} else {
+		cckok	= phy_query_bb_reg(padapter, 0xF88, bMaskDWord);
+		ofdmok	= phy_query_bb_reg(padapter, 0xF94, bMaskLWord);
+		htok		= phy_query_bb_reg(padapter, 0xF90, bMaskLWord);
+		vht_ok	= 0;
+		cckcrc	= phy_query_bb_reg(padapter, 0xF84, bMaskDWord);
+		ofdmcrc	= phy_query_bb_reg(padapter, 0xF94, bMaskHWord);
+		htcrc	= phy_query_bb_reg(padapter, 0xF90, bMaskHWord);
+		vht_err	= 0;
+		OFDM_FA = phy_query_bb_reg(padapter, 0xCF0, bMaskLWord) + phy_query_bb_reg(padapter, 0xCF2, bMaskLWord) +
+			phy_query_bb_reg(padapter, 0xDA2, bMaskLWord) + phy_query_bb_reg(padapter, 0xDA4, bMaskLWord) +
+			phy_query_bb_reg(padapter, 0xDA6, bMaskLWord) + phy_query_bb_reg(padapter, 0xDA8, bMaskLWord);
+
+		CCK_FA = (rtw_read8(padapter, 0xA5B) << 8) | (rtw_read8(padapter, 0xA5C));
+	}
+
+	rx_counter->rx_pkt_ok = cckok + ofdmok + htok + vht_ok;
+	rx_counter->rx_pkt_crc_error = cckcrc + ofdmcrc + htcrc + vht_err;
+	rx_counter->rx_ofdm_fa = OFDM_FA;
+	rx_counter->rx_cck_fa = CCK_FA;
+
+}
+
+void rtw_reset_phy_trx_ok_counters(_adapter *padapter)
+{
+	if (IS_HARDWARE_TYPE_JAGUAR(padapter) || IS_HARDWARE_TYPE_JAGUAR2(padapter)) {
+		phy_set_bb_reg(padapter, 0xB58, BIT0, 0x1);
+		phy_set_bb_reg(padapter, 0xB58, BIT0, 0x0);
+	}
+}
+void rtw_reset_phy_rx_counters(_adapter *padapter)
+{
+	/* reset phy counter */
+	if (IS_HARDWARE_TYPE_JAGUAR(padapter) || IS_HARDWARE_TYPE_JAGUAR2(padapter)) {
+		rtw_reset_phy_trx_ok_counters(padapter);
+
+		phy_set_bb_reg(padapter, 0x9A4, BIT17, 0x1);/* reset  OFDA FA counter */
+		phy_set_bb_reg(padapter, 0x9A4, BIT17, 0x0);
+
+		phy_set_bb_reg(padapter, 0xA2C, BIT15, 0x0);/* reset  CCK FA counter */
+		phy_set_bb_reg(padapter, 0xA2C, BIT15, 0x1);
+	} else {
+		phy_set_bb_reg(padapter, 0xF14, BIT16, 0x1);
+		rtw_msleep_os(10);
+		phy_set_bb_reg(padapter, 0xF14, BIT16, 0x0);
+
+		phy_set_bb_reg(padapter, 0xD00, BIT27, 0x1);/* reset  OFDA FA counter */
+		phy_set_bb_reg(padapter, 0xC0C, BIT31, 0x1);/* reset  OFDA FA counter */
+		phy_set_bb_reg(padapter, 0xD00, BIT27, 0x0);
+		phy_set_bb_reg(padapter, 0xC0C, BIT31, 0x0);
+
+		phy_set_bb_reg(padapter, 0xA2C, BIT15, 0x0);/* reset  CCK FA counter */
+		phy_set_bb_reg(padapter, 0xA2C, BIT15, 0x1);
+	}
+}
+#ifdef DBG_RX_COUNTER_DUMP
+void rtw_dump_drv_rx_counters(_adapter *padapter, struct dbg_rx_counter *rx_counter)
+{
+	struct recv_priv *precvpriv = &padapter->recvpriv;
+	if (!rx_counter) {
+		rtw_warn_on(1);
+		return;
+	}
+	rx_counter->rx_pkt_ok = padapter->drv_rx_cnt_ok;
+	rx_counter->rx_pkt_crc_error = padapter->drv_rx_cnt_crcerror;
+	rx_counter->rx_pkt_drop = precvpriv->rx_drop - padapter->drv_rx_cnt_drop;
+}
+void rtw_reset_drv_rx_counters(_adapter *padapter)
+{
+	struct recv_priv *precvpriv = &padapter->recvpriv;
+	padapter->drv_rx_cnt_ok = 0;
+	padapter->drv_rx_cnt_crcerror = 0;
+	padapter->drv_rx_cnt_drop = precvpriv->rx_drop;
+}
+void rtw_dump_phy_rxcnts_preprocess(_adapter *padapter, u8 rx_cnt_mode)
+{
+	u8 initialgain;
+	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(padapter);
+
+	if ((!(padapter->dump_rx_cnt_mode & DUMP_PHY_RX_COUNTER)) && (rx_cnt_mode & DUMP_PHY_RX_COUNTER)) {
+		rtw_hal_get_odm_var(padapter, HAL_ODM_INITIAL_GAIN, &initialgain, NULL);
+		RTW_INFO("%s CurIGValue:0x%02x\n", __FUNCTION__, initialgain);
+		rtw_hal_set_odm_var(padapter, HAL_ODM_INITIAL_GAIN, &initialgain, _FALSE);
+		/*disable dynamic functions, such as high power, DIG*/
+		rtw_phydm_ability_backup(padapter);
+		rtw_phydm_func_clr(padapter, (ODM_BB_DIG | ODM_BB_FA_CNT));
+	} else if ((padapter->dump_rx_cnt_mode & DUMP_PHY_RX_COUNTER) && (!(rx_cnt_mode & DUMP_PHY_RX_COUNTER))) {
+		/* turn on phy-dynamic functions */
+		rtw_phydm_ability_restore(padapter);
+		initialgain = 0xff; /* restore RX GAIN */
+		rtw_hal_set_odm_var(padapter, HAL_ODM_INITIAL_GAIN, &initialgain, _FALSE);
+
+	}
+}
+
+void rtw_dump_rx_counters(_adapter *padapter)
+{
+	struct dbg_rx_counter rx_counter;
+
+	if (padapter->dump_rx_cnt_mode & DUMP_DRV_RX_COUNTER) {
+		_rtw_memset(&rx_counter, 0, sizeof(struct dbg_rx_counter));
+		rtw_dump_drv_rx_counters(padapter, &rx_counter);
+		RTW_INFO("Drv Received packet OK:%d CRC error:%d Drop Packets: %d\n",
+			rx_counter.rx_pkt_ok, rx_counter.rx_pkt_crc_error, rx_counter.rx_pkt_drop);
+		rtw_reset_drv_rx_counters(padapter);
+	}
+
+	if (padapter->dump_rx_cnt_mode & DUMP_MAC_RX_COUNTER) {
+		_rtw_memset(&rx_counter, 0, sizeof(struct dbg_rx_counter));
+		rtw_dump_mac_rx_counters(padapter, &rx_counter);
+		RTW_INFO("Mac Received packet OK:%d CRC error:%d FA Counter: %d Drop Packets: %d\n",
+			 rx_counter.rx_pkt_ok, rx_counter.rx_pkt_crc_error,
+			rx_counter.rx_cck_fa + rx_counter.rx_ofdm_fa + rx_counter.rx_ht_fa,
+			 rx_counter.rx_pkt_drop);
+		rtw_reset_mac_rx_counters(padapter);
+	}
+
+	if (padapter->dump_rx_cnt_mode & DUMP_PHY_RX_COUNTER) {
+		_rtw_memset(&rx_counter, 0, sizeof(struct dbg_rx_counter));
+		rtw_dump_phy_rx_counters(padapter, &rx_counter);
+		/* RTW_INFO("%s: OFDM_FA =%d\n", __FUNCTION__, rx_counter.rx_ofdm_fa); */
+		/* RTW_INFO("%s: CCK_FA =%d\n", __FUNCTION__, rx_counter.rx_cck_fa); */
+		RTW_INFO("Phy Received packet OK:%d CRC error:%d FA Counter: %d\n", rx_counter.rx_pkt_ok, rx_counter.rx_pkt_crc_error,
+			 rx_counter.rx_ofdm_fa + rx_counter.rx_cck_fa);
+		rtw_reset_phy_rx_counters(padapter);
+	}
+}
+#endif
+u8 rtw_get_current_tx_sgi(_adapter *padapter, struct sta_info *psta)
+{
+	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(padapter);
+	u8 curr_tx_sgi = 0;
+	struct ra_sta_info *ra_info;
+
+	if (!psta)
+		return curr_tx_sgi;
+
+	if (padapter->fix_rate == 0xff) {
+#if defined(CONFIG_RTL8188E)
+#if (RATE_ADAPTIVE_SUPPORT == 1)
+		curr_tx_sgi = hal_data->odmpriv.ra_info[psta->cmn.mac_id].rate_sgi;
+#endif /* (RATE_ADAPTIVE_SUPPORT == 1)*/
+#else
+		ra_info = &psta->cmn.ra_info;
+		curr_tx_sgi = ((ra_info->curr_tx_rate) & 0x80) >> 7;
+#endif
+	} else {
+		curr_tx_sgi = ((padapter->fix_rate) & 0x80) >> 7;
+	}
+
+	return curr_tx_sgi;
+}
+
+u8 rtw_get_current_tx_rate(_adapter *padapter, struct sta_info *psta)
+{
+	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(padapter);
+	u8 rate_id = 0;
+	struct ra_sta_info *ra_info;
+
+	if (!psta)
+		return rate_id;
+
+	if (padapter->fix_rate == 0xff) {
+#if defined(CONFIG_RTL8188E)
+#if (RATE_ADAPTIVE_SUPPORT == 1)
+		rate_id = hal_data->odmpriv.ra_info[psta->cmn.mac_id].decision_rate;
+#endif /* (RATE_ADAPTIVE_SUPPORT == 1)*/
+#else
+		ra_info = &psta->cmn.ra_info;
+		rate_id = ra_info->curr_tx_rate & 0x7f;
+#endif
+	} else {
+		rate_id = padapter->fix_rate & 0x7f;
+	}
+
+	return rate_id;
+}
+
+void update_IOT_info(_adapter *padapter)
+{
+	struct mlme_ext_priv	*pmlmeext = &padapter->mlmeextpriv;
+	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
+
+	switch (pmlmeinfo->assoc_AP_vendor) {
+	case HT_IOT_PEER_MARVELL:
+		pmlmeinfo->turboMode_cts2self = 1;
+		pmlmeinfo->turboMode_rtsen = 0;
+		break;
+
+	case HT_IOT_PEER_RALINK:
+		pmlmeinfo->turboMode_cts2self = 0;
+		pmlmeinfo->turboMode_rtsen = 1;
+		break;
+	case HT_IOT_PEER_REALTEK:
+		/* rtw_write16(padapter, 0x4cc, 0xffff); */
+		/* rtw_write16(padapter, 0x546, 0x01c0); */
+		break;
+	default:
+		pmlmeinfo->turboMode_cts2self = 0;
+		pmlmeinfo->turboMode_rtsen = 1;
+		break;
+	}
+
+}
+
+/* TODO: merge with phydm, see odm_SetCrystalCap() */
+void hal_set_crystal_cap(_adapter *adapter, u8 crystal_cap)
+{
+	crystal_cap = crystal_cap & 0x3F;
+
+	switch (rtw_get_chip_type(adapter)) {
+#if defined(CONFIG_RTL8188E) || defined(CONFIG_RTL8188F) || defined(CONFIG_RTL8188GTV)
+	case RTL8188E:
+	case RTL8188F:
+	case RTL8188GTV:
+		/* write 0x24[16:11] = 0x24[22:17] = CrystalCap */
+		phy_set_bb_reg(adapter, REG_AFE_XTAL_CTRL, 0x007FF800, (crystal_cap | (crystal_cap << 6)));
+		break;
+#endif
+#if defined(CONFIG_RTL8812A)
+	case RTL8812:
+		/* write 0x2C[30:25] = 0x2C[24:19] = CrystalCap */
+		phy_set_bb_reg(adapter, REG_MAC_PHY_CTRL, 0x7FF80000, (crystal_cap | (crystal_cap << 6)));
+		break;
+#endif
+#if defined(CONFIG_RTL8723B) || defined(CONFIG_RTL8703B) || \
+		defined(CONFIG_RTL8723D) || defined(CONFIG_RTL8821A) || \
+		defined(CONFIG_RTL8192E) 
+	case RTL8723B:
+	case RTL8703B:
+	case RTL8723D:
+	case RTL8821:
+	case RTL8192E:
+		/* write 0x2C[23:18] = 0x2C[17:12] = CrystalCap */
+		phy_set_bb_reg(adapter, REG_MAC_PHY_CTRL, 0x00FFF000, (crystal_cap | (crystal_cap << 6)));
+		break;
+#endif
+#if defined(CONFIG_RTL8814A)
+	case RTL8814A:
+		/* write 0x2C[26:21] = 0x2C[20:15] = CrystalCap*/
+		phy_set_bb_reg(adapter, REG_MAC_PHY_CTRL, 0x07FF8000, (crystal_cap | (crystal_cap << 6)));
+		break;
+#endif
+#if defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C) || defined(CONFIG_RTL8192F)
+
+	case RTL8822B:
+	case RTL8821C:
+	case RTL8192F:	
+		/* write 0x28[6:1] = 0x24[30:25] = CrystalCap */
+		crystal_cap = crystal_cap & 0x3F;
+		phy_set_bb_reg(adapter, REG_AFE_XTAL_CTRL, 0x7E000000, crystal_cap);
+		phy_set_bb_reg(adapter, REG_AFE_PLL_CTRL, 0x7E, crystal_cap);
+		break;
+#endif
+#if defined(CONFIG_RTL8710B)
+	case RTL8710B:
+		/*Change by ylb 20160728, Becase 0x2C[23:12] is removed to syson 0x60[29:18] */
+		/* 0x2C[23:18] = 0x2C[29:24] = CrystalCap //Xo:[29:24], Xi:[23:18]*/
+		crystal_cap = crystal_cap & 0x3F;
+		hal_set_syson_reg(adapter, REG_SYS_XTAL_CTRL0, 0x3FFC0000, (crystal_cap | (crystal_cap << 6)));
+		break;
+#endif
+	default:
+		rtw_warn_on(1);
+	}
+}
+
+int hal_spec_init(_adapter *adapter)
+{
+	u8 interface_type = 0;
+	int ret = _SUCCESS;
+
+	interface_type = rtw_get_intf_type(adapter);
+
+	switch (rtw_get_chip_type(adapter)) {
+#ifdef CONFIG_RTL8723B
+	case RTL8723B:
+		init_hal_spec_8723b(adapter);
+		break;
+#endif
+#ifdef CONFIG_RTL8703B
+	case RTL8703B:
+		init_hal_spec_8703b(adapter);
+		break;
+#endif
+#ifdef CONFIG_RTL8723D
+	case RTL8723D:
+		init_hal_spec_8723d(adapter);
+		break;
+#endif
+#ifdef CONFIG_RTL8188E
+	case RTL8188E:
+		init_hal_spec_8188e(adapter);
+		break;
+#endif
+#ifdef CONFIG_RTL8188F
+	case RTL8188F:
+		init_hal_spec_8188f(adapter);
+		break;
+#endif
+#ifdef CONFIG_RTL8188GTV
+	case RTL8188GTV:
+		init_hal_spec_8188gtv(adapter);
+		break;
+#endif
+#ifdef CONFIG_RTL8812A
+	case RTL8812:
+		init_hal_spec_8812a(adapter);
+		break;
+#endif
+#ifdef CONFIG_RTL8821A
+	case RTL8821:
+		init_hal_spec_8821a(adapter);
+		break;
+#endif
+#ifdef CONFIG_RTL8192E
+	case RTL8192E:
+		init_hal_spec_8192e(adapter);
+		break;
+#endif
+#ifdef CONFIG_RTL8814A
+	case RTL8814A:
+		init_hal_spec_8814a(adapter);
+		break;
+#endif
+#ifdef CONFIG_RTL8822B
+	case RTL8822B:
+		rtl8822b_init_hal_spec(adapter);
+		break;
+#endif
+#ifdef CONFIG_RTL8821C
+	case RTL8821C:
+		init_hal_spec_rtl8821c(adapter);
+		break;
+#endif
+#ifdef CONFIG_RTL8710B
+	case RTL8710B:
+		init_hal_spec_8710b(adapter);
+		break;
+#endif
+#ifdef CONFIG_RTL8192F
+	case RTL8192F:
+		init_hal_spec_8192f(adapter);
+		break;
+#endif
+
+	default:
+		RTW_ERR("%s: unknown chip_type:%u\n"
+			, __func__, rtw_get_chip_type(adapter));
+		ret = _FAIL;
+		break;
+	}
+
+	return ret;
+}
+
+static const char *const _band_cap_str[] = {
+	/* BIT0 */"2G",
+	/* BIT1 */"5G",
+};
+
+static const char *const _bw_cap_str[] = {
+	/* BIT0 */"5M",
+	/* BIT1 */"10M",
+	/* BIT2 */"20M",
+	/* BIT3 */"40M",
+	/* BIT4 */"80M",
+	/* BIT5 */"160M",
+	/* BIT6 */"80_80M",
+};
+
+static const char *const _proto_cap_str[] = {
+	/* BIT0 */"b",
+	/* BIT1 */"g",
+	/* BIT2 */"n",
+	/* BIT3 */"ac",
+};
+
+static const char *const _wl_func_str[] = {
+	/* BIT0 */"P2P",
+	/* BIT1 */"MIRACAST",
+	/* BIT2 */"TDLS",
+	/* BIT3 */"FTM",
+};
+
+void dump_hal_spec(void *sel, _adapter *adapter)
+{
+	struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter);
+	int i;
+
+	RTW_PRINT_SEL(sel, "macid_num:%u\n", hal_spec->macid_num);
+	RTW_PRINT_SEL(sel, "sec_cap:0x%02x\n", hal_spec->sec_cap);
+	RTW_PRINT_SEL(sel, "sec_cam_ent_num:%u\n", hal_spec->sec_cam_ent_num);
+	RTW_PRINT_SEL(sel, "rfpath_num_2g:%u\n", hal_spec->rfpath_num_2g);
+	RTW_PRINT_SEL(sel, "rfpath_num_5g:%u\n", hal_spec->rfpath_num_5g);
+	RTW_PRINT_SEL(sel, "txgi_max:%u\n", hal_spec->txgi_max);
+	RTW_PRINT_SEL(sel, "txgi_pdbm:%u\n", hal_spec->txgi_pdbm);
+	RTW_PRINT_SEL(sel, "max_tx_cnt:%u\n", hal_spec->max_tx_cnt);
+	RTW_PRINT_SEL(sel, "tx_nss_num:%u\n", hal_spec->tx_nss_num);
+	RTW_PRINT_SEL(sel, "rx_nss_num:%u\n", hal_spec->rx_nss_num);
+
+	RTW_PRINT_SEL(sel, "band_cap:");
+	for (i = 0; i < BAND_CAP_BIT_NUM; i++) {
+		if (((hal_spec->band_cap) >> i) & BIT0 && _band_cap_str[i])
+			_RTW_PRINT_SEL(sel, "%s ", _band_cap_str[i]);
+	}
+	_RTW_PRINT_SEL(sel, "\n");
+
+	RTW_PRINT_SEL(sel, "bw_cap:");
+	for (i = 0; i < BW_CAP_BIT_NUM; i++) {
+		if (((hal_spec->bw_cap) >> i) & BIT0 && _bw_cap_str[i])
+			_RTW_PRINT_SEL(sel, "%s ", _bw_cap_str[i]);
+	}
+	_RTW_PRINT_SEL(sel, "\n");
+
+	RTW_PRINT_SEL(sel, "proto_cap:");
+	for (i = 0; i < PROTO_CAP_BIT_NUM; i++) {
+		if (((hal_spec->proto_cap) >> i) & BIT0 && _proto_cap_str[i])
+			_RTW_PRINT_SEL(sel, "%s ", _proto_cap_str[i]);
+	}
+	_RTW_PRINT_SEL(sel, "\n");
+
+	RTW_PRINT_SEL(sel, "wl_func:");
+	for (i = 0; i < WL_FUNC_BIT_NUM; i++) {
+		if (((hal_spec->wl_func) >> i) & BIT0 && _wl_func_str[i])
+			_RTW_PRINT_SEL(sel, "%s ", _wl_func_str[i]);
+	}
+	_RTW_PRINT_SEL(sel, "\n");
+
+	RTW_PRINT_SEL(sel, "rx_tsf_filter:%u\n", hal_spec->rx_tsf_filter);
+
+	RTW_PRINT_SEL(sel, "pg_txpwr_saddr:0x%X\n", hal_spec->pg_txpwr_saddr);
+	RTW_PRINT_SEL(sel, "pg_txgi_diff_factor:%u\n", hal_spec->pg_txgi_diff_factor);
+}
+
+inline bool hal_chk_band_cap(_adapter *adapter, u8 cap)
+{
+	return GET_HAL_SPEC(adapter)->band_cap & cap;
+}
+
+inline bool hal_chk_bw_cap(_adapter *adapter, u8 cap)
+{
+	return GET_HAL_SPEC(adapter)->bw_cap & cap;
+}
+
+inline bool hal_chk_proto_cap(_adapter *adapter, u8 cap)
+{
+	return GET_HAL_SPEC(adapter)->proto_cap & cap;
+}
+
+inline bool hal_chk_wl_func(_adapter *adapter, u8 func)
+{
+	return GET_HAL_SPEC(adapter)->wl_func & func;
+}
+
+inline bool hal_is_band_support(_adapter *adapter, u8 band)
+{
+	return GET_HAL_SPEC(adapter)->band_cap & band_to_band_cap(band);
+}
+
+inline bool hal_is_bw_support(_adapter *adapter, u8 bw)
+{
+	return GET_HAL_SPEC(adapter)->bw_cap & ch_width_to_bw_cap(bw);
+}
+
+inline bool hal_is_wireless_mode_support(_adapter *adapter, u8 mode)
+{
+	u8 proto_cap = GET_HAL_SPEC(adapter)->proto_cap;
+
+	if (mode == WIRELESS_11B)
+		if ((proto_cap & PROTO_CAP_11B) && hal_chk_band_cap(adapter, BAND_CAP_2G))
+			return 1;
+
+	if (mode == WIRELESS_11G)
+		if ((proto_cap & PROTO_CAP_11G) && hal_chk_band_cap(adapter, BAND_CAP_2G))
+			return 1;
+
+	if (mode == WIRELESS_11A)
+		if ((proto_cap & PROTO_CAP_11G) && hal_chk_band_cap(adapter, BAND_CAP_5G))
+			return 1;
+
+	if (mode == WIRELESS_11_24N)
+		if ((proto_cap & PROTO_CAP_11N) && hal_chk_band_cap(adapter, BAND_CAP_2G))
+			return 1;
+
+	if (mode == WIRELESS_11_5N)
+		if ((proto_cap & PROTO_CAP_11N) && hal_chk_band_cap(adapter, BAND_CAP_5G))
+			return 1;
+
+	if (mode == WIRELESS_11AC)
+		if ((proto_cap & PROTO_CAP_11AC) && hal_chk_band_cap(adapter, BAND_CAP_5G))
+			return 1;
+
+	return 0;
+}
+
+/*
+* hal_largest_bw - starting from in_bw, get largest bw supported by HAL
+* @adapter:
+* @in_bw: starting bw, value of enum channel_width
+*
+* Returns: value of enum channel_width
+*/
+u8 hal_largest_bw(_adapter *adapter, u8 in_bw)
+{
+	for (; in_bw > CHANNEL_WIDTH_20; in_bw--) {
+		if (hal_is_bw_support(adapter, in_bw))
+			break;
+	}
+
+	if (!hal_is_bw_support(adapter, in_bw))
+		rtw_warn_on(1);
+
+	return in_bw;
+}
+
+void ResumeTxBeacon(_adapter *padapter)
+{
+	rtw_write8(padapter, REG_FWHW_TXQ_CTRL + 2,
+		rtw_read8(padapter, REG_FWHW_TXQ_CTRL + 2) | BIT(6));
+
+#ifdef RTW_HALMAC
+	/* Add this for driver using HALMAC because driver doesn't have setup time init by self */
+	/* TBTT setup time */
+	rtw_write8(padapter, REG_TBTT_PROHIBIT, TBTT_PROHIBIT_SETUP_TIME);
+#endif
+
+	/* TBTT hold time: 0x540[19:8] */
+	rtw_write8(padapter, REG_TBTT_PROHIBIT + 1, TBTT_PROHIBIT_HOLD_TIME & 0xFF);
+	rtw_write8(padapter, REG_TBTT_PROHIBIT + 2,
+		(rtw_read8(padapter, REG_TBTT_PROHIBIT + 2) & 0xF0) | (TBTT_PROHIBIT_HOLD_TIME >> 8));
+}
+
+void StopTxBeacon(_adapter *padapter)
+{
+	rtw_write8(padapter, REG_FWHW_TXQ_CTRL + 2,
+		rtw_read8(padapter, REG_FWHW_TXQ_CTRL + 2) & (~BIT6));
+
+	/* TBTT hold time: 0x540[19:8] */
+	rtw_write8(padapter, REG_TBTT_PROHIBIT + 1, TBTT_PROHIBIT_HOLD_TIME_STOP_BCN & 0xFF);
+	rtw_write8(padapter, REG_TBTT_PROHIBIT + 2,
+		(rtw_read8(padapter, REG_TBTT_PROHIBIT + 2) & 0xF0) | (TBTT_PROHIBIT_HOLD_TIME_STOP_BCN >> 8));
+}
+
+#ifdef CONFIG_MI_WITH_MBSSID_CAM /*HW port0 - MBSS*/
+
+#ifdef CONFIG_CLIENT_PORT_CFG
+const u8 _clt_port_id[MAX_CLIENT_PORT_NUM] = {
+	CLT_PORT0,
+	CLT_PORT1,
+	CLT_PORT2,
+	CLT_PORT3
+};
+
+void rtw_clt_port_init(struct clt_port_t  *cltp)
+{
+	cltp->bmp = 0;
+	cltp->num = 0;
+	_rtw_spinlock_init(&cltp->lock);
+}
+void rtw_clt_port_deinit(struct clt_port_t *cltp)
+{
+	_rtw_spinlock_free(&cltp->lock);
+}
+static void _hw_client_port_alloc(_adapter *adapter)
+{
+	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
+	struct clt_port_t  *cltp = &dvobj->clt_port;
+	_irqL irql;
+	int i;
+
+	#if 0
+	if (cltp->num > MAX_CLIENT_PORT_NUM) {
+		RTW_ERR(ADPT_FMT" cann't  alloc client (%d)\n", ADPT_ARG(adapter), cltp->num);
+		rtw_warn_on(1);
+		return;
+	}
+	#endif
+
+	if (adapter->client_id !=  MAX_CLIENT_PORT_NUM) {
+		RTW_INFO(ADPT_FMT" client_id %d has allocated port:%d\n",
+			ADPT_ARG(adapter), adapter->client_id, adapter->client_port);
+		return;
+	}
+	_enter_critical_bh(&cltp->lock, &irql);
+	for (i = 0; i < MAX_CLIENT_PORT_NUM; i++) {
+		if (!(cltp->bmp & BIT(i)))
+			break;
+	}
+
+	if (i < MAX_CLIENT_PORT_NUM) {
+		adapter->client_id = i;
+		cltp->bmp |= BIT(i);
+		adapter->client_port = _clt_port_id[i];
+	}
+	cltp->num++;
+	_exit_critical_bh(&cltp->lock, &irql);
+	RTW_INFO("%s("ADPT_FMT")id:%d, port:%d clt_num:%d\n",
+		__func__, ADPT_ARG(adapter), adapter->client_id, adapter->client_port, cltp->num);
+}
+static void _hw_client_port_free(_adapter *adapter)
+{
+	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
+	struct clt_port_t  *cltp = &dvobj->clt_port;
+	_irqL irql;
+
+	#if 0
+	if (adapter->client_id >=  MAX_CLIENT_PORT_NUM) {
+		RTW_ERR(ADPT_FMT" client_id %d is invalid\n", ADPT_ARG(adapter), adapter->client_id);
+		/*rtw_warn_on(1);*/
+	}
+	#endif
+
+	RTW_INFO("%s ("ADPT_FMT") id:%d, port:%d clt_num:%d\n",
+		__func__, ADPT_ARG(adapter), adapter->client_id, adapter->client_port, cltp->num);
+
+	_enter_critical_bh(&cltp->lock, &irql);
+	if (adapter->client_id !=  MAX_CLIENT_PORT_NUM) {
+		cltp->bmp &= ~ BIT(adapter->client_id);
+		adapter->client_id = MAX_CLIENT_PORT_NUM;
+		adapter->client_port = CLT_PORT_INVALID;
+	}
+	cltp->num--;
+	if (cltp->num < 0)
+		cltp->num = 0;
+	_exit_critical_bh(&cltp->lock, &irql);
+}
+void rtw_hw_client_port_allocate(_adapter *adapter)
+{
+	struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter);
+
+	if (hal_spec->port_num != 5)
+		return;
+
+	_hw_client_port_alloc(adapter);
+}
+void rtw_hw_client_port_release(_adapter *adapter)
+{
+	struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter);
+
+	if (hal_spec->port_num != 5)
+		return;
+
+	_hw_client_port_free(adapter);
+}
+#endif /*CONFIG_CLIENT_PORT_CFG*/
+
+void hw_var_set_opmode_mbid(_adapter *Adapter, u8 mode)
+{
+	RTW_INFO("%s()-"ADPT_FMT" mode = %d\n", __func__, ADPT_ARG(Adapter), mode);
+
+	rtw_hal_rcr_set_chk_bssid(Adapter, MLME_ACTION_NONE);
+
+	/* set net_type */
+	Set_MSR(Adapter, mode);
+
+	if ((mode == _HW_STATE_STATION_) || (mode == _HW_STATE_NOLINK_)) {
+		if (!rtw_mi_get_ap_num(Adapter) && !rtw_mi_get_mesh_num(Adapter))
+			StopTxBeacon(Adapter);
+	} else if (mode == _HW_STATE_ADHOC_)
+		ResumeTxBeacon(Adapter);
+	else if (mode == _HW_STATE_AP_)
+		/* enable rx ps-poll */
+		rtw_write16(Adapter, REG_RXFLTMAP1, rtw_read16(Adapter, REG_RXFLTMAP1) | BIT_CTRLFLT10EN);
+
+	/* enable rx data frame */
+	rtw_write16(Adapter, REG_RXFLTMAP2, 0xFFFF);
+
+#ifdef CONFIG_CLIENT_PORT_CFG
+	if (mode == _HW_STATE_STATION_)
+		rtw_hw_client_port_allocate(Adapter);
+	else
+		rtw_hw_client_port_release(Adapter);
+#endif
+#if defined(CONFIG_RTL8192F)
+		rtw_write16(Adapter, REG_WLAN_ACT_MASK_CTRL_1, rtw_read16(Adapter, 
+					REG_WLAN_ACT_MASK_CTRL_1) | EN_PORT_0_FUNCTION);	
+#endif
+}
+#endif
+
+#ifdef CONFIG_ANTENNA_DIVERSITY
+u8	rtw_hal_antdiv_before_linked(_adapter *padapter)
+{
+	HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
+	u8 cur_ant, change_ant;
+
+	if (!pHalData->AntDivCfg)
+		return _FALSE;
+
+	if (pHalData->sw_antdiv_bl_state == 0) {
+		pHalData->sw_antdiv_bl_state = 1;
+
+		rtw_hal_get_odm_var(padapter, HAL_ODM_ANTDIV_SELECT, &cur_ant, NULL);
+		change_ant = (cur_ant == MAIN_ANT) ? AUX_ANT : MAIN_ANT;
+
+		return rtw_antenna_select_cmd(padapter, change_ant, _FALSE);
+	}
+
+	pHalData->sw_antdiv_bl_state = 0;
+	return _FALSE;
+}
+
+void	rtw_hal_antdiv_rssi_compared(_adapter *padapter, WLAN_BSSID_EX *dst, WLAN_BSSID_EX *src)
+{
+	HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
+
+	if (pHalData->AntDivCfg) {
+		/*RTW_INFO("update_network=> org-RSSI(%d), new-RSSI(%d)\n", dst->Rssi, src->Rssi);*/
+		/*select optimum_antenna for before linked =>For antenna diversity*/
+		if (dst->Rssi >=  src->Rssi) {/*keep org parameter*/
+			src->Rssi = dst->Rssi;
+			src->PhyInfo.Optimum_antenna = dst->PhyInfo.Optimum_antenna;
+		}
+	}
+}
+#endif
+
+#ifdef CONFIG_PHY_CAPABILITY_QUERY
+void rtw_dump_phy_cap_by_phydmapi(void *sel, _adapter *adapter)
+{
+	HAL_DATA_TYPE *pHalData = GET_HAL_DATA(adapter);
+	struct phy_spec_t *phy_spec = &pHalData->phy_spec;
+
+	RTW_PRINT_SEL(sel, "[PHY SPEC] TRx Capability : 0x%08x\n", phy_spec->trx_cap);
+	RTW_PRINT_SEL(sel, "[PHY SPEC] Tx Stream Num Index : %d\n", (phy_spec->trx_cap >> 24) & 0xFF); /*Tx Stream Num Index [31:24]*/
+	RTW_PRINT_SEL(sel, "[PHY SPEC] Rx Stream Num Index : %d\n", (phy_spec->trx_cap >> 16) & 0xFF); /*Rx Stream Num Index [23:16]*/
+	RTW_PRINT_SEL(sel, "[PHY SPEC] Tx Path Num Index : %d\n", (phy_spec->trx_cap >> 8) & 0xFF);/*Tx Path Num Index	[15:8]*/
+	RTW_PRINT_SEL(sel, "[PHY SPEC] Rx Path Num Index : %d\n\n", (phy_spec->trx_cap & 0xFF));/*Rx Path Num Index	[7:0]*/
+
+	RTW_PRINT_SEL(sel, "[PHY SPEC] STBC Capability : 0x%08x\n", phy_spec->stbc_cap);
+	RTW_PRINT_SEL(sel, "[PHY SPEC] VHT STBC Tx : %s\n", ((phy_spec->stbc_cap >> 24) & 0xFF) ? "Supported" : "N/A"); /*VHT STBC Tx [31:24]*/
+	/*VHT STBC Rx [23:16]
+	0 = not support
+	1 = support for 1 spatial stream
+	2 = support for 1 or 2 spatial streams
+	3 = support for 1 or 2 or 3 spatial streams
+	4 = support for 1 or 2 or 3 or 4 spatial streams*/
+	RTW_PRINT_SEL(sel, "[PHY SPEC] VHT STBC Rx :%d\n", ((phy_spec->stbc_cap >> 16) & 0xFF));
+	RTW_PRINT_SEL(sel, "[PHY SPEC] HT STBC Tx : %s\n", ((phy_spec->stbc_cap >> 8) & 0xFF) ? "Supported" : "N/A"); /*HT STBC Tx [15:8]*/
+	/*HT STBC Rx [7:0]
+	0 = not support
+	1 = support for 1 spatial stream
+	2 = support for 1 or 2 spatial streams
+	3 = support for 1 or 2 or 3 spatial streams*/
+	RTW_PRINT_SEL(sel, "[PHY SPEC] HT STBC Rx : %d\n\n", (phy_spec->stbc_cap & 0xFF));
+
+	RTW_PRINT_SEL(sel, "[PHY SPEC] LDPC Capability : 0x%08x\n", phy_spec->ldpc_cap);
+	RTW_PRINT_SEL(sel, "[PHY SPEC] VHT LDPC Tx : %s\n", ((phy_spec->ldpc_cap >> 24) & 0xFF) ? "Supported" : "N/A"); /*VHT LDPC Tx [31:24]*/
+	RTW_PRINT_SEL(sel, "[PHY SPEC] VHT LDPC Rx : %s\n", ((phy_spec->ldpc_cap >> 16) & 0xFF) ? "Supported" : "N/A"); /*VHT LDPC Rx [23:16]*/
+	RTW_PRINT_SEL(sel, "[PHY SPEC] HT LDPC Tx : %s\n", ((phy_spec->ldpc_cap >> 8) & 0xFF) ? "Supported" : "N/A"); /*HT LDPC Tx [15:8]*/
+	RTW_PRINT_SEL(sel, "[PHY SPEC] HT LDPC Rx : %s\n\n", (phy_spec->ldpc_cap & 0xFF) ? "Supported" : "N/A"); /*HT LDPC Rx [7:0]*/
+	#ifdef CONFIG_BEAMFORMING
+	RTW_PRINT_SEL(sel, "[PHY SPEC] TxBF Capability : 0x%08x\n", phy_spec->txbf_cap);
+	RTW_PRINT_SEL(sel, "[PHY SPEC] VHT MU Bfer : %s\n", ((phy_spec->txbf_cap >> 28) & 0xF) ? "Supported" : "N/A"); /*VHT MU Bfer [31:28]*/
+	RTW_PRINT_SEL(sel, "[PHY SPEC] VHT MU Bfee : %s\n", ((phy_spec->txbf_cap >> 24) & 0xF) ? "Supported" : "N/A"); /*VHT MU Bfee [27:24]*/
+	RTW_PRINT_SEL(sel, "[PHY SPEC] VHT SU Bfer : %s\n", ((phy_spec->txbf_cap >> 20) & 0xF) ? "Supported" : "N/A"); /*VHT SU Bfer [23:20]*/
+	RTW_PRINT_SEL(sel, "[PHY SPEC] VHT SU Bfee : %s\n", ((phy_spec->txbf_cap >> 16) & 0xF) ? "Supported" : "N/A"); /*VHT SU Bfee [19:16]*/
+	RTW_PRINT_SEL(sel, "[PHY SPEC] HT Bfer : %s\n", ((phy_spec->txbf_cap >> 4) & 0xF)  ? "Supported" : "N/A"); /*HT Bfer [7:4]*/
+	RTW_PRINT_SEL(sel, "[PHY SPEC] HT Bfee : %s\n\n", (phy_spec->txbf_cap & 0xF) ? "Supported" : "N/A"); /*HT Bfee [3:0]*/
+
+	RTW_PRINT_SEL(sel, "[PHY SPEC] TxBF parameter : 0x%08x\n", phy_spec->txbf_param);
+	RTW_PRINT_SEL(sel, "[PHY SPEC] VHT Sounding Dim : %d\n", (phy_spec->txbf_param >> 24) & 0xFF); /*VHT Sounding Dim [31:24]*/
+	RTW_PRINT_SEL(sel, "[PHY SPEC] VHT Steering Ant : %d\n", (phy_spec->txbf_param >> 16) & 0xFF); /*VHT Steering Ant [23:16]*/
+	RTW_PRINT_SEL(sel, "[PHY SPEC] HT Sounding Dim : %d\n", (phy_spec->txbf_param >> 8) & 0xFF); /*HT Sounding Dim [15:8]*/
+	RTW_PRINT_SEL(sel, "[PHY SPEC] HT Steering Ant : %d\n", phy_spec->txbf_param & 0xFF); /*HT Steering Ant [7:0]*/
+	#endif
+}
+#else
+void rtw_dump_phy_cap_by_hal(void *sel, _adapter *adapter)
+{
+	u8 phy_cap = _FALSE;
+
+	/* STBC */
+	rtw_hal_get_def_var(adapter, HAL_DEF_TX_STBC, (u8 *)&phy_cap);
+	RTW_PRINT_SEL(sel, "[HAL] STBC Tx : %s\n", (_TRUE == phy_cap) ? "Supported" : "N/A");
+
+	phy_cap = _FALSE;
+	rtw_hal_get_def_var(adapter, HAL_DEF_RX_STBC, (u8 *)&phy_cap);
+	RTW_PRINT_SEL(sel, "[HAL] STBC Rx : %s\n\n", (_TRUE == phy_cap) ? "Supported" : "N/A");
+
+	/* LDPC support */
+	phy_cap = _FALSE;
+	rtw_hal_get_def_var(adapter, HAL_DEF_TX_LDPC, (u8 *)&phy_cap);
+	RTW_PRINT_SEL(sel, "[HAL] LDPC Tx : %s\n", (_TRUE == phy_cap) ? "Supported" : "N/A");
+
+	phy_cap = _FALSE;
+	rtw_hal_get_def_var(adapter, HAL_DEF_RX_LDPC, (u8 *)&phy_cap);
+	RTW_PRINT_SEL(sel, "[HAL] LDPC Rx : %s\n\n", (_TRUE == phy_cap) ? "Supported" : "N/A");
+	
+	#ifdef CONFIG_BEAMFORMING
+	phy_cap = _FALSE;
+	rtw_hal_get_def_var(adapter, HAL_DEF_EXPLICIT_BEAMFORMER, (u8 *)&phy_cap);
+	RTW_PRINT_SEL(sel, "[HAL] Beamformer: %s\n", (_TRUE == phy_cap) ? "Supported" : "N/A");
+
+	phy_cap = _FALSE;
+	rtw_hal_get_def_var(adapter, HAL_DEF_EXPLICIT_BEAMFORMEE, (u8 *)&phy_cap);
+	RTW_PRINT_SEL(sel, "[HAL] Beamformee: %s\n", (_TRUE == phy_cap) ? "Supported" : "N/A");
+
+	phy_cap = _FALSE;
+	rtw_hal_get_def_var(adapter, HAL_DEF_VHT_MU_BEAMFORMER, &phy_cap);
+	RTW_PRINT_SEL(sel, "[HAL] VHT MU Beamformer: %s\n", (_TRUE == phy_cap) ? "Supported" : "N/A");
+
+	phy_cap = _FALSE;
+	rtw_hal_get_def_var(adapter, HAL_DEF_VHT_MU_BEAMFORMEE, &phy_cap);
+	RTW_PRINT_SEL(sel, "[HAL] VHT MU Beamformee: %s\n", (_TRUE == phy_cap) ? "Supported" : "N/A");
+	#endif
+}
+#endif
+void rtw_dump_phy_cap(void *sel, _adapter *adapter)
+{
+	RTW_PRINT_SEL(sel, "\n ======== PHY Capability ========\n");
+#ifdef CONFIG_PHY_CAPABILITY_QUERY
+	rtw_dump_phy_cap_by_phydmapi(sel, adapter);
+#else
+	rtw_dump_phy_cap_by_hal(sel, adapter);
+#endif
+}
+
+inline s16 translate_dbm_to_percentage(s16 signal)
+{
+	if ((signal <= -100) || (signal >= 20))
+		return	0;
+	else if (signal >= 0)
+		return	100;
+	else
+		return 100 + signal;
+}
+
+#ifdef CONFIG_SWTIMER_BASED_TXBCN
+#ifdef CONFIG_BCN_RECOVERY
+#define REG_CPU_MGQ_INFO	0x041C
+#define BIT_BCN_POLL			BIT(28)
+u8 rtw_ap_bcn_recovery(_adapter *padapter)
+{
+	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(padapter);
+
+	if (hal_data->issue_bcn_fail >= 2) {
+		RTW_ERR("%s ISSUE BCN Fail\n", __func__);
+		rtw_write8(padapter, REG_CPU_MGQ_INFO + 3, 0x10);
+		hal_data->issue_bcn_fail = 0;
+	}
+	return _SUCCESS;
+}
+#endif /*CONFIG_BCN_RECOVERY*/
+
+#ifdef CONFIG_BCN_XMIT_PROTECT
+u8 rtw_ap_bcn_queue_empty_check(_adapter *padapter, u32 txbcn_timer_ms)
+{
+	u32 start_time = rtw_get_current_time();
+	u8 bcn_queue_empty = _FALSE;
+
+	do {
+		if (rtw_read16(padapter, REG_TXPKT_EMPTY) & BIT(11)) {
+			bcn_queue_empty = _TRUE;
+			break;
+		}
+	} while (rtw_get_passing_time_ms(start_time) <= (txbcn_timer_ms + 10));
+
+	if (bcn_queue_empty == _FALSE)
+		RTW_ERR("%s BCN queue not empty\n", __func__);
+
+	return bcn_queue_empty;
+}
+#endif /*CONFIG_BCN_XMIT_PROTECT*/
+#endif /*CONFIG_SWTIMER_BASED_TXBCN*/
+
+static void _rf_type_to_ant_path(enum rf_type rf, enum bb_path *tx,
+				 enum bb_path *rx)
+{
+	if (tx) {
+		switch (rf) {
+		case RF_1T1R:
+		case RF_1T2R:
+			*tx = BB_PATH_A;
+			break;
+		case RF_2T2R:
+		case RF_2T3R:
+		case RF_2T4R:
+			*tx = BB_PATH_AB;
+			break;
+		case RF_3T3R:
+		case RF_3T4R:
+			*tx = BB_PATH_ABC;
+			break;
+		case RF_4T4R:
+		default:
+			*tx = BB_PATH_ABCD;
+			break;
+		}
+	}
+
+	if (rx) {
+		switch (rf) {
+		case RF_1T1R:
+			*rx = BB_PATH_A;
+			break;
+		case RF_1T2R:
+		case RF_2T2R:
+			*rx = BB_PATH_AB;
+			break;
+		case RF_2T3R:
+		case RF_3T3R:
+			*rx = BB_PATH_ABC;
+			break;
+		case RF_2T4R:
+		case RF_3T4R:
+		case RF_4T4R:
+		default:
+			*rx = BB_PATH_ABCD;
+			break;
+		}
+	}
+}
+
+/**
+ * rtw_hal_get_rf_path() - Get RF path related information
+ * @d:		struct dvobj_priv*
+ * @type:	RF type, nTnR
+ * @tx:		Tx path
+ * @rx:		Rx path
+ *
+ * Get RF type, TX path and RX path information.
+ */
+void rtw_hal_get_rf_path(struct dvobj_priv *d, enum rf_type *type,
+			 enum bb_path *tx, enum bb_path *rx)
+{
+	struct _ADAPTER *a;
+	u8 val8 = RF_1T1R;
+	enum rf_type rf;
+
+
+	a = dvobj_get_primary_adapter(d);
+
+	rtw_hal_get_hwreg(a, HW_VAR_RF_TYPE, &val8);
+	rf = (enum rf_type)val8;
+	if (type)
+		*type = rf;
+
+	if (tx || rx)
+		_rf_type_to_ant_path(rf, tx, rx);
+}
+
+#ifdef RTW_CHANNEL_SWITCH_OFFLOAD
+void rtw_hal_switch_chnl_and_set_bw_offload(_adapter *adapter, u8 central_ch, u8 pri_ch_idx, u8 bw)
+{
+	u8 h2c[H2C_SINGLE_CHANNELSWITCH_V2_LEN] = {0};
+	PHAL_DATA_TYPE hal;
+	struct submit_ctx *chsw_sctx;
+
+	hal = GET_HAL_DATA(adapter);
+	chsw_sctx = &hal->chsw_sctx;
+
+	SET_H2CCMD_SINGLE_CH_SWITCH_V2_CENTRAL_CH_NUM(h2c, central_ch);
+	SET_H2CCMD_SINGLE_CH_SWITCH_V2_PRIMARY_CH_IDX(h2c, pri_ch_idx);
+	SET_H2CCMD_SINGLE_CH_SWITCH_V2_BW(h2c, bw);
+
+	rtw_sctx_init(chsw_sctx, 10);
+	rtw_hal_fill_h2c_cmd(adapter, H2C_SINGLE_CHANNELSWITCH_V2, H2C_SINGLE_CHANNELSWITCH_V2_LEN, h2c);
+	rtw_sctx_wait(chsw_sctx, __func__);
+}
+#endif /* RTW_CHANNEL_SWITCH_OFFLOAD */
+
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/hal_com_c2h.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/hal_com_c2h.h
--- linux-5.6.3/3rdparty/rtl8821ce/hal/hal_com_c2h.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/hal_com_c2h.h	2020-04-10 16:35:06.788658760 +0300
@@ -0,0 +1,123 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#ifndef __COMMON_C2H_H__
+#define __COMMON_C2H_H__
+
+#define C2H_TYPE_REG 0
+#define C2H_TYPE_PKT 1
+
+/* 
+* C2H event format:
+* Fields    TRIGGER    PAYLOAD    SEQ    PLEN    ID
+* BITS     [127:120]    [119:16]   [15:8]  [7:4]  [3:0]
+*/
+#define C2H_ID(_c2h)		LE_BITS_TO_1BYTE(((u8*)(_c2h)), 0, 4)
+#define C2H_PLEN(_c2h)		LE_BITS_TO_1BYTE(((u8*)(_c2h)), 4, 4)
+#define C2H_SEQ(_c2h)		LE_BITS_TO_1BYTE(((u8*)(_c2h)) + 1, 0, 8)
+#define C2H_PAYLOAD(_c2h)	(((u8*)(_c2h)) + 2)
+
+#define SET_C2H_ID(_c2h, _val)		SET_BITS_TO_LE_1BYTE(((u8*)(_c2h)), 0, 4, _val)
+#define SET_C2H_PLEN(_c2h, _val)	SET_BITS_TO_LE_1BYTE(((u8*)(_c2h)), 4, 4, _val)
+#define SET_C2H_SEQ(_c2h, _val)		SET_BITS_TO_LE_1BYTE(((u8*)(_c2h)) + 1 , 0, 8, _val)
+
+/* 
+* C2H event format:
+* Fields    TRIGGER     PLEN      PAYLOAD    SEQ      ID
+* BITS    [127:120]  [119:112]  [111:16]   [15:8]   [7:0]
+*/
+#define C2H_ID_88XX(_c2h)		LE_BITS_TO_1BYTE(((u8*)(_c2h)), 0, 8)
+#define C2H_SEQ_88XX(_c2h)		LE_BITS_TO_1BYTE(((u8*)(_c2h)) + 1, 0, 8)
+#define C2H_PAYLOAD_88XX(_c2h)	(((u8*)(_c2h)) + 2)
+#define C2H_PLEN_88XX(_c2h)		LE_BITS_TO_1BYTE(((u8*)(_c2h)) + 14, 0, 8)
+#define C2H_TRIGGER_88XX(_c2h)	LE_BITS_TO_1BYTE(((u8*)(_c2h)) + 15, 0, 8)
+
+#define SET_C2H_ID_88XX(_c2h, _val)		SET_BITS_TO_LE_1BYTE(((u8*)(_c2h)), 0, 8, _val)
+#define SET_C2H_SEQ_88XX(_c2h, _val)	SET_BITS_TO_LE_1BYTE(((u8*)(_c2h)) + 1, 0, 8, _val)
+#define SET_C2H_PLEN_88XX(_c2h, _val)	SET_BITS_TO_LE_1BYTE(((u8*)(_c2h)) + 14, 0, 8, _val)
+
+typedef enum _C2H_EVT {
+	C2H_DBG = 0x00,
+	C2H_LB = 0x01,
+	C2H_TXBF = 0x02,
+	C2H_CCX_TX_RPT = 0x03,
+	C2H_AP_REQ_TXRPT = 0x04,
+	C2H_FW_SCAN_COMPLETE = 0x7,
+	C2H_BT_INFO = 0x09,
+	C2H_BT_MP_INFO = 0x0B,
+	C2H_RA_RPT = 0x0C,
+	C2H_SPC_STAT = 0x0D,
+	C2H_RA_PARA_RPT = 0x0E,
+	C2H_FW_CHNL_SWITCH_COMPLETE = 0x10,
+	C2H_IQK_FINISH = 0x11,
+	C2H_MAILBOX_STATUS = 0x15,
+	C2H_P2P_RPORT = 0x16,
+	C2H_MCC = 0x17,
+	C2H_MAC_HIDDEN_RPT = 0x19,
+	C2H_MAC_HIDDEN_RPT_2 = 0x1A,
+	C2H_BCN_EARLY_RPT = 0x1E,
+	C2H_DEFEATURE_DBG = 0x22,
+	C2H_CUSTOMER_STR_RPT = 0x24,
+	C2H_CUSTOMER_STR_RPT_2 = 0x25,
+	C2H_WLAN_INFO = 0x27,
+#ifdef RTW_PER_CMD_SUPPORT_FW
+	C2H_PER_RATE_RPT = 0x2c,
+#endif
+	C2H_DEFEATURE_RSVD = 0xFD,
+	C2H_EXTEND = 0xff,
+} C2H_EVT;
+
+typedef enum _EXTEND_C2H_EVT {
+	EXTEND_C2H_DBG_PRINT = 0
+} EXTEND_C2H_EVT;
+
+#define C2H_REG_LEN 16
+
+/* C2H_IQK_FINISH, 0x11 */
+#define IQK_OFFLOAD_LEN 1
+void c2h_iqk_offload(_adapter *adapter, u8 *data, u8 len);
+int	c2h_iqk_offload_wait(_adapter *adapter, u32 timeout_ms);
+#define rtl8812_iqk_wait c2h_iqk_offload_wait /* TODO: remove this after phydm call c2h_iqk_offload_wait instead */
+
+#ifdef CONFIG_RTW_MAC_HIDDEN_RPT
+/* C2H_MAC_HIDDEN_RPT, 0x19 */
+#define MAC_HIDDEN_RPT_LEN 8
+int c2h_mac_hidden_rpt_hdl(_adapter *adapter, u8 *data, u8 len);
+
+/* C2H_MAC_HIDDEN_RPT_2, 0x1A */
+#define MAC_HIDDEN_RPT_2_LEN 5
+int c2h_mac_hidden_rpt_2_hdl(_adapter *adapter, u8 *data, u8 len);
+int hal_read_mac_hidden_rpt(_adapter *adapter);
+#endif /* CONFIG_RTW_MAC_HIDDEN_RPT */
+
+/* C2H_DEFEATURE_DBG, 0x22 */
+#define DEFEATURE_DBG_LEN 1
+int c2h_defeature_dbg_hdl(_adapter *adapter, u8 *data, u8 len);
+
+#ifdef CONFIG_RTW_CUSTOMER_STR
+/* C2H_CUSTOMER_STR_RPT, 0x24 */
+#define CUSTOMER_STR_RPT_LEN 8
+int c2h_customer_str_rpt_hdl(_adapter *adapter, u8 *data, u8 len);
+
+/* C2H_CUSTOMER_STR_RPT_2, 0x25 */
+#define CUSTOMER_STR_RPT_2_LEN 8
+int c2h_customer_str_rpt_2_hdl(_adapter *adapter, u8 *data, u8 len);
+#endif /* CONFIG_RTW_CUSTOMER_STR */
+
+#ifdef RTW_PER_CMD_SUPPORT_FW
+/* C2H_PER_RATE_RPT, 0x2c */
+int c2h_per_rate_rpt_hdl(_adapter *adapter, u8 *data, u8 len);
+#endif
+
+#endif /* __COMMON_C2H_H__ */
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/hal_com_phycfg.c linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/hal_com_phycfg.c
--- linux-5.6.3/3rdparty/rtl8821ce/hal/hal_com_phycfg.c	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/hal_com_phycfg.c	2020-04-10 16:35:06.789658807 +0300
@@ -0,0 +1,5407 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#define _HAL_COM_PHYCFG_C_
+
+#include <drv_types.h>
+#include <hal_data.h>
+
+#define PG_TXPWR_1PATH_BYTE_NUM_2G 18
+#define PG_TXPWR_BASE_BYTE_NUM_2G 11
+
+#define PG_TXPWR_1PATH_BYTE_NUM_5G 24
+#define PG_TXPWR_BASE_BYTE_NUM_5G 14
+
+#define PG_TXPWR_MSB_DIFF_S4BIT(_pg_v) (((_pg_v) & 0xf0) >> 4)
+#define PG_TXPWR_LSB_DIFF_S4BIT(_pg_v) ((_pg_v) & 0x0f)
+#define PG_TXPWR_MSB_DIFF_TO_S8BIT(_pg_v) ((PG_TXPWR_MSB_DIFF_S4BIT(_pg_v) & BIT3) ? (PG_TXPWR_MSB_DIFF_S4BIT(_pg_v) | 0xF0) : PG_TXPWR_MSB_DIFF_S4BIT(_pg_v))
+#define PG_TXPWR_LSB_DIFF_TO_S8BIT(_pg_v) ((PG_TXPWR_LSB_DIFF_S4BIT(_pg_v) & BIT3) ? (PG_TXPWR_LSB_DIFF_S4BIT(_pg_v) | 0xF0) : PG_TXPWR_LSB_DIFF_S4BIT(_pg_v))
+#define IS_PG_TXPWR_BASE_INVALID(hal_spec, _base) ((_base) > hal_spec->txgi_max)
+#define IS_PG_TXPWR_DIFF_INVALID(_diff) ((_diff) > 7 || (_diff) < -8)
+#define PG_TXPWR_INVALID_BASE 255
+#define PG_TXPWR_INVALID_DIFF 8
+
+#if !IS_PG_TXPWR_DIFF_INVALID(PG_TXPWR_INVALID_DIFF)
+#error "PG_TXPWR_DIFF definition has problem"
+#endif
+
+#define PG_TXPWR_SRC_PG_DATA	0
+#define PG_TXPWR_SRC_IC_DEF		1
+#define PG_TXPWR_SRC_DEF		2
+#define PG_TXPWR_SRC_NUM		3
+
+const char *const _pg_txpwr_src_str[] = {
+	"PG_DATA",
+	"IC_DEF",
+	"DEF",
+	"UNKNOWN"
+};
+
+#define pg_txpwr_src_str(src) (((src) >= PG_TXPWR_SRC_NUM) ? _pg_txpwr_src_str[PG_TXPWR_SRC_NUM] : _pg_txpwr_src_str[(src)])
+
+#ifndef DBG_PG_TXPWR_READ
+#define DBG_PG_TXPWR_READ 0
+#endif
+
+#if DBG_PG_TXPWR_READ
+static void dump_pg_txpwr_info_2g(void *sel, TxPowerInfo24G *txpwr_info, u8 rfpath_num, u8 max_tx_cnt)
+{
+	int path, group, tx_idx;
+
+	RTW_PRINT_SEL(sel, "2.4G\n");
+	RTW_PRINT_SEL(sel, "CCK-1T base:\n");
+	RTW_PRINT_SEL(sel, "%4s ", "");
+	for (group = 0; group < MAX_CHNL_GROUP_24G; group++)
+		_RTW_PRINT_SEL(sel, "G%02d ", group);
+	_RTW_PRINT_SEL(sel, "\n");
+	for (path = 0; path < MAX_RF_PATH && path < rfpath_num; path++) {
+		RTW_PRINT_SEL(sel, "[%c]: ", rf_path_char(path));
+		for (group = 0; group < MAX_CHNL_GROUP_24G; group++)
+			_RTW_PRINT_SEL(sel, "%3u ", txpwr_info->IndexCCK_Base[path][group]);
+		_RTW_PRINT_SEL(sel, "\n");
+	}
+	RTW_PRINT_SEL(sel, "\n");
+
+	RTW_PRINT_SEL(sel, "CCK diff:\n");
+	RTW_PRINT_SEL(sel, "%4s ", "");
+	for (path = 0; path < MAX_RF_PATH && path < rfpath_num; path++)
+		_RTW_PRINT_SEL(sel, "%dT ", path + 1);
+	_RTW_PRINT_SEL(sel, "\n");
+	for (path = 0; path < MAX_RF_PATH && path < rfpath_num; path++) {
+		RTW_PRINT_SEL(sel, "[%c]: ", rf_path_char(path));
+		for (tx_idx = RF_1TX; tx_idx < MAX_TX_COUNT && tx_idx < max_tx_cnt; tx_idx++)
+			_RTW_PRINT_SEL(sel, "%2d ", txpwr_info->CCK_Diff[path][tx_idx]);
+		_RTW_PRINT_SEL(sel, "\n");
+	}
+	RTW_PRINT_SEL(sel, "\n");
+
+	RTW_PRINT_SEL(sel, "BW40-1S base:\n");
+	RTW_PRINT_SEL(sel, "%4s ", "");
+	for (group = 0; group < MAX_CHNL_GROUP_24G - 1; group++)
+		_RTW_PRINT_SEL(sel, "G%02d ", group);
+	_RTW_PRINT_SEL(sel, "\n");
+	for (path = 0; path < MAX_RF_PATH && path < rfpath_num; path++) {
+		RTW_PRINT_SEL(sel, "[%c]: ", rf_path_char(path));
+		for (group = 0; group < MAX_CHNL_GROUP_24G - 1; group++)
+			_RTW_PRINT_SEL(sel, "%3u ", txpwr_info->IndexBW40_Base[path][group]);
+		_RTW_PRINT_SEL(sel, "\n");
+	}
+	RTW_PRINT_SEL(sel, "\n");
+
+	RTW_PRINT_SEL(sel, "OFDM diff:\n");
+	RTW_PRINT_SEL(sel, "%4s ", "");
+	for (path = 0; path < MAX_RF_PATH && path < rfpath_num; path++)
+		_RTW_PRINT_SEL(sel, "%dT ", path + 1);
+	_RTW_PRINT_SEL(sel, "\n");
+	for (path = 0; path < MAX_RF_PATH && path < rfpath_num; path++) {
+		RTW_PRINT_SEL(sel, "[%c]: ", rf_path_char(path));
+		for (tx_idx = RF_1TX; tx_idx < MAX_TX_COUNT && tx_idx < max_tx_cnt; tx_idx++)
+			_RTW_PRINT_SEL(sel, "%2d ", txpwr_info->OFDM_Diff[path][tx_idx]);
+		_RTW_PRINT_SEL(sel, "\n");
+	}
+	RTW_PRINT_SEL(sel, "\n");
+
+	RTW_PRINT_SEL(sel, "BW20 diff:\n");
+	RTW_PRINT_SEL(sel, "%4s ", "");
+	for (path = 0; path < MAX_RF_PATH && path < rfpath_num; path++)
+		_RTW_PRINT_SEL(sel, "%dS ", path + 1);
+	_RTW_PRINT_SEL(sel, "\n");
+	for (path = 0; path < MAX_RF_PATH && path < rfpath_num; path++) {
+		RTW_PRINT_SEL(sel, "[%c]: ", rf_path_char(path));
+		for (tx_idx = RF_1TX; tx_idx < MAX_TX_COUNT && tx_idx < max_tx_cnt; tx_idx++)
+			_RTW_PRINT_SEL(sel, "%2d ", txpwr_info->BW20_Diff[path][tx_idx]);
+		_RTW_PRINT_SEL(sel, "\n");
+	}
+	RTW_PRINT_SEL(sel, "\n");
+
+	RTW_PRINT_SEL(sel, "BW40 diff:\n");
+	RTW_PRINT_SEL(sel, "%4s ", "");
+	for (path = 0; path < MAX_RF_PATH && path < rfpath_num; path++)
+		_RTW_PRINT_SEL(sel, "%dS ", path + 1);
+	_RTW_PRINT_SEL(sel, "\n");
+	for (path = 0; path < MAX_RF_PATH && path < rfpath_num; path++) {
+		RTW_PRINT_SEL(sel, "[%c]: ", rf_path_char(path));
+		for (tx_idx = RF_1TX; tx_idx < MAX_TX_COUNT && tx_idx < max_tx_cnt; tx_idx++)
+			_RTW_PRINT_SEL(sel, "%2d ", txpwr_info->BW40_Diff[path][tx_idx]);
+		_RTW_PRINT_SEL(sel, "\n");
+	}
+	RTW_PRINT_SEL(sel, "\n");
+}
+
+static void dump_pg_txpwr_info_5g(void *sel, TxPowerInfo5G *txpwr_info, u8 rfpath_num, u8 max_tx_cnt)
+{
+	int path, group, tx_idx;
+
+	RTW_PRINT_SEL(sel, "5G\n");
+	RTW_PRINT_SEL(sel, "BW40-1S base:\n");
+	RTW_PRINT_SEL(sel, "%4s ", "");
+	for (group = 0; group < MAX_CHNL_GROUP_5G; group++)
+		_RTW_PRINT_SEL(sel, "G%02d ", group);
+	_RTW_PRINT_SEL(sel, "\n");
+	for (path = 0; path < MAX_RF_PATH && path < rfpath_num; path++) {
+		RTW_PRINT_SEL(sel, "[%c]: ", rf_path_char(path));
+		for (group = 0; group < MAX_CHNL_GROUP_5G; group++)
+			_RTW_PRINT_SEL(sel, "%3u ", txpwr_info->IndexBW40_Base[path][group]);
+		_RTW_PRINT_SEL(sel, "\n");
+	}
+	RTW_PRINT_SEL(sel, "\n");
+
+	RTW_PRINT_SEL(sel, "OFDM diff:\n");
+	RTW_PRINT_SEL(sel, "%4s ", "");
+	for (path = 0; path < MAX_RF_PATH && path < rfpath_num; path++)
+		_RTW_PRINT_SEL(sel, "%dT ", path + 1);
+	_RTW_PRINT_SEL(sel, "\n");
+	for (path = 0; path < MAX_RF_PATH && path < rfpath_num; path++) {
+		RTW_PRINT_SEL(sel, "[%c]: ", rf_path_char(path));
+		for (tx_idx = RF_1TX; tx_idx < MAX_TX_COUNT && tx_idx < max_tx_cnt; tx_idx++)
+			_RTW_PRINT_SEL(sel, "%2d ", txpwr_info->OFDM_Diff[path][tx_idx]);
+		_RTW_PRINT_SEL(sel, "\n");
+	}
+	RTW_PRINT_SEL(sel, "\n");
+
+	RTW_PRINT_SEL(sel, "BW20 diff:\n");
+	RTW_PRINT_SEL(sel, "%4s ", "");
+	for (path = 0; path < MAX_RF_PATH && path < rfpath_num; path++)
+		_RTW_PRINT_SEL(sel, "%dS ", path + 1);
+	_RTW_PRINT_SEL(sel, "\n");
+	for (path = 0; path < MAX_RF_PATH && path < rfpath_num; path++) {
+		RTW_PRINT_SEL(sel, "[%c]: ", rf_path_char(path));
+		for (tx_idx = RF_1TX; tx_idx < MAX_TX_COUNT && tx_idx < max_tx_cnt; tx_idx++)
+			_RTW_PRINT_SEL(sel, "%2d ", txpwr_info->BW20_Diff[path][tx_idx]);
+		_RTW_PRINT_SEL(sel, "\n");
+	}
+	RTW_PRINT_SEL(sel, "\n");
+
+	RTW_PRINT_SEL(sel, "BW40 diff:\n");
+	RTW_PRINT_SEL(sel, "%4s ", "");
+	for (path = 0; path < MAX_RF_PATH && path < rfpath_num; path++)
+		_RTW_PRINT_SEL(sel, "%dS ", path + 1);
+	_RTW_PRINT_SEL(sel, "\n");
+	for (path = 0; path < MAX_RF_PATH && path < rfpath_num; path++) {
+		RTW_PRINT_SEL(sel, "[%c]: ", rf_path_char(path));
+		for (tx_idx = RF_1TX; tx_idx < MAX_TX_COUNT && tx_idx < max_tx_cnt; tx_idx++)
+			_RTW_PRINT_SEL(sel, "%2d ", txpwr_info->BW40_Diff[path][tx_idx]);
+		_RTW_PRINT_SEL(sel, "\n");
+	}
+	RTW_PRINT_SEL(sel, "\n");
+
+	RTW_PRINT_SEL(sel, "BW80 diff:\n");
+	RTW_PRINT_SEL(sel, "%4s ", "");
+	for (path = 0; path < MAX_RF_PATH && path < rfpath_num; path++)
+		_RTW_PRINT_SEL(sel, "%dS ", path + 1);
+	_RTW_PRINT_SEL(sel, "\n");
+	for (path = 0; path < MAX_RF_PATH && path < rfpath_num; path++) {
+		RTW_PRINT_SEL(sel, "[%c]: ", rf_path_char(path));
+		for (tx_idx = RF_1TX; tx_idx < MAX_TX_COUNT && tx_idx < max_tx_cnt; tx_idx++)
+			_RTW_PRINT_SEL(sel, "%2d ", txpwr_info->BW80_Diff[path][tx_idx]);
+		_RTW_PRINT_SEL(sel, "\n");
+	}
+	RTW_PRINT_SEL(sel, "\n");
+
+	RTW_PRINT_SEL(sel, "BW160 diff:\n");
+	RTW_PRINT_SEL(sel, "%4s ", "");
+	for (path = 0; path < MAX_RF_PATH && path < rfpath_num; path++)
+		_RTW_PRINT_SEL(sel, "%dS ", path + 1);
+	_RTW_PRINT_SEL(sel, "\n");
+	for (path = 0; path < MAX_RF_PATH && path < rfpath_num; path++) {
+		RTW_PRINT_SEL(sel, "[%c]: ", rf_path_char(path));
+		for (tx_idx = RF_1TX; tx_idx < MAX_TX_COUNT && tx_idx < max_tx_cnt; tx_idx++)
+			_RTW_PRINT_SEL(sel, "%2d ", txpwr_info->BW160_Diff[path][tx_idx]);
+		_RTW_PRINT_SEL(sel, "\n");
+	}
+	RTW_PRINT_SEL(sel, "\n");
+}
+#endif /* DBG_PG_TXPWR_READ */
+
+const struct map_t pg_txpwr_def_info =
+	MAP_ENT(0xB8, 1, 0xFF
+		, MAPSEG_ARRAY_ENT(0x10, 168,
+			0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x24, 0xEE, 0xEE, 0xEE, 0xEE,
+			0xEE, 0xEE, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A,
+			0x04, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D,
+			0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x24, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0x2A, 0x2A, 0x2A, 0x2A,
+			0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x04, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE,
+			0xEE, 0xEE, 0xEE, 0xEE, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x24,
+			0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A,
+			0x2A, 0x2A, 0x2A, 0x2A, 0x04, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0x2D, 0x2D,
+			0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x24, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE,
+			0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x04, 0xEE,
+			0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE)
+	);
+
+#ifdef CONFIG_RTL8188E
+static const struct map_t rtl8188e_pg_txpwr_def_info =
+	MAP_ENT(0xB8, 1, 0xFF
+		, MAPSEG_ARRAY_ENT(0x10, 12,
+			0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x24)
+	);
+#endif
+
+#ifdef CONFIG_RTL8188F
+static const struct map_t rtl8188f_pg_txpwr_def_info =
+	MAP_ENT(0xB8, 1, 0xFF
+		, MAPSEG_ARRAY_ENT(0x10, 12,
+			0x22, 0x22, 0x22, 0x22, 0x22, 0x22, 0x27, 0x27, 0x27, 0x27, 0x27, 0x24)
+	);
+#endif
+
+#ifdef CONFIG_RTL8188GTV
+static const struct map_t rtl8188gtv_pg_txpwr_def_info =
+	MAP_ENT(0xB8, 1, 0xFF
+		, MAPSEG_ARRAY_ENT(0x10, 12,
+			0x22, 0x22, 0x22, 0x22, 0x22, 0x22, 0x27, 0x27, 0x27, 0x27, 0x27, 0x24)
+	);
+#endif
+
+#ifdef CONFIG_RTL8723B
+static const struct map_t rtl8723b_pg_txpwr_def_info =
+	MAP_ENT(0xB8, 2, 0xFF
+		, MAPSEG_ARRAY_ENT(0x10, 12,
+			0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0xE0)
+		, MAPSEG_ARRAY_ENT(0x3A, 12,
+			0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0xE0)
+	);
+#endif
+
+#ifdef CONFIG_RTL8703B
+static const struct map_t rtl8703b_pg_txpwr_def_info =
+	MAP_ENT(0xB8, 1, 0xFF
+		, MAPSEG_ARRAY_ENT(0x10, 12,
+			0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x02)
+	);
+#endif
+
+#ifdef CONFIG_RTL8723D
+static const struct map_t rtl8723d_pg_txpwr_def_info =
+	MAP_ENT(0xB8, 2, 0xFF
+		, MAPSEG_ARRAY_ENT(0x10, 12,
+			0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x02)
+		, MAPSEG_ARRAY_ENT(0x3A, 12,
+			0x22, 0x22, 0x22, 0x22, 0x22, 0x22, 0x21, 0x21, 0x21, 0x21, 0x21, 0x02)
+	);
+#endif
+
+#ifdef CONFIG_RTL8192E
+static const struct map_t rtl8192e_pg_txpwr_def_info =
+	MAP_ENT(0xB8, 2, 0xFF
+		, MAPSEG_ARRAY_ENT(0x10, 14,
+			0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x24, 0xEE, 0xEE)
+		, MAPSEG_ARRAY_ENT(0x3A, 14,
+			0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x24, 0xEE, 0xEE)
+	);
+#endif
+
+#ifdef CONFIG_RTL8821A
+static const struct map_t rtl8821a_pg_txpwr_def_info =
+	MAP_ENT(0xB8, 1, 0xFF
+		, MAPSEG_ARRAY_ENT(0x10, 39,
+			0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x24, 0xFF, 0xFF, 0xFF, 0xFF,
+			0xFF, 0xFF, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A,
+			0x04, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00)
+	);
+#endif
+
+#ifdef CONFIG_RTL8821C
+static const struct map_t rtl8821c_pg_txpwr_def_info =
+	MAP_ENT(0xB8, 1, 0xFF
+		, MAPSEG_ARRAY_ENT(0x10, 54,
+			0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x02, 0xFF, 0xFF, 0xFF, 0xFF, 
+			0xFF, 0xFF, 0x28, 0x28, 0x28, 0x28, 0x28, 0x28, 0x28, 0x28, 0x28, 0x28, 0x28, 0x28, 0x28, 0x28, 
+			0x02, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xEC, 0xFF, 0xFF, 0xFF, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D,
+			0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x02)
+	);
+#endif
+
+#ifdef CONFIG_RTL8710B
+static const struct map_t rtl8710b_pg_txpwr_def_info =
+	MAP_ENT(0xC8, 1, 0xFF
+		, MAPSEG_ARRAY_ENT(0x20, 12,
+			0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x20)
+	);
+#endif
+
+#ifdef CONFIG_RTL8812A
+static const struct map_t rtl8812a_pg_txpwr_def_info =
+	MAP_ENT(0xB8, 1, 0xFF
+		, MAPSEG_ARRAY_ENT(0x10, 82,
+			0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x02, 0xEE, 0xEE, 0xFF, 0xFF,
+			0xFF, 0xFF, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A,
+			0x02, 0xEE, 0xFF, 0xFF, 0xEE, 0xFF, 0x00, 0xEE, 0xFF, 0xFF, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D,
+			0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x02, 0xEE, 0xEE, 0xFF, 0xFF, 0xFF, 0xFF, 0x2A, 0x2A, 0x2A, 0x2A,
+			0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x02, 0xEE, 0xFF, 0xFF, 0xEE, 0xFF,
+			0x00, 0xEE)
+	);
+#endif
+
+#ifdef CONFIG_RTL8822B
+static const struct map_t rtl8822b_pg_txpwr_def_info =
+	MAP_ENT(0xB8, 1, 0xFF
+		, MAPSEG_ARRAY_ENT(0x10, 82,
+			0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x02, 0xEE, 0xEE, 0xFF, 0xFF,
+			0xFF, 0xFF, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A,
+			0x02, 0xEE, 0xFF, 0xFF, 0xEE, 0xFF, 0xEC, 0xEC, 0xFF, 0xFF, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D,
+			0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x02, 0xEE, 0xEE, 0xFF, 0xFF, 0xFF, 0xFF, 0x2A, 0x2A, 0x2A, 0x2A,
+			0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x02, 0xEE, 0xFF, 0xFF, 0xEE, 0xFF,
+			0xEC, 0xEC)
+	);
+#endif
+
+#ifdef CONFIG_RTL8814A
+static const struct map_t rtl8814a_pg_txpwr_def_info =
+	MAP_ENT(0xB8, 1, 0xFF
+		, MAPSEG_ARRAY_ENT(0x10, 168,
+			0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x02, 0xEE, 0xEE, 0xEE, 0xEE,
+			0xEE, 0xEE, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A,
+			0x02, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0x00, 0xEE, 0xEE, 0xEE, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D,
+			0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x02, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0x2A, 0x2A, 0x2A, 0x2A,
+			0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x02, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE,
+			0x00, 0xEE, 0xEE, 0xEE, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x02,
+			0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A,
+			0x2A, 0x2A, 0x2A, 0x2A, 0x02, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0x00, 0xEE, 0xEE, 0xEE, 0x2D, 0x2D,
+			0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x02, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE,
+			0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x02, 0xEE,
+			0xEE, 0xEE, 0xEE, 0xEE, 0x00, 0xEE, 0xEE, 0xEE)
+	);
+#endif
+
+#ifdef CONFIG_RTL8192F/*use 8192F default,no document*/
+static const struct map_t rtl8192f_pg_txpwr_def_info =
+	MAP_ENT(0xB8, 2, 0xFF
+		, MAPSEG_ARRAY_ENT(0x10, 14,
+			0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x24, 0xEE, 0xEE)
+		, MAPSEG_ARRAY_ENT(0x3A, 14,
+			0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x24, 0xEE, 0xEE)
+	);
+#endif
+
+const struct map_t *hal_pg_txpwr_def_info(_adapter *adapter)
+{
+	u8 interface_type = 0;
+	const struct map_t *map = NULL;
+
+	interface_type = rtw_get_intf_type(adapter);
+
+	switch (rtw_get_chip_type(adapter)) {
+#ifdef CONFIG_RTL8723B
+	case RTL8723B:
+		map = &rtl8723b_pg_txpwr_def_info;
+		break;
+#endif
+#ifdef CONFIG_RTL8703B
+	case RTL8703B:
+		map = &rtl8703b_pg_txpwr_def_info;
+		break;
+#endif
+#ifdef CONFIG_RTL8723D
+	case RTL8723D:
+		map = &rtl8723d_pg_txpwr_def_info;
+		break;
+#endif
+#ifdef CONFIG_RTL8188E
+	case RTL8188E:
+		map = &rtl8188e_pg_txpwr_def_info;
+		break;
+#endif
+#ifdef CONFIG_RTL8188F
+	case RTL8188F:
+		map = &rtl8188f_pg_txpwr_def_info;
+		break;
+#endif
+#ifdef CONFIG_RTL8188GTV
+	case RTL8188GTV:
+		map = &rtl8188gtv_pg_txpwr_def_info;
+		break;
+#endif
+#ifdef CONFIG_RTL8812A
+	case RTL8812:
+		map = &rtl8812a_pg_txpwr_def_info;
+		break;
+#endif
+#ifdef CONFIG_RTL8821A
+	case RTL8821:
+		map = &rtl8821a_pg_txpwr_def_info;
+		break;
+#endif
+#ifdef CONFIG_RTL8192E
+	case RTL8192E:
+		map = &rtl8192e_pg_txpwr_def_info;
+		break;
+#endif
+#ifdef CONFIG_RTL8814A
+	case RTL8814A:
+		map = &rtl8814a_pg_txpwr_def_info;
+		break;
+#endif
+#ifdef CONFIG_RTL8822B
+	case RTL8822B:
+		map = &rtl8822b_pg_txpwr_def_info;
+		break;
+#endif
+#ifdef CONFIG_RTL8821C
+	case RTL8821C:
+		map = &rtl8821c_pg_txpwr_def_info;
+		break;
+#endif
+#ifdef CONFIG_RTL8710B
+	case RTL8710B:
+		map = &rtl8710b_pg_txpwr_def_info;
+		break;
+#endif
+#ifdef CONFIG_RTL8192F
+	case RTL8192F:
+		map = &rtl8192f_pg_txpwr_def_info;
+		break;
+#endif
+	}
+
+	if (map == NULL) {
+		RTW_ERR("%s: unknown chip_type:%u\n"
+			, __func__, rtw_get_chip_type(adapter));
+		rtw_warn_on(1);
+	}
+
+	return map;
+}
+
+static u8 hal_chk_pg_txpwr_info_2g(_adapter *adapter, TxPowerInfo24G *pwr_info)
+{
+	struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter);
+	u8 path, group, tx_idx;
+
+	if (pwr_info == NULL || !hal_chk_band_cap(adapter, BAND_CAP_2G))
+		return _SUCCESS;
+
+	for (path = 0; path < MAX_RF_PATH; path++) {
+		if (!HAL_SPEC_CHK_RF_PATH_2G(hal_spec, path))
+			continue;
+		for (group = 0; group < MAX_CHNL_GROUP_24G; group++) {
+			if (IS_PG_TXPWR_BASE_INVALID(hal_spec, pwr_info->IndexCCK_Base[path][group])
+				|| IS_PG_TXPWR_BASE_INVALID(hal_spec, pwr_info->IndexBW40_Base[path][group]))
+				return _FAIL;
+		}
+		for (tx_idx = 0; tx_idx < MAX_TX_COUNT; tx_idx++) {
+			if (!HAL_SPEC_CHK_TX_CNT(hal_spec, tx_idx))
+				continue;
+			if (IS_PG_TXPWR_DIFF_INVALID(pwr_info->CCK_Diff[path][tx_idx])
+				|| IS_PG_TXPWR_DIFF_INVALID(pwr_info->OFDM_Diff[path][tx_idx])
+				|| IS_PG_TXPWR_DIFF_INVALID(pwr_info->BW20_Diff[path][tx_idx])
+				|| IS_PG_TXPWR_DIFF_INVALID(pwr_info->BW40_Diff[path][tx_idx]))
+				return _FAIL;
+		}
+	}
+
+	return _SUCCESS;
+}
+
+static u8 hal_chk_pg_txpwr_info_5g(_adapter *adapter, TxPowerInfo5G *pwr_info)
+{
+#ifdef CONFIG_IEEE80211_BAND_5GHZ
+	struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter);
+	u8 path, group, tx_idx;
+
+	if (pwr_info == NULL || !hal_chk_band_cap(adapter, BAND_CAP_5G))
+		return _SUCCESS;
+
+	for (path = 0; path < MAX_RF_PATH; path++) {
+		if (!HAL_SPEC_CHK_RF_PATH_5G(hal_spec, path))
+			continue;
+		for (group = 0; group < MAX_CHNL_GROUP_5G; group++)
+			if (IS_PG_TXPWR_BASE_INVALID(hal_spec, pwr_info->IndexBW40_Base[path][group]))
+				return _FAIL;
+		for (tx_idx = 0; tx_idx < MAX_TX_COUNT; tx_idx++) {
+			if (!HAL_SPEC_CHK_TX_CNT(hal_spec, tx_idx))
+				continue;
+			if (IS_PG_TXPWR_DIFF_INVALID(pwr_info->OFDM_Diff[path][tx_idx])
+				|| IS_PG_TXPWR_DIFF_INVALID(pwr_info->BW20_Diff[path][tx_idx])
+				|| IS_PG_TXPWR_DIFF_INVALID(pwr_info->BW40_Diff[path][tx_idx])
+				|| IS_PG_TXPWR_DIFF_INVALID(pwr_info->BW80_Diff[path][tx_idx])
+				|| IS_PG_TXPWR_DIFF_INVALID(pwr_info->BW160_Diff[path][tx_idx]))
+				return _FAIL;
+		}
+	}
+#endif /* CONFIG_IEEE80211_BAND_5GHZ */
+	return _SUCCESS;
+}
+
+static inline void hal_init_pg_txpwr_info_2g(_adapter *adapter, TxPowerInfo24G *pwr_info)
+{
+	struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter);
+	u8 path, group, tx_idx;
+
+	if (pwr_info == NULL)
+		return;
+
+	_rtw_memset(pwr_info, 0, sizeof(TxPowerInfo24G));
+
+	/* init with invalid value */
+	for (path = 0; path < MAX_RF_PATH; path++) {
+		for (group = 0; group < MAX_CHNL_GROUP_24G; group++) {
+			pwr_info->IndexCCK_Base[path][group] = PG_TXPWR_INVALID_BASE;
+			pwr_info->IndexBW40_Base[path][group] = PG_TXPWR_INVALID_BASE;
+		}
+		for (tx_idx = 0; tx_idx < MAX_TX_COUNT; tx_idx++) {
+			pwr_info->CCK_Diff[path][tx_idx] = PG_TXPWR_INVALID_DIFF;
+			pwr_info->OFDM_Diff[path][tx_idx] = PG_TXPWR_INVALID_DIFF;
+			pwr_info->BW20_Diff[path][tx_idx] = PG_TXPWR_INVALID_DIFF;
+			pwr_info->BW40_Diff[path][tx_idx] = PG_TXPWR_INVALID_DIFF;
+		}
+	}
+
+	/* init for dummy base and diff */
+	for (path = 0; path < MAX_RF_PATH; path++) {
+		if (!HAL_SPEC_CHK_RF_PATH_2G(hal_spec, path))
+			break;
+		/* 2.4G BW40 base has 1 less group than CCK base*/
+		pwr_info->IndexBW40_Base[path][MAX_CHNL_GROUP_24G - 1] = 0;
+
+		/* dummy diff */
+		pwr_info->CCK_Diff[path][0] = 0; /* 2.4G CCK-1TX */
+		pwr_info->BW40_Diff[path][0] = 0; /* 2.4G BW40-1S */
+	}
+}
+
+static inline void hal_init_pg_txpwr_info_5g(_adapter *adapter, TxPowerInfo5G *pwr_info)
+{
+#ifdef CONFIG_IEEE80211_BAND_5GHZ
+	struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter);
+	u8 path, group, tx_idx;
+
+	if (pwr_info == NULL)
+		return;
+
+	_rtw_memset(pwr_info, 0, sizeof(TxPowerInfo5G));
+
+	/* init with invalid value */
+	for (path = 0; path < MAX_RF_PATH; path++) {
+		for (group = 0; group < MAX_CHNL_GROUP_5G; group++)
+			pwr_info->IndexBW40_Base[path][group] = PG_TXPWR_INVALID_BASE;
+		for (tx_idx = 0; tx_idx < MAX_TX_COUNT; tx_idx++) {
+			pwr_info->OFDM_Diff[path][tx_idx] = PG_TXPWR_INVALID_DIFF;
+			pwr_info->BW20_Diff[path][tx_idx] = PG_TXPWR_INVALID_DIFF;
+			pwr_info->BW40_Diff[path][tx_idx] = PG_TXPWR_INVALID_DIFF;
+			pwr_info->BW80_Diff[path][tx_idx] = PG_TXPWR_INVALID_DIFF;
+			pwr_info->BW160_Diff[path][tx_idx] = PG_TXPWR_INVALID_DIFF;
+		}
+	}
+
+	for (path = 0; path < MAX_RF_PATH; path++) {
+		if (!HAL_SPEC_CHK_RF_PATH_5G(hal_spec, path))
+			break;
+		/* dummy diff */
+		pwr_info->BW40_Diff[path][0] = 0; /* 5G BW40-1S */
+	}
+#endif /* CONFIG_IEEE80211_BAND_5GHZ */
+}
+
+#if DBG_PG_TXPWR_READ
+#define LOAD_PG_TXPWR_WARN_COND(_txpwr_src) 1
+#else
+#define LOAD_PG_TXPWR_WARN_COND(_txpwr_src) (_txpwr_src > PG_TXPWR_SRC_PG_DATA)
+#endif
+
+u16 hal_load_pg_txpwr_info_path_2g(
+	_adapter *adapter,
+	TxPowerInfo24G	*pwr_info,
+	u32 path,
+	u8 txpwr_src,
+	const struct map_t *txpwr_map,
+	u16 pg_offset)
+{
+	struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter);
+	u16 offset = pg_offset;
+	u8 group, tx_idx;
+	u8 val;
+	u8 tmp_base;
+	s8 tmp_diff;
+
+	if (pwr_info == NULL || !hal_chk_band_cap(adapter, BAND_CAP_2G)) {
+		offset += PG_TXPWR_1PATH_BYTE_NUM_2G;
+		goto exit;
+	}
+
+	if (DBG_PG_TXPWR_READ)
+		RTW_INFO("%s [%c] offset:0x%03x\n", __func__, rf_path_char(path), offset);
+
+	for (group = 0; group < MAX_CHNL_GROUP_24G; group++) {
+		if (HAL_SPEC_CHK_RF_PATH_2G(hal_spec, path)) {
+			tmp_base = map_read8(txpwr_map, offset);
+			if (!IS_PG_TXPWR_BASE_INVALID(hal_spec, tmp_base)
+				&& IS_PG_TXPWR_BASE_INVALID(hal_spec, pwr_info->IndexCCK_Base[path][group])
+			) {
+				pwr_info->IndexCCK_Base[path][group] = tmp_base;
+				if (LOAD_PG_TXPWR_WARN_COND(txpwr_src))
+					RTW_INFO("[%c] 2G G%02d CCK-1T base:%u from %s\n", rf_path_char(path), group, tmp_base, pg_txpwr_src_str(txpwr_src));
+			}
+		}
+		offset++;
+	}
+
+	for (group = 0; group < MAX_CHNL_GROUP_24G - 1; group++) {
+		if (HAL_SPEC_CHK_RF_PATH_2G(hal_spec, path)) {
+			tmp_base = map_read8(txpwr_map, offset);
+			if (!IS_PG_TXPWR_BASE_INVALID(hal_spec, tmp_base)
+				&& IS_PG_TXPWR_BASE_INVALID(hal_spec, pwr_info->IndexBW40_Base[path][group])
+			) {
+				pwr_info->IndexBW40_Base[path][group] =	tmp_base;
+				if (LOAD_PG_TXPWR_WARN_COND(txpwr_src))
+					RTW_INFO("[%c] 2G G%02d BW40-1S base:%u from %s\n", rf_path_char(path), group, tmp_base, pg_txpwr_src_str(txpwr_src));
+			}
+		}
+		offset++;
+	}
+
+	for (tx_idx = 0; tx_idx < MAX_TX_COUNT; tx_idx++) {
+		if (tx_idx == 0) {
+			if (HAL_SPEC_CHK_RF_PATH_2G(hal_spec, path) && HAL_SPEC_CHK_TX_CNT(hal_spec, tx_idx)) {
+				val = map_read8(txpwr_map, offset);
+				tmp_diff = PG_TXPWR_MSB_DIFF_TO_S8BIT(val);
+				if (!IS_PG_TXPWR_DIFF_INVALID(tmp_diff)
+					&& IS_PG_TXPWR_DIFF_INVALID(pwr_info->BW20_Diff[path][tx_idx])
+				) {
+					pwr_info->BW20_Diff[path][tx_idx] = tmp_diff;
+					if (LOAD_PG_TXPWR_WARN_COND(txpwr_src))
+						RTW_INFO("[%c] 2G BW20-%dS diff:%d from %s\n", rf_path_char(path), tx_idx + 1, tmp_diff, pg_txpwr_src_str(txpwr_src));
+				}
+				tmp_diff = PG_TXPWR_LSB_DIFF_TO_S8BIT(val);
+				if (!IS_PG_TXPWR_DIFF_INVALID(tmp_diff)
+					&& IS_PG_TXPWR_DIFF_INVALID(pwr_info->OFDM_Diff[path][tx_idx])
+				) {
+					pwr_info->OFDM_Diff[path][tx_idx] = tmp_diff;
+					if (LOAD_PG_TXPWR_WARN_COND(txpwr_src))
+						RTW_INFO("[%c] 2G OFDM-%dT diff:%d from %s\n", rf_path_char(path), tx_idx + 1, tmp_diff, pg_txpwr_src_str(txpwr_src));
+				}
+			}
+			offset++;
+		} else {
+			if (HAL_SPEC_CHK_RF_PATH_2G(hal_spec, path) && HAL_SPEC_CHK_TX_CNT(hal_spec, tx_idx)) {
+				val = map_read8(txpwr_map, offset);
+				tmp_diff = PG_TXPWR_MSB_DIFF_TO_S8BIT(val);
+				if (!IS_PG_TXPWR_DIFF_INVALID(tmp_diff)
+					&& IS_PG_TXPWR_DIFF_INVALID(pwr_info->BW40_Diff[path][tx_idx])
+				) {
+					pwr_info->BW40_Diff[path][tx_idx] = tmp_diff;
+					if (LOAD_PG_TXPWR_WARN_COND(txpwr_src))
+						RTW_INFO("[%c] 2G BW40-%dS diff:%d from %s\n", rf_path_char(path), tx_idx + 1, tmp_diff, pg_txpwr_src_str(txpwr_src));
+
+				}
+				tmp_diff = PG_TXPWR_LSB_DIFF_TO_S8BIT(val);
+				if (!IS_PG_TXPWR_DIFF_INVALID(tmp_diff)
+					&& IS_PG_TXPWR_DIFF_INVALID(pwr_info->BW20_Diff[path][tx_idx])
+				) {
+					pwr_info->BW20_Diff[path][tx_idx] = tmp_diff;
+					if (LOAD_PG_TXPWR_WARN_COND(txpwr_src))
+						RTW_INFO("[%c] 2G BW20-%dS diff:%d from %s\n", rf_path_char(path), tx_idx + 1, tmp_diff, pg_txpwr_src_str(txpwr_src));
+				}
+			}
+			offset++;
+
+			if (HAL_SPEC_CHK_RF_PATH_2G(hal_spec, path) && HAL_SPEC_CHK_TX_CNT(hal_spec, tx_idx)) {
+				val = map_read8(txpwr_map, offset);
+				tmp_diff = PG_TXPWR_MSB_DIFF_TO_S8BIT(val);
+				if (!IS_PG_TXPWR_DIFF_INVALID(tmp_diff)
+					&& IS_PG_TXPWR_DIFF_INVALID(pwr_info->OFDM_Diff[path][tx_idx])
+				) {
+					pwr_info->OFDM_Diff[path][tx_idx] = tmp_diff;
+					if (LOAD_PG_TXPWR_WARN_COND(txpwr_src))
+						RTW_INFO("[%c] 2G OFDM-%dT diff:%d from %s\n", rf_path_char(path), tx_idx + 1, tmp_diff, pg_txpwr_src_str(txpwr_src));
+				}
+				tmp_diff = PG_TXPWR_LSB_DIFF_TO_S8BIT(val);
+				if (!IS_PG_TXPWR_DIFF_INVALID(tmp_diff)
+					&& IS_PG_TXPWR_DIFF_INVALID(pwr_info->CCK_Diff[path][tx_idx])
+				) {
+					pwr_info->CCK_Diff[path][tx_idx] =	tmp_diff;
+					if (LOAD_PG_TXPWR_WARN_COND(txpwr_src))
+						RTW_INFO("[%c] 2G CCK-%dT diff:%d from %s\n", rf_path_char(path), tx_idx + 1, tmp_diff, pg_txpwr_src_str(txpwr_src));
+				}
+			}
+			offset++;
+		}
+	}
+
+	if (offset != pg_offset + PG_TXPWR_1PATH_BYTE_NUM_2G) {
+		RTW_ERR("%s parse %d bytes != %d\n", __func__, offset - pg_offset, PG_TXPWR_1PATH_BYTE_NUM_2G);
+		rtw_warn_on(1);
+	}
+
+exit:	
+	return offset;
+}
+
+u16 hal_load_pg_txpwr_info_path_5g(
+	_adapter *adapter,
+	TxPowerInfo5G	*pwr_info,
+	u32 path,
+	u8 txpwr_src,
+	const struct map_t *txpwr_map,
+	u16 pg_offset)
+{
+	struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter);
+	u16 offset = pg_offset;
+	u8 group, tx_idx;
+	u8 val;
+	u8 tmp_base;
+	s8 tmp_diff;
+
+#ifdef CONFIG_IEEE80211_BAND_5GHZ
+	if (pwr_info == NULL || !hal_chk_band_cap(adapter, BAND_CAP_5G))
+#endif
+	{
+		offset += PG_TXPWR_1PATH_BYTE_NUM_5G;
+		goto exit;
+	}
+	
+#ifdef CONFIG_IEEE80211_BAND_5GHZ
+	if (DBG_PG_TXPWR_READ)
+		RTW_INFO("%s[%c] eaddr:0x%03x\n", __func__, rf_path_char(path), offset);
+
+	for (group = 0; group < MAX_CHNL_GROUP_5G; group++) {
+		if (HAL_SPEC_CHK_RF_PATH_5G(hal_spec, path)) {
+			tmp_base = map_read8(txpwr_map, offset);
+			if (!IS_PG_TXPWR_BASE_INVALID(hal_spec, tmp_base)
+				&& IS_PG_TXPWR_BASE_INVALID(hal_spec, pwr_info->IndexBW40_Base[path][group])
+			) {
+				pwr_info->IndexBW40_Base[path][group] = tmp_base;
+				if (LOAD_PG_TXPWR_WARN_COND(txpwr_src))
+					RTW_INFO("[%c] 5G G%02d BW40-1S base:%u from %s\n", rf_path_char(path), group, tmp_base, pg_txpwr_src_str(txpwr_src));
+			}
+		}
+		offset++;
+	}
+
+	for (tx_idx = 0; tx_idx < MAX_TX_COUNT; tx_idx++) {
+		if (tx_idx == 0) {
+			if (HAL_SPEC_CHK_RF_PATH_5G(hal_spec, path) && HAL_SPEC_CHK_TX_CNT(hal_spec, tx_idx)) {
+				val = map_read8(txpwr_map, offset);
+				tmp_diff = PG_TXPWR_MSB_DIFF_TO_S8BIT(val);
+				if (!IS_PG_TXPWR_DIFF_INVALID(tmp_diff)
+					&& IS_PG_TXPWR_DIFF_INVALID(pwr_info->BW20_Diff[path][tx_idx])
+				) {
+					pwr_info->BW20_Diff[path][tx_idx] = tmp_diff;
+					if (LOAD_PG_TXPWR_WARN_COND(txpwr_src))
+						RTW_INFO("[%c] 5G BW20-%dS diff:%d from %s\n", rf_path_char(path), tx_idx + 1, tmp_diff, pg_txpwr_src_str(txpwr_src));
+				}
+				tmp_diff = PG_TXPWR_LSB_DIFF_TO_S8BIT(val);
+				if (!IS_PG_TXPWR_DIFF_INVALID(tmp_diff)
+					&& IS_PG_TXPWR_DIFF_INVALID(pwr_info->OFDM_Diff[path][tx_idx])
+				) {
+					pwr_info->OFDM_Diff[path][tx_idx] = tmp_diff;
+					if (LOAD_PG_TXPWR_WARN_COND(txpwr_src))
+						RTW_INFO("[%c] 5G OFDM-%dT diff:%d from %s\n", rf_path_char(path), tx_idx + 1, tmp_diff, pg_txpwr_src_str(txpwr_src));
+				}
+			}
+			offset++;
+		} else {
+			if (HAL_SPEC_CHK_RF_PATH_5G(hal_spec, path) && HAL_SPEC_CHK_TX_CNT(hal_spec, tx_idx)) {
+				val = map_read8(txpwr_map, offset);
+				tmp_diff = PG_TXPWR_MSB_DIFF_TO_S8BIT(val);
+				if (!IS_PG_TXPWR_DIFF_INVALID(tmp_diff)
+					&& IS_PG_TXPWR_DIFF_INVALID(pwr_info->BW40_Diff[path][tx_idx])
+				) {
+					pwr_info->BW40_Diff[path][tx_idx] = tmp_diff;
+					if (LOAD_PG_TXPWR_WARN_COND(txpwr_src))
+						RTW_INFO("[%c] 5G BW40-%dS diff:%d from %s\n", rf_path_char(path), tx_idx + 1, tmp_diff, pg_txpwr_src_str(txpwr_src));
+				}
+				tmp_diff = PG_TXPWR_LSB_DIFF_TO_S8BIT(val);
+				if (!IS_PG_TXPWR_DIFF_INVALID(tmp_diff)
+					&& IS_PG_TXPWR_DIFF_INVALID(pwr_info->BW20_Diff[path][tx_idx])
+				) {
+					pwr_info->BW20_Diff[path][tx_idx] = tmp_diff;
+					if (LOAD_PG_TXPWR_WARN_COND(txpwr_src))
+						RTW_INFO("[%c] 5G BW20-%dS diff:%d from %s\n", rf_path_char(path), tx_idx + 1, tmp_diff, pg_txpwr_src_str(txpwr_src));
+				}
+			}
+			offset++;
+		}
+	}	
+
+	/* OFDM diff 2T ~ 3T */
+	if (HAL_SPEC_CHK_RF_PATH_5G(hal_spec, path) && HAL_SPEC_CHK_TX_CNT(hal_spec, 1)) {
+		val = map_read8(txpwr_map, offset);
+		tmp_diff = PG_TXPWR_MSB_DIFF_TO_S8BIT(val);
+		if (!IS_PG_TXPWR_DIFF_INVALID(tmp_diff)
+			&& IS_PG_TXPWR_DIFF_INVALID(pwr_info->OFDM_Diff[path][1])
+		) {
+			pwr_info->OFDM_Diff[path][1] = tmp_diff;
+			if (LOAD_PG_TXPWR_WARN_COND(txpwr_src))
+				RTW_INFO("[%c] 5G OFDM-%dT diff:%d from %s\n", rf_path_char(path), 2, tmp_diff, pg_txpwr_src_str(txpwr_src));
+		}
+		if (HAL_SPEC_CHK_TX_CNT(hal_spec, 2)) {
+			tmp_diff = PG_TXPWR_LSB_DIFF_TO_S8BIT(val);
+			if (!IS_PG_TXPWR_DIFF_INVALID(tmp_diff)
+				&& IS_PG_TXPWR_DIFF_INVALID(pwr_info->OFDM_Diff[path][2])
+			) {
+				pwr_info->OFDM_Diff[path][2] = tmp_diff;
+				if (LOAD_PG_TXPWR_WARN_COND(txpwr_src))
+					RTW_INFO("[%c] 5G OFDM-%dT diff:%d from %s\n", rf_path_char(path), 3, tmp_diff, pg_txpwr_src_str(txpwr_src));
+			}
+		}
+	}
+	offset++;
+
+	/* OFDM diff 4T */
+	if (HAL_SPEC_CHK_RF_PATH_5G(hal_spec, path) && HAL_SPEC_CHK_TX_CNT(hal_spec, 3)) {
+		val = map_read8(txpwr_map, offset);
+		tmp_diff = PG_TXPWR_LSB_DIFF_TO_S8BIT(val);
+		if (!IS_PG_TXPWR_DIFF_INVALID(tmp_diff)
+			&& IS_PG_TXPWR_DIFF_INVALID(pwr_info->OFDM_Diff[path][3])
+		) {
+			pwr_info->OFDM_Diff[path][3] = tmp_diff;
+			if (LOAD_PG_TXPWR_WARN_COND(txpwr_src))
+				RTW_INFO("[%c] 5G OFDM-%dT diff:%d from %s\n", rf_path_char(path), 4, tmp_diff, pg_txpwr_src_str(txpwr_src));
+		}
+	}
+	offset++;
+
+	for (tx_idx = 0; tx_idx < MAX_TX_COUNT; tx_idx++) {
+		if (HAL_SPEC_CHK_RF_PATH_5G(hal_spec, path) && HAL_SPEC_CHK_TX_CNT(hal_spec, tx_idx)) {
+			val = map_read8(txpwr_map, offset);
+			tmp_diff = PG_TXPWR_MSB_DIFF_TO_S8BIT(val);
+			if (!IS_PG_TXPWR_DIFF_INVALID(tmp_diff)
+				&& IS_PG_TXPWR_DIFF_INVALID(pwr_info->BW80_Diff[path][tx_idx])
+			) {
+				pwr_info->BW80_Diff[path][tx_idx] = tmp_diff;
+				if (LOAD_PG_TXPWR_WARN_COND(txpwr_src))
+					RTW_INFO("[%c] 5G BW80-%dS diff:%d from %s\n", rf_path_char(path), tx_idx + 1, tmp_diff, pg_txpwr_src_str(txpwr_src));
+			}
+			tmp_diff = PG_TXPWR_LSB_DIFF_TO_S8BIT(val);
+			if (!IS_PG_TXPWR_DIFF_INVALID(tmp_diff)
+				&& IS_PG_TXPWR_DIFF_INVALID(pwr_info->BW160_Diff[path][tx_idx])
+			) {
+				pwr_info->BW160_Diff[path][tx_idx] = tmp_diff;
+				if (LOAD_PG_TXPWR_WARN_COND(txpwr_src))
+					RTW_INFO("[%c] 5G BW160-%dS diff:%d from %s\n", rf_path_char(path), tx_idx + 1, tmp_diff, pg_txpwr_src_str(txpwr_src));
+			}
+		}
+		offset++;
+	}
+
+	if (offset != pg_offset + PG_TXPWR_1PATH_BYTE_NUM_5G) {
+		RTW_ERR("%s parse %d bytes != %d\n", __func__, offset - pg_offset, PG_TXPWR_1PATH_BYTE_NUM_5G);
+		rtw_warn_on(1);
+	}
+
+#endif /* #ifdef CONFIG_IEEE80211_BAND_5GHZ */
+
+exit:
+	return offset;
+}
+
+void hal_load_pg_txpwr_info(
+	_adapter *adapter,
+	TxPowerInfo24G *pwr_info_2g,
+	TxPowerInfo5G *pwr_info_5g,
+	u8 *pg_data,
+	BOOLEAN AutoLoadFail
+)
+{
+	struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter);
+	u8 path;
+	u16 pg_offset;
+	u8 txpwr_src = PG_TXPWR_SRC_PG_DATA;
+	struct map_t pg_data_map = MAP_ENT(184, 1, 0xFF, MAPSEG_PTR_ENT(0x00, 184, pg_data));
+	const struct map_t *txpwr_map = NULL;
+
+	/* init with invalid value and some dummy base and diff */
+	hal_init_pg_txpwr_info_2g(adapter, pwr_info_2g);
+	hal_init_pg_txpwr_info_5g(adapter, pwr_info_5g);
+
+select_src:
+	pg_offset = hal_spec->pg_txpwr_saddr;
+
+	switch (txpwr_src) {
+	case PG_TXPWR_SRC_PG_DATA:
+		txpwr_map = &pg_data_map;
+		break;
+	case PG_TXPWR_SRC_IC_DEF:
+		txpwr_map = hal_pg_txpwr_def_info(adapter);
+		break;
+	case PG_TXPWR_SRC_DEF:
+	default:
+		txpwr_map = &pg_txpwr_def_info;
+		break;
+	};
+
+	if (txpwr_map == NULL)
+		goto end_parse;
+
+	for (path = 0; path < MAX_RF_PATH ; path++) {
+		if (!HAL_SPEC_CHK_RF_PATH_2G(hal_spec, path) && !HAL_SPEC_CHK_RF_PATH_5G(hal_spec, path))
+			break;
+		pg_offset = hal_load_pg_txpwr_info_path_2g(adapter, pwr_info_2g, path, txpwr_src, txpwr_map, pg_offset);
+		pg_offset = hal_load_pg_txpwr_info_path_5g(adapter, pwr_info_5g, path, txpwr_src, txpwr_map, pg_offset);
+	}
+
+	if (hal_chk_pg_txpwr_info_2g(adapter, pwr_info_2g) == _SUCCESS
+		&& hal_chk_pg_txpwr_info_5g(adapter, pwr_info_5g) == _SUCCESS)
+		goto exit;
+
+end_parse:
+	txpwr_src++;
+	if (txpwr_src < PG_TXPWR_SRC_NUM)
+		goto select_src;
+
+	if (hal_chk_pg_txpwr_info_2g(adapter, pwr_info_2g) != _SUCCESS
+		|| hal_chk_pg_txpwr_info_5g(adapter, pwr_info_5g) != _SUCCESS)
+		rtw_warn_on(1);
+
+exit:
+	#if DBG_PG_TXPWR_READ
+	if (pwr_info_2g)
+		dump_pg_txpwr_info_2g(RTW_DBGDUMP, pwr_info_2g, 4, 4);
+	if (pwr_info_5g)
+		dump_pg_txpwr_info_5g(RTW_DBGDUMP, pwr_info_5g, 4, 4);
+	#endif
+
+	return;
+}
+
+#ifdef CONFIG_EFUSE_CONFIG_FILE
+
+#define EFUSE_POWER_INDEX_INVALID 0xFF
+
+static u8 _check_phy_efuse_tx_power_info_valid(u8 *pg_data, int base_len, u16 pg_offset)
+{
+	int ff_cnt = 0;
+	int i;
+
+	for (i = 0; i < base_len; i++) {
+		if (*(pg_data + pg_offset + i) == 0xFF)
+			ff_cnt++;
+	}
+
+	if (ff_cnt == 0)
+		return _TRUE;
+	else if (ff_cnt == base_len)
+		return _FALSE;
+	else
+		return EFUSE_POWER_INDEX_INVALID;
+}
+
+int check_phy_efuse_tx_power_info_valid(_adapter *adapter)
+{
+	struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter);
+	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
+	u8 *pg_data = hal_data->efuse_eeprom_data;
+	u16 pg_offset = hal_spec->pg_txpwr_saddr;
+	u8 path;
+	u8 valid_2g_path_bmp = 0;
+#ifdef CONFIG_IEEE80211_BAND_5GHZ
+	u8 valid_5g_path_bmp = 0;
+#endif
+	int result = _FALSE;
+
+	for (path = 0; path < MAX_RF_PATH; path++) {
+		u8 ret = _FALSE;
+
+		if (!HAL_SPEC_CHK_RF_PATH_2G(hal_spec, path) && !HAL_SPEC_CHK_RF_PATH_5G(hal_spec, path))
+			break;
+
+		if (HAL_SPEC_CHK_RF_PATH_2G(hal_spec, path)) {
+			ret = _check_phy_efuse_tx_power_info_valid(pg_data, PG_TXPWR_BASE_BYTE_NUM_2G, pg_offset);
+			if (ret == _TRUE)
+				valid_2g_path_bmp |= BIT(path);
+			else if (ret == EFUSE_POWER_INDEX_INVALID)
+				return _FALSE;
+		}
+		pg_offset += PG_TXPWR_1PATH_BYTE_NUM_2G;
+
+		#ifdef CONFIG_IEEE80211_BAND_5GHZ
+		if (HAL_SPEC_CHK_RF_PATH_5G(hal_spec, path)) {
+			ret = _check_phy_efuse_tx_power_info_valid(pg_data, PG_TXPWR_BASE_BYTE_NUM_5G, pg_offset);
+			if (ret == _TRUE)
+				valid_5g_path_bmp |= BIT(path);
+			else if (ret == EFUSE_POWER_INDEX_INVALID)
+				return _FALSE;
+		}
+		#endif
+		pg_offset += PG_TXPWR_1PATH_BYTE_NUM_5G;
+	}
+
+	if ((hal_chk_band_cap(adapter, BAND_CAP_2G) && valid_2g_path_bmp)
+		#ifdef CONFIG_IEEE80211_BAND_5GHZ
+		|| (hal_chk_band_cap(adapter, BAND_CAP_5G) && valid_5g_path_bmp)
+		#endif
+	)
+		return _TRUE;
+
+	return _FALSE;
+}
+#endif /* CONFIG_EFUSE_CONFIG_FILE */
+
+void hal_load_txpwr_info(
+	_adapter *adapter,
+	TxPowerInfo24G *pwr_info_2g,
+	TxPowerInfo5G *pwr_info_5g,
+	u8 *pg_data
+)
+{
+	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
+	struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter);
+	u8 max_tx_cnt = hal_spec->max_tx_cnt;
+	u8 rfpath, ch_idx, group, tx_idx;
+
+	/* load from pg data (or default value) */
+	hal_load_pg_txpwr_info(adapter, pwr_info_2g, pwr_info_5g, pg_data, _FALSE);
+
+	/* transform to hal_data */
+	for (rfpath = 0; rfpath < MAX_RF_PATH; rfpath++) {
+
+		if (!pwr_info_2g || !HAL_SPEC_CHK_RF_PATH_2G(hal_spec, rfpath))
+			goto bypass_2g;
+
+		/* 2.4G base */
+		for (ch_idx = 0; ch_idx < CENTER_CH_2G_NUM; ch_idx++) {
+			u8 cck_group;
+
+			if (rtw_get_ch_group(ch_idx + 1, &group, &cck_group) != BAND_ON_2_4G)
+				continue;
+
+			hal_data->Index24G_CCK_Base[rfpath][ch_idx] = pwr_info_2g->IndexCCK_Base[rfpath][cck_group];
+			hal_data->Index24G_BW40_Base[rfpath][ch_idx] = pwr_info_2g->IndexBW40_Base[rfpath][group];
+		}
+
+		/* 2.4G diff */
+		for (tx_idx = 0; tx_idx < MAX_TX_COUNT; tx_idx++) {
+			if (tx_idx >= max_tx_cnt)
+				break;
+
+			hal_data->CCK_24G_Diff[rfpath][tx_idx] = pwr_info_2g->CCK_Diff[rfpath][tx_idx] * hal_spec->pg_txgi_diff_factor;
+			hal_data->OFDM_24G_Diff[rfpath][tx_idx] = pwr_info_2g->OFDM_Diff[rfpath][tx_idx] * hal_spec->pg_txgi_diff_factor;
+			hal_data->BW20_24G_Diff[rfpath][tx_idx] = pwr_info_2g->BW20_Diff[rfpath][tx_idx] * hal_spec->pg_txgi_diff_factor;
+			hal_data->BW40_24G_Diff[rfpath][tx_idx] = pwr_info_2g->BW40_Diff[rfpath][tx_idx] * hal_spec->pg_txgi_diff_factor;
+		}
+bypass_2g:
+		;
+
+#ifdef CONFIG_IEEE80211_BAND_5GHZ
+		if (!pwr_info_5g || !HAL_SPEC_CHK_RF_PATH_5G(hal_spec, rfpath))
+			goto bypass_5g;
+
+		/* 5G base */
+		for (ch_idx = 0; ch_idx < CENTER_CH_5G_ALL_NUM; ch_idx++) {
+			if (rtw_get_ch_group(center_ch_5g_all[ch_idx], &group, NULL) != BAND_ON_5G)
+				continue;
+			hal_data->Index5G_BW40_Base[rfpath][ch_idx] = pwr_info_5g->IndexBW40_Base[rfpath][group];
+		}
+
+		for (ch_idx = 0 ; ch_idx < CENTER_CH_5G_80M_NUM; ch_idx++) {
+			u8 upper, lower;
+
+			if (rtw_get_ch_group(center_ch_5g_80m[ch_idx], &group, NULL) != BAND_ON_5G)
+				continue;
+
+			upper = pwr_info_5g->IndexBW40_Base[rfpath][group];
+			lower = pwr_info_5g->IndexBW40_Base[rfpath][group + 1];
+			hal_data->Index5G_BW80_Base[rfpath][ch_idx] = (upper + lower) / 2;
+		}
+
+		/* 5G diff */
+		for (tx_idx = 0; tx_idx < MAX_TX_COUNT; tx_idx++) {
+			if (tx_idx >= max_tx_cnt)
+				break;
+
+			hal_data->OFDM_5G_Diff[rfpath][tx_idx] = pwr_info_5g->OFDM_Diff[rfpath][tx_idx] * hal_spec->pg_txgi_diff_factor;
+			hal_data->BW20_5G_Diff[rfpath][tx_idx] = pwr_info_5g->BW20_Diff[rfpath][tx_idx] * hal_spec->pg_txgi_diff_factor;
+			hal_data->BW40_5G_Diff[rfpath][tx_idx] = pwr_info_5g->BW40_Diff[rfpath][tx_idx] * hal_spec->pg_txgi_diff_factor;
+			hal_data->BW80_5G_Diff[rfpath][tx_idx] = pwr_info_5g->BW80_Diff[rfpath][tx_idx] * hal_spec->pg_txgi_diff_factor;
+		}
+bypass_5g:
+		;
+#endif /* CONFIG_IEEE80211_BAND_5GHZ */
+	}
+}
+
+void dump_hal_txpwr_info_2g(void *sel, _adapter *adapter, u8 rfpath_num, u8 max_tx_cnt)
+{
+	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
+	int path, ch_idx, tx_idx;
+
+	RTW_PRINT_SEL(sel, "2.4G\n");
+	RTW_PRINT_SEL(sel, "CCK-1T base:\n");
+	RTW_PRINT_SEL(sel, "%4s ", "");
+	for (ch_idx = 0; ch_idx < CENTER_CH_2G_NUM; ch_idx++)
+		_RTW_PRINT_SEL(sel, "%2d ", center_ch_2g[ch_idx]);
+	_RTW_PRINT_SEL(sel, "\n");
+	for (path = 0; path < MAX_RF_PATH && path < rfpath_num; path++) {
+		RTW_PRINT_SEL(sel, "[%c]: ", rf_path_char(path));
+		for (ch_idx = 0; ch_idx < CENTER_CH_2G_NUM; ch_idx++)
+			_RTW_PRINT_SEL(sel, "%2u ", hal_data->Index24G_CCK_Base[path][ch_idx]);
+		_RTW_PRINT_SEL(sel, "\n");
+	}
+	RTW_PRINT_SEL(sel, "\n");
+
+	RTW_PRINT_SEL(sel, "CCK diff:\n");
+	RTW_PRINT_SEL(sel, "%4s ", "");
+	for (tx_idx = RF_1TX; tx_idx < MAX_TX_COUNT && tx_idx < max_tx_cnt; tx_idx++)
+		_RTW_PRINT_SEL(sel, "%dT ", tx_idx + 1);
+	_RTW_PRINT_SEL(sel, "\n");
+	for (path = 0; path < MAX_RF_PATH && path < rfpath_num; path++) {
+		RTW_PRINT_SEL(sel, "[%c]: ", rf_path_char(path));
+		for (tx_idx = RF_1TX; tx_idx < MAX_TX_COUNT && tx_idx < max_tx_cnt; tx_idx++)
+			_RTW_PRINT_SEL(sel, "%2d ", hal_data->CCK_24G_Diff[path][tx_idx]);
+		_RTW_PRINT_SEL(sel, "\n");
+	}
+	RTW_PRINT_SEL(sel, "\n");
+
+	RTW_PRINT_SEL(sel, "BW40-1S base:\n");
+	RTW_PRINT_SEL(sel, "%4s ", "");
+	for (ch_idx = 0; ch_idx < CENTER_CH_2G_NUM; ch_idx++)
+		_RTW_PRINT_SEL(sel, "%2d ", center_ch_2g[ch_idx]);
+	_RTW_PRINT_SEL(sel, "\n");
+	for (path = 0; path < MAX_RF_PATH && path < rfpath_num; path++) {
+		RTW_PRINT_SEL(sel, "[%c]: ", rf_path_char(path));
+		for (ch_idx = 0; ch_idx < CENTER_CH_2G_NUM; ch_idx++)
+			_RTW_PRINT_SEL(sel, "%2u ", hal_data->Index24G_BW40_Base[path][ch_idx]);
+		_RTW_PRINT_SEL(sel, "\n");
+	}
+	RTW_PRINT_SEL(sel, "\n");
+
+	RTW_PRINT_SEL(sel, "OFDM diff:\n");
+	RTW_PRINT_SEL(sel, "%4s ", "");
+	for (tx_idx = RF_1TX; tx_idx < MAX_TX_COUNT && tx_idx < max_tx_cnt; tx_idx++)
+		_RTW_PRINT_SEL(sel, "%dT ", tx_idx + 1);
+	_RTW_PRINT_SEL(sel, "\n");
+	for (path = 0; path < MAX_RF_PATH && path < rfpath_num; path++) {
+		RTW_PRINT_SEL(sel, "[%c]: ", rf_path_char(path));
+		for (tx_idx = RF_1TX; tx_idx < MAX_TX_COUNT && tx_idx < max_tx_cnt; tx_idx++)
+			_RTW_PRINT_SEL(sel, "%2d ", hal_data->OFDM_24G_Diff[path][tx_idx]);
+		_RTW_PRINT_SEL(sel, "\n");
+	}
+	RTW_PRINT_SEL(sel, "\n");
+
+	RTW_PRINT_SEL(sel, "BW20 diff:\n");
+	RTW_PRINT_SEL(sel, "%4s ", "");
+	for (tx_idx = RF_1TX; tx_idx < MAX_TX_COUNT && tx_idx < max_tx_cnt; tx_idx++)
+		_RTW_PRINT_SEL(sel, "%dS ", tx_idx + 1);
+	_RTW_PRINT_SEL(sel, "\n");
+	for (path = 0; path < MAX_RF_PATH && path < rfpath_num; path++) {
+		RTW_PRINT_SEL(sel, "[%c]: ", rf_path_char(path));
+		for (tx_idx = RF_1TX; tx_idx < MAX_TX_COUNT && tx_idx < max_tx_cnt; tx_idx++)
+			_RTW_PRINT_SEL(sel, "%2d ", hal_data->BW20_24G_Diff[path][tx_idx]);
+		_RTW_PRINT_SEL(sel, "\n");
+	}
+	RTW_PRINT_SEL(sel, "\n");
+
+	RTW_PRINT_SEL(sel, "BW40 diff:\n");
+	RTW_PRINT_SEL(sel, "%4s ", "");
+	for (tx_idx = RF_1TX; tx_idx < MAX_TX_COUNT && tx_idx < max_tx_cnt; tx_idx++)
+		_RTW_PRINT_SEL(sel, "%dS ", tx_idx + 1);
+	_RTW_PRINT_SEL(sel, "\n");
+	for (path = 0; path < MAX_RF_PATH && path < rfpath_num; path++) {
+		RTW_PRINT_SEL(sel, "[%c]: ", rf_path_char(path));
+		for (tx_idx = RF_1TX; tx_idx < MAX_TX_COUNT && tx_idx < max_tx_cnt; tx_idx++)
+			_RTW_PRINT_SEL(sel, "%2d ", hal_data->BW40_24G_Diff[path][tx_idx]);
+		_RTW_PRINT_SEL(sel, "\n");
+	}
+	RTW_PRINT_SEL(sel, "\n");
+}
+
+void dump_hal_txpwr_info_5g(void *sel, _adapter *adapter, u8 rfpath_num, u8 max_tx_cnt)
+{
+#ifdef CONFIG_IEEE80211_BAND_5GHZ
+	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
+	int path, ch_idx, tx_idx;
+	u8 dump_section = 0;
+	u8 ch_idx_s = 0;
+
+	RTW_PRINT_SEL(sel, "5G\n");
+	RTW_PRINT_SEL(sel, "BW40-1S base:\n");
+	do {
+		#define DUMP_5G_BW40_BASE_SECTION_NUM 3
+		u8 end[DUMP_5G_BW40_BASE_SECTION_NUM] = {64, 144, 177};
+
+		RTW_PRINT_SEL(sel, "%4s ", "");
+		for (ch_idx = ch_idx_s; ch_idx < CENTER_CH_5G_ALL_NUM; ch_idx++) {
+			_RTW_PRINT_SEL(sel, "%3d ", center_ch_5g_all[ch_idx]);
+			if (end[dump_section] == center_ch_5g_all[ch_idx])
+				break;
+		}
+		_RTW_PRINT_SEL(sel, "\n");
+		for (path = 0; path < MAX_RF_PATH && path < rfpath_num; path++) {
+			RTW_PRINT_SEL(sel, "[%c]: ", rf_path_char(path));
+			for (ch_idx = ch_idx_s; ch_idx < CENTER_CH_5G_ALL_NUM; ch_idx++) {
+				_RTW_PRINT_SEL(sel, "%3u ", hal_data->Index5G_BW40_Base[path][ch_idx]);
+				if (end[dump_section] == center_ch_5g_all[ch_idx])
+					break;
+			}
+			_RTW_PRINT_SEL(sel, "\n");
+		}
+		RTW_PRINT_SEL(sel, "\n");
+
+		ch_idx_s = ch_idx + 1;
+		dump_section++;
+		if (dump_section >= DUMP_5G_BW40_BASE_SECTION_NUM)
+			break;
+	} while (1);
+
+	RTW_PRINT_SEL(sel, "BW80-1S base:\n");
+	RTW_PRINT_SEL(sel, "%4s ", "");
+	for (ch_idx = 0; ch_idx < CENTER_CH_5G_80M_NUM; ch_idx++)
+		_RTW_PRINT_SEL(sel, "%3d ", center_ch_5g_80m[ch_idx]);
+	_RTW_PRINT_SEL(sel, "\n");
+	for (path = 0; path < MAX_RF_PATH && path < rfpath_num; path++) {
+		RTW_PRINT_SEL(sel, "[%c]: ", rf_path_char(path));
+		for (ch_idx = 0; ch_idx < CENTER_CH_5G_80M_NUM; ch_idx++)
+			_RTW_PRINT_SEL(sel, "%3u ", hal_data->Index5G_BW80_Base[path][ch_idx]);
+		_RTW_PRINT_SEL(sel, "\n");
+	}
+	RTW_PRINT_SEL(sel, "\n");
+
+	RTW_PRINT_SEL(sel, "OFDM diff:\n");
+	RTW_PRINT_SEL(sel, "%4s ", "");
+	for (tx_idx = RF_1TX; tx_idx < MAX_TX_COUNT && tx_idx < max_tx_cnt; tx_idx++)
+		_RTW_PRINT_SEL(sel, "%dT ", tx_idx + 1);
+	_RTW_PRINT_SEL(sel, "\n");
+	for (path = 0; path < MAX_RF_PATH && path < rfpath_num; path++) {
+		RTW_PRINT_SEL(sel, "[%c]: ", rf_path_char(path));
+		for (tx_idx = RF_1TX; tx_idx < MAX_TX_COUNT && tx_idx < max_tx_cnt; tx_idx++)
+			_RTW_PRINT_SEL(sel, "%2d ", hal_data->OFDM_5G_Diff[path][tx_idx]);
+		_RTW_PRINT_SEL(sel, "\n");
+	}
+	RTW_PRINT_SEL(sel, "\n");
+
+	RTW_PRINT_SEL(sel, "BW20 diff:\n");
+	RTW_PRINT_SEL(sel, "%4s ", "");
+	for (tx_idx = RF_1TX; tx_idx < MAX_TX_COUNT && tx_idx < max_tx_cnt; tx_idx++)
+		_RTW_PRINT_SEL(sel, "%dS ", tx_idx + 1);
+	_RTW_PRINT_SEL(sel, "\n");
+	for (path = 0; path < MAX_RF_PATH && path < rfpath_num; path++) {
+		RTW_PRINT_SEL(sel, "[%c]: ", rf_path_char(path));
+		for (tx_idx = RF_1TX; tx_idx < MAX_TX_COUNT && tx_idx < max_tx_cnt; tx_idx++)
+			_RTW_PRINT_SEL(sel, "%2d ", hal_data->BW20_5G_Diff[path][tx_idx]);
+		_RTW_PRINT_SEL(sel, "\n");
+	}
+	RTW_PRINT_SEL(sel, "\n");
+
+	RTW_PRINT_SEL(sel, "BW40 diff:\n");
+	RTW_PRINT_SEL(sel, "%4s ", "");
+	for (tx_idx = RF_1TX; tx_idx < MAX_TX_COUNT && tx_idx < max_tx_cnt; tx_idx++)
+		_RTW_PRINT_SEL(sel, "%dS ", tx_idx + 1);
+	_RTW_PRINT_SEL(sel, "\n");
+	for (path = 0; path < MAX_RF_PATH && path < rfpath_num; path++) {
+		RTW_PRINT_SEL(sel, "[%c]: ", rf_path_char(path));
+		for (tx_idx = RF_1TX; tx_idx < MAX_TX_COUNT && tx_idx < max_tx_cnt; tx_idx++)
+			_RTW_PRINT_SEL(sel, "%2d ", hal_data->BW40_5G_Diff[path][tx_idx]);
+		_RTW_PRINT_SEL(sel, "\n");
+	}
+	RTW_PRINT_SEL(sel, "\n");
+
+	RTW_PRINT_SEL(sel, "BW80 diff:\n");
+	RTW_PRINT_SEL(sel, "%4s ", "");
+	for (tx_idx = RF_1TX; tx_idx < MAX_TX_COUNT && tx_idx < max_tx_cnt; tx_idx++)
+		_RTW_PRINT_SEL(sel, "%dS ", tx_idx + 1);
+	_RTW_PRINT_SEL(sel, "\n");
+	for (path = 0; path < MAX_RF_PATH && path < rfpath_num; path++) {
+		RTW_PRINT_SEL(sel, "[%c]: ", rf_path_char(path));
+		for (tx_idx = RF_1TX; tx_idx < MAX_TX_COUNT && tx_idx < max_tx_cnt; tx_idx++)
+			_RTW_PRINT_SEL(sel, "%2d ", hal_data->BW80_5G_Diff[path][tx_idx]);
+		_RTW_PRINT_SEL(sel, "\n");
+	}
+	RTW_PRINT_SEL(sel, "\n");
+#endif /* CONFIG_IEEE80211_BAND_5GHZ */
+}
+
+/*
+* rtw_regsty_get_target_tx_power -
+*
+* Return dBm or -1 for undefined
+*/
+s8 rtw_regsty_get_target_tx_power(
+	IN	PADAPTER		Adapter,
+	IN	u8				Band,
+	IN	u8				RfPath,
+	IN	RATE_SECTION	RateSection
+)
+{
+	struct registry_priv *regsty = adapter_to_regsty(Adapter);
+	s8 value = 0;
+
+	if (RfPath > RF_PATH_D) {
+		RTW_PRINT("%s invalid RfPath:%d\n", __func__, RfPath);
+		return -1;
+	}
+
+	if (Band != BAND_ON_2_4G
+		#ifdef CONFIG_IEEE80211_BAND_5GHZ
+		&& Band != BAND_ON_5G
+		#endif
+	) {
+		RTW_PRINT("%s invalid Band:%d\n", __func__, Band);
+		return -1;
+	}
+
+	if (RateSection >= RATE_SECTION_NUM
+		#ifdef CONFIG_IEEE80211_BAND_5GHZ
+		|| (Band == BAND_ON_5G && RateSection == CCK)
+		#endif
+	) {
+		RTW_PRINT("%s invalid RateSection:%d in Band:%d, RfPath:%d\n", __func__
+			, RateSection, Band, RfPath);
+		return -1;
+	}
+
+	if (Band == BAND_ON_2_4G)
+		value = regsty->target_tx_pwr_2g[RfPath][RateSection];
+#ifdef CONFIG_IEEE80211_BAND_5GHZ
+	else /* BAND_ON_5G */
+		value = regsty->target_tx_pwr_5g[RfPath][RateSection - 1];
+#endif
+
+	return value;
+}
+
+bool rtw_regsty_chk_target_tx_power_valid(_adapter *adapter)
+{
+	struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter);
+	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
+	int path, tx_num, band, rs;
+	s8 target;
+
+	for (band = BAND_ON_2_4G; band <= BAND_ON_5G; band++) {
+		if (!hal_is_band_support(adapter, band))
+			continue;
+
+		for (path = 0; path < RF_PATH_MAX; path++) {
+			if (!HAL_SPEC_CHK_RF_PATH(hal_spec, band, path))
+				break;
+
+			for (rs = 0; rs < RATE_SECTION_NUM; rs++) {
+				tx_num = rate_section_to_tx_num(rs);
+				if (tx_num >= hal_spec->tx_nss_num)
+					continue;
+
+				if (band == BAND_ON_5G && IS_CCK_RATE_SECTION(rs))
+					continue;
+
+				if (IS_VHT_RATE_SECTION(rs) && !IS_HARDWARE_TYPE_JAGUAR_AND_JAGUAR2(adapter))
+					continue;
+
+				target = rtw_regsty_get_target_tx_power(adapter, band, path, rs);
+				if (target == -1) {
+					RTW_PRINT("%s return _FALSE for band:%d, path:%d, rs:%d, t:%d\n", __func__, band, path, rs, target);
+					return _FALSE;
+				}
+			}
+		}
+	}
+
+	return _TRUE;
+}
+
+/*
+* PHY_GetTxPowerByRateBase -
+*
+* Return value in unit of TX Gain Index
+*/
+u8
+PHY_GetTxPowerByRateBase(
+	IN	PADAPTER		Adapter,
+	IN	u8				Band,
+	IN	u8				RfPath,
+	IN	RATE_SECTION	RateSection
+)
+{
+	HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
+	u8 value = 0;
+
+	if (RfPath > RF_PATH_D) {
+		RTW_PRINT("%s invalid RfPath:%d\n", __func__, RfPath);
+		return 0;
+	}
+
+	if (Band != BAND_ON_2_4G && Band != BAND_ON_5G) {
+		RTW_PRINT("%s invalid Band:%d\n", __func__, Band);
+		return 0;
+	}
+
+	if (RateSection >= RATE_SECTION_NUM
+		|| (Band == BAND_ON_5G && RateSection == CCK)
+	) {
+		RTW_PRINT("%s invalid RateSection:%d in Band:%d, RfPath:%d\n", __func__
+			, RateSection, Band, RfPath);
+		return 0;
+	}
+
+	if (Band == BAND_ON_2_4G)
+		value = pHalData->TxPwrByRateBase2_4G[RfPath][RateSection];
+	else /* BAND_ON_5G */
+		value = pHalData->TxPwrByRateBase5G[RfPath][RateSection - 1];
+
+	return value;
+}
+
+VOID
+phy_SetTxPowerByRateBase(
+	IN	PADAPTER		Adapter,
+	IN	u8				Band,
+	IN	u8				RfPath,
+	IN	RATE_SECTION	RateSection,
+	IN	u8				Value
+)
+{
+	HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
+
+	if (RfPath > RF_PATH_D) {
+		RTW_PRINT("%s invalid RfPath:%d\n", __func__, RfPath);
+		return;
+	}
+
+	if (Band != BAND_ON_2_4G && Band != BAND_ON_5G) {
+		RTW_PRINT("%s invalid Band:%d\n", __func__, Band);
+		return;
+	}
+
+	if (RateSection >= RATE_SECTION_NUM
+		|| (Band == BAND_ON_5G && RateSection == CCK)
+	) {
+		RTW_PRINT("%s invalid RateSection:%d in %sG, RfPath:%d\n", __func__
+			, RateSection, (Band == BAND_ON_2_4G) ? "2.4" : "5", RfPath);
+		return;
+	}
+
+	if (Band == BAND_ON_2_4G)
+		pHalData->TxPwrByRateBase2_4G[RfPath][RateSection] = Value;
+	else /* BAND_ON_5G */
+		pHalData->TxPwrByRateBase5G[RfPath][RateSection - 1] = Value;
+}
+
+static inline BOOLEAN phy_is_txpwr_by_rate_undefined_of_band_path(_adapter *adapter, u8 band, u8 path)
+{
+	struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter);
+	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
+	u8 rate_idx = 0;
+
+	for (rate_idx = 0; rate_idx < TX_PWR_BY_RATE_NUM_RATE; rate_idx++) {
+		if (hal_data->TxPwrByRateOffset[band][path][rate_idx] != 0)
+			goto exit;
+	}
+
+exit:
+	return rate_idx >= TX_PWR_BY_RATE_NUM_RATE ? _TRUE : _FALSE;
+}
+
+static inline void phy_txpwr_by_rate_duplicate_band_path(_adapter *adapter, u8 band, u8 s_path, u8 t_path)
+{
+	struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter);
+	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
+	u8 rate_idx = 0;
+
+	for (rate_idx = 0; rate_idx < TX_PWR_BY_RATE_NUM_RATE; rate_idx++)
+		hal_data->TxPwrByRateOffset[band][t_path][rate_idx] = hal_data->TxPwrByRateOffset[band][s_path][rate_idx];
+}
+
+static void phy_txpwr_by_rate_chk_for_path_dup(_adapter *adapter)
+{
+	struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter);
+	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
+	u8 band, path;
+	s8 src_path;
+
+	for (band = BAND_ON_2_4G; band <= BAND_ON_5G; band++)
+		for (path = RF_PATH_A; path < RF_PATH_MAX; path++)
+			hal_data->txpwr_by_rate_undefined_band_path[band][path] = 0;
+
+	for (band = BAND_ON_2_4G; band <= BAND_ON_5G; band++) {
+		if (!hal_is_band_support(adapter, band))
+			continue;
+
+		for (path = RF_PATH_A; path < RF_PATH_MAX; path++) {
+			if (!HAL_SPEC_CHK_RF_PATH(hal_spec, band, path))
+				continue;
+
+			if (phy_is_txpwr_by_rate_undefined_of_band_path(adapter, band, path))
+				hal_data->txpwr_by_rate_undefined_band_path[band][path] = 1;
+		}
+	}
+
+	for (band = BAND_ON_2_4G; band <= BAND_ON_5G; band++) {
+		if (!hal_is_band_support(adapter, band))
+			continue;
+
+		src_path = -1;
+		for (path = RF_PATH_A; path < RF_PATH_MAX; path++) {
+			if (!HAL_SPEC_CHK_RF_PATH(hal_spec, band, path))
+				continue;
+
+			/* find src */
+			if (src_path == -1 && hal_data->txpwr_by_rate_undefined_band_path[band][path] == 0)
+				src_path = path;
+		}
+
+		if (src_path == -1) {
+			RTW_ERR("%s all power by rate undefined\n", __func__);
+			continue;
+		}
+
+		for (path = RF_PATH_A; path < RF_PATH_MAX; path++) {
+			if (!HAL_SPEC_CHK_RF_PATH(hal_spec, band, path))
+				continue;
+
+			/* duplicate src to undefined one */
+			if (hal_data->txpwr_by_rate_undefined_band_path[band][path] == 1) {
+				RTW_INFO("%s duplicate %s [%c] to [%c]\n", __func__
+					, band_str(band), rf_path_char(src_path), rf_path_char(path));
+				phy_txpwr_by_rate_duplicate_band_path(adapter, band, src_path, path);
+			}
+		}
+	}
+}
+
+VOID
+phy_StoreTxPowerByRateBase(
+	IN	PADAPTER	pAdapter
+)
+{
+	struct hal_spec_t *hal_spec = GET_HAL_SPEC(pAdapter);
+	struct registry_priv *regsty = adapter_to_regsty(pAdapter);
+
+	u8 rate_sec_base[RATE_SECTION_NUM] = {
+		MGN_11M,
+		MGN_54M,
+		MGN_MCS7,
+		MGN_MCS15,
+		MGN_MCS23,
+		MGN_MCS31,
+		MGN_VHT1SS_MCS7,
+		MGN_VHT2SS_MCS7,
+		MGN_VHT3SS_MCS7,
+		MGN_VHT4SS_MCS7,
+	};
+
+	u8 band, path, rs, tx_num, base, index;
+
+	for (band = BAND_ON_2_4G; band <= BAND_ON_5G; band++) {
+		if (!hal_is_band_support(pAdapter, band))
+			continue;
+
+		for (path = RF_PATH_A; path < RF_PATH_MAX; path++) {
+			if (!HAL_SPEC_CHK_RF_PATH(hal_spec, band, path))
+				break;
+
+			for (rs = 0; rs < RATE_SECTION_NUM; rs++) {
+				tx_num = rate_section_to_tx_num(rs);
+				if (tx_num >= hal_spec->tx_nss_num)
+					continue;
+
+				if (band == BAND_ON_5G && IS_CCK_RATE_SECTION(rs))
+					continue;
+
+				if (IS_VHT_RATE_SECTION(rs) && !IS_HARDWARE_TYPE_JAGUAR_AND_JAGUAR2(pAdapter))
+					continue;
+
+				if (regsty->target_tx_pwr_valid == _TRUE)
+					base = hal_spec->txgi_pdbm * rtw_regsty_get_target_tx_power(pAdapter, band, path, rs);
+				else
+					base = _PHY_GetTxPowerByRate(pAdapter, band, path, rate_sec_base[rs]);
+				phy_SetTxPowerByRateBase(pAdapter, band, path, rs, base);
+			}
+		}
+	}
+}
+
+static u8 get_val_from_dhex(u32 dhex, u8 i)
+{
+	return (((dhex >> (i * 8 + 4)) & 0xF)) * 10 + ((dhex >> (i * 8)) & 0xF);
+}
+
+static u8 get_val_from_hex(u32 hex, u8 i)
+{
+	return (hex >> (i * 8)) & 0xFF;
+}
+
+VOID
+PHY_GetRateValuesOfTxPowerByRate(
+	IN	PADAPTER pAdapter,
+	IN	u32 RegAddr,
+	IN	u32 BitMask,
+	IN	u32 Value,
+	OUT	u8 *Rate,
+	OUT	s8 *PwrByRateVal,
+	OUT	u8 *RateNum
+)
+{
+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(pAdapter);
+	struct hal_spec_t *hal_spec = GET_HAL_SPEC(pAdapter);
+	struct dm_struct		*pDM_Odm = &pHalData->odmpriv;
+	u8				index = 0, i = 0;
+	u8 (*get_val)(u32, u8);
+
+	if (hal_spec->txgi_pdbm == 2)
+		get_val = get_val_from_dhex;
+	else
+		get_val = get_val_from_hex;
+
+	switch (RegAddr) {
+	case rTxAGC_A_Rate18_06:
+	case rTxAGC_B_Rate18_06:
+		Rate[0] = MGN_6M;
+		Rate[1] = MGN_9M;
+		Rate[2] = MGN_12M;
+		Rate[3] = MGN_18M;
+		for (i = 0; i < 4; ++i)
+			PwrByRateVal[i] = (s8)get_val(Value, i);
+		*RateNum = 4;
+		break;
+
+	case rTxAGC_A_Rate54_24:
+	case rTxAGC_B_Rate54_24:
+		Rate[0] = MGN_24M;
+		Rate[1] = MGN_36M;
+		Rate[2] = MGN_48M;
+		Rate[3] = MGN_54M;
+		for (i = 0; i < 4; ++i)
+			PwrByRateVal[i] = (s8)get_val(Value, i);
+		*RateNum = 4;
+		break;
+
+	case rTxAGC_A_CCK1_Mcs32:
+		Rate[0] = MGN_1M;
+		PwrByRateVal[0] = (s8)get_val(Value, 1);
+		*RateNum = 1;
+		break;
+
+	case rTxAGC_B_CCK11_A_CCK2_11:
+		if (BitMask == 0xffffff00) {
+			Rate[0] = MGN_2M;
+			Rate[1] = MGN_5_5M;
+			Rate[2] = MGN_11M;
+			for (i = 1; i < 4; ++i)
+				PwrByRateVal[i - 1] = (s8)get_val(Value, i);
+			*RateNum = 3;
+		} else if (BitMask == 0x000000ff) {
+			Rate[0] = MGN_11M;
+			PwrByRateVal[0] = (s8)get_val(Value, 0);
+			*RateNum = 1;
+		}
+		break;
+
+	case rTxAGC_A_Mcs03_Mcs00:
+	case rTxAGC_B_Mcs03_Mcs00:
+		Rate[0] = MGN_MCS0;
+		Rate[1] = MGN_MCS1;
+		Rate[2] = MGN_MCS2;
+		Rate[3] = MGN_MCS3;
+		for (i = 0; i < 4; ++i)
+			PwrByRateVal[i] = (s8)get_val(Value, i);
+		*RateNum = 4;
+		break;
+
+	case rTxAGC_A_Mcs07_Mcs04:
+	case rTxAGC_B_Mcs07_Mcs04:
+		Rate[0] = MGN_MCS4;
+		Rate[1] = MGN_MCS5;
+		Rate[2] = MGN_MCS6;
+		Rate[3] = MGN_MCS7;
+		for (i = 0; i < 4; ++i)
+			PwrByRateVal[i] = (s8)get_val(Value, i);
+		*RateNum = 4;
+		break;
+
+	case rTxAGC_A_Mcs11_Mcs08:
+	case rTxAGC_B_Mcs11_Mcs08:
+		Rate[0] = MGN_MCS8;
+		Rate[1] = MGN_MCS9;
+		Rate[2] = MGN_MCS10;
+		Rate[3] = MGN_MCS11;
+		for (i = 0; i < 4; ++i)
+			PwrByRateVal[i] = (s8)get_val(Value, i);
+		*RateNum = 4;
+		break;
+
+	case rTxAGC_A_Mcs15_Mcs12:
+	case rTxAGC_B_Mcs15_Mcs12:
+		Rate[0] = MGN_MCS12;
+		Rate[1] = MGN_MCS13;
+		Rate[2] = MGN_MCS14;
+		Rate[3] = MGN_MCS15;
+		for (i = 0; i < 4; ++i)
+			PwrByRateVal[i] = (s8)get_val(Value, i);
+		*RateNum = 4;
+		break;
+
+	case rTxAGC_B_CCK1_55_Mcs32:
+		Rate[0] = MGN_1M;
+		Rate[1] = MGN_2M;
+		Rate[2] = MGN_5_5M;
+		for (i = 1; i < 4; ++i)
+			PwrByRateVal[i - 1] = (s8)get_val(Value, i);
+		*RateNum = 3;
+		break;
+
+	case 0xC20:
+	case 0xE20:
+	case 0x1820:
+	case 0x1a20:
+		Rate[0] = MGN_1M;
+		Rate[1] = MGN_2M;
+		Rate[2] = MGN_5_5M;
+		Rate[3] = MGN_11M;
+		for (i = 0; i < 4; ++i)
+			PwrByRateVal[i] = (s8)get_val(Value, i);
+		*RateNum = 4;
+		break;
+
+	case 0xC24:
+	case 0xE24:
+	case 0x1824:
+	case 0x1a24:
+		Rate[0] = MGN_6M;
+		Rate[1] = MGN_9M;
+		Rate[2] = MGN_12M;
+		Rate[3] = MGN_18M;
+		for (i = 0; i < 4; ++i)
+			PwrByRateVal[i] = (s8)get_val(Value, i);
+		*RateNum = 4;
+		break;
+
+	case 0xC28:
+	case 0xE28:
+	case 0x1828:
+	case 0x1a28:
+		Rate[0] = MGN_24M;
+		Rate[1] = MGN_36M;
+		Rate[2] = MGN_48M;
+		Rate[3] = MGN_54M;
+		for (i = 0; i < 4; ++i)
+			PwrByRateVal[i] = (s8)get_val(Value, i);
+		*RateNum = 4;
+		break;
+
+	case 0xC2C:
+	case 0xE2C:
+	case 0x182C:
+	case 0x1a2C:
+		Rate[0] = MGN_MCS0;
+		Rate[1] = MGN_MCS1;
+		Rate[2] = MGN_MCS2;
+		Rate[3] = MGN_MCS3;
+		for (i = 0; i < 4; ++i)
+			PwrByRateVal[i] = (s8)get_val(Value, i);
+		*RateNum = 4;
+		break;
+
+	case 0xC30:
+	case 0xE30:
+	case 0x1830:
+	case 0x1a30:
+		Rate[0] = MGN_MCS4;
+		Rate[1] = MGN_MCS5;
+		Rate[2] = MGN_MCS6;
+		Rate[3] = MGN_MCS7;
+		for (i = 0; i < 4; ++i)
+			PwrByRateVal[i] = (s8)get_val(Value, i);
+		*RateNum = 4;
+		break;
+
+	case 0xC34:
+	case 0xE34:
+	case 0x1834:
+	case 0x1a34:
+		Rate[0] = MGN_MCS8;
+		Rate[1] = MGN_MCS9;
+		Rate[2] = MGN_MCS10;
+		Rate[3] = MGN_MCS11;
+		for (i = 0; i < 4; ++i)
+			PwrByRateVal[i] = (s8)get_val(Value, i);
+		*RateNum = 4;
+		break;
+
+	case 0xC38:
+	case 0xE38:
+	case 0x1838:
+	case 0x1a38:
+		Rate[0] = MGN_MCS12;
+		Rate[1] = MGN_MCS13;
+		Rate[2] = MGN_MCS14;
+		Rate[3] = MGN_MCS15;
+		for (i = 0; i < 4; ++i)
+			PwrByRateVal[i] = (s8)get_val(Value, i);
+		*RateNum = 4;
+		break;
+
+	case 0xC3C:
+	case 0xE3C:
+	case 0x183C:
+	case 0x1a3C:
+		Rate[0] = MGN_VHT1SS_MCS0;
+		Rate[1] = MGN_VHT1SS_MCS1;
+		Rate[2] = MGN_VHT1SS_MCS2;
+		Rate[3] = MGN_VHT1SS_MCS3;
+		for (i = 0; i < 4; ++i)
+			PwrByRateVal[i] = (s8)get_val(Value, i);
+		*RateNum = 4;
+		break;
+
+	case 0xC40:
+	case 0xE40:
+	case 0x1840:
+	case 0x1a40:
+		Rate[0] = MGN_VHT1SS_MCS4;
+		Rate[1] = MGN_VHT1SS_MCS5;
+		Rate[2] = MGN_VHT1SS_MCS6;
+		Rate[3] = MGN_VHT1SS_MCS7;
+		for (i = 0; i < 4; ++i)
+			PwrByRateVal[i] = (s8)get_val(Value, i);
+		*RateNum = 4;
+		break;
+
+	case 0xC44:
+	case 0xE44:
+	case 0x1844:
+	case 0x1a44:
+		Rate[0] = MGN_VHT1SS_MCS8;
+		Rate[1] = MGN_VHT1SS_MCS9;
+		Rate[2] = MGN_VHT2SS_MCS0;
+		Rate[3] = MGN_VHT2SS_MCS1;
+		for (i = 0; i < 4; ++i)
+			PwrByRateVal[i] = (s8)get_val(Value, i);
+		*RateNum = 4;
+		break;
+
+	case 0xC48:
+	case 0xE48:
+	case 0x1848:
+	case 0x1a48:
+		Rate[0] = MGN_VHT2SS_MCS2;
+		Rate[1] = MGN_VHT2SS_MCS3;
+		Rate[2] = MGN_VHT2SS_MCS4;
+		Rate[3] = MGN_VHT2SS_MCS5;
+		for (i = 0; i < 4; ++i)
+			PwrByRateVal[i] = (s8)get_val(Value, i);
+		*RateNum = 4;
+		break;
+
+	case 0xC4C:
+	case 0xE4C:
+	case 0x184C:
+	case 0x1a4C:
+		Rate[0] = MGN_VHT2SS_MCS6;
+		Rate[1] = MGN_VHT2SS_MCS7;
+		Rate[2] = MGN_VHT2SS_MCS8;
+		Rate[3] = MGN_VHT2SS_MCS9;
+		for (i = 0; i < 4; ++i)
+			PwrByRateVal[i] = (s8)get_val(Value, i);
+		*RateNum = 4;
+		break;
+
+	case 0xCD8:
+	case 0xED8:
+	case 0x18D8:
+	case 0x1aD8:
+		Rate[0] = MGN_MCS16;
+		Rate[1] = MGN_MCS17;
+		Rate[2] = MGN_MCS18;
+		Rate[3] = MGN_MCS19;
+		for (i = 0; i < 4; ++i)
+			PwrByRateVal[i] = (s8)get_val(Value, i);
+		*RateNum = 4;
+		break;
+
+	case 0xCDC:
+	case 0xEDC:
+	case 0x18DC:
+	case 0x1aDC:
+		Rate[0] = MGN_MCS20;
+		Rate[1] = MGN_MCS21;
+		Rate[2] = MGN_MCS22;
+		Rate[3] = MGN_MCS23;
+		for (i = 0; i < 4; ++i)
+			PwrByRateVal[i] = (s8)get_val(Value, i);
+		*RateNum = 4;
+		break;
+
+	case 0xCE0:
+	case 0xEE0:
+	case 0x18E0:
+	case 0x1aE0:
+		Rate[0] = MGN_VHT3SS_MCS0;
+		Rate[1] = MGN_VHT3SS_MCS1;
+		Rate[2] = MGN_VHT3SS_MCS2;
+		Rate[3] = MGN_VHT3SS_MCS3;
+		for (i = 0; i < 4; ++i)
+			PwrByRateVal[i] = (s8)get_val(Value, i);
+		*RateNum = 4;
+		break;
+
+	case 0xCE4:
+	case 0xEE4:
+	case 0x18E4:
+	case 0x1aE4:
+		Rate[0] = MGN_VHT3SS_MCS4;
+		Rate[1] = MGN_VHT3SS_MCS5;
+		Rate[2] = MGN_VHT3SS_MCS6;
+		Rate[3] = MGN_VHT3SS_MCS7;
+		for (i = 0; i < 4; ++i)
+			PwrByRateVal[i] = (s8)get_val(Value, i);
+		*RateNum = 4;
+		break;
+
+	case 0xCE8:
+	case 0xEE8:
+	case 0x18E8:
+	case 0x1aE8:
+		Rate[0] = MGN_VHT3SS_MCS8;
+		Rate[1] = MGN_VHT3SS_MCS9;
+		for (i = 0; i < 2; ++i)
+			PwrByRateVal[i] = (s8)get_val(Value, i);
+		*RateNum = 2;
+		break;
+
+	default:
+		RTW_PRINT("Invalid RegAddr 0x%x in %s()\n", RegAddr, __func__);
+		break;
+	};
+}
+
+void
+PHY_StoreTxPowerByRateNew(
+	IN	PADAPTER	pAdapter,
+	IN	u32			Band,
+	IN	u32			RfPath,
+	IN	u32			RegAddr,
+	IN	u32			BitMask,
+	IN	u32			Data
+)
+{
+	HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
+	u8	i = 0, rates[4] = {0}, rateNum = 0;
+	s8	PwrByRateVal[4] = {0};
+
+	PHY_GetRateValuesOfTxPowerByRate(pAdapter, RegAddr, BitMask, Data, rates, PwrByRateVal, &rateNum);
+
+	if (Band != BAND_ON_2_4G && Band != BAND_ON_5G) {
+		RTW_PRINT("Invalid Band %d\n", Band);
+		return;
+	}
+
+	if (RfPath > RF_PATH_D) {
+		RTW_PRINT("Invalid RfPath %d\n", RfPath);
+		return;
+	}
+
+	for (i = 0; i < rateNum; ++i) {
+		u8 rate_idx = PHY_GetRateIndexOfTxPowerByRate(rates[i]);
+
+		pHalData->TxPwrByRateOffset[Band][RfPath][rate_idx] = PwrByRateVal[i];
+	}
+}
+
+VOID
+PHY_InitTxPowerByRate(
+	IN	PADAPTER	pAdapter
+)
+{
+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(pAdapter);
+	u8	band = 0, rfPath = 0, rate = 0, i = 0, j = 0;
+
+	for (band = BAND_ON_2_4G; band <= BAND_ON_5G; ++band)
+		for (rfPath = 0; rfPath < TX_PWR_BY_RATE_NUM_RF; ++rfPath)
+				for (rate = 0; rate < TX_PWR_BY_RATE_NUM_RATE; ++rate)
+					pHalData->TxPwrByRateOffset[band][rfPath][rate] = 0;
+}
+
+VOID
+phy_store_tx_power_by_rate(
+	IN	PADAPTER	pAdapter,
+	IN	u32			Band,
+	IN	u32			RfPath,
+	IN	u32			TxNum,
+	IN	u32			RegAddr,
+	IN	u32			BitMask,
+	IN	u32			Data
+)
+{
+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(pAdapter);
+	struct dm_struct		*pDM_Odm = &pHalData->odmpriv;
+
+	if (pDM_Odm->phy_reg_pg_version > 0)
+		PHY_StoreTxPowerByRateNew(pAdapter, Band, RfPath, RegAddr, BitMask, Data);
+	else
+		RTW_INFO("Invalid PHY_REG_PG.txt version %d\n",  pDM_Odm->phy_reg_pg_version);
+
+}
+
+VOID
+phy_ConvertTxPowerByRateInDbmToRelativeValues(
+	IN	PADAPTER	pAdapter
+)
+{
+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(pAdapter);
+	u8			base = 0, i = 0, value = 0,
+				band = 0, path = 0, index = 0,
+				startIndex = 0, endIndex = 0;
+	u8	cckRates[4] = {MGN_1M, MGN_2M, MGN_5_5M, MGN_11M},
+		ofdmRates[8] = {MGN_6M, MGN_9M, MGN_12M, MGN_18M, MGN_24M, MGN_36M, MGN_48M, MGN_54M},
+		mcs0_7Rates[8] = {MGN_MCS0, MGN_MCS1, MGN_MCS2, MGN_MCS3, MGN_MCS4, MGN_MCS5, MGN_MCS6, MGN_MCS7},
+		mcs8_15Rates[8] = {MGN_MCS8, MGN_MCS9, MGN_MCS10, MGN_MCS11, MGN_MCS12, MGN_MCS13, MGN_MCS14, MGN_MCS15},
+		mcs16_23Rates[8] = {MGN_MCS16, MGN_MCS17, MGN_MCS18, MGN_MCS19, MGN_MCS20, MGN_MCS21, MGN_MCS22, MGN_MCS23},
+		vht1ssRates[10] = {MGN_VHT1SS_MCS0, MGN_VHT1SS_MCS1, MGN_VHT1SS_MCS2, MGN_VHT1SS_MCS3, MGN_VHT1SS_MCS4,
+			MGN_VHT1SS_MCS5, MGN_VHT1SS_MCS6, MGN_VHT1SS_MCS7, MGN_VHT1SS_MCS8, MGN_VHT1SS_MCS9},
+		vht2ssRates[10] = {MGN_VHT2SS_MCS0, MGN_VHT2SS_MCS1, MGN_VHT2SS_MCS2, MGN_VHT2SS_MCS3, MGN_VHT2SS_MCS4,
+			MGN_VHT2SS_MCS5, MGN_VHT2SS_MCS6, MGN_VHT2SS_MCS7, MGN_VHT2SS_MCS8, MGN_VHT2SS_MCS9},
+		vht3ssRates[10] = {MGN_VHT3SS_MCS0, MGN_VHT3SS_MCS1, MGN_VHT3SS_MCS2, MGN_VHT3SS_MCS3, MGN_VHT3SS_MCS4,
+			MGN_VHT3SS_MCS5, MGN_VHT3SS_MCS6, MGN_VHT3SS_MCS7, MGN_VHT3SS_MCS8, MGN_VHT3SS_MCS9};
+
+	/* RTW_INFO("===>PHY_ConvertTxPowerByRateInDbmToRelativeValues()\n" ); */
+
+	for (band = BAND_ON_2_4G; band <= BAND_ON_5G; ++band) {
+		for (path = RF_PATH_A; path <= RF_PATH_D; ++path) {
+			/* CCK */
+			if (band == BAND_ON_2_4G) {
+				base = PHY_GetTxPowerByRateBase(pAdapter, band, path, CCK);
+				for (i = 0; i < sizeof(cckRates); ++i) {
+					value = PHY_GetTxPowerByRate(pAdapter, band, path, cckRates[i]);
+					PHY_SetTxPowerByRate(pAdapter, band, path, cckRates[i], value - base);
+				}
+			}
+
+			/* OFDM */
+			base = PHY_GetTxPowerByRateBase(pAdapter, band, path, OFDM);
+			for (i = 0; i < sizeof(ofdmRates); ++i) {
+				value = PHY_GetTxPowerByRate(pAdapter, band, path, ofdmRates[i]);
+				PHY_SetTxPowerByRate(pAdapter, band, path, ofdmRates[i], value - base);
+			}
+
+			/* HT MCS0~7 */
+			base = PHY_GetTxPowerByRateBase(pAdapter, band, path, HT_1SS);
+			for (i = 0; i < sizeof(mcs0_7Rates); ++i) {
+				value = PHY_GetTxPowerByRate(pAdapter, band, path, mcs0_7Rates[i]);
+				PHY_SetTxPowerByRate(pAdapter, band, path, mcs0_7Rates[i], value - base);
+			}
+
+			/* HT MCS8~15 */
+			base = PHY_GetTxPowerByRateBase(pAdapter, band, path, HT_2SS);
+			for (i = 0; i < sizeof(mcs8_15Rates); ++i) {
+				value = PHY_GetTxPowerByRate(pAdapter, band, path, mcs8_15Rates[i]);
+				PHY_SetTxPowerByRate(pAdapter, band, path, mcs8_15Rates[i], value - base);
+			}
+
+			/* HT MCS16~23 */
+			base = PHY_GetTxPowerByRateBase(pAdapter, band, path, HT_3SS);
+			for (i = 0; i < sizeof(mcs16_23Rates); ++i) {
+				value = PHY_GetTxPowerByRate(pAdapter, band, path, mcs16_23Rates[i]);
+				PHY_SetTxPowerByRate(pAdapter, band, path, mcs16_23Rates[i], value - base);
+			}
+
+			/* VHT 1SS */
+			base = PHY_GetTxPowerByRateBase(pAdapter, band, path, VHT_1SS);
+			for (i = 0; i < sizeof(vht1ssRates); ++i) {
+				value = PHY_GetTxPowerByRate(pAdapter, band, path, vht1ssRates[i]);
+				PHY_SetTxPowerByRate(pAdapter, band, path, vht1ssRates[i], value - base);
+			}
+
+			/* VHT 2SS */
+			base = PHY_GetTxPowerByRateBase(pAdapter, band, path, VHT_2SS);
+			for (i = 0; i < sizeof(vht2ssRates); ++i) {
+				value = PHY_GetTxPowerByRate(pAdapter, band, path, vht2ssRates[i]);
+				PHY_SetTxPowerByRate(pAdapter, band, path, vht2ssRates[i], value - base);
+			}
+
+			/* VHT 3SS */
+			base = PHY_GetTxPowerByRateBase(pAdapter, band, path, VHT_3SS);
+			for (i = 0; i < sizeof(vht3ssRates); ++i) {
+				value = PHY_GetTxPowerByRate(pAdapter, band, path, vht3ssRates[i]);
+				PHY_SetTxPowerByRate(pAdapter, band, path, vht3ssRates[i], value - base);
+			}
+		}
+	}
+
+	/* RTW_INFO("<===PHY_ConvertTxPowerByRateInDbmToRelativeValues()\n" ); */
+}
+
+/*
+  * This function must be called if the value in the PHY_REG_PG.txt(or header)
+  * is exact dBm values
+  */
+VOID
+PHY_TxPowerByRateConfiguration(
+	IN  PADAPTER			pAdapter
+)
+{
+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(pAdapter);
+
+	phy_txpwr_by_rate_chk_for_path_dup(pAdapter);
+	phy_StoreTxPowerByRateBase(pAdapter);
+	phy_ConvertTxPowerByRateInDbmToRelativeValues(pAdapter);
+}
+
+VOID
+phy_set_tx_power_index_by_rate_section(
+	IN	PADAPTER		pAdapter,
+	IN	enum rf_path		RFPath,
+	IN	u8				Channel,
+	IN	u8				RateSection
+)
+{
+	PHAL_DATA_TYPE	pHalData = GET_HAL_DATA(pAdapter);
+
+	if (RateSection >= RATE_SECTION_NUM) {
+		RTW_INFO("Invalid RateSection %d in %s", RateSection, __func__);
+		rtw_warn_on(1);
+		goto exit;
+	}
+
+	if (RateSection == CCK && pHalData->current_band_type != BAND_ON_2_4G)
+		goto exit;
+
+	PHY_SetTxPowerIndexByRateArray(pAdapter, RFPath, pHalData->current_channel_bw, Channel,
+		rates_by_sections[RateSection].rates, rates_by_sections[RateSection].rate_num);
+
+exit:
+	return;
+}
+
+BOOLEAN
+phy_GetChnlIndex(
+	IN	u8	Channel,
+	OUT u8	*ChannelIdx
+)
+{
+	u8  i = 0;
+	BOOLEAN bIn24G = _TRUE;
+
+	if (Channel <= 14) {
+		bIn24G = _TRUE;
+		*ChannelIdx = Channel - 1;
+	} else {
+		bIn24G = _FALSE;
+
+		for (i = 0; i < CENTER_CH_5G_ALL_NUM; ++i) {
+			if (center_ch_5g_all[i] == Channel) {
+				*ChannelIdx = i;
+				return bIn24G;
+			}
+		}
+	}
+
+	return bIn24G;
+}
+
+u8
+PHY_GetTxPowerIndexBase(
+	IN	PADAPTER		pAdapter,
+	IN	enum rf_path		RFPath,
+	IN	u8				Rate,
+	u8 ntx_idx,
+	IN	enum channel_width	BandWidth,
+	IN	u8				Channel,
+	OUT PBOOLEAN		bIn24G
+)
+{
+	PHAL_DATA_TYPE		pHalData = GET_HAL_DATA(pAdapter);
+	struct dm_struct			*pDM_Odm = &pHalData->odmpriv;
+	u8					i = 0;	/* default set to 1S */
+	u8					txPower = 0;
+	u8					chnlIdx = (Channel - 1);
+
+	if (HAL_IsLegalChannel(pAdapter, Channel) == _FALSE) {
+		chnlIdx = 0;
+		RTW_INFO("Illegal channel!!\n");
+	}
+
+	*bIn24G = phy_GetChnlIndex(Channel, &chnlIdx);
+
+	if (0)
+		RTW_INFO("[%s] Channel Index: %d\n", (*bIn24G ? "2.4G" : "5G"), chnlIdx);
+
+	if (*bIn24G) {
+		if (IS_CCK_RATE(Rate)) {
+			/* CCK-nTX */
+			txPower = pHalData->Index24G_CCK_Base[RFPath][chnlIdx];
+			txPower += pHalData->CCK_24G_Diff[RFPath][RF_1TX];
+			if (ntx_idx >= RF_2TX)
+				txPower += pHalData->CCK_24G_Diff[RFPath][RF_2TX];
+			if (ntx_idx >= RF_3TX)
+				txPower += pHalData->CCK_24G_Diff[RFPath][RF_3TX];
+			if (ntx_idx >= RF_4TX)
+				txPower += pHalData->CCK_24G_Diff[RFPath][RF_4TX];
+			goto exit;
+		}
+
+		txPower = pHalData->Index24G_BW40_Base[RFPath][chnlIdx];
+
+		/* OFDM-nTX */
+		if ((MGN_6M <= Rate && Rate <= MGN_54M) && !IS_CCK_RATE(Rate)) {
+			txPower += pHalData->OFDM_24G_Diff[RFPath][RF_1TX];
+			if (ntx_idx >= RF_2TX)
+				txPower += pHalData->OFDM_24G_Diff[RFPath][RF_2TX];
+			if (ntx_idx >= RF_3TX)
+				txPower += pHalData->OFDM_24G_Diff[RFPath][RF_3TX];
+			if (ntx_idx >= RF_4TX)
+				txPower += pHalData->OFDM_24G_Diff[RFPath][RF_4TX];
+			goto exit;
+		}
+
+		/* BW20-nS */
+		if (BandWidth == CHANNEL_WIDTH_20) {
+			if ((MGN_MCS0 <= Rate && Rate <= MGN_MCS31) || (MGN_VHT1SS_MCS0 <= Rate && Rate <= MGN_VHT4SS_MCS9))
+				txPower += pHalData->BW20_24G_Diff[RFPath][RF_1TX];
+			if ((MGN_MCS8 <= Rate && Rate <= MGN_MCS31) || (MGN_VHT2SS_MCS0 <= Rate && Rate <= MGN_VHT4SS_MCS9))
+				txPower += pHalData->BW20_24G_Diff[RFPath][RF_2TX];
+			if ((MGN_MCS16 <= Rate && Rate <= MGN_MCS31) || (MGN_VHT3SS_MCS0 <= Rate && Rate <= MGN_VHT4SS_MCS9))
+				txPower += pHalData->BW20_24G_Diff[RFPath][RF_3TX];
+			if ((MGN_MCS24 <= Rate && Rate <= MGN_MCS31) || (MGN_VHT4SS_MCS0 <= Rate && Rate <= MGN_VHT4SS_MCS9))
+				txPower += pHalData->BW20_24G_Diff[RFPath][RF_4TX];
+			goto exit;
+		}
+
+		/* BW40-nS */
+		if (BandWidth == CHANNEL_WIDTH_40) {
+			if ((MGN_MCS0 <= Rate && Rate <= MGN_MCS31) || (MGN_VHT1SS_MCS0 <= Rate && Rate <= MGN_VHT4SS_MCS9))
+				txPower += pHalData->BW40_24G_Diff[RFPath][RF_1TX];
+			if ((MGN_MCS8 <= Rate && Rate <= MGN_MCS31) || (MGN_VHT2SS_MCS0 <= Rate && Rate <= MGN_VHT4SS_MCS9))
+				txPower += pHalData->BW40_24G_Diff[RFPath][RF_2TX];
+			if ((MGN_MCS16 <= Rate && Rate <= MGN_MCS31) || (MGN_VHT3SS_MCS0 <= Rate && Rate <= MGN_VHT4SS_MCS9))
+				txPower += pHalData->BW40_24G_Diff[RFPath][RF_3TX];
+			if ((MGN_MCS24 <= Rate && Rate <= MGN_MCS31) || (MGN_VHT4SS_MCS0 <= Rate && Rate <= MGN_VHT4SS_MCS9))
+				txPower += pHalData->BW40_24G_Diff[RFPath][RF_4TX];
+			goto exit;
+		}
+
+		/* Willis suggest adopt BW 40M power index while in BW 80 mode */
+		if (BandWidth == CHANNEL_WIDTH_80) {
+			if ((MGN_MCS0 <= Rate && Rate <= MGN_MCS31) || (MGN_VHT1SS_MCS0 <= Rate && Rate <= MGN_VHT4SS_MCS9))
+				txPower += pHalData->BW40_24G_Diff[RFPath][RF_1TX];
+			if ((MGN_MCS8 <= Rate && Rate <= MGN_MCS31) || (MGN_VHT2SS_MCS0 <= Rate && Rate <= MGN_VHT4SS_MCS9))
+				txPower += pHalData->BW40_24G_Diff[RFPath][RF_2TX];
+			if ((MGN_MCS16 <= Rate && Rate <= MGN_MCS31) || (MGN_VHT3SS_MCS0 <= Rate && Rate <= MGN_VHT4SS_MCS9))
+				txPower += pHalData->BW40_24G_Diff[RFPath][RF_3TX];
+			if ((MGN_MCS24 <= Rate && Rate <= MGN_MCS31) || (MGN_VHT4SS_MCS0 <= Rate && Rate <= MGN_VHT4SS_MCS9))
+				txPower += pHalData->BW40_24G_Diff[RFPath][RF_4TX];
+			goto exit;
+		}
+	}
+#ifdef CONFIG_IEEE80211_BAND_5GHZ
+	else {
+		if (Rate >= MGN_6M)
+			txPower = pHalData->Index5G_BW40_Base[RFPath][chnlIdx];
+		else {
+			RTW_INFO("===>PHY_GetTxPowerIndexBase: INVALID Rate(0x%02x).\n", Rate);
+			goto exit;
+		}
+
+		/* OFDM-nTX */
+		if ((MGN_6M <= Rate && Rate <= MGN_54M) && !IS_CCK_RATE(Rate)) {
+			txPower += pHalData->OFDM_5G_Diff[RFPath][RF_1TX];
+			if (ntx_idx >= RF_2TX)
+				txPower += pHalData->OFDM_5G_Diff[RFPath][RF_2TX];
+			if (ntx_idx >= RF_3TX)
+				txPower += pHalData->OFDM_5G_Diff[RFPath][RF_3TX];
+			if (ntx_idx >= RF_4TX)
+				txPower += pHalData->OFDM_5G_Diff[RFPath][RF_4TX];
+			goto exit;
+		}
+
+		/* BW20-nS */
+		if (BandWidth == CHANNEL_WIDTH_20) {
+			if ((MGN_MCS0 <= Rate && Rate <= MGN_MCS31)  || (MGN_VHT1SS_MCS0 <= Rate && Rate <= MGN_VHT4SS_MCS9))
+				txPower += pHalData->BW20_5G_Diff[RFPath][RF_1TX];
+			if ((MGN_MCS8 <= Rate && Rate <= MGN_MCS31) || (MGN_VHT2SS_MCS0 <= Rate && Rate <= MGN_VHT4SS_MCS9))
+				txPower += pHalData->BW20_5G_Diff[RFPath][RF_2TX];
+			if ((MGN_MCS16 <= Rate && Rate <= MGN_MCS31) || (MGN_VHT3SS_MCS0 <= Rate && Rate <= MGN_VHT4SS_MCS9))
+				txPower += pHalData->BW20_5G_Diff[RFPath][RF_3TX];
+			if ((MGN_MCS24 <= Rate && Rate <= MGN_MCS31) || (MGN_VHT4SS_MCS0 <= Rate && Rate <= MGN_VHT4SS_MCS9))
+				txPower += pHalData->BW20_5G_Diff[RFPath][RF_4TX];
+			goto exit;
+		}
+
+		/* BW40-nS */
+		if (BandWidth == CHANNEL_WIDTH_40) {
+			if ((MGN_MCS0 <= Rate && Rate <= MGN_MCS31)  || (MGN_VHT1SS_MCS0 <= Rate && Rate <= MGN_VHT4SS_MCS9))
+				txPower += pHalData->BW40_5G_Diff[RFPath][RF_1TX];
+			if ((MGN_MCS8 <= Rate && Rate <= MGN_MCS31) || (MGN_VHT2SS_MCS0 <= Rate && Rate <= MGN_VHT4SS_MCS9))
+				txPower += pHalData->BW40_5G_Diff[RFPath][RF_2TX];
+			if ((MGN_MCS16 <= Rate && Rate <= MGN_MCS31) || (MGN_VHT3SS_MCS0 <= Rate && Rate <= MGN_VHT4SS_MCS9))
+				txPower += pHalData->BW40_5G_Diff[RFPath][RF_3TX];
+			if ((MGN_MCS24 <= Rate && Rate <= MGN_MCS31) || (MGN_VHT4SS_MCS0 <= Rate && Rate <= MGN_VHT4SS_MCS9))
+				txPower += pHalData->BW40_5G_Diff[RFPath][RF_4TX];
+			goto exit;
+		}
+
+		/* BW80-nS */
+		if (BandWidth == CHANNEL_WIDTH_80) {
+			/* get 80MHz cch index */
+			for (i = 0; i < CENTER_CH_5G_80M_NUM; ++i) {
+				if (center_ch_5g_80m[i] == Channel) {
+					chnlIdx = i;
+					break;
+				}
+			}
+			if (i >= CENTER_CH_5G_80M_NUM) {
+			#ifdef CONFIG_MP_INCLUDED
+				if (rtw_mp_mode_check(pAdapter) == _FALSE)
+			#endif
+					rtw_warn_on(1);
+				txPower = 0;
+				goto exit;
+			}
+
+			txPower = pHalData->Index5G_BW80_Base[RFPath][chnlIdx];
+
+			if ((MGN_MCS0 <= Rate && Rate <= MGN_MCS31)  || (MGN_VHT1SS_MCS0 <= Rate && Rate <= MGN_VHT4SS_MCS9))
+				txPower += + pHalData->BW80_5G_Diff[RFPath][RF_1TX];
+			if ((MGN_MCS8 <= Rate && Rate <= MGN_MCS31) || (MGN_VHT2SS_MCS0 <= Rate && Rate <= MGN_VHT4SS_MCS9))
+				txPower += pHalData->BW80_5G_Diff[RFPath][RF_2TX];
+			if ((MGN_MCS16 <= Rate && Rate <= MGN_MCS31) || (MGN_VHT3SS_MCS0 <= Rate && Rate <= MGN_VHT4SS_MCS9))
+				txPower += pHalData->BW80_5G_Diff[RFPath][RF_3TX];
+			if ((MGN_MCS23 <= Rate && Rate <= MGN_MCS31) || (MGN_VHT4SS_MCS0 <= Rate && Rate <= MGN_VHT4SS_MCS9))
+				txPower += pHalData->BW80_5G_Diff[RFPath][RF_4TX];
+			goto exit;
+		}
+
+		/* TODO: BW160-nS */
+		rtw_warn_on(1);
+	}
+#endif /* CONFIG_IEEE80211_BAND_5GHZ */
+
+exit:
+	return txPower;
+}
+
+s8
+PHY_GetTxPowerTrackingOffset(
+	PADAPTER	pAdapter,
+	enum rf_path	RFPath,
+	u8			Rate
+)
+{
+	PHAL_DATA_TYPE		pHalData = GET_HAL_DATA(pAdapter);
+	struct dm_struct			*pDM_Odm = &pHalData->odmpriv;
+	s8	offset = 0;
+
+	if (pDM_Odm->rf_calibrate_info.txpowertrack_control  == _FALSE)
+		return offset;
+
+	if ((Rate == MGN_1M) || (Rate == MGN_2M) || (Rate == MGN_5_5M) || (Rate == MGN_11M)) {
+		offset = pDM_Odm->rf_calibrate_info.remnant_cck_swing_idx;
+		/*RTW_INFO("+Remnant_CCKSwingIdx = 0x%x\n", RFPath, Rate, pRFCalibrateInfo->Remnant_CCKSwingIdx);*/
+	} else {
+		offset = pDM_Odm->rf_calibrate_info.remnant_ofdm_swing_idx[RFPath];
+		/*RTW_INFO("+Remanant_OFDMSwingIdx[RFPath %u][Rate 0x%x] = 0x%x\n", RFPath, Rate, pRFCalibrateInfo->Remnant_OFDMSwingIdx[RFPath]);	*/
+
+	}
+
+	return offset;
+}
+
+/*The same as MRateToHwRate in hal_com.c*/
+u8
+PHY_GetRateIndexOfTxPowerByRate(
+	IN	u8		Rate
+)
+{
+	u8	index = 0;
+	switch (Rate) {
+	case MGN_1M:
+		index = 0;
+		break;
+	case MGN_2M:
+		index = 1;
+		break;
+	case MGN_5_5M:
+		index = 2;
+		break;
+	case MGN_11M:
+		index = 3;
+		break;
+	case MGN_6M:
+		index = 4;
+		break;
+	case MGN_9M:
+		index = 5;
+		break;
+	case MGN_12M:
+		index = 6;
+		break;
+	case MGN_18M:
+		index = 7;
+		break;
+	case MGN_24M:
+		index = 8;
+		break;
+	case MGN_36M:
+		index = 9;
+		break;
+	case MGN_48M:
+		index = 10;
+		break;
+	case MGN_54M:
+		index = 11;
+		break;
+	case MGN_MCS0:
+		index = 12;
+		break;
+	case MGN_MCS1:
+		index = 13;
+		break;
+	case MGN_MCS2:
+		index = 14;
+		break;
+	case MGN_MCS3:
+		index = 15;
+		break;
+	case MGN_MCS4:
+		index = 16;
+		break;
+	case MGN_MCS5:
+		index = 17;
+		break;
+	case MGN_MCS6:
+		index = 18;
+		break;
+	case MGN_MCS7:
+		index = 19;
+		break;
+	case MGN_MCS8:
+		index = 20;
+		break;
+	case MGN_MCS9:
+		index = 21;
+		break;
+	case MGN_MCS10:
+		index = 22;
+		break;
+	case MGN_MCS11:
+		index = 23;
+		break;
+	case MGN_MCS12:
+		index = 24;
+		break;
+	case MGN_MCS13:
+		index = 25;
+		break;
+	case MGN_MCS14:
+		index = 26;
+		break;
+	case MGN_MCS15:
+		index = 27;
+		break;
+	case MGN_MCS16:
+		index = 28;
+		break;
+	case MGN_MCS17:
+		index = 29;
+		break;
+	case MGN_MCS18:
+		index = 30;
+		break;
+	case MGN_MCS19:
+		index = 31;
+		break;
+	case MGN_MCS20:
+		index = 32;
+		break;
+	case MGN_MCS21:
+		index = 33;
+		break;
+	case MGN_MCS22:
+		index = 34;
+		break;
+	case MGN_MCS23:
+		index = 35;
+		break;
+	case MGN_MCS24:
+		index = 36;
+		break;
+	case MGN_MCS25:
+		index = 37;
+		break;
+	case MGN_MCS26:
+		index = 38;
+		break;
+	case MGN_MCS27:
+		index = 39;
+		break;
+	case MGN_MCS28:
+		index = 40;
+		break;
+	case MGN_MCS29:
+		index = 41;
+		break;
+	case MGN_MCS30:
+		index = 42;
+		break;
+	case MGN_MCS31:
+		index = 43;
+		break;
+	case MGN_VHT1SS_MCS0:
+		index = 44;
+		break;
+	case MGN_VHT1SS_MCS1:
+		index = 45;
+		break;
+	case MGN_VHT1SS_MCS2:
+		index = 46;
+		break;
+	case MGN_VHT1SS_MCS3:
+		index = 47;
+		break;
+	case MGN_VHT1SS_MCS4:
+		index = 48;
+		break;
+	case MGN_VHT1SS_MCS5:
+		index = 49;
+		break;
+	case MGN_VHT1SS_MCS6:
+		index = 50;
+		break;
+	case MGN_VHT1SS_MCS7:
+		index = 51;
+		break;
+	case MGN_VHT1SS_MCS8:
+		index = 52;
+		break;
+	case MGN_VHT1SS_MCS9:
+		index = 53;
+		break;
+	case MGN_VHT2SS_MCS0:
+		index = 54;
+		break;
+	case MGN_VHT2SS_MCS1:
+		index = 55;
+		break;
+	case MGN_VHT2SS_MCS2:
+		index = 56;
+		break;
+	case MGN_VHT2SS_MCS3:
+		index = 57;
+		break;
+	case MGN_VHT2SS_MCS4:
+		index = 58;
+		break;
+	case MGN_VHT2SS_MCS5:
+		index = 59;
+		break;
+	case MGN_VHT2SS_MCS6:
+		index = 60;
+		break;
+	case MGN_VHT2SS_MCS7:
+		index = 61;
+		break;
+	case MGN_VHT2SS_MCS8:
+		index = 62;
+		break;
+	case MGN_VHT2SS_MCS9:
+		index = 63;
+		break;
+	case MGN_VHT3SS_MCS0:
+		index = 64;
+		break;
+	case MGN_VHT3SS_MCS1:
+		index = 65;
+		break;
+	case MGN_VHT3SS_MCS2:
+		index = 66;
+		break;
+	case MGN_VHT3SS_MCS3:
+		index = 67;
+		break;
+	case MGN_VHT3SS_MCS4:
+		index = 68;
+		break;
+	case MGN_VHT3SS_MCS5:
+		index = 69;
+		break;
+	case MGN_VHT3SS_MCS6:
+		index = 70;
+		break;
+	case MGN_VHT3SS_MCS7:
+		index = 71;
+		break;
+	case MGN_VHT3SS_MCS8:
+		index = 72;
+		break;
+	case MGN_VHT3SS_MCS9:
+		index = 73;
+		break;
+	case MGN_VHT4SS_MCS0:
+		index = 74;
+		break;
+	case MGN_VHT4SS_MCS1:
+		index = 75;
+		break;
+	case MGN_VHT4SS_MCS2:
+		index = 76;
+		break;
+	case MGN_VHT4SS_MCS3:
+		index = 77;
+		break;
+	case MGN_VHT4SS_MCS4:
+		index = 78;
+		break;
+	case MGN_VHT4SS_MCS5:
+		index = 79;
+		break;
+	case MGN_VHT4SS_MCS6:
+		index = 80;
+		break;
+	case MGN_VHT4SS_MCS7:
+		index = 81;
+		break;
+	case MGN_VHT4SS_MCS8:
+		index = 82;
+		break;
+	case MGN_VHT4SS_MCS9:
+		index = 83;
+		break;
+	default:
+		RTW_INFO("Invalid rate 0x%x in %s\n", Rate, __FUNCTION__);
+		break;
+	};
+
+	return index;
+}
+
+s8
+_PHY_GetTxPowerByRate(
+	IN	PADAPTER	pAdapter,
+	IN	u8			Band,
+	IN	enum rf_path	RFPath,
+	IN	u8			Rate
+)
+{
+	HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
+	s8 value = 0;
+	u8 rateIndex = PHY_GetRateIndexOfTxPowerByRate(Rate);
+
+	if (Band != BAND_ON_2_4G && Band != BAND_ON_5G) {
+		RTW_INFO("Invalid band %d in %s\n", Band, __func__);
+		goto exit;
+	}
+	if (RFPath > RF_PATH_D) {
+		RTW_INFO("Invalid RfPath %d in %s\n", RFPath, __func__);
+		goto exit;
+	}
+	if (rateIndex >= TX_PWR_BY_RATE_NUM_RATE) {
+		RTW_INFO("Invalid RateIndex %d in %s\n", rateIndex, __func__);
+		goto exit;
+	}
+
+	value = pHalData->TxPwrByRateOffset[Band][RFPath][rateIndex];
+
+exit:
+	return value;
+}
+
+
+s8
+PHY_GetTxPowerByRate(
+	IN	PADAPTER	pAdapter,
+	IN	u8			Band,
+	IN	enum rf_path	RFPath,
+	IN	u8			Rate
+)
+{
+	if (!phy_is_tx_power_by_rate_needed(pAdapter))
+		return 0;
+
+	return _PHY_GetTxPowerByRate(pAdapter, Band, RFPath, Rate);
+}
+
+VOID
+PHY_SetTxPowerByRate(
+	IN	PADAPTER	pAdapter,
+	IN	u8			Band,
+	IN	enum rf_path	RFPath,
+	IN	u8			Rate,
+	IN	s8			Value
+)
+{
+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(pAdapter);
+	u8	rateIndex = PHY_GetRateIndexOfTxPowerByRate(Rate);
+
+	if (Band != BAND_ON_2_4G && Band != BAND_ON_5G) {
+		RTW_INFO("Invalid band %d in %s\n", Band, __FUNCTION__);
+		return;
+	}
+	if (RFPath > RF_PATH_D) {
+		RTW_INFO("Invalid RfPath %d in %s\n", RFPath, __FUNCTION__);
+		return;
+	}
+	if (rateIndex >= TX_PWR_BY_RATE_NUM_RATE) {
+		RTW_INFO("Invalid RateIndex %d in %s\n", rateIndex, __FUNCTION__);
+		return;
+	}
+
+	pHalData->TxPwrByRateOffset[Band][RFPath][rateIndex] = Value;
+}
+
+u8 phy_check_under_survey_ch(_adapter *adapter)
+{
+	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
+	_adapter *iface;
+	struct mlme_ext_priv *mlmeext;
+	u8 ret = _FALSE;
+	int i;
+
+	for (i = 0; i < dvobj->iface_nums; i++) {
+		iface = dvobj->padapters[i];
+		if (!iface)
+			continue;
+		mlmeext = &iface->mlmeextpriv;
+
+		/* check scan state */
+		if (mlmeext_scan_state(mlmeext) != SCAN_DISABLE
+			&& mlmeext_scan_state(mlmeext) != SCAN_COMPLETE
+				&& mlmeext_scan_state(mlmeext) != SCAN_BACKING_OP) {
+			ret = _TRUE;
+		} else if (mlmeext_scan_state(mlmeext) == SCAN_BACKING_OP
+			&& !mlmeext_chk_scan_backop_flags(mlmeext, SS_BACKOP_TX_RESUME)) {
+			ret = _TRUE;
+		}
+	}
+
+	return ret;
+}
+
+VOID
+phy_set_tx_power_level_by_path(
+	IN	PADAPTER	Adapter,
+	IN	u8			channel,
+	IN	u8			path
+)
+{
+	PHAL_DATA_TYPE	pHalData = GET_HAL_DATA(Adapter);
+	BOOLEAN bIsIn24G = (pHalData->current_band_type == BAND_ON_2_4G);
+	u8 under_survey_ch = phy_check_under_survey_ch(Adapter);
+
+
+	/* if ( pMgntInfo->RegNByteAccess == 0 ) */
+	{
+		if (bIsIn24G)
+			phy_set_tx_power_index_by_rate_section(Adapter, path, channel, CCK);
+
+		phy_set_tx_power_index_by_rate_section(Adapter, path, channel, OFDM);
+
+		if (!under_survey_ch) {
+			phy_set_tx_power_index_by_rate_section(Adapter, path, channel, HT_MCS0_MCS7);
+
+			if (IS_HARDWARE_TYPE_JAGUAR(Adapter) || IS_HARDWARE_TYPE_8814A(Adapter))
+				phy_set_tx_power_index_by_rate_section(Adapter, path, channel, VHT_1SSMCS0_1SSMCS9);
+
+			if (pHalData->NumTotalRFPath >= 2) {
+				phy_set_tx_power_index_by_rate_section(Adapter, path, channel, HT_MCS8_MCS15);
+
+				if (IS_HARDWARE_TYPE_JAGUAR(Adapter) || IS_HARDWARE_TYPE_8814A(Adapter))
+					phy_set_tx_power_index_by_rate_section(Adapter, path, channel, VHT_2SSMCS0_2SSMCS9);
+
+				if (IS_HARDWARE_TYPE_8814A(Adapter)) {
+					phy_set_tx_power_index_by_rate_section(Adapter, path, channel, HT_MCS16_MCS23);
+					phy_set_tx_power_index_by_rate_section(Adapter, path, channel, VHT_3SSMCS0_3SSMCS9);
+				}
+			}
+		}
+	}
+}
+
+#ifndef DBG_TX_POWER_IDX
+#define DBG_TX_POWER_IDX 0
+#endif
+
+VOID
+PHY_SetTxPowerIndexByRateArray(
+	IN	PADAPTER			pAdapter,
+	IN	enum rf_path			RFPath,
+	IN	enum channel_width	BandWidth,
+	IN	u8					Channel,
+	IN	u8					*Rates,
+	IN	u8					RateArraySize
+)
+{
+	u32	powerIndex = 0;
+	int	i = 0;
+
+	for (i = 0; i < RateArraySize; ++i) {
+#if DBG_TX_POWER_IDX
+		struct txpwr_idx_comp tic;
+
+		powerIndex = rtw_hal_get_tx_power_index(pAdapter, RFPath, Rates[i], BandWidth, Channel, &tic);
+		RTW_INFO("TXPWR: [%c][%s]ch:%u, %s %uT, pwr_idx:%u = %u + (%d=%d:%d) + (%d) + (%d)\n"
+			, rf_path_char(RFPath), ch_width_str(BandWidth), Channel, MGN_RATE_STR(Rates[i]), tic.ntx_idx + 1
+			, powerIndex, tic.base, (tic.by_rate > tic.limit ? tic.limit : tic.by_rate), tic.by_rate, tic.limit, tic.tpt, tic.ebias);
+#else
+		powerIndex = phy_get_tx_power_index(pAdapter, RFPath, Rates[i], BandWidth, Channel);
+#endif
+		PHY_SetTxPowerIndex(pAdapter, powerIndex, RFPath, Rates[i]);
+	}
+}
+
+#ifdef CONFIG_TXPWR_LIMIT
+const char *const _txpwr_lmt_rs_str[] = {
+	"CCK",
+	"OFDM",
+	"HT",
+	"VHT",
+	"UNKNOWN",
+};
+
+static s8
+phy_GetChannelIndexOfTxPowerLimit(
+	IN	u8			Band,
+	IN	u8			Channel
+)
+{
+	s8	channelIndex = -1;
+	u8	i = 0;
+
+	if (Band == BAND_ON_2_4G)
+		channelIndex = Channel - 1;
+	else if (Band == BAND_ON_5G) {
+		for (i = 0; i < CENTER_CH_5G_ALL_NUM; ++i) {
+			if (center_ch_5g_all[i] == Channel)
+				channelIndex = i;
+		}
+	} else
+		RTW_PRINT("Invalid Band %d in %s\n", Band, __func__);
+
+	if (channelIndex == -1)
+		RTW_PRINT("Invalid Channel %d of Band %d in %s\n", Channel, Band, __func__);
+
+	return channelIndex;
+}
+
+static s8 phy_txpwr_ww_lmt_value(_adapter *adapter)
+{
+	struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter);
+
+	if (hal_spec->txgi_max == 63)
+		return -63;
+	else if (hal_spec->txgi_max == 127)
+		return -128;
+
+	rtw_warn_on(1);
+	return -128;
+}
+
+/*
+* return txpwr limit absolute value
+* hsl_spec->txgi_max is returned when NO limit
+*/
+s8 phy_get_txpwr_lmt_abs(
+	IN	PADAPTER			Adapter,
+	IN	const char			*regd_name,
+	IN	BAND_TYPE			Band,
+	IN	enum channel_width		bw,
+	u8 tlrs,
+	u8 ntx_idx,
+	u8 cch,
+	u8 lock
+)
+{
+	struct dvobj_priv *dvobj = adapter_to_dvobj(Adapter);
+	struct rf_ctl_t *rfctl = adapter_to_rfctl(Adapter);
+	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(Adapter);
+	struct hal_spec_t *hal_spec = GET_HAL_SPEC(Adapter);
+	struct txpwr_lmt_ent *ent = NULL;
+	_irqL irqL;
+	_list *cur, *head;
+	s8 ch_idx;
+	u8 is_ww_regd = 0;
+	s8 ww_lmt_val = phy_txpwr_ww_lmt_value(Adapter);
+	s8 lmt = hal_spec->txgi_max;
+
+	if ((Adapter->registrypriv.RegEnableTxPowerLimit == 2 && hal_data->EEPROMRegulatory != 1) ||
+		Adapter->registrypriv.RegEnableTxPowerLimit == 0)
+		goto exit;
+
+	if (Band != BAND_ON_2_4G && Band != BAND_ON_5G) {
+		RTW_ERR("%s invalid band:%u\n", __func__, Band);
+		rtw_warn_on(1);
+		goto exit;
+	}
+
+	if (Band == BAND_ON_5G  && tlrs == TXPWR_LMT_RS_CCK) {
+		RTW_ERR("5G has no CCK\n");
+		goto exit;
+	}
+
+	if (lock)
+		_enter_critical_mutex(&rfctl->txpwr_lmt_mutex, &irqL);
+
+	if (!regd_name) /* no regd_name specified, use currnet */
+		regd_name = rfctl->regd_name;
+
+	if (rfctl->txpwr_regd_num == 0
+		|| strcmp(regd_name, regd_str(TXPWR_LMT_NONE)) == 0)
+		goto release_lock;
+
+	if (strcmp(regd_name, regd_str(TXPWR_LMT_WW)) == 0)
+		is_ww_regd = 1;
+
+	if (!is_ww_regd) {
+		ent = _rtw_txpwr_lmt_get_by_name(rfctl, regd_name);
+		if (!ent)
+			goto release_lock;
+	}
+
+	ch_idx = phy_GetChannelIndexOfTxPowerLimit(Band, cch);
+	if (ch_idx == -1)
+		goto release_lock;
+
+	if (Band == BAND_ON_2_4G) {
+		if (!is_ww_regd) {
+			lmt = ent->lmt_2g[bw][tlrs][ch_idx][ntx_idx];
+			if (lmt != ww_lmt_val)
+				goto release_lock;
+		}
+
+		/* search for min value for WW regd or WW limit */
+		lmt = hal_spec->txgi_max;
+		head = &rfctl->txpwr_lmt_list;
+		cur = get_next(head);
+		while ((rtw_end_of_queue_search(head, cur)) == _FALSE) {
+			ent = LIST_CONTAINOR(cur, struct txpwr_lmt_ent, list);
+			cur = get_next(cur);
+			if (ent->lmt_2g[bw][tlrs][ch_idx][ntx_idx] != ww_lmt_val)
+				lmt = rtw_min(lmt, ent->lmt_2g[bw][tlrs][ch_idx][ntx_idx]);
+		}
+	}
+	#ifdef CONFIG_IEEE80211_BAND_5GHZ
+	else if (Band == BAND_ON_5G) {
+		if (!is_ww_regd) {
+			lmt = ent->lmt_5g[bw][tlrs - 1][ch_idx][ntx_idx];
+			if (lmt != ww_lmt_val)
+				goto release_lock;
+		}
+
+		/* search for min value for WW regd or WW limit */
+		lmt = hal_spec->txgi_max;
+		head = &rfctl->txpwr_lmt_list;
+		cur = get_next(head);
+		while ((rtw_end_of_queue_search(head, cur)) == _FALSE) {
+			ent = LIST_CONTAINOR(cur, struct txpwr_lmt_ent, list);
+			cur = get_next(cur);
+			if (ent->lmt_5g[bw][tlrs - 1][ch_idx][ntx_idx] != ww_lmt_val)
+				lmt = rtw_min(lmt, ent->lmt_5g[bw][tlrs - 1][ch_idx][ntx_idx]);
+		}
+	}
+	#endif
+
+release_lock:
+	if (lock)
+		_exit_critical_mutex(&rfctl->txpwr_lmt_mutex, &irqL);
+
+exit:
+	return lmt;
+}
+
+/*
+* return txpwr limit diff value
+* hal_spec->txgi_max is returned when NO limit
+*/
+inline s8 phy_get_txpwr_lmt(_adapter *adapter
+	, const char *regd_name
+	, BAND_TYPE band, enum channel_width bw
+	, u8 rfpath, u8 rs, u8 ntx_idx, u8 cch, u8 lock
+)
+{
+	struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter);
+	u8 tlrs;
+	s8 lmt = hal_spec->txgi_max;
+
+	if (IS_CCK_RATE_SECTION(rs))
+		tlrs = TXPWR_LMT_RS_CCK;
+	else if (IS_OFDM_RATE_SECTION(rs))
+		tlrs = TXPWR_LMT_RS_OFDM;
+	else if (IS_HT_RATE_SECTION(rs))
+		tlrs = TXPWR_LMT_RS_HT;
+	else if (IS_VHT_RATE_SECTION(rs))
+		tlrs = TXPWR_LMT_RS_VHT;
+	else {
+		RTW_ERR("%s invalid rs %u\n", __func__, rs);
+		rtw_warn_on(1);
+		goto exit;
+	}
+
+	lmt = phy_get_txpwr_lmt_abs(adapter, regd_name, band, bw, tlrs, ntx_idx, cch, lock);
+
+	if (lmt != hal_spec->txgi_max) {
+		/* return diff value */
+		lmt = lmt - PHY_GetTxPowerByRateBase(adapter, band, rfpath, rs);
+	}
+
+exit:
+	return lmt;
+}
+
+/*
+* May search for secondary channels for min limit
+* return txpwr limit diff value
+*/
+s8
+PHY_GetTxPowerLimit(_adapter *adapter
+	, const char *regd_name
+	, BAND_TYPE band, enum channel_width bw
+	, u8 rfpath, u8 rate, u8 ntx_idx, u8 cch)
+{
+	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
+	struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter);
+	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
+	struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter);
+	BOOLEAN no_sc = _FALSE;
+	s8 tlrs = -1, rs = -1;
+	s8 lmt = hal_spec->txgi_max;
+	u8 tmp_cch = 0;
+	u8 tmp_bw;
+	u8 bw_bmp = 0;
+	s8 min_lmt = hal_spec->txgi_max;
+	u8 final_bw = bw, final_cch = cch;
+	_irqL irqL;
+
+#ifdef CONFIG_MP_INCLUDED
+	/* MP mode channel don't use secondary channel */
+	if (rtw_mp_mode_check(adapter) == _TRUE)
+		no_sc = _TRUE;
+#endif
+	if (IS_CCK_RATE(rate)) {
+		tlrs = TXPWR_LMT_RS_CCK;
+		rs = CCK;
+	} else if (IS_OFDM_RATE(rate)) {
+		tlrs = TXPWR_LMT_RS_OFDM;
+		rs = OFDM;
+	} else if (IS_HT_RATE(rate)) {
+		tlrs = TXPWR_LMT_RS_HT;
+		rs = HT_1SS + (IS_HT1SS_RATE(rate) ? 0 : IS_HT2SS_RATE(rate) ? 1 : IS_HT3SS_RATE(rate) ? 2 : IS_HT4SS_RATE(rate) ? 3 : 0);
+	} else if (IS_VHT_RATE(rate)) {
+		tlrs = TXPWR_LMT_RS_VHT;
+		rs = VHT_1SS + (IS_VHT1SS_RATE(rate) ? 0 : IS_VHT2SS_RATE(rate) ? 1 : IS_VHT3SS_RATE(rate) ? 2 : IS_VHT4SS_RATE(rate) ? 3 : 0);
+	} else {
+		RTW_ERR("%s invalid rate 0x%x\n", __func__, rate);
+		rtw_warn_on(1);
+		goto exit;
+	}
+
+	if (no_sc == _TRUE) {
+		/* use the input center channel and bandwidth directly */
+		tmp_cch = cch;
+		bw_bmp = ch_width_to_bw_cap(bw);
+	} else {
+		/*
+		* find the possible tx bandwidth bmp for this rate, and then will get center channel for each bandwidth
+		* if no possible tx bandwidth bmp, select valid bandwidth up to current RF bandwidth into bmp
+		*/
+		if (tlrs == TXPWR_LMT_RS_CCK || tlrs == TXPWR_LMT_RS_OFDM)
+			bw_bmp = BW_CAP_20M; /* CCK, OFDM only BW 20M */
+		else if (tlrs == TXPWR_LMT_RS_HT) {
+			bw_bmp = rtw_get_tx_bw_bmp_of_ht_rate(dvobj, rate, bw);
+			if (bw_bmp == 0)
+				bw_bmp = ch_width_to_bw_cap(bw > CHANNEL_WIDTH_40 ? CHANNEL_WIDTH_40 : bw);
+		} else if (tlrs == TXPWR_LMT_RS_VHT) {
+			bw_bmp = rtw_get_tx_bw_bmp_of_vht_rate(dvobj, rate, bw);
+			if (bw_bmp == 0)
+				bw_bmp = ch_width_to_bw_cap(bw > CHANNEL_WIDTH_160 ? CHANNEL_WIDTH_160 : bw);
+		} else
+			rtw_warn_on(1);
+	}
+
+	if (bw_bmp == 0)
+		goto exit;
+
+	_enter_critical_mutex(&rfctl->txpwr_lmt_mutex, &irqL);
+
+	/* loop for each possible tx bandwidth to find minimum limit */
+	for (tmp_bw = CHANNEL_WIDTH_20; tmp_bw <= bw; tmp_bw++) {
+		if (!(ch_width_to_bw_cap(tmp_bw) & bw_bmp))
+			continue;
+
+		if (no_sc == _FALSE) {
+			if (tmp_bw == CHANNEL_WIDTH_20)
+				tmp_cch = hal_data->cch_20;
+			else if (tmp_bw == CHANNEL_WIDTH_40)
+				tmp_cch = hal_data->cch_40;
+			else if (tmp_bw == CHANNEL_WIDTH_80)
+				tmp_cch = hal_data->cch_80;
+			else {
+				tmp_cch = 0;
+				rtw_warn_on(1);
+			}
+		}
+
+		lmt = phy_get_txpwr_lmt_abs(adapter, regd_name, band, tmp_bw, tlrs, ntx_idx, tmp_cch, 0);
+
+		if (min_lmt >= lmt) {
+			min_lmt = lmt;
+			final_cch = tmp_cch;
+			final_bw = tmp_bw;
+		}
+
+	}
+
+	_exit_critical_mutex(&rfctl->txpwr_lmt_mutex, &irqL);
+
+	if (min_lmt != hal_spec->txgi_max) {
+		/* return diff value */
+		min_lmt = min_lmt - PHY_GetTxPowerByRateBase(adapter, band, rfpath, rs);
+	}
+
+exit:
+
+	if (0) {
+		if (final_bw != bw && (IS_HT_RATE(rate) || IS_VHT_RATE(rate)))
+			RTW_INFO("%s min_lmt: %s ch%u -> %s ch%u\n"
+				, MGN_RATE_STR(rate)
+				, ch_width_str(bw), cch
+				, ch_width_str(final_bw), final_cch);
+	}
+
+	return min_lmt;
+}
+
+static void phy_txpwr_lmt_cck_ofdm_mt_chk(_adapter *adapter)
+{
+	struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter);
+	struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter);
+	struct txpwr_lmt_ent *ent;
+	_list *cur, *head;
+	u8 channel, tlrs, ntx_idx;
+
+	rfctl->txpwr_lmt_2g_cck_ofdm_state = 0;
+#ifdef CONFIG_IEEE80211_BAND_5GHZ
+	rfctl->txpwr_lmt_5g_cck_ofdm_state = 0;
+#endif
+
+	head = &rfctl->txpwr_lmt_list;
+	cur = get_next(head);
+
+	while ((rtw_end_of_queue_search(head, cur)) == _FALSE) {
+		ent = LIST_CONTAINOR(cur, struct txpwr_lmt_ent, list);
+		cur = get_next(cur);
+
+		/* check 2G CCK, OFDM state*/
+		for (tlrs = TXPWR_LMT_RS_CCK; tlrs <= TXPWR_LMT_RS_OFDM; tlrs++) {
+			for (ntx_idx = RF_1TX; ntx_idx < MAX_TX_COUNT; ntx_idx++) {
+				for (channel = 0; channel < CENTER_CH_2G_NUM; ++channel) {
+					if (ent->lmt_2g[CHANNEL_WIDTH_20][tlrs][channel][ntx_idx] != hal_spec->txgi_max) {
+						if (tlrs == TXPWR_LMT_RS_CCK)
+							rfctl->txpwr_lmt_2g_cck_ofdm_state |= TXPWR_LMT_HAS_CCK_1T << ntx_idx;
+						else
+							rfctl->txpwr_lmt_2g_cck_ofdm_state |= TXPWR_LMT_HAS_OFDM_1T << ntx_idx;
+						break;
+					}
+				}
+			}
+		}
+
+		/* if 2G OFDM multi-TX is not defined, reference HT20 */
+		for (channel = 0; channel < CENTER_CH_2G_NUM; ++channel) {
+			for (ntx_idx = RF_2TX; ntx_idx < MAX_TX_COUNT; ntx_idx++) {
+				if (rfctl->txpwr_lmt_2g_cck_ofdm_state & (TXPWR_LMT_HAS_OFDM_1T << ntx_idx))
+					continue;
+				ent->lmt_2g[CHANNEL_WIDTH_20][TXPWR_LMT_RS_OFDM][channel][ntx_idx] =
+					ent->lmt_2g[CHANNEL_WIDTH_20][TXPWR_LMT_RS_HT][channel][ntx_idx];
+			}
+		}
+
+#ifdef CONFIG_IEEE80211_BAND_5GHZ
+		/* check 5G OFDM state*/
+		for (ntx_idx = RF_1TX; ntx_idx < MAX_TX_COUNT; ntx_idx++) {
+			for (channel = 0; channel < CENTER_CH_5G_ALL_NUM; ++channel) {
+				if (ent->lmt_5g[CHANNEL_WIDTH_20][TXPWR_LMT_RS_OFDM - 1][channel][ntx_idx] != hal_spec->txgi_max) {
+					rfctl->txpwr_lmt_5g_cck_ofdm_state |= TXPWR_LMT_HAS_OFDM_1T << ntx_idx;
+					break;
+				}
+			}
+		}
+
+		for (channel = 0; channel < CENTER_CH_5G_ALL_NUM; ++channel) {
+			for (ntx_idx = RF_2TX; ntx_idx < MAX_TX_COUNT; ntx_idx++) {
+				if (rfctl->txpwr_lmt_5g_cck_ofdm_state & (TXPWR_LMT_HAS_OFDM_1T << ntx_idx))
+					continue;
+				/* if 5G OFDM multi-TX is not defined, reference HT20 */
+				ent->lmt_5g[CHANNEL_WIDTH_20][TXPWR_LMT_RS_OFDM - 1][channel][ntx_idx] =
+					ent->lmt_5g[CHANNEL_WIDTH_20][TXPWR_LMT_RS_HT - 1][channel][ntx_idx];
+			}
+		}
+#endif /* CONFIG_IEEE80211_BAND_5GHZ */
+	}
+}
+
+#ifdef CONFIG_IEEE80211_BAND_5GHZ
+static void phy_txpwr_lmt_cross_ref_ht_vht(_adapter *adapter)
+{
+	struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter);
+	struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter);
+	struct txpwr_lmt_ent *ent;
+	_list *cur, *head;
+	u8 bw, channel, tlrs, ref_tlrs, ntx_idx;
+	int ht_ref_vht_5g_20_40 = 0;
+	int vht_ref_ht_5g_20_40 = 0;
+	int ht_has_ref_5g_20_40 = 0;
+	int vht_has_ref_5g_20_40 = 0;
+
+	rfctl->txpwr_lmt_5g_20_40_ref = 0;
+
+	head = &rfctl->txpwr_lmt_list;
+	cur = get_next(head);
+
+	while ((rtw_end_of_queue_search(head, cur)) == _FALSE) {
+		ent = LIST_CONTAINOR(cur, struct txpwr_lmt_ent, list);
+		cur = get_next(cur);
+
+		for (bw = 0; bw < MAX_5G_BANDWIDTH_NUM; ++bw) {
+
+			for (channel = 0; channel < CENTER_CH_5G_ALL_NUM; ++channel) {
+
+				for (tlrs = TXPWR_LMT_RS_HT; tlrs < TXPWR_LMT_RS_NUM; ++tlrs) {
+
+					/* 5G 20M 40M VHT and HT can cross reference */
+					if (bw == CHANNEL_WIDTH_20 || bw == CHANNEL_WIDTH_40) {
+						if (tlrs == TXPWR_LMT_RS_HT)
+							ref_tlrs = TXPWR_LMT_RS_VHT;
+						else if (tlrs == TXPWR_LMT_RS_VHT)
+							ref_tlrs = TXPWR_LMT_RS_HT;
+						else
+							continue;
+
+						for (ntx_idx = RF_1TX; ntx_idx < MAX_TX_COUNT; ntx_idx++) {
+
+							if (ent->lmt_5g[bw][ref_tlrs - 1][channel][ntx_idx] == hal_spec->txgi_max)
+								continue;
+
+							if (tlrs == TXPWR_LMT_RS_HT)
+								ht_has_ref_5g_20_40++;
+							else if (tlrs == TXPWR_LMT_RS_VHT)
+								vht_has_ref_5g_20_40++;
+							else
+								continue;
+
+							if (ent->lmt_5g[bw][tlrs - 1][channel][ntx_idx] != hal_spec->txgi_max)
+								continue;
+
+							if (tlrs == TXPWR_LMT_RS_HT && ref_tlrs == TXPWR_LMT_RS_VHT)
+								ht_ref_vht_5g_20_40++;
+							else if (tlrs == TXPWR_LMT_RS_VHT && ref_tlrs == TXPWR_LMT_RS_HT)
+								vht_ref_ht_5g_20_40++;
+
+							if (0)
+								RTW_INFO("reg:%s, bw:%u, ch:%u, %s-%uT ref %s-%uT\n"
+									, ent->regd_name, bw, channel
+									, txpwr_lmt_rs_str(tlrs), ntx_idx + 1
+									, txpwr_lmt_rs_str(ref_tlrs), ntx_idx + 1);
+
+							ent->lmt_5g[bw][tlrs - 1][channel][ntx_idx] =
+								ent->lmt_5g[bw][ref_tlrs - 1][channel][ntx_idx];
+						}
+					}
+
+				}
+			}
+		}
+	}
+
+	if (0) {
+		RTW_INFO("ht_ref_vht_5g_20_40:%d, ht_has_ref_5g_20_40:%d\n", ht_ref_vht_5g_20_40, ht_has_ref_5g_20_40);
+		RTW_INFO("vht_ref_ht_5g_20_40:%d, vht_has_ref_5g_20_40:%d\n", vht_ref_ht_5g_20_40, vht_has_ref_5g_20_40);
+	}
+
+	/* 5G 20M&40M HT all come from VHT*/
+	if (ht_ref_vht_5g_20_40 && ht_has_ref_5g_20_40 == ht_ref_vht_5g_20_40)
+		rfctl->txpwr_lmt_5g_20_40_ref |= TXPWR_LMT_REF_HT_FROM_VHT;
+
+	/* 5G 20M&40M VHT all come from HT*/
+	if (vht_ref_ht_5g_20_40 && vht_has_ref_5g_20_40 == vht_ref_ht_5g_20_40)
+		rfctl->txpwr_lmt_5g_20_40_ref |= TXPWR_LMT_REF_VHT_FROM_HT;
+}
+#endif /* CONFIG_IEEE80211_BAND_5GHZ */
+
+#ifndef DBG_TXPWR_LMT_BAND_CHK
+#define DBG_TXPWR_LMT_BAND_CHK 0
+#endif
+
+#if DBG_TXPWR_LMT_BAND_CHK
+/* check if larger bandwidth limit is less than smaller bandwidth for HT & VHT rate */
+void phy_txpwr_limit_bandwidth_chk(_adapter *adapter)
+{
+	struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter);
+	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
+	struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter);
+	u8 band, bw, path, tlrs, ntx_idx, cch, offset, scch;
+	u8 ch_num, n, i;
+
+	for (band = BAND_ON_2_4G; band <= BAND_ON_5G; band++) {
+		if (!hal_is_band_support(adapter, band))
+			continue;
+
+		for (bw = CHANNEL_WIDTH_40; bw <= CHANNEL_WIDTH_80; bw++) {
+			if (bw >= CHANNEL_WIDTH_160)
+				continue;
+			if (band == BAND_ON_2_4G && bw >= CHANNEL_WIDTH_80)
+				continue;
+
+			if (band == BAND_ON_2_4G)
+				ch_num = center_chs_2g_num(bw);
+			else
+				ch_num = center_chs_5g_num(bw);
+
+			if (ch_num == 0) {
+				rtw_warn_on(1);
+				break;
+			}
+
+			for (tlrs = TXPWR_LMT_RS_HT; tlrs < TXPWR_LMT_RS_NUM; tlrs++) {
+
+				if (band == BAND_ON_2_4G && tlrs == TXPWR_LMT_RS_VHT)
+					continue;
+				if (band == BAND_ON_5G && tlrs == TXPWR_LMT_RS_CCK)
+					continue;
+				if (bw > CHANNEL_WIDTH_20 && (tlrs == TXPWR_LMT_RS_CCK || tlrs == TXPWR_LMT_RS_OFDM))
+					continue;
+				if (bw > CHANNEL_WIDTH_40 && tlrs == TXPWR_LMT_RS_HT)
+					continue;
+				if (tlrs == TXPWR_LMT_RS_VHT && !IS_HARDWARE_TYPE_JAGUAR_AND_JAGUAR2(adapter))
+					continue;
+
+				for (ntx_idx = RF_1TX; ntx_idx < MAX_TX_COUNT; ntx_idx++) {
+					struct txpwr_lmt_ent *ent;
+					_list *cur, *head;
+
+					if (ntx_idx >= hal_spec->tx_nss_num)
+						continue;
+
+					/* bypass CCK multi-TX is not defined */
+					if (tlrs == TXPWR_LMT_RS_CCK && ntx_idx > RF_1TX) {
+						if (band == BAND_ON_2_4G
+							&& !(rfctl->txpwr_lmt_2g_cck_ofdm_state & (TXPWR_LMT_HAS_CCK_1T << ntx_idx)))
+							continue;
+					}
+
+					/* bypass OFDM multi-TX is not defined */
+					if (tlrs == TXPWR_LMT_RS_OFDM && ntx_idx > RF_1TX) {
+						if (band == BAND_ON_2_4G
+							&& !(rfctl->txpwr_lmt_2g_cck_ofdm_state & (TXPWR_LMT_HAS_OFDM_1T << ntx_idx)))
+							continue;
+						#ifdef CONFIG_IEEE80211_BAND_5GHZ
+						if (band == BAND_ON_5G
+							&& !(rfctl->txpwr_lmt_5g_cck_ofdm_state & (TXPWR_LMT_HAS_OFDM_1T << ntx_idx)))
+							continue;
+						#endif
+					}
+
+					/* bypass 5G 20M, 40M pure reference */
+					#ifdef CONFIG_IEEE80211_BAND_5GHZ
+					if (band == BAND_ON_5G && (bw == CHANNEL_WIDTH_20 || bw == CHANNEL_WIDTH_40)) {
+						if (rfctl->txpwr_lmt_5g_20_40_ref == TXPWR_LMT_REF_HT_FROM_VHT) {
+							if (tlrs == TXPWR_LMT_RS_HT)
+								continue;
+						} else if (rfctl->txpwr_lmt_5g_20_40_ref == TXPWR_LMT_REF_VHT_FROM_HT) {
+							if (tlrs == TXPWR_LMT_RS_VHT && bw <= CHANNEL_WIDTH_40)
+								continue;
+						}
+					}
+					#endif
+
+					for (n = 0; n < ch_num; n++) {
+						u8 cch_by_bw[3];
+						u8 offset_by_bw; /* bitmap, 0 for lower, 1 for upper */
+						u8 bw_pos;
+						s8 lmt[3];
+
+						if (band == BAND_ON_2_4G)
+							cch = center_chs_2g(bw, n);
+						else
+							cch = center_chs_5g(bw, n);
+
+						if (cch == 0) {
+							rtw_warn_on(1);
+							break;
+						}
+
+						_rtw_memset(cch_by_bw, 0, 3);
+						cch_by_bw[bw] = cch;
+						offset_by_bw = 0x01;
+
+						do {
+							for (bw_pos = bw; bw_pos >= CHANNEL_WIDTH_40; bw_pos--)
+								cch_by_bw[bw_pos - 1] = rtw_get_scch_by_cch_offset(cch_by_bw[bw_pos], bw_pos, offset_by_bw & BIT(bw_pos) ? HAL_PRIME_CHNL_OFFSET_UPPER : HAL_PRIME_CHNL_OFFSET_LOWER);
+
+							head = &rfctl->txpwr_lmt_list;
+							cur = get_next(head);
+							while ((rtw_end_of_queue_search(head, cur)) == _FALSE) {
+								ent = LIST_CONTAINOR(cur, struct txpwr_lmt_ent, list);
+								cur = get_next(cur);
+
+								for (bw_pos = bw; bw_pos < CHANNEL_WIDTH_160; bw_pos--)
+									lmt[bw_pos] = phy_get_txpwr_lmt_abs(adapter, ent->regd_name, band, bw_pos, tlrs, ntx_idx, cch_by_bw[bw_pos], 0);
+
+								for (bw_pos = bw; bw_pos > CHANNEL_WIDTH_20; bw_pos--)
+									if (lmt[bw_pos] > lmt[bw_pos - 1])
+										break;
+								if (bw_pos == CHANNEL_WIDTH_20)
+									continue;
+
+								RTW_PRINT_SEL(RTW_DBGDUMP, "[%s][%s][%s][%uT][%-4s] cch:"
+									, band_str(band)
+									, ch_width_str(bw)
+									, txpwr_lmt_rs_str(tlrs)
+									, ntx_idx + 1
+									, ent->regd_name
+								);
+								for (bw_pos = bw; bw_pos < CHANNEL_WIDTH_160; bw_pos--)
+									_RTW_PRINT_SEL(RTW_DBGDUMP, "%03u ", cch_by_bw[bw_pos]);
+								_RTW_PRINT_SEL(RTW_DBGDUMP, "limit:");
+								for (bw_pos = bw; bw_pos < CHANNEL_WIDTH_160; bw_pos--) {
+									if (lmt[bw_pos] == hal_spec->txgi_max)
+										_RTW_PRINT_SEL(RTW_DBGDUMP, "N/A ");
+									else if (lmt[bw_pos] > -hal_spec->txgi_pdbm && lmt[bw_pos] < 0) /* -1 < value < 0 */
+										_RTW_PRINT_SEL(RTW_DBGDUMP, "-0.%d", (rtw_abs(lmt[bw_pos]) % hal_spec->txgi_pdbm) * 100 / hal_spec->txgi_pdbm);
+									else if (lmt[bw_pos] % hal_spec->txgi_pdbm)
+										_RTW_PRINT_SEL(RTW_DBGDUMP, "%2d.%d ", lmt[bw_pos] / hal_spec->txgi_pdbm, (rtw_abs(lmt[bw_pos]) % hal_spec->txgi_pdbm) * 100 / hal_spec->txgi_pdbm);
+									else
+										_RTW_PRINT_SEL(RTW_DBGDUMP, "%2d ", lmt[bw_pos] / hal_spec->txgi_pdbm);
+								}
+								_RTW_PRINT_SEL(RTW_DBGDUMP, "\n");
+							}
+							for (bw_pos = bw; bw_pos < CHANNEL_WIDTH_160; bw_pos--)
+								lmt[bw_pos] = phy_get_txpwr_lmt_abs(adapter, regd_str(TXPWR_LMT_WW), band, bw_pos, tlrs, ntx_idx, cch_by_bw[bw_pos], 0);
+
+							for (bw_pos = bw; bw_pos > CHANNEL_WIDTH_20; bw_pos--)
+								if (lmt[bw_pos] > lmt[bw_pos - 1])
+									break;
+							if (bw_pos != CHANNEL_WIDTH_20) {
+								RTW_PRINT_SEL(RTW_DBGDUMP, "[%s][%s][%s][%uT][%-4s] cch:"
+									, band_str(band)
+									, ch_width_str(bw)
+									, txpwr_lmt_rs_str(tlrs)
+									, ntx_idx + 1
+									, regd_str(TXPWR_LMT_WW)
+								);
+								for (bw_pos = bw; bw_pos < CHANNEL_WIDTH_160; bw_pos--)
+									_RTW_PRINT_SEL(RTW_DBGDUMP, "%03u ", cch_by_bw[bw_pos]);
+								_RTW_PRINT_SEL(RTW_DBGDUMP, "limit:");
+								for (bw_pos = bw; bw_pos < CHANNEL_WIDTH_160; bw_pos--) {
+									if (lmt[bw_pos] == hal_spec->txgi_max)
+										_RTW_PRINT_SEL(RTW_DBGDUMP, "N/A ");
+									else if (lmt[bw_pos] > -hal_spec->txgi_pdbm && lmt[bw_pos] < 0) /* -1 < value < 0 */
+										_RTW_PRINT_SEL(RTW_DBGDUMP, "-0.%d", (rtw_abs(lmt[bw_pos]) % hal_spec->txgi_pdbm) * 100 / hal_spec->txgi_pdbm);
+									else if (lmt[bw_pos] % hal_spec->txgi_pdbm)
+										_RTW_PRINT_SEL(RTW_DBGDUMP, "%2d.%d ", lmt[bw_pos] / hal_spec->txgi_pdbm, (rtw_abs(lmt[bw_pos]) % hal_spec->txgi_pdbm) * 100 / hal_spec->txgi_pdbm);
+									else
+										_RTW_PRINT_SEL(RTW_DBGDUMP, "%2d ", lmt[bw_pos] / hal_spec->txgi_pdbm);
+								}
+								_RTW_PRINT_SEL(RTW_DBGDUMP, "\n");
+							}
+
+							offset_by_bw += 2;
+							if (offset_by_bw & BIT(bw + 1))
+								break;
+						} while (1); /* loop for all ch combinations */
+					} /* loop for center channels */
+				} /* loop fo each ntx_idx */
+			} /* loop for tlrs */
+		} /* loop for bandwidth */
+	} /* loop for band */
+}
+#endif /* DBG_TXPWR_LMT_BAND_CHK */
+
+static void phy_txpwr_lmt_post_hdl(_adapter *adapter)
+{
+	struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter);
+	_irqL irqL;
+
+	_enter_critical_mutex(&rfctl->txpwr_lmt_mutex, &irqL);
+
+#ifdef CONFIG_IEEE80211_BAND_5GHZ
+	if (IS_HARDWARE_TYPE_JAGUAR_AND_JAGUAR2(adapter))
+		phy_txpwr_lmt_cross_ref_ht_vht(adapter);
+#endif
+	phy_txpwr_lmt_cck_ofdm_mt_chk(adapter);
+
+#if DBG_TXPWR_LMT_BAND_CHK
+	phy_txpwr_limit_bandwidth_chk(adapter);
+#endif
+
+	_exit_critical_mutex(&rfctl->txpwr_lmt_mutex, &irqL);
+}
+
+BOOLEAN
+GetS1ByteIntegerFromStringInDecimal(
+	IN		char	*str,
+	IN OUT	s8		*val
+)
+{
+	u8 negative = 0;
+	u16 i = 0;
+
+	*val = 0;
+
+	while (str[i] != '\0') {
+		if (i == 0 && (str[i] == '+' || str[i] == '-')) {
+			if (str[i] == '-')
+				negative = 1;
+		} else if (str[i] >= '0' && str[i] <= '9') {
+			*val *= 10;
+			*val += (str[i] - '0');
+		} else
+			return _FALSE;
+		++i;
+	}
+
+	if (negative)
+		*val = -*val;
+
+	return _TRUE;
+}
+#endif /* CONFIG_TXPWR_LIMIT */
+
+/*
+* phy_set_tx_power_limit - Parsing TX power limit from phydm array, called by odm_ConfigBB_TXPWR_LMT_XXX in phydm
+*/
+VOID
+phy_set_tx_power_limit(
+	IN	struct dm_struct		*pDM_Odm,
+	IN	u8				*Regulation,
+	IN	u8				*Band,
+	IN	u8				*Bandwidth,
+	IN	u8				*RateSection,
+	IN	u8				*ntx,
+	IN	u8				*Channel,
+	IN	u8				*PowerLimit
+)
+{
+#ifdef CONFIG_TXPWR_LIMIT
+	PADAPTER Adapter = pDM_Odm->adapter;
+	HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
+	struct hal_spec_t *hal_spec = GET_HAL_SPEC(Adapter);
+	u8 band = 0, bandwidth = 0, tlrs = 0, channel;
+	u8 ntx_idx;
+	s8 powerLimit = 0, prevPowerLimit, channelIndex;
+	s8 ww_lmt_val = phy_txpwr_ww_lmt_value(Adapter);
+
+	if (0)
+		RTW_INFO("Index of power limit table [regulation %s][band %s][bw %s][rate section %s][ntx %s][chnl %s][val %s]\n"
+			, Regulation, Band, Bandwidth, RateSection, ntx, Channel, PowerLimit);
+
+	if (GetU1ByteIntegerFromStringInDecimal((char *)Channel, &channel) == _FALSE
+		|| GetS1ByteIntegerFromStringInDecimal((char *)PowerLimit, &powerLimit) == _FALSE
+	) {
+		RTW_PRINT("Illegal index of power limit table [ch %s][val %s]\n", Channel, PowerLimit);
+		return;
+	}
+
+	if (powerLimit != ww_lmt_val) {
+		if (powerLimit < -hal_spec->txgi_max || powerLimit > hal_spec->txgi_max)
+			RTW_PRINT("Illegal power limit value [ch %s][val %s]\n", Channel, PowerLimit);
+
+		if (powerLimit > hal_spec->txgi_max)
+			powerLimit = hal_spec->txgi_max;
+		else if (powerLimit < -hal_spec->txgi_max)
+			powerLimit =  ww_lmt_val + 1;
+	}
+
+	if (eqNByte(RateSection, (u8 *)("CCK"), 3))
+		tlrs = TXPWR_LMT_RS_CCK;
+	else if (eqNByte(RateSection, (u8 *)("OFDM"), 4))
+		tlrs = TXPWR_LMT_RS_OFDM;
+	else if (eqNByte(RateSection, (u8 *)("HT"), 2))
+		tlrs = TXPWR_LMT_RS_HT;
+	else if (eqNByte(RateSection, (u8 *)("VHT"), 3))
+		tlrs = TXPWR_LMT_RS_VHT;
+	else {
+		RTW_PRINT("Wrong rate section:%s\n", RateSection);
+		return;
+	}
+
+	if (eqNByte(ntx, (u8 *)("1T"), 2))
+		ntx_idx = RF_1TX;
+	else if (eqNByte(ntx, (u8 *)("2T"), 2))
+		ntx_idx = RF_2TX;
+	else if (eqNByte(ntx, (u8 *)("3T"), 2))
+		ntx_idx = RF_3TX;
+	else if (eqNByte(ntx, (u8 *)("4T"), 2))
+		ntx_idx = RF_4TX;
+	else {
+		RTW_PRINT("Wrong tx num:%s\n", ntx);
+		return;
+	}
+
+	if (eqNByte(Bandwidth, (u8 *)("20M"), 3))
+		bandwidth = CHANNEL_WIDTH_20;
+	else if (eqNByte(Bandwidth, (u8 *)("40M"), 3))
+		bandwidth = CHANNEL_WIDTH_40;
+	else if (eqNByte(Bandwidth, (u8 *)("80M"), 3))
+		bandwidth = CHANNEL_WIDTH_80;
+	else if (eqNByte(Bandwidth, (u8 *)("160M"), 4))
+		bandwidth = CHANNEL_WIDTH_160;
+	else {
+		RTW_PRINT("unknown bandwidth: %s\n", Bandwidth);
+		return;
+	}
+
+	if (eqNByte(Band, (u8 *)("2.4G"), 4)) {
+		band = BAND_ON_2_4G;
+		channelIndex = phy_GetChannelIndexOfTxPowerLimit(BAND_ON_2_4G, channel);
+
+		if (channelIndex == -1) {
+			RTW_PRINT("unsupported channel: %d at 2.4G\n", channel);
+			return;
+		}
+
+		if (bandwidth >= MAX_2_4G_BANDWIDTH_NUM) {
+			RTW_PRINT("unsupported bandwidth: %s at 2.4G\n", Bandwidth);
+			return;
+		}
+
+		rtw_txpwr_lmt_add(adapter_to_rfctl(Adapter), Regulation, band, bandwidth, tlrs, ntx_idx, channelIndex, powerLimit);
+	}
+#ifdef CONFIG_IEEE80211_BAND_5GHZ
+	else if (eqNByte(Band, (u8 *)("5G"), 2)) {
+		band = BAND_ON_5G;
+		channelIndex = phy_GetChannelIndexOfTxPowerLimit(BAND_ON_5G, channel);
+
+		if (channelIndex == -1) {
+			RTW_PRINT("unsupported channel: %d at 5G\n", channel);
+			return;
+		}
+
+		rtw_txpwr_lmt_add(adapter_to_rfctl(Adapter), Regulation, band, bandwidth, tlrs, ntx_idx, channelIndex, powerLimit);
+	}
+#endif
+	else {
+		RTW_PRINT("unknown/unsupported band:%s\n", Band);
+		return;
+	}
+#endif
+}
+
+u8
+phy_get_tx_power_index(
+	IN	PADAPTER			pAdapter,
+	IN	enum rf_path			RFPath,
+	IN	u8					Rate,
+	IN	enum channel_width	BandWidth,
+	IN	u8					Channel
+)
+{
+	return rtw_hal_get_tx_power_index(pAdapter, RFPath, Rate, BandWidth, Channel, NULL);
+}
+
+VOID
+PHY_SetTxPowerIndex(
+	IN	PADAPTER		pAdapter,
+	IN	u32				PowerIndex,
+	IN	enum rf_path		RFPath,
+	IN	u8				Rate
+)
+{
+	rtw_hal_set_tx_power_index(pAdapter, PowerIndex, RFPath, Rate);
+}
+
+void dump_tx_power_idx_title(void *sel, _adapter *adapter)
+{
+	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
+	u8 bw = hal_data->current_channel_bw;
+
+	RTW_PRINT_SEL(sel, "%s", ch_width_str(bw));
+	if (bw >= CHANNEL_WIDTH_80)
+		_RTW_PRINT_SEL(sel, ", cch80:%u", hal_data->cch_80);
+	if (bw >= CHANNEL_WIDTH_40)
+		_RTW_PRINT_SEL(sel, ", cch40:%u", hal_data->cch_40);
+	_RTW_PRINT_SEL(sel, ", cch20:%u\n", hal_data->cch_20);
+
+	RTW_PRINT_SEL(sel, "%-4s %-9s %2s %-3s %-4s %-3s %-4s %-4s %-3s %-5s\n"
+		, "path", "rate", "", "pwr", "base", "", "(byr", "lmt)", "tpt", "ebias");
+}
+
+void dump_tx_power_idx_by_path_rs(void *sel, _adapter *adapter, u8 rfpath, u8 rs)
+{
+	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
+	struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter);
+	u8 power_idx;
+	struct txpwr_idx_comp tic;
+	u8 tx_num, i;
+	u8 band = hal_data->current_band_type;
+	u8 cch = hal_data->current_channel;
+	u8 bw = hal_data->current_channel_bw;
+
+	if (!HAL_SPEC_CHK_RF_PATH(hal_spec, band, rfpath))
+		return;
+
+	if (rs >= RATE_SECTION_NUM)
+		return;
+
+	tx_num = rate_section_to_tx_num(rs);
+	if (tx_num >= hal_spec->tx_nss_num || tx_num >= hal_spec->max_tx_cnt)
+		return;
+
+	if (band == BAND_ON_5G && IS_CCK_RATE_SECTION(rs))
+		return;
+
+	if (IS_VHT_RATE_SECTION(rs) && !IS_HARDWARE_TYPE_JAGUAR_AND_JAGUAR2(adapter))
+		return;
+
+	for (i = 0; i < rates_by_sections[rs].rate_num; i++) {
+		power_idx = rtw_hal_get_tx_power_index(adapter, rfpath, rates_by_sections[rs].rates[i], bw, cch, &tic);
+
+		RTW_PRINT_SEL(sel, "%4c %9s %uT %3u %4u %3d (%3d %3d) %3d %5d\n"
+			, rf_path_char(rfpath), MGN_RATE_STR(rates_by_sections[rs].rates[i]), tic.ntx_idx + 1
+			, power_idx, tic.base, (tic.by_rate > tic.limit ? tic.limit : tic.by_rate), tic.by_rate, tic.limit, tic.tpt, tic.ebias);
+	}
+}
+
+void dump_tx_power_idx(void *sel, _adapter *adapter)
+{
+	u8 rfpath, rs;
+
+	dump_tx_power_idx_title(sel, adapter);
+	for (rfpath = RF_PATH_A; rfpath < RF_PATH_MAX; rfpath++)
+		for (rs = CCK; rs < RATE_SECTION_NUM; rs++)
+			dump_tx_power_idx_by_path_rs(sel, adapter, rfpath, rs);
+}
+
+bool phy_is_tx_power_limit_needed(_adapter *adapter)
+{
+	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
+	struct registry_priv *regsty = dvobj_to_regsty(adapter_to_dvobj(adapter));
+
+#ifdef CONFIG_TXPWR_LIMIT
+	if (regsty->RegEnableTxPowerLimit == 1
+		|| (regsty->RegEnableTxPowerLimit == 2 && hal_data->EEPROMRegulatory == 1))
+		return _TRUE;
+#endif
+
+	return _FALSE;
+}
+
+bool phy_is_tx_power_by_rate_needed(_adapter *adapter)
+{
+	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
+	struct registry_priv *regsty = dvobj_to_regsty(adapter_to_dvobj(adapter));
+
+	if (regsty->RegEnableTxPowerByRate == 1
+		|| (regsty->RegEnableTxPowerByRate == 2 && hal_data->EEPROMRegulatory != 2))
+		return _TRUE;
+	return _FALSE;
+}
+
+int phy_load_tx_power_by_rate(_adapter *adapter, u8 chk_file)
+{
+	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
+	struct registry_priv *regsty = dvobj_to_regsty(adapter_to_dvobj(adapter));
+	int ret = _FAIL;
+
+	hal_data->txpwr_by_rate_loaded = 0;
+	PHY_InitTxPowerByRate(adapter);
+
+	/* tx power limit is based on tx power by rate */
+	hal_data->txpwr_limit_loaded = 0;
+
+#ifdef CONFIG_LOAD_PHY_PARA_FROM_FILE
+	if (chk_file
+		&& phy_ConfigBBWithPgParaFile(adapter, PHY_FILE_PHY_REG_PG) == _SUCCESS
+	) {
+		hal_data->txpwr_by_rate_from_file = 1;
+		goto post_hdl;
+	}
+#endif
+
+#ifdef CONFIG_EMBEDDED_FWIMG
+	if (HAL_STATUS_SUCCESS == odm_config_bb_with_header_file(&hal_data->odmpriv, CONFIG_BB_PHY_REG_PG)) {
+		RTW_INFO("default power by rate loaded\n");
+		hal_data->txpwr_by_rate_from_file = 0;
+		goto post_hdl;
+	}
+#endif
+
+	RTW_ERR("%s():Read Tx power by rate fail\n", __func__);
+	goto exit;
+
+post_hdl:
+	if (hal_data->odmpriv.phy_reg_pg_value_type != PHY_REG_PG_EXACT_VALUE) {
+		rtw_warn_on(1);
+		goto exit;
+	}
+
+	PHY_TxPowerByRateConfiguration(adapter);
+	hal_data->txpwr_by_rate_loaded = 1;
+
+	ret = _SUCCESS;
+
+exit:
+	return ret;
+}
+
+#ifdef CONFIG_TXPWR_LIMIT
+int phy_load_tx_power_limit(_adapter *adapter, u8 chk_file)
+{
+	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
+	struct registry_priv *regsty = dvobj_to_regsty(adapter_to_dvobj(adapter));
+	struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter);
+	int ret = _FAIL;
+
+	hal_data->txpwr_limit_loaded = 0;
+	rtw_regd_exc_list_free(rfctl);
+	rtw_txpwr_lmt_list_free(rfctl);
+
+	if (!hal_data->txpwr_by_rate_loaded && regsty->target_tx_pwr_valid != _TRUE) {
+		RTW_ERR("%s():Read Tx power limit before target tx power is specify\n", __func__);
+		goto exit;
+	}
+
+#ifdef CONFIG_LOAD_PHY_PARA_FROM_FILE
+	if (chk_file
+		&& PHY_ConfigRFWithPowerLimitTableParaFile(adapter, PHY_FILE_TXPWR_LMT) == _SUCCESS
+	) {
+		hal_data->txpwr_limit_from_file = 1;
+		goto post_hdl;
+	}
+#endif
+
+#ifdef CONFIG_EMBEDDED_FWIMG
+	if (odm_config_rf_with_header_file(&hal_data->odmpriv, CONFIG_RF_TXPWR_LMT, RF_PATH_A) == HAL_STATUS_SUCCESS) {
+		RTW_INFO("default power limit loaded\n");
+		hal_data->txpwr_limit_from_file = 0;
+		goto post_hdl;
+	}
+#endif
+
+	RTW_ERR("%s():Read Tx power limit fail\n", __func__);
+	goto exit;
+
+post_hdl:
+	phy_txpwr_lmt_post_hdl(adapter);
+	rtw_txpwr_init_regd(rfctl);
+	hal_data->txpwr_limit_loaded = 1;
+	ret = _SUCCESS;
+
+exit:
+	return ret;
+}
+#endif /* CONFIG_TXPWR_LIMIT */
+
+void phy_load_tx_power_ext_info(_adapter *adapter, u8 chk_file)
+{
+	struct registry_priv *regsty = adapter_to_regsty(adapter);
+
+	/* check registy target tx power */
+	regsty->target_tx_pwr_valid = rtw_regsty_chk_target_tx_power_valid(adapter);
+
+	/* power by rate and limit */
+	if (phy_is_tx_power_by_rate_needed(adapter)
+		|| (phy_is_tx_power_limit_needed(adapter) && regsty->target_tx_pwr_valid != _TRUE)
+	)
+		phy_load_tx_power_by_rate(adapter, chk_file);
+
+#ifdef CONFIG_TXPWR_LIMIT
+	if (phy_is_tx_power_limit_needed(adapter))
+		phy_load_tx_power_limit(adapter, chk_file);
+#endif
+}
+
+inline void phy_reload_tx_power_ext_info(_adapter *adapter)
+{
+	phy_load_tx_power_ext_info(adapter, 1);
+}
+
+inline void phy_reload_default_tx_power_ext_info(_adapter *adapter)
+{
+	phy_load_tx_power_ext_info(adapter, 0);
+}
+
+void dump_tx_power_ext_info(void *sel, _adapter *adapter)
+{
+	struct registry_priv *regsty = adapter_to_regsty(adapter);
+	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
+
+	if (regsty->target_tx_pwr_valid == _TRUE)
+		RTW_PRINT_SEL(sel, "target_tx_power: from registry\n");
+	else if (phy_is_tx_power_by_rate_needed(adapter))
+		RTW_PRINT_SEL(sel, "target_tx_power: from power by rate\n"); 
+	else
+		RTW_PRINT_SEL(sel, "target_tx_power: unavailable\n");
+
+	RTW_PRINT_SEL(sel, "tx_power_by_rate: %s, %s, %s\n"
+		, phy_is_tx_power_by_rate_needed(adapter) ? "enabled" : "disabled"
+		, hal_data->txpwr_by_rate_loaded ? "loaded" : "unloaded"
+		, hal_data->txpwr_by_rate_from_file ? "file" : "default"
+	);
+
+	RTW_PRINT_SEL(sel, "tx_power_limit: %s, %s, %s\n"
+		, phy_is_tx_power_limit_needed(adapter) ? "enabled" : "disabled"
+		, hal_data->txpwr_limit_loaded ? "loaded" : "unloaded"
+		, hal_data->txpwr_limit_from_file ? "file" : "default"
+	);
+}
+
+void dump_target_tx_power(void *sel, _adapter *adapter)
+{
+	struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter);
+	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
+	struct registry_priv *regsty = adapter_to_regsty(adapter);
+	int path, tx_num, band, rs;
+	u8 target;
+
+	for (band = BAND_ON_2_4G; band <= BAND_ON_5G; band++) {
+		if (!hal_is_band_support(adapter, band))
+			continue;
+
+		for (path = 0; path < RF_PATH_MAX; path++) {
+			if (!HAL_SPEC_CHK_RF_PATH(hal_spec, band, path))
+				break;
+
+			RTW_PRINT_SEL(sel, "[%s][%c]%s\n", band_str(band), rf_path_char(path)
+				, (regsty->target_tx_pwr_valid == _FALSE && hal_data->txpwr_by_rate_undefined_band_path[band][path]) ? "(dup)" : "");
+
+			for (rs = 0; rs < RATE_SECTION_NUM; rs++) {
+				tx_num = rate_section_to_tx_num(rs);
+				if (tx_num >= hal_spec->tx_nss_num)
+					continue;
+
+				if (band == BAND_ON_5G && IS_CCK_RATE_SECTION(rs))
+					continue;
+
+				if (IS_VHT_RATE_SECTION(rs) && !IS_HARDWARE_TYPE_JAGUAR_AND_JAGUAR2(adapter))
+					continue;
+
+				target = PHY_GetTxPowerByRateBase(adapter, band, path, rs);
+
+				if (target % hal_spec->txgi_pdbm) {
+					_RTW_PRINT_SEL(sel, "%7s: %2d.%d\n", rate_section_str(rs)
+						, target / hal_spec->txgi_pdbm, (target % hal_spec->txgi_pdbm) * 100 / hal_spec->txgi_pdbm);
+				} else {
+					_RTW_PRINT_SEL(sel, "%7s: %5d\n", rate_section_str(rs)
+						, target / hal_spec->txgi_pdbm);
+				}
+			}
+		}
+	}
+
+exit:
+	return;
+}
+
+void dump_tx_power_by_rate(void *sel, _adapter *adapter)
+{
+	struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter);
+	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
+	int path, tx_num, band, n, rs;
+	u8 rate_num, max_rate_num, base;
+	s8 by_rate_offset;
+
+	for (band = BAND_ON_2_4G; band <= BAND_ON_5G; band++) {
+		if (!hal_is_band_support(adapter, band))
+			continue;
+
+		for (path = 0; path < RF_PATH_MAX; path++) {
+			if (!HAL_SPEC_CHK_RF_PATH(hal_spec, band, path))
+				break;
+
+			RTW_PRINT_SEL(sel, "[%s][%c]%s\n", band_str(band), rf_path_char(path)
+				, hal_data->txpwr_by_rate_undefined_band_path[band][path] ? "(dup)" : "");
+
+			for (rs = 0; rs < RATE_SECTION_NUM; rs++) {
+				tx_num = rate_section_to_tx_num(rs);
+				if (tx_num >= hal_spec->tx_nss_num)
+					continue;
+
+				if (band == BAND_ON_5G && IS_CCK_RATE_SECTION(rs))
+					continue;
+
+				if (IS_VHT_RATE_SECTION(rs) && !IS_HARDWARE_TYPE_JAGUAR_AND_JAGUAR2(adapter))
+					continue;
+
+				if (IS_HARDWARE_TYPE_JAGUAR_AND_JAGUAR2(adapter))
+					max_rate_num = 10;
+				else
+					max_rate_num = 8;
+				rate_num = rate_section_rate_num(rs);
+				base = PHY_GetTxPowerByRateBase(adapter, band, path, rs);
+
+				RTW_PRINT_SEL(sel, "%7s: ", rate_section_str(rs));
+
+				/* dump power by rate in db */
+				for (n = rate_num - 1; n >= 0; n--) {
+					by_rate_offset = PHY_GetTxPowerByRate(adapter, band, path, rates_by_sections[rs].rates[n]);
+
+					if ((base + by_rate_offset) % hal_spec->txgi_pdbm) {
+						_RTW_PRINT_SEL(sel, "%2d.%d ", (base + by_rate_offset) / hal_spec->txgi_pdbm
+							, ((base + by_rate_offset) % hal_spec->txgi_pdbm) * 100 / hal_spec->txgi_pdbm);
+					} else
+						_RTW_PRINT_SEL(sel, "%5d ", (base + by_rate_offset) / hal_spec->txgi_pdbm);
+				}
+				for (n = 0; n < max_rate_num - rate_num; n++)
+					_RTW_PRINT_SEL(sel, "%5s ", "");
+
+				_RTW_PRINT_SEL(sel, "|");
+
+				/* dump power by rate in offset */
+				for (n = rate_num - 1; n >= 0; n--) {
+					by_rate_offset = PHY_GetTxPowerByRate(adapter, band, path, rates_by_sections[rs].rates[n]);
+					_RTW_PRINT_SEL(sel, "%3d ", by_rate_offset);
+				}
+				RTW_PRINT_SEL(sel, "\n");
+
+			}
+		}
+	}
+}
+
+/*
+ * phy file path is stored in global char array rtw_phy_para_file_path
+ * need to care about racing
+ */
+int rtw_get_phy_file_path(_adapter *adapter, const char *file_name)
+{
+#ifdef CONFIG_LOAD_PHY_PARA_FROM_FILE
+	struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter);
+	int len = 0;
+
+	if (file_name) {
+		len += snprintf(rtw_phy_para_file_path, PATH_LENGTH_MAX, "%s", rtw_phy_file_path);
+		#if defined(CONFIG_MULTIDRV) || defined(REALTEK_CONFIG_PATH_WITH_IC_NAME_FOLDER)
+		len += snprintf(rtw_phy_para_file_path + len, PATH_LENGTH_MAX - len, "%s/", hal_spec->ic_name);
+		#endif
+		len += snprintf(rtw_phy_para_file_path + len, PATH_LENGTH_MAX - len, "%s", file_name);
+
+		return _TRUE;
+	}
+#endif
+	return _FALSE;
+}
+
+#ifdef CONFIG_LOAD_PHY_PARA_FROM_FILE
+int
+phy_ConfigMACWithParaFile(
+	IN	PADAPTER	Adapter,
+	IN	char		*pFileName
+)
+{
+	PHAL_DATA_TYPE	pHalData = GET_HAL_DATA(Adapter);
+	int	rlen = 0, rtStatus = _FAIL;
+	char	*szLine, *ptmp;
+	u32	u4bRegOffset, u4bRegValue, u4bMove;
+
+	if (!(Adapter->registrypriv.load_phy_file & LOAD_MAC_PARA_FILE))
+		return rtStatus;
+
+	_rtw_memset(pHalData->para_file_buf, 0, MAX_PARA_FILE_BUF_LEN);
+
+	if ((pHalData->mac_reg_len == 0) && (pHalData->mac_reg == NULL)) {
+		rtw_get_phy_file_path(Adapter, pFileName);
+		if (rtw_is_file_readable(rtw_phy_para_file_path) == _TRUE) {
+			rlen = rtw_retrieve_from_file(rtw_phy_para_file_path, pHalData->para_file_buf, MAX_PARA_FILE_BUF_LEN);
+			if (rlen > 0) {
+				rtStatus = _SUCCESS;
+				pHalData->mac_reg = rtw_zvmalloc(rlen);
+				if (pHalData->mac_reg) {
+					_rtw_memcpy(pHalData->mac_reg, pHalData->para_file_buf, rlen);
+					pHalData->mac_reg_len = rlen;
+				} else
+					RTW_INFO("%s mac_reg alloc fail !\n", __FUNCTION__);
+			}
+		}
+	} else {
+		if ((pHalData->mac_reg_len != 0) && (pHalData->mac_reg != NULL)) {
+			_rtw_memcpy(pHalData->para_file_buf, pHalData->mac_reg, pHalData->mac_reg_len);
+			rtStatus = _SUCCESS;
+		} else
+			RTW_INFO("%s(): Critical Error !!!\n", __FUNCTION__);
+	}
+
+	if (rtStatus == _SUCCESS) {
+		ptmp = pHalData->para_file_buf;
+		for (szLine = GetLineFromBuffer(ptmp); szLine != NULL; szLine = GetLineFromBuffer(ptmp)) {
+			if (!IsCommentString(szLine)) {
+				/* Get 1st hex value as register offset */
+				if (GetHexValueFromString(szLine, &u4bRegOffset, &u4bMove)) {
+					if (u4bRegOffset == 0xffff) {
+						/* Ending. */
+						break;
+					}
+
+					/* Get 2nd hex value as register value. */
+					szLine += u4bMove;
+					if (GetHexValueFromString(szLine, &u4bRegValue, &u4bMove))
+						rtw_write8(Adapter, u4bRegOffset, (u8)u4bRegValue);
+				}
+			}
+		}
+	} else
+		RTW_INFO("%s(): No File %s, Load from HWImg Array!\n", __FUNCTION__, pFileName);
+
+	return rtStatus;
+}
+
+int
+phy_ConfigBBWithParaFile(
+	IN	PADAPTER	Adapter,
+	IN	char		*pFileName,
+	IN	u32			ConfigType
+)
+{
+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(Adapter);
+	int	rlen = 0, rtStatus = _FAIL;
+	char	*szLine, *ptmp;
+	u32	u4bRegOffset, u4bRegValue, u4bMove;
+	char	*pBuf = NULL;
+	u32	*pBufLen = NULL;
+
+	if (!(Adapter->registrypriv.load_phy_file & LOAD_BB_PARA_FILE))
+		return rtStatus;
+
+	switch (ConfigType) {
+	case CONFIG_BB_PHY_REG:
+		pBuf = pHalData->bb_phy_reg;
+		pBufLen = &pHalData->bb_phy_reg_len;
+		break;
+	case CONFIG_BB_AGC_TAB:
+		pBuf = pHalData->bb_agc_tab;
+		pBufLen = &pHalData->bb_agc_tab_len;
+		break;
+	default:
+		RTW_INFO("Unknown ConfigType!! %d\r\n", ConfigType);
+		break;
+	}
+
+	_rtw_memset(pHalData->para_file_buf, 0, MAX_PARA_FILE_BUF_LEN);
+
+	if ((pBufLen != NULL) && (*pBufLen == 0) && (pBuf == NULL)) {
+		rtw_get_phy_file_path(Adapter, pFileName);
+		if (rtw_is_file_readable(rtw_phy_para_file_path) == _TRUE) {
+			rlen = rtw_retrieve_from_file(rtw_phy_para_file_path, pHalData->para_file_buf, MAX_PARA_FILE_BUF_LEN);
+			if (rlen > 0) {
+				rtStatus = _SUCCESS;
+				pBuf = rtw_zvmalloc(rlen);
+				if (pBuf) {
+					_rtw_memcpy(pBuf, pHalData->para_file_buf, rlen);
+					*pBufLen = rlen;
+
+					switch (ConfigType) {
+					case CONFIG_BB_PHY_REG:
+						pHalData->bb_phy_reg = pBuf;
+						break;
+					case CONFIG_BB_AGC_TAB:
+						pHalData->bb_agc_tab = pBuf;
+						break;
+					}
+				} else
+					RTW_INFO("%s(): ConfigType %d  alloc fail !\n", __FUNCTION__, ConfigType);
+			}
+		}
+	} else {
+		if ((pBufLen != NULL) && (*pBufLen != 0) && (pBuf != NULL)) {
+			_rtw_memcpy(pHalData->para_file_buf, pBuf, *pBufLen);
+			rtStatus = _SUCCESS;
+		} else
+			RTW_INFO("%s(): Critical Error !!!\n", __FUNCTION__);
+	}
+
+	if (rtStatus == _SUCCESS) {
+		ptmp = pHalData->para_file_buf;
+		for (szLine = GetLineFromBuffer(ptmp); szLine != NULL; szLine = GetLineFromBuffer(ptmp)) {
+			if (!IsCommentString(szLine)) {
+				/* Get 1st hex value as register offset. */
+				if (GetHexValueFromString(szLine, &u4bRegOffset, &u4bMove)) {
+					if (u4bRegOffset == 0xffff) {
+						/* Ending. */
+						break;
+					} else if (u4bRegOffset == 0xfe || u4bRegOffset == 0xffe) {
+#ifdef CONFIG_LONG_DELAY_ISSUE
+						rtw_msleep_os(50);
+#else
+						rtw_mdelay_os(50);
+#endif
+					} else if (u4bRegOffset == 0xfd)
+						rtw_mdelay_os(5);
+					else if (u4bRegOffset == 0xfc)
+						rtw_mdelay_os(1);
+					else if (u4bRegOffset == 0xfb)
+						rtw_udelay_os(50);
+					else if (u4bRegOffset == 0xfa)
+						rtw_udelay_os(5);
+					else if (u4bRegOffset == 0xf9)
+						rtw_udelay_os(1);
+
+					/* Get 2nd hex value as register value. */
+					szLine += u4bMove;
+					if (GetHexValueFromString(szLine, &u4bRegValue, &u4bMove)) {
+						/* RTW_INFO("[BB-ADDR]%03lX=%08lX\n", u4bRegOffset, u4bRegValue); */
+						phy_set_bb_reg(Adapter, u4bRegOffset, bMaskDWord, u4bRegValue);
+
+						if (u4bRegOffset == 0xa24)
+							pHalData->odmpriv.rf_calibrate_info.rega24 = u4bRegValue;
+
+						/* Add 1us delay between BB/RF register setting. */
+						rtw_udelay_os(1);
+					}
+				}
+			}
+		}
+	} else
+		RTW_INFO("%s(): No File %s, Load from HWImg Array!\n", __FUNCTION__, pFileName);
+
+	return rtStatus;
+}
+
+VOID
+phy_DecryptBBPgParaFile(
+	PADAPTER		Adapter,
+	char			*buffer
+)
+{
+	u32	i = 0, j = 0;
+	u8	map[95] = {0};
+	u8	currentChar;
+	char	*BufOfLines, *ptmp;
+
+	/* RTW_INFO("=====>phy_DecryptBBPgParaFile()\n"); */
+	/* 32 the ascii code of the first visable char, 126 the last one */
+	for (i = 0; i < 95; ++i)
+		map[i] = (u8)(94 - i);
+
+	ptmp = buffer;
+	i = 0;
+	for (BufOfLines = GetLineFromBuffer(ptmp); BufOfLines != NULL; BufOfLines = GetLineFromBuffer(ptmp)) {
+		/* RTW_INFO("Encrypted Line: %s\n", BufOfLines); */
+
+		for (j = 0; j < strlen(BufOfLines); ++j) {
+			currentChar = BufOfLines[j];
+
+			if (currentChar == '\0')
+				break;
+
+			currentChar -= (u8)((((i + j) * 3) % 128));
+
+			BufOfLines[j] = map[currentChar - 32] + 32;
+		}
+		/* RTW_INFO("Decrypted Line: %s\n", BufOfLines ); */
+		if (strlen(BufOfLines) != 0)
+			i++;
+		BufOfLines[strlen(BufOfLines)] = '\n';
+	}
+}
+
+#ifndef DBG_TXPWR_BY_RATE_FILE_PARSE
+#define DBG_TXPWR_BY_RATE_FILE_PARSE 0
+#endif
+
+int
+phy_ParseBBPgParaFile(
+	PADAPTER		Adapter,
+	char			*buffer
+)
+{
+	int	rtStatus = _FAIL;
+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(Adapter);
+	struct hal_spec_t *hal_spec = GET_HAL_SPEC(Adapter);
+	char	*szLine, *ptmp;
+	u32	u4bRegOffset, u4bRegMask, u4bRegValue;
+	u32	u4bMove;
+	BOOLEAN firstLine = _TRUE;
+	u8	tx_num = 0;
+	u8	band = 0, rf_path = 0;
+
+	if (Adapter->registrypriv.RegDecryptCustomFile == 1)
+		phy_DecryptBBPgParaFile(Adapter, buffer);
+
+	ptmp = buffer;
+	for (szLine = GetLineFromBuffer(ptmp); szLine != NULL; szLine = GetLineFromBuffer(ptmp)) {
+		if (isAllSpaceOrTab(szLine, sizeof(*szLine)))
+			continue;
+
+		if (!IsCommentString(szLine)) {
+			/* Get header info (relative value or exact value) */
+			if (firstLine) {
+				if (eqNByte(szLine, (u8 *)("#[v1]"), 5))
+					pHalData->odmpriv.phy_reg_pg_version = szLine[3] - '0';
+				else {
+					RTW_ERR("The format in PHY_REG_PG are invalid %s\n", szLine);
+					goto exit;
+				}
+
+				if (eqNByte(szLine + 5, (u8 *)("[Exact]#"), 8)) {
+					pHalData->odmpriv.phy_reg_pg_value_type = PHY_REG_PG_EXACT_VALUE;
+					firstLine = _FALSE;
+					continue;
+				} else {
+					RTW_ERR("The values in PHY_REG_PG are invalid %s\n", szLine);
+					goto exit;
+				}
+			}
+
+			if (pHalData->odmpriv.phy_reg_pg_version > 0) {
+				u32	index = 0, cnt = 0;
+
+				if (eqNByte(szLine, "0xffff", 6))
+					break;
+
+				if (!eqNByte("#[END]#", szLine, 7)) {
+					/* load the table label info */
+					if (szLine[0] == '#') {
+						index = 0;
+						if (eqNByte(szLine, "#[2.4G]" , 7)) {
+							band = BAND_ON_2_4G;
+							index += 8;
+						} else if (eqNByte(szLine, "#[5G]", 5)) {
+							band = BAND_ON_5G;
+							index += 6;
+						} else {
+							RTW_ERR("Invalid band %s in PHY_REG_PG.txt\n", szLine);
+							goto exit;
+						}
+
+						rf_path = szLine[index] - 'A';
+						if (DBG_TXPWR_BY_RATE_FILE_PARSE)
+							RTW_INFO(" Table label Band %d, RfPath %d\n", band, rf_path );
+					} else { /* load rows of tables */
+						if (szLine[1] == '1')
+							tx_num = RF_1TX;
+						else if (szLine[1] == '2')
+							tx_num = RF_2TX;
+						else if (szLine[1] == '3')
+							tx_num = RF_3TX;
+						else if (szLine[1] == '4')
+							tx_num = RF_4TX;
+						else {
+							RTW_ERR("Invalid row in PHY_REG_PG.txt '%c'(%d)\n", szLine[1], szLine[1]);
+							goto exit;
+						}
+
+						while (szLine[index] != ']')
+							++index;
+						++index;/* skip ] */
+
+						/* Get 2nd hex value as register offset. */
+						szLine += index;
+						if (GetHexValueFromString(szLine, &u4bRegOffset, &u4bMove))
+							szLine += u4bMove;
+						else
+							goto exit;
+
+						/* Get 2nd hex value as register mask. */
+						if (GetHexValueFromString(szLine, &u4bRegMask, &u4bMove))
+							szLine += u4bMove;
+						else
+							goto exit;
+
+						if (pHalData->odmpriv.phy_reg_pg_value_type == PHY_REG_PG_EXACT_VALUE) {
+							u32	combineValue = 0;
+							u8	integer = 0, fraction = 0;
+
+							if (GetFractionValueFromString(szLine, &integer, &fraction, &u4bMove))
+								szLine += u4bMove;
+							else
+								goto exit;
+
+							integer *= hal_spec->txgi_pdbm;
+							integer += ((u16)fraction * (u16)hal_spec->txgi_pdbm) / 100;
+							if (hal_spec->txgi_pdbm == 2)
+								combineValue |= (((integer / 10) << 4) + (integer % 10));
+							else
+								combineValue |= integer;
+
+							if (GetFractionValueFromString(szLine, &integer, &fraction, &u4bMove))
+								szLine += u4bMove;
+							else
+								goto exit;
+
+							integer *= hal_spec->txgi_pdbm;
+							integer += ((u16)fraction * (u16)hal_spec->txgi_pdbm) / 100;
+							combineValue <<= 8;
+							if (hal_spec->txgi_pdbm == 2)
+								combineValue |= (((integer / 10) << 4) + (integer % 10));
+							else
+								combineValue |= integer;
+
+							if (GetFractionValueFromString(szLine, &integer, &fraction, &u4bMove))
+								szLine += u4bMove;
+							else
+								goto exit;
+
+							integer *= hal_spec->txgi_pdbm;
+							integer += ((u16)fraction * (u16)hal_spec->txgi_pdbm) / 100;
+							combineValue <<= 8;
+							if (hal_spec->txgi_pdbm == 2)
+								combineValue |= (((integer / 10) << 4) + (integer % 10));
+							else
+								combineValue |= integer;
+
+							if (GetFractionValueFromString(szLine, &integer, &fraction, &u4bMove))
+								szLine += u4bMove;
+							else
+								goto exit;
+
+							integer *= hal_spec->txgi_pdbm;
+							integer += ((u16)fraction * (u16)hal_spec->txgi_pdbm) / 100;
+							combineValue <<= 8;
+							if (hal_spec->txgi_pdbm == 2)
+								combineValue |= (((integer / 10) << 4) + (integer % 10));
+							else
+								combineValue |= integer;
+
+							phy_store_tx_power_by_rate(Adapter, band, rf_path, tx_num, u4bRegOffset, u4bRegMask, combineValue);
+
+							if (DBG_TXPWR_BY_RATE_FILE_PARSE)
+								RTW_INFO("addr:0x%3x mask:0x%08x %dTx = 0x%08x\n", u4bRegOffset, u4bRegMask, tx_num, combineValue);
+						}
+					}
+				}
+			}
+		}
+	}
+
+	rtStatus = _SUCCESS;
+
+exit:
+	RTW_INFO("%s return %d\n", __func__, rtStatus);
+	return rtStatus;
+}
+
+int
+phy_ConfigBBWithPgParaFile(
+	IN	PADAPTER	Adapter,
+	IN	const char	*pFileName)
+{
+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(Adapter);
+	int	rlen = 0, rtStatus = _FAIL;
+
+	if (!(Adapter->registrypriv.load_phy_file & LOAD_BB_PG_PARA_FILE))
+		return rtStatus;
+
+	_rtw_memset(pHalData->para_file_buf, 0, MAX_PARA_FILE_BUF_LEN);
+
+	if (pHalData->bb_phy_reg_pg == NULL) {
+		rtw_get_phy_file_path(Adapter, pFileName);
+		if (rtw_is_file_readable(rtw_phy_para_file_path) == _TRUE) {
+			rlen = rtw_retrieve_from_file(rtw_phy_para_file_path, pHalData->para_file_buf, MAX_PARA_FILE_BUF_LEN);
+			if (rlen > 0) {
+				rtStatus = _SUCCESS;
+				pHalData->bb_phy_reg_pg = rtw_zvmalloc(rlen);
+				if (pHalData->bb_phy_reg_pg) {
+					_rtw_memcpy(pHalData->bb_phy_reg_pg, pHalData->para_file_buf, rlen);
+					pHalData->bb_phy_reg_pg_len = rlen;
+				} else
+					RTW_INFO("%s bb_phy_reg_pg alloc fail !\n", __FUNCTION__);
+			}
+		}
+	} else {
+		if ((pHalData->bb_phy_reg_pg_len != 0) && (pHalData->bb_phy_reg_pg != NULL)) {
+			_rtw_memcpy(pHalData->para_file_buf, pHalData->bb_phy_reg_pg, pHalData->bb_phy_reg_pg_len);
+			rtStatus = _SUCCESS;
+		} else
+			RTW_INFO("%s(): Critical Error !!!\n", __FUNCTION__);
+	}
+
+	if (rtStatus == _SUCCESS) {
+		/* RTW_INFO("phy_ConfigBBWithPgParaFile(): read %s ok\n", pFileName); */
+		rtStatus = phy_ParseBBPgParaFile(Adapter, pHalData->para_file_buf);
+	} else
+		RTW_INFO("%s(): No File %s, Load from HWImg Array!\n", __FUNCTION__, pFileName);
+
+	return rtStatus;
+}
+
+#if (MP_DRIVER == 1)
+
+int
+phy_ConfigBBWithMpParaFile(
+	IN	PADAPTER	Adapter,
+	IN	char		*pFileName
+)
+{
+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(Adapter);
+	int	rlen = 0, rtStatus = _FAIL;
+	char	*szLine, *ptmp;
+	u32	u4bRegOffset, u4bRegValue, u4bMove;
+
+	if (!(Adapter->registrypriv.load_phy_file & LOAD_BB_MP_PARA_FILE))
+		return rtStatus;
+
+	_rtw_memset(pHalData->para_file_buf, 0, MAX_PARA_FILE_BUF_LEN);
+
+	if ((pHalData->bb_phy_reg_mp_len == 0) && (pHalData->bb_phy_reg_mp == NULL)) {
+		rtw_get_phy_file_path(Adapter, pFileName);
+		if (rtw_is_file_readable(rtw_phy_para_file_path) == _TRUE) {
+			rlen = rtw_retrieve_from_file(rtw_phy_para_file_path, pHalData->para_file_buf, MAX_PARA_FILE_BUF_LEN);
+			if (rlen > 0) {
+				rtStatus = _SUCCESS;
+				pHalData->bb_phy_reg_mp = rtw_zvmalloc(rlen);
+				if (pHalData->bb_phy_reg_mp) {
+					_rtw_memcpy(pHalData->bb_phy_reg_mp, pHalData->para_file_buf, rlen);
+					pHalData->bb_phy_reg_mp_len = rlen;
+				} else
+					RTW_INFO("%s bb_phy_reg_mp alloc fail !\n", __FUNCTION__);
+			}
+		}
+	} else {
+		if ((pHalData->bb_phy_reg_mp_len != 0) && (pHalData->bb_phy_reg_mp != NULL)) {
+			_rtw_memcpy(pHalData->para_file_buf, pHalData->bb_phy_reg_mp, pHalData->bb_phy_reg_mp_len);
+			rtStatus = _SUCCESS;
+		} else
+			RTW_INFO("%s(): Critical Error !!!\n", __FUNCTION__);
+	}
+
+	if (rtStatus == _SUCCESS) {
+		/* RTW_INFO("phy_ConfigBBWithMpParaFile(): read %s ok\n", pFileName); */
+
+		ptmp = pHalData->para_file_buf;
+		for (szLine = GetLineFromBuffer(ptmp); szLine != NULL; szLine = GetLineFromBuffer(ptmp)) {
+			if (!IsCommentString(szLine)) {
+				/* Get 1st hex value as register offset. */
+				if (GetHexValueFromString(szLine, &u4bRegOffset, &u4bMove)) {
+					if (u4bRegOffset == 0xffff) {
+						/* Ending. */
+						break;
+					} else if (u4bRegOffset == 0xfe || u4bRegOffset == 0xffe) {
+#ifdef CONFIG_LONG_DELAY_ISSUE
+						rtw_msleep_os(50);
+#else
+						rtw_mdelay_os(50);
+#endif
+					} else if (u4bRegOffset == 0xfd)
+						rtw_mdelay_os(5);
+					else if (u4bRegOffset == 0xfc)
+						rtw_mdelay_os(1);
+					else if (u4bRegOffset == 0xfb)
+						rtw_udelay_os(50);
+					else if (u4bRegOffset == 0xfa)
+						rtw_udelay_os(5);
+					else if (u4bRegOffset == 0xf9)
+						rtw_udelay_os(1);
+
+					/* Get 2nd hex value as register value. */
+					szLine += u4bMove;
+					if (GetHexValueFromString(szLine, &u4bRegValue, &u4bMove)) {
+						/* RTW_INFO("[ADDR]%03lX=%08lX\n", u4bRegOffset, u4bRegValue); */
+						phy_set_bb_reg(Adapter, u4bRegOffset, bMaskDWord, u4bRegValue);
+
+						/* Add 1us delay between BB/RF register setting. */
+						rtw_udelay_os(1);
+					}
+				}
+			}
+		}
+	} else
+		RTW_INFO("%s(): No File %s, Load from HWImg Array!\n", __FUNCTION__, pFileName);
+
+	return rtStatus;
+}
+
+#endif
+
+int
+PHY_ConfigRFWithParaFile(
+	IN	PADAPTER	Adapter,
+	IN	char		*pFileName,
+	IN	enum rf_path		eRFPath
+)
+{
+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(Adapter);
+	int	rlen = 0, rtStatus = _FAIL;
+	char	*szLine, *ptmp;
+	u32	u4bRegOffset, u4bRegValue, u4bMove;
+	u16	i;
+	char	*pBuf = NULL;
+	u32	*pBufLen = NULL;
+
+	if (!(Adapter->registrypriv.load_phy_file & LOAD_RF_PARA_FILE))
+		return rtStatus;
+
+	switch (eRFPath) {
+	case RF_PATH_A:
+		pBuf = pHalData->rf_radio_a;
+		pBufLen = &pHalData->rf_radio_a_len;
+		break;
+	case RF_PATH_B:
+		pBuf = pHalData->rf_radio_b;
+		pBufLen = &pHalData->rf_radio_b_len;
+		break;
+	default:
+		RTW_INFO("Unknown RF path!! %d\r\n", eRFPath);
+		break;
+	}
+
+	_rtw_memset(pHalData->para_file_buf, 0, MAX_PARA_FILE_BUF_LEN);
+
+	if ((pBufLen != NULL) && (*pBufLen == 0) && (pBuf == NULL)) {
+		rtw_get_phy_file_path(Adapter, pFileName);
+		if (rtw_is_file_readable(rtw_phy_para_file_path) == _TRUE) {
+			rlen = rtw_retrieve_from_file(rtw_phy_para_file_path, pHalData->para_file_buf, MAX_PARA_FILE_BUF_LEN);
+			if (rlen > 0) {
+				rtStatus = _SUCCESS;
+				pBuf = rtw_zvmalloc(rlen);
+				if (pBuf) {
+					_rtw_memcpy(pBuf, pHalData->para_file_buf, rlen);
+					*pBufLen = rlen;
+
+					switch (eRFPath) {
+					case RF_PATH_A:
+						pHalData->rf_radio_a = pBuf;
+						break;
+					case RF_PATH_B:
+						pHalData->rf_radio_b = pBuf;
+						break;
+					default:
+						RTW_INFO("Unknown RF path!! %d\r\n", eRFPath);
+						break;
+					}
+				} else
+					RTW_INFO("%s(): eRFPath=%d  alloc fail !\n", __FUNCTION__, eRFPath);
+			}
+		}
+	} else {
+		if ((pBufLen != NULL) && (*pBufLen != 0) && (pBuf != NULL)) {
+			_rtw_memcpy(pHalData->para_file_buf, pBuf, *pBufLen);
+			rtStatus = _SUCCESS;
+		} else
+			RTW_INFO("%s(): Critical Error !!!\n", __FUNCTION__);
+	}
+
+	if (rtStatus == _SUCCESS) {
+		/* RTW_INFO("%s(): read %s successfully\n", __FUNCTION__, pFileName); */
+
+		ptmp = pHalData->para_file_buf;
+		for (szLine = GetLineFromBuffer(ptmp); szLine != NULL; szLine = GetLineFromBuffer(ptmp)) {
+			if (!IsCommentString(szLine)) {
+				/* Get 1st hex value as register offset. */
+				if (GetHexValueFromString(szLine, &u4bRegOffset, &u4bMove)) {
+					if (u4bRegOffset == 0xfe || u4bRegOffset == 0xffe) {
+						/* Deay specific ms. Only RF configuration require delay.												 */
+#ifdef CONFIG_LONG_DELAY_ISSUE
+						rtw_msleep_os(50);
+#else
+						rtw_mdelay_os(50);
+#endif
+					} else if (u4bRegOffset == 0xfd) {
+						/* delay_ms(5); */
+						for (i = 0; i < 100; i++)
+							rtw_udelay_os(MAX_STALL_TIME);
+					} else if (u4bRegOffset == 0xfc) {
+						/* delay_ms(1); */
+						for (i = 0; i < 20; i++)
+							rtw_udelay_os(MAX_STALL_TIME);
+					} else if (u4bRegOffset == 0xfb)
+						rtw_udelay_os(50);
+					else if (u4bRegOffset == 0xfa)
+						rtw_udelay_os(5);
+					else if (u4bRegOffset == 0xf9)
+						rtw_udelay_os(1);
+					else if (u4bRegOffset == 0xffff)
+						break;
+
+					/* Get 2nd hex value as register value. */
+					szLine += u4bMove;
+					if (GetHexValueFromString(szLine, &u4bRegValue, &u4bMove)) {
+						phy_set_rf_reg(Adapter, eRFPath, u4bRegOffset, bRFRegOffsetMask, u4bRegValue);
+
+						/* Temp add, for frequency lock, if no delay, that may cause */
+						/* frequency shift, ex: 2412MHz => 2417MHz */
+						/* If frequency shift, the following action may works. */
+						/* Fractional-N table in radio_a.txt */
+						/* 0x2a 0x00001		 */ /* channel 1 */
+						/* 0x2b 0x00808		frequency divider. */
+						/* 0x2b 0x53333 */
+						/* 0x2c 0x0000c */
+						rtw_udelay_os(1);
+					}
+				}
+			}
+		}
+	} else
+		RTW_INFO("%s(): No File %s, Load from HWImg Array!\n", __FUNCTION__, pFileName);
+
+	return rtStatus;
+}
+
+VOID
+initDeltaSwingIndexTables(
+	PADAPTER	Adapter,
+	char		*Band,
+	char		*Path,
+	char		*Sign,
+	char		*Channel,
+	char		*Rate,
+	char		*Data
+)
+{
+#define STR_EQUAL_5G(_band, _path, _sign, _rate, _chnl) \
+	((strcmp(Band, _band) == 0) && (strcmp(Path, _path) == 0) && (strcmp(Sign, _sign) == 0) &&\
+	 (strcmp(Rate, _rate) == 0) && (strcmp(Channel, _chnl) == 0)\
+	)
+#define STR_EQUAL_2G(_band, _path, _sign, _rate) \
+	((strcmp(Band, _band) == 0) && (strcmp(Path, _path) == 0) && (strcmp(Sign, _sign) == 0) &&\
+	 (strcmp(Rate, _rate) == 0)\
+	)
+
+#define STORE_SWING_TABLE(_array, _iteratedIdx) \
+	do {	\
+	for (token = strsep(&Data, delim); token != NULL; token = strsep(&Data, delim)) {\
+		sscanf(token, "%d", &idx);\
+		_array[_iteratedIdx++] = (u8)idx;\
+	} } while (0)\
+
+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(Adapter);
+	struct dm_struct		*pDM_Odm = &pHalData->odmpriv;
+	struct dm_rf_calibration_struct	*pRFCalibrateInfo = &(pDM_Odm->rf_calibrate_info);
+	u32	j = 0;
+	char	*token;
+	char	delim[] = ",";
+	u32	idx = 0;
+
+	/* RTW_INFO("===>initDeltaSwingIndexTables(): Band: %s;\nPath: %s;\nSign: %s;\nChannel: %s;\nRate: %s;\n, Data: %s;\n",  */
+	/*	Band, Path, Sign, Channel, Rate, Data); */
+
+	if (STR_EQUAL_2G("2G", "A", "+", "CCK"))
+		STORE_SWING_TABLE(pRFCalibrateInfo->delta_swing_table_idx_2g_cck_a_p, j);
+	else if (STR_EQUAL_2G("2G", "A", "-", "CCK"))
+		STORE_SWING_TABLE(pRFCalibrateInfo->delta_swing_table_idx_2g_cck_a_n, j);
+	else if (STR_EQUAL_2G("2G", "B", "+", "CCK"))
+		STORE_SWING_TABLE(pRFCalibrateInfo->delta_swing_table_idx_2g_cck_b_p, j);
+	else if (STR_EQUAL_2G("2G", "B", "-", "CCK"))
+		STORE_SWING_TABLE(pRFCalibrateInfo->delta_swing_table_idx_2g_cck_b_n, j);
+	else if (STR_EQUAL_2G("2G", "A", "+", "ALL"))
+		STORE_SWING_TABLE(pRFCalibrateInfo->delta_swing_table_idx_2ga_p, j);
+	else if (STR_EQUAL_2G("2G", "A", "-", "ALL"))
+		STORE_SWING_TABLE(pRFCalibrateInfo->delta_swing_table_idx_2ga_n, j);
+	else if (STR_EQUAL_2G("2G", "B", "+", "ALL"))
+		STORE_SWING_TABLE(pRFCalibrateInfo->delta_swing_table_idx_2gb_p, j);
+	else if (STR_EQUAL_2G("2G", "B", "-", "ALL"))
+		STORE_SWING_TABLE(pRFCalibrateInfo->delta_swing_table_idx_2gb_n, j);
+	else if (STR_EQUAL_5G("5G", "A", "+", "ALL", "0"))
+		STORE_SWING_TABLE(pRFCalibrateInfo->delta_swing_table_idx_5ga_p[0], j);
+	else if (STR_EQUAL_5G("5G", "A", "-", "ALL", "0"))
+		STORE_SWING_TABLE(pRFCalibrateInfo->delta_swing_table_idx_5ga_n[0], j);
+	else if (STR_EQUAL_5G("5G", "B", "+", "ALL", "0"))
+		STORE_SWING_TABLE(pRFCalibrateInfo->delta_swing_table_idx_5gb_p[0], j);
+	else if (STR_EQUAL_5G("5G", "B", "-", "ALL", "0"))
+		STORE_SWING_TABLE(pRFCalibrateInfo->delta_swing_table_idx_5gb_n[0], j);
+	else if (STR_EQUAL_5G("5G", "A", "+", "ALL", "1"))
+		STORE_SWING_TABLE(pRFCalibrateInfo->delta_swing_table_idx_5ga_p[1], j);
+	else if (STR_EQUAL_5G("5G", "A", "-", "ALL", "1"))
+		STORE_SWING_TABLE(pRFCalibrateInfo->delta_swing_table_idx_5ga_n[1], j);
+	else if (STR_EQUAL_5G("5G", "B", "+", "ALL", "1"))
+		STORE_SWING_TABLE(pRFCalibrateInfo->delta_swing_table_idx_5gb_p[1], j);
+	else if (STR_EQUAL_5G("5G", "B", "-", "ALL", "1"))
+		STORE_SWING_TABLE(pRFCalibrateInfo->delta_swing_table_idx_5gb_n[1], j);
+	else if (STR_EQUAL_5G("5G", "A", "+", "ALL", "2"))
+		STORE_SWING_TABLE(pRFCalibrateInfo->delta_swing_table_idx_5ga_p[2], j);
+	else if (STR_EQUAL_5G("5G", "A", "-", "ALL", "2"))
+		STORE_SWING_TABLE(pRFCalibrateInfo->delta_swing_table_idx_5ga_n[2], j);
+	else if (STR_EQUAL_5G("5G", "B", "+", "ALL", "2"))
+		STORE_SWING_TABLE(pRFCalibrateInfo->delta_swing_table_idx_5gb_p[2], j);
+	else if (STR_EQUAL_5G("5G", "B", "-", "ALL", "2"))
+		STORE_SWING_TABLE(pRFCalibrateInfo->delta_swing_table_idx_5gb_n[2], j);
+	else if (STR_EQUAL_5G("5G", "A", "+", "ALL", "3"))
+		STORE_SWING_TABLE(pRFCalibrateInfo->delta_swing_table_idx_5ga_p[3], j);
+	else if (STR_EQUAL_5G("5G", "A", "-", "ALL", "3"))
+		STORE_SWING_TABLE(pRFCalibrateInfo->delta_swing_table_idx_5ga_n[3], j);
+	else if (STR_EQUAL_5G("5G", "B", "+", "ALL", "3"))
+		STORE_SWING_TABLE(pRFCalibrateInfo->delta_swing_table_idx_5gb_p[3], j);
+	else if (STR_EQUAL_5G("5G", "B", "-", "ALL", "3"))
+		STORE_SWING_TABLE(pRFCalibrateInfo->delta_swing_table_idx_5gb_n[3], j);
+	else
+		RTW_INFO("===>initDeltaSwingIndexTables(): The input is invalid!!\n");
+}
+
+int
+PHY_ConfigRFWithTxPwrTrackParaFile(
+	IN	PADAPTER		Adapter,
+	IN	char			*pFileName
+)
+{
+	HAL_DATA_TYPE		*pHalData = GET_HAL_DATA(Adapter);
+	struct dm_struct			*pDM_Odm = &pHalData->odmpriv;
+	struct dm_rf_calibration_struct		*pRFCalibrateInfo = &(pDM_Odm->rf_calibrate_info);
+	int	rlen = 0, rtStatus = _FAIL;
+	char	*szLine, *ptmp;
+	u32	i = 0, j = 0;
+	char	c = 0;
+
+	if (!(Adapter->registrypriv.load_phy_file & LOAD_RF_TXPWR_TRACK_PARA_FILE))
+		return rtStatus;
+
+	_rtw_memset(pHalData->para_file_buf, 0, MAX_PARA_FILE_BUF_LEN);
+
+	if ((pHalData->rf_tx_pwr_track_len == 0) && (pHalData->rf_tx_pwr_track == NULL)) {
+		rtw_get_phy_file_path(Adapter, pFileName);
+		if (rtw_is_file_readable(rtw_phy_para_file_path) == _TRUE) {
+			rlen = rtw_retrieve_from_file(rtw_phy_para_file_path, pHalData->para_file_buf, MAX_PARA_FILE_BUF_LEN);
+			if (rlen > 0) {
+				rtStatus = _SUCCESS;
+				pHalData->rf_tx_pwr_track = rtw_zvmalloc(rlen);
+				if (pHalData->rf_tx_pwr_track) {
+					_rtw_memcpy(pHalData->rf_tx_pwr_track, pHalData->para_file_buf, rlen);
+					pHalData->rf_tx_pwr_track_len = rlen;
+				} else
+					RTW_INFO("%s rf_tx_pwr_track alloc fail !\n", __FUNCTION__);
+			}
+		}
+	} else {
+		if ((pHalData->rf_tx_pwr_track_len != 0) && (pHalData->rf_tx_pwr_track != NULL)) {
+			_rtw_memcpy(pHalData->para_file_buf, pHalData->rf_tx_pwr_track, pHalData->rf_tx_pwr_track_len);
+			rtStatus = _SUCCESS;
+		} else
+			RTW_INFO("%s(): Critical Error !!!\n", __FUNCTION__);
+	}
+
+	if (rtStatus == _SUCCESS) {
+		/* RTW_INFO("%s(): read %s successfully\n", __FUNCTION__, pFileName); */
+
+		ptmp = pHalData->para_file_buf;
+		for (szLine = GetLineFromBuffer(ptmp); szLine != NULL; szLine = GetLineFromBuffer(ptmp)) {
+			if (!IsCommentString(szLine)) {
+				char	band[5] = "", path[5] = "", sign[5]  = "";
+				char	chnl[5] = "", rate[10] = "";
+				char	data[300] = ""; /* 100 is too small */
+
+				if (strlen(szLine) < 10 || szLine[0] != '[')
+					continue;
+
+				strncpy(band, szLine + 1, 2);
+				strncpy(path, szLine + 5, 1);
+				strncpy(sign, szLine + 8, 1);
+
+				i = 10; /* szLine+10 */
+				if (!ParseQualifiedString(szLine, &i, rate, '[', ']')) {
+					/* RTW_INFO("Fail to parse rate!\n"); */
+				}
+				if (!ParseQualifiedString(szLine, &i, chnl, '[', ']')) {
+					/* RTW_INFO("Fail to parse channel group!\n"); */
+				}
+				while (szLine[i] != '{' && i < strlen(szLine))
+					i++;
+				if (!ParseQualifiedString(szLine, &i, data, '{', '}')) {
+					/* RTW_INFO("Fail to parse data!\n"); */
+				}
+
+				initDeltaSwingIndexTables(Adapter, band, path, sign, chnl, rate, data);
+			}
+		}
+	} else
+		RTW_INFO("%s(): No File %s, Load from HWImg Array!\n", __FUNCTION__, pFileName);
+#if 0
+	for (i = 0; i < DELTA_SWINGIDX_SIZE; ++i) {
+		RTW_INFO("pRFCalibrateInfo->delta_swing_table_idx_2ga_p[%d] = %d\n", i, pRFCalibrateInfo->delta_swing_table_idx_2ga_p[i]);
+		RTW_INFO("pRFCalibrateInfo->delta_swing_table_idx_2ga_n[%d] = %d\n", i, pRFCalibrateInfo->delta_swing_table_idx_2ga_n[i]);
+		RTW_INFO("pRFCalibrateInfo->delta_swing_table_idx_2gb_p[%d] = %d\n", i, pRFCalibrateInfo->delta_swing_table_idx_2gb_p[i]);
+		RTW_INFO("pRFCalibrateInfo->delta_swing_table_idx_2gb_n[%d] = %d\n", i, pRFCalibrateInfo->delta_swing_table_idx_2gb_n[i]);
+		RTW_INFO("pRFCalibrateInfo->delta_swing_table_idx_2g_cck_a_p[%d] = %d\n", i, pRFCalibrateInfo->delta_swing_table_idx_2g_cck_a_p[i]);
+		RTW_INFO("pRFCalibrateInfo->delta_swing_table_idx_2g_cck_a_n[%d] = %d\n", i, pRFCalibrateInfo->delta_swing_table_idx_2g_cck_a_n[i]);
+		RTW_INFO("pRFCalibrateInfo->delta_swing_table_idx_2g_cck_b_p[%d] = %d\n", i, pRFCalibrateInfo->delta_swing_table_idx_2g_cck_b_p[i]);
+		RTW_INFO("pRFCalibrateInfo->delta_swing_table_idx_2g_cck_b_n[%d] = %d\n", i, pRFCalibrateInfo->delta_swing_table_idx_2g_cck_b_n[i]);
+
+		for (j = 0; j < 3; ++j) {
+			RTW_INFO("pRFCalibrateInfo->delta_swing_table_idx_5ga_p[%d][%d] = %d\n", j, i, pRFCalibrateInfo->delta_swing_table_idx_5ga_p[j][i]);
+			RTW_INFO("pRFCalibrateInfo->delta_swing_table_idx_5ga_n[%d][%d] = %d\n", j, i, pRFCalibrateInfo->delta_swing_table_idx_5ga_n[j][i]);
+			RTW_INFO("pRFCalibrateInfo->delta_swing_table_idx_5gb_p[%d][%d] = %d\n", j, i, pRFCalibrateInfo->delta_swing_table_idx_5gb_p[j][i]);
+			RTW_INFO("pRFCalibrateInfo->delta_swing_table_idx_5gb_n[%d][%d] = %d\n", j, i, pRFCalibrateInfo->delta_swing_table_idx_5gb_n[j][i]);
+		}
+	}
+#endif
+	return rtStatus;
+}
+
+#ifdef CONFIG_TXPWR_LIMIT
+
+#ifndef DBG_TXPWR_LMT_FILE_PARSE
+#define DBG_TXPWR_LMT_FILE_PARSE 0
+#endif
+
+#define PARSE_RET_NO_HDL	0
+#define PARSE_RET_SUCCESS	1
+#define PARSE_RET_FAIL		2
+
+/*
+* @@Ver=2.0
+* or
+* @@DomainCode=0x28, Regulation=C6
+* or
+* @@CountryCode=GB, Regulation=C7
+*/
+static u8 parse_reg_exc_config(_adapter *adapter, char *szLine)
+{
+#define VER_PREFIX "Ver="
+#define DOMAIN_PREFIX "DomainCode=0x"
+#define COUNTRY_PREFIX "CountryCode="
+#define REG_PREFIX "Regulation="
+
+	const u8 ver_prefix_len = strlen(VER_PREFIX);
+	const u8 domain_prefix_len = strlen(DOMAIN_PREFIX);
+	const u8 country_prefix_len = strlen(COUNTRY_PREFIX);
+	const u8 reg_prefix_len = strlen(REG_PREFIX);
+	u32 i, i_val_s, i_val_e;
+	u32 j;
+	u8 domain = 0xFF;
+	char *country = NULL;
+	u8 parse_reg = 0;
+
+	if (szLine[0] != '@' || szLine[1] != '@')
+		return PARSE_RET_NO_HDL;
+
+	i = 2;
+	if (strncmp(szLine + i, VER_PREFIX, ver_prefix_len) == 0)
+		; /* nothing to do */
+	else if (strncmp(szLine + i, DOMAIN_PREFIX, domain_prefix_len) == 0) {
+		/* get string after domain prefix to ',' */
+		i += domain_prefix_len;
+		i_val_s = i;
+		while (szLine[i] != ',') {
+			if (szLine[i] == '\0')
+				return PARSE_RET_FAIL;
+			i++;
+		}
+		i_val_e = i;
+
+		/* check if all hex */
+		for (j = i_val_s; j < i_val_e; j++)
+			if (IsHexDigit(szLine[j]) == _FALSE)
+				return PARSE_RET_FAIL;
+
+		/* get value from hex string */
+		if (sscanf(szLine + i_val_s, "%hhx", &domain) != 1)
+			return PARSE_RET_FAIL;
+
+		parse_reg = 1;
+	} else if (strncmp(szLine + i, COUNTRY_PREFIX, country_prefix_len) == 0) {
+		/* get string after country prefix to ',' */
+		i += country_prefix_len;
+		i_val_s = i;
+		while (szLine[i] != ',') {
+			if (szLine[i] == '\0')
+				return PARSE_RET_FAIL;
+			i++;
+		}
+		i_val_e = i;
+
+		if (i_val_e - i_val_s != 2)
+			return PARSE_RET_FAIL;
+
+		/* check if all alpha */
+		for (j = i_val_s; j < i_val_e; j++)
+			if (is_alpha(szLine[j]) == _FALSE)
+				return PARSE_RET_FAIL;
+
+		country = szLine + i_val_s;
+
+		parse_reg = 1;
+
+	} else
+		return PARSE_RET_FAIL;
+
+	if (parse_reg) {
+		/* move to 'R' */
+		while (szLine[i] != 'R') {
+			if (szLine[i] == '\0')
+				return PARSE_RET_FAIL;
+			i++;
+		}
+
+		/* check if matching regulation prefix */
+		if (strncmp(szLine + i, REG_PREFIX, reg_prefix_len) != 0)
+			return PARSE_RET_FAIL;
+
+		/* get string after regulation prefix ending with space */
+		i += reg_prefix_len;
+		i_val_s = i;
+		while (szLine[i] != ' ' && szLine[i] != '\t' && szLine[i] != '\0')
+			i++;
+
+		if (i == i_val_s)
+			return PARSE_RET_FAIL;
+
+		rtw_regd_exc_add_with_nlen(adapter_to_rfctl(adapter), country, domain, szLine + i_val_s, i - i_val_s);
+	}
+
+	return PARSE_RET_SUCCESS;
+}
+
+static int
+phy_ParsePowerLimitTableFile(
+	PADAPTER		Adapter,
+	char			*buffer
+)
+{
+#define LD_STAGE_EXC_MAPPING	0
+#define LD_STAGE_TAB_DEFINE		1
+#define LD_STAGE_TAB_START		2
+#define LD_STAGE_COLUMN_DEFINE	3
+#define LD_STAGE_CH_ROW			4
+
+	int	rtStatus = _FAIL;
+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(Adapter);
+	struct hal_spec_t *hal_spec = GET_HAL_SPEC(Adapter);
+	struct dm_struct	*pDM_Odm = &(pHalData->odmpriv);
+	u8	loadingStage = LD_STAGE_EXC_MAPPING;
+	u32	i = 0, forCnt = 0;
+	char	*szLine, *ptmp;
+	char band[10], bandwidth[10], rateSection[10], ntx[10], colNumBuf[10];
+	char **regulation = NULL;
+	u8	colNum = 0;
+
+	if (Adapter->registrypriv.RegDecryptCustomFile == 1)
+		phy_DecryptBBPgParaFile(Adapter, buffer);
+
+	ptmp = buffer;
+	for (szLine = GetLineFromBuffer(ptmp); szLine != NULL; szLine = GetLineFromBuffer(ptmp)) {
+		if (isAllSpaceOrTab(szLine, sizeof(*szLine)))
+			continue;
+		if (IsCommentString(szLine))
+			continue;
+
+		if (loadingStage == LD_STAGE_EXC_MAPPING) {
+			if (szLine[0] == '#' || szLine[1] == '#') {
+				loadingStage = LD_STAGE_TAB_DEFINE;
+				if (DBG_TXPWR_LMT_FILE_PARSE)
+					dump_regd_exc_list(RTW_DBGDUMP, adapter_to_rfctl(Adapter));
+			} else {
+				if (parse_reg_exc_config(Adapter, szLine) == PARSE_RET_FAIL) {
+					RTW_ERR("Fail to parse regulation exception ruls!\n");
+					goto exit;
+				}
+				continue;
+			}
+		}
+
+		if (loadingStage == LD_STAGE_TAB_DEFINE) {
+			/* read "##	2.4G, 20M, 1T, CCK" */
+			if (szLine[0] != '#' || szLine[1] != '#')
+				continue;
+
+			/* skip the space */
+			i = 2;
+			while (szLine[i] == ' ' || szLine[i] == '\t')
+				++i;
+
+			szLine[--i] = ' '; /* return the space in front of the regulation info */
+
+			/* Parse the label of the table */
+			_rtw_memset((PVOID) band, 0, 10);
+			_rtw_memset((PVOID) bandwidth, 0, 10);
+			_rtw_memset((PVOID) ntx, 0, 10);
+			_rtw_memset((PVOID) rateSection, 0, 10);
+			if (!ParseQualifiedString(szLine, &i, band, ' ', ',')) {
+				RTW_ERR("Fail to parse band!\n");
+				goto exit;
+			}
+			if (!ParseQualifiedString(szLine, &i, bandwidth, ' ', ',')) {
+				RTW_ERR("Fail to parse bandwidth!\n");
+				goto exit;
+			}
+			if (!ParseQualifiedString(szLine, &i, ntx, ' ', ',')) {
+				RTW_ERR("Fail to parse ntx!\n");
+				goto exit;
+			}
+			if (!ParseQualifiedString(szLine, &i, rateSection, ' ', ',')) {
+				RTW_ERR("Fail to parse rate!\n");
+				goto exit;
+			}
+
+			loadingStage = LD_STAGE_TAB_START;
+		} else if (loadingStage == LD_STAGE_TAB_START) {
+			/* read "##	START" */
+			if (szLine[0] != '#' || szLine[1] != '#')
+				continue;
+
+			/* skip the space */
+			i = 2;
+			while (szLine[i] == ' ' || szLine[i] == '\t')
+				++i;
+
+			if (!eqNByte((u8 *)(szLine + i), (u8 *)("START"), 5)) {
+				RTW_ERR("Missing \"##   START\" label\n");
+				goto exit;
+			}
+
+			loadingStage = LD_STAGE_COLUMN_DEFINE;
+		} else if (loadingStage == LD_STAGE_COLUMN_DEFINE) {
+			/* read "##	#5#	FCC	ETSI	MKK	IC	KCC" */
+			if (szLine[0] != '#' || szLine[1] != '#')
+				continue;
+
+			/* skip the space */
+			i = 2;
+			while (szLine[i] == ' ' || szLine[i] == '\t')
+				++i;
+
+			_rtw_memset((PVOID) colNumBuf, 0, 10);
+			if (!ParseQualifiedString(szLine, &i, colNumBuf, '#', '#')) {
+				RTW_ERR("Fail to parse column number!\n");
+				goto exit;
+			}
+			if (!GetU1ByteIntegerFromStringInDecimal(colNumBuf, &colNum)) {
+				RTW_ERR("Column number \"%s\" is not unsigned decimal\n", colNumBuf);
+				goto exit;
+			}
+			if (colNum == 0) {
+				RTW_ERR("Column number is 0\n");
+				goto exit;
+			}
+
+			if (DBG_TXPWR_LMT_FILE_PARSE)
+				RTW_PRINT("[%s][%s][%s][%s] column num:%d\n", band, bandwidth, rateSection, ntx, colNum);
+
+			regulation = (char **)rtw_zmalloc(sizeof(char *) * colNum);
+			if (!regulation) {
+				RTW_ERR("Regulation alloc fail\n");
+				goto exit;
+			}
+
+			for (forCnt = 0; forCnt < colNum; ++forCnt) {
+				u32 i_ns;
+
+				/* skip the space */
+				while (szLine[i] == ' ' || szLine[i] == '\t')
+					i++;
+				i_ns = i;
+
+				while (szLine[i] != ' ' && szLine[i] != '\t' && szLine[i] != '\0')
+					i++;
+
+				regulation[forCnt] = (char *)rtw_malloc(i - i_ns + 1);
+				if (!regulation[forCnt]) {
+					RTW_ERR("Regulation alloc fail\n");
+					goto exit;
+				}
+
+				_rtw_memcpy(regulation[forCnt], szLine + i_ns, i - i_ns);
+				regulation[forCnt][i - i_ns] = '\0';
+			}
+
+			if (DBG_TXPWR_LMT_FILE_PARSE) {
+				RTW_PRINT("column name:");
+				for (forCnt = 0; forCnt < colNum; ++forCnt)
+					_RTW_PRINT(" %s", regulation[forCnt]);
+				_RTW_PRINT("\n");
+			}
+
+			loadingStage = LD_STAGE_CH_ROW;
+		} else if (loadingStage == LD_STAGE_CH_ROW) {
+			char	channel[10] = {0}, powerLimit[10] = {0};
+			u8	cnt = 0;
+
+			/* the table ends */
+			if (szLine[0] == '#' && szLine[1] == '#') {
+				i = 2;
+				while (szLine[i] == ' ' || szLine[i] == '\t')
+					++i;
+
+				if (eqNByte((u8 *)(szLine + i), (u8 *)("END"), 3)) {
+					loadingStage = LD_STAGE_TAB_DEFINE;
+					if (regulation) {
+						for (forCnt = 0; forCnt < colNum; ++forCnt) {
+							if (regulation[forCnt]) {
+								rtw_mfree(regulation[forCnt], strlen(regulation[forCnt]) + 1);
+								regulation[forCnt] = NULL;
+							}
+						}
+						rtw_mfree((u8 *)regulation, sizeof(char *) * colNum);
+						regulation = NULL;
+					}
+					colNum = 0;
+					continue;
+				} else {
+					RTW_ERR("Missing \"##   END\" label\n");
+					goto exit;
+				}
+			}
+
+			if ((szLine[0] != 'c' && szLine[0] != 'C') ||
+				(szLine[1] != 'h' && szLine[1] != 'H')
+			) {
+				RTW_WARN("Wrong channel prefix: '%c','%c'(%d,%d)\n", szLine[0], szLine[1], szLine[0], szLine[1]);
+				continue;
+			}
+			i = 2;/* move to the  location behind 'h' */
+
+			/* load the channel number */
+			cnt = 0;
+			while (szLine[i] >= '0' && szLine[i] <= '9') {
+				channel[cnt] = szLine[i];
+				++cnt;
+				++i;
+			}
+			/* RTW_INFO("chnl %s!\n", channel); */
+
+			for (forCnt = 0; forCnt < colNum; ++forCnt) {
+				/* skip the space between channel number and the power limit value */
+				while (szLine[i] == ' ' || szLine[i] == '\t')
+					++i;
+
+				/* load the power limit value */
+				_rtw_memset((PVOID) powerLimit, 0, 10);
+
+				if (szLine[i] == 'W' && szLine[i + 1] == 'W') {
+					/*
+					* case "WW" assign special ww value
+					* means to get minimal limit in other regulations at same channel
+					*/
+					s8 ww_value = phy_txpwr_ww_lmt_value(Adapter);
+
+					sprintf(powerLimit, "%d", ww_value);
+					i += 2;
+
+				} else if (szLine[i] == 'N' && szLine[i + 1] == 'A') {
+					/*
+					* case "NA" assign max txgi value
+					* means no limitation
+					*/
+					sprintf(powerLimit, "%d", hal_spec->txgi_max);
+					i += 2;
+
+				} else if ((szLine[i] >= '0' && szLine[i] <= '9') || szLine[i] == '.'
+					|| szLine[i] == '+' || szLine[i] == '-'
+				){
+					/* case of dBm value */
+					u8 integer = 0, fraction = 0, negative = 0;
+					u32 u4bMove;
+					s8 lmt = 0;
+
+					if (szLine[i] == '+' || szLine[i] == '-') {
+						if (szLine[i] == '-')
+							negative = 1;
+						i++;
+					}
+
+					if (GetFractionValueFromString(&szLine[i], &integer, &fraction, &u4bMove))
+						i += u4bMove;
+					else {
+						RTW_ERR("Limit \"%s\" is not valid decimal\n", &szLine[i]);
+						goto exit;
+					}
+
+					/* transform to string of value in unit of txgi */
+					lmt = integer * hal_spec->txgi_pdbm + ((u16)fraction * (u16)hal_spec->txgi_pdbm) / 100;
+					if (negative)
+						lmt = -lmt;
+					sprintf(powerLimit, "%d", lmt);
+
+				} else {
+					RTW_ERR("Wrong limit expression \"%c%c\"(%d, %d)\n"
+						, szLine[i], szLine[i + 1], szLine[i], szLine[i + 1]);
+					goto exit;
+				}
+
+				/* store the power limit value */
+				phy_set_tx_power_limit(pDM_Odm, (u8 *)regulation[forCnt], (u8 *)band,
+					(u8 *)bandwidth, (u8 *)rateSection, (u8 *)ntx, (u8 *)channel, (u8 *)powerLimit);
+
+			}
+		}
+	}
+
+	rtStatus = _SUCCESS;
+
+exit:
+	if (regulation) {
+		for (forCnt = 0; forCnt < colNum; ++forCnt) {
+			if (regulation[forCnt]) {
+				rtw_mfree(regulation[forCnt], strlen(regulation[forCnt]) + 1);
+				regulation[forCnt] = NULL;
+			}
+		}
+		rtw_mfree((u8 *)regulation, sizeof(char *) * colNum);
+		regulation = NULL;
+	}
+
+	RTW_INFO("%s return %d\n", __func__, rtStatus);
+	return rtStatus;
+}
+
+int
+PHY_ConfigRFWithPowerLimitTableParaFile(
+	IN	PADAPTER	Adapter,
+	IN	const char	*pFileName
+)
+{
+	HAL_DATA_TYPE		*pHalData = GET_HAL_DATA(Adapter);
+	int	rlen = 0, rtStatus = _FAIL;
+
+	if (!(Adapter->registrypriv.load_phy_file & LOAD_RF_TXPWR_LMT_PARA_FILE))
+		return rtStatus;
+
+	_rtw_memset(pHalData->para_file_buf, 0, MAX_PARA_FILE_BUF_LEN);
+
+	if (pHalData->rf_tx_pwr_lmt == NULL) {
+		rtw_get_phy_file_path(Adapter, pFileName);
+		if (rtw_is_file_readable(rtw_phy_para_file_path) == _TRUE) {
+			rlen = rtw_retrieve_from_file(rtw_phy_para_file_path, pHalData->para_file_buf, MAX_PARA_FILE_BUF_LEN);
+			if (rlen > 0) {
+				rtStatus = _SUCCESS;
+				pHalData->rf_tx_pwr_lmt = rtw_zvmalloc(rlen);
+				if (pHalData->rf_tx_pwr_lmt) {
+					_rtw_memcpy(pHalData->rf_tx_pwr_lmt, pHalData->para_file_buf, rlen);
+					pHalData->rf_tx_pwr_lmt_len = rlen;
+				} else
+					RTW_INFO("%s rf_tx_pwr_lmt alloc fail !\n", __FUNCTION__);
+			}
+		}
+	} else {
+		if ((pHalData->rf_tx_pwr_lmt_len != 0) && (pHalData->rf_tx_pwr_lmt != NULL)) {
+			_rtw_memcpy(pHalData->para_file_buf, pHalData->rf_tx_pwr_lmt, pHalData->rf_tx_pwr_lmt_len);
+			rtStatus = _SUCCESS;
+		} else
+			RTW_INFO("%s(): Critical Error !!!\n", __FUNCTION__);
+	}
+
+	if (rtStatus == _SUCCESS) {
+		/* RTW_INFO("%s(): read %s ok\n", __FUNCTION__, pFileName); */
+		rtStatus = phy_ParsePowerLimitTableFile(Adapter, pHalData->para_file_buf);
+	} else
+		RTW_INFO("%s(): No File %s, Load from HWImg Array!\n", __FUNCTION__, pFileName);
+
+	return rtStatus;
+}
+#endif /* CONFIG_TXPWR_LIMIT */
+
+void phy_free_filebuf_mask(_adapter *padapter, u8 mask)
+{
+	HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
+
+	if (pHalData->mac_reg && (mask & LOAD_MAC_PARA_FILE)) {
+		rtw_vmfree(pHalData->mac_reg, pHalData->mac_reg_len);
+		pHalData->mac_reg = NULL;
+	}
+	if (mask & LOAD_BB_PARA_FILE) {
+		if (pHalData->bb_phy_reg) {
+			rtw_vmfree(pHalData->bb_phy_reg, pHalData->bb_phy_reg_len);
+			pHalData->bb_phy_reg = NULL;
+		}
+		if (pHalData->bb_agc_tab) {
+			rtw_vmfree(pHalData->bb_agc_tab, pHalData->bb_agc_tab_len);
+			pHalData->bb_agc_tab = NULL;
+		}
+	}
+	if (pHalData->bb_phy_reg_pg && (mask & LOAD_BB_PG_PARA_FILE)) {
+		rtw_vmfree(pHalData->bb_phy_reg_pg, pHalData->bb_phy_reg_pg_len);
+		pHalData->bb_phy_reg_pg = NULL;
+	}
+	if (pHalData->bb_phy_reg_mp && (mask & LOAD_BB_MP_PARA_FILE)) {
+		rtw_vmfree(pHalData->bb_phy_reg_mp, pHalData->bb_phy_reg_mp_len);
+		pHalData->bb_phy_reg_mp = NULL;
+	}
+	if (mask & LOAD_RF_PARA_FILE) {
+		if (pHalData->rf_radio_a) {
+			rtw_vmfree(pHalData->rf_radio_a, pHalData->rf_radio_a_len);
+			pHalData->rf_radio_a = NULL;
+		}
+		if (pHalData->rf_radio_b) {
+			rtw_vmfree(pHalData->rf_radio_b, pHalData->rf_radio_b_len);
+			pHalData->rf_radio_b = NULL;
+		}
+	}
+	if (pHalData->rf_tx_pwr_track && (mask & LOAD_RF_TXPWR_TRACK_PARA_FILE)) {
+		rtw_vmfree(pHalData->rf_tx_pwr_track, pHalData->rf_tx_pwr_track_len);
+		pHalData->rf_tx_pwr_track = NULL;
+	}
+	if (pHalData->rf_tx_pwr_lmt && (mask & LOAD_RF_TXPWR_LMT_PARA_FILE)) {
+		rtw_vmfree(pHalData->rf_tx_pwr_lmt, pHalData->rf_tx_pwr_lmt_len);
+		pHalData->rf_tx_pwr_lmt = NULL;
+	}
+}
+
+inline void phy_free_filebuf(_adapter *padapter)
+{
+	phy_free_filebuf_mask(padapter, 0xFF);
+}
+
+#endif
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/hal_dm_acs.c linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/hal_dm_acs.c
--- linux-5.6.3/3rdparty/rtl8821ce/hal/hal_dm_acs.c	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/hal_dm_acs.c	2020-04-10 16:35:06.789658807 +0300
@@ -0,0 +1,554 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2014 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#include <drv_types.h>
+#include <hal_data.h>
+
+
+#if defined(CONFIG_RTW_ACS) || defined(CONFIG_BACKGROUND_NOISE_MONITOR)
+static void _rtw_bss_nums_count(_adapter *adapter, u8 *pbss_nums)
+{
+	struct mlme_priv	*pmlmepriv = &(adapter->mlmepriv);
+	_queue *queue = &(pmlmepriv->scanned_queue);
+	struct wlan_network *pnetwork = NULL;
+	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
+
+	_list	*plist, *phead;
+	_irqL irqL;
+	int chan_idx = -1;
+
+	if (pbss_nums == NULL) {
+		RTW_ERR("%s pbss_nums is null pointer\n", __func__);
+		return;
+	}
+	_rtw_memset(pbss_nums, 0, MAX_CHANNEL_NUM);
+
+	_enter_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);
+	phead = get_list_head(queue);
+	plist = get_next(phead);
+	while (1) {
+		if (rtw_end_of_queue_search(phead, plist) == _TRUE)
+			break;
+
+		pnetwork = LIST_CONTAINOR(plist, struct wlan_network, list);
+		if (!pnetwork)
+			break;
+		chan_idx = rtw_chset_search_ch(adapter_to_chset(adapter), pnetwork->network.Configuration.DSConfig);
+		if ((chan_idx == -1) || (chan_idx >= MAX_CHANNEL_NUM)) {
+			RTW_ERR("%s can't get chan_idx(CH:%d)\n",
+				__func__, pnetwork->network.Configuration.DSConfig);
+			chan_idx = 0;
+		}
+		/*if (pnetwork->network.Reserved[0] != BSS_TYPE_PROB_REQ)*/
+
+		pbss_nums[chan_idx]++;
+
+		plist = get_next(plist);
+	}
+	_exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);
+}
+
+u8 rtw_get_ch_num_by_idx(_adapter *adapter, u8 idx)
+{
+	struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter);
+	RT_CHANNEL_INFO *pch_set = rfctl->channel_set;
+	u8 max_chan_nums = rfctl->max_chan_nums;
+
+	if (idx >= max_chan_nums)
+		return 0;
+	return pch_set[idx].ChannelNum;
+}
+#endif /*defined(CONFIG_RTW_ACS) || defined(CONFIG_BACKGROUND_NOISE_MONITOR)*/
+
+
+#ifdef CONFIG_RTW_ACS
+void rtw_acs_version_dump(void *sel, _adapter *adapter)
+{
+	_RTW_PRINT_SEL(sel, "RTK_ACS VER_%d\n", RTK_ACS_VERSION);
+}
+u8 rtw_phydm_clm_ratio(_adapter *adapter)
+{
+	struct dm_struct *phydm = adapter_to_phydm(adapter);
+
+	return phydm_cmn_info_query(phydm, (enum phydm_info_query) PHYDM_INFO_CLM_RATIO);
+}
+u8 rtw_phydm_nhm_ratio(_adapter *adapter)
+{
+	struct dm_struct *phydm = adapter_to_phydm(adapter);
+
+	return phydm_cmn_info_query(phydm, (enum phydm_info_query) PHYDM_INFO_NHM_RATIO);
+}
+void rtw_acs_reset(_adapter *adapter)
+{
+	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
+	struct auto_chan_sel *pacs = &hal_data->acs;
+
+	_rtw_memset(pacs, 0, sizeof(struct auto_chan_sel));
+	#ifdef CONFIG_RTW_ACS_DBG
+	rtw_acs_adv_reset(adapter);
+	#endif /*CONFIG_RTW_ACS_DBG*/
+}
+
+#ifdef CONFIG_RTW_ACS_DBG
+u8 rtw_is_acs_igi_valid(_adapter *adapter)
+{
+	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
+	struct auto_chan_sel *pacs = &hal_data->acs;
+
+	if ((pacs->igi) && ((pacs->igi >= 0x1E) || (pacs->igi < 0x60)))
+		return _TRUE;
+
+	return _FALSE;
+}
+void rtw_acs_adv_setting(_adapter *adapter, RT_SCAN_TYPE scan_type, u16 scan_time, u8 igi, u8 bw)
+{
+	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
+	struct auto_chan_sel *pacs = &hal_data->acs;
+	struct mlme_ext_priv *pmlmeext = &adapter->mlmeextpriv;
+	struct mlme_ext_info *pmlmeinfo = &pmlmeext->mlmext_info;
+
+	pacs->scan_type = scan_type;
+	pacs->scan_time = scan_time;
+	pacs->igi = igi;
+	pacs->bw = bw;
+	RTW_INFO("[ACS] ADV setting - scan_type:%c, ch_ms:%d(ms), igi:0x%02x, bw:%d\n",
+		pacs->scan_type ? 'A' : 'P', pacs->scan_time, pacs->igi, pacs->bw);
+}
+void rtw_acs_adv_reset(_adapter *adapter)
+{
+	rtw_acs_adv_setting(adapter, SCAN_ACTIVE, 0, 0, 0);
+}
+#endif /*CONFIG_RTW_ACS_DBG*/
+
+void rtw_acs_trigger(_adapter *adapter, u16 scan_time_ms, u8 scan_chan, enum NHM_PID pid)
+{
+	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
+	struct dm_struct *phydm = adapter_to_phydm(adapter);
+#if (RTK_ACS_VERSION == 3)
+	struct clm_para_info clm_para;
+	struct nhm_para_info nhm_para;
+	struct env_trig_rpt trig_rpt;
+
+	scan_time_ms -= 10;
+
+	init_acs_clm(clm_para, scan_time_ms);
+
+	if (pid == NHM_PID_IEEE_11K_HIGH)
+		init_11K_high_nhm(nhm_para, scan_time_ms);
+	else if (pid == NHM_PID_IEEE_11K_LOW)
+		init_11K_low_nhm(nhm_para, scan_time_ms);
+	else
+		init_acs_nhm(nhm_para, scan_time_ms);
+
+	hal_data->acs.trig_rst = phydm_env_mntr_trigger(phydm, &nhm_para, &clm_para, &trig_rpt);
+	if (hal_data->acs.trig_rst == (NHM_SUCCESS | CLM_SUCCESS)) {
+		hal_data->acs.trig_rpt.clm_rpt_stamp = trig_rpt.clm_rpt_stamp;
+		hal_data->acs.trig_rpt.nhm_rpt_stamp = trig_rpt.nhm_rpt_stamp;
+		/*RTW_INFO("[ACS] trigger success (rst = 0x%02x, clm_stamp:%d, nhm_stamp:%d)\n",
+			hal_data->acs.trig_rst, hal_data->acs.trig_rpt.clm_rpt_stamp, hal_data->acs.trig_rpt.nhm_rpt_stamp);*/
+	} else
+		RTW_ERR("[ACS] trigger failed (rst = 0x%02x)\n", hal_data->acs.trig_rst);
+#else
+	phydm_ccx_monitor_trigger(phydm, scan_time_ms);
+#endif
+
+	hal_data->acs.trigger_ch = scan_chan;
+	hal_data->acs.triggered = _TRUE;
+
+	#ifdef CONFIG_RTW_ACS_DBG
+	RTW_INFO("[ACS] Trigger CH:%d, Times:%d\n", hal_data->acs.trigger_ch, scan_time_ms);
+	#endif
+}
+void rtw_acs_get_rst(_adapter *adapter)
+{
+	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
+	struct dm_struct *phydm = adapter_to_phydm(adapter);
+	int chan_idx = -1;
+	u8 cur_chan = hal_data->acs.trigger_ch;
+
+	if (cur_chan == 0)
+		return;
+
+	if (!hal_data->acs.triggered)
+		return;
+
+	chan_idx = rtw_chset_search_ch(adapter_to_chset(adapter), cur_chan);
+	if ((chan_idx == -1) || (chan_idx >= MAX_CHANNEL_NUM)) {
+		RTW_ERR("[ACS] %s can't get chan_idx(CH:%d)\n", __func__, cur_chan);
+		return;
+	}
+#if (RTK_ACS_VERSION == 3)
+	if (!(hal_data->acs.trig_rst == (NHM_SUCCESS | CLM_SUCCESS))) {
+		RTW_ERR("[ACS] get_rst return, due to acs trigger failed\n");
+		return;
+	}
+
+	{
+		struct env_mntr_rpt rpt = {0};
+		u8 rst;
+
+		rst = phydm_env_mntr_result(phydm, &rpt);
+		if ((rst == (NHM_SUCCESS | CLM_SUCCESS)) &&
+			(rpt.clm_rpt_stamp == hal_data->acs.trig_rpt.clm_rpt_stamp) &&
+			(rpt.nhm_rpt_stamp == hal_data->acs.trig_rpt.nhm_rpt_stamp)){
+			hal_data->acs.clm_ratio[chan_idx] = rpt.clm_ratio;
+			hal_data->acs.nhm_ratio[chan_idx] = rpt.nhm_ratio;
+			_rtw_memcpy(&hal_data->acs.nhm[chan_idx][0], rpt.nhm_result, NHM_RPT_NUM);
+
+			/*RTW_INFO("[ACS] get_rst success (rst = 0x%02x, clm_stamp:%d:%d, nhm_stamp:%d:%d)\n",
+			rst,
+			hal_data->acs.trig_rpt.clm_rpt_stamp, rpt.clm_rpt_stamp,
+			hal_data->acs.trig_rpt.nhm_rpt_stamp, rpt.nhm_rpt_stamp);*/
+		} else {
+			RTW_ERR("[ACS] get_rst failed (rst = 0x%02x, clm_stamp:%d:%d, nhm_stamp:%d:%d)\n",
+			rst,
+			hal_data->acs.trig_rpt.clm_rpt_stamp, rpt.clm_rpt_stamp,
+			hal_data->acs.trig_rpt.nhm_rpt_stamp, rpt.nhm_rpt_stamp);
+		}
+	}
+
+#else
+	phydm_ccx_monitor_result(phydm);
+
+	hal_data->acs.clm_ratio[chan_idx] = rtw_phydm_clm_ratio(adapter);
+	hal_data->acs.nhm_ratio[chan_idx] = rtw_phydm_nhm_ratio(adapter);
+#endif
+	hal_data->acs.triggered = _FALSE;
+	#ifdef CONFIG_RTW_ACS_DBG
+	RTW_INFO("[ACS] Result CH:%d, CLM:%d NHM:%d\n",
+		cur_chan, hal_data->acs.clm_ratio[chan_idx], hal_data->acs.nhm_ratio[chan_idx]);
+	#endif
+}
+
+void _rtw_phydm_acs_select_best_chan(_adapter *adapter)
+{
+	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
+	struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter);
+	u8 ch_idx;
+	u8 ch_idx_24g = 0xFF, ch_idx_5g = 0xFF;
+	u8 min_itf_24g = 0xFF,  min_itf_5g = 0xFF;
+	u8 *pbss_nums = hal_data->acs.bss_nums;
+	u8 *pclm_ratio = hal_data->acs.clm_ratio;
+	u8 *pnhm_ratio = hal_data->acs.nhm_ratio;
+	u8 *pinterference_time = hal_data->acs.interference_time;
+	u8 max_chan_nums = rfctl->max_chan_nums;
+
+	for (ch_idx = 0; ch_idx < max_chan_nums; ch_idx++) {
+		if (pbss_nums[ch_idx])
+			pinterference_time[ch_idx] = (pclm_ratio[ch_idx] / 2) + pnhm_ratio[ch_idx];
+		else
+			pinterference_time[ch_idx] = pclm_ratio[ch_idx] + pnhm_ratio[ch_idx];
+
+		if (rtw_get_ch_num_by_idx(adapter, ch_idx) < 14) {
+			if (pinterference_time[ch_idx] < min_itf_24g) {
+				min_itf_24g = pinterference_time[ch_idx];
+				ch_idx_24g = ch_idx;
+			}
+		} else {
+			if (pinterference_time[ch_idx] < min_itf_5g) {
+				min_itf_5g = pinterference_time[ch_idx];
+				ch_idx_5g = ch_idx;
+			}
+		}
+	}
+	if (ch_idx_24g != 0xFF)
+		hal_data->acs.best_chan_24g = rtw_get_ch_num_by_idx(adapter, ch_idx_24g);
+
+	if (ch_idx_5g != 0xFF)
+		hal_data->acs.best_chan_5g = rtw_get_ch_num_by_idx(adapter, ch_idx_5g);
+
+	hal_data->acs.trigger_ch = 0;
+}
+
+void rtw_acs_info_dump(void *sel, _adapter *adapter)
+{
+	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
+	struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter);
+	u8 max_chan_nums = rfctl->max_chan_nums;
+	u8 ch_idx, ch_num;
+
+	_RTW_PRINT_SEL(sel, "========== ACS (VER-%d) ==========\n", RTK_ACS_VERSION);
+	_RTW_PRINT_SEL(sel, "Best 24G Channel:%d\n", hal_data->acs.best_chan_24g);
+	_RTW_PRINT_SEL(sel, "Best 5G Channel:%d\n\n", hal_data->acs.best_chan_5g);
+
+	#ifdef CONFIG_RTW_ACS_DBG
+	_RTW_PRINT_SEL(sel, "Advanced setting - scan_type:%c, ch_ms:%d(ms), igi:0x%02x, bw:%d\n",
+		hal_data->acs.scan_type ? 'A' : 'P', hal_data->acs.scan_time, hal_data->acs.igi, hal_data->acs.bw);
+
+	_RTW_PRINT_SEL(sel, "BW  20MHz\n");
+	_RTW_PRINT_SEL(sel, "%5s  %3s  %3s  %3s(%%)  %3s(%%)  %3s\n",
+						"Index", "CH", "BSS", "CLM", "NHM", "ITF");
+
+	for (ch_idx = 0; ch_idx < max_chan_nums; ch_idx++) {
+		ch_num = rtw_get_ch_num_by_idx(adapter, ch_idx);
+		_RTW_PRINT_SEL(sel, "%5d  %3d  %3d  %6d  %6d  %3d\n",
+						ch_idx, ch_num, hal_data->acs.bss_nums[ch_idx],
+						hal_data->acs.clm_ratio[ch_idx],
+						hal_data->acs.nhm_ratio[ch_idx],
+						hal_data->acs.interference_time[ch_idx]);
+	}
+	#endif
+}
+void rtw_acs_select_best_chan(_adapter *adapter)
+{
+	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
+
+	_rtw_bss_nums_count(adapter, hal_data->acs.bss_nums);
+	_rtw_phydm_acs_select_best_chan(adapter);
+	rtw_acs_info_dump(RTW_DBGDUMP, adapter);
+}
+
+void rtw_acs_start(_adapter *adapter)
+{
+	rtw_acs_reset(adapter);
+	if (GET_ACS_STATE(adapter) != ACS_ENABLE)
+		SET_ACS_STATE(adapter, ACS_ENABLE);
+}
+void rtw_acs_stop(_adapter *adapter)
+{
+	SET_ACS_STATE(adapter, ACS_DISABLE);
+}
+
+
+u8 rtw_acs_get_clm_ratio_by_ch_num(_adapter *adapter, u8 chan)
+{
+	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
+	int chan_idx = -1;
+
+	chan_idx = rtw_chset_search_ch(adapter_to_chset(adapter), chan);
+	if ((chan_idx == -1) || (chan_idx >= MAX_CHANNEL_NUM)) {
+		RTW_ERR("[ACS] Get CLM fail, can't get chan_idx(CH:%d)\n", chan);
+		return 0;
+	}
+
+	return hal_data->acs.clm_ratio[chan_idx];
+}
+u8 rtw_acs_get_clm_ratio_by_ch_idx(_adapter *adapter, u8 ch_idx)
+{
+	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
+
+	if (ch_idx >= MAX_CHANNEL_NUM) {
+		RTW_ERR("%s [ACS] ch_idx(%d) is invalid\n", __func__, ch_idx);
+		return 0;
+	}
+
+	return hal_data->acs.clm_ratio[ch_idx];
+}
+u8 rtw_acs_get_nhm_ratio_by_ch_num(_adapter *adapter, u8 chan)
+{
+	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
+	int chan_idx = -1;
+
+	chan_idx = rtw_chset_search_ch(adapter_to_chset(adapter), chan);
+	if ((chan_idx == -1) || (chan_idx >= MAX_CHANNEL_NUM)) {
+		RTW_ERR("[ACS] Get NHM fail, can't get chan_idx(CH:%d)\n", chan);
+		return 0;
+	}
+
+	return hal_data->acs.nhm_ratio[chan_idx];
+}
+u8 rtw_acs_get_num_ratio_by_ch_idx(_adapter *adapter, u8 ch_idx)
+{
+	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
+
+	if (ch_idx >= MAX_CHANNEL_NUM) {
+		RTW_ERR("%s [ACS] ch_idx(%d) is invalid\n", __func__, ch_idx);
+		return 0;
+	}
+
+	return hal_data->acs.nhm_ratio[ch_idx];
+}
+void rtw_acs_chan_info_dump(void *sel, _adapter *adapter)
+{
+	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
+	struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter);
+	u8 max_chan_nums = rfctl->max_chan_nums;
+	u8 ch_idx, ch_num;
+	u8 utilization;
+
+	_RTW_PRINT_SEL(sel, "BW  20MHz\n");
+	_RTW_PRINT_SEL(sel, "%5s  %3s  %7s(%%)  %12s(%%)  %11s(%%)  %9s(%%)  %8s(%%)\n",
+						"Index", "CH", "Quality", "Availability", "Utilization",
+						"WIFI Util", "Interference Util");
+
+	for (ch_idx = 0; ch_idx < max_chan_nums; ch_idx++) {
+		ch_num = rtw_get_ch_num_by_idx(adapter, ch_idx);
+		utilization = hal_data->acs.clm_ratio[ch_idx] + hal_data->acs.nhm_ratio[ch_idx];
+		_RTW_PRINT_SEL(sel, "%5d  %3d  %7d   %12d   %12d   %12d   %12d\n",
+						ch_idx, ch_num,
+						(100-hal_data->acs.interference_time[ch_idx]),
+						(100-utilization),
+						utilization,
+						hal_data->acs.clm_ratio[ch_idx],
+						hal_data->acs.nhm_ratio[ch_idx]);
+	}
+}
+void rtw_acs_current_info_dump(void *sel, _adapter *adapter)
+{
+	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
+	u8 ch, cen_ch, bw, offset;
+
+	_RTW_PRINT_SEL(sel, "========== ACS (VER-%d) ==========\n", RTK_ACS_VERSION);
+
+	ch = rtw_get_oper_ch(adapter);
+	bw = rtw_get_oper_bw(adapter);
+	offset = rtw_get_oper_choffset(adapter);
+
+	_RTW_PRINT_SEL(sel, "Current Channel:%d\n", ch);
+	if ((bw == CHANNEL_WIDTH_80) ||(bw == CHANNEL_WIDTH_40)) {
+		cen_ch = rtw_get_center_ch(ch, bw, offset);
+		_RTW_PRINT_SEL(sel, "Center Channel:%d\n", cen_ch);
+	}
+
+	_RTW_PRINT_SEL(sel, "Current BW %s\n", ch_width_str(bw));
+	if (0)
+		_RTW_PRINT_SEL(sel, "Current IGI 0x%02x\n", rtw_phydm_get_cur_igi(adapter));
+	_RTW_PRINT_SEL(sel, "CLM:%d, NHM:%d\n\n",
+		hal_data->acs.cur_ch_clm_ratio, hal_data->acs.cur_ch_nhm_ratio);
+}
+
+void rtw_acs_update_current_info(_adapter *adapter)
+{
+	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
+
+	hal_data->acs.cur_ch_clm_ratio = rtw_phydm_clm_ratio(adapter);
+	hal_data->acs.cur_ch_nhm_ratio = rtw_phydm_nhm_ratio(adapter);
+
+	#ifdef CONFIG_RTW_ACS_DBG
+	rtw_acs_current_info_dump(RTW_DBGDUMP, adapter);
+	#endif
+}
+#endif /*CONFIG_RTW_ACS*/
+
+#ifdef CONFIG_BACKGROUND_NOISE_MONITOR
+void rtw_noise_monitor_version_dump(void *sel, _adapter *adapter)
+{
+	_RTW_PRINT_SEL(sel, "RTK_NOISE_MONITOR VER_%d\n", RTK_NOISE_MONITOR_VERSION);
+}
+void rtw_nm_enable(_adapter *adapter)
+{
+	SET_NM_STATE(adapter, NM_ENABLE);
+}
+void rtw_nm_disable(_adapter *adapter)
+{
+	SET_NM_STATE(adapter, NM_DISABLE);
+}
+void rtw_noise_info_dump(void *sel, _adapter *adapter)
+{
+	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
+	struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter);
+	u8 max_chan_nums = rfctl->max_chan_nums;
+	u8 ch_idx, ch_num;
+
+	_RTW_PRINT_SEL(sel, "========== NM (VER-%d) ==========\n", RTK_NOISE_MONITOR_VERSION);
+
+	_RTW_PRINT_SEL(sel, "%5s  %3s  %3s  %10s", "Index", "CH", "BSS", "Noise(dBm)\n");
+
+	_rtw_bss_nums_count(adapter, hal_data->nm.bss_nums);
+
+	for (ch_idx = 0; ch_idx < max_chan_nums; ch_idx++) {
+		ch_num = rtw_get_ch_num_by_idx(adapter, ch_idx);
+		_RTW_PRINT_SEL(sel, "%5d  %3d  %3d  %10d\n",
+						ch_idx, ch_num, hal_data->nm.bss_nums[ch_idx],
+						hal_data->nm.noise[ch_idx]);
+	}
+}
+
+void rtw_noise_measure(_adapter *adapter, u8 chan, u8 is_pause_dig, u8 igi_value, u32 max_time)
+{
+	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
+	struct dm_struct *phydm = &hal_data->odmpriv;
+	int chan_idx = -1;
+	s16 noise = 0;
+
+	#ifdef DBG_NOISE_MONITOR
+	RTW_INFO("[NM] chan(%d)-PauseDIG:%s,  IGIValue:0x%02x, max_time:%d (ms)\n",
+		chan, (is_pause_dig) ? "Y" : "N", igi_value, max_time);
+	#endif
+
+	chan_idx = rtw_chset_search_ch(adapter_to_chset(adapter), chan);
+	if ((chan_idx == -1) || (chan_idx >= MAX_CHANNEL_NUM)) {
+		RTW_ERR("[NM] Get noise fail, can't get chan_idx(CH:%d)\n", chan);
+		return;
+	}
+	noise = odm_inband_noise_monitor(phydm, is_pause_dig, igi_value, max_time); /*dBm*/
+
+	hal_data->nm.noise[chan_idx] = noise;
+
+	#ifdef DBG_NOISE_MONITOR
+	RTW_INFO("[NM] %s chan_%d, noise = %d (dBm)\n", __func__, chan, hal_data->nm.noise[chan_idx]);
+
+	RTW_INFO("[NM] noise_a = %d, noise_b = %d  noise_all:%d\n",
+			 phydm->noise_level.noise[RF_PATH_A],
+			 phydm->noise_level.noise[RF_PATH_B],
+			 phydm->noise_level.noise_all);
+	#endif /*DBG_NOISE_MONITOR*/
+}
+
+s16 rtw_noise_query_by_chan_num(_adapter *adapter, u8 chan)
+{
+	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
+	s16 noise = 0;
+	int chan_idx = -1;
+
+	chan_idx = rtw_chset_search_ch(adapter_to_chset(adapter), chan);
+	if ((chan_idx == -1) || (chan_idx >= MAX_CHANNEL_NUM)) {
+		RTW_ERR("[NM] Get noise fail, can't get chan_idx(CH:%d)\n", chan);
+		return noise;
+	}
+	noise = hal_data->nm.noise[chan_idx];
+
+	#ifdef DBG_NOISE_MONITOR
+	RTW_INFO("[NM] %s chan_%d, noise = %d (dBm)\n", __func__, chan, noise);
+	#endif/*DBG_NOISE_MONITOR*/
+	return noise;
+}
+s16 rtw_noise_query_by_chan_idx(_adapter *adapter, u8 ch_idx)
+{
+	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
+	s16 noise = 0;
+
+	if (ch_idx >= MAX_CHANNEL_NUM) {
+		RTW_ERR("[NM] %s ch_idx(%d) is invalid\n", __func__, ch_idx);
+		return noise;
+	}
+	noise = hal_data->nm.noise[ch_idx];
+
+	#ifdef DBG_NOISE_MONITOR
+	RTW_INFO("[NM] %s ch_idx %d, noise = %d (dBm)\n", __func__, ch_idx, noise);
+	#endif/*DBG_NOISE_MONITOR*/
+	return noise;
+}
+
+s16 rtw_noise_measure_curchan(_adapter *padapter)
+{
+	s16 noise = 0;
+	u8 igi_value = 0x1E;
+	u32 max_time = 100;/* ms */
+	u8 is_pause_dig = _TRUE;
+	u8 cur_chan = rtw_get_oper_ch(padapter);
+
+	if (rtw_linked_check(padapter) == _FALSE)
+		return noise;
+
+	rtw_ps_deny(padapter, PS_DENY_IOCTL);
+	LeaveAllPowerSaveModeDirect(padapter);
+	rtw_noise_measure(padapter, cur_chan, is_pause_dig, igi_value, max_time);
+	noise = rtw_noise_query_by_chan_num(padapter, cur_chan);
+	rtw_ps_deny_cancel(padapter, PS_DENY_IOCTL);
+
+	return noise;
+}
+#endif /*CONFIG_BACKGROUND_NOISE_MONITOR*/
+
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/hal_dm_acs.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/hal_dm_acs.h
--- linux-5.6.3/3rdparty/rtl8821ce/hal/hal_dm_acs.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/hal_dm_acs.h	2020-04-10 16:35:06.789658807 +0300
@@ -0,0 +1,167 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#ifndef __HAL_DM_ACS_H__
+#define __HAL_DM_ACS_H__
+#ifdef CONFIG_RTW_ACS
+#define RTK_ACS_VERSION	3
+
+#if (RTK_ACS_VERSION == 3)
+enum NHM_PID {
+	NHM_PID_ACS,
+	NHM_PID_IEEE_11K_HIGH,
+	NHM_PID_IEEE_11K_LOW,
+};
+
+#define init_clm_param(clm, app, lv, time) \
+	do {\
+		clm.clm_app = app;\
+		clm.clm_lv = lv;\
+		clm.mntr_time = time;\
+	} while (0)
+
+#define init_nhm_param(nhm, txon, cca, cnt_opt, app, lv, time) \
+	do {\
+		nhm.incld_txon = txon;\
+		nhm.incld_cca = cca;\
+		nhm.div_opt = cnt_opt;\
+		nhm.nhm_app = app;\
+		nhm.nhm_lv = lv;\
+		nhm.mntr_time = time;\
+	} while (0)
+
+	
+#define init_acs_clm(clm, time) \
+	init_clm_param(clm, CLM_ACS, CLM_LV_2, time)
+
+#define init_acs_nhm(nhm, time) \
+	init_nhm_param(nhm, NHM_EXCLUDE_TXON, NHM_EXCLUDE_CCA, NHM_CNT_ALL, NHM_ACS, NHM_LV_2, time)
+
+#define init_11K_high_nhm(nhm, time) \
+	init_nhm_param(nhm, NHM_EXCLUDE_TXON, NHM_EXCLUDE_CCA, NHM_CNT_ALL, IEEE_11K_HIGH, NHM_LV_2, time)
+	
+#define init_11K_low_nhm(nhm, time) \
+		init_nhm_param(nhm, NHM_EXCLUDE_TXON, NHM_EXCLUDE_CCA, NHM_CNT_ALL, IEEE_11K_LOW, NHM_LV_2, time)
+
+
+#endif /*(RTK_ACS_VERSION == 3)*/
+void rtw_acs_version_dump(void *sel, _adapter *adapter);
+extern void phydm_ccx_monitor_trigger(void *p_dm_void, u16 monitor_time);
+extern void phydm_ccx_monitor_result(void *p_dm_void);
+
+#define GET_ACS_STATE(padapter)					(ATOMIC_READ(&GET_HAL_DATA(padapter)->acs.state))
+#define SET_ACS_STATE(padapter, set_state)			(ATOMIC_SET(&GET_HAL_DATA(padapter)->acs.state, set_state))
+#define IS_ACS_ENABLE(padapter)					((GET_ACS_STATE(padapter) == ACS_ENABLE) ? _TRUE : _FALSE)
+
+enum ACS_STATE {
+	ACS_DISABLE,
+	ACS_ENABLE,
+};
+
+#define ACS_BW_20M	BIT(0)
+#define ACS_BW_40M	BIT(1)
+#define ACS_BW_80M	BIT(2)
+#define ACS_BW_160M	BIT(3)
+
+struct auto_chan_sel {
+	ATOMIC_T state;
+	u8 trigger_ch;
+	bool triggered;
+	u8 clm_ratio[MAX_CHANNEL_NUM];
+	u8 nhm_ratio[MAX_CHANNEL_NUM];
+	#if (RTK_ACS_VERSION == 3)
+	u8 nhm[MAX_CHANNEL_NUM][NHM_RPT_NUM];
+	#endif
+	u8 bss_nums[MAX_CHANNEL_NUM];
+	u8 interference_time[MAX_CHANNEL_NUM];
+	u8 cur_ch_clm_ratio;
+	u8 cur_ch_nhm_ratio;
+	u8 best_chan_5g;
+	u8 best_chan_24g;
+
+	#if (RTK_ACS_VERSION == 3)
+	u8 trig_rst;
+	struct env_trig_rpt	trig_rpt;
+	#endif
+
+	#ifdef CONFIG_RTW_ACS_DBG
+	RT_SCAN_TYPE scan_type;
+	u16 scan_time;
+	u8 igi;
+	u8 bw;
+	#endif
+};
+
+#define rtw_acs_get_best_chan_24g(adapter)		(GET_HAL_DATA(adapter)->acs.best_chan_24g)
+#define rtw_acs_get_best_chan_5g(adapter)		(GET_HAL_DATA(adapter)->acs.best_chan_5g)
+
+#ifdef CONFIG_RTW_ACS_DBG
+#define rtw_is_acs_passiv_scan(adapter)	(((GET_HAL_DATA(adapter)->acs.scan_type) == SCAN_PASSIVE) ? _TRUE : _FALSE)
+
+#define rtw_acs_get_adv_st(adapter)	(GET_HAL_DATA(adapter)->acs.scan_time)
+#define rtw_is_acs_st_valid(adapter)	((GET_HAL_DATA(adapter)->acs.scan_time) ? _TRUE : _FALSE)
+
+#define rtw_acs_get_adv_igi(adapter)	(GET_HAL_DATA(adapter)->acs.igi)
+u8 rtw_is_acs_igi_valid(_adapter *adapter);
+
+#define rtw_acs_get_adv_bw(adapter)	(GET_HAL_DATA(adapter)->acs.bw)
+
+void rtw_acs_adv_setting(_adapter *adapter, RT_SCAN_TYPE scan_type, u16 scan_time, u8 igi, u8 bw);
+void rtw_acs_adv_reset(_adapter *adapter);
+#endif
+
+u8 rtw_acs_get_clm_ratio_by_ch_num(_adapter *adapter, u8 chan);
+u8 rtw_acs_get_clm_ratio_by_ch_idx(_adapter *adapter, u8 ch_idx);
+u8 rtw_acs_get_nhm_ratio_by_ch_num(_adapter *adapter, u8 chan);
+u8 rtw_acs_get_num_ratio_by_ch_idx(_adapter *adapter, u8 ch_idx);
+
+void rtw_acs_reset(_adapter *adapter);
+void rtw_acs_trigger(_adapter *adapter, u16 scan_time_ms, u8 scan_chan, enum NHM_PID pid);
+void rtw_acs_get_rst(_adapter *adapter);
+void rtw_acs_select_best_chan(_adapter *adapter);
+void rtw_acs_info_dump(void *sel, _adapter *adapter);
+void rtw_acs_update_current_info(_adapter *adapter);
+void rtw_acs_chan_info_dump(void *sel, _adapter *adapter);
+void rtw_acs_current_info_dump(void *sel, _adapter *adapter);
+
+void rtw_acs_start(_adapter *adapter);
+void rtw_acs_stop(_adapter *adapter);
+
+#endif /*CONFIG_RTW_ACS*/
+
+#ifdef CONFIG_BACKGROUND_NOISE_MONITOR
+#define RTK_NOISE_MONITOR_VERSION	3
+#define GET_NM_STATE(padapter)					(ATOMIC_READ(&GET_HAL_DATA(padapter)->nm.state))
+#define SET_NM_STATE(padapter, set_state)			(ATOMIC_SET(&GET_HAL_DATA(padapter)->nm.state, set_state))
+#define IS_NM_ENABLE(padapter)					((GET_NM_STATE(padapter) == NM_ENABLE) ? _TRUE : _FALSE)
+
+enum NM_STATE {
+	NM_DISABLE,
+	NM_ENABLE,
+};
+
+struct noise_monitor {
+	ATOMIC_T state;
+	s16 noise[MAX_CHANNEL_NUM];
+	u8 bss_nums[MAX_CHANNEL_NUM];
+};
+void rtw_nm_enable(_adapter *adapter);
+void rtw_nm_disable(_adapter *adapter);
+void rtw_noise_measure(_adapter *adapter, u8 chan, u8 is_pause_dig, u8 igi_value, u32 max_time);
+s16 rtw_noise_query_by_chan_num(_adapter *adapter, u8 chan);
+s16 rtw_noise_query_by_chan_idx(_adapter *adapter, u8 ch_idx);
+s16 rtw_noise_measure_curchan(_adapter *padapter);
+void rtw_noise_info_dump(void *sel, _adapter *adapter);
+#endif
+#endif /* __HAL_DM_ACS_H__ */
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/hal_dm.c linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/hal_dm.c
--- linux-5.6.3/3rdparty/rtl8821ce/hal/hal_dm.c	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/hal_dm.c	2020-04-10 16:35:06.789658807 +0300
@@ -0,0 +1,1470 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2014 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+
+#include <drv_types.h>
+#include <hal_data.h>
+
+/* A mapping from HalData to ODM. */
+enum odm_board_type boardType(u8 InterfaceSel)
+{
+	enum odm_board_type        board	= ODM_BOARD_DEFAULT;
+
+#ifdef CONFIG_PCI_HCI
+	INTERFACE_SELECT_PCIE   pcie	= (INTERFACE_SELECT_PCIE)InterfaceSel;
+	switch (pcie) {
+	case INTF_SEL0_SOLO_MINICARD:
+		board |= ODM_BOARD_MINICARD;
+		break;
+	case INTF_SEL1_BT_COMBO_MINICARD:
+		board |= ODM_BOARD_BT;
+		board |= ODM_BOARD_MINICARD;
+		break;
+	default:
+		board = ODM_BOARD_DEFAULT;
+		break;
+	}
+
+#elif defined(CONFIG_USB_HCI)
+	INTERFACE_SELECT_USB    usb	= (INTERFACE_SELECT_USB)InterfaceSel;
+	switch (usb) {
+	case INTF_SEL1_USB_High_Power:
+		board |= ODM_BOARD_EXT_LNA;
+		board |= ODM_BOARD_EXT_PA;
+		break;
+	case INTF_SEL2_MINICARD:
+		board |= ODM_BOARD_MINICARD;
+		break;
+	case INTF_SEL4_USB_Combo:
+		board |= ODM_BOARD_BT;
+		break;
+	case INTF_SEL5_USB_Combo_MF:
+		board |= ODM_BOARD_BT;
+		break;
+	case INTF_SEL0_USB:
+	case INTF_SEL3_USB_Solo:
+	default:
+		board = ODM_BOARD_DEFAULT;
+		break;
+	}
+
+#endif
+	/* RTW_INFO("===> boardType(): (pHalData->InterfaceSel, pDM_Odm->BoardType) = (%d, %d)\n", InterfaceSel, board); */
+
+	return board;
+}
+
+void rtw_hal_update_iqk_fw_offload_cap(_adapter *adapter)
+{
+	PHAL_DATA_TYPE hal = GET_HAL_DATA(adapter);
+	struct dm_struct *p_dm_odm = adapter_to_phydm(adapter);
+
+	if (hal->RegIQKFWOffload) {
+		rtw_sctx_init(&hal->iqk_sctx, 0);
+		phydm_fwoffload_ability_init(p_dm_odm, PHYDM_RF_IQK_OFFLOAD);
+	} else
+		phydm_fwoffload_ability_clear(p_dm_odm, PHYDM_RF_IQK_OFFLOAD);
+
+	RTW_INFO("IQK FW offload:%s\n", hal->RegIQKFWOffload ? "enable" : "disable");
+}
+
+#if ((RTL8822B_SUPPORT == 1) || (RTL8821C_SUPPORT == 1) || (RTL8814B_SUPPORT == 1))
+void rtw_phydm_iqk_trigger(_adapter *adapter)
+{
+	struct dm_struct *p_dm_odm = adapter_to_phydm(adapter);
+	u8 clear = _TRUE;
+	u8 segment = _FALSE;
+	u8 rfk_forbidden = _FALSE;
+
+	/*segment = _rtw_phydm_iqk_segment_chk(adapter);*/
+	halrf_cmn_info_set(p_dm_odm, HALRF_CMNINFO_RFK_FORBIDDEN, rfk_forbidden);
+	halrf_cmn_info_set(p_dm_odm, HALRF_CMNINFO_IQK_SEGMENT, segment);
+	halrf_segment_iqk_trigger(p_dm_odm, clear, segment);
+}
+#endif
+
+void rtw_phydm_iqk_trigger_dbg(_adapter *adapter, bool recovery, bool clear, bool segment)
+{
+	struct dm_struct *p_dm_odm = adapter_to_phydm(adapter);
+
+#if ((RTL8822B_SUPPORT == 1) || (RTL8821C_SUPPORT == 1) || (RTL8814B_SUPPORT == 1))
+		halrf_segment_iqk_trigger(p_dm_odm, clear, segment);
+#else
+		halrf_iqk_trigger(p_dm_odm, recovery);
+#endif
+}
+void rtw_phydm_lck_trigger(_adapter *adapter)
+{
+	struct dm_struct *p_dm_odm = adapter_to_phydm(adapter);
+
+	halrf_lck_trigger(p_dm_odm);
+}
+#ifdef CONFIG_DBG_RF_CAL
+void rtw_hal_iqk_test(_adapter *adapter, bool recovery, bool clear, bool segment)
+{
+	struct dm_struct *p_dm_odm = adapter_to_phydm(adapter);
+
+	rtw_ps_deny(adapter, PS_DENY_IOCTL);
+	LeaveAllPowerSaveModeDirect(adapter);
+
+	rtw_phydm_ability_backup(adapter);
+	rtw_phydm_func_disable_all(adapter);
+
+	halrf_cmn_info_set(p_dm_odm, HALRF_CMNINFO_ABILITY, HAL_RF_IQK);
+
+	rtw_phydm_iqk_trigger_dbg(adapter, recovery, clear, segment);
+	rtw_phydm_ability_restore(adapter);
+
+	rtw_ps_deny_cancel(adapter, PS_DENY_IOCTL);
+}
+
+void rtw_hal_lck_test(_adapter *adapter)
+{
+	struct dm_struct *p_dm_odm = adapter_to_phydm(adapter);
+
+	rtw_ps_deny(adapter, PS_DENY_IOCTL);
+	LeaveAllPowerSaveModeDirect(adapter);
+
+	rtw_phydm_ability_backup(adapter);
+	rtw_phydm_func_disable_all(adapter);
+
+	halrf_cmn_info_set(p_dm_odm, HALRF_CMNINFO_ABILITY, HAL_RF_LCK);
+
+	rtw_phydm_lck_trigger(adapter);
+
+	rtw_phydm_ability_restore(adapter);
+	rtw_ps_deny_cancel(adapter, PS_DENY_IOCTL);
+}
+#endif
+
+#ifdef CONFIG_FW_OFFLOAD_PARAM_INIT
+void rtw_hal_update_param_init_fw_offload_cap(_adapter *adapter)
+{
+	struct dm_struct *p_dm_odm = adapter_to_phydm(adapter);
+
+	if (adapter->registrypriv.fw_param_init)
+		phydm_fwoffload_ability_init(p_dm_odm, PHYDM_PHY_PARAM_OFFLOAD);
+	else
+		phydm_fwoffload_ability_clear(p_dm_odm, PHYDM_PHY_PARAM_OFFLOAD);
+
+	RTW_INFO("Init-Parameter FW offload:%s\n", adapter->registrypriv.fw_param_init ? "enable" : "disable");
+}
+#endif
+
+void record_ra_info(void *p_dm_void, u8 macid, struct cmn_sta_info *p_sta, u64 ra_mask)
+{
+	struct dm_struct *p_dm = (struct dm_struct *)p_dm_void;
+	_adapter *adapter = p_dm->adapter;
+	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
+	struct macid_ctl_t *macid_ctl = dvobj_to_macidctl(dvobj);
+
+	if (p_sta) {
+		rtw_macid_ctl_set_bw(macid_ctl, macid, p_sta->ra_info.ra_bw_mode);
+		rtw_macid_ctl_set_vht_en(macid_ctl, macid, p_sta->ra_info.is_vht_enable);
+		rtw_macid_ctl_set_rate_bmp0(macid_ctl, macid, ra_mask);
+		rtw_macid_ctl_set_rate_bmp1(macid_ctl, macid, ra_mask >> 32);
+
+		rtw_update_tx_rate_bmp(adapter_to_dvobj(adapter));
+	}
+}
+
+#ifdef CONFIG_SUPPORT_DYNAMIC_TXPWR
+void rtw_phydm_fill_desc_dpt(void *dm, u8 *desc, u8 dpt_lv)
+{
+	struct dm_struct *p_dm = (struct dm_struct *)dm;
+	_adapter *adapter = p_dm->adapter;
+
+	switch (rtw_get_chip_type(adapter)) {
+/*
+	#ifdef CONFIG_RTL8188F
+	case RTL8188F:
+		break;
+	#endif
+
+	#ifdef CONFIG_RTL8723B
+	case RTL8723B :
+		break;
+	#endif
+
+	#ifdef CONFIG_RTL8703B
+	case RTL8703B :
+		break;
+	#endif
+
+	#ifdef CONFIG_RTL8812A
+	case RTL8812 :
+		break;
+	#endif
+
+	#ifdef CONFIG_RTL8821A
+	case RTL8821:
+		break;
+	#endif
+
+	#ifdef CONFIG_RTL8814A
+	case RTL8814A :
+		break;
+	#endif
+
+	#ifdef CONFIG_RTL8192F
+	case RTL8192F :
+		break;
+	#endif
+*/
+/*
+	#ifdef CONFIG_RTL8192E
+	case RTL8192E :
+		SET_TX_DESC_TX_POWER_0_PSET_92E(desc, dpt_lv);
+		break;
+	#endif
+*/
+
+	#ifdef CONFIG_RTL8821C
+	case RTL8821C :
+		SET_TX_DESC_TXPWR_OFSET_8821C(desc, dpt_lv);
+	break;
+	#endif
+
+	default :
+		RTW_ERR("%s IC not support dynamic tx power\n", __func__);
+		break;
+	}
+}
+void rtw_phydm_set_dyntxpwr(_adapter *adapter, u8 *desc, u8 mac_id)
+{
+	struct dm_struct *dm = adapter_to_phydm(adapter);
+
+	odm_set_dyntxpwr(dm, desc, mac_id);
+}
+#endif
+
+#ifdef CONFIG_RTW_TX_2PATH_EN
+void rtw_phydm_tx_2path_en(_adapter *adapter)
+{
+	struct dm_struct *dm = adapter_to_phydm(adapter);
+
+	phydm_tx_2path(dm);
+}
+#endif
+
+void rtw_phydm_ops_func_init(struct dm_struct *p_phydm)
+{
+	struct ra_table *p_ra_t = &p_phydm->dm_ra_table;
+
+	p_ra_t->record_ra_info = record_ra_info;
+	#ifdef CONFIG_SUPPORT_DYNAMIC_TXPWR
+	p_phydm->fill_desc_dyntxpwr = rtw_phydm_fill_desc_dpt;
+	#endif
+}
+void rtw_phydm_priv_init(_adapter *adapter)
+{
+	PHAL_DATA_TYPE hal = GET_HAL_DATA(adapter);
+	struct dm_struct *phydm = &(hal->odmpriv);
+
+	phydm->adapter = adapter;
+	odm_cmn_info_init(phydm, ODM_CMNINFO_PLATFORM, ODM_CE);
+}
+
+void Init_ODM_ComInfo(_adapter *adapter)
+{
+	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
+	PHAL_DATA_TYPE	pHalData = GET_HAL_DATA(adapter);
+	struct dm_struct	*pDM_Odm = &(pHalData->odmpriv);
+	struct pwrctrl_priv *pwrctl = adapter_to_pwrctl(adapter);
+	int i;
+
+	/*phydm_op_mode could be change for different scenarios: ex: SoftAP - PHYDM_BALANCE_MODE*/
+	pHalData->phydm_op_mode = PHYDM_PERFORMANCE_MODE;/*Service one device*/
+	rtw_odm_init_ic_type(adapter);
+
+	if (rtw_get_intf_type(adapter) == RTW_GSPI)
+		odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_INTERFACE, ODM_ITRF_SDIO);
+	else
+		odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_INTERFACE, rtw_get_intf_type(adapter));
+
+	odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_MP_TEST_CHIP, IS_NORMAL_CHIP(pHalData->version_id));
+
+	odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_PATCH_ID, pHalData->CustomerID);
+
+	odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_BWIFI_TEST, adapter->registrypriv.wifi_spec);
+
+#ifdef CONFIG_ADVANCE_OTA
+	odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_ADVANCE_OTA, adapter->registrypriv.adv_ota);
+#endif
+	odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_RF_TYPE, pHalData->rf_type);
+
+	{
+		/* 1 ======= BoardType: ODM_CMNINFO_BOARD_TYPE ======= */
+		u8 odm_board_type = ODM_BOARD_DEFAULT;
+
+		if (pHalData->ExternalLNA_2G != 0) {
+			odm_board_type |= ODM_BOARD_EXT_LNA;
+			odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_EXT_LNA, 1);
+		}
+		if (pHalData->external_lna_5g != 0) {
+			odm_board_type |= ODM_BOARD_EXT_LNA_5G;
+			odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_5G_EXT_LNA, 1);
+		}
+		if (pHalData->ExternalPA_2G != 0) {
+			odm_board_type |= ODM_BOARD_EXT_PA;
+			odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_EXT_PA, 1);
+		}
+		if (pHalData->external_pa_5g != 0) {
+			odm_board_type |= ODM_BOARD_EXT_PA_5G;
+			odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_5G_EXT_PA, 1);
+		}
+		if (pHalData->EEPROMBluetoothCoexist)
+			odm_board_type |= ODM_BOARD_BT;
+
+		odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_BOARD_TYPE, odm_board_type);
+		/* 1 ============== End of BoardType ============== */
+	}
+
+	rtw_hal_set_odm_var(adapter, HAL_ODM_REGULATION, NULL, _TRUE);
+
+#ifdef CONFIG_DFS_MASTER
+	odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_DFS_REGION_DOMAIN, adapter->registrypriv.dfs_region_domain);
+	odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_DFS_MASTER_ENABLE, &(adapter_to_rfctl(adapter)->radar_detect_enabled));
+#endif
+
+	odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_GPA, pHalData->TypeGPA);
+	odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_APA, pHalData->TypeAPA);
+	odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_GLNA, pHalData->TypeGLNA);
+	odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_ALNA, pHalData->TypeALNA);
+
+	odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_RFE_TYPE, pHalData->rfe_type);
+	odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_X_CAP_SETTING, pHalData->crystal_cap);
+
+	odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_EXT_TRSW, 0);
+
+	/*Add by YuChen for kfree init*/
+	odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_REGRFKFREEENABLE, adapter->registrypriv.RegPwrTrimEnable);
+	odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_RFKFREEENABLE, pHalData->RfKFreeEnable);
+
+	odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_RF_ANTENNA_TYPE, pHalData->TRxAntDivType);
+	odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_BE_FIX_TX_ANT, pHalData->b_fix_tx_ant);
+	odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_WITH_EXT_ANTENNA_SWITCH, pHalData->with_extenal_ant_switch);
+
+	/* (8822B) efuse 0x3D7 & 0x3D8 for TX PA bias */
+	odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_EFUSE0X3D7, pHalData->efuse0x3d7);
+	odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_EFUSE0X3D8, pHalData->efuse0x3d8);
+
+	/*Add by YuChen for adaptivity init*/
+	odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_ADAPTIVITY, &(adapter->registrypriv.adaptivity_en));
+	phydm_adaptivity_info_init(pDM_Odm, PHYDM_ADAPINFO_CARRIER_SENSE_ENABLE, (adapter->registrypriv.adaptivity_mode != 0) ? TRUE : FALSE);
+	phydm_adaptivity_info_init(pDM_Odm, PHYDM_ADAPINFO_TH_L2H_INI, adapter->registrypriv.adaptivity_th_l2h_ini);
+	phydm_adaptivity_info_init(pDM_Odm, PHYDM_ADAPINFO_TH_EDCCA_HL_DIFF, adapter->registrypriv.adaptivity_th_edcca_hl_diff);
+
+	/*halrf info init*/
+	halrf_cmn_info_init(pDM_Odm, HALRF_CMNINFO_EEPROM_THERMAL_VALUE, pHalData->eeprom_thermal_meter);
+	halrf_cmn_info_init(pDM_Odm, HALRF_CMNINFO_PWT_TYPE, 0);
+
+	if (rtw_odm_adaptivity_needed(adapter) == _TRUE)
+		rtw_odm_adaptivity_config_msg(RTW_DBGDUMP, adapter);
+
+#ifdef CONFIG_IQK_PA_OFF
+	odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_IQKPAOFF, 1);
+#endif
+	rtw_hal_update_iqk_fw_offload_cap(adapter);
+	#ifdef CONFIG_FW_OFFLOAD_PARAM_INIT
+	rtw_hal_update_param_init_fw_offload_cap(adapter);
+	#endif
+
+	/* Pointer reference */
+	/*Antenna diversity relative parameters*/
+	odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_ANT_DIV, &(pHalData->AntDivCfg));
+	odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_MP_MODE, &(adapter->registrypriv.mp_mode));
+
+	odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_BB_OPERATION_MODE, &(pHalData->phydm_op_mode));
+	odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_TX_UNI, &(dvobj->traffic_stat.tx_bytes));
+	odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_RX_UNI, &(dvobj->traffic_stat.rx_bytes));
+
+	odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_BAND, &(pHalData->current_band_type));
+	odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_FORCED_RATE, &(pHalData->ForcedDataRate));
+
+	odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_SEC_CHNL_OFFSET, &(pHalData->nCur40MhzPrimeSC));
+	odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_SEC_MODE, &(adapter->securitypriv.dot11PrivacyAlgrthm));
+	odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_BW, &(pHalData->current_channel_bw));
+	odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_CHNL, &(pHalData->current_channel));
+	odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_NET_CLOSED, &(adapter->net_closed));
+
+	odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_SCAN, &(pHalData->bScanInProcess));
+	odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_POWER_SAVING, &(pwrctl->bpower_saving));
+	/*Add by Yuchen for phydm beamforming*/
+	odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_TX_TP, &(dvobj->traffic_stat.cur_tx_tp));
+	odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_RX_TP, &(dvobj->traffic_stat.cur_rx_tp));
+	odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_ANT_TEST, &(pHalData->antenna_test));
+#ifdef CONFIG_RTL8723B
+	odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_IS1ANTENNA, &pHalData->EEPROMBluetoothAntNum);
+	odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_RFDEFAULTPATH, &pHalData->ant_path);
+#endif /*CONFIG_RTL8723B*/
+#ifdef CONFIG_USB_HCI
+	odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_HUBUSBMODE, &(dvobj->usb_speed));
+#endif
+
+#ifdef CONFIG_DYNAMIC_SOML
+	odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_ADAPTIVE_SOML, &(adapter->registrypriv.dyn_soml_en));
+#endif
+
+	/*halrf info hook*/
+#ifdef CONFIG_MP_INCLUDED
+	halrf_cmn_info_hook(pDM_Odm, HALRF_CMNINFO_CON_TX, &(adapter->mppriv.mpt_ctx.is_start_cont_tx));
+	halrf_cmn_info_hook(pDM_Odm, HALRF_CMNINFO_SINGLE_TONE, &(adapter->mppriv.mpt_ctx.is_single_tone));
+	halrf_cmn_info_hook(pDM_Odm, HALRF_CMNINFO_CARRIER_SUPPRESSION, &(adapter->mppriv.mpt_ctx.is_carrier_suppression));
+	halrf_cmn_info_hook(pDM_Odm, HALRF_CMNINFO_MP_RATE_INDEX, &(adapter->mppriv.mpt_ctx.mpt_rate_index));
+#endif/*CONFIG_MP_INCLUDED*/
+	for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++)
+		odm_cmn_info_ptr_array_hook(pDM_Odm, ODM_CMNINFO_STA_STATUS, i, NULL);
+
+	phydm_init_debug_setting(pDM_Odm);
+	rtw_phydm_ops_func_init(pDM_Odm);
+	/* TODO */
+	/* odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_BT_OPERATION, _FALSE); */
+	/* odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_BT_DISABLE_EDCA, _FALSE); */
+}
+
+
+static u32 edca_setting_UL[HT_IOT_PEER_MAX] =
+/*UNKNOWN, REALTEK_90, REALTEK_92SE, BROADCOM,*/
+/*RALINK, ATHEROS, CISCO, MERU, MARVELL, 92U_AP, SELF_AP(DownLink/Tx) */
+{ 0x5e4322, 0xa44f, 0x5e4322, 0x5ea32b, 0x5ea422, 0x5ea322, 0x3ea430, 0x5ea42b, 0x5ea44f, 0x5e4322, 0x5e4322};
+
+static u32 edca_setting_DL[HT_IOT_PEER_MAX] =
+/*UNKNOWN, REALTEK_90, REALTEK_92SE, BROADCOM,*/
+/*RALINK, ATHEROS, CISCO, MERU, MARVELL, 92U_AP, SELF_AP(UpLink/Rx)*/
+{ 0xa44f, 0x5ea44f,	 0x5e4322, 0x5ea42b, 0xa44f, 0xa630, 0x5ea630, 0x5ea42b, 0xa44f, 0xa42b, 0xa42b};
+
+static u32 edca_setting_dl_g_mode[HT_IOT_PEER_MAX] =
+/*UNKNOWN, REALTEK_90, REALTEK_92SE, BROADCOM,*/
+/*RALINK, ATHEROS, CISCO, MERU, MARVELL, 92U_AP, SELF_AP */
+{ 0x4322, 0xa44f, 0x5e4322, 0xa42b, 0x5e4322, 0x4322,	 0xa42b, 0x5ea42b, 0xa44f, 0x5e4322, 0x5ea42b};
+
+void rtw_hal_turbo_edca(_adapter *adapter)
+{
+	HAL_DATA_TYPE		*hal_data = GET_HAL_DATA(adapter);
+	struct dvobj_priv		*dvobj = adapter_to_dvobj(adapter);
+	struct recv_priv		*precvpriv = &(adapter->recvpriv);
+	struct registry_priv		*pregpriv = &adapter->registrypriv;
+	struct mlme_ext_priv	*pmlmeext = &(adapter->mlmeextpriv);
+	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
+
+	/* Parameter suggested by Scott  */
+#if 0
+	u32	EDCA_BE_UL = edca_setting_UL[p_mgnt_info->iot_peer];
+	u32	EDCA_BE_DL = edca_setting_DL[p_mgnt_info->iot_peer];
+#endif
+	u32	EDCA_BE_UL = 0x5ea42b;
+	u32	EDCA_BE_DL = 0x00a42b;
+	u8	ic_type = rtw_get_chip_type(adapter);
+
+	u8	iot_peer = 0;
+	u8	wireless_mode = 0xFF;                 /* invalid value */
+	u8	traffic_index;
+	u32	edca_param;
+	u64	cur_tx_bytes = 0;
+	u64	cur_rx_bytes = 0;
+	u8	bbtchange = _TRUE;
+	u8	is_bias_on_rx = _FALSE;
+	u8	is_linked = _FALSE;
+	u8	interface_type;
+
+	if (hal_data->dis_turboedca)
+		return;
+
+	if (rtw_mi_check_status(adapter, MI_ASSOC))
+		is_linked = _TRUE;
+
+	if (is_linked != _TRUE) {
+		precvpriv->is_any_non_be_pkts = _FALSE;
+		return;
+	}
+
+	if ((pregpriv->wifi_spec == 1)) { /* || (pmlmeinfo->HT_enable == 0)) */
+		precvpriv->is_any_non_be_pkts = _FALSE;
+		return;
+	}
+
+	interface_type = rtw_get_intf_type(adapter);
+	wireless_mode = pmlmeext->cur_wireless_mode;
+
+	iot_peer = pmlmeinfo->assoc_AP_vendor;
+
+	if (iot_peer >=  HT_IOT_PEER_MAX) {
+		precvpriv->is_any_non_be_pkts = _FALSE;
+		return;
+	}
+
+	if (ic_type == RTL8188E) {
+		if ((iot_peer == HT_IOT_PEER_RALINK) || (iot_peer == HT_IOT_PEER_ATHEROS))
+			is_bias_on_rx = _TRUE;
+	}
+
+	/* Check if the status needs to be changed. */
+	if ((bbtchange) || (!precvpriv->is_any_non_be_pkts)) {
+		cur_tx_bytes = dvobj->traffic_stat.cur_tx_bytes;
+		cur_rx_bytes = dvobj->traffic_stat.cur_rx_bytes;
+
+		/* traffic, TX or RX */
+		if (is_bias_on_rx) {
+			if (cur_tx_bytes > (cur_rx_bytes << 2)) {
+				/* Uplink TP is present. */
+				traffic_index = UP_LINK;
+			} else {
+				/* Balance TP is present. */
+				traffic_index = DOWN_LINK;
+			}
+		} else {
+			if (cur_rx_bytes > (cur_tx_bytes << 2)) {
+				/* Downlink TP is present. */
+				traffic_index = DOWN_LINK;
+			} else {
+				/* Balance TP is present. */
+				traffic_index = UP_LINK;
+			}
+		}
+#if 0
+		if ((p_dm_odm->dm_edca_table.prv_traffic_idx != traffic_index)
+			|| (!p_dm_odm->dm_edca_table.is_current_turbo_edca))
+#endif
+		{
+			if (interface_type == RTW_PCIE) {
+				EDCA_BE_UL = 0x6ea42b;
+				EDCA_BE_DL = 0x6ea42b;
+			}
+
+			/* 92D txop can't be set to 0x3e for cisco1250 */
+			if ((iot_peer == HT_IOT_PEER_CISCO) && (wireless_mode == ODM_WM_N24G)) {
+				EDCA_BE_DL = edca_setting_DL[iot_peer];
+				EDCA_BE_UL = edca_setting_UL[iot_peer];
+			}
+			/* merge from 92s_92c_merge temp*/
+			else if ((iot_peer == HT_IOT_PEER_CISCO) && ((wireless_mode == ODM_WM_G) || (wireless_mode == (ODM_WM_B | ODM_WM_G)) || (wireless_mode == ODM_WM_A) || (wireless_mode == ODM_WM_B)))
+				EDCA_BE_DL = edca_setting_dl_g_mode[iot_peer];
+			else if ((iot_peer == HT_IOT_PEER_AIRGO) && ((wireless_mode == ODM_WM_G) || (wireless_mode == ODM_WM_A)))
+				EDCA_BE_DL = 0xa630;
+			else if (iot_peer == HT_IOT_PEER_MARVELL) {
+				EDCA_BE_DL = edca_setting_DL[iot_peer];
+				EDCA_BE_UL = edca_setting_UL[iot_peer];
+			} else if (iot_peer == HT_IOT_PEER_ATHEROS) {
+				/* Set DL EDCA for Atheros peer to 0x3ea42b.*/
+				/* Suggested by SD3 Wilson for ASUS TP issue.*/
+				EDCA_BE_DL = edca_setting_DL[iot_peer];
+			}
+
+			if ((ic_type == RTL8812) || (ic_type == RTL8821) || (ic_type == RTL8192E) || (ic_type == RTL8192F)) { /* add 8812AU/8812AE */
+				EDCA_BE_UL = 0x5ea42b;
+				EDCA_BE_DL = 0x5ea42b;
+
+				RTW_DBG("8812A: EDCA_BE_UL=0x%x EDCA_BE_DL =0x%x\n", EDCA_BE_UL, EDCA_BE_DL);
+			}
+
+			if (interface_type == RTW_PCIE &&
+				((ic_type == RTL8822B)
+				|| (ic_type == RTL8814A))) {
+				EDCA_BE_UL = 0x6ea42b;
+				EDCA_BE_DL = 0x6ea42b;
+			}
+
+			if (traffic_index == DOWN_LINK)
+				edca_param = EDCA_BE_DL;
+			else
+				edca_param = EDCA_BE_UL;
+
+#ifdef CONFIG_EXTEND_LOWRATE_TXOP
+#define TXOP_CCK1M			0x01A6
+#define TXOP_CCK2M			0x00E6
+#define TXOP_CCK5M			0x006B
+#define TXOP_OFD6M			0x0066
+#define TXOP_MCS6M			0x0061
+{
+			struct sta_info *psta;
+			struct macid_ctl_t *macid_ctl = dvobj_to_macidctl(dvobj);
+			u8 mac_id, role, current_rate_id;
+			
+			/*	search all used & connect2AP macid	*/
+			for (mac_id = 0; mac_id < macid_ctl->num; mac_id++) {
+				if (rtw_macid_is_used(macid_ctl, mac_id))  {
+					role = GET_H2CCMD_MSRRPT_PARM_ROLE(&(macid_ctl->h2c_msr[mac_id]));
+					if (role != H2C_MSR_ROLE_AP)
+						continue;
+
+					psta = macid_ctl->sta[mac_id];
+					current_rate_id = rtw_get_current_tx_rate(adapter, psta);
+					/*  Check init tx_rate==1M and set 0x508[31:16]==0x019B(unit 32us) if it is 	*/
+					switch (current_rate_id) {
+						case DESC_RATE1M:
+							edca_param &= 0x0000FFFF;
+							edca_param |= (TXOP_CCK1M<<16);
+							break;
+						case DESC_RATE2M:
+							edca_param &= 0x0000FFFF;
+							edca_param |= (TXOP_CCK2M<<16);
+							break;
+						case DESC_RATE5_5M:
+							edca_param &= 0x0000FFFF;
+							edca_param |= (TXOP_CCK5M<<16);
+							break;
+						case DESC_RATE6M:
+							edca_param &= 0x0000FFFF;
+							edca_param |= (TXOP_OFD6M<<16);
+							break;
+						case DESC_RATEMCS0:
+							edca_param &= 0x0000FFFF;
+							edca_param |= (TXOP_MCS6M<<16);
+							break;
+						default:
+							break;
+					}
+				}
+			}
+}
+#endif
+
+#ifdef 	CONFIG_RTW_CUSTOMIZE_BEEDCA
+			edca_param = CONFIG_RTW_CUSTOMIZE_BEEDCA;
+#endif
+			rtw_hal_set_hwreg(adapter, HW_VAR_AC_PARAM_BE, (u8 *)(&edca_param));
+
+			RTW_DBG("Turbo EDCA =0x%x\n", edca_param);
+
+			hal_data->prv_traffic_idx = traffic_index;
+		}
+
+		hal_data->is_turbo_edca = _TRUE;
+	} else {
+		/*  */
+		/* Turn Off EDCA turbo here. */
+		/* Restore original EDCA according to the declaration of AP. */
+		/*  */
+		if (hal_data->is_turbo_edca) {
+			edca_param = hal_data->ac_param_be;
+			rtw_hal_set_hwreg(adapter, HW_VAR_AC_PARAM_BE, (u8 *)(&edca_param));
+			hal_data->is_turbo_edca = _FALSE;
+		}
+	}
+
+}
+
+s8 rtw_phydm_get_min_rssi(_adapter *adapter)
+{
+	struct dm_struct *phydm = adapter_to_phydm(adapter);
+	s8 rssi_min = 0;
+
+	rssi_min = phydm_cmn_info_query(phydm, (enum phydm_info_query) PHYDM_INFO_RSSI_MIN);
+	return rssi_min;
+}
+
+u8 rtw_phydm_get_cur_igi(_adapter *adapter)
+{
+	struct dm_struct *phydm = adapter_to_phydm(adapter);
+	u8 cur_igi = 0;
+
+	cur_igi = phydm_cmn_info_query(phydm, (enum phydm_info_query) PHYDM_INFO_CURR_IGI);
+	return cur_igi;
+}
+
+u32 rtw_phydm_get_phy_cnt(_adapter *adapter, enum phy_cnt cnt)
+{
+	struct dm_struct *phydm = adapter_to_phydm(adapter);
+
+	if (cnt == FA_OFDM)
+		return  phydm_cmn_info_query(phydm, (enum phydm_info_query) PHYDM_INFO_FA_OFDM);
+	else if (cnt == FA_CCK)
+		return  phydm_cmn_info_query(phydm, (enum phydm_info_query) PHYDM_INFO_FA_CCK);
+	else if (cnt == FA_TOTAL)
+		return  phydm_cmn_info_query(phydm, (enum phydm_info_query) PHYDM_INFO_FA_TOTAL);
+	else if (cnt == CCA_OFDM)
+		return	phydm_cmn_info_query(phydm, (enum phydm_info_query) PHYDM_INFO_CCA_OFDM);
+	else if (cnt == CCA_CCK)
+		return	phydm_cmn_info_query(phydm, (enum phydm_info_query) PHYDM_INFO_CCA_CCK);
+	else if (cnt == CCA_ALL)
+		return	phydm_cmn_info_query(phydm, (enum phydm_info_query) PHYDM_INFO_CCA_ALL);
+	else if (cnt == CRC32_OK_VHT)
+		return	phydm_cmn_info_query(phydm, (enum phydm_info_query) PHYDM_INFO_CRC32_OK_VHT);
+	else if (cnt == CRC32_OK_HT)
+		return	phydm_cmn_info_query(phydm, (enum phydm_info_query) PHYDM_INFO_CRC32_OK_HT);
+	else if (cnt == CRC32_OK_LEGACY)
+		return	phydm_cmn_info_query(phydm, (enum phydm_info_query) PHYDM_INFO_CRC32_OK_LEGACY);
+	else if (cnt == CRC32_OK_CCK)
+		return	phydm_cmn_info_query(phydm, (enum phydm_info_query) PHYDM_INFO_CRC32_OK_CCK);
+	else if (cnt == CRC32_ERROR_VHT)
+		return	phydm_cmn_info_query(phydm, (enum phydm_info_query) PHYDM_INFO_CRC32_ERROR_VHT);
+	else if (cnt == CRC32_ERROR_HT)
+		return	phydm_cmn_info_query(phydm, (enum phydm_info_query) PHYDM_INFO_CRC32_ERROR_HT);
+	else if (cnt == CRC32_ERROR_LEGACY)
+		return	phydm_cmn_info_query(phydm, (enum phydm_info_query) PHYDM_INFO_CRC32_ERROR_LEGACY);
+	else if (cnt == CRC32_ERROR_CCK)
+		return	phydm_cmn_info_query(phydm, (enum phydm_info_query) PHYDM_INFO_CRC32_ERROR_CCK);
+	else
+		return 0;
+}
+
+u8 rtw_phydm_is_iqk_in_progress(_adapter *adapter)
+{
+	u8 rts = _FALSE;
+	struct dm_struct *podmpriv = adapter_to_phydm(adapter);
+
+	odm_acquire_spin_lock(podmpriv, RT_IQK_SPINLOCK);
+	if (podmpriv->rf_calibrate_info.is_iqk_in_progress == _TRUE) {
+		RTW_ERR("IQK InProgress\n");
+		rts = _TRUE;
+	}
+	odm_release_spin_lock(podmpriv, RT_IQK_SPINLOCK);
+
+	return rts;
+}
+
+void SetHalODMVar(
+	PADAPTER				Adapter,
+	HAL_ODM_VARIABLE		eVariable,
+	PVOID					pValue1,
+	BOOLEAN					bSet)
+{
+	struct dm_struct *podmpriv = adapter_to_phydm(Adapter);
+	/* _irqL irqL; */
+	switch (eVariable) {
+	case HAL_ODM_STA_INFO: {
+		struct sta_info *psta = (struct sta_info *)pValue1;
+
+		if (bSet) {
+			RTW_INFO("### Set STA_(%d) info ###\n", psta->cmn.mac_id);
+			odm_cmn_info_ptr_array_hook(podmpriv, ODM_CMNINFO_STA_STATUS, psta->cmn.mac_id, psta);
+			psta->cmn.dm_ctrl = STA_DM_CTRL_ACTIVE;
+			phydm_cmn_sta_info_hook(podmpriv, psta->cmn.mac_id, &(psta->cmn));
+		} else {
+			RTW_INFO("### Clean STA_(%d) info ###\n", psta->cmn.mac_id);
+			/* _enter_critical_bh(&pHalData->odm_stainfo_lock, &irqL); */
+			psta->cmn.dm_ctrl = 0;
+			odm_cmn_info_ptr_array_hook(podmpriv, ODM_CMNINFO_STA_STATUS, psta->cmn.mac_id, NULL);
+			phydm_cmn_sta_info_hook(podmpriv, psta->cmn.mac_id, NULL);
+
+			/* _exit_critical_bh(&pHalData->odm_stainfo_lock, &irqL); */
+		}
+	}
+		break;
+	case HAL_ODM_P2P_STATE:
+		odm_cmn_info_update(podmpriv, ODM_CMNINFO_WIFI_DIRECT, bSet);
+		break;
+	case HAL_ODM_WIFI_DISPLAY_STATE:
+		odm_cmn_info_update(podmpriv, ODM_CMNINFO_WIFI_DISPLAY, bSet);
+		break;
+	case HAL_ODM_REGULATION:
+		/* used to auto enable/disable adaptivity by SD7 */
+		phydm_adaptivity_info_update(podmpriv, PHYDM_ADAPINFO_DOMAIN_CODE_2G, 0);
+		phydm_adaptivity_info_update(podmpriv, PHYDM_ADAPINFO_DOMAIN_CODE_5G, 0);
+		break;
+	case HAL_ODM_INITIAL_GAIN: {
+		u8 rx_gain = *((u8 *)(pValue1));
+		/*printk("rx_gain:%x\n",rx_gain);*/
+		if (rx_gain == 0xff) {/*restore rx gain*/
+			/*odm_write_dig(podmpriv,pDigTable->backup_ig_value);*/
+			odm_pause_dig(podmpriv, PHYDM_RESUME, PHYDM_PAUSE_LEVEL_0, rx_gain);
+		} else {
+			/*pDigTable->backup_ig_value = pDigTable->cur_ig_value;*/
+			/*odm_write_dig(podmpriv,rx_gain);*/
+			odm_pause_dig(podmpriv, PHYDM_PAUSE, PHYDM_PAUSE_LEVEL_0, rx_gain);
+		}
+	}
+	break;
+	case HAL_ODM_RX_INFO_DUMP: {
+		u8 cur_igi = 0;
+		s8 rssi_min;
+		void *sel;
+
+		sel = pValue1;
+		cur_igi = rtw_phydm_get_cur_igi(Adapter);
+		rssi_min = rtw_phydm_get_min_rssi(Adapter);
+
+		_RTW_PRINT_SEL(sel, "============ Rx Info dump ===================\n");
+		_RTW_PRINT_SEL(sel, "is_linked = %d, rssi_min = %d(%%), current_igi = 0x%x\n", podmpriv->is_linked, rssi_min, cur_igi);
+		_RTW_PRINT_SEL(sel, "cnt_cck_fail = %d, cnt_ofdm_fail = %d, Total False Alarm = %d\n",
+			rtw_phydm_get_phy_cnt(Adapter, FA_CCK),
+			rtw_phydm_get_phy_cnt(Adapter, FA_OFDM),
+			rtw_phydm_get_phy_cnt(Adapter, FA_TOTAL));
+
+		if (podmpriv->is_linked) {
+			_RTW_PRINT_SEL(sel, "rx_rate = %s", HDATA_RATE(podmpriv->rx_rate));
+			if (IS_HARDWARE_TYPE_8814A(Adapter))
+				_RTW_PRINT_SEL(sel, " rssi_a = %d(%%), rssi_b = %d(%%), rssi_c = %d(%%), rssi_d = %d(%%)\n",
+					podmpriv->rssi_a, podmpriv->rssi_b, podmpriv->rssi_c, podmpriv->rssi_d);
+			else
+				_RTW_PRINT_SEL(sel, " rssi_a = %d(%%), rssi_b = %d(%%)\n", podmpriv->rssi_a, podmpriv->rssi_b);
+#ifdef DBG_RX_SIGNAL_DISPLAY_RAW_DATA
+			rtw_dump_raw_rssi_info(Adapter, sel);
+#endif
+		}
+	}
+		break;
+	case HAL_ODM_RX_Dframe_INFO: {
+		void *sel;
+
+		sel = pValue1;
+
+		/*_RTW_PRINT_SEL(sel , "HAL_ODM_RX_Dframe_INFO\n");*/
+#ifdef DBG_RX_DFRAME_RAW_DATA
+		rtw_dump_rx_dframe_info(Adapter, sel);
+#endif
+	}
+		break;
+
+#ifdef CONFIG_ANTENNA_DIVERSITY
+	case HAL_ODM_ANTDIV_SELECT: {
+		u8	antenna = (*(u8 *)pValue1);
+		HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(Adapter);
+		/*switch antenna*/
+		odm_update_rx_idle_ant(&pHalData->odmpriv, antenna);
+		/*RTW_INFO("==> HAL_ODM_ANTDIV_SELECT, Ant_(%s)\n", (antenna == MAIN_ANT) ? "MAIN_ANT" : "AUX_ANT");*/
+
+	}
+		break;
+#endif
+
+	default:
+		break;
+	}
+}
+
+void GetHalODMVar(
+	PADAPTER				Adapter,
+	HAL_ODM_VARIABLE		eVariable,
+	PVOID					pValue1,
+	PVOID					pValue2)
+{
+	struct dm_struct *podmpriv = adapter_to_phydm(Adapter);
+
+	switch (eVariable) {
+#ifdef CONFIG_ANTENNA_DIVERSITY
+	case HAL_ODM_ANTDIV_SELECT: {
+		struct phydm_fat_struct	*pDM_FatTable = &podmpriv->dm_fat_table;
+		*((u8 *)pValue1) = pDM_FatTable->rx_idle_ant;
+	}
+		break;
+#endif
+	case HAL_ODM_INITIAL_GAIN:
+		*((u8 *)pValue1) = rtw_phydm_get_cur_igi(Adapter);
+		break;
+	default:
+		break;
+	}
+}
+
+#ifdef RTW_HALMAC
+#include "../hal_halmac.h"
+#endif
+
+enum hal_status
+rtw_phydm_fw_iqk(
+	struct dm_struct	*p_dm_odm,
+	u8 clear,
+	u8 segment
+)
+{
+	#ifdef RTW_HALMAC
+	struct _ADAPTER *adapter = p_dm_odm->adapter;
+
+	if (rtw_halmac_iqk(adapter_to_dvobj(adapter), clear, segment) == 0)
+		return HAL_STATUS_SUCCESS;
+	#endif
+	return HAL_STATUS_FAILURE;
+}
+
+enum hal_status
+rtw_phydm_cfg_phy_para(
+	struct dm_struct	*p_dm_odm,
+	enum phydm_halmac_param config_type,
+	u32 offset,
+	u32 data,
+	u32 mask,
+	enum rf_path e_rf_path,
+	u32 delay_time)
+{
+	#ifdef RTW_HALMAC
+	struct _ADAPTER *adapter = p_dm_odm->adapter;
+	struct rtw_phy_parameter para;
+
+	switch (config_type) {
+	case PHYDM_HALMAC_CMD_MAC_W8:
+		para.cmd = 0; /* MAC register */
+		para.data.mac.offset = offset;
+		para.data.mac.value = data;
+		para.data.mac.msk = mask;
+		para.data.mac.msk_en = (mask) ? 1 : 0;
+		para.data.mac.size = 1;
+	break;
+	case PHYDM_HALMAC_CMD_MAC_W16:
+		para.cmd = 0; /* MAC register */
+		para.data.mac.offset = offset;
+		para.data.mac.value = data;
+		para.data.mac.msk = mask;
+		para.data.mac.msk_en = (mask) ? 1 : 0;
+		para.data.mac.size = 2;
+	break;
+	case PHYDM_HALMAC_CMD_MAC_W32:
+		para.cmd = 0; /* MAC register */
+		para.data.mac.offset = offset;
+		para.data.mac.value = data;
+		para.data.mac.msk = mask;
+		para.data.mac.msk_en = (mask) ? 1 : 0;
+		para.data.mac.size = 4;
+	break;
+	case PHYDM_HALMAC_CMD_BB_W8:
+		para.cmd = 1; /* BB register */
+		para.data.bb.offset = offset;
+		para.data.bb.value = data;
+		para.data.bb.msk = mask;
+		para.data.bb.msk_en = (mask) ? 1 : 0;
+		para.data.bb.size = 1;
+	break;
+	case PHYDM_HALMAC_CMD_BB_W16:
+		para.cmd = 1; /* BB register */
+		para.data.bb.offset = offset;
+		para.data.bb.value = data;
+		para.data.bb.msk = mask;
+		para.data.bb.msk_en = (mask) ? 1 : 0;
+		para.data.bb.size = 2;
+	break;
+	case PHYDM_HALMAC_CMD_BB_W32:
+		para.cmd = 1; /* BB register */
+		para.data.bb.offset = offset;
+		para.data.bb.value = data;
+		para.data.bb.msk = mask;
+		para.data.bb.msk_en = (mask) ? 1 : 0;
+		para.data.bb.size = 4;
+	break;
+	case PHYDM_HALMAC_CMD_RF_W:
+		para.cmd = 2; /* RF register */
+		para.data.rf.offset = offset;
+		para.data.rf.value = data;
+		para.data.rf.msk = mask;
+		para.data.rf.msk_en = (mask) ? 1 : 0;
+		if (e_rf_path == RF_PATH_A)
+			para.data.rf.path = 0;
+		else if (e_rf_path == RF_PATH_B)
+			para.data.rf.path = 1;
+		else if (e_rf_path == RF_PATH_C)
+			para.data.rf.path = 2;
+		else if (e_rf_path == RF_PATH_D)
+			para.data.rf.path = 3;
+		else
+			para.data.rf.path = 0;
+	break;
+	case PHYDM_HALMAC_CMD_DELAY_US:
+		para.cmd = 3; /* Delay */
+		para.data.delay.unit = 0; /* microsecond */
+		para.data.delay.value = delay_time;
+	break;
+	case PHYDM_HALMAC_CMD_DELAY_MS:
+		para.cmd = 3; /* Delay */
+		para.data.delay.unit = 1; /* millisecond */
+		para.data.delay.value = delay_time;
+	break;
+	case PHYDM_HALMAC_CMD_END:
+		para.cmd = 0xFF; /* End command */
+	break;
+	default:
+		return HAL_STATUS_FAILURE;
+	}
+
+	if (rtw_halmac_cfg_phy_para(adapter_to_dvobj(adapter), &para))
+		return HAL_STATUS_FAILURE;
+	#endif /*RTW_HALMAC*/
+	return HAL_STATUS_SUCCESS;
+}
+
+
+#ifdef CONFIG_LPS_LCLK_WD_TIMER
+void rtw_phydm_wd_lps_lclk_hdl(_adapter *adapter)
+{
+	struct mlme_priv *pmlmepriv = &adapter->mlmepriv;
+	PHAL_DATA_TYPE pHalData = GET_HAL_DATA(adapter);
+	struct dm_struct	*podmpriv = &(pHalData->odmpriv);
+	struct sta_priv *pstapriv = &adapter->stapriv;
+	struct sta_info *psta = NULL;
+	u8 rssi_min = 0;
+	u32	rssi_rpt = 0;
+	bool is_linked = _FALSE;
+
+	if (!rtw_is_hw_init_completed(adapter))
+		return;
+
+	if (rtw_mi_check_status(adapter, MI_ASSOC))
+		is_linked = _TRUE;
+
+	if (is_linked == _FALSE)
+		return;
+
+	psta = rtw_get_stainfo(pstapriv, get_bssid(pmlmepriv));
+	if (psta == NULL)
+		return;
+
+	odm_cmn_info_update(&pHalData->odmpriv, ODM_CMNINFO_LINK, is_linked);
+
+	phydm_watchdog_lps_32k(&pHalData->odmpriv);
+}
+
+void rtw_phydm_watchdog_in_lps_lclk(_adapter *adapter)
+{
+	struct mlme_priv	*pmlmepriv = &adapter->mlmepriv;
+	struct sta_priv *pstapriv = &adapter->stapriv;
+	struct sta_info *psta = NULL;
+	u8 cur_igi = 0;
+	s8 min_rssi = 0;
+
+	if (!rtw_is_hw_init_completed(adapter))
+		return;
+
+	psta = rtw_get_stainfo(pstapriv, get_bssid(pmlmepriv));
+	if (psta == NULL)
+		return;
+
+	cur_igi = rtw_phydm_get_cur_igi(adapter);
+	min_rssi = rtw_phydm_get_min_rssi(adapter);
+	if (min_rssi <= 0)
+		min_rssi = psta->cmn.rssi_stat.rssi;
+	/*RTW_INFO("%s "ADPT_FMT" cur_ig_value=%d, min_rssi = %d\n", __func__,  ADPT_ARG(adapter), cur_igi, min_rssi);*/
+
+	if (min_rssi <= 0)
+		return;
+
+	if ((cur_igi > min_rssi + 5) ||
+		(cur_igi < min_rssi - 5)) {
+#ifdef CONFIG_LPS
+		rtw_dm_in_lps_wk_cmd(adapter);
+#endif
+	}
+}
+#endif /*CONFIG_LPS_LCLK_WD_TIMER*/
+
+void dump_sta_traffic(void *sel, _adapter *adapter, struct sta_info *psta)
+{
+	struct ra_sta_info *ra_info;
+	u8 curr_sgi = _FALSE;
+	u32 tx_tp_mbips, rx_tp_mbips, bi_tp_mbips;
+
+	if (!psta)
+		return;
+	RTW_PRINT_SEL(sel, "\n");
+	RTW_PRINT_SEL(sel, "====== mac_id : %d [" MAC_FMT "] ======\n",
+		psta->cmn.mac_id, MAC_ARG(psta->cmn.mac_addr));
+
+	if (is_client_associated_to_ap(psta->padapter))
+		RTW_PRINT_SEL(sel, "BCN counts : %d (per-%d second), DTIM Period:%d\n",
+		rtw_get_bcn_cnt(psta->padapter) / 2, 1, adapter->mlmeextpriv.dtim);
+
+	ra_info = &psta->cmn.ra_info;
+	curr_sgi = rtw_get_current_tx_sgi(adapter, psta);
+	RTW_PRINT_SEL(sel, "tx_rate : %s(%s)  rx_rate : %s, rx_rate_bmc : %s, rssi : %d %%\n"
+		, HDATA_RATE(rtw_get_current_tx_rate(adapter, psta)), (curr_sgi) ? "S" : "L"
+		, HDATA_RATE((psta->curr_rx_rate & 0x7F)), HDATA_RATE((psta->curr_rx_rate_bmc & 0x7F)), psta->cmn.rssi_stat.rssi
+	);
+
+	if (0) {
+		RTW_PRINT_SEL(sel, "tx_bytes:%llu(%llu - %llu)\n"
+			, psta->sta_stats.tx_bytes - psta->sta_stats.last_tx_bytes
+			, psta->sta_stats.tx_bytes, psta->sta_stats.last_tx_bytes
+		);
+		RTW_PRINT_SEL(sel, "rx_uc_bytes:%llu(%llu - %llu)\n"
+			, sta_rx_uc_bytes(psta) - sta_last_rx_uc_bytes(psta)
+			, sta_rx_uc_bytes(psta), sta_last_rx_uc_bytes(psta)
+		);
+		RTW_PRINT_SEL(sel, "rx_mc_bytes:%llu(%llu - %llu)\n"
+			, psta->sta_stats.rx_mc_bytes - psta->sta_stats.last_rx_mc_bytes
+			, psta->sta_stats.rx_mc_bytes, psta->sta_stats.last_rx_mc_bytes
+		);
+		RTW_PRINT_SEL(sel, "rx_bc_bytes:%llu(%llu - %llu)\n"
+			, psta->sta_stats.rx_bc_bytes - psta->sta_stats.last_rx_bc_bytes
+			, psta->sta_stats.rx_bc_bytes, psta->sta_stats.last_rx_bc_bytes
+		);
+	}
+
+	_RTW_PRINT_SEL(sel, "RTW: [TP] ");
+	tx_tp_mbips = psta->sta_stats.tx_tp_kbits >> 10;
+	rx_tp_mbips = psta->sta_stats.rx_tp_kbits >> 10;
+	bi_tp_mbips = tx_tp_mbips + rx_tp_mbips;
+
+	if (tx_tp_mbips)
+		_RTW_PRINT_SEL(sel, "Tx : %d(Mbps) ", tx_tp_mbips);
+	else
+		_RTW_PRINT_SEL(sel, "Tx : %d(Kbps) ", psta->sta_stats.tx_tp_kbits);
+
+	if (rx_tp_mbips) 
+		_RTW_PRINT_SEL(sel, "Rx : %d(Mbps) ", rx_tp_mbips);
+	else
+		_RTW_PRINT_SEL(sel, "Rx : %d(Kbps) ", psta->sta_stats.rx_tp_kbits);
+
+	if (bi_tp_mbips)
+		_RTW_PRINT_SEL(sel, "Total : %d(Mbps)\n", bi_tp_mbips);
+	else
+		_RTW_PRINT_SEL(sel, "Total : %d(Kbps)\n", psta->sta_stats.tx_tp_kbits + psta->sta_stats.rx_tp_kbits);
+
+
+	_RTW_PRINT_SEL(sel, "RTW: [Smooth TP] ");
+	tx_tp_mbips = psta->sta_stats.smooth_tx_tp_kbits >> 10;
+	rx_tp_mbips = psta->sta_stats.smooth_rx_tp_kbits >> 10;
+	bi_tp_mbips = tx_tp_mbips + rx_tp_mbips;
+	if (tx_tp_mbips)
+		_RTW_PRINT_SEL(sel, "Tx : %d(Mbps) ", tx_tp_mbips);
+	else
+		_RTW_PRINT_SEL(sel, "Tx : %d(Kbps) ", psta->sta_stats.smooth_tx_tp_kbits);
+
+	if (rx_tp_mbips) 
+		_RTW_PRINT_SEL(sel, "Rx : %d(Mbps) ", rx_tp_mbips);
+	else
+		_RTW_PRINT_SEL(sel, "Rx : %d(Kbps) ", psta->sta_stats.smooth_rx_tp_kbits);
+
+	if (bi_tp_mbips)
+		_RTW_PRINT_SEL(sel, "Total : %d(Mbps)\n", bi_tp_mbips);
+	else
+		_RTW_PRINT_SEL(sel, "Total : %d(Kbps)\n", psta->sta_stats.smooth_tx_tp_kbits + psta->sta_stats.rx_tp_kbits);
+
+	#if 0
+	RTW_PRINT_SEL(sel, "Moving-AVG TP {Tx,Rx,Total} = { %d , %d , %d } Mbps\n\n",
+		(psta->cmn.tx_moving_average_tp << 3), (psta->cmn.rx_moving_average_tp << 3),
+		(psta->cmn.tx_moving_average_tp + psta->cmn.rx_moving_average_tp) << 3);
+	#endif
+}
+
+void dump_sta_info(void *sel, struct sta_info *psta)
+{
+	struct ra_sta_info *ra_info;
+	u8 curr_tx_sgi = _FALSE;
+	u8 curr_tx_rate = 0;
+
+	if (!psta)
+		return;
+
+	ra_info = &psta->cmn.ra_info;
+
+	RTW_PRINT_SEL(sel, "============ STA [" MAC_FMT "]  ===================\n",
+		MAC_ARG(psta->cmn.mac_addr));
+	RTW_PRINT_SEL(sel, "mac_id : %d\n", psta->cmn.mac_id);
+	RTW_PRINT_SEL(sel, "wireless_mode : 0x%02x\n", psta->wireless_mode);
+	RTW_PRINT_SEL(sel, "mimo_type : %d\n", psta->cmn.mimo_type);
+	RTW_PRINT_SEL(sel, "bw_mode : %s, ra_bw_mode : %s\n",
+			ch_width_str(psta->cmn.bw_mode), ch_width_str(ra_info->ra_bw_mode));
+	RTW_PRINT_SEL(sel, "rate_id : %d\n", ra_info->rate_id);
+	RTW_PRINT_SEL(sel, "rssi : %d (%%), rssi_level : %d\n", psta->cmn.rssi_stat.rssi, ra_info->rssi_level);
+	RTW_PRINT_SEL(sel, "is_support_sgi : %s, is_vht_enable : %s\n",
+			(ra_info->is_support_sgi) ? "Y" : "N", (ra_info->is_vht_enable) ? "Y" : "N");
+	RTW_PRINT_SEL(sel, "disable_ra : %s, disable_pt : %s\n",
+				(ra_info->disable_ra) ? "Y" : "N", (ra_info->disable_pt) ? "Y" : "N");
+	RTW_PRINT_SEL(sel, "is_noisy : %s\n", (ra_info->is_noisy) ? "Y" : "N");
+	RTW_PRINT_SEL(sel, "txrx_state : %d\n", ra_info->txrx_state);/*0: uplink, 1:downlink, 2:bi-direction*/
+
+	curr_tx_sgi = rtw_get_current_tx_sgi(psta->padapter, psta);
+	curr_tx_rate = rtw_get_current_tx_rate(psta->padapter, psta);
+	RTW_PRINT_SEL(sel, "curr_tx_rate : %s (%s)\n",
+			HDATA_RATE(curr_tx_rate), (curr_tx_sgi) ? "S" : "L");
+	RTW_PRINT_SEL(sel, "curr_tx_bw : %s\n", ch_width_str(ra_info->curr_tx_bw));
+	RTW_PRINT_SEL(sel, "curr_retry_ratio : %d\n", ra_info->curr_retry_ratio);
+	RTW_PRINT_SEL(sel, "ra_mask : 0x%016llx\n\n", ra_info->ramask);
+}
+
+void rtw_phydm_ra_registed(_adapter *adapter, struct sta_info *psta)
+{
+	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
+
+	if (psta == NULL) {
+		RTW_ERR(FUNC_ADPT_FMT" sta is NULL\n", FUNC_ADPT_ARG(adapter));
+		rtw_warn_on(1);
+		return;
+	}
+
+	phydm_ra_registed(&hal_data->odmpriv, psta->cmn.mac_id, psta->cmn.rssi_stat.rssi);
+	dump_sta_info(RTW_DBGDUMP, psta);
+}
+
+static void init_phydm_info(_adapter *adapter)
+{
+	PHAL_DATA_TYPE	hal_data = GET_HAL_DATA(adapter);
+	struct dm_struct *phydm = &(hal_data->odmpriv);
+
+	odm_cmn_info_init(phydm, ODM_CMNINFO_FW_VER, hal_data->firmware_version);
+	odm_cmn_info_init(phydm, ODM_CMNINFO_FW_SUB_VER, hal_data->firmware_sub_version);
+}
+void rtw_phydm_init(_adapter *adapter)
+{
+	PHAL_DATA_TYPE	hal_data = GET_HAL_DATA(adapter);
+	struct dm_struct	*phydm = &(hal_data->odmpriv);
+
+	init_phydm_info(adapter);
+	odm_dm_init(phydm);
+}
+
+#ifdef CONFIG_LPS_PG
+/*
+static void _lps_pg_state_update(_adapter *adapter)
+{
+	u8	is_in_lpspg = _FALSE;
+	struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(adapter);
+	PHAL_DATA_TYPE	pHalData = GET_HAL_DATA(adapter);
+	struct mlme_priv *pmlmepriv = &adapter->mlmepriv;
+	struct sta_priv *pstapriv = &adapter->stapriv;
+	struct sta_info *psta = NULL;
+
+	if ((pwrpriv->lps_level == LPS_PG) && (pwrpriv->pwr_mode != PS_MODE_ACTIVE) && (pwrpriv->rpwm <= PS_STATE_S2))
+		is_in_lpspg = _TRUE;
+	psta = rtw_get_stainfo(pstapriv, get_bssid(pmlmepriv));
+
+	if (psta)
+		psta->cmn.ra_info.disable_ra = (is_in_lpspg) ? _TRUE : _FALSE;
+}
+*/
+void rtw_phydm_lps_pg_hdl(_adapter *adapter, struct sta_info *sta, bool in_lpspg)
+{
+	struct dm_struct *phydm = adapter_to_phydm(adapter);
+	/*u8 rate_id;*/
+
+	if(sta == NULL) {
+		RTW_ERR("%s sta is null\n", __func__);
+		rtw_warn_on(1);
+		return;
+	}
+
+	if (in_lpspg) {
+		sta->cmn.ra_info.disable_ra = _TRUE;
+		sta->cmn.ra_info.disable_pt = _TRUE;
+		/*TODO : DRV fix tx rate*/
+		/*rate_id = phydm_get_rate_from_rssi_lv(phydm, sta->cmn.mac_id);*/
+	} else {
+		sta->cmn.ra_info.disable_ra = _FALSE;
+		sta->cmn.ra_info.disable_pt = _FALSE;
+	}
+
+	rtw_phydm_ra_registed(adapter, sta);
+}
+#endif
+
+/*#define DBG_PHYDM_STATE_CHK*/
+
+
+static u8 _rtw_phydm_rfk_condition_check(_adapter *adapter, u8 is_scaning, u8 ifs_linked)
+{
+	u8 rfk_allowed = _TRUE;
+
+	#ifdef CONFIG_SKIP_RFK_IN_DM
+	rfk_allowed = _FALSE;
+	if (0)
+		RTW_ERR("[RFK-CHK] RF-K not allowed due to CONFIG_SKIP_RFK_IN_DM\n");
+	return rfk_allowed;
+	#endif
+
+	if (ifs_linked) {
+		if (is_scaning) {
+			rfk_allowed = _FALSE;
+			RTW_ERR("[RFK-CHK] RF-K not allowed due to ifaces under site-survey\n");
+		}
+		else {
+			rfk_allowed = rtw_mi_stayin_union_ch_chk(adapter) ? _TRUE : _FALSE;
+			if (rfk_allowed == _FALSE)
+				RTW_ERR("[RFK-CHK] RF-K not allowed due to ld_iface not stayin union ch\n");
+		}
+	}
+
+	#ifdef CONFIG_MCC_MODE
+	/*not in MCC State*/
+	if (MCC_EN(adapter)) {
+		if (rtw_hal_check_mcc_status(adapter, MCC_STATUS_DOING_MCC)) {
+			rfk_allowed = _FALSE;
+			if (0)
+				RTW_ERR("[RFK-CHK] RF-K not allowed due to doing MCC\n");
+		}
+	}
+	#endif
+
+	#if defined(CONFIG_TDLS) && defined(CONFIG_TDLS_CH_SW)
+
+	#endif
+
+	return rfk_allowed;
+}
+#if ((RTL8822B_SUPPORT == 1) || (RTL8821C_SUPPORT == 1) || (RTL8814B_SUPPORT == 1))
+static u8 _rtw_phydm_iqk_segment_chk(_adapter *adapter, u8 ifs_linked)
+{
+	u8 iqk_sgt = _FALSE;
+
+#if 0
+	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
+	if (is_linked && (dvobj->traffic_stat.cur_tx_tp > 2 || dvobj->traffic_stat.cur_rx_tp > 2))
+		rst = _TRUE;
+#else
+	if (ifs_linked)
+		iqk_sgt = _TRUE;
+#endif
+	return iqk_sgt;
+}
+#endif
+
+/*check the tx low rate while unlinked to any AP;for pwr tracking */
+static u8 _rtw_phydm_pwr_tracking_rate_check(_adapter *adapter)
+{
+	int i;
+	_adapter *iface;
+	u8		if_tx_rate = 0xFF;
+	u8		tx_rate = 0xFF;
+	struct mlme_ext_priv	*pmlmeext = NULL;
+	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
+
+	for (i = 0; i < dvobj->iface_nums; i++) {
+		iface = dvobj->padapters[i];
+		pmlmeext = &(iface->mlmeextpriv);
+		if ((iface) && rtw_is_adapter_up(iface)) {
+#ifdef CONFIG_P2P
+			if (!rtw_p2p_chk_role(&(iface)->wdinfo, P2P_ROLE_DISABLE))
+				if_tx_rate = IEEE80211_OFDM_RATE_6MB;
+			else
+#endif
+				if_tx_rate = pmlmeext->tx_rate;
+			if(if_tx_rate < tx_rate)
+				tx_rate = if_tx_rate;
+
+			RTW_DBG("%s i=%d tx_rate =0x%x\n", __func__, i, if_tx_rate);
+		}
+	}
+	RTW_DBG("%s tx_low_rate (unlinked to any AP)=0x%x\n", __func__, tx_rate);
+	return tx_rate;
+}
+
+#ifdef CONFIG_DYNAMIC_SOML
+void rtw_dyn_soml_byte_update(_adapter *adapter, u8 data_rate, u32 size)
+{
+	struct dm_struct *phydm = adapter_to_phydm(adapter);
+
+	phydm_soml_bytes_acq(phydm, data_rate, size);
+}
+
+void rtw_dyn_soml_para_set(_adapter *adapter, u8 train_num, u8 intvl,
+			u8 period, u8 delay)
+{
+	struct dm_struct *phydm = adapter_to_phydm(adapter);
+
+	phydm_adaptive_soml_para_set(phydm, train_num, intvl, period, delay);
+	RTW_INFO("%s.\n", __func__);
+}
+
+void rtw_dyn_soml_config(_adapter *adapter)
+{
+	RTW_INFO("%s.\n", __func__);
+
+	if (adapter->registrypriv.dyn_soml_en == 1) {
+		/* Must after phydm_adaptive_soml_init() */
+		rtw_hal_set_hwreg(adapter , HW_VAR_SET_SOML_PARAM , NULL);
+		RTW_INFO("dyn_soml_en = 1\n");
+	} else {
+		if (adapter->registrypriv.dyn_soml_en == 2) {
+			rtw_dyn_soml_para_set(adapter, 
+				adapter->registrypriv.dyn_soml_train_num, 
+				adapter->registrypriv.dyn_soml_interval, 
+				adapter->registrypriv.dyn_soml_period,
+				adapter->registrypriv.dyn_soml_delay);
+			RTW_INFO("dyn_soml_en = 2\n");
+			RTW_INFO("dyn_soml_en, param = %d, %d, %d, %d\n",
+				adapter->registrypriv.dyn_soml_train_num,
+				adapter->registrypriv.dyn_soml_interval, 
+				adapter->registrypriv.dyn_soml_period,
+				adapter->registrypriv.dyn_soml_delay);
+		} else if (adapter->registrypriv.dyn_soml_en == 0) {
+			RTW_INFO("dyn_soml_en = 0\n");
+		} else
+			RTW_ERR("%s, wrong setting: dyn_soml_en = %d\n", __func__,
+				adapter->registrypriv.dyn_soml_en);
+	}
+}
+#endif
+
+
+void rtw_phydm_read_efuse(_adapter *adapter)
+{
+	PHAL_DATA_TYPE hal_data = GET_HAL_DATA(adapter);
+	struct dm_struct *phydm = &(hal_data->odmpriv);
+
+	/*PHYDM API - thermal trim*/
+	phydm_get_thermal_trim_offset(phydm);
+	/*PHYDM API - power trim*/
+	phydm_get_power_trim_offset(phydm);
+}
+
+void rtw_phydm_watchdog(_adapter *adapter)
+{
+	u8	bLinked = _FALSE;
+	u8	bsta_state = _FALSE;
+	u8	bBtDisabled = _TRUE;
+	u8	rfk_forbidden = _FALSE;
+	#if ((RTL8822B_SUPPORT == 1) || (RTL8821C_SUPPORT == 1) || (RTL8814B_SUPPORT == 1))
+	u8	segment_iqk = _FALSE;
+	#endif
+	u8	tx_unlinked_low_rate = 0xFF;
+	PHAL_DATA_TYPE	pHalData = GET_HAL_DATA(adapter);
+	struct pwrctrl_priv *pwrctl = adapter_to_pwrctl(adapter);
+
+	if (!rtw_is_hw_init_completed(adapter)) {
+		RTW_DBG("%s skip due to hw_init_completed == FALSE\n", __func__);
+		return;
+	}
+	if (rtw_mi_check_fwstate(adapter, _FW_UNDER_SURVEY))
+		pHalData->bScanInProcess = _TRUE;
+	else
+		pHalData->bScanInProcess = _FALSE;
+
+	if (rtw_mi_check_status(adapter, MI_ASSOC)) {
+		bLinked = _TRUE;
+		if (rtw_mi_check_status(adapter, MI_STA_LINKED))
+		bsta_state = _TRUE;
+	}
+
+	odm_cmn_info_update(&pHalData->odmpriv, ODM_CMNINFO_LINK, bLinked);
+	odm_cmn_info_update(&pHalData->odmpriv, ODM_CMNINFO_STATION_STATE, bsta_state);
+
+	#ifdef CONFIG_BT_COEXIST
+	bBtDisabled = rtw_btcoex_IsBtDisabled(adapter);
+	#endif /* CONFIG_BT_COEXIST */
+	odm_cmn_info_update(&pHalData->odmpriv, ODM_CMNINFO_BT_ENABLED,
+							(bBtDisabled == _TRUE) ? _FALSE : _TRUE);
+
+	rfk_forbidden = (_rtw_phydm_rfk_condition_check(adapter, pHalData->bScanInProcess, bLinked) == _TRUE) ? _FALSE : _TRUE;
+	halrf_cmn_info_set(&pHalData->odmpriv, HALRF_CMNINFO_RFK_FORBIDDEN, rfk_forbidden);
+
+	#if ((RTL8822B_SUPPORT == 1) || (RTL8821C_SUPPORT == 1) || (RTL8814B_SUPPORT == 1))
+	segment_iqk = _rtw_phydm_iqk_segment_chk(adapter, bLinked);
+	halrf_cmn_info_set(&pHalData->odmpriv, HALRF_CMNINFO_IQK_SEGMENT, segment_iqk);
+	#endif
+	#ifdef DBG_PHYDM_STATE_CHK
+	RTW_INFO("%s rfk_forbidden = %s, segment_iqk = %s\n",
+			__func__, (rfk_forbidden) ? "Y" : "N", (segment_iqk) ? "Y" : "N");
+	#endif
+
+	if (bLinked == _FALSE) {
+		tx_unlinked_low_rate = _rtw_phydm_pwr_tracking_rate_check(adapter);
+		halrf_cmn_info_set(&pHalData->odmpriv, HALRF_CMNINFO_RATE_INDEX, tx_unlinked_low_rate);
+	}
+
+	/*if (!rtw_mi_stayin_union_band_chk(adapter)) {
+		#ifdef DBG_PHYDM_STATE_CHK
+		RTW_ERR("Not stay in union band, skip phydm\n");
+		#endif
+		goto _exit;
+	}*/
+	if (pwrctl->bpower_saving)
+		phydm_watchdog_lps(&pHalData->odmpriv);
+	else
+		phydm_watchdog(&pHalData->odmpriv);
+
+	#ifdef CONFIG_RTW_ACS
+	rtw_acs_update_current_info(adapter);
+	#endif
+
+_exit:
+	return;
+}
+
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/hal_dm.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/hal_dm.h
--- linux-5.6.3/3rdparty/rtl8821ce/hal/hal_dm.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/hal_dm.h	2020-04-10 16:35:06.789658807 +0300
@@ -0,0 +1,100 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#ifndef __HAL_DM_H__
+#define __HAL_DM_H__
+
+#define adapter_to_phydm(adapter) (&(GET_HAL_DATA(adapter)->odmpriv))
+#define dvobj_to_phydm(dvobj) adapter_to_phydm(dvobj_get_primary_adapter(dvobj))
+
+void rtw_phydm_priv_init(_adapter *adapter);
+void Init_ODM_ComInfo(_adapter *adapter);
+void rtw_phydm_init(_adapter *adapter);
+
+void rtw_hal_turbo_edca(_adapter *adapter);
+u8 rtw_phydm_is_iqk_in_progress(_adapter *adapter);
+
+void GetHalODMVar(
+	PADAPTER				Adapter,
+	HAL_ODM_VARIABLE		eVariable,
+	PVOID					pValue1,
+	PVOID					pValue2);
+void SetHalODMVar(
+	PADAPTER				Adapter,
+	HAL_ODM_VARIABLE		eVariable,
+	PVOID					pValue1,
+	BOOLEAN					bSet);
+
+void rtw_phydm_ra_registed(_adapter *adapter, struct sta_info *psta);
+
+#ifdef CONFIG_DYNAMIC_SOML
+void rtw_dyn_soml_byte_update(_adapter *adapter, u8 data_rate, u32 size);
+void rtw_dyn_soml_para_set(_adapter *adapter, u8 train_num, u8 intvl,
+			u8 period, u8 delay);
+void rtw_dyn_soml_config(_adapter *adapter);
+#endif
+void rtw_phydm_watchdog(_adapter *adapter);
+
+void rtw_hal_update_iqk_fw_offload_cap(_adapter *adapter);
+void dump_sta_info(void *sel, struct sta_info *psta);
+void dump_sta_traffic(void *sel, _adapter *adapter, struct sta_info *psta);
+
+#ifdef CONFIG_DBG_RF_CAL
+void rtw_hal_iqk_test(_adapter *adapter, bool recovery, bool clear, bool segment);
+void rtw_hal_lck_test(_adapter *adapter);
+#endif
+
+s8 rtw_phydm_get_min_rssi(_adapter *adapter);
+u8 rtw_phydm_get_cur_igi(_adapter *adapter);
+
+
+#ifdef CONFIG_LPS_LCLK_WD_TIMER
+extern void phydm_rssi_monitor_check(void *p_dm_void);
+
+void rtw_phydm_wd_lps_lclk_hdl(_adapter *adapter);
+void rtw_phydm_watchdog_in_lps_lclk(_adapter *adapter);
+#endif
+
+enum phy_cnt {
+	FA_OFDM,
+	FA_CCK,
+	FA_TOTAL,
+	CCA_OFDM,
+	CCA_CCK,
+	CCA_ALL,
+	CRC32_OK_VHT,
+	CRC32_OK_HT,
+	CRC32_OK_LEGACY,
+	CRC32_OK_CCK,
+	CRC32_ERROR_VHT,
+	CRC32_ERROR_HT,
+	CRC32_ERROR_LEGACY,
+	CRC32_ERROR_CCK,
+};
+u32 rtw_phydm_get_phy_cnt(_adapter *adapter, enum phy_cnt cnt);
+#if ((RTL8822B_SUPPORT == 1) || (RTL8821C_SUPPORT == 1) || (RTL8814B_SUPPORT == 1))
+void rtw_phydm_iqk_trigger(_adapter *adapter);
+#endif
+void rtw_phydm_read_efuse(_adapter *adapter);
+
+#ifdef CONFIG_SUPPORT_DYNAMIC_TXPWR
+void rtw_phydm_set_dyntxpwr(_adapter *adapter, u8 *desc, u8 mac_id);
+#endif
+#ifdef CONFIG_RTW_TX_2PATH_EN
+void rtw_phydm_tx_2path_en(_adapter *adapter);
+#endif
+#ifdef CONFIG_LPS_PG
+void rtw_phydm_lps_pg_hdl(_adapter *adapter, struct sta_info *sta, bool in_lpspg);
+#endif
+#endif /* __HAL_DM_H__ */
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/hal_halmac.c linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/hal_halmac.c
--- linux-5.6.3/3rdparty/rtl8821ce/hal/hal_halmac.c	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/hal_halmac.c	2020-04-10 16:35:06.789658807 +0300
@@ -0,0 +1,5252 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2015 - 2018 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#define _HAL_HALMAC_C_
+
+#include <drv_types.h>		/* PADAPTER, struct dvobj_priv, SDIO_ERR_VAL8 and etc. */
+#include <hal_data.h>		/* efuse, PHAL_DATA_TYPE and etc. */
+#include "hal_halmac.h"		/* dvobj_to_halmac() and ect. */
+
+/*
+ * HALMAC take return value 0 for fail and 1 for success to replace
+ * _FALSE/_TRUE after V1_04_09
+ */
+#define RTW_HALMAC_FAIL			0
+#define RTW_HALMAC_SUCCESS		1
+
+#define DEFAULT_INDICATOR_TIMELMT	1000	/* ms */
+#define MSG_PREFIX			"[HALMAC]"
+
+#define RTW_HALMAC_DLFW_MEM_NO_STOP_TX
+
+/*
+ * Driver API for HALMAC operations
+ */
+
+#ifdef CONFIG_SDIO_HCI
+#include <rtw_sdio.h>
+
+static u8 _halmac_mac_reg_page0_chk(const char *func, struct dvobj_priv *dvobj, u32 offset)
+{
+#if defined(CONFIG_IO_CHECK_IN_ANA_LOW_CLK) && defined(CONFIG_LPS_LCLK)
+	struct pwrctrl_priv *pwrpriv = &dvobj->pwrctl_priv;
+	u32 mac_reg_offset = 0;
+
+	if (pwrpriv->pwr_mode == PS_MODE_ACTIVE)
+		return _TRUE;
+
+	if (pwrpriv->lps_level == LPS_NORMAL)
+		return _TRUE;
+
+	if (pwrpriv->rpwm >= PS_STATE_S2)
+		return _TRUE;
+
+	if (offset & (WLAN_IOREG_DEVICE_ID << 13))  { /*WLAN_IOREG_OFFSET*/
+		mac_reg_offset = offset & HALMAC_WLAN_MAC_REG_MSK;
+		if (mac_reg_offset < 0x100) {
+			RTW_ERR(FUNC_ADPT_FMT
+				"access MAC REG -0x%04x in PS-mode:0x%02x (rpwm:0x%02x, lps_level:0x%02x)\n",
+				FUNC_ADPT_ARG(dvobj_get_primary_adapter(dvobj)), mac_reg_offset,
+				pwrpriv->pwr_mode, pwrpriv->rpwm, pwrpriv->lps_level);
+			rtw_warn_on(1);
+			return _FALSE;
+		}
+	}
+#endif
+	return _TRUE;
+}
+
+static u8 _halmac_sdio_cmd52_read(void *p, u32 offset)
+{
+	struct dvobj_priv *d;
+	u8 val;
+	u8 ret;
+
+
+	d = (struct dvobj_priv *)p;
+	_halmac_mac_reg_page0_chk(__func__, d, offset);
+	ret = rtw_sdio_read_cmd52(d, offset, &val, 1);
+	if (_FAIL == ret) {
+		RTW_ERR("%s: I/O FAIL!\n", __FUNCTION__);
+		return SDIO_ERR_VAL8;
+	}
+
+	return val;
+}
+
+static void _halmac_sdio_cmd52_write(void *p, u32 offset, u8 val)
+{
+	struct dvobj_priv *d;
+	u8 ret;
+
+
+	d = (struct dvobj_priv *)p;
+	_halmac_mac_reg_page0_chk(__func__, d, offset);
+	ret = rtw_sdio_write_cmd52(d, offset, &val, 1);
+	if (_FAIL == ret)
+		RTW_ERR("%s: I/O FAIL!\n", __FUNCTION__);
+}
+
+static u8 _halmac_sdio_reg_read_8(void *p, u32 offset)
+{
+	struct dvobj_priv *d;
+	u8 *pbuf;
+	u8 val;
+	u8 ret;
+
+
+	d = (struct dvobj_priv *)p;
+	val = SDIO_ERR_VAL8;
+	_halmac_mac_reg_page0_chk(__func__, d, offset);
+	pbuf = rtw_zmalloc(1);
+	if (!pbuf)
+		return val;
+
+	ret = rtw_sdio_read_cmd53(d, offset, pbuf, 1);
+	if (ret == _FAIL) {
+		RTW_ERR("%s: I/O FAIL!\n", __FUNCTION__);
+		goto exit;
+	}
+
+	val = *pbuf;
+
+exit:
+	rtw_mfree(pbuf, 1);
+
+	return val;
+}
+
+static u16 _halmac_sdio_reg_read_16(void *p, u32 offset)
+{
+	struct dvobj_priv *d;
+	u8 *pbuf;
+	u16 val;
+	u8 ret;
+
+
+	d = (struct dvobj_priv *)p;
+	val = SDIO_ERR_VAL16;
+	_halmac_mac_reg_page0_chk(__func__, d, offset);
+	pbuf = rtw_zmalloc(2);
+	if (!pbuf)
+		return val;
+
+	ret = rtw_sdio_read_cmd53(d, offset, pbuf, 2);
+	if (ret == _FAIL) {
+		RTW_ERR("%s: I/O FAIL!\n", __FUNCTION__);
+		goto exit;
+	}
+
+	val = le16_to_cpu(*(u16 *)pbuf);
+
+exit:
+	rtw_mfree(pbuf, 2);
+
+	return val;
+}
+
+static u32 _halmac_sdio_reg_read_32(void *p, u32 offset)
+{
+	struct dvobj_priv *d;
+	u8 *pbuf;
+	u32 val;
+	u8 ret;
+
+
+	d = (struct dvobj_priv *)p;
+	val = SDIO_ERR_VAL32;
+	_halmac_mac_reg_page0_chk(__func__, d, offset);
+	pbuf = rtw_zmalloc(4);
+	if (!pbuf)
+		return val;
+
+	ret = rtw_sdio_read_cmd53(d, offset, pbuf, 4);
+	if (ret == _FAIL) {
+		RTW_ERR("%s: I/O FAIL!\n", __FUNCTION__);
+		goto exit;
+	}
+
+	val = le32_to_cpu(*(u32 *)pbuf);
+
+exit:
+	rtw_mfree(pbuf, 4);
+
+	return val;
+}
+
+static u8 _halmac_sdio_reg_read_n(void *p, u32 offset, u32 size, u8 *data)
+{
+	struct dvobj_priv *d = (struct dvobj_priv *)p;
+	u8 *pbuf;
+	u8 ret;
+	u8 rst = RTW_HALMAC_FAIL;
+	u32 sdio_read_size;
+
+
+	sdio_read_size = RND4(size);
+	sdio_read_size = rtw_sdio_cmd53_align_size(d, sdio_read_size);
+
+	pbuf = rtw_zmalloc(sdio_read_size);
+	if ((!pbuf) || (!data))
+		return rst;
+
+	ret = rtw_sdio_read_cmd53(d, offset, pbuf, sdio_read_size);
+	if (ret == _FAIL) {
+		RTW_ERR("%s: I/O FAIL!\n", __FUNCTION__);
+		goto exit;
+	}
+
+	_rtw_memcpy(data, pbuf, size);
+	rst = RTW_HALMAC_SUCCESS;
+exit:
+	rtw_mfree(pbuf, sdio_read_size);
+
+	return rst;
+}
+
+static void _halmac_sdio_reg_write_8(void *p, u32 offset, u8 val)
+{
+	struct dvobj_priv *d;
+	u8 *pbuf;
+	u8 ret;
+
+
+	d = (struct dvobj_priv *)p;
+	_halmac_mac_reg_page0_chk(__func__, d, offset);
+	pbuf = rtw_zmalloc(1);
+	if (!pbuf)
+		return;
+	_rtw_memcpy(pbuf, &val, 1);
+
+	ret = rtw_sdio_write_cmd53(d, offset, pbuf, 1);
+	if (ret == _FAIL)
+		RTW_ERR("%s: I/O FAIL!\n", __FUNCTION__);
+
+	rtw_mfree(pbuf, 1);
+}
+
+static void _halmac_sdio_reg_write_16(void *p, u32 offset, u16 val)
+{
+	struct dvobj_priv *d;
+	u8 *pbuf;
+	u8 ret;
+
+
+	d = (struct dvobj_priv *)p;
+	_halmac_mac_reg_page0_chk(__func__, d, offset);
+	val = cpu_to_le16(val);
+	pbuf = rtw_zmalloc(2);
+	if (!pbuf)
+		return;
+	_rtw_memcpy(pbuf, &val, 2);
+
+	ret = rtw_sdio_write_cmd53(d, offset, pbuf, 2);
+	if (ret == _FAIL)
+		RTW_ERR("%s: I/O FAIL!\n", __FUNCTION__);
+
+	rtw_mfree(pbuf, 2);
+}
+
+static void _halmac_sdio_reg_write_32(void *p, u32 offset, u32 val)
+{
+	struct dvobj_priv *d;
+	u8 *pbuf;
+	u8 ret;
+
+
+	d = (struct dvobj_priv *)p;
+	_halmac_mac_reg_page0_chk(__func__, d, offset);
+	val = cpu_to_le32(val);
+	pbuf = rtw_zmalloc(4);
+	if (!pbuf)
+		return;
+	_rtw_memcpy(pbuf, &val, 4);
+
+	ret = rtw_sdio_write_cmd53(d, offset, pbuf, 4);
+	if (ret == _FAIL)
+		RTW_ERR("%s: I/O FAIL!\n", __FUNCTION__);
+
+	rtw_mfree(pbuf, 4);
+}
+
+static u8 _halmac_sdio_read_cia(void *p, u32 offset)
+{
+	struct dvobj_priv *d;
+	u8 data = 0;
+	u8 ret;
+
+
+	d = (struct dvobj_priv *)p;
+
+	ret = rtw_sdio_f0_read(d, offset, &data, 1);
+	if (ret == _FAIL)
+		RTW_ERR("%s: I/O FAIL!\n", __FUNCTION__);
+
+	return data;
+}
+
+#else /* !CONFIG_SDIO_HCI */
+
+static u8 _halmac_reg_read_8(void *p, u32 offset)
+{
+	struct dvobj_priv *d;
+	PADAPTER adapter;
+
+
+	d = (struct dvobj_priv *)p;
+	adapter = dvobj_get_primary_adapter(d);
+
+	return rtw_read8(adapter, offset);
+}
+
+static u16 _halmac_reg_read_16(void *p, u32 offset)
+{
+	struct dvobj_priv *d;
+	PADAPTER adapter;
+
+
+	d = (struct dvobj_priv *)p;
+	adapter = dvobj_get_primary_adapter(d);
+
+	return rtw_read16(adapter, offset);
+}
+
+static u32 _halmac_reg_read_32(void *p, u32 offset)
+{
+	struct dvobj_priv *d;
+	PADAPTER adapter;
+
+
+	d = (struct dvobj_priv *)p;
+	adapter = dvobj_get_primary_adapter(d);
+
+	return rtw_read32(adapter, offset);
+}
+
+static void _halmac_reg_write_8(void *p, u32 offset, u8 val)
+{
+	struct dvobj_priv *d;
+	PADAPTER adapter;
+	int err;
+
+
+	d = (struct dvobj_priv *)p;
+	adapter = dvobj_get_primary_adapter(d);
+
+	err = rtw_write8(adapter, offset, val);
+	if (err == _FAIL)
+		RTW_ERR("%s: I/O FAIL!\n", __FUNCTION__);
+}
+
+static void _halmac_reg_write_16(void *p, u32 offset, u16 val)
+{
+	struct dvobj_priv *d;
+	PADAPTER adapter;
+	int err;
+
+
+	d = (struct dvobj_priv *)p;
+	adapter = dvobj_get_primary_adapter(d);
+
+	err = rtw_write16(adapter, offset, val);
+	if (err == _FAIL)
+		RTW_ERR("%s: I/O FAIL!\n", __FUNCTION__);
+}
+
+static void _halmac_reg_write_32(void *p, u32 offset, u32 val)
+{
+	struct dvobj_priv *d;
+	PADAPTER adapter;
+	int err;
+
+
+	d = (struct dvobj_priv *)p;
+	adapter = dvobj_get_primary_adapter(d);
+
+	err = rtw_write32(adapter, offset, val);
+	if (err == _FAIL)
+		RTW_ERR("%s: I/O FAIL!\n", __FUNCTION__);
+}
+#endif /* !CONFIG_SDIO_HCI */
+
+static u8 _halmac_mfree(void *p, void *buffer, u32 size)
+{
+	rtw_mfree(buffer, size);
+	return RTW_HALMAC_SUCCESS;
+}
+
+static void *_halmac_malloc(void *p, u32 size)
+{
+	return rtw_zmalloc(size);
+}
+
+static u8 _halmac_memcpy(void *p, void *dest, void *src, u32 size)
+{
+	_rtw_memcpy(dest, src, size);
+	return RTW_HALMAC_SUCCESS;
+}
+
+static u8 _halmac_memset(void *p, void *addr, u8 value, u32 size)
+{
+	_rtw_memset(addr, value, size);
+	return RTW_HALMAC_SUCCESS;
+}
+
+static void _halmac_udelay(void *p, u32 us)
+{
+	/* Most hardware polling wait time < 50us) */
+	if (us <= 50)
+		rtw_udelay_os(us);
+	else if (us <= 1000)
+		rtw_usleep_os(us);
+	else
+		rtw_msleep_os(RTW_DIV_ROUND_UP(us, 1000));
+}
+
+static u8 _halmac_mutex_init(void *p, HALMAC_MUTEX *pMutex)
+{
+	_rtw_mutex_init(pMutex);
+	return RTW_HALMAC_SUCCESS;
+}
+
+static u8 _halmac_mutex_deinit(void *p, HALMAC_MUTEX *pMutex)
+{
+	_rtw_mutex_free(pMutex);
+	return RTW_HALMAC_SUCCESS;
+}
+
+static u8 _halmac_mutex_lock(void *p, HALMAC_MUTEX *pMutex)
+{
+	int err;
+
+	err = _enter_critical_mutex(pMutex, NULL);
+	if (err)
+		return RTW_HALMAC_FAIL;
+
+	return RTW_HALMAC_SUCCESS;
+}
+
+static u8 _halmac_mutex_unlock(void *p, HALMAC_MUTEX *pMutex)
+{
+	_exit_critical_mutex(pMutex, NULL);
+	return RTW_HALMAC_SUCCESS;
+}
+
+static u8 _halmac_msg_print(void *p, u32 msg_type, u8 msg_level, s8 *fmt, ...)
+{
+#define MSG_LEN		100
+	va_list args;
+	u8 str[MSG_LEN] = {0};
+	int err;
+	u8 ret = RTW_HALMAC_SUCCESS;
+
+
+	str[0] = '\n';
+	va_start(args, fmt);
+	err = vsnprintf(str, MSG_LEN, fmt, args);
+	va_end(args);
+
+	/* An output error is encountered */
+	if (err < 0)
+		return RTW_HALMAC_FAIL;
+	/* Output may be truncated due to size limit */
+	if ((err == (MSG_LEN - 1)) && (str[MSG_LEN - 2] != '\n'))
+		ret = RTW_HALMAC_FAIL;
+
+	if (msg_level == HALMAC_DBG_ALWAYS)
+		RTW_PRINT(MSG_PREFIX "%s", str);
+	else if (msg_level <= HALMAC_DBG_ERR)
+		RTW_ERR(MSG_PREFIX "%s", str);
+	else if (msg_level <= HALMAC_DBG_WARN)
+		RTW_WARN(MSG_PREFIX "%s", str);
+	else
+		RTW_DBG(MSG_PREFIX "%s", str);
+
+	return ret;
+}
+
+static u8 _halmac_buff_print(void *p, u32 msg_type, u8 msg_level, s8 *buf, u32 size)
+{
+	if (msg_level <= HALMAC_DBG_WARN)
+		RTW_INFO_DUMP(MSG_PREFIX, buf, size);
+	else
+		RTW_DBG_DUMP(MSG_PREFIX, buf, size);
+
+	return RTW_HALMAC_SUCCESS;
+}
+
+
+const char *const RTW_HALMAC_FEATURE_NAME[] = {
+	"HALMAC_FEATURE_CFG_PARA",
+	"HALMAC_FEATURE_DUMP_PHYSICAL_EFUSE",
+	"HALMAC_FEATURE_DUMP_LOGICAL_EFUSE",
+	"HALMAC_FEATURE_UPDATE_PACKET",
+	"HALMAC_FEATURE_UPDATE_DATAPACK",
+	"HALMAC_FEATURE_RUN_DATAPACK",
+	"HALMAC_FEATURE_CHANNEL_SWITCH",
+	"HALMAC_FEATURE_IQK",
+	"HALMAC_FEATURE_POWER_TRACKING",
+	"HALMAC_FEATURE_PSD",
+	"HALMAC_FEATURE_FW_SNDING",
+	"HALMAC_FEATURE_ALL"
+};
+
+static inline u8 is_valid_id_status(enum halmac_feature_id id, enum halmac_cmd_process_status status)
+{
+	switch (id) {
+	case HALMAC_FEATURE_CFG_PARA:
+		RTW_DBG("%s: %s\n", __FUNCTION__, RTW_HALMAC_FEATURE_NAME[id]);
+		break;
+	case HALMAC_FEATURE_DUMP_PHYSICAL_EFUSE:
+		RTW_INFO("%s: %s\n", __FUNCTION__, RTW_HALMAC_FEATURE_NAME[id]);
+		if (HALMAC_CMD_PROCESS_DONE != status)
+			RTW_INFO("%s: id(%d) unspecified status(%d)!\n",
+				 __FUNCTION__, id, status);
+		break;
+	case HALMAC_FEATURE_DUMP_LOGICAL_EFUSE:
+		RTW_INFO("%s: %s\n", __FUNCTION__, RTW_HALMAC_FEATURE_NAME[id]);
+		if (HALMAC_CMD_PROCESS_DONE != status)
+			RTW_INFO("%s: id(%d) unspecified status(%d)!\n",
+				 __FUNCTION__, id, status);
+		break;
+	case HALMAC_FEATURE_UPDATE_PACKET:
+		RTW_INFO("%s: %s\n", __FUNCTION__, RTW_HALMAC_FEATURE_NAME[id]);
+		break;
+	case HALMAC_FEATURE_UPDATE_DATAPACK:
+		RTW_INFO("%s: %s\n", __FUNCTION__, RTW_HALMAC_FEATURE_NAME[id]);
+		break;
+	case HALMAC_FEATURE_RUN_DATAPACK:
+		RTW_INFO("%s: %s\n", __FUNCTION__, RTW_HALMAC_FEATURE_NAME[id]);
+		break;
+	case HALMAC_FEATURE_CHANNEL_SWITCH:
+		RTW_INFO("%s: %s\n", __FUNCTION__, RTW_HALMAC_FEATURE_NAME[id]);
+		break;
+	case HALMAC_FEATURE_IQK:
+		RTW_INFO("%s: %s\n", __FUNCTION__, RTW_HALMAC_FEATURE_NAME[id]);
+		break;
+	case HALMAC_FEATURE_POWER_TRACKING:
+		RTW_INFO("%s: %s\n", __FUNCTION__, RTW_HALMAC_FEATURE_NAME[id]);
+		break;
+	case HALMAC_FEATURE_PSD:
+		RTW_INFO("%s: %s\n", __FUNCTION__, RTW_HALMAC_FEATURE_NAME[id]);
+		break;
+	case HALMAC_FEATURE_FW_SNDING:
+		RTW_INFO("%s: %s\n", __FUNCTION__, RTW_HALMAC_FEATURE_NAME[id]);
+		break;
+	case HALMAC_FEATURE_ALL:
+		RTW_INFO("%s: %s\n", __FUNCTION__, RTW_HALMAC_FEATURE_NAME[id]);
+		break;
+	default:
+		RTW_ERR("%s: unknown feature id(%d)\n", __FUNCTION__, id);
+		return _FALSE;
+	}
+
+	return _TRUE;
+}
+
+static int init_halmac_event_with_waittime(struct dvobj_priv *d, enum halmac_feature_id id, u8 *buf, u32 size, u32 time)
+{
+	struct submit_ctx *sctx;
+
+
+	if (!d->hmpriv.indicator[id].sctx) {
+		sctx = (struct submit_ctx *)rtw_zmalloc(sizeof(*sctx));
+		if (!sctx)
+			return -1;
+	} else {
+		RTW_WARN("%s: id(%d) sctx is not NULL!!\n", __FUNCTION__, id);
+		sctx = d->hmpriv.indicator[id].sctx;
+		d->hmpriv.indicator[id].sctx = NULL;
+	}
+
+	rtw_sctx_init(sctx, time);
+	d->hmpriv.indicator[id].buffer = buf;
+	d->hmpriv.indicator[id].buf_size = size;
+	d->hmpriv.indicator[id].ret_size = 0;
+	d->hmpriv.indicator[id].status = 0;
+	/* fill sctx at least to sure other variables are all ready! */
+	d->hmpriv.indicator[id].sctx = sctx;
+
+	return 0;
+}
+
+static inline int init_halmac_event(struct dvobj_priv *d, enum halmac_feature_id id, u8 *buf, u32 size)
+{
+	return init_halmac_event_with_waittime(d, id, buf, size, DEFAULT_INDICATOR_TIMELMT);
+}
+
+static void free_halmac_event(struct dvobj_priv *d, enum halmac_feature_id id)
+{
+	struct submit_ctx *sctx;
+
+
+	if (!d->hmpriv.indicator[id].sctx)
+		return;
+
+	sctx = d->hmpriv.indicator[id].sctx;
+	d->hmpriv.indicator[id].sctx = NULL;
+	rtw_mfree((u8 *)sctx, sizeof(*sctx));
+}
+
+static int wait_halmac_event(struct dvobj_priv *d, enum halmac_feature_id id)
+{
+	struct halmac_adapter *mac;
+	struct halmac_api *api;
+	struct submit_ctx *sctx;
+	int ret;
+
+
+	sctx = d->hmpriv.indicator[id].sctx;
+	if (!sctx)
+		return -1;
+
+	ret = rtw_sctx_wait(sctx, RTW_HALMAC_FEATURE_NAME[id]);
+	free_halmac_event(d, id);
+	if (_SUCCESS == ret)
+		return 0;
+
+	/* timeout! We have to reset halmac state */
+	RTW_ERR("%s: Wait id(%d, %s) TIMEOUT! Reset HALMAC state!\n",
+		__FUNCTION__, id, RTW_HALMAC_FEATURE_NAME[id]);
+	mac = dvobj_to_halmac(d);
+	api = HALMAC_GET_API(mac);
+	api->halmac_reset_feature(mac, id);
+
+	return -1;
+}
+
+/*
+ * Return:
+ *	Always return RTW_HALMAC_SUCCESS, HALMAC don't care the return value.
+ */
+static u8 _halmac_event_indication(void *p, enum halmac_feature_id feature_id, enum halmac_cmd_process_status process_status, u8 *buf, u32 size)
+{
+	struct dvobj_priv *d;
+	PADAPTER adapter;
+	PHAL_DATA_TYPE hal;
+	struct halmac_indicator *tbl, *indicator;
+	struct submit_ctx *sctx;
+	u32 cpsz;
+	u8 ret;
+
+
+	d = (struct dvobj_priv *)p;
+	adapter = dvobj_get_primary_adapter(d);
+	hal = GET_HAL_DATA(adapter);
+	tbl = d->hmpriv.indicator;
+
+	/* Filter(Skip) middle status indication */
+	ret = is_valid_id_status(feature_id, process_status);
+	if (_FALSE == ret)
+		goto exit;
+
+	indicator = &tbl[feature_id];
+	indicator->status = process_status;
+	indicator->ret_size = size;
+	if (!indicator->sctx) {
+		RTW_WARN("%s: No feature id(%d, %s) waiting!!\n", __FUNCTION__, feature_id, RTW_HALMAC_FEATURE_NAME[feature_id]);
+		goto exit;
+	}
+	sctx = indicator->sctx;
+
+	if (HALMAC_CMD_PROCESS_ERROR == process_status) {
+		RTW_ERR("%s: Something wrong id(%d, %s)!!\n", __FUNCTION__, feature_id, RTW_HALMAC_FEATURE_NAME[feature_id]);
+		rtw_sctx_done_err(&sctx, RTW_SCTX_DONE_UNKNOWN);
+		goto exit;
+	}
+
+	if (size > indicator->buf_size) {
+		RTW_WARN("%s: id(%d, %s) buffer is not enough(%d<%d), data will be truncated!\n",
+			 __FUNCTION__, feature_id, RTW_HALMAC_FEATURE_NAME[feature_id], indicator->buf_size, size);
+		cpsz = indicator->buf_size;
+	} else {
+		cpsz = size;
+	}
+	if (cpsz && indicator->buffer)
+		_rtw_memcpy(indicator->buffer, buf, cpsz);
+
+	rtw_sctx_done(&sctx);
+
+exit:
+	return RTW_HALMAC_SUCCESS;
+}
+
+struct halmac_platform_api rtw_halmac_platform_api = {
+	/* R/W register */
+#ifdef CONFIG_SDIO_HCI
+	.SDIO_CMD52_READ = _halmac_sdio_cmd52_read,
+	.SDIO_CMD53_READ_8 = _halmac_sdio_reg_read_8,
+	.SDIO_CMD53_READ_16 = _halmac_sdio_reg_read_16,
+	.SDIO_CMD53_READ_32 = _halmac_sdio_reg_read_32,
+	.SDIO_CMD53_READ_N = _halmac_sdio_reg_read_n,
+	.SDIO_CMD52_WRITE = _halmac_sdio_cmd52_write,
+	.SDIO_CMD53_WRITE_8 = _halmac_sdio_reg_write_8,
+	.SDIO_CMD53_WRITE_16 = _halmac_sdio_reg_write_16,
+	.SDIO_CMD53_WRITE_32 = _halmac_sdio_reg_write_32,
+	.SDIO_CMD52_CIA_READ = _halmac_sdio_read_cia,
+#endif /* CONFIG_SDIO_HCI */
+#if defined(CONFIG_USB_HCI) || defined(CONFIG_PCI_HCI)
+	.REG_READ_8 = _halmac_reg_read_8,
+	.REG_READ_16 = _halmac_reg_read_16,
+	.REG_READ_32 = _halmac_reg_read_32,
+	.REG_WRITE_8 = _halmac_reg_write_8,
+	.REG_WRITE_16 = _halmac_reg_write_16,
+	.REG_WRITE_32 = _halmac_reg_write_32,
+#endif /* CONFIG_USB_HCI || CONFIG_PCI_HCI */
+
+	/* Write data */
+#if 0
+	/* impletement in HAL-IC level */
+	.SEND_RSVD_PAGE = sdio_write_data_rsvd_page,
+	.SEND_H2C_PKT = sdio_write_data_h2c,
+#endif
+	/* Memory allocate */
+	.RTL_FREE = _halmac_mfree,
+	.RTL_MALLOC = _halmac_malloc,
+	.RTL_MEMCPY = _halmac_memcpy,
+	.RTL_MEMSET = _halmac_memset,
+
+	/* Sleep */
+	.RTL_DELAY_US = _halmac_udelay,
+
+	/* Process Synchronization */
+	.MUTEX_INIT = _halmac_mutex_init,
+	.MUTEX_DEINIT = _halmac_mutex_deinit,
+	.MUTEX_LOCK = _halmac_mutex_lock,
+	.MUTEX_UNLOCK = _halmac_mutex_unlock,
+
+	.MSG_PRINT = _halmac_msg_print,
+	.BUFF_PRINT = _halmac_buff_print,
+	.EVENT_INDICATION = _halmac_event_indication,
+};
+
+u8 rtw_halmac_read8(struct intf_hdl *pintfhdl, u32 addr)
+{
+	struct halmac_adapter *mac;
+	struct halmac_api *api;
+
+
+	/* WARNING: pintf_dev should not be null! */
+	mac = dvobj_to_halmac(pintfhdl->pintf_dev);
+	api = HALMAC_GET_API(mac);
+
+	return api->halmac_reg_read_8(mac, addr);
+}
+
+u16 rtw_halmac_read16(struct intf_hdl *pintfhdl, u32 addr)
+{
+	struct halmac_adapter *mac;
+	struct halmac_api *api;
+
+
+	/* WARNING: pintf_dev should not be null! */
+	mac = dvobj_to_halmac(pintfhdl->pintf_dev);
+	api = HALMAC_GET_API(mac);
+
+	return api->halmac_reg_read_16(mac, addr);
+}
+
+u32 rtw_halmac_read32(struct intf_hdl *pintfhdl, u32 addr)
+{
+	struct halmac_adapter *mac;
+	struct halmac_api *api;
+
+
+	/* WARNING: pintf_dev should not be null! */
+	mac = dvobj_to_halmac(pintfhdl->pintf_dev);
+	api = HALMAC_GET_API(mac);
+
+	return api->halmac_reg_read_32(mac, addr);
+}
+
+static void _read_register(struct dvobj_priv *d, u32 addr, u32 cnt, u8 *buf)
+{
+#if 1
+	struct _ADAPTER *a;
+	u32 i, n;
+	u16 val16;
+	u32 val32;
+
+
+	a = dvobj_get_primary_adapter(d);
+
+	i = addr & 0x3;
+	/* Handle address not start from 4 bytes alignment case */
+	if (i) {
+		val32 = cpu_to_le32(rtw_read32(a, addr & ~0x3));
+		n = 4 - i;
+		_rtw_memcpy(buf, ((u8 *)&val32) + i, n);
+		i = n;
+		cnt -= n;
+	}
+
+	while (cnt) {
+		if (cnt >= 4)
+			n = 4;
+		else if (cnt >= 2)
+			n = 2;
+		else
+			n = 1;
+		cnt -= n;
+
+		switch (n) {
+		case 1:
+			buf[i] = rtw_read8(a, addr+i);
+			i++;
+			break;
+		case 2:
+			val16 = cpu_to_le16(rtw_read16(a, addr+i));
+			_rtw_memcpy(&buf[i], &val16, 2);
+			i += 2;
+			break;
+		case 4:
+			val32 = cpu_to_le32(rtw_read32(a, addr+i));
+			_rtw_memcpy(&buf[i], &val32, 4);
+			i += 4;
+			break;
+		}
+	}
+#else
+	struct _ADAPTER *a;
+	u32 i;
+
+
+	a = dvobj_get_primary_adapter(d);
+	for (i = 0; i < cnt; i++)
+		buf[i] = rtw_read8(a, addr + i);
+#endif
+}
+
+#ifdef CONFIG_SDIO_HCI
+static int _sdio_read_local(struct dvobj_priv *d, u32 addr, u32 cnt, u8 *buf)
+{
+	struct halmac_adapter *mac;
+	struct halmac_api *api;
+	enum halmac_ret_status status;
+
+
+	if (buf == NULL)
+		return -1;
+
+	mac = dvobj_to_halmac(d);
+	api = HALMAC_GET_API(mac);
+
+	status = api->halmac_reg_sdio_cmd53_read_n(mac, addr, cnt, buf);
+	if (status != HALMAC_RET_SUCCESS) {
+		RTW_ERR("%s: addr=0x%08x cnt=%d err=%d\n",
+			__FUNCTION__, addr, cnt, status);
+		return -1;
+	}
+
+	return 0;
+}
+#endif /* CONFIG_SDIO_HCI */
+
+void rtw_halmac_read_mem(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *pmem)
+{
+	struct dvobj_priv *d;
+
+
+	if (pmem == NULL) {
+		RTW_ERR("pmem is NULL\n");
+		return;
+	}
+
+	d = pintfhdl->pintf_dev;
+
+#ifdef CONFIG_SDIO_HCI
+	if (addr & 0xFFFF0000) {
+		int err = 0;
+
+		err = _sdio_read_local(d, addr, cnt, pmem);
+		if (!err)
+			return;
+	}
+#endif /* CONFIG_SDIO_HCI */
+
+	_read_register(d, addr, cnt, pmem);
+}
+
+#ifdef CONFIG_SDIO_INDIRECT_ACCESS
+u8 rtw_halmac_iread8(struct intf_hdl *pintfhdl, u32 addr)
+{
+	struct halmac_adapter *mac;
+	struct halmac_api *api;
+
+	/* WARNING: pintf_dev should not be null! */
+	mac = dvobj_to_halmac(pintfhdl->pintf_dev);
+	api = HALMAC_GET_API(mac);
+
+	/*return api->halmac_reg_read_indirect_8(mac, addr);*/
+	return api->halmac_reg_read_8(mac, addr);
+}
+
+u16 rtw_halmac_iread16(struct intf_hdl *pintfhdl, u32 addr)
+{
+	struct halmac_adapter *mac;
+	struct halmac_api *api;
+	u16 val16 = 0;
+
+	/* WARNING: pintf_dev should not be null! */
+	mac = dvobj_to_halmac(pintfhdl->pintf_dev);
+	api = HALMAC_GET_API(mac);
+
+	/*return api->halmac_reg_read_indirect_16(mac, addr);*/
+	return api->halmac_reg_read_16(mac, addr);
+}
+
+u32 rtw_halmac_iread32(struct intf_hdl *pintfhdl, u32 addr)
+{
+	struct halmac_adapter *mac;
+	struct halmac_api *api;
+
+
+	/* WARNING: pintf_dev should not be null! */
+	mac = dvobj_to_halmac(pintfhdl->pintf_dev);
+	api = HALMAC_GET_API(mac);
+
+	return api->halmac_reg_read_indirect_32(mac, addr);
+}
+#endif /* CONFIG_SDIO_INDIRECT_ACCESS */
+
+int rtw_halmac_write8(struct intf_hdl *pintfhdl, u32 addr, u8 value)
+{
+	struct halmac_adapter *mac;
+	struct halmac_api *api;
+	enum halmac_ret_status status;
+
+
+	/* WARNING: pintf_dev should not be null! */
+	mac = dvobj_to_halmac(pintfhdl->pintf_dev);
+	api = HALMAC_GET_API(mac);
+
+	status = api->halmac_reg_write_8(mac, addr, value);
+
+	if (status == HALMAC_RET_SUCCESS)
+		return 0;
+
+	return -1;
+}
+
+int rtw_halmac_write16(struct intf_hdl *pintfhdl, u32 addr, u16 value)
+{
+	struct halmac_adapter *mac;
+	struct halmac_api *api;
+	enum halmac_ret_status status;
+
+
+	/* WARNING: pintf_dev should not be null! */
+	mac = dvobj_to_halmac(pintfhdl->pintf_dev);
+	api = HALMAC_GET_API(mac);
+
+	status = api->halmac_reg_write_16(mac, addr, value);
+
+	if (status == HALMAC_RET_SUCCESS)
+		return 0;
+
+	return -1;
+}
+
+int rtw_halmac_write32(struct intf_hdl *pintfhdl, u32 addr, u32 value)
+{
+	struct halmac_adapter *mac;
+	struct halmac_api *api;
+	enum halmac_ret_status status;
+
+
+	/* WARNING: pintf_dev should not be null! */
+	mac = dvobj_to_halmac(pintfhdl->pintf_dev);
+	api = HALMAC_GET_API(mac);
+
+	status = api->halmac_reg_write_32(mac, addr, value);
+
+	if (status == HALMAC_RET_SUCCESS)
+		return 0;
+
+	return -1;
+}
+
+static int init_write_rsvd_page_size(struct dvobj_priv *d)
+{
+	struct halmac_adapter *mac;
+	struct halmac_api *api;
+	u32 size = 0;
+	struct halmac_ofld_func_info ofld_info;
+	enum halmac_ret_status status;
+	int err = 0;
+
+
+#ifdef CONFIG_USB_HCI
+	/* for USB do not exceed MAX_CMDBUF_SZ */
+	size = 0x1000;
+#elif defined(CONFIG_PCI_HCI)
+	size = MAX_CMDBUF_SZ - TXDESC_OFFSET;
+#elif defined(CONFIG_SDIO_HCI)
+	size = 0x7000; /* 28KB */
+#endif
+
+	/* If size==0, use HALMAC default setting and don't call any function */
+	if (!size)
+		return 0;
+
+	err = rtw_halmac_set_max_dl_fw_size(d, size);
+	if (err) {
+		RTW_ERR("%s: Fail to set max download fw size!\n", __FUNCTION__);
+		return -1;
+	}
+
+	mac = dvobj_to_halmac(d);
+	api = HALMAC_GET_API(mac);
+
+	_rtw_memset(&ofld_info, 0, sizeof(ofld_info));
+	ofld_info.halmac_malloc_max_sz = 0xFFFFFFFF;
+	ofld_info.rsvd_pg_drv_buf_max_sz = size;
+	status = api->halmac_ofld_func_cfg(mac, &ofld_info);
+	if (status != HALMAC_RET_SUCCESS) {
+		RTW_ERR("%s: Fail to config offload parameters!\n", __FUNCTION__);
+		return -1;
+	}
+
+	return 0;
+}
+
+static int init_priv(struct halmacpriv *priv)
+{
+	struct halmac_indicator *indicator;
+	u32 count, size;
+
+
+	if (priv->indicator)
+		RTW_WARN("%s: HALMAC private data is not CLEAR!\n", __FUNCTION__);
+	count = HALMAC_FEATURE_ALL + 1;
+	size = sizeof(*indicator) * count;
+	indicator = (struct halmac_indicator *)rtw_zmalloc(size);
+	if (!indicator)
+		return -1;
+	priv->indicator = indicator;
+
+	return 0;
+}
+
+static void deinit_priv(struct halmacpriv *priv)
+{
+	struct halmac_indicator *indicator;
+
+
+	indicator = priv->indicator;
+	priv->indicator = NULL;
+	if (indicator) {
+		u32 count, size;
+
+		count = HALMAC_FEATURE_ALL + 1;
+#ifdef CONFIG_RTW_DEBUG
+		{
+			struct submit_ctx *sctx;
+			u32 i;
+
+			for (i = 0; i < count; i++) {
+				if (!indicator[i].sctx)
+					continue;
+
+				RTW_WARN("%s: %s id(%d) sctx still exist!!\n",
+					__FUNCTION__, RTW_HALMAC_FEATURE_NAME[i], i);
+				sctx = indicator[i].sctx;
+				indicator[i].sctx = NULL;
+				rtw_mfree((u8 *)sctx, sizeof(*sctx));
+			}
+		}
+#endif /* !CONFIG_RTW_DEBUG */
+		size = sizeof(*indicator) * count;
+		rtw_mfree((u8 *)indicator, size);
+	}
+}
+
+#ifdef CONFIG_SDIO_HCI
+static enum halmac_sdio_spec_ver _sdio_ver_drv2halmac(struct dvobj_priv *d)
+{
+	bool v3;
+	enum halmac_sdio_spec_ver ver;
+
+
+	v3 = rtw_is_sdio30(dvobj_get_primary_adapter(d));
+	if (v3)
+		ver = HALMAC_SDIO_SPEC_VER_3_00;
+	else
+		ver = HALMAC_SDIO_SPEC_VER_2_00;
+
+	return ver;
+}
+#endif /* CONFIG_SDIO_HCI */
+
+void rtw_halmac_get_version(char *str, u32 len)
+{
+	enum halmac_ret_status status;
+	struct halmac_ver ver;
+
+
+	status = halmac_get_version(&ver);
+	if (status != HALMAC_RET_SUCCESS)
+		return;
+
+	rtw_sprintf(str, len, "V%d_%02d_%02d",
+		    ver.major_ver, ver.prototype_ver, ver.minor_ver);
+}
+
+int rtw_halmac_init_adapter(struct dvobj_priv *d, struct halmac_platform_api *pf_api)
+{
+	struct halmac_adapter *halmac;
+	struct halmac_api *api;
+	enum halmac_interface intf;
+	enum halmac_ret_status status;
+	int err = 0;
+#ifdef CONFIG_SDIO_HCI
+	struct halmac_sdio_hw_info info;
+#endif /* CONFIG_SDIO_HCI */
+
+
+	halmac = dvobj_to_halmac(d);
+	if (halmac) {
+		RTW_WARN("%s: initialize already completed!\n", __FUNCTION__);
+		goto error;
+	}
+
+	err = init_priv(&d->hmpriv);
+	if (err)
+		goto error;
+
+#ifdef CONFIG_SDIO_HCI
+	intf = HALMAC_INTERFACE_SDIO;
+#elif defined(CONFIG_USB_HCI)
+	intf = HALMAC_INTERFACE_USB;
+#elif defined(CONFIG_PCI_HCI)
+	intf = HALMAC_INTERFACE_PCIE;
+#else
+#warning "INTERFACE(CONFIG_XXX_HCI) not be defined!!"
+	intf = HALMAC_INTERFACE_UNDEFINE;
+#endif
+	status = halmac_init_adapter(d, pf_api, intf, &halmac, &api);
+	if (HALMAC_RET_SUCCESS != status) {
+		RTW_ERR("%s: halmac_init_adapter fail!(status=%d)\n", __FUNCTION__, status);
+		err = -1;
+		if (halmac)
+			goto deinit;
+		goto free;
+	}
+
+	dvobj_set_halmac(d, halmac);
+
+	status = api->halmac_interface_integration_tuning(halmac);
+	if (status != HALMAC_RET_SUCCESS) {
+		RTW_ERR("%s: halmac_interface_integration_tuning fail!(status=%d)\n", __FUNCTION__, status);
+		err = -1;
+		goto deinit;
+	}
+
+	status = api->halmac_phy_cfg(halmac, HALMAC_INTF_PHY_PLATFORM_ALL);
+	if (status != HALMAC_RET_SUCCESS) {
+		RTW_ERR("%s: halmac_phy_cfg fail!(status=%d)\n", __FUNCTION__, status);
+		err = -1;
+		goto deinit;
+	}
+
+	init_write_rsvd_page_size(d);
+
+#ifdef CONFIG_SDIO_HCI
+	_rtw_memset(&info, 0, sizeof(info));
+	info.spec_ver = _sdio_ver_drv2halmac(d);
+	/* Convert clock speed unit to MHz from Hz */
+	info.clock_speed = RTW_DIV_ROUND_UP(rtw_sdio_get_clock(d), 1000000);
+	info.block_size = rtw_sdio_get_block_size(d);
+	RTW_DBG("%s: SDIO ver=%u clock=%uMHz blk_size=%u bytes\n",
+		__FUNCTION__, info.spec_ver+2, info.clock_speed,
+		info.block_size);
+	status = api->halmac_sdio_hw_info(halmac, &info);
+	if (status != HALMAC_RET_SUCCESS) {
+		RTW_ERR("%s: halmac_sdio_hw_info fail!(status=%d)\n",
+			__FUNCTION__, status);
+		err = -1;
+		goto deinit;
+	}
+#endif /* CONFIG_SDIO_HCI */
+
+	return 0;
+
+deinit:
+	status = halmac_deinit_adapter(halmac);
+	dvobj_set_halmac(d, NULL);
+	if (status != HALMAC_RET_SUCCESS)
+		RTW_ERR("%s: halmac_deinit_adapter fail!(status=%d)\n",
+			__FUNCTION__, status);
+
+free:
+	deinit_priv(&d->hmpriv);
+
+error:
+	return err;
+}
+
+int rtw_halmac_deinit_adapter(struct dvobj_priv *d)
+{
+	struct halmac_adapter *halmac;
+	enum halmac_ret_status status;
+	int err = 0;
+
+
+	halmac = dvobj_to_halmac(d);
+	if (halmac) {
+		status = halmac_deinit_adapter(halmac);
+		dvobj_set_halmac(d, NULL);
+		if (status != HALMAC_RET_SUCCESS)
+			err = -1;
+	}
+
+	deinit_priv(&d->hmpriv);
+
+	return err;
+}
+
+static inline enum halmac_portid _hw_port_drv2halmac(enum _hw_port hwport)
+{
+	enum halmac_portid port = HALMAC_PORTID_NUM;
+
+
+	switch (hwport) {
+	case HW_PORT0:
+		port = HALMAC_PORTID0;
+		break;
+	case HW_PORT1:
+		port = HALMAC_PORTID1;
+		break;
+	case HW_PORT2:
+		port = HALMAC_PORTID2;
+		break;
+	case HW_PORT3:
+		port = HALMAC_PORTID3;
+		break;
+	case HW_PORT4:
+		port = HALMAC_PORTID4;
+		break;
+	default:
+		break;
+	}
+
+	return port;
+}
+
+static enum halmac_network_type_select _network_type_drv2halmac(u8 type)
+{
+	enum halmac_network_type_select network = HALMAC_NETWORK_UNDEFINE;
+
+
+	switch (type) {
+	case _HW_STATE_NOLINK_:
+	case _HW_STATE_MONITOR_:
+		network = HALMAC_NETWORK_NO_LINK;
+		break;
+
+	case _HW_STATE_ADHOC_:
+		network = HALMAC_NETWORK_ADHOC;
+		break;
+
+	case _HW_STATE_STATION_:
+		network = HALMAC_NETWORK_INFRASTRUCTURE;
+		break;
+
+	case _HW_STATE_AP_:
+		network = HALMAC_NETWORK_AP;
+		break;
+	}
+
+	return network;
+}
+
+static u8 _network_type_halmac2drv(enum halmac_network_type_select network)
+{
+	u8 type = _HW_STATE_NOLINK_;
+
+
+	switch (network) {
+	case HALMAC_NETWORK_NO_LINK:
+	case HALMAC_NETWORK_UNDEFINE:
+		type = _HW_STATE_NOLINK_;
+		break;
+
+	case HALMAC_NETWORK_ADHOC:
+		type = _HW_STATE_ADHOC_;
+		break;
+
+	case HALMAC_NETWORK_INFRASTRUCTURE:
+		type = _HW_STATE_STATION_;
+		break;
+
+	case HALMAC_NETWORK_AP:
+		type = _HW_STATE_AP_;
+		break;
+	}
+
+	return type;
+}
+
+static void _beacon_ctrl_halmac2drv(struct halmac_bcn_ctrl *ctrl,
+				struct rtw_halmac_bcn_ctrl *drv_ctrl)
+{
+	drv_ctrl->rx_bssid_fit = ctrl->dis_rx_bssid_fit ? 0 : 1;
+	drv_ctrl->txbcn_rpt = ctrl->en_txbcn_rpt ? 1 : 0;
+	drv_ctrl->tsf_update = ctrl->dis_tsf_udt ? 0 : 1;
+	drv_ctrl->enable_bcn = ctrl->en_bcn ? 1 : 0;
+	drv_ctrl->rxbcn_rpt = ctrl->en_rxbcn_rpt ? 1 : 0;
+	drv_ctrl->p2p_ctwin = ctrl->en_p2p_ctwin ? 1 : 0;
+	drv_ctrl->p2p_bcn_area = ctrl->en_p2p_bcn_area ? 1 : 0;
+}
+
+static void _beacon_ctrl_drv2halmac(struct rtw_halmac_bcn_ctrl *drv_ctrl,
+				struct halmac_bcn_ctrl *ctrl)
+{
+	ctrl->dis_rx_bssid_fit = drv_ctrl->rx_bssid_fit ? 0 : 1;
+	ctrl->en_txbcn_rpt = drv_ctrl->txbcn_rpt ? 1 : 0;
+	ctrl->dis_tsf_udt = drv_ctrl->tsf_update ? 0 : 1;
+	ctrl->en_bcn = drv_ctrl->enable_bcn ? 1 : 0;
+	ctrl->en_rxbcn_rpt = drv_ctrl->rxbcn_rpt ? 1 : 0;
+	ctrl->en_p2p_ctwin = drv_ctrl->p2p_ctwin ? 1 : 0;
+	ctrl->en_p2p_bcn_area = drv_ctrl->p2p_bcn_area ? 1 : 0;
+}
+
+int rtw_halmac_get_hw_value(struct dvobj_priv *d, enum halmac_hw_id hw_id, void *pvalue)
+{
+	struct halmac_adapter *mac;
+	struct halmac_api *api;
+	enum halmac_ret_status status;
+
+
+	mac = dvobj_to_halmac(d);
+	api = HALMAC_GET_API(mac);
+
+	status = api->halmac_get_hw_value(mac, hw_id, pvalue);
+	if (HALMAC_RET_SUCCESS != status)
+		return -1;
+
+	return 0;
+}
+
+/**
+ * rtw_halmac_get_tx_fifo_size() - TX FIFO size
+ * @d:		struct dvobj_priv*
+ * @size:	TX FIFO size, unit is byte.
+ *
+ * Get TX FIFO size(byte) from HALMAC.
+ *
+ * Rteurn 0 for OK, otherwise fail.
+ */
+int rtw_halmac_get_tx_fifo_size(struct dvobj_priv *d, u32 *size)
+{
+	struct halmac_adapter *halmac;
+	struct halmac_api *api;
+	enum halmac_ret_status status;
+	u32 val = 0;
+
+
+	halmac = dvobj_to_halmac(d);
+	api = HALMAC_GET_API(halmac);
+
+	status = api->halmac_get_hw_value(halmac, HALMAC_HW_TXFIFO_SIZE, &val);
+	if (status != HALMAC_RET_SUCCESS)
+		return -1;
+
+	*size = val;
+
+	return 0;
+}
+
+/**
+ * rtw_halmac_get_rx_fifo_size() - RX FIFO size
+ * @d:		struct dvobj_priv*
+ * @size:	RX FIFO size, unit is byte
+ *
+ * Get RX FIFO size(byte) from HALMAC.
+ *
+ * Rteurn 0 for OK, otherwise fail.
+ */
+int rtw_halmac_get_rx_fifo_size(struct dvobj_priv *d, u32 *size)
+{
+	struct halmac_adapter *halmac;
+	struct halmac_api *api;
+	enum halmac_ret_status status;
+	u32 val = 0;
+
+
+	halmac = dvobj_to_halmac(d);
+	api = HALMAC_GET_API(halmac);
+
+	status = api->halmac_get_hw_value(halmac, HALMAC_HW_RXFIFO_SIZE, &val);
+	if (status != HALMAC_RET_SUCCESS)
+		return -1;
+
+	*size = val;
+
+	return 0;
+}
+
+/**
+ * rtw_halmac_get_rsvd_drv_pg_bndy() - Reserve page boundary of driver
+ * @d:		struct dvobj_priv*
+ * @size:	Page size, unit is byte
+ *
+ * Get reserve page boundary of driver from HALMAC.
+ *
+ * Rteurn 0 for OK, otherwise fail.
+ */
+int rtw_halmac_get_rsvd_drv_pg_bndy(struct dvobj_priv *d, u16 *bndy)
+{
+	struct halmac_adapter *halmac;
+	struct halmac_api *api;
+	enum halmac_ret_status status;
+	u16 val = 0;
+
+
+	halmac = dvobj_to_halmac(d);
+	api = HALMAC_GET_API(halmac);
+
+	status = api->halmac_get_hw_value(halmac, HALMAC_HW_RSVD_PG_BNDY, &val);
+	if (status != HALMAC_RET_SUCCESS)
+		return -1;
+
+	*bndy = val;
+
+	return 0;
+}
+
+/**
+ * rtw_halmac_get_page_size() - Page size
+ * @d:		struct dvobj_priv*
+ * @size:	Page size, unit is byte
+ *
+ * Get TX/RX page size(byte) from HALMAC.
+ *
+ * Rteurn 0 for OK, otherwise fail.
+ */
+int rtw_halmac_get_page_size(struct dvobj_priv *d, u32 *size)
+{
+	struct halmac_adapter *halmac;
+	struct halmac_api *api;
+	enum halmac_ret_status status;
+	u32 val = 0;
+
+
+	halmac = dvobj_to_halmac(d);
+	api = HALMAC_GET_API(halmac);
+
+	status = api->halmac_get_hw_value(halmac, HALMAC_HW_PAGE_SIZE, &val);
+	if (status != HALMAC_RET_SUCCESS)
+		return -1;
+
+	*size = val;
+
+	return 0;
+}
+
+/**
+ * rtw_halmac_get_tx_agg_align_size() - TX aggregation align size
+ * @d:		struct dvobj_priv*
+ * @size:	TX aggregation align size, unit is byte
+ *
+ * Get TX aggregation align size(byte) from HALMAC.
+ *
+ * Rteurn 0 for OK, otherwise fail.
+ */
+int rtw_halmac_get_tx_agg_align_size(struct dvobj_priv *d, u16 *size)
+{
+	struct halmac_adapter *halmac;
+	struct halmac_api *api;
+	enum halmac_ret_status status;
+	u16 val = 0;
+
+
+	halmac = dvobj_to_halmac(d);
+	api = HALMAC_GET_API(halmac);
+
+	status = api->halmac_get_hw_value(halmac, HALMAC_HW_TX_AGG_ALIGN_SIZE, &val);
+	if (status != HALMAC_RET_SUCCESS)
+		return -1;
+
+	*size = val;
+
+	return 0;
+}
+
+/**
+ * rtw_halmac_get_rx_agg_align_size() - RX aggregation align size
+ * @d:		struct dvobj_priv*
+ * @size:	RX aggregation align size, unit is byte
+ *
+ * Get RX aggregation align size(byte) from HALMAC.
+ *
+ * Rteurn 0 for OK, otherwise fail.
+ */
+int rtw_halmac_get_rx_agg_align_size(struct dvobj_priv *d, u8 *size)
+{
+	struct halmac_adapter *halmac;
+	struct halmac_api *api;
+	enum halmac_ret_status status;
+	u8 val = 0;
+
+
+	halmac = dvobj_to_halmac(d);
+	api = HALMAC_GET_API(halmac);
+
+	status = api->halmac_get_hw_value(halmac, HALMAC_HW_RX_AGG_ALIGN_SIZE, &val);
+	if (status != HALMAC_RET_SUCCESS)
+		return -1;
+
+	*size = val;
+
+	return 0;
+}
+
+/*
+ * Description:
+ *	Get RX driver info size. RX driver info is a small memory space between
+ *	scriptor and RX payload.
+ *
+ *	+-------------------------+
+ *	| RX descriptor           |
+ *	| usually 24 bytes        |
+ *	+-------------------------+
+ *	| RX driver info          |
+ *	| depends on driver cfg   |
+ *	+-------------------------+
+ *	| RX paylad               |
+ *	|                         |
+ *	+-------------------------+
+ *
+ * Parameter:
+ *	d	pointer to struct dvobj_priv of driver
+ *	sz	rx driver info size in bytes.
+ *
+ * Rteurn:
+ *	0	Success
+ *	other	Fail
+ */
+int rtw_halmac_get_rx_drv_info_sz(struct dvobj_priv *d, u8 *sz)
+{
+	enum halmac_ret_status status;
+	struct halmac_adapter *halmac = dvobj_to_halmac(d);
+	struct halmac_api *api = HALMAC_GET_API(halmac);
+	u8 dw = 0;
+
+	status = api->halmac_get_hw_value(halmac, HALMAC_HW_DRV_INFO_SIZE, &dw);
+	if (status != HALMAC_RET_SUCCESS)
+		return -1;
+
+	*sz = dw * 8;
+	return 0;
+}
+
+/**
+ * rtw_halmac_get_tx_desc_size() - TX descriptor size
+ * @d:		struct dvobj_priv*
+ * @size:	TX descriptor size, unit is byte.
+ *
+ * Get TX descriptor size(byte) from HALMAC.
+ *
+ * Rteurn 0 for OK, otherwise fail.
+ */
+int rtw_halmac_get_tx_desc_size(struct dvobj_priv *d, u32 *size)
+{
+	struct halmac_adapter *halmac;
+	struct halmac_api *api;
+	enum halmac_ret_status status;
+	u32 val = 0;
+
+
+	halmac = dvobj_to_halmac(d);
+	api = HALMAC_GET_API(halmac);
+
+	status = api->halmac_get_hw_value(halmac, HALMAC_HW_TX_DESC_SIZE, &val);
+	if (status != HALMAC_RET_SUCCESS)
+		return -1;
+
+	*size = val;
+
+	return 0;
+}
+
+/**
+ * rtw_halmac_get_rx_desc_size() - RX descriptor size
+ * @d:		struct dvobj_priv*
+ * @size:	RX descriptor size, unit is byte.
+ *
+ * Get RX descriptor size(byte) from HALMAC.
+ *
+ * Rteurn 0 for OK, otherwise fail.
+ */
+int rtw_halmac_get_rx_desc_size(struct dvobj_priv *d, u32 *size)
+{
+	struct halmac_adapter *halmac;
+	struct halmac_api *api;
+	enum halmac_ret_status status;
+	u32 val = 0;
+
+
+	halmac = dvobj_to_halmac(d);
+	api = HALMAC_GET_API(halmac);
+
+	status = api->halmac_get_hw_value(halmac, HALMAC_HW_RX_DESC_SIZE, &val);
+	if (status != HALMAC_RET_SUCCESS)
+		return -1;
+
+	*size = val;
+
+	return 0;
+}
+
+
+/**
+ * rtw_halmac_get_fw_max_size() - Firmware MAX size
+ * @d:		struct dvobj_priv*
+ * @size:	MAX Firmware size, unit is byte.
+ *
+ * Get Firmware MAX size(byte) from HALMAC.
+ *
+ * Rteurn 0 for OK, otherwise fail.
+ */
+static int rtw_halmac_get_fw_max_size(struct dvobj_priv *d, u32 *size)
+{
+	struct halmac_adapter *halmac;
+	struct halmac_api *api;
+	enum halmac_ret_status status;
+	u32 val = 0;
+
+
+	halmac = dvobj_to_halmac(d);
+	api = HALMAC_GET_API(halmac);
+
+	status = api->halmac_get_hw_value(halmac, HALMAC_HW_FW_MAX_SIZE, &val);
+	if (status != HALMAC_RET_SUCCESS)
+		return -1;
+
+	*size = val;
+
+	return 0;
+}
+
+/**
+ * rtw_halmac_get_ori_h2c_size() - Original H2C MAX size
+ * @d:		struct dvobj_priv*
+ * @size:	H2C MAX size, unit is byte.
+ *
+ * Get original H2C MAX size(byte) from HALMAC.
+ *
+ * Rteurn 0 for OK, otherwise fail.
+ */
+int rtw_halmac_get_ori_h2c_size(struct dvobj_priv *d, u32 *size)
+{
+	struct halmac_adapter *halmac;
+	struct halmac_api *api;
+	enum halmac_ret_status status;
+	u32 val = 0;
+
+
+	halmac = dvobj_to_halmac(d);
+	api = HALMAC_GET_API(halmac);
+
+	status = api->halmac_get_hw_value(halmac, HALMAC_HW_ORI_H2C_SIZE, &val);
+	if (status != HALMAC_RET_SUCCESS)
+		return -1;
+
+	*size = val;
+
+	return 0;
+}
+
+int rtw_halmac_get_oqt_size(struct dvobj_priv *d, u8 *size)
+{
+	enum halmac_ret_status status;
+	struct halmac_adapter *halmac;
+	struct halmac_api *api;
+	u8 val;
+
+
+	if (!size)
+		return -1;
+
+	halmac = dvobj_to_halmac(d);
+	api = HALMAC_GET_API(halmac);
+
+	status = api->halmac_get_hw_value(halmac, HALMAC_HW_AC_OQT_SIZE, &val);
+	if (status != HALMAC_RET_SUCCESS)
+		return -1;
+
+	*size = val;
+	return 0;
+}
+
+int rtw_halmac_get_ac_queue_number(struct dvobj_priv *d, u8 *num)
+{
+	enum halmac_ret_status status;
+	struct halmac_adapter *halmac;
+	struct halmac_api *api;
+	u8 val;
+
+
+	if (!num)
+		return -1;
+
+	halmac = dvobj_to_halmac(d);
+	api = HALMAC_GET_API(halmac);
+
+	status = api->halmac_get_hw_value(halmac, HALMAC_HW_AC_QUEUE_NUM, &val);
+	if (status != HALMAC_RET_SUCCESS)
+		return -1;
+
+	*num = val;
+	return 0;
+}
+
+/**
+ * rtw_halmac_get_mac_address() - Get MAC address of specific port
+ * @d:		struct dvobj_priv*
+ * @hwport:	port
+ * @addr:	buffer for storing MAC address
+ *
+ * Get MAC address of specific port from HALMAC.
+ *
+ * Rteurn 0 for OK, otherwise fail.
+ */
+int rtw_halmac_get_mac_address(struct dvobj_priv *d, enum _hw_port hwport, u8 *addr)
+{
+	struct halmac_adapter *halmac;
+	struct halmac_api *api;
+	enum halmac_portid port;
+	union halmac_wlan_addr hwa;
+	enum halmac_ret_status status;
+	int err = -1;
+
+
+	if (!addr)
+		goto out;
+
+	halmac = dvobj_to_halmac(d);
+	api = HALMAC_GET_API(halmac);
+	port = _hw_port_drv2halmac(hwport);
+	_rtw_memset(&hwa, 0, sizeof(hwa));
+
+	status = api->halmac_get_mac_addr(halmac, port, &hwa);
+	if (status != HALMAC_RET_SUCCESS)
+		goto out;
+
+	_rtw_memcpy(addr, hwa.addr, 6);
+
+	err = 0;
+out:
+	return err;
+}
+
+/**
+ * rtw_halmac_get_network_type() - Get network type of specific port
+ * @d:		struct dvobj_priv*
+ * @hwport:	port
+ * @type:	buffer to put network type (_HW_STATE_*)
+ *
+ * Get network type of specific port from HALMAC.
+ *
+ * Rteurn 0 for OK, otherwise fail.
+ */
+int rtw_halmac_get_network_type(struct dvobj_priv *d, enum _hw_port hwport, u8 *type)
+{
+#if 0
+	struct halmac_adapter *halmac;
+	struct halmac_api *api;
+	enum halmac_portid port;
+	enum halmac_network_type_select network;
+	enum halmac_ret_status status;
+	int err = -1;
+
+
+	halmac = dvobj_to_halmac(d);
+	api = HALMAC_GET_API(halmac);
+	port = _hw_port_drv2halmac(hwport);
+	network = HALMAC_NETWORK_UNDEFINE;
+
+	status = api->halmac_get_net_type(halmac, port, &network);
+	if (status != HALMAC_RET_SUCCESS)
+		goto out;
+
+	*type = _network_type_halmac2drv(network);
+
+	err = 0;
+out:
+	return err;
+#else
+	struct _ADAPTER *a;
+	enum halmac_portid port;
+	enum halmac_network_type_select network;
+	u32 val;
+	int err = -1;
+
+
+	a = dvobj_get_primary_adapter(d);
+	port = _hw_port_drv2halmac(hwport);
+	network = HALMAC_NETWORK_UNDEFINE;
+
+	switch (port) {
+	case HALMAC_PORTID0:
+		val = rtw_read32(a, REG_CR);
+		network = BIT_GET_NETYPE0(val);
+		break;
+
+	case HALMAC_PORTID1:
+		val = rtw_read32(a, REG_CR);
+		network = BIT_GET_NETYPE1(val);
+		break;
+
+	case HALMAC_PORTID2:
+		val = rtw_read32(a, REG_CR_EXT);
+		network = BIT_GET_NETYPE2(val);
+		break;
+
+	case HALMAC_PORTID3:
+		val = rtw_read32(a, REG_CR_EXT);
+		network = BIT_GET_NETYPE3(val);
+		break;
+
+	case HALMAC_PORTID4:
+		val = rtw_read32(a, REG_CR_EXT);
+		network = BIT_GET_NETYPE4(val);
+		break;
+
+	default:
+		goto out;
+	}
+
+	*type = _network_type_halmac2drv(network);
+
+	err = 0;
+out:
+	return err;
+#endif
+}
+
+/**
+ * rtw_halmac_get_bcn_ctrl() - Get beacon control setting of specific port
+ * @d:		struct dvobj_priv*
+ * @hwport:	port
+ * @bcn_ctrl:	setting of beacon control
+ *
+ * Get beacon control setting of specific port from HALMAC.
+ *
+ * Rteurn 0 for OK, otherwise fail.
+ */
+int rtw_halmac_get_bcn_ctrl(struct dvobj_priv *d, enum _hw_port hwport,
+			struct rtw_halmac_bcn_ctrl *bcn_ctrl)
+{
+	struct halmac_adapter *halmac;
+	struct halmac_api *api;
+	enum halmac_portid port;
+	struct halmac_bcn_ctrl ctrl;
+	enum halmac_ret_status status;
+	int err = -1;
+
+
+	halmac = dvobj_to_halmac(d);
+	api = HALMAC_GET_API(halmac);
+	port = _hw_port_drv2halmac(hwport);
+	_rtw_memset(&ctrl, 0, sizeof(ctrl));
+
+	status = api->halmac_rw_bcn_ctrl(halmac, port, 0, &ctrl);
+	if (status != HALMAC_RET_SUCCESS)
+		goto out;
+	_beacon_ctrl_halmac2drv(&ctrl, bcn_ctrl);
+
+	err = 0;
+out:
+	return err;
+}
+
+/*
+ * Note:
+ *	When this function return, the register REG_RCR may be changed.
+ */
+int rtw_halmac_config_rx_info(struct dvobj_priv *d, enum halmac_drv_info info)
+{
+	struct halmac_adapter *halmac;
+	struct halmac_api *api;
+	enum halmac_ret_status status;
+	int err = -1;
+
+
+	halmac = dvobj_to_halmac(d);
+	api = HALMAC_GET_API(halmac);
+
+	status = api->halmac_cfg_drv_info(halmac, info);
+	if (status != HALMAC_RET_SUCCESS)
+		goto out;
+
+	err = 0;
+out:
+	return err;
+}
+
+/**
+ * rtw_halmac_set_max_dl_fw_size() - Set the MAX download firmware size
+ * @d:		struct dvobj_priv*
+ * @size:	the max download firmware size in one I/O
+ *
+ * Set the max download firmware size in one I/O.
+ * Please also consider the max size of the callback function "SEND_RSVD_PAGE"
+ * could accept, because download firmware would call "SEND_RSVD_PAGE" to send
+ * firmware to IC.
+ *
+ * If the value of "size" is not even, it would be rounded down to nearest
+ * even, and 0 and 1 are both invalid value.
+ *
+ * Return 0 for setting OK, otherwise fail.
+ */
+int rtw_halmac_set_max_dl_fw_size(struct dvobj_priv *d, u32 size)
+{
+	struct halmac_adapter *mac;
+	struct halmac_api *api;
+	enum halmac_ret_status status;
+
+
+	if (!size || (size == 1))
+		return -1;
+
+	mac = dvobj_to_halmac(d);
+	if (!mac) {
+		RTW_ERR("%s: HALMAC is not ready!!\n", __FUNCTION__);
+		return -1;
+	}
+	api = HALMAC_GET_API(mac);
+
+	size &= ~1; /* round down to even */
+	status = api->halmac_cfg_max_dl_size(mac, size);
+	if (status != HALMAC_RET_SUCCESS) {
+		RTW_WARN("%s: Fail to cfg_max_dl_size(%d), err=%d!!\n",
+			 __FUNCTION__, size, status);
+		return -1;
+	}
+
+	return 0;
+}
+
+/**
+ * rtw_halmac_set_mac_address() - Set mac address of specific port
+ * @d:		struct dvobj_priv*
+ * @hwport:	port
+ * @addr:	mac address
+ *
+ * Set self mac address of specific port to HALMAC.
+ *
+ * Rteurn 0 for OK, otherwise fail.
+ */
+int rtw_halmac_set_mac_address(struct dvobj_priv *d, enum _hw_port hwport, u8 *addr)
+{
+	struct halmac_adapter *halmac;
+	struct halmac_api *api;
+	enum halmac_portid port;
+	union halmac_wlan_addr hwa;
+	enum halmac_ret_status status;
+	int err = -1;
+
+
+	halmac = dvobj_to_halmac(d);
+	api = HALMAC_GET_API(halmac);
+
+	port = _hw_port_drv2halmac(hwport);
+	_rtw_memset(&hwa, 0, sizeof(hwa));
+	_rtw_memcpy(hwa.addr, addr, 6);
+
+	status = api->halmac_cfg_mac_addr(halmac, port, &hwa);
+	if (status != HALMAC_RET_SUCCESS)
+		goto out;
+
+	err = 0;
+out:
+	return err;
+}
+
+/**
+ * rtw_halmac_set_bssid() - Set BSSID of specific port
+ * @d:		struct dvobj_priv*
+ * @hwport:	port
+ * @addr:	BSSID, mac address of AP
+ *
+ * Set BSSID of specific port to HALMAC.
+ *
+ * Rteurn 0 for OK, otherwise fail.
+ */
+int rtw_halmac_set_bssid(struct dvobj_priv *d, enum _hw_port hwport, u8 *addr)
+{
+	struct halmac_adapter *halmac;
+	struct halmac_api *api;
+	enum halmac_portid port;
+	union halmac_wlan_addr hwa;
+	enum halmac_ret_status status;
+	int err = -1;
+
+
+	halmac = dvobj_to_halmac(d);
+	api = HALMAC_GET_API(halmac);
+	port = _hw_port_drv2halmac(hwport);
+
+	_rtw_memset(&hwa, 0, sizeof(hwa));
+	_rtw_memcpy(hwa.addr, addr, 6);
+	status = api->halmac_cfg_bssid(halmac, port, &hwa);
+	if (status != HALMAC_RET_SUCCESS)
+		goto out;
+
+	err = 0;
+out:
+	return err;
+}
+
+/**
+ * rtw_halmac_set_tx_address() - Set transmitter address of specific port
+ * @d:		struct dvobj_priv*
+ * @hwport:	port
+ * @addr:	transmitter address
+ *
+ * Set transmitter address of specific port to HALMAC.
+ *
+ * Rteurn 0 for OK, otherwise fail.
+ */
+int rtw_halmac_set_tx_address(struct dvobj_priv *d, enum _hw_port hwport, u8 *addr)
+{
+	struct halmac_adapter *halmac;
+	struct halmac_api *api;
+	enum halmac_portid port;
+	union halmac_wlan_addr hwa;
+	enum halmac_ret_status status;
+	int err = -1;
+
+
+	halmac = dvobj_to_halmac(d);
+	api = HALMAC_GET_API(halmac);
+	port = _hw_port_drv2halmac(hwport);
+	_rtw_memset(&hwa, 0, sizeof(hwa));
+	_rtw_memcpy(hwa.addr, addr, 6);
+
+	status = api->halmac_cfg_transmitter_addr(halmac, port, &hwa);
+	if (status != HALMAC_RET_SUCCESS)
+		goto out;
+
+	err = 0;
+out:
+	return err;
+}
+
+/**
+ * rtw_halmac_set_network_type() - Set network type of specific port
+ * @d:		struct dvobj_priv*
+ * @hwport:	port
+ * @type:	network type (_HW_STATE_*)
+ *
+ * Set network type of specific port to HALMAC.
+ *
+ * Rteurn 0 for OK, otherwise fail.
+ */
+int rtw_halmac_set_network_type(struct dvobj_priv *d, enum _hw_port hwport, u8 type)
+{
+	struct halmac_adapter *halmac;
+	struct halmac_api *api;
+	enum halmac_portid port;
+	enum halmac_network_type_select network;
+	enum halmac_ret_status status;
+	int err = -1;
+
+
+	halmac = dvobj_to_halmac(d);
+	api = HALMAC_GET_API(halmac);
+	port = _hw_port_drv2halmac(hwport);
+	network = _network_type_drv2halmac(type);
+
+	status = api->halmac_cfg_net_type(halmac, port, network);
+	if (status != HALMAC_RET_SUCCESS)
+		goto out;
+
+	err = 0;
+out:
+	return err;
+}
+
+/**
+ * rtw_halmac_reset_tsf() - Reset TSF timer of specific port
+ * @d:		struct dvobj_priv*
+ * @hwport:	port
+ *
+ * Notice HALMAC to reset timing synchronization function(TSF) timer of
+ * specific port.
+ *
+ * Rteurn 0 for OK, otherwise fail.
+ */
+int rtw_halmac_reset_tsf(struct dvobj_priv *d, enum _hw_port hwport)
+{
+	struct halmac_adapter *halmac;
+	struct halmac_api *api;
+	enum halmac_portid port;
+	enum halmac_ret_status status;
+	int err = -1;
+
+
+	halmac = dvobj_to_halmac(d);
+	api = HALMAC_GET_API(halmac);
+	port = _hw_port_drv2halmac(hwport);
+
+	status = api->halmac_cfg_tsf_rst(halmac, port);
+	if (status != HALMAC_RET_SUCCESS)
+		goto out;
+
+	err = 0;
+out:
+	return err;
+}
+
+/**
+ * rtw_halmac_set_bcn_interval() - Set beacon interval of each port
+ * @d:		struct dvobj_priv*
+ * @hwport:	port
+ * @space:	beacon interval, unit is ms
+ *
+ * Set beacon interval of specific port to HALMAC.
+ *
+ * Rteurn 0 for OK, otherwise fail.
+ */
+int rtw_halmac_set_bcn_interval(struct dvobj_priv *d, enum _hw_port hwport,
+				u32 interval)
+{
+	struct halmac_adapter *halmac;
+	struct halmac_api *api;
+	enum halmac_portid port;
+	enum halmac_ret_status status;
+	int err = -1;
+
+
+	halmac = dvobj_to_halmac(d);
+	api = HALMAC_GET_API(halmac);
+	port = _hw_port_drv2halmac(hwport);
+
+	status = api->halmac_cfg_bcn_space(halmac, port, interval);
+	if (status != HALMAC_RET_SUCCESS)
+		goto out;
+
+	err = 0;
+out:
+	return err;
+}
+
+/**
+ * rtw_halmac_set_bcn_ctrl() - Set beacon control setting of each port
+ * @d:		struct dvobj_priv*
+ * @hwport:	port
+ * @bcn_ctrl:	setting of beacon control
+ *
+ * Set beacon control setting of specific port to HALMAC.
+ *
+ * Rteurn 0 for OK, otherwise fail.
+ */
+int rtw_halmac_set_bcn_ctrl(struct dvobj_priv *d, enum _hw_port hwport,
+			struct rtw_halmac_bcn_ctrl *bcn_ctrl)
+{
+	struct halmac_adapter *halmac;
+	struct halmac_api *api;
+	enum halmac_portid port;
+	struct halmac_bcn_ctrl ctrl;
+	enum halmac_ret_status status;
+	int err = -1;
+
+
+	halmac = dvobj_to_halmac(d);
+	api = HALMAC_GET_API(halmac);
+	port = _hw_port_drv2halmac(hwport);
+	_rtw_memset(&ctrl, 0, sizeof(ctrl));
+	_beacon_ctrl_drv2halmac(bcn_ctrl, &ctrl);
+
+	status = api->halmac_rw_bcn_ctrl(halmac, port, 1, &ctrl);
+	if (status != HALMAC_RET_SUCCESS)
+		goto out;
+
+	err = 0;
+out:
+	return err;
+}
+
+/**
+ * rtw_halmac_set_aid() - Set association identifier(AID) of specific port
+ * @d:		struct dvobj_priv*
+ * @hwport:	port
+ * @aid:	Association identifier
+ *
+ * Set association identifier(AID) of specific port to HALMAC.
+ *
+ * Rteurn 0 for OK, otherwise fail.
+ */
+int rtw_halmac_set_aid(struct dvobj_priv *d, enum _hw_port hwport, u16 aid)
+{
+	struct halmac_adapter *halmac;
+	struct halmac_api *api;
+	enum halmac_portid port;
+	enum halmac_ret_status status;
+	int err = -1;
+
+
+	halmac = dvobj_to_halmac(d);
+	api = HALMAC_GET_API(halmac);
+	port = _hw_port_drv2halmac(hwport);
+
+#if 0
+	status = api->halmac_cfg_aid(halmac, port, aid);
+	if (status != HALMAC_RET_SUCCESS)
+		goto out;
+#else
+{
+	struct _ADAPTER *a;
+	u32 addr;
+	u16 val;
+
+	a = dvobj_get_primary_adapter(d);
+
+	switch (port) {
+	case 0:
+		addr = REG_BCN_PSR_RPT;
+		val = rtw_read16(a, addr);
+		val = BIT_SET_PS_AID_0(val, aid);
+		rtw_write16(a, addr, val);
+		break;
+
+	case 1:
+		addr = REG_BCN_PSR_RPT1;
+		val = rtw_read16(a, addr);
+		val = BIT_SET_PS_AID_1(val, aid);
+		rtw_write16(a, addr, val);
+		break;
+
+	case 2:
+		addr = REG_BCN_PSR_RPT2;
+		val = rtw_read16(a, addr);
+		val = BIT_SET_PS_AID_2(val, aid);
+		rtw_write16(a, addr, val);
+		break;
+
+	case 3:
+		addr = REG_BCN_PSR_RPT3;
+		val = rtw_read16(a, addr);
+		val = BIT_SET_PS_AID_3(val, aid);
+		rtw_write16(a, addr, val);
+		break;
+
+	case 4:
+		addr = REG_BCN_PSR_RPT4;
+		val = rtw_read16(a, addr);
+		val = BIT_SET_PS_AID_4(val, aid);
+		rtw_write16(a, addr, val);
+		break;
+
+	default:
+		goto out;
+	}
+}
+#endif
+
+	err = 0;
+out:
+	return err;
+}
+
+int rtw_halmac_set_bandwidth(struct dvobj_priv *d, u8 channel, u8 pri_ch_idx, u8 bw)
+{
+	struct halmac_adapter *mac;
+	struct halmac_api *api;
+	enum halmac_ret_status status;
+
+
+	mac = dvobj_to_halmac(d);
+	api = HALMAC_GET_API(mac);
+
+	status = api->halmac_cfg_ch_bw(mac, channel, pri_ch_idx, bw);
+	if (HALMAC_RET_SUCCESS != status)
+		return -1;
+
+	return 0;
+}
+
+/**
+ * rtw_halmac_set_edca() - config edca parameter
+ * @d:		struct dvobj_priv*
+ * @queue:	XMIT_[VO/VI/BE/BK]_QUEUE
+ * @aifs:	Arbitration inter-frame space(AIFS)
+ * @cw:		Contention window(CW)
+ * @txop:	MAX Transmit Opportunity(TXOP)
+ *
+ * Return: 0 if process OK, otherwise -1.
+ */
+int rtw_halmac_set_edca(struct dvobj_priv *d, u8 queue, u8 aifs, u8 cw, u16 txop)
+{
+	struct halmac_adapter *mac;
+	struct halmac_api *api;
+	enum halmac_acq_id ac;
+	struct halmac_edca_para edca;
+	enum halmac_ret_status status;
+
+
+	mac = dvobj_to_halmac(d);
+	api = HALMAC_GET_API(mac);
+
+	switch (queue) {
+	case XMIT_VO_QUEUE:
+		ac = HALMAC_ACQ_ID_VO;
+		break;
+	case XMIT_VI_QUEUE:
+		ac = HALMAC_ACQ_ID_VI;
+		break;
+	case XMIT_BE_QUEUE:
+		ac = HALMAC_ACQ_ID_BE;
+		break;
+	case XMIT_BK_QUEUE:
+		ac = HALMAC_ACQ_ID_BK;
+		break;
+	default:
+		return -1;
+	}
+
+	edca.aifs = aifs;
+	edca.cw = cw;
+	edca.txop_limit = txop;
+
+	status = api->halmac_cfg_edca_para(mac, ac, &edca);
+	if (status != HALMAC_RET_SUCCESS)
+		return -1;
+
+	return 0;
+}
+
+/**
+ * rtw_halmac_set_rts_full_bw() - Send RTS to all covered channels
+ * @d:		struct dvobj_priv*
+ * @enable:	_TRUE(enable), _FALSE(disable)
+ *
+ * Hradware will duplicate RTS packet to all channels which are covered in used
+ * bandwidth.
+ *
+ * Return 0 if process OK, otherwise -1.
+ */
+int rtw_halmac_set_rts_full_bw(struct dvobj_priv *d, u8 enable)
+{
+	struct halmac_adapter *mac;
+	struct halmac_api *api;
+	enum halmac_ret_status status;
+	u8 full;
+
+
+	mac = dvobj_to_halmac(d);
+	api = HALMAC_GET_API(mac);
+	full = (enable == _TRUE) ? 1 : 0;
+
+	status = api->halmac_set_hw_value(mac, HALMAC_HW_RTS_FULL_BW, &full);
+	if (HALMAC_RET_SUCCESS != status)
+		return -1;
+
+	return 0;
+}
+
+#ifdef RTW_HALMAC_DBG_POWER_SWITCH
+static void _dump_mac_reg(struct dvobj_priv *d, u32 start, u32 end)
+{
+	struct _ADAPTER *adapter;
+	int i, j = 1;
+
+
+	adapter = dvobj_get_primary_adapter(d);
+	for (i = start; i < end; i += 4) {
+		if (j % 4 == 1)
+			RTW_PRINT("0x%04x", i);
+		_RTW_PRINT(" 0x%08x ", rtw_read32(adapter, i));
+		if ((j++) % 4 == 0)
+			_RTW_PRINT("\n");
+	}
+}
+
+void dump_dbg_val(struct _ADAPTER *a, u32 reg)
+{
+	u32 v32;
+
+
+	rtw_write8(a, 0x3A, reg);
+	v32 = rtw_read32(a, 0xC0);
+	RTW_PRINT("0x3A = %02x, 0xC0 = 0x%08x\n",reg, v32);
+}
+
+#ifdef CONFIG_PCI_HCI
+static void _dump_pcie_cfg_space(struct dvobj_priv *d)
+{
+	struct _ADAPTER *padapter = dvobj_get_primary_adapter(d);
+	struct dvobj_priv       *pdvobjpriv = adapter_to_dvobj(padapter);
+	struct pci_dev  *pdev = pdvobjpriv->ppcidev;
+	struct pci_dev  *bridge_pdev = pdev->bus->self;
+
+        u32 tmp[4] = { 0 };
+        u32 i, j;
+
+	RTW_PRINT("\n*****  PCI Device Configuration Space *****\n\n");
+
+        for(i = 0; i < 0x100; i += 0x10)
+        {
+                for (j = 0 ; j < 4 ; j++)
+                        pci_read_config_dword(pdev, i + j * 4, tmp+j);
+
+        	RTW_PRINT("%03x: %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x\n",
+                        i, tmp[0] & 0xFF, (tmp[0] >> 8) & 0xFF, (tmp[0] >> 16) & 0xFF, (tmp[0] >> 24) & 0xFF,
+                        tmp[1] & 0xFF, (tmp[1] >> 8) & 0xFF, (tmp[1] >> 16) & 0xFF, (tmp[1] >> 24) & 0xFF,
+                        tmp[2] & 0xFF, (tmp[2] >> 8) & 0xFF, (tmp[2] >> 16) & 0xFF, (tmp[2] >> 24) & 0xFF,
+                        tmp[3] & 0xFF, (tmp[3] >> 8) & 0xFF, (tmp[3] >> 16) & 0xFF, (tmp[3] >> 24) & 0xFF);
+        }
+
+	RTW_PRINT("\n*****  PCI Host Device Configuration Space*****\n\n");
+
+        for(i = 0; i < 0x100; i += 0x10)
+        {
+                for (j = 0 ; j < 4 ; j++)
+                        pci_read_config_dword(bridge_pdev, i + j * 4, tmp+j);
+
+        	RTW_PRINT("%03x: %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x\n",
+                        i, tmp[0] & 0xFF, (tmp[0] >> 8) & 0xFF, (tmp[0] >> 16) & 0xFF, (tmp[0] >> 24) & 0xFF,
+                        tmp[1] & 0xFF, (tmp[1] >> 8) & 0xFF, (tmp[1] >> 16) & 0xFF, (tmp[1] >> 24) & 0xFF,
+                        tmp[2] & 0xFF, (tmp[2] >> 8) & 0xFF, (tmp[2] >> 16) & 0xFF, (tmp[2] >> 24) & 0xFF,
+                        tmp[3] & 0xFF, (tmp[3] >> 8) & 0xFF, (tmp[3] >> 16) & 0xFF, (tmp[3] >> 24) & 0xFF);
+        }
+}
+#endif
+
+static void _dump_mac_reg_for_power_switch(struct dvobj_priv *d,
+					   const char* caller, char* desc)
+{
+	struct _ADAPTER *a;
+	u8 v8;
+
+
+	RTW_PRINT("%s: %s\n", caller, desc);
+	RTW_PRINT("======= MAC REG =======\n");
+	/* page 0/1 */
+	_dump_mac_reg(d, 0x0, 0x200);
+	_dump_mac_reg(d, 0x300, 0x400); /* also dump page 3 */
+
+	/* dump debug register */
+	a = dvobj_get_primary_adapter(d);
+
+#ifdef CONFIG_PCI_HCI
+	_dump_pcie_cfg_space(d);
+
+	v8 = rtw_read8(a, 0xF6) | 0x01;
+	rtw_write8(a, 0xF6, v8);
+	RTW_PRINT("0xF6 = %02x\n", v8);
+
+	dump_dbg_val(a, 0x63);
+	dump_dbg_val(a, 0x64);
+	dump_dbg_val(a, 0x68);
+	dump_dbg_val(a, 0x69);
+	dump_dbg_val(a, 0x6a);
+	dump_dbg_val(a, 0x6b);
+	dump_dbg_val(a, 0x71);
+	dump_dbg_val(a, 0x72);
+#endif
+}
+
+static enum halmac_ret_status _power_switch(struct halmac_adapter *halmac,
+					    struct halmac_api *api,
+					    enum halmac_mac_power pwr)
+{
+	enum halmac_ret_status status;
+	char desc[80] = {0};
+
+
+	rtw_sprintf(desc, 80, "before calling power %s",
+				(pwr==HALMAC_MAC_POWER_ON)?"on":"off");
+	_dump_mac_reg_for_power_switch((struct dvobj_priv *)halmac->drv_adapter,
+			__FUNCTION__, desc);
+
+	status = api->halmac_mac_power_switch(halmac, pwr);
+	RTW_PRINT("%s: status=%d\n", __FUNCTION__, status);
+
+	rtw_sprintf(desc, 80, "after calling power %s",
+				(pwr==HALMAC_MAC_POWER_ON)?"on":"off");
+	_dump_mac_reg_for_power_switch((struct dvobj_priv *)halmac->drv_adapter,
+			__FUNCTION__, desc);
+
+	return status;
+}
+#else /* !RTW_HALMAC_DBG_POWER_SWITCH */
+#define _power_switch(mac, api, pwr)	(api)->halmac_mac_power_switch(mac, pwr)
+#endif /* !RTW_HALMAC_DBG_POWER_SWITCH */
+
+/*
+ * Description:
+ *	Power on device hardware.
+ *	[Notice!] If device's power state is on before,
+ *	it would be power off first and turn on power again.
+ *
+ * Return:
+ *	0	power on success
+ *	-1	power on fail
+ *	-2	power state unchange
+ */
+int rtw_halmac_poweron(struct dvobj_priv *d)
+{
+	struct halmac_adapter *halmac;
+	struct halmac_api *api;
+	enum halmac_ret_status status;
+	int err = -1;
+#if defined(CONFIG_PCI_HCI) && defined(CONFIG_RTL8822B)
+	struct _ADAPTER *a;
+	u8 v8;
+	u32 addr;
+
+	a = dvobj_get_primary_adapter(d);
+#endif
+
+	halmac = dvobj_to_halmac(d);
+	if (!halmac)
+		goto out;
+
+	api = HALMAC_GET_API(halmac);
+
+	status = api->halmac_pre_init_system_cfg(halmac);
+	if (status != HALMAC_RET_SUCCESS)
+		goto out;
+
+#ifdef CONFIG_SDIO_HCI
+	status = api->halmac_sdio_cmd53_4byte(halmac, HALMAC_SDIO_CMD53_4BYTE_MODE_RW);
+	if (status != HALMAC_RET_SUCCESS)
+		goto out;
+#endif /* CONFIG_SDIO_HCI */
+
+#if defined(CONFIG_PCI_HCI) && defined(CONFIG_RTL8822B)
+	addr = 0x3F3;
+	v8 = rtw_read8(a, addr);
+	RTW_PRINT("%s: 0x%X = 0x%02x\n", __FUNCTION__, addr, v8);
+	/* are we in pcie debug mode? */
+	if (!(v8 & BIT(2))) {
+		RTW_PRINT("%s: Enable pcie debug mode\n", __FUNCTION__);
+		v8 |= BIT(2);
+		v8 = rtw_write8(a, addr, v8);
+	}
+#endif
+
+	status = _power_switch(halmac, api, HALMAC_MAC_POWER_ON);
+	if (HALMAC_RET_PWR_UNCHANGE == status) {
+
+#if defined(CONFIG_PCI_HCI) && defined(CONFIG_RTL8822B)
+		addr = 0x3F3;
+		v8 = rtw_read8(a, addr);
+		RTW_PRINT("%s: 0x%X = 0x%02x\n", __FUNCTION__, addr, v8);
+		
+		/* are we in pcie debug mode? */
+		if (!(v8 & BIT(2))) {
+			RTW_PRINT("%s: Enable pcie debug mode\n", __FUNCTION__);
+			v8 |= BIT(2);
+			v8 = rtw_write8(a, addr, v8);
+		} else if (v8 & BIT(0)) {
+			/* DMA stuck */
+			addr = 0x1350;
+			v8 = rtw_read8(a, addr);
+			RTW_PRINT("%s: 0x%X = 0x%02x\n", __FUNCTION__, addr, v8);
+			RTW_PRINT("%s: recover DMA stuck\n", __FUNCTION__);
+			v8 |= BIT(6);
+			v8 = rtw_write8(a, addr, v8);
+			RTW_PRINT("%s: 0x%X = 0x%02x\n", __FUNCTION__, addr, v8);
+		}
+#endif
+		/*
+		 * Work around for warm reboot but device not power off,
+		 * but it would also fall into this case when auto power on is enabled.
+		 */
+		_power_switch(halmac, api, HALMAC_MAC_POWER_OFF);
+		status = _power_switch(halmac, api, HALMAC_MAC_POWER_ON);
+		RTW_WARN("%s: Power state abnormal, try to recover...%s\n",
+			 __FUNCTION__, (HALMAC_RET_SUCCESS == status)?"OK":"FAIL!");
+	}
+	if (HALMAC_RET_SUCCESS != status) {
+		if (HALMAC_RET_PWR_UNCHANGE == status)
+			err = -2;
+		goto out;
+	}
+
+	status = api->halmac_init_system_cfg(halmac);
+	if (status != HALMAC_RET_SUCCESS)
+		goto out;
+
+	err = 0;
+out:
+	return err;
+}
+
+/*
+ * Description:
+ *	Power off device hardware.
+ *
+ * Return:
+ *	0	Power off success
+ *	-1	Power off fail
+ */
+int rtw_halmac_poweroff(struct dvobj_priv *d)
+{
+	struct halmac_adapter *halmac;
+	struct halmac_api *api;
+	enum halmac_ret_status status;
+	int err = -1;
+
+
+	halmac = dvobj_to_halmac(d);
+	if (!halmac)
+		goto out;
+
+	api = HALMAC_GET_API(halmac);
+
+	status = _power_switch(halmac, api, HALMAC_MAC_POWER_OFF);
+	if ((HALMAC_RET_SUCCESS != status)
+	    && (HALMAC_RET_PWR_UNCHANGE != status))
+		goto out;
+
+	err = 0;
+out:
+	return err;
+}
+
+#ifdef CONFIG_SUPPORT_TRX_SHARED
+static inline enum halmac_rx_fifo_expanding_mode _trx_share_mode_drv2halmac(u8 trx_share_mode)
+{
+	if (0 == trx_share_mode)
+		return HALMAC_RX_FIFO_EXPANDING_MODE_DISABLE;
+	else if (1 == trx_share_mode)
+		return HALMAC_RX_FIFO_EXPANDING_MODE_1_BLOCK;
+	else if (2 == trx_share_mode)
+		return HALMAC_RX_FIFO_EXPANDING_MODE_2_BLOCK;
+	else if (3 == trx_share_mode)
+		return HALMAC_RX_FIFO_EXPANDING_MODE_3_BLOCK;
+	else
+		return HALMAC_RX_FIFO_EXPANDING_MODE_DISABLE;
+}
+
+static enum halmac_rx_fifo_expanding_mode _rtw_get_trx_share_mode(struct _ADAPTER *adapter)
+{
+	struct registry_priv *registry_par = &adapter->registrypriv;
+
+	return _trx_share_mode_drv2halmac(registry_par->trx_share_mode);
+}
+
+void dump_trx_share_mode(void *sel, struct _ADAPTER *adapter)
+{
+	struct registry_priv  *registry_par = &adapter->registrypriv;
+	u8 mode = _trx_share_mode_drv2halmac(registry_par->trx_share_mode);
+
+	if (HALMAC_RX_FIFO_EXPANDING_MODE_1_BLOCK == mode)
+		RTW_PRINT_SEL(sel, "TRx share mode : %s\n", "RX_FIFO_EXPANDING_MODE_1");
+	else if (HALMAC_RX_FIFO_EXPANDING_MODE_2_BLOCK == mode)
+		RTW_PRINT_SEL(sel, "TRx share mode : %s\n", "RX_FIFO_EXPANDING_MODE_2");
+	else if (HALMAC_RX_FIFO_EXPANDING_MODE_3_BLOCK == mode)
+		RTW_PRINT_SEL(sel, "TRx share mode : %s\n", "RX_FIFO_EXPANDING_MODE_3");
+	else
+		RTW_PRINT_SEL(sel, "TRx share mode : %s\n", "DISABLE");
+}
+#endif
+
+static enum halmac_drv_rsvd_pg_num _rsvd_page_num_drv2halmac(u8 num)
+{
+	if (num <= 8)
+		return HALMAC_RSVD_PG_NUM8;
+	if (num <= 16)
+		return HALMAC_RSVD_PG_NUM16;
+	if (num <= 24)
+		return HALMAC_RSVD_PG_NUM24;
+	if (num <= 32)
+		return HALMAC_RSVD_PG_NUM32;
+	if (num <= 64)
+		return HALMAC_RSVD_PG_NUM64;
+
+	if (num > 128)
+		RTW_WARN("%s: Fail to allocate RSVD page(%d)!!"
+			 " The MAX RSVD page number is 128...\n",
+			 __FUNCTION__, num);
+
+	return HALMAC_RSVD_PG_NUM128;
+}
+
+static u8 _rsvd_page_num_halmac2drv(enum halmac_drv_rsvd_pg_num rsvd_page_number)
+{
+	u8 num = 0;
+
+
+	switch (rsvd_page_number) {
+	case HALMAC_RSVD_PG_NUM8:
+		num = 8;
+		break;
+
+	case HALMAC_RSVD_PG_NUM16:
+		num = 16;
+		break;
+
+	case HALMAC_RSVD_PG_NUM24:
+		num = 24;
+		break;
+
+	case HALMAC_RSVD_PG_NUM32:
+		num = 32;
+		break;
+
+	case HALMAC_RSVD_PG_NUM64:
+		num = 64;
+		break;
+
+	case HALMAC_RSVD_PG_NUM128:
+		num = 128;
+		break;
+	}
+
+	return num;
+}
+
+static enum halmac_trx_mode _choose_trx_mode(struct dvobj_priv *d)
+{
+	PADAPTER p;
+
+
+	p = dvobj_get_primary_adapter(d);
+
+	if (p->registrypriv.wifi_spec)
+		return HALMAC_TRX_MODE_WMM;
+
+#ifdef CONFIG_SUPPORT_TRX_SHARED
+	if (_rtw_get_trx_share_mode(p))
+		return HALMAC_TRX_MODE_TRXSHARE;
+#endif
+
+	return HALMAC_TRX_MODE_NORMAL;
+}
+
+static inline enum halmac_rf_type _rf_type_drv2halmac(enum rf_type rf_drv)
+{
+	enum halmac_rf_type rf_mac;
+
+
+	switch (rf_drv) {
+	case RF_1T1R:
+		rf_mac = HALMAC_RF_1T1R;
+		break;
+	case RF_1T2R:
+		rf_mac = HALMAC_RF_1T2R;
+		break;
+	case RF_2T2R:
+		rf_mac = HALMAC_RF_2T2R;
+		break;
+	case RF_2T3R:
+		rf_mac = HALMAC_RF_2T3R;
+		break;
+	case RF_2T4R:
+		rf_mac = HALMAC_RF_2T4R;
+		break;
+	case RF_3T3R:
+		rf_mac = HALMAC_RF_3T3R;
+		break;
+	case RF_3T4R:
+		rf_mac = HALMAC_RF_3T4R;
+		break;
+	case RF_4T4R:
+		rf_mac = HALMAC_RF_4T4R;
+		break;
+	default:
+		rf_mac = HALMAC_RF_MAX_TYPE;
+		RTW_ERR("%s: Invalid RF type(0x%x)!\n", __FUNCTION__, rf_drv);
+		break;
+	}
+
+	return rf_mac;
+}
+
+static inline enum rf_type _rf_type_halmac2drv(enum halmac_rf_type rf_mac)
+{
+	enum rf_type rf_drv;
+
+
+	switch (rf_mac) {
+	case HALMAC_RF_1T2R:
+		rf_drv = RF_1T2R;
+		break;
+	case HALMAC_RF_2T4R:
+		rf_drv = RF_2T4R;
+		break;
+	case HALMAC_RF_2T2R:
+	case HALMAC_RF_2T2R_GREEN:
+		rf_drv = RF_2T2R;
+		break;
+	case HALMAC_RF_2T3R:
+		rf_drv = RF_2T3R;
+		break;
+	case HALMAC_RF_1T1R:
+		rf_drv = RF_1T1R;
+		break;
+	case HALMAC_RF_3T3R:
+		rf_drv = RF_3T3R;
+		break;
+	case HALMAC_RF_3T4R:
+		rf_drv = RF_3T4R;
+		break;
+	case HALMAC_RF_4T4R:
+		rf_drv = RF_4T4R;
+		break;
+	default:
+		rf_drv = RF_TYPE_MAX;
+		RTW_ERR("%s: Invalid RF type(0x%x)!\n", __FUNCTION__, rf_mac);
+		break;
+	}
+
+	return rf_drv;
+}
+
+static enum odm_cut_version _cut_version_drv2phydm(
+				enum tag_HAL_Cut_Version_Definition cut_drv)
+{
+	enum odm_cut_version cut_phydm = ODM_CUT_A;
+	u32 diff;
+
+
+	if (cut_drv > K_CUT_VERSION)
+		RTW_WARN("%s: unknown cut_ver=%d !!\n", __FUNCTION__, cut_drv);
+
+	diff = cut_drv - A_CUT_VERSION;
+	cut_phydm += diff;
+
+	return cut_phydm;
+}
+
+static int _send_general_info_by_reg(struct dvobj_priv *d,
+				     struct halmac_general_info *info)
+{
+	struct _ADAPTER *a;
+	struct hal_com_data *hal;
+	enum tag_HAL_Cut_Version_Definition cut_drv;
+	enum rf_type rftype;
+	enum odm_cut_version cut_phydm;
+	u8 h2c[RTW_HALMAC_H2C_MAX_SIZE] = {0};
+
+
+	a = dvobj_get_primary_adapter(d);
+	hal = GET_HAL_DATA(a);
+	rftype = _rf_type_halmac2drv(info->rf_type);
+	cut_drv = GET_CVID_CUT_VERSION(hal->version_id);
+	cut_phydm = _cut_version_drv2phydm(cut_drv);
+
+#define CLASS_GENERAL_INFO_REG				0x02
+#define CMD_ID_GENERAL_INFO_REG				0x0C
+#define GENERAL_INFO_REG_SET_CMD_ID(buf, v)		SET_BITS_TO_LE_4BYTE(buf, 0, 5, v)
+#define GENERAL_INFO_REG_SET_CLASS(buf, v)		SET_BITS_TO_LE_4BYTE(buf, 5, 3, v)
+#define GENERAL_INFO_REG_SET_RFE_TYPE(buf, v)		SET_BITS_TO_LE_4BYTE(buf, 8, 8, v)
+#define GENERAL_INFO_REG_SET_RF_TYPE(buf, v)		SET_BITS_TO_LE_4BYTE(buf, 16, 8, v)
+#define GENERAL_INFO_REG_SET_CUT_VERSION(buf, v)	SET_BITS_TO_LE_4BYTE(buf, 24, 8, v)
+#define GENERAL_INFO_REG_SET_RX_ANT_STATUS(buf, v)	SET_BITS_TO_LE_1BYTE(buf+4, 0, 4, v)
+#define GENERAL_INFO_REG_SET_TX_ANT_STATUS(buf, v)	SET_BITS_TO_LE_1BYTE(buf+4, 4, 4, v)
+
+	GENERAL_INFO_REG_SET_CMD_ID(h2c, CMD_ID_GENERAL_INFO_REG);
+	GENERAL_INFO_REG_SET_CLASS(h2c, CLASS_GENERAL_INFO_REG);
+	GENERAL_INFO_REG_SET_RFE_TYPE(h2c, info->rfe_type);
+	GENERAL_INFO_REG_SET_RF_TYPE(h2c, rftype);
+	GENERAL_INFO_REG_SET_CUT_VERSION(h2c, cut_phydm);
+	GENERAL_INFO_REG_SET_RX_ANT_STATUS(h2c, info->rx_ant_status);
+	GENERAL_INFO_REG_SET_TX_ANT_STATUS(h2c, info->tx_ant_status);
+
+	return rtw_halmac_send_h2c(d, h2c);
+}
+
+static int _send_general_info(struct dvobj_priv *d)
+{
+	struct _ADAPTER *adapter;
+	struct hal_com_data *hal;
+	struct halmac_adapter *halmac;
+	struct halmac_api *api;
+	struct halmac_general_info info;
+	enum halmac_ret_status status;
+	enum rf_type rf = RF_1T1R;
+	enum bb_path txpath = BB_PATH_A;
+	enum bb_path rxpath = BB_PATH_A;
+	int err;
+
+
+	adapter = dvobj_get_primary_adapter(d);
+	hal = GET_HAL_DATA(adapter);
+	halmac = dvobj_to_halmac(d);
+	if (!halmac)
+		return -1;
+	api = HALMAC_GET_API(halmac);
+
+	_rtw_memset(&info, 0, sizeof(info));
+	info.rfe_type = (u8)hal->rfe_type;
+	rtw_hal_get_rf_path(d, &rf, &txpath, &rxpath);
+	info.rf_type = _rf_type_drv2halmac(rf);
+	info.tx_ant_status = (u8)txpath;
+	info.rx_ant_status = (u8)rxpath;
+
+	status = api->halmac_send_general_info(halmac, &info);
+	switch (status) {
+	case HALMAC_RET_SUCCESS:
+		break;
+	case HALMAC_RET_NO_DLFW:
+		RTW_WARN("%s: halmac_send_general_info() fail because fw not dl!\n",
+			 __FUNCTION__);
+		__attribute__((__fallthrough__));
+	default:
+		return -1;
+	}
+
+	err = _send_general_info_by_reg(d, &info);
+	if (err) {
+		RTW_ERR("%s: Fail to send general info by register!\n",
+			 __FUNCTION__);
+		return -1;
+	}
+
+	return 0;
+}
+
+static int _cfg_drv_rsvd_pg_num(struct dvobj_priv *d)
+{
+	struct _ADAPTER *a;
+	struct hal_com_data *hal;
+	struct halmac_adapter *halmac;
+	struct halmac_api *api;
+	enum halmac_drv_rsvd_pg_num rsvd_page_number;
+	enum halmac_ret_status status;
+	u8 drv_rsvd_num;
+
+
+	a = dvobj_get_primary_adapter(d);
+	hal = GET_HAL_DATA(a);
+	halmac = dvobj_to_halmac(d);
+	api = HALMAC_GET_API(halmac);
+
+	drv_rsvd_num = rtw_hal_get_rsvd_page_num(a);
+	rsvd_page_number = _rsvd_page_num_drv2halmac(drv_rsvd_num);
+	status = api->halmac_cfg_drv_rsvd_pg_num(halmac, rsvd_page_number);
+	if (status != HALMAC_RET_SUCCESS)
+		return -1;
+	hal->drv_rsvd_page_number = _rsvd_page_num_halmac2drv(rsvd_page_number);
+
+	if (drv_rsvd_num != hal->drv_rsvd_page_number)
+		RTW_INFO("%s: request %d pages, but allocate %d pages\n",
+			 __FUNCTION__, drv_rsvd_num, hal->drv_rsvd_page_number);
+
+	return 0;
+}
+
+static void _debug_dlfw_fail(struct dvobj_priv *d)
+{
+	struct _ADAPTER *a;
+	u32 addr;
+	u32 v32, i, n;
+	u8 data[0x100] = {0};
+
+
+	a = dvobj_get_primary_adapter(d);
+
+	/* read 0x80[15:0], 0x10F8[31:0] once */
+	addr = 0x80;
+	v32 = rtw_read16(a, addr);
+	RTW_PRINT("%s: 0x%X = 0x%04x\n", __FUNCTION__, addr, v32);
+
+	addr = 0x10F8;
+	v32 = rtw_read32(a, addr);
+	RTW_PRINT("%s: 0x%X = 0x%08x\n", __FUNCTION__, addr, v32);
+
+	/* read 0x10FC[31:0], 5 times */
+	addr = 0x10FC;
+	n = 5;
+	for (i = 0; i < n; i++) {
+		v32 = rtw_read32(a, addr);
+		RTW_PRINT("%s: 0x%X = 0x%08x (%u/%u)\n",
+			  __FUNCTION__, addr, v32, i, n);
+	}
+
+	/*
+	 * write 0x3A[7:0]=0x28 and 0xF6[7:0]=0x01
+	 * and then read 0xC0[31:0] 5 times
+	 */
+	addr = 0x3A;
+	v32 = 0x28;
+	rtw_write8(a, addr, (u8)v32);
+	v32 = rtw_read8(a, addr);
+	RTW_PRINT("%s: 0x%X = 0x%02x\n", __FUNCTION__, addr, v32);
+
+	addr = 0xF6;
+	v32 = 0x1;
+	rtw_write8(a, addr, (u8)v32);
+	v32 = rtw_read8(a, addr);
+	RTW_PRINT("%s: 0x%X = 0x%02x\n", __FUNCTION__, addr, v32);
+
+	addr = 0xC0;
+	n = 5;
+	for (i = 0; i < n; i++) {
+		v32 = rtw_read32(a, addr);
+		RTW_PRINT("%s: 0x%X = 0x%08x (%u/%u)\n",
+			  __FUNCTION__, addr, v32, i, n);
+	}
+
+	/* 0x00~0xFF, 0x1000~0x10FF */
+	addr = 0;
+	n = 0x100;
+	for (i = 0; i < n; i+=4)
+		*(u32*)&data[i] = cpu_to_le32(rtw_read32(a, addr+i));
+	for (i = 0; i < n; i++) {
+		if (i % 16 == 0)
+			RTW_PRINT("0x%04x\t", addr+i);
+		_RTW_PRINT("0x%02x", data[i]);
+		if (i % 16 == 15)
+			_RTW_PRINT("\n");
+		else
+			_RTW_PRINT(" ");
+	}
+
+	addr = 0x1000;
+	n = 0x100;
+	for (i = 0; i < n; i+=4)
+		*(u32*)&data[i] = cpu_to_le32(rtw_read32(a, addr+i));
+	for (i = 0; i < n; i++) {
+		if (i % 16 == 0)
+			RTW_PRINT("0x%04x\t", addr+i);
+		_RTW_PRINT("0x%02x", data[i]);
+		if (i % 16 == 15)
+			_RTW_PRINT("\n");
+		else
+			_RTW_PRINT(" ");
+	}
+
+	/* read 0x80 after 10 secs */
+	rtw_msleep_os(10000);
+	addr = 0x80;
+	v32 = rtw_read16(a, addr);
+	RTW_PRINT("%s: 0x%X = 0x%04x (after 10 secs)\n",
+		  __FUNCTION__, addr, v32);
+}
+
+static enum halmac_ret_status _enter_cpu_sleep_mode(struct dvobj_priv *d)
+{
+	struct hal_com_data *hal;
+	struct halmac_adapter *mac;
+	struct halmac_api *api;
+
+
+	hal = GET_HAL_DATA(dvobj_get_primary_adapter(d));
+	mac = dvobj_to_halmac(d);
+	api = HALMAC_GET_API(mac);
+
+#ifdef CONFIG_RTL8822B
+	/* Support after firmware version 21 */
+	if (hal->firmware_version < 21)
+		return HALMAC_RET_NOT_SUPPORT;
+#elif defined(CONFIG_RTL8821C)
+	/* Support after firmware version 13.6 or 16 */
+	if (hal->firmware_version == 13) {
+		if (hal->firmware_sub_version < 6)
+			return HALMAC_RET_NOT_SUPPORT;
+	} else if (hal->firmware_version < 16) {
+		return HALMAC_RET_NOT_SUPPORT;
+	}
+#endif
+
+	return api->halmac_enter_cpu_sleep_mode(mac);
+}
+
+/*
+ * _cpu_sleep() - Let IC CPU enter sleep mode
+ * @d:		struct dvobj_priv*
+ * @timeout:	time limit of wait, unit is ms
+ *		0 for no limit
+ *
+ * Rteurn 0 for CPU in sleep mode, otherwise fail to enter sleep mode.
+ * Error codes definition are as follow:
+ * 	-1	HALMAC enter sleep return fail
+ *	-2	HALMAC get CPU mode return fail
+ *	-110	timeout
+ */
+static int _cpu_sleep(struct dvobj_priv *d, u32 timeout)
+{
+	struct halmac_adapter *mac;
+	struct halmac_api *api;
+	enum halmac_ret_status status;
+	enum halmac_wlcpu_mode mode = HALMAC_WLCPU_UNDEFINE;
+	systime start_t;
+	s32 period = 0;
+	u32 cnt = 0;
+	int err = 0;
+
+
+	mac = dvobj_to_halmac(d);
+	api = HALMAC_GET_API(mac);
+
+	start_t = rtw_get_current_time();
+
+	status = _enter_cpu_sleep_mode(d);
+	if (status != HALMAC_RET_SUCCESS) {
+		if (status != HALMAC_RET_NOT_SUPPORT)
+			err = -1;
+		goto exit;
+	}
+
+	do {
+		cnt++;
+
+		mode = HALMAC_WLCPU_UNDEFINE;
+		status = api->halmac_get_cpu_mode(mac, &mode);
+
+		period = rtw_get_passing_time_ms(start_t);
+
+		if (status != HALMAC_RET_SUCCESS) {
+			err = -2;
+			break;
+		}
+		if (mode == HALMAC_WLCPU_SLEEP)
+			break;
+		if (period > timeout) {
+			err = -110;
+			break;
+		}
+
+		rtw_msleep_os(1);
+	} while (1);
+
+exit:
+	if (err)
+		RTW_ERR("%s: Fail to enter sleep mode! (%d, %d)\n",
+			__FUNCTION__, status, mode);
+
+	RTW_INFO("%s: Cost %dms to polling %u times. (err=%d)\n",
+		__FUNCTION__, period, cnt, err);
+
+	return err;
+}
+
+static void _init_trx_cfg_drv(struct dvobj_priv *d)
+{
+#ifdef CONFIG_PCI_HCI
+	rtw_hal_irp_reset(dvobj_get_primary_adapter(d));
+#endif
+}
+
+/*
+ * Description:
+ *	Downlaod Firmware Flow
+ *
+ * Parameters:
+ *	d	pointer of struct dvobj_priv
+ *	fw	firmware array
+ *	fwsize	firmware size
+ *	re_dl	re-download firmware or not
+ *		0: run in init hal flow, not re-download
+ *		1: it is a stand alone operation, not in init hal flow
+ *
+ * Return:
+ *	0	Success
+ *	others	Fail
+ */
+static int download_fw(struct dvobj_priv *d, u8 *fw, u32 fwsize, u8 re_dl)
+{
+	PHAL_DATA_TYPE hal;
+	struct halmac_adapter *mac;
+	struct halmac_api *api;
+	struct halmac_fw_version fw_vesion;
+	enum halmac_ret_status status;
+	int err = 0;
+
+
+	hal = GET_HAL_DATA(dvobj_get_primary_adapter(d));
+	mac = dvobj_to_halmac(d);
+	api = HALMAC_GET_API(mac);
+
+	if ((!fw) || (!fwsize))
+		return -1;
+
+	/* 1. Driver Stop Tx */
+	/* ToDo */
+
+	/* 2. Driver Check Tx FIFO is empty */
+	err = rtw_halmac_txfifo_wait_empty(d, 2000); /* wait 2s */
+	if (err) {
+		err = -1;
+		goto resume_tx;
+	}
+
+	/* 3. Config MAX download size */
+	/*
+	 * Already done in rtw_halmac_init_adapter() or
+	 * somewhere calling rtw_halmac_set_max_dl_fw_size().
+	 */
+
+	if (re_dl) {
+		/* 4. Enter IC CPU sleep mode */
+		err = _cpu_sleep(d, 2000);
+		if (err) {
+			RTW_ERR("%s: IC CPU fail to enter sleep mode!(%d)\n",
+				__FUNCTION__, err);
+			/* skip this error */
+			err = 0;
+		}
+	}
+
+	/* 5. Download Firmware */
+	status = api->halmac_download_firmware(mac, fw, fwsize);
+	if (status != HALMAC_RET_SUCCESS) {
+		RTW_ERR("%s: download firmware FAIL! status=0x%02x\n",
+			__FUNCTION__, status);
+		_debug_dlfw_fail(d);
+		err = -1;
+		goto resume_tx;
+	}
+
+	/* 5.1. (Driver) Reset driver variables if needed */
+	hal->LastHMEBoxNum = 0;
+
+	/* 5.2. (Driver) Get FW version */
+	status = api->halmac_get_fw_version(mac, &fw_vesion);
+	if (status == HALMAC_RET_SUCCESS) {
+		hal->firmware_version = fw_vesion.version;
+		hal->firmware_sub_version = fw_vesion.sub_version;
+		hal->firmware_size = fwsize;
+	}
+
+resume_tx:
+	/* 6. Driver resume TX if needed */
+	/* ToDo */
+
+	if (err)
+		goto exit;
+
+	if (re_dl) {
+		enum halmac_trx_mode mode;
+
+		/* 7. Change reserved page size */
+		err = _cfg_drv_rsvd_pg_num(d);
+		if (err)
+			return -1;
+
+		/* 8. Init TRX Configuration */
+		mode = _choose_trx_mode(d);
+		status = api->halmac_init_trx_cfg(mac, mode);
+		if (HALMAC_RET_SUCCESS != status)
+			return -1;
+		_init_trx_cfg_drv(d);
+
+		/* 9. Config RX Aggregation */
+		err = rtw_halmac_rx_agg_switch(d, _TRUE);
+		if (err)
+			return -1;
+
+		/* 10. Send General Info */
+		err = _send_general_info(d);
+		if (err)
+			return -1;
+	}
+
+exit:
+	return err;
+}
+
+static int init_mac_flow(struct dvobj_priv *d)
+{
+	PADAPTER p;
+	struct hal_com_data *hal;
+	struct halmac_adapter *halmac;
+	struct halmac_api *api;
+	enum halmac_drv_rsvd_pg_num rsvd_page_number;
+	union halmac_wlan_addr hwa;
+	enum halmac_trx_mode trx_mode;
+	enum halmac_ret_status status;
+	u8 drv_rsvd_num;
+	u8 nettype;
+	int err, err_ret = -1;
+
+
+	p = dvobj_get_primary_adapter(d);
+	hal = GET_HAL_DATA(p);
+	halmac = dvobj_to_halmac(d);
+	api = HALMAC_GET_API(halmac);
+
+#ifdef CONFIG_SUPPORT_TRX_SHARED
+	status = api->halmac_cfg_rxff_expand_mode(halmac,
+						  _rtw_get_trx_share_mode(p));
+	if (status != HALMAC_RET_SUCCESS)
+		goto out;
+#endif
+
+#if 0 /* It is not necessary to call this in normal driver */
+	status = api->halmac_cfg_la_mode(halmac, HALMAC_LA_MODE_DISABLE);
+	if (status != HALMAC_RET_SUCCESS)
+		goto out;
+#endif
+
+	err = _cfg_drv_rsvd_pg_num(d);
+	if (err)
+		goto out;
+
+#ifdef CONFIG_USB_HCI
+	status = api->halmac_set_bulkout_num(halmac, d->RtNumOutPipes);
+	if (status != HALMAC_RET_SUCCESS)
+		goto out;
+#endif /* CONFIG_USB_HCI */
+
+	trx_mode = _choose_trx_mode(d);
+	status = api->halmac_init_mac_cfg(halmac, trx_mode);
+	if (status != HALMAC_RET_SUCCESS)
+		goto out;
+	_init_trx_cfg_drv(d);
+
+	err = rtw_halmac_rx_agg_switch(d, _TRUE);
+	if (err)
+		goto out;
+
+	nettype = dvobj_to_regsty(d)->wireless_mode;
+	if (is_supported_vht(nettype) == _TRUE)
+		status = api->halmac_cfg_operation_mode(halmac, HALMAC_WIRELESS_MODE_AC);
+	else if (is_supported_ht(nettype) == _TRUE)
+		status = api->halmac_cfg_operation_mode(halmac, HALMAC_WIRELESS_MODE_N);
+	else if (IsSupportedTxOFDM(nettype) == _TRUE)
+		status = api->halmac_cfg_operation_mode(halmac, HALMAC_WIRELESS_MODE_G);
+	else
+		status = api->halmac_cfg_operation_mode(halmac, HALMAC_WIRELESS_MODE_B);
+	if (status != HALMAC_RET_SUCCESS)
+		goto out;
+
+	err_ret = 0;
+out:
+	return err_ret;
+}
+
+static int _drv_enable_trx(struct dvobj_priv *d)
+{
+	struct _ADAPTER *adapter;
+	u32 status;
+
+
+	adapter = dvobj_get_primary_adapter(d);
+	if (adapter->bup == _FALSE) {
+#ifdef CONFIG_NEW_NETDEV_HDL
+		status = rtw_mi_start_drv_threads(adapter);
+#else
+		status = rtw_start_drv_threads(adapter);
+#endif
+		if (status == _FAIL) {
+			RTW_ERR("%s: Start threads Failed!\n", __FUNCTION__);
+			return -1;
+		}
+	}
+
+	rtw_intf_start(adapter);
+
+	return 0;
+}
+
+/*
+ * Notices:
+ *	Make sure
+ *	1. rtw_hal_get_hwreg(HW_VAR_RF_TYPE)
+ *	2. HAL_DATA_TYPE.rfe_type
+ *	already ready for use before calling this function.
+ */
+static int _halmac_init_hal(struct dvobj_priv *d, u8 *fw, u32 fwsize)
+{
+	PADAPTER adapter;
+	struct halmac_adapter *halmac;
+	struct halmac_api *api;
+	enum halmac_ret_status status;
+	u32 ok;
+	u8 fw_ok = _FALSE;
+	int err, err_ret = -1;
+
+
+	adapter = dvobj_get_primary_adapter(d);
+	halmac = dvobj_to_halmac(d);
+	if (!halmac)
+		goto out;
+	api = HALMAC_GET_API(halmac);
+
+	/* StatePowerOff */
+
+	/* SKIP: halmac_init_adapter (Already done before) */
+
+	/* halmac_pre_Init_system_cfg */
+	/* halmac_mac_power_switch(on) */
+	/* halmac_Init_system_cfg */
+	ok = rtw_hal_power_on(adapter);
+	if (_FAIL == ok)
+		goto out;
+
+	/* StatePowerOn */
+
+	/* DownloadFW */
+	if (fw && fwsize) {
+		err = download_fw(d, fw, fwsize, 0);
+		if (err)
+			goto out;
+		fw_ok = _TRUE;
+	}
+
+	/* InitMACFlow */
+	err = init_mac_flow(d);
+	if (err)
+		goto out;
+
+	/* Driver insert flow: Enable TR/RX */
+	err = _drv_enable_trx(d);
+	if (err)
+		goto out;
+
+	/* halmac_send_general_info */
+	if (_TRUE == fw_ok) {
+		err = _send_general_info(d);
+		if (err)
+			goto out;
+	}
+
+	/* Init Phy parameter-MAC */
+	ok = rtw_hal_init_mac_register(adapter);
+	if (_FALSE == ok)
+		goto out;
+
+	/* StateMacInitialized */
+
+	/* halmac_cfg_drv_info */
+	err = rtw_halmac_config_rx_info(d, HALMAC_DRV_INFO_PHY_STATUS);
+	if (err)
+		goto out;
+
+	/* halmac_set_hw_value(HALMAC_HW_EN_BB_RF) */
+	/* Init BB, RF */
+	ok = rtw_hal_init_phy(adapter);
+	if (_FALSE == ok)
+		goto out;
+
+	status = api->halmac_init_interface_cfg(halmac);
+	if (status != HALMAC_RET_SUCCESS)
+		goto out;
+
+	/* SKIP: halmac_verify_platform_api */
+	/* SKIP: halmac_h2c_lb */
+
+	/* StateRxIdle */
+
+	err_ret = 0;
+out:
+	return err_ret;
+}
+
+int rtw_halmac_init_hal(struct dvobj_priv *d)
+{
+	return _halmac_init_hal(d, NULL, 0);
+}
+
+/*
+ * Notices:
+ *	Make sure
+ *	1. rtw_hal_get_hwreg(HW_VAR_RF_TYPE)
+ *	2. HAL_DATA_TYPE.rfe_type
+ *	already ready for use before calling this function.
+ */
+int rtw_halmac_init_hal_fw(struct dvobj_priv *d, u8 *fw, u32 fwsize)
+{
+	return _halmac_init_hal(d, fw, fwsize);
+}
+
+/*
+ * Notices:
+ *	Make sure
+ *	1. rtw_hal_get_hwreg(HW_VAR_RF_TYPE)
+ *	2. HAL_DATA_TYPE.rfe_type
+ *	already ready for use before calling this function.
+ */
+int rtw_halmac_init_hal_fw_file(struct dvobj_priv *d, u8 *fwpath)
+{
+	u8 *fw = NULL;
+	u32 fwmaxsize = 0, size = 0;
+	int err = 0;
+
+
+	err = rtw_halmac_get_fw_max_size(d, &fwmaxsize);
+	if (err) {
+		RTW_ERR("%s: Fail to get Firmware MAX size(err=%d)\n", __FUNCTION__, err);
+		return -1;
+	}
+
+	fw = rtw_zmalloc(fwmaxsize);
+	if (!fw)
+		return -1;
+
+	size = rtw_retrieve_from_file(fwpath, fw, fwmaxsize);
+	if (!size) {
+		err = -1;
+		goto exit;
+	}
+
+	err = _halmac_init_hal(d, fw, size);
+
+exit:
+	rtw_mfree(fw, fwmaxsize);
+	/*fw = NULL;*/
+
+	return err;
+}
+
+int rtw_halmac_deinit_hal(struct dvobj_priv *d)
+{
+	PADAPTER adapter;
+	struct halmac_adapter *halmac;
+	struct halmac_api *api;
+	enum halmac_ret_status status;
+	int err = -1;
+
+
+	adapter = dvobj_get_primary_adapter(d);
+	halmac = dvobj_to_halmac(d);
+	if (!halmac)
+		goto out;
+	api = HALMAC_GET_API(halmac);
+
+	status = api->halmac_deinit_interface_cfg(halmac);
+	if (status != HALMAC_RET_SUCCESS)
+		goto out;
+
+	rtw_hal_power_off(adapter);
+
+	err = 0;
+out:
+	return err;
+}
+
+int rtw_halmac_self_verify(struct dvobj_priv *d)
+{
+	struct halmac_adapter *mac;
+	struct halmac_api *api;
+	enum halmac_ret_status status;
+	int err = -1;
+
+
+	mac = dvobj_to_halmac(d);
+	api = HALMAC_GET_API(mac);
+
+	status = api->halmac_verify_platform_api(mac);
+	if (status != HALMAC_RET_SUCCESS)
+		goto out;
+
+	status = api->halmac_h2c_lb(mac);
+	if (status != HALMAC_RET_SUCCESS)
+		goto out;
+
+	err = 0;
+out:
+	return err;
+}
+
+static u8 rtw_halmac_txfifo_is_empty(struct dvobj_priv *d)
+{
+	struct halmac_adapter *mac;
+	struct halmac_api *api;
+	enum halmac_ret_status status;
+	u32 chk_num = 10;
+	u8 rst = _FALSE;
+
+
+	mac = dvobj_to_halmac(d);
+	api = HALMAC_GET_API(mac);
+
+	status = api->halmac_txfifo_is_empty(mac, chk_num);
+	if (status == HALMAC_RET_SUCCESS)
+		rst = _TRUE;
+
+	return rst;
+}
+
+/**
+ * rtw_halmac_txfifo_wait_empty() - Wait TX FIFO to be emtpy
+ * @d:		struct dvobj_priv*
+ * @timeout:	time limit of wait, unit is ms
+ *		0 for no limit
+ *
+ * Wait TX FIFO to be emtpy.
+ *
+ * Rteurn 0 for TX FIFO is empty, otherwise not empty.
+ */
+int rtw_halmac_txfifo_wait_empty(struct dvobj_priv *d, u32 timeout)
+{
+	struct _ADAPTER *a;
+	u8 empty = _FALSE;
+	u32 cnt = 0;
+	systime start_time = 0;
+	u32 pass_time; /* ms */
+
+
+	a = dvobj_get_primary_adapter(d);
+	start_time = rtw_get_current_time();
+
+	do {
+		cnt++;
+		empty = rtw_halmac_txfifo_is_empty(d);
+		if (empty == _TRUE)
+			break;
+
+		if (timeout) {
+			pass_time = rtw_get_passing_time_ms(start_time);
+			if (pass_time > timeout)
+				break;
+		}
+		if (RTW_CANNOT_IO(a)) {
+			RTW_WARN("%s: Interrupted by I/O forbiden!\n", __FUNCTION__);
+			break;
+		}
+
+		rtw_msleep_os(2);
+	} while (1);
+
+	if (empty == _FALSE) {
+#ifdef CONFIG_RTW_DEBUG
+		u16 dbg_reg[] = {0x210, 0x230, 0x234, 0x238, 0x23C, 0x240,
+				 0x41A, 0x10FC, 0x10F8, 0x11F4, 0x11F8};
+		u8 i;
+		u32 val;
+
+		if (!RTW_CANNOT_IO(a)) {
+			for (i = 0; i < ARRAY_SIZE(dbg_reg); i++) {
+				val = rtw_read32(a, dbg_reg[i]);
+				RTW_ERR("REG_%X:0x%08x\n", dbg_reg[i], val);
+			}
+		}
+#endif /* CONFIG_RTW_DEBUG */
+
+		RTW_ERR("%s: Fail to wait txfifo empty!(cnt=%d)\n",
+			__FUNCTION__, cnt);
+		return -1;
+	}
+
+	return 0;
+}
+
+static enum halmac_dlfw_mem _fw_mem_drv2halmac(enum fw_mem mem, u8 tx_stop)
+{
+	enum halmac_dlfw_mem mem_halmac = HALMAC_DLFW_MEM_UNDEFINE;
+
+
+	switch (mem) {
+	case FW_EMEM:
+		if (tx_stop == _FALSE)
+			mem_halmac = HALMAC_DLFW_MEM_EMEM_RSVD_PG;
+		else
+			mem_halmac = HALMAC_DLFW_MEM_EMEM;
+		break;
+
+	case FW_IMEM:
+	case FW_DMEM:
+		mem_halmac = HALMAC_DLFW_MEM_UNDEFINE;
+		break;
+	}
+
+	return mem_halmac;
+}
+
+int rtw_halmac_dlfw_mem(struct dvobj_priv *d, u8 *fw, u32 fwsize, enum fw_mem mem)
+{
+	struct halmac_adapter *mac;
+	struct halmac_api *api;
+	enum halmac_ret_status status;
+	enum halmac_dlfw_mem dlfw_mem;
+	u8 tx_stop = _FALSE;
+	u32 chk_timeout = 2000; /* unit: ms */
+	int err = 0;
+
+
+	mac = dvobj_to_halmac(d);
+	api = HALMAC_GET_API(mac);
+
+	if ((!fw) || (!fwsize))
+		return -1;
+
+#ifndef RTW_HALMAC_DLFW_MEM_NO_STOP_TX
+	/* 1. Driver Stop Tx */
+	/* ToDo */
+
+	/* 2. Driver Check Tx FIFO is empty */
+	err = rtw_halmac_txfifo_wait_empty(d, chk_timeout);
+	if (err)
+		tx_stop = _FALSE;
+	else
+		tx_stop = _TRUE;
+#endif /* !RTW_HALMAC_DLFW_MEM_NO_STOP_TX */
+
+	/* 3. Download Firmware MEM */
+	dlfw_mem = _fw_mem_drv2halmac(mem, tx_stop);
+	if (dlfw_mem == HALMAC_DLFW_MEM_UNDEFINE) {
+		err = -1;
+		goto resume_tx;
+	}
+	status = api->halmac_free_download_firmware(mac, dlfw_mem, fw, fwsize);
+	if (status != HALMAC_RET_SUCCESS) {
+		RTW_ERR("%s: halmac_free_download_firmware fail(err=0x%x)\n",
+			__FUNCTION__, status);
+		err = -1;
+		goto resume_tx;
+	}
+
+resume_tx:
+#ifndef RTW_HALMAC_DLFW_MEM_NO_STOP_TX
+	/* 4. Driver resume TX if needed */
+	/* ToDo */
+#endif /* !RTW_HALMAC_DLFW_MEM_NO_STOP_TX */
+
+	return err;
+}
+
+int rtw_halmac_dlfw_mem_from_file(struct dvobj_priv *d, u8 *fwpath, enum fw_mem mem)
+{
+	u8 *fw = NULL;
+	u32 fwmaxsize = 0, size = 0;
+	int err = 0;
+
+
+	err = rtw_halmac_get_fw_max_size(d, &fwmaxsize);
+	if (err) {
+		RTW_ERR("%s: Fail to get Firmware MAX size(err=%d)\n", __FUNCTION__, err);
+		return -1;
+	}
+
+	fw = rtw_zmalloc(fwmaxsize);
+	if (!fw)
+		return -1;
+
+	size = rtw_retrieve_from_file(fwpath, fw, fwmaxsize);
+	if (size)
+		err = rtw_halmac_dlfw_mem(d, fw, size, mem);
+	else
+		err = -1;
+
+	rtw_mfree(fw, fwmaxsize);
+	/*fw = NULL;*/
+
+	return err;
+}
+
+/*
+ * Return:
+ *	0	Success
+ *	-22	Invalid arguemnt
+ */
+int rtw_halmac_dlfw(struct dvobj_priv *d, u8 *fw, u32 fwsize)
+{
+	PADAPTER adapter;
+	enum halmac_ret_status status;
+	u32 ok;
+	int err, err_ret = -1;
+
+
+	if (!fw || !fwsize)
+		return -22;
+
+	adapter = dvobj_get_primary_adapter(d);
+
+	/* re-download firmware */
+	if (rtw_is_hw_init_completed(adapter))
+		return download_fw(d, fw, fwsize, 1);
+
+	/* Download firmware before hal init */
+	/* Power on, download firmware and init mac */
+	ok = rtw_hal_power_on(adapter);
+	if (_FAIL == ok)
+		goto out;
+
+	err = download_fw(d, fw, fwsize, 0);
+	if (err) {
+		err_ret = err;
+		goto out;
+	}
+
+	err = init_mac_flow(d);
+	if (err)
+		goto out;
+
+	err = _send_general_info(d);
+	if (err)
+		goto out;
+
+	err_ret = 0;
+
+out:
+	return err_ret;
+}
+
+int rtw_halmac_dlfw_from_file(struct dvobj_priv *d, u8 *fwpath)
+{
+	u8 *fw = NULL;
+	u32 fwmaxsize = 0, size = 0;
+	int err = 0;
+
+
+	err = rtw_halmac_get_fw_max_size(d, &fwmaxsize);
+	if (err) {
+		RTW_ERR("%s: Fail to get Firmware MAX size(err=%d)\n", __FUNCTION__, err);
+		return -1;
+	}
+
+	fw = rtw_zmalloc(fwmaxsize);
+	if (!fw)
+		return -1;
+
+	size = rtw_retrieve_from_file(fwpath, fw, fwmaxsize);
+	if (size)
+		err = rtw_halmac_dlfw(d, fw, size);
+	else
+		err = -1;
+
+	rtw_mfree(fw, fwmaxsize);
+	/*fw = NULL;*/
+
+	return err;
+}
+
+/*
+ * Description:
+ *	Power on/off BB/RF domain.
+ *
+ * Parameters:
+ *	enable	_TRUE/_FALSE for power on/off
+ *
+ * Return:
+ *	0	Success
+ *	others	Fail
+ */
+int rtw_halmac_phy_power_switch(struct dvobj_priv *d, u8 enable)
+{
+	PADAPTER adapter;
+	struct halmac_adapter *halmac;
+	struct halmac_api *api;
+	enum halmac_ret_status status;
+	u8 on;
+
+
+	adapter = dvobj_get_primary_adapter(d);
+	halmac = dvobj_to_halmac(d);
+	if (!halmac)
+		return -1;
+	api = HALMAC_GET_API(halmac);
+	on = (enable == _TRUE) ? 1 : 0;
+
+	status = api->halmac_set_hw_value(halmac, HALMAC_HW_EN_BB_RF, &on);
+	if (status != HALMAC_RET_SUCCESS)
+		return -1;
+
+	return 0;
+}
+
+static u8 _is_fw_read_cmd_down(PADAPTER adapter, u8 msgbox_num)
+{
+	u8 read_down = _FALSE;
+	int retry_cnts = 100;
+	u8 valid;
+
+	do {
+		valid = rtw_read8(adapter, REG_HMETFR) & BIT(msgbox_num);
+		if (0 == valid)
+			read_down = _TRUE;
+		else
+			rtw_msleep_os(1);
+	} while ((!read_down) && (retry_cnts--));
+
+	if (_FALSE == read_down)
+		RTW_WARN("%s, reg_1cc(%x), msg_box(%d)...\n", __func__, rtw_read8(adapter, REG_HMETFR), msgbox_num);
+
+	return read_down;
+}
+
+/**
+ * rtw_halmac_send_h2c() - Send H2C to firmware
+ * @d:		struct dvobj_priv*
+ * @h2c:	H2C data buffer, suppose to be 8 bytes
+ *
+ * Send H2C to firmware by message box register(0x1D0~0x1D3 & 0x1F0~0x1F3).
+ *
+ * Assume firmware be ready to accept H2C here, please check
+ * (hal->bFWReady == _TRUE) before call this function or make sure firmware is
+ * ready.
+ *
+ * Return: 0 if process OK, otherwise fail to send this H2C.
+ */
+int rtw_halmac_send_h2c(struct dvobj_priv *d, u8 *h2c)
+{
+	PADAPTER adapter = dvobj_get_primary_adapter(d);
+	PHAL_DATA_TYPE hal = GET_HAL_DATA(adapter);
+	u8 h2c_box_num = 0;
+	u32 msgbox_addr = 0;
+	u32 msgbox_ex_addr = 0;
+	u32 h2c_cmd = 0;
+	u32 h2c_cmd_ex = 0;
+	int err = -1;
+
+
+	if (!h2c) {
+		RTW_WARN("%s: pbuf is NULL\n", __FUNCTION__);
+		return err;
+	}
+
+	if (rtw_is_surprise_removed(adapter)) {
+		RTW_WARN("%s: surprise removed\n", __FUNCTION__);
+		return err;
+	}
+
+	_enter_critical_mutex(&d->h2c_fwcmd_mutex, NULL);
+
+	/* pay attention to if race condition happened in H2C cmd setting */
+	h2c_box_num = hal->LastHMEBoxNum;
+
+	if (!_is_fw_read_cmd_down(adapter, h2c_box_num)) {
+		RTW_WARN(" fw read cmd failed...\n");
+#ifdef DBG_CONFIG_ERROR_DETECT
+		hal->srestpriv.self_dect_fw = _TRUE;
+		hal->srestpriv.self_dect_fw_cnt++;
+#endif /* DBG_CONFIG_ERROR_DETECT */
+		goto exit;
+	}
+
+	/* Write Ext command (byte 4~7) */
+	msgbox_ex_addr = REG_HMEBOX_E0 + (h2c_box_num * EX_MESSAGE_BOX_SIZE);
+	_rtw_memcpy((u8 *)(&h2c_cmd_ex), h2c + 4, EX_MESSAGE_BOX_SIZE);
+	h2c_cmd_ex = le32_to_cpu(h2c_cmd_ex);
+	rtw_write32(adapter, msgbox_ex_addr, h2c_cmd_ex);
+
+	/* Write command (byte 0~3) */
+	msgbox_addr = REG_HMEBOX0 + (h2c_box_num * MESSAGE_BOX_SIZE);
+	_rtw_memcpy((u8 *)(&h2c_cmd), h2c, 4);
+	h2c_cmd = le32_to_cpu(h2c_cmd);
+	rtw_write32(adapter, msgbox_addr, h2c_cmd);
+
+	/* update last msg box number */
+	hal->LastHMEBoxNum = (h2c_box_num + 1) % MAX_H2C_BOX_NUMS;
+	err = 0;
+
+#ifdef DBG_H2C_CONTENT
+	RTW_INFO_DUMP("[H2C] - ", h2c, RTW_HALMAC_H2C_MAX_SIZE);
+#endif
+exit:
+	_exit_critical_mutex(&d->h2c_fwcmd_mutex, NULL);
+	return err;
+}
+
+/**
+ * rtw_halmac_c2h_handle() - Handle C2H for HALMAC
+ * @d:		struct dvobj_priv*
+ * @c2h:	Full C2H packet, including RX description and payload
+ * @size:	Size(byte) of c2h
+ *
+ * Send C2H packet to HALMAC to process C2H packets, and the expected C2H ID is
+ * 0xFF. This function won't have any I/O, so caller doesn't have to call it in
+ * I/O safe place(ex. command thread).
+ *
+ * Please sure doesn't call this function in the same thread as someone is
+ * waiting HALMAC C2H ack, otherwise there is a deadlock happen.
+ *
+ * Return: 0 if process OK, otherwise no action for this C2H.
+ */
+int rtw_halmac_c2h_handle(struct dvobj_priv *d, u8 *c2h, u32 size)
+{
+	struct halmac_adapter *mac;
+	struct halmac_api *api;
+	enum halmac_ret_status status;
+
+
+	mac = dvobj_to_halmac(d);
+	api = HALMAC_GET_API(mac);
+
+	status = api->halmac_get_c2h_info(mac, c2h, size);
+	if (HALMAC_RET_SUCCESS != status)
+		return -1;
+
+	return 0;
+}
+
+int rtw_halmac_get_available_efuse_size(struct dvobj_priv *d, u32 *size)
+{
+	struct halmac_adapter *mac;
+	struct halmac_api *api;
+	enum halmac_ret_status status;
+	u32 val;
+
+
+	mac = dvobj_to_halmac(d);
+	api = HALMAC_GET_API(mac);
+
+	status = api->halmac_get_efuse_available_size(mac, &val);
+	if (HALMAC_RET_SUCCESS != status)
+		return -1;
+
+	*size = val;
+	return 0;
+}
+
+int rtw_halmac_get_physical_efuse_size(struct dvobj_priv *d, u32 *size)
+{
+	struct halmac_adapter *mac;
+	struct halmac_api *api;
+	enum halmac_ret_status status;
+	u32 val;
+
+
+	mac = dvobj_to_halmac(d);
+	api = HALMAC_GET_API(mac);
+
+	status = api->halmac_get_efuse_size(mac, &val);
+	if (HALMAC_RET_SUCCESS != status)
+		return -1;
+
+	*size = val;
+	return 0;
+}
+
+int rtw_halmac_read_physical_efuse_map(struct dvobj_priv *d, u8 *map, u32 size)
+{
+	struct halmac_adapter *mac;
+	struct halmac_api *api;
+	enum halmac_ret_status status;
+	enum halmac_feature_id id;
+	int ret;
+
+
+	mac = dvobj_to_halmac(d);
+	api = HALMAC_GET_API(mac);
+	id = HALMAC_FEATURE_DUMP_PHYSICAL_EFUSE;
+
+	ret = init_halmac_event(d, id, map, size);
+	if (ret)
+		return -1;
+
+	status = api->halmac_dump_efuse_map(mac, HALMAC_EFUSE_R_DRV);
+	if (HALMAC_RET_SUCCESS != status) {
+		free_halmac_event(d, id);
+		return -1;
+	}
+
+	ret = wait_halmac_event(d, id);
+	if (ret)
+		return -1;
+
+	return 0;
+}
+
+int rtw_halmac_read_physical_efuse(struct dvobj_priv *d, u32 offset, u32 cnt, u8 *data)
+{
+	struct halmac_adapter *mac;
+	struct halmac_api *api;
+	enum halmac_ret_status status;
+	u8 v;
+	u32 i;
+	u8 *efuse = NULL;
+	u32 size = 0;
+	int err = 0;
+
+
+	mac = dvobj_to_halmac(d);
+	api = HALMAC_GET_API(mac);
+
+	if (api->halmac_read_efuse) {
+		for (i = 0; i < cnt; i++) {
+			status = api->halmac_read_efuse(mac, offset + i, &v);
+			if (HALMAC_RET_SUCCESS != status)
+				return -1;
+			data[i] = v;
+		}
+	} else {
+		err = rtw_halmac_get_physical_efuse_size(d, &size);
+		if (err)
+			return -1;
+
+		efuse = rtw_zmalloc(size);
+		if (!efuse)
+			return -1;
+
+		err = rtw_halmac_read_physical_efuse_map(d, efuse, size);
+		if (err)
+			err = -1;
+		else
+			_rtw_memcpy(data, efuse + offset, cnt);
+
+		rtw_mfree(efuse, size);
+	}
+
+	return err;
+}
+
+int rtw_halmac_write_physical_efuse(struct dvobj_priv *d, u32 offset, u32 cnt, u8 *data)
+{
+	struct halmac_adapter *mac;
+	struct halmac_api *api;
+	enum halmac_ret_status status;
+	u32 i;
+
+
+	mac = dvobj_to_halmac(d);
+	api = HALMAC_GET_API(mac);
+
+	if (api->halmac_write_efuse == NULL)
+		return -1;
+
+	for (i = 0; i < cnt; i++) {
+		status = api->halmac_write_efuse(mac, offset + i, data[i]);
+		if (HALMAC_RET_SUCCESS != status)
+			return -1;
+	}
+
+	return 0;
+}
+
+int rtw_halmac_get_logical_efuse_size(struct dvobj_priv *d, u32 *size)
+{
+	struct halmac_adapter *mac;
+	struct halmac_api *api;
+	enum halmac_ret_status status;
+	u32 val;
+
+
+	mac = dvobj_to_halmac(d);
+	api = HALMAC_GET_API(mac);
+
+	status = api->halmac_get_logical_efuse_size(mac, &val);
+	if (HALMAC_RET_SUCCESS != status)
+		return -1;
+
+	*size = val;
+	return 0;
+}
+
+int rtw_halmac_read_logical_efuse_map(struct dvobj_priv *d, u8 *map, u32 size, u8 *maskmap, u32 masksize)
+{
+	struct halmac_adapter *mac;
+	struct halmac_api *api;
+	enum halmac_ret_status status;
+	enum halmac_feature_id id;
+	int ret;
+
+
+	mac = dvobj_to_halmac(d);
+	api = HALMAC_GET_API(mac);
+	id = HALMAC_FEATURE_DUMP_LOGICAL_EFUSE;
+
+	ret = init_halmac_event(d, id, map, size);
+	if (ret)
+		return -1;
+
+	status = api->halmac_dump_logical_efuse_map(mac, HALMAC_EFUSE_R_DRV);
+	if (HALMAC_RET_SUCCESS != status) {
+		free_halmac_event(d, id);
+		return -1;
+	}
+
+	ret = wait_halmac_event(d, id);
+	if (ret)
+		return -1;
+
+	if (maskmap && masksize) {
+		struct halmac_pg_efuse_info pginfo;
+
+		pginfo.efuse_map = map;
+		pginfo.efuse_map_size = size;
+		pginfo.efuse_mask = maskmap;
+		pginfo.efuse_mask_size = masksize;
+
+		status = api->halmac_mask_logical_efuse(mac, &pginfo);
+		if (status != HALMAC_RET_SUCCESS)
+			RTW_WARN("%s: mask logical efuse FAIL!\n", __FUNCTION__);
+	}
+
+	return 0;
+}
+
+int rtw_halmac_write_logical_efuse_map(struct dvobj_priv *d, u8 *map, u32 size, u8 *maskmap, u32 masksize)
+{
+	struct halmac_adapter *mac;
+	struct halmac_api *api;
+	struct halmac_pg_efuse_info pginfo;
+	enum halmac_ret_status status;
+
+
+	mac = dvobj_to_halmac(d);
+	api = HALMAC_GET_API(mac);
+
+	pginfo.efuse_map = map;
+	pginfo.efuse_map_size = size;
+	pginfo.efuse_mask = maskmap;
+	pginfo.efuse_mask_size = masksize;
+
+	status = api->halmac_pg_efuse_by_map(mac, &pginfo, HALMAC_EFUSE_R_AUTO);
+	if (HALMAC_RET_SUCCESS != status)
+		return -1;
+
+	return 0;
+}
+
+int rtw_halmac_read_logical_efuse(struct dvobj_priv *d, u32 offset, u32 cnt, u8 *data)
+{
+	struct halmac_adapter *mac;
+	struct halmac_api *api;
+	enum halmac_ret_status status;
+	u8 v;
+	u32 i;
+
+
+	mac = dvobj_to_halmac(d);
+	api = HALMAC_GET_API(mac);
+
+	for (i = 0; i < cnt; i++) {
+		status = api->halmac_read_logical_efuse(mac, offset + i, &v);
+		if (HALMAC_RET_SUCCESS != status)
+			return -1;
+		data[i] = v;
+	}
+
+	return 0;
+}
+
+int rtw_halmac_write_logical_efuse(struct dvobj_priv *d, u32 offset, u32 cnt, u8 *data)
+{
+	struct halmac_adapter *mac;
+	struct halmac_api *api;
+	enum halmac_ret_status status;
+	u32 i;
+
+
+	mac = dvobj_to_halmac(d);
+	api = HALMAC_GET_API(mac);
+
+	for (i = 0; i < cnt; i++) {
+		status = api->halmac_write_logical_efuse(mac, offset + i, data[i]);
+		if (HALMAC_RET_SUCCESS != status)
+			return -1;
+	}
+
+	return 0;
+}
+
+int rtw_halmac_write_bt_physical_efuse(struct dvobj_priv *d, u32 offset, u32 cnt, u8 *data)
+{
+	struct halmac_adapter *mac;
+	struct halmac_api *api;
+	enum halmac_ret_status status;
+	u32 i;
+	u8 bank = 1;
+
+
+	mac = dvobj_to_halmac(d);
+	api = HALMAC_GET_API(mac);
+
+	for (i = 0; i < cnt; i++) {
+		status = api->halmac_write_efuse_bt(mac, offset + i, data[i], bank);
+		if (HALMAC_RET_SUCCESS != status) {
+			printk("%s: halmac_write_efuse_bt status = %d\n", __FUNCTION__, status);
+			return -1;
+		}
+	}
+	printk("%s: halmac_write_efuse_bt status = HALMAC_RET_SUCCESS %d\n", __FUNCTION__, status);
+	return 0;
+}
+
+
+int rtw_halmac_read_bt_physical_efuse_map(struct dvobj_priv *d, u8 *map, u32 size)
+{
+	struct halmac_adapter *mac;
+	struct halmac_api *api;
+	enum halmac_ret_status status;
+	int bank = 1;
+
+
+	mac = dvobj_to_halmac(d);
+	api = HALMAC_GET_API(mac);
+
+	status = api->halmac_dump_efuse_map_bt(mac, bank, size, map);
+	if (HALMAC_RET_SUCCESS != status) {
+		printk("%s: halmac_dump_efuse_map_bt fail!\n", __FUNCTION__);
+		return -1;
+	}
+
+	printk("%s: OK!\n", __FUNCTION__);
+
+	return 0;
+}
+
+static enum hal_fifo_sel _fifo_sel_drv2halmac(u8 fifo_sel)
+{
+	switch (fifo_sel) {
+	case 0:
+		return HAL_FIFO_SEL_TX;
+	case 1:
+		return HAL_FIFO_SEL_RX;
+	case 2:
+		return HAL_FIFO_SEL_RSVD_PAGE;
+	case 3:
+		return HAL_FIFO_SEL_REPORT;
+	case 4:
+		return HAL_FIFO_SEL_LLT;
+	case 5:
+		return HAL_FIFO_SEL_RXBUF_FW;
+	}
+
+	return HAL_FIFO_SEL_RSVD_PAGE;
+}
+
+/*#define CONFIG_HALMAC_FIFO_DUMP*/
+int rtw_halmac_dump_fifo(struct dvobj_priv *d, u8 fifo_sel, u32 addr, u32 size, u8 *buffer)
+{
+	struct halmac_adapter *mac;
+	struct halmac_api *api;
+	enum hal_fifo_sel halmac_fifo_sel;
+	enum halmac_ret_status status;
+	u8 *pfifo_map = NULL;
+	u32 fifo_size = 0;
+	s8 ret = 0;/* 0:success, -1:error */
+	u8 mem_created = _FALSE;
+
+
+	mac = dvobj_to_halmac(d);
+	api = HALMAC_GET_API(mac);
+
+	if ((size != 0) && (buffer == NULL))
+		return -1;
+
+	halmac_fifo_sel = _fifo_sel_drv2halmac(fifo_sel);
+
+	if ((size) && (buffer)) {
+		pfifo_map = buffer;
+		fifo_size = size;
+	} else {
+		fifo_size = api->halmac_get_fifo_size(mac, halmac_fifo_sel);
+
+		if (fifo_size)
+			pfifo_map = rtw_zvmalloc(fifo_size);
+		if (pfifo_map == NULL)
+			return -1;
+		mem_created = _TRUE;
+	}
+
+	status = api->halmac_dump_fifo(mac, halmac_fifo_sel, addr, fifo_size, pfifo_map);
+	if (HALMAC_RET_SUCCESS != status) {
+		ret = -1;
+		goto _exit;
+	}
+
+#ifdef CONFIG_HALMAC_FIFO_DUMP
+	{
+		static const char * const fifo_sel_str[] = {
+			"TX", "RX", "RSVD_PAGE", "REPORT", "LLT", "RXBUF_FW"
+		};
+
+		RTW_INFO("%s FIFO DUMP [start_addr:0x%04x , size:%d]\n", fifo_sel_str[halmac_fifo_sel], addr, fifo_size);
+		RTW_INFO_DUMP("\n", pfifo_map, fifo_size);
+		RTW_INFO(" ==================================================\n");
+	}
+#endif /* CONFIG_HALMAC_FIFO_DUMP */
+
+_exit:
+	if ((mem_created == _TRUE) && pfifo_map)
+		rtw_vmfree(pfifo_map, fifo_size);
+
+	return ret;
+}
+
+/*
+ * rtw_halmac_rx_agg_switch() - Switch RX aggregation function and setting
+ * @d		struct dvobj_priv *
+ * @enable	_FALSE/_TRUE for disable/enable RX aggregation function
+ *
+ * This function could help to on/off bus RX aggregation function, and is only
+ * useful for SDIO and USB interface. Although only "enable" flag is brough in,
+ * some setting would be taken from other places, and they are from:
+ * [DMA aggregation]
+ *	struct hal_com_data.rxagg_dma_size
+ *	struct hal_com_data.rxagg_dma_timeout
+ * [USB aggregation] (only use for USB interface)
+ *	struct hal_com_data.rxagg_usb_size
+ *	struct hal_com_data.rxagg_usb_timeout
+ * If above values of size and timeout are both 0 means driver would not
+ * control the threshold setting and leave it to HALMAC handle.
+ *
+ * From HALMAC V1_04_04, driver force the size threshold be hard limit, and the
+ * rx size can not exceed the setting.
+ *
+ * Return 0 for success, otherwise fail.
+ */
+int rtw_halmac_rx_agg_switch(struct dvobj_priv *d, u8 enable)
+{
+	struct _ADAPTER *adapter;
+	struct hal_com_data *hal;
+	struct halmac_adapter *halmac;
+	struct halmac_api *api;
+	struct halmac_rxagg_cfg rxaggcfg;
+	enum halmac_ret_status status;
+
+
+	adapter = dvobj_get_primary_adapter(d);
+	hal = GET_HAL_DATA(adapter);
+	halmac = dvobj_to_halmac(d);
+	api = HALMAC_GET_API(halmac);
+	_rtw_memset((void *)&rxaggcfg, 0, sizeof(rxaggcfg));
+	rxaggcfg.mode = HALMAC_RX_AGG_MODE_NONE;
+	/*
+	 * Always enable size limit to avoid rx size exceed
+	 * driver defined size.
+	 */
+	rxaggcfg.threshold.size_limit_en = 1;
+
+#ifdef RTW_RX_AGGREGATION
+	if (_TRUE == enable) {
+#ifdef CONFIG_SDIO_HCI
+		rxaggcfg.mode = HALMAC_RX_AGG_MODE_DMA;
+		rxaggcfg.threshold.drv_define = 0;
+		if (hal->rxagg_dma_size || hal->rxagg_dma_timeout) {
+			rxaggcfg.threshold.drv_define = 1;
+			rxaggcfg.threshold.timeout = hal->rxagg_dma_timeout;
+			rxaggcfg.threshold.size = hal->rxagg_dma_size;
+			RTW_INFO("%s: RX aggregation threshold: "
+				 "timeout=%u size=%u\n",
+				 __FUNCTION__,
+				 hal->rxagg_dma_timeout,
+				 hal->rxagg_dma_size);
+		}
+#elif defined(CONFIG_USB_HCI)
+		switch (hal->rxagg_mode) {
+		case RX_AGG_DISABLE:
+			rxaggcfg.mode = HALMAC_RX_AGG_MODE_NONE;
+			break;
+
+		case RX_AGG_DMA:
+			rxaggcfg.mode = HALMAC_RX_AGG_MODE_DMA;
+			if (hal->rxagg_dma_size || hal->rxagg_dma_timeout) {
+				rxaggcfg.threshold.drv_define = 1;
+				rxaggcfg.threshold.timeout = hal->rxagg_dma_timeout;
+				rxaggcfg.threshold.size = hal->rxagg_dma_size;
+			}
+			break;
+
+		case RX_AGG_USB:
+		case RX_AGG_MIX:
+			rxaggcfg.mode = HALMAC_RX_AGG_MODE_USB;
+			if (hal->rxagg_usb_size || hal->rxagg_usb_timeout) {
+				rxaggcfg.threshold.drv_define = 1;
+				rxaggcfg.threshold.timeout = hal->rxagg_usb_timeout;
+				rxaggcfg.threshold.size = hal->rxagg_usb_size;
+			}
+			break;
+		}
+#endif /* CONFIG_USB_HCI */
+	}
+#endif /* RTW_RX_AGGREGATION */
+
+	status = api->halmac_cfg_rx_aggregation(halmac, &rxaggcfg);
+	if (status != HALMAC_RET_SUCCESS)
+		return -1;
+
+	return 0;
+}
+
+int rtw_halmac_download_rsvd_page(struct dvobj_priv *dvobj, u8 pg_offset, u8 *pbuf, u32 size)
+{
+	enum halmac_ret_status status = HALMAC_RET_SUCCESS;
+	struct halmac_adapter *halmac = dvobj_to_halmac(dvobj);
+	struct halmac_api *api = HALMAC_GET_API(halmac);
+
+	status = api->halmac_dl_drv_rsvd_page(halmac, pg_offset, pbuf, size);
+	if (status != HALMAC_RET_SUCCESS)
+		return -1;
+
+	return 0;
+}
+
+/*
+ * Description
+ *	Fill following spec info from HALMAC API:
+ *	sec_cam_ent_num
+ *
+ * Return
+ *	0	Success
+ *	others	Fail
+ */
+int rtw_halmac_fill_hal_spec(struct dvobj_priv *dvobj, struct hal_spec_t *spec)
+{
+	enum halmac_ret_status status;
+	struct halmac_adapter *halmac;
+	struct halmac_api *api;
+	u8 cam = 0;	/* Security Cam Entry Number */
+
+
+	halmac = dvobj_to_halmac(dvobj);
+	api = HALMAC_GET_API(halmac);
+
+	/* Prepare data from HALMAC */
+	status = api->halmac_get_hw_value(halmac, HALMAC_HW_CAM_ENTRY_NUM, &cam);
+	if (status != HALMAC_RET_SUCCESS)
+		return -1;
+
+	/* Fill data to hal_spec_t */
+	spec->sec_cam_ent_num = cam;
+
+	return 0;
+}
+
+int rtw_halmac_p2pps(struct dvobj_priv *dvobj, struct hal_p2p_ps_para *pp2p_ps_para)
+{
+	enum halmac_ret_status status = HALMAC_RET_SUCCESS;
+	struct halmac_adapter *halmac = dvobj_to_halmac(dvobj);
+	struct halmac_api *api = HALMAC_GET_API(halmac);
+	struct halmac_p2pps halmac_p2p_ps;
+
+	(&halmac_p2p_ps)->offload_en = pp2p_ps_para->offload_en;
+	(&halmac_p2p_ps)->role = pp2p_ps_para->role;
+	(&halmac_p2p_ps)->ctwindow_en = pp2p_ps_para->ctwindow_en;
+	(&halmac_p2p_ps)->noa_en = pp2p_ps_para->noa_en;
+	(&halmac_p2p_ps)->noa_sel = pp2p_ps_para->noa_sel;
+	(&halmac_p2p_ps)->all_sta_sleep = pp2p_ps_para->all_sta_sleep;
+	(&halmac_p2p_ps)->discovery = pp2p_ps_para->discovery;
+	(&halmac_p2p_ps)->p2p_port_id = _hw_port_drv2halmac(pp2p_ps_para->p2p_port_id);
+	(&halmac_p2p_ps)->p2p_group = pp2p_ps_para->p2p_group;
+	(&halmac_p2p_ps)->p2p_macid = pp2p_ps_para->p2p_macid;
+	(&halmac_p2p_ps)->ctwindow_length = pp2p_ps_para->ctwindow_length;
+	(&halmac_p2p_ps)->noa_duration_para = pp2p_ps_para->noa_duration_para;
+	(&halmac_p2p_ps)->noa_interval_para = pp2p_ps_para->noa_interval_para;
+	(&halmac_p2p_ps)->noa_start_time_para = pp2p_ps_para->noa_start_time_para;
+	(&halmac_p2p_ps)->noa_count_para = pp2p_ps_para->noa_count_para;
+
+	status = api->halmac_p2pps(halmac, (&halmac_p2p_ps));
+	if (status != HALMAC_RET_SUCCESS)
+		return -1;
+
+	return 0;
+
+}
+
+/**
+ * rtw_halmac_iqk() - Run IQ Calibration
+ * @d:		struct dvobj_priv*
+ * @clear:	IQK parameters
+ * @segment:	IQK parameters
+ *
+ * Process IQ Calibration(IQK).
+ *
+ * Rteurn: 0 for OK, otherwise fail.
+ */
+int rtw_halmac_iqk(struct dvobj_priv *d, u8 clear, u8 segment)
+{
+	struct halmac_adapter *mac;
+	struct halmac_api *api;
+	enum halmac_ret_status status;
+	enum halmac_feature_id id;
+	struct halmac_iqk_para para;
+	int ret;
+	u8 retry = 3;
+	u8 delay = 1; /* ms */
+
+
+	mac = dvobj_to_halmac(d);
+	api = HALMAC_GET_API(mac);
+	id = HALMAC_FEATURE_IQK;
+
+	ret = init_halmac_event(d, id, NULL, 0);
+	if (ret)
+		return -1;
+
+	para.clear = clear;
+	para.segment_iqk = segment;
+
+	do {
+		status = api->halmac_start_iqk(mac, &para);
+		if (status != HALMAC_RET_BUSY_STATE)
+			break;
+		RTW_WARN("%s: Fail to start IQK, status is BUSY! retry=%d\n", __FUNCTION__, retry);
+		if (!retry)
+			break;
+		retry--;
+		rtw_msleep_os(delay);
+	} while (1);
+	if (status != HALMAC_RET_SUCCESS) {
+		free_halmac_event(d, id);
+		return -1;
+	}
+
+	ret = wait_halmac_event(d, id);
+	if (ret)
+		return -1;
+
+	return 0;
+}
+
+static inline u32 _phy_parameter_val_drv2halmac(u32 val, u8 msk_en, u32 msk)
+{
+	if (!msk_en)
+		return val;
+
+	return (val << bitshift(msk));
+}
+
+static int _phy_parameter_drv2halmac(struct rtw_phy_parameter *para, struct halmac_phy_parameter_info *info)
+{
+	if (!para || !info)
+		return -1;
+
+	_rtw_memset(info, 0, sizeof(*info));
+
+	switch (para->cmd) {
+	case 0:
+		/* MAC register */
+		switch (para->data.mac.size) {
+		case 1:
+			info->cmd_id = HALMAC_PARAMETER_CMD_MAC_W8;
+			break;
+		case 2:
+			info->cmd_id = HALMAC_PARAMETER_CMD_MAC_W16;
+			break;
+		default:
+			info->cmd_id = HALMAC_PARAMETER_CMD_MAC_W32;
+			break;
+		}
+		info->content.MAC_REG_W.value = _phy_parameter_val_drv2halmac(
+							para->data.mac.value,
+							para->data.mac.msk_en,
+							para->data.mac.msk);
+		info->content.MAC_REG_W.msk = para->data.mac.msk;
+		info->content.MAC_REG_W.offset = para->data.mac.offset;
+		info->content.MAC_REG_W.msk_en = para->data.mac.msk_en;
+		break;
+
+	case 1:
+		/* BB register */
+		switch (para->data.bb.size) {
+		case 1:
+			info->cmd_id = HALMAC_PARAMETER_CMD_BB_W8;
+			break;
+		case 2:
+			info->cmd_id = HALMAC_PARAMETER_CMD_BB_W16;
+			break;
+		default:
+			info->cmd_id = HALMAC_PARAMETER_CMD_BB_W32;
+			break;
+		}
+		info->content.BB_REG_W.value = _phy_parameter_val_drv2halmac(
+							para->data.bb.value,
+							para->data.bb.msk_en,
+							para->data.bb.msk);
+		info->content.BB_REG_W.msk = para->data.bb.msk;
+		info->content.BB_REG_W.offset = para->data.bb.offset;
+		info->content.BB_REG_W.msk_en = para->data.bb.msk_en;
+		break;
+
+	case 2:
+		/* RF register */
+		info->cmd_id = HALMAC_PARAMETER_CMD_RF_W;
+		info->content.RF_REG_W.value = _phy_parameter_val_drv2halmac(
+							para->data.rf.value,
+							para->data.rf.msk_en,
+							para->data.rf.msk);
+		info->content.RF_REG_W.msk = para->data.rf.msk;
+		info->content.RF_REG_W.offset = para->data.rf.offset;
+		info->content.RF_REG_W.msk_en = para->data.rf.msk_en;
+		info->content.RF_REG_W.rf_path = para->data.rf.path;
+		break;
+
+	case 3:
+		/* Delay register */
+		if (para->data.delay.unit == 0)
+			info->cmd_id = HALMAC_PARAMETER_CMD_DELAY_US;
+		else
+			info->cmd_id = HALMAC_PARAMETER_CMD_DELAY_MS;
+		info->content.DELAY_TIME.delay_time = para->data.delay.value;
+		break;
+
+	case 0xFF:
+		/* Latest(End) command */
+		info->cmd_id = HALMAC_PARAMETER_CMD_END;
+		break;
+
+	default:
+		return -1;
+	}
+
+	return 0;
+}
+
+/**
+ * rtw_halmac_cfg_phy_para() - Register(Phy parameter) configuration
+ * @d:		struct dvobj_priv*
+ * @para:	phy parameter
+ *
+ * Configure registers by firmware using H2C/C2H mechanism.
+ * The latest command should be para->cmd==0xFF(End command) to finish all
+ * processes.
+ *
+ * Return: 0 for OK, otherwise fail.
+ */
+int rtw_halmac_cfg_phy_para(struct dvobj_priv *d, struct rtw_phy_parameter *para)
+{
+	struct halmac_adapter *mac;
+	struct halmac_api *api;
+	enum halmac_ret_status status;
+	enum halmac_feature_id id;
+	struct halmac_phy_parameter_info info;
+	u8 full_fifo;
+	int err, ret;
+
+
+	mac = dvobj_to_halmac(d);
+	api = HALMAC_GET_API(mac);
+	id = HALMAC_FEATURE_CFG_PARA;
+	full_fifo = 1; /* ToDo: How to deciede? */
+	ret = 0;
+
+	err = _phy_parameter_drv2halmac(para, &info);
+	if (err)
+		return -1;
+
+	err = init_halmac_event(d, id, NULL, 0);
+	if (err)
+		return -1;
+
+	status = api->halmac_cfg_parameter(mac, &info, full_fifo);
+	if (info.cmd_id == HALMAC_PARAMETER_CMD_END) {
+		if (status == HALMAC_RET_SUCCESS) {
+			err = wait_halmac_event(d, id);
+			if (err)
+				ret = -1;
+		} else {
+			free_halmac_event(d, id);
+			ret = -1;
+			RTW_ERR("%s: Fail to send END of cfg parameter, status is 0x%x!\n", __FUNCTION__, status);
+		}
+	} else {
+		if (status == HALMAC_RET_PARA_SENDING) {
+			err = wait_halmac_event(d, id);
+			if (err)
+				ret = -1;
+		} else {
+			free_halmac_event(d, id);
+			if (status != HALMAC_RET_SUCCESS) {
+				ret = -1;
+				RTW_ERR("%s: Fail to cfg parameter, status is 0x%x!\n", __FUNCTION__, status);
+			}
+		}
+	}
+
+	return ret;
+}
+
+static enum halmac_wlled_mode _led_mode_drv2halmac(u8 drv_mode)
+{
+	enum halmac_wlled_mode halmac_mode;
+
+
+	switch (drv_mode) {
+	case 1:
+		halmac_mode = HALMAC_WLLED_MODE_TX;
+		break;
+	case 2:
+		halmac_mode = HALMAC_WLLED_MODE_RX;
+		break;
+	case 3:
+		halmac_mode = HALMAC_WLLED_MODE_SW_CTRL;
+		break;
+	case 0:
+	default:
+		halmac_mode = HALMAC_WLLED_MODE_TRX;
+		break;
+	}
+
+	return halmac_mode;
+}
+
+/**
+ * rtw_halmac_led_cfg() - Configure Hardware LED Mode
+ * @d:		struct dvobj_priv*
+ * @enable:	enable or disable LED function
+ *		0: disable
+ *		1: enable
+ * @mode:	WLan LED mode (valid when enable==1)
+ *		0: Blink when TX(transmit packet) and RX(receive packet)
+ *		1: Blink when TX only
+ *		2: Blink when RX only
+ *		3: Software control
+ *
+ * Configure hardware WLan LED mode.
+ * If want to change LED mode after enabled, need to disable LED first and
+ * enable again to set new mode.
+ *
+ * Rteurn 0 for OK, otherwise fail.
+ */
+int rtw_halmac_led_cfg(struct dvobj_priv *d, u8 enable, u8 mode)
+{
+	struct halmac_adapter *halmac;
+	struct halmac_api *api;
+	enum halmac_wlled_mode led_mode;
+	enum halmac_ret_status status;
+
+
+	halmac = dvobj_to_halmac(d);
+	api = HALMAC_GET_API(halmac);
+
+	if (enable) {
+		status = api->halmac_pinmux_set_func(halmac,
+						     HALMAC_GPIO_FUNC_WL_LED);
+		if (status != HALMAC_RET_SUCCESS) {
+			RTW_ERR("%s: pinmux set fail!(0x%x)\n",
+				__FUNCTION__, status);
+			return -1;
+		}
+
+		led_mode = _led_mode_drv2halmac(mode);
+		status = api->halmac_pinmux_wl_led_mode(halmac, led_mode);
+		if (status != HALMAC_RET_SUCCESS) {
+			RTW_ERR("%s: mode set fail!(0x%x)\n",
+				__FUNCTION__, status);
+			return -1;
+		}
+	} else {
+		/* Change LED to software control and turn off */
+		api->halmac_pinmux_wl_led_mode(halmac,
+					       HALMAC_WLLED_MODE_SW_CTRL);
+		api->halmac_pinmux_wl_led_sw_ctrl(halmac, 0);
+
+		status = api->halmac_pinmux_free_func(halmac,
+						      HALMAC_GPIO_FUNC_WL_LED);
+		if (status != HALMAC_RET_SUCCESS) {
+			RTW_ERR("%s: pinmux free fail!(0x%x)\n",
+				__FUNCTION__, status);
+			return -1;
+		}
+	}
+
+	return 0;
+}
+
+/**
+ * rtw_halmac_led_switch() - Turn Hardware LED on/off
+ * @d:		struct dvobj_priv*
+ * @on:		LED light or not
+ *		0: Off
+ *		1: On(Light)
+ *
+ * Turn Hardware WLan LED On/Off.
+ * Before use this function, user should call rtw_halmac_led_ctrl() to switch
+ * mode to "software control(3)" first, otherwise control would fail.
+ * The interval between on and off must be longer than 1 ms, or the LED would
+ * keep light or dark only.
+ * Ex. Turn off LED at first, turn on after 0.5ms and turn off again after
+ * 0.5ms. The LED during this flow will only keep dark, and miss the turn on
+ * operation between two turn off operations.
+ */
+void rtw_halmac_led_switch(struct dvobj_priv *d, u8 on)
+{
+	struct halmac_adapter *halmac;
+	struct halmac_api *api;
+
+
+	halmac = dvobj_to_halmac(d);
+	api = HALMAC_GET_API(halmac);
+
+	api->halmac_pinmux_wl_led_sw_ctrl(halmac, on);
+}
+
+#ifdef CONFIG_SDIO_HCI
+
+/*
+ * Description:
+ *	Update queue allocated page number to driver
+ *
+ * Parameter:
+ *	d	pointer to struct dvobj_priv of driver
+ *
+ * Rteurn:
+ *	0	Success, "page" is valid.
+ *	others	Fail, "page" is invalid.
+ */
+int rtw_halmac_query_tx_page_num(struct dvobj_priv *d)
+{
+	PADAPTER adapter;
+	struct halmacpriv *hmpriv;
+	struct halmac_adapter *halmac;
+	struct halmac_api *api;
+	struct halmac_rqpn_map rqpn;
+	enum halmac_dma_mapping dmaqueue;
+	struct halmac_txff_allocation fifosize;
+	enum halmac_ret_status status;
+	u8 i;
+
+
+	adapter = dvobj_get_primary_adapter(d);
+	hmpriv = &d->hmpriv;
+	halmac = dvobj_to_halmac(d);
+	api = HALMAC_GET_API(halmac);
+	_rtw_memset((void *)&rqpn, 0, sizeof(rqpn));
+	_rtw_memset((void *)&fifosize, 0, sizeof(fifosize));
+
+	status = api->halmac_get_hw_value(halmac, HALMAC_HW_RQPN_MAPPING, &rqpn);
+	if (status != HALMAC_RET_SUCCESS)
+		return -1;
+	status = api->halmac_get_hw_value(halmac, HALMAC_HW_TXFF_ALLOCATION, &fifosize);
+	if (status != HALMAC_RET_SUCCESS)
+		return -1;
+
+	for (i = 0; i < HW_QUEUE_ENTRY; i++) {
+		hmpriv->txpage[i] = 0;
+
+		/* Driver index mapping to HALMAC DMA queue */
+		dmaqueue = HALMAC_DMA_MAPPING_UNDEFINE;
+		switch (i) {
+		case VO_QUEUE_INX:
+			dmaqueue = rqpn.dma_map_vo;
+			break;
+		case VI_QUEUE_INX:
+			dmaqueue = rqpn.dma_map_vi;
+			break;
+		case BE_QUEUE_INX:
+			dmaqueue = rqpn.dma_map_be;
+			break;
+		case BK_QUEUE_INX:
+			dmaqueue = rqpn.dma_map_bk;
+			break;
+		case MGT_QUEUE_INX:
+			dmaqueue = rqpn.dma_map_mg;
+			break;
+		case HIGH_QUEUE_INX:
+			dmaqueue = rqpn.dma_map_hi;
+			break;
+		case BCN_QUEUE_INX:
+		case TXCMD_QUEUE_INX:
+			/* Unlimited */
+			hmpriv->txpage[i] = 0xFFFF;
+			continue;
+		}
+
+		switch (dmaqueue) {
+		case HALMAC_DMA_MAPPING_EXTRA:
+			hmpriv->txpage[i] = fifosize.extra_queue_pg_num;
+			break;
+		case HALMAC_DMA_MAPPING_LOW:
+			hmpriv->txpage[i] = fifosize.low_queue_pg_num;
+			break;
+		case HALMAC_DMA_MAPPING_NORMAL:
+			hmpriv->txpage[i] = fifosize.normal_queue_pg_num;
+			break;
+		case HALMAC_DMA_MAPPING_HIGH:
+			hmpriv->txpage[i] = fifosize.high_queue_pg_num;
+			break;
+		case HALMAC_DMA_MAPPING_UNDEFINE:
+			break;
+		}
+		hmpriv->txpage[i] += fifosize.pub_queue_pg_num;
+	}
+
+	return 0;
+}
+
+/*
+ * Description:
+ *	Get specific queue allocated page number
+ *
+ * Parameter:
+ *	d	pointer to struct dvobj_priv of driver
+ *	queue	target queue to query, VO/VI/BE/BK/.../TXCMD_QUEUE_INX
+ *	page	return allocated page number
+ *
+ * Rteurn:
+ *	0	Success, "page" is valid.
+ *	others	Fail, "page" is invalid.
+ */
+int rtw_halmac_get_tx_queue_page_num(struct dvobj_priv *d, u8 queue, u32 *page)
+{
+	*page = 0;
+	if (queue < HW_QUEUE_ENTRY)
+		*page = d->hmpriv.txpage[queue];
+
+	return 0;
+}
+
+/*
+ * Return:
+ *	address for SDIO command
+ */
+u32 rtw_halmac_sdio_get_tx_addr(struct dvobj_priv *d, u8 *desc, u32 size)
+{
+	struct halmac_adapter *mac;
+	struct halmac_api *api;
+	enum halmac_ret_status status;
+	u32 addr;
+
+
+	mac = dvobj_to_halmac(d);
+	api = HALMAC_GET_API(mac);
+
+	status = api->halmac_get_sdio_tx_addr(mac, desc, size, &addr);
+	if (HALMAC_RET_SUCCESS != status)
+		return 0;
+
+	return addr;
+}
+
+int rtw_halmac_sdio_tx_allowed(struct dvobj_priv *d, u8 *buf, u32 size)
+{
+	struct halmac_adapter *mac;
+	struct halmac_api *api;
+	enum halmac_ret_status status;
+
+
+	mac = dvobj_to_halmac(d);
+	api = HALMAC_GET_API(mac);
+
+	status = api->halmac_tx_allowed_sdio(mac, buf, size);
+	if (HALMAC_RET_SUCCESS != status)
+		return -1;
+
+	return 0;
+}
+
+u32 rtw_halmac_sdio_get_rx_addr(struct dvobj_priv *d, u8 *seq)
+{
+	u8 id;
+
+#define RTW_SDIO_ADDR_RX_RX0FF_PRFIX	0x0E000
+#define RTW_SDIO_ADDR_RX_RX0FF_GEN(a)	(RTW_SDIO_ADDR_RX_RX0FF_PRFIX|(a&0x3))
+
+	id = *seq;
+	(*seq)++;
+	return RTW_SDIO_ADDR_RX_RX0FF_GEN(id);
+}
+#endif /* CONFIG_SDIO_HCI */
+
+#ifdef CONFIG_USB_HCI
+u8 rtw_halmac_usb_get_bulkout_id(struct dvobj_priv *d, u8 *buf, u32 size)
+{
+	struct halmac_adapter *mac;
+	struct halmac_api *api;
+	enum halmac_ret_status status;
+	u8 bulkout_id;
+
+
+	mac = dvobj_to_halmac(d);
+	api = HALMAC_GET_API(mac);
+
+	status = api->halmac_get_usb_bulkout_id(mac, buf, size, &bulkout_id);
+	if (HALMAC_RET_SUCCESS != status)
+		return 0;
+
+	return bulkout_id;
+}
+
+/**
+ * rtw_halmac_usb_get_txagg_desc_num() - MAX descriptor number in one bulk for TX
+ * @d:		struct dvobj_priv*
+ * @size:	TX FIFO size, unit is byte.
+ *
+ * Get MAX descriptor number in one bulk out from HALMAC.
+ *
+ * Rteurn 0 for OK, otherwise fail.
+ */
+int rtw_halmac_usb_get_txagg_desc_num(struct dvobj_priv *d, u8 *num)
+{
+	struct halmac_adapter *halmac;
+	struct halmac_api *api;
+	enum halmac_ret_status status;
+	u8 val = 0;
+
+
+	halmac = dvobj_to_halmac(d);
+	api = HALMAC_GET_API(halmac);
+
+	status = api->halmac_get_hw_value(halmac, HALMAC_HW_USB_TXAGG_DESC_NUM, &val);
+	if (status != HALMAC_RET_SUCCESS)
+		return -1;
+
+	*num = val;
+
+	return 0;
+}
+
+static inline enum halmac_usb_mode _usb_mode_drv2halmac(enum RTW_USB_SPEED usb_mode)
+{
+	enum halmac_usb_mode halmac_usb_mode = HALMAC_USB_MODE_U2;
+
+	switch (usb_mode) {
+	case RTW_USB_SPEED_2:
+		halmac_usb_mode = HALMAC_USB_MODE_U2;
+		break;
+	case RTW_USB_SPEED_3:
+		halmac_usb_mode = HALMAC_USB_MODE_U3;
+		break;
+	default:
+		halmac_usb_mode = HALMAC_USB_MODE_U2;
+		break;
+	}
+
+	return halmac_usb_mode;
+}
+
+u8 rtw_halmac_switch_usb_mode(struct dvobj_priv *d, enum RTW_USB_SPEED usb_mode)
+{
+	PADAPTER adapter;
+	struct halmac_adapter *mac;
+	struct halmac_api *api;
+	enum halmac_ret_status status;
+	enum halmac_usb_mode halmac_usb_mode;
+
+	adapter = dvobj_get_primary_adapter(d);
+	mac = dvobj_to_halmac(d);
+	api = HALMAC_GET_API(mac);
+	halmac_usb_mode = _usb_mode_drv2halmac(usb_mode);
+	status = api->halmac_set_hw_value(mac, HALMAC_HW_USB_MODE, (void *)&halmac_usb_mode);
+
+	if (HALMAC_RET_SUCCESS != status)
+		return _FAIL;
+
+	return _SUCCESS;
+}
+#endif /* CONFIG_USB_HCI */
+
+#ifdef CONFIG_BEAMFORMING
+#ifdef RTW_BEAMFORMING_VERSION_2
+int rtw_halmac_bf_add_mu_bfer(struct dvobj_priv *d, u16 paid, u16 csi_para,
+		u16 my_aid, enum halmac_csi_seg_len sel, u8 *addr)
+{
+	struct halmac_adapter *mac;
+	struct halmac_api *api;
+	enum halmac_ret_status status;
+	struct halmac_mu_bfer_init_para param;
+
+
+	mac = dvobj_to_halmac(d);
+	api = HALMAC_GET_API(mac);
+
+	_rtw_memset(&param, 0, sizeof(param));
+	param.paid = paid;
+	param.csi_para = csi_para;
+	param.my_aid = my_aid;
+	param.csi_length_sel = sel;
+	_rtw_memcpy(param.bfer_address.addr, addr, 6);
+
+	status = api->halmac_mu_bfer_entry_init(mac, &param);
+	if (status != HALMAC_RET_SUCCESS)
+		return -1;
+
+	return 0;
+}
+
+int rtw_halmac_bf_del_mu_bfer(struct dvobj_priv *d)
+{
+	struct halmac_adapter *mac;
+	struct halmac_api *api;
+	enum halmac_ret_status status;
+
+
+	mac = dvobj_to_halmac(d);
+	api = HALMAC_GET_API(mac);
+
+	status = api->halmac_mu_bfer_entry_del(mac);
+	if (status != HALMAC_RET_SUCCESS)
+		return -1;
+
+	return 0;
+}
+
+
+int rtw_halmac_bf_cfg_sounding(struct dvobj_priv *d,
+		enum halmac_snd_role role, enum halmac_data_rate rate)
+{
+	struct halmac_adapter *mac;
+	struct halmac_api *api;
+	enum halmac_ret_status status;
+
+
+	mac = dvobj_to_halmac(d);
+	api = HALMAC_GET_API(mac);
+
+	status = api->halmac_cfg_sounding(mac, role, rate);
+	if (status != HALMAC_RET_SUCCESS)
+		return -1;
+
+	return 0;
+}
+
+int rtw_halmac_bf_del_sounding(struct dvobj_priv *d,
+		enum halmac_snd_role role)
+{
+	struct halmac_adapter *mac;
+	struct halmac_api *api;
+	enum halmac_ret_status status;
+
+
+	mac = dvobj_to_halmac(d);
+	api = HALMAC_GET_API(mac);
+
+	status = api->halmac_del_sounding(mac, role);
+	if (status != HALMAC_RET_SUCCESS)
+		return -1;
+
+	return 0;
+}
+
+int rtw_halmac_bf_cfg_csi_rate(struct dvobj_priv *d,
+		u8 rssi, u8 current_rate, u8 fixrate_en,
+		u8 *new_rate)
+{
+	struct halmac_adapter *mac;
+	struct halmac_api *api;
+	enum halmac_ret_status status;
+
+
+	mac = dvobj_to_halmac(d);
+	api = HALMAC_GET_API(mac);
+
+	status = api->halmac_cfg_csi_rate(mac,
+			rssi, current_rate, fixrate_en, new_rate);
+	if (status != HALMAC_RET_SUCCESS)
+		return -1;
+
+	return 0;
+}
+
+int rtw_halmac_bf_cfg_mu_mimo(struct dvobj_priv *d, enum halmac_snd_role role,
+		u8 *sounding_sts, u16 grouping_bitmap, u8 mu_tx_en,
+		u32 *given_gid_tab, u32 *given_user_pos)
+{
+	struct halmac_adapter *mac;
+	struct halmac_api *api;
+	enum halmac_ret_status status;
+	struct halmac_cfg_mumimo_para param;
+
+
+	mac = dvobj_to_halmac(d);
+	api = HALMAC_GET_API(mac);
+
+	_rtw_memset(&param, 0, sizeof(param));
+
+	param.role = role;
+	param.grouping_bitmap = grouping_bitmap;
+	param.mu_tx_en = mu_tx_en;
+
+	if (sounding_sts)
+		_rtw_memcpy(param.sounding_sts, sounding_sts, 6);
+
+	if (given_gid_tab)
+		_rtw_memcpy(param.given_gid_tab, given_gid_tab, 8);
+
+	if (given_user_pos)
+		_rtw_memcpy(param.given_user_pos, given_user_pos, 16);
+
+	status = api->halmac_cfg_mumimo(mac, &param);
+	if (status != HALMAC_RET_SUCCESS)
+		return -1;
+
+	return 0;
+}
+
+#endif /* RTW_BEAMFORMING_VERSION_2 */
+#endif /* CONFIG_BEAMFORMING */
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/hal_halmac.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/hal_halmac.h
--- linux-5.6.3/3rdparty/rtl8821ce/hal/hal_halmac.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/hal_halmac.h	2020-04-10 16:35:06.789658807 +0300
@@ -0,0 +1,241 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2015 - 2018 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#ifndef _HAL_HALMAC_H_
+#define _HAL_HALMAC_H_
+
+#include <drv_types.h>		/* adapter_to_dvobj(), struct intf_hdl and etc. */
+#include <hal_data.h>		/* struct hal_spec_t */
+#include "halmac/halmac_api.h"	/* struct halmac_adapter* and etc. */
+
+/* HALMAC Definition for Driver */
+#define RTW_HALMAC_H2C_MAX_SIZE		8
+#define RTW_HALMAC_BA_SSN_RPT_SIZE	4
+
+#define dvobj_set_halmac(d, mac)	((d)->halmac = (mac))
+#define dvobj_to_halmac(d)		((struct halmac_adapter *)((d)->halmac))
+#define adapter_to_halmac(p)		dvobj_to_halmac(adapter_to_dvobj(p))
+
+/* for H2C cmd */
+#define MAX_H2C_BOX_NUMS 4
+#define MESSAGE_BOX_SIZE 4
+#define EX_MESSAGE_BOX_SIZE 4
+
+typedef enum _RTW_HALMAC_MODE {
+	RTW_HALMAC_MODE_NORMAL,
+	RTW_HALMAC_MODE_WIFI_TEST,
+} RTW_HALMAC_MODE;
+
+union rtw_phy_para_data {
+	struct _mac {
+		u32	value;	/* value to be set in bit mask(msk) */
+		u32	msk;	/* bit mask */
+		u16	offset; /* address */
+		u8	msk_en;	/* 0/1 for msk invalid/valid */
+		u8	size;	/* Unit is bytes, and value should be 1/2/4 */
+	} mac;
+	struct _bb {
+		u32	value;
+		u32	msk;
+		u16	offset;
+		u8	msk_en;
+		u8	size;
+	} bb;
+	struct _rf {
+		u32	value;
+		u32	msk;
+		u8	offset;
+		u8	msk_en;
+		/*
+		 * 0: path A
+		 * 1: path B
+		 * 2: path C
+		 * 3: path D
+		 */
+		u8	path;
+	} rf;
+	struct _delay {
+		/*
+		 * 0: microsecond (us)
+		 * 1: millisecond (ms)
+		 */
+		u8	unit;
+		u16	value;
+	} delay;
+};
+
+struct rtw_phy_parameter {
+	/*
+	 * 0: MAC register
+	 * 1: BB register
+	 * 2: RF register
+	 * 3: Delay
+	 * 0xFF: Latest(End) command
+	 */
+	u8 cmd;
+	union rtw_phy_para_data data;
+};
+
+struct rtw_halmac_bcn_ctrl {
+	u8 rx_bssid_fit:1;	/* 0:HW handle beacon, 1:ignore */
+	u8 txbcn_rpt:1;		/* Enable TXBCN report in ad hoc and AP mode */
+	u8 tsf_update:1;	/* Update TSF when beacon or probe response */
+	u8 enable_bcn:1;	/* Enable beacon related functions */
+	u8 rxbcn_rpt:1;		/* Enable RXBCNOK report */
+	u8 p2p_ctwin:1;		/* Enable P2P CTN WINDOWS function */
+	u8 p2p_bcn_area:1;	/* Enable P2P BCN area on function */
+};
+
+extern struct halmac_platform_api rtw_halmac_platform_api;
+
+/* HALMAC API for Driver(HAL) */
+u8 rtw_halmac_read8(struct intf_hdl *, u32 addr);
+u16 rtw_halmac_read16(struct intf_hdl *, u32 addr);
+u32 rtw_halmac_read32(struct intf_hdl *, u32 addr);
+void rtw_halmac_read_mem(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *pmem);
+#ifdef CONFIG_SDIO_INDIRECT_ACCESS
+u8 rtw_halmac_iread8(struct intf_hdl *pintfhdl, u32 addr);
+u16 rtw_halmac_iread16(struct intf_hdl *pintfhdl, u32 addr);
+u32 rtw_halmac_iread32(struct intf_hdl *pintfhdl, u32 addr);
+#endif /* CONFIG_SDIO_INDIRECT_ACCESS */
+int rtw_halmac_write8(struct intf_hdl *, u32 addr, u8 value);
+int rtw_halmac_write16(struct intf_hdl *, u32 addr, u16 value);
+int rtw_halmac_write32(struct intf_hdl *, u32 addr, u32 value);
+
+/* Software Information */
+void rtw_halmac_get_version(char *str, u32 len);
+
+/* Software Initialization */
+int rtw_halmac_init_adapter(struct dvobj_priv *d, struct halmac_platform_api *pf_api);
+int rtw_halmac_deinit_adapter(struct dvobj_priv *);
+
+/* Get operations */
+int rtw_halmac_get_hw_value(struct dvobj_priv *d, enum halmac_hw_id hw_id, void *pvalue);
+int rtw_halmac_get_tx_fifo_size(struct dvobj_priv *d, u32 *size);
+int rtw_halmac_get_rx_fifo_size(struct dvobj_priv *d, u32 *size);
+int rtw_halmac_get_rsvd_drv_pg_bndy(struct dvobj_priv *d, u16 *bndy);
+int rtw_halmac_get_page_size(struct dvobj_priv *d, u32 *size);
+int rtw_halmac_get_tx_agg_align_size(struct dvobj_priv *d, u16 *size);
+int rtw_halmac_get_rx_agg_align_size(struct dvobj_priv *d, u8 *size);
+int rtw_halmac_get_rx_drv_info_sz(struct dvobj_priv *, u8 *sz);
+int rtw_halmac_get_tx_desc_size(struct dvobj_priv *d, u32 *size);
+int rtw_halmac_get_rx_desc_size(struct dvobj_priv *d, u32 *size);
+int rtw_halmac_get_ori_h2c_size(struct dvobj_priv *d, u32 *size);
+int rtw_halmac_get_oqt_size(struct dvobj_priv *d, u8 *size);
+int rtw_halmac_get_ac_queue_number(struct dvobj_priv *d, u8 *num);
+int rtw_halmac_get_mac_address(struct dvobj_priv *d, enum _hw_port hwport, u8 *addr);
+int rtw_halmac_get_network_type(struct dvobj_priv *d, enum _hw_port hwport, u8 *type);
+int rtw_halmac_get_bcn_ctrl(struct dvobj_priv *d, enum _hw_port hwport, struct rtw_halmac_bcn_ctrl *bcn_ctrl);
+/*int rtw_halmac_get_wow_reason(struct dvobj_priv *, u8 *reason);*/
+
+/* Set operations */
+int rtw_halmac_config_rx_info(struct dvobj_priv *d, enum halmac_drv_info info);
+int rtw_halmac_set_max_dl_fw_size(struct dvobj_priv *d, u32 size);
+int rtw_halmac_set_mac_address(struct dvobj_priv *d, enum _hw_port hwport, u8 *addr);
+int rtw_halmac_set_bssid(struct dvobj_priv *d, enum _hw_port hwport, u8 *addr);
+int rtw_halmac_set_tx_address(struct dvobj_priv *d, enum _hw_port hwport, u8 *addr);
+int rtw_halmac_set_network_type(struct dvobj_priv *d, enum _hw_port hwport, u8 type);
+int rtw_halmac_reset_tsf(struct dvobj_priv *d, enum _hw_port hwport);
+int rtw_halmac_set_bcn_interval(struct dvobj_priv *d, enum _hw_port hwport, u32 space);
+int rtw_halmac_set_bcn_ctrl(struct dvobj_priv *d, enum _hw_port hwport, struct rtw_halmac_bcn_ctrl *bcn_ctrl);
+int rtw_halmac_set_aid(struct dvobj_priv *d, enum _hw_port hwport, u16 aid);
+int rtw_halmac_set_bandwidth(struct dvobj_priv *d, u8 channel, u8 pri_ch_idx, u8 bw);
+int rtw_halmac_set_edca(struct dvobj_priv *d, u8 queue, u8 aifs, u8 cw, u16 txop);
+int rtw_halmac_set_rts_full_bw(struct dvobj_priv *d, u8 enable);
+
+/* Functions */
+int rtw_halmac_poweron(struct dvobj_priv *);
+int rtw_halmac_poweroff(struct dvobj_priv *);
+int rtw_halmac_init_hal(struct dvobj_priv *);
+int rtw_halmac_init_hal_fw(struct dvobj_priv *, u8 *fw, u32 fwsize);
+int rtw_halmac_init_hal_fw_file(struct dvobj_priv *, u8 *fwpath);
+int rtw_halmac_deinit_hal(struct dvobj_priv *);
+int rtw_halmac_self_verify(struct dvobj_priv *);
+int rtw_halmac_txfifo_wait_empty(struct dvobj_priv *d, u32 timeout);
+int rtw_halmac_dlfw(struct dvobj_priv *, u8 *fw, u32 fwsize);
+int rtw_halmac_dlfw_from_file(struct dvobj_priv *, u8 *fwpath);
+int rtw_halmac_dlfw_mem(struct dvobj_priv *d, u8 *fw, u32 fwsize, enum fw_mem mem);
+int rtw_halmac_dlfw_mem_from_file(struct dvobj_priv *d, u8 *fwpath, enum fw_mem mem);
+int rtw_halmac_phy_power_switch(struct dvobj_priv *, u8 enable);
+int rtw_halmac_send_h2c(struct dvobj_priv *, u8 *h2c);
+int rtw_halmac_c2h_handle(struct dvobj_priv *, u8 *c2h, u32 size);
+
+/* eFuse */
+int rtw_halmac_get_available_efuse_size(struct dvobj_priv *d, u32 *size);
+int rtw_halmac_get_physical_efuse_size(struct dvobj_priv *, u32 *size);
+int rtw_halmac_read_physical_efuse_map(struct dvobj_priv *, u8 *map, u32 size);
+int rtw_halmac_read_physical_efuse(struct dvobj_priv *, u32 offset, u32 cnt, u8 *data);
+int rtw_halmac_write_physical_efuse(struct dvobj_priv *, u32 offset, u32 cnt, u8 *data);
+int rtw_halmac_get_logical_efuse_size(struct dvobj_priv *, u32 *size);
+int rtw_halmac_read_logical_efuse_map(struct dvobj_priv *, u8 *map, u32 size, u8 *maskmap, u32 masksize);
+int rtw_halmac_write_logical_efuse_map(struct dvobj_priv *, u8 *map, u32 size, u8 *maskmap, u32 masksize);
+int rtw_halmac_read_logical_efuse(struct dvobj_priv *, u32 offset, u32 cnt, u8 *data);
+int rtw_halmac_write_logical_efuse(struct dvobj_priv *, u32 offset, u32 cnt, u8 *data);
+
+int rtw_halmac_write_bt_physical_efuse(struct dvobj_priv *, u32 offset, u32 cnt, u8 *data);
+int rtw_halmac_read_bt_physical_efuse_map(struct dvobj_priv *, u8 *map, u32 size);
+
+int rtw_halmac_dump_fifo(struct dvobj_priv *d, u8 fifo_sel, u32 addr, u32 size, u8 *buffer);
+int rtw_halmac_rx_agg_switch(struct dvobj_priv *, u8 enable);
+
+/* Specific function APIs*/
+int rtw_halmac_download_rsvd_page(struct dvobj_priv *dvobj, u8 pg_offset, u8 *pbuf, u32 size);
+int rtw_halmac_fill_hal_spec(struct dvobj_priv *, struct hal_spec_t *);
+int rtw_halmac_p2pps(struct dvobj_priv *dvobj, PHAL_P2P_PS_PARA pp2p_ps_para);
+int rtw_halmac_iqk(struct dvobj_priv *d, u8 clear, u8 segment);
+int rtw_halmac_cfg_phy_para(struct dvobj_priv *d, struct rtw_phy_parameter *para);
+int rtw_halmac_led_cfg(struct dvobj_priv *d, u8 enable, u8 mode);
+void rtw_halmac_led_switch(struct dvobj_priv *d, u8 on);
+
+#ifdef CONFIG_SDIO_HCI
+int rtw_halmac_query_tx_page_num(struct dvobj_priv *);
+int rtw_halmac_get_tx_queue_page_num(struct dvobj_priv *, u8 queue, u32 *page);
+u32 rtw_halmac_sdio_get_tx_addr(struct dvobj_priv *, u8 *desc, u32 size);
+int rtw_halmac_sdio_tx_allowed(struct dvobj_priv *, u8 *buf, u32 size);
+u32 rtw_halmac_sdio_get_rx_addr(struct dvobj_priv *, u8 *seq);
+#endif /* CONFIG_SDIO_HCI */
+
+#ifdef CONFIG_USB_HCI
+u8 rtw_halmac_usb_get_bulkout_id(struct dvobj_priv *, u8 *buf, u32 size);
+int rtw_halmac_usb_get_txagg_desc_num(struct dvobj_priv *d, u8 *num);
+u8 rtw_halmac_switch_usb_mode(struct dvobj_priv *d, enum RTW_USB_SPEED usb_mode);
+#endif /* CONFIG_USB_HCI */
+
+#ifdef CONFIG_SUPPORT_TRX_SHARED
+void dump_trx_share_mode(void *sel, _adapter *adapter);
+#endif
+
+#ifdef CONFIG_BEAMFORMING
+#ifdef RTW_BEAMFORMING_VERSION_2
+int rtw_halmac_bf_add_mu_bfer(struct dvobj_priv *d, u16 paid, u16 csi_para,
+		u16 my_aid, enum halmac_csi_seg_len sel, u8 *addr);
+int rtw_halmac_bf_del_mu_bfer(struct dvobj_priv *d);
+
+int rtw_halmac_bf_cfg_sounding(struct dvobj_priv *d, enum halmac_snd_role role,
+		enum halmac_data_rate rate);
+int rtw_halmac_bf_del_sounding(struct dvobj_priv *d, enum halmac_snd_role role);
+
+int rtw_halmac_bf_cfg_csi_rate(struct dvobj_priv *d, u8 rssi, u8 current_rate,
+		u8 fixrate_en, u8 *new_rate);
+
+int rtw_halmac_bf_cfg_mu_mimo(struct dvobj_priv *d, enum halmac_snd_role role,
+		u8 *sounding_sts, u16 grouping_bitmap, u8 mu_tx_en,
+		u32 *given_gid_tab, u32 *given_user_pos);
+#define rtw_halmac_bf_cfg_mu_bfee(d, gid_tab, user_pos) \
+	rtw_halmac_bf_cfg_mu_mimo(d, HAL_BFEE, NULL, 0, 0, gid_tab, user_pos)
+
+#endif /* RTW_BEAMFORMING_VERSION_2 */
+#endif /* CONFIG_BEAMFORMING */
+
+#endif /* _HAL_HALMAC_H_ */
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/hal_hci/hal_pci.c linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/hal_hci/hal_pci.c
--- linux-5.6.3/3rdparty/rtl8821ce/hal/hal_hci/hal_pci.c	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/hal_hci/hal_pci.c	2020-04-10 16:35:06.789658807 +0300
@@ -0,0 +1,18 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#define _HAL_PCI_C_
+
+#include <drv_types.h>
+#include <hal_data.h>
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/hal_intf.c linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/hal_intf.c
--- linux-5.6.3/3rdparty/rtl8821ce/hal/hal_intf.c	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/hal_intf.c	2020-04-10 16:35:06.790658854 +0300
@@ -0,0 +1,1705 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+
+#define _HAL_INTF_C_
+
+#include <drv_types.h>
+#include <hal_data.h>
+
+const u32 _chip_type_to_odm_ic_type[] = {
+	0,
+	ODM_RTL8188E,
+	ODM_RTL8192E,
+	ODM_RTL8812,
+	ODM_RTL8821,
+	ODM_RTL8723B,
+	ODM_RTL8814A,
+	ODM_RTL8703B,
+	ODM_RTL8188F,
+	ODM_RTL8188F,
+	ODM_RTL8822B,
+	ODM_RTL8723D,
+	ODM_RTL8821C,
+	ODM_RTL8710B,
+	ODM_RTL8192F,
+	0,
+};
+
+void rtw_hal_chip_configure(_adapter *padapter)
+{
+	padapter->hal_func.intf_chip_configure(padapter);
+}
+
+/*
+ * Description:
+ *	Read chip internal ROM data
+ *
+ * Return:
+ *	_SUCCESS success
+ *	_FAIL	 fail
+ */
+u8 rtw_hal_read_chip_info(_adapter *padapter)
+{
+	u8 rtn = _SUCCESS;
+	u8 hci_type = rtw_get_intf_type(padapter);
+	systime start = rtw_get_current_time();
+
+	/*  before access eFuse, make sure card enable has been called */
+	if ((hci_type == RTW_SDIO || hci_type == RTW_GSPI)
+	    && !rtw_is_hw_init_completed(padapter))
+		rtw_hal_power_on(padapter);
+
+	rtn = padapter->hal_func.read_adapter_info(padapter);
+
+	if ((hci_type == RTW_SDIO || hci_type == RTW_GSPI)
+	    && !rtw_is_hw_init_completed(padapter))
+		rtw_hal_power_off(padapter);
+
+	RTW_INFO("%s in %d ms\n", __func__, rtw_get_passing_time_ms(start));
+
+	return rtn;
+}
+
+void rtw_hal_read_chip_version(_adapter *padapter)
+{
+	padapter->hal_func.read_chip_version(padapter);
+	rtw_odm_init_ic_type(padapter);
+}
+
+static void rtw_init_wireless_mode(_adapter *padapter)
+{
+	u8 proto_wireless_mode = 0;
+	struct hal_spec_t *hal_spec = GET_HAL_SPEC(padapter);
+	if(hal_spec->proto_cap & PROTO_CAP_11B)
+		proto_wireless_mode |= WIRELESS_11B;
+	
+	if(hal_spec->proto_cap & PROTO_CAP_11G)
+		proto_wireless_mode |= WIRELESS_11G;
+#ifdef CONFIG_80211AC_VHT
+	if(hal_spec->band_cap & BAND_CAP_5G)
+		proto_wireless_mode |= WIRELESS_11A;
+#endif
+
+#ifdef CONFIG_80211N_HT
+	if(hal_spec->proto_cap & PROTO_CAP_11N) {
+
+		if(hal_spec->band_cap & BAND_CAP_2G)
+			proto_wireless_mode |= WIRELESS_11_24N;
+		if(hal_spec->band_cap & BAND_CAP_5G)
+			proto_wireless_mode |= WIRELESS_11_5N;
+	}
+#endif
+
+#ifdef CONFIG_80211AC_VHT
+	if(hal_spec->proto_cap & PROTO_CAP_11AC) 
+		proto_wireless_mode |= WIRELESS_11AC;
+#endif
+	padapter->registrypriv.wireless_mode &= proto_wireless_mode;
+}
+
+void rtw_hal_def_value_init(_adapter *padapter)
+{
+	if (is_primary_adapter(padapter)) {
+		/*init fw_psmode_iface_id*/
+		adapter_to_pwrctl(padapter)->fw_psmode_iface_id = 0xff;
+		/*wireless_mode*/
+		rtw_init_wireless_mode(padapter);
+		padapter->hal_func.init_default_value(padapter);
+
+		rtw_init_hal_com_default_value(padapter);
+		
+		#ifdef CONFIG_FW_MULTI_PORT_SUPPORT
+		adapter_to_dvobj(padapter)->dft.port_id = 0xFF;
+		adapter_to_dvobj(padapter)->dft.mac_id = 0xFF;
+		#endif
+		#ifdef CONFIG_HW_P0_TSF_SYNC
+		adapter_to_dvobj(padapter)->p0_tsf.sync_port = MAX_HW_PORT;
+		adapter_to_dvobj(padapter)->p0_tsf.offset = 0;
+		#endif
+
+		{
+			struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
+			struct hal_spec_t *hal_spec = GET_HAL_SPEC(padapter);
+
+			/* hal_spec is ready here */
+			dvobj->macid_ctl.num = rtw_min(hal_spec->macid_num, MACID_NUM_SW_LIMIT);
+
+			dvobj->cam_ctl.sec_cap = hal_spec->sec_cap;
+			dvobj->cam_ctl.num = rtw_min(hal_spec->sec_cam_ent_num, SEC_CAM_ENT_NUM_SW_LIMIT);
+		}
+		GET_HAL_DATA(padapter)->rx_tsf_addr_filter_config = 0;
+	}
+}
+
+u8 rtw_hal_data_init(_adapter *padapter)
+{
+	if (is_primary_adapter(padapter)) {
+		padapter->hal_data_sz = sizeof(HAL_DATA_TYPE);
+		padapter->HalData = rtw_zvmalloc(padapter->hal_data_sz);
+		if (padapter->HalData == NULL) {
+			RTW_INFO("cant not alloc memory for HAL DATA\n");
+			return _FAIL;
+		}
+		rtw_phydm_priv_init(padapter);
+	}
+	return _SUCCESS;
+}
+
+void rtw_hal_data_deinit(_adapter *padapter)
+{
+	if (is_primary_adapter(padapter)) {
+		if (padapter->HalData) {
+#ifdef CONFIG_LOAD_PHY_PARA_FROM_FILE
+			phy_free_filebuf(padapter);
+#endif
+			rtw_vmfree(padapter->HalData, padapter->hal_data_sz);
+			padapter->HalData = NULL;
+			padapter->hal_data_sz = 0;
+		}
+	}
+}
+
+void	rtw_hal_free_data(_adapter *padapter)
+{
+	/* free HAL Data	 */
+	rtw_hal_data_deinit(padapter);
+}
+void rtw_hal_dm_init(_adapter *padapter)
+{
+	if (is_primary_adapter(padapter)) {
+		PHAL_DATA_TYPE	pHalData = GET_HAL_DATA(padapter);
+
+		padapter->hal_func.dm_init(padapter);
+
+		_rtw_spinlock_init(&pHalData->IQKSpinLock);
+
+		phy_load_tx_power_ext_info(padapter, 1);
+	}
+}
+void rtw_hal_dm_deinit(_adapter *padapter)
+{
+	if (is_primary_adapter(padapter)) {
+		PHAL_DATA_TYPE	pHalData = GET_HAL_DATA(padapter);
+
+		padapter->hal_func.dm_deinit(padapter);
+
+		_rtw_spinlock_free(&pHalData->IQKSpinLock);
+	}
+}
+
+#ifdef CONFIG_RTW_SW_LED
+void rtw_hal_sw_led_init(_adapter *padapter)
+{
+	struct led_priv *ledpriv = adapter_to_led(padapter);
+
+	if (ledpriv->bRegUseLed == _FALSE)
+		return;
+
+	if (!is_primary_adapter(padapter))
+		return;
+
+	if (padapter->hal_func.InitSwLeds) {
+		padapter->hal_func.InitSwLeds(padapter);
+		rtw_led_set_ctl_en_mask_primary(padapter);
+		rtw_led_set_iface_en(padapter, 1);
+	}
+}
+
+void rtw_hal_sw_led_deinit(_adapter *padapter)
+{
+	struct led_priv *ledpriv = adapter_to_led(padapter);
+
+	if (ledpriv->bRegUseLed == _FALSE)
+		return;
+
+	if (!is_primary_adapter(padapter))
+		return;
+
+	if (padapter->hal_func.DeInitSwLeds)
+		padapter->hal_func.DeInitSwLeds(padapter);
+}
+#endif
+
+u32 rtw_hal_power_on(_adapter *padapter)
+{
+	u32 ret = 0;
+	PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter);
+
+	ret = padapter->hal_func.hal_power_on(padapter);
+
+#ifdef CONFIG_BT_COEXIST
+	if ((ret == _SUCCESS) && (pHalData->EEPROMBluetoothCoexist == _TRUE))
+		rtw_btcoex_PowerOnSetting(padapter);
+#endif
+
+	return ret;
+}
+void rtw_hal_power_off(_adapter *padapter)
+{
+	struct macid_ctl_t *macid_ctl = &padapter->dvobj->macid_ctl;
+
+	_rtw_memset(macid_ctl->h2c_msr, 0, MACID_NUM_SW_LIMIT);
+
+#ifdef CONFIG_BT_COEXIST
+	rtw_btcoex_PowerOffSetting(padapter);
+#endif
+
+	padapter->hal_func.hal_power_off(padapter);
+}
+
+
+void rtw_hal_init_opmode(_adapter *padapter)
+{
+	NDIS_802_11_NETWORK_INFRASTRUCTURE networkType = Ndis802_11InfrastructureMax;
+	struct  mlme_priv *pmlmepriv = &(padapter->mlmepriv);
+	sint fw_state;
+
+	fw_state = get_fwstate(pmlmepriv);
+
+	if (fw_state & WIFI_ADHOC_STATE)
+		networkType = Ndis802_11IBSS;
+	else if (fw_state & WIFI_STATION_STATE)
+		networkType = Ndis802_11Infrastructure;
+#ifdef CONFIG_AP_MODE
+	else if (fw_state & WIFI_AP_STATE)
+		networkType = Ndis802_11APMode;
+#endif
+#ifdef CONFIG_RTW_MESH
+	else if (fw_state & WIFI_MESH_STATE)
+		networkType = Ndis802_11_mesh;
+#endif
+	else
+		return;
+
+	rtw_setopmode_cmd(padapter, networkType, RTW_CMDF_DIRECTLY);
+}
+
+#ifdef CONFIG_NEW_NETDEV_HDL
+uint rtw_hal_iface_init(_adapter *adapter)
+{
+	uint status = _SUCCESS;
+
+	rtw_hal_set_hwreg(adapter, HW_VAR_MAC_ADDR, adapter_mac_addr(adapter));
+	#ifdef RTW_HALMAC
+	rtw_hal_hw_port_enable(adapter);
+	#endif
+	rtw_sec_restore_wep_key(adapter);
+	rtw_hal_init_opmode(adapter);
+	rtw_hal_start_thread(adapter);
+	return status;
+}
+uint rtw_hal_init(_adapter *padapter)
+{
+	uint status = _SUCCESS;
+
+	status = padapter->hal_func.hal_init(padapter);
+
+	if (status == _SUCCESS) {
+		rtw_set_hw_init_completed(padapter, _TRUE);
+		if (padapter->registrypriv.notch_filter == 1)
+			rtw_hal_notch_filter(padapter, 1);
+		rtw_led_control(padapter, LED_CTL_POWER_ON);
+		init_hw_mlme_ext(padapter);
+		#ifdef CONFIG_RF_POWER_TRIM
+		rtw_bb_rf_gain_offset(padapter);
+		#endif /*CONFIG_RF_POWER_TRIM*/
+		GET_PRIMARY_ADAPTER(padapter)->bup = _TRUE; /*temporary*/
+		#ifdef CONFIG_MI_WITH_MBSSID_CAM
+		rtw_mi_set_mbid_cam(padapter);
+		#endif
+		#ifdef CONFIG_SUPPORT_MULTI_BCN
+		rtw_ap_multi_bcn_cfg(padapter);
+		#endif
+		#if (RTL8822B_SUPPORT == 1) || (RTL8192F_SUPPORT == 1)
+		#ifdef CONFIG_DYNAMIC_SOML
+		rtw_dyn_soml_config(padapter);
+		#endif
+		#endif
+#ifdef CONFIG_RTW_TX_2PATH_EN
+		rtw_phydm_tx_2path_en(padapter);
+#endif
+	} else {
+		rtw_set_hw_init_completed(padapter, _FALSE);
+		RTW_ERR("%s: hal_init fail\n", __func__);
+	}
+	return status;
+}
+#else
+uint	 rtw_hal_init(_adapter *padapter)
+{
+	uint	status = _SUCCESS;
+	struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
+	int i;
+
+	status = padapter->hal_func.hal_init(padapter);
+
+	if (status == _SUCCESS) {
+		rtw_set_hw_init_completed(padapter, _TRUE);
+		rtw_mi_set_mac_addr(padapter);/*set mac addr of all ifaces*/
+		#ifdef RTW_HALMAC
+		rtw_restore_hw_port_cfg(padapter);
+		#endif
+		if (padapter->registrypriv.notch_filter == 1)
+			rtw_hal_notch_filter(padapter, 1);
+
+		for (i = 0; i < dvobj->iface_nums; i++)
+			rtw_sec_restore_wep_key(dvobj->padapters[i]);
+
+		rtw_led_control(padapter, LED_CTL_POWER_ON);
+
+		init_hw_mlme_ext(padapter);
+
+		rtw_hal_init_opmode(padapter);
+
+		#ifdef CONFIG_RF_POWER_TRIM
+		rtw_bb_rf_gain_offset(padapter);
+		#endif /*CONFIG_RF_POWER_TRIM*/
+
+		#ifdef CONFIG_SUPPORT_MULTI_BCN
+		rtw_ap_multi_bcn_cfg(padapter);
+		#endif
+
+#if (RTL8822B_SUPPORT == 1) || (RTL8192F_SUPPORT == 1)
+#ifdef CONFIG_DYNAMIC_SOML
+		rtw_dyn_soml_config(padapter);
+#endif
+#endif
+
+#ifdef CONFIG_RTW_TX_2PATH_EN
+		rtw_phydm_tx_2path_en(padapter);
+#endif
+	} else {
+		rtw_set_hw_init_completed(padapter, _FALSE);
+		RTW_ERR("%s: fail\n", __func__);
+	}
+
+
+	return status;
+
+}
+#endif
+
+uint rtw_hal_deinit(_adapter *padapter)
+{
+	uint	status = _SUCCESS;
+	struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
+	int i;
+
+	status = padapter->hal_func.hal_deinit(padapter);
+
+	if (status == _SUCCESS) {
+		rtw_led_control(padapter, LED_CTL_POWER_OFF);
+		rtw_set_hw_init_completed(padapter, _FALSE);
+	} else
+		RTW_INFO("\n rtw_hal_deinit: hal_init fail\n");
+
+
+	return status;
+}
+
+u8 rtw_hal_set_hwreg(_adapter *padapter, u8 variable, u8 *val)
+{
+	return padapter->hal_func.set_hw_reg_handler(padapter, variable, val);
+}
+
+void rtw_hal_get_hwreg(_adapter *padapter, u8 variable, u8 *val)
+{
+	padapter->hal_func.GetHwRegHandler(padapter, variable, val);
+}
+
+u8 rtw_hal_set_def_var(_adapter *padapter, HAL_DEF_VARIABLE eVariable, PVOID pValue)
+{
+	return padapter->hal_func.SetHalDefVarHandler(padapter, eVariable, pValue);
+}
+u8 rtw_hal_get_def_var(_adapter *padapter, HAL_DEF_VARIABLE eVariable, PVOID pValue)
+{
+	return padapter->hal_func.get_hal_def_var_handler(padapter, eVariable, pValue);
+}
+
+void rtw_hal_set_odm_var(_adapter *padapter, HAL_ODM_VARIABLE eVariable, PVOID pValue1, BOOLEAN bSet)
+{
+	padapter->hal_func.SetHalODMVarHandler(padapter, eVariable, pValue1, bSet);
+}
+void	rtw_hal_get_odm_var(_adapter *padapter, HAL_ODM_VARIABLE eVariable, PVOID pValue1, PVOID pValue2)
+{
+	padapter->hal_func.GetHalODMVarHandler(padapter, eVariable, pValue1, pValue2);
+}
+
+/* FOR SDIO & PCIE */
+void rtw_hal_enable_interrupt(_adapter *padapter)
+{
+#if defined(CONFIG_PCI_HCI) || defined(CONFIG_SDIO_HCI) || defined (CONFIG_GSPI_HCI)
+	padapter->hal_func.enable_interrupt(padapter);
+#endif /* #if defined(CONFIG_PCI_HCI) || defined (CONFIG_SDIO_HCI) || defined (CONFIG_GSPI_HCI) */
+}
+
+/* FOR SDIO & PCIE */
+void rtw_hal_disable_interrupt(_adapter *padapter)
+{
+#if defined(CONFIG_PCI_HCI) || defined(CONFIG_SDIO_HCI) || defined (CONFIG_GSPI_HCI)
+	padapter->hal_func.disable_interrupt(padapter);
+#endif /* #if defined(CONFIG_PCI_HCI) || defined (CONFIG_SDIO_HCI) || defined (CONFIG_GSPI_HCI) */
+}
+
+
+u8 rtw_hal_check_ips_status(_adapter *padapter)
+{
+	u8 val = _FALSE;
+	if (padapter->hal_func.check_ips_status)
+		val = padapter->hal_func.check_ips_status(padapter);
+	else
+		RTW_INFO("%s: hal_func.check_ips_status is NULL!\n", __FUNCTION__);
+
+	return val;
+}
+
+s32 rtw_hal_fw_dl(_adapter *padapter, u8 wowlan)
+{
+	return padapter->hal_func.fw_dl(padapter, wowlan);
+}
+
+#ifdef RTW_HALMAC
+s32 rtw_hal_fw_mem_dl(_adapter *padapter, enum fw_mem mem)
+{
+	systime dlfw_start_time = rtw_get_current_time();
+	struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
+	struct debug_priv *pdbgpriv = &dvobj->drv_dbg;
+	s32 rst = _FALSE;
+
+	rst = padapter->hal_func.fw_mem_dl(padapter, mem);
+	RTW_INFO("%s in %dms\n", __func__, rtw_get_passing_time_ms(dlfw_start_time));
+
+	if (rst == _FALSE)
+		pdbgpriv->dbg_fw_mem_dl_error_cnt++;
+	if (1)
+		RTW_INFO("%s dbg_fw_mem_dl_error_cnt:%d\n", __func__, pdbgpriv->dbg_fw_mem_dl_error_cnt);
+	return rst;
+}
+#endif
+
+#if defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN)
+void rtw_hal_clear_interrupt(_adapter *padapter)
+{
+#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
+	padapter->hal_func.clear_interrupt(padapter);
+#endif
+}
+#endif
+
+#if defined(CONFIG_USB_HCI) || defined(CONFIG_PCI_HCI)
+u32	rtw_hal_inirp_init(_adapter *padapter)
+{
+	if (is_primary_adapter(padapter))
+		return padapter->hal_func.inirp_init(padapter);
+	return _SUCCESS;
+}
+u32	rtw_hal_inirp_deinit(_adapter *padapter)
+{
+
+	if (is_primary_adapter(padapter))
+		return padapter->hal_func.inirp_deinit(padapter);
+
+	return _SUCCESS;
+}
+#endif /* #if defined(CONFIG_USB_HCI) || defined (CONFIG_PCI_HCI) */
+
+#if defined(CONFIG_PCI_HCI)
+void	rtw_hal_irp_reset(_adapter *padapter)
+{
+	padapter->hal_func.irp_reset(GET_PRIMARY_ADAPTER(padapter));
+}
+
+void rtw_hal_pci_dbi_write(_adapter *padapter, u16 addr, u8 data)
+{
+	u16 cmd[2];
+
+	cmd[0] = addr;
+	cmd[1] = data;
+
+	padapter->hal_func.set_hw_reg_handler(padapter, HW_VAR_DBI, (u8 *) cmd);
+}
+
+u8 rtw_hal_pci_dbi_read(_adapter *padapter, u16 addr)
+{
+	padapter->hal_func.GetHwRegHandler(padapter, HW_VAR_DBI, (u8 *)(&addr));
+
+	return (u8)addr;
+}
+
+void rtw_hal_pci_mdio_write(_adapter *padapter, u8 addr, u16 data)
+{
+	u16 cmd[2];
+
+	cmd[0] = (u16)addr;
+	cmd[1] = data;
+
+	padapter->hal_func.set_hw_reg_handler(padapter, HW_VAR_MDIO, (u8 *) cmd);
+}
+
+u16 rtw_hal_pci_mdio_read(_adapter *padapter, u8 addr)
+{
+	padapter->hal_func.GetHwRegHandler(padapter, HW_VAR_MDIO, &addr);
+
+	return (u8)addr;
+}
+
+u8 rtw_hal_pci_l1off_nic_support(_adapter *padapter)
+{
+	u8 l1off;
+
+	padapter->hal_func.GetHwRegHandler(padapter, HW_VAR_L1OFF_NIC_SUPPORT, &l1off);
+	return l1off;
+}
+
+u8 rtw_hal_pci_l1off_capability(_adapter *padapter)
+{
+	u8 l1off;
+
+	padapter->hal_func.GetHwRegHandler(padapter, HW_VAR_L1OFF_CAPABILITY, &l1off);
+	return l1off;
+}
+
+
+#endif /* #if defined(CONFIG_PCI_HCI) */
+
+/* for USB Auto-suspend */
+u8	rtw_hal_intf_ps_func(_adapter *padapter, HAL_INTF_PS_FUNC efunc_id, u8 *val)
+{
+	if (padapter->hal_func.interface_ps_func)
+		return padapter->hal_func.interface_ps_func(padapter, efunc_id, val);
+	return _FAIL;
+}
+
+s32	rtw_hal_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe)
+{
+	return padapter->hal_func.hal_xmitframe_enqueue(padapter, pxmitframe);
+}
+
+s32	rtw_hal_xmit(_adapter *padapter, struct xmit_frame *pxmitframe)
+{
+	return padapter->hal_func.hal_xmit(padapter, pxmitframe);
+}
+
+/*
+ * [IMPORTANT] This function would be run in interrupt context.
+ */
+s32	rtw_hal_mgnt_xmit(_adapter *padapter, struct xmit_frame *pmgntframe)
+{
+	s32 ret = _FAIL;
+
+	update_mgntframe_attrib_addr(padapter, pmgntframe);
+
+#if defined(CONFIG_IEEE80211W) || defined(CONFIG_RTW_MESH)
+	if ((!MLME_IS_MESH(padapter) && SEC_IS_BIP_KEY_INSTALLED(&padapter->securitypriv) == _TRUE)
+		#ifdef CONFIG_RTW_MESH
+		|| (MLME_IS_MESH(padapter) && padapter->mesh_info.mesh_auth_id)
+		#endif
+	)
+		rtw_mgmt_xmitframe_coalesce(padapter, pmgntframe->pkt, pmgntframe);
+#endif
+
+no_mgmt_coalesce:
+	ret = padapter->hal_func.mgnt_xmit(padapter, pmgntframe);
+	return ret;
+}
+
+s32	rtw_hal_init_xmit_priv(_adapter *padapter)
+{
+	return padapter->hal_func.init_xmit_priv(padapter);
+}
+void	rtw_hal_free_xmit_priv(_adapter *padapter)
+{
+	padapter->hal_func.free_xmit_priv(padapter);
+}
+
+s32	rtw_hal_init_recv_priv(_adapter *padapter)
+{
+	return padapter->hal_func.init_recv_priv(padapter);
+}
+void	rtw_hal_free_recv_priv(_adapter *padapter)
+{
+	padapter->hal_func.free_recv_priv(padapter);
+}
+
+void rtw_sta_ra_registed(_adapter *padapter, struct sta_info *psta)
+{
+	struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
+	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(padapter);
+
+	if (psta == NULL) {
+		RTW_ERR(FUNC_ADPT_FMT" sta is NULL\n", FUNC_ADPT_ARG(padapter));
+		rtw_warn_on(1);
+		return;
+	}
+
+#ifdef CONFIG_AP_MODE
+	if (MLME_IS_AP(padapter) || MLME_IS_MESH(padapter)) {
+		if (psta->cmn.aid > padapter->stapriv.max_aid) {
+			RTW_ERR("station aid %d exceed the max number\n", psta->cmn.aid);
+			rtw_warn_on(1);
+			return;
+		}
+		rtw_ap_update_sta_ra_info(padapter, psta);
+	}
+#endif
+
+	psta->cmn.ra_info.ra_bw_mode = rtw_get_tx_bw_mode(padapter, psta);
+	/*set correct initial date rate for each mac_id */
+	hal_data->INIDATA_RATE[psta->cmn.mac_id] = psta->init_rate;
+
+	rtw_phydm_ra_registed(padapter, psta);
+}
+
+void rtw_hal_update_ra_mask(struct sta_info *psta)
+{
+	_adapter *padapter;
+
+	if (!psta)
+		return;
+
+	padapter = psta->padapter;
+	rtw_sta_ra_registed(padapter, psta);
+}
+
+/*	Start specifical interface thread		*/
+void	rtw_hal_start_thread(_adapter *padapter)
+{
+#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
+#ifndef CONFIG_SDIO_TX_TASKLET
+	padapter->hal_func.run_thread(padapter);
+#endif
+#endif
+}
+/*	Start specifical interface thread		*/
+void	rtw_hal_stop_thread(_adapter *padapter)
+{
+#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
+#ifndef CONFIG_SDIO_TX_TASKLET
+
+	padapter->hal_func.cancel_thread(padapter);
+
+#endif
+#endif
+}
+
+u32	rtw_hal_read_bbreg(_adapter *padapter, u32 RegAddr, u32 BitMask)
+{
+	u32 data = 0;
+	if (padapter->hal_func.read_bbreg)
+		data = padapter->hal_func.read_bbreg(padapter, RegAddr, BitMask);
+	return data;
+}
+void	rtw_hal_write_bbreg(_adapter *padapter, u32 RegAddr, u32 BitMask, u32 Data)
+{
+	if (padapter->hal_func.write_bbreg)
+		padapter->hal_func.write_bbreg(padapter, RegAddr, BitMask, Data);
+}
+
+u32 rtw_hal_read_rfreg(_adapter *padapter, enum rf_path eRFPath, u32 RegAddr, u32 BitMask)
+{
+	u32 data = 0;
+
+	if (padapter->hal_func.read_rfreg) {
+		data = padapter->hal_func.read_rfreg(padapter, eRFPath, RegAddr, BitMask);
+
+		#ifdef DBG_IO
+		if (match_rf_read_sniff_ranges(padapter, eRFPath, RegAddr, BitMask)) {
+			RTW_INFO("DBG_IO rtw_hal_read_rfreg(%u, 0x%04x, 0x%08x) read:0x%08x(0x%08x)\n"
+				, eRFPath, RegAddr, BitMask, (data << PHY_CalculateBitShift(BitMask)), data);
+		}
+		#endif
+	}
+
+	return data;
+}
+
+void rtw_hal_write_rfreg(_adapter *padapter, enum rf_path eRFPath, u32 RegAddr, u32 BitMask, u32 Data)
+{
+	if (padapter->hal_func.write_rfreg) {
+
+		#ifdef DBG_IO
+		if (match_rf_write_sniff_ranges(padapter, eRFPath, RegAddr, BitMask)) {
+			RTW_INFO("DBG_IO rtw_hal_write_rfreg(%u, 0x%04x, 0x%08x) write:0x%08x(0x%08x)\n"
+				, eRFPath, RegAddr, BitMask, (Data << PHY_CalculateBitShift(BitMask)), Data);
+		}
+		#endif
+
+		padapter->hal_func.write_rfreg(padapter, eRFPath, RegAddr, BitMask, Data);
+
+#ifdef CONFIG_PCI_HCI
+		if (!IS_HARDWARE_TYPE_JAGUAR_AND_JAGUAR2(padapter)) /*For N-Series IC, suggest by Jenyu*/
+			rtw_udelay_os(2);
+#endif
+	}
+}
+
+#ifdef CONFIG_SYSON_INDIRECT_ACCESS
+u32 rtw_hal_read_syson_reg(PADAPTER padapter, u32 RegAddr, u32 BitMask)
+{
+	u32 data = 0;
+	if (padapter->hal_func.read_syson_reg)
+		data = padapter->hal_func.read_syson_reg(padapter, RegAddr, BitMask);
+
+	return data;
+}
+
+void rtw_hal_write_syson_reg(_adapter *padapter, u32 RegAddr, u32 BitMask, u32 Data)
+{
+	if (padapter->hal_func.write_syson_reg)
+		padapter->hal_func.write_syson_reg(padapter, RegAddr, BitMask, Data);
+}
+#endif
+
+#if defined(CONFIG_PCI_HCI)
+s32	rtw_hal_interrupt_handler(_adapter *padapter)
+{
+	s32 ret = _FAIL;
+	ret = padapter->hal_func.interrupt_handler(padapter);
+	return ret;
+}
+#endif
+#if defined(CONFIG_USB_HCI) && defined(CONFIG_SUPPORT_USB_INT)
+void	rtw_hal_interrupt_handler(_adapter *padapter, u16 pkt_len, u8 *pbuf)
+{
+	padapter->hal_func.interrupt_handler(padapter, pkt_len, pbuf);
+}
+#endif
+
+void	rtw_hal_set_chnl_bw(_adapter *padapter, u8 channel, enum channel_width Bandwidth, u8 Offset40, u8 Offset80)
+{
+	PHAL_DATA_TYPE	pHalData = GET_HAL_DATA(padapter);
+	u8 cch_160 = Bandwidth == CHANNEL_WIDTH_160 ? channel : 0;
+	u8 cch_80 = Bandwidth == CHANNEL_WIDTH_80 ? channel : 0;
+	u8 cch_40 = Bandwidth == CHANNEL_WIDTH_40 ? channel : 0;
+	u8 cch_20 = Bandwidth == CHANNEL_WIDTH_20 ? channel : 0;
+
+	if (rtw_phydm_is_iqk_in_progress(padapter))
+		RTW_ERR("%s, %d, IQK may race condition\n", __func__, __LINE__);
+
+#ifdef CONFIG_MP_INCLUDED
+	/* MP mode channel don't use secondary channel */
+	if (rtw_mp_mode_check(padapter) == _FALSE)
+#endif
+	{
+		#if 0
+		if (cch_160 != 0)
+			cch_80 = rtw_get_scch_by_cch_offset(cch_160, CHANNEL_WIDTH_160, Offset80);
+		#endif
+		if (cch_80 != 0)
+			cch_40 = rtw_get_scch_by_cch_offset(cch_80, CHANNEL_WIDTH_80, Offset80);
+		if (cch_40 != 0)
+			cch_20 = rtw_get_scch_by_cch_offset(cch_40, CHANNEL_WIDTH_40, Offset40);
+	}
+
+	pHalData->cch_80 = cch_80;
+	pHalData->cch_40 = cch_40;
+	pHalData->cch_20 = cch_20;
+
+	if (0)
+		RTW_INFO("%s cch:%u, %s, offset40:%u, offset80:%u (%u, %u, %u)\n", __func__
+			, channel, ch_width_str(Bandwidth), Offset40, Offset80
+			, pHalData->cch_80, pHalData->cch_40, pHalData->cch_20);
+
+	padapter->hal_func.set_chnl_bw_handler(padapter, channel, Bandwidth, Offset40, Offset80);
+}
+
+void	rtw_hal_set_tx_power_level(_adapter *padapter, u8 channel)
+{
+	if (padapter->hal_func.set_tx_power_level_handler)
+		padapter->hal_func.set_tx_power_level_handler(padapter, channel);
+}
+
+void	rtw_hal_get_tx_power_level(_adapter *padapter, s32 *powerlevel)
+{
+	if (padapter->hal_func.get_tx_power_level_handler)
+		padapter->hal_func.get_tx_power_level_handler(padapter, powerlevel);
+}
+
+void	rtw_hal_dm_watchdog(_adapter *padapter)
+{
+
+	rtw_hal_turbo_edca(padapter);
+	padapter->hal_func.hal_dm_watchdog(padapter);
+
+#ifdef CONFIG_PCI_DYNAMIC_ASPM
+	rtw_pci_aspm_config_dynamic_l1_ilde_time(padapter);
+#endif
+}
+
+#ifdef CONFIG_LPS_LCLK_WD_TIMER
+void	rtw_hal_dm_watchdog_in_lps(_adapter *padapter)
+{
+#if defined(CONFIG_CONCURRENT_MODE)
+#ifndef CONFIG_FW_MULTI_PORT_SUPPORT
+	if (padapter->hw_port != HW_PORT0)
+		return;
+#endif
+#endif
+
+	if (adapter_to_pwrctl(padapter)->bFwCurrentInPSMode == _TRUE)
+		rtw_phydm_watchdog_in_lps_lclk(padapter);/* this function caller is in interrupt context */
+}
+#endif /*CONFIG_LPS_LCLK_WD_TIMER*/
+
+void rtw_hal_bcn_related_reg_setting(_adapter *padapter)
+{
+	padapter->hal_func.SetBeaconRelatedRegistersHandler(padapter);
+}
+
+#ifdef CONFIG_HOSTAPD_MLME
+s32	rtw_hal_hostap_mgnt_xmit_entry(_adapter *padapter, _pkt *pkt)
+{
+	if (padapter->hal_func.hostap_mgnt_xmit_entry)
+		return padapter->hal_func.hostap_mgnt_xmit_entry(padapter, pkt);
+	return _FAIL;
+}
+#endif /* CONFIG_HOSTAPD_MLME */
+
+#ifdef DBG_CONFIG_ERROR_DETECT
+void	rtw_hal_sreset_init(_adapter *padapter)
+{
+	padapter->hal_func.sreset_init_value(padapter);
+}
+void rtw_hal_sreset_reset(_adapter *padapter)
+{
+	padapter = GET_PRIMARY_ADAPTER(padapter);
+	padapter->hal_func.silentreset(padapter);
+}
+
+void rtw_hal_sreset_reset_value(_adapter *padapter)
+{
+	padapter->hal_func.sreset_reset_value(padapter);
+}
+
+void rtw_hal_sreset_xmit_status_check(_adapter *padapter)
+{
+	padapter->hal_func.sreset_xmit_status_check(padapter);
+}
+void rtw_hal_sreset_linked_status_check(_adapter *padapter)
+{
+	padapter->hal_func.sreset_linked_status_check(padapter);
+}
+u8   rtw_hal_sreset_get_wifi_status(_adapter *padapter)
+{
+	return padapter->hal_func.sreset_get_wifi_status(padapter);
+}
+
+bool rtw_hal_sreset_inprogress(_adapter *padapter)
+{
+	padapter = GET_PRIMARY_ADAPTER(padapter);
+	return padapter->hal_func.sreset_inprogress(padapter);
+}
+#endif /* DBG_CONFIG_ERROR_DETECT */
+
+#ifdef CONFIG_IOL
+int rtw_hal_iol_cmd(ADAPTER *adapter, struct xmit_frame *xmit_frame, u32 max_waiting_ms, u32 bndy_cnt)
+{
+	if (adapter->hal_func.IOL_exec_cmds_sync)
+		return adapter->hal_func.IOL_exec_cmds_sync(adapter, xmit_frame, max_waiting_ms, bndy_cnt);
+	return _FAIL;
+}
+#endif
+
+#ifdef CONFIG_XMIT_THREAD_MODE
+s32 rtw_hal_xmit_thread_handler(_adapter *padapter)
+{
+	return padapter->hal_func.xmit_thread_handler(padapter);
+}
+#endif
+
+#ifdef CONFIG_RECV_THREAD_MODE
+s32 rtw_hal_recv_hdl(_adapter *adapter)
+{
+	return adapter->hal_func.recv_hdl(adapter);
+}
+#endif
+
+void rtw_hal_notch_filter(_adapter *adapter, bool enable)
+{
+	if (adapter->hal_func.hal_notch_filter)
+		adapter->hal_func.hal_notch_filter(adapter, enable);
+}
+
+#ifdef CONFIG_FW_C2H_REG
+inline bool rtw_hal_c2h_valid(_adapter *adapter, u8 *buf)
+{
+	HAL_DATA_TYPE *HalData = GET_HAL_DATA(adapter);
+	HAL_VERSION *hal_ver = &HalData->version_id;
+	bool ret = _FAIL;
+
+	ret = C2H_ID_88XX(buf) || C2H_PLEN_88XX(buf);
+
+	return ret;
+}
+
+inline s32 rtw_hal_c2h_evt_read(_adapter *adapter, u8 *buf)
+{
+	HAL_DATA_TYPE *HalData = GET_HAL_DATA(adapter);
+	HAL_VERSION *hal_ver = &HalData->version_id;
+	s32 ret = _FAIL;
+
+	ret = c2h_evt_read_88xx(adapter, buf);
+
+	return ret;
+}
+
+bool rtw_hal_c2h_reg_hdr_parse(_adapter *adapter, u8 *buf, u8 *id, u8 *seq, u8 *plen, u8 **payload)
+{
+	HAL_DATA_TYPE *HalData = GET_HAL_DATA(adapter);
+	HAL_VERSION *hal_ver = &HalData->version_id;
+	bool ret = _FAIL;
+
+	*id = C2H_ID_88XX(buf);
+	*seq = C2H_SEQ_88XX(buf);
+	*plen = C2H_PLEN_88XX(buf);
+	*payload = C2H_PAYLOAD_88XX(buf);
+	ret = _SUCCESS;
+
+	return ret;
+}
+#endif /* CONFIG_FW_C2H_REG */
+
+#ifdef CONFIG_FW_C2H_PKT
+bool rtw_hal_c2h_pkt_hdr_parse(_adapter *adapter, u8 *buf, u16 len, u8 *id, u8 *seq, u8 *plen, u8 **payload)
+{
+	HAL_DATA_TYPE *HalData = GET_HAL_DATA(adapter);
+	HAL_VERSION *hal_ver = &HalData->version_id;
+	bool ret = _FAIL;
+
+	if (!buf || len > 256 || len < 3)
+		goto exit;
+
+	*id = C2H_ID_88XX(buf);
+	*seq = C2H_SEQ_88XX(buf);
+	*plen = len - 2;
+	*payload = C2H_PAYLOAD_88XX(buf);
+	ret = _SUCCESS;
+
+exit:
+	return ret;
+}
+#endif /* CONFIG_FW_C2H_PKT */
+
+#if defined(CONFIG_MP_INCLUDED) && defined(CONFIG_RTL8723B)
+#include <rtw_bt_mp.h> /* for MPTBT_FwC2hBtMpCtrl */
+#endif
+s32 c2h_handler(_adapter *adapter, u8 id, u8 seq, u8 plen, u8 *payload)
+{
+	u8 sub_id = 0;
+	s32 ret = _SUCCESS;
+
+	switch (id) {
+	case C2H_FW_SCAN_COMPLETE:
+		RTW_INFO("[C2H], FW Scan Complete\n");
+		break;
+
+#ifdef CONFIG_BT_COEXIST
+	case C2H_BT_INFO:
+		rtw_btcoex_BtInfoNotify(adapter, plen, payload);
+		break;
+	case C2H_BT_MP_INFO:
+		#if defined(CONFIG_MP_INCLUDED) && defined(CONFIG_RTL8723B)
+		MPTBT_FwC2hBtMpCtrl(adapter, payload, plen);
+		#endif
+		rtw_btcoex_BtMpRptNotify(adapter, plen, payload);
+		break;
+	case C2H_MAILBOX_STATUS:
+		RTW_DBG_DUMP("C2H_MAILBOX_STATUS: ", payload, plen);
+		break;
+	case C2H_WLAN_INFO:
+		rtw_btcoex_WlFwDbgInfoNotify(adapter, payload, plen);
+		break;
+#endif /* CONFIG_BT_COEXIST */
+
+	case C2H_IQK_FINISH:
+		c2h_iqk_offload(adapter, payload, plen);
+		break;
+
+#if defined(CONFIG_TDLS) && defined(CONFIG_TDLS_CH_SW)
+	case C2H_FW_CHNL_SWITCH_COMPLETE:
+		rtw_tdls_chsw_oper_done(adapter);
+		break;
+	case C2H_BCN_EARLY_RPT:
+		rtw_tdls_ch_sw_back_to_base_chnl(adapter);
+		break;
+#endif
+
+#ifdef CONFIG_MCC_MODE
+	case C2H_MCC:
+		rtw_hal_mcc_c2h_handler(adapter, plen, payload);
+		break;
+#endif
+
+#ifdef CONFIG_RTW_MAC_HIDDEN_RPT
+	case C2H_MAC_HIDDEN_RPT:
+		c2h_mac_hidden_rpt_hdl(adapter, payload, plen);
+		break;
+	case C2H_MAC_HIDDEN_RPT_2:
+		c2h_mac_hidden_rpt_2_hdl(adapter, payload, plen);
+		break;
+#endif
+
+	case C2H_DEFEATURE_DBG:
+		c2h_defeature_dbg_hdl(adapter, payload, plen);
+		break;
+
+#ifdef CONFIG_RTW_CUSTOMER_STR
+	case C2H_CUSTOMER_STR_RPT:
+		c2h_customer_str_rpt_hdl(adapter, payload, plen);
+		break;
+	case C2H_CUSTOMER_STR_RPT_2:
+		c2h_customer_str_rpt_2_hdl(adapter, payload, plen);
+		break;
+#endif
+#ifdef RTW_PER_CMD_SUPPORT_FW
+	case C2H_PER_RATE_RPT:
+		c2h_per_rate_rpt_hdl(adapter, payload, plen);
+		break;
+#endif
+	case C2H_EXTEND:
+		sub_id = payload[0];
+		__attribute__((__fallthrough__));
+	default:
+		if (phydm_c2H_content_parsing(adapter_to_phydm(adapter), id, plen, payload) != TRUE)
+			ret = _FAIL;
+		break;
+	}
+
+exit:
+	if (ret != _SUCCESS) {
+		if (id == C2H_EXTEND)
+			RTW_WARN("%s: unknown C2H(0x%02x, 0x%02x)\n", __func__, id, sub_id);
+		else
+			RTW_WARN("%s: unknown C2H(0x%02x)\n", __func__, id);
+	}
+
+	return ret;
+}
+
+#ifndef RTW_HALMAC
+s32 rtw_hal_c2h_handler(_adapter *adapter, u8 id, u8 seq, u8 plen, u8 *payload)
+{
+	s32 ret = _FAIL;
+
+	ret = adapter->hal_func.c2h_handler(adapter, id, seq, plen, payload);
+	if (ret != _SUCCESS)
+		ret = c2h_handler(adapter, id, seq, plen, payload);
+
+	return ret;
+}
+
+s32 rtw_hal_c2h_id_handle_directly(_adapter *adapter, u8 id, u8 seq, u8 plen, u8 *payload)
+{
+	switch (id) {
+	case C2H_CCX_TX_RPT:
+	case C2H_BT_MP_INFO:
+	case C2H_FW_CHNL_SWITCH_COMPLETE:
+	case C2H_IQK_FINISH:
+	case C2H_MCC:
+	case C2H_BCN_EARLY_RPT:
+	case C2H_AP_REQ_TXRPT:
+	case C2H_SPC_STAT:
+		return _TRUE;
+	default:
+		return _FALSE;
+	}
+}
+#endif /* !RTW_HALMAC */
+
+s32 rtw_hal_is_disable_sw_channel_plan(PADAPTER padapter)
+{
+	return GET_HAL_DATA(padapter)->bDisableSWChannelPlan;
+}
+
+static s32 _rtw_hal_macid_sleep(_adapter *adapter, u8 macid, u8 sleep)
+{
+	struct macid_ctl_t *macid_ctl = adapter_to_macidctl(adapter);
+	u16 reg_sleep;
+	u8 bit_shift;
+	u32 val32;
+	s32 ret = _FAIL;
+
+	if (macid >= macid_ctl->num) {
+		RTW_ERR(ADPT_FMT" %s invalid macid(%u)\n"
+			, ADPT_ARG(adapter), sleep ? "sleep" : "wakeup" , macid);
+		goto exit;
+	}
+
+	if (macid < 32) {
+		reg_sleep = macid_ctl->reg_sleep_m0;
+		bit_shift = macid;
+	#if (MACID_NUM_SW_LIMIT > 32)
+	} else if (macid < 64) {
+		reg_sleep = macid_ctl->reg_sleep_m1;
+		bit_shift = macid - 32;
+	#endif
+	#if (MACID_NUM_SW_LIMIT > 64)
+	} else if (macid < 96) {
+		reg_sleep = macid_ctl->reg_sleep_m2;
+		bit_shift = macid - 64;
+	#endif
+	#if (MACID_NUM_SW_LIMIT > 96)
+	} else if (macid < 128) {
+		reg_sleep = macid_ctl->reg_sleep_m3;
+		bit_shift = macid - 96;
+	#endif
+	} else {
+		rtw_warn_on(1);
+		goto exit;
+	}
+
+	if (!reg_sleep) {
+		rtw_warn_on(1);
+		goto exit;
+	}
+
+	val32 = rtw_read32(adapter, reg_sleep);
+	RTW_INFO(ADPT_FMT" %s macid=%d, ori reg_0x%03x=0x%08x\n"
+		, ADPT_ARG(adapter), sleep ? "sleep" : "wakeup"
+		, macid, reg_sleep, val32);
+
+	ret = _SUCCESS;
+
+	if (sleep) {
+		if (val32 & BIT(bit_shift))
+			goto exit;
+		val32 |= BIT(bit_shift);
+	} else {
+		if (!(val32 & BIT(bit_shift)))
+			goto exit;
+		val32 &= ~BIT(bit_shift);
+	}
+
+	rtw_write32(adapter, reg_sleep, val32);
+
+exit:
+	return ret;
+}
+
+inline s32 rtw_hal_macid_sleep(_adapter *adapter, u8 macid)
+{
+	return _rtw_hal_macid_sleep(adapter, macid, 1);
+}
+
+inline s32 rtw_hal_macid_wakeup(_adapter *adapter, u8 macid)
+{
+	return _rtw_hal_macid_sleep(adapter, macid, 0);
+}
+
+static s32 _rtw_hal_macid_bmp_sleep(_adapter *adapter, struct macid_bmp *bmp, u8 sleep)
+{
+	struct macid_ctl_t *macid_ctl = adapter_to_macidctl(adapter);
+	u16 reg_sleep;
+	u32 m;
+	u8 mid = 0;
+	u32 val32;
+
+	do {
+		if (mid == 0) {
+			m = bmp->m0;
+			reg_sleep = macid_ctl->reg_sleep_m0;
+		#if (MACID_NUM_SW_LIMIT > 32)
+		} else if (mid == 1) {
+			m = bmp->m1;
+			reg_sleep = macid_ctl->reg_sleep_m1;
+		#endif
+		#if (MACID_NUM_SW_LIMIT > 64)
+		} else if (mid == 2) {
+			m = bmp->m2;
+			reg_sleep = macid_ctl->reg_sleep_m2;
+		#endif
+		#if (MACID_NUM_SW_LIMIT > 96)
+		} else if (mid == 3) {
+			m = bmp->m3;
+			reg_sleep = macid_ctl->reg_sleep_m3;
+		#endif
+		} else {
+			rtw_warn_on(1);
+			break;
+		}
+
+		if (m == 0)
+			goto move_next;
+
+		if (!reg_sleep) {
+			rtw_warn_on(1);
+			break;
+		}
+
+		val32 = rtw_read32(adapter, reg_sleep);
+		RTW_INFO(ADPT_FMT" %s m%u=0x%08x, ori reg_0x%03x=0x%08x\n"
+			, ADPT_ARG(adapter), sleep ? "sleep" : "wakeup"
+			, mid, m, reg_sleep, val32);
+
+		if (sleep) {
+			if ((val32 & m) == m)
+				goto move_next;
+			val32 |= m;
+		} else {
+			if ((val32 & m) == 0)
+				goto move_next;
+			val32 &= ~m;
+		}
+
+		rtw_write32(adapter, reg_sleep, val32);
+
+move_next:
+		mid++;
+	} while (mid * 32 < MACID_NUM_SW_LIMIT);
+
+	return _SUCCESS;
+}
+
+inline s32 rtw_hal_macid_sleep_all_used(_adapter *adapter)
+{
+	struct macid_ctl_t *macid_ctl = adapter_to_macidctl(adapter);
+
+	return _rtw_hal_macid_bmp_sleep(adapter, &macid_ctl->used, 1);
+}
+
+inline s32 rtw_hal_macid_wakeup_all_used(_adapter *adapter)
+{
+	struct macid_ctl_t *macid_ctl = adapter_to_macidctl(adapter);
+
+	return _rtw_hal_macid_bmp_sleep(adapter, &macid_ctl->used, 0);
+}
+
+s32 rtw_hal_fill_h2c_cmd(PADAPTER padapter, u8 ElementID, u32 CmdLen, u8 *pCmdBuffer)
+{
+	_adapter *pri_adapter = GET_PRIMARY_ADAPTER(padapter);
+
+	if (GET_HAL_DATA(pri_adapter)->bFWReady == _TRUE)
+		return padapter->hal_func.fill_h2c_cmd(padapter, ElementID, CmdLen, pCmdBuffer);
+	else if (padapter->registrypriv.mp_mode == 0)
+		RTW_PRINT(FUNC_ADPT_FMT" FW doesn't exit when no MP mode, by pass H2C id:0x%02x\n"
+			  , FUNC_ADPT_ARG(padapter), ElementID);
+	return _FAIL;
+}
+
+void rtw_hal_fill_fake_txdesc(_adapter *padapter, u8 *pDesc, u32 BufferLen,
+			      u8 IsPsPoll, u8 IsBTQosNull, u8 bDataFrame)
+{
+	padapter->hal_func.fill_fake_txdesc(padapter, pDesc, BufferLen, IsPsPoll, IsBTQosNull, bDataFrame);
+
+}
+
+u8 rtw_hal_get_txbuff_rsvd_page_num(_adapter *adapter, bool wowlan)
+{
+	u8 num = 0;
+
+
+	if (adapter->hal_func.hal_get_tx_buff_rsvd_page_num) {
+		num = adapter->hal_func.hal_get_tx_buff_rsvd_page_num(adapter, wowlan);
+	} else {
+#ifdef RTW_HALMAC
+		num = GET_HAL_DATA(adapter)->drv_rsvd_page_number;
+#endif /* RTW_HALMAC */
+	}
+
+	return num;
+}
+
+#ifdef CONFIG_GPIO_API
+void rtw_hal_update_hisr_hsisr_ind(_adapter *padapter, u32 flag)
+{
+	if (padapter->hal_func.update_hisr_hsisr_ind)
+		padapter->hal_func.update_hisr_hsisr_ind(padapter, flag);
+}
+
+int rtw_hal_gpio_func_check(_adapter *padapter, u8 gpio_num)
+{
+	int ret = _SUCCESS;
+
+	if (padapter->hal_func.hal_gpio_func_check)
+		ret = padapter->hal_func.hal_gpio_func_check(padapter, gpio_num);
+
+	return ret;
+}
+
+void rtw_hal_gpio_multi_func_reset(_adapter *padapter, u8 gpio_num)
+{
+	if (padapter->hal_func.hal_gpio_multi_func_reset)
+		padapter->hal_func.hal_gpio_multi_func_reset(padapter, gpio_num);
+}
+#endif
+
+#ifdef CONFIG_FW_CORRECT_BCN
+void rtw_hal_fw_correct_bcn(_adapter *padapter)
+{
+	if (padapter->hal_func.fw_correct_bcn)
+		padapter->hal_func.fw_correct_bcn(padapter);
+}
+#endif
+
+void rtw_hal_set_tx_power_index(PADAPTER padapter, u32 powerindex, enum rf_path rfpath, u8 rate)
+{
+	return padapter->hal_func.set_tx_power_index_handler(padapter, powerindex, rfpath, rate);
+}
+
+u8 rtw_hal_get_tx_power_index(PADAPTER padapter, enum rf_path rfpath, u8 rate, u8 bandwidth, u8 channel, struct txpwr_idx_comp *tic)
+{
+	return padapter->hal_func.get_tx_power_index_handler(padapter, rfpath, rate, bandwidth, channel, tic);
+}
+
+#ifdef RTW_HALMAC
+/*
+ * Description:
+ *	Initialize MAC registers
+ *
+ * Return:
+ *	_TRUE	success
+ *	_FALSE	fail
+ */
+u8 rtw_hal_init_mac_register(PADAPTER adapter)
+{
+	return adapter->hal_func.init_mac_register(adapter);
+}
+
+/*
+ * Description:
+ *	Initialize PHY(BB/RF) related functions
+ *
+ * Return:
+ *	_TRUE	success
+ *	_FALSE	fail
+ */
+u8 rtw_hal_init_phy(PADAPTER adapter)
+{
+	return adapter->hal_func.init_phy(adapter);
+}
+#endif /* RTW_HALMAC */
+
+#ifdef CONFIG_RFKILL_POLL
+bool rtw_hal_rfkill_poll(_adapter *adapter, u8 *valid)
+{
+	bool ret;
+
+	if (adapter->hal_func.hal_radio_onoff_check)
+		ret = adapter->hal_func.hal_radio_onoff_check(adapter, valid);
+	else {
+		*valid = 0;
+		ret = _FALSE;
+	}
+	return ret;
+}
+#endif
+
+#define rtw_hal_error_msg(ops_fun)		\
+	RTW_PRINT("### %s - Error : Please hook hal_func.%s ###\n", __FUNCTION__, ops_fun)
+
+u8 rtw_hal_ops_check(_adapter *padapter)
+{
+	u8 ret = _SUCCESS;
+#if 1
+	/*** initialize section ***/
+	if (NULL == padapter->hal_func.read_chip_version) {
+		rtw_hal_error_msg("read_chip_version");
+		ret = _FAIL;
+	}
+	if (NULL == padapter->hal_func.init_default_value) {
+		rtw_hal_error_msg("init_default_value");
+		ret = _FAIL;
+	}
+	if (NULL == padapter->hal_func.intf_chip_configure) {
+		rtw_hal_error_msg("intf_chip_configure");
+		ret = _FAIL;
+	}
+	if (NULL == padapter->hal_func.read_adapter_info) {
+		rtw_hal_error_msg("read_adapter_info");
+		ret = _FAIL;
+	}
+
+	if (NULL == padapter->hal_func.hal_power_on) {
+		rtw_hal_error_msg("hal_power_on");
+		ret = _FAIL;
+	}
+	if (NULL == padapter->hal_func.hal_power_off) {
+		rtw_hal_error_msg("hal_power_off");
+		ret = _FAIL;
+	}
+
+	if (NULL == padapter->hal_func.hal_init) {
+		rtw_hal_error_msg("hal_init");
+		ret = _FAIL;
+	}
+	if (NULL == padapter->hal_func.hal_deinit) {
+		rtw_hal_error_msg("hal_deinit");
+		ret = _FAIL;
+	}
+
+	/*** xmit section ***/
+	if (NULL == padapter->hal_func.init_xmit_priv) {
+		rtw_hal_error_msg("init_xmit_priv");
+		ret = _FAIL;
+	}
+	if (NULL == padapter->hal_func.free_xmit_priv) {
+		rtw_hal_error_msg("free_xmit_priv");
+		ret = _FAIL;
+	}
+	if (NULL == padapter->hal_func.hal_xmit) {
+		rtw_hal_error_msg("hal_xmit");
+		ret = _FAIL;
+	}
+	if (NULL == padapter->hal_func.mgnt_xmit) {
+		rtw_hal_error_msg("mgnt_xmit");
+		ret = _FAIL;
+	}
+#ifdef CONFIG_XMIT_THREAD_MODE
+	if (NULL == padapter->hal_func.xmit_thread_handler) {
+		rtw_hal_error_msg("xmit_thread_handler");
+		ret = _FAIL;
+	}
+#endif
+	if (NULL == padapter->hal_func.hal_xmitframe_enqueue) {
+		rtw_hal_error_msg("hal_xmitframe_enqueue");
+		ret = _FAIL;
+	}
+#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
+#ifndef CONFIG_SDIO_TX_TASKLET
+	if (NULL == padapter->hal_func.run_thread) {
+		rtw_hal_error_msg("run_thread");
+		ret = _FAIL;
+	}
+	if (NULL == padapter->hal_func.cancel_thread) {
+		rtw_hal_error_msg("cancel_thread");
+		ret = _FAIL;
+	}
+#endif
+#endif
+
+	/*** recv section ***/
+	if (NULL == padapter->hal_func.init_recv_priv) {
+		rtw_hal_error_msg("init_recv_priv");
+		ret = _FAIL;
+	}
+	if (NULL == padapter->hal_func.free_recv_priv) {
+		rtw_hal_error_msg("free_recv_priv");
+		ret = _FAIL;
+	}
+#ifdef CONFIG_RECV_THREAD_MODE
+	if (NULL == padapter->hal_func.recv_hdl) {
+		rtw_hal_error_msg("recv_hdl");
+		ret = _FAIL;
+	}
+#endif
+#if defined(CONFIG_USB_HCI) || defined(CONFIG_PCI_HCI)
+	if (NULL == padapter->hal_func.inirp_init) {
+		rtw_hal_error_msg("inirp_init");
+		ret = _FAIL;
+	}
+	if (NULL == padapter->hal_func.inirp_deinit) {
+		rtw_hal_error_msg("inirp_deinit");
+		ret = _FAIL;
+	}
+#endif /* #if defined(CONFIG_USB_HCI) || defined (CONFIG_PCI_HCI) */
+
+
+	/*** interrupt hdl section ***/
+#if defined(CONFIG_PCI_HCI)
+	if (NULL == padapter->hal_func.irp_reset) {
+		rtw_hal_error_msg("irp_reset");
+		ret = _FAIL;
+	}
+#endif/*#if defined(CONFIG_PCI_HCI)*/
+#if (defined(CONFIG_PCI_HCI)) || (defined(CONFIG_USB_HCI) && defined(CONFIG_SUPPORT_USB_INT))
+	if (NULL == padapter->hal_func.interrupt_handler) {
+		rtw_hal_error_msg("interrupt_handler");
+		ret = _FAIL;
+	}
+#endif /*#if (defined(CONFIG_PCI_HCI)) || (defined(CONFIG_USB_HCI) && defined(CONFIG_SUPPORT_USB_INT))*/
+
+#if defined(CONFIG_PCI_HCI) || defined(CONFIG_SDIO_HCI) || defined (CONFIG_GSPI_HCI)
+	if (NULL == padapter->hal_func.enable_interrupt) {
+		rtw_hal_error_msg("enable_interrupt");
+		ret = _FAIL;
+	}
+	if (NULL == padapter->hal_func.disable_interrupt) {
+		rtw_hal_error_msg("disable_interrupt");
+		ret = _FAIL;
+	}
+#endif /* defined(CONFIG_PCI_HCI) || defined (CONFIG_SDIO_HCI) || defined (CONFIG_GSPI_HCI) */
+
+
+	/*** DM section ***/
+	if (NULL == padapter->hal_func.dm_init) {
+		rtw_hal_error_msg("dm_init");
+		ret = _FAIL;
+	}
+	if (NULL == padapter->hal_func.dm_deinit) {
+		rtw_hal_error_msg("dm_deinit");
+		ret = _FAIL;
+	}
+	if (NULL == padapter->hal_func.hal_dm_watchdog) {
+		rtw_hal_error_msg("hal_dm_watchdog");
+		ret = _FAIL;
+	}
+
+	/*** xxx section ***/
+	if (NULL == padapter->hal_func.set_chnl_bw_handler) {
+		rtw_hal_error_msg("set_chnl_bw_handler");
+		ret = _FAIL;
+	}
+
+	if (NULL == padapter->hal_func.set_hw_reg_handler) {
+		rtw_hal_error_msg("set_hw_reg_handler");
+		ret = _FAIL;
+	}
+	if (NULL == padapter->hal_func.GetHwRegHandler) {
+		rtw_hal_error_msg("GetHwRegHandler");
+		ret = _FAIL;
+	}
+	if (NULL == padapter->hal_func.get_hal_def_var_handler) {
+		rtw_hal_error_msg("get_hal_def_var_handler");
+		ret = _FAIL;
+	}
+	if (NULL == padapter->hal_func.SetHalDefVarHandler) {
+		rtw_hal_error_msg("SetHalDefVarHandler");
+		ret = _FAIL;
+	}
+	if (NULL == padapter->hal_func.GetHalODMVarHandler) {
+		rtw_hal_error_msg("GetHalODMVarHandler");
+		ret = _FAIL;
+	}
+	if (NULL == padapter->hal_func.SetHalODMVarHandler) {
+		rtw_hal_error_msg("SetHalODMVarHandler");
+		ret = _FAIL;
+	}
+
+	if (NULL == padapter->hal_func.SetBeaconRelatedRegistersHandler) {
+		rtw_hal_error_msg("SetBeaconRelatedRegistersHandler");
+		ret = _FAIL;
+	}
+
+	if (NULL == padapter->hal_func.fill_h2c_cmd) {
+		rtw_hal_error_msg("fill_h2c_cmd");
+		ret = _FAIL;
+	}
+
+#ifdef RTW_HALMAC
+	if (NULL == padapter->hal_func.hal_mac_c2h_handler) {
+		rtw_hal_error_msg("hal_mac_c2h_handler");
+		ret = _FAIL;
+	}
+#elif !defined(CONFIG_RTL8188E)
+	if (NULL == padapter->hal_func.c2h_handler) {
+		rtw_hal_error_msg("c2h_handler");
+		ret = _FAIL;
+	}
+#endif
+
+#if defined(CONFIG_LPS) || defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN)
+	if (NULL == padapter->hal_func.fill_fake_txdesc) {
+		rtw_hal_error_msg("fill_fake_txdesc");
+		ret = _FAIL;
+	}
+#endif
+
+#ifndef RTW_HALMAC
+	if (NULL == padapter->hal_func.hal_get_tx_buff_rsvd_page_num) {
+		rtw_hal_error_msg("hal_get_tx_buff_rsvd_page_num");
+		ret = _FAIL;
+	}
+#endif /* !RTW_HALMAC */
+
+#if defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN)
+#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
+	if (NULL == padapter->hal_func.clear_interrupt) {
+		rtw_hal_error_msg("clear_interrupt");
+		ret = _FAIL;
+	}
+#endif
+#endif /* CONFIG_WOWLAN */
+
+	if (NULL == padapter->hal_func.fw_dl) {
+		rtw_hal_error_msg("fw_dl");
+		ret = _FAIL;
+	}
+
+#if defined(RTW_HALMAC) && defined(CONFIG_LPS_PG)
+	if (NULL == padapter->hal_func.fw_mem_dl) {
+		rtw_hal_error_msg("fw_mem_dl");
+		ret = _FAIL;
+	}
+#endif
+
+	#ifdef CONFIG_FW_CORRECT_BCN
+	if (IS_HARDWARE_TYPE_8814A(padapter)
+	    && NULL == padapter->hal_func.fw_correct_bcn) {
+		rtw_hal_error_msg("fw_correct_bcn");
+		ret = _FAIL;
+	}
+	#endif
+
+	if (!padapter->hal_func.set_tx_power_index_handler) {
+		rtw_hal_error_msg("set_tx_power_index_handler");
+		ret = _FAIL;
+	}
+	if (!padapter->hal_func.get_tx_power_index_handler) {
+		rtw_hal_error_msg("get_tx_power_index_handler");
+		ret = _FAIL;
+	}
+
+	/*** SReset section ***/
+#ifdef DBG_CONFIG_ERROR_DETECT
+	if (NULL == padapter->hal_func.sreset_init_value) {
+		rtw_hal_error_msg("sreset_init_value");
+		ret = _FAIL;
+	}
+	if (NULL == padapter->hal_func.sreset_reset_value) {
+		rtw_hal_error_msg("sreset_reset_value");
+		ret = _FAIL;
+	}
+	if (NULL == padapter->hal_func.silentreset) {
+		rtw_hal_error_msg("silentreset");
+		ret = _FAIL;
+	}
+	if (NULL == padapter->hal_func.sreset_xmit_status_check) {
+		rtw_hal_error_msg("sreset_xmit_status_check");
+		ret = _FAIL;
+	}
+	if (NULL == padapter->hal_func.sreset_linked_status_check) {
+		rtw_hal_error_msg("sreset_linked_status_check");
+		ret = _FAIL;
+	}
+	if (NULL == padapter->hal_func.sreset_get_wifi_status) {
+		rtw_hal_error_msg("sreset_get_wifi_status");
+		ret = _FAIL;
+	}
+	if (NULL == padapter->hal_func.sreset_inprogress) {
+		rtw_hal_error_msg("sreset_inprogress");
+		ret = _FAIL;
+	}
+#endif  /* #ifdef DBG_CONFIG_ERROR_DETECT */
+
+#ifdef RTW_HALMAC
+	if (NULL == padapter->hal_func.init_mac_register) {
+		rtw_hal_error_msg("init_mac_register");
+		ret = _FAIL;
+	}
+	if (NULL == padapter->hal_func.init_phy) {
+		rtw_hal_error_msg("init_phy");
+		ret = _FAIL;
+	}
+#endif /* RTW_HALMAC */
+
+#ifdef CONFIG_RFKILL_POLL
+	if (padapter->hal_func.hal_radio_onoff_check == NULL) {
+		rtw_hal_error_msg("hal_radio_onoff_check");
+		ret = _FAIL;
+	}
+#endif
+#endif
+	return  ret;
+}
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/halmac/halmac_2_platform.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/halmac/halmac_2_platform.h
--- linux-5.6.3/3rdparty/rtl8821ce/hal/halmac/halmac_2_platform.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/halmac/halmac_2_platform.h	2020-04-10 16:35:06.790658854 +0300
@@ -0,0 +1,87 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2015 - 2018 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ ******************************************************************************/
+
+#ifndef _HALMAC_2_PLATFORM_H_
+#define _HALMAC_2_PLATFORM_H_
+
+/*[Driver] always set BUILD_TEST =0*/
+#define BUILD_TEST	0
+
+#if BUILD_TEST
+#include "../Platform/App/Test/halmac_2_platformapi.h"
+#else
+/*[Driver] use their own header files*/
+#include <drv_conf.h>			/* for basic_types.h and osdep_service.h */
+#include <basic_types.h>		/* u8, u16, u32 and etc.*/
+#include <osdep_service.h>		/* __BIG_ENDIAN, __LITTLE_ENDIAN, _sema, _mutex */
+#endif
+
+/*[Driver] provide the define of NULL, u8, u16, u32*/
+#ifndef NULL
+#define NULL		((void *)0)
+#endif
+
+#define HALMAC_INLINE	inline
+
+/*
+ * Ignore following typedef because Linux already have these
+ * u8, u16, u32, s8, s16, s32
+ * __le16, __le32, __be16, __be32
+ */
+
+#define HALMAC_PLATFORM_LITTLE_ENDIAN	1
+#define HALMAC_PLATFORM_BIG_ENDIAN	0
+
+/* Note : Named HALMAC_PLATFORM_LITTLE_ENDIAN / HALMAC_PLATFORM_BIG_ENDIAN
+ * is not mandatory. But Little endian must be '1'. Big endian must be '0'
+ */
+/*[Driver] config the system endian*/
+#ifdef __LITTLE_ENDIAN
+#define HALMAC_SYSTEM_ENDIAN	HALMAC_PLATFORM_LITTLE_ENDIAN
+#else /* !__LITTLE_ENDIAN */
+#define HALMAC_SYSTEM_ENDIAN	HALMAC_PLATFORM_BIG_ENDIAN
+#endif /* !__LITTLE_ENDIAN */
+
+/*[Driver] config if the operating platform*/
+#define HALMAC_PLATFORM_WINDOWS		0
+#define HALMAC_PLATFORM_LINUX		1
+#define HALMAC_PLATFORM_AP		0
+/*[Driver] must set HALMAC_PLATFORM_TESTPROGRAM = 0*/
+#define HALMAC_PLATFORM_TESTPROGRAM	0
+
+/*[Driver] config if enable the dbg msg or notl*/
+#define HALMAC_DBG_MSG_ENABLE		1
+
+#define HALMAC_MSG_LEVEL_TRACE		3
+#define HALMAC_MSG_LEVEL_WARNING	2
+#define HALMAC_MSG_LEVEL_ERR		1
+#define HALMAC_MSG_LEVEL_NO_LOG		0
+/*[Driver] config halmac msg level
+ * Use HALMAC_MSG_LEVEL_XXXX
+ */
+#define HALMAC_MSG_LEVEL HALMAC_MSG_LEVEL_TRACE
+
+/*[Driver] define the Rx FIFO expanding mode packet size unit for 8821C and 8822B */
+/*Should be 8 Byte alignment*/
+#define HALMAC_RX_FIFO_EXPANDING_MODE_PKT_SIZE	80 /*Bytes*/
+
+#define HALMAC_USE_TYPEDEF		0
+
+/*[Driver] provide the type mutex*/
+/* Mutex type */
+typedef _mutex		HALMAC_MUTEX;
+
+#endif /* _HALMAC_2_PLATFORM_H_ */
+
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/halmac/halmac_88xx/halmac_8821c/halmac_8821c_cfg.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/halmac/halmac_88xx/halmac_8821c/halmac_8821c_cfg.h
--- linux-5.6.3/3rdparty/rtl8821ce/hal/halmac/halmac_88xx/halmac_8821c/halmac_8821c_cfg.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/halmac/halmac_88xx/halmac_8821c/halmac_8821c_cfg.h	2020-04-10 16:35:06.790658854 +0300
@@ -0,0 +1,65 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ ******************************************************************************/
+
+#ifndef _HALMAC_8821C_CFG_H_
+#define _HALMAC_8821C_CFG_H_
+
+#include "../../halmac_hw_cfg.h"
+#include "../halmac_88xx_cfg.h"
+
+#if HALMAC_8821C_SUPPORT
+
+#define TX_FIFO_SIZE_8821C	65536
+#define RX_FIFO_SIZE_8821C	16384
+#define TRX_SHARE_SIZE_8821C	32768
+
+#define RX_DESC_DUMMY_SIZE_8821C	72 /* 8 * 9 Bytes */
+#define RX_FIFO_EXPANDING_MODE_PKT_SIZE_MAX_8821C	80 /* 8 Byte alignment*/
+
+/* should be 8 Byte alignment*/
+#if (HALMAC_RX_FIFO_EXPANDING_MODE_PKT_SIZE <= \
+	RX_FIFO_EXPANDING_MODE_PKT_SIZE_MAX_8821C)
+#define RX_FIFO_EXPANDING_UNIT_8821C	(RX_DESC_SIZE_88XX + \
+	RX_DESC_DUMMY_SIZE_8821C + HALMAC_RX_FIFO_EXPANDING_MODE_PKT_SIZE)
+#else
+#define RX_FIFO_EXPANDING_UNIT_8821C	(RX_DESC_SIZE_88XX + \
+	RX_DESC_DUMMY_SIZE_8821C + RX_FIFO_EXPANDING_MODE_PKT_SIZE_MAX_8821C)
+#endif
+
+#define TX_FIFO_SIZE_LA_8821C	(TX_FIFO_SIZE_8821C >> 1)
+#define TX_FIFO_SIZE_RX_EXPAND_1BLK_8821C	\
+		(TX_FIFO_SIZE_8821C - TRX_SHARE_SIZE_8821C)
+#define RX_FIFO_SIZE_RX_EXPAND_1BLK_8821C	\
+		((((RX_FIFO_EXPANDING_UNIT_8821C << 8) - 1) >> 10) << 10)
+
+#define EFUSE_SIZE_8821C		512
+#define EEPROM_SIZE_8821C		512
+#define BT_EFUSE_SIZE_8821C		128
+
+#define SEC_CAM_NUM_8821C		64
+
+#define	OQT_ENTRY_AC_8821C		32
+#define OQT_ENTRY_NOAC_8821C		32
+#define MACID_MAX_8821C			128
+
+#define WLAN_FW_IRAM_MAX_SIZE_8821C	65536
+#define WLAN_FW_DRAM_MAX_SIZE_8821C	49152
+#define WLAN_FW_ERAM_MAX_SIZE_8821C	49152
+#define WLAN_FW_MAX_SIZE_8821C		(WLAN_FW_IRAM_MAX_SIZE_8821C + \
+	WLAN_FW_DRAM_MAX_SIZE_8821C + WLAN_FW_ERAM_MAX_SIZE_8821C)
+
+#endif /* HALMAC_8821C_SUPPORT */
+
+#endif
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/halmac/halmac_88xx/halmac_8821c/halmac_8821c_phy.c linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/halmac/halmac_88xx/halmac_8821c/halmac_8821c_phy.c
--- linux-5.6.3/3rdparty/rtl8821ce/hal/halmac/halmac_88xx/halmac_8821c/halmac_8821c_phy.c	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/halmac/halmac_88xx/halmac_8821c/halmac_8821c_phy.c	2020-04-10 16:35:06.790658854 +0300
@@ -0,0 +1,36 @@
+#include "../halmac_88xx_cfg.h"
+#include "halmac_8821c_cfg.h"
+
+/**
+ * ============ip sel item list============
+ * HALMAC_IP_SEL_INTF_PHY
+ *	USB2 : usb2 phy, 1byte value
+ *	USB3 : usb3 phy, 2byte value
+ *	PCIE1 : pcie gen1 mdio, 2byte value
+ *	PCIE2 : pcie gen2 mdio, 2byte value
+ * HALMAC_IP_SEL_MAC
+ *	USB2, USB3, PCIE1, PCIE2 : mac ip, 1byte value
+ * HALMAC_IP_SEL_PCIE_DBI
+ *	USB2 USB3 : none
+ *	PCIE1, PCIE2 : pcie dbi, 1byte value
+ */
+
+HALMAC_INTF_PHY_PARA HALMAC_RTL8821C_USB2_PHY[] = {
+	/* {offset, value, ip sel, cut mask, platform mask} */
+	{0xFFFF, 0x00, HALMAC_IP_SEL_INTF_PHY, HALMAC_INTF_PHY_CUT_ALL, HALMAC_INTF_PHY_PLATFORM_ALL},
+};
+
+HALMAC_INTF_PHY_PARA HALMAC_RTL8821C_USB3_PHY[] = {
+	/* {offset, value, cut mask, platform mask} */
+	{0xFFFF, 0x0000, HALMAC_IP_SEL_INTF_PHY, HALMAC_INTF_PHY_CUT_ALL, HALMAC_INTF_PHY_PLATFORM_ALL},
+};
+
+HALMAC_INTF_PHY_PARA HALMAC_RTL8821C_PCIE_PHY_GEN1[] = {
+	/* {offset, value, ip sel, cut mask, platform mask} */
+	{0xFFFF, 0x0000, HALMAC_IP_SEL_INTF_PHY, HALMAC_INTF_PHY_CUT_ALL, HALMAC_INTF_PHY_PLATFORM_ALL},
+};
+
+HALMAC_INTF_PHY_PARA HALMAC_RTL8821C_PCIE_PHY_GEN2[] = {
+	/* {offset, value, ip sel, cut mask, platform mask} */
+	{0xFFFF, 0x0000, HALMAC_IP_SEL_INTF_PHY, HALMAC_INTF_PHY_CUT_ALL, HALMAC_INTF_PHY_PLATFORM_ALL},
+};
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/halmac/halmac_88xx/halmac_8821c/halmac_8821c_pwr_seq.c linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/halmac/halmac_88xx/halmac_8821c/halmac_8821c_pwr_seq.c
--- linux-5.6.3/3rdparty/rtl8821ce/hal/halmac/halmac_88xx/halmac_8821c/halmac_8821c_pwr_seq.c	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/halmac/halmac_88xx/halmac_8821c/halmac_8821c_pwr_seq.c	2020-04-10 16:35:06.790658854 +0300
@@ -0,0 +1,239 @@
+#include "../halmac_88xx_cfg.h"
+#include "halmac_8821c_cfg.h"
+
+HALMAC_WLAN_PWR_CFG HALMAC_RTL8821C_TRANS_CARDEMU_TO_ACT[] = {
+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value } */
+	{0x0020, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_USB_MSK | HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(0), BIT(0)}, /*0x20[0] = 1b'1 enable LDOA12 MACRO block for all interface*/
+	{0x0001, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_USB_MSK | HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_DELAY, 1, HALMAC_PWRSEQ_DELAY_MS}, /*Delay 1ms*/
+	{0x0000, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_USB_MSK | HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(5), 0}, /*0x00[5] = 1b'0 release analog Ips to digital ,1:isolation*/
+	{0x0005, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, (BIT(4) | BIT(3) | BIT(2)), 0}, /* disable SW LPS 0x04[10]=0 and WLSUS_EN 0x04[12:11]=0*/
+	{0x0075, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_PCI_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(0), BIT(0)}, /* Disable USB suspend */
+	{0x0006, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_POLLING, BIT(1), BIT(1)}, /* wait till 0x04[17] = 1    power ready*/
+	{0x0075, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_PCI_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(0), 0 }, /* Enable USB suspend */
+	{0x0006, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(0), BIT(0)}, /* release WLON reset  0x04[16]=1*/
+	{0x0005, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(7), 0 }, /* disable HWPDN 0x04[15]=0*/
+	{0x0005, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, (BIT(4) | BIT(3)), 0}, /* disable WL suspend*/
+	{0x0005, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(0), BIT(0)}, /* polling until return 0*/
+	{0x0005, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_POLLING, BIT(0), 0},
+	{0x0020, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(3), BIT(3)}, /*Enable XTAL_CLK*/
+	{0x0074, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_PCI_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(5), BIT(5)}, /*0x74[5]=1 , PCIE WAKE# enabled*/
+	{0x0022, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_PCI_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(1), 0}, /*0x22[1]=0 , turn off usb bandgap*/
+	{0x0062, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_PCI_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, (BIT(7) | BIT(6) | BIT(5)), (BIT(7) | BIT(6) | BIT(5))}, /*PCIE , GPIO15/14/13 set to output mode*/
+	{0x0061, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_PCI_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, (BIT(7) | BIT(6) | BIT(5)), 0}, /*PCIE , GPIO15/14/13 set to output value 0*/
+	{0x007C, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(1), 0 }, /*SWR freq�אּ2.4MHz*/
+	{0xFFFF, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, 0, HALMAC_PWR_CMD_END, 0, 0},
+};
+
+HALMAC_WLAN_PWR_CFG HALMAC_RTL8821C_TRANS_ACT_TO_CARDEMU[] = {
+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value } */
+	{0x001F, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, 0xFF, 0}, /*0x1F[7:0] = 0 turn off RF*/
+	{0x0049, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(1), 0}, /*Enable rising edge triggering interrupt*/
+	{0x0006, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(0), BIT(0)}, /* release WLON reset  0x04[16]=1*/
+	{0x0002, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(1), 0}, /* Whole BB is reset */
+	{0x0005, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(1), BIT(1)}, /*0x04[9] = 1 turn off MAC by HW state machine*/
+	{0x0005, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_POLLING, BIT(1), 0}, /*wait till 0x04[9] = 0 polling until return 0 to disable*/
+	{0x0020, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(3), 0}, /* XTAL_CLK gated*/
+	{0x0000, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_USB_MSK | HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(5), BIT(5)}, /*0x00[5] = 1b'1 analog Ips to digital ,1:isolation*/
+	{0xFFFF, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, 0, HALMAC_PWR_CMD_END, 0, 0},
+};
+
+HALMAC_WLAN_PWR_CFG HALMAC_RTL8821C_TRANS_CARDEMU_TO_SUS[] = {
+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value } */
+	{0x0005, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_PCI_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(4) | BIT(3), (BIT(4) | BIT(3))}, /*0x04[12:11] = 2b'11 enable WL suspend for PCIe*/
+	{0x0005, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_USB_MSK | HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(3) | BIT(4), BIT(3)}, /*0x04[12:11] = 2b'01 enable WL suspend*/
+	{0x0007, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, 0xFF, 0x20}, /*0x07[7:0] = 0x20 SDIO SOP option to disable BG/MB/ACK/SWR*/
+	{0x0005, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_PCI_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(3) | BIT(4), BIT(3) | BIT(4)}, /*0x04[12:11] = 2b'11 enable WL suspend for PCIe*/
+	{0x0086, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_SDIO, HALMAC_PWR_CMD_WRITE, BIT(0), BIT(0)}, /*Set SDIO suspend local register*/
+	{0x0086, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_SDIO, HALMAC_PWR_CMD_POLLING, BIT(1), 0}, /*wait power state to suspend*/
+	{0xFFFF, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, 0, HALMAC_PWR_CMD_END, 0, 0},
+};
+
+HALMAC_WLAN_PWR_CFG HALMAC_RTL8821C_TRANS_SUS_TO_CARDEMU[] = {
+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value } */
+	{0x0005, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(3) | BIT(7), 0}, /*clear suspend enable and power down enable*/
+	{0x0086, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_SDIO, HALMAC_PWR_CMD_WRITE, BIT(0), 0}, /*Set SDIO suspend local register*/
+	{0x0086, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_SDIO, HALMAC_PWR_CMD_POLLING, BIT(1), BIT(1)}, /*wait power state to suspend*/
+	{0x0005, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(3) | BIT(4), 0}, /*0x04[12:11] = 2b'01enable WL suspend*/
+	{0xFFFF, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, 0, HALMAC_PWR_CMD_END, 0, 0},
+};
+
+HALMAC_WLAN_PWR_CFG HALMAC_RTL8821C_TRANS_CARDEMU_TO_CARDDIS[] = {
+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value } */
+	{0x0007, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_USB_MSK | HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, 0xFF, 0x20}, /* SOP option to disable BG/MB*/
+	{0x0067, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(5), 0}, /*BIT_PAPE_WLBT_SEL*/
+	{0x0005, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_USB_MSK | HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(3) | BIT(4), BIT(3)}, /*enable WL suspend*/
+	{0x0005, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_PCI_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(2), BIT(2)}, /*enable SW LPS*/
+	{0x004A, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_USB_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(0), 0}, /*disable GPIO9 as EXT WAKEUP*/
+	{0x0067, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(5), 0 }, /* 0: BT PAPE control ; 1: WL BB LNAON control*/
+	{0x0067, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(4), 0 }, /* 0: BT GPIO[11:10] control  ; 1: WL BB LNAON control*/
+	{0x004F, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(0), 0 }, /* 0: BT Control*/
+	{0x0067, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(1), 0 }, /* turn off BT_3DD_SYNC_B and BT_GPIO[18] */
+	{0x0046, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(6), BIT(6) }, /* GPIO[6] : Output mode*/
+	{0x0067, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(2), 0 }, /* turn off BT_GPIO[16] */
+	{0x0046, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(7), BIT(7) }, /* GPIO[7] : Output mode*/
+	{0x0062, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(4), BIT(4) }, /* GPIO[12] : Output mode */
+	{0x0086, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_SDIO, HALMAC_PWR_CMD_WRITE, BIT(0), BIT(0)}, /*Set SDIO suspend local register*/
+	{0x0086, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_SDIO, HALMAC_PWR_CMD_POLLING, BIT(1), 0}, /*wait power state to suspend*/
+	{0x0090, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_USB_MSK | HALMAC_PWR_INTF_PCI_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(1), 0}, /*disable 32k clock*/
+	{0x0044, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_SDIO, HALMAC_PWR_CMD_WRITE, 0xFF, 0}, /*disable 32k clock by indirect access*/
+	{0x0040, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_SDIO, HALMAC_PWR_CMD_WRITE, 0xFF, 0x90}, /*disable 32k clock by indirect access*/
+	{0x0041, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_SDIO, HALMAC_PWR_CMD_WRITE, 0xFF, 0x00}, /*disable 32k clock by indirect access*/
+	{0x0042, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_SDIO, HALMAC_PWR_CMD_WRITE, 0xFF, 0x04}, /*disable 32k clock by indirect access*/
+	{0xFFFF, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, 0, HALMAC_PWR_CMD_END, 0, 0},
+};
+
+HALMAC_WLAN_PWR_CFG HALMAC_RTL8821C_TRANS_CARDDIS_TO_CARDEMU[] = {
+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value } */
+	{0x0086, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_SDIO, HALMAC_PWR_CMD_WRITE, BIT(0), 0}, /*Set SDIO suspend local register*/
+	{0x0086, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_SDIO, HALMAC_PWR_CMD_POLLING, BIT(1), BIT(1)}, /*wait power state to suspend*/
+	{0x004A, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_USB_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(0), 0}, /*0x48[16] = 0 to disable GPIO9 as EXT WAKEUP*/
+	{0x0005, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(3) | BIT(4) | BIT(7), 0}, /*clear suspend enable and power down enable*/
+	{0x0301, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_PCI_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, 0xFF, 0}, /*PCIe DMA start*/
+	{0xFFFF, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, 0, HALMAC_PWR_CMD_END, 0, 0},
+};
+
+HALMAC_WLAN_PWR_CFG HALMAC_RTL8821C_TRANS_CARDEMU_TO_PDN[] = {
+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value } */
+	{0x0007, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_SDIO_MSK | HALMAC_PWR_INTF_USB_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, 0xFF, 0x20}, /*0x07[7:0] = 0x20 SOP option to disable BG/MB/ACK/SWR*/
+	{0x0006, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(0), 0}, /* 0x04[16] = 0*/
+	{0x0005, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(7), BIT(7)}, /* 0x04[15] = 1*/
+	{0xFFFF, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, 0, HALMAC_PWR_CMD_END, 0, 0},
+};
+
+HALMAC_WLAN_PWR_CFG HALMAC_RTL8821C_TRANS_PDN_TO_CARDEMU[] = {
+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value } */
+	{0x0005, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(7), 0},
+	{0xFFFF, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, 0, HALMAC_PWR_CMD_END, 0, 0},
+};
+
+HALMAC_WLAN_PWR_CFG HALMAC_RTL8821C_TRANS_ACT_TO_LPS[] = {
+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value } */
+	{0x0101, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(2), BIT(2)}, /*Enable 32k calibration and thermal meter*/
+	{0x0199, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(3), BIT(3)}, /*Register write data of 32K calibration*/
+	{0x019B, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(7), BIT(7)}, /*Enable 32k calibration reg write*/
+	{0x1138, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(0) | BIT(1), BIT(0) | BIT(1)}, /*set RPWM IMR*/
+	{0x0194, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(0), BIT(0)}, /* enable 32K CLK*/
+	{0x0093, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, 0xFF, 0x42}, /* LPS Option MAC OFF enable*/
+	{0x0092, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, 0xFF, 0x20}, /* LPS Option  Enable memory to deep sleep mode*/
+	{0x0090, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(1), BIT(1)}, /* enable reg use 32K CLK*/
+	{0x0301, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_PCI_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, 0xFF, 0xFF}, /*PCIe DMA stop*/
+	{0x0522, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, 0xFF, 0xFF}, /*Tx Pause*/
+	{0x05F8, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_POLLING, 0xFF, 0}, /*Should be zero if no packet is transmitting*/
+	{0x05F9, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_POLLING, 0xFF, 0}, /*Should be zero if no packet is transmitting*/
+	{0x05FA, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_POLLING, 0xFF, 0}, /*Should be zero if no packet is transmitting*/
+	{0x05FB, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_POLLING, 0xFF, 0}, /*Should be zero if no packet is transmitting*/
+	{0x0002, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(0), 0}, /*CCK and OFDM are disabled,and clock are gated*/
+	{0x0002, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_DELAY, 0, HALMAC_PWRSEQ_DELAY_US}, /*Delay 1us*/
+	{0x0002, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(1), 0}, /*Whole BB is reset*/
+	{0x0100, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, 0xFF, 0x3F}, /*Reset MAC TRX*/
+	{0x0101, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(1), 0}, /*check if removed later*/
+	{0x0553, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(5), BIT(5)}, /*Respond TxOK to scheduler*/
+	{0x0008, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(4), BIT(4)}, /* switch TSF clock to 32K*/
+	{0x0109, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_POLLING, BIT(7), BIT(7)}, /*Polling 0x109[7]=0  TSF in 40M*/
+	{0x0090, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(0), BIT(0)}, /* enable WL_LPS_EN*/
+	{0xFFFF, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, 0, HALMAC_PWR_CMD_END, 0, 0},
+};
+
+HALMAC_WLAN_PWR_CFG HALMAC_RTL8821C_TRANS_ACT_TO_DEEP_LPS[] = {
+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value } */
+	{0x0101, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(2), BIT(2)}, /*Enable 32k calibration and thermal meter*/
+	{0x0199, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(3), BIT(3)}, /*Register write data of 32K calibration*/
+	{0x019B, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(7), BIT(7)}, /*Enable 32k calibration reg write*/
+	{0x1138, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(0) | BIT(1), BIT(0) | BIT(1)}, /*set RPWM IMR*/
+	{0x0194, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(0), BIT(0)}, /* enable 32K CLK*/
+	{0x0093, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, 0xFF, 0x40}, /* LPS Option MAC OFF enable*/
+	{0x0092, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, 0xFF, 0x20}, /* LPS Option  Enable memory to deep sleep mode*/
+	{0x0090, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(1), BIT(1)}, /* enable reg use 32K CLK*/
+	{0x0301, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_PCI_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, 0xFF, 0xFF}, /*PCIe DMA stop*/
+	{0x0522, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, 0xFF, 0xFF}, /*Tx Pause*/
+	{0x05F8, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_POLLING, 0xFF, 0}, /*Should be zero if no packet is transmitting*/
+	{0x05F9, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_POLLING, 0xFF, 0}, /*Should be zero if no packet is transmitting*/
+	{0x05FA, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_POLLING, 0xFF, 0}, /*Should be zero if no packet is transmitting*/
+	{0x05FB, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_POLLING, 0xFF, 0}, /*Should be zero if no packet is transmitting*/
+	{0x0002, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(0), 0}, /*CCK and OFDM are disabled,and clock are gated*/
+	{0x0002, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_DELAY, 0, HALMAC_PWRSEQ_DELAY_US}, /*Delay 1us*/
+	{0x0002, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(1), 0}, /*Whole BB is reset*/
+	{0x0100, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, 0xFF, 0x3F}, /*Reset MAC TRX*/
+	{0x0101, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(1), 0}, /*check if removed later*/
+	{0x0553, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(5), BIT(5)}, /*Respond TxOK to scheduler*/
+	{0x0008, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(4), BIT(4)}, /* switch TSF clock to 32K*/
+	{0x0109, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_POLLING, BIT(7), BIT(7)}, /*Polling 0x109[7]=1  TSF in 32K*/
+	{0x0090, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(0), BIT(0)}, /* enable WL_LPS_EN*/
+	{0xFFFF, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, 0, HALMAC_PWR_CMD_END, 0, 0},
+};
+
+HALMAC_WLAN_PWR_CFG HALMAC_RTL8821C_TRANS_LPS_TO_ACT[] = {
+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value } */
+	{0x0080, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_SDIO, HALMAC_PWR_CMD_WRITE, BIT(7), BIT(7)}, /*SDIO RPWM*/
+	{0x0002, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_DELAY, 0, HALMAC_PWRSEQ_DELAY_MS}, /*Delay*/
+	{0x0080, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_SDIO, HALMAC_PWR_CMD_WRITE, BIT(7), 0}, /*SDIO RPWM*/
+	{0xFE58, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_USB_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, 0xFF, 0x84}, /*USB RPWM*/
+	{0x0361, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_PCI_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, 0xFF, 0x84}, /*PCIe RPWM*/
+	{0x0002, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_DELAY, 0, HALMAC_PWRSEQ_DELAY_MS}, /*Delay*/
+	{0x0008, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(4), 0}, /*switch TSF to 40M*/
+	{0x0109, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_POLLING, BIT(7), 0}, /*Polling 0x109[7]=0  TSF in 40M*/
+	{0x0101, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(1), BIT(1)},
+	{0x0100, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, 0xFF, 0xFF }, /*enable WMAC TRX*/
+	{0x0002, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(1) | BIT(0), BIT(1) | BIT(0)}, /*enable BB macro*/
+	{0x0522, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, 0xFF, 0},
+	{0x113C, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, 0xFF, 0x03}, /*clear RPWM INT*/
+	{0x0124, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, 0xFF, 0xFF}, /*clear FW INT*/
+	{0x0125, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, 0xFF, 0xFF}, /*clear FW INT*/
+	{0x0126, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, 0xFF, 0xFF}, /*clear FW INT*/
+	{0x0127, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, 0xFF, 0xFF}, /*clear FW INT*/
+	{0x0090, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(1), 0}, /* disable reg use 32K CLK*/
+	{0x0101, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(2), 0}, /*disable 32k calibration and thermal meter*/
+	{0xFFFF, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, 0, HALMAC_PWR_CMD_END, 0, 0},
+};
+
+/* Card Enable Array */
+PHALMAC_WLAN_PWR_CFG halmac_8821c_card_enable_flow[] = {
+	HALMAC_RTL8821C_TRANS_CARDDIS_TO_CARDEMU,
+	HALMAC_RTL8821C_TRANS_CARDEMU_TO_ACT,
+	NULL
+};
+
+/* Card Disable Array */
+PHALMAC_WLAN_PWR_CFG halmac_8821c_card_disable_flow[] = {
+	HALMAC_RTL8821C_TRANS_ACT_TO_CARDEMU,
+	HALMAC_RTL8821C_TRANS_CARDEMU_TO_CARDDIS,
+	NULL
+};
+
+/* Suspend Array */
+PHALMAC_WLAN_PWR_CFG halmac_8821c_suspend_flow[] = {
+	HALMAC_RTL8821C_TRANS_ACT_TO_CARDEMU,
+	HALMAC_RTL8821C_TRANS_CARDEMU_TO_SUS,
+	NULL
+};
+
+/* Resume Array */
+PHALMAC_WLAN_PWR_CFG halmac_8821c_resume_flow[] = {
+	HALMAC_RTL8821C_TRANS_SUS_TO_CARDEMU,
+	HALMAC_RTL8821C_TRANS_CARDEMU_TO_ACT,
+	NULL
+};
+
+/* HWPDN Array - HW behavior */
+PHALMAC_WLAN_PWR_CFG halmac_8821c_hwpdn_flow[] = {
+	NULL
+};
+
+/* Enter LPS - FW behavior */
+PHALMAC_WLAN_PWR_CFG halmac_8821c_enter_lps_flow[] = {
+	HALMAC_RTL8821C_TRANS_ACT_TO_LPS,
+	NULL
+};
+
+/* Enter Deep LPS - FW behavior */
+PHALMAC_WLAN_PWR_CFG halmac_8821c_enter_deep_lps_flow[] = {
+	HALMAC_RTL8821C_TRANS_ACT_TO_DEEP_LPS,
+	NULL
+};
+
+/* Leave LPS -FW behavior */
+PHALMAC_WLAN_PWR_CFG halmac_8821c_leave_lps_flow[] = {
+	HALMAC_RTL8821C_TRANS_LPS_TO_ACT,
+	NULL
+};
+
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/halmac/halmac_88xx/halmac_8821c/halmac_8821c_pwr_seq.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/halmac/halmac_88xx/halmac_8821c/halmac_8821c_pwr_seq.h
--- linux-5.6.3/3rdparty/rtl8821ce/hal/halmac/halmac_88xx/halmac_8821c/halmac_8821c_pwr_seq.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/halmac/halmac_88xx/halmac_8821c/halmac_8821c_pwr_seq.h	2020-04-10 16:35:06.790658854 +0300
@@ -0,0 +1,16 @@
+#ifndef HALMAC_POWER_SEQUENCE_8821C
+#define HALMAC_POWER_SEQUENCE_8821C
+
+#include "../../halmac_pwr_seq_cmd.h"
+
+#define HALMAC_8821C_PWR_SEQ_VER  "V13"
+extern PHALMAC_WLAN_PWR_CFG halmac_8821c_card_disable_flow[];
+extern PHALMAC_WLAN_PWR_CFG halmac_8821c_card_enable_flow[];
+extern PHALMAC_WLAN_PWR_CFG halmac_8821c_suspend_flow[];
+extern PHALMAC_WLAN_PWR_CFG halmac_8821c_resume_flow[];
+extern PHALMAC_WLAN_PWR_CFG halmac_8821c_hwpdn_flow[];
+extern PHALMAC_WLAN_PWR_CFG halmac_8821c_enter_lps_flow[];
+extern PHALMAC_WLAN_PWR_CFG halmac_8821c_enter_deep_lps_flow[];
+extern PHALMAC_WLAN_PWR_CFG halmac_8821c_leave_lps_flow[];
+
+#endif
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/halmac/halmac_88xx/halmac_8821c/halmac_api_8821c.c linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/halmac/halmac_88xx/halmac_8821c/halmac_api_8821c.c
--- linux-5.6.3/3rdparty/rtl8821ce/hal/halmac/halmac_88xx/halmac_8821c/halmac_api_8821c.c	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/halmac/halmac_88xx/halmac_8821c/halmac_api_8821c.c	2020-04-10 16:35:06.790658854 +0300
@@ -0,0 +1,287 @@
+#include "halmac_8821c_cfg.h"
+#include "halmac_func_8821c.h"
+#include "../halmac_func_88xx.h"
+
+
+/**
+ * halmac_mount_api_8821c() - attach functions to function pointer
+ * @pHalmac_adapter
+ *
+ * SD1 internal use
+ *
+ * Author : KaiYuan Chang/Ivan Lin
+ * Return : HALMAC_RET_STATUS
+ */
+HALMAC_RET_STATUS
+halmac_mount_api_8821c(
+	IN PHALMAC_ADAPTER pHalmac_adapter
+)
+{
+	PHALMAC_API pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api;
+
+	pHalmac_adapter->chip_id = HALMAC_CHIP_ID_8821C;
+	pHalmac_adapter->hw_config_info.efuse_size = HALMAC_EFUSE_SIZE_8821C;
+	pHalmac_adapter->hw_config_info.eeprom_size = HALMAC_EEPROM_SIZE_8821C;
+	pHalmac_adapter->hw_config_info.bt_efuse_size = HALMAC_BT_EFUSE_SIZE_8821C;
+	pHalmac_adapter->hw_config_info.cam_entry_num = HALMAC_SECURITY_CAM_ENTRY_NUM_8821C;
+	pHalmac_adapter->hw_config_info.txdesc_size = HALMAC_TX_DESC_SIZE_8821C;
+	pHalmac_adapter->hw_config_info.rxdesc_size = HALMAC_RX_DESC_SIZE_8821C;
+	pHalmac_adapter->hw_config_info.tx_fifo_size = HALMAC_TX_FIFO_SIZE_8821C;
+	pHalmac_adapter->hw_config_info.rx_fifo_size = HALMAC_RX_FIFO_SIZE_8821C;
+	pHalmac_adapter->hw_config_info.page_size = HALMAC_TX_PAGE_SIZE_8821C;
+	pHalmac_adapter->hw_config_info.tx_align_size = HALMAC_TX_ALIGN_SIZE_8821C;
+	pHalmac_adapter->hw_config_info.page_size_2_power = HALMAC_TX_PAGE_SIZE_2_POWER_8821C;
+
+	pHalmac_adapter->txff_allocation.rsvd_drv_pg_num = HALMAC_RSVD_DRV_PGNUM_8821C;
+
+#if HALMAC_8821C_SUPPORT
+	pHalmac_api->halmac_init_trx_cfg = halmac_init_trx_cfg_8821C;
+		pHalmac_api->halmac_init_protocol_cfg = halmac_init_protocol_cfg_8821c;
+	pHalmac_api->halmac_init_h2c = halmac_init_h2c_8821c;
+
+	if (HALMAC_INTERFACE_SDIO == pHalmac_adapter->halmac_interface) {
+		pHalmac_api->halmac_tx_allowed_sdio = halmac_tx_allowed_sdio_88xx;
+		pHalmac_api->halmac_cfg_tx_agg_align = halmac_cfg_tx_agg_align_sdio_88xx;
+		pHalmac_api->halmac_mac_power_switch = halmac_mac_power_switch_8821c_sdio;
+		pHalmac_api->halmac_phy_cfg = halmac_phy_cfg_8821c_sdio;
+		pHalmac_api->halmac_interface_integration_tuning = halmac_interface_integration_tuning_8821c_sdio;
+	} else if (HALMAC_INTERFACE_USB == pHalmac_adapter->halmac_interface) {
+		pHalmac_api->halmac_mac_power_switch = halmac_mac_power_switch_8821c_usb;
+		pHalmac_api->halmac_cfg_tx_agg_align = halmac_cfg_tx_agg_align_usb_not_support_88xx;
+		pHalmac_api->halmac_phy_cfg = halmac_phy_cfg_8821c_usb;
+		pHalmac_api->halmac_interface_integration_tuning = halmac_interface_integration_tuning_8821c_usb;
+	} else if (HALMAC_INTERFACE_PCIE == pHalmac_adapter->halmac_interface) {
+		pHalmac_api->halmac_mac_power_switch = halmac_mac_power_switch_8821c_pcie;
+		pHalmac_api->halmac_cfg_tx_agg_align = halmac_cfg_tx_agg_align_pcie_not_support_88xx;
+		pHalmac_api->halmac_pcie_switch = halmac_pcie_switch_8821c;
+		pHalmac_api->halmac_phy_cfg = halmac_phy_cfg_8821c_pcie;
+		pHalmac_api->halmac_interface_integration_tuning = halmac_interface_integration_tuning_8821c_pcie;
+	} else {
+		pHalmac_api->halmac_pcie_switch = halmac_pcie_switch_8821c_nc;
+	}
+#endif
+
+	return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * halmac_init_trx_cfg_8821c() - config trx dma register
+ * @pHalmac_adapter : the adapter of halmac
+ * @halmac_trx_mode : trx mode selection
+ * Author : KaiYuan Chang/Ivan Lin
+ * Return : HALMAC_RET_STATUS
+ * More details of status code can be found in prototype document
+ */
+HALMAC_RET_STATUS
+halmac_init_trx_cfg_8821C(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN HALMAC_TRX_MODE halmac_trx_mode
+)
+{
+	u8 value8;
+	u32 value32;
+	VOID *pDriver_adapter = NULL;
+	PHALMAC_API pHalmac_api;
+	HALMAC_RET_STATUS status = HALMAC_RET_SUCCESS;
+
+	if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter))
+		return HALMAC_RET_ADAPTER_INVALID;
+
+	if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter))
+		return HALMAC_RET_API_INVALID;
+
+	halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_INIT_TRX_CFG);
+
+	pDriver_adapter = pHalmac_adapter->pDriver_adapter;
+	pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api;
+	pHalmac_adapter->trx_mode = halmac_trx_mode;
+
+	PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_init_trx_cfg ==========>halmac_trx_mode = %d\n", halmac_trx_mode);
+
+	status = halmac_txdma_queue_mapping_8821c(pHalmac_adapter, halmac_trx_mode);
+
+	if (HALMAC_RET_SUCCESS != status) {
+		PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_txdma_queue_mapping fail!\n");
+		return status;
+	}
+
+	value8 = 0;
+	HALMAC_REG_WRITE_8(pHalmac_adapter, REG_CR, value8);
+	value8 = HALMAC_CR_TRX_ENABLE_8821C;
+	HALMAC_REG_WRITE_8(pHalmac_adapter, REG_CR, value8);
+	HALMAC_REG_WRITE_32(pHalmac_adapter, REG_H2CQ_CSR, BIT(31));
+
+	status = halmac_priority_queue_config_8821c(pHalmac_adapter, halmac_trx_mode);
+	if (HALMAC_RX_FIFO_EXPANDING_MODE_DISABLE != pHalmac_adapter->txff_allocation.rx_fifo_expanding_mode)
+		HALMAC_REG_WRITE_8(pHalmac_adapter, REG_RX_DRVINFO_SZ, HALMAC_RX_DESC_DUMMY_SIZE_MAX_88XX >> 3);
+
+	if (HALMAC_RET_SUCCESS != status) {
+		PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_txdma_queue_mapping fail!\n");
+		return status;
+	}
+
+	/* Config H2C packet buffer */
+	value32 = HALMAC_REG_READ_32(pHalmac_adapter, REG_H2C_HEAD);
+	/* value32 = (value32 & 0xFFFC0000) | HALMAC_RSVD_H2C_QUEUE_BOUNDARY_8821C; */
+	/* value32 = (value32 & 0xFFFC0000) | pHalmac_adapter->txff_allocation.rsvd_h2c_queue_pg_bndy * HALMAC_TX_PAGE_SIZE_8821C; */
+	value32 = (value32 & 0xFFFC0000) | (pHalmac_adapter->txff_allocation.rsvd_h2c_queue_pg_bndy << HALMAC_TX_PAGE_SIZE_2_POWER_8821C);
+	HALMAC_REG_WRITE_32(pHalmac_adapter, REG_H2C_HEAD, value32);
+
+	value32 = HALMAC_REG_READ_32(pHalmac_adapter, REG_H2C_READ_ADDR);
+	/* value32 = (value32 & 0xFFFC0000) | HALMAC_RSVD_H2C_QUEUE_BOUNDARY_8821C; */
+	value32 = (value32 & 0xFFFC0000) | (pHalmac_adapter->txff_allocation.rsvd_h2c_queue_pg_bndy << HALMAC_TX_PAGE_SIZE_2_POWER_8821C);
+	HALMAC_REG_WRITE_32(pHalmac_adapter, REG_H2C_READ_ADDR, value32);
+
+	value32 = HALMAC_REG_READ_32(pHalmac_adapter, REG_H2C_TAIL);
+	/* value32 = (value32 & 0xFFFC0000) | (HALMAC_RSVD_H2C_QUEUE_BOUNDARY_8821C + HALMAC_RSVD_H2C_QUEUE_SIZE_8821C); */
+	value32 = (value32 & 0xFFFC0000) | ((pHalmac_adapter->txff_allocation.rsvd_h2c_queue_pg_bndy << HALMAC_TX_PAGE_SIZE_2_POWER_8821C) + (HALMAC_RSVD_H2C_QUEUE_PGNUM_8821C << HALMAC_TX_PAGE_SIZE_2_POWER_8821C));
+	HALMAC_REG_WRITE_32(pHalmac_adapter, REG_H2C_TAIL, value32);
+
+	value8 = HALMAC_REG_READ_8(pHalmac_adapter, REG_H2C_INFO);
+	value8 = (u8)((value8 & 0xFC) | 0x01);
+	HALMAC_REG_WRITE_8(pHalmac_adapter, REG_H2C_INFO, value8);
+
+	value8 = HALMAC_REG_READ_8(pHalmac_adapter, REG_H2C_INFO);
+	value8 = (u8)((value8 & 0xFB) | 0x04);
+	HALMAC_REG_WRITE_8(pHalmac_adapter, REG_H2C_INFO, value8);
+
+	value8 = HALMAC_REG_READ_8(pHalmac_adapter, REG_TXDMA_OFFSET_CHK + 1);
+	value8 = (u8)((value8 & 0x7f) | 0x80);
+	HALMAC_REG_WRITE_8(pHalmac_adapter, REG_TXDMA_OFFSET_CHK + 1, value8);
+
+	pHalmac_adapter->h2c_buff_size = HALMAC_RSVD_H2C_QUEUE_PGNUM_8821C << HALMAC_TX_PAGE_SIZE_2_POWER_8821C;
+	halmac_get_h2c_buff_free_space_88xx(pHalmac_adapter);
+
+	if (pHalmac_adapter->h2c_buff_size != pHalmac_adapter->h2c_buf_free_space) {
+		PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "get h2c free space error!\n");
+		return HALMAC_RET_GET_H2C_SPACE_ERR;
+	}
+
+	PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_init_trx_cfg <==========\n");
+
+	return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * halmac_init_protocol_cfg_8821c() - config protocol register
+ * @pHalmac_adapter : the adapter of halmac
+ * Author : KaiYuan Chang/Ivan Lin
+ * Return : HALMAC_RET_STATUS
+ * More details of status code can be found in prototype document
+ */
+HALMAC_RET_STATUS
+halmac_init_protocol_cfg_8821c(
+	IN PHALMAC_ADAPTER pHalmac_adapter
+)
+{
+	u32 max_agg_num, max_rts_agg_num;
+	u32 value32;
+	VOID *pDriver_adapter = NULL;
+	PHALMAC_API pHalmac_api;
+
+	if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter))
+		return HALMAC_RET_ADAPTER_INVALID;
+
+	if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter))
+		return HALMAC_RET_API_INVALID;
+
+	pDriver_adapter = pHalmac_adapter->pDriver_adapter;
+	pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api;
+
+	PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "[TRACE]halmac_init_protocol_cfg_8821c ==========>\n");
+
+	HALMAC_REG_WRITE_8(pHalmac_adapter, REG_AMPDU_MAX_TIME_V1, HALMAC_AMPDU_MAX_TIME_8821C);
+	HALMAC_REG_WRITE_8(pHalmac_adapter, REG_TX_HANG_CTRL, BIT_EN_EOF_V1);
+
+	max_agg_num = HALMAC_PROT_MAX_AGG_PKT_LIMIT_8821C;
+	max_rts_agg_num = HALMAC_PROT_RTS_MAX_AGG_PKT_LIMIT_8821C;
+
+	if (HALMAC_INTERFACE_SDIO == pHalmac_adapter->halmac_interface) {
+		max_agg_num = HALMAC_PROT_MAX_AGG_PKT_LIMIT_8821C_SDIO;
+		max_rts_agg_num = HALMAC_PROT_RTS_MAX_AGG_PKT_LIMIT_8821C_SDIO;
+	}
+
+	value32 = HALMAC_PROT_RTS_LEN_TH_8821C | (HALMAC_PROT_RTS_TX_TIME_TH_8821C << 8) | (max_agg_num << 16) | (max_rts_agg_num << 24);
+	HALMAC_REG_WRITE_32(pHalmac_adapter, REG_PROT_MODE_CTRL, value32);
+
+	HALMAC_REG_WRITE_16(pHalmac_adapter, REG_BAR_MODE_CTRL + 2, HALMAC_BAR_RETRY_LIMIT_8821C | HALMAC_RA_TRY_RATE_AGG_LIMIT_8821C << 8);
+
+	HALMAC_REG_WRITE_8(pHalmac_adapter, REG_FAST_EDCA_VOVI_SETTING, HALMAC_FAST_EDCA_VO_TH_8821C);
+	HALMAC_REG_WRITE_8(pHalmac_adapter, REG_FAST_EDCA_VOVI_SETTING + 2, HALMAC_FAST_EDCA_VI_TH_8821C);
+	HALMAC_REG_WRITE_8(pHalmac_adapter, REG_FAST_EDCA_BEBK_SETTING, HALMAC_FAST_EDCA_BE_TH_8821C);
+	HALMAC_REG_WRITE_8(pHalmac_adapter, REG_FAST_EDCA_BEBK_SETTING + 2, HALMAC_FAST_EDCA_BK_TH_8821C);
+
+	PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "[TRACE]halmac_init_protocol_cfg_8821c <==========\n");
+
+	return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * halmac_init_h2c_8821c() - config h2c packet buffer
+ * @pHalmac_adapter : the adapter of halmac
+ * Author : KaiYuan Chang/Ivan Lin
+ * Return : HALMAC_RET_STATUS
+ * More details of status code can be found in prototype document
+ */
+HALMAC_RET_STATUS
+halmac_init_h2c_8821c(
+	IN PHALMAC_ADAPTER pHalmac_adapter
+)
+{
+	u8 value8;
+	u32 value32;
+	VOID *pDriver_adapter = NULL;
+	PHALMAC_API pHalmac_api;
+
+	if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter))
+		return HALMAC_RET_ADAPTER_INVALID;
+
+	if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter))
+		return HALMAC_RET_API_INVALID;
+
+	pDriver_adapter = pHalmac_adapter->pDriver_adapter;
+	pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api;
+
+	value8 = 0;
+	HALMAC_REG_WRITE_8(pHalmac_adapter, REG_CR, value8);
+	value8 = HALMAC_CR_TRX_ENABLE_8821C;
+	HALMAC_REG_WRITE_8(pHalmac_adapter, REG_CR, value8);
+
+	value32 = HALMAC_REG_READ_32(pHalmac_adapter, REG_H2C_HEAD);
+	/* value32 = (value32 & 0xFFFC0000) | HALMAC_RSVD_H2C_QUEUE_BOUNDARY_8821C; */
+	value32 = (value32 & 0xFFFC0000) | (pHalmac_adapter->txff_allocation.rsvd_h2c_queue_pg_bndy << HALMAC_TX_PAGE_SIZE_2_POWER_8821C);
+	HALMAC_REG_WRITE_32(pHalmac_adapter, REG_H2C_HEAD, value32);
+
+	value32 = HALMAC_REG_READ_32(pHalmac_adapter, REG_H2C_READ_ADDR);
+	/* value32 = (value32 & 0xFFFC0000) | HALMAC_RSVD_H2C_QUEUE_BOUNDARY_8821C; */
+	value32 = (value32 & 0xFFFC0000) | (pHalmac_adapter->txff_allocation.rsvd_h2c_queue_pg_bndy << HALMAC_TX_PAGE_SIZE_2_POWER_8821C);
+	HALMAC_REG_WRITE_32(pHalmac_adapter, REG_H2C_READ_ADDR, value32);
+
+	value32 = HALMAC_REG_READ_32(pHalmac_adapter, REG_H2C_TAIL);
+	/* value32 = (value32 & 0xFFFC0000) | (HALMAC_RSVD_H2C_QUEUE_BOUNDARY_8821C + HALMAC_RSVD_H2C_QUEUE_SIZE_8821C); */
+	value32 = (value32 & 0xFFFC0000) | ((pHalmac_adapter->txff_allocation.rsvd_h2c_queue_pg_bndy << HALMAC_TX_PAGE_SIZE_2_POWER_8821C) + (HALMAC_RSVD_H2C_QUEUE_PGNUM_8821C << HALMAC_TX_PAGE_SIZE_2_POWER_8821C));
+	HALMAC_REG_WRITE_32(pHalmac_adapter, REG_H2C_TAIL, value32);
+	value8 = HALMAC_REG_READ_8(pHalmac_adapter, REG_H2C_INFO);
+	value8 = (u8)((value8 & 0xFC) | 0x01);
+	HALMAC_REG_WRITE_8(pHalmac_adapter, REG_H2C_INFO, value8);
+
+	value8 = HALMAC_REG_READ_8(pHalmac_adapter, REG_H2C_INFO);
+	value8 = (u8)((value8 & 0xFB) | 0x04);
+	HALMAC_REG_WRITE_8(pHalmac_adapter, REG_H2C_INFO, value8);
+
+	value8 = HALMAC_REG_READ_8(pHalmac_adapter, REG_TXDMA_OFFSET_CHK + 1);
+	value8 = (u8)((value8 & 0x7f) | 0x80);
+	HALMAC_REG_WRITE_8(pHalmac_adapter, REG_TXDMA_OFFSET_CHK + 1, value8);
+
+	pHalmac_adapter->h2c_buff_size = (HALMAC_RSVD_H2C_QUEUE_PGNUM_8821C << HALMAC_TX_PAGE_SIZE_2_POWER_8821C);
+	halmac_get_h2c_buff_free_space_88xx(pHalmac_adapter);
+
+	if (pHalmac_adapter->h2c_buff_size != pHalmac_adapter->h2c_buf_free_space) {
+		PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "get h2c free space error!\n");
+		return HALMAC_RET_GET_H2C_SPACE_ERR;
+	}
+
+	PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "h2c free space : %d\n", pHalmac_adapter->h2c_buf_free_space);
+
+	return HALMAC_RET_SUCCESS;
+}
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/halmac/halmac_88xx/halmac_8821c/halmac_api_8821c.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/halmac/halmac_88xx/halmac_8821c/halmac_api_8821c.h
--- linux-5.6.3/3rdparty/rtl8821ce/hal/halmac/halmac_88xx/halmac_8821c/halmac_api_8821c.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/halmac/halmac_88xx/halmac_8821c/halmac_api_8821c.h	2020-04-10 16:35:06.791658901 +0300
@@ -0,0 +1,28 @@
+#ifndef _HALMAC_API_8821C_H_
+#define _HALMAC_API_8821C_H_
+
+#include "../../halmac_2_platform.h"
+#include "../../halmac_type.h"
+
+HALMAC_RET_STATUS
+halmac_mount_api_8821c(
+	IN PHALMAC_ADAPTER pHalmac_adapter
+);
+
+HALMAC_RET_STATUS
+halmac_init_trx_cfg_8821C(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN HALMAC_TRX_MODE halmac_trx_mode
+);
+
+HALMAC_RET_STATUS
+halmac_init_protocol_cfg_8821c(
+	IN PHALMAC_ADAPTER pHalmac_adapter
+);
+
+HALMAC_RET_STATUS
+halmac_init_h2c_8821c(
+	IN PHALMAC_ADAPTER pHalmac_adapter
+);
+
+#endif/* _HALMAC_API_8821C_H_ */
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/halmac/halmac_88xx/halmac_8821c/halmac_api_8821c_pcie.c linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/halmac/halmac_88xx/halmac_8821c/halmac_api_8821c_pcie.c
--- linux-5.6.3/3rdparty/rtl8821ce/hal/halmac/halmac_88xx/halmac_8821c/halmac_api_8821c_pcie.c	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/halmac/halmac_88xx/halmac_8821c/halmac_api_8821c_pcie.c	2020-04-10 16:35:06.791658901 +0300
@@ -0,0 +1,251 @@
+#include "../halmac_88xx_cfg.h"
+#include "halmac_8821c_cfg.h"
+
+#define CLKCAL_CTRL_PHYPARA		0x00
+#define CLKCAL_SET_PHYPARA		0x20
+#define CLKCAL_TRG_VAL_PHYPARA	0x21
+
+static HALMAC_RET_STATUS
+halmac_auto_refclk_cal_8821c_pcie(
+	IN PHALMAC_ADAPTER pHalmac_adapter
+);
+
+/**
+ * halmac_mac_power_switch_8821c_pcie() - switch mac power
+ * @pHalmac_adapter : the adapter of halmac
+ * @halmac_power : power state
+ * Author : KaiYuan Chang / Ivan Lin
+ * Return : HALMAC_RET_STATUS
+ * More details of status code can be found in prototype document
+ */
+HALMAC_RET_STATUS
+halmac_mac_power_switch_8821c_pcie(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN HALMAC_MAC_POWER	halmac_power
+)
+{
+	u8 interface_mask;
+	u8 value8;
+	VOID *pDriver_adapter = NULL;
+	PHALMAC_API pHalmac_api;
+
+	if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter))
+		return HALMAC_RET_ADAPTER_INVALID;
+
+	if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter))
+		return HALMAC_RET_API_INVALID;
+
+	halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_MAC_POWER_SWITCH);
+
+	pDriver_adapter = pHalmac_adapter->pDriver_adapter;
+	pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api;
+
+	PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_PWR, HALMAC_DBG_TRACE, "halmac_mac_power_switch_88xx_pcie halmac_power =  %x ==========>\n", halmac_power);
+	interface_mask = HALMAC_PWR_INTF_PCI_MSK;
+
+	value8 = HALMAC_REG_READ_8(pHalmac_adapter, REG_CR);
+	if (0xEA == value8)
+		pHalmac_adapter->halmac_state.mac_power = HALMAC_MAC_POWER_OFF;
+	else
+		pHalmac_adapter->halmac_state.mac_power = HALMAC_MAC_POWER_ON;
+
+	/* Check if power switch is needed */
+	if (halmac_power == HALMAC_MAC_POWER_ON && pHalmac_adapter->halmac_state.mac_power == HALMAC_MAC_POWER_ON) {
+		PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_PWR, HALMAC_DBG_WARN, "halmac_mac_power_switch power state unchange!\n");
+		return HALMAC_RET_PWR_UNCHANGE;
+	} else {
+		if (HALMAC_MAC_POWER_OFF == halmac_power) {
+			if (HALMAC_RET_SUCCESS != halmac_pwr_seq_parser_88xx(pHalmac_adapter, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_TSMC_MSK,
+				    interface_mask, halmac_8821c_card_disable_flow)) {
+				PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_PWR, HALMAC_DBG_ERR, "Handle power off cmd error\n");
+				return HALMAC_RET_POWER_OFF_FAIL;
+			}
+
+			pHalmac_adapter->halmac_state.mac_power = HALMAC_MAC_POWER_OFF;
+			pHalmac_adapter->halmac_state.ps_state = HALMAC_PS_STATE_UNDEFINE;
+			pHalmac_adapter->halmac_state.dlfw_state = HALMAC_DLFW_NONE;
+			halmac_init_adapter_dynamic_para_88xx(pHalmac_adapter);
+		} else {
+			if (HALMAC_RET_SUCCESS != halmac_pwr_seq_parser_88xx(pHalmac_adapter, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_TSMC_MSK,
+				    interface_mask, halmac_8821c_card_enable_flow)) {
+				PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_PWR, HALMAC_DBG_ERR, "Handle power on cmd error\n");
+				return HALMAC_RET_POWER_ON_FAIL;
+			}
+
+			pHalmac_adapter->halmac_state.mac_power = HALMAC_MAC_POWER_ON;
+			pHalmac_adapter->halmac_state.ps_state = HALMAC_PS_STATE_ACT;
+		}
+	}
+
+	PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_PWR, HALMAC_DBG_TRACE, "halmac_mac_power_switch_88xx_pcie <==========\n");
+
+	return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * halmac_pcie_switch_8821c() - pcie gen1/gen2 switch
+ * @pHalmac_adapter : the adapter of halmac
+ * @pcie_cfg : gen1/gen2 selection
+ * Author : KaiYuan Chang / Ivan Lin
+ * Return : HALMAC_RET_STATUS
+ * More details of status code can be found in prototype document
+ */
+HALMAC_RET_STATUS
+halmac_pcie_switch_8821c(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN HALMAC_PCIE_CFG	pcie_cfg
+)
+{
+	VOID *pDriver_adapter = NULL;
+	PHALMAC_API pHalmac_api;
+
+	if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter))
+		return HALMAC_RET_ADAPTER_INVALID;
+
+	if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter))
+		return HALMAC_RET_API_INVALID;
+
+	halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_PCIE_SWITCH);
+
+	pDriver_adapter = pHalmac_adapter->pDriver_adapter;
+	pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api;
+
+	PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_PWR, HALMAC_DBG_TRACE, "halmac_pcie_switch_8821c ==========>\n");
+
+
+	PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_PWR, HALMAC_DBG_TRACE, "halmac_pcie_switch_8821c <==========\n");
+
+	return HALMAC_RET_SUCCESS;
+}
+
+HALMAC_RET_STATUS
+halmac_pcie_switch_8821c_nc(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN HALMAC_PCIE_CFG	pcie_cfg
+)
+{
+	VOID *pDriver_adapter = NULL;
+	PHALMAC_API pHalmac_api;
+
+	if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter))
+		return HALMAC_RET_ADAPTER_INVALID;
+
+	if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter))
+		return HALMAC_RET_API_INVALID;
+
+	halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_PCIE_SWITCH);
+
+	pDriver_adapter = pHalmac_adapter->pDriver_adapter;
+	pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api;
+
+	PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_PWR, HALMAC_DBG_TRACE, "halmac_pcie_switch_8821c_nc ==========>\n");
+
+	PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_PWR, HALMAC_DBG_TRACE, "halmac_pcie_switch_8821c_nc <==========\n");
+
+	return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * halmac_phy_cfg_8821c_pcie() - phy config
+ * @pHalmac_adapter : the adapter of halmac
+ * Author : KaiYuan Chang / Ivan Lin
+ * Return : HALMAC_RET_STATUS
+ * More details of status code can be found in prototype document
+ */
+HALMAC_RET_STATUS
+halmac_phy_cfg_8821c_pcie(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN HALMAC_INTF_PHY_PLATFORM platform
+)
+{
+	VOID *pDriver_adapter = NULL;
+	HALMAC_RET_STATUS status = HALMAC_RET_SUCCESS;
+	PHALMAC_API pHalmac_api;
+
+	if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter))
+		return HALMAC_RET_ADAPTER_INVALID;
+
+	if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter))
+		return HALMAC_RET_API_INVALID;
+
+	halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_PHY_CFG);
+
+	pDriver_adapter = pHalmac_adapter->pDriver_adapter;
+	pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api;
+
+	PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_PWR, HALMAC_DBG_TRACE, "halmac_phy_cfg ==========>\n");
+
+	status = halmac_parse_intf_phy_88xx(pHalmac_adapter, HALMAC_RTL8821C_PCIE_PHY_GEN1, platform, HAL_INTF_PHY_PCIE_GEN1);
+
+	if (HALMAC_RET_SUCCESS != status)
+		return status;
+
+	status = halmac_parse_intf_phy_88xx(pHalmac_adapter, HALMAC_RTL8821C_PCIE_PHY_GEN2, platform, HAL_INTF_PHY_PCIE_GEN2);
+
+	if (HALMAC_RET_SUCCESS != status)
+		return status;
+
+	PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_PWR, HALMAC_DBG_TRACE, "halmac_phy_cfg <==========\n");
+
+	return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * halmac_interface_integration_tuning_8821c_pcie() - pcie interface fine tuning
+ * @pHalmac_adapter : the adapter of halmac
+ * Author : Rick Liu
+ * Return : HALMAC_RET_STATUS
+ * More details of status code can be found in prototype document
+ */
+HALMAC_RET_STATUS
+halmac_interface_integration_tuning_8821c_pcie(
+	IN PHALMAC_ADAPTER pHalmac_adapter
+)
+{
+	HALMAC_RET_STATUS status;
+
+	status = halmac_auto_refclk_cal_8821c_pcie(pHalmac_adapter);
+
+	return status;
+}
+
+static HALMAC_RET_STATUS
+halmac_auto_refclk_cal_8821c_pcie(
+	IN PHALMAC_ADAPTER pHalmac_adapter
+)
+{
+	u16 read_tmp;
+	u16 cal_target;
+	u16 margin;
+	HALMAC_RET_STATUS status;
+	VOID *pDriver_adapter = NULL;
+
+	pDriver_adapter = pHalmac_adapter->pDriver_adapter;
+
+	/* Set reference clock div number at 0x00[7:6] */
+	read_tmp = halmac_mdio_read_88xx(pHalmac_adapter, CLKCAL_CTRL_PHYPARA, HAL_INTF_PHY_PCIE_GEN1);
+	/* status = halmac_mdio_write_88xx(pHalmac_adapter, CLKCAL_CTRL_PHYPARA, read_tmp & ~(BIT(6) | BIT(7)), HAL_INTF_PHY_PCIE_GEN1); */
+	/* status = halmac_mdio_write_88xx(pHalmac_adapter, CLKCAL_CTRL_PHYPARA, read_tmp & ~(BIT(6)) | BIT(7), HAL_INTF_PHY_PCIE_GEN1); */
+	status = halmac_mdio_write_88xx(pHalmac_adapter, CLKCAL_CTRL_PHYPARA, read_tmp | BIT(7) | BIT(6), HAL_INTF_PHY_PCIE_GEN1);
+	if (HALMAC_RET_SUCCESS != status)
+		return status;
+
+	/* Set 0x00[11] to count 1T of reference clock and read target value at 0x21[11:0] */
+	read_tmp = halmac_mdio_read_88xx(pHalmac_adapter, CLKCAL_CTRL_PHYPARA, HAL_INTF_PHY_PCIE_GEN1);
+	status = halmac_mdio_write_88xx(pHalmac_adapter, CLKCAL_CTRL_PHYPARA, read_tmp | BIT(11), HAL_INTF_PHY_PCIE_GEN1);
+	if (HALMAC_RET_SUCCESS != status)
+		return status;
+	PLATFORM_RTL_DELAY_US(pDriver_adapter, 22);
+	cal_target = halmac_mdio_read_88xx(pHalmac_adapter, CLKCAL_TRG_VAL_PHYPARA, HAL_INTF_PHY_PCIE_GEN1);
+
+	/* Set calibration target at 0x20[11:0] and margin at 0x20[15:12] */
+	margin = 0x0003;
+	status = halmac_mdio_write_88xx(pHalmac_adapter, CLKCAL_SET_PHYPARA, (cal_target & 0x0FFF) | (margin << 12), HAL_INTF_PHY_PCIE_GEN1);
+	if (HALMAC_RET_SUCCESS != status)
+		return status;
+
+	/* Turn on calibration mechanium at 0x00[9] */
+	status = halmac_mdio_write_88xx(pHalmac_adapter, CLKCAL_CTRL_PHYPARA, read_tmp | BIT(9), HAL_INTF_PHY_PCIE_GEN1);
+
+	return HALMAC_RET_SUCCESS;
+}
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/halmac/halmac_88xx/halmac_8821c/halmac_api_8821c_pcie.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/halmac/halmac_88xx/halmac_8821c/halmac_api_8821c_pcie.h
--- linux-5.6.3/3rdparty/rtl8821ce/hal/halmac/halmac_88xx/halmac_8821c/halmac_api_8821c_pcie.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/halmac/halmac_88xx/halmac_8821c/halmac_api_8821c_pcie.h	2020-04-10 16:35:06.791658901 +0300
@@ -0,0 +1,39 @@
+#ifndef _HALMAC_API_8821C_PCIE_H_
+#define _HALMAC_API_8821C_PCIE_H_
+
+#include "../../halmac_2_platform.h"
+#include "../../halmac_type.h"
+
+extern HALMAC_INTF_PHY_PARA HALMAC_RTL8821C_PCIE_PHY_GEN1[];
+extern HALMAC_INTF_PHY_PARA HALMAC_RTL8821C_PCIE_PHY_GEN2[];
+
+HALMAC_RET_STATUS
+halmac_mac_power_switch_8821c_pcie(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN HALMAC_MAC_POWER halmac_power
+);
+
+HALMAC_RET_STATUS
+halmac_pcie_switch_8821c(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN HALMAC_PCIE_CFG	pcie_cfg
+);
+
+HALMAC_RET_STATUS
+halmac_pcie_switch_8821c_nc(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN HALMAC_PCIE_CFG	pcie_cfg
+);
+
+HALMAC_RET_STATUS
+halmac_phy_cfg_8821c_pcie(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN HALMAC_INTF_PHY_PLATFORM platform
+);
+
+HALMAC_RET_STATUS
+halmac_interface_integration_tuning_8821c_pcie(
+	IN PHALMAC_ADAPTER pHalmac_adapter
+);
+
+#endif/* _HALMAC_API_8821C_PCIE_H_ */
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/halmac/halmac_88xx/halmac_8821c/halmac_api_8821c_sdio.c linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/halmac/halmac_88xx/halmac_8821c/halmac_api_8821c_sdio.c
--- linux-5.6.3/3rdparty/rtl8821ce/hal/halmac/halmac_88xx/halmac_8821c/halmac_api_8821c_sdio.c	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/halmac/halmac_88xx/halmac_8821c/halmac_api_8821c_sdio.c	2020-04-10 16:35:06.791658901 +0300
@@ -0,0 +1,144 @@
+/* #include "../halmac_88xx_cfg.h" */
+#include "halmac_8821c_cfg.h"
+
+/**
+ * halmac_mac_power_switch_8821c_sdio() - switch mac power
+ * @pHalmac_adapter : the adapter of halmac
+ * @halmac_power : power state
+ * Author : KaiYuan Chang/Ivan Lin
+ * Return : HALMAC_RET_STATUS
+ * More details of status code can be found in prototype document
+ */
+HALMAC_RET_STATUS
+halmac_mac_power_switch_8821c_sdio(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN HALMAC_MAC_POWER	halmac_power
+)
+{
+	u8 interface_mask;
+	u8 value8;
+	u8 rpwm;
+	u32 imr_backup;
+	VOID *pDriver_adapter = NULL;
+	PHALMAC_API pHalmac_api;
+
+	if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter))
+		return HALMAC_RET_ADAPTER_INVALID;
+
+	if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter))
+		return HALMAC_RET_API_INVALID;
+
+	pDriver_adapter = pHalmac_adapter->pDriver_adapter;
+	pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api;
+
+	PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_PWR, HALMAC_DBG_TRACE, "[TRACE]halmac_mac_power_switch_88xx_sdio halmac_power\n");
+	PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_PWR, HALMAC_DBG_TRACE, "[TRACE]%x\n", halmac_power);
+	PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_PWR, HALMAC_DBG_TRACE, "[TRACE]8821C pwr seq ver = %s\n", HALMAC_8821C_PWR_SEQ_VER);
+
+	interface_mask = HALMAC_PWR_INTF_SDIO_MSK;
+
+	pHalmac_adapter->rpwm_record = HALMAC_REG_READ_8(pHalmac_adapter, REG_SDIO_HRPWM1);
+
+	/* Check FW still exist or not */
+	if (0xC078 == HALMAC_REG_READ_16(pHalmac_adapter, REG_MCUFW_CTRL)) {
+		/* Leave 32K */
+		rpwm = (u8)((pHalmac_adapter->rpwm_record ^ BIT(7)) & 0x80);
+		HALMAC_REG_WRITE_8(pHalmac_adapter, REG_SDIO_HRPWM1, rpwm);
+	}
+
+	value8 = HALMAC_REG_READ_8(pHalmac_adapter, REG_CR);
+	if (0xEA == value8)
+		pHalmac_adapter->halmac_state.mac_power = HALMAC_MAC_POWER_OFF;
+	else
+		pHalmac_adapter->halmac_state.mac_power = HALMAC_MAC_POWER_ON;
+
+	/*Check if power switch is needed*/
+	if (halmac_power == HALMAC_MAC_POWER_ON && pHalmac_adapter->halmac_state.mac_power == HALMAC_MAC_POWER_ON) {
+		PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_PWR, HALMAC_DBG_WARN, "[WARN]halmac_mac_power_switch power state unchange!\n");
+		return HALMAC_RET_PWR_UNCHANGE;
+	} else {
+		imr_backup = HALMAC_REG_READ_32(pHalmac_adapter, REG_SDIO_HIMR);
+		HALMAC_REG_WRITE_32(pHalmac_adapter, REG_SDIO_HIMR, 0);
+
+		if (HALMAC_MAC_POWER_OFF == halmac_power) {
+			if (HALMAC_RET_SUCCESS != halmac_pwr_seq_parser_88xx(pHalmac_adapter, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_TSMC_MSK,
+				    interface_mask, halmac_8821c_card_disable_flow)) {
+				PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_PWR, HALMAC_DBG_ERR, "[ERR]Handle power off cmd error\n");
+				HALMAC_REG_WRITE_32(pHalmac_adapter, REG_SDIO_HIMR, imr_backup);
+				return HALMAC_RET_POWER_OFF_FAIL;
+			}
+
+			pHalmac_adapter->halmac_state.mac_power = HALMAC_MAC_POWER_OFF;
+			pHalmac_adapter->halmac_state.ps_state = HALMAC_PS_STATE_UNDEFINE;
+			pHalmac_adapter->halmac_state.dlfw_state = HALMAC_DLFW_NONE;
+			halmac_init_adapter_dynamic_para_88xx(pHalmac_adapter);
+		} else {
+			if (HALMAC_RET_SUCCESS != halmac_pwr_seq_parser_88xx(pHalmac_adapter, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_TSMC_MSK,
+				    interface_mask, halmac_8821c_card_enable_flow)) {
+				PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_PWR, HALMAC_DBG_ERR, "[ERR]Handle power on cmd error\n");
+				HALMAC_REG_WRITE_32(pHalmac_adapter, REG_SDIO_HIMR, imr_backup);
+				return HALMAC_RET_POWER_ON_FAIL;
+			}
+
+			pHalmac_adapter->halmac_state.mac_power = HALMAC_MAC_POWER_ON;
+			pHalmac_adapter->halmac_state.ps_state = HALMAC_PS_STATE_ACT;
+		}
+
+		HALMAC_REG_WRITE_32(pHalmac_adapter, REG_SDIO_HIMR, imr_backup);
+	}
+
+	PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_PWR, HALMAC_DBG_TRACE, "[TRACE]halmac_mac_power_switch_88xx_sdio <==========\n");
+
+	return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * halmac_phy_cfg_8821c_sdio() - phy config
+ * @pHalmac_adapter : the adapter of halmac
+ * Author : KaiYuan Chang
+ * Return : HALMAC_RET_STATUS
+ * More details of status code can be found in prototype document
+ */
+HALMAC_RET_STATUS
+halmac_phy_cfg_8821c_sdio(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN HALMAC_INTF_PHY_PLATFORM platform
+)
+{
+	VOID *pDriver_adapter = NULL;
+	PHALMAC_API pHalmac_api;
+
+	if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter))
+		return HALMAC_RET_ADAPTER_INVALID;
+
+	if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter))
+		return HALMAC_RET_API_INVALID;
+
+	halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_PHY_CFG);
+
+	pDriver_adapter = pHalmac_adapter->pDriver_adapter;
+	pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api;
+
+	PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_PWR, HALMAC_DBG_TRACE, "halmac_phy_cfg ==========>\n");
+
+	PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_PWR, HALMAC_DBG_TRACE, "sdio no phy\n");
+
+	PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_PWR, HALMAC_DBG_TRACE, "halmac_phy_cfg <==========\n");
+
+	return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * halmac_interface_integration_tuning_8821c_sdio() - sdio interface fine tuning
+ * @pHalmac_adapter : the adapter of halmac
+ * Author : Ivan
+ * Return : HALMAC_RET_STATUS
+ * More details of status code can be found in prototype document
+ */
+HALMAC_RET_STATUS
+halmac_interface_integration_tuning_8821c_sdio(
+	IN PHALMAC_ADAPTER pHalmac_adapter
+)
+{
+	return HALMAC_RET_SUCCESS;
+}
\ Ingen nyrad vid filslut
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/halmac/halmac_88xx/halmac_8821c/halmac_api_8821c_sdio.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/halmac/halmac_88xx/halmac_8821c/halmac_api_8821c_sdio.h
--- linux-5.6.3/3rdparty/rtl8821ce/hal/halmac/halmac_88xx/halmac_8821c/halmac_api_8821c_sdio.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/halmac/halmac_88xx/halmac_8821c/halmac_api_8821c_sdio.h	2020-04-10 16:35:06.791658901 +0300
@@ -0,0 +1,33 @@
+#ifndef _HALMAC_API_8821C_SDIO_H_
+#define _HALMAC_API_8821C_SDIO_H_
+
+#include "../../halmac_2_platform.h"
+#include "../../halmac_type.h"
+
+HALMAC_RET_STATUS
+halmac_mac_power_switch_8821c_sdio(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN HALMAC_MAC_POWER halmac_power
+);
+
+#if 0
+HALMAC_RET_STATUS
+halmac_tx_allowed_sdio_8821c(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN u8 *pHalmac_buf,
+	IN u32 halmac_size
+);
+#endif
+
+HALMAC_RET_STATUS
+halmac_phy_cfg_8821c_sdio(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN HALMAC_INTF_PHY_PLATFORM platform
+);
+
+HALMAC_RET_STATUS
+halmac_interface_integration_tuning_8821c_sdio(
+	IN PHALMAC_ADAPTER pHalmac_adapter
+);
+
+#endif/* _HALMAC_API_8821C_SDIO_H_ */
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/halmac/halmac_88xx/halmac_8821c/halmac_api_8821c_usb.c linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/halmac/halmac_88xx/halmac_8821c/halmac_api_8821c_usb.c
--- linux-5.6.3/3rdparty/rtl8821ce/hal/halmac/halmac_88xx/halmac_8821c/halmac_api_8821c_usb.c	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/halmac/halmac_88xx/halmac_8821c/halmac_api_8821c_usb.c	2020-04-10 16:35:06.791658901 +0300
@@ -0,0 +1,142 @@
+#include "../halmac_88xx_cfg.h"
+#include "halmac_8821c_cfg.h"
+
+/**
+ * halmac_mac_power_switch_8821c_usb() - switch mac power
+ * @pHalmac_adapter : the adapter of halmac
+ * @halmac_power : power state
+ * Author : KaiYuan Chang
+ * Return : HALMAC_RET_STATUS
+ * More details of status code can be found in prototype document
+ */
+HALMAC_RET_STATUS
+halmac_mac_power_switch_8821c_usb(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN HALMAC_MAC_POWER	halmac_power
+)
+{
+	u8 interface_mask;
+	u8 value8;
+	VOID *pDriver_adapter = NULL;
+	PHALMAC_API pHalmac_api;
+
+	if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter))
+		return HALMAC_RET_ADAPTER_INVALID;
+
+	if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter))
+		return HALMAC_RET_API_INVALID;
+
+	halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_MAC_POWER_SWITCH);
+
+	pDriver_adapter = pHalmac_adapter->pDriver_adapter;
+	pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api;
+
+	PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_PWR, HALMAC_DBG_TRACE, "halmac_mac_power_switch_88xx_usb halmac_power = %x ==========>\n", halmac_power);
+
+	interface_mask = HALMAC_PWR_INTF_USB_MSK;
+
+	value8 = HALMAC_REG_READ_8(pHalmac_adapter, REG_CR);
+	if (0xEA == value8) {
+		pHalmac_adapter->halmac_state.mac_power = HALMAC_MAC_POWER_OFF;
+	} else {
+		if (BIT(0) == (HALMAC_REG_READ_8(pHalmac_adapter, REG_SYS_STATUS1 + 1) & BIT(0)))
+			pHalmac_adapter->halmac_state.mac_power = HALMAC_MAC_POWER_OFF;
+		else
+			pHalmac_adapter->halmac_state.mac_power = HALMAC_MAC_POWER_ON;
+	}
+
+	/*Check if power switch is needed*/
+	if (halmac_power == HALMAC_MAC_POWER_ON && pHalmac_adapter->halmac_state.mac_power == HALMAC_MAC_POWER_ON) {
+		PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_PWR, HALMAC_DBG_WARN, "halmac_mac_power_switch power state unchange!\n");
+		return HALMAC_RET_PWR_UNCHANGE;
+	} else {
+		if (HALMAC_MAC_POWER_OFF == halmac_power) {
+			if (HALMAC_RET_SUCCESS != halmac_pwr_seq_parser_88xx(pHalmac_adapter, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_TSMC_MSK,
+				    interface_mask, halmac_8821c_card_disable_flow)) {
+				PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_PWR, HALMAC_DBG_ERR, "Handle power off cmd error\n");
+				return HALMAC_RET_POWER_OFF_FAIL;
+			}
+
+			pHalmac_adapter->halmac_state.mac_power = HALMAC_MAC_POWER_OFF;
+			pHalmac_adapter->halmac_state.ps_state = HALMAC_PS_STATE_UNDEFINE;
+			pHalmac_adapter->halmac_state.dlfw_state = HALMAC_DLFW_NONE;
+			halmac_init_adapter_dynamic_para_88xx(pHalmac_adapter);
+		} else {
+			if (HALMAC_RET_SUCCESS != halmac_pwr_seq_parser_88xx(pHalmac_adapter, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_TSMC_MSK,
+				    interface_mask, halmac_8821c_card_enable_flow)) {
+				PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_PWR, HALMAC_DBG_ERR, "Handle power on cmd error\n");
+				return HALMAC_RET_POWER_ON_FAIL;
+			}
+
+			HALMAC_REG_WRITE_8(pHalmac_adapter, REG_SYS_STATUS1 + 1, HALMAC_REG_READ_8(pHalmac_adapter, REG_SYS_STATUS1 + 1) & ~(BIT(0)));
+
+			pHalmac_adapter->halmac_state.mac_power = HALMAC_MAC_POWER_ON;
+			pHalmac_adapter->halmac_state.ps_state = HALMAC_PS_STATE_ACT;
+		}
+	}
+
+	PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_PWR, HALMAC_DBG_TRACE, "halmac_mac_power_switch_88xx_usb <==========\n");
+
+	return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * halmac_phy_cfg_8821c_usb() - phy config
+ * @pHalmac_adapter : the adapter of halmac
+ * Author : KaiYuan Chang
+ * Return : HALMAC_RET_STATUS
+ * More details of status code can be found in prototype document
+ */
+HALMAC_RET_STATUS
+halmac_phy_cfg_8821c_usb(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN HALMAC_INTF_PHY_PLATFORM platform
+)
+{
+	VOID *pDriver_adapter = NULL;
+	HALMAC_RET_STATUS status = HALMAC_RET_SUCCESS;
+	PHALMAC_API pHalmac_api;
+
+	if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter))
+		return HALMAC_RET_ADAPTER_INVALID;
+
+	if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter))
+		return HALMAC_RET_API_INVALID;
+
+	halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_PHY_CFG);
+
+	pDriver_adapter = pHalmac_adapter->pDriver_adapter;
+	pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api;
+
+	PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_PWR, HALMAC_DBG_TRACE, "halmac_phy_cfg ==========>\n");
+
+	status = halmac_parse_intf_phy_88xx(pHalmac_adapter, HALMAC_RTL8821C_USB2_PHY, platform, HAL_INTF_PHY_USB2);
+
+	if (HALMAC_RET_SUCCESS != status)
+		return status;
+
+	status = halmac_parse_intf_phy_88xx(pHalmac_adapter, HALMAC_RTL8821C_USB3_PHY, platform, HAL_INTF_PHY_USB3);
+
+	if (HALMAC_RET_SUCCESS != status)
+		return status;
+
+	PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_PWR, HALMAC_DBG_TRACE, "halmac_phy_cfg <==========\n");
+
+	return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * halmac_interface_integration_tuning_8821c_usb() - usb interface fine tuning
+ * @pHalmac_adapter : the adapter of halmac
+ * Author : Ivan
+ * Return : HALMAC_RET_STATUS
+ * More details of status code can be found in prototype document
+ */
+HALMAC_RET_STATUS
+halmac_interface_integration_tuning_8821c_usb(
+	IN PHALMAC_ADAPTER pHalmac_adapter
+)
+{
+	return HALMAC_RET_SUCCESS;
+}
+
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/halmac/halmac_88xx/halmac_8821c/halmac_api_8821c_usb.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/halmac/halmac_88xx/halmac_8821c/halmac_api_8821c_usb.h
--- linux-5.6.3/3rdparty/rtl8821ce/hal/halmac/halmac_88xx/halmac_8821c/halmac_api_8821c_usb.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/halmac/halmac_88xx/halmac_8821c/halmac_api_8821c_usb.h	2020-04-10 16:35:06.791658901 +0300
@@ -0,0 +1,27 @@
+#ifndef _HALMAC_API_8821C_USB_H_
+#define _HALMAC_API_8821C_USB_H_
+
+#include "../../halmac_2_platform.h"
+#include "../../halmac_type.h"
+
+extern HALMAC_INTF_PHY_PARA HALMAC_RTL8821C_USB2_PHY[];
+extern HALMAC_INTF_PHY_PARA HALMAC_RTL8821C_USB3_PHY[];
+
+HALMAC_RET_STATUS
+halmac_mac_power_switch_8821c_usb(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN HALMAC_MAC_POWER halmac_power
+);
+
+HALMAC_RET_STATUS
+halmac_phy_cfg_8821c_usb(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN HALMAC_INTF_PHY_PLATFORM platform
+);
+
+HALMAC_RET_STATUS
+halmac_interface_integration_tuning_8821c_usb(
+	IN PHALMAC_ADAPTER pHalmac_adapter
+);
+
+#endif/* _HALMAC_API_8821C_USB_H_ */
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/halmac/halmac_88xx/halmac_8821c/halmac_cfg_wmac_8821c.c linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/halmac/halmac_88xx/halmac_8821c/halmac_cfg_wmac_8821c.c
--- linux-5.6.3/3rdparty/rtl8821ce/hal/halmac/halmac_88xx/halmac_8821c/halmac_cfg_wmac_8821c.c	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/halmac/halmac_88xx/halmac_8821c/halmac_cfg_wmac_8821c.c	2020-04-10 16:35:06.791658901 +0300
@@ -0,0 +1,145 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2017 - 2018 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ ******************************************************************************/
+
+#include "halmac_cfg_wmac_8821c.h"
+#include "halmac_8821c_cfg.h"
+
+#if HALMAC_8821C_SUPPORT
+
+/**
+ * cfg_drv_info_8821c() - config driver info
+ * @adapter : the adapter of halmac
+ * @drv_info : driver information selection
+ * Author : KaiYuan Chang/Ivan Lin
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+cfg_drv_info_8821c(struct halmac_adapter *adapter,
+		   enum halmac_drv_info drv_info)
+{
+	u8 drv_info_size = 0;
+	u8 phy_status_en = 0;
+	u8 sniffer_en = 0;
+	u8 plcp_hdr_en = 0;
+	u8 value8;
+	u32 value32;
+	struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
+
+	PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
+	PLTFM_MSG_TRACE("[TRACE]drv info = %d\n", drv_info);
+
+	switch (drv_info) {
+	case HALMAC_DRV_INFO_NONE:
+		drv_info_size = 0;
+		phy_status_en = 0;
+		sniffer_en = 0;
+		plcp_hdr_en = 0;
+		break;
+	case HALMAC_DRV_INFO_PHY_STATUS:
+		drv_info_size = 4;
+		phy_status_en = 1;
+		sniffer_en = 0;
+		plcp_hdr_en = 0;
+		break;
+	case HALMAC_DRV_INFO_PHY_SNIFFER:
+		drv_info_size = 5; /* phy status 4byte, sniffer info 1byte */
+		phy_status_en = 1;
+		sniffer_en = 1;
+		plcp_hdr_en = 0;
+		break;
+	case HALMAC_DRV_INFO_PHY_PLCP:
+		drv_info_size = 6; /* phy status 4byte, plcp header 2byte */
+		phy_status_en = 1;
+		sniffer_en = 0;
+		plcp_hdr_en = 1;
+		break;
+	default:
+		return HALMAC_RET_SW_CASE_NOT_SUPPORT;
+	}
+
+	if (adapter->txff_alloc.rx_fifo_exp_mode !=
+	    HALMAC_RX_FIFO_EXPANDING_MODE_DISABLE)
+		drv_info_size = RX_DESC_DUMMY_SIZE_8821C >> 3;
+
+	HALMAC_REG_W8(REG_RX_DRVINFO_SZ, drv_info_size);
+
+	value8 = HALMAC_REG_R8(REG_TRXFF_BNDY + 1);
+	value8 &= 0xF0;
+	/* For rxdesc len = 0 issue */
+	value8 |= 0xF;
+	HALMAC_REG_W8(REG_TRXFF_BNDY + 1, value8);
+
+	adapter->drv_info_size = drv_info_size;
+
+	value32 = HALMAC_REG_R32(REG_RCR);
+	value32 = (value32 & (~BIT_APP_PHYSTS));
+	if (phy_status_en == 1)
+		value32 = value32 | BIT_APP_PHYSTS;
+	HALMAC_REG_W32(REG_RCR, value32);
+
+	value32 = HALMAC_REG_R32(REG_WMAC_OPTION_FUNCTION + 4);
+	value32 = (value32 & (~(BIT(8) | BIT(9))));
+	if (sniffer_en == 1)
+		value32 = value32 | BIT(9);
+	if (plcp_hdr_en == 1)
+		value32 = value32 | BIT(8);
+	HALMAC_REG_W32(REG_WMAC_OPTION_FUNCTION + 4, value32);
+
+	PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
+
+	return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * init_low_pwr_8821c() - config WMAC register
+ * @adapter
+ * Author : KaiYuan Chang/Ivan Lin
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+init_low_pwr_8821c(struct halmac_adapter *adapter)
+{
+	return HALMAC_RET_SUCCESS;
+}
+
+void
+cfg_rx_ignore_8821c(struct halmac_adapter *adapter,
+		    struct halmac_mac_rx_ignore_cfg *cfg)
+{
+}
+
+enum halmac_ret_status
+cfg_ampdu_8821c(struct halmac_adapter *adapter,
+		struct halmac_ampdu_config *cfg)
+{
+	struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
+
+	if (cfg->ht_max_len != cfg->vht_max_len) {
+		PLTFM_MSG_ERR("[ERR]max len ht != vht!!\n");
+		return HALMAC_RET_PARA_NOT_SUPPORT;
+	}
+
+	HALMAC_REG_W8(REG_PROT_MODE_CTRL + 2, cfg->max_agg_num);
+	HALMAC_REG_W8(REG_PROT_MODE_CTRL + 3, cfg->max_agg_num);
+
+	if (cfg->max_len_en == 1)
+		HALMAC_REG_W32(REG_AMPDU_MAX_LENGTH, cfg->ht_max_len);
+
+	return HALMAC_RET_SUCCESS;
+}
+
+#endif /* HALMAC_8821C_SUPPORT */
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/halmac/halmac_88xx/halmac_8821c/halmac_cfg_wmac_8821c.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/halmac/halmac_88xx/halmac_8821c/halmac_cfg_wmac_8821c.h
--- linux-5.6.3/3rdparty/rtl8821ce/hal/halmac/halmac_88xx/halmac_8821c/halmac_cfg_wmac_8821c.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/halmac/halmac_88xx/halmac_8821c/halmac_cfg_wmac_8821c.h	2020-04-10 16:35:06.791658901 +0300
@@ -0,0 +1,40 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2017 - 2018 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ ******************************************************************************/
+
+#ifndef _HALMAC_CFG_WMAC_8821C_H_
+#define _HALMAC_CFG_WMAC_8821C_H_
+
+#include "../../halmac_api.h"
+
+#if HALMAC_8821C_SUPPORT
+
+enum halmac_ret_status
+cfg_drv_info_8821c(struct halmac_adapter *adapter,
+		   enum halmac_drv_info drv_info);
+
+enum halmac_ret_status
+init_low_pwr_8821c(struct halmac_adapter *adapter);
+
+void
+cfg_rx_ignore_8821c(struct halmac_adapter *adapter,
+		    struct halmac_mac_rx_ignore_cfg *cfg);
+
+enum halmac_ret_status
+cfg_ampdu_8821c(struct halmac_adapter *adapter,
+		struct halmac_ampdu_config *cfg);
+
+#endif/* HALMAC_8821C_SUPPORT */
+
+#endif/* _HALMAC_CFG_WMAC_8821C_H_ */
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/halmac/halmac_88xx/halmac_8821c/halmac_common_8821c.c linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/halmac/halmac_88xx/halmac_8821c/halmac_common_8821c.c
--- linux-5.6.3/3rdparty/rtl8821ce/hal/halmac/halmac_88xx/halmac_8821c/halmac_common_8821c.c	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/halmac/halmac_88xx/halmac_8821c/halmac_common_8821c.c	2020-04-10 16:35:06.791658901 +0300
@@ -0,0 +1,182 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2017 - 2018 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ ******************************************************************************/
+
+#include "halmac_8821c_cfg.h"
+#include "halmac_common_8821c.h"
+#include "../halmac_common_88xx.h"
+#include "halmac_cfg_wmac_8821c.h"
+#if HALMAC_PCIE_SUPPORT
+#include "halmac_pcie_8821c.h"
+#endif
+
+#if HALMAC_8821C_SUPPORT
+
+static void
+cfg_ldo25_8821c(struct halmac_adapter *adapter, u8 enable);
+
+/**
+ * get_hw_value_8821c() -get hw config value
+ * @adapter : the adapter of halmac
+ * @hw_id : hw id for driver to query
+ * @value : hw value, reference table to get data type
+ * Author : KaiYuan Chang / Ivan Lin
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+get_hw_value_8821c(struct halmac_adapter *adapter, enum halmac_hw_id hw_id,
+		   void *value)
+{
+	PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
+
+	if (!value) {
+		PLTFM_MSG_ERR("[ERR]null pointer\n");
+		return HALMAC_RET_NULL_POINTER;
+	}
+
+	if (get_hw_value_88xx(adapter, hw_id, value) == HALMAC_RET_SUCCESS)
+		return HALMAC_RET_SUCCESS;
+
+	switch (hw_id) {
+	case HALMAC_HW_FW_MAX_SIZE:
+		*(u32 *)value = WLAN_FW_MAX_SIZE_8821C;
+		break;
+	case HALMAC_HW_SDIO_INT_LAT:
+		break;
+	case HALMAC_HW_SDIO_CLK_CNT:
+		break;
+	default:
+		return HALMAC_RET_PARA_NOT_SUPPORT;
+	}
+
+	PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
+
+	return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * set_hw_value_8821c() -set hw config value
+ * @adapter : the adapter of halmac
+ * @hw_id : hw id for driver to config
+ * @value : hw value, reference table to get data type
+ * Author : KaiYuan Chang / Ivan Lin
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+set_hw_value_8821c(struct halmac_adapter *adapter, enum halmac_hw_id hw_id,
+		   void *value)
+{
+	enum halmac_ret_status status = HALMAC_RET_SUCCESS;
+
+	PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
+
+	if (!value) {
+		PLTFM_MSG_ERR("[ERR]null pointer\n");
+		return HALMAC_RET_NULL_POINTER;
+	}
+
+	if (set_hw_value_88xx(adapter, hw_id, value) == HALMAC_RET_SUCCESS)
+		return HALMAC_RET_SUCCESS;
+
+	switch (hw_id) {
+	case HALMAC_HW_AMPDU_CONFIG:
+		status = cfg_ampdu_8821c(adapter,
+					 (struct halmac_ampdu_config *)value);
+		break;
+	case HALMAC_HW_SDIO_TX_FORMAT:
+		break;
+	case HALMAC_HW_RXGCK_FIFO:
+		break;
+	case HALMAC_HW_RX_IGNORE:
+		break;
+	case HALMAC_HW_LDO25_EN:
+		cfg_ldo25_8821c(adapter, *(u8 *)value);
+		break;
+#if HALMAC_PCIE_SUPPORT
+	case HALMAC_HW_PCIE_REF_AUTOK:
+		if (adapter->intf != HALMAC_INTERFACE_PCIE)
+			return HALMAC_RET_WRONG_INTF;
+		status = auto_refclk_cal_8821c_pcie(adapter);
+		if (status != HALMAC_RET_SUCCESS)
+			return status;
+		break;
+#endif
+	case HALMAC_HW_SDIO_WT_EN:
+		break;
+	case HALMAC_HW_SDIO_CLK_MONITOR:
+		break;
+	default:
+		return HALMAC_RET_PARA_NOT_SUPPORT;
+	}
+
+	PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
+
+	return status;
+}
+
+/**
+ * halmac_fill_txdesc_check_sum_88xx() -  fill in tx desc check sum
+ * @adapter : the adapter of halmac
+ * @txdesc : tx desc packet
+ * Author : KaiYuan Chang/Ivan Lin
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+fill_txdesc_check_sum_8821c(struct halmac_adapter *adapter, u8 *txdesc)
+{
+	__le16 chksum = 0;
+	__le16 *data;
+	u32 i;
+
+	if (!txdesc) {
+		PLTFM_MSG_ERR("[ERR]null pointer\n");
+		return HALMAC_RET_NULL_POINTER;
+	}
+
+	if (adapter->tx_desc_checksum != 1)
+		PLTFM_MSG_TRACE("[TRACE]chksum disable\n");
+
+	SET_TX_DESC_TXDESC_CHECKSUM(txdesc, 0x0000);
+
+	data = (__le16 *)(txdesc);
+
+	/* HW clculates only 32byte */
+	for (i = 0; i < 8; i++)
+		chksum ^= (*(data + 2 * i) ^ *(data + (2 * i + 1)));
+
+	/* *(data + 2 * i) & *(data + (2 * i + 1) have endain issue*/
+	/* Process eniadn issue after checksum calculation */
+	SET_TX_DESC_TXDESC_CHECKSUM(txdesc, rtk_le16_to_cpu(chksum));
+
+	return HALMAC_RET_SUCCESS;
+}
+
+static void
+cfg_ldo25_8821c(struct halmac_adapter *adapter, u8 enable)
+{
+	u8 value8;
+	struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
+
+	value8 = HALMAC_REG_R8(REG_LDO_EFUSE_CTRL + 3);
+
+	if (enable == 1)
+		HALMAC_REG_W8(REG_LDO_EFUSE_CTRL + 3, (u8)(value8 | BIT(7)));
+	else
+		HALMAC_REG_W8(REG_LDO_EFUSE_CTRL + 3, (u8)(value8 & ~BIT(7)));
+}
+
+#endif /* HALMAC_8821C_SUPPORT */
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/halmac/halmac_88xx/halmac_8821c/halmac_common_8821c.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/halmac/halmac_88xx/halmac_8821c/halmac_common_8821c.h
--- linux-5.6.3/3rdparty/rtl8821ce/hal/halmac/halmac_88xx/halmac_8821c/halmac_common_8821c.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/halmac/halmac_88xx/halmac_8821c/halmac_common_8821c.h	2020-04-10 16:35:06.791658901 +0300
@@ -0,0 +1,36 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2017 - 2018 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ ******************************************************************************/
+
+#ifndef _HALMAC_COMMON_8821C_H_
+#define _HALMAC_COMMON_8821C_H_
+
+#include "../../halmac_api.h"
+
+#if HALMAC_8821C_SUPPORT
+
+enum halmac_ret_status
+get_hw_value_8821c(struct halmac_adapter *adapter, enum halmac_hw_id hw_id,
+		   void *value);
+
+enum halmac_ret_status
+set_hw_value_8821c(struct halmac_adapter *adapter, enum halmac_hw_id hw_id,
+		   void *value);
+
+enum halmac_ret_status
+fill_txdesc_check_sum_8821c(struct halmac_adapter *adapter, u8 *txdesc);
+
+#endif/* HALMAC_8821C_SUPPORT */
+
+#endif/* _HALMAC_COMMON_8821C_H_ */
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/halmac/halmac_88xx/halmac_8821c/halmac_func_8821c.c linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/halmac/halmac_88xx/halmac_8821c/halmac_func_8821c.c
--- linux-5.6.3/3rdparty/rtl8821ce/hal/halmac/halmac_88xx/halmac_8821c/halmac_func_8821c.c	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/halmac/halmac_88xx/halmac_8821c/halmac_func_8821c.c	2020-04-10 16:35:06.791658901 +0300
@@ -0,0 +1,311 @@
+#include "halmac_8821c_cfg.h"
+
+
+#if HALMAC_PLATFORM_WINDOWS
+/*SDIO RQPN Mapping for Windows, extra queue is not implemented in Driver code*/
+HALMAC_RQPN HALMAC_RQPN_SDIO_8821C[] = {
+	/* { mode, vo_map, vi_map, be_map, bk_map, mg_map, hi_map } */
+	{HALMAC_TRX_MODE_NORMAL, HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ, HALMAC_MAP2_LQ, HALMAC_MAP2_HQ, HALMAC_MAP2_HQ},
+	{HALMAC_TRX_MODE_TRXSHARE, HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ, HALMAC_MAP2_LQ, HALMAC_MAP2_HQ, HALMAC_MAP2_HQ},
+	{HALMAC_TRX_MODE_WMM, HALMAC_MAP2_HQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ, HALMAC_MAP2_NQ, HALMAC_MAP2_EXQ, HALMAC_MAP2_HQ},
+	{HALMAC_TRX_MODE_P2P, HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ, HALMAC_MAP2_LQ, HALMAC_MAP2_HQ, HALMAC_MAP2_HQ},
+	{HALMAC_TRX_MODE_LOOPBACK, HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ, HALMAC_MAP2_LQ, HALMAC_MAP2_HQ, HALMAC_MAP2_HQ},
+	{HALMAC_TRX_MODE_DELAY_LOOPBACK, HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ, HALMAC_MAP2_LQ, HALMAC_MAP2_HQ, HALMAC_MAP2_HQ},
+};
+#else
+/*SDIO RQPN Mapping*/
+HALMAC_RQPN HALMAC_RQPN_SDIO_8821C[] = {
+	/* { mode, vo_map, vi_map, be_map, bk_map, mg_map, hi_map } */
+	{HALMAC_TRX_MODE_NORMAL, HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ, HALMAC_MAP2_LQ, HALMAC_MAP2_EXQ, HALMAC_MAP2_HQ},
+	{HALMAC_TRX_MODE_TRXSHARE, HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ, HALMAC_MAP2_LQ, HALMAC_MAP2_EXQ, HALMAC_MAP2_HQ},
+	{HALMAC_TRX_MODE_WMM, HALMAC_MAP2_HQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ, HALMAC_MAP2_NQ, HALMAC_MAP2_EXQ, HALMAC_MAP2_HQ},
+	{HALMAC_TRX_MODE_P2P, HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ, HALMAC_MAP2_LQ, HALMAC_MAP2_EXQ, HALMAC_MAP2_HQ},
+	{HALMAC_TRX_MODE_LOOPBACK, HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ, HALMAC_MAP2_LQ, HALMAC_MAP2_EXQ, HALMAC_MAP2_HQ},
+	{HALMAC_TRX_MODE_DELAY_LOOPBACK, HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ, HALMAC_MAP2_LQ, HALMAC_MAP2_EXQ, HALMAC_MAP2_HQ},
+};
+#endif
+
+/*PCIE RQPN Mapping*/
+HALMAC_RQPN HALMAC_RQPN_PCIE_8821C[] = {
+	/* { mode, vo_map, vi_map, be_map, bk_map, mg_map, hi_map } */
+	{HALMAC_TRX_MODE_NORMAL, HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ, HALMAC_MAP2_LQ, HALMAC_MAP2_EXQ, HALMAC_MAP2_HQ},
+	{HALMAC_TRX_MODE_TRXSHARE, HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ, HALMAC_MAP2_LQ, HALMAC_MAP2_EXQ, HALMAC_MAP2_HQ},
+	{HALMAC_TRX_MODE_WMM, HALMAC_MAP2_HQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ, HALMAC_MAP2_NQ, HALMAC_MAP2_EXQ, HALMAC_MAP2_HQ},
+	{HALMAC_TRX_MODE_P2P, HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ, HALMAC_MAP2_LQ, HALMAC_MAP2_EXQ, HALMAC_MAP2_HQ},
+	{HALMAC_TRX_MODE_LOOPBACK, HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ, HALMAC_MAP2_LQ, HALMAC_MAP2_EXQ, HALMAC_MAP2_HQ},
+	{HALMAC_TRX_MODE_DELAY_LOOPBACK, HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ, HALMAC_MAP2_LQ, HALMAC_MAP2_EXQ, HALMAC_MAP2_HQ},
+};
+
+/*USB 2 Bulkout RQPN Mapping*/
+HALMAC_RQPN HALMAC_RQPN_2BULKOUT_8821C[] = {
+	/* { mode, vo_map, vi_map, be_map, bk_map, mg_map, hi_map } */
+	{HALMAC_TRX_MODE_NORMAL, HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_HQ, HALMAC_MAP2_HQ, HALMAC_MAP2_HQ},
+	{HALMAC_TRX_MODE_TRXSHARE, HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_HQ, HALMAC_MAP2_HQ, HALMAC_MAP2_HQ},
+	{HALMAC_TRX_MODE_WMM, HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_HQ, HALMAC_MAP2_HQ, HALMAC_MAP2_HQ},
+	{HALMAC_TRX_MODE_P2P, HALMAC_MAP2_HQ, HALMAC_MAP2_HQ, HALMAC_MAP2_HQ, HALMAC_MAP2_NQ, HALMAC_MAP2_HQ, HALMAC_MAP2_HQ},
+	{HALMAC_TRX_MODE_LOOPBACK, HALMAC_MAP2_HQ, HALMAC_MAP2_HQ, HALMAC_MAP2_HQ, HALMAC_MAP2_NQ, HALMAC_MAP2_HQ, HALMAC_MAP2_HQ},
+	{HALMAC_TRX_MODE_DELAY_LOOPBACK, HALMAC_MAP2_HQ, HALMAC_MAP2_HQ, HALMAC_MAP2_HQ, HALMAC_MAP2_NQ, HALMAC_MAP2_HQ, HALMAC_MAP2_HQ},
+};
+
+/*USB 3 Bulkout RQPN Mapping*/
+HALMAC_RQPN HALMAC_RQPN_3BULKOUT_8821C[] = {
+	/* { mode, vo_map, vi_map, be_map, bk_map, mg_map, hi_map } */
+	{HALMAC_TRX_MODE_NORMAL, HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ, HALMAC_MAP2_LQ, HALMAC_MAP2_HQ, HALMAC_MAP2_HQ},
+	{HALMAC_TRX_MODE_TRXSHARE, HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ, HALMAC_MAP2_LQ, HALMAC_MAP2_HQ, HALMAC_MAP2_HQ},
+	{HALMAC_TRX_MODE_WMM, HALMAC_MAP2_HQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ, HALMAC_MAP2_NQ, HALMAC_MAP2_HQ, HALMAC_MAP2_HQ},
+	{HALMAC_TRX_MODE_P2P, HALMAC_MAP2_HQ, HALMAC_MAP2_HQ, HALMAC_MAP2_LQ, HALMAC_MAP2_NQ, HALMAC_MAP2_HQ, HALMAC_MAP2_HQ},
+	{HALMAC_TRX_MODE_LOOPBACK, HALMAC_MAP2_HQ, HALMAC_MAP2_HQ, HALMAC_MAP2_LQ, HALMAC_MAP2_NQ, HALMAC_MAP2_HQ, HALMAC_MAP2_HQ},
+	{HALMAC_TRX_MODE_DELAY_LOOPBACK, HALMAC_MAP2_HQ, HALMAC_MAP2_HQ, HALMAC_MAP2_LQ, HALMAC_MAP2_NQ, HALMAC_MAP2_HQ, HALMAC_MAP2_HQ},
+};
+
+/*USB 4 Bulkout RQPN Mapping*/
+HALMAC_RQPN HALMAC_RQPN_4BULKOUT_8821C[] = {
+	/* { mode, vo_map, vi_map, be_map, bk_map, mg_map, hi_map } */
+	{HALMAC_TRX_MODE_NORMAL, HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ, HALMAC_MAP2_LQ, HALMAC_MAP2_EXQ, HALMAC_MAP2_HQ},
+	{HALMAC_TRX_MODE_TRXSHARE, HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ, HALMAC_MAP2_LQ, HALMAC_MAP2_EXQ, HALMAC_MAP2_HQ},
+	{HALMAC_TRX_MODE_WMM, HALMAC_MAP2_HQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ, HALMAC_MAP2_NQ, HALMAC_MAP2_EXQ, HALMAC_MAP2_HQ},
+	{HALMAC_TRX_MODE_P2P, HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ, HALMAC_MAP2_LQ, HALMAC_MAP2_EXQ, HALMAC_MAP2_HQ},
+	{HALMAC_TRX_MODE_LOOPBACK, HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ, HALMAC_MAP2_LQ, HALMAC_MAP2_EXQ, HALMAC_MAP2_HQ},
+	{HALMAC_TRX_MODE_DELAY_LOOPBACK, HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ, HALMAC_MAP2_LQ, HALMAC_MAP2_EXQ, HALMAC_MAP2_HQ},
+};
+#if HALMAC_PLATFORM_WINDOWS
+/*SDIO Page Number*/
+HALMAC_PG_NUM HALMAC_PG_NUM_SDIO_8821C[] = {
+	/* { mode, hq_num, nq_num, lq_num, exq_num, gap_num} */
+	{HALMAC_TRX_MODE_NORMAL, 16, 16, 16, 0, 1},
+	{HALMAC_TRX_MODE_TRXSHARE, 8, 8, 8, 0, 1},
+	{HALMAC_TRX_MODE_WMM, 16, 16, 16, 0, 1},
+	{HALMAC_TRX_MODE_P2P, 16, 16, 16, 0, 1},
+	{HALMAC_TRX_MODE_LOOPBACK, 16, 16, 16, 0, 256},
+	{HALMAC_TRX_MODE_DELAY_LOOPBACK, 16, 16, 16, 0, 256},
+};
+#else
+/*SDIO Page Number*/
+HALMAC_PG_NUM HALMAC_PG_NUM_SDIO_8821C[] = {
+	/* { mode, hq_num, nq_num, lq_num, exq_num, gap_num} */
+	{HALMAC_TRX_MODE_NORMAL, 16, 16, 16, 14, 1},
+	{HALMAC_TRX_MODE_TRXSHARE, 8, 8, 8, 8, 1},
+	{HALMAC_TRX_MODE_WMM, 16, 16, 16, 14, 1},
+	{HALMAC_TRX_MODE_P2P, 16, 16, 16, 14, 1},
+	{HALMAC_TRX_MODE_LOOPBACK, 16, 16, 16, 14, 256},
+	{HALMAC_TRX_MODE_DELAY_LOOPBACK, 16, 16, 16, 14, 256},
+};
+#endif
+
+/*PCIE Page Number*/
+HALMAC_PG_NUM HALMAC_PG_NUM_PCIE_8821C[] = {
+	/* { mode, hq_num, nq_num, lq_num, exq_num, gap_num} */
+	{HALMAC_TRX_MODE_NORMAL, 16, 16, 16, 14, 1},
+	{HALMAC_TRX_MODE_TRXSHARE, 16, 16, 16, 14, 1},
+	{HALMAC_TRX_MODE_WMM, 16, 16, 16, 14, 1},
+	{HALMAC_TRX_MODE_P2P, 16, 16, 16, 14, 1},
+	{HALMAC_TRX_MODE_LOOPBACK, 16, 16, 16, 14, 256},
+	{HALMAC_TRX_MODE_DELAY_LOOPBACK, 16, 16, 16, 14, 256},
+};
+
+/*USB 2 Bulkout Page Number*/
+HALMAC_PG_NUM HALMAC_PG_NUM_2BULKOUT_8821C[] = {
+	/* { mode, hq_num, nq_num, lq_num, exq_num, gap_num} */
+	{HALMAC_TRX_MODE_NORMAL, 16, 16, 0, 0, 1},
+	{HALMAC_TRX_MODE_TRXSHARE, 16, 16, 0, 0, 1},
+	{HALMAC_TRX_MODE_WMM, 16, 16, 0, 0, 1},
+	{HALMAC_TRX_MODE_P2P, 16, 16, 0, 0, 1},
+	{HALMAC_TRX_MODE_LOOPBACK, 16, 16, 0, 0, 256},
+	{HALMAC_TRX_MODE_DELAY_LOOPBACK, 16, 16, 0, 0, 256},
+};
+
+/*USB 3 Bulkout Page Number*/
+HALMAC_PG_NUM HALMAC_PG_NUM_3BULKOUT_8821C[] = {
+	/* { mode, hq_num, nq_num, lq_num, exq_num, gap_num} */
+	{HALMAC_TRX_MODE_NORMAL, 16, 16, 16, 0, 1},
+	{HALMAC_TRX_MODE_TRXSHARE, 16, 16, 16, 0, 1},
+	{HALMAC_TRX_MODE_WMM, 16, 16, 16, 0, 1},
+	{HALMAC_TRX_MODE_P2P, 16, 16, 16, 0, 1},
+	{HALMAC_TRX_MODE_LOOPBACK, 16, 16, 16, 0, 256},
+	{HALMAC_TRX_MODE_DELAY_LOOPBACK, 16, 16, 16, 0, 256},
+};
+
+/*USB 4 Bulkout Page Number*/
+HALMAC_PG_NUM HALMAC_PG_NUM_4BULKOUT_8821C[] = {
+	/* { mode, hq_num, nq_num, lq_num, exq_num, gap_num} */
+	{HALMAC_TRX_MODE_NORMAL, 16, 16, 16, 14, 1},
+	{HALMAC_TRX_MODE_TRXSHARE, 16, 16, 16, 14, 1},
+	{HALMAC_TRX_MODE_WMM, 16, 16, 16, 14, 1},
+	{HALMAC_TRX_MODE_P2P, 16, 16, 16, 14, 1},
+	{HALMAC_TRX_MODE_LOOPBACK, 16, 16, 16, 14, 256},
+	{HALMAC_TRX_MODE_DELAY_LOOPBACK, 16, 16, 16, 14, 256},
+};
+
+HALMAC_RET_STATUS
+halmac_txdma_queue_mapping_8821c(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN HALMAC_TRX_MODE halmac_trx_mode
+)
+{
+	u16 value16;
+	VOID *pDriver_adapter = NULL;
+	PHALMAC_RQPN pCurr_rqpn_Sel = NULL;
+	HALMAC_RET_STATUS status;
+	PHALMAC_API pHalmac_api;
+
+	pDriver_adapter = pHalmac_adapter->pDriver_adapter;
+	pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api;
+
+	if (HALMAC_INTERFACE_SDIO == pHalmac_adapter->halmac_interface) {
+		pCurr_rqpn_Sel = HALMAC_RQPN_SDIO_8821C;
+	} else if (HALMAC_INTERFACE_PCIE == pHalmac_adapter->halmac_interface) {
+		pCurr_rqpn_Sel = HALMAC_RQPN_PCIE_8821C;
+	} else if (HALMAC_INTERFACE_USB == pHalmac_adapter->halmac_interface) {
+		if (pHalmac_adapter->halmac_bulkout_num == 2) {
+			pCurr_rqpn_Sel = HALMAC_RQPN_2BULKOUT_8821C;
+		} else if (pHalmac_adapter->halmac_bulkout_num == 3) {
+			pCurr_rqpn_Sel = HALMAC_RQPN_3BULKOUT_8821C;
+		} else if (pHalmac_adapter->halmac_bulkout_num == 4) {
+			pCurr_rqpn_Sel = HALMAC_RQPN_4BULKOUT_8821C;
+		} else {
+			PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "interface not support\n");
+			return HALMAC_RET_NOT_SUPPORT;
+		}
+	}
+
+	status = halmac_rqpn_parser_88xx(pHalmac_adapter, halmac_trx_mode, pCurr_rqpn_Sel);
+	if (HALMAC_RET_SUCCESS != status)
+		return status;
+
+	value16 = 0;
+	value16 |= BIT_TXDMA_HIQ_MAP(pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_HI]);
+	value16 |= BIT_TXDMA_MGQ_MAP(pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_MG]);
+	value16 |= BIT_TXDMA_BKQ_MAP(pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_BK]);
+	value16 |= BIT_TXDMA_BEQ_MAP(pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_BE]);
+	value16 |= BIT_TXDMA_VIQ_MAP(pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_VI]);
+	value16 |= BIT_TXDMA_VOQ_MAP(pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_VO]);
+	HALMAC_REG_WRITE_16(pHalmac_adapter, REG_TXDMA_PQ_MAP, value16);
+
+	return HALMAC_RET_SUCCESS;
+}
+
+HALMAC_RET_STATUS
+halmac_priority_queue_config_8821c(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN HALMAC_TRX_MODE halmac_trx_mode
+)
+{
+	u8 transfer_mode = 0;
+	u8 value8;
+	u32 counter;
+	HALMAC_RET_STATUS status;
+	PHALMAC_PG_NUM pCurr_pg_num = NULL;
+	VOID *pDriver_adapter = NULL;
+	PHALMAC_API pHalmac_api;
+
+	pDriver_adapter = pHalmac_adapter->pDriver_adapter;
+	pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api;
+
+	if (HALMAC_LA_MODE_DISABLE == pHalmac_adapter->txff_allocation.la_mode) {
+		if (HALMAC_RX_FIFO_EXPANDING_MODE_DISABLE == pHalmac_adapter->txff_allocation.rx_fifo_expanding_mode) {
+			pHalmac_adapter->txff_allocation.tx_fifo_pg_num = HALMAC_TX_FIFO_SIZE_8821C >> HALMAC_TX_PAGE_SIZE_2_POWER_8821C;
+		} else if (HALMAC_RX_FIFO_EXPANDING_MODE_1_BLOCK == pHalmac_adapter->txff_allocation.rx_fifo_expanding_mode) {
+			pHalmac_adapter->txff_allocation.tx_fifo_pg_num = HALMAC_TX_FIFO_SIZE_RX_FIFO_EXPANDING_1_BLOCK_8821C >> HALMAC_TX_PAGE_SIZE_2_POWER_8821C;
+			pHalmac_adapter->hw_config_info.tx_fifo_size = HALMAC_TX_FIFO_SIZE_RX_FIFO_EXPANDING_1_BLOCK_8821C;
+			if (HALMAC_RX_FIFO_SIZE_RX_FIFO_EXPANDING_1_BLOCK_8821C <= HALMAC_RX_FIFO_SIZE_RX_FIFO_EXPANDING_1_BLOCK_MAX_8821C)
+				pHalmac_adapter->hw_config_info.rx_fifo_size = HALMAC_RX_FIFO_SIZE_RX_FIFO_EXPANDING_1_BLOCK_8821C;
+			else
+				pHalmac_adapter->hw_config_info.rx_fifo_size = HALMAC_RX_FIFO_SIZE_RX_FIFO_EXPANDING_1_BLOCK_MAX_8821C;
+		} else {
+			pHalmac_adapter->txff_allocation.tx_fifo_pg_num = HALMAC_TX_FIFO_SIZE_8821C >> HALMAC_TX_PAGE_SIZE_2_POWER_8821C;
+			PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "rx_fifo_expanding_mode = %d not support\n", pHalmac_adapter->txff_allocation.rx_fifo_expanding_mode);
+		}
+	} else {
+		pHalmac_adapter->txff_allocation.tx_fifo_pg_num = HALMAC_TX_FIFO_SIZE_LA_8821C >> HALMAC_TX_PAGE_SIZE_2_POWER_8821C;
+	}
+	pHalmac_adapter->txff_allocation.rsvd_pg_num = (pHalmac_adapter->txff_allocation.rsvd_drv_pg_num +
+							HALMAC_RSVD_H2C_EXTRAINFO_PGNUM_8821C +
+							HALMAC_RSVD_H2C_QUEUE_PGNUM_8821C +
+							HALMAC_RSVD_CPU_INSTRUCTION_PGNUM_8821C +
+							HALMAC_RSVD_FW_TXBUFF_PGNUM_8821C);
+	if (pHalmac_adapter->txff_allocation.rsvd_pg_num > pHalmac_adapter->txff_allocation.tx_fifo_pg_num)
+		return HALMAC_RET_CFG_TXFIFO_PAGE_FAIL;
+
+	pHalmac_adapter->txff_allocation.ac_q_pg_num = pHalmac_adapter->txff_allocation.tx_fifo_pg_num - pHalmac_adapter->txff_allocation.rsvd_pg_num;
+	pHalmac_adapter->txff_allocation.rsvd_pg_bndy = pHalmac_adapter->txff_allocation.tx_fifo_pg_num - pHalmac_adapter->txff_allocation.rsvd_pg_num;
+	pHalmac_adapter->txff_allocation.rsvd_fw_txbuff_pg_bndy = pHalmac_adapter->txff_allocation.tx_fifo_pg_num - HALMAC_RSVD_FW_TXBUFF_PGNUM_8821C;
+	pHalmac_adapter->txff_allocation.rsvd_cpu_instr_pg_bndy = pHalmac_adapter->txff_allocation.rsvd_fw_txbuff_pg_bndy - HALMAC_RSVD_CPU_INSTRUCTION_PGNUM_8821C;
+	pHalmac_adapter->txff_allocation.rsvd_h2c_queue_pg_bndy = pHalmac_adapter->txff_allocation.rsvd_cpu_instr_pg_bndy - HALMAC_RSVD_H2C_QUEUE_PGNUM_8821C;
+	pHalmac_adapter->txff_allocation.rsvd_h2c_extra_info_pg_bndy = pHalmac_adapter->txff_allocation.rsvd_h2c_queue_pg_bndy - HALMAC_RSVD_H2C_EXTRAINFO_PGNUM_8821C;
+	pHalmac_adapter->txff_allocation.rsvd_drv_pg_bndy = pHalmac_adapter->txff_allocation.rsvd_h2c_extra_info_pg_bndy - pHalmac_adapter->txff_allocation.rsvd_drv_pg_num;
+
+	if (HALMAC_INTERFACE_SDIO == pHalmac_adapter->halmac_interface) {
+		pCurr_pg_num = HALMAC_PG_NUM_SDIO_8821C;
+	} else if (HALMAC_INTERFACE_PCIE == pHalmac_adapter->halmac_interface) {
+		pCurr_pg_num = HALMAC_PG_NUM_PCIE_8821C;
+	} else if (HALMAC_INTERFACE_USB == pHalmac_adapter->halmac_interface) {
+		if (pHalmac_adapter->halmac_bulkout_num == 2) {
+			pCurr_pg_num = HALMAC_PG_NUM_2BULKOUT_8821C;
+		} else if (pHalmac_adapter->halmac_bulkout_num == 3) {
+			pCurr_pg_num = HALMAC_PG_NUM_3BULKOUT_8821C;
+		} else if (pHalmac_adapter->halmac_bulkout_num == 4) {
+			pCurr_pg_num = HALMAC_PG_NUM_4BULKOUT_8821C;
+		} else {
+			PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "interface not support\n");
+			return HALMAC_RET_NOT_SUPPORT;
+		}
+	}
+
+	status = halmac_pg_num_parser_88xx(pHalmac_adapter, halmac_trx_mode, pCurr_pg_num);
+	if (HALMAC_RET_SUCCESS != status)
+		return status;
+
+	PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "Set FIFO page\n");
+
+	HALMAC_REG_WRITE_16(pHalmac_adapter, REG_FIFOPAGE_INFO_1, pHalmac_adapter->txff_allocation.high_queue_pg_num);
+	HALMAC_REG_WRITE_16(pHalmac_adapter, REG_FIFOPAGE_INFO_2, pHalmac_adapter->txff_allocation.low_queue_pg_num);
+	HALMAC_REG_WRITE_16(pHalmac_adapter, REG_FIFOPAGE_INFO_3, pHalmac_adapter->txff_allocation.normal_queue_pg_num);
+	HALMAC_REG_WRITE_16(pHalmac_adapter, REG_FIFOPAGE_INFO_4, pHalmac_adapter->txff_allocation.extra_queue_pg_num);
+	HALMAC_REG_WRITE_16(pHalmac_adapter, REG_FIFOPAGE_INFO_5, pHalmac_adapter->txff_allocation.pub_queue_pg_num);
+
+	pHalmac_adapter->sdio_free_space.high_queue_number = pHalmac_adapter->txff_allocation.high_queue_pg_num;
+	pHalmac_adapter->sdio_free_space.normal_queue_number = pHalmac_adapter->txff_allocation.normal_queue_pg_num;
+	pHalmac_adapter->sdio_free_space.low_queue_number = pHalmac_adapter->txff_allocation.low_queue_pg_num;
+	pHalmac_adapter->sdio_free_space.public_queue_number = pHalmac_adapter->txff_allocation.pub_queue_pg_num;
+	pHalmac_adapter->sdio_free_space.extra_queue_number = pHalmac_adapter->txff_allocation.extra_queue_pg_num;
+
+	HALMAC_REG_WRITE_32(pHalmac_adapter, REG_RQPN_CTRL_2, HALMAC_REG_READ_32(pHalmac_adapter, REG_RQPN_CTRL_2) | BIT(31));
+
+	HALMAC_REG_WRITE_16(pHalmac_adapter, REG_FIFOPAGE_CTRL_2, (u16)(pHalmac_adapter->txff_allocation.rsvd_pg_bndy & BIT_MASK_BCN_HEAD_1_V1));
+	HALMAC_REG_WRITE_16(pHalmac_adapter, REG_BCNQ_BDNY_V1, (u16)(pHalmac_adapter->txff_allocation.rsvd_pg_bndy & BIT_MASK_BCNQ_PGBNDY_V1));
+	HALMAC_REG_WRITE_16(pHalmac_adapter, REG_FIFOPAGE_CTRL_2 + 2, (u16)(pHalmac_adapter->txff_allocation.rsvd_pg_bndy & BIT_MASK_BCN_HEAD_1_V1));
+	HALMAC_REG_WRITE_16(pHalmac_adapter, REG_BCNQ1_BDNY_V1, (u16)(pHalmac_adapter->txff_allocation.rsvd_pg_bndy & BIT_MASK_BCNQ_PGBNDY_V1));
+
+	HALMAC_REG_WRITE_32(pHalmac_adapter, REG_RXFF_BNDY, pHalmac_adapter->hw_config_info.rx_fifo_size - HALMAC_C2H_PKT_BUF_8821C - 1);
+
+	PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "Init LLT table\n");
+
+	if (HALMAC_INTERFACE_USB == pHalmac_adapter->halmac_interface) {
+		value8 = (u8)(HALMAC_REG_READ_8(pHalmac_adapter, REG_AUTO_LLT_V1) & ~(BIT_MASK_BLK_DESC_NUM << BIT_SHIFT_BLK_DESC_NUM));
+		value8 = (u8)(value8 | (HALMAC_BLK_DESC_NUM_8821C << BIT_SHIFT_BLK_DESC_NUM));
+		HALMAC_REG_WRITE_8(pHalmac_adapter, REG_AUTO_LLT_V1, value8);
+
+		HALMAC_REG_WRITE_8(pHalmac_adapter, REG_AUTO_LLT_V1 + 3, HALMAC_BLK_DESC_NUM_8821C);
+		HALMAC_REG_WRITE_8(pHalmac_adapter, REG_TXDMA_OFFSET_CHK + 1, HALMAC_REG_READ_8(pHalmac_adapter, REG_TXDMA_OFFSET_CHK + 1) | BIT(1));
+	}
+
+	HALMAC_REG_WRITE_8(pHalmac_adapter, REG_AUTO_LLT_V1, (u8)(HALMAC_REG_READ_8(pHalmac_adapter, REG_AUTO_LLT_V1) | BIT_AUTO_INIT_LLT_V1));
+	counter = 1000;
+	while (HALMAC_REG_READ_8(pHalmac_adapter, REG_AUTO_LLT_V1) & BIT_AUTO_INIT_LLT_V1) {
+		counter--;
+		if (counter == 0)
+			return HALMAC_RET_INIT_LLT_FAIL;
+	}
+
+	if (HALMAC_TRX_MODE_DELAY_LOOPBACK == halmac_trx_mode) {
+		transfer_mode = HALMAC_TRNSFER_LOOPBACK_DELAY;
+		HALMAC_REG_WRITE_16(pHalmac_adapter, REG_WMAC_LBK_BUF_HD_V1, (u16)pHalmac_adapter->txff_allocation.rsvd_pg_bndy);
+	} else if (HALMAC_TRX_MODE_LOOPBACK == halmac_trx_mode)
+		transfer_mode = HALMAC_TRNSFER_LOOPBACK_DIRECT;
+	else
+		transfer_mode = HALMAC_TRNSFER_NORMAL;
+
+	HALMAC_REG_WRITE_8(pHalmac_adapter, REG_CR + 3, (u8)transfer_mode);
+
+	return HALMAC_RET_SUCCESS;
+}
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/halmac/halmac_88xx/halmac_8821c/halmac_func_8821c.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/halmac/halmac_88xx/halmac_8821c/halmac_func_8821c.h
--- linux-5.6.3/3rdparty/rtl8821ce/hal/halmac/halmac_88xx/halmac_8821c/halmac_func_8821c.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/halmac/halmac_88xx/halmac_8821c/halmac_func_8821c.h	2020-04-10 16:35:06.791658901 +0300
@@ -0,0 +1,19 @@
+#ifndef _HALMAC_FUNC_8821C_H_
+#define _HALMAC_FUNC_8821C_H_
+
+#include "../../halmac_type.h"
+
+HALMAC_RET_STATUS
+halmac_txdma_queue_mapping_8821c(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN HALMAC_TRX_MODE halmac_trx_mode
+);
+
+
+HALMAC_RET_STATUS
+halmac_priority_queue_config_8821c(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN HALMAC_TRX_MODE halmac_trx_mode
+);
+
+#endif /* _HALMAC_FUNC_8821C_H_ */
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/halmac/halmac_88xx/halmac_8821c/halmac_gpio_8821c.c linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/halmac/halmac_88xx/halmac_8821c/halmac_gpio_8821c.c
--- linux-5.6.3/3rdparty/rtl8821ce/hal/halmac/halmac_88xx/halmac_8821c/halmac_gpio_8821c.c	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/halmac/halmac_88xx/halmac_8821c/halmac_gpio_8821c.c	2020-04-10 16:35:06.791658901 +0300
@@ -0,0 +1,846 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ ******************************************************************************/
+
+#include "halmac_gpio_8821c.h"
+#include "../halmac_gpio_88xx.h"
+
+#if HALMAC_8821C_SUPPORT
+
+/* P_LED0 definition */
+#define GPIO0_BT_GPIO0_8821C	\
+	{HALMAC_BT_GPIO, HALMAC_GPIO0, HALMAC_GPIO_IN_OUT, \
+	 0x66, BIT(2), BIT(2)}
+#define GPIO0_BT_GPIO0_8821C	\
+	{HALMAC_BT_GPIO, HALMAC_GPIO0, HALMAC_GPIO_IN_OUT, \
+	 0x66, BIT(2), BIT(2)}
+#define GPIO0_BT_ACT_8821C	\
+	{HALMAC_BT_PTA, HALMAC_GPIO0, HALMAC_GPIO_IN_OUT, \
+	 0x41, BIT(1), 0}
+#define GPIO0_WL_ACT_8821C	\
+	{HALMAC_WL_PTA, HALMAC_GPIO0, HALMAC_GPIO_IN_OUT, \
+	 0x41, BIT(2), BIT(2)}
+#define GPIO0_WLMAC_DBG_GPIO0_8821C	\
+	{HALMAC_WLMAC_DBG, HALMAC_GPIO0, HALMAC_GPIO_OUT, \
+	 0x40, BIT(1) | BIT(0), BIT(0)}
+#define GPIO0_WLPHY_DBG_GPIO0_8821C	\
+	{HALMAC_WLPHY_DBG, HALMAC_GPIO0, HALMAC_GPIO_IN_OUT, \
+	 0x40, BIT(1) | BIT(0), BIT(1)}
+#define GPIO0_BT_DBG_GPIO0_8821C	\
+	{HALMAC_BT_DBG, HALMAC_GPIO0, HALMAC_GPIO_OUT, \
+	 0x40, BIT(1) | BIT(0), BIT(0) | BIT(1)}
+#define GPIO0_SW_IO_8821C	\
+	{HALMAC_SW_IO, HALMAC_GPIO0, HALMAC_GPIO_IN_OUT, \
+	 0x40, BIT(1) | BIT(0), 0}
+
+/* GPIO1 definition */
+#define GPIO1_BT_GPIO1_8821C	\
+	{HALMAC_BT_GPIO, HALMAC_GPIO1, HALMAC_GPIO_IN_OUT, \
+	 0x66, BIT(2), BIT(2)}
+#define GPIO1_BT_3DD_SYNC_A_8821C	\
+	{HALMAC_BT_3DDLS_A, HALMAC_GPIO1, HALMAC_GPIO_IN, \
+	 0x66, BIT(2), BIT(2)}
+#define GPIO1_WL_CK_8821C	\
+	{HALMAC_BT_PTA, HALMAC_GPIO1, HALMAC_GPIO_OUT, \
+	 0x41, BIT(1), 0}
+#define GPIO1_BT_CK_8821C	\
+	{HALMAC_WL_PTA, HALMAC_GPIO1, HALMAC_GPIO_OUT, \
+	 0x41, BIT(2), BIT(2)}
+#define GPIO1_WLMAC_DBG_GPIO1_8821C	\
+	{HALMAC_WLMAC_DBG, HALMAC_GPIO1, HALMAC_GPIO_OUT, \
+	 0x40, BIT(1) | BIT(0), BIT(0)}
+#define GPIO1_WLPHY_DBG_GPIO1_8821C	\
+	{HALMAC_WLPHY_DBG, HALMAC_GPIO1, HALMAC_GPIO_IN_OUT, \
+	 0x40, BIT(1) | BIT(0), BIT(1)}
+#define GPIO1_BT_DBG_GPIO1_8821C	\
+	{HALMAC_BT_DBG, HALMAC_GPIO1, HALMAC_GPIO_OUT, \
+	 0x40, BIT(1) | BIT(0), BIT(0) | BIT(1)}
+#define GPIO1_SW_IO_8821C	\
+	{HALMAC_SW_IO, HALMAC_GPIO1, HALMAC_GPIO_IN_OUT, \
+	 0x40, BIT(1) | BIT(0), 0}
+
+/* GPIO2 definition */
+#define GPIO2_BT_GPIO2_8821C	\
+	{HALMAC_BT_GPIO, HALMAC_GPIO2, HALMAC_GPIO_IN_OUT, \
+	 0x66, BIT(2), BIT(2)}
+#define GPIO2_WL_STATE_8821C	\
+	{HALMAC_BT_PTA, HALMAC_GPIO2, HALMAC_GPIO_OUT, \
+	 0x41, BIT(1), 0}
+#define GPIO2_BT_STATE_8821C	\
+	{HALMAC_WL_PTA, HALMAC_GPIO2, HALMAC_GPIO_OUT, \
+	 0x41, BIT(2), BIT(2)}
+#define GPIO2_WLMAC_DBG_GPIO2_8821C	\
+	{HALMAC_WLMAC_DBG, HALMAC_GPIO2, HALMAC_GPIO_OUT, \
+	 0x40, BIT(1) | BIT(0), BIT(0)}
+#define GPIO2_WLPHY_DBG_GPIO2_8821C	\
+	{HALMAC_WLPHY_DBG, HALMAC_GPIO2, HALMAC_GPIO_IN_OUT, \
+	 0x40, BIT(1) | BIT(0), BIT(1)}
+#define GPIO2_BT_DBG_GPIO2_8821C	\
+	{HALMAC_BT_DBG, HALMAC_GPIO2, HALMAC_GPIO_OUT, \
+	 0x40, BIT(1) | BIT(0), BIT(0) | BIT(1)}
+#define GPIO2_RFE_CTRL_5_8821C	\
+	{HALMAC_WLPHY_RFE_CTRL2GPIO, HALMAC_GPIO2, HALMAC_GPIO_IN_OUT, \
+	 0x40, BIT(2), BIT(2)}
+#define GPIO2_SW_IO_8821C	\
+	{HALMAC_SW_IO, HALMAC_GPIO2, HALMAC_GPIO_IN_OUT, \
+	 0x40, BIT(1) | BIT(0), 0}
+
+/* GPIO3 definition */
+#define GPIO3_BT_GPIO3_8821C	\
+	{HALMAC_BT_GPIO, HALMAC_GPIO3, HALMAC_GPIO_IN_OUT, \
+	 0x66, BIT(2), BIT(2)}
+#define GPIO3_WL_PRI_8821C	\
+	{HALMAC_BT_PTA, HALMAC_GPIO3, HALMAC_GPIO_OUT, \
+	 0x41, BIT(1), 0}
+#define GPIO3_BT_PRI_8821C	\
+	{HALMAC_WL_PTA, HALMAC_GPIO3, HALMAC_GPIO_OUT, \
+	 0x41, BIT(2), BIT(2)}
+#define GPIO3_WLMAC_DBG_GPIO3_8821C	\
+	{HALMAC_WLMAC_DBG, HALMAC_GPIO3, HALMAC_GPIO_OUT, \
+	 0x40, BIT(1) | BIT(0), BIT(0)}
+#define GPIO3_WLPHY_DBG_GPIO3_8821C	\
+	{HALMAC_WLPHY_DBG, HALMAC_GPIO3, HALMAC_GPIO_IN_OUT, \
+	 0x40, BIT(1) | BIT(0), BIT(1)}
+#define GPIO3_BT_DBG_GPIO3_8821C	\
+	{HALMAC_BT_DBG, HALMAC_GPIO3, HALMAC_GPIO_OUT, \
+	 0x40, BIT(1) | BIT(0), BIT(0) | BIT(1)}
+#define GPIO3_RFE_CTRL_4_8821C	\
+	{HALMAC_WLPHY_RFE_CTRL2GPIO, HALMAC_GPIO3, HALMAC_GPIO_IN_OUT, \
+	 0x40, BIT(2), BIT(2)}
+#define GPIO3_SW_IO_8821C	\
+	{HALMAC_SW_IO, HALMAC_GPIO3, HALMAC_GPIO_IN_OUT, \
+	 0x40, BIT(1) | BIT(0), 0}
+
+/* GPIO4 definition */
+#define GPIO4_BT_SPI_D0_8821C	\
+	{HALMAC_BT_SFLASH, HALMAC_GPIO4, HALMAC_GPIO_IN_OUT, \
+	 0x66, BIT(4), BIT(4)}
+#define GPIO4_WL_SPI_D0_8821C	\
+	{HALMAC_WL_SFLASH, HALMAC_GPIO4, HALMAC_GPIO_IN_OUT, \
+	 0x42, BIT(3), BIT(3)}
+#define GPIO4_SDIO_INT_8821C	\
+	{HALMAC_SDIO_INT, HALMAC_GPIO4, HALMAC_GPIO_OUT, \
+	 0x72, BIT(2), BIT(2)}
+#define GPIO4_JTAG_TRST_8821C	\
+	{HALMAC_JTAG, HALMAC_GPIO4, HALMAC_GPIO_IN, \
+	 0x67, BIT(0), BIT(0)}
+#define GPIO4_DBG_GNT_WL_8821C	\
+	{HALMAC_DBG_GNT_WL_BT, HALMAC_GPIO4, HALMAC_GPIO_OUT, \
+	 0x73, BIT(3), BIT(3)}
+#define GPIO4_WLMAC_DBG_GPIO4_8821C	\
+	{HALMAC_WLMAC_DBG, HALMAC_GPIO4, HALMAC_GPIO_OUT, \
+	 0x40, BIT(1) | BIT(0), BIT(0)}
+#define GPIO4_WLPHY_DBG_GPIO4_8821C	\
+	{HALMAC_WLPHY_DBG, HALMAC_GPIO4, HALMAC_GPIO_IN_OUT, \
+	 0x40, BIT(1) | BIT(0), BIT(1)}
+#define GPIO4_BT_DBG_GPIO4_8821C	\
+	{HALMAC_BT_DBG, HALMAC_GPIO4, HALMAC_GPIO_OUT, \
+	 0x40, BIT(1) | BIT(0), BIT(0) | BIT(1)}
+#define GPIO4_SW_IO_8821C	\
+	{HALMAC_SW_IO, HALMAC_GPIO4, HALMAC_GPIO_IN_OUT, \
+	 0x40, BIT(1) | BIT(0), 0}
+
+/* GPIO5 definition */
+#define GPIO5_BT_SPI_D1_8821C	\
+	{HALMAC_BT_SFLASH, HALMAC_GPIO5, HALMAC_GPIO_IN_OUT, \
+	 0x66, BIT(4), BIT(4)}
+#define GPIO5_WL_SPI_D1_8821C	\
+	{HALMAC_WL_SFLASH, HALMAC_GPIO5, HALMAC_GPIO_IN_OUT, \
+	 0x42, BIT(3), BIT(3)}
+#define GPIO5_JTAG_TDI_8821C	\
+	{HALMAC_JTAG, HALMAC_GPIO5, HALMAC_GPIO_IN, \
+	 0x67, BIT(0), BIT(0)}
+#define GPIO5_DBG_GNT_BT_8821C	\
+	{HALMAC_DBG_GNT_WL_BT, HALMAC_GPIO5, HALMAC_GPIO_OUT, \
+	 0x73, BIT(3), BIT(3)}
+#define GPIO5_WLMAC_DBG_GPIO5_8821C	\
+	{HALMAC_WLMAC_DBG, HALMAC_GPIO5, HALMAC_GPIO_OUT, \
+	 0x40, BIT(1) | BIT(0), BIT(0)}
+#define GPIO5_WLPHY_DBG_GPIO5_8821C	\
+	{HALMAC_WLPHY_DBG, HALMAC_GPIO5, HALMAC_GPIO_IN_OUT, \
+	 0x40, BIT(1) | BIT(0), BIT(1)}
+#define GPIO5_BT_DBG_GPIO5_8821C	\
+	{HALMAC_BT_DBG, HALMAC_GPIO5, HALMAC_GPIO_OUT, \
+	 0x40, BIT(1) | BIT(0), BIT(0) | BIT(1)}
+#define GPIO5_SW_IO_8821C	\
+	{HALMAC_SW_IO, HALMAC_GPIO5, HALMAC_GPIO_IN_OUT, \
+	 0x40, BIT(1) | BIT(0), 0}
+
+/* GPIO6 definition */
+#define GPIO6_BT_SPI_D2_8821C	\
+	{HALMAC_BT_SFLASH, HALMAC_GPIO6, HALMAC_GPIO_IN_OUT, \
+	 0x66, BIT(4), BIT(4)}
+#define GPIO6_WL_SPI_D2_8821C	\
+	{HALMAC_WL_SFLASH, HALMAC_GPIO6, HALMAC_GPIO_IN_OUT, \
+	 0x42, BIT(3), BIT(3)}
+#define GPIO6_EEDO_8821C	\
+	{HALMAC_EEPROM, HALMAC_GPIO6, HALMAC_GPIO_IN, \
+	 0x40, BIT(4), BIT(4)}
+#define GPIO6_JTAG_TDO_8821C	\
+	{HALMAC_JTAG, HALMAC_GPIO6, HALMAC_GPIO_OUT, \
+	 0x67, BIT(0), BIT(0)}
+#define GPIO6_BT_3DD_SYNC_B_8821C	\
+	{HALMAC_BT_3DDLS_B, HALMAC_GPIO6, HALMAC_GPIO_IN, \
+	 0x67, BIT(1), BIT(1)}
+#define GPIO6_BT_GPIO18_8821C	\
+	{HALMAC_BT_GPIO, HALMAC_GPIO6, HALMAC_GPIO_IN_OUT, \
+	 0x67, BIT(1), BIT(1)}
+#define GPIO6_SIN_8821C	\
+	{HALMAC_WL_UART, HALMAC_GPIO6, HALMAC_GPIO_IN, \
+	 0x41, BIT(0), BIT(0)}
+#define GPIO6_WLMAC_DBG_GPIO6_8821C	\
+	{HALMAC_WLMAC_DBG, HALMAC_GPIO6, HALMAC_GPIO_OUT, \
+	 0x40, BIT(1) | BIT(0), BIT(0)}
+#define GPIO6_WLPHY_DBG_GPIO6_8821C	\
+	{HALMAC_WLPHY_DBG, HALMAC_GPIO6, HALMAC_GPIO_IN_OUT, \
+	 0x40, BIT(1) | BIT(0), BIT(1)}
+#define GPIO6_BT_DBG_GPIO6_8821C	\
+	{HALMAC_BT_DBG, HALMAC_GPIO6, HALMAC_GPIO_OUT, \
+	 0x40, BIT(1) | BIT(0), BIT(0) | BIT(1)}
+#define GPIO6_SW_IO_8821C	\
+	{HALMAC_SW_IO, HALMAC_GPIO6, HALMAC_GPIO_IN_OUT, \
+	 0x40, BIT(1) | BIT(0), 0}
+
+/* GPIO7 definition */
+#define GPIO7_BT_SPI_D3_8821C	\
+	{HALMAC_BT_SFLASH, HALMAC_GPIO7, HALMAC_GPIO_IN_OUT, \
+	 0x66, BIT(4), BIT(4)}
+#define GPIO7_WL_SPI_D3_8821C	\
+	{HALMAC_WL_SFLASH, HALMAC_GPIO7, HALMAC_GPIO_IN_OUT, \
+	 0x42, BIT(3), BIT(3)}
+#define GPIO7_EEDI_8821C	\
+	{HALMAC_EEPROM, HALMAC_GPIO7, HALMAC_GPIO_OUT, \
+	 0x40, BIT(4), BIT(4)}
+#define GPIO7_JTAG_TMS_8821C	\
+	{HALMAC_JTAG, HALMAC_GPIO7, HALMAC_GPIO_IN, \
+	 0x67, BIT(0), BIT(0)}
+#define GPIO7_BT_GPIO16_8821C	\
+	{HALMAC_BT_GPIO, HALMAC_GPIO7, HALMAC_GPIO_IN_OUT, \
+	 0x67, BIT(2), BIT(2)}
+#define GPIO7_SOUT_8821C	\
+	{HALMAC_WL_UART, HALMAC_GPIO7, HALMAC_GPIO_OUT, \
+	 0x41, BIT(0), BIT(0)}
+#define GPIO7_WLMAC_DBG_GPIO7_8821C	\
+	{HALMAC_WLMAC_DBG, HALMAC_GPIO7, HALMAC_GPIO_OUT, \
+	 0x40, BIT(1) | BIT(0), BIT(0)}
+#define GPIO7_WLPHY_DBG_GPIO7_8821C	\
+	{HALMAC_WLPHY_DBG, HALMAC_GPIO7, HALMAC_GPIO_IN_OUT, \
+	 0x40, BIT(1) | BIT(0), BIT(1)}
+#define GPIO7_BT_DBG_GPIO7_8821C	\
+	{HALMAC_BT_DBG, HALMAC_GPIO7, HALMAC_GPIO_OUT, \
+	 0x40, BIT(1) | BIT(0), BIT(0) | BIT(1)}
+#define GPIO7_SW_IO_8821C	\
+	{HALMAC_SW_IO, HALMAC_GPIO7, HALMAC_GPIO_IN_OUT, \
+	 0x40, BIT(1) | BIT(0), 0}
+
+/* GPIO8 definition */
+#define GPIO8_WL_EXT_WOL_8821C	\
+	{HALMAC_WL_HW_EXTWOL, HALMAC_GPIO8, HALMAC_GPIO_IN, \
+	 0x4a, BIT(0) | BIT(1), BIT(0) | BIT(1)}
+#define GPIO8_WL_LED_8821C	\
+	{HALMAC_WL_LED, HALMAC_GPIO8, HALMAC_GPIO_OUT, \
+	 0x4e, BIT(5), BIT(5)}
+#define GPIO8_SW_IO_8821C	\
+	{HALMAC_SW_IO, HALMAC_GPIO8, HALMAC_GPIO_IN_OUT, \
+	 0x40, BIT(1) | BIT(0), 0}
+
+/* GPIO9 definition */
+#define GPIO9_DIS_WL_N_8821C	\
+	{HALMAC_WL_HWPDN, HALMAC_GPIO9, HALMAC_GPIO_IN, \
+	 0x68, BIT(3) | BIT(0), BIT(3) | BIT(0)}
+#define GPIO9_WL_EXT_WOL_8821C	\
+	{HALMAC_WL_HW_EXTWOL, HALMAC_GPIO9, HALMAC_GPIO_IN, \
+	 0x4a, BIT(0) | BIT(1), BIT(0)}
+#define GPIO9_USCTS0_8821C	\
+	{HALMAC_UART0, HALMAC_GPIO9, HALMAC_GPIO_IN, \
+	 0x66, BIT(6), BIT(6)}
+#define GPIO9_SW_IO_8821C	\
+	{HALMAC_SW_IO, HALMAC_GPIO9, HALMAC_GPIO_IN_OUT, \
+	 0x40, BIT(1) | BIT(0), 0}
+
+/* GPIO10 definition */
+#define GPIO10_SW_IO_8821C	\
+	{HALMAC_SW_IO, HALMAC_GPIO10, HALMAC_GPIO_IN_OUT, \
+	 0x40, BIT(1) | BIT(0), 0}
+
+/* GPIO11 definition */
+#define GPIO11_DIS_BT_N_8821C	\
+	{HALMAC_BT_HWPDN, HALMAC_GPIO11, HALMAC_GPIO_IN, \
+	 0x6a, BIT(0), BIT(0)}
+#define GPIO11_USOUT0_8821C	\
+	{HALMAC_UART0, HALMAC_GPIO11, HALMAC_GPIO_OUT, \
+	 0x66, BIT(6), BIT(6)}
+#define GPIO11_SW_IO_8821C	\
+	{HALMAC_SW_IO, HALMAC_GPIO11, HALMAC_GPIO_IN_OUT, \
+	 0x40, BIT(1) | BIT(0), 0}
+
+/* GPIO12 definition */
+#define GPIO12_USIN0_8821C	\
+	{HALMAC_UART0, HALMAC_GPIO12, HALMAC_GPIO_IN, \
+	 0x66, BIT(6), BIT(6)}
+#define GPIO12_SW_IO_8821C	\
+	{HALMAC_SW_IO, HALMAC_GPIO12, HALMAC_GPIO_IN_OUT, \
+	 0x40, BIT(1) | BIT(0), 0}
+
+/* GPIO13 definition */
+#define GPIO13_BT_WAKE_8821C	\
+	{HALMAC_GPIO13_14_WL_CTRL_EN, HALMAC_GPIO13, HALMAC_GPIO_IN, \
+	 0x4e, BIT(6), BIT(6)}
+#define GPIO13_SW_IO_8821C	\
+	{HALMAC_SW_IO, HALMAC_GPIO13, HALMAC_GPIO_IN_OUT, \
+	 0x40, BIT(1) | BIT(0), 0}
+
+/* GPIO14 definition */
+#define GPIO14_UART_WAKE_8821C	\
+	{HALMAC_GPIO13_14_WL_CTRL_EN, HALMAC_GPIO14, HALMAC_GPIO_OUT, \
+	 0x4e, BIT(6), BIT(6)}
+#define GPIO14_SW_IO_8821C	\
+	{HALMAC_SW_IO, HALMAC_GPIO14, HALMAC_GPIO_IN_OUT, \
+	 0x40, BIT(1) | BIT(0), 0}
+
+/* GPIO15 definition */
+#define GPIO15_EXT_XTAL_8821C	\
+	{HALMAC_EXT_XTAL, HALMAC_GPIO15, HALMAC_GPIO_OUT, \
+	 0x66, BIT(7), BIT(7)}
+#define GPIO15_SW_IO_8821C	\
+	{HALMAC_SW_IO, HALMAC_GPIO15, HALMAC_GPIO_IN_OUT, \
+	 0x40, BIT(1) | BIT(0), 0}
+
+static const struct halmac_gpio_pimux_list PINMUX_LIST_GPIO0_8821C[] = {
+	GPIO0_BT_GPIO0_8821C,
+	GPIO0_BT_ACT_8821C,
+	GPIO0_WL_ACT_8821C,
+	GPIO0_WLMAC_DBG_GPIO0_8821C,
+	GPIO0_WLPHY_DBG_GPIO0_8821C,
+	GPIO0_BT_DBG_GPIO0_8821C,
+	GPIO0_SW_IO_8821C
+};
+
+static const struct halmac_gpio_pimux_list PINMUX_LIST_GPIO1_8821C[] = {
+	GPIO1_BT_GPIO1_8821C,
+	GPIO1_BT_3DD_SYNC_A_8821C,
+	GPIO1_WL_CK_8821C,
+	GPIO1_BT_CK_8821C,
+	GPIO1_WLMAC_DBG_GPIO1_8821C,
+	GPIO1_WLPHY_DBG_GPIO1_8821C,
+	GPIO1_BT_DBG_GPIO1_8821C,
+	GPIO1_SW_IO_8821C
+};
+
+static const struct halmac_gpio_pimux_list PINMUX_LIST_GPIO2_8821C[] = {
+	GPIO2_BT_GPIO2_8821C,
+	GPIO2_WL_STATE_8821C,
+	GPIO2_BT_STATE_8821C,
+	GPIO2_WLMAC_DBG_GPIO2_8821C,
+	GPIO2_WLPHY_DBG_GPIO2_8821C,
+	GPIO2_BT_DBG_GPIO2_8821C,
+	GPIO2_RFE_CTRL_5_8821C,
+	GPIO2_SW_IO_8821C
+};
+
+static const struct halmac_gpio_pimux_list PINMUX_LIST_GPIO3_8821C[] = {
+	GPIO3_BT_GPIO3_8821C,
+	GPIO3_WL_PRI_8821C,
+	GPIO3_BT_PRI_8821C,
+	GPIO3_WLMAC_DBG_GPIO3_8821C,
+	GPIO3_WLPHY_DBG_GPIO3_8821C,
+	GPIO3_BT_DBG_GPIO3_8821C,
+	GPIO3_RFE_CTRL_4_8821C,
+	GPIO3_SW_IO_8821C
+};
+
+static const struct halmac_gpio_pimux_list PINMUX_LIST_GPIO4_8821C[] = {
+	GPIO4_BT_SPI_D0_8821C,
+	GPIO4_WL_SPI_D0_8821C,
+	GPIO4_SDIO_INT_8821C,
+	GPIO4_JTAG_TRST_8821C,
+	GPIO4_DBG_GNT_WL_8821C,
+	GPIO4_WLMAC_DBG_GPIO4_8821C,
+	GPIO4_WLPHY_DBG_GPIO4_8821C,
+	GPIO4_BT_DBG_GPIO4_8821C,
+	GPIO4_SW_IO_8821C
+};
+
+static const struct halmac_gpio_pimux_list PINMUX_LIST_GPIO5_8821C[] = {
+	GPIO5_BT_SPI_D1_8821C,
+	GPIO5_WL_SPI_D1_8821C,
+	GPIO5_JTAG_TDI_8821C,
+	GPIO5_DBG_GNT_BT_8821C,
+	GPIO5_WLMAC_DBG_GPIO5_8821C,
+	GPIO5_WLPHY_DBG_GPIO5_8821C,
+	GPIO5_BT_DBG_GPIO5_8821C,
+	GPIO5_SW_IO_8821C
+};
+
+static const struct halmac_gpio_pimux_list PINMUX_LIST_GPIO6_8821C[] = {
+	GPIO6_BT_SPI_D2_8821C,
+	GPIO6_WL_SPI_D2_8821C,
+	GPIO6_EEDO_8821C,
+	GPIO6_JTAG_TDO_8821C,
+	GPIO6_BT_3DD_SYNC_B_8821C,
+	GPIO6_BT_GPIO18_8821C,
+	GPIO6_SIN_8821C,
+	GPIO6_WLMAC_DBG_GPIO6_8821C,
+	GPIO6_WLPHY_DBG_GPIO6_8821C,
+	GPIO6_BT_DBG_GPIO6_8821C,
+	GPIO6_SW_IO_8821C
+};
+
+static const struct halmac_gpio_pimux_list PINMUX_LIST_GPIO7_8821C[] = {
+	GPIO7_BT_SPI_D3_8821C,
+	GPIO7_WL_SPI_D3_8821C,
+	GPIO7_EEDI_8821C,
+	GPIO7_JTAG_TMS_8821C,
+	GPIO7_BT_GPIO16_8821C,
+	GPIO7_SOUT_8821C,
+	GPIO7_WLMAC_DBG_GPIO7_8821C,
+	GPIO7_WLPHY_DBG_GPIO7_8821C,
+	GPIO7_BT_DBG_GPIO7_8821C,
+	GPIO7_SW_IO_8821C
+};
+
+static const struct halmac_gpio_pimux_list PINMUX_LIST_GPIO8_8821C[] = {
+	GPIO8_WL_EXT_WOL_8821C,
+	GPIO8_WL_LED_8821C,
+	GPIO8_SW_IO_8821C
+};
+
+static const struct halmac_gpio_pimux_list PINMUX_LIST_GPIO9_8821C[] = {
+	GPIO9_DIS_WL_N_8821C,
+	GPIO9_WL_EXT_WOL_8821C,
+	GPIO9_USCTS0_8821C,
+	GPIO9_SW_IO_8821C
+};
+
+static const struct halmac_gpio_pimux_list PINMUX_LIST_GPIO10_8821C[] = {
+	GPIO10_SW_IO_8821C
+};
+
+static const struct halmac_gpio_pimux_list PINMUX_LIST_GPIO11_8821C[] = {
+	GPIO11_DIS_BT_N_8821C,
+	GPIO11_USOUT0_8821C,
+	GPIO11_SW_IO_8821C
+};
+
+static const struct halmac_gpio_pimux_list PINMUX_LIST_GPIO12_8821C[] = {
+	GPIO12_USIN0_8821C,
+	GPIO12_SW_IO_8821C
+};
+
+static const struct halmac_gpio_pimux_list PINMUX_LIST_GPIO13_8821C[] = {
+	GPIO13_BT_WAKE_8821C,
+	GPIO13_SW_IO_8821C
+};
+
+static const struct halmac_gpio_pimux_list PINMUX_LIST_GPIO14_8821C[] = {
+	GPIO14_UART_WAKE_8821C,
+	GPIO14_SW_IO_8821C
+};
+
+static const struct halmac_gpio_pimux_list PINMUX_LIST_GPIO15_8821C[] = {
+	GPIO15_EXT_XTAL_8821C,
+	GPIO15_SW_IO_8821C
+};
+
+static enum halmac_ret_status
+get_pinmux_list_8821c(struct halmac_adapter *adapter,
+		      enum halmac_gpio_func gpio_func,
+		      const struct halmac_gpio_pimux_list **list,
+		      u32 *list_size, u32 *gpio_id);
+
+static enum halmac_ret_status
+chk_pinmux_valid_8821c(struct halmac_adapter *adapter,
+		       enum halmac_gpio_func gpio_func);
+
+/**
+ * pinmux_get_func_8821c() -get current gpio status
+ * @adapter : the adapter of halmac
+ * @gpio_func : gpio function
+ * @enable : function is enable(1) or disable(0)
+ * Author : Ivan Lin
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+pinmux_get_func_8821c(struct halmac_adapter *adapter,
+		      enum halmac_gpio_func gpio_func, u8 *enable)
+{
+	u32 list_size;
+	u32 cur_func;
+	u32 gpio_id;
+	enum halmac_ret_status status;
+	const struct halmac_gpio_pimux_list *list = NULL;
+
+	PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
+
+	status = get_pinmux_list_8821c(adapter, gpio_func, &list, &list_size,
+				       &gpio_id);
+	if (status != HALMAC_RET_SUCCESS)
+		return status;
+
+	status = pinmux_parser_88xx(adapter, list, list_size, gpio_id,
+				    &cur_func);
+	if (status != HALMAC_RET_SUCCESS)
+		return status;
+
+	switch (gpio_func) {
+	case HALMAC_GPIO_FUNC_WL_LED:
+		*enable = (cur_func == HALMAC_WL_LED) ? 1 : 0;
+		break;
+	case HALMAC_GPIO_FUNC_SDIO_INT:
+		*enable = (cur_func == HALMAC_SDIO_INT) ? 1 : 0;
+		break;
+	case HALMAC_GPIO_FUNC_BT_HOST_WAKE1:
+	case HALMAC_GPIO_FUNC_BT_DEV_WAKE1:
+		*enable = (cur_func == HALMAC_GPIO13_14_WL_CTRL_EN) ? 1 : 0;
+		break;
+	case HALMAC_GPIO_FUNC_SW_IO_0:
+	case HALMAC_GPIO_FUNC_SW_IO_1:
+	case HALMAC_GPIO_FUNC_SW_IO_2:
+	case HALMAC_GPIO_FUNC_SW_IO_3:
+	case HALMAC_GPIO_FUNC_SW_IO_4:
+	case HALMAC_GPIO_FUNC_SW_IO_5:
+	case HALMAC_GPIO_FUNC_SW_IO_6:
+	case HALMAC_GPIO_FUNC_SW_IO_7:
+	case HALMAC_GPIO_FUNC_SW_IO_8:
+	case HALMAC_GPIO_FUNC_SW_IO_9:
+	case HALMAC_GPIO_FUNC_SW_IO_10:
+	case HALMAC_GPIO_FUNC_SW_IO_11:
+	case HALMAC_GPIO_FUNC_SW_IO_12:
+	case HALMAC_GPIO_FUNC_SW_IO_13:
+	case HALMAC_GPIO_FUNC_SW_IO_14:
+	case HALMAC_GPIO_FUNC_SW_IO_15:
+		*enable = (cur_func == HALMAC_SW_IO) ? 1 : 0;
+		break;
+	default:
+		*enable = 0;
+		return HALMAC_RET_GET_PINMUX_ERR;
+	}
+
+	PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
+
+	return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * pinmux_set_func_8821c() -set gpio function
+ * @adapter : the adapter of halmac
+ * @gpio_func : gpio function
+ * Author : Ivan Lin
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+pinmux_set_func_8821c(struct halmac_adapter *adapter,
+		      enum halmac_gpio_func gpio_func)
+{
+	u32 list_size;
+	u32 gpio_id;
+	enum halmac_ret_status status;
+	const struct halmac_gpio_pimux_list *list = NULL;
+
+	PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
+	PLTFM_MSG_TRACE("[TRACE]func name : %d\n", gpio_func);
+
+	status = chk_pinmux_valid_8821c(adapter, gpio_func);
+	if (status != HALMAC_RET_SUCCESS)
+		return status;
+
+	status = get_pinmux_list_8821c(adapter, gpio_func, &list, &list_size,
+				       &gpio_id);
+	if (status != HALMAC_RET_SUCCESS)
+		return status;
+
+	status = pinmux_switch_88xx(adapter, list, list_size, gpio_id,
+				    gpio_func);
+	if (status != HALMAC_RET_SUCCESS)
+		return status;
+
+	status = pinmux_record_88xx(adapter, gpio_func, 1);
+	if (status != HALMAC_RET_SUCCESS)
+		return status;
+
+	PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
+
+	return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * pinmux_free_func_8821c() -free locked gpio function
+ * @adapter : the adapter of halmac
+ * @gpio_func : gpio function
+ * Author : Ivan Lin
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+pinmux_free_func_8821c(struct halmac_adapter *adapter,
+		       enum halmac_gpio_func gpio_func)
+{
+	struct halmac_pinmux_info *info = &adapter->pinmux_info;
+
+	PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
+
+	switch (gpio_func) {
+	case HALMAC_GPIO_FUNC_SW_IO_0:
+		info->sw_io_0 = 0;
+		break;
+	case HALMAC_GPIO_FUNC_SW_IO_1:
+		info->sw_io_1 = 0;
+		break;
+	case HALMAC_GPIO_FUNC_SW_IO_2:
+		info->sw_io_2 = 0;
+		break;
+	case HALMAC_GPIO_FUNC_SW_IO_3:
+		info->sw_io_3 = 0;
+		break;
+	case HALMAC_GPIO_FUNC_SW_IO_4:
+	case HALMAC_GPIO_FUNC_SDIO_INT:
+		info->sw_io_4 = 0;
+		info->sdio_int = 0;
+		break;
+	case HALMAC_GPIO_FUNC_SW_IO_5:
+		info->sw_io_5 = 0;
+		break;
+	case HALMAC_GPIO_FUNC_SW_IO_6:
+		info->sw_io_6 = 0;
+		break;
+	case HALMAC_GPIO_FUNC_SW_IO_7:
+		info->sw_io_7 = 0;
+		break;
+	case HALMAC_GPIO_FUNC_SW_IO_8:
+	case HALMAC_GPIO_FUNC_WL_LED:
+		info->sw_io_8 = 0;
+		info->wl_led = 0;
+		break;
+	case HALMAC_GPIO_FUNC_SW_IO_9:
+		info->sw_io_9 = 0;
+		break;
+	case HALMAC_GPIO_FUNC_SW_IO_10:
+		info->sw_io_10 = 0;
+		break;
+	case HALMAC_GPIO_FUNC_SW_IO_11:
+		info->sw_io_11 = 0;
+		break;
+	case HALMAC_GPIO_FUNC_SW_IO_12:
+		info->sw_io_12 = 0;
+		break;
+	case HALMAC_GPIO_FUNC_SW_IO_13:
+	case HALMAC_GPIO_FUNC_BT_DEV_WAKE1:
+		info->bt_dev_wake = 0;
+		info->sw_io_13 = 0;
+		break;
+	case HALMAC_GPIO_FUNC_SW_IO_14:
+	case HALMAC_GPIO_FUNC_BT_HOST_WAKE1:
+		info->bt_host_wake = 0;
+		info->sw_io_14 = 0;
+		break;
+	case HALMAC_GPIO_FUNC_SW_IO_15:
+		info->sw_io_15 = 0;
+		break;
+	default:
+		return HALMAC_RET_SWITCH_CASE_ERROR;
+	}
+
+	PLTFM_MSG_TRACE("[TRACE]func : %X\n", gpio_func);
+	PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
+
+	return HALMAC_RET_SUCCESS;
+}
+
+static enum halmac_ret_status
+get_pinmux_list_8821c(struct halmac_adapter *adapter,
+		      enum halmac_gpio_func gpio_func,
+		      const struct halmac_gpio_pimux_list **list,
+		      u32 *list_size, u32 *gpio_id)
+{
+	switch (gpio_func) {
+	case HALMAC_GPIO_FUNC_SW_IO_0:
+		*list = PINMUX_LIST_GPIO0_8821C;
+		*list_size = ARRAY_SIZE(PINMUX_LIST_GPIO0_8821C);
+		*gpio_id = HALMAC_GPIO0;
+		break;
+	case HALMAC_GPIO_FUNC_SW_IO_1:
+		*list = PINMUX_LIST_GPIO1_8821C;
+		*list_size = ARRAY_SIZE(PINMUX_LIST_GPIO1_8821C);
+		*gpio_id = HALMAC_GPIO1;
+		break;
+	case HALMAC_GPIO_FUNC_SW_IO_2:
+		*list = PINMUX_LIST_GPIO2_8821C;
+		*list_size = ARRAY_SIZE(PINMUX_LIST_GPIO2_8821C);
+		*gpio_id = HALMAC_GPIO2;
+		break;
+	case HALMAC_GPIO_FUNC_SW_IO_3:
+		*list = PINMUX_LIST_GPIO3_8821C;
+		*list_size = ARRAY_SIZE(PINMUX_LIST_GPIO3_8821C);
+		*gpio_id = HALMAC_GPIO3;
+		break;
+	case HALMAC_GPIO_FUNC_SW_IO_4:
+	case HALMAC_GPIO_FUNC_SDIO_INT:
+		*list = PINMUX_LIST_GPIO4_8821C;
+		*list_size = ARRAY_SIZE(PINMUX_LIST_GPIO4_8821C);
+		*gpio_id = HALMAC_GPIO4;
+		break;
+	case HALMAC_GPIO_FUNC_SW_IO_5:
+		*list = PINMUX_LIST_GPIO5_8821C;
+		*list_size = ARRAY_SIZE(PINMUX_LIST_GPIO5_8821C);
+		*gpio_id = HALMAC_GPIO5;
+		break;
+	case HALMAC_GPIO_FUNC_SW_IO_6:
+		*list = PINMUX_LIST_GPIO6_8821C;
+		*list_size = ARRAY_SIZE(PINMUX_LIST_GPIO6_8821C);
+		*gpio_id = HALMAC_GPIO6;
+		break;
+	case HALMAC_GPIO_FUNC_SW_IO_7:
+		*list = PINMUX_LIST_GPIO7_8821C;
+		*list_size = ARRAY_SIZE(PINMUX_LIST_GPIO7_8821C);
+		*gpio_id = HALMAC_GPIO7;
+		break;
+	case HALMAC_GPIO_FUNC_SW_IO_8:
+	case HALMAC_GPIO_FUNC_WL_LED:
+		*list = PINMUX_LIST_GPIO8_8821C;
+		*list_size = ARRAY_SIZE(PINMUX_LIST_GPIO8_8821C);
+		*gpio_id = HALMAC_GPIO8;
+		break;
+	case HALMAC_GPIO_FUNC_SW_IO_9:
+		*list = PINMUX_LIST_GPIO9_8821C;
+		*list_size = ARRAY_SIZE(PINMUX_LIST_GPIO9_8821C);
+		*gpio_id = HALMAC_GPIO9;
+		break;
+	case HALMAC_GPIO_FUNC_SW_IO_10:
+		*list = PINMUX_LIST_GPIO10_8821C;
+		*list_size = ARRAY_SIZE(PINMUX_LIST_GPIO10_8821C);
+		*gpio_id = HALMAC_GPIO10;
+		break;
+	case HALMAC_GPIO_FUNC_SW_IO_11:
+		*list = PINMUX_LIST_GPIO11_8821C;
+		*list_size = ARRAY_SIZE(PINMUX_LIST_GPIO11_8821C);
+		*gpio_id = HALMAC_GPIO11;
+		break;
+	case HALMAC_GPIO_FUNC_SW_IO_12:
+		*list = PINMUX_LIST_GPIO12_8821C;
+		*list_size = ARRAY_SIZE(PINMUX_LIST_GPIO12_8821C);
+		*gpio_id = HALMAC_GPIO12;
+		break;
+	case HALMAC_GPIO_FUNC_SW_IO_13:
+	case HALMAC_GPIO_FUNC_BT_DEV_WAKE1:
+		*list = PINMUX_LIST_GPIO13_8821C;
+		*list_size = ARRAY_SIZE(PINMUX_LIST_GPIO13_8821C);
+		*gpio_id = HALMAC_GPIO13;
+		break;
+	case HALMAC_GPIO_FUNC_SW_IO_14:
+	case HALMAC_GPIO_FUNC_BT_HOST_WAKE1:
+		*list = PINMUX_LIST_GPIO14_8821C;
+		*list_size = ARRAY_SIZE(PINMUX_LIST_GPIO14_8821C);
+		*gpio_id = HALMAC_GPIO14;
+		break;
+	case HALMAC_GPIO_FUNC_SW_IO_15:
+		*list = PINMUX_LIST_GPIO15_8821C;
+		*list_size = ARRAY_SIZE(PINMUX_LIST_GPIO15_8821C);
+		*gpio_id = HALMAC_GPIO15;
+		break;
+	default:
+		return HALMAC_RET_SWITCH_CASE_ERROR;
+	}
+
+	return HALMAC_RET_SUCCESS;
+}
+
+static enum halmac_ret_status
+chk_pinmux_valid_8821c(struct halmac_adapter *adapter,
+		       enum halmac_gpio_func gpio_func)
+{
+	struct halmac_pinmux_info *info = &adapter->pinmux_info;
+	enum halmac_ret_status status = HALMAC_RET_SUCCESS;
+
+	switch (gpio_func) {
+	case HALMAC_GPIO_FUNC_SW_IO_0:
+		if (info->sw_io_0 == 1)
+			status = HALMAC_RET_PINMUX_USED;
+		break;
+	case HALMAC_GPIO_FUNC_SW_IO_1:
+		if (info->sw_io_1 == 1)
+			status = HALMAC_RET_PINMUX_USED;
+		break;
+	case HALMAC_GPIO_FUNC_SW_IO_2:
+		if (info->sw_io_2 == 1)
+			status = HALMAC_RET_PINMUX_USED;
+		break;
+	case HALMAC_GPIO_FUNC_SW_IO_3:
+		if (info->sw_io_3 == 1)
+			status = HALMAC_RET_PINMUX_USED;
+		break;
+	case HALMAC_GPIO_FUNC_SW_IO_4:
+	case HALMAC_GPIO_FUNC_SDIO_INT:
+		if (info->sw_io_4 == 1 || info->sdio_int == 1)
+			status = HALMAC_RET_PINMUX_USED;
+		break;
+	case HALMAC_GPIO_FUNC_SW_IO_5:
+		if (info->sw_io_5 == 1)
+			status = HALMAC_RET_PINMUX_USED;
+		break;
+	case HALMAC_GPIO_FUNC_SW_IO_6:
+		if (info->sw_io_6 == 1)
+			status = HALMAC_RET_PINMUX_USED;
+		break;
+	case HALMAC_GPIO_FUNC_SW_IO_7:
+		if (info->sw_io_7 == 1)
+			status = HALMAC_RET_PINMUX_USED;
+		break;
+	case HALMAC_GPIO_FUNC_SW_IO_8:
+	case HALMAC_GPIO_FUNC_WL_LED:
+		if (info->sw_io_8 == 1 || info->wl_led == 1)
+			status = HALMAC_RET_PINMUX_USED;
+		break;
+	case HALMAC_GPIO_FUNC_SW_IO_9:
+		if (info->sw_io_9 == 1)
+			status = HALMAC_RET_PINMUX_USED;
+		break;
+	case HALMAC_GPIO_FUNC_SW_IO_10:
+		if (info->sw_io_10 == 1)
+			status = HALMAC_RET_PINMUX_USED;
+		break;
+	case HALMAC_GPIO_FUNC_SW_IO_11:
+		if (info->sw_io_11 == 1)
+			status = HALMAC_RET_PINMUX_USED;
+		break;
+	case HALMAC_GPIO_FUNC_SW_IO_12:
+		if (info->sw_io_12 == 1)
+			status = HALMAC_RET_PINMUX_USED;
+		break;
+	case HALMAC_GPIO_FUNC_SW_IO_13:
+	case HALMAC_GPIO_FUNC_BT_DEV_WAKE1:
+		if (info->sw_io_13 == 1 || info->bt_dev_wake == 1)
+			status = HALMAC_RET_PINMUX_USED;
+		break;
+	case HALMAC_GPIO_FUNC_SW_IO_14:
+	case HALMAC_GPIO_FUNC_BT_HOST_WAKE1:
+		if (info->sw_io_14 == 1 || info->bt_host_wake == 1)
+			status = HALMAC_RET_PINMUX_USED;
+		break;
+	case HALMAC_GPIO_FUNC_SW_IO_15:
+		if (info->sw_io_15 == 1)
+			status = HALMAC_RET_PINMUX_USED;
+		break;
+	default:
+		return HALMAC_RET_SWITCH_CASE_ERROR;
+	}
+
+	PLTFM_MSG_TRACE("[TRACE]chk_pinmux_valid func : %X status : %X\n",
+			gpio_func, status);
+
+	return status;
+}
+#endif /* HALMAC_8821C_SUPPORT */
+
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/halmac/halmac_88xx/halmac_8821c/halmac_gpio_8821c.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/halmac/halmac_88xx/halmac_8821c/halmac_gpio_8821c.h
--- linux-5.6.3/3rdparty/rtl8821ce/hal/halmac/halmac_88xx/halmac_8821c/halmac_gpio_8821c.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/halmac/halmac_88xx/halmac_8821c/halmac_gpio_8821c.h	2020-04-10 16:35:06.791658901 +0300
@@ -0,0 +1,37 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ ******************************************************************************/
+
+#ifndef _HALMAC_GPIO_8821C_H_
+#define _HALMAC_GPIO_8821C_H_
+
+#include "../../halmac_api.h"
+
+#if HALMAC_8821C_SUPPORT
+
+enum halmac_ret_status
+pinmux_get_func_8821c(struct halmac_adapter *adapter,
+		      enum halmac_gpio_func gpio_func, u8 *enable);
+
+enum halmac_ret_status
+pinmux_set_func_8821c(struct halmac_adapter *adapter,
+		      enum halmac_gpio_func gpio_func);
+
+enum halmac_ret_status
+pinmux_free_func_8821c(struct halmac_adapter *adapter,
+		       enum halmac_gpio_func gpio_func);
+
+#endif /* HALMAC_8821C_SUPPORT */
+
+#endif/* _HALMAC_GPIO_8821C_H_ */
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/halmac/halmac_88xx/halmac_8821c/halmac_init_8821c.c linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/halmac/halmac_88xx/halmac_8821c/halmac_init_8821c.c
--- linux-5.6.3/3rdparty/rtl8821ce/hal/halmac/halmac_88xx/halmac_8821c/halmac_init_8821c.c	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/halmac/halmac_88xx/halmac_8821c/halmac_init_8821c.c	2020-04-10 16:35:06.791658901 +0300
@@ -0,0 +1,890 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ ******************************************************************************/
+
+#include "halmac_init_8821c.h"
+#include "halmac_8821c_cfg.h"
+#if HALMAC_PCIE_SUPPORT
+#include "halmac_pcie_8821c.h"
+#endif
+#if HALMAC_SDIO_SUPPORT
+#include "halmac_sdio_8821c.h"
+#endif
+#if HALMAC_USB_SUPPORT
+#include "halmac_usb_8821c.h"
+#endif
+#include "halmac_gpio_8821c.h"
+#include "halmac_common_8821c.h"
+#include "halmac_cfg_wmac_8821c.h"
+#include "../halmac_common_88xx.h"
+#include "../halmac_init_88xx.h"
+
+#if HALMAC_8821C_SUPPORT
+
+#define RSVD_PG_DRV_NUM			16
+#define RSVD_PG_H2C_EXTRAINFO_NUM	24
+#define RSVD_PG_H2C_STATICINFO_NUM	8
+#define RSVD_PG_H2CQ_NUM		8
+#define RSVD_PG_CPU_INSTRUCTION_NUM	0
+#define RSVD_PG_FW_TXBUF_NUM		4
+#define RSVD_PG_CSIBUF_NUM		0
+#define RSVD_PG_DLLB_NUM		(TX_FIFO_SIZE_8821C / 3 >> \
+					TX_PAGE_SIZE_SHIFT_88XX)
+
+#define MAC_TRX_ENABLE	(BIT_HCI_TXDMA_EN | BIT_HCI_RXDMA_EN | BIT_TXDMA_EN | \
+			BIT_RXDMA_EN | BIT_PROTOCOL_EN | BIT_SCHEDULE_EN | \
+			BIT_MACTXEN | BIT_MACRXEN)
+
+#define BLK_DESC_NUM   0x3
+
+#define WLAN_SLOT_TIME		0x05
+#define WLAN_PIFS_TIME		0x19
+#define WLAN_SIFS_CCK_CONT_TX	0xA
+#define WLAN_SIFS_OFDM_CONT_TX	0xA
+#define WLAN_SIFS_CCK_TRX	0x10
+#define WLAN_SIFS_OFDM_TRX	0x10
+#define WLAN_VO_TXOP_LIMIT	0x186 /* unit : 32us */
+#define WLAN_VI_TXOP_LIMIT	0x3BC /* unit : 32us */
+#define WLAN_RDG_NAV		0x05
+#define WLAN_TXOP_NAV		0x1B
+#define WLAN_CCK_RX_TSF		0x30
+#define WLAN_OFDM_RX_TSF	0x30
+#define WLAN_TBTT_PROHIBIT	0x04 /* unit : 32us */
+#define WLAN_TBTT_HOLD_TIME	0x064 /* unit : 32us */
+#define WLAN_DRV_EARLY_INT	0x04
+#define WLAN_BCN_DMA_TIME	0x02
+#define WLAN_ACK_TO_CCK		0x40
+
+#define WLAN_RX_FILTER0		0x0FFFFFFF
+#define WLAN_RX_FILTER2		0xFFFF
+#define WLAN_RCR_CFG		0xE400220E
+#define WLAN_RXPKT_MAX_SZ	12288
+#define WLAN_RXPKT_MAX_SZ_512	(WLAN_RXPKT_MAX_SZ >> 9)
+
+#define WLAN_AMPDU_MAX_TIME		0x70
+#define WLAN_RTS_LEN_TH			0xFF
+#define WLAN_RTS_TX_TIME_TH		0x08
+#define WLAN_MAX_AGG_PKT_LIMIT		0x10
+#define WLAN_RTS_MAX_AGG_PKT_LIMIT	0x10
+#define WLAN_MAX_AGG_PKT_LIMIT_SDIO	0x2B
+#define WLAN_RTS_MAX_AGG_PKT_LIMIT_SDIO	0x2B
+#define WLAN_PRE_TXCNT_TIME_TH		0x1E4
+#define WALN_FAST_EDCA_VO_TH		0x06
+#define WLAN_FAST_EDCA_VI_TH		0x06
+#define WLAN_FAST_EDCA_BE_TH		0x06
+#define WLAN_FAST_EDCA_BK_TH		0x06
+#define WLAN_BAR_RETRY_LIMIT		0x01
+#define WLAN_RA_TRY_RATE_AGG_LIMIT	0x08
+
+#define WLAN_TX_FUNC_CFG1		0x30
+#define WLAN_TX_FUNC_CFG2		0x30
+#define WLAN_MAC_OPT_NORM_FUNC1		0x98
+#define WLAN_MAC_OPT_LB_FUNC1		0x80
+#define WLAN_MAC_OPT_FUNC2		0x30810041
+
+#define WLAN_SIFS_CFG	(WLAN_SIFS_CCK_CONT_TX | \
+			(WLAN_SIFS_OFDM_CONT_TX << BIT_SHIFT_SIFS_OFDM_CTX) | \
+			(WLAN_SIFS_CCK_TRX << BIT_SHIFT_SIFS_CCK_TRX) | \
+			(WLAN_SIFS_OFDM_TRX << BIT_SHIFT_SIFS_OFDM_TRX))
+
+#define WLAN_TBTT_TIME	(WLAN_TBTT_PROHIBIT |\
+			(WLAN_TBTT_HOLD_TIME << BIT_SHIFT_TBTT_HOLD_TIME_AP))
+
+#define WLAN_NAV_CFG		(WLAN_RDG_NAV | (WLAN_TXOP_NAV << 16))
+#define WLAN_RX_TSF_CFG		(WLAN_CCK_RX_TSF | (WLAN_OFDM_RX_TSF) << 8)
+
+#if HALMAC_PLATFORM_WINDOWS
+/*SDIO RQPN Mapping for Windows, extra queue is not implemented in Driver code*/
+static struct halmac_rqpn HALMAC_RQPN_SDIO_8821C[] = {
+	/* { mode, vo_map, vi_map, be_map, bk_map, mg_map, hi_map } */
+	{HALMAC_TRX_MODE_NORMAL,
+	 HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ, HALMAC_MAP2_LQ,
+	 HALMAC_MAP2_HQ, HALMAC_MAP2_HQ},
+	{HALMAC_TRX_MODE_TRXSHARE,
+	 HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ, HALMAC_MAP2_LQ,
+	 HALMAC_MAP2_HQ, HALMAC_MAP2_HQ},
+	{HALMAC_TRX_MODE_WMM,
+	 HALMAC_MAP2_HQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ, HALMAC_MAP2_NQ,
+	 HALMAC_MAP2_EXQ, HALMAC_MAP2_HQ},
+	{HALMAC_TRX_MODE_P2P,
+	 HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ, HALMAC_MAP2_LQ,
+	 HALMAC_MAP2_HQ, HALMAC_MAP2_HQ},
+	{HALMAC_TRX_MODE_LOOPBACK,
+	 HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ, HALMAC_MAP2_LQ,
+	 HALMAC_MAP2_HQ, HALMAC_MAP2_HQ},
+	{HALMAC_TRX_MODE_DELAY_LOOPBACK,
+	 HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ, HALMAC_MAP2_LQ,
+	 HALMAC_MAP2_HQ, HALMAC_MAP2_HQ},
+};
+#else
+/*SDIO RQPN Mapping*/
+static struct halmac_rqpn HALMAC_RQPN_SDIO_8821C[] = {
+	/* { mode, vo_map, vi_map, be_map, bk_map, mg_map, hi_map } */
+	{HALMAC_TRX_MODE_NORMAL,
+	 HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ, HALMAC_MAP2_LQ,
+	 HALMAC_MAP2_EXQ, HALMAC_MAP2_HQ},
+	{HALMAC_TRX_MODE_TRXSHARE,
+	 HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ, HALMAC_MAP2_LQ,
+	 HALMAC_MAP2_EXQ, HALMAC_MAP2_HQ},
+	{HALMAC_TRX_MODE_WMM,
+	 HALMAC_MAP2_HQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ, HALMAC_MAP2_NQ,
+	 HALMAC_MAP2_EXQ, HALMAC_MAP2_HQ},
+	{HALMAC_TRX_MODE_P2P,
+	 HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ, HALMAC_MAP2_LQ,
+	 HALMAC_MAP2_EXQ, HALMAC_MAP2_HQ},
+	{HALMAC_TRX_MODE_LOOPBACK,
+	 HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ, HALMAC_MAP2_LQ,
+	 HALMAC_MAP2_EXQ, HALMAC_MAP2_HQ},
+	{HALMAC_TRX_MODE_DELAY_LOOPBACK,
+	 HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ, HALMAC_MAP2_LQ,
+	 HALMAC_MAP2_EXQ, HALMAC_MAP2_HQ},
+};
+#endif
+
+/*PCIE RQPN Mapping*/
+static struct halmac_rqpn HALMAC_RQPN_PCIE_8821C[] = {
+	/* { mode, vo_map, vi_map, be_map, bk_map, mg_map, hi_map } */
+	{HALMAC_TRX_MODE_NORMAL,
+	 HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ, HALMAC_MAP2_LQ,
+	 HALMAC_MAP2_EXQ, HALMAC_MAP2_HQ},
+	{HALMAC_TRX_MODE_TRXSHARE,
+	 HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ, HALMAC_MAP2_LQ,
+	 HALMAC_MAP2_EXQ, HALMAC_MAP2_HQ},
+	{HALMAC_TRX_MODE_WMM,
+	 HALMAC_MAP2_HQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ, HALMAC_MAP2_NQ,
+	 HALMAC_MAP2_EXQ, HALMAC_MAP2_HQ},
+	{HALMAC_TRX_MODE_P2P,
+	 HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ, HALMAC_MAP2_LQ,
+	 HALMAC_MAP2_EXQ, HALMAC_MAP2_HQ},
+	{HALMAC_TRX_MODE_LOOPBACK,
+	 HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ, HALMAC_MAP2_LQ,
+	 HALMAC_MAP2_EXQ, HALMAC_MAP2_HQ},
+	{HALMAC_TRX_MODE_DELAY_LOOPBACK,
+	 HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ, HALMAC_MAP2_LQ,
+	 HALMAC_MAP2_EXQ, HALMAC_MAP2_HQ},
+};
+
+/*USB 2 Bulkout RQPN Mapping*/
+static struct halmac_rqpn HALMAC_RQPN_2BULKOUT_8821C[] = {
+	/* { mode, vo_map, vi_map, be_map, bk_map, mg_map, hi_map } */
+	{HALMAC_TRX_MODE_NORMAL,
+	 HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_HQ,
+	 HALMAC_MAP2_HQ, HALMAC_MAP2_HQ},
+	{HALMAC_TRX_MODE_TRXSHARE,
+	 HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_HQ,
+	 HALMAC_MAP2_HQ, HALMAC_MAP2_HQ},
+	{HALMAC_TRX_MODE_WMM,
+	 HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_HQ,
+	 HALMAC_MAP2_HQ, HALMAC_MAP2_HQ},
+	{HALMAC_TRX_MODE_P2P,
+	 HALMAC_MAP2_HQ, HALMAC_MAP2_HQ, HALMAC_MAP2_HQ, HALMAC_MAP2_NQ,
+	 HALMAC_MAP2_HQ, HALMAC_MAP2_HQ},
+	{HALMAC_TRX_MODE_LOOPBACK,
+	 HALMAC_MAP2_HQ, HALMAC_MAP2_HQ, HALMAC_MAP2_HQ, HALMAC_MAP2_NQ,
+	 HALMAC_MAP2_HQ, HALMAC_MAP2_HQ},
+	{HALMAC_TRX_MODE_DELAY_LOOPBACK,
+	 HALMAC_MAP2_HQ, HALMAC_MAP2_HQ, HALMAC_MAP2_HQ, HALMAC_MAP2_NQ,
+	 HALMAC_MAP2_HQ, HALMAC_MAP2_HQ},
+};
+
+/*USB 3 Bulkout RQPN Mapping*/
+static struct halmac_rqpn HALMAC_RQPN_3BULKOUT_8821C[] = {
+	/* { mode, vo_map, vi_map, be_map, bk_map, mg_map, hi_map } */
+	{HALMAC_TRX_MODE_NORMAL,
+	 HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ, HALMAC_MAP2_LQ,
+	 HALMAC_MAP2_HQ, HALMAC_MAP2_HQ},
+	{HALMAC_TRX_MODE_TRXSHARE,
+	 HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ, HALMAC_MAP2_LQ,
+	 HALMAC_MAP2_HQ, HALMAC_MAP2_HQ},
+	{HALMAC_TRX_MODE_WMM,
+	 HALMAC_MAP2_HQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ, HALMAC_MAP2_NQ,
+	 HALMAC_MAP2_HQ, HALMAC_MAP2_HQ},
+	{HALMAC_TRX_MODE_P2P,
+	 HALMAC_MAP2_HQ, HALMAC_MAP2_HQ, HALMAC_MAP2_LQ, HALMAC_MAP2_NQ,
+	 HALMAC_MAP2_HQ, HALMAC_MAP2_HQ},
+	{HALMAC_TRX_MODE_LOOPBACK,
+	 HALMAC_MAP2_HQ, HALMAC_MAP2_HQ, HALMAC_MAP2_LQ, HALMAC_MAP2_NQ,
+	 HALMAC_MAP2_HQ, HALMAC_MAP2_HQ},
+	{HALMAC_TRX_MODE_DELAY_LOOPBACK,
+	 HALMAC_MAP2_HQ, HALMAC_MAP2_HQ, HALMAC_MAP2_LQ, HALMAC_MAP2_NQ,
+	 HALMAC_MAP2_HQ, HALMAC_MAP2_HQ},
+};
+
+/*USB 4 Bulkout RQPN Mapping*/
+static struct halmac_rqpn HALMAC_RQPN_4BULKOUT_8821C[] = {
+	/* { mode, vo_map, vi_map, be_map, bk_map, mg_map, hi_map } */
+	{HALMAC_TRX_MODE_NORMAL,
+	 HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ, HALMAC_MAP2_LQ,
+	 HALMAC_MAP2_EXQ, HALMAC_MAP2_HQ},
+	{HALMAC_TRX_MODE_TRXSHARE,
+	 HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ, HALMAC_MAP2_LQ,
+	 HALMAC_MAP2_EXQ, HALMAC_MAP2_HQ},
+	{HALMAC_TRX_MODE_WMM,
+	 HALMAC_MAP2_HQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ, HALMAC_MAP2_NQ,
+	 HALMAC_MAP2_EXQ, HALMAC_MAP2_HQ},
+	{HALMAC_TRX_MODE_P2P,
+	 HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ, HALMAC_MAP2_LQ,
+	 HALMAC_MAP2_EXQ, HALMAC_MAP2_HQ},
+	{HALMAC_TRX_MODE_LOOPBACK,
+	 HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ, HALMAC_MAP2_LQ,
+	 HALMAC_MAP2_EXQ, HALMAC_MAP2_HQ},
+	{HALMAC_TRX_MODE_DELAY_LOOPBACK,
+	 HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ, HALMAC_MAP2_LQ,
+	 HALMAC_MAP2_EXQ, HALMAC_MAP2_HQ},
+};
+
+#if HALMAC_PLATFORM_WINDOWS
+/*SDIO Page Number*/
+static struct halmac_pg_num HALMAC_PG_NUM_SDIO_8821C[] = {
+	/* { mode, hq_num, nq_num, lq_num, exq_num, gap_num} */
+	{HALMAC_TRX_MODE_NORMAL, 16, 16, 16, 0, 1},
+	{HALMAC_TRX_MODE_TRXSHARE, 8, 8, 8, 0, 1},
+	{HALMAC_TRX_MODE_WMM, 16, 16, 16, 0, 1},
+	{HALMAC_TRX_MODE_P2P, 16, 16, 16, 0, 1},
+	{HALMAC_TRX_MODE_LOOPBACK, 16, 16, 16, 0, 1},
+	{HALMAC_TRX_MODE_DELAY_LOOPBACK, 16, 16, 16, 0, 1},
+};
+#else
+/*SDIO Page Number*/
+static struct halmac_pg_num HALMAC_PG_NUM_SDIO_8821C[] = {
+	/* { mode, hq_num, nq_num, lq_num, exq_num, gap_num} */
+	{HALMAC_TRX_MODE_NORMAL, 16, 16, 16, 14, 1},
+	{HALMAC_TRX_MODE_TRXSHARE, 8, 8, 8, 8, 1},
+	{HALMAC_TRX_MODE_WMM, 16, 16, 16, 14, 1},
+	{HALMAC_TRX_MODE_P2P, 16, 16, 16, 14, 1},
+	{HALMAC_TRX_MODE_LOOPBACK, 16, 16, 16, 14, 1},
+	{HALMAC_TRX_MODE_DELAY_LOOPBACK, 16, 16, 16, 14, 1},
+};
+#endif
+
+/*PCIE Page Number*/
+static struct halmac_pg_num HALMAC_PG_NUM_PCIE_8821C[] = {
+	/* { mode, hq_num, nq_num, lq_num, exq_num, gap_num} */
+	{HALMAC_TRX_MODE_NORMAL, 16, 16, 16, 14, 1},
+	{HALMAC_TRX_MODE_TRXSHARE, 16, 16, 16, 14, 1},
+	{HALMAC_TRX_MODE_WMM, 16, 16, 16, 14, 1},
+	{HALMAC_TRX_MODE_P2P, 16, 16, 16, 14, 1},
+	{HALMAC_TRX_MODE_LOOPBACK, 16, 16, 16, 14, 1},
+	{HALMAC_TRX_MODE_DELAY_LOOPBACK, 16, 16, 16, 14, 1},
+};
+
+/*USB 2 Bulkout Page Number*/
+static struct halmac_pg_num HALMAC_PG_NUM_2BULKOUT_8821C[] = {
+	/* { mode, hq_num, nq_num, lq_num, exq_num, gap_num} */
+	{HALMAC_TRX_MODE_NORMAL, 16, 16, 0, 0, 1},
+	{HALMAC_TRX_MODE_TRXSHARE, 16, 16, 0, 0, 1},
+	{HALMAC_TRX_MODE_WMM, 16, 16, 0, 0, 1},
+	{HALMAC_TRX_MODE_P2P, 16, 16, 0, 0, 1},
+	{HALMAC_TRX_MODE_LOOPBACK, 16, 16, 0, 0, 1},
+	{HALMAC_TRX_MODE_DELAY_LOOPBACK, 16, 16, 0, 0, 1},
+};
+
+/*USB 3 Bulkout Page Number*/
+static struct halmac_pg_num HALMAC_PG_NUM_3BULKOUT_8821C[] = {
+	/* { mode, hq_num, nq_num, lq_num, exq_num, gap_num} */
+	{HALMAC_TRX_MODE_NORMAL, 16, 16, 16, 0, 1},
+	{HALMAC_TRX_MODE_TRXSHARE, 16, 16, 16, 0, 1},
+	{HALMAC_TRX_MODE_WMM, 16, 16, 16, 0, 1},
+	{HALMAC_TRX_MODE_P2P, 16, 16, 16, 0, 1},
+	{HALMAC_TRX_MODE_LOOPBACK, 16, 16, 16, 0, 1},
+	{HALMAC_TRX_MODE_DELAY_LOOPBACK, 16, 16, 16, 0, 1},
+};
+
+/*USB 4 Bulkout Page Number*/
+static struct halmac_pg_num HALMAC_PG_NUM_4BULKOUT_8821C[] = {
+	/* { mode, hq_num, nq_num, lq_num, exq_num, gap_num} */
+	{HALMAC_TRX_MODE_NORMAL, 16, 16, 16, 14, 1},
+	{HALMAC_TRX_MODE_TRXSHARE, 16, 16, 16, 14, 1},
+	{HALMAC_TRX_MODE_WMM, 16, 16, 16, 14, 1},
+	{HALMAC_TRX_MODE_P2P, 16, 16, 16, 14, 1},
+	{HALMAC_TRX_MODE_LOOPBACK, 16, 16, 16, 14, 1},
+	{HALMAC_TRX_MODE_DELAY_LOOPBACK, 16, 16, 16, 14, 1},
+};
+
+static enum halmac_ret_status
+txdma_queue_mapping_8821c(struct halmac_adapter *adapter,
+			  enum halmac_trx_mode mode);
+
+static enum halmac_ret_status
+priority_queue_cfg_8821c(struct halmac_adapter *adapter,
+			 enum halmac_trx_mode mode);
+
+static enum halmac_ret_status
+set_trx_fifo_info_8821c(struct halmac_adapter *adapter,
+			enum halmac_trx_mode mode);
+
+enum halmac_ret_status
+mount_api_8821c(struct halmac_adapter *adapter)
+{
+	struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
+
+	adapter->chip_id = HALMAC_CHIP_ID_8821C;
+	adapter->hw_cfg_info.efuse_size = EFUSE_SIZE_8821C;
+	adapter->hw_cfg_info.eeprom_size = EEPROM_SIZE_8821C;
+	adapter->hw_cfg_info.bt_efuse_size = BT_EFUSE_SIZE_8821C;
+	adapter->hw_cfg_info.cam_entry_num = SEC_CAM_NUM_8821C;
+	adapter->hw_cfg_info.tx_fifo_size = TX_FIFO_SIZE_8821C;
+	adapter->hw_cfg_info.rx_fifo_size = RX_FIFO_SIZE_8821C;
+	adapter->hw_cfg_info.ac_oqt_size = OQT_ENTRY_AC_8821C;
+	adapter->hw_cfg_info.non_ac_oqt_size = OQT_ENTRY_NOAC_8821C;
+	adapter->hw_cfg_info.usb_txagg_num = BLK_DESC_NUM;
+	adapter->txff_alloc.rsvd_drv_pg_num = RSVD_PG_DRV_NUM;
+
+	api->halmac_init_trx_cfg = init_trx_cfg_8821c;
+	api->halmac_init_protocol_cfg = init_protocol_cfg_8821c;
+	api->halmac_init_h2c = init_h2c_8821c;
+	api->halmac_pinmux_get_func = pinmux_get_func_8821c;
+	api->halmac_pinmux_set_func = pinmux_set_func_8821c;
+	api->halmac_pinmux_free_func = pinmux_free_func_8821c;
+	api->halmac_get_hw_value = get_hw_value_8821c;
+	api->halmac_set_hw_value = set_hw_value_8821c;
+	api->halmac_cfg_drv_info = cfg_drv_info_8821c;
+	api->halmac_fill_txdesc_checksum = fill_txdesc_check_sum_8821c;
+	api->halmac_init_low_pwr = init_low_pwr_8821c;
+
+	api->halmac_init_wmac_cfg = init_wmac_cfg_8821c;
+	api->halmac_init_edca_cfg = init_edca_cfg_8821c;
+
+	if (adapter->intf == HALMAC_INTERFACE_SDIO) {
+#if HALMAC_SDIO_SUPPORT
+		api->halmac_mac_power_switch = mac_pwr_switch_sdio_8821c;
+		api->halmac_phy_cfg = phy_cfg_sdio_8821c;
+		api->halmac_pcie_switch = pcie_switch_sdio_8821c;
+		api->halmac_interface_integration_tuning = intf_tun_sdio_8821c;
+		api->halmac_tx_allowed_sdio = tx_allowed_sdio_8821c;
+		api->halmac_get_sdio_tx_addr = get_sdio_tx_addr_8821c;
+		api->halmac_reg_read_8 = reg_r8_sdio_8821c;
+		api->halmac_reg_write_8 = reg_w8_sdio_8821c;
+		api->halmac_reg_read_16 = reg_r16_sdio_8821c;
+		api->halmac_reg_write_16 = reg_w16_sdio_8821c;
+		api->halmac_reg_read_32 = reg_r32_sdio_8821c;
+		api->halmac_reg_write_32 = reg_w32_sdio_8821c;
+
+		adapter->sdio_fs.macid_map_size = MACID_MAX_8821C * 2;
+		if (!adapter->sdio_fs.macid_map) {
+			adapter->sdio_fs.macid_map =
+			(u8 *)PLTFM_MALLOC(adapter->sdio_fs.macid_map_size);
+			if (!adapter->sdio_fs.macid_map)
+				PLTFM_MSG_ERR("[ERR]mac id map malloc!!\n");
+		}
+#endif
+	} else if (adapter->intf == HALMAC_INTERFACE_USB) {
+#if HALMAC_USB_SUPPORT
+		api->halmac_mac_power_switch = mac_pwr_switch_usb_8821c;
+		api->halmac_phy_cfg = phy_cfg_usb_8821c;
+		api->halmac_pcie_switch = pcie_switch_usb_8821c;
+		api->halmac_interface_integration_tuning = intf_tun_usb_8821c;
+#endif
+	} else if (adapter->intf == HALMAC_INTERFACE_PCIE) {
+#if HALMAC_PCIE_SUPPORT
+		api->halmac_mac_power_switch = mac_pwr_switch_pcie_8821c;
+		api->halmac_phy_cfg = phy_cfg_pcie_8821c;
+		api->halmac_pcie_switch = pcie_switch_8821c;
+		api->halmac_interface_integration_tuning = intf_tun_pcie_8821c;
+#endif
+	} else {
+		PLTFM_MSG_ERR("[ERR]Undefined IC\n");
+		return HALMAC_RET_CHIP_NOT_SUPPORT;
+	}
+
+	return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * init_trx_cfg_8821c() - config trx dma register
+ * @adapter : the adapter of halmac
+ * @mode : trx mode selection
+ * Author : KaiYuan Chang/Ivan Lin
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+init_trx_cfg_8821c(struct halmac_adapter *adapter, enum halmac_trx_mode mode)
+{
+	u8 value8;
+	struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
+	enum halmac_ret_status status = HALMAC_RET_SUCCESS;
+
+	PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
+
+	adapter->trx_mode = mode;
+
+	status = txdma_queue_mapping_8821c(adapter, mode);
+	if (status != HALMAC_RET_SUCCESS) {
+		PLTFM_MSG_ERR("[ERR]queue mapping\n");
+		return status;
+	}
+
+	value8 = 0;
+	HALMAC_REG_W8(REG_CR, value8);
+	value8 = MAC_TRX_ENABLE;
+	HALMAC_REG_W8(REG_CR, value8);
+	HALMAC_REG_W32(REG_H2CQ_CSR, BIT(31));
+
+	status = priority_queue_cfg_8821c(adapter, mode);
+	if (status != HALMAC_RET_SUCCESS) {
+		PLTFM_MSG_ERR("[ERR]priority queue cfg\n");
+		return status;
+	}
+
+	if (adapter->txff_alloc.rx_fifo_exp_mode !=
+	    HALMAC_RX_FIFO_EXPANDING_MODE_DISABLE)
+		HALMAC_REG_W8(REG_RX_DRVINFO_SZ, RX_DESC_DUMMY_SIZE_8821C >> 3);
+
+	status = init_h2c_8821c(adapter);
+	if (status != HALMAC_RET_SUCCESS) {
+		PLTFM_MSG_ERR("[ERR]init h2cq!\n");
+		return status;
+	}
+
+	PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
+
+	return HALMAC_RET_SUCCESS;
+}
+
+static enum halmac_ret_status
+txdma_queue_mapping_8821c(struct halmac_adapter *adapter,
+			  enum halmac_trx_mode mode)
+{
+	u16 value16;
+	struct halmac_rqpn *cur_rqpn_sel = NULL;
+	enum halmac_ret_status status;
+	struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
+
+	if (adapter->intf == HALMAC_INTERFACE_SDIO) {
+		cur_rqpn_sel = HALMAC_RQPN_SDIO_8821C;
+	} else if (adapter->intf == HALMAC_INTERFACE_PCIE) {
+		cur_rqpn_sel = HALMAC_RQPN_PCIE_8821C;
+	} else if (adapter->intf == HALMAC_INTERFACE_USB) {
+		if (adapter->bulkout_num == 2) {
+			cur_rqpn_sel = HALMAC_RQPN_2BULKOUT_8821C;
+		} else if (adapter->bulkout_num == 3) {
+			cur_rqpn_sel = HALMAC_RQPN_3BULKOUT_8821C;
+		} else if (adapter->bulkout_num == 4) {
+			cur_rqpn_sel = HALMAC_RQPN_4BULKOUT_8821C;
+		} else {
+			PLTFM_MSG_ERR("[ERR]invalid intf\n");
+			return HALMAC_RET_NOT_SUPPORT;
+		}
+	} else {
+		return HALMAC_RET_NOT_SUPPORT;
+	}
+
+	status = rqpn_parser_88xx(adapter, mode, cur_rqpn_sel);
+	if (status != HALMAC_RET_SUCCESS)
+		return status;
+
+	value16 = 0;
+	value16 |= BIT_TXDMA_HIQ_MAP(adapter->pq_map[HALMAC_PQ_MAP_HI]);
+	value16 |= BIT_TXDMA_MGQ_MAP(adapter->pq_map[HALMAC_PQ_MAP_MG]);
+	value16 |= BIT_TXDMA_BKQ_MAP(adapter->pq_map[HALMAC_PQ_MAP_BK]);
+	value16 |= BIT_TXDMA_BEQ_MAP(adapter->pq_map[HALMAC_PQ_MAP_BE]);
+	value16 |= BIT_TXDMA_VIQ_MAP(adapter->pq_map[HALMAC_PQ_MAP_VI]);
+	value16 |= BIT_TXDMA_VOQ_MAP(adapter->pq_map[HALMAC_PQ_MAP_VO]);
+	HALMAC_REG_W16(REG_TXDMA_PQ_MAP, value16);
+
+	return HALMAC_RET_SUCCESS;
+}
+
+static enum halmac_ret_status
+priority_queue_cfg_8821c(struct halmac_adapter *adapter,
+			 enum halmac_trx_mode mode)
+{
+	u8 transfer_mode = 0;
+	u8 value8;
+	u32 cnt;
+	struct halmac_txff_allocation *txff_info = &adapter->txff_alloc;
+	enum halmac_ret_status status;
+	struct halmac_pg_num *cur_pg_num = NULL;
+	struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
+
+	status = set_trx_fifo_info_8821c(adapter, mode);
+	if (status != HALMAC_RET_SUCCESS) {
+		PLTFM_MSG_ERR("[ERR]set trx fifo!!\n");
+		return status;
+	}
+
+	if (adapter->intf == HALMAC_INTERFACE_SDIO) {
+		cur_pg_num = HALMAC_PG_NUM_SDIO_8821C;
+	} else if (adapter->intf == HALMAC_INTERFACE_PCIE) {
+		cur_pg_num = HALMAC_PG_NUM_PCIE_8821C;
+	} else if (adapter->intf == HALMAC_INTERFACE_USB) {
+		if (adapter->bulkout_num == 2) {
+			cur_pg_num = HALMAC_PG_NUM_2BULKOUT_8821C;
+		} else if (adapter->bulkout_num == 3) {
+			cur_pg_num = HALMAC_PG_NUM_3BULKOUT_8821C;
+		} else if (adapter->bulkout_num == 4) {
+			cur_pg_num = HALMAC_PG_NUM_4BULKOUT_8821C;
+		} else {
+			PLTFM_MSG_ERR("[ERR]invalid intf\n");
+			return HALMAC_RET_NOT_SUPPORT;
+		}
+	} else {
+		return HALMAC_RET_NOT_SUPPORT;
+	}
+
+	status = pg_num_parser_88xx(adapter, mode, cur_pg_num);
+	if (status != HALMAC_RET_SUCCESS)
+		return status;
+
+	PLTFM_MSG_TRACE("[TRACE]Set FIFO page\n");
+
+	HALMAC_REG_W16(REG_FIFOPAGE_INFO_1, txff_info->high_queue_pg_num);
+	HALMAC_REG_W16(REG_FIFOPAGE_INFO_2, txff_info->low_queue_pg_num);
+	HALMAC_REG_W16(REG_FIFOPAGE_INFO_3, txff_info->normal_queue_pg_num);
+	HALMAC_REG_W16(REG_FIFOPAGE_INFO_4, txff_info->extra_queue_pg_num);
+	HALMAC_REG_W16(REG_FIFOPAGE_INFO_5, txff_info->pub_queue_pg_num);
+	HALMAC_REG_W32_SET(REG_RQPN_CTRL_2, BIT(31));
+
+	adapter->sdio_fs.hiq_pg_num = txff_info->high_queue_pg_num;
+	adapter->sdio_fs.miq_pg_num = txff_info->normal_queue_pg_num;
+	adapter->sdio_fs.lowq_pg_num = txff_info->low_queue_pg_num;
+	adapter->sdio_fs.pubq_pg_num = txff_info->pub_queue_pg_num;
+	adapter->sdio_fs.exq_pg_num = txff_info->extra_queue_pg_num;
+
+	HALMAC_REG_W16(REG_FIFOPAGE_CTRL_2, txff_info->rsvd_boundary);
+	HALMAC_REG_W8_SET(REG_FWHW_TXQ_CTRL + 2, BIT(4));
+
+	/*20170411 Soar*/
+	/* SDIO sometimes use two CMD52 to do HALMAC_REG_W16 */
+	/* and may cause a mismatch between HW status and Reg value. */
+	/* A patch is to write high byte first, suggested by Argis */
+	if (adapter->intf == HALMAC_INTERFACE_SDIO) {
+		value8 = (u8)(txff_info->rsvd_boundary >> 8 & 0xFF);
+		HALMAC_REG_W8(REG_BCNQ_BDNY_V1 + 1, value8);
+		value8 = (u8)(txff_info->rsvd_boundary & 0xFF);
+		HALMAC_REG_W8(REG_BCNQ_BDNY_V1, value8);
+	} else {
+		HALMAC_REG_W16(REG_BCNQ_BDNY_V1, txff_info->rsvd_boundary);
+	}
+
+	HALMAC_REG_W16(REG_FIFOPAGE_CTRL_2 + 2, txff_info->rsvd_boundary);
+
+	/*20170411 Soar*/
+	/* SDIO sometimes use two CMD52 to do HALMAC_REG_W16 */
+	/* and may cause a mismatch between HW status and Reg value. */
+	/* A patch is to write high byte first, suggested by Argis */
+	if (adapter->intf == HALMAC_INTERFACE_SDIO) {
+		value8 = (u8)(txff_info->rsvd_boundary >> 8 & 0xFF);
+		HALMAC_REG_W8(REG_BCNQ1_BDNY_V1 + 1, value8);
+		value8 = (u8)(txff_info->rsvd_boundary & 0xFF);
+		HALMAC_REG_W8(REG_BCNQ1_BDNY_V1, value8);
+	} else {
+		HALMAC_REG_W16(REG_BCNQ1_BDNY_V1, txff_info->rsvd_boundary);
+	}
+
+	HALMAC_REG_W32(REG_RXFF_BNDY,
+		       adapter->hw_cfg_info.rx_fifo_size -
+		       C2H_PKT_BUF_88XX - 1);
+
+	if (adapter->intf == HALMAC_INTERFACE_USB) {
+		value8 = HALMAC_REG_R8(REG_AUTO_LLT_V1);
+		value8 &= ~(BIT_MASK_BLK_DESC_NUM << BIT_SHIFT_BLK_DESC_NUM);
+		value8 |= (BLK_DESC_NUM << BIT_SHIFT_BLK_DESC_NUM);
+		HALMAC_REG_W8(REG_AUTO_LLT_V1, value8);
+
+		HALMAC_REG_W8(REG_AUTO_LLT_V1 + 3, BLK_DESC_NUM);
+		HALMAC_REG_W8_SET(REG_TXDMA_OFFSET_CHK + 1, BIT(1));
+	}
+
+	HALMAC_REG_W8_SET(REG_AUTO_LLT_V1, BIT_AUTO_INIT_LLT_V1);
+	cnt = 1000;
+	while (HALMAC_REG_R8(REG_AUTO_LLT_V1) & BIT_AUTO_INIT_LLT_V1) {
+		cnt--;
+		if (cnt == 0)
+			return HALMAC_RET_INIT_LLT_FAIL;
+	}
+
+	if (mode == HALMAC_TRX_MODE_DELAY_LOOPBACK) {
+		transfer_mode = HALMAC_TRNSFER_LOOPBACK_DELAY;
+		HALMAC_REG_W16(REG_WMAC_LBK_BUF_HD_V1,
+			       adapter->txff_alloc.rsvd_boundary);
+	} else if (mode == HALMAC_TRX_MODE_LOOPBACK) {
+		transfer_mode = HALMAC_TRNSFER_LOOPBACK_DIRECT;
+	} else {
+		transfer_mode = HALMAC_TRNSFER_NORMAL;
+	}
+
+	adapter->hw_cfg_info.trx_mode = transfer_mode;
+	HALMAC_REG_W8(REG_CR + 3, (u8)transfer_mode);
+
+	return HALMAC_RET_SUCCESS;
+}
+
+static enum halmac_ret_status
+set_trx_fifo_info_8821c(struct halmac_adapter *adapter,
+			enum halmac_trx_mode mode)
+{
+	u16 cur_pg_addr;
+	u32 txff_size = TX_FIFO_SIZE_8821C;
+	u32 rxff_size = RX_FIFO_SIZE_8821C;
+	struct halmac_txff_allocation *info = &adapter->txff_alloc;
+
+	if (info->rx_fifo_exp_mode == HALMAC_RX_FIFO_EXPANDING_MODE_1_BLOCK) {
+		txff_size = TX_FIFO_SIZE_RX_EXPAND_1BLK_8821C;
+		rxff_size = RX_FIFO_SIZE_RX_EXPAND_1BLK_8821C;
+	}
+
+	if (info->la_mode != HALMAC_LA_MODE_DISABLE) {
+		txff_size = TX_FIFO_SIZE_LA_8821C;
+		rxff_size = RX_FIFO_SIZE_8821C;
+	}
+
+	adapter->hw_cfg_info.tx_fifo_size = txff_size;
+	adapter->hw_cfg_info.rx_fifo_size = rxff_size;
+	info->tx_fifo_pg_num = (u16)(txff_size >> TX_PAGE_SIZE_SHIFT_88XX);
+
+	info->rsvd_pg_num = info->rsvd_drv_pg_num +
+					RSVD_PG_H2C_EXTRAINFO_NUM +
+					RSVD_PG_H2C_STATICINFO_NUM +
+					RSVD_PG_H2CQ_NUM +
+					RSVD_PG_CPU_INSTRUCTION_NUM +
+					RSVD_PG_FW_TXBUF_NUM +
+					RSVD_PG_CSIBUF_NUM;
+
+	if (mode == HALMAC_TRX_MODE_DELAY_LOOPBACK)
+		info->rsvd_pg_num += RSVD_PG_DLLB_NUM;
+
+	if (info->rsvd_pg_num > info->tx_fifo_pg_num)
+		return HALMAC_RET_CFG_TXFIFO_PAGE_FAIL;
+
+	info->acq_pg_num = info->tx_fifo_pg_num - info->rsvd_pg_num;
+	info->rsvd_boundary = info->tx_fifo_pg_num - info->rsvd_pg_num;
+
+	cur_pg_addr = info->tx_fifo_pg_num;
+	cur_pg_addr -= RSVD_PG_CSIBUF_NUM;
+	info->rsvd_csibuf_addr = cur_pg_addr;
+	cur_pg_addr -= RSVD_PG_FW_TXBUF_NUM;
+	info->rsvd_fw_txbuf_addr = cur_pg_addr;
+	cur_pg_addr -= RSVD_PG_CPU_INSTRUCTION_NUM;
+	info->rsvd_cpu_instr_addr = cur_pg_addr;
+	cur_pg_addr -= RSVD_PG_H2CQ_NUM;
+	info->rsvd_h2cq_addr = cur_pg_addr;
+	cur_pg_addr -= RSVD_PG_H2C_STATICINFO_NUM;
+	info->rsvd_h2c_sta_info_addr = cur_pg_addr;
+	cur_pg_addr -= RSVD_PG_H2C_EXTRAINFO_NUM;
+	info->rsvd_h2c_info_addr = cur_pg_addr;
+	cur_pg_addr -= info->rsvd_drv_pg_num;
+	info->rsvd_drv_addr = cur_pg_addr;
+
+	if (mode == HALMAC_TRX_MODE_DELAY_LOOPBACK)
+		info->rsvd_drv_addr -= RSVD_PG_DLLB_NUM;
+
+	if (info->rsvd_boundary != info->rsvd_drv_addr)
+		return HALMAC_RET_CFG_TXFIFO_PAGE_FAIL;
+
+	return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * init_protocol_cfg_8821c() - config protocol register
+ * @adapter : the adapter of halmac
+ * Author : KaiYuan Chang/Ivan Lin
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+init_protocol_cfg_8821c(struct halmac_adapter *adapter)
+{
+	u16 pre_txcnt;
+	u32 max_agg_num;
+	u32 max_rts_agg_num;
+	u32 value32;
+	struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
+
+	PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
+
+	HALMAC_REG_W8(REG_AMPDU_MAX_TIME_V1, WLAN_AMPDU_MAX_TIME);
+	HALMAC_REG_W8_SET(REG_TX_HANG_CTRL, BIT_EN_EOF_V1);
+
+	pre_txcnt = WLAN_PRE_TXCNT_TIME_TH | BIT_EN_PRECNT;
+	HALMAC_REG_W8(REG_PRECNT_CTRL, (u8)(pre_txcnt & 0xFF));
+	HALMAC_REG_W8(REG_PRECNT_CTRL + 1, (u8)(pre_txcnt >> 8));
+
+	max_agg_num = WLAN_MAX_AGG_PKT_LIMIT;
+	max_rts_agg_num = WLAN_RTS_MAX_AGG_PKT_LIMIT;
+
+	if (adapter->intf == HALMAC_INTERFACE_SDIO) {
+		max_agg_num = WLAN_MAX_AGG_PKT_LIMIT_SDIO;
+		max_rts_agg_num = WLAN_RTS_MAX_AGG_PKT_LIMIT_SDIO;
+	}
+
+	value32 = WLAN_RTS_LEN_TH | (WLAN_RTS_TX_TIME_TH << 8) |
+				(max_agg_num << 16) | (max_rts_agg_num << 24);
+	HALMAC_REG_W32(REG_PROT_MODE_CTRL, value32);
+
+	HALMAC_REG_W16(REG_BAR_MODE_CTRL + 2,
+		       WLAN_BAR_RETRY_LIMIT | WLAN_RA_TRY_RATE_AGG_LIMIT << 8);
+
+	HALMAC_REG_W8(REG_FAST_EDCA_VOVI_SETTING, WALN_FAST_EDCA_VO_TH);
+	HALMAC_REG_W8(REG_FAST_EDCA_VOVI_SETTING + 2, WLAN_FAST_EDCA_VI_TH);
+	HALMAC_REG_W8(REG_FAST_EDCA_BEBK_SETTING, WLAN_FAST_EDCA_BE_TH);
+	HALMAC_REG_W8(REG_FAST_EDCA_BEBK_SETTING + 2, WLAN_FAST_EDCA_BK_TH);
+
+	PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
+
+	return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * init_h2c_8821c() - config h2c packet buffer
+ * @adapter : the adapter of halmac
+ * Author : KaiYuan Chang/Ivan Lin
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+init_h2c_8821c(struct halmac_adapter *adapter)
+{
+	u8 value8;
+	u32 value32;
+	u32 h2cq_addr;
+	u32 h2cq_size;
+	struct halmac_txff_allocation *txff_info = &adapter->txff_alloc;
+	struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
+
+	h2cq_addr = txff_info->rsvd_h2cq_addr << TX_PAGE_SIZE_SHIFT_88XX;
+	h2cq_size = RSVD_PG_H2CQ_NUM << TX_PAGE_SIZE_SHIFT_88XX;
+
+	value32 = HALMAC_REG_R32(REG_H2C_HEAD);
+	value32 = (value32 & 0xFFFC0000) | h2cq_addr;
+	HALMAC_REG_W32(REG_H2C_HEAD, value32);
+
+	value32 = HALMAC_REG_R32(REG_H2C_READ_ADDR);
+	value32 = (value32 & 0xFFFC0000) | h2cq_addr;
+	HALMAC_REG_W32(REG_H2C_READ_ADDR, value32);
+
+	value32 = HALMAC_REG_R32(REG_H2C_TAIL);
+	value32 &= 0xFFFC0000;
+	value32 |= (h2cq_addr + h2cq_size);
+	HALMAC_REG_W32(REG_H2C_TAIL, value32);
+
+	value8 = HALMAC_REG_R8(REG_H2C_INFO);
+	value8 = (u8)((value8 & 0xFC) | 0x01);
+	HALMAC_REG_W8(REG_H2C_INFO, value8);
+
+	value8 = HALMAC_REG_R8(REG_H2C_INFO);
+	value8 = (u8)((value8 & 0xFB) | 0x04);
+	HALMAC_REG_W8(REG_H2C_INFO, value8);
+
+	value8 = HALMAC_REG_R8(REG_TXDMA_OFFSET_CHK + 1);
+	value8 = (u8)((value8 & 0x7f) | 0x80);
+	HALMAC_REG_W8(REG_TXDMA_OFFSET_CHK + 1, value8);
+
+	adapter->h2c_info.buf_size = h2cq_size;
+	get_h2c_buf_free_space_88xx(adapter);
+
+	if (adapter->h2c_info.buf_size != adapter->h2c_info.buf_fs) {
+		PLTFM_MSG_ERR("[ERR]get h2c free space error!\n");
+		return HALMAC_RET_GET_H2C_SPACE_ERR;
+	}
+
+	PLTFM_MSG_TRACE("[TRACE]h2c fs : %d\n", adapter->h2c_info.buf_fs);
+
+	return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * init_edca_cfg_8821c() - init EDCA config
+ * @adapter : the adapter of halmac
+ * Author : KaiYuan Chang/Ivan Lin
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+init_edca_cfg_8821c(struct halmac_adapter *adapter)
+{
+	struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
+
+	PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
+
+	/* Init SYNC_CLI_SEL : reg 0x5B4[6:4] = 0 */
+	HALMAC_REG_W8_CLR(REG_TIMER0_SRC_SEL, BIT(4) | BIT(5) | BIT(6));
+
+	/* Clear TX pause */
+	HALMAC_REG_W16(REG_TXPAUSE, 0x0000);
+
+	HALMAC_REG_W8(REG_SLOT, WLAN_SLOT_TIME);
+	HALMAC_REG_W8(REG_PIFS, WLAN_PIFS_TIME);
+	HALMAC_REG_W32(REG_SIFS, WLAN_SIFS_CFG);
+
+	HALMAC_REG_W16(REG_EDCA_VO_PARAM + 2, WLAN_VO_TXOP_LIMIT);
+	HALMAC_REG_W16(REG_EDCA_VI_PARAM + 2, WLAN_VI_TXOP_LIMIT);
+
+	HALMAC_REG_W32(REG_RD_NAV_NXT, WLAN_NAV_CFG);
+	HALMAC_REG_W16(REG_RXTSF_OFFSET_CCK, WLAN_RX_TSF_CFG);
+
+	/* Set beacon cotnrol - enable TSF and other related functions */
+	HALMAC_REG_W8(REG_BCN_CTRL, (u8)(HALMAC_REG_R8(REG_BCN_CTRL) |
+					  BIT_EN_BCN_FUNCTION));
+
+	/* Set send beacon related registers */
+	HALMAC_REG_W32(REG_TBTT_PROHIBIT, WLAN_TBTT_TIME);
+	HALMAC_REG_W8(REG_DRVERLYINT, WLAN_DRV_EARLY_INT);
+	HALMAC_REG_W8(REG_BCNDMATIM, WLAN_BCN_DMA_TIME);
+
+	HALMAC_REG_W8_CLR(REG_TX_PTCL_CTRL + 1, BIT(4));
+
+	PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
+
+	return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * init_wmac_cfg_8821c() - init wmac config
+ * @adapter : the adapter of halmac
+ * Author : KaiYuan Chang/Ivan Lin
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+init_wmac_cfg_8821c(struct halmac_adapter *adapter)
+{
+	u8 value8;
+	struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
+	enum halmac_ret_status status = HALMAC_RET_SUCCESS;
+
+	PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
+
+	HALMAC_REG_W32(REG_RXFLTMAP0, WLAN_RX_FILTER0);
+	HALMAC_REG_W16(REG_RXFLTMAP2, WLAN_RX_FILTER2);
+
+	HALMAC_REG_W32(REG_RCR, WLAN_RCR_CFG);
+
+	HALMAC_REG_W8(REG_RX_PKT_LIMIT, WLAN_RXPKT_MAX_SZ_512);
+
+	HALMAC_REG_W8(REG_TCR + 2, WLAN_TX_FUNC_CFG2);
+	HALMAC_REG_W8(REG_TCR + 1, WLAN_TX_FUNC_CFG1);
+
+	HALMAC_REG_W8(REG_ACKTO_CCK, WLAN_ACK_TO_CCK);
+
+	HALMAC_REG_W32(REG_WMAC_OPTION_FUNCTION + 8, WLAN_MAC_OPT_FUNC2);
+
+	if (adapter->hw_cfg_info.trx_mode == HALMAC_TRNSFER_NORMAL)
+		value8 = WLAN_MAC_OPT_NORM_FUNC1;
+	else
+		value8 = WLAN_MAC_OPT_LB_FUNC1;
+
+	HALMAC_REG_W8(REG_WMAC_OPTION_FUNCTION + 4, value8);
+
+	status = api->halmac_init_low_pwr(adapter);
+	if (status != HALMAC_RET_SUCCESS)
+		return status;
+
+	PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
+
+	return HALMAC_RET_SUCCESS;
+}
+
+#endif /* HALMAC_8821C_SUPPORT */
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/halmac/halmac_88xx/halmac_8821c/halmac_init_8821c.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/halmac/halmac_88xx/halmac_8821c/halmac_init_8821c.h
--- linux-5.6.3/3rdparty/rtl8821ce/hal/halmac/halmac_88xx/halmac_8821c/halmac_init_8821c.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/halmac/halmac_88xx/halmac_8821c/halmac_init_8821c.h	2020-04-10 16:35:06.791658901 +0300
@@ -0,0 +1,43 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ ******************************************************************************/
+
+#ifndef _HALMAC_INIT_8821C_H_
+#define _HALMAC_INIT_8821C_H_
+
+#include "../../halmac_api.h"
+
+#if HALMAC_8821C_SUPPORT
+
+enum halmac_ret_status
+mount_api_8821c(struct halmac_adapter *adapter);
+
+enum halmac_ret_status
+init_trx_cfg_8821c(struct halmac_adapter *adapter, enum halmac_trx_mode mode);
+
+enum halmac_ret_status
+init_protocol_cfg_8821c(struct halmac_adapter *adapter);
+
+enum halmac_ret_status
+init_h2c_8821c(struct halmac_adapter *adapter);
+
+enum halmac_ret_status
+init_edca_cfg_8821c(struct halmac_adapter *adapter);
+
+enum halmac_ret_status
+init_wmac_cfg_8821c(struct halmac_adapter *adapter);
+
+#endif /* HALMAC_8821C_SUPPORT */
+
+#endif/* _HALMAC_INIT_8821C_H_ */
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/halmac/halmac_88xx/halmac_8821c/halmac_pcie_8821c.c linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/halmac/halmac_88xx/halmac_8821c/halmac_pcie_8821c.c
--- linux-5.6.3/3rdparty/rtl8821ce/hal/halmac/halmac_88xx/halmac_8821c/halmac_pcie_8821c.c	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/halmac/halmac_88xx/halmac_8821c/halmac_pcie_8821c.c	2020-04-10 16:35:06.791658901 +0300
@@ -0,0 +1,356 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ ******************************************************************************/
+
+#include "halmac_pcie_8821c.h"
+#include "halmac_pwr_seq_8821c.h"
+#include "../halmac_init_88xx.h"
+#include "../halmac_common_88xx.h"
+#include "../halmac_pcie_88xx.h"
+#include "halmac_8821c_cfg.h"
+
+#if (HALMAC_8821C_SUPPORT && HALMAC_PCIE_SUPPORT)
+
+#define INTF_INTGRA_MINREF	90
+#define INTF_INTGRA_HOSTREF	100
+
+static u16
+get_target(struct halmac_adapter *adapter);
+
+static enum halmac_ret_status
+freerun_delay_us(struct halmac_adapter *adapter, u16 delay);
+
+/**
+ * mac_pwr_switch_pcie_8821c() - switch mac power
+ * @adapter : the adapter of halmac
+ * @pwr : power state
+ * Author : KaiYuan Chang / Ivan Lin
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+mac_pwr_switch_pcie_8821c(struct halmac_adapter *adapter,
+			  enum halmac_mac_power pwr)
+{
+	u8 value8;
+	u8 rpwm;
+	struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
+	enum halmac_ret_status status;
+
+	PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
+	PLTFM_MSG_TRACE("[TRACE]pwr = %x\n", pwr);
+	PLTFM_MSG_TRACE("[TRACE]8821C pwr seq ver = %s\n",
+			HALMAC_8821C_PWR_SEQ_VER);
+
+	adapter->rpwm = HALMAC_REG_R8(REG_PCIE_HRPWM1_V1);
+
+	/* Check FW still exist or not */
+	if (HALMAC_REG_R16(REG_MCUFW_CTRL) == 0xC078) {
+		/* Leave 32K */
+		rpwm = (u8)((adapter->rpwm ^ BIT(7)) & 0x80);
+		HALMAC_REG_W8(REG_PCIE_HRPWM1_V1, rpwm);
+	}
+
+	value8 = HALMAC_REG_R8(REG_CR);
+	if (value8 == 0xEA)
+		adapter->halmac_state.mac_pwr = HALMAC_MAC_POWER_OFF;
+	else
+		adapter->halmac_state.mac_pwr = HALMAC_MAC_POWER_ON;
+
+	/* Check if power switch is needed */
+	if (pwr == HALMAC_MAC_POWER_ON &&
+	    adapter->halmac_state.mac_pwr == HALMAC_MAC_POWER_ON) {
+		PLTFM_MSG_WARN("[WARN]power state unchange!!\n");
+		return HALMAC_RET_PWR_UNCHANGE;
+	}
+
+	if (pwr == HALMAC_MAC_POWER_OFF) {
+		status = trxdma_check_idle_88xx(adapter);
+		if (status != HALMAC_RET_SUCCESS)
+			return status;
+		if (pwr_seq_parser_88xx(adapter, card_dis_flow_8821c) !=
+		    HALMAC_RET_SUCCESS) {
+			PLTFM_MSG_ERR("[ERR]Handle power off cmd error\n");
+			return HALMAC_RET_POWER_OFF_FAIL;
+		}
+
+		adapter->halmac_state.mac_pwr = HALMAC_MAC_POWER_OFF;
+		adapter->halmac_state.dlfw_state = HALMAC_DLFW_NONE;
+		init_adapter_dynamic_param_88xx(adapter);
+	} else {
+		if (pwr_seq_parser_88xx(adapter, card_en_flow_8821c) !=
+		    HALMAC_RET_SUCCESS) {
+			PLTFM_MSG_ERR("[ERR]Handle power on cmd error\n");
+			return HALMAC_RET_POWER_ON_FAIL;
+		}
+
+		adapter->halmac_state.mac_pwr = HALMAC_MAC_POWER_ON;
+	}
+
+	PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
+
+	return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * halmac_pcie_switch_8821c() - pcie gen1/gen2 switch
+ * @adapter : the adapter of halmac
+ * @cfg : gen1/gen2 selection
+ * Author : KaiYuan Chang / Ivan Lin
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+pcie_switch_8821c(struct halmac_adapter *adapter, enum halmac_pcie_cfg cfg)
+{
+	return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * phy_cfg_pcie_8821c() - phy config
+ * @adapter : the adapter of halmac
+ * Author : KaiYuan Chang / Ivan Lin
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+phy_cfg_pcie_8821c(struct halmac_adapter *adapter,
+		   enum halmac_intf_phy_platform pltfm)
+{
+	enum halmac_ret_status status = HALMAC_RET_SUCCESS;
+
+	PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
+
+	status = parse_intf_phy_88xx(adapter, pcie_gen1_phy_param_8821c, pltfm,
+				     HAL_INTF_PHY_PCIE_GEN1);
+
+	if (status != HALMAC_RET_SUCCESS)
+		return status;
+
+	status = parse_intf_phy_88xx(adapter, pcie_gen2_phy_param_8821c, pltfm,
+				     HAL_INTF_PHY_PCIE_GEN2);
+
+	if (status != HALMAC_RET_SUCCESS)
+		return status;
+
+	PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
+
+	return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * intf_tun_pcie_8821c() - pcie interface fine tuning
+ * @adapter : the adapter of halmac
+ * Author : Rick Liu
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+intf_tun_pcie_8821c(struct halmac_adapter *adapter)
+{
+	return HALMAC_RET_SUCCESS;
+}
+
+enum halmac_ret_status
+auto_refclk_cal_8821c_pcie(struct halmac_adapter *adapter)
+{
+	u8 bdr_ori;
+	u16 tmp_u16;
+	u16 div_set;
+	u16 mgn_tmp;
+	u16 mgn_set;
+	u16 tar;
+	enum halmac_ret_status status = HALMAC_RET_SUCCESS;
+	u8 l1_flag = 0;
+
+#if (INTF_INTGRA_HOSTREF <= INTF_INTGRA_MINREF || 0 >= INTF_INTGRA_MINREF)
+	return status;
+#endif
+	/* Disable L1BD */
+	bdr_ori = dbi_r8_88xx(adapter, PCIE_L1_BACKDOOR);
+	if (bdr_ori & (BIT(4) | BIT(3))) {
+		status = dbi_w8_88xx(adapter, PCIE_L1_BACKDOOR,
+				     bdr_ori & ~(BIT(4) | BIT(3)));
+		if (status != HALMAC_RET_SUCCESS)
+			return status;
+		l1_flag = 1;
+	}
+
+	/* Disable function */
+	tmp_u16 = mdio_read_88xx(adapter, RAC_CTRL_PPR,
+				 HAL_INTF_PHY_PCIE_GEN1);
+	if (tmp_u16 & BIT(9)) {
+		status = mdio_write_88xx(adapter, RAC_CTRL_PPR,
+					 tmp_u16 & ~(BIT(9)),
+					 HAL_INTF_PHY_PCIE_GEN1);
+		if (status != HALMAC_RET_SUCCESS)
+			return status;
+	}
+	if (adapter->pcie_refautok_en == 0) {
+		if (l1_flag == 1)
+			status = dbi_w8_88xx(adapter, PCIE_L1_BACKDOOR,
+					     bdr_ori);
+		return status;
+	}
+
+	/* Set div */
+	tmp_u16 = mdio_read_88xx(adapter, RAC_CTRL_PPR, HAL_INTF_PHY_PCIE_GEN1);
+	status = mdio_write_88xx(adapter, RAC_CTRL_PPR,
+				 tmp_u16 & ~(BIT(7) | BIT(6)),
+				 HAL_INTF_PHY_PCIE_GEN1);
+	if (status != HALMAC_RET_SUCCESS)
+		return status;
+
+	/*  Obtain div and margin */
+	tar = get_target(adapter);
+	if (tar == 0xFFFF)
+		return HALMAC_RET_FAIL;
+	mgn_tmp = tar * INTF_INTGRA_HOSTREF / INTF_INTGRA_MINREF - tar;
+
+	if (mgn_tmp >= 128) {
+		div_set = 0x0003;
+		mgn_set = 0x000F;
+	} else if (mgn_tmp >= 64) {
+		div_set = 0x0003;
+		mgn_set = mgn_tmp >> 3;
+	} else if (mgn_tmp >= 32) {
+		div_set = 0x0002;
+		mgn_set = mgn_tmp >> 2;
+	} else if (mgn_tmp >= 16) {
+		div_set = 0x0001;
+		mgn_set = mgn_tmp >> 1;
+	} else if (mgn_tmp == 0) {
+		div_set = 0x0000;
+		mgn_set = 0x0001;
+	} else {
+		div_set = 0x0000;
+		mgn_set = mgn_tmp;
+	}
+
+	/* Set div, margin, target*/
+	tmp_u16 = mdio_read_88xx(adapter, RAC_CTRL_PPR, HAL_INTF_PHY_PCIE_GEN1);
+	tmp_u16 = (tmp_u16 & ~(BIT(7) | BIT(6))) | (div_set << 6);
+	status = mdio_write_88xx(adapter, RAC_CTRL_PPR,
+				 tmp_u16, HAL_INTF_PHY_PCIE_GEN1);
+	if (status != HALMAC_RET_SUCCESS)
+		return status;
+	tar = get_target(adapter);
+	if (tar == 0xFFFF)
+		return HALMAC_RET_FAIL;
+	PLTFM_MSG_TRACE("[TRACE]target = 0x%X, div = 0x%X, margin = 0x%X\n",
+			tar, div_set, mgn_set);
+	status = mdio_write_88xx(adapter, RAC_SET_PPR,
+				 (tar & 0x0FFF) | (mgn_set << 12),
+				 HAL_INTF_PHY_PCIE_GEN1);
+	if (status != HALMAC_RET_SUCCESS)
+		return status;
+
+	/* Enable function */
+	tmp_u16 = mdio_read_88xx(adapter, RAC_CTRL_PPR, HAL_INTF_PHY_PCIE_GEN1);
+	status = mdio_write_88xx(adapter, RAC_CTRL_PPR, tmp_u16 | BIT(9),
+				 HAL_INTF_PHY_PCIE_GEN1);
+	if (status != HALMAC_RET_SUCCESS)
+		return status;
+	PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
+
+	/* Set L1BD to ori */
+	if (l1_flag == 1)
+		status = dbi_w8_88xx(adapter, PCIE_L1_BACKDOOR, bdr_ori);
+
+	return status;
+}
+
+static u16
+get_target(struct halmac_adapter *adapter)
+{
+	u16 tmp_u16;
+	u16 tar;
+	enum halmac_ret_status status = HALMAC_RET_SUCCESS;
+
+	/* Enable counter */
+	tmp_u16 = mdio_read_88xx(adapter, RAC_CTRL_PPR, HAL_INTF_PHY_PCIE_GEN1);
+	status = mdio_write_88xx(adapter, RAC_CTRL_PPR,
+				 tmp_u16 | BIT(11), HAL_INTF_PHY_PCIE_GEN1);
+	if (status != HALMAC_RET_SUCCESS)
+		return 0xFFFF;
+
+	/* Obtain target */
+	status = freerun_delay_us(adapter, 300);
+	if (status != HALMAC_RET_SUCCESS)
+		return 0xFFFF;
+	tar = mdio_read_88xx(adapter, RAC_TRG_PPR, HAL_INTF_PHY_PCIE_GEN1);
+	if (tar == 0) {
+		PLTFM_MSG_ERR("[ERR]Get target failed.\n");
+		return 0xFFFF;
+	}
+
+	/* Disable counter */
+	tmp_u16 = mdio_read_88xx(adapter, RAC_CTRL_PPR, HAL_INTF_PHY_PCIE_GEN1);
+	status = mdio_write_88xx(adapter, RAC_CTRL_PPR,
+				 tmp_u16 & ~(BIT(11)), HAL_INTF_PHY_PCIE_GEN1);
+	if (status != HALMAC_RET_SUCCESS)
+		return 0xFFFF;
+	return tar;
+}
+
+static enum halmac_ret_status
+freerun_delay_us(struct halmac_adapter *adapter, u16 delay)
+{
+	u16 count;
+	u8 mc_ori;
+	u32 frcnt_ori;
+	u32 frcnt_cmp;
+	u8 frcnt_onflg = 0;
+	u32 cmp_val;
+	struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
+	enum halmac_ret_status status = HALMAC_RET_SUCCESS;
+
+	/* Enable free-run counter */
+	mc_ori = HALMAC_REG_R8(REG_MISC_CTRL);
+	if ((mc_ori & BIT(3)) == 0) {
+		status = HALMAC_REG_W8(REG_MISC_CTRL, mc_ori | BIT(3));
+		if (status != HALMAC_RET_SUCCESS)
+			return status;
+		frcnt_onflg = 1;
+	}
+
+	/* counting delay */
+	count = 20;
+	frcnt_ori = HALMAC_REG_R32(REG_FREERUN_CNT);
+	PLTFM_MSG_TRACE("[TRACE]free_ori = 0x%X\n", frcnt_ori);
+	do {
+		PLTFM_DELAY_US(100);
+		count--;
+		frcnt_cmp = HALMAC_REG_R32(REG_FREERUN_CNT);
+		PLTFM_MSG_TRACE("[TRACE]Count=0x%X, free_cmp=0x%X\n"
+				, count, frcnt_cmp);
+		if (frcnt_cmp >= frcnt_ori)
+			cmp_val = frcnt_cmp - frcnt_ori;
+		else
+			cmp_val = 0xFFFFFFFF - frcnt_ori + frcnt_cmp;
+	} while ((count > 0) && (cmp_val < delay));
+
+	/*  Reset freerun counter */
+	if (frcnt_onflg != 1)
+		return status;
+
+	status = HALMAC_REG_W8(REG_MISC_CTRL, mc_ori);
+	if (status != HALMAC_RET_SUCCESS)
+		return status;
+	status = HALMAC_REG_W8(REG_DUAL_TSF_RST,
+			       HALMAC_REG_R8(REG_DUAL_TSF_RST) | BIT(5));
+	return status;
+}
+
+#endif /* HALMAC_8821C_SUPPORT */
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/halmac/halmac_88xx/halmac_8821c/halmac_pcie_8821c.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/halmac/halmac_88xx/halmac_8821c/halmac_pcie_8821c.h
--- linux-5.6.3/3rdparty/rtl8821ce/hal/halmac/halmac_88xx/halmac_8821c/halmac_pcie_8821c.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/halmac/halmac_88xx/halmac_8821c/halmac_pcie_8821c.h	2020-04-10 16:35:06.791658901 +0300
@@ -0,0 +1,45 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ ******************************************************************************/
+
+#ifndef _HALMAC_PCIE_8821C_H_
+#define _HALMAC_PCIE_8821C_H_
+
+#include "../../halmac_api.h"
+
+#if (HALMAC_8821C_SUPPORT && HALMAC_PCIE_SUPPORT)
+
+extern struct halmac_intf_phy_para pcie_gen1_phy_param_8821c[];
+extern struct halmac_intf_phy_para pcie_gen2_phy_param_8821c[];
+
+enum halmac_ret_status
+mac_pwr_switch_pcie_8821c(struct halmac_adapter *adapter,
+			  enum halmac_mac_power pwr);
+
+enum halmac_ret_status
+pcie_switch_8821c(struct halmac_adapter *adapter, enum halmac_pcie_cfg cfg);
+
+enum halmac_ret_status
+phy_cfg_pcie_8821c(struct halmac_adapter *adapter,
+		   enum halmac_intf_phy_platform pltfm);
+
+enum halmac_ret_status
+intf_tun_pcie_8821c(struct halmac_adapter *adapter);
+
+enum halmac_ret_status
+auto_refclk_cal_8821c_pcie(struct halmac_adapter *adapter);
+
+#endif /* HALMAC_8821C_SUPPORT */
+
+#endif/* _HALMAC_PCIE_8821C_H_ */
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/halmac/halmac_88xx/halmac_8821c/halmac_phy_8821c.c linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/halmac/halmac_88xx/halmac_8821c/halmac_phy_8821c.c
--- linux-5.6.3/3rdparty/rtl8821ce/hal/halmac/halmac_88xx/halmac_8821c/halmac_phy_8821c.c	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/halmac/halmac_88xx/halmac_8821c/halmac_phy_8821c.c	2020-04-10 16:35:06.791658901 +0300
@@ -0,0 +1,76 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ ******************************************************************************/
+
+#include "../../halmac_type.h"
+#if HALMAC_USB_SUPPORT
+#include "halmac_usb_8821c.h"
+#endif
+#if HALMAC_PCIE_SUPPORT
+#include "halmac_pcie_8821c.h"
+#endif
+
+/**
+ * ============ip sel item list============
+ * HALMAC_IP_INTF_PHY
+ *	USB2 : usb2 phy, 1byte value
+ *	USB3 : usb3 phy, 2byte value
+ *	PCIE1 : pcie gen1 mdio, 2byte value
+ *	PCIE2 : pcie gen2 mdio, 2byte value
+ * HALMAC_IP_SEL_MAC
+ *	USB2, USB3, PCIE1, PCIE2 : mac ip, 1byte value
+ * HALMAC_IP_PCIE_DBI
+ *	USB2 USB3 : none
+ *	PCIE1, PCIE2 : pcie dbi, 1byte value
+ */
+
+#if HALMAC_8821C_SUPPORT
+
+struct halmac_intf_phy_para usb2_phy_param_8821c[] = {
+	/* {offset, value, ip sel, cut mask, platform mask} */
+	{0xFFFF, 0x00,
+	 HALMAC_IP_INTF_PHY,
+	 HALMAC_INTF_PHY_CUT_ALL,
+	 HALMAC_INTF_PHY_PLATFORM_ALL},
+};
+
+struct halmac_intf_phy_para usb3_phy_param_8821c[] = {
+	/* {offset, value, cut mask, platform mask} */
+	{0xFFFF, 0x0000,
+	 HALMAC_IP_INTF_PHY,
+	 HALMAC_INTF_PHY_CUT_ALL,
+	 HALMAC_INTF_PHY_PLATFORM_ALL},
+};
+
+struct halmac_intf_phy_para pcie_gen1_phy_param_8821c[] = {
+	/* {offset, value, ip sel, cut mask, platform mask} */
+	{0x0009, 0x6380,
+	 HALMAC_IP_INTF_PHY,
+	 HALMAC_INTF_PHY_CUT_ALL,
+	 HALMAC_INTF_PHY_PLATFORM_ALL},
+	{0xFFFF, 0x0000,
+	 HALMAC_IP_INTF_PHY,
+	 HALMAC_INTF_PHY_CUT_ALL,
+	 HALMAC_INTF_PHY_PLATFORM_ALL},
+};
+
+struct halmac_intf_phy_para pcie_gen2_phy_param_8821c[] = {
+	/* {offset, value, ip sel, cut mask, platform mask} */
+	{0xFFFF, 0x0000,
+	 HALMAC_IP_INTF_PHY,
+	 HALMAC_INTF_PHY_CUT_ALL,
+	 HALMAC_INTF_PHY_PLATFORM_ALL},
+};
+
+#endif /* HALMAC_8821C_SUPPORT */
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/halmac/halmac_88xx/halmac_8821c/halmac_pwr_seq_8821c.c linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/halmac/halmac_88xx/halmac_8821c/halmac_pwr_seq_8821c.c
--- linux-5.6.3/3rdparty/rtl8821ce/hal/halmac/halmac_88xx/halmac_8821c/halmac_pwr_seq_8821c.c	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/halmac/halmac_88xx/halmac_8821c/halmac_pwr_seq_8821c.c	2020-04-10 16:35:06.791658901 +0300
@@ -0,0 +1,905 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ ******************************************************************************/
+
+#include "halmac_pwr_seq_8821c.h"
+
+#if HALMAC_8821C_SUPPORT
+
+static struct halmac_wlan_pwr_cfg TRANS_CARDDIS_TO_CARDEMU_8821C[] = {
+	/* { offset, cut_msk, interface_msk, base|cmd, msk, value } */
+	{0x0086,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_SDIO_MSK,
+	 HALMAC_PWR_ADDR_SDIO,
+	 HALMAC_PWR_CMD_WRITE, BIT(0), 0},
+	{0x0086,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_SDIO_MSK,
+	 HALMAC_PWR_ADDR_SDIO,
+	 HALMAC_PWR_CMD_POLLING, BIT(1), BIT(1)},
+	{0x004A,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_USB_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_WRITE, BIT(0), 0},
+	{0x0005,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_ALL_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_WRITE, BIT(3) | BIT(4) | BIT(7), 0},
+	{0x0300,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_PCI_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_WRITE, 0xFF, 0},
+	{0x0301,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_PCI_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_WRITE, 0xFF, 0},
+	{0xFFFF,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_ALL_MSK,
+	 0,
+	 HALMAC_PWR_CMD_END, 0, 0},
+};
+
+static struct halmac_wlan_pwr_cfg TRANS_CARDEMU_TO_ACT_8821C[] = {
+	/* { offset, cut_msk, interface_msk, base|cmd, msk, value } */
+	{0x0020,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_USB_MSK | HALMAC_PWR_INTF_SDIO_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_WRITE, BIT(0), BIT(0)},
+	{0x0001,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_USB_MSK | HALMAC_PWR_INTF_SDIO_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_DELAY, 1, HALMAC_PWR_DELAY_MS},
+	{0x0000,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_USB_MSK | HALMAC_PWR_INTF_SDIO_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_WRITE, BIT(5), 0},
+	{0x0005,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_ALL_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_WRITE, (BIT(4) | BIT(3) | BIT(2)), 0},
+	{0x0075,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_PCI_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_WRITE, BIT(0), BIT(0)},
+	{0x0006,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_ALL_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_POLLING, BIT(1), BIT(1)},
+	{0x0075,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_PCI_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_WRITE, BIT(0), 0 },
+	{0x0006,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_ALL_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_WRITE, BIT(0), BIT(0)},
+	{0x0005,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_ALL_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_WRITE, BIT(7), 0 },
+	{0x0005,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_ALL_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_WRITE, (BIT(4) | BIT(3)), 0},
+	{0x10C3,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_USB_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_WRITE, BIT(0), BIT(0)},
+	{0x0005,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_ALL_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_WRITE, BIT(0), BIT(0)},
+	{0x0005,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_ALL_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_POLLING, BIT(0), 0},
+	{0x0020,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_ALL_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_WRITE, BIT(3), BIT(3)},
+	{0x0074,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_PCI_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_WRITE, BIT(5), BIT(5)},
+	{0x0022,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_PCI_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_WRITE, BIT(1), 0},
+	{0x0062,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_PCI_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_WRITE, (BIT(7) | BIT(6) | BIT(5)),
+	 (BIT(7) | BIT(6) | BIT(5))},
+	{0x0061,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_PCI_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_WRITE, (BIT(7) | BIT(6) | BIT(5)), 0},
+	{0x007C,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_ALL_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_WRITE, BIT(1), 0 },
+	{0xFFFF,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_ALL_MSK,
+	 0,
+	 HALMAC_PWR_CMD_END, 0, 0},
+};
+
+static struct halmac_wlan_pwr_cfg TRANS_ACT_TO_CARDEMU_8821C[] = {
+	/* { offset, cut_msk, interface_msk, base|cmd, msk, value } */
+	{0x0093,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_ALL_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_WRITE, BIT(3), 0},
+	{0x001F,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_ALL_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_WRITE, 0xFF, 0},
+	{0x0049,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_ALL_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_WRITE, BIT(1), 0},
+	{0x0006,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_ALL_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_WRITE, BIT(0), BIT(0)},
+	{0x0002,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_ALL_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_WRITE, BIT(1), 0},
+	{0x10C3,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_USB_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_WRITE, BIT(0), 0},
+	{0x0005,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_ALL_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_WRITE, BIT(1), BIT(1)},
+	{0x0005,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_ALL_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_POLLING, BIT(1), 0},
+	{0x0020,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_ALL_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_WRITE, BIT(3), 0},
+	{0x0000,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_USB_MSK | HALMAC_PWR_INTF_SDIO_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_WRITE, BIT(5), BIT(5)},
+	{0xFFFF,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_ALL_MSK,
+	 0,
+	 HALMAC_PWR_CMD_END, 0, 0},
+};
+
+static struct halmac_wlan_pwr_cfg TRANS_CARDEMU_TO_CARDDIS_8821C[] = {
+	/* { offset, cut_msk, interface_msk, base|cmd, msk, value } */
+	{0x0007,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_USB_MSK | HALMAC_PWR_INTF_SDIO_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_WRITE, 0xFF, 0x20},
+	{0x0067,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_ALL_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_WRITE, BIT(5), 0},
+	{0x0005,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_USB_MSK | HALMAC_PWR_INTF_SDIO_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_WRITE, BIT(3) | BIT(4), BIT(3)},
+	{0x0005,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_PCI_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_WRITE, BIT(2), BIT(2)},
+	{0x004A,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_USB_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_WRITE, BIT(0), 0},
+	{0x0067,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_SDIO_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_WRITE, BIT(5), 0 },
+	{0x0067,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_SDIO_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_WRITE, BIT(4), 0 },
+	{0x004F,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_SDIO_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_WRITE, BIT(0), 0 },
+	{0x0067,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_SDIO_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_WRITE, BIT(1), 0 },
+	{0x0046,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_SDIO_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_WRITE, BIT(6), BIT(6) },
+	{0x0067,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_SDIO_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_WRITE, BIT(2), 0 },
+	{0x0046,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_SDIO_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_WRITE, BIT(7), BIT(7) },
+	{0x0062,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_SDIO_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_WRITE, BIT(4), BIT(4) },
+	{0x0081,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_ALL_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_WRITE, BIT(7) | BIT(6), 0},
+	{0x0086,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_SDIO_MSK,
+	 HALMAC_PWR_ADDR_SDIO,
+	 HALMAC_PWR_CMD_WRITE, BIT(0), BIT(0)},
+	{0x0086,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_SDIO_MSK,
+	 HALMAC_PWR_ADDR_SDIO,
+	 HALMAC_PWR_CMD_POLLING, BIT(1), 0},
+	{0x0090,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_USB_MSK | HALMAC_PWR_INTF_PCI_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_WRITE, BIT(1), 0},
+	{0x0044,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_SDIO_MSK,
+	 HALMAC_PWR_ADDR_SDIO,
+	 HALMAC_PWR_CMD_WRITE, 0xFF, 0},
+	{0x0040,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_SDIO_MSK,
+	 HALMAC_PWR_ADDR_SDIO,
+	 HALMAC_PWR_CMD_WRITE, 0xFF, 0x90},
+	{0x0041,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_SDIO_MSK,
+	 HALMAC_PWR_ADDR_SDIO,
+	 HALMAC_PWR_CMD_WRITE, 0xFF, 0x00},
+	{0x0042,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_SDIO_MSK,
+	 HALMAC_PWR_ADDR_SDIO,
+	 HALMAC_PWR_CMD_WRITE, 0xFF, 0x04},
+	{0xFFFF,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_ALL_MSK,
+	 0,
+	 HALMAC_PWR_CMD_END, 0, 0},
+};
+
+/* Card Enable Array */
+struct halmac_wlan_pwr_cfg *card_en_flow_8821c[] = {
+	TRANS_CARDDIS_TO_CARDEMU_8821C,
+	TRANS_CARDEMU_TO_ACT_8821C,
+	NULL
+};
+
+/* Card Disable Array */
+struct halmac_wlan_pwr_cfg *card_dis_flow_8821c[] = {
+	TRANS_ACT_TO_CARDEMU_8821C,
+	TRANS_CARDEMU_TO_CARDDIS_8821C,
+	NULL
+};
+
+#if HALMAC_PLATFORM_TESTPROGRAM
+
+static struct halmac_wlan_pwr_cfg TRANS_CARDEMU_TO_SUS_8821C[] = {
+	/* { offset, cut_msk, interface_msk, base|cmd, msk, value } */
+	{0x0005,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_PCI_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_WRITE, BIT(4) | BIT(3), (BIT(4) | BIT(3))},
+	{0x0005,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_USB_MSK | HALMAC_PWR_INTF_SDIO_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_WRITE, BIT(3) | BIT(4), BIT(3)},
+	{0x0007,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_SDIO_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_WRITE, 0xFF, 0x20},
+	{0x0005,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_PCI_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_WRITE, BIT(3) | BIT(4), BIT(3) | BIT(4)},
+	{0x0086,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_SDIO_MSK,
+	 HALMAC_PWR_ADDR_SDIO,
+	 HALMAC_PWR_CMD_WRITE, BIT(0), BIT(0)},
+	{0x0086,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_SDIO_MSK,
+	 HALMAC_PWR_ADDR_SDIO,
+	 HALMAC_PWR_CMD_POLLING, BIT(1), 0},
+	{0xFFFF,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_ALL_MSK,
+	 0,
+	 HALMAC_PWR_CMD_END, 0, 0},
+};
+
+static struct halmac_wlan_pwr_cfg TRANS_SUS_TO_CARDEMU_8821C[] = {
+	/* { offset, cut_msk, interface_msk, base|cmd, msk, value } */
+	{0x0005,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_ALL_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_WRITE, BIT(3) | BIT(7), 0},
+	{0x0086,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_SDIO_MSK,
+	 HALMAC_PWR_ADDR_SDIO,
+	 HALMAC_PWR_CMD_WRITE, BIT(0), 0},
+	{0x0086,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_SDIO_MSK,
+	 HALMAC_PWR_ADDR_SDIO,
+	 HALMAC_PWR_CMD_POLLING, BIT(1), BIT(1)},
+	{0x0005,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_ALL_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_WRITE, BIT(3) | BIT(4), 0},
+	{0xFFFF,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_ALL_MSK,
+	 0,
+	 HALMAC_PWR_CMD_END, 0, 0},
+};
+
+static struct halmac_wlan_pwr_cfg TRANS_CARDEMU_TO_PDN_8821C[] = {
+	/* { offset, cut_msk, interface_msk, base|cmd, msk, value } */
+	{0x0007,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_SDIO_MSK | HALMAC_PWR_INTF_USB_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_WRITE, 0xFF, 0x20},
+	{0x0006,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_ALL_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_WRITE, BIT(0), 0},
+	{0x0005,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_ALL_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_WRITE, BIT(7), BIT(7)},
+	{0xFFFF,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_ALL_MSK,
+	 0,
+	 HALMAC_PWR_CMD_END, 0, 0},
+};
+
+static struct halmac_wlan_pwr_cfg TRANS_PDN_TO_CARDEMU_8821C[] = {
+	/* { offset, cut_msk, interface_msk, base|cmd, msk, value } */
+	{0x0005,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_ALL_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_WRITE, BIT(7), 0},
+	{0xFFFF,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_ALL_MSK,
+	 0,
+	 HALMAC_PWR_CMD_END, 0, 0},
+};
+
+static struct halmac_wlan_pwr_cfg TRANS_ACT_TO_LPS_8821C[] = {
+	/* { offset, cut_msk, interface_msk, base|cmd, msk, value } */
+	{0x0101,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_ALL_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_WRITE, BIT(2), BIT(2)},
+	{0x0199,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_ALL_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_WRITE, BIT(3), BIT(3)},
+	{0x019B,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_ALL_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_WRITE, BIT(7), BIT(7)},
+	{0x1138,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_ALL_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_WRITE, BIT(0) | BIT(1), BIT(0) | BIT(1)},
+	{0x0194,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_ALL_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_WRITE, BIT(0), BIT(0)},
+	{0x0093,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_PCI_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_WRITE, 0xFF, 0xD6},
+	{0x0092,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_PCI_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_WRITE, 0xFF, 0x60},
+	{0x0093,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_USB_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_WRITE, 0xFF, 0x93},
+	{0x0092,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_USB_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_WRITE, 0xFF, 0x60},
+	{0x0093,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_SDIO_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_WRITE, 0xFF, 0x2},
+	{0x0092,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_SDIO_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_WRITE, 0xFF, 0x60},
+	{0x0090,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_ALL_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_WRITE, BIT(1), BIT(1)},
+	{0x0301,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_PCI_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_WRITE, 0xFF, 0xFF},
+	{0x0522,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_ALL_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_WRITE, 0xFF, 0xFF},
+	{0x05F8,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_ALL_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_POLLING, 0xFF, 0},
+	{0x05F9,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_ALL_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_POLLING, 0xFF, 0},
+	{0x05FA,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_ALL_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_POLLING, 0xFF, 0},
+	{0x05FB,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_ALL_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_POLLING, 0xFF, 0},
+	{0x0002,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_ALL_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_WRITE, BIT(0), 0},
+	{0x0002,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_ALL_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_DELAY, 0, HALMAC_PWR_DELAY_US},
+	{0x0002,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_ALL_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_WRITE, BIT(1), 0},
+	{0x0100,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_ALL_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_WRITE, 0xFF, 0x3F},
+	{0x0101,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_ALL_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_WRITE, BIT(1), 0},
+	{0x0553,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_ALL_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_WRITE, BIT(5), BIT(5)},
+	{0x0008,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_ALL_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_WRITE, BIT(4), BIT(4)},
+	{0x0109,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_ALL_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_POLLING, BIT(7), BIT(7)},
+	{0x0090,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_ALL_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_WRITE, BIT(0), BIT(0)},
+	{0xFFFF,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_ALL_MSK,
+	 0,
+	 HALMAC_PWR_CMD_END, 0, 0},
+};
+
+static struct halmac_wlan_pwr_cfg TRANS_ACT_TO_DEEP_LPS_8821C[] = {
+	/* { offset, cut_msk, interface_msk, base|cmd, msk, value } */
+	{0x0101,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_ALL_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_WRITE, BIT(2), BIT(2)},
+	{0x0199,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_ALL_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_WRITE, BIT(3), BIT(3)},
+	{0x019B,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_ALL_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_WRITE, BIT(7), BIT(7)},
+	{0x1138,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_ALL_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_WRITE, BIT(0) | BIT(1), BIT(0) | BIT(1)},
+	{0x0194,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_ALL_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_WRITE, BIT(0), BIT(0)},
+	{0x0093,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_PCI_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_WRITE, 0xFF, 0xD4},
+	{0x0092,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_PCI_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_WRITE, 0xFF, 0x20},
+	{0x0093,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_USB_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_WRITE, 0xFF, 0x91},
+	{0x0092,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_USB_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_WRITE, 0xFF, 0x20},
+	{0x0093,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_SDIO_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_WRITE, 0xFF, 0x0},
+	{0x0092,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_SDIO_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_WRITE, 0xFF, 0x20},
+	{0x0090,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_ALL_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_WRITE, BIT(1), BIT(1)},
+	{0x0301,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_PCI_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_WRITE, 0xFF, 0xFF},
+	{0x0522,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_ALL_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_WRITE, 0xFF, 0xFF},
+	{0x05F8,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_ALL_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_POLLING, 0xFF, 0},
+	{0x05F9,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_ALL_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_POLLING, 0xFF, 0},
+	{0x05FA,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_ALL_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_POLLING, 0xFF, 0},
+	{0x05FB,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_ALL_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_POLLING, 0xFF, 0},
+	{0x0002,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_ALL_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_WRITE, BIT(0), 0},
+	{0x0002,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_ALL_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_DELAY, 0, HALMAC_PWR_DELAY_US},
+	{0x0002,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_ALL_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_WRITE, BIT(1), 0},
+	{0x0100,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_ALL_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_WRITE, 0xFF, 0x3F},
+	{0x0101,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_ALL_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_WRITE, BIT(1), 0},
+	{0x0553,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_ALL_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_WRITE, BIT(5), BIT(5)},
+	{0x0008,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_ALL_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_WRITE, BIT(4), BIT(4)},
+	{0x0109,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_ALL_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_POLLING, BIT(7), BIT(7)},
+	{0x0090,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_ALL_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_WRITE, BIT(0), BIT(0)},
+	{0xFFFF,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_ALL_MSK,
+	 0,
+	 HALMAC_PWR_CMD_END, 0, 0},
+};
+
+static struct halmac_wlan_pwr_cfg TRANS_LPS_TO_ACT_8821C[] = {
+	/* { offset, cut_msk, interface_msk, base|cmd, msk, value } */
+	{0x0080,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_SDIO_MSK,
+	 HALMAC_PWR_ADDR_SDIO,
+	 HALMAC_PWR_CMD_WRITE, BIT(7), BIT(7)},
+	{0x0002,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_ALL_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_DELAY, 0, HALMAC_PWR_DELAY_MS},
+	{0x0080,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_SDIO_MSK,
+	 HALMAC_PWR_ADDR_SDIO,
+	 HALMAC_PWR_CMD_WRITE, BIT(7), 0},
+	{0xFE58,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_USB_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_WRITE, 0xFF, 0x84},
+	{0xFE58,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_USB_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_WRITE, 0xFF, 0x04},
+	{0x03D9,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_PCI_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_WRITE, BIT(7), BIT(7)},
+	{0x0002,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_PCI_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_DELAY, 0, HALMAC_PWR_DELAY_MS},
+	{0x03D9,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_PCI_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_WRITE, BIT(7), 0},
+	{0x0002,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_ALL_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_DELAY, 0, HALMAC_PWR_DELAY_MS},
+	{0x0008,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_ALL_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_WRITE, BIT(4), 0},
+	{0x0109,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_ALL_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_POLLING, BIT(7), 0},
+	{0x0101,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_ALL_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_WRITE, BIT(1), BIT(1)},
+	{0x0100,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_ALL_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_WRITE, 0xFF, 0xFF },
+	{0x0002,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_ALL_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_WRITE, BIT(1) | BIT(0), BIT(1) | BIT(0)},
+	{0x0522,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_ALL_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_WRITE, 0xFF, 0},
+	{0x113C,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_ALL_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_WRITE, 0xFF, 0x03},
+	{0x0124,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_ALL_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_WRITE, 0xFF, 0xFF},
+	{0x0125,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_ALL_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_WRITE, 0xFF, 0xFF},
+	{0x0126,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_ALL_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_WRITE, 0xFF, 0xFF},
+	{0x0127,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_ALL_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_WRITE, 0xFF, 0xFF},
+	{0x0090,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_ALL_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_WRITE, BIT(1), 0},
+	{0x0101,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_ALL_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_WRITE, BIT(2), 0},
+	{0xFFFF,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_ALL_MSK,
+	 0,
+	 HALMAC_PWR_CMD_END, 0, 0},
+};
+
+/* Suspend Array */
+struct halmac_wlan_pwr_cfg *suspend_flow_8821c[] = {
+	TRANS_ACT_TO_CARDEMU_8821C,
+	TRANS_CARDEMU_TO_SUS_8821C,
+	NULL
+};
+
+/* Resume Array */
+struct halmac_wlan_pwr_cfg *resume_flow_8821c[] = {
+	TRANS_SUS_TO_CARDEMU_8821C,
+	TRANS_CARDEMU_TO_ACT_8821C,
+	NULL
+};
+
+/* HWPDN Array - HW behavior */
+struct halmac_wlan_pwr_cfg *hwpdn_flow_8821c[] = {
+	NULL
+};
+
+/* Enter LPS - FW behavior */
+struct halmac_wlan_pwr_cfg *enter_lps_flow_8821c[] = {
+	TRANS_ACT_TO_LPS_8821C,
+	NULL
+};
+
+/* Enter Deep LPS - FW behavior */
+struct halmac_wlan_pwr_cfg *enter_dlps_flow_8821c[] = {
+	TRANS_ACT_TO_DEEP_LPS_8821C,
+	NULL
+};
+
+/* Leave LPS -FW behavior */
+struct halmac_wlan_pwr_cfg *leave_lps_flow_8821c[] = {
+	TRANS_LPS_TO_ACT_8821C,
+	NULL
+};
+
+#endif
+
+#endif /* HALMAC_8821C_SUPPORT */
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/halmac/halmac_88xx/halmac_8821c/halmac_pwr_seq_8821c.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/halmac/halmac_88xx/halmac_8821c/halmac_pwr_seq_8821c.h
--- linux-5.6.3/3rdparty/rtl8821ce/hal/halmac/halmac_88xx/halmac_8821c/halmac_pwr_seq_8821c.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/halmac/halmac_88xx/halmac_8821c/halmac_pwr_seq_8821c.h	2020-04-10 16:35:06.791658901 +0300
@@ -0,0 +1,37 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ ******************************************************************************/
+
+#ifndef HALMAC_POWER_SEQUENCE_8821C
+#define HALMAC_POWER_SEQUENCE_8821C
+
+#include "../../halmac_pwr_seq_cmd.h"
+#include "../../halmac_hw_cfg.h"
+
+#if HALMAC_8821C_SUPPORT
+
+#define HALMAC_8821C_PWR_SEQ_VER  "V19"
+
+extern struct halmac_wlan_pwr_cfg *card_dis_flow_8821c[];
+extern struct halmac_wlan_pwr_cfg *card_en_flow_8821c[];
+extern struct halmac_wlan_pwr_cfg *suspend_flow_8821c[];
+extern struct halmac_wlan_pwr_cfg *resume_flow_8821c[];
+extern struct halmac_wlan_pwr_cfg *hwpdn_flow_8821c[];
+extern struct halmac_wlan_pwr_cfg *enter_lps_flow_8821c[];
+extern struct halmac_wlan_pwr_cfg *enter_dlps_flow_8821c[];
+extern struct halmac_wlan_pwr_cfg *leave_lps_flow_8821c[];
+
+#endif /* HALMAC_8821C_SUPPORT */
+
+#endif
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/halmac/halmac_88xx/halmac_88xx_cfg.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/halmac/halmac_88xx/halmac_88xx_cfg.h
--- linux-5.6.3/3rdparty/rtl8821ce/hal/halmac/halmac_88xx/halmac_88xx_cfg.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/halmac/halmac_88xx/halmac_88xx_cfg.h	2020-04-10 16:35:06.791658901 +0300
@@ -0,0 +1,44 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ ******************************************************************************/
+
+#ifndef _HALMAC_88XX_CFG_H_
+#define _HALMAC_88XX_CFG_H_
+
+#include "../halmac_api.h"
+
+#if HALMAC_88XX_SUPPORT
+
+#define TX_PAGE_SIZE_88XX		128
+#define TX_PAGE_SIZE_SHIFT_88XX		7 /* 128 = 2^7 */
+#define TX_ALIGN_SIZE_88XX		8
+#define SDIO_TX_MAX_SIZE_88XX		31744
+#define RX_BUF_FW_88XX			12288
+
+#define TX_DESC_SIZE_88XX		48
+#define RX_DESC_SIZE_88XX		24
+
+#define H2C_PKT_SIZE_88XX		32 /* Only support 32 byte packet now */
+#define H2C_PKT_HDR_SIZE_88XX		8
+#define C2H_DATA_OFFSET_88XX		10
+#define C2H_PKT_BUF_88XX		256
+
+/* HW memory address */
+#define OCPBASE_TXBUF_88XX		0x18780000
+#define OCPBASE_DMEM_88XX		0x00200000
+#define OCPBASE_EMEM_88XX		0x00100000
+
+#endif /* HALMAC_88XX_SUPPORT */
+
+#endif
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/halmac/halmac_88xx/halmac_api_88xx.c linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/halmac/halmac_88xx/halmac_api_88xx.c
--- linux-5.6.3/3rdparty/rtl8821ce/hal/halmac/halmac_88xx/halmac_api_88xx.c	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/halmac/halmac_88xx/halmac_api_88xx.c	2020-04-10 16:35:06.792658947 +0300
@@ -0,0 +1,5617 @@
+#include "halmac_88xx_cfg.h"
+
+/**
+ * halmac_init_adapter_para_88xx() - int halmac adapter
+ * @pHalmac_adapter
+ *
+ * SD1 internal use
+ *
+ * Author : KaiYuan Chang/Ivan Lin
+ * Return : VOID
+ */
+VOID
+halmac_init_adapter_para_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter
+)
+{
+	pHalmac_adapter->api_record.array_wptr = 0;
+	pHalmac_adapter->pHalAdapter_backup = pHalmac_adapter;
+	pHalmac_adapter->pHalEfuse_map = (u8 *)NULL;
+	pHalmac_adapter->hal_efuse_map_valid = _FALSE;
+	pHalmac_adapter->efuse_end = 0;
+	pHalmac_adapter->pHal_mac_addr[0].Address_L_H.Address_Low = 0;
+	pHalmac_adapter->pHal_mac_addr[0].Address_L_H.Address_High = 0;
+	pHalmac_adapter->pHal_mac_addr[1].Address_L_H.Address_Low = 0;
+	pHalmac_adapter->pHal_mac_addr[1].Address_L_H.Address_High = 0;
+	pHalmac_adapter->pHal_bss_addr[0].Address_L_H.Address_Low = 0;
+	pHalmac_adapter->pHal_bss_addr[0].Address_L_H.Address_High = 0;
+	pHalmac_adapter->pHal_bss_addr[1].Address_L_H.Address_Low = 0;
+	pHalmac_adapter->pHal_bss_addr[1].Address_L_H.Address_High = 0;
+
+	pHalmac_adapter->low_clk = _FALSE;
+	pHalmac_adapter->max_download_size = HALMAC_FW_MAX_DL_SIZE_88XX;
+
+	/* Init LPS Option */
+	pHalmac_adapter->fwlps_option.mode = 0x01; /*0:Active 1:LPS 2:WMMPS*/
+	pHalmac_adapter->fwlps_option.awake_interval = 1;
+	pHalmac_adapter->fwlps_option.enter_32K = 1;
+	pHalmac_adapter->fwlps_option.clk_request = 0;
+	pHalmac_adapter->fwlps_option.rlbm = 0;
+	pHalmac_adapter->fwlps_option.smart_ps = 0;
+	pHalmac_adapter->fwlps_option.awake_interval = 1;
+	pHalmac_adapter->fwlps_option.all_queue_uapsd = 0;
+	pHalmac_adapter->fwlps_option.pwr_state = 0;
+	pHalmac_adapter->fwlps_option.low_pwr_rx_beacon = 0;
+	pHalmac_adapter->fwlps_option.ant_auto_switch = 0;
+	pHalmac_adapter->fwlps_option.ps_allow_bt_high_Priority = 0;
+	pHalmac_adapter->fwlps_option.protect_bcn = 0;
+	pHalmac_adapter->fwlps_option.silence_period = 0;
+	pHalmac_adapter->fwlps_option.fast_bt_connect = 0;
+	pHalmac_adapter->fwlps_option.two_antenna_en = 0;
+	pHalmac_adapter->fwlps_option.adopt_user_Setting = 1;
+	pHalmac_adapter->fwlps_option.drv_bcn_early_shift = 0;
+
+	pHalmac_adapter->config_para_info.pCfg_para_buf = NULL;
+	pHalmac_adapter->config_para_info.pPara_buf_w = NULL;
+	pHalmac_adapter->config_para_info.para_num = 0;
+	pHalmac_adapter->config_para_info.full_fifo_mode = _FALSE;
+	pHalmac_adapter->config_para_info.para_buf_size = 0;
+	pHalmac_adapter->config_para_info.avai_para_buf_size = 0;
+	pHalmac_adapter->config_para_info.offset_accumulation = 0;
+	pHalmac_adapter->config_para_info.value_accumulation = 0;
+	pHalmac_adapter->config_para_info.datapack_segment = 0;
+
+	pHalmac_adapter->ch_sw_info.ch_info_buf = NULL;
+	pHalmac_adapter->ch_sw_info.ch_info_buf_w = NULL;
+	pHalmac_adapter->ch_sw_info.extra_info_en = 0;
+	pHalmac_adapter->ch_sw_info.buf_size = 0;
+	pHalmac_adapter->ch_sw_info.avai_buf_size = 0;
+	pHalmac_adapter->ch_sw_info.total_size = 0;
+	pHalmac_adapter->ch_sw_info.ch_num = 0;
+
+	pHalmac_adapter->drv_info_size = 0;
+
+	PLATFORM_RTL_MEMSET(pHalmac_adapter->pDriver_adapter, pHalmac_adapter->api_record.api_array, HALMAC_API_STUFF, sizeof(pHalmac_adapter->api_record.api_array));
+
+	pHalmac_adapter->txff_allocation.tx_fifo_pg_num = 0;
+	pHalmac_adapter->txff_allocation.ac_q_pg_num = 0;
+	pHalmac_adapter->txff_allocation.rsvd_pg_bndy = 0;
+	pHalmac_adapter->txff_allocation.rsvd_drv_pg_bndy = 0;
+	pHalmac_adapter->txff_allocation.rsvd_h2c_extra_info_pg_bndy = 0;
+	pHalmac_adapter->txff_allocation.rsvd_h2c_queue_pg_bndy = 0;
+	pHalmac_adapter->txff_allocation.rsvd_cpu_instr_pg_bndy = 0;
+	pHalmac_adapter->txff_allocation.rsvd_fw_txbuff_pg_bndy = 0;
+	pHalmac_adapter->txff_allocation.pub_queue_pg_num = 0;
+	pHalmac_adapter->txff_allocation.high_queue_pg_num = 0;
+	pHalmac_adapter->txff_allocation.low_queue_pg_num = 0;
+	pHalmac_adapter->txff_allocation.normal_queue_pg_num = 0;
+	pHalmac_adapter->txff_allocation.extra_queue_pg_num = 0;
+
+	pHalmac_adapter->txff_allocation.la_mode = HALMAC_LA_MODE_DISABLE;
+    pHalmac_adapter->txff_allocation.rx_fifo_expanding_mode = HALMAC_RX_FIFO_EXPANDING_MODE_DISABLE;
+
+	pHalmac_adapter->sdio_cmd53_4byte = HALMAC_SDIO_CMD53_4BYTE_MODE_DISABLE;
+	pHalmac_adapter->sdio_hw_info.io_hi_speed_flag = 0;
+	pHalmac_adapter->sdio_hw_info.spec_ver = HALMAC_SDIO_SPEC_VER_2_00;
+	pHalmac_adapter->sdio_hw_info.clock_speed = 50;
+
+	halmac_init_adapter_dynamic_para_88xx(pHalmac_adapter);
+	halmac_init_state_machine_88xx(pHalmac_adapter);
+
+}
+
+/**
+ * halmac_init_adapter_dynamic_para_88xx() - int halmac adapter
+ * @pHalmac_adapter
+ *
+ * SD1 internal use
+ *
+ * Author : KaiYuan Chang/Ivan Lin
+ * Return : VOID
+ */
+VOID
+halmac_init_adapter_dynamic_para_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter
+)
+{
+	pHalmac_adapter->h2c_packet_seq = 0;
+	pHalmac_adapter->h2c_buf_free_space = 0;
+	pHalmac_adapter->gen_info_valid = _FALSE;
+}
+
+/**
+ * halmac_init_state_machine_88xx() - init halmac software state machine
+ * @pHalmac_adapter
+ *
+ * SD1 internal use.
+ *
+ * Author : KaiYuan Chang/Ivan Lin
+ * Return : VOID
+ */
+VOID
+halmac_init_state_machine_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter
+)
+{
+	PHALMAC_STATE pState = &(pHalmac_adapter->halmac_state);
+
+	halmac_init_offload_feature_state_machine_88xx(pHalmac_adapter);
+
+	pState->api_state = HALMAC_API_STATE_INIT;
+
+	pState->dlfw_state = HALMAC_DLFW_NONE;
+	pState->mac_power = HALMAC_MAC_POWER_OFF;
+	pState->ps_state = HALMAC_PS_STATE_UNDEFINE;
+}
+
+/**
+ * halmac_mount_api_88xx() - attach functions to function pointer
+ * @pHalmac_adapter
+ *
+ * SD1 internal use
+ *
+ * Author : KaiYuan Chang/Ivan Lin
+ * Return : HALMAC_RET_STATUS
+ */
+HALMAC_RET_STATUS
+halmac_mount_api_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter
+)
+{
+	VOID *pDriver_adapter = pHalmac_adapter->pDriver_adapter;
+	PHALMAC_API pHalmac_api = (PHALMAC_API)NULL;
+
+	pHalmac_adapter->pHalmac_api = (PHALMAC_API)PLATFORM_RTL_MALLOC(pDriver_adapter, sizeof(HALMAC_API));
+	if (NULL == pHalmac_adapter->pHalmac_api)
+		return HALMAC_RET_MALLOC_FAIL;
+	pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api;
+
+	PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ALWAYS, HALMAC_SVN_VER_88XX"\n");
+	PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ALWAYS, "HALMAC_MAJOR_VER_88XX = %x\n", HALMAC_MAJOR_VER_88XX);
+	PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ALWAYS, "HALMAC_PROTOTYPE_88XX = %x\n", HALMAC_PROTOTYPE_VER_88XX);
+	PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ALWAYS, "HALMAC_MINOR_VER_88XX = %x\n", HALMAC_MINOR_VER_88XX);
+	PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ALWAYS, "HALMAC_PATCH_VER_88XX = %x\n", HALMAC_PATCH_VER_88XX);
+
+	/* Mount function pointer */
+	pHalmac_api->halmac_download_firmware = halmac_download_firmware_88xx;
+	pHalmac_api->halmac_free_download_firmware = halmac_free_download_firmware_88xx;
+	pHalmac_api->halmac_get_fw_version = halmac_get_fw_version_88xx;
+	pHalmac_api->halmac_cfg_mac_addr = halmac_cfg_mac_addr_88xx;
+	pHalmac_api->halmac_cfg_bssid = halmac_cfg_bssid_88xx;
+	pHalmac_api->halmac_cfg_multicast_addr = halmac_cfg_multicast_addr_88xx;
+	pHalmac_api->halmac_pre_init_system_cfg = halmac_pre_init_system_cfg_88xx;
+	pHalmac_api->halmac_init_system_cfg = halmac_init_system_cfg_88xx;
+	pHalmac_api->halmac_init_edca_cfg = halmac_init_edca_cfg_88xx;
+	pHalmac_api->halmac_cfg_operation_mode = halmac_cfg_operation_mode_88xx;
+	pHalmac_api->halmac_cfg_ch_bw = halmac_cfg_ch_bw_88xx;
+	pHalmac_api->halmac_cfg_bw = halmac_cfg_bw_88xx;
+	pHalmac_api->halmac_init_wmac_cfg = halmac_init_wmac_cfg_88xx;
+	pHalmac_api->halmac_init_mac_cfg = halmac_init_mac_cfg_88xx;
+	pHalmac_api->halmac_init_sdio_cfg = halmac_init_sdio_cfg_88xx;
+	pHalmac_api->halmac_init_usb_cfg = halmac_init_usb_cfg_88xx;
+	pHalmac_api->halmac_init_pcie_cfg = halmac_init_pcie_cfg_88xx;
+	pHalmac_api->halmac_deinit_sdio_cfg = halmac_deinit_sdio_cfg_88xx;
+	pHalmac_api->halmac_deinit_usb_cfg = halmac_deinit_usb_cfg_88xx;
+	pHalmac_api->halmac_deinit_pcie_cfg = halmac_deinit_pcie_cfg_88xx;
+	pHalmac_api->halmac_dump_efuse_map = halmac_dump_efuse_map_88xx;
+	pHalmac_api->halmac_dump_efuse_map_bt = halmac_dump_efuse_map_bt_88xx;
+	pHalmac_api->halmac_write_efuse_bt = halmac_write_efuse_bt_88xx;
+	pHalmac_api->halmac_dump_logical_efuse_map = halmac_dump_logical_efuse_map_88xx;
+	pHalmac_api->halmac_pg_efuse_by_map = halmac_pg_efuse_by_map_88xx;
+	pHalmac_api->halmac_get_efuse_size = halmac_get_efuse_size_88xx;
+	pHalmac_api->halmac_get_efuse_available_size = halmac_get_efuse_available_size_88xx;
+	pHalmac_api->halmac_get_c2h_info = halmac_get_c2h_info_88xx;
+
+	pHalmac_api->halmac_get_logical_efuse_size = halmac_get_logical_efuse_size_88xx;
+
+	pHalmac_api->halmac_write_logical_efuse = halmac_write_logical_efuse_88xx;
+	pHalmac_api->halmac_read_logical_efuse = halmac_read_logical_efuse_88xx;
+
+	pHalmac_api->halmac_cfg_fwlps_option = halmac_cfg_fwlps_option_88xx;
+	pHalmac_api->halmac_cfg_fwips_option = halmac_cfg_fwips_option_88xx;
+	pHalmac_api->halmac_enter_wowlan = halmac_enter_wowlan_88xx;
+	pHalmac_api->halmac_leave_wowlan = halmac_leave_wowlan_88xx;
+	pHalmac_api->halmac_enter_ps = halmac_enter_ps_88xx;
+	pHalmac_api->halmac_leave_ps = halmac_leave_ps_88xx;
+	pHalmac_api->halmac_h2c_lb = halmac_h2c_lb_88xx;
+	pHalmac_api->halmac_debug = halmac_debug_88xx;
+	pHalmac_api->halmac_cfg_parameter = halmac_cfg_parameter_88xx;
+	pHalmac_api->halmac_update_datapack = halmac_update_datapack_88xx;
+	pHalmac_api->halmac_run_datapack = halmac_run_datapack_88xx;
+	pHalmac_api->halmac_cfg_drv_info = halmac_cfg_drv_info_88xx;
+	pHalmac_api->halmac_send_bt_coex = halmac_send_bt_coex_88xx;
+	pHalmac_api->halmac_verify_platform_api = halmac_verify_platform_api_88xx;
+	pHalmac_api->halmac_update_packet = halmac_update_packet_88xx;
+	pHalmac_api->halmac_bcn_ie_filter = halmac_bcn_ie_filter_88xx;
+	pHalmac_api->halmac_cfg_txbf = halmac_cfg_txbf_88xx;
+	pHalmac_api->halmac_cfg_mumimo = halmac_cfg_mumimo_88xx;
+	pHalmac_api->halmac_cfg_sounding = halmac_cfg_sounding_88xx;
+	pHalmac_api->halmac_del_sounding = halmac_del_sounding_88xx;
+	pHalmac_api->halmac_su_bfer_entry_init = halmac_su_bfer_entry_init_88xx;
+	pHalmac_api->halmac_su_bfee_entry_init = halmac_su_bfee_entry_init_88xx;
+	pHalmac_api->halmac_mu_bfer_entry_init = halmac_mu_bfer_entry_init_88xx;
+	pHalmac_api->halmac_mu_bfee_entry_init = halmac_mu_bfee_entry_init_88xx;
+	pHalmac_api->halmac_su_bfer_entry_del = halmac_su_bfer_entry_del_88xx;
+	pHalmac_api->halmac_su_bfee_entry_del = halmac_su_bfee_entry_del_88xx;
+	pHalmac_api->halmac_mu_bfer_entry_del = halmac_mu_bfer_entry_del_88xx;
+	pHalmac_api->halmac_mu_bfee_entry_del = halmac_mu_bfee_entry_del_88xx;
+
+	pHalmac_api->halmac_add_ch_info = halmac_add_ch_info_88xx;
+	pHalmac_api->halmac_add_extra_ch_info = halmac_add_extra_ch_info_88xx;
+	pHalmac_api->halmac_ctrl_ch_switch = halmac_ctrl_ch_switch_88xx;
+	pHalmac_api->halmac_p2pps = halmac_p2pps_88xx;
+	pHalmac_api->halmac_clear_ch_info = halmac_clear_ch_info_88xx;
+	pHalmac_api->halmac_send_general_info = halmac_send_general_info_88xx;
+
+	pHalmac_api->halmac_start_iqk = halmac_start_iqk_88xx;
+	pHalmac_api->halmac_ctrl_pwr_tracking = halmac_ctrl_pwr_tracking_88xx;
+	pHalmac_api->halmac_psd = halmac_psd_88xx;
+	pHalmac_api->halmac_cfg_la_mode = halmac_cfg_la_mode_88xx;
+    pHalmac_api->halmac_cfg_rx_fifo_expanding_mode = halmac_cfg_rx_fifo_expanding_mode_88xx;
+
+	pHalmac_api->halmac_config_security = halmac_config_security_88xx;
+	pHalmac_api->halmac_get_used_cam_entry_num = halmac_get_used_cam_entry_num_88xx;
+	pHalmac_api->halmac_read_cam_entry = halmac_read_cam_entry_88xx;
+	pHalmac_api->halmac_write_cam = halmac_write_cam_88xx;
+	pHalmac_api->halmac_clear_cam_entry = halmac_clear_cam_entry_88xx;
+
+	pHalmac_api->halmac_get_hw_value = halmac_get_hw_value_88xx;
+	pHalmac_api->halmac_set_hw_value = halmac_set_hw_value_88xx;
+
+	pHalmac_api->halmac_cfg_drv_rsvd_pg_num = halmac_cfg_drv_rsvd_pg_num_88xx;
+	pHalmac_api->halmac_get_chip_version = halmac_get_chip_version_88xx;
+
+	pHalmac_api->halmac_query_status = halmac_query_status_88xx;
+	pHalmac_api->halmac_reset_feature = halmac_reset_feature_88xx;
+	pHalmac_api->halmac_check_fw_status = halmac_check_fw_status_88xx;
+	pHalmac_api->halmac_dump_fw_dmem = halmac_dump_fw_dmem_88xx;
+	pHalmac_api->halmac_cfg_max_dl_size = halmac_cfg_max_dl_size_88xx;
+
+	pHalmac_api->halmac_dump_fifo = halmac_dump_fifo_88xx;
+	pHalmac_api->halmac_get_fifo_size = halmac_get_fifo_size_88xx;
+
+	pHalmac_api->halmac_chk_txdesc = halmac_chk_txdesc_88xx;
+	pHalmac_api->halmac_dl_drv_rsvd_page = halmac_dl_drv_rsvd_page_88xx;
+	pHalmac_api->halmac_cfg_csi_rate = halmac_cfg_csi_rate_88xx;
+
+	pHalmac_api->halmac_sdio_cmd53_4byte = halmac_sdio_cmd53_4byte_88xx;
+	pHalmac_api->halmac_sdio_hw_info = halmac_sdio_hw_info_88xx;
+	pHalmac_api->halmac_txfifo_is_empty = halmac_txfifo_is_empty_88xx;
+
+	if (HALMAC_INTERFACE_SDIO == pHalmac_adapter->halmac_interface) {
+		pHalmac_api->halmac_cfg_rx_aggregation = halmac_cfg_rx_aggregation_88xx_sdio;
+		pHalmac_api->halmac_init_interface_cfg = halmac_init_sdio_cfg_88xx;
+		pHalmac_api->halmac_deinit_interface_cfg = halmac_deinit_sdio_cfg_88xx;
+		pHalmac_api->halmac_reg_read_8 = halmac_reg_read_8_sdio_88xx;
+		pHalmac_api->halmac_reg_write_8 = halmac_reg_write_8_sdio_88xx;
+		pHalmac_api->halmac_reg_read_16 = halmac_reg_read_16_sdio_88xx;
+		pHalmac_api->halmac_reg_write_16 = halmac_reg_write_16_sdio_88xx;
+		pHalmac_api->halmac_reg_read_32 = halmac_reg_read_32_sdio_88xx;
+		pHalmac_api->halmac_reg_write_32 = halmac_reg_write_32_sdio_88xx;
+		pHalmac_api->halmac_reg_read_indirect_32 = halmac_reg_read_indirect_32_sdio_88xx;
+		pHalmac_api->halmac_reg_sdio_cmd53_read_n = halmac_reg_read_nbyte_sdio_88xx;
+	} else if (HALMAC_INTERFACE_USB == pHalmac_adapter->halmac_interface) {
+		pHalmac_api->halmac_cfg_rx_aggregation = halmac_cfg_rx_aggregation_88xx_usb;
+		pHalmac_api->halmac_init_interface_cfg = halmac_init_usb_cfg_88xx;
+		pHalmac_api->halmac_deinit_interface_cfg = halmac_deinit_usb_cfg_88xx;
+		pHalmac_api->halmac_reg_read_8 = halmac_reg_read_8_usb_88xx;
+		pHalmac_api->halmac_reg_write_8 = halmac_reg_write_8_usb_88xx;
+		pHalmac_api->halmac_reg_read_16 = halmac_reg_read_16_usb_88xx;
+		pHalmac_api->halmac_reg_write_16 = halmac_reg_write_16_usb_88xx;
+		pHalmac_api->halmac_reg_read_32 = halmac_reg_read_32_usb_88xx;
+		pHalmac_api->halmac_reg_write_32 = halmac_reg_write_32_usb_88xx;
+	} else if (HALMAC_INTERFACE_PCIE == pHalmac_adapter->halmac_interface) {
+		pHalmac_api->halmac_cfg_rx_aggregation = halmac_cfg_rx_aggregation_88xx_pcie;
+		pHalmac_api->halmac_init_interface_cfg = halmac_init_pcie_cfg_88xx;
+		pHalmac_api->halmac_deinit_interface_cfg = halmac_deinit_pcie_cfg_88xx;
+		pHalmac_api->halmac_reg_read_8 = halmac_reg_read_8_pcie_88xx;
+		pHalmac_api->halmac_reg_write_8 = halmac_reg_write_8_pcie_88xx;
+		pHalmac_api->halmac_reg_read_16 = halmac_reg_read_16_pcie_88xx;
+		pHalmac_api->halmac_reg_write_16 = halmac_reg_write_16_pcie_88xx;
+		pHalmac_api->halmac_reg_read_32 = halmac_reg_read_32_pcie_88xx;
+		pHalmac_api->halmac_reg_write_32 = halmac_reg_write_32_pcie_88xx;
+	} else {
+		PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "Set halmac io function Error!!\n");
+	}
+
+	pHalmac_api->halmac_set_bulkout_num = halmac_set_bulkout_num_88xx;
+	pHalmac_api->halmac_get_sdio_tx_addr = halmac_get_sdio_tx_addr_88xx;
+	pHalmac_api->halmac_get_usb_bulkout_id = halmac_get_usb_bulkout_id_88xx;
+	pHalmac_api->halmac_timer_2s = halmac_timer_2s_88xx;
+	pHalmac_api->halmac_fill_txdesc_checksum = halmac_fill_txdesc_check_sum_88xx;
+
+
+	if (HALMAC_CHIP_ID_8822B == pHalmac_adapter->chip_id) {
+#if HALMAC_8822B_SUPPORT
+		/*mount 8822b function and data*/
+		halmac_mount_api_8822b(pHalmac_adapter);
+#endif
+
+	} else if (HALMAC_CHIP_ID_8821C == pHalmac_adapter->chip_id) {
+#if HALMAC_8821C_SUPPORT
+		/*mount 8822b function and data*/
+		halmac_mount_api_8821c(pHalmac_adapter);
+#endif
+	} else {
+		PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "Chip ID undefine!!\n");
+		return HALMAC_RET_CHIP_NOT_SUPPORT;
+	}
+#if HALMAC_PLATFORM_TESTPROGRAM
+	pHalmac_api->halmac_write_efuse = halmac_write_efuse_88xx;
+	pHalmac_api->halmac_read_efuse = halmac_read_efuse_88xx;
+	pHalmac_api->halmac_switch_efuse_bank = halmac_switch_efuse_bank_88xx;
+
+	pHalmac_api->halmac_gen_txdesc = halmac_gen_tx_desc_88xx;
+	pHalmac_api->halmac_txdesc_parser = halmac_tx_desc_parser_88xx;
+	pHalmac_api->halmac_rxdesc_parser = halmac_rx_desc_parser_88xx;
+	pHalmac_api->halmac_get_txdesc_size = halmac_get_txdesc_size_88xx;
+	pHalmac_api->halmac_send_packet = halmac_send_packet_88xx;
+	pHalmac_api->halmac_parse_packet = halmac_parse_packet_88xx;
+
+	pHalmac_api->halmac_get_pcie_packet = halmac_get_pcie_packet_88xx;
+	pHalmac_api->halmac_gen_txagg_desc = halmac_gen_txagg_desc_88xx;
+
+	pHalmac_api->halmac_bb_reg_read = halmac_bb_reg_read_88xx;
+	pHalmac_api->halmac_bb_reg_write = halmac_bb_reg_write_88xx;
+
+	pHalmac_api->halmac_rf_reg_read = halmac_rf_ac_reg_read_88xx;
+	pHalmac_api->halmac_rf_reg_write = halmac_rf_ac_reg_write_88xx;
+	pHalmac_api->halmac_init_antenna_selection = halmac_init_antenna_selection_88xx;
+	pHalmac_api->halmac_bb_preconfig = halmac_bb_preconfig_88xx;
+	pHalmac_api->halmac_init_crystal_capacity = halmac_init_crystal_capacity_88xx;
+	pHalmac_api->halmac_trx_antenna_setting = halmac_trx_antenna_setting_88xx;
+
+	pHalmac_api->halmac_himr_setting_sdio = halmac_himr_setting_88xx_sdio;
+
+	pHalmac_api->halmac_send_beacon = halmac_send_beacon_88xx;
+	pHalmac_api->halmac_stop_beacon = halmac_stop_beacon_88xx;
+	pHalmac_api->halmac_check_trx_status = halmac_check_trx_status_88xx;
+	pHalmac_api->halmac_set_agg_num = halmac_set_agg_num_88xx;
+	pHalmac_api->halmac_get_management_txdesc = halmac_get_management_txdesc_88xx;
+	pHalmac_api->halmac_send_control = halmac_send_control_88xx;
+	pHalmac_api->halmac_send_hiqueue = halmac_send_hiqueue_88xx;
+	pHalmac_api->halmac_media_status_rpt = halmac_media_status_rpt_88xx;
+
+	pHalmac_api->halmac_timer_10ms = halmac_timer_10ms_88xx;
+
+	pHalmac_api->halmac_download_firmware_fpag = halmac_download_firmware_fpga_88xx;
+	pHalmac_api->halmac_download_rom_fpga = halmac_download_rom_fpga_88xx;
+	pHalmac_api->halmac_download_flash = halmac_download_flash_88xx;
+	pHalmac_api->halmac_erase_flash = halmac_erase_flash_88xx;
+	pHalmac_api->halmac_check_flash = halmac_check_flash_88xx;
+	pHalmac_api->halmac_send_nlo = halmac_send_nlo_88xx;
+
+	pHalmac_api->halmac_dump_cam_table = halmac_dump_cam_table_88xx;
+	pHalmac_api->halmac_load_cam_table = halmac_load_cam_table_88xx;
+
+	pHalmac_api->halmac_get_chip_type = halmac_get_chip_type_88xx;
+
+	pHalmac_api->halmac_get_rx_agg_num = halmac_get_rx_agg_num_88xx;
+	pHalmac_api->halmac_check_rx_scsi_resp = halmac_check_rx_scsi_resp_88xx_usb;
+
+	pHalmac_api->halmac_get_hcpwm = halmac_get_hcpwm_88xx;
+	pHalmac_api->halmac_get_hcpwm2 = halmac_get_hcpwm2_88xx;
+	pHalmac_api->halmac_set_hrpwm = halmac_set_hrpwm_88xx;
+	pHalmac_api->halmac_set_hrpwm2 = halmac_set_hrpwm2_88xx;
+#if HALMAC_8822B_SUPPORT
+	if (pHalmac_adapter->chip_id == HALMAC_CHIP_ID_8822B)
+		pHalmac_api->halmac_run_pwrseq = halmac_run_pwrseq_8822b;
+#endif
+#if HALMAC_8821C_SUPPORT
+	if (pHalmac_adapter->chip_id == HALMAC_CHIP_ID_8821C)
+		pHalmac_api->halmac_run_pwrseq = halmac_run_pwrseq_8821c;
+#endif
+	if (HALMAC_INTERFACE_SDIO == pHalmac_adapter->halmac_interface) {
+		pHalmac_api->halmac_reg_read_8 = halmac_reg_read_8_sdio_88xx;
+		pHalmac_api->halmac_reg_write_8 = halmac_reg_write_8_sdio_88xx;
+		pHalmac_api->halmac_reg_read_16 = halmac_reg_read_16_sdio_88xx;
+		pHalmac_api->halmac_reg_write_16 = halmac_reg_write_16_sdio_88xx;
+		pHalmac_api->halmac_reg_read_32 = halmac_reg_read_32_sdio_88xx;
+		pHalmac_api->halmac_reg_write_32 = halmac_reg_write_32_sdio_88xx;
+	}
+#endif
+	return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * halmac_download_firmware_88xx() - download Firmware
+ * @pHalmac_adapter : the adapter of halmac
+ * @pHamacl_fw : firmware bin
+ * @halmac_fw_size : firmware size
+ * Author : KaiYuan Chang/Ivan Lin
+ * Return : HALMAC_RET_STATUS
+ * More details of status code can be found in prototype document
+ */
+HALMAC_RET_STATUS
+halmac_download_firmware_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN u8 *pHamacl_fw,
+	IN u32 halmac_fw_size
+)
+{
+	u8 value8;
+	u8 *pFile_ptr;
+	u16 value16;
+	u32 restore_index = 0;
+	u32 halmac_h2c_ver = 0, fw_h2c_ver = 0;
+	u32 iram_pkt_size, dmem_pkt_size, eram_pkt_size = 0;
+	VOID *pDriver_adapter = NULL;
+	PHALMAC_API pHalmac_api;
+	HALMAC_RESTORE_INFO restore_info[DLFW_RESTORE_REG_NUM_88XX];
+
+	if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter))
+		return HALMAC_RET_ADAPTER_INVALID;
+
+	if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter))
+		return HALMAC_RET_API_INVALID;
+
+	halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_DOWNLOAD_FIRMWARE);
+
+	pDriver_adapter = pHalmac_adapter->pDriver_adapter;
+	pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api;
+
+	PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_download_firmware_88xx ==========>\n");
+	PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_download_firmware_88xx start!!\n");
+
+	if (halmac_fw_size > HALMAC_FW_SIZE_MAX_88XX || halmac_fw_size < HALMAC_FWHDR_SIZE_88XX) {
+		PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "FW size error!\n");
+		return HALMAC_RET_FW_SIZE_ERR;
+	}
+
+	fw_h2c_ver = rtk_le32_to_cpu(*((u32 *)(pHamacl_fw + HALMAC_FWHDR_OFFSET_H2C_FORMAT_VER_88XX)));
+	halmac_h2c_ver = H2C_FORMAT_VERSION;
+	PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac h2c/c2h format = %x, fw h2c/c2h format = %x!!\n", halmac_h2c_ver, fw_h2c_ver);
+	if (fw_h2c_ver != halmac_h2c_ver)
+		PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_WARN, "[WARN]H2C/C2H version between HALMAC and FW is compatible!!\n");
+
+	pHalmac_adapter->halmac_state.dlfw_state = HALMAC_DLFW_NONE;
+
+	value8 = HALMAC_REG_READ_8(pHalmac_adapter, REG_SYS_FUNC_EN + 1);
+	value8 = (u8)(value8 & ~(BIT(2)));
+	HALMAC_REG_WRITE_8(pHalmac_adapter, REG_SYS_FUNC_EN + 1, value8); /* Disable CPU reset */
+
+	value8 = HALMAC_REG_READ_8(pHalmac_adapter, REG_RSV_CTRL + 1);
+	value8 = (u8)(value8 & ~(BIT(0)));
+	HALMAC_REG_WRITE_8(pHalmac_adapter, REG_RSV_CTRL + 1, value8);
+
+	restore_info[restore_index].length = 1;
+	restore_info[restore_index].mac_register = REG_TXDMA_PQ_MAP + 1;
+	restore_info[restore_index].value = HALMAC_REG_READ_8(pHalmac_adapter, REG_TXDMA_PQ_MAP + 1);
+	restore_index++;
+	value8 = HALMAC_DMA_MAPPING_HIGH << 6;
+	HALMAC_REG_WRITE_8(pHalmac_adapter, REG_TXDMA_PQ_MAP + 1, value8);  /* set HIQ to hi priority */
+
+	/* DLFW only use HIQ, map HIQ to hi priority */
+	pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_HI] = HALMAC_DMA_MAPPING_HIGH;
+	restore_info[restore_index].length = 1;
+	restore_info[restore_index].mac_register = REG_CR;
+	restore_info[restore_index].value = HALMAC_REG_READ_8(pHalmac_adapter, REG_CR);
+	restore_index++;
+	restore_info[restore_index].length = 4;
+	restore_info[restore_index].mac_register = REG_H2CQ_CSR;
+	restore_info[restore_index].value = BIT(31);
+	restore_index++;
+	value8 = BIT_HCI_TXDMA_EN | BIT_TXDMA_EN;
+	HALMAC_REG_WRITE_8(pHalmac_adapter, REG_CR, value8);
+	HALMAC_REG_WRITE_32(pHalmac_adapter, REG_H2CQ_CSR, BIT(31));
+
+	/* Config hi priority queue and public priority queue page number (only for DLFW) */
+	restore_info[restore_index].length = 2;
+	restore_info[restore_index].mac_register = REG_FIFOPAGE_INFO_1;
+	restore_info[restore_index].value = HALMAC_REG_READ_16(pHalmac_adapter, REG_FIFOPAGE_INFO_1);
+	restore_index++;
+	restore_info[restore_index].length = 4;
+	restore_info[restore_index].mac_register = REG_RQPN_CTRL_2;
+	restore_info[restore_index].value = HALMAC_REG_READ_32(pHalmac_adapter, REG_RQPN_CTRL_2) | BIT(31);
+	restore_index++;
+	HALMAC_REG_WRITE_16(pHalmac_adapter, REG_FIFOPAGE_INFO_1, 0x200);
+	HALMAC_REG_WRITE_32(pHalmac_adapter, REG_RQPN_CTRL_2, restore_info[restore_index - 1].value);
+
+	if (HALMAC_INTERFACE_SDIO == pHalmac_adapter->halmac_interface) {
+		HALMAC_REG_READ_32(pHalmac_adapter, REG_SDIO_FREE_TXPG);
+		HALMAC_REG_WRITE_32(pHalmac_adapter, REG_SDIO_TX_CTRL, 0x00000000);
+	}
+
+	halmac_update_fw_info_88xx(pHalmac_adapter, pHamacl_fw, halmac_fw_size);
+
+	dmem_pkt_size = *((u32 *)(pHamacl_fw + HALMAC_FWHDR_OFFSET_DMEM_SIZE_88XX));
+	iram_pkt_size = *((u32 *)(pHamacl_fw + HALMAC_FWHDR_OFFSET_IRAM_SIZE_88XX));
+	if (0 != ((*(pHamacl_fw + HALMAC_FWHDR_OFFSET_MEM_USAGE_88XX)) & BIT(4)))
+		eram_pkt_size = *((u32 *)(pHamacl_fw + HALMAC_FWHDR_OFFSET_ERAM_SIZE_88XX));
+
+	dmem_pkt_size = rtk_le32_to_cpu(dmem_pkt_size);
+	iram_pkt_size = rtk_le32_to_cpu(iram_pkt_size);
+	eram_pkt_size = rtk_le32_to_cpu(eram_pkt_size);
+
+	dmem_pkt_size += HALMAC_FW_CHKSUM_DUMMY_SIZE_88XX;
+	iram_pkt_size += HALMAC_FW_CHKSUM_DUMMY_SIZE_88XX;
+	if (0 != eram_pkt_size)
+		eram_pkt_size += HALMAC_FW_CHKSUM_DUMMY_SIZE_88XX;
+
+	if (halmac_fw_size != (HALMAC_FWHDR_SIZE_88XX + dmem_pkt_size + iram_pkt_size + eram_pkt_size)) {
+		PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "FW size mismatch the real fw size!\n");
+		goto DLFW_FAIL;
+	}
+
+	value8 = HALMAC_REG_READ_8(pHalmac_adapter, REG_CR + 1);
+	restore_info[restore_index].length = 1;
+	restore_info[restore_index].mac_register = REG_CR + 1;
+	restore_info[restore_index].value = value8;
+	restore_index++;
+	value8 = (u8)(value8 | BIT(0));
+	HALMAC_REG_WRITE_8(pHalmac_adapter, REG_CR + 1, value8); /* Enable SW TX beacon */
+
+	value8 = HALMAC_REG_READ_8(pHalmac_adapter, REG_BCN_CTRL);
+	restore_info[restore_index].length = 1;
+	restore_info[restore_index].mac_register = REG_BCN_CTRL;
+	restore_info[restore_index].value = value8;
+	restore_index++;
+	value8 = (u8)((value8 & (~BIT(3))) | BIT(4));
+	HALMAC_REG_WRITE_8(pHalmac_adapter, REG_BCN_CTRL, value8); /* Disable beacon related functions */
+
+	value8 = HALMAC_REG_READ_8(pHalmac_adapter, REG_FWHW_TXQ_CTRL + 2);
+	restore_info[restore_index].length = 1;
+	restore_info[restore_index].mac_register = REG_FWHW_TXQ_CTRL + 2;
+	restore_info[restore_index].value = value8;
+	restore_index++;
+	value8 = (u8)(value8 & ~(BIT(6)));
+	HALMAC_REG_WRITE_8(pHalmac_adapter, REG_FWHW_TXQ_CTRL + 2, value8); /* Disable ptcl tx bcnq */
+
+	restore_info[restore_index].length = 2;
+	restore_info[restore_index].mac_register = REG_FIFOPAGE_CTRL_2;
+	restore_info[restore_index].value = HALMAC_REG_READ_16(pHalmac_adapter, REG_FIFOPAGE_CTRL_2) | BIT(15);
+	restore_index++;
+	value16 = 0x8000;
+	HALMAC_REG_WRITE_16(pHalmac_adapter, REG_FIFOPAGE_CTRL_2, value16); /* Set beacon header to  0 */
+
+	value16 = (u16)(HALMAC_REG_READ_16(pHalmac_adapter, REG_MCUFW_CTRL) & 0x3800);
+	value16 |= BIT(0);
+	HALMAC_REG_WRITE_16(pHalmac_adapter, REG_MCUFW_CTRL, value16); /* MCU/FW setting */
+
+	value8 = HALMAC_REG_READ_8(pHalmac_adapter, REG_CPU_DMEM_CON + 2);
+	value8 &= ~(BIT(0));
+	HALMAC_REG_WRITE_8(pHalmac_adapter, REG_CPU_DMEM_CON + 2, value8);
+	value8 |= BIT(0);
+	HALMAC_REG_WRITE_8(pHalmac_adapter, REG_CPU_DMEM_CON + 2, value8);
+
+	/* Download to DMEM */
+	pFile_ptr = pHamacl_fw + HALMAC_FWHDR_SIZE_88XX;
+	/* if (HALMAC_RET_SUCCESS != halmac_dlfw_to_mem_88xx(pHalmac_adapter, pFile_ptr, HALMAC_OCPBASE_DMEM_88XX, dmem_pkt_size)) */
+	if (HALMAC_RET_SUCCESS != halmac_dlfw_to_mem_88xx(pHalmac_adapter, pFile_ptr,
+		    rtk_le32_to_cpu(*((u32 *)(pHamacl_fw + HALMAC_FWHDR_OFFSET_DMEM_ADDR_88XX))) & ~(BIT(31)), dmem_pkt_size))
+		goto DLFW_END;
+
+	/* Download to IMEM */
+	pFile_ptr = pHamacl_fw + HALMAC_FWHDR_SIZE_88XX + dmem_pkt_size;
+	/* if (HALMAC_RET_SUCCESS != halmac_dlfw_to_mem_88xx(pHalmac_adapter, pFile_ptr, HALMAC_OCPBASE_IMEM_88XX, iram_pkt_size)) */
+	if (HALMAC_RET_SUCCESS != halmac_dlfw_to_mem_88xx(pHalmac_adapter, pFile_ptr,
+		    rtk_le32_to_cpu(*((u32 *)(pHamacl_fw + HALMAC_FWHDR_OFFSET_IRAM_ADDR_88XX))) & ~(BIT(31)), iram_pkt_size))
+		goto DLFW_END;
+
+	/* Download to EMEM */
+	if (0 != eram_pkt_size) {
+		pFile_ptr = pHamacl_fw + HALMAC_FWHDR_SIZE_88XX + dmem_pkt_size + iram_pkt_size;
+		if (HALMAC_RET_SUCCESS != halmac_dlfw_to_mem_88xx(pHalmac_adapter, pFile_ptr,
+			    rtk_le32_to_cpu(*((u32 *)(pHamacl_fw + HALMAC_FWHDR_OFFSET_EMEM_ADDR_88XX))) & ~(BIT(31)), eram_pkt_size))
+			goto DLFW_END;
+	}
+
+	halmac_init_offload_feature_state_machine_88xx(pHalmac_adapter);
+DLFW_END:
+
+	halmac_restore_mac_register_88xx(pHalmac_adapter, restore_info, DLFW_RESTORE_REG_NUM_88XX);
+
+	if (HALMAC_RET_SUCCESS != halmac_dlfw_end_flow_88xx(pHalmac_adapter))
+		goto DLFW_FAIL;
+
+	pHalmac_adapter->halmac_state.dlfw_state = HALMAC_DLFW_DONE;
+
+	PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_download_firmware_88xx <==========\n");
+
+	return HALMAC_RET_SUCCESS;
+
+DLFW_FAIL:
+
+	/* Disable FWDL_EN */
+	HALMAC_REG_WRITE_8(pHalmac_adapter, REG_MCUFW_CTRL, (u8)(HALMAC_REG_READ_8(pHalmac_adapter, REG_MCUFW_CTRL) & ~(BIT(0))));
+
+	return HALMAC_RET_DLFW_FAIL;
+}
+
+/**
+ * halmac_free_download_firmware_88xx() - download specific memory firmware
+ * @pHalmac_adapter
+ * @dlfw_mem : memory selection
+ * @pHamacl_fw : firmware bin
+ * @halmac_fw_size : firmware size
+ * Author : KaiYuan Chang/Ivan Lin
+ * Return : HALMAC_RET_STATUS
+ */
+HALMAC_RET_STATUS
+halmac_free_download_firmware_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN HALMAC_DLFW_MEM dlfw_mem,
+	IN u8 *pHamacl_fw,
+	IN u32 halmac_fw_size
+)
+{
+	u8 tx_pause_backup;
+	u8 *pFile_ptr;
+	u16 bcn_head_backup;
+	u32 iram_pkt_size, dmem_pkt_size, eram_pkt_size = 0;
+	VOID *pDriver_adapter = NULL;
+	HALMAC_RET_STATUS status = HALMAC_RET_DLFW_FAIL;
+	PHALMAC_API pHalmac_api;
+
+	if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter))
+		return HALMAC_RET_ADAPTER_INVALID;
+
+	if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter))
+		return HALMAC_RET_API_INVALID;
+
+	if (HALMAC_RET_SUCCESS != halmac_fw_validate(pHalmac_adapter))
+		return HALMAC_RET_NO_DLFW;
+
+	pDriver_adapter = pHalmac_adapter->pDriver_adapter;
+	pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api;
+
+	PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "[TRACE]halmac_free_download_firmware_88xx ==========>\n");
+
+	if (halmac_fw_size > HALMAC_FW_SIZE_MAX_88XX || halmac_fw_size < HALMAC_FWHDR_SIZE_88XX) {
+		PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "[ERR]FW size error!\n");
+		return HALMAC_RET_FW_SIZE_ERR;
+	}
+
+	dmem_pkt_size = *((u32 *)(pHamacl_fw + HALMAC_FWHDR_OFFSET_DMEM_SIZE_88XX));
+	iram_pkt_size = *((u32 *)(pHamacl_fw + HALMAC_FWHDR_OFFSET_IRAM_SIZE_88XX));
+	if (0 != ((*(pHamacl_fw + HALMAC_FWHDR_OFFSET_MEM_USAGE_88XX)) & BIT(4)))
+		eram_pkt_size = *((u32 *)(pHamacl_fw + HALMAC_FWHDR_OFFSET_ERAM_SIZE_88XX));
+
+	dmem_pkt_size = rtk_le32_to_cpu(dmem_pkt_size);
+	iram_pkt_size = rtk_le32_to_cpu(iram_pkt_size);
+	eram_pkt_size = rtk_le32_to_cpu(eram_pkt_size);
+
+	dmem_pkt_size += HALMAC_FW_CHKSUM_DUMMY_SIZE_88XX;
+	iram_pkt_size += HALMAC_FW_CHKSUM_DUMMY_SIZE_88XX;
+	if (0 != eram_pkt_size)
+		eram_pkt_size += HALMAC_FW_CHKSUM_DUMMY_SIZE_88XX;
+
+	if (halmac_fw_size != (HALMAC_FWHDR_SIZE_88XX + dmem_pkt_size + iram_pkt_size + eram_pkt_size)) {
+		PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "[ERR]FW size mismatch the real fw size!\n");
+		return HALMAC_RET_DLFW_FAIL;
+	}
+
+	tx_pause_backup = HALMAC_REG_READ_8(pHalmac_adapter, REG_TXPAUSE);
+	HALMAC_REG_WRITE_8(pHalmac_adapter, REG_TXPAUSE, tx_pause_backup | BIT(7));
+
+	bcn_head_backup = HALMAC_REG_READ_16(pHalmac_adapter, REG_FIFOPAGE_CTRL_2) | BIT(15);
+	HALMAC_REG_WRITE_16(pHalmac_adapter, REG_FIFOPAGE_CTRL_2, 0x8000);
+
+	if (0 != eram_pkt_size) {
+		pFile_ptr = pHamacl_fw + HALMAC_FWHDR_SIZE_88XX + dmem_pkt_size + iram_pkt_size;
+		status = halmac_dlfw_to_mem_88xx(pHalmac_adapter, pFile_ptr,
+					rtk_le32_to_cpu(*((u32 *)(pHamacl_fw + HALMAC_FWHDR_OFFSET_EMEM_ADDR_88XX))) & ~(BIT(31)), eram_pkt_size);
+		if (HALMAC_RET_SUCCESS != status)
+			goto DL_FREE_FW_END;
+	}
+
+	status = halmac_free_dl_fw_end_flow_88xx(pHalmac_adapter);
+
+DL_FREE_FW_END:
+	HALMAC_REG_WRITE_8(pHalmac_adapter, REG_TXPAUSE, tx_pause_backup);
+	HALMAC_REG_WRITE_16(pHalmac_adapter, REG_FIFOPAGE_CTRL_2, bcn_head_backup);
+
+	PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "[TRACE]halmac_free_download_firmware_88xx <==========\n");
+
+	return status;
+}
+
+/**
+ * halmac_get_fw_version_88xx() - get FW version
+ * @pHalmac_adapter : the adapter of halmac
+ * @pFw_version : fw version info
+ * Author : Ivan Lin
+ * Return : HALMAC_RET_STATUS
+ * More details of status code can be found in prototype document
+ */
+HALMAC_RET_STATUS
+halmac_get_fw_version_88xx(
+	IN PHALMAC_ADAPTER	pHalmac_adapter,
+	OUT PHALMAC_FW_VERSION	pFw_version
+)
+{
+	PHALMAC_FW_VERSION pFw_info = &(pHalmac_adapter->fw_version);
+
+	if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter))
+		return HALMAC_RET_ADAPTER_INVALID;
+
+	if (pFw_version == NULL)
+		return HALMAC_RET_NULL_POINTER;
+
+	if (pHalmac_adapter->halmac_state.dlfw_state == HALMAC_DLFW_NONE) {
+		return HALMAC_RET_NO_DLFW;
+	} else {
+		pFw_version->version = pFw_info->version;
+		pFw_version->sub_version = pFw_info->sub_version;
+		pFw_version->sub_index = pFw_info->sub_index;
+		pFw_version->h2c_version = pFw_info->h2c_version;
+		pFw_version->build_time.month = pFw_info->build_time.month;
+		pFw_version->build_time.date = pFw_info->build_time.date;
+		pFw_version->build_time.hour = pFw_info->build_time.hour;
+		pFw_version->build_time.min = pFw_info->build_time.min;
+		pFw_version->build_time.year = pFw_info->build_time.year;
+	}
+
+	return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * halmac_cfg_mac_addr_88xx() - config mac address
+ * @pHalmac_adapter : the adapter of halmac
+ * @halmac_port : 0 for port0, 1 for port1, 2 for port2, 3 for port3, 4 for port4
+ * @pHal_address : mac address
+ * Author : KaiYuan Chang/Ivan Lin
+ * Return : HALMAC_RET_STATUS
+ * More details of status code can be found in prototype document
+ */
+HALMAC_RET_STATUS
+halmac_cfg_mac_addr_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN u8 halmac_port,
+	IN PHALMAC_WLAN_ADDR pHal_address
+)
+{
+	u16 mac_address_H;
+	u32 mac_address_L;
+	VOID *pDriver_adapter = NULL;
+	PHALMAC_API pHalmac_api;
+
+	if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter))
+		return HALMAC_RET_ADAPTER_INVALID;
+
+	if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter))
+		return HALMAC_RET_API_INVALID;
+
+	pDriver_adapter = pHalmac_adapter->pDriver_adapter;
+	pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api;
+
+	PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "[TRACE]halmac_cfg_mac_addr_88xx ==========>\n");
+
+	if (halmac_port >= HALMAC_PORTIDMAX) {
+		PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "[ERR]port index > 5\n");
+		return HALMAC_RET_PORT_NOT_SUPPORT;
+	}
+
+	mac_address_L = pHal_address->Address_L_H.Address_Low;
+	mac_address_H = pHal_address->Address_L_H.Address_High;
+
+	mac_address_L = rtk_le32_to_cpu(mac_address_L);
+	mac_address_H = rtk_le16_to_cpu(mac_address_H);
+
+	pHalmac_adapter->pHal_mac_addr[halmac_port].Address_L_H.Address_Low = mac_address_L;
+	pHalmac_adapter->pHal_mac_addr[halmac_port].Address_L_H.Address_High = mac_address_H;
+
+	switch (halmac_port) {
+
+	case HALMAC_PORTID0:
+		HALMAC_REG_WRITE_32(pHalmac_adapter, REG_MACID, mac_address_L);
+		HALMAC_REG_WRITE_16(pHalmac_adapter, REG_MACID + 4, mac_address_H);
+		break;
+
+	case HALMAC_PORTID1:
+		HALMAC_REG_WRITE_32(pHalmac_adapter, REG_MACID1, mac_address_L);
+		HALMAC_REG_WRITE_16(pHalmac_adapter, REG_MACID1 + 4, mac_address_H);
+		break;
+
+	case HALMAC_PORTID2:
+		HALMAC_REG_WRITE_32(pHalmac_adapter, REG_MACID2, mac_address_L);
+		HALMAC_REG_WRITE_16(pHalmac_adapter, REG_MACID2 + 4, mac_address_H);
+		break;
+
+	case HALMAC_PORTID3:
+		HALMAC_REG_WRITE_32(pHalmac_adapter, REG_MACID3, mac_address_L);
+		HALMAC_REG_WRITE_16(pHalmac_adapter, REG_MACID3 + 4, mac_address_H);
+		break;
+
+	case HALMAC_PORTID4:
+		HALMAC_REG_WRITE_32(pHalmac_adapter, REG_MACID4, mac_address_L);
+		HALMAC_REG_WRITE_16(pHalmac_adapter, REG_MACID4 + 4, mac_address_H);
+		break;
+
+	default:
+		break;
+
+	}
+
+	PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "[TRACE]halmac_cfg_mac_addr_88xx <==========\n");
+
+	return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * halmac_cfg_bssid_88xx() - config BSSID
+ * @pHalmac_adapter : the adapter of halmac
+ * @halmac_port : 0 for port0, 1 for port1, 2 for port2, 3 for port3, 4 for port4
+ * @pHal_address : bssid
+ * Author : KaiYuan Chang/Ivan Lin
+ * Return : HALMAC_RET_STATUS
+ * More details of status code can be found in prototype document
+ */
+HALMAC_RET_STATUS
+halmac_cfg_bssid_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN u8 halmac_port,
+	IN PHALMAC_WLAN_ADDR pHal_address
+)
+{
+	u16 bssid_address_H;
+	u32 bssid_address_L;
+	VOID *pDriver_adapter = NULL;
+	PHALMAC_API pHalmac_api;
+
+	if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter))
+		return HALMAC_RET_ADAPTER_INVALID;
+
+	if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter))
+		return HALMAC_RET_API_INVALID;
+
+	pDriver_adapter = pHalmac_adapter->pDriver_adapter;
+	pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api;
+
+	PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "[TRACE]halmac_cfg_bssid_88xx ==========>\n");
+
+	if (halmac_port >= HALMAC_PORTIDMAX) {
+		PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "[ERR]port index > 5\n");
+		return HALMAC_RET_PORT_NOT_SUPPORT;
+	}
+
+	bssid_address_L = pHal_address->Address_L_H.Address_Low;
+	bssid_address_H = pHal_address->Address_L_H.Address_High;
+
+	bssid_address_L = rtk_le32_to_cpu(bssid_address_L);
+	bssid_address_H = rtk_le16_to_cpu(bssid_address_H);
+
+	pHalmac_adapter->pHal_bss_addr[halmac_port].Address_L_H.Address_Low = bssid_address_L;
+	pHalmac_adapter->pHal_bss_addr[halmac_port].Address_L_H.Address_High = bssid_address_H;
+
+	switch (halmac_port) {
+
+	case HALMAC_PORTID0:
+		HALMAC_REG_WRITE_32(pHalmac_adapter, REG_BSSID, bssid_address_L);
+		HALMAC_REG_WRITE_16(pHalmac_adapter, REG_BSSID + 4, bssid_address_H);
+		break;
+
+	case HALMAC_PORTID1:
+		HALMAC_REG_WRITE_32(pHalmac_adapter, REG_BSSID1, bssid_address_L);
+		HALMAC_REG_WRITE_16(pHalmac_adapter, REG_BSSID1 + 4, bssid_address_H);
+		break;
+
+	case HALMAC_PORTID2:
+		HALMAC_REG_WRITE_32(pHalmac_adapter, REG_BSSID2, bssid_address_L);
+		HALMAC_REG_WRITE_16(pHalmac_adapter, REG_BSSID2 + 4, bssid_address_H);
+		break;
+
+	case HALMAC_PORTID3:
+		HALMAC_REG_WRITE_32(pHalmac_adapter, REG_BSSID3, bssid_address_L);
+		HALMAC_REG_WRITE_16(pHalmac_adapter, REG_BSSID3 + 4, bssid_address_H);
+		break;
+
+	case HALMAC_PORTID4:
+		HALMAC_REG_WRITE_32(pHalmac_adapter, REG_BSSID4, bssid_address_L);
+		HALMAC_REG_WRITE_16(pHalmac_adapter, REG_BSSID4 + 4, bssid_address_H);
+		break;
+
+	default:
+		break;
+
+	}
+
+	PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "[TRACE]halmac_cfg_bssid_88xx <==========\n");
+
+	return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * halmac_cfg_multicast_addr_88xx() - config multicast address
+ * @pHalmac_adapter : the adapter of halmac
+ * @pHal_address : multicast address
+ * Author : KaiYuan Chang/Ivan Lin
+ * Return : HALMAC_RET_STATUS
+ * More details of status code can be found in prototype document
+ */
+HALMAC_RET_STATUS
+halmac_cfg_multicast_addr_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN PHALMAC_WLAN_ADDR pHal_address
+)
+{
+	u16 address_H;
+	u32 address_L;
+	VOID *pDriver_adapter = NULL;
+	PHALMAC_API pHalmac_api;
+
+	if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter))
+		return HALMAC_RET_ADAPTER_INVALID;
+
+	if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter))
+		return HALMAC_RET_API_INVALID;
+
+	halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_CFG_MULTICAST_ADDR);
+
+	pDriver_adapter = pHalmac_adapter->pDriver_adapter;
+	pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api;
+
+	PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_cfg_multicast_addr_88xx ==========>\n");
+
+	address_L = pHal_address->Address_L_H.Address_Low;
+	address_H = pHal_address->Address_L_H.Address_High;
+
+	address_L = rtk_le32_to_cpu(address_L);
+	address_H = rtk_le16_to_cpu(address_H);
+
+	HALMAC_REG_WRITE_32(pHalmac_adapter, REG_MAR, address_L);
+	HALMAC_REG_WRITE_16(pHalmac_adapter, REG_MAR + 4, address_H);
+
+	PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_cfg_multicast_addr_88xx <==========\n");
+
+	return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * halmac_pre_init_system_cfg_88xx() - pre-init system config
+ * @pHalmac_adapter : the adapter of halmac
+ * Author : KaiYuan Chang/Ivan Lin
+ * Return : HALMAC_RET_STATUS
+ * More details of status code can be found in prototype document
+ */
+HALMAC_RET_STATUS
+halmac_pre_init_system_cfg_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter
+)
+{
+	u32 value32, counter;
+	VOID *pDriver_adapter = NULL;
+	PHALMAC_API pHalmac_api;
+	u8 enable_bb;
+
+	if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter))
+		return HALMAC_RET_ADAPTER_INVALID;
+
+	if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter))
+		return HALMAC_RET_API_INVALID;
+
+	halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_PRE_INIT_SYSTEM_CFG);
+
+	pDriver_adapter = pHalmac_adapter->pDriver_adapter;
+	pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api;
+
+	PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_pre_init_system_cfg ==========>\n");
+
+	if (HALMAC_INTERFACE_SDIO == pHalmac_adapter->halmac_interface) {
+		HALMAC_REG_WRITE_8(pHalmac_adapter, REG_SDIO_HSUS_CTRL, HALMAC_REG_READ_8(pHalmac_adapter, REG_SDIO_HSUS_CTRL) & ~(BIT(0)));
+		counter = 10000;
+		while (!(HALMAC_REG_READ_8(pHalmac_adapter, REG_SDIO_HSUS_CTRL) & 0x02)) {
+			counter--;
+			if (counter == 0)
+				return HALMAC_RET_SDIO_LEAVE_SUSPEND_FAIL;
+		}
+
+		if (pHalmac_adapter->sdio_hw_info.spec_ver == HALMAC_SDIO_SPEC_VER_3_00)
+			HALMAC_REG_WRITE_8(pHalmac_adapter, REG_HCI_OPT_CTRL + 2, HALMAC_REG_READ_8(pHalmac_adapter, REG_HCI_OPT_CTRL + 2) | BIT(2));
+		else
+			HALMAC_REG_WRITE_8(pHalmac_adapter, REG_HCI_OPT_CTRL + 2, HALMAC_REG_READ_8(pHalmac_adapter, REG_HCI_OPT_CTRL + 2) & ~(BIT(2)));
+	} else if (HALMAC_INTERFACE_USB == pHalmac_adapter->halmac_interface) {
+		if (HALMAC_REG_READ_8(pHalmac_adapter, REG_SYS_CFG2 + 3) == 0x20)	 /* usb3.0 */
+			HALMAC_REG_WRITE_8(pHalmac_adapter, 0xFE5B, HALMAC_REG_READ_8(pHalmac_adapter, 0xFE5B) | BIT(4));
+	}
+
+	/* Config PIN Mux */
+	value32 = HALMAC_REG_READ_32(pHalmac_adapter, REG_PAD_CTRL1);
+	value32 = value32 & (~(BIT(28) | BIT(29)));
+	value32 = value32 | BIT(28) | BIT(29);
+	HALMAC_REG_WRITE_32(pHalmac_adapter, REG_PAD_CTRL1, value32);
+
+	value32 = HALMAC_REG_READ_32(pHalmac_adapter, REG_LED_CFG);
+	value32 = value32 & (~(BIT(25) | BIT(26)));
+	HALMAC_REG_WRITE_32(pHalmac_adapter, REG_LED_CFG, value32);
+
+	value32 = HALMAC_REG_READ_32(pHalmac_adapter, REG_GPIO_MUXCFG);
+	value32 = value32 & (~(BIT(2)));
+	value32 = value32 | BIT(2);
+	HALMAC_REG_WRITE_32(pHalmac_adapter, REG_GPIO_MUXCFG, value32);
+
+	enable_bb = _FALSE;
+	halmac_set_hw_value_88xx(pHalmac_adapter, HALMAC_HW_EN_BB_RF, &enable_bb);
+
+
+	PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_pre_init_system_cfg <==========\n");
+
+	return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * halmac_init_system_cfg_88xx() -  init system config
+ * @pHalmac_adapter : the adapter of halmac
+ * Author : KaiYuan Chang/Ivan Lin
+ * Return : HALMAC_RET_STATUS
+ * More details of status code can be found in prototype document
+ */
+HALMAC_RET_STATUS
+halmac_init_system_cfg_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter
+)
+{
+	VOID *pDriver_adapter = NULL;
+	PHALMAC_API pHalmac_api;
+	u32 temp = 0;
+
+
+	if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter))
+		return HALMAC_RET_ADAPTER_INVALID;
+
+	if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter))
+		return HALMAC_RET_API_INVALID;
+
+	halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_INIT_SYSTEM_CFG);
+
+	pDriver_adapter = pHalmac_adapter->pDriver_adapter;
+	pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api;
+
+	PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_init_system_cfg ==========>\n");
+
+	HALMAC_REG_WRITE_8(pHalmac_adapter, REG_SYS_FUNC_EN + 1, HALMAC_FUNCTION_ENABLE_88XX);
+	HALMAC_REG_WRITE_32(pHalmac_adapter, REG_SYS_SDIO_CTRL, (u32)(HALMAC_REG_READ_32(pHalmac_adapter, REG_SYS_SDIO_CTRL) | BIT_LTE_MUX_CTRL_PATH));
+	HALMAC_REG_WRITE_32(pHalmac_adapter, REG_CPU_DMEM_CON, (u32)(HALMAC_REG_READ_32(pHalmac_adapter, REG_CPU_DMEM_CON) | BIT_WL_PLATFORM_RST));
+
+	/*disable boot-from-flash for driver's DL FW*/
+	temp = HALMAC_REG_READ_32(pHalmac_adapter, REG_MCUFW_CTRL);
+	if (temp & BIT_BOOT_FSPI_EN) {
+		HALMAC_REG_WRITE_32(pHalmac_adapter, REG_MCUFW_CTRL, temp & (~BIT_BOOT_FSPI_EN));
+		HALMAC_REG_WRITE_32(pHalmac_adapter, REG_GPIO_MUXCFG, HALMAC_REG_READ_32(pHalmac_adapter, REG_GPIO_MUXCFG) & (~BIT_FSPI_EN));
+	}
+
+	/* pHalmac_api->halmac_init_h2c(pHalmac_adapter); */
+
+	PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_init_system_cfg <==========\n");
+
+	return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * halmac_init_edca_cfg_88xx() - init EDCA config
+ * @pHalmac_adapter : the adapter of halmac
+ * Author : KaiYuan Chang/Ivan Lin
+ * Return : HALMAC_RET_STATUS
+ * More details of status code can be found in prototype document
+ */
+HALMAC_RET_STATUS
+halmac_init_edca_cfg_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter
+)
+{
+	u8 value8;
+	u32 value32;
+	VOID *pDriver_adapter = NULL;
+	PHALMAC_API pHalmac_api;
+
+	if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter))
+		return HALMAC_RET_ADAPTER_INVALID;
+
+	if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter))
+		return HALMAC_RET_API_INVALID;
+
+	halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_INIT_EDCA_CFG);
+
+	pDriver_adapter = pHalmac_adapter->pDriver_adapter;
+	pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api;
+
+	PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_init_edca_cfg_88xx ==========>\n");
+
+	/* Clear TX pause */
+	HALMAC_REG_WRITE_16(pHalmac_adapter, REG_TXPAUSE, 0x0000);
+
+	HALMAC_REG_WRITE_8(pHalmac_adapter, REG_SLOT, HALMAC_SLOT_TIME_88XX);
+	HALMAC_REG_WRITE_8(pHalmac_adapter, REG_PIFS, HALMAC_PIFS_TIME_88XX);
+	value32 = HALMAC_SIFS_CCK_CTX_88XX | (HALMAC_SIFS_OFDM_CTX_88XX << BIT_SHIFT_SIFS_OFDM_CTX) |
+		  (HALMAC_SIFS_CCK_TRX_88XX << BIT_SHIFT_SIFS_CCK_TRX) | (HALMAC_SIFS_OFDM_TRX_88XX << BIT_SHIFT_SIFS_OFDM_TRX);
+	HALMAC_REG_WRITE_32(pHalmac_adapter, REG_SIFS, value32);
+
+	HALMAC_REG_WRITE_32(pHalmac_adapter, REG_EDCA_VO_PARAM, HALMAC_REG_READ_32(pHalmac_adapter, REG_EDCA_VO_PARAM) & 0xFFFF);
+	HALMAC_REG_WRITE_16(pHalmac_adapter, REG_EDCA_VO_PARAM + 2, HALMAC_VO_TXOP_LIMIT_88XX);
+	HALMAC_REG_WRITE_16(pHalmac_adapter, REG_EDCA_VI_PARAM + 2, HALMAC_VI_TXOP_LIMIT_88XX);
+
+	HALMAC_REG_WRITE_32(pHalmac_adapter, REG_RD_NAV_NXT, HALMAC_RDG_NAV_88XX | (HALMAC_TXOP_NAV_88XX << 16));
+	HALMAC_REG_WRITE_16(pHalmac_adapter, REG_RXTSF_OFFSET_CCK, HALMAC_CCK_RX_TSF_88XX | (HALMAC_OFDM_RX_TSF_88XX) << 8);
+
+	value8 = HALMAC_REG_READ_8(pHalmac_adapter, REG_RD_CTRL + 1);
+	value8 |= (BIT_VOQ_RD_INIT_EN | BIT_VIQ_RD_INIT_EN | BIT_BEQ_RD_INIT_EN);
+	HALMAC_REG_WRITE_8(pHalmac_adapter, REG_RD_CTRL + 1, value8);
+
+	/* Set beacon cotnrol - enable TSF and other related functions */
+	HALMAC_REG_WRITE_8(pHalmac_adapter, REG_BCN_CTRL, (u8)(HALMAC_REG_READ_8(pHalmac_adapter, REG_BCN_CTRL) | BIT_EN_BCN_FUNCTION));
+
+	/* Set send beacon related registers */
+	HALMAC_REG_WRITE_32(pHalmac_adapter, REG_TBTT_PROHIBIT, HALMAC_TBTT_PROHIBIT_88XX | (HALMAC_TBTT_HOLD_TIME_88XX << BIT_SHIFT_TBTT_HOLD_TIME_AP));
+	HALMAC_REG_WRITE_8(pHalmac_adapter, REG_DRVERLYINT, HALMAC_DRIVER_EARLY_INT_88XX);
+	HALMAC_REG_WRITE_8(pHalmac_adapter, REG_BCNDMATIM, HALMAC_BEACON_DMA_TIM_88XX);
+
+	PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_init_edca_cfg_88xx <==========\n");
+
+	return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * halmac_init_wmac_cfg_88xx() - init wmac config
+ * @pHalmac_adapter : the adapter of halmac
+ * Author : KaiYuan Chang/Ivan Lin
+ * Return : HALMAC_RET_STATUS
+ * More details of status code can be found in prototype document
+ */
+HALMAC_RET_STATUS
+halmac_init_wmac_cfg_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter
+)
+{
+	VOID *pDriver_adapter = NULL;
+	PHALMAC_API pHalmac_api;
+
+	if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter))
+		return HALMAC_RET_ADAPTER_INVALID;
+
+	if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter))
+		return HALMAC_RET_API_INVALID;
+
+	halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_INIT_WMAC_CFG);
+
+	pDriver_adapter = pHalmac_adapter->pDriver_adapter;
+	pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api;
+
+	PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_init_wmac_cfg_88xx ==========>\n");
+
+	HALMAC_REG_WRITE_32(pHalmac_adapter, REG_RXFLTMAP0, HALMAC_RX_FILTER0_88XX);
+	HALMAC_REG_WRITE_16(pHalmac_adapter, REG_RXFLTMAP, HALMAC_RX_FILTER_88XX);
+
+	HALMAC_REG_WRITE_32(pHalmac_adapter, REG_RCR, HALMAC_RCR_CONFIG_88XX);
+
+	HALMAC_REG_WRITE_8(pHalmac_adapter, REG_RX_PKT_LIMIT, HALMAC_RXPKT_MAX_SIZE_BASE512);
+
+	HALMAC_REG_WRITE_8(pHalmac_adapter, REG_TCR + 1, (u8)(HALMAC_REG_READ_8(pHalmac_adapter, REG_TCR + 1) | 0x30));
+	HALMAC_REG_WRITE_8(pHalmac_adapter, REG_TCR + 2, 0x30);
+	HALMAC_REG_WRITE_8(pHalmac_adapter, REG_TCR + 1, 0x00);
+
+#if HALMAC_8821C_SUPPORT
+	if (HALMAC_CHIP_ID_8821C == pHalmac_adapter->chip_id)
+		HALMAC_REG_WRITE_8(pHalmac_adapter, REG_ACKTO_CCK, HALMAC_ACK_TO_CCK_88XX);
+#endif
+
+	HALMAC_REG_WRITE_32(pHalmac_adapter, REG_WMAC_OPTION_FUNCTION + 8, 0x30810041);
+	HALMAC_REG_WRITE_32(pHalmac_adapter, REG_WMAC_OPTION_FUNCTION + 4, 0x50802080);
+	HALMAC_REG_WRITE_32(pHalmac_adapter, REG_WL2LTECOEX_INDIRECT_ACCESS_CTRL_V1, 0xC00F0038);
+
+	PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_init_wmac_cfg_88xx <==========\n");
+
+	return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * halmac_init_mac_cfg_88xx() - config page1~page7 register
+ * @pHalmac_adapter : the adapter of halmac
+ * @mode : trx mode
+ * Author : KaiYuan Chang/Ivan Lin
+ * Return : HALMAC_RET_STATUS
+ * More details of status code can be found in prototype document
+ */
+HALMAC_RET_STATUS
+halmac_init_mac_cfg_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN HALMAC_TRX_MODE mode
+)
+{
+	VOID *pDriver_adapter = NULL;
+	PHALMAC_API pHalmac_api;
+	HALMAC_RET_STATUS status = HALMAC_RET_SUCCESS;
+
+	if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter))
+		return HALMAC_RET_ADAPTER_INVALID;
+
+	if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter))
+		return HALMAC_RET_API_INVALID;
+
+	halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_INIT_MAC_CFG);
+
+	pDriver_adapter = pHalmac_adapter->pDriver_adapter;
+	pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api;
+
+	PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_init_mac_cfg_88xx ==========>mode = %d\n", mode);
+
+	status = pHalmac_api->halmac_init_trx_cfg(pHalmac_adapter, mode);
+	if (HALMAC_RET_SUCCESS != status) {
+		PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "halmac_init_trx_cfg errorr = %x\n", status);
+		return status;
+	}
+#if 1
+	status = pHalmac_api->halmac_init_protocol_cfg(pHalmac_adapter);
+	if (HALMAC_RET_SUCCESS != status) {
+		PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "halmac_init_protocol_cfg_88xx error = %x\n", status);
+		return status;
+	}
+
+	status = halmac_init_edca_cfg_88xx(pHalmac_adapter);
+	if (HALMAC_RET_SUCCESS != status) {
+		PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "halmac_init_edca_cfg_88xx error = %x\n", status);
+		return status;
+	}
+
+	status = halmac_init_wmac_cfg_88xx(pHalmac_adapter);
+	if (HALMAC_RET_SUCCESS != status) {
+		PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "halmac_init_wmac_cfg_88xx error = %x\n", status);
+		return status;
+	}
+#endif
+	PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_init_mac_cfg_88xx <==========\n");
+
+	return status;
+}
+
+/**
+ * halmac_cfg_operation_mode_88xx() - config operation mode
+ * @pHalmac_adapter : the adapter of halmac
+ * @wireless_mode : 802.11 standard(b/g/n/ac�K)
+ * Author : KaiYuan Chang/Ivan Lin
+ * Return : HALMAC_RET_STATUS
+ * More details of status code can be found in prototype document
+ */
+HALMAC_RET_STATUS
+halmac_cfg_operation_mode_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN HALMAC_WIRELESS_MODE wireless_mode
+)
+{
+	VOID *pDriver_adapter = NULL;
+	HALMAC_WIRELESS_MODE wireless_mode_local = HALMAC_WIRELESS_MODE_UNDEFINE;
+
+	wireless_mode_local = wireless_mode;
+
+	if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter))
+		return HALMAC_RET_ADAPTER_INVALID;
+
+	if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter))
+		return HALMAC_RET_API_INVALID;
+
+	halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_CFG_OPERATION_MODE);
+
+	pDriver_adapter = pHalmac_adapter->pDriver_adapter;
+
+	PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_cfg_operation_mode_88xx ==========>wireless_mode = %d\n", wireless_mode);
+
+	PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_cfg_operation_mode_88xx <==========\n");
+
+	return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * halmac_cfg_ch_bw_88xx() - config channel & bandwidth
+ * @pHalmac_adapter : the adapter of halmac
+ * @channel : WLAN channel, support 2.4G & 5G
+ * @pri_ch_idx : primary channel index, idx1, idx2, idx3, idx4
+ * @bw : band width, 20, 40, 80, 160, 5 ,10
+ * Author : KaiYuan Chang
+ * Return : HALMAC_RET_STATUS
+ * More details of status code can be found in prototype document
+ */
+HALMAC_RET_STATUS
+halmac_cfg_ch_bw_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN u8 channel,
+	IN HALMAC_PRI_CH_IDX pri_ch_idx,
+	IN HALMAC_BW bw
+)
+{
+	VOID *pDriver_adapter = NULL;
+	PHALMAC_API pHalmac_api;
+
+	if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter))
+		return HALMAC_RET_ADAPTER_INVALID;
+
+	if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter))
+		return HALMAC_RET_API_INVALID;
+
+	halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_CFG_CH_BW);
+
+	pDriver_adapter = pHalmac_adapter->pDriver_adapter;
+	pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api;
+
+	PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_cfg_ch_bw_88xx ==========>ch = %d, idx=%d, bw=%d\n", channel, pri_ch_idx, bw);
+
+	halmac_cfg_pri_ch_idx_88xx(pHalmac_adapter,  pri_ch_idx);
+
+	halmac_cfg_bw_88xx(pHalmac_adapter, bw);
+
+	halmac_cfg_ch_88xx(pHalmac_adapter,  channel);
+
+	PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_cfg_ch_bw_88xx <==========\n");
+
+	return HALMAC_RET_SUCCESS;
+}
+
+HALMAC_RET_STATUS
+halmac_cfg_ch_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN u8 channel
+)
+{
+	u8 value8;
+	VOID *pDriver_adapter = NULL;
+	PHALMAC_API pHalmac_api;
+
+	if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter))
+		return HALMAC_RET_ADAPTER_INVALID;
+
+	if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter))
+		return HALMAC_RET_API_INVALID;
+
+	halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_CFG_CH_BW);
+
+	pDriver_adapter = pHalmac_adapter->pDriver_adapter;
+	pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api;
+
+	PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_cfg_ch_88xx ==========>ch = %d\n", channel);
+
+	value8 = HALMAC_REG_READ_8(pHalmac_adapter, REG_CCK_CHECK);
+	value8 = value8 & (~(BIT(7)));
+
+	if (channel > 35)
+		value8 = value8 | BIT(7);
+
+	HALMAC_REG_WRITE_8(pHalmac_adapter, REG_CCK_CHECK, value8);
+
+	PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_cfg_ch_88xx <==========\n");
+
+	return HALMAC_RET_SUCCESS;
+}
+
+HALMAC_RET_STATUS
+halmac_cfg_pri_ch_idx_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN HALMAC_PRI_CH_IDX pri_ch_idx
+)
+{
+	u8 txsc_40 = 0, txsc_20 = 0;
+	VOID *pDriver_adapter = NULL;
+	PHALMAC_API pHalmac_api;
+
+	if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter))
+		return HALMAC_RET_ADAPTER_INVALID;
+
+	if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter))
+		return HALMAC_RET_API_INVALID;
+
+	halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_CFG_CH_BW);
+
+	pDriver_adapter = pHalmac_adapter->pDriver_adapter;
+	pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api;
+
+	PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_cfg_pri_ch_idx_88xx ==========> idx=%d\n",  pri_ch_idx);
+
+	txsc_20 = pri_ch_idx;
+	if ((HALMAC_CH_IDX_1 == txsc_20) || (HALMAC_CH_IDX_3 == txsc_20))
+		txsc_40 = 9;
+	else
+		txsc_40 = 10;
+
+	HALMAC_REG_WRITE_8(pHalmac_adapter, REG_DATA_SC, BIT_TXSC_20M(txsc_20) | BIT_TXSC_40M(txsc_40));
+
+	PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_cfg_pri_ch_idx_88xx <==========\n");
+
+	return HALMAC_RET_SUCCESS;
+
+}
+
+/**
+ * halmac_cfg_bw_88xx() - config bandwidth
+ * @pHalmac_adapter : the adapter of halmac
+ * @bw : band width, 20, 40, 80, 160, 5 ,10
+ * Author : KaiYuan Chang
+ * Return : HALMAC_RET_STATUS
+ * More details of status code can be found in prototype document
+ */
+HALMAC_RET_STATUS
+halmac_cfg_bw_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN HALMAC_BW bw
+)
+{
+	u32 value32;
+	VOID *pDriver_adapter = NULL;
+	PHALMAC_API pHalmac_api;
+
+	if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter))
+		return HALMAC_RET_ADAPTER_INVALID;
+
+	if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter))
+		return HALMAC_RET_API_INVALID;
+
+	halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_CFG_BW);
+
+	pDriver_adapter = pHalmac_adapter->pDriver_adapter;
+	pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api;
+
+	PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_cfg_bw_88xx ==========>bw=%d\n", bw);
+
+	/* RF Mode */
+	value32 = HALMAC_REG_READ_32(pHalmac_adapter, REG_WMAC_TRXPTCL_CTL);
+	value32 = value32 & (~(BIT(7) | BIT(8)));
+
+	switch (bw) {
+	case HALMAC_BW_80:
+		value32 = value32 | BIT(7);
+		break;
+	case HALMAC_BW_40:
+		value32 = value32 | BIT(8);
+		break;
+	case HALMAC_BW_20:
+	case HALMAC_BW_10:
+	case HALMAC_BW_5:
+		break;
+	default:
+		PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "halmac_cfg_bw_88xx switch case not support\n");
+		break;
+	}
+	HALMAC_REG_WRITE_32(pHalmac_adapter, REG_WMAC_TRXPTCL_CTL, value32);
+
+	/* MAC CLK */
+	value32 = HALMAC_REG_READ_32(pHalmac_adapter, REG_AFE_CTRL1);
+	value32 = (value32 & (~(BIT(20) | BIT(21)))) | (HALMAC_MAC_CLOCK_HW_DEF_80M << BIT_SHIFT_MAC_CLK_SEL);
+	HALMAC_REG_WRITE_32(pHalmac_adapter, REG_AFE_CTRL1, value32);
+
+	HALMAC_REG_WRITE_8(pHalmac_adapter, REG_USTIME_TSF, HALMAC_MAC_CLOCK_88XX);
+	HALMAC_REG_WRITE_8(pHalmac_adapter, REG_USTIME_EDCA, HALMAC_MAC_CLOCK_88XX);
+
+	PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_cfg_bw_88xx <==========\n");
+
+	return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * halmac_dump_efuse_map_88xx() - dump "physical" efuse map
+ * @pHalmac_adapter : the adapter of halmac
+ * @cfg : dump efuse method
+ * Author : Ivan Lin/KaiYuan Chang
+ * Return : HALMAC_RET_STATUS
+ * More details of status code can be found in prototype document
+ */
+HALMAC_RET_STATUS
+halmac_dump_efuse_map_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN HALMAC_EFUSE_READ_CFG cfg
+)
+{
+	VOID *pDriver_adapter = NULL;
+	HALMAC_RET_STATUS status = HALMAC_RET_SUCCESS;
+	HALMAC_CMD_PROCESS_STATUS *pProcess_status = &(pHalmac_adapter->halmac_state.efuse_state_set.process_status);
+
+	if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter))
+		return HALMAC_RET_ADAPTER_INVALID;
+
+	if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter))
+		return HALMAC_RET_API_INVALID;
+
+	halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_DUMP_EFUSE_MAP);
+
+	pDriver_adapter = pHalmac_adapter->pDriver_adapter;
+
+	PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_dump_efuse_map_88xx ==========>cfg=%d\n", cfg);
+
+	if (HALMAC_CMD_PROCESS_SENDING == *pProcess_status) {
+		PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "Wait event(dump efuse)...\n");
+		return HALMAC_RET_BUSY_STATE;
+	}
+
+	if (HALMAC_EFUSE_CMD_CONSTRUCT_IDLE != halmac_query_efuse_curr_state_88xx(pHalmac_adapter)) {
+		PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "Not idle state(dump efuse)...\n");
+		return HALMAC_RET_ERROR_STATE;
+	}
+
+	if (HALMAC_MAC_POWER_OFF == pHalmac_adapter->halmac_state.mac_power)
+		PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_WARN, "[WARN]Dump efuse in suspend mode\n");
+
+	*pProcess_status = HALMAC_CMD_PROCESS_IDLE;
+	pHalmac_adapter->event_trigger.physical_efuse_map = 1;
+
+	status = halmac_func_switch_efuse_bank_88xx(pHalmac_adapter, HALMAC_EFUSE_BANK_WIFI);
+	if (HALMAC_RET_SUCCESS != status) {
+		PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_ERR, "halmac_func_switch_efuse_bank error = %x\n", status);
+		return status;
+	}
+
+	status = halmac_dump_efuse_88xx(pHalmac_adapter, cfg);
+
+	if (HALMAC_RET_SUCCESS != status) {
+		PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_ERR, "halmac_read_efuse error = %x\n", status);
+		return status;
+	}
+
+	if (_TRUE == pHalmac_adapter->hal_efuse_map_valid) {
+		*pProcess_status = HALMAC_CMD_PROCESS_DONE;
+
+		PLATFORM_EVENT_INDICATION(pDriver_adapter, HALMAC_FEATURE_DUMP_PHYSICAL_EFUSE, *pProcess_status,
+			pHalmac_adapter->pHalEfuse_map, pHalmac_adapter->hw_config_info.efuse_size);
+		pHalmac_adapter->event_trigger.physical_efuse_map = 0;
+	}
+
+	if (HALMAC_RET_SUCCESS != halmac_transition_efuse_state_88xx(pHalmac_adapter, HALMAC_EFUSE_CMD_CONSTRUCT_IDLE))
+		return HALMAC_RET_ERROR_STATE;
+
+	PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_TRACE, "halmac_dump_efuse_map_88xx <==========\n");
+
+	return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * halmac_dump_efuse_map_bt_88xx() - dump "BT physical" efuse map
+ * @pHalmac_adapter : the adapter of halmac
+ * @halmac_efuse_bank : bt efuse bank
+ * @bt_efuse_map_size : bt efuse map size. get from halmac_get_efuse_size API
+ * @pBT_efuse_map : bt efuse map
+ * Author : Soar / Ivan Lin
+ * Return : HALMAC_RET_STATUS
+ * More details of status code can be found in prototype document
+ */
+HALMAC_RET_STATUS
+halmac_dump_efuse_map_bt_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN HALMAC_EFUSE_BANK halmac_efuse_bank,
+	IN u32 bt_efuse_map_size,
+	OUT u8 *pBT_efuse_map
+)
+{
+	VOID *pDriver_adapter = NULL;
+	HALMAC_RET_STATUS status = HALMAC_RET_SUCCESS;
+	HALMAC_CMD_PROCESS_STATUS *pProcess_status = &(pHalmac_adapter->halmac_state.efuse_state_set.process_status);
+
+	if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter))
+		return HALMAC_RET_ADAPTER_INVALID;
+
+	if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter))
+		return HALMAC_RET_API_INVALID;
+
+	halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_DUMP_EFUSE_MAP_BT);
+
+	pDriver_adapter = pHalmac_adapter->pDriver_adapter;
+
+	PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_dump_efuse_map_bt_88xx ==========>\n");
+
+	if (pHalmac_adapter->hw_config_info.bt_efuse_size != bt_efuse_map_size)
+		return HALMAC_RET_EFUSE_SIZE_INCORRECT;
+
+	if ((halmac_efuse_bank >= HALMAC_EFUSE_BANK_MAX) || (halmac_efuse_bank == HALMAC_EFUSE_BANK_WIFI)) {
+		PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_ERR, "Undefined BT bank\n");
+		return HALMAC_RET_EFUSE_BANK_INCORRECT;
+	}
+
+	if (HALMAC_CMD_PROCESS_SENDING == *pProcess_status) {
+		PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "Wait event(dump efuse)...\n");
+		return HALMAC_RET_BUSY_STATE;
+	}
+
+	if (HALMAC_EFUSE_CMD_CONSTRUCT_IDLE != halmac_query_efuse_curr_state_88xx(pHalmac_adapter)) {
+		PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "Not idle state(dump efuse)...\n");
+		return HALMAC_RET_ERROR_STATE;
+	}
+
+	status = halmac_func_switch_efuse_bank_88xx(pHalmac_adapter, halmac_efuse_bank);
+	if (HALMAC_RET_SUCCESS != status) {
+		PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_ERR, "halmac_func_switch_efuse_bank error = %x\n", status);
+		return status;
+	}
+
+	status = halmac_read_hw_efuse_88xx(pHalmac_adapter, 0, bt_efuse_map_size, pBT_efuse_map);
+
+	if (HALMAC_RET_SUCCESS != status) {
+		PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_ERR, "halmac_read_hw_efuse_88xx error = %x\n", status);
+		return status;
+	}
+
+	if (HALMAC_RET_SUCCESS != halmac_transition_efuse_state_88xx(pHalmac_adapter, HALMAC_EFUSE_CMD_CONSTRUCT_IDLE))
+		return HALMAC_RET_ERROR_STATE;
+
+	PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_TRACE, "halmac_dump_efuse_map_bt_88xx <==========\n");
+
+	return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * halmac_write_efuse_bt_88xx() - write "BT physical" efuse offset
+ * @pHalmac_adapter : the adapter of halmac
+ * @halmac_offset : offset
+ * @halmac_value : Write value
+ * @pBT_efuse_map : bt efuse map
+ * Author : Soar
+ * Return : HALMAC_RET_STATUS
+ * More details of status code can be found in prototype document
+ */
+HALMAC_RET_STATUS
+halmac_write_efuse_bt_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN u32 halmac_offset,
+	IN u8 halmac_value,
+	IN HALMAC_EFUSE_BANK halmac_efuse_bank
+)
+{
+	VOID *pDriver_adapter = NULL;
+	HALMAC_RET_STATUS status = HALMAC_RET_SUCCESS;
+
+
+	HALMAC_CMD_PROCESS_STATUS *pProcess_status = &(pHalmac_adapter->halmac_state.efuse_state_set.process_status);
+
+	if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter))
+		return HALMAC_RET_ADAPTER_INVALID;
+
+	if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter))
+		return HALMAC_RET_API_INVALID;
+
+	halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_WRITE_EFUSE_BT);
+
+	pDriver_adapter = pHalmac_adapter->pDriver_adapter;
+
+	PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_TRACE, "halmac_write_efuse_bt_88xx ==========>\n");
+	PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_TRACE, "offset : %X value : %X Bank : %X\n", halmac_offset, halmac_value, halmac_efuse_bank);
+
+	if (HALMAC_CMD_PROCESS_SENDING == *pProcess_status) {
+		PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "Wait/Rcvd event(dump efuse)...\n");
+		return HALMAC_RET_BUSY_STATE;
+	}
+
+	if (HALMAC_EFUSE_CMD_CONSTRUCT_IDLE != halmac_query_efuse_curr_state_88xx(pHalmac_adapter)) {
+		PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "Not idle state(dump efuse)...\n");
+		return HALMAC_RET_ERROR_STATE;
+	}
+
+	if (halmac_offset >= pHalmac_adapter->hw_config_info.efuse_size) {
+		PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_ERR, "Offset is too large\n");
+		return HALMAC_RET_EFUSE_SIZE_INCORRECT;
+	}
+
+	if ((halmac_efuse_bank > HALMAC_EFUSE_BANK_MAX) || (halmac_efuse_bank == HALMAC_EFUSE_BANK_WIFI)) {
+		PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_ERR, "Undefined BT bank\n");
+		return HALMAC_RET_EFUSE_BANK_INCORRECT;
+	}
+
+	status = halmac_func_switch_efuse_bank_88xx(pHalmac_adapter, halmac_efuse_bank);
+	if (HALMAC_RET_SUCCESS != status) {
+		PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_ERR, "halmac_func_switch_efuse_bank error = %x\n", status);
+		return status;
+	}
+
+	status = halmac_func_write_efuse_88xx(pHalmac_adapter, halmac_offset, halmac_value);
+	if (HALMAC_RET_SUCCESS != status) {
+		PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_ERR, "halmac_func_write_efuse error = %x\n", status);
+		return status;
+	}
+
+	if (HALMAC_RET_SUCCESS != halmac_transition_efuse_state_88xx(pHalmac_adapter, HALMAC_EFUSE_CMD_CONSTRUCT_IDLE))
+		return HALMAC_RET_ERROR_STATE;
+
+	PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_TRACE, "halmac_write_efuse_bt_88xx <==========\n");
+
+	return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * halmac_get_efuse_available_size_88xx() - get efuse available size
+ * @pHalmac_adapter : the adapter of halmac
+ * @halmac_size : physical efuse available size
+ * Author : Soar
+ * Return : HALMAC_RET_STATUS
+ * More details of status code can be found in prototype document
+ */
+HALMAC_RET_STATUS
+halmac_get_efuse_available_size_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	OUT u32 *halmac_size
+)
+{
+	HALMAC_RET_STATUS status;
+	VOID *pDriver_adapter = NULL;
+
+	if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter))
+		return HALMAC_RET_ADAPTER_INVALID;
+
+	if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter))
+		return HALMAC_RET_API_INVALID;
+
+	pDriver_adapter = pHalmac_adapter->pDriver_adapter;
+
+	PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_TRACE, "halmac_get_efuse_available_size_88xx ==========>\n");
+
+	status = halmac_dump_logical_efuse_map_88xx(pHalmac_adapter, HALMAC_EFUSE_R_DRV);
+
+	if (HALMAC_RET_SUCCESS != status)
+		return status;
+
+	*halmac_size = pHalmac_adapter->hw_config_info.efuse_size - HALMAC_PROTECTED_EFUSE_SIZE_88XX - pHalmac_adapter->efuse_end;
+
+	PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_TRACE, "halmac_get_efuse_available_size_88xx <==========\n");
+
+	return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * halmac_get_efuse_size_88xx() - get "physical" efuse size
+ * @pHalmac_adapter : the adapter of halmac
+ * @halmac_size : physical efuse size
+ * Author : Ivan Lin/KaiYuan Chang
+ * Return : HALMAC_RET_STATUS
+ * More details of status code can be found in prototype document
+ */
+HALMAC_RET_STATUS
+halmac_get_efuse_size_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	OUT u32 *halmac_size
+)
+{
+	VOID *pDriver_adapter = NULL;
+
+	if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter))
+		return HALMAC_RET_ADAPTER_INVALID;
+
+	if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter))
+		return HALMAC_RET_API_INVALID;
+
+	halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_GET_EFUSE_SIZE);
+
+	pDriver_adapter = pHalmac_adapter->pDriver_adapter;
+
+	PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_TRACE, "halmac_get_efuse_size_88xx ==========>\n");
+
+	*halmac_size = pHalmac_adapter->hw_config_info.efuse_size;
+
+	PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_TRACE, "halmac_get_efuse_size_88xx <==========\n");
+
+	return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * halmac_get_logical_efuse_size_88xx() - get "logical" efuse size
+ * @pHalmac_adapter : the adapter of halmac
+ * @halmac_size : logical efuse size
+ * Author : Ivan Lin/KaiYuan Chang
+ * Return : HALMAC_RET_STATUS
+ * More details of status code can be found in prototype document
+ */
+HALMAC_RET_STATUS
+halmac_get_logical_efuse_size_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	OUT u32 *halmac_size
+)
+{
+	VOID *pDriver_adapter = NULL;
+
+	if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter))
+		return HALMAC_RET_ADAPTER_INVALID;
+
+	if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter))
+		return HALMAC_RET_API_INVALID;
+
+	halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_GET_LOGICAL_EFUSE_SIZE);
+
+	pDriver_adapter = pHalmac_adapter->pDriver_adapter;
+
+	PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_TRACE, "halmac_get_logical_efuse_size_88xx ==========>\n");
+
+	*halmac_size = pHalmac_adapter->hw_config_info.eeprom_size;
+
+	PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_TRACE, "halmac_get_logical_efuse_size_88xx <==========\n");
+
+	return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * halmac_dump_logical_efuse_map_88xx() - dump "logical" efuse map
+ * @pHalmac_adapter : the adapter of halmac
+ * @cfg : dump efuse method
+ * Author : Soar
+ * Return : HALMAC_RET_STATUS
+ * More details of status code can be found in prototype document
+ */
+HALMAC_RET_STATUS
+halmac_dump_logical_efuse_map_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN HALMAC_EFUSE_READ_CFG cfg
+)
+{
+	u8 *pEeprom_map = NULL;
+	u32 eeprom_size = pHalmac_adapter->hw_config_info.eeprom_size;
+	VOID *pDriver_adapter = NULL;
+	HALMAC_RET_STATUS status = HALMAC_RET_SUCCESS;
+	HALMAC_CMD_PROCESS_STATUS *pProcess_status = &(pHalmac_adapter->halmac_state.efuse_state_set.process_status);
+
+	if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter))
+		return HALMAC_RET_ADAPTER_INVALID;
+
+	if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter))
+		return HALMAC_RET_API_INVALID;
+
+	halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_DUMP_LOGICAL_EFUSE_MAP);
+
+	pDriver_adapter = pHalmac_adapter->pDriver_adapter;
+
+	PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_TRACE, "halmac_dump_logical_efuse_map_88xx ==========>cfg = %d\n", cfg);
+
+	if (HALMAC_CMD_PROCESS_SENDING == *pProcess_status) {
+		PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "Wait/Rcvd event(dump efuse)...\n");
+		return HALMAC_RET_BUSY_STATE;
+	}
+
+	if (HALMAC_EFUSE_CMD_CONSTRUCT_IDLE != halmac_query_efuse_curr_state_88xx(pHalmac_adapter)) {
+		PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "Not idle state(dump efuse)...\n");
+		return HALMAC_RET_ERROR_STATE;
+	}
+
+	if (HALMAC_MAC_POWER_OFF == pHalmac_adapter->halmac_state.mac_power)
+		PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_WARN, "[WARN]Dump logical efuse in suspend mode\n");
+
+	*pProcess_status = HALMAC_CMD_PROCESS_IDLE;
+	pHalmac_adapter->event_trigger.logical_efuse_map = 1;
+
+	status = halmac_func_switch_efuse_bank_88xx(pHalmac_adapter, HALMAC_EFUSE_BANK_WIFI);
+	if (HALMAC_RET_SUCCESS != status) {
+		PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_ERR, "halmac_func_switch_efuse_bank error = %x\n", status);
+		return status;
+	}
+
+	status = halmac_dump_efuse_88xx(pHalmac_adapter, cfg);
+
+	if (HALMAC_RET_SUCCESS != status) {
+		PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_ERR, "halmac_eeprom_parser_88xx error = %x\n", status);
+		return status;
+	}
+
+	if (_TRUE == pHalmac_adapter->hal_efuse_map_valid) {
+		*pProcess_status = HALMAC_CMD_PROCESS_DONE;
+
+		pEeprom_map = (u8 *)PLATFORM_RTL_MALLOC(pDriver_adapter, eeprom_size);
+		if (NULL == pEeprom_map) {
+			PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_ERR, "halmac allocate local eeprom map Fail!!\n");
+			return HALMAC_RET_MALLOC_FAIL;
+		}
+		PLATFORM_RTL_MEMSET(pDriver_adapter, pEeprom_map, 0xFF, eeprom_size);
+
+		if (HALMAC_RET_SUCCESS != halmac_eeprom_parser_88xx(pHalmac_adapter, pHalmac_adapter->pHalEfuse_map, pEeprom_map))
+			return HALMAC_RET_EEPROM_PARSING_FAIL;
+
+		PLATFORM_EVENT_INDICATION(pDriver_adapter, HALMAC_FEATURE_DUMP_LOGICAL_EFUSE, *pProcess_status, pEeprom_map, eeprom_size);
+		pHalmac_adapter->event_trigger.logical_efuse_map = 0;
+
+		PLATFORM_RTL_FREE(pDriver_adapter, pEeprom_map, eeprom_size);
+	}
+
+	if (HALMAC_RET_SUCCESS != halmac_transition_efuse_state_88xx(pHalmac_adapter, HALMAC_EFUSE_CMD_CONSTRUCT_IDLE))
+		return HALMAC_RET_ERROR_STATE;
+
+	PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_TRACE, "halmac_dump_logical_efuse_map_88xx <==========\n");
+
+	return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * halmac_read_logical_efuse_88xx() - read logical efuse map 1 byte
+ * @pHalmac_adapter : the adapter of halmac
+ * @halmac_offset : offset
+ * @pValue : 1 byte efuse value
+ * Author : Soar
+ * Return : HALMAC_RET_STATUS
+ * More details of status code can be found in prototype document
+ */
+HALMAC_RET_STATUS
+halmac_read_logical_efuse_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN u32 halmac_offset,
+	OUT u8 *pValue
+)
+{
+	u8 *pEeprom_map = NULL;
+	u32 eeprom_size = pHalmac_adapter->hw_config_info.eeprom_size;
+	VOID *pDriver_adapter = NULL;
+	HALMAC_RET_STATUS status = HALMAC_RET_SUCCESS;
+
+	HALMAC_CMD_PROCESS_STATUS *pProcess_status = &(pHalmac_adapter->halmac_state.efuse_state_set.process_status);
+
+	if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter))
+		return HALMAC_RET_ADAPTER_INVALID;
+
+	if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter))
+		return HALMAC_RET_API_INVALID;
+
+	halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_READ_LOGICAL_EFUSE);
+
+	pDriver_adapter = pHalmac_adapter->pDriver_adapter;
+
+	PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_TRACE, "halmac_read_logical_efuse_88xx ==========>\n");
+
+	if (halmac_offset >= eeprom_size) {
+		PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_ERR, "Offset is too large\n");
+		return HALMAC_RET_EFUSE_SIZE_INCORRECT;
+	}
+
+	if (HALMAC_CMD_PROCESS_SENDING == *pProcess_status) {
+		PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "Wait/Rcvd event(dump efuse)...\n");
+		return HALMAC_RET_BUSY_STATE;
+	}
+	if (HALMAC_EFUSE_CMD_CONSTRUCT_IDLE != halmac_query_efuse_curr_state_88xx(pHalmac_adapter)) {
+		PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "Not idle state(dump efuse)...\n");
+		return HALMAC_RET_ERROR_STATE;
+	}
+
+	status = halmac_func_switch_efuse_bank_88xx(pHalmac_adapter, HALMAC_EFUSE_BANK_WIFI);
+	if (HALMAC_RET_SUCCESS != status) {
+		PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_ERR, "halmac_func_switch_efuse_bank error = %x\n", status);
+		return status;
+	}
+
+	pEeprom_map = (u8 *)PLATFORM_RTL_MALLOC(pDriver_adapter, eeprom_size);
+	if (NULL == pEeprom_map) {
+		PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_ERR, "halmac allocate local eeprom map Fail!!\n");
+		return HALMAC_RET_MALLOC_FAIL;
+	}
+	PLATFORM_RTL_MEMSET(pDriver_adapter, pEeprom_map, 0xFF, eeprom_size);
+
+	status = halmac_read_logical_efuse_map_88xx(pHalmac_adapter, pEeprom_map);
+	if (HALMAC_RET_SUCCESS != status) {
+		PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_ERR, "halmac_read_logical_efuse_map error = %x\n", status);
+		PLATFORM_RTL_FREE(pDriver_adapter, pEeprom_map, eeprom_size);
+		return status;
+	}
+
+	*pValue = *(pEeprom_map + halmac_offset);
+
+	if (HALMAC_RET_SUCCESS != halmac_transition_efuse_state_88xx(pHalmac_adapter, HALMAC_EFUSE_CMD_CONSTRUCT_IDLE)) {
+		PLATFORM_RTL_FREE(pDriver_adapter, pEeprom_map, eeprom_size);
+		return HALMAC_RET_ERROR_STATE;
+	}
+
+	PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_TRACE, "halmac_read_logical_efuse_88xx <==========\n");
+
+	PLATFORM_RTL_FREE(pDriver_adapter, pEeprom_map, eeprom_size);
+
+	return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * halmac_write_logical_efuse_88xx() - write "logical" efuse offset
+ * @pHalmac_adapter : the adapter of halmac
+ * @halmac_offset : offset
+ * @halmac_value : value
+ * Author : Soar
+ * Return : HALMAC_RET_STATUS
+ * More details of status code can be found in prototype document
+ */
+HALMAC_RET_STATUS
+halmac_write_logical_efuse_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN u32 halmac_offset,
+	IN u8 halmac_value
+)
+{
+	VOID *pDriver_adapter = NULL;
+	PHALMAC_API pHalmac_api;
+	HALMAC_RET_STATUS status = HALMAC_RET_SUCCESS;
+
+	HALMAC_CMD_PROCESS_STATUS *pProcess_status = &(pHalmac_adapter->halmac_state.efuse_state_set.process_status);
+
+	if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter))
+		return HALMAC_RET_ADAPTER_INVALID;
+
+	if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter))
+		return HALMAC_RET_API_INVALID;
+
+	halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_WRITE_LOGICAL_EFUSE);
+
+	pDriver_adapter = pHalmac_adapter->pDriver_adapter;
+	pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api;
+
+	PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_TRACE, "halmac_write_logical_efuse_88xx ==========>\n");
+
+	if (halmac_offset >= pHalmac_adapter->hw_config_info.eeprom_size) {
+		PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_ERR, "Offset is too large\n");
+		return HALMAC_RET_EFUSE_SIZE_INCORRECT;
+	}
+
+	if (HALMAC_CMD_PROCESS_SENDING == *pProcess_status) {
+		PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "Wait/Rcvd event(dump efuse)...\n");
+		return HALMAC_RET_BUSY_STATE;
+	}
+
+	if (HALMAC_EFUSE_CMD_CONSTRUCT_IDLE != halmac_query_efuse_curr_state_88xx(pHalmac_adapter)) {
+		PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "Not idle state(dump efuse)...\n");
+		return HALMAC_RET_ERROR_STATE;
+	}
+
+	status = halmac_func_switch_efuse_bank_88xx(pHalmac_adapter, HALMAC_EFUSE_BANK_WIFI);
+	if (HALMAC_RET_SUCCESS != status) {
+		PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_ERR, "halmac_func_switch_efuse_bank error = %x\n", status);
+		return status;
+	}
+
+	status = halmac_func_write_logical_efuse_88xx(pHalmac_adapter, halmac_offset, halmac_value);
+	if (HALMAC_RET_SUCCESS != status) {
+		PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_ERR, "halmac_write_logical_efuse error = %x\n", status);
+		return status;
+	}
+
+	if (HALMAC_RET_SUCCESS != halmac_transition_efuse_state_88xx(pHalmac_adapter, HALMAC_EFUSE_CMD_CONSTRUCT_IDLE))
+		return HALMAC_RET_ERROR_STATE;
+
+	PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_TRACE, "halmac_write_logical_efuse_88xx <==========\n");
+
+	return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * halmac_pg_efuse_by_map_88xx() - pg logical efuse by map
+ * @pHalmac_adapter : the adapter of halmac
+ * @pPg_efuse_info : efuse map information
+ * @cfg : dump efuse method
+ * Author : Soar
+ * Return : HALMAC_RET_STATUS
+ * More details of status code can be found in prototype document
+ */
+HALMAC_RET_STATUS
+halmac_pg_efuse_by_map_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN PHALMAC_PG_EFUSE_INFO pPg_efuse_info,
+	IN HALMAC_EFUSE_READ_CFG cfg
+)
+{
+	VOID *pDriver_adapter = NULL;
+	HALMAC_RET_STATUS status = HALMAC_RET_SUCCESS;
+
+	HALMAC_CMD_PROCESS_STATUS *pProcess_status = &(pHalmac_adapter->halmac_state.efuse_state_set.process_status);
+
+	if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter))
+		return HALMAC_RET_ADAPTER_INVALID;
+
+	if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter))
+		return HALMAC_RET_API_INVALID;
+
+	halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_PG_EFUSE_BY_MAP);
+
+	pDriver_adapter = pHalmac_adapter->pDriver_adapter;
+
+	PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_TRACE, "halmac_pg_efuse_by_map_88xx ==========>\n");
+
+	if (pPg_efuse_info->efuse_map_size != pHalmac_adapter->hw_config_info.eeprom_size) {
+		PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_ERR, "efuse_map_size is incorrect, should be %d bytes\n", pHalmac_adapter->hw_config_info.eeprom_size);
+		return HALMAC_RET_EFUSE_SIZE_INCORRECT;
+	}
+
+	if ((pPg_efuse_info->efuse_map_size & 0xF) > 0) {
+		PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_ERR, "efuse_map_size should be multiple of 16\n");
+		return HALMAC_RET_EFUSE_SIZE_INCORRECT;
+	}
+
+	if (pPg_efuse_info->efuse_mask_size != pPg_efuse_info->efuse_map_size >> 4) {
+		PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_ERR, "efuse_mask_size is incorrect, should be %d bytes\n", pPg_efuse_info->efuse_map_size >> 4);
+		return HALMAC_RET_EFUSE_SIZE_INCORRECT;
+	}
+
+	if (NULL == pPg_efuse_info->pEfuse_map) {
+		PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_ERR, "efuse_map is NULL\n");
+		return HALMAC_RET_NULL_POINTER;
+	}
+
+	if (NULL == pPg_efuse_info->pEfuse_mask) {
+		PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_ERR, "efuse_mask is NULL\n");
+		return HALMAC_RET_NULL_POINTER;
+	}
+
+	if (HALMAC_CMD_PROCESS_SENDING == *pProcess_status) {
+		PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "Wait/Rcvd event(dump efuse)...\n");
+		return HALMAC_RET_BUSY_STATE;
+	}
+
+	if (HALMAC_EFUSE_CMD_CONSTRUCT_IDLE != halmac_query_efuse_curr_state_88xx(pHalmac_adapter)) {
+		PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "Not idle state(dump efuse)...\n");
+		return HALMAC_RET_ERROR_STATE;
+	}
+
+	status = halmac_func_switch_efuse_bank_88xx(pHalmac_adapter, HALMAC_EFUSE_BANK_WIFI);
+	if (HALMAC_RET_SUCCESS != status) {
+		PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_ERR, "halmac_func_switch_efuse_bank error = %x\n", status);
+		return status;
+	}
+
+	status = halmac_func_pg_efuse_by_map_88xx(pHalmac_adapter, pPg_efuse_info, cfg);
+
+	if (HALMAC_RET_SUCCESS != status) {
+		PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_ERR, "halmac_pg_efuse_by_map error = %x\n", status);
+		return status;
+	}
+
+	if (HALMAC_RET_SUCCESS != halmac_transition_efuse_state_88xx(pHalmac_adapter, HALMAC_EFUSE_CMD_CONSTRUCT_IDLE))
+		return HALMAC_RET_ERROR_STATE;
+
+	PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_TRACE, "halmac_pg_efuse_by_map_88xx <==========\n");
+
+	return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * halmac_get_c2h_info_88xx() - process halmac C2H packet
+ * @pHalmac_adapter : the adapter of halmac
+ * @halmac_buf : RX Packet pointer
+ * @halmac_size : RX Packet size
+ * Author : KaiYuan Chang/Ivan Lin
+ *
+ * Used to process c2h packet info from RX path. After receiving the packet,
+ * user need to call this api and pass the packet pointer.
+ *
+ * Return : HALMAC_RET_STATUS
+ * More details of status code can be found in prototype document
+ */
+HALMAC_RET_STATUS
+halmac_get_c2h_info_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN u8 *halmac_buf,
+	IN u32 halmac_size
+)
+{
+	VOID *pDriver_adapter = NULL;
+	HALMAC_RET_STATUS status = HALMAC_RET_SUCCESS;
+
+
+	if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter))
+		return HALMAC_RET_ADAPTER_INVALID;
+
+	if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter))
+		return HALMAC_RET_API_INVALID;
+
+	halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_GET_C2H_INFO);
+
+	pDriver_adapter = pHalmac_adapter->pDriver_adapter;
+
+	/* PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_get_c2h_info_88xx ==========>\n"); */
+
+	/* Check if it is C2H packet */
+	if (_TRUE == GET_RX_DESC_C2H(halmac_buf)) {
+		PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "C2H packet, start parsing!\n");
+
+		status = halmac_parse_c2h_packet_88xx(pHalmac_adapter, halmac_buf, halmac_size);
+
+		if (HALMAC_RET_SUCCESS != status) {
+			PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_ERR, "halmac_parse_c2h_packet_88xx error = %x\n", status);
+			return status;
+		}
+	}
+
+	/* PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_get_c2h_info_88xx <==========\n"); */
+
+	return HALMAC_RET_SUCCESS;
+}
+
+HALMAC_RET_STATUS
+halmac_cfg_fwlps_option_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN PHALMAC_FWLPS_OPTION pLps_option
+)
+{
+	VOID *pDriver_adapter = NULL;
+	PHALMAC_FWLPS_OPTION pHal_fwlps_option;
+
+	if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter))
+		return HALMAC_RET_ADAPTER_INVALID;
+
+	if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter))
+		return HALMAC_RET_API_INVALID;
+
+	halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_CFG_FWLPS_OPTION);
+
+	pDriver_adapter = pHalmac_adapter->pDriver_adapter;
+	pHal_fwlps_option = &(pHalmac_adapter->fwlps_option);
+
+	PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_PWR, HALMAC_DBG_TRACE, "halmac_cfg_fwlps_option_88xx ==========>\n");
+
+	pHal_fwlps_option->mode = pLps_option->mode;
+	pHal_fwlps_option->clk_request = pLps_option->clk_request;
+	pHal_fwlps_option->rlbm = pLps_option->rlbm;
+	pHal_fwlps_option->smart_ps = pLps_option->smart_ps;
+	pHal_fwlps_option->awake_interval = pLps_option->awake_interval;
+	pHal_fwlps_option->all_queue_uapsd = pLps_option->all_queue_uapsd;
+	pHal_fwlps_option->pwr_state = pLps_option->pwr_state;
+	pHal_fwlps_option->low_pwr_rx_beacon = pLps_option->low_pwr_rx_beacon;
+	pHal_fwlps_option->ant_auto_switch = pLps_option->ant_auto_switch;
+	pHal_fwlps_option->ps_allow_bt_high_Priority = pLps_option->ps_allow_bt_high_Priority;
+	pHal_fwlps_option->protect_bcn = pLps_option->protect_bcn;
+	pHal_fwlps_option->silence_period = pLps_option->silence_period;
+	pHal_fwlps_option->fast_bt_connect = pLps_option->fast_bt_connect;
+	pHal_fwlps_option->two_antenna_en = pLps_option->two_antenna_en;
+	pHal_fwlps_option->adopt_user_Setting = pLps_option->adopt_user_Setting;
+	pHal_fwlps_option->drv_bcn_early_shift = pLps_option->drv_bcn_early_shift;
+	pHal_fwlps_option->enter_32K = pLps_option->enter_32K;
+
+	PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_PWR, HALMAC_DBG_TRACE, "halmac_cfg_fwlps_option_88xx <==========\n");
+
+	return HALMAC_RET_SUCCESS;
+}
+
+HALMAC_RET_STATUS
+halmac_cfg_fwips_option_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN PHALMAC_FWIPS_OPTION pIps_option
+)
+{
+	VOID *pDriver_adapter = NULL;
+	PHALMAC_FWIPS_OPTION pIps_option_local;
+
+	if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter))
+		return HALMAC_RET_ADAPTER_INVALID;
+
+	if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter))
+		return HALMAC_RET_API_INVALID;
+
+	halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_CFG_FWIPS_OPTION);
+
+	pDriver_adapter = pHalmac_adapter->pDriver_adapter;
+
+	PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_PWR, HALMAC_DBG_TRACE, "halmac_cfg_fwips_option_88xx ==========>\n");
+
+	pIps_option_local = pIps_option;
+
+	PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_PWR, HALMAC_DBG_TRACE, "halmac_cfg_fwips_option_88xx <==========\n");
+
+	return HALMAC_RET_SUCCESS;
+}
+
+HALMAC_RET_STATUS
+halmac_enter_wowlan_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN PHALMAC_WOWLAN_OPTION pWowlan_option
+)
+{
+	VOID *pDriver_adapter = NULL;
+	PHALMAC_WOWLAN_OPTION pWowlan_option_local;
+
+	if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter))
+		return HALMAC_RET_ADAPTER_INVALID;
+
+	if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter))
+		return HALMAC_RET_API_INVALID;
+
+	halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_ENTER_WOWLAN);
+
+	pDriver_adapter = pHalmac_adapter->pDriver_adapter;
+
+	PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_PWR, HALMAC_DBG_TRACE, "halmac_enter_wowlan_88xx ==========>\n");
+
+	pWowlan_option_local = pWowlan_option;
+
+	PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_PWR, HALMAC_DBG_TRACE, "halmac_enter_wowlan_88xx <==========\n");
+
+	return HALMAC_RET_SUCCESS;
+}
+
+HALMAC_RET_STATUS
+halmac_leave_wowlan_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter
+)
+{
+	VOID *pDriver_adapter = NULL;
+
+	if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter))
+		return HALMAC_RET_ADAPTER_INVALID;
+
+	if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter))
+		return HALMAC_RET_API_INVALID;
+
+	halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_LEAVE_WOWLAN);
+
+	pDriver_adapter = pHalmac_adapter->pDriver_adapter;
+
+	PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_PWR, HALMAC_DBG_TRACE, "halmac_leave_wowlan_88xx ==========>\n");
+
+
+	PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_PWR, HALMAC_DBG_TRACE, "halmac_leave_wowlan_88xx <==========\n");
+
+	return HALMAC_RET_SUCCESS;
+}
+
+HALMAC_RET_STATUS
+halmac_enter_ps_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN HALMAC_PS_STATE ps_state
+)
+{
+	u8 rpwm;
+	VOID *pDriver_adapter = NULL;
+	PHALMAC_API pHalmac_api;
+	HALMAC_RET_STATUS status = HALMAC_RET_SUCCESS;
+
+	if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter))
+		return HALMAC_RET_ADAPTER_INVALID;
+
+	if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter))
+		return HALMAC_RET_API_INVALID;
+
+	if (HALMAC_RET_SUCCESS != halmac_fw_validate(pHalmac_adapter))
+		return HALMAC_RET_NO_DLFW;
+
+	halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_ENTER_PS);
+
+	pDriver_adapter = pHalmac_adapter->pDriver_adapter;
+	pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api;
+
+	PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_PWR, HALMAC_DBG_TRACE, "halmac_enter_ps_88xx ==========>\n");
+
+	if (ps_state == pHalmac_adapter->halmac_state.ps_state) {
+		PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_PWR, HALMAC_DBG_ERR, "power state is already in PS State!!\n");
+		return HALMAC_RET_SUCCESS;
+	}
+
+	if (HALMAC_PS_STATE_LPS == ps_state) {
+		status = halmac_send_h2c_set_pwr_mode_88xx(pHalmac_adapter, &(pHalmac_adapter->fwlps_option));
+		if (HALMAC_RET_SUCCESS != status) {
+			PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_PWR, HALMAC_DBG_ERR, "halmac_send_h2c_set_pwr_mode_88xx error = %x!!\n", status);
+			return status;
+		}
+	} else if (HALMAC_PS_STATE_IPS == ps_state) {
+	}
+
+	pHalmac_adapter->halmac_state.ps_state = ps_state;
+
+	/* Enter 32K */
+	if (HALMAC_INTERFACE_SDIO == pHalmac_adapter->halmac_interface) {
+		if (_TRUE == pHalmac_adapter->fwlps_option.enter_32K) {
+			rpwm = (u8)(((pHalmac_adapter->rpwm_record ^ (BIT(7))) | (BIT(0))) & 0x81);
+			HALMAC_REG_WRITE_8(pHalmac_adapter, REG_SDIO_HRPWM1, rpwm);
+			pHalmac_adapter->low_clk = _TRUE;
+		}
+	} else if (HALMAC_INTERFACE_USB == pHalmac_adapter->halmac_interface) {
+		if (_TRUE == pHalmac_adapter->fwlps_option.enter_32K) {
+			rpwm = (u8)(((pHalmac_adapter->rpwm_record ^ (BIT(7))) | (BIT(0))) & 0x81);
+			HALMAC_REG_WRITE_8(pHalmac_adapter, 0xFE58, rpwm);
+			pHalmac_adapter->low_clk = _TRUE;
+		}
+	}
+
+	PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_PWR, HALMAC_DBG_TRACE, "halmac_enter_ps_88xx <==========\n");
+
+	return HALMAC_RET_SUCCESS;
+}
+
+HALMAC_RET_STATUS
+halmac_leave_ps_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter
+)
+{
+	u8 rpwm, cpwm;
+	u32 counter;
+	VOID *pDriver_adapter = NULL;
+	PHALMAC_API pHalmac_api;
+	HALMAC_FWLPS_OPTION fw_lps_option;
+	HALMAC_RET_STATUS status = HALMAC_RET_SUCCESS;
+
+
+	if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter))
+		return HALMAC_RET_ADAPTER_INVALID;
+
+	if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter))
+		return HALMAC_RET_API_INVALID;
+
+	if (HALMAC_RET_SUCCESS != halmac_fw_validate(pHalmac_adapter))
+		return HALMAC_RET_NO_DLFW;
+
+	halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_LEAVE_PS);
+
+	pDriver_adapter = pHalmac_adapter->pDriver_adapter;
+	pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api;
+
+	PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_PWR, HALMAC_DBG_TRACE, "halmac_leave_ps_88xx ==========>\n");
+
+	if (HALMAC_PS_STATE_ACT == pHalmac_adapter->halmac_state.ps_state) {
+		PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_PWR, HALMAC_DBG_ERR, "power state is already in active!!\n");
+		return HALMAC_RET_SUCCESS;
+	}
+
+	if (_TRUE == pHalmac_adapter->low_clk) {
+		cpwm = HALMAC_REG_READ_8(pHalmac_adapter, REG_SDIO_HRPWM1);
+		rpwm = (u8)(((pHalmac_adapter->rpwm_record ^ (BIT(7))) | (BIT(6))) & 0xC0);
+		HALMAC_REG_WRITE_8(pHalmac_adapter, REG_SDIO_HRPWM1, rpwm);
+
+		cpwm = (u8)((cpwm ^ BIT(7)) & BIT(7));
+		counter = 100;
+		while (cpwm != (HALMAC_REG_READ_8(pHalmac_adapter, REG_SDIO_HRPWM1) & BIT(7))) {
+			PLATFORM_RTL_DELAY_US(pDriver_adapter, 50);
+			counter--;
+			if (0 == counter)
+				return HALMAC_RET_CHANGE_PS_FAIL;
+		}
+		pHalmac_adapter->low_clk = _FALSE;
+	}
+
+	PLATFORM_RTL_MEMCPY(pDriver_adapter, &fw_lps_option, &(pHalmac_adapter->fwlps_option), sizeof(HALMAC_FWLPS_OPTION));
+	fw_lps_option.mode = 0;
+
+	status = halmac_send_h2c_set_pwr_mode_88xx(pHalmac_adapter, &(fw_lps_option));
+	if (HALMAC_RET_SUCCESS != status) {
+		PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_PWR, HALMAC_DBG_ERR, "halmac_send_h2c_set_pwr_mode_88xx error!!=%x\n", status);
+		return status;
+	}
+
+	pHalmac_adapter->halmac_state.ps_state = HALMAC_PS_STATE_ACT;
+
+	PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_PWR, HALMAC_DBG_TRACE, "halmac_leave_ps_88xx <==========\n");
+
+	return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * (debug API)halmac_h2c_lb_88xx() - send h2c loopback packet
+ * @pHalmac_adapter : the adapter of halmac
+ * Author : KaiYuan Chang/Ivan Lin
+ * Return : HALMAC_RET_STATUS
+ * More details of status code can be found in prototype document
+ */
+HALMAC_RET_STATUS
+halmac_h2c_lb_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter
+)
+{
+	VOID *pDriver_adapter = NULL;
+
+	if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter))
+		return HALMAC_RET_ADAPTER_INVALID;
+
+	if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter))
+		return HALMAC_RET_API_INVALID;
+
+	halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_H2C_LB);
+
+	pDriver_adapter = pHalmac_adapter->pDriver_adapter;
+
+	PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_h2c_lb_88xx ==========>\n");
+
+	PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_h2c_lb_88xx <==========\n");
+
+	return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * halmac_debug_88xx() - dump information for debugging
+ * @pHalmac_adapter : the adapter of halmac
+ * Author : KaiYuan Chang/Ivan Lin
+ * Return : HALMAC_RET_STATUS
+ * More details of status code can be found in prototype document
+ */
+HALMAC_RET_STATUS
+halmac_debug_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter
+)
+{
+	u8 temp8 = 0;
+	u32 i = 0, temp32 = 0;
+	VOID *pDriver_adapter = NULL;
+	PHALMAC_API pHalmac_api;
+
+	if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter))
+		return HALMAC_RET_ADAPTER_INVALID;
+
+	if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter))
+		return HALMAC_RET_API_INVALID;
+
+	halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_DEBUG);
+
+	pDriver_adapter = pHalmac_adapter->pDriver_adapter;
+	pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api;
+
+	PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_debug_88xx ==========>\n");
+
+	if (HALMAC_INTERFACE_SDIO == pHalmac_adapter->halmac_interface) {
+		/* Dump CCCR, it needs new platform api */
+
+		/*Dump SDIO Local Register, use CMD52*/
+		for (i = 0x10250000; i < 0x102500ff; i++) {
+			temp8 = PLATFORM_SDIO_CMD52_READ(pHalmac_adapter, i);
+			PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_debug: sdio[%x]=%x\n", i, temp8);
+		}
+
+		/*Dump MAC Register*/
+		for (i = 0x0000; i < 0x17ff; i++) {
+			temp8 = PLATFORM_SDIO_CMD52_READ(pHalmac_adapter, i);
+			PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_debug: mac[%x]=%x\n", i, temp8);
+		}
+
+		/*Check RX Fifo status*/
+		i = REG_RXFF_PTR_V1;
+		temp8 = PLATFORM_SDIO_CMD52_READ(pHalmac_adapter, i);
+		PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_debug: mac[%x]=%x\n", i, temp8);
+		i = REG_RXFF_WTR_V1;
+		temp8 = PLATFORM_SDIO_CMD52_READ(pHalmac_adapter, i);
+		PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_debug: mac[%x]=%x\n", i, temp8);
+		i = REG_RXFF_PTR_V1;
+		temp8 = PLATFORM_SDIO_CMD52_READ(pHalmac_adapter, i);
+		PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_debug: mac[%x]=%x\n", i, temp8);
+		i = REG_RXFF_WTR_V1;
+		temp8 = PLATFORM_SDIO_CMD52_READ(pHalmac_adapter, i);
+		PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_debug: mac[%x]=%x\n", i, temp8);
+	} else {
+		/*Dump MAC Register*/
+		for (i = 0x0000; i < 0x17fc; i += 4) {
+			temp32 = HALMAC_REG_READ_32(pHalmac_adapter, i);
+			PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_debug: mac[%x]=%x\n", i, temp32);
+		}
+
+		/*Check RX Fifo status*/
+		i = REG_RXFF_PTR_V1;
+		temp32 = HALMAC_REG_READ_32(pHalmac_adapter, i);
+		PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_debug: mac[%x]=%x\n", i, temp32);
+		i = REG_RXFF_WTR_V1;
+		temp32 = HALMAC_REG_READ_32(pHalmac_adapter, i);
+		PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_debug: mac[%x]=%x\n", i, temp32);
+		i = REG_RXFF_PTR_V1;
+		temp32 = HALMAC_REG_READ_32(pHalmac_adapter, i);
+		PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_debug: mac[%x]=%x\n", i, temp32);
+		i = REG_RXFF_WTR_V1;
+		temp32 = HALMAC_REG_READ_32(pHalmac_adapter, i);
+		PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_debug: mac[%x]=%x\n", i, temp32);
+	}
+
+	/*	TODO: Add check register code, including MAC CLK, CPU CLK */
+
+	PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_debug_88xx <==========\n");
+
+	return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * halmac_cfg_parameter_88xx() - config parameter by FW
+ * @pHalmac_adapter : the adapter of halmac
+ * @para_info : cmd id, content
+ * @full_fifo : parameter information
+ *
+ * If msk_en = _TRUE, the format of array is {reg_info, mask, value}.
+ * If msk_en =_FAUSE, the format of array is {reg_info, value}
+ * The format of reg_info is
+ * reg_info[31]=rf_reg, 0: MAC_BB reg, 1: RF reg
+ * reg_info[27:24]=rf_path, 0: path_A, 1: path_B
+ * if rf_reg=0(MAC_BB reg), rf_path is meaningless.
+ * ref_info[15:0]=offset
+ *
+ * Example: msk_en = _FALSE
+ * {0x8100000a, 0x00001122}
+ * =>Set RF register, path_B, offset 0xA to 0x00001122
+ * {0x00000824, 0x11224433}
+ * =>Set MAC_BB register, offset 0x800 to 0x11224433
+ *
+ * Note : full fifo mode only for init flow
+ *
+ * Author : KaiYuan Chang/Ivan Lin
+ * Return : HALMAC_RET_STATUS
+ * More details of status code can be found in prototype document
+ */
+HALMAC_RET_STATUS
+halmac_cfg_parameter_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN PHALMAC_PHY_PARAMETER_INFO para_info,
+	IN u8 full_fifo
+)
+{
+	VOID *pDriver_adapter = NULL;
+	HALMAC_RET_STATUS ret_status = HALMAC_RET_SUCCESS;
+	HALMAC_CMD_PROCESS_STATUS *pProcess_status = &(pHalmac_adapter->halmac_state.cfg_para_state_set.process_status);
+
+	if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter))
+		return HALMAC_RET_ADAPTER_INVALID;
+
+	if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter))
+		return HALMAC_RET_API_INVALID;
+
+	if (HALMAC_RET_SUCCESS != halmac_fw_validate(pHalmac_adapter))
+		return HALMAC_RET_NO_DLFW;
+
+	if (pHalmac_adapter->fw_version.h2c_version < 4)
+		return HALMAC_RET_FW_NO_SUPPORT;
+
+	halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_CFG_PARAMETER);
+
+	pDriver_adapter = pHalmac_adapter->pDriver_adapter;
+
+	/* PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_cfg_parameter_88xx ==========>\n"); */
+
+	if (HALMAC_DLFW_NONE == pHalmac_adapter->halmac_state.dlfw_state) {
+		PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "halmac_cfg_parameter_88xx Fail due to DLFW NONE!!\n");
+		return HALMAC_RET_DLFW_FAIL;
+	}
+
+	if (HALMAC_CMD_PROCESS_SENDING == *pProcess_status) {
+		PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "Wait event(cfg para)...\n");
+		return HALMAC_RET_BUSY_STATE;
+	}
+
+	if ((HALMAC_CFG_PARA_CMD_CONSTRUCT_IDLE != halmac_query_cfg_para_curr_state_88xx(pHalmac_adapter)) &&
+	    (HALMAC_CFG_PARA_CMD_CONSTRUCT_CONSTRUCTING != halmac_query_cfg_para_curr_state_88xx(pHalmac_adapter))) {
+		PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "Not idle state(cfg para)...\n");
+		return HALMAC_RET_BUSY_STATE;
+	}
+
+	*pProcess_status = HALMAC_CMD_PROCESS_IDLE;
+
+	ret_status = halmac_send_h2c_phy_parameter_88xx(pHalmac_adapter, para_info, full_fifo);
+
+	if (HALMAC_RET_SUCCESS != ret_status) {
+		PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "halmac_send_h2c_phy_parameter_88xx Fail!! = %x\n", ret_status);
+		return ret_status;
+	}
+
+	/* PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_cfg_parameter_88xx <==========\n"); */
+
+	return ret_status;
+}
+
+/**
+ * halmac_update_packet_88xx() - send specific packet to FW
+ * @pHalmac_adapter : the adapter of halmac
+ * @pkt_id : packet id, to know the purpose of this packet
+ * @pkt : packet
+ * @pkt_size : packet size
+ *
+ * Note : TX_DESC is not included in the pkt
+ *
+ * Author : KaiYuan Chang/Ivan Lin
+ * Return : HALMAC_RET_STATUS
+ * More details of status code can be found in prototype document
+ */
+HALMAC_RET_STATUS
+halmac_update_packet_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN HALMAC_PACKET_ID	pkt_id,
+	IN u8 *pkt,
+	IN u32 pkt_size
+)
+{
+	VOID *pDriver_adapter = NULL;
+	PHALMAC_API pHalmac_api;
+	HALMAC_RET_STATUS status = HALMAC_RET_SUCCESS;
+	HALMAC_CMD_PROCESS_STATUS *pProcess_status = &(pHalmac_adapter->halmac_state.update_packet_set.process_status);
+
+	if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter))
+		return HALMAC_RET_ADAPTER_INVALID;
+
+	if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter))
+		return HALMAC_RET_API_INVALID;
+
+	if (HALMAC_RET_SUCCESS != halmac_fw_validate(pHalmac_adapter))
+		return HALMAC_RET_NO_DLFW;
+
+	if (pHalmac_adapter->fw_version.h2c_version < 4)
+		return HALMAC_RET_FW_NO_SUPPORT;
+
+	halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_UPDATE_PACKET);
+
+	pDriver_adapter = pHalmac_adapter->pDriver_adapter;
+	pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api;
+
+	PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_update_packet_88xx ==========>\n");
+
+	if (HALMAC_CMD_PROCESS_SENDING == *pProcess_status) {
+		PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "Wait event(update_packet)...\n");
+		return HALMAC_RET_BUSY_STATE;
+	}
+
+	*pProcess_status = HALMAC_CMD_PROCESS_SENDING;
+
+	status = halmac_send_h2c_update_packet_88xx(pHalmac_adapter, pkt_id, pkt, pkt_size);
+
+	if (HALMAC_RET_SUCCESS != status) {
+		PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "halmac_send_h2c_update_packet_88xx packet = %x,  fail = %x!!\n", pkt_id, status);
+		return status;
+	}
+
+	PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_update_packet_88xx <==========\n");
+
+	return HALMAC_RET_SUCCESS;
+}
+
+HALMAC_RET_STATUS
+halmac_bcn_ie_filter_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN PHALMAC_BCN_IE_INFO pBcn_ie_info
+)
+{
+	VOID *pDriver_adapter = NULL;
+	HALMAC_RET_STATUS status = HALMAC_RET_SUCCESS;
+
+	if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter))
+		return HALMAC_RET_ADAPTER_INVALID;
+
+	if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter))
+		return HALMAC_RET_API_INVALID;
+
+	if (HALMAC_RET_SUCCESS != halmac_fw_validate(pHalmac_adapter))
+		return HALMAC_RET_NO_DLFW;
+
+	if (pHalmac_adapter->fw_version.h2c_version < 4)
+		return HALMAC_RET_FW_NO_SUPPORT;
+
+	halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_BCN_IE_FILTER);
+
+	pDriver_adapter = pHalmac_adapter->pDriver_adapter;
+
+	PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_bcn_ie_filter_88xx ==========>\n");
+
+	status = halmac_send_h2c_update_bcn_parse_info_88xx(pHalmac_adapter, pBcn_ie_info);
+
+	if (HALMAC_RET_SUCCESS != status) {
+		PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "halmac_send_h2c_update_bcn_parse_info_88xx fail = %x\n", status);
+		return status;
+	}
+
+	PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_bcn_ie_filter_88xx <==========\n");
+
+	return HALMAC_RET_SUCCESS;
+}
+
+HALMAC_RET_STATUS
+halmac_update_datapack_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN HALMAC_DATA_TYPE halmac_data_type,
+	IN PHALMAC_PHY_PARAMETER_INFO para_info
+)
+{
+	VOID *pDriver_adapter = NULL;
+
+	if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter))
+		return HALMAC_RET_ADAPTER_INVALID;
+
+	if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter))
+		return HALMAC_RET_API_INVALID;
+
+	if (HALMAC_RET_SUCCESS != halmac_fw_validate(pHalmac_adapter))
+		return HALMAC_RET_NO_DLFW;
+
+	if (pHalmac_adapter->fw_version.h2c_version < 4)
+		return HALMAC_RET_FW_NO_SUPPORT;
+
+	PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "[TRACE]halmac_update_datapack_88xx ==========>\n");
+
+	pDriver_adapter = pHalmac_adapter->pDriver_adapter;
+
+	PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "[TRACE]halmac_update_datapack_88xx <==========\n");
+
+	return HALMAC_RET_SUCCESS;
+}
+
+HALMAC_RET_STATUS
+halmac_run_datapack_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN HALMAC_DATA_TYPE halmac_data_type
+)
+{
+	VOID *pDriver_adapter = NULL;
+	HALMAC_RET_STATUS ret_status = HALMAC_RET_SUCCESS;
+
+	if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter))
+		return HALMAC_RET_ADAPTER_INVALID;
+
+	if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter))
+		return HALMAC_RET_API_INVALID;
+
+	if (HALMAC_RET_SUCCESS != halmac_fw_validate(pHalmac_adapter))
+		return HALMAC_RET_NO_DLFW;
+
+	if (pHalmac_adapter->fw_version.h2c_version < 4)
+		return HALMAC_RET_FW_NO_SUPPORT;
+
+	halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_RUN_DATAPACK);
+
+	pDriver_adapter = pHalmac_adapter->pDriver_adapter;
+
+	PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_run_datapack_88xx ==========>\n");
+
+	ret_status = halmac_send_h2c_run_datapack_88xx(pHalmac_adapter, halmac_data_type);
+
+	if (HALMAC_RET_SUCCESS != ret_status) {
+		PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "halmac_send_h2c_run_datapack_88xx Fail, datatype = %x, status = %x!!\n", halmac_data_type, ret_status);
+		return ret_status;
+	}
+
+	PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_update_datapack_88xx <==========\n");
+
+	return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * halmac_cfg_drv_info_88xx() - config driver info
+ * @pHalmac_adapter : the adapter of halmac
+ * @halmac_drv_info : driver information selection
+ * Author : KaiYuan Chang/Ivan Lin
+ * Return : HALMAC_RET_STATUS
+ * More details of status code can be found in prototype document
+ */
+HALMAC_RET_STATUS
+halmac_cfg_drv_info_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN HALMAC_DRV_INFO halmac_drv_info
+)
+{
+	u8 drv_info_size = 0;
+	u8 phy_status_en = 0;
+	u8 sniffer_en = 0;
+	u8 plcp_hdr_en = 0;
+	u32 value32;
+	VOID *pDriver_adapter = NULL;
+	PHALMAC_API pHalmac_api;
+	HALMAC_RET_STATUS status = HALMAC_RET_SUCCESS;
+
+	if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter))
+		return HALMAC_RET_ADAPTER_INVALID;
+
+	if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter))
+		return HALMAC_RET_API_INVALID;
+
+	halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_CFG_DRV_INFO);
+
+	pDriver_adapter = pHalmac_adapter->pDriver_adapter;
+	pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api;
+
+	PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_cfg_drv_info_88xx ==========>\n");
+
+	PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_cfg_drv_info = %d\n", halmac_drv_info);
+
+	switch (halmac_drv_info) {
+	case HALMAC_DRV_INFO_NONE:
+		drv_info_size = 0;
+		phy_status_en = 0;
+		sniffer_en = 0;
+		plcp_hdr_en = 0;
+		break;
+	case HALMAC_DRV_INFO_PHY_STATUS:
+		drv_info_size = 4;
+		phy_status_en = 1;
+		sniffer_en = 0;
+		plcp_hdr_en = 0;
+		break;
+	case HALMAC_DRV_INFO_PHY_SNIFFER:
+		drv_info_size = 5; /* phy status 4byte, sniffer info 1byte */
+		phy_status_en = 1;
+		sniffer_en = 1;
+		plcp_hdr_en = 0;
+		break;
+	case HALMAC_DRV_INFO_PHY_PLCP:
+		drv_info_size = 6; /* phy status 4byte, plcp header 2byte */
+		phy_status_en = 1;
+		sniffer_en = 0;
+		plcp_hdr_en = 1;
+		break;
+	default:
+		status = HALMAC_RET_SW_CASE_NOT_SUPPORT;
+		PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "halmac_cfg_drv_info_88xx error = %x\n", status);
+		return status;
+	}
+
+	if (HALMAC_RX_FIFO_EXPANDING_MODE_DISABLE != pHalmac_adapter->txff_allocation.rx_fifo_expanding_mode)
+		drv_info_size = HALMAC_RX_DESC_DUMMY_SIZE_MAX_88XX >> 3;
+
+	HALMAC_REG_WRITE_8(pHalmac_adapter, REG_RX_DRVINFO_SZ, drv_info_size);
+
+	pHalmac_adapter->drv_info_size = drv_info_size;
+
+	value32 = HALMAC_REG_READ_32(pHalmac_adapter, REG_RCR);
+	value32 = (value32 & (~BIT_APP_PHYSTS));
+	if (1 == phy_status_en)
+		value32 = value32 | BIT_APP_PHYSTS;
+	HALMAC_REG_WRITE_32(pHalmac_adapter, REG_RCR, value32);
+
+	value32 = HALMAC_REG_READ_32(pHalmac_adapter, REG_WMAC_OPTION_FUNCTION + 4);
+	value32 = (value32 & (~(BIT(8) | BIT(9))));
+	if (1 == sniffer_en)
+		value32 = value32 | BIT(9);
+	if (1 == plcp_hdr_en)
+		value32 = value32 | BIT(8);
+	HALMAC_REG_WRITE_32(pHalmac_adapter, REG_WMAC_OPTION_FUNCTION + 4, value32);
+
+	PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_cfg_drv_info_88xx <==========\n");
+
+	return HALMAC_RET_SUCCESS;
+}
+
+HALMAC_RET_STATUS
+halmac_send_bt_coex_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN u8 *pBt_buf,
+	IN u32 bt_size,
+	IN u8 ack
+)
+{
+	VOID *pDriver_adapter = NULL;
+	PHALMAC_API pHalmac_api;
+	HALMAC_RET_STATUS ret_status = HALMAC_RET_SUCCESS;
+
+	if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter))
+		return HALMAC_RET_ADAPTER_INVALID;
+
+	if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter))
+		return HALMAC_RET_API_INVALID;
+
+	if (HALMAC_RET_SUCCESS != halmac_fw_validate(pHalmac_adapter))
+		return HALMAC_RET_NO_DLFW;
+
+	halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_SEND_BT_COEX);
+
+	pDriver_adapter = pHalmac_adapter->pDriver_adapter;
+	pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api;
+
+	PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_send_bt_coex_88xx ==========>\n");
+
+	ret_status = halmac_send_bt_coex_cmd_88xx(pHalmac_adapter, pBt_buf, bt_size, ack);
+
+	if (HALMAC_RET_SUCCESS != ret_status) {
+		PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "halmac_send_bt_coex_cmd_88xx Fail = %x!!\n", ret_status);
+		return ret_status;
+	}
+
+	PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_send_bt_coex_88xx <==========\n");
+
+	return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * (debug API)halmac_verify_platform_api_88xx() - verify platform api
+ * @pHalmac_adapter : the adapter of halmac
+ * Author : KaiYuan Chang/Ivan Lin
+ * Return : HALMAC_RET_STATUS
+ * More details of status code can be found in prototype document
+ */
+HALMAC_RET_STATUS
+halmac_verify_platform_api_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter
+)
+{
+	VOID *pDriver_adapter = NULL;
+	HALMAC_RET_STATUS ret_status = HALMAC_RET_SUCCESS;
+
+	if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter))
+		return HALMAC_RET_ADAPTER_INVALID;
+
+	if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter))
+		return HALMAC_RET_API_INVALID;
+
+	halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_VERIFY_PLATFORM_API);
+
+	pDriver_adapter = pHalmac_adapter->pDriver_adapter;
+
+	PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_verify_platform_api_88xx ==========>\n");
+
+	ret_status = halmac_verify_io_88xx(pHalmac_adapter);
+
+	if (HALMAC_RET_SUCCESS != ret_status)
+		return ret_status;
+
+	if (HALMAC_LA_MODE_FULL != pHalmac_adapter->txff_allocation.la_mode)
+		ret_status = halmac_verify_send_rsvd_page_88xx(pHalmac_adapter);
+
+	if (HALMAC_RET_SUCCESS != ret_status)
+		return ret_status;
+
+	PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_verify_platform_api_88xx <==========\n");
+
+	return ret_status;
+}
+
+HALMAC_RET_STATUS
+halmac_send_original_h2c_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN u8 *original_h2c,
+	IN u16 *seq,
+	IN u8 ack
+)
+{
+	VOID *pDriver_adapter = NULL;
+	PHALMAC_API pHalmac_api;
+	HALMAC_RET_STATUS status = HALMAC_RET_SUCCESS;
+
+	if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter))
+		return HALMAC_RET_ADAPTER_INVALID;
+
+	if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter))
+		return HALMAC_RET_API_INVALID;
+
+	if (HALMAC_RET_SUCCESS != halmac_fw_validate(pHalmac_adapter))
+		return HALMAC_RET_NO_DLFW;
+
+	halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_SEND_ORIGINAL_H2C);
+
+	pDriver_adapter = pHalmac_adapter->pDriver_adapter;
+	pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api;
+
+	PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_send_original_h2c_88xx ==========>\n");
+
+	status = halmac_func_send_original_h2c_88xx(pHalmac_adapter, original_h2c, seq, ack);
+
+	if (HALMAC_RET_SUCCESS != status) {
+		PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "halmac_send_original_h2c FAIL = %x!!\n", status);
+		return status;
+	}
+
+	PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_send_original_h2c_88xx <==========\n");
+
+	return HALMAC_RET_SUCCESS;
+}
+
+HALMAC_RET_STATUS
+halmac_timer_2s_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter
+)
+{
+	VOID *pDriver_adapter = NULL;
+
+	if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter))
+		return HALMAC_RET_ADAPTER_INVALID;
+
+	if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter))
+		return HALMAC_RET_API_INVALID;
+
+	pDriver_adapter = pHalmac_adapter->pDriver_adapter;
+
+	PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_timer_2s_88xx ==========>\n");
+
+
+	PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_timer_2s_88xx <==========\n");
+
+	return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * halmac_fill_txdesc_check_sum_88xx() -  fill in tx desc check sum
+ * @pHalmac_adapter : the adapter of halmac
+ * @pCur_desc : tx desc packet
+ * Author : KaiYuan Chang/Ivan Lin
+ * Return : HALMAC_RET_STATUS
+ * More details of status code can be found in prototype document
+ */
+HALMAC_RET_STATUS
+halmac_fill_txdesc_check_sum_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	INOUT u8 *pCur_desc
+)
+{
+	u16 chk_result = 0;
+	u16 *pData = (u16 *)NULL;
+	u32 i;
+	VOID *pDriver_adapter = NULL;
+	PHALMAC_API pHalmac_api;
+
+	if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter))
+		return HALMAC_RET_ADAPTER_INVALID;
+
+	if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter))
+		return HALMAC_RET_API_INVALID;
+
+	halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_FILL_TXDESC_CHECKSUM);
+
+	pDriver_adapter = pHalmac_adapter->pDriver_adapter;
+	pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api;
+
+
+	if (NULL == pCur_desc) {
+		PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "halmac_fill_txdesc_check_sum_88xx NULL PTR");
+		return HALMAC_RET_NULL_POINTER;
+	}
+
+	SET_TX_DESC_TXDESC_CHECKSUM(pCur_desc, 0x0000);
+
+	pData = (u16 *)(pCur_desc);
+
+	/* HW clculates only 32byte */
+	for (i = 0; i < 8; i++)
+		chk_result ^= (*(pData + 2 * i) ^ *(pData + (2 * i + 1)));
+
+	/* *(pData + 2 * i) & *(pData + (2 * i + 1) have endain issue*/
+	/* Process eniadn issue after checksum calculation */
+	chk_result = rtk_le16_to_cpu(chk_result);
+
+	SET_TX_DESC_TXDESC_CHECKSUM(pCur_desc, chk_result);
+
+	return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * halmac_dump_fifo_88xx() - dump fifo data
+ * @pHalmac_adapter : the adapter of halmac
+ * @halmac_fifo_sel : FIFO selection
+ * @halmac_start_addr : start address of selected FIFO
+ * @halmac_fifo_dump_size : dump size of selected FIFO
+ * @pFifo_map : FIFO data
+ *
+ * Note : before dump fifo, user need to call halmac_get_fifo_size to
+ * get fifo size. Then input this size to halmac_dump_fifo.
+ *
+ * Author : Ivan Lin/KaiYuan Chang
+ * Return : HALMAC_RET_STATUS
+ * More details of status code can be found in prototype document
+ */
+HALMAC_RET_STATUS
+halmac_dump_fifo_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN HAL_FIFO_SEL halmac_fifo_sel,
+	IN u32 halmac_start_addr,
+	IN u32 halmac_fifo_dump_size,
+	OUT u8 *pFifo_map
+)
+{
+	VOID *pDriver_adapter = NULL;
+	HALMAC_RET_STATUS status = HALMAC_RET_SUCCESS;
+
+	if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter))
+		return HALMAC_RET_ADAPTER_INVALID;
+
+	if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter))
+		return HALMAC_RET_API_INVALID;
+
+	halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_DUMP_FIFO);
+
+	pDriver_adapter = pHalmac_adapter->pDriver_adapter;
+
+	PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_dump_fifo_88xx ==========>\n");
+
+	if (HAL_FIFO_SEL_TX == halmac_fifo_sel && (halmac_start_addr + halmac_fifo_dump_size) > pHalmac_adapter->hw_config_info.tx_fifo_size) {
+		PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "TX fifo dump size is too large\n");
+		return HALMAC_RET_DUMP_FIFOSIZE_INCORRECT;
+	}
+
+	if (HAL_FIFO_SEL_RX == halmac_fifo_sel && (halmac_start_addr + halmac_fifo_dump_size) > pHalmac_adapter->hw_config_info.rx_fifo_size) {
+		PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "RX fifo dump size is too large\n");
+		return HALMAC_RET_DUMP_FIFOSIZE_INCORRECT;
+	}
+
+	if (0 != (halmac_fifo_dump_size & (4 - 1))) {
+		PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "halmac_fifo_dump_size shall 4byte align\n");
+		return HALMAC_RET_DUMP_FIFOSIZE_INCORRECT;
+	}
+
+	if (NULL == pFifo_map) {
+		PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "pFifo_map address is NULL\n");
+		return HALMAC_RET_NULL_POINTER;
+	}
+
+	status = halmac_buffer_read_88xx(pHalmac_adapter, halmac_start_addr, halmac_fifo_dump_size, halmac_fifo_sel, pFifo_map);
+
+	if (HALMAC_RET_SUCCESS != status) {
+		PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "halmac_buffer_read_88xx error = %x\n", status);
+		return status;
+	}
+
+	PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_dump_fifo_88xx <==========\n");
+
+	return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * halmac_get_fifo_size_88xx() - get fifo size
+ * @pHalmac_adapter : the adapter of halmac
+ * @halmac_fifo_sel : FIFO selection
+ * Author : Ivan Lin/KaiYuan Chang
+ * Return : u32
+ * More details of status code can be found in prototype document
+ */
+u32
+halmac_get_fifo_size_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN HAL_FIFO_SEL halmac_fifo_sel
+)
+{
+	u32 fifo_size = 0;
+
+	if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter))
+		return HALMAC_RET_ADAPTER_INVALID;
+
+	if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter))
+		return HALMAC_RET_API_INVALID;
+
+	halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_GET_FIFO_SIZE);
+
+	if (HAL_FIFO_SEL_TX == halmac_fifo_sel)
+		fifo_size = pHalmac_adapter->hw_config_info.tx_fifo_size;
+	else if (HAL_FIFO_SEL_RX == halmac_fifo_sel)
+		fifo_size = pHalmac_adapter->hw_config_info.rx_fifo_size;
+	else if (HAL_FIFO_SEL_RSVD_PAGE == halmac_fifo_sel)
+		fifo_size = ((pHalmac_adapter->hw_config_info.tx_fifo_size >> HALMAC_TX_PAGE_SIZE_2_POWER_88XX)
+						- pHalmac_adapter->txff_allocation.rsvd_pg_bndy) << HALMAC_TX_PAGE_SIZE_2_POWER_88XX;
+	else if (HAL_FIFO_SEL_REPORT == halmac_fifo_sel)
+		fifo_size = 65536;
+	else if (HAL_FIFO_SEL_LLT == halmac_fifo_sel)
+		fifo_size = 65536;
+
+	return fifo_size;
+}
+
+/**
+ * halmac_cfg_txbf_88xx() - enable/disable specific user's txbf
+ * @pHalmac_adapter : the adapter of halmac
+ * @userid : su bfee userid = 0 or 1 to apply TXBF
+ * @bw : the sounding bandwidth
+ * @txbf_en : 0: disable TXBF, 1: enable TXBF
+ * Author : chunchu
+ * Return : HALMAC_RET_STATUS
+ * More details of status code can be found in prototype document
+ */
+HALMAC_RET_STATUS
+halmac_cfg_txbf_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN u8 userid,
+	IN HALMAC_BW bw,
+	IN u8 txbf_en
+)
+{
+	u16 temp42C = 0;
+	VOID *pDriver_adapter = NULL;
+	PHALMAC_API pHalmac_api;
+
+	if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter))
+		return HALMAC_RET_ADAPTER_INVALID;
+
+	if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter))
+		return HALMAC_RET_API_INVALID;
+
+	halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_CFG_TXBF);
+
+	pDriver_adapter = pHalmac_adapter->pDriver_adapter;
+	pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api;
+
+	if (txbf_en) {
+		switch (bw) {
+		case HALMAC_BW_80:
+			temp42C |= BIT_R_TXBF0_80M;
+		case HALMAC_BW_40:
+			temp42C |= BIT_R_TXBF0_40M;
+		case HALMAC_BW_20:
+			temp42C |= BIT_R_TXBF0_20M;
+			break;
+		default:
+			PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_SND, HALMAC_DBG_ERR, "halmac_cfg_txbf_88xx invalid TXBF BW setting 0x%x of userid %d\n", bw, userid);
+			return HALMAC_RET_INVALID_SOUNDING_SETTING;
+		}
+	}
+
+	switch (userid) {
+	case 0:
+		temp42C |= HALMAC_REG_READ_16(pHalmac_adapter, REG_TXBF_CTRL) & ~(BIT_R_TXBF0_20M | BIT_R_TXBF0_40M | BIT_R_TXBF0_80M);
+		HALMAC_REG_WRITE_16(pHalmac_adapter, REG_TXBF_CTRL, temp42C);
+		break;
+	case 1:
+		temp42C |= HALMAC_REG_READ_16(pHalmac_adapter, REG_TXBF_CTRL + 2) & ~(BIT_R_TXBF0_20M | BIT_R_TXBF0_40M | BIT_R_TXBF0_80M);
+		HALMAC_REG_WRITE_16(pHalmac_adapter, REG_TXBF_CTRL + 2, temp42C);
+		break;
+	default:
+		PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_SND, HALMAC_DBG_ERR, "halmac_cfg_txbf_88xx invalid userid %d\n", userid);
+		return HALMAC_RET_INVALID_SOUNDING_SETTING;
+	}
+
+	PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_SND, HALMAC_DBG_TRACE, "halmac_cfg_txbf_88xx, txbf_en = %x <==========\n", txbf_en);
+
+	return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * halmac_cfg_mumimo_88xx() -config mumimo
+ * @pHalmac_adapter : the adapter of halmac
+ * @pCfgmu : parameters to configure MU PPDU Tx/Rx
+ * Author : chunchu
+ * Return : HALMAC_RET_STATUS
+ * More details of status code can be found in prototype document
+ */
+HALMAC_RET_STATUS
+halmac_cfg_mumimo_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN PHALMAC_CFG_MUMIMO_PARA pCfgmu
+)
+{
+	VOID *pDriver_adapter = NULL;
+	PHALMAC_API pHalmac_api;
+	u8 i, idx, id0, id1, gid, mu_tab_sel;
+	u8 mu_tab_valid = 0;
+	u32 gid_valid[6] = {0};
+	u8 temp14C0 = 0;
+
+	if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter))
+		return HALMAC_RET_ADAPTER_INVALID;
+
+	if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter))
+		return HALMAC_RET_API_INVALID;
+
+	halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_CFG_MUMIMO);
+
+	pDriver_adapter = pHalmac_adapter->pDriver_adapter;
+	pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api;
+
+	if (pCfgmu->role == HAL_BFEE) {
+		/*config MU BFEE*/
+		temp14C0 = HALMAC_REG_READ_8(pHalmac_adapter, REG_MU_TX_CTL) & ~BIT_MASK_R_MU_TABLE_VALID;
+		HALMAC_REG_WRITE_8(pHalmac_adapter, REG_MU_TX_CTL, (temp14C0|BIT(0)|BIT(1)) & ~(BIT(7)));	/*enable MU table 0 and 1, disable MU TX*/
+
+		/*config GID valid table and user position table*/
+		mu_tab_sel = HALMAC_REG_READ_8(pHalmac_adapter, REG_MU_TX_CTL+1) & ~(BIT(0)|BIT(1)|BIT(2));
+		for (i = 0; i < 2; i++) {
+			HALMAC_REG_WRITE_8(pHalmac_adapter, REG_MU_TX_CTL+1, mu_tab_sel | i);
+			HALMAC_REG_WRITE_32(pHalmac_adapter, REG_MU_STA_GID_VLD, pCfgmu->given_gid_tab[i]);
+			HALMAC_REG_WRITE_32(pHalmac_adapter, REG_MU_STA_USER_POS_INFO, pCfgmu->given_user_pos[i*2]);
+			HALMAC_REG_WRITE_32(pHalmac_adapter, REG_MU_STA_USER_POS_INFO+4, pCfgmu->given_user_pos[i*2+1]);
+		}
+	} else {
+		/*config MU BFER*/
+		if (_FALSE == pCfgmu->mu_tx_en) {
+			HALMAC_REG_WRITE_8(pHalmac_adapter, REG_MU_TX_CTL, HALMAC_REG_READ_8(pHalmac_adapter, REG_MU_TX_CTL) & ~(BIT(7)));
+			PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_SND, HALMAC_DBG_TRACE, "halmac_cfg_mumimo_88xx disable mu tx <==========\n");
+			return HALMAC_RET_SUCCESS;
+		}
+
+		/*Transform BB grouping bitmap[14:0] to MAC GID_valid table*/
+		for (idx = 0; idx < 15; idx++) {
+			if (idx < 5) {
+				/*grouping_bitmap bit0~4, MU_STA0 with MUSTA1~5*/
+				id0 = 0;
+				id1 = (u8)(idx + 1);
+			} else if (idx < 9) {
+				/*grouping_bitmap bit5~8, MU_STA1 with MUSTA2~5*/
+				id0 = 1;
+				id1 = (u8)(idx - 3);
+			} else if (idx < 12) {
+				/*grouping_bitmap bit9~11, MU_STA2 with MUSTA3~5*/
+				id0 = 2;
+				id1 = (u8)(idx - 6);
+			} else if (idx < 14) {
+				/*grouping_bitmap bit12~13, MU_STA3 with MUSTA4~5*/
+				id0 = 3;
+				id1 = (u8)(idx - 8);
+			} else {
+				/*grouping_bitmap bit14, MU_STA4 with MUSTA5*/
+				id0 = 4;
+				id1 = (u8)(idx - 9);
+			}
+			if (pCfgmu->grouping_bitmap & BIT(idx)) {
+				/*Pair 1*/
+				gid = (idx << 1) + 1;
+				gid_valid[id0] |= (BIT(gid));
+				gid_valid[id1] |= (BIT(gid));
+				/*Pair 2*/
+				gid += 1;
+				gid_valid[id0] |= (BIT(gid));
+				gid_valid[id1] |= (BIT(gid));
+			} else {
+				/*Pair 1*/
+				gid = (idx << 1) + 1;
+				gid_valid[id0] &= ~(BIT(gid));
+				gid_valid[id1] &= ~(BIT(gid));
+				/*Pair 2*/
+				gid += 1;
+				gid_valid[id0] &= ~(BIT(gid));
+				gid_valid[id1] &= ~(BIT(gid));
+			}
+		}
+
+		/*set MU STA GID valid TABLE*/
+		mu_tab_sel = HALMAC_REG_READ_8(pHalmac_adapter, REG_MU_TX_CTL+1) & ~(BIT(0)|BIT(1)|BIT(2));
+		for (idx = 0; idx < 6; idx++) {
+			HALMAC_REG_WRITE_8(pHalmac_adapter, REG_MU_TX_CTL+1, idx | mu_tab_sel);
+			HALMAC_REG_WRITE_32(pHalmac_adapter, REG_MU_STA_GID_VLD, gid_valid[idx]);
+		}
+
+		/*To validate the sounding successful MU STA and enable MU TX*/
+		for (i = 0; i < 6; i++) {
+			if (_TRUE == pCfgmu->sounding_sts[i])
+				mu_tab_valid |= BIT(i);
+		}
+		HALMAC_REG_WRITE_8(pHalmac_adapter, REG_MU_TX_CTL, mu_tab_valid | BIT(7));
+	}
+	PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_SND, HALMAC_DBG_TRACE, "halmac_cfg_mumimo_88xx <==========\n");
+	return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * halmac_cfg_sounding_88xx() - configure general sounding
+ * @pHalmac_adapter : the adapter of halmac
+ * @role : driver's role, BFer or BFee
+ * @datarate : set ndpa tx rate if driver is BFer, or set csi response rate if driver is BFee
+ * Author : chunchu
+ * Return : HALMAC_RET_STATUS
+ * More details of status code can be found in prototype document
+ */
+HALMAC_RET_STATUS
+halmac_cfg_sounding_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN HALMAC_SND_ROLE role,
+	IN HALMAC_DATA_RATE	datarate
+)
+{
+	VOID *pDriver_adapter = NULL;
+	PHALMAC_API pHalmac_api;
+
+	if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter))
+		return HALMAC_RET_ADAPTER_INVALID;
+
+	if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter))
+		return HALMAC_RET_API_INVALID;
+
+	halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_CFG_SOUNDING);
+
+	pDriver_adapter = pHalmac_adapter->pDriver_adapter;
+	pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api;
+
+	switch (role) {
+	case HAL_BFER:
+		HALMAC_REG_WRITE_32(pHalmac_adapter, REG_TXBF_CTRL, HALMAC_REG_READ_32(pHalmac_adapter, REG_TXBF_CTRL) | BIT_R_ENABLE_NDPA
+			| BIT_USE_NDPA_PARAMETER | BIT_R_EN_NDPA_INT | BIT_DIS_NDP_BFEN);
+		HALMAC_REG_WRITE_8(pHalmac_adapter, REG_NDPA_RATE, datarate);
+		HALMAC_REG_WRITE_8(pHalmac_adapter, REG_NDPA_OPT_CTRL, HALMAC_REG_READ_8(pHalmac_adapter, REG_NDPA_OPT_CTRL) & (~(BIT(0) | BIT(1))));
+		HALMAC_REG_WRITE_8(pHalmac_adapter, REG_SND_PTCL_CTRL + 1, 0x2 | BIT(7));	/*service file length 2 bytes; fix non-STA1 csi start offset */
+		HALMAC_REG_WRITE_8(pHalmac_adapter, REG_SND_PTCL_CTRL + 2, 0x2);
+		break;
+	case HAL_BFEE:
+		HALMAC_REG_WRITE_8(pHalmac_adapter, REG_SND_PTCL_CTRL, 0xDB);
+		HALMAC_REG_WRITE_8(pHalmac_adapter, REG_SND_PTCL_CTRL + 3, 0x50);
+		HALMAC_REG_WRITE_8(pHalmac_adapter, REG_BBPSF_CTRL + 3, HALMAC_OFDM54 | BIT(6));		//use ndpa rx rate to decide csi rate
+		HALMAC_REG_WRITE_16(pHalmac_adapter, REG_RRSR, HALMAC_REG_READ_16(pHalmac_adapter, REG_RRSR) | BIT(datarate));
+		HALMAC_REG_WRITE_8(pHalmac_adapter, REG_RXFLTMAP1, HALMAC_REG_READ_8(pHalmac_adapter, REG_RXFLTMAP1) & (~(BIT(4))));	/*RXFF do not accept BF Rpt Poll, avoid CSI crc error*/
+		HALMAC_REG_WRITE_8(pHalmac_adapter, REG_RXFLTMAP4, HALMAC_REG_READ_8(pHalmac_adapter, REG_RXFLTMAP4) & (~(BIT(4))));	/*FWFF do not accept BF Rpt Poll, avoid CSI crc error*/
+		break;
+	default:
+		PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_SND, HALMAC_DBG_ERR, "halmac_cfg_sounding_88xx invalid role\n");
+		return HALMAC_RET_INVALID_SOUNDING_SETTING;
+	}
+
+	PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_SND, HALMAC_DBG_TRACE, "halmac_cfg_sounding_88xx <==========\n");
+
+	return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * halmac_del_sounding_88xx() - reset general sounding
+ * @pHalmac_adapter : the adapter of halmac
+ * @role : driver's role, BFer or BFee
+ * Author : chunchu
+ * Return : HALMAC_RET_STATUS
+ * More details of status code can be found in prototype document
+ */
+HALMAC_RET_STATUS
+halmac_del_sounding_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN HALMAC_SND_ROLE role
+)
+{
+	VOID *pDriver_adapter = NULL;
+	PHALMAC_API pHalmac_api;
+
+	if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter))
+		return HALMAC_RET_ADAPTER_INVALID;
+
+	if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter))
+		return HALMAC_RET_API_INVALID;
+
+	halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_DEL_SOUNDING);
+
+	pDriver_adapter = pHalmac_adapter->pDriver_adapter;
+	pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api;
+
+	switch (role) {
+	case HAL_BFER:
+		HALMAC_REG_WRITE_8(pHalmac_adapter, REG_TXBF_CTRL + 3, 0);
+		break;
+	case HAL_BFEE:
+		HALMAC_REG_WRITE_8(pHalmac_adapter, REG_SND_PTCL_CTRL, 0);
+		break;
+	default:
+		PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_SND, HALMAC_DBG_ERR, "halmac_del_sounding_88xx invalid role\n");
+		return HALMAC_RET_INVALID_SOUNDING_SETTING;
+	}
+
+	PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_SND, HALMAC_DBG_TRACE, "halmac_del_sounding_88xx <==========\n");
+
+	return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * halmac_su_bfee_entry_init_88xx() - config SU beamformee's registers
+ * @pHalmac_adapter : the adapter of halmac
+ * @userid : SU bfee userid = 0 or 1 to be added
+ * @paid : partial AID of this bfee
+ * Author : chunchu
+ * Return : HALMAC_RET_STATUS
+ * More details of status code can be found in prototype document
+ */
+HALMAC_RET_STATUS
+halmac_su_bfee_entry_init_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN u8 userid,
+	IN u16 paid
+)
+{
+	u16 temp42C = 0;
+	VOID *pDriver_adapter = NULL;
+	PHALMAC_API pHalmac_api;
+
+	if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter))
+		return HALMAC_RET_ADAPTER_INVALID;
+
+	if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter))
+		return HALMAC_RET_API_INVALID;
+
+	halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_SU_BFEE_ENTRY_INIT);
+
+	pDriver_adapter = pHalmac_adapter->pDriver_adapter;
+	pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api;
+
+	switch (userid) {
+	case 0:
+		temp42C = HALMAC_REG_READ_16(pHalmac_adapter, REG_TXBF_CTRL) & ~(BIT_MASK_R_TXBF0_AID | BIT_R_TXBF0_20M | BIT_R_TXBF0_40M | BIT_R_TXBF0_80M);
+		HALMAC_REG_WRITE_16(pHalmac_adapter, REG_TXBF_CTRL, temp42C | paid);
+		HALMAC_REG_WRITE_16(pHalmac_adapter, REG_ASSOCIATED_BFMEE_SEL, paid);
+		break;
+	case 1:
+		temp42C = HALMAC_REG_READ_16(pHalmac_adapter, REG_TXBF_CTRL + 2) & ~(BIT_MASK_R_TXBF1_AID | BIT_R_TXBF0_20M | BIT_R_TXBF0_40M | BIT_R_TXBF0_80M);
+		HALMAC_REG_WRITE_16(pHalmac_adapter, REG_TXBF_CTRL + 2, temp42C | paid);
+		HALMAC_REG_WRITE_16(pHalmac_adapter, REG_ASSOCIATED_BFMEE_SEL + 2, paid | BIT(9));
+		break;
+	default:
+		PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_SND, HALMAC_DBG_ERR, "halmac_su_bfee_entry_init_88xx invalid userid %d\n", userid);
+		return HALMAC_RET_INVALID_SOUNDING_SETTING;
+	}
+
+	PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_SND, HALMAC_DBG_TRACE, "halmac_su_bfee_entry_init_88xx <==========\n");
+
+	return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * halmac_su_bfee_entry_init_88xx() - config SU beamformer's registers
+ * @pHalmac_adapter : the adapter of halmac
+ * @pSu_bfer_init : parameters to configure SU BFER entry
+ * Author : chunchu
+ * Return : HALMAC_RET_STATUS
+ * More details of status code can be found in prototype document
+ */
+HALMAC_RET_STATUS
+halmac_su_bfer_entry_init_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN PHALMAC_SU_BFER_INIT_PARA pSu_bfer_init
+)
+{
+	u16 mac_address_H;
+	u32 mac_address_L;
+	VOID *pDriver_adapter = NULL;
+	PHALMAC_API pHalmac_api;
+
+	if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter))
+		return HALMAC_RET_ADAPTER_INVALID;
+
+	if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter))
+		return HALMAC_RET_API_INVALID;
+
+	halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_SU_BFER_ENTRY_INIT);
+
+	pDriver_adapter = pHalmac_adapter->pDriver_adapter;
+	pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api;
+
+	/* mac_address_L = bfer_address.Address_L_H.Address_Low; */
+	/* mac_address_H = bfer_address.Address_L_H.Address_High; */
+
+	mac_address_L = rtk_le32_to_cpu(pSu_bfer_init->bfer_address.Address_L_H.Address_Low);
+	mac_address_H = rtk_le16_to_cpu(pSu_bfer_init->bfer_address.Address_L_H.Address_High);
+
+	switch (pSu_bfer_init->userid) {
+	case 0:
+		HALMAC_REG_WRITE_32(pHalmac_adapter, REG_ASSOCIATED_BFMER0_INFO, mac_address_L);
+		HALMAC_REG_WRITE_16(pHalmac_adapter, REG_ASSOCIATED_BFMER0_INFO + 4, mac_address_H);
+		HALMAC_REG_WRITE_16(pHalmac_adapter, REG_ASSOCIATED_BFMER0_INFO + 6, pSu_bfer_init->paid);
+		HALMAC_REG_WRITE_16(pHalmac_adapter, REG_TX_CSI_RPT_PARAM_BW20, pSu_bfer_init->csi_para);
+		break;
+	case 1:
+		HALMAC_REG_WRITE_32(pHalmac_adapter, REG_ASSOCIATED_BFMER1_INFO, mac_address_L);
+		HALMAC_REG_WRITE_16(pHalmac_adapter, REG_ASSOCIATED_BFMER1_INFO + 4, mac_address_H);
+		HALMAC_REG_WRITE_16(pHalmac_adapter, REG_ASSOCIATED_BFMER1_INFO + 6, pSu_bfer_init->paid);
+		HALMAC_REG_WRITE_16(pHalmac_adapter, REG_TX_CSI_RPT_PARAM_BW20 + 2, pSu_bfer_init->csi_para);
+		break;
+	default:
+		PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_SND, HALMAC_DBG_ERR, "halmac_su_bfer_entry_init_88xx invalid userid %d\n", pSu_bfer_init->userid);
+		return HALMAC_RET_INVALID_SOUNDING_SETTING;
+	}
+
+	PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_SND, HALMAC_DBG_TRACE, "halmac_su_bfer_entry_init_88xx <==========\n");
+
+	return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * halmac_mu_bfee_entry_init_88xx() - config MU beamformee's registers
+ * @pHalmac_adapter : the adapter of halmac
+ * @pMu_bfee_init : parameters to configure MU BFEE entry
+ * Author : chunchu
+ * Return : HALMAC_RET_STATUS
+ * More details of status code can be found in prototype document
+ */
+HALMAC_RET_STATUS
+halmac_mu_bfee_entry_init_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN PHALMAC_MU_BFEE_INIT_PARA pMu_bfee_init
+)
+{
+	u16 temp168X = 0, temp14C0;
+	VOID *pDriver_adapter = NULL;
+	PHALMAC_API pHalmac_api;
+
+	if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter))
+		return HALMAC_RET_ADAPTER_INVALID;
+
+	if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter))
+		return HALMAC_RET_API_INVALID;
+
+	halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_MU_BFEE_ENTRY_INIT);
+
+	pDriver_adapter = pHalmac_adapter->pDriver_adapter;
+	pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api;
+
+	temp168X |= pMu_bfee_init->paid | BIT(9);
+	HALMAC_REG_WRITE_16(pHalmac_adapter, (0x1680 + pMu_bfee_init->userid * 2), temp168X);
+
+	temp14C0 = HALMAC_REG_READ_16(pHalmac_adapter, REG_MU_TX_CTL) & ~(BIT(8)|BIT(9)|BIT(10));
+	HALMAC_REG_WRITE_16(pHalmac_adapter, REG_MU_TX_CTL, temp14C0|((pMu_bfee_init->userid-2)<<8));
+	HALMAC_REG_WRITE_32(pHalmac_adapter, REG_MU_STA_GID_VLD, 0);
+	HALMAC_REG_WRITE_32(pHalmac_adapter, REG_MU_STA_USER_POS_INFO, pMu_bfee_init->user_position_l);
+	HALMAC_REG_WRITE_32(pHalmac_adapter, REG_MU_STA_USER_POS_INFO+4, pMu_bfee_init->user_position_h);
+
+	PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_SND, HALMAC_DBG_TRACE, "halmac_mu_bfee_entry_init_88xx <==========\n");
+
+	return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * halmac_mu_bfer_entry_init_88xx() - config MU beamformer's registers
+ * @pHalmac_adapter : the adapter of halmac
+ * @pMu_bfer_init : parameters to configure MU BFER entry
+ * Author : chunchu
+ * Return : HALMAC_RET_STATUS
+ * More details of status code can be found in prototype document
+ */
+HALMAC_RET_STATUS
+halmac_mu_bfer_entry_init_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN PHALMAC_MU_BFER_INIT_PARA pMu_bfer_init
+)
+{
+	u16 temp1680 = 0;
+	u16 mac_address_H;
+	u32 mac_address_L;
+	VOID *pDriver_adapter = NULL;
+	PHALMAC_API pHalmac_api;
+
+	if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter))
+		return HALMAC_RET_ADAPTER_INVALID;
+
+	if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter))
+		return HALMAC_RET_API_INVALID;
+
+	halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_MU_BFER_ENTRY_INIT);
+
+	pDriver_adapter = pHalmac_adapter->pDriver_adapter;
+	pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api;
+
+	/* mac_address_L = pHalmac_adapter->snd_info.bfer_address.Address_L_H.Address_Low; */
+	/* mac_address_H = pHalmac_adapter->snd_info.bfer_address.Address_L_H.Address_High; */
+
+	mac_address_L = rtk_le32_to_cpu(pMu_bfer_init->bfer_address.Address_L_H.Address_Low);
+	mac_address_H = rtk_le16_to_cpu(pMu_bfer_init->bfer_address.Address_L_H.Address_High);
+
+	HALMAC_REG_WRITE_32(pHalmac_adapter, REG_ASSOCIATED_BFMER0_INFO, mac_address_L);
+	HALMAC_REG_WRITE_16(pHalmac_adapter, REG_ASSOCIATED_BFMER0_INFO + 4, mac_address_H);
+	HALMAC_REG_WRITE_16(pHalmac_adapter, REG_ASSOCIATED_BFMER0_INFO + 6, pMu_bfer_init->paid);
+	HALMAC_REG_WRITE_16(pHalmac_adapter, REG_TX_CSI_RPT_PARAM_BW20, pMu_bfer_init->csi_para);
+
+	temp1680 = HALMAC_REG_READ_16(pHalmac_adapter, 0x1680) & 0xC000;
+	temp1680 |= pMu_bfer_init->my_aid | (pMu_bfer_init->csi_length_sel << 12);
+	HALMAC_REG_WRITE_16(pHalmac_adapter, 0x1680, temp1680);
+
+	PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_SND, HALMAC_DBG_TRACE, "halmac_mu_bfer_entry_init_88xx <==========\n");
+
+	return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * halmac_su_bfee_entry_del_88xx() - reset SU beamformee's registers
+ * @pHalmac_adapter : the adapter of halmac
+ * @userid : the SU BFee userid to be deleted
+ * Author : chunchu
+ * Return : HALMAC_RET_STATUS
+ * More details of status code can be found in prototype document
+ */
+HALMAC_RET_STATUS
+halmac_su_bfee_entry_del_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN u8 userid
+)
+{
+	VOID *pDriver_adapter = NULL;
+	PHALMAC_API pHalmac_api;
+
+	if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter))
+		return HALMAC_RET_ADAPTER_INVALID;
+
+	if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter))
+		return HALMAC_RET_API_INVALID;
+
+	halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_SU_BFEE_ENTRY_DEL);
+
+	pDriver_adapter = pHalmac_adapter->pDriver_adapter;
+	pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api;
+
+	switch (userid) {
+	case 0:
+		HALMAC_REG_WRITE_16(pHalmac_adapter, REG_TXBF_CTRL, HALMAC_REG_READ_16(pHalmac_adapter, REG_TXBF_CTRL) &
+			~(BIT_MASK_R_TXBF0_AID | BIT_R_TXBF0_20M | BIT_R_TXBF0_40M | BIT_R_TXBF0_80M));
+		HALMAC_REG_WRITE_16(pHalmac_adapter, REG_ASSOCIATED_BFMEE_SEL, 0);
+		break;
+	case 1:
+		HALMAC_REG_WRITE_16(pHalmac_adapter, REG_TXBF_CTRL + 2, HALMAC_REG_READ_16(pHalmac_adapter, REG_TXBF_CTRL + 2) &
+			~(BIT_MASK_R_TXBF1_AID | BIT_R_TXBF0_20M | BIT_R_TXBF0_40M | BIT_R_TXBF0_80M));
+		HALMAC_REG_WRITE_16(pHalmac_adapter, REG_ASSOCIATED_BFMEE_SEL + 2, 0);
+		break;
+	default:
+		PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_SND, HALMAC_DBG_ERR, "halmac_su_bfee_entry_del_88xx invalid userid %d\n", userid);
+		return HALMAC_RET_INVALID_SOUNDING_SETTING;
+	}
+
+	PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_SND, HALMAC_DBG_TRACE, "halmac_su_bfee_entry_del_88xx <==========\n");
+
+	return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * halmac_su_bfee_entry_del_88xx() - reset SU beamformer's registers
+ * @pHalmac_adapter : the adapter of halmac
+ * @userid : the SU BFer userid to be deleted
+ * Author : chunchu
+ * Return : HALMAC_RET_STATUS
+ * More details of status code can be found in prototype document
+ */
+HALMAC_RET_STATUS
+halmac_su_bfer_entry_del_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN u8 userid
+)
+{
+	VOID *pDriver_adapter = NULL;
+	PHALMAC_API pHalmac_api;
+
+	if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter))
+		return HALMAC_RET_ADAPTER_INVALID;
+
+	if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter))
+		return HALMAC_RET_API_INVALID;
+
+	halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_SU_BFER_ENTRY_DEL);
+
+	pDriver_adapter = pHalmac_adapter->pDriver_adapter;
+	pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api;
+
+	switch (userid) {
+	case 0:
+		HALMAC_REG_WRITE_32(pHalmac_adapter, REG_ASSOCIATED_BFMER0_INFO, 0);
+		HALMAC_REG_WRITE_32(pHalmac_adapter, REG_ASSOCIATED_BFMER0_INFO + 4, 0);
+		break;
+	case 1:
+		HALMAC_REG_WRITE_32(pHalmac_adapter, REG_ASSOCIATED_BFMER1_INFO, 0);
+		HALMAC_REG_WRITE_32(pHalmac_adapter, REG_ASSOCIATED_BFMER1_INFO + 4, 0);
+		break;
+	default:
+		PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_SND, HALMAC_DBG_ERR, "halmac_su_bfer_entry_del_88xx invalid userid %d\n", userid);
+		return HALMAC_RET_INVALID_SOUNDING_SETTING;
+	}
+
+	PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_SND, HALMAC_DBG_TRACE, "halmac_su_bfer_entry_del_88xx <==========\n");
+
+	return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * halmac_mu_bfee_entry_del_88xx() - reset MU beamformee's registers
+ * @pHalmac_adapter : the adapter of halmac
+ * @userid : the MU STA userid to be deleted
+ * Author : chunchu
+ * Return : HALMAC_RET_STATUS
+ * More details of status code can be found in prototype document
+ */
+HALMAC_RET_STATUS
+halmac_mu_bfee_entry_del_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN u8 userid
+)
+{
+	VOID *pDriver_adapter = NULL;
+	PHALMAC_API pHalmac_api;
+
+	if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter))
+		return HALMAC_RET_ADAPTER_INVALID;
+
+	if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter))
+		return HALMAC_RET_API_INVALID;
+
+	halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_MU_BFEE_ENTRY_DEL);
+
+	pDriver_adapter = pHalmac_adapter->pDriver_adapter;
+	pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api;
+
+	HALMAC_REG_WRITE_16(pHalmac_adapter, 0x1680 + userid * 2, 0);
+	HALMAC_REG_WRITE_8(pHalmac_adapter, REG_MU_TX_CTL, HALMAC_REG_READ_8(pHalmac_adapter, REG_MU_TX_CTL) & ~(BIT(userid-2)));
+
+	PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_SND, HALMAC_DBG_TRACE, "halmac_mu_bfee_entry_del_88xx <==========\n");
+
+	return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * halmac_mu_bfer_entry_del_88xx() -reset MU beamformer's registers
+ * @pHalmac_adapter : the adapter of halmac
+ * Author : chunchu
+ * Return : HALMAC_RET_STATUS
+ * More details of status code can be found in prototype document
+ */
+HALMAC_RET_STATUS
+halmac_mu_bfer_entry_del_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter
+)
+{
+	VOID *pDriver_adapter = NULL;
+	PHALMAC_API pHalmac_api;
+
+	if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter))
+		return HALMAC_RET_ADAPTER_INVALID;
+
+	if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter))
+		return HALMAC_RET_API_INVALID;
+
+	halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_MU_BFER_ENTRY_DEL);
+
+	pDriver_adapter = pHalmac_adapter->pDriver_adapter;
+	pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api;
+
+	HALMAC_REG_WRITE_32(pHalmac_adapter, REG_ASSOCIATED_BFMER0_INFO, 0);
+	HALMAC_REG_WRITE_32(pHalmac_adapter, REG_ASSOCIATED_BFMER0_INFO + 4, 0);
+	HALMAC_REG_WRITE_16(pHalmac_adapter, 0x1680, 0);
+	HALMAC_REG_WRITE_8(pHalmac_adapter, REG_MU_TX_CTL, 0);
+
+	PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_SND, HALMAC_DBG_TRACE, "halmac_mu_bfer_entry_del_88xx <==========\n");
+
+	return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * halmac_add_ch_info_88xx() -add channel information
+ * @pHalmac_adapter : the adapter of halmac
+ * @pCh_info : channel information
+ * Author : KaiYuan Chang/Ivan Lin
+ * Return : HALMAC_RET_STATUS
+ * More details of status code can be found in prototype document
+ */
+HALMAC_RET_STATUS
+halmac_add_ch_info_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN PHALMAC_CH_INFO pCh_info
+)
+{
+	VOID *pDriver_adapter = NULL;
+	PHALMAC_CS_INFO pCh_sw_info;
+	HALMAC_SCAN_CMD_CONSTRUCT_STATE state_scan;
+
+	if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter))
+		return HALMAC_RET_ADAPTER_INVALID;
+
+	if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter))
+		return HALMAC_RET_API_INVALID;
+
+	pDriver_adapter = pHalmac_adapter->pDriver_adapter;
+	pCh_sw_info = &(pHalmac_adapter->ch_sw_info);
+
+	PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "[TRACE]halmac_add_ch_info_88xx ==========>\n");
+
+	if (HALMAC_GEN_INFO_SENT != pHalmac_adapter->halmac_state.dlfw_state) {
+		PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "[ERR]halmac_add_ch_info_88xx: gen_info is not send to FW!!!!\n");
+		return HALMAC_RET_GEN_INFO_NOT_SENT;
+	}
+
+	state_scan = halmac_query_scan_curr_state_88xx(pHalmac_adapter);
+	if ((HALMAC_SCAN_CMD_CONSTRUCT_BUFFER_CLEARED != state_scan) && (HALMAC_SCAN_CMD_CONSTRUCT_CONSTRUCTING != state_scan)) {
+		PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_WARN, "[WARN]Scan machine fail(add ch info)...\n");
+		return HALMAC_RET_ERROR_STATE;
+	}
+
+	if (NULL == pCh_sw_info->ch_info_buf) {
+		pCh_sw_info->ch_info_buf = (u8 *)PLATFORM_RTL_MALLOC(pDriver_adapter, HALMAC_EXTRA_INFO_BUFF_SIZE_88XX);
+		if (NULL == pCh_sw_info->ch_info_buf)
+			return HALMAC_RET_NULL_POINTER;
+		pCh_sw_info->ch_info_buf_w = pCh_sw_info->ch_info_buf;
+		pCh_sw_info->buf_size = HALMAC_EXTRA_INFO_BUFF_SIZE_88XX;
+		pCh_sw_info->avai_buf_size = HALMAC_EXTRA_INFO_BUFF_SIZE_88XX;
+		pCh_sw_info->total_size = 0;
+		pCh_sw_info->extra_info_en = 0;
+		pCh_sw_info->ch_num = 0;
+	}
+
+	if (1 == pCh_sw_info->extra_info_en) {
+		PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "[ERR]halmac_add_ch_info_88xx: construct sequence wrong!!\n");
+		return HALMAC_RET_CH_SW_SEQ_WRONG;
+	}
+
+	if (4 > pCh_sw_info->avai_buf_size) {
+		PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "[ERR]halmac_add_ch_info_88xx: no available buffer!!\n");
+		return HALMAC_RET_CH_SW_NO_BUF;
+	}
+
+	if (HALMAC_RET_SUCCESS != halmac_transition_scan_state_88xx(pHalmac_adapter, HALMAC_SCAN_CMD_CONSTRUCT_CONSTRUCTING))
+		return HALMAC_RET_ERROR_STATE;
+
+	CHANNEL_INFO_SET_CHANNEL(pCh_sw_info->ch_info_buf_w, pCh_info->channel);
+	CHANNEL_INFO_SET_PRI_CH_IDX(pCh_sw_info->ch_info_buf_w, pCh_info->pri_ch_idx);
+	CHANNEL_INFO_SET_BANDWIDTH(pCh_sw_info->ch_info_buf_w, pCh_info->bw);
+	CHANNEL_INFO_SET_TIMEOUT(pCh_sw_info->ch_info_buf_w, pCh_info->timeout);
+	CHANNEL_INFO_SET_ACTION_ID(pCh_sw_info->ch_info_buf_w, pCh_info->action_id);
+	CHANNEL_INFO_SET_CH_EXTRA_INFO(pCh_sw_info->ch_info_buf_w, pCh_info->extra_info);
+
+	pCh_sw_info->avai_buf_size = pCh_sw_info->avai_buf_size - 4;
+	pCh_sw_info->total_size = pCh_sw_info->total_size + 4;
+	pCh_sw_info->ch_num++;
+	pCh_sw_info->extra_info_en = pCh_info->extra_info;
+	pCh_sw_info->ch_info_buf_w = pCh_sw_info->ch_info_buf_w + 4;
+
+	PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "[TRACE]halmac_add_ch_info_88xx <==========\n");
+
+	return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * halmac_add_extra_ch_info_88xx() -add extra channel information
+ * @pHalmac_adapter : the adapter of halmac
+ * @pCh_extra_info : extra channel information
+ * Author : KaiYuan Chang/Ivan Lin
+ * Return : HALMAC_RET_STATUS
+ * More details of status code can be found in prototype document
+ */
+HALMAC_RET_STATUS
+halmac_add_extra_ch_info_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN PHALMAC_CH_EXTRA_INFO pCh_extra_info
+)
+{
+	VOID *pDriver_adapter = NULL;
+	PHALMAC_CS_INFO pCh_sw_info;
+
+	if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter))
+		return HALMAC_RET_ADAPTER_INVALID;
+
+	if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter))
+		return HALMAC_RET_API_INVALID;
+
+	halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_ADD_EXTRA_CH_INFO);
+
+	pDriver_adapter = pHalmac_adapter->pDriver_adapter;
+	pCh_sw_info = &(pHalmac_adapter->ch_sw_info);
+
+	PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_add_extra_ch_info_88xx ==========>\n");
+
+	if (NULL == pCh_sw_info->ch_info_buf) {
+		PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "halmac_add_extra_ch_info_88xx: NULL==pCh_sw_info->ch_info_buf!!\n");
+		return HALMAC_RET_CH_SW_SEQ_WRONG;
+	}
+
+	if (0 == pCh_sw_info->extra_info_en) {
+		PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "halmac_add_extra_ch_info_88xx: construct sequence wrong!!\n");
+		return HALMAC_RET_CH_SW_SEQ_WRONG;
+	}
+
+	if (pCh_sw_info->avai_buf_size < (u32)(pCh_extra_info->extra_info_size + 2)) {/* 2:ch_extra_info_id, ch_extra_info, ch_extra_info_size are totally 2Byte */
+		PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "halmac_add_extra_ch_info_88xx: no available buffer!!\n");
+		return HALMAC_RET_CH_SW_NO_BUF;
+	}
+
+	if (HALMAC_SCAN_CMD_CONSTRUCT_CONSTRUCTING != halmac_query_scan_curr_state_88xx(pHalmac_adapter)) {
+		PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "Scan machine fail(add extra ch info)...\n");
+		return HALMAC_RET_ERROR_STATE;
+	}
+
+	if (HALMAC_RET_SUCCESS != halmac_transition_scan_state_88xx(pHalmac_adapter, HALMAC_SCAN_CMD_CONSTRUCT_CONSTRUCTING))
+		return HALMAC_RET_ERROR_STATE;
+
+	CH_EXTRA_INFO_SET_CH_EXTRA_INFO_ID(pCh_sw_info->ch_info_buf_w, pCh_extra_info->extra_action_id);
+	CH_EXTRA_INFO_SET_CH_EXTRA_INFO(pCh_sw_info->ch_info_buf_w, pCh_extra_info->extra_info);
+	CH_EXTRA_INFO_SET_CH_EXTRA_INFO_SIZE(pCh_sw_info->ch_info_buf_w, pCh_extra_info->extra_info_size);
+	PLATFORM_RTL_MEMCPY(pDriver_adapter, pCh_sw_info->ch_info_buf_w + 2, pCh_extra_info->extra_info_data, pCh_extra_info->extra_info_size);
+
+	pCh_sw_info->avai_buf_size = pCh_sw_info->avai_buf_size - (2 + pCh_extra_info->extra_info_size);
+	pCh_sw_info->total_size = pCh_sw_info->total_size + (2 + pCh_extra_info->extra_info_size);
+	pCh_sw_info->extra_info_en = pCh_extra_info->extra_info;
+	pCh_sw_info->ch_info_buf_w = pCh_sw_info->ch_info_buf_w + (2 + pCh_extra_info->extra_info_size);
+
+	PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_add_extra_ch_info_88xx <==========\n");
+
+	return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * halmac_ctrl_ch_switch_88xx() -send channel switch cmd
+ * @pHalmac_adapter : the adapter of halmac
+ * @pCs_option : channel switch config
+ * Author : KaiYuan Chang/Ivan Lin
+ * Return : HALMAC_RET_STATUS
+ * More details of status code can be found in prototype document
+ */
+HALMAC_RET_STATUS
+halmac_ctrl_ch_switch_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN PHALMAC_CH_SWITCH_OPTION	pCs_option
+)
+{
+	VOID *pDriver_adapter = NULL;
+	PHALMAC_API pHalmac_api;
+	HALMAC_RET_STATUS status = HALMAC_RET_SUCCESS;
+	HALMAC_SCAN_CMD_CONSTRUCT_STATE state_scan;
+	HALMAC_CMD_PROCESS_STATUS *pProcess_status = &(pHalmac_adapter->halmac_state.scan_state_set.process_status);
+
+	if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter))
+		return HALMAC_RET_ADAPTER_INVALID;
+
+	if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter))
+		return HALMAC_RET_API_INVALID;
+
+	if (HALMAC_RET_SUCCESS != halmac_fw_validate(pHalmac_adapter))
+		return HALMAC_RET_NO_DLFW;
+
+	if (pHalmac_adapter->fw_version.h2c_version < 4)
+		return HALMAC_RET_FW_NO_SUPPORT;
+
+	halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_CTRL_CH_SWITCH);
+
+	pDriver_adapter = pHalmac_adapter->pDriver_adapter;
+	pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api;
+
+	PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_ctrl_ch_switch_88xx  pCs_option->switch_en = %d==========>\n", pCs_option->switch_en);
+
+	if (_FALSE == pCs_option->switch_en)
+		*pProcess_status = HALMAC_CMD_PROCESS_IDLE;
+
+	if ((HALMAC_CMD_PROCESS_SENDING == *pProcess_status) || (HALMAC_CMD_PROCESS_RCVD == *pProcess_status)) {
+		PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "Wait event(ctrl ch switch)...\n");
+		return HALMAC_RET_BUSY_STATE;
+	}
+
+	state_scan = halmac_query_scan_curr_state_88xx(pHalmac_adapter);
+	if (_TRUE == pCs_option->switch_en) {
+		if (HALMAC_SCAN_CMD_CONSTRUCT_CONSTRUCTING != state_scan) {
+			PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_ctrl_ch_switch_88xx(on)  invalid in state %x\n", state_scan);
+			return HALMAC_RET_ERROR_STATE;
+		}
+	} else {
+		if (HALMAC_SCAN_CMD_CONSTRUCT_BUFFER_CLEARED != state_scan) {
+			PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_ctrl_ch_switch_88xx(off)  invalid in state %x\n", state_scan);
+			return HALMAC_RET_ERROR_STATE;
+		}
+	}
+
+	status = halmac_func_ctrl_ch_switch_88xx(pHalmac_adapter, pCs_option);
+
+	if (HALMAC_RET_SUCCESS != status) {
+		PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "halmac_ctrl_ch_switch FAIL = %x!!\n", status);
+		return status;
+	}
+
+	PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_ctrl_ch_switch_88xx <==========\n");
+
+	return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * halmac_clear_ch_info_88xx() -clear channel information
+ * @pHalmac_adapter : the adapter of halmac
+ * Author : KaiYuan Chang/Ivan Lin
+ * Return : HALMAC_RET_STATUS
+ * More details of status code can be found in prototype document
+ */
+HALMAC_RET_STATUS
+halmac_clear_ch_info_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter
+)
+{
+	VOID *pDriver_adapter = NULL;
+	PHALMAC_API pHalmac_api;
+
+	if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter))
+		return HALMAC_RET_ADAPTER_INVALID;
+
+	if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter))
+		return HALMAC_RET_API_INVALID;
+
+	halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_CLEAR_CH_INFO);
+
+	pDriver_adapter = pHalmac_adapter->pDriver_adapter;
+	pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api;
+
+	PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_clear_ch_info_88xx ==========>\n");
+
+	if (HALMAC_SCAN_CMD_CONSTRUCT_H2C_SENT == halmac_query_scan_curr_state_88xx(pHalmac_adapter)) {
+		PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "Scan machine fail(clear ch info)...\n");
+		return HALMAC_RET_ERROR_STATE;
+	}
+
+	if (HALMAC_RET_SUCCESS != halmac_transition_scan_state_88xx(pHalmac_adapter, HALMAC_SCAN_CMD_CONSTRUCT_BUFFER_CLEARED))
+		return HALMAC_RET_ERROR_STATE;
+
+	PLATFORM_RTL_FREE(pDriver_adapter, pHalmac_adapter->ch_sw_info.ch_info_buf, pHalmac_adapter->ch_sw_info.buf_size);
+	pHalmac_adapter->ch_sw_info.ch_info_buf = NULL;
+	pHalmac_adapter->ch_sw_info.ch_info_buf_w = NULL;
+	pHalmac_adapter->ch_sw_info.extra_info_en = 0;
+	pHalmac_adapter->ch_sw_info.buf_size = 0;
+	pHalmac_adapter->ch_sw_info.avai_buf_size = 0;
+	pHalmac_adapter->ch_sw_info.total_size = 0;
+	pHalmac_adapter->ch_sw_info.ch_num = 0;
+
+	PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_clear_ch_info_88xx <==========\n");
+
+	return HALMAC_RET_SUCCESS;
+}
+
+HALMAC_RET_STATUS
+halmac_p2pps_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN PHALMAC_P2PPS	pP2PPS
+)
+{
+	VOID *pDriver_adapter = NULL;
+	HALMAC_RET_STATUS status = HALMAC_RET_SUCCESS;
+
+	if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter))
+		return HALMAC_RET_ADAPTER_INVALID;
+
+	if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter))
+		return HALMAC_RET_API_INVALID;
+
+	if (HALMAC_RET_SUCCESS != halmac_fw_validate(pHalmac_adapter))
+		return HALMAC_RET_NO_DLFW;
+
+	if (pHalmac_adapter->fw_version.h2c_version < 6)
+		return HALMAC_RET_FW_NO_SUPPORT;
+
+	pDriver_adapter = pHalmac_adapter->pDriver_adapter;
+
+	status = halmac_func_p2pps_88xx(pHalmac_adapter, pP2PPS);
+
+	if (HALMAC_RET_SUCCESS != status) {
+		PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "[ERR]halmac_p2pps FAIL = %x!!\n", status);
+		return status;
+	}
+
+	return HALMAC_RET_SUCCESS;
+}
+
+static HALMAC_RET_STATUS
+halmac_func_p2pps_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN PHALMAC_P2PPS	pP2PPS
+)
+{
+	u8 pH2c_buff[HALMAC_H2C_CMD_SIZE_88XX] = { 0 };
+	u16 h2c_seq_mum = 0;
+	VOID *pDriver_adapter = NULL;
+	PHALMAC_API pHalmac_api;
+	HALMAC_H2C_HEADER_INFO h2c_header_info;
+	HALMAC_RET_STATUS status = HALMAC_RET_SUCCESS;
+
+	PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "[TRACE]halmac_p2pps !!\n");
+
+	pDriver_adapter = pHalmac_adapter->pDriver_adapter;
+	pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api;
+
+	P2PPS_SET_OFFLOAD_EN(pH2c_buff, pP2PPS->offload_en);
+	P2PPS_SET_ROLE(pH2c_buff, pP2PPS->role);
+	P2PPS_SET_CTWINDOW_EN(pH2c_buff, pP2PPS->ctwindow_en);
+	P2PPS_SET_NOA_EN(pH2c_buff, pP2PPS->noa_en);
+	P2PPS_SET_NOA_SEL(pH2c_buff, pP2PPS->noa_sel);
+	P2PPS_SET_ALLSTASLEEP(pH2c_buff, pP2PPS->all_sta_sleep);
+	P2PPS_SET_DISCOVERY(pH2c_buff, pP2PPS->discovery);
+	P2PPS_SET_P2P_PORT_ID(pH2c_buff, pP2PPS->p2p_port_id);
+	P2PPS_SET_P2P_GROUP(pH2c_buff, pP2PPS->p2p_group);
+	P2PPS_SET_P2P_MACID(pH2c_buff, pP2PPS->p2p_macid);
+
+	P2PPS_SET_CTWINDOW_LENGTH(pH2c_buff, pP2PPS->ctwindow_length);
+
+	P2PPS_SET_NOA_DURATION_PARA(pH2c_buff, pP2PPS->noa_duration_para);
+	P2PPS_SET_NOA_INTERVAL_PARA(pH2c_buff, pP2PPS->noa_interval_para);
+	P2PPS_SET_NOA_START_TIME_PARA(pH2c_buff, pP2PPS->noa_start_time_para);
+	P2PPS_SET_NOA_COUNT_PARA(pH2c_buff, pP2PPS->noa_count_para);
+
+	h2c_header_info.sub_cmd_id = SUB_CMD_ID_P2PPS;
+	h2c_header_info.content_size = 24;
+	h2c_header_info.ack = _FALSE;
+	halmac_set_fw_offload_h2c_header_88xx(pHalmac_adapter, pH2c_buff, &h2c_header_info, &h2c_seq_mum);
+
+	status = halmac_send_h2c_pkt_88xx(pHalmac_adapter, pH2c_buff, HALMAC_H2C_CMD_SIZE_88XX, _FALSE);
+
+	if (HALMAC_RET_SUCCESS != status)
+		PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "[ERR]halmac_send_h2c_p2pps_88xx Fail = %x!!\n", status);
+
+	return status;
+}
+
+/**
+ * halmac_send_general_info_88xx() -send general information to FW
+ * @pHalmac_adapter : the adapter of halmac
+ * @pGeneral_info : general information
+ * Author : KaiYuan Chang/Ivan Lin
+ * Return : HALMAC_RET_STATUS
+ * More details of status code can be found in prototype document
+ */
+HALMAC_RET_STATUS
+halmac_send_general_info_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN PHALMAC_GENERAL_INFO pGeneral_info
+)
+{
+	VOID *pDriver_adapter = NULL;
+	HALMAC_RET_STATUS status = HALMAC_RET_SUCCESS;
+
+	if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter))
+		return HALMAC_RET_ADAPTER_INVALID;
+
+	if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter))
+		return HALMAC_RET_API_INVALID;
+
+	if (HALMAC_RET_SUCCESS != halmac_fw_validate(pHalmac_adapter))
+		return HALMAC_RET_NO_DLFW;
+
+	if (pHalmac_adapter->fw_version.h2c_version < 4)
+		return HALMAC_RET_FW_NO_SUPPORT;
+
+	halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_SEND_GENERAL_INFO);
+
+	pDriver_adapter = pHalmac_adapter->pDriver_adapter;
+
+	PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_send_general_info_88xx ==========>\n");
+
+	if (HALMAC_DLFW_NONE == pHalmac_adapter->halmac_state.dlfw_state) {
+		PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "halmac_send_general_info_88xx Fail due to DLFW NONE!!\n");
+		return HALMAC_RET_DLFW_FAIL;
+	}
+
+	status = halmac_func_send_general_info_88xx(pHalmac_adapter, pGeneral_info);
+
+	if (HALMAC_RET_SUCCESS != status) {
+		PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "halmac_send_general_info error = %x\n", status);
+		return status;
+	}
+
+	if (HALMAC_DLFW_DONE == pHalmac_adapter->halmac_state.dlfw_state)
+		pHalmac_adapter->halmac_state.dlfw_state = HALMAC_GEN_INFO_SENT;
+
+	pHalmac_adapter->gen_info_valid = _TRUE;
+	PLATFORM_RTL_MEMCPY(pDriver_adapter, &(pHalmac_adapter->general_info), pGeneral_info, sizeof(HALMAC_GENERAL_INFO));
+
+	PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_send_general_info_88xx <==========\n");
+
+	return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * halmac_start_iqk_88xx() -trigger FW IQK
+ * @pHalmac_adapter : the adapter of halmac
+ * @pIqk_para : IQK parameter
+ * Author : KaiYuan Chang/Ivan Lin
+ * Return : HALMAC_RET_STATUS
+ * More details of status code can be found in prototype document
+ */
+HALMAC_RET_STATUS
+halmac_start_iqk_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN PHALMAC_IQK_PARA pIqk_para
+)
+{
+	u8 pH2c_buff[HALMAC_H2C_CMD_SIZE_88XX] = { 0 };
+	u16 h2c_seq_num = 0;
+	VOID *pDriver_adapter = NULL;
+	HALMAC_RET_STATUS status = HALMAC_RET_SUCCESS;
+	HALMAC_H2C_HEADER_INFO h2c_header_info;
+	HALMAC_CMD_PROCESS_STATUS *pProcess_status = &(pHalmac_adapter->halmac_state.iqk_set.process_status);
+
+	if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter))
+		return HALMAC_RET_ADAPTER_INVALID;
+
+	if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter))
+		return HALMAC_RET_API_INVALID;
+
+	if (HALMAC_RET_SUCCESS != halmac_fw_validate(pHalmac_adapter))
+		return HALMAC_RET_NO_DLFW;
+
+	halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_START_IQK);
+
+	pDriver_adapter = pHalmac_adapter->pDriver_adapter;
+
+	PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_start_iqk_88xx ==========>\n");
+
+	if (HALMAC_CMD_PROCESS_SENDING == *pProcess_status) {
+		PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "Wait event(iqk)...\n");
+		return HALMAC_RET_BUSY_STATE;
+	}
+
+	*pProcess_status = HALMAC_CMD_PROCESS_SENDING;
+
+	IQK_SET_CLEAR(pH2c_buff, pIqk_para->clear);
+	IQK_SET_SEGMENT_IQK(pH2c_buff, pIqk_para->segment_iqk);
+
+	h2c_header_info.sub_cmd_id = SUB_CMD_ID_IQK;
+	h2c_header_info.content_size = 1;
+	h2c_header_info.ack = _TRUE;
+	halmac_set_fw_offload_h2c_header_88xx(pHalmac_adapter, pH2c_buff, &h2c_header_info, &h2c_seq_num);
+
+	pHalmac_adapter->halmac_state.iqk_set.seq_num = h2c_seq_num;
+
+	status = halmac_send_h2c_pkt_88xx(pHalmac_adapter, pH2c_buff, HALMAC_H2C_CMD_SIZE_88XX, _TRUE);
+
+	if (HALMAC_RET_SUCCESS != status) {
+		PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "halmac_send_h2c_pkt_88xx Fail = %x!!\n", status);
+		return status;
+	}
+
+	PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_start_iqk_88xx <==========\n");
+
+	return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * halmac_ctrl_pwr_tracking_88xx() -trigger FW power tracking
+ * @pHalmac_adapter : the adapter of halmac
+ * @pPwr_tracking_opt : power tracking option
+ * Author : KaiYuan Chang/Ivan Lin
+ * Return : HALMAC_RET_STATUS
+ * More details of status code can be found in prototype document
+ */
+HALMAC_RET_STATUS
+halmac_ctrl_pwr_tracking_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN PHALMAC_PWR_TRACKING_OPTION pPwr_tracking_opt
+)
+{
+	u8 pH2c_buff[HALMAC_H2C_CMD_SIZE_88XX] = { 0 };
+	u16 h2c_seq_mum = 0;
+	VOID *pDriver_adapter = NULL;
+	HALMAC_RET_STATUS status = HALMAC_RET_SUCCESS;
+	HALMAC_H2C_HEADER_INFO h2c_header_info;
+	HALMAC_CMD_PROCESS_STATUS *pProcess_status = &(pHalmac_adapter->halmac_state.power_tracking_set.process_status);
+
+	if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter))
+		return HALMAC_RET_ADAPTER_INVALID;
+
+	if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter))
+		return HALMAC_RET_API_INVALID;
+
+	if (HALMAC_RET_SUCCESS != halmac_fw_validate(pHalmac_adapter))
+		return HALMAC_RET_NO_DLFW;
+
+	halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_CTRL_PWR_TRACKING);
+
+	pDriver_adapter = pHalmac_adapter->pDriver_adapter;
+
+	PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_start_iqk_88xx ==========>\n");
+
+	if (HALMAC_CMD_PROCESS_SENDING == *pProcess_status) {
+		PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "Wait event(pwr tracking)...\n");
+		return HALMAC_RET_BUSY_STATE;
+	}
+
+	*pProcess_status = HALMAC_CMD_PROCESS_SENDING;
+
+	POWER_TRACKING_SET_TYPE(pH2c_buff, pPwr_tracking_opt->type);
+	POWER_TRACKING_SET_BBSWING_INDEX(pH2c_buff, pPwr_tracking_opt->bbswing_index);
+	POWER_TRACKING_SET_ENABLE_A(pH2c_buff, pPwr_tracking_opt->pwr_tracking_para[HALMAC_RF_PATH_A].enable);
+	POWER_TRACKING_SET_TX_PWR_INDEX_A(pH2c_buff, pPwr_tracking_opt->pwr_tracking_para[HALMAC_RF_PATH_A].tx_pwr_index);
+	POWER_TRACKING_SET_PWR_TRACKING_OFFSET_VALUE_A(pH2c_buff, pPwr_tracking_opt->pwr_tracking_para[HALMAC_RF_PATH_A].pwr_tracking_offset_value);
+	POWER_TRACKING_SET_TSSI_VALUE_A(pH2c_buff, pPwr_tracking_opt->pwr_tracking_para[HALMAC_RF_PATH_A].tssi_value);
+	POWER_TRACKING_SET_ENABLE_B(pH2c_buff, pPwr_tracking_opt->pwr_tracking_para[HALMAC_RF_PATH_B].enable);
+	POWER_TRACKING_SET_TX_PWR_INDEX_B(pH2c_buff, pPwr_tracking_opt->pwr_tracking_para[HALMAC_RF_PATH_B].tx_pwr_index);
+	POWER_TRACKING_SET_PWR_TRACKING_OFFSET_VALUE_B(pH2c_buff, pPwr_tracking_opt->pwr_tracking_para[HALMAC_RF_PATH_B].pwr_tracking_offset_value);
+	POWER_TRACKING_SET_TSSI_VALUE_B(pH2c_buff, pPwr_tracking_opt->pwr_tracking_para[HALMAC_RF_PATH_B].tssi_value);
+	POWER_TRACKING_SET_ENABLE_C(pH2c_buff, pPwr_tracking_opt->pwr_tracking_para[HALMAC_RF_PATH_C].enable);
+	POWER_TRACKING_SET_TX_PWR_INDEX_C(pH2c_buff, pPwr_tracking_opt->pwr_tracking_para[HALMAC_RF_PATH_C].tx_pwr_index);
+	POWER_TRACKING_SET_PWR_TRACKING_OFFSET_VALUE_C(pH2c_buff, pPwr_tracking_opt->pwr_tracking_para[HALMAC_RF_PATH_C].pwr_tracking_offset_value);
+	POWER_TRACKING_SET_TSSI_VALUE_C(pH2c_buff, pPwr_tracking_opt->pwr_tracking_para[HALMAC_RF_PATH_C].tssi_value);
+	POWER_TRACKING_SET_ENABLE_D(pH2c_buff, pPwr_tracking_opt->pwr_tracking_para[HALMAC_RF_PATH_D].enable);
+	POWER_TRACKING_SET_TX_PWR_INDEX_D(pH2c_buff, pPwr_tracking_opt->pwr_tracking_para[HALMAC_RF_PATH_D].tx_pwr_index);
+	POWER_TRACKING_SET_PWR_TRACKING_OFFSET_VALUE_D(pH2c_buff, pPwr_tracking_opt->pwr_tracking_para[HALMAC_RF_PATH_D].pwr_tracking_offset_value);
+	POWER_TRACKING_SET_TSSI_VALUE_D(pH2c_buff, pPwr_tracking_opt->pwr_tracking_para[HALMAC_RF_PATH_D].tssi_value);
+
+	h2c_header_info.sub_cmd_id = SUB_CMD_ID_POWER_TRACKING;
+	h2c_header_info.content_size = 20;
+	h2c_header_info.ack = _TRUE;
+	halmac_set_fw_offload_h2c_header_88xx(pHalmac_adapter, pH2c_buff, &h2c_header_info, &h2c_seq_mum);
+
+	pHalmac_adapter->halmac_state.power_tracking_set.seq_num = h2c_seq_mum;
+
+	status = halmac_send_h2c_pkt_88xx(pHalmac_adapter, pH2c_buff, HALMAC_H2C_CMD_SIZE_88XX, _TRUE);
+
+	if (HALMAC_RET_SUCCESS != status) {
+		PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "halmac_send_h2c_pkt_88xx Fail = %x!!\n", status);
+		return status;
+	}
+
+	PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_start_iqk_88xx <==========\n");
+
+	return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * halmac_query_status_88xx() -query the offload feature status
+ * @pHalmac_adapter : the adapter of halmac
+ * @feature_id : feature_id
+ * @pProcess_status : feature_status
+ * @data : data buffer
+ * @size : data size
+ *
+ * Note :
+ * If user wants to know the data size, use can allocate zero
+ * size buffer first. If this size less than the data size, halmac
+ * will return  HALMAC_RET_BUFFER_TOO_SMALL. User need to
+ * re-allocate data buffer with correct data size.
+ *
+ * Author : Ivan Lin/KaiYuan Chang
+ * Return : HALMAC_RET_STATUS
+ * More details of status code can be found in prototype document
+ */
+HALMAC_RET_STATUS
+halmac_query_status_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN HALMAC_FEATURE_ID feature_id,
+	OUT HALMAC_CMD_PROCESS_STATUS *pProcess_status,
+	INOUT u8 *data,
+	INOUT u32 *size
+)
+{
+	VOID *pDriver_adapter = NULL;
+	HALMAC_RET_STATUS status = HALMAC_RET_SUCCESS;
+
+	if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter))
+		return HALMAC_RET_ADAPTER_INVALID;
+
+	if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter))
+		return HALMAC_RET_API_INVALID;
+
+	halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_QUERY_STATE);
+
+	pDriver_adapter = pHalmac_adapter->pDriver_adapter;
+
+	/* PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_query_status_88xx ==========>\n"); */
+
+	if (NULL == pProcess_status) {
+		PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "null pointer!!\n");
+		return HALMAC_RET_NULL_POINTER;
+	}
+
+	switch (feature_id) {
+	case HALMAC_FEATURE_CFG_PARA:
+		status = halmac_query_cfg_para_status_88xx(pHalmac_adapter, pProcess_status, data, size);
+		break;
+	case HALMAC_FEATURE_DUMP_PHYSICAL_EFUSE:
+		status = halmac_query_dump_physical_efuse_status_88xx(pHalmac_adapter, pProcess_status, data, size);
+		break;
+	case HALMAC_FEATURE_DUMP_LOGICAL_EFUSE:
+		status = halmac_query_dump_logical_efuse_status_88xx(pHalmac_adapter, pProcess_status, data, size);
+		break;
+	case HALMAC_FEATURE_CHANNEL_SWITCH:
+		status = halmac_query_channel_switch_status_88xx(pHalmac_adapter, pProcess_status, data, size);
+		break;
+	case HALMAC_FEATURE_UPDATE_PACKET:
+		status = halmac_query_update_packet_status_88xx(pHalmac_adapter, pProcess_status, data, size);
+		break;
+	case HALMAC_FEATURE_IQK:
+		status = halmac_query_iqk_status_88xx(pHalmac_adapter, pProcess_status, data, size);
+		break;
+	case HALMAC_FEATURE_POWER_TRACKING:
+		status = halmac_query_power_tracking_status_88xx(pHalmac_adapter, pProcess_status, data, size);
+		break;
+	case HALMAC_FEATURE_PSD:
+		status = halmac_query_psd_status_88xx(pHalmac_adapter, pProcess_status, data, size);
+		break;
+	default:
+		PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_SND, HALMAC_DBG_ERR, "halmac_query_status_88xx invalid feature id %d\n", feature_id);
+		return HALMAC_RET_INVALID_FEATURE_ID;
+	}
+
+	/* PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_query_status_88xx <==========\n"); */
+
+	return status;
+}
+
+/**
+ * halmac_reset_feature_88xx() -reset async api cmd status
+ * @pHalmac_adapter : the adapter of halmac
+ * @feature_id : feature_id
+ * Author : Ivan Lin/KaiYuan Chang
+ * Return : HALMAC_RET_STATUS.
+ * More details of status code can be found in prototype document
+ */
+HALMAC_RET_STATUS
+halmac_reset_feature_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN HALMAC_FEATURE_ID feature_id
+)
+{
+	VOID *pDriver_adapter = NULL;
+	PHALMAC_STATE pState = &(pHalmac_adapter->halmac_state);
+
+	if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter))
+		return HALMAC_RET_ADAPTER_INVALID;
+
+	if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter))
+		return HALMAC_RET_API_INVALID;
+
+	halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_RESET_FEATURE);
+
+	pDriver_adapter = pHalmac_adapter->pDriver_adapter;
+
+	PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_reset_feature_88xx ==========>\n");
+
+	switch (feature_id) {
+	case HALMAC_FEATURE_CFG_PARA:
+		pState->cfg_para_state_set.process_status = HALMAC_CMD_PROCESS_IDLE;
+		pState->cfg_para_state_set.cfg_para_cmd_construct_state = HALMAC_CFG_PARA_CMD_CONSTRUCT_IDLE;
+		break;
+	case HALMAC_FEATURE_DUMP_PHYSICAL_EFUSE:
+	case HALMAC_FEATURE_DUMP_LOGICAL_EFUSE:
+		pState->efuse_state_set.process_status = HALMAC_CMD_PROCESS_IDLE;
+		pState->efuse_state_set.efuse_cmd_construct_state = HALMAC_EFUSE_CMD_CONSTRUCT_IDLE;
+		break;
+	case HALMAC_FEATURE_CHANNEL_SWITCH:
+		pState->scan_state_set.process_status = HALMAC_CMD_PROCESS_IDLE;
+		pState->scan_state_set.scan_cmd_construct_state = HALMAC_SCAN_CMD_CONSTRUCT_IDLE;
+		break;
+	case HALMAC_FEATURE_UPDATE_PACKET:
+		pState->update_packet_set.process_status = HALMAC_CMD_PROCESS_IDLE;
+		break;
+	case HALMAC_FEATURE_ALL:
+		pState->cfg_para_state_set.process_status = HALMAC_CMD_PROCESS_IDLE;
+		pState->cfg_para_state_set.cfg_para_cmd_construct_state = HALMAC_CFG_PARA_CMD_CONSTRUCT_IDLE;
+		pState->efuse_state_set.process_status = HALMAC_CMD_PROCESS_IDLE;
+		pState->efuse_state_set.efuse_cmd_construct_state = HALMAC_EFUSE_CMD_CONSTRUCT_IDLE;
+		pState->scan_state_set.process_status = HALMAC_CMD_PROCESS_IDLE;
+		pState->scan_state_set.scan_cmd_construct_state = HALMAC_SCAN_CMD_CONSTRUCT_IDLE;
+		pState->update_packet_set.process_status = HALMAC_CMD_PROCESS_IDLE;
+		break;
+	default:
+		PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_SND, HALMAC_DBG_ERR, "halmac_reset_feature_88xx invalid feature id %d\n", feature_id);
+		return HALMAC_RET_INVALID_FEATURE_ID;
+	}
+
+	PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_reset_feature_88xx <==========\n");
+
+	return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * halmac_check_fw_status_88xx() -check fw status
+ * @pHalmac_adapter : the adapter of halmac
+ * @fw_status : fw status
+ * Author : KaiYuan Chang/Ivan Lin
+ * Return : HALMAC_RET_STATUS
+ * More details of status code can be found in prototype document
+ */
+HALMAC_RET_STATUS
+halmac_check_fw_status_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	OUT u8 *fw_status
+)
+{
+	u32 value32 = 0, value32_backup = 0, i = 0;
+	VOID *pDriver_adapter = NULL;
+	PHALMAC_API pHalmac_api;
+	HALMAC_RET_STATUS status = HALMAC_RET_SUCCESS;
+
+	if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter))
+		return HALMAC_RET_ADAPTER_INVALID;
+
+	if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter))
+		return HALMAC_RET_API_INVALID;
+
+	halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_CHECK_FW_STATUS);
+
+	pDriver_adapter = pHalmac_adapter->pDriver_adapter;
+	pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api;
+
+	PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_check_fw_status_88xx ==========>\n");
+
+	value32 = PLATFORM_REG_READ_32(pDriver_adapter, REG_FW_DBG6);
+
+	if (0 != value32) {
+		PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "halmac_check_fw_status REG_FW_DBG6 !=0\n");
+		*fw_status = _FALSE;
+		return status;
+	}
+
+	value32_backup = PLATFORM_REG_READ_32(pDriver_adapter, REG_FW_DBG7);
+
+	for (i = 0; i <= 10; i++) {
+		value32 = PLATFORM_REG_READ_32(pDriver_adapter, REG_FW_DBG7);
+		if (value32_backup != value32) {
+			break;
+		} else {
+			if (10 == i) {
+				PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "halmac_check_fw_status Polling FW PC fail\n");
+				*fw_status = _FALSE;
+				return status;
+			}
+		}
+	}
+
+	PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_check_fw_status_88xx <==========\n");
+
+	return status;
+}
+
+HALMAC_RET_STATUS
+halmac_dump_fw_dmem_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	INOUT u8 *dmem,
+	INOUT u32 *size
+)
+{
+	VOID *pDriver_adapter = NULL;
+	HALMAC_RET_STATUS status = HALMAC_RET_SUCCESS;
+
+	if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter))
+		return HALMAC_RET_ADAPTER_INVALID;
+
+	if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter))
+		return HALMAC_RET_API_INVALID;
+
+	halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_DUMP_FW_DMEM);
+
+	pDriver_adapter = pHalmac_adapter->pDriver_adapter;
+
+	PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_dump_fw_dmem_88xx ==========>\n");
+
+
+
+	PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_dump_fw_dmem_88xx <==========\n");
+
+	return status;
+}
+
+/**
+ * halmac_cfg_max_dl_size_88xx() - config max download FW size
+ * @pHalmac_adapter : the adapter of halmac
+ * @size : max download fw size
+ *
+ * Halmac uses this setting to set max packet size for
+ * download FW.
+ * If user has not called this API, halmac use default
+ * setting for download FW
+ * Note1 : size need multiple of 2
+ * Note2 : max size is 31K
+ *
+ * Author : Ivan Lin/KaiYuan Chang
+ * Return : HALMAC_RET_STATUS
+ * More details of status code can be found in prototype document
+ */
+HALMAC_RET_STATUS
+halmac_cfg_max_dl_size_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN u32 size
+)
+{
+	VOID *pDriver_adapter = NULL;
+
+	if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter))
+		return HALMAC_RET_ADAPTER_INVALID;
+
+	if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter))
+		return HALMAC_RET_API_INVALID;
+
+	halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_CFG_MAX_DL_SIZE);
+
+	pDriver_adapter = pHalmac_adapter->pDriver_adapter;
+
+	PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_FW, HALMAC_DBG_TRACE, "halmac_cfg_max_dl_size_88xx ==========>\n");
+
+	if (size > HALMAC_FW_CFG_MAX_DL_SIZE_MAX_88XX) {
+		PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_FW, HALMAC_DBG_ERR, "size > HALMAC_FW_CFG_MAX_DL_SIZE_MAX!\n");
+		return HALMAC_RET_CFG_DLFW_SIZE_FAIL;
+	}
+
+	if (0 != (size & (2 - 1))) {
+		PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_FW, HALMAC_DBG_ERR, "size is not power of 2!\n");
+		return HALMAC_RET_CFG_DLFW_SIZE_FAIL;
+	}
+
+	pHalmac_adapter->max_download_size = size;
+
+	PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_FW, HALMAC_DBG_TRACE, "Cfg max size is : %X\n", size);
+
+	PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_FW, HALMAC_DBG_TRACE, "halmac_cfg_max_dl_size_88xx <==========\n");
+
+	return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * halmac_psd_88xx() - trigger fw psd
+ * @pHalmac_adapter : the adapter of halmac
+ * @start_psd : start PSD
+ * @end_psd : end PSD
+ * Author : KaiYuan Chang/Ivan Lin
+ * Return : HALMAC_RET_STATUS
+ * More details of status code can be found in prototype document
+ */
+HALMAC_RET_STATUS
+halmac_psd_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN u16 start_psd,
+	IN u16 end_psd
+)
+{
+	u8 pH2c_buff[HALMAC_H2C_CMD_SIZE_88XX] = { 0 };
+	u16 h2c_seq_mum = 0;
+	VOID *pDriver_adapter = NULL;
+	HALMAC_RET_STATUS status = HALMAC_RET_SUCCESS;
+	HALMAC_H2C_HEADER_INFO h2c_header_info;
+	HALMAC_CMD_PROCESS_STATUS *pProcess_status = &(pHalmac_adapter->halmac_state.psd_set.process_status);
+
+	if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter))
+		return HALMAC_RET_ADAPTER_INVALID;
+
+	if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter))
+		return HALMAC_RET_API_INVALID;
+
+	if (HALMAC_RET_SUCCESS != halmac_fw_validate(pHalmac_adapter))
+		return HALMAC_RET_NO_DLFW;
+
+	halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_PSD);
+
+	pDriver_adapter = pHalmac_adapter->pDriver_adapter;
+
+	PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_psd_88xx ==========>\n");
+
+	if (HALMAC_CMD_PROCESS_SENDING == *pProcess_status) {
+		PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "Wait event(psd)...\n");
+		return HALMAC_RET_BUSY_STATE;
+	}
+
+	if (NULL != pHalmac_adapter->halmac_state.psd_set.pData) {
+		PLATFORM_RTL_FREE(pDriver_adapter, pHalmac_adapter->halmac_state.psd_set.pData, pHalmac_adapter->halmac_state.psd_set.data_size);
+		pHalmac_adapter->halmac_state.psd_set.pData = (u8 *)NULL;
+	}
+
+	pHalmac_adapter->halmac_state.psd_set.data_size = 0;
+	pHalmac_adapter->halmac_state.psd_set.segment_size = 0;
+
+	*pProcess_status = HALMAC_CMD_PROCESS_SENDING;
+
+	PSD_SET_START_PSD(pH2c_buff, start_psd);
+	PSD_SET_END_PSD(pH2c_buff, end_psd);
+
+	h2c_header_info.sub_cmd_id = SUB_CMD_ID_PSD;
+	h2c_header_info.content_size = 4;
+	h2c_header_info.ack = _TRUE;
+	halmac_set_fw_offload_h2c_header_88xx(pHalmac_adapter, pH2c_buff, &h2c_header_info, &h2c_seq_mum);
+
+	status = halmac_send_h2c_pkt_88xx(pHalmac_adapter, pH2c_buff, HALMAC_H2C_CMD_SIZE_88XX, _TRUE);
+
+	if (HALMAC_RET_SUCCESS != status) {
+		PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "halmac_send_h2c_pkt_88xx Fail = %x!!\n", status);
+		return status;
+	}
+
+	PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_psd_88xx <==========\n");
+
+	return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * halmac_cfg_la_mode_88xx() - config la mode
+ * @pHalmac_adapter : the adapter of halmac
+ * @la_mode :
+ *	disable : no TXFF space reserved for LA debug
+ *	partial : partial TXFF space is reserved for LA debug
+ *	full : all TXFF space is reserved for LA debug
+ * Author : KaiYuan Chang
+ * Return : HALMAC_RET_STATUS
+ * More details of status code can be found in prototype document
+ */
+HALMAC_RET_STATUS
+halmac_cfg_la_mode_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN HALMAC_LA_MODE la_mode
+)
+{
+	VOID *pDriver_adapter = NULL;
+
+	if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter))
+		return HALMAC_RET_ADAPTER_INVALID;
+
+	if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter))
+		return HALMAC_RET_API_INVALID;
+
+	halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_CFG_LA_MODE);
+
+	pDriver_adapter = pHalmac_adapter->pDriver_adapter;
+
+	PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_cfg_la_mode_88xx ==========>la_mode = %d\n", la_mode);
+
+	pHalmac_adapter->txff_allocation.la_mode = la_mode;
+
+	PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_cfg_la_mode_88xx <==========\n");
+
+	return HALMAC_RET_SUCCESS;
+}
+/**
+ * halmac_cfg_rx_fifo_expanding_mode_88xx() - rx fifo expanding
+ * @pHalmac_adapter : the adapter of halmac
+ * @la_mode :
+ *	disable : normal mode
+ *	1 block : Rx FIFO + 1 FIFO block; Tx fifo - 1 FIFO block
+ *	2 block : Rx FIFO + 2 FIFO block; Tx fifo - 2 FIFO block
+ *	3 block : Rx FIFO + 3 FIFO block; Tx fifo - 3 FIFO block
+ * Author : Soar
+ * Return : HALMAC_RET_STATUS
+ * More details of status code can be found in prototype document
+ */
+HALMAC_RET_STATUS
+halmac_cfg_rx_fifo_expanding_mode_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN HALMAC_RX_FIFO_EXPANDING_MODE rx_fifo_expanding_mode
+)
+{
+	VOID *pDriver_adapter = NULL;
+
+	if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter))
+		return HALMAC_RET_ADAPTER_INVALID;
+
+	if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter))
+		return HALMAC_RET_API_INVALID;
+
+	halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_CFG_RX_FIFO_EXPANDING_MODE);
+
+	pDriver_adapter = pHalmac_adapter->pDriver_adapter;
+
+	PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_cfg_rx_fifo_expanding_mode_88xx ==========>rx_fifo_expanding_mode = %d\n", rx_fifo_expanding_mode);
+
+	pHalmac_adapter->txff_allocation.rx_fifo_expanding_mode = rx_fifo_expanding_mode;
+
+	PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_cfg_rx_fifo_expanding_mode_88xx <==========\n");
+
+	return HALMAC_RET_SUCCESS;
+}
+
+HALMAC_RET_STATUS
+halmac_config_security_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN PHALMAC_SECURITY_SETTING pSec_setting
+)
+{
+	PHALMAC_API pHalmac_api;
+	VOID *pDriver_adapter = NULL;
+
+	if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter))
+	return HALMAC_RET_ADAPTER_INVALID;
+
+	if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter))
+		return HALMAC_RET_API_INVALID;
+
+	pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api;
+	pDriver_adapter = pHalmac_adapter->pDriver_adapter;
+
+	PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_COMMON, HALMAC_DBG_TRACE, "halmac_config_security_88xx ==========>\n");
+
+	HALMAC_REG_WRITE_16(pHalmac_adapter, REG_CR, (u16)(HALMAC_REG_READ_16(pHalmac_adapter, REG_CR) | BIT_MAC_SEC_EN));
+
+	if (1 == pSec_setting->tx_encryption)
+		HALMAC_REG_WRITE_8(pHalmac_adapter, REG_SECCFG, HALMAC_REG_READ_8(pHalmac_adapter, REG_SECCFG) | BIT(2));
+	else
+		HALMAC_REG_WRITE_8(pHalmac_adapter, REG_SECCFG, HALMAC_REG_READ_8(pHalmac_adapter, REG_SECCFG) & ~(BIT(2)));
+
+	if (1 == pSec_setting->rx_decryption)
+		HALMAC_REG_WRITE_8(pHalmac_adapter, REG_SECCFG, HALMAC_REG_READ_8(pHalmac_adapter, REG_SECCFG) | BIT(3));
+	else
+		HALMAC_REG_WRITE_8(pHalmac_adapter, REG_SECCFG, HALMAC_REG_READ_8(pHalmac_adapter, REG_SECCFG) & ~(BIT(3)));
+
+	if (1 == pSec_setting->bip_enable) {
+		if (HALMAC_CHIP_ID_8822B == pHalmac_adapter->chip_id)
+			return HALMAC_RET_BIP_NO_SUPPORT;
+#if HALMAC_8821C_SUPPORT
+		if (1 == pSec_setting->tx_encryption)
+			HALMAC_REG_WRITE_8(pHalmac_adapter, REG_WSEC_OPTION + 2, HALMAC_REG_READ_8(pHalmac_adapter, REG_WSEC_OPTION + 2) | (BIT(3) | BIT(5)));
+		else
+			HALMAC_REG_WRITE_8(pHalmac_adapter, REG_WSEC_OPTION + 2, HALMAC_REG_READ_8(pHalmac_adapter, REG_WSEC_OPTION + 2) & ~(BIT(3) | BIT(5)));
+
+		if (1 == pSec_setting->rx_decryption)
+			HALMAC_REG_WRITE_8(pHalmac_adapter, REG_WSEC_OPTION + 2, HALMAC_REG_READ_8(pHalmac_adapter, REG_WSEC_OPTION + 2) | (BIT(4) | BIT(6)));
+		else
+			HALMAC_REG_WRITE_8(pHalmac_adapter, REG_WSEC_OPTION + 2, HALMAC_REG_READ_8(pHalmac_adapter, REG_WSEC_OPTION + 2) & ~(BIT(4) | BIT(6)));
+#endif
+	}
+
+	PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_COMMON, HALMAC_DBG_TRACE, "halmac_config_security_88xx <==========\n");
+
+	return HALMAC_RET_SUCCESS;
+}
+
+u8
+halmac_get_used_cam_entry_num_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN HAL_SECURITY_TYPE sec_type
+)
+{
+	u8 entry_num;
+	VOID *pDriver_adapter = NULL;
+
+	pDriver_adapter = pHalmac_adapter->pDriver_adapter;
+
+	PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_COMMON, HALMAC_DBG_TRACE, "halmac_get_used_cam_entry_num_88xx ==========>\n");
+
+	switch (sec_type) {
+	case HAL_SECURITY_TYPE_WEP40:
+	case HAL_SECURITY_TYPE_WEP104:
+	case HAL_SECURITY_TYPE_TKIP:
+	case HAL_SECURITY_TYPE_AES128:
+	case HAL_SECURITY_TYPE_GCMP128:
+	case HAL_SECURITY_TYPE_GCMSMS4:
+	case HAL_SECURITY_TYPE_BIP:
+		entry_num = 1;
+		break;
+	case HAL_SECURITY_TYPE_WAPI:
+	case HAL_SECURITY_TYPE_AES256:
+	case HAL_SECURITY_TYPE_GCMP256:
+		entry_num = 2;
+		break;
+	default:
+		entry_num = 0;
+		break;
+	}
+
+	PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_COMMON, HALMAC_DBG_TRACE, "halmac_get_used_cam_entry_num_88xx <==========\n");
+
+	return entry_num;
+}
+
+HALMAC_RET_STATUS
+halmac_write_cam_88xx(
+	IN PHALMAC_ADAPTER	pHalmac_adapter,
+	IN u32 entry_index,
+	IN PHALMAC_CAM_ENTRY_INFO pCam_entry_info
+)
+{
+	u32 i;
+	u32 command = 0x80010000;
+	PHALMAC_API pHalmac_api;
+	VOID *pDriver_adapter = NULL;
+	PHALMAC_CAM_ENTRY_FORMAT pCam_entry_format = NULL;
+
+	pDriver_adapter = pHalmac_adapter->pDriver_adapter;
+	pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api;
+
+	PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_COMMON, HALMAC_DBG_TRACE, "[TRACE]halmac_write_cam_88xx ==========>\n");
+
+	if (entry_index >= pHalmac_adapter->hw_config_info.cam_entry_num)
+		return HALMAC_RET_ENTRY_INDEX_ERROR;
+
+	if (pCam_entry_info->key_id > 3)
+		return HALMAC_RET_FAIL;
+
+	pCam_entry_format = (PHALMAC_CAM_ENTRY_FORMAT)PLATFORM_RTL_MALLOC(pDriver_adapter, sizeof(*pCam_entry_format));
+	if (NULL == pCam_entry_format)
+		return HALMAC_RET_NULL_POINTER;
+	PLATFORM_RTL_MEMSET(pDriver_adapter, pCam_entry_format, 0x00, sizeof(*pCam_entry_format));
+
+	pCam_entry_format->key_id = pCam_entry_info->key_id;
+	pCam_entry_format->valid = pCam_entry_info->valid;
+	PLATFORM_RTL_MEMCPY(pDriver_adapter, pCam_entry_format->mac_address, pCam_entry_info->mac_address, 6);
+	PLATFORM_RTL_MEMCPY(pDriver_adapter, pCam_entry_format->key, pCam_entry_info->key, 16);
+
+	switch (pCam_entry_info->security_type) {
+	case HAL_SECURITY_TYPE_NONE:
+		pCam_entry_format->type = 0;
+		break;
+	case HAL_SECURITY_TYPE_WEP40:
+		pCam_entry_format->type = 1;
+		break;
+	case HAL_SECURITY_TYPE_WEP104:
+		pCam_entry_format->type = 5;
+		break;
+	case HAL_SECURITY_TYPE_TKIP:
+		pCam_entry_format->type = 2;
+		break;
+	case HAL_SECURITY_TYPE_AES128:
+		pCam_entry_format->type = 4;
+		break;
+	case HAL_SECURITY_TYPE_WAPI:
+		pCam_entry_format->type = 6;
+		break;
+	case HAL_SECURITY_TYPE_AES256:
+		pCam_entry_format->type = 4;
+		pCam_entry_format->ext_sectype = 1;
+		break;
+	case HAL_SECURITY_TYPE_GCMP128:
+		pCam_entry_format->type = 7;
+		break;
+	case HAL_SECURITY_TYPE_GCMP256:
+	case HAL_SECURITY_TYPE_GCMSMS4:
+		pCam_entry_format->type = 7;
+		pCam_entry_format->ext_sectype = 1;
+		break;
+	case HAL_SECURITY_TYPE_BIP:
+		pCam_entry_format->type = (1 == pCam_entry_info->unicast) ? 4 : 0;
+		pCam_entry_format->mgnt = 1;
+		pCam_entry_format->grp = (1 == pCam_entry_info->unicast) ? 0 : 1;
+		break;
+	default:
+		PLATFORM_RTL_FREE(pDriver_adapter, pCam_entry_format, sizeof(*pCam_entry_format));
+		return HALMAC_RET_FAIL;
+	}
+
+
+	for (i = 0; i < 8; i++) {
+		HALMAC_REG_WRITE_32(pHalmac_adapter, REG_CAMWRITE, *((u32 *)pCam_entry_format + i));
+		HALMAC_REG_WRITE_32(pHalmac_adapter, REG_CAMCMD, command | ((entry_index << 3) + i));
+		PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_COMMON, HALMAC_DBG_TRACE, "[TRACE]1 - CAM entry format : %X\n", *((u32 *)pCam_entry_format + i));
+		PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_COMMON, HALMAC_DBG_TRACE, "[TRACE]1 - REG_CAMCMD : %X\n", command | ((entry_index << 3) + i));
+	}
+
+	if (HAL_SECURITY_TYPE_WAPI == pCam_entry_info->security_type || HAL_SECURITY_TYPE_AES256 == pCam_entry_info->security_type ||
+			HAL_SECURITY_TYPE_GCMP256 == pCam_entry_info->security_type || HAL_SECURITY_TYPE_GCMSMS4 == pCam_entry_info->security_type) {
+		pCam_entry_format->mic = 1;
+		PLATFORM_RTL_MEMCPY(pDriver_adapter, pCam_entry_format->key, pCam_entry_info->key_ext, 16);
+
+		for (i = 0; i < 8; i++) {
+			HALMAC_REG_WRITE_32(pHalmac_adapter, REG_CAMWRITE, *((u32 *)pCam_entry_format + i));
+			HALMAC_REG_WRITE_32(pHalmac_adapter, REG_CAMCMD, command | (((entry_index + 1) << 3) + i));
+			PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_COMMON, HALMAC_DBG_TRACE, "[TRACE]2 - CAM entry format : %X\n", *((u32 *)pCam_entry_format + i));
+			PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_COMMON, HALMAC_DBG_TRACE, "[TRACE]2 - REG_CAMCMD : %X\n", command | (((entry_index + 1) << 3) + i));
+		}
+	}
+
+	PLATFORM_RTL_FREE(pDriver_adapter, pCam_entry_format, sizeof(*pCam_entry_format));
+
+	PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_COMMON, HALMAC_DBG_TRACE, "[TRACE]halmac_write_cam_88xx <==========\n");
+
+	return HALMAC_RET_SUCCESS;
+}
+
+HALMAC_RET_STATUS
+halmac_read_cam_entry_88xx(
+	IN PHALMAC_ADAPTER	pHalmac_adapter,
+	IN u32 entry_index,
+	OUT PHALMAC_CAM_ENTRY_FORMAT pContent
+)
+{
+	u32 i;
+	u32 command = 0x80000000;
+	PHALMAC_API pHalmac_api;
+	VOID *pDriver_adapter = NULL;
+
+	pDriver_adapter = pHalmac_adapter->pDriver_adapter;
+	pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api;
+
+	PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_COMMON, HALMAC_DBG_TRACE, "halmac_read_cam_entry_88xx ==========>\n");
+
+	if (entry_index >= pHalmac_adapter->hw_config_info.cam_entry_num)
+		return HALMAC_RET_ENTRY_INDEX_ERROR;
+
+	for (i = 0; i < 8; i++) {
+		HALMAC_REG_WRITE_32(pHalmac_adapter, REG_CAMCMD, command | ((entry_index << 3) + i));
+		*((u32 *)pContent + i) = HALMAC_REG_READ_32(pHalmac_adapter, REG_CAMREAD);
+	}
+
+	PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_COMMON, HALMAC_DBG_TRACE, "halmac_read_cam_entry_88xx <==========\n");
+
+	return HALMAC_RET_SUCCESS;
+}
+
+HALMAC_RET_STATUS
+halmac_clear_cam_entry_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN u32 entry_index
+)
+{
+	u32 i;
+	u32 command = 0x80010000;
+	VOID *pDriver_adapter = NULL;
+	PHALMAC_API pHalmac_api;
+	PHALMAC_CAM_ENTRY_FORMAT pCam_entry_format;
+
+	if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter))
+		return HALMAC_RET_ADAPTER_INVALID;
+
+	if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter))
+		return HALMAC_RET_API_INVALID;
+
+	pDriver_adapter = pHalmac_adapter->pDriver_adapter;
+	pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api;
+
+	PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "[TRACE]halmac_clear_security_cam_88xx ==========>\n");
+
+	if (entry_index >= pHalmac_adapter->hw_config_info.cam_entry_num)
+		return HALMAC_RET_ENTRY_INDEX_ERROR;
+
+	pCam_entry_format = (PHALMAC_CAM_ENTRY_FORMAT)PLATFORM_RTL_MALLOC(pDriver_adapter, sizeof(*pCam_entry_format));
+	if (NULL == pCam_entry_format)
+		return HALMAC_RET_NULL_POINTER;
+	PLATFORM_RTL_MEMSET(pDriver_adapter, pCam_entry_format, 0x00, sizeof(*pCam_entry_format));
+
+	for (i = 0; i < 8; i++) {
+		HALMAC_REG_WRITE_32(pHalmac_adapter, REG_CAMWRITE, *((u32 *)pCam_entry_format + i));
+		HALMAC_REG_WRITE_32(pHalmac_adapter, REG_CAMCMD, command | ((entry_index << 3) + i));
+	}
+
+	PLATFORM_RTL_FREE(pDriver_adapter, pCam_entry_format, sizeof(*pCam_entry_format));
+
+	PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "[TRACE]halmac_clear_security_cam_88xx <==========\n");
+
+	return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * halmac_get_hw_value_88xx() -get hw config value
+ * @pHalmac_adapter : the adapter of halmac
+ * @hw_id : hw id for driver to query
+ * @pvalue : hw value, reference table to get data type
+ * Author : KaiYuan Chang / Ivan Lin
+ * Return : HALMAC_RET_STATUS
+ * More details of status code can be found in prototype document
+ */
+HALMAC_RET_STATUS
+halmac_get_hw_value_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN HALMAC_HW_ID hw_id,
+	OUT VOID *pvalue
+)
+{
+	VOID *pDriver_adapter = NULL;
+	HALMAC_RET_STATUS status = HALMAC_RET_SUCCESS;
+
+	if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter))
+		return HALMAC_RET_ADAPTER_INVALID;
+
+	if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter))
+		return HALMAC_RET_API_INVALID;
+
+	halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_GET_HW_VALUE);
+
+	pDriver_adapter = pHalmac_adapter->pDriver_adapter;
+
+	PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_get_hw_value_88xx ==========>\n");
+
+	if (NULL == pvalue) {
+		PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "halmac_get_hw_value_88xx (NULL ==pvalue)==========>\n");
+		return HALMAC_RET_NULL_POINTER;
+	}
+
+	switch (hw_id) {
+	case HALMAC_HW_RQPN_MAPPING:
+		((PHALMAC_RQPN_MAP)pvalue)->dma_map_vo = pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_VO];
+		((PHALMAC_RQPN_MAP)pvalue)->dma_map_vi = pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_VI];
+		((PHALMAC_RQPN_MAP)pvalue)->dma_map_be = pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_BE];
+		((PHALMAC_RQPN_MAP)pvalue)->dma_map_bk = pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_BK];
+		((PHALMAC_RQPN_MAP)pvalue)->dma_map_mg = pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_MG];
+		((PHALMAC_RQPN_MAP)pvalue)->dma_map_hi = pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_HI];
+		break;
+	case HALMAC_HW_EFUSE_SIZE:
+		*(u32 *)pvalue = pHalmac_adapter->hw_config_info.efuse_size;
+		break;
+	case HALMAC_HW_EEPROM_SIZE:
+		*(u32 *)pvalue = pHalmac_adapter->hw_config_info.eeprom_size;
+		break;
+	case HALMAC_HW_BT_BANK_EFUSE_SIZE:
+		*(u32 *)pvalue = pHalmac_adapter->hw_config_info.bt_efuse_size;
+		break;
+	case HALMAC_HW_BT_BANK1_EFUSE_SIZE:
+	case HALMAC_HW_BT_BANK2_EFUSE_SIZE:
+		*(u32 *)pvalue = 0;
+		break;
+	case HALMAC_HW_TXFIFO_SIZE:
+		*(u32 *)pvalue = pHalmac_adapter->hw_config_info.tx_fifo_size;
+		break;
+	case HALMAC_HW_RSVD_PG_BNDY:
+		*(u16 *)pvalue = pHalmac_adapter->txff_allocation.rsvd_drv_pg_bndy;
+		break;
+	case HALMAC_HW_CAM_ENTRY_NUM:
+		*(u8 *)pvalue = pHalmac_adapter->hw_config_info.cam_entry_num;
+		break;
+	case HALMAC_HW_WLAN_EFUSE_AVAILABLE_SIZE: /*Remove later*/
+		status = halmac_dump_logical_efuse_map_88xx(pHalmac_adapter, HALMAC_EFUSE_R_DRV);
+		if (HALMAC_RET_SUCCESS != status)
+			return status;
+		*(u32 *)pvalue = pHalmac_adapter->hw_config_info.efuse_size - HALMAC_PROTECTED_EFUSE_SIZE_88XX - pHalmac_adapter->efuse_end;
+		break;
+	case HALMAC_HW_IC_VERSION:
+		*(u8 *)pvalue = pHalmac_adapter->chip_version;
+		break;
+	case HALMAC_HW_PAGE_SIZE:
+		*(u32 *)pvalue = pHalmac_adapter->hw_config_info.page_size;
+		break;
+	case HALMAC_HW_TX_AGG_ALIGN_SIZE:
+		*(u16 *)pvalue = pHalmac_adapter->hw_config_info.tx_align_size;
+		break;
+	case HALMAC_HW_RX_AGG_ALIGN_SIZE:
+		*(u8 *)pvalue = 8;
+		break;
+	case HALMAC_HW_DRV_INFO_SIZE:
+		*(u8 *)pvalue = pHalmac_adapter->drv_info_size;
+		break;
+	case HALMAC_HW_TXFF_ALLOCATION:
+		PLATFORM_RTL_MEMCPY(pDriver_adapter, pvalue, &(pHalmac_adapter->txff_allocation), sizeof(HALMAC_TXFF_ALLOCATION));
+		break;
+	case HALMAC_HW_TX_DESC_SIZE:
+		*(u32 *)pvalue = pHalmac_adapter->hw_config_info.txdesc_size;
+		break;
+	case HALMAC_HW_RX_DESC_SIZE:
+		*(u32 *)pvalue = pHalmac_adapter->hw_config_info.rxdesc_size;
+		break;
+	default:
+		return HALMAC_RET_PARA_NOT_SUPPORT;
+	}
+
+
+
+	PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_get_hw_value_88xx <==========\n");
+
+	return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * halmac_set_hw_value_88xx() -set hw config value
+ * @pHalmac_adapter : the adapter of halmac
+ * @hw_id : hw id for driver to config
+ * @pvalue : hw value, reference table to get data type
+ * Author : KaiYuan Chang / Ivan Lin
+ * Return : HALMAC_RET_STATUS
+ * More details of status code can be found in prototype document
+ */
+HALMAC_RET_STATUS
+halmac_set_hw_value_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN HALMAC_HW_ID hw_id,
+	IN VOID *pvalue
+)
+{
+	VOID *pDriver_adapter = NULL;
+	HALMAC_RET_STATUS status;
+
+	if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter))
+		return HALMAC_RET_ADAPTER_INVALID;
+
+	if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter))
+		return HALMAC_RET_API_INVALID;
+
+	halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_GET_HW_VALUE);
+
+	pDriver_adapter = pHalmac_adapter->pDriver_adapter;
+
+	PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_set_hw_value_88xx ==========>\n");
+
+	if (NULL == pvalue) {
+		PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "halmac_set_hw_value_88xx (NULL == pvalue)==========>\n");
+		return HALMAC_RET_NULL_POINTER;
+	}
+
+	switch (hw_id) {
+	case HALMAC_HW_USB_MODE:
+		status = halmac_set_usb_mode_88xx(pHalmac_adapter, *(HALMAC_USB_MODE *)pvalue);
+		if (HALMAC_RET_SUCCESS != status)
+			return status;
+		break;
+	case HALMAC_HW_SEQ_EN:
+		/*if (_TRUE == hw_seq_en) {
+		} else {
+		}*/
+		break;
+	case HALMAC_HW_BANDWIDTH:
+		halmac_cfg_bw_88xx(pHalmac_adapter, *(HALMAC_BW *)pvalue);
+		break;
+	case HALMAC_HW_CHANNEL:
+		halmac_cfg_ch_88xx(pHalmac_adapter, *(u8 *)pvalue);
+		break;
+	case HALMAC_HW_PRI_CHANNEL_IDX:
+		halmac_cfg_pri_ch_idx_88xx(pHalmac_adapter, *(HALMAC_PRI_CH_IDX *)pvalue);
+		break;
+	case HALMAC_HW_EN_BB_RF:
+		halmac_enable_bb_rf_88xx(pHalmac_adapter, *(u8 *)pvalue);
+		break;
+	case HALMAC_HW_SDIO_TX_PAGE_THRESHOLD:
+		halmac_config_sdio_tx_page_threshold_88xx(pHalmac_adapter, (PHALMAC_TX_PAGE_THRESHOLD_INFO)pvalue);
+		break;
+	case HALMAC_HW_AMPDU_CONFIG:
+		halmac_config_ampdu_88xx(pHalmac_adapter, (PHALMAC_AMPDU_CONFIG)pvalue);
+		break;
+	default:
+		return HALMAC_RET_PARA_NOT_SUPPORT;
+	}
+
+	PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_set_hw_value_88xx <==========\n");
+
+	return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * halmac_cfg_drv_rsvd_pg_num_88xx() -config reserved page number for driver
+ * @pHalmac_adapter : the adapter of halmac
+ * @pg_num : page number
+ * Author : KaiYuan Chang
+ * Return : HALMAC_RET_STATUS
+ * More details of status code can be found in prototype document
+ */
+HALMAC_RET_STATUS
+halmac_cfg_drv_rsvd_pg_num_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN HALMAC_DRV_RSVD_PG_NUM pg_num
+)
+{
+	VOID *pDriver_adapter = NULL;
+
+	if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter))
+		return HALMAC_RET_ADAPTER_INVALID;
+
+	if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter))
+		return HALMAC_RET_API_INVALID;
+
+	halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_CFG_DRV_RSVD_PG_NUM);
+
+	pDriver_adapter = pHalmac_adapter->pDriver_adapter;
+
+	PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_cfg_drv_rsvd_pg_num_88xx ==========>pg_num = %d\n", pg_num);
+
+	switch (pg_num) {
+	case HALMAC_RSVD_PG_NUM16:
+		pHalmac_adapter->txff_allocation.rsvd_drv_pg_num = 16;
+		break;
+	case HALMAC_RSVD_PG_NUM24:
+		pHalmac_adapter->txff_allocation.rsvd_drv_pg_num = 24;
+		break;
+	case HALMAC_RSVD_PG_NUM32:
+		pHalmac_adapter->txff_allocation.rsvd_drv_pg_num = 32;
+		break;
+	}
+
+	PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_cfg_drv_rsvd_pg_num_88xx <==========\n");
+
+	return HALMAC_RET_SUCCESS;
+}
+
+HALMAC_RET_STATUS
+halmac_get_chip_version_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN PHALMAC_VER pVersion
+)
+{
+	VOID *pDriver_adapter = NULL;
+	PHALMAC_API pHalmac_api;
+
+	if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter))
+		return HALMAC_RET_ADAPTER_INVALID;
+
+	if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter))
+		return HALMAC_RET_API_INVALID;
+
+	pDriver_adapter = pHalmac_adapter->pDriver_adapter;
+	pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api;
+
+	PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_get_chip_version_88xx ==========>\n");
+	pVersion->major_ver = (u8)HALMAC_MAJOR_VER_88XX;
+	pVersion->prototype_ver = (u8)HALMAC_PROTOTYPE_VER_88XX;
+	pVersion->minor_ver = (u8)HALMAC_MINOR_VER_88XX;
+	PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_get_chip_version_88xx <==========\n");
+
+	return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * halmac_chk_txdesc_88xx() -check if the tx packet format is incorrect
+ * @pHalmac_adapter : the adapter of halmac
+ * @halmac_buf : tx Packet buffer, tx desc is included
+ * @halmac_size : tx packet size
+ * Author : KaiYuan Chang
+ * Return : HALMAC_RET_STATUS
+ * More details of status code can be found in prototype document
+ */
+HALMAC_RET_STATUS
+halmac_chk_txdesc_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN u8 *pHalmac_buf,
+	IN u32 halmac_size
+)
+{
+	VOID *pDriver_adapter = NULL;
+	PHALMAC_API pHalmac_api;
+
+	if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter))
+		return HALMAC_RET_ADAPTER_INVALID;
+
+	if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter))
+		return HALMAC_RET_API_INVALID;
+
+	pDriver_adapter = pHalmac_adapter->pDriver_adapter;
+	pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api;
+
+	PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_chk_txdesc_88xx ==========>\n");
+
+	if (_TRUE == GET_TX_DESC_BMC(pHalmac_buf))
+		if (_TRUE == GET_TX_DESC_AGG_EN(pHalmac_buf))
+			PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "TxDesc: Agg should not be set when BMC\n");
+
+	if (halmac_size < (GET_TX_DESC_TXPKTSIZE(pHalmac_buf) + GET_TX_DESC_OFFSET(pHalmac_buf)))
+		PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "TxDesc: PktSize too small\n");
+
+	/* PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_WARN, "halmac_chk_txdesc_88xx <==========\n"); */
+
+	return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * halmac_dl_drv_rsvd_page_88xx() - download packet to rsvd page
+ * @pHalmac_adapter : the adapter of halmac
+ * @pg_offset : page offset of driver's rsvd page
+ * @halmac_buf : data to be downloaded, tx_desc is not included
+ * @halmac_size : data size to be downloaded
+ * Author : KaiYuan Chang
+ * Return : HALMAC_RET_STATUS
+ * More details of status code can be found in prototype document
+ */
+HALMAC_RET_STATUS
+halmac_dl_drv_rsvd_page_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN u8 pg_offset,
+	IN u8 *pHalmac_buf,
+	IN u32 halmac_size
+)
+{
+	VOID *pDriver_adapter = NULL;
+	PHALMAC_API pHalmac_api;
+	HALMAC_RET_STATUS ret_status;
+	u16 drv_pg_bndy = 0;
+	u32 dl_pg_num = 0;
+
+
+	if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter))
+		return HALMAC_RET_ADAPTER_INVALID;
+
+	if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter))
+		return HALMAC_RET_API_INVALID;
+
+	halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_DL_DRV_RSVD_PG);
+
+	pDriver_adapter = pHalmac_adapter->pDriver_adapter;
+	pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api;
+
+	PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_dl_drv_rsvd_page_88xx ==========>\n");
+
+	/*check boundary and size valid*/
+	dl_pg_num = halmac_size/pHalmac_adapter->hw_config_info.page_size + ((halmac_size & (pHalmac_adapter->hw_config_info.page_size - 1)) ? 1 : 0);
+	if (pg_offset + dl_pg_num > pHalmac_adapter->txff_allocation.rsvd_drv_pg_num) {
+		PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "[ERROR] driver download offset or size error ==========>\n");
+		return HALMAC_RET_DRV_DL_ERR;
+	}
+
+	/*update to target download boundary*/
+	drv_pg_bndy = pHalmac_adapter->txff_allocation.rsvd_drv_pg_bndy + pg_offset;
+	HALMAC_REG_WRITE_16(pHalmac_adapter, REG_FIFOPAGE_CTRL_2, (u16)(drv_pg_bndy & BIT_MASK_BCN_HEAD_1_V1));
+
+	ret_status = halmac_download_rsvd_page_88xx(pHalmac_adapter, pHalmac_buf, halmac_size);
+
+	/*restore to original bundary*/
+	if (HALMAC_RET_SUCCESS != ret_status) {
+		PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "halmac_download_rsvd_page_88xx Fail = %x!!\n", ret_status);
+		HALMAC_REG_WRITE_16(pHalmac_adapter, REG_FIFOPAGE_CTRL_2, (u16)(pHalmac_adapter->txff_allocation.rsvd_pg_bndy & BIT_MASK_BCN_HEAD_1_V1));
+		return ret_status;
+	}
+
+	HALMAC_REG_WRITE_16(pHalmac_adapter, REG_FIFOPAGE_CTRL_2, (u16)(pHalmac_adapter->txff_allocation.rsvd_pg_bndy & BIT_MASK_BCN_HEAD_1_V1));
+
+	PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_dl_drv_rsvd_page_88xx < ==========\n");
+	return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * halmac_cfg_csi_rate_88xx() - config CSI frame Tx rate
+ * @pHalmac_adapter : the adapter of halmac
+ * @rssi : rssi in decimal value
+ * @current_rate : current CSI frame rate
+ * @fixrate_en : enable to fix CSI frame in VHT rate, otherwise legacy OFDM rate
+ * @new_rate : API returns the final CSI frame rate
+ * Author : chunchu
+ * Return : HALMAC_RET_STATUS
+ * More details of status code can be found in prototype document
+ */
+HALMAC_RET_STATUS
+halmac_cfg_csi_rate_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN u8 rssi,
+	IN u8 current_rate,
+	IN u8 fixrate_en,
+	OUT u8 *new_rate
+)
+{
+	VOID *pDriver_adapter = NULL;
+	PHALMAC_API pHalmac_api;
+	u32 temp_csi_setting;
+	u16 current_rrsr;
+
+	if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter))
+		return HALMAC_RET_ADAPTER_INVALID;
+
+	if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter))
+		return HALMAC_RET_API_INVALID;
+
+	halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_CFG_CSI_RATE);
+
+	pDriver_adapter = pHalmac_adapter->pDriver_adapter;
+	pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api;
+	PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_SND, HALMAC_DBG_TRACE, "halmac_cfg_csi_rate_88xx ==========>\n");
+
+#if HALMAC_8821C_SUPPORT
+	if (pHalmac_adapter->chip_id == HALMAC_CHIP_ID_8821C) {
+		if (fixrate_en) {
+			temp_csi_setting = HALMAC_REG_READ_32(pHalmac_adapter, REG_BBPSF_CTRL) & ~(BIT_MASK_WMAC_CSI_RATE << BIT_SHIFT_WMAC_CSI_RATE);
+			HALMAC_REG_WRITE_32(pHalmac_adapter, REG_BBPSF_CTRL, temp_csi_setting | BIT_CSI_FORCE_RATE_EN | BIT_CSI_RSC(1) | BIT_WMAC_CSI_RATE(HALMAC_VHT_NSS1_MCS3));
+			*new_rate = HALMAC_VHT_NSS1_MCS3;
+			return HALMAC_RET_SUCCESS;
+		}
+	}
+	temp_csi_setting = HALMAC_REG_READ_32(pHalmac_adapter, REG_BBPSF_CTRL) & ~(BIT_MASK_WMAC_CSI_RATE << BIT_SHIFT_WMAC_CSI_RATE) & ~BIT_CSI_FORCE_RATE_EN;
+#else
+	temp_csi_setting = HALMAC_REG_READ_32(pHalmac_adapter, REG_BBPSF_CTRL) & ~(BIT_MASK_WMAC_CSI_RATE << BIT_SHIFT_WMAC_CSI_RATE);
+#endif
+
+	current_rrsr = HALMAC_REG_READ_16(pHalmac_adapter, REG_RRSR);
+
+	if (rssi >= 40) {
+		if (current_rate != HALMAC_OFDM54) {
+			HALMAC_REG_WRITE_16(pHalmac_adapter, REG_RRSR, current_rrsr | BIT(HALMAC_OFDM54));
+			HALMAC_REG_WRITE_32(pHalmac_adapter, REG_BBPSF_CTRL, temp_csi_setting | BIT_WMAC_CSI_RATE(HALMAC_OFDM54));
+		}
+		*new_rate = HALMAC_OFDM54;
+		return HALMAC_RET_SUCCESS;
+	} else {
+		if (current_rate != HALMAC_OFDM24) {
+			HALMAC_REG_WRITE_16(pHalmac_adapter, REG_RRSR, current_rrsr & ~(BIT(HALMAC_OFDM54)));
+			HALMAC_REG_WRITE_32(pHalmac_adapter, REG_BBPSF_CTRL, temp_csi_setting | BIT_WMAC_CSI_RATE(HALMAC_OFDM24));
+		}
+		*new_rate = HALMAC_OFDM24;
+		return HALMAC_RET_SUCCESS;
+	}
+}
+
+/**
+ * halmac_txfifo_is_empty_88xx() -check if txfifo is empty
+ * @pHalmac_adapter : the adapter of halmac
+ * Author : Ivan Lin
+ * Return : HALMAC_RET_STATUS
+ * More details of status code can be found in prototype document
+ */
+HALMAC_RET_STATUS
+halmac_txfifo_is_empty_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN u32 chk_num
+)
+{
+	u32 counter;
+	VOID *pDriver_adapter = NULL;
+	PHALMAC_API pHalmac_api;
+
+	pDriver_adapter = pHalmac_adapter->pDriver_adapter;
+	pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api;
+
+	PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_COMMON, HALMAC_DBG_TRACE, "halmac_txfifo_is_empty_88xx ==========>\n");
+
+	counter = (chk_num <= 10) ? 10 : chk_num;
+	do {
+		if (0xFF != HALMAC_REG_READ_8(pHalmac_adapter, REG_TXPKT_EMPTY))
+			return HALMAC_RET_TXFIFO_NO_EMPTY;
+
+		if (0x07 != (HALMAC_REG_READ_8(pHalmac_adapter, REG_TXPKT_EMPTY + 1) & 0x07))
+			return HALMAC_RET_TXFIFO_NO_EMPTY;
+		counter--;
+
+	} while (0 != counter);
+
+	PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_COMMON, HALMAC_DBG_TRACE, "halmac_txfifo_is_empty_88xx <==========\n");
+
+	return HALMAC_RET_SUCCESS;
+}
+
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/halmac/halmac_88xx/halmac_api_88xx.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/halmac/halmac_88xx/halmac_api_88xx.h
--- linux-5.6.3/3rdparty/rtl8821ce/hal/halmac/halmac_88xx/halmac_api_88xx.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/halmac/halmac_88xx/halmac_api_88xx.h	2020-04-10 16:35:06.792658947 +0300
@@ -0,0 +1,607 @@
+#ifndef _HALMAC_API_88XX_H_
+#define _HALMAC_API_88XX_H_
+
+#include "../halmac_2_platform.h"
+#include "../halmac_type.h"
+
+VOID
+halmac_init_state_machine_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter
+);
+
+VOID
+halmac_init_adapter_para_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter
+);
+
+VOID
+halmac_init_adapter_dynamic_para_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter
+);
+
+HALMAC_RET_STATUS
+halmac_mount_api_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter
+);
+
+HALMAC_RET_STATUS
+halmac_download_firmware_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN u8 *pHamacl_fw,
+	IN u32 halmac_fw_size
+);
+
+HALMAC_RET_STATUS
+halmac_free_download_firmware_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN HALMAC_DLFW_MEM dlfw_mem,
+	IN u8 *pHamacl_fw,
+	IN u32 halmac_fw_size
+);
+
+HALMAC_RET_STATUS
+halmac_get_fw_version_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	OUT PHALMAC_FW_VERSION pFw_version
+);
+
+HALMAC_RET_STATUS
+halmac_cfg_mac_addr_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN u8 halmac_port,
+	IN PHALMAC_WLAN_ADDR pHal_address
+);
+
+HALMAC_RET_STATUS
+halmac_cfg_bssid_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN u8 halmac_port,
+	IN PHALMAC_WLAN_ADDR pHal_address
+);
+
+HALMAC_RET_STATUS
+halmac_cfg_multicast_addr_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN PHALMAC_WLAN_ADDR pHal_address
+);
+
+HALMAC_RET_STATUS
+halmac_pre_init_system_cfg_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter
+);
+
+HALMAC_RET_STATUS
+halmac_init_system_cfg_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter
+);
+
+HALMAC_RET_STATUS
+halmac_cfg_rx_aggregation_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN HALMAC_RXAGG_CFG halmac_rxagg_cfg
+);
+
+HALMAC_RET_STATUS
+halmac_init_edca_cfg_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter
+);
+
+HALMAC_RET_STATUS
+halmac_cfg_operation_mode_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN HALMAC_WIRELESS_MODE wireless_mode
+);
+
+HALMAC_RET_STATUS
+halmac_cfg_ch_bw_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN u8 channel,
+	IN HALMAC_PRI_CH_IDX pri_ch_idx,
+	IN HALMAC_BW bw
+);
+
+HALMAC_RET_STATUS
+halmac_cfg_ch_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN u8 channel
+);
+
+HALMAC_RET_STATUS
+halmac_cfg_pri_ch_idx_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN HALMAC_PRI_CH_IDX pri_ch_idx
+);
+
+HALMAC_RET_STATUS
+halmac_cfg_bw_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN HALMAC_BW bw
+);
+
+HALMAC_RET_STATUS
+halmac_init_wmac_cfg_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter
+);
+
+HALMAC_RET_STATUS
+halmac_init_mac_cfg_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN HALMAC_TRX_MODE mode
+);
+
+HALMAC_RET_STATUS
+halmac_dump_efuse_map_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN HALMAC_EFUSE_READ_CFG cfg
+);
+
+HALMAC_RET_STATUS
+halmac_dump_efuse_map_bt_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN HALMAC_EFUSE_BANK halmac_efuse_bank,
+	IN u32 bt_efuse_map_size,
+	OUT u8 *pBT_efuse_map
+);
+
+HALMAC_RET_STATUS
+halmac_write_efuse_bt_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN u32 halmac_offset,
+	IN u8 halmac_value,
+	IN HALMAC_EFUSE_BANK halmac_efuse_bank
+);
+
+HALMAC_RET_STATUS
+halmac_pg_efuse_by_map_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN PHALMAC_PG_EFUSE_INFO pPg_efuse_info,
+	IN HALMAC_EFUSE_READ_CFG cfg
+);
+
+HALMAC_RET_STATUS
+halmac_get_efuse_size_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	OUT u32 *halmac_size
+);
+
+HALMAC_RET_STATUS
+halmac_get_efuse_available_size_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	OUT u32 *halmac_size
+);
+
+HALMAC_RET_STATUS
+halmac_get_c2h_info_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN u8 *halmac_buf,
+	IN u32 halmac_size
+);
+
+HALMAC_RET_STATUS
+halmac_get_logical_efuse_size_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	OUT u32 *halmac_size
+);
+
+HALMAC_RET_STATUS
+halmac_dump_logical_efuse_map_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN HALMAC_EFUSE_READ_CFG cfg
+);
+
+HALMAC_RET_STATUS
+halmac_write_logical_efuse_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN u32 halmac_offset,
+	IN u8 halmac_value
+);
+
+HALMAC_RET_STATUS
+halmac_read_logical_efuse_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN u32 halmac_offset,
+	OUT u8 *pValue
+);
+
+HALMAC_RET_STATUS
+halmac_cfg_fwlps_option_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN PHALMAC_FWLPS_OPTION pLps_option
+);
+
+HALMAC_RET_STATUS
+halmac_cfg_fwips_option_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN PHALMAC_FWIPS_OPTION pIps_option
+);
+
+HALMAC_RET_STATUS
+halmac_enter_wowlan_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN PHALMAC_WOWLAN_OPTION pWowlan_option
+);
+
+HALMAC_RET_STATUS
+halmac_leave_wowlan_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter
+);
+
+HALMAC_RET_STATUS
+halmac_enter_ps_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN HALMAC_PS_STATE ps_state
+);
+
+HALMAC_RET_STATUS
+halmac_leave_ps_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter
+);
+
+HALMAC_RET_STATUS
+halmac_h2c_lb_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter
+);
+
+HALMAC_RET_STATUS
+halmac_debug_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter
+);
+
+HALMAC_RET_STATUS
+halmac_cfg_parameter_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN PHALMAC_PHY_PARAMETER_INFO para_info,
+	IN u8 full_fifo
+);
+
+HALMAC_RET_STATUS
+halmac_update_packet_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN HALMAC_PACKET_ID pkt_id,
+	IN u8 *pkt,
+	IN u32 pkt_size
+);
+
+HALMAC_RET_STATUS
+halmac_bcn_ie_filter_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN PHALMAC_BCN_IE_INFO pBcn_ie_info
+);
+
+HALMAC_RET_STATUS
+halmac_send_original_h2c_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN u8 *original_h2c,
+	IN u16 *seq,
+	IN u8 ack
+);
+
+HALMAC_RET_STATUS
+halmac_update_datapack_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN HALMAC_DATA_TYPE halmac_data_type,
+	IN PHALMAC_PHY_PARAMETER_INFO para_info
+);
+
+HALMAC_RET_STATUS
+halmac_run_datapack_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN HALMAC_DATA_TYPE halmac_data_type
+);
+
+HALMAC_RET_STATUS
+halmac_cfg_drv_info_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN HALMAC_DRV_INFO halmac_drv_info
+);
+
+HALMAC_RET_STATUS
+halmac_send_bt_coex_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN u8 *pBt_buf,
+	IN u32 bt_size,
+	IN u8 ack
+);
+
+HALMAC_RET_STATUS
+halmac_verify_platform_api_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter
+);
+
+HALMAC_RET_STATUS
+halmac_timer_2s_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter
+);
+
+HALMAC_RET_STATUS
+halmac_fill_txdesc_check_sum_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN u8 *cur_desc
+);
+
+HALMAC_RET_STATUS
+halmac_dump_fifo_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN HAL_FIFO_SEL halmac_fifo_sel,
+	IN u32 halmac_start_addr,
+	IN u32 halmac_fifo_dump_size,
+	OUT u8 *pFifo_map
+);
+
+u32
+halmac_get_fifo_size_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN HAL_FIFO_SEL halmac_fifo_sel
+);
+
+HALMAC_RET_STATUS
+halmac_cfg_txbf_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN u8 userid,
+	IN HALMAC_BW bw,
+	IN u8 txbf_en
+);
+
+HALMAC_RET_STATUS
+halmac_cfg_mumimo_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN PHALMAC_CFG_MUMIMO_PARA pCfgmu
+);
+
+HALMAC_RET_STATUS
+halmac_cfg_sounding_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN HALMAC_SND_ROLE role,
+	IN HALMAC_DATA_RATE datarate
+);
+
+HALMAC_RET_STATUS
+halmac_del_sounding_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN HALMAC_SND_ROLE role
+);
+
+HALMAC_RET_STATUS
+halmac_su_bfee_entry_init_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN u8 userid,
+	IN u16 paid
+);
+
+HALMAC_RET_STATUS
+halmac_su_bfer_entry_init_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN PHALMAC_SU_BFER_INIT_PARA pSu_bfer_init
+);
+
+HALMAC_RET_STATUS
+halmac_mu_bfee_entry_init_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN PHALMAC_MU_BFEE_INIT_PARA pMu_bfee_init
+);
+
+HALMAC_RET_STATUS
+halmac_mu_bfer_entry_init_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN PHALMAC_MU_BFER_INIT_PARA pMu_bfer_init
+);
+
+HALMAC_RET_STATUS
+halmac_su_bfee_entry_del_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN u8 userid
+);
+
+HALMAC_RET_STATUS
+halmac_su_bfer_entry_del_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN u8 userid
+);
+
+HALMAC_RET_STATUS
+halmac_mu_bfee_entry_del_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN u8 userid
+);
+
+HALMAC_RET_STATUS
+halmac_mu_bfer_entry_del_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter
+);
+
+HALMAC_RET_STATUS
+halmac_add_ch_info_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN PHALMAC_CH_INFO pCh_info
+);
+
+HALMAC_RET_STATUS
+halmac_add_extra_ch_info_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN PHALMAC_CH_EXTRA_INFO pCh_extra_info
+);
+
+HALMAC_RET_STATUS
+halmac_ctrl_ch_switch_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN PHALMAC_CH_SWITCH_OPTION pCs_option
+);
+
+HALMAC_RET_STATUS
+halmac_p2pps_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN PHALMAC_P2PPS	pP2PPS
+);
+
+static HALMAC_RET_STATUS
+halmac_func_p2pps_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN PHALMAC_P2PPS	pP2PPS
+);
+
+HALMAC_RET_STATUS
+halmac_clear_ch_info_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter
+);
+
+HALMAC_RET_STATUS
+halmac_send_general_info_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN PHALMAC_GENERAL_INFO pGeneral_info
+);
+
+HALMAC_RET_STATUS
+halmac_start_iqk_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN PHALMAC_IQK_PARA pIqk_para
+);
+
+HALMAC_RET_STATUS
+halmac_ctrl_pwr_tracking_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN PHALMAC_PWR_TRACKING_OPTION pPwr_tracking_opt
+);
+
+HALMAC_RET_STATUS
+halmac_query_status_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN HALMAC_FEATURE_ID feature_id,
+	OUT HALMAC_CMD_PROCESS_STATUS *pProcess_status,
+	INOUT u8 *data,
+	INOUT u32 *size
+);
+
+HALMAC_RET_STATUS
+halmac_reset_feature_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN HALMAC_FEATURE_ID feature_id
+);
+
+HALMAC_RET_STATUS
+halmac_check_fw_status_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	OUT u8 *fw_status
+);
+
+HALMAC_RET_STATUS
+halmac_dump_fw_dmem_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	INOUT u8 *dmem,
+	INOUT u32 *size
+);
+
+HALMAC_RET_STATUS
+halmac_cfg_max_dl_size_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN u32 size
+);
+
+
+HALMAC_RET_STATUS
+halmac_psd_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN u16 start_psd,
+	IN u16 end_psd
+);
+
+HALMAC_RET_STATUS
+halmac_cfg_la_mode_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN HALMAC_LA_MODE la_mode
+);
+
+HALMAC_RET_STATUS
+halmac_cfg_rx_fifo_expanding_mode_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN HALMAC_RX_FIFO_EXPANDING_MODE rx_fifo_expanding_mode
+);
+
+HALMAC_RET_STATUS
+halmac_config_security_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN PHALMAC_SECURITY_SETTING pSec_setting
+);
+
+u8
+halmac_get_used_cam_entry_num_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN HAL_SECURITY_TYPE sec_type
+);
+
+HALMAC_RET_STATUS
+halmac_write_cam_88xx(
+	IN PHALMAC_ADAPTER	pHalmac_adapter,
+	IN u32 entry_index,
+	IN PHALMAC_CAM_ENTRY_INFO pCam_entry_info
+);
+
+HALMAC_RET_STATUS
+halmac_read_cam_entry_88xx(
+	IN PHALMAC_ADAPTER	pHalmac_adapter,
+	IN u32 entry_index,
+	OUT PHALMAC_CAM_ENTRY_FORMAT pContent
+);
+
+HALMAC_RET_STATUS
+halmac_clear_cam_entry_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN u32 entry_index
+);
+
+HALMAC_RET_STATUS
+halmac_get_hw_value_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN HALMAC_HW_ID hw_id,
+	OUT VOID *pvalue
+);
+
+HALMAC_RET_STATUS
+halmac_set_hw_value_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN HALMAC_HW_ID hw_id,
+	IN VOID *pvalue
+);
+
+HALMAC_RET_STATUS
+halmac_cfg_drv_rsvd_pg_num_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN HALMAC_DRV_RSVD_PG_NUM pg_num
+);
+
+HALMAC_RET_STATUS
+halmac_get_chip_version_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN PHALMAC_VER pVersion
+);
+
+HALMAC_RET_STATUS
+halmac_chk_txdesc_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN u8 *pHalmac_buf,
+	IN u32 halmac_size
+);
+
+HALMAC_RET_STATUS
+halmac_dl_drv_rsvd_page_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN u8 pg_offset,
+	IN u8 *pHalmac_buf,
+	IN u32 halmac_size
+);
+
+HALMAC_RET_STATUS
+halmac_cfg_csi_rate_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN u8 rssi,
+	IN u8 current_rate,
+	IN u8 fixrate_en,
+	OUT u8 *new_rate
+);
+
+HALMAC_RET_STATUS
+halmac_txfifo_is_empty_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN u32 chk_num
+);
+
+#endif/* _HALMAC_API_H_ */
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/halmac/halmac_88xx/halmac_api_88xx_pcie.c linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/halmac/halmac_88xx/halmac_api_88xx_pcie.c
--- linux-5.6.3/3rdparty/rtl8821ce/hal/halmac/halmac_88xx/halmac_api_88xx_pcie.c	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/halmac/halmac_88xx/halmac_api_88xx_pcie.c	2020-04-10 16:35:06.792658947 +0300
@@ -0,0 +1,322 @@
+#include "halmac_88xx_cfg.h"
+
+/**
+ * halmac_init_pcie_cfg_88xx() -  init PCIe
+ * @pHalmac_adapter : the adapter of halmac
+ * Author : KaiYuan Chang
+ * Return : HALMAC_RET_STATUS
+ * More details of status code can be found in prototype document
+ */
+HALMAC_RET_STATUS
+halmac_init_pcie_cfg_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter
+)
+{
+	VOID *pDriver_adapter = NULL;
+
+	if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter))
+		return HALMAC_RET_ADAPTER_INVALID;
+
+	if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter))
+		return HALMAC_RET_API_INVALID;
+
+	halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_INIT_PCIE_CFG);
+
+	pDriver_adapter = pHalmac_adapter->pDriver_adapter;
+
+	PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_init_pcie_cfg_88xx ==========>\n");
+
+	PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_init_pcie_cfg_88xx <==========\n");
+
+	return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * halmac_deinit_pcie_cfg_88xx() - deinit PCIE
+ * @pHalmac_adapter : the adapter of halmac
+ * Author : KaiYuan Chang
+ * Return : HALMAC_RET_STATUS
+ * More details of status code can be found in prototype document
+ */
+HALMAC_RET_STATUS
+halmac_deinit_pcie_cfg_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter
+)
+{
+	VOID *pDriver_adapter = NULL;
+
+	if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter))
+		return HALMAC_RET_ADAPTER_INVALID;
+
+	if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter))
+		return HALMAC_RET_API_INVALID;
+
+	halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_DEINIT_PCIE_CFG);
+
+	pDriver_adapter = pHalmac_adapter->pDriver_adapter;
+
+	PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_deinit_pcie_cfg_88xx ==========>\n");
+
+	PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_deinit_pcie_cfg_88xx <==========\n");
+
+	return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * halmac_cfg_rx_aggregation_88xx_pcie() - config rx aggregation
+ * @pHalmac_adapter : the adapter of halmac
+ * @halmac_rx_agg_mode
+ * Author : KaiYuan Chang/Ivan Lin
+ * Return : HALMAC_RET_STATUS
+ * More details of status code can be found in prototype document
+ */
+HALMAC_RET_STATUS
+halmac_cfg_rx_aggregation_88xx_pcie(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN PHALMAC_RXAGG_CFG phalmac_rxagg_cfg
+)
+{
+	VOID *pDriver_adapter = NULL;
+
+	if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter))
+		return HALMAC_RET_ADAPTER_INVALID;
+
+	if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter))
+		return HALMAC_RET_API_INVALID;
+
+	halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_CFG_RX_AGGREGATION);
+
+	pDriver_adapter = pHalmac_adapter->pDriver_adapter;
+
+	PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_cfg_rx_aggregation_88xx_pcie ==========>\n");
+
+	PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_cfg_rx_aggregation_88xx_pcie <==========\n");
+
+	return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * halmac_reg_read_8_pcie_88xx() - read 1byte register
+ * @pHalmac_adapter : the adapter of halmac
+ * @halmac_offset : register offset
+ * Author : KaiYuan Chang/Ivan Lin
+ * Return : HALMAC_RET_STATUS
+ * More details of status code can be found in prototype document
+ */
+u8
+halmac_reg_read_8_pcie_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN u32 halmac_offset
+)
+{
+	VOID *pDriver_adapter = NULL;
+	PHALMAC_API pHalmac_api;
+
+	if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter))
+		return HALMAC_RET_ADAPTER_INVALID;
+
+	if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter))
+		return HALMAC_RET_API_INVALID;
+
+	pDriver_adapter = pHalmac_adapter->pDriver_adapter;
+	pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api;
+
+	return PLATFORM_REG_READ_8(pDriver_adapter, halmac_offset);
+}
+
+/**
+ * halmac_reg_write_8_pcie_88xx() - write 1byte register
+ * @pHalmac_adapter : the adapter of halmac
+ * @halmac_offset : register offset
+ * @halmac_data : register value
+ * Author : KaiYuan Chang/Ivan Lin
+ * Return : HALMAC_RET_STATUS
+ * More details of status code can be found in prototype document
+ */
+HALMAC_RET_STATUS
+halmac_reg_write_8_pcie_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN u32 halmac_offset,
+	IN u8 halmac_data
+)
+{
+	VOID *pDriver_adapter = NULL;
+	PHALMAC_API pHalmac_api;
+
+	if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter))
+		return HALMAC_RET_ADAPTER_INVALID;
+
+	if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter))
+		return HALMAC_RET_API_INVALID;
+
+	pDriver_adapter = pHalmac_adapter->pDriver_adapter;
+	pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api;
+
+	PLATFORM_REG_WRITE_8(pDriver_adapter, halmac_offset, halmac_data);
+
+	return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * halmac_reg_read_16_pcie_88xx() - read 2byte register
+ * @pHalmac_adapter : the adapter of halmac
+ * @halmac_offset : register offset
+ * Author : KaiYuan Chang/Ivan Lin
+ * Return : HALMAC_RET_STATUS
+ * More details of status code can be found in prototype document
+ */
+u16
+halmac_reg_read_16_pcie_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN u32 halmac_offset
+)
+{
+	VOID *pDriver_adapter = NULL;
+	PHALMAC_API pHalmac_api;
+
+	if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter))
+		return HALMAC_RET_ADAPTER_INVALID;
+
+	if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter))
+		return HALMAC_RET_API_INVALID;
+
+	pDriver_adapter = pHalmac_adapter->pDriver_adapter;
+	pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api;
+
+	return PLATFORM_REG_READ_16(pDriver_adapter, halmac_offset);
+}
+
+/**
+ * halmac_reg_write_16_pcie_88xx() - write 2byte register
+ * @pHalmac_adapter : the adapter of halmac
+ * @halmac_offset : register offset
+ * @halmac_data : register value
+ * Author : KaiYuan Chang/Ivan Lin
+ * Return : HALMAC_RET_STATUS
+ * More details of status code can be found in prototype document
+ */
+HALMAC_RET_STATUS
+halmac_reg_write_16_pcie_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN u32 halmac_offset,
+	IN u16 halmac_data
+)
+{
+	VOID *pDriver_adapter = NULL;
+	PHALMAC_API pHalmac_api;
+
+	if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter))
+		return HALMAC_RET_ADAPTER_INVALID;
+
+	if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter))
+		return HALMAC_RET_API_INVALID;
+
+	pDriver_adapter = pHalmac_adapter->pDriver_adapter;
+	pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api;
+
+	PLATFORM_REG_WRITE_16(pDriver_adapter, halmac_offset, halmac_data);
+
+	return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * halmac_reg_read_32_pcie_88xx() - read 4byte register
+ * @pHalmac_adapter : the adapter of halmac
+ * @halmac_offset : register offset
+ * Author : KaiYuan Chang/Ivan Lin
+ * Return : HALMAC_RET_STATUS
+ * More details of status code can be found in prototype document
+ */
+u32
+halmac_reg_read_32_pcie_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN u32 halmac_offset
+)
+{
+	VOID *pDriver_adapter = NULL;
+	PHALMAC_API pHalmac_api;
+
+	if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter))
+		return HALMAC_RET_ADAPTER_INVALID;
+
+	if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter))
+		return HALMAC_RET_API_INVALID;
+
+	pDriver_adapter = pHalmac_adapter->pDriver_adapter;
+	pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api;
+
+	return PLATFORM_REG_READ_32(pDriver_adapter, halmac_offset);
+}
+
+/**
+ * halmac_reg_write_32_pcie_88xx() - write 4byte register
+ * @pHalmac_adapter : the adapter of halmac
+ * @halmac_offset : register offset
+ * @halmac_data : register value
+ * Author : KaiYuan Chang/Ivan Lin
+ * Return : HALMAC_RET_STATUS
+ * More details of status code can be found in prototype document
+ */
+HALMAC_RET_STATUS
+halmac_reg_write_32_pcie_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN u32 halmac_offset,
+	IN u32 halmac_data
+)
+{
+	VOID *pDriver_adapter = NULL;
+	PHALMAC_API pHalmac_api;
+
+	if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter))
+		return HALMAC_RET_ADAPTER_INVALID;
+
+	if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter))
+		return HALMAC_RET_API_INVALID;
+
+	pDriver_adapter = pHalmac_adapter->pDriver_adapter;
+	pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api;
+
+	PLATFORM_REG_WRITE_32(pDriver_adapter, halmac_offset, halmac_data);
+
+	return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * halmac_cfg_tx_agg_align_pcie_88xx() -config sdio bus tx agg alignment
+ * @pHalmac_adapter : the adapter of halmac
+ * @enable : function enable(1)/disable(0)
+ * @align_size : sdio bus tx agg alignment size (2^n, n = 3~11)
+ * Author : Soar Tu
+ * Return : HALMAC_RET_STATUS
+ * More details of status code can be found in prototype document
+ */
+HALMAC_RET_STATUS
+halmac_cfg_tx_agg_align_pcie_not_support_88xx(
+	IN PHALMAC_ADAPTER	pHalmac_adapter,
+	IN u8	enable,
+	IN u16	align_size
+)
+{
+	PHALMAC_API pHalmac_api;
+	VOID *pDriver_adapter = NULL;
+
+	if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter))
+		return HALMAC_RET_ADAPTER_INVALID;
+
+	if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter))
+		return HALMAC_RET_API_INVALID;
+
+	halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_CFG_TX_AGG_ALIGN);
+
+	pDriver_adapter = pHalmac_adapter->pDriver_adapter;
+	pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api;
+
+
+	PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_cfg_tx_agg_align_pcie_not_support_88xx ==========>\n");
+
+	PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_cfg_tx_agg_align_pcie_not_support_88xx not support\n");
+	PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_cfg_tx_agg_align_pcie_not_support_88xx <==========\n");
+
+	return HALMAC_RET_SUCCESS;
+}
+
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/halmac/halmac_88xx/halmac_api_88xx_pcie.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/halmac/halmac_88xx/halmac_api_88xx_pcie.h
--- linux-5.6.3/3rdparty/rtl8821ce/hal/halmac/halmac_88xx/halmac_api_88xx_pcie.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/halmac/halmac_88xx/halmac_api_88xx_pcie.h	2020-04-10 16:35:06.792658947 +0300
@@ -0,0 +1,76 @@
+#ifndef _HALMAC_API_88XX_PCIE_H_
+#define _HALMAC_API_88XX_PCIE_H_
+
+#include "../halmac_2_platform.h"
+#include "../halmac_type.h"
+
+#define LINK_CTRL2_REG_OFFSET	0xA0
+#define GEN2_CTRL_OFFSET		0x80C
+#define LINK_STATUS_REG_OFFSET	0x82
+#define GEN1_SPEED				0x01
+#define GEN2_SPEED				0x02
+
+
+HALMAC_RET_STATUS
+halmac_init_pcie_cfg_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter
+);
+
+HALMAC_RET_STATUS
+halmac_deinit_pcie_cfg_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter
+);
+
+HALMAC_RET_STATUS
+halmac_cfg_rx_aggregation_88xx_pcie(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN PHALMAC_RXAGG_CFG phalmac_rxagg_cfg
+);
+
+u8
+halmac_reg_read_8_pcie_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN u32 halmac_offset
+);
+
+HALMAC_RET_STATUS
+halmac_reg_write_8_pcie_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN u32 halmac_offset,
+	IN u8 halmac_data
+);
+
+u16
+halmac_reg_read_16_pcie_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN u32 halmac_offset
+);
+
+HALMAC_RET_STATUS
+halmac_reg_write_16_pcie_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN u32 halmac_offset,
+	IN u16 halmac_data
+);
+
+u32
+halmac_reg_read_32_pcie_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN u32 halmac_offset
+);
+
+HALMAC_RET_STATUS
+halmac_reg_write_32_pcie_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN u32 halmac_offset,
+	IN u32 halmac_data
+);
+
+HALMAC_RET_STATUS
+halmac_cfg_tx_agg_align_pcie_not_support_88xx(
+	IN PHALMAC_ADAPTER	pHalmac_adapter,
+	IN u8	enable,
+	IN u16	align_size
+);
+
+#endif/* _HALMAC_API_88XX_PCIE_H_ */
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/halmac/halmac_88xx/halmac_api_88xx_sdio.c linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/halmac/halmac_88xx/halmac_api_88xx_sdio.c
--- linux-5.6.3/3rdparty/rtl8821ce/hal/halmac/halmac_88xx/halmac_api_88xx_sdio.c	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/halmac/halmac_88xx/halmac_api_88xx_sdio.c	2020-04-10 16:35:06.792658947 +0300
@@ -0,0 +1,975 @@
+#include "halmac_88xx_cfg.h"
+
+/**
+ * halmac_init_sdio_cfg_88xx() - init SDIO
+ * @pHalmac_adapter : the adapter of halmac
+ * Author : KaiYuan Chang/Ivan Lin
+ * Return : HALMAC_RET_STATUS
+ * More details of status code can be found in prototype document
+ */
+HALMAC_RET_STATUS
+halmac_init_sdio_cfg_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter
+)
+{
+	VOID *pDriver_adapter = NULL;
+	PHALMAC_API pHalmac_api;
+	u8 data[16] = {0};
+
+	if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter))
+		return HALMAC_RET_ADAPTER_INVALID;
+
+	if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter))
+		return HALMAC_RET_API_INVALID;
+
+	halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_INIT_SDIO_CFG);
+
+	pDriver_adapter = pHalmac_adapter->pDriver_adapter;
+	pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api;
+
+	PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_init_sdio_cfg_88xx ==========>\n");
+
+	HALMAC_REG_READ_32(pHalmac_adapter, REG_SDIO_FREE_TXPG);
+	HALMAC_REG_WRITE_32(pHalmac_adapter, REG_SDIO_TX_CTRL, 0x00000000);
+
+	PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_init_sdio_cfg_88xx <==========\n");
+
+	return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * halmac_deinit_sdio_cfg_88xx() - deinit SDIO
+ * @pHalmac_adapter : the adapter of halmac
+ * Author : KaiYuan Chang/Ivan Lin
+ * Return : HALMAC_RET_STATUS
+ * More details of status code can be found in prototype document
+ */
+HALMAC_RET_STATUS
+halmac_deinit_sdio_cfg_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter
+)
+{
+	VOID *pDriver_adapter = NULL;
+
+	if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter))
+		return HALMAC_RET_ADAPTER_INVALID;
+
+	if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter))
+		return HALMAC_RET_API_INVALID;
+
+	halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_DEINIT_SDIO_CFG);
+
+	pDriver_adapter = pHalmac_adapter->pDriver_adapter;
+
+	PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_deinit_sdio_cfg_88xx ==========>\n");
+
+	PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_deinit_sdio_cfg_88xx <==========\n");
+
+	return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * halmac_cfg_rx_aggregation_88xx_sdio() - config rx aggregation
+ * @pHalmac_adapter : the adapter of halmac
+ * @halmac_rx_agg_mode
+ * Author : KaiYuan Chang/Ivan Lin
+ * Return : HALMAC_RET_STATUS
+ * More details of status code can be found in prototype document
+ */
+HALMAC_RET_STATUS
+halmac_cfg_rx_aggregation_88xx_sdio(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN PHALMAC_RXAGG_CFG phalmac_rxagg_cfg
+)
+{
+	u8 value8;
+	u8 size = 0, timeout = 0, agg_enable = 0;
+	VOID *pDriver_adapter = NULL;
+	PHALMAC_API pHalmac_api;
+
+	if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter))
+		return HALMAC_RET_ADAPTER_INVALID;
+
+	if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter))
+		return HALMAC_RET_API_INVALID;
+
+	halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_CFG_RX_AGGREGATION);
+
+	pDriver_adapter = pHalmac_adapter->pDriver_adapter;
+	pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api;
+
+	PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_cfg_rx_aggregation_88xx_sdio ==========>\n");
+
+	agg_enable = HALMAC_REG_READ_8(pHalmac_adapter, REG_TXDMA_PQ_MAP);
+
+	switch (phalmac_rxagg_cfg->mode) {
+	case HALMAC_RX_AGG_MODE_NONE:
+		agg_enable &= ~(BIT_RXDMA_AGG_EN);
+		break;
+	case HALMAC_RX_AGG_MODE_DMA:
+	case HALMAC_RX_AGG_MODE_USB:
+		agg_enable |= BIT_RXDMA_AGG_EN;
+		break;
+	default:
+		PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "halmac_cfg_rx_aggregation_88xx_usb switch case not support\n");
+		agg_enable &= ~BIT_RXDMA_AGG_EN;
+		break;
+	}
+
+	if (_FALSE == phalmac_rxagg_cfg->threshold.drv_define) {
+		size = 0xFF;
+		timeout = 0x01;
+	} else {
+		size = phalmac_rxagg_cfg->threshold.size;
+		timeout = phalmac_rxagg_cfg->threshold.timeout;
+	}
+
+	HALMAC_REG_WRITE_8(pHalmac_adapter, REG_TXDMA_PQ_MAP, agg_enable);
+	HALMAC_REG_WRITE_16(pHalmac_adapter, REG_RXDMA_AGG_PG_TH, (u16)(size | (timeout << BIT_SHIFT_DMA_AGG_TO_V1)));
+
+	value8 = HALMAC_REG_READ_8(pHalmac_adapter, REG_RXDMA_MODE);
+	if (0 != (agg_enable & BIT_RXDMA_AGG_EN))
+		HALMAC_REG_WRITE_8(pHalmac_adapter, REG_RXDMA_MODE, value8 | BIT_DMA_MODE);
+	else
+		HALMAC_REG_WRITE_8(pHalmac_adapter, REG_RXDMA_MODE, value8 & ~(BIT_DMA_MODE));
+
+	PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_cfg_rx_aggregation_88xx_sdio <==========\n");
+
+	return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * halmac_reg_read_8_sdio_88xx() - read 1byte register
+ * @pHalmac_adapter : the adapter of halmac
+ * @halmac_offset : register offset
+ * Author : KaiYuan Chang/Ivan Lin
+ * Return : HALMAC_RET_STATUS
+ * More details of status code can be found in prototype document
+ */
+u8
+halmac_reg_read_8_sdio_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN u32 halmac_offset
+)
+{
+	u8 value8;
+	VOID *pDriver_adapter = NULL;
+	PHALMAC_API pHalmac_api;
+	HALMAC_RET_STATUS status = HALMAC_RET_SUCCESS;
+
+	if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter))
+		return HALMAC_RET_ADAPTER_INVALID;
+
+	if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter))
+		return HALMAC_RET_API_INVALID;
+
+	pDriver_adapter = pHalmac_adapter->pDriver_adapter;
+	pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api;
+
+	if (0 == (halmac_offset & 0xFFFF0000))
+		halmac_offset |= WLAN_IOREG_OFFSET;
+
+	status = halmac_convert_to_sdio_bus_offset_88xx(pHalmac_adapter, &halmac_offset);
+
+	if (HALMAC_RET_SUCCESS != status) {
+		PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "halmac_reg_read_8_sdio_88xx error = %x\n", status);
+		return status;
+	}
+
+	value8 = PLATFORM_SDIO_CMD52_READ(pDriver_adapter, halmac_offset);
+
+	return value8;
+}
+
+/**
+ * halmac_reg_write_8_sdio_88xx() - write 1byte register
+ * @pHalmac_adapter : the adapter of halmac
+ * @halmac_offset : register offset
+ * @halmac_data : register value
+ * Author : KaiYuan Chang/Ivan Lin
+ * Return : HALMAC_RET_STATUS
+ * More details of status code can be found in prototype document
+ */
+HALMAC_RET_STATUS
+halmac_reg_write_8_sdio_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN u32 halmac_offset,
+	IN u8 halmac_data
+)
+{
+	VOID *pDriver_adapter = NULL;
+	PHALMAC_API pHalmac_api;
+	HALMAC_RET_STATUS status = HALMAC_RET_SUCCESS;
+
+	if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter))
+		return HALMAC_RET_ADAPTER_INVALID;
+
+	if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter))
+		return HALMAC_RET_API_INVALID;
+
+	pDriver_adapter = pHalmac_adapter->pDriver_adapter;
+	pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api;
+
+	if (0 == (halmac_offset & 0xFFFF0000))
+		halmac_offset |= WLAN_IOREG_OFFSET;
+
+	status = halmac_convert_to_sdio_bus_offset_88xx(pHalmac_adapter, &halmac_offset);
+
+	if (HALMAC_RET_SUCCESS != status) {
+		PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "halmac_reg_write_8_sdio_88xx error = %x\n", status);
+		return status;
+	}
+
+	PLATFORM_SDIO_CMD52_WRITE(pDriver_adapter, halmac_offset, halmac_data);
+
+	return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * halmac_reg_read_16_sdio_88xx() - read 2byte register
+ * @pHalmac_adapter : the adapter of halmac
+ * @halmac_offset : register offset
+ * Author : KaiYuan Chang/Ivan Lin
+ * Return : HALMAC_RET_STATUS
+ * More details of status code can be found in prototype document
+ */
+u16
+halmac_reg_read_16_sdio_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN u32 halmac_offset
+)
+{
+	VOID *pDriver_adapter = NULL;
+	PHALMAC_API pHalmac_api;
+	HALMAC_RET_STATUS status = HALMAC_RET_SUCCESS;
+	u32 halmac_offset_old = 0;
+
+	union {
+		u16	word;
+		u8	byte[2];
+	} value16 = { 0x0000 };
+
+	if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter))
+		return HALMAC_RET_ADAPTER_INVALID;
+
+	if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter))
+		return HALMAC_RET_API_INVALID;
+
+	pDriver_adapter = pHalmac_adapter->pDriver_adapter;
+	pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api;
+
+	halmac_offset_old = halmac_offset;
+
+	if (0 == (halmac_offset & 0xFFFF0000))
+		halmac_offset |= WLAN_IOREG_OFFSET;
+
+	status = halmac_convert_to_sdio_bus_offset_88xx(pHalmac_adapter, &halmac_offset);
+
+	if (HALMAC_RET_SUCCESS != status) {
+		PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "halmac_reg_read_16_sdio_88xx error = %x\n", status);
+		return status;
+	}
+
+	if ((HALMAC_MAC_POWER_OFF == pHalmac_adapter->halmac_state.mac_power) || (0 != (halmac_offset & (2 - 1))) ||
+		(HALMAC_SDIO_CMD53_4BYTE_MODE_RW == pHalmac_adapter->sdio_cmd53_4byte) || (HALMAC_SDIO_CMD53_4BYTE_MODE_R == pHalmac_adapter->sdio_cmd53_4byte)) {
+		PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_COMMON, HALMAC_DBG_TRACE, "[WARN]use cmd52, offset = %x\n", halmac_offset);
+		value16.byte[0] = PLATFORM_SDIO_CMD52_READ(pDriver_adapter, halmac_offset);
+		value16.byte[1] = PLATFORM_SDIO_CMD52_READ(pDriver_adapter, halmac_offset + 1);
+		value16.word = rtk_le16_to_cpu(value16.word);
+	} else {
+		if (pHalmac_adapter->sdio_hw_info.io_hi_speed_flag != 0) {
+			if ((halmac_offset_old & 0xffffef00) == 0x00000000) {
+				value16.byte[0] = PLATFORM_SDIO_CMD52_READ(pDriver_adapter, halmac_offset);
+				value16.byte[1] = PLATFORM_SDIO_CMD52_READ(pDriver_adapter, halmac_offset + 1);
+				value16.word = rtk_le16_to_cpu(value16.word);
+			} else {
+				value16.word = PLATFORM_SDIO_CMD53_READ_16(pDriver_adapter, halmac_offset);
+			}
+		} else {
+			value16.word = PLATFORM_SDIO_CMD53_READ_16(pDriver_adapter, halmac_offset);
+		}
+	}
+
+	return value16.word;
+}
+
+/**
+ * halmac_reg_write_16_sdio_88xx() - write 2byte register
+ * @pHalmac_adapter : the adapter of halmac
+ * @halmac_offset : register offset
+ * @halmac_data : register value
+ * Author : KaiYuan Chang/Ivan Lin
+ * Return : HALMAC_RET_STATUS
+ * More details of status code can be found in prototype document
+ */
+HALMAC_RET_STATUS
+halmac_reg_write_16_sdio_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN u32 halmac_offset,
+	IN u16 halmac_data
+)
+{
+	VOID *pDriver_adapter = NULL;
+	PHALMAC_API pHalmac_api;
+	HALMAC_RET_STATUS status = HALMAC_RET_SUCCESS;
+
+	if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter))
+		return HALMAC_RET_ADAPTER_INVALID;
+
+	if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter))
+		return HALMAC_RET_API_INVALID;
+
+	pDriver_adapter = pHalmac_adapter->pDriver_adapter;
+	pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api;
+
+	if (0 == (halmac_offset & 0xFFFF0000))
+		halmac_offset |= WLAN_IOREG_OFFSET;
+
+	status = halmac_convert_to_sdio_bus_offset_88xx(pHalmac_adapter, &halmac_offset);
+
+	if (HALMAC_RET_SUCCESS != status) {
+		PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "halmac_reg_write_16_sdio_88xx error = %x\n", status);
+		return status;
+	}
+
+	if ((HALMAC_MAC_POWER_OFF == pHalmac_adapter->halmac_state.mac_power) || (0 != (halmac_offset & (2 - 1))) ||
+		(HALMAC_SDIO_CMD53_4BYTE_MODE_RW == pHalmac_adapter->sdio_cmd53_4byte) || (HALMAC_SDIO_CMD53_4BYTE_MODE_W == pHalmac_adapter->sdio_cmd53_4byte)) {
+		PLATFORM_SDIO_CMD52_WRITE(pDriver_adapter, halmac_offset, (u8)(halmac_data & 0xFF));
+		PLATFORM_SDIO_CMD52_WRITE(pDriver_adapter, halmac_offset + 1, (u8)((halmac_data & 0xFF00) >> 8));
+	} else {
+		PLATFORM_SDIO_CMD53_WRITE_16(pDriver_adapter, halmac_offset, halmac_data);
+	}
+
+	return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * halmac_reg_read_32_sdio_88xx() - read 4byte register
+ * @pHalmac_adapter : the adapter of halmac
+ * @halmac_offset : register offset
+ * Author : KaiYuan Chang/Ivan Lin
+ * Return : HALMAC_RET_STATUS
+ * More details of status code can be found in prototype document
+ */
+u32
+halmac_reg_read_32_sdio_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN u32 halmac_offset
+)
+{
+	VOID *pDriver_adapter = NULL;
+	PHALMAC_API pHalmac_api;
+	HALMAC_RET_STATUS status = HALMAC_RET_SUCCESS;
+    u32 halmac_offset_old = 0;
+
+	union {
+		u32	dword;
+		u8	byte[4];
+	} value32 = { 0x00000000 };
+
+	if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter))
+		return HALMAC_RET_ADAPTER_INVALID;
+
+	if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter))
+		return HALMAC_RET_API_INVALID;
+
+	pDriver_adapter = pHalmac_adapter->pDriver_adapter;
+	pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api;
+
+    halmac_offset_old = halmac_offset;
+
+	if (0 == (halmac_offset & 0xFFFF0000))
+		halmac_offset |= WLAN_IOREG_OFFSET;
+
+	status = halmac_convert_to_sdio_bus_offset_88xx(pHalmac_adapter, &halmac_offset);
+	if (HALMAC_RET_SUCCESS != status) {
+		PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "halmac_reg_read_32_sdio_88xx error = %x\n", status);
+		return status;
+	}
+
+	if (HALMAC_MAC_POWER_OFF == pHalmac_adapter->halmac_state.mac_power || 0 != (halmac_offset & (4 - 1))) {
+		PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_COMMON, HALMAC_DBG_TRACE, "[WARN]use cmd52, offset = %x\n", halmac_offset);
+		value32.byte[0] = PLATFORM_SDIO_CMD52_READ(pDriver_adapter, halmac_offset);
+		value32.byte[1] = PLATFORM_SDIO_CMD52_READ(pDriver_adapter, halmac_offset + 1);
+		value32.byte[2] = PLATFORM_SDIO_CMD52_READ(pDriver_adapter, halmac_offset + 2);
+		value32.byte[3] = PLATFORM_SDIO_CMD52_READ(pDriver_adapter, halmac_offset + 3);
+		value32.dword = rtk_le32_to_cpu(value32.dword);
+	} else {
+		if (pHalmac_adapter->sdio_hw_info.io_hi_speed_flag != 0) {
+			if ((halmac_offset_old & 0xffffef00) == 0x00000000) {
+				value32.byte[0] = PLATFORM_SDIO_CMD52_READ(pDriver_adapter, halmac_offset);
+				value32.byte[1] = PLATFORM_SDIO_CMD52_READ(pDriver_adapter, halmac_offset + 1);
+				value32.byte[2] = PLATFORM_SDIO_CMD52_READ(pDriver_adapter, halmac_offset + 2);
+				value32.byte[3] = PLATFORM_SDIO_CMD52_READ(pDriver_adapter, halmac_offset + 3);
+				value32.dword = rtk_le32_to_cpu(value32.dword);
+			} else {
+				value32.dword = PLATFORM_SDIO_CMD53_READ_32(pDriver_adapter, halmac_offset);
+			}
+		} else {
+			value32.dword = PLATFORM_SDIO_CMD53_READ_32(pDriver_adapter, halmac_offset);
+		}
+	}
+
+	return value32.dword;
+}
+
+/**
+ * halmac_reg_write_32_sdio_88xx() - write 4byte register
+ * @pHalmac_adapter : the adapter of halmac
+ * @halmac_offset : register offset
+ * @halmac_data : register value
+ * Author : KaiYuan Chang/Ivan Lin
+ * Return : HALMAC_RET_STATUS
+ * More details of status code can be found in prototype document
+ */
+HALMAC_RET_STATUS
+halmac_reg_write_32_sdio_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN u32 halmac_offset,
+	IN u32 halmac_data
+)
+{
+	VOID *pDriver_adapter = NULL;
+	PHALMAC_API pHalmac_api;
+	HALMAC_RET_STATUS status = HALMAC_RET_SUCCESS;
+
+	if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter))
+		return HALMAC_RET_ADAPTER_INVALID;
+
+	if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter))
+		return HALMAC_RET_API_INVALID;
+
+	pDriver_adapter = pHalmac_adapter->pDriver_adapter;
+	pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api;
+
+	if (0 == (halmac_offset & 0xFFFF0000))
+		halmac_offset |= WLAN_IOREG_OFFSET;
+
+	status = halmac_convert_to_sdio_bus_offset_88xx(pHalmac_adapter, &halmac_offset);
+
+	if (HALMAC_RET_SUCCESS != status) {
+		PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "halmac_reg_write_32_sdio_88xx error = %x\n", status);
+		return status;
+	}
+
+	if (HALMAC_MAC_POWER_OFF == pHalmac_adapter->halmac_state.mac_power || 0 != (halmac_offset & (4 - 1))) {
+		PLATFORM_SDIO_CMD52_WRITE(pDriver_adapter, halmac_offset, (u8)(halmac_data & 0xFF));
+		PLATFORM_SDIO_CMD52_WRITE(pDriver_adapter, halmac_offset + 1, (u8)((halmac_data & 0xFF00) >> 8));
+		PLATFORM_SDIO_CMD52_WRITE(pDriver_adapter, halmac_offset + 2, (u8)((halmac_data & 0xFF0000) >> 16));
+		PLATFORM_SDIO_CMD52_WRITE(pDriver_adapter, halmac_offset + 3, (u8)((halmac_data & 0xFF000000) >> 24));
+	} else {
+		PLATFORM_SDIO_CMD53_WRITE_32(pDriver_adapter, halmac_offset, halmac_data);
+	}
+
+	return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * halmac_reg_read_nbyte_sdio_88xx() - read n byte register
+ * @pHalmac_adapter : the adapter of halmac
+ * @halmac_offset : register offset
+ * @halmac_size : register value size
+ * @halmac_data : register value
+ * Author : Soar
+ * Return : HALMAC_RET_STATUS
+ * More details of status code can be found in prototype document
+ */
+u8
+halmac_reg_read_nbyte_sdio_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN u32 halmac_offset,
+	IN u32 halmac_size,
+	OUT u8 *halmac_data
+)
+{
+	u8 rtemp = 0xFF;
+	u32 counter = 1000;
+	VOID *pDriver_adapter = NULL;
+	PHALMAC_API pHalmac_api;
+	HALMAC_RET_STATUS status = HALMAC_RET_SUCCESS;
+
+	union {
+		u32	dword;
+		u8	byte[4];
+	} value32 = { 0x00000000 };
+
+	if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter))
+		return HALMAC_RET_ADAPTER_INVALID;
+
+	if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter))
+		return HALMAC_RET_API_INVALID;
+
+	pDriver_adapter = pHalmac_adapter->pDriver_adapter;
+	pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api;
+
+	if (0 == (halmac_offset & 0xFFFF0000)) {
+		PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "halmac_offset error = 0x%x\n", halmac_offset);
+		return HALMAC_RET_FAIL;
+	}
+
+	status = halmac_convert_to_sdio_bus_offset_88xx(pHalmac_adapter, &halmac_offset);
+	if (HALMAC_RET_SUCCESS != status) {
+		PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "halmac_reg_read_nbyte_sdio_88xx error = %x\n", status);
+		return status;
+	}
+
+	if (HALMAC_MAC_POWER_OFF == pHalmac_adapter->halmac_state.mac_power) {
+		PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "halmac_state error = 0x%x\n", pHalmac_adapter->halmac_state.mac_power);
+		return HALMAC_RET_FAIL;
+	}
+
+	PLATFORM_SDIO_CMD53_READ_N(pDriver_adapter, halmac_offset, halmac_size, halmac_data);
+
+	return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * halmac_get_sdio_tx_addr_sdio_88xx() - get CMD53 addr for the TX packet
+ * @pHalmac_adapter : the adapter of halmac
+ * @halmac_buf : tx packet, include txdesc
+ * @halmac_size : tx packet size
+ * @pcmd53_addr : cmd53 addr value
+ * Author : KaiYuan Chang/Ivan Lin
+ * Return : HALMAC_RET_STATUS
+ * More details of status code can be found in prototype document
+ */
+HALMAC_RET_STATUS
+halmac_get_sdio_tx_addr_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN u8 *halmac_buf,
+	IN u32 halmac_size,
+	OUT u32 *pcmd53_addr
+)
+{
+	u32 four_byte_len;
+	VOID *pDriver_adapter = NULL;
+	PHALMAC_API pHalmac_api;
+	HALMAC_QUEUE_SELECT queue_sel;
+	HALMAC_DMA_MAPPING dma_mapping;
+
+	if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter))
+		return HALMAC_RET_ADAPTER_INVALID;
+
+	if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter))
+		return HALMAC_RET_API_INVALID;
+
+	halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_GET_SDIO_TX_ADDR);
+
+	pDriver_adapter = pHalmac_adapter->pDriver_adapter;
+	pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api;
+
+	PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_get_sdio_tx_addr_88xx ==========>\n");
+
+	if (NULL == halmac_buf) {
+		PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "halmac_buf is NULL!!\n");
+		return HALMAC_RET_DATA_BUF_NULL;
+	}
+
+	if (0 == halmac_size) {
+		PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "halmac_size is 0!!\n");
+		return HALMAC_RET_DATA_SIZE_INCORRECT;
+	}
+
+	queue_sel = (HALMAC_QUEUE_SELECT)GET_TX_DESC_QSEL(halmac_buf);
+
+	switch (queue_sel) {
+	case HALMAC_QUEUE_SELECT_VO:
+	case HALMAC_QUEUE_SELECT_VO_V2:
+		dma_mapping = pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_VO];
+		break;
+	case HALMAC_QUEUE_SELECT_VI:
+	case HALMAC_QUEUE_SELECT_VI_V2:
+		dma_mapping = pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_VI];
+		break;
+	case HALMAC_QUEUE_SELECT_BE:
+	case HALMAC_QUEUE_SELECT_BE_V2:
+		dma_mapping = pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_BE];
+		break;
+	case HALMAC_QUEUE_SELECT_BK:
+	case HALMAC_QUEUE_SELECT_BK_V2:
+		dma_mapping = pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_BK];
+		break;
+	case HALMAC_QUEUE_SELECT_MGNT:
+		dma_mapping = pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_MG];
+		break;
+	case HALMAC_QUEUE_SELECT_HIGH:
+	case HALMAC_QUEUE_SELECT_BCN:
+	case HALMAC_QUEUE_SELECT_CMD:
+		dma_mapping = pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_HI];
+		break;
+	default:
+		PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "Qsel is out of range\n");
+		return HALMAC_RET_QSEL_INCORRECT;
+	}
+
+	four_byte_len = (halmac_size >> 2) + ((halmac_size & (4 - 1)) ? 1 : 0);
+
+	switch (dma_mapping) {
+	case HALMAC_DMA_MAPPING_HIGH:
+		*pcmd53_addr = HALMAC_SDIO_CMD_ADDR_TXFF_HIGH;
+		break;
+	case HALMAC_DMA_MAPPING_NORMAL:
+		*pcmd53_addr = HALMAC_SDIO_CMD_ADDR_TXFF_NORMAL;
+		break;
+	case HALMAC_DMA_MAPPING_LOW:
+		*pcmd53_addr = HALMAC_SDIO_CMD_ADDR_TXFF_LOW;
+		break;
+	case HALMAC_DMA_MAPPING_EXTRA:
+		*pcmd53_addr = HALMAC_SDIO_CMD_ADDR_TXFF_EXTRA;
+		break;
+	default:
+		PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "DmaMapping is out of range\n");
+		return HALMAC_RET_DMA_MAP_INCORRECT;
+	}
+
+	*pcmd53_addr = (*pcmd53_addr << 13) | (four_byte_len & HALMAC_SDIO_4BYTE_LEN_MASK);
+
+	PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_get_sdio_tx_addr_88xx <==========\n");
+
+	return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * halmac_cfg_tx_agg_align_sdio_88xx() -config sdio bus tx agg alignment
+ * @pHalmac_adapter : the adapter of halmac
+ * @enable : function enable(1)/disable(0)
+ * @align_size : sdio bus tx agg alignment size (2^n, n = 3~11)
+ * Author : Soar Tu
+ * Return : HALMAC_RET_STATUS
+ * More details of status code can be found in prototype document
+ */
+HALMAC_RET_STATUS
+halmac_cfg_tx_agg_align_sdio_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN u8 enable,
+	IN u16 align_size
+)
+{
+	PHALMAC_API pHalmac_api;
+	VOID *pDriver_adapter = NULL;
+	u8 i, align_size_ok = 0;
+
+	if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter))
+		return HALMAC_RET_ADAPTER_INVALID;
+
+	if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter))
+		return HALMAC_RET_API_INVALID;
+
+	halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_CFG_TX_AGG_ALIGN);
+
+	pDriver_adapter = pHalmac_adapter->pDriver_adapter;
+	pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api;
+
+
+	PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_cfg_tx_agg_align_sdio_88xx ==========>\n");
+
+	if ((align_size & 0xF000) != 0) {
+		PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "Align size is out of range\n");
+		return HALMAC_RET_FAIL;
+	}
+
+	for (i = 3; i <= 11; i++) {
+		if (align_size == 1 << i) {
+			align_size_ok = 1;
+			break;
+		}
+	}
+	if (align_size_ok == 0) {
+		PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "Align size is not 2^3 ~ 2^11\n");
+		return HALMAC_RET_FAIL;
+	}
+
+	/*Keep sdio tx agg alignment size for driver query*/
+	pHalmac_adapter->hw_config_info.tx_align_size = align_size;
+
+	if (enable)
+		HALMAC_REG_WRITE_16(pHalmac_adapter, REG_RQPN_CTRL_2, 0x8000 | align_size);
+	else
+		HALMAC_REG_WRITE_16(pHalmac_adapter, REG_RQPN_CTRL_2, align_size);
+
+	PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_cfg_tx_agg_align_sdio_88xx <==========\n");
+
+	return HALMAC_RET_SUCCESS;
+}
+
+HALMAC_RET_STATUS
+halmac_cfg_tx_agg_align_sdio_not_support_88xx(
+	IN PHALMAC_ADAPTER	pHalmac_adapter,
+	IN u8	enable,
+	IN u16	align_size
+)
+{
+	PHALMAC_API pHalmac_api;
+	VOID *pDriver_adapter = NULL;
+
+	if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter))
+		return HALMAC_RET_ADAPTER_INVALID;
+
+	if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter))
+		return HALMAC_RET_API_INVALID;
+
+	halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_CFG_TX_AGG_ALIGN);
+
+	pDriver_adapter = pHalmac_adapter->pDriver_adapter;
+	pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api;
+
+
+	PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_cfg_tx_agg_align_sdio_not_support_88xx ==========>\n");
+
+	PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_cfg_tx_agg_align_sdio_not_support_88xx not support\n");
+	PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_cfg_tx_agg_align_sdio_not_support_88xx <==========\n");
+
+	return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * halmac_tx_allowed_sdio_88xx() - check tx status
+ * @pHalmac_adapter : the adapter of halmac
+ * @pHalmac_buf : tx packet, include txdesc
+ * @halmac_size : tx packet size, include txdesc
+ * Author : Ivan Lin
+ * Return : HALMAC_RET_STATUS
+ * More details of status code can be found in prototype document
+ */
+HALMAC_RET_STATUS
+halmac_tx_allowed_sdio_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN u8 *pHalmac_buf,
+	IN u32 halmac_size
+)
+{
+	u8 *pCurr_packet;
+	u16 *pCurr_free_space;
+	u32 i, counter;
+	u32 tx_agg_num, packet_size = 0;
+	u32 tx_required_page_num, total_required_page_num = 0;
+	HALMAC_RET_STATUS status = HALMAC_RET_SUCCESS;
+	VOID *pDriver_adapter = NULL;
+	HALMAC_DMA_MAPPING dma_mapping;
+
+	if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter))
+		return HALMAC_RET_ADAPTER_INVALID;
+
+	if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter))
+		return HALMAC_RET_API_INVALID;
+
+	halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_TX_ALLOWED_SDIO);
+
+	pDriver_adapter = pHalmac_adapter->pDriver_adapter;
+
+	PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_tx_allowed_sdio_88xx ==========>\n");
+
+	tx_agg_num = GET_TX_DESC_DMA_TXAGG_NUM(pHalmac_buf);
+	pCurr_packet = pHalmac_buf;
+
+	tx_agg_num = (tx_agg_num == 0) ? 1 : tx_agg_num;
+
+	switch ((HALMAC_QUEUE_SELECT)GET_TX_DESC_QSEL(pCurr_packet)) {
+	case HALMAC_QUEUE_SELECT_VO:
+	case HALMAC_QUEUE_SELECT_VO_V2:
+		dma_mapping = pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_VO];
+		break;
+	case HALMAC_QUEUE_SELECT_VI:
+	case HALMAC_QUEUE_SELECT_VI_V2:
+		dma_mapping = pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_VI];
+		break;
+	case HALMAC_QUEUE_SELECT_BE:
+	case HALMAC_QUEUE_SELECT_BE_V2:
+		dma_mapping = pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_BE];
+		break;
+	case HALMAC_QUEUE_SELECT_BK:
+	case HALMAC_QUEUE_SELECT_BK_V2:
+		dma_mapping = pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_BK];
+		break;
+	case HALMAC_QUEUE_SELECT_MGNT:
+		dma_mapping = pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_MG];
+		break;
+	case HALMAC_QUEUE_SELECT_HIGH:
+		dma_mapping = pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_HI];
+		break;
+	case HALMAC_QUEUE_SELECT_BCN:
+	case HALMAC_QUEUE_SELECT_CMD:
+		return HALMAC_RET_SUCCESS;
+	default:
+		PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "Qsel is out of range\n");
+		return HALMAC_RET_QSEL_INCORRECT;
+	}
+
+	switch (dma_mapping) {
+	case HALMAC_DMA_MAPPING_HIGH:
+		pCurr_free_space = &(pHalmac_adapter->sdio_free_space.high_queue_number);
+		break;
+	case HALMAC_DMA_MAPPING_NORMAL:
+		pCurr_free_space = &(pHalmac_adapter->sdio_free_space.normal_queue_number);
+		break;
+	case HALMAC_DMA_MAPPING_LOW:
+		pCurr_free_space = &(pHalmac_adapter->sdio_free_space.low_queue_number);
+		break;
+	case HALMAC_DMA_MAPPING_EXTRA:
+		pCurr_free_space = &(pHalmac_adapter->sdio_free_space.extra_queue_number);
+		break;
+	default:
+		PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "DmaMapping is out of range\n");
+		return HALMAC_RET_DMA_MAP_INCORRECT;
+	}
+
+	for (i = 0; i < tx_agg_num; i++) {
+		packet_size = GET_TX_DESC_TXPKTSIZE(pCurr_packet) + GET_TX_DESC_OFFSET(pCurr_packet) + (GET_TX_DESC_PKT_OFFSET(pCurr_packet) << 3);
+		tx_required_page_num = (packet_size >> pHalmac_adapter->hw_config_info.page_size_2_power) + ((packet_size & (pHalmac_adapter->hw_config_info.page_size - 1)) ? 1 : 0);
+		total_required_page_num += tx_required_page_num;
+
+		packet_size = HALMAC_ALIGN(packet_size, 8);
+
+		pCurr_packet += packet_size;
+	}
+
+	counter = 10;
+	do {
+		if ((u32)(*pCurr_free_space + pHalmac_adapter->sdio_free_space.public_queue_number) > total_required_page_num) {
+			if (*pCurr_free_space >= total_required_page_num) {
+				*pCurr_free_space -= (u16)total_required_page_num;
+			} else {
+				pHalmac_adapter->sdio_free_space.public_queue_number -= (u16)(total_required_page_num - *pCurr_free_space);
+				*pCurr_free_space = 0;
+			}
+
+			status = halmac_check_oqt_88xx(pHalmac_adapter, tx_agg_num, pHalmac_buf);
+
+			if (HALMAC_RET_SUCCESS != status)
+				return status;
+
+			break;
+		} else {
+			halmac_update_sdio_free_page_88xx(pHalmac_adapter);
+		}
+
+		counter--;
+		if (0 == counter)
+			return HALMAC_RET_FREE_SPACE_NOT_ENOUGH;
+	} while (1);
+
+	PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_tx_allowed_sdio_88xx <==========\n");
+
+	return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * halmac_reg_read_indirect_32_sdio_88xx() - read MAC reg by SDIO reg
+ * @pHalmac_adapter : the adapter of halmac
+ * @halmac_offset : register offset
+ * Author : Soar
+ * Return : HALMAC_RET_STATUS
+ * More details of status code can be found in prototype document
+ */
+u32
+halmac_reg_read_indirect_32_sdio_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN u32 halmac_offset
+)
+{
+	u8 rtemp;
+	u32 counter = 1000;
+	VOID *pDriver_adapter = NULL;
+
+	union {
+		u32	dword;
+		u8	byte[4];
+	} value32 = { 0x00000000 };
+
+	if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter))
+		return HALMAC_RET_ADAPTER_INVALID;
+
+	if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter))
+		return HALMAC_RET_API_INVALID;
+
+	pDriver_adapter = pHalmac_adapter->pDriver_adapter;
+
+	PLATFORM_SDIO_CMD53_WRITE_32(pDriver_adapter, (HALMAC_SDIO_CMD_ADDR_SDIO_REG << 13) | (REG_SDIO_INDIRECT_REG_CFG & HALMAC_SDIO_LOCAL_MSK), halmac_offset | BIT(19) | BIT(17));
+
+	do {
+		rtemp = PLATFORM_SDIO_CMD52_READ(pDriver_adapter, (HALMAC_SDIO_CMD_ADDR_SDIO_REG << 13) | ((REG_SDIO_INDIRECT_REG_CFG + 2) & HALMAC_SDIO_LOCAL_MSK));
+		counter--;
+	} while (((rtemp & BIT(4)) != 0) && (counter > 0));
+
+	value32.dword = PLATFORM_SDIO_CMD53_READ_32(pDriver_adapter, (HALMAC_SDIO_CMD_ADDR_SDIO_REG << 13) | (REG_SDIO_INDIRECT_REG_DATA & HALMAC_SDIO_LOCAL_MSK));
+
+	return value32.dword;
+}
+
+
+/**
+ * halmac_sdio_cmd53_4byte_88xx() - cmd53 only for 4byte len register IO
+ * @pHalmac_adapter : the adapter of halmac
+ * @enable : 1->CMD53 only use in 4byte reg, 0 : No limitation
+ * Author : Ivan Lin/KaiYuan Chang
+ * Return : HALMAC_RET_STATUS
+ * More details of status code can be found in prototype document
+ */
+HALMAC_RET_STATUS
+halmac_sdio_cmd53_4byte_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN HALMAC_SDIO_CMD53_4BYTE_MODE cmd53_4byte_mode
+)
+{
+	if (halmac_adapter_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS)
+		return HALMAC_RET_ADAPTER_INVALID;
+
+	if (halmac_api_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS)
+		return HALMAC_RET_API_INVALID;
+
+	if (pHalmac_adapter->halmac_interface != HALMAC_INTERFACE_SDIO)
+		return HALMAC_RET_WRONG_INTF;
+
+	pHalmac_adapter->sdio_cmd53_4byte = cmd53_4byte_mode;
+
+	return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * halmac_sdio_hw_info_88xx() - info sdio hw info
+ * @pHalmac_adapter : the adapter of halmac
+ * @HALMAC_SDIO_CMD53_4BYTE_MODE :
+ * clock_speed : sdio bus clock. Unit -> MHz
+ * spec_ver : sdio spec version
+ * Author : Ivan Lin
+ * Return : HALMAC_RET_STATUS
+ * More details of status code can be found in prototype document
+ */
+HALMAC_RET_STATUS
+halmac_sdio_hw_info_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN PHALMAC_SDIO_HW_INFO pSdio_hw_info
+)
+{
+	VOID *pDriver_adapter = NULL;
+	PHALMAC_API pHalmac_api;
+
+	pDriver_adapter = pHalmac_adapter->pDriver_adapter;
+	pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api;
+
+	PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "[TRACE]halmac_sdio_hw_info_88xx ==========>\n");
+
+	if (halmac_adapter_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS)
+		return HALMAC_RET_ADAPTER_INVALID;
+
+	if (halmac_api_validate(pHalmac_adapter) != HALMAC_RET_SUCCESS)
+		return HALMAC_RET_API_INVALID;
+
+	if (pHalmac_adapter->halmac_interface != HALMAC_INTERFACE_SDIO)
+		return HALMAC_RET_WRONG_INTF;
+
+	PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "[TRACE]SDIO hw clock : %d, spec : %d\n", pSdio_hw_info->clock_speed, pSdio_hw_info->spec_ver);
+
+	if (pSdio_hw_info->clock_speed > HALMAC_SDIO_CLOCK_SPEED_MAX_88XX)
+		return HALMAC_RET_SDIO_CLOCK_ERR;
+
+	if (pSdio_hw_info->clock_speed > HALMAC_SDIO_CLK_THRESHOLD_88XX)
+		pHalmac_adapter->sdio_hw_info.io_hi_speed_flag = 1;
+
+	pHalmac_adapter->sdio_hw_info.clock_speed = pSdio_hw_info->clock_speed;
+	pHalmac_adapter->sdio_hw_info.spec_ver = pSdio_hw_info->spec_ver;
+
+	PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "[TRACE]halmac_sdio_hw_info_88xx <==========\n");
+
+	return HALMAC_RET_SUCCESS;
+}
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/halmac/halmac_88xx/halmac_api_88xx_sdio.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/halmac/halmac_88xx/halmac_api_88xx_sdio.h
--- linux-5.6.3/3rdparty/rtl8821ce/hal/halmac/halmac_88xx/halmac_api_88xx_sdio.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/halmac/halmac_88xx/halmac_api_88xx_sdio.h	2020-04-10 16:35:06.792658947 +0300
@@ -0,0 +1,118 @@
+#ifndef _HALMAC_API_88XX_SDIO_H_
+#define _HALMAC_API_88XX_SDIO_H_
+
+#include "../halmac_2_platform.h"
+#include "../halmac_type.h"
+
+HALMAC_RET_STATUS
+halmac_init_sdio_cfg_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter
+);
+
+HALMAC_RET_STATUS
+halmac_deinit_sdio_cfg_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter
+);
+
+HALMAC_RET_STATUS
+halmac_cfg_rx_aggregation_88xx_sdio(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN PHALMAC_RXAGG_CFG phalmac_rxagg_cfg
+);
+
+u8
+halmac_reg_read_8_sdio_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN u32 halmac_offset
+);
+
+HALMAC_RET_STATUS
+halmac_reg_write_8_sdio_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN u32 halmac_offset,
+	IN u8 halmac_data
+);
+
+u16
+halmac_reg_read_16_sdio_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN u32 halmac_offset
+);
+
+HALMAC_RET_STATUS
+halmac_reg_write_16_sdio_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN u32 halmac_offset,
+	IN u16 halmac_data
+);
+
+u32
+halmac_reg_read_32_sdio_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN u32 halmac_offset
+);
+
+HALMAC_RET_STATUS
+halmac_reg_write_32_sdio_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN u32 halmac_offset,
+	IN u32 halmac_data
+);
+
+HALMAC_RET_STATUS
+halmac_get_sdio_tx_addr_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN u8 *halmac_buf,
+	IN u32 halmac_size,
+	OUT u32 *pcmd53_addr
+);
+
+HALMAC_RET_STATUS
+halmac_cfg_tx_agg_align_sdio_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN u8 enable,
+	IN u16 align_size
+);
+
+HALMAC_RET_STATUS
+halmac_cfg_tx_agg_align_sdio_not_support_88xx(
+	IN PHALMAC_ADAPTER	pHalmac_adapter,
+	IN u8	enable,
+	IN u16	align_size
+);
+
+HALMAC_RET_STATUS
+halmac_tx_allowed_sdio_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN u8 *pHalmac_buf,
+	IN u32 halmac_size
+);
+
+u32
+halmac_reg_read_indirect_32_sdio_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN u32 halmac_offset
+);
+
+
+HALMAC_RET_STATUS
+halmac_sdio_cmd53_4byte_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN HALMAC_SDIO_CMD53_4BYTE_MODE cmd53_4byte_mode
+);
+
+u8
+halmac_reg_read_nbyte_sdio_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN u32 halmac_offset,
+	IN u32 halmac_size,
+	OUT u8 *halmac_data
+);
+
+HALMAC_RET_STATUS
+halmac_sdio_hw_info_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN PHALMAC_SDIO_HW_INFO pSdio_hw_info
+);
+
+#endif/* _HALMAC_API_88XX_SDIO_H_ */
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/halmac/halmac_88xx/halmac_api_88xx_usb.c linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/halmac/halmac_88xx/halmac_api_88xx_usb.c
--- linux-5.6.3/3rdparty/rtl8821ce/hal/halmac/halmac_88xx/halmac_api_88xx_usb.c	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/halmac/halmac_88xx/halmac_api_88xx_usb.c	2020-04-10 16:35:06.792658947 +0300
@@ -0,0 +1,563 @@
+#include "halmac_88xx_cfg.h"
+
+/**
+ * halmac_init_usb_cfg_88xx() - init USB
+ * @pHalmac_adapter : the adapter of halmac
+ * Author : KaiYuan Chang/Ivan Lin
+ * Return : HALMAC_RET_STATUS
+ * More details of status code can be found in prototype document
+ */
+HALMAC_RET_STATUS
+halmac_init_usb_cfg_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter
+)
+{
+	VOID *pDriver_adapter = NULL;
+	u8 value8 = 0;
+
+	if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter))
+		return HALMAC_RET_ADAPTER_INVALID;
+
+	if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter))
+		return HALMAC_RET_API_INVALID;
+
+	halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_INIT_USB_CFG);
+
+	pDriver_adapter = pHalmac_adapter->pDriver_adapter;
+
+	PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_init_usb_cfg_88xx ==========>\n");
+
+	value8 |= (BIT_DMA_MODE | (0x3 << BIT_SHIFT_BURST_CNT)); /* burst number = 4 */
+
+	if (PLATFORM_REG_READ_8(pDriver_adapter, REG_SYS_CFG2 + 3) == 0x20) { /* usb3.0 */
+		value8 |= (HALMAC_USB_BURST_SIZE_3_0 << BIT_SHIFT_BURST_SIZE);
+	} else {
+		if ((PLATFORM_REG_READ_8(pDriver_adapter, REG_USB_USBSTAT) & 0x3) == 0x1) /* usb2.0 */
+			value8 |= HALMAC_USB_BURST_SIZE_2_0_HSPEED << BIT_SHIFT_BURST_SIZE;
+		else /* usb1.1 */
+			value8 |= HALMAC_USB_BURST_SIZE_2_0_FSPEED << BIT_SHIFT_BURST_SIZE;
+	}
+
+	PLATFORM_REG_WRITE_8(pDriver_adapter, REG_RXDMA_MODE, value8);
+	PLATFORM_REG_WRITE_16(pDriver_adapter, REG_TXDMA_OFFSET_CHK, PLATFORM_REG_READ_16(pDriver_adapter, REG_TXDMA_OFFSET_CHK) | BIT_DROP_DATA_EN);
+
+	PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_init_usb_cfg_88xx <==========\n");
+
+	return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * halmac_deinit_usb_cfg_88xx() - deinit USB
+ * @pHalmac_adapter : the adapter of halmac
+ * Author : KaiYuan Chang/Ivan Lin
+ * Return : HALMAC_RET_STATUS
+ * More details of status code can be found in prototype document
+ */
+HALMAC_RET_STATUS
+halmac_deinit_usb_cfg_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter
+)
+{
+	VOID *pDriver_adapter = NULL;
+
+	if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter))
+		return HALMAC_RET_ADAPTER_INVALID;
+
+	if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter))
+		return HALMAC_RET_API_INVALID;
+
+	halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_DEINIT_USB_CFG);
+
+	pDriver_adapter = pHalmac_adapter->pDriver_adapter;
+
+	PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_deinit_usb_cfg_88xx ==========>\n");
+
+	PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_deinit_usb_cfg_88xx <==========\n");
+
+	return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * halmac_cfg_rx_aggregation_88xx_usb() - config rx aggregation
+ * @pHalmac_adapter : the adapter of halmac
+ * @halmac_rx_agg_mode
+ * Author : KaiYuan Chang/Ivan Lin
+ * Return : HALMAC_RET_STATUS
+ * More details of status code can be found in prototype document
+ */
+HALMAC_RET_STATUS
+halmac_cfg_rx_aggregation_88xx_usb(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN PHALMAC_RXAGG_CFG phalmac_rxagg_cfg
+)
+{
+	u8 dma_usb_agg;
+	u8 size = 0, timeout = 0, agg_enable = 0;
+	VOID *pDriver_adapter = NULL;
+	PHALMAC_API pHalmac_api;
+
+	if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter))
+		return HALMAC_RET_ADAPTER_INVALID;
+
+	if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter))
+		return HALMAC_RET_API_INVALID;
+
+	halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_CFG_RX_AGGREGATION);
+
+	pDriver_adapter = pHalmac_adapter->pDriver_adapter;
+	pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api;
+
+	PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_cfg_rx_aggregation_88xx_usb ==========>\n");
+
+	dma_usb_agg = HALMAC_REG_READ_8(pHalmac_adapter, REG_RXDMA_AGG_PG_TH + 3);
+	agg_enable = HALMAC_REG_READ_8(pHalmac_adapter, REG_TXDMA_PQ_MAP);
+
+	switch (phalmac_rxagg_cfg->mode) {
+	case HALMAC_RX_AGG_MODE_NONE:
+		agg_enable &= ~BIT_RXDMA_AGG_EN;
+		break;
+	case HALMAC_RX_AGG_MODE_DMA:
+		agg_enable |= BIT_RXDMA_AGG_EN;
+		dma_usb_agg |= BIT(7);
+		break;
+
+	case HALMAC_RX_AGG_MODE_USB:
+		agg_enable |= BIT_RXDMA_AGG_EN;
+		dma_usb_agg &= ~BIT(7);
+		break;
+	default:
+		PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "halmac_cfg_rx_aggregation_88xx_usb switch case not support\n");
+		agg_enable &= ~BIT_RXDMA_AGG_EN;
+		break;
+	}
+
+	if (_FALSE == phalmac_rxagg_cfg->threshold.drv_define) {
+		if (PLATFORM_REG_READ_8(pDriver_adapter, REG_SYS_CFG2 + 3) == 0x20) {
+			/* usb3.0 */
+			size = 0x5;
+			timeout = 0xA;
+		} else {
+			/* usb2.0 */
+			size = 0x5;
+			timeout = 0x20;
+		}
+	} else {
+		size = phalmac_rxagg_cfg->threshold.size;
+		timeout = phalmac_rxagg_cfg->threshold.timeout;
+	}
+
+	HALMAC_REG_WRITE_8(pHalmac_adapter, REG_TXDMA_PQ_MAP, agg_enable);
+	HALMAC_REG_WRITE_8(pHalmac_adapter, REG_RXDMA_AGG_PG_TH + 3, dma_usb_agg);
+	HALMAC_REG_WRITE_16(pHalmac_adapter, REG_RXDMA_AGG_PG_TH, (u16)(size | (timeout << BIT_SHIFT_DMA_AGG_TO_V1)));
+
+	PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_cfg_rx_aggregation_88xx_usb <==========\n");
+
+	return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * halmac_reg_read_8_usb_88xx() - read 1byte register
+ * @pHalmac_adapter : the adapter of halmac
+ * @halmac_offset : register offset
+ * Author : KaiYuan Chang/Ivan Lin
+ * Return : HALMAC_RET_STATUS
+ * More details of status code can be found in prototype document
+ */
+u8
+halmac_reg_read_8_usb_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN u32 halmac_offset
+)
+{
+	u8 value8;
+	VOID *pDriver_adapter = NULL;
+	PHALMAC_API pHalmac_api;
+
+	if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter))
+		return HALMAC_RET_ADAPTER_INVALID;
+
+	if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter))
+		return HALMAC_RET_API_INVALID;
+
+	pDriver_adapter = pHalmac_adapter->pDriver_adapter;
+	pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api;
+
+	/* PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_reg_read_8_usb_88xx ==========>\n"); */
+
+	value8 = PLATFORM_REG_READ_8(pDriver_adapter, halmac_offset);
+
+	/* PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_reg_read_8_usb_88xx <==========\n"); */
+
+	return value8;
+}
+
+/**
+ * halmac_reg_write_8_usb_88xx() - write 1byte register
+ * @pHalmac_adapter : the adapter of halmac
+ * @halmac_offset : register offset
+ * @halmac_data : register value
+ * Author : KaiYuan Chang/Ivan Lin
+ * Return : HALMAC_RET_STATUS
+ * More details of status code can be found in prototype document
+ */
+HALMAC_RET_STATUS
+halmac_reg_write_8_usb_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN u32 halmac_offset,
+	IN u8 halmac_data
+)
+{
+	VOID *pDriver_adapter = NULL;
+	PHALMAC_API pHalmac_api;
+
+	if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter))
+		return HALMAC_RET_ADAPTER_INVALID;
+
+	if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter))
+		return HALMAC_RET_API_INVALID;
+
+	pDriver_adapter = pHalmac_adapter->pDriver_adapter;
+	pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api;
+
+
+	/* PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_reg_write_8_usb_88xx ==========>\n"); */
+
+	PLATFORM_REG_WRITE_8(pDriver_adapter, halmac_offset, halmac_data);
+
+	/* PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_reg_write_8_usb_88xx <==========\n"); */
+
+	return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * halmac_reg_read_16_usb_88xx() - read 2byte register
+ * @pHalmac_adapter : the adapter of halmac
+ * @halmac_offset : register offset
+ * Author : KaiYuan Chang/Ivan Lin
+ * Return : HALMAC_RET_STATUS
+ * More details of status code can be found in prototype document
+ */
+u16
+halmac_reg_read_16_usb_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN u32 halmac_offset
+)
+{
+	VOID *pDriver_adapter = NULL;
+	PHALMAC_API pHalmac_api;
+
+	union {
+		u16	word;
+		u8	byte[2];
+	} value16 = { 0x0000 };
+
+	if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter))
+		return HALMAC_RET_ADAPTER_INVALID;
+
+	if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter))
+		return HALMAC_RET_API_INVALID;
+
+	pDriver_adapter = pHalmac_adapter->pDriver_adapter;
+	pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api;
+
+	/* PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_reg_read_16_usb_88xx ==========>\n"); */
+
+	value16.word = PLATFORM_REG_READ_16(pDriver_adapter, halmac_offset);
+
+	/* PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_reg_read_16_usb_88xx <==========\n"); */
+
+	return value16.word;
+}
+
+/**
+ * halmac_reg_write_16_usb_88xx() - write 2byte register
+ * @pHalmac_adapter : the adapter of halmac
+ * @halmac_offset : register offset
+ * @halmac_data : register value
+ * Author : KaiYuan Chang/Ivan Lin
+ * Return : HALMAC_RET_STATUS
+ * More details of status code can be found in prototype document
+ */
+HALMAC_RET_STATUS
+halmac_reg_write_16_usb_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN u32 halmac_offset,
+	IN u16 halmac_data
+)
+{
+	VOID *pDriver_adapter = NULL;
+	PHALMAC_API pHalmac_api;
+
+	if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter))
+		return HALMAC_RET_ADAPTER_INVALID;
+
+	if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter))
+		return HALMAC_RET_API_INVALID;
+
+	pDriver_adapter = pHalmac_adapter->pDriver_adapter;
+	pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api;
+
+	/* PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_reg_write_16_usb_88xx ==========>\n"); */
+
+	PLATFORM_REG_WRITE_16(pDriver_adapter, halmac_offset, halmac_data);
+
+	/* PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_reg_write_16_usb_88xx <==========\n"); */
+
+	return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * halmac_reg_read_32_usb_88xx() - read 4byte register
+ * @pHalmac_adapter : the adapter of halmac
+ * @halmac_offset : register offset
+ * Author : KaiYuan Chang/Ivan Lin
+ * Return : HALMAC_RET_STATUS
+ * More details of status code can be found in prototype document
+ */
+u32
+halmac_reg_read_32_usb_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN u32 halmac_offset
+)
+{
+	VOID *pDriver_adapter = NULL;
+	PHALMAC_API pHalmac_api;
+
+	union {
+		u32	dword;
+		u8	byte[4];
+	} value32 = { 0x00000000 };
+
+	if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter))
+		return HALMAC_RET_ADAPTER_INVALID;
+
+	if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter))
+		return HALMAC_RET_API_INVALID;
+
+	pDriver_adapter = pHalmac_adapter->pDriver_adapter;
+	pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api;
+
+	/* PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_reg_read_32_usb_88xx ==========>\n"); */
+
+	value32.dword = PLATFORM_REG_READ_32(pDriver_adapter, halmac_offset);
+
+	/* PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_reg_read_32_usb_88xx <==========\n"); */
+
+	return value32.dword;
+}
+
+/**
+ * halmac_reg_write_32_usb_88xx() - write 4byte register
+ * @pHalmac_adapter : the adapter of halmac
+ * @halmac_offset : register offset
+ * @halmac_data : register value
+ * Author : KaiYuan Chang/Ivan Lin
+ * Return : HALMAC_RET_STATUS
+ * More details of status code can be found in prototype document
+ */
+HALMAC_RET_STATUS
+halmac_reg_write_32_usb_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN u32 halmac_offset,
+	IN u32 halmac_data
+)
+{
+	VOID *pDriver_adapter = NULL;
+	PHALMAC_API pHalmac_api;
+
+	if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter))
+		return HALMAC_RET_ADAPTER_INVALID;
+
+	if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter))
+		return HALMAC_RET_API_INVALID;
+
+	pDriver_adapter = pHalmac_adapter->pDriver_adapter;
+	pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api;
+
+	/* PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_reg_write_32_usb_88xx ==========>\n"); */
+
+	PLATFORM_REG_WRITE_32(pDriver_adapter, halmac_offset, halmac_data);
+
+	/* PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_reg_write_32_usb_88xx <==========\n"); */
+
+	return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * halmac_set_bulkout_num_usb_88xx() - inform bulk-out num
+ * @pHalmac_adapter : the adapter of halmac
+ * @bulkout_num : usb bulk-out number
+ * Author : KaiYuan Chang
+ * Return : HALMAC_RET_STATUS
+ * More details of status code can be found in prototype document
+ */
+HALMAC_RET_STATUS
+halmac_set_bulkout_num_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN u8 bulkout_num
+)
+{
+	VOID *pDriver_adapter = NULL;
+	PHALMAC_API pHalmac_api;
+
+	if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter))
+		return HALMAC_RET_ADAPTER_INVALID;
+
+	if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter))
+		return HALMAC_RET_API_INVALID;
+
+	halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_SET_BULKOUT_NUM);
+
+	pDriver_adapter = pHalmac_adapter->pDriver_adapter;
+	pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api;
+
+	/* PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE,"halmac_set_bulkout_num_88xx ==========>\n"); */
+	/* PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE,"bulkout_num = %d\n", bulkout_num); */
+
+	pHalmac_adapter->halmac_bulkout_num = bulkout_num;
+
+	/* PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE,"halmac_set_bulkout_num_88xx <==========\n"); */
+
+	return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * halmac_get_usb_bulkout_id_usb_88xx() - get bulk out id for the TX packet
+ * @pHalmac_adapter : the adapter of halmac
+ * @halmac_buf : tx packet, include txdesc
+ * @halmac_size : tx packet size
+ * @bulkout_id : usb bulk-out id
+ * Author : KaiYuan Chang
+ * Return : HALMAC_RET_STATUS
+ * More details of status code can be found in prototype document
+ */
+HALMAC_RET_STATUS
+halmac_get_usb_bulkout_id_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN u8 *halmac_buf,
+	IN u32 halmac_size,
+	OUT u8 *bulkout_id
+)
+{
+	VOID *pDriver_adapter = NULL;
+	PHALMAC_API pHalmac_api;
+	HALMAC_QUEUE_SELECT queue_sel;
+	HALMAC_DMA_MAPPING dma_mapping;
+
+	if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter))
+		return HALMAC_RET_ADAPTER_INVALID;
+
+	if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter))
+		return HALMAC_RET_API_INVALID;
+
+	halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_GET_USB_BULKOUT_ID);
+
+	pDriver_adapter = pHalmac_adapter->pDriver_adapter;
+	pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api;
+
+	PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_get_usb_bulkout_id_88xx ==========>\n");
+
+	if (NULL == halmac_buf) {
+		PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "halmac_buf is NULL!!\n");
+		return HALMAC_RET_DATA_BUF_NULL;
+	}
+
+	if (0 == halmac_size) {
+		PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "halmac_size is 0!!\n");
+		return HALMAC_RET_DATA_SIZE_INCORRECT;
+	}
+
+	queue_sel = (HALMAC_QUEUE_SELECT)GET_TX_DESC_QSEL(halmac_buf);
+
+	switch (queue_sel) {
+	case HALMAC_QUEUE_SELECT_VO:
+	case HALMAC_QUEUE_SELECT_VO_V2:
+		dma_mapping = pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_VO];
+		break;
+	case HALMAC_QUEUE_SELECT_VI:
+	case HALMAC_QUEUE_SELECT_VI_V2:
+		dma_mapping = pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_VI];
+		break;
+	case HALMAC_QUEUE_SELECT_BE:
+	case HALMAC_QUEUE_SELECT_BE_V2:
+		dma_mapping = pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_BE];
+		break;
+	case HALMAC_QUEUE_SELECT_BK:
+	case HALMAC_QUEUE_SELECT_BK_V2:
+		dma_mapping = pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_BK];
+		break;
+	case HALMAC_QUEUE_SELECT_MGNT:
+		dma_mapping = pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_MG];
+		break;
+	case HALMAC_QUEUE_SELECT_HIGH:
+	case HALMAC_QUEUE_SELECT_BCN:
+	case HALMAC_QUEUE_SELECT_CMD:
+		dma_mapping = HALMAC_DMA_MAPPING_HIGH;
+		break;
+	default:
+		PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "Qsel is out of range\n");
+		return HALMAC_RET_QSEL_INCORRECT;
+	}
+
+	switch (dma_mapping) {
+	case HALMAC_DMA_MAPPING_HIGH:
+		*bulkout_id = 0;
+		break;
+	case HALMAC_DMA_MAPPING_NORMAL:
+		*bulkout_id = 1;
+		break;
+	case HALMAC_DMA_MAPPING_LOW:
+		*bulkout_id = 2;
+		break;
+	case HALMAC_DMA_MAPPING_EXTRA:
+		*bulkout_id = 3;
+		break;
+	default:
+		PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "DmaMapping is out of range\n");
+		return HALMAC_RET_DMA_MAP_INCORRECT;
+	}
+
+	PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_get_usb_bulkout_id_88xx <==========\n");
+
+	return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * halmac_cfg_tx_agg_align_usb_88xx() -config sdio bus tx agg alignment
+ * @pHalmac_adapter : the adapter of halmac
+ * @enable : function enable(1)/disable(0)
+ * @align_size : sdio bus tx agg alignment size (2^n, n = 3~11)
+ * Author : Soar Tu
+ * Return : HALMAC_RET_STATUS
+ * More details of status code can be found in prototype document
+ */
+HALMAC_RET_STATUS
+halmac_cfg_tx_agg_align_usb_not_support_88xx(
+	IN PHALMAC_ADAPTER	pHalmac_adapter,
+	IN u8	enable,
+	IN u16	align_size
+)
+{
+	PHALMAC_API pHalmac_api;
+	VOID *pDriver_adapter = NULL;
+
+	if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter))
+		return HALMAC_RET_ADAPTER_INVALID;
+
+	if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter))
+		return HALMAC_RET_API_INVALID;
+
+	halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_CFG_TX_AGG_ALIGN);
+
+	pDriver_adapter = pHalmac_adapter->pDriver_adapter;
+	pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api;
+
+
+	PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_cfg_tx_agg_align_usb_not_support_88xx ==========>\n");
+
+	PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_cfg_tx_agg_align_usb_not_support_88xx not support\n");
+	PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_cfg_tx_agg_align_usb_not_support_88xx <==========\n");
+
+	return HALMAC_RET_SUCCESS;
+}
+
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/halmac/halmac_88xx/halmac_api_88xx_usb.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/halmac/halmac_88xx/halmac_api_88xx_usb.h
--- linux-5.6.3/3rdparty/rtl8821ce/hal/halmac/halmac_88xx/halmac_api_88xx_usb.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/halmac/halmac_88xx/halmac_api_88xx_usb.h	2020-04-10 16:35:06.792658947 +0300
@@ -0,0 +1,83 @@
+#ifndef _HALMAC_API_88XX_USB_H_
+#define _HALMAC_API_88XX_USB_H_
+
+#include "../halmac_2_platform.h"
+#include "../halmac_type.h"
+
+HALMAC_RET_STATUS
+halmac_init_usb_cfg_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter
+);
+
+HALMAC_RET_STATUS
+halmac_deinit_usb_cfg_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter
+);
+
+HALMAC_RET_STATUS
+halmac_cfg_rx_aggregation_88xx_usb(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN PHALMAC_RXAGG_CFG phalmac_rxagg_cfg
+);
+
+u8
+halmac_reg_read_8_usb_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN u32 halmac_offset
+);
+
+HALMAC_RET_STATUS
+halmac_reg_write_8_usb_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN u32 halmac_offset,
+	IN u8 halmac_data
+);
+
+u16
+halmac_reg_read_16_usb_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN u32 halmac_offset
+);
+
+HALMAC_RET_STATUS
+halmac_reg_write_16_usb_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN u32 halmac_offset,
+	IN u16 halmac_data
+);
+
+u32
+halmac_reg_read_32_usb_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN u32 halmac_offset
+);
+
+HALMAC_RET_STATUS
+halmac_reg_write_32_usb_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN u32 halmac_offset,
+	IN u32 halmac_data
+);
+
+HALMAC_RET_STATUS
+halmac_set_bulkout_num_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN u8 bulkout_num
+);
+
+HALMAC_RET_STATUS
+halmac_get_usb_bulkout_id_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN u8 *halmac_buf,
+	IN u32 halmac_size,
+	OUT u8 *bulkout_id
+);
+
+HALMAC_RET_STATUS
+halmac_cfg_tx_agg_align_usb_not_support_88xx(
+	IN PHALMAC_ADAPTER	pHalmac_adapter,
+	IN u8	enable,
+	IN u16	align_size
+);
+
+#endif/* _HALMAC_API_88XX_USB_H_ */
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/halmac/halmac_88xx/halmac_bb_rf_88xx.c linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/halmac/halmac_88xx/halmac_bb_rf_88xx.c
--- linux-5.6.3/3rdparty/rtl8821ce/hal/halmac/halmac_88xx/halmac_bb_rf_88xx.c	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/halmac/halmac_88xx/halmac_bb_rf_88xx.c	2020-04-10 16:35:06.792658947 +0300
@@ -0,0 +1,395 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ ******************************************************************************/
+
+#include "halmac_bb_rf_88xx.h"
+#include "halmac_88xx_cfg.h"
+#include "halmac_common_88xx.h"
+#include "halmac_init_88xx.h"
+
+#if HALMAC_88XX_SUPPORT
+
+/**
+ * start_iqk_88xx() -trigger FW IQK
+ * @adapter : the adapter of halmac
+ * @param : IQK parameter
+ * Author : KaiYuan Chang/Ivan Lin
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+start_iqk_88xx(struct halmac_adapter *adapter, struct halmac_iqk_para *param)
+{
+	u8 h2c_buf[H2C_PKT_SIZE_88XX] = { 0 };
+	u16 seq_num = 0;
+	enum halmac_ret_status status = HALMAC_RET_SUCCESS;
+	struct halmac_h2c_header_info hdr_info;
+	enum halmac_cmd_process_status *proc_status;
+
+	proc_status = &adapter->halmac_state.iqk_state.proc_status;
+
+	if (halmac_fw_validate(adapter) != HALMAC_RET_SUCCESS)
+		return HALMAC_RET_NO_DLFW;
+
+	PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
+
+	if (*proc_status == HALMAC_CMD_PROCESS_SENDING) {
+		PLTFM_MSG_TRACE("[TRACE]Wait event(iqk)\n");
+		return HALMAC_RET_BUSY_STATE;
+	}
+
+	*proc_status = HALMAC_CMD_PROCESS_SENDING;
+
+	IQK_SET_CLEAR(h2c_buf, param->clear);
+	IQK_SET_SEGMENT_IQK(h2c_buf, param->segment_iqk);
+
+	hdr_info.sub_cmd_id = SUB_CMD_ID_IQK;
+	hdr_info.content_size = 1;
+	hdr_info.ack = 1;
+	set_h2c_pkt_hdr_88xx(adapter, h2c_buf, &hdr_info, &seq_num);
+
+	adapter->halmac_state.iqk_state.seq_num = seq_num;
+
+	status = send_h2c_pkt_88xx(adapter, h2c_buf);
+
+	if (status != HALMAC_RET_SUCCESS) {
+		PLTFM_MSG_ERR("[ERR]send h2c pkt fail!!\n");
+		reset_ofld_feature_88xx(adapter, HALMAC_FEATURE_IQK);
+		return status;
+	}
+
+	PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
+
+	return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * ctrl_pwr_tracking_88xx() -trigger FW power tracking
+ * @adapter : the adapter of halmac
+ * @opt : power tracking option
+ * Author : KaiYuan Chang/Ivan Lin
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+ctrl_pwr_tracking_88xx(struct halmac_adapter *adapter,
+		       struct halmac_pwr_tracking_option *opt)
+{
+	u8 h2c_buf[H2C_PKT_SIZE_88XX] = { 0 };
+	u16 seq_num = 0;
+	enum halmac_ret_status status = HALMAC_RET_SUCCESS;
+	struct halmac_h2c_header_info hdr_info;
+	struct halmac_pwr_tracking_para *param;
+	enum halmac_cmd_process_status *proc_status;
+
+	proc_status = &adapter->halmac_state.pwr_trk_state.proc_status;
+
+	if (halmac_fw_validate(adapter) != HALMAC_RET_SUCCESS)
+		return HALMAC_RET_NO_DLFW;
+
+	PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
+
+	if (*proc_status == HALMAC_CMD_PROCESS_SENDING) {
+		PLTFM_MSG_TRACE("[TRACE]Wait event(pwr tracking)...\n");
+		return HALMAC_RET_BUSY_STATE;
+	}
+
+	*proc_status = HALMAC_CMD_PROCESS_SENDING;
+
+	PWR_TRK_SET_TYPE(h2c_buf, opt->type);
+	PWR_TRK_SET_BBSWING_INDEX(h2c_buf, opt->bbswing_index);
+
+	param = &opt->pwr_tracking_para[HALMAC_RF_PATH_A];
+	PWR_TRK_SET_ENABLE_A(h2c_buf, param->enable);
+	PWR_TRK_SET_TX_PWR_INDEX_A(h2c_buf, param->tx_pwr_index);
+	PWR_TRK_SET_TSSI_VALUE_A(h2c_buf, param->tssi_value);
+	PWR_TRK_SET_OFFSET_VALUE_A(h2c_buf, param->pwr_tracking_offset_value);
+
+	param = &opt->pwr_tracking_para[HALMAC_RF_PATH_B];
+	PWR_TRK_SET_ENABLE_B(h2c_buf, param->enable);
+	PWR_TRK_SET_TX_PWR_INDEX_B(h2c_buf, param->tx_pwr_index);
+	PWR_TRK_SET_TSSI_VALUE_B(h2c_buf, param->tssi_value);
+	PWR_TRK_SET_OFFSET_VALUE_B(h2c_buf, param->pwr_tracking_offset_value);
+
+	param = &opt->pwr_tracking_para[HALMAC_RF_PATH_C];
+	PWR_TRK_SET_ENABLE_C(h2c_buf, param->enable);
+	PWR_TRK_SET_TX_PWR_INDEX_C(h2c_buf, param->tx_pwr_index);
+	PWR_TRK_SET_TSSI_VALUE_C(h2c_buf, param->tssi_value);
+	PWR_TRK_SET_OFFSET_VALUE_C(h2c_buf, param->pwr_tracking_offset_value);
+
+	param = &opt->pwr_tracking_para[HALMAC_RF_PATH_D];
+	PWR_TRK_SET_ENABLE_D(h2c_buf, param->enable);
+	PWR_TRK_SET_TX_PWR_INDEX_D(h2c_buf, param->tx_pwr_index);
+	PWR_TRK_SET_TSSI_VALUE_D(h2c_buf, param->tssi_value);
+	PWR_TRK_SET_OFFSET_VALUE_D(h2c_buf, param->pwr_tracking_offset_value);
+
+	hdr_info.sub_cmd_id = SUB_CMD_ID_PWR_TRK;
+	hdr_info.content_size = 20;
+	hdr_info.ack = 1;
+	set_h2c_pkt_hdr_88xx(adapter, h2c_buf, &hdr_info, &seq_num);
+
+	adapter->halmac_state.pwr_trk_state.seq_num = seq_num;
+
+	status = send_h2c_pkt_88xx(adapter, h2c_buf);
+
+	if (status != HALMAC_RET_SUCCESS) {
+		PLTFM_MSG_ERR("[ERR]send h2c pkt fail!!\n");
+		reset_ofld_feature_88xx(adapter, HALMAC_FEATURE_POWER_TRACKING);
+		return status;
+	}
+
+	PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
+
+	return HALMAC_RET_SUCCESS;
+}
+
+enum halmac_ret_status
+get_iqk_status_88xx(struct halmac_adapter *adapter,
+		    enum halmac_cmd_process_status *proc_status)
+{
+	*proc_status = adapter->halmac_state.iqk_state.proc_status;
+
+	return HALMAC_RET_SUCCESS;
+}
+
+enum halmac_ret_status
+get_pwr_trk_status_88xx(struct halmac_adapter *adapter,
+			enum halmac_cmd_process_status *proc_status)
+{
+	*proc_status = adapter->halmac_state.pwr_trk_state.proc_status;
+
+	return HALMAC_RET_SUCCESS;
+}
+
+enum halmac_ret_status
+get_psd_status_88xx(struct halmac_adapter *adapter,
+		    enum halmac_cmd_process_status *proc_status, u8 *data,
+		    u32 *size)
+{
+	struct halmac_psd_state *state = &adapter->halmac_state.psd_state;
+
+	*proc_status = state->proc_status;
+
+	if (!data)
+		return HALMAC_RET_NULL_POINTER;
+
+	if (!size)
+		return HALMAC_RET_NULL_POINTER;
+
+	if (*proc_status == HALMAC_CMD_PROCESS_DONE) {
+		if (*size < state->data_size) {
+			*size = state->data_size;
+			return HALMAC_RET_BUFFER_TOO_SMALL;
+		}
+
+		*size = state->data_size;
+		PLTFM_MEMCPY(data, state->data, *size);
+	}
+
+	return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * psd_88xx() - trigger fw psd
+ * @adapter : the adapter of halmac
+ * @start_psd : start PSD
+ * @end_psd : end PSD
+ * Author : KaiYuan Chang/Ivan Lin
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+psd_88xx(struct halmac_adapter *adapter, u16 start_psd, u16 end_psd)
+{
+	u8 h2c_buf[H2C_PKT_SIZE_88XX] = { 0 };
+	u16 seq_num = 0;
+	enum halmac_ret_status status = HALMAC_RET_SUCCESS;
+	struct halmac_h2c_header_info hdr_info;
+	enum halmac_cmd_process_status *proc_status;
+
+	proc_status = &adapter->halmac_state.psd_state.proc_status;
+
+	if (halmac_fw_validate(adapter) != HALMAC_RET_SUCCESS)
+		return HALMAC_RET_NO_DLFW;
+
+	PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
+
+	if (*proc_status == HALMAC_CMD_PROCESS_SENDING) {
+		PLTFM_MSG_TRACE("[TRACE]Wait event(psd)\n");
+		return HALMAC_RET_BUSY_STATE;
+	}
+
+	if (adapter->halmac_state.psd_state.data) {
+		PLTFM_FREE(adapter->halmac_state.psd_state.data,
+			   adapter->halmac_state.psd_state.data_size);
+		adapter->halmac_state.psd_state.data = (u8 *)NULL;
+	}
+
+	adapter->halmac_state.psd_state.data_size = 0;
+	adapter->halmac_state.psd_state.seg_size = 0;
+
+	*proc_status = HALMAC_CMD_PROCESS_SENDING;
+
+	PSD_SET_START_PSD(h2c_buf, start_psd);
+	PSD_SET_END_PSD(h2c_buf, end_psd);
+
+	hdr_info.sub_cmd_id = SUB_CMD_ID_PSD;
+	hdr_info.content_size = 4;
+	hdr_info.ack = 1;
+	set_h2c_pkt_hdr_88xx(adapter, h2c_buf, &hdr_info, &seq_num);
+
+	status = send_h2c_pkt_88xx(adapter, h2c_buf);
+
+	if (status != HALMAC_RET_SUCCESS) {
+		PLTFM_MSG_ERR("[ERR]send h2c pkt fail!!\n");
+		reset_ofld_feature_88xx(adapter, HALMAC_FEATURE_PSD);
+		return status;
+	}
+
+	PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
+
+	return HALMAC_RET_SUCCESS;
+}
+
+enum halmac_ret_status
+get_h2c_ack_iqk_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size)
+{
+	u8 seq_num;
+	u8 fw_rc;
+	struct halmac_iqk_state *state = &adapter->halmac_state.iqk_state;
+	enum halmac_cmd_process_status proc_status;
+
+	seq_num = (u8)H2C_ACK_HDR_GET_H2C_SEQ(buf);
+	PLTFM_MSG_TRACE("[TRACE]Seq num : h2c->%d c2h->%d\n",
+			state->seq_num, seq_num);
+	if (seq_num != state->seq_num) {
+		PLTFM_MSG_ERR("[ERR]Seq num mismatch : h2c->%d c2h->%d\n",
+			      state->seq_num, seq_num);
+		return HALMAC_RET_SUCCESS;
+	}
+
+	if (state->proc_status != HALMAC_CMD_PROCESS_SENDING) {
+		PLTFM_MSG_ERR("[ERR]not cmd sending\n");
+		return HALMAC_RET_SUCCESS;
+	}
+
+	fw_rc = (u8)H2C_ACK_HDR_GET_H2C_RETURN_CODE(buf);
+	state->fw_rc = fw_rc;
+
+	if ((enum halmac_h2c_return_code)fw_rc == HALMAC_H2C_RETURN_SUCCESS) {
+		proc_status = HALMAC_CMD_PROCESS_DONE;
+		state->proc_status = proc_status;
+		PLTFM_EVENT_SIG(HALMAC_FEATURE_IQK, proc_status, NULL, 0);
+	} else {
+		proc_status = HALMAC_CMD_PROCESS_ERROR;
+		state->proc_status = proc_status;
+		PLTFM_EVENT_SIG(HALMAC_FEATURE_IQK, proc_status, &fw_rc, 1);
+	}
+
+	return HALMAC_RET_SUCCESS;
+}
+
+enum halmac_ret_status
+get_h2c_ack_pwr_trk_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size)
+{
+	u8 seq_num;
+	u8 fw_rc;
+	struct halmac_pwr_tracking_state *state;
+	enum halmac_cmd_process_status proc_status;
+
+	state = &adapter->halmac_state.pwr_trk_state;
+
+	seq_num = (u8)H2C_ACK_HDR_GET_H2C_SEQ(buf);
+	PLTFM_MSG_TRACE("[TRACE]Seq num : h2c->%d c2h->%d\n",
+			state->seq_num, seq_num);
+	if (seq_num != state->seq_num) {
+		PLTFM_MSG_ERR("[ERR]Seq num mismatch : h2c->%d c2h->%d\n",
+			      state->seq_num, seq_num);
+		return HALMAC_RET_SUCCESS;
+	}
+
+	if (state->proc_status != HALMAC_CMD_PROCESS_SENDING) {
+		PLTFM_MSG_ERR("[ERR]not cmd sending\n");
+		return HALMAC_RET_SUCCESS;
+	}
+
+	fw_rc = (u8)H2C_ACK_HDR_GET_H2C_RETURN_CODE(buf);
+	state->fw_rc = fw_rc;
+
+	if ((enum halmac_h2c_return_code)fw_rc == HALMAC_H2C_RETURN_SUCCESS) {
+		proc_status = HALMAC_CMD_PROCESS_DONE;
+		state->proc_status = proc_status;
+		PLTFM_EVENT_SIG(HALMAC_FEATURE_POWER_TRACKING, proc_status,
+				NULL, 0);
+	} else {
+		proc_status = HALMAC_CMD_PROCESS_ERROR;
+		state->proc_status = proc_status;
+		PLTFM_EVENT_SIG(HALMAC_FEATURE_POWER_TRACKING, proc_status,
+				&fw_rc, 1);
+	}
+
+	return HALMAC_RET_SUCCESS;
+}
+
+enum halmac_ret_status
+get_psd_data_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size)
+{
+	u8 seg_id;
+	u8 seg_size;
+	u8 seq_num;
+	u16 total_size;
+	enum halmac_cmd_process_status proc_status;
+	struct halmac_psd_state *state = &adapter->halmac_state.psd_state;
+
+	seq_num = (u8)PSD_DATA_GET_H2C_SEQ(buf);
+	PLTFM_MSG_TRACE("[TRACE]seq num : h2c->%d c2h->%d\n",
+			state->seq_num, seq_num);
+	if (seq_num != state->seq_num) {
+		PLTFM_MSG_ERR("[ERR]seq num mismatch : h2c->%d c2h->%d\n",
+			      state->seq_num, seq_num);
+		return HALMAC_RET_SUCCESS;
+	}
+
+	if (state->proc_status != HALMAC_CMD_PROCESS_SENDING) {
+		PLTFM_MSG_ERR("[ERR]not cmd sending\n");
+		return HALMAC_RET_SUCCESS;
+	}
+
+	total_size = (u16)PSD_DATA_GET_TOTAL_SIZE(buf);
+	seg_id = (u8)PSD_DATA_GET_SEGMENT_ID(buf);
+	seg_size = (u8)PSD_DATA_GET_SEGMENT_SIZE(buf);
+	state->data_size = total_size;
+
+	if (!state->data)
+		state->data = (u8 *)PLTFM_MALLOC(state->data_size);
+
+	if (seg_id == 0)
+		state->seg_size = seg_size;
+
+	PLTFM_MEMCPY(state->data + seg_id * state->seg_size,
+		     buf + C2H_DATA_OFFSET_88XX, seg_size);
+
+	if (PSD_DATA_GET_END_SEGMENT(buf) == 0)
+		return HALMAC_RET_SUCCESS;
+
+	proc_status = HALMAC_CMD_PROCESS_DONE;
+	state->proc_status = proc_status;
+
+	PLTFM_EVENT_SIG(HALMAC_FEATURE_PSD, proc_status, state->data,
+			state->data_size);
+
+	return HALMAC_RET_SUCCESS;
+}
+
+#endif /* HALMAC_88XX_SUPPORT */
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/halmac/halmac_88xx/halmac_bb_rf_88xx.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/halmac/halmac_88xx/halmac_bb_rf_88xx.h
--- linux-5.6.3/3rdparty/rtl8821ce/hal/halmac/halmac_88xx/halmac_bb_rf_88xx.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/halmac/halmac_88xx/halmac_bb_rf_88xx.h	2020-04-10 16:35:06.792658947 +0300
@@ -0,0 +1,57 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ ******************************************************************************/
+
+#ifndef _HALMAC_BB_RF_88XX_H_
+#define _HALMAC_BB_RF_88XX_H_
+
+#include "../halmac_api.h"
+
+#if HALMAC_88XX_SUPPORT
+
+enum halmac_ret_status
+start_iqk_88xx(struct halmac_adapter *adapter, struct halmac_iqk_para *param);
+
+enum halmac_ret_status
+ctrl_pwr_tracking_88xx(struct halmac_adapter *adapter,
+		       struct halmac_pwr_tracking_option *opt);
+
+enum halmac_ret_status
+get_iqk_status_88xx(struct halmac_adapter *adapter,
+		    enum halmac_cmd_process_status *proc_status);
+
+enum halmac_ret_status
+get_pwr_trk_status_88xx(struct halmac_adapter *adapter,
+			enum halmac_cmd_process_status *proc_status);
+
+enum halmac_ret_status
+get_psd_status_88xx(struct halmac_adapter *adapter,
+		    enum halmac_cmd_process_status *proc_status, u8 *data,
+		    u32 *size);
+
+enum halmac_ret_status
+psd_88xx(struct halmac_adapter *adapter, u16 start_psd, u16 end_psd);
+
+enum halmac_ret_status
+get_h2c_ack_iqk_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size);
+
+enum halmac_ret_status
+get_h2c_ack_pwr_trk_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size);
+
+enum halmac_ret_status
+get_psd_data_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size);
+
+#endif /* HALMAC_88XX_SUPPORT */
+
+#endif/* _HALMAC_BB_RF_88XX_H_ */
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/halmac/halmac_88xx/halmac_cfg_wmac_88xx.c linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/halmac/halmac_88xx/halmac_cfg_wmac_88xx.c
--- linux-5.6.3/3rdparty/rtl8821ce/hal/halmac/halmac_88xx/halmac_cfg_wmac_88xx.c	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/halmac/halmac_88xx/halmac_cfg_wmac_88xx.c	2020-04-10 16:35:06.792658947 +0300
@@ -0,0 +1,1133 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ ******************************************************************************/
+
+#include "halmac_cfg_wmac_88xx.h"
+#include "halmac_88xx_cfg.h"
+
+#if HALMAC_88XX_SUPPORT
+
+#define MAC_CLK_SPEED	80 /* 80M */
+
+enum mac_clock_hw_def {
+	MAC_CLK_HW_DEF_80M = 0,
+	MAC_CLK_HW_DEF_40M = 1,
+	MAC_CLK_HW_DEF_20M = 2,
+};
+
+/**
+ * cfg_mac_addr_88xx() - config mac address
+ * @adapter : the adapter of halmac
+ * @port : 0 for port0, 1 for port1, 2 for port2, 3 for port3, 4 for port4
+ * @addr : mac address
+ * Author : KaiYuan Chang/Ivan Lin
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+cfg_mac_addr_88xx(struct halmac_adapter *adapter, u8 port,
+		  union halmac_wlan_addr *addr)
+{
+	u32 offset;
+	struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
+
+	PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
+
+	if (port >= HALMAC_PORTID_NUM) {
+		PLTFM_MSG_ERR("[ERR]port index >= 5\n");
+		return HALMAC_RET_PORT_NOT_SUPPORT;
+	}
+
+	switch (port) {
+	case HALMAC_PORTID0:
+		offset = REG_MACID;
+		break;
+	case HALMAC_PORTID1:
+		offset = REG_MACID1;
+		break;
+	case HALMAC_PORTID2:
+		offset = REG_MACID2;
+		break;
+	case HALMAC_PORTID3:
+		offset = REG_MACID3;
+		break;
+	case HALMAC_PORTID4:
+		offset = REG_MACID4;
+		break;
+	default:
+		return HALMAC_RET_PORT_NOT_SUPPORT;
+	}
+
+	HALMAC_REG_W32(offset, rtk_le32_to_cpu(addr->addr_l_h.low));
+	HALMAC_REG_W16(offset + 4, rtk_le16_to_cpu(addr->addr_l_h.high));
+
+	PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
+
+	return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * cfg_bssid_88xx() - config BSSID
+ * @adapter : the adapter of halmac
+ * @port : 0 for port0, 1 for port1, 2 for port2, 3 for port3, 4 for port4
+ * @addr : bssid
+ * Author : KaiYuan Chang/Ivan Lin
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+cfg_bssid_88xx(struct halmac_adapter *adapter, u8 port,
+	       union halmac_wlan_addr *addr)
+{
+	u32 offset;
+	struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
+
+	PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
+
+	if (port >= HALMAC_PORTID_NUM) {
+		PLTFM_MSG_ERR("[ERR]port index > 5\n");
+		return HALMAC_RET_PORT_NOT_SUPPORT;
+	}
+
+	switch (port) {
+	case HALMAC_PORTID0:
+		offset = REG_BSSID;
+		break;
+	case HALMAC_PORTID1:
+		offset = REG_BSSID1;
+		break;
+	case HALMAC_PORTID2:
+		offset = REG_BSSID2;
+		break;
+	case HALMAC_PORTID3:
+		offset = REG_BSSID3;
+		break;
+	case HALMAC_PORTID4:
+		offset = REG_BSSID4;
+		break;
+	default:
+		return HALMAC_RET_PORT_NOT_SUPPORT;
+	}
+
+	HALMAC_REG_W32(offset, rtk_le32_to_cpu(addr->addr_l_h.low));
+	HALMAC_REG_W16(offset + 4, rtk_le16_to_cpu(addr->addr_l_h.high));
+
+	PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
+
+	return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * cfg_transmitter_addr_88xx() - config transmitter address
+ * @adapter : the adapter of halmac
+ * @port :  0 for port0, 1 for port1, 2 for port2, 3 for port3, 4 for port4
+ * @addr :
+ * Author : Alan
+ * Return : enum halmac_ret_status
+ */
+enum halmac_ret_status
+cfg_transmitter_addr_88xx(struct halmac_adapter *adapter, u8 port,
+			  union halmac_wlan_addr *addr)
+{
+	u32 offset;
+	struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
+
+	PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
+
+	if (port >= HALMAC_PORTID_NUM) {
+		PLTFM_MSG_ERR("[ERR]port index > 5\n");
+		return HALMAC_RET_PORT_NOT_SUPPORT;
+	}
+
+	switch (port) {
+	case HALMAC_PORTID0:
+		offset = REG_TRANSMIT_ADDRSS_0;
+		break;
+	case HALMAC_PORTID1:
+		offset = REG_TRANSMIT_ADDRSS_1;
+		break;
+	case HALMAC_PORTID2:
+		offset = REG_TRANSMIT_ADDRSS_2;
+		break;
+	case HALMAC_PORTID3:
+		offset = REG_TRANSMIT_ADDRSS_3;
+		break;
+	case HALMAC_PORTID4:
+		offset = REG_TRANSMIT_ADDRSS_4;
+		break;
+	default:
+		return HALMAC_RET_PORT_NOT_SUPPORT;
+	}
+
+	HALMAC_REG_W32(offset, rtk_le32_to_cpu(addr->addr_l_h.low));
+	HALMAC_REG_W16(offset + 4, rtk_le16_to_cpu(addr->addr_l_h.high));
+
+	PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
+
+	return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * cfg_net_type_88xx() - config network type
+ * @adapter : the adapter of halmac
+ * @port :  0 for port0, 1 for port1, 2 for port2, 3 for port3, 4 for port4
+ * @addr : mac address
+ * Author : Alan
+ * Return : enum halmac_ret_status
+ */
+enum halmac_ret_status
+cfg_net_type_88xx(struct halmac_adapter *adapter, u8 port,
+		  enum halmac_network_type_select net_type)
+{
+	struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
+	u8 value8 = 0;
+	u8 net_type_tmp = 0;
+
+	PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
+
+	if (net_type == HALMAC_NETWORK_AP) {
+		if (port >= HALMAC_PORTID1) {
+			PLTFM_MSG_ERR("[ERR]AP port > 1\n");
+			return HALMAC_RET_PORT_NOT_SUPPORT;
+		}
+	}
+
+	switch (port) {
+	case HALMAC_PORTID0:
+		net_type_tmp = net_type;
+		value8 = ((HALMAC_REG_R8(REG_CR + 2) & 0xFC) | net_type_tmp);
+		HALMAC_REG_W8(REG_CR + 2, value8);
+		break;
+	case HALMAC_PORTID1:
+		net_type_tmp = (net_type << 2);
+		value8 = ((HALMAC_REG_R8(REG_CR + 2) & 0xF3) | net_type_tmp);
+		HALMAC_REG_W8(REG_CR + 2, value8);
+		break;
+	case HALMAC_PORTID2:
+		net_type_tmp = net_type;
+		value8 = ((HALMAC_REG_R8(REG_CR_EXT) & 0xFC) | net_type_tmp);
+		HALMAC_REG_W8(REG_CR_EXT, value8);
+		break;
+	case HALMAC_PORTID3:
+		net_type_tmp = (net_type << 2);
+		value8 = ((HALMAC_REG_R8(REG_CR_EXT) & 0xF3) | net_type_tmp);
+		HALMAC_REG_W8(REG_CR_EXT, value8);
+		break;
+	case HALMAC_PORTID4:
+		net_type_tmp = (net_type << 4);
+		value8 = ((HALMAC_REG_R8(REG_CR_EXT) & 0xCF) | net_type_tmp);
+		HALMAC_REG_W8(REG_CR_EXT, value8);
+		break;
+	default:
+		break;
+	}
+
+	PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
+
+	return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * cfg_tsf_rst_88xx() - tsf reset
+ * @adapter : the adapter of halmac
+ * @port :  0 for port0, 1 for port1, 2 for port2, 3 for port3, 4 for port4
+ * Author : Alan
+ * Return : enum halmac_ret_status
+ */
+enum halmac_ret_status
+cfg_tsf_rst_88xx(struct halmac_adapter *adapter, u8 port)
+{
+	u8 tsf_rst = 0;
+	u8 value8;
+	struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
+
+	PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
+
+	switch (port) {
+	case HALMAC_PORTID0:
+		tsf_rst = BIT_TSFTR_RST;
+		break;
+	case HALMAC_PORTID1:
+		tsf_rst = BIT_TSFTR_CLI0_RST;
+		break;
+	case HALMAC_PORTID2:
+		tsf_rst = BIT_TSFTR_CLI1_RST;
+		break;
+	case HALMAC_PORTID3:
+		tsf_rst = BIT_TSFTR_CLI2_RST;
+		break;
+	case HALMAC_PORTID4:
+		tsf_rst = BIT_TSFTR_CLI3_RST;
+		break;
+	default:
+		break;
+	}
+
+	value8 = HALMAC_REG_R8(REG_DUAL_TSF_RST);
+	HALMAC_REG_W8(REG_DUAL_TSF_RST, value8 | tsf_rst);
+
+	PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
+
+	return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * cfg_bcn_space_88xx() - config beacon space
+ * @adapter : the adapter of halmac
+ * @port :  0 for port0, 1 for port1, 2 for port2, 3 for port3, 4 for port4
+ * @bcn_space : beacon space
+ * Author : Alan
+ * Return : enum halmac_ret_status
+ */
+enum halmac_ret_status
+cfg_bcn_space_88xx(struct halmac_adapter *adapter, u8 port, u32 bcn_space)
+{
+	struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
+	u16 bcn_space_real = 0;
+	u16 value16 = 0;
+
+	PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
+
+	bcn_space_real = ((u16)bcn_space);
+
+	switch (port) {
+	case HALMAC_PORTID0:
+		HALMAC_REG_W16(REG_MBSSID_BCN_SPACE, bcn_space_real);
+		break;
+	case HALMAC_PORTID1:
+		value16 = HALMAC_REG_R16(REG_MBSSID_BCN_SPACE + 2) & 0xF000;
+		value16 |= bcn_space_real;
+		HALMAC_REG_W16(REG_MBSSID_BCN_SPACE + 2, value16);
+		break;
+	case HALMAC_PORTID2:
+		value16 = HALMAC_REG_R16(REG_MBSSID_BCN_SPACE2) & 0xF000;
+		value16 |= bcn_space_real;
+		HALMAC_REG_W16(REG_MBSSID_BCN_SPACE2, value16);
+		break;
+	case HALMAC_PORTID3:
+		value16 = HALMAC_REG_R16(REG_MBSSID_BCN_SPACE2 + 2) & 0xF000;
+		value16 |= bcn_space_real;
+		HALMAC_REG_W16(REG_MBSSID_BCN_SPACE2 + 2, value16);
+		break;
+	case HALMAC_PORTID4:
+		value16 = HALMAC_REG_R16(REG_MBSSID_BCN_SPACE3) & 0xF000;
+		value16 |= bcn_space_real;
+		HALMAC_REG_W16(REG_MBSSID_BCN_SPACE3, value16);
+		break;
+	default:
+		break;
+	}
+
+	PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
+
+	return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * rw_bcn_ctrl_88xx() - r/w beacon control
+ * @adapter : the adapter of halmac
+ * @port :  0 for port0, 1 for port1, 2 for port2, 3 for port3, 4 for port4
+ * @write_en : 1->write beacon function 0->read beacon function
+ * @pBcn_ctrl : beacon control info
+ * Author : KaiYuan Chang/Ivan Lin
+ * Return : enum halmac_ret_status
+ */
+enum halmac_ret_status
+rw_bcn_ctrl_88xx(struct halmac_adapter *adapter, u8 port, u8 write_en,
+		 struct halmac_bcn_ctrl *ctrl)
+{
+	struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
+	u8 ctrl_value = 0;
+
+	PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
+
+	if (write_en) {
+		if (ctrl->dis_rx_bssid_fit == 1)
+			ctrl_value |= BIT_DIS_RX_BSSID_FIT;
+
+		if (ctrl->en_txbcn_rpt == 1)
+			ctrl_value |= BIT_P0_EN_TXBCN_RPT;
+
+		if (ctrl->dis_tsf_udt == 1)
+			ctrl_value |= BIT_DIS_TSF_UDT;
+
+		if (ctrl->en_bcn == 1)
+			ctrl_value |= BIT_EN_BCN_FUNCTION;
+
+		if (ctrl->en_rxbcn_rpt == 1)
+			ctrl_value |= BIT_P0_EN_RXBCN_RPT;
+
+		if (ctrl->en_p2p_ctwin == 1)
+			ctrl_value |= BIT_EN_P2P_CTWINDOW;
+
+		if (ctrl->en_p2p_bcn_area == 1)
+			ctrl_value |= BIT_EN_P2P_BCNQ_AREA;
+
+		switch (port) {
+		case HALMAC_PORTID0:
+			HALMAC_REG_W8(REG_BCN_CTRL, ctrl_value);
+			break;
+		case HALMAC_PORTID1:
+			HALMAC_REG_W8(REG_BCN_CTRL_CLINT0, ctrl_value);
+			break;
+		case HALMAC_PORTID2:
+			HALMAC_REG_W8(REG_BCN_CTRL_CLINT1, ctrl_value);
+			break;
+		case HALMAC_PORTID3:
+			HALMAC_REG_W8(REG_BCN_CTRL_CLINT2, ctrl_value);
+			break;
+		case HALMAC_PORTID4:
+			HALMAC_REG_W8(REG_BCN_CTRL_CLINT3, ctrl_value);
+			break;
+		default:
+			break;
+		}
+
+	} else {
+		switch (port) {
+		case HALMAC_PORTID0:
+			ctrl_value = HALMAC_REG_R8(REG_BCN_CTRL);
+			break;
+		case HALMAC_PORTID1:
+			ctrl_value = HALMAC_REG_R8(REG_BCN_CTRL_CLINT0);
+			break;
+		case HALMAC_PORTID2:
+			ctrl_value = HALMAC_REG_R8(REG_BCN_CTRL_CLINT1);
+			break;
+		case HALMAC_PORTID3:
+			ctrl_value = HALMAC_REG_R8(REG_BCN_CTRL_CLINT2);
+			break;
+		case HALMAC_PORTID4:
+			ctrl_value = HALMAC_REG_R8(REG_BCN_CTRL_CLINT3);
+			break;
+		default:
+			break;
+		}
+
+		if (ctrl_value & BIT_EN_P2P_BCNQ_AREA)
+			ctrl->en_p2p_bcn_area = 1;
+		else
+			ctrl->en_p2p_bcn_area = 0;
+
+		if (ctrl_value & BIT_EN_P2P_CTWINDOW)
+			ctrl->en_p2p_ctwin = 1;
+		else
+			ctrl->en_p2p_ctwin = 0;
+
+		if (ctrl_value & BIT_P0_EN_RXBCN_RPT)
+			ctrl->en_rxbcn_rpt = 1;
+		else
+			ctrl->en_rxbcn_rpt = 0;
+
+		if (ctrl_value & BIT_EN_BCN_FUNCTION)
+			ctrl->en_bcn = 1;
+		else
+			ctrl->en_bcn = 0;
+
+		if (ctrl_value & BIT_DIS_TSF_UDT)
+			ctrl->dis_tsf_udt = 1;
+		else
+			ctrl->dis_tsf_udt = 0;
+
+		if (ctrl_value & BIT_P0_EN_TXBCN_RPT)
+			ctrl->en_txbcn_rpt = 1;
+		else
+			ctrl->en_txbcn_rpt = 0;
+
+		if (ctrl_value & BIT_DIS_RX_BSSID_FIT)
+			ctrl->dis_rx_bssid_fit = 1;
+		else
+			ctrl->dis_rx_bssid_fit = 0;
+	}
+
+	PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
+
+	return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * cfg_multicast_addr_88xx() - config multicast address
+ * @adapter : the adapter of halmac
+ * @addr : multicast address
+ * Author : KaiYuan Chang/Ivan Lin
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+cfg_multicast_addr_88xx(struct halmac_adapter *adapter,
+			union halmac_wlan_addr *addr)
+{
+	struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
+
+	PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
+
+	HALMAC_REG_W32(REG_MAR, rtk_le32_to_cpu(addr->addr_l_h.low));
+	HALMAC_REG_W16(REG_MAR + 4, rtk_le16_to_cpu(addr->addr_l_h.high));
+
+	PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
+
+	return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * cfg_operation_mode_88xx() - config operation mode
+ * @adapter : the adapter of halmac
+ * @mode : 802.11 standard(b/g/n/ac)
+ * Author : KaiYuan Chang/Ivan Lin
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+cfg_operation_mode_88xx(struct halmac_adapter *adapter,
+			enum halmac_wireless_mode mode)
+{
+	return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * cfg_ch_bw_88xx() - config channel & bandwidth
+ * @adapter : the adapter of halmac
+ * @ch : WLAN channel, support 2.4G & 5G
+ * @idx : primary channel index, idx1, idx2, idx3, idx4
+ * @bw : band width, 20, 40, 80, 160, 5 ,10
+ * Author : KaiYuan Chang
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+cfg_ch_bw_88xx(struct halmac_adapter *adapter, u8 ch,
+	       enum halmac_pri_ch_idx idx, enum halmac_bw bw)
+{
+	PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
+
+	cfg_pri_ch_idx_88xx(adapter, idx);
+	cfg_bw_88xx(adapter, bw);
+	cfg_ch_88xx(adapter, ch);
+
+	PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
+
+	return HALMAC_RET_SUCCESS;
+}
+
+enum halmac_ret_status
+cfg_ch_88xx(struct halmac_adapter *adapter, u8 ch)
+{
+	u8 value8;
+	struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
+
+	PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
+
+	value8 = HALMAC_REG_R8(REG_CCK_CHECK);
+	value8 = value8 & (~(BIT(7)));
+
+	if (ch > 35)
+		value8 = value8 | BIT(7);
+
+	HALMAC_REG_W8(REG_CCK_CHECK, value8);
+
+	PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
+
+	return HALMAC_RET_SUCCESS;
+}
+
+enum halmac_ret_status
+cfg_pri_ch_idx_88xx(struct halmac_adapter *adapter, enum halmac_pri_ch_idx idx)
+{
+	u8 txsc40 = 0, txsc20 = 0;
+	struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
+
+	PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
+
+	txsc20 = idx;
+	if (txsc20 == HALMAC_CH_IDX_1 || txsc20 == HALMAC_CH_IDX_3)
+		txsc40 = 9;
+	else
+		txsc40 = 10;
+
+	HALMAC_REG_W8(REG_DATA_SC, BIT_TXSC_20M(txsc20) | BIT_TXSC_40M(txsc40));
+
+	PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
+
+	return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * cfg_bw_88xx() - config bandwidth
+ * @adapter : the adapter of halmac
+ * @bw : band width, 20, 40, 80, 160, 5 ,10
+ * Author : KaiYuan Chang
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+cfg_bw_88xx(struct halmac_adapter *adapter, enum halmac_bw bw)
+{
+	u32 value32;
+	struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
+
+	PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
+
+	value32 = HALMAC_REG_R32(REG_WMAC_TRXPTCL_CTL);
+	value32 = value32 & (~(BIT(7) | BIT(8)));
+
+	switch (bw) {
+	case HALMAC_BW_80:
+		value32 = value32 | BIT(8);
+		break;
+	case HALMAC_BW_40:
+		value32 = value32 | BIT(7);
+		break;
+	case HALMAC_BW_20:
+	case HALMAC_BW_10:
+	case HALMAC_BW_5:
+		break;
+	default:
+		break;
+	}
+
+	HALMAC_REG_W32(REG_WMAC_TRXPTCL_CTL, value32);
+
+	/* TODO:Move to change mac clk api later... */
+	value32 = HALMAC_REG_R32(REG_AFE_CTRL1) & ~(BIT(20) | BIT(21));
+	value32 |= (MAC_CLK_HW_DEF_80M << BIT_SHIFT_MAC_CLK_SEL);
+	HALMAC_REG_W32(REG_AFE_CTRL1, value32);
+
+	HALMAC_REG_W8(REG_USTIME_TSF, MAC_CLK_SPEED);
+	HALMAC_REG_W8(REG_USTIME_EDCA, MAC_CLK_SPEED);
+
+	PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
+
+	return HALMAC_RET_SUCCESS;
+}
+
+void
+enable_bb_rf_88xx(struct halmac_adapter *adapter, u8 enable)
+{
+	u8 value8;
+	u32 value32;
+	struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
+
+	if (enable == 1) {
+		value8 = HALMAC_REG_R8(REG_SYS_FUNC_EN);
+		value8 = value8 | BIT(0) | BIT(1);
+		HALMAC_REG_W8(REG_SYS_FUNC_EN, value8);
+
+		value8 = HALMAC_REG_R8(REG_RF_CTRL);
+		value8 = value8 | BIT(0) | BIT(1) | BIT(2);
+		HALMAC_REG_W8(REG_RF_CTRL, value8);
+
+		value32 = HALMAC_REG_R32(REG_WLRF1);
+		value32 = value32 | BIT(24) | BIT(25) | BIT(26);
+		HALMAC_REG_W32(REG_WLRF1, value32);
+	} else {
+		value8 = HALMAC_REG_R8(REG_SYS_FUNC_EN);
+		value8 = value8 & (~(BIT(0) | BIT(1)));
+		HALMAC_REG_W8(REG_SYS_FUNC_EN, value8);
+
+		value8 = HALMAC_REG_R8(REG_RF_CTRL);
+		value8 = value8 & (~(BIT(0) | BIT(1) | BIT(2)));
+		HALMAC_REG_W8(REG_RF_CTRL, value8);
+
+		value32 = HALMAC_REG_R32(REG_WLRF1);
+		value32 = value32 & (~(BIT(24) | BIT(25) | BIT(26)));
+		HALMAC_REG_W32(REG_WLRF1, value32);
+	}
+}
+
+/**
+ * cfg_la_mode_88xx() - config la mode
+ * @adapter : the adapter of halmac
+ * @mode :
+ *	disable : no TXFF space reserved for LA debug
+ *	partial : partial TXFF space is reserved for LA debug
+ *	full : all TXFF space is reserved for LA debug
+ * Author : KaiYuan Chang
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+cfg_la_mode_88xx(struct halmac_adapter *adapter, enum halmac_la_mode mode)
+{
+	if (adapter->api_registry.la_mode_en == 0)
+		return HALMAC_RET_NOT_SUPPORT;
+
+	PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
+
+	adapter->txff_alloc.la_mode = mode;
+
+	PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
+
+	return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * cfg_rxfifo_expand_mode_88xx() - rx fifo expanding
+ * @adapter : the adapter of halmac
+ * @mode :
+ *	disable : normal mode
+ *	1 block : Rx FIFO + 1 FIFO block; Tx fifo - 1 FIFO block
+ *	2 block : Rx FIFO + 2 FIFO block; Tx fifo - 2 FIFO block
+ *	3 block : Rx FIFO + 3 FIFO block; Tx fifo - 3 FIFO block
+ * Author : Soar
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+cfg_rxfifo_expand_mode_88xx(struct halmac_adapter *adapter,
+			    enum halmac_rx_fifo_expanding_mode mode)
+{
+	if (adapter->api_registry.rx_exp_en == 0)
+		return HALMAC_RET_NOT_SUPPORT;
+
+	PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
+
+	adapter->txff_alloc.rx_fifo_exp_mode = mode;
+
+	PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
+
+	return HALMAC_RET_SUCCESS;
+}
+
+enum halmac_ret_status
+config_security_88xx(struct halmac_adapter *adapter,
+		     struct halmac_security_setting *setting)
+{
+	u8 sec_cfg;
+	struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
+
+	PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
+
+	HALMAC_REG_W16_SET(REG_CR, BIT_MAC_SEC_EN);
+
+	if (setting->compare_keyid == 1) {
+		HALMAC_REG_W8_SET(REG_SECCFG + 1, BIT(0));
+		adapter->hw_cfg_info.chk_security_keyid = 1;
+	} else {
+		adapter->hw_cfg_info.chk_security_keyid = 0;
+	}
+
+	sec_cfg = HALMAC_REG_R8(REG_SECCFG);
+
+	/* BC/MC uses default key */
+	/* cam entry 0~3, kei id = 0 -> entry0, kei id = 1 -> entry1... */
+	sec_cfg |= (BIT_TXBCUSEDK | BIT_RXBCUSEDK);
+
+	if (setting->tx_encryption == 1)
+		sec_cfg |= BIT_TXENC;
+	else
+		sec_cfg &= ~BIT_TXENC;
+
+	if (setting->rx_decryption == 1)
+		sec_cfg |= BIT_RXDEC;
+	else
+		sec_cfg &= ~BIT_RXDEC;
+
+	HALMAC_REG_W8(REG_SECCFG, sec_cfg);
+
+	if (setting->bip_enable == 1) {
+		if (adapter->chip_id == HALMAC_CHIP_ID_8822B)
+			return HALMAC_RET_BIP_NO_SUPPORT;
+#if (HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8812F_SUPPORT)
+		sec_cfg = HALMAC_REG_R8(REG_WSEC_OPTION + 2);
+
+		if (setting->tx_encryption == 1)
+			sec_cfg |= (BIT(3) | BIT(5));
+		else
+			sec_cfg &= ~(BIT(3) | BIT(5));
+
+		if (setting->rx_decryption == 1)
+			sec_cfg |= (BIT(4) | BIT(6));
+		else
+			sec_cfg &= ~(BIT(4) | BIT(6));
+
+		HALMAC_REG_W8(REG_WSEC_OPTION + 2, sec_cfg);
+#endif
+	}
+
+	PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
+
+	return HALMAC_RET_SUCCESS;
+}
+
+u8
+get_used_cam_entry_num_88xx(struct halmac_adapter *adapter,
+			    enum hal_security_type sec_type)
+{
+	u8 entry_num;
+
+	PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
+
+	switch (sec_type) {
+	case HAL_SECURITY_TYPE_WEP40:
+	case HAL_SECURITY_TYPE_WEP104:
+	case HAL_SECURITY_TYPE_TKIP:
+	case HAL_SECURITY_TYPE_AES128:
+	case HAL_SECURITY_TYPE_GCMP128:
+	case HAL_SECURITY_TYPE_GCMSMS4:
+	case HAL_SECURITY_TYPE_BIP:
+		entry_num = 1;
+		break;
+	case HAL_SECURITY_TYPE_WAPI:
+	case HAL_SECURITY_TYPE_AES256:
+	case HAL_SECURITY_TYPE_GCMP256:
+		entry_num = 2;
+		break;
+	default:
+		entry_num = 0;
+		break;
+	}
+
+	PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
+
+	return entry_num;
+}
+
+enum halmac_ret_status
+write_cam_88xx(struct halmac_adapter *adapter, u32 idx,
+	       struct halmac_cam_entry_info *info)
+{
+	u32 i;
+	u32 cmd = 0x80010000;
+	struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
+	struct halmac_cam_entry_format *fmt = NULL;
+
+	PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
+
+	if (idx >= adapter->hw_cfg_info.cam_entry_num)
+		return HALMAC_RET_ENTRY_INDEX_ERROR;
+
+	if (info->key_id > 3)
+		return HALMAC_RET_FAIL;
+
+	fmt = (struct halmac_cam_entry_format *)PLTFM_MALLOC(sizeof(*fmt));
+	if (!fmt)
+		return HALMAC_RET_NULL_POINTER;
+	PLTFM_MEMSET(fmt, 0x00, sizeof(*fmt));
+
+	if (adapter->hw_cfg_info.chk_security_keyid == 1)
+		fmt->key_id = info->key_id;
+	fmt->valid = info->valid;
+	PLTFM_MEMCPY(fmt->mac_address, info->mac_address, 6);
+	PLTFM_MEMCPY(fmt->key, info->key, 16);
+
+	switch (info->security_type) {
+	case HAL_SECURITY_TYPE_NONE:
+		fmt->type = 0;
+		break;
+	case HAL_SECURITY_TYPE_WEP40:
+		fmt->type = 1;
+		break;
+	case HAL_SECURITY_TYPE_WEP104:
+		fmt->type = 5;
+		break;
+	case HAL_SECURITY_TYPE_TKIP:
+		fmt->type = 2;
+		break;
+	case HAL_SECURITY_TYPE_AES128:
+		fmt->type = 4;
+		break;
+	case HAL_SECURITY_TYPE_WAPI:
+		fmt->type = 6;
+		break;
+	case HAL_SECURITY_TYPE_AES256:
+		fmt->type = 4;
+		fmt->ext_sectype = 1;
+		break;
+	case HAL_SECURITY_TYPE_GCMP128:
+		fmt->type = 7;
+		break;
+	case HAL_SECURITY_TYPE_GCMP256:
+	case HAL_SECURITY_TYPE_GCMSMS4:
+		fmt->type = 7;
+		fmt->ext_sectype = 1;
+		break;
+	case HAL_SECURITY_TYPE_BIP:
+		fmt->type = (info->unicast == 1) ? 4 : 0;
+		fmt->mgnt = 1;
+		fmt->grp = (info->unicast == 1) ? 0 : 1;
+		break;
+	default:
+		PLTFM_FREE(fmt, sizeof(*fmt));
+		return HALMAC_RET_FAIL;
+	}
+
+	for (i = 0; i < 8; i++) {
+		HALMAC_REG_W32(REG_CAMWRITE, *((u32 *)fmt + i));
+		HALMAC_REG_W32(REG_CAMCMD, cmd | ((idx << 3) + i));
+	}
+
+	if (info->security_type == HAL_SECURITY_TYPE_WAPI ||
+	    info->security_type == HAL_SECURITY_TYPE_AES256 ||
+	    info->security_type == HAL_SECURITY_TYPE_GCMP256 ||
+	    info->security_type == HAL_SECURITY_TYPE_GCMSMS4) {
+		fmt->mic = 1;
+		PLTFM_MEMCPY(fmt->key, info->key_ext, 16);
+		idx++;
+		for (i = 0; i < 8; i++) {
+			HALMAC_REG_W32(REG_CAMWRITE, *((u32 *)fmt + i));
+			HALMAC_REG_W32(REG_CAMCMD, cmd | ((idx << 3) + i));
+		}
+	}
+
+	PLTFM_FREE(fmt, sizeof(*fmt));
+
+	PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
+
+	return HALMAC_RET_SUCCESS;
+}
+
+enum halmac_ret_status
+read_cam_entry_88xx(struct halmac_adapter *adapter, u32 idx,
+		    struct halmac_cam_entry_format *content)
+{
+	u32 i;
+	u32 cmd = 0x80000000;
+	struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
+
+	PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
+
+	if (idx >= adapter->hw_cfg_info.cam_entry_num)
+		return HALMAC_RET_ENTRY_INDEX_ERROR;
+
+	for (i = 0; i < 8; i++) {
+		HALMAC_REG_W32(REG_CAMCMD, cmd | ((idx << 3) + i));
+		*((u32 *)content + i) = HALMAC_REG_R32(REG_CAMREAD);
+	}
+
+	PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
+
+	return HALMAC_RET_SUCCESS;
+}
+
+enum halmac_ret_status
+clear_cam_entry_88xx(struct halmac_adapter *adapter, u32 idx)
+{
+	u32 i;
+	u32 cmd = 0x80010000;
+	struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
+	struct halmac_cam_entry_format *fmt = NULL;
+
+	PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
+
+	if (idx >= adapter->hw_cfg_info.cam_entry_num)
+		return HALMAC_RET_ENTRY_INDEX_ERROR;
+
+	fmt = (struct halmac_cam_entry_format *)PLTFM_MALLOC(sizeof(*fmt));
+	if (!fmt)
+		return HALMAC_RET_NULL_POINTER;
+	PLTFM_MEMSET(fmt, 0x00, sizeof(*fmt));
+
+	for (i = 0; i < 8; i++) {
+		HALMAC_REG_W32(REG_CAMWRITE, *((u32 *)fmt + i));
+		HALMAC_REG_W32(REG_CAMCMD, cmd | ((idx << 3) + i));
+	}
+
+	PLTFM_FREE(fmt, sizeof(*fmt));
+
+	PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
+
+	return HALMAC_RET_SUCCESS;
+}
+
+void
+rx_shift_88xx(struct halmac_adapter *adapter, u8 enable)
+{
+	u8 value8;
+	struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
+
+	value8 = HALMAC_REG_R8(REG_TXDMA_PQ_MAP);
+
+	if (enable == 1)
+		HALMAC_REG_W8(REG_TXDMA_PQ_MAP, value8 | BIT(1));
+	else
+		HALMAC_REG_W8(REG_TXDMA_PQ_MAP, value8 & ~(BIT(1)));
+}
+
+/**
+ * cfg_edca_para_88xx() - config edca parameter
+ * @adapter : the adapter of halmac
+ * @acq_id : VO/VI/BE/BK
+ * @param : aifs, cw, txop limit
+ * Author : Ivan Lin
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+cfg_edca_para_88xx(struct halmac_adapter *adapter, enum halmac_acq_id acq_id,
+		   struct halmac_edca_para *param)
+{
+	u32 offset;
+	u32 value32;
+	struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
+
+	PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
+
+	switch (acq_id) {
+	case HALMAC_ACQ_ID_VO:
+		offset = REG_EDCA_VO_PARAM;
+		break;
+	case HALMAC_ACQ_ID_VI:
+		offset = REG_EDCA_VI_PARAM;
+		break;
+	case HALMAC_ACQ_ID_BE:
+		offset = REG_EDCA_BE_PARAM;
+		break;
+	case HALMAC_ACQ_ID_BK:
+		offset = REG_EDCA_BK_PARAM;
+		break;
+	default:
+		return HALMAC_RET_SWITCH_CASE_ERROR;
+	}
+
+	param->txop_limit &= 0x7FF;
+	value32 = (param->aifs) | (param->cw << 8) | (param->txop_limit << 16);
+
+	HALMAC_REG_W32(offset, value32);
+
+	PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
+
+	return HALMAC_RET_SUCCESS;
+}
+
+void
+rx_clk_gate_88xx(struct halmac_adapter *adapter, u8 enable)
+{
+	u8 value8;
+	struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
+
+	value8 = HALMAC_REG_R8(REG_RCR + 2);
+
+	if (enable == 1)
+		HALMAC_REG_W8(REG_RCR + 2, value8 & ~(BIT(3)));
+	else
+		HALMAC_REG_W8(REG_RCR + 2, value8 | BIT(3));
+}
+
+enum halmac_ret_status
+rx_cut_amsdu_cfg_88xx(struct halmac_adapter *adapter,
+		      struct halmac_cut_amsdu_cfg *cfg)
+{
+	return HALMAC_RET_NOT_SUPPORT;
+}
+
+enum halmac_ret_status
+fast_edca_cfg_88xx(struct halmac_adapter *adapter,
+		   struct halmac_fast_edca_cfg *cfg)
+{
+	u16 value16;
+	u32 offset;
+	struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
+
+	PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
+
+	switch (cfg->acq_id) {
+	case HALMAC_ACQ_ID_VO:
+		offset = REG_FAST_EDCA_VOVI_SETTING;
+		break;
+	case HALMAC_ACQ_ID_VI:
+		offset = REG_FAST_EDCA_VOVI_SETTING + 2;
+		break;
+	case HALMAC_ACQ_ID_BE:
+		offset = REG_FAST_EDCA_BEBK_SETTING;
+		break;
+	case HALMAC_ACQ_ID_BK:
+		offset = REG_FAST_EDCA_BEBK_SETTING + 2;
+		break;
+	default:
+		return HALMAC_RET_SWITCH_CASE_ERROR;
+	}
+
+	value16 = HALMAC_REG_R16(offset);
+	value16 &= 0xFF;
+	value16 = value16 | (cfg->queue_to << 8);
+
+	HALMAC_REG_W16(offset, value16);
+
+	PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
+
+	return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * get_mac_addr_88xx() - get mac address
+ * @adapter : the adapter of halmac
+ * @port : 0 for port0, 1 for port1, 2 for port2, 3 for port3, 4 for port4
+ * @addr : mac address
+ * Author : Ivan Lin
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+get_mac_addr_88xx(struct halmac_adapter *adapter, u8 port,
+		  union halmac_wlan_addr *addr)
+{
+	u16 mac_addr_h;
+	u32 mac_addr_l;
+	struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
+
+	PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
+
+	if (port >= HALMAC_PORTID_NUM) {
+		PLTFM_MSG_ERR("[ERR]port index >= 5\n");
+		return HALMAC_RET_PORT_NOT_SUPPORT;
+	}
+
+	switch (port) {
+	case HALMAC_PORTID0:
+		mac_addr_l = HALMAC_REG_R32(REG_MACID);
+		mac_addr_h = HALMAC_REG_R16(REG_MACID + 4);
+		break;
+	case HALMAC_PORTID1:
+		mac_addr_l = HALMAC_REG_R32(REG_MACID1);
+		mac_addr_h = HALMAC_REG_R16(REG_MACID1 + 4);
+		break;
+	case HALMAC_PORTID2:
+		mac_addr_l = HALMAC_REG_R32(REG_MACID2);
+		mac_addr_h = HALMAC_REG_R16(REG_MACID2 + 4);
+		break;
+	case HALMAC_PORTID3:
+		mac_addr_l = HALMAC_REG_R32(REG_MACID3);
+		mac_addr_h = HALMAC_REG_R16(REG_MACID3 + 4);
+		break;
+	case HALMAC_PORTID4:
+		mac_addr_l = HALMAC_REG_R32(REG_MACID4);
+		mac_addr_h = HALMAC_REG_R16(REG_MACID4 + 4);
+		break;
+	default:
+		return HALMAC_RET_PORT_NOT_SUPPORT;
+	}
+
+	addr->addr_l_h.low = rtk_cpu_to_le32(mac_addr_l);
+	addr->addr_l_h.high = rtk_cpu_to_le16(mac_addr_h);
+
+	PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
+
+	return HALMAC_RET_SUCCESS;
+}
+
+void
+rts_full_bw_88xx(struct halmac_adapter *adapter, u8 enable)
+{
+	u8 value8;
+	struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
+
+	value8 = HALMAC_REG_R8(REG_INIRTS_RATE_SEL);
+
+	if (enable == 1)
+		HALMAC_REG_W8(REG_INIRTS_RATE_SEL, value8 | BIT(5));
+	else
+		HALMAC_REG_W8(REG_INIRTS_RATE_SEL, value8 & ~(BIT(5)));
+}
+
+#endif /* HALMAC_88XX_SUPPORT */
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/halmac/halmac_88xx/halmac_cfg_wmac_88xx.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/halmac/halmac_88xx/halmac_cfg_wmac_88xx.h
--- linux-5.6.3/3rdparty/rtl8821ce/hal/halmac/halmac_88xx/halmac_cfg_wmac_88xx.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/halmac/halmac_88xx/halmac_cfg_wmac_88xx.h	2020-04-10 16:35:06.792658947 +0300
@@ -0,0 +1,126 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ ******************************************************************************/
+
+#ifndef _HALMAC_CFG_WMAC_88XX_H_
+#define _HALMAC_CFG_WMAC_88XX_H_
+
+#include "../halmac_api.h"
+
+#if HALMAC_88XX_SUPPORT
+
+enum halmac_ret_status
+cfg_mac_addr_88xx(struct halmac_adapter *adapter, u8 port,
+		  union halmac_wlan_addr *addr);
+
+enum halmac_ret_status
+cfg_bssid_88xx(struct halmac_adapter *adapter, u8 port,
+	       union halmac_wlan_addr *addr);
+
+enum halmac_ret_status
+cfg_transmitter_addr_88xx(struct halmac_adapter *adapter, u8 port,
+			  union halmac_wlan_addr *addr);
+
+enum halmac_ret_status
+cfg_net_type_88xx(struct halmac_adapter *adapter, u8 port,
+		  enum halmac_network_type_select net_type);
+
+enum halmac_ret_status
+cfg_tsf_rst_88xx(struct halmac_adapter *adapter, u8 port);
+
+enum halmac_ret_status
+cfg_bcn_space_88xx(struct halmac_adapter *adapter, u8 port, u32 bcn_space);
+
+enum halmac_ret_status
+rw_bcn_ctrl_88xx(struct halmac_adapter *adapter, u8 port, u8 write_en,
+		 struct halmac_bcn_ctrl *ctrl);
+
+enum halmac_ret_status
+cfg_multicast_addr_88xx(struct halmac_adapter *adapter,
+			union halmac_wlan_addr *addr);
+
+enum halmac_ret_status
+cfg_operation_mode_88xx(struct halmac_adapter *adapter,
+			enum halmac_wireless_mode mode);
+
+enum halmac_ret_status
+cfg_ch_bw_88xx(struct halmac_adapter *adapter, u8 ch,
+	       enum halmac_pri_ch_idx idx, enum halmac_bw bw);
+
+enum halmac_ret_status
+cfg_ch_88xx(struct halmac_adapter *adapter, u8 ch);
+
+enum halmac_ret_status
+cfg_pri_ch_idx_88xx(struct halmac_adapter *adapter, enum halmac_pri_ch_idx idx);
+
+enum halmac_ret_status
+cfg_bw_88xx(struct halmac_adapter *adapter, enum halmac_bw bw);
+
+void
+enable_bb_rf_88xx(struct halmac_adapter *adapter, u8 enable);
+
+enum halmac_ret_status
+cfg_la_mode_88xx(struct halmac_adapter *adapter, enum halmac_la_mode mode);
+
+enum halmac_ret_status
+cfg_rxfifo_expand_mode_88xx(struct halmac_adapter *adapter,
+			    enum halmac_rx_fifo_expanding_mode mode);
+
+enum halmac_ret_status
+config_security_88xx(struct halmac_adapter *adapter,
+		     struct halmac_security_setting *setting);
+
+u8
+get_used_cam_entry_num_88xx(struct halmac_adapter *adapter,
+			    enum hal_security_type sec_type);
+
+enum halmac_ret_status
+write_cam_88xx(struct halmac_adapter *adapter, u32 idx,
+	       struct halmac_cam_entry_info *info);
+
+enum halmac_ret_status
+read_cam_entry_88xx(struct halmac_adapter *adapter, u32 idx,
+		    struct halmac_cam_entry_format *content);
+
+enum halmac_ret_status
+clear_cam_entry_88xx(struct halmac_adapter *adapter, u32 idx);
+
+void
+rx_shift_88xx(struct halmac_adapter *adapter, u8 enable);
+
+enum halmac_ret_status
+cfg_edca_para_88xx(struct halmac_adapter *adapter, enum halmac_acq_id acq_id,
+		   struct halmac_edca_para *param);
+
+void
+rx_clk_gate_88xx(struct halmac_adapter *adapter, u8 enable);
+
+enum halmac_ret_status
+rx_cut_amsdu_cfg_88xx(struct halmac_adapter *adapter,
+		      struct halmac_cut_amsdu_cfg *cfg);
+
+enum halmac_ret_status
+fast_edca_cfg_88xx(struct halmac_adapter *adapter,
+		   struct halmac_fast_edca_cfg *cfg);
+
+enum halmac_ret_status
+get_mac_addr_88xx(struct halmac_adapter *adapter, u8 port,
+		  union halmac_wlan_addr *addr);
+
+void
+rts_full_bw_88xx(struct halmac_adapter *adapter, u8 enable);
+
+#endif/* HALMAC_88XX_SUPPORT */
+
+#endif/* _HALMAC_CFG_WMAC_88XX_H_ */
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/halmac/halmac_88xx/halmac_common_88xx.c linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/halmac/halmac_88xx/halmac_common_88xx.c
--- linux-5.6.3/3rdparty/rtl8821ce/hal/halmac/halmac_88xx/halmac_common_88xx.c	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/halmac/halmac_88xx/halmac_common_88xx.c	2020-04-10 16:35:06.792658947 +0300
@@ -0,0 +1,2895 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ ******************************************************************************/
+
+#include "halmac_common_88xx.h"
+#include "halmac_88xx_cfg.h"
+#include "halmac_init_88xx.h"
+#include "halmac_cfg_wmac_88xx.h"
+#include "halmac_efuse_88xx.h"
+#include "halmac_bb_rf_88xx.h"
+#if HALMAC_USB_SUPPORT
+#include "halmac_usb_88xx.h"
+#endif
+#if HALMAC_SDIO_SUPPORT
+#include "halmac_sdio_88xx.h"
+#endif
+#if HALMAC_PCIE_SUPPORT
+#include "halmac_pcie_88xx.h"
+#endif
+#include "halmac_mimo_88xx.h"
+
+#if HALMAC_88XX_SUPPORT
+
+#define CFG_PARAM_H2C_INFO_SIZE	12
+#define ORIGINAL_H2C_CMD_SIZE	8
+
+#define WLHDR_PROT_VER	0
+
+#define WLHDR_TYPE_MGMT		0
+#define WLHDR_TYPE_CTRL		1
+#define WLHDR_TYPE_DATA		2
+
+/* mgmt frame */
+#define WLHDR_SUB_TYPE_ASSOC_REQ	0
+#define WLHDR_SUB_TYPE_ASSOC_RSPNS	1
+#define WLHDR_SUB_TYPE_REASSOC_REQ	2
+#define WLHDR_SUB_TYPE_REASSOC_RSPNS	3
+#define WLHDR_SUB_TYPE_PROBE_REQ	4
+#define WLHDR_SUB_TYPE_PROBE_RSPNS	5
+#define WLHDR_SUB_TYPE_BCN		8
+#define WLHDR_SUB_TYPE_DISASSOC		10
+#define WLHDR_SUB_TYPE_AUTH		11
+#define WLHDR_SUB_TYPE_DEAUTH		12
+#define WLHDR_SUB_TYPE_ACTION		13
+#define WLHDR_SUB_TYPE_ACTION_NOACK	14
+
+/* ctrl frame */
+#define WLHDR_SUB_TYPE_BF_RPT_POLL	4
+#define WLHDR_SUB_TYPE_NDPA		5
+
+/* data frame */
+#define WLHDR_SUB_TYPE_DATA		0
+#define WLHDR_SUB_TYPE_NULL		4
+#define WLHDR_SUB_TYPE_QOS_DATA		8
+#define WLHDR_SUB_TYPE_QOS_NULL		12
+
+#define LTECOEX_ACCESS_CTRL REG_WL2LTECOEX_INDIRECT_ACCESS_CTRL_V1
+
+struct wlhdr_frame_ctrl {
+	u16 protocol:2;
+	u16 type:2;
+	u16 sub_type:4;
+	u16 to_ds:1;
+	u16 from_ds:1;
+	u16 more_frag:1;
+	u16 retry:1;
+	u16 pwr_mgmt:1;
+	u16 more_data:1;
+	u16 protect_frame:1;
+	u16 order:1;
+};
+
+static enum halmac_ret_status
+parse_c2h_pkt_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size);
+
+static enum halmac_ret_status
+get_c2h_dbg_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size);
+
+static enum halmac_ret_status
+get_h2c_ack_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size);
+
+static enum halmac_ret_status
+get_scan_rpt_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size);
+
+static enum halmac_ret_status
+get_h2c_ack_cfg_param_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size);
+
+static enum halmac_ret_status
+get_h2c_ack_update_pkt_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size);
+
+static enum halmac_ret_status
+get_h2c_ack_update_datapkt_88xx(struct halmac_adapter *adapter, u8 *buf,
+				u32 size);
+
+static enum halmac_ret_status
+get_h2c_ack_run_datapkt_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size);
+
+static enum halmac_ret_status
+get_h2c_ack_ch_switch_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size);
+
+static enum halmac_ret_status
+malloc_cfg_param_buf_88xx(struct halmac_adapter *adapter, u8 full_fifo);
+
+static enum halmac_cmd_construct_state
+cfg_param_cmd_cnstr_state_88xx(struct halmac_adapter *adapter);
+
+static enum halmac_ret_status
+proc_cfg_param_88xx(struct halmac_adapter *adapter,
+		    struct halmac_phy_parameter_info *param, u8 full_fifo);
+
+static enum halmac_ret_status
+send_cfg_param_h2c_88xx(struct halmac_adapter *adapter);
+
+static enum halmac_ret_status
+cnv_cfg_param_state_88xx(struct halmac_adapter *adapter,
+			 enum halmac_cmd_construct_state dest_state);
+
+static enum halmac_ret_status
+add_param_buf_88xx(struct halmac_adapter *adapter,
+		   struct halmac_phy_parameter_info *param, u8 *buf,
+		   u8 *end_cmd);
+
+static enum halmac_ret_status
+gen_cfg_param_h2c_88xx(struct halmac_adapter *adapter, u8 *buff);
+
+static enum halmac_ret_status
+send_h2c_update_packet_88xx(struct halmac_adapter *adapter,
+			    enum halmac_packet_id pkt_id, u8 *pkt, u32 size);
+
+static enum halmac_ret_status
+send_bt_coex_cmd_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size,
+		      u8 ack);
+
+static enum halmac_ret_status
+read_buf_88xx(struct halmac_adapter *adapter, u32 offset, u32 size,
+	      enum hal_fifo_sel sel, u8 *data);
+
+static enum halmac_cmd_construct_state
+scan_cmd_cnstr_state_88xx(struct halmac_adapter *adapter);
+
+static enum halmac_ret_status
+cnv_scan_state_88xx(struct halmac_adapter *adapter,
+		    enum halmac_cmd_construct_state dest_state);
+
+static enum halmac_ret_status
+proc_ctrl_ch_switch_88xx(struct halmac_adapter *adapter,
+			 struct halmac_ch_switch_option *opt);
+
+static enum halmac_ret_status
+proc_p2pps_88xx(struct halmac_adapter *adapter, struct halmac_p2pps *info);
+
+static enum halmac_ret_status
+get_cfg_param_status_88xx(struct halmac_adapter *adapter,
+			  enum halmac_cmd_process_status *proc_status);
+
+static enum halmac_ret_status
+get_ch_switch_status_88xx(struct halmac_adapter *adapter,
+			  enum halmac_cmd_process_status *proc_status);
+
+static enum halmac_ret_status
+get_update_packet_status_88xx(struct halmac_adapter *adapter,
+			      enum halmac_cmd_process_status *proc_status);
+
+static enum halmac_ret_status
+pwr_sub_seq_parser_88xx(struct halmac_adapter *adapter, u8 cut, u8 intf,
+			struct halmac_wlan_pwr_cfg *cmd);
+
+static void
+pwr_state_88xx(struct halmac_adapter *adapter, enum halmac_mac_power *state);
+
+static enum halmac_ret_status
+pwr_cmd_polling_88xx(struct halmac_adapter *adapter,
+		     struct halmac_wlan_pwr_cfg *cmd);
+
+static void
+get_pq_mapping_88xx(struct halmac_adapter *adapter,
+		    struct halmac_rqpn_map *mapping);
+
+static void
+dump_reg_sdio_88xx(struct halmac_adapter *adapter);
+
+static enum halmac_ret_status
+wlhdr_valid_88xx(struct halmac_adapter *adapter, u8 *buf);
+
+static u8
+wlhdr_mgmt_valid_88xx(struct halmac_adapter *adapter,
+		      struct wlhdr_frame_ctrl *wlhdr);
+
+static u8
+wlhdr_ctrl_valid_88xx(struct halmac_adapter *adapter,
+		      struct wlhdr_frame_ctrl *wlhdr);
+
+static u8
+wlhdr_data_valid_88xx(struct halmac_adapter *adapter,
+		      struct wlhdr_frame_ctrl *wlhdr);
+
+static void
+dump_reg_88xx(struct halmac_adapter *adapter);
+
+/**
+ * ofld_func_cfg_88xx() - config offload function
+ * @adapter : the adapter of halmac
+ * @info : offload function information
+ * Author : Ivan Lin
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+ofld_func_cfg_88xx(struct halmac_adapter *adapter,
+		   struct halmac_ofld_func_info *info)
+{
+	if (adapter->intf == HALMAC_INTERFACE_SDIO &&
+	    info->rsvd_pg_drv_buf_max_sz > SDIO_TX_MAX_SIZE_88XX)
+		return HALMAC_RET_FAIL;
+
+	adapter->pltfm_info.malloc_size = info->halmac_malloc_max_sz;
+	adapter->pltfm_info.rsvd_pg_size = info->rsvd_pg_drv_buf_max_sz;
+
+	return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * dl_drv_rsvd_page_88xx() - download packet to rsvd page
+ * @adapter : the adapter of halmac
+ * @pg_offset : page offset of driver's rsvd page
+ * @halmac_buf : data to be downloaded, tx_desc is not included
+ * @halmac_size : data size to be downloaded
+ * Author : KaiYuan Chang
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+dl_drv_rsvd_page_88xx(struct halmac_adapter *adapter, u8 pg_offset, u8 *buf,
+		      u32 size)
+{
+	enum halmac_ret_status status;
+	u32 pg_size;
+	u32 pg_num = 0;
+	u16 pg_addr = 0;
+
+	PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
+
+	pg_size = adapter->hw_cfg_info.page_size;
+	pg_num = size / pg_size + ((size & (pg_size - 1)) ? 1 : 0);
+	if (pg_offset + pg_num > adapter->txff_alloc.rsvd_drv_pg_num) {
+		PLTFM_MSG_ERR("[ERR] pkt overflow!!\n");
+		return HALMAC_RET_DRV_DL_ERR;
+	}
+
+	pg_addr = adapter->txff_alloc.rsvd_drv_addr + pg_offset;
+
+	status = dl_rsvd_page_88xx(adapter, pg_addr, buf, size);
+
+	if (status != HALMAC_RET_SUCCESS) {
+		PLTFM_MSG_ERR("[ERR]dl rsvd page fail!!\n");
+		return status;
+	}
+
+	PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
+
+	return HALMAC_RET_SUCCESS;
+}
+
+enum halmac_ret_status
+dl_rsvd_page_88xx(struct halmac_adapter *adapter, u16 pg_addr, u8 *buf,
+		  u32 size)
+{
+	u8 restore[2];
+	u8 value8;
+	u16 rsvd_pg_head;
+	u32 cnt;
+	enum halmac_rsvd_pg_state *state = &adapter->halmac_state.rsvd_pg_state;
+	struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
+	enum halmac_ret_status status = HALMAC_RET_SUCCESS;
+
+	if (size == 0) {
+		PLTFM_MSG_TRACE("[TRACE]pkt size = 0\n");
+		return HALMAC_RET_ZERO_LEN_RSVD_PACKET;
+	}
+
+	if (*state == HALMAC_RSVD_PG_STATE_BUSY)
+		return HALMAC_RET_BUSY_STATE;
+
+	*state = HALMAC_RSVD_PG_STATE_BUSY;
+
+	pg_addr &= BIT_MASK_BCN_HEAD_1_V1;
+	HALMAC_REG_W16(REG_FIFOPAGE_CTRL_2, (u16)(pg_addr | BIT(15)));
+
+	value8 = HALMAC_REG_R8(REG_CR + 1);
+	restore[0] = value8;
+	value8 = (u8)(value8 | BIT(0));
+	HALMAC_REG_W8(REG_CR + 1, value8);
+
+	value8 = HALMAC_REG_R8(REG_FWHW_TXQ_CTRL + 2);
+	restore[1] = value8;
+	value8 = (u8)(value8 & ~(BIT(6)));
+	HALMAC_REG_W8(REG_FWHW_TXQ_CTRL + 2, value8);
+
+	if (PLTFM_SEND_RSVD_PAGE(buf, size) == 0) {
+		PLTFM_MSG_ERR("[ERR]send rvsd pg(pltfm)!!\n");
+		status = HALMAC_RET_DL_RSVD_PAGE_FAIL;
+		goto DL_RSVD_PG_END;
+	}
+
+	cnt = 1000;
+	while (!(HALMAC_REG_R8(REG_FIFOPAGE_CTRL_2 + 1) & BIT(7))) {
+		PLTFM_DELAY_US(10);
+		cnt--;
+		if (cnt == 0) {
+			PLTFM_MSG_ERR("[ERR]bcn valid!!\n");
+			status = HALMAC_RET_POLLING_BCN_VALID_FAIL;
+			break;
+		}
+	}
+DL_RSVD_PG_END:
+	rsvd_pg_head = adapter->txff_alloc.rsvd_boundary;
+	HALMAC_REG_W16(REG_FIFOPAGE_CTRL_2, rsvd_pg_head | BIT(15));
+	HALMAC_REG_W8(REG_FWHW_TXQ_CTRL + 2, restore[1]);
+	HALMAC_REG_W8(REG_CR + 1, restore[0]);
+
+	*state = HALMAC_RSVD_PG_STATE_IDLE;
+
+	return status;
+}
+
+enum halmac_ret_status
+get_hw_value_88xx(struct halmac_adapter *adapter, enum halmac_hw_id hw_id,
+		  void *value)
+{
+	PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
+
+	switch (hw_id) {
+	case HALMAC_HW_RQPN_MAPPING:
+		get_pq_mapping_88xx(adapter, (struct halmac_rqpn_map *)value);
+		break;
+	case HALMAC_HW_EFUSE_SIZE:
+		*(u32 *)value = adapter->hw_cfg_info.efuse_size;
+		break;
+	case HALMAC_HW_EEPROM_SIZE:
+		*(u32 *)value = adapter->hw_cfg_info.eeprom_size;
+		break;
+	case HALMAC_HW_BT_BANK_EFUSE_SIZE:
+		*(u32 *)value = adapter->hw_cfg_info.bt_efuse_size;
+		break;
+	case HALMAC_HW_BT_BANK1_EFUSE_SIZE:
+	case HALMAC_HW_BT_BANK2_EFUSE_SIZE:
+		*(u32 *)value = 0;
+		break;
+	case HALMAC_HW_TXFIFO_SIZE:
+		*(u32 *)value = adapter->hw_cfg_info.tx_fifo_size;
+		break;
+	case HALMAC_HW_RXFIFO_SIZE:
+		*(u32 *)value = adapter->hw_cfg_info.rx_fifo_size;
+		break;
+	case HALMAC_HW_RSVD_PG_BNDY:
+		*(u16 *)value = adapter->txff_alloc.rsvd_drv_addr;
+		break;
+	case HALMAC_HW_CAM_ENTRY_NUM:
+		*(u8 *)value = adapter->hw_cfg_info.cam_entry_num;
+		break;
+	case HALMAC_HW_WLAN_EFUSE_AVAILABLE_SIZE:
+		get_efuse_available_size_88xx(adapter, (u32 *)value);
+		break;
+	case HALMAC_HW_IC_VERSION:
+		*(u8 *)value = adapter->chip_ver;
+		break;
+	case HALMAC_HW_PAGE_SIZE:
+		*(u32 *)value = adapter->hw_cfg_info.page_size;
+		break;
+	case HALMAC_HW_TX_AGG_ALIGN_SIZE:
+		*(u16 *)value = adapter->hw_cfg_info.tx_align_size;
+		break;
+	case HALMAC_HW_RX_AGG_ALIGN_SIZE:
+		*(u8 *)value = 8;
+		break;
+	case HALMAC_HW_DRV_INFO_SIZE:
+		*(u8 *)value = adapter->drv_info_size;
+		break;
+	case HALMAC_HW_TXFF_ALLOCATION:
+		PLTFM_MEMCPY(value, &adapter->txff_alloc,
+			     sizeof(struct halmac_txff_allocation));
+		break;
+	case HALMAC_HW_RSVD_EFUSE_SIZE:
+		*(u32 *)value = get_rsvd_efuse_size_88xx(adapter);
+		break;
+	case HALMAC_HW_FW_HDR_SIZE:
+		*(u32 *)value = WLAN_FW_HDR_SIZE;
+		break;
+	case HALMAC_HW_TX_DESC_SIZE:
+		*(u32 *)value = adapter->hw_cfg_info.txdesc_size;
+		break;
+	case HALMAC_HW_RX_DESC_SIZE:
+		*(u32 *)value = adapter->hw_cfg_info.rxdesc_size;
+		break;
+	case HALMAC_HW_ORI_H2C_SIZE:
+		*(u32 *)value = ORIGINAL_H2C_CMD_SIZE;
+		break;
+	case HALMAC_HW_RSVD_DRV_PGNUM:
+		*(u16 *)value = adapter->txff_alloc.rsvd_drv_pg_num;
+		break;
+	case HALMAC_HW_TX_PAGE_SIZE:
+		*(u16 *)value = TX_PAGE_SIZE_88XX;
+		break;
+	case HALMAC_HW_USB_TXAGG_DESC_NUM:
+		*(u8 *)value = adapter->hw_cfg_info.usb_txagg_num;
+		break;
+	case HALMAC_HW_AC_OQT_SIZE:
+		*(u8 *)value = adapter->hw_cfg_info.ac_oqt_size;
+		break;
+	case HALMAC_HW_NON_AC_OQT_SIZE:
+		*(u8 *)value = adapter->hw_cfg_info.non_ac_oqt_size;
+		break;
+	case HALMAC_HW_AC_QUEUE_NUM:
+		*(u8 *)value = adapter->hw_cfg_info.acq_num;
+		break;
+	case HALMAC_HW_PWR_STATE:
+		pwr_state_88xx(adapter, (enum halmac_mac_power *)value);
+		break;
+	default:
+		return HALMAC_RET_PARA_NOT_SUPPORT;
+	}
+
+	PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
+
+	return HALMAC_RET_SUCCESS;
+}
+
+static void
+get_pq_mapping_88xx(struct halmac_adapter *adapter,
+		    struct halmac_rqpn_map *mapping)
+{
+	mapping->dma_map_vo = adapter->pq_map[HALMAC_PQ_MAP_VO];
+	mapping->dma_map_vi = adapter->pq_map[HALMAC_PQ_MAP_VI];
+	mapping->dma_map_be = adapter->pq_map[HALMAC_PQ_MAP_BE];
+	mapping->dma_map_bk = adapter->pq_map[HALMAC_PQ_MAP_BK];
+	mapping->dma_map_mg = adapter->pq_map[HALMAC_PQ_MAP_MG];
+	mapping->dma_map_hi = adapter->pq_map[HALMAC_PQ_MAP_HI];
+}
+
+/**
+ * set_hw_value_88xx() -set hw config value
+ * @adapter : the adapter of halmac
+ * @hw_id : hw id for driver to config
+ * @value : hw value, reference table to get data type
+ * Author : KaiYuan Chang / Ivan Lin
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+set_hw_value_88xx(struct halmac_adapter *adapter, enum halmac_hw_id hw_id,
+		  void *value)
+{
+	enum halmac_ret_status status = HALMAC_RET_SUCCESS;
+	struct halmac_tx_page_threshold_info *th_info = NULL;
+	struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
+
+	PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
+
+	if (!value) {
+		PLTFM_MSG_ERR("[ERR]null ptr-set hw value\n");
+		return HALMAC_RET_NULL_POINTER;
+	}
+
+	switch (hw_id) {
+#if HALMAC_USB_SUPPORT
+	case HALMAC_HW_USB_MODE:
+		status = set_usb_mode_88xx(adapter,
+					   *(enum halmac_usb_mode *)value);
+		if (status != HALMAC_RET_SUCCESS)
+			return status;
+		break;
+#endif
+	case HALMAC_HW_BANDWIDTH:
+		cfg_bw_88xx(adapter, *(enum halmac_bw *)value);
+		break;
+	case HALMAC_HW_CHANNEL:
+		cfg_ch_88xx(adapter, *(u8 *)value);
+		break;
+	case HALMAC_HW_PRI_CHANNEL_IDX:
+		cfg_pri_ch_idx_88xx(adapter, *(enum halmac_pri_ch_idx *)value);
+		break;
+	case HALMAC_HW_EN_BB_RF:
+		enable_bb_rf_88xx(adapter, *(u8 *)value);
+		break;
+#if HALMAC_SDIO_SUPPORT
+	case HALMAC_HW_SDIO_TX_PAGE_THRESHOLD:
+		if (adapter->intf == HALMAC_INTERFACE_SDIO) {
+			th_info = (struct halmac_tx_page_threshold_info *)value;
+			cfg_sdio_tx_page_threshold_88xx(adapter, th_info);
+		} else {
+			return HALMAC_RET_FAIL;
+		}
+		break;
+#endif
+	case HALMAC_HW_RX_SHIFT:
+		rx_shift_88xx(adapter, *(u8 *)value);
+		break;
+	case HALMAC_HW_TXDESC_CHECKSUM:
+		tx_desc_chksum_88xx(adapter, *(u8 *)value);
+		break;
+	case HALMAC_HW_RX_CLK_GATE:
+		rx_clk_gate_88xx(adapter, *(u8 *)value);
+		break;
+	case HALMAC_HW_FAST_EDCA:
+		fast_edca_cfg_88xx(adapter,
+				   (struct halmac_fast_edca_cfg *)value);
+		break;
+	case HALMAC_HW_RTS_FULL_BW:
+		rts_full_bw_88xx(adapter, *(u8 *)value);
+		break;
+	case HALMAC_HW_FREE_CNT_EN:
+		HALMAC_REG_W8_SET(REG_MISC_CTRL, BIT_EN_FREECNT);
+		break;
+	default:
+		return HALMAC_RET_PARA_NOT_SUPPORT;
+	}
+
+	PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
+
+	return HALMAC_RET_SUCCESS;
+}
+
+enum halmac_ret_status
+set_h2c_pkt_hdr_88xx(struct halmac_adapter *adapter, u8 *hdr,
+		     struct halmac_h2c_header_info *info, u16 *seq_num)
+{
+	u16 total_size;
+
+	PLTFM_MSG_TRACE("[TRACE]%s!!\n", __func__);
+
+	total_size = H2C_PKT_HDR_SIZE_88XX + info->content_size;
+	FW_OFFLOAD_H2C_SET_TOTAL_LEN(hdr, total_size);
+	FW_OFFLOAD_H2C_SET_SUB_CMD_ID(hdr, info->sub_cmd_id);
+
+	FW_OFFLOAD_H2C_SET_CATEGORY(hdr, 0x01);
+	FW_OFFLOAD_H2C_SET_CMD_ID(hdr, 0xFF);
+
+	PLTFM_MUTEX_LOCK(&adapter->h2c_seq_mutex);
+	FW_OFFLOAD_H2C_SET_SEQ_NUM(hdr, adapter->h2c_info.seq_num);
+	*seq_num = adapter->h2c_info.seq_num;
+	(adapter->h2c_info.seq_num)++;
+	PLTFM_MUTEX_UNLOCK(&adapter->h2c_seq_mutex);
+
+	if (info->ack == 1)
+		FW_OFFLOAD_H2C_SET_ACK(hdr, 1);
+
+	return HALMAC_RET_SUCCESS;
+}
+
+enum halmac_ret_status
+send_h2c_pkt_88xx(struct halmac_adapter *adapter, u8 *pkt)
+{
+	u32 cnt = 100;
+	enum halmac_ret_status status = HALMAC_RET_SUCCESS;
+
+	while (adapter->h2c_info.buf_fs <= H2C_PKT_SIZE_88XX) {
+		get_h2c_buf_free_space_88xx(adapter);
+		cnt--;
+		if (cnt == 0) {
+			PLTFM_MSG_ERR("[ERR]h2c free space!!\n");
+			return HALMAC_RET_H2C_SPACE_FULL;
+		}
+	}
+
+	cnt = 100;
+	do {
+		if (PLTFM_SEND_H2C_PKT(pkt, H2C_PKT_SIZE_88XX) == 1)
+			break;
+		cnt--;
+		if (cnt == 0) {
+			PLTFM_MSG_ERR("[ERR]pltfm - sned h2c pkt!!\n");
+			return HALMAC_RET_SEND_H2C_FAIL;
+		}
+		PLTFM_DELAY_US(5);
+
+	} while (1);
+
+	adapter->h2c_info.buf_fs -= H2C_PKT_SIZE_88XX;
+
+	return status;
+}
+
+enum halmac_ret_status
+get_h2c_buf_free_space_88xx(struct halmac_adapter *adapter)
+{
+	u32 hw_wptr;
+	u32 fw_rptr;
+	struct halmac_h2c_info *info = &adapter->h2c_info;
+	struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
+
+	hw_wptr = HALMAC_REG_R32(REG_H2C_PKT_WRITEADDR) & 0x3FFFF;
+	fw_rptr = HALMAC_REG_R32(REG_H2C_PKT_READADDR) & 0x3FFFF;
+
+	if (hw_wptr >= fw_rptr)
+		info->buf_fs = info->buf_size - (hw_wptr - fw_rptr);
+	else
+		info->buf_fs = fw_rptr - hw_wptr;
+
+	return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * get_c2h_info_88xx() - process halmac C2H packet
+ * @adapter : the adapter of halmac
+ * @buf : RX Packet pointer
+ * @size : RX Packet size
+ *
+ * Note : Don't use any IO or DELAY in this API
+ *
+ * Author : KaiYuan Chang/Ivan Lin
+ *
+ * Used to process c2h packet info from RX path. After receiving the packet,
+ * user need to call this api and pass the packet pointer.
+ *
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+get_c2h_info_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size)
+{
+	enum halmac_ret_status status = HALMAC_RET_SUCCESS;
+
+	if (GET_RX_DESC_C2H(buf) == 1) {
+		PLTFM_MSG_TRACE("[TRACE]Parse c2h pkt\n");
+
+		status = parse_c2h_pkt_88xx(adapter, buf, size);
+		if (status != HALMAC_RET_SUCCESS) {
+			PLTFM_MSG_ERR("[ERR]Parse c2h pkt\n");
+			return status;
+		}
+	}
+
+	return HALMAC_RET_SUCCESS;
+}
+
+static enum halmac_ret_status
+parse_c2h_pkt_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size)
+{
+	u8 cmd_id;
+	u8 sub_cmd_id;
+	u8 *c2h_pkt = buf + adapter->hw_cfg_info.rxdesc_size;
+	u32 c2h_size = size - adapter->hw_cfg_info.rxdesc_size;
+	enum halmac_ret_status status = HALMAC_RET_SUCCESS;
+
+	cmd_id = (u8)C2H_HDR_GET_CMD_ID(c2h_pkt);
+
+	if (cmd_id != 0xFF) {
+		PLTFM_MSG_TRACE("[TRACE]Not 0xFF cmd!!\n");
+		return HALMAC_RET_C2H_NOT_HANDLED;
+	}
+
+	sub_cmd_id = (u8)C2H_HDR_GET_C2H_SUB_CMD_ID(c2h_pkt);
+
+	switch (sub_cmd_id) {
+	case C2H_SUB_CMD_ID_C2H_DBG:
+		status = get_c2h_dbg_88xx(adapter, c2h_pkt, c2h_size);
+		break;
+	case C2H_SUB_CMD_ID_H2C_ACK_HDR:
+		status = get_h2c_ack_88xx(adapter, c2h_pkt, c2h_size);
+		break;
+	case C2H_SUB_CMD_ID_BT_COEX_INFO:
+		status = HALMAC_RET_C2H_NOT_HANDLED;
+		break;
+	case C2H_SUB_CMD_ID_SCAN_STATUS_RPT:
+		status = get_scan_rpt_88xx(adapter, c2h_pkt, c2h_size);
+		break;
+	case C2H_SUB_CMD_ID_PSD_DATA:
+		status = get_psd_data_88xx(adapter, c2h_pkt, c2h_size);
+		break;
+	case C2H_SUB_CMD_ID_EFUSE_DATA:
+		status = get_efuse_data_88xx(adapter, c2h_pkt, c2h_size);
+		break;
+	default:
+		PLTFM_MSG_WARN("[WARN]Sub cmd id!!\n");
+		status = HALMAC_RET_C2H_NOT_HANDLED;
+		break;
+	}
+
+	return status;
+}
+
+static enum halmac_ret_status
+get_c2h_dbg_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size)
+{
+	u8 i;
+	u8 next_msg = 0;
+	u8 cur_msg = 0;
+	u8 msg_len = 0;
+	char *c2h_buf = (char *)NULL;
+	u8 content_len = 0;
+	u8 seq_num = 0;
+
+	content_len = (u8)C2H_HDR_GET_LEN((u8 *)buf);
+
+	if (content_len > C2H_DBG_CONTENT_MAX_LENGTH) {
+		PLTFM_MSG_ERR("[ERR]c2h size > max len!\n");
+		return HALMAC_RET_C2H_NOT_HANDLED;
+	}
+
+	for (i = 0; i < content_len; i++) {
+		if (*(buf + C2H_DBG_HDR_LEN + i) == '\n') {
+			if ((*(buf + C2H_DBG_HDR_LEN + i + 1) == '\0') ||
+			    (*(buf + C2H_DBG_HDR_LEN + i + 1) == 0xff)) {
+				next_msg = C2H_DBG_HDR_LEN + i + 1;
+				goto _ENDFOUND;
+			}
+		}
+	}
+
+_ENDFOUND:
+	msg_len = next_msg - C2H_DBG_HDR_LEN;
+
+	c2h_buf = (char *)PLTFM_MALLOC(msg_len);
+	if (!c2h_buf)
+		return HALMAC_RET_MALLOC_FAIL;
+
+	PLTFM_MEMCPY(c2h_buf, buf + C2H_DBG_HDR_LEN, msg_len);
+
+	seq_num = (u8)(*(c2h_buf));
+	*(c2h_buf + msg_len - 1) = '\0';
+	PLTFM_MSG_ALWAYS("[RTKFW, SEQ=%d]: %s\n",
+			 seq_num, (char *)(c2h_buf + 1));
+	PLTFM_FREE(c2h_buf, msg_len);
+
+	while (*(buf + next_msg) != '\0') {
+		cur_msg = next_msg;
+
+		msg_len = (u8)(*(buf + cur_msg + 3)) - 1;
+		next_msg += C2H_DBG_HDR_LEN + msg_len;
+
+		c2h_buf = (char *)PLTFM_MALLOC(msg_len);
+		if (!c2h_buf)
+			return HALMAC_RET_MALLOC_FAIL;
+
+		PLTFM_MEMCPY(c2h_buf, buf + cur_msg + C2H_DBG_HDR_LEN, msg_len);
+		*(c2h_buf + msg_len - 1) = '\0';
+		seq_num = (u8)(*(c2h_buf));
+		PLTFM_MSG_ALWAYS("[RTKFW, SEQ=%d]: %s\n",
+				 seq_num, (char *)(c2h_buf + 1));
+		PLTFM_FREE(c2h_buf, msg_len);
+	}
+
+	return HALMAC_RET_SUCCESS;
+}
+
+static enum halmac_ret_status
+get_h2c_ack_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size)
+{
+	u8 cmd_id;
+	u8 sub_cmd_id;
+	u8 fw_rc;
+	enum halmac_ret_status status = HALMAC_RET_SUCCESS;
+
+	PLTFM_MSG_TRACE("[TRACE]Ack for C2H!!\n");
+
+	fw_rc = (u8)H2C_ACK_HDR_GET_H2C_RETURN_CODE(buf);
+	if (HALMAC_H2C_RETURN_SUCCESS != (enum halmac_h2c_return_code)fw_rc)
+		PLTFM_MSG_TRACE("[TRACE]fw rc = %d\n", fw_rc);
+
+	cmd_id = (u8)H2C_ACK_HDR_GET_H2C_CMD_ID(buf);
+
+	if (cmd_id != 0xFF) {
+		PLTFM_MSG_ERR("[ERR]h2c ack cmd id!!\n");
+		return HALMAC_RET_C2H_NOT_HANDLED;
+	}
+
+	sub_cmd_id = (u8)H2C_ACK_HDR_GET_H2C_SUB_CMD_ID(buf);
+
+	switch (sub_cmd_id) {
+	case H2C_SUB_CMD_ID_DUMP_PHYSICAL_EFUSE_ACK:
+		status = get_h2c_ack_phy_efuse_88xx(adapter, buf, size);
+		break;
+	case H2C_SUB_CMD_ID_CFG_PARAM_ACK:
+		status = get_h2c_ack_cfg_param_88xx(adapter, buf, size);
+		break;
+	case H2C_SUB_CMD_ID_UPDATE_PKT_ACK:
+		status = get_h2c_ack_update_pkt_88xx(adapter, buf, size);
+		break;
+	case H2C_SUB_CMD_ID_UPDATE_DATAPACK_ACK:
+		status = get_h2c_ack_update_datapkt_88xx(adapter, buf, size);
+		break;
+	case H2C_SUB_CMD_ID_RUN_DATAPACK_ACK:
+		status = get_h2c_ack_run_datapkt_88xx(adapter, buf, size);
+		break;
+	case H2C_SUB_CMD_ID_CH_SWITCH_ACK:
+		status = get_h2c_ack_ch_switch_88xx(adapter, buf, size);
+		break;
+	case H2C_SUB_CMD_ID_IQK_ACK:
+		status = get_h2c_ack_iqk_88xx(adapter, buf, size);
+		break;
+	case H2C_SUB_CMD_ID_PWR_TRK_ACK:
+		status = get_h2c_ack_pwr_trk_88xx(adapter, buf, size);
+		break;
+	case H2C_SUB_CMD_ID_PSD_ACK:
+		break;
+	case H2C_SUB_CMD_ID_FW_SNDING_ACK:
+		status = get_h2c_ack_fw_snding_88xx(adapter, buf, size);
+		break;
+	default:
+		status = HALMAC_RET_C2H_NOT_HANDLED;
+		break;
+	}
+
+	return status;
+}
+
+static enum halmac_ret_status
+get_scan_rpt_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size)
+{
+	u8 fw_rc;
+	enum halmac_cmd_process_status proc_status;
+
+	fw_rc = (u8)SCAN_STATUS_RPT_GET_H2C_RETURN_CODE(buf);
+	proc_status = (HALMAC_H2C_RETURN_SUCCESS ==
+		(enum halmac_h2c_return_code)fw_rc) ?
+		HALMAC_CMD_PROCESS_DONE : HALMAC_CMD_PROCESS_ERROR;
+
+	PLTFM_EVENT_SIG(HALMAC_FEATURE_CHANNEL_SWITCH, proc_status, NULL, 0);
+
+	adapter->halmac_state.scan_state.proc_status = proc_status;
+
+	PLTFM_MSG_TRACE("[TRACE]scan : %X\n", proc_status);
+
+	return HALMAC_RET_SUCCESS;
+}
+
+static enum halmac_ret_status
+get_h2c_ack_cfg_param_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size)
+{
+	u8 seq_num;
+	u8 fw_rc;
+	u32 offset_accum;
+	u32 value_accum;
+	struct halmac_cfg_param_state *state =
+		&adapter->halmac_state.cfg_param_state;
+	enum halmac_cmd_process_status proc_status =
+		HALMAC_CMD_PROCESS_UNDEFINE;
+
+	seq_num = (u8)H2C_ACK_HDR_GET_H2C_SEQ(buf);
+	PLTFM_MSG_TRACE("[TRACE]Seq num : h2c->%d c2h->%d\n",
+			state->seq_num, seq_num);
+	if (seq_num != state->seq_num) {
+		PLTFM_MSG_ERR("[ERR]Seq num mismatch : h2c->%d c2h->%d\n",
+			      state->seq_num, seq_num);
+		return HALMAC_RET_SUCCESS;
+	}
+
+	if (state->proc_status != HALMAC_CMD_PROCESS_SENDING) {
+		PLTFM_MSG_ERR("[ERR]not cmd sending\n");
+		return HALMAC_RET_SUCCESS;
+	}
+
+	fw_rc = (u8)H2C_ACK_HDR_GET_H2C_RETURN_CODE(buf);
+	state->fw_rc = fw_rc;
+	offset_accum = CFG_PARAM_ACK_GET_OFFSET_ACCUMULATION(buf);
+	value_accum = CFG_PARAM_ACK_GET_VALUE_ACCUMULATION(buf);
+
+	if (offset_accum != adapter->cfg_param_info.offset_accum ||
+	    value_accum != adapter->cfg_param_info.value_accum) {
+		PLTFM_MSG_ERR("[ERR][C2H]offset_accu : %x, value_accu : %xn",
+			      offset_accum, value_accum);
+		PLTFM_MSG_ERR("[ERR][Ada]offset_accu : %x, value_accu : %x\n",
+			      adapter->cfg_param_info.offset_accum,
+			      adapter->cfg_param_info.value_accum);
+		proc_status = HALMAC_CMD_PROCESS_ERROR;
+	}
+
+	if ((enum halmac_h2c_return_code)fw_rc == HALMAC_H2C_RETURN_SUCCESS &&
+	    proc_status != HALMAC_CMD_PROCESS_ERROR) {
+		proc_status = HALMAC_CMD_PROCESS_DONE;
+		state->proc_status = proc_status;
+		PLTFM_EVENT_SIG(HALMAC_FEATURE_CFG_PARA, proc_status, NULL, 0);
+	} else {
+		proc_status = HALMAC_CMD_PROCESS_ERROR;
+		state->proc_status = proc_status;
+		PLTFM_EVENT_SIG(HALMAC_FEATURE_CFG_PARA, proc_status,
+				&fw_rc, 1);
+	}
+
+	return HALMAC_RET_SUCCESS;
+}
+
+static enum halmac_ret_status
+get_h2c_ack_update_pkt_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size)
+{
+	u8 seq_num;
+	u8 fw_rc;
+	struct halmac_update_pkt_state *state =
+		&adapter->halmac_state.update_pkt_state;
+	enum halmac_cmd_process_status proc_status;
+
+	seq_num = (u8)H2C_ACK_HDR_GET_H2C_SEQ(buf);
+	PLTFM_MSG_TRACE("[TRACE]Seq num : h2c->%d c2h->%d\n",
+			state->seq_num, seq_num);
+	if (seq_num != state->seq_num) {
+		PLTFM_MSG_ERR("[ERR]Seq num mismatch : h2c->%d c2h->%d\n",
+			      state->seq_num, seq_num);
+		return HALMAC_RET_SUCCESS;
+	}
+
+	if (state->proc_status != HALMAC_CMD_PROCESS_SENDING) {
+		PLTFM_MSG_ERR("[ERR]not cmd sending\n");
+		return HALMAC_RET_SUCCESS;
+	}
+
+	fw_rc = (u8)H2C_ACK_HDR_GET_H2C_RETURN_CODE(buf);
+	state->fw_rc = fw_rc;
+
+	if (HALMAC_H2C_RETURN_SUCCESS == (enum halmac_h2c_return_code)fw_rc) {
+		proc_status = HALMAC_CMD_PROCESS_DONE;
+		state->proc_status = proc_status;
+		PLTFM_EVENT_SIG(HALMAC_FEATURE_UPDATE_PACKET, proc_status,
+				NULL, 0);
+	} else {
+		proc_status = HALMAC_CMD_PROCESS_ERROR;
+		state->proc_status = proc_status;
+		PLTFM_EVENT_SIG(HALMAC_FEATURE_UPDATE_PACKET, proc_status,
+				&state->fw_rc, 1);
+	}
+
+	return HALMAC_RET_SUCCESS;
+}
+
+static enum halmac_ret_status
+get_h2c_ack_update_datapkt_88xx(struct halmac_adapter *adapter, u8 *buf,
+				u32 size)
+{
+	return HALMAC_RET_NOT_SUPPORT;
+}
+
+static enum halmac_ret_status
+get_h2c_ack_run_datapkt_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size)
+{
+	return HALMAC_RET_NOT_SUPPORT;
+}
+
+static enum halmac_ret_status
+get_h2c_ack_ch_switch_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size)
+{
+	u8 seq_num;
+	u8 fw_rc;
+	struct halmac_scan_state *state = &adapter->halmac_state.scan_state;
+	enum halmac_cmd_process_status proc_status;
+
+	seq_num = (u8)H2C_ACK_HDR_GET_H2C_SEQ(buf);
+	PLTFM_MSG_TRACE("[TRACE]Seq num : h2c->%d c2h->%d\n",
+			state->seq_num, seq_num);
+	if (seq_num != state->seq_num) {
+		PLTFM_MSG_ERR("[ERR]Seq num mismatch : h2c->%d c2h->%d\n",
+			      state->seq_num, seq_num);
+		return HALMAC_RET_SUCCESS;
+	}
+
+	if (state->proc_status != HALMAC_CMD_PROCESS_SENDING) {
+		PLTFM_MSG_ERR("[ERR]not cmd sending\n");
+		return HALMAC_RET_SUCCESS;
+	}
+
+	fw_rc = (u8)H2C_ACK_HDR_GET_H2C_RETURN_CODE(buf);
+	state->fw_rc = fw_rc;
+
+	if ((enum halmac_h2c_return_code)fw_rc == HALMAC_H2C_RETURN_SUCCESS) {
+		proc_status = HALMAC_CMD_PROCESS_RCVD;
+		state->proc_status = proc_status;
+		PLTFM_EVENT_SIG(HALMAC_FEATURE_CHANNEL_SWITCH, proc_status,
+				NULL, 0);
+	} else {
+		proc_status = HALMAC_CMD_PROCESS_ERROR;
+		state->proc_status = proc_status;
+		PLTFM_EVENT_SIG(HALMAC_FEATURE_CHANNEL_SWITCH, proc_status,
+				&fw_rc, 1);
+	}
+
+	return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * mac_debug_88xx_v1() - read some registers for debug
+ * @adapter
+ * Author : KaiYuan Chang/Ivan Lin
+ * Return : enum halmac_ret_status
+ */
+enum halmac_ret_status
+mac_debug_88xx(struct halmac_adapter *adapter)
+{
+	PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
+
+	if (adapter->intf == HALMAC_INTERFACE_SDIO)
+		dump_reg_sdio_88xx(adapter);
+	else
+		dump_reg_88xx(adapter);
+
+	PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
+
+	return HALMAC_RET_SUCCESS;
+}
+
+static void
+dump_reg_sdio_88xx(struct halmac_adapter *adapter)
+{
+	u8 tmp8;
+	u32 i;
+
+	/* Dump CCCR, it needs new platform api */
+
+	/*Dump SDIO Local Register, use CMD52*/
+	for (i = 0x10250000; i < 0x102500ff; i++) {
+		tmp8 = PLTFM_SDIO_CMD52_R(i);
+		PLTFM_MSG_TRACE("[TRACE]dbg-sdio[%x]=%x\n", i, tmp8);
+	}
+
+	/*Dump MAC Register*/
+	for (i = 0x0000; i < 0x17ff; i++) {
+		tmp8 = PLTFM_SDIO_CMD52_R(i);
+		PLTFM_MSG_TRACE("[TRACE]dbg-mac[%x]=%x\n", i, tmp8);
+	}
+
+	tmp8 = PLTFM_SDIO_CMD52_R(REG_SDIO_CRC_ERR_IDX);
+	if (tmp8)
+		PLTFM_MSG_ERR("[ERR]sdio crc=%x\n", tmp8);
+
+	/*Check RX Fifo status*/
+	i = REG_RXFF_PTR_V1;
+	tmp8 = PLTFM_SDIO_CMD52_R(i);
+	PLTFM_MSG_TRACE("[TRACE]dbg-mac[%x]=%x\n", i, tmp8);
+	i = REG_RXFF_WTR_V1;
+	tmp8 = PLTFM_SDIO_CMD52_R(i);
+	PLTFM_MSG_TRACE("[TRACE]dbg-mac[%x]=%x\n", i, tmp8);
+	i = REG_RXFF_PTR_V1;
+	tmp8 = PLTFM_SDIO_CMD52_R(i);
+	PLTFM_MSG_TRACE("[TRACE]dbg-mac[%x]=%x\n", i, tmp8);
+	i = REG_RXFF_WTR_V1;
+	tmp8 = PLTFM_SDIO_CMD52_R(i);
+	PLTFM_MSG_TRACE("[TRACE]dbg-mac[%x]=%x\n", i, tmp8);
+}
+
+static void
+dump_reg_88xx(struct halmac_adapter *adapter)
+{
+	u32 tmp32;
+	u32 i;
+	struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
+
+	/*Dump MAC Register*/
+	for (i = 0x0000; i < 0x17fc; i += 4) {
+		tmp32 = HALMAC_REG_R32(i);
+		PLTFM_MSG_TRACE("[TRACE]dbg-mac[%x]=%x\n", i, tmp32);
+	}
+
+	/*Check RX Fifo status*/
+	i = REG_RXFF_PTR_V1;
+	tmp32 = HALMAC_REG_R32(i);
+	PLTFM_MSG_TRACE("[TRACE]dbg-mac[%x]=%x\n", i, tmp32);
+	i = REG_RXFF_WTR_V1;
+	tmp32 = HALMAC_REG_R32(i);
+	PLTFM_MSG_TRACE("[TRACE]dbg-mac[%x]=%x\n", i, tmp32);
+	i = REG_RXFF_PTR_V1;
+	tmp32 = HALMAC_REG_R32(i);
+	PLTFM_MSG_TRACE("[TRACE]dbg-mac[%x]=%x\n", i, tmp32);
+	i = REG_RXFF_WTR_V1;
+	tmp32 = HALMAC_REG_R32(i);
+	PLTFM_MSG_TRACE("[TRACE]dbg-mac[%x]=%x\n", i, tmp32);
+}
+
+/**
+ * cfg_parameter_88xx() - config parameter by FW
+ * @adapter : the adapter of halmac
+ * @info : cmd id, content
+ * @full_fifo : parameter information
+ *
+ * If msk_en = 1, the format of array is {reg_info, mask, value}.
+ * If msk_en =_FAUSE, the format of array is {reg_info, value}
+ * The format of reg_info is
+ * reg_info[31]=rf_reg, 0: MAC_BB reg, 1: RF reg
+ * reg_info[27:24]=rf_path, 0: path_A, 1: path_B
+ * if rf_reg=0(MAC_BB reg), rf_path is meaningless.
+ * ref_info[15:0]=offset
+ *
+ * Example: msk_en = 0
+ * {0x8100000a, 0x00001122}
+ * =>Set RF register, path_B, offset 0xA to 0x00001122
+ * {0x00000824, 0x11224433}
+ * =>Set MAC_BB register, offset 0x800 to 0x11224433
+ *
+ * Note : full fifo mode only for init flow
+ *
+ * Author : KaiYuan Chang/Ivan Lin
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+cfg_parameter_88xx(struct halmac_adapter *adapter,
+		   struct halmac_phy_parameter_info *info, u8 full_fifo)
+{
+	enum halmac_ret_status status = HALMAC_RET_SUCCESS;
+	enum halmac_cmd_process_status *proc_status;
+	enum halmac_cmd_construct_state cmd_state;
+
+	proc_status = &adapter->halmac_state.cfg_param_state.proc_status;
+
+	if (halmac_fw_validate(adapter) != HALMAC_RET_SUCCESS)
+		return HALMAC_RET_NO_DLFW;
+
+	if (adapter->fw_ver.h2c_version < 4)
+		return HALMAC_RET_FW_NO_SUPPORT;
+
+	if (*proc_status == HALMAC_CMD_PROCESS_SENDING) {
+		PLTFM_MSG_TRACE("[TRACE]Wait event(para)\n");
+		return HALMAC_RET_BUSY_STATE;
+	}
+
+	cmd_state = cfg_param_cmd_cnstr_state_88xx(adapter);
+	if (cmd_state != HALMAC_CMD_CNSTR_IDLE &&
+	    cmd_state != HALMAC_CMD_CNSTR_CNSTR) {
+		PLTFM_MSG_TRACE("[TRACE]Not idle(para)\n");
+		return HALMAC_RET_BUSY_STATE;
+	}
+
+	*proc_status = HALMAC_CMD_PROCESS_IDLE;
+
+	status = proc_cfg_param_88xx(adapter, info, full_fifo);
+
+	if (status != HALMAC_RET_SUCCESS && status != HALMAC_RET_PARA_SENDING) {
+		PLTFM_MSG_ERR("[ERR]send param h2c\n");
+		return status;
+	}
+
+	return status;
+}
+
+static enum halmac_cmd_construct_state
+cfg_param_cmd_cnstr_state_88xx(struct halmac_adapter *adapter)
+{
+	return adapter->halmac_state.cfg_param_state.cmd_cnstr_state;
+}
+
+static enum halmac_ret_status
+proc_cfg_param_88xx(struct halmac_adapter *adapter,
+		    struct halmac_phy_parameter_info *param, u8 full_fifo)
+{
+	u8 end_cmd = 0;
+	u32 rsvd_size;
+	enum halmac_ret_status status = HALMAC_RET_SUCCESS;
+	struct halmac_cfg_param_info *info = &adapter->cfg_param_info;
+	enum halmac_cmd_process_status *proc_status;
+
+	proc_status = &adapter->halmac_state.cfg_param_state.proc_status;
+
+	status = malloc_cfg_param_buf_88xx(adapter, full_fifo);
+	if (status != HALMAC_RET_SUCCESS)
+		return status;
+
+	if (cnv_cfg_param_state_88xx(adapter, HALMAC_CMD_CNSTR_CNSTR) !=
+	    HALMAC_RET_SUCCESS) {
+		PLTFM_FREE(info->buf, info->buf_size);
+		info->buf = NULL;
+		info->buf_wptr = NULL;
+		return HALMAC_RET_ERROR_STATE;
+	}
+
+	add_param_buf_88xx(adapter, param, info->buf_wptr, &end_cmd);
+	if (param->cmd_id != HALMAC_PARAMETER_CMD_END) {
+		info->num++;
+		info->buf_wptr += CFG_PARAM_H2C_INFO_SIZE;
+		info->avl_buf_size -= CFG_PARAM_H2C_INFO_SIZE;
+	}
+
+	rsvd_size = info->avl_buf_size - adapter->hw_cfg_info.txdesc_size;
+	if (rsvd_size > CFG_PARAM_H2C_INFO_SIZE && end_cmd == 0)
+		return HALMAC_RET_SUCCESS;
+
+	if (info->num == 0) {
+		PLTFM_FREE(info->buf, info->buf_size);
+		info->buf = NULL;
+		info->buf_wptr = NULL;
+		PLTFM_MSG_TRACE("[TRACE]param num = 0!!\n");
+
+		*proc_status = HALMAC_CMD_PROCESS_DONE;
+		PLTFM_EVENT_SIG(HALMAC_FEATURE_CFG_PARA, *proc_status, NULL, 0);
+
+		reset_ofld_feature_88xx(adapter, HALMAC_FEATURE_CFG_PARA);
+
+		return HALMAC_RET_SUCCESS;
+	}
+
+	status = send_cfg_param_h2c_88xx(adapter);
+	if (status != HALMAC_RET_SUCCESS) {
+		if (info->buf) {
+			PLTFM_FREE(info->buf, info->buf_size);
+			info->buf = NULL;
+			info->buf_wptr = NULL;
+		}
+		return status;
+	}
+
+	if (end_cmd == 0) {
+		PLTFM_MSG_TRACE("[TRACE]send h2c-buf full\n");
+		return HALMAC_RET_PARA_SENDING;
+	}
+
+	return status;
+}
+
+static enum halmac_ret_status
+send_cfg_param_h2c_88xx(struct halmac_adapter *adapter)
+{
+	u8 h2c_buf[H2C_PKT_SIZE_88XX] = { 0 };
+	u16 pg_addr;
+	u16 seq_num = 0;
+	u32 info_size;
+	struct halmac_h2c_header_info hdr_info;
+	enum halmac_ret_status status = HALMAC_RET_SUCCESS;
+	struct halmac_cfg_param_info *info = &adapter->cfg_param_info;
+	enum halmac_cmd_process_status *proc_status;
+
+	proc_status = &adapter->halmac_state.cfg_param_state.proc_status;
+
+	if (cnv_cfg_param_state_88xx(adapter, HALMAC_CMD_CNSTR_H2C_SENT) !=
+	    HALMAC_RET_SUCCESS)
+		return HALMAC_RET_ERROR_STATE;
+
+	*proc_status = HALMAC_CMD_PROCESS_SENDING;
+
+	if (info->full_fifo_mode == 1)
+		pg_addr = 0;
+	else
+		pg_addr = adapter->txff_alloc.rsvd_h2c_info_addr;
+
+	info_size = info->num * CFG_PARAM_H2C_INFO_SIZE;
+
+	status = dl_rsvd_page_88xx(adapter, pg_addr, info->buf, info_size);
+	if (status != HALMAC_RET_SUCCESS) {
+		PLTFM_MSG_ERR("[ERR]dl rsvd pg!!\n");
+		goto CFG_PARAM_H2C_FAIL;
+	}
+
+	gen_cfg_param_h2c_88xx(adapter, h2c_buf);
+
+	hdr_info.sub_cmd_id = SUB_CMD_ID_CFG_PARAM;
+	hdr_info.content_size = 4;
+	hdr_info.ack = 1;
+	set_h2c_pkt_hdr_88xx(adapter, h2c_buf, &hdr_info, &seq_num);
+
+	adapter->halmac_state.cfg_param_state.seq_num = seq_num;
+
+	status = send_h2c_pkt_88xx(adapter, h2c_buf);
+
+	if (status != HALMAC_RET_SUCCESS) {
+		PLTFM_MSG_ERR("[ERR]send h2c!!\n");
+		reset_ofld_feature_88xx(adapter, HALMAC_FEATURE_CFG_PARA);
+	}
+
+CFG_PARAM_H2C_FAIL:
+	PLTFM_FREE(info->buf, info->buf_size);
+	info->buf = NULL;
+	info->buf_wptr = NULL;
+
+	if (cnv_cfg_param_state_88xx(adapter, HALMAC_CMD_CNSTR_IDLE) !=
+	    HALMAC_RET_SUCCESS)
+		return HALMAC_RET_ERROR_STATE;
+
+	return status;
+}
+
+static enum halmac_ret_status
+cnv_cfg_param_state_88xx(struct halmac_adapter *adapter,
+			 enum halmac_cmd_construct_state dest_state)
+{
+	enum halmac_cmd_construct_state *state;
+
+	state = &adapter->halmac_state.cfg_param_state.cmd_cnstr_state;
+
+	if ((*state != HALMAC_CMD_CNSTR_IDLE) &&
+	    (*state != HALMAC_CMD_CNSTR_CNSTR) &&
+	    (*state != HALMAC_CMD_CNSTR_H2C_SENT))
+		return HALMAC_RET_ERROR_STATE;
+
+	if (dest_state == HALMAC_CMD_CNSTR_IDLE) {
+		if (*state == HALMAC_CMD_CNSTR_CNSTR)
+			return HALMAC_RET_ERROR_STATE;
+	} else if (dest_state == HALMAC_CMD_CNSTR_CNSTR) {
+		if (*state == HALMAC_CMD_CNSTR_H2C_SENT)
+			return HALMAC_RET_ERROR_STATE;
+	} else if (dest_state == HALMAC_CMD_CNSTR_H2C_SENT) {
+		if ((*state == HALMAC_CMD_CNSTR_IDLE) ||
+		    (*state == HALMAC_CMD_CNSTR_H2C_SENT))
+			return HALMAC_RET_ERROR_STATE;
+	}
+
+	*state = dest_state;
+
+	return HALMAC_RET_SUCCESS;
+}
+
+static enum halmac_ret_status
+add_param_buf_88xx(struct halmac_adapter *adapter,
+		   struct halmac_phy_parameter_info *param, u8 *buf,
+		   u8 *end_cmd)
+{
+	struct halmac_cfg_param_info *info = &adapter->cfg_param_info;
+	union halmac_parameter_content *content = &param->content;
+
+	*end_cmd = 0;
+
+	PARAM_INFO_SET_LEN(buf, CFG_PARAM_H2C_INFO_SIZE);
+	PARAM_INFO_SET_IO_CMD(buf, param->cmd_id);
+
+	switch (param->cmd_id) {
+	case HALMAC_PARAMETER_CMD_BB_W8:
+	case HALMAC_PARAMETER_CMD_BB_W16:
+	case HALMAC_PARAMETER_CMD_BB_W32:
+	case HALMAC_PARAMETER_CMD_MAC_W8:
+	case HALMAC_PARAMETER_CMD_MAC_W16:
+	case HALMAC_PARAMETER_CMD_MAC_W32:
+		PARAM_INFO_SET_IO_ADDR(buf, content->MAC_REG_W.offset);
+		PARAM_INFO_SET_DATA(buf, content->MAC_REG_W.value);
+		PARAM_INFO_SET_MASK(buf, content->MAC_REG_W.msk);
+		PARAM_INFO_SET_MSK_EN(buf, content->MAC_REG_W.msk_en);
+		info->value_accum += content->MAC_REG_W.value;
+		info->offset_accum += content->MAC_REG_W.offset;
+		break;
+	case HALMAC_PARAMETER_CMD_RF_W:
+		/*In rf register, the address is only 1 byte*/
+		PARAM_INFO_SET_RF_ADDR(buf, content->RF_REG_W.offset);
+		PARAM_INFO_SET_RF_PATH(buf, content->RF_REG_W.rf_path);
+		PARAM_INFO_SET_DATA(buf, content->RF_REG_W.value);
+		PARAM_INFO_SET_MASK(buf, content->RF_REG_W.msk);
+		PARAM_INFO_SET_MSK_EN(buf, content->RF_REG_W.msk_en);
+		info->value_accum += content->RF_REG_W.value;
+		info->offset_accum += (content->RF_REG_W.offset +
+					(content->RF_REG_W.rf_path << 8));
+		break;
+	case HALMAC_PARAMETER_CMD_DELAY_US:
+	case HALMAC_PARAMETER_CMD_DELAY_MS:
+		PARAM_INFO_SET_DELAY_VAL(buf, content->DELAY_TIME.delay_time);
+		break;
+	case HALMAC_PARAMETER_CMD_END:
+		*end_cmd = 1;
+		break;
+	default:
+		PLTFM_MSG_ERR("[ERR]cmd id!!\n");
+		break;
+	}
+
+	return HALMAC_RET_SUCCESS;
+}
+
+static enum halmac_ret_status
+gen_cfg_param_h2c_88xx(struct halmac_adapter *adapter, u8 *buff)
+{
+	struct halmac_cfg_param_info *info = &adapter->cfg_param_info;
+	u16 h2c_info_addr = adapter->txff_alloc.rsvd_h2c_info_addr;
+	u16 rsvd_pg_addr = adapter->txff_alloc.rsvd_boundary;
+
+	CFG_PARAM_SET_NUM(buff, info->num);
+
+	if (info->full_fifo_mode == 1) {
+		CFG_PARAM_SET_INIT_CASE(buff, 0x1);
+		CFG_PARAM_SET_LOC(buff, 0);
+	} else {
+		CFG_PARAM_SET_INIT_CASE(buff, 0x0);
+		CFG_PARAM_SET_LOC(buff, h2c_info_addr - rsvd_pg_addr);
+	}
+
+	return HALMAC_RET_SUCCESS;
+}
+
+static enum halmac_ret_status
+malloc_cfg_param_buf_88xx(struct halmac_adapter *adapter, u8 full_fifo)
+{
+	struct halmac_cfg_param_info *info = &adapter->cfg_param_info;
+	struct halmac_pltfm_cfg_info *pltfm_info = &adapter->pltfm_info;
+
+	if (info->buf)
+		return HALMAC_RET_SUCCESS;
+
+	if (full_fifo == 1)
+		info->buf_size = pltfm_info->malloc_size;
+	else
+		info->buf_size = CFG_PARAM_RSVDPG_SIZE;
+
+	if (info->buf_size > pltfm_info->rsvd_pg_size)
+		info->buf_size = pltfm_info->rsvd_pg_size;
+
+	info->buf = smart_malloc_88xx(adapter, info->buf_size, &info->buf_size);
+	if (info->buf) {
+		PLTFM_MEMSET(info->buf, 0x00, info->buf_size);
+		info->full_fifo_mode = full_fifo;
+		info->buf_wptr = info->buf;
+		info->num = 0;
+		info->avl_buf_size = info->buf_size;
+		info->value_accum = 0;
+		info->offset_accum = 0;
+	} else {
+		return HALMAC_RET_MALLOC_FAIL;
+	}
+
+	return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * update_packet_88xx() - send specific packet to FW
+ * @adapter : the adapter of halmac
+ * @pkt_id : packet id, to know the purpose of this packet
+ * @pkt : packet
+ * @size : packet size
+ *
+ * Note : TX_DESC is not included in the pkt
+ *
+ * Author : KaiYuan Chang/Ivan Lin
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+update_packet_88xx(struct halmac_adapter *adapter, enum halmac_packet_id pkt_id,
+		   u8 *pkt, u32 size)
+{
+	enum halmac_ret_status status = HALMAC_RET_SUCCESS;
+	enum halmac_cmd_process_status *proc_status =
+		&adapter->halmac_state.update_pkt_state.proc_status;
+
+	if (halmac_fw_validate(adapter) != HALMAC_RET_SUCCESS)
+		return HALMAC_RET_NO_DLFW;
+
+	if (adapter->fw_ver.h2c_version < 4)
+		return HALMAC_RET_FW_NO_SUPPORT;
+
+	if (size > UPDATE_PKT_RSVDPG_SIZE)
+		return HALMAC_RET_RSVD_PG_OVERFLOW_FAIL;
+
+	PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
+
+	if (*proc_status == HALMAC_CMD_PROCESS_SENDING) {
+		PLTFM_MSG_TRACE("[TRACE]Wait event(upd)\n");
+		return HALMAC_RET_BUSY_STATE;
+	}
+
+	*proc_status = HALMAC_CMD_PROCESS_SENDING;
+
+	status = send_h2c_update_packet_88xx(adapter, pkt_id, pkt, size);
+	if (status != HALMAC_RET_SUCCESS) {
+		PLTFM_MSG_ERR("[ERR]send h2c!!\n");
+		PLTFM_MSG_ERR("[ERR]pkt id : %X!!\n", pkt_id);
+		return status;
+	}
+
+	PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
+
+	return HALMAC_RET_SUCCESS;
+}
+
+static enum halmac_ret_status
+send_h2c_update_packet_88xx(struct halmac_adapter *adapter,
+			    enum halmac_packet_id pkt_id, u8 *pkt, u32 size)
+{
+	u8 h2c_buf[H2C_PKT_SIZE_88XX] = { 0 };
+	u16 seq_num = 0;
+	u16 pg_addr = adapter->txff_alloc.rsvd_h2c_info_addr;
+	u16 pg_offset;
+	struct halmac_h2c_header_info hdr_info;
+	enum halmac_ret_status status = HALMAC_RET_SUCCESS;
+
+	status = dl_rsvd_page_88xx(adapter, pg_addr, pkt, size);
+	if (status != HALMAC_RET_SUCCESS) {
+		PLTFM_MSG_ERR("[ERR]dl rsvd pg!!\n");
+		return status;
+	}
+
+	pg_offset = pg_addr - adapter->txff_alloc.rsvd_boundary;
+	UPDATE_PKT_SET_SIZE(h2c_buf, size + adapter->hw_cfg_info.txdesc_size);
+	UPDATE_PKT_SET_ID(h2c_buf, pkt_id);
+	UPDATE_PKT_SET_LOC(h2c_buf, pg_offset);
+
+	hdr_info.sub_cmd_id = SUB_CMD_ID_UPDATE_PKT;
+	hdr_info.content_size = 8;
+	hdr_info.ack = 1;
+	set_h2c_pkt_hdr_88xx(adapter, h2c_buf, &hdr_info, &seq_num);
+	adapter->halmac_state.update_pkt_state.seq_num = seq_num;
+
+	status = send_h2c_pkt_88xx(adapter, h2c_buf);
+
+	if (status != HALMAC_RET_SUCCESS) {
+		PLTFM_MSG_ERR("[ERR]send h2c!!\n");
+		reset_ofld_feature_88xx(adapter, HALMAC_FEATURE_UPDATE_PACKET);
+		return status;
+	}
+
+	return status;
+}
+
+enum halmac_ret_status
+bcn_ie_filter_88xx(struct halmac_adapter *adapter,
+		   struct halmac_bcn_ie_info *info)
+{
+	return HALMAC_RET_NOT_SUPPORT;
+}
+
+enum halmac_ret_status
+update_datapack_88xx(struct halmac_adapter *adapter,
+		     enum halmac_data_type data_type,
+		     struct halmac_phy_parameter_info *info)
+{
+	return HALMAC_RET_NOT_SUPPORT;
+}
+
+enum halmac_ret_status
+run_datapack_88xx(struct halmac_adapter *adapter,
+		  enum halmac_data_type data_type)
+{
+	return HALMAC_RET_NOT_SUPPORT;
+}
+
+enum halmac_ret_status
+send_bt_coex_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size, u8 ack)
+{
+	enum halmac_ret_status status = HALMAC_RET_SUCCESS;
+
+	if (halmac_fw_validate(adapter) != HALMAC_RET_SUCCESS)
+		return HALMAC_RET_NO_DLFW;
+
+	PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
+
+	status = send_bt_coex_cmd_88xx(adapter, buf, size, ack);
+
+	if (status != HALMAC_RET_SUCCESS) {
+		PLTFM_MSG_ERR("[ERR]bt coex cmd!!\n");
+		return status;
+	}
+
+	PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
+
+	return HALMAC_RET_SUCCESS;
+}
+
+static enum halmac_ret_status
+send_bt_coex_cmd_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size,
+		      u8 ack)
+{
+	u8 h2c_buf[H2C_PKT_SIZE_88XX] = { 0 };
+	u16 seq_num = 0;
+	struct halmac_h2c_header_info hdr_info;
+	enum halmac_ret_status status = HALMAC_RET_SUCCESS;
+
+	PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
+
+	PLTFM_MEMCPY(h2c_buf + 8, buf, size);
+
+	hdr_info.sub_cmd_id = SUB_CMD_ID_BT_COEX;
+	hdr_info.content_size = (u16)size;
+	hdr_info.ack = ack;
+	set_h2c_pkt_hdr_88xx(adapter, h2c_buf, &hdr_info, &seq_num);
+
+	status = send_h2c_pkt_88xx(adapter, h2c_buf);
+
+	if (status != HALMAC_RET_SUCCESS) {
+		PLTFM_MSG_ERR("[ERR]send h2c!!\n");
+		return status;
+	}
+
+	return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * dump_fifo_88xx() - dump fifo data
+ * @adapter : the adapter of halmac
+ * @sel : FIFO selection
+ * @start_addr : start address of selected FIFO
+ * @size : dump size of selected FIFO
+ * @data : FIFO data
+ *
+ * Note : before dump fifo, user need to call halmac_get_fifo_size to
+ * get fifo size. Then input this size to halmac_dump_fifo.
+ *
+ * Author : Ivan Lin/KaiYuan Chang
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+dump_fifo_88xx(struct halmac_adapter *adapter, enum hal_fifo_sel sel,
+	       u32 start_addr, u32 size, u8 *data)
+{
+	enum halmac_ret_status status = HALMAC_RET_SUCCESS;
+	u8 tmp8;
+	u8 enable;
+	struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
+
+	PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
+
+	if (sel == HAL_FIFO_SEL_TX &&
+	    (start_addr + size) > adapter->hw_cfg_info.tx_fifo_size) {
+		PLTFM_MSG_ERR("[ERR]size overflow!!\n");
+		return HALMAC_RET_DUMP_FIFOSIZE_INCORRECT;
+	}
+
+	if (sel == HAL_FIFO_SEL_RX &&
+	    (start_addr + size) > adapter->hw_cfg_info.rx_fifo_size) {
+		PLTFM_MSG_ERR("[ERR]size overflow!!\n");
+		return HALMAC_RET_DUMP_FIFOSIZE_INCORRECT;
+	}
+
+	if ((size & (4 - 1)) != 0) {
+		PLTFM_MSG_ERR("[ERR]not 4byte alignment!!\n");
+		return HALMAC_RET_DUMP_FIFOSIZE_INCORRECT;
+	}
+
+	if (!data)
+		return HALMAC_RET_NULL_POINTER;
+
+	tmp8 = HALMAC_REG_R8(REG_RCR + 2);
+	enable = 0;
+	status = api->halmac_set_hw_value(adapter, HALMAC_HW_RX_CLK_GATE,
+					  &enable);
+	if (status != HALMAC_RET_SUCCESS)
+		return status;
+	status = read_buf_88xx(adapter, start_addr, size, sel, data);
+
+	HALMAC_REG_W8(REG_RCR + 2, tmp8);
+
+	if (status != HALMAC_RET_SUCCESS) {
+		PLTFM_MSG_ERR("[ERR]read buf!!\n");
+		return status;
+	}
+
+	PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
+
+	return HALMAC_RET_SUCCESS;
+}
+
+static enum halmac_ret_status
+read_buf_88xx(struct halmac_adapter *adapter, u32 offset, u32 size,
+	      enum hal_fifo_sel sel, u8 *data)
+{
+	u32 start_pg;
+	u32 value32;
+	u32 i;
+	u32 residue;
+	u32 cnt = 0;
+	struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
+
+	if (sel == HAL_FIFO_SEL_RSVD_PAGE)
+		offset += (adapter->txff_alloc.rsvd_boundary <<
+			   TX_PAGE_SIZE_SHIFT_88XX);
+
+	start_pg = offset >> 12;
+	residue = offset & (4096 - 1);
+
+	if (sel == HAL_FIFO_SEL_TX || sel == HAL_FIFO_SEL_RSVD_PAGE)
+		start_pg += 0x780;
+	else if (sel == HAL_FIFO_SEL_RX)
+		start_pg += 0x700;
+	else if (sel == HAL_FIFO_SEL_REPORT)
+		start_pg += 0x660;
+	else if (sel == HAL_FIFO_SEL_LLT)
+		start_pg += 0x650;
+	else if (sel == HAL_FIFO_SEL_RXBUF_FW)
+		start_pg += 0x680;
+	else
+		return HALMAC_RET_NOT_SUPPORT;
+
+	value32 = HALMAC_REG_R16(REG_PKTBUF_DBG_CTRL) & 0xF000;
+
+	do {
+		HALMAC_REG_W16(REG_PKTBUF_DBG_CTRL, (u16)(start_pg | value32));
+
+		for (i = 0x8000 + residue; i <= 0x8FFF; i += 4) {
+			*(u32 *)(data + cnt) = HALMAC_REG_R32(i);
+			*(u32 *)(data + cnt) =
+				rtk_le32_to_cpu(*(u32 *)(data + cnt));
+			cnt += 4;
+			if (size == cnt)
+				goto HALMAC_BUF_READ_OK;
+		}
+
+		residue = 0;
+		start_pg++;
+	} while (1);
+
+HALMAC_BUF_READ_OK:
+	HALMAC_REG_W16(REG_PKTBUF_DBG_CTRL, (u16)value32);
+
+	return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * get_fifo_size_88xx() - get fifo size
+ * @adapter : the adapter of halmac
+ * @sel : FIFO selection
+ * Author : Ivan Lin/KaiYuan Chang
+ * Return : u32
+ * More details of status code can be found in prototype document
+ */
+u32
+get_fifo_size_88xx(struct halmac_adapter *adapter, enum hal_fifo_sel sel)
+{
+	u32 size = 0;
+
+	if (sel == HAL_FIFO_SEL_TX)
+		size = adapter->hw_cfg_info.tx_fifo_size;
+	else if (sel == HAL_FIFO_SEL_RX)
+		size = adapter->hw_cfg_info.rx_fifo_size;
+	else if (sel == HAL_FIFO_SEL_RSVD_PAGE)
+		size = adapter->hw_cfg_info.tx_fifo_size -
+		       (adapter->txff_alloc.rsvd_boundary <<
+			TX_PAGE_SIZE_SHIFT_88XX);
+	else if (sel == HAL_FIFO_SEL_REPORT)
+		size = 65536;
+	else if (sel == HAL_FIFO_SEL_LLT)
+		size = 65536;
+	else if (sel == HAL_FIFO_SEL_RXBUF_FW)
+		size = RX_BUF_FW_88XX;
+
+	return size;
+}
+
+enum halmac_ret_status
+set_h2c_header_88xx(struct halmac_adapter *adapter, u8 *hdr, u16 *seq, u8 ack)
+{
+	PLTFM_MSG_TRACE("[TRACE]%s!!\n", __func__);
+
+	H2C_CMD_HEADER_SET_CATEGORY(hdr, 0x00);
+	H2C_CMD_HEADER_SET_TOTAL_LEN(hdr, 16);
+
+	PLTFM_MUTEX_LOCK(&adapter->h2c_seq_mutex);
+	H2C_CMD_HEADER_SET_SEQ_NUM(hdr, adapter->h2c_info.seq_num);
+	*seq = adapter->h2c_info.seq_num;
+	(adapter->h2c_info.seq_num)++;
+	PLTFM_MUTEX_UNLOCK(&adapter->h2c_seq_mutex);
+
+	if (ack == 1)
+		H2C_CMD_HEADER_SET_ACK(hdr, 1);
+
+	return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * add_ch_info_88xx() -add channel information
+ * @adapter : the adapter of halmac
+ * @info : channel information
+ * Author : KaiYuan Chang/Ivan Lin
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+add_ch_info_88xx(struct halmac_adapter *adapter, struct halmac_ch_info *info)
+{
+	struct halmac_ch_sw_info *ch_sw_info = &adapter->ch_sw_info;
+	enum halmac_cmd_construct_state state;
+
+	PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
+
+	if (adapter->halmac_state.dlfw_state != HALMAC_GEN_INFO_SENT) {
+		PLTFM_MSG_ERR("[ERR]gen info\n");
+		return HALMAC_RET_GEN_INFO_NOT_SENT;
+	}
+
+	state = scan_cmd_cnstr_state_88xx(adapter);
+	if (state != HALMAC_CMD_CNSTR_BUF_CLR &&
+	    state != HALMAC_CMD_CNSTR_CNSTR) {
+		PLTFM_MSG_WARN("[WARN]cmd state (scan)\n");
+		return HALMAC_RET_ERROR_STATE;
+	}
+
+	if (!ch_sw_info->buf) {
+		ch_sw_info->buf = (u8 *)PLTFM_MALLOC(SCAN_INFO_RSVDPG_SIZE);
+		if (!ch_sw_info->buf)
+			return HALMAC_RET_NULL_POINTER;
+		ch_sw_info->buf_wptr = ch_sw_info->buf;
+		ch_sw_info->buf_size = SCAN_INFO_RSVDPG_SIZE;
+		ch_sw_info->avl_buf_size = SCAN_INFO_RSVDPG_SIZE;
+		ch_sw_info->total_size = 0;
+		ch_sw_info->extra_info_en = 0;
+		ch_sw_info->ch_num = 0;
+	}
+
+	if (ch_sw_info->extra_info_en == 1) {
+		PLTFM_MSG_ERR("[ERR]extra info = 1!!\n");
+		return HALMAC_RET_CH_SW_SEQ_WRONG;
+	}
+
+	if (ch_sw_info->avl_buf_size < 4) {
+		PLTFM_MSG_ERR("[ERR]buf full!!\n");
+		return HALMAC_RET_CH_SW_NO_BUF;
+	}
+
+	if (cnv_scan_state_88xx(adapter, HALMAC_CMD_CNSTR_CNSTR) !=
+	    HALMAC_RET_SUCCESS)
+		return HALMAC_RET_ERROR_STATE;
+
+	CH_INFO_SET_CH(ch_sw_info->buf_wptr, info->channel);
+	CH_INFO_SET_PRI_CH_IDX(ch_sw_info->buf_wptr, info->pri_ch_idx);
+	CH_INFO_SET_BW(ch_sw_info->buf_wptr, info->bw);
+	CH_INFO_SET_TIMEOUT(ch_sw_info->buf_wptr, info->timeout);
+	CH_INFO_SET_ACTION_ID(ch_sw_info->buf_wptr, info->action_id);
+	CH_INFO_SET_EXTRA_INFO(ch_sw_info->buf_wptr, info->extra_info);
+
+	ch_sw_info->avl_buf_size = ch_sw_info->avl_buf_size - 4;
+	ch_sw_info->total_size = ch_sw_info->total_size + 4;
+	ch_sw_info->ch_num++;
+	ch_sw_info->extra_info_en = info->extra_info;
+	ch_sw_info->buf_wptr = ch_sw_info->buf_wptr + 4;
+
+	PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
+
+	return HALMAC_RET_SUCCESS;
+}
+
+static enum halmac_cmd_construct_state
+scan_cmd_cnstr_state_88xx(struct halmac_adapter *adapter)
+{
+	return adapter->halmac_state.scan_state.cmd_cnstr_state;
+}
+
+static enum halmac_ret_status
+cnv_scan_state_88xx(struct halmac_adapter *adapter,
+		    enum halmac_cmd_construct_state dest_state)
+{
+	enum halmac_cmd_construct_state *state;
+
+	state = &adapter->halmac_state.scan_state.cmd_cnstr_state;
+
+	if (dest_state == HALMAC_CMD_CNSTR_IDLE) {
+		if ((*state == HALMAC_CMD_CNSTR_BUF_CLR) ||
+		    (*state == HALMAC_CMD_CNSTR_CNSTR))
+			return HALMAC_RET_ERROR_STATE;
+	} else if (dest_state == HALMAC_CMD_CNSTR_BUF_CLR) {
+		if (*state == HALMAC_CMD_CNSTR_H2C_SENT)
+			return HALMAC_RET_ERROR_STATE;
+	} else if (dest_state == HALMAC_CMD_CNSTR_CNSTR) {
+		if ((*state == HALMAC_CMD_CNSTR_IDLE) ||
+		    (*state == HALMAC_CMD_CNSTR_H2C_SENT))
+			return HALMAC_RET_ERROR_STATE;
+	} else if (dest_state == HALMAC_CMD_CNSTR_H2C_SENT) {
+		if ((*state != HALMAC_CMD_CNSTR_CNSTR) &&
+		    (*state != HALMAC_CMD_CNSTR_BUF_CLR))
+			return HALMAC_RET_ERROR_STATE;
+	}
+
+	*state = dest_state;
+
+	return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * add_extra_ch_info_88xx() -add extra channel information
+ * @adapter : the adapter of halmac
+ * @info : extra channel information
+ * Author : KaiYuan Chang/Ivan Lin
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+add_extra_ch_info_88xx(struct halmac_adapter *adapter,
+		       struct halmac_ch_extra_info *info)
+{
+	struct halmac_ch_sw_info *ch_sw_info = &adapter->ch_sw_info;
+
+	PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
+
+	if (!ch_sw_info->buf) {
+		PLTFM_MSG_ERR("[ERR]buf = null!!\n");
+		return HALMAC_RET_CH_SW_SEQ_WRONG;
+	}
+
+	if (ch_sw_info->extra_info_en == 0) {
+		PLTFM_MSG_ERR("[ERR]extra info = 0!!\n");
+		return HALMAC_RET_CH_SW_SEQ_WRONG;
+	}
+
+	if (ch_sw_info->avl_buf_size < (u32)(info->extra_info_size + 2)) {
+		PLTFM_MSG_ERR("[ERR]no available buffer!!\n");
+		return HALMAC_RET_CH_SW_NO_BUF;
+	}
+
+	if (scan_cmd_cnstr_state_88xx(adapter) != HALMAC_CMD_CNSTR_CNSTR) {
+		PLTFM_MSG_WARN("[WARN]cmd state (ex scan)\n");
+		return HALMAC_RET_ERROR_STATE;
+	}
+
+	if (cnv_scan_state_88xx(adapter, HALMAC_CMD_CNSTR_CNSTR) !=
+	    HALMAC_RET_SUCCESS)
+		return HALMAC_RET_ERROR_STATE;
+
+	CH_EXTRA_INFO_SET_ID(ch_sw_info->buf_wptr, info->extra_action_id);
+	CH_EXTRA_INFO_SET_INFO(ch_sw_info->buf_wptr, info->extra_info);
+	CH_EXTRA_INFO_SET_SIZE(ch_sw_info->buf_wptr, info->extra_info_size);
+	PLTFM_MEMCPY(ch_sw_info->buf_wptr + 2, info->extra_info_data,
+		     info->extra_info_size);
+
+	ch_sw_info->avl_buf_size -= (2 + info->extra_info_size);
+	ch_sw_info->total_size += (2 + info->extra_info_size);
+	ch_sw_info->extra_info_en = info->extra_info;
+	ch_sw_info->buf_wptr += (2 + info->extra_info_size);
+
+	PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
+
+	return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * ctrl_ch_switch_88xx() -send channel switch cmd
+ * @adapter : the adapter of halmac
+ * @opt : channel switch config
+ * Author : KaiYuan Chang/Ivan Lin
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+ctrl_ch_switch_88xx(struct halmac_adapter *adapter,
+		    struct halmac_ch_switch_option *opt)
+{
+	enum halmac_ret_status status = HALMAC_RET_SUCCESS;
+	enum halmac_cmd_construct_state state;
+	enum halmac_cmd_process_status *proc_status;
+
+	proc_status = &adapter->halmac_state.scan_state.proc_status;
+
+	if (halmac_fw_validate(adapter) != HALMAC_RET_SUCCESS)
+		return HALMAC_RET_NO_DLFW;
+
+	if (adapter->fw_ver.h2c_version < 4)
+		return HALMAC_RET_FW_NO_SUPPORT;
+
+	PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
+
+	if (opt->switch_en == 0)
+		*proc_status = HALMAC_CMD_PROCESS_IDLE;
+
+	if ((*proc_status == HALMAC_CMD_PROCESS_SENDING) ||
+	    (*proc_status == HALMAC_CMD_PROCESS_RCVD)) {
+		PLTFM_MSG_TRACE("[TRACE]Wait event(scan)\n");
+		return HALMAC_RET_BUSY_STATE;
+	}
+
+	state = scan_cmd_cnstr_state_88xx(adapter);
+	if (opt->switch_en == 1) {
+		if (state != HALMAC_CMD_CNSTR_CNSTR) {
+			PLTFM_MSG_ERR("[ERR]state(en = 1)\n");
+			return HALMAC_RET_ERROR_STATE;
+		}
+	} else {
+		if (state != HALMAC_CMD_CNSTR_BUF_CLR) {
+			PLTFM_MSG_ERR("[ERR]state(en = 0)\n");
+			return HALMAC_RET_ERROR_STATE;
+		}
+	}
+
+	status = proc_ctrl_ch_switch_88xx(adapter, opt);
+	if (status != HALMAC_RET_SUCCESS) {
+		PLTFM_MSG_ERR("[ERR]ctrl ch sw!!\n");
+		return status;
+	}
+
+	PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
+
+	return HALMAC_RET_SUCCESS;
+}
+
+static enum halmac_ret_status
+proc_ctrl_ch_switch_88xx(struct halmac_adapter *adapter,
+			 struct halmac_ch_switch_option *opt)
+{
+	u8 h2c_buf[H2C_PKT_SIZE_88XX] = { 0 };
+	u16 seq_num = 0;
+	u16 pg_addr = adapter->txff_alloc.rsvd_h2c_info_addr;
+	struct halmac_h2c_header_info hdr_info;
+	enum halmac_ret_status status = HALMAC_RET_SUCCESS;
+	enum halmac_cmd_process_status *proc_status;
+
+	proc_status = &adapter->halmac_state.scan_state.proc_status;
+
+	PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
+
+	if (cnv_scan_state_88xx(adapter, HALMAC_CMD_CNSTR_H2C_SENT) !=
+	    HALMAC_RET_SUCCESS)
+		return HALMAC_RET_ERROR_STATE;
+
+	*proc_status = HALMAC_CMD_PROCESS_SENDING;
+
+	if (opt->switch_en != 0) {
+		status = dl_rsvd_page_88xx(adapter, pg_addr,
+					   adapter->ch_sw_info.buf,
+					   adapter->ch_sw_info.total_size);
+		if (status != HALMAC_RET_SUCCESS) {
+			PLTFM_MSG_ERR("[ERR]dl rsvd pg!!\n");
+			return status;
+		}
+	}
+
+	CH_SWITCH_SET_START(h2c_buf, opt->switch_en);
+	CH_SWITCH_SET_CH_NUM(h2c_buf, adapter->ch_sw_info.ch_num);
+	CH_SWITCH_SET_INFO_LOC(h2c_buf,
+			       pg_addr - adapter->txff_alloc.rsvd_boundary);
+	CH_SWITCH_SET_DEST_CH_EN(h2c_buf, opt->dest_ch_en);
+	CH_SWITCH_SET_DEST_CH(h2c_buf, opt->dest_ch);
+	CH_SWITCH_SET_PRI_CH_IDX(h2c_buf, opt->dest_pri_ch_idx);
+	CH_SWITCH_SET_ABSOLUTE_TIME(h2c_buf, opt->absolute_time_en);
+	CH_SWITCH_SET_TSF_LOW(h2c_buf, opt->tsf_low);
+	CH_SWITCH_SET_PERIODIC_OPT(h2c_buf, opt->periodic_option);
+	CH_SWITCH_SET_NORMAL_CYCLE(h2c_buf, opt->normal_cycle);
+	CH_SWITCH_SET_NORMAL_PERIOD(h2c_buf, opt->normal_period);
+	CH_SWITCH_SET_SLOW_PERIOD(h2c_buf, opt->phase_2_period);
+	CH_SWITCH_SET_NORMAL_PERIOD_SEL(h2c_buf, opt->normal_period_sel);
+	CH_SWITCH_SET_SLOW_PERIOD_SEL(h2c_buf, opt->phase_2_period_sel);
+	CH_SWITCH_SET_INFO_SIZE(h2c_buf, adapter->ch_sw_info.total_size);
+
+	hdr_info.sub_cmd_id = SUB_CMD_ID_CH_SWITCH;
+	hdr_info.content_size = 20;
+	hdr_info.ack = 1;
+	set_h2c_pkt_hdr_88xx(adapter, h2c_buf, &hdr_info, &seq_num);
+	adapter->halmac_state.scan_state.seq_num = seq_num;
+
+	status = send_h2c_pkt_88xx(adapter, h2c_buf);
+
+	if (status != HALMAC_RET_SUCCESS) {
+		PLTFM_MSG_ERR("[ERR]send h2c!!\n");
+		reset_ofld_feature_88xx(adapter, HALMAC_FEATURE_CHANNEL_SWITCH);
+	}
+	PLTFM_FREE(adapter->ch_sw_info.buf, adapter->ch_sw_info.buf_size);
+	adapter->ch_sw_info.buf = NULL;
+	adapter->ch_sw_info.buf_wptr = NULL;
+	adapter->ch_sw_info.extra_info_en = 0;
+	adapter->ch_sw_info.buf_size = 0;
+	adapter->ch_sw_info.avl_buf_size = 0;
+	adapter->ch_sw_info.total_size = 0;
+	adapter->ch_sw_info.ch_num = 0;
+
+	if (cnv_scan_state_88xx(adapter, HALMAC_CMD_CNSTR_IDLE) !=
+	    HALMAC_RET_SUCCESS)
+		return HALMAC_RET_ERROR_STATE;
+
+	return status;
+}
+
+/**
+ * clear_ch_info_88xx() -clear channel information
+ * @adapter : the adapter of halmac
+ * Author : KaiYuan Chang/Ivan Lin
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+clear_ch_info_88xx(struct halmac_adapter *adapter)
+{
+	PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
+
+	if (scan_cmd_cnstr_state_88xx(adapter) == HALMAC_CMD_CNSTR_H2C_SENT) {
+		PLTFM_MSG_WARN("[WARN]state(clear)\n");
+		return HALMAC_RET_ERROR_STATE;
+	}
+
+	if (cnv_scan_state_88xx(adapter, HALMAC_CMD_CNSTR_BUF_CLR) !=
+	    HALMAC_RET_SUCCESS)
+		return HALMAC_RET_ERROR_STATE;
+
+	PLTFM_FREE(adapter->ch_sw_info.buf, adapter->ch_sw_info.buf_size);
+	adapter->ch_sw_info.buf = NULL;
+	adapter->ch_sw_info.buf_wptr = NULL;
+	adapter->ch_sw_info.extra_info_en = 0;
+	adapter->ch_sw_info.buf_size = 0;
+	adapter->ch_sw_info.avl_buf_size = 0;
+	adapter->ch_sw_info.total_size = 0;
+	adapter->ch_sw_info.ch_num = 0;
+
+	PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
+
+	return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * chk_txdesc_88xx() -check if the tx packet format is incorrect
+ * @adapter : the adapter of halmac
+ * @buf : tx Packet buffer, tx desc is included
+ * @size : tx packet size
+ * Author : KaiYuan Chang
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+chk_txdesc_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size)
+{
+	u32 mac_clk = 0;
+	enum halmac_ret_status status = HALMAC_RET_SUCCESS;
+	struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
+
+	PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
+
+	if (GET_TX_DESC_BMC(buf) == 1 && GET_TX_DESC_AGG_EN(buf) == 1)
+		PLTFM_MSG_ERR("[ERR]txdesc - agg + bmc\n");
+
+	if (size < (GET_TX_DESC_TXPKTSIZE(buf) +
+		    adapter->hw_cfg_info.txdesc_size +
+		    (GET_TX_DESC_PKT_OFFSET(buf) << 3))) {
+		PLTFM_MSG_ERR("[ERR]txdesc - total size\n");
+		status = HALMAC_RET_TXDESC_SET_FAIL;
+	}
+
+	if (wlhdr_valid_88xx(adapter, buf) != HALMAC_RET_SUCCESS) {
+		PLTFM_MSG_ERR("[ERR]wlhdr\n");
+		status = HALMAC_RET_WLHDR_FAIL;
+	}
+
+	if (GET_TX_DESC_AMSDU_PAD_EN(buf) != 0) {
+		PLTFM_MSG_ERR("[ERR]txdesc - amsdu_pad\n");
+		status = HALMAC_RET_TXDESC_SET_FAIL;
+	}
+
+	switch (BIT_GET_MAC_CLK_SEL(HALMAC_REG_R32(REG_AFE_CTRL1))) {
+	case 0x0:
+		mac_clk = 80;
+		break;
+	case 0x1:
+		mac_clk = 40;
+		break;
+	case 0x2:
+		mac_clk = 20;
+		break;
+	case 0x3:
+		mac_clk = 10;
+		break;
+	}
+
+	PLTFM_MSG_ALWAYS("MAC clock : 0x%XM\n", mac_clk);
+	PLTFM_MSG_ALWAYS("mac agg en : 0x%X\n", GET_TX_DESC_AGG_EN(buf));
+	PLTFM_MSG_ALWAYS("mac agg num : 0x%X\n", GET_TX_DESC_MAX_AGG_NUM(buf));
+
+	PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
+
+	return status;
+}
+
+static enum halmac_ret_status
+wlhdr_valid_88xx(struct halmac_adapter *adapter, u8 *buf)
+{
+	u32 txdesc_size = adapter->hw_cfg_info.txdesc_size +
+						GET_TX_DESC_PKT_OFFSET(buf);
+	enum halmac_ret_status status = HALMAC_RET_SUCCESS;
+	struct wlhdr_frame_ctrl *wlhdr;
+
+	wlhdr = (struct wlhdr_frame_ctrl *)(buf + txdesc_size);
+
+	if (wlhdr->protocol != WLHDR_PROT_VER) {
+		PLTFM_MSG_ERR("[ERR]prot ver!!\n");
+		return HALMAC_RET_WLHDR_FAIL;
+	}
+
+	switch (wlhdr->type) {
+	case WLHDR_TYPE_MGMT:
+		if (wlhdr_mgmt_valid_88xx(adapter, wlhdr) != 1)
+			status = HALMAC_RET_WLHDR_FAIL;
+		break;
+	case WLHDR_TYPE_CTRL:
+		if (wlhdr_ctrl_valid_88xx(adapter, wlhdr) != 1)
+			status = HALMAC_RET_WLHDR_FAIL;
+		break;
+	case WLHDR_TYPE_DATA:
+		if (wlhdr_data_valid_88xx(adapter, wlhdr) != 1)
+			status = HALMAC_RET_WLHDR_FAIL;
+		break;
+	default:
+		PLTFM_MSG_ERR("[ERR]undefined type!!\n");
+		status = HALMAC_RET_WLHDR_FAIL;
+		break;
+	}
+
+	return status;
+}
+
+static u8
+wlhdr_mgmt_valid_88xx(struct halmac_adapter *adapter,
+		      struct wlhdr_frame_ctrl *wlhdr)
+{
+	u8 state;
+
+	switch (wlhdr->sub_type) {
+	case WLHDR_SUB_TYPE_ASSOC_REQ:
+	case WLHDR_SUB_TYPE_ASSOC_RSPNS:
+	case WLHDR_SUB_TYPE_REASSOC_REQ:
+	case WLHDR_SUB_TYPE_REASSOC_RSPNS:
+	case WLHDR_SUB_TYPE_PROBE_REQ:
+	case WLHDR_SUB_TYPE_PROBE_RSPNS:
+	case WLHDR_SUB_TYPE_BCN:
+	case WLHDR_SUB_TYPE_DISASSOC:
+	case WLHDR_SUB_TYPE_AUTH:
+	case WLHDR_SUB_TYPE_DEAUTH:
+	case WLHDR_SUB_TYPE_ACTION:
+	case WLHDR_SUB_TYPE_ACTION_NOACK:
+		state = 1;
+		break;
+	default:
+		PLTFM_MSG_ERR("[ERR]mgmt invalid!!\n");
+		state = 0;
+		break;
+	}
+
+	return state;
+}
+
+static u8
+wlhdr_ctrl_valid_88xx(struct halmac_adapter *adapter,
+		      struct wlhdr_frame_ctrl *wlhdr)
+{
+	u8 state;
+
+	switch (wlhdr->sub_type) {
+	case WLHDR_SUB_TYPE_BF_RPT_POLL:
+	case WLHDR_SUB_TYPE_NDPA:
+		state = 1;
+		break;
+	default:
+		PLTFM_MSG_ERR("[ERR]ctrl invalid!!\n");
+		state = 0;
+		break;
+	}
+
+	return state;
+}
+
+static u8
+wlhdr_data_valid_88xx(struct halmac_adapter *adapter,
+		      struct wlhdr_frame_ctrl *wlhdr)
+{
+	u8 state;
+
+	switch (wlhdr->sub_type) {
+	case WLHDR_SUB_TYPE_DATA:
+	case WLHDR_SUB_TYPE_NULL:
+	case WLHDR_SUB_TYPE_QOS_DATA:
+	case WLHDR_SUB_TYPE_QOS_NULL:
+		state = 1;
+		break;
+	default:
+		PLTFM_MSG_ERR("[ERR]data invalid!!\n");
+		state = 0;
+		break;
+	}
+
+	return state;
+}
+
+/**
+ * get_version_88xx() - get HALMAC version
+ * @ver : return version of major, prototype and minor information
+ * Author : KaiYuan Chang / Ivan Lin
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+get_version_88xx(struct halmac_adapter *adapter, struct halmac_ver *ver)
+{
+	PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
+
+	ver->major_ver = (u8)HALMAC_MAJOR_VER;
+	ver->prototype_ver = (u8)HALMAC_PROTOTYPE_VER;
+	ver->minor_ver = (u8)HALMAC_MINOR_VER;
+
+	PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
+
+	return HALMAC_RET_SUCCESS;
+}
+
+enum halmac_ret_status
+p2pps_88xx(struct halmac_adapter *adapter, struct halmac_p2pps *info)
+{
+	enum halmac_ret_status status = HALMAC_RET_SUCCESS;
+
+	if (halmac_fw_validate(adapter) != HALMAC_RET_SUCCESS)
+		return HALMAC_RET_NO_DLFW;
+
+	if (adapter->fw_ver.h2c_version < 6)
+		return HALMAC_RET_FW_NO_SUPPORT;
+
+	status = proc_p2pps_88xx(adapter, info);
+	if (status != HALMAC_RET_SUCCESS) {
+		PLTFM_MSG_ERR("[ERR]p2pps!!\n");
+		return status;
+	}
+
+	return HALMAC_RET_SUCCESS;
+}
+
+static enum halmac_ret_status
+proc_p2pps_88xx(struct halmac_adapter *adapter, struct halmac_p2pps *info)
+{
+	u8 h2c_buf[H2C_PKT_SIZE_88XX] = { 0 };
+	u16 seq_num = 0;
+	struct halmac_h2c_header_info hdr_info;
+	enum halmac_ret_status status = HALMAC_RET_SUCCESS;
+
+	P2PPS_SET_OFFLOAD_EN(h2c_buf, info->offload_en);
+	P2PPS_SET_ROLE(h2c_buf, info->role);
+	P2PPS_SET_CTWINDOW_EN(h2c_buf, info->ctwindow_en);
+	P2PPS_SET_NOA_EN(h2c_buf, info->noa_en);
+	P2PPS_SET_NOA_SEL(h2c_buf, info->noa_sel);
+	P2PPS_SET_ALLSTASLEEP(h2c_buf, info->all_sta_sleep);
+	P2PPS_SET_DISCOVERY(h2c_buf, info->discovery);
+	P2PPS_SET_DISABLE_CLOSERF(h2c_buf, info->disable_close_rf);
+	P2PPS_SET_P2P_PORT_ID(h2c_buf, info->p2p_port_id);
+	P2PPS_SET_P2P_GROUP(h2c_buf, info->p2p_group);
+	P2PPS_SET_P2P_MACID(h2c_buf, info->p2p_macid);
+
+	P2PPS_SET_CTWINDOW_LENGTH(h2c_buf, info->ctwindow_length);
+
+	P2PPS_SET_NOA_DURATION_PARA(h2c_buf, info->noa_duration_para);
+	P2PPS_SET_NOA_INTERVAL_PARA(h2c_buf, info->noa_interval_para);
+	P2PPS_SET_NOA_START_TIME_PARA(h2c_buf, info->noa_start_time_para);
+	P2PPS_SET_NOA_COUNT_PARA(h2c_buf, info->noa_count_para);
+
+	hdr_info.sub_cmd_id = SUB_CMD_ID_P2PPS;
+	hdr_info.content_size = 24;
+	hdr_info.ack = 0;
+	set_h2c_pkt_hdr_88xx(adapter, h2c_buf, &hdr_info, &seq_num);
+
+	status = send_h2c_pkt_88xx(adapter, h2c_buf);
+
+	if (status != HALMAC_RET_SUCCESS)
+		PLTFM_MSG_ERR("[ERR]send h2c!!\n");
+
+	return status;
+}
+
+/**
+ * query_status_88xx() -query the offload feature status
+ * @adapter : the adapter of halmac
+ * @feature_id : feature_id
+ * @proc_status : feature_status
+ * @data : data buffer
+ * @size : data size
+ *
+ * Note :
+ * If user wants to know the data size, user can allocate zero
+ * size buffer first. If this size less than the data size, halmac
+ * will return  HALMAC_RET_BUFFER_TOO_SMALL. User need to
+ * re-allocate data buffer with correct data size.
+ *
+ * Author : Ivan Lin/KaiYuan Chang
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+query_status_88xx(struct halmac_adapter *adapter,
+		  enum halmac_feature_id feature_id,
+		  enum halmac_cmd_process_status *proc_status, u8 *data,
+		  u32 *size)
+{
+	enum halmac_ret_status status = HALMAC_RET_SUCCESS;
+
+	if (!proc_status)
+		return HALMAC_RET_NULL_POINTER;
+
+	switch (feature_id) {
+	case HALMAC_FEATURE_CFG_PARA:
+		status = get_cfg_param_status_88xx(adapter, proc_status);
+		break;
+	case HALMAC_FEATURE_DUMP_PHYSICAL_EFUSE:
+		status = get_dump_phy_efuse_status_88xx(adapter, proc_status,
+							data, size);
+		break;
+	case HALMAC_FEATURE_DUMP_LOGICAL_EFUSE:
+		status = get_dump_log_efuse_status_88xx(adapter, proc_status,
+							data, size);
+		break;
+	case HALMAC_FEATURE_CHANNEL_SWITCH:
+		status = get_ch_switch_status_88xx(adapter, proc_status);
+		break;
+	case HALMAC_FEATURE_UPDATE_PACKET:
+		status = get_update_packet_status_88xx(adapter, proc_status);
+		break;
+	case HALMAC_FEATURE_IQK:
+		status = get_iqk_status_88xx(adapter, proc_status);
+		break;
+	case HALMAC_FEATURE_POWER_TRACKING:
+		status = get_pwr_trk_status_88xx(adapter, proc_status);
+		break;
+	case HALMAC_FEATURE_PSD:
+		status = get_psd_status_88xx(adapter, proc_status, data, size);
+		break;
+	case HALMAC_FEATURE_FW_SNDING:
+		status = get_fw_snding_status_88xx(adapter, proc_status);
+		break;
+	default:
+		return HALMAC_RET_INVALID_FEATURE_ID;
+	}
+
+	return status;
+}
+
+static enum halmac_ret_status
+get_cfg_param_status_88xx(struct halmac_adapter *adapter,
+			  enum halmac_cmd_process_status *proc_status)
+{
+	*proc_status = adapter->halmac_state.cfg_param_state.proc_status;
+
+	return HALMAC_RET_SUCCESS;
+}
+
+static enum halmac_ret_status
+get_ch_switch_status_88xx(struct halmac_adapter *adapter,
+			  enum halmac_cmd_process_status *proc_status)
+{
+	*proc_status = adapter->halmac_state.scan_state.proc_status;
+
+	return HALMAC_RET_SUCCESS;
+}
+
+static enum halmac_ret_status
+get_update_packet_status_88xx(struct halmac_adapter *adapter,
+			      enum halmac_cmd_process_status *proc_status)
+{
+	*proc_status = adapter->halmac_state.update_pkt_state.proc_status;
+
+	return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * cfg_drv_rsvd_pg_num_88xx() -config reserved page number for driver
+ * @adapter : the adapter of halmac
+ * @pg_num : page number
+ * Author : KaiYuan Chang
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+cfg_drv_rsvd_pg_num_88xx(struct halmac_adapter *adapter,
+			 enum halmac_drv_rsvd_pg_num pg_num)
+{
+	if (adapter->api_registry.cfg_drv_rsvd_pg_en == 0)
+		return HALMAC_RET_NOT_SUPPORT;
+
+	PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
+	PLTFM_MSG_TRACE("[TRACE]pg_num = %d\n", pg_num);
+
+	switch (pg_num) {
+	case HALMAC_RSVD_PG_NUM8:
+		adapter->txff_alloc.rsvd_drv_pg_num = 8;
+		break;
+	case HALMAC_RSVD_PG_NUM16:
+		adapter->txff_alloc.rsvd_drv_pg_num = 16;
+		break;
+	case HALMAC_RSVD_PG_NUM24:
+		adapter->txff_alloc.rsvd_drv_pg_num = 24;
+		break;
+	case HALMAC_RSVD_PG_NUM32:
+		adapter->txff_alloc.rsvd_drv_pg_num = 32;
+		break;
+	case HALMAC_RSVD_PG_NUM64:
+		adapter->txff_alloc.rsvd_drv_pg_num = 64;
+		break;
+	case HALMAC_RSVD_PG_NUM128:
+		adapter->txff_alloc.rsvd_drv_pg_num = 128;
+		break;
+	}
+
+	PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
+
+	return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * (debug API)h2c_lb_88xx() - send h2c loopback packet
+ * @adapter : the adapter of halmac
+ * Author : KaiYuan Chang/Ivan Lin
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+h2c_lb_88xx(struct halmac_adapter *adapter)
+{
+	return HALMAC_RET_SUCCESS;
+}
+
+enum halmac_ret_status
+pwr_seq_parser_88xx(struct halmac_adapter *adapter,
+		    struct halmac_wlan_pwr_cfg **cmd_seq)
+{
+	u8 cut;
+	u8 intf;
+	u32 idx = 0;
+	enum halmac_ret_status status = HALMAC_RET_SUCCESS;
+	struct halmac_wlan_pwr_cfg *cmd;
+
+	switch (adapter->chip_ver) {
+	case HALMAC_CHIP_VER_A_CUT:
+		cut = HALMAC_PWR_CUT_A_MSK;
+		break;
+	case HALMAC_CHIP_VER_B_CUT:
+		cut = HALMAC_PWR_CUT_B_MSK;
+		break;
+	case HALMAC_CHIP_VER_C_CUT:
+		cut = HALMAC_PWR_CUT_C_MSK;
+		break;
+	case HALMAC_CHIP_VER_D_CUT:
+		cut = HALMAC_PWR_CUT_D_MSK;
+		break;
+	case HALMAC_CHIP_VER_E_CUT:
+		cut = HALMAC_PWR_CUT_E_MSK;
+		break;
+	case HALMAC_CHIP_VER_F_CUT:
+		cut = HALMAC_PWR_CUT_F_MSK;
+		break;
+	case HALMAC_CHIP_VER_TEST:
+		cut = HALMAC_PWR_CUT_TESTCHIP_MSK;
+		break;
+	default:
+		PLTFM_MSG_ERR("[ERR]cut version!!\n");
+		return HALMAC_RET_SWITCH_CASE_ERROR;
+	}
+
+	switch (adapter->intf) {
+	case HALMAC_INTERFACE_PCIE:
+	case HALMAC_INTERFACE_AXI:
+		intf = HALMAC_PWR_INTF_PCI_MSK;
+		break;
+	case HALMAC_INTERFACE_USB:
+		intf = HALMAC_PWR_INTF_USB_MSK;
+		break;
+	case HALMAC_INTERFACE_SDIO:
+		intf = HALMAC_PWR_INTF_SDIO_MSK;
+		break;
+	default:
+		PLTFM_MSG_ERR("[ERR]interface!!\n");
+		return HALMAC_RET_SWITCH_CASE_ERROR;
+	}
+
+	do {
+		cmd = cmd_seq[idx];
+
+		if (!cmd)
+			break;
+
+		status = pwr_sub_seq_parser_88xx(adapter, cut, intf, cmd);
+		if (status != HALMAC_RET_SUCCESS) {
+			PLTFM_MSG_ERR("[ERR]pwr sub seq!!\n");
+			return status;
+		}
+
+		idx++;
+	} while (1);
+
+	return status;
+}
+
+static enum halmac_ret_status
+pwr_sub_seq_parser_88xx(struct halmac_adapter *adapter, u8 cut, u8 intf,
+			struct halmac_wlan_pwr_cfg *cmd)
+{
+	u8 value;
+	u32 offset;
+	struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
+
+	do {
+		if ((cmd->interface_msk & intf) && (cmd->cut_msk & cut)) {
+			switch (cmd->cmd) {
+			case HALMAC_PWR_CMD_WRITE:
+				offset = cmd->offset;
+
+				if (cmd->base == HALMAC_PWR_ADDR_SDIO)
+					offset |= SDIO_LOCAL_OFFSET;
+
+				value = HALMAC_REG_R8(offset);
+				value = (u8)(value & (u8)(~(cmd->msk)));
+				value = (u8)(value | (cmd->value & cmd->msk));
+
+				HALMAC_REG_W8(offset, value);
+				break;
+			case HALMAC_PWR_CMD_POLLING:
+				if (pwr_cmd_polling_88xx(adapter, cmd) !=
+				    HALMAC_RET_SUCCESS)
+					return HALMAC_RET_PWRSEQ_POLLING_FAIL;
+				break;
+			case HALMAC_PWR_CMD_DELAY:
+				if (cmd->value == HALMAC_PWR_DELAY_US)
+					PLTFM_DELAY_US(cmd->offset);
+				else
+					PLTFM_DELAY_US(1000 * cmd->offset);
+				break;
+			case HALMAC_PWR_CMD_READ:
+				break;
+			case HALMAC_PWR_CMD_END:
+				return HALMAC_RET_SUCCESS;
+			default:
+				return HALMAC_RET_PWRSEQ_CMD_INCORRECT;
+			}
+		}
+		cmd++;
+	} while (1);
+
+	return HALMAC_RET_SUCCESS;
+}
+
+static enum halmac_ret_status
+pwr_cmd_polling_88xx(struct halmac_adapter *adapter,
+		     struct halmac_wlan_pwr_cfg *cmd)
+{
+	u8 value;
+	u8 flg;
+	u8 poll_bit;
+	u32 offset;
+	u32 cnt;
+	static u32 stats;
+	enum halmac_interface intf;
+	struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
+
+	poll_bit = 0;
+	cnt = HALMAC_PWR_POLLING_CNT;
+	flg = 0;
+	intf = adapter->intf;
+
+	if (cmd->base == HALMAC_PWR_ADDR_SDIO)
+		offset = cmd->offset | SDIO_LOCAL_OFFSET;
+	else
+		offset = cmd->offset;
+
+	do {
+		cnt--;
+		value = HALMAC_REG_R8(offset);
+		value = (u8)(value & cmd->msk);
+
+		if (value == (cmd->value & cmd->msk)) {
+			poll_bit = 1;
+		} else {
+			if (cnt == 0) {
+				if (intf == HALMAC_INTERFACE_PCIE && flg == 0) {
+					/* PCIE + USB package */
+					/* power bit polling timeout issue */
+					stats++;
+					PLTFM_MSG_WARN("[WARN]PCIE stats:%d\n",
+						       stats);
+					value = HALMAC_REG_R8(REG_SYS_PW_CTRL);
+					value |= BIT(3);
+					HALMAC_REG_W8(REG_SYS_PW_CTRL, value);
+					value &= ~BIT(3);
+					HALMAC_REG_W8(REG_SYS_PW_CTRL, value);
+					poll_bit = 0;
+					cnt = HALMAC_PWR_POLLING_CNT;
+					flg = 1;
+				} else {
+					PLTFM_MSG_ERR("[ERR]polling to!!\n");
+					PLTFM_MSG_ERR("[ERR]cmd offset:%X\n",
+						      cmd->offset);
+					PLTFM_MSG_ERR("[ERR]cmd value:%X\n",
+						      cmd->value);
+					PLTFM_MSG_ERR("[ERR]cmd msk:%X\n",
+						      cmd->msk);
+					PLTFM_MSG_ERR("[ERR]offset = %X\n",
+						      offset);
+					PLTFM_MSG_ERR("[ERR]value = %X\n",
+						      value);
+					return HALMAC_RET_PWRSEQ_POLLING_FAIL;
+				}
+			} else {
+				PLTFM_DELAY_US(50);
+			}
+		}
+	} while (!poll_bit);
+
+	return HALMAC_RET_SUCCESS;
+}
+
+enum halmac_ret_status
+parse_intf_phy_88xx(struct halmac_adapter *adapter,
+		    struct halmac_intf_phy_para *param,
+		    enum halmac_intf_phy_platform pltfm,
+		    enum hal_intf_phy intf_phy)
+{
+	u16 value;
+	u16 cur_cut;
+	u16 offset;
+	u16 ip_sel;
+	struct halmac_intf_phy_para *cur_param;
+	struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
+	u8 result = HALMAC_RET_SUCCESS;
+
+	switch (adapter->chip_ver) {
+	case HALMAC_CHIP_VER_A_CUT:
+		cur_cut = (u16)HALMAC_INTF_PHY_CUT_A;
+		break;
+	case HALMAC_CHIP_VER_B_CUT:
+		cur_cut = (u16)HALMAC_INTF_PHY_CUT_B;
+		break;
+	case HALMAC_CHIP_VER_C_CUT:
+		cur_cut = (u16)HALMAC_INTF_PHY_CUT_C;
+		break;
+	case HALMAC_CHIP_VER_D_CUT:
+		cur_cut = (u16)HALMAC_INTF_PHY_CUT_D;
+		break;
+	case HALMAC_CHIP_VER_E_CUT:
+		cur_cut = (u16)HALMAC_INTF_PHY_CUT_E;
+		break;
+	case HALMAC_CHIP_VER_F_CUT:
+		cur_cut = (u16)HALMAC_INTF_PHY_CUT_F;
+		break;
+	case HALMAC_CHIP_VER_TEST:
+		cur_cut = (u16)HALMAC_INTF_PHY_CUT_TESTCHIP;
+		break;
+	default:
+		return HALMAC_RET_FAIL;
+	}
+
+	cur_param = param;
+
+	do {
+		if ((cur_param->cut & cur_cut) &&
+		    (cur_param->plaform & (u16)pltfm)) {
+			offset =  cur_param->offset;
+			value = cur_param->value;
+			ip_sel = cur_param->ip_sel;
+
+			if (offset == 0xFFFF)
+				break;
+
+			if (ip_sel == HALMAC_IP_SEL_MAC) {
+				HALMAC_REG_W8((u32)offset, (u8)value);
+			} else if (intf_phy == HAL_INTF_PHY_USB2 ||
+				   intf_phy == HAL_INTF_PHY_USB3) {
+#if HALMAC_USB_SUPPORT
+				result = usbphy_write_88xx(adapter, (u8)offset,
+							   value, intf_phy);
+				if (result != HALMAC_RET_SUCCESS)
+					PLTFM_MSG_ERR("[ERR]usb phy!!\n");
+#endif
+			} else if (intf_phy == HAL_INTF_PHY_PCIE_GEN1 ||
+				   intf_phy == HAL_INTF_PHY_PCIE_GEN2) {
+#if HALMAC_PCIE_SUPPORT
+				if (ip_sel == HALMAC_IP_INTF_PHY)
+					result = mdio_write_88xx(adapter,
+								 (u8)offset,
+								 value,
+								 intf_phy);
+				else
+					result = dbi_w8_88xx(adapter, offset,
+							     (u8)value);
+				if (result != HALMAC_RET_SUCCESS)
+					PLTFM_MSG_ERR("[ERR]mdio/dbi!!\n");
+#endif
+			} else {
+				PLTFM_MSG_ERR("[ERR]intf phy sel!!\n");
+			}
+		}
+		cur_param++;
+	} while (1);
+
+	return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * txfifo_is_empty_88xx() -check if txfifo is empty
+ * @adapter : the adapter of halmac
+ * @chk_num : check number
+ * Author : Ivan Lin
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+txfifo_is_empty_88xx(struct halmac_adapter *adapter, u32 chk_num)
+{
+	u32 cnt;
+	struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
+
+	PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
+
+	cnt = (chk_num <= 10) ? 10 : chk_num;
+	do {
+		if (HALMAC_REG_R8(REG_TXPKT_EMPTY) != 0xFF)
+			return HALMAC_RET_TXFIFO_NO_EMPTY;
+
+		if ((HALMAC_REG_R8(REG_TXPKT_EMPTY + 1) & 0x06) != 0x06)
+			return HALMAC_RET_TXFIFO_NO_EMPTY;
+		cnt--;
+
+	} while (cnt != 0);
+
+	PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
+
+	return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * (internal use)
+ * smart_malloc_88xx() - adapt malloc size
+ * @adapter : the adapter of halmac
+ * @size : expected malloc size
+ * @pNew_size : real malloc size
+ * Author : Ivan Lin
+ * Return : address pointer
+ */
+u8*
+smart_malloc_88xx(struct halmac_adapter *adapter, u32 size, u32 *new_size)
+{
+	u8 retry_num;
+	u8 *malloc_buf = NULL;
+
+	for (retry_num = 0; retry_num < 5; retry_num++) {
+		malloc_buf = (u8 *)PLTFM_MALLOC(size);
+
+		if (malloc_buf) {
+			*new_size = size;
+			return malloc_buf;
+		}
+
+		size = size >> 1;
+
+		if (size == 0)
+			break;
+	}
+
+	PLTFM_MSG_ERR("[ERR]adptive malloc!!\n");
+
+	return NULL;
+}
+
+/**
+ * (internal use)
+ * ltecoex_reg_read_88xx() - read ltecoex register
+ * @adapter : the adapter of halmac
+ * @offset : offset
+ * @pValue : value
+ * Author : Ivan Lin
+ * Return : enum halmac_ret_status
+ */
+enum halmac_ret_status
+ltecoex_reg_read_88xx(struct halmac_adapter *adapter, u16 offset, u32 *value)
+{
+	u32 cnt;
+	struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
+
+	cnt = 10000;
+	while ((HALMAC_REG_R8(LTECOEX_ACCESS_CTRL + 3) & BIT(5)) == 0) {
+		if (cnt == 0) {
+			PLTFM_MSG_ERR("[ERR]lte ready(R)\n");
+			return HALMAC_RET_LTECOEX_READY_FAIL;
+		}
+		cnt--;
+		PLTFM_DELAY_US(50);
+	}
+
+	HALMAC_REG_W32(LTECOEX_ACCESS_CTRL, 0x800F0000 | offset);
+	*value = HALMAC_REG_R32(REG_WL2LTECOEX_INDIRECT_ACCESS_READ_DATA_V1);
+
+	return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * (internal use)
+ * ltecoex_reg_write_88xx() - write ltecoex register
+ * @adapter : the adapter of halmac
+ * @offset : offset
+ * @value : value
+ * Author : Ivan Lin
+ * Return : enum halmac_ret_status
+ */
+enum halmac_ret_status
+ltecoex_reg_write_88xx(struct halmac_adapter *adapter, u16 offset, u32 value)
+{
+	u32 cnt;
+	struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
+
+	cnt = 10000;
+	while ((HALMAC_REG_R8(LTECOEX_ACCESS_CTRL + 3) & BIT(5)) == 0) {
+		if (cnt == 0) {
+			PLTFM_MSG_ERR("[ERR]lte ready(W)\n");
+			return HALMAC_RET_LTECOEX_READY_FAIL;
+		}
+		cnt--;
+		PLTFM_DELAY_US(50);
+	}
+
+	HALMAC_REG_W32(REG_WL2LTECOEX_INDIRECT_ACCESS_WRITE_DATA_V1, value);
+	HALMAC_REG_W32(LTECOEX_ACCESS_CTRL, 0xC00F0000 | offset);
+
+	return HALMAC_RET_SUCCESS;
+}
+
+static void
+pwr_state_88xx(struct halmac_adapter *adapter, enum halmac_mac_power *state)
+{
+	struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
+
+	if ((HALMAC_REG_R8(REG_SYS_FUNC_EN + 1) & BIT(3)) == 0)
+		*state = HALMAC_MAC_POWER_OFF;
+	else
+		*state = HALMAC_MAC_POWER_ON;
+}
+
+#endif /* HALMAC_88XX_SUPPORT */
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/halmac/halmac_88xx/halmac_common_88xx.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/halmac/halmac_88xx/halmac_common_88xx.h
--- linux-5.6.3/3rdparty/rtl8821ce/hal/halmac/halmac_88xx/halmac_common_88xx.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/halmac/halmac_88xx/halmac_common_88xx.h	2020-04-10 16:35:06.792658947 +0300
@@ -0,0 +1,155 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ ******************************************************************************/
+
+#ifndef _HALMAC_COMMON_88XX_H_
+#define _HALMAC_COMMON_88XX_H_
+
+#include "../halmac_api.h"
+#include "../halmac_pwr_seq_cmd.h"
+#include "../halmac_gpio_cmd.h"
+
+#if HALMAC_88XX_SUPPORT
+
+enum halmac_ret_status
+ofld_func_cfg_88xx(struct halmac_adapter *adapter,
+		   struct halmac_ofld_func_info *info);
+
+enum halmac_ret_status
+dl_drv_rsvd_page_88xx(struct halmac_adapter *adapter, u8 pg_offset, u8 *buf,
+		      u32 size);
+
+enum halmac_ret_status
+dl_rsvd_page_88xx(struct halmac_adapter *adapter, u16 pg_addr, u8 *buf,
+		  u32 size);
+
+enum halmac_ret_status
+get_hw_value_88xx(struct halmac_adapter *adapter, enum halmac_hw_id hw_id,
+		  void *value);
+
+enum halmac_ret_status
+set_hw_value_88xx(struct halmac_adapter *adapter, enum halmac_hw_id hw_id,
+		  void *value);
+
+enum halmac_ret_status
+set_h2c_pkt_hdr_88xx(struct halmac_adapter *adapter, u8 *hdr,
+		     struct halmac_h2c_header_info *info, u16 *seq_num);
+
+enum halmac_ret_status
+send_h2c_pkt_88xx(struct halmac_adapter *adapter, u8 *pkt);
+
+enum halmac_ret_status
+get_h2c_buf_free_space_88xx(struct halmac_adapter *adapter);
+
+enum halmac_ret_status
+get_c2h_info_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size);
+
+enum halmac_ret_status
+mac_debug_88xx(struct halmac_adapter *adapter);
+
+enum halmac_ret_status
+cfg_parameter_88xx(struct halmac_adapter *adapter,
+		   struct halmac_phy_parameter_info *info, u8 full_fifo);
+
+enum halmac_ret_status
+update_packet_88xx(struct halmac_adapter *adapter, enum halmac_packet_id pkt_id,
+		   u8 *pkt, u32 size);
+
+enum halmac_ret_status
+bcn_ie_filter_88xx(struct halmac_adapter *adapter,
+		   struct halmac_bcn_ie_info *info);
+
+enum halmac_ret_status
+update_datapack_88xx(struct halmac_adapter *adapter,
+		     enum halmac_data_type data_type,
+		     struct halmac_phy_parameter_info *info);
+
+enum halmac_ret_status
+run_datapack_88xx(struct halmac_adapter *adapter,
+		  enum halmac_data_type data_type);
+
+enum halmac_ret_status
+send_bt_coex_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size, u8 ack);
+
+enum halmac_ret_status
+dump_fifo_88xx(struct halmac_adapter *adapter, enum hal_fifo_sel sel,
+	       u32 start_addr, u32 size, u8 *data);
+
+u32
+get_fifo_size_88xx(struct halmac_adapter *adapter, enum hal_fifo_sel sel);
+
+enum halmac_ret_status
+set_h2c_header_88xx(struct halmac_adapter *adapter, u8 *hdr, u16 *seq, u8 ack);
+
+enum halmac_ret_status
+add_ch_info_88xx(struct halmac_adapter *adapter, struct halmac_ch_info *info);
+
+enum halmac_ret_status
+add_extra_ch_info_88xx(struct halmac_adapter *adapter,
+		       struct halmac_ch_extra_info *info);
+
+enum halmac_ret_status
+ctrl_ch_switch_88xx(struct halmac_adapter *adapter,
+		    struct halmac_ch_switch_option *opt);
+
+enum halmac_ret_status
+clear_ch_info_88xx(struct halmac_adapter *adapter);
+
+enum halmac_ret_status
+chk_txdesc_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size);
+
+enum halmac_ret_status
+get_version_88xx(struct halmac_adapter *adapter, struct halmac_ver *ver);
+
+enum halmac_ret_status
+p2pps_88xx(struct halmac_adapter *adapter, struct halmac_p2pps *info);
+
+enum halmac_ret_status
+query_status_88xx(struct halmac_adapter *adapter,
+		  enum halmac_feature_id feature_id,
+		  enum halmac_cmd_process_status *proc_status, u8 *data,
+		  u32 *size);
+
+enum halmac_ret_status
+cfg_drv_rsvd_pg_num_88xx(struct halmac_adapter *adapter,
+			 enum halmac_drv_rsvd_pg_num pg_num);
+
+enum halmac_ret_status
+h2c_lb_88xx(struct halmac_adapter *adapter);
+
+enum halmac_ret_status
+pwr_seq_parser_88xx(struct halmac_adapter *adapter,
+		    struct halmac_wlan_pwr_cfg **cmd_seq);
+
+enum halmac_ret_status
+parse_intf_phy_88xx(struct halmac_adapter *adapter,
+		    struct halmac_intf_phy_para *param,
+		    enum halmac_intf_phy_platform pltfm,
+		    enum hal_intf_phy intf_phy);
+
+enum halmac_ret_status
+txfifo_is_empty_88xx(struct halmac_adapter *adapter, u32 chk_num);
+
+u8*
+smart_malloc_88xx(struct halmac_adapter *adapter, u32 size, u32 *new_size);
+
+enum halmac_ret_status
+ltecoex_reg_read_88xx(struct halmac_adapter *adapter, u16 offset, u32 *value);
+
+enum halmac_ret_status
+ltecoex_reg_write_88xx(struct halmac_adapter *adapter, u16 offset, u32 value);
+
+#endif/* HALMAC_88XX_SUPPORT */
+
+#endif/* _HALMAC_COMMON_88XX_H_ */
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/halmac/halmac_88xx/halmac_efuse_88xx.c linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/halmac/halmac_88xx/halmac_efuse_88xx.c
--- linux-5.6.3/3rdparty/rtl8821ce/hal/halmac/halmac_88xx/halmac_efuse_88xx.c	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/halmac/halmac_88xx/halmac_efuse_88xx.c	2020-04-10 16:35:06.792658947 +0300
@@ -0,0 +1,1905 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ ******************************************************************************/
+
+#include "halmac_efuse_88xx.h"
+#include "halmac_88xx_cfg.h"
+#include "halmac_common_88xx.h"
+#include "halmac_init_88xx.h"
+
+#if HALMAC_88XX_SUPPORT
+
+#define RSVD_EFUSE_SIZE		16
+#define RSVD_CS_EFUSE_SIZE	24
+#define PROTECT_EFUSE_SIZE	96
+#define FEATURE_DUMP_PHY_EFUSE	HALMAC_FEATURE_DUMP_PHYSICAL_EFUSE
+#define FEATURE_DUMP_LOG_EFUSE	HALMAC_FEATURE_DUMP_LOGICAL_EFUSE
+
+static enum halmac_cmd_construct_state
+efuse_cmd_cnstr_state_88xx(struct halmac_adapter *adapter);
+
+static enum halmac_ret_status
+proc_dump_efuse_88xx(struct halmac_adapter *adapter,
+		     enum halmac_efuse_read_cfg cfg);
+
+static enum halmac_ret_status
+read_hw_efuse_88xx(struct halmac_adapter *adapter, u32 offset, u32 size,
+		   u8 *map);
+
+static enum halmac_ret_status
+eeprom_parser_88xx(struct halmac_adapter *adapter, u8 *phy_map, u8 *log_map);
+
+static enum halmac_ret_status
+read_log_efuse_map_88xx(struct halmac_adapter *adapter, u8 *map);
+
+static enum halmac_ret_status
+proc_pg_efuse_by_map_88xx(struct halmac_adapter *adapter,
+			  struct halmac_pg_efuse_info *info,
+			  enum halmac_efuse_read_cfg cfg);
+
+static enum halmac_ret_status
+dump_efuse_fw_88xx(struct halmac_adapter *adapter);
+
+static enum halmac_ret_status
+dump_efuse_drv_88xx(struct halmac_adapter *adapter);
+
+static enum halmac_ret_status
+proc_write_log_efuse_88xx(struct halmac_adapter *adapter, u32 offset, u8 value);
+
+static enum halmac_ret_status
+update_eeprom_mask_88xx(struct halmac_adapter *adapter,
+			struct halmac_pg_efuse_info *info, u8 *updated_mask);
+
+static enum halmac_ret_status
+check_efuse_enough_88xx(struct halmac_adapter *adapter,
+			struct halmac_pg_efuse_info *info, u8 *updated_mask);
+
+static enum halmac_ret_status
+pg_extend_efuse_88xx(struct halmac_adapter *adapter,
+		     struct halmac_pg_efuse_info *info, u8 word_en,
+		     u8 pre_word_en, u32 eeprom_offset);
+
+static enum halmac_ret_status
+proc_pg_efuse_88xx(struct halmac_adapter *adapter,
+		   struct halmac_pg_efuse_info *info, u8 word_en,
+		   u8 pre_word_en, u32 eeprom_offset);
+
+static enum halmac_ret_status
+program_efuse_88xx(struct halmac_adapter *adapter,
+		   struct halmac_pg_efuse_info *info, u8 *updated_mask);
+
+static void
+mask_eeprom_88xx(struct halmac_adapter *adapter,
+		 struct halmac_pg_efuse_info *info);
+
+/**
+ * dump_efuse_map_88xx() - dump "physical" efuse map
+ * @adapter : the adapter of halmac
+ * @cfg : dump efuse method
+ * Author : Ivan Lin/KaiYuan Chang
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+dump_efuse_map_88xx(struct halmac_adapter *adapter,
+		    enum halmac_efuse_read_cfg cfg)
+{
+	u8 *map = NULL;
+	u8 *efuse_map;
+	u32 efuse_size = adapter->hw_cfg_info.efuse_size;
+	enum halmac_ret_status status = HALMAC_RET_SUCCESS;
+	enum halmac_cmd_process_status *proc_status;
+
+	proc_status = &adapter->halmac_state.efuse_state.proc_status;
+
+	if (cfg == HALMAC_EFUSE_R_FW &&
+	    halmac_fw_validate(adapter) != HALMAC_RET_SUCCESS)
+		return HALMAC_RET_NO_DLFW;
+
+	PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
+	PLTFM_MSG_TRACE("[TRACE]cfg = %d\n", cfg);
+
+	if (*proc_status == HALMAC_CMD_PROCESS_SENDING) {
+		PLTFM_MSG_WARN("[WARN]Wait event(efuse)\n");
+		return HALMAC_RET_BUSY_STATE;
+	}
+
+	if (efuse_cmd_cnstr_state_88xx(adapter) != HALMAC_CMD_CNSTR_IDLE) {
+		PLTFM_MSG_WARN("[WARN]Not idle(efuse)\n");
+		return HALMAC_RET_ERROR_STATE;
+	}
+
+	if (adapter->halmac_state.mac_pwr == HALMAC_MAC_POWER_OFF)
+		PLTFM_MSG_ERR("[ERR]Dump efuse in suspend\n");
+
+	*proc_status = HALMAC_CMD_PROCESS_IDLE;
+	adapter->evnt.phy_efuse_map = 1;
+
+	status = switch_efuse_bank_88xx(adapter, HALMAC_EFUSE_BANK_WIFI);
+	if (status != HALMAC_RET_SUCCESS) {
+		PLTFM_MSG_ERR("[ERR]switch efuse bank!!\n");
+		return status;
+	}
+
+	status = proc_dump_efuse_88xx(adapter, cfg);
+	if (status != HALMAC_RET_SUCCESS) {
+		PLTFM_MSG_ERR("[ERR]dump efuse!!\n");
+		return status;
+	}
+
+	if (adapter->efuse_map_valid == 1) {
+		*proc_status = HALMAC_CMD_PROCESS_DONE;
+		efuse_map = adapter->efuse_map;
+
+		map = (u8 *)PLTFM_MALLOC(efuse_size);
+		if (!map) {
+			PLTFM_MSG_ERR("[ERR]malloc!!\n");
+			return HALMAC_RET_MALLOC_FAIL;
+		}
+		PLTFM_MEMSET(map, 0xFF, efuse_size);
+		PLTFM_MUTEX_LOCK(&adapter->efuse_mutex);
+		PLTFM_MEMCPY(map, efuse_map, efuse_size - PROTECT_EFUSE_SIZE);
+		PLTFM_MEMCPY(map + efuse_size - PROTECT_EFUSE_SIZE +
+			     RSVD_CS_EFUSE_SIZE,
+			     efuse_map + efuse_size - PROTECT_EFUSE_SIZE +
+			     RSVD_CS_EFUSE_SIZE,
+			     PROTECT_EFUSE_SIZE - RSVD_EFUSE_SIZE -
+			     RSVD_CS_EFUSE_SIZE);
+		PLTFM_MUTEX_UNLOCK(&adapter->efuse_mutex);
+
+		PLTFM_EVENT_SIG(HALMAC_FEATURE_DUMP_PHYSICAL_EFUSE,
+				*proc_status, map, efuse_size);
+		adapter->evnt.phy_efuse_map = 0;
+
+		PLTFM_FREE(map, efuse_size);
+	}
+
+	if (cnv_efuse_state_88xx(adapter, HALMAC_CMD_CNSTR_IDLE) !=
+	    HALMAC_RET_SUCCESS)
+		return HALMAC_RET_ERROR_STATE;
+
+	PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
+
+	return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * dump_efuse_map_bt_88xx() - dump "BT physical" efuse map
+ * @adapter : the adapter of halmac
+ * @bank : bt efuse bank
+ * @size : bt efuse map size. get from halmac_get_efuse_size API
+ * @map : bt efuse map
+ * Author : Soar / Ivan Lin
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+dump_efuse_map_bt_88xx(struct halmac_adapter *adapter,
+		       enum halmac_efuse_bank bank, u32 size, u8 *map)
+{
+	enum halmac_ret_status status = HALMAC_RET_SUCCESS;
+	enum halmac_cmd_process_status *proc_status;
+
+	proc_status = &adapter->halmac_state.efuse_state.proc_status;
+
+	PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
+
+	if (adapter->hw_cfg_info.bt_efuse_size != size)
+		return HALMAC_RET_EFUSE_SIZE_INCORRECT;
+
+	if (bank >= HALMAC_EFUSE_BANK_MAX || bank == HALMAC_EFUSE_BANK_WIFI) {
+		PLTFM_MSG_ERR("[ERR]Undefined BT bank\n");
+		return HALMAC_RET_EFUSE_BANK_INCORRECT;
+	}
+
+	if (*proc_status == HALMAC_CMD_PROCESS_SENDING) {
+		PLTFM_MSG_WARN("[WARN]Wait event(efuse)\n");
+		return HALMAC_RET_BUSY_STATE;
+	}
+
+	if (efuse_cmd_cnstr_state_88xx(adapter) != HALMAC_CMD_CNSTR_IDLE) {
+		PLTFM_MSG_WARN("[WARN]Not idle(efuse)\n");
+		return HALMAC_RET_ERROR_STATE;
+	}
+
+	status = switch_efuse_bank_88xx(adapter, bank);
+	if (status != HALMAC_RET_SUCCESS) {
+		PLTFM_MSG_ERR("[ERR]switch efuse bank!!\n");
+		return status;
+	}
+
+	status = read_hw_efuse_88xx(adapter, 0, size, map);
+	if (status != HALMAC_RET_SUCCESS) {
+		PLTFM_MSG_ERR("[ERR]read hw efuse\n");
+		return status;
+	}
+
+	if (cnv_efuse_state_88xx(adapter, HALMAC_CMD_CNSTR_IDLE) !=
+	    HALMAC_RET_SUCCESS)
+		return HALMAC_RET_ERROR_STATE;
+
+	PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
+
+	return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * write_efuse_bt_88xx() - write "BT physical" efuse offset
+ * @adapter : the adapter of halmac
+ * @offset : offset
+ * @value : Write value
+ * @map : bt efuse map
+ * Author : Soar
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+write_efuse_bt_88xx(struct halmac_adapter *adapter, u32 offset, u8 value,
+		    enum halmac_efuse_bank bank)
+{
+	enum halmac_ret_status status = HALMAC_RET_SUCCESS;
+	enum halmac_cmd_process_status *proc_status;
+
+	proc_status = &adapter->halmac_state.efuse_state.proc_status;
+
+	PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
+
+	if (*proc_status == HALMAC_CMD_PROCESS_SENDING) {
+		PLTFM_MSG_WARN("[WARN]Wait event(efuse)\n");
+		return HALMAC_RET_BUSY_STATE;
+	}
+
+	if (efuse_cmd_cnstr_state_88xx(adapter) != HALMAC_CMD_CNSTR_IDLE) {
+		PLTFM_MSG_WARN("[WARN]Not idle(efuse)\n");
+		return HALMAC_RET_ERROR_STATE;
+	}
+
+	if (offset >= adapter->hw_cfg_info.efuse_size) {
+		PLTFM_MSG_ERR("[ERR]Offset is too large\n");
+		return HALMAC_RET_EFUSE_SIZE_INCORRECT;
+	}
+
+	if (bank > HALMAC_EFUSE_BANK_MAX || bank == HALMAC_EFUSE_BANK_WIFI) {
+		PLTFM_MSG_ERR("[ERR]Undefined BT bank\n");
+		return HALMAC_RET_EFUSE_BANK_INCORRECT;
+	}
+
+	status = switch_efuse_bank_88xx(adapter, bank);
+	if (status != HALMAC_RET_SUCCESS) {
+		PLTFM_MSG_ERR("[ERR]switch efuse bank!!\n");
+		return status;
+	}
+
+	status = write_hw_efuse_88xx(adapter, offset, value);
+	if (status != HALMAC_RET_SUCCESS) {
+		PLTFM_MSG_ERR("[ERR]write efuse\n");
+		return status;
+	}
+
+	if (cnv_efuse_state_88xx(adapter, HALMAC_CMD_CNSTR_IDLE) !=
+	    HALMAC_RET_SUCCESS)
+		return HALMAC_RET_ERROR_STATE;
+
+	PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
+
+	return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * read_efuse_bt_88xx() - read "BT physical" efuse offset
+ * @adapter : the adapter of halmac
+ * @offset : offset
+ * @value : 1 byte efuse value
+ * @bank : efuse bank
+ * Author : Soar
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+read_efuse_bt_88xx(struct halmac_adapter *adapter, u32 offset, u8 *value,
+		   enum halmac_efuse_bank bank)
+{
+	enum halmac_ret_status status = HALMAC_RET_SUCCESS;
+	enum halmac_cmd_process_status *proc_status;
+
+	proc_status = &adapter->halmac_state.efuse_state.proc_status;
+
+	PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
+
+	if (*proc_status == HALMAC_CMD_PROCESS_SENDING) {
+		PLTFM_MSG_WARN("[WARN]Wait event(efuse)\n");
+		return HALMAC_RET_BUSY_STATE;
+	}
+
+	if (efuse_cmd_cnstr_state_88xx(adapter) != HALMAC_CMD_CNSTR_IDLE) {
+		PLTFM_MSG_WARN("[WARN]Not idle(efuse)\n");
+		return HALMAC_RET_ERROR_STATE;
+	}
+
+	if (offset >= adapter->hw_cfg_info.efuse_size) {
+		PLTFM_MSG_ERR("[ERR]Offset is too large\n");
+		return HALMAC_RET_EFUSE_SIZE_INCORRECT;
+	}
+
+	if (bank > HALMAC_EFUSE_BANK_MAX || bank == HALMAC_EFUSE_BANK_WIFI) {
+		PLTFM_MSG_ERR("[ERR]Undefined BT bank\n");
+		return HALMAC_RET_EFUSE_BANK_INCORRECT;
+	}
+
+	status = switch_efuse_bank_88xx(adapter, bank);
+	if (status != HALMAC_RET_SUCCESS) {
+		PLTFM_MSG_ERR("[ERR]switch efuse bank\n");
+		return status;
+	}
+
+	status = read_efuse_88xx(adapter, offset, 1, value);
+	if (status != HALMAC_RET_SUCCESS) {
+		PLTFM_MSG_ERR("[ERR]read efuse\n");
+		return status;
+	}
+
+	if (cnv_efuse_state_88xx(adapter, HALMAC_CMD_CNSTR_IDLE) !=
+	    HALMAC_RET_SUCCESS)
+		return HALMAC_RET_ERROR_STATE;
+
+	PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
+
+	return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * cfg_efuse_auto_check_88xx() - check efuse after writing it
+ * @adapter : the adapter of halmac
+ * @enable : 1, enable efuse auto check. others, disable
+ * Author : Soar
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+cfg_efuse_auto_check_88xx(struct halmac_adapter *adapter, u8 enable)
+{
+	PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
+
+	adapter->efuse_auto_check_en = enable;
+
+	PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
+
+	return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * get_efuse_available_size_88xx() - get efuse available size
+ * @adapter : the adapter of halmac
+ * @size : physical efuse available size
+ * Author : Soar
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+get_efuse_available_size_88xx(struct halmac_adapter *adapter, u32 *size)
+{
+	enum halmac_ret_status status;
+
+	PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
+
+	status = dump_log_efuse_map_88xx(adapter, HALMAC_EFUSE_R_DRV);
+
+	if (status != HALMAC_RET_SUCCESS)
+		return status;
+
+	*size = adapter->hw_cfg_info.efuse_size - PROTECT_EFUSE_SIZE -
+		adapter->efuse_end;
+
+	PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
+
+	return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * get_efuse_size_88xx() - get "physical" efuse size
+ * @adapter : the adapter of halmac
+ * @size : physical efuse size
+ * Author : Ivan Lin/KaiYuan Chang
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+get_efuse_size_88xx(struct halmac_adapter *adapter, u32 *size)
+{
+	PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
+
+	*size = adapter->hw_cfg_info.efuse_size;
+
+	PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
+
+	return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * get_log_efuse_size_88xx() - get "logical" efuse size
+ * @adapter : the adapter of halmac
+ * @size : logical efuse size
+ * Author : Ivan Lin/KaiYuan Chang
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+get_log_efuse_size_88xx(struct halmac_adapter *adapter, u32 *size)
+{
+	PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
+
+	*size = adapter->hw_cfg_info.eeprom_size;
+
+	PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
+
+	return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * dump_log_efuse_map_88xx() - dump "logical" efuse map
+ * @adapter : the adapter of halmac
+ * @cfg : dump efuse method
+ * Author : Soar
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+dump_log_efuse_map_88xx(struct halmac_adapter *adapter,
+			enum halmac_efuse_read_cfg cfg)
+{
+	u8 *map = NULL;
+	u32 size = adapter->hw_cfg_info.eeprom_size;
+	enum halmac_ret_status status = HALMAC_RET_SUCCESS;
+	enum halmac_cmd_process_status *proc_status;
+
+	proc_status = &adapter->halmac_state.efuse_state.proc_status;
+
+	if (cfg == HALMAC_EFUSE_R_FW &&
+	    halmac_fw_validate(adapter) != HALMAC_RET_SUCCESS)
+		return HALMAC_RET_NO_DLFW;
+
+	PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
+	PLTFM_MSG_TRACE("[TRACE]cfg = %d\n", cfg);
+
+	if (*proc_status == HALMAC_CMD_PROCESS_SENDING) {
+		PLTFM_MSG_WARN("[WARN]Wait event(efuse)\n");
+		return HALMAC_RET_BUSY_STATE;
+	}
+
+	if (efuse_cmd_cnstr_state_88xx(adapter) != HALMAC_CMD_CNSTR_IDLE) {
+		PLTFM_MSG_WARN("[WARN]Not idle(efuse)\n");
+		return HALMAC_RET_ERROR_STATE;
+	}
+
+	if (adapter->halmac_state.mac_pwr == HALMAC_MAC_POWER_OFF)
+		PLTFM_MSG_ERR("[ERR]Dump efuse in suspend\n");
+
+	*proc_status = HALMAC_CMD_PROCESS_IDLE;
+	adapter->evnt.log_efuse_map = 1;
+
+	status = switch_efuse_bank_88xx(adapter, HALMAC_EFUSE_BANK_WIFI);
+	if (status != HALMAC_RET_SUCCESS) {
+		PLTFM_MSG_ERR("[ERR]switch efuse bank\n");
+		return status;
+	}
+
+	status = proc_dump_efuse_88xx(adapter, cfg);
+	if (status != HALMAC_RET_SUCCESS) {
+		PLTFM_MSG_ERR("[ERR]dump efuse\n");
+		return status;
+	}
+
+	if (adapter->efuse_map_valid == 1) {
+		*proc_status = HALMAC_CMD_PROCESS_DONE;
+
+		map = (u8 *)PLTFM_MALLOC(size);
+		if (!map) {
+			PLTFM_MSG_ERR("[ERR]malloc map\n");
+			return HALMAC_RET_MALLOC_FAIL;
+		}
+		PLTFM_MEMSET(map, 0xFF, size);
+
+		if (eeprom_parser_88xx(adapter, adapter->efuse_map, map) !=
+		    HALMAC_RET_SUCCESS) {
+			PLTFM_FREE(map, size);
+			return HALMAC_RET_EEPROM_PARSING_FAIL;
+		}
+
+		PLTFM_EVENT_SIG(HALMAC_FEATURE_DUMP_LOGICAL_EFUSE,
+				*proc_status, map, size);
+		adapter->evnt.log_efuse_map = 0;
+
+		PLTFM_FREE(map, size);
+	}
+
+	if (cnv_efuse_state_88xx(adapter, HALMAC_CMD_CNSTR_IDLE) !=
+	    HALMAC_RET_SUCCESS)
+		return HALMAC_RET_ERROR_STATE;
+
+	PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
+
+	return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * read_logical_efuse_88xx() - read logical efuse map 1 byte
+ * @adapter : the adapter of halmac
+ * @offset : offset
+ * @value : 1 byte efuse value
+ * Author : Soar
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+read_logical_efuse_88xx(struct halmac_adapter *adapter, u32 offset, u8 *value)
+{
+	u8 *map = NULL;
+	u32 size = adapter->hw_cfg_info.eeprom_size;
+	enum halmac_ret_status status = HALMAC_RET_SUCCESS;
+	enum halmac_cmd_process_status *proc_status;
+
+	proc_status = &adapter->halmac_state.efuse_state.proc_status;
+
+	PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
+
+	if (offset >= size) {
+		PLTFM_MSG_ERR("[ERR]Offset is too large\n");
+		return HALMAC_RET_EFUSE_SIZE_INCORRECT;
+	}
+
+	if (*proc_status == HALMAC_CMD_PROCESS_SENDING) {
+		PLTFM_MSG_WARN("[WARN]Wait event(efuse)\n");
+		return HALMAC_RET_BUSY_STATE;
+	}
+	if (efuse_cmd_cnstr_state_88xx(adapter) != HALMAC_CMD_CNSTR_IDLE) {
+		PLTFM_MSG_WARN("[WARN]Not idle(efuse)\n");
+		return HALMAC_RET_ERROR_STATE;
+	}
+
+	status = switch_efuse_bank_88xx(adapter, HALMAC_EFUSE_BANK_WIFI);
+	if (status != HALMAC_RET_SUCCESS) {
+		PLTFM_MSG_ERR("[ERR]switch efuse bank\n");
+		return status;
+	}
+
+	map = (u8 *)PLTFM_MALLOC(size);
+	if (!map) {
+		PLTFM_MSG_ERR("[ERR]malloc map\n");
+		return HALMAC_RET_MALLOC_FAIL;
+	}
+	PLTFM_MEMSET(map, 0xFF, size);
+
+	status = read_log_efuse_map_88xx(adapter, map);
+	if (status != HALMAC_RET_SUCCESS) {
+		PLTFM_MSG_ERR("[ERR]read logical efuse\n");
+		PLTFM_FREE(map, size);
+		return status;
+	}
+
+	*value = *(map + offset);
+
+	if (cnv_efuse_state_88xx(adapter, HALMAC_CMD_CNSTR_IDLE) !=
+	    HALMAC_RET_SUCCESS) {
+		PLTFM_FREE(map, size);
+		return HALMAC_RET_ERROR_STATE;
+	}
+
+	PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
+
+	PLTFM_FREE(map, size);
+
+	return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * write_log_efuse_88xx() - write "logical" efuse offset
+ * @adapter : the adapter of halmac
+ * @offset : offset
+ * @value : value
+ * Author : Soar
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+write_log_efuse_88xx(struct halmac_adapter *adapter, u32 offset, u8 value)
+{
+	enum halmac_ret_status status = HALMAC_RET_SUCCESS;
+	enum halmac_cmd_process_status *proc_status;
+
+	proc_status = &adapter->halmac_state.efuse_state.proc_status;
+
+	PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
+
+	if (offset >= adapter->hw_cfg_info.eeprom_size) {
+		PLTFM_MSG_ERR("[ERR]Offset is too large\n");
+		return HALMAC_RET_EFUSE_SIZE_INCORRECT;
+	}
+
+	if (*proc_status == HALMAC_CMD_PROCESS_SENDING) {
+		PLTFM_MSG_WARN("[WARN]Wait event(efuse)\n");
+		return HALMAC_RET_BUSY_STATE;
+	}
+
+	if (efuse_cmd_cnstr_state_88xx(adapter) != HALMAC_CMD_CNSTR_IDLE) {
+		PLTFM_MSG_WARN("[WARN]Not idle(efuse)\n");
+		return HALMAC_RET_ERROR_STATE;
+	}
+
+	status = switch_efuse_bank_88xx(adapter, HALMAC_EFUSE_BANK_WIFI);
+	if (status != HALMAC_RET_SUCCESS) {
+		PLTFM_MSG_ERR("[ERR]switch efuse bank\n");
+		return status;
+	}
+
+	status = proc_write_log_efuse_88xx(adapter, offset, value);
+	if (status != HALMAC_RET_SUCCESS) {
+		PLTFM_MSG_ERR("[ERR]write logical efuse\n");
+		return status;
+	}
+
+	if (cnv_efuse_state_88xx(adapter, HALMAC_CMD_CNSTR_IDLE) !=
+	    HALMAC_RET_SUCCESS)
+		return HALMAC_RET_ERROR_STATE;
+
+	PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
+
+	return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * pg_efuse_by_map_88xx() - pg logical efuse by map
+ * @adapter : the adapter of halmac
+ * @info : efuse map information
+ * @cfg : dump efuse method
+ * Author : Soar
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+pg_efuse_by_map_88xx(struct halmac_adapter *adapter,
+		     struct halmac_pg_efuse_info *info,
+		     enum halmac_efuse_read_cfg cfg)
+{
+	enum halmac_ret_status status = HALMAC_RET_SUCCESS;
+	enum halmac_cmd_process_status *proc_status;
+
+	proc_status = &adapter->halmac_state.efuse_state.proc_status;
+
+	PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
+
+	if (info->efuse_map_size != adapter->hw_cfg_info.eeprom_size) {
+		PLTFM_MSG_ERR("[ERR]map size error\n");
+		return HALMAC_RET_EFUSE_SIZE_INCORRECT;
+	}
+
+	if ((info->efuse_map_size & 0xF) > 0) {
+		PLTFM_MSG_ERR("[ERR]not multiple of 16\n");
+		return HALMAC_RET_EFUSE_SIZE_INCORRECT;
+	}
+
+	if (info->efuse_mask_size != info->efuse_map_size >> 4) {
+		PLTFM_MSG_ERR("[ERR]mask size error\n");
+		return HALMAC_RET_EFUSE_SIZE_INCORRECT;
+	}
+
+	if (!info->efuse_map) {
+		PLTFM_MSG_ERR("[ERR]map is NULL\n");
+		return HALMAC_RET_NULL_POINTER;
+	}
+
+	if (!info->efuse_mask) {
+		PLTFM_MSG_ERR("[ERR]mask is NULL\n");
+		return HALMAC_RET_NULL_POINTER;
+	}
+
+	if (*proc_status == HALMAC_CMD_PROCESS_SENDING) {
+		PLTFM_MSG_WARN("[WARN]Wait event(efuse)\n");
+		return HALMAC_RET_BUSY_STATE;
+	}
+
+	if (efuse_cmd_cnstr_state_88xx(adapter) != HALMAC_CMD_CNSTR_IDLE) {
+		PLTFM_MSG_WARN("[WARN]Not idle(efuse)\n");
+		return HALMAC_RET_ERROR_STATE;
+	}
+
+	status = switch_efuse_bank_88xx(adapter, HALMAC_EFUSE_BANK_WIFI);
+	if (status != HALMAC_RET_SUCCESS) {
+		PLTFM_MSG_ERR("[ERR]switch efuse bank\n");
+		return status;
+	}
+
+	status = proc_pg_efuse_by_map_88xx(adapter, info, cfg);
+	if (status != HALMAC_RET_SUCCESS) {
+		PLTFM_MSG_ERR("[ERR]pg efuse\n");
+		return status;
+	}
+
+	if (cnv_efuse_state_88xx(adapter, HALMAC_CMD_CNSTR_IDLE) !=
+	    HALMAC_RET_SUCCESS)
+		return HALMAC_RET_ERROR_STATE;
+
+	PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
+
+	return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * mask_log_efuse_88xx() - mask logical efuse
+ * @adapter : the adapter of halmac
+ * @info : efuse map information
+ * Author : Soar
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+mask_log_efuse_88xx(struct halmac_adapter *adapter,
+		    struct halmac_pg_efuse_info *info)
+{
+	PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
+
+	if (info->efuse_map_size != adapter->hw_cfg_info.eeprom_size) {
+		PLTFM_MSG_ERR("[ERR]map size error\n");
+		return HALMAC_RET_EFUSE_SIZE_INCORRECT;
+	}
+
+	if ((info->efuse_map_size & 0xF) > 0) {
+		PLTFM_MSG_ERR("[ERR]not multiple of 16\n");
+		return HALMAC_RET_EFUSE_SIZE_INCORRECT;
+	}
+
+	if (info->efuse_mask_size != info->efuse_map_size >> 4) {
+		PLTFM_MSG_ERR("[ERR]mask size error\n");
+		return HALMAC_RET_EFUSE_SIZE_INCORRECT;
+	}
+
+	if (!info->efuse_map) {
+		PLTFM_MSG_ERR("[ERR]map is NULL\n");
+		return HALMAC_RET_NULL_POINTER;
+	}
+
+	if (!info->efuse_mask) {
+		PLTFM_MSG_ERR("[ERR]mask is NULL\n");
+		return HALMAC_RET_NULL_POINTER;
+	}
+
+	mask_eeprom_88xx(adapter, info);
+
+	PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
+
+	return HALMAC_RET_SUCCESS;
+}
+
+static enum halmac_cmd_construct_state
+efuse_cmd_cnstr_state_88xx(struct halmac_adapter *adapter)
+{
+	return adapter->halmac_state.efuse_state.cmd_cnstr_state;
+}
+
+enum halmac_ret_status
+switch_efuse_bank_88xx(struct halmac_adapter *adapter,
+		       enum halmac_efuse_bank bank)
+{
+	u8 reg_value;
+	struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
+
+	if (cnv_efuse_state_88xx(adapter, HALMAC_CMD_CNSTR_BUSY) !=
+	    HALMAC_RET_SUCCESS)
+		return HALMAC_RET_ERROR_STATE;
+
+	reg_value = HALMAC_REG_R8(REG_LDO_EFUSE_CTRL + 1);
+
+	if (bank == (reg_value & (BIT(0) | BIT(1))))
+		return HALMAC_RET_SUCCESS;
+
+	reg_value &= ~(BIT(0) | BIT(1));
+	reg_value |= bank;
+	HALMAC_REG_W8(REG_LDO_EFUSE_CTRL + 1, reg_value);
+
+	reg_value = HALMAC_REG_R8(REG_LDO_EFUSE_CTRL + 1);
+	if ((reg_value & (BIT(0) | BIT(1))) != bank)
+		return HALMAC_RET_SWITCH_EFUSE_BANK_FAIL;
+
+	return HALMAC_RET_SUCCESS;
+}
+
+static enum halmac_ret_status
+proc_dump_efuse_88xx(struct halmac_adapter *adapter,
+		     enum halmac_efuse_read_cfg cfg)
+{
+	u32 h2c_init;
+	struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
+	enum halmac_ret_status status = HALMAC_RET_SUCCESS;
+	enum halmac_cmd_process_status *proc_status;
+
+	proc_status = &adapter->halmac_state.efuse_state.proc_status;
+
+	*proc_status = HALMAC_CMD_PROCESS_SENDING;
+
+	if (cnv_efuse_state_88xx(adapter, HALMAC_CMD_CNSTR_H2C_SENT) !=
+	    HALMAC_RET_SUCCESS)
+		return HALMAC_RET_ERROR_STATE;
+
+	if (cfg == HALMAC_EFUSE_R_AUTO) {
+		h2c_init = HALMAC_REG_R32(REG_H2C_PKT_READADDR);
+		if (adapter->halmac_state.dlfw_state == HALMAC_DLFW_NONE ||
+		    h2c_init == 0)
+			status = dump_efuse_drv_88xx(adapter);
+		else
+			status = dump_efuse_fw_88xx(adapter);
+	} else if (cfg == HALMAC_EFUSE_R_FW) {
+		status = dump_efuse_fw_88xx(adapter);
+	} else {
+		status = dump_efuse_drv_88xx(adapter);
+	}
+
+	if (status != HALMAC_RET_SUCCESS) {
+		PLTFM_MSG_ERR("[ERR]dump efsue drv/fw\n");
+		return status;
+	}
+
+	return status;
+}
+
+enum halmac_ret_status
+cnv_efuse_state_88xx(struct halmac_adapter *adapter,
+		     enum halmac_cmd_construct_state dest_state)
+{
+	struct halmac_efuse_state *state = &adapter->halmac_state.efuse_state;
+
+	if (state->cmd_cnstr_state != HALMAC_CMD_CNSTR_IDLE &&
+	    state->cmd_cnstr_state != HALMAC_CMD_CNSTR_BUSY &&
+	    state->cmd_cnstr_state != HALMAC_CMD_CNSTR_H2C_SENT)
+		return HALMAC_RET_ERROR_STATE;
+
+	if (state->cmd_cnstr_state == dest_state)
+		return HALMAC_RET_ERROR_STATE;
+
+	if (dest_state == HALMAC_CMD_CNSTR_BUSY) {
+		if (state->cmd_cnstr_state == HALMAC_CMD_CNSTR_H2C_SENT)
+			return HALMAC_RET_ERROR_STATE;
+	} else if (dest_state == HALMAC_CMD_CNSTR_H2C_SENT) {
+		if (state->cmd_cnstr_state == HALMAC_CMD_CNSTR_IDLE)
+			return HALMAC_RET_ERROR_STATE;
+	}
+
+	state->cmd_cnstr_state = dest_state;
+
+	return HALMAC_RET_SUCCESS;
+}
+
+static enum halmac_ret_status
+read_hw_efuse_88xx(struct halmac_adapter *adapter, u32 offset, u32 size,
+		   u8 *map)
+{
+	u8 enable;
+	u32 value32;
+	u32 addr;
+	u32 tmp32;
+	u32 cnt;
+	enum halmac_ret_status status = HALMAC_RET_SUCCESS;
+	struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
+
+	/* Read efuse no need 2.5V LDO */
+	enable = 0;
+	status = api->halmac_set_hw_value(adapter, HALMAC_HW_LDO25_EN, &enable);
+	if (status != HALMAC_RET_SUCCESS) {
+		PLTFM_MSG_ERR("[ERR]dis ldo25\n");
+		return status;
+	}
+	value32 = HALMAC_REG_R32(REG_EFUSE_CTRL);
+
+	for (addr = offset; addr < offset + size; addr++) {
+		value32 &= ~(BIT_MASK_EF_DATA | BITS_EF_ADDR);
+		value32 |= ((addr & BIT_MASK_EF_ADDR) << BIT_SHIFT_EF_ADDR);
+		HALMAC_REG_W32(REG_EFUSE_CTRL, value32 & (~BIT_EF_FLAG));
+
+		cnt = 1000000;
+		do {
+			PLTFM_DELAY_US(1);
+			tmp32 = HALMAC_REG_R32(REG_EFUSE_CTRL);
+			cnt--;
+			if (cnt == 0) {
+				PLTFM_MSG_ERR("[ERR]read\n");
+				return HALMAC_RET_EFUSE_R_FAIL;
+			}
+		} while ((tmp32 & BIT_EF_FLAG) == 0);
+
+		*(map + addr - offset) = (u8)(tmp32 & BIT_MASK_EF_DATA);
+	}
+
+	return HALMAC_RET_SUCCESS;
+}
+
+enum halmac_ret_status
+write_hw_efuse_88xx(struct halmac_adapter *adapter, u32 offset, u8 value)
+{
+	const u8 unlock_code = 0x69;
+	u8 value_read = 0;
+	u8 enable;
+	u32 value32;
+	u32 tmp32;
+	u32 cnt;
+	enum halmac_ret_status status = HALMAC_RET_SUCCESS;
+	struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
+
+	PLTFM_MUTEX_LOCK(&adapter->efuse_mutex);
+	adapter->efuse_map_valid = 0;
+	PLTFM_MUTEX_UNLOCK(&adapter->efuse_mutex);
+
+	HALMAC_REG_W8(REG_PMC_DBG_CTRL2 + 3, unlock_code);
+
+	/* Enable 2.5V LDO */
+	enable = 1;
+	status = api->halmac_set_hw_value(adapter, HALMAC_HW_LDO25_EN, &enable);
+	if (status != HALMAC_RET_SUCCESS) {
+		PLTFM_MSG_ERR("[ERR]en ldo25\n");
+		return status;
+	}
+
+	value32 = HALMAC_REG_R32(REG_EFUSE_CTRL);
+	value32 &= ~(BIT_MASK_EF_DATA | BITS_EF_ADDR);
+	value32 = value32 | ((offset & BIT_MASK_EF_ADDR) << BIT_SHIFT_EF_ADDR) |
+			(value & BIT_MASK_EF_DATA);
+	HALMAC_REG_W32(REG_EFUSE_CTRL, value32 | BIT_EF_FLAG);
+
+	cnt = 1000000;
+	do {
+		PLTFM_DELAY_US(1);
+		tmp32 = HALMAC_REG_R32(REG_EFUSE_CTRL);
+		cnt--;
+		if (cnt == 0) {
+			PLTFM_MSG_ERR("[ERR]write!!\n");
+			return HALMAC_RET_EFUSE_W_FAIL;
+		}
+	} while (BIT_EF_FLAG == (tmp32 & BIT_EF_FLAG));
+
+	HALMAC_REG_W8(REG_PMC_DBG_CTRL2 + 3, 0x00);
+
+	/* Disable 2.5V LDO */
+	enable = 0;
+	status = api->halmac_set_hw_value(adapter, HALMAC_HW_LDO25_EN, &enable);
+	if (status != HALMAC_RET_SUCCESS) {
+		PLTFM_MSG_ERR("[ERR]dis ldo25\n");
+		return status;
+	}
+
+	if (adapter->efuse_auto_check_en == 1) {
+		if (read_hw_efuse_88xx(adapter, offset, 1, &value_read) !=
+		    HALMAC_RET_SUCCESS)
+			return HALMAC_RET_EFUSE_R_FAIL;
+		if (value_read != value) {
+			PLTFM_MSG_ERR("[ERR]efuse compare\n");
+			return HALMAC_RET_EFUSE_W_FAIL;
+		}
+	}
+
+	return HALMAC_RET_SUCCESS;
+}
+
+static enum halmac_ret_status
+eeprom_parser_88xx(struct halmac_adapter *adapter, u8 *phy_map, u8 *log_map)
+{
+	u8 i;
+	u8 value8;
+	u8 blk_idx;
+	u8 word_en;
+	u8 valid;
+	u8 hdr;
+	u8 hdr2 = 0;
+	u32 eeprom_idx;
+	u32 efuse_idx = 0;
+	struct halmac_hw_cfg_info *hw_info = &adapter->hw_cfg_info;
+
+	PLTFM_MEMSET(log_map, 0xFF, hw_info->eeprom_size);
+
+	do {
+		value8 = *(phy_map + efuse_idx);
+		hdr = value8;
+
+		if ((hdr & 0x1f) == 0x0f) {
+			efuse_idx++;
+			value8 = *(phy_map + efuse_idx);
+			hdr2 = value8;
+			if (hdr2 == 0xff)
+				break;
+			blk_idx = ((hdr2 & 0xF0) >> 1) | ((hdr >> 5) & 0x07);
+			word_en = hdr2 & 0x0F;
+		} else {
+			blk_idx = (hdr & 0xF0) >> 4;
+			word_en = hdr & 0x0F;
+		}
+
+		if (hdr == 0xff)
+			break;
+
+		efuse_idx++;
+
+		if (efuse_idx >= hw_info->efuse_size - PROTECT_EFUSE_SIZE - 1)
+			return HALMAC_RET_EEPROM_PARSING_FAIL;
+
+		for (i = 0; i < 4; i++) {
+			valid = (u8)((~(word_en >> i)) & BIT(0));
+			if (valid == 1) {
+				eeprom_idx = (blk_idx << 3) + (i << 1);
+
+				if ((eeprom_idx + 1) > hw_info->eeprom_size) {
+					PLTFM_MSG_ERR("[ERR]efuse idx:0x%X\n",
+						      efuse_idx - 1);
+
+					PLTFM_MSG_ERR("[ERR]read hdr:0x%X\n",
+						      hdr);
+
+					PLTFM_MSG_ERR("[ERR]rad hdr2:0x%X\n",
+						      hdr2);
+
+					return HALMAC_RET_EEPROM_PARSING_FAIL;
+				}
+
+				value8 = *(phy_map + efuse_idx);
+				*(log_map + eeprom_idx) = value8;
+
+				eeprom_idx++;
+				efuse_idx++;
+
+				if (efuse_idx > hw_info->efuse_size -
+				    PROTECT_EFUSE_SIZE - 1)
+					return HALMAC_RET_EEPROM_PARSING_FAIL;
+
+				value8 = *(phy_map + efuse_idx);
+				*(log_map + eeprom_idx) = value8;
+
+				efuse_idx++;
+
+				if (efuse_idx > hw_info->efuse_size -
+				    PROTECT_EFUSE_SIZE)
+					return HALMAC_RET_EEPROM_PARSING_FAIL;
+			}
+		}
+	} while (1);
+
+	adapter->efuse_end = efuse_idx;
+
+	return HALMAC_RET_SUCCESS;
+}
+
+static enum halmac_ret_status
+read_log_efuse_map_88xx(struct halmac_adapter *adapter, u8 *map)
+{
+	u8 *local_map = NULL;
+	u32 efuse_size;
+	enum halmac_ret_status status = HALMAC_RET_SUCCESS;
+
+	if (adapter->efuse_map_valid == 0) {
+		efuse_size = adapter->hw_cfg_info.efuse_size;
+
+		local_map = (u8 *)PLTFM_MALLOC(efuse_size);
+		if (!local_map) {
+			PLTFM_MSG_ERR("[ERR]local map\n");
+			return HALMAC_RET_MALLOC_FAIL;
+		}
+
+		status = read_efuse_88xx(adapter, 0, efuse_size, local_map);
+		if (status != HALMAC_RET_SUCCESS) {
+			PLTFM_MSG_ERR("[ERR]read efuse\n");
+			PLTFM_FREE(local_map, efuse_size);
+			return status;
+		}
+
+		if (!adapter->efuse_map) {
+			adapter->efuse_map = (u8 *)PLTFM_MALLOC(efuse_size);
+			if (!adapter->efuse_map) {
+				PLTFM_MSG_ERR("[ERR]malloc adapter map\n");
+				PLTFM_FREE(local_map, efuse_size);
+				return HALMAC_RET_MALLOC_FAIL;
+			}
+		}
+
+		PLTFM_MUTEX_LOCK(&adapter->efuse_mutex);
+		PLTFM_MEMCPY(adapter->efuse_map, local_map, efuse_size);
+		adapter->efuse_map_valid = 1;
+		PLTFM_MUTEX_UNLOCK(&adapter->efuse_mutex);
+
+		PLTFM_FREE(local_map, efuse_size);
+	}
+
+	if (eeprom_parser_88xx(adapter, adapter->efuse_map, map) !=
+	    HALMAC_RET_SUCCESS)
+		return HALMAC_RET_EEPROM_PARSING_FAIL;
+
+	return status;
+}
+
+static enum halmac_ret_status
+proc_pg_efuse_by_map_88xx(struct halmac_adapter *adapter,
+			  struct halmac_pg_efuse_info *info,
+			  enum halmac_efuse_read_cfg cfg)
+{
+	u8 *updated_mask = NULL;
+	u32 mask_size = adapter->hw_cfg_info.eeprom_size >> 4;
+	enum halmac_ret_status status = HALMAC_RET_SUCCESS;
+
+	updated_mask = (u8 *)PLTFM_MALLOC(mask_size);
+	if (!updated_mask) {
+		PLTFM_MSG_ERR("[ERR]malloc updated mask\n");
+		return HALMAC_RET_MALLOC_FAIL;
+	}
+	PLTFM_MEMSET(updated_mask, 0x00, mask_size);
+
+	status = update_eeprom_mask_88xx(adapter, info, updated_mask);
+	if (status != HALMAC_RET_SUCCESS) {
+		PLTFM_MSG_ERR("[ERR]update eeprom mask\n");
+		PLTFM_FREE(updated_mask, mask_size);
+		return status;
+	}
+
+	status = check_efuse_enough_88xx(adapter, info, updated_mask);
+	if (status != HALMAC_RET_SUCCESS) {
+		PLTFM_MSG_ERR("[ERR]chk efuse enough\n");
+		PLTFM_FREE(updated_mask, mask_size);
+		return status;
+	}
+
+	status = program_efuse_88xx(adapter, info, updated_mask);
+	if (status != HALMAC_RET_SUCCESS) {
+		PLTFM_MSG_ERR("[ERR]pg efuse\n");
+		PLTFM_FREE(updated_mask, mask_size);
+		return status;
+	}
+
+	PLTFM_FREE(updated_mask, mask_size);
+
+	return HALMAC_RET_SUCCESS;
+}
+
+static enum halmac_ret_status
+dump_efuse_drv_88xx(struct halmac_adapter *adapter)
+{
+	u8 *map = NULL;
+	u32 efuse_size = adapter->hw_cfg_info.efuse_size;
+
+	if (!adapter->efuse_map) {
+		adapter->efuse_map = (u8 *)PLTFM_MALLOC(efuse_size);
+		if (!adapter->efuse_map) {
+			PLTFM_MSG_ERR("[ERR]malloc adapter map!!\n");
+			reset_ofld_feature_88xx(adapter,
+						FEATURE_DUMP_PHY_EFUSE);
+			return HALMAC_RET_MALLOC_FAIL;
+		}
+	}
+
+	if (adapter->efuse_map_valid == 0) {
+		map = (u8 *)PLTFM_MALLOC(efuse_size);
+		if (!map) {
+			PLTFM_MSG_ERR("[ERR]malloc map\n");
+			return HALMAC_RET_MALLOC_FAIL;
+		}
+
+		if (read_hw_efuse_88xx(adapter, 0, efuse_size, map) !=
+		    HALMAC_RET_SUCCESS) {
+			PLTFM_FREE(map, efuse_size);
+			return HALMAC_RET_EFUSE_R_FAIL;
+		}
+
+		PLTFM_MUTEX_LOCK(&adapter->efuse_mutex);
+		PLTFM_MEMCPY(adapter->efuse_map, map, efuse_size);
+		adapter->efuse_map_valid = 1;
+		PLTFM_MUTEX_UNLOCK(&adapter->efuse_mutex);
+
+		PLTFM_FREE(map, efuse_size);
+	}
+
+	return HALMAC_RET_SUCCESS;
+}
+
+static enum halmac_ret_status
+dump_efuse_fw_88xx(struct halmac_adapter *adapter)
+{
+	u8 h2c_buf[H2C_PKT_SIZE_88XX] = { 0 };
+	u16 seq_num = 0;
+	u32 efuse_size = adapter->hw_cfg_info.efuse_size;
+	struct halmac_h2c_header_info hdr_info;
+	enum halmac_ret_status status = HALMAC_RET_SUCCESS;
+
+	hdr_info.sub_cmd_id = SUB_CMD_ID_DUMP_PHYSICAL_EFUSE;
+	hdr_info.content_size = 0;
+	hdr_info.ack = 1;
+	set_h2c_pkt_hdr_88xx(adapter, h2c_buf, &hdr_info, &seq_num);
+
+	adapter->halmac_state.efuse_state.seq_num = seq_num;
+
+	if (!adapter->efuse_map) {
+		adapter->efuse_map = (u8 *)PLTFM_MALLOC(efuse_size);
+		if (!adapter->efuse_map) {
+			PLTFM_MSG_ERR("[ERR]malloc adapter map\n");
+			reset_ofld_feature_88xx(adapter,
+						FEATURE_DUMP_PHY_EFUSE);
+			return HALMAC_RET_MALLOC_FAIL;
+		}
+	}
+
+	if (adapter->efuse_map_valid == 0) {
+		status = send_h2c_pkt_88xx(adapter, h2c_buf);
+		if (status != HALMAC_RET_SUCCESS) {
+			PLTFM_MSG_ERR("[ERR]send h2c pkt\n");
+			reset_ofld_feature_88xx(adapter,
+						FEATURE_DUMP_PHY_EFUSE);
+			return status;
+		}
+	}
+
+	return HALMAC_RET_SUCCESS;
+}
+
+static enum halmac_ret_status
+proc_write_log_efuse_88xx(struct halmac_adapter *adapter, u32 offset, u8 value)
+{
+	u8 byte1;
+	u8 byte2;
+	u8 blk;
+	u8 blk_idx;
+	u8 hdr;
+	u8 hdr2;
+	u8 *map = NULL;
+	u32 eeprom_size = adapter->hw_cfg_info.eeprom_size;
+	u32 end;
+	enum halmac_ret_status status = HALMAC_RET_SUCCESS;
+
+	map = (u8 *)PLTFM_MALLOC(eeprom_size);
+	if (!map) {
+		PLTFM_MSG_ERR("[ERR]malloc map\n");
+		return HALMAC_RET_MALLOC_FAIL;
+	}
+	PLTFM_MEMSET(map, 0xFF, eeprom_size);
+
+	status = read_log_efuse_map_88xx(adapter, map);
+	if (status != HALMAC_RET_SUCCESS) {
+		PLTFM_MSG_ERR("[ERR]read logical efuse\n");
+		PLTFM_FREE(map, eeprom_size);
+		return status;
+	}
+
+	if (*(map + offset) != value) {
+		end = adapter->efuse_end;
+		blk = (u8)(offset >> 3);
+		blk_idx = (u8)((offset & (8 - 1)) >> 1);
+
+		if (offset > 0x7f) {
+			hdr = (((blk & 0x07) << 5) & 0xE0) | 0x0F;
+			hdr2 = (u8)(((blk & 0x78) << 1) +
+						((0x1 << blk_idx) ^ 0x0F));
+		} else {
+			hdr = (u8)((blk << 4) + ((0x01 << blk_idx) ^ 0x0F));
+		}
+
+		if ((offset & 1) == 0) {
+			byte1 = value;
+			byte2 = *(map + offset + 1);
+		} else {
+			byte1 = *(map + offset - 1);
+			byte2 = value;
+		}
+
+		if (offset > 0x7f) {
+			if (adapter->hw_cfg_info.efuse_size <=
+			    4 + PROTECT_EFUSE_SIZE + end) {
+				PLTFM_FREE(map, eeprom_size);
+				return HALMAC_RET_EFUSE_NOT_ENOUGH;
+			}
+
+			status = write_hw_efuse_88xx(adapter, end, hdr);
+			if (status != HALMAC_RET_SUCCESS) {
+				PLTFM_FREE(map, eeprom_size);
+				return status;
+			}
+
+			status = write_hw_efuse_88xx(adapter, end + 1, hdr2);
+			if (status != HALMAC_RET_SUCCESS) {
+				PLTFM_FREE(map, eeprom_size);
+				return status;
+			}
+
+			status = write_hw_efuse_88xx(adapter, end + 2, byte1);
+			if (status != HALMAC_RET_SUCCESS) {
+				PLTFM_FREE(map, eeprom_size);
+				return status;
+			}
+
+			status = write_hw_efuse_88xx(adapter, end + 3, byte2);
+			if (status != HALMAC_RET_SUCCESS) {
+				PLTFM_FREE(map, eeprom_size);
+				return status;
+			}
+		} else {
+			if (adapter->hw_cfg_info.efuse_size <=
+			    3 + PROTECT_EFUSE_SIZE + end) {
+				PLTFM_FREE(map, eeprom_size);
+				return HALMAC_RET_EFUSE_NOT_ENOUGH;
+			}
+
+			status = write_hw_efuse_88xx(adapter, end, hdr);
+			if (status != HALMAC_RET_SUCCESS) {
+				PLTFM_FREE(map, eeprom_size);
+				return status;
+			}
+
+			status = write_hw_efuse_88xx(adapter, end + 1, byte1);
+			if (status != HALMAC_RET_SUCCESS) {
+				PLTFM_FREE(map, eeprom_size);
+				return status;
+			}
+
+			status = write_hw_efuse_88xx(adapter, end + 2, byte2);
+			if (status != HALMAC_RET_SUCCESS) {
+				PLTFM_FREE(map, eeprom_size);
+				return status;
+			}
+		}
+	}
+
+	PLTFM_FREE(map, eeprom_size);
+
+	return HALMAC_RET_SUCCESS;
+}
+
+enum halmac_ret_status
+read_efuse_88xx(struct halmac_adapter *adapter, u32 offset, u32 size, u8 *map)
+{
+	if (!map) {
+		PLTFM_MSG_ERR("[ERR]malloc map\n");
+		return HALMAC_RET_NULL_POINTER;
+	}
+
+	if (adapter->efuse_map_valid == 1) {
+		PLTFM_MEMCPY(map, adapter->efuse_map + offset, size);
+	} else {
+		if (read_hw_efuse_88xx(adapter, offset, size, map) !=
+		    HALMAC_RET_SUCCESS)
+			return HALMAC_RET_EFUSE_R_FAIL;
+	}
+
+	return HALMAC_RET_SUCCESS;
+}
+
+static enum halmac_ret_status
+update_eeprom_mask_88xx(struct halmac_adapter *adapter,
+			struct halmac_pg_efuse_info *info, u8 *updated_mask)
+{
+	u8 *map = NULL;
+	u8 clr_bit = 0;
+	u32 eeprom_size = adapter->hw_cfg_info.eeprom_size;
+	u8 *map_pg;
+	u8 *efuse_mask;
+	u16 i;
+	u16 j;
+	u16 map_offset;
+	u16 mask_offset;
+	enum halmac_ret_status status = HALMAC_RET_SUCCESS;
+
+	map = (u8 *)PLTFM_MALLOC(eeprom_size);
+	if (!map) {
+		PLTFM_MSG_ERR("[ERR]malloc map\n");
+		return HALMAC_RET_MALLOC_FAIL;
+	}
+	PLTFM_MEMSET(map, 0xFF, eeprom_size);
+
+	PLTFM_MEMSET(updated_mask, 0x00, info->efuse_mask_size);
+
+	status = read_log_efuse_map_88xx(adapter, map);
+
+	if (status != HALMAC_RET_SUCCESS) {
+		PLTFM_FREE(map, eeprom_size);
+		return status;
+	}
+
+	map_pg = info->efuse_map;
+	efuse_mask = info->efuse_mask;
+
+	for (i = 0; i < info->efuse_mask_size; i++)
+		*(updated_mask + i) = *(efuse_mask + i);
+
+	for (i = 0; i < info->efuse_map_size; i += 16) {
+		for (j = 0; j < 16; j += 2) {
+			map_offset = i + j;
+			mask_offset = i >> 4;
+			if (*(u16 *)(map_pg + map_offset) ==
+			    *(u16 *)(map + map_offset)) {
+				switch (j) {
+				case 0:
+					clr_bit = BIT(4);
+					break;
+				case 2:
+					clr_bit = BIT(5);
+					break;
+				case 4:
+					clr_bit = BIT(6);
+					break;
+				case 6:
+					clr_bit = BIT(7);
+					break;
+				case 8:
+					clr_bit = BIT(0);
+					break;
+				case 10:
+					clr_bit = BIT(1);
+					break;
+				case 12:
+					clr_bit = BIT(2);
+					break;
+				case 14:
+					clr_bit = BIT(3);
+					break;
+				default:
+					break;
+				}
+				*(updated_mask + mask_offset) &= ~clr_bit;
+			}
+		}
+	}
+
+	PLTFM_FREE(map, eeprom_size);
+
+	return status;
+}
+
+static enum halmac_ret_status
+check_efuse_enough_88xx(struct halmac_adapter *adapter,
+			struct halmac_pg_efuse_info *info, u8 *updated_mask)
+{
+	u8 pre_word_en;
+	u16 i;
+	u16 j;
+	u32 eeprom_offset;
+	u32 pg_num = 0;
+
+	for (i = 0; i < info->efuse_map_size; i = i + 8) {
+		eeprom_offset = i;
+
+		if ((eeprom_offset & 7) > 0)
+			pre_word_en = (*(updated_mask + (i >> 4)) & 0x0F);
+		else
+			pre_word_en = (*(updated_mask + (i >> 4)) >> 4);
+
+		if (pre_word_en > 0) {
+			if (eeprom_offset > 0x7f) {
+				pg_num += 2;
+				for (j = 0; j < 4; j++) {
+					if (((pre_word_en >> j) & 0x1) > 0)
+						pg_num += 2;
+				}
+			} else {
+				pg_num++;
+				for (j = 0; j < 4; j++) {
+					if (((pre_word_en >> j) & 0x1) > 0)
+						pg_num += 2;
+				}
+			}
+		}
+	}
+
+	if (adapter->hw_cfg_info.efuse_size <=
+	    (pg_num + PROTECT_EFUSE_SIZE + adapter->efuse_end))
+		return HALMAC_RET_EFUSE_NOT_ENOUGH;
+
+	return HALMAC_RET_SUCCESS;
+}
+
+static enum halmac_ret_status
+pg_extend_efuse_88xx(struct halmac_adapter *adapter,
+		     struct halmac_pg_efuse_info *info, u8 word_en,
+		     u8 pre_word_en, u32 eeprom_offset)
+{
+	u8 blk;
+	u8 hdr;
+	u8 hdr2;
+	u16 i;
+	u32 efuse_end;
+	enum halmac_ret_status status = HALMAC_RET_SUCCESS;
+
+	efuse_end = adapter->efuse_end;
+
+	blk = (u8)(eeprom_offset >> 3);
+	hdr = (((blk & 0x07) << 5) & 0xE0) | 0x0F;
+	hdr2 = (u8)(((blk & 0x78) << 1) + word_en);
+
+	status = write_hw_efuse_88xx(adapter, efuse_end, hdr);
+	if (status != HALMAC_RET_SUCCESS) {
+		PLTFM_MSG_ERR("[ERR]write efuse\n");
+		return status;
+	}
+
+	status = write_hw_efuse_88xx(adapter, efuse_end + 1, hdr2);
+	if (status != HALMAC_RET_SUCCESS) {
+		PLTFM_MSG_ERR("[ERR]write efuse(+1)\n");
+		return status;
+	}
+
+	efuse_end = efuse_end + 2;
+	for (i = 0; i < 4; i++) {
+		if (((pre_word_en >> i) & 0x1) > 0) {
+			status = write_hw_efuse_88xx(adapter, efuse_end,
+						     *(info->efuse_map +
+						     eeprom_offset +
+						     (i << 1)));
+			if (status != HALMAC_RET_SUCCESS) {
+				PLTFM_MSG_ERR("[ERR]write efuse(<<1)\n");
+				return status;
+			}
+
+			status = write_hw_efuse_88xx(adapter, efuse_end + 1,
+						     *(info->efuse_map +
+						     eeprom_offset + (i << 1)
+						     + 1));
+			if (status != HALMAC_RET_SUCCESS) {
+				PLTFM_MSG_ERR("[ERR]write efuse(<<1)+1\n");
+				return status;
+			}
+			efuse_end = efuse_end + 2;
+		}
+	}
+	adapter->efuse_end = efuse_end;
+	return status;
+}
+
+static enum halmac_ret_status
+proc_pg_efuse_88xx(struct halmac_adapter *adapter,
+		   struct halmac_pg_efuse_info *info, u8 word_en,
+		   u8 pre_word_en, u32 eeprom_offset)
+{
+	u8 blk;
+	u8 hdr;
+	u16 i;
+	u32 efuse_end;
+	enum halmac_ret_status status = HALMAC_RET_SUCCESS;
+
+	efuse_end = adapter->efuse_end;
+
+	blk = (u8)(eeprom_offset >> 3);
+	hdr = (u8)((blk << 4) + word_en);
+
+	status = write_hw_efuse_88xx(adapter, efuse_end, hdr);
+	if (status != HALMAC_RET_SUCCESS) {
+		PLTFM_MSG_ERR("[ERR]write efuse\n");
+		return status;
+	}
+	efuse_end = efuse_end + 1;
+	for (i = 0; i < 4; i++) {
+		if (((pre_word_en >> i) & 0x1) > 0) {
+			status = write_hw_efuse_88xx(adapter, efuse_end,
+						     *(info->efuse_map +
+						     eeprom_offset +
+						     (i << 1)));
+			if (status != HALMAC_RET_SUCCESS) {
+				PLTFM_MSG_ERR("[ERR]write efuse(<<1)\n");
+				return status;
+			}
+			status = write_hw_efuse_88xx(adapter, efuse_end + 1,
+						     *(info->efuse_map +
+						     eeprom_offset + (i << 1)
+						     + 1));
+			if (status != HALMAC_RET_SUCCESS) {
+				PLTFM_MSG_ERR("[ERR]write efuse(<<1)+1\n");
+				return status;
+			}
+			efuse_end = efuse_end + 2;
+		}
+	}
+	adapter->efuse_end = efuse_end;
+	return status;
+}
+
+static enum halmac_ret_status
+program_efuse_88xx(struct halmac_adapter *adapter,
+		   struct halmac_pg_efuse_info *info, u8 *updated_mask)
+{
+	u8 pre_word_en;
+	u8 word_en;
+	u16 i;
+	u32 eeprom_offset;
+	enum halmac_ret_status status = HALMAC_RET_SUCCESS;
+
+	for (i = 0; i < info->efuse_map_size; i = i + 8) {
+		eeprom_offset = i;
+
+		if (((eeprom_offset >> 3) & 1) > 0) {
+			pre_word_en = (*(updated_mask + (i >> 4)) & 0x0F);
+			word_en = pre_word_en ^ 0x0F;
+		} else {
+			pre_word_en = (*(updated_mask + (i >> 4)) >> 4);
+			word_en = pre_word_en ^ 0x0F;
+		}
+
+		if (pre_word_en > 0) {
+			if (eeprom_offset > 0x7f) {
+				status = pg_extend_efuse_88xx(adapter, info,
+							      word_en,
+							      pre_word_en,
+							      eeprom_offset);
+				if (status != HALMAC_RET_SUCCESS) {
+					PLTFM_MSG_ERR("[ERR]extend efuse\n");
+					return status;
+				}
+			} else {
+				status = proc_pg_efuse_88xx(adapter, info,
+							    word_en,
+							    pre_word_en,
+							    eeprom_offset);
+				if (status != HALMAC_RET_SUCCESS) {
+					PLTFM_MSG_ERR("[ERR]extend efuse");
+					return status;
+				}
+			}
+		}
+	}
+
+	return status;
+}
+
+static void
+mask_eeprom_88xx(struct halmac_adapter *adapter,
+		 struct halmac_pg_efuse_info *info)
+{
+	u8 pre_word_en;
+	u8 *updated_mask;
+	u8 *efuse_map;
+	u16 i;
+	u16 j;
+	u32 offset;
+
+	updated_mask = info->efuse_mask;
+	efuse_map = info->efuse_map;
+
+	for (i = 0; i < info->efuse_map_size; i = i + 8) {
+		offset = i;
+
+		if (((offset >> 3) & 1) > 0)
+			pre_word_en = (*(updated_mask + (i >> 4)) & 0x0F);
+		else
+			pre_word_en = (*(updated_mask + (i >> 4)) >> 4);
+
+		for (j = 0; j < 4; j++) {
+			if (((pre_word_en >> j) & 0x1) == 0) {
+				*(efuse_map + offset + (j << 1)) = 0xFF;
+				*(efuse_map + offset + (j << 1) + 1) = 0xFF;
+			}
+		}
+	}
+}
+
+enum halmac_ret_status
+get_efuse_data_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size)
+{
+	u8 seg_id;
+	u8 seg_size;
+	u8 seq_num;
+	u8 fw_rc;
+	u8 *map = NULL;
+	u32 eeprom_size = adapter->hw_cfg_info.eeprom_size;
+	struct halmac_efuse_state *state = &adapter->halmac_state.efuse_state;
+	enum halmac_cmd_process_status proc_status;
+
+	seq_num = (u8)EFUSE_DATA_GET_H2C_SEQ(buf);
+	PLTFM_MSG_TRACE("[TRACE]Seq num : h2c->%d c2h->%d\n",
+			state->seq_num, seq_num);
+	if (seq_num != state->seq_num) {
+		PLTFM_MSG_ERR("[ERR]Seq num mismatch : h2c->%d c2h->%d\n",
+			      state->seq_num, seq_num);
+		return HALMAC_RET_SUCCESS;
+	}
+
+	if (state->proc_status != HALMAC_CMD_PROCESS_SENDING) {
+		PLTFM_MSG_ERR("[ERR]not cmd sending\n");
+		return HALMAC_RET_SUCCESS;
+	}
+
+	seg_id = (u8)EFUSE_DATA_GET_SEGMENT_ID(buf);
+	seg_size = (u8)EFUSE_DATA_GET_SEGMENT_SIZE(buf);
+	if (seg_id == 0)
+		adapter->efuse_seg_size = seg_size;
+
+	map = (u8 *)PLTFM_MALLOC(eeprom_size);
+	if (!map) {
+		PLTFM_MSG_ERR("[ERR]malloc map\n");
+		return HALMAC_RET_MALLOC_FAIL;
+	}
+	PLTFM_MEMSET(map, 0xFF, eeprom_size);
+
+	PLTFM_MUTEX_LOCK(&adapter->efuse_mutex);
+	PLTFM_MEMCPY(adapter->efuse_map + seg_id * adapter->efuse_seg_size,
+		     buf + C2H_DATA_OFFSET_88XX, seg_size);
+	PLTFM_MUTEX_UNLOCK(&adapter->efuse_mutex);
+
+	if (EFUSE_DATA_GET_END_SEGMENT(buf) == 0) {
+		PLTFM_FREE(map, eeprom_size);
+		return HALMAC_RET_SUCCESS;
+	}
+
+	fw_rc = state->fw_rc;
+
+	if ((enum halmac_h2c_return_code)fw_rc == HALMAC_H2C_RETURN_SUCCESS) {
+		proc_status = HALMAC_CMD_PROCESS_DONE;
+		state->proc_status = proc_status;
+
+		PLTFM_MUTEX_LOCK(&adapter->efuse_mutex);
+		adapter->efuse_map_valid = 1;
+		PLTFM_MUTEX_UNLOCK(&adapter->efuse_mutex);
+
+		if (adapter->evnt.phy_efuse_map == 1) {
+			PLTFM_EVENT_SIG(FEATURE_DUMP_PHY_EFUSE,
+					proc_status, adapter->efuse_map,
+					adapter->hw_cfg_info.efuse_size);
+			adapter->evnt.phy_efuse_map = 0;
+		}
+
+		if (adapter->evnt.log_efuse_map == 1) {
+			if (eeprom_parser_88xx(adapter, adapter->efuse_map,
+					       map) != HALMAC_RET_SUCCESS) {
+				PLTFM_FREE(map, eeprom_size);
+				return HALMAC_RET_EEPROM_PARSING_FAIL;
+			}
+			PLTFM_EVENT_SIG(FEATURE_DUMP_LOG_EFUSE, proc_status,
+					map, eeprom_size);
+			adapter->evnt.log_efuse_map = 0;
+		}
+	} else {
+		proc_status = HALMAC_CMD_PROCESS_ERROR;
+		state->proc_status = proc_status;
+
+		if (adapter->evnt.phy_efuse_map == 1) {
+			PLTFM_EVENT_SIG(FEATURE_DUMP_PHY_EFUSE, proc_status,
+					&state->fw_rc, 1);
+			adapter->evnt.phy_efuse_map = 0;
+		}
+
+		if (adapter->evnt.log_efuse_map == 1) {
+			PLTFM_EVENT_SIG(FEATURE_DUMP_LOG_EFUSE, proc_status,
+					&state->fw_rc, 1);
+			adapter->evnt.log_efuse_map = 0;
+		}
+	}
+
+	PLTFM_FREE(map, eeprom_size);
+
+	return HALMAC_RET_SUCCESS;
+}
+
+enum halmac_ret_status
+get_dump_phy_efuse_status_88xx(struct halmac_adapter *adapter,
+			       enum halmac_cmd_process_status *proc_status,
+			       u8 *data, u32 *size)
+{
+	u8 *map = NULL;
+	u32 efuse_size = adapter->hw_cfg_info.efuse_size;
+	struct halmac_efuse_state *state = &adapter->halmac_state.efuse_state;
+
+	*proc_status = state->proc_status;
+
+	if (!data)
+		return HALMAC_RET_NULL_POINTER;
+
+	if (!size)
+		return HALMAC_RET_NULL_POINTER;
+
+	if (*proc_status == HALMAC_CMD_PROCESS_DONE) {
+		if (*size < efuse_size) {
+			*size = efuse_size;
+			return HALMAC_RET_BUFFER_TOO_SMALL;
+		}
+
+		*size = efuse_size;
+
+		map = (u8 *)PLTFM_MALLOC(efuse_size);
+		if (!map) {
+			PLTFM_MSG_ERR("[ERR]malloc map\n");
+			return HALMAC_RET_MALLOC_FAIL;
+		}
+		PLTFM_MEMSET(map, 0xFF, efuse_size);
+		PLTFM_MUTEX_LOCK(&adapter->efuse_mutex);
+		PLTFM_MEMCPY(map, adapter->efuse_map,
+			     efuse_size - PROTECT_EFUSE_SIZE);
+		PLTFM_MEMCPY(map + efuse_size - PROTECT_EFUSE_SIZE +
+			     RSVD_CS_EFUSE_SIZE,
+			     adapter->efuse_map + efuse_size -
+			     PROTECT_EFUSE_SIZE + RSVD_CS_EFUSE_SIZE,
+			     PROTECT_EFUSE_SIZE - RSVD_EFUSE_SIZE -
+			     RSVD_CS_EFUSE_SIZE);
+		PLTFM_MUTEX_UNLOCK(&adapter->efuse_mutex);
+
+		PLTFM_MEMCPY(data, map, *size);
+
+		PLTFM_FREE(map, efuse_size);
+	}
+
+	return HALMAC_RET_SUCCESS;
+}
+
+enum halmac_ret_status
+get_dump_log_efuse_status_88xx(struct halmac_adapter *adapter,
+			       enum halmac_cmd_process_status *proc_status,
+			       u8 *data, u32 *size)
+{
+	u8 *map = NULL;
+	u32 eeprom_size = adapter->hw_cfg_info.eeprom_size;
+	struct halmac_efuse_state *state = &adapter->halmac_state.efuse_state;
+
+	*proc_status = state->proc_status;
+
+	if (!data)
+		return HALMAC_RET_NULL_POINTER;
+
+	if (!size)
+		return HALMAC_RET_NULL_POINTER;
+
+	if (*proc_status == HALMAC_CMD_PROCESS_DONE) {
+		if (*size < eeprom_size) {
+			*size = eeprom_size;
+			return HALMAC_RET_BUFFER_TOO_SMALL;
+		}
+
+		*size = eeprom_size;
+
+		map = (u8 *)PLTFM_MALLOC(eeprom_size);
+		if (!map) {
+			PLTFM_MSG_ERR("[ERR]malloc map\n");
+			return HALMAC_RET_MALLOC_FAIL;
+		}
+		PLTFM_MEMSET(map, 0xFF, eeprom_size);
+
+		if (eeprom_parser_88xx(adapter, adapter->efuse_map, map) !=
+		    HALMAC_RET_SUCCESS) {
+			PLTFM_FREE(map, eeprom_size);
+			return HALMAC_RET_EEPROM_PARSING_FAIL;
+		}
+
+		PLTFM_MEMCPY(data, map, *size);
+
+		PLTFM_FREE(map, eeprom_size);
+	}
+
+	return HALMAC_RET_SUCCESS;
+}
+
+enum halmac_ret_status
+get_h2c_ack_phy_efuse_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size)
+{
+	u8 seq_num = 0;
+	u8 fw_rc;
+	struct halmac_efuse_state *state = &adapter->halmac_state.efuse_state;
+
+	seq_num = (u8)H2C_ACK_HDR_GET_H2C_SEQ(buf);
+	PLTFM_MSG_TRACE("[TRACE]Seq num : h2c->%d c2h->%d\n",
+			state->seq_num, seq_num);
+	if (seq_num != state->seq_num) {
+		PLTFM_MSG_ERR("[ERR]Seq num mismatch : h2c->%d c2h->%d\n",
+			      state->seq_num, seq_num);
+		return HALMAC_RET_SUCCESS;
+	}
+
+	if (state->proc_status != HALMAC_CMD_PROCESS_SENDING) {
+		PLTFM_MSG_ERR("[ERR]not cmd sending\n");
+		return HALMAC_RET_SUCCESS;
+	}
+
+	fw_rc = (u8)H2C_ACK_HDR_GET_H2C_RETURN_CODE(buf);
+	state->fw_rc = fw_rc;
+
+	return HALMAC_RET_SUCCESS;
+}
+
+u32
+get_rsvd_efuse_size_88xx(struct halmac_adapter *adapter)
+{
+	return PROTECT_EFUSE_SIZE;
+}
+
+#endif /* HALMAC_88XX_SUPPORT */
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/halmac/halmac_88xx/halmac_efuse_88xx.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/halmac/halmac_88xx/halmac_efuse_88xx.h
--- linux-5.6.3/3rdparty/rtl8821ce/hal/halmac/halmac_88xx/halmac_efuse_88xx.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/halmac/halmac_88xx/halmac_efuse_88xx.h	2020-04-10 16:35:06.792658947 +0300
@@ -0,0 +1,105 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ ******************************************************************************/
+
+#ifndef _HALMAC_EFUSE_88XX_H_
+#define _HALMAC_EFUSE_88XX_H_
+
+#include "../halmac_api.h"
+
+#if HALMAC_88XX_SUPPORT
+
+enum halmac_ret_status
+dump_efuse_map_88xx(struct halmac_adapter *adapter,
+		    enum halmac_efuse_read_cfg cfg);
+
+enum halmac_ret_status
+dump_efuse_map_bt_88xx(struct halmac_adapter *adapter,
+		       enum halmac_efuse_bank bank, u32 size, u8 *map);
+
+enum halmac_ret_status
+write_efuse_bt_88xx(struct halmac_adapter *adapter, u32 offset, u8 value,
+		    enum halmac_efuse_bank bank);
+
+enum halmac_ret_status
+read_efuse_bt_88xx(struct halmac_adapter *adapter, u32 offset, u8 *value,
+		   enum halmac_efuse_bank bank);
+
+enum halmac_ret_status
+cfg_efuse_auto_check_88xx(struct halmac_adapter *adapter, u8 enable);
+
+enum halmac_ret_status
+get_efuse_available_size_88xx(struct halmac_adapter *adapter, u32 *size);
+
+enum halmac_ret_status
+get_efuse_size_88xx(struct halmac_adapter *adapter, u32 *size);
+
+enum halmac_ret_status
+get_log_efuse_size_88xx(struct halmac_adapter *adapter, u32 *size);
+
+enum halmac_ret_status
+dump_log_efuse_map_88xx(struct halmac_adapter *adapter,
+			enum halmac_efuse_read_cfg cfg);
+
+enum halmac_ret_status
+read_logical_efuse_88xx(struct halmac_adapter *adapter, u32 offset, u8 *value);
+
+enum halmac_ret_status
+write_log_efuse_88xx(struct halmac_adapter *adapter, u32 offset, u8 value);
+
+enum halmac_ret_status
+pg_efuse_by_map_88xx(struct halmac_adapter *adapter,
+		     struct halmac_pg_efuse_info *info,
+		     enum halmac_efuse_read_cfg cfg);
+
+enum halmac_ret_status
+mask_log_efuse_88xx(struct halmac_adapter *adapter,
+		    struct halmac_pg_efuse_info *info);
+
+enum halmac_ret_status
+read_efuse_88xx(struct halmac_adapter *adapter, u32 offset, u32 size, u8 *map);
+
+enum halmac_ret_status
+write_hw_efuse_88xx(struct halmac_adapter *adapter, u32 offset, u8 value);
+
+enum halmac_ret_status
+switch_efuse_bank_88xx(struct halmac_adapter *adapter,
+		       enum halmac_efuse_bank bank);
+
+enum halmac_ret_status
+get_efuse_data_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size);
+
+enum halmac_ret_status
+cnv_efuse_state_88xx(struct halmac_adapter *adapter,
+		     enum halmac_cmd_construct_state dest_state);
+
+enum halmac_ret_status
+get_dump_phy_efuse_status_88xx(struct halmac_adapter *adapter,
+			       enum halmac_cmd_process_status *proc_status,
+			       u8 *data, u32 *size);
+
+enum halmac_ret_status
+get_dump_log_efuse_status_88xx(struct halmac_adapter *adapter,
+			       enum halmac_cmd_process_status *proc_status,
+			       u8 *data, u32 *size);
+
+enum halmac_ret_status
+get_h2c_ack_phy_efuse_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size);
+
+u32
+get_rsvd_efuse_size_88xx(struct halmac_adapter *adapter);
+
+#endif /* HALMAC_88XX_SUPPORT */
+
+#endif/* _HALMAC_EFUSE_88XX_H_ */
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/halmac/halmac_88xx/halmac_flash_88xx.c linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/halmac/halmac_88xx/halmac_flash_88xx.c
--- linux-5.6.3/3rdparty/rtl8821ce/hal/halmac/halmac_88xx/halmac_flash_88xx.c	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/halmac/halmac_88xx/halmac_flash_88xx.c	2020-04-10 16:35:06.792658947 +0300
@@ -0,0 +1,316 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2017 - 2018 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ ******************************************************************************/
+
+#include "halmac_flash_88xx.h"
+#include "halmac_88xx_cfg.h"
+#include "halmac_common_88xx.h"
+
+#if HALMAC_88XX_SUPPORT
+
+/**
+ * download_flash_88xx() -download firmware to flash
+ * @adapter : the adapter of halmac
+ * @fw_bin : pointer to fw
+ * @size : fw size
+ * @rom_addr : flash start address where fw should be download
+ * Author : Pablo Chiu
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+download_flash_88xx(struct halmac_adapter *adapter, u8 *fw_bin, u32 size,
+		    u32 rom_addr)
+{
+	struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
+	enum halmac_ret_status rc;
+	struct halmac_h2c_header_info hdr_info;
+	u8 value8;
+	u8 restore[3];
+	u8 h2c_buf[H2C_PKT_SIZE_88XX] = {0};
+	u16 seq_num = 0;
+	u16 h2c_info_offset;
+	u32 pkt_size;
+	u32 mem_offset;
+
+	PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
+
+	value8 = HALMAC_REG_R8(REG_CR + 1);
+	restore[0] = value8;
+	value8 = (u8)(value8 | BIT(0));
+	HALMAC_REG_W8(REG_CR + 1, value8);
+
+	value8 = HALMAC_REG_R8(REG_BCN_CTRL);
+	restore[1] = value8;
+	value8 = (u8)((value8 & ~(BIT(3))) | BIT(4));
+	HALMAC_REG_W8(REG_BCN_CTRL, value8);
+
+	value8 = HALMAC_REG_R8(REG_FWHW_TXQ_CTRL + 2);
+	restore[2] = value8;
+	value8 = (u8)(value8 & ~(BIT(6)));
+	HALMAC_REG_W8(REG_FWHW_TXQ_CTRL + 2, value8);
+
+	/* Download FW to Flash flow */
+	h2c_info_offset = adapter->txff_alloc.rsvd_h2c_info_addr -
+					adapter->txff_alloc.rsvd_boundary;
+	mem_offset = 0;
+
+	while (size != 0) {
+		if (size >= (DL_FLASH_RSVDPG_SIZE - 48))
+			pkt_size = DL_FLASH_RSVDPG_SIZE - 48;
+		else
+			pkt_size = size;
+
+		rc = dl_rsvd_page_88xx(adapter,
+				       adapter->txff_alloc.rsvd_h2c_info_addr,
+				       fw_bin + mem_offset, pkt_size);
+		if (rc != HALMAC_RET_SUCCESS) {
+			PLTFM_MSG_ERR("[ERR]dl rsvd pg!!\n");
+			return rc;
+		}
+
+		DOWNLOAD_FLASH_SET_SPI_CMD(h2c_buf, 0x02);
+		DOWNLOAD_FLASH_SET_LOCATION(h2c_buf, h2c_info_offset);
+		DOWNLOAD_FLASH_SET_SIZE(h2c_buf, pkt_size);
+		DOWNLOAD_FLASH_SET_START_ADDR(h2c_buf, rom_addr);
+
+		hdr_info.sub_cmd_id = SUB_CMD_ID_DOWNLOAD_FLASH;
+		hdr_info.content_size = 20;
+		hdr_info.ack = 1;
+		set_h2c_pkt_hdr_88xx(adapter, h2c_buf, &hdr_info, &seq_num);
+
+		rc = send_h2c_pkt_88xx(adapter, h2c_buf);
+
+		if (rc != HALMAC_RET_SUCCESS) {
+			PLTFM_MSG_ERR("[ERR]send h2c!!\n");
+			return rc;
+		}
+
+		value8 = HALMAC_REG_R8(REG_MCUTST_I);
+		value8 |= BIT(0);
+		HALMAC_REG_W8(REG_MCUTST_I, value8);
+
+		rom_addr += pkt_size;
+		mem_offset += pkt_size;
+		size -= pkt_size;
+
+		while (((HALMAC_REG_R8(REG_MCUTST_I)) & BIT(0)) != 0)
+			PLTFM_DELAY_US(1000);
+
+		if (((HALMAC_REG_R8(REG_MCUTST_I)) & BIT(0)) != 0) {
+			PLTFM_MSG_ERR("[ERR]dl flash!!\n");
+			return  HALMAC_RET_DLFW_FAIL;
+		}
+	}
+
+	HALMAC_REG_W8(REG_FWHW_TXQ_CTRL + 2, restore[2]);
+	HALMAC_REG_W8(REG_BCN_CTRL, restore[1]);
+	HALMAC_REG_W8(REG_CR + 1, restore[0]);
+	PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
+
+	return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * read_flash_88xx() -read data from flash
+ * @adapter : the adapter of halmac
+ * @addr : flash start address where fw should be read
+ * Author : Pablo Chiu
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+read_flash_88xx(struct halmac_adapter *adapter, u32 addr, u32 length)
+{
+	struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
+	enum halmac_ret_status status;
+	struct halmac_h2c_header_info hdr_info;
+	u8 value8;
+	u8 restore[3];
+	u8 h2c_buf[H2C_PKT_SIZE_88XX] = {0};
+	u16 seq_num = 0;
+	u16 h2c_info_addr = adapter->txff_alloc.rsvd_h2c_info_addr;
+	u16 rsvd_pg_addr = adapter->txff_alloc.rsvd_boundary;
+
+	PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
+
+	value8 = HALMAC_REG_R8(REG_CR + 1);
+	restore[0] = value8;
+	value8 = (u8)(value8 | BIT(0));
+	HALMAC_REG_W8(REG_CR + 1, value8);
+
+	value8 = HALMAC_REG_R8(REG_BCN_CTRL);
+	restore[1] = value8;
+	value8 = (u8)((value8 & ~(BIT(3))) | BIT(4));
+	HALMAC_REG_W8(REG_BCN_CTRL, value8);
+
+	value8 = HALMAC_REG_R8(REG_FWHW_TXQ_CTRL + 2);
+	restore[2] = value8;
+	value8 = (u8)(value8 & ~(BIT(6)));
+	HALMAC_REG_W8(REG_FWHW_TXQ_CTRL + 2, value8);
+
+	HALMAC_REG_W16(REG_FIFOPAGE_CTRL_2, h2c_info_addr);
+	value8 = HALMAC_REG_R8(REG_MCUTST_I);
+	value8 |= BIT(0);
+	HALMAC_REG_W8(REG_MCUTST_I, value8);
+
+	/* Construct H2C Content */
+	DOWNLOAD_FLASH_SET_SPI_CMD(h2c_buf, 0x03);
+	DOWNLOAD_FLASH_SET_LOCATION(h2c_buf, h2c_info_addr - rsvd_pg_addr);
+	DOWNLOAD_FLASH_SET_SIZE(h2c_buf, length);
+	DOWNLOAD_FLASH_SET_START_ADDR(h2c_buf, addr);
+
+	/* Fill in H2C Header */
+	hdr_info.sub_cmd_id = SUB_CMD_ID_DOWNLOAD_FLASH;
+	hdr_info.content_size = 16;
+	hdr_info.ack = 1;
+	set_h2c_pkt_hdr_88xx(adapter, h2c_buf, &hdr_info, &seq_num);
+
+	/* Send H2C Cmd Packet */
+	status = send_h2c_pkt_88xx(adapter, h2c_buf);
+
+	if (status != HALMAC_RET_SUCCESS) {
+		PLTFM_MSG_ERR("[ERR]send h2c!!\n");
+		return status;
+	}
+
+	while (((HALMAC_REG_R8(REG_MCUTST_I)) & BIT(0)) != 0)
+		PLTFM_DELAY_US(1000);
+
+	HALMAC_REG_W16(REG_FIFOPAGE_CTRL_2, rsvd_pg_addr);
+	HALMAC_REG_W8(REG_FWHW_TXQ_CTRL + 2, restore[2]);
+	HALMAC_REG_W8(REG_BCN_CTRL, restore[1]);
+	HALMAC_REG_W8(REG_CR + 1, restore[0]);
+
+	PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
+
+	return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * erase_flash_88xx() -erase flash data
+ * @adapter : the adapter of halmac
+ * @erase_cmd : erase command
+ * @addr : flash start address where fw should be erased
+ * Author : Pablo Chiu
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+erase_flash_88xx(struct halmac_adapter *adapter, u8 erase_cmd, u32 addr)
+{
+	enum halmac_ret_status status;
+	struct halmac_h2c_header_info hdr_info;
+	struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
+	u8 value8;
+	u8 h2c_buf[H2C_PKT_SIZE_88XX] = {0};
+	u16 seq_num = 0;
+	u32 cnt;
+
+	/* Construct H2C Content */
+	DOWNLOAD_FLASH_SET_SPI_CMD(h2c_buf, erase_cmd);
+	DOWNLOAD_FLASH_SET_LOCATION(h2c_buf, 0);
+	DOWNLOAD_FLASH_SET_START_ADDR(h2c_buf, addr);
+	DOWNLOAD_FLASH_SET_SIZE(h2c_buf, 0);
+
+	value8 = HALMAC_REG_R8(REG_MCUTST_I);
+	value8 |= BIT(0);
+	HALMAC_REG_W8(REG_MCUTST_I, value8);
+
+	/* Fill in H2C Header */
+	hdr_info.sub_cmd_id = SUB_CMD_ID_DOWNLOAD_FLASH;
+	hdr_info.content_size = 16;
+	hdr_info.ack = 1;
+	set_h2c_pkt_hdr_88xx(adapter, h2c_buf, &hdr_info, &seq_num);
+
+	/* Send H2C Cmd Packet */
+	status = send_h2c_pkt_88xx(adapter, h2c_buf);
+
+	if (status != HALMAC_RET_SUCCESS)
+		PLTFM_MSG_ERR("[ERR]send h2c!!\n");
+
+	cnt = 5000;
+	while (((HALMAC_REG_R8(REG_MCUTST_I)) & BIT(0)) != 0 && cnt != 0) {
+		PLTFM_DELAY_US(1000);
+		cnt--;
+	}
+
+	if (cnt == 0)
+		return HALMAC_RET_FAIL;
+	else
+		return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * check_flash_88xx() -check flash data
+ * @adapter : the adapter of halmac
+ * @fw_bin : pointer to fw
+ * @size : fw size
+ * @addr : flash start address where fw should be checked
+ * Author : Pablo Chiu
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+check_flash_88xx(struct halmac_adapter *adapter, u8 *fw_bin, u32 size,
+		 u32 addr)
+{
+	struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
+	u8 value8;
+	u16 i;
+	u16 residue;
+	u16 pg_addr;
+	u32 pkt_size;
+	u32 start_page;
+	u32 cnt;
+
+	pg_addr = adapter->txff_alloc.rsvd_h2c_info_addr;
+
+	while (size != 0) {
+		start_page = ((pg_addr << 7) >> 12) + 0x780;
+		residue = (pg_addr << 7) & (4096 - 1);
+
+		if (size >= DL_FLASH_RSVDPG_SIZE)
+			pkt_size = DL_FLASH_RSVDPG_SIZE;
+		else
+			pkt_size = size;
+
+		read_flash_88xx(adapter, addr, 4096);
+
+		cnt = 0;
+		while (cnt < pkt_size) {
+			HALMAC_REG_W16(REG_PKTBUF_DBG_CTRL, (u16)(start_page));
+			for (i = 0x8000 + residue; i <= 0x8FFF; i++) {
+				value8 = HALMAC_REG_R8(i);
+				if (*fw_bin != value8) {
+					PLTFM_MSG_ERR("[ERR]check flash!!\n");
+					return HALMAC_RET_FAIL;
+				}
+
+				fw_bin++;
+				cnt++;
+				if (cnt == pkt_size)
+					break;
+			}
+			residue = 0;
+			start_page++;
+		}
+		addr += pkt_size;
+		size -= pkt_size;
+	}
+
+	return HALMAC_RET_SUCCESS;
+}
+
+#endif /* HALMAC_88XX_SUPPORT */
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/halmac/halmac_88xx/halmac_flash_88xx.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/halmac/halmac_88xx/halmac_flash_88xx.h
--- linux-5.6.3/3rdparty/rtl8821ce/hal/halmac/halmac_88xx/halmac_flash_88xx.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/halmac/halmac_88xx/halmac_flash_88xx.h	2020-04-10 16:35:06.792658947 +0300
@@ -0,0 +1,39 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2017 - 2018 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ ******************************************************************************/
+
+#ifndef _HALMAC_FLASH_88XX_H_
+#define _HALMAC_FLASH_88XX_H_
+
+#include "../halmac_api.h"
+
+#if HALMAC_88XX_SUPPORT
+
+enum halmac_ret_status
+download_flash_88xx(struct halmac_adapter *adapter, u8 *fw_bin, u32 size,
+		    u32 rom_addr);
+
+enum halmac_ret_status
+read_flash_88xx(struct halmac_adapter *adapter, u32 addr, u32 length);
+
+enum halmac_ret_status
+erase_flash_88xx(struct halmac_adapter *adapter, u8 erase_cmd, u32 addr);
+
+enum halmac_ret_status
+check_flash_88xx(struct halmac_adapter *adapter, u8 *fw_bin, u32 size,
+		 u32 addr);
+
+#endif /* HALMAC_88XX_SUPPORT */
+
+#endif/* _HALMAC_FLASH_88XX_H_ */
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/halmac/halmac_88xx/halmac_func_88xx.c linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/halmac/halmac_88xx/halmac_func_88xx.c
--- linux-5.6.3/3rdparty/rtl8821ce/hal/halmac/halmac_88xx/halmac_func_88xx.c	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/halmac/halmac_88xx/halmac_func_88xx.c	2020-04-10 16:35:06.793658994 +0300
@@ -0,0 +1,4323 @@
+#include "halmac_88xx_cfg.h"
+
+HALMAC_RET_STATUS
+halmac_dump_efuse_fw_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter
+);
+
+HALMAC_RET_STATUS
+halmac_dump_efuse_drv_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter
+);
+
+HALMAC_RET_STATUS
+halmac_update_eeprom_mask_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	INOUT PHALMAC_PG_EFUSE_INFO pPg_efuse_info,
+	OUT u8 *pEeprom_mask_updated
+);
+
+HALMAC_RET_STATUS
+halmac_check_efuse_enough_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN PHALMAC_PG_EFUSE_INFO pPg_efuse_info,
+	IN u8 *pEeprom_mask_updated
+);
+
+HALMAC_RET_STATUS
+halmac_program_efuse_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN PHALMAC_PG_EFUSE_INFO pPg_efuse_info,
+	IN u8 *pEeprom_mask_updated
+);
+
+HALMAC_RET_STATUS
+halmac_pwr_sub_seq_parer_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN u8 cut,
+	IN u8 fab,
+	IN u8 intf,
+	IN PHALMAC_WLAN_PWR_CFG pPwr_sub_seq_cfg
+);
+
+HALMAC_RET_STATUS
+halmac_parse_c2h_debug_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN u8 *pC2h_buf,
+	IN u32 c2h_size
+);
+
+HALMAC_RET_STATUS
+halmac_parse_scan_status_rpt_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN u8 *pC2h_buf,
+	IN u32 c2h_size
+);
+
+HALMAC_RET_STATUS
+halmac_parse_psd_data_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN u8 *pC2h_buf,
+	IN u32 c2h_size
+);
+
+HALMAC_RET_STATUS
+halmac_parse_efuse_data_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN u8 *pC2h_buf,
+	IN u32 c2h_size
+);
+
+
+HALMAC_RET_STATUS
+halmac_parse_h2c_ack_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN u8 *pC2h_buf,
+	IN u32 c2h_size
+);
+
+HALMAC_RET_STATUS
+halmac_parse_h2c_ack_physical_efuse_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN u8 *pC2h_buf,
+	IN u32 c2h_size
+);
+
+HALMAC_RET_STATUS
+halmac_enqueue_para_buff_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN PHALMAC_PHY_PARAMETER_INFO para_info,
+	IN u8 *pCurr_buff_wptr,
+	OUT u8 *pEnd_cmd
+);
+
+HALMAC_RET_STATUS
+halmac_parse_h2c_ack_phy_efuse_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN u8 *pC2h_buf,
+	IN u32 c2h_size
+);
+
+HALMAC_RET_STATUS
+halmac_parse_h2c_ack_cfg_para_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN u8 *pC2h_buf,
+	IN u32 c2h_size
+);
+
+HALMAC_RET_STATUS
+halmac_gen_cfg_para_h2c_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN u8 *pH2c_buff
+);
+
+HALMAC_RET_STATUS
+halmac_parse_h2c_ack_update_packet_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN u8 *pC2h_buf,
+	IN u32 c2h_size
+);
+HALMAC_RET_STATUS
+halmac_parse_h2c_ack_update_datapack_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN u8 *pC2h_buf,
+	IN u32 c2h_size
+);
+
+HALMAC_RET_STATUS
+halmac_parse_h2c_ack_run_datapack_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN u8 *pC2h_buf,
+	IN u32 c2h_size
+);
+
+HALMAC_RET_STATUS
+halmac_parse_h2c_ack_channel_switch_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN u8 *pC2h_buf,
+	IN u32 c2h_size
+);
+
+HALMAC_RET_STATUS
+halmac_parse_h2c_ack_iqk_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN u8 *pC2h_buf,
+	IN u32 c2h_size
+);
+
+HALMAC_RET_STATUS
+halmac_parse_h2c_ack_power_tracking_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN u8 *pC2h_buf,
+	IN u32 c2h_size
+);
+
+VOID
+halmac_init_offload_feature_state_machine_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter
+)
+{
+	PHALMAC_STATE pState = &(pHalmac_adapter->halmac_state);
+
+	pState->efuse_state_set.efuse_cmd_construct_state = HALMAC_EFUSE_CMD_CONSTRUCT_IDLE;
+	pState->efuse_state_set.process_status = HALMAC_CMD_PROCESS_IDLE;
+	pState->efuse_state_set.seq_num = pHalmac_adapter->h2c_packet_seq;
+
+	pState->cfg_para_state_set.cfg_para_cmd_construct_state = HALMAC_CFG_PARA_CMD_CONSTRUCT_IDLE;
+	pState->cfg_para_state_set.process_status = HALMAC_CMD_PROCESS_IDLE;
+	pState->cfg_para_state_set.seq_num = pHalmac_adapter->h2c_packet_seq;
+
+	pState->scan_state_set.scan_cmd_construct_state = HALMAC_SCAN_CMD_CONSTRUCT_IDLE;
+	pState->scan_state_set.process_status = HALMAC_CMD_PROCESS_IDLE;
+	pState->scan_state_set.seq_num = pHalmac_adapter->h2c_packet_seq;
+
+	pState->update_packet_set.process_status = HALMAC_CMD_PROCESS_IDLE;
+	pState->update_packet_set.seq_num = pHalmac_adapter->h2c_packet_seq;
+
+	pState->iqk_set.process_status = HALMAC_CMD_PROCESS_IDLE;
+	pState->iqk_set.seq_num = pHalmac_adapter->h2c_packet_seq;
+
+	pState->power_tracking_set.process_status = HALMAC_CMD_PROCESS_IDLE;
+	pState->power_tracking_set.seq_num = pHalmac_adapter->h2c_packet_seq;
+
+	pState->psd_set.process_status = HALMAC_CMD_PROCESS_IDLE;
+	pState->psd_set.seq_num = pHalmac_adapter->h2c_packet_seq;
+	pState->psd_set.data_size = 0;
+	pState->psd_set.segment_size = 0;
+	pState->psd_set.pData = NULL;
+}
+
+HALMAC_RET_STATUS
+halmac_dump_efuse_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN HALMAC_EFUSE_READ_CFG cfg
+)
+{
+	u32 chk_h2c_init;
+	VOID *pDriver_adapter = NULL;
+	PHALMAC_API pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api;
+	HALMAC_RET_STATUS status = HALMAC_RET_SUCCESS;
+	HALMAC_CMD_PROCESS_STATUS *pProcess_status = &(pHalmac_adapter->halmac_state.efuse_state_set.process_status);
+
+	pDriver_adapter = pHalmac_adapter->pDriver_adapter;
+
+	*pProcess_status = HALMAC_CMD_PROCESS_SENDING;
+
+	if (HALMAC_RET_SUCCESS != halmac_transition_efuse_state_88xx(pHalmac_adapter, HALMAC_EFUSE_CMD_CONSTRUCT_H2C_SENT))
+		return HALMAC_RET_ERROR_STATE;
+
+	if (HALMAC_EFUSE_R_AUTO == cfg) {
+		chk_h2c_init = HALMAC_REG_READ_32(pHalmac_adapter, REG_H2C_PKT_READADDR);
+		if (HALMAC_DLFW_NONE == pHalmac_adapter->halmac_state.dlfw_state || 0 == chk_h2c_init)
+			status = halmac_dump_efuse_drv_88xx(pHalmac_adapter);
+		else
+			status = halmac_dump_efuse_fw_88xx(pHalmac_adapter);
+	} else if (HALMAC_EFUSE_R_FW == cfg) {
+		status = halmac_dump_efuse_fw_88xx(pHalmac_adapter);
+	} else {
+		status = halmac_dump_efuse_drv_88xx(pHalmac_adapter);
+	}
+
+	if (HALMAC_RET_SUCCESS != status) {
+		PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_ERR, "halmac_read_efuse error = %x\n", status);
+		return status;
+	}
+
+	return status;
+}
+
+HALMAC_RET_STATUS
+halmac_func_read_efuse_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN u32 offset,
+	IN u32 size,
+	OUT u8 *pEfuse_map
+)
+{
+	VOID *pDriver_adapter = NULL;
+
+	pDriver_adapter = pHalmac_adapter->pDriver_adapter;
+
+	if (NULL == pEfuse_map) {
+		PLATFORM_MSG_PRINT(pHalmac_adapter->pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_ERR, "Malloc for dump efuse map error\n");
+		return HALMAC_RET_NULL_POINTER;
+	}
+
+	if (_TRUE == pHalmac_adapter->hal_efuse_map_valid)
+		PLATFORM_RTL_MEMCPY(pDriver_adapter, pEfuse_map, pHalmac_adapter->pHalEfuse_map + offset, size);
+	else
+	if (HALMAC_RET_SUCCESS != halmac_read_hw_efuse_88xx(pHalmac_adapter, offset, size, pEfuse_map))
+		return HALMAC_RET_EFUSE_R_FAIL;
+
+	return HALMAC_RET_SUCCESS;
+}
+
+HALMAC_RET_STATUS
+halmac_read_hw_efuse_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN u32 offset,
+	IN u32 size,
+	OUT u8 *pEfuse_map
+)
+{
+	u8 value8;
+	u32 value32;
+	u32 address;
+	u32 tmp32, counter;
+	VOID *pDriver_adapter = NULL;
+	PHALMAC_API pHalmac_api;
+
+	pDriver_adapter = pHalmac_adapter->pDriver_adapter;
+	pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api;
+
+	/* Read efuse no need 2.5V LDO */
+	value8 = HALMAC_REG_READ_8(pHalmac_adapter, REG_LDO_EFUSE_CTRL + 3);
+	if (value8 & BIT(7))
+		HALMAC_REG_WRITE_8(pHalmac_adapter, REG_LDO_EFUSE_CTRL + 3, (u8)(value8 & ~(BIT(7))));
+
+	value32 = HALMAC_REG_READ_32(pHalmac_adapter, REG_EFUSE_CTRL);
+
+	for (address = offset; address < offset + size; address++) {
+		value32 = value32 & ~((BIT_MASK_EF_DATA) | (BIT_MASK_EF_ADDR << BIT_SHIFT_EF_ADDR));
+		value32 = value32 | ((address & BIT_MASK_EF_ADDR) << BIT_SHIFT_EF_ADDR);
+		HALMAC_REG_WRITE_32(pHalmac_adapter, REG_EFUSE_CTRL, value32 & (~BIT_EF_FLAG));
+
+		counter = 1000000;
+		do {
+			PLATFORM_RTL_DELAY_US(pDriver_adapter, 1);
+			tmp32 = HALMAC_REG_READ_32(pHalmac_adapter, REG_EFUSE_CTRL);
+			counter--;
+			if (0 == counter) {
+				PLATFORM_MSG_PRINT(pHalmac_adapter->pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_ERR, "HALMAC_RET_EFUSE_R_FAIL\n");
+				return HALMAC_RET_EFUSE_R_FAIL;
+			}
+		} while (0 == (tmp32 & BIT_EF_FLAG));
+
+		*(pEfuse_map + address - offset) = (u8)(tmp32 & BIT_MASK_EF_DATA);
+	}
+
+	return HALMAC_RET_SUCCESS;
+}
+
+HALMAC_RET_STATUS
+halmac_dump_efuse_drv_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter
+)
+{
+	u8 *pEfuse_map = NULL;
+	u32 efuse_size;
+	VOID *pDriver_adapter = NULL;
+
+	pDriver_adapter = pHalmac_adapter->pDriver_adapter;
+
+	efuse_size = pHalmac_adapter->hw_config_info.efuse_size;
+
+	if (NULL == pHalmac_adapter->pHalEfuse_map) {
+		pHalmac_adapter->pHalEfuse_map = (u8 *)PLATFORM_RTL_MALLOC(pDriver_adapter, efuse_size);
+		if (NULL == pHalmac_adapter->pHalEfuse_map) {
+			PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_ERR, "[ERR]halmac allocate efuse map Fail!!\n");
+			return HALMAC_RET_MALLOC_FAIL;
+		}
+	}
+
+	pEfuse_map = (u8 *)PLATFORM_RTL_MALLOC(pDriver_adapter, efuse_size);
+	if (NULL == pEfuse_map) {
+		PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_ERR, "[ERR]halmac allocate local efuse map Fail!!\n");
+		return HALMAC_RET_MALLOC_FAIL;
+	}
+
+	if (HALMAC_RET_SUCCESS != halmac_read_hw_efuse_88xx(pHalmac_adapter, 0, efuse_size, pEfuse_map)) {
+		PLATFORM_RTL_FREE(pDriver_adapter, pEfuse_map, efuse_size);
+		return HALMAC_RET_EFUSE_R_FAIL;
+	}
+
+	PLATFORM_MUTEX_LOCK(pDriver_adapter, &(pHalmac_adapter->EfuseMutex));
+	PLATFORM_RTL_MEMCPY(pDriver_adapter, pHalmac_adapter->pHalEfuse_map, pEfuse_map, efuse_size);
+	pHalmac_adapter->hal_efuse_map_valid = _TRUE;
+	PLATFORM_MUTEX_UNLOCK(pDriver_adapter, &(pHalmac_adapter->EfuseMutex));
+
+	PLATFORM_RTL_FREE(pDriver_adapter, pEfuse_map, efuse_size);
+
+	return HALMAC_RET_SUCCESS;
+}
+
+HALMAC_RET_STATUS
+halmac_dump_efuse_fw_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter
+)
+{
+	u8 pH2c_buff[HALMAC_H2C_CMD_SIZE_88XX] = { 0 };
+	u32 eeprom_size = pHalmac_adapter->hw_config_info.eeprom_size;
+	u16 h2c_seq_mum = 0;
+	VOID *pDriver_adapter = NULL;
+	HALMAC_H2C_HEADER_INFO h2c_header_info;
+	HALMAC_RET_STATUS status = HALMAC_RET_SUCCESS;
+
+	pDriver_adapter = pHalmac_adapter->pDriver_adapter;
+
+	h2c_header_info.sub_cmd_id = SUB_CMD_ID_DUMP_PHYSICAL_EFUSE;
+	h2c_header_info.content_size = 0;
+	h2c_header_info.ack = _TRUE;
+	halmac_set_fw_offload_h2c_header_88xx(pHalmac_adapter, pH2c_buff, &h2c_header_info, &h2c_seq_mum);
+	pHalmac_adapter->halmac_state.efuse_state_set.seq_num = h2c_seq_mum;
+
+	if (NULL == pHalmac_adapter->pHalEfuse_map) {
+		pHalmac_adapter->pHalEfuse_map = (u8 *)PLATFORM_RTL_MALLOC(pDriver_adapter, pHalmac_adapter->hw_config_info.efuse_size);
+		if (NULL == pHalmac_adapter->pHalEfuse_map) {
+			PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "halmac allocate efuse map Fail!!\n");
+			return HALMAC_RET_MALLOC_FAIL;
+		}
+	}
+
+	if (_FALSE == pHalmac_adapter->hal_efuse_map_valid) {
+		status = halmac_send_h2c_pkt_88xx(pHalmac_adapter, pH2c_buff, HALMAC_H2C_CMD_SIZE_88XX, _TRUE);
+		if (HALMAC_RET_SUCCESS != status) {
+			PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "halmac_read_efuse_fw Fail = %x!!\n", status);
+			return status;
+		}
+	}
+
+	return HALMAC_RET_SUCCESS;
+}
+
+HALMAC_RET_STATUS
+halmac_func_write_efuse_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN u32 offset,
+	IN u8 value
+)
+{
+	const u8 wite_protect_code = 0x69;
+	u32 value32, tmp32, counter;
+	VOID *pDriver_adapter = NULL;
+	PHALMAC_API pHalmac_api;
+
+	pDriver_adapter = pHalmac_adapter->pDriver_adapter;
+	pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api;
+
+	PLATFORM_MUTEX_LOCK(pDriver_adapter, &(pHalmac_adapter->EfuseMutex));
+	pHalmac_adapter->hal_efuse_map_valid = _FALSE;
+	PLATFORM_MUTEX_UNLOCK(pDriver_adapter, &(pHalmac_adapter->EfuseMutex));
+
+	HALMAC_REG_WRITE_8(pHalmac_adapter, REG_PMC_DBG_CTRL2 + 3, wite_protect_code);
+
+	/* Enable 2.5V LDO */
+	HALMAC_REG_WRITE_8(pHalmac_adapter, REG_LDO_EFUSE_CTRL + 3, (u8)(HALMAC_REG_READ_8(pHalmac_adapter, REG_LDO_EFUSE_CTRL + 3) | BIT(7)));
+
+	value32 = HALMAC_REG_READ_32(pHalmac_adapter, REG_EFUSE_CTRL);
+	value32 = value32 & ~((BIT_MASK_EF_DATA) | (BIT_MASK_EF_ADDR << BIT_SHIFT_EF_ADDR));
+	value32 = value32 | ((offset & BIT_MASK_EF_ADDR) << BIT_SHIFT_EF_ADDR) | (value & BIT_MASK_EF_DATA);
+	HALMAC_REG_WRITE_32(pHalmac_adapter, REG_EFUSE_CTRL, value32 | BIT_EF_FLAG);
+
+	counter = 1000000;
+	do {
+		PLATFORM_RTL_DELAY_US(pDriver_adapter, 1);
+		tmp32 = HALMAC_REG_READ_32(pHalmac_adapter, REG_EFUSE_CTRL);
+		counter--;
+		if (0 == counter) {
+			PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "halmac_write_efuse Fail !!\n");
+			return HALMAC_RET_EFUSE_W_FAIL;
+		}
+	} while (BIT_EF_FLAG == (tmp32 & BIT_EF_FLAG));
+
+	HALMAC_REG_WRITE_8(pHalmac_adapter, REG_PMC_DBG_CTRL2 + 3, 0x00);
+
+	/* Disable 2.5V LDO */
+	HALMAC_REG_WRITE_8(pHalmac_adapter, REG_LDO_EFUSE_CTRL + 3, (u8)(HALMAC_REG_READ_8(pHalmac_adapter, REG_LDO_EFUSE_CTRL + 3) & ~(BIT(7))));
+
+	return HALMAC_RET_SUCCESS;
+}
+
+
+HALMAC_RET_STATUS
+halmac_func_switch_efuse_bank_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN HALMAC_EFUSE_BANK efuse_bank
+)
+{
+	u8 reg_value;
+	PHALMAC_API pHalmac_api;
+
+	HALMAC_RET_STATUS status = HALMAC_RET_SUCCESS;
+
+	pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api;
+
+	if (HALMAC_RET_SUCCESS != halmac_transition_efuse_state_88xx(pHalmac_adapter, HALMAC_EFUSE_CMD_CONSTRUCT_BUSY))
+		return HALMAC_RET_ERROR_STATE;
+
+	reg_value = HALMAC_REG_READ_8(pHalmac_adapter, REG_LDO_EFUSE_CTRL + 1);
+
+	if (efuse_bank == (reg_value & (BIT(0) | BIT(1))))
+		return HALMAC_RET_SUCCESS;
+
+	reg_value &= ~(BIT(0) | BIT(1));
+	reg_value |= efuse_bank;
+	HALMAC_REG_WRITE_8(pHalmac_adapter, REG_LDO_EFUSE_CTRL + 1, reg_value);
+
+	if ((HALMAC_REG_READ_8(pHalmac_adapter, REG_LDO_EFUSE_CTRL + 1) & (BIT(0) | BIT(1))) != efuse_bank)
+		return HALMAC_RET_SWITCH_EFUSE_BANK_FAIL;
+
+	return HALMAC_RET_SUCCESS;
+}
+
+HALMAC_RET_STATUS
+halmac_eeprom_parser_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN u8 *pPhysical_efuse_map,
+	OUT u8 *pLogical_efuse_map
+)
+{
+	u8 j;
+	u8 value8;
+	u8 block_index;
+	u8 valid_word_enable, word_enable;
+	u8 efuse_read_header, efuse_read_header2 = 0;
+	u32 eeprom_index;
+	u32 efuse_index = 0;
+	u32 eeprom_size = pHalmac_adapter->hw_config_info.eeprom_size;
+	VOID *pDriver_adapter = NULL;
+
+	pDriver_adapter = pHalmac_adapter->pDriver_adapter;
+
+	PLATFORM_RTL_MEMSET(pDriver_adapter, pLogical_efuse_map, 0xFF, eeprom_size);
+
+	do {
+		value8 = *(pPhysical_efuse_map + efuse_index);
+		efuse_read_header = value8;
+
+		if ((efuse_read_header & 0x1f) == 0x0f) {
+			efuse_index++;
+			value8 = *(pPhysical_efuse_map + efuse_index);
+			efuse_read_header2 = value8;
+			block_index = ((efuse_read_header2 & 0xF0) >> 1) | ((efuse_read_header >> 5) & 0x07);
+			word_enable = efuse_read_header2 & 0x0F;
+		} else {
+			block_index = (efuse_read_header & 0xF0) >> 4;
+			word_enable = efuse_read_header & 0x0F;
+		}
+
+		if (efuse_read_header == 0xff)
+			break;
+
+		efuse_index++;
+
+		if (efuse_index >= pHalmac_adapter->hw_config_info.efuse_size - HALMAC_PROTECTED_EFUSE_SIZE_88XX - 1)
+			return HALMAC_RET_EEPROM_PARSING_FAIL;
+
+		for (j = 0; j < 4; j++) {
+			valid_word_enable = (u8)((~(word_enable >> j)) & BIT(0));
+			if (valid_word_enable == 1) {
+				eeprom_index = (block_index << 3) + (j << 1);
+
+				if ((eeprom_index + 1) > eeprom_size) {
+					PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_ERR, "Error: EEPROM addr exceeds eeprom_size:0x%X, at eFuse 0x%X\n", eeprom_size, efuse_index - 1);
+					if ((efuse_read_header & 0x1f) == 0x0f)
+						PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_ERR, "Error: EEPROM header: 0x%X, 0x%X,\n", efuse_read_header, efuse_read_header2);
+					else
+						PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_ERR, "Error: EEPROM header: 0x%X,\n", efuse_read_header);
+
+					return HALMAC_RET_EEPROM_PARSING_FAIL;
+				} else {
+					value8 = *(pPhysical_efuse_map + efuse_index);
+					*(pLogical_efuse_map + eeprom_index) = value8;
+
+					eeprom_index++;
+					efuse_index++;
+
+					if (efuse_index > pHalmac_adapter->hw_config_info.efuse_size - HALMAC_PROTECTED_EFUSE_SIZE_88XX - 1)
+						return HALMAC_RET_EEPROM_PARSING_FAIL;
+
+					value8 = *(pPhysical_efuse_map + efuse_index);
+					*(pLogical_efuse_map + eeprom_index) = value8;
+
+					efuse_index++;
+
+					if (efuse_index > pHalmac_adapter->hw_config_info.efuse_size - HALMAC_PROTECTED_EFUSE_SIZE_88XX)
+						return HALMAC_RET_EEPROM_PARSING_FAIL;
+				}
+			}
+		}
+	} while (1);
+
+	pHalmac_adapter->efuse_end = efuse_index;
+
+	return HALMAC_RET_SUCCESS;
+}
+
+HALMAC_RET_STATUS
+halmac_read_logical_efuse_map_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN u8 *pMap
+)
+{
+	u8 *pEfuse_map = NULL;
+	u32 efuse_size;
+	VOID *pDriver_adapter = NULL;
+	HALMAC_RET_STATUS status = HALMAC_RET_SUCCESS;
+
+	pDriver_adapter = pHalmac_adapter->pDriver_adapter;
+	efuse_size = pHalmac_adapter->hw_config_info.efuse_size;
+
+	if (_FALSE == pHalmac_adapter->hal_efuse_map_valid) {
+		pEfuse_map = (u8 *)PLATFORM_RTL_MALLOC(pDriver_adapter, efuse_size);
+		if (NULL == pEfuse_map) {
+			PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_ERR, "[ERR]halmac allocate local efuse map Fail!!\n");
+			return HALMAC_RET_MALLOC_FAIL;
+		}
+
+		status = halmac_func_read_efuse_88xx(pHalmac_adapter, 0, efuse_size, pEfuse_map);
+		if (HALMAC_RET_SUCCESS != status) {
+			PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_ERR, "[ERR]halmac_read_efuse error = %x\n", status);
+			PLATFORM_RTL_FREE(pDriver_adapter, pEfuse_map, efuse_size);
+			return status;
+		}
+
+		if (NULL == pHalmac_adapter->pHalEfuse_map) {
+			pHalmac_adapter->pHalEfuse_map = (u8 *)PLATFORM_RTL_MALLOC(pDriver_adapter, efuse_size);
+			if (NULL == pHalmac_adapter->pHalEfuse_map) {
+				PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_ERR, "[ERR]halmac allocate efuse map Fail!!\n");
+				PLATFORM_RTL_FREE(pDriver_adapter, pEfuse_map, efuse_size);
+				return HALMAC_RET_MALLOC_FAIL;
+			}
+		}
+
+		PLATFORM_MUTEX_LOCK(pDriver_adapter, &(pHalmac_adapter->EfuseMutex));
+		PLATFORM_RTL_MEMCPY(pDriver_adapter, pHalmac_adapter->pHalEfuse_map, pEfuse_map, efuse_size);
+		pHalmac_adapter->hal_efuse_map_valid = _TRUE;
+		PLATFORM_MUTEX_UNLOCK(pDriver_adapter, &(pHalmac_adapter->EfuseMutex));
+
+		PLATFORM_RTL_FREE(pDriver_adapter, pEfuse_map, efuse_size);
+	}
+
+	if (HALMAC_RET_SUCCESS != halmac_eeprom_parser_88xx(pHalmac_adapter, pHalmac_adapter->pHalEfuse_map, pMap))
+		return HALMAC_RET_EEPROM_PARSING_FAIL;
+
+	return status;
+}
+
+HALMAC_RET_STATUS
+halmac_func_write_logical_efuse_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN u32 offset,
+	IN u8 value
+)
+{
+	u8 pg_efuse_byte1, pg_efuse_byte2;
+	u8 pg_block, pg_block_index;
+	u8 pg_efuse_header, pg_efuse_header2;
+	u8 *pEeprom_map = NULL;
+	u32 eeprom_size = pHalmac_adapter->hw_config_info.eeprom_size;
+	u32 efuse_end, pg_efuse_num;
+	VOID *pDriver_adapter = NULL;
+	HALMAC_RET_STATUS status = HALMAC_RET_SUCCESS;
+
+	pDriver_adapter = pHalmac_adapter->pDriver_adapter;
+
+	pEeprom_map = (u8 *)PLATFORM_RTL_MALLOC(pDriver_adapter, eeprom_size);
+	if (NULL == pEeprom_map) {
+		PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_ERR, "[ERR]halmac allocate local eeprom map Fail!!\n");
+		return HALMAC_RET_MALLOC_FAIL;
+	}
+	PLATFORM_RTL_MEMSET(pDriver_adapter, pEeprom_map, 0xFF, eeprom_size);
+
+	status = halmac_read_logical_efuse_map_88xx(pHalmac_adapter, pEeprom_map);
+	if (HALMAC_RET_SUCCESS != status) {
+		PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_ERR, "[ERR]halmac_read_logical_efuse_map_88xx error = %x\n", status);
+		PLATFORM_RTL_FREE(pDriver_adapter, pEeprom_map, eeprom_size);
+		return status;
+	}
+
+	if (*(pEeprom_map + offset) != value) {
+		efuse_end = pHalmac_adapter->efuse_end;
+		pg_block = (u8)(offset >> 3);
+		pg_block_index = (u8)((offset & (8 - 1)) >> 1);
+
+		if (offset > 0x7f) {
+			pg_efuse_header = (((pg_block & 0x07) << 5) & 0xE0) | 0x0F;
+			pg_efuse_header2 = (u8)(((pg_block & 0x78) << 1) + ((0x1 << pg_block_index) ^ 0x0F));
+		} else {
+			pg_efuse_header = (u8)((pg_block << 4) + ((0x01 << pg_block_index) ^ 0x0F));
+		}
+
+		if ((offset & 1) == 0) {
+			pg_efuse_byte1 = value;
+			pg_efuse_byte2 = *(pEeprom_map + offset + 1);
+		} else {
+			pg_efuse_byte1 = *(pEeprom_map + offset - 1);
+			pg_efuse_byte2 = value;
+		}
+
+		if (offset > 0x7f) {
+			pg_efuse_num = 4;
+			if (pHalmac_adapter->hw_config_info.efuse_size <= (pg_efuse_num + HALMAC_PROTECTED_EFUSE_SIZE_88XX + pHalmac_adapter->efuse_end)) {
+				PLATFORM_RTL_FREE(pDriver_adapter, pEeprom_map, eeprom_size);
+				return HALMAC_RET_EFUSE_NOT_ENOUGH;
+			}
+			halmac_func_write_efuse_88xx(pHalmac_adapter, efuse_end, pg_efuse_header);
+			halmac_func_write_efuse_88xx(pHalmac_adapter, efuse_end + 1, pg_efuse_header2);
+			halmac_func_write_efuse_88xx(pHalmac_adapter, efuse_end + 2, pg_efuse_byte1);
+			status = halmac_func_write_efuse_88xx(pHalmac_adapter, efuse_end + 3, pg_efuse_byte2);
+		} else {
+			pg_efuse_num = 3;
+			if (pHalmac_adapter->hw_config_info.efuse_size <= (pg_efuse_num + HALMAC_PROTECTED_EFUSE_SIZE_88XX + pHalmac_adapter->efuse_end)) {
+				PLATFORM_RTL_FREE(pDriver_adapter, pEeprom_map, eeprom_size);
+				return HALMAC_RET_EFUSE_NOT_ENOUGH;
+			}
+			halmac_func_write_efuse_88xx(pHalmac_adapter, efuse_end, pg_efuse_header);
+			halmac_func_write_efuse_88xx(pHalmac_adapter, efuse_end + 1, pg_efuse_byte1);
+			status = halmac_func_write_efuse_88xx(pHalmac_adapter, efuse_end + 2, pg_efuse_byte2);
+		}
+
+		if (HALMAC_RET_SUCCESS != status) {
+			PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_ERR, "[ERR]halmac_write_logical_efuse error = %x\n", status);
+			PLATFORM_RTL_FREE(pDriver_adapter, pEeprom_map, eeprom_size);
+			return status;
+		}
+	}
+
+	PLATFORM_RTL_FREE(pDriver_adapter, pEeprom_map, eeprom_size);
+
+	return HALMAC_RET_SUCCESS;
+}
+
+HALMAC_RET_STATUS
+halmac_func_pg_efuse_by_map_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN PHALMAC_PG_EFUSE_INFO pPg_efuse_info,
+	IN HALMAC_EFUSE_READ_CFG cfg
+)
+{
+	u8 *pEeprom_mask_updated = NULL;
+	u32 eeprom_mask_size = pHalmac_adapter->hw_config_info.eeprom_size >> 4;
+	VOID *pDriver_adapter = NULL;
+	HALMAC_RET_STATUS status = HALMAC_RET_SUCCESS;
+
+	pEeprom_mask_updated = (u8 *)PLATFORM_RTL_MALLOC(pDriver_adapter, eeprom_mask_size);
+	if (NULL == pEeprom_mask_updated) {
+		PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_ERR, "[ERR]halmac allocate local eeprom map Fail!!\n");
+		return HALMAC_RET_MALLOC_FAIL;
+	}
+	PLATFORM_RTL_MEMSET(pDriver_adapter, pEeprom_mask_updated, 0x00, eeprom_mask_size);
+
+	status = halmac_update_eeprom_mask_88xx(pHalmac_adapter, pPg_efuse_info, pEeprom_mask_updated);
+
+	if (HALMAC_RET_SUCCESS != status) {
+		PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_ERR, "[ERR]halmac_update_eeprom_mask_88xx error = %x\n", status);
+		PLATFORM_RTL_FREE(pDriver_adapter, pEeprom_mask_updated, eeprom_mask_size);
+		return status;
+	}
+
+	status = halmac_check_efuse_enough_88xx(pHalmac_adapter, pPg_efuse_info, pEeprom_mask_updated);
+
+	if (HALMAC_RET_SUCCESS != status) {
+		PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_ERR, "[ERR]halmac_check_efuse_enough_88xx error = %x\n", status);
+		PLATFORM_RTL_FREE(pDriver_adapter, pEeprom_mask_updated, eeprom_mask_size);
+		return status;
+	}
+
+	status = halmac_program_efuse_88xx(pHalmac_adapter, pPg_efuse_info, pEeprom_mask_updated);
+
+	if (HALMAC_RET_SUCCESS != status) {
+		PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_ERR, "[ERR]halmac_program_efuse_88xx error = %x\n", status);
+		PLATFORM_RTL_FREE(pDriver_adapter, pEeprom_mask_updated, eeprom_mask_size);
+		return status;
+	}
+
+	PLATFORM_RTL_FREE(pDriver_adapter, pEeprom_mask_updated, eeprom_mask_size);
+
+	return HALMAC_RET_SUCCESS;
+}
+
+HALMAC_RET_STATUS
+halmac_update_eeprom_mask_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	INOUT PHALMAC_PG_EFUSE_INFO	pPg_efuse_info,
+	OUT u8 *pEeprom_mask_updated
+)
+{
+	u8 *pEeprom_map = NULL;
+	u32 eeprom_size = pHalmac_adapter->hw_config_info.eeprom_size;
+	u8 *pEeprom_map_pg, *pEeprom_mask;
+	u16 i, j;
+	u16 map_byte_offset, mask_byte_offset;
+	HALMAC_RET_STATUS status = HALMAC_RET_SUCCESS;
+
+	VOID *pDriver_adapter = NULL;
+
+	pDriver_adapter = pHalmac_adapter->pDriver_adapter;
+
+	pEeprom_map = (u8 *)PLATFORM_RTL_MALLOC(pDriver_adapter, eeprom_size);
+	if (NULL == pEeprom_map) {
+		PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_ERR, "[ERR]halmac allocate local eeprom map Fail!!\n");
+		return HALMAC_RET_MALLOC_FAIL;
+	}
+	PLATFORM_RTL_MEMSET(pDriver_adapter, pEeprom_map, 0xFF, eeprom_size);
+
+	PLATFORM_RTL_MEMSET(pDriver_adapter, pEeprom_mask_updated, 0x00, pPg_efuse_info->efuse_mask_size);
+
+	status = halmac_read_logical_efuse_map_88xx(pHalmac_adapter, pEeprom_map);
+
+	if (HALMAC_RET_SUCCESS != status) {
+		PLATFORM_RTL_FREE(pDriver_adapter, pEeprom_map, eeprom_size);
+		return status;
+	}
+
+	pEeprom_map_pg = pPg_efuse_info->pEfuse_map;
+	pEeprom_mask = pPg_efuse_info->pEfuse_mask;
+
+
+	for (i = 0; i < pPg_efuse_info->efuse_mask_size; i++)
+		*(pEeprom_mask_updated + i) = *(pEeprom_mask + i);
+
+	for (i = 0; i < pPg_efuse_info->efuse_map_size; i = i + 16) {
+		for (j = 0; j < 16; j = j + 2) {
+			map_byte_offset = i + j;
+			mask_byte_offset = i >> 4;
+			if (*(pEeprom_map_pg + map_byte_offset) == *(pEeprom_map + map_byte_offset)) {
+				if (*(pEeprom_map_pg + map_byte_offset + 1) == *(pEeprom_map + map_byte_offset + 1)) {
+					switch (j) {
+					case 0:
+						*(pEeprom_mask_updated + mask_byte_offset) = *(pEeprom_mask_updated + mask_byte_offset) & (BIT(4) ^ 0xFF);
+						break;
+					case 2:
+						*(pEeprom_mask_updated + mask_byte_offset) = *(pEeprom_mask_updated + mask_byte_offset) & (BIT(5) ^ 0xFF);
+						break;
+					case 4:
+						*(pEeprom_mask_updated + mask_byte_offset) = *(pEeprom_mask_updated + mask_byte_offset) & (BIT(6) ^ 0xFF);
+						break;
+					case 6:
+						*(pEeprom_mask_updated + mask_byte_offset) = *(pEeprom_mask_updated + mask_byte_offset) & (BIT(7) ^ 0xFF);
+						break;
+					case 8:
+						*(pEeprom_mask_updated + mask_byte_offset) = *(pEeprom_mask_updated + mask_byte_offset) & (BIT(0) ^ 0xFF);
+						break;
+					case 10:
+						*(pEeprom_mask_updated + mask_byte_offset) = *(pEeprom_mask_updated + mask_byte_offset) & (BIT(1) ^ 0xFF);
+						break;
+					case 12:
+						*(pEeprom_mask_updated + mask_byte_offset) = *(pEeprom_mask_updated + mask_byte_offset) & (BIT(2) ^ 0xFF);
+						break;
+					case 14:
+						*(pEeprom_mask_updated + mask_byte_offset) = *(pEeprom_mask_updated + mask_byte_offset) & (BIT(3) ^ 0xFF);
+						break;
+					default:
+						break;
+					}
+				}
+			}
+		}
+	}
+
+	PLATFORM_RTL_FREE(pDriver_adapter, pEeprom_map, eeprom_size);
+
+	return status;
+}
+
+HALMAC_RET_STATUS
+halmac_check_efuse_enough_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN PHALMAC_PG_EFUSE_INFO pPg_efuse_info,
+	IN u8 *pEeprom_mask_updated
+)
+{
+	u8 pre_word_enb, word_enb;
+	u8 pg_efuse_header, pg_efuse_header2;
+	u8 pg_block;
+	u16 i, j;
+	u32 efuse_end;
+	u32 tmp_eeprom_offset, pg_efuse_num = 0;
+
+	efuse_end = pHalmac_adapter->efuse_end;
+
+	for (i = 0; i < pPg_efuse_info->efuse_map_size; i = i + 8) {
+		tmp_eeprom_offset = i;
+
+		if ((tmp_eeprom_offset & 7) > 0) {
+			pre_word_enb = (*(pEeprom_mask_updated + (i >> 4)) & 0x0F);
+			word_enb = pre_word_enb ^ 0x0F;
+		} else {
+			pre_word_enb = (*(pEeprom_mask_updated + (i >> 4)) >> 4);
+			word_enb = pre_word_enb ^ 0x0F;
+		}
+
+		pg_block = (u8)(tmp_eeprom_offset >> 3);
+
+		if (pre_word_enb > 0) {
+			if (tmp_eeprom_offset > 0x7f) {
+				pg_efuse_header = (((pg_block & 0x07) << 5) & 0xE0) | 0x0F;
+				pg_efuse_header2 = (u8)(((pg_block & 0x78) << 1) + word_enb);
+			} else {
+				pg_efuse_header = (u8)((pg_block << 4) + word_enb);
+			}
+
+			if (tmp_eeprom_offset > 0x7f) {
+				pg_efuse_num++;
+				pg_efuse_num++;
+				efuse_end = efuse_end + 2;
+				for (j = 0; j < 4; j++) {
+					if (((pre_word_enb >> j) & 0x1) > 0) {
+						pg_efuse_num++;
+						pg_efuse_num++;
+						efuse_end = efuse_end + 2;
+					}
+				}
+			} else {
+				pg_efuse_num++;
+				efuse_end = efuse_end + 1;
+				for (j = 0; j < 4; j++) {
+					if (((pre_word_enb >> j) & 0x1) > 0) {
+						pg_efuse_num++;
+						pg_efuse_num++;
+						efuse_end = efuse_end + 2;
+					}
+				}
+			}
+		}
+	}
+
+	if (pHalmac_adapter->hw_config_info.efuse_size <= (pg_efuse_num + HALMAC_PROTECTED_EFUSE_SIZE_88XX + pHalmac_adapter->efuse_end))
+		return HALMAC_RET_EFUSE_NOT_ENOUGH;
+
+	return HALMAC_RET_SUCCESS;
+}
+
+HALMAC_RET_STATUS
+halmac_program_efuse_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN PHALMAC_PG_EFUSE_INFO pPg_efuse_info,
+	IN u8 *pEeprom_mask_updated
+)
+{
+	u8 pre_word_enb, word_enb;
+	u8 pg_efuse_header, pg_efuse_header2;
+	u8 pg_block;
+	u16 i, j;
+	u32 efuse_end;
+	u32 tmp_eeprom_offset;
+	HALMAC_RET_STATUS status = HALMAC_RET_SUCCESS;
+
+	efuse_end = pHalmac_adapter->efuse_end;
+
+	for (i = 0; i < pPg_efuse_info->efuse_map_size; i = i + 8) {
+		tmp_eeprom_offset = i;
+
+		if (((tmp_eeprom_offset >> 3) & 1) > 0) {
+			pre_word_enb = (*(pEeprom_mask_updated + (i >> 4)) & 0x0F);
+			word_enb = pre_word_enb ^ 0x0F;
+		} else {
+			pre_word_enb = (*(pEeprom_mask_updated + (i >> 4)) >> 4);
+			word_enb = pre_word_enb ^ 0x0F;
+		}
+
+		pg_block = (u8)(tmp_eeprom_offset >> 3);
+
+		if (pre_word_enb > 0) {
+			if (tmp_eeprom_offset > 0x7f) {
+				pg_efuse_header = (((pg_block & 0x07) << 5) & 0xE0) | 0x0F;
+				pg_efuse_header2 = (u8)(((pg_block & 0x78) << 1) + word_enb);
+			} else {
+				pg_efuse_header = (u8)((pg_block << 4) + word_enb);
+			}
+
+			if (tmp_eeprom_offset > 0x7f) {
+				halmac_func_write_efuse_88xx(pHalmac_adapter, efuse_end, pg_efuse_header);
+				status = halmac_func_write_efuse_88xx(pHalmac_adapter, efuse_end + 1, pg_efuse_header2);
+				efuse_end = efuse_end + 2;
+				for (j = 0; j < 4; j++) {
+					if (((pre_word_enb >> j) & 0x1) > 0) {
+						halmac_func_write_efuse_88xx(pHalmac_adapter, efuse_end, *(pPg_efuse_info->pEfuse_map + tmp_eeprom_offset + (j << 1)));
+						status = halmac_func_write_efuse_88xx(pHalmac_adapter, efuse_end + 1, *(pPg_efuse_info->pEfuse_map + tmp_eeprom_offset + (j << 1) + 1));
+						efuse_end = efuse_end + 2;
+					}
+				}
+			} else {
+				status = halmac_func_write_efuse_88xx(pHalmac_adapter, efuse_end, pg_efuse_header);
+				efuse_end = efuse_end + 1;
+				for (j = 0; j < 4; j++) {
+					if (((pre_word_enb >> j) & 0x1) > 0) {
+						halmac_func_write_efuse_88xx(pHalmac_adapter, efuse_end, *(pPg_efuse_info->pEfuse_map + tmp_eeprom_offset + (j << 1)));
+						status = halmac_func_write_efuse_88xx(pHalmac_adapter, efuse_end + 1, *(pPg_efuse_info->pEfuse_map + tmp_eeprom_offset + (j << 1) + 1));
+						efuse_end = efuse_end + 2;
+					}
+				}
+			}
+		}
+	}
+
+	return status;
+}
+
+HALMAC_RET_STATUS
+halmac_update_fw_info_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN u8 *pHamacl_fw,
+	IN u32 halmac_fw_size
+)
+{
+	PHALMAC_FW_VERSION pFw_info = &(pHalmac_adapter->fw_version);
+
+	pFw_info->version = rtk_le16_to_cpu(*((u16 *)(pHamacl_fw + HALMAC_FWHDR_OFFSET_VERSION_88XX)));
+	pFw_info->sub_version = *(pHamacl_fw + HALMAC_FWHDR_OFFSET_SUBVERSION_88XX);
+	pFw_info->sub_index = *(pHamacl_fw + HALMAC_FWHDR_OFFSET_SUBINDEX_88XX);
+	pFw_info->h2c_version = (u16)rtk_le32_to_cpu(*((u32 *)(pHamacl_fw + HALMAC_FWHDR_OFFSET_H2C_FORMAT_VER_88XX)));
+	pFw_info->build_time.month = *(pHamacl_fw + HALMAC_FWHDR_OFFSET_MONTH_88XX);
+	pFw_info->build_time.date = *(pHamacl_fw + HALMAC_FWHDR_OFFSET_DATE_88XX);
+	pFw_info->build_time.hour = *(pHamacl_fw + HALMAC_FWHDR_OFFSET_HOUR_88XX);
+	pFw_info->build_time.min = *(pHamacl_fw + HALMAC_FWHDR_OFFSET_MIN_88XX);
+	pFw_info->build_time.year = rtk_le16_to_cpu(*((u16 *)(pHamacl_fw + HALMAC_FWHDR_OFFSET_YEAR_88XX)));
+
+	return HALMAC_RET_SUCCESS;
+}
+
+HALMAC_RET_STATUS
+halmac_dlfw_to_mem_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN u8 *pRam_code,
+	IN u32 dest,
+	IN u32 code_size
+)
+{
+	u8 *pCode_ptr;
+	u8 first_part;
+	u32 mem_offset;
+	u32 pkt_size_tmp, send_pkt_size;
+	VOID *pDriver_adapter = NULL;
+	PHALMAC_API pHalmac_api;
+
+	pDriver_adapter = pHalmac_adapter->pDriver_adapter;
+	pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api;
+
+	pCode_ptr = pRam_code;
+	mem_offset = 0;
+	first_part = 1;
+	pkt_size_tmp = code_size;
+
+	HALMAC_REG_WRITE_32(pHalmac_adapter, REG_DDMA_CH0CTRL, HALMAC_REG_READ_32(pHalmac_adapter, REG_DDMA_CH0CTRL) | BIT_DDMACH0_RESET_CHKSUM_STS);
+
+	while (0 != pkt_size_tmp) {
+		if (pkt_size_tmp >= pHalmac_adapter->max_download_size)
+			send_pkt_size = pHalmac_adapter->max_download_size;
+		else
+			send_pkt_size = pkt_size_tmp;
+
+		if (HALMAC_RET_SUCCESS != halmac_send_fwpkt_88xx(pHalmac_adapter, pCode_ptr + mem_offset, send_pkt_size)) {
+			PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "halmac_send_fwpkt_88xx fail!!");
+			return HALMAC_RET_DLFW_FAIL;
+		}
+
+		if (HALMAC_RET_SUCCESS != halmac_iddma_dlfw_88xx(pHalmac_adapter, HALMAC_OCPBASE_TXBUF_88XX + pHalmac_adapter->hw_config_info.txdesc_size,
+			    dest + mem_offset, send_pkt_size, first_part)) {
+			PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "halmac_iddma_dlfw_88xx fail!!");
+			return HALMAC_RET_DLFW_FAIL;
+		}
+
+		first_part = 0;
+		mem_offset += send_pkt_size;
+		pkt_size_tmp -= send_pkt_size;
+	}
+
+	if (HALMAC_RET_SUCCESS != halmac_check_fw_chksum_88xx(pHalmac_adapter, dest)) {
+		PLATFORM_MSG_PRINT(pHalmac_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "halmac_check_fw_chksum_88xx fail!!");
+		return HALMAC_RET_DLFW_FAIL;
+	}
+
+	return HALMAC_RET_SUCCESS;
+}
+
+HALMAC_RET_STATUS
+halmac_send_fwpkt_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN u8 *pRam_code,
+	IN u32 code_size
+)
+{
+	VOID *pDriver_adapter = pHalmac_adapter->pDriver_adapter;
+
+	if (HALMAC_RET_SUCCESS != halmac_download_rsvd_page_88xx(pHalmac_adapter, pRam_code, code_size)) {
+		PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_FW, HALMAC_DBG_ERR, "PLATFORM_SEND_RSVD_PAGE 0 error!!\n");
+		return HALMAC_RET_DL_RSVD_PAGE_FAIL;
+	}
+
+	return HALMAC_RET_SUCCESS;
+}
+
+HALMAC_RET_STATUS
+halmac_iddma_dlfw_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN u32 source,
+	IN u32 dest,
+	IN u32 length,
+	IN u8 first
+)
+{
+	u32 counter;
+	u32 ch0_control = (u32)(BIT_DDMACH0_CHKSUM_EN | BIT_DDMACH0_OWN);
+	VOID *pDriver_adapter = NULL;
+	PHALMAC_API pHalmac_api;
+
+	pDriver_adapter = pHalmac_adapter->pDriver_adapter;
+	pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api;
+
+	counter = HALMC_DDMA_POLLING_COUNT;
+	while (HALMAC_REG_READ_32(pHalmac_adapter, REG_DDMA_CH0CTRL) & BIT_DDMACH0_OWN) {
+		counter--;
+		if (0 == counter) {
+			PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_FW, HALMAC_DBG_ERR, "halmac_iddma_dlfw_88xx error-1!!\n");
+			return HALMAC_RET_DDMA_FAIL;
+		}
+	}
+
+	ch0_control |= (length & BIT_MASK_DDMACH0_DLEN);
+	if (0 == first)
+		ch0_control |= BIT_DDMACH0_CHKSUM_CONT;
+
+	HALMAC_REG_WRITE_32(pHalmac_adapter, REG_DDMA_CH0SA, source);
+	HALMAC_REG_WRITE_32(pHalmac_adapter, REG_DDMA_CH0DA, dest);
+	HALMAC_REG_WRITE_32(pHalmac_adapter, REG_DDMA_CH0CTRL, ch0_control);
+
+	counter = HALMC_DDMA_POLLING_COUNT;
+	while (HALMAC_REG_READ_32(pHalmac_adapter, REG_DDMA_CH0CTRL) & BIT_DDMACH0_OWN) {
+		counter--;
+		if (0 == counter) {
+			PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_FW, HALMAC_DBG_ERR, "halmac_iddma_dlfw_88xx error-2!!\n");
+			return HALMAC_RET_DDMA_FAIL;
+		}
+	}
+
+	return HALMAC_RET_SUCCESS;
+}
+
+HALMAC_RET_STATUS
+halmac_check_fw_chksum_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN u32 memory_address
+)
+{
+	u8 mcu_fw_ctrl;
+	VOID *pDriver_adapter = NULL;
+	PHALMAC_API pHalmac_api;
+
+	pDriver_adapter = pHalmac_adapter->pDriver_adapter;
+	pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api;
+
+	mcu_fw_ctrl = HALMAC_REG_READ_8(pHalmac_adapter, REG_MCUFW_CTRL);
+
+	if (HALMAC_REG_READ_32(pHalmac_adapter, REG_DDMA_CH0CTRL) & BIT_DDMACH0_CHKSUM_STS) {
+		if (memory_address < HALMAC_OCPBASE_DMEM_88XX) {
+			mcu_fw_ctrl |= BIT_IMEM_DW_OK;
+			HALMAC_REG_WRITE_8(pHalmac_adapter, REG_MCUFW_CTRL, (u8)(mcu_fw_ctrl & ~(BIT_IMEM_CHKSUM_OK)));
+		} else {
+			mcu_fw_ctrl |= BIT_DMEM_DW_OK;
+			HALMAC_REG_WRITE_8(pHalmac_adapter, REG_MCUFW_CTRL, (u8)(mcu_fw_ctrl & ~(BIT_DMEM_CHKSUM_OK)));
+		}
+
+		PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_FW, HALMAC_DBG_ERR, "halmac_check_fw_chksum_88xx error!!\n");
+
+		return HALMAC_RET_FW_CHECKSUM_FAIL;
+	} else {
+		if (memory_address < HALMAC_OCPBASE_DMEM_88XX) {
+			mcu_fw_ctrl |= BIT_IMEM_DW_OK;
+			HALMAC_REG_WRITE_8(pHalmac_adapter, REG_MCUFW_CTRL, (u8)(mcu_fw_ctrl | BIT_IMEM_CHKSUM_OK));
+		} else {
+			mcu_fw_ctrl |= BIT_DMEM_DW_OK;
+			HALMAC_REG_WRITE_8(pHalmac_adapter, REG_MCUFW_CTRL, (u8)(mcu_fw_ctrl | BIT_DMEM_CHKSUM_OK));
+		}
+
+		return HALMAC_RET_SUCCESS;
+	}
+}
+
+HALMAC_RET_STATUS
+halmac_dlfw_end_flow_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter
+)
+{
+	u8 value8;
+	u32 counter;
+	VOID *pDriver_adapter = pHalmac_adapter->pDriver_adapter;
+	PHALMAC_API pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api;
+
+	HALMAC_REG_WRITE_32(pHalmac_adapter, REG_TXDMA_STATUS, BIT(2));
+
+	/* Check IMEM & DMEM checksum is OK or not */
+	if (0x50 == (HALMAC_REG_READ_8(pHalmac_adapter, REG_MCUFW_CTRL) & 0x50))
+		HALMAC_REG_WRITE_16(pHalmac_adapter, REG_MCUFW_CTRL, (u16)(HALMAC_REG_READ_16(pHalmac_adapter, REG_MCUFW_CTRL) | BIT_FW_DW_RDY));
+	else
+		return HALMAC_RET_DLFW_FAIL;
+
+	HALMAC_REG_WRITE_8(pHalmac_adapter, REG_MCUFW_CTRL, (u8)(HALMAC_REG_READ_8(pHalmac_adapter, REG_MCUFW_CTRL) & ~(BIT(0))));
+
+	value8 = HALMAC_REG_READ_8(pHalmac_adapter, REG_RSV_CTRL + 1);
+	value8 = (u8)(value8 | BIT(0));
+	HALMAC_REG_WRITE_8(pHalmac_adapter, REG_RSV_CTRL + 1, value8);
+
+	value8 = HALMAC_REG_READ_8(pHalmac_adapter, REG_SYS_FUNC_EN + 1);
+	value8 = (u8)(value8 | BIT(2));
+	HALMAC_REG_WRITE_8(pHalmac_adapter, REG_SYS_FUNC_EN + 1, value8); /* Release MCU reset */
+	PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "Download Finish, Reset CPU\n");
+
+	HALMAC_REG_WRITE_32(pHalmac_adapter, REG_WL2LTECOEX_INDIRECT_ACCESS_CTRL_V1, 0xC00F0038);
+
+	counter = 10000;
+	while (0xC078 != HALMAC_REG_READ_16(pHalmac_adapter, REG_MCUFW_CTRL)) {
+		if (counter == 0) {
+			PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "Check 0x80 = 0xC078 fail\n");
+			if (0xFAAAAA00 == (HALMAC_REG_READ_32(pHalmac_adapter, REG_FW_DBG7) & 0xFFFFFF00))
+				PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "Key fail\n");
+			return HALMAC_RET_DLFW_FAIL;
+		}
+		counter--;
+		PLATFORM_RTL_DELAY_US(pDriver_adapter, 50);
+	}
+
+	PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "Check 0x80 = 0xC078 counter = %d\n", counter);
+
+	return HALMAC_RET_SUCCESS;
+}
+
+HALMAC_RET_STATUS
+halmac_free_dl_fw_end_flow_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter
+)
+{
+	u32 counter;
+	VOID *pDriver_adapter = pHalmac_adapter->pDriver_adapter;
+	PHALMAC_API pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api;
+
+	counter = 100;
+	while (0 != HALMAC_REG_READ_8(pHalmac_adapter, REG_HMETFR + 3)) {
+		counter--;
+		if (0 == counter) {
+			PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "[ERR]0x1CF != 0\n");
+			return HALMAC_RET_DLFW_FAIL;
+		}
+		PLATFORM_RTL_DELAY_US(pDriver_adapter, 50);
+	}
+
+	HALMAC_REG_WRITE_8(pHalmac_adapter, REG_HMETFR + 3, ID_INFORM_DLEMEM_RDY);
+
+	counter = 10000;
+	while (ID_INFORM_DLEMEM_RDY != HALMAC_REG_READ_8(pHalmac_adapter, REG_C2HEVT_3 + 3)) {
+		counter--;
+		if (0 == counter) {
+			PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "[ERR]0x1AF != 0x80\n");
+			return HALMAC_RET_DLFW_FAIL;
+		}
+		PLATFORM_RTL_DELAY_US(pDriver_adapter, 50);
+	}
+
+	HALMAC_REG_WRITE_8(pHalmac_adapter, REG_C2HEVT_3 + 3, 0);
+
+	return HALMAC_RET_SUCCESS;
+}
+
+HALMAC_RET_STATUS
+halmac_pwr_seq_parser_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN u8 cut,
+	IN u8 fab,
+	IN u8 intf,
+	IN PHALMAC_WLAN_PWR_CFG *ppPwr_seq_cfg
+)
+{
+	u32 seq_idx = 0;
+	VOID *pDriver_adapter = NULL;
+	HALMAC_RET_STATUS status = HALMAC_RET_SUCCESS;
+	PHALMAC_WLAN_PWR_CFG pSeq_cmd;
+
+	pDriver_adapter = pHalmac_adapter->pDriver_adapter;
+
+	do {
+		pSeq_cmd = &(*ppPwr_seq_cfg[seq_idx]);
+
+		if (NULL == pSeq_cmd)
+			break;
+
+		status = halmac_pwr_sub_seq_parer_88xx(pHalmac_adapter, cut, fab, intf, pSeq_cmd);
+		if (HALMAC_RET_SUCCESS != status) {
+			PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "[Err]pwr sub seq parser fail, status = 0x%X!\n", status);
+			return status;
+		}
+
+		seq_idx++;
+	} while (1);
+
+	return status;
+}
+
+HALMAC_RET_STATUS
+halmac_pwr_sub_seq_parer_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN u8 cut,
+	IN u8 fab,
+	IN u8 intf,
+	IN PHALMAC_WLAN_PWR_CFG pPwr_sub_seq_cfg
+)
+{
+	u8 value, flag;
+	u8 polling_bit;
+	u32 offset;
+	u32 polling_count;
+	static u32 poll_to_static, poll_long_static;
+	VOID *pDriver_adapter = NULL;
+	PHALMAC_WLAN_PWR_CFG pSub_seq_cmd;
+	PHALMAC_API pHalmac_api;
+
+	pDriver_adapter = pHalmac_adapter->pDriver_adapter;
+	pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api;
+
+	pSub_seq_cmd = pPwr_sub_seq_cfg;
+
+	do {
+		if ((pSub_seq_cmd->interface_msk & intf) && (pSub_seq_cmd->fab_msk & fab) && (pSub_seq_cmd->cut_msk & cut)) {
+			switch (pSub_seq_cmd->cmd) {
+			case HALMAC_PWR_CMD_WRITE:
+				if (pSub_seq_cmd->base == HALMAC_PWR_BASEADDR_SDIO)
+					offset = pSub_seq_cmd->offset | SDIO_LOCAL_OFFSET;
+				else
+					offset = pSub_seq_cmd->offset;
+
+				value = HALMAC_REG_READ_8(pHalmac_adapter, offset);
+				value = (u8)(value & (u8)(~(pSub_seq_cmd->msk)));
+				value = (u8)(value | (u8)(pSub_seq_cmd->value & pSub_seq_cmd->msk));
+
+				HALMAC_REG_WRITE_8(pHalmac_adapter, offset, value);
+				break;
+			case HALMAC_PWR_CMD_POLLING:
+				polling_bit = 0;
+				polling_count = HALMAC_POLLING_READY_TIMEOUT_COUNT;
+				flag = 0;
+
+
+				if (pSub_seq_cmd->base == HALMAC_PWR_BASEADDR_SDIO)
+					offset = pSub_seq_cmd->offset | SDIO_LOCAL_OFFSET;
+				else
+					offset = pSub_seq_cmd->offset;
+
+				do {
+					polling_count--;
+					value = HALMAC_REG_READ_8(pHalmac_adapter, offset);
+					value = (u8)(value & pSub_seq_cmd->msk);
+
+					if (value == (pSub_seq_cmd->value & pSub_seq_cmd->msk)) {
+						polling_bit = 1;
+					} else {
+						if (0 == polling_count) {
+							if (HALMAC_INTERFACE_PCIE == pHalmac_adapter->halmac_interface && 0 == flag) {
+								/* For PCIE + USB package poll power bit timeout issue */
+								poll_to_static++;
+								PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_PWR, HALMAC_DBG_WARN, "[WARN]PCIE polling timeout : %d!!\n", poll_to_static);
+								HALMAC_REG_WRITE_8(pHalmac_adapter, REG_SYS_PW_CTRL, HALMAC_REG_READ_8(pHalmac_adapter, REG_SYS_PW_CTRL) | BIT(3));
+								HALMAC_REG_WRITE_8(pHalmac_adapter, REG_SYS_PW_CTRL, HALMAC_REG_READ_8(pHalmac_adapter, REG_SYS_PW_CTRL) & ~BIT(3));
+								polling_bit = 0;
+								polling_count = HALMAC_POLLING_READY_TIMEOUT_COUNT;
+								flag = 1;
+							} else {
+								PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_PWR, HALMAC_DBG_ERR, "[ERR]Pwr cmd polling timeout!!\n");
+								PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_PWR, HALMAC_DBG_ERR, "[ERR]Pwr cmd offset : %X!!\n", pSub_seq_cmd->offset);
+								PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_PWR, HALMAC_DBG_ERR, "[ERR]Pwr cmd value : %X!!\n", pSub_seq_cmd->value);
+								PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_PWR, HALMAC_DBG_ERR, "[ERR]Pwr cmd msk : %X!!\n", pSub_seq_cmd->msk);
+								PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_PWR, HALMAC_DBG_ERR, "[ERR]Read offset = %X value = %X!!\n", offset, value);
+								return HALMAC_RET_PWRSEQ_POLLING_FAIL;
+							}
+						} else {
+							PLATFORM_RTL_DELAY_US(pDriver_adapter, 50);
+						}
+					}
+				} while (!polling_bit);
+				break;
+			case HALMAC_PWR_CMD_DELAY:
+				if (pSub_seq_cmd->value == HALMAC_PWRSEQ_DELAY_US)
+					PLATFORM_RTL_DELAY_US(pDriver_adapter, pSub_seq_cmd->offset);
+				else
+					PLATFORM_RTL_DELAY_US(pDriver_adapter, 1000 * pSub_seq_cmd->offset);
+				break;
+			case HALMAC_PWR_CMD_READ:
+				break;
+			case HALMAC_PWR_CMD_END:
+				return HALMAC_RET_SUCCESS;
+			default:
+				return HALMAC_RET_PWRSEQ_CMD_INCORRECT;
+			}
+		}
+		pSub_seq_cmd++;
+	} while (1);
+
+
+	return HALMAC_RET_SUCCESS;
+}
+
+HALMAC_RET_STATUS
+halmac_get_h2c_buff_free_space_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter
+)
+{
+	u32 hw_wptr, fw_rptr;
+	PHALMAC_API pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api;
+
+	hw_wptr = HALMAC_REG_READ_32(pHalmac_adapter, REG_H2C_PKT_WRITEADDR) & BIT_MASK_H2C_WR_ADDR;
+	fw_rptr = HALMAC_REG_READ_32(pHalmac_adapter, REG_H2C_PKT_READADDR) & BIT_MASK_H2C_READ_ADDR;
+
+	if (hw_wptr >= fw_rptr)
+		pHalmac_adapter->h2c_buf_free_space = pHalmac_adapter->h2c_buff_size - (hw_wptr - fw_rptr);
+	else
+		pHalmac_adapter->h2c_buf_free_space = fw_rptr - hw_wptr;
+
+	return HALMAC_RET_SUCCESS;
+}
+
+HALMAC_RET_STATUS
+halmac_send_h2c_pkt_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN u8 *pHal_h2c_cmd,
+	IN u32 size,
+	IN u8 ack
+)
+{
+	u32 counter = 100;
+	VOID *pDriver_adapter = pHalmac_adapter->pDriver_adapter;
+	HALMAC_RET_STATUS status = HALMAC_RET_SUCCESS;
+
+	while (pHalmac_adapter->h2c_buf_free_space <= HALMAC_H2C_CMD_SIZE_UNIT_88XX) {
+		halmac_get_h2c_buff_free_space_88xx(pHalmac_adapter);
+		counter--;
+		if (0 == counter) {
+			PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "h2c free space is not enough!!\n");
+			return HALMAC_RET_H2C_SPACE_FULL;
+		}
+	}
+
+	/* Send TxDesc + H2C_CMD */
+	if (_FALSE == PLATFORM_SEND_H2C_PKT(pDriver_adapter, pHal_h2c_cmd, size)) {
+		PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "Send H2C_CMD pkt error!!\n");
+		return HALMAC_RET_SEND_H2C_FAIL;
+	}
+
+	pHalmac_adapter->h2c_buf_free_space -= HALMAC_H2C_CMD_SIZE_UNIT_88XX;
+
+	PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "H2C free space : %d\n", pHalmac_adapter->h2c_buf_free_space);
+
+	return status;
+}
+
+HALMAC_RET_STATUS
+halmac_download_rsvd_page_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN u8 *pHal_buf,
+	IN u32 size
+)
+{
+	u8 restore[3];
+	u8 value8;
+	u32 counter;
+	VOID *pDriver_adapter = NULL;
+	PHALMAC_API pHalmac_api;
+	HALMAC_RET_STATUS status = HALMAC_RET_SUCCESS;
+
+	pDriver_adapter = pHalmac_adapter->pDriver_adapter;
+	pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api;
+
+	if (0 == size) {
+		PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "Rsvd page packet size is zero!!\n");
+		return HALMAC_RET_ZERO_LEN_RSVD_PACKET;
+	}
+
+	value8 = HALMAC_REG_READ_8(pHalmac_adapter, REG_FIFOPAGE_CTRL_2 + 1);
+	value8 = (u8)(value8 | BIT(7));
+	HALMAC_REG_WRITE_8(pHalmac_adapter, REG_FIFOPAGE_CTRL_2 + 1, value8);
+
+	value8 = HALMAC_REG_READ_8(pHalmac_adapter, REG_CR + 1);
+	restore[0] = value8;
+	value8 = (u8)(value8 | BIT(0));
+	HALMAC_REG_WRITE_8(pHalmac_adapter, REG_CR + 1, value8);
+
+	value8 = HALMAC_REG_READ_8(pHalmac_adapter, REG_BCN_CTRL);
+	restore[1] = value8;
+	value8 = (u8)((value8 & ~(BIT(3))) | BIT(4));
+	HALMAC_REG_WRITE_8(pHalmac_adapter, REG_BCN_CTRL, value8);
+
+	value8 = HALMAC_REG_READ_8(pHalmac_adapter, REG_FWHW_TXQ_CTRL + 2);
+	restore[2] = value8;
+	value8 = (u8)(value8 & ~(BIT(6)));
+	HALMAC_REG_WRITE_8(pHalmac_adapter, REG_FWHW_TXQ_CTRL + 2, value8);
+
+	if (_FALSE == PLATFORM_SEND_RSVD_PAGE(pDriver_adapter, pHal_buf, size)) {
+		PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "PLATFORM_SEND_RSVD_PAGE 1 error!!\n");
+		status = HALMAC_RET_DL_RSVD_PAGE_FAIL;
+	}
+
+	/* Check Bcn_Valid_Bit */
+	counter = 1000;
+	while (!(HALMAC_REG_READ_8(pHalmac_adapter, REG_FIFOPAGE_CTRL_2 + 1) & BIT(7))) {
+		PLATFORM_RTL_DELAY_US(pDriver_adapter, 10);
+		counter--;
+		if (0 == counter) {
+			PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "Polling Bcn_Valid_Fail error!!\n");
+			status = HALMAC_RET_POLLING_BCN_VALID_FAIL;
+			break;
+		}
+	}
+
+	value8 = HALMAC_REG_READ_8(pHalmac_adapter, REG_FIFOPAGE_CTRL_2 + 1);
+	HALMAC_REG_WRITE_8(pHalmac_adapter, REG_FIFOPAGE_CTRL_2 + 1, (value8 | BIT(7)));
+
+	HALMAC_REG_WRITE_8(pHalmac_adapter, REG_FWHW_TXQ_CTRL + 2, restore[2]);
+	HALMAC_REG_WRITE_8(pHalmac_adapter, REG_BCN_CTRL, restore[1]);
+	HALMAC_REG_WRITE_8(pHalmac_adapter, REG_CR + 1, restore[0]);
+
+	return status;
+}
+
+HALMAC_RET_STATUS
+halmac_set_h2c_header_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	OUT u8 *pHal_h2c_hdr,
+	IN u16 *seq,
+	IN u8 ack
+)
+{
+	VOID *pDriver_adapter = pHalmac_adapter->pDriver_adapter;
+
+	PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_set_h2c_header_88xx!!\n");
+
+	H2C_CMD_HEADER_SET_CATEGORY(pHal_h2c_hdr, 0x00);
+	H2C_CMD_HEADER_SET_TOTAL_LEN(pHal_h2c_hdr, 16);
+
+	PLATFORM_MUTEX_LOCK(pDriver_adapter, &(pHalmac_adapter->h2c_seq_mutex));
+	H2C_CMD_HEADER_SET_SEQ_NUM(pHal_h2c_hdr, pHalmac_adapter->h2c_packet_seq);
+	*seq = pHalmac_adapter->h2c_packet_seq;
+	pHalmac_adapter->h2c_packet_seq++;
+	PLATFORM_MUTEX_UNLOCK(pDriver_adapter, &(pHalmac_adapter->h2c_seq_mutex));
+
+	if (_TRUE == ack)
+		H2C_CMD_HEADER_SET_ACK(pHal_h2c_hdr, _TRUE);
+
+	return HALMAC_RET_SUCCESS;
+}
+
+HALMAC_RET_STATUS
+halmac_set_fw_offload_h2c_header_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	OUT u8 *pHal_h2c_hdr,
+	IN PHALMAC_H2C_HEADER_INFO pH2c_header_info,
+	OUT u16 *pSeq_num
+)
+{
+	VOID *pDriver_adapter = pHalmac_adapter->pDriver_adapter;
+
+	PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_set_fw_offload_h2c_header_88xx!!\n");
+
+	FW_OFFLOAD_H2C_SET_TOTAL_LEN(pHal_h2c_hdr, 8 + pH2c_header_info->content_size);
+	FW_OFFLOAD_H2C_SET_SUB_CMD_ID(pHal_h2c_hdr, pH2c_header_info->sub_cmd_id);
+
+	FW_OFFLOAD_H2C_SET_CATEGORY(pHal_h2c_hdr, 0x01);
+	FW_OFFLOAD_H2C_SET_CMD_ID(pHal_h2c_hdr, 0xFF);
+
+	PLATFORM_MUTEX_LOCK(pDriver_adapter, &(pHalmac_adapter->h2c_seq_mutex));
+	FW_OFFLOAD_H2C_SET_SEQ_NUM(pHal_h2c_hdr, pHalmac_adapter->h2c_packet_seq);
+	*pSeq_num = pHalmac_adapter->h2c_packet_seq;
+	pHalmac_adapter->h2c_packet_seq++;
+	PLATFORM_MUTEX_UNLOCK(pDriver_adapter, &(pHalmac_adapter->h2c_seq_mutex));
+
+	if (_TRUE == pH2c_header_info->ack)
+		FW_OFFLOAD_H2C_SET_ACK(pHal_h2c_hdr, _TRUE);
+
+	return HALMAC_RET_SUCCESS;
+}
+
+HALMAC_RET_STATUS
+halmac_send_h2c_set_pwr_mode_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN PHALMAC_FWLPS_OPTION pHal_FwLps_Opt
+)
+{
+	u8 h2c_buff[HALMAC_H2C_CMD_SIZE_88XX];
+	u8 *pH2c_header, *pH2c_cmd;
+	u16 seq = 0;
+	VOID *pDriver_adapter = NULL;
+	HALMAC_RET_STATUS status = HALMAC_RET_SUCCESS;
+
+	PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_send_h2c_set_pwr_mode_88xx!!\n");
+
+	pDriver_adapter = pHalmac_adapter->pDriver_adapter;
+	pH2c_header = h2c_buff;
+	pH2c_cmd = pH2c_header + HALMAC_H2C_CMD_HDR_SIZE_88XX;
+
+	PLATFORM_RTL_MEMSET(pDriver_adapter, h2c_buff, 0x00, HALMAC_H2C_CMD_SIZE_88XX);
+
+	SET_PWR_MODE_SET_CMD_ID(pH2c_cmd, CMD_ID_SET_PWR_MODE);
+	SET_PWR_MODE_SET_CLASS(pH2c_cmd, CLASS_SET_PWR_MODE);
+	SET_PWR_MODE_SET_MODE(pH2c_cmd, pHal_FwLps_Opt->mode);
+	SET_PWR_MODE_SET_CLK_REQUEST(pH2c_cmd, pHal_FwLps_Opt->clk_request);
+	SET_PWR_MODE_SET_RLBM(pH2c_cmd, pHal_FwLps_Opt->rlbm);
+	SET_PWR_MODE_SET_SMART_PS(pH2c_cmd, pHal_FwLps_Opt->smart_ps);
+	SET_PWR_MODE_SET_AWAKE_INTERVAL(pH2c_cmd, pHal_FwLps_Opt->awake_interval);
+	SET_PWR_MODE_SET_B_ALL_QUEUE_UAPSD(pH2c_cmd, pHal_FwLps_Opt->all_queue_uapsd);
+	SET_PWR_MODE_SET_PWR_STATE(pH2c_cmd, pHal_FwLps_Opt->pwr_state);
+	SET_PWR_MODE_SET_ANT_AUTO_SWITCH(pH2c_cmd, pHal_FwLps_Opt->ant_auto_switch);
+	SET_PWR_MODE_SET_PS_ALLOW_BT_HIGH_PRIORITY(pH2c_cmd, pHal_FwLps_Opt->ps_allow_bt_high_Priority);
+	SET_PWR_MODE_SET_PROTECT_BCN(pH2c_cmd, pHal_FwLps_Opt->protect_bcn);
+	SET_PWR_MODE_SET_SILENCE_PERIOD(pH2c_cmd, pHal_FwLps_Opt->silence_period);
+	SET_PWR_MODE_SET_FAST_BT_CONNECT(pH2c_cmd, pHal_FwLps_Opt->fast_bt_connect);
+	SET_PWR_MODE_SET_TWO_ANTENNA_EN(pH2c_cmd, pHal_FwLps_Opt->two_antenna_en);
+	SET_PWR_MODE_SET_ADOPT_USER_SETTING(pH2c_cmd, pHal_FwLps_Opt->adopt_user_Setting);
+	SET_PWR_MODE_SET_DRV_BCN_EARLY_SHIFT(pH2c_cmd, pHal_FwLps_Opt->drv_bcn_early_shift);
+
+	halmac_set_h2c_header_88xx(pHalmac_adapter, pH2c_header, &seq, _TRUE);
+
+	status = halmac_send_h2c_pkt_88xx(pHalmac_adapter, h2c_buff, HALMAC_H2C_CMD_SIZE_88XX, _TRUE);
+
+	if (HALMAC_RET_SUCCESS != status) {
+		PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "halmac_send_h2c_set_pwr_mode_88xx Fail = %x!!\n", status);
+		return status;
+	}
+
+	return HALMAC_RET_SUCCESS;
+}
+
+HALMAC_RET_STATUS
+halmac_func_send_original_h2c_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN u8 *original_h2c,
+	IN u16 *seq,
+	IN u8 ack
+)
+{
+	u8 H2c_buff[HALMAC_H2C_CMD_SIZE_88XX] = { 0 };
+	u8 *pH2c_header, *pH2c_cmd;
+	VOID *pDriver_adapter = NULL;
+	PHALMAC_API pHalmac_api;
+	HALMAC_RET_STATUS status = HALMAC_RET_SUCCESS;
+
+	pDriver_adapter = pHalmac_adapter->pDriver_adapter;
+	pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api;
+
+	PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_send_original_h2c ==========>\n");
+
+	pH2c_header = H2c_buff;
+	pH2c_cmd = pH2c_header + HALMAC_H2C_CMD_HDR_SIZE_88XX;
+	PLATFORM_RTL_MEMCPY(pDriver_adapter, pH2c_cmd, original_h2c, 8); /* Original H2C 8 byte */
+
+	halmac_set_h2c_header_88xx(pHalmac_adapter, pH2c_header, seq, ack);
+
+	status = halmac_send_h2c_pkt_88xx(pHalmac_adapter, H2c_buff, HALMAC_H2C_CMD_SIZE_88XX, ack);
+
+	if (HALMAC_RET_SUCCESS != status) {
+		PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "halmac_send_original_h2c Fail = %x!!\n", status);
+		return status;
+	}
+
+	PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_send_original_h2c <==========\n");
+
+	return HALMAC_RET_SUCCESS;
+}
+
+HALMAC_RET_STATUS
+halmac_media_status_rpt_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN u8 op_mode,
+	IN u8 mac_id_ind,
+	IN u8 mac_id,
+	IN u8 mac_id_end
+)
+{
+	u8 H2c_buff[HALMAC_H2C_CMD_SIZE_88XX] = { 0 };
+	u8 *pH2c_header, *pH2c_cmd;
+	u16 seq = 0;
+	VOID *pDriver_adapter = NULL;
+	HALMAC_RET_STATUS status = HALMAC_RET_SUCCESS;
+
+	PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_send_h2c_set_pwr_mode_88xx!!\n");
+
+	pDriver_adapter = pHalmac_adapter->pDriver_adapter;
+	pH2c_header = H2c_buff;
+	pH2c_cmd = pH2c_header + HALMAC_H2C_CMD_HDR_SIZE_88XX;
+
+	PLATFORM_RTL_MEMSET(pDriver_adapter, H2c_buff, 0x00, HALMAC_H2C_CMD_SIZE_88XX);
+
+	MEDIA_STATUS_RPT_SET_CMD_ID(pH2c_cmd, CMD_ID_MEDIA_STATUS_RPT);
+	MEDIA_STATUS_RPT_SET_CLASS(pH2c_cmd, CLASS_MEDIA_STATUS_RPT);
+	MEDIA_STATUS_RPT_SET_OP_MODE(pH2c_cmd, op_mode);
+	MEDIA_STATUS_RPT_SET_MACID_IN(pH2c_cmd, mac_id_ind);
+	MEDIA_STATUS_RPT_SET_MACID(pH2c_cmd, mac_id);
+	MEDIA_STATUS_RPT_SET_MACID_END(pH2c_cmd, mac_id_end);
+
+	halmac_set_h2c_header_88xx(pHalmac_adapter, pH2c_header, &seq, _TRUE);
+
+	status = halmac_send_h2c_pkt_88xx(pHalmac_adapter, H2c_buff, HALMAC_H2C_CMD_SIZE_88XX, _TRUE);
+
+	if (HALMAC_RET_SUCCESS != status) {
+		PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "halmac_media_status_rpt_88xx Fail = %x!!\n", status);
+		return status;
+	}
+
+	return HALMAC_RET_SUCCESS;
+}
+
+HALMAC_RET_STATUS
+halmac_send_h2c_update_packet_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN HALMAC_PACKET_ID	pkt_id,
+	IN u8 *pkt,
+	IN u32 pkt_size
+)
+{
+	u8 pH2c_buff[HALMAC_H2C_CMD_SIZE_88XX] = { 0 };
+	u16 h2c_seq_mum = 0;
+	VOID *pDriver_adapter = NULL;
+	PHALMAC_API pHalmac_api;
+	HALMAC_H2C_HEADER_INFO h2c_header_info;
+	HALMAC_RET_STATUS ret_status = HALMAC_RET_SUCCESS;
+
+	pDriver_adapter = pHalmac_adapter->pDriver_adapter;
+	pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api;
+
+	HALMAC_REG_WRITE_16(pHalmac_adapter, REG_FIFOPAGE_CTRL_2, (u16)(pHalmac_adapter->txff_allocation.rsvd_h2c_extra_info_pg_bndy & BIT_MASK_BCN_HEAD_1_V1));
+
+	ret_status = halmac_download_rsvd_page_88xx(pHalmac_adapter, pkt, pkt_size);
+
+	if (HALMAC_RET_SUCCESS != ret_status) {
+		PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "halmac_download_rsvd_page_88xx Fail = %x!!\n", ret_status);
+		HALMAC_REG_WRITE_16(pHalmac_adapter, REG_FIFOPAGE_CTRL_2, (u16)(pHalmac_adapter->txff_allocation.rsvd_pg_bndy & BIT_MASK_BCN_HEAD_1_V1));
+		return ret_status;
+	}
+
+	HALMAC_REG_WRITE_16(pHalmac_adapter, REG_FIFOPAGE_CTRL_2, (u16)(pHalmac_adapter->txff_allocation.rsvd_pg_bndy & BIT_MASK_BCN_HEAD_1_V1));
+
+	UPDATE_PACKET_SET_SIZE(pH2c_buff, pkt_size + pHalmac_adapter->hw_config_info.txdesc_size);
+	UPDATE_PACKET_SET_PACKET_ID(pH2c_buff, pkt_id);
+	UPDATE_PACKET_SET_PACKET_LOC(pH2c_buff, pHalmac_adapter->txff_allocation.rsvd_h2c_extra_info_pg_bndy - pHalmac_adapter->txff_allocation.rsvd_pg_bndy);
+
+	h2c_header_info.sub_cmd_id = SUB_CMD_ID_UPDATE_PACKET;
+	h2c_header_info.content_size = 8;
+	h2c_header_info.ack = _TRUE;
+	halmac_set_fw_offload_h2c_header_88xx(pHalmac_adapter, pH2c_buff, &h2c_header_info, &h2c_seq_mum);
+	pHalmac_adapter->halmac_state.update_packet_set.seq_num = h2c_seq_mum;
+
+	ret_status = halmac_send_h2c_pkt_88xx(pHalmac_adapter, pH2c_buff, HALMAC_H2C_CMD_SIZE_88XX, _TRUE);
+
+	if (HALMAC_RET_SUCCESS != ret_status) {
+		PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "halmac_send_h2c_update_packet_88xx Fail = %x!!\n", ret_status);
+		return ret_status;
+	}
+
+	return ret_status;
+}
+
+HALMAC_RET_STATUS
+halmac_send_h2c_phy_parameter_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN PHALMAC_PHY_PARAMETER_INFO para_info,
+	IN u8 full_fifo
+)
+{
+	u8 drv_trigger_send = _FALSE;
+	u8 pH2c_buff[HALMAC_H2C_CMD_SIZE_88XX] = { 0 };
+	u16 h2c_seq_mum = 0;
+	u32 info_size = 0;
+	VOID *pDriver_adapter = NULL;
+	PHALMAC_API pHalmac_api;
+	HALMAC_H2C_HEADER_INFO h2c_header_info;
+	HALMAC_RET_STATUS status = HALMAC_RET_SUCCESS;
+	PHALMAC_CONFIG_PARA_INFO pConfig_para_info;
+
+	pDriver_adapter = pHalmac_adapter->pDriver_adapter;
+	pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api;
+	pConfig_para_info = &(pHalmac_adapter->config_para_info);
+
+	/* PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_send_h2c_phy_parameter_88xx!!\n"); */
+
+	if (NULL == pConfig_para_info->pCfg_para_buf) {
+		if (_TRUE == full_fifo)
+			pConfig_para_info->para_buf_size = HALMAC_EXTRA_INFO_BUFF_SIZE_FULL_FIFO_88XX;
+		else
+			pConfig_para_info->para_buf_size = HALMAC_EXTRA_INFO_BUFF_SIZE_88XX;
+
+		pConfig_para_info->pCfg_para_buf = (u8 *)PLATFORM_RTL_MALLOC(pDriver_adapter, pConfig_para_info->para_buf_size);
+
+		if (NULL != pConfig_para_info->pCfg_para_buf) {
+			PLATFORM_RTL_MEMSET(pDriver_adapter, pConfig_para_info->pCfg_para_buf, 0x00, pConfig_para_info->para_buf_size);
+			pConfig_para_info->full_fifo_mode = full_fifo;
+			pConfig_para_info->pPara_buf_w = pConfig_para_info->pCfg_para_buf;
+			pConfig_para_info->para_num = 0;
+			pConfig_para_info->avai_para_buf_size = pConfig_para_info->para_buf_size;
+			pConfig_para_info->value_accumulation = 0;
+			pConfig_para_info->offset_accumulation = 0;
+		} else {
+			PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "Allocate pCfg_para_buf fail!!\n");
+			return HALMAC_RET_MALLOC_FAIL;
+		}
+	}
+
+	if (HALMAC_RET_SUCCESS != halmac_transition_cfg_para_state_88xx(pHalmac_adapter, HALMAC_CFG_PARA_CMD_CONSTRUCT_CONSTRUCTING))
+		return HALMAC_RET_ERROR_STATE;
+
+	halmac_enqueue_para_buff_88xx(pHalmac_adapter, para_info, pConfig_para_info->pPara_buf_w, &drv_trigger_send);
+
+	if (HALMAC_PARAMETER_CMD_END != para_info->cmd_id) {
+		pConfig_para_info->para_num++;
+		pConfig_para_info->pPara_buf_w += HALMAC_FW_OFFLOAD_CMD_SIZE_88XX;
+		pConfig_para_info->avai_para_buf_size = pConfig_para_info->avai_para_buf_size - HALMAC_FW_OFFLOAD_CMD_SIZE_88XX;
+	}
+
+	if (((pConfig_para_info->avai_para_buf_size - pHalmac_adapter->hw_config_info.txdesc_size) > HALMAC_FW_OFFLOAD_CMD_SIZE_88XX) &&
+	    (_FALSE == drv_trigger_send)) {
+		return HALMAC_RET_SUCCESS;
+	} else {
+		if (0 == pConfig_para_info->para_num) {
+			PLATFORM_RTL_FREE(pDriver_adapter, pConfig_para_info->pCfg_para_buf, pConfig_para_info->para_buf_size);
+			pConfig_para_info->pCfg_para_buf = NULL;
+			pConfig_para_info->pPara_buf_w = NULL;
+			PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_WARN, "no cfg parameter element!!\n");
+
+			if (HALMAC_RET_SUCCESS != halmac_transition_cfg_para_state_88xx(pHalmac_adapter, HALMAC_CFG_PARA_CMD_CONSTRUCT_IDLE))
+				return HALMAC_RET_ERROR_STATE;
+
+			return HALMAC_RET_SUCCESS;
+		}
+
+		if (HALMAC_RET_SUCCESS != halmac_transition_cfg_para_state_88xx(pHalmac_adapter, HALMAC_CFG_PARA_CMD_CONSTRUCT_H2C_SENT))
+			return HALMAC_RET_ERROR_STATE;
+
+		pHalmac_adapter->halmac_state.cfg_para_state_set.process_status = HALMAC_CMD_PROCESS_SENDING;
+
+		if (_TRUE == pConfig_para_info->full_fifo_mode)
+			HALMAC_REG_WRITE_16(pHalmac_adapter, REG_FIFOPAGE_CTRL_2, 0);
+		else
+			HALMAC_REG_WRITE_16(pHalmac_adapter, REG_FIFOPAGE_CTRL_2, (u16)(pHalmac_adapter->txff_allocation.rsvd_h2c_extra_info_pg_bndy & BIT_MASK_BCN_HEAD_1_V1));
+
+		info_size = pConfig_para_info->para_num * HALMAC_FW_OFFLOAD_CMD_SIZE_88XX;
+
+		status = halmac_download_rsvd_page_88xx(pHalmac_adapter, (u8 *)pConfig_para_info->pCfg_para_buf, info_size);
+
+		if (HALMAC_RET_SUCCESS != status) {
+			PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "halmac_download_rsvd_page_88xx Fail!!\n");
+		} else {
+			halmac_gen_cfg_para_h2c_88xx(pHalmac_adapter, pH2c_buff);
+
+			h2c_header_info.sub_cmd_id = SUB_CMD_ID_CFG_PARAMETER;
+			h2c_header_info.content_size = 4;
+			h2c_header_info.ack = _TRUE;
+			halmac_set_fw_offload_h2c_header_88xx(pHalmac_adapter, pH2c_buff, &h2c_header_info, &h2c_seq_mum);
+
+			pHalmac_adapter->halmac_state.cfg_para_state_set.seq_num = h2c_seq_mum;
+
+			status = halmac_send_h2c_pkt_88xx(pHalmac_adapter, pH2c_buff, HALMAC_H2C_CMD_SIZE_88XX, _TRUE);
+
+			if (HALMAC_RET_SUCCESS != status)
+				PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "halmac_send_h2c_pkt_88xx Fail!!\n");
+
+			PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "config parameter time = %d\n", HALMAC_REG_READ_32(pHalmac_adapter, REG_FW_DBG6));
+		}
+
+		PLATFORM_RTL_FREE(pDriver_adapter, pConfig_para_info->pCfg_para_buf, pConfig_para_info->para_buf_size);
+		pConfig_para_info->pCfg_para_buf = NULL;
+		pConfig_para_info->pPara_buf_w = NULL;
+
+		/* Restore bcn head */
+		HALMAC_REG_WRITE_16(pHalmac_adapter, REG_FIFOPAGE_CTRL_2, (u16)(pHalmac_adapter->txff_allocation.rsvd_pg_bndy & BIT_MASK_BCN_HEAD_1_V1));
+
+		if (HALMAC_RET_SUCCESS != halmac_transition_cfg_para_state_88xx(pHalmac_adapter, HALMAC_CFG_PARA_CMD_CONSTRUCT_IDLE))
+			return HALMAC_RET_ERROR_STATE;
+	}
+
+	if (_FALSE == drv_trigger_send) {
+		PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "Buffer full trigger sending H2C!!\n");
+		return HALMAC_RET_PARA_SENDING;
+	}
+
+	return status;
+}
+
+HALMAC_RET_STATUS
+halmac_enqueue_para_buff_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN PHALMAC_PHY_PARAMETER_INFO para_info,
+	IN u8 *pCurr_buff_wptr,
+	OUT u8 *pEnd_cmd
+)
+{
+	VOID *pDriver_adapter = NULL;
+	PHALMAC_CONFIG_PARA_INFO pConfig_para_info = &(pHalmac_adapter->config_para_info);
+
+	*pEnd_cmd = _FALSE;
+
+	PHY_PARAMETER_INFO_SET_LENGTH(pCurr_buff_wptr, HALMAC_FW_OFFLOAD_CMD_SIZE_88XX);
+	PHY_PARAMETER_INFO_SET_IO_CMD(pCurr_buff_wptr, para_info->cmd_id);
+
+	switch (para_info->cmd_id) {
+	case HALMAC_PARAMETER_CMD_BB_W8:
+	case HALMAC_PARAMETER_CMD_BB_W16:
+	case HALMAC_PARAMETER_CMD_BB_W32:
+	case HALMAC_PARAMETER_CMD_MAC_W8:
+	case HALMAC_PARAMETER_CMD_MAC_W16:
+	case HALMAC_PARAMETER_CMD_MAC_W32:
+		PHY_PARAMETER_INFO_SET_IO_ADDR(pCurr_buff_wptr, para_info->content.MAC_REG_W.offset);
+		PHY_PARAMETER_INFO_SET_DATA(pCurr_buff_wptr, para_info->content.MAC_REG_W.value);
+		PHY_PARAMETER_INFO_SET_MASK(pCurr_buff_wptr, para_info->content.MAC_REG_W.msk);
+		PHY_PARAMETER_INFO_SET_MSK_EN(pCurr_buff_wptr, para_info->content.MAC_REG_W.msk_en);
+		pConfig_para_info->value_accumulation += para_info->content.MAC_REG_W.value;
+		pConfig_para_info->offset_accumulation += para_info->content.MAC_REG_W.offset;
+		break;
+	case HALMAC_PARAMETER_CMD_RF_W:
+		PHY_PARAMETER_INFO_SET_RF_ADDR(pCurr_buff_wptr, para_info->content.RF_REG_W.offset); /*In rf register, the address is only 1 byte*/
+		PHY_PARAMETER_INFO_SET_RF_PATH(pCurr_buff_wptr, para_info->content.RF_REG_W.rf_path);
+		PHY_PARAMETER_INFO_SET_DATA(pCurr_buff_wptr, para_info->content.RF_REG_W.value);
+		PHY_PARAMETER_INFO_SET_MASK(pCurr_buff_wptr, para_info->content.RF_REG_W.msk);
+		PHY_PARAMETER_INFO_SET_MSK_EN(pCurr_buff_wptr, para_info->content.RF_REG_W.msk_en);
+		pConfig_para_info->value_accumulation += para_info->content.RF_REG_W.value;
+		pConfig_para_info->offset_accumulation += (para_info->content.RF_REG_W.offset + (para_info->content.RF_REG_W.rf_path << 8));
+		break;
+	case HALMAC_PARAMETER_CMD_DELAY_US:
+	case HALMAC_PARAMETER_CMD_DELAY_MS:
+		PHY_PARAMETER_INFO_SET_DELAY_VALUE(pCurr_buff_wptr, para_info->content.DELAY_TIME.delay_time);
+		break;
+	case HALMAC_PARAMETER_CMD_END:
+		*pEnd_cmd = _TRUE;
+		break;
+	default:
+		PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, " halmac_send_h2c_phy_parameter_88xx illegal cmd_id!!\n");
+		break;
+	}
+
+	return HALMAC_RET_SUCCESS;
+}
+
+HALMAC_RET_STATUS
+halmac_gen_cfg_para_h2c_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN u8 *pH2c_buff
+)
+{
+	VOID *pDriver_adapter = NULL;
+	PHALMAC_CONFIG_PARA_INFO pConfig_para_info = &(pHalmac_adapter->config_para_info);
+
+	CFG_PARAMETER_SET_NUM(pH2c_buff, pConfig_para_info->para_num);
+
+	if (_TRUE == pConfig_para_info->full_fifo_mode) {
+		CFG_PARAMETER_SET_INIT_CASE(pH2c_buff, 0x1);
+		CFG_PARAMETER_SET_PHY_PARAMETER_LOC(pH2c_buff, 0);
+	} else {
+		CFG_PARAMETER_SET_INIT_CASE(pH2c_buff, 0x0);
+		CFG_PARAMETER_SET_PHY_PARAMETER_LOC(pH2c_buff, pHalmac_adapter->txff_allocation.rsvd_h2c_extra_info_pg_bndy - pHalmac_adapter->txff_allocation.rsvd_pg_bndy);
+	}
+
+	return HALMAC_RET_SUCCESS;
+}
+#if 0
+HALMAC_RET_STATUS
+halmac_send_h2c_update_datapack_88xx(
+	IN PHALMAC_ADAPTER		pHalmac_adapter,
+	IN HALMAC_DATA_TYPE		halmac_data_type,
+	IN PHALMAC_PHY_PARAMETER_INFO	para_info
+)
+{
+	u8 drv_trigger_send = _FALSE;
+	u8 pH2c_buff[HALMAC_H2C_CMD_SIZE_88XX] = { 0 };
+	u8 *pCurr_buf_w;
+	u16 h2c_seq_mum = 0;
+	u32 info_size = 0;
+	VOID *pDriver_adapter = NULL;
+	PHALMAC_API pHalmac_api;
+	PHALMAC_CONFIG_PARA_INFO pConfig_para_info;
+	HALMAC_H2C_HEADER_INFO h2c_header_info;
+	HALMAC_RET_STATUS status = HALMAC_RET_SUCCESS;
+
+	pDriver_adapter = pHalmac_adapter->pDriver_adapter;
+	pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api;
+	pConfig_para_info = &(pHalmac_adapter->config_para_info);
+
+	PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_send_h2c_phy_parameter_88xx!!\n");
+
+	if (NULL == pConfig_para_info->pCfg_para_buf) {/*Buff null, allocate memory according to use mode*/
+		/*else, only 4k reserved page is used*/
+		pConfig_para_info->para_buf_size = HALMAC_EXTRA_INFO_BUFF_SIZE_88XX;
+		/* pConfig_para_info->datapack_segment =0; */
+
+
+		pConfig_para_info->pCfg_para_buf = (u8 *)PLATFORM_RTL_MALLOC(pDriver_adapter, pConfig_para_info->para_buf_size);
+		if (NULL != pConfig_para_info->pCfg_para_buf) {
+			/*Reset buffer parameter*/
+			PLATFORM_RTL_MEMSET(pDriver_adapter, pConfig_para_info->pCfg_para_buf, 0x00, pConfig_para_info->para_buf_size);
+			/* pConfig_para_info->full_fifo_mode = full_fifo; */
+			pConfig_para_info->data_type = halmac_data_type;
+			pConfig_para_info->pPara_buf_w = pConfig_para_info->pCfg_para_buf;
+			pConfig_para_info->para_num = 0;
+			pConfig_para_info->avai_para_buf_size = pConfig_para_info->para_buf_size;
+		} else {
+			PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "Allocate pCfg_para_buf fail!!\n");
+			return HALMAC_RET_MALLOC_FAIL;
+		}
+	}
+
+	pCurr_buf_w = pConfig_para_info->pPara_buf_w;
+
+	/*Start fill buffer content*/
+	PHY_PARAMETER_INFO_SET_LENGTH(pCurr_buf_w, HALMAC_FW_OFFLOAD_CMD_SIZE_88XX);/* Each element is 12 Byte */
+	PHY_PARAMETER_INFO_SET_IO_CMD(pCurr_buf_w, para_info->cmd_id);
+
+	switch (para_info->cmd_id) {
+	case HALMAC_PARAMETER_CMD_BB_W8:
+	case HALMAC_PARAMETER_CMD_BB_W16:
+	case HALMAC_PARAMETER_CMD_BB_W32:
+	case HALMAC_PARAMETER_CMD_MAC_W8:
+	case HALMAC_PARAMETER_CMD_MAC_W16:
+	case HALMAC_PARAMETER_CMD_MAC_W32:
+		PHY_PARAMETER_INFO_SET_IO_ADDR(pCurr_buf_w, para_info->content.MAC_REG_W.offset);
+		PHY_PARAMETER_INFO_SET_DATA(pCurr_buf_w, para_info->content.MAC_REG_W.value);
+		PHY_PARAMETER_INFO_SET_MASK(pCurr_buf_w, para_info->content.MAC_REG_W.msk);
+		PHY_PARAMETER_INFO_SET_MSK_EN(pCurr_buf_w, para_info->content.MAC_REG_W.msk_en);
+		break;
+	case HALMAC_PARAMETER_CMD_RF_W:
+		PHY_PARAMETER_INFO_SET_RF_ADDR(pCurr_buf_w, para_info->content.RF_REG_W.offset);        /* In rf register, the address is only 1 byte */
+		PHY_PARAMETER_INFO_SET_RF_PATH(pCurr_buf_w, para_info->content.RF_REG_W.rf_path);
+		PHY_PARAMETER_INFO_SET_DATA(pCurr_buf_w, para_info->content.RF_REG_W.value);
+		PHY_PARAMETER_INFO_SET_MASK(pCurr_buf_w, para_info->content.RF_REG_W.msk);
+		PHY_PARAMETER_INFO_SET_MSK_EN(pCurr_buf_w, para_info->content.MAC_REG_W.msk_en);
+		break;
+	case HALMAC_PARAMETER_CMD_DELAY_US:
+	case HALMAC_PARAMETER_CMD_DELAY_MS:
+		PHY_PARAMETER_INFO_SET_DELAY_VALUE(pCurr_buf_w, para_info->content.DELAY_TIME.delay_time);
+		break;
+
+	case HALMAC_PARAMETER_CMD_END:
+		/* PHY_PARAMETER_INFO_SET_MSK_EN(pHalmac_adapter->pPara_buf_w, 1); */
+		drv_trigger_send = _TRUE;
+		break;
+	default:
+		PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "illegal cmd_id!!\n");
+		/* return _FALSE; */
+		break;
+	}
+
+	/*Update parameter buffer variable*/
+	if (HALMAC_PARAMETER_CMD_END != para_info->cmd_id) {
+		pConfig_para_info->para_num++;
+		pConfig_para_info->pPara_buf_w += HALMAC_FW_OFFLOAD_CMD_SIZE_88XX;
+		pConfig_para_info->avai_para_buf_size = pConfig_para_info->avai_para_buf_size - HALMAC_FW_OFFLOAD_CMD_SIZE_88XX;
+	}
+
+	if (((pConfig_para_info->avai_para_buf_size - pHalmac_adapter->hw_config_info.txdesc_size) > HALMAC_FW_OFFLOAD_CMD_SIZE_88XX) && (_FALSE == drv_trigger_send)) {
+		/*There are still space for parameter cmd, and driver does not trigger it to send, so keep it in buffer temporarily*/
+		return HALMAC_RET_SUCCESS_ENQUEUE;
+	} else {
+		/*There is no space or driver trigger it to send*/
+
+		/*Update the bcn head(dma)*/
+		HALMAC_REG_WRITE_16(pHalmac_adapter, REG_FIFOPAGE_CTRL_2, (u16)(pHalmac_adapter->h2c_extra_info_boundary & BIT_MASK_BCN_HEAD_1_V1));
+
+		/* Download to reserved page */
+		info_size = pConfig_para_info->para_num * HALMAC_FW_OFFLOAD_CMD_SIZE_88XX;
+		status = halmac_download_rsvd_page_88xx(pHalmac_adapter, (u8 *)pConfig_para_info->pCfg_para_buf, info_size);
+		if (HALMAC_RET_SUCCESS != status) {
+			PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "halmac_download_rsvd_page_88xx Fail!!\n");
+		} else {/*download rsvd page ok, send h2c packet to fw*/
+			/* Construct H2C Content */
+			UPDATE_DATAPACK_SET_SIZE(pH2c_buff, pConfig_para_info->para_num * HALMAC_FW_OFFLOAD_CMD_SIZE_88XX);
+			UPDATE_DATAPACK_SET_DATAPACK_ID(pH2c_buff, pConfig_para_info->data_type);
+			UPDATE_DATAPACK_SET_DATAPACK_LOC(pH2c_buff, pHalmac_adapter->h2c_extra_info_boundary - pHalmac_adapter->Tx_boundary);
+			UPDATE_DATAPACK_SET_DATAPACK_SEGMENT(pH2c_buff, pConfig_para_info->datapack_segment);
+			UPDATE_DATAPACK_SET_END_SEGMENT(pH2c_buff, drv_trigger_send);
+
+			/* Fill in H2C Header */
+			h2c_header_info.sub_cmd_id = SUB_CMD_ID_UPDATE_DATAPACK;
+			h2c_header_info.content_size = 8;
+			h2c_header_info.ack = _TRUE;
+			halmac_set_fw_offload_h2c_header_88xx(pHalmac_adapter, pH2c_buff, &h2c_header_info, &h2c_seq_mum);
+
+			/* Send H2C Cmd Packet */
+			status = halmac_send_h2c_pkt_88xx(pHalmac_adapter, pH2c_buff, HALMAC_H2C_CMD_SIZE_88XX, _TRUE);
+			if (HALMAC_RET_SUCCESS != status)
+				PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "halmac_send_h2c_pkt_88xx Fail!!\n");
+		}
+
+		PLATFORM_RTL_FREE(pDriver_adapter, pConfig_para_info->pCfg_para_buf, pConfig_para_info->para_buf_size);
+		if (_TRUE == drv_trigger_send)
+			pConfig_para_info->datapack_segment = 0;
+		else
+			pConfig_para_info->datapack_segment++;
+
+		pConfig_para_info->pCfg_para_buf = NULL;
+		pConfig_para_info->pPara_buf_w = NULL;
+		pConfig_para_info->para_num = 0;
+		pConfig_para_info->avai_para_buf_size = 0;
+
+		/*Restore Register after FW handle the H2C packet*/
+
+		/*only set bcn head back*/
+		HALMAC_REG_WRITE_16(pHalmac_adapter, REG_FIFOPAGE_CTRL_2, (u16)(pHalmac_adapter->Tx_boundary & BIT_MASK_BCN_HEAD_1_V1));
+	}
+
+	return status;
+}
+#endif
+HALMAC_RET_STATUS
+halmac_send_h2c_run_datapack_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN HALMAC_DATA_TYPE halmac_data_type
+)
+{
+	u8 pH2c_buff[HALMAC_H2C_CMD_SIZE_88XX] = { 0 };
+	u16 h2c_seq_mum = 0;
+	VOID *pDriver_adapter = NULL;
+	HALMAC_H2C_HEADER_INFO h2c_header_info;
+	HALMAC_RET_STATUS status = HALMAC_RET_SUCCESS;
+
+	pDriver_adapter = pHalmac_adapter->pDriver_adapter;
+
+	PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_send_h2c_run_datapack_88xx!!\n");
+
+	RUN_DATAPACK_SET_DATAPACK_ID(pH2c_buff, halmac_data_type);
+
+	h2c_header_info.sub_cmd_id = SUB_CMD_ID_RUN_DATAPACK;
+	h2c_header_info.content_size = 4;
+	h2c_header_info.ack = _TRUE;
+	halmac_set_fw_offload_h2c_header_88xx(pHalmac_adapter, pH2c_buff, &h2c_header_info, &h2c_seq_mum);
+
+	status = halmac_send_h2c_pkt_88xx(pHalmac_adapter, pH2c_buff, HALMAC_H2C_CMD_SIZE_88XX, _TRUE);
+
+	if (HALMAC_RET_SUCCESS != status) {
+		PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "halmac_send_h2c_pkt_88xx Fail = %x!!\n", status);
+		return status;
+	}
+
+	return HALMAC_RET_SUCCESS;
+}
+
+HALMAC_RET_STATUS
+halmac_send_bt_coex_cmd_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN u8 *pBt_buf,
+	IN u32 bt_size,
+	IN u8 ack
+)
+{
+	u8 pH2c_buff[HALMAC_H2C_CMD_SIZE_88XX] = { 0 };
+	u16 h2c_seq_mum = 0;
+	VOID *pDriver_adapter = NULL;
+	HALMAC_H2C_HEADER_INFO h2c_header_info;
+	HALMAC_RET_STATUS status = HALMAC_RET_SUCCESS;
+
+	pDriver_adapter = pHalmac_adapter->pDriver_adapter;
+
+	PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_send_bt_coex_cmd_88xx!!\n");
+
+	PLATFORM_RTL_MEMCPY(pDriver_adapter, pH2c_buff + 8, pBt_buf, bt_size);
+
+	h2c_header_info.sub_cmd_id = SUB_CMD_ID_BT_COEX;
+	h2c_header_info.content_size = (u16)bt_size;
+	h2c_header_info.ack = ack;
+	halmac_set_fw_offload_h2c_header_88xx(pHalmac_adapter, pH2c_buff, &h2c_header_info, &h2c_seq_mum);
+
+	status = halmac_send_h2c_pkt_88xx(pHalmac_adapter, pH2c_buff, HALMAC_H2C_CMD_SIZE_88XX, ack);
+
+	if (HALMAC_RET_SUCCESS != status) {
+		PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "halmac_send_h2c_pkt_88xx Fail = %x!!\n", status);
+		return status;
+	}
+
+	return HALMAC_RET_SUCCESS;
+}
+
+
+HALMAC_RET_STATUS
+halmac_func_ctrl_ch_switch_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN PHALMAC_CH_SWITCH_OPTION pCs_option
+)
+{
+	u8 pH2c_buff[HALMAC_H2C_CMD_SIZE_88XX] = { 0 };
+	u16 h2c_seq_mum = 0;
+	VOID *pDriver_adapter = NULL;
+	PHALMAC_API pHalmac_api;
+	HALMAC_H2C_HEADER_INFO h2c_header_info;
+	HALMAC_RET_STATUS status = HALMAC_RET_SUCCESS;
+	HALMAC_CMD_PROCESS_STATUS *pProcess_status = &(pHalmac_adapter->halmac_state.scan_state_set.process_status);
+
+	PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_ctrl_ch_switch!!\n");
+
+	pDriver_adapter = pHalmac_adapter->pDriver_adapter;
+	pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api;
+
+	if (HALMAC_RET_SUCCESS != halmac_transition_scan_state_88xx(pHalmac_adapter, HALMAC_SCAN_CMD_CONSTRUCT_H2C_SENT))
+		return HALMAC_RET_ERROR_STATE;
+
+	*pProcess_status = HALMAC_CMD_PROCESS_SENDING;
+
+	if (0 != pCs_option->switch_en) {
+		HALMAC_REG_WRITE_16(pHalmac_adapter, REG_FIFOPAGE_CTRL_2, (u16)(pHalmac_adapter->txff_allocation.rsvd_h2c_extra_info_pg_bndy & BIT_MASK_BCN_HEAD_1_V1));
+
+		status = halmac_download_rsvd_page_88xx(pHalmac_adapter, pHalmac_adapter->ch_sw_info.ch_info_buf, pHalmac_adapter->ch_sw_info.total_size);
+
+		if (HALMAC_RET_SUCCESS != status) {
+			PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "halmac_download_rsvd_page_88xx Fail = %x!!\n", status);
+			HALMAC_REG_WRITE_16(pHalmac_adapter, REG_FIFOPAGE_CTRL_2, (u16)(pHalmac_adapter->txff_allocation.rsvd_pg_bndy & BIT_MASK_BCN_HEAD_1_V1));
+			return status;
+		}
+
+		HALMAC_REG_WRITE_16(pHalmac_adapter, REG_FIFOPAGE_CTRL_2, (u16)(pHalmac_adapter->txff_allocation.rsvd_pg_bndy & BIT_MASK_BCN_HEAD_1_V1));
+	}
+
+	CHANNEL_SWITCH_SET_SWITCH_START(pH2c_buff, pCs_option->switch_en);
+	CHANNEL_SWITCH_SET_CHANNEL_NUM(pH2c_buff, pHalmac_adapter->ch_sw_info.ch_num);
+	CHANNEL_SWITCH_SET_CHANNEL_INFO_LOC(pH2c_buff, pHalmac_adapter->txff_allocation.rsvd_h2c_extra_info_pg_bndy - pHalmac_adapter->txff_allocation.rsvd_pg_bndy);
+	CHANNEL_SWITCH_SET_DEST_CH_EN(pH2c_buff, pCs_option->dest_ch_en);
+	CHANNEL_SWITCH_SET_DEST_CH(pH2c_buff, pCs_option->dest_ch);
+	CHANNEL_SWITCH_SET_PRI_CH_IDX(pH2c_buff, pCs_option->dest_pri_ch_idx);
+	CHANNEL_SWITCH_SET_ABSOLUTE_TIME(pH2c_buff, pCs_option->absolute_time_en);
+	CHANNEL_SWITCH_SET_TSF_LOW(pH2c_buff, pCs_option->tsf_low);
+	CHANNEL_SWITCH_SET_PERIODIC_OPTION(pH2c_buff, pCs_option->periodic_option);
+	CHANNEL_SWITCH_SET_NORMAL_CYCLE(pH2c_buff, pCs_option->normal_cycle);
+	CHANNEL_SWITCH_SET_NORMAL_PERIOD(pH2c_buff, pCs_option->normal_period);
+	CHANNEL_SWITCH_SET_SLOW_PERIOD(pH2c_buff, pCs_option->phase_2_period);
+	CHANNEL_SWITCH_SET_CHANNEL_INFO_SIZE(pH2c_buff, pHalmac_adapter->ch_sw_info.total_size);
+
+	h2c_header_info.sub_cmd_id = SUB_CMD_ID_CHANNEL_SWITCH;
+	h2c_header_info.content_size = 20;
+	h2c_header_info.ack = _TRUE;
+	halmac_set_fw_offload_h2c_header_88xx(pHalmac_adapter, pH2c_buff, &h2c_header_info, &h2c_seq_mum);
+	pHalmac_adapter->halmac_state.scan_state_set.seq_num = h2c_seq_mum;
+
+	status = halmac_send_h2c_pkt_88xx(pHalmac_adapter, pH2c_buff, HALMAC_H2C_CMD_SIZE_88XX, _TRUE);
+
+	if (HALMAC_RET_SUCCESS != status)
+		PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "halmac_send_h2c_pkt_88xx Fail = %x!!\n", status);
+
+	PLATFORM_RTL_FREE(pDriver_adapter, pHalmac_adapter->ch_sw_info.ch_info_buf, pHalmac_adapter->ch_sw_info.buf_size);
+	pHalmac_adapter->ch_sw_info.ch_info_buf = NULL;
+	pHalmac_adapter->ch_sw_info.ch_info_buf_w = NULL;
+	pHalmac_adapter->ch_sw_info.extra_info_en = 0;
+	pHalmac_adapter->ch_sw_info.buf_size = 0;
+	pHalmac_adapter->ch_sw_info.avai_buf_size = 0;
+	pHalmac_adapter->ch_sw_info.total_size = 0;
+	pHalmac_adapter->ch_sw_info.ch_num = 0;
+
+	if (HALMAC_RET_SUCCESS != halmac_transition_scan_state_88xx(pHalmac_adapter, HALMAC_SCAN_CMD_CONSTRUCT_IDLE))
+		return HALMAC_RET_ERROR_STATE;
+
+	return status;
+}
+
+HALMAC_RET_STATUS
+halmac_func_send_general_info_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN PHALMAC_GENERAL_INFO pGeneral_info
+)
+{
+	u8 pH2c_buff[HALMAC_H2C_CMD_SIZE_88XX] = { 0 };
+	u16 h2c_seq_mum = 0;
+	VOID *pDriver_adapter = NULL;
+	HALMAC_H2C_HEADER_INFO h2c_header_info;
+	HALMAC_RET_STATUS status = HALMAC_RET_SUCCESS;
+
+	pDriver_adapter = pHalmac_adapter->pDriver_adapter;
+
+	PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_send_general_info!!\n");
+
+	GENERAL_INFO_SET_REF_TYPE(pH2c_buff, pGeneral_info->rfe_type);
+	GENERAL_INFO_SET_RF_TYPE(pH2c_buff, pGeneral_info->rf_type);
+	GENERAL_INFO_SET_FW_TX_BOUNDARY(pH2c_buff, pHalmac_adapter->txff_allocation.rsvd_fw_txbuff_pg_bndy - pHalmac_adapter->txff_allocation.rsvd_pg_bndy);
+
+	h2c_header_info.sub_cmd_id = SUB_CMD_ID_GENERAL_INFO;
+	h2c_header_info.content_size = 4;
+	h2c_header_info.ack = _FALSE;
+	halmac_set_fw_offload_h2c_header_88xx(pHalmac_adapter, pH2c_buff, &h2c_header_info, &h2c_seq_mum);
+
+	status = halmac_send_h2c_pkt_88xx(pHalmac_adapter, pH2c_buff, HALMAC_H2C_CMD_SIZE_88XX, _TRUE);
+
+	if (HALMAC_RET_SUCCESS != status)
+		PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "halmac_send_h2c_pkt_88xx Fail = %x!!\n", status);
+
+	return status;
+}
+
+HALMAC_RET_STATUS
+halmac_send_h2c_update_bcn_parse_info_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN PHALMAC_BCN_IE_INFO pBcn_ie_info
+)
+{
+	u8 pH2c_buff[HALMAC_H2C_CMD_SIZE_88XX] = { 0 };
+	u16 h2c_seq_mum = 0;
+	VOID *pDriver_adapter = NULL;
+	HALMAC_H2C_HEADER_INFO h2c_header_info;
+	HALMAC_RET_STATUS status = HALMAC_RET_SUCCESS;
+
+	PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_send_h2c_update_bcn_parse_info_88xx!!\n");
+
+	pDriver_adapter = pHalmac_adapter->pDriver_adapter;
+
+	UPDATE_BEACON_PARSING_INFO_SET_FUNC_EN(pH2c_buff, pBcn_ie_info->func_en);
+	UPDATE_BEACON_PARSING_INFO_SET_SIZE_TH(pH2c_buff, pBcn_ie_info->size_th);
+	UPDATE_BEACON_PARSING_INFO_SET_TIMEOUT(pH2c_buff, pBcn_ie_info->timeout);
+
+	UPDATE_BEACON_PARSING_INFO_SET_IE_ID_BMP_0(pH2c_buff, (u32)(pBcn_ie_info->ie_bmp[0]));
+	UPDATE_BEACON_PARSING_INFO_SET_IE_ID_BMP_1(pH2c_buff, (u32)(pBcn_ie_info->ie_bmp[1]));
+	UPDATE_BEACON_PARSING_INFO_SET_IE_ID_BMP_2(pH2c_buff, (u32)(pBcn_ie_info->ie_bmp[2]));
+	UPDATE_BEACON_PARSING_INFO_SET_IE_ID_BMP_3(pH2c_buff, (u32)(pBcn_ie_info->ie_bmp[3]));
+	UPDATE_BEACON_PARSING_INFO_SET_IE_ID_BMP_4(pH2c_buff, (u32)(pBcn_ie_info->ie_bmp[4]));
+
+	h2c_header_info.sub_cmd_id = SUB_CMD_ID_UPDATE_BEACON_PARSING_INFO;
+	h2c_header_info.content_size = 24;
+	h2c_header_info.ack = _TRUE;
+	halmac_set_fw_offload_h2c_header_88xx(pHalmac_adapter, pH2c_buff, &h2c_header_info, &h2c_seq_mum);
+
+	status = halmac_send_h2c_pkt_88xx(pHalmac_adapter, pH2c_buff, HALMAC_H2C_CMD_SIZE_88XX, _TRUE);
+
+	if (HALMAC_RET_SUCCESS != status) {
+		PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "halmac_send_h2c_pkt_88xx Fail =%x !!\n", status);
+		return status;
+	}
+
+	return status;
+}
+
+HALMAC_RET_STATUS
+halmac_send_h2c_ps_tuning_para_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter
+)
+{
+	u8 pH2c_buff[HALMAC_H2C_CMD_SIZE_88XX] = { 0 };
+	u8 *pH2c_header, *pH2c_cmd;
+	u16 seq = 0;
+	VOID *pDriver_adapter = NULL;
+	HALMAC_RET_STATUS status = HALMAC_RET_SUCCESS;
+
+	pDriver_adapter = pHalmac_adapter->pDriver_adapter;
+
+	PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_send_h2c_ps_tuning_para_88xx!!\n");
+
+	pH2c_header = pH2c_buff;
+	pH2c_cmd = pH2c_header + HALMAC_H2C_CMD_HDR_SIZE_88XX;
+
+	halmac_set_h2c_header_88xx(pHalmac_adapter, pH2c_header, &seq, _FALSE);
+
+	status = halmac_send_h2c_pkt_88xx(pHalmac_adapter, pH2c_buff, HALMAC_H2C_CMD_SIZE_88XX, _FALSE);
+
+	if (HALMAC_RET_SUCCESS != status) {
+		PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "halmac_send_h2c_pkt_88xx Fail = %x!!\n", status);
+		return status;
+	}
+
+	return status;
+}
+
+HALMAC_RET_STATUS
+halmac_parse_c2h_packet_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN u8 *halmac_buf,
+	IN u32 halmac_size
+)
+{
+	u8 c2h_cmd, c2h_sub_cmd_id;
+	u8 *pC2h_buf = halmac_buf + pHalmac_adapter->hw_config_info.rxdesc_size;
+	u32 c2h_size = halmac_size - pHalmac_adapter->hw_config_info.rxdesc_size;
+	VOID *pDriver_adapter = pHalmac_adapter->pDriver_adapter;
+	HALMAC_RET_STATUS status = HALMAC_RET_SUCCESS;
+
+	/* PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_parse_c2h_packet_88xx!!\n"); */
+
+	c2h_cmd = (u8)C2H_HDR_GET_CMD_ID(pC2h_buf);
+
+	/* FW offload C2H cmd is 0xFF */
+	if (0xFF != c2h_cmd) {
+		PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "C2H_PKT not for FwOffloadC2HFormat!!\n");
+		return HALMAC_RET_C2H_NOT_HANDLED;
+	}
+
+	/* Get C2H sub cmd ID */
+	c2h_sub_cmd_id = (u8)C2H_HDR_GET_C2H_SUB_CMD_ID(pC2h_buf);
+
+	switch (c2h_sub_cmd_id) {
+	case C2H_SUB_CMD_ID_C2H_DBG:
+		status = halmac_parse_c2h_debug_88xx(pHalmac_adapter, pC2h_buf, c2h_size);
+		break;
+	case C2H_SUB_CMD_ID_H2C_ACK_HDR:
+		status = halmac_parse_h2c_ack_88xx(pHalmac_adapter, pC2h_buf, c2h_size);
+		break;
+	case C2H_SUB_CMD_ID_BT_COEX_INFO:
+		status = HALMAC_RET_C2H_NOT_HANDLED;
+		break;
+	case C2H_SUB_CMD_ID_SCAN_STATUS_RPT:
+		status = halmac_parse_scan_status_rpt_88xx(pHalmac_adapter, pC2h_buf, c2h_size);
+		break;
+	case C2H_SUB_CMD_ID_PSD_DATA:
+		status = halmac_parse_psd_data_88xx(pHalmac_adapter, pC2h_buf, c2h_size);
+		break;
+
+	case C2H_SUB_CMD_ID_EFUSE_DATA:
+		status = halmac_parse_efuse_data_88xx(pHalmac_adapter, pC2h_buf, c2h_size);
+		break;
+	default:
+		PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_WARN, "c2h_sub_cmd_id switch case out of boundary!!\n");
+		PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_WARN, "[ERR]c2h pkt : %.8X %.8X!!\n", *(u32 *)pC2h_buf, *(u32 *)(pC2h_buf + 4));
+		status = HALMAC_RET_C2H_NOT_HANDLED;
+		break;
+	}
+
+	return status;
+}
+
+HALMAC_RET_STATUS
+halmac_parse_c2h_debug_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN u8 *pC2h_buf,
+	IN u32 c2h_size
+)
+{
+	VOID *pDriver_adapter = NULL;
+	u8 *pC2h_buf_local = (u8 *)NULL;
+	u32 c2h_size_local = 0;
+	u8 dbg_content_length = 0;
+	u8 dbg_seq_num = 0;
+
+	pDriver_adapter = pHalmac_adapter->pDriver_adapter;
+	pC2h_buf_local = pC2h_buf;
+	c2h_size_local = c2h_size;
+
+	dbg_content_length = (u8)C2H_HDR_GET_LEN((u8 *)pC2h_buf_local);
+
+	if (dbg_content_length > C2H_DBG_CONTENT_MAX_LENGTH) {
+		return HALMAC_RET_SUCCESS;
+	} else {
+		*(pC2h_buf_local + C2H_DBG_HEADER_LENGTH + dbg_content_length - 2) = '\n';
+		dbg_seq_num = (u8)(*(pC2h_buf_local + C2H_DBG_HEADER_LENGTH));
+		PLATFORM_MSG_PRINT(pDriver_adapter,  HALMAC_MSG_H2C,  HALMAC_DBG_TRACE,  "[RTKFW, SEQ=%d]: %s",  dbg_seq_num,  (char *)(pC2h_buf_local + C2H_DBG_HEADER_LENGTH + 1));
+	}
+
+	return HALMAC_RET_SUCCESS;
+}
+
+
+HALMAC_RET_STATUS
+halmac_parse_scan_status_rpt_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN u8 *pC2h_buf,
+	IN u32 c2h_size
+)
+{
+	u8 h2c_return_code;
+	VOID *pDriver_adapter = pHalmac_adapter->pDriver_adapter;
+	HALMAC_CMD_PROCESS_STATUS process_status;
+
+	h2c_return_code = (u8)SCAN_STATUS_RPT_GET_H2C_RETURN_CODE(pC2h_buf);
+	process_status = (HALMAC_H2C_RETURN_SUCCESS == (HALMAC_H2C_RETURN_CODE)h2c_return_code) ? HALMAC_CMD_PROCESS_DONE : HALMAC_CMD_PROCESS_ERROR;
+
+	PLATFORM_EVENT_INDICATION(pDriver_adapter, HALMAC_FEATURE_CHANNEL_SWITCH, process_status, NULL, 0);
+
+	pHalmac_adapter->halmac_state.scan_state_set.process_status = process_status;
+
+	PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "[TRACE]scan status : %X\n", process_status);
+
+	return HALMAC_RET_SUCCESS;
+}
+
+
+HALMAC_RET_STATUS
+halmac_parse_psd_data_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN u8 *pC2h_buf,
+	IN u32 c2h_size
+)
+{
+	u8 segment_id = 0, segment_size = 0, h2c_seq = 0;
+	u16 total_size;
+	VOID *pDriver_adapter = pHalmac_adapter->pDriver_adapter;
+	HALMAC_CMD_PROCESS_STATUS process_status;
+	PHALMAC_PSD_STATE_SET pPsd_set = &(pHalmac_adapter->halmac_state.psd_set);
+
+	h2c_seq = (u8)PSD_DATA_GET_H2C_SEQ(pC2h_buf);
+	PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "[TRACE]Seq num : h2c -> %d c2h -> %d\n", pPsd_set->seq_num, h2c_seq);
+	if (h2c_seq != pPsd_set->seq_num) {
+		PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "[ERR]Seq num mismactch : h2c -> %d c2h -> %d\n", pPsd_set->seq_num, h2c_seq);
+		return HALMAC_RET_SUCCESS;
+	}
+
+	if (HALMAC_CMD_PROCESS_SENDING != pPsd_set->process_status) {
+		PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "[ERR]Not in HALMAC_CMD_PROCESS_SENDING\n");
+		return HALMAC_RET_SUCCESS;
+	}
+
+	total_size = (u16)PSD_DATA_GET_TOTAL_SIZE(pC2h_buf);
+	segment_id = (u8)PSD_DATA_GET_SEGMENT_ID(pC2h_buf);
+	segment_size = (u8)PSD_DATA_GET_SEGMENT_SIZE(pC2h_buf);
+	pPsd_set->data_size = total_size;
+
+	if (NULL == pPsd_set->pData)
+		pPsd_set->pData = (u8 *)PLATFORM_RTL_MALLOC(pDriver_adapter, pPsd_set->data_size);
+
+	if (0 == segment_id)
+		pPsd_set->segment_size = segment_size;
+
+	PLATFORM_RTL_MEMCPY(pDriver_adapter, pPsd_set->pData + segment_id * pPsd_set->segment_size, pC2h_buf + HALMAC_C2H_DATA_OFFSET_88XX, segment_size);
+
+	if (_FALSE == PSD_DATA_GET_END_SEGMENT(pC2h_buf))
+		return HALMAC_RET_SUCCESS;
+
+	process_status = HALMAC_CMD_PROCESS_DONE;
+	pPsd_set->process_status = process_status;
+
+	PLATFORM_EVENT_INDICATION(pDriver_adapter, HALMAC_FEATURE_PSD, process_status, pPsd_set->pData, pPsd_set->data_size);
+
+	return HALMAC_RET_SUCCESS;
+}
+
+HALMAC_RET_STATUS
+halmac_parse_efuse_data_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN u8 *pC2h_buf,
+	IN u32 c2h_size
+)
+{
+	u8 segment_id = 0, segment_size = 0, h2c_seq = 0;
+	u8 *pEeprom_map = NULL;
+	u32 eeprom_size = pHalmac_adapter->hw_config_info.eeprom_size;
+	u8 h2c_return_code = 0;
+	VOID *pDriver_adapter = pHalmac_adapter->pDriver_adapter;
+	HALMAC_CMD_PROCESS_STATUS process_status;
+
+	h2c_seq = (u8)EFUSE_DATA_GET_H2C_SEQ(pC2h_buf);
+	PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "[TRACE]Seq num : h2c -> %d c2h -> %d\n", pHalmac_adapter->halmac_state.efuse_state_set.seq_num, h2c_seq);
+	if (h2c_seq != pHalmac_adapter->halmac_state.efuse_state_set.seq_num) {
+		PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "[ERR]Seq num mismactch : h2c -> %d c2h -> %d\n", pHalmac_adapter->halmac_state.efuse_state_set.seq_num, h2c_seq);
+		return HALMAC_RET_SUCCESS;
+	}
+
+	if (HALMAC_CMD_PROCESS_SENDING != pHalmac_adapter->halmac_state.efuse_state_set.process_status) {
+		PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "[ERR]Not in HALMAC_CMD_PROCESS_SENDING\n");
+		return HALMAC_RET_SUCCESS;
+	}
+
+	segment_id = (u8)EFUSE_DATA_GET_SEGMENT_ID(pC2h_buf);
+	segment_size = (u8)EFUSE_DATA_GET_SEGMENT_SIZE(pC2h_buf);
+	if (0 == segment_id)
+		pHalmac_adapter->efuse_segment_size = segment_size;
+
+	pEeprom_map = (u8 *)PLATFORM_RTL_MALLOC(pDriver_adapter, eeprom_size);
+	if (NULL == pEeprom_map) {
+		PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_ERR, "[ERR]halmac allocate local eeprom map Fail!!\n");
+		return HALMAC_RET_MALLOC_FAIL;
+	}
+	PLATFORM_RTL_MEMSET(pDriver_adapter, pEeprom_map, 0xFF, eeprom_size);
+
+	PLATFORM_MUTEX_LOCK(pDriver_adapter, &(pHalmac_adapter->EfuseMutex));
+	PLATFORM_RTL_MEMCPY(pDriver_adapter, pHalmac_adapter->pHalEfuse_map + segment_id * pHalmac_adapter->efuse_segment_size,
+		pC2h_buf + HALMAC_C2H_DATA_OFFSET_88XX, segment_size);
+	PLATFORM_MUTEX_UNLOCK(pDriver_adapter, &(pHalmac_adapter->EfuseMutex));
+
+	if (_FALSE == EFUSE_DATA_GET_END_SEGMENT(pC2h_buf)) {
+		PLATFORM_RTL_FREE(pDriver_adapter, pEeprom_map, eeprom_size);
+		return HALMAC_RET_SUCCESS;
+	}
+
+	h2c_return_code = pHalmac_adapter->halmac_state.efuse_state_set.fw_return_code;
+
+	if (HALMAC_H2C_RETURN_SUCCESS == (HALMAC_H2C_RETURN_CODE)h2c_return_code) {
+		process_status = HALMAC_CMD_PROCESS_DONE;
+		pHalmac_adapter->halmac_state.efuse_state_set.process_status = process_status;
+
+		PLATFORM_MUTEX_LOCK(pDriver_adapter, &(pHalmac_adapter->EfuseMutex));
+		pHalmac_adapter->hal_efuse_map_valid = _TRUE;
+		PLATFORM_MUTEX_UNLOCK(pDriver_adapter, &(pHalmac_adapter->EfuseMutex));
+
+		if (1 == pHalmac_adapter->event_trigger.physical_efuse_map) {
+			PLATFORM_EVENT_INDICATION(pDriver_adapter, HALMAC_FEATURE_DUMP_PHYSICAL_EFUSE, process_status, pHalmac_adapter->pHalEfuse_map, pHalmac_adapter->hw_config_info.efuse_size);
+			pHalmac_adapter->event_trigger.physical_efuse_map = 0;
+		}
+
+		if (1 == pHalmac_adapter->event_trigger.logical_efuse_map) {
+			if (HALMAC_RET_SUCCESS != halmac_eeprom_parser_88xx(pHalmac_adapter, pHalmac_adapter->pHalEfuse_map, pEeprom_map)) {
+				PLATFORM_RTL_FREE(pDriver_adapter, pEeprom_map, eeprom_size);
+				return HALMAC_RET_EEPROM_PARSING_FAIL;
+			}
+			PLATFORM_EVENT_INDICATION(pDriver_adapter, HALMAC_FEATURE_DUMP_LOGICAL_EFUSE, process_status, pEeprom_map, eeprom_size);
+			pHalmac_adapter->event_trigger.logical_efuse_map = 0;
+		}
+	} else {
+		process_status = HALMAC_CMD_PROCESS_ERROR;
+		pHalmac_adapter->halmac_state.efuse_state_set.process_status = process_status;
+
+		if (1 == pHalmac_adapter->event_trigger.physical_efuse_map) {
+			PLATFORM_EVENT_INDICATION(pDriver_adapter, HALMAC_FEATURE_DUMP_PHYSICAL_EFUSE, process_status, &(pHalmac_adapter->halmac_state.efuse_state_set.fw_return_code), 1);
+			pHalmac_adapter->event_trigger.physical_efuse_map = 0;
+		}
+
+		if (1 == pHalmac_adapter->event_trigger.logical_efuse_map) {
+			if (HALMAC_RET_SUCCESS != halmac_eeprom_parser_88xx(pHalmac_adapter, pHalmac_adapter->pHalEfuse_map, pEeprom_map)) {
+				PLATFORM_RTL_FREE(pDriver_adapter, pEeprom_map, eeprom_size);
+				return HALMAC_RET_EEPROM_PARSING_FAIL;
+			}
+			PLATFORM_EVENT_INDICATION(pDriver_adapter, HALMAC_FEATURE_DUMP_LOGICAL_EFUSE, process_status, &(pHalmac_adapter->halmac_state.efuse_state_set.fw_return_code), 1);
+			pHalmac_adapter->event_trigger.logical_efuse_map = 0;
+		}
+	}
+
+	PLATFORM_RTL_FREE(pDriver_adapter, pEeprom_map, eeprom_size);
+
+	return HALMAC_RET_SUCCESS;
+}
+
+HALMAC_RET_STATUS
+halmac_parse_h2c_ack_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN u8 *pC2h_buf,
+	IN u32 c2h_size
+)
+{
+	u8 h2c_cmd_id, h2c_sub_cmd_id;
+	u8 h2c_seq = 0, offset = 0, shift = 0;
+	u8 h2c_return_code;
+	VOID *pDriver_adapter = pHalmac_adapter->pDriver_adapter;
+	HALMAC_CMD_PROCESS_STATUS process_status = HALMAC_CMD_PROCESS_UNDEFINE;
+	HALMAC_RET_STATUS status = HALMAC_RET_SUCCESS;
+
+
+	PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "Ack for C2H!!\n");
+
+	h2c_return_code = (u8)H2C_ACK_HDR_GET_H2C_RETURN_CODE(pC2h_buf);
+	if (HALMAC_H2C_RETURN_SUCCESS != (HALMAC_H2C_RETURN_CODE)h2c_return_code)
+		PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "C2H_PKT Status Error!! Status = %d\n", h2c_return_code);
+
+	h2c_cmd_id = (u8)H2C_ACK_HDR_GET_H2C_CMD_ID(pC2h_buf);
+
+	if (0xFF != h2c_cmd_id) {
+		PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "original h2c ack is not handled!!\n");
+		status = HALMAC_RET_C2H_NOT_HANDLED;
+	} else {
+		h2c_sub_cmd_id = (u8)H2C_ACK_HDR_GET_H2C_SUB_CMD_ID(pC2h_buf);
+
+		switch (h2c_sub_cmd_id) {
+		case H2C_SUB_CMD_ID_DUMP_PHYSICAL_EFUSE_ACK:
+			status = halmac_parse_h2c_ack_phy_efuse_88xx(pHalmac_adapter, pC2h_buf, c2h_size);
+			break;
+		case H2C_SUB_CMD_ID_CFG_PARAMETER_ACK:
+			status = halmac_parse_h2c_ack_cfg_para_88xx(pHalmac_adapter, pC2h_buf, c2h_size);
+			break;
+		case H2C_SUB_CMD_ID_UPDATE_PACKET_ACK:
+			status = halmac_parse_h2c_ack_update_packet_88xx(pHalmac_adapter, pC2h_buf, c2h_size);
+			break;
+		case H2C_SUB_CMD_ID_UPDATE_DATAPACK_ACK:
+			status = halmac_parse_h2c_ack_update_datapack_88xx(pHalmac_adapter, pC2h_buf, c2h_size);
+			break;
+		case H2C_SUB_CMD_ID_RUN_DATAPACK_ACK:
+			status = halmac_parse_h2c_ack_run_datapack_88xx(pHalmac_adapter, pC2h_buf, c2h_size);
+			break;
+		case H2C_SUB_CMD_ID_CHANNEL_SWITCH_ACK:
+			status = halmac_parse_h2c_ack_channel_switch_88xx(pHalmac_adapter, pC2h_buf, c2h_size);
+			break;
+		case H2C_SUB_CMD_ID_IQK_ACK:
+			status = halmac_parse_h2c_ack_iqk_88xx(pHalmac_adapter, pC2h_buf, c2h_size);
+			break;
+		case H2C_SUB_CMD_ID_POWER_TRACKING_ACK:
+			status = halmac_parse_h2c_ack_power_tracking_88xx(pHalmac_adapter, pC2h_buf, c2h_size);
+			break;
+		case H2C_SUB_CMD_ID_PSD_ACK:
+			break;
+		default:
+			PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_WARN, "h2c_sub_cmd_id switch case out of boundary!!\n");
+			status = HALMAC_RET_C2H_NOT_HANDLED;
+			break;
+		}
+	}
+
+	return status;
+}
+
+HALMAC_RET_STATUS
+halmac_parse_h2c_ack_phy_efuse_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN u8 *pC2h_buf,
+	IN u32 c2h_size
+)
+{
+	u8 h2c_seq = 0;
+	u8 h2c_return_code;
+	VOID *pDriver_adapter = pHalmac_adapter->pDriver_adapter;
+
+	h2c_seq = (u8)H2C_ACK_HDR_GET_H2C_SEQ(pC2h_buf);
+	PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "[TRACE]Seq num : h2c -> %d c2h -> %d\n", pHalmac_adapter->halmac_state.efuse_state_set.seq_num, h2c_seq);
+	if (h2c_seq != pHalmac_adapter->halmac_state.efuse_state_set.seq_num) {
+		PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "[ERR]Seq num mismactch : h2c -> %d c2h -> %d\n", pHalmac_adapter->halmac_state.efuse_state_set.seq_num, h2c_seq);
+		return HALMAC_RET_SUCCESS;
+	}
+
+	if (HALMAC_CMD_PROCESS_SENDING != pHalmac_adapter->halmac_state.efuse_state_set.process_status) {
+		PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "[ERR]Not in HALMAC_CMD_PROCESS_SENDING\n");
+		return HALMAC_RET_SUCCESS;
+	}
+
+	h2c_return_code = (u8)H2C_ACK_HDR_GET_H2C_RETURN_CODE(pC2h_buf);
+	pHalmac_adapter->halmac_state.efuse_state_set.fw_return_code = h2c_return_code;
+
+	return HALMAC_RET_SUCCESS;
+}
+
+HALMAC_RET_STATUS
+halmac_parse_h2c_ack_cfg_para_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN u8 *pC2h_buf,
+	IN u32 c2h_size
+)
+{
+	u8 h2c_seq = 0;
+	u8 h2c_return_code;
+	u32 offset_accu = 0, value_accu = 0;
+	VOID *pDriver_adapter = pHalmac_adapter->pDriver_adapter;
+	HALMAC_CMD_PROCESS_STATUS process_status = HALMAC_CMD_PROCESS_UNDEFINE;
+
+	h2c_seq = (u8)H2C_ACK_HDR_GET_H2C_SEQ(pC2h_buf);
+	PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "Seq num : h2c -> %d c2h -> %d\n", pHalmac_adapter->halmac_state.cfg_para_state_set.seq_num, h2c_seq);
+	if (h2c_seq != pHalmac_adapter->halmac_state.cfg_para_state_set.seq_num) {
+		PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "Seq num mismactch : h2c -> %d c2h -> %d\n", pHalmac_adapter->halmac_state.cfg_para_state_set.seq_num, h2c_seq);
+		return HALMAC_RET_SUCCESS;
+	}
+
+	if (HALMAC_CMD_PROCESS_SENDING != pHalmac_adapter->halmac_state.cfg_para_state_set.process_status) {
+		PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "Not in HALMAC_CMD_PROCESS_SENDING\n");
+		return HALMAC_RET_SUCCESS;
+	}
+
+	h2c_return_code = (u8)H2C_ACK_HDR_GET_H2C_RETURN_CODE(pC2h_buf);
+	pHalmac_adapter->halmac_state.cfg_para_state_set.fw_return_code = h2c_return_code;
+	offset_accu = CFG_PARAMETER_ACK_GET_OFFSET_ACCUMULATION(pC2h_buf);
+	value_accu = CFG_PARAMETER_ACK_GET_VALUE_ACCUMULATION(pC2h_buf);
+
+	if ((offset_accu != pHalmac_adapter->config_para_info.offset_accumulation) || (value_accu != pHalmac_adapter->config_para_info.value_accumulation)) {
+		PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "[C2H]offset_accu : %x, value_accu : %x!!\n", offset_accu, value_accu);
+		PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "[Adapter]offset_accu : %x, value_accu : %x!!\n", pHalmac_adapter->config_para_info.offset_accumulation, pHalmac_adapter->config_para_info.value_accumulation);
+		process_status = HALMAC_CMD_PROCESS_ERROR;
+	}
+
+	if ((HALMAC_H2C_RETURN_SUCCESS == (HALMAC_H2C_RETURN_CODE)h2c_return_code) && (HALMAC_CMD_PROCESS_ERROR != process_status)) {
+		process_status = HALMAC_CMD_PROCESS_DONE;
+		pHalmac_adapter->halmac_state.cfg_para_state_set.process_status = process_status;
+		PLATFORM_EVENT_INDICATION(pDriver_adapter, HALMAC_FEATURE_CFG_PARA, process_status, NULL, 0);
+	} else {
+		process_status = HALMAC_CMD_PROCESS_ERROR;
+		pHalmac_adapter->halmac_state.cfg_para_state_set.process_status = process_status;
+		PLATFORM_EVENT_INDICATION(pDriver_adapter, HALMAC_FEATURE_CFG_PARA, process_status, &(pHalmac_adapter->halmac_state.cfg_para_state_set.fw_return_code), 1);
+	}
+
+	return HALMAC_RET_SUCCESS;
+}
+
+HALMAC_RET_STATUS
+halmac_parse_h2c_ack_update_packet_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN u8 *pC2h_buf,
+	IN u32 c2h_size
+)
+{
+	u8 h2c_seq = 0;
+	u8 h2c_return_code;
+	VOID *pDriver_adapter = pHalmac_adapter->pDriver_adapter;
+	HALMAC_CMD_PROCESS_STATUS process_status;
+
+	h2c_seq = (u8)H2C_ACK_HDR_GET_H2C_SEQ(pC2h_buf);
+	PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "[TRACE]Seq num : h2c -> %d c2h -> %d\n", pHalmac_adapter->halmac_state.update_packet_set.seq_num, h2c_seq);
+	if (h2c_seq != pHalmac_adapter->halmac_state.update_packet_set.seq_num) {
+		PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "[ERR]Seq num mismactch : h2c -> %d c2h -> %d\n", pHalmac_adapter->halmac_state.update_packet_set.seq_num, h2c_seq);
+		return HALMAC_RET_SUCCESS;
+	}
+
+	if (HALMAC_CMD_PROCESS_SENDING != pHalmac_adapter->halmac_state.update_packet_set.process_status) {
+		PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "[ERR]Not in HALMAC_CMD_PROCESS_SENDING\n");
+		return HALMAC_RET_SUCCESS;
+	}
+
+	h2c_return_code = (u8)H2C_ACK_HDR_GET_H2C_RETURN_CODE(pC2h_buf);
+	pHalmac_adapter->halmac_state.update_packet_set.fw_return_code = h2c_return_code;
+
+	if (HALMAC_H2C_RETURN_SUCCESS == (HALMAC_H2C_RETURN_CODE)h2c_return_code) {
+		process_status = HALMAC_CMD_PROCESS_DONE;
+		pHalmac_adapter->halmac_state.update_packet_set.process_status = process_status;
+		PLATFORM_EVENT_INDICATION(pDriver_adapter, HALMAC_FEATURE_UPDATE_PACKET, process_status, NULL, 0);
+	} else {
+		process_status = HALMAC_CMD_PROCESS_ERROR;
+		pHalmac_adapter->halmac_state.update_packet_set.process_status = process_status;
+		PLATFORM_EVENT_INDICATION(pDriver_adapter, HALMAC_FEATURE_UPDATE_PACKET, process_status, &(pHalmac_adapter->halmac_state.update_packet_set.fw_return_code), 1);
+	}
+
+	return HALMAC_RET_SUCCESS;
+}
+
+HALMAC_RET_STATUS
+halmac_parse_h2c_ack_update_datapack_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN u8 *pC2h_buf,
+	IN u32 c2h_size
+)
+{
+	VOID *pDriver_adapter = pHalmac_adapter->pDriver_adapter;
+	HALMAC_CMD_PROCESS_STATUS process_status = HALMAC_CMD_PROCESS_UNDEFINE;
+
+	PLATFORM_EVENT_INDICATION(pDriver_adapter, HALMAC_FEATURE_UPDATE_DATAPACK, process_status, NULL, 0);
+
+	return HALMAC_RET_SUCCESS;
+}
+
+
+HALMAC_RET_STATUS
+halmac_parse_h2c_ack_run_datapack_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN u8 *pC2h_buf,
+	IN u32 c2h_size
+)
+{
+	VOID *pDriver_adapter = pHalmac_adapter->pDriver_adapter;
+	HALMAC_CMD_PROCESS_STATUS process_status = HALMAC_CMD_PROCESS_UNDEFINE;
+
+	PLATFORM_EVENT_INDICATION(pDriver_adapter, HALMAC_FEATURE_RUN_DATAPACK, process_status, NULL, 0);
+
+	return HALMAC_RET_SUCCESS;
+}
+
+
+HALMAC_RET_STATUS
+halmac_parse_h2c_ack_channel_switch_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN u8 *pC2h_buf,
+	IN u32 c2h_size
+)
+{
+	u8 h2c_seq = 0;
+	u8 h2c_return_code;
+	VOID *pDriver_adapter = pHalmac_adapter->pDriver_adapter;
+	HALMAC_CMD_PROCESS_STATUS process_status;
+
+	h2c_seq = (u8)H2C_ACK_HDR_GET_H2C_SEQ(pC2h_buf);
+	PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "[TRACE]Seq num : h2c -> %d c2h -> %d\n", pHalmac_adapter->halmac_state.scan_state_set.seq_num, h2c_seq);
+	if (h2c_seq != pHalmac_adapter->halmac_state.scan_state_set.seq_num) {
+		PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "[ERR]Seq num mismactch : h2c -> %d c2h -> %d\n", pHalmac_adapter->halmac_state.scan_state_set.seq_num, h2c_seq);
+		return HALMAC_RET_SUCCESS;
+	}
+
+	if (HALMAC_CMD_PROCESS_SENDING != pHalmac_adapter->halmac_state.scan_state_set.process_status) {
+		PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "[ERR]Not in HALMAC_CMD_PROCESS_SENDING\n");
+		return HALMAC_RET_SUCCESS;
+	}
+
+	h2c_return_code = (u8)H2C_ACK_HDR_GET_H2C_RETURN_CODE(pC2h_buf);
+	pHalmac_adapter->halmac_state.scan_state_set.fw_return_code = h2c_return_code;
+
+	if (HALMAC_H2C_RETURN_SUCCESS == (HALMAC_H2C_RETURN_CODE)h2c_return_code) {
+		process_status = HALMAC_CMD_PROCESS_RCVD;
+		pHalmac_adapter->halmac_state.scan_state_set.process_status = process_status;
+		PLATFORM_EVENT_INDICATION(pDriver_adapter, HALMAC_FEATURE_CHANNEL_SWITCH, process_status, NULL, 0);
+	} else {
+		process_status = HALMAC_CMD_PROCESS_ERROR;
+		pHalmac_adapter->halmac_state.scan_state_set.process_status = process_status;
+		PLATFORM_EVENT_INDICATION(pDriver_adapter, HALMAC_FEATURE_CHANNEL_SWITCH, process_status, &(pHalmac_adapter->halmac_state.scan_state_set.fw_return_code), 1);
+	}
+
+	return HALMAC_RET_SUCCESS;
+}
+
+HALMAC_RET_STATUS
+halmac_parse_h2c_ack_iqk_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN u8 *pC2h_buf,
+	IN u32 c2h_size
+)
+{
+	u8 h2c_seq = 0;
+	u8 h2c_return_code;
+	VOID *pDriver_adapter = pHalmac_adapter->pDriver_adapter;
+	HALMAC_CMD_PROCESS_STATUS process_status;
+
+	h2c_seq = (u8)H2C_ACK_HDR_GET_H2C_SEQ(pC2h_buf);
+	PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "[TRACE]Seq num : h2c -> %d c2h -> %d\n", pHalmac_adapter->halmac_state.iqk_set.seq_num, h2c_seq);
+	if (h2c_seq != pHalmac_adapter->halmac_state.iqk_set.seq_num) {
+		PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "[ERR]Seq num mismactch : h2c -> %d c2h -> %d\n", pHalmac_adapter->halmac_state.iqk_set.seq_num, h2c_seq);
+		return HALMAC_RET_SUCCESS;
+	}
+
+	if (HALMAC_CMD_PROCESS_SENDING != pHalmac_adapter->halmac_state.iqk_set.process_status) {
+		PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "[ERR]Not in HALMAC_CMD_PROCESS_SENDING\n");
+		return HALMAC_RET_SUCCESS;
+	}
+
+	h2c_return_code = (u8)H2C_ACK_HDR_GET_H2C_RETURN_CODE(pC2h_buf);
+	pHalmac_adapter->halmac_state.iqk_set.fw_return_code = h2c_return_code;
+
+	if (HALMAC_H2C_RETURN_SUCCESS == (HALMAC_H2C_RETURN_CODE)h2c_return_code) {
+		process_status = HALMAC_CMD_PROCESS_DONE;
+		pHalmac_adapter->halmac_state.iqk_set.process_status = process_status;
+		PLATFORM_EVENT_INDICATION(pDriver_adapter, HALMAC_FEATURE_IQK, process_status, NULL, 0);
+	} else {
+		process_status = HALMAC_CMD_PROCESS_ERROR;
+		pHalmac_adapter->halmac_state.iqk_set.process_status = process_status;
+		PLATFORM_EVENT_INDICATION(pDriver_adapter, HALMAC_FEATURE_IQK, process_status, &(pHalmac_adapter->halmac_state.iqk_set.fw_return_code), 1);
+	}
+
+	return HALMAC_RET_SUCCESS;
+}
+
+HALMAC_RET_STATUS
+halmac_parse_h2c_ack_power_tracking_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN u8 *pC2h_buf,
+	IN u32 c2h_size
+)
+{
+	u8 h2c_seq = 0;
+	u8 h2c_return_code;
+	VOID *pDriver_adapter = pHalmac_adapter->pDriver_adapter;
+	HALMAC_CMD_PROCESS_STATUS process_status;
+
+	h2c_seq = (u8)H2C_ACK_HDR_GET_H2C_SEQ(pC2h_buf);
+	PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "[TRACE]Seq num : h2c -> %d c2h -> %d\n", pHalmac_adapter->halmac_state.power_tracking_set.seq_num, h2c_seq);
+	if (h2c_seq != pHalmac_adapter->halmac_state.power_tracking_set.seq_num) {
+		PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "[ERR]Seq num mismactch : h2c -> %d c2h -> %d\n", pHalmac_adapter->halmac_state.power_tracking_set.seq_num, h2c_seq);
+		return HALMAC_RET_SUCCESS;
+	}
+
+	if (HALMAC_CMD_PROCESS_SENDING != pHalmac_adapter->halmac_state.power_tracking_set.process_status) {
+		PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "[ERR]Not in HALMAC_CMD_PROCESS_SENDING\n");
+		return HALMAC_RET_SUCCESS;
+	}
+
+	h2c_return_code = (u8)H2C_ACK_HDR_GET_H2C_RETURN_CODE(pC2h_buf);
+	pHalmac_adapter->halmac_state.power_tracking_set.fw_return_code = h2c_return_code;
+
+	if (HALMAC_H2C_RETURN_SUCCESS == (HALMAC_H2C_RETURN_CODE)h2c_return_code) {
+		process_status = HALMAC_CMD_PROCESS_DONE;
+		pHalmac_adapter->halmac_state.power_tracking_set.process_status = process_status;
+		PLATFORM_EVENT_INDICATION(pDriver_adapter, HALMAC_FEATURE_POWER_TRACKING, process_status, NULL, 0);
+	} else {
+		process_status = HALMAC_CMD_PROCESS_ERROR;
+		pHalmac_adapter->halmac_state.power_tracking_set.process_status = process_status;
+		PLATFORM_EVENT_INDICATION(pDriver_adapter, HALMAC_FEATURE_POWER_TRACKING, process_status, &(pHalmac_adapter->halmac_state.power_tracking_set.fw_return_code), 1);
+	}
+
+	return HALMAC_RET_SUCCESS;
+}
+
+HALMAC_RET_STATUS
+halmac_convert_to_sdio_bus_offset_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	INOUT u32 *halmac_offset
+)
+{
+	VOID *pDriver_adapter = NULL;
+
+	pDriver_adapter = pHalmac_adapter->pDriver_adapter;
+
+	switch ((*halmac_offset) & 0xFFFF0000) {
+	case WLAN_IOREG_OFFSET:
+		*halmac_offset = (HALMAC_SDIO_CMD_ADDR_MAC_REG << 13) | (*halmac_offset & HALMAC_WLAN_MAC_REG_MSK);
+		break;
+	case SDIO_LOCAL_OFFSET:
+		*halmac_offset = (HALMAC_SDIO_CMD_ADDR_SDIO_REG << 13) | (*halmac_offset & HALMAC_SDIO_LOCAL_MSK);
+		break;
+	default:
+		*halmac_offset = 0xFFFFFFFF;
+		PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "Unknown base address!!\n");
+		return HALMAC_RET_CONVERT_SDIO_OFFSET_FAIL;
+	}
+
+	return HALMAC_RET_SUCCESS;
+}
+
+HALMAC_RET_STATUS
+halmac_update_sdio_free_page_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter
+)
+{
+	u32 free_page = 0, free_page2 = 0, free_page3 = 0;
+	VOID *pDriver_adapter = NULL;
+	PHALMAC_API pHalmac_api;
+	PHALMAC_SDIO_FREE_SPACE pSdio_free_space;
+	u8 data[12] = {0};
+	HALMAC_RET_STATUS status = HALMAC_RET_SUCCESS;
+
+	pDriver_adapter = pHalmac_adapter->pDriver_adapter;
+	pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api;
+
+	PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_update_sdio_free_page_88xx ==========>\n");
+
+	pSdio_free_space = &(pHalmac_adapter->sdio_free_space);
+	/*need to use HALMAC_REG_READ_N, 20160316, Soar*/
+	HALMAC_REG_SDIO_CMD53_READ_N(pHalmac_adapter, REG_SDIO_FREE_TXPG, 12, data);
+/*
+	free_page = HALMAC_REG_READ_32(pHalmac_adapter, REG_SDIO_FREE_TXPG);
+	free_page2 = HALMAC_REG_READ_32(pHalmac_adapter, REG_SDIO_FREE_TXPG2);
+	free_page3 = HALMAC_REG_READ_32(pHalmac_adapter, REG_SDIO_OQT_FREE_TXPG_V1);
+*/
+	free_page = data[0] | (data[1] << 8) | (data[2] << 16) | (data[3] << 24);
+	free_page2 = data[4] | (data[5] << 8) | (data[6] << 16) | (data[7] << 24);
+	free_page3 = data[8] | (data[9] << 8) | (data[10] << 16) | (data[11] << 24);
+
+	pSdio_free_space->high_queue_number = (u16)BIT_GET_HIQ_FREEPG_V1(free_page);
+	pSdio_free_space->normal_queue_number = (u16)BIT_GET_MID_FREEPG_V1(free_page);
+	pSdio_free_space->low_queue_number = (u16)BIT_GET_LOW_FREEPG_V1(free_page2);
+	pSdio_free_space->public_queue_number = (u16)BIT_GET_PUB_FREEPG_V1(free_page2);
+	pSdio_free_space->extra_queue_number = (u16)BIT_GET_EXQ_FREEPG_V1(free_page3);
+	pSdio_free_space->ac_oqt_number = (u8)((free_page3 >> 16) & 0xFF);
+	pSdio_free_space->non_ac_oqt_number = (u8)((free_page3 >> 24) & 0xFF);
+
+	PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_update_sdio_free_page_88xx <==========\n");
+
+	return HALMAC_RET_SUCCESS;
+}
+
+HALMAC_RET_STATUS
+halmac_update_oqt_free_space_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter
+)
+{
+	VOID *pDriver_adapter = NULL;
+	PHALMAC_API pHalmac_api;
+	PHALMAC_SDIO_FREE_SPACE pSdio_free_space;
+	u8 value;
+
+	pDriver_adapter = pHalmac_adapter->pDriver_adapter;
+	pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api;
+
+	PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_update_oqt_free_space_88xx ==========>\n");
+
+	pSdio_free_space = &(pHalmac_adapter->sdio_free_space);
+
+	pSdio_free_space->ac_oqt_number = HALMAC_REG_READ_8(pHalmac_adapter, REG_SDIO_OQT_FREE_TXPG_V1 + 2);
+	/* pSdio_free_space->non_ac_oqt_number = (u8)BIT_GET_NOAC_OQT_FREEPG_V1(oqt_free_page); */
+	pSdio_free_space->ac_empty = 0;
+	value = HALMAC_REG_READ_8(pHalmac_adapter, REG_TXPKT_EMPTY);
+	while (value > 0) {
+		value = value & (value - 1);
+		pSdio_free_space->ac_empty++;
+	};
+
+	PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_update_oqt_free_space_88xx <==========\n");
+
+	return HALMAC_RET_SUCCESS;
+}
+
+HALMAC_EFUSE_CMD_CONSTRUCT_STATE
+halmac_query_efuse_curr_state_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter
+)
+{
+	return pHalmac_adapter->halmac_state.efuse_state_set.efuse_cmd_construct_state;
+}
+
+HALMAC_RET_STATUS
+halmac_transition_efuse_state_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN HALMAC_EFUSE_CMD_CONSTRUCT_STATE dest_state
+)
+{
+	PHALMAC_EFUSE_STATE_SET pEfuse_state = &(pHalmac_adapter->halmac_state.efuse_state_set);
+
+	if ((HALMAC_EFUSE_CMD_CONSTRUCT_IDLE != pEfuse_state->efuse_cmd_construct_state)
+	    && (HALMAC_EFUSE_CMD_CONSTRUCT_BUSY != pEfuse_state->efuse_cmd_construct_state)
+	    && (HALMAC_EFUSE_CMD_CONSTRUCT_H2C_SENT != pEfuse_state->efuse_cmd_construct_state))
+		return HALMAC_RET_ERROR_STATE;
+
+	if (pEfuse_state->efuse_cmd_construct_state == dest_state)
+		return HALMAC_RET_ERROR_STATE;
+
+	if (HALMAC_EFUSE_CMD_CONSTRUCT_BUSY == dest_state) {
+		if (HALMAC_EFUSE_CMD_CONSTRUCT_H2C_SENT == pEfuse_state->efuse_cmd_construct_state)
+			return HALMAC_RET_ERROR_STATE;
+	} else if (HALMAC_EFUSE_CMD_CONSTRUCT_H2C_SENT == dest_state) {
+		if (HALMAC_EFUSE_CMD_CONSTRUCT_IDLE == pEfuse_state->efuse_cmd_construct_state)
+			return HALMAC_RET_ERROR_STATE;
+	}
+
+	pEfuse_state->efuse_cmd_construct_state = dest_state;
+
+	return HALMAC_RET_SUCCESS;
+}
+
+HALMAC_CFG_PARA_CMD_CONSTRUCT_STATE
+halmac_query_cfg_para_curr_state_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter
+)
+{
+	return pHalmac_adapter->halmac_state.cfg_para_state_set.cfg_para_cmd_construct_state;
+}
+
+HALMAC_RET_STATUS
+halmac_transition_cfg_para_state_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN HALMAC_CFG_PARA_CMD_CONSTRUCT_STATE dest_state
+)
+{
+	PHALMAC_CFG_PARA_STATE_SET pCfg_para = &(pHalmac_adapter->halmac_state.cfg_para_state_set);
+
+	if ((HALMAC_CFG_PARA_CMD_CONSTRUCT_IDLE != pCfg_para->cfg_para_cmd_construct_state) &&
+	    (HALMAC_CFG_PARA_CMD_CONSTRUCT_CONSTRUCTING != pCfg_para->cfg_para_cmd_construct_state) &&
+	    (HALMAC_CFG_PARA_CMD_CONSTRUCT_H2C_SENT != pCfg_para->cfg_para_cmd_construct_state))
+		return HALMAC_RET_ERROR_STATE;
+
+	if (HALMAC_CFG_PARA_CMD_CONSTRUCT_IDLE == dest_state) {
+		if (HALMAC_CFG_PARA_CMD_CONSTRUCT_CONSTRUCTING == pCfg_para->cfg_para_cmd_construct_state)
+			return HALMAC_RET_ERROR_STATE;
+	} else if (HALMAC_CFG_PARA_CMD_CONSTRUCT_CONSTRUCTING == dest_state) {
+		if (HALMAC_CFG_PARA_CMD_CONSTRUCT_H2C_SENT == pCfg_para->cfg_para_cmd_construct_state)
+			return HALMAC_RET_ERROR_STATE;
+	} else if (HALMAC_CFG_PARA_CMD_CONSTRUCT_H2C_SENT == dest_state) {
+		if ((HALMAC_CFG_PARA_CMD_CONSTRUCT_IDLE == pCfg_para->cfg_para_cmd_construct_state)
+		    || (HALMAC_CFG_PARA_CMD_CONSTRUCT_H2C_SENT == pCfg_para->cfg_para_cmd_construct_state))
+			return HALMAC_RET_ERROR_STATE;
+	}
+
+	pCfg_para->cfg_para_cmd_construct_state = dest_state;
+
+	return HALMAC_RET_SUCCESS;
+}
+
+HALMAC_SCAN_CMD_CONSTRUCT_STATE
+halmac_query_scan_curr_state_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter
+)
+{
+	return pHalmac_adapter->halmac_state.scan_state_set.scan_cmd_construct_state;
+}
+
+HALMAC_RET_STATUS
+halmac_transition_scan_state_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN HALMAC_SCAN_CMD_CONSTRUCT_STATE dest_state
+)
+{
+	PHALMAC_SCAN_STATE_SET pScan = &(pHalmac_adapter->halmac_state.scan_state_set);
+
+	if (pScan->scan_cmd_construct_state > HALMAC_SCAN_CMD_CONSTRUCT_H2C_SENT)
+		return HALMAC_RET_ERROR_STATE;
+
+	if (HALMAC_SCAN_CMD_CONSTRUCT_IDLE == dest_state) {
+		if ((HALMAC_SCAN_CMD_CONSTRUCT_BUFFER_CLEARED == pScan->scan_cmd_construct_state) ||
+		    (HALMAC_SCAN_CMD_CONSTRUCT_CONSTRUCTING == pScan->scan_cmd_construct_state))
+			return HALMAC_RET_ERROR_STATE;
+	} else if (HALMAC_SCAN_CMD_CONSTRUCT_BUFFER_CLEARED == dest_state) {
+		if (HALMAC_SCAN_CMD_CONSTRUCT_H2C_SENT == pScan->scan_cmd_construct_state)
+			return HALMAC_RET_ERROR_STATE;
+	} else if (HALMAC_SCAN_CMD_CONSTRUCT_CONSTRUCTING == dest_state) {
+		if ((HALMAC_SCAN_CMD_CONSTRUCT_IDLE == pScan->scan_cmd_construct_state) ||
+		    (HALMAC_SCAN_CMD_CONSTRUCT_H2C_SENT == pScan->scan_cmd_construct_state))
+			return HALMAC_RET_ERROR_STATE;
+	} else if (HALMAC_SCAN_CMD_CONSTRUCT_H2C_SENT == dest_state) {
+		if ((HALMAC_SCAN_CMD_CONSTRUCT_CONSTRUCTING != pScan->scan_cmd_construct_state) &&
+		    (HALMAC_SCAN_CMD_CONSTRUCT_BUFFER_CLEARED != pScan->scan_cmd_construct_state))
+			return HALMAC_RET_ERROR_STATE;
+	}
+
+	pScan->scan_cmd_construct_state = dest_state;
+
+	return HALMAC_RET_SUCCESS;
+}
+
+HALMAC_RET_STATUS
+halmac_query_cfg_para_status_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	OUT HALMAC_CMD_PROCESS_STATUS *pProcess_status,
+	INOUT u8 *data,
+	INOUT u32 *size
+)
+{
+	PHALMAC_CFG_PARA_STATE_SET pCfg_para_state_set = &(pHalmac_adapter->halmac_state.cfg_para_state_set);
+
+	*pProcess_status = pCfg_para_state_set->process_status;
+
+	return HALMAC_RET_SUCCESS;
+}
+
+HALMAC_RET_STATUS
+halmac_query_dump_physical_efuse_status_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	OUT HALMAC_CMD_PROCESS_STATUS *pProcess_status,
+	INOUT u8 *data,
+	INOUT u32 *size
+)
+{
+	VOID *pDriver_adapter = NULL;
+	PHALMAC_EFUSE_STATE_SET pEfuse_state_set = &(pHalmac_adapter->halmac_state.efuse_state_set);
+
+	pDriver_adapter = pHalmac_adapter->pDriver_adapter;
+
+	*pProcess_status = pEfuse_state_set->process_status;
+
+	if (NULL == data)
+		return HALMAC_RET_NULL_POINTER;
+
+	if (NULL == size)
+		return HALMAC_RET_NULL_POINTER;
+
+	if (HALMAC_CMD_PROCESS_DONE == *pProcess_status) {
+		if (*size < pHalmac_adapter->hw_config_info.efuse_size) {
+			*size = pHalmac_adapter->hw_config_info.efuse_size;
+			return HALMAC_RET_BUFFER_TOO_SMALL;
+		}
+
+		*size = pHalmac_adapter->hw_config_info.efuse_size;
+		PLATFORM_RTL_MEMCPY(pDriver_adapter, data, pHalmac_adapter->pHalEfuse_map, *size);
+	}
+
+	return HALMAC_RET_SUCCESS;
+}
+
+HALMAC_RET_STATUS
+halmac_query_dump_logical_efuse_status_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	OUT HALMAC_CMD_PROCESS_STATUS *pProcess_status,
+	INOUT u8 *data,
+	INOUT u32 *size
+)
+{
+	u8 *pEeprom_map = NULL;
+	u32 eeprom_size = pHalmac_adapter->hw_config_info.eeprom_size;
+	VOID *pDriver_adapter = NULL;
+	PHALMAC_EFUSE_STATE_SET pEfuse_state_set = &(pHalmac_adapter->halmac_state.efuse_state_set);
+
+	pDriver_adapter = pHalmac_adapter->pDriver_adapter;
+
+	*pProcess_status = pEfuse_state_set->process_status;
+
+	if (NULL == data)
+		return HALMAC_RET_NULL_POINTER;
+
+	if (NULL == size)
+		return HALMAC_RET_NULL_POINTER;
+
+	if (HALMAC_CMD_PROCESS_DONE == *pProcess_status) {
+		if (*size < eeprom_size) {
+			*size = eeprom_size;
+			return HALMAC_RET_BUFFER_TOO_SMALL;
+		}
+
+		*size = eeprom_size;
+
+		pEeprom_map = (u8 *)PLATFORM_RTL_MALLOC(pDriver_adapter, eeprom_size);
+		if (NULL == pEeprom_map) {
+			PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_ERR, "[ERR]halmac allocate local eeprom map Fail!!\n");
+			return HALMAC_RET_MALLOC_FAIL;
+		}
+		PLATFORM_RTL_MEMSET(pDriver_adapter, pEeprom_map, 0xFF, eeprom_size);
+
+		if (HALMAC_RET_SUCCESS != halmac_eeprom_parser_88xx(pHalmac_adapter, pHalmac_adapter->pHalEfuse_map, pEeprom_map)) {
+			PLATFORM_RTL_FREE(pDriver_adapter, pEeprom_map, eeprom_size);
+			return HALMAC_RET_EEPROM_PARSING_FAIL;
+		}
+
+		PLATFORM_RTL_MEMCPY(pDriver_adapter, data, pEeprom_map, *size);
+
+		PLATFORM_RTL_FREE(pDriver_adapter, pEeprom_map, eeprom_size);
+	}
+
+	return HALMAC_RET_SUCCESS;
+}
+
+HALMAC_RET_STATUS
+halmac_query_channel_switch_status_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	OUT HALMAC_CMD_PROCESS_STATUS *pProcess_status,
+	INOUT u8 *data,
+	INOUT u32 *size
+)
+{
+	PHALMAC_SCAN_STATE_SET pScan_state_set = &(pHalmac_adapter->halmac_state.scan_state_set);
+
+	*pProcess_status = pScan_state_set->process_status;
+
+	return HALMAC_RET_SUCCESS;
+}
+
+HALMAC_RET_STATUS
+halmac_query_update_packet_status_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	OUT HALMAC_CMD_PROCESS_STATUS *pProcess_status,
+	INOUT u8 *data,
+	INOUT u32 *size
+)
+{
+	PHALMAC_UPDATE_PACKET_STATE_SET pUpdate_packet_set = &(pHalmac_adapter->halmac_state.update_packet_set);
+
+	*pProcess_status = pUpdate_packet_set->process_status;
+
+	return HALMAC_RET_SUCCESS;
+}
+
+HALMAC_RET_STATUS
+halmac_query_iqk_status_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	OUT HALMAC_CMD_PROCESS_STATUS *pProcess_status,
+	INOUT u8 *data,
+	INOUT u32 *size
+)
+{
+	PHALMAC_IQK_STATE_SET pIqk_set = &(pHalmac_adapter->halmac_state.iqk_set);
+
+	*pProcess_status = pIqk_set->process_status;
+
+	return HALMAC_RET_SUCCESS;
+}
+
+HALMAC_RET_STATUS
+halmac_query_power_tracking_status_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	OUT HALMAC_CMD_PROCESS_STATUS *pProcess_status,
+	INOUT u8 *data,
+	INOUT u32 *size
+)
+{
+	PHALMAC_POWER_TRACKING_STATE_SET pPower_tracking_state_set = &(pHalmac_adapter->halmac_state.power_tracking_set);;
+
+	*pProcess_status = pPower_tracking_state_set->process_status;
+
+	return HALMAC_RET_SUCCESS;
+}
+
+HALMAC_RET_STATUS
+halmac_query_psd_status_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	OUT HALMAC_CMD_PROCESS_STATUS *pProcess_status,
+	INOUT u8 *data,
+	INOUT u32 *size
+)
+{
+	VOID *pDriver_adapter = NULL;
+	PHALMAC_PSD_STATE_SET pPsd_set = &(pHalmac_adapter->halmac_state.psd_set);
+
+	pDriver_adapter = pHalmac_adapter->pDriver_adapter;
+
+	*pProcess_status = pPsd_set->process_status;
+
+	if (NULL == data)
+		return HALMAC_RET_NULL_POINTER;
+
+	if (NULL == size)
+		return HALMAC_RET_NULL_POINTER;
+
+	if (HALMAC_CMD_PROCESS_DONE == *pProcess_status) {
+		if (*size < pPsd_set->data_size) {
+			*size = pPsd_set->data_size;
+			return HALMAC_RET_BUFFER_TOO_SMALL;
+		}
+
+		*size = pPsd_set->data_size;
+		PLATFORM_RTL_MEMCPY(pDriver_adapter, data, pPsd_set->pData, *size);
+	}
+
+	return HALMAC_RET_SUCCESS;
+}
+
+HALMAC_RET_STATUS
+halmac_verify_io_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter
+)
+{
+	u8 value8, wvalue8;
+	u32 value32, value32_2, wvalue32;
+	u32 halmac_offset;
+	VOID *pDriver_adapter = NULL;
+	HALMAC_RET_STATUS ret_status = HALMAC_RET_SUCCESS;
+
+	pDriver_adapter = pHalmac_adapter->pDriver_adapter;
+
+	if (HALMAC_INTERFACE_SDIO == pHalmac_adapter->halmac_interface) {
+		halmac_offset = REG_PAGE5_DUMMY;
+		if (0 == (halmac_offset & 0xFFFF0000))
+			halmac_offset |= WLAN_IOREG_OFFSET;
+
+		ret_status = halmac_convert_to_sdio_bus_offset_88xx(pHalmac_adapter, &halmac_offset);
+
+		/* Verify CMD52 R/W */
+		wvalue8 = 0xab;
+		PLATFORM_SDIO_CMD52_WRITE(pDriver_adapter, halmac_offset, wvalue8);
+
+		value8 = PLATFORM_SDIO_CMD52_READ(pDriver_adapter, halmac_offset);
+
+		if (value8 != wvalue8) {
+			PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "cmd52 r/w fail write = %X read = %X\n", wvalue8, value8);
+			ret_status = HALMAC_RET_PLATFORM_API_INCORRECT;
+		} else {
+			PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "cmd52 r/w ok\n");
+		}
+
+		/* Verify CMD53 R/W */
+		PLATFORM_SDIO_CMD52_WRITE(pDriver_adapter, halmac_offset, 0xaa);
+		PLATFORM_SDIO_CMD52_WRITE(pDriver_adapter, halmac_offset + 1, 0xbb);
+		PLATFORM_SDIO_CMD52_WRITE(pDriver_adapter, halmac_offset + 2, 0xcc);
+		PLATFORM_SDIO_CMD52_WRITE(pDriver_adapter, halmac_offset + 3, 0xdd);
+
+		value32 = PLATFORM_SDIO_CMD53_READ_32(pDriver_adapter, halmac_offset);
+
+		if (0xddccbbaa != value32) {
+			PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "cmd53 r fail : read = %X\n");
+			ret_status = HALMAC_RET_PLATFORM_API_INCORRECT;
+		} else {
+			PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "cmd53 r ok\n");
+		}
+
+		wvalue32 = 0x11223344;
+		PLATFORM_SDIO_CMD53_WRITE_32(pDriver_adapter, halmac_offset, wvalue32);
+
+		value32 = PLATFORM_SDIO_CMD53_READ_32(pDriver_adapter, halmac_offset);
+
+		if (value32 != wvalue32) {
+			PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "cmd53 w fail\n");
+			ret_status = HALMAC_RET_PLATFORM_API_INCORRECT;
+		} else {
+			PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "cmd53 w ok\n");
+		}
+
+		value32 = PLATFORM_SDIO_CMD53_READ_32(pDriver_adapter, halmac_offset + 2); /* value32 should be 0x33441122 */
+
+		wvalue32 = 0x11225566;
+		PLATFORM_SDIO_CMD53_WRITE_32(pDriver_adapter, halmac_offset, wvalue32);
+
+		value32_2 = PLATFORM_SDIO_CMD53_READ_32(pDriver_adapter, halmac_offset + 2); /* value32 should be 0x55661122 */
+		if (value32_2 == value32) {
+			PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "cmd52 is used for HAL_SDIO_CMD53_READ_32\n");
+			ret_status = HALMAC_RET_PLATFORM_API_INCORRECT;
+		} else {
+			PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "cmd53 is correctly used\n");
+		}
+	} else {
+		wvalue32 = 0x77665511;
+		PLATFORM_REG_WRITE_32(pDriver_adapter, REG_PAGE5_DUMMY, wvalue32);
+
+		value32 = PLATFORM_REG_READ_32(pDriver_adapter, REG_PAGE5_DUMMY);
+		if (value32 != wvalue32) {
+			PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "reg rw\n");
+			ret_status = HALMAC_RET_PLATFORM_API_INCORRECT;
+		} else {
+			PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "reg rw ok\n");
+		}
+	}
+
+	return ret_status;
+}
+
+HALMAC_RET_STATUS
+halmac_verify_send_rsvd_page_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter
+)
+{
+	u8 *rsvd_buf = NULL;
+	u8 *rsvd_page = NULL;
+	u32 i;
+	u32 h2c_pkt_verify_size = 64, h2c_pkt_verify_payload = 0xab;
+	VOID *pDriver_adapter = NULL;
+	HALMAC_RET_STATUS ret_status = HALMAC_RET_SUCCESS;
+
+	pDriver_adapter = pHalmac_adapter->pDriver_adapter;
+
+	rsvd_buf = (u8 *)PLATFORM_RTL_MALLOC(pDriver_adapter, h2c_pkt_verify_size);
+
+	if (NULL == rsvd_buf) {
+		PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "[ERR]rsvd buffer malloc fail!!\n");
+		return HALMAC_RET_MALLOC_FAIL;
+	}
+
+	PLATFORM_RTL_MEMSET(pDriver_adapter, rsvd_buf, (u8)h2c_pkt_verify_payload, h2c_pkt_verify_size);
+
+	ret_status = halmac_download_rsvd_page_88xx(pHalmac_adapter, rsvd_buf, h2c_pkt_verify_size);
+
+	if (HALMAC_RET_SUCCESS != ret_status) {
+		PLATFORM_RTL_FREE(pDriver_adapter, rsvd_buf, h2c_pkt_verify_size);
+		return ret_status;
+	}
+
+	rsvd_page = (u8 *)PLATFORM_RTL_MALLOC(pDriver_adapter, h2c_pkt_verify_size + pHalmac_adapter->hw_config_info.txdesc_size);
+
+	if (NULL == rsvd_page) {
+		PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "[ERR]rsvd page malloc fail!!\n");
+		PLATFORM_RTL_FREE(pDriver_adapter, rsvd_buf, h2c_pkt_verify_size);
+		return HALMAC_RET_MALLOC_FAIL;
+	}
+
+	PLATFORM_RTL_MEMSET(pDriver_adapter, rsvd_page, 0x00, h2c_pkt_verify_size + pHalmac_adapter->hw_config_info.txdesc_size);
+
+	ret_status = halmac_dump_fifo_88xx(pHalmac_adapter, HAL_FIFO_SEL_RSVD_PAGE, 0, h2c_pkt_verify_size + pHalmac_adapter->hw_config_info.txdesc_size, rsvd_page);
+
+	if (HALMAC_RET_SUCCESS != ret_status) {
+		PLATFORM_RTL_FREE(pDriver_adapter, rsvd_buf, h2c_pkt_verify_size);
+		PLATFORM_RTL_FREE(pDriver_adapter, rsvd_page, h2c_pkt_verify_size + pHalmac_adapter->hw_config_info.txdesc_size);
+		return ret_status;
+	}
+
+	for (i = 0; i < h2c_pkt_verify_size; i++) {
+		if (*(rsvd_buf + i) != *(rsvd_page + (i + pHalmac_adapter->hw_config_info.txdesc_size))) {
+			PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "[ERR]Compare RSVD page Fail\n");
+			ret_status = HALMAC_RET_PLATFORM_API_INCORRECT;
+		}
+	}
+
+	PLATFORM_RTL_FREE(pDriver_adapter, rsvd_buf, h2c_pkt_verify_size);
+	PLATFORM_RTL_FREE(pDriver_adapter, rsvd_page, h2c_pkt_verify_size + pHalmac_adapter->hw_config_info.txdesc_size);
+
+	return ret_status;
+}
+
+VOID
+halmac_power_save_cb_88xx(
+	IN VOID *CbData
+)
+{
+	VOID *pDriver_adapter = NULL;
+	PHALMAC_ADAPTER pHalmac_adapter = (PHALMAC_ADAPTER)NULL;
+
+	pHalmac_adapter = (PHALMAC_ADAPTER)CbData;
+	pDriver_adapter = pHalmac_adapter->pDriver_adapter;
+
+	PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_PWR, HALMAC_DBG_TRACE, "halmac_power_save_cb_88xx\n");
+}
+
+HALMAC_RET_STATUS
+halmac_buffer_read_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN u32 offset,
+	IN u32 size,
+	IN HAL_FIFO_SEL halmac_fifo_sel,
+	OUT u8 *pFifo_map
+)
+{
+	u32 start_page, value_read;
+	u32 i, counter = 0, residue;
+	PHALMAC_API pHalmac_api;
+
+	pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api;
+
+	if (HAL_FIFO_SEL_RSVD_PAGE == halmac_fifo_sel)
+		offset = offset + (pHalmac_adapter->txff_allocation.rsvd_pg_bndy << HALMAC_TX_PAGE_SIZE_2_POWER_88XX);
+
+	start_page = offset >> 12;
+	residue = offset & (4096 - 1);
+
+	if ((HAL_FIFO_SEL_TX == halmac_fifo_sel) || (HAL_FIFO_SEL_RSVD_PAGE == halmac_fifo_sel))
+		start_page += 0x780;
+	else if (HAL_FIFO_SEL_RX == halmac_fifo_sel)
+		start_page += 0x700;
+	else if (HAL_FIFO_SEL_REPORT == halmac_fifo_sel)
+		start_page += 0x660;
+	else if (HAL_FIFO_SEL_LLT == halmac_fifo_sel)
+		start_page += 0x650;
+	else
+		return HALMAC_RET_NOT_SUPPORT;
+
+	value_read = HALMAC_REG_READ_16(pHalmac_adapter, REG_PKTBUF_DBG_CTRL);
+
+	do {
+		HALMAC_REG_WRITE_16(pHalmac_adapter, REG_PKTBUF_DBG_CTRL, (u16)(start_page | (value_read & 0xF000)));
+
+		for (i = 0x8000 + residue; i <= 0x8FFF; i += 4) {
+			*(u32 *)(pFifo_map + counter) = HALMAC_REG_READ_32(pHalmac_adapter, i);
+			*(u32 *)(pFifo_map + counter) = rtk_le32_to_cpu(*(u32 *)(pFifo_map + counter));
+			counter += 4;
+			if (size == counter)
+				goto HALMAC_BUF_READ_OK;
+		}
+
+		residue = 0;
+		start_page++;
+	} while (1);
+
+HALMAC_BUF_READ_OK:
+	HALMAC_REG_WRITE_16(pHalmac_adapter, REG_PKTBUF_DBG_CTRL, (u16)value_read);
+
+	return HALMAC_RET_SUCCESS;
+}
+
+VOID
+halmac_restore_mac_register_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN PHALMAC_RESTORE_INFO pRestore_info,
+	IN u32 restore_num
+)
+{
+	u8 value_length;
+	u32 i;
+	u32 mac_register;
+	u32 mac_value;
+	PHALMAC_API pHalmac_api;
+	PHALMAC_RESTORE_INFO pCurr_restore_info = pRestore_info;
+
+	pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api;
+
+	for (i = 0; i < restore_num; i++) {
+		mac_register = pCurr_restore_info->mac_register;
+		mac_value = pCurr_restore_info->value;
+		value_length = pCurr_restore_info->length;
+
+		if (1 == value_length)
+			HALMAC_REG_WRITE_8(pHalmac_adapter, mac_register, (u8)mac_value);
+		else if (2 == value_length)
+			HALMAC_REG_WRITE_16(pHalmac_adapter, mac_register, (u16)mac_value);
+		else if (4 == value_length)
+			HALMAC_REG_WRITE_32(pHalmac_adapter, mac_register, mac_value);
+
+		pCurr_restore_info++;
+	}
+}
+
+VOID
+halmac_api_record_id_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN HALMAC_API_ID api_id
+)
+{
+
+}
+
+HALMAC_RET_STATUS
+halmac_set_usb_mode_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN HALMAC_USB_MODE usb_mode
+)
+{
+	u32 usb_temp;
+	VOID *pDriver_adapter = NULL;
+	PHALMAC_API pHalmac_api;
+	HALMAC_USB_MODE current_usb_mode;
+
+	pDriver_adapter = pHalmac_adapter->pDriver_adapter;
+	pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api;
+
+	current_usb_mode = (HALMAC_REG_READ_8(pHalmac_adapter, REG_SYS_CFG2 + 3) == 0x20) ? HALMAC_USB_MODE_U3 : HALMAC_USB_MODE_U2;
+
+	/*check if HW supports usb2_usb3 swtich*/
+	usb_temp = HALMAC_REG_READ_32(pHalmac_adapter, REG_PAD_CTRL2);
+	if (_FALSE == (BIT_GET_USB23_SW_MODE_V1(usb_temp) | (usb_temp & BIT_USB3_USB2_TRANSITION))) {
+		PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "HALMAC_HW_USB_MODE usb mode HW unsupport\n");
+		return HALMAC_RET_USB2_3_SWITCH_UNSUPPORT;
+	}
+
+	if (usb_mode == current_usb_mode) {
+		PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "HALMAC_HW_USB_MODE usb mode unchange\n");
+		return HALMAC_RET_USB_MODE_UNCHANGE;
+	}
+
+	usb_temp &= ~(BIT_USB23_SW_MODE_V1(0x3));
+
+	if (HALMAC_USB_MODE_U2 == usb_mode) {
+		/* usb3 to usb2 */
+		HALMAC_REG_WRITE_32(pHalmac_adapter, REG_PAD_CTRL2, usb_temp | BIT_USB23_SW_MODE_V1(HALMAC_USB_MODE_U2) | BIT_RSM_EN_V1);
+	} else {
+		/* usb2 to usb3 */
+		HALMAC_REG_WRITE_32(pHalmac_adapter, REG_PAD_CTRL2, usb_temp | BIT_USB23_SW_MODE_V1(HALMAC_USB_MODE_U3) | BIT_RSM_EN_V1);
+	}
+
+	HALMAC_REG_WRITE_8(pHalmac_adapter, REG_PAD_CTRL2 + 1, 4); /* set counter down timer 4x64 ms */
+	HALMAC_REG_WRITE_16(pHalmac_adapter, REG_SYS_PW_CTRL, HALMAC_REG_READ_16(pHalmac_adapter, REG_SYS_PW_CTRL) | BIT_APFM_OFFMAC);
+	PLATFORM_RTL_DELAY_US(pDriver_adapter, 1000);
+	HALMAC_REG_WRITE_32(pHalmac_adapter, REG_PAD_CTRL2, HALMAC_REG_READ_32(pHalmac_adapter, REG_PAD_CTRL2) | BIT_NO_PDN_CHIPOFF_V1);
+
+	return HALMAC_RET_SUCCESS;
+}
+
+VOID
+halmac_enable_bb_rf_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN u8 enable
+)
+{
+	u8 value8;
+	u32 value32;
+	PHALMAC_API pHalmac_api;
+
+	pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api;
+
+	if (1 == enable) {
+		value8 = HALMAC_REG_READ_8(pHalmac_adapter, REG_SYS_FUNC_EN);
+		value8 = value8 | BIT(0) | BIT(1);
+		HALMAC_REG_WRITE_8(pHalmac_adapter, REG_SYS_FUNC_EN, value8);
+
+		value8 = HALMAC_REG_READ_8(pHalmac_adapter, REG_RF_CTRL);
+		value8 = value8 | BIT(0) | BIT(1) | BIT(2);
+		HALMAC_REG_WRITE_8(pHalmac_adapter, REG_RF_CTRL, value8);
+
+		value32 = HALMAC_REG_READ_32(pHalmac_adapter, REG_WLRF1);
+		value32 = value32 | BIT(24) | BIT(25) | BIT(26);
+		HALMAC_REG_WRITE_32(pHalmac_adapter, REG_WLRF1, value32);
+	} else {
+		value8 = HALMAC_REG_READ_8(pHalmac_adapter, REG_SYS_FUNC_EN);
+		value8 = value8 & (~(BIT(0) | BIT(1)));
+		HALMAC_REG_WRITE_8(pHalmac_adapter, REG_SYS_FUNC_EN, value8);
+
+		value8 = HALMAC_REG_READ_8(pHalmac_adapter, REG_RF_CTRL);
+		value8 = value8 & (~(BIT(0) | BIT(1) | BIT(2)));
+		HALMAC_REG_WRITE_8(pHalmac_adapter, REG_RF_CTRL, value8);
+
+		value32 = HALMAC_REG_READ_32(pHalmac_adapter, REG_WLRF1);
+		value32 = value32 & (~(BIT(24) | BIT(25) | BIT(26)));
+		HALMAC_REG_WRITE_32(pHalmac_adapter, REG_WLRF1, value32);
+	}
+}
+
+VOID
+halmac_config_sdio_tx_page_threshold_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN PHALMAC_TX_PAGE_THRESHOLD_INFO pThreshold_info
+)
+{
+	PHALMAC_API pHalmac_api;
+
+	pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api;
+
+	switch (pThreshold_info->dma_queue_sel) {
+	case HALMAC_MAP2_HQ:
+			HALMAC_REG_WRITE_32(pHalmac_adapter, REG_TQPNT1, pThreshold_info->threshold);
+		break;
+	case HALMAC_MAP2_NQ:
+			HALMAC_REG_WRITE_32(pHalmac_adapter, REG_TQPNT2, pThreshold_info->threshold);
+		break;
+	case HALMAC_MAP2_LQ:
+			HALMAC_REG_WRITE_32(pHalmac_adapter, REG_TQPNT3, pThreshold_info->threshold);
+		break;
+	case HALMAC_MAP2_EXQ:
+			HALMAC_REG_WRITE_32(pHalmac_adapter, REG_TQPNT4, pThreshold_info->threshold);
+		break;
+	default:
+		break;
+	}
+}
+
+VOID
+halmac_config_ampdu_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN PHALMAC_AMPDU_CONFIG pAmpdu_config
+)
+{
+	PHALMAC_API pHalmac_api;
+
+	pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api;
+
+	HALMAC_REG_WRITE_8(pHalmac_adapter, REG_PROT_MODE_CTRL + 2, pAmpdu_config->max_agg_num);
+	HALMAC_REG_WRITE_8(pHalmac_adapter, REG_PROT_MODE_CTRL + 3, pAmpdu_config->max_agg_num);
+};
+
+HALMAC_RET_STATUS
+halmac_check_oqt_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN u32 tx_agg_num,
+	IN u8 *pHalmac_buf
+)
+{
+	u32 counter = 10;
+
+	/*S0, S1 are not allowed to use, 0x4E4[0] should be 0. Soar 20160323*/
+	/*no need to check non_ac_oqt_number. HI and MGQ blocked will cause protocal issue before H_OQT being full*/
+	switch ((HALMAC_QUEUE_SELECT)GET_TX_DESC_QSEL(pHalmac_buf)) {
+	case HALMAC_QUEUE_SELECT_VO:
+	case HALMAC_QUEUE_SELECT_VO_V2:
+	case HALMAC_QUEUE_SELECT_VI:
+	case HALMAC_QUEUE_SELECT_VI_V2:
+	case HALMAC_QUEUE_SELECT_BE:
+	case HALMAC_QUEUE_SELECT_BE_V2:
+	case HALMAC_QUEUE_SELECT_BK:
+	case HALMAC_QUEUE_SELECT_BK_V2:
+		counter = 10;
+		do {
+			if (pHalmac_adapter->sdio_free_space.ac_empty > 0) {
+				pHalmac_adapter->sdio_free_space.ac_empty -= 1;
+				break;
+			}
+
+			if (pHalmac_adapter->sdio_free_space.ac_oqt_number >= tx_agg_num) {
+				pHalmac_adapter->sdio_free_space.ac_oqt_number -= (u8)tx_agg_num;
+				break;
+			}
+
+			halmac_update_oqt_free_space_88xx(pHalmac_adapter);
+
+			counter--;
+			if (0 == counter)
+				return HALMAC_RET_OQT_NOT_ENOUGH;
+		} while (1);
+		break;
+	default:
+		break;
+	}
+
+	return HALMAC_RET_SUCCESS;
+}
+
+HALMAC_RET_STATUS
+halmac_rqpn_parser_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN HALMAC_TRX_MODE halmac_trx_mode,
+	IN PHALMAC_RQPN pRqpn_table
+)
+{
+	u8 search_flag;
+	u32 i;
+	VOID *pDriver_adapter = NULL;
+	PHALMAC_API pHalmac_api;
+
+	pDriver_adapter = pHalmac_adapter->pDriver_adapter;
+	pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api;
+
+	search_flag = 0;
+	for (i = 0; i < HALMAC_TRX_MODE_MAX; i++) {
+		if (halmac_trx_mode == pRqpn_table[i].mode) {
+			pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_VO] = pRqpn_table[i].dma_map_vo;
+			pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_VI] = pRqpn_table[i].dma_map_vi;
+			pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_BE] = pRqpn_table[i].dma_map_be;
+			pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_BK] = pRqpn_table[i].dma_map_bk;
+			pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_MG] = pRqpn_table[i].dma_map_mg;
+			pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_HI] = pRqpn_table[i].dma_map_hi;
+			search_flag = 1;
+			PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_rqpn_parser_88xx done\n");
+			break;
+		}
+	}
+
+	if (0 == search_flag) {
+		PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "HALMAC_RET_TRX_MODE_NOT_SUPPORT 1 switch case not support\n");
+		return HALMAC_RET_TRX_MODE_NOT_SUPPORT;
+	}
+
+	return HALMAC_RET_SUCCESS;
+}
+
+HALMAC_RET_STATUS
+halmac_pg_num_parser_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN HALMAC_TRX_MODE halmac_trx_mode,
+	IN PHALMAC_PG_NUM pPg_num_table
+)
+{
+	u8 search_flag;
+	u16 HPQ_num = 0, LPQ_Nnum = 0, NPQ_num = 0, GAPQ_num = 0;
+	u16 EXPQ_num = 0, PUBQ_num = 0;
+	u32 i = 0;
+	VOID *pDriver_adapter = NULL;
+	PHALMAC_API pHalmac_api;
+
+	pDriver_adapter = pHalmac_adapter->pDriver_adapter;
+	pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api;
+
+	search_flag = 0;
+	for (i = 0; i < HALMAC_TRX_MODE_MAX; i++) {
+		if (halmac_trx_mode == pPg_num_table[i].mode) {
+			HPQ_num = pPg_num_table[i].hq_num;
+			LPQ_Nnum = pPg_num_table[i].lq_num;
+			NPQ_num = pPg_num_table[i].nq_num;
+			EXPQ_num = pPg_num_table[i].exq_num;
+			GAPQ_num = pPg_num_table[i].gap_num;
+			PUBQ_num = pHalmac_adapter->txff_allocation.ac_q_pg_num - HPQ_num - LPQ_Nnum - NPQ_num - EXPQ_num - GAPQ_num;
+			search_flag = 1;
+			PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_pg_num_parser_88xx done\n");
+			break;
+		}
+	}
+
+	if (0 == search_flag) {
+		PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "HALMAC_RET_TRX_MODE_NOT_SUPPORT 1 switch case not support\n");
+		return HALMAC_RET_TRX_MODE_NOT_SUPPORT;
+	}
+
+	if (pHalmac_adapter->txff_allocation.ac_q_pg_num < HPQ_num + LPQ_Nnum + NPQ_num + EXPQ_num + GAPQ_num)
+		return HALMAC_RET_CFG_TXFIFO_PAGE_FAIL;
+
+	pHalmac_adapter->txff_allocation.high_queue_pg_num = HPQ_num;
+	pHalmac_adapter->txff_allocation.low_queue_pg_num = LPQ_Nnum;
+	pHalmac_adapter->txff_allocation.normal_queue_pg_num = NPQ_num;
+	pHalmac_adapter->txff_allocation.extra_queue_pg_num = EXPQ_num;
+	pHalmac_adapter->txff_allocation.pub_queue_pg_num = PUBQ_num;
+
+	return HALMAC_RET_SUCCESS;
+}
+
+HALMAC_RET_STATUS
+halmac_parse_intf_phy_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN PHALMAC_INTF_PHY_PARA pIntf_phy_para,
+	IN HALMAC_INTF_PHY_PLATFORM platform,
+	IN HAL_INTF_PHY intf_phy
+)
+{
+	u16 value;
+	u16 curr_cut;
+	u16 offset;
+	u16 ip_sel;
+	PHALMAC_INTF_PHY_PARA pCurr_phy_para;
+	PHALMAC_API pHalmac_api;
+	VOID *pDriver_adapter = NULL;
+	u8 result = HALMAC_RET_SUCCESS;
+
+	pDriver_adapter = pHalmac_adapter->pDriver_adapter;
+	pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api;
+
+	switch (pHalmac_adapter->chip_version) {
+	case HALMAC_CHIP_VER_A_CUT:
+		curr_cut = (u16)HALMAC_INTF_PHY_CUT_A;
+		break;
+	case HALMAC_CHIP_VER_B_CUT:
+		curr_cut = (u16)HALMAC_INTF_PHY_CUT_B;
+		break;
+	case HALMAC_CHIP_VER_C_CUT:
+		curr_cut = (u16)HALMAC_INTF_PHY_CUT_C;
+		break;
+	case HALMAC_CHIP_VER_D_CUT:
+		curr_cut = (u16)HALMAC_INTF_PHY_CUT_D;
+		break;
+	case HALMAC_CHIP_VER_E_CUT:
+		curr_cut = (u16)HALMAC_INTF_PHY_CUT_E;
+		break;
+	case HALMAC_CHIP_VER_F_CUT:
+		curr_cut = (u16)HALMAC_INTF_PHY_CUT_F;
+		break;
+	case HALMAC_CHIP_VER_TEST:
+		curr_cut = (u16)HALMAC_INTF_PHY_CUT_TESTCHIP;
+		break;
+	default:
+		return HALMAC_RET_FAIL;
+	}
+
+	pCurr_phy_para = pIntf_phy_para;
+
+	do {
+		if ((pCurr_phy_para->cut & curr_cut) && (pCurr_phy_para->plaform & (u16)platform)) {
+			offset =  pCurr_phy_para->offset;
+			value = pCurr_phy_para->value;
+			ip_sel = pCurr_phy_para->ip_sel;
+
+			if (0xFFFF == offset)
+				break;
+
+			if (HALMAC_IP_SEL_MAC == ip_sel) {
+				HALMAC_REG_WRITE_8(pHalmac_adapter, (u32)offset, (u8)value);
+			} else if (HAL_INTF_PHY_USB2 == intf_phy) {
+
+				result = halmac_usbphy_write_88xx(pHalmac_adapter, (u8)offset, value, HAL_INTF_PHY_USB2);
+
+				if (HALMAC_RET_SUCCESS != result)
+					PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_USB, HALMAC_DBG_ERR, "[ERR]Write USB2PHY fail!\n");
+
+			} else if (HAL_INTF_PHY_USB3 == intf_phy) {
+
+				result = halmac_usbphy_write_88xx(pHalmac_adapter, (u8)offset, value, HAL_INTF_PHY_USB3);
+
+				if (HALMAC_RET_SUCCESS != result)
+					PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_USB, HALMAC_DBG_ERR, "[ERR]Write USB3PHY fail!\n");
+
+			} else if (HAL_INTF_PHY_PCIE_GEN1 == intf_phy) {
+
+				if (HALMAC_IP_SEL_INTF_PHY == ip_sel)
+					result = halmac_mdio_write_88xx(pHalmac_adapter, (u8)offset, value, HAL_INTF_PHY_PCIE_GEN1);
+				else
+					result = halmac_dbi_write8_88xx(pHalmac_adapter, offset, (u8)value);
+
+				if (HALMAC_RET_SUCCESS != result)
+					PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_MDIO, HALMAC_DBG_ERR, "[ERR]MDIO write GEN1 fail!\n");
+
+			} else if (HAL_INTF_PHY_PCIE_GEN2 == intf_phy) {
+
+				if (HALMAC_IP_SEL_INTF_PHY == ip_sel)
+					result = halmac_mdio_write_88xx(pHalmac_adapter, (u8)offset, value, HAL_INTF_PHY_PCIE_GEN2);
+				else
+					result = halmac_dbi_write8_88xx(pHalmac_adapter, offset, (u8)value);
+
+				if (HALMAC_RET_SUCCESS != result)
+					PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_MDIO, HALMAC_DBG_ERR, "[ERR]MDIO write GEN2 fail!\n");
+			} else {
+				PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_COMMON, HALMAC_DBG_ERR, "[ERR]Parse intf phy cfg error!\n");
+			}
+
+		}
+		pCurr_phy_para++;
+	} while (1);
+
+	return HALMAC_RET_SUCCESS;
+}
+
+HALMAC_RET_STATUS
+halmac_dbi_write32_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN u16 addr,
+	IN u32 data
+)
+{
+	u8 tmp_u1b = 0;
+	u32 count = 0;
+	u16 write_addr = 0;
+	VOID *pDriver_adapter = NULL;
+	PHALMAC_API pHalmac_api;
+
+	pDriver_adapter = pHalmac_adapter->pDriver_adapter;
+	pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api;
+
+	HALMAC_REG_WRITE_32(pHalmac_adapter, REG_DBI_WDATA_V1, data);
+
+	write_addr = ((addr & 0x0ffc) | (0x000F << 12));
+	HALMAC_REG_WRITE_16(pHalmac_adapter, REG_DBI_FLAG_V1, write_addr);
+
+	PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_DBI, HALMAC_DBG_TRACE, "WriteAddr = %x\n", write_addr);
+
+	HALMAC_REG_WRITE_8(pHalmac_adapter, REG_DBI_FLAG_V1 + 2, 0x01);
+	tmp_u1b = HALMAC_REG_READ_8(pHalmac_adapter, REG_DBI_FLAG_V1 + 2);
+
+	count = 20;
+	while (tmp_u1b && (count != 0)) {
+		PLATFORM_RTL_DELAY_US(pDriver_adapter, 10);
+		tmp_u1b = HALMAC_REG_READ_8(pHalmac_adapter, REG_DBI_FLAG_V1 + 2);
+		count--;
+	}
+
+	if (tmp_u1b) {
+		PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_DBI, HALMAC_DBG_ERR, "DBI write fail!\n");
+		return HALMAC_RET_FAIL;
+	} else {
+		return HALMAC_RET_SUCCESS;
+	}
+
+}
+
+u32
+halmac_dbi_read32_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN u16 addr
+)
+{
+	u16 read_addr = addr & 0x0ffc;
+	u8 tmp_u1b = 0;
+	u32 count = 0;
+	u32 ret = 0;
+	VOID *pDriver_adapter = NULL;
+	PHALMAC_API pHalmac_api; ;
+
+	pDriver_adapter = pHalmac_adapter->pDriver_adapter;
+	pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api;
+
+
+	HALMAC_REG_WRITE_16(pHalmac_adapter, REG_DBI_FLAG_V1, read_addr);
+
+	HALMAC_REG_WRITE_8(pHalmac_adapter, REG_DBI_FLAG_V1 + 2, 0x2);
+	tmp_u1b = HALMAC_REG_READ_8(pHalmac_adapter, REG_DBI_FLAG_V1 + 2);
+
+	count = 20;
+	while (tmp_u1b && (count != 0)) {
+		PLATFORM_RTL_DELAY_US(pDriver_adapter, 10);
+		tmp_u1b = HALMAC_REG_READ_8(pHalmac_adapter, REG_DBI_FLAG_V1 + 2);
+		count--;
+	}
+
+	if (tmp_u1b) {
+		ret  = 0xFFFF;
+		PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_DBI, HALMAC_DBG_ERR, "DBI read fail!\n");
+	} else {
+		ret = HALMAC_REG_READ_32(pHalmac_adapter, REG_DBI_RDATA_V1);
+		PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_DBI, HALMAC_DBG_TRACE, "Read Value = %x\n", ret);
+	}
+
+	return ret;
+
+}
+
+
+HALMAC_RET_STATUS
+halmac_dbi_write8_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN u16 addr,
+	IN u8 data
+)
+{
+	u8 tmp_u1b = 0;
+	u32 count = 0;
+	u16 write_addr = 0;
+	u16 remainder = addr & (4 - 1);
+	VOID *pDriver_adapter = NULL;
+	PHALMAC_API pHalmac_api; ;
+
+	pDriver_adapter = pHalmac_adapter->pDriver_adapter;
+	pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api;
+
+	HALMAC_REG_WRITE_8(pHalmac_adapter, REG_DBI_WDATA_V1 + remainder, data);
+
+	write_addr = ((addr & 0x0ffc) | (BIT(0) << (remainder + 12)));
+
+	HALMAC_REG_WRITE_16(pHalmac_adapter, REG_DBI_FLAG_V1, write_addr);
+
+	PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_DBI, HALMAC_DBG_TRACE, "WriteAddr = %x\n", write_addr);
+
+	HALMAC_REG_WRITE_8(pHalmac_adapter, REG_DBI_FLAG_V1 + 2, 0x01);
+
+	tmp_u1b = HALMAC_REG_READ_8(pHalmac_adapter, REG_DBI_FLAG_V1 + 2);
+
+	count = 20;
+	while (tmp_u1b && (count != 0)) {
+		PLATFORM_RTL_DELAY_US(pDriver_adapter, 10);
+		tmp_u1b = HALMAC_REG_READ_8(pHalmac_adapter, REG_DBI_FLAG_V1+2);
+		count--;
+	}
+
+	if (tmp_u1b) {
+		PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_DBI, HALMAC_DBG_ERR, "DBI write fail!\n");
+		return HALMAC_RET_FAIL;
+	} else {
+
+		return HALMAC_RET_SUCCESS;
+	}
+
+}
+
+u8
+halmac_dbi_read8_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN u16 addr
+)
+{
+	u16 read_addr = addr & 0x0ffc;
+	u8 tmp_u1b = 0;
+	u32 count = 0;
+	u8 ret = 0;
+	VOID *pDriver_adapter = NULL;
+	PHALMAC_API pHalmac_api; ;
+
+	pDriver_adapter = pHalmac_adapter->pDriver_adapter;
+	pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api;
+
+
+	HALMAC_REG_WRITE_16(pHalmac_adapter, REG_DBI_FLAG_V1, read_addr);
+	HALMAC_REG_WRITE_8(pHalmac_adapter, REG_DBI_FLAG_V1 + 2, 0x2);
+
+	tmp_u1b = HALMAC_REG_READ_8(pHalmac_adapter, REG_DBI_FLAG_V1 + 2);
+
+	count = 20;
+	while (tmp_u1b && (count != 0)) {
+		PLATFORM_RTL_DELAY_US(pDriver_adapter, 10);
+		tmp_u1b = HALMAC_REG_READ_8(pHalmac_adapter, REG_DBI_FLAG_V1 + 2);
+		count--;
+	}
+
+	if (tmp_u1b) {
+		ret  = 0xFF;
+		PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_DBI, HALMAC_DBG_ERR, "DBI read fail!\n");
+	} else {
+		ret = HALMAC_REG_READ_8(pHalmac_adapter, REG_DBI_RDATA_V1 + (addr & (4 - 1)));
+		PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_DBI, HALMAC_DBG_TRACE, "Read Value = %x\n", ret);
+	}
+
+	return ret;
+
+}
+
+
+HALMAC_RET_STATUS
+halmac_mdio_write_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN u8 addr,
+	IN u16 data,
+	IN u8 speed
+)
+{
+	u8 tmp_u1b = 0;
+	u32 count = 0;
+	VOID *pDriver_adapter = NULL;
+	PHALMAC_API pHalmac_api;
+	u8 real_addr = 0;
+
+	pDriver_adapter = pHalmac_adapter->pDriver_adapter;
+	pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api;
+
+	HALMAC_REG_WRITE_16(pHalmac_adapter, REG_MDIO_V1, data);
+
+	/* address : 5bit */
+	real_addr = (addr & 0x1F);
+	HALMAC_REG_WRITE_8(pHalmac_adapter, REG_PCIE_MIX_CFG, real_addr);
+
+	if (HAL_INTF_PHY_PCIE_GEN1 == speed) {
+
+		/* GEN1 page 0 */
+		if (addr < 0x20) {
+
+			/* select MDIO PHY Addr : reg 0x3F8[28:24]=5'b00 */
+			HALMAC_REG_WRITE_8(pHalmac_adapter, REG_PCIE_MIX_CFG + 3, 0x00);
+
+		/* GEN1 page 1 */
+		} else {
+
+			/* select MDIO PHY Addr : reg 0x3F8[28:24]=5'b01 */
+			HALMAC_REG_WRITE_8(pHalmac_adapter, REG_PCIE_MIX_CFG + 3, 0x01);
+		}
+
+	} else if (HAL_INTF_PHY_PCIE_GEN2 == speed) {
+
+		/* GEN2 page 0 */
+		if (addr < 0x20) {
+
+			/* select MDIO PHY Addr : reg 0x3F8[28:24]=5'b10 */
+			HALMAC_REG_WRITE_8(pHalmac_adapter, REG_PCIE_MIX_CFG + 3, 0x02);
+
+		/* GEN2 page 1 */
+		} else {
+
+			/* select MDIO PHY Addr : reg 0x3F8[28:24]=5'b11 */
+			HALMAC_REG_WRITE_8(pHalmac_adapter, REG_PCIE_MIX_CFG + 3, 0x03);
+		}
+	} else {
+
+		PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_MDIO, HALMAC_DBG_ERR, "Error Speed !\n");
+	}
+
+	HALMAC_REG_WRITE_8(pHalmac_adapter, REG_PCIE_MIX_CFG, HALMAC_REG_READ_8(pHalmac_adapter, REG_PCIE_MIX_CFG) | BIT_MDIO_WFLAG_V1);
+
+	tmp_u1b = HALMAC_REG_READ_8(pHalmac_adapter, REG_PCIE_MIX_CFG) & BIT_MDIO_WFLAG_V1 ;
+	count = 20;
+
+	while (tmp_u1b && (count != 0)) {
+		PLATFORM_RTL_DELAY_US(pDriver_adapter, 10);
+		tmp_u1b = HALMAC_REG_READ_8(pHalmac_adapter, REG_PCIE_MIX_CFG) & BIT_MDIO_WFLAG_V1;
+		count--;
+	}
+
+	if (tmp_u1b) {
+		PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_MDIO, HALMAC_DBG_ERR, "MDIO write fail!\n");
+		return HALMAC_RET_FAIL;
+	} else {
+
+		return HALMAC_RET_SUCCESS;
+	}
+
+}
+
+
+
+u16
+halmac_mdio_read_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN u8 addr,
+	IN u8 speed
+
+)
+{
+	u16 ret = 0;
+	u8 tmp_u1b = 0;
+	u32 count = 0;
+	VOID *pDriver_adapter = NULL;
+	PHALMAC_API pHalmac_api;
+	u8 real_addr = 0;
+
+	pDriver_adapter = pHalmac_adapter->pDriver_adapter;
+	pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api;
+
+	/* address : 5bit */
+	real_addr = (addr & 0x1F);
+	HALMAC_REG_WRITE_8(pHalmac_adapter, REG_PCIE_MIX_CFG, real_addr);
+
+	if (HAL_INTF_PHY_PCIE_GEN1 == speed) {
+		/* GEN1 page 0 */
+		if (addr < 0x20) {
+
+			/* select MDIO PHY Addr : reg 0x3F8[28:24]=5'b00 */
+			HALMAC_REG_WRITE_8(pHalmac_adapter, REG_PCIE_MIX_CFG + 3, 0x00);
+
+		/* GEN1 page 1 */
+		} else {
+
+			/* select MDIO PHY Addr : reg 0x3F8[28:24]=5'b01 */
+			HALMAC_REG_WRITE_8(pHalmac_adapter, REG_PCIE_MIX_CFG + 3, 0x01);
+		}
+
+	} else if (HAL_INTF_PHY_PCIE_GEN2 == speed) {
+
+		/* GEN2 page 0 */
+		if (addr < 0x20) {
+
+			/* select MDIO PHY Addr : reg 0x3F8[28:24]=5'b10 */
+			HALMAC_REG_WRITE_8(pHalmac_adapter, REG_PCIE_MIX_CFG + 3, 0x02);
+
+		/* GEN2 page 1 */
+		} else {
+
+			/* select MDIO PHY Addr : reg 0x3F8[28:24]=5'b11 */
+			HALMAC_REG_WRITE_8(pHalmac_adapter, REG_PCIE_MIX_CFG + 3, 0x03);
+		}
+	} else {
+
+		PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_MDIO, HALMAC_DBG_ERR, "Error Speed !\n");
+	}
+
+	HALMAC_REG_WRITE_8(pHalmac_adapter, REG_PCIE_MIX_CFG, HALMAC_REG_READ_8(pHalmac_adapter, REG_PCIE_MIX_CFG) | BIT_MDIO_RFLAG_V1);
+
+	tmp_u1b = HALMAC_REG_READ_8(pHalmac_adapter, REG_PCIE_MIX_CFG) & BIT_MDIO_RFLAG_V1 ;
+	count = 20;
+
+	while (tmp_u1b && (count != 0)) {
+
+		PLATFORM_RTL_DELAY_US(pDriver_adapter, 10);
+		tmp_u1b = HALMAC_REG_READ_8(pHalmac_adapter, REG_PCIE_MIX_CFG) & BIT_MDIO_RFLAG_V1;
+		count--;
+	}
+
+	if (tmp_u1b) {
+		ret  = 0xFFFF;
+		PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_MDIO, HALMAC_DBG_ERR, "MDIO read fail!\n");
+
+	} else {
+		ret = HALMAC_REG_READ_16(pHalmac_adapter, REG_MDIO_V1+2);
+		PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_MDIO, HALMAC_DBG_TRACE, "Read Value = %x\n", ret);
+	}
+
+	return ret;
+}
+
+HALMAC_RET_STATUS
+halmac_usbphy_write_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN u8 addr,
+	IN u16 data,
+	IN u8 speed
+)
+{
+	VOID *pDriver_adapter = NULL;
+	PHALMAC_API pHalmac_api;
+
+	pDriver_adapter = pHalmac_adapter->pDriver_adapter;
+	pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api;
+
+	if (HAL_INTF_PHY_USB3 == speed) {
+		HALMAC_REG_WRITE_8(pHalmac_adapter, 0xff0d, (u8)data);
+		HALMAC_REG_WRITE_8(pHalmac_adapter, 0xff0e, (u8)(data>>8));
+		HALMAC_REG_WRITE_8(pHalmac_adapter, 0xff0c, addr|BIT(7));
+	} else if (HAL_INTF_PHY_USB2 == speed) {
+		HALMAC_REG_WRITE_8(pHalmac_adapter, 0xfe41, (u8)data);
+		HALMAC_REG_WRITE_8(pHalmac_adapter, 0xfe40, addr);
+		HALMAC_REG_WRITE_8(pHalmac_adapter, 0xfe42, 0x81);
+	} else {
+		PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_USB, HALMAC_DBG_ERR, "[ERR]Error USB Speed !\n");
+		return HALMAC_RET_NOT_SUPPORT;
+	}
+
+	return HALMAC_RET_SUCCESS;
+}
+
+u16
+halmac_usbphy_read_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN u8 addr,
+	IN u8 speed
+)
+{
+	VOID *pDriver_adapter = NULL;
+	PHALMAC_API pHalmac_api;
+	u16 value = 0;
+
+	pDriver_adapter = pHalmac_adapter->pDriver_adapter;
+	pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api;
+
+	if (HAL_INTF_PHY_USB3 == speed) {
+		HALMAC_REG_WRITE_8(pHalmac_adapter, 0xff0c, addr|BIT(6));
+		value = (u16)(HALMAC_REG_READ_32(pHalmac_adapter, 0xff0c)>>8);
+	} else if (HAL_INTF_PHY_USB2 == speed) {
+		if ((addr >= 0xE0) && (addr <= 0xFF))
+			addr -= 0x20;
+		if ((addr >= 0xC0) && (addr <= 0xDF)) {
+			HALMAC_REG_WRITE_8(pHalmac_adapter, 0xfe40, addr);
+			HALMAC_REG_WRITE_8(pHalmac_adapter, 0xfe42, 0x81);
+			value = HALMAC_REG_READ_8(pHalmac_adapter, 0xfe43);
+		} else {
+			PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_USB, HALMAC_DBG_ERR, "[ERR]Error USB2PHY offset!\n");
+			return HALMAC_RET_NOT_SUPPORT;
+		}
+	} else {
+		PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_USB, HALMAC_DBG_ERR, "[ERR]Error USB Speed !\n");
+		return HALMAC_RET_NOT_SUPPORT;
+	}
+
+	return value;
+}
+
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/halmac/halmac_88xx/halmac_func_88xx.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/halmac/halmac_88xx/halmac_func_88xx.h
--- linux-5.6.3/3rdparty/rtl8821ce/hal/halmac/halmac_88xx/halmac_func_88xx.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/halmac/halmac_88xx/halmac_func_88xx.h	2020-04-10 16:35:06.793658994 +0300
@@ -0,0 +1,522 @@
+#ifndef _HALMAC_FUNC_88XX_H_
+#define _HALMAC_FUNC_88XX_H_
+
+#include "../halmac_type.h"
+
+VOID
+halmac_init_offload_feature_state_machine_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter
+);
+
+HALMAC_RET_STATUS
+halmac_send_h2c_pkt_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN u8 *pHal_buff,
+	IN u32 size,
+	IN u8 ack
+);
+
+HALMAC_RET_STATUS
+halmac_download_rsvd_page_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN u8 *pHal_buf,
+	IN u32 size
+);
+
+HALMAC_RET_STATUS
+halmac_set_h2c_header_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	OUT u8 *pHal_h2c_hdr,
+	IN u16 *seq,
+	IN u8 ack
+);
+
+HALMAC_RET_STATUS
+halmac_set_fw_offload_h2c_header_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	OUT u8 *pHal_h2c_hdr,
+	IN PHALMAC_H2C_HEADER_INFO pH2c_header_info,
+	OUT u16 *pSeq_num
+);
+
+HALMAC_RET_STATUS
+halmac_dump_efuse_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN HALMAC_EFUSE_READ_CFG cfg
+);
+
+HALMAC_RET_STATUS
+halmac_func_read_efuse_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN u32 offset,
+	IN u32 size,
+	OUT u8 *pEfuse_map
+);
+
+HALMAC_RET_STATUS
+halmac_func_write_efuse_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN u32 offset,
+	IN u8 value
+);
+
+HALMAC_RET_STATUS
+halmac_func_switch_efuse_bank_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN HALMAC_EFUSE_BANK efuse_bank
+);
+
+HALMAC_RET_STATUS
+halmac_read_logical_efuse_map_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN u8 *pMap
+);
+
+HALMAC_RET_STATUS
+halmac_func_write_logical_efuse_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN u32 offset,
+	IN u8 value
+);
+
+HALMAC_RET_STATUS
+halmac_func_pg_efuse_by_map_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN PHALMAC_PG_EFUSE_INFO pPg_efuse_info,
+	IN HALMAC_EFUSE_READ_CFG cfg
+);
+
+HALMAC_RET_STATUS
+halmac_eeprom_parser_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN u8 *pPhysical_efuse_map,
+	OUT u8 *pLogical_efuse_map
+);
+
+HALMAC_RET_STATUS
+halmac_read_hw_efuse_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN u32 offset,
+	IN u32 size,
+	OUT u8 *pEfuse_map
+);
+
+HALMAC_RET_STATUS
+halmac_update_fw_info_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN u8 *pHamacl_fw,
+	IN u32 halmac_fw_size
+);
+
+HALMAC_RET_STATUS
+halmac_dlfw_to_mem_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN u8 *pRam_code,
+	IN u32 dest,
+	IN u32 code_size
+);
+
+HALMAC_RET_STATUS
+halmac_send_fwpkt_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN u8 *pRam_code,
+	IN u32 code_size
+);
+
+HALMAC_RET_STATUS
+halmac_iddma_dlfw_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN u32 source,
+	IN u32 dest,
+	IN u32 length,
+	IN u8 first
+);
+
+HALMAC_RET_STATUS
+halmac_check_fw_chksum_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN u32 memory_address
+);
+
+HALMAC_RET_STATUS
+halmac_dlfw_end_flow_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter
+);
+
+HALMAC_RET_STATUS
+halmac_free_dl_fw_end_flow_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter
+);
+
+HALMAC_RET_STATUS
+halmac_pwr_seq_parser_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN u8 cut,
+	IN u8 fab,
+	IN u8 intf,
+	IN PHALMAC_WLAN_PWR_CFG *ppPwr_seq_cfg
+
+);
+
+HALMAC_RET_STATUS
+halmac_get_h2c_buff_free_space_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter
+);
+
+HALMAC_RET_STATUS
+halmac_send_h2c_set_pwr_mode_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN PHALMAC_FWLPS_OPTION pHal_FwLps_Opt
+);
+
+HALMAC_RET_STATUS
+halmac_func_send_original_h2c_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN u8 *original_h2c,
+	IN u16 *seq,
+	IN u8 ack
+);
+
+HALMAC_RET_STATUS
+halmac_media_status_rpt_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN u8 op_mode,
+	IN u8 mac_id_ind,
+	IN u8 mac_id,
+	IN u8 mac_id_end
+);
+
+HALMAC_RET_STATUS
+halmac_send_h2c_update_datapack_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN HALMAC_DATA_TYPE halmac_data_type,
+	IN PHALMAC_PHY_PARAMETER_INFO para_info
+);
+
+HALMAC_RET_STATUS
+halmac_send_h2c_run_datapack_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN HALMAC_DATA_TYPE halmac_data_type
+);
+
+HALMAC_RET_STATUS
+halmac_send_bt_coex_cmd_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN u8 *pBt_buf,
+	IN u32 bt_size,
+	IN u8 ack
+);
+
+HALMAC_RET_STATUS
+halmac_func_ctrl_ch_switch_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN PHALMAC_CH_SWITCH_OPTION pCs_option
+);
+
+HALMAC_RET_STATUS
+halmac_func_send_general_info_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN PHALMAC_GENERAL_INFO pGeneral_info
+);
+
+HALMAC_RET_STATUS
+halmac_send_h2c_ps_tuning_para_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter
+);
+
+HALMAC_RET_STATUS
+halmac_parse_c2h_packet_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN u8 *halmac_buf,
+	IN u32 halmac_size
+);
+
+HALMAC_RET_STATUS
+halmac_send_h2c_update_packet_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN HALMAC_PACKET_ID pkt_id,
+	IN u8 *pkt,
+	IN u32 pkt_size
+);
+
+HALMAC_RET_STATUS
+halmac_send_h2c_phy_parameter_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN PHALMAC_PHY_PARAMETER_INFO para_info,
+	IN u8 full_fifo
+);
+
+HALMAC_RET_STATUS
+halmac_dump_physical_efuse_fw_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN u32 offset,
+	IN u32 Size,
+	OUT u8 *pEfuse_map
+);
+
+HALMAC_RET_STATUS
+halmac_send_h2c_update_bcn_parse_info_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN PHALMAC_BCN_IE_INFO pBcn_ie_info
+);
+
+HALMAC_RET_STATUS
+halmac_convert_to_sdio_bus_offset_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	INOUT u32 *halmac_offset
+);
+
+HALMAC_RET_STATUS
+halmac_update_sdio_free_page_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter
+);
+
+HALMAC_RET_STATUS
+halmac_update_oqt_free_space_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter
+);
+
+HALMAC_EFUSE_CMD_CONSTRUCT_STATE
+halmac_query_efuse_curr_state_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter
+);
+
+HALMAC_RET_STATUS
+halmac_transition_efuse_state_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN HALMAC_EFUSE_CMD_CONSTRUCT_STATE dest_state
+);
+
+HALMAC_CFG_PARA_CMD_CONSTRUCT_STATE
+halmac_query_cfg_para_curr_state_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter
+);
+
+HALMAC_RET_STATUS
+halmac_transition_cfg_para_state_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN HALMAC_CFG_PARA_CMD_CONSTRUCT_STATE dest_state
+);
+
+HALMAC_SCAN_CMD_CONSTRUCT_STATE
+halmac_query_scan_curr_state_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter
+);
+
+HALMAC_RET_STATUS
+halmac_transition_scan_state_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN HALMAC_SCAN_CMD_CONSTRUCT_STATE dest_state
+);
+
+HALMAC_RET_STATUS
+halmac_query_cfg_para_status_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	OUT HALMAC_CMD_PROCESS_STATUS *pProcess_status,
+	INOUT u8 *data,
+	INOUT u32 *size
+);
+
+HALMAC_RET_STATUS
+halmac_query_dump_physical_efuse_status_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	OUT HALMAC_CMD_PROCESS_STATUS *pProcess_status,
+	INOUT u8 *data,
+	INOUT u32 *size
+);
+
+HALMAC_RET_STATUS
+halmac_query_dump_logical_efuse_status_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	OUT HALMAC_CMD_PROCESS_STATUS *pProcess_status,
+	INOUT u8 *data,
+	INOUT u32 *size
+);
+
+HALMAC_RET_STATUS
+halmac_query_channel_switch_status_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	OUT HALMAC_CMD_PROCESS_STATUS *pProcess_status,
+	INOUT u8 *data,
+	INOUT u32 *size
+);
+
+HALMAC_RET_STATUS
+halmac_query_update_packet_status_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	OUT HALMAC_CMD_PROCESS_STATUS *pProcess_status,
+	INOUT u8 *data,
+	INOUT u32 *size
+);
+
+HALMAC_RET_STATUS
+halmac_query_iqk_status_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	OUT HALMAC_CMD_PROCESS_STATUS *pProcess_status,
+	INOUT u8 *data,
+	INOUT u32 *size
+);
+
+HALMAC_RET_STATUS
+halmac_query_power_tracking_status_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	OUT HALMAC_CMD_PROCESS_STATUS *pProcess_status,
+	INOUT u8 *data,
+	INOUT u32 *size
+);
+
+HALMAC_RET_STATUS
+halmac_query_psd_status_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	OUT HALMAC_CMD_PROCESS_STATUS *pProcess_status,
+	INOUT u8 *data,
+	INOUT u32 *size
+);
+
+HALMAC_RET_STATUS
+halmac_verify_io_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter
+);
+
+HALMAC_RET_STATUS
+halmac_verify_send_rsvd_page_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter
+);
+
+VOID
+halmac_power_save_cb_88xx(
+	IN VOID *CbData
+);
+
+HALMAC_RET_STATUS
+halmac_buffer_read_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN u32 offset,
+	IN u32 size,
+	IN HAL_FIFO_SEL halmac_fifo_sel,
+	OUT u8 *pFifo_map
+);
+
+VOID
+halmac_restore_mac_register_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN PHALMAC_RESTORE_INFO pRestore_info,
+	IN u32 restore_num
+);
+
+VOID
+halmac_api_record_id_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN HALMAC_API_ID api_id
+);
+
+HALMAC_RET_STATUS
+halmac_set_usb_mode_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN HALMAC_USB_MODE usb_mode
+);
+
+VOID
+halmac_enable_bb_rf_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN u8 enable
+);
+
+VOID
+halmac_config_sdio_tx_page_threshold_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN PHALMAC_TX_PAGE_THRESHOLD_INFO pThreshold_info
+);
+
+HALMAC_RET_STATUS
+halmac_rqpn_parser_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN HALMAC_TRX_MODE halmac_trx_mode,
+	IN PHALMAC_RQPN pPwr_seq_cfg
+);
+
+HALMAC_RET_STATUS
+halmac_check_oqt_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN u32 tx_agg_num,
+	IN u8 *pHalmac_buf
+);
+
+HALMAC_RET_STATUS
+halmac_pg_num_parser_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN HALMAC_TRX_MODE halmac_trx_mode,
+	IN PHALMAC_PG_NUM pPg_num_table
+);
+
+HALMAC_RET_STATUS
+halmac_parse_intf_phy_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN PHALMAC_INTF_PHY_PARA pIntf_phy_para,
+	IN HALMAC_INTF_PHY_PLATFORM platform,
+	IN HAL_INTF_PHY intf_phy
+);
+
+HALMAC_RET_STATUS
+halmac_dbi_write32_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN u16 addr,
+	IN u32 data
+);
+
+u32
+halmac_dbi_read32_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN u16 addr
+);
+
+HALMAC_RET_STATUS
+halmac_dbi_write8_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN u16 addr,
+	IN u8 data
+);
+
+u8
+halmac_dbi_read8_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN u16 addr
+);
+
+u16
+halmac_mdio_read_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN u8 addr,
+	IN u8 speed
+
+);
+
+HALMAC_RET_STATUS
+halmac_mdio_write_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN u8 addr,
+	IN u16 data,
+	IN u8 speed
+);
+
+VOID
+halmac_config_ampdu_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN PHALMAC_AMPDU_CONFIG pAmpdu_config
+);
+
+HALMAC_RET_STATUS
+halmac_usbphy_write_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN u8 addr,
+	IN u16 data,
+	IN u8 speed
+);
+
+u16
+halmac_usbphy_read_88xx(
+	IN PHALMAC_ADAPTER pHalmac_adapter,
+	IN u8 addr,
+	IN u8 speed
+);
+#endif /* _HALMAC_FUNC_88XX_H_ */
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/halmac/halmac_88xx/halmac_fw_88xx.c linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/halmac/halmac_88xx/halmac_fw_88xx.c
--- linux-5.6.3/3rdparty/rtl8821ce/hal/halmac/halmac_88xx/halmac_fw_88xx.c	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/halmac/halmac_88xx/halmac_fw_88xx.c	2020-04-10 16:35:06.793658994 +0300
@@ -0,0 +1,1167 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ ******************************************************************************/
+
+#include "halmac_fw_88xx.h"
+#include "halmac_88xx_cfg.h"
+#include "halmac_common_88xx.h"
+#include "halmac_init_88xx.h"
+
+#if HALMAC_88XX_SUPPORT
+
+#define DLFW_RESTORE_REG_NUM		6
+#define ILLEGAL_KEY_GROUP		0xFAAAAA00
+
+/* Max dlfw size can not over 31K, due to SDIO HW limitation */
+#define DLFW_PKT_SIZE_LIMIT		31744
+
+#define ID_INFORM_DLEMEM_RDY		0x80
+#define ID_INFORM_ENETR_CPU_SLEEP	0x20
+#define ID_CHECK_DLEMEM_RDY		0x80
+#define ID_CHECK_ENETR_CPU_SLEEP	0x05
+
+#define FW_STATUS_CHK_FATAL	(BIT(1) | BIT(20))
+#define FW_STATUS_CHK_ERR	(BIT(4) | BIT(5) | BIT(6) | BIT(7) | BIT(8) | \
+				 BIT(9) | BIT(12) | BIT(14) | BIT(15) | \
+				 BIT(16) | BIT(17) | BIT(18) | BIT(19) | \
+				 BIT(21) | BIT(22) | BIT(25))
+#define FW_STATUS_CHK_WARN	~(FW_STATUS_CHK_FATAL | FW_STATUS_CHK_ERR)
+
+struct halmac_backup_info {
+	u32 mac_register;
+	u32 value;
+	u8 length;
+};
+
+static enum halmac_ret_status
+update_fw_info_88xx(struct halmac_adapter *adapter, u8 *fw_bin);
+
+static void
+restore_mac_reg_88xx(struct halmac_adapter *adapter,
+		     struct halmac_backup_info *info, u32 num);
+
+static enum halmac_ret_status
+dlfw_to_mem_88xx(struct halmac_adapter *adapter, u8 *fw_bin, u32 src, u32 dest,
+		 u32 size);
+
+static enum halmac_ret_status
+dlfw_end_flow_88xx(struct halmac_adapter *adapter);
+
+static enum halmac_ret_status
+free_dl_fw_end_flow_88xx(struct halmac_adapter *adapter);
+
+static enum halmac_ret_status
+send_fwpkt_88xx(struct halmac_adapter *adapter, u16 pg_addr, u8 *fw_bin,
+		u32 size);
+
+static enum halmac_ret_status
+iddma_dlfw_88xx(struct halmac_adapter *adapter, u32 src, u32 dest, u32 len,
+		u8 first);
+
+static enum halmac_ret_status
+iddma_en_88xx(struct halmac_adapter *adapter, u32 src, u32 dest, u32 ctrl);
+
+static enum halmac_ret_status
+check_fw_chksum_88xx(struct halmac_adapter *adapter, u32 mem_addr);
+
+static void
+fw_fatal_status_debug_88xx(struct halmac_adapter *adapter);
+
+static enum halmac_ret_status
+start_dlfw_88xx(struct halmac_adapter *adapter, u8 *fw_bin, u32 size,
+		u32 dl_addr, u8 emem_only);
+
+static enum halmac_ret_status
+chk_fw_size_88xx(struct halmac_adapter *adapter, u8 *fw_bin, u32 size);
+
+static void
+chk_h2c_ver_88xx(struct halmac_adapter *adapter, u8 *fw_bin);
+
+static void
+wlan_cpu_en_88xx(struct halmac_adapter *adapter, u8 enable);
+
+static void
+pltfm_reset_88xx(struct halmac_adapter *adapter);
+
+static enum halmac_ret_status
+proc_send_general_info_88xx(struct halmac_adapter *adapter,
+			    struct halmac_general_info *info);
+
+static enum halmac_ret_status
+proc_send_phydm_info_88xx(struct halmac_adapter *adapter,
+			  struct halmac_general_info *info);
+
+/**
+ * download_firmware_88xx() - download Firmware
+ * @adapter : the adapter of halmac
+ * @fw_bin : firmware bin
+ * @size : firmware size
+ * Author : KaiYuan Chang/Ivan Lin
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+download_firmware_88xx(struct halmac_adapter *adapter, u8 *fw_bin, u32 size)
+{
+	u8 value8;
+	u32 bckp_idx = 0;
+	u32 lte_coex_backup = 0;
+	struct halmac_backup_info bckp[DLFW_RESTORE_REG_NUM];
+	enum halmac_ret_status status;
+	struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
+
+	if (adapter->halmac_state.mac_pwr == HALMAC_MAC_POWER_OFF)
+		return HALMAC_RET_POWER_STATE_INVALID;
+
+	PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
+
+	status = chk_fw_size_88xx(adapter, fw_bin, size);
+	if (status != HALMAC_RET_SUCCESS)
+		return status;
+
+	chk_h2c_ver_88xx(adapter, fw_bin);
+
+	if (adapter->halmac_state.wlcpu_mode == HALMAC_WLCPU_ENTER_SLEEP)
+		PLTFM_MSG_WARN("[WARN]Enter Sleep..zZZ\n");
+
+	adapter->halmac_state.dlfw_state = HALMAC_DLFW_NONE;
+
+	status = ltecoex_reg_read_88xx(adapter, 0x38, &lte_coex_backup);
+	if (status != HALMAC_RET_SUCCESS)
+		return status;
+
+	wlan_cpu_en_88xx(adapter, 0);
+
+	/* set HIQ to hi priority */
+	bckp[bckp_idx].length = 1;
+	bckp[bckp_idx].mac_register = REG_TXDMA_PQ_MAP + 1;
+	bckp[bckp_idx].value = HALMAC_REG_R8(REG_TXDMA_PQ_MAP + 1);
+	bckp_idx++;
+	value8 = HALMAC_DMA_MAPPING_HIGH << 6;
+	HALMAC_REG_W8(REG_TXDMA_PQ_MAP + 1, value8);
+
+	/* DLFW only use HIQ, map HIQ to hi priority */
+	adapter->pq_map[HALMAC_PQ_MAP_HI] = HALMAC_DMA_MAPPING_HIGH;
+	bckp[bckp_idx].length = 1;
+	bckp[bckp_idx].mac_register = REG_CR;
+	bckp[bckp_idx].value = HALMAC_REG_R8(REG_CR);
+	bckp_idx++;
+	bckp[bckp_idx].length = 4;
+	bckp[bckp_idx].mac_register = REG_H2CQ_CSR;
+	bckp[bckp_idx].value = BIT(31);
+	bckp_idx++;
+	value8 = BIT_HCI_TXDMA_EN | BIT_TXDMA_EN;
+	HALMAC_REG_W8(REG_CR, value8);
+	HALMAC_REG_W32(REG_H2CQ_CSR, BIT(31));
+
+	/* Config hi priority queue and public priority queue page number */
+	bckp[bckp_idx].length = 2;
+	bckp[bckp_idx].mac_register = REG_FIFOPAGE_INFO_1;
+	bckp[bckp_idx].value = HALMAC_REG_R16(REG_FIFOPAGE_INFO_1);
+	bckp_idx++;
+	bckp[bckp_idx].length = 4;
+	bckp[bckp_idx].mac_register = REG_RQPN_CTRL_2;
+	bckp[bckp_idx].value = HALMAC_REG_R32(REG_RQPN_CTRL_2) | BIT(31);
+	bckp_idx++;
+	HALMAC_REG_W16(REG_FIFOPAGE_INFO_1, 0x200);
+	HALMAC_REG_W32(REG_RQPN_CTRL_2, bckp[bckp_idx - 1].value);
+
+	/* Disable beacon related functions */
+	value8 = HALMAC_REG_R8(REG_BCN_CTRL);
+	bckp[bckp_idx].length = 1;
+	bckp[bckp_idx].mac_register = REG_BCN_CTRL;
+	bckp[bckp_idx].value = value8;
+	bckp_idx++;
+	value8 = (u8)((value8 & (~BIT(3))) | BIT(4));
+	HALMAC_REG_W8(REG_BCN_CTRL, value8);
+
+	if (adapter->intf == HALMAC_INTERFACE_SDIO)
+		HALMAC_REG_R32(REG_SDIO_FREE_TXPG);
+
+	pltfm_reset_88xx(adapter);
+
+	status = start_dlfw_88xx(adapter, fw_bin, size, 0, 0);
+
+	restore_mac_reg_88xx(adapter, bckp, DLFW_RESTORE_REG_NUM);
+
+	if (status != HALMAC_RET_SUCCESS)
+		goto DLFW_FAIL;
+
+	status = dlfw_end_flow_88xx(adapter);
+	if (status != HALMAC_RET_SUCCESS)
+		goto DLFW_FAIL;
+
+	status = ltecoex_reg_write_88xx(adapter, 0x38, lte_coex_backup);
+	if (status != HALMAC_RET_SUCCESS)
+		return status;
+
+	adapter->halmac_state.dlfw_state = HALMAC_DLFW_DONE;
+
+	PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
+
+	return HALMAC_RET_SUCCESS;
+
+DLFW_FAIL:
+
+	/* Disable FWDL_EN */
+	value8 = HALMAC_REG_R8(REG_MCUFW_CTRL);
+	value8 &= ~BIT(0);
+	HALMAC_REG_W8(REG_MCUFW_CTRL, value8);
+
+	value8 = HALMAC_REG_R8(REG_SYS_FUNC_EN + 1);
+	value8 |= BIT(2);
+	HALMAC_REG_W8(REG_SYS_FUNC_EN + 1, value8);
+
+	if (ltecoex_reg_write_88xx(adapter, 0x38, lte_coex_backup) !=
+	    HALMAC_RET_SUCCESS)
+		return HALMAC_RET_LTECOEX_READY_FAIL;
+
+	return status;
+}
+
+static enum halmac_ret_status
+start_dlfw_88xx(struct halmac_adapter *adapter, u8 *fw_bin, u32 size,
+		u32 dl_addr, u8 emem_only)
+{
+	u8 *cur_fw;
+	u16 value16;
+	u32 imem_size;
+	u32 dmem_size;
+	u32 emem_size = 0;
+	u32 addr;
+	struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
+	enum halmac_ret_status status;
+
+	dmem_size =
+		rtk_le32_to_cpu(*((__le32 *)(fw_bin + WLAN_FW_HDR_DMEM_SIZE)));
+	imem_size =
+		rtk_le32_to_cpu(*((__le32 *)(fw_bin + WLAN_FW_HDR_IMEM_SIZE)));
+	if (0 != ((*(fw_bin + WLAN_FW_HDR_MEM_USAGE)) & BIT(4)))
+		emem_size =
+		rtk_le32_to_cpu(*((__le32 *)(fw_bin + WLAN_FW_HDR_EMEM_SIZE)));
+
+	dmem_size += WLAN_FW_HDR_CHKSUM_SIZE;
+	imem_size += WLAN_FW_HDR_CHKSUM_SIZE;
+	if (emem_size != 0)
+		emem_size += WLAN_FW_HDR_CHKSUM_SIZE;
+
+	if (emem_only == 1) {
+		if (!emem_size)
+			return HALMAC_RET_SUCCESS;
+		goto DLFW_EMEM;
+	}
+
+	value16 = (u16)(HALMAC_REG_R16(REG_MCUFW_CTRL) & 0x3800);
+	value16 |= BIT(0);
+	HALMAC_REG_W16(REG_MCUFW_CTRL, value16);
+
+	cur_fw = fw_bin + WLAN_FW_HDR_SIZE;
+	addr = rtk_le32_to_cpu(*((__le32 *)(fw_bin + WLAN_FW_HDR_DMEM_ADDR)));
+	addr &= ~BIT(31);
+	status = dlfw_to_mem_88xx(adapter, cur_fw, 0, addr, dmem_size);
+	if (status != HALMAC_RET_SUCCESS)
+		return status;
+
+	cur_fw = fw_bin + WLAN_FW_HDR_SIZE + dmem_size;
+	addr = rtk_le32_to_cpu(*((__le32 *)(fw_bin + WLAN_FW_HDR_IMEM_ADDR)));
+	addr &= ~BIT(31);
+	status = dlfw_to_mem_88xx(adapter, cur_fw, 0, addr, imem_size);
+	if (status != HALMAC_RET_SUCCESS)
+		return status;
+
+DLFW_EMEM:
+	if (emem_size) {
+		cur_fw = fw_bin + WLAN_FW_HDR_SIZE +
+				dmem_size + imem_size;
+		addr = rtk_le32_to_cpu(*((__le32 *)(fw_bin +
+				       WLAN_FW_HDR_EMEM_ADDR)));
+		addr &= ~BIT(31);
+		status = dlfw_to_mem_88xx(adapter, cur_fw, dl_addr << 7, addr,
+					  emem_size);
+		if (status != HALMAC_RET_SUCCESS)
+			return status;
+
+		if (emem_only == 1)
+			return HALMAC_RET_SUCCESS;
+	}
+
+	update_fw_info_88xx(adapter, fw_bin);
+	init_ofld_feature_state_machine_88xx(adapter);
+
+	return HALMAC_RET_SUCCESS;
+}
+
+static void
+chk_h2c_ver_88xx(struct halmac_adapter *adapter, u8 *fw_bin)
+{
+	u16 halmac_h2c_ver;
+	u16 fw_h2c_ver;
+
+	fw_h2c_ver = rtk_le16_to_cpu(*((__le16 *)(fw_bin +
+						  WLAN_FW_HDR_H2C_FMT_VER)));
+	halmac_h2c_ver = H2C_FORMAT_VERSION;
+
+	PLTFM_MSG_TRACE("[TRACE]halmac h2c ver = %x, fw h2c ver = %x!!\n",
+			halmac_h2c_ver, fw_h2c_ver);
+}
+
+static enum halmac_ret_status
+chk_fw_size_88xx(struct halmac_adapter *adapter, u8 *fw_bin, u32 size)
+{
+	u32 imem_size;
+	u32 dmem_size;
+	u32 emem_size = 0;
+	u32 real_size;
+
+	if (size < WLAN_FW_HDR_SIZE) {
+		PLTFM_MSG_ERR("[ERR]FW size error!\n");
+		return HALMAC_RET_FW_SIZE_ERR;
+	}
+
+	dmem_size =
+		rtk_le32_to_cpu(*((__le32 *)(fw_bin + WLAN_FW_HDR_DMEM_SIZE)));
+	imem_size =
+		rtk_le32_to_cpu(*((__le32 *)(fw_bin + WLAN_FW_HDR_IMEM_SIZE)));
+	if (0 != ((*(fw_bin + WLAN_FW_HDR_MEM_USAGE)) & BIT(4)))
+		emem_size =
+		rtk_le32_to_cpu(*((__le32 *)(fw_bin + WLAN_FW_HDR_EMEM_SIZE)));
+
+	dmem_size += WLAN_FW_HDR_CHKSUM_SIZE;
+	imem_size += WLAN_FW_HDR_CHKSUM_SIZE;
+	if (emem_size != 0)
+		emem_size += WLAN_FW_HDR_CHKSUM_SIZE;
+
+	real_size = WLAN_FW_HDR_SIZE + dmem_size + imem_size + emem_size;
+	if (size != real_size) {
+		PLTFM_MSG_ERR("[ERR]size != real size!\n");
+		return HALMAC_RET_FW_SIZE_ERR;
+	}
+
+	return HALMAC_RET_SUCCESS;
+}
+
+static void
+wlan_cpu_en_88xx(struct halmac_adapter *adapter, u8 enable)
+{
+	u8 value8;
+	struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
+
+	if (enable == 1) {
+		/* cpu io interface enable or disable */
+		value8 = HALMAC_REG_R8(REG_RSV_CTRL + 1);
+		value8 |= BIT(0);
+		HALMAC_REG_W8(REG_RSV_CTRL + 1, value8);
+
+		/* cpu enable or disable */
+		value8 = HALMAC_REG_R8(REG_SYS_FUNC_EN + 1);
+		value8 |= BIT(2);
+		HALMAC_REG_W8(REG_SYS_FUNC_EN + 1, value8);
+
+	} else {
+		/* cpu enable or disable */
+		value8 = HALMAC_REG_R8(REG_SYS_FUNC_EN + 1);
+		value8 &= ~BIT(2);
+		HALMAC_REG_W8(REG_SYS_FUNC_EN + 1, value8);
+
+		/* cpu io interface enable or disable */
+		value8 = HALMAC_REG_R8(REG_RSV_CTRL + 1);
+		value8 &= ~BIT(0);
+		HALMAC_REG_W8(REG_RSV_CTRL + 1, value8);
+	}
+}
+
+static void
+pltfm_reset_88xx(struct halmac_adapter *adapter)
+{
+	u8 value8;
+	struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
+
+	value8 = HALMAC_REG_R8(REG_CPU_DMEM_CON + 2) & ~BIT(0);
+	HALMAC_REG_W8(REG_CPU_DMEM_CON + 2, value8);
+
+	/* For 8822B & 8821C clock sync issue */
+	if (adapter->chip_id == HALMAC_CHIP_ID_8821C ||
+	    adapter->chip_id == HALMAC_CHIP_ID_8822B) {
+		value8 = HALMAC_REG_R8(REG_SYS_CLK_CTRL + 1) & ~BIT(6);
+		HALMAC_REG_W8(REG_SYS_CLK_CTRL + 1, value8);
+	}
+
+	value8 = HALMAC_REG_R8(REG_CPU_DMEM_CON + 2) | BIT(0);
+	HALMAC_REG_W8(REG_CPU_DMEM_CON + 2, value8);
+
+	if (adapter->chip_id == HALMAC_CHIP_ID_8821C ||
+	    adapter->chip_id == HALMAC_CHIP_ID_8822B) {
+		value8 = HALMAC_REG_R8(REG_SYS_CLK_CTRL + 1) | BIT(6);
+		HALMAC_REG_W8(REG_SYS_CLK_CTRL + 1, value8);
+	}
+}
+
+/**
+ * free_download_firmware_88xx() - download specific memory firmware
+ * @adapter
+ * @mem_sel : memory selection
+ * @fw_bin : firmware bin
+ * @size : firmware size
+ * Author : KaiYuan Chang/Ivan Lin
+ * Return : enum halmac_ret_status
+ */
+enum halmac_ret_status
+free_download_firmware_88xx(struct halmac_adapter *adapter,
+			    enum halmac_dlfw_mem mem_sel, u8 *fw_bin, u32 size)
+{
+	u8 tx_pause_bckp;
+	u32 dl_addr;
+	u32 dlfw_size_bckp;
+	enum halmac_ret_status status;
+	struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
+
+	if (halmac_fw_validate(adapter) != HALMAC_RET_SUCCESS)
+		return HALMAC_RET_NO_DLFW;
+
+	PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
+
+	status = chk_fw_size_88xx(adapter, fw_bin, size);
+	if (status != HALMAC_RET_SUCCESS)
+		return status;
+
+	if (((*(fw_bin + WLAN_FW_HDR_MEM_USAGE)) & BIT(4)) == 0)
+		return HALMAC_RET_SUCCESS;
+
+	dlfw_size_bckp = adapter->dlfw_pkt_size;
+	if (mem_sel == HALMAC_DLFW_MEM_EMEM) {
+		dl_addr = 0;
+	} else {
+		dl_addr = adapter->txff_alloc.rsvd_h2c_info_addr;
+		adapter->dlfw_pkt_size = (dlfw_size_bckp > DLFW_RSVDPG_SIZE) ?
+					DLFW_RSVDPG_SIZE : dlfw_size_bckp;
+	}
+
+	tx_pause_bckp = HALMAC_REG_R8(REG_TXPAUSE);
+	HALMAC_REG_W8(REG_TXPAUSE, tx_pause_bckp | BIT(7));
+
+	status = start_dlfw_88xx(adapter, fw_bin, size, dl_addr, 1);
+	if (status != HALMAC_RET_SUCCESS)
+		goto DL_FREE_FW_END;
+
+	status = free_dl_fw_end_flow_88xx(adapter);
+
+DL_FREE_FW_END:
+	HALMAC_REG_W8(REG_TXPAUSE, tx_pause_bckp);
+	adapter->dlfw_pkt_size = dlfw_size_bckp;
+
+	PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
+
+	return status;
+}
+
+/**
+ * get_fw_version_88xx() - get FW version
+ * @adapter : the adapter of halmac
+ * @ver : fw version info
+ * Author : Ivan Lin
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+get_fw_version_88xx(struct halmac_adapter *adapter,
+		    struct halmac_fw_version *ver)
+{
+	struct halmac_fw_version *info = &adapter->fw_ver;
+
+	if (!ver)
+		return HALMAC_RET_NULL_POINTER;
+
+	if (adapter->halmac_state.dlfw_state == HALMAC_DLFW_NONE)
+		return HALMAC_RET_NO_DLFW;
+
+	ver->version = info->version;
+	ver->sub_version = info->sub_version;
+	ver->sub_index = info->sub_index;
+	ver->h2c_version = info->h2c_version;
+	ver->build_time.month = info->build_time.month;
+	ver->build_time.date = info->build_time.date;
+	ver->build_time.hour = info->build_time.hour;
+	ver->build_time.min = info->build_time.min;
+	ver->build_time.year = info->build_time.year;
+
+	return HALMAC_RET_SUCCESS;
+}
+
+static enum halmac_ret_status
+update_fw_info_88xx(struct halmac_adapter *adapter, u8 *fw_bin)
+{
+	struct halmac_fw_version *info = &adapter->fw_ver;
+
+	info->version =
+		rtk_le16_to_cpu(*((__le16 *)(fw_bin + WLAN_FW_HDR_VERSION)));
+	info->sub_version = *(fw_bin + WLAN_FW_HDR_SUBVERSION);
+	info->sub_index = *(fw_bin + WLAN_FW_HDR_SUBINDEX);
+	info->h2c_version = rtk_le16_to_cpu(*((__le16 *)(fw_bin +
+					    WLAN_FW_HDR_H2C_FMT_VER)));
+	info->build_time.month = *(fw_bin + WLAN_FW_HDR_MONTH);
+	info->build_time.date = *(fw_bin + WLAN_FW_HDR_DATE);
+	info->build_time.hour = *(fw_bin + WLAN_FW_HDR_HOUR);
+	info->build_time.min = *(fw_bin + WLAN_FW_HDR_MIN);
+	info->build_time.year =
+		rtk_le16_to_cpu(*((__le16 *)(fw_bin + WLAN_FW_HDR_YEAR)));
+
+	PLTFM_MSG_TRACE("[TRACE]=== FW info ===\n");
+	PLTFM_MSG_TRACE("[TRACE]ver : %X\n", info->version);
+	PLTFM_MSG_TRACE("[TRACE]sub-ver : %X\n",
+			info->sub_version);
+	PLTFM_MSG_TRACE("[TRACE]sub-idx : %X\n",
+			info->sub_index);
+	PLTFM_MSG_TRACE("[TRACE]build : %d/%d/%d %d:%d\n",
+			info->build_time.year, info->build_time.month,
+			info->build_time.date, info->build_time.hour,
+			info->build_time.min);
+
+	return HALMAC_RET_SUCCESS;
+}
+
+static enum halmac_ret_status
+dlfw_to_mem_88xx(struct halmac_adapter *adapter, u8 *fw_bin, u32 src, u32 dest,
+		 u32 size)
+{
+	u8 first_part;
+	u32 mem_offset;
+	u32 residue_size;
+	u32 pkt_size;
+	enum halmac_ret_status status;
+	struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
+
+	mem_offset = 0;
+	first_part = 1;
+	residue_size = size;
+
+	HALMAC_REG_W32_SET(REG_DDMA_CH0CTRL, BIT_DDMACH0_RESET_CHKSUM_STS);
+
+	while (residue_size != 0) {
+		if (residue_size >= adapter->dlfw_pkt_size)
+			pkt_size = adapter->dlfw_pkt_size;
+		else
+			pkt_size = residue_size;
+
+		status = send_fwpkt_88xx(adapter, (u16)(src >> 7),
+					 fw_bin + mem_offset, pkt_size);
+		if (status != HALMAC_RET_SUCCESS) {
+			PLTFM_MSG_ERR("[ERR]send fw pkt!!\n");
+			return status;
+		}
+
+		status = iddma_dlfw_88xx(adapter,
+					 OCPBASE_TXBUF_88XX +
+					 src + adapter->hw_cfg_info.txdesc_size,
+					 dest + mem_offset, pkt_size,
+					 first_part);
+		if (status != HALMAC_RET_SUCCESS) {
+			PLTFM_MSG_ERR("[ERR]iddma dlfw!!\n");
+			return status;
+		}
+
+		first_part = 0;
+		mem_offset += pkt_size;
+		residue_size -= pkt_size;
+	}
+
+	status = check_fw_chksum_88xx(adapter, dest);
+	if (status != HALMAC_RET_SUCCESS) {
+		PLTFM_MSG_ERR("[ERR]chk fw chksum!!\n");
+		return status;
+	}
+
+	return HALMAC_RET_SUCCESS;
+}
+
+static void
+restore_mac_reg_88xx(struct halmac_adapter *adapter,
+		     struct halmac_backup_info *info, u32 num)
+{
+	u8 len;
+	u32 i;
+	u32 reg;
+	u32 value;
+	struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
+	struct halmac_backup_info *curr_info = info;
+
+	for (i = 0; i < num; i++) {
+		reg = curr_info->mac_register;
+		value = curr_info->value;
+		len = curr_info->length;
+
+		if (len == 1)
+			HALMAC_REG_W8(reg, (u8)value);
+		else if (len == 2)
+			HALMAC_REG_W16(reg, (u16)value);
+		else if (len == 4)
+			HALMAC_REG_W32(reg, value);
+
+		curr_info++;
+	}
+}
+
+static enum halmac_ret_status
+dlfw_end_flow_88xx(struct halmac_adapter *adapter)
+{
+	u16 fw_ctrl;
+	u32 cnt;
+	struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
+
+	HALMAC_REG_W32(REG_TXDMA_STATUS, BIT(2));
+
+	/* Check IMEM & DMEM checksum is OK or not */
+	fw_ctrl = HALMAC_REG_R16(REG_MCUFW_CTRL);
+	if ((fw_ctrl & 0x50) != 0x50)
+		return HALMAC_RET_IDMEM_CHKSUM_FAIL;
+
+	HALMAC_REG_W16(REG_MCUFW_CTRL, (fw_ctrl | BIT_FW_DW_RDY) & ~BIT(0));
+
+	wlan_cpu_en_88xx(adapter, 1);
+	PLTFM_MSG_TRACE("[TRACE]Dlfw OK, enable CPU\n");
+
+	cnt = 5000;
+	while (HALMAC_REG_R16(REG_MCUFW_CTRL) != 0xC078) {
+		if (cnt == 0) {
+			PLTFM_MSG_ERR("[ERR]Check 0x80 = 0xC078 fail\n");
+			if ((HALMAC_REG_R32(REG_FW_DBG7) & 0xFFFFFF00) ==
+			    ILLEGAL_KEY_GROUP) {
+				PLTFM_MSG_ERR("[ERR]Key!!\n");
+				return HALMAC_RET_ILLEGAL_KEY_FAIL;
+			}
+			return HALMAC_RET_FW_READY_CHK_FAIL;
+		}
+		cnt--;
+		PLTFM_DELAY_US(50);
+	}
+
+	PLTFM_MSG_TRACE("[TRACE]0x80=0xC078, cnt=%d\n", cnt);
+
+	return HALMAC_RET_SUCCESS;
+}
+
+static enum halmac_ret_status
+free_dl_fw_end_flow_88xx(struct halmac_adapter *adapter)
+{
+	u32 cnt;
+	struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
+
+	cnt = 100;
+	while (HALMAC_REG_R8(REG_HMETFR + 3) != 0) {
+		cnt--;
+		if (cnt == 0) {
+			PLTFM_MSG_ERR("[ERR]0x1CF != 0\n");
+			return HALMAC_RET_DLFW_FAIL;
+		}
+		PLTFM_DELAY_US(50);
+	}
+
+	HALMAC_REG_W8(REG_HMETFR + 3, ID_INFORM_DLEMEM_RDY);
+
+	cnt = 10000;
+	while (HALMAC_REG_R8(REG_MCU_TST_CFG) != ID_CHECK_DLEMEM_RDY) {
+		cnt--;
+		if (cnt == 0) {
+			PLTFM_MSG_ERR("[ERR]0x84 != 0x80\n");
+			return HALMAC_RET_DLFW_FAIL;
+		}
+		PLTFM_DELAY_US(50);
+	}
+
+	HALMAC_REG_W8(REG_MCU_TST_CFG, 0);
+
+	return HALMAC_RET_SUCCESS;
+}
+
+static enum halmac_ret_status
+send_fwpkt_88xx(struct halmac_adapter *adapter, u16 pg_addr, u8 *fw_bin,
+		u32 size)
+{
+	u8 *fw_add_dum = NULL;
+	enum halmac_ret_status status;
+
+	if (adapter->intf == HALMAC_INTERFACE_USB &&
+	    !((size + TX_DESC_SIZE_88XX) & (512 - 1))) {
+		fw_add_dum = (u8 *)PLTFM_MALLOC(size + 1);
+		if (!fw_add_dum) {
+			PLTFM_MSG_ERR("[ERR]fw bin malloc!!\n");
+			return HALMAC_RET_MALLOC_FAIL;
+		}
+
+		PLTFM_MEMCPY(fw_add_dum, fw_bin, size);
+
+		status = dl_rsvd_page_88xx(adapter, pg_addr,
+					   fw_add_dum, size + 1);
+		if (status != HALMAC_RET_SUCCESS)
+			PLTFM_MSG_ERR("[ERR]dl rsvd page - dum!!\n");
+
+		PLTFM_FREE(fw_add_dum, size + 1);
+
+		return status;
+	}
+
+	status = dl_rsvd_page_88xx(adapter, pg_addr, fw_bin, size);
+	if (status != HALMAC_RET_SUCCESS)
+		PLTFM_MSG_ERR("[ERR]dl rsvd page!!\n");
+
+	return status;
+}
+
+static enum halmac_ret_status
+iddma_dlfw_88xx(struct halmac_adapter *adapter, u32 src, u32 dest, u32 len,
+		u8 first)
+{
+	u32 cnt;
+	u32 ch0_ctrl = (u32)(BIT_DDMACH0_CHKSUM_EN | BIT_DDMACH0_OWN);
+	struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
+
+	cnt = HALMC_DDMA_POLLING_COUNT;
+	while (HALMAC_REG_R32(REG_DDMA_CH0CTRL) & BIT_DDMACH0_OWN) {
+		cnt--;
+		if (cnt == 0) {
+			PLTFM_MSG_ERR("[ERR]ch0 ready!!\n");
+			return HALMAC_RET_DDMA_FAIL;
+		}
+	}
+
+	ch0_ctrl |= (len & BIT_MASK_DDMACH0_DLEN);
+	if (first == 0)
+		ch0_ctrl |= BIT_DDMACH0_CHKSUM_CONT;
+
+	if (iddma_en_88xx(adapter, src, dest, ch0_ctrl) !=
+	    HALMAC_RET_SUCCESS) {
+		PLTFM_MSG_ERR("[ERR]iddma en!!\n");
+		return HALMAC_RET_DDMA_FAIL;
+	}
+
+	return HALMAC_RET_SUCCESS;
+}
+
+static enum halmac_ret_status
+iddma_en_88xx(struct halmac_adapter *adapter, u32 src, u32 dest, u32 ctrl)
+{
+	u32 cnt = HALMC_DDMA_POLLING_COUNT;
+	struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
+
+	HALMAC_REG_W32(REG_DDMA_CH0SA, src);
+	HALMAC_REG_W32(REG_DDMA_CH0DA, dest);
+	HALMAC_REG_W32(REG_DDMA_CH0CTRL, ctrl);
+
+	while (HALMAC_REG_R32(REG_DDMA_CH0CTRL) & BIT_DDMACH0_OWN) {
+		cnt--;
+		if (cnt == 0)
+			return HALMAC_RET_DDMA_FAIL;
+	}
+
+	return HALMAC_RET_SUCCESS;
+}
+
+static enum halmac_ret_status
+check_fw_chksum_88xx(struct halmac_adapter *adapter, u32 mem_addr)
+{
+	u8 fw_ctrl;
+	struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
+
+	fw_ctrl = HALMAC_REG_R8(REG_MCUFW_CTRL);
+
+	if (HALMAC_REG_R32(REG_DDMA_CH0CTRL) & BIT_DDMACH0_CHKSUM_STS) {
+		if (mem_addr < OCPBASE_DMEM_88XX) {
+			fw_ctrl |= BIT_IMEM_DW_OK;
+			fw_ctrl &= ~BIT_IMEM_CHKSUM_OK;
+			HALMAC_REG_W8(REG_MCUFW_CTRL, fw_ctrl);
+		} else {
+			fw_ctrl |= BIT_DMEM_DW_OK;
+			fw_ctrl &= ~BIT_DMEM_CHKSUM_OK;
+			HALMAC_REG_W8(REG_MCUFW_CTRL, fw_ctrl);
+		}
+
+		PLTFM_MSG_ERR("[ERR]fw chksum!!\n");
+
+		return HALMAC_RET_FW_CHECKSUM_FAIL;
+	}
+
+	if (mem_addr < OCPBASE_DMEM_88XX) {
+		fw_ctrl |= (BIT_IMEM_DW_OK | BIT_IMEM_CHKSUM_OK);
+		HALMAC_REG_W8(REG_MCUFW_CTRL, fw_ctrl);
+	} else {
+		fw_ctrl |= (BIT_DMEM_DW_OK | BIT_DMEM_CHKSUM_OK);
+		HALMAC_REG_W8(REG_MCUFW_CTRL, fw_ctrl);
+	}
+
+	return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * check_fw_status_88xx() -check fw status
+ * @adapter : the adapter of halmac
+ * @status : fw status
+ * Author : KaiYuan Chang/Ivan Lin
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+check_fw_status_88xx(struct halmac_adapter *adapter, u8 *fw_status)
+{
+	u32 cnt;
+	u32 fw_dbg6;
+	u32 fw_pc;
+	struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
+	enum halmac_ret_status status = HALMAC_RET_SUCCESS;
+
+	PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
+
+	*fw_status = 1;
+
+	fw_dbg6 = HALMAC_REG_R32(REG_FW_DBG6);
+
+	if (fw_dbg6 != 0) {
+		PLTFM_MSG_ERR("[ERR]REG_FW_DBG6 !=0\n");
+		if ((fw_dbg6 & FW_STATUS_CHK_WARN) != 0)
+			PLTFM_MSG_WARN("[WARN]fw status(warn):%X\n", fw_dbg6);
+
+		if ((fw_dbg6 & FW_STATUS_CHK_ERR) != 0)
+			PLTFM_MSG_ERR("[ERR]fw status(err):%X\n", fw_dbg6);
+
+		if ((fw_dbg6 & FW_STATUS_CHK_FATAL) != 0) {
+			PLTFM_MSG_ERR("[ERR]fw status(fatal):%X\n", fw_dbg6);
+			fw_fatal_status_debug_88xx(adapter);
+			*fw_status = 0;
+			return status;
+		}
+	}
+
+	fw_pc = HALMAC_REG_R32(REG_FW_DBG7);
+	cnt = 10;
+	while (HALMAC_REG_R32(REG_FW_DBG7) == fw_pc) {
+		cnt--;
+		if (cnt == 0)
+			break;
+	}
+
+	if (cnt == 0) {
+		cnt = 200;
+		while (HALMAC_REG_R32(REG_FW_DBG7) == fw_pc) {
+			cnt--;
+			if (cnt == 0) {
+				PLTFM_MSG_ERR("[ERR]fw pc\n");
+				*fw_status = 0;
+				return status;
+			}
+			PLTFM_DELAY_US(50);
+		}
+	}
+
+	PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
+
+	return status;
+}
+
+static void
+fw_fatal_status_debug_88xx(struct halmac_adapter *adapter)
+{
+	struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
+
+	PLTFM_MSG_ERR("[ERR]0x%X = %X\n",
+		      REG_FW_DBG6, HALMAC_REG_R32(REG_FW_DBG6));
+
+	PLTFM_MSG_ERR("[ERR]0x%X = %X\n",
+		      REG_ARFR5, HALMAC_REG_R32(REG_ARFR5));
+
+	PLTFM_MSG_ERR("[ERR]0x%X = %X\n",
+		      REG_MCUTST_I, HALMAC_REG_R32(REG_MCUTST_I));
+}
+
+enum halmac_ret_status
+dump_fw_dmem_88xx(struct halmac_adapter *adapter, u8 *dmem, u32 *size)
+{
+	return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * cfg_max_dl_size_88xx() - config max download FW size
+ * @adapter : the adapter of halmac
+ * @size : max download fw size
+ *
+ * Halmac uses this setting to set max packet size for
+ * download FW.
+ * If user has not called this API, halmac use default
+ * setting for download FW
+ * Note1 : size need multiple of 2
+ * Note2 : max size is 31K
+ *
+ * Author : Ivan Lin/KaiYuan Chang
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+cfg_max_dl_size_88xx(struct halmac_adapter *adapter, u32 size)
+{
+	PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
+
+	if (size > DLFW_PKT_SIZE_LIMIT) {
+		PLTFM_MSG_ERR("[ERR]size > max dl size!\n");
+		return HALMAC_RET_CFG_DLFW_SIZE_FAIL;
+	}
+
+	if ((size & (2 - 1)) != 0) {
+		PLTFM_MSG_ERR("[ERR]not multiple of 2!\n");
+		return HALMAC_RET_CFG_DLFW_SIZE_FAIL;
+	}
+
+	adapter->dlfw_pkt_size = size;
+
+	PLTFM_MSG_TRACE("[TRACE]Cfg max size:%X\n", size);
+	PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
+
+	return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * enter_cpu_sleep_mode_88xx() -wlan cpu enter sleep mode
+ * @adapter : the adapter of halmac
+ * Author : Ivan Lin
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+enter_cpu_sleep_mode_88xx(struct halmac_adapter *adapter)
+{
+	u32 cnt;
+	struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
+	enum halmac_wlcpu_mode *cur_mode = &adapter->halmac_state.wlcpu_mode;
+
+	if (halmac_fw_validate(adapter) != HALMAC_RET_SUCCESS)
+		return HALMAC_RET_NO_DLFW;
+
+	if (*cur_mode != HALMAC_WLCPU_ACTIVE)
+		return HALMAC_RET_ERROR_STATE;
+
+	cnt = 100;
+	while (HALMAC_REG_R8(REG_HMETFR + 3) != 0) {
+		cnt--;
+		if (cnt == 0) {
+			PLTFM_MSG_ERR("[ERR]0x1CF != 0\n");
+			return HALMAC_RET_STATE_INCORRECT;
+		}
+		PLTFM_DELAY_US(50);
+	}
+
+	HALMAC_REG_W8(REG_HMETFR + 3, ID_INFORM_ENETR_CPU_SLEEP);
+
+	*cur_mode = HALMAC_WLCPU_ENTER_SLEEP;
+
+	return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * get_cpu_mode_88xx() -get wlcpu mode
+ * @adapter : the adapter of halmac
+ * @mode : cpu mode
+ * Author : Ivan Lin
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+get_cpu_mode_88xx(struct halmac_adapter *adapter,
+		  enum halmac_wlcpu_mode *mode)
+{
+	struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
+	enum halmac_wlcpu_mode *cur_mode = &adapter->halmac_state.wlcpu_mode;
+
+	if (halmac_fw_validate(adapter) != HALMAC_RET_SUCCESS)
+		return HALMAC_RET_NO_DLFW;
+
+	if (*cur_mode == HALMAC_WLCPU_ACTIVE) {
+		*mode = HALMAC_WLCPU_ACTIVE;
+		return HALMAC_RET_SUCCESS;
+	}
+
+	if (*cur_mode == HALMAC_WLCPU_SLEEP) {
+		*mode = HALMAC_WLCPU_SLEEP;
+		return HALMAC_RET_SUCCESS;
+	}
+
+	if (HALMAC_REG_R8(REG_MCU_TST_CFG) == ID_CHECK_ENETR_CPU_SLEEP) {
+		*mode = HALMAC_WLCPU_SLEEP;
+		HALMAC_REG_W8(REG_MCU_TST_CFG, 0);
+	} else {
+		*mode = HALMAC_WLCPU_ENTER_SLEEP;
+	}
+
+	return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * send_general_info_88xx() -send general information to FW
+ * @adapter : the adapter of halmac
+ * @info : general information
+ * Author : KaiYuan Chang/Ivan Lin
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+send_general_info_88xx(struct halmac_adapter *adapter,
+		       struct halmac_general_info *info)
+{
+	u8 h2cq_ele[4] = {0};
+	u32 h2cq_addr;
+	enum halmac_ret_status status = HALMAC_RET_SUCCESS;
+
+	if (halmac_fw_validate(adapter) != HALMAC_RET_SUCCESS)
+		return HALMAC_RET_NO_DLFW;
+
+	if (adapter->fw_ver.h2c_version < 4)
+		return HALMAC_RET_FW_NO_SUPPORT;
+
+	PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
+
+	if (adapter->halmac_state.dlfw_state == HALMAC_DLFW_NONE) {
+		PLTFM_MSG_ERR("[ERR]no dl fw!!\n");
+		return HALMAC_RET_NO_DLFW;
+	}
+
+	status = proc_send_general_info_88xx(adapter, info);
+	if (status != HALMAC_RET_SUCCESS) {
+		PLTFM_MSG_ERR("[ERR]send gen info!!\n");
+		return status;
+	}
+
+	status = proc_send_phydm_info_88xx(adapter, info);
+	if (status != HALMAC_RET_SUCCESS) {
+		PLTFM_MSG_ERR("[ERR]send phydm info\n");
+		return status;
+	}
+
+	h2cq_addr = adapter->txff_alloc.rsvd_h2cq_addr;
+	h2cq_addr <<= TX_PAGE_SIZE_SHIFT_88XX;
+	status = dump_fifo_88xx(adapter, HAL_FIFO_SEL_TX,
+				h2cq_addr, 4, h2cq_ele);
+	if (status != HALMAC_RET_SUCCESS) {
+		PLTFM_MSG_ERR("[ERR]dump h2cq!!\n");
+		return status;
+	}
+
+	if ((h2cq_ele[0] & 0x7F) != 0x01 || h2cq_ele[1] != 0xFF) {
+		PLTFM_MSG_ERR("[ERR]h2cq compare!!\n");
+		return HALMAC_RET_SEND_H2C_FAIL;
+	}
+
+	if (adapter->halmac_state.dlfw_state == HALMAC_DLFW_DONE)
+		adapter->halmac_state.dlfw_state = HALMAC_GEN_INFO_SENT;
+
+	PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
+
+	return HALMAC_RET_SUCCESS;
+}
+
+static enum halmac_ret_status
+proc_send_general_info_88xx(struct halmac_adapter *adapter,
+			    struct halmac_general_info *info)
+{
+	u8 h2c_buf[H2C_PKT_SIZE_88XX] = { 0 };
+	u16 seq_num = 0;
+	struct halmac_h2c_header_info hdr_info;
+	enum halmac_ret_status status = HALMAC_RET_SUCCESS;
+
+	PLTFM_MSG_TRACE("[TRACE]%s\n", __func__);
+
+	GENERAL_INFO_SET_FW_TX_BOUNDARY(h2c_buf,
+					adapter->txff_alloc.rsvd_fw_txbuf_addr -
+					adapter->txff_alloc.rsvd_boundary);
+
+	hdr_info.sub_cmd_id = SUB_CMD_ID_GENERAL_INFO;
+	hdr_info.content_size = 4;
+	hdr_info.ack = 0;
+	set_h2c_pkt_hdr_88xx(adapter, h2c_buf, &hdr_info, &seq_num);
+
+	status = send_h2c_pkt_88xx(adapter, h2c_buf);
+
+	if (status != HALMAC_RET_SUCCESS)
+		PLTFM_MSG_ERR("[ERR]send h2c!!\n");
+
+	return status;
+}
+
+static enum halmac_ret_status
+proc_send_phydm_info_88xx(struct halmac_adapter *adapter,
+			  struct halmac_general_info *info)
+{
+	u8 h2c_buf[H2C_PKT_SIZE_88XX] = { 0 };
+	u16 seq_num = 0;
+	struct halmac_h2c_header_info hdr_info;
+	enum halmac_ret_status status = HALMAC_RET_SUCCESS;
+
+	PLTFM_MSG_TRACE("[TRACE]%s\n", __func__);
+
+	PHYDM_INFO_SET_REF_TYPE(h2c_buf, info->rfe_type);
+	PHYDM_INFO_SET_RF_TYPE(h2c_buf, info->rf_type);
+	PHYDM_INFO_SET_CUT_VER(h2c_buf, adapter->chip_ver);
+	PHYDM_INFO_SET_RX_ANT_STATUS(h2c_buf, info->rx_ant_status);
+	PHYDM_INFO_SET_TX_ANT_STATUS(h2c_buf, info->tx_ant_status);
+
+	hdr_info.sub_cmd_id = SUB_CMD_ID_PHYDM_INFO;
+	hdr_info.content_size = 8;
+	hdr_info.ack = 0;
+	set_h2c_pkt_hdr_88xx(adapter, h2c_buf, &hdr_info, &seq_num);
+
+	status = send_h2c_pkt_88xx(adapter, h2c_buf);
+
+	if (status != HALMAC_RET_SUCCESS)
+		PLTFM_MSG_ERR("[ERR]send h2c!!\n");
+
+	return status;
+}
+
+/**
+ * drv_fwctrl_88xx() - send drv-defined h2c pkt
+ * @adapter : the adapter of halmac
+ * @payload : no include offload pkt h2c header
+ * @size : no include offload pkt h2c header
+ * Author : Ivan Lin
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+drv_fwctrl_88xx(struct halmac_adapter *adapter, u8 *payload, u32 size, u8 ack)
+{
+	u8 h2c_buf[H2C_PKT_SIZE_88XX] = { 0 };
+	u16 seq_num = 0;
+	struct halmac_h2c_header_info hdr_info;
+	enum halmac_ret_status status = HALMAC_RET_SUCCESS;
+
+	PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
+
+	if (!payload)
+		return HALMAC_RET_DATA_BUF_NULL;
+
+	if (size > H2C_PKT_SIZE_88XX - H2C_PKT_HDR_SIZE_88XX)
+		return HALMAC_RET_DATA_SIZE_INCORRECT;
+
+	PLTFM_MEMCPY(h2c_buf + H2C_PKT_HDR_SIZE_88XX, payload, size);
+
+	hdr_info.sub_cmd_id = SUB_CMD_ID_FW_FWCTRL;
+	hdr_info.content_size = (u16)size;
+	hdr_info.ack = ack;
+	set_h2c_pkt_hdr_88xx(adapter, h2c_buf, &hdr_info, &seq_num);
+
+	status = send_h2c_pkt_88xx(adapter, h2c_buf);
+
+	if (status != HALMAC_RET_SUCCESS)
+		PLTFM_MSG_ERR("[ERR]send h2c!!\n");
+
+	PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
+
+	return status;
+}
+
+#endif /* HALMAC_88XX_SUPPORT */
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/halmac/halmac_88xx/halmac_fw_88xx.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/halmac/halmac_88xx/halmac_fw_88xx.h
--- linux-5.6.3/3rdparty/rtl8821ce/hal/halmac/halmac_88xx/halmac_fw_88xx.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/halmac/halmac_88xx/halmac_fw_88xx.h	2020-04-10 16:35:06.793658994 +0300
@@ -0,0 +1,61 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ ******************************************************************************/
+
+#ifndef _HALMAC_FW_88XX_H_
+#define _HALMAC_FW_88XX_H_
+
+#include "../halmac_api.h"
+
+#if HALMAC_88XX_SUPPORT
+
+#define HALMC_DDMA_POLLING_COUNT		1000
+
+enum halmac_ret_status
+download_firmware_88xx(struct halmac_adapter *adapter, u8 *fw_bin, u32 size);
+
+enum halmac_ret_status
+free_download_firmware_88xx(struct halmac_adapter *adapter,
+			    enum halmac_dlfw_mem mem_sel, u8 *fw_bin, u32 size);
+
+enum halmac_ret_status
+get_fw_version_88xx(struct halmac_adapter *adapter,
+		    struct halmac_fw_version *ver);
+
+enum halmac_ret_status
+check_fw_status_88xx(struct halmac_adapter *adapter, u8 *fw_status);
+
+enum halmac_ret_status
+dump_fw_dmem_88xx(struct halmac_adapter *adapter, u8 *dmem, u32 *size);
+
+enum halmac_ret_status
+cfg_max_dl_size_88xx(struct halmac_adapter *adapter, u32 size);
+
+enum halmac_ret_status
+enter_cpu_sleep_mode_88xx(struct halmac_adapter *adapter);
+
+enum halmac_ret_status
+get_cpu_mode_88xx(struct halmac_adapter *adapter,
+		  enum halmac_wlcpu_mode *mode);
+
+enum halmac_ret_status
+send_general_info_88xx(struct halmac_adapter *adapter,
+		       struct halmac_general_info *info);
+
+enum halmac_ret_status
+drv_fwctrl_88xx(struct halmac_adapter *adapter, u8 *payload, u32 size, u8 ack);
+
+#endif /* HALMAC_88XX_SUPPORT */
+
+#endif/* _HALMAC_FW_88XX_H_ */
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/halmac/halmac_88xx/halmac_gpio_88xx.c linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/halmac/halmac_88xx/halmac_gpio_88xx.c
--- linux-5.6.3/3rdparty/rtl8821ce/hal/halmac/halmac_88xx/halmac_gpio_88xx.c	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/halmac/halmac_88xx/halmac_gpio_88xx.c	2020-04-10 16:35:06.793658994 +0300
@@ -0,0 +1,421 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ ******************************************************************************/
+
+#include "halmac_gpio_88xx.h"
+
+#if HALMAC_88XX_SUPPORT
+
+/**
+ * pinmux_wl_led_mode_88xx() -control wlan led gpio function
+ * @adapter : the adapter of halmac
+ * @mode : wlan led mode
+ * Author : Ivan Lin
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+pinmux_wl_led_mode_88xx(struct halmac_adapter *adapter,
+			enum halmac_wlled_mode mode)
+{
+	u8 value8;
+	struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
+
+	PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
+
+	value8 = HALMAC_REG_R8(REG_LED_CFG + 2);
+	value8 &= ~(BIT(6));
+	value8 |= BIT(3);
+	value8 &= ~(BIT(0) | BIT(1) | BIT(2));
+
+	switch (mode) {
+	case HALMAC_WLLED_MODE_TRX:
+		value8 |= 2;
+		break;
+	case HALMAC_WLLED_MODE_TX:
+		value8 |= 4;
+		break;
+	case HALMAC_WLLED_MODE_RX:
+		value8 |= 6;
+		break;
+	case HALMAC_WLLED_MODE_SW_CTRL:
+		value8 |= 0;
+		break;
+	default:
+		return HALMAC_RET_SWITCH_CASE_ERROR;
+	}
+
+	HALMAC_REG_W8(REG_LED_CFG + 2, value8);
+
+	PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
+
+	return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * pinmux_wl_led_sw_ctrl_88xx() -control wlan led on/off
+ * @adapter : the adapter of halmac
+ * @on : on(1), off(0)
+ * Author : Ivan Lin
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+void
+pinmux_wl_led_sw_ctrl_88xx(struct halmac_adapter *adapter, u8 on)
+{
+	u8 value8;
+	struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
+
+	value8 = HALMAC_REG_R8(REG_LED_CFG + 2);
+	value8 = (on == 0) ? value8 | BIT(3) : value8 & ~(BIT(3));
+
+	HALMAC_REG_W8(REG_LED_CFG + 2, value8);
+}
+
+/**
+ * pinmux_sdio_int_polarity_88xx() -control sdio int polarity
+ * @adapter : the adapter of halmac
+ * @low_active : low active(1), high active(0)
+ * Author : Ivan Lin
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+void
+pinmux_sdio_int_polarity_88xx(struct halmac_adapter *adapter, u8 low_active)
+{
+	u8 value8;
+	struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
+
+	value8 = HALMAC_REG_R8(REG_SYS_SDIO_CTRL + 2);
+	value8 = (low_active == 0) ? value8 | BIT(3) : value8 & ~(BIT(3));
+
+	HALMAC_REG_W8(REG_SYS_SDIO_CTRL + 2, value8);
+}
+
+/**
+ * pinmux_gpio_mode_88xx() -control gpio io mode
+ * @adapter : the adapter of halmac
+ * @gpio_id : gpio0~15(0~15)
+ * @output : output(1), input(0)
+ * Author : Ivan Lin
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+pinmux_gpio_mode_88xx(struct halmac_adapter *adapter, u8 gpio_id, u8 output)
+{
+	u16 value16;
+	u8 in_out;
+	u32 offset;
+	struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
+
+	if (gpio_id <= 7)
+		offset = REG_GPIO_PIN_CTRL + 2;
+	else if (gpio_id >= 8 && gpio_id <= 15)
+		offset = REG_GPIO_EXT_CTRL + 2;
+	else
+		return HALMAC_RET_WRONG_GPIO;
+
+	in_out = (output == 0) ? 0 : 1;
+	gpio_id &= (8 - 1);
+
+	value16 = HALMAC_REG_R16(offset);
+	value16 &= ~((1 << gpio_id) | (1 << gpio_id << 8));
+	value16 |= (in_out << gpio_id);
+	HALMAC_REG_W16(offset, value16);
+
+	return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * pinmux_gpio_output_88xx() -control gpio output high/low
+ * @adapter : the adapter of halmac
+ * @gpio_id : gpio0~15(0~15)
+ * @high : high(1), low(0)
+ * Author : Ivan Lin
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+pinmux_gpio_output_88xx(struct halmac_adapter *adapter, u8 gpio_id, u8 high)
+{
+	u8 value8;
+	u8 hi_low;
+	u32 offset;
+	struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
+
+	if (gpio_id <= 7)
+		offset = REG_GPIO_PIN_CTRL + 1;
+	else if (gpio_id >= 8 && gpio_id <= 15)
+		offset = REG_GPIO_EXT_CTRL + 1;
+	else
+		return HALMAC_RET_WRONG_GPIO;
+
+	hi_low = (high == 0) ? 0 : 1;
+	gpio_id &= (8 - 1);
+
+	value8 = HALMAC_REG_R8(offset);
+	value8 &= ~(1 << gpio_id);
+	value8 |= (hi_low << gpio_id);
+	HALMAC_REG_W8(offset, value8);
+
+	return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * halmac_pinmux_status_88xx() -get current gpio status(high/low)
+ * @adapter : the adapter of halmac
+ * @pin_id : 0~15(0~15)
+ * @phigh : high(1), low(0)
+ * Author : Ivan Lin
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+pinmux_pin_status_88xx(struct halmac_adapter *adapter, u8 pin_id, u8 *high)
+{
+	u8 value8;
+	u32 offset;
+	struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
+
+	if (pin_id <= 7)
+		offset = REG_GPIO_PIN_CTRL;
+	else if (pin_id >= 8 && pin_id <= 15)
+		offset = REG_GPIO_EXT_CTRL;
+	else
+		return HALMAC_RET_WRONG_GPIO;
+
+	pin_id &= (8 - 1);
+
+	value8 = HALMAC_REG_R8(offset);
+	*high = (value8 & (1 << pin_id)) >> pin_id;
+
+	return HALMAC_RET_SUCCESS;
+}
+
+enum halmac_ret_status
+pinmux_parser_88xx(struct halmac_adapter *adapter,
+		   const struct halmac_gpio_pimux_list *list, u32 size,
+		   u32 gpio_id, u32 *cur_func)
+{
+	u32 i;
+	u8 value8;
+	const struct halmac_gpio_pimux_list *cur_list = list;
+	enum halmac_gpio_cfg_state *state;
+	struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
+
+	state = &adapter->halmac_state.gpio_cfg_state;
+
+	if (*state == HALMAC_GPIO_CFG_STATE_BUSY)
+		return HALMAC_RET_BUSY_STATE;
+
+	*state = HALMAC_GPIO_CFG_STATE_BUSY;
+
+	for (i = 0; i < size; i++) {
+		if (gpio_id != cur_list->id) {
+			PLTFM_MSG_ERR("[ERR]offset:%X, value:%X, func:%X\n",
+				      cur_list->offset, cur_list->value,
+				      cur_list->func);
+			PLTFM_MSG_ERR("[ERR]id1 : %X, id2 : %X\n",
+				      gpio_id, cur_list->id);
+			*state = HALMAC_GPIO_CFG_STATE_IDLE;
+			return HALMAC_RET_GET_PINMUX_ERR;
+		}
+		value8 = HALMAC_REG_R8(cur_list->offset);
+		value8 &= cur_list->msk;
+		if (value8 == cur_list->value) {
+			*cur_func = cur_list->func;
+			break;
+		}
+		cur_list++;
+	}
+
+	*state = HALMAC_GPIO_CFG_STATE_IDLE;
+
+	if (i == size)
+		return HALMAC_RET_GET_PINMUX_ERR;
+
+	return HALMAC_RET_SUCCESS;
+}
+
+enum halmac_ret_status
+pinmux_switch_88xx(struct halmac_adapter *adapter,
+		   const struct halmac_gpio_pimux_list *list, u32 size,
+		   u32 gpio_id, enum halmac_gpio_func gpio_func)
+{
+	u32 i;
+	u8 value8;
+	u16 switch_func;
+	const struct halmac_gpio_pimux_list *cur_list = list;
+	enum halmac_gpio_cfg_state *state;
+	struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
+
+	state = &adapter->halmac_state.gpio_cfg_state;
+
+	if (*state == HALMAC_GPIO_CFG_STATE_BUSY)
+		return HALMAC_RET_BUSY_STATE;
+
+	switch (gpio_func) {
+	case HALMAC_GPIO_FUNC_WL_LED:
+		switch_func = HALMAC_WL_LED;
+		break;
+	case HALMAC_GPIO_FUNC_SDIO_INT:
+		switch_func = HALMAC_SDIO_INT;
+		break;
+	case HALMAC_GPIO_FUNC_BT_HOST_WAKE1:
+	case HALMAC_GPIO_FUNC_BT_DEV_WAKE1:
+		switch_func = HALMAC_GPIO13_14_WL_CTRL_EN;
+		break;
+	case HALMAC_GPIO_FUNC_SW_IO_0:
+	case HALMAC_GPIO_FUNC_SW_IO_1:
+	case HALMAC_GPIO_FUNC_SW_IO_2:
+	case HALMAC_GPIO_FUNC_SW_IO_3:
+	case HALMAC_GPIO_FUNC_SW_IO_4:
+	case HALMAC_GPIO_FUNC_SW_IO_5:
+	case HALMAC_GPIO_FUNC_SW_IO_6:
+	case HALMAC_GPIO_FUNC_SW_IO_7:
+	case HALMAC_GPIO_FUNC_SW_IO_8:
+	case HALMAC_GPIO_FUNC_SW_IO_9:
+	case HALMAC_GPIO_FUNC_SW_IO_10:
+	case HALMAC_GPIO_FUNC_SW_IO_11:
+	case HALMAC_GPIO_FUNC_SW_IO_12:
+	case HALMAC_GPIO_FUNC_SW_IO_13:
+	case HALMAC_GPIO_FUNC_SW_IO_14:
+	case HALMAC_GPIO_FUNC_SW_IO_15:
+		switch_func = HALMAC_SW_IO;
+		break;
+	default:
+		return HALMAC_RET_SWITCH_CASE_ERROR;
+	}
+
+	for (i = 0; i < size; i++) {
+		if (gpio_id != cur_list->id) {
+			PLTFM_MSG_ERR("[ERR]offset:%X, value:%X, func:%X\n",
+				      cur_list->offset, cur_list->value,
+				      cur_list->func);
+			PLTFM_MSG_ERR("[ERR]id1 : %X, id2 : %X\n",
+				      gpio_id, cur_list->id);
+			return HALMAC_RET_GET_PINMUX_ERR;
+		}
+
+		if (switch_func == cur_list->func)
+			break;
+
+		cur_list++;
+	}
+
+	if (i == size) {
+		PLTFM_MSG_ERR("[ERR]gpio func error:%X %X\n",
+			      gpio_id, cur_list->id);
+		return HALMAC_RET_GET_PINMUX_ERR;
+	}
+
+	*state = HALMAC_GPIO_CFG_STATE_BUSY;
+
+	cur_list = list;
+	for (i = 0; i < size; i++) {
+		value8 = HALMAC_REG_R8(cur_list->offset);
+		value8 &= ~(cur_list->msk);
+
+		if (switch_func == cur_list->func) {
+			value8 |= (cur_list->value & cur_list->msk);
+			HALMAC_REG_W8(cur_list->offset, value8);
+			break;
+		}
+
+		value8 |= (~cur_list->value & cur_list->msk);
+		HALMAC_REG_W8(cur_list->offset, value8);
+
+		cur_list++;
+	}
+
+	*state = HALMAC_GPIO_CFG_STATE_IDLE;
+
+	return HALMAC_RET_SUCCESS;
+}
+
+enum halmac_ret_status
+pinmux_record_88xx(struct halmac_adapter *adapter,
+		   enum halmac_gpio_func gpio_func, u8 val)
+{
+	switch (gpio_func) {
+	case HALMAC_GPIO_FUNC_WL_LED:
+		adapter->pinmux_info.wl_led = val;
+		break;
+	case HALMAC_GPIO_FUNC_SDIO_INT:
+		adapter->pinmux_info.sdio_int = val;
+		break;
+	case HALMAC_GPIO_FUNC_BT_HOST_WAKE1:
+		adapter->pinmux_info.bt_host_wake = val;
+		break;
+	case HALMAC_GPIO_FUNC_BT_DEV_WAKE1:
+		adapter->pinmux_info.bt_dev_wake = val;
+		break;
+	case HALMAC_GPIO_FUNC_SW_IO_0:
+		adapter->pinmux_info.sw_io_0 = val;
+		break;
+	case HALMAC_GPIO_FUNC_SW_IO_1:
+		adapter->pinmux_info.sw_io_1 = val;
+		break;
+	case HALMAC_GPIO_FUNC_SW_IO_2:
+		adapter->pinmux_info.sw_io_2 = val;
+		break;
+	case HALMAC_GPIO_FUNC_SW_IO_3:
+		adapter->pinmux_info.sw_io_3 = val;
+		break;
+	case HALMAC_GPIO_FUNC_SW_IO_4:
+		adapter->pinmux_info.sw_io_4 = val;
+		break;
+	case HALMAC_GPIO_FUNC_SW_IO_5:
+		adapter->pinmux_info.sw_io_5 = val;
+		break;
+	case HALMAC_GPIO_FUNC_SW_IO_6:
+		adapter->pinmux_info.sw_io_6 = val;
+		break;
+	case HALMAC_GPIO_FUNC_SW_IO_7:
+		adapter->pinmux_info.sw_io_7 = val;
+		break;
+	case HALMAC_GPIO_FUNC_SW_IO_8:
+		adapter->pinmux_info.sw_io_8 = val;
+		break;
+	case HALMAC_GPIO_FUNC_SW_IO_9:
+		adapter->pinmux_info.sw_io_9 = val;
+		break;
+	case HALMAC_GPIO_FUNC_SW_IO_10:
+		adapter->pinmux_info.sw_io_10 = val;
+		break;
+	case HALMAC_GPIO_FUNC_SW_IO_11:
+		adapter->pinmux_info.sw_io_11 = val;
+		break;
+	case HALMAC_GPIO_FUNC_SW_IO_12:
+		adapter->pinmux_info.sw_io_12 = val;
+		break;
+	case HALMAC_GPIO_FUNC_SW_IO_13:
+		adapter->pinmux_info.sw_io_13 = val;
+		break;
+	case HALMAC_GPIO_FUNC_SW_IO_14:
+		adapter->pinmux_info.sw_io_14 = val;
+		break;
+	case HALMAC_GPIO_FUNC_SW_IO_15:
+		adapter->pinmux_info.sw_io_15 = val;
+		break;
+	default:
+		return HALMAC_RET_GET_PINMUX_ERR;
+	}
+
+	return HALMAC_RET_SUCCESS;
+}
+
+#endif /* HALMAC_88XX_SUPPORT */
+
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/halmac/halmac_88xx/halmac_gpio_88xx.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/halmac/halmac_88xx/halmac_gpio_88xx.h
--- linux-5.6.3/3rdparty/rtl8821ce/hal/halmac/halmac_88xx/halmac_gpio_88xx.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/halmac/halmac_88xx/halmac_gpio_88xx.h	2020-04-10 16:35:06.793658994 +0300
@@ -0,0 +1,59 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ ******************************************************************************/
+
+#ifndef _HALMAC_GPIO_88XX_H_
+#define _HALMAC_GPIO_88XX_H_
+
+#include "../halmac_api.h"
+#include "../halmac_gpio_cmd.h"
+
+#if HALMAC_88XX_SUPPORT
+
+enum halmac_ret_status
+pinmux_wl_led_mode_88xx(struct halmac_adapter *adapter,
+			enum halmac_wlled_mode mode);
+
+void
+pinmux_wl_led_sw_ctrl_88xx(struct halmac_adapter *adapter, u8 on);
+
+void
+pinmux_sdio_int_polarity_88xx(struct halmac_adapter *adapter, u8 low_active);
+
+enum halmac_ret_status
+pinmux_gpio_mode_88xx(struct halmac_adapter *adapter, u8 gpio_id, u8 output);
+
+enum halmac_ret_status
+pinmux_gpio_output_88xx(struct halmac_adapter *adapter, u8 gpio_id, u8 high);
+
+enum halmac_ret_status
+pinmux_pin_status_88xx(struct halmac_adapter *adapter, u8 pin_id, u8 *high);
+
+enum halmac_ret_status
+pinmux_parser_88xx(struct halmac_adapter *adapter,
+		   const struct halmac_gpio_pimux_list *list, u32 size,
+		   u32 gpio_id, u32 *cur_func);
+
+enum halmac_ret_status
+pinmux_switch_88xx(struct halmac_adapter *adapter,
+		   const struct halmac_gpio_pimux_list *list, u32 size,
+		   u32 gpio_id, enum halmac_gpio_func gpio_func);
+
+enum halmac_ret_status
+pinmux_record_88xx(struct halmac_adapter *adapter,
+		   enum halmac_gpio_func gpio_func, u8 val);
+
+#endif /* HALMAC_88XX_SUPPORT */
+
+#endif/* _HALMAC_GPIO_88XX_H_ */
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/halmac/halmac_88xx/halmac_init_88xx.c linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/halmac/halmac_88xx/halmac_init_88xx.c
--- linux-5.6.3/3rdparty/rtl8821ce/hal/halmac/halmac_88xx/halmac_init_88xx.c	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/halmac/halmac_88xx/halmac_init_88xx.c	2020-04-10 16:35:06.793658994 +0300
@@ -0,0 +1,992 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ ******************************************************************************/
+
+#include "halmac_init_88xx.h"
+#include "halmac_88xx_cfg.h"
+#include "halmac_fw_88xx.h"
+#include "halmac_common_88xx.h"
+#include "halmac_cfg_wmac_88xx.h"
+#include "halmac_efuse_88xx.h"
+#include "halmac_mimo_88xx.h"
+#include "halmac_bb_rf_88xx.h"
+#if HALMAC_SDIO_SUPPORT
+#include "halmac_sdio_88xx.h"
+#endif
+#if HALMAC_USB_SUPPORT
+#include "halmac_usb_88xx.h"
+#endif
+#if HALMAC_PCIE_SUPPORT
+#include "halmac_pcie_88xx.h"
+#endif
+#include "halmac_gpio_88xx.h"
+#include "halmac_flash_88xx.h"
+
+#if HALMAC_8822B_SUPPORT
+#include "halmac_8822b/halmac_init_8822b.h"
+#endif
+
+#if HALMAC_8821C_SUPPORT
+#include "halmac_8821c/halmac_init_8821c.h"
+#endif
+
+#if HALMAC_8822C_SUPPORT
+#include "halmac_8822c/halmac_init_8822c.h"
+#endif
+
+#if HALMAC_8812F_SUPPORT
+#include "halmac_8812f/halmac_init_8812f.h"
+#endif
+
+#if HALMAC_PLATFORM_TESTPROGRAM
+#include "halmisc_api_88xx.h"
+#endif
+
+#if HALMAC_88XX_SUPPORT
+
+#define PLTFM_INFO_MALLOC_MAX_SIZE	16384
+#define PLTFM_INFO_RSVD_PG_SIZE		16384
+#define DLFW_PKT_MAX_SIZE		8192 /* need multiple of 2 */
+
+#define SYS_FUNC_EN		0xD8
+
+static void
+init_state_machine_88xx(struct halmac_adapter *adapter);
+
+static enum halmac_ret_status
+verify_io_88xx(struct halmac_adapter *adapter);
+
+static enum halmac_ret_status
+verify_send_rsvd_page_88xx(struct halmac_adapter *adapter);
+
+void
+init_adapter_param_88xx(struct halmac_adapter *adapter)
+{
+	adapter->api_registry.rx_exp_en = 1;
+	adapter->api_registry.la_mode_en = 1;
+	adapter->api_registry.cfg_drv_rsvd_pg_en = 1;
+	adapter->api_registry.sdio_cmd53_4byte_en = 1;
+
+	adapter->efuse_map = (u8 *)NULL;
+	adapter->efuse_map_valid = 0;
+	adapter->efuse_end = 0;
+
+	adapter->dlfw_pkt_size = DLFW_PKT_MAX_SIZE;
+	adapter->pltfm_info.malloc_size = PLTFM_INFO_MALLOC_MAX_SIZE;
+	adapter->pltfm_info.rsvd_pg_size = PLTFM_INFO_RSVD_PG_SIZE;
+
+	adapter->cfg_param_info.buf = NULL;
+	adapter->cfg_param_info.buf_wptr = NULL;
+	adapter->cfg_param_info.num = 0;
+	adapter->cfg_param_info.full_fifo_mode = 0;
+	adapter->cfg_param_info.buf_size = 0;
+	adapter->cfg_param_info.avl_buf_size = 0;
+	adapter->cfg_param_info.offset_accum = 0;
+	adapter->cfg_param_info.value_accum = 0;
+
+	adapter->ch_sw_info.buf = NULL;
+	adapter->ch_sw_info.buf_wptr = NULL;
+	adapter->ch_sw_info.extra_info_en = 0;
+	adapter->ch_sw_info.buf_size = 0;
+	adapter->ch_sw_info.avl_buf_size = 0;
+	adapter->ch_sw_info.total_size = 0;
+	adapter->ch_sw_info.ch_num = 0;
+
+	adapter->drv_info_size = 0;
+	adapter->tx_desc_transfer = 0;
+
+	adapter->txff_alloc.tx_fifo_pg_num = 0;
+	adapter->txff_alloc.acq_pg_num = 0;
+	adapter->txff_alloc.rsvd_boundary = 0;
+	adapter->txff_alloc.rsvd_drv_addr = 0;
+	adapter->txff_alloc.rsvd_h2c_info_addr = 0;
+	adapter->txff_alloc.rsvd_h2cq_addr = 0;
+	adapter->txff_alloc.rsvd_cpu_instr_addr = 0;
+	adapter->txff_alloc.rsvd_fw_txbuf_addr = 0;
+	adapter->txff_alloc.pub_queue_pg_num = 0;
+	adapter->txff_alloc.high_queue_pg_num = 0;
+	adapter->txff_alloc.low_queue_pg_num = 0;
+	adapter->txff_alloc.normal_queue_pg_num = 0;
+	adapter->txff_alloc.extra_queue_pg_num = 0;
+
+	adapter->txff_alloc.la_mode = HALMAC_LA_MODE_DISABLE;
+	adapter->txff_alloc.rx_fifo_exp_mode =
+					HALMAC_RX_FIFO_EXPANDING_MODE_DISABLE;
+
+	adapter->hw_cfg_info.chk_security_keyid = 0;
+	adapter->hw_cfg_info.acq_num = 8;
+	adapter->hw_cfg_info.page_size = TX_PAGE_SIZE_88XX;
+	adapter->hw_cfg_info.tx_align_size = TX_ALIGN_SIZE_88XX;
+	adapter->hw_cfg_info.txdesc_size = TX_DESC_SIZE_88XX;
+	adapter->hw_cfg_info.rxdesc_size = RX_DESC_SIZE_88XX;
+	adapter->hw_cfg_info.rx_desc_fifo_size = 0;
+
+	adapter->sdio_cmd53_4byte = HALMAC_SDIO_CMD53_4BYTE_MODE_DISABLE;
+	adapter->sdio_hw_info.io_hi_speed_flag = 0;
+	adapter->sdio_hw_info.io_indir_flag = 0;
+	adapter->sdio_hw_info.spec_ver = HALMAC_SDIO_SPEC_VER_2_00;
+	adapter->sdio_hw_info.clock_speed = 50;
+	adapter->sdio_hw_info.block_size = 512;
+	adapter->sdio_hw_info.tx_seq = 1;
+	adapter->sdio_fs.macid_map = (u8 *)NULL;
+
+	adapter->pinmux_info.wl_led = 0;
+	adapter->pinmux_info.sdio_int = 0;
+	adapter->pinmux_info.sw_io_0 = 0;
+	adapter->pinmux_info.sw_io_1 = 0;
+	adapter->pinmux_info.sw_io_2 = 0;
+	adapter->pinmux_info.sw_io_3 = 0;
+	adapter->pinmux_info.sw_io_4 = 0;
+	adapter->pinmux_info.sw_io_5 = 0;
+	adapter->pinmux_info.sw_io_6 = 0;
+	adapter->pinmux_info.sw_io_7 = 0;
+	adapter->pinmux_info.sw_io_8 = 0;
+	adapter->pinmux_info.sw_io_9 = 0;
+	adapter->pinmux_info.sw_io_10 = 0;
+	adapter->pinmux_info.sw_io_11 = 0;
+	adapter->pinmux_info.sw_io_12 = 0;
+	adapter->pinmux_info.sw_io_13 = 0;
+	adapter->pinmux_info.sw_io_14 = 0;
+	adapter->pinmux_info.sw_io_15 = 0;
+
+	adapter->pcie_refautok_en = 1;
+	adapter->pwr_off_flow_flag = 0;
+
+	adapter->rx_ignore_info.hdr_chk_mask = 1;
+	adapter->rx_ignore_info.fcs_chk_mask = 1;
+	adapter->rx_ignore_info.hdr_chk_en = 0;
+	adapter->rx_ignore_info.fcs_chk_en = 0;
+	adapter->rx_ignore_info.cck_rst_en = 0;
+	adapter->rx_ignore_info.fcs_chk_thr = HALMAC_PSF_FCS_CHK_THR_28;
+
+	init_adapter_dynamic_param_88xx(adapter);
+	init_state_machine_88xx(adapter);
+}
+
+void
+init_adapter_dynamic_param_88xx(struct halmac_adapter *adapter)
+{
+	adapter->h2c_info.seq_num = 0;
+	adapter->h2c_info.buf_fs = 0;
+}
+
+enum halmac_ret_status
+mount_api_88xx(struct halmac_adapter *adapter)
+{
+	struct halmac_api *api = NULL;
+
+	adapter->halmac_api =
+		(struct halmac_api *)PLTFM_MALLOC(sizeof(struct halmac_api));
+	if (!adapter->halmac_api)
+		return HALMAC_RET_MALLOC_FAIL;
+
+	api = (struct halmac_api *)adapter->halmac_api;
+
+	api->halmac_read_efuse = NULL;
+	api->halmac_write_efuse = NULL;
+
+	/* Mount function pointer */
+	api->halmac_register_api = register_api_88xx;
+	api->halmac_download_firmware = download_firmware_88xx;
+	api->halmac_free_download_firmware = free_download_firmware_88xx;
+	api->halmac_get_fw_version = get_fw_version_88xx;
+	api->halmac_cfg_mac_addr = cfg_mac_addr_88xx;
+	api->halmac_cfg_bssid = cfg_bssid_88xx;
+	api->halmac_cfg_transmitter_addr = cfg_transmitter_addr_88xx;
+	api->halmac_cfg_net_type = cfg_net_type_88xx;
+	api->halmac_cfg_tsf_rst = cfg_tsf_rst_88xx;
+	api->halmac_cfg_bcn_space = cfg_bcn_space_88xx;
+	api->halmac_rw_bcn_ctrl = rw_bcn_ctrl_88xx;
+	api->halmac_cfg_multicast_addr = cfg_multicast_addr_88xx;
+	api->halmac_pre_init_system_cfg = pre_init_system_cfg_88xx;
+	api->halmac_init_system_cfg = init_system_cfg_88xx;
+	api->halmac_cfg_operation_mode = cfg_operation_mode_88xx;
+	api->halmac_cfg_ch_bw = cfg_ch_bw_88xx;
+	api->halmac_cfg_bw = cfg_bw_88xx;
+	api->halmac_init_mac_cfg = init_mac_cfg_88xx;
+	api->halmac_dump_efuse_map = dump_efuse_map_88xx;
+	api->halmac_dump_efuse_map_bt = dump_efuse_map_bt_88xx;
+	api->halmac_write_efuse_bt = write_efuse_bt_88xx;
+	api->halmac_read_efuse_bt = read_efuse_bt_88xx;
+	api->halmac_cfg_efuse_auto_check = cfg_efuse_auto_check_88xx;
+	api->halmac_dump_logical_efuse_map = dump_log_efuse_map_88xx;
+	api->halmac_pg_efuse_by_map = pg_efuse_by_map_88xx;
+	api->halmac_mask_logical_efuse = mask_log_efuse_88xx;
+	api->halmac_get_efuse_size = get_efuse_size_88xx;
+	api->halmac_get_efuse_available_size = get_efuse_available_size_88xx;
+	api->halmac_get_c2h_info = get_c2h_info_88xx;
+
+	api->halmac_get_logical_efuse_size = get_log_efuse_size_88xx;
+
+	api->halmac_write_logical_efuse = write_log_efuse_88xx;
+	api->halmac_read_logical_efuse = read_logical_efuse_88xx;
+
+	api->halmac_ofld_func_cfg = ofld_func_cfg_88xx;
+	api->halmac_h2c_lb = h2c_lb_88xx;
+	api->halmac_debug = mac_debug_88xx;
+	api->halmac_cfg_parameter = cfg_parameter_88xx;
+	api->halmac_update_datapack = update_datapack_88xx;
+	api->halmac_run_datapack = run_datapack_88xx;
+	api->halmac_send_bt_coex = send_bt_coex_88xx;
+	api->halmac_verify_platform_api = verify_platform_api_88xx;
+	api->halmac_update_packet = update_packet_88xx;
+	api->halmac_bcn_ie_filter = bcn_ie_filter_88xx;
+	api->halmac_cfg_txbf = cfg_txbf_88xx;
+	api->halmac_cfg_mumimo = cfg_mumimo_88xx;
+	api->halmac_cfg_sounding = cfg_sounding_88xx;
+	api->halmac_del_sounding = del_sounding_88xx;
+	api->halmac_su_bfer_entry_init = su_bfer_entry_init_88xx;
+	api->halmac_su_bfee_entry_init = su_bfee_entry_init_88xx;
+	api->halmac_mu_bfer_entry_init = mu_bfer_entry_init_88xx;
+	api->halmac_mu_bfee_entry_init = mu_bfee_entry_init_88xx;
+	api->halmac_su_bfer_entry_del = su_bfer_entry_del_88xx;
+	api->halmac_su_bfee_entry_del = su_bfee_entry_del_88xx;
+	api->halmac_mu_bfer_entry_del = mu_bfer_entry_del_88xx;
+	api->halmac_mu_bfee_entry_del = mu_bfee_entry_del_88xx;
+
+	api->halmac_add_ch_info = add_ch_info_88xx;
+	api->halmac_add_extra_ch_info = add_extra_ch_info_88xx;
+	api->halmac_ctrl_ch_switch = ctrl_ch_switch_88xx;
+	api->halmac_p2pps = p2pps_88xx;
+	api->halmac_clear_ch_info = clear_ch_info_88xx;
+	api->halmac_send_general_info = send_general_info_88xx;
+
+	api->halmac_start_iqk = start_iqk_88xx;
+	api->halmac_ctrl_pwr_tracking = ctrl_pwr_tracking_88xx;
+	api->halmac_psd = psd_88xx;
+	api->halmac_cfg_la_mode = cfg_la_mode_88xx;
+	api->halmac_cfg_rxff_expand_mode = cfg_rxfifo_expand_mode_88xx;
+
+	api->halmac_config_security = config_security_88xx;
+	api->halmac_get_used_cam_entry_num = get_used_cam_entry_num_88xx;
+	api->halmac_read_cam_entry = read_cam_entry_88xx;
+	api->halmac_write_cam = write_cam_88xx;
+	api->halmac_clear_cam_entry = clear_cam_entry_88xx;
+
+	api->halmac_cfg_drv_rsvd_pg_num = cfg_drv_rsvd_pg_num_88xx;
+	api->halmac_get_chip_version = get_version_88xx;
+
+	api->halmac_query_status = query_status_88xx;
+	api->halmac_reset_feature = reset_ofld_feature_88xx;
+	api->halmac_check_fw_status = check_fw_status_88xx;
+	api->halmac_dump_fw_dmem = dump_fw_dmem_88xx;
+	api->halmac_cfg_max_dl_size = cfg_max_dl_size_88xx;
+
+	api->halmac_dump_fifo = dump_fifo_88xx;
+	api->halmac_get_fifo_size = get_fifo_size_88xx;
+
+	api->halmac_chk_txdesc = chk_txdesc_88xx;
+	api->halmac_dl_drv_rsvd_page = dl_drv_rsvd_page_88xx;
+	api->halmac_cfg_csi_rate = cfg_csi_rate_88xx;
+
+	api->halmac_txfifo_is_empty = txfifo_is_empty_88xx;
+	api->halmac_download_flash = download_flash_88xx;
+	api->halmac_read_flash = read_flash_88xx;
+	api->halmac_erase_flash = erase_flash_88xx;
+	api->halmac_check_flash = check_flash_88xx;
+	api->halmac_cfg_edca_para = cfg_edca_para_88xx;
+	api->halmac_pinmux_wl_led_mode = pinmux_wl_led_mode_88xx;
+	api->halmac_pinmux_wl_led_sw_ctrl = pinmux_wl_led_sw_ctrl_88xx;
+	api->halmac_pinmux_sdio_int_polarity = pinmux_sdio_int_polarity_88xx;
+	api->halmac_pinmux_gpio_mode = pinmux_gpio_mode_88xx;
+	api->halmac_pinmux_gpio_output = pinmux_gpio_output_88xx;
+	api->halmac_pinmux_pin_status = pinmux_pin_status_88xx;
+
+	api->halmac_rx_cut_amsdu_cfg = rx_cut_amsdu_cfg_88xx;
+	api->halmac_fw_snding = fw_snding_88xx;
+	api->halmac_get_mac_addr = get_mac_addr_88xx;
+
+	api->halmac_enter_cpu_sleep_mode = enter_cpu_sleep_mode_88xx;
+	api->halmac_get_cpu_mode = get_cpu_mode_88xx;
+	api->halmac_drv_fwctrl = drv_fwctrl_88xx;
+
+	if (adapter->intf == HALMAC_INTERFACE_SDIO) {
+#if HALMAC_SDIO_SUPPORT
+		api->halmac_init_sdio_cfg = init_sdio_cfg_88xx;
+		api->halmac_deinit_sdio_cfg = deinit_sdio_cfg_88xx;
+		api->halmac_cfg_rx_aggregation = cfg_sdio_rx_agg_88xx;
+		api->halmac_init_interface_cfg = init_sdio_cfg_88xx;
+		api->halmac_deinit_interface_cfg = deinit_sdio_cfg_88xx;
+		api->halmac_cfg_tx_agg_align = cfg_txagg_sdio_align_88xx;
+		api->halmac_set_bulkout_num = set_sdio_bulkout_num_88xx;
+		api->halmac_get_usb_bulkout_id = get_sdio_bulkout_id_88xx;
+		api->halmac_reg_read_indirect_32 = sdio_indirect_reg_r32_88xx;
+		api->halmac_reg_sdio_cmd53_read_n = sdio_reg_rn_88xx;
+		api->halmac_sdio_cmd53_4byte = sdio_cmd53_4byte_88xx;
+		api->halmac_sdio_hw_info = sdio_hw_info_88xx;
+
+#endif
+	} else if (adapter->intf == HALMAC_INTERFACE_USB) {
+#if HALMAC_USB_SUPPORT
+		api->halmac_init_usb_cfg = init_usb_cfg_88xx;
+		api->halmac_deinit_usb_cfg = deinit_usb_cfg_88xx;
+		api->halmac_cfg_rx_aggregation = cfg_usb_rx_agg_88xx;
+		api->halmac_init_interface_cfg = init_usb_cfg_88xx;
+		api->halmac_deinit_interface_cfg = deinit_usb_cfg_88xx;
+		api->halmac_cfg_tx_agg_align = cfg_txagg_usb_align_88xx;
+		api->halmac_tx_allowed_sdio = tx_allowed_usb_88xx;
+		api->halmac_set_bulkout_num = set_usb_bulkout_num_88xx;
+		api->halmac_get_sdio_tx_addr = get_usb_tx_addr_88xx;
+		api->halmac_get_usb_bulkout_id = get_usb_bulkout_id_88xx;
+		api->halmac_reg_read_8 = reg_r8_usb_88xx;
+		api->halmac_reg_write_8 = reg_w8_usb_88xx;
+		api->halmac_reg_read_16 = reg_r16_usb_88xx;
+		api->halmac_reg_write_16 = reg_w16_usb_88xx;
+		api->halmac_reg_read_32 = reg_r32_usb_88xx;
+		api->halmac_reg_write_32 = reg_w32_usb_88xx;
+		api->halmac_reg_read_indirect_32 = usb_indirect_reg_r32_88xx;
+		api->halmac_reg_sdio_cmd53_read_n = usb_reg_rn_88xx;
+#endif
+	} else if (adapter->intf == HALMAC_INTERFACE_PCIE) {
+#if HALMAC_PCIE_SUPPORT
+		api->halmac_init_pcie_cfg = init_pcie_cfg_88xx;
+		api->halmac_deinit_pcie_cfg = deinit_pcie_cfg_88xx;
+		api->halmac_cfg_rx_aggregation = cfg_pcie_rx_agg_88xx;
+		api->halmac_init_interface_cfg = init_pcie_cfg_88xx;
+		api->halmac_deinit_interface_cfg = deinit_pcie_cfg_88xx;
+		api->halmac_cfg_tx_agg_align = cfg_txagg_pcie_align_88xx;
+		api->halmac_tx_allowed_sdio = tx_allowed_pcie_88xx;
+		api->halmac_set_bulkout_num = set_pcie_bulkout_num_88xx;
+		api->halmac_get_sdio_tx_addr = get_pcie_tx_addr_88xx;
+		api->halmac_get_usb_bulkout_id = get_pcie_bulkout_id_88xx;
+		api->halmac_reg_read_8 = reg_r8_pcie_88xx;
+		api->halmac_reg_write_8 = reg_w8_pcie_88xx;
+		api->halmac_reg_read_16 = reg_r16_pcie_88xx;
+		api->halmac_reg_write_16 = reg_w16_pcie_88xx;
+		api->halmac_reg_read_32 = reg_r32_pcie_88xx;
+		api->halmac_reg_write_32 = reg_w32_pcie_88xx;
+		api->halmac_reg_read_indirect_32 = pcie_indirect_reg_r32_88xx;
+		api->halmac_reg_sdio_cmd53_read_n = pcie_reg_rn_88xx;
+		api->halmac_en_ref_autok_pcie = en_ref_autok_88xx;
+#endif
+	} else {
+		PLTFM_MSG_ERR("[ERR]Set halmac io function Error!!\n");
+	}
+
+	if (adapter->chip_id == HALMAC_CHIP_ID_8822B) {
+#if HALMAC_8822B_SUPPORT
+		mount_api_8822b(adapter);
+#endif
+	} else if (adapter->chip_id == HALMAC_CHIP_ID_8821C) {
+#if HALMAC_8821C_SUPPORT
+		mount_api_8821c(adapter);
+#endif
+	} else if (adapter->chip_id == HALMAC_CHIP_ID_8822C) {
+#if HALMAC_8822C_SUPPORT
+		mount_api_8822c(adapter);
+#endif
+	} else if (adapter->chip_id == HALMAC_CHIP_ID_8812F) {
+#if HALMAC_8812F_SUPPORT
+		mount_api_8812f(adapter);
+#endif
+	} else {
+		PLTFM_MSG_ERR("[ERR]Chip ID undefine!!\n");
+		return HALMAC_RET_CHIP_NOT_SUPPORT;
+	}
+
+#if HALMAC_PLATFORM_TESTPROGRAM
+	halmac_mount_misc_api_88xx(adapter);
+#endif
+
+	return HALMAC_RET_SUCCESS;
+}
+
+static void
+init_state_machine_88xx(struct halmac_adapter *adapter)
+{
+	struct halmac_state *state = &adapter->halmac_state;
+
+	init_ofld_feature_state_machine_88xx(adapter);
+
+	state->api_state = HALMAC_API_STATE_INIT;
+
+	state->dlfw_state = HALMAC_DLFW_NONE;
+	state->mac_pwr = HALMAC_MAC_POWER_OFF;
+	state->gpio_cfg_state = HALMAC_GPIO_CFG_STATE_IDLE;
+	state->rsvd_pg_state = HALMAC_RSVD_PG_STATE_IDLE;
+}
+
+void
+init_ofld_feature_state_machine_88xx(struct halmac_adapter *adapter)
+{
+	struct halmac_state *state = &adapter->halmac_state;
+
+	state->efuse_state.cmd_cnstr_state = HALMAC_CMD_CNSTR_IDLE;
+	state->efuse_state.proc_status = HALMAC_CMD_PROCESS_IDLE;
+	state->efuse_state.seq_num = adapter->h2c_info.seq_num;
+
+	state->cfg_param_state.cmd_cnstr_state = HALMAC_CMD_CNSTR_IDLE;
+	state->cfg_param_state.proc_status = HALMAC_CMD_PROCESS_IDLE;
+	state->cfg_param_state.seq_num = adapter->h2c_info.seq_num;
+
+	state->scan_state.cmd_cnstr_state = HALMAC_CMD_CNSTR_IDLE;
+	state->scan_state.proc_status = HALMAC_CMD_PROCESS_IDLE;
+	state->scan_state.seq_num = adapter->h2c_info.seq_num;
+
+	state->update_pkt_state.proc_status = HALMAC_CMD_PROCESS_IDLE;
+	state->update_pkt_state.seq_num = adapter->h2c_info.seq_num;
+
+	state->iqk_state.proc_status = HALMAC_CMD_PROCESS_IDLE;
+	state->iqk_state.seq_num = adapter->h2c_info.seq_num;
+
+	state->pwr_trk_state.proc_status = HALMAC_CMD_PROCESS_IDLE;
+	state->pwr_trk_state.seq_num = adapter->h2c_info.seq_num;
+
+	state->psd_state.proc_status = HALMAC_CMD_PROCESS_IDLE;
+	state->psd_state.seq_num = adapter->h2c_info.seq_num;
+	state->psd_state.data_size = 0;
+	state->psd_state.seg_size = 0;
+	state->psd_state.data = NULL;
+
+	state->fw_snding_state.cmd_cnstr_state = HALMAC_CMD_CNSTR_IDLE;
+	state->fw_snding_state.proc_status = HALMAC_CMD_PROCESS_IDLE;
+	state->fw_snding_state.seq_num = adapter->h2c_info.seq_num;
+
+	state->wlcpu_mode = HALMAC_WLCPU_ACTIVE;
+}
+
+/**
+ * register_api_88xx() - register feature list
+ * @adapter
+ * @registry : feature list, 1->enable 0->disable
+ * Author : Ivan Lin
+ *
+ * Default is enable all api registry
+ *
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+register_api_88xx(struct halmac_adapter *adapter,
+		  struct halmac_api_registry *registry)
+{
+	if (!registry)
+		return HALMAC_RET_NULL_POINTER;
+
+	PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
+
+	PLTFM_MEMCPY(&adapter->api_registry, registry, sizeof(*registry));
+
+	PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
+
+	return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * pre_init_system_cfg_88xx() - pre-init system config
+ * @adapter : the adapter of halmac
+ * Author : KaiYuan Chang/Ivan Lin
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+pre_init_system_cfg_88xx(struct halmac_adapter *adapter)
+{
+	u32 value32;
+	struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
+	u8 enable_bb;
+
+	PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
+
+	HALMAC_REG_W8(REG_RSV_CTRL, 0);
+
+	if (adapter->intf == HALMAC_INTERFACE_SDIO) {
+#if HALMAC_SDIO_SUPPORT
+		if (leave_sdio_suspend_88xx(adapter) != HALMAC_RET_SUCCESS)
+			return HALMAC_RET_SDIO_LEAVE_SUSPEND_FAIL;
+#endif
+	} else if (adapter->intf == HALMAC_INTERFACE_USB) {
+#if HALMAC_USB_SUPPORT
+		if (HALMAC_REG_R8(REG_SYS_CFG2 + 3) == 0x20)
+			HALMAC_REG_W8(0xFE5B, HALMAC_REG_R8(0xFE5B) | BIT(4));
+#endif
+	} else if (adapter->intf == HALMAC_INTERFACE_PCIE) {
+#if HALMAC_PCIE_SUPPORT
+		/* For PCIE power on fail issue */
+		HALMAC_REG_W8(REG_HCI_OPT_CTRL + 1,
+			      HALMAC_REG_R8(REG_HCI_OPT_CTRL + 1) | BIT(0));
+#endif
+	}
+
+	/* Config PIN Mux */
+	value32 = HALMAC_REG_R32(REG_PAD_CTRL1);
+	value32 = value32 & (~(BIT(28) | BIT(29)));
+	value32 = value32 | BIT(28) | BIT(29);
+	HALMAC_REG_W32(REG_PAD_CTRL1, value32);
+
+	value32 = HALMAC_REG_R32(REG_LED_CFG);
+	value32 = value32 & (~(BIT(25) | BIT(26)));
+	HALMAC_REG_W32(REG_LED_CFG, value32);
+
+	value32 = HALMAC_REG_R32(REG_GPIO_MUXCFG);
+	value32 = value32 & (~(BIT(2)));
+	value32 = value32 | BIT(2);
+	HALMAC_REG_W32(REG_GPIO_MUXCFG, value32);
+
+	enable_bb = 0;
+	set_hw_value_88xx(adapter, HALMAC_HW_EN_BB_RF, &enable_bb);
+
+	if (HALMAC_REG_R8(REG_SYS_CFG1 + 2) & BIT(4)) {
+		PLTFM_MSG_ERR("[ERR]test mode!!\n");
+		return HALMAC_RET_WLAN_MODE_FAIL;
+	}
+
+	PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
+
+	return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * init_system_cfg_88xx() -  init system config
+ * @adapter : the adapter of halmac
+ * Author : KaiYuan Chang/Ivan Lin
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+init_system_cfg_88xx(struct halmac_adapter *adapter)
+{
+	struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
+	u32 tmp = 0;
+	u32 value32;
+	enum halmac_ret_status status;
+	u8 hwval;
+
+	PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
+
+	if (adapter->intf == HALMAC_INTERFACE_PCIE) {
+		hwval = 1;
+		status = api->halmac_set_hw_value(adapter,
+						  HALMAC_HW_PCIE_REF_AUTOK,
+						  &hwval);
+		if (status != HALMAC_RET_SUCCESS)
+			return status;
+	}
+
+	value32 = HALMAC_REG_R32(REG_CPU_DMEM_CON) | BIT_WL_PLATFORM_RST;
+#if HALMAC_8822C_SUPPORT
+	if (adapter->chip_id != HALMAC_CHIP_ID_8822B &&
+	    adapter->chip_id != HALMAC_CHIP_ID_8821C)
+		value32 |= BIT_DDMA_EN;
+#endif
+	HALMAC_REG_W32(REG_CPU_DMEM_CON, value32);
+
+	HALMAC_REG_W8(REG_SYS_FUNC_EN + 1, SYS_FUNC_EN);
+#if HALMAC_8822B_SUPPORT
+	/* cpu_en is related to wlan tx in 8822B hw design */
+	/* 8822B should enable cpu_en in init flow */
+	if (adapter->chip_id == HALMAC_CHIP_ID_8822B)
+		HALMAC_REG_W8_SET(REG_SYS_FUNC_EN + 1, BIT(2));
+#endif
+	/*disable boot-from-flash for driver's DL FW*/
+	tmp = HALMAC_REG_R32(REG_MCUFW_CTRL);
+	if (tmp & BIT_BOOT_FSPI_EN) {
+		HALMAC_REG_W32(REG_MCUFW_CTRL, tmp & (~BIT_BOOT_FSPI_EN));
+		value32 = HALMAC_REG_R32(REG_GPIO_MUXCFG) & (~BIT_FSPI_EN);
+		HALMAC_REG_W32(REG_GPIO_MUXCFG, value32);
+	}
+
+	PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
+
+	return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * init_mac_cfg_88xx() - config page1~page7 register
+ * @adapter : the adapter of halmac
+ * @mode : trx mode
+ * Author : KaiYuan Chang/Ivan Lin
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+init_mac_cfg_88xx(struct halmac_adapter *adapter, enum halmac_trx_mode mode)
+{
+	struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
+	enum halmac_ret_status status = HALMAC_RET_SUCCESS;
+
+	PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
+
+	status = api->halmac_init_trx_cfg(adapter, mode);
+	if (status != HALMAC_RET_SUCCESS) {
+		PLTFM_MSG_ERR("[ERR]init trx %x\n", status);
+		return status;
+	}
+
+	status = api->halmac_init_protocol_cfg(adapter);
+	if (status != HALMAC_RET_SUCCESS) {
+		PLTFM_MSG_ERR("[ERR]init ptcl %x\n", status);
+		return status;
+	}
+
+	status = api->halmac_init_edca_cfg(adapter);
+	if (status != HALMAC_RET_SUCCESS) {
+		PLTFM_MSG_ERR("[ERR]init edca %x\n", status);
+		return status;
+	}
+
+	status = api->halmac_init_wmac_cfg(adapter);
+	if (status != HALMAC_RET_SUCCESS) {
+		PLTFM_MSG_ERR("[ERR]init wmac %x\n", status);
+		return status;
+	}
+
+	PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
+
+	return status;
+}
+
+/**
+ * reset_ofld_feature_88xx() -reset async api cmd status
+ * @adapter : the adapter of halmac
+ * @feature_id : feature_id
+ * Author : Ivan Lin/KaiYuan Chang
+ * Return : enum halmac_ret_status.
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+reset_ofld_feature_88xx(struct halmac_adapter *adapter,
+			enum halmac_feature_id feature_id)
+{
+	struct halmac_state *state = &adapter->halmac_state;
+
+	PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
+
+	switch (feature_id) {
+	case HALMAC_FEATURE_CFG_PARA:
+		state->cfg_param_state.proc_status = HALMAC_CMD_PROCESS_IDLE;
+		state->cfg_param_state.cmd_cnstr_state = HALMAC_CMD_CNSTR_IDLE;
+		break;
+	case HALMAC_FEATURE_DUMP_PHYSICAL_EFUSE:
+	case HALMAC_FEATURE_DUMP_LOGICAL_EFUSE:
+		state->efuse_state.proc_status = HALMAC_CMD_PROCESS_IDLE;
+		state->efuse_state.cmd_cnstr_state = HALMAC_CMD_CNSTR_IDLE;
+		break;
+	case HALMAC_FEATURE_CHANNEL_SWITCH:
+		state->scan_state.proc_status = HALMAC_CMD_PROCESS_IDLE;
+		state->scan_state.cmd_cnstr_state = HALMAC_CMD_CNSTR_IDLE;
+		break;
+	case HALMAC_FEATURE_UPDATE_PACKET:
+		state->update_pkt_state.proc_status = HALMAC_CMD_PROCESS_IDLE;
+		break;
+	case HALMAC_FEATURE_IQK:
+		state->iqk_state.proc_status = HALMAC_CMD_PROCESS_IDLE;
+		break;
+	case HALMAC_FEATURE_POWER_TRACKING:
+		state->pwr_trk_state.proc_status = HALMAC_CMD_PROCESS_IDLE;
+		break;
+	case HALMAC_FEATURE_PSD:
+		state->psd_state.proc_status = HALMAC_CMD_PROCESS_IDLE;
+		break;
+	case HALMAC_FEATURE_FW_SNDING:
+		state->fw_snding_state.proc_status = HALMAC_CMD_PROCESS_IDLE;
+		state->fw_snding_state.cmd_cnstr_state = HALMAC_CMD_CNSTR_IDLE;
+		break;
+	case HALMAC_FEATURE_ALL:
+		state->cfg_param_state.proc_status = HALMAC_CMD_PROCESS_IDLE;
+		state->cfg_param_state.cmd_cnstr_state = HALMAC_CMD_CNSTR_IDLE;
+		state->efuse_state.proc_status = HALMAC_CMD_PROCESS_IDLE;
+		state->efuse_state.cmd_cnstr_state = HALMAC_CMD_CNSTR_IDLE;
+		state->scan_state.proc_status = HALMAC_CMD_PROCESS_IDLE;
+		state->scan_state.cmd_cnstr_state = HALMAC_CMD_CNSTR_IDLE;
+		state->update_pkt_state.proc_status = HALMAC_CMD_PROCESS_IDLE;
+		state->iqk_state.proc_status = HALMAC_CMD_PROCESS_IDLE;
+		state->pwr_trk_state.proc_status = HALMAC_CMD_PROCESS_IDLE;
+		state->psd_state.proc_status = HALMAC_CMD_PROCESS_IDLE;
+		state->fw_snding_state.proc_status = HALMAC_CMD_PROCESS_IDLE;
+		state->fw_snding_state.cmd_cnstr_state = HALMAC_CMD_CNSTR_IDLE;
+		break;
+	default:
+		PLTFM_MSG_ERR("[ERR]invalid feature id\n");
+		return HALMAC_RET_INVALID_FEATURE_ID;
+	}
+
+	PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
+
+	return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * (debug API)verify_platform_api_88xx() - verify platform api
+ * @adapter : the adapter of halmac
+ * Author : KaiYuan Chang/Ivan Lin
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+verify_platform_api_88xx(struct halmac_adapter *adapter)
+{
+	enum halmac_ret_status ret_status = HALMAC_RET_SUCCESS;
+
+	PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
+
+	ret_status = verify_io_88xx(adapter);
+
+	if (ret_status != HALMAC_RET_SUCCESS)
+		return ret_status;
+
+	if (adapter->txff_alloc.la_mode != HALMAC_LA_MODE_FULL)
+		ret_status = verify_send_rsvd_page_88xx(adapter);
+
+	if (ret_status != HALMAC_RET_SUCCESS)
+		return ret_status;
+
+	PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
+
+	return ret_status;
+}
+
+void
+tx_desc_chksum_88xx(struct halmac_adapter *adapter, u8 enable)
+{
+	u16 value16;
+	struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
+
+	PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
+
+	adapter->tx_desc_checksum = enable;
+
+	value16 = HALMAC_REG_R16(REG_TXDMA_OFFSET_CHK);
+	if (enable == 1)
+		HALMAC_REG_W16(REG_TXDMA_OFFSET_CHK, value16 | BIT(13));
+	else
+		HALMAC_REG_W16(REG_TXDMA_OFFSET_CHK, value16 & ~BIT(13));
+}
+
+static enum halmac_ret_status
+verify_io_88xx(struct halmac_adapter *adapter)
+{
+	u8 value8;
+	u8 wvalue8;
+	u32 value32;
+	u32 value32_2;
+	u32 wvalue32;
+	u32 offset;
+	enum halmac_ret_status ret_status = HALMAC_RET_SUCCESS;
+
+	if (adapter->intf == HALMAC_INTERFACE_SDIO) {
+		offset = REG_PAGE5_DUMMY;
+		if (0 == (offset & 0xFFFF0000))
+			offset |= WLAN_IOREG_OFFSET;
+#if HALMAC_SDIO_SUPPORT
+		ret_status = cnv_to_sdio_bus_offset_88xx(adapter, &offset);
+#else
+		return HALMAC_RET_WRONG_INTF;
+#endif
+		/* Verify CMD52 R/W */
+		wvalue8 = 0xab;
+		PLTFM_SDIO_CMD52_W(offset, wvalue8);
+
+		value8 = PLTFM_SDIO_CMD52_R(offset);
+
+		if (value8 != wvalue8) {
+			PLTFM_MSG_ERR("[ERR]cmd52 r/w\n");
+			ret_status = HALMAC_RET_PLATFORM_API_INCORRECT;
+		}
+
+		/* Verify CMD53 R/W */
+		PLTFM_SDIO_CMD52_W(offset, 0xaa);
+		PLTFM_SDIO_CMD52_W(offset + 1, 0xbb);
+		PLTFM_SDIO_CMD52_W(offset + 2, 0xcc);
+		PLTFM_SDIO_CMD52_W(offset + 3, 0xdd);
+
+		value32 = PLTFM_SDIO_CMD53_R32(offset);
+
+		if (value32 != 0xddccbbaa) {
+			PLTFM_MSG_ERR("[ERR]cmd53 r\n");
+			ret_status = HALMAC_RET_PLATFORM_API_INCORRECT;
+		}
+
+		wvalue32 = 0x11223344;
+		PLTFM_SDIO_CMD53_W32(offset, wvalue32);
+
+		value32 = PLTFM_SDIO_CMD53_R32(offset);
+
+		if (value32 != wvalue32) {
+			PLTFM_MSG_ERR("[ERR]cmd53 w\n");
+			ret_status = HALMAC_RET_PLATFORM_API_INCORRECT;
+		}
+
+		/* value32 should be 0x33441122 */
+		value32 = PLTFM_SDIO_CMD53_R32(offset + 2);
+
+		wvalue32 = 0x11225566;
+		PLTFM_SDIO_CMD53_W32(offset, wvalue32);
+
+		/* value32 should be 0x55661122 */
+		value32_2 = PLTFM_SDIO_CMD53_R32(offset + 2);
+		if (value32_2 == value32) {
+			PLTFM_MSG_ERR("[ERR]cmd52 is used\n");
+			ret_status = HALMAC_RET_PLATFORM_API_INCORRECT;
+		}
+	} else {
+		wvalue32 = 0x77665511;
+		PLTFM_REG_W32(REG_PAGE5_DUMMY, wvalue32);
+
+		value32 = PLTFM_REG_R32(REG_PAGE5_DUMMY);
+		if (value32 != wvalue32) {
+			PLTFM_MSG_ERR("[ERR]reg rw\n");
+			ret_status = HALMAC_RET_PLATFORM_API_INCORRECT;
+		}
+	}
+
+	return ret_status;
+}
+
+static enum halmac_ret_status
+verify_send_rsvd_page_88xx(struct halmac_adapter *adapter)
+{
+	u8 txdesc_size = adapter->hw_cfg_info.txdesc_size;
+	u8 *rsvd_buf = NULL;
+	u8 *rsvd_page = NULL;
+	u32 i;
+	u32 pkt_size = 64;
+	u32 payload = 0xab;
+	enum halmac_ret_status ret_status = HALMAC_RET_SUCCESS;
+
+	rsvd_buf = (u8 *)PLTFM_MALLOC(pkt_size);
+
+	if (!rsvd_buf) {
+		PLTFM_MSG_ERR("[ERR]rsvd buf malloc!!\n");
+		return HALMAC_RET_MALLOC_FAIL;
+	}
+
+	PLTFM_MEMSET(rsvd_buf, (u8)payload, pkt_size);
+
+	ret_status = dl_rsvd_page_88xx(adapter,
+				       adapter->txff_alloc.rsvd_boundary,
+				       rsvd_buf, pkt_size);
+	if (ret_status != HALMAC_RET_SUCCESS) {
+		PLTFM_FREE(rsvd_buf, pkt_size);
+		return ret_status;
+	}
+
+	rsvd_page = (u8 *)PLTFM_MALLOC(pkt_size + txdesc_size);
+
+	if (!rsvd_page) {
+		PLTFM_MSG_ERR("[ERR]rsvd page malloc!!\n");
+		PLTFM_FREE(rsvd_buf, pkt_size);
+		return HALMAC_RET_MALLOC_FAIL;
+	}
+
+	PLTFM_MEMSET(rsvd_page, 0x00, pkt_size + txdesc_size);
+
+	ret_status = dump_fifo_88xx(adapter, HAL_FIFO_SEL_RSVD_PAGE, 0,
+				    pkt_size + txdesc_size, rsvd_page);
+
+	if (ret_status != HALMAC_RET_SUCCESS) {
+		PLTFM_FREE(rsvd_buf, pkt_size);
+		PLTFM_FREE(rsvd_page, pkt_size + txdesc_size);
+		return ret_status;
+	}
+
+	for (i = 0; i < pkt_size; i++) {
+		if (*(rsvd_buf + i) != *(rsvd_page + (i + txdesc_size))) {
+			PLTFM_MSG_ERR("[ERR]Compare RSVD page Fail\n");
+			ret_status = HALMAC_RET_PLATFORM_API_INCORRECT;
+		}
+	}
+
+	PLTFM_FREE(rsvd_buf, pkt_size);
+	PLTFM_FREE(rsvd_page, pkt_size + txdesc_size);
+
+	return ret_status;
+}
+
+enum halmac_ret_status
+pg_num_parser_88xx(struct halmac_adapter *adapter, enum halmac_trx_mode mode,
+		   struct halmac_pg_num *tbl)
+{
+	u8 flag;
+	u16 hpq_num = 0;
+	u16 lpq_num = 0;
+	u16 npq_num = 0;
+	u16 gapq_num = 0;
+	u16 expq_num = 0;
+	u16 pubq_num = 0;
+	u32 i = 0;
+
+	flag = 0;
+	for (i = 0; i < HALMAC_TRX_MODE_MAX; i++) {
+		if (mode == tbl[i].mode) {
+			hpq_num = tbl[i].hq_num;
+			lpq_num = tbl[i].lq_num;
+			npq_num = tbl[i].nq_num;
+			expq_num = tbl[i].exq_num;
+			gapq_num = tbl[i].gap_num;
+			pubq_num = adapter->txff_alloc.acq_pg_num - hpq_num -
+					lpq_num - npq_num - expq_num - gapq_num;
+			flag = 1;
+			PLTFM_MSG_TRACE("[TRACE]%s done\n", __func__);
+			break;
+		}
+	}
+
+	if (flag == 0) {
+		PLTFM_MSG_ERR("[ERR]trx mode!!\n");
+		return HALMAC_RET_TRX_MODE_NOT_SUPPORT;
+	}
+
+	if (adapter->txff_alloc.acq_pg_num <
+	    hpq_num + lpq_num + npq_num + expq_num + gapq_num) {
+		PLTFM_MSG_ERR("[ERR]acqnum = %d\n",
+			      adapter->txff_alloc.acq_pg_num);
+		PLTFM_MSG_ERR("[ERR]hpq_num = %d\n", hpq_num);
+		PLTFM_MSG_ERR("[ERR]LPQ_num = %d\n", lpq_num);
+		PLTFM_MSG_ERR("[ERR]npq_num = %d\n", npq_num);
+		PLTFM_MSG_ERR("[ERR]EPQ_num = %d\n", expq_num);
+		PLTFM_MSG_ERR("[ERR]gapq_num = %d\n", gapq_num);
+		return HALMAC_RET_CFG_TXFIFO_PAGE_FAIL;
+	}
+
+	adapter->txff_alloc.high_queue_pg_num = hpq_num;
+	adapter->txff_alloc.low_queue_pg_num = lpq_num;
+	adapter->txff_alloc.normal_queue_pg_num = npq_num;
+	adapter->txff_alloc.extra_queue_pg_num = expq_num;
+	adapter->txff_alloc.pub_queue_pg_num = pubq_num;
+
+	return HALMAC_RET_SUCCESS;
+}
+
+enum halmac_ret_status
+rqpn_parser_88xx(struct halmac_adapter *adapter, enum halmac_trx_mode mode,
+		 struct halmac_rqpn *tbl)
+{
+	u8 flag;
+	u32 i;
+
+	flag = 0;
+	for (i = 0; i < HALMAC_TRX_MODE_MAX; i++) {
+		if (mode == tbl[i].mode) {
+			adapter->pq_map[HALMAC_PQ_MAP_VO] = tbl[i].dma_map_vo;
+			adapter->pq_map[HALMAC_PQ_MAP_VI] = tbl[i].dma_map_vi;
+			adapter->pq_map[HALMAC_PQ_MAP_BE] = tbl[i].dma_map_be;
+			adapter->pq_map[HALMAC_PQ_MAP_BK] = tbl[i].dma_map_bk;
+			adapter->pq_map[HALMAC_PQ_MAP_MG] = tbl[i].dma_map_mg;
+			adapter->pq_map[HALMAC_PQ_MAP_HI] = tbl[i].dma_map_hi;
+			flag = 1;
+			PLTFM_MSG_TRACE("[TRACE]%s done\n", __func__);
+			break;
+		}
+	}
+
+	if (flag == 0) {
+		PLTFM_MSG_ERR("[ERR]trx mdoe!!\n");
+		return HALMAC_RET_TRX_MODE_NOT_SUPPORT;
+	}
+
+	return HALMAC_RET_SUCCESS;
+}
+
+#endif /* HALMAC_88XX_SUPPORT */
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/halmac/halmac_88xx/halmac_init_88xx.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/halmac/halmac_88xx/halmac_init_88xx.h
--- linux-5.6.3/3rdparty/rtl8821ce/hal/halmac/halmac_88xx/halmac_init_88xx.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/halmac/halmac_88xx/halmac_init_88xx.h	2020-04-10 16:35:06.793658994 +0300
@@ -0,0 +1,68 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ ******************************************************************************/
+
+#ifndef _HALMAC_INIT_88XX_H_
+#define _HALMAC_INIT_88XX_H_
+
+#include "../halmac_api.h"
+
+#if HALMAC_88XX_SUPPORT
+
+enum halmac_ret_status
+register_api_88xx(struct halmac_adapter *adapter,
+		  struct halmac_api_registry *registry);
+
+void
+init_adapter_param_88xx(struct halmac_adapter *adapter);
+
+void
+init_adapter_dynamic_param_88xx(struct halmac_adapter *adapter);
+
+enum halmac_ret_status
+mount_api_88xx(struct halmac_adapter *adapter);
+
+enum halmac_ret_status
+pre_init_system_cfg_88xx(struct halmac_adapter *adapter);
+
+enum halmac_ret_status
+init_system_cfg_88xx(struct halmac_adapter *adapter);
+
+enum halmac_ret_status
+init_mac_cfg_88xx(struct halmac_adapter *adapter, enum halmac_trx_mode mode);
+
+enum halmac_ret_status
+reset_ofld_feature_88xx(struct halmac_adapter *adapter,
+			enum halmac_feature_id feature_id);
+
+enum halmac_ret_status
+verify_platform_api_88xx(struct halmac_adapter *adapter);
+
+void
+tx_desc_chksum_88xx(struct halmac_adapter *adapter, u8 enable);
+
+enum halmac_ret_status
+pg_num_parser_88xx(struct halmac_adapter *adapter, enum halmac_trx_mode mode,
+		   struct halmac_pg_num *tbl);
+
+enum halmac_ret_status
+rqpn_parser_88xx(struct halmac_adapter *adapter, enum halmac_trx_mode mode,
+		 struct halmac_rqpn *tbl);
+
+void
+init_ofld_feature_state_machine_88xx(struct halmac_adapter *adapter);
+
+#endif /* HALMAC_88XX_SUPPORT */
+
+#endif/* _HALMAC_INIT_88XX_H_ */
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/halmac/halmac_88xx/halmac_mimo_88xx.c linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/halmac/halmac_88xx/halmac_mimo_88xx.c
--- linux-5.6.3/3rdparty/rtl8821ce/hal/halmac/halmac_88xx/halmac_mimo_88xx.c	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/halmac/halmac_88xx/halmac_mimo_88xx.c	2020-04-10 16:35:06.793658994 +0300
@@ -0,0 +1,878 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ ******************************************************************************/
+
+#include "halmac_mimo_88xx.h"
+#include "halmac_88xx_cfg.h"
+#include "halmac_common_88xx.h"
+#include "halmac_init_88xx.h"
+
+#if HALMAC_88XX_SUPPORT
+
+#define TXBF_CTRL_CFG	(BIT_R_ENABLE_NDPA | BIT_USE_NDPA_PARAMETER | \
+			 BIT_R_EN_NDPA_INT | BIT_DIS_NDP_BFEN)
+
+static void
+cfg_mu_bfee_88xx(struct halmac_adapter *adapter,
+		 struct halmac_cfg_mumimo_para *param);
+
+static void
+cfg_mu_bfer_88xx(struct halmac_adapter *adapter,
+		 struct halmac_cfg_mumimo_para *param);
+
+static enum halmac_cmd_construct_state
+fw_snding_cmd_cnstr_state_88xx(struct halmac_adapter *adapter);
+
+static enum halmac_ret_status
+cnv_fw_snding_state_88xx(struct halmac_adapter *adapter,
+			 enum halmac_cmd_construct_state dest_state);
+
+static u8
+snding_pkt_chk_88xx(struct halmac_adapter *adapter, u8 *pkt);
+
+/**
+ * cfg_txbf_88xx() - enable/disable specific user's txbf
+ * @adapter : the adapter of halmac
+ * @userid : su bfee userid = 0 or 1 to apply TXBF
+ * @bw : the sounding bandwidth
+ * @txbf_en : 0: disable TXBF, 1: enable TXBF
+ * Author : chunchu
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+cfg_txbf_88xx(struct halmac_adapter *adapter, u8 userid, enum halmac_bw bw,
+	      u8 txbf_en)
+{
+	u16 tmp42c = 0;
+	struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
+
+	if (txbf_en) {
+		switch (bw) {
+		case HALMAC_BW_80:
+			tmp42c |= BIT_R_TXBF0_80M;
+			__attribute__((__fallthrough__));
+		case HALMAC_BW_40:
+			tmp42c |= BIT_R_TXBF0_40M;
+			__attribute__((__fallthrough__));
+		case HALMAC_BW_20:
+			tmp42c |= BIT_R_TXBF0_20M;
+			break;
+		default:
+			return HALMAC_RET_INVALID_SOUNDING_SETTING;
+		}
+	}
+
+	switch (userid) {
+	case 0:
+		tmp42c |= HALMAC_REG_R16(REG_TXBF_CTRL) &
+			~(BIT_R_TXBF0_20M | BIT_R_TXBF0_40M | BIT_R_TXBF0_80M);
+		HALMAC_REG_W16(REG_TXBF_CTRL, tmp42c);
+		break;
+	case 1:
+		tmp42c |= HALMAC_REG_R16(REG_TXBF_CTRL + 2) &
+			~(BIT_R_TXBF0_20M | BIT_R_TXBF0_40M | BIT_R_TXBF0_80M);
+		HALMAC_REG_W16(REG_TXBF_CTRL + 2, tmp42c);
+		break;
+	default:
+		return HALMAC_RET_INVALID_SOUNDING_SETTING;
+	}
+
+	PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
+
+	return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * cfg_mumimo_88xx() -config mumimo
+ * @adapter : the adapter of halmac
+ * @param : parameters to configure MU PPDU Tx/Rx
+ * Author : chunchu
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+cfg_mumimo_88xx(struct halmac_adapter *adapter,
+		struct halmac_cfg_mumimo_para *param)
+{
+	if (param->role == HAL_BFEE)
+		cfg_mu_bfee_88xx(adapter, param);
+	else
+		cfg_mu_bfer_88xx(adapter, param);
+
+	PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
+
+	return HALMAC_RET_SUCCESS;
+}
+
+static void
+cfg_mu_bfee_88xx(struct halmac_adapter *adapter,
+		 struct halmac_cfg_mumimo_para *param)
+{
+	u8 mu_tbl_sel;
+	u8 tmp14c0;
+	struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
+
+	tmp14c0 = HALMAC_REG_R8(REG_MU_TX_CTL) & ~BIT_MASK_R_MU_TABLE_VALID;
+	HALMAC_REG_W8(REG_MU_TX_CTL, (tmp14c0 | BIT(0) | BIT(1)) & ~(BIT(7)));
+
+	/*config GID valid table and user position table*/
+	mu_tbl_sel = HALMAC_REG_R8(REG_MU_TX_CTL + 1) & 0xF8;
+
+	HALMAC_REG_W8(REG_MU_TX_CTL + 1, mu_tbl_sel);
+	HALMAC_REG_W32(REG_MU_STA_GID_VLD, param->given_gid_tab[0]);
+	HALMAC_REG_W32(REG_MU_STA_USER_POS_INFO, param->given_user_pos[0]);
+	HALMAC_REG_W32(REG_MU_STA_USER_POS_INFO + 4, param->given_user_pos[1]);
+
+	HALMAC_REG_W8(REG_MU_TX_CTL + 1, mu_tbl_sel | 1);
+	HALMAC_REG_W32(REG_MU_STA_GID_VLD, param->given_gid_tab[1]);
+	HALMAC_REG_W32(REG_MU_STA_USER_POS_INFO, param->given_user_pos[2]);
+	HALMAC_REG_W32(REG_MU_STA_USER_POS_INFO + 4, param->given_user_pos[3]);
+}
+
+static void
+cfg_mu_bfer_88xx(struct halmac_adapter *adapter,
+		 struct halmac_cfg_mumimo_para *param)
+{
+	u8 i;
+	u8 idx;
+	u8 id0;
+	u8 id1;
+	u8 gid;
+	u8 mu_tbl_sel;
+	u8 mu_tbl_valid = 0;
+	u32 gid_valid[6] = {0};
+	struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
+
+	if (param->mu_tx_en == 0) {
+		HALMAC_REG_W8(REG_MU_TX_CTL,
+			      HALMAC_REG_R8(REG_MU_TX_CTL) & ~(BIT(7)));
+		return;
+	}
+
+	for (idx = 0; idx < 15; idx++) {
+		if (idx < 5) {
+			/*grouping_bitmap bit0~4, MU_STA0 with MUSTA1~5*/
+			id0 = 0;
+			id1 = (u8)(idx + 1);
+		} else if (idx < 9) {
+			/*grouping_bitmap bit5~8, MU_STA1 with MUSTA2~5*/
+			id0 = 1;
+			id1 = (u8)(idx - 3);
+		} else if (idx < 12) {
+			/*grouping_bitmap bit9~11, MU_STA2 with MUSTA3~5*/
+			id0 = 2;
+			id1 = (u8)(idx - 6);
+		} else if (idx < 14) {
+			/*grouping_bitmap bit12~13, MU_STA3 with MUSTA4~5*/
+			id0 = 3;
+			id1 = (u8)(idx - 8);
+		} else {
+			/*grouping_bitmap bit14, MU_STA4 with MUSTA5*/
+			id0 = 4;
+			id1 = (u8)(idx - 9);
+		}
+		if (param->grouping_bitmap & BIT(idx)) {
+			/*Pair 1*/
+			gid = (idx << 1) + 1;
+			gid_valid[id0] |= (BIT(gid));
+			gid_valid[id1] |= (BIT(gid));
+			/*Pair 2*/
+			gid += 1;
+			gid_valid[id0] |= (BIT(gid));
+			gid_valid[id1] |= (BIT(gid));
+		} else {
+			/*Pair 1*/
+			gid = (idx << 1) + 1;
+			gid_valid[id0] &= ~(BIT(gid));
+			gid_valid[id1] &= ~(BIT(gid));
+			/*Pair 2*/
+			gid += 1;
+			gid_valid[id0] &= ~(BIT(gid));
+			gid_valid[id1] &= ~(BIT(gid));
+		}
+	}
+
+	/*set MU STA GID valid TABLE*/
+	mu_tbl_sel = HALMAC_REG_R8(REG_MU_TX_CTL + 1) & 0xF8;
+	for (idx = 0; idx < 6; idx++) {
+		HALMAC_REG_W8(REG_MU_TX_CTL + 1, idx | mu_tbl_sel);
+		HALMAC_REG_W32(REG_MU_STA_GID_VLD, gid_valid[idx]);
+	}
+
+	/*To validate the sounding successful MU STA and enable MU TX*/
+	for (i = 0; i < 6; i++) {
+		if (param->sounding_sts[i] == 1)
+			mu_tbl_valid |= BIT(i);
+	}
+	HALMAC_REG_W8(REG_MU_TX_CTL, mu_tbl_valid | BIT(7));
+}
+
+/**
+ * cfg_sounding_88xx() - configure general sounding
+ * @adapter : the adapter of halmac
+ * @role : driver's role, BFer or BFee
+ * @rate : set ndpa tx rate if driver is BFer,
+ * or set csi response rate if driver is BFee
+ * Author : chunchu
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+cfg_sounding_88xx(struct halmac_adapter *adapter, enum halmac_snd_role role,
+		  enum halmac_data_rate rate)
+{
+	struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
+	u32 tmp6dc = 0;
+	u8 csi_rsc = 0x1;
+
+	/*use ndpa rx rate to decide csi rate*/
+	tmp6dc = HALMAC_REG_R32(REG_BBPSF_CTRL) | BIT_WMAC_USE_NDPARATE
+							| (csi_rsc << 13);
+
+	switch (role) {
+	case HAL_BFER:
+		HALMAC_REG_W32_SET(REG_TXBF_CTRL, TXBF_CTRL_CFG);
+		HALMAC_REG_W8(REG_NDPA_RATE, rate);
+		HALMAC_REG_W8_CLR(REG_NDPA_OPT_CTRL, BIT(0) | BIT(1));
+		HALMAC_REG_W8(REG_SND_PTCL_CTRL + 1, 0x2 | BIT(7));
+		HALMAC_REG_W8(REG_SND_PTCL_CTRL + 2, 0x2);
+		break;
+	case HAL_BFEE:
+		HALMAC_REG_W8(REG_SND_PTCL_CTRL, 0xDB);
+		HALMAC_REG_W8(REG_SND_PTCL_CTRL + 3, 0x26);
+		HALMAC_REG_W8_CLR(REG_RXFLTMAP1, BIT(4));
+		HALMAC_REG_W8_CLR(REG_RXFLTMAP4, BIT(4));
+		break;
+	default:
+		return HALMAC_RET_INVALID_SOUNDING_SETTING;
+	}
+
+	/*AP mode set tx gid to 63*/
+	/*STA mode set tx gid to 0*/
+	if (BIT_GET_NETYPE0(HALMAC_REG_R32(REG_CR)) == 0x3)
+		HALMAC_REG_W32(REG_BBPSF_CTRL, tmp6dc | BIT(12));
+	else
+		HALMAC_REG_W32(REG_BBPSF_CTRL, tmp6dc & ~(BIT(12)));
+
+	PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
+
+	return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * del_sounding_88xx() - reset general sounding
+ * @adapter : the adapter of halmac
+ * @role : driver's role, BFer or BFee
+ * Author : chunchu
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+del_sounding_88xx(struct halmac_adapter *adapter, enum halmac_snd_role role)
+{
+	struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
+
+	switch (role) {
+	case HAL_BFER:
+		HALMAC_REG_W8(REG_TXBF_CTRL + 3, 0);
+		break;
+	case HAL_BFEE:
+		HALMAC_REG_W8(REG_SND_PTCL_CTRL, 0);
+		break;
+	default:
+		return HALMAC_RET_INVALID_SOUNDING_SETTING;
+	}
+
+	PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
+
+	return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * su_bfee_entry_init_88xx() - config SU beamformee's registers
+ * @adapter : the adapter of halmac
+ * @userid : SU bfee userid = 0 or 1 to be added
+ * @paid : partial AID of this bfee
+ * Author : chunchu
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+su_bfee_entry_init_88xx(struct halmac_adapter *adapter, u8 userid, u16 paid)
+{
+	u16 tmp42c = 0;
+	u16 tmp168x = 0;
+	struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
+
+	switch (userid) {
+	case 0:
+		tmp42c = HALMAC_REG_R16(REG_TXBF_CTRL) &
+				~(BIT_MASK_R_TXBF0_AID | BIT_R_TXBF0_20M |
+				BIT_R_TXBF0_40M | BIT_R_TXBF0_80M);
+		HALMAC_REG_W16(REG_TXBF_CTRL, tmp42c | paid);
+		HALMAC_REG_W16(REG_ASSOCIATED_BFMEE_SEL, paid);
+		#if HALMAC_8822C_SUPPORT
+		if (adapter->chip_id == HALMAC_CHIP_ID_8822C)
+			HALMAC_REG_W16(REG_ASSOCIATED_BFMEE_SEL, paid | BIT(9));
+		#endif
+		break;
+	case 1:
+		tmp42c = HALMAC_REG_R16(REG_TXBF_CTRL + 2) &
+				~(BIT_MASK_R_TXBF1_AID | BIT_R_TXBF0_20M |
+				BIT_R_TXBF0_40M | BIT_R_TXBF0_80M);
+		HALMAC_REG_W16(REG_TXBF_CTRL + 2, tmp42c | paid);
+		HALMAC_REG_W16(REG_ASSOCIATED_BFMEE_SEL + 2, paid | BIT(9));
+		break;
+	case 2:
+		tmp168x = HALMAC_REG_R16(REG_WMAC_ASSOCIATED_MU_BFMEE2);
+		tmp168x = BIT_CLEAR_WMAC_MU_BFEE2_AID(tmp168x);
+		tmp168x |= (paid | BIT(9));
+		HALMAC_REG_W16(REG_WMAC_ASSOCIATED_MU_BFMEE2, tmp168x);
+		break;
+	case 3:
+		tmp168x = HALMAC_REG_R16(REG_WMAC_ASSOCIATED_MU_BFMEE3);
+		tmp168x = BIT_CLEAR_WMAC_MU_BFEE3_AID(tmp168x);
+		tmp168x |= (paid | BIT(9));
+		HALMAC_REG_W16(REG_WMAC_ASSOCIATED_MU_BFMEE3, tmp168x);
+		break;
+	case 4:
+		tmp168x = HALMAC_REG_R16(REG_WMAC_ASSOCIATED_MU_BFMEE4);
+		tmp168x = BIT_CLEAR_WMAC_MU_BFEE4_AID(tmp168x);
+		tmp168x |= (paid | BIT(9));
+		HALMAC_REG_W16(REG_WMAC_ASSOCIATED_MU_BFMEE4, tmp168x);
+		break;
+	case 5:
+		tmp168x = HALMAC_REG_R16(REG_WMAC_ASSOCIATED_MU_BFMEE5);
+		tmp168x = BIT_CLEAR_WMAC_MU_BFEE5_AID(tmp168x);
+		tmp168x |= (paid | BIT(9));
+		HALMAC_REG_W16(REG_WMAC_ASSOCIATED_MU_BFMEE5, tmp168x);
+		break;
+	default:
+		return HALMAC_RET_INVALID_SOUNDING_SETTING;
+	}
+
+	PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
+
+	return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * su_bfee_entry_init_88xx() - config SU beamformer's registers
+ * @adapter : the adapter of halmac
+ * @param : parameters to configure SU BFER entry
+ * Author : chunchu
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+su_bfer_entry_init_88xx(struct halmac_adapter *adapter,
+			struct halmac_su_bfer_init_para *param)
+{
+	u16 mac_addr_h;
+	u32 mac_addr_l;
+	struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
+
+	mac_addr_l = rtk_le32_to_cpu(param->bfer_address.addr_l_h.low);
+	mac_addr_h = rtk_le16_to_cpu(param->bfer_address.addr_l_h.high);
+
+	switch (param->userid) {
+	case 0:
+		HALMAC_REG_W32(REG_ASSOCIATED_BFMER0_INFO, mac_addr_l);
+		HALMAC_REG_W16(REG_ASSOCIATED_BFMER0_INFO + 4, mac_addr_h);
+		HALMAC_REG_W16(REG_ASSOCIATED_BFMER0_INFO + 6, param->paid);
+		HALMAC_REG_W16(REG_TX_CSI_RPT_PARAM_BW20, param->csi_para);
+		break;
+	case 1:
+		HALMAC_REG_W32(REG_ASSOCIATED_BFMER1_INFO, mac_addr_l);
+		HALMAC_REG_W16(REG_ASSOCIATED_BFMER1_INFO + 4, mac_addr_h);
+		HALMAC_REG_W16(REG_ASSOCIATED_BFMER1_INFO + 6, param->paid);
+		HALMAC_REG_W16(REG_TX_CSI_RPT_PARAM_BW20 + 2, param->csi_para);
+		break;
+	default:
+		return HALMAC_RET_INVALID_SOUNDING_SETTING;
+	}
+
+	PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
+
+	return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * mu_bfee_entry_init_88xx() - config MU beamformee's registers
+ * @adapter : the adapter of halmac
+ * @param : parameters to configure MU BFEE entry
+ * Author : chunchu
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+mu_bfee_entry_init_88xx(struct halmac_adapter *adapter,
+			struct halmac_mu_bfee_init_para *param)
+{
+	u16 tmp168x = 0;
+	u16 tmp14c0;
+	struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
+
+	tmp168x |= param->paid | BIT(9);
+	HALMAC_REG_W16((0x1680 + param->userid * 2), tmp168x);
+
+	tmp14c0 = HALMAC_REG_R16(REG_MU_TX_CTL) & ~(BIT(8) | BIT(9) | BIT(10));
+	HALMAC_REG_W16(REG_MU_TX_CTL, tmp14c0 | ((param->userid - 2) << 8));
+	HALMAC_REG_W32(REG_MU_STA_GID_VLD, 0);
+	HALMAC_REG_W32(REG_MU_STA_USER_POS_INFO, param->user_position_l);
+	HALMAC_REG_W32(REG_MU_STA_USER_POS_INFO + 4, param->user_position_h);
+
+	PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
+
+	return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * mu_bfer_entry_init_88xx() - config MU beamformer's registers
+ * @adapter : the adapter of halmac
+ * @param : parameters to configure MU BFER entry
+ * Author : chunchu
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+mu_bfer_entry_init_88xx(struct halmac_adapter *adapter,
+			struct halmac_mu_bfer_init_para *param)
+{
+	u16 tmp1680 = 0;
+	u16 mac_addr_h;
+	u32 mac_addr_l;
+	struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
+
+	mac_addr_l = rtk_le32_to_cpu(param->bfer_address.addr_l_h.low);
+	mac_addr_h = rtk_le16_to_cpu(param->bfer_address.addr_l_h.high);
+
+	HALMAC_REG_W32(REG_ASSOCIATED_BFMER0_INFO, mac_addr_l);
+	HALMAC_REG_W16(REG_ASSOCIATED_BFMER0_INFO + 4, mac_addr_h);
+	HALMAC_REG_W16(REG_ASSOCIATED_BFMER0_INFO + 6, param->paid);
+	HALMAC_REG_W16(REG_TX_CSI_RPT_PARAM_BW20, param->csi_para);
+
+	tmp1680 = HALMAC_REG_R16(0x1680) & 0xC000;
+	tmp1680 |= param->my_aid | (param->csi_length_sel << 12);
+	HALMAC_REG_W16(0x1680, tmp1680);
+
+	PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
+
+	return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * su_bfee_entry_del_88xx() - reset SU beamformee's registers
+ * @adapter : the adapter of halmac
+ * @userid : the SU BFee userid to be deleted
+ * Author : chunchu
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+su_bfee_entry_del_88xx(struct halmac_adapter *adapter, u8 userid)
+{
+	u16 value16;
+	struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
+
+	switch (userid) {
+	case 0:
+		value16 = HALMAC_REG_R16(REG_TXBF_CTRL);
+		value16 &= ~(BIT_MASK_R_TXBF0_AID | BIT_R_TXBF0_20M |
+					BIT_R_TXBF0_40M | BIT_R_TXBF0_80M);
+		HALMAC_REG_W16(REG_TXBF_CTRL, value16);
+		HALMAC_REG_W16(REG_ASSOCIATED_BFMEE_SEL, 0);
+		break;
+	case 1:
+		value16 = HALMAC_REG_R16(REG_TXBF_CTRL + 2);
+		value16 &= ~(BIT_MASK_R_TXBF1_AID | BIT_R_TXBF0_20M |
+					BIT_R_TXBF0_40M | BIT_R_TXBF0_80M);
+		HALMAC_REG_W16(REG_TXBF_CTRL + 2, value16);
+		HALMAC_REG_W16(REG_ASSOCIATED_BFMEE_SEL + 2, 0);
+		break;
+	case 2:
+		HALMAC_REG_W16(REG_WMAC_ASSOCIATED_MU_BFMEE2, 0);
+		break;
+	case 3:
+		HALMAC_REG_W16(REG_WMAC_ASSOCIATED_MU_BFMEE3, 0);
+		break;
+	case 4:
+		HALMAC_REG_W16(REG_WMAC_ASSOCIATED_MU_BFMEE4, 0);
+		break;
+	case 5:
+		HALMAC_REG_W16(REG_WMAC_ASSOCIATED_MU_BFMEE5, 0);
+		break;
+	default:
+		return HALMAC_RET_INVALID_SOUNDING_SETTING;
+	}
+
+	PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
+
+	return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * su_bfee_entry_del_88xx() - reset SU beamformer's registers
+ * @adapter : the adapter of halmac
+ * @userid : the SU BFer userid to be deleted
+ * Author : chunchu
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+su_bfer_entry_del_88xx(struct halmac_adapter *adapter, u8 userid)
+{
+	struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
+
+	switch (userid) {
+	case 0:
+		HALMAC_REG_W32(REG_ASSOCIATED_BFMER0_INFO, 0);
+		HALMAC_REG_W32(REG_ASSOCIATED_BFMER0_INFO + 4, 0);
+		break;
+	case 1:
+		HALMAC_REG_W32(REG_ASSOCIATED_BFMER1_INFO, 0);
+		HALMAC_REG_W32(REG_ASSOCIATED_BFMER1_INFO + 4, 0);
+		break;
+	default:
+		return HALMAC_RET_INVALID_SOUNDING_SETTING;
+	}
+
+	PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
+
+	return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * mu_bfee_entry_del_88xx() - reset MU beamformee's registers
+ * @adapter : the adapter of halmac
+ * @userid : the MU STA userid to be deleted
+ * Author : chunchu
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+mu_bfee_entry_del_88xx(struct halmac_adapter *adapter, u8 userid)
+{
+	struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
+
+	HALMAC_REG_W16(0x1680 + userid * 2, 0);
+	HALMAC_REG_W8_CLR(REG_MU_TX_CTL, BIT(userid - 2));
+
+	PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
+
+	return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * mu_bfer_entry_del_88xx() -reset MU beamformer's registers
+ * @adapter : the adapter of halmac
+ * Author : chunchu
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+mu_bfer_entry_del_88xx(struct halmac_adapter *adapter)
+{
+	struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
+
+	HALMAC_REG_W32(REG_ASSOCIATED_BFMER0_INFO, 0);
+	HALMAC_REG_W32(REG_ASSOCIATED_BFMER0_INFO + 4, 0);
+	HALMAC_REG_W16(0x1680, 0);
+	HALMAC_REG_W8(REG_MU_TX_CTL, 0);
+
+	PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
+
+	return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * cfg_csi_rate_88xx() - config CSI frame Tx rate
+ * @adapter : the adapter of halmac
+ * @rssi : rssi in decimal value
+ * @cur_rate : current CSI frame rate
+ * @fixrate_en : enable to fix CSI frame in VHT rate, otherwise legacy OFDM rate
+ * @new_rate : API returns the final CSI frame rate
+ * Author : chunchu
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+cfg_csi_rate_88xx(struct halmac_adapter *adapter, u8 rssi, u8 cur_rate,
+		  u8 fixrate_en, u8 *new_rate)
+{
+	u32 csi_cfg;
+	u16 cur_rrsr;
+	struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
+
+	PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
+
+#if HALMAC_8821C_SUPPORT
+	if (adapter->chip_id == HALMAC_CHIP_ID_8821C && fixrate_en) {
+		csi_cfg = HALMAC_REG_R32(REG_BBPSF_CTRL) & ~BITS_WMAC_CSI_RATE;
+		HALMAC_REG_W32(REG_BBPSF_CTRL,
+			       csi_cfg | BIT_CSI_FORCE_RATE_EN |
+			       BIT_CSI_RSC(1) |
+			       BIT_WMAC_CSI_RATE(HALMAC_VHT_NSS1_MCS3));
+		*new_rate = HALMAC_VHT_NSS1_MCS3;
+		return HALMAC_RET_SUCCESS;
+	}
+	csi_cfg = HALMAC_REG_R32(REG_BBPSF_CTRL) & ~BITS_WMAC_CSI_RATE &
+							~BIT_CSI_FORCE_RATE_EN;
+#else
+	csi_cfg = HALMAC_REG_R32(REG_BBPSF_CTRL) & ~BITS_WMAC_CSI_RATE;
+#endif
+
+	cur_rrsr = HALMAC_REG_R16(REG_RRSR);
+
+	if (rssi >= 40) {
+		if (cur_rate != HALMAC_OFDM54) {
+			cur_rrsr |= BIT(HALMAC_OFDM54);
+			csi_cfg |= BIT_WMAC_CSI_RATE(HALMAC_OFDM54);
+			HALMAC_REG_W16(REG_RRSR, cur_rrsr);
+			HALMAC_REG_W32(REG_BBPSF_CTRL, csi_cfg);
+		}
+		*new_rate = HALMAC_OFDM54;
+	} else {
+		if (cur_rate != HALMAC_OFDM24) {
+			cur_rrsr &= ~(BIT(HALMAC_OFDM54));
+			csi_cfg |= BIT_WMAC_CSI_RATE(HALMAC_OFDM24);
+			HALMAC_REG_W16(REG_RRSR, cur_rrsr);
+			HALMAC_REG_W32(REG_BBPSF_CTRL, csi_cfg);
+		}
+		*new_rate = HALMAC_OFDM24;
+	}
+
+	return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * fw_snding_88xx() - fw sounding control
+ * @adapter : the adapter of halmac
+ * @su_info :
+ *	su0_en : enable/disable fw sounding
+ *	su0_ndpa_pkt : ndpa pkt, shall include txdesc
+ *	su0_pkt_sz : ndpa pkt size, shall include txdesc
+ * @mu_info : currently not in use, input NULL is acceptable
+ * @period : sounding period, unit is 5ms
+ * Author : Ivan Lin
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+fw_snding_88xx(struct halmac_adapter *adapter,
+	       struct halmac_su_snding_info *su_info,
+	       struct halmac_mu_snding_info *mu_info, u8 period)
+{
+	u8 h2c_buf[H2C_PKT_SIZE_88XX] = { 0 };
+	u16 seq_num;
+	u16 snding_info_addr;
+	struct halmac_h2c_header_info hdr_info;
+	enum halmac_cmd_process_status *proc_status;
+	enum halmac_ret_status status;
+
+	proc_status = &adapter->halmac_state.fw_snding_state.proc_status;
+
+	if (adapter->chip_id == HALMAC_CHIP_ID_8821C)
+		return HALMAC_RET_NOT_SUPPORT;
+
+	if (halmac_fw_validate(adapter) != HALMAC_RET_SUCCESS)
+		return HALMAC_RET_NO_DLFW;
+
+	if (adapter->fw_ver.h2c_version < 9)
+		return HALMAC_RET_FW_NO_SUPPORT;
+
+	if (*proc_status == HALMAC_CMD_PROCESS_SENDING) {
+		PLTFM_MSG_TRACE("[TRACE]Wait event(snd)\n");
+		return HALMAC_RET_BUSY_STATE;
+	}
+
+	if (su_info->su0_en == 1) {
+		if (!su_info->su0_ndpa_pkt)
+			return HALMAC_RET_NULL_POINTER;
+
+		if (su_info->su0_pkt_sz > (u32)SU0_SNDING_PKT_RSVDPG_SIZE -
+		    adapter->hw_cfg_info.txdesc_size)
+			return HALMAC_RET_DATA_SIZE_INCORRECT;
+
+		if (!snding_pkt_chk_88xx(adapter, su_info->su0_ndpa_pkt))
+			return HALMAC_RET_TXDESC_SET_FAIL;
+
+		if (fw_snding_cmd_cnstr_state_88xx(adapter) !=
+		    HALMAC_CMD_CNSTR_IDLE) {
+			PLTFM_MSG_ERR("[ERR]Not idle(snd)\n");
+			return HALMAC_RET_ERROR_STATE;
+		}
+
+		snding_info_addr = adapter->txff_alloc.rsvd_h2c_sta_info_addr +
+				   SU0_SNDING_PKT_OFFSET;
+		status = dl_rsvd_page_88xx(adapter, snding_info_addr,
+					   su_info->su0_ndpa_pkt,
+					   su_info->su0_pkt_sz);
+		if (status != HALMAC_RET_SUCCESS) {
+			PLTFM_MSG_ERR("[ERR]dl rsvd page\n");
+			return status;
+		}
+
+		FW_SNDING_SET_SU0(h2c_buf, 1);
+		FW_SNDING_SET_PERIOD(h2c_buf, period);
+		FW_SNDING_SET_NDPA0_HEAD_PG(h2c_buf, snding_info_addr -
+					    adapter->txff_alloc.rsvd_boundary);
+	} else {
+		if (fw_snding_cmd_cnstr_state_88xx(adapter) !=
+		    HALMAC_CMD_CNSTR_BUSY) {
+			PLTFM_MSG_ERR("[ERR]Not snd(snd)\n");
+			return HALMAC_RET_ERROR_STATE;
+		}
+		FW_SNDING_SET_SU0(h2c_buf, 0);
+	}
+
+	*proc_status = HALMAC_CMD_PROCESS_SENDING;
+
+	hdr_info.sub_cmd_id = SUB_CMD_ID_FW_SNDING;
+	hdr_info.content_size = 8;
+	hdr_info.ack = 1;
+	set_h2c_pkt_hdr_88xx(adapter, h2c_buf, &hdr_info, &seq_num);
+	adapter->halmac_state.fw_snding_state.seq_num = seq_num;
+
+	status = send_h2c_pkt_88xx(adapter, h2c_buf);
+	if (status != HALMAC_RET_SUCCESS) {
+		PLTFM_MSG_ERR("[ERR]send h2c\n");
+		reset_ofld_feature_88xx(adapter, HALMAC_FEATURE_FW_SNDING);
+		return status;
+	}
+
+	if (cnv_fw_snding_state_88xx(adapter, su_info->su0_en == 1 ?
+				     HALMAC_CMD_CNSTR_BUSY :
+				     HALMAC_CMD_CNSTR_IDLE)
+				     != HALMAC_RET_SUCCESS)
+		return HALMAC_RET_ERROR_STATE;
+
+	return HALMAC_RET_SUCCESS;
+}
+
+static u8
+snding_pkt_chk_88xx(struct halmac_adapter *adapter, u8 *pkt)
+{
+	u8 data_rate;
+
+	if (GET_TX_DESC_NDPA(pkt) == 0) {
+		PLTFM_MSG_ERR("[ERR]txdesc ndpa = 0\n");
+		return 0;
+	}
+
+	data_rate = (u8)GET_TX_DESC_DATARATE(pkt);
+	if (!(data_rate >= HALMAC_VHT_NSS2_MCS0 &&
+	      data_rate <= HALMAC_VHT_NSS2_MCS9)) {
+		if (!(data_rate >= HALMAC_MCS8 && data_rate <= HALMAC_MCS15)) {
+			PLTFM_MSG_ERR("[ERR]txdesc rate\n");
+			return 0;
+		}
+	}
+
+	if (GET_TX_DESC_NAVUSEHDR(pkt) == 0) {
+		PLTFM_MSG_ERR("[ERR]txdesc navusehdr = 0\n");
+		return 0;
+	}
+
+	if (GET_TX_DESC_USE_RATE(pkt) == 0) {
+		PLTFM_MSG_ERR("[ERR]txdesc userate = 0\n");
+		return 0;
+	}
+
+	return 1;
+}
+
+static enum halmac_cmd_construct_state
+fw_snding_cmd_cnstr_state_88xx(struct halmac_adapter *adapter)
+{
+	return adapter->halmac_state.fw_snding_state.cmd_cnstr_state;
+}
+
+enum halmac_ret_status
+get_h2c_ack_fw_snding_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size)
+{
+	u8 seq_num = 0;
+	u8 fw_rc;
+	struct halmac_fw_snding_state *state;
+	enum halmac_cmd_process_status proc_status;
+
+	state = &adapter->halmac_state.fw_snding_state;
+
+	seq_num = (u8)H2C_ACK_HDR_GET_H2C_SEQ(buf);
+	PLTFM_MSG_TRACE("[TRACE]Seq num:h2c->%d c2h->%d\n",
+			state->seq_num, seq_num);
+	if (seq_num != state->seq_num) {
+		PLTFM_MSG_ERR("[ERR]Seq num mismatch:h2c->%d c2h->%d\n",
+			      state->seq_num, seq_num);
+		return HALMAC_RET_SUCCESS;
+	}
+
+	if (state->proc_status != HALMAC_CMD_PROCESS_SENDING) {
+		PLTFM_MSG_ERR("[ERR]not sending(snd)\n");
+		return HALMAC_RET_SUCCESS;
+	}
+
+	fw_rc = (u8)H2C_ACK_HDR_GET_H2C_RETURN_CODE(buf);
+	state->fw_rc = fw_rc;
+
+	if ((enum halmac_h2c_return_code)fw_rc == HALMAC_H2C_RETURN_SUCCESS) {
+		proc_status = HALMAC_CMD_PROCESS_DONE;
+		state->proc_status = proc_status;
+		PLTFM_EVENT_SIG(HALMAC_FEATURE_FW_SNDING, proc_status,
+				NULL, 0);
+	} else {
+		proc_status = HALMAC_CMD_PROCESS_ERROR;
+		state->proc_status = proc_status;
+		PLTFM_EVENT_SIG(HALMAC_FEATURE_FW_SNDING, proc_status,
+				&fw_rc, 1);
+	}
+
+	return HALMAC_RET_SUCCESS;
+}
+
+enum halmac_ret_status
+get_fw_snding_status_88xx(struct halmac_adapter *adapter,
+			  enum halmac_cmd_process_status *proc_status)
+{
+	*proc_status = adapter->halmac_state.fw_snding_state.proc_status;
+
+	return HALMAC_RET_SUCCESS;
+}
+
+static enum halmac_ret_status
+cnv_fw_snding_state_88xx(struct halmac_adapter *adapter,
+			 enum halmac_cmd_construct_state dest_state)
+{
+	struct halmac_fw_snding_state *state;
+
+	state = &adapter->halmac_state.fw_snding_state;
+
+	if (state->cmd_cnstr_state != HALMAC_CMD_CNSTR_IDLE &&
+	    state->cmd_cnstr_state != HALMAC_CMD_CNSTR_BUSY)
+		return HALMAC_RET_ERROR_STATE;
+
+	if (dest_state == HALMAC_CMD_CNSTR_IDLE) {
+		if (state->cmd_cnstr_state == HALMAC_CMD_CNSTR_IDLE)
+			return HALMAC_RET_ERROR_STATE;
+	} else if (dest_state == HALMAC_CMD_CNSTR_BUSY) {
+		if (state->cmd_cnstr_state == HALMAC_CMD_CNSTR_BUSY)
+			return HALMAC_RET_ERROR_STATE;
+	}
+
+	state->cmd_cnstr_state = dest_state;
+
+	return HALMAC_RET_SUCCESS;
+}
+#endif /* HALMAC_88XX_SUPPORT */
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/halmac/halmac_88xx/halmac_mimo_88xx.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/halmac/halmac_88xx/halmac_mimo_88xx.h
--- linux-5.6.3/3rdparty/rtl8821ce/hal/halmac/halmac_88xx/halmac_mimo_88xx.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/halmac/halmac_88xx/halmac_mimo_88xx.h	2020-04-10 16:35:06.793658994 +0300
@@ -0,0 +1,83 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ ******************************************************************************/
+
+#ifndef _HALMAC_MIMO_88XX_H_
+#define _HALMAC_MIMO_88XX_H_
+
+#include "../halmac_api.h"
+
+#if HALMAC_88XX_SUPPORT
+
+enum halmac_ret_status
+cfg_txbf_88xx(struct halmac_adapter *adapter, u8 userid, enum halmac_bw bw,
+	      u8 txbf_en);
+
+enum halmac_ret_status
+cfg_mumimo_88xx(struct halmac_adapter *adapter,
+		struct halmac_cfg_mumimo_para *param);
+
+enum halmac_ret_status
+cfg_sounding_88xx(struct halmac_adapter *adapter, enum halmac_snd_role role,
+		  enum halmac_data_rate rate);
+
+enum halmac_ret_status
+del_sounding_88xx(struct halmac_adapter *adapter, enum halmac_snd_role role);
+
+enum halmac_ret_status
+su_bfee_entry_init_88xx(struct halmac_adapter *adapter, u8 userid, u16 paid);
+
+enum halmac_ret_status
+su_bfer_entry_init_88xx(struct halmac_adapter *adapter,
+			struct halmac_su_bfer_init_para *param);
+
+enum halmac_ret_status
+mu_bfee_entry_init_88xx(struct halmac_adapter *adapter,
+			struct halmac_mu_bfee_init_para *param);
+
+enum halmac_ret_status
+mu_bfer_entry_init_88xx(struct halmac_adapter *adapter,
+			struct halmac_mu_bfer_init_para *param);
+
+enum halmac_ret_status
+su_bfee_entry_del_88xx(struct halmac_adapter *adapter, u8 userid);
+
+enum halmac_ret_status
+su_bfer_entry_del_88xx(struct halmac_adapter *adapter, u8 userid);
+
+enum halmac_ret_status
+mu_bfee_entry_del_88xx(struct halmac_adapter *adapter, u8 userid);
+
+enum halmac_ret_status
+mu_bfer_entry_del_88xx(struct halmac_adapter *adapter);
+
+enum halmac_ret_status
+cfg_csi_rate_88xx(struct halmac_adapter *adapter, u8 rssi, u8 cur_rate,
+		  u8 fixrate_en, u8 *new_rate);
+
+enum halmac_ret_status
+fw_snding_88xx(struct halmac_adapter *adapter,
+	       struct halmac_su_snding_info *su_info,
+	       struct halmac_mu_snding_info *mu_info, u8 period);
+
+enum halmac_ret_status
+get_h2c_ack_fw_snding_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size);
+
+enum halmac_ret_status
+get_fw_snding_status_88xx(struct halmac_adapter *adapter,
+			  enum halmac_cmd_process_status *proc_status);
+
+#endif /* HALMAC_88XX_SUPPORT */
+
+#endif/* _HALMAC_MIMO_88XX_H_ */
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/halmac/halmac_88xx/halmac_pcie_88xx.c linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/halmac/halmac_88xx/halmac_pcie_88xx.c
--- linux-5.6.3/3rdparty/rtl8821ce/hal/halmac/halmac_88xx/halmac_pcie_88xx.c	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/halmac/halmac_88xx/halmac_pcie_88xx.c	2020-04-10 16:35:06.794659041 +0300
@@ -0,0 +1,537 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ ******************************************************************************/
+
+#include "halmac_pcie_88xx.h"
+
+#if (HALMAC_88XX_SUPPORT && HALMAC_PCIE_SUPPORT)
+
+/**
+ * init_pcie_cfg_88xx() -  init PCIe
+ * @adapter : the adapter of halmac
+ * Author : KaiYuan Chang
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+init_pcie_cfg_88xx(struct halmac_adapter *adapter)
+{
+	return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * deinit_pcie_cfg_88xx() - deinit PCIE
+ * @adapter : the adapter of halmac
+ * Author : KaiYuan Chang
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+deinit_pcie_cfg_88xx(struct halmac_adapter *adapter)
+{
+	return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * cfg_pcie_rx_agg_88xx() - config rx aggregation
+ * @adapter : the adapter of halmac
+ * @halmac_rx_agg_mode
+ * Author : KaiYuan Chang/Ivan Lin
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+cfg_pcie_rx_agg_88xx(struct halmac_adapter *adapter,
+		     struct halmac_rxagg_cfg *cfg)
+{
+	return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * reg_r8_pcie_88xx() - read 1byte register
+ * @adapter : the adapter of halmac
+ * @offset : register offset
+ * Author : KaiYuan Chang/Ivan Lin
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+u8
+reg_r8_pcie_88xx(struct halmac_adapter *adapter, u32 offset)
+{
+	return PLTFM_REG_R8(offset);
+}
+
+/**
+ * reg_w8_pcie_88xx() - write 1byte register
+ * @adapter : the adapter of halmac
+ * @offset : register offset
+ * @value : register value
+ * Author : KaiYuan Chang/Ivan Lin
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+reg_w8_pcie_88xx(struct halmac_adapter *adapter, u32 offset, u8 value)
+{
+	PLTFM_REG_W8(offset, value);
+
+	return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * reg_r16_pcie_88xx() - read 2byte register
+ * @adapter : the adapter of halmac
+ * @offset : register offset
+ * Author : KaiYuan Chang/Ivan Lin
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+u16
+reg_r16_pcie_88xx(struct halmac_adapter *adapter, u32 offset)
+{
+	return PLTFM_REG_R16(offset);
+}
+
+/**
+ * reg_w16_pcie_88xx() - write 2byte register
+ * @adapter : the adapter of halmac
+ * @offset : register offset
+ * @value : register value
+ * Author : KaiYuan Chang/Ivan Lin
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+reg_w16_pcie_88xx(struct halmac_adapter *adapter, u32 offset, u16 value)
+{
+	PLTFM_REG_W16(offset, value);
+
+	return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * reg_r32_pcie_88xx() - read 4byte register
+ * @adapter : the adapter of halmac
+ * @offset : register offset
+ * Author : KaiYuan Chang/Ivan Lin
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+u32
+reg_r32_pcie_88xx(struct halmac_adapter *adapter, u32 offset)
+{
+	return PLTFM_REG_R32(offset);
+}
+
+/**
+ * reg_w32_pcie_88xx() - write 4byte register
+ * @adapter : the adapter of halmac
+ * @offset : register offset
+ * @value : register value
+ * Author : KaiYuan Chang/Ivan Lin
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+reg_w32_pcie_88xx(struct halmac_adapter *adapter, u32 offset, u32 value)
+{
+	PLTFM_REG_W32(offset, value);
+
+	return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * cfg_txagg_pcie_align_88xx() -config sdio bus tx agg alignment
+ * @adapter : the adapter of halmac
+ * @enable : function enable(1)/disable(0)
+ * @align_size : sdio bus tx agg alignment size (2^n, n = 3~11)
+ * Author : Soar Tu
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+cfg_txagg_pcie_align_88xx(struct halmac_adapter *adapter, u8 enable,
+			  u16 align_size)
+{
+	return HALMAC_RET_NOT_SUPPORT;
+}
+
+/**
+ * tx_allowed_pcie_88xx() - check tx status
+ * @adapter : the adapter of halmac
+ * @buf : tx packet, include txdesc
+ * @size : tx packet size, include txdesc
+ * Author : Ivan Lin
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+tx_allowed_pcie_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size)
+{
+	return HALMAC_RET_NOT_SUPPORT;
+}
+
+/**
+ * pcie_indirect_reg_r32_88xx() - read MAC reg by SDIO reg
+ * @adapter : the adapter of halmac
+ * @offset : register offset
+ * Author : Soar
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+u32
+pcie_indirect_reg_r32_88xx(struct halmac_adapter *adapter, u32 offset)
+{
+	return 0xFFFFFFFF;
+}
+
+/**
+ * pcie_reg_rn_88xx() - read n byte register
+ * @adapter : the adapter of halmac
+ * @offset : register offset
+ * @size : register value size
+ * @value : register value
+ * Author : Soar
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+pcie_reg_rn_88xx(struct halmac_adapter *adapter, u32 offset, u32 size,
+		 u8 *value)
+{
+	return HALMAC_RET_NOT_SUPPORT;
+}
+
+/**
+ * set_pcie_bulkout_num_88xx() - inform bulk-out num
+ * @adapter : the adapter of halmac
+ * @num : usb bulk-out number
+ * Author : KaiYuan Chang
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+set_pcie_bulkout_num_88xx(struct halmac_adapter *adapter, u8 num)
+{
+	return HALMAC_RET_NOT_SUPPORT;
+}
+
+/**
+ * get_pcie_tx_addr_88xx() - get CMD53 addr for the TX packet
+ * @adapter : the adapter of halmac
+ * @buf : tx packet, include txdesc
+ * @size : tx packet size
+ * @cmd53_addr : cmd53 addr value
+ * Author : KaiYuan Chang/Ivan Lin
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+get_pcie_tx_addr_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size,
+		      u32 *cmd53_addr)
+{
+	return HALMAC_RET_NOT_SUPPORT;
+}
+
+/**
+ * get_pcie_bulkout_id_88xx() - get bulk out id for the TX packet
+ * @adapter : the adapter of halmac
+ * @buf : tx packet, include txdesc
+ * @size : tx packet size
+ * @id : usb bulk-out id
+ * Author : KaiYuan Chang
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+get_pcie_bulkout_id_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size,
+			 u8 *id)
+{
+	return HALMAC_RET_NOT_SUPPORT;
+}
+
+enum halmac_ret_status
+mdio_write_88xx(struct halmac_adapter *adapter, u8 addr, u16 data, u8 speed)
+{
+	u8 tmp_u1b = 0;
+	u32 cnt = 0;
+	struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
+	u8 real_addr = 0;
+
+	HALMAC_REG_W16(REG_MDIO_V1, data);
+
+	real_addr = (addr & 0x1F);
+	HALMAC_REG_W8(REG_PCIE_MIX_CFG, real_addr);
+
+	if (speed == HAL_INTF_PHY_PCIE_GEN1) {
+		if (addr < 0x20)
+			HALMAC_REG_W8(REG_PCIE_MIX_CFG + 3, 0x00);
+		else
+			HALMAC_REG_W8(REG_PCIE_MIX_CFG + 3, 0x01);
+	} else if (speed == HAL_INTF_PHY_PCIE_GEN2) {
+		if (addr < 0x20)
+			HALMAC_REG_W8(REG_PCIE_MIX_CFG + 3, 0x02);
+		else
+			HALMAC_REG_W8(REG_PCIE_MIX_CFG + 3, 0x03);
+	} else {
+		PLTFM_MSG_ERR("[ERR]Error Speed !\n");
+	}
+
+	HALMAC_REG_W8_SET(REG_PCIE_MIX_CFG, BIT_MDIO_WFLAG_V1);
+
+	tmp_u1b = HALMAC_REG_R8(REG_PCIE_MIX_CFG) & BIT_MDIO_WFLAG_V1;
+	cnt = 20;
+
+	while (tmp_u1b && (cnt != 0)) {
+		PLTFM_DELAY_US(10);
+		tmp_u1b = HALMAC_REG_R8(REG_PCIE_MIX_CFG) & BIT_MDIO_WFLAG_V1;
+		cnt--;
+	}
+
+	if (tmp_u1b) {
+		PLTFM_MSG_ERR("[ERR]MDIO write fail!\n");
+		return HALMAC_RET_FAIL;
+	}
+
+	return HALMAC_RET_SUCCESS;
+}
+
+u16
+mdio_read_88xx(struct halmac_adapter *adapter, u8 addr, u8 speed)
+{
+	u16 ret = 0;
+	u8 tmp_u1b = 0;
+	u32 cnt = 0;
+	struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
+	u8 real_addr = 0;
+
+	real_addr = (addr & 0x1F);
+	HALMAC_REG_W8(REG_PCIE_MIX_CFG, real_addr);
+
+	if (speed == HAL_INTF_PHY_PCIE_GEN1) {
+		if (addr < 0x20)
+			HALMAC_REG_W8(REG_PCIE_MIX_CFG + 3, 0x00);
+		else
+			HALMAC_REG_W8(REG_PCIE_MIX_CFG + 3, 0x01);
+	} else if (speed == HAL_INTF_PHY_PCIE_GEN2) {
+		if (addr < 0x20)
+			HALMAC_REG_W8(REG_PCIE_MIX_CFG + 3, 0x02);
+		else
+			HALMAC_REG_W8(REG_PCIE_MIX_CFG + 3, 0x03);
+	} else {
+		PLTFM_MSG_ERR("[ERR]Error Speed !\n");
+	}
+
+	HALMAC_REG_W8_SET(REG_PCIE_MIX_CFG, BIT_MDIO_RFLAG_V1);
+
+	tmp_u1b = HALMAC_REG_R8(REG_PCIE_MIX_CFG) & BIT_MDIO_RFLAG_V1;
+	cnt = 20;
+	while (tmp_u1b && (cnt != 0)) {
+		PLTFM_DELAY_US(10);
+		tmp_u1b = HALMAC_REG_R8(REG_PCIE_MIX_CFG) & BIT_MDIO_RFLAG_V1;
+		cnt--;
+	}
+
+	if (tmp_u1b) {
+		ret  = 0xFFFF;
+		PLTFM_MSG_ERR("[ERR]MDIO read fail!\n");
+	} else {
+		ret = HALMAC_REG_R16(REG_MDIO_V1 + 2);
+		PLTFM_MSG_TRACE("[TRACE]Value-R = %x\n", ret);
+	}
+
+	return ret;
+}
+
+enum halmac_ret_status
+dbi_w32_88xx(struct halmac_adapter *adapter, u16 addr, u32 data)
+{
+	u8 tmp_u1b = 0;
+	u32 cnt = 0;
+	u16 write_addr = 0;
+	struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
+
+	HALMAC_REG_W32(REG_DBI_WDATA_V1, data);
+
+	write_addr = ((addr & 0x0ffc) | (0x000F << 12));
+	HALMAC_REG_W16(REG_DBI_FLAG_V1, write_addr);
+
+	PLTFM_MSG_TRACE("[TRACE]Addr-W = %x\n", write_addr);
+
+	HALMAC_REG_W8(REG_DBI_FLAG_V1 + 2, 0x01);
+	tmp_u1b = HALMAC_REG_R8(REG_DBI_FLAG_V1 + 2);
+
+	cnt = 20;
+	while (tmp_u1b && (cnt != 0)) {
+		PLTFM_DELAY_US(10);
+		tmp_u1b = HALMAC_REG_R8(REG_DBI_FLAG_V1 + 2);
+		cnt--;
+	}
+
+	if (tmp_u1b) {
+		PLTFM_MSG_ERR("[ERR]DBI write fail!\n");
+		return HALMAC_RET_FAIL;
+	}
+
+	return HALMAC_RET_SUCCESS;
+}
+
+u32
+dbi_r32_88xx(struct halmac_adapter *adapter, u16 addr)
+{
+	u16 read_addr = addr & 0x0ffc;
+	u8 tmp_u1b = 0;
+	u32 cnt = 0;
+	u32 ret = 0;
+	struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
+
+	HALMAC_REG_W16(REG_DBI_FLAG_V1, read_addr);
+
+	HALMAC_REG_W8(REG_DBI_FLAG_V1 + 2, 0x2);
+	tmp_u1b = HALMAC_REG_R8(REG_DBI_FLAG_V1 + 2);
+
+	cnt = 20;
+	while (tmp_u1b && (cnt != 0)) {
+		PLTFM_DELAY_US(10);
+		tmp_u1b = HALMAC_REG_R8(REG_DBI_FLAG_V1 + 2);
+		cnt--;
+	}
+
+	if (tmp_u1b) {
+		ret  = 0xFFFF;
+		PLTFM_MSG_ERR("[ERR]DBI read fail!\n");
+	} else {
+		ret = HALMAC_REG_R32(REG_DBI_RDATA_V1);
+		PLTFM_MSG_TRACE("[TRACE]Value-R = %x\n", ret);
+	}
+
+	return ret;
+}
+
+enum halmac_ret_status
+dbi_w8_88xx(struct halmac_adapter *adapter, u16 addr, u8 data)
+{
+	u8 tmp_u1b = 0;
+	u32 cnt = 0;
+	u16 write_addr = 0;
+	u16 remainder = addr & (4 - 1);
+	struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
+
+	HALMAC_REG_W8(REG_DBI_WDATA_V1 + remainder, data);
+
+	write_addr = ((addr & 0x0ffc) | (BIT(0) << (remainder + 12)));
+
+	HALMAC_REG_W16(REG_DBI_FLAG_V1, write_addr);
+
+	PLTFM_MSG_TRACE("[TRACE]Addr-W = %x\n", write_addr);
+
+	HALMAC_REG_W8(REG_DBI_FLAG_V1 + 2, 0x01);
+
+	tmp_u1b = HALMAC_REG_R8(REG_DBI_FLAG_V1 + 2);
+
+	cnt = 20;
+	while (tmp_u1b && (cnt != 0)) {
+		PLTFM_DELAY_US(10);
+		tmp_u1b = HALMAC_REG_R8(REG_DBI_FLAG_V1 + 2);
+		cnt--;
+	}
+
+	if (tmp_u1b) {
+		PLTFM_MSG_ERR("[ERR]DBI write fail!\n");
+		return HALMAC_RET_FAIL;
+	}
+
+	return HALMAC_RET_SUCCESS;
+}
+
+u8
+dbi_r8_88xx(struct halmac_adapter *adapter, u16 addr)
+{
+	u16 read_addr = addr & 0x0ffc;
+	u8 tmp_u1b = 0;
+	u32 cnt = 0;
+	u8 ret = 0;
+	struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
+
+	HALMAC_REG_W16(REG_DBI_FLAG_V1, read_addr);
+	HALMAC_REG_W8(REG_DBI_FLAG_V1 + 2, 0x2);
+
+	tmp_u1b = HALMAC_REG_R8(REG_DBI_FLAG_V1 + 2);
+
+	cnt = 20;
+	while (tmp_u1b && (cnt != 0)) {
+		PLTFM_DELAY_US(10);
+		tmp_u1b = HALMAC_REG_R8(REG_DBI_FLAG_V1 + 2);
+		cnt--;
+	}
+
+	if (tmp_u1b) {
+		ret  = 0xFF;
+		PLTFM_MSG_ERR("[ERR]DBI read fail!\n");
+	} else {
+		ret = HALMAC_REG_R8(REG_DBI_RDATA_V1 + (addr & (4 - 1)));
+		PLTFM_MSG_TRACE("[TRACE]Value-R = %x\n", ret);
+	}
+
+	return ret;
+}
+
+enum halmac_ret_status
+trxdma_check_idle_88xx(struct halmac_adapter *adapter)
+{
+	u32 cnt = 0;
+	struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
+
+	/* Stop Tx & Rx DMA */
+	HALMAC_REG_W32_SET(REG_RXPKT_NUM, BIT(18));
+	HALMAC_REG_W16_SET(REG_PCIE_CTRL, ~(BIT(15) | BIT(8)));
+
+	/* Stop FW */
+	HALMAC_REG_W16_CLR(REG_SYS_FUNC_EN, BIT(10));
+
+	/* Check Tx DMA is idle */
+	cnt = 20;
+	while ((HALMAC_REG_R8(REG_SYS_CFG5) & BIT(2)) == BIT(2)) {
+		PLTFM_DELAY_US(10);
+		cnt--;
+		if (cnt == 0) {
+			PLTFM_MSG_ERR("[ERR]Chk tx idle\n");
+			return HALMAC_RET_POWER_OFF_FAIL;
+		}
+	}
+
+	/* Check Rx DMA is idle */
+	cnt = 20;
+	while ((HALMAC_REG_R32(REG_RXPKT_NUM) & BIT(17)) != BIT(17)) {
+		PLTFM_DELAY_US(10);
+		cnt--;
+		if (cnt == 0) {
+			PLTFM_MSG_ERR("[ERR]Chk rx idle\n");
+			return HALMAC_RET_POWER_OFF_FAIL;
+		}
+	}
+
+	return HALMAC_RET_SUCCESS;
+}
+
+void
+en_ref_autok_88xx(struct halmac_adapter *adapter, u8 en)
+{
+	if (en == 1)
+		adapter->pcie_refautok_en = 1;
+	else
+		adapter->pcie_refautok_en = 0;
+}
+
+#endif /* HALMAC_88XX_SUPPORT */
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/halmac/halmac_88xx/halmac_pcie_88xx.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/halmac/halmac_88xx/halmac_pcie_88xx.h
--- linux-5.6.3/3rdparty/rtl8821ce/hal/halmac/halmac_88xx/halmac_pcie_88xx.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/halmac/halmac_88xx/halmac_pcie_88xx.h	2020-04-10 16:35:06.794659041 +0300
@@ -0,0 +1,102 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ ******************************************************************************/
+
+#ifndef _HALMAC_PCIE_88XX_H_
+#define _HALMAC_PCIE_88XX_H_
+
+#include "../halmac_api.h"
+
+#if (HALMAC_88XX_SUPPORT && HALMAC_PCIE_SUPPORT)
+
+enum halmac_ret_status
+init_pcie_cfg_88xx(struct halmac_adapter *adapter);
+
+enum halmac_ret_status
+deinit_pcie_cfg_88xx(struct halmac_adapter *adapter);
+
+enum halmac_ret_status
+cfg_pcie_rx_agg_88xx(struct halmac_adapter *adapter,
+		     struct halmac_rxagg_cfg *cfg);
+
+u8
+reg_r8_pcie_88xx(struct halmac_adapter *adapter, u32 offset);
+
+enum halmac_ret_status
+reg_w8_pcie_88xx(struct halmac_adapter *adapter, u32 offset, u8 value);
+
+u16
+reg_r16_pcie_88xx(struct halmac_adapter *adapter, u32 offset);
+
+enum halmac_ret_status
+reg_w16_pcie_88xx(struct halmac_adapter *adapter, u32 offset, u16 value);
+
+u32
+reg_r32_pcie_88xx(struct halmac_adapter *adapter, u32 offset);
+
+enum halmac_ret_status
+reg_w32_pcie_88xx(struct halmac_adapter *adapter, u32 offset, u32 value);
+
+enum halmac_ret_status
+cfg_txagg_pcie_align_88xx(struct halmac_adapter *adapter, u8 enable,
+			  u16 align_size);
+
+enum halmac_ret_status
+tx_allowed_pcie_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size);
+
+u32
+pcie_indirect_reg_r32_88xx(struct halmac_adapter *adapter, u32 offset);
+
+enum halmac_ret_status
+pcie_reg_rn_88xx(struct halmac_adapter *adapter, u32 offset, u32 size,
+		 u8 *value);
+
+enum halmac_ret_status
+set_pcie_bulkout_num_88xx(struct halmac_adapter *adapter, u8 num);
+
+enum halmac_ret_status
+get_pcie_tx_addr_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size,
+		      u32 *cmd53_addr);
+
+enum halmac_ret_status
+get_pcie_bulkout_id_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size,
+			 u8 *id);
+
+enum halmac_ret_status
+mdio_write_88xx(struct halmac_adapter *adapter, u8 addr, u16 data, u8 speed);
+
+u16
+mdio_read_88xx(struct halmac_adapter *adapter, u8 addr, u8 speed);
+
+enum halmac_ret_status
+dbi_w32_88xx(struct halmac_adapter *adapter, u16 addr, u32 data);
+
+u32
+dbi_r32_88xx(struct halmac_adapter *adapter, u16 addr);
+
+enum halmac_ret_status
+dbi_w8_88xx(struct halmac_adapter *adapter, u16 addr, u8 data);
+
+u8
+dbi_r8_88xx(struct halmac_adapter *adapter, u16 addr);
+
+enum halmac_ret_status
+trxdma_check_idle_88xx(struct halmac_adapter *adapter);
+
+void
+en_ref_autok_88xx(struct halmac_adapter *dapter, u8 en);
+
+#endif /* HALMAC_88XX_SUPPORT */
+
+#endif/* _HALMAC_PCIE_88XX_H_ */
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/halmac/halmac_api.c linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/halmac/halmac_api.c
--- linux-5.6.3/3rdparty/rtl8821ce/hal/halmac/halmac_api.c	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/halmac/halmac_api.c	2020-04-10 16:35:06.794659041 +0300
@@ -0,0 +1,622 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ ******************************************************************************/
+
+#include "halmac_type.h"
+#include "halmac_api.h"
+
+#if (HALMAC_PLATFORM_WINDOWS)
+
+#if HALMAC_8822B_SUPPORT
+#include "halmac_88xx/halmac_init_win8822b.h"
+#endif
+
+#if HALMAC_8821C_SUPPORT
+#include "halmac_88xx/halmac_init_win8821c.h"
+#endif
+
+#if HALMAC_8814B_SUPPORT
+#include "halmac_88xx_v1/halmac_init_win8814b_v1.h"
+#endif
+
+#if HALMAC_8822C_SUPPORT
+#include "halmac_88xx/halmac_init_win8822c.h"
+#endif
+
+#else
+
+#if HALMAC_88XX_SUPPORT
+#include "halmac_88xx/halmac_init_88xx.h"
+#endif
+#if HALMAC_88XX_V1_SUPPORT
+#include "halmac_88xx_v1/halmac_init_88xx_v1.h"
+#if defined(HALMAC_DATA_CPU_EN)
+#include "halmac_88xxd_v1/halmac_init_88xxd_v1.h"
+#endif
+#endif
+
+#endif
+
+enum chip_id_hw_def {
+	CHIP_ID_HW_DEF_8723A = 0x01,
+	CHIP_ID_HW_DEF_8188E = 0x02,
+	CHIP_ID_HW_DEF_8881A = 0x03,
+	CHIP_ID_HW_DEF_8812A = 0x04,
+	CHIP_ID_HW_DEF_8821A = 0x05,
+	CHIP_ID_HW_DEF_8723B = 0x06,
+	CHIP_ID_HW_DEF_8192E = 0x07,
+	CHIP_ID_HW_DEF_8814A = 0x08,
+	CHIP_ID_HW_DEF_8821C = 0x09,
+	CHIP_ID_HW_DEF_8822B = 0x0A,
+	CHIP_ID_HW_DEF_8703B = 0x0B,
+	CHIP_ID_HW_DEF_8188F = 0x0C,
+	CHIP_ID_HW_DEF_8192F = 0x0D,
+	CHIP_ID_HW_DEF_8197F = 0x0E,
+	CHIP_ID_HW_DEF_8723D = 0x0F,
+	CHIP_ID_HW_DEF_8814B = 0x11,
+	CHIP_ID_HW_DEF_8822C = 0x13,
+	CHIP_ID_HW_DEF_8812F = 0x14,
+	CHIP_ID_HW_DEF_UNDEFINE = 0x7F,
+	CHIP_ID_HW_DEF_PS = 0xEA,
+};
+
+static enum halmac_ret_status
+chk_pltfm_api(void *drv_adapter, enum halmac_interface intf,
+	      struct halmac_platform_api *pltfm_api);
+
+static enum halmac_ret_status
+get_chip_info(void *drv_adapter, struct halmac_platform_api *pltfm_api,
+	      enum halmac_interface intf, struct halmac_adapter *adapter);
+
+static u8
+pltfm_reg_r8_sdio(void *drv_adapter, struct halmac_platform_api *pltfm_api,
+		  u32 offset);
+
+static enum halmac_ret_status
+pltfm_reg_w8_sdio(void *drv_adapter, struct halmac_platform_api *pltfm_api,
+		  u32 offset, u8 data);
+
+static u8
+pltfm_reg_r_indir_sdio(void *drv_adapter, struct halmac_platform_api *pltfm_api,
+		       u32 offset);
+
+static enum halmac_ret_status
+cnv_to_sdio_bus_offset(u32 *offset);
+
+/**
+ * halmac_init_adapter() - init halmac_adapter
+ * @drv_adapter : the adapter of caller
+ * @pltfm_api : the platform APIs which is used in halmac
+ * @intf : bus interface
+ * @halmac_adapter : the adapter of halmac
+ * @halmac_api : the function pointer of APIs
+ * Author : KaiYuan Chang / Ivan Lin
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+halmac_init_adapter(void *drv_adapter, struct halmac_platform_api *pltfm_api,
+		    enum halmac_interface intf,
+		    struct halmac_adapter **halmac_adapter,
+		    struct halmac_api **halmac_api)
+{
+	struct halmac_adapter *adapter = NULL;
+	enum halmac_ret_status status = HALMAC_RET_SUCCESS;
+	u8 *buf = NULL;
+
+	union {
+		u32 i;
+		u8 x[4];
+	} ENDIAN_CHECK = { 0x01000000 };
+
+	status = chk_pltfm_api(drv_adapter, intf, pltfm_api);
+	if (status != HALMAC_RET_SUCCESS)
+		return status;
+
+	pltfm_api->MSG_PRINT(drv_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ALWAYS,
+			     HALMAC_SVN_VER "\n"
+			     "HALMAC_MAJOR_VER = %x\n"
+			     "HALMAC_PROTOTYPE_VER = %x\n"
+			     "HALMAC_MINOR_VER = %x\n"
+			     "HALMAC_PATCH_VER = %x\n",
+			     HALMAC_MAJOR_VER, HALMAC_PROTOTYPE_VER,
+			     HALMAC_MINOR_VER, HALMAC_PATCH_VER);
+
+	if (ENDIAN_CHECK.x[0] == HALMAC_SYSTEM_ENDIAN) {
+		pltfm_api->MSG_PRINT(drv_adapter, HALMAC_MSG_INIT,
+				     HALMAC_DBG_ERR,
+				     "[ERR]Endian setting err!!\n");
+		return HALMAC_RET_ENDIAN_ERR;
+	}
+
+	buf = (u8 *)pltfm_api->RTL_MALLOC(drv_adapter, sizeof(*adapter));
+
+	if (!buf) {
+		pltfm_api->MSG_PRINT(drv_adapter, HALMAC_MSG_INIT,
+				     HALMAC_DBG_ERR,
+				     "[ERR]Malloc HAL adapter err!!\n");
+		return HALMAC_RET_MALLOC_FAIL;
+	}
+	pltfm_api->RTL_MEMSET(drv_adapter, buf, 0x00, sizeof(*adapter));
+	adapter = (struct halmac_adapter *)buf;
+
+	*halmac_adapter = adapter;
+
+	adapter->pltfm_api = pltfm_api;
+	adapter->drv_adapter = drv_adapter;
+	intf = (intf == HALMAC_INTERFACE_AXI) ? HALMAC_INTERFACE_PCIE : intf;
+	adapter->intf = intf;
+
+	if (get_chip_info(drv_adapter, pltfm_api, intf, adapter)
+	    != HALMAC_RET_SUCCESS) {
+		PLTFM_FREE(*halmac_adapter, sizeof(**halmac_adapter));
+		*halmac_adapter = NULL;
+		return HALMAC_RET_CHIP_NOT_SUPPORT;
+	}
+
+	PLTFM_MUTEX_INIT(&adapter->efuse_mutex);
+	PLTFM_MUTEX_INIT(&adapter->h2c_seq_mutex);
+	PLTFM_MUTEX_INIT(&adapter->sdio_indir_mutex);
+
+#if (HALMAC_PLATFORM_WINDOWS == 0)
+
+#if HALMAC_88XX_SUPPORT
+	if (adapter->chip_id == HALMAC_CHIP_ID_8822B ||
+	    adapter->chip_id == HALMAC_CHIP_ID_8821C ||
+	    adapter->chip_id == HALMAC_CHIP_ID_8822C ||
+	    adapter->chip_id == HALMAC_CHIP_ID_8812F) {
+		init_adapter_param_88xx(adapter);
+		status = mount_api_88xx(adapter);
+	}
+#endif
+
+#if HALMAC_88XX_V1_SUPPORT
+	if (adapter->chip_id == HALMAC_CHIP_ID_8814B) {
+		init_adapter_param_88xx_v1(adapter);
+		status = mount_api_88xx_v1(adapter);
+	}
+#if defined(HALMAC_DATA_CPU_EN)
+	if (adapter->chip_id == HALMAC_CHIP_ID_8814B) {
+		init_adapter_param_88xxd_v1(adapter);
+		status = mount_api_88xxd_v1(adapter);
+	}
+#endif
+#endif
+
+#else
+
+#if HALMAC_8822B_SUPPORT
+	if (adapter->chip_id == HALMAC_CHIP_ID_8822B) {
+		init_adapter_param_win8822b(adapter);
+		status = mount_api_win8822b(adapter);
+	}
+#endif
+
+#if HALMAC_8821C_SUPPORT
+	if (adapter->chip_id == HALMAC_CHIP_ID_8821C) {
+		init_adapter_param_win8821c(adapter);
+		status = mount_api_win8821c(adapter);
+	}
+#endif
+
+#if HALMAC_8814B_SUPPORT
+	if (adapter->chip_id == HALMAC_CHIP_ID_8814B) {
+		init_adapter_param_win8814b_v1(adapter);
+		status = mount_api_win8814b_v1(adapter);
+	}
+#endif
+
+#if HALMAC_8822C_SUPPORT
+	if (adapter->chip_id == HALMAC_CHIP_ID_8822C) {
+		init_adapter_param_win8822c(adapter);
+		status = mount_api_win8822c(adapter);
+	}
+#endif
+
+#if HALMAC_8812F_SUPPORT
+	if (adapter->chip_id == HALMAC_CHIP_ID_8812F) {
+		init_adapter_param_win8812f(adapter);
+		status = mount_api_win8812f(adapter);
+	}
+#endif
+
+#endif
+	*halmac_api = (struct halmac_api *)adapter->halmac_api;
+
+	PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
+
+	return status;
+}
+
+/**
+ * halmac_halt_api() - stop halmac_api action
+ * @adapter : the adapter of halmac
+ * Author : Ivan Lin
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+halmac_halt_api(struct halmac_adapter *adapter)
+{
+	PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
+
+	adapter->halmac_state.api_state = HALMAC_API_STATE_HALT;
+
+	PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
+
+	return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * halmac_deinit_adapter() - deinit halmac adapter
+ * @adapter : the adapter of halmac
+ * Author : KaiYuan Chang / Ivan Lin
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+halmac_deinit_adapter(struct halmac_adapter *adapter)
+{
+	PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
+
+	PLTFM_MUTEX_DEINIT(&adapter->efuse_mutex);
+	PLTFM_MUTEX_DEINIT(&adapter->h2c_seq_mutex);
+	PLTFM_MUTEX_DEINIT(&adapter->sdio_indir_mutex);
+
+	if (adapter->efuse_map) {
+		PLTFM_FREE(adapter->efuse_map, adapter->hw_cfg_info.efuse_size);
+		adapter->efuse_map = (u8 *)NULL;
+	}
+
+	if (adapter->sdio_fs.macid_map) {
+		PLTFM_FREE(adapter->sdio_fs.macid_map,
+			   adapter->sdio_fs.macid_map_size);
+		adapter->sdio_fs.macid_map = (u8 *)NULL;
+	}
+
+	if (adapter->halmac_state.psd_state.data) {
+		PLTFM_FREE(adapter->halmac_state.psd_state.data,
+			   adapter->halmac_state.psd_state.data_size);
+		adapter->halmac_state.psd_state.data = (u8 *)NULL;
+	}
+
+	if (adapter->halmac_api) {
+		PLTFM_FREE(adapter->halmac_api, sizeof(struct halmac_api));
+		adapter->halmac_api = NULL;
+	}
+
+	PLTFM_FREE(adapter, sizeof(*adapter));
+
+	return HALMAC_RET_SUCCESS;
+}
+
+static enum halmac_ret_status
+chk_pltfm_api(void *drv_adapter, enum halmac_interface intf,
+	      struct halmac_platform_api *pltfm_api)
+{
+	if (!pltfm_api)
+		return HALMAC_RET_PLATFORM_API_NULL;
+
+	if (!pltfm_api->MSG_PRINT)
+		return HALMAC_RET_PLATFORM_API_NULL;
+
+	if (intf == HALMAC_INTERFACE_SDIO) {
+		if (!pltfm_api->SDIO_CMD52_READ) {
+			pltfm_api->MSG_PRINT(drv_adapter, HALMAC_MSG_INIT,
+					     HALMAC_DBG_ERR, "[ERR]sdio-r\n");
+			return HALMAC_RET_PLATFORM_API_NULL;
+		}
+		if (!pltfm_api->SDIO_CMD53_READ_8) {
+			pltfm_api->MSG_PRINT(drv_adapter, HALMAC_MSG_INIT,
+					     HALMAC_DBG_ERR, "[ERR]sdio-r8\n");
+			return HALMAC_RET_PLATFORM_API_NULL;
+		}
+		if (!pltfm_api->SDIO_CMD53_READ_16) {
+			pltfm_api->MSG_PRINT(drv_adapter, HALMAC_MSG_INIT,
+					     HALMAC_DBG_ERR, "[ERR]sdio-r16\n");
+			return HALMAC_RET_PLATFORM_API_NULL;
+		}
+		if (!pltfm_api->SDIO_CMD53_READ_32) {
+			pltfm_api->MSG_PRINT(drv_adapter, HALMAC_MSG_INIT,
+					     HALMAC_DBG_ERR, "[ERR]sdio-r32\n");
+			return HALMAC_RET_PLATFORM_API_NULL;
+		}
+		if (!pltfm_api->SDIO_CMD53_READ_N) {
+			pltfm_api->MSG_PRINT(drv_adapter, HALMAC_MSG_INIT,
+					     HALMAC_DBG_ERR, "[ERR]sdio-rn\n");
+			return HALMAC_RET_PLATFORM_API_NULL;
+		}
+		if (!pltfm_api->SDIO_CMD52_WRITE) {
+			pltfm_api->MSG_PRINT(drv_adapter, HALMAC_MSG_INIT,
+					     HALMAC_DBG_ERR, "[ERR]sdio-w\n");
+			return HALMAC_RET_PLATFORM_API_NULL;
+		}
+		if (!pltfm_api->SDIO_CMD53_WRITE_8) {
+			pltfm_api->MSG_PRINT(drv_adapter, HALMAC_MSG_INIT,
+					     HALMAC_DBG_ERR, "[ERR]sdio-w8\n");
+			return HALMAC_RET_PLATFORM_API_NULL;
+		}
+		if (!pltfm_api->SDIO_CMD53_WRITE_16) {
+			pltfm_api->MSG_PRINT(drv_adapter, HALMAC_MSG_INIT,
+					     HALMAC_DBG_ERR, "[ERR]sdio-w16\n");
+			return HALMAC_RET_PLATFORM_API_NULL;
+		}
+		if (!pltfm_api->SDIO_CMD53_WRITE_32) {
+			pltfm_api->MSG_PRINT(drv_adapter, HALMAC_MSG_INIT,
+					     HALMAC_DBG_ERR, "[ERR]sdio-w32\n");
+			return HALMAC_RET_PLATFORM_API_NULL;
+		}
+		if (!pltfm_api->SDIO_CMD52_CIA_READ) {
+			pltfm_api->MSG_PRINT(drv_adapter, HALMAC_MSG_INIT,
+					     HALMAC_DBG_ERR, "[ERR]sdio-cia\n");
+			return HALMAC_RET_PLATFORM_API_NULL;
+		}
+	}
+
+	if (intf == HALMAC_INTERFACE_USB || intf == HALMAC_INTERFACE_PCIE) {
+		if (!pltfm_api->REG_READ_8) {
+			pltfm_api->MSG_PRINT(drv_adapter, HALMAC_MSG_INIT,
+					     HALMAC_DBG_ERR, "[ERR]reg-r8\n");
+			return HALMAC_RET_PLATFORM_API_NULL;
+		}
+		if (!pltfm_api->REG_READ_16) {
+			pltfm_api->MSG_PRINT(drv_adapter, HALMAC_MSG_INIT,
+					     HALMAC_DBG_ERR, "[ERR]reg-r16\n");
+			return HALMAC_RET_PLATFORM_API_NULL;
+		}
+		if (!pltfm_api->REG_READ_32) {
+			pltfm_api->MSG_PRINT(drv_adapter, HALMAC_MSG_INIT,
+					     HALMAC_DBG_ERR, "[ERR]reg-r32\n");
+			return HALMAC_RET_PLATFORM_API_NULL;
+		}
+		if (!pltfm_api->REG_WRITE_8) {
+			pltfm_api->MSG_PRINT(drv_adapter, HALMAC_MSG_INIT,
+					     HALMAC_DBG_ERR, "[ERR]reg-w8\n");
+			return HALMAC_RET_PLATFORM_API_NULL;
+		}
+		if (!pltfm_api->REG_WRITE_16) {
+			pltfm_api->MSG_PRINT(drv_adapter, HALMAC_MSG_INIT,
+					     HALMAC_DBG_ERR, "[ERR]reg-w16\n");
+			return HALMAC_RET_PLATFORM_API_NULL;
+		}
+		if (!pltfm_api->REG_WRITE_32) {
+			pltfm_api->MSG_PRINT(drv_adapter, HALMAC_MSG_INIT,
+					     HALMAC_DBG_ERR, "[ERR]reg-w32\n");
+			return HALMAC_RET_PLATFORM_API_NULL;
+		}
+	}
+
+	if (!pltfm_api->RTL_FREE) {
+		pltfm_api->MSG_PRINT(drv_adapter, HALMAC_MSG_INIT,
+				     HALMAC_DBG_ERR, "[ERR]mem-free\n");
+		return HALMAC_RET_PLATFORM_API_NULL;
+	}
+
+	if (!pltfm_api->RTL_MALLOC) {
+		pltfm_api->MSG_PRINT(drv_adapter, HALMAC_MSG_INIT,
+				     HALMAC_DBG_ERR, "[ERR]mem-malloc\n");
+		return HALMAC_RET_PLATFORM_API_NULL;
+	}
+	if (!pltfm_api->RTL_MEMCPY) {
+		pltfm_api->MSG_PRINT(drv_adapter, HALMAC_MSG_INIT,
+				     HALMAC_DBG_ERR, "[ERR]mem-cpy\n");
+		return HALMAC_RET_PLATFORM_API_NULL;
+	}
+	if (!pltfm_api->RTL_MEMSET) {
+		pltfm_api->MSG_PRINT(drv_adapter, HALMAC_MSG_INIT,
+				     HALMAC_DBG_ERR, "[ERR]mem-set\n");
+		return HALMAC_RET_PLATFORM_API_NULL;
+	}
+	if (!pltfm_api->RTL_DELAY_US) {
+		pltfm_api->MSG_PRINT(drv_adapter, HALMAC_MSG_INIT,
+				     HALMAC_DBG_ERR, "[ERR]time-delay\n");
+		return HALMAC_RET_PLATFORM_API_NULL;
+	}
+
+	if (!pltfm_api->MUTEX_INIT) {
+		pltfm_api->MSG_PRINT(drv_adapter, HALMAC_MSG_INIT,
+				     HALMAC_DBG_ERR, "[ERR]mutex-init\n");
+		return HALMAC_RET_PLATFORM_API_NULL;
+	}
+	if (!pltfm_api->MUTEX_DEINIT) {
+		pltfm_api->MSG_PRINT(drv_adapter, HALMAC_MSG_INIT,
+				     HALMAC_DBG_ERR, "[ERR]mutex-deinit\n");
+		return HALMAC_RET_PLATFORM_API_NULL;
+	}
+	if (!pltfm_api->MUTEX_LOCK) {
+		pltfm_api->MSG_PRINT(drv_adapter, HALMAC_MSG_INIT,
+				     HALMAC_DBG_ERR, "[ERR]mutex-lock\n");
+		return HALMAC_RET_PLATFORM_API_NULL;
+	}
+	if (!pltfm_api->MUTEX_UNLOCK) {
+		pltfm_api->MSG_PRINT(drv_adapter, HALMAC_MSG_INIT,
+				     HALMAC_DBG_ERR, "[ERR]mutex-unlock\n");
+		return HALMAC_RET_PLATFORM_API_NULL;
+	}
+	if (!pltfm_api->EVENT_INDICATION) {
+		pltfm_api->MSG_PRINT(drv_adapter, HALMAC_MSG_INIT,
+				     HALMAC_DBG_ERR, "[ERR]event-indication\n");
+		return HALMAC_RET_PLATFORM_API_NULL;
+	}
+
+	return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * halmac_get_version() - get HALMAC version
+ * @version : return version of major, prototype and minor information
+ * Author : KaiYuan Chang / Ivan Lin
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+halmac_get_version(struct halmac_ver *version)
+{
+	version->major_ver = (u8)HALMAC_MAJOR_VER;
+	version->prototype_ver = (u8)HALMAC_PROTOTYPE_VER;
+	version->minor_ver = (u8)HALMAC_MINOR_VER;
+
+	return HALMAC_RET_SUCCESS;
+}
+
+static enum halmac_ret_status
+get_chip_info(void *drv_adapter, struct halmac_platform_api *pltfm_api,
+	      enum halmac_interface intf, struct halmac_adapter *adapter)
+{
+	u8 chip_id;
+	u8 chip_ver;
+	u32 cnt;
+
+	if (adapter->intf == HALMAC_INTERFACE_SDIO) {
+		pltfm_reg_w8_sdio(drv_adapter, pltfm_api, REG_SDIO_HSUS_CTRL,
+				  pltfm_reg_r8_sdio(drv_adapter, pltfm_api,
+						    REG_SDIO_HSUS_CTRL) &
+						    ~(BIT(0)));
+
+		cnt = 10000;
+		while (!(pltfm_reg_r8_sdio(drv_adapter, pltfm_api,
+					   REG_SDIO_HSUS_CTRL) & BIT(1))) {
+			cnt--;
+			if (cnt == 0)
+				return HALMAC_RET_SDIO_LEAVE_SUSPEND_FAIL;
+		}
+
+		chip_id = pltfm_reg_r_indir_sdio(drv_adapter, pltfm_api,
+						 REG_SYS_CFG2);
+		chip_ver = pltfm_reg_r_indir_sdio(drv_adapter, pltfm_api,
+						  REG_SYS_CFG1 + 1) >> 4;
+	} else {
+		chip_id = pltfm_api->REG_READ_8(drv_adapter, REG_SYS_CFG2);
+		chip_ver = pltfm_api->REG_READ_8(drv_adapter,
+						 REG_SYS_CFG1 + 1) >> 4;
+	}
+
+	adapter->chip_ver = (enum halmac_chip_ver)chip_ver;
+
+	if (chip_id == CHIP_ID_HW_DEF_8822B) {
+		adapter->chip_id = HALMAC_CHIP_ID_8822B;
+	} else if (chip_id == CHIP_ID_HW_DEF_8821C) {
+		adapter->chip_id = HALMAC_CHIP_ID_8821C;
+	} else if (chip_id == CHIP_ID_HW_DEF_8814B) {
+		adapter->chip_id = HALMAC_CHIP_ID_8814B;
+	} else if (chip_id == CHIP_ID_HW_DEF_8197F) {
+		adapter->chip_id = HALMAC_CHIP_ID_8197F;
+	} else if (chip_id == CHIP_ID_HW_DEF_8822C) {
+		adapter->chip_id = HALMAC_CHIP_ID_8822C;
+	} else if (chip_id == CHIP_ID_HW_DEF_8812F) {
+		adapter->chip_id = HALMAC_CHIP_ID_8812F;
+	} else {
+		adapter->chip_id = HALMAC_CHIP_ID_UNDEFINE;
+		PLTFM_MSG_ERR("[ERR]Chip id is undefined\n");
+		return HALMAC_RET_CHIP_NOT_SUPPORT;
+	}
+
+	return HALMAC_RET_SUCCESS;
+}
+
+static u8
+pltfm_reg_r8_sdio(void *drv_adapter, struct halmac_platform_api *pltfm_api,
+		  u32 offset)
+{
+	u8 value8;
+	enum halmac_ret_status status = HALMAC_RET_SUCCESS;
+
+	if (0 == (offset & 0xFFFF0000))
+		offset |= WLAN_IOREG_OFFSET;
+
+	status = cnv_to_sdio_bus_offset(&offset);
+	if (status != HALMAC_RET_SUCCESS)
+		return status;
+
+	value8 = pltfm_api->SDIO_CMD52_READ(drv_adapter, offset);
+
+	return value8;
+}
+
+static enum halmac_ret_status
+pltfm_reg_w8_sdio(void *drv_adapter, struct halmac_platform_api *pltfm_api,
+		  u32 offset, u8 data)
+{
+	enum halmac_ret_status status = HALMAC_RET_SUCCESS;
+
+	if (0 == (offset & 0xFFFF0000))
+		offset |= WLAN_IOREG_OFFSET;
+
+	status = cnv_to_sdio_bus_offset(&offset);
+
+	if (status != HALMAC_RET_SUCCESS)
+		return status;
+
+	pltfm_api->SDIO_CMD52_WRITE(drv_adapter, offset, data);
+
+	return HALMAC_RET_SUCCESS;
+}
+
+static u8
+pltfm_reg_r_indir_sdio(void *drv_adapter, struct halmac_platform_api *pltfm_api,
+		       u32 offset)
+{
+	u8 value8, tmp, cnt = 50;
+	u32 reg_cfg = REG_SDIO_INDIRECT_REG_CFG;
+	u32 reg_data = REG_SDIO_INDIRECT_REG_DATA;
+	enum halmac_ret_status status = HALMAC_RET_SUCCESS;
+
+	status = cnv_to_sdio_bus_offset(&reg_cfg);
+	if (status != HALMAC_RET_SUCCESS)
+		return status;
+	status = cnv_to_sdio_bus_offset(&reg_data);
+	if (status != HALMAC_RET_SUCCESS)
+		return status;
+
+	pltfm_api->SDIO_CMD52_WRITE(drv_adapter, reg_cfg, (u8)offset);
+	pltfm_api->SDIO_CMD52_WRITE(drv_adapter, reg_cfg + 1,
+				    (u8)(offset >> 8));
+	pltfm_api->SDIO_CMD52_WRITE(drv_adapter, reg_cfg + 2,
+				    (u8)(BIT(3) | BIT(4)));
+
+	do {
+		tmp = pltfm_api->SDIO_CMD52_READ(drv_adapter, reg_cfg + 2);
+		cnt--;
+	} while (((tmp & BIT(4)) == 0) && (cnt > 0));
+
+	if (((cnt & BIT(4)) == 0) && cnt == 0)
+		pltfm_api->MSG_PRINT(drv_adapter, HALMAC_MSG_INIT,
+				     HALMAC_DBG_ERR, "[ERR]sdio indir read\n");
+
+	value8 = pltfm_api->SDIO_CMD52_READ(drv_adapter, reg_data);
+
+	return value8;
+}
+
+/*Note: copy from cnv_to_sdio_bus_offset_88xx*/
+static enum halmac_ret_status
+cnv_to_sdio_bus_offset(u32 *offset)
+{
+	switch ((*offset) & 0xFFFF0000) {
+	case WLAN_IOREG_OFFSET:
+		*offset &= HALMAC_WLAN_MAC_REG_MSK;
+		*offset |= HALMAC_SDIO_CMD_ADDR_MAC_REG << 13;
+		break;
+	case SDIO_LOCAL_OFFSET:
+		*offset &= HALMAC_SDIO_LOCAL_MSK;
+		*offset |= HALMAC_SDIO_CMD_ADDR_SDIO_REG << 13;
+		break;
+	default:
+		*offset = 0xFFFFFFFF;
+		return HALMAC_RET_CONVERT_SDIO_OFFSET_FAIL;
+	}
+
+	return HALMAC_RET_SUCCESS;
+}
+
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/halmac/halmac_api.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/halmac/halmac_api.h
--- linux-5.6.3/3rdparty/rtl8821ce/hal/halmac/halmac_api.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/halmac/halmac_api.h	2020-04-10 16:35:06.794659041 +0300
@@ -0,0 +1,120 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ ******************************************************************************/
+
+#ifndef _HALMAC_API_H_
+#define _HALMAC_API_H_
+
+#define HALMAC_SVN_VER  "11692M"
+
+#define HALMAC_MAJOR_VER        0x0001
+#define HALMAC_PROTOTYPE_VER    0x0005
+#define HALMAC_MINOR_VER        0x0000
+#define HALMAC_PATCH_VER        0x0002
+
+#define HALMAC_88XX_SUPPORT	(HALMAC_8821C_SUPPORT || \
+				 HALMAC_8822B_SUPPORT || \
+				 HALMAC_8822C_SUPPORT || \
+				 HALMAC_8812F_SUPPORT)
+
+#define HALMAC_88XX_V1_SUPPORT	HALMAC_8814B_SUPPORT
+
+#include "halmac_2_platform.h"
+#include "halmac_type.h"
+#include "halmac_hw_cfg.h"
+#include "halmac_usb_reg.h"
+#include "halmac_sdio_reg.h"
+#include "halmac_pcie_reg.h"
+#include "halmac_bit2.h"
+#include "halmac_reg2.h"
+
+#if HALMAC_PLATFORM_TESTPROGRAM
+#include "halmac_type_testprogram.h"
+#endif
+
+#ifndef HALMAC_USE_TYPEDEF
+#define HALMAC_USE_TYPEDEF	1
+#endif
+
+#if HALMAC_USE_TYPEDEF
+#include "halmac_typedef.h"
+#endif
+
+#if HALMAC_8822B_SUPPORT
+#include "halmac_reg_8822b.h"
+#include "halmac_bit_8822b.h"
+#endif
+
+#if HALMAC_8821C_SUPPORT
+#include "halmac_reg_8821c.h"
+#include "halmac_bit_8821c.h"
+#endif
+
+#if HALMAC_8814B_SUPPORT
+#include "halmac_reg_8814b.h"
+#include "halmac_bit_8814b.h"
+#endif
+
+#if HALMAC_8822C_SUPPORT
+#include "halmac_reg_8822c.h"
+#include "halmac_bit_8822c.h"
+#endif
+
+#if (HALMAC_PLATFORM_WINDOWS || HALMAC_PLATFORM_LINUX)
+#include "halmac_tx_desc_nic.h"
+#include "halmac_tx_desc_buffer_nic.h"
+#include "halmac_tx_desc_ie_nic.h"
+#include "halmac_rx_desc_nic.h"
+#include "halmac_tx_bd_nic.h"
+#include "halmac_rx_bd_nic.h"
+#include "halmac_fw_offload_c2h_nic.h"
+#include "halmac_fw_offload_h2c_nic.h"
+#include "halmac_h2c_extra_info_nic.h"
+#include "halmac_original_c2h_nic.h"
+#include "halmac_original_h2c_nic.h"
+#endif
+
+#if (HALMAC_PLATFORM_AP)
+#include "halmac_rx_desc_ap.h"
+#include "halmac_tx_desc_ap.h"
+#include "halmac_tx_desc_buffer_ap.h"
+#include "halmac_tx_desc_ie_ap.h"
+#include "halmac_fw_offload_c2h_ap.h"
+#include "halmac_fw_offload_h2c_ap.h"
+#include "halmac_h2c_extra_info_ap.h"
+#include "halmac_original_c2h_ap.h"
+#include "halmac_original_h2c_ap.h"
+#endif
+
+#include "halmac_tx_desc_chip.h"
+#include "halmac_rx_desc_chip.h"
+#include "halmac_tx_desc_buffer_chip.h"
+#include "halmac_tx_desc_ie_chip.h"
+
+enum halmac_ret_status
+halmac_init_adapter(void *drv_adapter, struct halmac_platform_api *pltfm_api,
+		    enum halmac_interface intf,
+		    struct halmac_adapter **halmac_adapter,
+		    struct halmac_api **halmac_api);
+
+enum halmac_ret_status
+halmac_deinit_adapter(struct halmac_adapter *adapter);
+
+enum halmac_ret_status
+halmac_halt_api(struct halmac_adapter *adapter);
+
+enum halmac_ret_status
+halmac_get_version(struct halmac_ver *version);
+
+#endif
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/halmac/halmac_bit2.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/halmac/halmac_bit2.h
--- linux-5.6.3/3rdparty/rtl8821ce/hal/halmac/halmac_bit2.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/halmac/halmac_bit2.h	2020-04-10 16:35:06.798659227 +0300
@@ -0,0 +1,73023 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ ******************************************************************************/
+
+#ifndef __RTL_WLAN_BITDEF_H__
+#define __RTL_WLAN_BITDEF_H__
+
+#include "halmac_hw_cfg.h"
+
+#define CPU_OPT_WIDTH 0x1F
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define BIT_WRITE_ENABLE BIT(31)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+#define BIT_MEM_RMV_SIGN BIT(31)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define BIT_QUEUE_MACID_AC_NOT_THE_SAME BIT(31)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define BIT_SHIFT_LLTE_RWM 30
+#define BIT_MASK_LLTE_RWM 0x3
+#define BIT_LLTE_RWM(x) (((x) & BIT_MASK_LLTE_RWM) << BIT_SHIFT_LLTE_RWM)
+#define BITS_LLTE_RWM (BIT_MASK_LLTE_RWM << BIT_SHIFT_LLTE_RWM)
+#define BIT_CLEAR_LLTE_RWM(x) ((x) & (~BITS_LLTE_RWM))
+#define BIT_GET_LLTE_RWM(x) (((x) >> BIT_SHIFT_LLTE_RWM) & BIT_MASK_LLTE_RWM)
+#define BIT_SET_LLTE_RWM(x, v) (BIT_CLEAR_LLTE_RWM(x) | BIT_LLTE_RWM(v))
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+#define BIT_MEM_RMV_2PRF1 BIT(29)
+#define BIT_MEM_RMV_2PRF0 BIT(28)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define BIT_SHIFT_GTAB_ID 28
+#define BIT_MASK_GTAB_ID 0x7
+#define BIT_GTAB_ID(x) (((x) & BIT_MASK_GTAB_ID) << BIT_SHIFT_GTAB_ID)
+#define BITS_GTAB_ID (BIT_MASK_GTAB_ID << BIT_SHIFT_GTAB_ID)
+#define BIT_CLEAR_GTAB_ID(x) ((x) & (~BITS_GTAB_ID))
+#define BIT_GET_GTAB_ID(x) (((x) >> BIT_SHIFT_GTAB_ID) & BIT_MASK_GTAB_ID)
+#define BIT_SET_GTAB_ID(x, v) (BIT_CLEAR_GTAB_ID(x) | BIT_GTAB_ID(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+
+#define BIT_MULRW BIT(27)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+#define BIT_MEM_RMV_1PRF1 BIT(27)
+#define BIT_MEM_RMV_1PRF0 BIT(26)
+#define BIT_MEM_RMV_1PSR BIT(25)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+     HALMAC_8881A_SUPPORT)
+
+#define BIT_SHIFT_MBIDCAM_ADDR 24
+#define BIT_MASK_MBIDCAM_ADDR 0x1f
+#define BIT_MBIDCAM_ADDR(x)                                                    \
+	(((x) & BIT_MASK_MBIDCAM_ADDR) << BIT_SHIFT_MBIDCAM_ADDR)
+#define BITS_MBIDCAM_ADDR (BIT_MASK_MBIDCAM_ADDR << BIT_SHIFT_MBIDCAM_ADDR)
+#define BIT_CLEAR_MBIDCAM_ADDR(x) ((x) & (~BITS_MBIDCAM_ADDR))
+#define BIT_GET_MBIDCAM_ADDR(x)                                                \
+	(((x) >> BIT_SHIFT_MBIDCAM_ADDR) & BIT_MASK_MBIDCAM_ADDR)
+#define BIT_SET_MBIDCAM_ADDR(x, v)                                             \
+	(BIT_CLEAR_MBIDCAM_ADDR(x) | BIT_MBIDCAM_ADDR(v))
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+#define BIT_MEM_RMV_ROM BIT(24)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define BIT_CPRST BIT(23)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define BIT_CTS_EN BIT(16)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define BIT_SHIFT_R_OFDM_LEN_V1 16
+#define BIT_MASK_R_OFDM_LEN_V1 0xffff
+#define BIT_R_OFDM_LEN_V1(x)                                                   \
+	(((x) & BIT_MASK_R_OFDM_LEN_V1) << BIT_SHIFT_R_OFDM_LEN_V1)
+#define BITS_R_OFDM_LEN_V1 (BIT_MASK_R_OFDM_LEN_V1 << BIT_SHIFT_R_OFDM_LEN_V1)
+#define BIT_CLEAR_R_OFDM_LEN_V1(x) ((x) & (~BITS_R_OFDM_LEN_V1))
+#define BIT_GET_R_OFDM_LEN_V1(x)                                               \
+	(((x) >> BIT_SHIFT_R_OFDM_LEN_V1) & BIT_MASK_R_OFDM_LEN_V1)
+#define BIT_SET_R_OFDM_LEN_V1(x, v)                                            \
+	(BIT_CLEAR_R_OFDM_LEN_V1(x) | BIT_R_OFDM_LEN_V1(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822C_SUPPORT)
+
+#define BIT_SHIFT_COUNTER_BASE 16
+#define BIT_MASK_COUNTER_BASE 0x1fff
+#define BIT_COUNTER_BASE(x)                                                    \
+	(((x) & BIT_MASK_COUNTER_BASE) << BIT_SHIFT_COUNTER_BASE)
+#define BITS_COUNTER_BASE (BIT_MASK_COUNTER_BASE << BIT_SHIFT_COUNTER_BASE)
+#define BIT_CLEAR_COUNTER_BASE(x) ((x) & (~BITS_COUNTER_BASE))
+#define BIT_GET_COUNTER_BASE(x)                                                \
+	(((x) >> BIT_SHIFT_COUNTER_BASE) & BIT_MASK_COUNTER_BASE)
+#define BIT_SET_COUNTER_BASE(x, v)                                             \
+	(BIT_CLEAR_COUNTER_BASE(x) | BIT_COUNTER_BASE(v))
+
+#define BIT_SHIFT_AGG_VALUE2 16
+#define BIT_MASK_AGG_VALUE2 0x7f
+#define BIT_AGG_VALUE2(x) (((x) & BIT_MASK_AGG_VALUE2) << BIT_SHIFT_AGG_VALUE2)
+#define BITS_AGG_VALUE2 (BIT_MASK_AGG_VALUE2 << BIT_SHIFT_AGG_VALUE2)
+#define BIT_CLEAR_AGG_VALUE2(x) ((x) & (~BITS_AGG_VALUE2))
+#define BIT_GET_AGG_VALUE2(x)                                                  \
+	(((x) >> BIT_SHIFT_AGG_VALUE2) & BIT_MASK_AGG_VALUE2)
+#define BIT_SET_AGG_VALUE2(x, v) (BIT_CLEAR_AGG_VALUE2(x) | BIT_AGG_VALUE2(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define BIT_QUEUE_MACID_AC_NOT_THE_SAME_V1 BIT(15)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+#define BIT_SHIFT_XTAL_DRV_RF1 13
+#define BIT_MASK_XTAL_DRV_RF1 0x3
+#define BIT_XTAL_DRV_RF1(x)                                                    \
+	(((x) & BIT_MASK_XTAL_DRV_RF1) << BIT_SHIFT_XTAL_DRV_RF1)
+#define BITS_XTAL_DRV_RF1 (BIT_MASK_XTAL_DRV_RF1 << BIT_SHIFT_XTAL_DRV_RF1)
+#define BIT_CLEAR_XTAL_DRV_RF1(x) ((x) & (~BITS_XTAL_DRV_RF1))
+#define BIT_GET_XTAL_DRV_RF1(x)                                                \
+	(((x) >> BIT_SHIFT_XTAL_DRV_RF1) & BIT_MASK_XTAL_DRV_RF1)
+#define BIT_SET_XTAL_DRV_RF1(x, v)                                             \
+	(BIT_CLEAR_XTAL_DRV_RF1(x) | BIT_XTAL_DRV_RF1(v))
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+
+#define BIT_DISABLE_B0 BIT(13)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define BIT_ATIMEND BIT(12)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define BIT_SHIFT_GTAB_ID_V1 12
+#define BIT_MASK_GTAB_ID_V1 0x7
+#define BIT_GTAB_ID_V1(x) (((x) & BIT_MASK_GTAB_ID_V1) << BIT_SHIFT_GTAB_ID_V1)
+#define BITS_GTAB_ID_V1 (BIT_MASK_GTAB_ID_V1 << BIT_SHIFT_GTAB_ID_V1)
+#define BIT_CLEAR_GTAB_ID_V1(x) ((x) & (~BITS_GTAB_ID_V1))
+#define BIT_GET_GTAB_ID_V1(x)                                                  \
+	(((x) >> BIT_SHIFT_GTAB_ID_V1) & BIT_MASK_GTAB_ID_V1)
+#define BIT_SET_GTAB_ID_V1(x, v) (BIT_CLEAR_GTAB_ID_V1(x) | BIT_GTAB_ID_V1(v))
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define BIT_SHIFT_WATCH_DOG_RECORD_V1 10
+#define BIT_MASK_WATCH_DOG_RECORD_V1 0x3fff
+#define BIT_WATCH_DOG_RECORD_V1(x)                                             \
+	(((x) & BIT_MASK_WATCH_DOG_RECORD_V1) << BIT_SHIFT_WATCH_DOG_RECORD_V1)
+#define BITS_WATCH_DOG_RECORD_V1                                               \
+	(BIT_MASK_WATCH_DOG_RECORD_V1 << BIT_SHIFT_WATCH_DOG_RECORD_V1)
+#define BIT_CLEAR_WATCH_DOG_RECORD_V1(x) ((x) & (~BITS_WATCH_DOG_RECORD_V1))
+#define BIT_GET_WATCH_DOG_RECORD_V1(x)                                         \
+	(((x) >> BIT_SHIFT_WATCH_DOG_RECORD_V1) & BIT_MASK_WATCH_DOG_RECORD_V1)
+#define BIT_SET_WATCH_DOG_RECORD_V1(x, v)                                      \
+	(BIT_CLEAR_WATCH_DOG_RECORD_V1(x) | BIT_WATCH_DOG_RECORD_V1(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8881A_SUPPORT)
+
+#define BIT_R_8051_SPD BIT(9)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define BIT_R_IO_TIMEOUT_FLAG_V1 BIT(9)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822C_SUPPORT)
+
+#define BIT_EN_RTS_REQ BIT(9)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define BIT_EN_WATCH_DOG_V1 BIT(8)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822C_SUPPORT)
+
+#define BIT_EN_EDCA_REQ BIT(8)
+
+#define BIT_SHIFT_AGG_VALUE1 8
+#define BIT_MASK_AGG_VALUE1 0x7f
+#define BIT_AGG_VALUE1(x) (((x) & BIT_MASK_AGG_VALUE1) << BIT_SHIFT_AGG_VALUE1)
+#define BITS_AGG_VALUE1 (BIT_MASK_AGG_VALUE1 << BIT_SHIFT_AGG_VALUE1)
+#define BIT_CLEAR_AGG_VALUE1(x) ((x) & (~BITS_AGG_VALUE1))
+#define BIT_GET_AGG_VALUE1(x)                                                  \
+	(((x) >> BIT_SHIFT_AGG_VALUE1) & BIT_MASK_AGG_VALUE1)
+#define BIT_SET_AGG_VALUE1(x, v) (BIT_CLEAR_AGG_VALUE1(x) | BIT_AGG_VALUE1(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+     HALMAC_8822C_SUPPORT)
+
+#define BIT_DIS_TXDMA_PRE BIT(7)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8881A_SUPPORT)
+
+#define BIT_RAM_DL_SEL BIT(7)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822C_SUPPORT)
+
+#define BIT_EN_PTCL_REQ BIT(7)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+     HALMAC_8822C_SUPPORT)
+
+#define BIT_DIS_RXDMA_PRE BIT(6)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8881A_SUPPORT)
+
+#define BIT_WINTINI_RDY BIT(6)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822C_SUPPORT)
+
+#define BIT_EN_SCH_REQ BIT(6)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+#define BIT_CLR_HGQ_REQ_BLOCK BIT(5)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+     HALMAC_8822C_SUPPORT)
+
+#define BIT_TXFLAG_EXIT_L1_EN BIT(2)
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define BIT_DATA_FW_STS_FILTER BIT(2)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+#define BIT_EN_RXDMA_ALIGN_V1 BIT(1)
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define BIT_CTRL_FW_STS_FILTER BIT(1)
+
+#endif
+
+#if (HALMAC_8881A_SUPPORT)
+
+#define BIT_AFE_MBIAS BIT(1)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT)
+
+#define BIT_SHIFT_MDIO_REG_ADDR 0
+#define BIT_MASK_MDIO_REG_ADDR 0x1f
+#define BIT_MDIO_REG_ADDR(x)                                                   \
+	(((x) & BIT_MASK_MDIO_REG_ADDR) << BIT_SHIFT_MDIO_REG_ADDR)
+#define BITS_MDIO_REG_ADDR (BIT_MASK_MDIO_REG_ADDR << BIT_SHIFT_MDIO_REG_ADDR)
+#define BIT_CLEAR_MDIO_REG_ADDR(x) ((x) & (~BITS_MDIO_REG_ADDR))
+#define BIT_GET_MDIO_REG_ADDR(x)                                               \
+	(((x) >> BIT_SHIFT_MDIO_REG_ADDR) & BIT_MASK_MDIO_REG_ADDR)
+#define BIT_SET_MDIO_REG_ADDR(x, v)                                            \
+	(BIT_CLEAR_MDIO_REG_ADDR(x) | BIT_MDIO_REG_ADDR(v))
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+#define BIT_EN_TXDMA_ALIGN_V1 BIT(0)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822C_SUPPORT)
+
+#define BIT_SHIFT_AGG_VALUE0 0
+#define BIT_MASK_AGG_VALUE0 0x7f
+#define BIT_AGG_VALUE0(x) (((x) & BIT_MASK_AGG_VALUE0) << BIT_SHIFT_AGG_VALUE0)
+#define BITS_AGG_VALUE0 (BIT_MASK_AGG_VALUE0 << BIT_SHIFT_AGG_VALUE0)
+#define BIT_CLEAR_AGG_VALUE0(x) ((x) & (~BITS_AGG_VALUE0))
+#define BIT_GET_AGG_VALUE0(x)                                                  \
+	(((x) >> BIT_SHIFT_AGG_VALUE0) & BIT_MASK_AGG_VALUE0)
+#define BIT_SET_AGG_VALUE0(x, v) (BIT_CLEAR_AGG_VALUE0(x) | BIT_AGG_VALUE0(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define BIT_SHIFT_BW_CFG 0
+#define BIT_MASK_BW_CFG 0x3
+#define BIT_BW_CFG(x) (((x) & BIT_MASK_BW_CFG) << BIT_SHIFT_BW_CFG)
+#define BITS_BW_CFG (BIT_MASK_BW_CFG << BIT_SHIFT_BW_CFG)
+#define BIT_CLEAR_BW_CFG(x) ((x) & (~BITS_BW_CFG))
+#define BIT_GET_BW_CFG(x) (((x) >> BIT_SHIFT_BW_CFG) & BIT_MASK_BW_CFG)
+#define BIT_SET_BW_CFG(x, v) (BIT_CLEAR_BW_CFG(x) | BIT_BW_CFG(v))
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define BIT_MGNT_FW_STS_FILTER BIT(0)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8822B_SUPPORT)
+
+#define BIT_ISO_MD2PP BIT(0)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_SDIO_TX_CTRL			(Offset 0x10250000) */
+
+#define BIT_SHIFT_SDIO_INT_TIMEOUT 16
+#define BIT_MASK_SDIO_INT_TIMEOUT 0xffff
+#define BIT_SDIO_INT_TIMEOUT(x)                                                \
+	(((x) & BIT_MASK_SDIO_INT_TIMEOUT) << BIT_SHIFT_SDIO_INT_TIMEOUT)
+#define BITS_SDIO_INT_TIMEOUT                                                  \
+	(BIT_MASK_SDIO_INT_TIMEOUT << BIT_SHIFT_SDIO_INT_TIMEOUT)
+#define BIT_CLEAR_SDIO_INT_TIMEOUT(x) ((x) & (~BITS_SDIO_INT_TIMEOUT))
+#define BIT_GET_SDIO_INT_TIMEOUT(x)                                            \
+	(((x) >> BIT_SHIFT_SDIO_INT_TIMEOUT) & BIT_MASK_SDIO_INT_TIMEOUT)
+#define BIT_SET_SDIO_INT_TIMEOUT(x, v)                                         \
+	(BIT_CLEAR_SDIO_INT_TIMEOUT(x) | BIT_SDIO_INT_TIMEOUT(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_SYS_ISO_CTRL			(Offset 0x0000) */
+
+#define BIT_PWC_EV12V BIT(15)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_SYS_ISO_CTRL			(Offset 0x0000) */
+
+#define BIT_PWC_ON2EF BIT(15)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_SDIO_TX_CTRL			(Offset 0x10250000) */
+
+#define BIT_IO_ERR_STATUS BIT(15)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_SYS_ISO_CTRL			(Offset 0x0000) */
+
+#define BIT_PWC_EBCOEB BIT(15)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_SYS_ISO_CTRL			(Offset 0x0000) */
+
+#define BIT_PWC_EV25V BIT(14)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_SYS_ISO_CTRL			(Offset 0x0000) */
+
+#define BIT_PWC_EV2EF BIT(14)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_SDIO_TX_CTRL			(Offset 0x10250000) */
+
+#define BIT_CMD53_W_MIX BIT(14)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8881A_SUPPORT)
+
+/* 2 REG_SYS_ISO_CTRL			(Offset 0x0000) */
+
+#define BIT_PA33V_EN BIT(13)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_SDIO_TX_CTRL			(Offset 0x10250000) */
+
+#define BIT_CMD53_TX_FORMAT BIT(13)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8881A_SUPPORT)
+
+/* 2 REG_SYS_ISO_CTRL			(Offset 0x0000) */
+
+#define BIT_PA12V_EN BIT(12)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_SDIO_TX_CTRL			(Offset 0x10250000) */
+
+#define BIT_CMD53_R_TIMEOUT_MASK BIT(12)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_SYS_ISO_CTRL			(Offset 0x0000) */
+
+#define BIT_PC_A15V BIT(12)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8881A_SUPPORT)
+
+/* 2 REG_SYS_ISO_CTRL			(Offset 0x0000) */
+
+#define BIT_UA33V_EN BIT(11)
+#define BIT_UA12V_EN BIT(10)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_SDIO_TX_CTRL			(Offset 0x10250000) */
+
+#define BIT_SHIFT_CMD53_R_TIMEOUT_UNIT 10
+#define BIT_MASK_CMD53_R_TIMEOUT_UNIT 0x3
+#define BIT_CMD53_R_TIMEOUT_UNIT(x)                                            \
+	(((x) & BIT_MASK_CMD53_R_TIMEOUT_UNIT)                                 \
+	 << BIT_SHIFT_CMD53_R_TIMEOUT_UNIT)
+#define BITS_CMD53_R_TIMEOUT_UNIT                                              \
+	(BIT_MASK_CMD53_R_TIMEOUT_UNIT << BIT_SHIFT_CMD53_R_TIMEOUT_UNIT)
+#define BIT_CLEAR_CMD53_R_TIMEOUT_UNIT(x) ((x) & (~BITS_CMD53_R_TIMEOUT_UNIT))
+#define BIT_GET_CMD53_R_TIMEOUT_UNIT(x)                                        \
+	(((x) >> BIT_SHIFT_CMD53_R_TIMEOUT_UNIT) &                             \
+	 BIT_MASK_CMD53_R_TIMEOUT_UNIT)
+#define BIT_SET_CMD53_R_TIMEOUT_UNIT(x, v)                                     \
+	(BIT_CLEAR_CMD53_R_TIMEOUT_UNIT(x) | BIT_CMD53_R_TIMEOUT_UNIT(v))
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_SYS_ISO_CTRL			(Offset 0x0000) */
+
+#define BIT_ISO_AFE_OUTPUT_SIGNAL BIT(10)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8881A_SUPPORT)
+
+/* 2 REG_SYS_ISO_CTRL			(Offset 0x0000) */
+
+#define BIT_ISO_RFDIO BIT(9)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_SDIO_TX_CTRL			(Offset 0x10250000) */
+
+#define BIT_REPLY_ERRCRC_IN_DATA BIT(9)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_SYS_ISO_CTRL			(Offset 0x0000) */
+
+#define BIT_ISO_EB2CORE BIT(8)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_SYS_ISO_CTRL			(Offset 0x0000) */
+
+#define BIT_ISO_EF2PP BIT(8)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_SDIO_TX_CTRL			(Offset 0x10250000) */
+
+#define BIT_EN_CMD53_OVERLAP BIT(8)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_SYS_ISO_CTRL			(Offset 0x0000) */
+
+#define BIT_ISO_DIOE BIT(7)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_SYS_ISO_CTRL			(Offset 0x0000) */
+
+#define BIT_ISO_EXTIO BIT(7)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_SDIO_TX_CTRL			(Offset 0x10250000) */
+
+#define BIT_REPLY_ERR_IN_R5 BIT(7)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_SYS_ISO_CTRL			(Offset 0x0000) */
+
+#define BIT_ISO_DIOP BIT(6)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_SYS_ISO_CTRL			(Offset 0x0000) */
+
+#define BIT_ISO_WLPON2PP BIT(6)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_SDIO_TX_CTRL			(Offset 0x10250000) */
+
+#define BIT_R18A_EN BIT(6)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_SYS_ISO_CTRL			(Offset 0x0000) */
+
+#define BIT_ISO_IP2MAC_WA2PP BIT(5)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_SYS_ISO_CTRL			(Offset 0x0000) */
+
+#define BIT_ISO_WA2PP BIT(5)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_SDIO_TX_CTRL			(Offset 0x10250000) */
+
+#define BIT_SDIO_CMD_FORCE_VLD BIT(5)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_SYS_ISO_CTRL			(Offset 0x0000) */
+
+#define BIT_ISO_PD2CORE BIT(4)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_SYS_ISO_CTRL			(Offset 0x0000) */
+
+#define BIT_ISO_PD2PP BIT(4)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_SDIO_TX_CTRL			(Offset 0x10250000) */
+
+#define BIT_INIT_CMD_EN BIT(4)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_SYS_ISO_CTRL			(Offset 0x0000) */
+
+#define BIT_ISO_PA2PCIE BIT(3)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_SYS_ISO_CTRL			(Offset 0x0000) */
+
+#define BIT_ISO_PA2PD BIT(3)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_SDIO_TX_CTRL			(Offset 0x10250000) */
+
+#define BIT_RXINT_READ_MASK_DIS BIT(3)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_SDIO_TX_CTRL			(Offset 0x10250000) */
+
+#define BIT_EN_32K_TRANS BIT(3)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_SYS_ISO_CTRL			(Offset 0x0000) */
+
+#define BIT_ISO_UD2CORE BIT(2)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_SYS_ISO_CTRL			(Offset 0x0000) */
+
+#define BIT_ISO_UD2PP BIT(2)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_SDIO_TX_CTRL			(Offset 0x10250000) */
+
+#define BIT_EN_RXDMA_MASK_INT BIT(2)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_SYS_ISO_CTRL			(Offset 0x0000) */
+
+#define BIT_ISO_HD2CORE BIT(2)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_SYS_ISO_CTRL			(Offset 0x0000) */
+
+#define BIT_ISO_UA2USB BIT(1)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_SYS_ISO_CTRL			(Offset 0x0000) */
+
+#define BIT_ISO_UA2UD BIT(1)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_SDIO_TX_CTRL			(Offset 0x10250000) */
+
+#define BIT_EN_MASK_TIMER BIT(1)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_SYS_ISO_CTRL			(Offset 0x0000) */
+
+#define BIT_ISO_WD2PP BIT(0)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_SYS_ISO_CTRL			(Offset 0x0000) */
+
+#define BIT_ISO_WL2PP BIT(0)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_SDIO_TX_CTRL			(Offset 0x10250000) */
+
+#define BIT_CMD_ERR_STOP_INT_EN BIT(0)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_SYS_FUNC_EN				(Offset 0x0002) */
+
+#define BIT_FEN_MREGEN BIT(15)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_SYS_FUNC_EN				(Offset 0x0002) */
+
+#define BIT_FEN_WLMACPON BIT(15)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_SYS_FUNC_EN				(Offset 0x0002) */
+
+#define BIT_FEN_HWPDN BIT(14)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_SYS_FUNC_EN				(Offset 0x0002) */
+
+#define BIT_AIP_PD12_N BIT(14)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8881A_SUPPORT)
+
+/* 2 REG_SYS_FUNC_EN				(Offset 0x0002) */
+
+#define BIT_EN_25_1 BIT(13)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_SYS_FUNC_EN				(Offset 0x0002) */
+
+#define BIT_FEN_ELDR BIT(12)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_SYS_FUNC_EN				(Offset 0x0002) */
+
+#define BIT_FEN_DCORE BIT(11)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_SYS_FUNC_EN				(Offset 0x0002) */
+
+#define BIT_FEN_WLMACPOF BIT(11)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_SYS_FUNC_EN				(Offset 0x0002) */
+
+#define BIT_FEN_CPUEN BIT(10)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_SYS_FUNC_EN				(Offset 0x0002) */
+
+#define BIT_FEN_DIOE BIT(9)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_SYS_FUNC_EN				(Offset 0x0002) */
+
+#define BIT_FEN_EXTIO BIT(9)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_SYS_FUNC_EN				(Offset 0x0002) */
+
+#define BIT_FEN_PCIED BIT(8)
+#define BIT_FEN_PPLL BIT(7)
+#define BIT_FEN_PCIEA BIT(6)
+#define BIT_FEN_DIO_PCIE BIT(5)
+#define BIT_FEN_USBD BIT(4)
+#define BIT_FEN_UPLL BIT(3)
+#define BIT_FEN_USBA BIT(2)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_SYS_FUNC_EN				(Offset 0x0002) */
+
+#define BIT_FEN_BB_GLB_RSTN BIT(1)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_SYS_FUNC_EN				(Offset 0x0002) */
+
+#define BIT_FEN_WLPHYGLB BIT(1)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_SYS_FUNC_EN				(Offset 0x0002) */
+
+#define BIT_FEN_BBRSTB BIT(0)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_SYS_FUNC_EN				(Offset 0x0002) */
+
+#define BIT_FEN_WLPHYFUN BIT(0)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8881A_SUPPORT)
+
+/* 2 REG_SYS_PW_CTRL				(Offset 0x0004) */
+
+#define BIT_SOP_EABM BIT(31)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_SYS_PW_CTRL				(Offset 0x0004) */
+
+#define BIT_SKP_ALD BIT(31)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_SYS_PW_CTRL				(Offset 0x0004) */
+
+#define BIT_SOP_ACKF BIT(30)
+#define BIT_SOP_ERCK BIT(29)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8881A_SUPPORT)
+
+/* 2 REG_SYS_PW_CTRL				(Offset 0x0004) */
+
+#define BIT_SOP_ESWR BIT(28)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_SYS_PW_CTRL				(Offset 0x0004) */
+
+#define BIT_SOP_AFEP BIT(28)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8881A_SUPPORT)
+
+/* 2 REG_SYS_PW_CTRL				(Offset 0x0004) */
+
+#define BIT_SOP_PWMM BIT(27)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_SYS_PW_CTRL				(Offset 0x0004) */
+
+#define BIT_SOP_EPWM BIT(27)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_SYS_PW_CTRL				(Offset 0x0004) */
+
+#define BIT_SOP_EECK BIT(26)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_SYS_PW_CTRL				(Offset 0x0004) */
+
+#define BIT_PMC_RATIO_BIT2 BIT(25)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_SYS_PW_CTRL				(Offset 0x0004) */
+
+#define BIT_SOP_ANA_CLK_DIVISION_2 BIT(25)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_SYS_PW_CTRL				(Offset 0x0004) */
+
+#define BIT_ROP_ENXT BIT(25)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_SYS_PW_CTRL				(Offset 0x0004) */
+
+#define BIT_SOP_EXTL BIT(24)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_SYS_PW_CTRL				(Offset 0x0004) */
+
+#define BIT_PMC_RATIO_BIT1 BIT(23)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_SYS_PW_CTRL				(Offset 0x0004) */
+
+#define BIT_CHIPOFF_EN BIT(23)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8881A_SUPPORT)
+
+/* 2 REG_SYS_PW_CTRL				(Offset 0x0004) */
+
+#define BIT_SYM_OP_RING_12M BIT(22)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_SYS_PW_CTRL				(Offset 0x0004) */
+
+#define BIT_DIS_USB3_SUS_ALD BIT(22)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_SYS_PW_CTRL				(Offset 0x0004) */
+
+#define BIT_ROP_SWPR BIT(21)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8881A_SUPPORT)
+
+/* 2 REG_SYS_PW_CTRL				(Offset 0x0004) */
+
+#define BIT_DIS_HW_LPLDM BIT(20)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_SYS_PW_CTRL				(Offset 0x0004) */
+
+#define BIT_SOP_ALD BIT(20)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_SYS_PW_CTRL				(Offset 0x0004) */
+
+#define BIT_OPT_SWRST_WLMCU BIT(19)
+#define BIT_RDY_SYSPWR BIT(17)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8881A_SUPPORT)
+
+/* 2 REG_SYS_PW_CTRL				(Offset 0x0004) */
+
+#define BIT_EN_WLON BIT(16)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_SYS_PW_CTRL				(Offset 0x0004) */
+
+#define BIT_APDM_HPDN BIT(15)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_SYS_PW_CTRL				(Offset 0x0004) */
+
+#define BIT_PMC_RATIO_BIT0 BIT(14)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_SYS_PW_CTRL				(Offset 0x0004) */
+
+#define BIT_HSUS BIT(14)
+#define BIT_PDN_SEL BIT(13)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8881A_SUPPORT)
+
+/* 2 REG_SYS_PW_CTRL				(Offset 0x0004) */
+
+#define BIT_AFSM_PCIE_SUS_EN BIT(12)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_SYS_PW_CTRL				(Offset 0x0004) */
+
+#define BIT_AFSM_WLSUS_EN BIT(11)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8881A_SUPPORT)
+
+/* 2 REG_SYS_PW_CTRL				(Offset 0x0004) */
+
+#define BIT_APFM_SWLPS BIT(10)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_SYS_PW_CTRL				(Offset 0x0004) */
+
+#define BIT_APFM_SWLPS_EN BIT(10)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_SYS_PW_CTRL				(Offset 0x0004) */
+
+#define BIT_APFM_OFFMAC BIT(9)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_SYS_PW_CTRL				(Offset 0x0004) */
+
+#define BIT_HW_AUTO_CTRL_EXT_SWR BIT(9)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_SYS_PW_CTRL				(Offset 0x0004) */
+
+#define BIT_APFN_ONMAC BIT(8)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_SYS_PW_CTRL				(Offset 0x0004) */
+
+#define BIT_USE_INTERNAL_SWR_AND_LDO BIT(8)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8881A_SUPPORT)
+
+/* 2 REG_SYS_PW_CTRL				(Offset 0x0004) */
+
+#define BIT_CHIP_PDN_EN BIT(7)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_SYS_PW_CTRL				(Offset 0x0004) */
+
+#define BIT_BT_SUSEN BIT(7)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_SYS_PW_CTRL				(Offset 0x0004) */
+
+#define BIT_RDY_MACDIS BIT(6)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_SYS_PW_CTRL				(Offset 0x0004) */
+
+#define BIT_PD_RF BIT(5)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8881A_SUPPORT)
+
+/* 2 REG_SYS_PW_CTRL				(Offset 0x0004) */
+
+#define BIT_RING_CLK_12M_EN BIT(4)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_SDIO_CMD11_VOL_SWITCH		(Offset 0x10250004) */
+
+#define BIT_SHIFT_CMD11_SEQ_END_DELAY 4
+#define BIT_MASK_CMD11_SEQ_END_DELAY 0xf
+#define BIT_CMD11_SEQ_END_DELAY(x)                                             \
+	(((x) & BIT_MASK_CMD11_SEQ_END_DELAY) << BIT_SHIFT_CMD11_SEQ_END_DELAY)
+#define BITS_CMD11_SEQ_END_DELAY                                               \
+	(BIT_MASK_CMD11_SEQ_END_DELAY << BIT_SHIFT_CMD11_SEQ_END_DELAY)
+#define BIT_CLEAR_CMD11_SEQ_END_DELAY(x) ((x) & (~BITS_CMD11_SEQ_END_DELAY))
+#define BIT_GET_CMD11_SEQ_END_DELAY(x)                                         \
+	(((x) >> BIT_SHIFT_CMD11_SEQ_END_DELAY) & BIT_MASK_CMD11_SEQ_END_DELAY)
+#define BIT_SET_CMD11_SEQ_END_DELAY(x, v)                                      \
+	(BIT_CLEAR_CMD11_SEQ_END_DELAY(x) | BIT_CMD11_SEQ_END_DELAY(v))
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_SYS_PW_CTRL				(Offset 0x0004) */
+
+#define BIT_ENPDN BIT(4)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8881A_SUPPORT)
+
+/* 2 REG_SYS_PW_CTRL				(Offset 0x0004) */
+
+#define BIT_PFM_WOWL BIT(3)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_SYS_PW_CTRL				(Offset 0x0004) */
+
+#define BIT_SW_WAKE BIT(3)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_SYS_PW_CTRL				(Offset 0x0004) */
+
+#define BIT_PFM_LDKP BIT(2)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8881A_SUPPORT)
+
+/* 2 REG_SYS_PW_CTRL				(Offset 0x0004) */
+
+#define BIT_WL_HCI_ALD BIT(1)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_SYS_PW_CTRL				(Offset 0x0004) */
+
+#define BIT_ANA_CLK_DIVISION_2 BIT(1)
+
+#define BIT_SHIFT_CMD11_SEQ_SAMPLE_INTERVAL 1
+#define BIT_MASK_CMD11_SEQ_SAMPLE_INTERVAL 0x7
+#define BIT_CMD11_SEQ_SAMPLE_INTERVAL(x)                                       \
+	(((x) & BIT_MASK_CMD11_SEQ_SAMPLE_INTERVAL)                            \
+	 << BIT_SHIFT_CMD11_SEQ_SAMPLE_INTERVAL)
+#define BITS_CMD11_SEQ_SAMPLE_INTERVAL                                         \
+	(BIT_MASK_CMD11_SEQ_SAMPLE_INTERVAL                                    \
+	 << BIT_SHIFT_CMD11_SEQ_SAMPLE_INTERVAL)
+#define BIT_CLEAR_CMD11_SEQ_SAMPLE_INTERVAL(x)                                 \
+	((x) & (~BITS_CMD11_SEQ_SAMPLE_INTERVAL))
+#define BIT_GET_CMD11_SEQ_SAMPLE_INTERVAL(x)                                   \
+	(((x) >> BIT_SHIFT_CMD11_SEQ_SAMPLE_INTERVAL) &                        \
+	 BIT_MASK_CMD11_SEQ_SAMPLE_INTERVAL)
+#define BIT_SET_CMD11_SEQ_SAMPLE_INTERVAL(x, v)                                \
+	(BIT_CLEAR_CMD11_SEQ_SAMPLE_INTERVAL(x) |                              \
+	 BIT_CMD11_SEQ_SAMPLE_INTERVAL(v))
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_SYS_PW_CTRL				(Offset 0x0004) */
+
+#define BIT_PFM_ALDN BIT(1)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_SYS_PW_CTRL				(Offset 0x0004) */
+
+#define BIT_PFM_LDALL BIT(0)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_SDIO_CMD11_VOL_SWITCH		(Offset 0x10250004) */
+
+#define BIT_CMD11_SEQ_EN BIT(0)
+
+/* 2 REG_SDIO_CTRL				(Offset 0x10250005) */
+
+#define BIT_SIG_OUT_PH BIT(0)
+
+/* 2 REG_SDIO_DRIVING			(Offset 0x10250006) */
+
+#define BIT_SHIFT_SDIO_DRV_TYPE_D 12
+#define BIT_MASK_SDIO_DRV_TYPE_D 0xf
+#define BIT_SDIO_DRV_TYPE_D(x)                                                 \
+	(((x) & BIT_MASK_SDIO_DRV_TYPE_D) << BIT_SHIFT_SDIO_DRV_TYPE_D)
+#define BITS_SDIO_DRV_TYPE_D                                                   \
+	(BIT_MASK_SDIO_DRV_TYPE_D << BIT_SHIFT_SDIO_DRV_TYPE_D)
+#define BIT_CLEAR_SDIO_DRV_TYPE_D(x) ((x) & (~BITS_SDIO_DRV_TYPE_D))
+#define BIT_GET_SDIO_DRV_TYPE_D(x)                                             \
+	(((x) >> BIT_SHIFT_SDIO_DRV_TYPE_D) & BIT_MASK_SDIO_DRV_TYPE_D)
+#define BIT_SET_SDIO_DRV_TYPE_D(x, v)                                          \
+	(BIT_CLEAR_SDIO_DRV_TYPE_D(x) | BIT_SDIO_DRV_TYPE_D(v))
+
+#define BIT_SHIFT_SDIO_DRV_TYPE_C 8
+#define BIT_MASK_SDIO_DRV_TYPE_C 0xf
+#define BIT_SDIO_DRV_TYPE_C(x)                                                 \
+	(((x) & BIT_MASK_SDIO_DRV_TYPE_C) << BIT_SHIFT_SDIO_DRV_TYPE_C)
+#define BITS_SDIO_DRV_TYPE_C                                                   \
+	(BIT_MASK_SDIO_DRV_TYPE_C << BIT_SHIFT_SDIO_DRV_TYPE_C)
+#define BIT_CLEAR_SDIO_DRV_TYPE_C(x) ((x) & (~BITS_SDIO_DRV_TYPE_C))
+#define BIT_GET_SDIO_DRV_TYPE_C(x)                                             \
+	(((x) >> BIT_SHIFT_SDIO_DRV_TYPE_C) & BIT_MASK_SDIO_DRV_TYPE_C)
+#define BIT_SET_SDIO_DRV_TYPE_C(x, v)                                          \
+	(BIT_CLEAR_SDIO_DRV_TYPE_C(x) | BIT_SDIO_DRV_TYPE_C(v))
+
+#define BIT_SHIFT_SDIO_DRV_TYPE_B 4
+#define BIT_MASK_SDIO_DRV_TYPE_B 0xf
+#define BIT_SDIO_DRV_TYPE_B(x)                                                 \
+	(((x) & BIT_MASK_SDIO_DRV_TYPE_B) << BIT_SHIFT_SDIO_DRV_TYPE_B)
+#define BITS_SDIO_DRV_TYPE_B                                                   \
+	(BIT_MASK_SDIO_DRV_TYPE_B << BIT_SHIFT_SDIO_DRV_TYPE_B)
+#define BIT_CLEAR_SDIO_DRV_TYPE_B(x) ((x) & (~BITS_SDIO_DRV_TYPE_B))
+#define BIT_GET_SDIO_DRV_TYPE_B(x)                                             \
+	(((x) >> BIT_SHIFT_SDIO_DRV_TYPE_B) & BIT_MASK_SDIO_DRV_TYPE_B)
+#define BIT_SET_SDIO_DRV_TYPE_B(x, v)                                          \
+	(BIT_CLEAR_SDIO_DRV_TYPE_B(x) | BIT_SDIO_DRV_TYPE_B(v))
+
+#define BIT_SHIFT_SDIO_DRV_TYPE_A 0
+#define BIT_MASK_SDIO_DRV_TYPE_A 0xf
+#define BIT_SDIO_DRV_TYPE_A(x)                                                 \
+	(((x) & BIT_MASK_SDIO_DRV_TYPE_A) << BIT_SHIFT_SDIO_DRV_TYPE_A)
+#define BITS_SDIO_DRV_TYPE_A                                                   \
+	(BIT_MASK_SDIO_DRV_TYPE_A << BIT_SHIFT_SDIO_DRV_TYPE_A)
+#define BIT_CLEAR_SDIO_DRV_TYPE_A(x) ((x) & (~BITS_SDIO_DRV_TYPE_A))
+#define BIT_GET_SDIO_DRV_TYPE_A(x)                                             \
+	(((x) >> BIT_SHIFT_SDIO_DRV_TYPE_A) & BIT_MASK_SDIO_DRV_TYPE_A)
+#define BIT_SET_SDIO_DRV_TYPE_A(x, v)                                          \
+	(BIT_CLEAR_SDIO_DRV_TYPE_A(x) | BIT_SDIO_DRV_TYPE_A(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_SYS_CLK_CTRL			(Offset 0x0008) */
+
+#define BIT_CPHY_LDO_CL_EN BIT(19)
+#define BIT_CPHY_LDO_OK BIT(18)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8881A_SUPPORT)
+
+/* 2 REG_SYS_CLK_CTRL			(Offset 0x0008) */
+
+#define BIT_LDO_DUMMY BIT(15)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_SYS_CLK_CTRL			(Offset 0x0008) */
+
+#define BIT_ANA_CLK_EN BIT(15)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_SYS_CLK_CTRL			(Offset 0x0008) */
+
+#define BIT_DATA_CPU_CLK_EN BIT(15)
+#define BIT_DATA_CPU_PWC BIT(15)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_SYS_CLK_CTRL			(Offset 0x0008) */
+
+#define BIT_CPU_CLK_EN BIT(14)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8881A_SUPPORT)
+
+/* 2 REG_SYS_CLK_CTRL			(Offset 0x0008) */
+
+#define BIT_SYMREG_CLK_EN BIT(13)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_SYS_CLK_CTRL			(Offset 0x0008) */
+
+#define BIT_RING_CLK_EN BIT(13)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8881A_SUPPORT)
+
+/* 2 REG_SYS_CLK_CTRL			(Offset 0x0008) */
+
+#define BIT_HCI_CLK_EN BIT(12)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_SYS_CLK_CTRL			(Offset 0x0008) */
+
+#define BIT_SYS_CLK_EN BIT(12)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_SYS_CLK_CTRL			(Offset 0x0008) */
+
+#define BIT_MAC_CLK_EN BIT(11)
+#define BIT_SEC_CLK_EN BIT(10)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_SYS_CLK_CTRL			(Offset 0x0008) */
+
+#define BIT_CTRL_SPS_PWM_FREQ BIT(10)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8881A_SUPPORT)
+
+/* 2 REG_SYS_CLK_CTRL			(Offset 0x0008) */
+
+#define BIT_PHY_SSC_RSTB BIT(9)
+#define BIT_EXT_32K_EN BIT(8)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_SYS_CLK_CTRL			(Offset 0x0008) */
+
+#define BIT_EXT32K_EN BIT(8)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_SYS_CLK_CTRL			(Offset 0x0008) */
+
+#define BIT_DISABLE_OPEN_SPS_LDO BIT(8)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8881A_SUPPORT)
+
+/* 2 REG_SYS_CLK_CTRL			(Offset 0x0008) */
+
+#define BIT_WL_CLK_TEST BIT(7)
+#define BIT_OP_SPS_PWM_EN BIT(6)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_SYS_CLK_CTRL			(Offset 0x0008) */
+
+#define BIT_SHIFT_MAC_CLK_SEL_V1 6
+#define BIT_MASK_MAC_CLK_SEL_V1 0x3
+#define BIT_MAC_CLK_SEL_V1(x)                                                  \
+	(((x) & BIT_MASK_MAC_CLK_SEL_V1) << BIT_SHIFT_MAC_CLK_SEL_V1)
+#define BITS_MAC_CLK_SEL_V1                                                    \
+	(BIT_MASK_MAC_CLK_SEL_V1 << BIT_SHIFT_MAC_CLK_SEL_V1)
+#define BIT_CLEAR_MAC_CLK_SEL_V1(x) ((x) & (~BITS_MAC_CLK_SEL_V1))
+#define BIT_GET_MAC_CLK_SEL_V1(x)                                              \
+	(((x) >> BIT_SHIFT_MAC_CLK_SEL_V1) & BIT_MASK_MAC_CLK_SEL_V1)
+#define BIT_SET_MAC_CLK_SEL_V1(x, v)                                           \
+	(BIT_CLEAR_MAC_CLK_SEL_V1(x) | BIT_MAC_CLK_SEL_V1(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_SYS_CLK_CTRL			(Offset 0x0008) */
+
+#define BIT_LOADER_CLK_EN BIT(5)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_SYS_CLK_CTRL			(Offset 0x0008) */
+
+#define BIT_POW_PC_LDO3 BIT(5)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_SYS_CLK_CTRL			(Offset 0x0008) */
+
+#define BIT_MACSLP BIT(4)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_SYS_CLK_CTRL			(Offset 0x0008) */
+
+#define BIT_POW_PC_LDO2 BIT(4)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_SYS_CLK_CTRL			(Offset 0x0008) */
+
+#define BIT_WAKEPAD_EN BIT(3)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_SYS_CLK_CTRL			(Offset 0x0008) */
+
+#define BIT_ENB_LDO_DIODE_L BIT(3)
+#define BIT_POW_PC_LDO1 BIT(3)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_SYS_CLK_CTRL			(Offset 0x0008) */
+
+#define BIT_ROMD16V_EN BIT(2)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_SYS_CLK_CTRL			(Offset 0x0008) */
+
+#define BIT_AFE_BGEN_PCIE_OP BIT(2)
+#define BIT_POW_PC_LDO0 BIT(2)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_SYS_CLK_CTRL			(Offset 0x0008) */
+
+#define BIT_CKANA8M_EN BIT(1)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+
+/* 2 REG_SYS_CLK_CTRL			(Offset 0x0008) */
+
+#define BIT_CKANA12M_EN BIT(1)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_SYS_CLK_CTRL			(Offset 0x0008) */
+
+#define BIT_ANA8M_EN BIT(1)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_SYS_CLK_CTRL			(Offset 0x0008) */
+
+#define BIT_CNTD16V_EN BIT(0)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_SDIO_MONITOR			(Offset 0x10250008) */
+
+#define BIT_SHIFT_SDIO_INT_START 0
+#define BIT_MASK_SDIO_INT_START 0xffffffffL
+#define BIT_SDIO_INT_START(x)                                                  \
+	(((x) & BIT_MASK_SDIO_INT_START) << BIT_SHIFT_SDIO_INT_START)
+#define BITS_SDIO_INT_START                                                    \
+	(BIT_MASK_SDIO_INT_START << BIT_SHIFT_SDIO_INT_START)
+#define BIT_CLEAR_SDIO_INT_START(x) ((x) & (~BITS_SDIO_INT_START))
+#define BIT_GET_SDIO_INT_START(x)                                              \
+	(((x) >> BIT_SHIFT_SDIO_INT_START) & BIT_MASK_SDIO_INT_START)
+#define BIT_SET_SDIO_INT_START(x, v)                                           \
+	(BIT_CLEAR_SDIO_INT_START(x) | BIT_SDIO_INT_START(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_SYS_CLK_CTRL			(Offset 0x0008) */
+
+#define BIT_POW_POWER_CUT BIT(0)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_SYS_EEPROM_CTRL			(Offset 0x000A) */
+
+#define BIT_SHIFT_VPDIDX 8
+#define BIT_MASK_VPDIDX 0xff
+#define BIT_VPDIDX(x) (((x) & BIT_MASK_VPDIDX) << BIT_SHIFT_VPDIDX)
+#define BITS_VPDIDX (BIT_MASK_VPDIDX << BIT_SHIFT_VPDIDX)
+#define BIT_CLEAR_VPDIDX(x) ((x) & (~BITS_VPDIDX))
+#define BIT_GET_VPDIDX(x) (((x) >> BIT_SHIFT_VPDIDX) & BIT_MASK_VPDIDX)
+#define BIT_SET_VPDIDX(x, v) (BIT_CLEAR_VPDIDX(x) | BIT_VPDIDX(v))
+
+#define BIT_SHIFT_EEM1_0 6
+#define BIT_MASK_EEM1_0 0x3
+#define BIT_EEM1_0(x) (((x) & BIT_MASK_EEM1_0) << BIT_SHIFT_EEM1_0)
+#define BITS_EEM1_0 (BIT_MASK_EEM1_0 << BIT_SHIFT_EEM1_0)
+#define BIT_CLEAR_EEM1_0(x) ((x) & (~BITS_EEM1_0))
+#define BIT_GET_EEM1_0(x) (((x) >> BIT_SHIFT_EEM1_0) & BIT_MASK_EEM1_0)
+#define BIT_SET_EEM1_0(x, v) (BIT_CLEAR_EEM1_0(x) | BIT_EEM1_0(v))
+
+#define BIT_AUTOLOAD_SUS BIT(5)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8881A_SUPPORT)
+
+/* 2 REG_SYS_EEPROM_CTRL			(Offset 0x000A) */
+
+#define BIT_EERPOMSEL BIT(4)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_SYS_EEPROM_CTRL			(Offset 0x000A) */
+
+#define BIT_EEPROMSEL BIT(4)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_SYS_EEPROM_CTRL			(Offset 0x000A) */
+
+#define BIT_EECS_V1 BIT(3)
+#define BIT_EESK_V1 BIT(2)
+#define BIT_EEDI_V1 BIT(1)
+#define BIT_EEDO_V1 BIT(0)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_SDIO_MONITOR_2			(Offset 0x1025000C) */
+
+#define BIT_CMD53_WT_EN BIT(23)
+
+#define BIT_SHIFT_SDIO_CLK_MONITOR 21
+#define BIT_MASK_SDIO_CLK_MONITOR 0x3
+#define BIT_SDIO_CLK_MONITOR(x)                                                \
+	(((x) & BIT_MASK_SDIO_CLK_MONITOR) << BIT_SHIFT_SDIO_CLK_MONITOR)
+#define BITS_SDIO_CLK_MONITOR                                                  \
+	(BIT_MASK_SDIO_CLK_MONITOR << BIT_SHIFT_SDIO_CLK_MONITOR)
+#define BIT_CLEAR_SDIO_CLK_MONITOR(x) ((x) & (~BITS_SDIO_CLK_MONITOR))
+#define BIT_GET_SDIO_CLK_MONITOR(x)                                            \
+	(((x) >> BIT_SHIFT_SDIO_CLK_MONITOR) & BIT_MASK_SDIO_CLK_MONITOR)
+#define BIT_SET_SDIO_CLK_MONITOR(x, v)                                         \
+	(BIT_CLEAR_SDIO_CLK_MONITOR(x) | BIT_SDIO_CLK_MONITOR(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8881A_SUPPORT)
+
+/* 2 REG_EE_VPD				(Offset 0x000C) */
+
+#define BIT_SHIFT_VPD_DATA 0
+#define BIT_MASK_VPD_DATA 0xffffffffL
+#define BIT_VPD_DATA(x) (((x) & BIT_MASK_VPD_DATA) << BIT_SHIFT_VPD_DATA)
+#define BITS_VPD_DATA (BIT_MASK_VPD_DATA << BIT_SHIFT_VPD_DATA)
+#define BIT_CLEAR_VPD_DATA(x) ((x) & (~BITS_VPD_DATA))
+#define BIT_GET_VPD_DATA(x) (((x) >> BIT_SHIFT_VPD_DATA) & BIT_MASK_VPD_DATA)
+#define BIT_SET_VPD_DATA(x, v) (BIT_CLEAR_VPD_DATA(x) | BIT_VPD_DATA(v))
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_SDIO_MONITOR_2			(Offset 0x1025000C) */
+
+#define BIT_SHIFT_SDIO_CLK_CNT 0
+#define BIT_MASK_SDIO_CLK_CNT 0x1fffff
+#define BIT_SDIO_CLK_CNT(x)                                                    \
+	(((x) & BIT_MASK_SDIO_CLK_CNT) << BIT_SHIFT_SDIO_CLK_CNT)
+#define BITS_SDIO_CLK_CNT (BIT_MASK_SDIO_CLK_CNT << BIT_SHIFT_SDIO_CLK_CNT)
+#define BIT_CLEAR_SDIO_CLK_CNT(x) ((x) & (~BITS_SDIO_CLK_CNT))
+#define BIT_GET_SDIO_CLK_CNT(x)                                                \
+	(((x) >> BIT_SHIFT_SDIO_CLK_CNT) & BIT_MASK_SDIO_CLK_CNT)
+#define BIT_SET_SDIO_CLK_CNT(x, v)                                             \
+	(BIT_CLEAR_SDIO_CLK_CNT(x) | BIT_SDIO_CLK_CNT(v))
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_EE_VPD				(Offset 0x000C) */
+
+#define BIT_SHIFT_VDP_DATA 0
+#define BIT_MASK_VDP_DATA 0xffffffffL
+#define BIT_VDP_DATA(x) (((x) & BIT_MASK_VDP_DATA) << BIT_SHIFT_VDP_DATA)
+#define BITS_VDP_DATA (BIT_MASK_VDP_DATA << BIT_SHIFT_VDP_DATA)
+#define BIT_CLEAR_VDP_DATA(x) ((x) & (~BITS_VDP_DATA))
+#define BIT_GET_VDP_DATA(x) (((x) >> BIT_SHIFT_VDP_DATA) & BIT_MASK_VDP_DATA)
+#define BIT_SET_VDP_DATA(x, v) (BIT_CLEAR_VDP_DATA(x) | BIT_VDP_DATA(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_SYS_SWR_CTRL1			(Offset 0x0010) */
+
+#define BIT_SW18_C2_BIT0 BIT(31)
+
+#endif
+
+#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+
+/* 2 REG_SYS_SWR_CTRL1			(Offset 0x0010) */
+
+#define BIT_C2_L_BIT0 BIT(31)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_SYS_SWR_CTRL1			(Offset 0x0010) */
+
+#define BIT_SHIFT_R1_L1_V1 30
+#define BIT_MASK_R1_L1_V1 0x3
+#define BIT_R1_L1_V1(x) (((x) & BIT_MASK_R1_L1_V1) << BIT_SHIFT_R1_L1_V1)
+#define BITS_R1_L1_V1 (BIT_MASK_R1_L1_V1 << BIT_SHIFT_R1_L1_V1)
+#define BIT_CLEAR_R1_L1_V1(x) ((x) & (~BITS_R1_L1_V1))
+#define BIT_GET_R1_L1_V1(x) (((x) >> BIT_SHIFT_R1_L1_V1) & BIT_MASK_R1_L1_V1)
+#define BIT_SET_R1_L1_V1(x, v) (BIT_CLEAR_R1_L1_V1(x) | BIT_R1_L1_V1(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_SYS_SWR_CTRL1			(Offset 0x0010) */
+
+#define BIT_SHIFT_SW18_C1 29
+#define BIT_MASK_SW18_C1 0x3
+#define BIT_SW18_C1(x) (((x) & BIT_MASK_SW18_C1) << BIT_SHIFT_SW18_C1)
+#define BITS_SW18_C1 (BIT_MASK_SW18_C1 << BIT_SHIFT_SW18_C1)
+#define BIT_CLEAR_SW18_C1(x) ((x) & (~BITS_SW18_C1))
+#define BIT_GET_SW18_C1(x) (((x) >> BIT_SHIFT_SW18_C1) & BIT_MASK_SW18_C1)
+#define BIT_SET_SW18_C1(x, v) (BIT_CLEAR_SW18_C1(x) | BIT_SW18_C1(v))
+
+#endif
+
+#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+
+/* 2 REG_SYS_SWR_CTRL1			(Offset 0x0010) */
+
+#define BIT_SHIFT_C1_L 29
+#define BIT_MASK_C1_L 0x3
+#define BIT_C1_L(x) (((x) & BIT_MASK_C1_L) << BIT_SHIFT_C1_L)
+#define BITS_C1_L (BIT_MASK_C1_L << BIT_SHIFT_C1_L)
+#define BIT_CLEAR_C1_L(x) ((x) & (~BITS_C1_L))
+#define BIT_GET_C1_L(x) (((x) >> BIT_SHIFT_C1_L) & BIT_MASK_C1_L)
+#define BIT_SET_C1_L(x, v) (BIT_CLEAR_C1_L(x) | BIT_C1_L(v))
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_SYS_SWR_CTRL1			(Offset 0x0010) */
+
+#define BIT_SHIFT_C3_L1_V1 28
+#define BIT_MASK_C3_L1_V1 0x3
+#define BIT_C3_L1_V1(x) (((x) & BIT_MASK_C3_L1_V1) << BIT_SHIFT_C3_L1_V1)
+#define BITS_C3_L1_V1 (BIT_MASK_C3_L1_V1 << BIT_SHIFT_C3_L1_V1)
+#define BIT_CLEAR_C3_L1_V1(x) ((x) & (~BITS_C3_L1_V1))
+#define BIT_GET_C3_L1_V1(x) (((x) >> BIT_SHIFT_C3_L1_V1) & BIT_MASK_C3_L1_V1)
+#define BIT_SET_C3_L1_V1(x, v) (BIT_CLEAR_C3_L1_V1(x) | BIT_C3_L1_V1(v))
+
+#define BIT_SHIFT_C2_L1_V1 26
+#define BIT_MASK_C2_L1_V1 0x3
+#define BIT_C2_L1_V1(x) (((x) & BIT_MASK_C2_L1_V1) << BIT_SHIFT_C2_L1_V1)
+#define BITS_C2_L1_V1 (BIT_MASK_C2_L1_V1 << BIT_SHIFT_C2_L1_V1)
+#define BIT_CLEAR_C2_L1_V1(x) ((x) & (~BITS_C2_L1_V1))
+#define BIT_GET_C2_L1_V1(x) (((x) >> BIT_SHIFT_C2_L1_V1) & BIT_MASK_C2_L1_V1)
+#define BIT_SET_C2_L1_V1(x, v) (BIT_CLEAR_C2_L1_V1(x) | BIT_C2_L1_V1(v))
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+
+/* 2 REG_SYS_SWR_CTRL1			(Offset 0x0010) */
+
+#define BIT_SHIFT_REG_FREQ_L 25
+#define BIT_MASK_REG_FREQ_L 0x7
+#define BIT_REG_FREQ_L(x) (((x) & BIT_MASK_REG_FREQ_L) << BIT_SHIFT_REG_FREQ_L)
+#define BITS_REG_FREQ_L (BIT_MASK_REG_FREQ_L << BIT_SHIFT_REG_FREQ_L)
+#define BIT_CLEAR_REG_FREQ_L(x) ((x) & (~BITS_REG_FREQ_L))
+#define BIT_GET_REG_FREQ_L(x)                                                  \
+	(((x) >> BIT_SHIFT_REG_FREQ_L) & BIT_MASK_REG_FREQ_L)
+#define BIT_SET_REG_FREQ_L(x, v) (BIT_CLEAR_REG_FREQ_L(x) | BIT_REG_FREQ_L(v))
+
+#define BIT_REG_EN_DUTY BIT(24)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_SYS_SWR_CTRL1			(Offset 0x0010) */
+
+#define BIT_SHIFT_C1_L1_V1 24
+#define BIT_MASK_C1_L1_V1 0x3
+#define BIT_C1_L1_V1(x) (((x) & BIT_MASK_C1_L1_V1) << BIT_SHIFT_C1_L1_V1)
+#define BITS_C1_L1_V1 (BIT_MASK_C1_L1_V1 << BIT_SHIFT_C1_L1_V1)
+#define BIT_CLEAR_C1_L1_V1(x) ((x) & (~BITS_C1_L1_V1))
+#define BIT_GET_C1_L1_V1(x) (((x) >> BIT_SHIFT_C1_L1_V1) & BIT_MASK_C1_L1_V1)
+#define BIT_SET_C1_L1_V1(x, v) (BIT_CLEAR_C1_L1_V1(x) | BIT_C1_L1_V1(v))
+
+#define BIT_REG_TYPE_L_V3 BIT(23)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+
+/* 2 REG_SYS_SWR_CTRL1			(Offset 0x0010) */
+
+#define BIT_SHIFT_REG_MODE 22
+#define BIT_MASK_REG_MODE 0x3
+#define BIT_REG_MODE(x) (((x) & BIT_MASK_REG_MODE) << BIT_SHIFT_REG_MODE)
+#define BITS_REG_MODE (BIT_MASK_REG_MODE << BIT_SHIFT_REG_MODE)
+#define BIT_CLEAR_REG_MODE(x) ((x) & (~BITS_REG_MODE))
+#define BIT_GET_REG_MODE(x) (((x) >> BIT_SHIFT_REG_MODE) & BIT_MASK_REG_MODE)
+#define BIT_SET_REG_MODE(x, v) (BIT_CLEAR_REG_MODE(x) | BIT_REG_MODE(v))
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_SYS_SWR_CTRL1			(Offset 0x0010) */
+
+#define BIT_FPWM_L1_V1 BIT(22)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+
+/* 2 REG_SYS_SWR_CTRL1			(Offset 0x0010) */
+
+#define BIT_REG_EN_SP BIT(21)
+#define BIT_REG_AUTO_L BIT(20)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8881A_SUPPORT)
+
+/* 2 REG_SYS_SWR_CTRL1			(Offset 0x0010) */
+
+#define BIT_SW18_SELD_BIT0 BIT(19)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_SYS_SWR_CTRL1			(Offset 0x0010) */
+
+#define BIT_SHIFT_V15ADJ_L1 19
+#define BIT_MASK_V15ADJ_L1 0x7
+#define BIT_V15ADJ_L1(x) (((x) & BIT_MASK_V15ADJ_L1) << BIT_SHIFT_V15ADJ_L1)
+#define BITS_V15ADJ_L1 (BIT_MASK_V15ADJ_L1 << BIT_SHIFT_V15ADJ_L1)
+#define BIT_CLEAR_V15ADJ_L1(x) ((x) & (~BITS_V15ADJ_L1))
+#define BIT_GET_V15ADJ_L1(x) (((x) >> BIT_SHIFT_V15ADJ_L1) & BIT_MASK_V15ADJ_L1)
+#define BIT_SET_V15ADJ_L1(x, v) (BIT_CLEAR_V15ADJ_L1(x) | BIT_V15ADJ_L1(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8881A_SUPPORT)
+
+/* 2 REG_SYS_SWR_CTRL1			(Offset 0x0010) */
+
+#define BIT_SW18_POWOCP BIT(18)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_SYS_SWR_CTRL1			(Offset 0x0010) */
+
+#define BIT_SHIFT_IN_L1 16
+#define BIT_MASK_IN_L1 0x7
+#define BIT_IN_L1(x) (((x) & BIT_MASK_IN_L1) << BIT_SHIFT_IN_L1)
+#define BITS_IN_L1 (BIT_MASK_IN_L1 << BIT_SHIFT_IN_L1)
+#define BIT_CLEAR_IN_L1(x) ((x) & (~BITS_IN_L1))
+#define BIT_GET_IN_L1(x) (((x) >> BIT_SHIFT_IN_L1) & BIT_MASK_IN_L1)
+#define BIT_SET_IN_L1(x, v) (BIT_CLEAR_IN_L1(x) | BIT_IN_L1(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_SYS_SWR_CTRL1			(Offset 0x0010) */
+
+#define BIT_SHIFT_SW18_OCP 15
+#define BIT_MASK_SW18_OCP 0x7
+#define BIT_SW18_OCP(x) (((x) & BIT_MASK_SW18_OCP) << BIT_SHIFT_SW18_OCP)
+#define BITS_SW18_OCP (BIT_MASK_SW18_OCP << BIT_SHIFT_SW18_OCP)
+#define BIT_CLEAR_SW18_OCP(x) ((x) & (~BITS_SW18_OCP))
+#define BIT_GET_SW18_OCP(x) (((x) >> BIT_SHIFT_SW18_OCP) & BIT_MASK_SW18_OCP)
+#define BIT_SET_SW18_OCP(x, v) (BIT_CLEAR_SW18_OCP(x) | BIT_SW18_OCP(v))
+
+#endif
+
+#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+
+/* 2 REG_SYS_SWR_CTRL1			(Offset 0x0010) */
+
+#define BIT_SHIFT_OCP_L1 15
+#define BIT_MASK_OCP_L1 0x7
+#define BIT_OCP_L1(x) (((x) & BIT_MASK_OCP_L1) << BIT_SHIFT_OCP_L1)
+#define BITS_OCP_L1 (BIT_MASK_OCP_L1 << BIT_SHIFT_OCP_L1)
+#define BIT_CLEAR_OCP_L1(x) ((x) & (~BITS_OCP_L1))
+#define BIT_GET_OCP_L1(x) (((x) >> BIT_SHIFT_OCP_L1) & BIT_MASK_OCP_L1)
+#define BIT_SET_OCP_L1(x, v) (BIT_CLEAR_OCP_L1(x) | BIT_OCP_L1(v))
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_SYS_SWR_CTRL1			(Offset 0x0010) */
+
+#define BIT_SHIFT_STD_L1 14
+#define BIT_MASK_STD_L1 0x3
+#define BIT_STD_L1(x) (((x) & BIT_MASK_STD_L1) << BIT_SHIFT_STD_L1)
+#define BITS_STD_L1 (BIT_MASK_STD_L1 << BIT_SHIFT_STD_L1)
+#define BIT_CLEAR_STD_L1(x) ((x) & (~BITS_STD_L1))
+#define BIT_GET_STD_L1(x) (((x) >> BIT_SHIFT_STD_L1) & BIT_MASK_STD_L1)
+#define BIT_SET_STD_L1(x, v) (BIT_CLEAR_STD_L1(x) | BIT_STD_L1(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_SYS_SWR_CTRL1			(Offset 0x0010) */
+
+#define BIT_SHIFT_CF_L_BIT0_TO_1 13
+#define BIT_MASK_CF_L_BIT0_TO_1 0x3
+#define BIT_CF_L_BIT0_TO_1(x)                                                  \
+	(((x) & BIT_MASK_CF_L_BIT0_TO_1) << BIT_SHIFT_CF_L_BIT0_TO_1)
+#define BITS_CF_L_BIT0_TO_1                                                    \
+	(BIT_MASK_CF_L_BIT0_TO_1 << BIT_SHIFT_CF_L_BIT0_TO_1)
+#define BIT_CLEAR_CF_L_BIT0_TO_1(x) ((x) & (~BITS_CF_L_BIT0_TO_1))
+#define BIT_GET_CF_L_BIT0_TO_1(x)                                              \
+	(((x) >> BIT_SHIFT_CF_L_BIT0_TO_1) & BIT_MASK_CF_L_BIT0_TO_1)
+#define BIT_SET_CF_L_BIT0_TO_1(x, v)                                           \
+	(BIT_CLEAR_CF_L_BIT0_TO_1(x) | BIT_CF_L_BIT0_TO_1(v))
+
+#endif
+
+#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+
+/* 2 REG_SYS_SWR_CTRL1			(Offset 0x0010) */
+
+#define BIT_SHIFT_CF_L 13
+#define BIT_MASK_CF_L 0x3
+#define BIT_CF_L(x) (((x) & BIT_MASK_CF_L) << BIT_SHIFT_CF_L)
+#define BITS_CF_L (BIT_MASK_CF_L << BIT_SHIFT_CF_L)
+#define BIT_CLEAR_CF_L(x) ((x) & (~BITS_CF_L))
+#define BIT_GET_CF_L(x) (((x) >> BIT_SHIFT_CF_L) & BIT_MASK_CF_L)
+#define BIT_SET_CF_L(x, v) (BIT_CLEAR_CF_L(x) | BIT_CF_L(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_SYS_SWR_CTRL1			(Offset 0x0010) */
+
+#define BIT_SW18_FPWM BIT(11)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_SYS_SWR_CTRL1			(Offset 0x0010) */
+
+#define BIT_SPS_FPWM BIT(11)
+#define BIT_WL_CTRL_SPS_PWMFREQ BIT(10)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_SYS_SWR_CTRL1			(Offset 0x0010) */
+
+#define BIT_SHIFT_VOL_L1 10
+#define BIT_MASK_VOL_L1 0xf
+#define BIT_VOL_L1(x) (((x) & BIT_MASK_VOL_L1) << BIT_SHIFT_VOL_L1)
+#define BITS_VOL_L1 (BIT_MASK_VOL_L1 << BIT_SHIFT_VOL_L1)
+#define BIT_CLEAR_VOL_L1(x) ((x) & (~BITS_VOL_L1))
+#define BIT_GET_VOL_L1(x) (((x) >> BIT_SHIFT_VOL_L1) & BIT_MASK_VOL_L1)
+#define BIT_SET_VOL_L1(x, v) (BIT_CLEAR_VOL_L1(x) | BIT_VOL_L1(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_SYS_SWR_CTRL1			(Offset 0x0010) */
+
+#define BIT_SW18_SWEN BIT(9)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_SYS_SWR_CTRL1			(Offset 0x0010) */
+
+#define BIT_SPS_SWEN BIT(9)
+#define BIT_HALF_L BIT(9)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_SYS_SWR_CTRL1			(Offset 0x0010) */
+
+#define BIT_SW18_LDEN BIT(8)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_SYS_SWR_CTRL1			(Offset 0x0010) */
+
+#define BIT_SPS_LDEN BIT(8)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_SYS_SWR_CTRL1			(Offset 0x0010) */
+
+#define BIT_MAC_ID_EN BIT(7)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8814B_SUPPORT)
+
+/* 2 REG_SYS_SWR_CTRL1			(Offset 0x0010) */
+
+#define BIT_WL_CTRL_XTAL_CADJ BIT(6)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_SYS_SWR_CTRL1			(Offset 0x0010) */
+
+#define BIT_LDO11_EN BIT(6)
+#define BIT_AFE_P3_PC BIT(5)
+#define BIT_AFE_P2_PC BIT(4)
+#define BIT_AFE_P1_PC BIT(3)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_SYS_SWR_CTRL1			(Offset 0x0010) */
+
+#define BIT_AFE_MBEN_PCIE_OPT BIT(2)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_SYS_SWR_CTRL1			(Offset 0x0010) */
+
+#define BIT_AFE_P0_PC BIT(2)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_SYS_SWR_CTRL1			(Offset 0x0010) */
+
+#define BIT_AFE_MBEN BIT(1)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8881A_SUPPORT)
+
+/* 2 REG_SYS_SWR_CTRL1			(Offset 0x0010) */
+
+#define BIT_AFE_BGEN BIT(0)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_SYS_SWR_CTRL2			(Offset 0x0014) */
+
+#define BIT_POW_ZCD_L BIT(31)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_SDIO_HIMR				(Offset 0x10250014) */
+
+#define BIT_SDIO_CRCERR_MSK BIT(31)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_SDIO_HIMR				(Offset 0x10250014) */
+
+#define BIT_IO_READY_SIGNAL_ERR_MSK BIT(31)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_SYS_SWR_CTRL2			(Offset 0x0014) */
+
+#define BIT_ENABLE_ZCDOUT_L BIT(30)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+
+/* 2 REG_SYS_SWR_CTRL2			(Offset 0x0014) */
+
+#define BIT_AUTOZCD_L BIT(30)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_SDIO_HIMR				(Offset 0x10250014) */
+
+#define BIT_SDIO_HSISR3_IND_MSK BIT(30)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_SDIO_HIMR				(Offset 0x10250014) */
+
+#define BIT_SDIO_TX_CRC__MSK BIT(30)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_SDIO_HIMR				(Offset 0x10250014) */
+
+#define BIT_SDIO_HSISR2_IND_MSK BIT(29)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_SYS_SWR_CTRL2			(Offset 0x0014) */
+
+#define BIT_SHIFT_REG_DELAY 28
+#define BIT_MASK_REG_DELAY 0x3
+#define BIT_REG_DELAY(x) (((x) & BIT_MASK_REG_DELAY) << BIT_SHIFT_REG_DELAY)
+#define BITS_REG_DELAY (BIT_MASK_REG_DELAY << BIT_SHIFT_REG_DELAY)
+#define BIT_CLEAR_REG_DELAY(x) ((x) & (~BITS_REG_DELAY))
+#define BIT_GET_REG_DELAY(x) (((x) >> BIT_SHIFT_REG_DELAY) & BIT_MASK_REG_DELAY)
+#define BIT_SET_REG_DELAY(x, v) (BIT_CLEAR_REG_DELAY(x) | BIT_REG_DELAY(v))
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_SDIO_HIMR				(Offset 0x10250014) */
+
+#define BIT_SDIO_HEISR_IND_MSK BIT(28)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_SDIO_HIMR				(Offset 0x10250014) */
+
+#define BIT_SDIO_CTWEND_MSK BIT(27)
+#define BIT_SDIO_ATIMEND_E_MSK BIT(26)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_SDIO_HIMR				(Offset 0x10250014) */
+
+#define BIT_SDIIO_ATIMEND_MSK BIT(25)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_SDIO_HIMR				(Offset 0x10250014) */
+
+#define BIT_SDIO_ATIMEND_MSK BIT(25)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_SYS_SWR_CTRL2			(Offset 0x0014) */
+
+#define BIT_SHIFT_SW18_V15ADJ 24
+#define BIT_MASK_SW18_V15ADJ 0x7
+#define BIT_SW18_V15ADJ(x)                                                     \
+	(((x) & BIT_MASK_SW18_V15ADJ) << BIT_SHIFT_SW18_V15ADJ)
+#define BITS_SW18_V15ADJ (BIT_MASK_SW18_V15ADJ << BIT_SHIFT_SW18_V15ADJ)
+#define BIT_CLEAR_SW18_V15ADJ(x) ((x) & (~BITS_SW18_V15ADJ))
+#define BIT_GET_SW18_V15ADJ(x)                                                 \
+	(((x) >> BIT_SHIFT_SW18_V15ADJ) & BIT_MASK_SW18_V15ADJ)
+#define BIT_SET_SW18_V15ADJ(x, v)                                              \
+	(BIT_CLEAR_SW18_V15ADJ(x) | BIT_SW18_V15ADJ(v))
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+
+/* 2 REG_SYS_SWR_CTRL2			(Offset 0x0014) */
+
+#define BIT_SHIFT_V15ADJ_L1_V1 24
+#define BIT_MASK_V15ADJ_L1_V1 0x7
+#define BIT_V15ADJ_L1_V1(x)                                                    \
+	(((x) & BIT_MASK_V15ADJ_L1_V1) << BIT_SHIFT_V15ADJ_L1_V1)
+#define BITS_V15ADJ_L1_V1 (BIT_MASK_V15ADJ_L1_V1 << BIT_SHIFT_V15ADJ_L1_V1)
+#define BIT_CLEAR_V15ADJ_L1_V1(x) ((x) & (~BITS_V15ADJ_L1_V1))
+#define BIT_GET_V15ADJ_L1_V1(x)                                                \
+	(((x) >> BIT_SHIFT_V15ADJ_L1_V1) & BIT_MASK_V15ADJ_L1_V1)
+#define BIT_SET_V15ADJ_L1_V1(x, v)                                             \
+	(BIT_CLEAR_V15ADJ_L1_V1(x) | BIT_V15ADJ_L1_V1(v))
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_SDIO_HIMR				(Offset 0x10250014) */
+
+#define BIT_SDIO_OCPINT_MSK BIT(24)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_SYS_SWR_CTRL2			(Offset 0x0014) */
+
+#define BIT_OCPSL BIT(24)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_SDIO_HIMR				(Offset 0x10250014) */
+
+#define BIT_SDIO_PSTIMEOUT_MSK BIT(23)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_SYS_SWR_CTRL2			(Offset 0x0014) */
+
+#define BIT_REG_LDOF_L_V1 BIT(23)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_SDIO_HIMR				(Offset 0x10250014) */
+
+#define BIT_SDIO_GTINT4_MSK BIT(22)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_SYS_SWR_CTRL2			(Offset 0x0014) */
+
+#define BIT_PARSW_DUMMY BIT(22)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_SDIO_HIMR				(Offset 0x10250014) */
+
+#define BIT_SDIO_GTINT3_MSK BIT(21)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_SYS_SWR_CTRL2			(Offset 0x0014) */
+
+#define BIT_CLAMP_MAX_DUTY BIT(21)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_SYS_SWR_CTRL2			(Offset 0x0014) */
+
+#define BIT_SHIFT_SW18_VOL 20
+#define BIT_MASK_SW18_VOL 0xf
+#define BIT_SW18_VOL(x) (((x) & BIT_MASK_SW18_VOL) << BIT_SHIFT_SW18_VOL)
+#define BITS_SW18_VOL (BIT_MASK_SW18_VOL << BIT_SHIFT_SW18_VOL)
+#define BIT_CLEAR_SW18_VOL(x) ((x) & (~BITS_SW18_VOL))
+#define BIT_GET_SW18_VOL(x) (((x) >> BIT_SHIFT_SW18_VOL) & BIT_MASK_SW18_VOL)
+#define BIT_SET_SW18_VOL(x, v) (BIT_CLEAR_SW18_VOL(x) | BIT_SW18_VOL(v))
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+
+/* 2 REG_SYS_SWR_CTRL2			(Offset 0x0014) */
+
+#define BIT_SHIFT_VOL_L1_V1 20
+#define BIT_MASK_VOL_L1_V1 0xf
+#define BIT_VOL_L1_V1(x) (((x) & BIT_MASK_VOL_L1_V1) << BIT_SHIFT_VOL_L1_V1)
+#define BITS_VOL_L1_V1 (BIT_MASK_VOL_L1_V1 << BIT_SHIFT_VOL_L1_V1)
+#define BIT_CLEAR_VOL_L1_V1(x) ((x) & (~BITS_VOL_L1_V1))
+#define BIT_GET_VOL_L1_V1(x) (((x) >> BIT_SHIFT_VOL_L1_V1) & BIT_MASK_VOL_L1_V1)
+#define BIT_SET_VOL_L1_V1(x, v) (BIT_CLEAR_VOL_L1_V1(x) | BIT_VOL_L1_V1(v))
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_SDIO_HIMR				(Offset 0x10250014) */
+
+#define BIT_SDIO_HSISR_IND_MSK BIT(20)
+#define BIT_SDIO_CPWM2_MSK BIT(19)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_SYS_SWR_CTRL2			(Offset 0x0014) */
+
+#define BIT_SHIFT_TBOX_L1_V1 19
+#define BIT_MASK_TBOX_L1_V1 0x3
+#define BIT_TBOX_L1_V1(x) (((x) & BIT_MASK_TBOX_L1_V1) << BIT_SHIFT_TBOX_L1_V1)
+#define BITS_TBOX_L1_V1 (BIT_MASK_TBOX_L1_V1 << BIT_SHIFT_TBOX_L1_V1)
+#define BIT_CLEAR_TBOX_L1_V1(x) ((x) & (~BITS_TBOX_L1_V1))
+#define BIT_GET_TBOX_L1_V1(x)                                                  \
+	(((x) >> BIT_SHIFT_TBOX_L1_V1) & BIT_MASK_TBOX_L1_V1)
+#define BIT_SET_TBOX_L1_V1(x, v) (BIT_CLEAR_TBOX_L1_V1(x) | BIT_TBOX_L1_V1(v))
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_SDIO_HIMR				(Offset 0x10250014) */
+
+#define BIT_SDIO_CPWM1_MSK BIT(18)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_SYS_SWR_CTRL2			(Offset 0x0014) */
+
+#define BIT_SHIFT_SW18_IN 17
+#define BIT_MASK_SW18_IN 0x7
+#define BIT_SW18_IN(x) (((x) & BIT_MASK_SW18_IN) << BIT_SHIFT_SW18_IN)
+#define BITS_SW18_IN (BIT_MASK_SW18_IN << BIT_SHIFT_SW18_IN)
+#define BIT_CLEAR_SW18_IN(x) ((x) & (~BITS_SW18_IN))
+#define BIT_GET_SW18_IN(x) (((x) >> BIT_SHIFT_SW18_IN) & BIT_MASK_SW18_IN)
+#define BIT_SET_SW18_IN(x, v) (BIT_CLEAR_SW18_IN(x) | BIT_SW18_IN(v))
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+
+/* 2 REG_SYS_SWR_CTRL2			(Offset 0x0014) */
+
+#define BIT_SHIFT_IN_L1_V1 17
+#define BIT_MASK_IN_L1_V1 0x7
+#define BIT_IN_L1_V1(x) (((x) & BIT_MASK_IN_L1_V1) << BIT_SHIFT_IN_L1_V1)
+#define BITS_IN_L1_V1 (BIT_MASK_IN_L1_V1 << BIT_SHIFT_IN_L1_V1)
+#define BIT_CLEAR_IN_L1_V1(x) ((x) & (~BITS_IN_L1_V1))
+#define BIT_GET_IN_L1_V1(x) (((x) >> BIT_SHIFT_IN_L1_V1) & BIT_MASK_IN_L1_V1)
+#define BIT_SET_IN_L1_V1(x, v) (BIT_CLEAR_IN_L1_V1(x) | BIT_IN_L1_V1(v))
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_SDIO_HIMR				(Offset 0x10250014) */
+
+#define BIT_SDIO_C2HCMD_INT_MSK BIT(17)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_SYS_SWR_CTRL2			(Offset 0x0014) */
+
+#define BIT_SHIFT_REG_DELAY_V3 17
+#define BIT_MASK_REG_DELAY_V3 0x3
+#define BIT_REG_DELAY_V3(x)                                                    \
+	(((x) & BIT_MASK_REG_DELAY_V3) << BIT_SHIFT_REG_DELAY_V3)
+#define BITS_REG_DELAY_V3 (BIT_MASK_REG_DELAY_V3 << BIT_SHIFT_REG_DELAY_V3)
+#define BIT_CLEAR_REG_DELAY_V3(x) ((x) & (~BITS_REG_DELAY_V3))
+#define BIT_GET_REG_DELAY_V3(x)                                                \
+	(((x) >> BIT_SHIFT_REG_DELAY_V3) & BIT_MASK_REG_DELAY_V3)
+#define BIT_SET_REG_DELAY_V3(x, v)                                             \
+	(BIT_CLEAR_REG_DELAY_V3(x) | BIT_REG_DELAY_V3(v))
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_SDIO_HIMR				(Offset 0x10250014) */
+
+#define BIT_SDIO_BCNERLY_INT_MSK BIT(16)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_SYS_SWR_CTRL2			(Offset 0x0014) */
+
+#define BIT_REG_CLAMP_D_L_V2 BIT(16)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_SYS_SWR_CTRL2			(Offset 0x0014) */
+
+#define BIT_SHIFT_SW18_TBOX 15
+#define BIT_MASK_SW18_TBOX 0x3
+#define BIT_SW18_TBOX(x) (((x) & BIT_MASK_SW18_TBOX) << BIT_SHIFT_SW18_TBOX)
+#define BITS_SW18_TBOX (BIT_MASK_SW18_TBOX << BIT_SHIFT_SW18_TBOX)
+#define BIT_CLEAR_SW18_TBOX(x) ((x) & (~BITS_SW18_TBOX))
+#define BIT_GET_SW18_TBOX(x) (((x) >> BIT_SHIFT_SW18_TBOX) & BIT_MASK_SW18_TBOX)
+#define BIT_SET_SW18_TBOX(x, v) (BIT_CLEAR_SW18_TBOX(x) | BIT_SW18_TBOX(v))
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_SYS_SWR_CTRL2			(Offset 0x0014) */
+
+#define BIT_REG_BYPASS_L_V3 BIT(15)
+
+#endif
+
+#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+
+/* 2 REG_SYS_SWR_CTRL2			(Offset 0x0014) */
+
+#define BIT_SHIFT_TBOX_L1 15
+#define BIT_MASK_TBOX_L1 0x3
+#define BIT_TBOX_L1(x) (((x) & BIT_MASK_TBOX_L1) << BIT_SHIFT_TBOX_L1)
+#define BITS_TBOX_L1 (BIT_MASK_TBOX_L1 << BIT_SHIFT_TBOX_L1)
+#define BIT_CLEAR_TBOX_L1(x) ((x) & (~BITS_TBOX_L1))
+#define BIT_GET_TBOX_L1(x) (((x) >> BIT_SHIFT_TBOX_L1) & BIT_MASK_TBOX_L1)
+#define BIT_SET_TBOX_L1(x, v) (BIT_CLEAR_TBOX_L1(x) | BIT_TBOX_L1(v))
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_SYS_SWR_CTRL2			(Offset 0x0014) */
+
+#define BIT_ENABLE_ZCDOUT_L_V3 BIT(14)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8881A_SUPPORT)
+
+/* 2 REG_SYS_SWR_CTRL2			(Offset 0x0014) */
+
+#define BIT_SW18_SEL BIT(13)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_SYS_SWR_CTRL2			(Offset 0x0014) */
+
+#define BIT_POW_ZCD_L_V3 BIT(13)
+#define BIT_AREN_L1_V1 BIT(12)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_SYS_SWR_CTRL2			(Offset 0x0014) */
+
+#define BIT_SHIFT_SW18_STD 11
+#define BIT_MASK_SW18_STD 0x3
+#define BIT_SW18_STD(x) (((x) & BIT_MASK_SW18_STD) << BIT_SHIFT_SW18_STD)
+#define BITS_SW18_STD (BIT_MASK_SW18_STD << BIT_SHIFT_SW18_STD)
+#define BIT_CLEAR_SW18_STD(x) ((x) & (~BITS_SW18_STD))
+#define BIT_GET_SW18_STD(x) (((x) >> BIT_SHIFT_SW18_STD) & BIT_MASK_SW18_STD)
+#define BIT_SET_SW18_STD(x, v) (BIT_CLEAR_SW18_STD(x) | BIT_SW18_STD(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8881A_SUPPORT)
+
+/* 2 REG_SYS_SWR_CTRL2			(Offset 0x0014) */
+
+#define BIT_SW18_SD BIT(10)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_SYS_SWR_CTRL2			(Offset 0x0014) */
+
+#define BIT_SW18_AREN BIT(9)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_SYS_SWR_CTRL2			(Offset 0x0014) */
+
+#define BIT_SHIFT_OCP_V3 9
+#define BIT_MASK_OCP_V3 0x7
+#define BIT_OCP_V3(x) (((x) & BIT_MASK_OCP_V3) << BIT_SHIFT_OCP_V3)
+#define BITS_OCP_V3 (BIT_MASK_OCP_V3 << BIT_SHIFT_OCP_V3)
+#define BIT_CLEAR_OCP_V3(x) ((x) & (~BITS_OCP_V3))
+#define BIT_GET_OCP_V3(x) (((x) >> BIT_SHIFT_OCP_V3) & BIT_MASK_OCP_V3)
+#define BIT_SET_OCP_V3(x, v) (BIT_CLEAR_OCP_V3(x) | BIT_OCP_V3(v))
+
+#define BIT_POWOCP_V3 BIT(8)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_SYS_SWR_CTRL2			(Offset 0x0014) */
+
+#define BIT_SHIFT_SW18_R3 7
+#define BIT_MASK_SW18_R3 0x3
+#define BIT_SW18_R3(x) (((x) & BIT_MASK_SW18_R3) << BIT_SHIFT_SW18_R3)
+#define BITS_SW18_R3 (BIT_MASK_SW18_R3 << BIT_SHIFT_SW18_R3)
+#define BIT_CLEAR_SW18_R3(x) ((x) & (~BITS_SW18_R3))
+#define BIT_GET_SW18_R3(x) (((x) >> BIT_SHIFT_SW18_R3) & BIT_MASK_SW18_R3)
+#define BIT_SET_SW18_R3(x, v) (BIT_CLEAR_SW18_R3(x) | BIT_SW18_R3(v))
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_SDIO_HIMR				(Offset 0x10250014) */
+
+#define BIT_SDIO_TXBCNERR_MSK BIT(7)
+
+#endif
+
+#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+
+/* 2 REG_SYS_SWR_CTRL2			(Offset 0x0014) */
+
+#define BIT_SHIFT_R3_L 7
+#define BIT_MASK_R3_L 0x3
+#define BIT_R3_L(x) (((x) & BIT_MASK_R3_L) << BIT_SHIFT_R3_L)
+#define BITS_R3_L (BIT_MASK_R3_L << BIT_SHIFT_R3_L)
+#define BIT_CLEAR_R3_L(x) ((x) & (~BITS_R3_L))
+#define BIT_GET_R3_L(x) (((x) >> BIT_SHIFT_R3_L) & BIT_MASK_R3_L)
+#define BIT_SET_R3_L(x, v) (BIT_CLEAR_R3_L(x) | BIT_R3_L(v))
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_SDIO_HIMR				(Offset 0x10250014) */
+
+#define BIT_SDIO_TXBCNOK_MSK BIT(6)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_SYS_SWR_CTRL2			(Offset 0x0014) */
+
+#define BIT_SHIFT_CF_L_V3 6
+#define BIT_MASK_CF_L_V3 0x3
+#define BIT_CF_L_V3(x) (((x) & BIT_MASK_CF_L_V3) << BIT_SHIFT_CF_L_V3)
+#define BITS_CF_L_V3 (BIT_MASK_CF_L_V3 << BIT_SHIFT_CF_L_V3)
+#define BIT_CLEAR_CF_L_V3(x) ((x) & (~BITS_CF_L_V3))
+#define BIT_GET_CF_L_V3(x) (((x) >> BIT_SHIFT_CF_L_V3) & BIT_MASK_CF_L_V3)
+#define BIT_SET_CF_L_V3(x, v) (BIT_CLEAR_CF_L_V3(x) | BIT_CF_L_V3(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_SYS_SWR_CTRL2			(Offset 0x0014) */
+
+#define BIT_SHIFT_SW18_R2 5
+#define BIT_MASK_SW18_R2 0x3
+#define BIT_SW18_R2(x) (((x) & BIT_MASK_SW18_R2) << BIT_SHIFT_SW18_R2)
+#define BITS_SW18_R2 (BIT_MASK_SW18_R2 << BIT_SHIFT_SW18_R2)
+#define BIT_CLEAR_SW18_R2(x) ((x) & (~BITS_SW18_R2))
+#define BIT_GET_SW18_R2(x) (((x) >> BIT_SHIFT_SW18_R2) & BIT_MASK_SW18_R2)
+#define BIT_SET_SW18_R2(x, v) (BIT_CLEAR_SW18_R2(x) | BIT_SW18_R2(v))
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_SDIO_HIMR				(Offset 0x10250014) */
+
+#define BIT_SDIO_RXFOVW_MSK BIT(5)
+#define BIT_SDIO_TXFOVW_MSK BIT(4)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_SYS_SWR_CTRL2			(Offset 0x0014) */
+
+#define BIT_SHIFT_CFC_L_BIT0_TO_1_V1 4
+#define BIT_MASK_CFC_L_BIT0_TO_1_V1 0x3
+#define BIT_CFC_L_BIT0_TO_1_V1(x)                                              \
+	(((x) & BIT_MASK_CFC_L_BIT0_TO_1_V1) << BIT_SHIFT_CFC_L_BIT0_TO_1_V1)
+#define BITS_CFC_L_BIT0_TO_1_V1                                                \
+	(BIT_MASK_CFC_L_BIT0_TO_1_V1 << BIT_SHIFT_CFC_L_BIT0_TO_1_V1)
+#define BIT_CLEAR_CFC_L_BIT0_TO_1_V1(x) ((x) & (~BITS_CFC_L_BIT0_TO_1_V1))
+#define BIT_GET_CFC_L_BIT0_TO_1_V1(x)                                          \
+	(((x) >> BIT_SHIFT_CFC_L_BIT0_TO_1_V1) & BIT_MASK_CFC_L_BIT0_TO_1_V1)
+#define BIT_SET_CFC_L_BIT0_TO_1_V1(x, v)                                       \
+	(BIT_CLEAR_CFC_L_BIT0_TO_1_V1(x) | BIT_CFC_L_BIT0_TO_1_V1(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_SYS_SWR_CTRL2			(Offset 0x0014) */
+
+#define BIT_SHIFT_SW18_R1 3
+#define BIT_MASK_SW18_R1 0x3
+#define BIT_SW18_R1(x) (((x) & BIT_MASK_SW18_R1) << BIT_SHIFT_SW18_R1)
+#define BITS_SW18_R1 (BIT_MASK_SW18_R1 << BIT_SHIFT_SW18_R1)
+#define BIT_CLEAR_SW18_R1(x) ((x) & (~BITS_SW18_R1))
+#define BIT_GET_SW18_R1(x) (((x) >> BIT_SHIFT_SW18_R1) & BIT_MASK_SW18_R1)
+#define BIT_SET_SW18_R1(x, v) (BIT_CLEAR_SW18_R1(x) | BIT_SW18_R1(v))
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_SDIO_HIMR				(Offset 0x10250014) */
+
+#define BIT_SDIO_RXERR_MSK BIT(3)
+#define BIT_SDIO_TXERR_MSK BIT(2)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_SYS_SWR_CTRL2			(Offset 0x0014) */
+
+#define BIT_SHIFT_R3_L1_V1 2
+#define BIT_MASK_R3_L1_V1 0x3
+#define BIT_R3_L1_V1(x) (((x) & BIT_MASK_R3_L1_V1) << BIT_SHIFT_R3_L1_V1)
+#define BITS_R3_L1_V1 (BIT_MASK_R3_L1_V1 << BIT_SHIFT_R3_L1_V1)
+#define BIT_CLEAR_R3_L1_V1(x) ((x) & (~BITS_R3_L1_V1))
+#define BIT_GET_R3_L1_V1(x) (((x) >> BIT_SHIFT_R3_L1_V1) & BIT_MASK_R3_L1_V1)
+#define BIT_SET_R3_L1_V1(x, v) (BIT_CLEAR_R3_L1_V1(x) | BIT_R3_L1_V1(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_SYS_SWR_CTRL2			(Offset 0x0014) */
+
+#define BIT_SHIFT_SW18_C3 1
+#define BIT_MASK_SW18_C3 0x3
+#define BIT_SW18_C3(x) (((x) & BIT_MASK_SW18_C3) << BIT_SHIFT_SW18_C3)
+#define BITS_SW18_C3 (BIT_MASK_SW18_C3 << BIT_SHIFT_SW18_C3)
+#define BIT_CLEAR_SW18_C3(x) ((x) & (~BITS_SW18_C3))
+#define BIT_GET_SW18_C3(x) (((x) >> BIT_SHIFT_SW18_C3) & BIT_MASK_SW18_C3)
+#define BIT_SET_SW18_C3(x, v) (BIT_CLEAR_SW18_C3(x) | BIT_SW18_C3(v))
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_SDIO_HIMR				(Offset 0x10250014) */
+
+#define BIT_SDIO_AVAL_MSK BIT(1)
+
+#endif
+
+#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+
+/* 2 REG_SYS_SWR_CTRL2			(Offset 0x0014) */
+
+#define BIT_SHIFT_C3_L_C3 1
+#define BIT_MASK_C3_L_C3 0x3
+#define BIT_C3_L_C3(x) (((x) & BIT_MASK_C3_L_C3) << BIT_SHIFT_C3_L_C3)
+#define BITS_C3_L_C3 (BIT_MASK_C3_L_C3 << BIT_SHIFT_C3_L_C3)
+#define BIT_CLEAR_C3_L_C3(x) ((x) & (~BITS_C3_L_C3))
+#define BIT_GET_C3_L_C3(x) (((x) >> BIT_SHIFT_C3_L_C3) & BIT_MASK_C3_L_C3)
+#define BIT_SET_C3_L_C3(x, v) (BIT_CLEAR_C3_L_C3(x) | BIT_C3_L_C3(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_SYS_SWR_CTRL2			(Offset 0x0014) */
+
+#define BIT_SW18_C2_BIT1 BIT(0)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_SDIO_HIMR				(Offset 0x10250014) */
+
+#define BIT_RX_REQUEST_MSK BIT(0)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_SYS_SWR_CTRL2			(Offset 0x0014) */
+
+#define BIT_SHIFT_R2_L1_V1 0
+#define BIT_MASK_R2_L1_V1 0x3
+#define BIT_R2_L1_V1(x) (((x) & BIT_MASK_R2_L1_V1) << BIT_SHIFT_R2_L1_V1)
+#define BITS_R2_L1_V1 (BIT_MASK_R2_L1_V1 << BIT_SHIFT_R2_L1_V1)
+#define BIT_CLEAR_R2_L1_V1(x) ((x) & (~BITS_R2_L1_V1))
+#define BIT_GET_R2_L1_V1(x) (((x) >> BIT_SHIFT_R2_L1_V1) & BIT_MASK_R2_L1_V1)
+#define BIT_SET_R2_L1_V1(x, v) (BIT_CLEAR_R2_L1_V1(x) | BIT_R2_L1_V1(v))
+
+#endif
+
+#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+
+/* 2 REG_SYS_SWR_CTRL2			(Offset 0x0014) */
+
+#define BIT_C2_L_BIT1 BIT(0)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_SYS_SWR_CTRL3			(Offset 0x0018) */
+
+#define BIT_SPS18_OCP_DIS BIT(31)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_SDIO_HISR				(Offset 0x10250018) */
+
+#define BIT_SDIO_CRCERR BIT(31)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_SDIO_HISR				(Offset 0x10250018) */
+
+#define BIT_IO_READY_SIGNAL_ERR BIT(31)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_SDIO_HISR				(Offset 0x10250018) */
+
+#define BIT_SDIO_HSISR3_IND BIT(30)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_SDIO_HISR				(Offset 0x10250018) */
+
+#define BIT_TX_CRC BIT(30)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_SDIO_HISR				(Offset 0x10250018) */
+
+#define BIT_SDIO_HSISR2_IND BIT(29)
+#define BIT_SDIO_HEISR_IND BIT(28)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_SDIO_HISR				(Offset 0x10250018) */
+
+#define BIT_SDIO_CTWEND BIT(27)
+#define BIT_SDIO_ATIMEND_E BIT(26)
+#define BIT_SDIO_ATIMEND BIT(25)
+#define BIT_SDIO_OCPINT BIT(24)
+#define BIT_SDIO_PSTIMEOUT BIT(23)
+#define BIT_SDIO_GTINT4 BIT(22)
+#define BIT_SDIO_GTINT3 BIT(21)
+#define BIT_SDIO_HSISR_IND BIT(20)
+#define BIT_SDIO_CPWM2 BIT(19)
+#define BIT_SDIO_CPWM1 BIT(18)
+#define BIT_SDIO_C2HCMD_INT BIT(17)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_SYS_SWR_CTRL3			(Offset 0x0018) */
+
+#define BIT_SHIFT_SPS18_OCP_TH 16
+#define BIT_MASK_SPS18_OCP_TH 0x7fff
+#define BIT_SPS18_OCP_TH(x)                                                    \
+	(((x) & BIT_MASK_SPS18_OCP_TH) << BIT_SHIFT_SPS18_OCP_TH)
+#define BITS_SPS18_OCP_TH (BIT_MASK_SPS18_OCP_TH << BIT_SHIFT_SPS18_OCP_TH)
+#define BIT_CLEAR_SPS18_OCP_TH(x) ((x) & (~BITS_SPS18_OCP_TH))
+#define BIT_GET_SPS18_OCP_TH(x)                                                \
+	(((x) >> BIT_SHIFT_SPS18_OCP_TH) & BIT_MASK_SPS18_OCP_TH)
+#define BIT_SET_SPS18_OCP_TH(x, v)                                             \
+	(BIT_CLEAR_SPS18_OCP_TH(x) | BIT_SPS18_OCP_TH(v))
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_SDIO_HISR				(Offset 0x10250018) */
+
+#define BIT_SDIO_BCNERLY_INT BIT(16)
+#define BIT_SDIO_TXBCNERR BIT(7)
+#define BIT_SDIO_TXBCNOK BIT(6)
+#define BIT_SDIO_RXFOVW BIT(5)
+#define BIT_SDIO_TXFOVW BIT(4)
+#define BIT_SDIO_RXERR BIT(3)
+#define BIT_SDIO_TXERR BIT(2)
+#define BIT_SDIO_AVAL BIT(1)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_SYS_SWR_CTRL3			(Offset 0x0018) */
+
+#define BIT_SHIFT_OCP_WINDOW 0
+#define BIT_MASK_OCP_WINDOW 0xffff
+#define BIT_OCP_WINDOW(x) (((x) & BIT_MASK_OCP_WINDOW) << BIT_SHIFT_OCP_WINDOW)
+#define BITS_OCP_WINDOW (BIT_MASK_OCP_WINDOW << BIT_SHIFT_OCP_WINDOW)
+#define BIT_CLEAR_OCP_WINDOW(x) ((x) & (~BITS_OCP_WINDOW))
+#define BIT_GET_OCP_WINDOW(x)                                                  \
+	(((x) >> BIT_SHIFT_OCP_WINDOW) & BIT_MASK_OCP_WINDOW)
+#define BIT_SET_OCP_WINDOW(x, v) (BIT_CLEAR_OCP_WINDOW(x) | BIT_OCP_WINDOW(v))
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_SDIO_HISR				(Offset 0x10250018) */
+
+#define BIT_RX_REQUEST BIT(0)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_RSV_CTRL				(Offset 0x001C) */
+
+#define BIT_HREG_DBG BIT(23)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT)
+
+/* 2 REG_RSV_CTRL				(Offset 0x001C) */
+
+#define BIT_SHIFT_HREG_DBG_V1 12
+#define BIT_MASK_HREG_DBG_V1 0xfff
+#define BIT_HREG_DBG_V1(x)                                                     \
+	(((x) & BIT_MASK_HREG_DBG_V1) << BIT_SHIFT_HREG_DBG_V1)
+#define BITS_HREG_DBG_V1 (BIT_MASK_HREG_DBG_V1 << BIT_SHIFT_HREG_DBG_V1)
+#define BIT_CLEAR_HREG_DBG_V1(x) ((x) & (~BITS_HREG_DBG_V1))
+#define BIT_GET_HREG_DBG_V1(x)                                                 \
+	(((x) >> BIT_SHIFT_HREG_DBG_V1) & BIT_MASK_HREG_DBG_V1)
+#define BIT_SET_HREG_DBG_V1(x, v)                                              \
+	(BIT_CLEAR_HREG_DBG_V1(x) | BIT_HREG_DBG_V1(v))
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_RSV_CTRL				(Offset 0x001C) */
+
+#define BIT_MCU_RST BIT(11)
+#define BIT_WLOCK_90 BIT(10)
+#define BIT_WLOCK_70 BIT(9)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8881A_SUPPORT)
+
+/* 2 REG_RSV_CTRL				(Offset 0x001C) */
+
+#define BIT_WLMCUIOIF BIT(8)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_RSV_CTRL				(Offset 0x001C) */
+
+#define BIT_WLOCK_78 BIT(8)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_RSV_CTRL				(Offset 0x001C) */
+
+#define BIT_LOCK_ALL_EN BIT(7)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8881A_SUPPORT)
+
+/* 2 REG_RSV_CTRL				(Offset 0x001C) */
+
+#define BIT_R_DIS_PRST BIT(6)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_RSV_CTRL				(Offset 0x001C) */
+
+#define BIT_R_DIS_PRST_1 BIT(6)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8881A_SUPPORT)
+
+/* 2 REG_RSV_CTRL				(Offset 0x001C) */
+
+#define BIT_WLOCK_1C_B6 BIT(5)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_RSV_CTRL				(Offset 0x001C) */
+
+#define BIT_R_DIS_PRST_0 BIT(5)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_RSV_CTRL				(Offset 0x001C) */
+
+#define BIT_WLOCK_40 BIT(4)
+#define BIT_WLOCK_08 BIT(3)
+#define BIT_WLOCK_04 BIT(2)
+#define BIT_WLOCK_00 BIT(1)
+#define BIT_WLOCK_ALL BIT(0)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_SDIO_RX_REQ_LEN			(Offset 0x1025001C) */
+
+#define BIT_SHIFT_RX_REQ_LEN_V1 0
+#define BIT_MASK_RX_REQ_LEN_V1 0x3ffff
+#define BIT_RX_REQ_LEN_V1(x)                                                   \
+	(((x) & BIT_MASK_RX_REQ_LEN_V1) << BIT_SHIFT_RX_REQ_LEN_V1)
+#define BITS_RX_REQ_LEN_V1 (BIT_MASK_RX_REQ_LEN_V1 << BIT_SHIFT_RX_REQ_LEN_V1)
+#define BIT_CLEAR_RX_REQ_LEN_V1(x) ((x) & (~BITS_RX_REQ_LEN_V1))
+#define BIT_GET_RX_REQ_LEN_V1(x)                                               \
+	(((x) >> BIT_SHIFT_RX_REQ_LEN_V1) & BIT_MASK_RX_REQ_LEN_V1)
+#define BIT_SET_RX_REQ_LEN_V1(x, v)                                            \
+	(BIT_CLEAR_RX_REQ_LEN_V1(x) | BIT_RX_REQ_LEN_V1(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8881A_SUPPORT)
+
+/* 2 REG_RF_CTRL				(Offset 0x001F) */
+
+#define BIT_RF_SDMRSTB BIT(2)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_RF0_CTRL				(Offset 0x001F) */
+
+#define BIT_RF0_SDMRSTB BIT(2)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8881A_SUPPORT)
+
+/* 2 REG_RF_CTRL				(Offset 0x001F) */
+
+#define BIT_RF_RSTB BIT(1)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_RF0_CTRL				(Offset 0x001F) */
+
+#define BIT_RF0_RSTB BIT(1)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8881A_SUPPORT)
+
+/* 2 REG_RF_CTRL				(Offset 0x001F) */
+
+#define BIT_RF_EN BIT(0)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_RF0_CTRL				(Offset 0x001F) */
+
+#define BIT_RF0_EN BIT(0)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_SDIO_FREE_TXPG_SEQ_V1		(Offset 0x1025001F) */
+
+#define BIT_SHIFT_FREE_TXPG_SEQ 0
+#define BIT_MASK_FREE_TXPG_SEQ 0xff
+#define BIT_FREE_TXPG_SEQ(x)                                                   \
+	(((x) & BIT_MASK_FREE_TXPG_SEQ) << BIT_SHIFT_FREE_TXPG_SEQ)
+#define BITS_FREE_TXPG_SEQ (BIT_MASK_FREE_TXPG_SEQ << BIT_SHIFT_FREE_TXPG_SEQ)
+#define BIT_CLEAR_FREE_TXPG_SEQ(x) ((x) & (~BITS_FREE_TXPG_SEQ))
+#define BIT_GET_FREE_TXPG_SEQ(x)                                               \
+	(((x) >> BIT_SHIFT_FREE_TXPG_SEQ) & BIT_MASK_FREE_TXPG_SEQ)
+#define BIT_SET_FREE_TXPG_SEQ(x, v)                                            \
+	(BIT_CLEAR_FREE_TXPG_SEQ(x) | BIT_FREE_TXPG_SEQ(v))
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_AFE_LDO_CTRL			(Offset 0x0020) */
+
+#define BIT_R_SYM_WLPON_EMEM1_EN BIT(31)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_AFE_LDO_CTRL			(Offset 0x0020) */
+
+#define BIT_LPLDH12_RSV1 BIT(31)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_AFE_LDO_CTRL			(Offset 0x0020) */
+
+#define BIT_R_SYM_WLPON_EMEM0_EN BIT(30)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_AFE_LDO_CTRL			(Offset 0x0020) */
+
+#define BIT_LPLDH12_RSV0 BIT(30)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8881A_SUPPORT)
+
+/* 2 REG_AFE_LDO_CTRL			(Offset 0x0020) */
+
+#define BIT_SHIFT_LPLDH12_RSV 29
+#define BIT_MASK_LPLDH12_RSV 0x7
+#define BIT_LPLDH12_RSV(x)                                                     \
+	(((x) & BIT_MASK_LPLDH12_RSV) << BIT_SHIFT_LPLDH12_RSV)
+#define BITS_LPLDH12_RSV (BIT_MASK_LPLDH12_RSV << BIT_SHIFT_LPLDH12_RSV)
+#define BIT_CLEAR_LPLDH12_RSV(x) ((x) & (~BITS_LPLDH12_RSV))
+#define BIT_GET_LPLDH12_RSV(x)                                                 \
+	(((x) >> BIT_SHIFT_LPLDH12_RSV) & BIT_MASK_LPLDH12_RSV)
+#define BIT_SET_LPLDH12_RSV(x, v)                                              \
+	(BIT_CLEAR_LPLDH12_RSV(x) | BIT_LPLDH12_RSV(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_AFE_LDO_CTRL			(Offset 0x0020) */
+
+#define BIT_LPLDH12_SLP BIT(28)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_AFE_LDO_CTRL			(Offset 0x0020) */
+
+#define BIT_R_SYM_WLPOFF_P4EN BIT(28)
+#define BIT_R_SYM_WLPOFF_P3EN BIT(27)
+#define BIT_R_SYM_WLPOFF_P2EN BIT(26)
+#define BIT_R_SYM_WLPOFF_P1EN BIT(25)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_AFE_LDO_CTRL			(Offset 0x0020) */
+
+#define BIT_SHIFT_LPLDH12_VADJ 24
+#define BIT_MASK_LPLDH12_VADJ 0xf
+#define BIT_LPLDH12_VADJ(x)                                                    \
+	(((x) & BIT_MASK_LPLDH12_VADJ) << BIT_SHIFT_LPLDH12_VADJ)
+#define BITS_LPLDH12_VADJ (BIT_MASK_LPLDH12_VADJ << BIT_SHIFT_LPLDH12_VADJ)
+#define BIT_CLEAR_LPLDH12_VADJ(x) ((x) & (~BITS_LPLDH12_VADJ))
+#define BIT_GET_LPLDH12_VADJ(x)                                                \
+	(((x) >> BIT_SHIFT_LPLDH12_VADJ) & BIT_MASK_LPLDH12_VADJ)
+#define BIT_SET_LPLDH12_VADJ(x, v)                                             \
+	(BIT_CLEAR_LPLDH12_VADJ(x) | BIT_LPLDH12_VADJ(v))
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_AFE_LDO_CTRL			(Offset 0x0020) */
+
+#define BIT_R_SYM_WLPOFF_EN BIT(24)
+#define BIT_R_SYM_WLPON_P3EN BIT(21)
+#define BIT_R_SYM_WLPON_P2EN BIT(20)
+#define BIT_R_SYM_WLPON_P1EN BIT(19)
+#define BIT_R_SYM_WLPON_EN BIT(18)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT)
+
+/* 2 REG_AFE_LDO_CTRL			(Offset 0x0020) */
+
+#define BIT_PCIE_CALIB_EN BIT(17)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_AFE_LDO_CTRL			(Offset 0x0020) */
+
+#define BIT_LDH12_EN BIT(16)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_SDIO_FREE_TXPG			(Offset 0x10250020) */
+
+#define BIT_SHIFT_MID_FREEPG_V1 16
+#define BIT_MASK_MID_FREEPG_V1 0xfff
+#define BIT_MID_FREEPG_V1(x)                                                   \
+	(((x) & BIT_MASK_MID_FREEPG_V1) << BIT_SHIFT_MID_FREEPG_V1)
+#define BITS_MID_FREEPG_V1 (BIT_MASK_MID_FREEPG_V1 << BIT_SHIFT_MID_FREEPG_V1)
+#define BIT_CLEAR_MID_FREEPG_V1(x) ((x) & (~BITS_MID_FREEPG_V1))
+#define BIT_GET_MID_FREEPG_V1(x)                                               \
+	(((x) >> BIT_SHIFT_MID_FREEPG_V1) & BIT_MASK_MID_FREEPG_V1)
+#define BIT_SET_MID_FREEPG_V1(x, v)                                            \
+	(BIT_CLEAR_MID_FREEPG_V1(x) | BIT_MID_FREEPG_V1(v))
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_AFE_LDO_CTRL			(Offset 0x0020) */
+
+#define BIT_R_SYM_LDOV12D_STBY BIT(16)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT)
+
+/* 2 REG_AFE_LDO_CTRL			(Offset 0x0020) */
+
+#define BIT_BB_POWER_CUT_CTRL_BY_BB BIT(15)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+
+/* 2 REG_AFE_LDO_CTRL			(Offset 0x0020) */
+
+#define BIT_WLBBOFF_BIG_PWC_EN BIT(14)
+#define BIT_WLBBOFF_SMALL_PWC_EN BIT(13)
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+/* 2 REG_AFE_LDO_CTRL			(Offset 0x0020) */
+
+#define BIT_POW_REGU_P3 BIT(12)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+
+/* 2 REG_AFE_LDO_CTRL			(Offset 0x0020) */
+
+#define BIT_WLMACOFF_BIG_PWC_EN BIT(12)
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+/* 2 REG_AFE_LDO_CTRL			(Offset 0x0020) */
+
+#define BIT_POW_REGU_P2 BIT(11)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+
+/* 2 REG_AFE_LDO_CTRL			(Offset 0x0020) */
+
+#define BIT_WLPON_PWC_EN BIT(11)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+
+/* 2 REG_AFE_LDO_CTRL			(Offset 0x0020) */
+
+#define BIT_POW_REGU_P1 BIT(10)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_AFE_LDO_CTRL			(Offset 0x0020) */
+
+#define BIT_MEM_DS_EN BIT(9)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_AFE_LDO_CTRL			(Offset 0x0020) */
+
+#define BIT_R_SYM_WLBBOFF1_P4_EN BIT(9)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_AFE_LDO_CTRL			(Offset 0x0020) */
+
+#define BIT_LDOV12W_EN BIT(8)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_AFE_LDO_CTRL			(Offset 0x0020) */
+
+#define BIT_R_SYM_WLBBOFF1_P3_EN BIT(8)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_AFE_LDO_CTRL			(Offset 0x0020) */
+
+#define BIT_SHIFT_ANAPAR_RFC2 8
+#define BIT_MASK_ANAPAR_RFC2 0xff
+#define BIT_ANAPAR_RFC2(x)                                                     \
+	(((x) & BIT_MASK_ANAPAR_RFC2) << BIT_SHIFT_ANAPAR_RFC2)
+#define BITS_ANAPAR_RFC2 (BIT_MASK_ANAPAR_RFC2 << BIT_SHIFT_ANAPAR_RFC2)
+#define BIT_CLEAR_ANAPAR_RFC2(x) ((x) & (~BITS_ANAPAR_RFC2))
+#define BIT_GET_ANAPAR_RFC2(x)                                                 \
+	(((x) >> BIT_SHIFT_ANAPAR_RFC2) & BIT_MASK_ANAPAR_RFC2)
+#define BIT_SET_ANAPAR_RFC2(x, v)                                              \
+	(BIT_CLEAR_ANAPAR_RFC2(x) | BIT_ANAPAR_RFC2(v))
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+
+/* 2 REG_AFE_LDO_CTRL			(Offset 0x0020) */
+
+#define BIT_EX_XTAL_DRV_DIGI BIT(7)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_AFE_LDO_CTRL			(Offset 0x0020) */
+
+#define BIT_R_SYM_WLBBOFF1_P2_EN BIT(7)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+
+/* 2 REG_AFE_LDO_CTRL			(Offset 0x0020) */
+
+#define BIT_EX_XTAL_DRV_USB BIT(6)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_AFE_LDO_CTRL			(Offset 0x0020) */
+
+#define BIT_R_SYM_WLBBOFF1_P1_EN BIT(6)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+
+/* 2 REG_AFE_LDO_CTRL			(Offset 0x0020) */
+
+#define BIT_EX_XTAL_DRV_AFE BIT(5)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_AFE_LDO_CTRL			(Offset 0x0020) */
+
+#define BIT_SHIFT_LDA12_VOADJ 4
+#define BIT_MASK_LDA12_VOADJ 0xf
+#define BIT_LDA12_VOADJ(x)                                                     \
+	(((x) & BIT_MASK_LDA12_VOADJ) << BIT_SHIFT_LDA12_VOADJ)
+#define BITS_LDA12_VOADJ (BIT_MASK_LDA12_VOADJ << BIT_SHIFT_LDA12_VOADJ)
+#define BIT_CLEAR_LDA12_VOADJ(x) ((x) & (~BITS_LDA12_VOADJ))
+#define BIT_GET_LDA12_VOADJ(x)                                                 \
+	(((x) >> BIT_SHIFT_LDA12_VOADJ) & BIT_MASK_LDA12_VOADJ)
+#define BIT_SET_LDA12_VOADJ(x, v)                                              \
+	(BIT_CLEAR_LDA12_VOADJ(x) | BIT_LDA12_VOADJ(v))
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+
+/* 2 REG_AFE_LDO_CTRL			(Offset 0x0020) */
+
+#define BIT_EX_XTAL_DRV_RF2 BIT(4)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_AFE_LDO_CTRL			(Offset 0x0020) */
+
+#define BIT_R_SYM_WLBBOFF_P4_EN BIT(4)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_AFE_LDO_CTRL			(Offset 0x0020) */
+
+#define BIT_REG_VOS BIT(3)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+
+/* 2 REG_AFE_LDO_CTRL			(Offset 0x0020) */
+
+#define BIT_EX_XTAL_DRV_RF1 BIT(3)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_AFE_LDO_CTRL			(Offset 0x0020) */
+
+#define BIT_R_SYM_WLBBOFF_P3_EN BIT(3)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+
+/* 2 REG_AFE_LDO_CTRL			(Offset 0x0020) */
+
+#define BIT_POW_REGU_P0 BIT(2)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_AFE_LDO_CTRL			(Offset 0x0020) */
+
+#define BIT_R_SYM_WLBBOFF_P2_EN BIT(2)
+#define BIT_R_SYM_WLBBOFF_P1_EN BIT(1)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_AFE_LDO_CTRL			(Offset 0x0020) */
+
+#define BIT_LDA12_EN BIT(0)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+
+/* 2 REG_AFE_LDO_CTRL			(Offset 0x0020) */
+
+#define BIT_POW_PLL_LDO BIT(0)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_SDIO_FREE_TXPG			(Offset 0x10250020) */
+
+#define BIT_SHIFT_HIQ_FREEPG_V1 0
+#define BIT_MASK_HIQ_FREEPG_V1 0xfff
+#define BIT_HIQ_FREEPG_V1(x)                                                   \
+	(((x) & BIT_MASK_HIQ_FREEPG_V1) << BIT_SHIFT_HIQ_FREEPG_V1)
+#define BITS_HIQ_FREEPG_V1 (BIT_MASK_HIQ_FREEPG_V1 << BIT_SHIFT_HIQ_FREEPG_V1)
+#define BIT_CLEAR_HIQ_FREEPG_V1(x) ((x) & (~BITS_HIQ_FREEPG_V1))
+#define BIT_GET_HIQ_FREEPG_V1(x)                                               \
+	(((x) >> BIT_SHIFT_HIQ_FREEPG_V1) & BIT_MASK_HIQ_FREEPG_V1)
+#define BIT_SET_HIQ_FREEPG_V1(x, v)                                            \
+	(BIT_CLEAR_HIQ_FREEPG_V1(x) | BIT_HIQ_FREEPG_V1(v))
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_AFE_LDO_CTRL			(Offset 0x0020) */
+
+#define BIT_R_SYM_WLBBOFF_EN BIT(0)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_AFE_LDO_CTRL			(Offset 0x0020) */
+
+#define BIT_SHIFT_ANAPAR_RFC1 0
+#define BIT_MASK_ANAPAR_RFC1 0xff
+#define BIT_ANAPAR_RFC1(x)                                                     \
+	(((x) & BIT_MASK_ANAPAR_RFC1) << BIT_SHIFT_ANAPAR_RFC1)
+#define BITS_ANAPAR_RFC1 (BIT_MASK_ANAPAR_RFC1 << BIT_SHIFT_ANAPAR_RFC1)
+#define BIT_CLEAR_ANAPAR_RFC1(x) ((x) & (~BITS_ANAPAR_RFC1))
+#define BIT_GET_ANAPAR_RFC1(x)                                                 \
+	(((x) >> BIT_SHIFT_ANAPAR_RFC1) & BIT_MASK_ANAPAR_RFC1)
+#define BIT_SET_ANAPAR_RFC1(x, v)                                              \
+	(BIT_CLEAR_ANAPAR_RFC1(x) | BIT_ANAPAR_RFC1(v))
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+
+/* 2 REG_AFE_CTRL1				(Offset 0x0024) */
+
+#define BIT_AGPIO_GPE BIT(31)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_AFE_CTRL1				(Offset 0x0024) */
+
+#define BIT_XQSEL_V3 BIT(31)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_AFE_CTRL1				(Offset 0x0024) */
+
+#define BIT_SHIFT_REG_CC 30
+#define BIT_MASK_REG_CC 0x3
+#define BIT_REG_CC(x) (((x) & BIT_MASK_REG_CC) << BIT_SHIFT_REG_CC)
+#define BITS_REG_CC (BIT_MASK_REG_CC << BIT_SHIFT_REG_CC)
+#define BIT_CLEAR_REG_CC(x) ((x) & (~BITS_REG_CC))
+#define BIT_GET_REG_CC(x) (((x) >> BIT_SHIFT_REG_CC) & BIT_MASK_REG_CC)
+#define BIT_SET_REG_CC(x, v) (BIT_CLEAR_REG_CC(x) | BIT_REG_CC(v))
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_AFE_CTRL1				(Offset 0x0024) */
+
+#define BIT_CKDELAY_AFE_V1 BIT(30)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_AFE_CTRL1				(Offset 0x0024) */
+
+#define BIT_CKDLY_DIG BIT(28)
+#define BIT_CKDLY_USB BIT(27)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_AFE_CTRL1				(Offset 0x0024) */
+
+#define BIT_SHIFT_XTAL_GPIO_V1 27
+#define BIT_MASK_XTAL_GPIO_V1 0x7
+#define BIT_XTAL_GPIO_V1(x)                                                    \
+	(((x) & BIT_MASK_XTAL_GPIO_V1) << BIT_SHIFT_XTAL_GPIO_V1)
+#define BITS_XTAL_GPIO_V1 (BIT_MASK_XTAL_GPIO_V1 << BIT_SHIFT_XTAL_GPIO_V1)
+#define BIT_CLEAR_XTAL_GPIO_V1(x) ((x) & (~BITS_XTAL_GPIO_V1))
+#define BIT_GET_XTAL_GPIO_V1(x)                                                \
+	(((x) >> BIT_SHIFT_XTAL_GPIO_V1) & BIT_MASK_XTAL_GPIO_V1)
+#define BIT_SET_XTAL_GPIO_V1(x, v)                                             \
+	(BIT_CLEAR_XTAL_GPIO_V1(x) | BIT_XTAL_GPIO_V1(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_AFE_CTRL1				(Offset 0x0024) */
+
+#define BIT_CKDLY_AFE BIT(26)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+
+/* 2 REG_AFE_CTRL1				(Offset 0x0024) */
+
+#define BIT_SHIFT_XTAL_CAP_XI 25
+#define BIT_MASK_XTAL_CAP_XI 0x3f
+#define BIT_XTAL_CAP_XI(x)                                                     \
+	(((x) & BIT_MASK_XTAL_CAP_XI) << BIT_SHIFT_XTAL_CAP_XI)
+#define BITS_XTAL_CAP_XI (BIT_MASK_XTAL_CAP_XI << BIT_SHIFT_XTAL_CAP_XI)
+#define BIT_CLEAR_XTAL_CAP_XI(x) ((x) & (~BITS_XTAL_CAP_XI))
+#define BIT_GET_XTAL_CAP_XI(x)                                                 \
+	(((x) >> BIT_SHIFT_XTAL_CAP_XI) & BIT_MASK_XTAL_CAP_XI)
+#define BIT_SET_XTAL_CAP_XI(x, v)                                              \
+	(BIT_CLEAR_XTAL_CAP_XI(x) | BIT_XTAL_CAP_XI(v))
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_AFE_CTRL1				(Offset 0x0024) */
+
+#define BIT_SHIFT_XTAL_DIG_DRV_1_TO_0 25
+#define BIT_MASK_XTAL_DIG_DRV_1_TO_0 0x3
+#define BIT_XTAL_DIG_DRV_1_TO_0(x)                                             \
+	(((x) & BIT_MASK_XTAL_DIG_DRV_1_TO_0) << BIT_SHIFT_XTAL_DIG_DRV_1_TO_0)
+#define BITS_XTAL_DIG_DRV_1_TO_0                                               \
+	(BIT_MASK_XTAL_DIG_DRV_1_TO_0 << BIT_SHIFT_XTAL_DIG_DRV_1_TO_0)
+#define BIT_CLEAR_XTAL_DIG_DRV_1_TO_0(x) ((x) & (~BITS_XTAL_DIG_DRV_1_TO_0))
+#define BIT_GET_XTAL_DIG_DRV_1_TO_0(x)                                         \
+	(((x) >> BIT_SHIFT_XTAL_DIG_DRV_1_TO_0) & BIT_MASK_XTAL_DIG_DRV_1_TO_0)
+#define BIT_SET_XTAL_DIG_DRV_1_TO_0(x, v)                                      \
+	(BIT_CLEAR_XTAL_DIG_DRV_1_TO_0(x) | BIT_XTAL_DIG_DRV_1_TO_0(v))
+
+#define BIT_XTAL_GDIG BIT(24)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_AFE_CTRL1				(Offset 0x0024) */
+
+#define BIT_SHIFT_XTAL_GPIO 23
+#define BIT_MASK_XTAL_GPIO 0x7
+#define BIT_XTAL_GPIO(x) (((x) & BIT_MASK_XTAL_GPIO) << BIT_SHIFT_XTAL_GPIO)
+#define BITS_XTAL_GPIO (BIT_MASK_XTAL_GPIO << BIT_SHIFT_XTAL_GPIO)
+#define BIT_CLEAR_XTAL_GPIO(x) ((x) & (~BITS_XTAL_GPIO))
+#define BIT_GET_XTAL_GPIO(x) (((x) >> BIT_SHIFT_XTAL_GPIO) & BIT_MASK_XTAL_GPIO)
+#define BIT_SET_XTAL_GPIO(x, v) (BIT_CLEAR_XTAL_GPIO(x) | BIT_XTAL_GPIO(v))
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+
+/* 2 REG_AFE_CTRL1				(Offset 0x0024) */
+
+#define BIT_SHIFT_XTAL_DRV_DIGI 23
+#define BIT_MASK_XTAL_DRV_DIGI 0x3
+#define BIT_XTAL_DRV_DIGI(x)                                                   \
+	(((x) & BIT_MASK_XTAL_DRV_DIGI) << BIT_SHIFT_XTAL_DRV_DIGI)
+#define BITS_XTAL_DRV_DIGI (BIT_MASK_XTAL_DRV_DIGI << BIT_SHIFT_XTAL_DRV_DIGI)
+#define BIT_CLEAR_XTAL_DRV_DIGI(x) ((x) & (~BITS_XTAL_DRV_DIGI))
+#define BIT_GET_XTAL_DRV_DIGI(x)                                               \
+	(((x) >> BIT_SHIFT_XTAL_DRV_DIGI) & BIT_MASK_XTAL_DRV_DIGI)
+#define BIT_SET_XTAL_DRV_DIGI(x, v)                                            \
+	(BIT_CLEAR_XTAL_DRV_DIGI(x) | BIT_XTAL_DRV_DIGI(v))
+
+#define BIT_XTAL_DRV_USB_BIT1 BIT(22)
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+/* 2 REG_AFE_CTRL1				(Offset 0x0024) */
+
+#define BIT_XTAL_DRV_RF_LATCH_V2 BIT(22)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT)
+
+/* 2 REG_AFE_CTRL1				(Offset 0x0024) */
+
+#define BIT_SHIFT_XTAL_RDRV_RF2_1_TO_0 22
+#define BIT_MASK_XTAL_RDRV_RF2_1_TO_0 0x3
+#define BIT_XTAL_RDRV_RF2_1_TO_0(x)                                            \
+	(((x) & BIT_MASK_XTAL_RDRV_RF2_1_TO_0)                                 \
+	 << BIT_SHIFT_XTAL_RDRV_RF2_1_TO_0)
+#define BITS_XTAL_RDRV_RF2_1_TO_0                                              \
+	(BIT_MASK_XTAL_RDRV_RF2_1_TO_0 << BIT_SHIFT_XTAL_RDRV_RF2_1_TO_0)
+#define BIT_CLEAR_XTAL_RDRV_RF2_1_TO_0(x) ((x) & (~BITS_XTAL_RDRV_RF2_1_TO_0))
+#define BIT_GET_XTAL_RDRV_RF2_1_TO_0(x)                                        \
+	(((x) >> BIT_SHIFT_XTAL_RDRV_RF2_1_TO_0) &                             \
+	 BIT_MASK_XTAL_RDRV_RF2_1_TO_0)
+#define BIT_SET_XTAL_RDRV_RF2_1_TO_0(x, v)                                     \
+	(BIT_CLEAR_XTAL_RDRV_RF2_1_TO_0(x) | BIT_XTAL_RDRV_RF2_1_TO_0(v))
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_AFE_CTRL1				(Offset 0x0024) */
+
+#define BIT_XTAL_GMN_4 BIT(21)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8881A_SUPPORT)
+
+/* 2 REG_AFE_CTRL1				(Offset 0x0024) */
+
+#define BIT_SHIFT_MAC_CLK_SEL 20
+#define BIT_MASK_MAC_CLK_SEL 0x3
+#define BIT_MAC_CLK_SEL(x)                                                     \
+	(((x) & BIT_MASK_MAC_CLK_SEL) << BIT_SHIFT_MAC_CLK_SEL)
+#define BITS_MAC_CLK_SEL (BIT_MASK_MAC_CLK_SEL << BIT_SHIFT_MAC_CLK_SEL)
+#define BIT_CLEAR_MAC_CLK_SEL(x) ((x) & (~BITS_MAC_CLK_SEL))
+#define BIT_GET_MAC_CLK_SEL(x)                                                 \
+	(((x) >> BIT_SHIFT_MAC_CLK_SEL) & BIT_MASK_MAC_CLK_SEL)
+#define BIT_SET_MAC_CLK_SEL(x, v)                                              \
+	(BIT_CLEAR_MAC_CLK_SEL(x) | BIT_MAC_CLK_SEL(v))
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+
+/* 2 REG_AFE_CTRL1				(Offset 0x0024) */
+
+#define BIT_XTAL_DRV_USB_BIT0 BIT(19)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_AFE_CTRL1				(Offset 0x0024) */
+
+#define BIT_SHIFT_XTAL_RDRV_1_TO_0 19
+#define BIT_MASK_XTAL_RDRV_1_TO_0 0x3
+#define BIT_XTAL_RDRV_1_TO_0(x)                                                \
+	(((x) & BIT_MASK_XTAL_RDRV_1_TO_0) << BIT_SHIFT_XTAL_RDRV_1_TO_0)
+#define BITS_XTAL_RDRV_1_TO_0                                                  \
+	(BIT_MASK_XTAL_RDRV_1_TO_0 << BIT_SHIFT_XTAL_RDRV_1_TO_0)
+#define BIT_CLEAR_XTAL_RDRV_1_TO_0(x) ((x) & (~BITS_XTAL_RDRV_1_TO_0))
+#define BIT_GET_XTAL_RDRV_1_TO_0(x)                                            \
+	(((x) >> BIT_SHIFT_XTAL_RDRV_1_TO_0) & BIT_MASK_XTAL_RDRV_1_TO_0)
+#define BIT_SET_XTAL_RDRV_1_TO_0(x, v)                                         \
+	(BIT_CLEAR_XTAL_RDRV_1_TO_0(x) | BIT_XTAL_RDRV_1_TO_0(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_AFE_CTRL1				(Offset 0x0024) */
+
+#define BIT_SHIFT_XTAL_DIG_DRV 18
+#define BIT_MASK_XTAL_DIG_DRV 0x3
+#define BIT_XTAL_DIG_DRV(x)                                                    \
+	(((x) & BIT_MASK_XTAL_DIG_DRV) << BIT_SHIFT_XTAL_DIG_DRV)
+#define BITS_XTAL_DIG_DRV (BIT_MASK_XTAL_DIG_DRV << BIT_SHIFT_XTAL_DIG_DRV)
+#define BIT_CLEAR_XTAL_DIG_DRV(x) ((x) & (~BITS_XTAL_DIG_DRV))
+#define BIT_GET_XTAL_DIG_DRV(x)                                                \
+	(((x) >> BIT_SHIFT_XTAL_DIG_DRV) & BIT_MASK_XTAL_DIG_DRV)
+#define BIT_SET_XTAL_DIG_DRV(x, v)                                             \
+	(BIT_CLEAR_XTAL_DIG_DRV(x) | BIT_XTAL_DIG_DRV(v))
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_AFE_CTRL1				(Offset 0x0024) */
+
+#define BIT_XTAL_GMP_4 BIT(18)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_AFE_CTRL1				(Offset 0x0024) */
+
+#define BIT_XTAL_GATE_DIG BIT(17)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+
+/* 2 REG_AFE_CTRL1				(Offset 0x0024) */
+
+#define BIT_SHIFT_XTAL_DRV_AFE 17
+#define BIT_MASK_XTAL_DRV_AFE 0x3
+#define BIT_XTAL_DRV_AFE(x)                                                    \
+	(((x) & BIT_MASK_XTAL_DRV_AFE) << BIT_SHIFT_XTAL_DRV_AFE)
+#define BITS_XTAL_DRV_AFE (BIT_MASK_XTAL_DRV_AFE << BIT_SHIFT_XTAL_DRV_AFE)
+#define BIT_CLEAR_XTAL_DRV_AFE(x) ((x) & (~BITS_XTAL_DRV_AFE))
+#define BIT_GET_XTAL_DRV_AFE(x)                                                \
+	(((x) >> BIT_SHIFT_XTAL_DRV_AFE) & BIT_MASK_XTAL_DRV_AFE)
+#define BIT_SET_XTAL_DRV_AFE(x, v)                                             \
+	(BIT_CLEAR_XTAL_DRV_AFE(x) | BIT_XTAL_DRV_AFE(v))
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_SDIO_FREE_TXPG2			(Offset 0x10250024) */
+
+#define BIT_SHIFT_PUB_FREEPG_V1 16
+#define BIT_MASK_PUB_FREEPG_V1 0xfff
+#define BIT_PUB_FREEPG_V1(x)                                                   \
+	(((x) & BIT_MASK_PUB_FREEPG_V1) << BIT_SHIFT_PUB_FREEPG_V1)
+#define BITS_PUB_FREEPG_V1 (BIT_MASK_PUB_FREEPG_V1 << BIT_SHIFT_PUB_FREEPG_V1)
+#define BIT_CLEAR_PUB_FREEPG_V1(x) ((x) & (~BITS_PUB_FREEPG_V1))
+#define BIT_GET_PUB_FREEPG_V1(x)                                               \
+	(((x) >> BIT_SHIFT_PUB_FREEPG_V1) & BIT_MASK_PUB_FREEPG_V1)
+#define BIT_SET_PUB_FREEPG_V1(x, v)                                            \
+	(BIT_CLEAR_PUB_FREEPG_V1(x) | BIT_PUB_FREEPG_V1(v))
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_AFE_CTRL1				(Offset 0x0024) */
+
+#define BIT_SHIFT_XTAL_ADRV_1_TO_0 16
+#define BIT_MASK_XTAL_ADRV_1_TO_0 0x3
+#define BIT_XTAL_ADRV_1_TO_0(x)                                                \
+	(((x) & BIT_MASK_XTAL_ADRV_1_TO_0) << BIT_SHIFT_XTAL_ADRV_1_TO_0)
+#define BITS_XTAL_ADRV_1_TO_0                                                  \
+	(BIT_MASK_XTAL_ADRV_1_TO_0 << BIT_SHIFT_XTAL_ADRV_1_TO_0)
+#define BIT_CLEAR_XTAL_ADRV_1_TO_0(x) ((x) & (~BITS_XTAL_ADRV_1_TO_0))
+#define BIT_GET_XTAL_ADRV_1_TO_0(x)                                            \
+	(((x) >> BIT_SHIFT_XTAL_ADRV_1_TO_0) & BIT_MASK_XTAL_ADRV_1_TO_0)
+#define BIT_SET_XTAL_ADRV_1_TO_0(x, v)                                         \
+	(BIT_CLEAR_XTAL_ADRV_1_TO_0(x) | BIT_XTAL_ADRV_1_TO_0(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_AFE_CTRL1				(Offset 0x0024) */
+
+#define BIT_SHIFT_XTAL_RF_DRV 15
+#define BIT_MASK_XTAL_RF_DRV 0x3
+#define BIT_XTAL_RF_DRV(x)                                                     \
+	(((x) & BIT_MASK_XTAL_RF_DRV) << BIT_SHIFT_XTAL_RF_DRV)
+#define BITS_XTAL_RF_DRV (BIT_MASK_XTAL_RF_DRV << BIT_SHIFT_XTAL_RF_DRV)
+#define BIT_CLEAR_XTAL_RF_DRV(x) ((x) & (~BITS_XTAL_RF_DRV))
+#define BIT_GET_XTAL_RF_DRV(x)                                                 \
+	(((x) >> BIT_SHIFT_XTAL_RF_DRV) & BIT_MASK_XTAL_RF_DRV)
+#define BIT_SET_XTAL_RF_DRV(x, v)                                              \
+	(BIT_CLEAR_XTAL_RF_DRV(x) | BIT_XTAL_RF_DRV(v))
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+
+/* 2 REG_AFE_CTRL1				(Offset 0x0024) */
+
+#define BIT_SHIFT_XTAL_DRV_RF2 15
+#define BIT_MASK_XTAL_DRV_RF2 0x3
+#define BIT_XTAL_DRV_RF2(x)                                                    \
+	(((x) & BIT_MASK_XTAL_DRV_RF2) << BIT_SHIFT_XTAL_DRV_RF2)
+#define BITS_XTAL_DRV_RF2 (BIT_MASK_XTAL_DRV_RF2 << BIT_SHIFT_XTAL_DRV_RF2)
+#define BIT_CLEAR_XTAL_DRV_RF2(x) ((x) & (~BITS_XTAL_DRV_RF2))
+#define BIT_GET_XTAL_DRV_RF2(x)                                                \
+	(((x) >> BIT_SHIFT_XTAL_DRV_RF2) & BIT_MASK_XTAL_DRV_RF2)
+#define BIT_SET_XTAL_DRV_RF2(x, v)                                             \
+	(BIT_CLEAR_XTAL_DRV_RF2(x) | BIT_XTAL_DRV_RF2(v))
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_AFE_CTRL1				(Offset 0x0024) */
+
+#define BIT_XTAL_GAFE BIT(15)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_AFE_CTRL1				(Offset 0x0024) */
+
+#define BIT_XTAL_RF_GATE BIT(14)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_AFE_CTRL1				(Offset 0x0024) */
+
+#define BIT_SHIFT_XTAL_DDRV_1_TO_0 13
+#define BIT_MASK_XTAL_DDRV_1_TO_0 0x3
+#define BIT_XTAL_DDRV_1_TO_0(x)                                                \
+	(((x) & BIT_MASK_XTAL_DDRV_1_TO_0) << BIT_SHIFT_XTAL_DDRV_1_TO_0)
+#define BITS_XTAL_DDRV_1_TO_0                                                  \
+	(BIT_MASK_XTAL_DDRV_1_TO_0 << BIT_SHIFT_XTAL_DDRV_1_TO_0)
+#define BIT_CLEAR_XTAL_DDRV_1_TO_0(x) ((x) & (~BITS_XTAL_DDRV_1_TO_0))
+#define BIT_GET_XTAL_DDRV_1_TO_0(x)                                            \
+	(((x) >> BIT_SHIFT_XTAL_DDRV_1_TO_0) & BIT_MASK_XTAL_DDRV_1_TO_0)
+#define BIT_SET_XTAL_DDRV_1_TO_0(x, v)                                         \
+	(BIT_CLEAR_XTAL_DDRV_1_TO_0(x) | BIT_XTAL_DDRV_1_TO_0(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_AFE_CTRL1				(Offset 0x0024) */
+
+#define BIT_SHIFT_XTAL_AFE_DRV 12
+#define BIT_MASK_XTAL_AFE_DRV 0x3
+#define BIT_XTAL_AFE_DRV(x)                                                    \
+	(((x) & BIT_MASK_XTAL_AFE_DRV) << BIT_SHIFT_XTAL_AFE_DRV)
+#define BITS_XTAL_AFE_DRV (BIT_MASK_XTAL_AFE_DRV << BIT_SHIFT_XTAL_AFE_DRV)
+#define BIT_CLEAR_XTAL_AFE_DRV(x) ((x) & (~BITS_XTAL_AFE_DRV))
+#define BIT_GET_XTAL_AFE_DRV(x)                                                \
+	(((x) >> BIT_SHIFT_XTAL_AFE_DRV) & BIT_MASK_XTAL_AFE_DRV)
+#define BIT_SET_XTAL_AFE_DRV(x, v)                                             \
+	(BIT_CLEAR_XTAL_AFE_DRV(x) | BIT_XTAL_AFE_DRV(v))
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+
+/* 2 REG_AFE_CTRL1				(Offset 0x0024) */
+
+#define BIT_XTAL_DELAY_DIGI BIT(12)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_AFE_CTRL1				(Offset 0x0024) */
+
+#define BIT_XTAL_GUSB BIT(12)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_AFE_CTRL1				(Offset 0x0024) */
+
+#define BIT_XTAL_GATE_AFE BIT(11)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+
+/* 2 REG_AFE_CTRL1				(Offset 0x0024) */
+
+#define BIT_XTAL_DELAY_USB BIT(11)
+#define BIT_XTAL_DELAY_AFE BIT(10)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_AFE_CTRL1				(Offset 0x0024) */
+
+#define BIT_SHIFT_XTAL_USB_DRV 9
+#define BIT_MASK_XTAL_USB_DRV 0x3
+#define BIT_XTAL_USB_DRV(x)                                                    \
+	(((x) & BIT_MASK_XTAL_USB_DRV) << BIT_SHIFT_XTAL_USB_DRV)
+#define BITS_XTAL_USB_DRV (BIT_MASK_XTAL_USB_DRV << BIT_SHIFT_XTAL_USB_DRV)
+#define BIT_CLEAR_XTAL_USB_DRV(x) ((x) & (~BITS_XTAL_USB_DRV))
+#define BIT_GET_XTAL_USB_DRV(x)                                                \
+	(((x) >> BIT_SHIFT_XTAL_USB_DRV) & BIT_MASK_XTAL_USB_DRV)
+#define BIT_SET_XTAL_USB_DRV(x, v)                                             \
+	(BIT_CLEAR_XTAL_USB_DRV(x) | BIT_XTAL_USB_DRV(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_AFE_CTRL1				(Offset 0x0024) */
+
+#define BIT_XTAL_LP_V1 BIT(9)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_AFE_CTRL1				(Offset 0x0024) */
+
+#define BIT_XTAL_GATE_USB BIT(8)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_AFE_CTRL1				(Offset 0x0024) */
+
+#define BIT_XTAL_GM_SEP_V1 BIT(8)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_AFE_CTRL1				(Offset 0x0024) */
+
+#define BIT_SHIFT_XTAL_GMN_3_TO_0 8
+#define BIT_MASK_XTAL_GMN_3_TO_0 0xf
+#define BIT_XTAL_GMN_3_TO_0(x)                                                 \
+	(((x) & BIT_MASK_XTAL_GMN_3_TO_0) << BIT_SHIFT_XTAL_GMN_3_TO_0)
+#define BITS_XTAL_GMN_3_TO_0                                                   \
+	(BIT_MASK_XTAL_GMN_3_TO_0 << BIT_SHIFT_XTAL_GMN_3_TO_0)
+#define BIT_CLEAR_XTAL_GMN_3_TO_0(x) ((x) & (~BITS_XTAL_GMN_3_TO_0))
+#define BIT_GET_XTAL_GMN_3_TO_0(x)                                             \
+	(((x) >> BIT_SHIFT_XTAL_GMN_3_TO_0) & BIT_MASK_XTAL_GMN_3_TO_0)
+#define BIT_SET_XTAL_GMN_3_TO_0(x, v)                                          \
+	(BIT_CLEAR_XTAL_GMN_3_TO_0(x) | BIT_XTAL_GMN_3_TO_0(v))
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_AFE_CTRL1				(Offset 0x0024) */
+
+#define BIT_XTAL_LDO_VREF_V1 BIT(7)
+
+#endif
+
+#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+
+/* 2 REG_AFE_CTRL1				(Offset 0x0024) */
+
+#define BIT_SHIFT_XTAL_LDO_VREF 7
+#define BIT_MASK_XTAL_LDO_VREF 0x7
+#define BIT_XTAL_LDO_VREF(x)                                                   \
+	(((x) & BIT_MASK_XTAL_LDO_VREF) << BIT_SHIFT_XTAL_LDO_VREF)
+#define BITS_XTAL_LDO_VREF (BIT_MASK_XTAL_LDO_VREF << BIT_SHIFT_XTAL_LDO_VREF)
+#define BIT_CLEAR_XTAL_LDO_VREF(x) ((x) & (~BITS_XTAL_LDO_VREF))
+#define BIT_GET_XTAL_LDO_VREF(x)                                               \
+	(((x) >> BIT_SHIFT_XTAL_LDO_VREF) & BIT_MASK_XTAL_LDO_VREF)
+#define BIT_SET_XTAL_LDO_VREF(x, v)                                            \
+	(BIT_CLEAR_XTAL_LDO_VREF(x) | BIT_XTAL_LDO_VREF(v))
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+
+/* 2 REG_AFE_CTRL1				(Offset 0x0024) */
+
+#define BIT_XTAL_XQSEL_RF BIT(6)
+#define BIT_XTAL_XQSEL BIT(5)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_AFE_CTRL1				(Offset 0x0024) */
+
+#define BIT_SHIFT_XTAL_GMP 4
+#define BIT_MASK_XTAL_GMP 0xf
+#define BIT_XTAL_GMP(x) (((x) & BIT_MASK_XTAL_GMP) << BIT_SHIFT_XTAL_GMP)
+#define BITS_XTAL_GMP (BIT_MASK_XTAL_GMP << BIT_SHIFT_XTAL_GMP)
+#define BIT_CLEAR_XTAL_GMP(x) ((x) & (~BITS_XTAL_GMP))
+#define BIT_GET_XTAL_GMP(x) (((x) >> BIT_SHIFT_XTAL_GMP) & BIT_MASK_XTAL_GMP)
+#define BIT_SET_XTAL_GMP(x, v) (BIT_CLEAR_XTAL_GMP(x) | BIT_XTAL_GMP(v))
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_AFE_CTRL1				(Offset 0x0024) */
+
+#define BIT_SHIFT_XTAL_GMP_3_TO_0 4
+#define BIT_MASK_XTAL_GMP_3_TO_0 0xf
+#define BIT_XTAL_GMP_3_TO_0(x)                                                 \
+	(((x) & BIT_MASK_XTAL_GMP_3_TO_0) << BIT_SHIFT_XTAL_GMP_3_TO_0)
+#define BITS_XTAL_GMP_3_TO_0                                                   \
+	(BIT_MASK_XTAL_GMP_3_TO_0 << BIT_SHIFT_XTAL_GMP_3_TO_0)
+#define BIT_CLEAR_XTAL_GMP_3_TO_0(x) ((x) & (~BITS_XTAL_GMP_3_TO_0))
+#define BIT_GET_XTAL_GMP_3_TO_0(x)                                             \
+	(((x) >> BIT_SHIFT_XTAL_GMP_3_TO_0) & BIT_MASK_XTAL_GMP_3_TO_0)
+#define BIT_SET_XTAL_GMP_3_TO_0(x, v)                                          \
+	(BIT_CLEAR_XTAL_GMP_3_TO_0(x) | BIT_XTAL_GMP_3_TO_0(v))
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+
+/* 2 REG_AFE_CTRL1				(Offset 0x0024) */
+
+#define BIT_SHIFT_XTAL_GMN_V2 3
+#define BIT_MASK_XTAL_GMN_V2 0x3
+#define BIT_XTAL_GMN_V2(x)                                                     \
+	(((x) & BIT_MASK_XTAL_GMN_V2) << BIT_SHIFT_XTAL_GMN_V2)
+#define BITS_XTAL_GMN_V2 (BIT_MASK_XTAL_GMN_V2 << BIT_SHIFT_XTAL_GMN_V2)
+#define BIT_CLEAR_XTAL_GMN_V2(x) ((x) & (~BITS_XTAL_GMN_V2))
+#define BIT_GET_XTAL_GMN_V2(x)                                                 \
+	(((x) >> BIT_SHIFT_XTAL_GMN_V2) & BIT_MASK_XTAL_GMN_V2)
+#define BIT_SET_XTAL_GMN_V2(x, v)                                              \
+	(BIT_CLEAR_XTAL_GMN_V2(x) | BIT_XTAL_GMN_V2(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_AFE_CTRL1				(Offset 0x0024) */
+
+#define BIT_SHIFT_XTAL_GMN_V1 3
+#define BIT_MASK_XTAL_GMN_V1 0x3
+#define BIT_XTAL_GMN_V1(x)                                                     \
+	(((x) & BIT_MASK_XTAL_GMN_V1) << BIT_SHIFT_XTAL_GMN_V1)
+#define BITS_XTAL_GMN_V1 (BIT_MASK_XTAL_GMN_V1 << BIT_SHIFT_XTAL_GMN_V1)
+#define BIT_CLEAR_XTAL_GMN_V1(x) ((x) & (~BITS_XTAL_GMN_V1))
+#define BIT_GET_XTAL_GMN_V1(x)                                                 \
+	(((x) >> BIT_SHIFT_XTAL_GMN_V1) & BIT_MASK_XTAL_GMN_V1)
+#define BIT_SET_XTAL_GMN_V1(x, v)                                              \
+	(BIT_CLEAR_XTAL_GMN_V1(x) | BIT_XTAL_GMN_V1(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_AFE_CTRL1				(Offset 0x0024) */
+
+#define BIT_SHIFT_XTAL_LDO_VCM 2
+#define BIT_MASK_XTAL_LDO_VCM 0x3
+#define BIT_XTAL_LDO_VCM(x)                                                    \
+	(((x) & BIT_MASK_XTAL_LDO_VCM) << BIT_SHIFT_XTAL_LDO_VCM)
+#define BITS_XTAL_LDO_VCM (BIT_MASK_XTAL_LDO_VCM << BIT_SHIFT_XTAL_LDO_VCM)
+#define BIT_CLEAR_XTAL_LDO_VCM(x) ((x) & (~BITS_XTAL_LDO_VCM))
+#define BIT_GET_XTAL_LDO_VCM(x)                                                \
+	(((x) >> BIT_SHIFT_XTAL_LDO_VCM) & BIT_MASK_XTAL_LDO_VCM)
+#define BIT_SET_XTAL_LDO_VCM(x, v)                                             \
+	(BIT_CLEAR_XTAL_LDO_VCM(x) | BIT_XTAL_LDO_VCM(v))
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_AFE_CTRL1				(Offset 0x0024) */
+
+#define BIT_SHIFT_DRV_LDO_VCM_1_TO_0 2
+#define BIT_MASK_DRV_LDO_VCM_1_TO_0 0x3
+#define BIT_DRV_LDO_VCM_1_TO_0(x)                                              \
+	(((x) & BIT_MASK_DRV_LDO_VCM_1_TO_0) << BIT_SHIFT_DRV_LDO_VCM_1_TO_0)
+#define BITS_DRV_LDO_VCM_1_TO_0                                                \
+	(BIT_MASK_DRV_LDO_VCM_1_TO_0 << BIT_SHIFT_DRV_LDO_VCM_1_TO_0)
+#define BIT_CLEAR_DRV_LDO_VCM_1_TO_0(x) ((x) & (~BITS_DRV_LDO_VCM_1_TO_0))
+#define BIT_GET_DRV_LDO_VCM_1_TO_0(x)                                          \
+	(((x) >> BIT_SHIFT_DRV_LDO_VCM_1_TO_0) & BIT_MASK_DRV_LDO_VCM_1_TO_0)
+#define BIT_SET_DRV_LDO_VCM_1_TO_0(x, v)                                       \
+	(BIT_CLEAR_DRV_LDO_VCM_1_TO_0(x) | BIT_DRV_LDO_VCM_1_TO_0(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT)
+
+/* 2 REG_AFE_CTRL1				(Offset 0x0024) */
+
+#define BIT_XTAL_DUMMY BIT(1)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+
+/* 2 REG_AFE_CTRL1				(Offset 0x0024) */
+
+#define BIT_SHIFT_XTAL_GMP_V2 1
+#define BIT_MASK_XTAL_GMP_V2 0x3
+#define BIT_XTAL_GMP_V2(x)                                                     \
+	(((x) & BIT_MASK_XTAL_GMP_V2) << BIT_SHIFT_XTAL_GMP_V2)
+#define BITS_XTAL_GMP_V2 (BIT_MASK_XTAL_GMP_V2 << BIT_SHIFT_XTAL_GMP_V2)
+#define BIT_CLEAR_XTAL_GMP_V2(x) ((x) & (~BITS_XTAL_GMP_V2))
+#define BIT_GET_XTAL_GMP_V2(x)                                                 \
+	(((x) >> BIT_SHIFT_XTAL_GMP_V2) & BIT_MASK_XTAL_GMP_V2)
+#define BIT_SET_XTAL_GMP_V2(x, v)                                              \
+	(BIT_CLEAR_XTAL_GMP_V2(x) | BIT_XTAL_GMP_V2(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_AFE_CTRL1				(Offset 0x0024) */
+
+#define BIT_SHIFT_XTAL_GMP_V1 1
+#define BIT_MASK_XTAL_GMP_V1 0x3
+#define BIT_XTAL_GMP_V1(x)                                                     \
+	(((x) & BIT_MASK_XTAL_GMP_V1) << BIT_SHIFT_XTAL_GMP_V1)
+#define BITS_XTAL_GMP_V1 (BIT_MASK_XTAL_GMP_V1 << BIT_SHIFT_XTAL_GMP_V1)
+#define BIT_CLEAR_XTAL_GMP_V1(x) ((x) & (~BITS_XTAL_GMP_V1))
+#define BIT_GET_XTAL_GMP_V1(x)                                                 \
+	(((x) >> BIT_SHIFT_XTAL_GMP_V1) & BIT_MASK_XTAL_GMP_V1)
+#define BIT_SET_XTAL_GMP_V1(x, v)                                              \
+	(BIT_CLEAR_XTAL_GMP_V1(x) | BIT_XTAL_GMP_V1(v))
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_AFE_CTRL1				(Offset 0x0024) */
+
+#define BIT_XQSEL_RF_INITIAL_V1 BIT(1)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_AFE_CTRL1				(Offset 0x0024) */
+
+#define BIT_XTAL_EN BIT(0)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_SDIO_FREE_TXPG2			(Offset 0x10250024) */
+
+#define BIT_SHIFT_LOW_FREEPG_V1 0
+#define BIT_MASK_LOW_FREEPG_V1 0xfff
+#define BIT_LOW_FREEPG_V1(x)                                                   \
+	(((x) & BIT_MASK_LOW_FREEPG_V1) << BIT_SHIFT_LOW_FREEPG_V1)
+#define BITS_LOW_FREEPG_V1 (BIT_MASK_LOW_FREEPG_V1 << BIT_SHIFT_LOW_FREEPG_V1)
+#define BIT_CLEAR_LOW_FREEPG_V1(x) ((x) & (~BITS_LOW_FREEPG_V1))
+#define BIT_GET_LOW_FREEPG_V1(x)                                               \
+	(((x) >> BIT_SHIFT_LOW_FREEPG_V1) & BIT_MASK_LOW_FREEPG_V1)
+#define BIT_SET_LOW_FREEPG_V1(x, v)                                            \
+	(BIT_CLEAR_LOW_FREEPG_V1(x) | BIT_LOW_FREEPG_V1(v))
+
+#endif
+
+#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+
+/* 2 REG_AFE_CTRL2				(Offset 0x0028) */
+
+#define BIT_SHIFT_REG_C3_V4 30
+#define BIT_MASK_REG_C3_V4 0x3
+#define BIT_REG_C3_V4(x) (((x) & BIT_MASK_REG_C3_V4) << BIT_SHIFT_REG_C3_V4)
+#define BITS_REG_C3_V4 (BIT_MASK_REG_C3_V4 << BIT_SHIFT_REG_C3_V4)
+#define BIT_CLEAR_REG_C3_V4(x) ((x) & (~BITS_REG_C3_V4))
+#define BIT_GET_REG_C3_V4(x) (((x) >> BIT_SHIFT_REG_C3_V4) & BIT_MASK_REG_C3_V4)
+#define BIT_SET_REG_C3_V4(x, v) (BIT_CLEAR_REG_C3_V4(x) | BIT_REG_C3_V4(v))
+
+#define BIT_REG_CP_BIT1 BIT(29)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_AFE_CTRL2				(Offset 0x0028) */
+
+#define BIT_SHIFT_XTAL_GMN 28
+#define BIT_MASK_XTAL_GMN 0xf
+#define BIT_XTAL_GMN(x) (((x) & BIT_MASK_XTAL_GMN) << BIT_SHIFT_XTAL_GMN)
+#define BITS_XTAL_GMN (BIT_MASK_XTAL_GMN << BIT_SHIFT_XTAL_GMN)
+#define BIT_CLEAR_XTAL_GMN(x) ((x) & (~BITS_XTAL_GMN))
+#define BIT_GET_XTAL_GMN(x) (((x) >> BIT_SHIFT_XTAL_GMN) & BIT_MASK_XTAL_GMN)
+#define BIT_SET_XTAL_GMN(x, v) (BIT_CLEAR_XTAL_GMN(x) | BIT_XTAL_GMN(v))
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_AFE_CTRL2				(Offset 0x0028) */
+
+#define BIT_SHIFT_IOOFFSET_3_TO_0 28
+#define BIT_MASK_IOOFFSET_3_TO_0 0xf
+#define BIT_IOOFFSET_3_TO_0(x)                                                 \
+	(((x) & BIT_MASK_IOOFFSET_3_TO_0) << BIT_SHIFT_IOOFFSET_3_TO_0)
+#define BITS_IOOFFSET_3_TO_0                                                   \
+	(BIT_MASK_IOOFFSET_3_TO_0 << BIT_SHIFT_IOOFFSET_3_TO_0)
+#define BIT_CLEAR_IOOFFSET_3_TO_0(x) ((x) & (~BITS_IOOFFSET_3_TO_0))
+#define BIT_GET_IOOFFSET_3_TO_0(x)                                             \
+	(((x) >> BIT_SHIFT_IOOFFSET_3_TO_0) & BIT_MASK_IOOFFSET_3_TO_0)
+#define BIT_SET_IOOFFSET_3_TO_0(x, v)                                          \
+	(BIT_CLEAR_IOOFFSET_3_TO_0(x) | BIT_IOOFFSET_3_TO_0(v))
+
+#define BIT_REG_FREF_SEL_BIT3_V1 BIT(27)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_AFE_CTRL2				(Offset 0x0028) */
+
+#define BIT_SHIFT_REG_VO_AD 26
+#define BIT_MASK_REG_VO_AD 0x3
+#define BIT_REG_VO_AD(x) (((x) & BIT_MASK_REG_VO_AD) << BIT_SHIFT_REG_VO_AD)
+#define BITS_REG_VO_AD (BIT_MASK_REG_VO_AD << BIT_SHIFT_REG_VO_AD)
+#define BIT_CLEAR_REG_VO_AD(x) ((x) & (~BITS_REG_VO_AD))
+#define BIT_GET_REG_VO_AD(x) (((x) >> BIT_SHIFT_REG_VO_AD) & BIT_MASK_REG_VO_AD)
+#define BIT_SET_REG_VO_AD(x, v) (BIT_CLEAR_REG_VO_AD(x) | BIT_REG_VO_AD(v))
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_AFE_CTRL2				(Offset 0x0028) */
+
+#define BIT_SHIFT_RS_SET 26
+#define BIT_MASK_RS_SET 0x7
+#define BIT_RS_SET(x) (((x) & BIT_MASK_RS_SET) << BIT_SHIFT_RS_SET)
+#define BITS_RS_SET (BIT_MASK_RS_SET << BIT_SHIFT_RS_SET)
+#define BIT_CLEAR_RS_SET(x) ((x) & (~BITS_RS_SET))
+#define BIT_GET_RS_SET(x) (((x) >> BIT_SHIFT_RS_SET) & BIT_MASK_RS_SET)
+#define BIT_SET_RS_SET(x, v) (BIT_CLEAR_RS_SET(x) | BIT_RS_SET(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_AFE_CTRL2				(Offset 0x0028) */
+
+#define BIT_SHIFT_RS_SET_V2 26
+#define BIT_MASK_RS_SET_V2 0x7
+#define BIT_RS_SET_V2(x) (((x) & BIT_MASK_RS_SET_V2) << BIT_SHIFT_RS_SET_V2)
+#define BITS_RS_SET_V2 (BIT_MASK_RS_SET_V2 << BIT_SHIFT_RS_SET_V2)
+#define BIT_CLEAR_RS_SET_V2(x) ((x) & (~BITS_RS_SET_V2))
+#define BIT_GET_RS_SET_V2(x) (((x) >> BIT_SHIFT_RS_SET_V2) & BIT_MASK_RS_SET_V2)
+#define BIT_SET_RS_SET_V2(x, v) (BIT_CLEAR_RS_SET_V2(x) | BIT_RS_SET_V2(v))
+
+#endif
+
+#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+
+/* 2 REG_AFE_CTRL2				(Offset 0x0028) */
+
+#define BIT_SHIFT_REG_RS_V4 26
+#define BIT_MASK_REG_RS_V4 0x7
+#define BIT_REG_RS_V4(x) (((x) & BIT_MASK_REG_RS_V4) << BIT_SHIFT_REG_RS_V4)
+#define BITS_REG_RS_V4 (BIT_MASK_REG_RS_V4 << BIT_SHIFT_REG_RS_V4)
+#define BIT_CLEAR_REG_RS_V4(x) ((x) & (~BITS_REG_RS_V4))
+#define BIT_GET_REG_RS_V4(x) (((x) >> BIT_SHIFT_REG_RS_V4) & BIT_MASK_REG_RS_V4)
+#define BIT_SET_REG_RS_V4(x, v) (BIT_CLEAR_REG_RS_V4(x) | BIT_REG_RS_V4(v))
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_AFE_CTRL2				(Offset 0x0028) */
+
+#define BIT_SHIFT_V12ADJ_V1 25
+#define BIT_MASK_V12ADJ_V1 0x3
+#define BIT_V12ADJ_V1(x) (((x) & BIT_MASK_V12ADJ_V1) << BIT_SHIFT_V12ADJ_V1)
+#define BITS_V12ADJ_V1 (BIT_MASK_V12ADJ_V1 << BIT_SHIFT_V12ADJ_V1)
+#define BIT_CLEAR_V12ADJ_V1(x) ((x) & (~BITS_V12ADJ_V1))
+#define BIT_GET_V12ADJ_V1(x) (((x) >> BIT_SHIFT_V12ADJ_V1) & BIT_MASK_V12ADJ_V1)
+#define BIT_SET_V12ADJ_V1(x, v) (BIT_CLEAR_V12ADJ_V1(x) | BIT_V12ADJ_V1(v))
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_SDIO_OQT_FREE_TXPG_V1		(Offset 0x10250028) */
+
+#define BIT_SHIFT_NOAC_OQT_FREEPG_V1 24
+#define BIT_MASK_NOAC_OQT_FREEPG_V1 0xff
+#define BIT_NOAC_OQT_FREEPG_V1(x)                                              \
+	(((x) & BIT_MASK_NOAC_OQT_FREEPG_V1) << BIT_SHIFT_NOAC_OQT_FREEPG_V1)
+#define BITS_NOAC_OQT_FREEPG_V1                                                \
+	(BIT_MASK_NOAC_OQT_FREEPG_V1 << BIT_SHIFT_NOAC_OQT_FREEPG_V1)
+#define BIT_CLEAR_NOAC_OQT_FREEPG_V1(x) ((x) & (~BITS_NOAC_OQT_FREEPG_V1))
+#define BIT_GET_NOAC_OQT_FREEPG_V1(x)                                          \
+	(((x) >> BIT_SHIFT_NOAC_OQT_FREEPG_V1) & BIT_MASK_NOAC_OQT_FREEPG_V1)
+#define BIT_SET_NOAC_OQT_FREEPG_V1(x, v)                                       \
+	(BIT_CLEAR_NOAC_OQT_FREEPG_V1(x) | BIT_NOAC_OQT_FREEPG_V1(v))
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_AFE_CTRL2				(Offset 0x0028) */
+
+#define BIT_PS_EN BIT(24)
+
+#endif
+
+#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+
+/* 2 REG_AFE_CTRL2				(Offset 0x0028) */
+
+#define BIT_SHIFT_REG__CS 24
+#define BIT_MASK_REG__CS 0x3
+#define BIT_REG__CS(x) (((x) & BIT_MASK_REG__CS) << BIT_SHIFT_REG__CS)
+#define BITS_REG__CS (BIT_MASK_REG__CS << BIT_SHIFT_REG__CS)
+#define BIT_CLEAR_REG__CS(x) ((x) & (~BITS_REG__CS))
+#define BIT_GET_REG__CS(x) (((x) >> BIT_SHIFT_REG__CS) & BIT_MASK_REG__CS)
+#define BIT_SET_REG__CS(x, v) (BIT_CLEAR_REG__CS(x) | BIT_REG__CS(v))
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_AFE_CTRL2				(Offset 0x0028) */
+
+#define BIT_EN_CK320M_V1 BIT(23)
+#define BIT_AGPIO BIT(22)
+#define BIT_REG_EDGE_SEL_V1 BIT(21)
+
+#endif
+
+#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+
+/* 2 REG_AFE_CTRL2				(Offset 0x0028) */
+
+#define BIT_SHIFT_REG_CP_OFFSET 21
+#define BIT_MASK_REG_CP_OFFSET 0x7
+#define BIT_REG_CP_OFFSET(x)                                                   \
+	(((x) & BIT_MASK_REG_CP_OFFSET) << BIT_SHIFT_REG_CP_OFFSET)
+#define BITS_REG_CP_OFFSET (BIT_MASK_REG_CP_OFFSET << BIT_SHIFT_REG_CP_OFFSET)
+#define BIT_CLEAR_REG_CP_OFFSET(x) ((x) & (~BITS_REG_CP_OFFSET))
+#define BIT_GET_REG_CP_OFFSET(x)                                               \
+	(((x) >> BIT_SHIFT_REG_CP_OFFSET) & BIT_MASK_REG_CP_OFFSET)
+#define BIT_SET_REG_CP_OFFSET(x, v)                                            \
+	(BIT_CLEAR_REG_CP_OFFSET(x) | BIT_REG_CP_OFFSET(v))
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_AFE_CTRL2				(Offset 0x0028) */
+
+#define BIT_REG_VCO_BIAS_0 BIT(20)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+
+/* 2 REG_AFE_CTRL2				(Offset 0x0028) */
+
+#define BIT_SHIFT_CP_BIAS 18
+#define BIT_MASK_CP_BIAS 0x7
+#define BIT_CP_BIAS(x) (((x) & BIT_MASK_CP_BIAS) << BIT_SHIFT_CP_BIAS)
+#define BITS_CP_BIAS (BIT_MASK_CP_BIAS << BIT_SHIFT_CP_BIAS)
+#define BIT_CLEAR_CP_BIAS(x) ((x) & (~BITS_CP_BIAS))
+#define BIT_GET_CP_BIAS(x) (((x) >> BIT_SHIFT_CP_BIAS) & BIT_MASK_CP_BIAS)
+#define BIT_SET_CP_BIAS(x, v) (BIT_CLEAR_CP_BIAS(x) | BIT_CP_BIAS(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_AFE_CTRL2				(Offset 0x0028) */
+
+#define BIT_SHIFT_CP_BIAS_V2 18
+#define BIT_MASK_CP_BIAS_V2 0x7
+#define BIT_CP_BIAS_V2(x) (((x) & BIT_MASK_CP_BIAS_V2) << BIT_SHIFT_CP_BIAS_V2)
+#define BITS_CP_BIAS_V2 (BIT_MASK_CP_BIAS_V2 << BIT_SHIFT_CP_BIAS_V2)
+#define BIT_CLEAR_CP_BIAS_V2(x) ((x) & (~BITS_CP_BIAS_V2))
+#define BIT_GET_CP_BIAS_V2(x)                                                  \
+	(((x) >> BIT_SHIFT_CP_BIAS_V2) & BIT_MASK_CP_BIAS_V2)
+#define BIT_SET_CP_BIAS_V2(x, v) (BIT_CLEAR_CP_BIAS_V2(x) | BIT_CP_BIAS_V2(v))
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_AFE_CTRL2				(Offset 0x0028) */
+
+#define BIT_SHIFT_REG_PLLBIAS_2_TO_0_V1 17
+#define BIT_MASK_REG_PLLBIAS_2_TO_0_V1 0x7
+#define BIT_REG_PLLBIAS_2_TO_0_V1(x)                                           \
+	(((x) & BIT_MASK_REG_PLLBIAS_2_TO_0_V1)                                \
+	 << BIT_SHIFT_REG_PLLBIAS_2_TO_0_V1)
+#define BITS_REG_PLLBIAS_2_TO_0_V1                                             \
+	(BIT_MASK_REG_PLLBIAS_2_TO_0_V1 << BIT_SHIFT_REG_PLLBIAS_2_TO_0_V1)
+#define BIT_CLEAR_REG_PLLBIAS_2_TO_0_V1(x) ((x) & (~BITS_REG_PLLBIAS_2_TO_0_V1))
+#define BIT_GET_REG_PLLBIAS_2_TO_0_V1(x)                                       \
+	(((x) >> BIT_SHIFT_REG_PLLBIAS_2_TO_0_V1) &                            \
+	 BIT_MASK_REG_PLLBIAS_2_TO_0_V1)
+#define BIT_SET_REG_PLLBIAS_2_TO_0_V1(x, v)                                    \
+	(BIT_CLEAR_REG_PLLBIAS_2_TO_0_V1(x) | BIT_REG_PLLBIAS_2_TO_0_V1(v))
+
+#endif
+
+#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+
+/* 2 REG_AFE_CTRL2				(Offset 0x0028) */
+
+#define BIT_REG_IDOUBLE_V2 BIT(17)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_AFE_CTRL2				(Offset 0x0028) */
+
+#define BIT_FREF_SEL BIT(16)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_SDIO_OQT_FREE_TXPG_V1		(Offset 0x10250028) */
+
+#define BIT_SHIFT_AC_OQT_FREEPG_V1 16
+#define BIT_MASK_AC_OQT_FREEPG_V1 0xff
+#define BIT_AC_OQT_FREEPG_V1(x)                                                \
+	(((x) & BIT_MASK_AC_OQT_FREEPG_V1) << BIT_SHIFT_AC_OQT_FREEPG_V1)
+#define BITS_AC_OQT_FREEPG_V1                                                  \
+	(BIT_MASK_AC_OQT_FREEPG_V1 << BIT_SHIFT_AC_OQT_FREEPG_V1)
+#define BIT_CLEAR_AC_OQT_FREEPG_V1(x) ((x) & (~BITS_AC_OQT_FREEPG_V1))
+#define BIT_GET_AC_OQT_FREEPG_V1(x)                                            \
+	(((x) >> BIT_SHIFT_AC_OQT_FREEPG_V1) & BIT_MASK_AC_OQT_FREEPG_V1)
+#define BIT_SET_AC_OQT_FREEPG_V1(x, v)                                         \
+	(BIT_CLEAR_AC_OQT_FREEPG_V1(x) | BIT_AC_OQT_FREEPG_V1(v))
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_AFE_CTRL2				(Offset 0x0028) */
+
+#define BIT_REG_IDOUBLE_V1 BIT(16)
+
+#define BIT_SHIFT_AC_OQT__FREEPG_V1 16
+#define BIT_MASK_AC_OQT__FREEPG_V1 0xff
+#define BIT_AC_OQT__FREEPG_V1(x)                                               \
+	(((x) & BIT_MASK_AC_OQT__FREEPG_V1) << BIT_SHIFT_AC_OQT__FREEPG_V1)
+#define BITS_AC_OQT__FREEPG_V1                                                 \
+	(BIT_MASK_AC_OQT__FREEPG_V1 << BIT_SHIFT_AC_OQT__FREEPG_V1)
+#define BIT_CLEAR_AC_OQT__FREEPG_V1(x) ((x) & (~BITS_AC_OQT__FREEPG_V1))
+#define BIT_GET_AC_OQT__FREEPG_V1(x)                                           \
+	(((x) >> BIT_SHIFT_AC_OQT__FREEPG_V1) & BIT_MASK_AC_OQT__FREEPG_V1)
+#define BIT_SET_AC_OQT__FREEPG_V1(x, v)                                        \
+	(BIT_CLEAR_AC_OQT__FREEPG_V1(x) | BIT_AC_OQT__FREEPG_V1(v))
+
+#endif
+
+#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+
+/* 2 REG_AFE_CTRL2				(Offset 0x0028) */
+
+#define BIT_EN_SYN BIT(16)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_AFE_CTRL2				(Offset 0x0028) */
+
+#define BIT_REG_KVCO_V1 BIT(15)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_AFE_CTRL2				(Offset 0x0028) */
+
+#define BIT_APLL_320_GATEB BIT(14)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+
+/* 2 REG_AFE_CTRL2				(Offset 0x0028) */
+
+#define BIT_SHIFT_MCCO 14
+#define BIT_MASK_MCCO 0x3
+#define BIT_MCCO(x) (((x) & BIT_MASK_MCCO) << BIT_SHIFT_MCCO)
+#define BITS_MCCO (BIT_MASK_MCCO << BIT_SHIFT_MCCO)
+#define BIT_CLEAR_MCCO(x) ((x) & (~BITS_MCCO))
+#define BIT_GET_MCCO(x) (((x) >> BIT_SHIFT_MCCO) & BIT_MASK_MCCO)
+#define BIT_SET_MCCO(x, v) (BIT_CLEAR_MCCO(x) | BIT_MCCO(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_AFE_CTRL2				(Offset 0x0028) */
+
+#define BIT_SHIFT_MCCO_V2 14
+#define BIT_MASK_MCCO_V2 0x3
+#define BIT_MCCO_V2(x) (((x) & BIT_MASK_MCCO_V2) << BIT_SHIFT_MCCO_V2)
+#define BITS_MCCO_V2 (BIT_MASK_MCCO_V2 << BIT_SHIFT_MCCO_V2)
+#define BIT_CLEAR_MCCO_V2(x) ((x) & (~BITS_MCCO_V2))
+#define BIT_GET_MCCO_V2(x) (((x) >> BIT_SHIFT_MCCO_V2) & BIT_MASK_MCCO_V2)
+#define BIT_SET_MCCO_V2(x, v) (BIT_CLEAR_MCCO_V2(x) | BIT_MCCO_V2(v))
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_AFE_CTRL2				(Offset 0x0028) */
+
+#define BIT_REG_VCO_BIAS_1_V1 BIT(14)
+#define BIT_REG_DOGB_V1 BIT(13)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_AFE_CTRL2				(Offset 0x0028) */
+
+#define BIT_SHIFT_CK320_EN 12
+#define BIT_MASK_CK320_EN 0x3
+#define BIT_CK320_EN(x) (((x) & BIT_MASK_CK320_EN) << BIT_SHIFT_CK320_EN)
+#define BITS_CK320_EN (BIT_MASK_CK320_EN << BIT_SHIFT_CK320_EN)
+#define BIT_CLEAR_CK320_EN(x) ((x) & (~BITS_CK320_EN))
+#define BIT_GET_CK320_EN(x) (((x) >> BIT_SHIFT_CK320_EN) & BIT_MASK_CK320_EN)
+#define BIT_SET_CK320_EN(x, v) (BIT_CLEAR_CK320_EN(x) | BIT_CK320_EN(v))
+
+#endif
+
+#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+
+/* 2 REG_AFE_CTRL2				(Offset 0x0028) */
+
+#define BIT_SHIFT_REG_LDO_SEL 12
+#define BIT_MASK_REG_LDO_SEL 0x3
+#define BIT_REG_LDO_SEL(x)                                                     \
+	(((x) & BIT_MASK_REG_LDO_SEL) << BIT_SHIFT_REG_LDO_SEL)
+#define BITS_REG_LDO_SEL (BIT_MASK_REG_LDO_SEL << BIT_SHIFT_REG_LDO_SEL)
+#define BIT_CLEAR_REG_LDO_SEL(x) ((x) & (~BITS_REG_LDO_SEL))
+#define BIT_GET_REG_LDO_SEL(x)                                                 \
+	(((x) >> BIT_SHIFT_REG_LDO_SEL) & BIT_MASK_REG_LDO_SEL)
+#define BIT_SET_REG_LDO_SEL(x, v)                                              \
+	(BIT_CLEAR_REG_LDO_SEL(x) | BIT_REG_LDO_SEL(v))
+
+#define BIT_REG_KVCO_V2 BIT(10)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+
+/* 2 REG_AFE_CTRL2				(Offset 0x0028) */
+
+#define BIT_AGPIO_GPO BIT(9)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_AFE_CTRL2				(Offset 0x0028) */
+
+#define BIT_SHIFT_APLL_BIAS 8
+#define BIT_MASK_APLL_BIAS 0x7
+#define BIT_APLL_BIAS(x) (((x) & BIT_MASK_APLL_BIAS) << BIT_SHIFT_APLL_BIAS)
+#define BITS_APLL_BIAS (BIT_MASK_APLL_BIAS << BIT_SHIFT_APLL_BIAS)
+#define BIT_CLEAR_APLL_BIAS(x) ((x) & (~BITS_APLL_BIAS))
+#define BIT_GET_APLL_BIAS(x) (((x) >> BIT_SHIFT_APLL_BIAS) & BIT_MASK_APLL_BIAS)
+#define BIT_SET_APLL_BIAS(x, v) (BIT_CLEAR_APLL_BIAS(x) | BIT_APLL_BIAS(v))
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+
+/* 2 REG_AFE_CTRL2				(Offset 0x0028) */
+
+#define BIT_SHIFT_AGPIO_DRV 7
+#define BIT_MASK_AGPIO_DRV 0x3
+#define BIT_AGPIO_DRV(x) (((x) & BIT_MASK_AGPIO_DRV) << BIT_SHIFT_AGPIO_DRV)
+#define BITS_AGPIO_DRV (BIT_MASK_AGPIO_DRV << BIT_SHIFT_AGPIO_DRV)
+#define BIT_CLEAR_AGPIO_DRV(x) ((x) & (~BITS_AGPIO_DRV))
+#define BIT_GET_AGPIO_DRV(x) (((x) >> BIT_SHIFT_AGPIO_DRV) & BIT_MASK_AGPIO_DRV)
+#define BIT_SET_AGPIO_DRV(x, v) (BIT_CLEAR_AGPIO_DRV(x) | BIT_AGPIO_DRV(v))
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_AFE_CTRL2				(Offset 0x0028) */
+
+#define BIT_SHIFT_REG_V15_3_TO_0_V1 7
+#define BIT_MASK_REG_V15_3_TO_0_V1 0xf
+#define BIT_REG_V15_3_TO_0_V1(x)                                               \
+	(((x) & BIT_MASK_REG_V15_3_TO_0_V1) << BIT_SHIFT_REG_V15_3_TO_0_V1)
+#define BITS_REG_V15_3_TO_0_V1                                                 \
+	(BIT_MASK_REG_V15_3_TO_0_V1 << BIT_SHIFT_REG_V15_3_TO_0_V1)
+#define BIT_CLEAR_REG_V15_3_TO_0_V1(x) ((x) & (~BITS_REG_V15_3_TO_0_V1))
+#define BIT_GET_REG_V15_3_TO_0_V1(x)                                           \
+	(((x) >> BIT_SHIFT_REG_V15_3_TO_0_V1) & BIT_MASK_REG_V15_3_TO_0_V1)
+#define BIT_SET_REG_V15_3_TO_0_V1(x, v)                                        \
+	(BIT_CLEAR_REG_V15_3_TO_0_V1(x) | BIT_REG_V15_3_TO_0_V1(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_AFE_CTRL2				(Offset 0x0028) */
+
+#define BIT_APLL_KVCO BIT(6)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_AFE_CTRL2				(Offset 0x0028) */
+
+#define BIT_REG_SEL_LDO_PC BIT(6)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_AFE_CTRL2				(Offset 0x0028) */
+
+#define BIT_APLL_WDOGB BIT(4)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_AFE_CTRL2				(Offset 0x0028) */
+
+#define BIT_SHIFT_REG_CC_1_TO_0_V1 4
+#define BIT_MASK_REG_CC_1_TO_0_V1 0x3
+#define BIT_REG_CC_1_TO_0_V1(x)                                                \
+	(((x) & BIT_MASK_REG_CC_1_TO_0_V1) << BIT_SHIFT_REG_CC_1_TO_0_V1)
+#define BITS_REG_CC_1_TO_0_V1                                                  \
+	(BIT_MASK_REG_CC_1_TO_0_V1 << BIT_SHIFT_REG_CC_1_TO_0_V1)
+#define BIT_CLEAR_REG_CC_1_TO_0_V1(x) ((x) & (~BITS_REG_CC_1_TO_0_V1))
+#define BIT_GET_REG_CC_1_TO_0_V1(x)                                            \
+	(((x) >> BIT_SHIFT_REG_CC_1_TO_0_V1) & BIT_MASK_REG_CC_1_TO_0_V1)
+#define BIT_SET_REG_CC_1_TO_0_V1(x, v)                                         \
+	(BIT_CLEAR_REG_CC_1_TO_0_V1(x) | BIT_REG_CC_1_TO_0_V1(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_AFE_CTRL2				(Offset 0x0028) */
+
+#define BIT_APLL_EDGE_SEL BIT(3)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_AFE_CTRL2				(Offset 0x0028) */
+
+#define BIT_CKDELAY_USB_V1 BIT(3)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_AFE_CTRL2				(Offset 0x0028) */
+
+#define BIT_APLL_FREF_SEL_BIT0 BIT(2)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_ANAPARSW_POW_MAC			(Offset 0x0028) */
+
+#define BIT_POW_LDO15 BIT(2)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_AFE_CTRL2				(Offset 0x0028) */
+
+#define BIT_CKDELAY_DIG_V1 BIT(2)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+
+/* 2 REG_AFE_CTRL2				(Offset 0x0028) */
+
+#define BIT_SHIFT_XTAL_CAP_XO 1
+#define BIT_MASK_XTAL_CAP_XO 0x3f
+#define BIT_XTAL_CAP_XO(x)                                                     \
+	(((x) & BIT_MASK_XTAL_CAP_XO) << BIT_SHIFT_XTAL_CAP_XO)
+#define BITS_XTAL_CAP_XO (BIT_MASK_XTAL_CAP_XO << BIT_SHIFT_XTAL_CAP_XO)
+#define BIT_CLEAR_XTAL_CAP_XO(x) ((x) & (~BITS_XTAL_CAP_XO))
+#define BIT_GET_XTAL_CAP_XO(x)                                                 \
+	(((x) >> BIT_SHIFT_XTAL_CAP_XO) & BIT_MASK_XTAL_CAP_XO)
+#define BIT_SET_XTAL_CAP_XO(x, v)                                              \
+	(BIT_CLEAR_XTAL_CAP_XO(x) | BIT_XTAL_CAP_XO(v))
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_ANAPARSW_POW_MAC			(Offset 0x0028) */
+
+#define BIT_POW_SW BIT(1)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_AFE_CTRL2				(Offset 0x0028) */
+
+#define BIT_MPLL_EN BIT(1)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8881A_SUPPORT)
+
+/* 2 REG_AFE_CTRL2				(Offset 0x0028) */
+
+#define BIT_APLL_EN BIT(0)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+
+/* 2 REG_AFE_CTRL2				(Offset 0x0028) */
+
+#define BIT_POW_PLL BIT(0)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_SDIO_OQT_FREE_TXPG_V1		(Offset 0x10250028) */
+
+#define BIT_SHIFT_EXQ_FREEPG_V1 0
+#define BIT_MASK_EXQ_FREEPG_V1 0xfff
+#define BIT_EXQ_FREEPG_V1(x)                                                   \
+	(((x) & BIT_MASK_EXQ_FREEPG_V1) << BIT_SHIFT_EXQ_FREEPG_V1)
+#define BITS_EXQ_FREEPG_V1 (BIT_MASK_EXQ_FREEPG_V1 << BIT_SHIFT_EXQ_FREEPG_V1)
+#define BIT_CLEAR_EXQ_FREEPG_V1(x) ((x) & (~BITS_EXQ_FREEPG_V1))
+#define BIT_GET_EXQ_FREEPG_V1(x)                                               \
+	(((x) >> BIT_SHIFT_EXQ_FREEPG_V1) & BIT_MASK_EXQ_FREEPG_V1)
+#define BIT_SET_EXQ_FREEPG_V1(x, v)                                            \
+	(BIT_CLEAR_EXQ_FREEPG_V1(x) | BIT_EXQ_FREEPG_V1(v))
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_ANAPARSW_POW_MAC			(Offset 0x0028) */
+
+#define BIT_POW_LDO14 BIT(0)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_SDIO_OQT_FREE_TXPG_V1		(Offset 0x10250028) */
+
+#define BIT_SHIFT_EXQ__FREEPG_V1 0
+#define BIT_MASK_EXQ__FREEPG_V1 0xfff
+#define BIT_EXQ__FREEPG_V1(x)                                                  \
+	(((x) & BIT_MASK_EXQ__FREEPG_V1) << BIT_SHIFT_EXQ__FREEPG_V1)
+#define BITS_EXQ__FREEPG_V1                                                    \
+	(BIT_MASK_EXQ__FREEPG_V1 << BIT_SHIFT_EXQ__FREEPG_V1)
+#define BIT_CLEAR_EXQ__FREEPG_V1(x) ((x) & (~BITS_EXQ__FREEPG_V1))
+#define BIT_GET_EXQ__FREEPG_V1(x)                                              \
+	(((x) >> BIT_SHIFT_EXQ__FREEPG_V1) & BIT_MASK_EXQ__FREEPG_V1)
+#define BIT_SET_EXQ__FREEPG_V1(x, v)                                           \
+	(BIT_CLEAR_EXQ__FREEPG_V1(x) | BIT_EXQ__FREEPG_V1(v))
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_ANAPARLDO_POW_MAC			(Offset 0x0029) */
+
+#define BIT_LDOE25_POW_L BIT(0)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_ANAPAR_POW_MAC			(Offset 0x002A) */
+
+#define BIT_REG_STANDBY_L BIT(19)
+#define BIT_PD_REGU_L BIT(18)
+#define BIT_EN_PC_BT_L BIT(17)
+
+#define BIT_SHIFT_REG_LDOADJ_L 13
+#define BIT_MASK_REG_LDOADJ_L 0xf
+#define BIT_REG_LDOADJ_L(x)                                                    \
+	(((x) & BIT_MASK_REG_LDOADJ_L) << BIT_SHIFT_REG_LDOADJ_L)
+#define BITS_REG_LDOADJ_L (BIT_MASK_REG_LDOADJ_L << BIT_SHIFT_REG_LDOADJ_L)
+#define BIT_CLEAR_REG_LDOADJ_L(x) ((x) & (~BITS_REG_LDOADJ_L))
+#define BIT_GET_REG_LDOADJ_L(x)                                                \
+	(((x) >> BIT_SHIFT_REG_LDOADJ_L) & BIT_MASK_REG_LDOADJ_L)
+#define BIT_SET_REG_LDOADJ_L(x, v)                                             \
+	(BIT_CLEAR_REG_LDOADJ_L(x) | BIT_REG_LDOADJ_L(v))
+
+#define BIT_CK12M_EN BIT(11)
+#define BIT_CK12M_SEL BIT(10)
+#define BIT_EN_25_L BIT(9)
+#define BIT_EN_SLEEP BIT(8)
+#define BIT_DUMMY_V4 BIT(7)
+#define BIT_DUMMY_V3 BIT(6)
+#define BIT_DUMMY_V2 BIT(5)
+#define BIT_DUMMY_V1 BIT(4)
+
+#define BIT_SHIFT_LDOH12_V12ADJ_L 4
+#define BIT_MASK_LDOH12_V12ADJ_L 0xf
+#define BIT_LDOH12_V12ADJ_L(x)                                                 \
+	(((x) & BIT_MASK_LDOH12_V12ADJ_L) << BIT_SHIFT_LDOH12_V12ADJ_L)
+#define BITS_LDOH12_V12ADJ_L                                                   \
+	(BIT_MASK_LDOH12_V12ADJ_L << BIT_SHIFT_LDOH12_V12ADJ_L)
+#define BIT_CLEAR_LDOH12_V12ADJ_L(x) ((x) & (~BITS_LDOH12_V12ADJ_L))
+#define BIT_GET_LDOH12_V12ADJ_L(x)                                             \
+	(((x) >> BIT_SHIFT_LDOH12_V12ADJ_L) & BIT_MASK_LDOH12_V12ADJ_L)
+#define BIT_SET_LDOH12_V12ADJ_L(x, v)                                          \
+	(BIT_CLEAR_LDOH12_V12ADJ_L(x) | BIT_LDOH12_V12ADJ_L(v))
+
+#define BIT_POW_PC_LDO_PORT1 BIT(3)
+#define BIT_POW_PC_LDO_PORT0 BIT(2)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_ANAPAR_POW_MAC			(Offset 0x002A) */
+
+#define BIT_POW_PLL_V1 BIT(1)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_ANAPAR_POW_MAC			(Offset 0x002A) */
+
+#define BIT_POW_POWER_CUT_POW_LDO BIT(0)
+
+#define BIT_SHIFT_LDOE25_V12ADJ_L_V1 0
+#define BIT_MASK_LDOE25_V12ADJ_L_V1 0xf
+#define BIT_LDOE25_V12ADJ_L_V1(x)                                              \
+	(((x) & BIT_MASK_LDOE25_V12ADJ_L_V1) << BIT_SHIFT_LDOE25_V12ADJ_L_V1)
+#define BITS_LDOE25_V12ADJ_L_V1                                                \
+	(BIT_MASK_LDOE25_V12ADJ_L_V1 << BIT_SHIFT_LDOE25_V12ADJ_L_V1)
+#define BIT_CLEAR_LDOE25_V12ADJ_L_V1(x) ((x) & (~BITS_LDOE25_V12ADJ_L_V1))
+#define BIT_GET_LDOE25_V12ADJ_L_V1(x)                                          \
+	(((x) >> BIT_SHIFT_LDOE25_V12ADJ_L_V1) & BIT_MASK_LDOE25_V12ADJ_L_V1)
+#define BIT_SET_LDOE25_V12ADJ_L_V1(x, v)                                       \
+	(BIT_CLEAR_LDOE25_V12ADJ_L_V1(x) | BIT_LDOE25_V12ADJ_L_V1(v))
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_ANAPAR_POW_XTAL			(Offset 0x002B) */
+
+#define BIT_PSTIMER_2 BIT(31)
+#define BIT_PSTIMER_1 BIT(30)
+#define BIT_PSTIMER_0 BIT(29)
+#define BIT_TXDMA_START_INT BIT(23)
+#define BIT_TXDMA_STOP_INT BIT(22)
+#define BIT_HISR7_IND BIT(21)
+#define BIT_HISR6_IND BIT(19)
+#define BIT_HISR5_IND BIT(18)
+#define BIT_HISR4_IND BIT(17)
+#define BIT_HISR3_IND BIT(14)
+#define BIT_HISR2_IND BIT(13)
+#define BIT_POW_XTAL BIT(1)
+#define BIT_POW_BG BIT(0)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_AFE_CTRL3				(Offset 0x002C) */
+
+#define BIT_SHIFT_XTAL_RF2_DRV 30
+#define BIT_MASK_XTAL_RF2_DRV 0x3
+#define BIT_XTAL_RF2_DRV(x)                                                    \
+	(((x) & BIT_MASK_XTAL_RF2_DRV) << BIT_SHIFT_XTAL_RF2_DRV)
+#define BITS_XTAL_RF2_DRV (BIT_MASK_XTAL_RF2_DRV << BIT_SHIFT_XTAL_RF2_DRV)
+#define BIT_CLEAR_XTAL_RF2_DRV(x) ((x) & (~BITS_XTAL_RF2_DRV))
+#define BIT_GET_XTAL_RF2_DRV(x)                                                \
+	(((x) >> BIT_SHIFT_XTAL_RF2_DRV) & BIT_MASK_XTAL_RF2_DRV)
+#define BIT_SET_XTAL_RF2_DRV(x, v)                                             \
+	(BIT_CLEAR_XTAL_RF2_DRV(x) | BIT_XTAL_RF2_DRV(v))
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_AFE_CTRL3				(Offset 0x002C) */
+
+#define BIT_REG_REF_SEL_V3 BIT(30)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_AFE_CTRL3				(Offset 0x002C) */
+
+#define BIT_XTAL_GMN_BIT4 BIT(29)
+#define BIT_XTAL_GMP_BIT4 BIT(28)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT)
+
+/* 2 REG_AFE_CTRL3				(Offset 0x002C) */
+
+#define BIT_XQSEL BIT(27)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_AFE_CTRL3				(Offset 0x002C) */
+
+#define BIT_SHIFT_REG_FREF_SEL_2_TO_0 27
+#define BIT_MASK_REG_FREF_SEL_2_TO_0 0x7
+#define BIT_REG_FREF_SEL_2_TO_0(x)                                             \
+	(((x) & BIT_MASK_REG_FREF_SEL_2_TO_0) << BIT_SHIFT_REG_FREF_SEL_2_TO_0)
+#define BITS_REG_FREF_SEL_2_TO_0                                               \
+	(BIT_MASK_REG_FREF_SEL_2_TO_0 << BIT_SHIFT_REG_FREF_SEL_2_TO_0)
+#define BIT_CLEAR_REG_FREF_SEL_2_TO_0(x) ((x) & (~BITS_REG_FREF_SEL_2_TO_0))
+#define BIT_GET_REG_FREF_SEL_2_TO_0(x)                                         \
+	(((x) >> BIT_SHIFT_REG_FREF_SEL_2_TO_0) & BIT_MASK_REG_FREF_SEL_2_TO_0)
+#define BIT_SET_REG_FREF_SEL_2_TO_0(x, v)                                      \
+	(BIT_CLEAR_REG_FREF_SEL_2_TO_0(x) | BIT_REG_FREF_SEL_2_TO_0(v))
+
+#endif
+
+#if (HALMAC_8881A_SUPPORT)
+
+/* 2 REG_AFE_CTRL3				(Offset 0x002C) */
+
+#define BIT_XQSEL_BIT0 BIT(27)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_AFE_CTRL3				(Offset 0x002C) */
+
+#define BIT_APLL_DUMMY BIT(26)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_AFE_CTRL3				(Offset 0x002C) */
+
+#define BIT_SHIFT_XTAL_CADJ_XOUT_5_TO_0_V1 21
+#define BIT_MASK_XTAL_CADJ_XOUT_5_TO_0_V1 0x3f
+#define BIT_XTAL_CADJ_XOUT_5_TO_0_V1(x)                                        \
+	(((x) & BIT_MASK_XTAL_CADJ_XOUT_5_TO_0_V1)                             \
+	 << BIT_SHIFT_XTAL_CADJ_XOUT_5_TO_0_V1)
+#define BITS_XTAL_CADJ_XOUT_5_TO_0_V1                                          \
+	(BIT_MASK_XTAL_CADJ_XOUT_5_TO_0_V1                                     \
+	 << BIT_SHIFT_XTAL_CADJ_XOUT_5_TO_0_V1)
+#define BIT_CLEAR_XTAL_CADJ_XOUT_5_TO_0_V1(x)                                  \
+	((x) & (~BITS_XTAL_CADJ_XOUT_5_TO_0_V1))
+#define BIT_GET_XTAL_CADJ_XOUT_5_TO_0_V1(x)                                    \
+	(((x) >> BIT_SHIFT_XTAL_CADJ_XOUT_5_TO_0_V1) &                         \
+	 BIT_MASK_XTAL_CADJ_XOUT_5_TO_0_V1)
+#define BIT_SET_XTAL_CADJ_XOUT_5_TO_0_V1(x, v)                                 \
+	(BIT_CLEAR_XTAL_CADJ_XOUT_5_TO_0_V1(x) |                               \
+	 BIT_XTAL_CADJ_XOUT_5_TO_0_V1(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_AFE_CTRL3				(Offset 0x002C) */
+
+#define BIT_SHIFT_XTAL_CADJ_XOUT 18
+#define BIT_MASK_XTAL_CADJ_XOUT 0x3f
+#define BIT_XTAL_CADJ_XOUT(x)                                                  \
+	(((x) & BIT_MASK_XTAL_CADJ_XOUT) << BIT_SHIFT_XTAL_CADJ_XOUT)
+#define BITS_XTAL_CADJ_XOUT                                                    \
+	(BIT_MASK_XTAL_CADJ_XOUT << BIT_SHIFT_XTAL_CADJ_XOUT)
+#define BIT_CLEAR_XTAL_CADJ_XOUT(x) ((x) & (~BITS_XTAL_CADJ_XOUT))
+#define BIT_GET_XTAL_CADJ_XOUT(x)                                              \
+	(((x) >> BIT_SHIFT_XTAL_CADJ_XOUT) & BIT_MASK_XTAL_CADJ_XOUT)
+#define BIT_SET_XTAL_CADJ_XOUT(x, v)                                           \
+	(BIT_CLEAR_XTAL_CADJ_XOUT(x) | BIT_XTAL_CADJ_XOUT(v))
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_AFE_CTRL3				(Offset 0x002C) */
+
+#define BIT_SHIFT_XTAL_CADJ_XIN_V2 15
+#define BIT_MASK_XTAL_CADJ_XIN_V2 0x3f
+#define BIT_XTAL_CADJ_XIN_V2(x)                                                \
+	(((x) & BIT_MASK_XTAL_CADJ_XIN_V2) << BIT_SHIFT_XTAL_CADJ_XIN_V2)
+#define BITS_XTAL_CADJ_XIN_V2                                                  \
+	(BIT_MASK_XTAL_CADJ_XIN_V2 << BIT_SHIFT_XTAL_CADJ_XIN_V2)
+#define BIT_CLEAR_XTAL_CADJ_XIN_V2(x) ((x) & (~BITS_XTAL_CADJ_XIN_V2))
+#define BIT_GET_XTAL_CADJ_XIN_V2(x)                                            \
+	(((x) >> BIT_SHIFT_XTAL_CADJ_XIN_V2) & BIT_MASK_XTAL_CADJ_XIN_V2)
+#define BIT_SET_XTAL_CADJ_XIN_V2(x, v)                                         \
+	(BIT_CLEAR_XTAL_CADJ_XIN_V2(x) | BIT_XTAL_CADJ_XIN_V2(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_AFE_CTRL3				(Offset 0x002C) */
+
+#define BIT_SHIFT_XTAL_CADJ_XIN 12
+#define BIT_MASK_XTAL_CADJ_XIN 0x3f
+#define BIT_XTAL_CADJ_XIN(x)                                                   \
+	(((x) & BIT_MASK_XTAL_CADJ_XIN) << BIT_SHIFT_XTAL_CADJ_XIN)
+#define BITS_XTAL_CADJ_XIN (BIT_MASK_XTAL_CADJ_XIN << BIT_SHIFT_XTAL_CADJ_XIN)
+#define BIT_CLEAR_XTAL_CADJ_XIN(x) ((x) & (~BITS_XTAL_CADJ_XIN))
+#define BIT_GET_XTAL_CADJ_XIN(x)                                               \
+	(((x) >> BIT_SHIFT_XTAL_CADJ_XIN) & BIT_MASK_XTAL_CADJ_XIN)
+#define BIT_SET_XTAL_CADJ_XIN(x, v)                                            \
+	(BIT_CLEAR_XTAL_CADJ_XIN(x) | BIT_XTAL_CADJ_XIN(v))
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_AFE_CTRL3				(Offset 0x002C) */
+
+#define BIT_SHIFT_REG_RS_V3 12
+#define BIT_MASK_REG_RS_V3 0x7
+#define BIT_REG_RS_V3(x) (((x) & BIT_MASK_REG_RS_V3) << BIT_SHIFT_REG_RS_V3)
+#define BITS_REG_RS_V3 (BIT_MASK_REG_RS_V3 << BIT_SHIFT_REG_RS_V3)
+#define BIT_CLEAR_REG_RS_V3(x) ((x) & (~BITS_REG_RS_V3))
+#define BIT_GET_REG_RS_V3(x) (((x) >> BIT_SHIFT_REG_RS_V3) & BIT_MASK_REG_RS_V3)
+#define BIT_SET_REG_RS_V3(x, v) (BIT_CLEAR_REG_RS_V3(x) | BIT_REG_RS_V3(v))
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_SDIO_TXPKT_EMPTY			(Offset 0x1025002C) */
+
+#define BIT_SDIO_BCNQ_EMPTY BIT(11)
+#define BIT_SDIO_HQQ_EMPTY BIT(10)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_AFE_CTRL3				(Offset 0x002C) */
+
+#define BIT_SHIFT_REG_RS 9
+#define BIT_MASK_REG_RS 0x7
+#define BIT_REG_RS(x) (((x) & BIT_MASK_REG_RS) << BIT_SHIFT_REG_RS)
+#define BITS_REG_RS (BIT_MASK_REG_RS << BIT_SHIFT_REG_RS)
+#define BIT_CLEAR_REG_RS(x) ((x) & (~BITS_REG_RS))
+#define BIT_GET_REG_RS(x) (((x) >> BIT_SHIFT_REG_RS) & BIT_MASK_REG_RS)
+#define BIT_SET_REG_RS(x, v) (BIT_CLEAR_REG_RS(x) | BIT_REG_RS(v))
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_SDIO_TXPKT_EMPTY			(Offset 0x1025002C) */
+
+#define BIT_SDIO_MQQ_EMPTY BIT(9)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_AFE_CTRL3				(Offset 0x002C) */
+
+#define BIT_SHIFT_REG_R3_V3 9
+#define BIT_MASK_REG_R3_V3 0x7
+#define BIT_REG_R3_V3(x) (((x) & BIT_MASK_REG_R3_V3) << BIT_SHIFT_REG_R3_V3)
+#define BITS_REG_R3_V3 (BIT_MASK_REG_R3_V3 << BIT_SHIFT_REG_R3_V3)
+#define BIT_CLEAR_REG_R3_V3(x) ((x) & (~BITS_REG_R3_V3))
+#define BIT_GET_REG_R3_V3(x) (((x) >> BIT_SHIFT_REG_R3_V3) & BIT_MASK_REG_R3_V3)
+#define BIT_SET_REG_R3_V3(x, v) (BIT_CLEAR_REG_R3_V3(x) | BIT_REG_R3_V3(v))
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_SDIO_TXPKT_EMPTY			(Offset 0x1025002C) */
+
+#define BIT_SDIO_MGQ_CPU_EMPTY BIT(8)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_AFE_CTRL3				(Offset 0x002C) */
+
+#define BIT_SHIFT_PS_V2 7
+#define BIT_MASK_PS_V2 0x7
+#define BIT_PS_V2(x) (((x) & BIT_MASK_PS_V2) << BIT_SHIFT_PS_V2)
+#define BITS_PS_V2 (BIT_MASK_PS_V2 << BIT_SHIFT_PS_V2)
+#define BIT_CLEAR_PS_V2(x) ((x) & (~BITS_PS_V2))
+#define BIT_GET_PS_V2(x) (((x) >> BIT_SHIFT_PS_V2) & BIT_MASK_PS_V2)
+#define BIT_SET_PS_V2(x, v) (BIT_CLEAR_PS_V2(x) | BIT_PS_V2(v))
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_SDIO_TXPKT_EMPTY			(Offset 0x1025002C) */
+
+#define BIT_SDIO_AC7Q_EMPTY BIT(7)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_AFE_CTRL3				(Offset 0x002C) */
+
+#define BIT_SHIFT_REG_CS_V3 7
+#define BIT_MASK_REG_CS_V3 0x3
+#define BIT_REG_CS_V3(x) (((x) & BIT_MASK_REG_CS_V3) << BIT_SHIFT_REG_CS_V3)
+#define BITS_REG_CS_V3 (BIT_MASK_REG_CS_V3 << BIT_SHIFT_REG_CS_V3)
+#define BIT_CLEAR_REG_CS_V3(x) ((x) & (~BITS_REG_CS_V3))
+#define BIT_GET_REG_CS_V3(x) (((x) >> BIT_SHIFT_REG_CS_V3) & BIT_MASK_REG_CS_V3)
+#define BIT_SET_REG_CS_V3(x, v) (BIT_CLEAR_REG_CS_V3(x) | BIT_REG_CS_V3(v))
+
+#endif
+
+#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+
+/* 2 REG_AFE_CTRL3				(Offset 0x002C) */
+
+#define BIT_SHIFT_PS 7
+#define BIT_MASK_PS 0x7
+#define BIT_PS(x) (((x) & BIT_MASK_PS) << BIT_SHIFT_PS)
+#define BITS_PS (BIT_MASK_PS << BIT_SHIFT_PS)
+#define BIT_CLEAR_PS(x) ((x) & (~BITS_PS))
+#define BIT_GET_PS(x) (((x) >> BIT_SHIFT_PS) & BIT_MASK_PS)
+#define BIT_SET_PS(x, v) (BIT_CLEAR_PS(x) | BIT_PS(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_AFE_CTRL3				(Offset 0x002C) */
+
+#define BIT_SHIFT_REG_R3 6
+#define BIT_MASK_REG_R3 0x7
+#define BIT_REG_R3(x) (((x) & BIT_MASK_REG_R3) << BIT_SHIFT_REG_R3)
+#define BITS_REG_R3 (BIT_MASK_REG_R3 << BIT_SHIFT_REG_R3)
+#define BIT_CLEAR_REG_R3(x) ((x) & (~BITS_REG_R3))
+#define BIT_GET_REG_R3(x) (((x) >> BIT_SHIFT_REG_R3) & BIT_MASK_REG_R3)
+#define BIT_SET_REG_R3(x, v) (BIT_CLEAR_REG_R3(x) | BIT_REG_R3(v))
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+
+/* 2 REG_AFE_CTRL3				(Offset 0x002C) */
+
+#define BIT_PSEN BIT(6)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_SDIO_TXPKT_EMPTY			(Offset 0x1025002C) */
+
+#define BIT_SDIO_AC6Q_EMPTY BIT(6)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+
+/* 2 REG_AFE_CTRL3				(Offset 0x002C) */
+
+#define BIT_DOGENB BIT(5)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_SDIO_TXPKT_EMPTY			(Offset 0x1025002C) */
+
+#define BIT_SDIO_AC5Q_EMPTY BIT(5)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT)
+
+/* 2 REG_AFE_CTRL3				(Offset 0x002C) */
+
+#define BIT_SHIFT_REG_CP_V3 5
+#define BIT_MASK_REG_CP_V3 0x3
+#define BIT_REG_CP_V3(x) (((x) & BIT_MASK_REG_CP_V3) << BIT_SHIFT_REG_CP_V3)
+#define BITS_REG_CP_V3 (BIT_MASK_REG_CP_V3 << BIT_SHIFT_REG_CP_V3)
+#define BIT_CLEAR_REG_CP_V3(x) ((x) & (~BITS_REG_CP_V3))
+#define BIT_GET_REG_CP_V3(x) (((x) >> BIT_SHIFT_REG_CP_V3) & BIT_MASK_REG_CP_V3)
+#define BIT_SET_REG_CP_V3(x, v) (BIT_CLEAR_REG_CP_V3(x) | BIT_REG_CP_V3(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_AFE_CTRL3				(Offset 0x002C) */
+
+#define BIT_SHIFT_REG_CS 4
+#define BIT_MASK_REG_CS 0x3
+#define BIT_REG_CS(x) (((x) & BIT_MASK_REG_CS) << BIT_SHIFT_REG_CS)
+#define BITS_REG_CS (BIT_MASK_REG_CS << BIT_SHIFT_REG_CS)
+#define BIT_CLEAR_REG_CS(x) ((x) & (~BITS_REG_CS))
+#define BIT_GET_REG_CS(x) (((x) >> BIT_SHIFT_REG_CS) & BIT_MASK_REG_CS)
+#define BIT_SET_REG_CS(x, v) (BIT_CLEAR_REG_CS(x) | BIT_REG_CS(v))
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_SDIO_TXPKT_EMPTY			(Offset 0x1025002C) */
+
+#define BIT_SDIO_AC4Q_EMPTY BIT(4)
+
+#endif
+
+#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+
+/* 2 REG_AFE_CTRL3				(Offset 0x002C) */
+
+#define BIT_REG_MBIAS BIT(4)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_SDIO_TXPKT_EMPTY			(Offset 0x1025002C) */
+
+#define BIT_SDIO_AC3Q_EMPTY BIT(3)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT)
+
+/* 2 REG_AFE_CTRL3				(Offset 0x002C) */
+
+#define BIT_SHIFT_REG_C3_V3 3
+#define BIT_MASK_REG_C3_V3 0x3
+#define BIT_REG_C3_V3(x) (((x) & BIT_MASK_REG_C3_V3) << BIT_SHIFT_REG_C3_V3)
+#define BITS_REG_C3_V3 (BIT_MASK_REG_C3_V3 << BIT_SHIFT_REG_C3_V3)
+#define BIT_CLEAR_REG_C3_V3(x) ((x) & (~BITS_REG_C3_V3))
+#define BIT_GET_REG_C3_V3(x) (((x) >> BIT_SHIFT_REG_C3_V3) & BIT_MASK_REG_C3_V3)
+#define BIT_SET_REG_C3_V3(x, v) (BIT_CLEAR_REG_C3_V3(x) | BIT_REG_C3_V3(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_AFE_CTRL3				(Offset 0x002C) */
+
+#define BIT_SHIFT_REG_CP 2
+#define BIT_MASK_REG_CP 0x3
+#define BIT_REG_CP(x) (((x) & BIT_MASK_REG_CP) << BIT_SHIFT_REG_CP)
+#define BITS_REG_CP (BIT_MASK_REG_CP << BIT_SHIFT_REG_CP)
+#define BIT_CLEAR_REG_CP(x) ((x) & (~BITS_REG_CP))
+#define BIT_GET_REG_CP(x) (((x) >> BIT_SHIFT_REG_CP) & BIT_MASK_REG_CP)
+#define BIT_SET_REG_CP(x, v) (BIT_CLEAR_REG_CP(x) | BIT_REG_CP(v))
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_SDIO_TXPKT_EMPTY			(Offset 0x1025002C) */
+
+#define BIT_SDIO_AC2Q_EMPTY BIT(2)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT)
+
+/* 2 REG_AFE_CTRL3				(Offset 0x002C) */
+
+#define BIT_REG_320_SEL_V3 BIT(2)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_SDIO_TXPKT_EMPTY			(Offset 0x1025002C) */
+
+#define BIT_SDIO_AC1Q_EMPTY BIT(1)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_AFE_CTRL3				(Offset 0x002C) */
+
+#define BIT_EN_SYN_V1 BIT(1)
+
+#endif
+
+#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+
+/* 2 REG_AFE_CTRL3				(Offset 0x002C) */
+
+#define BIT_SHIFT_REG_R3_V4 1
+#define BIT_MASK_REG_R3_V4 0x7
+#define BIT_REG_R3_V4(x) (((x) & BIT_MASK_REG_R3_V4) << BIT_SHIFT_REG_R3_V4)
+#define BITS_REG_R3_V4 (BIT_MASK_REG_R3_V4 << BIT_SHIFT_REG_R3_V4)
+#define BIT_CLEAR_REG_R3_V4(x) ((x) & (~BITS_REG_R3_V4))
+#define BIT_GET_REG_R3_V4(x) (((x) >> BIT_SHIFT_REG_R3_V4) & BIT_MASK_REG_R3_V4)
+#define BIT_SET_REG_R3_V4(x, v) (BIT_CLEAR_REG_R3_V4(x) | BIT_REG_R3_V4(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_AFE_CTRL3				(Offset 0x002C) */
+
+#define BIT_SHIFT_REG_C3 0
+#define BIT_MASK_REG_C3 0x3
+#define BIT_REG_C3(x) (((x) & BIT_MASK_REG_C3) << BIT_SHIFT_REG_C3)
+#define BITS_REG_C3 (BIT_MASK_REG_C3 << BIT_SHIFT_REG_C3)
+#define BIT_CLEAR_REG_C3(x) ((x) & (~BITS_REG_C3))
+#define BIT_GET_REG_C3(x) (((x) >> BIT_SHIFT_REG_C3) & BIT_MASK_REG_C3)
+#define BIT_SET_REG_C3(x, v) (BIT_CLEAR_REG_C3(x) | BIT_REG_C3(v))
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_SDIO_TXPKT_EMPTY			(Offset 0x1025002C) */
+
+#define BIT_SDIO_AC0Q_EMPTY BIT(0)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_AFE_CTRL3				(Offset 0x002C) */
+
+#define BIT_IOOFFSET_BIT4 BIT(0)
+
+#endif
+
+#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+
+/* 2 REG_AFE_CTRL3				(Offset 0x002C) */
+
+#define BIT_REG_CP_BIT0 BIT(0)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_EFUSE_CTRL				(Offset 0x0030) */
+
+#define BIT_EF_FLAG BIT(31)
+
+#define BIT_SHIFT_EF_PGPD 28
+#define BIT_MASK_EF_PGPD 0x7
+#define BIT_EF_PGPD(x) (((x) & BIT_MASK_EF_PGPD) << BIT_SHIFT_EF_PGPD)
+#define BITS_EF_PGPD (BIT_MASK_EF_PGPD << BIT_SHIFT_EF_PGPD)
+#define BIT_CLEAR_EF_PGPD(x) ((x) & (~BITS_EF_PGPD))
+#define BIT_GET_EF_PGPD(x) (((x) >> BIT_SHIFT_EF_PGPD) & BIT_MASK_EF_PGPD)
+#define BIT_SET_EF_PGPD(x, v) (BIT_CLEAR_EF_PGPD(x) | BIT_EF_PGPD(v))
+
+#define BIT_SHIFT_EF_RDT 24
+#define BIT_MASK_EF_RDT 0xf
+#define BIT_EF_RDT(x) (((x) & BIT_MASK_EF_RDT) << BIT_SHIFT_EF_RDT)
+#define BITS_EF_RDT (BIT_MASK_EF_RDT << BIT_SHIFT_EF_RDT)
+#define BIT_CLEAR_EF_RDT(x) ((x) & (~BITS_EF_RDT))
+#define BIT_GET_EF_RDT(x) (((x) >> BIT_SHIFT_EF_RDT) & BIT_MASK_EF_RDT)
+#define BIT_SET_EF_RDT(x, v) (BIT_CLEAR_EF_RDT(x) | BIT_EF_RDT(v))
+
+#define BIT_SHIFT_EF_PGTS 20
+#define BIT_MASK_EF_PGTS 0xf
+#define BIT_EF_PGTS(x) (((x) & BIT_MASK_EF_PGTS) << BIT_SHIFT_EF_PGTS)
+#define BITS_EF_PGTS (BIT_MASK_EF_PGTS << BIT_SHIFT_EF_PGTS)
+#define BIT_CLEAR_EF_PGTS(x) ((x) & (~BITS_EF_PGTS))
+#define BIT_GET_EF_PGTS(x) (((x) >> BIT_SHIFT_EF_PGTS) & BIT_MASK_EF_PGTS)
+#define BIT_SET_EF_PGTS(x, v) (BIT_CLEAR_EF_PGTS(x) | BIT_EF_PGTS(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8881A_SUPPORT)
+
+/* 2 REG_EFUSE_CTRL				(Offset 0x0030) */
+
+#define BIT_EF_PDWN BIT(19)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_EFUSE_CTRL				(Offset 0x0030) */
+
+#define BIT_EF_ALDEN BIT(18)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_SDIO_HTSFR_INFO			(Offset 0x10250030) */
+
+#define BIT_SHIFT_HTSFR1 16
+#define BIT_MASK_HTSFR1 0xffff
+#define BIT_HTSFR1(x) (((x) & BIT_MASK_HTSFR1) << BIT_SHIFT_HTSFR1)
+#define BITS_HTSFR1 (BIT_MASK_HTSFR1 << BIT_SHIFT_HTSFR1)
+#define BIT_CLEAR_HTSFR1(x) ((x) & (~BITS_HTSFR1))
+#define BIT_GET_HTSFR1(x) (((x) >> BIT_SHIFT_HTSFR1) & BIT_MASK_HTSFR1)
+#define BIT_SET_HTSFR1(x, v) (BIT_CLEAR_HTSFR1(x) | BIT_HTSFR1(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_EFUSE_CTRL				(Offset 0x0030) */
+
+#define BIT_SHIFT_EF_ADDR 8
+#define BIT_MASK_EF_ADDR 0x3ff
+#define BIT_EF_ADDR(x) (((x) & BIT_MASK_EF_ADDR) << BIT_SHIFT_EF_ADDR)
+#define BITS_EF_ADDR (BIT_MASK_EF_ADDR << BIT_SHIFT_EF_ADDR)
+#define BIT_CLEAR_EF_ADDR(x) ((x) & (~BITS_EF_ADDR))
+#define BIT_GET_EF_ADDR(x) (((x) >> BIT_SHIFT_EF_ADDR) & BIT_MASK_EF_ADDR)
+#define BIT_SET_EF_ADDR(x, v) (BIT_CLEAR_EF_ADDR(x) | BIT_EF_ADDR(v))
+
+#define BIT_SHIFT_EF_DATA 0
+#define BIT_MASK_EF_DATA 0xff
+#define BIT_EF_DATA(x) (((x) & BIT_MASK_EF_DATA) << BIT_SHIFT_EF_DATA)
+#define BITS_EF_DATA (BIT_MASK_EF_DATA << BIT_SHIFT_EF_DATA)
+#define BIT_CLEAR_EF_DATA(x) ((x) & (~BITS_EF_DATA))
+#define BIT_GET_EF_DATA(x) (((x) >> BIT_SHIFT_EF_DATA) & BIT_MASK_EF_DATA)
+#define BIT_SET_EF_DATA(x, v) (BIT_CLEAR_EF_DATA(x) | BIT_EF_DATA(v))
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_SDIO_HTSFR_INFO			(Offset 0x10250030) */
+
+#define BIT_SHIFT_HTSFR0 0
+#define BIT_MASK_HTSFR0 0xffff
+#define BIT_HTSFR0(x) (((x) & BIT_MASK_HTSFR0) << BIT_SHIFT_HTSFR0)
+#define BITS_HTSFR0 (BIT_MASK_HTSFR0 << BIT_SHIFT_HTSFR0)
+#define BIT_CLEAR_HTSFR0(x) ((x) & (~BITS_HTSFR0))
+#define BIT_GET_HTSFR0(x) (((x) >> BIT_SHIFT_HTSFR0) & BIT_MASK_HTSFR0)
+#define BIT_SET_HTSFR0(x, v) (BIT_CLEAR_HTSFR0(x) | BIT_HTSFR0(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_LDO_EFUSE_CTRL			(Offset 0x0034) */
+
+#define BIT_LDOE25_EN BIT(31)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_LDO_EFUSE_CTRL			(Offset 0x0034) */
+
+#define BIT_SHIFT_LDOE25_VADJ_BIT0_TO_2 28
+#define BIT_MASK_LDOE25_VADJ_BIT0_TO_2 0x7
+#define BIT_LDOE25_VADJ_BIT0_TO_2(x)                                           \
+	(((x) & BIT_MASK_LDOE25_VADJ_BIT0_TO_2)                                \
+	 << BIT_SHIFT_LDOE25_VADJ_BIT0_TO_2)
+#define BITS_LDOE25_VADJ_BIT0_TO_2                                             \
+	(BIT_MASK_LDOE25_VADJ_BIT0_TO_2 << BIT_SHIFT_LDOE25_VADJ_BIT0_TO_2)
+#define BIT_CLEAR_LDOE25_VADJ_BIT0_TO_2(x) ((x) & (~BITS_LDOE25_VADJ_BIT0_TO_2))
+#define BIT_GET_LDOE25_VADJ_BIT0_TO_2(x)                                       \
+	(((x) >> BIT_SHIFT_LDOE25_VADJ_BIT0_TO_2) &                            \
+	 BIT_MASK_LDOE25_VADJ_BIT0_TO_2)
+#define BIT_SET_LDOE25_VADJ_BIT0_TO_2(x, v)                                    \
+	(BIT_CLEAR_LDOE25_VADJ_BIT0_TO_2(x) | BIT_LDOE25_VADJ_BIT0_TO_2(v))
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_LDO_EFUSE_CTRL			(Offset 0x0034) */
+
+#define BIT_SHIFT_LDOE25_V12ADJ_L_LOW 28
+#define BIT_MASK_LDOE25_V12ADJ_L_LOW 0x7
+#define BIT_LDOE25_V12ADJ_L_LOW(x)                                             \
+	(((x) & BIT_MASK_LDOE25_V12ADJ_L_LOW) << BIT_SHIFT_LDOE25_V12ADJ_L_LOW)
+#define BITS_LDOE25_V12ADJ_L_LOW                                               \
+	(BIT_MASK_LDOE25_V12ADJ_L_LOW << BIT_SHIFT_LDOE25_V12ADJ_L_LOW)
+#define BIT_CLEAR_LDOE25_V12ADJ_L_LOW(x) ((x) & (~BITS_LDOE25_V12ADJ_L_LOW))
+#define BIT_GET_LDOE25_V12ADJ_L_LOW(x)                                         \
+	(((x) >> BIT_SHIFT_LDOE25_V12ADJ_L_LOW) & BIT_MASK_LDOE25_V12ADJ_L_LOW)
+#define BIT_SET_LDOE25_V12ADJ_L_LOW(x, v)                                      \
+	(BIT_CLEAR_LDOE25_V12ADJ_L_LOW(x) | BIT_LDOE25_V12ADJ_L_LOW(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_LDO_EFUSE_CTRL			(Offset 0x0034) */
+
+#define BIT_LDOE25_VADJ_BIT3 BIT(27)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_LDO_EFUSE_CTRL			(Offset 0x0034) */
+
+#define BIT_LDOE25_V12ADJ_L_HIGH BIT(27)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT)
+
+/* 2 REG_LDO_EFUSE_CTRL			(Offset 0x0034) */
+
+#define BIT_SHIFT_LDOE25_V12ADJ_L 27
+#define BIT_MASK_LDOE25_V12ADJ_L 0xf
+#define BIT_LDOE25_V12ADJ_L(x)                                                 \
+	(((x) & BIT_MASK_LDOE25_V12ADJ_L) << BIT_SHIFT_LDOE25_V12ADJ_L)
+#define BITS_LDOE25_V12ADJ_L                                                   \
+	(BIT_MASK_LDOE25_V12ADJ_L << BIT_SHIFT_LDOE25_V12ADJ_L)
+#define BIT_CLEAR_LDOE25_V12ADJ_L(x) ((x) & (~BITS_LDOE25_V12ADJ_L))
+#define BIT_GET_LDOE25_V12ADJ_L(x)                                             \
+	(((x) >> BIT_SHIFT_LDOE25_V12ADJ_L) & BIT_MASK_LDOE25_V12ADJ_L)
+#define BIT_SET_LDOE25_V12ADJ_L(x, v)                                          \
+	(BIT_CLEAR_LDOE25_V12ADJ_L(x) | BIT_LDOE25_V12ADJ_L(v))
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_LDO_EFUSE_CTRL			(Offset 0x0034) */
+
+#define BIT_SHIFT_LDOE25_VADJ_3_TO_0 27
+#define BIT_MASK_LDOE25_VADJ_3_TO_0 0xf
+#define BIT_LDOE25_VADJ_3_TO_0(x)                                              \
+	(((x) & BIT_MASK_LDOE25_VADJ_3_TO_0) << BIT_SHIFT_LDOE25_VADJ_3_TO_0)
+#define BITS_LDOE25_VADJ_3_TO_0                                                \
+	(BIT_MASK_LDOE25_VADJ_3_TO_0 << BIT_SHIFT_LDOE25_VADJ_3_TO_0)
+#define BIT_CLEAR_LDOE25_VADJ_3_TO_0(x) ((x) & (~BITS_LDOE25_VADJ_3_TO_0))
+#define BIT_GET_LDOE25_VADJ_3_TO_0(x)                                          \
+	(((x) >> BIT_SHIFT_LDOE25_VADJ_3_TO_0) & BIT_MASK_LDOE25_VADJ_3_TO_0)
+#define BIT_SET_LDOE25_VADJ_3_TO_0(x, v)                                       \
+	(BIT_CLEAR_LDOE25_VADJ_3_TO_0(x) | BIT_LDOE25_VADJ_3_TO_0(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT)
+
+/* 2 REG_LDO_EFUSE_CTRL			(Offset 0x0034) */
+
+#define BIT_EFCRES_SEL BIT(26)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_LDO_EFUSE_CTRL			(Offset 0x0034) */
+
+#define BIT_EF_CRES_SEL BIT(26)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_LDO_EFUSE_CTRL			(Offset 0x0034) */
+
+#define BIT_EF_CSER BIT(26)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_LDO_EFUSE_CTRL			(Offset 0x0034) */
+
+#define BIT_SHIFT_EF_SCAN_START 16
+#define BIT_MASK_EF_SCAN_START 0x1ff
+#define BIT_EF_SCAN_START(x)                                                   \
+	(((x) & BIT_MASK_EF_SCAN_START) << BIT_SHIFT_EF_SCAN_START)
+#define BITS_EF_SCAN_START (BIT_MASK_EF_SCAN_START << BIT_SHIFT_EF_SCAN_START)
+#define BIT_CLEAR_EF_SCAN_START(x) ((x) & (~BITS_EF_SCAN_START))
+#define BIT_GET_EF_SCAN_START(x)                                               \
+	(((x) >> BIT_SHIFT_EF_SCAN_START) & BIT_MASK_EF_SCAN_START)
+#define BIT_SET_EF_SCAN_START(x, v)                                            \
+	(BIT_CLEAR_EF_SCAN_START(x) | BIT_EF_SCAN_START(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_LDO_EFUSE_CTRL			(Offset 0x0034) */
+
+#define BIT_SHIFT_EF_SCAN_START_V1 16
+#define BIT_MASK_EF_SCAN_START_V1 0x3ff
+#define BIT_EF_SCAN_START_V1(x)                                                \
+	(((x) & BIT_MASK_EF_SCAN_START_V1) << BIT_SHIFT_EF_SCAN_START_V1)
+#define BITS_EF_SCAN_START_V1                                                  \
+	(BIT_MASK_EF_SCAN_START_V1 << BIT_SHIFT_EF_SCAN_START_V1)
+#define BIT_CLEAR_EF_SCAN_START_V1(x) ((x) & (~BITS_EF_SCAN_START_V1))
+#define BIT_GET_EF_SCAN_START_V1(x)                                            \
+	(((x) >> BIT_SHIFT_EF_SCAN_START_V1) & BIT_MASK_EF_SCAN_START_V1)
+#define BIT_SET_EF_SCAN_START_V1(x, v)                                         \
+	(BIT_CLEAR_EF_SCAN_START_V1(x) | BIT_EF_SCAN_START_V1(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_LDO_EFUSE_CTRL			(Offset 0x0034) */
+
+#define BIT_SHIFT_EF_SCAN_END 12
+#define BIT_MASK_EF_SCAN_END 0xf
+#define BIT_EF_SCAN_END(x)                                                     \
+	(((x) & BIT_MASK_EF_SCAN_END) << BIT_SHIFT_EF_SCAN_END)
+#define BITS_EF_SCAN_END (BIT_MASK_EF_SCAN_END << BIT_SHIFT_EF_SCAN_END)
+#define BIT_CLEAR_EF_SCAN_END(x) ((x) & (~BITS_EF_SCAN_END))
+#define BIT_GET_EF_SCAN_END(x)                                                 \
+	(((x) >> BIT_SHIFT_EF_SCAN_END) & BIT_MASK_EF_SCAN_END)
+#define BIT_SET_EF_SCAN_END(x, v)                                              \
+	(BIT_CLEAR_EF_SCAN_END(x) | BIT_EF_SCAN_END(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT)
+
+/* 2 REG_LDO_EFUSE_CTRL			(Offset 0x0034) */
+
+#define BIT_EF_FORCE_PGMEN BIT(11)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_LDO_EFUSE_CTRL			(Offset 0x0034) */
+
+#define BIT_EF_PD_DIS BIT(11)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_LDO_EFUSE_CTRL			(Offset 0x0034) */
+
+#define BIT_SCAN_EN BIT(11)
+#define BIT_SW_PG_EN BIT(10)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8881A_SUPPORT)
+
+/* 2 REG_LDO_EFUSE_CTRL			(Offset 0x0034) */
+
+#define BIT_SHIFT_EF_CELL_SEL 8
+#define BIT_MASK_EF_CELL_SEL 0x3
+#define BIT_EF_CELL_SEL(x)                                                     \
+	(((x) & BIT_MASK_EF_CELL_SEL) << BIT_SHIFT_EF_CELL_SEL)
+#define BITS_EF_CELL_SEL (BIT_MASK_EF_CELL_SEL << BIT_SHIFT_EF_CELL_SEL)
+#define BIT_CLEAR_EF_CELL_SEL(x) ((x) & (~BITS_EF_CELL_SEL))
+#define BIT_GET_EF_CELL_SEL(x)                                                 \
+	(((x) >> BIT_SHIFT_EF_CELL_SEL) & BIT_MASK_EF_CELL_SEL)
+#define BIT_SET_EF_CELL_SEL(x, v)                                              \
+	(BIT_CLEAR_EF_CELL_SEL(x) | BIT_EF_CELL_SEL(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_LDO_EFUSE_CTRL			(Offset 0x0034) */
+
+#define BIT_EF_TRPT BIT(7)
+
+#define BIT_SHIFT_EF_TTHD 0
+#define BIT_MASK_EF_TTHD 0x7f
+#define BIT_EF_TTHD(x) (((x) & BIT_MASK_EF_TTHD) << BIT_SHIFT_EF_TTHD)
+#define BITS_EF_TTHD (BIT_MASK_EF_TTHD << BIT_SHIFT_EF_TTHD)
+#define BIT_CLEAR_EF_TTHD(x) ((x) & (~BITS_EF_TTHD))
+#define BIT_GET_EF_TTHD(x) (((x) >> BIT_SHIFT_EF_TTHD) & BIT_MASK_EF_TTHD)
+#define BIT_SET_EF_TTHD(x, v) (BIT_CLEAR_EF_TTHD(x) | BIT_EF_TTHD(v))
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_PWR_OPTION_CTRL			(Offset 0x0038) */
+
+#define BIT_SHIFT_UPHY_BG_ON_OPT 30
+#define BIT_MASK_UPHY_BG_ON_OPT 0x3
+#define BIT_UPHY_BG_ON_OPT(x)                                                  \
+	(((x) & BIT_MASK_UPHY_BG_ON_OPT) << BIT_SHIFT_UPHY_BG_ON_OPT)
+#define BITS_UPHY_BG_ON_OPT                                                    \
+	(BIT_MASK_UPHY_BG_ON_OPT << BIT_SHIFT_UPHY_BG_ON_OPT)
+#define BIT_CLEAR_UPHY_BG_ON_OPT(x) ((x) & (~BITS_UPHY_BG_ON_OPT))
+#define BIT_GET_UPHY_BG_ON_OPT(x)                                              \
+	(((x) >> BIT_SHIFT_UPHY_BG_ON_OPT) & BIT_MASK_UPHY_BG_ON_OPT)
+#define BIT_SET_UPHY_BG_ON_OPT(x, v)                                           \
+	(BIT_CLEAR_UPHY_BG_ON_OPT(x) | BIT_UPHY_BG_ON_OPT(v))
+
+#define BIT_UPHY_BG_ON_USB2 BIT(29)
+#define BIT_UPHY_BG_ON_PCIE BIT(28)
+#define BIT_VD33IO_LEFT_SHD_N_ BIT(27)
+#define BIT_VDIO_RIGHT1_SHD_N_ BIT(26)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_PWR_OPTION_CTRL			(Offset 0x0038) */
+
+#define BIT_SHIFT_AFE_USB_CURRENT_SEL 26
+#define BIT_MASK_AFE_USB_CURRENT_SEL 0x7
+#define BIT_AFE_USB_CURRENT_SEL(x)                                             \
+	(((x) & BIT_MASK_AFE_USB_CURRENT_SEL) << BIT_SHIFT_AFE_USB_CURRENT_SEL)
+#define BITS_AFE_USB_CURRENT_SEL                                               \
+	(BIT_MASK_AFE_USB_CURRENT_SEL << BIT_SHIFT_AFE_USB_CURRENT_SEL)
+#define BIT_CLEAR_AFE_USB_CURRENT_SEL(x) ((x) & (~BITS_AFE_USB_CURRENT_SEL))
+#define BIT_GET_AFE_USB_CURRENT_SEL(x)                                         \
+	(((x) >> BIT_SHIFT_AFE_USB_CURRENT_SEL) & BIT_MASK_AFE_USB_CURRENT_SEL)
+#define BIT_SET_AFE_USB_CURRENT_SEL(x, v)                                      \
+	(BIT_CLEAR_AFE_USB_CURRENT_SEL(x) | BIT_AFE_USB_CURRENT_SEL(v))
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_PWR_OPTION_CTRL			(Offset 0x0038) */
+
+#define BIT_VDIO_RIGHT0_SHD_N_ BIT(25)
+#define BIT_DIS_LPS_WT_PDNSUS BIT(24)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_PWR_OPTION_CTRL			(Offset 0x0038) */
+
+#define BIT_SHIFT_AFE_USB_PATH_SEL 24
+#define BIT_MASK_AFE_USB_PATH_SEL 0x3
+#define BIT_AFE_USB_PATH_SEL(x)                                                \
+	(((x) & BIT_MASK_AFE_USB_PATH_SEL) << BIT_SHIFT_AFE_USB_PATH_SEL)
+#define BITS_AFE_USB_PATH_SEL                                                  \
+	(BIT_MASK_AFE_USB_PATH_SEL << BIT_SHIFT_AFE_USB_PATH_SEL)
+#define BIT_CLEAR_AFE_USB_PATH_SEL(x) ((x) & (~BITS_AFE_USB_PATH_SEL))
+#define BIT_GET_AFE_USB_PATH_SEL(x)                                            \
+	(((x) >> BIT_SHIFT_AFE_USB_PATH_SEL) & BIT_MASK_AFE_USB_PATH_SEL)
+#define BIT_SET_AFE_USB_PATH_SEL(x, v)                                         \
+	(BIT_CLEAR_AFE_USB_PATH_SEL(x) | BIT_AFE_USB_PATH_SEL(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_PWR_OPTION_CTRL			(Offset 0x0038) */
+
+#define BIT_SHIFT_DBG_SEL_V1 16
+#define BIT_MASK_DBG_SEL_V1 0xff
+#define BIT_DBG_SEL_V1(x) (((x) & BIT_MASK_DBG_SEL_V1) << BIT_SHIFT_DBG_SEL_V1)
+#define BITS_DBG_SEL_V1 (BIT_MASK_DBG_SEL_V1 << BIT_SHIFT_DBG_SEL_V1)
+#define BIT_CLEAR_DBG_SEL_V1(x) ((x) & (~BITS_DBG_SEL_V1))
+#define BIT_GET_DBG_SEL_V1(x)                                                  \
+	(((x) >> BIT_SHIFT_DBG_SEL_V1) & BIT_MASK_DBG_SEL_V1)
+#define BIT_SET_DBG_SEL_V1(x, v) (BIT_CLEAR_DBG_SEL_V1(x) | BIT_DBG_SEL_V1(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT)
+
+/* 2 REG_PWR_OPTION_CTRL			(Offset 0x0038) */
+
+#define BIT_CLK_REQ_INPUT BIT(15)
+#define BIT_USB_XTAL_CLK_SEL BIT(14)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_PWR_OPTION_CTRL			(Offset 0x0038) */
+
+#define BIT_SHIFT_DBG_SEL_BYTE 14
+#define BIT_MASK_DBG_SEL_BYTE 0x3
+#define BIT_DBG_SEL_BYTE(x)                                                    \
+	(((x) & BIT_MASK_DBG_SEL_BYTE) << BIT_SHIFT_DBG_SEL_BYTE)
+#define BITS_DBG_SEL_BYTE (BIT_MASK_DBG_SEL_BYTE << BIT_SHIFT_DBG_SEL_BYTE)
+#define BIT_CLEAR_DBG_SEL_BYTE(x) ((x) & (~BITS_DBG_SEL_BYTE))
+#define BIT_GET_DBG_SEL_BYTE(x)                                                \
+	(((x) >> BIT_SHIFT_DBG_SEL_BYTE) & BIT_MASK_DBG_SEL_BYTE)
+#define BIT_SET_DBG_SEL_BYTE(x, v)                                             \
+	(BIT_CLEAR_DBG_SEL_BYTE(x) | BIT_DBG_SEL_BYTE(v))
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_PWR_OPTION_CTRL			(Offset 0x0038) */
+
+#define BIT_USB_REG_XTAL_SEL BIT(14)
+#define BIT_SYSON_BTIO1POW_PAD_E2 BIT(13)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT)
+
+/* 2 REG_PWR_OPTION_CTRL			(Offset 0x0038) */
+
+#define BIT_SHIFT_SYSON_SPS0_STD_L1 12
+#define BIT_MASK_SYSON_SPS0_STD_L1 0x3
+#define BIT_SYSON_SPS0_STD_L1(x)                                               \
+	(((x) & BIT_MASK_SYSON_SPS0_STD_L1) << BIT_SHIFT_SYSON_SPS0_STD_L1)
+#define BITS_SYSON_SPS0_STD_L1                                                 \
+	(BIT_MASK_SYSON_SPS0_STD_L1 << BIT_SHIFT_SYSON_SPS0_STD_L1)
+#define BIT_CLEAR_SYSON_SPS0_STD_L1(x) ((x) & (~BITS_SYSON_SPS0_STD_L1))
+#define BIT_GET_SYSON_SPS0_STD_L1(x)                                           \
+	(((x) >> BIT_SHIFT_SYSON_SPS0_STD_L1) & BIT_MASK_SYSON_SPS0_STD_L1)
+#define BIT_SET_SYSON_SPS0_STD_L1(x, v)                                        \
+	(BIT_CLEAR_SYSON_SPS0_STD_L1(x) | BIT_SYSON_SPS0_STD_L1(v))
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+
+/* 2 REG_PWR_OPTION_CTRL			(Offset 0x0038) */
+
+#define BIT_SHIFT_STD_L1_V1 12
+#define BIT_MASK_STD_L1_V1 0x3
+#define BIT_STD_L1_V1(x) (((x) & BIT_MASK_STD_L1_V1) << BIT_SHIFT_STD_L1_V1)
+#define BITS_STD_L1_V1 (BIT_MASK_STD_L1_V1 << BIT_SHIFT_STD_L1_V1)
+#define BIT_CLEAR_STD_L1_V1(x) ((x) & (~BITS_STD_L1_V1))
+#define BIT_GET_STD_L1_V1(x) (((x) >> BIT_SHIFT_STD_L1_V1) & BIT_MASK_STD_L1_V1)
+#define BIT_SET_STD_L1_V1(x, v) (BIT_CLEAR_STD_L1_V1(x) | BIT_STD_L1_V1(v))
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_PWR_OPTION_CTRL			(Offset 0x0038) */
+
+#define BIT_SYSON_BTIOPOW_PAD_E2 BIT(12)
+
+#endif
+
+#if (HALMAC_8881A_SUPPORT)
+
+/* 2 REG_PWR_OPTION_CTRL			(Offset 0x0038) */
+
+#define BIT_SHIFT_SYSON_LDOA12V_WT 12
+#define BIT_MASK_SYSON_LDOA12V_WT 0x3
+#define BIT_SYSON_LDOA12V_WT(x)                                                \
+	(((x) & BIT_MASK_SYSON_LDOA12V_WT) << BIT_SHIFT_SYSON_LDOA12V_WT)
+#define BITS_SYSON_LDOA12V_WT                                                  \
+	(BIT_MASK_SYSON_LDOA12V_WT << BIT_SHIFT_SYSON_LDOA12V_WT)
+#define BIT_CLEAR_SYSON_LDOA12V_WT(x) ((x) & (~BITS_SYSON_LDOA12V_WT))
+#define BIT_GET_SYSON_LDOA12V_WT(x)                                            \
+	(((x) >> BIT_SHIFT_SYSON_LDOA12V_WT) & BIT_MASK_SYSON_LDOA12V_WT)
+#define BIT_SET_SYSON_LDOA12V_WT(x, v)                                         \
+	(BIT_CLEAR_SYSON_LDOA12V_WT(x) | BIT_SYSON_LDOA12V_WT(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8881A_SUPPORT)
+
+/* 2 REG_PWR_OPTION_CTRL			(Offset 0x0038) */
+
+#define BIT_SYSON_DBG_PAD_E2 BIT(11)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_PWR_OPTION_CTRL			(Offset 0x0038) */
+
+#define BIT_SYSON_SDIOPOW_PAD_E2 BIT(11)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_PWR_OPTION_CTRL			(Offset 0x0038) */
+
+#define BIT_SYSON_LED_PAD_E2 BIT(10)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8881A_SUPPORT)
+
+/* 2 REG_PWR_OPTION_CTRL			(Offset 0x0038) */
+
+#define BIT_SYSON_GPEE_PAD_E2 BIT(9)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_PWR_OPTION_CTRL			(Offset 0x0038) */
+
+#define BIT_SYSON_GPEE_PAD_E2_V33 BIT(9)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_PWR_OPTION_CTRL			(Offset 0x0038) */
+
+#define BIT_SYSON_PCI_PAD_E2 BIT(8)
+
+#define BIT_SHIFT_MATCH_CNT 8
+#define BIT_MASK_MATCH_CNT 0xff
+#define BIT_MATCH_CNT(x) (((x) & BIT_MASK_MATCH_CNT) << BIT_SHIFT_MATCH_CNT)
+#define BITS_MATCH_CNT (BIT_MASK_MATCH_CNT << BIT_SHIFT_MATCH_CNT)
+#define BIT_CLEAR_MATCH_CNT(x) ((x) & (~BITS_MATCH_CNT))
+#define BIT_GET_MATCH_CNT(x) (((x) >> BIT_SHIFT_MATCH_CNT) & BIT_MASK_MATCH_CNT)
+#define BIT_SET_MATCH_CNT(x, v) (BIT_CLEAR_MATCH_CNT(x) | BIT_MATCH_CNT(v))
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_PWR_OPTION_CTRL			(Offset 0x0038) */
+
+#define BIT_AUTO_SW_LDO_VOL_EN BIT(7)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT)
+
+/* 2 REG_PWR_OPTION_CTRL			(Offset 0x0038) */
+
+#define BIT_AUTO_SW_LDO_VOL_EN_V1 BIT(6)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_PWR_OPTION_CTRL			(Offset 0x0038) */
+
+#define BIT_ADJ_LDO_VOLT BIT(6)
+
+#endif
+
+#if (HALMAC_8881A_SUPPORT)
+
+/* 2 REG_PWR_OPTION_CTRL			(Offset 0x0038) */
+
+#define BIT_SHIFT_SYSON_LDOHCI12_WT 6
+#define BIT_MASK_SYSON_LDOHCI12_WT 0x3
+#define BIT_SYSON_LDOHCI12_WT(x)                                               \
+	(((x) & BIT_MASK_SYSON_LDOHCI12_WT) << BIT_SHIFT_SYSON_LDOHCI12_WT)
+#define BITS_SYSON_LDOHCI12_WT                                                 \
+	(BIT_MASK_SYSON_LDOHCI12_WT << BIT_SHIFT_SYSON_LDOHCI12_WT)
+#define BIT_CLEAR_SYSON_LDOHCI12_WT(x) ((x) & (~BITS_SYSON_LDOHCI12_WT))
+#define BIT_GET_SYSON_LDOHCI12_WT(x)                                           \
+	(((x) >> BIT_SHIFT_SYSON_LDOHCI12_WT) & BIT_MASK_SYSON_LDOHCI12_WT)
+#define BIT_SET_SYSON_LDOHCI12_WT(x, v)                                        \
+	(BIT_CLEAR_SYSON_LDOHCI12_WT(x) | BIT_SYSON_LDOHCI12_WT(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8881A_SUPPORT)
+
+/* 2 REG_PWR_OPTION_CTRL			(Offset 0x0038) */
+
+#define BIT_SHIFT_SYSON_SPS0WWV_WT 4
+#define BIT_MASK_SYSON_SPS0WWV_WT 0x3
+#define BIT_SYSON_SPS0WWV_WT(x)                                                \
+	(((x) & BIT_MASK_SYSON_SPS0WWV_WT) << BIT_SHIFT_SYSON_SPS0WWV_WT)
+#define BITS_SYSON_SPS0WWV_WT                                                  \
+	(BIT_MASK_SYSON_SPS0WWV_WT << BIT_SHIFT_SYSON_SPS0WWV_WT)
+#define BIT_CLEAR_SYSON_SPS0WWV_WT(x) ((x) & (~BITS_SYSON_SPS0WWV_WT))
+#define BIT_GET_SYSON_SPS0WWV_WT(x)                                            \
+	(((x) >> BIT_SHIFT_SYSON_SPS0WWV_WT) & BIT_MASK_SYSON_SPS0WWV_WT)
+#define BIT_SET_SYSON_SPS0WWV_WT(x, v)                                         \
+	(BIT_CLEAR_SYSON_SPS0WWV_WT(x) | BIT_SYSON_SPS0WWV_WT(v))
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_PWR_OPTION_CTRL			(Offset 0x0038) */
+
+#define BIT_SHIFT_SYSON_SPS0SPS_WT 4
+#define BIT_MASK_SYSON_SPS0SPS_WT 0x3
+#define BIT_SYSON_SPS0SPS_WT(x)                                                \
+	(((x) & BIT_MASK_SYSON_SPS0SPS_WT) << BIT_SHIFT_SYSON_SPS0SPS_WT)
+#define BITS_SYSON_SPS0SPS_WT                                                  \
+	(BIT_MASK_SYSON_SPS0SPS_WT << BIT_SHIFT_SYSON_SPS0SPS_WT)
+#define BIT_CLEAR_SYSON_SPS0SPS_WT(x) ((x) & (~BITS_SYSON_SPS0SPS_WT))
+#define BIT_GET_SYSON_SPS0SPS_WT(x)                                            \
+	(((x) >> BIT_SHIFT_SYSON_SPS0SPS_WT) & BIT_MASK_SYSON_SPS0SPS_WT)
+#define BIT_SET_SYSON_SPS0SPS_WT(x, v)                                         \
+	(BIT_CLEAR_SYSON_SPS0SPS_WT(x) | BIT_SYSON_SPS0SPS_WT(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8881A_SUPPORT)
+
+/* 2 REG_PWR_OPTION_CTRL			(Offset 0x0038) */
+
+#define BIT_SHIFT_SYSON_SPS0LDO_WT 2
+#define BIT_MASK_SYSON_SPS0LDO_WT 0x3
+#define BIT_SYSON_SPS0LDO_WT(x)                                                \
+	(((x) & BIT_MASK_SYSON_SPS0LDO_WT) << BIT_SHIFT_SYSON_SPS0LDO_WT)
+#define BITS_SYSON_SPS0LDO_WT                                                  \
+	(BIT_MASK_SYSON_SPS0LDO_WT << BIT_SHIFT_SYSON_SPS0LDO_WT)
+#define BIT_CLEAR_SYSON_SPS0LDO_WT(x) ((x) & (~BITS_SYSON_SPS0LDO_WT))
+#define BIT_GET_SYSON_SPS0LDO_WT(x)                                            \
+	(((x) >> BIT_SHIFT_SYSON_SPS0LDO_WT) & BIT_MASK_SYSON_SPS0LDO_WT)
+#define BIT_SET_SYSON_SPS0LDO_WT(x, v)                                         \
+	(BIT_CLEAR_SYSON_SPS0LDO_WT(x) | BIT_SYSON_SPS0LDO_WT(v))
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_PWR_OPTION_CTRL			(Offset 0x0038) */
+
+#define BIT_SHIFT_SYSON_SPS11VLDO_WT 2
+#define BIT_MASK_SYSON_SPS11VLDO_WT 0x3
+#define BIT_SYSON_SPS11VLDO_WT(x)                                              \
+	(((x) & BIT_MASK_SYSON_SPS11VLDO_WT) << BIT_SHIFT_SYSON_SPS11VLDO_WT)
+#define BITS_SYSON_SPS11VLDO_WT                                                \
+	(BIT_MASK_SYSON_SPS11VLDO_WT << BIT_SHIFT_SYSON_SPS11VLDO_WT)
+#define BIT_CLEAR_SYSON_SPS11VLDO_WT(x) ((x) & (~BITS_SYSON_SPS11VLDO_WT))
+#define BIT_GET_SYSON_SPS11VLDO_WT(x)                                          \
+	(((x) >> BIT_SHIFT_SYSON_SPS11VLDO_WT) & BIT_MASK_SYSON_SPS11VLDO_WT)
+#define BIT_SET_SYSON_SPS11VLDO_WT(x, v)                                       \
+	(BIT_CLEAR_SYSON_SPS11VLDO_WT(x) | BIT_SYSON_SPS11VLDO_WT(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_PWR_OPTION_CTRL			(Offset 0x0038) */
+
+#define BIT_SHIFT_SYSON_RCLK_SCALE 0
+#define BIT_MASK_SYSON_RCLK_SCALE 0x3
+#define BIT_SYSON_RCLK_SCALE(x)                                                \
+	(((x) & BIT_MASK_SYSON_RCLK_SCALE) << BIT_SHIFT_SYSON_RCLK_SCALE)
+#define BITS_SYSON_RCLK_SCALE                                                  \
+	(BIT_MASK_SYSON_RCLK_SCALE << BIT_SHIFT_SYSON_RCLK_SCALE)
+#define BIT_CLEAR_SYSON_RCLK_SCALE(x) ((x) & (~BITS_SYSON_RCLK_SCALE))
+#define BIT_GET_SYSON_RCLK_SCALE(x)                                            \
+	(((x) >> BIT_SHIFT_SYSON_RCLK_SCALE) & BIT_MASK_SYSON_RCLK_SCALE)
+#define BIT_SET_SYSON_RCLK_SCALE(x, v)                                         \
+	(BIT_CLEAR_SYSON_RCLK_SCALE(x) | BIT_SYSON_RCLK_SCALE(v))
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_SDIO_HCPWM1_V2			(Offset 0x10250038) */
+
+#define BIT_CUR_PS BIT(0)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_CAL_TIMER				(Offset 0x003C) */
+
+#define BIT_SHIFT_CAL_SCAL 0
+#define BIT_MASK_CAL_SCAL 0xff
+#define BIT_CAL_SCAL(x) (((x) & BIT_MASK_CAL_SCAL) << BIT_SHIFT_CAL_SCAL)
+#define BITS_CAL_SCAL (BIT_MASK_CAL_SCAL << BIT_SHIFT_CAL_SCAL)
+#define BIT_CLEAR_CAL_SCAL(x) ((x) & (~BITS_CAL_SCAL))
+#define BIT_GET_CAL_SCAL(x) (((x) >> BIT_SHIFT_CAL_SCAL) & BIT_MASK_CAL_SCAL)
+#define BIT_SET_CAL_SCAL(x, v) (BIT_CLEAR_CAL_SCAL(x) | BIT_CAL_SCAL(v))
+
+/* 2 REG_ACLK_MON				(Offset 0x003E) */
+
+#define BIT_SHIFT_RCLK_MON 5
+#define BIT_MASK_RCLK_MON 0x7ff
+#define BIT_RCLK_MON(x) (((x) & BIT_MASK_RCLK_MON) << BIT_SHIFT_RCLK_MON)
+#define BITS_RCLK_MON (BIT_MASK_RCLK_MON << BIT_SHIFT_RCLK_MON)
+#define BIT_CLEAR_RCLK_MON(x) ((x) & (~BITS_RCLK_MON))
+#define BIT_GET_RCLK_MON(x) (((x) >> BIT_SHIFT_RCLK_MON) & BIT_MASK_RCLK_MON)
+#define BIT_SET_RCLK_MON(x, v) (BIT_CLEAR_RCLK_MON(x) | BIT_RCLK_MON(v))
+
+#define BIT_CAL_EN BIT(4)
+
+#define BIT_SHIFT_DPSTU 2
+#define BIT_MASK_DPSTU 0x3
+#define BIT_DPSTU(x) (((x) & BIT_MASK_DPSTU) << BIT_SHIFT_DPSTU)
+#define BITS_DPSTU (BIT_MASK_DPSTU << BIT_SHIFT_DPSTU)
+#define BIT_CLEAR_DPSTU(x) ((x) & (~BITS_DPSTU))
+#define BIT_GET_DPSTU(x) (((x) >> BIT_SHIFT_DPSTU) & BIT_MASK_DPSTU)
+#define BIT_SET_DPSTU(x, v) (BIT_CLEAR_DPSTU(x) | BIT_DPSTU(v))
+
+#define BIT_SUS_16X BIT(1)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_ACLK_MON				(Offset 0x003E) */
+
+#define BIT_RSM_EN BIT(0)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_GPIO_MUXCFG_2			(Offset 0x003F) */
+
+#define BIT_SOUT_GPIO8 BIT(7)
+#define BIT_SOUT_GPIO5 BIT(6)
+#define BIT_RFE_CTRL_5_GPIO14_V1 BIT(5)
+#define BIT_RFE_CTRL_10_GPIO13_V1 BIT(4)
+#define BIT_RFE_CTRL_11_GPIO4_V1 BIT(3)
+#define BIT_RFE_CTRL_5_GPIO14 BIT(2)
+#define BIT_RFE_CTRL_10_GPIO13 BIT(1)
+#define BIT_RFE_CTRL_11_GPIO4 BIT(0)
+
+/* 2 REG_GPIO_MUXCFG				(Offset 0x0040) */
+
+#define BIT_RFE_CTRL_3_GPIO12 BIT(31)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_GPIO_MUXCFG				(Offset 0x0040) */
+
+#define BIT_PAD_D_PAPE_2G_E BIT(31)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_GPIO_MUXCFG				(Offset 0x0040) */
+
+#define BIT_BT_RFE_CTRL_5_GPIO12 BIT(30)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_GPIO_MUXCFG				(Offset 0x0040) */
+
+#define BIT_PAD_D_PAPE_5G_E BIT(30)
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+/* 2 REG_GPIO_MUXCFG				(Offset 0x0040) */
+
+#define BIT_SIC_LOWEST_PRIORITY_V1 BIT(29)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_GPIO_MUXCFG				(Offset 0x0040) */
+
+#define BIT_S0_TRSW_GPIO12 BIT(29)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_GPIO_MUXCFG				(Offset 0x0040) */
+
+#define BIT_PAD_D_TRSW_E BIT(29)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_GPIO_MUXCFG				(Offset 0x0040) */
+
+#define BIT_SIC_PRI_LOWEST BIT(28)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT)
+
+/* 2 REG_GPIO_MUXCFG				(Offset 0x0040) */
+
+#define BIT_SIC_LOWEST_PRIORITY BIT(28)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_GPIO_MUXCFG				(Offset 0x0040) */
+
+#define BIT_RFE_CTRL_9_GPIO13 BIT(28)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_GPIO_MUXCFG				(Offset 0x0040) */
+
+#define BIT_PAD_D_TRSWB_E BIT(28)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT)
+
+/* 2 REG_GPIO_MUXCFG				(Offset 0x0040) */
+
+#define BIT_WL_DSS_RSTN BIT(27)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_GPIO_MUXCFG				(Offset 0x0040) */
+
+#define BIT_RFE_CTRL_9_GPIO12 BIT(27)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_GPIO_MUXCFG				(Offset 0x0040) */
+
+#define BIT_PAD_D_PAPE_2G_O BIT(27)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT)
+
+/* 2 REG_GPIO_MUXCFG				(Offset 0x0040) */
+
+#define BIT_WL_DSS_EN_CLK BIT(26)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_GPIO_MUXCFG				(Offset 0x0040) */
+
+#define BIT_RFE_CTRL_8_GPIO4 BIT(26)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_GPIO_MUXCFG				(Offset 0x0040) */
+
+#define BIT_PAD_D_PAPE_5G_O BIT(26)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_GPIO_MUXCFG				(Offset 0x0040) */
+
+#define BIT_BT_RFE_CTRL_1_GPIO13 BIT(25)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_GPIO_MUXCFG				(Offset 0x0040) */
+
+#define BIT_PAD_D_TRSW_O BIT(25)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT)
+
+/* 2 REG_GPIO_MUXCFG				(Offset 0x0040) */
+
+#define BIT_SHIFT_PIN_USECASE 24
+#define BIT_MASK_PIN_USECASE 0xf
+#define BIT_PIN_USECASE(x)                                                     \
+	(((x) & BIT_MASK_PIN_USECASE) << BIT_SHIFT_PIN_USECASE)
+#define BITS_PIN_USECASE (BIT_MASK_PIN_USECASE << BIT_SHIFT_PIN_USECASE)
+#define BIT_CLEAR_PIN_USECASE(x) ((x) & (~BITS_PIN_USECASE))
+#define BIT_GET_PIN_USECASE(x)                                                 \
+	(((x) >> BIT_SHIFT_PIN_USECASE) & BIT_MASK_PIN_USECASE)
+#define BIT_SET_PIN_USECASE(x, v)                                              \
+	(BIT_CLEAR_PIN_USECASE(x) | BIT_PIN_USECASE(v))
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+/* 2 REG_GPIO_MUXCFG				(Offset 0x0040) */
+
+#define BIT_SHIFT_PIN_USECASE_V1 24
+#define BIT_MASK_PIN_USECASE_V1 0x1f
+#define BIT_PIN_USECASE_V1(x)                                                  \
+	(((x) & BIT_MASK_PIN_USECASE_V1) << BIT_SHIFT_PIN_USECASE_V1)
+#define BITS_PIN_USECASE_V1                                                    \
+	(BIT_MASK_PIN_USECASE_V1 << BIT_SHIFT_PIN_USECASE_V1)
+#define BIT_CLEAR_PIN_USECASE_V1(x) ((x) & (~BITS_PIN_USECASE_V1))
+#define BIT_GET_PIN_USECASE_V1(x)                                              \
+	(((x) >> BIT_SHIFT_PIN_USECASE_V1) & BIT_MASK_PIN_USECASE_V1)
+#define BIT_SET_PIN_USECASE_V1(x, v)                                           \
+	(BIT_CLEAR_PIN_USECASE_V1(x) | BIT_PIN_USECASE_V1(v))
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_GPIO_MUXCFG				(Offset 0x0040) */
+
+#define BIT_BT_RFE_CTRL_1_GPIO12 BIT(24)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_GPIO_MUXCFG				(Offset 0x0040) */
+
+#define BIT_PAD_D_TRSWB_O BIT(24)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_GPIO_MUXCFG				(Offset 0x0040) */
+
+#define BIT_EN_DATACPU_GPIO2 BIT(24)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_GPIO_MUXCFG				(Offset 0x0040) */
+
+#define BIT_BT_RFE_CTRL_0_GPIO4 BIT(23)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_GPIO_MUXCFG				(Offset 0x0040) */
+
+#define BIT_EN_A_ANTSEL BIT(23)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_GPIO_MUXCFG				(Offset 0x0040) */
+
+#define BIT_EN_DATACPU_GPIO BIT(23)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_GPIO_MUXCFG				(Offset 0x0040) */
+
+#define BIT_ANTSW_GPIO13 BIT(22)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_GPIO_MUXCFG				(Offset 0x0040) */
+
+#define BIT_EN_A_ANTSELB BIT(22)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_GPIO_MUXCFG				(Offset 0x0040) */
+
+#define BIT_EN_DATACPU_UART BIT(22)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_GPIO_MUXCFG				(Offset 0x0040) */
+
+#define BIT_ANTSW_GPIO12 BIT(21)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_GPIO_MUXCFG				(Offset 0x0040) */
+
+#define BIT_EN_D_PAPE_2G BIT(21)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_GPIO_MUXCFG				(Offset 0x0040) */
+
+#define BIT_DATACPU_FSPI_EN BIT(21)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_SDIO_INDIRECT_REG_CFG		(Offset 0x10250040) */
+
+#define BIT_INDIRECT_REG_RDY BIT(20)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_GPIO_MUXCFG				(Offset 0x0040) */
+
+#define BIT_ANTSWB_GPIO4 BIT(20)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_GPIO_MUXCFG				(Offset 0x0040) */
+
+#define BIT_EN_D_PAPE_5G BIT(20)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_GPIO_MUXCFG				(Offset 0x0040) */
+
+#define BIT_EN_GPIO8_UART_OUT BIT(20)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_GPIO_MUXCFG				(Offset 0x0040) */
+
+#define BIT_FSPI_EN BIT(19)
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+/* 2 REG_GPIO_MUXCFG				(Offset 0x0040) */
+
+#define BIT_SW_IO_EN BIT(19)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_SDIO_INDIRECT_REG_CFG		(Offset 0x10250040) */
+
+#define BIT_INDIRECT_REG_R BIT(19)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_GPIO_MUXCFG				(Offset 0x0040) */
+
+#define BIT_WL_RTS_EXT_32K_SEL BIT(18)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_SDIO_INDIRECT_REG_CFG		(Offset 0x10250040) */
+
+#define BIT_INDIRECT_REG_W BIT(18)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT)
+
+/* 2 REG_GPIO_MUXCFG				(Offset 0x0040) */
+
+#define BIT_CKOUT33_EN BIT(17)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_GPIO_MUXCFG				(Offset 0x0040) */
+
+#define BIT_WLBT_DPDT_SEL_EN BIT(17)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_GPIO_MUXCFG				(Offset 0x0040) */
+
+#define BIT_XTAL_OUT_EN BIT(17)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8881A_SUPPORT)
+
+/* 2 REG_GPIO_MUXCFG				(Offset 0x0040) */
+
+#define BIT_WLGP_SPI_EN BIT(16)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_GPIO_MUXCFG				(Offset 0x0040) */
+
+#define BIT_WLGP_CKOUT BIT(16)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_SDIO_INDIRECT_REG_CFG		(Offset 0x10250040) */
+
+#define BIT_SHIFT_INDIRECT_REG_SIZE 16
+#define BIT_MASK_INDIRECT_REG_SIZE 0x3
+#define BIT_INDIRECT_REG_SIZE(x)                                               \
+	(((x) & BIT_MASK_INDIRECT_REG_SIZE) << BIT_SHIFT_INDIRECT_REG_SIZE)
+#define BITS_INDIRECT_REG_SIZE                                                 \
+	(BIT_MASK_INDIRECT_REG_SIZE << BIT_SHIFT_INDIRECT_REG_SIZE)
+#define BIT_CLEAR_INDIRECT_REG_SIZE(x) ((x) & (~BITS_INDIRECT_REG_SIZE))
+#define BIT_GET_INDIRECT_REG_SIZE(x)                                           \
+	(((x) >> BIT_SHIFT_INDIRECT_REG_SIZE) & BIT_MASK_INDIRECT_REG_SIZE)
+#define BIT_SET_INDIRECT_REG_SIZE(x, v)                                        \
+	(BIT_CLEAR_INDIRECT_REG_SIZE(x) | BIT_INDIRECT_REG_SIZE(v))
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_GPIO_MUXCFG				(Offset 0x0040) */
+
+#define BIT_WLBT_LNAON_SEL_EN BIT(16)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_GPIO_MUXCFG				(Offset 0x0040) */
+
+#define BIT_SIC_LBK BIT(15)
+#define BIT_ENHTP BIT(14)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_GPIO_MUXCFG				(Offset 0x0040) */
+
+#define BIT_PHY_TEST_EN BIT(13)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_GPIO_MUXCFG				(Offset 0x0040) */
+
+#define BIT_WLPHY_DBG_EN BIT(13)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_GPIO_MUXCFG				(Offset 0x0040) */
+
+#define BIT_BT_AOD_GPIO3 BIT(13)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_GPIO_MUXCFG				(Offset 0x0040) */
+
+#define BIT_SIC_23 BIT(13)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_GPIO_MUXCFG				(Offset 0x0040) */
+
+#define BIT_ENSIC BIT(12)
+#define BIT_SIC_SWRST BIT(11)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_GPIO_MUXCFG				(Offset 0x0040) */
+
+#define BIT_PO_WIFI_PTA_PINS BIT(10)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_GPIO_MUXCFG				(Offset 0x0040) */
+
+#define BIT_ENPMAC BIT(10)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT)
+
+/* 2 REG_GPIO_MUXCFG				(Offset 0x0040) */
+
+#define BIT_ENBTCMD BIT(9)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_GPIO_MUXCFG				(Offset 0x0040) */
+
+#define BIT_COEX_MBOX BIT(9)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_GPIO_MUXCFG				(Offset 0x0040) */
+
+#define BIT_BTCOEX_MBOX_EN BIT(9)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_GPIO_MUXCFG				(Offset 0x0040) */
+
+#define BIT_PO_BT_PTA_PINS BIT(9)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_GPIO_MUXCFG				(Offset 0x0040) */
+
+#define BIT_BTCMD_OUT_EN BIT(9)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_GPIO_MUXCFG				(Offset 0x0040) */
+
+#define BIT_ENUART BIT(8)
+
+#define BIT_SHIFT_BTMODE 6
+#define BIT_MASK_BTMODE 0x3
+#define BIT_BTMODE(x) (((x) & BIT_MASK_BTMODE) << BIT_SHIFT_BTMODE)
+#define BITS_BTMODE (BIT_MASK_BTMODE << BIT_SHIFT_BTMODE)
+#define BIT_CLEAR_BTMODE(x) ((x) & (~BITS_BTMODE))
+#define BIT_GET_BTMODE(x) (((x) >> BIT_SHIFT_BTMODE) & BIT_MASK_BTMODE)
+#define BIT_SET_BTMODE(x, v) (BIT_CLEAR_BTMODE(x) | BIT_BTMODE(v))
+
+#define BIT_ENBT BIT(5)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_GPIO_MUXCFG				(Offset 0x0040) */
+
+#define BIT_GEN1GEN2_SWITCH BIT(5)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_GPIO_MUXCFG				(Offset 0x0040) */
+
+#define BIT_EROM_EN BIT(4)
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+/* 2 REG_GPIO_MUXCFG				(Offset 0x0040) */
+
+#define BIT_ENUARTTX BIT(4)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_GPIO_MUXCFG				(Offset 0x0040) */
+
+#define BIT_WLRFE_6_7_EN BIT(3)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_GPIO_MUXCFG				(Offset 0x0040) */
+
+#define BIT_WLRFE_12_EN BIT(3)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_GPIO_MUXCFG				(Offset 0x0040) */
+
+#define BIT_EN_D_TRSW BIT(3)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_GPIO_MUXCFG				(Offset 0x0040) */
+
+#define BIT_WLRFE_4_5_EN BIT(2)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_GPIO_MUXCFG				(Offset 0x0040) */
+
+#define BIT_SPDT_SEL BIT(2)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_GPIO_MUXCFG				(Offset 0x0040) */
+
+#define BIT_EN_D_TRSWB BIT(2)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_GPIO_MUXCFG				(Offset 0x0040) */
+
+#define BIT_SHIFT_GPIOSEL 0
+#define BIT_MASK_GPIOSEL 0x3
+#define BIT_GPIOSEL(x) (((x) & BIT_MASK_GPIOSEL) << BIT_SHIFT_GPIOSEL)
+#define BITS_GPIOSEL (BIT_MASK_GPIOSEL << BIT_SHIFT_GPIOSEL)
+#define BIT_CLEAR_GPIOSEL(x) ((x) & (~BITS_GPIOSEL))
+#define BIT_GET_GPIOSEL(x) (((x) >> BIT_SHIFT_GPIOSEL) & BIT_MASK_GPIOSEL)
+#define BIT_SET_GPIOSEL(x, v) (BIT_CLEAR_GPIOSEL(x) | BIT_GPIOSEL(v))
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_SDIO_INDIRECT_REG_CFG		(Offset 0x10250040) */
+
+#define BIT_SHIFT_INDIRECT_REG_ADDR 0
+#define BIT_MASK_INDIRECT_REG_ADDR 0xffff
+#define BIT_INDIRECT_REG_ADDR(x)                                               \
+	(((x) & BIT_MASK_INDIRECT_REG_ADDR) << BIT_SHIFT_INDIRECT_REG_ADDR)
+#define BITS_INDIRECT_REG_ADDR                                                 \
+	(BIT_MASK_INDIRECT_REG_ADDR << BIT_SHIFT_INDIRECT_REG_ADDR)
+#define BIT_CLEAR_INDIRECT_REG_ADDR(x) ((x) & (~BITS_INDIRECT_REG_ADDR))
+#define BIT_GET_INDIRECT_REG_ADDR(x)                                           \
+	(((x) >> BIT_SHIFT_INDIRECT_REG_ADDR) & BIT_MASK_INDIRECT_REG_ADDR)
+#define BIT_SET_INDIRECT_REG_ADDR(x, v)                                        \
+	(BIT_CLEAR_INDIRECT_REG_ADDR(x) | BIT_INDIRECT_REG_ADDR(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_GPIO_PIN_CTRL			(Offset 0x0044) */
+
+#define BIT_SHIFT_GPIO_MOD_7_TO_0 24
+#define BIT_MASK_GPIO_MOD_7_TO_0 0xff
+#define BIT_GPIO_MOD_7_TO_0(x)                                                 \
+	(((x) & BIT_MASK_GPIO_MOD_7_TO_0) << BIT_SHIFT_GPIO_MOD_7_TO_0)
+#define BITS_GPIO_MOD_7_TO_0                                                   \
+	(BIT_MASK_GPIO_MOD_7_TO_0 << BIT_SHIFT_GPIO_MOD_7_TO_0)
+#define BIT_CLEAR_GPIO_MOD_7_TO_0(x) ((x) & (~BITS_GPIO_MOD_7_TO_0))
+#define BIT_GET_GPIO_MOD_7_TO_0(x)                                             \
+	(((x) >> BIT_SHIFT_GPIO_MOD_7_TO_0) & BIT_MASK_GPIO_MOD_7_TO_0)
+#define BIT_SET_GPIO_MOD_7_TO_0(x, v)                                          \
+	(BIT_CLEAR_GPIO_MOD_7_TO_0(x) | BIT_GPIO_MOD_7_TO_0(v))
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_GPIO_PIN_CTRL			(Offset 0x0044) */
+
+#define BIT_SHIFT_WLGP1_SWIOMOD 24
+#define BIT_MASK_WLGP1_SWIOMOD 0xff
+#define BIT_WLGP1_SWIOMOD(x)                                                   \
+	(((x) & BIT_MASK_WLGP1_SWIOMOD) << BIT_SHIFT_WLGP1_SWIOMOD)
+#define BITS_WLGP1_SWIOMOD (BIT_MASK_WLGP1_SWIOMOD << BIT_SHIFT_WLGP1_SWIOMOD)
+#define BIT_CLEAR_WLGP1_SWIOMOD(x) ((x) & (~BITS_WLGP1_SWIOMOD))
+#define BIT_GET_WLGP1_SWIOMOD(x)                                               \
+	(((x) >> BIT_SHIFT_WLGP1_SWIOMOD) & BIT_MASK_WLGP1_SWIOMOD)
+#define BIT_SET_WLGP1_SWIOMOD(x, v)                                            \
+	(BIT_CLEAR_WLGP1_SWIOMOD(x) | BIT_WLGP1_SWIOMOD(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_GPIO_PIN_CTRL			(Offset 0x0044) */
+
+#define BIT_SHIFT_GPIO_IO_SEL_7_TO_0 16
+#define BIT_MASK_GPIO_IO_SEL_7_TO_0 0xff
+#define BIT_GPIO_IO_SEL_7_TO_0(x)                                              \
+	(((x) & BIT_MASK_GPIO_IO_SEL_7_TO_0) << BIT_SHIFT_GPIO_IO_SEL_7_TO_0)
+#define BITS_GPIO_IO_SEL_7_TO_0                                                \
+	(BIT_MASK_GPIO_IO_SEL_7_TO_0 << BIT_SHIFT_GPIO_IO_SEL_7_TO_0)
+#define BIT_CLEAR_GPIO_IO_SEL_7_TO_0(x) ((x) & (~BITS_GPIO_IO_SEL_7_TO_0))
+#define BIT_GET_GPIO_IO_SEL_7_TO_0(x)                                          \
+	(((x) >> BIT_SHIFT_GPIO_IO_SEL_7_TO_0) & BIT_MASK_GPIO_IO_SEL_7_TO_0)
+#define BIT_SET_GPIO_IO_SEL_7_TO_0(x, v)                                       \
+	(BIT_CLEAR_GPIO_IO_SEL_7_TO_0(x) | BIT_GPIO_IO_SEL_7_TO_0(v))
+
+#define BIT_SHIFT_GPIO_OUT_7_TO_0 8
+#define BIT_MASK_GPIO_OUT_7_TO_0 0xff
+#define BIT_GPIO_OUT_7_TO_0(x)                                                 \
+	(((x) & BIT_MASK_GPIO_OUT_7_TO_0) << BIT_SHIFT_GPIO_OUT_7_TO_0)
+#define BITS_GPIO_OUT_7_TO_0                                                   \
+	(BIT_MASK_GPIO_OUT_7_TO_0 << BIT_SHIFT_GPIO_OUT_7_TO_0)
+#define BIT_CLEAR_GPIO_OUT_7_TO_0(x) ((x) & (~BITS_GPIO_OUT_7_TO_0))
+#define BIT_GET_GPIO_OUT_7_TO_0(x)                                             \
+	(((x) >> BIT_SHIFT_GPIO_OUT_7_TO_0) & BIT_MASK_GPIO_OUT_7_TO_0)
+#define BIT_SET_GPIO_OUT_7_TO_0(x, v)                                          \
+	(BIT_CLEAR_GPIO_OUT_7_TO_0(x) | BIT_GPIO_OUT_7_TO_0(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_GPIO_PIN_CTRL			(Offset 0x0044) */
+
+#define BIT_SHIFT_GPIO_IN_7_TO_0 0
+#define BIT_MASK_GPIO_IN_7_TO_0 0xff
+#define BIT_GPIO_IN_7_TO_0(x)                                                  \
+	(((x) & BIT_MASK_GPIO_IN_7_TO_0) << BIT_SHIFT_GPIO_IN_7_TO_0)
+#define BITS_GPIO_IN_7_TO_0                                                    \
+	(BIT_MASK_GPIO_IN_7_TO_0 << BIT_SHIFT_GPIO_IN_7_TO_0)
+#define BIT_CLEAR_GPIO_IN_7_TO_0(x) ((x) & (~BITS_GPIO_IN_7_TO_0))
+#define BIT_GET_GPIO_IN_7_TO_0(x)                                              \
+	(((x) >> BIT_SHIFT_GPIO_IN_7_TO_0) & BIT_MASK_GPIO_IN_7_TO_0)
+#define BIT_SET_GPIO_IN_7_TO_0(x, v)                                           \
+	(BIT_CLEAR_GPIO_IN_7_TO_0(x) | BIT_GPIO_IN_7_TO_0(v))
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_SDIO_INDIRECT_REG_DATA		(Offset 0x10250044) */
+
+#define BIT_SHIFT_INDIRECT_REG_DATA 0
+#define BIT_MASK_INDIRECT_REG_DATA 0xffffffffL
+#define BIT_INDIRECT_REG_DATA(x)                                               \
+	(((x) & BIT_MASK_INDIRECT_REG_DATA) << BIT_SHIFT_INDIRECT_REG_DATA)
+#define BITS_INDIRECT_REG_DATA                                                 \
+	(BIT_MASK_INDIRECT_REG_DATA << BIT_SHIFT_INDIRECT_REG_DATA)
+#define BIT_CLEAR_INDIRECT_REG_DATA(x) ((x) & (~BITS_INDIRECT_REG_DATA))
+#define BIT_GET_INDIRECT_REG_DATA(x)                                           \
+	(((x) >> BIT_SHIFT_INDIRECT_REG_DATA) & BIT_MASK_INDIRECT_REG_DATA)
+#define BIT_SET_INDIRECT_REG_DATA(x, v)                                        \
+	(BIT_CLEAR_INDIRECT_REG_DATA(x) | BIT_INDIRECT_REG_DATA(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_GPIO_INTM				(Offset 0x0048) */
+
+#define BIT_SHIFT_MUXDBG_SEL 30
+#define BIT_MASK_MUXDBG_SEL 0x3
+#define BIT_MUXDBG_SEL(x) (((x) & BIT_MASK_MUXDBG_SEL) << BIT_SHIFT_MUXDBG_SEL)
+#define BITS_MUXDBG_SEL (BIT_MASK_MUXDBG_SEL << BIT_SHIFT_MUXDBG_SEL)
+#define BIT_CLEAR_MUXDBG_SEL(x) ((x) & (~BITS_MUXDBG_SEL))
+#define BIT_GET_MUXDBG_SEL(x)                                                  \
+	(((x) >> BIT_SHIFT_MUXDBG_SEL) & BIT_MASK_MUXDBG_SEL)
+#define BIT_SET_MUXDBG_SEL(x, v) (BIT_CLEAR_MUXDBG_SEL(x) | BIT_MUXDBG_SEL(v))
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_GPIO_INTM				(Offset 0x0048) */
+
+#define BIT_PCI_LPS_LDACT BIT(29)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT)
+
+/* 2 REG_GPIO_INTM				(Offset 0x0048) */
+
+#define BIT_SHIFT_MUXDBG_SEL2 28
+#define BIT_MASK_MUXDBG_SEL2 0x3
+#define BIT_MUXDBG_SEL2(x)                                                     \
+	(((x) & BIT_MASK_MUXDBG_SEL2) << BIT_SHIFT_MUXDBG_SEL2)
+#define BITS_MUXDBG_SEL2 (BIT_MASK_MUXDBG_SEL2 << BIT_SHIFT_MUXDBG_SEL2)
+#define BIT_CLEAR_MUXDBG_SEL2(x) ((x) & (~BITS_MUXDBG_SEL2))
+#define BIT_GET_MUXDBG_SEL2(x)                                                 \
+	(((x) >> BIT_SHIFT_MUXDBG_SEL2) & BIT_MASK_MUXDBG_SEL2)
+#define BIT_SET_MUXDBG_SEL2(x, v)                                              \
+	(BIT_CLEAR_MUXDBG_SEL2(x) | BIT_MUXDBG_SEL2(v))
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_GPIO_INTM				(Offset 0x0048) */
+
+#define BIT_GPIO_EXT_EN BIT(20)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT)
+
+/* 2 REG_GPIO_INTM				(Offset 0x0048) */
+
+#define BIT_EXTWOL1_SEL BIT(19)
+#define BIT_EXTWOL1_EN BIT(18)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_GPIO_INTM				(Offset 0x0048) */
+
+#define BIT_EXTWOL0_SEL BIT(17)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_GPIO_INTM				(Offset 0x0048) */
+
+#define BIT_BT_EXTWOL_DIS BIT(17)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_GPIO_INTM				(Offset 0x0048) */
+
+#define BIT_EXTWOL_SEL BIT(17)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_GPIO_INTM				(Offset 0x0048) */
+
+#define BIT_EXTWOL0_EN BIT(16)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_GPIO_INTM				(Offset 0x0048) */
+
+#define BIT_EXTWOL_EN BIT(16)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_GPIO_INTM				(Offset 0x0048) */
+
+#define BIT_SHIFT_GPIO_EXT_WOL_V1 16
+#define BIT_MASK_GPIO_EXT_WOL_V1 0xf
+#define BIT_GPIO_EXT_WOL_V1(x)                                                 \
+	(((x) & BIT_MASK_GPIO_EXT_WOL_V1) << BIT_SHIFT_GPIO_EXT_WOL_V1)
+#define BITS_GPIO_EXT_WOL_V1                                                   \
+	(BIT_MASK_GPIO_EXT_WOL_V1 << BIT_SHIFT_GPIO_EXT_WOL_V1)
+#define BIT_CLEAR_GPIO_EXT_WOL_V1(x) ((x) & (~BITS_GPIO_EXT_WOL_V1))
+#define BIT_GET_GPIO_EXT_WOL_V1(x)                                             \
+	(((x) >> BIT_SHIFT_GPIO_EXT_WOL_V1) & BIT_MASK_GPIO_EXT_WOL_V1)
+#define BIT_SET_GPIO_EXT_WOL_V1(x, v)                                          \
+	(BIT_CLEAR_GPIO_EXT_WOL_V1(x) | BIT_GPIO_EXT_WOL_V1(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_GPIO_INTM				(Offset 0x0048) */
+
+#define BIT_GPIOF_INT_MD BIT(15)
+#define BIT_GPIOE_INT_MD BIT(14)
+#define BIT_GPIOD_INT_MD BIT(13)
+#define BIT_GPIOC_INT_MD BIT(12)
+#define BIT_GPIOB_INT_MD BIT(11)
+#define BIT_GPIOA_INT_MD BIT(10)
+#define BIT_GPIO9_INT_MD BIT(9)
+#define BIT_GPIO8_INT_MD BIT(8)
+#define BIT_GPIO7_INT_MD BIT(7)
+#define BIT_GPIO6_INT_MD BIT(6)
+#define BIT_GPIO5_INT_MD BIT(5)
+#define BIT_GPIO4_INT_MD BIT(4)
+#define BIT_GPIO3_INT_MD BIT(3)
+#define BIT_GPIO2_INT_MD BIT(2)
+#define BIT_GPIO1_INT_MD BIT(1)
+#define BIT_GPIO0_INT_MD BIT(0)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_LED_CFG				(Offset 0x004C) */
+
+#define BIT_MAILBOX_1WIRE_GPIO_CFG BIT(31)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_LED_CFG				(Offset 0x004C) */
+
+#define BIT_PAD_ANTSEL_I BIT(31)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT)
+
+/* 2 REG_LED_CFG				(Offset 0x004C) */
+
+#define BIT_ANT_SEL7_EN BIT(30)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_LED_CFG				(Offset 0x004C) */
+
+#define BIT_BT_RF_GPIO_CFG BIT(30)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_LED_CFG				(Offset 0x004C) */
+
+#define BIT_PAD_ANTSELB_I BIT(30)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT)
+
+/* 2 REG_LED_CFG				(Offset 0x004C) */
+
+#define BIT_ANT_SEL46_EN BIT(29)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_LED_CFG				(Offset 0x004C) */
+
+#define BIT_BT_SDIO_INT_GPIO_CFG BIT(29)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_LED_CFG				(Offset 0x004C) */
+
+#define BIT_PAD_D_PAPE_2G_I BIT(29)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT)
+
+/* 2 REG_LED_CFG				(Offset 0x004C) */
+
+#define BIT_ANT_SEL3_EN BIT(28)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_LED_CFG				(Offset 0x004C) */
+
+#define BIT_MAILBOX_3WIRE_GPIO_CFG BIT(28)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_LED_CFG				(Offset 0x004C) */
+
+#define BIT_PAD_D_PAPE_5G_I BIT(28)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT)
+
+/* 2 REG_LED_CFG				(Offset 0x004C) */
+
+#define BIT_TRSW_SEL_EN BIT(27)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_LED_CFG				(Offset 0x004C) */
+
+#define BIT_WLBT_PAPE_SEL_EN BIT(27)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_LED_CFG				(Offset 0x004C) */
+
+#define BIT_PAD_D_TRSW_I BIT(27)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+
+/* 2 REG_LED_CFG				(Offset 0x004C) */
+
+#define BIT_GPIO3_WL_CTRL_EN BIT(27)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT)
+
+/* 2 REG_LED_CFG				(Offset 0x004C) */
+
+#define BIT_PAPE1_SEL_EN BIT(26)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_LED_CFG				(Offset 0x004C) */
+
+#define BIT_LNAON_SEL_EN BIT(26)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_LED_CFG				(Offset 0x004C) */
+
+#define BIT_PAD_D_TRSWB_I BIT(26)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT)
+
+/* 2 REG_LED_CFG				(Offset 0x004C) */
+
+#define BIT_PAPE0_SEL_EN BIT(25)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_LED_CFG				(Offset 0x004C) */
+
+#define BIT_PAPE_SEL_EN BIT(25)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_LED_CFG				(Offset 0x004C) */
+
+#define BIT_DWH_EN BIT(25)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT)
+
+/* 2 REG_LED_CFG				(Offset 0x004C) */
+
+#define BIT_ANTSEL2_EN BIT(24)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_LED_CFG				(Offset 0x004C) */
+
+#define BIT_ANT01_EN BIT(24)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_LED_CFG				(Offset 0x004C) */
+
+#define BIT_DPDT_WLBT_SEL BIT(24)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_LED_CFG				(Offset 0x004C) */
+
+#define BIT_DHW_EN BIT(24)
+
+#endif
+
+#if (HALMAC_8881A_SUPPORT)
+
+/* 2 REG_LED_CFG				(Offset 0x004C) */
+
+#define BIT_RFE_ANT_EXT_SEL BIT(24)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT)
+
+/* 2 REG_LED_CFG				(Offset 0x004C) */
+
+#define BIT_ANTSEL_EN BIT(23)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_LED_CFG				(Offset 0x004C) */
+
+#define BIT_DPDT_SEL_EN BIT(23)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_LED_CFG				(Offset 0x004C) */
+
+#define BIT_GPIO13_14_WL_CTRL_EN BIT(22)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_LED_CFG				(Offset 0x004C) */
+
+#define BIT_SW_SPDT_SEL BIT(22)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_LED_CFG				(Offset 0x004C) */
+
+#define BIT_LED2DIS_V1 BIT(22)
+
+#endif
+
+#if (HALMAC_8881A_SUPPORT)
+
+/* 2 REG_LED_CFG				(Offset 0x004C) */
+
+#define BIT_TRXIQ_DBG_EN BIT(22)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8881A_SUPPORT)
+
+/* 2 REG_LED_CFG				(Offset 0x004C) */
+
+#define BIT_LED2DIS BIT(21)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_LED_CFG				(Offset 0x004C) */
+
+#define BIT_LED0_GPIO_EN BIT(21)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_LED_CFG				(Offset 0x004C) */
+
+#define BIT_LED2EN BIT(21)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_LED_CFG				(Offset 0x004C) */
+
+#define BIT_LED2PL BIT(20)
+#define BIT_LED2SV BIT(19)
+
+#define BIT_SHIFT_LED2CM 16
+#define BIT_MASK_LED2CM 0x7
+#define BIT_LED2CM(x) (((x) & BIT_MASK_LED2CM) << BIT_SHIFT_LED2CM)
+#define BITS_LED2CM (BIT_MASK_LED2CM << BIT_SHIFT_LED2CM)
+#define BIT_CLEAR_LED2CM(x) ((x) & (~BITS_LED2CM))
+#define BIT_GET_LED2CM(x) (((x) >> BIT_SHIFT_LED2CM) & BIT_MASK_LED2CM)
+#define BIT_SET_LED2CM(x, v) (BIT_CLEAR_LED2CM(x) | BIT_LED2CM(v))
+
+#define BIT_LED1DIS BIT(15)
+#define BIT_LED1PL BIT(12)
+#define BIT_LED1SV BIT(11)
+
+#define BIT_SHIFT_LED1CM 8
+#define BIT_MASK_LED1CM 0x7
+#define BIT_LED1CM(x) (((x) & BIT_MASK_LED1CM) << BIT_SHIFT_LED1CM)
+#define BITS_LED1CM (BIT_MASK_LED1CM << BIT_SHIFT_LED1CM)
+#define BIT_CLEAR_LED1CM(x) ((x) & (~BITS_LED1CM))
+#define BIT_GET_LED1CM(x) (((x) >> BIT_SHIFT_LED1CM) & BIT_MASK_LED1CM)
+#define BIT_SET_LED1CM(x, v) (BIT_CLEAR_LED1CM(x) | BIT_LED1CM(v))
+
+#define BIT_LED0DIS BIT(7)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8881A_SUPPORT)
+
+/* 2 REG_LED_CFG				(Offset 0x004C) */
+
+#define BIT_SHIFT_AFE_LDO_SWR_CHECK 5
+#define BIT_MASK_AFE_LDO_SWR_CHECK 0x3
+#define BIT_AFE_LDO_SWR_CHECK(x)                                               \
+	(((x) & BIT_MASK_AFE_LDO_SWR_CHECK) << BIT_SHIFT_AFE_LDO_SWR_CHECK)
+#define BITS_AFE_LDO_SWR_CHECK                                                 \
+	(BIT_MASK_AFE_LDO_SWR_CHECK << BIT_SHIFT_AFE_LDO_SWR_CHECK)
+#define BIT_CLEAR_AFE_LDO_SWR_CHECK(x) ((x) & (~BITS_AFE_LDO_SWR_CHECK))
+#define BIT_GET_AFE_LDO_SWR_CHECK(x)                                           \
+	(((x) >> BIT_SHIFT_AFE_LDO_SWR_CHECK) & BIT_MASK_AFE_LDO_SWR_CHECK)
+#define BIT_SET_AFE_LDO_SWR_CHECK(x, v)                                        \
+	(BIT_CLEAR_AFE_LDO_SWR_CHECK(x) | BIT_AFE_LDO_SWR_CHECK(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_LED_CFG				(Offset 0x004C) */
+
+#define BIT_LED0PL BIT(4)
+#define BIT_LED0SV BIT(3)
+
+#define BIT_SHIFT_LED0CM 0
+#define BIT_MASK_LED0CM 0x7
+#define BIT_LED0CM(x) (((x) & BIT_MASK_LED0CM) << BIT_SHIFT_LED0CM)
+#define BITS_LED0CM (BIT_MASK_LED0CM << BIT_SHIFT_LED0CM)
+#define BIT_CLEAR_LED0CM(x) ((x) & (~BITS_LED0CM))
+#define BIT_GET_LED0CM(x) (((x) >> BIT_SHIFT_LED0CM) & BIT_MASK_LED0CM)
+#define BIT_SET_LED0CM(x, v) (BIT_CLEAR_LED0CM(x) | BIT_LED0CM(v))
+
+/* 2 REG_FSIMR				(Offset 0x0050) */
+
+#define BIT_FS_PDNINT_EN BIT(31)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+
+/* 2 REG_FSIMR				(Offset 0x0050) */
+
+#define BIT_NFC_INT_PAD_EN BIT(30)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8881A_SUPPORT)
+
+/* 2 REG_FSIMR				(Offset 0x0050) */
+
+#define BIT_FS_SPS_OCP_INT_EN BIT(29)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_FSIMR				(Offset 0x0050) */
+
+#define BIT_SW_SPS_OCP_INT_EN BIT(29)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8881A_SUPPORT)
+
+/* 2 REG_FSIMR				(Offset 0x0050) */
+
+#define BIT_FS_PWMERR_INT_EN BIT(28)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_FSIMR				(Offset 0x0050) */
+
+#define BIT_FS_PWM_HW_ERR_EN BIT(28)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8881A_SUPPORT)
+
+/* 2 REG_FSIMR				(Offset 0x0050) */
+
+#define BIT_FS_GPIOF_INT_EN BIT(27)
+#define BIT_FS_GPIOE_INT_EN BIT(26)
+#define BIT_FS_GPIOD_INT_EN BIT(25)
+#define BIT_FS_GPIOC_INT_EN BIT(24)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_FSIMR				(Offset 0x0050) */
+
+#define BIT_ACT2RECOVERY_INT_EN BIT(24)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8881A_SUPPORT)
+
+/* 2 REG_FSIMR				(Offset 0x0050) */
+
+#define BIT_FS_GPIOB_INT_EN BIT(23)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_FSIMR				(Offset 0x0050) */
+
+#define BIT_PCIE_GEN12_SWITCH_EN BIT(23)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8881A_SUPPORT)
+
+/* 2 REG_FSIMR				(Offset 0x0050) */
+
+#define BIT_FS_GPIOA_INT_EN BIT(22)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_FSIMR				(Offset 0x0050) */
+
+#define BIT_FS_HCI_SUS_EN_V1 BIT(22)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8881A_SUPPORT)
+
+/* 2 REG_FSIMR				(Offset 0x0050) */
+
+#define BIT_FS_GPIO9_INT_EN BIT(21)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_FSIMR				(Offset 0x0050) */
+
+#define BIT_FS_HCI_RES_EN_V1 BIT(21)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8881A_SUPPORT)
+
+/* 2 REG_FSIMR				(Offset 0x0050) */
+
+#define BIT_FS_GPIO8_INT_EN BIT(20)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_FSIMR				(Offset 0x0050) */
+
+#define BIT_FS_HCI_RESET_EN_V1 BIT(20)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8881A_SUPPORT)
+
+/* 2 REG_FSIMR				(Offset 0x0050) */
+
+#define BIT_FS_GPIO7_INT_EN BIT(19)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_FSIMR				(Offset 0x0050) */
+
+#define BIT_FS_32K_LEAVE_SETTING_EN BIT(19)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8881A_SUPPORT)
+
+/* 2 REG_FSIMR				(Offset 0x0050) */
+
+#define BIT_FS_GPIO6_INT_EN BIT(18)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_FSIMR				(Offset 0x0050) */
+
+#define BIT_FS_32K_ENTER_SETTING_EN BIT(18)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8881A_SUPPORT)
+
+/* 2 REG_FSIMR				(Offset 0x0050) */
+
+#define BIT_FS_GPIO5_INT_EN BIT(17)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_FSIMR				(Offset 0x0050) */
+
+#define BIT_FS_SIE_LPM_RSM_EN_V1 BIT(17)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8881A_SUPPORT)
+
+/* 2 REG_FSIMR				(Offset 0x0050) */
+
+#define BIT_FS_GPIO4_INT_EN BIT(16)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_FSIMR				(Offset 0x0050) */
+
+#define BIT_FS_SIE_LPM_ACT_EN_V1 BIT(16)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8881A_SUPPORT)
+
+/* 2 REG_FSIMR				(Offset 0x0050) */
+
+#define BIT_FS_GPIO3_INT_EN BIT(15)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_FSIMR				(Offset 0x0050) */
+
+#define BIT_FS_GPIOF_INT_EN_V1 BIT(15)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8881A_SUPPORT)
+
+/* 2 REG_FSIMR				(Offset 0x0050) */
+
+#define BIT_FS_GPIO2_INT_EN BIT(14)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_FSIMR				(Offset 0x0050) */
+
+#define BIT_FS_GPIOE_INT_EN_V1 BIT(14)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8881A_SUPPORT)
+
+/* 2 REG_FSIMR				(Offset 0x0050) */
+
+#define BIT_FS_GPIO1_INT_EN BIT(13)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_FSIMR				(Offset 0x0050) */
+
+#define BIT_FS_GPIOD_INT_EN_V1 BIT(13)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8881A_SUPPORT)
+
+/* 2 REG_FSIMR				(Offset 0x0050) */
+
+#define BIT_FS_GPIO0_INT_EN BIT(12)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_FSIMR				(Offset 0x0050) */
+
+#define BIT_FS_GPIOC_INT_EN_V1 BIT(12)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8881A_SUPPORT)
+
+/* 2 REG_FSIMR				(Offset 0x0050) */
+
+#define BIT_FS_HCI_SUS_EN BIT(11)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_FSIMR				(Offset 0x0050) */
+
+#define BIT_FS_GPIOB_INT_EN_V1 BIT(11)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8881A_SUPPORT)
+
+/* 2 REG_FSIMR				(Offset 0x0050) */
+
+#define BIT_FS_HCI_RES_EN BIT(10)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_FSIMR				(Offset 0x0050) */
+
+#define BIT_FS_GPIOA_INT_EN_V1 BIT(10)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8881A_SUPPORT)
+
+/* 2 REG_FSIMR				(Offset 0x0050) */
+
+#define BIT_FS_HCI_RESET_EN BIT(9)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_FSIMR				(Offset 0x0050) */
+
+#define BIT_FS_GPIO9_INT_EN_V1 BIT(9)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_FSIMR				(Offset 0x0050) */
+
+#define BIT_AXI_EXCEPT_FINT_EN BIT(8)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FSIMR				(Offset 0x0050) */
+
+#define BIT_USB_SCSI_CMD_EN BIT(8)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_FSIMR				(Offset 0x0050) */
+
+#define BIT_FS_GPIO8_INT_EN_V1 BIT(8)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FSIMR				(Offset 0x0050) */
+
+#define BIT_FS_BTON_STS_UPDATE_MSK_EN BIT(7)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_FSIMR				(Offset 0x0050) */
+
+#define BIT_FS_GPIO7_INT_EN_V1 BIT(7)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FSIMR				(Offset 0x0050) */
+
+#define BIT_ACT2RECOVERY_INT_EN_V1 BIT(6)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_FSIMR				(Offset 0x0050) */
+
+#define BIT_FS_GPIO6_INT_EN_V1 BIT(6)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_FSIMR				(Offset 0x0050) */
+
+#define BIT_FS_TRPC_TO_INT_EN BIT(5)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_FSIMR				(Offset 0x0050) */
+
+#define BIT_FS_GPIO5_INT_EN_V1 BIT(5)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_FSIMR				(Offset 0x0050) */
+
+#define BIT_FS_RPC_O_T_INT_EN BIT(4)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FSIMR				(Offset 0x0050) */
+
+#define BIT_HCI_TXDMA_REQ_HIMR BIT(4)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_FSIMR				(Offset 0x0050) */
+
+#define BIT_FS_GPIO4_INT_EN_V1 BIT(4)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8881A_SUPPORT)
+
+/* 2 REG_FSIMR				(Offset 0x0050) */
+
+#define BIT_FS_32K_LEAVE_SETTING_MAK BIT(3)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_FSIMR				(Offset 0x0050) */
+
+#define BIT_FS_GPIO3_INT_EN_V1 BIT(3)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8881A_SUPPORT)
+
+/* 2 REG_FSIMR				(Offset 0x0050) */
+
+#define BIT_FS_32K_ENTER_SETTING_MAK BIT(2)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_FSIMR				(Offset 0x0050) */
+
+#define BIT_FS_GPIO2_INT_EN_V1 BIT(2)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8881A_SUPPORT)
+
+/* 2 REG_FSIMR				(Offset 0x0050) */
+
+#define BIT_FS_USB_LPMRSM_MSK BIT(1)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_FSIMR				(Offset 0x0050) */
+
+#define BIT_FS_GPIO1_INT_EN_V1 BIT(1)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8881A_SUPPORT)
+
+/* 2 REG_FSIMR				(Offset 0x0050) */
+
+#define BIT_FS_USB_LPMINT_MSK BIT(0)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_FSIMR				(Offset 0x0050) */
+
+#define BIT_FS_GPIO0_INT_EN_V1 BIT(0)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_FSISR				(Offset 0x0054) */
+
+#define BIT_FS_PDNINT BIT(31)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8881A_SUPPORT)
+
+/* 2 REG_FSISR				(Offset 0x0054) */
+
+#define BIT_FS_SPS_OCP_INT BIT(29)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_FSISR				(Offset 0x0054) */
+
+#define BIT_SW_SPS_OCP_INT BIT(29)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8881A_SUPPORT)
+
+/* 2 REG_FSISR				(Offset 0x0054) */
+
+#define BIT_FS_PWMERR_INT BIT(28)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_FSISR				(Offset 0x0054) */
+
+#define BIT_FS_PWM_HW_ERR BIT(28)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8881A_SUPPORT)
+
+/* 2 REG_FSISR				(Offset 0x0054) */
+
+#define BIT_FS_GPIOF_INT BIT(27)
+#define BIT_FS_GPIOE_INT BIT(26)
+#define BIT_FS_GPIOD_INT BIT(25)
+#define BIT_FS_GPIOC_INT BIT(24)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_FSISR				(Offset 0x0054) */
+
+#define BIT_ACT2RECOVERY_INT BIT(24)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8881A_SUPPORT)
+
+/* 2 REG_FSISR				(Offset 0x0054) */
+
+#define BIT_FS_GPIOB_INT BIT(23)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_FSISR				(Offset 0x0054) */
+
+#define BIT_PCIE_GEN12_SWITCH BIT(23)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8881A_SUPPORT)
+
+/* 2 REG_FSISR				(Offset 0x0054) */
+
+#define BIT_FS_GPIOA_INT BIT(22)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_FSISR				(Offset 0x0054) */
+
+#define BIT_FS_HCI_SUS_V1 BIT(22)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8881A_SUPPORT)
+
+/* 2 REG_FSISR				(Offset 0x0054) */
+
+#define BIT_FS_GPIO9_INT BIT(21)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_FSISR				(Offset 0x0054) */
+
+#define BIT_FS_HCI_RES_V1 BIT(21)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8881A_SUPPORT)
+
+/* 2 REG_FSISR				(Offset 0x0054) */
+
+#define BIT_FS_GPIO8_INT BIT(20)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_FSISR				(Offset 0x0054) */
+
+#define BIT_FS_HCI_RESET_V1 BIT(20)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8881A_SUPPORT)
+
+/* 2 REG_FSISR				(Offset 0x0054) */
+
+#define BIT_FS_GPIO7_INT BIT(19)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_FSISR				(Offset 0x0054) */
+
+#define BIT_FS_32K_LEAVE_SETTING BIT(19)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8881A_SUPPORT)
+
+/* 2 REG_FSISR				(Offset 0x0054) */
+
+#define BIT_FS_GPIO6_INT BIT(18)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_FSISR				(Offset 0x0054) */
+
+#define BIT_FS_32K_ENTER_SETTING BIT(18)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8881A_SUPPORT)
+
+/* 2 REG_FSISR				(Offset 0x0054) */
+
+#define BIT_FS_GPIO5_INT BIT(17)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_FSISR				(Offset 0x0054) */
+
+#define BIT_FS_SIE_LPM_RSM_V1 BIT(17)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8881A_SUPPORT)
+
+/* 2 REG_FSISR				(Offset 0x0054) */
+
+#define BIT_FS_GPIO4_INT BIT(16)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_FSISR				(Offset 0x0054) */
+
+#define BIT_FS_SIE_LPM_ACT_V1 BIT(16)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8881A_SUPPORT)
+
+/* 2 REG_FSISR				(Offset 0x0054) */
+
+#define BIT_FS_GPIO3_INT BIT(15)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_FSISR				(Offset 0x0054) */
+
+#define BIT_FS_GPIOF_INT_V1 BIT(15)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8881A_SUPPORT)
+
+/* 2 REG_FSISR				(Offset 0x0054) */
+
+#define BIT_FS_GPIO2_INT BIT(14)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_FSISR				(Offset 0x0054) */
+
+#define BIT_FS_GPIOE_INT_V1 BIT(14)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8881A_SUPPORT)
+
+/* 2 REG_FSISR				(Offset 0x0054) */
+
+#define BIT_FS_GPIO1_INT BIT(13)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_FSISR				(Offset 0x0054) */
+
+#define BIT_FS_GPIOD_INT_V1 BIT(13)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8881A_SUPPORT)
+
+/* 2 REG_FSISR				(Offset 0x0054) */
+
+#define BIT_FS_GPIO0_INT BIT(12)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_FSISR				(Offset 0x0054) */
+
+#define BIT_FS_GPIOC_INT_V1 BIT(12)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8881A_SUPPORT)
+
+/* 2 REG_FSISR				(Offset 0x0054) */
+
+#define BIT_FS_HCI_SUS_INT BIT(11)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_FSISR				(Offset 0x0054) */
+
+#define BIT_FS_GPIOB_INT_V1 BIT(11)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8881A_SUPPORT)
+
+/* 2 REG_FSISR				(Offset 0x0054) */
+
+#define BIT_FS_HCI_RES_INT BIT(10)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_FSISR				(Offset 0x0054) */
+
+#define BIT_FS_GPIOA_INT_V1 BIT(10)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8881A_SUPPORT)
+
+/* 2 REG_FSISR				(Offset 0x0054) */
+
+#define BIT_FS_HCI_RESET_INT BIT(9)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_FSISR				(Offset 0x0054) */
+
+#define BIT_FS_GPIO9_INT_V1 BIT(9)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_FSISR				(Offset 0x0054) */
+
+#define BIT_AXI_EXCEPT_FINT BIT(8)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FSISR				(Offset 0x0054) */
+
+#define BIT_USB_SCSI_CMD_INT BIT(8)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_FSISR				(Offset 0x0054) */
+
+#define BIT_FS_GPIO8_INT_V1 BIT(8)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8814B_SUPPORT)
+
+/* 2 REG_FSISR				(Offset 0x0054) */
+
+#define BIT_FS_BTON_STS_UPDATE_INT BIT(7)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_FSISR				(Offset 0x0054) */
+
+#define BIT_FS_GPIO7_INT_V1 BIT(7)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_FSISR				(Offset 0x0054) */
+
+#define BIT_ACT2RECOVERY_INT_V1 BIT(6)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FSISR				(Offset 0x0054) */
+
+#define BIT_ACT2RECOVERY BIT(6)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_FSISR				(Offset 0x0054) */
+
+#define BIT_FS_GPIO6_INT_V1 BIT(6)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_FSISR				(Offset 0x0054) */
+
+#define BIT_FS_TRPC_TO_INT_INT BIT(5)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_FSISR				(Offset 0x0054) */
+
+#define BIT_FS_GPIO5_INT_V1 BIT(5)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_FSISR				(Offset 0x0054) */
+
+#define BIT_FS_RPC_O_T_INT_INT BIT(4)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FSISR				(Offset 0x0054) */
+
+#define BIT_HCI_TXDMA_REQ_HISR BIT(4)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_FSISR				(Offset 0x0054) */
+
+#define BIT_FS_GPIO4_INT_V1 BIT(4)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8881A_SUPPORT)
+
+/* 2 REG_FSISR				(Offset 0x0054) */
+
+#define BIT_FS_32K_LEAVE_SETTING_INT BIT(3)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_FSISR				(Offset 0x0054) */
+
+#define BIT_FS_GPIO3_INT_V1 BIT(3)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8881A_SUPPORT)
+
+/* 2 REG_FSISR				(Offset 0x0054) */
+
+#define BIT_FS_32K_ENTER_SETTING_INT BIT(2)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_FSISR				(Offset 0x0054) */
+
+#define BIT_FS_GPIO2_INT_V1 BIT(2)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8881A_SUPPORT)
+
+/* 2 REG_FSISR				(Offset 0x0054) */
+
+#define BIT_FS_USB_LPMRSM_INT BIT(1)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_FSISR				(Offset 0x0054) */
+
+#define BIT_FS_GPIO1_INT_V1 BIT(1)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8881A_SUPPORT)
+
+/* 2 REG_FSISR				(Offset 0x0054) */
+
+#define BIT_FS_USB_LPMINT_INT BIT(0)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_FSISR				(Offset 0x0054) */
+
+#define BIT_FS_GPIO0_INT_V1 BIT(0)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_HSIMR				(Offset 0x0058) */
+
+#define BIT_GPIOF_INT_EN BIT(31)
+#define BIT_GPIOE_INT_EN BIT(30)
+#define BIT_GPIOD_INT_EN BIT(29)
+#define BIT_GPIOC_INT_EN BIT(28)
+#define BIT_GPIOB_INT_EN BIT(27)
+#define BIT_GPIOA_INT_EN BIT(26)
+#define BIT_GPIO9_INT_EN BIT(25)
+#define BIT_GPIO8_INT_EN BIT(24)
+#define BIT_GPIO7_INT_EN BIT(23)
+#define BIT_GPIO6_INT_EN BIT(22)
+#define BIT_GPIO5_INT_EN BIT(21)
+#define BIT_GPIO4_INT_EN BIT(20)
+#define BIT_GPIO3_INT_EN BIT(19)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8881A_SUPPORT)
+
+/* 2 REG_HSIMR				(Offset 0x0058) */
+
+#define BIT_GPIO2_INT_EN BIT(18)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_HSIMR				(Offset 0x0058) */
+
+#define BIT_GPIO2_INT_EN_V1 BIT(18)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_HSIMR				(Offset 0x0058) */
+
+#define BIT_GPIO1_INT_EN BIT(17)
+#define BIT_GPIO0_INT_EN BIT(16)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_HSIMR				(Offset 0x0058) */
+
+#define BIT_AXI_EXCEPT_HINT_EN BIT(9)
+#define BIT_PDNINT_EN_V2 BIT(8)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_HSIMR				(Offset 0x0058) */
+
+#define BIT_PDNINT_EN BIT(7)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_HSIMR				(Offset 0x0058) */
+
+#define BIT_PDNINT_EN_V1 BIT(7)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_HSIMR				(Offset 0x0058) */
+
+#define BIT_PDN_INT_EN BIT(7)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8881A_SUPPORT)
+
+/* 2 REG_HSIMR				(Offset 0x0058) */
+
+#define BIT_RON_INT_EN BIT(6)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_HSIMR				(Offset 0x0058) */
+
+#define BIT_RON_INT_EN_V1 BIT(6)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8881A_SUPPORT)
+
+/* 2 REG_HSIMR				(Offset 0x0058) */
+
+#define BIT_SPS_OCP_INT_EN BIT(5)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_HSIMR				(Offset 0x0058) */
+
+#define BIT_SPS_OCP_INT_EN_V1 BIT(5)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8881A_SUPPORT)
+
+/* 2 REG_HSIMR				(Offset 0x0058) */
+
+#define BIT_GPIO15_0_INT_EN BIT(0)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_HSIMR				(Offset 0x0058) */
+
+#define BIT_GPIO15_0_INT_EN_V1 BIT(0)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_HSISR				(Offset 0x005C) */
+
+#define BIT_GPIOF_INT BIT(31)
+#define BIT_GPIOE_INT BIT(30)
+#define BIT_GPIOD_INT BIT(29)
+#define BIT_GPIOC_INT BIT(28)
+#define BIT_GPIOB_INT BIT(27)
+#define BIT_GPIOA_INT BIT(26)
+#define BIT_GPIO9_INT BIT(25)
+#define BIT_GPIO8_INT BIT(24)
+#define BIT_GPIO7_INT BIT(23)
+#define BIT_GPIO6_INT BIT(22)
+#define BIT_GPIO5_INT BIT(21)
+#define BIT_GPIO4_INT BIT(20)
+#define BIT_GPIO3_INT BIT(19)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8881A_SUPPORT)
+
+/* 2 REG_HSISR				(Offset 0x005C) */
+
+#define BIT_GPIO2_INT BIT(18)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_HSISR				(Offset 0x005C) */
+
+#define BIT_GPIO2_INT_V1 BIT(18)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_HSISR				(Offset 0x005C) */
+
+#define BIT_GPIO1_INT BIT(17)
+#define BIT_GPIO0_INT BIT(16)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_HSISR				(Offset 0x005C) */
+
+#define BIT_AXI_EXCEPT_HINT BIT(8)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_HSISR				(Offset 0x005C) */
+
+#define BIT_PDNINT BIT(7)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_HSISR				(Offset 0x005C) */
+
+#define BIT_PDNINT_V1 BIT(7)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_HSISR				(Offset 0x005C) */
+
+#define BIT_PDN_INT BIT(7)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8881A_SUPPORT)
+
+/* 2 REG_HSISR				(Offset 0x005C) */
+
+#define BIT_RON_INT BIT(6)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_HSISR				(Offset 0x005C) */
+
+#define BIT_RON_INT_V1 BIT(6)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8881A_SUPPORT)
+
+/* 2 REG_HSISR				(Offset 0x005C) */
+
+#define BIT_SPS_OCP_INT BIT(5)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_HSISR				(Offset 0x005C) */
+
+#define BIT_SPS_OCP_INT_V1 BIT(5)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8881A_SUPPORT)
+
+/* 2 REG_HSISR				(Offset 0x005C) */
+
+#define BIT_GPIO15_0_INT BIT(0)
+#define BIT_MCUFWDL_EN BIT(0)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_HSISR				(Offset 0x005C) */
+
+#define BIT_GPIO15_0_INT_V1 BIT(0)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_GPIO_EXT_CTRL			(Offset 0x0060) */
+
+#define BIT_SHIFT_GPIO_MOD_15_TO_8 24
+#define BIT_MASK_GPIO_MOD_15_TO_8 0xff
+#define BIT_GPIO_MOD_15_TO_8(x)                                                \
+	(((x) & BIT_MASK_GPIO_MOD_15_TO_8) << BIT_SHIFT_GPIO_MOD_15_TO_8)
+#define BITS_GPIO_MOD_15_TO_8                                                  \
+	(BIT_MASK_GPIO_MOD_15_TO_8 << BIT_SHIFT_GPIO_MOD_15_TO_8)
+#define BIT_CLEAR_GPIO_MOD_15_TO_8(x) ((x) & (~BITS_GPIO_MOD_15_TO_8))
+#define BIT_GET_GPIO_MOD_15_TO_8(x)                                            \
+	(((x) >> BIT_SHIFT_GPIO_MOD_15_TO_8) & BIT_MASK_GPIO_MOD_15_TO_8)
+#define BIT_SET_GPIO_MOD_15_TO_8(x, v)                                         \
+	(BIT_CLEAR_GPIO_MOD_15_TO_8(x) | BIT_GPIO_MOD_15_TO_8(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_GPIO_EXT_CTRL			(Offset 0x0060) */
+
+#define BIT_ROM_DLEN BIT(19)
+
+#define BIT_SHIFT_GPIO_IO_SEL_15_TO_8 16
+#define BIT_MASK_GPIO_IO_SEL_15_TO_8 0xff
+#define BIT_GPIO_IO_SEL_15_TO_8(x)                                             \
+	(((x) & BIT_MASK_GPIO_IO_SEL_15_TO_8) << BIT_SHIFT_GPIO_IO_SEL_15_TO_8)
+#define BITS_GPIO_IO_SEL_15_TO_8                                               \
+	(BIT_MASK_GPIO_IO_SEL_15_TO_8 << BIT_SHIFT_GPIO_IO_SEL_15_TO_8)
+#define BIT_CLEAR_GPIO_IO_SEL_15_TO_8(x) ((x) & (~BITS_GPIO_IO_SEL_15_TO_8))
+#define BIT_GET_GPIO_IO_SEL_15_TO_8(x)                                         \
+	(((x) >> BIT_SHIFT_GPIO_IO_SEL_15_TO_8) & BIT_MASK_GPIO_IO_SEL_15_TO_8)
+#define BIT_SET_GPIO_IO_SEL_15_TO_8(x, v)                                      \
+	(BIT_CLEAR_GPIO_IO_SEL_15_TO_8(x) | BIT_GPIO_IO_SEL_15_TO_8(v))
+
+#define BIT_SHIFT_ROM_PGE 16
+#define BIT_MASK_ROM_PGE 0x7
+#define BIT_ROM_PGE(x) (((x) & BIT_MASK_ROM_PGE) << BIT_SHIFT_ROM_PGE)
+#define BITS_ROM_PGE (BIT_MASK_ROM_PGE << BIT_SHIFT_ROM_PGE)
+#define BIT_CLEAR_ROM_PGE(x) ((x) & (~BITS_ROM_PGE))
+#define BIT_GET_ROM_PGE(x) (((x) >> BIT_SHIFT_ROM_PGE) & BIT_MASK_ROM_PGE)
+#define BIT_SET_ROM_PGE(x, v) (BIT_CLEAR_ROM_PGE(x) | BIT_ROM_PGE(v))
+
+#define BIT_SHIFT_GPIO_OUT_15_TO_8 8
+#define BIT_MASK_GPIO_OUT_15_TO_8 0xff
+#define BIT_GPIO_OUT_15_TO_8(x)                                                \
+	(((x) & BIT_MASK_GPIO_OUT_15_TO_8) << BIT_SHIFT_GPIO_OUT_15_TO_8)
+#define BITS_GPIO_OUT_15_TO_8                                                  \
+	(BIT_MASK_GPIO_OUT_15_TO_8 << BIT_SHIFT_GPIO_OUT_15_TO_8)
+#define BIT_CLEAR_GPIO_OUT_15_TO_8(x) ((x) & (~BITS_GPIO_OUT_15_TO_8))
+#define BIT_GET_GPIO_OUT_15_TO_8(x)                                            \
+	(((x) >> BIT_SHIFT_GPIO_OUT_15_TO_8) & BIT_MASK_GPIO_OUT_15_TO_8)
+#define BIT_SET_GPIO_OUT_15_TO_8(x, v)                                         \
+	(BIT_CLEAR_GPIO_OUT_15_TO_8(x) | BIT_GPIO_OUT_15_TO_8(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_GPIO_EXT_CTRL			(Offset 0x0060) */
+
+#define BIT_SHIFT_GPIO_IN_15_TO_8 0
+#define BIT_MASK_GPIO_IN_15_TO_8 0xff
+#define BIT_GPIO_IN_15_TO_8(x)                                                 \
+	(((x) & BIT_MASK_GPIO_IN_15_TO_8) << BIT_SHIFT_GPIO_IN_15_TO_8)
+#define BITS_GPIO_IN_15_TO_8                                                   \
+	(BIT_MASK_GPIO_IN_15_TO_8 << BIT_SHIFT_GPIO_IN_15_TO_8)
+#define BIT_CLEAR_GPIO_IN_15_TO_8(x) ((x) & (~BITS_GPIO_IN_15_TO_8))
+#define BIT_GET_GPIO_IN_15_TO_8(x)                                             \
+	(((x) >> BIT_SHIFT_GPIO_IN_15_TO_8) & BIT_MASK_GPIO_IN_15_TO_8)
+#define BIT_SET_GPIO_IN_15_TO_8(x, v)                                          \
+	(BIT_CLEAR_GPIO_IN_15_TO_8(x) | BIT_GPIO_IN_15_TO_8(v))
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_SDIO_H2C				(Offset 0x10250060) */
+
+#define BIT_SHIFT_SDIO_H2C_MSG 0
+#define BIT_MASK_SDIO_H2C_MSG 0xffffffffL
+#define BIT_SDIO_H2C_MSG(x)                                                    \
+	(((x) & BIT_MASK_SDIO_H2C_MSG) << BIT_SHIFT_SDIO_H2C_MSG)
+#define BITS_SDIO_H2C_MSG (BIT_MASK_SDIO_H2C_MSG << BIT_SHIFT_SDIO_H2C_MSG)
+#define BIT_CLEAR_SDIO_H2C_MSG(x) ((x) & (~BITS_SDIO_H2C_MSG))
+#define BIT_GET_SDIO_H2C_MSG(x)                                                \
+	(((x) >> BIT_SHIFT_SDIO_H2C_MSG) & BIT_MASK_SDIO_H2C_MSG)
+#define BIT_SET_SDIO_H2C_MSG(x, v)                                             \
+	(BIT_CLEAR_SDIO_H2C_MSG(x) | BIT_SDIO_H2C_MSG(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_PAD_CTRL1				(Offset 0x0064) */
+
+#define BIT_DATA_CPU_JTAG BIT(30)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_PAD_CTRL1				(Offset 0x0064) */
+
+#define BIT_PAPE_WLBT_SEL BIT(29)
+#define BIT_LNAON_WLBT_SEL BIT(28)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_PAD_CTRL1				(Offset 0x0064) */
+
+#define BIT_BDEN BIT(28)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_PAD_CTRL1				(Offset 0x0064) */
+
+#define BIT_BT_BQB_GPIO_SEL BIT(27)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_PAD_CTRL1				(Offset 0x0064) */
+
+#define BIT_BTGP_GPG3_FEN BIT(26)
+#define BIT_BTGP_GPG2_FEN BIT(25)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_PAD_CTRL1				(Offset 0x0064) */
+
+#define BIT_BTGP_JTAG_EN BIT(24)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_PAD_CTRL1				(Offset 0x0064) */
+
+#define BIT_BB2PP_ISO BIT(24)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_PAD_CTRL1				(Offset 0x0064) */
+
+#define BIT_XTAL_CLK_EXTARNAL_EN BIT(23)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_PAD_CTRL1				(Offset 0x0064) */
+
+#define BIT_BTBRI_UART_EN BIT(22)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_PAD_CTRL1				(Offset 0x0064) */
+
+#define BIT_BTGP_UART0_EN BIT(22)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_PAD_CTRL1				(Offset 0x0064) */
+
+#define BIT_BTGP_UART1_EN BIT(21)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_PAD_CTRL1				(Offset 0x0064) */
+
+#define BIT_BTCOEX_PU BIT(21)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_PAD_CTRL1				(Offset 0x0064) */
+
+#define BIT_BTGP_SPI_EN BIT(20)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_PAD_CTRL1				(Offset 0x0064) */
+
+#define BIT_EEPROM_SEL_PD BIT(20)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8881A_SUPPORT)
+
+/* 2 REG_PAD_CTRL1				(Offset 0x0064) */
+
+#define BIT_BTGP_GPIO_E2 BIT(19)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_PAD_CTRL1				(Offset 0x0064) */
+
+#define BIT_TST_MOD_PD BIT(19)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_PAD_CTRL1				(Offset 0x0064) */
+
+#define BIT_BTGP_GPIO_EN BIT(18)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_PAD_CTRL1				(Offset 0x0064) */
+
+#define BIT_BOOT_FLUSH_PD BIT(18)
+#define BIT_USB_XTAL_SEL1_PD BIT(17)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_PAD_CTRL1				(Offset 0x0064) */
+
+#define BIT_SHIFT_BTGP_GPIO_SL 16
+#define BIT_MASK_BTGP_GPIO_SL 0x3
+#define BIT_BTGP_GPIO_SL(x)                                                    \
+	(((x) & BIT_MASK_BTGP_GPIO_SL) << BIT_SHIFT_BTGP_GPIO_SL)
+#define BITS_BTGP_GPIO_SL (BIT_MASK_BTGP_GPIO_SL << BIT_SHIFT_BTGP_GPIO_SL)
+#define BIT_CLEAR_BTGP_GPIO_SL(x) ((x) & (~BITS_BTGP_GPIO_SL))
+#define BIT_GET_BTGP_GPIO_SL(x)                                                \
+	(((x) >> BIT_SHIFT_BTGP_GPIO_SL) & BIT_MASK_BTGP_GPIO_SL)
+#define BIT_SET_BTGP_GPIO_SL(x, v)                                             \
+	(BIT_CLEAR_BTGP_GPIO_SL(x) | BIT_BTGP_GPIO_SL(v))
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_PAD_CTRL1				(Offset 0x0064) */
+
+#define BIT_USB_XTAL_SEL0_PD BIT(16)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT)
+
+/* 2 REG_PAD_CTRL1				(Offset 0x0064) */
+
+#define BIT_HST_WKE_DEV_SL BIT(15)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_PAD_CTRL1				(Offset 0x0064) */
+
+#define BIT_BTSUSB_PL BIT(15)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_PAD_CTRL1				(Offset 0x0064) */
+
+#define BIT_WL_JTAG BIT(15)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_PAD_CTRL1				(Offset 0x0064) */
+
+#define BIT_PAD_SDIO_SR BIT(14)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_PAD_CTRL1				(Offset 0x0064) */
+
+#define BIT_GPIO14_OUTPUT_PL BIT(13)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_PAD_CTRL1				(Offset 0x0064) */
+
+#define BIT_SW_DEVWHOST_POLARITY BIT(13)
+
+#endif
+
+#if (HALMAC_8881A_SUPPORT)
+
+/* 2 REG_PAD_CTRL1				(Offset 0x0064) */
+
+#define BIT_GPIO15_OUTPUT_PL BIT(13)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8881A_SUPPORT)
+
+/* 2 REG_PAD_CTRL1				(Offset 0x0064) */
+
+#define BIT_HOST_WAKE_PAD_PULL_EN BIT(12)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_PAD_CTRL1				(Offset 0x0064) */
+
+#define BIT_HOST_WAKE_DEV_PLL_EN BIT(12)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_PAD_CTRL1				(Offset 0x0064) */
+
+#define BIT_HOST_WAKE_PAD_SL BIT(11)
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+/* 2 REG_PAD_CTRL1				(Offset 0x0064) */
+
+#define BIT_SW_TRSW_3 BIT(11)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_PAD_CTRL1				(Offset 0x0064) */
+
+#define BIT_HOST_WAKE_DEV_POLARITY BIT(11)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT)
+
+/* 2 REG_PAD_CTRL1				(Offset 0x0064) */
+
+#define BIT_PAD_TRSW_SR BIT(10)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8881A_SUPPORT)
+
+/* 2 REG_PAD_CTRL1				(Offset 0x0064) */
+
+#define BIT_PAD_LNAON_SR BIT(10)
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+/* 2 REG_PAD_CTRL1				(Offset 0x0064) */
+
+#define BIT_SW_TRSW_2 BIT(10)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT)
+
+/* 2 REG_PAD_CTRL1				(Offset 0x0064) */
+
+#define BIT_PAD_TRSW_E2 BIT(9)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8881A_SUPPORT)
+
+/* 2 REG_PAD_CTRL1				(Offset 0x0064) */
+
+#define BIT_PAD_LNAON_E2 BIT(9)
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+/* 2 REG_PAD_CTRL1				(Offset 0x0064) */
+
+#define BIT_SW_TRSW_1 BIT(9)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_PAD_CTRL1				(Offset 0x0064) */
+
+#define BIT_A_ANTSEL_SR BIT(9)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT)
+
+/* 2 REG_PAD_CTRL1				(Offset 0x0064) */
+
+#define BIT_SW_TRSW_P_SEL_DATA BIT(8)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_PAD_CTRL1				(Offset 0x0064) */
+
+#define BIT_SW_LNAON_G_SEL_DATA BIT(8)
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+/* 2 REG_PAD_CTRL1				(Offset 0x0064) */
+
+#define BIT_SW_TRSW_0 BIT(8)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_PAD_CTRL1				(Offset 0x0064) */
+
+#define BIT_A_ANTSEL_E2 BIT(8)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT)
+
+/* 2 REG_PAD_CTRL1				(Offset 0x0064) */
+
+#define BIT_SW_TRSW_N_SEL_DATA BIT(7)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_PAD_CTRL1				(Offset 0x0064) */
+
+#define BIT_SW_LNAON_A_SEL_DATA BIT(7)
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+/* 2 REG_PAD_CTRL1				(Offset 0x0064) */
+
+#define BIT_SW_PAPE_3 BIT(7)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_PAD_CTRL1				(Offset 0x0064) */
+
+#define BIT_D_PAPE_2G_SR BIT(7)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_PAD_CTRL1				(Offset 0x0064) */
+
+#define BIT_PAD_PAPE_SR BIT(6)
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+/* 2 REG_PAD_CTRL1				(Offset 0x0064) */
+
+#define BIT_SW_PAPE_2 BIT(6)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_PAD_CTRL1				(Offset 0x0064) */
+
+#define BIT_D_PAPE_5G_SR BIT(6)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_PAD_CTRL1				(Offset 0x0064) */
+
+#define BIT_PAD_PAPE_E2 BIT(5)
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+/* 2 REG_PAD_CTRL1				(Offset 0x0064) */
+
+#define BIT_SW_PAPE_1 BIT(5)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_PAD_CTRL1				(Offset 0x0064) */
+
+#define BIT_D_TRSW_SR BIT(5)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT)
+
+/* 2 REG_PAD_CTRL1				(Offset 0x0064) */
+
+#define BIT_SW_PAPE_1_SEL_DATA BIT(4)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_PAD_CTRL1				(Offset 0x0064) */
+
+#define BIT_SW_PAPE_G_SEL_DATA BIT(4)
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+/* 2 REG_PAD_CTRL1				(Offset 0x0064) */
+
+#define BIT_SW_PAPE_0 BIT(4)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_PAD_CTRL1				(Offset 0x0064) */
+
+#define BIT_D_TRSWB_SR BIT(4)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT)
+
+/* 2 REG_PAD_CTRL1				(Offset 0x0064) */
+
+#define BIT_SW_PAPE_0_SEL_DATA BIT(3)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_PAD_CTRL1				(Offset 0x0064) */
+
+#define BIT_SW_PAPE_A_SEL_DATA BIT(3)
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+/* 2 REG_PAD_CTRL1				(Offset 0x0064) */
+
+#define BIT_SW_ANTSEL_3 BIT(3)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_PAD_CTRL1				(Offset 0x0064) */
+
+#define BIT_D_PAPE_2G_E2 BIT(3)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT)
+
+/* 2 REG_PAD_CTRL1				(Offset 0x0064) */
+
+#define BIT_SW_ANTSEL_2_SEL_DATA BIT(2)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8881A_SUPPORT)
+
+/* 2 REG_PAD_CTRL1				(Offset 0x0064) */
+
+#define BIT_PAD_DPDT_SR BIT(2)
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+/* 2 REG_PAD_CTRL1				(Offset 0x0064) */
+
+#define BIT_SW_ANTSEL_2 BIT(2)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_PAD_CTRL1				(Offset 0x0064) */
+
+#define BIT_D_PAPE_5G_E2 BIT(2)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT)
+
+/* 2 REG_PAD_CTRL1				(Offset 0x0064) */
+
+#define BIT_SW_ANTSEL_N_SEL_DATA BIT(1)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_PAD_CTRL1				(Offset 0x0064) */
+
+#define BIT_PAD_DPDT_PAD_E2 BIT(1)
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+/* 2 REG_PAD_CTRL1				(Offset 0x0064) */
+
+#define BIT_SW_ANTSEL_1 BIT(1)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_PAD_CTRL1				(Offset 0x0064) */
+
+#define BIT_D_TRSW_E2 BIT(1)
+
+#endif
+
+#if (HALMAC_8881A_SUPPORT)
+
+/* 2 REG_PAD_CTRL1				(Offset 0x0064) */
+
+#define BIT_PAD_DPDT_E2 BIT(1)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT)
+
+/* 2 REG_PAD_CTRL1				(Offset 0x0064) */
+
+#define BIT_SW_ANTSEL_P_SEL_DATA BIT(0)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_PAD_CTRL1				(Offset 0x0064) */
+
+#define BIT_SW_DPDT_SEL_DATA BIT(0)
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+/* 2 REG_PAD_CTRL1				(Offset 0x0064) */
+
+#define BIT_SW_ANTSEL_0 BIT(0)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_SDIO_C2H				(Offset 0x10250064) */
+
+#define BIT_SHIFT_SDIO_C2H_MSG 0
+#define BIT_MASK_SDIO_C2H_MSG 0xffffffffL
+#define BIT_SDIO_C2H_MSG(x)                                                    \
+	(((x) & BIT_MASK_SDIO_C2H_MSG) << BIT_SHIFT_SDIO_C2H_MSG)
+#define BITS_SDIO_C2H_MSG (BIT_MASK_SDIO_C2H_MSG << BIT_SHIFT_SDIO_C2H_MSG)
+#define BIT_CLEAR_SDIO_C2H_MSG(x) ((x) & (~BITS_SDIO_C2H_MSG))
+#define BIT_GET_SDIO_C2H_MSG(x)                                                \
+	(((x) >> BIT_SHIFT_SDIO_C2H_MSG) & BIT_MASK_SDIO_C2H_MSG)
+#define BIT_SET_SDIO_C2H_MSG(x, v)                                             \
+	(BIT_CLEAR_SDIO_C2H_MSG(x) | BIT_SDIO_C2H_MSG(v))
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_PAD_CTRL1				(Offset 0x0064) */
+
+#define BIT_D_TRSWB_E2 BIT(0)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_WL_BT_PWR_CTRL			(Offset 0x0068) */
+
+#define BIT_ISO_BD2PP BIT(31)
+#define BIT_LDOV12B_EN BIT(30)
+#define BIT_CKEN_BTGPS BIT(29)
+#define BIT_FEN_BTGPS BIT(28)
+#define BIT_BTCPU_BOOTSEL BIT(27)
+#define BIT_SPI_SPEEDUP BIT(26)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_WL_BT_PWR_CTRL			(Offset 0x0068) */
+
+#define BIT_BT_LPS_EN BIT(25)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_WL_BT_PWR_CTRL			(Offset 0x0068) */
+
+#define BIT_BT_LDO_MODE BIT(25)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_WL_BT_PWR_CTRL			(Offset 0x0068) */
+
+#define BIT_BT_SUS BIT(25)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_WL_BT_PWR_CTRL			(Offset 0x0068) */
+
+#define BIT_DEVWAKE_PAD_TYPE_SEL BIT(24)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_WL_BT_PWR_CTRL			(Offset 0x0068) */
+
+#define BIT_CLKREQ_PAD_PL BIT(23)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_WL_BT_PWR_CTRL			(Offset 0x0068) */
+
+#define BIT_CLKREQ_PAD_TYPE_SEL BIT(23)
+
+#endif
+
+#if (HALMAC_8881A_SUPPORT)
+
+/* 2 REG_WL_BT_PWR_CTRL			(Offset 0x0068) */
+
+#define BIT_CKSL_BZSLP BIT(23)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_WL_BT_PWR_CTRL			(Offset 0x0068) */
+
+#define BIT_EN_CPL_TIMEOUT_PS BIT(22)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT)
+
+/* 2 REG_WL_BT_PWR_CTRL			(Offset 0x0068) */
+
+#define BIT_BT_WAKE_HST_EN BIT(22)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_WL_BT_PWR_CTRL			(Offset 0x0068) */
+
+#define BIT_BTGP_WAKE_HST_EN BIT(22)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_WL_BT_PWR_CTRL			(Offset 0x0068) */
+
+#define BIT_ISO_BTPON2PP BIT(22)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_WL_BT_PWR_CTRL			(Offset 0x0068) */
+
+#define BIT_REG_TXDMA_FAIL_PS BIT(21)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT)
+
+/* 2 REG_WL_BT_PWR_CTRL			(Offset 0x0068) */
+
+#define BIT_WAKE_BT_EN BIT(21)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_WL_BT_PWR_CTRL			(Offset 0x0068) */
+
+#define BIT_BTGP_WAKE_BT_EN BIT(21)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_WL_BT_PWR_CTRL			(Offset 0x0068) */
+
+#define BIT_BTCOEX_CMD BIT(21)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT)
+
+/* 2 REG_WL_BT_PWR_CTRL			(Offset 0x0068) */
+
+#define BIT_EN_BT BIT(20)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_WL_BT_PWR_CTRL			(Offset 0x0068) */
+
+#define BIT_BTGP_EN BIT(20)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_WL_BT_PWR_CTRL			(Offset 0x0068) */
+
+#define BIT_BT_UART_INTF BIT(20)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_WL_BT_PWR_CTRL			(Offset 0x0068) */
+
+#define BIT_EN_HWENTR_L1 BIT(19)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT)
+
+/* 2 REG_WL_BT_PWR_CTRL			(Offset 0x0068) */
+
+#define BIT_BT_SUSN_EN BIT(19)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_WL_BT_PWR_CTRL			(Offset 0x0068) */
+
+#define BIT_BTGP_SUS_EN BIT(19)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_WL_BT_PWR_CTRL			(Offset 0x0068) */
+
+#define BIT_BT_HWROF_EN BIT(19)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_WL_BT_PWR_CTRL			(Offset 0x0068) */
+
+#define BIT_S3_RF_HW_EN BIT(19)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_WL_BT_PWR_CTRL			(Offset 0x0068) */
+
+#define BIT_EN_ADV_CLKGATE BIT(18)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8881A_SUPPORT)
+
+/* 2 REG_WL_BT_PWR_CTRL			(Offset 0x0068) */
+
+#define BIT_BT_FUNC_EN BIT(18)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_WL_BT_PWR_CTRL			(Offset 0x0068) */
+
+#define BIT_S2_RF_HW_EN BIT(18)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8881A_SUPPORT)
+
+/* 2 REG_WL_BT_PWR_CTRL			(Offset 0x0068) */
+
+#define BIT_BT_HWPDN_SL BIT(17)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_WL_BT_PWR_CTRL			(Offset 0x0068) */
+
+#define BIT_S1_RF_HW_EN BIT(17)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_WL_BT_PWR_CTRL			(Offset 0x0068) */
+
+#define BIT_BT_DISN_EN BIT(16)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_WL_BT_PWR_CTRL			(Offset 0x0068) */
+
+#define BIT_BT_HWPDEN BIT(16)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_WL_BT_PWR_CTRL			(Offset 0x0068) */
+
+#define BIT_S0_RF_HW_EN BIT(16)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8881A_SUPPORT)
+
+/* 2 REG_WL_BT_PWR_CTRL			(Offset 0x0068) */
+
+#define BIT_BT_PDN_PULL_EN BIT(15)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_WL_BT_PWR_CTRL			(Offset 0x0068) */
+
+#define BIT_WL_PDN_PULL_EN BIT(14)
+#define BIT_EXTERNAL_REQUEST_PL BIT(13)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8881A_SUPPORT)
+
+/* 2 REG_WL_BT_PWR_CTRL			(Offset 0x0068) */
+
+#define BIT_GPIO0_2_3_PULL_LOW_EN BIT(12)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_WL_BT_PWR_CTRL			(Offset 0x0068) */
+
+#define BIT_ISO_BA2PP BIT(11)
+#define BIT_BT_AFE_LDO_EN BIT(10)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_WL_BT_PWR_CTRL			(Offset 0x0068) */
+
+#define BIT_PDN_PIN_SEL BIT(10)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT)
+
+/* 2 REG_WL_BT_PWR_CTRL			(Offset 0x0068) */
+
+#define BIT_GPIO11_PULL_LOW_EN BIT(9)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_WL_BT_PWR_CTRL			(Offset 0x0068) */
+
+#define BIT_BT_AFE_PLL_EN BIT(9)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT)
+
+/* 2 REG_WL_BT_PWR_CTRL			(Offset 0x0068) */
+
+#define BIT_GPIO4_PULL_LOW_EN BIT(8)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_WL_BT_PWR_CTRL			(Offset 0x0068) */
+
+#define BIT_BT_DIG_CLK_EN BIT(8)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT)
+
+/* 2 REG_WL_BT_PWR_CTRL			(Offset 0x0068) */
+
+#define BIT_BT_WAKE_HST_SL BIT(7)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_WL_BT_PWR_CTRL			(Offset 0x0068) */
+
+#define BIT_BT_WAKE_HST_PL BIT(7)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_WL_BT_PWR_CTRL			(Offset 0x0068) */
+
+#define BIT_ASSERT_SPS_EN BIT(7)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_WL_BT_PWR_CTRL			(Offset 0x0068) */
+
+#define BIT_UART_BRIDGE BIT(7)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT)
+
+/* 2 REG_WL_BT_PWR_CTRL			(Offset 0x0068) */
+
+#define BIT_WAKE_BT_SL BIT(6)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_WL_BT_PWR_CTRL			(Offset 0x0068) */
+
+#define BIT_WAKE_BT_PL BIT(6)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_WL_BT_PWR_CTRL			(Offset 0x0068) */
+
+#define BIT_WLAN_32K_SEL BIT(6)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_WL_BT_PWR_CTRL			(Offset 0x0068) */
+
+#define BIT_MASK_CHIPEN BIT(6)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_WL_BT_PWR_CTRL			(Offset 0x0068) */
+
+#define BIT_OSC32K_CTRL_SEL BIT(6)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_WL_BT_PWR_CTRL			(Offset 0x0068) */
+
+#define BIT_WL_DRV_EXIST_IDX BIT(5)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_WL_BT_PWR_CTRL			(Offset 0x0068) */
+
+#define BIT_ASSERT_RF_EN BIT(5)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_WL_BT_PWR_CTRL			(Offset 0x0068) */
+
+#define BIT_DOP_EHPAD BIT(4)
+
+#endif
+
+#if (HALMAC_8881A_SUPPORT)
+
+/* 2 REG_WL_BT_PWR_CTRL			(Offset 0x0068) */
+
+#define BIT_BIT_DOP_EHPAD BIT(4)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8881A_SUPPORT)
+
+/* 2 REG_WL_BT_PWR_CTRL			(Offset 0x0068) */
+
+#define BIT_WL_HWROF_EN BIT(3)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_WL_BT_PWR_CTRL			(Offset 0x0068) */
+
+#define BIT_SDIO_PAD_SHUTDOWNB BIT(3)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8881A_SUPPORT)
+
+/* 2 REG_WL_BT_PWR_CTRL			(Offset 0x0068) */
+
+#define BIT_WL_FUNC_EN BIT(2)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_WL_BT_PWR_CTRL			(Offset 0x0068) */
+
+#define BIT_SDIO_CLK_SMT BIT(2)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8881A_SUPPORT)
+
+/* 2 REG_WL_BT_PWR_CTRL			(Offset 0x0068) */
+
+#define BIT_WL_HWPDN_SL BIT(1)
+#define BIT_WL_HWPDN_EN BIT(0)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_SDM_DEBUG				(Offset 0x006C) */
+
+#define BIT_SHIFT_F0N 23
+#define BIT_MASK_F0N 0x7
+#define BIT_F0N(x) (((x) & BIT_MASK_F0N) << BIT_SHIFT_F0N)
+#define BITS_F0N (BIT_MASK_F0N << BIT_SHIFT_F0N)
+#define BIT_CLEAR_F0N(x) ((x) & (~BITS_F0N))
+#define BIT_GET_F0N(x) (((x) >> BIT_SHIFT_F0N) & BIT_MASK_F0N)
+#define BIT_SET_F0N(x, v) (BIT_CLEAR_F0N(x) | BIT_F0N(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_SDM_DEBUG				(Offset 0x006C) */
+
+#define BIT_BT_WAKE_DEV_EN_V1 BIT(19)
+#define BIT_BT_WAKE_HST_EN_V1 BIT(18)
+#define BIT_BT_WAKE_HST_PL_V1 BIT(17)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_GSSR				(Offset 0x006C) */
+
+#define BIT_SHIFT_GPIO_15_TO_0_VAL 16
+#define BIT_MASK_GPIO_15_TO_0_VAL 0xffff
+#define BIT_GPIO_15_TO_0_VAL(x)                                                \
+	(((x) & BIT_MASK_GPIO_15_TO_0_VAL) << BIT_SHIFT_GPIO_15_TO_0_VAL)
+#define BITS_GPIO_15_TO_0_VAL                                                  \
+	(BIT_MASK_GPIO_15_TO_0_VAL << BIT_SHIFT_GPIO_15_TO_0_VAL)
+#define BIT_CLEAR_GPIO_15_TO_0_VAL(x) ((x) & (~BITS_GPIO_15_TO_0_VAL))
+#define BIT_GET_GPIO_15_TO_0_VAL(x)                                            \
+	(((x) >> BIT_SHIFT_GPIO_15_TO_0_VAL) & BIT_MASK_GPIO_15_TO_0_VAL)
+#define BIT_SET_GPIO_15_TO_0_VAL(x, v)                                         \
+	(BIT_CLEAR_GPIO_15_TO_0_VAL(x) | BIT_GPIO_15_TO_0_VAL(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_SDM_DEBUG				(Offset 0x006C) */
+
+#define BIT_BT_CLKREQ_EN_V1 BIT(16)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_SDM_DEBUG				(Offset 0x006C) */
+
+#define BIT_SHIFT_F0F 10
+#define BIT_MASK_F0F 0x1fff
+#define BIT_F0F(x) (((x) & BIT_MASK_F0F) << BIT_SHIFT_F0F)
+#define BITS_F0F (BIT_MASK_F0F << BIT_SHIFT_F0F)
+#define BIT_CLEAR_F0F(x) ((x) & (~BITS_F0F))
+#define BIT_GET_F0F(x) (((x) >> BIT_SHIFT_F0F) & BIT_MASK_F0F)
+#define BIT_SET_F0F(x, v) (BIT_CLEAR_F0F(x) | BIT_F0F(v))
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_SDM_DEBUG				(Offset 0x006C) */
+
+#define BIT_GPIO_IE_V18 BIT(10)
+#define BIT_PCIE_IE_V18 BIT(9)
+#define BIT_UART_IE_V18 BIT(8)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_SDM_DEBUG				(Offset 0x006C) */
+
+#define BIT_SHIFT_DIVN 4
+#define BIT_MASK_DIVN 0x3f
+#define BIT_DIVN(x) (((x) & BIT_MASK_DIVN) << BIT_SHIFT_DIVN)
+#define BITS_DIVN (BIT_MASK_DIVN << BIT_SHIFT_DIVN)
+#define BIT_CLEAR_DIVN(x) ((x) & (~BITS_DIVN))
+#define BIT_GET_DIVN(x) (((x) >> BIT_SHIFT_DIVN) & BIT_MASK_DIVN)
+#define BIT_SET_DIVN(x, v) (BIT_CLEAR_DIVN(x) | BIT_DIVN(v))
+
+#define BIT_SHIFT_BB_DBG_SEL_AFE_SDM 0
+#define BIT_MASK_BB_DBG_SEL_AFE_SDM 0xf
+#define BIT_BB_DBG_SEL_AFE_SDM(x)                                              \
+	(((x) & BIT_MASK_BB_DBG_SEL_AFE_SDM) << BIT_SHIFT_BB_DBG_SEL_AFE_SDM)
+#define BITS_BB_DBG_SEL_AFE_SDM                                                \
+	(BIT_MASK_BB_DBG_SEL_AFE_SDM << BIT_SHIFT_BB_DBG_SEL_AFE_SDM)
+#define BIT_CLEAR_BB_DBG_SEL_AFE_SDM(x) ((x) & (~BITS_BB_DBG_SEL_AFE_SDM))
+#define BIT_GET_BB_DBG_SEL_AFE_SDM(x)                                          \
+	(((x) >> BIT_SHIFT_BB_DBG_SEL_AFE_SDM) & BIT_MASK_BB_DBG_SEL_AFE_SDM)
+#define BIT_SET_BB_DBG_SEL_AFE_SDM(x, v)                                       \
+	(BIT_CLEAR_BB_DBG_SEL_AFE_SDM(x) | BIT_BB_DBG_SEL_AFE_SDM(v))
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_SDM_DEBUG				(Offset 0x006C) */
+
+#define BIT_SHIFT_WLCLK_PHASE 0
+#define BIT_MASK_WLCLK_PHASE 0x1f
+#define BIT_WLCLK_PHASE(x)                                                     \
+	(((x) & BIT_MASK_WLCLK_PHASE) << BIT_SHIFT_WLCLK_PHASE)
+#define BITS_WLCLK_PHASE (BIT_MASK_WLCLK_PHASE << BIT_SHIFT_WLCLK_PHASE)
+#define BIT_CLEAR_WLCLK_PHASE(x) ((x) & (~BITS_WLCLK_PHASE))
+#define BIT_GET_WLCLK_PHASE(x)                                                 \
+	(((x) >> BIT_SHIFT_WLCLK_PHASE) & BIT_MASK_WLCLK_PHASE)
+#define BIT_SET_WLCLK_PHASE(x, v)                                              \
+	(BIT_CLEAR_WLCLK_PHASE(x) | BIT_WLCLK_PHASE(v))
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_GSSR				(Offset 0x006C) */
+
+#define BIT_SHIFT_GPIO_15_TO_0_EN 0
+#define BIT_MASK_GPIO_15_TO_0_EN 0xffff
+#define BIT_GPIO_15_TO_0_EN(x)                                                 \
+	(((x) & BIT_MASK_GPIO_15_TO_0_EN) << BIT_SHIFT_GPIO_15_TO_0_EN)
+#define BITS_GPIO_15_TO_0_EN                                                   \
+	(BIT_MASK_GPIO_15_TO_0_EN << BIT_SHIFT_GPIO_15_TO_0_EN)
+#define BIT_CLEAR_GPIO_15_TO_0_EN(x) ((x) & (~BITS_GPIO_15_TO_0_EN))
+#define BIT_GET_GPIO_15_TO_0_EN(x)                                             \
+	(((x) >> BIT_SHIFT_GPIO_15_TO_0_EN) & BIT_MASK_GPIO_15_TO_0_EN)
+#define BIT_SET_GPIO_15_TO_0_EN(x, v)                                          \
+	(BIT_CLEAR_GPIO_15_TO_0_EN(x) | BIT_GPIO_15_TO_0_EN(v))
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_SYS_SDIO_CTRL			(Offset 0x0070) */
+
+#define BIT_FORCE_RST_PCIE_APHY BIT(30)
+#define BIT_FORCE_OFF_EPC BIT(29)
+#define BIT_PTA_3W_MODE BIT(28)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_SYS_CLKR				(Offset 0x0070) */
+
+#define BIT_BBRSTB_STANDBY_V1 BIT(28)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_SYS_SDIO_CTRL			(Offset 0x0070) */
+
+#define BIT_DBG_GNT_WL_BT BIT(27)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_SYS_CLKR				(Offset 0x0070) */
+
+#define BIT_AFE_PORT3_ISO BIT(27)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_SYS_SDIO_CTRL			(Offset 0x0070) */
+
+#define BIT_LTE_MUX_CTRL_PATH BIT(26)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_SYS_CLKR				(Offset 0x0070) */
+
+#define BIT_AFE_PORT2_ISO BIT(26)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_SYS_SDIO_CTRL			(Offset 0x0070) */
+
+#define BIT_LTE_COEX_EN BIT(25)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_SYS_SDIO_CTRL			(Offset 0x0070) */
+
+#define BIT_LTE_COEX_UART BIT(25)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_SYS_CLKR				(Offset 0x0070) */
+
+#define BIT_AFE_PORT1_ISO BIT(25)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_SYS_SDIO_CTRL			(Offset 0x0070) */
+
+#define BIT_3W_LTE_GPIO_EN BIT(24)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_SYS_SDIO_CTRL			(Offset 0x0070) */
+
+#define BIT_3W_LTE_WL_GPIO BIT(24)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_SYS_CLKR				(Offset 0x0070) */
+
+#define BIT_AFE_PORT0_ISO BIT(24)
+#define BIT_USB_PWR_OFF_SEL BIT(23)
+#define BIT_USB_HOST_PWR_OFF_EN_V1 BIT(22)
+#define BIT_SYM_LPS_BLOCK_EN_V1 BIT(21)
+#define BIT_USB_LPM_ACT_EN_V1 BIT(20)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_SYS_SDIO_CTRL			(Offset 0x0070) */
+
+#define BIT_SDIO_INT_POLARITY BIT(19)
+#define BIT_SDIO_INT BIT(18)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8881A_SUPPORT)
+
+/* 2 REG_SYS_SDIO_CTRL			(Offset 0x0070) */
+
+#define BIT_SDIO_OFF_EN BIT(17)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_SYS_CLKR				(Offset 0x0070) */
+
+#define BIT_SDIO_OFF_EN_V1 BIT(17)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8881A_SUPPORT)
+
+/* 2 REG_SYS_SDIO_CTRL			(Offset 0x0070) */
+
+#define BIT_SDIO_ON_EN BIT(16)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_SYS_CLKR				(Offset 0x0070) */
+
+#define BIT_SDIO_ON_EN_V1 BIT(16)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_SYS_SDIO_CTRL			(Offset 0x0070) */
+
+#define BIT_PCIE_FORCE_PWR_NGAT BIT(13)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_SYS_CLKR				(Offset 0x0070) */
+
+#define BIT_DIS_U3MB_INU2 BIT(13)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_SYS_SDIO_CTRL			(Offset 0x0070) */
+
+#define BIT_PCIE_CALIB_EN_V1 BIT(12)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_SYS_CLKR				(Offset 0x0070) */
+
+#define BIT_USB3_MDIO_EN BIT(12)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_SYS_SDIO_CTRL			(Offset 0x0070) */
+
+#define BIT_PAGE3_AUXCLK_GATE BIT(11)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_SYS_CLKR				(Offset 0x0070) */
+
+#define BIT_USB3_BG_EN BIT(11)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_SYS_SDIO_CTRL			(Offset 0x0070) */
+
+#define BIT_PCIE_WAIT_TIMEOUT_EVENT BIT(10)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_SYS_CLKR				(Offset 0x0070) */
+
+#define BIT_USB3_MB_EN BIT(10)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_SYS_SDIO_CTRL			(Offset 0x0070) */
+
+#define BIT_PCIE_WAIT_TIME BIT(9)
+#define BIT_MPCIE_REFCLK_XTAL_SEL BIT(8)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_SYS_CLKR				(Offset 0x0070) */
+
+#define BIT_SHIFT_USB3_CK_MD 8
+#define BIT_MASK_USB3_CK_MD 0x3
+#define BIT_USB3_CK_MD(x) (((x) & BIT_MASK_USB3_CK_MD) << BIT_SHIFT_USB3_CK_MD)
+#define BITS_USB3_CK_MD (BIT_MASK_USB3_CK_MD << BIT_SHIFT_USB3_CK_MD)
+#define BIT_CLEAR_USB3_CK_MD(x) ((x) & (~BITS_USB3_CK_MD))
+#define BIT_GET_USB3_CK_MD(x)                                                  \
+	(((x) >> BIT_SHIFT_USB3_CK_MD) & BIT_MASK_USB3_CK_MD)
+#define BIT_SET_USB3_CK_MD(x, v) (BIT_CLEAR_USB3_CK_MD(x) | BIT_USB3_CK_MD(v))
+
+#define BIT_USB3_CKBUF BIT(7)
+#define BIT_USB3_IBX_EN BIT(6)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_SYS_SDIO_CTRL			(Offset 0x0070) */
+
+#define BIT_BT_CLKREQ_EN BIT(6)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_SYS_SDIO_CTRL			(Offset 0x0070) */
+
+#define BIT_BT_CTRL_USB_PWR_BACKDOOR BIT(5)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_SYS_CLKR				(Offset 0x0070) */
+
+#define BIT_U3_MB_MASK BIT(5)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_SYS_SDIO_CTRL			(Offset 0x0070) */
+
+#define BIT_USB_D_STATE_HOLD BIT(4)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_SYS_CLKR				(Offset 0x0070) */
+
+#define BIT_U3_BG_MASK BIT(4)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_SYS_SDIO_CTRL			(Offset 0x0070) */
+
+#define BIT_SHIFT_USB_CKREF_CML_R 4
+#define BIT_MASK_USB_CKREF_CML_R 0x3
+#define BIT_USB_CKREF_CML_R(x)                                                 \
+	(((x) & BIT_MASK_USB_CKREF_CML_R) << BIT_SHIFT_USB_CKREF_CML_R)
+#define BITS_USB_CKREF_CML_R                                                   \
+	(BIT_MASK_USB_CKREF_CML_R << BIT_SHIFT_USB_CKREF_CML_R)
+#define BIT_CLEAR_USB_CKREF_CML_R(x) ((x) & (~BITS_USB_CKREF_CML_R))
+#define BIT_GET_USB_CKREF_CML_R(x)                                             \
+	(((x) >> BIT_SHIFT_USB_CKREF_CML_R) & BIT_MASK_USB_CKREF_CML_R)
+#define BIT_SET_USB_CKREF_CML_R(x, v)                                          \
+	(BIT_CLEAR_USB_CKREF_CML_R(x) | BIT_USB_CKREF_CML_R(v))
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_SYS_SDIO_CTRL			(Offset 0x0070) */
+
+#define BIT_REG_FORCE_DP BIT(3)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_SYS_CLKR				(Offset 0x0070) */
+
+#define BIT_DIS_USB3_MB_POLLING BIT(3)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_SYS_SDIO_CTRL			(Offset 0x0070) */
+
+#define BIT_BTGP_CLKREQ_EN BIT(2)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_SYS_SDIO_CTRL			(Offset 0x0070) */
+
+#define BIT_REG_DP_MODE BIT(2)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_SYS_CLKR				(Offset 0x0070) */
+
+#define BIT_PDN_MASK BIT(2)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_SYS_SDIO_CTRL			(Offset 0x0070) */
+
+#define BIT_SHIFT_USB_CKREF_D2S_I 2
+#define BIT_MASK_USB_CKREF_D2S_I 0x3
+#define BIT_USB_CKREF_D2S_I(x)                                                 \
+	(((x) & BIT_MASK_USB_CKREF_D2S_I) << BIT_SHIFT_USB_CKREF_D2S_I)
+#define BITS_USB_CKREF_D2S_I                                                   \
+	(BIT_MASK_USB_CKREF_D2S_I << BIT_SHIFT_USB_CKREF_D2S_I)
+#define BIT_CLEAR_USB_CKREF_D2S_I(x) ((x) & (~BITS_USB_CKREF_D2S_I))
+#define BIT_GET_USB_CKREF_D2S_I(x)                                             \
+	(((x) >> BIT_SHIFT_USB_CKREF_D2S_I) & BIT_MASK_USB_CKREF_D2S_I)
+#define BIT_SET_USB_CKREF_D2S_I(x, v)                                          \
+	(BIT_CLEAR_USB_CKREF_D2S_I(x) | BIT_USB_CKREF_D2S_I(v))
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_SYS_SDIO_CTRL			(Offset 0x0070) */
+
+#define BIT_USB_INSTALL_EN BIT(1)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_SYS_SDIO_CTRL			(Offset 0x0070) */
+
+#define BIT_RES_USB_MASS_STORAGE_DESC BIT(1)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_SYS_CLKR				(Offset 0x0070) */
+
+#define BIT_NO_PDN_CHIPOFF BIT(1)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_SYS_SDIO_CTRL			(Offset 0x0070) */
+
+#define BIT_USB_BT_CLKSEL BIT(0)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_SYS_SDIO_CTRL			(Offset 0x0070) */
+
+#define BIT_USB_WAIT_TIME BIT(0)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_SYS_CLKR				(Offset 0x0070) */
+
+#define BIT_PDN_HCOUNT BIT(0)
+
+#endif
+
+#if (HALMAC_8822B_SUPPORT)
+
+/* 2 REG_SYS_SDIO_CTRL			(Offset 0x0070) */
+
+#define BIT_SHIFT_SI_AUTHORIZATION 0
+#define BIT_MASK_SI_AUTHORIZATION 0xff
+#define BIT_SI_AUTHORIZATION(x)                                                \
+	(((x) & BIT_MASK_SI_AUTHORIZATION) << BIT_SHIFT_SI_AUTHORIZATION)
+#define BITS_SI_AUTHORIZATION                                                  \
+	(BIT_MASK_SI_AUTHORIZATION << BIT_SHIFT_SI_AUTHORIZATION)
+#define BIT_CLEAR_SI_AUTHORIZATION(x) ((x) & (~BITS_SI_AUTHORIZATION))
+#define BIT_GET_SI_AUTHORIZATION(x)                                            \
+	(((x) >> BIT_SHIFT_SI_AUTHORIZATION) & BIT_MASK_SI_AUTHORIZATION)
+#define BIT_SET_SI_AUTHORIZATION(x, v)                                         \
+	(BIT_CLEAR_SI_AUTHORIZATION(x) | BIT_SI_AUTHORIZATION(v))
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_HCI_OPT_CTRL			(Offset 0x0074) */
+
+#define BIT_SHIFT_HCI_RATIO 30
+#define BIT_MASK_HCI_RATIO 0x3
+#define BIT_HCI_RATIO(x) (((x) & BIT_MASK_HCI_RATIO) << BIT_SHIFT_HCI_RATIO)
+#define BITS_HCI_RATIO (BIT_MASK_HCI_RATIO << BIT_SHIFT_HCI_RATIO)
+#define BIT_CLEAR_HCI_RATIO(x) ((x) & (~BITS_HCI_RATIO))
+#define BIT_GET_HCI_RATIO(x) (((x) >> BIT_SHIFT_HCI_RATIO) & BIT_MASK_HCI_RATIO)
+#define BIT_SET_HCI_RATIO(x, v) (BIT_CLEAR_HCI_RATIO(x) | BIT_HCI_RATIO(v))
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_HCI_OPT_CTRL			(Offset 0x0074) */
+
+#define BIT_SHIFT_TSFT_SEL 29
+#define BIT_MASK_TSFT_SEL 0x7
+#define BIT_TSFT_SEL(x) (((x) & BIT_MASK_TSFT_SEL) << BIT_SHIFT_TSFT_SEL)
+#define BITS_TSFT_SEL (BIT_MASK_TSFT_SEL << BIT_SHIFT_TSFT_SEL)
+#define BIT_CLEAR_TSFT_SEL(x) ((x) & (~BITS_TSFT_SEL))
+#define BIT_GET_TSFT_SEL(x) (((x) >> BIT_SHIFT_TSFT_SEL) & BIT_MASK_TSFT_SEL)
+#define BIT_SET_TSFT_SEL(x, v) (BIT_CLEAR_TSFT_SEL(x) | BIT_TSFT_SEL(v))
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_HCI_OPT_CTRL			(Offset 0x0074) */
+
+#define BIT_SHIFT_WAIT_HPOW_TIME 28
+#define BIT_MASK_WAIT_HPOW_TIME 0x3
+#define BIT_WAIT_HPOW_TIME(x)                                                  \
+	(((x) & BIT_MASK_WAIT_HPOW_TIME) << BIT_SHIFT_WAIT_HPOW_TIME)
+#define BITS_WAIT_HPOW_TIME                                                    \
+	(BIT_MASK_WAIT_HPOW_TIME << BIT_SHIFT_WAIT_HPOW_TIME)
+#define BIT_CLEAR_WAIT_HPOW_TIME(x) ((x) & (~BITS_WAIT_HPOW_TIME))
+#define BIT_GET_WAIT_HPOW_TIME(x)                                              \
+	(((x) >> BIT_SHIFT_WAIT_HPOW_TIME) & BIT_MASK_WAIT_HPOW_TIME)
+#define BIT_SET_WAIT_HPOW_TIME(x, v)                                           \
+	(BIT_CLEAR_WAIT_HPOW_TIME(x) | BIT_WAIT_HPOW_TIME(v))
+
+#endif
+
+#if (HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_HCI_OPT_CTRL			(Offset 0x0074) */
+
+#define BIT_SHIFT_XTAL_SEL_0_V1 28
+#define BIT_MASK_XTAL_SEL_0_V1 0xf
+#define BIT_XTAL_SEL_0_V1(x)                                                   \
+	(((x) & BIT_MASK_XTAL_SEL_0_V1) << BIT_SHIFT_XTAL_SEL_0_V1)
+#define BITS_XTAL_SEL_0_V1 (BIT_MASK_XTAL_SEL_0_V1 << BIT_SHIFT_XTAL_SEL_0_V1)
+#define BIT_CLEAR_XTAL_SEL_0_V1(x) ((x) & (~BITS_XTAL_SEL_0_V1))
+#define BIT_GET_XTAL_SEL_0_V1(x)                                               \
+	(((x) >> BIT_SHIFT_XTAL_SEL_0_V1) & BIT_MASK_XTAL_SEL_0_V1)
+#define BIT_SET_XTAL_SEL_0_V1(x, v)                                            \
+	(BIT_CLEAR_XTAL_SEL_0_V1(x) | BIT_XTAL_SEL_0_V1(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_HCI_OPT_CTRL			(Offset 0x0074) */
+
+#define BIT_TSFT_BAND_SEL BIT(28)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_HCI_OPT_CTRL			(Offset 0x0074) */
+
+#define BIT_PCIE_HPOW_OPT2 BIT(27)
+
+#endif
+
+#if (HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_HCI_OPT_CTRL			(Offset 0x0074) */
+
+#define BIT_ISO_RFC2RF_3 BIT(27)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_HCI_OPT_CTRL			(Offset 0x0074) */
+
+#define BIT_PCIE_HPOW_OPT1 BIT(26)
+
+#endif
+
+#if (HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_HCI_OPT_CTRL			(Offset 0x0074) */
+
+#define BIT_ISO_RFC2RF_2 BIT(26)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_HCI_OPT_CTRL			(Offset 0x0074) */
+
+#define BIT_PCIE_HPOW_OPT0 BIT(25)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_HCI_OPT_CTRL			(Offset 0x0074) */
+
+#define BIT_SHIFT_RPWM 24
+#define BIT_MASK_RPWM 0xff
+#define BIT_RPWM(x) (((x) & BIT_MASK_RPWM) << BIT_SHIFT_RPWM)
+#define BITS_RPWM (BIT_MASK_RPWM << BIT_SHIFT_RPWM)
+#define BIT_CLEAR_RPWM(x) ((x) & (~BITS_RPWM))
+#define BIT_GET_RPWM(x) (((x) >> BIT_SHIFT_RPWM) & BIT_MASK_RPWM)
+#define BIT_SET_RPWM(x, v) (BIT_CLEAR_RPWM(x) | BIT_RPWM(v))
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_HCI_OPT_CTRL			(Offset 0x0074) */
+
+#define BIT_PCIE_EPC_ISO BIT(24)
+#define BIT_PCIE_EPC_OPT BIT(23)
+#define BIT_PCIE_SUS_OPT BIT(22)
+#define BIT_PCIE_L1OF_OPT BIT(21)
+#define BIT_PCIE_L1OF_LDOA BIT(20)
+#define BIT_USB_SUS_LDOA BIT(19)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_HCI_OPT_CTRL			(Offset 0x0074) */
+
+#define BIT_SDIO_PAD_E5 BIT(18)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_HCI_OPT_CTRL			(Offset 0x0074) */
+
+#define BIT_USB_HOST_PWR_OFF_SEL BIT(13)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT)
+
+/* 2 REG_HCI_OPT_CTRL			(Offset 0x0074) */
+
+#define BIT_R_FORCE_CLK_U3 BIT(13)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_HCI_OPT_CTRL			(Offset 0x0074) */
+
+#define BIT_USB_HOST_PWR_OFF_EN BIT(12)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT)
+
+/* 2 REG_HCI_OPT_CTRL			(Offset 0x0074) */
+
+#define BIT_R_USB2_AUTOLOAD BIT(12)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8881A_SUPPORT)
+
+/* 2 REG_HCI_OPT_CTRL			(Offset 0x0074) */
+
+#define BIT_SYM_LPS_BLOCK_EN BIT(11)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT)
+
+/* 2 REG_HCI_OPT_CTRL			(Offset 0x0074) */
+
+#define BIT_FORCE_U2CK BIT(11)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8881A_SUPPORT)
+
+/* 2 REG_HCI_OPT_CTRL			(Offset 0x0074) */
+
+#define BIT_USB_LPM_ACT_EN BIT(10)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_HCI_OPT_CTRL			(Offset 0x0074) */
+
+#define BIT_FORCE_CLK BIT(10)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8881A_SUPPORT)
+
+/* 2 REG_HCI_OPT_CTRL			(Offset 0x0074) */
+
+#define BIT_USB_LPM_NY BIT(9)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_HCI_OPT_CTRL			(Offset 0x0074) */
+
+#define BIT_IBX_EN_VALUE BIT(9)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_HCI_OPT_CTRL			(Offset 0x0074) */
+
+#define BIT_U2_FORCE BIT(9)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8881A_SUPPORT)
+
+/* 2 REG_HCI_OPT_CTRL			(Offset 0x0074) */
+
+#define BIT_USB_SUS_DIS BIT(8)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_HCI_OPT_CTRL			(Offset 0x0074) */
+
+#define BIT_IB_EN_VALUE BIT(8)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_HCI_OPT_CTRL			(Offset 0x0074) */
+
+#define BIT_U3_FORCE BIT(8)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_HCI_OPT_CTRL			(Offset 0x0074) */
+
+#define BIT_EN_LW_PWR BIT(6)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_HCI_OPT_CTRL			(Offset 0x0074) */
+
+#define BIT_SHIFT_SDIO_PAD_E 5
+#define BIT_MASK_SDIO_PAD_E 0x7
+#define BIT_SDIO_PAD_E(x) (((x) & BIT_MASK_SDIO_PAD_E) << BIT_SHIFT_SDIO_PAD_E)
+#define BITS_SDIO_PAD_E (BIT_MASK_SDIO_PAD_E << BIT_SHIFT_SDIO_PAD_E)
+#define BIT_CLEAR_SDIO_PAD_E(x) ((x) & (~BITS_SDIO_PAD_E))
+#define BIT_GET_SDIO_PAD_E(x)                                                  \
+	(((x) >> BIT_SHIFT_SDIO_PAD_E) & BIT_MASK_SDIO_PAD_E)
+#define BIT_SET_SDIO_PAD_E(x, v) (BIT_CLEAR_SDIO_PAD_E(x) | BIT_SDIO_PAD_E(v))
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_HCI_OPT_CTRL			(Offset 0x0074) */
+
+#define BIT_EN_REGU BIT(5)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8881A_SUPPORT)
+
+/* 2 REG_HCI_OPT_CTRL			(Offset 0x0074) */
+
+#define BIT_USB_LPPLL_EN BIT(4)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_HCI_OPT_CTRL			(Offset 0x0074) */
+
+#define BIT_FORCED_IB_EN BIT(4)
+#define BIT_EN_PC BIT(4)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_HCI_OPT_CTRL			(Offset 0x0074) */
+
+#define BIT_SDIO_H3L1 BIT(4)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_HCI_OPT_CTRL			(Offset 0x0074) */
+
+#define BIT_PERST_SYNC_EN BIT(3)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_HCI_OPT_CTRL			(Offset 0x0074) */
+
+#define BIT_USB1_1_USB2_0_DECISION BIT(3)
+#define BIT_EN_REGBG BIT(3)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8881A_SUPPORT)
+
+/* 2 REG_HCI_OPT_CTRL			(Offset 0x0074) */
+
+#define BIT_ROP_SW15 BIT(2)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_HCI_OPT_CTRL			(Offset 0x0074) */
+
+#define BIT_REG_BG_LPF BIT(2)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_HCI_OPT_CTRL			(Offset 0x0074) */
+
+#define BIT_SHIFT_USB23_SW_MODE 2
+#define BIT_MASK_USB23_SW_MODE 0x3
+#define BIT_USB23_SW_MODE(x)                                                   \
+	(((x) & BIT_MASK_USB23_SW_MODE) << BIT_SHIFT_USB23_SW_MODE)
+#define BITS_USB23_SW_MODE (BIT_MASK_USB23_SW_MODE << BIT_SHIFT_USB23_SW_MODE)
+#define BIT_CLEAR_USB23_SW_MODE(x) ((x) & (~BITS_USB23_SW_MODE))
+#define BIT_GET_USB23_SW_MODE(x)                                               \
+	(((x) >> BIT_SHIFT_USB23_SW_MODE) & BIT_MASK_USB23_SW_MODE)
+#define BIT_SET_USB23_SW_MODE(x, v)                                            \
+	(BIT_CLEAR_USB23_SW_MODE(x) | BIT_USB23_SW_MODE(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8881A_SUPPORT)
+
+/* 2 REG_HCI_OPT_CTRL			(Offset 0x0074) */
+
+#define BIT_PCI_CKRDY_OPT BIT(1)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_HCI_OPT_CTRL			(Offset 0x0074) */
+
+#define BIT_PCLK_VLD_SEL BIT(1)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8881A_SUPPORT)
+
+/* 2 REG_HCI_OPT_CTRL			(Offset 0x0074) */
+
+#define BIT_PCI_VAUX_EN BIT(0)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_HCI_OPT_CTRL			(Offset 0x0074) */
+
+#define BIT_SHIFT_REG_BG 0
+#define BIT_MASK_REG_BG 0x3
+#define BIT_REG_BG(x) (((x) & BIT_MASK_REG_BG) << BIT_SHIFT_REG_BG)
+#define BITS_REG_BG (BIT_MASK_REG_BG << BIT_SHIFT_REG_BG)
+#define BIT_CLEAR_REG_BG(x) ((x) & (~BITS_REG_BG))
+#define BIT_GET_REG_BG(x) (((x) >> BIT_SHIFT_REG_BG) & BIT_MASK_REG_BG)
+#define BIT_SET_REG_BG(x, v) (BIT_CLEAR_REG_BG(x) | BIT_REG_BG(v))
+
+#define BIT_SHIFT_REG_VADJ 0
+#define BIT_MASK_REG_VADJ 0xf
+#define BIT_REG_VADJ(x) (((x) & BIT_MASK_REG_VADJ) << BIT_SHIFT_REG_VADJ)
+#define BITS_REG_VADJ (BIT_MASK_REG_VADJ << BIT_SHIFT_REG_VADJ)
+#define BIT_CLEAR_REG_VADJ(x) ((x) & (~BITS_REG_VADJ))
+#define BIT_GET_REG_VADJ(x) (((x) >> BIT_SHIFT_REG_VADJ) & BIT_MASK_REG_VADJ)
+#define BIT_SET_REG_VADJ(x, v) (BIT_CLEAR_REG_VADJ(x) | BIT_REG_VADJ(v))
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_HCI_OPT_CTRL			(Offset 0x0074) */
+
+#define BIT_VAUX_EN BIT(0)
+
+/* 2 REG_AFE_XTAL_CTRL_EXT			(Offset 0x0078) */
+
+#define BIT_SDM_ORDER BIT(30)
+#define BIT_XTAL_DRV_RF_LATCH_V1 BIT(29)
+#define BIT_XTAL_VDD_SEL_V1 BIT(28)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_AFE_CTRL4				(Offset 0x0078) */
+
+#define BIT_XTAL_DRV_RF_LATCH BIT(27)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_AFE_XTAL_CTRL_EXT			(Offset 0x0078) */
+
+#define BIT_XQSEL_RF_AWAKE_V1 BIT(27)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_AFE_CTRL4				(Offset 0x0078) */
+
+#define BIT_XTAL_VDD_SEL BIT(26)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_AFE_CTRL4				(Offset 0x0078) */
+
+#define BIT_RF1_SDMRSTB BIT(26)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_AFE_XTAL_CTRL_EXT			(Offset 0x0078) */
+
+#define BIT_GATED_XTAL_OK0_V1 BIT(26)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT)
+
+/* 2 REG_AFE_CTRL4				(Offset 0x0078) */
+
+#define BIT_XQSEL_RF BIT(25)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_AFE_CTRL4				(Offset 0x0078) */
+
+#define BIT_RF1_RSTB BIT(25)
+
+#endif
+
+#if (HALMAC_8881A_SUPPORT)
+
+/* 2 REG_AFE_CTRL4				(Offset 0x0078) */
+
+#define BIT_XQSEL_RF_AWAKE BIT(25)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT)
+
+/* 2 REG_AFE_CTRL4				(Offset 0x0078) */
+
+#define BIT_XQSEL_RF_INITIAL BIT(24)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_AFE_CTRL4				(Offset 0x0078) */
+
+#define BIT_RF1_EN BIT(24)
+
+#endif
+
+#if (HALMAC_8881A_SUPPORT)
+
+/* 2 REG_AFE_CTRL4				(Offset 0x0078) */
+
+#define BIT_XQSEL_BIT1 BIT(24)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT)
+
+/* 2 REG_AFE_CTRL4				(Offset 0x0078) */
+
+#define BIT_REG_VREF_SEL BIT(23)
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+/* 2 REG_AFE_CTRL4				(Offset 0x0078) */
+
+#define BIT_DITHER_SDM_BIT3 BIT(23)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_AFE_XTAL_CTRL_EXT			(Offset 0x0078) */
+
+#define BIT_SHIFT_F0N_2_TO_0 23
+#define BIT_MASK_F0N_2_TO_0 0x7
+#define BIT_F0N_2_TO_0(x) (((x) & BIT_MASK_F0N_2_TO_0) << BIT_SHIFT_F0N_2_TO_0)
+#define BITS_F0N_2_TO_0 (BIT_MASK_F0N_2_TO_0 << BIT_SHIFT_F0N_2_TO_0)
+#define BIT_CLEAR_F0N_2_TO_0(x) ((x) & (~BITS_F0N_2_TO_0))
+#define BIT_GET_F0N_2_TO_0(x)                                                  \
+	(((x) >> BIT_SHIFT_F0N_2_TO_0) & BIT_MASK_F0N_2_TO_0)
+#define BIT_SET_F0N_2_TO_0(x, v) (BIT_CLEAR_F0N_2_TO_0(x) | BIT_F0N_2_TO_0(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT)
+
+/* 2 REG_AFE_CTRL4				(Offset 0x0078) */
+
+#define BIT_REG_LPFEN BIT(22)
+#define BIT_REG_KVCO BIT(21)
+#define BIT_XTAL_DRV_AGPIO_BIT1 BIT(20)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_AFE_CTRL4				(Offset 0x0078) */
+
+#define BIT_SHIFT_XTAL_LDO 20
+#define BIT_MASK_XTAL_LDO 0x7
+#define BIT_XTAL_LDO(x) (((x) & BIT_MASK_XTAL_LDO) << BIT_SHIFT_XTAL_LDO)
+#define BITS_XTAL_LDO (BIT_MASK_XTAL_LDO << BIT_SHIFT_XTAL_LDO)
+#define BIT_CLEAR_XTAL_LDO(x) ((x) & (~BITS_XTAL_LDO))
+#define BIT_GET_XTAL_LDO(x) (((x) >> BIT_SHIFT_XTAL_LDO) & BIT_MASK_XTAL_LDO)
+#define BIT_SET_XTAL_LDO(x, v) (BIT_CLEAR_XTAL_LDO(x) | BIT_XTAL_LDO(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT)
+
+/* 2 REG_AFE_CTRL4				(Offset 0x0078) */
+
+#define BIT_XTAL_DRV_AGPIO_BIT0 BIT(19)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_AFE_CTRL4				(Offset 0x0078) */
+
+#define BIT_XTAL_GRF2 BIT(18)
+#define BIT_REG_REF_SEL BIT(17)
+#define BIT_REG_320_SEL BIT(16)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_AFE_CTRL4				(Offset 0x0078) */
+
+#define BIT_ADC_CK_SYNC_EN BIT(16)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_AFE_CTRL4				(Offset 0x0078) */
+
+#define BIT_EN_SYM BIT(15)
+
+#define BIT_SHIFT_IOFFSET 10
+#define BIT_MASK_IOFFSET 0x1f
+#define BIT_IOFFSET(x) (((x) & BIT_MASK_IOFFSET) << BIT_SHIFT_IOFFSET)
+#define BITS_IOFFSET (BIT_MASK_IOFFSET << BIT_SHIFT_IOFFSET)
+#define BIT_CLEAR_IOFFSET(x) ((x) & (~BITS_IOFFSET))
+#define BIT_GET_IOFFSET(x) (((x) >> BIT_SHIFT_IOFFSET) & BIT_MASK_IOFFSET)
+#define BIT_SET_IOFFSET(x, v) (BIT_CLEAR_IOFFSET(x) | BIT_IOFFSET(v))
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+/* 2 REG_AFE_CTRL4				(Offset 0x0078) */
+
+#define BIT_RF2_SDMRSTB BIT(10)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_AFE_XTAL_CTRL_EXT			(Offset 0x0078) */
+
+#define BIT_SHIFT_F0F_12_TO_0 10
+#define BIT_MASK_F0F_12_TO_0 0x1fff
+#define BIT_F0F_12_TO_0(x)                                                     \
+	(((x) & BIT_MASK_F0F_12_TO_0) << BIT_SHIFT_F0F_12_TO_0)
+#define BITS_F0F_12_TO_0 (BIT_MASK_F0F_12_TO_0 << BIT_SHIFT_F0F_12_TO_0)
+#define BIT_CLEAR_F0F_12_TO_0(x) ((x) & (~BITS_F0F_12_TO_0))
+#define BIT_GET_F0F_12_TO_0(x)                                                 \
+	(((x) >> BIT_SHIFT_F0F_12_TO_0) & BIT_MASK_F0F_12_TO_0)
+#define BIT_SET_F0F_12_TO_0(x, v)                                              \
+	(BIT_CLEAR_F0F_12_TO_0(x) | BIT_F0F_12_TO_0(v))
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+/* 2 REG_AFE_CTRL4				(Offset 0x0078) */
+
+#define BIT_RF2_RSTB BIT(9)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_AFE_CTRL4				(Offset 0x0078) */
+
+#define BIT_SHIFT_APLL_FREF_SEL_BIT_2_TO_1 8
+#define BIT_MASK_APLL_FREF_SEL_BIT_2_TO_1 0x3
+#define BIT_APLL_FREF_SEL_BIT_2_TO_1(x)                                        \
+	(((x) & BIT_MASK_APLL_FREF_SEL_BIT_2_TO_1)                             \
+	 << BIT_SHIFT_APLL_FREF_SEL_BIT_2_TO_1)
+#define BITS_APLL_FREF_SEL_BIT_2_TO_1                                          \
+	(BIT_MASK_APLL_FREF_SEL_BIT_2_TO_1                                     \
+	 << BIT_SHIFT_APLL_FREF_SEL_BIT_2_TO_1)
+#define BIT_CLEAR_APLL_FREF_SEL_BIT_2_TO_1(x)                                  \
+	((x) & (~BITS_APLL_FREF_SEL_BIT_2_TO_1))
+#define BIT_GET_APLL_FREF_SEL_BIT_2_TO_1(x)                                    \
+	(((x) >> BIT_SHIFT_APLL_FREF_SEL_BIT_2_TO_1) &                         \
+	 BIT_MASK_APLL_FREF_SEL_BIT_2_TO_1)
+#define BIT_SET_APLL_FREF_SEL_BIT_2_TO_1(x, v)                                 \
+	(BIT_CLEAR_APLL_FREF_SEL_BIT_2_TO_1(x) |                               \
+	 BIT_APLL_FREF_SEL_BIT_2_TO_1(v))
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+/* 2 REG_AFE_CTRL4				(Offset 0x0078) */
+
+#define BIT_RF2_EN BIT(8)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_AFE_CTRL4				(Offset 0x0078) */
+
+#define BIT_APLL_FREF_SEL_BIT3 BIT(7)
+
+#define BIT_SHIFT_APLL_LDO_V12ADJ 5
+#define BIT_MASK_APLL_LDO_V12ADJ 0x3
+#define BIT_APLL_LDO_V12ADJ(x)                                                 \
+	(((x) & BIT_MASK_APLL_LDO_V12ADJ) << BIT_SHIFT_APLL_LDO_V12ADJ)
+#define BITS_APLL_LDO_V12ADJ                                                   \
+	(BIT_MASK_APLL_LDO_V12ADJ << BIT_SHIFT_APLL_LDO_V12ADJ)
+#define BIT_CLEAR_APLL_LDO_V12ADJ(x) ((x) & (~BITS_APLL_LDO_V12ADJ))
+#define BIT_GET_APLL_LDO_V12ADJ(x)                                             \
+	(((x) >> BIT_SHIFT_APLL_LDO_V12ADJ) & BIT_MASK_APLL_LDO_V12ADJ)
+#define BIT_SET_APLL_LDO_V12ADJ(x, v)                                          \
+	(BIT_CLEAR_APLL_LDO_V12ADJ(x) | BIT_APLL_LDO_V12ADJ(v))
+
+#define BIT_APLL_160_GATEB BIT(4)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_AFE_XTAL_CTRL_EXT			(Offset 0x0078) */
+
+#define BIT_SHIFT_DIVN_5_TO_0 4
+#define BIT_MASK_DIVN_5_TO_0 0x3f
+#define BIT_DIVN_5_TO_0(x)                                                     \
+	(((x) & BIT_MASK_DIVN_5_TO_0) << BIT_SHIFT_DIVN_5_TO_0)
+#define BITS_DIVN_5_TO_0 (BIT_MASK_DIVN_5_TO_0 << BIT_SHIFT_DIVN_5_TO_0)
+#define BIT_CLEAR_DIVN_5_TO_0(x) ((x) & (~BITS_DIVN_5_TO_0))
+#define BIT_GET_DIVN_5_TO_0(x)                                                 \
+	(((x) >> BIT_SHIFT_DIVN_5_TO_0) & BIT_MASK_DIVN_5_TO_0)
+#define BIT_SET_DIVN_5_TO_0(x, v)                                              \
+	(BIT_CLEAR_DIVN_5_TO_0(x) | BIT_DIVN_5_TO_0(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_AFE_CTRL4				(Offset 0x0078) */
+
+#define BIT_AFE_DUMMY BIT(3)
+#define BIT_REG_IDOUBLE BIT(2)
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+/* 2 REG_AFE_CTRL4				(Offset 0x0078) */
+
+#define BIT_RF3_SDMRSTB BIT(2)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_AFE_CTRL4				(Offset 0x0078) */
+
+#define BIT_REG_VCO_BIAS_BIT0 BIT(1)
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+/* 2 REG_AFE_CTRL4				(Offset 0x0078) */
+
+#define BIT_RF3_RSTB BIT(1)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_AFE_CTRL4				(Offset 0x0078) */
+
+#define BIT_REG_VCO_BIAS_BIT1 BIT(0)
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+/* 2 REG_AFE_CTRL4				(Offset 0x0078) */
+
+#define BIT_RF3_EN BIT(0)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_AFE_XTAL_CTRL_EXT			(Offset 0x0078) */
+
+#define BIT_SHIFT_BB_DBG_SEL_AFE_SDM_3_TO_0 0
+#define BIT_MASK_BB_DBG_SEL_AFE_SDM_3_TO_0 0xf
+#define BIT_BB_DBG_SEL_AFE_SDM_3_TO_0(x)                                       \
+	(((x) & BIT_MASK_BB_DBG_SEL_AFE_SDM_3_TO_0)                            \
+	 << BIT_SHIFT_BB_DBG_SEL_AFE_SDM_3_TO_0)
+#define BITS_BB_DBG_SEL_AFE_SDM_3_TO_0                                         \
+	(BIT_MASK_BB_DBG_SEL_AFE_SDM_3_TO_0                                    \
+	 << BIT_SHIFT_BB_DBG_SEL_AFE_SDM_3_TO_0)
+#define BIT_CLEAR_BB_DBG_SEL_AFE_SDM_3_TO_0(x)                                 \
+	((x) & (~BITS_BB_DBG_SEL_AFE_SDM_3_TO_0))
+#define BIT_GET_BB_DBG_SEL_AFE_SDM_3_TO_0(x)                                   \
+	(((x) >> BIT_SHIFT_BB_DBG_SEL_AFE_SDM_3_TO_0) &                        \
+	 BIT_MASK_BB_DBG_SEL_AFE_SDM_3_TO_0)
+#define BIT_SET_BB_DBG_SEL_AFE_SDM_3_TO_0(x, v)                                \
+	(BIT_CLEAR_BB_DBG_SEL_AFE_SDM_3_TO_0(x) |                              \
+	 BIT_BB_DBG_SEL_AFE_SDM_3_TO_0(v))
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_LDO_SWR_CTRL			(Offset 0x007C) */
+
+#define BIT_SPS_EN_DIODE BIT(31)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_LDO_SWR_CTRL			(Offset 0x007C) */
+
+#define BIT_EXT_SWR_CTRL_EN BIT(31)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_LDO_SWR_CTRL			(Offset 0x007C) */
+
+#define BIT_REF_FREF_EDGE BIT(29)
+#define BIT_REG_VREF_SEL_V1 BIT(28)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_LDO_SWR_CTRL			(Offset 0x007C) */
+
+#define BIT_ZCD_HW_AUTO_EN BIT(27)
+#define BIT_ZCD_REGSEL BIT(26)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_LDO_SWR_CTRL			(Offset 0x007C) */
+
+#define BIT_SHIFT_REG_CP_OFFSET_4_TO_0 23
+#define BIT_MASK_REG_CP_OFFSET_4_TO_0 0x1f
+#define BIT_REG_CP_OFFSET_4_TO_0(x)                                            \
+	(((x) & BIT_MASK_REG_CP_OFFSET_4_TO_0)                                 \
+	 << BIT_SHIFT_REG_CP_OFFSET_4_TO_0)
+#define BITS_REG_CP_OFFSET_4_TO_0                                              \
+	(BIT_MASK_REG_CP_OFFSET_4_TO_0 << BIT_SHIFT_REG_CP_OFFSET_4_TO_0)
+#define BIT_CLEAR_REG_CP_OFFSET_4_TO_0(x) ((x) & (~BITS_REG_CP_OFFSET_4_TO_0))
+#define BIT_GET_REG_CP_OFFSET_4_TO_0(x)                                        \
+	(((x) >> BIT_SHIFT_REG_CP_OFFSET_4_TO_0) &                             \
+	 BIT_MASK_REG_CP_OFFSET_4_TO_0)
+#define BIT_SET_REG_CP_OFFSET_4_TO_0(x, v)                                     \
+	(BIT_CLEAR_REG_CP_OFFSET_4_TO_0(x) | BIT_REG_CP_OFFSET_4_TO_0(v))
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_LDO_SWR_CTRL			(Offset 0x007C) */
+
+#define BIT_SHIFT_AUTO_ZCD_IN_CODE 21
+#define BIT_MASK_AUTO_ZCD_IN_CODE 0x1f
+#define BIT_AUTO_ZCD_IN_CODE(x)                                                \
+	(((x) & BIT_MASK_AUTO_ZCD_IN_CODE) << BIT_SHIFT_AUTO_ZCD_IN_CODE)
+#define BITS_AUTO_ZCD_IN_CODE                                                  \
+	(BIT_MASK_AUTO_ZCD_IN_CODE << BIT_SHIFT_AUTO_ZCD_IN_CODE)
+#define BIT_CLEAR_AUTO_ZCD_IN_CODE(x) ((x) & (~BITS_AUTO_ZCD_IN_CODE))
+#define BIT_GET_AUTO_ZCD_IN_CODE(x)                                            \
+	(((x) >> BIT_SHIFT_AUTO_ZCD_IN_CODE) & BIT_MASK_AUTO_ZCD_IN_CODE)
+#define BIT_SET_AUTO_ZCD_IN_CODE(x, v)                                         \
+	(BIT_CLEAR_AUTO_ZCD_IN_CODE(x) | BIT_AUTO_ZCD_IN_CODE(v))
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_LDO_SWR_CTRL			(Offset 0x007C) */
+
+#define BIT_SHIFT_REG_RS_SET_2_TO_0 20
+#define BIT_MASK_REG_RS_SET_2_TO_0 0x7
+#define BIT_REG_RS_SET_2_TO_0(x)                                               \
+	(((x) & BIT_MASK_REG_RS_SET_2_TO_0) << BIT_SHIFT_REG_RS_SET_2_TO_0)
+#define BITS_REG_RS_SET_2_TO_0                                                 \
+	(BIT_MASK_REG_RS_SET_2_TO_0 << BIT_SHIFT_REG_RS_SET_2_TO_0)
+#define BIT_CLEAR_REG_RS_SET_2_TO_0(x) ((x) & (~BITS_REG_RS_SET_2_TO_0))
+#define BIT_GET_REG_RS_SET_2_TO_0(x)                                           \
+	(((x) >> BIT_SHIFT_REG_RS_SET_2_TO_0) & BIT_MASK_REG_RS_SET_2_TO_0)
+#define BIT_SET_REG_RS_SET_2_TO_0(x, v)                                        \
+	(BIT_CLEAR_REG_RS_SET_2_TO_0(x) | BIT_REG_RS_SET_2_TO_0(v))
+
+#define BIT_SHIFT_REG_CS_SET_1_TO_0 18
+#define BIT_MASK_REG_CS_SET_1_TO_0 0x3
+#define BIT_REG_CS_SET_1_TO_0(x)                                               \
+	(((x) & BIT_MASK_REG_CS_SET_1_TO_0) << BIT_SHIFT_REG_CS_SET_1_TO_0)
+#define BITS_REG_CS_SET_1_TO_0                                                 \
+	(BIT_MASK_REG_CS_SET_1_TO_0 << BIT_SHIFT_REG_CS_SET_1_TO_0)
+#define BIT_CLEAR_REG_CS_SET_1_TO_0(x) ((x) & (~BITS_REG_CS_SET_1_TO_0))
+#define BIT_GET_REG_CS_SET_1_TO_0(x)                                           \
+	(((x) >> BIT_SHIFT_REG_CS_SET_1_TO_0) & BIT_MASK_REG_CS_SET_1_TO_0)
+#define BIT_SET_REG_CS_SET_1_TO_0(x, v)                                        \
+	(BIT_CLEAR_REG_CS_SET_1_TO_0(x) | BIT_REG_CS_SET_1_TO_0(v))
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_LDO_SWR_CTRL			(Offset 0x007C) */
+
+#define BIT_SHIFT_ZCD_CODE_IN_L 16
+#define BIT_MASK_ZCD_CODE_IN_L 0x1f
+#define BIT_ZCD_CODE_IN_L(x)                                                   \
+	(((x) & BIT_MASK_ZCD_CODE_IN_L) << BIT_SHIFT_ZCD_CODE_IN_L)
+#define BITS_ZCD_CODE_IN_L (BIT_MASK_ZCD_CODE_IN_L << BIT_SHIFT_ZCD_CODE_IN_L)
+#define BIT_CLEAR_ZCD_CODE_IN_L(x) ((x) & (~BITS_ZCD_CODE_IN_L))
+#define BIT_GET_ZCD_CODE_IN_L(x)                                               \
+	(((x) >> BIT_SHIFT_ZCD_CODE_IN_L) & BIT_MASK_ZCD_CODE_IN_L)
+#define BIT_SET_ZCD_CODE_IN_L(x, v)                                            \
+	(BIT_CLEAR_ZCD_CODE_IN_L(x) | BIT_ZCD_CODE_IN_L(v))
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_LDO_SWR_CTRL			(Offset 0x007C) */
+
+#define BIT_SHIFT_REG_CP_SET_1_TO_0 16
+#define BIT_MASK_REG_CP_SET_1_TO_0 0x3
+#define BIT_REG_CP_SET_1_TO_0(x)                                               \
+	(((x) & BIT_MASK_REG_CP_SET_1_TO_0) << BIT_SHIFT_REG_CP_SET_1_TO_0)
+#define BITS_REG_CP_SET_1_TO_0                                                 \
+	(BIT_MASK_REG_CP_SET_1_TO_0 << BIT_SHIFT_REG_CP_SET_1_TO_0)
+#define BIT_CLEAR_REG_CP_SET_1_TO_0(x) ((x) & (~BITS_REG_CP_SET_1_TO_0))
+#define BIT_GET_REG_CP_SET_1_TO_0(x)                                           \
+	(((x) >> BIT_SHIFT_REG_CP_SET_1_TO_0) & BIT_MASK_REG_CP_SET_1_TO_0)
+#define BIT_SET_REG_CP_SET_1_TO_0(x, v)                                        \
+	(BIT_CLEAR_REG_CP_SET_1_TO_0(x) | BIT_REG_CP_SET_1_TO_0(v))
+
+#define BIT_LPFEN BIT(15)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT)
+
+/* 2 REG_LDO_SWR_CTRL			(Offset 0x007C) */
+
+#define BIT_SHIFT_LDO_HV5_DUMMY 14
+#define BIT_MASK_LDO_HV5_DUMMY 0x3
+#define BIT_LDO_HV5_DUMMY(x)                                                   \
+	(((x) & BIT_MASK_LDO_HV5_DUMMY) << BIT_SHIFT_LDO_HV5_DUMMY)
+#define BITS_LDO_HV5_DUMMY (BIT_MASK_LDO_HV5_DUMMY << BIT_SHIFT_LDO_HV5_DUMMY)
+#define BIT_CLEAR_LDO_HV5_DUMMY(x) ((x) & (~BITS_LDO_HV5_DUMMY))
+#define BIT_GET_LDO_HV5_DUMMY(x)                                               \
+	(((x) >> BIT_SHIFT_LDO_HV5_DUMMY) & BIT_MASK_LDO_HV5_DUMMY)
+#define BIT_SET_LDO_HV5_DUMMY(x, v)                                            \
+	(BIT_CLEAR_LDO_HV5_DUMMY(x) | BIT_LDO_HV5_DUMMY(v))
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_LDO_SWR_CTRL			(Offset 0x007C) */
+
+#define BIT_REG_DOGENB BIT(14)
+#define BIT_REG_TEST_EN BIT(13)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT)
+
+/* 2 REG_LDO_SWR_CTRL			(Offset 0x007C) */
+
+#define BIT_SHIFT_REG_VTUNE33 12
+#define BIT_MASK_REG_VTUNE33 0x3
+#define BIT_REG_VTUNE33(x)                                                     \
+	(((x) & BIT_MASK_REG_VTUNE33) << BIT_SHIFT_REG_VTUNE33)
+#define BITS_REG_VTUNE33 (BIT_MASK_REG_VTUNE33 << BIT_SHIFT_REG_VTUNE33)
+#define BIT_CLEAR_REG_VTUNE33(x) ((x) & (~BITS_REG_VTUNE33))
+#define BIT_GET_REG_VTUNE33(x)                                                 \
+	(((x) >> BIT_SHIFT_REG_VTUNE33) & BIT_MASK_REG_VTUNE33)
+#define BIT_SET_REG_VTUNE33(x, v)                                              \
+	(BIT_CLEAR_REG_VTUNE33(x) | BIT_REG_VTUNE33(v))
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+
+/* 2 REG_LDO_SWR_CTRL			(Offset 0x007C) */
+
+#define BIT_SHIFT_REG_VTUNE33_BIT0_TO_BIT1 12
+#define BIT_MASK_REG_VTUNE33_BIT0_TO_BIT1 0x3
+#define BIT_REG_VTUNE33_BIT0_TO_BIT1(x)                                        \
+	(((x) & BIT_MASK_REG_VTUNE33_BIT0_TO_BIT1)                             \
+	 << BIT_SHIFT_REG_VTUNE33_BIT0_TO_BIT1)
+#define BITS_REG_VTUNE33_BIT0_TO_BIT1                                          \
+	(BIT_MASK_REG_VTUNE33_BIT0_TO_BIT1                                     \
+	 << BIT_SHIFT_REG_VTUNE33_BIT0_TO_BIT1)
+#define BIT_CLEAR_REG_VTUNE33_BIT0_TO_BIT1(x)                                  \
+	((x) & (~BITS_REG_VTUNE33_BIT0_TO_BIT1))
+#define BIT_GET_REG_VTUNE33_BIT0_TO_BIT1(x)                                    \
+	(((x) >> BIT_SHIFT_REG_VTUNE33_BIT0_TO_BIT1) &                         \
+	 BIT_MASK_REG_VTUNE33_BIT0_TO_BIT1)
+#define BIT_SET_REG_VTUNE33_BIT0_TO_BIT1(x, v)                                 \
+	(BIT_CLEAR_REG_VTUNE33_BIT0_TO_BIT1(x) |                               \
+	 BIT_REG_VTUNE33_BIT0_TO_BIT1(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT)
+
+/* 2 REG_LDO_SWR_CTRL			(Offset 0x007C) */
+
+#define BIT_SHIFT_REG_STANDBY33 10
+#define BIT_MASK_REG_STANDBY33 0x3
+#define BIT_REG_STANDBY33(x)                                                   \
+	(((x) & BIT_MASK_REG_STANDBY33) << BIT_SHIFT_REG_STANDBY33)
+#define BITS_REG_STANDBY33 (BIT_MASK_REG_STANDBY33 << BIT_SHIFT_REG_STANDBY33)
+#define BIT_CLEAR_REG_STANDBY33(x) ((x) & (~BITS_REG_STANDBY33))
+#define BIT_GET_REG_STANDBY33(x)                                               \
+	(((x) >> BIT_SHIFT_REG_STANDBY33) & BIT_MASK_REG_STANDBY33)
+#define BIT_SET_REG_STANDBY33(x, v)                                            \
+	(BIT_CLEAR_REG_STANDBY33(x) | BIT_REG_STANDBY33(v))
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+
+/* 2 REG_LDO_SWR_CTRL			(Offset 0x007C) */
+
+#define BIT_SHIFT_REG_STANDBY33_BIT0_TO_BIT1 10
+#define BIT_MASK_REG_STANDBY33_BIT0_TO_BIT1 0x3
+#define BIT_REG_STANDBY33_BIT0_TO_BIT1(x)                                      \
+	(((x) & BIT_MASK_REG_STANDBY33_BIT0_TO_BIT1)                           \
+	 << BIT_SHIFT_REG_STANDBY33_BIT0_TO_BIT1)
+#define BITS_REG_STANDBY33_BIT0_TO_BIT1                                        \
+	(BIT_MASK_REG_STANDBY33_BIT0_TO_BIT1                                   \
+	 << BIT_SHIFT_REG_STANDBY33_BIT0_TO_BIT1)
+#define BIT_CLEAR_REG_STANDBY33_BIT0_TO_BIT1(x)                                \
+	((x) & (~BITS_REG_STANDBY33_BIT0_TO_BIT1))
+#define BIT_GET_REG_STANDBY33_BIT0_TO_BIT1(x)                                  \
+	(((x) >> BIT_SHIFT_REG_STANDBY33_BIT0_TO_BIT1) &                       \
+	 BIT_MASK_REG_STANDBY33_BIT0_TO_BIT1)
+#define BIT_SET_REG_STANDBY33_BIT0_TO_BIT1(x, v)                               \
+	(BIT_CLEAR_REG_STANDBY33_BIT0_TO_BIT1(x) |                             \
+	 BIT_REG_STANDBY33_BIT0_TO_BIT1(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT)
+
+/* 2 REG_LDO_SWR_CTRL			(Offset 0x007C) */
+
+#define BIT_SHIFT_REG_LOAD33 8
+#define BIT_MASK_REG_LOAD33 0x3
+#define BIT_REG_LOAD33(x) (((x) & BIT_MASK_REG_LOAD33) << BIT_SHIFT_REG_LOAD33)
+#define BITS_REG_LOAD33 (BIT_MASK_REG_LOAD33 << BIT_SHIFT_REG_LOAD33)
+#define BIT_CLEAR_REG_LOAD33(x) ((x) & (~BITS_REG_LOAD33))
+#define BIT_GET_REG_LOAD33(x)                                                  \
+	(((x) >> BIT_SHIFT_REG_LOAD33) & BIT_MASK_REG_LOAD33)
+#define BIT_SET_REG_LOAD33(x, v) (BIT_CLEAR_REG_LOAD33(x) | BIT_REG_LOAD33(v))
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+
+/* 2 REG_LDO_SWR_CTRL			(Offset 0x007C) */
+
+#define BIT_SHIFT_REG_LOAD33_BIT0_TO_BIT1 8
+#define BIT_MASK_REG_LOAD33_BIT0_TO_BIT1 0x3
+#define BIT_REG_LOAD33_BIT0_TO_BIT1(x)                                         \
+	(((x) & BIT_MASK_REG_LOAD33_BIT0_TO_BIT1)                              \
+	 << BIT_SHIFT_REG_LOAD33_BIT0_TO_BIT1)
+#define BITS_REG_LOAD33_BIT0_TO_BIT1                                           \
+	(BIT_MASK_REG_LOAD33_BIT0_TO_BIT1 << BIT_SHIFT_REG_LOAD33_BIT0_TO_BIT1)
+#define BIT_CLEAR_REG_LOAD33_BIT0_TO_BIT1(x)                                   \
+	((x) & (~BITS_REG_LOAD33_BIT0_TO_BIT1))
+#define BIT_GET_REG_LOAD33_BIT0_TO_BIT1(x)                                     \
+	(((x) >> BIT_SHIFT_REG_LOAD33_BIT0_TO_BIT1) &                          \
+	 BIT_MASK_REG_LOAD33_BIT0_TO_BIT1)
+#define BIT_SET_REG_LOAD33_BIT0_TO_BIT1(x, v)                                  \
+	(BIT_CLEAR_REG_LOAD33_BIT0_TO_BIT1(x) | BIT_REG_LOAD33_BIT0_TO_BIT1(v))
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_LDO_SWR_CTRL			(Offset 0x007C) */
+
+#define BIT_SHIFT_REG_DIV_SEL 8
+#define BIT_MASK_REG_DIV_SEL 0x1f
+#define BIT_REG_DIV_SEL(x)                                                     \
+	(((x) & BIT_MASK_REG_DIV_SEL) << BIT_SHIFT_REG_DIV_SEL)
+#define BITS_REG_DIV_SEL (BIT_MASK_REG_DIV_SEL << BIT_SHIFT_REG_DIV_SEL)
+#define BIT_CLEAR_REG_DIV_SEL(x) ((x) & (~BITS_REG_DIV_SEL))
+#define BIT_GET_REG_DIV_SEL(x)                                                 \
+	(((x) >> BIT_SHIFT_REG_DIV_SEL) & BIT_MASK_REG_DIV_SEL)
+#define BIT_SET_REG_DIV_SEL(x, v)                                              \
+	(BIT_CLEAR_REG_DIV_SEL(x) | BIT_REG_DIV_SEL(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_LDO_SWR_CTRL			(Offset 0x007C) */
+
+#define BIT_REG_BYPASS_L BIT(7)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_LDO_SWR_CTRL			(Offset 0x007C) */
+
+#define BIT_EN_CK200M BIT(7)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_LDO_SWR_CTRL			(Offset 0x007C) */
+
+#define BIT_REG_LDOF_L BIT(6)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8881A_SUPPORT)
+
+/* 2 REG_LDO_SWR_CTRL			(Offset 0x007C) */
+
+#define BIT_REG_OCPS_L BIT(5)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_LDO_SWR_CTRL			(Offset 0x007C) */
+
+#define BIT_SHIFT_REG_KVCO_200M_1_TO_0 5
+#define BIT_MASK_REG_KVCO_200M_1_TO_0 0x3
+#define BIT_REG_KVCO_200M_1_TO_0(x)                                            \
+	(((x) & BIT_MASK_REG_KVCO_200M_1_TO_0)                                 \
+	 << BIT_SHIFT_REG_KVCO_200M_1_TO_0)
+#define BITS_REG_KVCO_200M_1_TO_0                                              \
+	(BIT_MASK_REG_KVCO_200M_1_TO_0 << BIT_SHIFT_REG_KVCO_200M_1_TO_0)
+#define BIT_CLEAR_REG_KVCO_200M_1_TO_0(x) ((x) & (~BITS_REG_KVCO_200M_1_TO_0))
+#define BIT_GET_REG_KVCO_200M_1_TO_0(x)                                        \
+	(((x) >> BIT_SHIFT_REG_KVCO_200M_1_TO_0) &                             \
+	 BIT_MASK_REG_KVCO_200M_1_TO_0)
+#define BIT_SET_REG_KVCO_200M_1_TO_0(x, v)                                     \
+	(BIT_CLEAR_REG_KVCO_200M_1_TO_0(x) | BIT_REG_KVCO_200M_1_TO_0(v))
+
+#endif
+
+#if (HALMAC_8822B_SUPPORT)
+
+/* 2 REG_LDO_SWR_CTRL			(Offset 0x007C) */
+
+#define BIT_REG_TYPE_L_V1 BIT(5)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+
+/* 2 REG_LDO_SWR_CTRL			(Offset 0x007C) */
+
+#define BIT_ARENB_L BIT(3)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_LDO_SWR_CTRL			(Offset 0x007C) */
+
+#define BIT_SHIFT_REG_CP_BIAS_200M_2_TO_0 2
+#define BIT_MASK_REG_CP_BIAS_200M_2_TO_0 0x7
+#define BIT_REG_CP_BIAS_200M_2_TO_0(x)                                         \
+	(((x) & BIT_MASK_REG_CP_BIAS_200M_2_TO_0)                              \
+	 << BIT_SHIFT_REG_CP_BIAS_200M_2_TO_0)
+#define BITS_REG_CP_BIAS_200M_2_TO_0                                           \
+	(BIT_MASK_REG_CP_BIAS_200M_2_TO_0 << BIT_SHIFT_REG_CP_BIAS_200M_2_TO_0)
+#define BIT_CLEAR_REG_CP_BIAS_200M_2_TO_0(x)                                   \
+	((x) & (~BITS_REG_CP_BIAS_200M_2_TO_0))
+#define BIT_GET_REG_CP_BIAS_200M_2_TO_0(x)                                     \
+	(((x) >> BIT_SHIFT_REG_CP_BIAS_200M_2_TO_0) &                          \
+	 BIT_MASK_REG_CP_BIAS_200M_2_TO_0)
+#define BIT_SET_REG_CP_BIAS_200M_2_TO_0(x, v)                                  \
+	(BIT_CLEAR_REG_CP_BIAS_200M_2_TO_0(x) | BIT_REG_CP_BIAS_200M_2_TO_0(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_LDO_SWR_CTRL			(Offset 0x007C) */
+
+#define BIT_SHIFT_CFC_L_BIT_1_TO_0 1
+#define BIT_MASK_CFC_L_BIT_1_TO_0 0x3
+#define BIT_CFC_L_BIT_1_TO_0(x)                                                \
+	(((x) & BIT_MASK_CFC_L_BIT_1_TO_0) << BIT_SHIFT_CFC_L_BIT_1_TO_0)
+#define BITS_CFC_L_BIT_1_TO_0                                                  \
+	(BIT_MASK_CFC_L_BIT_1_TO_0 << BIT_SHIFT_CFC_L_BIT_1_TO_0)
+#define BIT_CLEAR_CFC_L_BIT_1_TO_0(x) ((x) & (~BITS_CFC_L_BIT_1_TO_0))
+#define BIT_GET_CFC_L_BIT_1_TO_0(x)                                            \
+	(((x) >> BIT_SHIFT_CFC_L_BIT_1_TO_0) & BIT_MASK_CFC_L_BIT_1_TO_0)
+#define BIT_SET_CFC_L_BIT_1_TO_0(x, v)                                         \
+	(BIT_CLEAR_CFC_L_BIT_1_TO_0(x) | BIT_CFC_L_BIT_1_TO_0(v))
+
+#endif
+
+#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+
+/* 2 REG_LDO_SWR_CTRL			(Offset 0x007C) */
+
+#define BIT_SHIFT_CFC_L 1
+#define BIT_MASK_CFC_L 0x3
+#define BIT_CFC_L(x) (((x) & BIT_MASK_CFC_L) << BIT_SHIFT_CFC_L)
+#define BITS_CFC_L (BIT_MASK_CFC_L << BIT_SHIFT_CFC_L)
+#define BIT_CLEAR_CFC_L(x) ((x) & (~BITS_CFC_L))
+#define BIT_GET_CFC_L(x) (((x) >> BIT_SHIFT_CFC_L) & BIT_MASK_CFC_L)
+#define BIT_SET_CFC_L(x, v) (BIT_CLEAR_CFC_L(x) | BIT_CFC_L(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8881A_SUPPORT)
+
+/* 2 REG_LDO_SWR_CTRL			(Offset 0x007C) */
+
+#define BIT_REG_TYPE_L BIT(0)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_LDO_SWR_CTRL			(Offset 0x007C) */
+
+#define BIT_XCK_OUT_EN BIT(0)
+
+#endif
+
+#if (HALMAC_8822B_SUPPORT)
+
+/* 2 REG_LDO_SWR_CTRL			(Offset 0x007C) */
+
+#define BIT_REG_OCPS_L_V1 BIT(0)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_MCUFW_CTRL				(Offset 0x0080) */
+
+#define BIT_MCUSUS_EN BIT(23)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_MCUFW_CTRL				(Offset 0x0080) */
+
+#define BIT_ANA_PORT_EN BIT(22)
+#define BIT_MAC_PORT_EN BIT(21)
+#define BIT_BOOT_FSPI_EN BIT(20)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_MCUFW_CTRL				(Offset 0x0080) */
+
+#define BIT_SHIFT_MCUROM_DL 16
+#define BIT_MASK_MCUROM_DL 0xf
+#define BIT_MCUROM_DL(x) (((x) & BIT_MASK_MCUROM_DL) << BIT_SHIFT_MCUROM_DL)
+#define BITS_MCUROM_DL (BIT_MASK_MCUROM_DL << BIT_SHIFT_MCUROM_DL)
+#define BIT_CLEAR_MCUROM_DL(x) ((x) & (~BITS_MCUROM_DL))
+#define BIT_GET_MCUROM_DL(x) (((x) >> BIT_SHIFT_MCUROM_DL) & BIT_MASK_MCUROM_DL)
+#define BIT_SET_MCUROM_DL(x, v) (BIT_CLEAR_MCUROM_DL(x) | BIT_MCUROM_DL(v))
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_MCUFW_CTRL				(Offset 0x0080) */
+
+#define BIT_WMAC_SRCH_FIFOFULL BIT(15)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_MCUFW_CTRL				(Offset 0x0080) */
+
+#define BIT_FW_INIT_RDY BIT(15)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_MCUFW_CTRL				(Offset 0x0080) */
+
+#define BIT_SHIFT_MCUFWDL_DMA_2KB_SEL 14
+#define BIT_MASK_MCUFWDL_DMA_2KB_SEL 0x3
+#define BIT_MCUFWDL_DMA_2KB_SEL(x)                                             \
+	(((x) & BIT_MASK_MCUFWDL_DMA_2KB_SEL) << BIT_SHIFT_MCUFWDL_DMA_2KB_SEL)
+#define BITS_MCUFWDL_DMA_2KB_SEL                                               \
+	(BIT_MASK_MCUFWDL_DMA_2KB_SEL << BIT_SHIFT_MCUFWDL_DMA_2KB_SEL)
+#define BIT_CLEAR_MCUFWDL_DMA_2KB_SEL(x) ((x) & (~BITS_MCUFWDL_DMA_2KB_SEL))
+#define BIT_GET_MCUFWDL_DMA_2KB_SEL(x)                                         \
+	(((x) >> BIT_SHIFT_MCUFWDL_DMA_2KB_SEL) & BIT_MASK_MCUFWDL_DMA_2KB_SEL)
+#define BIT_SET_MCUFWDL_DMA_2KB_SEL(x, v)                                      \
+	(BIT_CLEAR_MCUFWDL_DMA_2KB_SEL(x) | BIT_MCUFWDL_DMA_2KB_SEL(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_MCUFW_CTRL				(Offset 0x0080) */
+
+#define BIT_FW_DW_RDY BIT(14)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_8051FW_CTRL				(Offset 0x0080) */
+
+#define BIT_FWDL_RSVDPAGE_RDY BIT(12)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_MCUFW_CTRL				(Offset 0x0080) */
+
+#define BIT_SHIFT_CPU_CLK_SEL 12
+#define BIT_MASK_CPU_CLK_SEL 0x3
+#define BIT_CPU_CLK_SEL(x)                                                     \
+	(((x) & BIT_MASK_CPU_CLK_SEL) << BIT_SHIFT_CPU_CLK_SEL)
+#define BITS_CPU_CLK_SEL (BIT_MASK_CPU_CLK_SEL << BIT_SHIFT_CPU_CLK_SEL)
+#define BIT_CLEAR_CPU_CLK_SEL(x) ((x) & (~BITS_CPU_CLK_SEL))
+#define BIT_GET_CPU_CLK_SEL(x)                                                 \
+	(((x) >> BIT_SHIFT_CPU_CLK_SEL) & BIT_MASK_CPU_CLK_SEL)
+#define BIT_SET_CPU_CLK_SEL(x, v)                                              \
+	(BIT_CLEAR_CPU_CLK_SEL(x) | BIT_CPU_CLK_SEL(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_8051FW_CTRL				(Offset 0x0080) */
+
+#define BIT_R_8051_ROMDLFW_EN BIT(11)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_MCUFW_CTRL				(Offset 0x0080) */
+
+#define BIT_MCUFWDL_DMA_EN BIT(11)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_MCUFW_CTRL				(Offset 0x0080) */
+
+#define BIT_CCLK_CHG_MASK BIT(11)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_8051FW_CTRL				(Offset 0x0080) */
+
+#define BIT_R_8051_INIT_RDY BIT(10)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_MCUFW_CTRL				(Offset 0x0080) */
+
+#define BIT_MCUINI_WROMRDY BIT(10)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_MCUFW_CTRL				(Offset 0x0080) */
+
+#define BIT_FW_INIT_RDY_V1 BIT(10)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_MCUFW_CTRL				(Offset 0x0080) */
+
+#define BIT_EMEM__TXBUF_CHKSUM_OK BIT(10)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_MCUFW_CTRL				(Offset 0x0080) */
+
+#define BIT_EMEM_TXBUF_CHKSUM_OK BIT(10)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_MCUFW_CTRL				(Offset 0x0080) */
+
+#define BIT_MCUTXA_SPD BIT(9)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_MCUFW_CTRL				(Offset 0x0080) */
+
+#define BIT_EMEM_TXBUF_DW_RDY BIT(9)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_8051FW_CTRL				(Offset 0x0080) */
+
+#define BIT_R_8051_GAT BIT(8)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_MCUFW_CTRL				(Offset 0x0080) */
+
+#define BIT_MCUCLK_TEN BIT(8)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_MCUFW_CTRL				(Offset 0x0080) */
+
+#define BIT_MCU_CLK_EN BIT(8)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_MCUFW_CTRL				(Offset 0x0080) */
+
+#define BIT_EMEM_CHKSUM_OK BIT(8)
+#define BIT_EMEM_DW_OK BIT(7)
+#define BIT_TOGGLE BIT(7)
+#define BIT_DMEM_CHKSUM_OK BIT(6)
+#define BIT_ACK BIT(6)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_8051FW_CTRL				(Offset 0x0080) */
+
+#define BIT_RFINI_RDY BIT(5)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_MCUFW_CTRL				(Offset 0x0080) */
+
+#define BIT_MCUINI_WRFCRDY BIT(5)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_MCUFW_CTRL				(Offset 0x0080) */
+
+#define BIT_RF_INIT_RDY BIT(5)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_MCUFW_CTRL				(Offset 0x0080) */
+
+#define BIT_DMEM_DW_OK BIT(5)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_8051FW_CTRL				(Offset 0x0080) */
+
+#define BIT_BBINI_RDY BIT(4)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_MCUFW_CTRL				(Offset 0x0080) */
+
+#define BIT_MCUINI_WPHYRDY BIT(4)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_MCUFW_CTRL				(Offset 0x0080) */
+
+#define BIT_BB_INIT_RDY BIT(4)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_MCUFW_CTRL				(Offset 0x0080) */
+
+#define BIT_IMEM_CHKSUM_OK BIT(4)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_8051FW_CTRL				(Offset 0x0080) */
+
+#define BIT_MACINI_RDY BIT(3)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_MCUFW_CTRL				(Offset 0x0080) */
+
+#define BIT_MCUINI_WMACRDY BIT(3)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_MCUFW_CTRL				(Offset 0x0080) */
+
+#define BIT_MAC_INIT_RDY BIT(3)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_MCUFW_CTRL				(Offset 0x0080) */
+
+#define BIT_IMEM_DW_OK BIT(3)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_8051FW_CTRL				(Offset 0x0080) */
+
+#define BIT_FWDL_CHK_RPT BIT(2)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_MCUFW_CTRL				(Offset 0x0080) */
+
+#define BIT_IMEM_BOOT_LOAD_CHKSUM_OK BIT(2)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_8051FW_CTRL				(Offset 0x0080) */
+
+#define BIT_MCUFWDL_RDY BIT(1)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_MCUFW_CTRL				(Offset 0x0080) */
+
+#define BIT_IMEM_BOOT_LOAD_DW_OK BIT(1)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_MCUFW_CTRL				(Offset 0x0080) */
+
+#define BIT_MCU_FWDL_RDY BIT(1)
+#define BIT_MCU_FWDL_EN BIT(0)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_SDIO_HRPWM1				(Offset 0x10250080) */
+
+#define BIT_REQ_PS BIT(0)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_MCU_TST_CFG				(Offset 0x0084) */
+
+#define BIT_SHIFT_8051CODE_OFS 16
+#define BIT_MASK_8051CODE_OFS 0xffff
+#define BIT_8051CODE_OFS(x)                                                    \
+	(((x) & BIT_MASK_8051CODE_OFS) << BIT_SHIFT_8051CODE_OFS)
+#define BITS_8051CODE_OFS (BIT_MASK_8051CODE_OFS << BIT_SHIFT_8051CODE_OFS)
+#define BIT_CLEAR_8051CODE_OFS(x) ((x) & (~BITS_8051CODE_OFS))
+#define BIT_GET_8051CODE_OFS(x)                                                \
+	(((x) >> BIT_SHIFT_8051CODE_OFS) & BIT_MASK_8051CODE_OFS)
+#define BIT_SET_8051CODE_OFS(x, v)                                             \
+	(BIT_CLEAR_8051CODE_OFS(x) | BIT_8051CODE_OFS(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_MCU_TST_CFG				(Offset 0x0084) */
+
+#define BIT_SHIFT_LBKTST 0
+#define BIT_MASK_LBKTST 0xffff
+#define BIT_LBKTST(x) (((x) & BIT_MASK_LBKTST) << BIT_SHIFT_LBKTST)
+#define BITS_LBKTST (BIT_MASK_LBKTST << BIT_SHIFT_LBKTST)
+#define BIT_CLEAR_LBKTST(x) ((x) & (~BITS_LBKTST))
+#define BIT_GET_LBKTST(x) (((x) >> BIT_SHIFT_LBKTST) & BIT_MASK_LBKTST)
+#define BIT_SET_LBKTST(x, v) (BIT_CLEAR_LBKTST(x) | BIT_LBKTST(v))
+
+#endif
+
+#if (HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT)
+
+/* 2 REG_MCU_TST_CFG				(Offset 0x0084) */
+
+#define BIT_SHIFT_C2H_MSG 0
+#define BIT_MASK_C2H_MSG 0xffff
+#define BIT_C2H_MSG(x) (((x) & BIT_MASK_C2H_MSG) << BIT_SHIFT_C2H_MSG)
+#define BITS_C2H_MSG (BIT_MASK_C2H_MSG << BIT_SHIFT_C2H_MSG)
+#define BIT_CLEAR_C2H_MSG(x) ((x) & (~BITS_C2H_MSG))
+#define BIT_GET_C2H_MSG(x) (((x) >> BIT_SHIFT_C2H_MSG) & BIT_MASK_C2H_MSG)
+#define BIT_SET_C2H_MSG(x, v) (BIT_CLEAR_C2H_MSG(x) | BIT_C2H_MSG(v))
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_SDIO_BUS_CTRL			(Offset 0x10250085) */
+
+#define BIT_INT_MASK_DIS BIT(4)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_SDIO_BUS_CTRL			(Offset 0x10250085) */
+
+#define BIT_PAD_CLK_XHGE_EN BIT(3)
+#define BIT_INTER_CLK_EN BIT(2)
+#define BIT_EN_RPT_TXCRC BIT(1)
+#define BIT_DIS_RXDMA_STS BIT(0)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT)
+
+/* 2 REG_SDIO_HSUS_CTRL			(Offset 0x10250086) */
+
+#define BIT_SPI_PHASE BIT(5)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_SDIO_HSUS_CTRL			(Offset 0x10250086) */
+
+#define BIT_INTR_CTRL BIT(4)
+#define BIT_SDIO_VOLTAGE BIT(3)
+#define BIT_BYPASS_INIT BIT(2)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_SDIO_HSUS_CTRL			(Offset 0x10250086) */
+
+#define BIT_HCI_RESUME_RDY BIT(1)
+#define BIT_HCI_SUS_REQ BIT(0)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_HMEBOX_E0_E1			(Offset 0x0088) */
+
+#define BIT_SHIFT_HOST_MSG_E1 16
+#define BIT_MASK_HOST_MSG_E1 0xffff
+#define BIT_HOST_MSG_E1(x)                                                     \
+	(((x) & BIT_MASK_HOST_MSG_E1) << BIT_SHIFT_HOST_MSG_E1)
+#define BITS_HOST_MSG_E1 (BIT_MASK_HOST_MSG_E1 << BIT_SHIFT_HOST_MSG_E1)
+#define BIT_CLEAR_HOST_MSG_E1(x) ((x) & (~BITS_HOST_MSG_E1))
+#define BIT_GET_HOST_MSG_E1(x)                                                 \
+	(((x) >> BIT_SHIFT_HOST_MSG_E1) & BIT_MASK_HOST_MSG_E1)
+#define BIT_SET_HOST_MSG_E1(x, v)                                              \
+	(BIT_CLEAR_HOST_MSG_E1(x) | BIT_HOST_MSG_E1(v))
+
+#define BIT_SHIFT_HOST_MSG_E0 0
+#define BIT_MASK_HOST_MSG_E0 0xffff
+#define BIT_HOST_MSG_E0(x)                                                     \
+	(((x) & BIT_MASK_HOST_MSG_E0) << BIT_SHIFT_HOST_MSG_E0)
+#define BITS_HOST_MSG_E0 (BIT_MASK_HOST_MSG_E0 << BIT_SHIFT_HOST_MSG_E0)
+#define BIT_CLEAR_HOST_MSG_E0(x) ((x) & (~BITS_HOST_MSG_E0))
+#define BIT_GET_HOST_MSG_E0(x)                                                 \
+	(((x) >> BIT_SHIFT_HOST_MSG_E0) & BIT_MASK_HOST_MSG_E0)
+#define BIT_SET_HOST_MSG_E0(x, v)                                              \
+	(BIT_CLEAR_HOST_MSG_E0(x) | BIT_HOST_MSG_E0(v))
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_SDIO_RESPONSE_TIMER			(Offset 0x10250088) */
+
+#define BIT_SHIFT_CMDIN_2RESP_TIMER 0
+#define BIT_MASK_CMDIN_2RESP_TIMER 0xffff
+#define BIT_CMDIN_2RESP_TIMER(x)                                               \
+	(((x) & BIT_MASK_CMDIN_2RESP_TIMER) << BIT_SHIFT_CMDIN_2RESP_TIMER)
+#define BITS_CMDIN_2RESP_TIMER                                                 \
+	(BIT_MASK_CMDIN_2RESP_TIMER << BIT_SHIFT_CMDIN_2RESP_TIMER)
+#define BIT_CLEAR_CMDIN_2RESP_TIMER(x) ((x) & (~BITS_CMDIN_2RESP_TIMER))
+#define BIT_GET_CMDIN_2RESP_TIMER(x)                                           \
+	(((x) >> BIT_SHIFT_CMDIN_2RESP_TIMER) & BIT_MASK_CMDIN_2RESP_TIMER)
+#define BIT_SET_CMDIN_2RESP_TIMER(x, v)                                        \
+	(BIT_CLEAR_CMDIN_2RESP_TIMER(x) | BIT_CMDIN_2RESP_TIMER(v))
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_SDIO_CMD_CRC			(Offset 0x1025008A) */
+
+#define BIT_SHIFT_SDIO_CMD_CRC 1
+#define BIT_MASK_SDIO_CMD_CRC 0x7f
+#define BIT_SDIO_CMD_CRC(x)                                                    \
+	(((x) & BIT_MASK_SDIO_CMD_CRC) << BIT_SHIFT_SDIO_CMD_CRC)
+#define BITS_SDIO_CMD_CRC (BIT_MASK_SDIO_CMD_CRC << BIT_SHIFT_SDIO_CMD_CRC)
+#define BIT_CLEAR_SDIO_CMD_CRC(x) ((x) & (~BITS_SDIO_CMD_CRC))
+#define BIT_GET_SDIO_CMD_CRC(x)                                                \
+	(((x) >> BIT_SHIFT_SDIO_CMD_CRC) & BIT_MASK_SDIO_CMD_CRC)
+#define BIT_SET_SDIO_CMD_CRC(x, v)                                             \
+	(BIT_CLEAR_SDIO_CMD_CRC(x) | BIT_SDIO_CMD_CRC(v))
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_SDIO_CMD_CRC			(Offset 0x1025008A) */
+
+#define BIT_SHIFT_SDIO_CMD_CRC_V1 0
+#define BIT_MASK_SDIO_CMD_CRC_V1 0xff
+#define BIT_SDIO_CMD_CRC_V1(x)                                                 \
+	(((x) & BIT_MASK_SDIO_CMD_CRC_V1) << BIT_SHIFT_SDIO_CMD_CRC_V1)
+#define BITS_SDIO_CMD_CRC_V1                                                   \
+	(BIT_MASK_SDIO_CMD_CRC_V1 << BIT_SHIFT_SDIO_CMD_CRC_V1)
+#define BIT_CLEAR_SDIO_CMD_CRC_V1(x) ((x) & (~BITS_SDIO_CMD_CRC_V1))
+#define BIT_GET_SDIO_CMD_CRC_V1(x)                                             \
+	(((x) >> BIT_SHIFT_SDIO_CMD_CRC_V1) & BIT_MASK_SDIO_CMD_CRC_V1)
+#define BIT_SET_SDIO_CMD_CRC_V1(x, v)                                          \
+	(BIT_CLEAR_SDIO_CMD_CRC_V1(x) | BIT_SDIO_CMD_CRC_V1(v))
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_SDIO_CMD_CRC			(Offset 0x1025008A) */
+
+#define BIT_SDIO_CMD_E_BIT BIT(0)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_HMEBOX_E2_E3			(Offset 0x008C) */
+
+#define BIT_SHIFT_HOST_MSG_E3 16
+#define BIT_MASK_HOST_MSG_E3 0xffff
+#define BIT_HOST_MSG_E3(x)                                                     \
+	(((x) & BIT_MASK_HOST_MSG_E3) << BIT_SHIFT_HOST_MSG_E3)
+#define BITS_HOST_MSG_E3 (BIT_MASK_HOST_MSG_E3 << BIT_SHIFT_HOST_MSG_E3)
+#define BIT_CLEAR_HOST_MSG_E3(x) ((x) & (~BITS_HOST_MSG_E3))
+#define BIT_GET_HOST_MSG_E3(x)                                                 \
+	(((x) >> BIT_SHIFT_HOST_MSG_E3) & BIT_MASK_HOST_MSG_E3)
+#define BIT_SET_HOST_MSG_E3(x, v)                                              \
+	(BIT_CLEAR_HOST_MSG_E3(x) | BIT_HOST_MSG_E3(v))
+
+#define BIT_SHIFT_HOST_MSG_E2 0
+#define BIT_MASK_HOST_MSG_E2 0xffff
+#define BIT_HOST_MSG_E2(x)                                                     \
+	(((x) & BIT_MASK_HOST_MSG_E2) << BIT_SHIFT_HOST_MSG_E2)
+#define BITS_HOST_MSG_E2 (BIT_MASK_HOST_MSG_E2 << BIT_SHIFT_HOST_MSG_E2)
+#define BIT_CLEAR_HOST_MSG_E2(x) ((x) & (~BITS_HOST_MSG_E2))
+#define BIT_GET_HOST_MSG_E2(x)                                                 \
+	(((x) >> BIT_SHIFT_HOST_MSG_E2) & BIT_MASK_HOST_MSG_E2)
+#define BIT_SET_HOST_MSG_E2(x, v)                                              \
+	(BIT_CLEAR_HOST_MSG_E2(x) | BIT_HOST_MSG_E2(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_WLLPS_CTRL				(Offset 0x0090) */
+
+#define BIT_WLLPSOP_EABM BIT(31)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8881A_SUPPORT)
+
+/* 2 REG_WLLPS_CTRL				(Offset 0x0090) */
+
+#define BIT_WLLPSOP_ACKF BIT(30)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_WLLPS_CTRL				(Offset 0x0090) */
+
+#define BIT_TXFIFO_TH_INT BIT(30)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8881A_SUPPORT)
+
+/* 2 REG_WLLPS_CTRL				(Offset 0x0090) */
+
+#define BIT_WLLPSOP_DLDM BIT(29)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_WLLPS_CTRL				(Offset 0x0090) */
+
+#define BIT_WLLPSOP_NODS BIT(29)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_WLLPS_CTRL				(Offset 0x0090) */
+
+#define BIT_WLLPSOP_AFEP BIT(29)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_WLLPS_CTRL				(Offset 0x0090) */
+
+#define BIT_WLLPSOP_ESWR BIT(28)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_WLLPS_CTRL				(Offset 0x0090) */
+
+#define BIT_LPS_DIS_SW BIT(28)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8881A_SUPPORT)
+
+/* 2 REG_WLLPS_CTRL				(Offset 0x0090) */
+
+#define BIT_WLLPSOP_PWMM BIT(27)
+#define BIT_WLLPSOP_EECK BIT(26)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_WLLPS_CTRL				(Offset 0x0090) */
+
+#define BIT_WLLPSOP_WLPON BIT(25)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_WLLPS_CTRL				(Offset 0x0090) */
+
+#define BIT_WLLPSOP_WLMACOFF BIT(25)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_WLLPS_CTRL				(Offset 0x0090) */
+
+#define BIT_WLLPSOP_ELDO BIT(25)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8881A_SUPPORT)
+
+/* 2 REG_WLLPS_CTRL				(Offset 0x0090) */
+
+#define BIT_WLLPSOP_EXTAL BIT(24)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_WLLPS_CTRL				(Offset 0x0090) */
+
+#define BIT_WL_SYNPON_VOLTSPDN BIT(23)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_WLLPS_CTRL				(Offset 0x0090) */
+
+#define BIT_LPS_BB_REG_EN BIT(23)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_WLLPS_CTRL				(Offset 0x0090) */
+
+#define BIT_LOP_SKIP BIT(22)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_WLLPS_CTRL				(Offset 0x0090) */
+
+#define BIT_WLLPSOP_WLBBOFF BIT(22)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_WLLPS_CTRL				(Offset 0x0090) */
+
+#define BIT_LPS_BB_PWR_EN BIT(22)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_WLLPS_CTRL				(Offset 0x0090) */
+
+#define BIT_LOP_MEMDS BIT(21)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_WLLPS_CTRL				(Offset 0x0090) */
+
+#define BIT_WLLPSOP_WLMEM_DS BIT(21)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_WLLPS_CTRL				(Offset 0x0090) */
+
+#define BIT_LPS_BB_GLB_EN BIT(21)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_WLLPS_CTRL				(Offset 0x0090) */
+
+#define BIT_WLLPSOP_LDO_WAIT_TIME BIT(20)
+#define BIT_WLLPSOP_ANA_CLK_DIVISION_2 BIT(19)
+#define BIT_AFE_BCN BIT(18)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_WLLPS_CTRL				(Offset 0x0090) */
+
+#define BIT_SUS_DIS_SW BIT(15)
+#define BIT_SUS_SKP_PAGE0_ALD BIT(14)
+#define BIT_SUS_LDO_SLEEP BIT(13)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_WLLPS_CTRL				(Offset 0x0090) */
+
+#define BIT_SHIFT_LPLDH12_VADJ_STEP_DN 12
+#define BIT_MASK_LPLDH12_VADJ_STEP_DN 0xf
+#define BIT_LPLDH12_VADJ_STEP_DN(x)                                            \
+	(((x) & BIT_MASK_LPLDH12_VADJ_STEP_DN)                                 \
+	 << BIT_SHIFT_LPLDH12_VADJ_STEP_DN)
+#define BITS_LPLDH12_VADJ_STEP_DN                                              \
+	(BIT_MASK_LPLDH12_VADJ_STEP_DN << BIT_SHIFT_LPLDH12_VADJ_STEP_DN)
+#define BIT_CLEAR_LPLDH12_VADJ_STEP_DN(x) ((x) & (~BITS_LPLDH12_VADJ_STEP_DN))
+#define BIT_GET_LPLDH12_VADJ_STEP_DN(x)                                        \
+	(((x) >> BIT_SHIFT_LPLDH12_VADJ_STEP_DN) &                             \
+	 BIT_MASK_LPLDH12_VADJ_STEP_DN)
+#define BIT_SET_LPLDH12_VADJ_STEP_DN(x, v)                                     \
+	(BIT_CLEAR_LPLDH12_VADJ_STEP_DN(x) | BIT_LPLDH12_VADJ_STEP_DN(v))
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_WLLPS_CTRL				(Offset 0x0090) */
+
+#define BIT_PFM_EN_ZCD BIT(12)
+#define BIT_KEEP_RFC_EN BIT(11)
+#define BIT_MACON_NO_RFCISO_RELEASE BIT(10)
+#define BIT_MACON_NO_AFEPORT_PWR BIT(9)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT)
+
+/* 2 REG_WLLPS_CTRL				(Offset 0x0090) */
+
+#define BIT_SHIFT_V15ADJ_L1_STEP_DN 8
+#define BIT_MASK_V15ADJ_L1_STEP_DN 0x7
+#define BIT_V15ADJ_L1_STEP_DN(x)                                               \
+	(((x) & BIT_MASK_V15ADJ_L1_STEP_DN) << BIT_SHIFT_V15ADJ_L1_STEP_DN)
+#define BITS_V15ADJ_L1_STEP_DN                                                 \
+	(BIT_MASK_V15ADJ_L1_STEP_DN << BIT_SHIFT_V15ADJ_L1_STEP_DN)
+#define BIT_CLEAR_V15ADJ_L1_STEP_DN(x) ((x) & (~BITS_V15ADJ_L1_STEP_DN))
+#define BIT_GET_V15ADJ_L1_STEP_DN(x)                                           \
+	(((x) >> BIT_SHIFT_V15ADJ_L1_STEP_DN) & BIT_MASK_V15ADJ_L1_STEP_DN)
+#define BIT_SET_V15ADJ_L1_STEP_DN(x, v)                                        \
+	(BIT_CLEAR_V15ADJ_L1_STEP_DN(x) | BIT_V15ADJ_L1_STEP_DN(v))
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_WLLPS_CTRL				(Offset 0x0090) */
+
+#define BIT_SHIFT_V15ADJ_L1_STEP_DN_V1 8
+#define BIT_MASK_V15ADJ_L1_STEP_DN_V1 0xf
+#define BIT_V15ADJ_L1_STEP_DN_V1(x)                                            \
+	(((x) & BIT_MASK_V15ADJ_L1_STEP_DN_V1)                                 \
+	 << BIT_SHIFT_V15ADJ_L1_STEP_DN_V1)
+#define BITS_V15ADJ_L1_STEP_DN_V1                                              \
+	(BIT_MASK_V15ADJ_L1_STEP_DN_V1 << BIT_SHIFT_V15ADJ_L1_STEP_DN_V1)
+#define BIT_CLEAR_V15ADJ_L1_STEP_DN_V1(x) ((x) & (~BITS_V15ADJ_L1_STEP_DN_V1))
+#define BIT_GET_V15ADJ_L1_STEP_DN_V1(x)                                        \
+	(((x) >> BIT_SHIFT_V15ADJ_L1_STEP_DN_V1) &                             \
+	 BIT_MASK_V15ADJ_L1_STEP_DN_V1)
+#define BIT_SET_V15ADJ_L1_STEP_DN_V1(x, v)                                     \
+	(BIT_CLEAR_V15ADJ_L1_STEP_DN_V1(x) | BIT_V15ADJ_L1_STEP_DN_V1(v))
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_WLLPS_CTRL				(Offset 0x0090) */
+
+#define BIT_MACON_NO_CPU_EN BIT(8)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_WLLPS_CTRL				(Offset 0x0090) */
+
+#define BIT_LD_B15V_EN BIT(7)
+#define BIT_LPRX_BCN_EN BIT(5)
+#define BIT_LBN BIT(4)
+#define BIT_LXSPS_UNUSED BIT(3)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_WLLPS_CTRL				(Offset 0x0090) */
+
+#define BIT_FORCE_LEAVE_LPS BIT(3)
+#define BIT_SW_AFE_MODE BIT(2)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_WLLPS_CTRL				(Offset 0x0090) */
+
+#define BIT_REGU_32K_CLK_EN BIT(1)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_SDIO_HSISR				(Offset 0x10250090) */
+
+#define BIT_DRV_WLAN_INT_CLR BIT(1)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8881A_SUPPORT)
+
+/* 2 REG_WLLPS_CTRL				(Offset 0x0090) */
+
+#define BIT_WL_LPS_EN BIT(0)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_SDIO_HSISR				(Offset 0x10250090) */
+
+#define BIT_DRV_WLAN_INT BIT(0)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_SDIO_HSIMR				(Offset 0x10250091) */
+
+#define BIT_HISR_MASK BIT(0)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_AFE_CTRL5				(Offset 0x0094) */
+
+#define BIT_BB_DBG_SEL_AFE_SDM_V3 BIT(31)
+
+#endif
+
+#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+
+/* 2 REG_AFE_CTRL5				(Offset 0x0094) */
+
+#define BIT_BB_DBG_SEL_AFE_SDM_BIT0 BIT(31)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+
+/* 2 REG_AFE_CTRL5				(Offset 0x0094) */
+
+#define BIT_ORDER_SDM BIT(30)
+#define BIT_RFE_SEL_SDM BIT(29)
+
+#define BIT_SHIFT_REF_SEL 25
+#define BIT_MASK_REF_SEL 0xf
+#define BIT_REF_SEL(x) (((x) & BIT_MASK_REF_SEL) << BIT_SHIFT_REF_SEL)
+#define BITS_REF_SEL (BIT_MASK_REF_SEL << BIT_SHIFT_REF_SEL)
+#define BIT_CLEAR_REF_SEL(x) ((x) & (~BITS_REF_SEL))
+#define BIT_GET_REF_SEL(x) (((x) >> BIT_SHIFT_REF_SEL) & BIT_MASK_REF_SEL)
+#define BIT_SET_REF_SEL(x, v) (BIT_CLEAR_REF_SEL(x) | BIT_REF_SEL(v))
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_AFE_CTRL5				(Offset 0x0094) */
+
+#define BIT_SHIFT_F0F_SDM_V2 12
+#define BIT_MASK_F0F_SDM_V2 0x1fff
+#define BIT_F0F_SDM_V2(x) (((x) & BIT_MASK_F0F_SDM_V2) << BIT_SHIFT_F0F_SDM_V2)
+#define BITS_F0F_SDM_V2 (BIT_MASK_F0F_SDM_V2 << BIT_SHIFT_F0F_SDM_V2)
+#define BIT_CLEAR_F0F_SDM_V2(x) ((x) & (~BITS_F0F_SDM_V2))
+#define BIT_GET_F0F_SDM_V2(x)                                                  \
+	(((x) >> BIT_SHIFT_F0F_SDM_V2) & BIT_MASK_F0F_SDM_V2)
+#define BIT_SET_F0F_SDM_V2(x, v) (BIT_CLEAR_F0F_SDM_V2(x) | BIT_F0F_SDM_V2(v))
+
+#endif
+
+#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+
+/* 2 REG_AFE_CTRL5				(Offset 0x0094) */
+
+#define BIT_SHIFT_F0F_SDM 12
+#define BIT_MASK_F0F_SDM 0x1fff
+#define BIT_F0F_SDM(x) (((x) & BIT_MASK_F0F_SDM) << BIT_SHIFT_F0F_SDM)
+#define BITS_F0F_SDM (BIT_MASK_F0F_SDM << BIT_SHIFT_F0F_SDM)
+#define BIT_CLEAR_F0F_SDM(x) ((x) & (~BITS_F0F_SDM))
+#define BIT_GET_F0F_SDM(x) (((x) >> BIT_SHIFT_F0F_SDM) & BIT_MASK_F0F_SDM)
+#define BIT_SET_F0F_SDM(x, v) (BIT_CLEAR_F0F_SDM(x) | BIT_F0F_SDM(v))
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_AFE_CTRL5				(Offset 0x0094) */
+
+#define BIT_SHIFT_F0N_SDM_V2 9
+#define BIT_MASK_F0N_SDM_V2 0x7
+#define BIT_F0N_SDM_V2(x) (((x) & BIT_MASK_F0N_SDM_V2) << BIT_SHIFT_F0N_SDM_V2)
+#define BITS_F0N_SDM_V2 (BIT_MASK_F0N_SDM_V2 << BIT_SHIFT_F0N_SDM_V2)
+#define BIT_CLEAR_F0N_SDM_V2(x) ((x) & (~BITS_F0N_SDM_V2))
+#define BIT_GET_F0N_SDM_V2(x)                                                  \
+	(((x) >> BIT_SHIFT_F0N_SDM_V2) & BIT_MASK_F0N_SDM_V2)
+#define BIT_SET_F0N_SDM_V2(x, v) (BIT_CLEAR_F0N_SDM_V2(x) | BIT_F0N_SDM_V2(v))
+
+#endif
+
+#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+
+/* 2 REG_AFE_CTRL5				(Offset 0x0094) */
+
+#define BIT_SHIFT_F0N_SDM 9
+#define BIT_MASK_F0N_SDM 0x7
+#define BIT_F0N_SDM(x) (((x) & BIT_MASK_F0N_SDM) << BIT_SHIFT_F0N_SDM)
+#define BITS_F0N_SDM (BIT_MASK_F0N_SDM << BIT_SHIFT_F0N_SDM)
+#define BIT_CLEAR_F0N_SDM(x) ((x) & (~BITS_F0N_SDM))
+#define BIT_GET_F0N_SDM(x) (((x) >> BIT_SHIFT_F0N_SDM) & BIT_MASK_F0N_SDM)
+#define BIT_SET_F0N_SDM(x, v) (BIT_CLEAR_F0N_SDM(x) | BIT_F0N_SDM(v))
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_AFE_CTRL5				(Offset 0x0094) */
+
+#define BIT_SHIFT_DIVN_SDM_V2 3
+#define BIT_MASK_DIVN_SDM_V2 0x3f
+#define BIT_DIVN_SDM_V2(x)                                                     \
+	(((x) & BIT_MASK_DIVN_SDM_V2) << BIT_SHIFT_DIVN_SDM_V2)
+#define BITS_DIVN_SDM_V2 (BIT_MASK_DIVN_SDM_V2 << BIT_SHIFT_DIVN_SDM_V2)
+#define BIT_CLEAR_DIVN_SDM_V2(x) ((x) & (~BITS_DIVN_SDM_V2))
+#define BIT_GET_DIVN_SDM_V2(x)                                                 \
+	(((x) >> BIT_SHIFT_DIVN_SDM_V2) & BIT_MASK_DIVN_SDM_V2)
+#define BIT_SET_DIVN_SDM_V2(x, v)                                              \
+	(BIT_CLEAR_DIVN_SDM_V2(x) | BIT_DIVN_SDM_V2(v))
+
+#endif
+
+#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+
+/* 2 REG_AFE_CTRL5				(Offset 0x0094) */
+
+#define BIT_SHIFT_DIVN_SDM 3
+#define BIT_MASK_DIVN_SDM 0x3f
+#define BIT_DIVN_SDM(x) (((x) & BIT_MASK_DIVN_SDM) << BIT_SHIFT_DIVN_SDM)
+#define BITS_DIVN_SDM (BIT_MASK_DIVN_SDM << BIT_SHIFT_DIVN_SDM)
+#define BIT_CLEAR_DIVN_SDM(x) ((x) & (~BITS_DIVN_SDM))
+#define BIT_GET_DIVN_SDM(x) (((x) >> BIT_SHIFT_DIVN_SDM) & BIT_MASK_DIVN_SDM)
+#define BIT_SET_DIVN_SDM(x, v) (BIT_CLEAR_DIVN_SDM(x) | BIT_DIVN_SDM(v))
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_AFE_CTRL5				(Offset 0x0094) */
+
+#define BIT_SHIFT_DITHER_SDM_V2 0
+#define BIT_MASK_DITHER_SDM_V2 0x7
+#define BIT_DITHER_SDM_V2(x)                                                   \
+	(((x) & BIT_MASK_DITHER_SDM_V2) << BIT_SHIFT_DITHER_SDM_V2)
+#define BITS_DITHER_SDM_V2 (BIT_MASK_DITHER_SDM_V2 << BIT_SHIFT_DITHER_SDM_V2)
+#define BIT_CLEAR_DITHER_SDM_V2(x) ((x) & (~BITS_DITHER_SDM_V2))
+#define BIT_GET_DITHER_SDM_V2(x)                                               \
+	(((x) >> BIT_SHIFT_DITHER_SDM_V2) & BIT_MASK_DITHER_SDM_V2)
+#define BIT_SET_DITHER_SDM_V2(x, v)                                            \
+	(BIT_CLEAR_DITHER_SDM_V2(x) | BIT_DITHER_SDM_V2(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_GPIO_DEBOUNCE_CTRL			(Offset 0x0098) */
+
+#define BIT_WLGP_DBC1EN BIT(15)
+
+#define BIT_SHIFT_WLGP_DBC1 8
+#define BIT_MASK_WLGP_DBC1 0xf
+#define BIT_WLGP_DBC1(x) (((x) & BIT_MASK_WLGP_DBC1) << BIT_SHIFT_WLGP_DBC1)
+#define BITS_WLGP_DBC1 (BIT_MASK_WLGP_DBC1 << BIT_SHIFT_WLGP_DBC1)
+#define BIT_CLEAR_WLGP_DBC1(x) ((x) & (~BITS_WLGP_DBC1))
+#define BIT_GET_WLGP_DBC1(x) (((x) >> BIT_SHIFT_WLGP_DBC1) & BIT_MASK_WLGP_DBC1)
+#define BIT_SET_WLGP_DBC1(x, v) (BIT_CLEAR_WLGP_DBC1(x) | BIT_WLGP_DBC1(v))
+
+#define BIT_WLGP_DBC0EN BIT(7)
+
+#define BIT_SHIFT_WLGP_DBC0 0
+#define BIT_MASK_WLGP_DBC0 0xf
+#define BIT_WLGP_DBC0(x) (((x) & BIT_MASK_WLGP_DBC0) << BIT_SHIFT_WLGP_DBC0)
+#define BITS_WLGP_DBC0 (BIT_MASK_WLGP_DBC0 << BIT_SHIFT_WLGP_DBC0)
+#define BIT_CLEAR_WLGP_DBC0(x) ((x) & (~BITS_WLGP_DBC0))
+#define BIT_GET_WLGP_DBC0(x) (((x) >> BIT_SHIFT_WLGP_DBC0) & BIT_MASK_WLGP_DBC0)
+#define BIT_SET_WLGP_DBC0(x, v) (BIT_CLEAR_WLGP_DBC0(x) | BIT_WLGP_DBC0(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_RPWM2				(Offset 0x009C) */
+
+#define BIT_SHIFT_RPWM2 16
+#define BIT_MASK_RPWM2 0xffff
+#define BIT_RPWM2(x) (((x) & BIT_MASK_RPWM2) << BIT_SHIFT_RPWM2)
+#define BITS_RPWM2 (BIT_MASK_RPWM2 << BIT_SHIFT_RPWM2)
+#define BIT_CLEAR_RPWM2(x) ((x) & (~BITS_RPWM2))
+#define BIT_GET_RPWM2(x) (((x) >> BIT_SHIFT_RPWM2) & BIT_MASK_RPWM2)
+#define BIT_SET_RPWM2(x, v) (BIT_CLEAR_RPWM2(x) | BIT_RPWM2(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8881A_SUPPORT)
+
+/* 2 REG_SYSON_FSM_MON			(Offset 0x00A0) */
+
+#define BIT_SHIFT_FSM_MON_SEL 24
+#define BIT_MASK_FSM_MON_SEL 0x7
+#define BIT_FSM_MON_SEL(x)                                                     \
+	(((x) & BIT_MASK_FSM_MON_SEL) << BIT_SHIFT_FSM_MON_SEL)
+#define BITS_FSM_MON_SEL (BIT_MASK_FSM_MON_SEL << BIT_SHIFT_FSM_MON_SEL)
+#define BIT_CLEAR_FSM_MON_SEL(x) ((x) & (~BITS_FSM_MON_SEL))
+#define BIT_GET_FSM_MON_SEL(x)                                                 \
+	(((x) >> BIT_SHIFT_FSM_MON_SEL) & BIT_MASK_FSM_MON_SEL)
+#define BIT_SET_FSM_MON_SEL(x, v)                                              \
+	(BIT_CLEAR_FSM_MON_SEL(x) | BIT_FSM_MON_SEL(v))
+
+#define BIT_DOP_ELDO BIT(23)
+#define BIT_FSM_MON_UPD BIT(15)
+
+#define BIT_SHIFT_FSM_PAR 0
+#define BIT_MASK_FSM_PAR 0x7fff
+#define BIT_FSM_PAR(x) (((x) & BIT_MASK_FSM_PAR) << BIT_SHIFT_FSM_PAR)
+#define BITS_FSM_PAR (BIT_MASK_FSM_PAR << BIT_SHIFT_FSM_PAR)
+#define BIT_CLEAR_FSM_PAR(x) ((x) & (~BITS_FSM_PAR))
+#define BIT_GET_FSM_PAR(x) (((x) >> BIT_SHIFT_FSM_PAR) & BIT_MASK_FSM_PAR)
+#define BIT_SET_FSM_PAR(x, v) (BIT_CLEAR_FSM_PAR(x) | BIT_FSM_PAR(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_AFE_CTRL6				(Offset 0x00A4) */
+
+#define BIT_SHIFT_TSFT_SEL_V1 0
+#define BIT_MASK_TSFT_SEL_V1 0x7
+#define BIT_TSFT_SEL_V1(x)                                                     \
+	(((x) & BIT_MASK_TSFT_SEL_V1) << BIT_SHIFT_TSFT_SEL_V1)
+#define BITS_TSFT_SEL_V1 (BIT_MASK_TSFT_SEL_V1 << BIT_SHIFT_TSFT_SEL_V1)
+#define BIT_CLEAR_TSFT_SEL_V1(x) ((x) & (~BITS_TSFT_SEL_V1))
+#define BIT_GET_TSFT_SEL_V1(x)                                                 \
+	(((x) >> BIT_SHIFT_TSFT_SEL_V1) & BIT_MASK_TSFT_SEL_V1)
+#define BIT_SET_TSFT_SEL_V1(x, v)                                              \
+	(BIT_CLEAR_TSFT_SEL_V1(x) | BIT_TSFT_SEL_V1(v))
+
+#endif
+
+#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+
+/* 2 REG_AFE_CTRL6				(Offset 0x00A4) */
+
+#define BIT_SHIFT_BB_DBG_SEL_AFE_SDM_BIT3_1 0
+#define BIT_MASK_BB_DBG_SEL_AFE_SDM_BIT3_1 0x7
+#define BIT_BB_DBG_SEL_AFE_SDM_BIT3_1(x)                                       \
+	(((x) & BIT_MASK_BB_DBG_SEL_AFE_SDM_BIT3_1)                            \
+	 << BIT_SHIFT_BB_DBG_SEL_AFE_SDM_BIT3_1)
+#define BITS_BB_DBG_SEL_AFE_SDM_BIT3_1                                         \
+	(BIT_MASK_BB_DBG_SEL_AFE_SDM_BIT3_1                                    \
+	 << BIT_SHIFT_BB_DBG_SEL_AFE_SDM_BIT3_1)
+#define BIT_CLEAR_BB_DBG_SEL_AFE_SDM_BIT3_1(x)                                 \
+	((x) & (~BITS_BB_DBG_SEL_AFE_SDM_BIT3_1))
+#define BIT_GET_BB_DBG_SEL_AFE_SDM_BIT3_1(x)                                   \
+	(((x) >> BIT_SHIFT_BB_DBG_SEL_AFE_SDM_BIT3_1) &                        \
+	 BIT_MASK_BB_DBG_SEL_AFE_SDM_BIT3_1)
+#define BIT_SET_BB_DBG_SEL_AFE_SDM_BIT3_1(x, v)                                \
+	(BIT_CLEAR_BB_DBG_SEL_AFE_SDM_BIT3_1(x) |                              \
+	 BIT_BB_DBG_SEL_AFE_SDM_BIT3_1(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_PMC_DBG_CTRL1			(Offset 0x00A8) */
+
+#define BIT_BT_INT_EN BIT(31)
+
+#define BIT_SHIFT_RD_WR_WIFI_BT_INFO 16
+#define BIT_MASK_RD_WR_WIFI_BT_INFO 0x7fff
+#define BIT_RD_WR_WIFI_BT_INFO(x)                                              \
+	(((x) & BIT_MASK_RD_WR_WIFI_BT_INFO) << BIT_SHIFT_RD_WR_WIFI_BT_INFO)
+#define BITS_RD_WR_WIFI_BT_INFO                                                \
+	(BIT_MASK_RD_WR_WIFI_BT_INFO << BIT_SHIFT_RD_WR_WIFI_BT_INFO)
+#define BIT_CLEAR_RD_WR_WIFI_BT_INFO(x) ((x) & (~BITS_RD_WR_WIFI_BT_INFO))
+#define BIT_GET_RD_WR_WIFI_BT_INFO(x)                                          \
+	(((x) >> BIT_SHIFT_RD_WR_WIFI_BT_INFO) & BIT_MASK_RD_WR_WIFI_BT_INFO)
+#define BIT_SET_RD_WR_WIFI_BT_INFO(x, v)                                       \
+	(BIT_CLEAR_RD_WR_WIFI_BT_INFO(x) | BIT_RD_WR_WIFI_BT_INFO(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_PMC_DBG_CTRL1			(Offset 0x00A8) */
+
+#define BIT_PMC_WR_OVF BIT(8)
+
+#define BIT_SHIFT_WLPMC_ERRINT 0
+#define BIT_MASK_WLPMC_ERRINT 0xff
+#define BIT_WLPMC_ERRINT(x)                                                    \
+	(((x) & BIT_MASK_WLPMC_ERRINT) << BIT_SHIFT_WLPMC_ERRINT)
+#define BITS_WLPMC_ERRINT (BIT_MASK_WLPMC_ERRINT << BIT_SHIFT_WLPMC_ERRINT)
+#define BIT_CLEAR_WLPMC_ERRINT(x) ((x) & (~BITS_WLPMC_ERRINT))
+#define BIT_GET_WLPMC_ERRINT(x)                                                \
+	(((x) >> BIT_SHIFT_WLPMC_ERRINT) & BIT_MASK_WLPMC_ERRINT)
+#define BIT_SET_WLPMC_ERRINT(x, v)                                             \
+	(BIT_CLEAR_WLPMC_ERRINT(x) | BIT_WLPMC_ERRINT(v))
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+
+/* 2 REG_AFE_CTRL7				(Offset 0x00AC) */
+
+#define BIT_SHIFT_SEL_V 30
+#define BIT_MASK_SEL_V 0x3
+#define BIT_SEL_V(x) (((x) & BIT_MASK_SEL_V) << BIT_SHIFT_SEL_V)
+#define BITS_SEL_V (BIT_MASK_SEL_V << BIT_SHIFT_SEL_V)
+#define BIT_CLEAR_SEL_V(x) ((x) & (~BITS_SEL_V))
+#define BIT_GET_SEL_V(x) (((x) >> BIT_SHIFT_SEL_V) & BIT_MASK_SEL_V)
+#define BIT_SET_SEL_V(x, v) (BIT_CLEAR_SEL_V(x) | BIT_SEL_V(v))
+
+#define BIT_SEL_LDO_PC BIT(29)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+
+/* 2 REG_AFE_CTRL7				(Offset 0x00AC) */
+
+#define BIT_SHIFT_CK_MON_SEL 26
+#define BIT_MASK_CK_MON_SEL 0x7
+#define BIT_CK_MON_SEL(x) (((x) & BIT_MASK_CK_MON_SEL) << BIT_SHIFT_CK_MON_SEL)
+#define BITS_CK_MON_SEL (BIT_MASK_CK_MON_SEL << BIT_SHIFT_CK_MON_SEL)
+#define BIT_CLEAR_CK_MON_SEL(x) ((x) & (~BITS_CK_MON_SEL))
+#define BIT_GET_CK_MON_SEL(x)                                                  \
+	(((x) >> BIT_SHIFT_CK_MON_SEL) & BIT_MASK_CK_MON_SEL)
+#define BIT_SET_CK_MON_SEL(x, v) (BIT_CLEAR_CK_MON_SEL(x) | BIT_CK_MON_SEL(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_AFE_CTRL7				(Offset 0x00AC) */
+
+#define BIT_SHIFT_CK_MON_SEL_V2 26
+#define BIT_MASK_CK_MON_SEL_V2 0x7
+#define BIT_CK_MON_SEL_V2(x)                                                   \
+	(((x) & BIT_MASK_CK_MON_SEL_V2) << BIT_SHIFT_CK_MON_SEL_V2)
+#define BITS_CK_MON_SEL_V2 (BIT_MASK_CK_MON_SEL_V2 << BIT_SHIFT_CK_MON_SEL_V2)
+#define BIT_CLEAR_CK_MON_SEL_V2(x) ((x) & (~BITS_CK_MON_SEL_V2))
+#define BIT_GET_CK_MON_SEL_V2(x)                                               \
+	(((x) >> BIT_SHIFT_CK_MON_SEL_V2) & BIT_MASK_CK_MON_SEL_V2)
+#define BIT_SET_CK_MON_SEL_V2(x, v)                                            \
+	(BIT_CLEAR_CK_MON_SEL_V2(x) | BIT_CK_MON_SEL_V2(v))
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+
+/* 2 REG_AFE_CTRL7				(Offset 0x00AC) */
+
+#define BIT_CK_MON_EN BIT(25)
+#define BIT_FREF_EDGE BIT(24)
+#define BIT_CK320M_EN BIT(23)
+#define BIT_CK_5M_EN BIT(22)
+#define BIT_TESTEN BIT(21)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_AFE_CTRL7				(Offset 0x00AC) */
+
+#define BIT_LD_B12V_EN_V1 BIT(7)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_HIMR0				(Offset 0x00B0) */
+
+#define BIT_TIMEOUT_INTERRUPT2_MASK BIT(31)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_HIMR0				(Offset 0x00B0) */
+
+#define BIT_PSTIMER_2_MSK BIT(31)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_HIMR0				(Offset 0x00B0) */
+
+#define BIT_TIMEOUT_INTERRUTP1_MASK BIT(30)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_HIMR0				(Offset 0x00B0) */
+
+#define BIT_PSTIMER_1_MSK BIT(30)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_HIMR0				(Offset 0x00B0) */
+
+#define BIT_PSTIMEOUT_MSK BIT(29)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_HIMR0				(Offset 0x00B0) */
+
+#define BIT_PSTIMER_0_MSK BIT(29)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_HIMR0				(Offset 0x00B0) */
+
+#define BIT_GTINT4_MSK BIT(28)
+#define BIT_GTINT4 BIT(28)
+#define BIT_GTINT3_MSK BIT(27)
+#define BIT_GTINT3 BIT(27)
+#define BIT_TXBCN0ERR_MSK BIT(26)
+#define BIT_TXBCN0ERR BIT(26)
+#define BIT_TXBCN0OK_MSK BIT(25)
+#define BIT_TXBCN0OK BIT(25)
+#define BIT_TSF_BIT32_TOGGLE_MSK BIT(24)
+#define BIT_TSF_BIT32_TOGGLE BIT(24)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_HIMR0				(Offset 0x00B0) */
+
+#define BIT_TXDMA_START_INT_MSK BIT(23)
+#define BIT_TXDMA_STOP_INT_MSK BIT(22)
+#define BIT_HISR7_IND_MSK BIT(21)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_HIMR0				(Offset 0x00B0) */
+
+#define BIT_BCNDMAINT0_MSK BIT(20)
+#define BIT_BCNDMAINT0 BIT(20)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_HIMR0				(Offset 0x00B0) */
+
+#define BIT_HISR6_IND_MSK BIT(19)
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+/* 2 REG_HIMR0				(Offset 0x00B0) */
+
+#define BIT_HISR5_MSK BIT(18)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_HIMR0				(Offset 0x00B0) */
+
+#define BIT_HISR5_IND_MSK BIT(18)
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+/* 2 REG_HIMR0				(Offset 0x00B0) */
+
+#define BIT_HISR4_MSK BIT(17)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_HIMR0				(Offset 0x00B0) */
+
+#define BIT_HISR4_IND_MSK BIT(17)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_HIMR0				(Offset 0x00B0) */
+
+#define BIT_BCNDERR0_MSK BIT(16)
+#define BIT_BCNDERR0 BIT(16)
+#define BIT_HSISR_IND_ON_INT_MSK BIT(15)
+#define BIT_HSISR_IND_ON_INT BIT(15)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_HIMR0				(Offset 0x00B0) */
+
+#define BIT_BCNDMAINT_E_MSK BIT(14)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT)
+
+/* 2 REG_HIMR0				(Offset 0x00B0) */
+
+#define BIT_HISR3_IND_INT_MSK BIT(14)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_HIMR0				(Offset 0x00B0) */
+
+#define BIT_HISR3_IND_MSK BIT(14)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT)
+
+/* 2 REG_HIMR0				(Offset 0x00B0) */
+
+#define BIT_HISR2_IND_INT_MSK BIT(13)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_HIMR0				(Offset 0x00B0) */
+
+#define BIT_HISR2_IND_MSK BIT(13)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_HIMR0				(Offset 0x00B0) */
+
+#define BIT_CTWEND_MSK BIT(12)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8881A_SUPPORT)
+
+/* 2 REG_HIMR0				(Offset 0x00B0) */
+
+#define BIT_HISR1_IND_MSK BIT(11)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_HIMR0				(Offset 0x00B0) */
+
+#define BIT_HISR1_IND_INT_MSK BIT(11)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_HIMR0				(Offset 0x00B0) */
+
+#define BIT_C2HCMD_MSK BIT(10)
+#define BIT_C2HCMD BIT(10)
+#define BIT_CPWM2_MSK BIT(9)
+#define BIT_CPWM2 BIT(9)
+#define BIT_CPWM_MSK BIT(8)
+#define BIT_CPWM BIT(8)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_HIMR0				(Offset 0x00B0) */
+
+#define BIT_HIGHDOK_MSK BIT(7)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_HIMR0				(Offset 0x00B0) */
+
+#define BIT_TXDMAOK_CHANNEL15_MSK BIT(7)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_HIMR0				(Offset 0x00B0) */
+
+#define BIT_MGTDOK_MSK BIT(6)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_HIMR0				(Offset 0x00B0) */
+
+#define BIT_TXDMAOK_CHANNEL14_MSK BIT(6)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_HIMR0				(Offset 0x00B0) */
+
+#define BIT_BKDOK_MSK BIT(5)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_HIMR0				(Offset 0x00B0) */
+
+#define BIT_TXDMAOK_CHANNEL3_MSK BIT(5)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_HIMR0				(Offset 0x00B0) */
+
+#define BIT_BEDOK_MSK BIT(4)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_HIMR0				(Offset 0x00B0) */
+
+#define BIT_TXDMAOK_CHANNEL2_MSK BIT(4)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_HIMR0				(Offset 0x00B0) */
+
+#define BIT_VIDOK_MSK BIT(3)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_HIMR0				(Offset 0x00B0) */
+
+#define BIT_TXDMAOK_CHANNEL1_MSK BIT(3)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_HIMR0				(Offset 0x00B0) */
+
+#define BIT_VODOK_MSK BIT(2)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_HIMR0				(Offset 0x00B0) */
+
+#define BIT_TXDMAOK_CHANNEL0_MSK BIT(2)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_HIMR0				(Offset 0x00B0) */
+
+#define BIT_RDU_MSK BIT(1)
+#define BIT_RDU BIT(1)
+#define BIT_RXOK_MSK BIT(0)
+#define BIT_RXOK BIT(0)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_HISR0				(Offset 0x00B4) */
+
+#define BIT_PSTIMEOUT2 BIT(31)
+#define BIT_PSTIMEOUT1 BIT(30)
+#define BIT_PSTIMEOUT BIT(29)
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+/* 2 REG_HISR0				(Offset 0x00B4) */
+
+#define BIT_HISR5_IND_INT BIT(18)
+#define BIT_HISR4_IND_INT BIT(17)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_HISR0				(Offset 0x00B4) */
+
+#define BIT_BCNDMAINT_E BIT(14)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT)
+
+/* 2 REG_HISR0				(Offset 0x00B4) */
+
+#define BIT_HISR3_IND_INT BIT(14)
+#define BIT_HISR2_IND_INT BIT(13)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_HISR0				(Offset 0x00B4) */
+
+#define BIT_CTWEND BIT(12)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_HISR0				(Offset 0x00B4) */
+
+#define BIT_HISR1_IND_INT BIT(11)
+#define BIT_HIGHDOK BIT(7)
+#define BIT_MGTDOK BIT(6)
+#define BIT_BKDOK BIT(5)
+#define BIT_BEDOK BIT(4)
+#define BIT_VIDOK BIT(3)
+#define BIT_VODOK BIT(2)
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+/* 2 REG_HIMR1				(Offset 0x00B8) */
+
+#define BIT_PRETXERR_HANDLE_MSK BIT(31)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_HIMR1				(Offset 0x00B8) */
+
+#define BIT_PRE_TX_ERR_INT_MSK BIT(31)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_HIMR1				(Offset 0x00B8) */
+
+#define BIT_BTON_STS_UPDATE_INT BIT(29)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_HIMR1				(Offset 0x00B8) */
+
+#define BIT_BTON_STS_UPDATE_MSK BIT(29)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_HIMR1				(Offset 0x00B8) */
+
+#define BIT_BTON_STS_UPDATE_MASK BIT(29)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_HIMR1				(Offset 0x00B8) */
+
+#define BIT_MCU_ERR_MASK BIT(28)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_HIMR1				(Offset 0x00B8) */
+
+#define BIT_BCNDMAINT7 BIT(27)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8881A_SUPPORT)
+
+/* 2 REG_HIMR1				(Offset 0x00B8) */
+
+#define BIT_BCNDMAINT7_MSK BIT(27)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_HIMR1				(Offset 0x00B8) */
+
+#define BIT_BCNDMAINT7__MSK BIT(27)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_HIMR1				(Offset 0x00B8) */
+
+#define BIT_BCNDMAINT6 BIT(26)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8881A_SUPPORT)
+
+/* 2 REG_HIMR1				(Offset 0x00B8) */
+
+#define BIT_BCNDMAINT6_MSK BIT(26)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_HIMR1				(Offset 0x00B8) */
+
+#define BIT_BCNDMAINT6__MSK BIT(26)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_HIMR1				(Offset 0x00B8) */
+
+#define BIT_BCNDMAINT5 BIT(25)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8881A_SUPPORT)
+
+/* 2 REG_HIMR1				(Offset 0x00B8) */
+
+#define BIT_BCNDMAINT5_MSK BIT(25)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_HIMR1				(Offset 0x00B8) */
+
+#define BIT_BCNDMAINT5__MSK BIT(25)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_HIMR1				(Offset 0x00B8) */
+
+#define BIT_BCNDMAINT4 BIT(24)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8881A_SUPPORT)
+
+/* 2 REG_HIMR1				(Offset 0x00B8) */
+
+#define BIT_BCNDMAINT4_MSK BIT(24)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_HIMR1				(Offset 0x00B8) */
+
+#define BIT_BCNDMAINT4__MSK BIT(24)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_HIMR1				(Offset 0x00B8) */
+
+#define BIT_BCNDMAINT3_MSK BIT(23)
+#define BIT_BCNDMAINT3 BIT(23)
+#define BIT_BCNDMAINT2_MSK BIT(22)
+#define BIT_BCNDMAINT2 BIT(22)
+#define BIT_BCNDMAINT1_MSK BIT(21)
+#define BIT_BCNDMAINT1 BIT(21)
+#define BIT_BCNDERR7_MSK BIT(20)
+#define BIT_BCNDERR7 BIT(20)
+#define BIT_BCNDERR6_MSK BIT(19)
+#define BIT_BCNDERR6 BIT(19)
+#define BIT_BCNDERR5_MSK BIT(18)
+#define BIT_BCNDERR5 BIT(18)
+#define BIT_BCNDERR4_MSK BIT(17)
+#define BIT_BCNDERR4 BIT(17)
+#define BIT_BCNDERR3_MSK BIT(16)
+#define BIT_BCNDERR3 BIT(16)
+#define BIT_BCNDERR2_MSK BIT(15)
+#define BIT_BCNDERR2 BIT(15)
+#define BIT_BCNDERR1_MSK BIT(14)
+#define BIT_BCNDERR1 BIT(14)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_HIMR1				(Offset 0x00B8) */
+
+#define BIT_ATIMEND_E_MSK BIT(13)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8881A_SUPPORT)
+
+/* 2 REG_HIMR1				(Offset 0x00B8) */
+
+#define BIT_ATIMEND_MSK BIT(12)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_HIMR1				(Offset 0x00B8) */
+
+#define BIT_ATIMEND__MSK BIT(12)
+
+#endif
+
+#if (HALMAC_8822B_SUPPORT)
+
+/* 2 REG_HIMR1				(Offset 0x00B8) */
+
+#define BIT_ATIMEND_E_V1_MSK BIT(12)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_HIMR1				(Offset 0x00B8) */
+
+#define BIT_TXERR_MSK BIT(11)
+#define BIT_TXERR_INT BIT(11)
+#define BIT_RXERR_MSK BIT(10)
+#define BIT_RXERR_INT BIT(10)
+#define BIT_TXFOVW_MSK BIT(9)
+#define BIT_TXFOVW BIT(9)
+#define BIT_FOVW_MSK BIT(8)
+#define BIT_FOVW BIT(8)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_HIMR1				(Offset 0x00B8) */
+
+#define BIT_CPU_MGQ_EARLY_INT_MSK BIT(6)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_HIMR1				(Offset 0x00B8) */
+
+#define BIT_CPU_MGQ_TXDONE_MSK BIT(5)
+#define BIT_CPU_MGQ_TXDONE BIT(5)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_HIMR1				(Offset 0x00B8) */
+
+#define BIT_PS_TIMER_C_MSK BIT(4)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_HIMR1				(Offset 0x00B8) */
+
+#define BIT_PSTIMER_5_MSK BIT(4)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_HIMR1				(Offset 0x00B8) */
+
+#define BIT_PS_TIMER_B_MSK BIT(3)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_HIMR1				(Offset 0x00B8) */
+
+#define BIT_PSTIMER_4_MSK BIT(3)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_HIMR1				(Offset 0x00B8) */
+
+#define BIT_PS_TIMER_A_MSK BIT(2)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_HIMR1				(Offset 0x00B8) */
+
+#define BIT_PSTIMER_3_MSK BIT(2)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_HIMR1				(Offset 0x00B8) */
+
+#define BIT_CPUMGQ_TX_TIMER_MSK BIT(1)
+#define BIT_CPUMGQ_TX_TIMER BIT(1)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_HIMR1				(Offset 0x00B8) */
+
+#define BIT_BB_STOPRX_INT_MSK BIT(0)
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+/* 2 REG_HISR1				(Offset 0x00BC) */
+
+#define BIT_PRETXERR_HANDLE_INT BIT(31)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_HISR1				(Offset 0x00BC) */
+
+#define BIT_MCU_ERR BIT(28)
+#define BIT_ATIMEND_E BIT(13)
+
+#endif
+
+#if (HALMAC_8822B_SUPPORT)
+
+/* 2 REG_HISR1				(Offset 0x00BC) */
+
+#define BIT_ATIMEND_E_V1_INT BIT(12)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_HISR1				(Offset 0x00BC) */
+
+#define BIT_PS_TIMER_C BIT(4)
+#define BIT_PS_TIMER_B BIT(3)
+#define BIT_PS_TIMER_A BIT(2)
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+/* 2 REG_HISR1				(Offset 0x00BC) */
+
+#define BIT_SHIFT_SYS_PINMUX_EN 0
+#define BIT_MASK_SYS_PINMUX_EN 0xfffffff
+#define BIT_SYS_PINMUX_EN(x)                                                   \
+	(((x) & BIT_MASK_SYS_PINMUX_EN) << BIT_SHIFT_SYS_PINMUX_EN)
+#define BITS_SYS_PINMUX_EN (BIT_MASK_SYS_PINMUX_EN << BIT_SHIFT_SYS_PINMUX_EN)
+#define BIT_CLEAR_SYS_PINMUX_EN(x) ((x) & (~BITS_SYS_PINMUX_EN))
+#define BIT_GET_SYS_PINMUX_EN(x)                                               \
+	(((x) >> BIT_SHIFT_SYS_PINMUX_EN) & BIT_MASK_SYS_PINMUX_EN)
+#define BIT_SET_SYS_PINMUX_EN(x, v)                                            \
+	(BIT_CLEAR_SYS_PINMUX_EN(x) | BIT_SYS_PINMUX_EN(v))
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+
+/* 2 REG_SDIO_ERR_RPT			(Offset 0x102500C0) */
+
+#define BIT_HR_FF_OVF BIT(6)
+#define BIT_HR_FF_UDN BIT(5)
+#define BIT_TXDMA_BUSY_ERR BIT(4)
+#define BIT_TXDMA_VLD_ERR BIT(3)
+#define BIT_QSEL_UNKNOWN_ERR BIT(2)
+#define BIT_QSEL_MIS_ERR BIT(1)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8881A_SUPPORT)
+
+/* 2 REG_DBG_PORT_SEL			(Offset 0x00C0) */
+
+#define BIT_SHIFT_DEBUG_ST 0
+#define BIT_MASK_DEBUG_ST 0xffffffffL
+#define BIT_DEBUG_ST(x) (((x) & BIT_MASK_DEBUG_ST) << BIT_SHIFT_DEBUG_ST)
+#define BITS_DEBUG_ST (BIT_MASK_DEBUG_ST << BIT_SHIFT_DEBUG_ST)
+#define BIT_CLEAR_DEBUG_ST(x) ((x) & (~BITS_DEBUG_ST))
+#define BIT_GET_DEBUG_ST(x) (((x) >> BIT_SHIFT_DEBUG_ST) & BIT_MASK_DEBUG_ST)
+#define BIT_SET_DEBUG_ST(x, v) (BIT_CLEAR_DEBUG_ST(x) | BIT_DEBUG_ST(v))
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_SDIO_DIOERR_RPT			(Offset 0x102500C0) */
+
+#define BIT_SDIO_PAGE_ERR BIT(0)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+
+/* 2 REG_SDIO_ERR_RPT			(Offset 0x102500C0) */
+
+#define BIT_SDIO_OVERRD_ERR BIT(0)
+
+#define BIT_SHIFT_SDIO_DATA_REPLY_TIME 0
+#define BIT_MASK_SDIO_DATA_REPLY_TIME 0x7
+#define BIT_SDIO_DATA_REPLY_TIME(x)                                            \
+	(((x) & BIT_MASK_SDIO_DATA_REPLY_TIME)                                 \
+	 << BIT_SHIFT_SDIO_DATA_REPLY_TIME)
+#define BITS_SDIO_DATA_REPLY_TIME                                              \
+	(BIT_MASK_SDIO_DATA_REPLY_TIME << BIT_SHIFT_SDIO_DATA_REPLY_TIME)
+#define BIT_CLEAR_SDIO_DATA_REPLY_TIME(x) ((x) & (~BITS_SDIO_DATA_REPLY_TIME))
+#define BIT_GET_SDIO_DATA_REPLY_TIME(x)                                        \
+	(((x) >> BIT_SHIFT_SDIO_DATA_REPLY_TIME) &                             \
+	 BIT_MASK_SDIO_DATA_REPLY_TIME)
+#define BIT_SET_SDIO_DATA_REPLY_TIME(x, v)                                     \
+	(BIT_CLEAR_SDIO_DATA_REPLY_TIME(x) | BIT_SDIO_DATA_REPLY_TIME(v))
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_SDIO_CMD_ERRCNT			(Offset 0x102500C2) */
+
+#define BIT_SHIFT_CMD_CRC_ERR_CNT 0
+#define BIT_MASK_CMD_CRC_ERR_CNT 0xff
+#define BIT_CMD_CRC_ERR_CNT(x)                                                 \
+	(((x) & BIT_MASK_CMD_CRC_ERR_CNT) << BIT_SHIFT_CMD_CRC_ERR_CNT)
+#define BITS_CMD_CRC_ERR_CNT                                                   \
+	(BIT_MASK_CMD_CRC_ERR_CNT << BIT_SHIFT_CMD_CRC_ERR_CNT)
+#define BIT_CLEAR_CMD_CRC_ERR_CNT(x) ((x) & (~BITS_CMD_CRC_ERR_CNT))
+#define BIT_GET_CMD_CRC_ERR_CNT(x)                                             \
+	(((x) >> BIT_SHIFT_CMD_CRC_ERR_CNT) & BIT_MASK_CMD_CRC_ERR_CNT)
+#define BIT_SET_CMD_CRC_ERR_CNT(x, v)                                          \
+	(BIT_CLEAR_CMD_CRC_ERR_CNT(x) | BIT_CMD_CRC_ERR_CNT(v))
+
+/* 2 REG_SDIO_DATA_ERRCNT			(Offset 0x102500C3) */
+
+#define BIT_SHIFT_DATA_CRC_ERR_CNT 0
+#define BIT_MASK_DATA_CRC_ERR_CNT 0xff
+#define BIT_DATA_CRC_ERR_CNT(x)                                                \
+	(((x) & BIT_MASK_DATA_CRC_ERR_CNT) << BIT_SHIFT_DATA_CRC_ERR_CNT)
+#define BITS_DATA_CRC_ERR_CNT                                                  \
+	(BIT_MASK_DATA_CRC_ERR_CNT << BIT_SHIFT_DATA_CRC_ERR_CNT)
+#define BIT_CLEAR_DATA_CRC_ERR_CNT(x) ((x) & (~BITS_DATA_CRC_ERR_CNT))
+#define BIT_GET_DATA_CRC_ERR_CNT(x)                                            \
+	(((x) >> BIT_SHIFT_DATA_CRC_ERR_CNT) & BIT_MASK_DATA_CRC_ERR_CNT)
+#define BIT_SET_DATA_CRC_ERR_CNT(x, v)                                         \
+	(BIT_CLEAR_DATA_CRC_ERR_CNT(x) | BIT_DATA_CRC_ERR_CNT(v))
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_PAD_CTRL2				(Offset 0x00C4) */
+
+#define BIT_MAC_SOP BIT(25)
+#define BIT_LDO11_ST_EXT BIT(24)
+#define BIT_ANTSELB_S2 BIT(23)
+#define BIT_ANTSELB_S1 BIT(22)
+#define BIT_ANTSEL_S3 BIT(21)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_PAD_CTRL2				(Offset 0x00C4) */
+
+#define BIT_USB3_USB2_TRANSITION BIT(20)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_PAD_CTRL2				(Offset 0x00C4) */
+
+#define BIT_ANTSEL_S2 BIT(20)
+#define BIT_ANTSEL_S1 BIT(19)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_PAD_CTRL2				(Offset 0x00C4) */
+
+#define BIT_SHIFT_USB23_SW_MODE_V1 18
+#define BIT_MASK_USB23_SW_MODE_V1 0x3
+#define BIT_USB23_SW_MODE_V1(x)                                                \
+	(((x) & BIT_MASK_USB23_SW_MODE_V1) << BIT_SHIFT_USB23_SW_MODE_V1)
+#define BITS_USB23_SW_MODE_V1                                                  \
+	(BIT_MASK_USB23_SW_MODE_V1 << BIT_SHIFT_USB23_SW_MODE_V1)
+#define BIT_CLEAR_USB23_SW_MODE_V1(x) ((x) & (~BITS_USB23_SW_MODE_V1))
+#define BIT_GET_USB23_SW_MODE_V1(x)                                            \
+	(((x) >> BIT_SHIFT_USB23_SW_MODE_V1) & BIT_MASK_USB23_SW_MODE_V1)
+#define BIT_SET_USB23_SW_MODE_V1(x, v)                                         \
+	(BIT_CLEAR_USB23_SW_MODE_V1(x) | BIT_USB23_SW_MODE_V1(v))
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_PAD_CTRL2				(Offset 0x00C4) */
+
+#define BIT_FCSN_PU BIT(18)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_PAD_CTRL2				(Offset 0x00C4) */
+
+#define BIT_NO_PDN_CHIPOFF_V1 BIT(17)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_PAD_CTRL2				(Offset 0x00C4) */
+
+#define BIT_KEEP_PAD BIT(17)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_PAD_CTRL2				(Offset 0x00C4) */
+
+#define BIT_RSM_EN_V1 BIT(16)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_PAD_CTRL2				(Offset 0x00C4) */
+
+#define BIT_PAD_ALD_SKP BIT(16)
+#define BIT_PAD_A_ANTSEL_E BIT(11)
+#define BIT_PAD_A_ANTSELB_E BIT(10)
+#define BIT_PAD_A_ANTSEL_O BIT(9)
+#define BIT_PAD_A_ANTSELB_O BIT(8)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8881A_SUPPORT)
+
+/* 2 REG_PAD_CTRL2				(Offset 0x00C4) */
+
+#define BIT_LD_B12V_EN BIT(7)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_PAD_CTRL2				(Offset 0x00C4) */
+
+#define BIT_B15V_EN BIT(7)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_PAD_CTRL2				(Offset 0x00C4) */
+
+#define BIT_EESK_IOSEL BIT(6)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_PAD_CTRL2				(Offset 0x00C4) */
+
+#define BIT_EECS_IOSEL_V1 BIT(6)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_PAD_CTRL2				(Offset 0x00C4) */
+
+#define BIT_EESK_DATA_O BIT(5)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_PAD_CTRL2				(Offset 0x00C4) */
+
+#define BIT_EECS_DATA_O_V1 BIT(5)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_PAD_CTRL2				(Offset 0x00C4) */
+
+#define BIT_EESK_DATA_I BIT(4)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_PAD_CTRL2				(Offset 0x00C4) */
+
+#define BIT_EECS_DATA_I_V1 BIT(4)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_PAD_CTRL2				(Offset 0x00C4) */
+
+#define BIT_EECS_IOSEL BIT(2)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_PAD_CTRL2				(Offset 0x00C4) */
+
+#define BIT_EESK_IOSEL_V1 BIT(2)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_PAD_CTRL2				(Offset 0x00C4) */
+
+#define BIT_EECS_DATA_O BIT(1)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_PAD_CTRL2				(Offset 0x00C4) */
+
+#define BIT_EESK_DATA_O_V1 BIT(1)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_PAD_CTRL2				(Offset 0x00C4) */
+
+#define BIT_EECS_DATA_I BIT(0)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_PAD_CTRL2				(Offset 0x00C4) */
+
+#define BIT_EESK_DATA_I_V1 BIT(0)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_SDIO_CMD_ERR_CONTENT		(Offset 0x102500C4) */
+
+#define BIT_SHIFT_SDIO_CMD_ERR_CONTENT 0
+#define BIT_MASK_SDIO_CMD_ERR_CONTENT 0xffffffffffL
+#define BIT_SDIO_CMD_ERR_CONTENT(x)                                            \
+	(((x) & BIT_MASK_SDIO_CMD_ERR_CONTENT)                                 \
+	 << BIT_SHIFT_SDIO_CMD_ERR_CONTENT)
+#define BITS_SDIO_CMD_ERR_CONTENT                                              \
+	(BIT_MASK_SDIO_CMD_ERR_CONTENT << BIT_SHIFT_SDIO_CMD_ERR_CONTENT)
+#define BIT_CLEAR_SDIO_CMD_ERR_CONTENT(x) ((x) & (~BITS_SDIO_CMD_ERR_CONTENT))
+#define BIT_GET_SDIO_CMD_ERR_CONTENT(x)                                        \
+	(((x) >> BIT_SHIFT_SDIO_CMD_ERR_CONTENT) &                             \
+	 BIT_MASK_SDIO_CMD_ERR_CONTENT)
+#define BIT_SET_SDIO_CMD_ERR_CONTENT(x, v)                                     \
+	(BIT_CLEAR_SDIO_CMD_ERR_CONTENT(x) | BIT_SDIO_CMD_ERR_CONTENT(v))
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_MEM_RMC				(Offset 0x00C8) */
+
+#define BIT_SHIFT_MEM_RME_WL_V2 4
+#define BIT_MASK_MEM_RME_WL_V2 0x3f
+#define BIT_MEM_RME_WL_V2(x)                                                   \
+	(((x) & BIT_MASK_MEM_RME_WL_V2) << BIT_SHIFT_MEM_RME_WL_V2)
+#define BITS_MEM_RME_WL_V2 (BIT_MASK_MEM_RME_WL_V2 << BIT_SHIFT_MEM_RME_WL_V2)
+#define BIT_CLEAR_MEM_RME_WL_V2(x) ((x) & (~BITS_MEM_RME_WL_V2))
+#define BIT_GET_MEM_RME_WL_V2(x)                                               \
+	(((x) >> BIT_SHIFT_MEM_RME_WL_V2) & BIT_MASK_MEM_RME_WL_V2)
+#define BIT_SET_MEM_RME_WL_V2(x, v)                                            \
+	(BIT_CLEAR_MEM_RME_WL_V2(x) | BIT_MEM_RME_WL_V2(v))
+
+#define BIT_SHIFT_MEM_RME_HCI_V2 0
+#define BIT_MASK_MEM_RME_HCI_V2 0x1f
+#define BIT_MEM_RME_HCI_V2(x)                                                  \
+	(((x) & BIT_MASK_MEM_RME_HCI_V2) << BIT_SHIFT_MEM_RME_HCI_V2)
+#define BITS_MEM_RME_HCI_V2                                                    \
+	(BIT_MASK_MEM_RME_HCI_V2 << BIT_SHIFT_MEM_RME_HCI_V2)
+#define BIT_CLEAR_MEM_RME_HCI_V2(x) ((x) & (~BITS_MEM_RME_HCI_V2))
+#define BIT_GET_MEM_RME_HCI_V2(x)                                              \
+	(((x) >> BIT_SHIFT_MEM_RME_HCI_V2) & BIT_MASK_MEM_RME_HCI_V2)
+#define BIT_SET_MEM_RME_HCI_V2(x, v)                                           \
+	(BIT_CLEAR_MEM_RME_HCI_V2(x) | BIT_MEM_RME_HCI_V2(v))
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_SDIO_CRC_ERR_IDX			(Offset 0x102500C9) */
+
+#define BIT_D3_CRC_ERR BIT(4)
+#define BIT_D2_CRC_ERR BIT(3)
+#define BIT_D1_CRC_ERR BIT(2)
+#define BIT_D0_CRC_ERR BIT(1)
+#define BIT_CMD_CRC_ERR BIT(0)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_SDIO_DATA_CRC			(Offset 0x102500CA) */
+
+#define BIT_SHIFT_SDIO_DATA_CRC 0
+#define BIT_MASK_SDIO_DATA_CRC 0xffff
+#define BIT_SDIO_DATA_CRC(x)                                                   \
+	(((x) & BIT_MASK_SDIO_DATA_CRC) << BIT_SHIFT_SDIO_DATA_CRC)
+#define BITS_SDIO_DATA_CRC (BIT_MASK_SDIO_DATA_CRC << BIT_SHIFT_SDIO_DATA_CRC)
+#define BIT_CLEAR_SDIO_DATA_CRC(x) ((x) & (~BITS_SDIO_DATA_CRC))
+#define BIT_GET_SDIO_DATA_CRC(x)                                               \
+	(((x) >> BIT_SHIFT_SDIO_DATA_CRC) & BIT_MASK_SDIO_DATA_CRC)
+#define BIT_SET_SDIO_DATA_CRC(x, v)                                            \
+	(BIT_CLEAR_SDIO_DATA_CRC(x) | BIT_SDIO_DATA_CRC(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8881A_SUPPORT)
+
+/* 2 REG_PMC_DBG_CTRL2			(Offset 0x00CC) */
+
+#define BIT_SHIFT_EFUSE_BURN_GNT 24
+#define BIT_MASK_EFUSE_BURN_GNT 0xff
+#define BIT_EFUSE_BURN_GNT(x)                                                  \
+	(((x) & BIT_MASK_EFUSE_BURN_GNT) << BIT_SHIFT_EFUSE_BURN_GNT)
+#define BITS_EFUSE_BURN_GNT                                                    \
+	(BIT_MASK_EFUSE_BURN_GNT << BIT_SHIFT_EFUSE_BURN_GNT)
+#define BIT_CLEAR_EFUSE_BURN_GNT(x) ((x) & (~BITS_EFUSE_BURN_GNT))
+#define BIT_GET_EFUSE_BURN_GNT(x)                                              \
+	(((x) >> BIT_SHIFT_EFUSE_BURN_GNT) & BIT_MASK_EFUSE_BURN_GNT)
+#define BIT_SET_EFUSE_BURN_GNT(x, v)                                           \
+	(BIT_CLEAR_EFUSE_BURN_GNT(x) | BIT_EFUSE_BURN_GNT(v))
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_PMC_DBG_CTRL2			(Offset 0x00CC) */
+
+#define BIT_SHIFT_EFUSE_PG_PWD 24
+#define BIT_MASK_EFUSE_PG_PWD 0xff
+#define BIT_EFUSE_PG_PWD(x)                                                    \
+	(((x) & BIT_MASK_EFUSE_PG_PWD) << BIT_SHIFT_EFUSE_PG_PWD)
+#define BITS_EFUSE_PG_PWD (BIT_MASK_EFUSE_PG_PWD << BIT_SHIFT_EFUSE_PG_PWD)
+#define BIT_CLEAR_EFUSE_PG_PWD(x) ((x) & (~BITS_EFUSE_PG_PWD))
+#define BIT_GET_EFUSE_PG_PWD(x)                                                \
+	(((x) >> BIT_SHIFT_EFUSE_PG_PWD) & BIT_MASK_EFUSE_PG_PWD)
+#define BIT_SET_EFUSE_PG_PWD(x, v)                                             \
+	(BIT_CLEAR_EFUSE_PG_PWD(x) | BIT_EFUSE_PG_PWD(v))
+
+#define BIT_DBG_READ_EN BIT(16)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8881A_SUPPORT)
+
+/* 2 REG_PMC_DBG_CTRL2			(Offset 0x00CC) */
+
+#define BIT_STOP_WL_PMC BIT(9)
+#define BIT_STOP_SYM_PMC BIT(8)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_PMC_DBG_CTRL2			(Offset 0x00CC) */
+
+#define BIT_SHIFT_EDATA1_V1 8
+#define BIT_MASK_EDATA1_V1 0xff
+#define BIT_EDATA1_V1(x) (((x) & BIT_MASK_EDATA1_V1) << BIT_SHIFT_EDATA1_V1)
+#define BITS_EDATA1_V1 (BIT_MASK_EDATA1_V1 << BIT_SHIFT_EDATA1_V1)
+#define BIT_CLEAR_EDATA1_V1(x) ((x) & (~BITS_EDATA1_V1))
+#define BIT_GET_EDATA1_V1(x) (((x) >> BIT_SHIFT_EDATA1_V1) & BIT_MASK_EDATA1_V1)
+#define BIT_SET_EDATA1_V1(x, v) (BIT_CLEAR_EDATA1_V1(x) | BIT_EDATA1_V1(v))
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_PMC_DBG_CTRL2			(Offset 0x00CC) */
+
+#define BIT_BT_ACCESS_WL_PAGE0 BIT(6)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8881A_SUPPORT)
+
+/* 2 REG_PMC_DBG_CTRL2			(Offset 0x00CC) */
+
+#define BIT_REG_RST_WLPMC BIT(5)
+#define BIT_REG_RST_PD12N BIT(4)
+#define BIT_SYSON_DIS_WLREG_WRMSK BIT(3)
+#define BIT_SYSON_DIS_PMCREG_WRMSK BIT(2)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_SDIO_TRANS_FIFO_STATUS		(Offset 0x102500CC) */
+
+#define BIT_TRANS_FIFO_UNDERFLOW BIT(1)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8881A_SUPPORT)
+
+/* 2 REG_PMC_DBG_CTRL2			(Offset 0x00CC) */
+
+#define BIT_SHIFT_SYSON_REG_ARB 0
+#define BIT_MASK_SYSON_REG_ARB 0x3
+#define BIT_SYSON_REG_ARB(x)                                                   \
+	(((x) & BIT_MASK_SYSON_REG_ARB) << BIT_SHIFT_SYSON_REG_ARB)
+#define BITS_SYSON_REG_ARB (BIT_MASK_SYSON_REG_ARB << BIT_SHIFT_SYSON_REG_ARB)
+#define BIT_CLEAR_SYSON_REG_ARB(x) ((x) & (~BITS_SYSON_REG_ARB))
+#define BIT_GET_SYSON_REG_ARB(x)                                               \
+	(((x) >> BIT_SHIFT_SYSON_REG_ARB) & BIT_MASK_SYSON_REG_ARB)
+#define BIT_SET_SYSON_REG_ARB(x, v)                                            \
+	(BIT_CLEAR_SYSON_REG_ARB(x) | BIT_SYSON_REG_ARB(v))
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_SDIO_TRANS_FIFO_STATUS		(Offset 0x102500CC) */
+
+#define BIT_TRANS_FIFO_OVERFLOW BIT(0)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_PMC_DBG_CTRL2			(Offset 0x00CC) */
+
+#define BIT_SHIFT_EDATA0_V1 0
+#define BIT_MASK_EDATA0_V1 0xff
+#define BIT_EDATA0_V1(x) (((x) & BIT_MASK_EDATA0_V1) << BIT_SHIFT_EDATA0_V1)
+#define BITS_EDATA0_V1 (BIT_MASK_EDATA0_V1 << BIT_SHIFT_EDATA0_V1)
+#define BIT_CLEAR_EDATA0_V1(x) ((x) & (~BITS_EDATA0_V1))
+#define BIT_GET_EDATA0_V1(x) (((x) >> BIT_SHIFT_EDATA0_V1) & BIT_MASK_EDATA0_V1)
+#define BIT_SET_EDATA0_V1(x, v) (BIT_CLEAR_EDATA0_V1(x) | BIT_EDATA0_V1(v))
+
+/* 2 REG_BIST_CTRL				(Offset 0x00D0) */
+
+#define BIT_SCAN_PLL_BYPASS BIT(30)
+#define BIT_DRF_BIST_FAIL_V1 BIT(28)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_BIST_CTRL				(Offset 0x00D0) */
+
+#define BIT_BIST_USB_DIS BIT(27)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_BIST_CTRL				(Offset 0x00D0) */
+
+#define BIT_DRF_BIST_READY_V1 BIT(27)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_BIST_CTRL				(Offset 0x00D0) */
+
+#define BIT_BIST_PCI_DIS BIT(26)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_BIST_CTRL				(Offset 0x00D0) */
+
+#define BIT_BIST_FAIL_V1 BIT(26)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_BIST_CTRL				(Offset 0x00D0) */
+
+#define BIT_BIST_BT_DIS BIT(25)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_BIST_CTRL				(Offset 0x00D0) */
+
+#define BIT_BIST_READY_V1 BIT(25)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_BIST_CTRL				(Offset 0x00D0) */
+
+#define BIT_BIST_WL_DIS BIT(24)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_BIST_CTRL				(Offset 0x00D0) */
+
+#define BIT_BIST_START_PAUSE_V1 BIT(24)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_BIST_CTRL				(Offset 0x00D0) */
+
+#define BIT_SHIFT_BIST_RPT_SEL_V1 20
+#define BIT_MASK_BIST_RPT_SEL_V1 0xf
+#define BIT_BIST_RPT_SEL_V1(x)                                                 \
+	(((x) & BIT_MASK_BIST_RPT_SEL_V1) << BIT_SHIFT_BIST_RPT_SEL_V1)
+#define BITS_BIST_RPT_SEL_V1                                                   \
+	(BIT_MASK_BIST_RPT_SEL_V1 << BIT_SHIFT_BIST_RPT_SEL_V1)
+#define BIT_CLEAR_BIST_RPT_SEL_V1(x) ((x) & (~BITS_BIST_RPT_SEL_V1))
+#define BIT_GET_BIST_RPT_SEL_V1(x)                                             \
+	(((x) >> BIT_SHIFT_BIST_RPT_SEL_V1) & BIT_MASK_BIST_RPT_SEL_V1)
+#define BIT_SET_BIST_RPT_SEL_V1(x, v)                                          \
+	(BIT_CLEAR_BIST_RPT_SEL_V1(x) | BIT_BIST_RPT_SEL_V1(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_BIST_CTRL				(Offset 0x00D0) */
+
+#define BIT_SHIFT_BIST_RPT_SEL 16
+#define BIT_MASK_BIST_RPT_SEL 0xf
+#define BIT_BIST_RPT_SEL(x)                                                    \
+	(((x) & BIT_MASK_BIST_RPT_SEL) << BIT_SHIFT_BIST_RPT_SEL)
+#define BITS_BIST_RPT_SEL (BIT_MASK_BIST_RPT_SEL << BIT_SHIFT_BIST_RPT_SEL)
+#define BIT_CLEAR_BIST_RPT_SEL(x) ((x) & (~BITS_BIST_RPT_SEL))
+#define BIT_GET_BIST_RPT_SEL(x)                                                \
+	(((x) >> BIT_SHIFT_BIST_RPT_SEL) & BIT_MASK_BIST_RPT_SEL)
+#define BIT_SET_BIST_RPT_SEL(x, v)                                             \
+	(BIT_CLEAR_BIST_RPT_SEL(x) | BIT_BIST_RPT_SEL(v))
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_BIST_CTRL				(Offset 0x00D0) */
+
+#define BIT_SHIFT_MBIST_RSTNI 8
+#define BIT_MASK_MBIST_RSTNI 0x3ff
+#define BIT_MBIST_RSTNI(x)                                                     \
+	(((x) & BIT_MASK_MBIST_RSTNI) << BIT_SHIFT_MBIST_RSTNI)
+#define BITS_MBIST_RSTNI (BIT_MASK_MBIST_RSTNI << BIT_SHIFT_MBIST_RSTNI)
+#define BIT_CLEAR_MBIST_RSTNI(x) ((x) & (~BITS_MBIST_RSTNI))
+#define BIT_GET_MBIST_RSTNI(x)                                                 \
+	(((x) >> BIT_SHIFT_MBIST_RSTNI) & BIT_MASK_MBIST_RSTNI)
+#define BIT_SET_MBIST_RSTNI(x, v)                                              \
+	(BIT_CLEAR_MBIST_RSTNI(x) | BIT_MBIST_RSTNI(v))
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_BIST_CTRL				(Offset 0x00D0) */
+
+#define BIT_BISD_MODE BIT(6)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_BIST_CTRL				(Offset 0x00D0) */
+
+#define BIT_BIST_RESUME_PS_V1 BIT(5)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_BIST_CTRL				(Offset 0x00D0) */
+
+#define BIT_BIST_RESUME_PS BIT(4)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_BIST_CTRL				(Offset 0x00D0) */
+
+#define BIT_BIST_RESUME_V1 BIT(4)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_BIST_CTRL				(Offset 0x00D0) */
+
+#define BIT_BIST_RESUME BIT(3)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_BIST_CTRL				(Offset 0x00D0) */
+
+#define BIT_BIST_DRF BIT(3)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_BIST_CTRL				(Offset 0x00D0) */
+
+#define BIT_BIST_NORMAL BIT(2)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_BIST_CTRL				(Offset 0x00D0) */
+
+#define BIT_SHIFT_BIST_MODE 2
+#define BIT_MASK_BIST_MODE 0x3
+#define BIT_BIST_MODE(x) (((x) & BIT_MASK_BIST_MODE) << BIT_SHIFT_BIST_MODE)
+#define BITS_BIST_MODE (BIT_MASK_BIST_MODE << BIT_SHIFT_BIST_MODE)
+#define BIT_CLEAR_BIST_MODE(x) ((x) & (~BITS_BIST_MODE))
+#define BIT_GET_BIST_MODE(x) (((x) >> BIT_SHIFT_BIST_MODE) & BIT_MASK_BIST_MODE)
+#define BIT_SET_BIST_MODE(x, v) (BIT_CLEAR_BIST_MODE(x) | BIT_BIST_MODE(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_BIST_CTRL				(Offset 0x00D0) */
+
+#define BIT_BIST_RSTN BIT(1)
+#define BIT_BIST_CLK_EN BIT(0)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_BIST_RPT				(Offset 0x00D4) */
+
+#define BIT_SHIFT_MBIST_REPORT 0
+#define BIT_MASK_MBIST_REPORT 0xffffffffL
+#define BIT_MBIST_REPORT(x)                                                    \
+	(((x) & BIT_MASK_MBIST_REPORT) << BIT_SHIFT_MBIST_REPORT)
+#define BITS_MBIST_REPORT (BIT_MASK_MBIST_REPORT << BIT_SHIFT_MBIST_REPORT)
+#define BIT_CLEAR_MBIST_REPORT(x) ((x) & (~BITS_MBIST_REPORT))
+#define BIT_GET_MBIST_REPORT(x)                                                \
+	(((x) >> BIT_SHIFT_MBIST_REPORT) & BIT_MASK_MBIST_REPORT)
+#define BIT_SET_MBIST_REPORT(x, v)                                             \
+	(BIT_CLEAR_MBIST_REPORT(x) | BIT_MBIST_REPORT(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT)
+
+/* 2 REG_MEM_CTRL				(Offset 0x00D8) */
+
+#define BIT_RMV_SIGN BIT(31)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_MEM_CTRL				(Offset 0x00D8) */
+
+#define BIT_UMEM_RME BIT(31)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT)
+
+/* 2 REG_MEM_CTRL				(Offset 0x00D8) */
+
+#define BIT_RMV_2PRF1 BIT(29)
+#define BIT_RMV_2PRF0 BIT(28)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_MEM_CTRL				(Offset 0x00D8) */
+
+#define BIT_SHIFT_BT_SPRAM 28
+#define BIT_MASK_BT_SPRAM 0x3
+#define BIT_BT_SPRAM(x) (((x) & BIT_MASK_BT_SPRAM) << BIT_SHIFT_BT_SPRAM)
+#define BITS_BT_SPRAM (BIT_MASK_BT_SPRAM << BIT_SHIFT_BT_SPRAM)
+#define BIT_CLEAR_BT_SPRAM(x) ((x) & (~BITS_BT_SPRAM))
+#define BIT_GET_BT_SPRAM(x) (((x) >> BIT_SHIFT_BT_SPRAM) & BIT_MASK_BT_SPRAM)
+#define BIT_SET_BT_SPRAM(x, v) (BIT_CLEAR_BT_SPRAM(x) | BIT_BT_SPRAM(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT)
+
+/* 2 REG_MEM_CTRL				(Offset 0x00D8) */
+
+#define BIT_RMV_1PRF1 BIT(27)
+#define BIT_RMV_1PRF0 BIT(26)
+#define BIT_RMV_1PSR BIT(25)
+#define BIT_RMV_ROM BIT(24)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_MEM_CTRL				(Offset 0x00D8) */
+
+#define BIT_SHIFT_BT_ROM 24
+#define BIT_MASK_BT_ROM 0xf
+#define BIT_BT_ROM(x) (((x) & BIT_MASK_BT_ROM) << BIT_SHIFT_BT_ROM)
+#define BITS_BT_ROM (BIT_MASK_BT_ROM << BIT_SHIFT_BT_ROM)
+#define BIT_CLEAR_BT_ROM(x) ((x) & (~BITS_BT_ROM))
+#define BIT_GET_BT_ROM(x) (((x) >> BIT_SHIFT_BT_ROM) & BIT_MASK_BT_ROM)
+#define BIT_SET_BT_ROM(x, v) (BIT_CLEAR_BT_ROM(x) | BIT_BT_ROM(v))
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_MEM_CTRL				(Offset 0x00D8) */
+
+#define BIT_MEM_RMV1_2PRF1 BIT(19)
+#define BIT_MEM_RMV1_2PRF0 BIT(18)
+#define BIT_MEM_RMV1_1PRF1 BIT(17)
+#define BIT_MEM_RMV1_1PRF0 BIT(16)
+#define BIT_MEM_RMV1_1PSR BIT(15)
+#define BIT_MEM_RMV1_ROM BIT(14)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_MEM_CTRL				(Offset 0x00D8) */
+
+#define BIT_SHIFT_PCI_DPRAM 10
+#define BIT_MASK_PCI_DPRAM 0x3
+#define BIT_PCI_DPRAM(x) (((x) & BIT_MASK_PCI_DPRAM) << BIT_SHIFT_PCI_DPRAM)
+#define BITS_PCI_DPRAM (BIT_MASK_PCI_DPRAM << BIT_SHIFT_PCI_DPRAM)
+#define BIT_CLEAR_PCI_DPRAM(x) ((x) & (~BITS_PCI_DPRAM))
+#define BIT_GET_PCI_DPRAM(x) (((x) >> BIT_SHIFT_PCI_DPRAM) & BIT_MASK_PCI_DPRAM)
+#define BIT_SET_PCI_DPRAM(x, v) (BIT_CLEAR_PCI_DPRAM(x) | BIT_PCI_DPRAM(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT)
+
+/* 2 REG_MEM_CTRL				(Offset 0x00D8) */
+
+#define BIT_SHIFT_MEM_RME_BT 8
+#define BIT_MASK_MEM_RME_BT 0xf
+#define BIT_MEM_RME_BT(x) (((x) & BIT_MASK_MEM_RME_BT) << BIT_SHIFT_MEM_RME_BT)
+#define BITS_MEM_RME_BT (BIT_MASK_MEM_RME_BT << BIT_SHIFT_MEM_RME_BT)
+#define BIT_CLEAR_MEM_RME_BT(x) ((x) & (~BITS_MEM_RME_BT))
+#define BIT_GET_MEM_RME_BT(x)                                                  \
+	(((x) >> BIT_SHIFT_MEM_RME_BT) & BIT_MASK_MEM_RME_BT)
+#define BIT_SET_MEM_RME_BT(x, v) (BIT_CLEAR_MEM_RME_BT(x) | BIT_MEM_RME_BT(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_MEM_CTRL				(Offset 0x00D8) */
+
+#define BIT_SHIFT_PCI_SPRAM 8
+#define BIT_MASK_PCI_SPRAM 0x3
+#define BIT_PCI_SPRAM(x) (((x) & BIT_MASK_PCI_SPRAM) << BIT_SHIFT_PCI_SPRAM)
+#define BITS_PCI_SPRAM (BIT_MASK_PCI_SPRAM << BIT_SHIFT_PCI_SPRAM)
+#define BIT_CLEAR_PCI_SPRAM(x) ((x) & (~BITS_PCI_SPRAM))
+#define BIT_GET_PCI_SPRAM(x) (((x) >> BIT_SHIFT_PCI_SPRAM) & BIT_MASK_PCI_SPRAM)
+#define BIT_SET_PCI_SPRAM(x, v) (BIT_CLEAR_PCI_SPRAM(x) | BIT_PCI_SPRAM(v))
+
+#define BIT_SHIFT_USB_SPRAM 6
+#define BIT_MASK_USB_SPRAM 0x3
+#define BIT_USB_SPRAM(x) (((x) & BIT_MASK_USB_SPRAM) << BIT_SHIFT_USB_SPRAM)
+#define BITS_USB_SPRAM (BIT_MASK_USB_SPRAM << BIT_SHIFT_USB_SPRAM)
+#define BIT_CLEAR_USB_SPRAM(x) ((x) & (~BITS_USB_SPRAM))
+#define BIT_GET_USB_SPRAM(x) (((x) >> BIT_SHIFT_USB_SPRAM) & BIT_MASK_USB_SPRAM)
+#define BIT_SET_USB_SPRAM(x, v) (BIT_CLEAR_USB_SPRAM(x) | BIT_USB_SPRAM(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT)
+
+/* 2 REG_MEM_CTRL				(Offset 0x00D8) */
+
+#define BIT_SHIFT_MEM_RME_WL 4
+#define BIT_MASK_MEM_RME_WL 0xf
+#define BIT_MEM_RME_WL(x) (((x) & BIT_MASK_MEM_RME_WL) << BIT_SHIFT_MEM_RME_WL)
+#define BITS_MEM_RME_WL (BIT_MASK_MEM_RME_WL << BIT_SHIFT_MEM_RME_WL)
+#define BIT_CLEAR_MEM_RME_WL(x) ((x) & (~BITS_MEM_RME_WL))
+#define BIT_GET_MEM_RME_WL(x)                                                  \
+	(((x) >> BIT_SHIFT_MEM_RME_WL) & BIT_MASK_MEM_RME_WL)
+#define BIT_SET_MEM_RME_WL(x, v) (BIT_CLEAR_MEM_RME_WL(x) | BIT_MEM_RME_WL(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_MEM_CTRL				(Offset 0x00D8) */
+
+#define BIT_SHIFT_USB_SPRF 4
+#define BIT_MASK_USB_SPRF 0x3
+#define BIT_USB_SPRF(x) (((x) & BIT_MASK_USB_SPRF) << BIT_SHIFT_USB_SPRF)
+#define BITS_USB_SPRF (BIT_MASK_USB_SPRF << BIT_SHIFT_USB_SPRF)
+#define BIT_CLEAR_USB_SPRF(x) ((x) & (~BITS_USB_SPRF))
+#define BIT_GET_USB_SPRF(x) (((x) >> BIT_SHIFT_USB_SPRF) & BIT_MASK_USB_SPRF)
+#define BIT_SET_USB_SPRF(x, v) (BIT_CLEAR_USB_SPRF(x) | BIT_USB_SPRF(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT)
+
+/* 2 REG_MEM_CTRL				(Offset 0x00D8) */
+
+#define BIT_SHIFT_MEM_RME_HCI 0
+#define BIT_MASK_MEM_RME_HCI 0xf
+#define BIT_MEM_RME_HCI(x)                                                     \
+	(((x) & BIT_MASK_MEM_RME_HCI) << BIT_SHIFT_MEM_RME_HCI)
+#define BITS_MEM_RME_HCI (BIT_MASK_MEM_RME_HCI << BIT_SHIFT_MEM_RME_HCI)
+#define BIT_CLEAR_MEM_RME_HCI(x) ((x) & (~BITS_MEM_RME_HCI))
+#define BIT_GET_MEM_RME_HCI(x)                                                 \
+	(((x) >> BIT_SHIFT_MEM_RME_HCI) & BIT_MASK_MEM_RME_HCI)
+#define BIT_SET_MEM_RME_HCI(x, v)                                              \
+	(BIT_CLEAR_MEM_RME_HCI(x) | BIT_MEM_RME_HCI(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_MEM_CTRL				(Offset 0x00D8) */
+
+#define BIT_SHIFT_MCU_ROM 0
+#define BIT_MASK_MCU_ROM 0xf
+#define BIT_MCU_ROM(x) (((x) & BIT_MASK_MCU_ROM) << BIT_SHIFT_MCU_ROM)
+#define BITS_MCU_ROM (BIT_MASK_MCU_ROM << BIT_SHIFT_MCU_ROM)
+#define BIT_CLEAR_MCU_ROM(x) ((x) & (~BITS_MCU_ROM))
+#define BIT_GET_MCU_ROM(x) (((x) >> BIT_SHIFT_MCU_ROM) & BIT_MASK_MCU_ROM)
+#define BIT_SET_MCU_ROM(x, v) (BIT_CLEAR_MCU_ROM(x) | BIT_MCU_ROM(v))
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_MEM_CTRL				(Offset 0x00D8) */
+
+#define BIT_SHIFT_BIST_ROM 0
+#define BIT_MASK_BIST_ROM 0xffffffffL
+#define BIT_BIST_ROM(x) (((x) & BIT_MASK_BIST_ROM) << BIT_SHIFT_BIST_ROM)
+#define BITS_BIST_ROM (BIT_MASK_BIST_ROM << BIT_SHIFT_BIST_ROM)
+#define BIT_CLEAR_BIST_ROM(x) ((x) & (~BITS_BIST_ROM))
+#define BIT_GET_BIST_ROM(x) (((x) >> BIT_SHIFT_BIST_ROM) & BIT_MASK_BIST_ROM)
+#define BIT_SET_BIST_ROM(x, v) (BIT_CLEAR_BIST_ROM(x) | BIT_BIST_ROM(v))
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_AFE_CTRL8				(Offset 0x00DC) */
+
+#define BIT_SHIFT_BB_DBG_SEL_AFE_SDM_V4 26
+#define BIT_MASK_BB_DBG_SEL_AFE_SDM_V4 0x7
+#define BIT_BB_DBG_SEL_AFE_SDM_V4(x)                                           \
+	(((x) & BIT_MASK_BB_DBG_SEL_AFE_SDM_V4)                                \
+	 << BIT_SHIFT_BB_DBG_SEL_AFE_SDM_V4)
+#define BITS_BB_DBG_SEL_AFE_SDM_V4                                             \
+	(BIT_MASK_BB_DBG_SEL_AFE_SDM_V4 << BIT_SHIFT_BB_DBG_SEL_AFE_SDM_V4)
+#define BIT_CLEAR_BB_DBG_SEL_AFE_SDM_V4(x) ((x) & (~BITS_BB_DBG_SEL_AFE_SDM_V4))
+#define BIT_GET_BB_DBG_SEL_AFE_SDM_V4(x)                                       \
+	(((x) >> BIT_SHIFT_BB_DBG_SEL_AFE_SDM_V4) &                            \
+	 BIT_MASK_BB_DBG_SEL_AFE_SDM_V4)
+#define BIT_SET_BB_DBG_SEL_AFE_SDM_V4(x, v)                                    \
+	(BIT_CLEAR_BB_DBG_SEL_AFE_SDM_V4(x) | BIT_BB_DBG_SEL_AFE_SDM_V4(v))
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+
+/* 2 REG_AFE_CTRL8				(Offset 0x00DC) */
+
+#define BIT_SYN_AGPIO BIT(20)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_SYN_RFC_CTRL			(Offset 0x00DC) */
+
+#define BIT_SHIFT_SYN_RF1_CTRL 8
+#define BIT_MASK_SYN_RF1_CTRL 0xff
+#define BIT_SYN_RF1_CTRL(x)                                                    \
+	(((x) & BIT_MASK_SYN_RF1_CTRL) << BIT_SHIFT_SYN_RF1_CTRL)
+#define BITS_SYN_RF1_CTRL (BIT_MASK_SYN_RF1_CTRL << BIT_SHIFT_SYN_RF1_CTRL)
+#define BIT_CLEAR_SYN_RF1_CTRL(x) ((x) & (~BITS_SYN_RF1_CTRL))
+#define BIT_GET_SYN_RF1_CTRL(x)                                                \
+	(((x) >> BIT_SHIFT_SYN_RF1_CTRL) & BIT_MASK_SYN_RF1_CTRL)
+#define BIT_SET_SYN_RF1_CTRL(x, v)                                             \
+	(BIT_CLEAR_SYN_RF1_CTRL(x) | BIT_SYN_RF1_CTRL(v))
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_AFE_CTRL8				(Offset 0x00DC) */
+
+#define BIT_SHIFT_XTAL_GM_REP 6
+#define BIT_MASK_XTAL_GM_REP 0x3
+#define BIT_XTAL_GM_REP(x)                                                     \
+	(((x) & BIT_MASK_XTAL_GM_REP) << BIT_SHIFT_XTAL_GM_REP)
+#define BITS_XTAL_GM_REP (BIT_MASK_XTAL_GM_REP << BIT_SHIFT_XTAL_GM_REP)
+#define BIT_CLEAR_XTAL_GM_REP(x) ((x) & (~BITS_XTAL_GM_REP))
+#define BIT_GET_XTAL_GM_REP(x)                                                 \
+	(((x) >> BIT_SHIFT_XTAL_GM_REP) & BIT_MASK_XTAL_GM_REP)
+#define BIT_SET_XTAL_GM_REP(x, v)                                              \
+	(BIT_CLEAR_XTAL_GM_REP(x) | BIT_XTAL_GM_REP(v))
+
+#define BIT_XTAL_DRV_RF_LATCH_V5 BIT(5)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+
+/* 2 REG_AFE_CTRL8				(Offset 0x00DC) */
+
+#define BIT_XTAL_LP BIT(4)
+#define BIT_XTAL_GM_SEP BIT(3)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_AFE_CTRL8				(Offset 0x00DC) */
+
+#define BIT_SHIFT_XTAL_SEL_TOK_V2 0
+#define BIT_MASK_XTAL_SEL_TOK_V2 0x7
+#define BIT_XTAL_SEL_TOK_V2(x)                                                 \
+	(((x) & BIT_MASK_XTAL_SEL_TOK_V2) << BIT_SHIFT_XTAL_SEL_TOK_V2)
+#define BITS_XTAL_SEL_TOK_V2                                                   \
+	(BIT_MASK_XTAL_SEL_TOK_V2 << BIT_SHIFT_XTAL_SEL_TOK_V2)
+#define BIT_CLEAR_XTAL_SEL_TOK_V2(x) ((x) & (~BITS_XTAL_SEL_TOK_V2))
+#define BIT_GET_XTAL_SEL_TOK_V2(x)                                             \
+	(((x) >> BIT_SHIFT_XTAL_SEL_TOK_V2) & BIT_MASK_XTAL_SEL_TOK_V2)
+#define BIT_SET_XTAL_SEL_TOK_V2(x, v)                                          \
+	(BIT_CLEAR_XTAL_SEL_TOK_V2(x) | BIT_XTAL_SEL_TOK_V2(v))
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_WLAN_DBG				(Offset 0x00DC) */
+
+#define BIT_SHIFT_WLAN_DBG 0
+#define BIT_MASK_WLAN_DBG 0xffffffffL
+#define BIT_WLAN_DBG(x) (((x) & BIT_MASK_WLAN_DBG) << BIT_SHIFT_WLAN_DBG)
+#define BITS_WLAN_DBG (BIT_MASK_WLAN_DBG << BIT_SHIFT_WLAN_DBG)
+#define BIT_CLEAR_WLAN_DBG(x) ((x) & (~BITS_WLAN_DBG))
+#define BIT_GET_WLAN_DBG(x) (((x) >> BIT_SHIFT_WLAN_DBG) & BIT_MASK_WLAN_DBG)
+#define BIT_SET_WLAN_DBG(x, v) (BIT_CLEAR_WLAN_DBG(x) | BIT_WLAN_DBG(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_SYN_RFC_CTRL			(Offset 0x00DC) */
+
+#define BIT_SHIFT_SYN_RF0_CTRL 0
+#define BIT_MASK_SYN_RF0_CTRL 0xff
+#define BIT_SYN_RF0_CTRL(x)                                                    \
+	(((x) & BIT_MASK_SYN_RF0_CTRL) << BIT_SHIFT_SYN_RF0_CTRL)
+#define BITS_SYN_RF0_CTRL (BIT_MASK_SYN_RF0_CTRL << BIT_SHIFT_SYN_RF0_CTRL)
+#define BIT_CLEAR_SYN_RF0_CTRL(x) ((x) & (~BITS_SYN_RF0_CTRL))
+#define BIT_GET_SYN_RF0_CTRL(x)                                                \
+	(((x) >> BIT_SHIFT_SYN_RF0_CTRL) & BIT_MASK_SYN_RF0_CTRL)
+#define BIT_SET_SYN_RF0_CTRL(x, v)                                             \
+	(BIT_CLEAR_SYN_RF0_CTRL(x) | BIT_SYN_RF0_CTRL(v))
+
+#endif
+
+#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+
+/* 2 REG_AFE_CTRL8				(Offset 0x00DC) */
+
+#define BIT_SHIFT_XTAL_SEL_TOK 0
+#define BIT_MASK_XTAL_SEL_TOK 0x7
+#define BIT_XTAL_SEL_TOK(x)                                                    \
+	(((x) & BIT_MASK_XTAL_SEL_TOK) << BIT_SHIFT_XTAL_SEL_TOK)
+#define BITS_XTAL_SEL_TOK (BIT_MASK_XTAL_SEL_TOK << BIT_SHIFT_XTAL_SEL_TOK)
+#define BIT_CLEAR_XTAL_SEL_TOK(x) ((x) & (~BITS_XTAL_SEL_TOK))
+#define BIT_GET_XTAL_SEL_TOK(x)                                                \
+	(((x) >> BIT_SHIFT_XTAL_SEL_TOK) & BIT_MASK_XTAL_SEL_TOK)
+#define BIT_SET_XTAL_SEL_TOK(x, v)                                             \
+	(BIT_CLEAR_XTAL_SEL_TOK(x) | BIT_XTAL_SEL_TOK(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_USB_SIE_INTF			(Offset 0x00E0) */
+
+#define BIT_RD_SEL BIT(31)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_USB_SIE_INTF			(Offset 0x00E0) */
+
+#define BIT_CPU_REG_SEL BIT(31)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_USB_SIE_INTF			(Offset 0x00E0) */
+
+#define BIT_USB_SIE_INTF_WE_V1 BIT(30)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_USB_SIE_INTF			(Offset 0x00E0) */
+
+#define BIT_USB3_REG_SEL BIT(30)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_USB_SIE_INTF			(Offset 0x00E0) */
+
+#define BIT_USB_SIE_INTF_BYIOREG_V1 BIT(29)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_USB_SIE_INTF			(Offset 0x00E0) */
+
+#define BIT_SHIFT_USB_SIE_EN 28
+#define BIT_MASK_USB_SIE_EN 0x3
+#define BIT_USB_SIE_EN(x) (((x) & BIT_MASK_USB_SIE_EN) << BIT_SHIFT_USB_SIE_EN)
+#define BITS_USB_SIE_EN (BIT_MASK_USB_SIE_EN << BIT_SHIFT_USB_SIE_EN)
+#define BIT_CLEAR_USB_SIE_EN(x) ((x) & (~BITS_USB_SIE_EN))
+#define BIT_GET_USB_SIE_EN(x)                                                  \
+	(((x) >> BIT_SHIFT_USB_SIE_EN) & BIT_MASK_USB_SIE_EN)
+#define BIT_SET_USB_SIE_EN(x, v) (BIT_CLEAR_USB_SIE_EN(x) | BIT_USB_SIE_EN(v))
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_USB_SIE_INTF			(Offset 0x00E0) */
+
+#define BIT_USB_SIE_SELECT BIT(28)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8881A_SUPPORT)
+
+/* 2 REG_USB_SIE_INTF			(Offset 0x00E0) */
+
+#define BIT_USB_SIE_INTF_WE BIT(25)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_USB_SIE_INTF			(Offset 0x00E0) */
+
+#define BIT_USB_SIE_INTF_BYIOREG BIT(24)
+
+#define BIT_SHIFT_USB_SIE_INTF_ADDR 16
+#define BIT_MASK_USB_SIE_INTF_ADDR 0xff
+#define BIT_USB_SIE_INTF_ADDR(x)                                               \
+	(((x) & BIT_MASK_USB_SIE_INTF_ADDR) << BIT_SHIFT_USB_SIE_INTF_ADDR)
+#define BITS_USB_SIE_INTF_ADDR                                                 \
+	(BIT_MASK_USB_SIE_INTF_ADDR << BIT_SHIFT_USB_SIE_INTF_ADDR)
+#define BIT_CLEAR_USB_SIE_INTF_ADDR(x) ((x) & (~BITS_USB_SIE_INTF_ADDR))
+#define BIT_GET_USB_SIE_INTF_ADDR(x)                                           \
+	(((x) >> BIT_SHIFT_USB_SIE_INTF_ADDR) & BIT_MASK_USB_SIE_INTF_ADDR)
+#define BIT_SET_USB_SIE_INTF_ADDR(x, v)                                        \
+	(BIT_CLEAR_USB_SIE_INTF_ADDR(x) | BIT_USB_SIE_INTF_ADDR(v))
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_USB_SIE_INTF			(Offset 0x00E0) */
+
+#define BIT_SHIFT_USB_SIE_INTF_ADDR_V1 16
+#define BIT_MASK_USB_SIE_INTF_ADDR_V1 0x1ff
+#define BIT_USB_SIE_INTF_ADDR_V1(x)                                            \
+	(((x) & BIT_MASK_USB_SIE_INTF_ADDR_V1)                                 \
+	 << BIT_SHIFT_USB_SIE_INTF_ADDR_V1)
+#define BITS_USB_SIE_INTF_ADDR_V1                                              \
+	(BIT_MASK_USB_SIE_INTF_ADDR_V1 << BIT_SHIFT_USB_SIE_INTF_ADDR_V1)
+#define BIT_CLEAR_USB_SIE_INTF_ADDR_V1(x) ((x) & (~BITS_USB_SIE_INTF_ADDR_V1))
+#define BIT_GET_USB_SIE_INTF_ADDR_V1(x)                                        \
+	(((x) >> BIT_SHIFT_USB_SIE_INTF_ADDR_V1) &                             \
+	 BIT_MASK_USB_SIE_INTF_ADDR_V1)
+#define BIT_SET_USB_SIE_INTF_ADDR_V1(x, v)                                     \
+	(BIT_CLEAR_USB_SIE_INTF_ADDR_V1(x) | BIT_USB_SIE_INTF_ADDR_V1(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8881A_SUPPORT)
+
+/* 2 REG_USB_SIE_INTF			(Offset 0x00E0) */
+
+#define BIT_SHIFT_USB_SIE_INTF_RD 8
+#define BIT_MASK_USB_SIE_INTF_RD 0xff
+#define BIT_USB_SIE_INTF_RD(x)                                                 \
+	(((x) & BIT_MASK_USB_SIE_INTF_RD) << BIT_SHIFT_USB_SIE_INTF_RD)
+#define BITS_USB_SIE_INTF_RD                                                   \
+	(BIT_MASK_USB_SIE_INTF_RD << BIT_SHIFT_USB_SIE_INTF_RD)
+#define BIT_CLEAR_USB_SIE_INTF_RD(x) ((x) & (~BITS_USB_SIE_INTF_RD))
+#define BIT_GET_USB_SIE_INTF_RD(x)                                             \
+	(((x) >> BIT_SHIFT_USB_SIE_INTF_RD) & BIT_MASK_USB_SIE_INTF_RD)
+#define BIT_SET_USB_SIE_INTF_RD(x, v)                                          \
+	(BIT_CLEAR_USB_SIE_INTF_RD(x) | BIT_USB_SIE_INTF_RD(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_USB_SIE_INTF			(Offset 0x00E0) */
+
+#define BIT_SHIFT_NPQ_AVAL_PG 8
+#define BIT_MASK_NPQ_AVAL_PG 0xff
+#define BIT_NPQ_AVAL_PG(x)                                                     \
+	(((x) & BIT_MASK_NPQ_AVAL_PG) << BIT_SHIFT_NPQ_AVAL_PG)
+#define BITS_NPQ_AVAL_PG (BIT_MASK_NPQ_AVAL_PG << BIT_SHIFT_NPQ_AVAL_PG)
+#define BIT_CLEAR_NPQ_AVAL_PG(x) ((x) & (~BITS_NPQ_AVAL_PG))
+#define BIT_GET_NPQ_AVAL_PG(x)                                                 \
+	(((x) >> BIT_SHIFT_NPQ_AVAL_PG) & BIT_MASK_NPQ_AVAL_PG)
+#define BIT_SET_NPQ_AVAL_PG(x, v)                                              \
+	(BIT_CLEAR_NPQ_AVAL_PG(x) | BIT_NPQ_AVAL_PG(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8881A_SUPPORT)
+
+/* 2 REG_USB_SIE_INTF			(Offset 0x00E0) */
+
+#define BIT_SHIFT_USB_SIE_INTF_WD 0
+#define BIT_MASK_USB_SIE_INTF_WD 0xff
+#define BIT_USB_SIE_INTF_WD(x)                                                 \
+	(((x) & BIT_MASK_USB_SIE_INTF_WD) << BIT_SHIFT_USB_SIE_INTF_WD)
+#define BITS_USB_SIE_INTF_WD                                                   \
+	(BIT_MASK_USB_SIE_INTF_WD << BIT_SHIFT_USB_SIE_INTF_WD)
+#define BIT_CLEAR_USB_SIE_INTF_WD(x) ((x) & (~BITS_USB_SIE_INTF_WD))
+#define BIT_GET_USB_SIE_INTF_WD(x)                                             \
+	(((x) >> BIT_SHIFT_USB_SIE_INTF_WD) & BIT_MASK_USB_SIE_INTF_WD)
+#define BIT_SET_USB_SIE_INTF_WD(x, v)                                          \
+	(BIT_CLEAR_USB_SIE_INTF_WD(x) | BIT_USB_SIE_INTF_WD(v))
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_PCIE_MIO_INTF			(Offset 0x00E4) */
+
+#define BIT_PCIE_MIO_EXIT_L1 BIT(19)
+#define BIT_PCIE_MIO_EXT BIT(18)
+#define BIT_PCIE_MIO_ACK BIT(17)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_PCIE_MIO_INTF			(Offset 0x00E4) */
+
+#define BIT_PCIE_MIO_RIO BIT(16)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_PCIE_MIO_INTF			(Offset 0x00E4) */
+
+#define BIT_SHIFT_PCIE_MIO_ADDR_PAGE 16
+#define BIT_MASK_PCIE_MIO_ADDR_PAGE 0x3
+#define BIT_PCIE_MIO_ADDR_PAGE(x)                                              \
+	(((x) & BIT_MASK_PCIE_MIO_ADDR_PAGE) << BIT_SHIFT_PCIE_MIO_ADDR_PAGE)
+#define BITS_PCIE_MIO_ADDR_PAGE                                                \
+	(BIT_MASK_PCIE_MIO_ADDR_PAGE << BIT_SHIFT_PCIE_MIO_ADDR_PAGE)
+#define BIT_CLEAR_PCIE_MIO_ADDR_PAGE(x) ((x) & (~BITS_PCIE_MIO_ADDR_PAGE))
+#define BIT_GET_PCIE_MIO_ADDR_PAGE(x)                                          \
+	(((x) >> BIT_SHIFT_PCIE_MIO_ADDR_PAGE) & BIT_MASK_PCIE_MIO_ADDR_PAGE)
+#define BIT_SET_PCIE_MIO_ADDR_PAGE(x, v)                                       \
+	(BIT_CLEAR_PCIE_MIO_ADDR_PAGE(x) | BIT_PCIE_MIO_ADDR_PAGE(v))
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_PCIE_MIO_INTF			(Offset 0x00E4) */
+
+#define BIT_PCIE_MIO_IOREG BIT(16)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_PCIE_MIO_INTF			(Offset 0x00E4) */
+
+#define BIT_PCIE_MIO_BYIOREG BIT(13)
+#define BIT_PCIE_MIO_RE BIT(12)
+
+#define BIT_SHIFT_PCIE_MIO_WE 8
+#define BIT_MASK_PCIE_MIO_WE 0xf
+#define BIT_PCIE_MIO_WE(x)                                                     \
+	(((x) & BIT_MASK_PCIE_MIO_WE) << BIT_SHIFT_PCIE_MIO_WE)
+#define BITS_PCIE_MIO_WE (BIT_MASK_PCIE_MIO_WE << BIT_SHIFT_PCIE_MIO_WE)
+#define BIT_CLEAR_PCIE_MIO_WE(x) ((x) & (~BITS_PCIE_MIO_WE))
+#define BIT_GET_PCIE_MIO_WE(x)                                                 \
+	(((x) >> BIT_SHIFT_PCIE_MIO_WE) & BIT_MASK_PCIE_MIO_WE)
+#define BIT_SET_PCIE_MIO_WE(x, v)                                              \
+	(BIT_CLEAR_PCIE_MIO_WE(x) | BIT_PCIE_MIO_WE(v))
+
+#define BIT_SHIFT_PCIE_MIO_ADDR 0
+#define BIT_MASK_PCIE_MIO_ADDR 0xff
+#define BIT_PCIE_MIO_ADDR(x)                                                   \
+	(((x) & BIT_MASK_PCIE_MIO_ADDR) << BIT_SHIFT_PCIE_MIO_ADDR)
+#define BITS_PCIE_MIO_ADDR (BIT_MASK_PCIE_MIO_ADDR << BIT_SHIFT_PCIE_MIO_ADDR)
+#define BIT_CLEAR_PCIE_MIO_ADDR(x) ((x) & (~BITS_PCIE_MIO_ADDR))
+#define BIT_GET_PCIE_MIO_ADDR(x)                                               \
+	(((x) >> BIT_SHIFT_PCIE_MIO_ADDR) & BIT_MASK_PCIE_MIO_ADDR)
+#define BIT_SET_PCIE_MIO_ADDR(x, v)                                            \
+	(BIT_CLEAR_PCIE_MIO_ADDR(x) | BIT_PCIE_MIO_ADDR(v))
+
+/* 2 REG_PCIE_MIO_INTD			(Offset 0x00E8) */
+
+#define BIT_SHIFT_PCIE_MIO_DATA 0
+#define BIT_MASK_PCIE_MIO_DATA 0xffffffffL
+#define BIT_PCIE_MIO_DATA(x)                                                   \
+	(((x) & BIT_MASK_PCIE_MIO_DATA) << BIT_SHIFT_PCIE_MIO_DATA)
+#define BITS_PCIE_MIO_DATA (BIT_MASK_PCIE_MIO_DATA << BIT_SHIFT_PCIE_MIO_DATA)
+#define BIT_CLEAR_PCIE_MIO_DATA(x) ((x) & (~BITS_PCIE_MIO_DATA))
+#define BIT_GET_PCIE_MIO_DATA(x)                                               \
+	(((x) >> BIT_SHIFT_PCIE_MIO_DATA) & BIT_MASK_PCIE_MIO_DATA)
+#define BIT_SET_PCIE_MIO_DATA(x, v)                                            \
+	(BIT_CLEAR_PCIE_MIO_DATA(x) | BIT_PCIE_MIO_DATA(v))
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_HPON_FSM				(Offset 0x00EC) */
+
+#define BIT_SUSPEND_V1 BIT(31)
+#define BIT_FSM_RESUME_V1 BIT(30)
+#define BIT_HOST_RESUME_SYNC_V1 BIT(29)
+#define BIT_CHIP_PDNB_V1 BIT(28)
+
+#define BIT_SHIFT_FSM_SUSPEND_V1 25
+#define BIT_MASK_FSM_SUSPEND_V1 0x7
+#define BIT_FSM_SUSPEND_V1(x)                                                  \
+	(((x) & BIT_MASK_FSM_SUSPEND_V1) << BIT_SHIFT_FSM_SUSPEND_V1)
+#define BITS_FSM_SUSPEND_V1                                                    \
+	(BIT_MASK_FSM_SUSPEND_V1 << BIT_SHIFT_FSM_SUSPEND_V1)
+#define BIT_CLEAR_FSM_SUSPEND_V1(x) ((x) & (~BITS_FSM_SUSPEND_V1))
+#define BIT_GET_FSM_SUSPEND_V1(x)                                              \
+	(((x) >> BIT_SHIFT_FSM_SUSPEND_V1) & BIT_MASK_FSM_SUSPEND_V1)
+#define BIT_SET_FSM_SUSPEND_V1(x, v)                                           \
+	(BIT_CLEAR_FSM_SUSPEND_V1(x) | BIT_FSM_SUSPEND_V1(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_WLRF1				(Offset 0x00EC) */
+
+#define BIT_SHIFT_XTAL_SEL 25
+#define BIT_MASK_XTAL_SEL 0x3
+#define BIT_XTAL_SEL(x) (((x) & BIT_MASK_XTAL_SEL) << BIT_SHIFT_XTAL_SEL)
+#define BITS_XTAL_SEL (BIT_MASK_XTAL_SEL << BIT_SHIFT_XTAL_SEL)
+#define BIT_CLEAR_XTAL_SEL(x) ((x) & (~BITS_XTAL_SEL))
+#define BIT_GET_XTAL_SEL(x) (((x) >> BIT_SHIFT_XTAL_SEL) & BIT_MASK_XTAL_SEL)
+#define BIT_SET_XTAL_SEL(x, v) (BIT_CLEAR_XTAL_SEL(x) | BIT_XTAL_SEL(v))
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_WLRF1				(Offset 0x00EC) */
+
+#define BIT_SHIFT_WLRF1_CTRL 24
+#define BIT_MASK_WLRF1_CTRL 0xff
+#define BIT_WLRF1_CTRL(x) (((x) & BIT_MASK_WLRF1_CTRL) << BIT_SHIFT_WLRF1_CTRL)
+#define BITS_WLRF1_CTRL (BIT_MASK_WLRF1_CTRL << BIT_SHIFT_WLRF1_CTRL)
+#define BIT_CLEAR_WLRF1_CTRL(x) ((x) & (~BITS_WLRF1_CTRL))
+#define BIT_GET_WLRF1_CTRL(x)                                                  \
+	(((x) >> BIT_SHIFT_WLRF1_CTRL) & BIT_MASK_WLRF1_CTRL)
+#define BIT_SET_WLRF1_CTRL(x, v) (BIT_CLEAR_WLRF1_CTRL(x) | BIT_WLRF1_CTRL(v))
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_HPON_FSM				(Offset 0x00EC) */
+
+#define BIT_PMC_ALD_V1 BIT(24)
+
+#define BIT_SHIFT_HCI_SEL_1 22
+#define BIT_MASK_HCI_SEL_1 0x3
+#define BIT_HCI_SEL_1(x) (((x) & BIT_MASK_HCI_SEL_1) << BIT_SHIFT_HCI_SEL_1)
+#define BITS_HCI_SEL_1 (BIT_MASK_HCI_SEL_1 << BIT_SHIFT_HCI_SEL_1)
+#define BIT_CLEAR_HCI_SEL_1(x) ((x) & (~BITS_HCI_SEL_1))
+#define BIT_GET_HCI_SEL_1(x) (((x) >> BIT_SHIFT_HCI_SEL_1) & BIT_MASK_HCI_SEL_1)
+#define BIT_SET_HCI_SEL_1(x, v) (BIT_CLEAR_HCI_SEL_1(x) | BIT_HCI_SEL_1(v))
+
+#define BIT_LOAD_DONE_V1 BIT(21)
+#define BIT_CNT_MATCH BIT(20)
+#define BIT_TIMEUP_V1 BIT(19)
+#define BIT_SPS_12V_VLD BIT(18)
+#define BIT_PCIERST_V1 BIT(17)
+#define BIT_HOST_CLK_VLD BIT(16)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_WLRF1				(Offset 0x00EC) */
+
+#define BIT_SHIFT_WLRF2_CTRL 16
+#define BIT_MASK_WLRF2_CTRL 0xff
+#define BIT_WLRF2_CTRL(x) (((x) & BIT_MASK_WLRF2_CTRL) << BIT_SHIFT_WLRF2_CTRL)
+#define BITS_WLRF2_CTRL (BIT_MASK_WLRF2_CTRL << BIT_SHIFT_WLRF2_CTRL)
+#define BIT_CLEAR_WLRF2_CTRL(x) ((x) & (~BITS_WLRF2_CTRL))
+#define BIT_GET_WLRF2_CTRL(x)                                                  \
+	(((x) >> BIT_SHIFT_WLRF2_CTRL) & BIT_MASK_WLRF2_CTRL)
+#define BIT_SET_WLRF2_CTRL(x, v) (BIT_CLEAR_WLRF2_CTRL(x) | BIT_WLRF2_CTRL(v))
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_HPON_FSM				(Offset 0x00EC) */
+
+#define BIT_PMC_WR_V1 BIT(15)
+#define BIT_PMC_DATA_V1 BIT(14)
+
+#define BIT_SHIFT_PMC_ADDR_V1 8
+#define BIT_MASK_PMC_ADDR_V1 0x3f
+#define BIT_PMC_ADDR_V1(x)                                                     \
+	(((x) & BIT_MASK_PMC_ADDR_V1) << BIT_SHIFT_PMC_ADDR_V1)
+#define BITS_PMC_ADDR_V1 (BIT_MASK_PMC_ADDR_V1 << BIT_SHIFT_PMC_ADDR_V1)
+#define BIT_CLEAR_PMC_ADDR_V1(x) ((x) & (~BITS_PMC_ADDR_V1))
+#define BIT_GET_PMC_ADDR_V1(x)                                                 \
+	(((x) >> BIT_SHIFT_PMC_ADDR_V1) & BIT_MASK_PMC_ADDR_V1)
+#define BIT_SET_PMC_ADDR_V1(x, v)                                              \
+	(BIT_CLEAR_PMC_ADDR_V1(x) | BIT_PMC_ADDR_V1(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_WLRF1				(Offset 0x00EC) */
+
+#define BIT_SHIFT_WLRF3_CTRL 8
+#define BIT_MASK_WLRF3_CTRL 0xff
+#define BIT_WLRF3_CTRL(x) (((x) & BIT_MASK_WLRF3_CTRL) << BIT_SHIFT_WLRF3_CTRL)
+#define BITS_WLRF3_CTRL (BIT_MASK_WLRF3_CTRL << BIT_SHIFT_WLRF3_CTRL)
+#define BIT_CLEAR_WLRF3_CTRL(x) ((x) & (~BITS_WLRF3_CTRL))
+#define BIT_GET_WLRF3_CTRL(x)                                                  \
+	(((x) >> BIT_SHIFT_WLRF3_CTRL) & BIT_MASK_WLRF3_CTRL)
+#define BIT_SET_WLRF3_CTRL(x, v) (BIT_CLEAR_WLRF3_CTRL(x) | BIT_WLRF3_CTRL(v))
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_HPON_FSM				(Offset 0x00EC) */
+
+#define BIT_PMC_COUNT_EN_V1 BIT(7)
+
+#define BIT_SHIFT_FSM_STATE_V1 0
+#define BIT_MASK_FSM_STATE_V1 0x7f
+#define BIT_FSM_STATE_V1(x)                                                    \
+	(((x) & BIT_MASK_FSM_STATE_V1) << BIT_SHIFT_FSM_STATE_V1)
+#define BITS_FSM_STATE_V1 (BIT_MASK_FSM_STATE_V1 << BIT_SHIFT_FSM_STATE_V1)
+#define BIT_CLEAR_FSM_STATE_V1(x) ((x) & (~BITS_FSM_STATE_V1))
+#define BIT_GET_FSM_STATE_V1(x)                                                \
+	(((x) >> BIT_SHIFT_FSM_STATE_V1) & BIT_MASK_FSM_STATE_V1)
+#define BIT_SET_FSM_STATE_V1(x, v)                                             \
+	(BIT_CLEAR_FSM_STATE_V1(x) | BIT_FSM_STATE_V1(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_SYS_CFG1				(Offset 0x00F0) */
+
+#define BIT_SHIFT_TRP_ICFG 28
+#define BIT_MASK_TRP_ICFG 0xf
+#define BIT_TRP_ICFG(x) (((x) & BIT_MASK_TRP_ICFG) << BIT_SHIFT_TRP_ICFG)
+#define BITS_TRP_ICFG (BIT_MASK_TRP_ICFG << BIT_SHIFT_TRP_ICFG)
+#define BIT_CLEAR_TRP_ICFG(x) ((x) & (~BITS_TRP_ICFG))
+#define BIT_GET_TRP_ICFG(x) (((x) >> BIT_SHIFT_TRP_ICFG) & BIT_MASK_TRP_ICFG)
+#define BIT_SET_TRP_ICFG(x, v) (BIT_CLEAR_TRP_ICFG(x) | BIT_TRP_ICFG(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8881A_SUPPORT)
+
+/* 2 REG_SYS_CFG1				(Offset 0x00F0) */
+
+#define BIT_RF_TYPE_ID BIT(27)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_SYS_CFG1				(Offset 0x00F0) */
+
+#define BIT_BD_HCI_SEL BIT(26)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_SYS_CFG1				(Offset 0x00F0) */
+
+#define BIT_LDO_VLD BIT(26)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_SYS_CFG1				(Offset 0x00F0) */
+
+#define BIT_SHIFT_BD_HCI_SEL_V1 26
+#define BIT_MASK_BD_HCI_SEL_V1 0x3
+#define BIT_BD_HCI_SEL_V1(x)                                                   \
+	(((x) & BIT_MASK_BD_HCI_SEL_V1) << BIT_SHIFT_BD_HCI_SEL_V1)
+#define BITS_BD_HCI_SEL_V1 (BIT_MASK_BD_HCI_SEL_V1 << BIT_SHIFT_BD_HCI_SEL_V1)
+#define BIT_CLEAR_BD_HCI_SEL_V1(x) ((x) & (~BITS_BD_HCI_SEL_V1))
+#define BIT_GET_BD_HCI_SEL_V1(x)                                               \
+	(((x) >> BIT_SHIFT_BD_HCI_SEL_V1) & BIT_MASK_BD_HCI_SEL_V1)
+#define BIT_SET_BD_HCI_SEL_V1(x, v)                                            \
+	(BIT_CLEAR_BD_HCI_SEL_V1(x) | BIT_BD_HCI_SEL_V1(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_SYS_CFG1				(Offset 0x00F0) */
+
+#define BIT_BD_PKG_SEL BIT(25)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_SYS_CFG1				(Offset 0x00F0) */
+
+#define BIT_SPSLDO_SEL BIT(24)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_SYS_CFG1				(Offset 0x00F0) */
+
+#define BIT_INTERNAL_EXTERNAL_SWR BIT(24)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_SYS_CFG1				(Offset 0x00F0) */
+
+#define BIT_LDO_SPS_SEL BIT(24)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_SYS_CFG1				(Offset 0x00F0) */
+
+#define BIT_RTL_ID BIT(23)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_SYS_CFG1				(Offset 0x00F0) */
+
+#define BIT_PAD_HWPD_IDN BIT(22)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_SYS_CFG1				(Offset 0x00F0) */
+
+#define BIT_DIS_WL BIT(22)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_SYS_CFG1				(Offset 0x00F0) */
+
+#define BIT_TESTMODE BIT(20)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_SYS_CFG1				(Offset 0x00F0) */
+
+#define BIT_SHIFT_PSC_TESTCFG 20
+#define BIT_MASK_PSC_TESTCFG 0x3
+#define BIT_PSC_TESTCFG(x)                                                     \
+	(((x) & BIT_MASK_PSC_TESTCFG) << BIT_SHIFT_PSC_TESTCFG)
+#define BITS_PSC_TESTCFG (BIT_MASK_PSC_TESTCFG << BIT_SHIFT_PSC_TESTCFG)
+#define BIT_CLEAR_PSC_TESTCFG(x) ((x) & (~BITS_PSC_TESTCFG))
+#define BIT_GET_PSC_TESTCFG(x)                                                 \
+	(((x) >> BIT_SHIFT_PSC_TESTCFG) & BIT_MASK_PSC_TESTCFG)
+#define BIT_SET_PSC_TESTCFG(x, v)                                              \
+	(BIT_CLEAR_PSC_TESTCFG(x) | BIT_PSC_TESTCFG(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8881A_SUPPORT)
+
+/* 2 REG_SYS_CFG1				(Offset 0x00F0) */
+
+#define BIT_SHIFT_VENDOR_ID 16
+#define BIT_MASK_VENDOR_ID 0xf
+#define BIT_VENDOR_ID(x) (((x) & BIT_MASK_VENDOR_ID) << BIT_SHIFT_VENDOR_ID)
+#define BITS_VENDOR_ID (BIT_MASK_VENDOR_ID << BIT_SHIFT_VENDOR_ID)
+#define BIT_CLEAR_VENDOR_ID(x) ((x) & (~BITS_VENDOR_ID))
+#define BIT_GET_VENDOR_ID(x) (((x) >> BIT_SHIFT_VENDOR_ID) & BIT_MASK_VENDOR_ID)
+#define BIT_SET_VENDOR_ID(x, v) (BIT_CLEAR_VENDOR_ID(x) | BIT_VENDOR_ID(v))
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_SYS_CFG1				(Offset 0x00F0) */
+
+#define BIT_SHIFT_CHIP_VER_V2 16
+#define BIT_MASK_CHIP_VER_V2 0xf
+#define BIT_CHIP_VER_V2(x)                                                     \
+	(((x) & BIT_MASK_CHIP_VER_V2) << BIT_SHIFT_CHIP_VER_V2)
+#define BITS_CHIP_VER_V2 (BIT_MASK_CHIP_VER_V2 << BIT_SHIFT_CHIP_VER_V2)
+#define BIT_CLEAR_CHIP_VER_V2(x) ((x) & (~BITS_CHIP_VER_V2))
+#define BIT_GET_CHIP_VER_V2(x)                                                 \
+	(((x) >> BIT_SHIFT_CHIP_VER_V2) & BIT_MASK_CHIP_VER_V2)
+#define BIT_SET_CHIP_VER_V2(x, v)                                              \
+	(BIT_CLEAR_CHIP_VER_V2(x) | BIT_CHIP_VER_V2(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_SYS_CFG1				(Offset 0x00F0) */
+
+#define BIT_SHIFT_CHIP_VER 12
+#define BIT_MASK_CHIP_VER 0xf
+#define BIT_CHIP_VER(x) (((x) & BIT_MASK_CHIP_VER) << BIT_SHIFT_CHIP_VER)
+#define BITS_CHIP_VER (BIT_MASK_CHIP_VER << BIT_SHIFT_CHIP_VER)
+#define BIT_CLEAR_CHIP_VER(x) ((x) & (~BITS_CHIP_VER))
+#define BIT_GET_CHIP_VER(x) (((x) >> BIT_SHIFT_CHIP_VER) & BIT_MASK_CHIP_VER)
+#define BIT_SET_CHIP_VER(x, v) (BIT_CLEAR_CHIP_VER(x) | BIT_CHIP_VER(v))
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_SYS_CFG1				(Offset 0x00F0) */
+
+#define BIT_TST_MODE_SEL BIT(11)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_SYS_CFG1				(Offset 0x00F0) */
+
+#define BIT_BD_MAC3 BIT(11)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_SYS_CFG1				(Offset 0x00F0) */
+
+#define BIT_IC_MACPHY_MODE BIT(11)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_SYS_CFG1				(Offset 0x00F0) */
+
+#define BIT_BD_MAC1 BIT(10)
+#define BIT_BD_MAC2 BIT(9)
+#define BIT_SIC_IDLE BIT(8)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_SYS_CFG1				(Offset 0x00F0) */
+
+#define BIT_SW_OFFLOAD_EN BIT(7)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8881A_SUPPORT)
+
+/* 2 REG_SYS_CFG1				(Offset 0x00F0) */
+
+#define BIT_OCP_SHUTDN BIT(6)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_SYS_CFG1				(Offset 0x00F0) */
+
+#define BIT_OCP_SHUTDN_1 BIT(6)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8881A_SUPPORT)
+
+/* 2 REG_SYS_CFG1				(Offset 0x00F0) */
+
+#define BIT_V15_VLD BIT(5)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_SYS_CFG1				(Offset 0x00F0) */
+
+#define BIT_V12_VLD BIT(5)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_SYS_CFG1				(Offset 0x00F0) */
+
+#define BIT_PCIRSTB BIT(4)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8881A_SUPPORT)
+
+/* 2 REG_SYS_CFG1				(Offset 0x00F0) */
+
+#define BIT_PCLK_VLD BIT(3)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_SYS_CFG1				(Offset 0x00F0) */
+
+#define BIT_PCLK_VLD_1 BIT(3)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_SYS_CFG1				(Offset 0x00F0) */
+
+#define BIT_UCLK_VLD BIT(2)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8881A_SUPPORT)
+
+/* 2 REG_SYS_CFG1				(Offset 0x00F0) */
+
+#define BIT_ACLK_VLD BIT(1)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_SYS_CFG1				(Offset 0x00F0) */
+
+#define BIT_M200CLK_VLD_V1 BIT(1)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_SYS_CFG1				(Offset 0x00F0) */
+
+#define BIT_XCLK_VLD BIT(0)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_SYS_STATUS1				(Offset 0x00F4) */
+
+#define BIT_SYM_OSC32K_OUTSEL BIT(31)
+#define BIT_BTGP_WAKE_BT_LOC_BIT0 BIT(31)
+
+#define BIT_SHIFT_SYM_SEC_CLKSEL 30
+#define BIT_MASK_SYM_SEC_CLKSEL 0x3
+#define BIT_SYM_SEC_CLKSEL(x)                                                  \
+	(((x) & BIT_MASK_SYM_SEC_CLKSEL) << BIT_SHIFT_SYM_SEC_CLKSEL)
+#define BITS_SYM_SEC_CLKSEL                                                    \
+	(BIT_MASK_SYM_SEC_CLKSEL << BIT_SHIFT_SYM_SEC_CLKSEL)
+#define BIT_CLEAR_SYM_SEC_CLKSEL(x) ((x) & (~BITS_SYM_SEC_CLKSEL))
+#define BIT_GET_SYM_SEC_CLKSEL(x)                                              \
+	(((x) >> BIT_SHIFT_SYM_SEC_CLKSEL) & BIT_MASK_SYM_SEC_CLKSEL)
+#define BIT_SET_SYM_SEC_CLKSEL(x, v)                                           \
+	(BIT_CLEAR_SYM_SEC_CLKSEL(x) | BIT_SYM_SEC_CLKSEL(v))
+
+#define BIT_SHIFT_WL_GPIO_SEL 30
+#define BIT_MASK_WL_GPIO_SEL 0x3
+#define BIT_WL_GPIO_SEL(x)                                                     \
+	(((x) & BIT_MASK_WL_GPIO_SEL) << BIT_SHIFT_WL_GPIO_SEL)
+#define BITS_WL_GPIO_SEL (BIT_MASK_WL_GPIO_SEL << BIT_SHIFT_WL_GPIO_SEL)
+#define BIT_CLEAR_WL_GPIO_SEL(x) ((x) & (~BITS_WL_GPIO_SEL))
+#define BIT_GET_WL_GPIO_SEL(x)                                                 \
+	(((x) >> BIT_SHIFT_WL_GPIO_SEL) & BIT_MASK_WL_GPIO_SEL)
+#define BIT_SET_WL_GPIO_SEL(x, v)                                              \
+	(BIT_CLEAR_WL_GPIO_SEL(x) | BIT_WL_GPIO_SEL(v))
+
+#define BIT_SHIFT_BT_MCM_CTRL_LOC 29
+#define BIT_MASK_BT_MCM_CTRL_LOC 0x3
+#define BIT_BT_MCM_CTRL_LOC(x)                                                 \
+	(((x) & BIT_MASK_BT_MCM_CTRL_LOC) << BIT_SHIFT_BT_MCM_CTRL_LOC)
+#define BITS_BT_MCM_CTRL_LOC                                                   \
+	(BIT_MASK_BT_MCM_CTRL_LOC << BIT_SHIFT_BT_MCM_CTRL_LOC)
+#define BIT_CLEAR_BT_MCM_CTRL_LOC(x) ((x) & (~BITS_BT_MCM_CTRL_LOC))
+#define BIT_GET_BT_MCM_CTRL_LOC(x)                                             \
+	(((x) >> BIT_SHIFT_BT_MCM_CTRL_LOC) & BIT_MASK_BT_MCM_CTRL_LOC)
+#define BIT_SET_BT_MCM_CTRL_LOC(x, v)                                          \
+	(BIT_CLEAR_BT_MCM_CTRL_LOC(x) | BIT_BT_MCM_CTRL_LOC(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_SYS_STATUS1				(Offset 0x00F4) */
+
+#define BIT_SHIFT_RF_RL_ID 28
+#define BIT_MASK_RF_RL_ID 0xf
+#define BIT_RF_RL_ID(x) (((x) & BIT_MASK_RF_RL_ID) << BIT_SHIFT_RF_RL_ID)
+#define BITS_RF_RL_ID (BIT_MASK_RF_RL_ID << BIT_SHIFT_RF_RL_ID)
+#define BIT_CLEAR_RF_RL_ID(x) ((x) & (~BITS_RF_RL_ID))
+#define BIT_GET_RF_RL_ID(x) (((x) >> BIT_SHIFT_RF_RL_ID) & BIT_MASK_RF_RL_ID)
+#define BIT_SET_RF_RL_ID(x, v) (BIT_CLEAR_RF_RL_ID(x) | BIT_RF_RL_ID(v))
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_SYS_STATUS1				(Offset 0x00F4) */
+
+#define BIT_SHIFT_SYM_MAC_CLKSEL 28
+#define BIT_MASK_SYM_MAC_CLKSEL 0x3
+#define BIT_SYM_MAC_CLKSEL(x)                                                  \
+	(((x) & BIT_MASK_SYM_MAC_CLKSEL) << BIT_SHIFT_SYM_MAC_CLKSEL)
+#define BITS_SYM_MAC_CLKSEL                                                    \
+	(BIT_MASK_SYM_MAC_CLKSEL << BIT_SHIFT_SYM_MAC_CLKSEL)
+#define BIT_CLEAR_SYM_MAC_CLKSEL(x) ((x) & (~BITS_SYM_MAC_CLKSEL))
+#define BIT_GET_SYM_MAC_CLKSEL(x)                                              \
+	(((x) >> BIT_SHIFT_SYM_MAC_CLKSEL) & BIT_MASK_SYM_MAC_CLKSEL)
+#define BIT_SET_SYM_MAC_CLKSEL(x, v)                                           \
+	(BIT_CLEAR_SYM_MAC_CLKSEL(x) | BIT_SYM_MAC_CLKSEL(v))
+
+#define BIT_SHIFT_SW_DPDT_LOC 27
+#define BIT_MASK_SW_DPDT_LOC 0x3
+#define BIT_SW_DPDT_LOC(x)                                                     \
+	(((x) & BIT_MASK_SW_DPDT_LOC) << BIT_SHIFT_SW_DPDT_LOC)
+#define BITS_SW_DPDT_LOC (BIT_MASK_SW_DPDT_LOC << BIT_SHIFT_SW_DPDT_LOC)
+#define BIT_CLEAR_SW_DPDT_LOC(x) ((x) & (~BITS_SW_DPDT_LOC))
+#define BIT_GET_SW_DPDT_LOC(x)                                                 \
+	(((x) >> BIT_SHIFT_SW_DPDT_LOC) & BIT_MASK_SW_DPDT_LOC)
+#define BIT_SET_SW_DPDT_LOC(x, v)                                              \
+	(BIT_CLEAR_SW_DPDT_LOC(x) | BIT_SW_DPDT_LOC(v))
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_SYS_STATUS1				(Offset 0x00F4) */
+
+#define BIT_U3_CLK_VLD BIT(27)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_SYS_STATUS1				(Offset 0x00F4) */
+
+#define BIT_WLGP_HW_DIS_LOC_BIT0 BIT(26)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_SYS_STATUS1				(Offset 0x00F4) */
+
+#define BIT_PRST_VLD_V1 BIT(26)
+#define BIT_PDN BIT(25)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_SYS_STATUS1				(Offset 0x00F4) */
+
+#define BIT_SHIFT_PKG_SEL 24
+#define BIT_MASK_PKG_SEL 0x3
+#define BIT_PKG_SEL(x) (((x) & BIT_MASK_PKG_SEL) << BIT_SHIFT_PKG_SEL)
+#define BITS_PKG_SEL (BIT_MASK_PKG_SEL << BIT_SHIFT_PKG_SEL)
+#define BIT_CLEAR_PKG_SEL(x) ((x) & (~BITS_PKG_SEL))
+#define BIT_GET_PKG_SEL(x) (((x) >> BIT_SHIFT_PKG_SEL) & BIT_MASK_PKG_SEL)
+#define BIT_SET_PKG_SEL(x, v) (BIT_CLEAR_PKG_SEL(x) | BIT_PKG_SEL(v))
+
+#define BIT_SHIFT_SYM_OSC32K_RCAL 24
+#define BIT_MASK_SYM_OSC32K_RCAL 0x3f
+#define BIT_SYM_OSC32K_RCAL(x)                                                 \
+	(((x) & BIT_MASK_SYM_OSC32K_RCAL) << BIT_SHIFT_SYM_OSC32K_RCAL)
+#define BITS_SYM_OSC32K_RCAL                                                   \
+	(BIT_MASK_SYM_OSC32K_RCAL << BIT_SHIFT_SYM_OSC32K_RCAL)
+#define BIT_CLEAR_SYM_OSC32K_RCAL(x) ((x) & (~BITS_SYM_OSC32K_RCAL))
+#define BIT_GET_SYM_OSC32K_RCAL(x)                                             \
+	(((x) >> BIT_SHIFT_SYM_OSC32K_RCAL) & BIT_MASK_SYM_OSC32K_RCAL)
+#define BIT_SET_SYM_OSC32K_RCAL(x, v)                                          \
+	(BIT_CLEAR_SYM_OSC32K_RCAL(x) | BIT_SYM_OSC32K_RCAL(v))
+
+#define BIT_SHIFT_SW_GPIO_B_PD 24
+#define BIT_MASK_SW_GPIO_B_PD 0xff
+#define BIT_SW_GPIO_B_PD(x)                                                    \
+	(((x) & BIT_MASK_SW_GPIO_B_PD) << BIT_SHIFT_SW_GPIO_B_PD)
+#define BITS_SW_GPIO_B_PD (BIT_MASK_SW_GPIO_B_PD << BIT_SHIFT_SW_GPIO_B_PD)
+#define BIT_CLEAR_SW_GPIO_B_PD(x) ((x) & (~BITS_SW_GPIO_B_PD))
+#define BIT_GET_SW_GPIO_B_PD(x)                                                \
+	(((x) >> BIT_SHIFT_SW_GPIO_B_PD) & BIT_MASK_SW_GPIO_B_PD)
+#define BIT_SET_SW_GPIO_B_PD(x, v)                                             \
+	(BIT_CLEAR_SW_GPIO_B_PD(x) | BIT_SW_GPIO_B_PD(v))
+
+#define BIT_SHIFT_SW_GPIO_B_IN 24
+#define BIT_MASK_SW_GPIO_B_IN 0xff
+#define BIT_SW_GPIO_B_IN(x)                                                    \
+	(((x) & BIT_MASK_SW_GPIO_B_IN) << BIT_SHIFT_SW_GPIO_B_IN)
+#define BITS_SW_GPIO_B_IN (BIT_MASK_SW_GPIO_B_IN << BIT_SHIFT_SW_GPIO_B_IN)
+#define BIT_CLEAR_SW_GPIO_B_IN(x) ((x) & (~BITS_SW_GPIO_B_IN))
+#define BIT_GET_SW_GPIO_B_IN(x)                                                \
+	(((x) >> BIT_SHIFT_SW_GPIO_B_IN) & BIT_MASK_SW_GPIO_B_IN)
+#define BIT_SET_SW_GPIO_B_IN(x, v)                                             \
+	(BIT_CLEAR_SW_GPIO_B_IN(x) | BIT_SW_GPIO_B_IN(v))
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_SYS_STATUS1				(Offset 0x00F4) */
+
+#define BIT_OCP_SHUTDN_V1 BIT(24)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_SYS_STATUS1				(Offset 0x00F4) */
+
+#define BIT_SHIFT_ANT_SEL_01_LOC 23
+#define BIT_MASK_ANT_SEL_01_LOC 0x7
+#define BIT_ANT_SEL_01_LOC(x)                                                  \
+	(((x) & BIT_MASK_ANT_SEL_01_LOC) << BIT_SHIFT_ANT_SEL_01_LOC)
+#define BITS_ANT_SEL_01_LOC                                                    \
+	(BIT_MASK_ANT_SEL_01_LOC << BIT_SHIFT_ANT_SEL_01_LOC)
+#define BIT_CLEAR_ANT_SEL_01_LOC(x) ((x) & (~BITS_ANT_SEL_01_LOC))
+#define BIT_GET_ANT_SEL_01_LOC(x)                                              \
+	(((x) >> BIT_SHIFT_ANT_SEL_01_LOC) & BIT_MASK_ANT_SEL_01_LOC)
+#define BIT_SET_ANT_SEL_01_LOC(x, v)                                           \
+	(BIT_CLEAR_ANT_SEL_01_LOC(x) | BIT_ANT_SEL_01_LOC(v))
+
+#define BIT_SHIFT_AUTOLOADABLE_AT_1FC 23
+#define BIT_MASK_AUTOLOADABLE_AT_1FC 0x3f
+#define BIT_AUTOLOADABLE_AT_1FC(x)                                             \
+	(((x) & BIT_MASK_AUTOLOADABLE_AT_1FC) << BIT_SHIFT_AUTOLOADABLE_AT_1FC)
+#define BITS_AUTOLOADABLE_AT_1FC                                               \
+	(BIT_MASK_AUTOLOADABLE_AT_1FC << BIT_SHIFT_AUTOLOADABLE_AT_1FC)
+#define BIT_CLEAR_AUTOLOADABLE_AT_1FC(x) ((x) & (~BITS_AUTOLOADABLE_AT_1FC))
+#define BIT_GET_AUTOLOADABLE_AT_1FC(x)                                         \
+	(((x) >> BIT_SHIFT_AUTOLOADABLE_AT_1FC) & BIT_MASK_AUTOLOADABLE_AT_1FC)
+#define BIT_SET_AUTOLOADABLE_AT_1FC(x, v)                                      \
+	(BIT_CLEAR_AUTOLOADABLE_AT_1FC(x) | BIT_AUTOLOADABLE_AT_1FC(v))
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_SYS_STATUS1				(Offset 0x00F4) */
+
+#define BIT_PCLK_VLD_V1 BIT(23)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_SYS_STATUS1				(Offset 0x00F4) */
+
+#define BIT_BT_DISN_EN_V1 BIT(22)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_SYS_STATUS1				(Offset 0x00F4) */
+
+#define BIT_U2_CLK_VLD BIT(22)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_SYS_STATUS1				(Offset 0x00F4) */
+
+#define BIT_SHIFT_ANT_SEL_23_LOC 21
+#define BIT_MASK_ANT_SEL_23_LOC 0x3
+#define BIT_ANT_SEL_23_LOC(x)                                                  \
+	(((x) & BIT_MASK_ANT_SEL_23_LOC) << BIT_SHIFT_ANT_SEL_23_LOC)
+#define BITS_ANT_SEL_23_LOC                                                    \
+	(BIT_MASK_ANT_SEL_23_LOC << BIT_SHIFT_ANT_SEL_23_LOC)
+#define BIT_CLEAR_ANT_SEL_23_LOC(x) ((x) & (~BITS_ANT_SEL_23_LOC))
+#define BIT_GET_ANT_SEL_23_LOC(x)                                              \
+	(((x) >> BIT_SHIFT_ANT_SEL_23_LOC) & BIT_MASK_ANT_SEL_23_LOC)
+#define BIT_SET_ANT_SEL_23_LOC(x, v)                                           \
+	(BIT_CLEAR_ANT_SEL_23_LOC(x) | BIT_ANT_SEL_23_LOC(v))
+
+#define BIT_BT_SUSN_LOC BIT(21)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_SYS_STATUS1				(Offset 0x00F4) */
+
+#define BIT_PLL_CLK_VLD BIT(21)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_SYS_STATUS1				(Offset 0x00F4) */
+
+#define BIT_SHIFT_SW_ICFG 20
+#define BIT_MASK_SW_ICFG 0xf
+#define BIT_SW_ICFG(x) (((x) & BIT_MASK_SW_ICFG) << BIT_SHIFT_SW_ICFG)
+#define BITS_SW_ICFG (BIT_MASK_SW_ICFG << BIT_SHIFT_SW_ICFG)
+#define BIT_CLEAR_SW_ICFG(x) ((x) & (~BITS_SW_ICFG))
+#define BIT_GET_SW_ICFG(x) (((x) >> BIT_SHIFT_SW_ICFG) & BIT_MASK_SW_ICFG)
+#define BIT_SET_SW_ICFG(x, v) (BIT_CLEAR_SW_ICFG(x) | BIT_SW_ICFG(v))
+
+#define BIT_SYM_CONF_BYTE_ENB BIT(20)
+#define BIT_WLBB_RFE_LED1 BIT(20)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_SYS_STATUS1				(Offset 0x00F4) */
+
+#define BIT_XCK_VLD BIT(20)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_SYS_STATUS1				(Offset 0x00F4) */
+
+#define BIT_HPHY_ICFG BIT(19)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_SYS_STATUS1				(Offset 0x00F4) */
+
+#define BIT_SHIFT_EXTCK32K_LOC 19
+#define BIT_MASK_EXTCK32K_LOC 0x3
+#define BIT_EXTCK32K_LOC(x)                                                    \
+	(((x) & BIT_MASK_EXTCK32K_LOC) << BIT_SHIFT_EXTCK32K_LOC)
+#define BITS_EXTCK32K_LOC (BIT_MASK_EXTCK32K_LOC << BIT_SHIFT_EXTCK32K_LOC)
+#define BIT_CLEAR_EXTCK32K_LOC(x) ((x) & (~BITS_EXTCK32K_LOC))
+#define BIT_GET_EXTCK32K_LOC(x)                                                \
+	(((x) >> BIT_SHIFT_EXTCK32K_LOC) & BIT_MASK_EXTCK32K_LOC)
+#define BIT_SET_EXTCK32K_LOC(x, v)                                             \
+	(BIT_CLEAR_EXTCK32K_LOC(x) | BIT_EXTCK32K_LOC(v))
+
+#define BIT_WLGP_LED1_EN BIT(19)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_SYS_STATUS1				(Offset 0x00F4) */
+
+#define BIT_CK200M_VLD BIT(19)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_SYS_STATUS1				(Offset 0x00F4) */
+
+#define BIT_BT_COEX_MBOX_LOC BIT(18)
+#define BIT_WLGP_ANT23_EN BIT(18)
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+/* 2 REG_SYS_STATUS1				(Offset 0x00F4) */
+
+#define BIT_HCI_SEL_EMBEDDED BIT(18)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_SYS_STATUS1				(Offset 0x00F4) */
+
+#define BIT_BTEN_TRAP BIT(18)
+#define BIT_PKG_EN_V1 BIT(17)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8881A_SUPPORT)
+
+/* 2 REG_SYS_STATUS1				(Offset 0x00F4) */
+
+#define BIT_SHIFT_SEL_0XC0 16
+#define BIT_MASK_SEL_0XC0 0x3
+#define BIT_SEL_0XC0(x) (((x) & BIT_MASK_SEL_0XC0) << BIT_SHIFT_SEL_0XC0)
+#define BITS_SEL_0XC0 (BIT_MASK_SEL_0XC0 << BIT_SHIFT_SEL_0XC0)
+#define BIT_CLEAR_SEL_0XC0(x) ((x) & (~BITS_SEL_0XC0))
+#define BIT_GET_SEL_0XC0(x) (((x) >> BIT_SHIFT_SEL_0XC0) & BIT_MASK_SEL_0XC0)
+#define BIT_SET_SEL_0XC0(x, v) (BIT_CLEAR_SEL_0XC0(x) | BIT_SEL_0XC0(v))
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_SYS_STATUS1				(Offset 0x00F4) */
+
+#define BIT_SYM_MCUFWDL_DDMA_EN BIT(16)
+#define BIT_SYM_SPIC_BOOT_ADDR_CMP BIT(16)
+
+#define BIT_SHIFT_SYM_OSC32K_CLKGEN0 16
+#define BIT_MASK_SYM_OSC32K_CLKGEN0 0xff
+#define BIT_SYM_OSC32K_CLKGEN0(x)                                              \
+	(((x) & BIT_MASK_SYM_OSC32K_CLKGEN0) << BIT_SHIFT_SYM_OSC32K_CLKGEN0)
+#define BITS_SYM_OSC32K_CLKGEN0                                                \
+	(BIT_MASK_SYM_OSC32K_CLKGEN0 << BIT_SHIFT_SYM_OSC32K_CLKGEN0)
+#define BIT_CLEAR_SYM_OSC32K_CLKGEN0(x) ((x) & (~BITS_SYM_OSC32K_CLKGEN0))
+#define BIT_GET_SYM_OSC32K_CLKGEN0(x)                                          \
+	(((x) >> BIT_SHIFT_SYM_OSC32K_CLKGEN0) & BIT_MASK_SYM_OSC32K_CLKGEN0)
+#define BIT_SET_SYM_OSC32K_CLKGEN0(x, v)                                       \
+	(BIT_CLEAR_SYM_OSC32K_CLKGEN0(x) | BIT_SYM_OSC32K_CLKGEN0(v))
+
+#define BIT_SHIFT_CRC16_RESULT 16
+#define BIT_MASK_CRC16_RESULT 0xffff
+#define BIT_CRC16_RESULT(x)                                                    \
+	(((x) & BIT_MASK_CRC16_RESULT) << BIT_SHIFT_CRC16_RESULT)
+#define BITS_CRC16_RESULT (BIT_MASK_CRC16_RESULT << BIT_SHIFT_CRC16_RESULT)
+#define BIT_CLEAR_CRC16_RESULT(x) ((x) & (~BITS_CRC16_RESULT))
+#define BIT_GET_CRC16_RESULT(x)                                                \
+	(((x) >> BIT_SHIFT_CRC16_RESULT) & BIT_MASK_CRC16_RESULT)
+#define BIT_SET_CRC16_RESULT(x, v)                                             \
+	(BIT_CLEAR_CRC16_RESULT(x) | BIT_CRC16_RESULT(v))
+
+#define BIT_SHIFT_BTGP_LEDIO_LOC 16
+#define BIT_MASK_BTGP_LEDIO_LOC 0x3
+#define BIT_BTGP_LEDIO_LOC(x)                                                  \
+	(((x) & BIT_MASK_BTGP_LEDIO_LOC) << BIT_SHIFT_BTGP_LEDIO_LOC)
+#define BITS_BTGP_LEDIO_LOC                                                    \
+	(BIT_MASK_BTGP_LEDIO_LOC << BIT_SHIFT_BTGP_LEDIO_LOC)
+#define BIT_CLEAR_BTGP_LEDIO_LOC(x) ((x) & (~BITS_BTGP_LEDIO_LOC))
+#define BIT_GET_BTGP_LEDIO_LOC(x)                                              \
+	(((x) >> BIT_SHIFT_BTGP_LEDIO_LOC) & BIT_MASK_BTGP_LEDIO_LOC)
+#define BIT_SET_BTGP_LEDIO_LOC(x, v)                                           \
+	(BIT_CLEAR_BTGP_LEDIO_LOC(x) | BIT_BTGP_LEDIO_LOC(v))
+
+#define BIT_SHIFT_FEM_EN 16
+#define BIT_MASK_FEM_EN 0x3
+#define BIT_FEM_EN(x) (((x) & BIT_MASK_FEM_EN) << BIT_SHIFT_FEM_EN)
+#define BITS_FEM_EN (BIT_MASK_FEM_EN << BIT_SHIFT_FEM_EN)
+#define BIT_CLEAR_FEM_EN(x) ((x) & (~BITS_FEM_EN))
+#define BIT_GET_FEM_EN(x) (((x) >> BIT_SHIFT_FEM_EN) & BIT_MASK_FEM_EN)
+#define BIT_SET_FEM_EN(x, v) (BIT_CLEAR_FEM_EN(x) | BIT_FEM_EN(v))
+
+#define BIT_SHIFT_SW_GPIO_B_PU 16
+#define BIT_MASK_SW_GPIO_B_PU 0xff
+#define BIT_SW_GPIO_B_PU(x)                                                    \
+	(((x) & BIT_MASK_SW_GPIO_B_PU) << BIT_SHIFT_SW_GPIO_B_PU)
+#define BITS_SW_GPIO_B_PU (BIT_MASK_SW_GPIO_B_PU << BIT_SHIFT_SW_GPIO_B_PU)
+#define BIT_CLEAR_SW_GPIO_B_PU(x) ((x) & (~BITS_SW_GPIO_B_PU))
+#define BIT_GET_SW_GPIO_B_PU(x)                                                \
+	(((x) >> BIT_SHIFT_SW_GPIO_B_PU) & BIT_MASK_SW_GPIO_B_PU)
+#define BIT_SET_SW_GPIO_B_PU(x, v)                                             \
+	(BIT_CLEAR_SW_GPIO_B_PU(x) | BIT_SW_GPIO_B_PU(v))
+
+#define BIT_SHIFT_SYM_INT_PERIODIC 16
+#define BIT_MASK_SYM_INT_PERIODIC 0x3ff
+#define BIT_SYM_INT_PERIODIC(x)                                                \
+	(((x) & BIT_MASK_SYM_INT_PERIODIC) << BIT_SHIFT_SYM_INT_PERIODIC)
+#define BITS_SYM_INT_PERIODIC                                                  \
+	(BIT_MASK_SYM_INT_PERIODIC << BIT_SHIFT_SYM_INT_PERIODIC)
+#define BIT_CLEAR_SYM_INT_PERIODIC(x) ((x) & (~BITS_SYM_INT_PERIODIC))
+#define BIT_GET_SYM_INT_PERIODIC(x)                                            \
+	(((x) >> BIT_SHIFT_SYM_INT_PERIODIC) & BIT_MASK_SYM_INT_PERIODIC)
+#define BIT_SET_SYM_INT_PERIODIC(x, v)                                         \
+	(BIT_CLEAR_SYM_INT_PERIODIC(x) | BIT_SYM_INT_PERIODIC(v))
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_SYS_STATUS1				(Offset 0x00F4) */
+
+#define BIT_TRAP_LDO_SPS_V1 BIT(16)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_SYS_STATUS1				(Offset 0x00F4) */
+
+#define BIT_IDV_DPDTSEL_P BIT(15)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_SYS_STATUS1				(Offset 0x00F4) */
+
+#define BIT_MACRDY BIT(15)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_SYS_STATUS1				(Offset 0x00F4) */
+
+#define BIT_SHIFT_LTE_COEX_UART_LOC 14
+#define BIT_MASK_LTE_COEX_UART_LOC 0x3
+#define BIT_LTE_COEX_UART_LOC(x)                                               \
+	(((x) & BIT_MASK_LTE_COEX_UART_LOC) << BIT_SHIFT_LTE_COEX_UART_LOC)
+#define BITS_LTE_COEX_UART_LOC                                                 \
+	(BIT_MASK_LTE_COEX_UART_LOC << BIT_SHIFT_LTE_COEX_UART_LOC)
+#define BIT_CLEAR_LTE_COEX_UART_LOC(x) ((x) & (~BITS_LTE_COEX_UART_LOC))
+#define BIT_GET_LTE_COEX_UART_LOC(x)                                           \
+	(((x) >> BIT_SHIFT_LTE_COEX_UART_LOC) & BIT_MASK_LTE_COEX_UART_LOC)
+#define BIT_SET_LTE_COEX_UART_LOC(x, v)                                        \
+	(BIT_CLEAR_LTE_COEX_UART_LOC(x) | BIT_LTE_COEX_UART_LOC(v))
+
+#define BIT_IDV_DPDTSEL_N BIT(14)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_SYS_STATUS1				(Offset 0x00F4) */
+
+#define BIT_12V_VLD BIT(14)
+#define BIT_U3PHY_RST BIT(13)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_SYS_STATUS1				(Offset 0x00F4) */
+
+#define BIT_SHIFT_SYM_LDOA12V_WT 12
+#define BIT_MASK_SYM_LDOA12V_WT 0x3
+#define BIT_SYM_LDOA12V_WT(x)                                                  \
+	(((x) & BIT_MASK_SYM_LDOA12V_WT) << BIT_SHIFT_SYM_LDOA12V_WT)
+#define BITS_SYM_LDOA12V_WT                                                    \
+	(BIT_MASK_SYM_LDOA12V_WT << BIT_SHIFT_SYM_LDOA12V_WT)
+#define BIT_CLEAR_SYM_LDOA12V_WT(x) ((x) & (~BITS_SYM_LDOA12V_WT))
+#define BIT_GET_SYM_LDOA12V_WT(x)                                              \
+	(((x) >> BIT_SHIFT_SYM_LDOA12V_WT) & BIT_MASK_SYM_LDOA12V_WT)
+#define BIT_SET_SYM_LDOA12V_WT(x, v)                                           \
+	(BIT_CLEAR_SYM_LDOA12V_WT(x) | BIT_SYM_LDOA12V_WT(v))
+
+#define BIT_SHIFT_SYM_OSC32K_TEMP_COMP 12
+#define BIT_MASK_SYM_OSC32K_TEMP_COMP 0xf
+#define BIT_SYM_OSC32K_TEMP_COMP(x)                                            \
+	(((x) & BIT_MASK_SYM_OSC32K_TEMP_COMP)                                 \
+	 << BIT_SHIFT_SYM_OSC32K_TEMP_COMP)
+#define BITS_SYM_OSC32K_TEMP_COMP                                              \
+	(BIT_MASK_SYM_OSC32K_TEMP_COMP << BIT_SHIFT_SYM_OSC32K_TEMP_COMP)
+#define BIT_CLEAR_SYM_OSC32K_TEMP_COMP(x) ((x) & (~BITS_SYM_OSC32K_TEMP_COMP))
+#define BIT_GET_SYM_OSC32K_TEMP_COMP(x)                                        \
+	(((x) >> BIT_SHIFT_SYM_OSC32K_TEMP_COMP) &                             \
+	 BIT_MASK_SYM_OSC32K_TEMP_COMP)
+#define BIT_SET_SYM_OSC32K_TEMP_COMP(x, v)                                     \
+	(BIT_CLEAR_SYM_OSC32K_TEMP_COMP(x) | BIT_SYM_OSC32K_TEMP_COMP(v))
+
+#define BIT_SHIFT_LTE_3W_LOC 12
+#define BIT_MASK_LTE_3W_LOC 0x3
+#define BIT_LTE_3W_LOC(x) (((x) & BIT_MASK_LTE_3W_LOC) << BIT_SHIFT_LTE_3W_LOC)
+#define BITS_LTE_3W_LOC (BIT_MASK_LTE_3W_LOC << BIT_SHIFT_LTE_3W_LOC)
+#define BIT_CLEAR_LTE_3W_LOC(x) ((x) & (~BITS_LTE_3W_LOC))
+#define BIT_GET_LTE_3W_LOC(x)                                                  \
+	(((x) >> BIT_SHIFT_LTE_3W_LOC) & BIT_MASK_LTE_3W_LOC)
+#define BIT_SET_LTE_3W_LOC(x, v) (BIT_CLEAR_LTE_3W_LOC(x) | BIT_LTE_3W_LOC(v))
+
+#define BIT_SHIFT_HW_EXTWOL_LOC 12
+#define BIT_MASK_HW_EXTWOL_LOC 0x3
+#define BIT_HW_EXTWOL_LOC(x)                                                   \
+	(((x) & BIT_MASK_HW_EXTWOL_LOC) << BIT_SHIFT_HW_EXTWOL_LOC)
+#define BITS_HW_EXTWOL_LOC (BIT_MASK_HW_EXTWOL_LOC << BIT_SHIFT_HW_EXTWOL_LOC)
+#define BIT_CLEAR_HW_EXTWOL_LOC(x) ((x) & (~BITS_HW_EXTWOL_LOC))
+#define BIT_GET_HW_EXTWOL_LOC(x)                                               \
+	(((x) >> BIT_SHIFT_HW_EXTWOL_LOC) & BIT_MASK_HW_EXTWOL_LOC)
+#define BIT_SET_HW_EXTWOL_LOC(x, v)                                            \
+	(BIT_CLEAR_HW_EXTWOL_LOC(x) | BIT_HW_EXTWOL_LOC(v))
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_SYS_STATUS1				(Offset 0x00F4) */
+
+#define BIT_SHIFT_HCI_SEL_V4 12
+#define BIT_MASK_HCI_SEL_V4 0x3
+#define BIT_HCI_SEL_V4(x) (((x) & BIT_MASK_HCI_SEL_V4) << BIT_SHIFT_HCI_SEL_V4)
+#define BITS_HCI_SEL_V4 (BIT_MASK_HCI_SEL_V4 << BIT_SHIFT_HCI_SEL_V4)
+#define BIT_CLEAR_HCI_SEL_V4(x) ((x) & (~BITS_HCI_SEL_V4))
+#define BIT_GET_HCI_SEL_V4(x)                                                  \
+	(((x) >> BIT_SHIFT_HCI_SEL_V4) & BIT_MASK_HCI_SEL_V4)
+#define BIT_SET_HCI_SEL_V4(x, v) (BIT_CLEAR_HCI_SEL_V4(x) | BIT_HCI_SEL_V4(v))
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_SYS_STATUS1				(Offset 0x00F4) */
+
+#define BIT_USB2_SEL_V1 BIT(12)
+
+#endif
+
+#if (HALMAC_8822B_SUPPORT)
+
+/* 2 REG_SYS_STATUS1				(Offset 0x00F4) */
+
+#define BIT_SHIFT_HCI_SEL_V3 12
+#define BIT_MASK_HCI_SEL_V3 0x7
+#define BIT_HCI_SEL_V3(x) (((x) & BIT_MASK_HCI_SEL_V3) << BIT_SHIFT_HCI_SEL_V3)
+#define BITS_HCI_SEL_V3 (BIT_MASK_HCI_SEL_V3 << BIT_SHIFT_HCI_SEL_V3)
+#define BIT_CLEAR_HCI_SEL_V3(x) ((x) & (~BITS_HCI_SEL_V3))
+#define BIT_GET_HCI_SEL_V3(x)                                                  \
+	(((x) >> BIT_SHIFT_HCI_SEL_V3) & BIT_MASK_HCI_SEL_V3)
+#define BIT_SET_HCI_SEL_V3(x, v) (BIT_CLEAR_HCI_SEL_V3(x) | BIT_HCI_SEL_V3(v))
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_SYS_STATUS1				(Offset 0x00F4) */
+
+#define BIT_SIC_LOC BIT(11)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8881A_SUPPORT)
+
+/* 2 REG_SYS_STATUS1				(Offset 0x00F4) */
+
+#define BIT_USB_OPERATION_MODE BIT(10)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_SYS_STATUS1				(Offset 0x00F4) */
+
+#define BIT_SHIFT_BTGP_WAKE_LOC 10
+#define BIT_MASK_BTGP_WAKE_LOC 0x3
+#define BIT_BTGP_WAKE_LOC(x)                                                   \
+	(((x) & BIT_MASK_BTGP_WAKE_LOC) << BIT_SHIFT_BTGP_WAKE_LOC)
+#define BITS_BTGP_WAKE_LOC (BIT_MASK_BTGP_WAKE_LOC << BIT_SHIFT_BTGP_WAKE_LOC)
+#define BIT_CLEAR_BTGP_WAKE_LOC(x) ((x) & (~BITS_BTGP_WAKE_LOC))
+#define BIT_GET_BTGP_WAKE_LOC(x)                                               \
+	(((x) >> BIT_SHIFT_BTGP_WAKE_LOC) & BIT_MASK_BTGP_WAKE_LOC)
+#define BIT_SET_BTGP_WAKE_LOC(x, v)                                            \
+	(BIT_CLEAR_BTGP_WAKE_LOC(x) | BIT_BTGP_WAKE_LOC(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8881A_SUPPORT)
+
+/* 2 REG_SYS_STATUS1				(Offset 0x00F4) */
+
+#define BIT_BT_PDN BIT(9)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_SYS_STATUS1				(Offset 0x00F4) */
+
+#define BIT_SHIFT_WLMAC_DBG_LOC 9
+#define BIT_MASK_WLMAC_DBG_LOC 0x3
+#define BIT_WLMAC_DBG_LOC(x)                                                   \
+	(((x) & BIT_MASK_WLMAC_DBG_LOC) << BIT_SHIFT_WLMAC_DBG_LOC)
+#define BITS_WLMAC_DBG_LOC (BIT_MASK_WLMAC_DBG_LOC << BIT_SHIFT_WLMAC_DBG_LOC)
+#define BIT_CLEAR_WLMAC_DBG_LOC(x) ((x) & (~BITS_WLMAC_DBG_LOC))
+#define BIT_GET_WLMAC_DBG_LOC(x)                                               \
+	(((x) >> BIT_SHIFT_WLMAC_DBG_LOC) & BIT_MASK_WLMAC_DBG_LOC)
+#define BIT_SET_WLMAC_DBG_LOC(x, v)                                            \
+	(BIT_CLEAR_WLMAC_DBG_LOC(x) | BIT_WLMAC_DBG_LOC(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8881A_SUPPORT)
+
+/* 2 REG_SYS_STATUS1				(Offset 0x00F4) */
+
+#define BIT_AUTO_WLPON BIT(8)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_SYS_STATUS1				(Offset 0x00F4) */
+
+#define BIT_SYM_MCU_CLK_DIV2 BIT(8)
+
+#define BIT_SHIFT_SYM_OSC32K_LDO_V18ADJ 8
+#define BIT_MASK_SYM_OSC32K_LDO_V18ADJ 0xf
+#define BIT_SYM_OSC32K_LDO_V18ADJ(x)                                           \
+	(((x) & BIT_MASK_SYM_OSC32K_LDO_V18ADJ)                                \
+	 << BIT_SHIFT_SYM_OSC32K_LDO_V18ADJ)
+#define BITS_SYM_OSC32K_LDO_V18ADJ                                             \
+	(BIT_MASK_SYM_OSC32K_LDO_V18ADJ << BIT_SHIFT_SYM_OSC32K_LDO_V18ADJ)
+#define BIT_CLEAR_SYM_OSC32K_LDO_V18ADJ(x) ((x) & (~BITS_SYM_OSC32K_LDO_V18ADJ))
+#define BIT_GET_SYM_OSC32K_LDO_V18ADJ(x)                                       \
+	(((x) >> BIT_SHIFT_SYM_OSC32K_LDO_V18ADJ) &                            \
+	 BIT_MASK_SYM_OSC32K_LDO_V18ADJ)
+#define BIT_SET_SYM_OSC32K_LDO_V18ADJ(x, v)                                    \
+	(BIT_CLEAR_SYM_OSC32K_LDO_V18ADJ(x) | BIT_SYM_OSC32K_LDO_V18ADJ(v))
+
+#define BIT_SHIFT_HOST_WAKE_WL_LOC 8
+#define BIT_MASK_HOST_WAKE_WL_LOC 0x3
+#define BIT_HOST_WAKE_WL_LOC(x)                                                \
+	(((x) & BIT_MASK_HOST_WAKE_WL_LOC) << BIT_SHIFT_HOST_WAKE_WL_LOC)
+#define BITS_HOST_WAKE_WL_LOC                                                  \
+	(BIT_MASK_HOST_WAKE_WL_LOC << BIT_SHIFT_HOST_WAKE_WL_LOC)
+#define BIT_CLEAR_HOST_WAKE_WL_LOC(x) ((x) & (~BITS_HOST_WAKE_WL_LOC))
+#define BIT_GET_HOST_WAKE_WL_LOC(x)                                            \
+	(((x) >> BIT_SHIFT_HOST_WAKE_WL_LOC) & BIT_MASK_HOST_WAKE_WL_LOC)
+#define BIT_SET_HOST_WAKE_WL_LOC(x, v)                                         \
+	(BIT_CLEAR_HOST_WAKE_WL_LOC(x) | BIT_HOST_WAKE_WL_LOC(v))
+
+#define BIT_SHIFT_SW_GPIO_B_OE2 8
+#define BIT_MASK_SW_GPIO_B_OE2 0xff
+#define BIT_SW_GPIO_B_OE2(x)                                                   \
+	(((x) & BIT_MASK_SW_GPIO_B_OE2) << BIT_SHIFT_SW_GPIO_B_OE2)
+#define BITS_SW_GPIO_B_OE2 (BIT_MASK_SW_GPIO_B_OE2 << BIT_SHIFT_SW_GPIO_B_OE2)
+#define BIT_CLEAR_SW_GPIO_B_OE2(x) ((x) & (~BITS_SW_GPIO_B_OE2))
+#define BIT_GET_SW_GPIO_B_OE2(x)                                               \
+	(((x) >> BIT_SHIFT_SW_GPIO_B_OE2) & BIT_MASK_SW_GPIO_B_OE2)
+#define BIT_SET_SW_GPIO_B_OE2(x, v)                                            \
+	(BIT_CLEAR_SW_GPIO_B_OE2(x) | BIT_SW_GPIO_B_OE2(v))
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_SYS_STATUS1				(Offset 0x00F4) */
+
+#define BIT_SHIFT_TRAP_ICFG 8
+#define BIT_MASK_TRAP_ICFG 0xf
+#define BIT_TRAP_ICFG(x) (((x) & BIT_MASK_TRAP_ICFG) << BIT_SHIFT_TRAP_ICFG)
+#define BITS_TRAP_ICFG (BIT_MASK_TRAP_ICFG << BIT_SHIFT_TRAP_ICFG)
+#define BIT_CLEAR_TRAP_ICFG(x) ((x) & (~BITS_TRAP_ICFG))
+#define BIT_GET_TRAP_ICFG(x) (((x) >> BIT_SHIFT_TRAP_ICFG) & BIT_MASK_TRAP_ICFG)
+#define BIT_SET_TRAP_ICFG(x, v) (BIT_CLEAR_TRAP_ICFG(x) | BIT_TRAP_ICFG(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8881A_SUPPORT)
+
+/* 2 REG_SYS_STATUS1				(Offset 0x00F4) */
+
+#define BIT_WL_MODE BIT(7)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_SYS_STATUS1				(Offset 0x00F4) */
+
+#define BIT_SPI_FLASH_LOC BIT(7)
+
+#define BIT_SHIFT_WLPHY_DBG_LOC 7
+#define BIT_MASK_WLPHY_DBG_LOC 0x3
+#define BIT_WLPHY_DBG_LOC(x)                                                   \
+	(((x) & BIT_MASK_WLPHY_DBG_LOC) << BIT_SHIFT_WLPHY_DBG_LOC)
+#define BITS_WLPHY_DBG_LOC (BIT_MASK_WLPHY_DBG_LOC << BIT_SHIFT_WLPHY_DBG_LOC)
+#define BIT_CLEAR_WLPHY_DBG_LOC(x) ((x) & (~BITS_WLPHY_DBG_LOC))
+#define BIT_GET_WLPHY_DBG_LOC(x)                                               \
+	(((x) >> BIT_SHIFT_WLPHY_DBG_LOC) & BIT_MASK_WLPHY_DBG_LOC)
+#define BIT_SET_WLPHY_DBG_LOC(x, v)                                            \
+	(BIT_CLEAR_WLPHY_DBG_LOC(x) | BIT_WLPHY_DBG_LOC(v))
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_SYS_STATUS1				(Offset 0x00F4) */
+
+#define BIT_WLAN_ID BIT(7)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8881A_SUPPORT)
+
+/* 2 REG_SYS_STATUS1				(Offset 0x00F4) */
+
+#define BIT_PKG_SEL_HCI BIT(6)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_SYS_STATUS1				(Offset 0x00F4) */
+
+#define BIT_SHIFT_SYM_OSC32K_COMP_LOAD_CUR 6
+#define BIT_MASK_SYM_OSC32K_COMP_LOAD_CUR 0x3
+#define BIT_SYM_OSC32K_COMP_LOAD_CUR(x)                                        \
+	(((x) & BIT_MASK_SYM_OSC32K_COMP_LOAD_CUR)                             \
+	 << BIT_SHIFT_SYM_OSC32K_COMP_LOAD_CUR)
+#define BITS_SYM_OSC32K_COMP_LOAD_CUR                                          \
+	(BIT_MASK_SYM_OSC32K_COMP_LOAD_CUR                                     \
+	 << BIT_SHIFT_SYM_OSC32K_COMP_LOAD_CUR)
+#define BIT_CLEAR_SYM_OSC32K_COMP_LOAD_CUR(x)                                  \
+	((x) & (~BITS_SYM_OSC32K_COMP_LOAD_CUR))
+#define BIT_GET_SYM_OSC32K_COMP_LOAD_CUR(x)                                    \
+	(((x) >> BIT_SHIFT_SYM_OSC32K_COMP_LOAD_CUR) &                         \
+	 BIT_MASK_SYM_OSC32K_COMP_LOAD_CUR)
+#define BIT_SET_SYM_OSC32K_COMP_LOAD_CUR(x, v)                                 \
+	(BIT_CLEAR_SYM_OSC32K_COMP_LOAD_CUR(x) |                               \
+	 BIT_SYM_OSC32K_COMP_LOAD_CUR(v))
+
+#define BIT_WLGP_HW_DIS_LOC_BIT1 BIT(6)
+#define BIT_XTAL_CKOUT_LOC BIT(6)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_SYS_STATUS1				(Offset 0x00F4) */
+
+#define BIT_ALDN BIT(6)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_SYS_STATUS1				(Offset 0x00F4) */
+
+#define BIT_XTAL_CLKREQ_EN BIT(5)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_SYS_STATUS1				(Offset 0x00F4) */
+
+#define BIT_BTCOEX_CMDEN BIT(5)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_SYS_STATUS1				(Offset 0x00F4) */
+
+#define BIT_SHIFT_HCI_SEL 4
+#define BIT_MASK_HCI_SEL 0x3
+#define BIT_HCI_SEL(x) (((x) & BIT_MASK_HCI_SEL) << BIT_SHIFT_HCI_SEL)
+#define BITS_HCI_SEL (BIT_MASK_HCI_SEL << BIT_SHIFT_HCI_SEL)
+#define BIT_CLEAR_HCI_SEL(x) ((x) & (~BITS_HCI_SEL))
+#define BIT_GET_HCI_SEL(x) (((x) >> BIT_SHIFT_HCI_SEL) & BIT_MASK_HCI_SEL)
+#define BIT_SET_HCI_SEL(x, v) (BIT_CLEAR_HCI_SEL(x) | BIT_HCI_SEL(v))
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_SYS_STATUS1				(Offset 0x00F4) */
+
+#define BIT_SYM_BOOT_SEL BIT(4)
+
+#define BIT_SHIFT_SYM_OSC32K_COMP_LATCH_CUR 4
+#define BIT_MASK_SYM_OSC32K_COMP_LATCH_CUR 0x3
+#define BIT_SYM_OSC32K_COMP_LATCH_CUR(x)                                       \
+	(((x) & BIT_MASK_SYM_OSC32K_COMP_LATCH_CUR)                            \
+	 << BIT_SHIFT_SYM_OSC32K_COMP_LATCH_CUR)
+#define BITS_SYM_OSC32K_COMP_LATCH_CUR                                         \
+	(BIT_MASK_SYM_OSC32K_COMP_LATCH_CUR                                    \
+	 << BIT_SHIFT_SYM_OSC32K_COMP_LATCH_CUR)
+#define BIT_CLEAR_SYM_OSC32K_COMP_LATCH_CUR(x)                                 \
+	((x) & (~BITS_SYM_OSC32K_COMP_LATCH_CUR))
+#define BIT_GET_SYM_OSC32K_COMP_LATCH_CUR(x)                                   \
+	(((x) >> BIT_SHIFT_SYM_OSC32K_COMP_LATCH_CUR) &                        \
+	 BIT_MASK_SYM_OSC32K_COMP_LATCH_CUR)
+#define BIT_SET_SYM_OSC32K_COMP_LATCH_CUR(x, v)                                \
+	(BIT_CLEAR_SYM_OSC32K_COMP_LATCH_CUR(x) |                              \
+	 BIT_SYM_OSC32K_COMP_LATCH_CUR(v))
+
+#define BIT_SHIFT_CRC16_CHECK_MAXIMUM_ADDRESS_BOUNDARY 4
+#define BIT_MASK_CRC16_CHECK_MAXIMUM_ADDRESS_BOUNDARY 0x3ff
+#define BIT_CRC16_CHECK_MAXIMUM_ADDRESS_BOUNDARY(x)                            \
+	(((x) & BIT_MASK_CRC16_CHECK_MAXIMUM_ADDRESS_BOUNDARY)                 \
+	 << BIT_SHIFT_CRC16_CHECK_MAXIMUM_ADDRESS_BOUNDARY)
+#define BITS_CRC16_CHECK_MAXIMUM_ADDRESS_BOUNDARY                              \
+	(BIT_MASK_CRC16_CHECK_MAXIMUM_ADDRESS_BOUNDARY                         \
+	 << BIT_SHIFT_CRC16_CHECK_MAXIMUM_ADDRESS_BOUNDARY)
+#define BIT_CLEAR_CRC16_CHECK_MAXIMUM_ADDRESS_BOUNDARY(x)                      \
+	((x) & (~BITS_CRC16_CHECK_MAXIMUM_ADDRESS_BOUNDARY))
+#define BIT_GET_CRC16_CHECK_MAXIMUM_ADDRESS_BOUNDARY(x)                        \
+	(((x) >> BIT_SHIFT_CRC16_CHECK_MAXIMUM_ADDRESS_BOUNDARY) &             \
+	 BIT_MASK_CRC16_CHECK_MAXIMUM_ADDRESS_BOUNDARY)
+#define BIT_SET_CRC16_CHECK_MAXIMUM_ADDRESS_BOUNDARY(x, v)                     \
+	(BIT_CLEAR_CRC16_CHECK_MAXIMUM_ADDRESS_BOUNDARY(x) |                   \
+	 BIT_CRC16_CHECK_MAXIMUM_ADDRESS_BOUNDARY(v))
+
+#define BIT_HOST_WAKE_WL_EN BIT(4)
+
+#define BIT_SHIFT_XTAL_CLKREQ_LOC 4
+#define BIT_MASK_XTAL_CLKREQ_LOC 0x3
+#define BIT_XTAL_CLKREQ_LOC(x)                                                 \
+	(((x) & BIT_MASK_XTAL_CLKREQ_LOC) << BIT_SHIFT_XTAL_CLKREQ_LOC)
+#define BITS_XTAL_CLKREQ_LOC                                                   \
+	(BIT_MASK_XTAL_CLKREQ_LOC << BIT_SHIFT_XTAL_CLKREQ_LOC)
+#define BIT_CLEAR_XTAL_CLKREQ_LOC(x) ((x) & (~BITS_XTAL_CLKREQ_LOC))
+#define BIT_GET_XTAL_CLKREQ_LOC(x)                                             \
+	(((x) >> BIT_SHIFT_XTAL_CLKREQ_LOC) & BIT_MASK_XTAL_CLKREQ_LOC)
+#define BIT_SET_XTAL_CLKREQ_LOC(x, v)                                          \
+	(BIT_CLEAR_XTAL_CLKREQ_LOC(x) | BIT_XTAL_CLKREQ_LOC(v))
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_SYS_STATUS1				(Offset 0x00F4) */
+
+#define BIT_BT_EN BIT(4)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_SYS_STATUS1				(Offset 0x00F4) */
+
+#define BIT_BTGP_MCM_UART_EN BIT(3)
+#define BIT_WLGP_UART_LOC BIT(3)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_SYS_STATUS1				(Offset 0x00F4) */
+
+#define BIT_SHIFT_PAD_HCI_SEL_V2 3
+#define BIT_MASK_PAD_HCI_SEL_V2 0x3
+#define BIT_PAD_HCI_SEL_V2(x)                                                  \
+	(((x) & BIT_MASK_PAD_HCI_SEL_V2) << BIT_SHIFT_PAD_HCI_SEL_V2)
+#define BITS_PAD_HCI_SEL_V2                                                    \
+	(BIT_MASK_PAD_HCI_SEL_V2 << BIT_SHIFT_PAD_HCI_SEL_V2)
+#define BIT_CLEAR_PAD_HCI_SEL_V2(x) ((x) & (~BITS_PAD_HCI_SEL_V2))
+#define BIT_GET_PAD_HCI_SEL_V2(x)                                              \
+	(((x) >> BIT_SHIFT_PAD_HCI_SEL_V2) & BIT_MASK_PAD_HCI_SEL_V2)
+#define BIT_SET_PAD_HCI_SEL_V2(x, v)                                           \
+	(BIT_CLEAR_PAD_HCI_SEL_V2(x) | BIT_PAD_HCI_SEL_V2(v))
+
+#endif
+
+#if (HALMAC_8822B_SUPPORT)
+
+/* 2 REG_SYS_STATUS1				(Offset 0x00F4) */
+
+#define BIT_SHIFT_PAD_HCI_SEL_V1 3
+#define BIT_MASK_PAD_HCI_SEL_V1 0x7
+#define BIT_PAD_HCI_SEL_V1(x)                                                  \
+	(((x) & BIT_MASK_PAD_HCI_SEL_V1) << BIT_SHIFT_PAD_HCI_SEL_V1)
+#define BITS_PAD_HCI_SEL_V1                                                    \
+	(BIT_MASK_PAD_HCI_SEL_V1 << BIT_SHIFT_PAD_HCI_SEL_V1)
+#define BIT_CLEAR_PAD_HCI_SEL_V1(x) ((x) & (~BITS_PAD_HCI_SEL_V1))
+#define BIT_GET_PAD_HCI_SEL_V1(x)                                              \
+	(((x) >> BIT_SHIFT_PAD_HCI_SEL_V1) & BIT_MASK_PAD_HCI_SEL_V1)
+#define BIT_SET_PAD_HCI_SEL_V1(x, v)                                           \
+	(BIT_CLEAR_PAD_HCI_SEL_V1(x) | BIT_PAD_HCI_SEL_V1(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_SYS_STATUS1				(Offset 0x00F4) */
+
+#define BIT_SHIFT_PAD_HCI_SEL 2
+#define BIT_MASK_PAD_HCI_SEL 0x3
+#define BIT_PAD_HCI_SEL(x)                                                     \
+	(((x) & BIT_MASK_PAD_HCI_SEL) << BIT_SHIFT_PAD_HCI_SEL)
+#define BITS_PAD_HCI_SEL (BIT_MASK_PAD_HCI_SEL << BIT_SHIFT_PAD_HCI_SEL)
+#define BIT_CLEAR_PAD_HCI_SEL(x) ((x) & (~BITS_PAD_HCI_SEL))
+#define BIT_GET_PAD_HCI_SEL(x)                                                 \
+	(((x) >> BIT_SHIFT_PAD_HCI_SEL) & BIT_MASK_PAD_HCI_SEL)
+#define BIT_SET_PAD_HCI_SEL(x, v)                                              \
+	(BIT_CLEAR_PAD_HCI_SEL(x) | BIT_PAD_HCI_SEL(v))
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_SYS_STATUS1				(Offset 0x00F4) */
+
+#define BIT_SHIFT_SYM_OSC32K_COMP_GM_CUR 2
+#define BIT_MASK_SYM_OSC32K_COMP_GM_CUR 0x3
+#define BIT_SYM_OSC32K_COMP_GM_CUR(x)                                          \
+	(((x) & BIT_MASK_SYM_OSC32K_COMP_GM_CUR)                               \
+	 << BIT_SHIFT_SYM_OSC32K_COMP_GM_CUR)
+#define BITS_SYM_OSC32K_COMP_GM_CUR                                            \
+	(BIT_MASK_SYM_OSC32K_COMP_GM_CUR << BIT_SHIFT_SYM_OSC32K_COMP_GM_CUR)
+#define BIT_CLEAR_SYM_OSC32K_COMP_GM_CUR(x)                                    \
+	((x) & (~BITS_SYM_OSC32K_COMP_GM_CUR))
+#define BIT_GET_SYM_OSC32K_COMP_GM_CUR(x)                                      \
+	(((x) >> BIT_SHIFT_SYM_OSC32K_COMP_GM_CUR) &                           \
+	 BIT_MASK_SYM_OSC32K_COMP_GM_CUR)
+#define BIT_SET_SYM_OSC32K_COMP_GM_CUR(x, v)                                   \
+	(BIT_CLEAR_SYM_OSC32K_COMP_GM_CUR(x) | BIT_SYM_OSC32K_COMP_GM_CUR(v))
+
+#define BIT_WLGP_MCM_COEXFEN BIT(2)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_SYS_STATUS1				(Offset 0x00F4) */
+
+#define BIT_SHIFT_HCI_SEL_V2 2
+#define BIT_MASK_HCI_SEL_V2 0x3
+#define BIT_HCI_SEL_V2(x) (((x) & BIT_MASK_HCI_SEL_V2) << BIT_SHIFT_HCI_SEL_V2)
+#define BITS_HCI_SEL_V2 (BIT_MASK_HCI_SEL_V2 << BIT_SHIFT_HCI_SEL_V2)
+#define BIT_CLEAR_HCI_SEL_V2(x) ((x) & (~BITS_HCI_SEL_V2))
+#define BIT_GET_HCI_SEL_V2(x)                                                  \
+	(((x) >> BIT_SHIFT_HCI_SEL_V2) & BIT_MASK_HCI_SEL_V2)
+#define BIT_SET_HCI_SEL_V2(x, v) (BIT_CLEAR_HCI_SEL_V2(x) | BIT_HCI_SEL_V2(v))
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_SYS_STATUS1				(Offset 0x00F4) */
+
+#define BIT_BT_COEX_MCM_MBOX BIT(1)
+
+#define BIT_SHIFT_BTGP_WAKE_HST_LOC 1
+#define BIT_MASK_BTGP_WAKE_HST_LOC 0x3
+#define BIT_BTGP_WAKE_HST_LOC(x)                                               \
+	(((x) & BIT_MASK_BTGP_WAKE_HST_LOC) << BIT_SHIFT_BTGP_WAKE_HST_LOC)
+#define BITS_BTGP_WAKE_HST_LOC                                                 \
+	(BIT_MASK_BTGP_WAKE_HST_LOC << BIT_SHIFT_BTGP_WAKE_HST_LOC)
+#define BIT_CLEAR_BTGP_WAKE_HST_LOC(x) ((x) & (~BITS_BTGP_WAKE_HST_LOC))
+#define BIT_GET_BTGP_WAKE_HST_LOC(x)                                           \
+	(((x) >> BIT_SHIFT_BTGP_WAKE_HST_LOC) & BIT_MASK_BTGP_WAKE_HST_LOC)
+#define BIT_SET_BTGP_WAKE_HST_LOC(x, v)                                        \
+	(BIT_CLEAR_BTGP_WAKE_HST_LOC(x) | BIT_BTGP_WAKE_HST_LOC(v))
+
+#define BIT_SYM_HCI_TADMA_ALLOW BIT(1)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_SYS_STATUS1				(Offset 0x00F4) */
+
+#define BIT_TST_MOD_SEL BIT(1)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8881A_SUPPORT)
+
+/* 2 REG_SYS_STATUS1				(Offset 0x00F4) */
+
+#define BIT_SHIFT_EFS_HCI_SEL 0
+#define BIT_MASK_EFS_HCI_SEL 0x3
+#define BIT_EFS_HCI_SEL(x)                                                     \
+	(((x) & BIT_MASK_EFS_HCI_SEL) << BIT_SHIFT_EFS_HCI_SEL)
+#define BITS_EFS_HCI_SEL (BIT_MASK_EFS_HCI_SEL << BIT_SHIFT_EFS_HCI_SEL)
+#define BIT_CLEAR_EFS_HCI_SEL(x) ((x) & (~BITS_EFS_HCI_SEL))
+#define BIT_GET_EFS_HCI_SEL(x)                                                 \
+	(((x) >> BIT_SHIFT_EFS_HCI_SEL) & BIT_MASK_EFS_HCI_SEL)
+#define BIT_SET_EFS_HCI_SEL(x, v)                                              \
+	(BIT_CLEAR_EFS_HCI_SEL(x) | BIT_EFS_HCI_SEL(v))
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_SYS_STATUS1				(Offset 0x00F4) */
+
+#define BIT_SYM_BOOT_CFG BIT(0)
+
+#define BIT_SHIFT_SYM_SPIC_BOOT_EXT_ADDR 0
+#define BIT_MASK_SYM_SPIC_BOOT_EXT_ADDR 0xffff
+#define BIT_SYM_SPIC_BOOT_EXT_ADDR(x)                                          \
+	(((x) & BIT_MASK_SYM_SPIC_BOOT_EXT_ADDR)                               \
+	 << BIT_SHIFT_SYM_SPIC_BOOT_EXT_ADDR)
+#define BITS_SYM_SPIC_BOOT_EXT_ADDR                                            \
+	(BIT_MASK_SYM_SPIC_BOOT_EXT_ADDR << BIT_SHIFT_SYM_SPIC_BOOT_EXT_ADDR)
+#define BIT_CLEAR_SYM_SPIC_BOOT_EXT_ADDR(x)                                    \
+	((x) & (~BITS_SYM_SPIC_BOOT_EXT_ADDR))
+#define BIT_GET_SYM_SPIC_BOOT_EXT_ADDR(x)                                      \
+	(((x) >> BIT_SHIFT_SYM_SPIC_BOOT_EXT_ADDR) &                           \
+	 BIT_MASK_SYM_SPIC_BOOT_EXT_ADDR)
+#define BIT_SET_SYM_SPIC_BOOT_EXT_ADDR(x, v)                                   \
+	(BIT_CLEAR_SYM_SPIC_BOOT_EXT_ADDR(x) | BIT_SYM_SPIC_BOOT_EXT_ADDR(v))
+
+#define BIT_SHIFT_SYM_OSC32K_FREQSEL 0
+#define BIT_MASK_SYM_OSC32K_FREQSEL 0x3
+#define BIT_SYM_OSC32K_FREQSEL(x)                                              \
+	(((x) & BIT_MASK_SYM_OSC32K_FREQSEL) << BIT_SHIFT_SYM_OSC32K_FREQSEL)
+#define BITS_SYM_OSC32K_FREQSEL                                                \
+	(BIT_MASK_SYM_OSC32K_FREQSEL << BIT_SHIFT_SYM_OSC32K_FREQSEL)
+#define BIT_CLEAR_SYM_OSC32K_FREQSEL(x) ((x) & (~BITS_SYM_OSC32K_FREQSEL))
+#define BIT_GET_SYM_OSC32K_FREQSEL(x)                                          \
+	(((x) >> BIT_SHIFT_SYM_OSC32K_FREQSEL) & BIT_MASK_SYM_OSC32K_FREQSEL)
+#define BIT_SET_SYM_OSC32K_FREQSEL(x, v)                                       \
+	(BIT_CLEAR_SYM_OSC32K_FREQSEL(x) | BIT_SYM_OSC32K_FREQSEL(v))
+
+#define BIT_CRC16_CHECK_ENABLE BIT(0)
+#define BIT_SW_GPIO_FUNC BIT(0)
+#define BIT_BTGP_WAKE_BT_LOC BIT(0)
+
+#define BIT_SHIFT_SW_GPIO_A_OUT 0
+#define BIT_MASK_SW_GPIO_A_OUT 0xffffffffL
+#define BIT_SW_GPIO_A_OUT(x)                                                   \
+	(((x) & BIT_MASK_SW_GPIO_A_OUT) << BIT_SHIFT_SW_GPIO_A_OUT)
+#define BITS_SW_GPIO_A_OUT (BIT_MASK_SW_GPIO_A_OUT << BIT_SHIFT_SW_GPIO_A_OUT)
+#define BIT_CLEAR_SW_GPIO_A_OUT(x) ((x) & (~BITS_SW_GPIO_A_OUT))
+#define BIT_GET_SW_GPIO_A_OUT(x)                                               \
+	(((x) >> BIT_SHIFT_SW_GPIO_A_OUT) & BIT_MASK_SW_GPIO_A_OUT)
+#define BIT_SET_SW_GPIO_A_OUT(x, v)                                            \
+	(BIT_CLEAR_SW_GPIO_A_OUT(x) | BIT_SW_GPIO_A_OUT(v))
+
+#define BIT_SHIFT_SW_GPIO_A_OEN 0
+#define BIT_MASK_SW_GPIO_A_OEN 0xffffffffL
+#define BIT_SW_GPIO_A_OEN(x)                                                   \
+	(((x) & BIT_MASK_SW_GPIO_A_OEN) << BIT_SHIFT_SW_GPIO_A_OEN)
+#define BITS_SW_GPIO_A_OEN (BIT_MASK_SW_GPIO_A_OEN << BIT_SHIFT_SW_GPIO_A_OEN)
+#define BIT_CLEAR_SW_GPIO_A_OEN(x) ((x) & (~BITS_SW_GPIO_A_OEN))
+#define BIT_GET_SW_GPIO_A_OEN(x)                                               \
+	(((x) >> BIT_SHIFT_SW_GPIO_A_OEN) & BIT_MASK_SW_GPIO_A_OEN)
+#define BIT_SET_SW_GPIO_A_OEN(x, v)                                            \
+	(BIT_CLEAR_SW_GPIO_A_OEN(x) | BIT_SW_GPIO_A_OEN(v))
+
+#define BIT_SHIFT_SW_GPIO_A_OE2 0
+#define BIT_MASK_SW_GPIO_A_OE2 0xffffffffL
+#define BIT_SW_GPIO_A_OE2(x)                                                   \
+	(((x) & BIT_MASK_SW_GPIO_A_OE2) << BIT_SHIFT_SW_GPIO_A_OE2)
+#define BITS_SW_GPIO_A_OE2 (BIT_MASK_SW_GPIO_A_OE2 << BIT_SHIFT_SW_GPIO_A_OE2)
+#define BIT_CLEAR_SW_GPIO_A_OE2(x) ((x) & (~BITS_SW_GPIO_A_OE2))
+#define BIT_GET_SW_GPIO_A_OE2(x)                                               \
+	(((x) >> BIT_SHIFT_SW_GPIO_A_OE2) & BIT_MASK_SW_GPIO_A_OE2)
+#define BIT_SET_SW_GPIO_A_OE2(x, v)                                            \
+	(BIT_CLEAR_SW_GPIO_A_OE2(x) | BIT_SW_GPIO_A_OE2(v))
+
+#define BIT_SHIFT_SW_GPIO_A_PU 0
+#define BIT_MASK_SW_GPIO_A_PU 0xffffffffL
+#define BIT_SW_GPIO_A_PU(x)                                                    \
+	(((x) & BIT_MASK_SW_GPIO_A_PU) << BIT_SHIFT_SW_GPIO_A_PU)
+#define BITS_SW_GPIO_A_PU (BIT_MASK_SW_GPIO_A_PU << BIT_SHIFT_SW_GPIO_A_PU)
+#define BIT_CLEAR_SW_GPIO_A_PU(x) ((x) & (~BITS_SW_GPIO_A_PU))
+#define BIT_GET_SW_GPIO_A_PU(x)                                                \
+	(((x) >> BIT_SHIFT_SW_GPIO_A_PU) & BIT_MASK_SW_GPIO_A_PU)
+#define BIT_SET_SW_GPIO_A_PU(x, v)                                             \
+	(BIT_CLEAR_SW_GPIO_A_PU(x) | BIT_SW_GPIO_A_PU(v))
+
+#define BIT_SHIFT_SW_GPIO_A_PD 0
+#define BIT_MASK_SW_GPIO_A_PD 0xffffffffL
+#define BIT_SW_GPIO_A_PD(x)                                                    \
+	(((x) & BIT_MASK_SW_GPIO_A_PD) << BIT_SHIFT_SW_GPIO_A_PD)
+#define BITS_SW_GPIO_A_PD (BIT_MASK_SW_GPIO_A_PD << BIT_SHIFT_SW_GPIO_A_PD)
+#define BIT_CLEAR_SW_GPIO_A_PD(x) ((x) & (~BITS_SW_GPIO_A_PD))
+#define BIT_GET_SW_GPIO_A_PD(x)                                                \
+	(((x) >> BIT_SHIFT_SW_GPIO_A_PD) & BIT_MASK_SW_GPIO_A_PD)
+#define BIT_SET_SW_GPIO_A_PD(x, v)                                             \
+	(BIT_CLEAR_SW_GPIO_A_PD(x) | BIT_SW_GPIO_A_PD(v))
+
+#define BIT_SHIFT_SW_GPIO_A_IN 0
+#define BIT_MASK_SW_GPIO_A_IN 0xffffffffL
+#define BIT_SW_GPIO_A_IN(x)                                                    \
+	(((x) & BIT_MASK_SW_GPIO_A_IN) << BIT_SHIFT_SW_GPIO_A_IN)
+#define BITS_SW_GPIO_A_IN (BIT_MASK_SW_GPIO_A_IN << BIT_SHIFT_SW_GPIO_A_IN)
+#define BIT_CLEAR_SW_GPIO_A_IN(x) ((x) & (~BITS_SW_GPIO_A_IN))
+#define BIT_GET_SW_GPIO_A_IN(x)                                                \
+	(((x) >> BIT_SHIFT_SW_GPIO_A_IN) & BIT_MASK_SW_GPIO_A_IN)
+#define BIT_SET_SW_GPIO_A_IN(x, v)                                             \
+	(BIT_CLEAR_SW_GPIO_A_IN(x) | BIT_SW_GPIO_A_IN(v))
+
+#define BIT_SHIFT_SW_GPIO_B_OEN 0
+#define BIT_MASK_SW_GPIO_B_OEN 0xff
+#define BIT_SW_GPIO_B_OEN(x)                                                   \
+	(((x) & BIT_MASK_SW_GPIO_B_OEN) << BIT_SHIFT_SW_GPIO_B_OEN)
+#define BITS_SW_GPIO_B_OEN (BIT_MASK_SW_GPIO_B_OEN << BIT_SHIFT_SW_GPIO_B_OEN)
+#define BIT_CLEAR_SW_GPIO_B_OEN(x) ((x) & (~BITS_SW_GPIO_B_OEN))
+#define BIT_GET_SW_GPIO_B_OEN(x)                                               \
+	(((x) >> BIT_SHIFT_SW_GPIO_B_OEN) & BIT_MASK_SW_GPIO_B_OEN)
+#define BIT_SET_SW_GPIO_B_OEN(x, v)                                            \
+	(BIT_CLEAR_SW_GPIO_B_OEN(x) | BIT_SW_GPIO_B_OEN(v))
+
+#define BIT_SHIFT_SW_GPIO_B_OUT 0
+#define BIT_MASK_SW_GPIO_B_OUT 0xff
+#define BIT_SW_GPIO_B_OUT(x)                                                   \
+	(((x) & BIT_MASK_SW_GPIO_B_OUT) << BIT_SHIFT_SW_GPIO_B_OUT)
+#define BITS_SW_GPIO_B_OUT (BIT_MASK_SW_GPIO_B_OUT << BIT_SHIFT_SW_GPIO_B_OUT)
+#define BIT_CLEAR_SW_GPIO_B_OUT(x) ((x) & (~BITS_SW_GPIO_B_OUT))
+#define BIT_GET_SW_GPIO_B_OUT(x)                                               \
+	(((x) >> BIT_SHIFT_SW_GPIO_B_OUT) & BIT_MASK_SW_GPIO_B_OUT)
+#define BIT_SET_SW_GPIO_B_OUT(x, v)                                            \
+	(BIT_CLEAR_SW_GPIO_B_OUT(x) | BIT_SW_GPIO_B_OUT(v))
+
+#define BIT_SYM_FW_CTL_HCI_TXDMA_EN BIT(0)
+
+#define BIT_SHIFT_TDE_H2C_RD_ADDR 0
+#define BIT_MASK_TDE_H2C_RD_ADDR 0x3ffff
+#define BIT_TDE_H2C_RD_ADDR(x)                                                 \
+	(((x) & BIT_MASK_TDE_H2C_RD_ADDR) << BIT_SHIFT_TDE_H2C_RD_ADDR)
+#define BITS_TDE_H2C_RD_ADDR                                                   \
+	(BIT_MASK_TDE_H2C_RD_ADDR << BIT_SHIFT_TDE_H2C_RD_ADDR)
+#define BIT_CLEAR_TDE_H2C_RD_ADDR(x) ((x) & (~BITS_TDE_H2C_RD_ADDR))
+#define BIT_GET_TDE_H2C_RD_ADDR(x)                                             \
+	(((x) >> BIT_SHIFT_TDE_H2C_RD_ADDR) & BIT_MASK_TDE_H2C_RD_ADDR)
+#define BIT_SET_TDE_H2C_RD_ADDR(x, v)                                          \
+	(BIT_CLEAR_TDE_H2C_RD_ADDR(x) | BIT_TDE_H2C_RD_ADDR(v))
+
+#define BIT_SHIFT_TDE_H2C_WR_ADDR 0
+#define BIT_MASK_TDE_H2C_WR_ADDR 0x3ffff
+#define BIT_TDE_H2C_WR_ADDR(x)                                                 \
+	(((x) & BIT_MASK_TDE_H2C_WR_ADDR) << BIT_SHIFT_TDE_H2C_WR_ADDR)
+#define BITS_TDE_H2C_WR_ADDR                                                   \
+	(BIT_MASK_TDE_H2C_WR_ADDR << BIT_SHIFT_TDE_H2C_WR_ADDR)
+#define BIT_CLEAR_TDE_H2C_WR_ADDR(x) ((x) & (~BITS_TDE_H2C_WR_ADDR))
+#define BIT_GET_TDE_H2C_WR_ADDR(x)                                             \
+	(((x) >> BIT_SHIFT_TDE_H2C_WR_ADDR) & BIT_MASK_TDE_H2C_WR_ADDR)
+#define BIT_SET_TDE_H2C_WR_ADDR(x, v)                                          \
+	(BIT_CLEAR_TDE_H2C_WR_ADDR(x) | BIT_TDE_H2C_WR_ADDR(v))
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_SYS_STATUS1				(Offset 0x00F4) */
+
+#define BIT_SHIFT_EFS_HCI_SEL_V1 0
+#define BIT_MASK_EFS_HCI_SEL_V1 0x7
+#define BIT_EFS_HCI_SEL_V1(x)                                                  \
+	(((x) & BIT_MASK_EFS_HCI_SEL_V1) << BIT_SHIFT_EFS_HCI_SEL_V1)
+#define BITS_EFS_HCI_SEL_V1                                                    \
+	(BIT_MASK_EFS_HCI_SEL_V1 << BIT_SHIFT_EFS_HCI_SEL_V1)
+#define BIT_CLEAR_EFS_HCI_SEL_V1(x) ((x) & (~BITS_EFS_HCI_SEL_V1))
+#define BIT_GET_EFS_HCI_SEL_V1(x)                                              \
+	(((x) >> BIT_SHIFT_EFS_HCI_SEL_V1) & BIT_MASK_EFS_HCI_SEL_V1)
+#define BIT_SET_EFS_HCI_SEL_V1(x, v)                                           \
+	(BIT_CLEAR_EFS_HCI_SEL_V1(x) | BIT_EFS_HCI_SEL_V1(v))
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_SYS_STATUS1				(Offset 0x00F4) */
+
+#define BIT_PAD_HWPDB BIT(0)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_SYS_STATUS2				(Offset 0x00F8) */
+
+#define BIT_HIOE_ON_TIMEOUT BIT(23)
+#define BIT_SIC_ON_TIMEOUT BIT(22)
+#define BIT_CPU_ON_TIMEOUT BIT(21)
+#define BIT_HCI_ON_TIMEOUT BIT(20)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8881A_SUPPORT)
+
+/* 2 REG_SYS_STATUS2				(Offset 0x00F8) */
+
+#define BIT_SIO_ALDN BIT(19)
+#define BIT_USB_ALDN BIT(18)
+#define BIT_PCI_ALDN BIT(17)
+#define BIT_SYS_ALDN BIT(16)
+
+#define BIT_SHIFT_EPVID1 8
+#define BIT_MASK_EPVID1 0xff
+#define BIT_EPVID1(x) (((x) & BIT_MASK_EPVID1) << BIT_SHIFT_EPVID1)
+#define BITS_EPVID1 (BIT_MASK_EPVID1 << BIT_SHIFT_EPVID1)
+#define BIT_CLEAR_EPVID1(x) ((x) & (~BITS_EPVID1))
+#define BIT_GET_EPVID1(x) (((x) >> BIT_SHIFT_EPVID1) & BIT_MASK_EPVID1)
+#define BIT_SET_EPVID1(x, v) (BIT_CLEAR_EPVID1(x) | BIT_EPVID1(v))
+
+#define BIT_SHIFT_EPVID0 0
+#define BIT_MASK_EPVID0 0xff
+#define BIT_EPVID0(x) (((x) & BIT_MASK_EPVID0) << BIT_SHIFT_EPVID0)
+#define BITS_EPVID0 (BIT_MASK_EPVID0 << BIT_SHIFT_EPVID0)
+#define BIT_CLEAR_EPVID0(x) ((x) & (~BITS_EPVID0))
+#define BIT_GET_EPVID0(x) (((x) >> BIT_SHIFT_EPVID0) & BIT_MASK_EPVID0)
+#define BIT_SET_EPVID0(x, v) (BIT_CLEAR_EPVID0(x) | BIT_EPVID0(v))
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_SYS_CFG2				(Offset 0x00FC) */
+
+#define BIT_USB2_SEL_1 BIT(31)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_SYS_CFG2				(Offset 0x00FC) */
+
+#define BIT_USB2_SEL BIT(31)
+#define BIT_FEN_WLMAC_OFF BIT(31)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_SYS_CFG2				(Offset 0x00FC) */
+
+#define BIT_USB3PHY_RST BIT(30)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_SYS_CFG2				(Offset 0x00FC) */
+
+#define BIT_U3PHY_RST_V1 BIT(30)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_SYS_CFG2				(Offset 0x00FC) */
+
+#define BIT_U3_TERM_DET BIT(29)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_SYS_CFG2				(Offset 0x00FC) */
+
+#define BIT_U3_TERM_DETECT BIT(29)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_SYS_CFG2				(Offset 0x00FC) */
+
+#define BIT_USB23_DBG_SEL BIT(24)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_SYS_CFG2				(Offset 0x00FC) */
+
+#define BIT_HCI_SEL_EMBEDDED BIT(8)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_SYS_CFG2				(Offset 0x00FC) */
+
+#define BIT_ISO_BB2PP BIT(7)
+#define BIT_ISO_DENG2PP BIT(6)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8881A_SUPPORT)
+
+/* 2 REG_SYS_CFG2				(Offset 0x00FC) */
+
+#define BIT_SHIFT_HW_ID 0
+#define BIT_MASK_HW_ID 0xff
+#define BIT_HW_ID(x) (((x) & BIT_MASK_HW_ID) << BIT_SHIFT_HW_ID)
+#define BITS_HW_ID (BIT_MASK_HW_ID << BIT_SHIFT_HW_ID)
+#define BIT_CLEAR_HW_ID(x) ((x) & (~BITS_HW_ID))
+#define BIT_GET_HW_ID(x) (((x) >> BIT_SHIFT_HW_ID) & BIT_MASK_HW_ID)
+#define BIT_SET_HW_ID(x, v) (BIT_CLEAR_HW_ID(x) | BIT_HW_ID(v))
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_SYS_CFG2				(Offset 0x00FC) */
+
+#define BIT_SHIFT_CHIPID 0
+#define BIT_MASK_CHIPID 0xff
+#define BIT_CHIPID(x) (((x) & BIT_MASK_CHIPID) << BIT_SHIFT_CHIPID)
+#define BITS_CHIPID (BIT_MASK_CHIPID << BIT_SHIFT_CHIPID)
+#define BIT_CLEAR_CHIPID(x) ((x) & (~BITS_CHIPID))
+#define BIT_GET_CHIPID(x) (((x) >> BIT_SHIFT_CHIPID) & BIT_MASK_CHIPID)
+#define BIT_SET_CHIPID(x, v) (BIT_CLEAR_CHIPID(x) | BIT_CHIPID(v))
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_CR					(Offset 0x0100) */
+
+#define BIT_BIST_H32BIT_SEL BIT(29)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_CR					(Offset 0x0100) */
+
+#define BIT_MACIO_TIMEOUT_EN BIT(29)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_CR					(Offset 0x0100) */
+
+#define BIT_SHIFT_LBMODE 24
+#define BIT_MASK_LBMODE 0x1f
+#define BIT_LBMODE(x) (((x) & BIT_MASK_LBMODE) << BIT_SHIFT_LBMODE)
+#define BITS_LBMODE (BIT_MASK_LBMODE << BIT_SHIFT_LBMODE)
+#define BIT_CLEAR_LBMODE(x) ((x) & (~BITS_LBMODE))
+#define BIT_GET_LBMODE(x) (((x) >> BIT_SHIFT_LBMODE) & BIT_MASK_LBMODE)
+#define BIT_SET_LBMODE(x, v) (BIT_CLEAR_LBMODE(x) | BIT_LBMODE(v))
+
+#define BIT_SHIFT_NETYPE1 18
+#define BIT_MASK_NETYPE1 0x3
+#define BIT_NETYPE1(x) (((x) & BIT_MASK_NETYPE1) << BIT_SHIFT_NETYPE1)
+#define BITS_NETYPE1 (BIT_MASK_NETYPE1 << BIT_SHIFT_NETYPE1)
+#define BIT_CLEAR_NETYPE1(x) ((x) & (~BITS_NETYPE1))
+#define BIT_GET_NETYPE1(x) (((x) >> BIT_SHIFT_NETYPE1) & BIT_MASK_NETYPE1)
+#define BIT_SET_NETYPE1(x, v) (BIT_CLEAR_NETYPE1(x) | BIT_NETYPE1(v))
+
+#define BIT_SHIFT_NETYPE0 16
+#define BIT_MASK_NETYPE0 0x3
+#define BIT_NETYPE0(x) (((x) & BIT_MASK_NETYPE0) << BIT_SHIFT_NETYPE0)
+#define BITS_NETYPE0 (BIT_MASK_NETYPE0 << BIT_SHIFT_NETYPE0)
+#define BIT_CLEAR_NETYPE0(x) ((x) & (~BITS_NETYPE0))
+#define BIT_GET_NETYPE0(x) (((x) >> BIT_SHIFT_NETYPE0) & BIT_MASK_NETYPE0)
+#define BIT_SET_NETYPE0(x, v) (BIT_CLEAR_NETYPE0(x) | BIT_NETYPE0(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_CR					(Offset 0x0100) */
+
+#define BIT_STAT_FUNC_RST BIT(13)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_CR					(Offset 0x0100) */
+
+#define BIT_COUNTER_STS_EN BIT(13)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_CR					(Offset 0x0100) */
+
+#define BIT_PTA_I2C_MBOX_EN BIT(12)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_CR					(Offset 0x0100) */
+
+#define BIT_I2C_MAILBOX_EN BIT(12)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_CR					(Offset 0x0100) */
+
+#define BIT_SHCUT_EN BIT(11)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_CR					(Offset 0x0100) */
+
+#define BIT_32K_CAL_TMR_EN BIT(10)
+#define BIT_MAC_SEC_EN BIT(9)
+#define BIT_ENSWBCN BIT(8)
+#define BIT_MACRXEN BIT(7)
+#define BIT_MACTXEN BIT(6)
+#define BIT_SCHEDULE_EN BIT(5)
+#define BIT_PROTOCOL_EN BIT(4)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_CR					(Offset 0x0100) */
+
+#define BIT_SHIFT_I2C_M_BUS_GNT_FW 4
+#define BIT_MASK_I2C_M_BUS_GNT_FW 0x7
+#define BIT_I2C_M_BUS_GNT_FW(x)                                                \
+	(((x) & BIT_MASK_I2C_M_BUS_GNT_FW) << BIT_SHIFT_I2C_M_BUS_GNT_FW)
+#define BITS_I2C_M_BUS_GNT_FW                                                  \
+	(BIT_MASK_I2C_M_BUS_GNT_FW << BIT_SHIFT_I2C_M_BUS_GNT_FW)
+#define BIT_CLEAR_I2C_M_BUS_GNT_FW(x) ((x) & (~BITS_I2C_M_BUS_GNT_FW))
+#define BIT_GET_I2C_M_BUS_GNT_FW(x)                                            \
+	(((x) >> BIT_SHIFT_I2C_M_BUS_GNT_FW) & BIT_MASK_I2C_M_BUS_GNT_FW)
+#define BIT_SET_I2C_M_BUS_GNT_FW(x, v)                                         \
+	(BIT_CLEAR_I2C_M_BUS_GNT_FW(x) | BIT_I2C_M_BUS_GNT_FW(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_CR					(Offset 0x0100) */
+
+#define BIT_RXDMA_EN BIT(3)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_CR					(Offset 0x0100) */
+
+#define BIT_I2C_M_GNT_FW BIT(3)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_CR					(Offset 0x0100) */
+
+#define BIT_TXDMA_EN BIT(2)
+#define BIT_HCI_RXDMA_EN BIT(1)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_CR					(Offset 0x0100) */
+
+#define BIT_SHIFT_I2C_M_SPEED 1
+#define BIT_MASK_I2C_M_SPEED 0x3
+#define BIT_I2C_M_SPEED(x)                                                     \
+	(((x) & BIT_MASK_I2C_M_SPEED) << BIT_SHIFT_I2C_M_SPEED)
+#define BITS_I2C_M_SPEED (BIT_MASK_I2C_M_SPEED << BIT_SHIFT_I2C_M_SPEED)
+#define BIT_CLEAR_I2C_M_SPEED(x) ((x) & (~BITS_I2C_M_SPEED))
+#define BIT_GET_I2C_M_SPEED(x)                                                 \
+	(((x) >> BIT_SHIFT_I2C_M_SPEED) & BIT_MASK_I2C_M_SPEED)
+#define BIT_SET_I2C_M_SPEED(x, v)                                              \
+	(BIT_CLEAR_I2C_M_SPEED(x) | BIT_I2C_M_SPEED(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_CR					(Offset 0x0100) */
+
+#define BIT_HCI_TXDMA_EN BIT(0)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_CR					(Offset 0x0100) */
+
+#define BIT_I2C_M_UNLOCK BIT(0)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_PG_SIZE				(Offset 0x0104) */
+
+#define BIT_SHIFT_DBG_FIFO_SEL 16
+#define BIT_MASK_DBG_FIFO_SEL 0xff
+#define BIT_DBG_FIFO_SEL(x)                                                    \
+	(((x) & BIT_MASK_DBG_FIFO_SEL) << BIT_SHIFT_DBG_FIFO_SEL)
+#define BITS_DBG_FIFO_SEL (BIT_MASK_DBG_FIFO_SEL << BIT_SHIFT_DBG_FIFO_SEL)
+#define BIT_CLEAR_DBG_FIFO_SEL(x) ((x) & (~BITS_DBG_FIFO_SEL))
+#define BIT_GET_DBG_FIFO_SEL(x)                                                \
+	(((x) >> BIT_SHIFT_DBG_FIFO_SEL) & BIT_MASK_DBG_FIFO_SEL)
+#define BIT_SET_DBG_FIFO_SEL(x, v)                                             \
+	(BIT_CLEAR_DBG_FIFO_SEL(x) | BIT_DBG_FIFO_SEL(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_PKT_BUFF_ACCESS_CTRL		(Offset 0x0106) */
+
+#define BIT_SHIFT_PKT_BUFF_ACCESS_CTRL 0
+#define BIT_MASK_PKT_BUFF_ACCESS_CTRL 0xff
+#define BIT_PKT_BUFF_ACCESS_CTRL(x)                                            \
+	(((x) & BIT_MASK_PKT_BUFF_ACCESS_CTRL)                                 \
+	 << BIT_SHIFT_PKT_BUFF_ACCESS_CTRL)
+#define BITS_PKT_BUFF_ACCESS_CTRL                                              \
+	(BIT_MASK_PKT_BUFF_ACCESS_CTRL << BIT_SHIFT_PKT_BUFF_ACCESS_CTRL)
+#define BIT_CLEAR_PKT_BUFF_ACCESS_CTRL(x) ((x) & (~BITS_PKT_BUFF_ACCESS_CTRL))
+#define BIT_GET_PKT_BUFF_ACCESS_CTRL(x)                                        \
+	(((x) >> BIT_SHIFT_PKT_BUFF_ACCESS_CTRL) &                             \
+	 BIT_MASK_PKT_BUFF_ACCESS_CTRL)
+#define BIT_SET_PKT_BUFF_ACCESS_CTRL(x, v)                                     \
+	(BIT_CLEAR_PKT_BUFF_ACCESS_CTRL(x) | BIT_PKT_BUFF_ACCESS_CTRL(v))
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_TSF_CLK_STATE			(Offset 0x0108) */
+
+#define BIT_RXPKTBUF_DBG BIT(16)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_TSF_CLK_STATE			(Offset 0x0108) */
+
+#define BIT_TSF_CLK_IDX BIT(15)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_TSF_CLK_STATE			(Offset 0x0108) */
+
+#define BIT_TSF_CLK_STABLE BIT(15)
+
+#define BIT_SHIFT_PKTBUF_DBG_ADDR 0
+#define BIT_MASK_PKTBUF_DBG_ADDR 0x1fff
+#define BIT_PKTBUF_DBG_ADDR(x)                                                 \
+	(((x) & BIT_MASK_PKTBUF_DBG_ADDR) << BIT_SHIFT_PKTBUF_DBG_ADDR)
+#define BITS_PKTBUF_DBG_ADDR                                                   \
+	(BIT_MASK_PKTBUF_DBG_ADDR << BIT_SHIFT_PKTBUF_DBG_ADDR)
+#define BIT_CLEAR_PKTBUF_DBG_ADDR(x) ((x) & (~BITS_PKTBUF_DBG_ADDR))
+#define BIT_GET_PKTBUF_DBG_ADDR(x)                                             \
+	(((x) >> BIT_SHIFT_PKTBUF_DBG_ADDR) & BIT_MASK_PKTBUF_DBG_ADDR)
+#define BIT_SET_PKTBUF_DBG_ADDR(x, v)                                          \
+	(BIT_CLEAR_PKTBUF_DBG_ADDR(x) | BIT_PKTBUF_DBG_ADDR(v))
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_TXDMA_PQ_MAP			(Offset 0x010C) */
+
+#define BIT_CSI_BW_EN BIT(31)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_TXDMA_PQ_MAP			(Offset 0x010C) */
+
+#define BIT_SHIFT_TXDMA_HIQ_MAP_V1 19
+#define BIT_MASK_TXDMA_HIQ_MAP_V1 0x7
+#define BIT_TXDMA_HIQ_MAP_V1(x)                                                \
+	(((x) & BIT_MASK_TXDMA_HIQ_MAP_V1) << BIT_SHIFT_TXDMA_HIQ_MAP_V1)
+#define BITS_TXDMA_HIQ_MAP_V1                                                  \
+	(BIT_MASK_TXDMA_HIQ_MAP_V1 << BIT_SHIFT_TXDMA_HIQ_MAP_V1)
+#define BIT_CLEAR_TXDMA_HIQ_MAP_V1(x) ((x) & (~BITS_TXDMA_HIQ_MAP_V1))
+#define BIT_GET_TXDMA_HIQ_MAP_V1(x)                                            \
+	(((x) >> BIT_SHIFT_TXDMA_HIQ_MAP_V1) & BIT_MASK_TXDMA_HIQ_MAP_V1)
+#define BIT_SET_TXDMA_HIQ_MAP_V1(x, v)                                         \
+	(BIT_CLEAR_TXDMA_HIQ_MAP_V1(x) | BIT_TXDMA_HIQ_MAP_V1(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_TXDMA_PQ_MAP			(Offset 0x010C) */
+
+#define BIT_SHIFT_TXDMA_CMQ_MAP 16
+#define BIT_MASK_TXDMA_CMQ_MAP 0x3
+#define BIT_TXDMA_CMQ_MAP(x)                                                   \
+	(((x) & BIT_MASK_TXDMA_CMQ_MAP) << BIT_SHIFT_TXDMA_CMQ_MAP)
+#define BITS_TXDMA_CMQ_MAP (BIT_MASK_TXDMA_CMQ_MAP << BIT_SHIFT_TXDMA_CMQ_MAP)
+#define BIT_CLEAR_TXDMA_CMQ_MAP(x) ((x) & (~BITS_TXDMA_CMQ_MAP))
+#define BIT_GET_TXDMA_CMQ_MAP(x)                                               \
+	(((x) >> BIT_SHIFT_TXDMA_CMQ_MAP) & BIT_MASK_TXDMA_CMQ_MAP)
+#define BIT_SET_TXDMA_CMQ_MAP(x, v)                                            \
+	(BIT_CLEAR_TXDMA_CMQ_MAP(x) | BIT_TXDMA_CMQ_MAP(v))
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_TXDMA_PQ_MAP			(Offset 0x010C) */
+
+#define BIT_SHIFT_TXDMA_MGQ_MAP_V1 16
+#define BIT_MASK_TXDMA_MGQ_MAP_V1 0x7
+#define BIT_TXDMA_MGQ_MAP_V1(x)                                                \
+	(((x) & BIT_MASK_TXDMA_MGQ_MAP_V1) << BIT_SHIFT_TXDMA_MGQ_MAP_V1)
+#define BITS_TXDMA_MGQ_MAP_V1                                                  \
+	(BIT_MASK_TXDMA_MGQ_MAP_V1 << BIT_SHIFT_TXDMA_MGQ_MAP_V1)
+#define BIT_CLEAR_TXDMA_MGQ_MAP_V1(x) ((x) & (~BITS_TXDMA_MGQ_MAP_V1))
+#define BIT_GET_TXDMA_MGQ_MAP_V1(x)                                            \
+	(((x) >> BIT_SHIFT_TXDMA_MGQ_MAP_V1) & BIT_MASK_TXDMA_MGQ_MAP_V1)
+#define BIT_SET_TXDMA_MGQ_MAP_V1(x, v)                                         \
+	(BIT_CLEAR_TXDMA_MGQ_MAP_V1(x) | BIT_TXDMA_MGQ_MAP_V1(v))
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_TXDMA_PQ_MAP			(Offset 0x010C) */
+
+#define BIT_SHIFT_TXDMA_H2C_MAP 16
+#define BIT_MASK_TXDMA_H2C_MAP 0x3
+#define BIT_TXDMA_H2C_MAP(x)                                                   \
+	(((x) & BIT_MASK_TXDMA_H2C_MAP) << BIT_SHIFT_TXDMA_H2C_MAP)
+#define BITS_TXDMA_H2C_MAP (BIT_MASK_TXDMA_H2C_MAP << BIT_SHIFT_TXDMA_H2C_MAP)
+#define BIT_CLEAR_TXDMA_H2C_MAP(x) ((x) & (~BITS_TXDMA_H2C_MAP))
+#define BIT_GET_TXDMA_H2C_MAP(x)                                               \
+	(((x) >> BIT_SHIFT_TXDMA_H2C_MAP) & BIT_MASK_TXDMA_H2C_MAP)
+#define BIT_SET_TXDMA_H2C_MAP(x, v)                                            \
+	(BIT_CLEAR_TXDMA_H2C_MAP(x) | BIT_TXDMA_H2C_MAP(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8881A_SUPPORT)
+
+/* 2 REG_TXDMA_PQ_MAP			(Offset 0x010C) */
+
+#define BIT_SHIFT_TXDMA_HIQ_MAP 14
+#define BIT_MASK_TXDMA_HIQ_MAP 0x3
+#define BIT_TXDMA_HIQ_MAP(x)                                                   \
+	(((x) & BIT_MASK_TXDMA_HIQ_MAP) << BIT_SHIFT_TXDMA_HIQ_MAP)
+#define BITS_TXDMA_HIQ_MAP (BIT_MASK_TXDMA_HIQ_MAP << BIT_SHIFT_TXDMA_HIQ_MAP)
+#define BIT_CLEAR_TXDMA_HIQ_MAP(x) ((x) & (~BITS_TXDMA_HIQ_MAP))
+#define BIT_GET_TXDMA_HIQ_MAP(x)                                               \
+	(((x) >> BIT_SHIFT_TXDMA_HIQ_MAP) & BIT_MASK_TXDMA_HIQ_MAP)
+#define BIT_SET_TXDMA_HIQ_MAP(x, v)                                            \
+	(BIT_CLEAR_TXDMA_HIQ_MAP(x) | BIT_TXDMA_HIQ_MAP(v))
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_TXDMA_PQ_MAP			(Offset 0x010C) */
+
+#define BIT_SHIFT_TXDMA_BKQ_MAP_V1 13
+#define BIT_MASK_TXDMA_BKQ_MAP_V1 0x7
+#define BIT_TXDMA_BKQ_MAP_V1(x)                                                \
+	(((x) & BIT_MASK_TXDMA_BKQ_MAP_V1) << BIT_SHIFT_TXDMA_BKQ_MAP_V1)
+#define BITS_TXDMA_BKQ_MAP_V1                                                  \
+	(BIT_MASK_TXDMA_BKQ_MAP_V1 << BIT_SHIFT_TXDMA_BKQ_MAP_V1)
+#define BIT_CLEAR_TXDMA_BKQ_MAP_V1(x) ((x) & (~BITS_TXDMA_BKQ_MAP_V1))
+#define BIT_GET_TXDMA_BKQ_MAP_V1(x)                                            \
+	(((x) >> BIT_SHIFT_TXDMA_BKQ_MAP_V1) & BIT_MASK_TXDMA_BKQ_MAP_V1)
+#define BIT_SET_TXDMA_BKQ_MAP_V1(x, v)                                         \
+	(BIT_CLEAR_TXDMA_BKQ_MAP_V1(x) | BIT_TXDMA_BKQ_MAP_V1(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8881A_SUPPORT)
+
+/* 2 REG_TXDMA_PQ_MAP			(Offset 0x010C) */
+
+#define BIT_SHIFT_TXDMA_MGQ_MAP 12
+#define BIT_MASK_TXDMA_MGQ_MAP 0x3
+#define BIT_TXDMA_MGQ_MAP(x)                                                   \
+	(((x) & BIT_MASK_TXDMA_MGQ_MAP) << BIT_SHIFT_TXDMA_MGQ_MAP)
+#define BITS_TXDMA_MGQ_MAP (BIT_MASK_TXDMA_MGQ_MAP << BIT_SHIFT_TXDMA_MGQ_MAP)
+#define BIT_CLEAR_TXDMA_MGQ_MAP(x) ((x) & (~BITS_TXDMA_MGQ_MAP))
+#define BIT_GET_TXDMA_MGQ_MAP(x)                                               \
+	(((x) >> BIT_SHIFT_TXDMA_MGQ_MAP) & BIT_MASK_TXDMA_MGQ_MAP)
+#define BIT_SET_TXDMA_MGQ_MAP(x, v)                                            \
+	(BIT_CLEAR_TXDMA_MGQ_MAP(x) | BIT_TXDMA_MGQ_MAP(v))
+
+#define BIT_SHIFT_TXDMA_BKQ_MAP 10
+#define BIT_MASK_TXDMA_BKQ_MAP 0x3
+#define BIT_TXDMA_BKQ_MAP(x)                                                   \
+	(((x) & BIT_MASK_TXDMA_BKQ_MAP) << BIT_SHIFT_TXDMA_BKQ_MAP)
+#define BITS_TXDMA_BKQ_MAP (BIT_MASK_TXDMA_BKQ_MAP << BIT_SHIFT_TXDMA_BKQ_MAP)
+#define BIT_CLEAR_TXDMA_BKQ_MAP(x) ((x) & (~BITS_TXDMA_BKQ_MAP))
+#define BIT_GET_TXDMA_BKQ_MAP(x)                                               \
+	(((x) >> BIT_SHIFT_TXDMA_BKQ_MAP) & BIT_MASK_TXDMA_BKQ_MAP)
+#define BIT_SET_TXDMA_BKQ_MAP(x, v)                                            \
+	(BIT_CLEAR_TXDMA_BKQ_MAP(x) | BIT_TXDMA_BKQ_MAP(v))
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_TXDMA_PQ_MAP			(Offset 0x010C) */
+
+#define BIT_SHIFT_TXDMA_BEQ_MAP_V1 10
+#define BIT_MASK_TXDMA_BEQ_MAP_V1 0x7
+#define BIT_TXDMA_BEQ_MAP_V1(x)                                                \
+	(((x) & BIT_MASK_TXDMA_BEQ_MAP_V1) << BIT_SHIFT_TXDMA_BEQ_MAP_V1)
+#define BITS_TXDMA_BEQ_MAP_V1                                                  \
+	(BIT_MASK_TXDMA_BEQ_MAP_V1 << BIT_SHIFT_TXDMA_BEQ_MAP_V1)
+#define BIT_CLEAR_TXDMA_BEQ_MAP_V1(x) ((x) & (~BITS_TXDMA_BEQ_MAP_V1))
+#define BIT_GET_TXDMA_BEQ_MAP_V1(x)                                            \
+	(((x) >> BIT_SHIFT_TXDMA_BEQ_MAP_V1) & BIT_MASK_TXDMA_BEQ_MAP_V1)
+#define BIT_SET_TXDMA_BEQ_MAP_V1(x, v)                                         \
+	(BIT_CLEAR_TXDMA_BEQ_MAP_V1(x) | BIT_TXDMA_BEQ_MAP_V1(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8881A_SUPPORT)
+
+/* 2 REG_TXDMA_PQ_MAP			(Offset 0x010C) */
+
+#define BIT_SHIFT_TXDMA_BEQ_MAP 8
+#define BIT_MASK_TXDMA_BEQ_MAP 0x3
+#define BIT_TXDMA_BEQ_MAP(x)                                                   \
+	(((x) & BIT_MASK_TXDMA_BEQ_MAP) << BIT_SHIFT_TXDMA_BEQ_MAP)
+#define BITS_TXDMA_BEQ_MAP (BIT_MASK_TXDMA_BEQ_MAP << BIT_SHIFT_TXDMA_BEQ_MAP)
+#define BIT_CLEAR_TXDMA_BEQ_MAP(x) ((x) & (~BITS_TXDMA_BEQ_MAP))
+#define BIT_GET_TXDMA_BEQ_MAP(x)                                               \
+	(((x) >> BIT_SHIFT_TXDMA_BEQ_MAP) & BIT_MASK_TXDMA_BEQ_MAP)
+#define BIT_SET_TXDMA_BEQ_MAP(x, v)                                            \
+	(BIT_CLEAR_TXDMA_BEQ_MAP(x) | BIT_TXDMA_BEQ_MAP(v))
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_TXDMA_PQ_MAP			(Offset 0x010C) */
+
+#define BIT_SHIFT_TXDMA_VIQ_MAP_V1 7
+#define BIT_MASK_TXDMA_VIQ_MAP_V1 0x7
+#define BIT_TXDMA_VIQ_MAP_V1(x)                                                \
+	(((x) & BIT_MASK_TXDMA_VIQ_MAP_V1) << BIT_SHIFT_TXDMA_VIQ_MAP_V1)
+#define BITS_TXDMA_VIQ_MAP_V1                                                  \
+	(BIT_MASK_TXDMA_VIQ_MAP_V1 << BIT_SHIFT_TXDMA_VIQ_MAP_V1)
+#define BIT_CLEAR_TXDMA_VIQ_MAP_V1(x) ((x) & (~BITS_TXDMA_VIQ_MAP_V1))
+#define BIT_GET_TXDMA_VIQ_MAP_V1(x)                                            \
+	(((x) >> BIT_SHIFT_TXDMA_VIQ_MAP_V1) & BIT_MASK_TXDMA_VIQ_MAP_V1)
+#define BIT_SET_TXDMA_VIQ_MAP_V1(x, v)                                         \
+	(BIT_CLEAR_TXDMA_VIQ_MAP_V1(x) | BIT_TXDMA_VIQ_MAP_V1(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8881A_SUPPORT)
+
+/* 2 REG_TXDMA_PQ_MAP			(Offset 0x010C) */
+
+#define BIT_SHIFT_TXDMA_VIQ_MAP 6
+#define BIT_MASK_TXDMA_VIQ_MAP 0x3
+#define BIT_TXDMA_VIQ_MAP(x)                                                   \
+	(((x) & BIT_MASK_TXDMA_VIQ_MAP) << BIT_SHIFT_TXDMA_VIQ_MAP)
+#define BITS_TXDMA_VIQ_MAP (BIT_MASK_TXDMA_VIQ_MAP << BIT_SHIFT_TXDMA_VIQ_MAP)
+#define BIT_CLEAR_TXDMA_VIQ_MAP(x) ((x) & (~BITS_TXDMA_VIQ_MAP))
+#define BIT_GET_TXDMA_VIQ_MAP(x)                                               \
+	(((x) >> BIT_SHIFT_TXDMA_VIQ_MAP) & BIT_MASK_TXDMA_VIQ_MAP)
+#define BIT_SET_TXDMA_VIQ_MAP(x, v)                                            \
+	(BIT_CLEAR_TXDMA_VIQ_MAP(x) | BIT_TXDMA_VIQ_MAP(v))
+
+#define BIT_SHIFT_TXDMA_VOQ_MAP 4
+#define BIT_MASK_TXDMA_VOQ_MAP 0x3
+#define BIT_TXDMA_VOQ_MAP(x)                                                   \
+	(((x) & BIT_MASK_TXDMA_VOQ_MAP) << BIT_SHIFT_TXDMA_VOQ_MAP)
+#define BITS_TXDMA_VOQ_MAP (BIT_MASK_TXDMA_VOQ_MAP << BIT_SHIFT_TXDMA_VOQ_MAP)
+#define BIT_CLEAR_TXDMA_VOQ_MAP(x) ((x) & (~BITS_TXDMA_VOQ_MAP))
+#define BIT_GET_TXDMA_VOQ_MAP(x)                                               \
+	(((x) >> BIT_SHIFT_TXDMA_VOQ_MAP) & BIT_MASK_TXDMA_VOQ_MAP)
+#define BIT_SET_TXDMA_VOQ_MAP(x, v)                                            \
+	(BIT_CLEAR_TXDMA_VOQ_MAP(x) | BIT_TXDMA_VOQ_MAP(v))
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_TXDMA_PQ_MAP			(Offset 0x010C) */
+
+#define BIT_SHIFT_TXDMA_VOQ_MAP_V1 4
+#define BIT_MASK_TXDMA_VOQ_MAP_V1 0x7
+#define BIT_TXDMA_VOQ_MAP_V1(x)                                                \
+	(((x) & BIT_MASK_TXDMA_VOQ_MAP_V1) << BIT_SHIFT_TXDMA_VOQ_MAP_V1)
+#define BITS_TXDMA_VOQ_MAP_V1                                                  \
+	(BIT_MASK_TXDMA_VOQ_MAP_V1 << BIT_SHIFT_TXDMA_VOQ_MAP_V1)
+#define BIT_CLEAR_TXDMA_VOQ_MAP_V1(x) ((x) & (~BITS_TXDMA_VOQ_MAP_V1))
+#define BIT_GET_TXDMA_VOQ_MAP_V1(x)                                            \
+	(((x) >> BIT_SHIFT_TXDMA_VOQ_MAP_V1) & BIT_MASK_TXDMA_VOQ_MAP_V1)
+#define BIT_SET_TXDMA_VOQ_MAP_V1(x, v)                                         \
+	(BIT_CLEAR_TXDMA_VOQ_MAP_V1(x) | BIT_TXDMA_VOQ_MAP_V1(v))
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_TXDMA_PQ_MAP			(Offset 0x010C) */
+
+#define BIT_TXDMA_BW_EN BIT(3)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_TXDMA_PQ_MAP			(Offset 0x010C) */
+
+#define BIT_RXDMA_AGG_EN BIT(2)
+#define BIT_RXSHFT_EN BIT(1)
+#define BIT_RXDMA_ARBBW_EN BIT(0)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT)
+
+/* 2 REG_TRXFF_BNDY				(Offset 0x0114) */
+
+#define BIT_SHIFT_RXFFOVFL_RSV_V1 28
+#define BIT_MASK_RXFFOVFL_RSV_V1 0xf
+#define BIT_RXFFOVFL_RSV_V1(x)                                                 \
+	(((x) & BIT_MASK_RXFFOVFL_RSV_V1) << BIT_SHIFT_RXFFOVFL_RSV_V1)
+#define BITS_RXFFOVFL_RSV_V1                                                   \
+	(BIT_MASK_RXFFOVFL_RSV_V1 << BIT_SHIFT_RXFFOVFL_RSV_V1)
+#define BIT_CLEAR_RXFFOVFL_RSV_V1(x) ((x) & (~BITS_RXFFOVFL_RSV_V1))
+#define BIT_GET_RXFFOVFL_RSV_V1(x)                                             \
+	(((x) >> BIT_SHIFT_RXFFOVFL_RSV_V1) & BIT_MASK_RXFFOVFL_RSV_V1)
+#define BIT_SET_RXFFOVFL_RSV_V1(x, v)                                          \
+	(BIT_CLEAR_RXFFOVFL_RSV_V1(x) | BIT_RXFFOVFL_RSV_V1(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_TRXFF_BNDY				(Offset 0x0114) */
+
+#define BIT_SHIFT_RXFF0_BNDY 16
+#define BIT_MASK_RXFF0_BNDY 0xffff
+#define BIT_RXFF0_BNDY(x) (((x) & BIT_MASK_RXFF0_BNDY) << BIT_SHIFT_RXFF0_BNDY)
+#define BITS_RXFF0_BNDY (BIT_MASK_RXFF0_BNDY << BIT_SHIFT_RXFF0_BNDY)
+#define BIT_CLEAR_RXFF0_BNDY(x) ((x) & (~BITS_RXFF0_BNDY))
+#define BIT_GET_RXFF0_BNDY(x)                                                  \
+	(((x) >> BIT_SHIFT_RXFF0_BNDY) & BIT_MASK_RXFF0_BNDY)
+#define BIT_SET_RXFF0_BNDY(x, v) (BIT_CLEAR_RXFF0_BNDY(x) | BIT_RXFF0_BNDY(v))
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_TRXFF_BNDY				(Offset 0x0114) */
+
+#define BIT_SHIFT_FWFFOVFL_RSV 16
+#define BIT_MASK_FWFFOVFL_RSV 0xf
+#define BIT_FWFFOVFL_RSV(x)                                                    \
+	(((x) & BIT_MASK_FWFFOVFL_RSV) << BIT_SHIFT_FWFFOVFL_RSV)
+#define BITS_FWFFOVFL_RSV (BIT_MASK_FWFFOVFL_RSV << BIT_SHIFT_FWFFOVFL_RSV)
+#define BIT_CLEAR_FWFFOVFL_RSV(x) ((x) & (~BITS_FWFFOVFL_RSV))
+#define BIT_GET_FWFFOVFL_RSV(x)                                                \
+	(((x) >> BIT_SHIFT_FWFFOVFL_RSV) & BIT_MASK_FWFFOVFL_RSV)
+#define BIT_SET_FWFFOVFL_RSV(x, v)                                             \
+	(BIT_CLEAR_FWFFOVFL_RSV(x) | BIT_FWFFOVFL_RSV(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_TRXFF_BNDY				(Offset 0x0114) */
+
+#define BIT_SHIFT_RXFFOVFL_RSV 8
+#define BIT_MASK_RXFFOVFL_RSV 0xf
+#define BIT_RXFFOVFL_RSV(x)                                                    \
+	(((x) & BIT_MASK_RXFFOVFL_RSV) << BIT_SHIFT_RXFFOVFL_RSV)
+#define BITS_RXFFOVFL_RSV (BIT_MASK_RXFFOVFL_RSV << BIT_SHIFT_RXFFOVFL_RSV)
+#define BIT_CLEAR_RXFFOVFL_RSV(x) ((x) & (~BITS_RXFFOVFL_RSV))
+#define BIT_GET_RXFFOVFL_RSV(x)                                                \
+	(((x) >> BIT_SHIFT_RXFFOVFL_RSV) & BIT_MASK_RXFFOVFL_RSV)
+#define BIT_SET_RXFFOVFL_RSV(x, v)                                             \
+	(BIT_CLEAR_RXFFOVFL_RSV(x) | BIT_RXFFOVFL_RSV(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_TRXFF_BNDY				(Offset 0x0114) */
+
+#define BIT_SHIFT_RXFFOVFL_RSV_V2 8
+#define BIT_MASK_RXFFOVFL_RSV_V2 0xf
+#define BIT_RXFFOVFL_RSV_V2(x)                                                 \
+	(((x) & BIT_MASK_RXFFOVFL_RSV_V2) << BIT_SHIFT_RXFFOVFL_RSV_V2)
+#define BITS_RXFFOVFL_RSV_V2                                                   \
+	(BIT_MASK_RXFFOVFL_RSV_V2 << BIT_SHIFT_RXFFOVFL_RSV_V2)
+#define BIT_CLEAR_RXFFOVFL_RSV_V2(x) ((x) & (~BITS_RXFFOVFL_RSV_V2))
+#define BIT_GET_RXFFOVFL_RSV_V2(x)                                             \
+	(((x) >> BIT_SHIFT_RXFFOVFL_RSV_V2) & BIT_MASK_RXFFOVFL_RSV_V2)
+#define BIT_SET_RXFFOVFL_RSV_V2(x, v)                                          \
+	(BIT_CLEAR_RXFFOVFL_RSV_V2(x) | BIT_RXFFOVFL_RSV_V2(v))
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT)
+
+/* 2 REG_TRXFF_BNDY				(Offset 0x0114) */
+
+#define BIT_SHIFT_RXFF0_BNDY_V1 8
+#define BIT_MASK_RXFF0_BNDY_V1 0x3ffff
+#define BIT_RXFF0_BNDY_V1(x)                                                   \
+	(((x) & BIT_MASK_RXFF0_BNDY_V1) << BIT_SHIFT_RXFF0_BNDY_V1)
+#define BITS_RXFF0_BNDY_V1 (BIT_MASK_RXFF0_BNDY_V1 << BIT_SHIFT_RXFF0_BNDY_V1)
+#define BIT_CLEAR_RXFF0_BNDY_V1(x) ((x) & (~BITS_RXFF0_BNDY_V1))
+#define BIT_GET_RXFF0_BNDY_V1(x)                                               \
+	(((x) >> BIT_SHIFT_RXFF0_BNDY_V1) & BIT_MASK_RXFF0_BNDY_V1)
+#define BIT_SET_RXFF0_BNDY_V1(x, v)                                            \
+	(BIT_CLEAR_RXFF0_BNDY_V1(x) | BIT_RXFF0_BNDY_V1(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT || \
+     HALMAC_8881A_SUPPORT)
+
+/* 2 REG_TRXFF_BNDY				(Offset 0x0114) */
+
+#define BIT_SHIFT_TXPKTBUF_PGBNDY 0
+#define BIT_MASK_TXPKTBUF_PGBNDY 0xff
+#define BIT_TXPKTBUF_PGBNDY(x)                                                 \
+	(((x) & BIT_MASK_TXPKTBUF_PGBNDY) << BIT_SHIFT_TXPKTBUF_PGBNDY)
+#define BITS_TXPKTBUF_PGBNDY                                                   \
+	(BIT_MASK_TXPKTBUF_PGBNDY << BIT_SHIFT_TXPKTBUF_PGBNDY)
+#define BIT_CLEAR_TXPKTBUF_PGBNDY(x) ((x) & (~BITS_TXPKTBUF_PGBNDY))
+#define BIT_GET_TXPKTBUF_PGBNDY(x)                                             \
+	(((x) >> BIT_SHIFT_TXPKTBUF_PGBNDY) & BIT_MASK_TXPKTBUF_PGBNDY)
+#define BIT_SET_TXPKTBUF_PGBNDY(x, v)                                          \
+	(BIT_CLEAR_TXPKTBUF_PGBNDY(x) | BIT_TXPKTBUF_PGBNDY(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_TRXFF_BNDY				(Offset 0x0114) */
+
+#define BIT_SHIFT_RXFF0_BNDY_V2 0
+#define BIT_MASK_RXFF0_BNDY_V2 0x3ffff
+#define BIT_RXFF0_BNDY_V2(x)                                                   \
+	(((x) & BIT_MASK_RXFF0_BNDY_V2) << BIT_SHIFT_RXFF0_BNDY_V2)
+#define BITS_RXFF0_BNDY_V2 (BIT_MASK_RXFF0_BNDY_V2 << BIT_SHIFT_RXFF0_BNDY_V2)
+#define BIT_CLEAR_RXFF0_BNDY_V2(x) ((x) & (~BITS_RXFF0_BNDY_V2))
+#define BIT_GET_RXFF0_BNDY_V2(x)                                               \
+	(((x) >> BIT_SHIFT_RXFF0_BNDY_V2) & BIT_MASK_RXFF0_BNDY_V2)
+#define BIT_SET_RXFF0_BNDY_V2(x, v)                                            \
+	(BIT_CLEAR_RXFF0_BNDY_V2(x) | BIT_RXFF0_BNDY_V2(v))
+
+#define BIT_SHIFT_RXFF0_RDPTR_V2 0
+#define BIT_MASK_RXFF0_RDPTR_V2 0x3ffff
+#define BIT_RXFF0_RDPTR_V2(x)                                                  \
+	(((x) & BIT_MASK_RXFF0_RDPTR_V2) << BIT_SHIFT_RXFF0_RDPTR_V2)
+#define BITS_RXFF0_RDPTR_V2                                                    \
+	(BIT_MASK_RXFF0_RDPTR_V2 << BIT_SHIFT_RXFF0_RDPTR_V2)
+#define BIT_CLEAR_RXFF0_RDPTR_V2(x) ((x) & (~BITS_RXFF0_RDPTR_V2))
+#define BIT_GET_RXFF0_RDPTR_V2(x)                                              \
+	(((x) >> BIT_SHIFT_RXFF0_RDPTR_V2) & BIT_MASK_RXFF0_RDPTR_V2)
+#define BIT_SET_RXFF0_RDPTR_V2(x, v)                                           \
+	(BIT_CLEAR_RXFF0_RDPTR_V2(x) | BIT_RXFF0_RDPTR_V2(v))
+
+#define BIT_SHIFT_RXFF0_WTPTR_V2 0
+#define BIT_MASK_RXFF0_WTPTR_V2 0x3ffff
+#define BIT_RXFF0_WTPTR_V2(x)                                                  \
+	(((x) & BIT_MASK_RXFF0_WTPTR_V2) << BIT_SHIFT_RXFF0_WTPTR_V2)
+#define BITS_RXFF0_WTPTR_V2                                                    \
+	(BIT_MASK_RXFF0_WTPTR_V2 << BIT_SHIFT_RXFF0_WTPTR_V2)
+#define BIT_CLEAR_RXFF0_WTPTR_V2(x) ((x) & (~BITS_RXFF0_WTPTR_V2))
+#define BIT_GET_RXFF0_WTPTR_V2(x)                                              \
+	(((x) >> BIT_SHIFT_RXFF0_WTPTR_V2) & BIT_MASK_RXFF0_WTPTR_V2)
+#define BIT_SET_RXFF0_WTPTR_V2(x, v)                                           \
+	(BIT_CLEAR_RXFF0_WTPTR_V2(x) | BIT_RXFF0_WTPTR_V2(v))
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT)
+
+/* 2 REG_FF_STATUS				(Offset 0x0118) */
+
+#define BIT_SHIFT_RXFF0_RDPTR_V1 13
+#define BIT_MASK_RXFF0_RDPTR_V1 0x3ffff
+#define BIT_RXFF0_RDPTR_V1(x)                                                  \
+	(((x) & BIT_MASK_RXFF0_RDPTR_V1) << BIT_SHIFT_RXFF0_RDPTR_V1)
+#define BITS_RXFF0_RDPTR_V1                                                    \
+	(BIT_MASK_RXFF0_RDPTR_V1 << BIT_SHIFT_RXFF0_RDPTR_V1)
+#define BIT_CLEAR_RXFF0_RDPTR_V1(x) ((x) & (~BITS_RXFF0_RDPTR_V1))
+#define BIT_GET_RXFF0_RDPTR_V1(x)                                              \
+	(((x) >> BIT_SHIFT_RXFF0_RDPTR_V1) & BIT_MASK_RXFF0_RDPTR_V1)
+#define BIT_SET_RXFF0_RDPTR_V1(x, v)                                           \
+	(BIT_CLEAR_RXFF0_RDPTR_V1(x) | BIT_RXFF0_RDPTR_V1(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_PTA_I2C_MBOX			(Offset 0x0118) */
+
+#define BIT_SHIFT_I2C_M_STATUS 8
+#define BIT_MASK_I2C_M_STATUS 0xf
+#define BIT_I2C_M_STATUS(x)                                                    \
+	(((x) & BIT_MASK_I2C_M_STATUS) << BIT_SHIFT_I2C_M_STATUS)
+#define BITS_I2C_M_STATUS (BIT_MASK_I2C_M_STATUS << BIT_SHIFT_I2C_M_STATUS)
+#define BIT_CLEAR_I2C_M_STATUS(x) ((x) & (~BITS_I2C_M_STATUS))
+#define BIT_GET_I2C_M_STATUS(x)                                                \
+	(((x) >> BIT_SHIFT_I2C_M_STATUS) & BIT_MASK_I2C_M_STATUS)
+#define BIT_SET_I2C_M_STATUS(x, v)                                             \
+	(BIT_CLEAR_I2C_M_STATUS(x) | BIT_I2C_M_STATUS(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_PTA_I2C_MBOX			(Offset 0x0118) */
+
+#define BIT_SHIFT_I2C_M_BUS_GNT 4
+#define BIT_MASK_I2C_M_BUS_GNT 0x7
+#define BIT_I2C_M_BUS_GNT(x)                                                   \
+	(((x) & BIT_MASK_I2C_M_BUS_GNT) << BIT_SHIFT_I2C_M_BUS_GNT)
+#define BITS_I2C_M_BUS_GNT (BIT_MASK_I2C_M_BUS_GNT << BIT_SHIFT_I2C_M_BUS_GNT)
+#define BIT_CLEAR_I2C_M_BUS_GNT(x) ((x) & (~BITS_I2C_M_BUS_GNT))
+#define BIT_GET_I2C_M_BUS_GNT(x)                                               \
+	(((x) >> BIT_SHIFT_I2C_M_BUS_GNT) & BIT_MASK_I2C_M_BUS_GNT)
+#define BIT_SET_I2C_M_BUS_GNT(x, v)                                            \
+	(BIT_CLEAR_I2C_M_BUS_GNT(x) | BIT_I2C_M_BUS_GNT(v))
+
+#define BIT_I2C_GNT_FW BIT(3)
+
+#define BIT_SHIFT_I2C_DATA_RATE 1
+#define BIT_MASK_I2C_DATA_RATE 0x3
+#define BIT_I2C_DATA_RATE(x)                                                   \
+	(((x) & BIT_MASK_I2C_DATA_RATE) << BIT_SHIFT_I2C_DATA_RATE)
+#define BITS_I2C_DATA_RATE (BIT_MASK_I2C_DATA_RATE << BIT_SHIFT_I2C_DATA_RATE)
+#define BIT_CLEAR_I2C_DATA_RATE(x) ((x) & (~BITS_I2C_DATA_RATE))
+#define BIT_GET_I2C_DATA_RATE(x)                                               \
+	(((x) >> BIT_SHIFT_I2C_DATA_RATE) & BIT_MASK_I2C_DATA_RATE)
+#define BIT_SET_I2C_DATA_RATE(x, v)                                            \
+	(BIT_CLEAR_I2C_DATA_RATE(x) | BIT_I2C_DATA_RATE(v))
+
+#define BIT_I2C_SW_CONTROL_UNLOCK BIT(0)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT)
+
+/* 2 REG_FF_STATUS				(Offset 0x0118) */
+
+#define BIT_SHIFT_RXFF0_WTPTR_V1 0
+#define BIT_MASK_RXFF0_WTPTR_V1 0x3ffff
+#define BIT_RXFF0_WTPTR_V1(x)                                                  \
+	(((x) & BIT_MASK_RXFF0_WTPTR_V1) << BIT_SHIFT_RXFF0_WTPTR_V1)
+#define BITS_RXFF0_WTPTR_V1                                                    \
+	(BIT_MASK_RXFF0_WTPTR_V1 << BIT_SHIFT_RXFF0_WTPTR_V1)
+#define BIT_CLEAR_RXFF0_WTPTR_V1(x) ((x) & (~BITS_RXFF0_WTPTR_V1))
+#define BIT_GET_RXFF0_WTPTR_V1(x)                                              \
+	(((x) >> BIT_SHIFT_RXFF0_WTPTR_V1) & BIT_MASK_RXFF0_WTPTR_V1)
+#define BIT_SET_RXFF0_WTPTR_V1(x, v)                                           \
+	(BIT_CLEAR_RXFF0_WTPTR_V1(x) | BIT_RXFF0_WTPTR_V1(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_RXFF_PTR				(Offset 0x011C) */
+
+#define BIT_SHIFT_RXFF0_RDPTR 16
+#define BIT_MASK_RXFF0_RDPTR 0xffff
+#define BIT_RXFF0_RDPTR(x)                                                     \
+	(((x) & BIT_MASK_RXFF0_RDPTR) << BIT_SHIFT_RXFF0_RDPTR)
+#define BITS_RXFF0_RDPTR (BIT_MASK_RXFF0_RDPTR << BIT_SHIFT_RXFF0_RDPTR)
+#define BIT_CLEAR_RXFF0_RDPTR(x) ((x) & (~BITS_RXFF0_RDPTR))
+#define BIT_GET_RXFF0_RDPTR(x)                                                 \
+	(((x) >> BIT_SHIFT_RXFF0_RDPTR) & BIT_MASK_RXFF0_RDPTR)
+#define BIT_SET_RXFF0_RDPTR(x, v)                                              \
+	(BIT_CLEAR_RXFF0_RDPTR(x) | BIT_RXFF0_RDPTR(v))
+
+#define BIT_SHIFT_RXFF0_WTPTR 0
+#define BIT_MASK_RXFF0_WTPTR 0xffff
+#define BIT_RXFF0_WTPTR(x)                                                     \
+	(((x) & BIT_MASK_RXFF0_WTPTR) << BIT_SHIFT_RXFF0_WTPTR)
+#define BITS_RXFF0_WTPTR (BIT_MASK_RXFF0_WTPTR << BIT_SHIFT_RXFF0_WTPTR)
+#define BIT_CLEAR_RXFF0_WTPTR(x) ((x) & (~BITS_RXFF0_WTPTR))
+#define BIT_GET_RXFF0_WTPTR(x)                                                 \
+	(((x) >> BIT_SHIFT_RXFF0_WTPTR) & BIT_MASK_RXFF0_WTPTR)
+#define BIT_SET_RXFF0_WTPTR(x, v)                                              \
+	(BIT_CLEAR_RXFF0_WTPTR(x) | BIT_RXFF0_WTPTR(v))
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_FEIMR				(Offset 0x0120) */
+
+#define BIT_H2C_OK_INT_MSK BIT(31)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FE1IMR				(Offset 0x0120) */
+
+#define BIT_FS_SW_PLL_LEAVE_32K_INT_EN BIT(31)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_FE1IMR				(Offset 0x0120) */
+
+#define BIT_CPUMGQ_DROP_BY_HOLD_TIME_INT_EN BIT(31)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_FEIMR				(Offset 0x0120) */
+
+#define BIT_H2C_CMD_FULL_INT_MSK BIT(30)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FE1IMR				(Offset 0x0120) */
+
+#define BIT_FS_FWFF_FULL_INT_EN BIT(30)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_FE1IMR				(Offset 0x0120) */
+
+#define BIT_FWFF_FULL_INT_EN BIT(30)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_FEIMR				(Offset 0x0120) */
+
+#define BIT_PWR_INT_127_MSK_V1 BIT(29)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT)
+
+/* 2 REG_FE1IMR				(Offset 0x0120) */
+
+#define BIT_BB_STOP_RX_INT_EN BIT(29)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FE1IMR				(Offset 0x0120) */
+
+#define BIT_FS_BB_STOP_RX_INT_EN BIT(29)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_FEIMR				(Offset 0x0120) */
+
+#define BIT_PWR_INT_126_MSK BIT(28)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FE1IMR				(Offset 0x0120) */
+
+#define BIT_FS_RXDMA2_DONE_INT_EN BIT(28)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_FEIMR				(Offset 0x0120) */
+
+#define BIT_PWR_INT_125TO96_MSK BIT(27)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT)
+
+/* 2 REG_FE1IMR				(Offset 0x0120) */
+
+#define BIT_FS_RXDONE3_INT_EN BIT(27)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_FEIMR				(Offset 0x0120) */
+
+#define BIT_PWR_INT_95TO64_MSK_V1 BIT(26)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FE1IMR				(Offset 0x0120) */
+
+#define BIT_FS_RXDONE2_INT_EN BIT(26)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_FEIMR				(Offset 0x0120) */
+
+#define BIT_PWR_INT_63TO32_MSK_V1 BIT(25)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FE1IMR				(Offset 0x0120) */
+
+#define BIT_FS_RX_BCN_P4_INT_EN BIT(25)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_FEIMR				(Offset 0x0120) */
+
+#define BIT_PWR_INT_31TO0_MSK_V1 BIT(24)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FE1IMR				(Offset 0x0120) */
+
+#define BIT_FS_RX_BCN_P3_INT_EN BIT(24)
+#define BIT_FS_RX_BCN_P2_INT_EN BIT(23)
+#define BIT_FS_RX_BCN_P1_INT_EN BIT(22)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_FEIMR				(Offset 0x0120) */
+
+#define BIT_BF0_TIMEOUT_INT_MSK BIT(21)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FE1IMR				(Offset 0x0120) */
+
+#define BIT_FS_RX_BCN_P0_INT_EN BIT(21)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_FEIMR				(Offset 0x0120) */
+
+#define BIT_BF1_TIMEOUT_INT_MSK BIT(20)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FE1IMR				(Offset 0x0120) */
+
+#define BIT_FS_RX_UMD0_INT_EN BIT(20)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_FEIMR				(Offset 0x0120) */
+
+#define BIT_EVTQ_TXDONE_INT_MSK BIT(19)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FE1IMR				(Offset 0x0120) */
+
+#define BIT_FS_RX_UMD1_INT_EN BIT(19)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_FEIMR				(Offset 0x0120) */
+
+#define BIT_EVTQ_START_INT_MSK BIT(18)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FE1IMR				(Offset 0x0120) */
+
+#define BIT_FS_RX_BMD0_INT_EN BIT(18)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_FEIMR				(Offset 0x0120) */
+
+#define BIT_TXBCN2_OK_INT_MSK BIT(17)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FE1IMR				(Offset 0x0120) */
+
+#define BIT_FS_RX_BMD1_INT_EN BIT(17)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_FEIMR				(Offset 0x0120) */
+
+#define BIT_TXBCN2_ERR_INT_MSK BIT(16)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FE1IMR				(Offset 0x0120) */
+
+#define BIT_FS_RXDONE_INT_EN BIT(16)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_FEIMR				(Offset 0x0120) */
+
+#define BIT_DWWIN_END_INT_MSK BIT(15)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FE1IMR				(Offset 0x0120) */
+
+#define BIT_FS_WWLAN_INT_EN BIT(15)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_FEIMR				(Offset 0x0120) */
+
+#define BIT_BCN2_EARLY_INT_MSK BIT(14)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FE1IMR				(Offset 0x0120) */
+
+#define BIT_FS_SOUND_DONE_INT_EN BIT(14)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_FEIMR				(Offset 0x0120) */
+
+#define BIT_TBTT1_INT_MSK BIT(13)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+
+/* 2 REG_FE1IMR				(Offset 0x0120) */
+
+#define BIT_FS_LP_STBY_INT_EN BIT(13)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_FEIMR				(Offset 0x0120) */
+
+#define BIT_PSTIMERB_INT_MSK BIT(12)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT)
+
+/* 2 REG_FE1IMR				(Offset 0x0120) */
+
+#define BIT_FS_TRL_MTR_INT_EN BIT(12)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_FEIMR				(Offset 0x0120) */
+
+#define BIT_PSTIMERA_INT_MSK BIT(11)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FE1IMR				(Offset 0x0120) */
+
+#define BIT_FS_BF1_PRETO_INT_EN BIT(11)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_FEIMR				(Offset 0x0120) */
+
+#define BIT_P2P_RFOFF_EARLY_INT_MSK BIT(10)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FE1IMR				(Offset 0x0120) */
+
+#define BIT_FS_BF0_PRETO_INT_EN BIT(10)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_FEIMR				(Offset 0x0120) */
+
+#define BIT_MACID_RELEASE_INT_MSK BIT(9)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FE1IMR				(Offset 0x0120) */
+
+#define BIT_FS_PTCL_RELEASE_MACID_INT_EN BIT(9)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_FEIMR				(Offset 0x0120) */
+
+#define BIT_NANRPT_DONE_INT_MSK BIT(8)
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+/* 2 REG_FE1IMR				(Offset 0x0120) */
+
+#define BIT_PRETXERR_HANDLE_FSIMR BIT(8)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FE1IMR				(Offset 0x0120) */
+
+#define BIT_FS_PRETX_ERRHLD_INT_EN BIT(8)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_FE1IMR				(Offset 0x0120) */
+
+#define BIT_PRETX_ERRHLD_INT_EN BIT(8)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_FEIMR				(Offset 0x0120) */
+
+#define BIT_FTM_PTT_INT_MSK_V1 BIT(7)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_FE1IMR				(Offset 0x0120) */
+
+#define BIT_FS_GTRD_INT_EN BIT(7)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_FEIMR				(Offset 0x0120) */
+
+#define BIT_RXFTMREQ_OK_INT_MSK BIT(6)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FE1IMR				(Offset 0x0120) */
+
+#define BIT_FS_LTE_COEX_EN BIT(6)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_FEIMR				(Offset 0x0120) */
+
+#define BIT_RXFTM_INT_MSK_V1 BIT(5)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FE1IMR				(Offset 0x0120) */
+
+#define BIT_FS_WLACTOFF_INT_EN BIT(5)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_FEIMR				(Offset 0x0120) */
+
+#define BIT_TXFTM_INT_MSK_V1 BIT(4)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FE1IMR				(Offset 0x0120) */
+
+#define BIT_FS_WLACTON_INT_EN BIT(4)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_FEIMR				(Offset 0x0120) */
+
+#define BIT_LTECOEX_INT_MSK BIT(3)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FE1IMR				(Offset 0x0120) */
+
+#define BIT_FS_BTCMD_INT_EN BIT(3)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT)
+
+/* 2 REG_FEIMR				(Offset 0x0120) */
+
+#define BIT_REG_MAILBOX_TO_I2C_INT BIT(2)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_FEIMR				(Offset 0x0120) */
+
+#define BIT_MAILBOX_INT_MSK BIT(2)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FE1IMR				(Offset 0x0120) */
+
+#define BIT_FS_REG_MAILBOX_TO_I2C_INT_EN BIT(2)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_FEIMR				(Offset 0x0120) */
+
+#define BIT_TRPC_TO_INT_EN BIT(1)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_FEIMR				(Offset 0x0120) */
+
+#define BIT_FLC_DRUTO_INT_MSK BIT(1)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FE1IMR				(Offset 0x0120) */
+
+#define BIT_FS_TRPC_TO_INT_EN_V1 BIT(1)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_FEIMR				(Offset 0x0120) */
+
+#define BIT_BIT_RPC_O_T_INT_EN BIT(0)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_FEIMR				(Offset 0x0120) */
+
+#define BIT_FLC_PKTTH_INT_MSK BIT(0)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FE1IMR				(Offset 0x0120) */
+
+#define BIT_FS_RPC_O_T_INT_EN_V1 BIT(0)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_FEISR				(Offset 0x0124) */
+
+#define BIT_H2C_OK_INT BIT(31)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FE1ISR				(Offset 0x0124) */
+
+#define BIT_FS_SW_PLL_LEAVE_32K_INT BIT(31)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_FE1ISR				(Offset 0x0124) */
+
+#define BIT_CPUMGQ_DROP_BY_HOLD_TIME_INT BIT(31)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_FEISR				(Offset 0x0124) */
+
+#define BIT_H2C_CMD_FULL_INT BIT(30)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FE1ISR				(Offset 0x0124) */
+
+#define BIT_FS_FS_FWFF_FULL_INT BIT(30)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_FE1ISR				(Offset 0x0124) */
+
+#define BIT_FWFF_FULL_INT BIT(30)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_FEISR				(Offset 0x0124) */
+
+#define BIT_PWR_INT_127_V2 BIT(29)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT)
+
+/* 2 REG_FE1ISR				(Offset 0x0124) */
+
+#define BIT_BB_STOP_RX_INT BIT(29)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FE1ISR				(Offset 0x0124) */
+
+#define BIT_FS_BB_STOP_RX_INT BIT(29)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_FEISR				(Offset 0x0124) */
+
+#define BIT_PWR_INT_126 BIT(28)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FE1ISR				(Offset 0x0124) */
+
+#define BIT_FS_RXDMA2_DONE_INT BIT(28)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_FEISR				(Offset 0x0124) */
+
+#define BIT_PWR_INT_125TO96 BIT(27)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+
+/* 2 REG_FE1ISR				(Offset 0x0124) */
+
+#define BIT_FS_RXDONE3_INT BIT(27)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_FE1ISR				(Offset 0x0124) */
+
+#define BIT_FS_RXDONE3_INT_INT BIT(27)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_FEISR				(Offset 0x0124) */
+
+#define BIT_PWR_INT_95TO64_V1 BIT(26)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FE1ISR				(Offset 0x0124) */
+
+#define BIT_FS_RXDONE2_INT BIT(26)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_FEISR				(Offset 0x0124) */
+
+#define BIT_PWR_INT_63TO32_V1 BIT(25)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FE1ISR				(Offset 0x0124) */
+
+#define BIT_FS_RX_BCN_P4_INT BIT(25)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_FEISR				(Offset 0x0124) */
+
+#define BIT_PWR_INT_31TO0_V1 BIT(24)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FE1ISR				(Offset 0x0124) */
+
+#define BIT_FS_RX_BCN_P3_INT BIT(24)
+#define BIT_FS_RX_BCN_P2_INT BIT(23)
+#define BIT_FS_RX_BCN_P1_INT BIT(22)
+#define BIT_FS_RX_BCN_P0_INT BIT(21)
+#define BIT_FS_RX_UMD0_INT BIT(20)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_FEISR				(Offset 0x0124) */
+
+#define BIT_EVTQ_TXDONE_INT BIT(19)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FE1ISR				(Offset 0x0124) */
+
+#define BIT_FS_RX_UMD1_INT BIT(19)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_FEISR				(Offset 0x0124) */
+
+#define BIT_EVTQ_START_INT BIT(18)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FE1ISR				(Offset 0x0124) */
+
+#define BIT_FS_RX_BMD0_INT BIT(18)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_FEISR				(Offset 0x0124) */
+
+#define BIT_TXBCN2_OK_INT BIT(17)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FE1ISR				(Offset 0x0124) */
+
+#define BIT_FS_RX_BMD1_INT BIT(17)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_FEISR				(Offset 0x0124) */
+
+#define BIT_TXBCN2_ERR_INT BIT(16)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FE1ISR				(Offset 0x0124) */
+
+#define BIT_FS_RXDONE_INT BIT(16)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_FEISR				(Offset 0x0124) */
+
+#define BIT_DWWIN_END_INT BIT(15)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FE1ISR				(Offset 0x0124) */
+
+#define BIT_FS_WWLAN_INT BIT(15)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_FEISR				(Offset 0x0124) */
+
+#define BIT_BCN2_EARLY_INT BIT(14)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FE1ISR				(Offset 0x0124) */
+
+#define BIT_FS_SOUND_DONE_INT BIT(14)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_FEISR				(Offset 0x0124) */
+
+#define BIT_TBTT1_INT BIT(13)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+
+/* 2 REG_FE1ISR				(Offset 0x0124) */
+
+#define BIT_FS_LP_STBY_INT BIT(13)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_FEISR				(Offset 0x0124) */
+
+#define BIT_PSTIMERB_INT BIT(12)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT)
+
+/* 2 REG_FE1ISR				(Offset 0x0124) */
+
+#define BIT_FS_TRL_MTR_INT BIT(12)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_FEISR				(Offset 0x0124) */
+
+#define BIT_PSTIMERA_INT BIT(11)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FE1ISR				(Offset 0x0124) */
+
+#define BIT_FS_BF1_PRETO_INT BIT(11)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_FEISR				(Offset 0x0124) */
+
+#define BIT_P2P_RFOFF_EARLY_INT BIT(10)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FE1ISR				(Offset 0x0124) */
+
+#define BIT_FS_BF0_PRETO_INT BIT(10)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_FEISR				(Offset 0x0124) */
+
+#define BIT_MACID_RELEASE_INT BIT(9)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FE1ISR				(Offset 0x0124) */
+
+#define BIT_FS_PTCL_RELEASE_MACID_INT BIT(9)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_FEISR				(Offset 0x0124) */
+
+#define BIT_NANRPT_DONE_INT BIT(8)
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+/* 2 REG_FE1ISR				(Offset 0x0124) */
+
+#define BIT_PRETXERR_HANDLE_FSISR BIT(8)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FE1ISR				(Offset 0x0124) */
+
+#define BIT_FS_PRETX_ERRHLD_INT BIT(8)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_FE1ISR				(Offset 0x0124) */
+
+#define BIT_PRETX_ERRHLD_INT BIT(8)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_FEISR				(Offset 0x0124) */
+
+#define BIT_FTM_PTT_INT_V1 BIT(7)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_FE1ISR				(Offset 0x0124) */
+
+#define BIT_SND_RDY_INT BIT(7)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_FEISR				(Offset 0x0124) */
+
+#define BIT_RXFTMREQ_OK_INT BIT(6)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FE1ISR				(Offset 0x0124) */
+
+#define BIT_FS_LTE_COEX_INT BIT(6)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_FEISR				(Offset 0x0124) */
+
+#define BIT_RXFTM_INT_V1 BIT(5)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FE1ISR				(Offset 0x0124) */
+
+#define BIT_FS_WLACTOFF_INT BIT(5)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_FEISR				(Offset 0x0124) */
+
+#define BIT_TXFTM_INT_V1 BIT(4)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FE1ISR				(Offset 0x0124) */
+
+#define BIT_FS_WLACTON_INT BIT(4)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_FEISR				(Offset 0x0124) */
+
+#define BIT_LTECOEX_INT BIT(3)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FE1ISR				(Offset 0x0124) */
+
+#define BIT_FS_BCN_RX_INT_INT BIT(3)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_FE1ISR				(Offset 0x0124) */
+
+#define BIT_BT_CMD_INT BIT(3)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT)
+
+/* 2 REG_FEISR				(Offset 0x0124) */
+
+#define BIT_MAILBOX_TO_I2C BIT(2)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_FEISR				(Offset 0x0124) */
+
+#define BIT_MAILBOX_INT BIT(2)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FE1ISR				(Offset 0x0124) */
+
+#define BIT_FS_MAILBOX_TO_I2C_INT BIT(2)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_FEISR				(Offset 0x0124) */
+
+#define BIT_TRPC_TO_INT BIT(1)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_FEISR				(Offset 0x0124) */
+
+#define BIT_FLC_DRUTO_INT BIT(1)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FE1ISR				(Offset 0x0124) */
+
+#define BIT_FS_TRPC_TO_INT BIT(1)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_FEISR				(Offset 0x0124) */
+
+#define BIT_RPC_O_T_INT BIT(0)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_FEISR				(Offset 0x0124) */
+
+#define BIT_FLC_PKTTH_INT BIT(0)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FE1ISR				(Offset 0x0124) */
+
+#define BIT_FS_RPC_O_T_INT BIT(0)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_CPWM				(Offset 0x012C) */
+
+#define BIT_CPWM_TOGGLING BIT(31)
+
+#define BIT_SHIFT_CPWM_MOD 24
+#define BIT_MASK_CPWM_MOD 0x7f
+#define BIT_CPWM_MOD(x) (((x) & BIT_MASK_CPWM_MOD) << BIT_SHIFT_CPWM_MOD)
+#define BITS_CPWM_MOD (BIT_MASK_CPWM_MOD << BIT_SHIFT_CPWM_MOD)
+#define BIT_CLEAR_CPWM_MOD(x) ((x) & (~BITS_CPWM_MOD))
+#define BIT_GET_CPWM_MOD(x) (((x) >> BIT_SHIFT_CPWM_MOD) & BIT_MASK_CPWM_MOD)
+#define BIT_SET_CPWM_MOD(x, v) (BIT_CLEAR_CPWM_MOD(x) | BIT_CPWM_MOD(v))
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_FWIMR				(Offset 0x0130) */
+
+#define BIT_PCIE_BCNDMAERR_INT_MSK BIT(31)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FWIMR				(Offset 0x0130) */
+
+#define BIT_FS_TXBCNOK_MB7_INT_EN BIT(31)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_FWIMR				(Offset 0x0130) */
+
+#define BIT_SOUND_DONE_MSK BIT(30)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_FWIMR				(Offset 0x0130) */
+
+#define BIT_SOUND_DONE_INT_MSK BIT(30)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FWIMR				(Offset 0x0130) */
+
+#define BIT_FS_TXBCNOK_MB6_INT_EN BIT(30)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_FWIMR				(Offset 0x0130) */
+
+#define BIT_TRY_DONE_MSK BIT(29)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_FWIMR				(Offset 0x0130) */
+
+#define BIT_TRY_DONE_INT_MSK BIT(29)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FWIMR				(Offset 0x0130) */
+
+#define BIT_FS_TXBCNOK_MB5_INT_EN BIT(29)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_FWIMR				(Offset 0x0130) */
+
+#define BIT_TXRPT_CNT_FULL_MSK BIT(28)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_FWIMR				(Offset 0x0130) */
+
+#define BIT_TXRPT_CNT_FULL_INT_MSK BIT(28)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FWIMR				(Offset 0x0130) */
+
+#define BIT_FS_TXBCNOK_MB4_INT_EN BIT(28)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_FWIMR				(Offset 0x0130) */
+
+#define BIT_WLACTOFF_INT_EN BIT(27)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_FWIMR				(Offset 0x0130) */
+
+#define BIT_WLACTOFF_INT_MSK BIT(27)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FWIMR				(Offset 0x0130) */
+
+#define BIT_FS_TXBCNOK_MB3_INT_EN BIT(27)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_FWIMR				(Offset 0x0130) */
+
+#define BIT_WLACTON_INT_EN BIT(26)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_FWIMR				(Offset 0x0130) */
+
+#define BIT_WLACTON_INT_MSK BIT(26)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FWIMR				(Offset 0x0130) */
+
+#define BIT_FS_TXBCNOK_MB2_INT_EN BIT(26)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_FWIMR				(Offset 0x0130) */
+
+#define BIT_TXPKTIN_INT_EN BIT(25)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_FWIMR				(Offset 0x0130) */
+
+#define BIT_TXPKTIN_INT_MSK BIT(25)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FWIMR				(Offset 0x0130) */
+
+#define BIT_FS_TXBCNOK_MB1_INT_EN BIT(25)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_FWIMR				(Offset 0x0130) */
+
+#define BIT_TXBCNOK_MSK BIT(24)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_FWIMR				(Offset 0x0130) */
+
+#define BIT_TXBCNOK_INT_MSK BIT(24)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FWIMR				(Offset 0x0130) */
+
+#define BIT_FS_TXBCNOK_MB0_INT_EN BIT(24)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_FWIMR				(Offset 0x0130) */
+
+#define BIT_TXBCNERR_MSK BIT(23)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_FWIMR				(Offset 0x0130) */
+
+#define BIT_TXBCNERR_INT_MSK BIT(23)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FWIMR				(Offset 0x0130) */
+
+#define BIT_FS_TXBCNERR_MB7_INT_EN BIT(23)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_FWIMR				(Offset 0x0130) */
+
+#define BIT_RX_UMD0_EN BIT(22)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_FWIMR				(Offset 0x0130) */
+
+#define BIT_RX_UMD0_INT_MSK BIT(22)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FWIMR				(Offset 0x0130) */
+
+#define BIT_FS_TXBCNERR_MB6_INT_EN BIT(22)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_FWIMR				(Offset 0x0130) */
+
+#define BIT_RX_UMD1_EN BIT(21)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_FWIMR				(Offset 0x0130) */
+
+#define BIT_RX_UMD1_INT_MSK BIT(21)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FWIMR				(Offset 0x0130) */
+
+#define BIT_FS_TXBCNERR_MB5_INT_EN BIT(21)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_FWIMR				(Offset 0x0130) */
+
+#define BIT_RX_BMD0_EN BIT(20)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_FWIMR				(Offset 0x0130) */
+
+#define BIT_RX_BMD0_INT_MSK BIT(20)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FWIMR				(Offset 0x0130) */
+
+#define BIT_FS_TXBCNERR_MB4_INT_EN BIT(20)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_FWIMR				(Offset 0x0130) */
+
+#define BIT_RX_BMD1_EN BIT(19)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_FWIMR				(Offset 0x0130) */
+
+#define BIT_RX_BMD1_INT_MSK BIT(19)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FWIMR				(Offset 0x0130) */
+
+#define BIT_FS_TXBCNERR_MB3_INT_EN BIT(19)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_FWIMR				(Offset 0x0130) */
+
+#define BIT_BCN_RX_INT_EN BIT(18)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_FWIMR				(Offset 0x0130) */
+
+#define BIT_BCN_RX_INT_INT_MSK BIT(18)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FWIMR				(Offset 0x0130) */
+
+#define BIT_FS_TXBCNERR_MB2_INT_EN BIT(18)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_FWIMR				(Offset 0x0130) */
+
+#define BIT_TBTTINT_MSK BIT(17)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_FWIMR				(Offset 0x0130) */
+
+#define BIT_TBTTINT_INT_MSK BIT(17)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FWIMR				(Offset 0x0130) */
+
+#define BIT_FS_TXBCNERR_MB1_INT_EN BIT(17)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_FWIMR				(Offset 0x0130) */
+
+#define BIT_BCNERLY_MSK BIT(16)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_FWIMR				(Offset 0x0130) */
+
+#define BIT_BCNERLY_INT_MSK BIT(16)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FWIMR				(Offset 0x0130) */
+
+#define BIT_FS_TXBCNERR_MB0_INT_EN BIT(16)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_FWIMR				(Offset 0x0130) */
+
+#define BIT_BCNDMA7_MSK BIT(15)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_FWIMR				(Offset 0x0130) */
+
+#define BIT_BCNDMA7_INT_MSK BIT(15)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_FWIMR				(Offset 0x0130) */
+
+#define BIT_CPUMGN_POLLED_PKT_DONE_INT_EN BIT(15)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FWIMR				(Offset 0x0130) */
+
+#define BIT_CPU_MGQ_TXDONE_INT_EN BIT(15)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_FWIMR				(Offset 0x0130) */
+
+#define BIT_BCNDMA6_MSK BIT(14)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_FWIMR				(Offset 0x0130) */
+
+#define BIT_BCNDMA6_INT_MSK BIT(14)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FWIMR				(Offset 0x0130) */
+
+#define BIT_SIFS_OVERSPEC_INT_EN BIT(14)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_FWIMR				(Offset 0x0130) */
+
+#define BIT_BCNDMA5_MSK BIT(13)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_FWIMR				(Offset 0x0130) */
+
+#define BIT_BCNDMA5_INT_MSK BIT(13)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FWIMR				(Offset 0x0130) */
+
+#define BIT_FS_MGNTQ_RPTR_RELEASE_INT_EN BIT(13)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_FWIMR				(Offset 0x0130) */
+
+#define BIT_BCNDMA4_MSK BIT(12)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_FWIMR				(Offset 0x0130) */
+
+#define BIT_BCNDMA4_INT_MSK BIT(12)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FWIMR				(Offset 0x0130) */
+
+#define BIT_FS_MGNTQFF_TO_INT_EN BIT(12)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_FWIMR				(Offset 0x0130) */
+
+#define BIT_BCNDMA3_MSK BIT(11)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_FWIMR				(Offset 0x0130) */
+
+#define BIT_BCNDMA3_INT_MSK BIT(11)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT)
+
+/* 2 REG_FWIMR				(Offset 0x0130) */
+
+#define BIT_FS_DDMA1_LP_INT_ENBIT_CPUMGN_POLLED_PKT_BUSY_ERR_INT_EN BIT(11)
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FWIMR				(Offset 0x0130) */
+
+#define BIT_FS_CPUMGQ_ERR_INT_EN BIT(11)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT)
+
+/* 2 REG_FWIMR				(Offset 0x0130) */
+
+#define BIT_FS_DDMA1_LP_INT_EN BIT(11)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_FWIMR				(Offset 0x0130) */
+
+#define BIT_BCNDMA2_MSK BIT(10)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_FWIMR				(Offset 0x0130) */
+
+#define BIT_BCNDMA2_INT_MSK BIT(10)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8821C_SUPPORT)
+
+/* 2 REG_FWIMR				(Offset 0x0130) */
+
+#define BIT_FS_DDMA1_HP_INT_EN BIT(10)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_FWIMR				(Offset 0x0130) */
+
+#define BIT_BCNDMA1_MSK BIT(9)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_FWIMR				(Offset 0x0130) */
+
+#define BIT_BCNDMA1_INT_MSK BIT(9)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FWIMR				(Offset 0x0130) */
+
+#define BIT_FS_DDMA0_LP_INT_EN BIT(9)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_FWIMR				(Offset 0x0130) */
+
+#define BIT_BCNDMA0_MSK BIT(8)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_FWIMR				(Offset 0x0130) */
+
+#define BIT_BCNDMA0_INT_MSK BIT(8)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FWIMR				(Offset 0x0130) */
+
+#define BIT_FS_DDMA0_HP_INT_EN BIT(8)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_FWIMR				(Offset 0x0130) */
+
+#define BIT_LP_STBY_MSK BIT(7)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_FWIMR				(Offset 0x0130) */
+
+#define BIT_LP_STBY_INT_MSK BIT(7)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FWIMR				(Offset 0x0130) */
+
+#define BIT_FS_TRXRPT_INT_EN BIT(7)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_FWIMR				(Offset 0x0130) */
+
+#define BIT_CTWENDINT_MSK BIT(6)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_FWIMR				(Offset 0x0130) */
+
+#define BIT_CTWENDINT_INT_MSK BIT(6)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FWIMR				(Offset 0x0130) */
+
+#define BIT_FS_C2H_W_READY_INT_EN BIT(6)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_FWIMR				(Offset 0x0130) */
+
+#define BIT_HRCV_MSK BIT(5)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_FWIMR				(Offset 0x0130) */
+
+#define BIT_HRCV_INT_MSK BIT(5)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FWIMR				(Offset 0x0130) */
+
+#define BIT_FS_HRCV_INT_EN BIT(5)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_FWIMR				(Offset 0x0130) */
+
+#define BIT_H2CCMD_MSK BIT(4)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_FWIMR				(Offset 0x0130) */
+
+#define BIT_H2CCMD_INT_MSK BIT(4)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FWIMR				(Offset 0x0130) */
+
+#define BIT_FS_H2CCMD_INT_EN BIT(4)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_FWIMR				(Offset 0x0130) */
+
+#define BIT_RXDONE_MSK BIT(3)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_FWIMR				(Offset 0x0130) */
+
+#define BIT_RXDONE_INT_MSK BIT(3)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FWIMR				(Offset 0x0130) */
+
+#define BIT_FS_TXPKTIN_INT_EN BIT(3)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_FWIMR				(Offset 0x0130) */
+
+#define BIT_ERRORHDL_MSK BIT(2)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_FWIMR				(Offset 0x0130) */
+
+#define BIT_ERRORHDL_INT_MSK BIT(2)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FWIMR				(Offset 0x0130) */
+
+#define BIT_FS_ERRORHDL_INT_EN BIT(2)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_FWIMR				(Offset 0x0130) */
+
+#define BIT_TXCCX_MSK_FW BIT(1)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_FWIMR				(Offset 0x0130) */
+
+#define BIT_TXCCX_INT_MSK BIT(1)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FWIMR				(Offset 0x0130) */
+
+#define BIT_FS_TXCCX_INT_EN BIT(1)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_FWIMR				(Offset 0x0130) */
+
+#define BIT_TXCLOSE_MSK BIT(0)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_FWIMR				(Offset 0x0130) */
+
+#define BIT_TXCLOSE_INT_MSK BIT(0)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FWIMR				(Offset 0x0130) */
+
+#define BIT_FS_TXCLOSE_INT_EN BIT(0)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_FWISR				(Offset 0x0134) */
+
+#define BIT_PCIE_BCNDMAERR_INT BIT(31)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FWISR				(Offset 0x0134) */
+
+#define BIT_FS_TXBCNOK_MB7_INT BIT(31)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_FWISR				(Offset 0x0134) */
+
+#define BIT_SOUND_DONE_INT BIT(30)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FWISR				(Offset 0x0134) */
+
+#define BIT_FS_TXBCNOK_MB6_INT BIT(30)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_FWISR				(Offset 0x0134) */
+
+#define BIT_TRY_DONE_INT BIT(29)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FWISR				(Offset 0x0134) */
+
+#define BIT_FS_TXBCNOK_MB5_INT BIT(29)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_FWISR				(Offset 0x0134) */
+
+#define BIT_TXRPT_CNT_FULL_INT BIT(28)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FWISR				(Offset 0x0134) */
+
+#define BIT_FS_TXBCNOK_MB4_INT BIT(28)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_FWISR				(Offset 0x0134) */
+
+#define BIT_WLACTOFF_INT BIT(27)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FWISR				(Offset 0x0134) */
+
+#define BIT_FS_TXBCNOK_MB3_INT BIT(27)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_FWISR				(Offset 0x0134) */
+
+#define BIT_WLACTON_INT BIT(26)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FWISR				(Offset 0x0134) */
+
+#define BIT_FS_TXBCNOK_MB2_INT BIT(26)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_FWISR				(Offset 0x0134) */
+
+#define BIT_TXPKTIN_INT BIT(25)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FWISR				(Offset 0x0134) */
+
+#define BIT_FS_TXBCNOK_MB1_INT BIT(25)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_FWISR				(Offset 0x0134) */
+
+#define BIT_TXBCNOK_INT BIT(24)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FWISR				(Offset 0x0134) */
+
+#define BIT_FS_TXBCNOK_MB0_INT BIT(24)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_FWISR				(Offset 0x0134) */
+
+#define BIT_TXBCNERR_INT BIT(23)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FWISR				(Offset 0x0134) */
+
+#define BIT_FS_TXBCNERR_MB7_INT BIT(23)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_FWISR				(Offset 0x0134) */
+
+#define BIT_RX_UMD0_INT BIT(22)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FWISR				(Offset 0x0134) */
+
+#define BIT_FS_TXBCNERR_MB6_INT BIT(22)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_FWISR				(Offset 0x0134) */
+
+#define BIT_RX_UMD1_INT BIT(21)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FWISR				(Offset 0x0134) */
+
+#define BIT_FS_TXBCNERR_MB5_INT BIT(21)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_FWISR				(Offset 0x0134) */
+
+#define BIT_RX_BMD0_INT BIT(20)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FWISR				(Offset 0x0134) */
+
+#define BIT_FS_TXBCNERR_MB4_INT BIT(20)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_FWISR				(Offset 0x0134) */
+
+#define BIT_RX_BMD1_INT BIT(19)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FWISR				(Offset 0x0134) */
+
+#define BIT_FS_TXBCNERR_MB3_INT BIT(19)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_FWISR				(Offset 0x0134) */
+
+#define BIT_BCN_RX_INT_INT BIT(18)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FWISR				(Offset 0x0134) */
+
+#define BIT_FS_TXBCNERR_MB2_INT BIT(18)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_FWISR				(Offset 0x0134) */
+
+#define BIT_TBTTINT_INT BIT(17)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FWISR				(Offset 0x0134) */
+
+#define BIT_FS_TXBCNERR_MB1_INT BIT(17)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_FWISR				(Offset 0x0134) */
+
+#define BIT_BCNERLY_INT BIT(16)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FWISR				(Offset 0x0134) */
+
+#define BIT_FS_TXBCNERR_MB0_INT BIT(16)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_FWISR				(Offset 0x0134) */
+
+#define BIT_BCNDMA7_INT BIT(15)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_FWISR				(Offset 0x0134) */
+
+#define BIT_CPUMGN_POLLED_PKT_DONE_INT BIT(15)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FWISR				(Offset 0x0134) */
+
+#define BIT_CPU_MGQ_TXDONE_INT BIT(15)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_FWISR				(Offset 0x0134) */
+
+#define BIT_BCNDMA6_INT BIT(14)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FWISR				(Offset 0x0134) */
+
+#define BIT_SIFS_OVERSPEC_INT BIT(14)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_FWISR				(Offset 0x0134) */
+
+#define BIT_BCNDMA5_INT BIT(13)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FWISR				(Offset 0x0134) */
+
+#define BIT_FS_MGNTQ_RPTR_RELEASE_INT BIT(13)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_FWISR				(Offset 0x0134) */
+
+#define BIT_BCNDMA4_INT BIT(12)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FWISR				(Offset 0x0134) */
+
+#define BIT_FS_MGNTQFF_TO_INT BIT(12)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_FWISR				(Offset 0x0134) */
+
+#define BIT_BCNDMA3_INT BIT(11)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT)
+
+/* 2 REG_FWISR				(Offset 0x0134) */
+
+#define BIT_FS_DDMA1_LP_INTBIT_CPUMGN_POLLED_PKT_BUSY_ERR_INT BIT(11)
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FWISR				(Offset 0x0134) */
+
+#define BIT_FS_CPUMGQ_ERR_INT BIT(11)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT)
+
+/* 2 REG_FWISR				(Offset 0x0134) */
+
+#define BIT_FS_DDMA1_LP_INT BIT(11)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_FWISR				(Offset 0x0134) */
+
+#define BIT_BCNDMA2_INT BIT(10)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8821C_SUPPORT)
+
+/* 2 REG_FWISR				(Offset 0x0134) */
+
+#define BIT_FS_DDMA1_HP_INT BIT(10)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_FWISR				(Offset 0x0134) */
+
+#define BIT_FWCMD_PKTIN_INT BIT(10)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_FWISR				(Offset 0x0134) */
+
+#define BIT_BCNDMA1_INT BIT(9)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FWISR				(Offset 0x0134) */
+
+#define BIT_FS_DDMA0_LP_INT BIT(9)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_FWISR				(Offset 0x0134) */
+
+#define BIT_BCNDMA0_INT BIT(8)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FWISR				(Offset 0x0134) */
+
+#define BIT_FS_DDMA0_HP_INT BIT(8)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_FWISR				(Offset 0x0134) */
+
+#define BIT_LP_STBY_INT BIT(7)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FWISR				(Offset 0x0134) */
+
+#define BIT_FS_TRXRPT_INT BIT(7)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_FWISR				(Offset 0x0134) */
+
+#define BIT_CTWENDINT_INT BIT(6)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FWISR				(Offset 0x0134) */
+
+#define BIT_FS_C2H_W_READY_INT BIT(6)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_FWISR				(Offset 0x0134) */
+
+#define BIT_HRCV_INT BIT(5)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FWISR				(Offset 0x0134) */
+
+#define BIT_FS_HRCV_INT BIT(5)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_FWISR				(Offset 0x0134) */
+
+#define BIT_H2CCMD_INT BIT(4)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FWISR				(Offset 0x0134) */
+
+#define BIT_FS_H2CCMD_INT BIT(4)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_FWISR				(Offset 0x0134) */
+
+#define BIT_RXDONE_INT BIT(3)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FWISR				(Offset 0x0134) */
+
+#define BIT_FS_TXPKTIN_INT BIT(3)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_FWISR				(Offset 0x0134) */
+
+#define BIT_ERRORHDL_INT BIT(2)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FWISR				(Offset 0x0134) */
+
+#define BIT_FS_ERRORHDL_INT BIT(2)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_FWISR				(Offset 0x0134) */
+
+#define BIT_TXCCX_INT BIT(1)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FWISR				(Offset 0x0134) */
+
+#define BIT_FS_TXCCX_INT BIT(1)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_FWISR				(Offset 0x0134) */
+
+#define BIT_TXCLOSE_INT BIT(0)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FWISR				(Offset 0x0134) */
+
+#define BIT_FS_TXCLOSE_INT BIT(0)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_FTIMR				(Offset 0x0138) */
+
+#define BIT_GTINT6_MSK BIT(31)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_FTIMR				(Offset 0x0138) */
+
+#define BIT_GT6INT_MSK BIT(31)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_FTIMR				(Offset 0x0138) */
+
+#define BIT_TX_NULL1_INT_MSK BIT(30)
+#define BIT_TX_NULL0_INT_MSK BIT(29)
+#define BIT_MTI_BCNIVLEAR_INT_MSK BIT(28)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_FTIMR				(Offset 0x0138) */
+
+#define BIT_ATIMINT_MSK BIT(27)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_FTIMR				(Offset 0x0138) */
+
+#define BIT_ATIM_INT_MSK BIT(27)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_FTIMR				(Offset 0x0138) */
+
+#define BIT_WWLAN_INT_EN BIT(26)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_FTIMR				(Offset 0x0138) */
+
+#define BIT_WWLAN_INT_MSK BIT(26)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_FTIMR				(Offset 0x0138) */
+
+#define BIT_C2H_W_READY_EN BIT(25)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_FTIMR				(Offset 0x0138) */
+
+#define BIT_C2H_W_READY_MSK BIT(25)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_FTIMR				(Offset 0x0138) */
+
+#define BIT_TRL_MTR_EN BIT(24)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_FTIMR				(Offset 0x0138) */
+
+#define BIT_TRL_MTR_INT_MSK BIT(24)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_FTIMR				(Offset 0x0138) */
+
+#define BIT_CLR_PS_STATUS_MSK BIT(23)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FTIMR				(Offset 0x0138) */
+
+#define BIT_PS_TIMER_C_EARLY_INT_EN BIT(23)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_FTIMR				(Offset 0x0138) */
+
+#define BIT_RETRIEVE_BUFFERED_MSK BIT(22)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_FTIMR				(Offset 0x0138) */
+
+#define BIT_RETRIEVE_BUFFERED_INT_MSK BIT(22)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FTIMR				(Offset 0x0138) */
+
+#define BIT_PS_TIMER_B_EARLY_INT_EN BIT(22)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_FTIMR				(Offset 0x0138) */
+
+#define BIT_RPWMINT2_MSK BIT(21)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_FTIMR				(Offset 0x0138) */
+
+#define BIT_RPWM2INT_MSK BIT(21)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FTIMR				(Offset 0x0138) */
+
+#define BIT_PS_TIMER_A_EARLY_INT_EN BIT(21)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_FTIMR				(Offset 0x0138) */
+
+#define BIT_TSF_BIT32_TOGGLE_MSK_V1 BIT(20)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_FTIMR				(Offset 0x0138) */
+
+#define BIT_TSF_BIT32_TOGGLE_INT_MSK BIT(20)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FTIMR				(Offset 0x0138) */
+
+#define BIT_CPUMGQ_TX_TIMER_EARLY_INT_EN BIT(20)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_FTIMR				(Offset 0x0138) */
+
+#define BIT_TRIGGER_PKT_MSK BIT(19)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FTIMR				(Offset 0x0138) */
+
+#define BIT_PS_TIMER_C_INT_EN BIT(19)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_FTIMR				(Offset 0x0138) */
+
+#define BIT_FW_BTCMD_INTMSK BIT(18)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_FTIMR				(Offset 0x0138) */
+
+#define BIT_FW_BTCMD_INT_MSK BIT(18)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FTIMR				(Offset 0x0138) */
+
+#define BIT_PS_TIMER_B_INT_EN BIT(18)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_FTIMR				(Offset 0x0138) */
+
+#define BIT_P2P_RFOFF_INTMSK BIT(17)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_FTIMR				(Offset 0x0138) */
+
+#define BIT_P2P_RFOFF_INT_MSK BIT(17)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FTIMR				(Offset 0x0138) */
+
+#define BIT_PS_TIMER_A_INT_EN BIT(17)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_FTIMR				(Offset 0x0138) */
+
+#define BIT_P2P_RFON_INTMSK BIT(16)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_FTIMR				(Offset 0x0138) */
+
+#define BIT_P2P_RFON_INT_MSK BIT(16)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FTIMR				(Offset 0x0138) */
+
+#define BIT_CPUMGQ_TX_TIMER_INT_EN BIT(16)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_FTIMR				(Offset 0x0138) */
+
+#define BIT_TXBCN1ERR_MSK BIT(15)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_FTIMR				(Offset 0x0138) */
+
+#define BIT_TX_BCN1ERR_INT_MSK BIT(15)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FTIMR				(Offset 0x0138) */
+
+#define BIT_FS_PS_TIMEOUT2_EN BIT(15)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_FTIMR				(Offset 0x0138) */
+
+#define BIT_TXBCN1OK_MSK BIT(14)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_FTIMR				(Offset 0x0138) */
+
+#define BIT_TX_BCN1OK_INT_MSK BIT(14)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FTIMR				(Offset 0x0138) */
+
+#define BIT_FS_PS_TIMEOUT1_EN BIT(14)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_FTIMR				(Offset 0x0138) */
+
+#define BIT_FT_ATIMEND_EMSK BIT(13)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_FTIMR				(Offset 0x0138) */
+
+#define BIT_FT_ATIMEND_E_MSK BIT(13)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FTIMR				(Offset 0x0138) */
+
+#define BIT_FS_PS_TIMEOUT0_EN BIT(13)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_FTIMR				(Offset 0x0138) */
+
+#define BIT_BCNDMAINT_EMSK BIT(12)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_FTIMR				(Offset 0x0138) */
+
+#define BIT_BCNDMAINT_E_MSK_V1 BIT(12)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_FTIMR				(Offset 0x0138) */
+
+#define BIT_FS_GTINT12_EN BIT(12)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_FTIMR				(Offset 0x0138) */
+
+#define BIT_GTINT5_MSK BIT(11)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_FTIMR				(Offset 0x0138) */
+
+#define BIT_GT5INT_MSK BIT(11)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_FTIMR				(Offset 0x0138) */
+
+#define BIT_FS_GTINT11_EN BIT(11)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_FTIMR				(Offset 0x0138) */
+
+#define BIT_EOSP_INT_MSK BIT(10)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_FTIMR				(Offset 0x0138) */
+
+#define BIT_FS_GTINT10_EN BIT(10)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_FTIMR				(Offset 0x0138) */
+
+#define BIT_RX_BCN_E_MSK BIT(9)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_FTIMR				(Offset 0x0138) */
+
+#define BIT_RX_BCN_E_INT_MSK BIT(9)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_FTIMR				(Offset 0x0138) */
+
+#define BIT_FS_GTINT9_EN BIT(9)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_FTIMR				(Offset 0x0138) */
+
+#define BIT_RPWM_INT_EN BIT(8)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_FTIMR				(Offset 0x0138) */
+
+#define BIT_RPWMINT_MSK BIT(8)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FTIMR				(Offset 0x0138) */
+
+#define BIT_FS_GTINT8_EN BIT(8)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_FTIMR				(Offset 0x0138) */
+
+#define BIT_PSTIMER_MSK BIT(7)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_FTIMR				(Offset 0x0138) */
+
+#define BIT_PSTIMER_INT_MSK BIT(7)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FTIMR				(Offset 0x0138) */
+
+#define BIT_FS_GTINT7_EN BIT(7)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_FTIMR				(Offset 0x0138) */
+
+#define BIT_TIMEOUT1_MSK BIT(6)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_FTIMR				(Offset 0x0138) */
+
+#define BIT_TIMEOUT1_INT_MSK BIT(6)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FTIMR				(Offset 0x0138) */
+
+#define BIT_FS_GTINT6_EN BIT(6)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_FTIMR				(Offset 0x0138) */
+
+#define BIT_TIMEOUT0_MSK BIT(5)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_FTIMR				(Offset 0x0138) */
+
+#define BIT_TIMEOUT0_INT_MSK BIT(5)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FTIMR				(Offset 0x0138) */
+
+#define BIT_FS_GTINT5_EN BIT(5)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_FTIMR				(Offset 0x0138) */
+
+#define BIT_FT_GTINT4_MSK BIT(4)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_FTIMR				(Offset 0x0138) */
+
+#define BIT_FT_GT4INT_MSK BIT(4)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FTIMR				(Offset 0x0138) */
+
+#define BIT_FS_GTINT4_EN BIT(4)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_FTIMR				(Offset 0x0138) */
+
+#define BIT_FT_GTINT3_MSK BIT(3)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_FTIMR				(Offset 0x0138) */
+
+#define BIT_FT_GT3INT_MSK BIT(3)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FTIMR				(Offset 0x0138) */
+
+#define BIT_FS_GTINT3_EN BIT(3)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_FTIMR				(Offset 0x0138) */
+
+#define BIT_GTINT2_MSK BIT(2)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_FTIMR				(Offset 0x0138) */
+
+#define BIT_GT2INT_MSK BIT(2)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FTIMR				(Offset 0x0138) */
+
+#define BIT_FS_GTINT2_EN BIT(2)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_FTIMR				(Offset 0x0138) */
+
+#define BIT_GTINT1_MSK BIT(1)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_FTIMR				(Offset 0x0138) */
+
+#define BIT_GT1INT_MSK BIT(1)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FTIMR				(Offset 0x0138) */
+
+#define BIT_FS_GTINT1_EN BIT(1)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_FTIMR				(Offset 0x0138) */
+
+#define BIT_GTINT0_MSK BIT(0)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_FTIMR				(Offset 0x0138) */
+
+#define BIT_GT0INT_MSK BIT(0)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FTIMR				(Offset 0x0138) */
+
+#define BIT_FS_GTINT0_EN BIT(0)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_FTISR				(Offset 0x013C) */
+
+#define BIT_GT6INT BIT(31)
+#define BIT_TX_NULL1_INT BIT(30)
+#define BIT_TX_NULL0_INT BIT(29)
+#define BIT_MTI_BCNIVLEAR_INT BIT(28)
+#define BIT_ATIM_INT BIT(27)
+#define BIT_WWLAN_INT BIT(26)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_FTISR				(Offset 0x013C) */
+
+#define BIT_PS_TIMER_5_EARLY__INT BIT(26)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_FTISR				(Offset 0x013C) */
+
+#define BIT_C2H_W_READY BIT(25)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_FTISR				(Offset 0x013C) */
+
+#define BIT_PS_TIMER_4_EARLY__INT BIT(25)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_FTISR				(Offset 0x013C) */
+
+#define BIT_TRL_MTR_INT BIT(24)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_FTISR				(Offset 0x013C) */
+
+#define BIT_PS_TIMER_3_EARLY__INT BIT(24)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_FTISR				(Offset 0x013C) */
+
+#define BIT_CLR_PS_STATUS BIT(23)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FTISR				(Offset 0x013C) */
+
+#define BIT_PS_TIMER_C_EARLY__INT BIT(23)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_FTISR				(Offset 0x013C) */
+
+#define BIT_PS_TIMER_2_EARLY__INT BIT(23)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_FTISR				(Offset 0x013C) */
+
+#define BIT_RETRIEVE_BUFFERED_INT BIT(22)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FTISR				(Offset 0x013C) */
+
+#define BIT_PS_TIMER_B_EARLY__INT BIT(22)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_FTISR				(Offset 0x013C) */
+
+#define BIT_PS_TIMER_1_EARLY__INT BIT(22)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_FTISR				(Offset 0x013C) */
+
+#define BIT_RPWM2INT BIT(21)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FTISR				(Offset 0x013C) */
+
+#define BIT_PS_TIMER_A_EARLY__INT BIT(21)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_FTISR				(Offset 0x013C) */
+
+#define BIT_PS_TIMER_0_EARLY__INT BIT(21)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_FTISR				(Offset 0x013C) */
+
+#define BIT_TSF_BIT32_TOGGLE_INT_V1 BIT(20)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FTISR				(Offset 0x013C) */
+
+#define BIT_CPUMGQ_TX_TIMER_EARLY_INT BIT(20)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_FTISR				(Offset 0x013C) */
+
+#define BIT_TRIGGER_PKT BIT(19)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FTISR				(Offset 0x013C) */
+
+#define BIT_PS_TIMER_C_INT BIT(19)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_FTISR				(Offset 0x013C) */
+
+#define BIT_PS_TIMER_5_INT BIT(19)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_FTISR				(Offset 0x013C) */
+
+#define BIT_FW_BTCMD_INT BIT(18)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FTISR				(Offset 0x013C) */
+
+#define BIT_PS_TIMER_B_INT BIT(18)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_FTISR				(Offset 0x013C) */
+
+#define BIT_PS_TIMER_4_INT BIT(18)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_FTISR				(Offset 0x013C) */
+
+#define BIT_P2P_RFOFF_INT BIT(17)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FTISR				(Offset 0x013C) */
+
+#define BIT_PS_TIMER_A_INT BIT(17)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_FTISR				(Offset 0x013C) */
+
+#define BIT_PS_TIMER_3_INT BIT(17)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_FTISR				(Offset 0x013C) */
+
+#define BIT_P2P_RFON_INT BIT(16)
+
+#define BIT_SHIFT_LLTINI_PDATA 16
+#define BIT_MASK_LLTINI_PDATA 0xff
+#define BIT_LLTINI_PDATA(x)                                                    \
+	(((x) & BIT_MASK_LLTINI_PDATA) << BIT_SHIFT_LLTINI_PDATA)
+#define BITS_LLTINI_PDATA (BIT_MASK_LLTINI_PDATA << BIT_SHIFT_LLTINI_PDATA)
+#define BIT_CLEAR_LLTINI_PDATA(x) ((x) & (~BITS_LLTINI_PDATA))
+#define BIT_GET_LLTINI_PDATA(x)                                                \
+	(((x) >> BIT_SHIFT_LLTINI_PDATA) & BIT_MASK_LLTINI_PDATA)
+#define BIT_SET_LLTINI_PDATA(x, v)                                             \
+	(BIT_CLEAR_LLTINI_PDATA(x) | BIT_LLTINI_PDATA(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FTISR				(Offset 0x013C) */
+
+#define BIT_CPUMGQ_TX_TIMER_INT BIT(16)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_FTISR				(Offset 0x013C) */
+
+#define BIT_TX_BCN1ERR_INT BIT(15)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FTISR				(Offset 0x013C) */
+
+#define BIT_FS_PS_TIMEOUT2_INT BIT(15)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_FTISR				(Offset 0x013C) */
+
+#define BIT_PS_TIMER_2_INT BIT(15)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_FTISR				(Offset 0x013C) */
+
+#define BIT_TX_BCN1OK_INT BIT(14)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FTISR				(Offset 0x013C) */
+
+#define BIT_FS_PS_TIMEOUT1_INT BIT(14)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_FTISR				(Offset 0x013C) */
+
+#define BIT_PS_TIMER_1_INT BIT(14)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_FTISR				(Offset 0x013C) */
+
+#define BIT_FT_ATIMEND_E BIT(13)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FTISR				(Offset 0x013C) */
+
+#define BIT_FS_PS_TIMEOUT0_INT BIT(13)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_FTISR				(Offset 0x013C) */
+
+#define BIT_PS_TIMER_0_INT BIT(13)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_FTISR				(Offset 0x013C) */
+
+#define BIT_BCNDMAINT_E_V1 BIT(12)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_FTISR				(Offset 0x013C) */
+
+#define BIT_FS_GTINT12_INT BIT(12)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_FTISR				(Offset 0x013C) */
+
+#define BIT_GT5INT BIT(11)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_FTISR				(Offset 0x013C) */
+
+#define BIT_FS_GTINT11_INT BIT(11)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_FTISR				(Offset 0x013C) */
+
+#define BIT_EOSP_INT BIT(10)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_FTISR				(Offset 0x013C) */
+
+#define BIT_FS_GTINT10_INT BIT(10)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_FTISR				(Offset 0x013C) */
+
+#define BIT_RX_BCN_E_INT BIT(9)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_FTISR				(Offset 0x013C) */
+
+#define BIT_FS_GTINT9_INT BIT(9)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_FTISR				(Offset 0x013C) */
+
+#define BIT_RPWMINT BIT(8)
+
+#define BIT_SHIFT_LLTINI_ADDR 8
+#define BIT_MASK_LLTINI_ADDR 0xff
+#define BIT_LLTINI_ADDR(x)                                                     \
+	(((x) & BIT_MASK_LLTINI_ADDR) << BIT_SHIFT_LLTINI_ADDR)
+#define BITS_LLTINI_ADDR (BIT_MASK_LLTINI_ADDR << BIT_SHIFT_LLTINI_ADDR)
+#define BIT_CLEAR_LLTINI_ADDR(x) ((x) & (~BITS_LLTINI_ADDR))
+#define BIT_GET_LLTINI_ADDR(x)                                                 \
+	(((x) >> BIT_SHIFT_LLTINI_ADDR) & BIT_MASK_LLTINI_ADDR)
+#define BIT_SET_LLTINI_ADDR(x, v)                                              \
+	(BIT_CLEAR_LLTINI_ADDR(x) | BIT_LLTINI_ADDR(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FTISR				(Offset 0x013C) */
+
+#define BIT_FS_GTINT8_INT BIT(8)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_FTISR				(Offset 0x013C) */
+
+#define BIT_PSTIMER_INT BIT(7)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FTISR				(Offset 0x013C) */
+
+#define BIT_FS_GTINT7_INT BIT(7)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_FTISR				(Offset 0x013C) */
+
+#define BIT_TIMEOUT1_INT BIT(6)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FTISR				(Offset 0x013C) */
+
+#define BIT_FS_GTINT6_INT BIT(6)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_FTISR				(Offset 0x013C) */
+
+#define BIT_TIMEOUT0_INT BIT(5)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FTISR				(Offset 0x013C) */
+
+#define BIT_FS_GTINT5_INT BIT(5)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_FTISR				(Offset 0x013C) */
+
+#define BIT_FT_GT4INT BIT(4)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FTISR				(Offset 0x013C) */
+
+#define BIT_FS_GTINT4_INT BIT(4)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_FTISR				(Offset 0x013C) */
+
+#define BIT_FT_GT3INT BIT(3)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FTISR				(Offset 0x013C) */
+
+#define BIT_FS_GTINT3_INT BIT(3)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_FTISR				(Offset 0x013C) */
+
+#define BIT_GT2INT BIT(2)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FTISR				(Offset 0x013C) */
+
+#define BIT_FS_GTINT2_INT BIT(2)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_FTISR				(Offset 0x013C) */
+
+#define BIT_GT1INT BIT(1)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FTISR				(Offset 0x013C) */
+
+#define BIT_FS_GTINT1_INT BIT(1)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_FTISR				(Offset 0x013C) */
+
+#define BIT_GT0INT BIT(0)
+
+#define BIT_SHIFT_LLTINI_HDATA 0
+#define BIT_MASK_LLTINI_HDATA 0xff
+#define BIT_LLTINI_HDATA(x)                                                    \
+	(((x) & BIT_MASK_LLTINI_HDATA) << BIT_SHIFT_LLTINI_HDATA)
+#define BITS_LLTINI_HDATA (BIT_MASK_LLTINI_HDATA << BIT_SHIFT_LLTINI_HDATA)
+#define BIT_CLEAR_LLTINI_HDATA(x) ((x) & (~BITS_LLTINI_HDATA))
+#define BIT_GET_LLTINI_HDATA(x)                                                \
+	(((x) >> BIT_SHIFT_LLTINI_HDATA) & BIT_MASK_LLTINI_HDATA)
+#define BIT_SET_LLTINI_HDATA(x, v)                                             \
+	(BIT_CLEAR_LLTINI_HDATA(x) | BIT_LLTINI_HDATA(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FTISR				(Offset 0x013C) */
+
+#define BIT_FS_GTINT0_INT BIT(0)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_PKTBUF_DBG_CTRL			(Offset 0x0140) */
+
+#define BIT_SHIFT_PKTBUF_WRITE_EN 24
+#define BIT_MASK_PKTBUF_WRITE_EN 0xff
+#define BIT_PKTBUF_WRITE_EN(x)                                                 \
+	(((x) & BIT_MASK_PKTBUF_WRITE_EN) << BIT_SHIFT_PKTBUF_WRITE_EN)
+#define BITS_PKTBUF_WRITE_EN                                                   \
+	(BIT_MASK_PKTBUF_WRITE_EN << BIT_SHIFT_PKTBUF_WRITE_EN)
+#define BIT_CLEAR_PKTBUF_WRITE_EN(x) ((x) & (~BITS_PKTBUF_WRITE_EN))
+#define BIT_GET_PKTBUF_WRITE_EN(x)                                             \
+	(((x) >> BIT_SHIFT_PKTBUF_WRITE_EN) & BIT_MASK_PKTBUF_WRITE_EN)
+#define BIT_SET_PKTBUF_WRITE_EN(x, v)                                          \
+	(BIT_CLEAR_PKTBUF_WRITE_EN(x) | BIT_PKTBUF_WRITE_EN(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_PKTBUF_DBG_CTRL			(Offset 0x0140) */
+
+#define BIT_TXPKT_BUF_READ_EN BIT(23)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_PKTBUF_DBG_CTRL			(Offset 0x0140) */
+
+#define BIT_TXPKTBUF_DBG BIT(23)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_PKTBUF_DBG_CTRL			(Offset 0x0140) */
+
+#define BIT_TXRPTBUF_DBG BIT(23)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_PKTBUF_DBG_CTRL			(Offset 0x0140) */
+
+#define BIT_TXRPT_BUF_READ_EN BIT(20)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_PKTBUF_DBG_CTRL			(Offset 0x0140) */
+
+#define BIT_TXRPTBUF_DBG_V2 BIT(20)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_PKTBUF_DBG_CTRL			(Offset 0x0140) */
+
+#define BIT_TXPKTBUF_DBG_V2 BIT(20)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_PKTBUF_DBG_CTRL			(Offset 0x0140) */
+
+#define BIT_RXPKT_BUF_READ_EN BIT(16)
+
+#define BIT_SHIFT_PKTBUF_ADDR 0
+#define BIT_MASK_PKTBUF_ADDR 0x1fff
+#define BIT_PKTBUF_ADDR(x)                                                     \
+	(((x) & BIT_MASK_PKTBUF_ADDR) << BIT_SHIFT_PKTBUF_ADDR)
+#define BITS_PKTBUF_ADDR (BIT_MASK_PKTBUF_ADDR << BIT_SHIFT_PKTBUF_ADDR)
+#define BIT_CLEAR_PKTBUF_ADDR(x) ((x) & (~BITS_PKTBUF_ADDR))
+#define BIT_GET_PKTBUF_ADDR(x)                                                 \
+	(((x) >> BIT_SHIFT_PKTBUF_ADDR) & BIT_MASK_PKTBUF_ADDR)
+#define BIT_SET_PKTBUF_ADDR(x, v)                                              \
+	(BIT_CLEAR_PKTBUF_ADDR(x) | BIT_PKTBUF_ADDR(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_PKTBUF_DBG_DATA_L			(Offset 0x0144) */
+
+#define BIT_SHIFT_PKTBUF_DBG_DATA_L 0
+#define BIT_MASK_PKTBUF_DBG_DATA_L 0xffffffffL
+#define BIT_PKTBUF_DBG_DATA_L(x)                                               \
+	(((x) & BIT_MASK_PKTBUF_DBG_DATA_L) << BIT_SHIFT_PKTBUF_DBG_DATA_L)
+#define BITS_PKTBUF_DBG_DATA_L                                                 \
+	(BIT_MASK_PKTBUF_DBG_DATA_L << BIT_SHIFT_PKTBUF_DBG_DATA_L)
+#define BIT_CLEAR_PKTBUF_DBG_DATA_L(x) ((x) & (~BITS_PKTBUF_DBG_DATA_L))
+#define BIT_GET_PKTBUF_DBG_DATA_L(x)                                           \
+	(((x) >> BIT_SHIFT_PKTBUF_DBG_DATA_L) & BIT_MASK_PKTBUF_DBG_DATA_L)
+#define BIT_SET_PKTBUF_DBG_DATA_L(x, v)                                        \
+	(BIT_CLEAR_PKTBUF_DBG_DATA_L(x) | BIT_PKTBUF_DBG_DATA_L(v))
+
+/* 2 REG_PKTBUF_DBG_DATA_H			(Offset 0x0148) */
+
+#define BIT_SHIFT_PKTBUF_DBG_DATA_H 0
+#define BIT_MASK_PKTBUF_DBG_DATA_H 0xffffffffL
+#define BIT_PKTBUF_DBG_DATA_H(x)                                               \
+	(((x) & BIT_MASK_PKTBUF_DBG_DATA_H) << BIT_SHIFT_PKTBUF_DBG_DATA_H)
+#define BITS_PKTBUF_DBG_DATA_H                                                 \
+	(BIT_MASK_PKTBUF_DBG_DATA_H << BIT_SHIFT_PKTBUF_DBG_DATA_H)
+#define BIT_CLEAR_PKTBUF_DBG_DATA_H(x) ((x) & (~BITS_PKTBUF_DBG_DATA_H))
+#define BIT_GET_PKTBUF_DBG_DATA_H(x)                                           \
+	(((x) >> BIT_SHIFT_PKTBUF_DBG_DATA_H) & BIT_MASK_PKTBUF_DBG_DATA_H)
+#define BIT_SET_PKTBUF_DBG_DATA_H(x, v)                                        \
+	(BIT_CLEAR_PKTBUF_DBG_DATA_H(x) | BIT_PKTBUF_DBG_DATA_H(v))
+
+/* 2 REG_CPWM2				(Offset 0x014C) */
+
+#define BIT_SHIFT_L0S_TO_RCVY_NUM 16
+#define BIT_MASK_L0S_TO_RCVY_NUM 0xff
+#define BIT_L0S_TO_RCVY_NUM(x)                                                 \
+	(((x) & BIT_MASK_L0S_TO_RCVY_NUM) << BIT_SHIFT_L0S_TO_RCVY_NUM)
+#define BITS_L0S_TO_RCVY_NUM                                                   \
+	(BIT_MASK_L0S_TO_RCVY_NUM << BIT_SHIFT_L0S_TO_RCVY_NUM)
+#define BIT_CLEAR_L0S_TO_RCVY_NUM(x) ((x) & (~BITS_L0S_TO_RCVY_NUM))
+#define BIT_GET_L0S_TO_RCVY_NUM(x)                                             \
+	(((x) >> BIT_SHIFT_L0S_TO_RCVY_NUM) & BIT_MASK_L0S_TO_RCVY_NUM)
+#define BIT_SET_L0S_TO_RCVY_NUM(x, v)                                          \
+	(BIT_CLEAR_L0S_TO_RCVY_NUM(x) | BIT_L0S_TO_RCVY_NUM(v))
+
+#define BIT_CPWM2_TOGGLING BIT(15)
+
+#define BIT_SHIFT_CPWM2_MOD 0
+#define BIT_MASK_CPWM2_MOD 0x7fff
+#define BIT_CPWM2_MOD(x) (((x) & BIT_MASK_CPWM2_MOD) << BIT_SHIFT_CPWM2_MOD)
+#define BITS_CPWM2_MOD (BIT_MASK_CPWM2_MOD << BIT_SHIFT_CPWM2_MOD)
+#define BIT_CLEAR_CPWM2_MOD(x) ((x) & (~BITS_CPWM2_MOD))
+#define BIT_GET_CPWM2_MOD(x) (((x) >> BIT_SHIFT_CPWM2_MOD) & BIT_MASK_CPWM2_MOD)
+#define BIT_SET_CPWM2_MOD(x, v) (BIT_CLEAR_CPWM2_MOD(x) | BIT_CPWM2_MOD(v))
+
+/* 2 REG_TC0_CTRL				(Offset 0x0150) */
+
+#define BIT_TC0INT_EN BIT(26)
+#define BIT_TC0MODE BIT(25)
+#define BIT_TC0EN BIT(24)
+
+#define BIT_SHIFT_TC0DATA 0
+#define BIT_MASK_TC0DATA 0xffffff
+#define BIT_TC0DATA(x) (((x) & BIT_MASK_TC0DATA) << BIT_SHIFT_TC0DATA)
+#define BITS_TC0DATA (BIT_MASK_TC0DATA << BIT_SHIFT_TC0DATA)
+#define BIT_CLEAR_TC0DATA(x) ((x) & (~BITS_TC0DATA))
+#define BIT_GET_TC0DATA(x) (((x) >> BIT_SHIFT_TC0DATA) & BIT_MASK_TC0DATA)
+#define BIT_SET_TC0DATA(x, v) (BIT_CLEAR_TC0DATA(x) | BIT_TC0DATA(v))
+
+/* 2 REG_TC1_CTRL				(Offset 0x0154) */
+
+#define BIT_TC1INT_EN BIT(26)
+#define BIT_TC1MODE BIT(25)
+#define BIT_TC1EN BIT(24)
+
+#define BIT_SHIFT_TC1DATA 0
+#define BIT_MASK_TC1DATA 0xffffff
+#define BIT_TC1DATA(x) (((x) & BIT_MASK_TC1DATA) << BIT_SHIFT_TC1DATA)
+#define BITS_TC1DATA (BIT_MASK_TC1DATA << BIT_SHIFT_TC1DATA)
+#define BIT_CLEAR_TC1DATA(x) ((x) & (~BITS_TC1DATA))
+#define BIT_GET_TC1DATA(x) (((x) >> BIT_SHIFT_TC1DATA) & BIT_MASK_TC1DATA)
+#define BIT_SET_TC1DATA(x, v) (BIT_CLEAR_TC1DATA(x) | BIT_TC1DATA(v))
+
+/* 2 REG_TC2_CTRL				(Offset 0x0158) */
+
+#define BIT_TC2INT_EN BIT(26)
+#define BIT_TC2MODE BIT(25)
+#define BIT_TC2EN BIT(24)
+
+#define BIT_SHIFT_TC2DATA 0
+#define BIT_MASK_TC2DATA 0xffffff
+#define BIT_TC2DATA(x) (((x) & BIT_MASK_TC2DATA) << BIT_SHIFT_TC2DATA)
+#define BITS_TC2DATA (BIT_MASK_TC2DATA << BIT_SHIFT_TC2DATA)
+#define BIT_CLEAR_TC2DATA(x) ((x) & (~BITS_TC2DATA))
+#define BIT_GET_TC2DATA(x) (((x) >> BIT_SHIFT_TC2DATA) & BIT_MASK_TC2DATA)
+#define BIT_SET_TC2DATA(x, v) (BIT_CLEAR_TC2DATA(x) | BIT_TC2DATA(v))
+
+/* 2 REG_TC3_CTRL				(Offset 0x015C) */
+
+#define BIT_TC3INT_EN BIT(26)
+#define BIT_TC3MODE BIT(25)
+#define BIT_TC3EN BIT(24)
+
+#define BIT_SHIFT_TC3DATA 0
+#define BIT_MASK_TC3DATA 0xffffff
+#define BIT_TC3DATA(x) (((x) & BIT_MASK_TC3DATA) << BIT_SHIFT_TC3DATA)
+#define BITS_TC3DATA (BIT_MASK_TC3DATA << BIT_SHIFT_TC3DATA)
+#define BIT_CLEAR_TC3DATA(x) ((x) & (~BITS_TC3DATA))
+#define BIT_GET_TC3DATA(x) (((x) >> BIT_SHIFT_TC3DATA) & BIT_MASK_TC3DATA)
+#define BIT_SET_TC3DATA(x, v) (BIT_CLEAR_TC3DATA(x) | BIT_TC3DATA(v))
+
+/* 2 REG_TC4_CTRL				(Offset 0x0160) */
+
+#define BIT_TC4INT_EN BIT(26)
+#define BIT_TC4MODE BIT(25)
+#define BIT_TC4EN BIT(24)
+
+#define BIT_SHIFT_TC4DATA 0
+#define BIT_MASK_TC4DATA 0xffffff
+#define BIT_TC4DATA(x) (((x) & BIT_MASK_TC4DATA) << BIT_SHIFT_TC4DATA)
+#define BITS_TC4DATA (BIT_MASK_TC4DATA << BIT_SHIFT_TC4DATA)
+#define BIT_CLEAR_TC4DATA(x) ((x) & (~BITS_TC4DATA))
+#define BIT_GET_TC4DATA(x) (((x) >> BIT_SHIFT_TC4DATA) & BIT_MASK_TC4DATA)
+#define BIT_SET_TC4DATA(x, v) (BIT_CLEAR_TC4DATA(x) | BIT_TC4DATA(v))
+
+/* 2 REG_TCUNIT_BASE				(Offset 0x0164) */
+
+#define BIT_SHIFT_TCUNIT_BASE 0
+#define BIT_MASK_TCUNIT_BASE 0x3fff
+#define BIT_TCUNIT_BASE(x)                                                     \
+	(((x) & BIT_MASK_TCUNIT_BASE) << BIT_SHIFT_TCUNIT_BASE)
+#define BITS_TCUNIT_BASE (BIT_MASK_TCUNIT_BASE << BIT_SHIFT_TCUNIT_BASE)
+#define BIT_CLEAR_TCUNIT_BASE(x) ((x) & (~BITS_TCUNIT_BASE))
+#define BIT_GET_TCUNIT_BASE(x)                                                 \
+	(((x) >> BIT_SHIFT_TCUNIT_BASE) & BIT_MASK_TCUNIT_BASE)
+#define BIT_SET_TCUNIT_BASE(x, v)                                              \
+	(BIT_CLEAR_TCUNIT_BASE(x) | BIT_TCUNIT_BASE(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_TC5_CTRL				(Offset 0x0168) */
+
+#define BIT_TC50INT_EN BIT(26)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_TC5_CTRL				(Offset 0x0168) */
+
+#define BIT_TC5INT_EN BIT(26)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_TC5_CTRL				(Offset 0x0168) */
+
+#define BIT_TC5MODE BIT(25)
+#define BIT_TC5EN BIT(24)
+
+#define BIT_SHIFT_TC5DATA 0
+#define BIT_MASK_TC5DATA 0xffffff
+#define BIT_TC5DATA(x) (((x) & BIT_MASK_TC5DATA) << BIT_SHIFT_TC5DATA)
+#define BITS_TC5DATA (BIT_MASK_TC5DATA << BIT_SHIFT_TC5DATA)
+#define BIT_CLEAR_TC5DATA(x) ((x) & (~BITS_TC5DATA))
+#define BIT_GET_TC5DATA(x) (((x) >> BIT_SHIFT_TC5DATA) & BIT_MASK_TC5DATA)
+#define BIT_SET_TC5DATA(x, v) (BIT_CLEAR_TC5DATA(x) | BIT_TC5DATA(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_TC6_CTRL				(Offset 0x016C) */
+
+#define BIT_TC60INT_EN BIT(26)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_TC6_CTRL				(Offset 0x016C) */
+
+#define BIT_TC6INT_EN BIT(26)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_TC6_CTRL				(Offset 0x016C) */
+
+#define BIT_TC6MODE BIT(25)
+#define BIT_TC6EN BIT(24)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_TC6_CTRL				(Offset 0x016C) */
+
+#define BIT_SHIFT_SEQNUM_MID 16
+#define BIT_MASK_SEQNUM_MID 0xffff
+#define BIT_SEQNUM_MID(x) (((x) & BIT_MASK_SEQNUM_MID) << BIT_SHIFT_SEQNUM_MID)
+#define BITS_SEQNUM_MID (BIT_MASK_SEQNUM_MID << BIT_SHIFT_SEQNUM_MID)
+#define BIT_CLEAR_SEQNUM_MID(x) ((x) & (~BITS_SEQNUM_MID))
+#define BIT_GET_SEQNUM_MID(x)                                                  \
+	(((x) >> BIT_SHIFT_SEQNUM_MID) & BIT_MASK_SEQNUM_MID)
+#define BIT_SET_SEQNUM_MID(x, v) (BIT_CLEAR_SEQNUM_MID(x) | BIT_SEQNUM_MID(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_TC6_CTRL				(Offset 0x016C) */
+
+#define BIT_SHIFT_TC6DATA 0
+#define BIT_MASK_TC6DATA 0xffffff
+#define BIT_TC6DATA(x) (((x) & BIT_MASK_TC6DATA) << BIT_SHIFT_TC6DATA)
+#define BITS_TC6DATA (BIT_MASK_TC6DATA << BIT_SHIFT_TC6DATA)
+#define BIT_CLEAR_TC6DATA(x) ((x) & (~BITS_TC6DATA))
+#define BIT_GET_TC6DATA(x) (((x) >> BIT_SHIFT_TC6DATA) & BIT_MASK_TC6DATA)
+#define BIT_SET_TC6DATA(x, v) (BIT_CLEAR_TC6DATA(x) | BIT_TC6DATA(v))
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_MBIST_DRF_FAIL			(Offset 0x0170) */
+
+#define BIT_SHIFT_WLON_MBIST_DRF_FAIL 30
+#define BIT_MASK_WLON_MBIST_DRF_FAIL 0x3
+#define BIT_WLON_MBIST_DRF_FAIL(x)                                             \
+	(((x) & BIT_MASK_WLON_MBIST_DRF_FAIL) << BIT_SHIFT_WLON_MBIST_DRF_FAIL)
+#define BITS_WLON_MBIST_DRF_FAIL                                               \
+	(BIT_MASK_WLON_MBIST_DRF_FAIL << BIT_SHIFT_WLON_MBIST_DRF_FAIL)
+#define BIT_CLEAR_WLON_MBIST_DRF_FAIL(x) ((x) & (~BITS_WLON_MBIST_DRF_FAIL))
+#define BIT_GET_WLON_MBIST_DRF_FAIL(x)                                         \
+	(((x) >> BIT_SHIFT_WLON_MBIST_DRF_FAIL) & BIT_MASK_WLON_MBIST_DRF_FAIL)
+#define BIT_SET_WLON_MBIST_DRF_FAIL(x, v)                                      \
+	(BIT_CLEAR_WLON_MBIST_DRF_FAIL(x) | BIT_WLON_MBIST_DRF_FAIL(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT || \
+     HALMAC_8881A_SUPPORT)
+
+/* 2 REG_MBIST_FAIL				(Offset 0x0170) */
+
+#define BIT_SHIFT_8051_MBIST_FAIL 26
+#define BIT_MASK_8051_MBIST_FAIL 0x7
+#define BIT_8051_MBIST_FAIL(x)                                                 \
+	(((x) & BIT_MASK_8051_MBIST_FAIL) << BIT_SHIFT_8051_MBIST_FAIL)
+#define BITS_8051_MBIST_FAIL                                                   \
+	(BIT_MASK_8051_MBIST_FAIL << BIT_SHIFT_8051_MBIST_FAIL)
+#define BIT_CLEAR_8051_MBIST_FAIL(x) ((x) & (~BITS_8051_MBIST_FAIL))
+#define BIT_GET_8051_MBIST_FAIL(x)                                             \
+	(((x) >> BIT_SHIFT_8051_MBIST_FAIL) & BIT_MASK_8051_MBIST_FAIL)
+#define BIT_SET_8051_MBIST_FAIL(x, v)                                          \
+	(BIT_CLEAR_8051_MBIST_FAIL(x) | BIT_8051_MBIST_FAIL(v))
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_MBIST_DRF_FAIL			(Offset 0x0170) */
+
+#define BIT_SHIFT_8051_MBIST_DRF_FAIL 26
+#define BIT_MASK_8051_MBIST_DRF_FAIL 0x3f
+#define BIT_8051_MBIST_DRF_FAIL(x)                                             \
+	(((x) & BIT_MASK_8051_MBIST_DRF_FAIL) << BIT_SHIFT_8051_MBIST_DRF_FAIL)
+#define BITS_8051_MBIST_DRF_FAIL                                               \
+	(BIT_MASK_8051_MBIST_DRF_FAIL << BIT_SHIFT_8051_MBIST_DRF_FAIL)
+#define BIT_CLEAR_8051_MBIST_DRF_FAIL(x) ((x) & (~BITS_8051_MBIST_DRF_FAIL))
+#define BIT_GET_8051_MBIST_DRF_FAIL(x)                                         \
+	(((x) >> BIT_SHIFT_8051_MBIST_DRF_FAIL) & BIT_MASK_8051_MBIST_DRF_FAIL)
+#define BIT_SET_8051_MBIST_DRF_FAIL(x, v)                                      \
+	(BIT_CLEAR_8051_MBIST_DRF_FAIL(x) | BIT_8051_MBIST_DRF_FAIL(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT || \
+     HALMAC_8881A_SUPPORT)
+
+/* 2 REG_MBIST_FAIL				(Offset 0x0170) */
+
+#define BIT_SHIFT_USB_MBIST_FAIL 24
+#define BIT_MASK_USB_MBIST_FAIL 0x3
+#define BIT_USB_MBIST_FAIL(x)                                                  \
+	(((x) & BIT_MASK_USB_MBIST_FAIL) << BIT_SHIFT_USB_MBIST_FAIL)
+#define BITS_USB_MBIST_FAIL                                                    \
+	(BIT_MASK_USB_MBIST_FAIL << BIT_SHIFT_USB_MBIST_FAIL)
+#define BIT_CLEAR_USB_MBIST_FAIL(x) ((x) & (~BITS_USB_MBIST_FAIL))
+#define BIT_GET_USB_MBIST_FAIL(x)                                              \
+	(((x) >> BIT_SHIFT_USB_MBIST_FAIL) & BIT_MASK_USB_MBIST_FAIL)
+#define BIT_SET_USB_MBIST_FAIL(x, v)                                           \
+	(BIT_CLEAR_USB_MBIST_FAIL(x) | BIT_USB_MBIST_FAIL(v))
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_MBIST_DRF_FAIL			(Offset 0x0170) */
+
+#define BIT_SHIFT_USB_MBIST_DRF_FAIL 24
+#define BIT_MASK_USB_MBIST_DRF_FAIL 0x3
+#define BIT_USB_MBIST_DRF_FAIL(x)                                              \
+	(((x) & BIT_MASK_USB_MBIST_DRF_FAIL) << BIT_SHIFT_USB_MBIST_DRF_FAIL)
+#define BITS_USB_MBIST_DRF_FAIL                                                \
+	(BIT_MASK_USB_MBIST_DRF_FAIL << BIT_SHIFT_USB_MBIST_DRF_FAIL)
+#define BIT_CLEAR_USB_MBIST_DRF_FAIL(x) ((x) & (~BITS_USB_MBIST_DRF_FAIL))
+#define BIT_GET_USB_MBIST_DRF_FAIL(x)                                          \
+	(((x) >> BIT_SHIFT_USB_MBIST_DRF_FAIL) & BIT_MASK_USB_MBIST_DRF_FAIL)
+#define BIT_SET_USB_MBIST_DRF_FAIL(x, v)                                       \
+	(BIT_CLEAR_USB_MBIST_DRF_FAIL(x) | BIT_USB_MBIST_DRF_FAIL(v))
+
+#define BIT_SHIFT_PCIE_MBIST_DRF_FAIL 18
+#define BIT_MASK_PCIE_MBIST_DRF_FAIL 0x3f
+#define BIT_PCIE_MBIST_DRF_FAIL(x)                                             \
+	(((x) & BIT_MASK_PCIE_MBIST_DRF_FAIL) << BIT_SHIFT_PCIE_MBIST_DRF_FAIL)
+#define BITS_PCIE_MBIST_DRF_FAIL                                               \
+	(BIT_MASK_PCIE_MBIST_DRF_FAIL << BIT_SHIFT_PCIE_MBIST_DRF_FAIL)
+#define BIT_CLEAR_PCIE_MBIST_DRF_FAIL(x) ((x) & (~BITS_PCIE_MBIST_DRF_FAIL))
+#define BIT_GET_PCIE_MBIST_DRF_FAIL(x)                                         \
+	(((x) >> BIT_SHIFT_PCIE_MBIST_DRF_FAIL) & BIT_MASK_PCIE_MBIST_DRF_FAIL)
+#define BIT_SET_PCIE_MBIST_DRF_FAIL(x, v)                                      \
+	(BIT_CLEAR_PCIE_MBIST_DRF_FAIL(x) | BIT_PCIE_MBIST_DRF_FAIL(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT || \
+     HALMAC_8881A_SUPPORT)
+
+/* 2 REG_MBIST_FAIL				(Offset 0x0170) */
+
+#define BIT_SHIFT_PCIE_MBIST_FAIL 16
+#define BIT_MASK_PCIE_MBIST_FAIL 0x3f
+#define BIT_PCIE_MBIST_FAIL(x)                                                 \
+	(((x) & BIT_MASK_PCIE_MBIST_FAIL) << BIT_SHIFT_PCIE_MBIST_FAIL)
+#define BITS_PCIE_MBIST_FAIL                                                   \
+	(BIT_MASK_PCIE_MBIST_FAIL << BIT_SHIFT_PCIE_MBIST_FAIL)
+#define BIT_CLEAR_PCIE_MBIST_FAIL(x) ((x) & (~BITS_PCIE_MBIST_FAIL))
+#define BIT_GET_PCIE_MBIST_FAIL(x)                                             \
+	(((x) >> BIT_SHIFT_PCIE_MBIST_FAIL) & BIT_MASK_PCIE_MBIST_FAIL)
+#define BIT_SET_PCIE_MBIST_FAIL(x, v)                                          \
+	(BIT_CLEAR_PCIE_MBIST_FAIL(x) | BIT_PCIE_MBIST_FAIL(v))
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_MBIST_DRF_FAIL			(Offset 0x0170) */
+
+#define BIT_SHIFT_WLOFF_MBIST_DRF_FAIL 16
+#define BIT_MASK_WLOFF_MBIST_DRF_FAIL 0x3fff
+#define BIT_WLOFF_MBIST_DRF_FAIL(x)                                            \
+	(((x) & BIT_MASK_WLOFF_MBIST_DRF_FAIL)                                 \
+	 << BIT_SHIFT_WLOFF_MBIST_DRF_FAIL)
+#define BITS_WLOFF_MBIST_DRF_FAIL                                              \
+	(BIT_MASK_WLOFF_MBIST_DRF_FAIL << BIT_SHIFT_WLOFF_MBIST_DRF_FAIL)
+#define BIT_CLEAR_WLOFF_MBIST_DRF_FAIL(x) ((x) & (~BITS_WLOFF_MBIST_DRF_FAIL))
+#define BIT_GET_WLOFF_MBIST_DRF_FAIL(x)                                        \
+	(((x) >> BIT_SHIFT_WLOFF_MBIST_DRF_FAIL) &                             \
+	 BIT_MASK_WLOFF_MBIST_DRF_FAIL)
+#define BIT_SET_WLOFF_MBIST_DRF_FAIL(x, v)                                     \
+	(BIT_CLEAR_WLOFF_MBIST_DRF_FAIL(x) | BIT_WLOFF_MBIST_DRF_FAIL(v))
+
+#define BIT_SHIFT_PCIE_MBIST_DRF_FAIL_V1 11
+#define BIT_MASK_PCIE_MBIST_DRF_FAIL_V1 0x1f
+#define BIT_PCIE_MBIST_DRF_FAIL_V1(x)                                          \
+	(((x) & BIT_MASK_PCIE_MBIST_DRF_FAIL_V1)                               \
+	 << BIT_SHIFT_PCIE_MBIST_DRF_FAIL_V1)
+#define BITS_PCIE_MBIST_DRF_FAIL_V1                                            \
+	(BIT_MASK_PCIE_MBIST_DRF_FAIL_V1 << BIT_SHIFT_PCIE_MBIST_DRF_FAIL_V1)
+#define BIT_CLEAR_PCIE_MBIST_DRF_FAIL_V1(x)                                    \
+	((x) & (~BITS_PCIE_MBIST_DRF_FAIL_V1))
+#define BIT_GET_PCIE_MBIST_DRF_FAIL_V1(x)                                      \
+	(((x) >> BIT_SHIFT_PCIE_MBIST_DRF_FAIL_V1) &                           \
+	 BIT_MASK_PCIE_MBIST_DRF_FAIL_V1)
+#define BIT_SET_PCIE_MBIST_DRF_FAIL_V1(x, v)                                   \
+	(BIT_CLEAR_PCIE_MBIST_DRF_FAIL_V1(x) | BIT_PCIE_MBIST_DRF_FAIL_V1(v))
+
+#define BIT_SHIFT_USB_MBIST_DRF_FAIL_V1 4
+#define BIT_MASK_USB_MBIST_DRF_FAIL_V1 0x7f
+#define BIT_USB_MBIST_DRF_FAIL_V1(x)                                           \
+	(((x) & BIT_MASK_USB_MBIST_DRF_FAIL_V1)                                \
+	 << BIT_SHIFT_USB_MBIST_DRF_FAIL_V1)
+#define BITS_USB_MBIST_DRF_FAIL_V1                                             \
+	(BIT_MASK_USB_MBIST_DRF_FAIL_V1 << BIT_SHIFT_USB_MBIST_DRF_FAIL_V1)
+#define BIT_CLEAR_USB_MBIST_DRF_FAIL_V1(x) ((x) & (~BITS_USB_MBIST_DRF_FAIL_V1))
+#define BIT_GET_USB_MBIST_DRF_FAIL_V1(x)                                       \
+	(((x) >> BIT_SHIFT_USB_MBIST_DRF_FAIL_V1) &                            \
+	 BIT_MASK_USB_MBIST_DRF_FAIL_V1)
+#define BIT_SET_USB_MBIST_DRF_FAIL_V1(x, v)                                    \
+	(BIT_CLEAR_USB_MBIST_DRF_FAIL_V1(x) | BIT_USB_MBIST_DRF_FAIL_V1(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_MBIST_FAIL				(Offset 0x0170) */
+
+#define BIT_SHIFT_MAC_MBIST_FAIL 0
+#define BIT_MASK_MAC_MBIST_FAIL 0xfff
+#define BIT_MAC_MBIST_FAIL(x)                                                  \
+	(((x) & BIT_MASK_MAC_MBIST_FAIL) << BIT_SHIFT_MAC_MBIST_FAIL)
+#define BITS_MAC_MBIST_FAIL                                                    \
+	(BIT_MASK_MAC_MBIST_FAIL << BIT_SHIFT_MAC_MBIST_FAIL)
+#define BIT_CLEAR_MAC_MBIST_FAIL(x) ((x) & (~BITS_MAC_MBIST_FAIL))
+#define BIT_GET_MAC_MBIST_FAIL(x)                                              \
+	(((x) >> BIT_SHIFT_MAC_MBIST_FAIL) & BIT_MASK_MAC_MBIST_FAIL)
+#define BIT_SET_MAC_MBIST_FAIL(x, v)                                           \
+	(BIT_CLEAR_MAC_MBIST_FAIL(x) | BIT_MAC_MBIST_FAIL(v))
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_MBIST_DRF_FAIL			(Offset 0x0170) */
+
+#define BIT_SHIFT_USB_WLON_MBIST_DRF_FAIL 0
+#define BIT_MASK_USB_WLON_MBIST_DRF_FAIL 0xf
+#define BIT_USB_WLON_MBIST_DRF_FAIL(x)                                         \
+	(((x) & BIT_MASK_USB_WLON_MBIST_DRF_FAIL)                              \
+	 << BIT_SHIFT_USB_WLON_MBIST_DRF_FAIL)
+#define BITS_USB_WLON_MBIST_DRF_FAIL                                           \
+	(BIT_MASK_USB_WLON_MBIST_DRF_FAIL << BIT_SHIFT_USB_WLON_MBIST_DRF_FAIL)
+#define BIT_CLEAR_USB_WLON_MBIST_DRF_FAIL(x)                                   \
+	((x) & (~BITS_USB_WLON_MBIST_DRF_FAIL))
+#define BIT_GET_USB_WLON_MBIST_DRF_FAIL(x)                                     \
+	(((x) >> BIT_SHIFT_USB_WLON_MBIST_DRF_FAIL) &                          \
+	 BIT_MASK_USB_WLON_MBIST_DRF_FAIL)
+#define BIT_SET_USB_WLON_MBIST_DRF_FAIL(x, v)                                  \
+	(BIT_CLEAR_USB_WLON_MBIST_DRF_FAIL(x) | BIT_USB_WLON_MBIST_DRF_FAIL(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_MBIST_FAIL				(Offset 0x0170) */
+
+#define BIT_SHIFT_MAC_MBIST_FAIL_DRF 0
+#define BIT_MASK_MAC_MBIST_FAIL_DRF 0x3ffff
+#define BIT_MAC_MBIST_FAIL_DRF(x)                                              \
+	(((x) & BIT_MASK_MAC_MBIST_FAIL_DRF) << BIT_SHIFT_MAC_MBIST_FAIL_DRF)
+#define BITS_MAC_MBIST_FAIL_DRF                                                \
+	(BIT_MASK_MAC_MBIST_FAIL_DRF << BIT_SHIFT_MAC_MBIST_FAIL_DRF)
+#define BIT_CLEAR_MAC_MBIST_FAIL_DRF(x) ((x) & (~BITS_MAC_MBIST_FAIL_DRF))
+#define BIT_GET_MAC_MBIST_FAIL_DRF(x)                                          \
+	(((x) >> BIT_SHIFT_MAC_MBIST_FAIL_DRF) & BIT_MASK_MAC_MBIST_FAIL_DRF)
+#define BIT_SET_MAC_MBIST_FAIL_DRF(x, v)                                       \
+	(BIT_CLEAR_MAC_MBIST_FAIL_DRF(x) | BIT_MAC_MBIST_FAIL_DRF(v))
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_MBIST_DRF_FAIL			(Offset 0x0170) */
+
+#define BIT_SHIFT_MAC_MBIST_DRF_FAIL 0
+#define BIT_MASK_MAC_MBIST_DRF_FAIL 0x3ffff
+#define BIT_MAC_MBIST_DRF_FAIL(x)                                              \
+	(((x) & BIT_MASK_MAC_MBIST_DRF_FAIL) << BIT_SHIFT_MAC_MBIST_DRF_FAIL)
+#define BITS_MAC_MBIST_DRF_FAIL                                                \
+	(BIT_MASK_MAC_MBIST_DRF_FAIL << BIT_SHIFT_MAC_MBIST_DRF_FAIL)
+#define BIT_CLEAR_MAC_MBIST_DRF_FAIL(x) ((x) & (~BITS_MAC_MBIST_DRF_FAIL))
+#define BIT_GET_MAC_MBIST_DRF_FAIL(x)                                          \
+	(((x) >> BIT_SHIFT_MAC_MBIST_DRF_FAIL) & BIT_MASK_MAC_MBIST_DRF_FAIL)
+#define BIT_SET_MAC_MBIST_DRF_FAIL(x, v)                                       \
+	(BIT_CLEAR_MAC_MBIST_DRF_FAIL(x) | BIT_MAC_MBIST_DRF_FAIL(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT || \
+     HALMAC_8881A_SUPPORT)
+
+/* 2 REG_MBIST_START_PAUSE			(Offset 0x0174) */
+
+#define BIT_SHIFT_8051_MBIST_START_PAUSE 26
+#define BIT_MASK_8051_MBIST_START_PAUSE 0x7
+#define BIT_8051_MBIST_START_PAUSE(x)                                          \
+	(((x) & BIT_MASK_8051_MBIST_START_PAUSE)                               \
+	 << BIT_SHIFT_8051_MBIST_START_PAUSE)
+#define BITS_8051_MBIST_START_PAUSE                                            \
+	(BIT_MASK_8051_MBIST_START_PAUSE << BIT_SHIFT_8051_MBIST_START_PAUSE)
+#define BIT_CLEAR_8051_MBIST_START_PAUSE(x)                                    \
+	((x) & (~BITS_8051_MBIST_START_PAUSE))
+#define BIT_GET_8051_MBIST_START_PAUSE(x)                                      \
+	(((x) >> BIT_SHIFT_8051_MBIST_START_PAUSE) &                           \
+	 BIT_MASK_8051_MBIST_START_PAUSE)
+#define BIT_SET_8051_MBIST_START_PAUSE(x, v)                                   \
+	(BIT_CLEAR_8051_MBIST_START_PAUSE(x) | BIT_8051_MBIST_START_PAUSE(v))
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_MBIST_START_PAUSE			(Offset 0x0174) */
+
+#define BIT_SHIFT_8051_MBIST_START_PAUSE_V1 26
+#define BIT_MASK_8051_MBIST_START_PAUSE_V1 0x3f
+#define BIT_8051_MBIST_START_PAUSE_V1(x)                                       \
+	(((x) & BIT_MASK_8051_MBIST_START_PAUSE_V1)                            \
+	 << BIT_SHIFT_8051_MBIST_START_PAUSE_V1)
+#define BITS_8051_MBIST_START_PAUSE_V1                                         \
+	(BIT_MASK_8051_MBIST_START_PAUSE_V1                                    \
+	 << BIT_SHIFT_8051_MBIST_START_PAUSE_V1)
+#define BIT_CLEAR_8051_MBIST_START_PAUSE_V1(x)                                 \
+	((x) & (~BITS_8051_MBIST_START_PAUSE_V1))
+#define BIT_GET_8051_MBIST_START_PAUSE_V1(x)                                   \
+	(((x) >> BIT_SHIFT_8051_MBIST_START_PAUSE_V1) &                        \
+	 BIT_MASK_8051_MBIST_START_PAUSE_V1)
+#define BIT_SET_8051_MBIST_START_PAUSE_V1(x, v)                                \
+	(BIT_CLEAR_8051_MBIST_START_PAUSE_V1(x) |                              \
+	 BIT_8051_MBIST_START_PAUSE_V1(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT || \
+     HALMAC_8881A_SUPPORT)
+
+/* 2 REG_MBIST_START_PAUSE			(Offset 0x0174) */
+
+#define BIT_SHIFT_USB_MBIST_START_PAUSE 24
+#define BIT_MASK_USB_MBIST_START_PAUSE 0x3
+#define BIT_USB_MBIST_START_PAUSE(x)                                           \
+	(((x) & BIT_MASK_USB_MBIST_START_PAUSE)                                \
+	 << BIT_SHIFT_USB_MBIST_START_PAUSE)
+#define BITS_USB_MBIST_START_PAUSE                                             \
+	(BIT_MASK_USB_MBIST_START_PAUSE << BIT_SHIFT_USB_MBIST_START_PAUSE)
+#define BIT_CLEAR_USB_MBIST_START_PAUSE(x) ((x) & (~BITS_USB_MBIST_START_PAUSE))
+#define BIT_GET_USB_MBIST_START_PAUSE(x)                                       \
+	(((x) >> BIT_SHIFT_USB_MBIST_START_PAUSE) &                            \
+	 BIT_MASK_USB_MBIST_START_PAUSE)
+#define BIT_SET_USB_MBIST_START_PAUSE(x, v)                                    \
+	(BIT_CLEAR_USB_MBIST_START_PAUSE(x) | BIT_USB_MBIST_START_PAUSE(v))
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_MBIST_START_PAUSE			(Offset 0x0174) */
+
+#define BIT_SHIFT_USB_MBIST_START_PAUSE_V1 24
+#define BIT_MASK_USB_MBIST_START_PAUSE_V1 0x3
+#define BIT_USB_MBIST_START_PAUSE_V1(x)                                        \
+	(((x) & BIT_MASK_USB_MBIST_START_PAUSE_V1)                             \
+	 << BIT_SHIFT_USB_MBIST_START_PAUSE_V1)
+#define BITS_USB_MBIST_START_PAUSE_V1                                          \
+	(BIT_MASK_USB_MBIST_START_PAUSE_V1                                     \
+	 << BIT_SHIFT_USB_MBIST_START_PAUSE_V1)
+#define BIT_CLEAR_USB_MBIST_START_PAUSE_V1(x)                                  \
+	((x) & (~BITS_USB_MBIST_START_PAUSE_V1))
+#define BIT_GET_USB_MBIST_START_PAUSE_V1(x)                                    \
+	(((x) >> BIT_SHIFT_USB_MBIST_START_PAUSE_V1) &                         \
+	 BIT_MASK_USB_MBIST_START_PAUSE_V1)
+#define BIT_SET_USB_MBIST_START_PAUSE_V1(x, v)                                 \
+	(BIT_CLEAR_USB_MBIST_START_PAUSE_V1(x) |                               \
+	 BIT_USB_MBIST_START_PAUSE_V1(v))
+
+#define BIT_SHIFT_PCIE_MBIST_START_PAUSE_V1 18
+#define BIT_MASK_PCIE_MBIST_START_PAUSE_V1 0x3f
+#define BIT_PCIE_MBIST_START_PAUSE_V1(x)                                       \
+	(((x) & BIT_MASK_PCIE_MBIST_START_PAUSE_V1)                            \
+	 << BIT_SHIFT_PCIE_MBIST_START_PAUSE_V1)
+#define BITS_PCIE_MBIST_START_PAUSE_V1                                         \
+	(BIT_MASK_PCIE_MBIST_START_PAUSE_V1                                    \
+	 << BIT_SHIFT_PCIE_MBIST_START_PAUSE_V1)
+#define BIT_CLEAR_PCIE_MBIST_START_PAUSE_V1(x)                                 \
+	((x) & (~BITS_PCIE_MBIST_START_PAUSE_V1))
+#define BIT_GET_PCIE_MBIST_START_PAUSE_V1(x)                                   \
+	(((x) >> BIT_SHIFT_PCIE_MBIST_START_PAUSE_V1) &                        \
+	 BIT_MASK_PCIE_MBIST_START_PAUSE_V1)
+#define BIT_SET_PCIE_MBIST_START_PAUSE_V1(x, v)                                \
+	(BIT_CLEAR_PCIE_MBIST_START_PAUSE_V1(x) |                              \
+	 BIT_PCIE_MBIST_START_PAUSE_V1(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT || \
+     HALMAC_8881A_SUPPORT)
+
+/* 2 REG_MBIST_START_PAUSE			(Offset 0x0174) */
+
+#define BIT_SHIFT_PCIE_MBIST_START_PAUSE 16
+#define BIT_MASK_PCIE_MBIST_START_PAUSE 0x3f
+#define BIT_PCIE_MBIST_START_PAUSE(x)                                          \
+	(((x) & BIT_MASK_PCIE_MBIST_START_PAUSE)                               \
+	 << BIT_SHIFT_PCIE_MBIST_START_PAUSE)
+#define BITS_PCIE_MBIST_START_PAUSE                                            \
+	(BIT_MASK_PCIE_MBIST_START_PAUSE << BIT_SHIFT_PCIE_MBIST_START_PAUSE)
+#define BIT_CLEAR_PCIE_MBIST_START_PAUSE(x)                                    \
+	((x) & (~BITS_PCIE_MBIST_START_PAUSE))
+#define BIT_GET_PCIE_MBIST_START_PAUSE(x)                                      \
+	(((x) >> BIT_SHIFT_PCIE_MBIST_START_PAUSE) &                           \
+	 BIT_MASK_PCIE_MBIST_START_PAUSE)
+#define BIT_SET_PCIE_MBIST_START_PAUSE(x, v)                                   \
+	(BIT_CLEAR_PCIE_MBIST_START_PAUSE(x) | BIT_PCIE_MBIST_START_PAUSE(v))
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_MBIST_START_PAUSE			(Offset 0x0174) */
+
+#define BIT_SHIFT_WLON_MBIST_START_PAUSE_V1 9
+#define BIT_MASK_WLON_MBIST_START_PAUSE_V1 0x3
+#define BIT_WLON_MBIST_START_PAUSE_V1(x)                                       \
+	(((x) & BIT_MASK_WLON_MBIST_START_PAUSE_V1)                            \
+	 << BIT_SHIFT_WLON_MBIST_START_PAUSE_V1)
+#define BITS_WLON_MBIST_START_PAUSE_V1                                         \
+	(BIT_MASK_WLON_MBIST_START_PAUSE_V1                                    \
+	 << BIT_SHIFT_WLON_MBIST_START_PAUSE_V1)
+#define BIT_CLEAR_WLON_MBIST_START_PAUSE_V1(x)                                 \
+	((x) & (~BITS_WLON_MBIST_START_PAUSE_V1))
+#define BIT_GET_WLON_MBIST_START_PAUSE_V1(x)                                   \
+	(((x) >> BIT_SHIFT_WLON_MBIST_START_PAUSE_V1) &                        \
+	 BIT_MASK_WLON_MBIST_START_PAUSE_V1)
+#define BIT_SET_WLON_MBIST_START_PAUSE_V1(x, v)                                \
+	(BIT_CLEAR_WLON_MBIST_START_PAUSE_V1(x) |                              \
+	 BIT_WLON_MBIST_START_PAUSE_V1(v))
+
+#define BIT_SHIFT_WLOFF_MBIST_START_PAUSE_V1 4
+#define BIT_MASK_WLOFF_MBIST_START_PAUSE_V1 0x1f
+#define BIT_WLOFF_MBIST_START_PAUSE_V1(x)                                      \
+	(((x) & BIT_MASK_WLOFF_MBIST_START_PAUSE_V1)                           \
+	 << BIT_SHIFT_WLOFF_MBIST_START_PAUSE_V1)
+#define BITS_WLOFF_MBIST_START_PAUSE_V1                                        \
+	(BIT_MASK_WLOFF_MBIST_START_PAUSE_V1                                   \
+	 << BIT_SHIFT_WLOFF_MBIST_START_PAUSE_V1)
+#define BIT_CLEAR_WLOFF_MBIST_START_PAUSE_V1(x)                                \
+	((x) & (~BITS_WLOFF_MBIST_START_PAUSE_V1))
+#define BIT_GET_WLOFF_MBIST_START_PAUSE_V1(x)                                  \
+	(((x) >> BIT_SHIFT_WLOFF_MBIST_START_PAUSE_V1) &                       \
+	 BIT_MASK_WLOFF_MBIST_START_PAUSE_V1)
+#define BIT_SET_WLOFF_MBIST_START_PAUSE_V1(x, v)                               \
+	(BIT_CLEAR_WLOFF_MBIST_START_PAUSE_V1(x) |                             \
+	 BIT_WLOFF_MBIST_START_PAUSE_V1(v))
+
+#define BIT_SHIFT_PCIE_MBIST_START_PAUSE_V2 2
+#define BIT_MASK_PCIE_MBIST_START_PAUSE_V2 0x3
+#define BIT_PCIE_MBIST_START_PAUSE_V2(x)                                       \
+	(((x) & BIT_MASK_PCIE_MBIST_START_PAUSE_V2)                            \
+	 << BIT_SHIFT_PCIE_MBIST_START_PAUSE_V2)
+#define BITS_PCIE_MBIST_START_PAUSE_V2                                         \
+	(BIT_MASK_PCIE_MBIST_START_PAUSE_V2                                    \
+	 << BIT_SHIFT_PCIE_MBIST_START_PAUSE_V2)
+#define BIT_CLEAR_PCIE_MBIST_START_PAUSE_V2(x)                                 \
+	((x) & (~BITS_PCIE_MBIST_START_PAUSE_V2))
+#define BIT_GET_PCIE_MBIST_START_PAUSE_V2(x)                                   \
+	(((x) >> BIT_SHIFT_PCIE_MBIST_START_PAUSE_V2) &                        \
+	 BIT_MASK_PCIE_MBIST_START_PAUSE_V2)
+#define BIT_SET_PCIE_MBIST_START_PAUSE_V2(x, v)                                \
+	(BIT_CLEAR_PCIE_MBIST_START_PAUSE_V2(x) |                              \
+	 BIT_PCIE_MBIST_START_PAUSE_V2(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_MBIST_START_PAUSE			(Offset 0x0174) */
+
+#define BIT_SHIFT_MAC_MBIST_START_PAUSE 0
+#define BIT_MASK_MAC_MBIST_START_PAUSE 0xfff
+#define BIT_MAC_MBIST_START_PAUSE(x)                                           \
+	(((x) & BIT_MASK_MAC_MBIST_START_PAUSE)                                \
+	 << BIT_SHIFT_MAC_MBIST_START_PAUSE)
+#define BITS_MAC_MBIST_START_PAUSE                                             \
+	(BIT_MASK_MAC_MBIST_START_PAUSE << BIT_SHIFT_MAC_MBIST_START_PAUSE)
+#define BIT_CLEAR_MAC_MBIST_START_PAUSE(x) ((x) & (~BITS_MAC_MBIST_START_PAUSE))
+#define BIT_GET_MAC_MBIST_START_PAUSE(x)                                       \
+	(((x) >> BIT_SHIFT_MAC_MBIST_START_PAUSE) &                            \
+	 BIT_MASK_MAC_MBIST_START_PAUSE)
+#define BIT_SET_MAC_MBIST_START_PAUSE(x, v)                                    \
+	(BIT_CLEAR_MAC_MBIST_START_PAUSE(x) | BIT_MAC_MBIST_START_PAUSE(v))
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_MBIST_START_PAUSE			(Offset 0x0174) */
+
+#define BIT_SHIFT_USB_MBIST_START_PAUSE_V2 0
+#define BIT_MASK_USB_MBIST_START_PAUSE_V2 0x3
+#define BIT_USB_MBIST_START_PAUSE_V2(x)                                        \
+	(((x) & BIT_MASK_USB_MBIST_START_PAUSE_V2)                             \
+	 << BIT_SHIFT_USB_MBIST_START_PAUSE_V2)
+#define BITS_USB_MBIST_START_PAUSE_V2                                          \
+	(BIT_MASK_USB_MBIST_START_PAUSE_V2                                     \
+	 << BIT_SHIFT_USB_MBIST_START_PAUSE_V2)
+#define BIT_CLEAR_USB_MBIST_START_PAUSE_V2(x)                                  \
+	((x) & (~BITS_USB_MBIST_START_PAUSE_V2))
+#define BIT_GET_USB_MBIST_START_PAUSE_V2(x)                                    \
+	(((x) >> BIT_SHIFT_USB_MBIST_START_PAUSE_V2) &                         \
+	 BIT_MASK_USB_MBIST_START_PAUSE_V2)
+#define BIT_SET_USB_MBIST_START_PAUSE_V2(x, v)                                 \
+	(BIT_CLEAR_USB_MBIST_START_PAUSE_V2(x) |                               \
+	 BIT_USB_MBIST_START_PAUSE_V2(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_MBIST_START_PAUSE			(Offset 0x0174) */
+
+#define BIT_SHIFT_MAC_MBIST_START_PAUSE_V1 0
+#define BIT_MASK_MAC_MBIST_START_PAUSE_V1 0x3ffff
+#define BIT_MAC_MBIST_START_PAUSE_V1(x)                                        \
+	(((x) & BIT_MASK_MAC_MBIST_START_PAUSE_V1)                             \
+	 << BIT_SHIFT_MAC_MBIST_START_PAUSE_V1)
+#define BITS_MAC_MBIST_START_PAUSE_V1                                          \
+	(BIT_MASK_MAC_MBIST_START_PAUSE_V1                                     \
+	 << BIT_SHIFT_MAC_MBIST_START_PAUSE_V1)
+#define BIT_CLEAR_MAC_MBIST_START_PAUSE_V1(x)                                  \
+	((x) & (~BITS_MAC_MBIST_START_PAUSE_V1))
+#define BIT_GET_MAC_MBIST_START_PAUSE_V1(x)                                    \
+	(((x) >> BIT_SHIFT_MAC_MBIST_START_PAUSE_V1) &                         \
+	 BIT_MASK_MAC_MBIST_START_PAUSE_V1)
+#define BIT_SET_MAC_MBIST_START_PAUSE_V1(x, v)                                 \
+	(BIT_CLEAR_MAC_MBIST_START_PAUSE_V1(x) |                               \
+	 BIT_MAC_MBIST_START_PAUSE_V1(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT || \
+     HALMAC_8881A_SUPPORT)
+
+/* 2 REG_MBIST_DONE				(Offset 0x0178) */
+
+#define BIT_SHIFT_8051_MBIST_DONE 26
+#define BIT_MASK_8051_MBIST_DONE 0x7
+#define BIT_8051_MBIST_DONE(x)                                                 \
+	(((x) & BIT_MASK_8051_MBIST_DONE) << BIT_SHIFT_8051_MBIST_DONE)
+#define BITS_8051_MBIST_DONE                                                   \
+	(BIT_MASK_8051_MBIST_DONE << BIT_SHIFT_8051_MBIST_DONE)
+#define BIT_CLEAR_8051_MBIST_DONE(x) ((x) & (~BITS_8051_MBIST_DONE))
+#define BIT_GET_8051_MBIST_DONE(x)                                             \
+	(((x) >> BIT_SHIFT_8051_MBIST_DONE) & BIT_MASK_8051_MBIST_DONE)
+#define BIT_SET_8051_MBIST_DONE(x, v)                                          \
+	(BIT_CLEAR_8051_MBIST_DONE(x) | BIT_8051_MBIST_DONE(v))
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_MBIST_DONE				(Offset 0x0178) */
+
+#define BIT_SHIFT_8051_MBIST_DONE_V1 26
+#define BIT_MASK_8051_MBIST_DONE_V1 0x3f
+#define BIT_8051_MBIST_DONE_V1(x)                                              \
+	(((x) & BIT_MASK_8051_MBIST_DONE_V1) << BIT_SHIFT_8051_MBIST_DONE_V1)
+#define BITS_8051_MBIST_DONE_V1                                                \
+	(BIT_MASK_8051_MBIST_DONE_V1 << BIT_SHIFT_8051_MBIST_DONE_V1)
+#define BIT_CLEAR_8051_MBIST_DONE_V1(x) ((x) & (~BITS_8051_MBIST_DONE_V1))
+#define BIT_GET_8051_MBIST_DONE_V1(x)                                          \
+	(((x) >> BIT_SHIFT_8051_MBIST_DONE_V1) & BIT_MASK_8051_MBIST_DONE_V1)
+#define BIT_SET_8051_MBIST_DONE_V1(x, v)                                       \
+	(BIT_CLEAR_8051_MBIST_DONE_V1(x) | BIT_8051_MBIST_DONE_V1(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT || \
+     HALMAC_8881A_SUPPORT)
+
+/* 2 REG_MBIST_DONE				(Offset 0x0178) */
+
+#define BIT_SHIFT_USB_MBIST_DONE 24
+#define BIT_MASK_USB_MBIST_DONE 0x3
+#define BIT_USB_MBIST_DONE(x)                                                  \
+	(((x) & BIT_MASK_USB_MBIST_DONE) << BIT_SHIFT_USB_MBIST_DONE)
+#define BITS_USB_MBIST_DONE                                                    \
+	(BIT_MASK_USB_MBIST_DONE << BIT_SHIFT_USB_MBIST_DONE)
+#define BIT_CLEAR_USB_MBIST_DONE(x) ((x) & (~BITS_USB_MBIST_DONE))
+#define BIT_GET_USB_MBIST_DONE(x)                                              \
+	(((x) >> BIT_SHIFT_USB_MBIST_DONE) & BIT_MASK_USB_MBIST_DONE)
+#define BIT_SET_USB_MBIST_DONE(x, v)                                           \
+	(BIT_CLEAR_USB_MBIST_DONE(x) | BIT_USB_MBIST_DONE(v))
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_MBIST_DONE				(Offset 0x0178) */
+
+#define BIT_SHIFT_USB_MBIST_DONE_V1 24
+#define BIT_MASK_USB_MBIST_DONE_V1 0x3
+#define BIT_USB_MBIST_DONE_V1(x)                                               \
+	(((x) & BIT_MASK_USB_MBIST_DONE_V1) << BIT_SHIFT_USB_MBIST_DONE_V1)
+#define BITS_USB_MBIST_DONE_V1                                                 \
+	(BIT_MASK_USB_MBIST_DONE_V1 << BIT_SHIFT_USB_MBIST_DONE_V1)
+#define BIT_CLEAR_USB_MBIST_DONE_V1(x) ((x) & (~BITS_USB_MBIST_DONE_V1))
+#define BIT_GET_USB_MBIST_DONE_V1(x)                                           \
+	(((x) >> BIT_SHIFT_USB_MBIST_DONE_V1) & BIT_MASK_USB_MBIST_DONE_V1)
+#define BIT_SET_USB_MBIST_DONE_V1(x, v)                                        \
+	(BIT_CLEAR_USB_MBIST_DONE_V1(x) | BIT_USB_MBIST_DONE_V1(v))
+
+#define BIT_SHIFT_PCIE_MBIST_DONE_V1 18
+#define BIT_MASK_PCIE_MBIST_DONE_V1 0x3f
+#define BIT_PCIE_MBIST_DONE_V1(x)                                              \
+	(((x) & BIT_MASK_PCIE_MBIST_DONE_V1) << BIT_SHIFT_PCIE_MBIST_DONE_V1)
+#define BITS_PCIE_MBIST_DONE_V1                                                \
+	(BIT_MASK_PCIE_MBIST_DONE_V1 << BIT_SHIFT_PCIE_MBIST_DONE_V1)
+#define BIT_CLEAR_PCIE_MBIST_DONE_V1(x) ((x) & (~BITS_PCIE_MBIST_DONE_V1))
+#define BIT_GET_PCIE_MBIST_DONE_V1(x)                                          \
+	(((x) >> BIT_SHIFT_PCIE_MBIST_DONE_V1) & BIT_MASK_PCIE_MBIST_DONE_V1)
+#define BIT_SET_PCIE_MBIST_DONE_V1(x, v)                                       \
+	(BIT_CLEAR_PCIE_MBIST_DONE_V1(x) | BIT_PCIE_MBIST_DONE_V1(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT || \
+     HALMAC_8881A_SUPPORT)
+
+/* 2 REG_MBIST_DONE				(Offset 0x0178) */
+
+#define BIT_SHIFT_PCIE_MBIST_DONE 16
+#define BIT_MASK_PCIE_MBIST_DONE 0x3f
+#define BIT_PCIE_MBIST_DONE(x)                                                 \
+	(((x) & BIT_MASK_PCIE_MBIST_DONE) << BIT_SHIFT_PCIE_MBIST_DONE)
+#define BITS_PCIE_MBIST_DONE                                                   \
+	(BIT_MASK_PCIE_MBIST_DONE << BIT_SHIFT_PCIE_MBIST_DONE)
+#define BIT_CLEAR_PCIE_MBIST_DONE(x) ((x) & (~BITS_PCIE_MBIST_DONE))
+#define BIT_GET_PCIE_MBIST_DONE(x)                                             \
+	(((x) >> BIT_SHIFT_PCIE_MBIST_DONE) & BIT_MASK_PCIE_MBIST_DONE)
+#define BIT_SET_PCIE_MBIST_DONE(x, v)                                          \
+	(BIT_CLEAR_PCIE_MBIST_DONE(x) | BIT_PCIE_MBIST_DONE(v))
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_MBIST_DONE				(Offset 0x0178) */
+
+#define BIT_SHIFT_WLON_MBIST_DONE_V1 9
+#define BIT_MASK_WLON_MBIST_DONE_V1 0x3
+#define BIT_WLON_MBIST_DONE_V1(x)                                              \
+	(((x) & BIT_MASK_WLON_MBIST_DONE_V1) << BIT_SHIFT_WLON_MBIST_DONE_V1)
+#define BITS_WLON_MBIST_DONE_V1                                                \
+	(BIT_MASK_WLON_MBIST_DONE_V1 << BIT_SHIFT_WLON_MBIST_DONE_V1)
+#define BIT_CLEAR_WLON_MBIST_DONE_V1(x) ((x) & (~BITS_WLON_MBIST_DONE_V1))
+#define BIT_GET_WLON_MBIST_DONE_V1(x)                                          \
+	(((x) >> BIT_SHIFT_WLON_MBIST_DONE_V1) & BIT_MASK_WLON_MBIST_DONE_V1)
+#define BIT_SET_WLON_MBIST_DONE_V1(x, v)                                       \
+	(BIT_CLEAR_WLON_MBIST_DONE_V1(x) | BIT_WLON_MBIST_DONE_V1(v))
+
+#define BIT_SHIFT_WLOFF_MBIST_DONE_V1 4
+#define BIT_MASK_WLOFF_MBIST_DONE_V1 0x1f
+#define BIT_WLOFF_MBIST_DONE_V1(x)                                             \
+	(((x) & BIT_MASK_WLOFF_MBIST_DONE_V1) << BIT_SHIFT_WLOFF_MBIST_DONE_V1)
+#define BITS_WLOFF_MBIST_DONE_V1                                               \
+	(BIT_MASK_WLOFF_MBIST_DONE_V1 << BIT_SHIFT_WLOFF_MBIST_DONE_V1)
+#define BIT_CLEAR_WLOFF_MBIST_DONE_V1(x) ((x) & (~BITS_WLOFF_MBIST_DONE_V1))
+#define BIT_GET_WLOFF_MBIST_DONE_V1(x)                                         \
+	(((x) >> BIT_SHIFT_WLOFF_MBIST_DONE_V1) & BIT_MASK_WLOFF_MBIST_DONE_V1)
+#define BIT_SET_WLOFF_MBIST_DONE_V1(x, v)                                      \
+	(BIT_CLEAR_WLOFF_MBIST_DONE_V1(x) | BIT_WLOFF_MBIST_DONE_V1(v))
+
+#define BIT_SHIFT_PCIE_MBIST_DONE_V2 2
+#define BIT_MASK_PCIE_MBIST_DONE_V2 0x3
+#define BIT_PCIE_MBIST_DONE_V2(x)                                              \
+	(((x) & BIT_MASK_PCIE_MBIST_DONE_V2) << BIT_SHIFT_PCIE_MBIST_DONE_V2)
+#define BITS_PCIE_MBIST_DONE_V2                                                \
+	(BIT_MASK_PCIE_MBIST_DONE_V2 << BIT_SHIFT_PCIE_MBIST_DONE_V2)
+#define BIT_CLEAR_PCIE_MBIST_DONE_V2(x) ((x) & (~BITS_PCIE_MBIST_DONE_V2))
+#define BIT_GET_PCIE_MBIST_DONE_V2(x)                                          \
+	(((x) >> BIT_SHIFT_PCIE_MBIST_DONE_V2) & BIT_MASK_PCIE_MBIST_DONE_V2)
+#define BIT_SET_PCIE_MBIST_DONE_V2(x, v)                                       \
+	(BIT_CLEAR_PCIE_MBIST_DONE_V2(x) | BIT_PCIE_MBIST_DONE_V2(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_MBIST_DONE				(Offset 0x0178) */
+
+#define BIT_SHIFT_MAC_MBIST_DONE 0
+#define BIT_MASK_MAC_MBIST_DONE 0xfff
+#define BIT_MAC_MBIST_DONE(x)                                                  \
+	(((x) & BIT_MASK_MAC_MBIST_DONE) << BIT_SHIFT_MAC_MBIST_DONE)
+#define BITS_MAC_MBIST_DONE                                                    \
+	(BIT_MASK_MAC_MBIST_DONE << BIT_SHIFT_MAC_MBIST_DONE)
+#define BIT_CLEAR_MAC_MBIST_DONE(x) ((x) & (~BITS_MAC_MBIST_DONE))
+#define BIT_GET_MAC_MBIST_DONE(x)                                              \
+	(((x) >> BIT_SHIFT_MAC_MBIST_DONE) & BIT_MASK_MAC_MBIST_DONE)
+#define BIT_SET_MAC_MBIST_DONE(x, v)                                           \
+	(BIT_CLEAR_MAC_MBIST_DONE(x) | BIT_MAC_MBIST_DONE(v))
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_MBIST_DONE				(Offset 0x0178) */
+
+#define BIT_SHIFT_USB_MBIST_DONE_V2 0
+#define BIT_MASK_USB_MBIST_DONE_V2 0x3
+#define BIT_USB_MBIST_DONE_V2(x)                                               \
+	(((x) & BIT_MASK_USB_MBIST_DONE_V2) << BIT_SHIFT_USB_MBIST_DONE_V2)
+#define BITS_USB_MBIST_DONE_V2                                                 \
+	(BIT_MASK_USB_MBIST_DONE_V2 << BIT_SHIFT_USB_MBIST_DONE_V2)
+#define BIT_CLEAR_USB_MBIST_DONE_V2(x) ((x) & (~BITS_USB_MBIST_DONE_V2))
+#define BIT_GET_USB_MBIST_DONE_V2(x)                                           \
+	(((x) >> BIT_SHIFT_USB_MBIST_DONE_V2) & BIT_MASK_USB_MBIST_DONE_V2)
+#define BIT_SET_USB_MBIST_DONE_V2(x, v)                                        \
+	(BIT_CLEAR_USB_MBIST_DONE_V2(x) | BIT_USB_MBIST_DONE_V2(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_MBIST_DONE				(Offset 0x0178) */
+
+#define BIT_SHIFT_MAC_MBIST_DONE_V1 0
+#define BIT_MASK_MAC_MBIST_DONE_V1 0x3ffff
+#define BIT_MAC_MBIST_DONE_V1(x)                                               \
+	(((x) & BIT_MASK_MAC_MBIST_DONE_V1) << BIT_SHIFT_MAC_MBIST_DONE_V1)
+#define BITS_MAC_MBIST_DONE_V1                                                 \
+	(BIT_MASK_MAC_MBIST_DONE_V1 << BIT_SHIFT_MAC_MBIST_DONE_V1)
+#define BIT_CLEAR_MAC_MBIST_DONE_V1(x) ((x) & (~BITS_MAC_MBIST_DONE_V1))
+#define BIT_GET_MAC_MBIST_DONE_V1(x)                                           \
+	(((x) >> BIT_SHIFT_MAC_MBIST_DONE_V1) & BIT_MASK_MAC_MBIST_DONE_V1)
+#define BIT_SET_MAC_MBIST_DONE_V1(x, v)                                        \
+	(BIT_CLEAR_MAC_MBIST_DONE_V1(x) | BIT_MAC_MBIST_DONE_V1(v))
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_MBIST_NRML_FAIL			(Offset 0x017C) */
+
+#define BIT_SHIFT_WLON_MBIST_NRML_FAIL 30
+#define BIT_MASK_WLON_MBIST_NRML_FAIL 0x3
+#define BIT_WLON_MBIST_NRML_FAIL(x)                                            \
+	(((x) & BIT_MASK_WLON_MBIST_NRML_FAIL)                                 \
+	 << BIT_SHIFT_WLON_MBIST_NRML_FAIL)
+#define BITS_WLON_MBIST_NRML_FAIL                                              \
+	(BIT_MASK_WLON_MBIST_NRML_FAIL << BIT_SHIFT_WLON_MBIST_NRML_FAIL)
+#define BIT_CLEAR_WLON_MBIST_NRML_FAIL(x) ((x) & (~BITS_WLON_MBIST_NRML_FAIL))
+#define BIT_GET_WLON_MBIST_NRML_FAIL(x)                                        \
+	(((x) >> BIT_SHIFT_WLON_MBIST_NRML_FAIL) &                             \
+	 BIT_MASK_WLON_MBIST_NRML_FAIL)
+#define BIT_SET_WLON_MBIST_NRML_FAIL(x, v)                                     \
+	(BIT_CLEAR_WLON_MBIST_NRML_FAIL(x) | BIT_WLON_MBIST_NRML_FAIL(v))
+
+#define BIT_SHIFT_WLOFF_MBIST_NRML_FAIL 16
+#define BIT_MASK_WLOFF_MBIST_NRML_FAIL 0x3fff
+#define BIT_WLOFF_MBIST_NRML_FAIL(x)                                           \
+	(((x) & BIT_MASK_WLOFF_MBIST_NRML_FAIL)                                \
+	 << BIT_SHIFT_WLOFF_MBIST_NRML_FAIL)
+#define BITS_WLOFF_MBIST_NRML_FAIL                                             \
+	(BIT_MASK_WLOFF_MBIST_NRML_FAIL << BIT_SHIFT_WLOFF_MBIST_NRML_FAIL)
+#define BIT_CLEAR_WLOFF_MBIST_NRML_FAIL(x) ((x) & (~BITS_WLOFF_MBIST_NRML_FAIL))
+#define BIT_GET_WLOFF_MBIST_NRML_FAIL(x)                                       \
+	(((x) >> BIT_SHIFT_WLOFF_MBIST_NRML_FAIL) &                            \
+	 BIT_MASK_WLOFF_MBIST_NRML_FAIL)
+#define BIT_SET_WLOFF_MBIST_NRML_FAIL(x, v)                                    \
+	(BIT_CLEAR_WLOFF_MBIST_NRML_FAIL(x) | BIT_WLOFF_MBIST_NRML_FAIL(v))
+
+#define BIT_SHIFT_PCIE_MBIST_NRML_FAIL 11
+#define BIT_MASK_PCIE_MBIST_NRML_FAIL 0x1f
+#define BIT_PCIE_MBIST_NRML_FAIL(x)                                            \
+	(((x) & BIT_MASK_PCIE_MBIST_NRML_FAIL)                                 \
+	 << BIT_SHIFT_PCIE_MBIST_NRML_FAIL)
+#define BITS_PCIE_MBIST_NRML_FAIL                                              \
+	(BIT_MASK_PCIE_MBIST_NRML_FAIL << BIT_SHIFT_PCIE_MBIST_NRML_FAIL)
+#define BIT_CLEAR_PCIE_MBIST_NRML_FAIL(x) ((x) & (~BITS_PCIE_MBIST_NRML_FAIL))
+#define BIT_GET_PCIE_MBIST_NRML_FAIL(x)                                        \
+	(((x) >> BIT_SHIFT_PCIE_MBIST_NRML_FAIL) &                             \
+	 BIT_MASK_PCIE_MBIST_NRML_FAIL)
+#define BIT_SET_PCIE_MBIST_NRML_FAIL(x, v)                                     \
+	(BIT_CLEAR_PCIE_MBIST_NRML_FAIL(x) | BIT_PCIE_MBIST_NRML_FAIL(v))
+
+#define BIT_SHIFT_USB_MBIST_NRML_FAIL 4
+#define BIT_MASK_USB_MBIST_NRML_FAIL 0x7f
+#define BIT_USB_MBIST_NRML_FAIL(x)                                             \
+	(((x) & BIT_MASK_USB_MBIST_NRML_FAIL) << BIT_SHIFT_USB_MBIST_NRML_FAIL)
+#define BITS_USB_MBIST_NRML_FAIL                                               \
+	(BIT_MASK_USB_MBIST_NRML_FAIL << BIT_SHIFT_USB_MBIST_NRML_FAIL)
+#define BIT_CLEAR_USB_MBIST_NRML_FAIL(x) ((x) & (~BITS_USB_MBIST_NRML_FAIL))
+#define BIT_GET_USB_MBIST_NRML_FAIL(x)                                         \
+	(((x) >> BIT_SHIFT_USB_MBIST_NRML_FAIL) & BIT_MASK_USB_MBIST_NRML_FAIL)
+#define BIT_SET_USB_MBIST_NRML_FAIL(x, v)                                      \
+	(BIT_CLEAR_USB_MBIST_NRML_FAIL(x) | BIT_USB_MBIST_NRML_FAIL(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_MBIST_ROM_CRC_DATA			(Offset 0x017C) */
+
+#define BIT_SHIFT_MBIST_ROM_CRC_DATA 0
+#define BIT_MASK_MBIST_ROM_CRC_DATA 0xffffffffL
+#define BIT_MBIST_ROM_CRC_DATA(x)                                              \
+	(((x) & BIT_MASK_MBIST_ROM_CRC_DATA) << BIT_SHIFT_MBIST_ROM_CRC_DATA)
+#define BITS_MBIST_ROM_CRC_DATA                                                \
+	(BIT_MASK_MBIST_ROM_CRC_DATA << BIT_SHIFT_MBIST_ROM_CRC_DATA)
+#define BIT_CLEAR_MBIST_ROM_CRC_DATA(x) ((x) & (~BITS_MBIST_ROM_CRC_DATA))
+#define BIT_GET_MBIST_ROM_CRC_DATA(x)                                          \
+	(((x) >> BIT_SHIFT_MBIST_ROM_CRC_DATA) & BIT_MASK_MBIST_ROM_CRC_DATA)
+#define BIT_SET_MBIST_ROM_CRC_DATA(x, v)                                       \
+	(BIT_CLEAR_MBIST_ROM_CRC_DATA(x) | BIT_MBIST_ROM_CRC_DATA(v))
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_MBIST_NRML_FAIL			(Offset 0x017C) */
+
+#define BIT_SHIFT_USB_WLON_MBIST_NRML_FAIL 0
+#define BIT_MASK_USB_WLON_MBIST_NRML_FAIL 0xf
+#define BIT_USB_WLON_MBIST_NRML_FAIL(x)                                        \
+	(((x) & BIT_MASK_USB_WLON_MBIST_NRML_FAIL)                             \
+	 << BIT_SHIFT_USB_WLON_MBIST_NRML_FAIL)
+#define BITS_USB_WLON_MBIST_NRML_FAIL                                          \
+	(BIT_MASK_USB_WLON_MBIST_NRML_FAIL                                     \
+	 << BIT_SHIFT_USB_WLON_MBIST_NRML_FAIL)
+#define BIT_CLEAR_USB_WLON_MBIST_NRML_FAIL(x)                                  \
+	((x) & (~BITS_USB_WLON_MBIST_NRML_FAIL))
+#define BIT_GET_USB_WLON_MBIST_NRML_FAIL(x)                                    \
+	(((x) >> BIT_SHIFT_USB_WLON_MBIST_NRML_FAIL) &                         \
+	 BIT_MASK_USB_WLON_MBIST_NRML_FAIL)
+#define BIT_SET_USB_WLON_MBIST_NRML_FAIL(x, v)                                 \
+	(BIT_CLEAR_USB_WLON_MBIST_NRML_FAIL(x) |                               \
+	 BIT_USB_WLON_MBIST_NRML_FAIL(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_MBIST_FAIL_NRML			(Offset 0x017C) */
+
+#define BIT_SHIFT_MBIST_FAIL_NRML_V1 0
+#define BIT_MASK_MBIST_FAIL_NRML_V1 0x3ffff
+#define BIT_MBIST_FAIL_NRML_V1(x)                                              \
+	(((x) & BIT_MASK_MBIST_FAIL_NRML_V1) << BIT_SHIFT_MBIST_FAIL_NRML_V1)
+#define BITS_MBIST_FAIL_NRML_V1                                                \
+	(BIT_MASK_MBIST_FAIL_NRML_V1 << BIT_SHIFT_MBIST_FAIL_NRML_V1)
+#define BIT_CLEAR_MBIST_FAIL_NRML_V1(x) ((x) & (~BITS_MBIST_FAIL_NRML_V1))
+#define BIT_GET_MBIST_FAIL_NRML_V1(x)                                          \
+	(((x) >> BIT_SHIFT_MBIST_FAIL_NRML_V1) & BIT_MASK_MBIST_FAIL_NRML_V1)
+#define BIT_SET_MBIST_FAIL_NRML_V1(x, v)                                       \
+	(BIT_CLEAR_MBIST_FAIL_NRML_V1(x) | BIT_MBIST_FAIL_NRML_V1(v))
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT)
+
+/* 2 REG_MBIST_FAIL_NRML			(Offset 0x017C) */
+
+#define BIT_SHIFT_MBIST_FAIL_NRML 0
+#define BIT_MASK_MBIST_FAIL_NRML 0xffffffffL
+#define BIT_MBIST_FAIL_NRML(x)                                                 \
+	(((x) & BIT_MASK_MBIST_FAIL_NRML) << BIT_SHIFT_MBIST_FAIL_NRML)
+#define BITS_MBIST_FAIL_NRML                                                   \
+	(BIT_MASK_MBIST_FAIL_NRML << BIT_SHIFT_MBIST_FAIL_NRML)
+#define BIT_CLEAR_MBIST_FAIL_NRML(x) ((x) & (~BITS_MBIST_FAIL_NRML))
+#define BIT_GET_MBIST_FAIL_NRML(x)                                             \
+	(((x) >> BIT_SHIFT_MBIST_FAIL_NRML) & BIT_MASK_MBIST_FAIL_NRML)
+#define BIT_SET_MBIST_FAIL_NRML(x, v)                                          \
+	(BIT_CLEAR_MBIST_FAIL_NRML(x) | BIT_MBIST_FAIL_NRML(v))
+
+#define BIT_SHIFT_R_WMAC_IPV6_MYIPAD 0
+#define BIT_MASK_R_WMAC_IPV6_MYIPAD 0xffffffffffffffffffffffffffffffffL
+#define BIT_R_WMAC_IPV6_MYIPAD(x)                                              \
+	(((x) & BIT_MASK_R_WMAC_IPV6_MYIPAD) << BIT_SHIFT_R_WMAC_IPV6_MYIPAD)
+#define BITS_R_WMAC_IPV6_MYIPAD                                                \
+	(BIT_MASK_R_WMAC_IPV6_MYIPAD << BIT_SHIFT_R_WMAC_IPV6_MYIPAD)
+#define BIT_CLEAR_R_WMAC_IPV6_MYIPAD(x) ((x) & (~BITS_R_WMAC_IPV6_MYIPAD))
+#define BIT_GET_R_WMAC_IPV6_MYIPAD(x)                                          \
+	(((x) >> BIT_SHIFT_R_WMAC_IPV6_MYIPAD) & BIT_MASK_R_WMAC_IPV6_MYIPAD)
+#define BIT_SET_R_WMAC_IPV6_MYIPAD(x, v)                                       \
+	(BIT_CLEAR_R_WMAC_IPV6_MYIPAD(x) | BIT_R_WMAC_IPV6_MYIPAD(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_AES_DECRPT_DATA			(Offset 0x0180) */
+
+#define BIT_SHIFT_IPS_CFG_ADDR 0
+#define BIT_MASK_IPS_CFG_ADDR 0xff
+#define BIT_IPS_CFG_ADDR(x)                                                    \
+	(((x) & BIT_MASK_IPS_CFG_ADDR) << BIT_SHIFT_IPS_CFG_ADDR)
+#define BITS_IPS_CFG_ADDR (BIT_MASK_IPS_CFG_ADDR << BIT_SHIFT_IPS_CFG_ADDR)
+#define BIT_CLEAR_IPS_CFG_ADDR(x) ((x) & (~BITS_IPS_CFG_ADDR))
+#define BIT_GET_IPS_CFG_ADDR(x)                                                \
+	(((x) >> BIT_SHIFT_IPS_CFG_ADDR) & BIT_MASK_IPS_CFG_ADDR)
+#define BIT_SET_IPS_CFG_ADDR(x, v)                                             \
+	(BIT_CLEAR_IPS_CFG_ADDR(x) | BIT_IPS_CFG_ADDR(v))
+
+/* 2 REG_AES_DECRPT_CFG			(Offset 0x0184) */
+
+#define BIT_SHIFT_IPS_CFG_DATA 0
+#define BIT_MASK_IPS_CFG_DATA 0xffffffffL
+#define BIT_IPS_CFG_DATA(x)                                                    \
+	(((x) & BIT_MASK_IPS_CFG_DATA) << BIT_SHIFT_IPS_CFG_DATA)
+#define BITS_IPS_CFG_DATA (BIT_MASK_IPS_CFG_DATA << BIT_SHIFT_IPS_CFG_DATA)
+#define BIT_CLEAR_IPS_CFG_DATA(x) ((x) & (~BITS_IPS_CFG_DATA))
+#define BIT_GET_IPS_CFG_DATA(x)                                                \
+	(((x) >> BIT_SHIFT_IPS_CFG_DATA) & BIT_MASK_IPS_CFG_DATA)
+#define BIT_SET_IPS_CFG_DATA(x, v)                                             \
+	(BIT_CLEAR_IPS_CFG_DATA(x) | BIT_IPS_CFG_DATA(v))
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_HIOE_CTRL				(Offset 0x0188) */
+
+#define BIT_HIOE_CFG_FILE_LOC_SEL BIT(31)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_HIOE_CTRL				(Offset 0x0188) */
+
+#define BIT_HIOE_WRITE_REQ BIT(30)
+#define BIT_HIOE_READ_REQ BIT(29)
+#define BIT_INST_FORMAT_ERR BIT(25)
+#define BIT_OP_TIMEOUT_ERR BIT(24)
+
+#define BIT_SHIFT_HIOE_OP_TIMEOUT 16
+#define BIT_MASK_HIOE_OP_TIMEOUT 0xff
+#define BIT_HIOE_OP_TIMEOUT(x)                                                 \
+	(((x) & BIT_MASK_HIOE_OP_TIMEOUT) << BIT_SHIFT_HIOE_OP_TIMEOUT)
+#define BITS_HIOE_OP_TIMEOUT                                                   \
+	(BIT_MASK_HIOE_OP_TIMEOUT << BIT_SHIFT_HIOE_OP_TIMEOUT)
+#define BIT_CLEAR_HIOE_OP_TIMEOUT(x) ((x) & (~BITS_HIOE_OP_TIMEOUT))
+#define BIT_GET_HIOE_OP_TIMEOUT(x)                                             \
+	(((x) >> BIT_SHIFT_HIOE_OP_TIMEOUT) & BIT_MASK_HIOE_OP_TIMEOUT)
+#define BIT_SET_HIOE_OP_TIMEOUT(x, v)                                          \
+	(BIT_CLEAR_HIOE_OP_TIMEOUT(x) | BIT_HIOE_OP_TIMEOUT(v))
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_MBIST_READ_BIST_RPT_V1		(Offset 0x0188) */
+
+#define BIT_SHIFT_MBIST_READ_BIST_RPT 0
+#define BIT_MASK_MBIST_READ_BIST_RPT 0xffffffffL
+#define BIT_MBIST_READ_BIST_RPT(x)                                             \
+	(((x) & BIT_MASK_MBIST_READ_BIST_RPT) << BIT_SHIFT_MBIST_READ_BIST_RPT)
+#define BITS_MBIST_READ_BIST_RPT                                               \
+	(BIT_MASK_MBIST_READ_BIST_RPT << BIT_SHIFT_MBIST_READ_BIST_RPT)
+#define BIT_CLEAR_MBIST_READ_BIST_RPT(x) ((x) & (~BITS_MBIST_READ_BIST_RPT))
+#define BIT_GET_MBIST_READ_BIST_RPT(x)                                         \
+	(((x) >> BIT_SHIFT_MBIST_READ_BIST_RPT) & BIT_MASK_MBIST_READ_BIST_RPT)
+#define BIT_SET_MBIST_READ_BIST_RPT(x, v)                                      \
+	(BIT_CLEAR_MBIST_READ_BIST_RPT(x) | BIT_MBIST_READ_BIST_RPT(v))
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_HIOE_CTRL				(Offset 0x0188) */
+
+#define BIT_SHIFT_BITDATA_CHECKSUM 0
+#define BIT_MASK_BITDATA_CHECKSUM 0xffff
+#define BIT_BITDATA_CHECKSUM(x)                                                \
+	(((x) & BIT_MASK_BITDATA_CHECKSUM) << BIT_SHIFT_BITDATA_CHECKSUM)
+#define BITS_BITDATA_CHECKSUM                                                  \
+	(BIT_MASK_BITDATA_CHECKSUM << BIT_SHIFT_BITDATA_CHECKSUM)
+#define BIT_CLEAR_BITDATA_CHECKSUM(x) ((x) & (~BITS_BITDATA_CHECKSUM))
+#define BIT_GET_BITDATA_CHECKSUM(x)                                            \
+	(((x) >> BIT_SHIFT_BITDATA_CHECKSUM) & BIT_MASK_BITDATA_CHECKSUM)
+#define BIT_SET_BITDATA_CHECKSUM(x, v)                                         \
+	(BIT_CLEAR_BITDATA_CHECKSUM(x) | BIT_BITDATA_CHECKSUM(v))
+
+/* 2 REG_HIOE_CFG_FILE			(Offset 0x018C) */
+
+#define BIT_SHIFT_TXBF_END_ADDR 16
+#define BIT_MASK_TXBF_END_ADDR 0xffff
+#define BIT_TXBF_END_ADDR(x)                                                   \
+	(((x) & BIT_MASK_TXBF_END_ADDR) << BIT_SHIFT_TXBF_END_ADDR)
+#define BITS_TXBF_END_ADDR (BIT_MASK_TXBF_END_ADDR << BIT_SHIFT_TXBF_END_ADDR)
+#define BIT_CLEAR_TXBF_END_ADDR(x) ((x) & (~BITS_TXBF_END_ADDR))
+#define BIT_GET_TXBF_END_ADDR(x)                                               \
+	(((x) >> BIT_SHIFT_TXBF_END_ADDR) & BIT_MASK_TXBF_END_ADDR)
+#define BIT_SET_TXBF_END_ADDR(x, v)                                            \
+	(BIT_CLEAR_TXBF_END_ADDR(x) | BIT_TXBF_END_ADDR(v))
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_MACCLKFRQ				(Offset 0x018C) */
+
+#define BIT_SHIFT_MACCLK_FREQ_LOW32 0
+#define BIT_MASK_MACCLK_FREQ_LOW32 0xffffffffL
+#define BIT_MACCLK_FREQ_LOW32(x)                                               \
+	(((x) & BIT_MASK_MACCLK_FREQ_LOW32) << BIT_SHIFT_MACCLK_FREQ_LOW32)
+#define BITS_MACCLK_FREQ_LOW32                                                 \
+	(BIT_MASK_MACCLK_FREQ_LOW32 << BIT_SHIFT_MACCLK_FREQ_LOW32)
+#define BIT_CLEAR_MACCLK_FREQ_LOW32(x) ((x) & (~BITS_MACCLK_FREQ_LOW32))
+#define BIT_GET_MACCLK_FREQ_LOW32(x)                                           \
+	(((x) >> BIT_SHIFT_MACCLK_FREQ_LOW32) & BIT_MASK_MACCLK_FREQ_LOW32)
+#define BIT_SET_MACCLK_FREQ_LOW32(x, v)                                        \
+	(BIT_CLEAR_MACCLK_FREQ_LOW32(x) | BIT_MACCLK_FREQ_LOW32(v))
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_HIOE_CFG_FILE			(Offset 0x018C) */
+
+#define BIT_SHIFT_TXBF_STR_ADDR 0
+#define BIT_MASK_TXBF_STR_ADDR 0xffff
+#define BIT_TXBF_STR_ADDR(x)                                                   \
+	(((x) & BIT_MASK_TXBF_STR_ADDR) << BIT_SHIFT_TXBF_STR_ADDR)
+#define BITS_TXBF_STR_ADDR (BIT_MASK_TXBF_STR_ADDR << BIT_SHIFT_TXBF_STR_ADDR)
+#define BIT_CLEAR_TXBF_STR_ADDR(x) ((x) & (~BITS_TXBF_STR_ADDR))
+#define BIT_GET_TXBF_STR_ADDR(x)                                               \
+	(((x) >> BIT_SHIFT_TXBF_STR_ADDR) & BIT_MASK_TXBF_STR_ADDR)
+#define BIT_SET_TXBF_STR_ADDR(x, v)                                            \
+	(BIT_CLEAR_TXBF_STR_ADDR(x) | BIT_TXBF_STR_ADDR(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_TMETER				(Offset 0x0190) */
+
+#define BIT_TEMP_VALID BIT(31)
+
+#define BIT_SHIFT_TEMP_VALUE 24
+#define BIT_MASK_TEMP_VALUE 0x3f
+#define BIT_TEMP_VALUE(x) (((x) & BIT_MASK_TEMP_VALUE) << BIT_SHIFT_TEMP_VALUE)
+#define BITS_TEMP_VALUE (BIT_MASK_TEMP_VALUE << BIT_SHIFT_TEMP_VALUE)
+#define BIT_CLEAR_TEMP_VALUE(x) ((x) & (~BITS_TEMP_VALUE))
+#define BIT_GET_TEMP_VALUE(x)                                                  \
+	(((x) >> BIT_SHIFT_TEMP_VALUE) & BIT_MASK_TEMP_VALUE)
+#define BIT_SET_TEMP_VALUE(x, v) (BIT_CLEAR_TEMP_VALUE(x) | BIT_TEMP_VALUE(v))
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_TMETER				(Offset 0x0190) */
+
+#define BIT_SHIFT_NCO_OUTCLK_FREQ 12
+#define BIT_MASK_NCO_OUTCLK_FREQ 0xfffff
+#define BIT_NCO_OUTCLK_FREQ(x)                                                 \
+	(((x) & BIT_MASK_NCO_OUTCLK_FREQ) << BIT_SHIFT_NCO_OUTCLK_FREQ)
+#define BITS_NCO_OUTCLK_FREQ                                                   \
+	(BIT_MASK_NCO_OUTCLK_FREQ << BIT_SHIFT_NCO_OUTCLK_FREQ)
+#define BIT_CLEAR_NCO_OUTCLK_FREQ(x) ((x) & (~BITS_NCO_OUTCLK_FREQ))
+#define BIT_GET_NCO_OUTCLK_FREQ(x)                                             \
+	(((x) >> BIT_SHIFT_NCO_OUTCLK_FREQ) & BIT_MASK_NCO_OUTCLK_FREQ)
+#define BIT_SET_NCO_OUTCLK_FREQ(x, v)                                          \
+	(BIT_CLEAR_NCO_OUTCLK_FREQ(x) | BIT_NCO_OUTCLK_FREQ(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_TMETER				(Offset 0x0190) */
+
+#define BIT_SHIFT_REG_TMETER_TIMER 8
+#define BIT_MASK_REG_TMETER_TIMER 0xfff
+#define BIT_REG_TMETER_TIMER(x)                                                \
+	(((x) & BIT_MASK_REG_TMETER_TIMER) << BIT_SHIFT_REG_TMETER_TIMER)
+#define BITS_REG_TMETER_TIMER                                                  \
+	(BIT_MASK_REG_TMETER_TIMER << BIT_SHIFT_REG_TMETER_TIMER)
+#define BIT_CLEAR_REG_TMETER_TIMER(x) ((x) & (~BITS_REG_TMETER_TIMER))
+#define BIT_GET_REG_TMETER_TIMER(x)                                            \
+	(((x) >> BIT_SHIFT_REG_TMETER_TIMER) & BIT_MASK_REG_TMETER_TIMER)
+#define BIT_SET_REG_TMETER_TIMER(x, v)                                         \
+	(BIT_CLEAR_REG_TMETER_TIMER(x) | BIT_REG_TMETER_TIMER(v))
+
+#define BIT_SHIFT_REG_TEMP_DELTA 2
+#define BIT_MASK_REG_TEMP_DELTA 0x3f
+#define BIT_REG_TEMP_DELTA(x)                                                  \
+	(((x) & BIT_MASK_REG_TEMP_DELTA) << BIT_SHIFT_REG_TEMP_DELTA)
+#define BITS_REG_TEMP_DELTA                                                    \
+	(BIT_MASK_REG_TEMP_DELTA << BIT_SHIFT_REG_TEMP_DELTA)
+#define BIT_CLEAR_REG_TEMP_DELTA(x) ((x) & (~BITS_REG_TEMP_DELTA))
+#define BIT_GET_REG_TEMP_DELTA(x)                                              \
+	(((x) >> BIT_SHIFT_REG_TEMP_DELTA) & BIT_MASK_REG_TEMP_DELTA)
+#define BIT_SET_REG_TEMP_DELTA(x, v)                                           \
+	(BIT_CLEAR_REG_TEMP_DELTA(x) | BIT_REG_TEMP_DELTA(v))
+
+#define BIT_REG_TMETER_EN BIT(0)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_TMETER				(Offset 0x0190) */
+
+#define BIT_SHIFT_MACCLK_FREQ_HIGH10 0
+#define BIT_MASK_MACCLK_FREQ_HIGH10 0x3ff
+#define BIT_MACCLK_FREQ_HIGH10(x)                                              \
+	(((x) & BIT_MASK_MACCLK_FREQ_HIGH10) << BIT_SHIFT_MACCLK_FREQ_HIGH10)
+#define BITS_MACCLK_FREQ_HIGH10                                                \
+	(BIT_MASK_MACCLK_FREQ_HIGH10 << BIT_SHIFT_MACCLK_FREQ_HIGH10)
+#define BIT_CLEAR_MACCLK_FREQ_HIGH10(x) ((x) & (~BITS_MACCLK_FREQ_HIGH10))
+#define BIT_GET_MACCLK_FREQ_HIGH10(x)                                          \
+	(((x) >> BIT_SHIFT_MACCLK_FREQ_HIGH10) & BIT_MASK_MACCLK_FREQ_HIGH10)
+#define BIT_SET_MACCLK_FREQ_HIGH10(x, v)                                       \
+	(BIT_CLEAR_MACCLK_FREQ_HIGH10(x) | BIT_MACCLK_FREQ_HIGH10(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_OSC_32K_CTRL			(Offset 0x0194) */
+
+#define BIT_SHIFT_OSC_32K_CLKGEN_0 16
+#define BIT_MASK_OSC_32K_CLKGEN_0 0xffff
+#define BIT_OSC_32K_CLKGEN_0(x)                                                \
+	(((x) & BIT_MASK_OSC_32K_CLKGEN_0) << BIT_SHIFT_OSC_32K_CLKGEN_0)
+#define BITS_OSC_32K_CLKGEN_0                                                  \
+	(BIT_MASK_OSC_32K_CLKGEN_0 << BIT_SHIFT_OSC_32K_CLKGEN_0)
+#define BIT_CLEAR_OSC_32K_CLKGEN_0(x) ((x) & (~BITS_OSC_32K_CLKGEN_0))
+#define BIT_GET_OSC_32K_CLKGEN_0(x)                                            \
+	(((x) >> BIT_SHIFT_OSC_32K_CLKGEN_0) & BIT_MASK_OSC_32K_CLKGEN_0)
+#define BIT_SET_OSC_32K_CLKGEN_0(x, v)                                         \
+	(BIT_CLEAR_OSC_32K_CLKGEN_0(x) | BIT_OSC_32K_CLKGEN_0(v))
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_OSC_32K_CTRL			(Offset 0x0194) */
+
+#define BIT_32K_CLK_OUT_RDY BIT(12)
+
+#define BIT_SHIFT_MONITOR_CYCLE_LOG2 8
+#define BIT_MASK_MONITOR_CYCLE_LOG2 0xf
+#define BIT_MONITOR_CYCLE_LOG2(x)                                              \
+	(((x) & BIT_MASK_MONITOR_CYCLE_LOG2) << BIT_SHIFT_MONITOR_CYCLE_LOG2)
+#define BITS_MONITOR_CYCLE_LOG2                                                \
+	(BIT_MASK_MONITOR_CYCLE_LOG2 << BIT_SHIFT_MONITOR_CYCLE_LOG2)
+#define BIT_CLEAR_MONITOR_CYCLE_LOG2(x) ((x) & (~BITS_MONITOR_CYCLE_LOG2))
+#define BIT_GET_MONITOR_CYCLE_LOG2(x)                                          \
+	(((x) >> BIT_SHIFT_MONITOR_CYCLE_LOG2) & BIT_MASK_MONITOR_CYCLE_LOG2)
+#define BIT_SET_MONITOR_CYCLE_LOG2(x, v)                                       \
+	(BIT_CLEAR_MONITOR_CYCLE_LOG2(x) | BIT_MONITOR_CYCLE_LOG2(v))
+
+#define BIT_SHIFT_FREQVALUE_UNREGCLK 8
+#define BIT_MASK_FREQVALUE_UNREGCLK 0xffffff
+#define BIT_FREQVALUE_UNREGCLK(x)                                              \
+	(((x) & BIT_MASK_FREQVALUE_UNREGCLK) << BIT_SHIFT_FREQVALUE_UNREGCLK)
+#define BITS_FREQVALUE_UNREGCLK                                                \
+	(BIT_MASK_FREQVALUE_UNREGCLK << BIT_SHIFT_FREQVALUE_UNREGCLK)
+#define BIT_CLEAR_FREQVALUE_UNREGCLK(x) ((x) & (~BITS_FREQVALUE_UNREGCLK))
+#define BIT_GET_FREQVALUE_UNREGCLK(x)                                          \
+	(((x) >> BIT_SHIFT_FREQVALUE_UNREGCLK) & BIT_MASK_FREQVALUE_UNREGCLK)
+#define BIT_SET_FREQVALUE_UNREGCLK(x, v)                                       \
+	(BIT_CLEAR_FREQVALUE_UNREGCLK(x) | BIT_FREQVALUE_UNREGCLK(v))
+
+#define BIT_CAL32K_DBGMOD BIT(7)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_OSC_32K_CTRL			(Offset 0x0194) */
+
+#define BIT_SHIFT_OSC_32K_RES_COMP 4
+#define BIT_MASK_OSC_32K_RES_COMP 0x3
+#define BIT_OSC_32K_RES_COMP(x)                                                \
+	(((x) & BIT_MASK_OSC_32K_RES_COMP) << BIT_SHIFT_OSC_32K_RES_COMP)
+#define BITS_OSC_32K_RES_COMP                                                  \
+	(BIT_MASK_OSC_32K_RES_COMP << BIT_SHIFT_OSC_32K_RES_COMP)
+#define BIT_CLEAR_OSC_32K_RES_COMP(x) ((x) & (~BITS_OSC_32K_RES_COMP))
+#define BIT_GET_OSC_32K_RES_COMP(x)                                            \
+	(((x) >> BIT_SHIFT_OSC_32K_RES_COMP) & BIT_MASK_OSC_32K_RES_COMP)
+#define BIT_SET_OSC_32K_RES_COMP(x, v)                                         \
+	(BIT_CLEAR_OSC_32K_RES_COMP(x) | BIT_OSC_32K_RES_COMP(v))
+
+#define BIT_OSC_32K_OUT_SEL BIT(3)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_OSC_32K_CTRL			(Offset 0x0194) */
+
+#define BIT_ISO_WL_2_OSC_32K BIT(1)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_OSC_32K_CTRL			(Offset 0x0194) */
+
+#define BIT_POW_CKGEN BIT(0)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_OSC_32K_CTRL			(Offset 0x0194) */
+
+#define BIT_SHIFT_NCO_THRS 0
+#define BIT_MASK_NCO_THRS 0x7f
+#define BIT_NCO_THRS(x) (((x) & BIT_MASK_NCO_THRS) << BIT_SHIFT_NCO_THRS)
+#define BITS_NCO_THRS (BIT_MASK_NCO_THRS << BIT_SHIFT_NCO_THRS)
+#define BIT_CLEAR_NCO_THRS(x) ((x) & (~BITS_NCO_THRS))
+#define BIT_GET_NCO_THRS(x) (((x) >> BIT_SHIFT_NCO_THRS) & BIT_MASK_NCO_THRS)
+#define BIT_SET_NCO_THRS(x, v) (BIT_CLEAR_NCO_THRS(x) | BIT_NCO_THRS(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_32K_CAL_REG1			(Offset 0x0198) */
+
+#define BIT_CAL_32K_REG_WR BIT(31)
+#define BIT_CAL_32K_DBG_SEL BIT(22)
+
+#define BIT_SHIFT_CAL_32K_REG_ADDR 16
+#define BIT_MASK_CAL_32K_REG_ADDR 0x3f
+#define BIT_CAL_32K_REG_ADDR(x)                                                \
+	(((x) & BIT_MASK_CAL_32K_REG_ADDR) << BIT_SHIFT_CAL_32K_REG_ADDR)
+#define BITS_CAL_32K_REG_ADDR                                                  \
+	(BIT_MASK_CAL_32K_REG_ADDR << BIT_SHIFT_CAL_32K_REG_ADDR)
+#define BIT_CLEAR_CAL_32K_REG_ADDR(x) ((x) & (~BITS_CAL_32K_REG_ADDR))
+#define BIT_GET_CAL_32K_REG_ADDR(x)                                            \
+	(((x) >> BIT_SHIFT_CAL_32K_REG_ADDR) & BIT_MASK_CAL_32K_REG_ADDR)
+#define BIT_SET_CAL_32K_REG_ADDR(x, v)                                         \
+	(BIT_CLEAR_CAL_32K_REG_ADDR(x) | BIT_CAL_32K_REG_ADDR(v))
+
+#define BIT_SHIFT_CAL_32K_REG_DATA 0
+#define BIT_MASK_CAL_32K_REG_DATA 0xffff
+#define BIT_CAL_32K_REG_DATA(x)                                                \
+	(((x) & BIT_MASK_CAL_32K_REG_DATA) << BIT_SHIFT_CAL_32K_REG_DATA)
+#define BITS_CAL_32K_REG_DATA                                                  \
+	(BIT_MASK_CAL_32K_REG_DATA << BIT_SHIFT_CAL_32K_REG_DATA)
+#define BIT_CLEAR_CAL_32K_REG_DATA(x) ((x) & (~BITS_CAL_32K_REG_DATA))
+#define BIT_GET_CAL_32K_REG_DATA(x)                                            \
+	(((x) >> BIT_SHIFT_CAL_32K_REG_DATA) & BIT_MASK_CAL_32K_REG_DATA)
+#define BIT_SET_CAL_32K_REG_DATA(x, v)                                         \
+	(BIT_CLEAR_CAL_32K_REG_DATA(x) | BIT_CAL_32K_REG_DATA(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_C2HEVT				(Offset 0x01A0) */
+
+#define BIT_SHIFT_C2HEVT_MSG 0
+#define BIT_MASK_C2HEVT_MSG 0xffffffffffffffffffffffffffffffffL
+#define BIT_C2HEVT_MSG(x) (((x) & BIT_MASK_C2HEVT_MSG) << BIT_SHIFT_C2HEVT_MSG)
+#define BITS_C2HEVT_MSG (BIT_MASK_C2HEVT_MSG << BIT_SHIFT_C2HEVT_MSG)
+#define BIT_CLEAR_C2HEVT_MSG(x) ((x) & (~BITS_C2HEVT_MSG))
+#define BIT_GET_C2HEVT_MSG(x)                                                  \
+	(((x) >> BIT_SHIFT_C2HEVT_MSG) & BIT_MASK_C2HEVT_MSG)
+#define BIT_SET_C2HEVT_MSG(x, v) (BIT_CLEAR_C2HEVT_MSG(x) | BIT_C2HEVT_MSG(v))
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_C2HEVT				(Offset 0x01A0) */
+
+#define BIT_SHIFT_C2HEVT_MSG_V1 0
+#define BIT_MASK_C2HEVT_MSG_V1 0xffffffffL
+#define BIT_C2HEVT_MSG_V1(x)                                                   \
+	(((x) & BIT_MASK_C2HEVT_MSG_V1) << BIT_SHIFT_C2HEVT_MSG_V1)
+#define BITS_C2HEVT_MSG_V1 (BIT_MASK_C2HEVT_MSG_V1 << BIT_SHIFT_C2HEVT_MSG_V1)
+#define BIT_CLEAR_C2HEVT_MSG_V1(x) ((x) & (~BITS_C2HEVT_MSG_V1))
+#define BIT_GET_C2HEVT_MSG_V1(x)                                               \
+	(((x) >> BIT_SHIFT_C2HEVT_MSG_V1) & BIT_MASK_C2HEVT_MSG_V1)
+#define BIT_SET_C2HEVT_MSG_V1(x, v)                                            \
+	(BIT_CLEAR_C2HEVT_MSG_V1(x) | BIT_C2HEVT_MSG_V1(v))
+
+/* 2 REG_C2HEVT_1				(Offset 0x01A4) */
+
+#define BIT_SHIFT_C2HEVT_MSG_1 0
+#define BIT_MASK_C2HEVT_MSG_1 0xffffffffL
+#define BIT_C2HEVT_MSG_1(x)                                                    \
+	(((x) & BIT_MASK_C2HEVT_MSG_1) << BIT_SHIFT_C2HEVT_MSG_1)
+#define BITS_C2HEVT_MSG_1 (BIT_MASK_C2HEVT_MSG_1 << BIT_SHIFT_C2HEVT_MSG_1)
+#define BIT_CLEAR_C2HEVT_MSG_1(x) ((x) & (~BITS_C2HEVT_MSG_1))
+#define BIT_GET_C2HEVT_MSG_1(x)                                                \
+	(((x) >> BIT_SHIFT_C2HEVT_MSG_1) & BIT_MASK_C2HEVT_MSG_1)
+#define BIT_SET_C2HEVT_MSG_1(x, v)                                             \
+	(BIT_CLEAR_C2HEVT_MSG_1(x) | BIT_C2HEVT_MSG_1(v))
+
+/* 2 REG_C2HEVT_2				(Offset 0x01A8) */
+
+#define BIT_SHIFT_C2HEVT_MSG_2 0
+#define BIT_MASK_C2HEVT_MSG_2 0xffffffffL
+#define BIT_C2HEVT_MSG_2(x)                                                    \
+	(((x) & BIT_MASK_C2HEVT_MSG_2) << BIT_SHIFT_C2HEVT_MSG_2)
+#define BITS_C2HEVT_MSG_2 (BIT_MASK_C2HEVT_MSG_2 << BIT_SHIFT_C2HEVT_MSG_2)
+#define BIT_CLEAR_C2HEVT_MSG_2(x) ((x) & (~BITS_C2HEVT_MSG_2))
+#define BIT_GET_C2HEVT_MSG_2(x)                                                \
+	(((x) >> BIT_SHIFT_C2HEVT_MSG_2) & BIT_MASK_C2HEVT_MSG_2)
+#define BIT_SET_C2HEVT_MSG_2(x, v)                                             \
+	(BIT_CLEAR_C2HEVT_MSG_2(x) | BIT_C2HEVT_MSG_2(v))
+
+/* 2 REG_C2HEVT_3				(Offset 0x01AC) */
+
+#define BIT_SHIFT_C2HEVT_MSG_3 0
+#define BIT_MASK_C2HEVT_MSG_3 0xffffffffL
+#define BIT_C2HEVT_MSG_3(x)                                                    \
+	(((x) & BIT_MASK_C2HEVT_MSG_3) << BIT_SHIFT_C2HEVT_MSG_3)
+#define BITS_C2HEVT_MSG_3 (BIT_MASK_C2HEVT_MSG_3 << BIT_SHIFT_C2HEVT_MSG_3)
+#define BIT_CLEAR_C2HEVT_MSG_3(x) ((x) & (~BITS_C2HEVT_MSG_3))
+#define BIT_GET_C2HEVT_MSG_3(x)                                                \
+	(((x) >> BIT_SHIFT_C2HEVT_MSG_3) & BIT_MASK_C2HEVT_MSG_3)
+#define BIT_SET_C2HEVT_MSG_3(x, v)                                             \
+	(BIT_CLEAR_C2HEVT_MSG_3(x) | BIT_C2HEVT_MSG_3(v))
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_MISC_CTRL_V1			(Offset 0x01B0) */
+
+#define BIT_SHIFT_PHYWR_SETUP_CNT 28
+#define BIT_MASK_PHYWR_SETUP_CNT 0xf
+#define BIT_PHYWR_SETUP_CNT(x)                                                 \
+	(((x) & BIT_MASK_PHYWR_SETUP_CNT) << BIT_SHIFT_PHYWR_SETUP_CNT)
+#define BITS_PHYWR_SETUP_CNT                                                   \
+	(BIT_MASK_PHYWR_SETUP_CNT << BIT_SHIFT_PHYWR_SETUP_CNT)
+#define BIT_CLEAR_PHYWR_SETUP_CNT(x) ((x) & (~BITS_PHYWR_SETUP_CNT))
+#define BIT_GET_PHYWR_SETUP_CNT(x)                                             \
+	(((x) >> BIT_SHIFT_PHYWR_SETUP_CNT) & BIT_MASK_PHYWR_SETUP_CNT)
+#define BIT_SET_PHYWR_SETUP_CNT(x, v)                                          \
+	(BIT_CLEAR_PHYWR_SETUP_CNT(x) | BIT_PHYWR_SETUP_CNT(v))
+
+#define BIT_SHIFT_PHYWR_HOLD_CNT 24
+#define BIT_MASK_PHYWR_HOLD_CNT 0xf
+#define BIT_PHYWR_HOLD_CNT(x)                                                  \
+	(((x) & BIT_MASK_PHYWR_HOLD_CNT) << BIT_SHIFT_PHYWR_HOLD_CNT)
+#define BITS_PHYWR_HOLD_CNT                                                    \
+	(BIT_MASK_PHYWR_HOLD_CNT << BIT_SHIFT_PHYWR_HOLD_CNT)
+#define BIT_CLEAR_PHYWR_HOLD_CNT(x) ((x) & (~BITS_PHYWR_HOLD_CNT))
+#define BIT_GET_PHYWR_HOLD_CNT(x)                                              \
+	(((x) >> BIT_SHIFT_PHYWR_HOLD_CNT) & BIT_MASK_PHYWR_HOLD_CNT)
+#define BIT_SET_PHYWR_HOLD_CNT(x, v)                                           \
+	(BIT_CLEAR_PHYWR_HOLD_CNT(x) | BIT_PHYWR_HOLD_CNT(v))
+
+#define BIT_SHIFT_TXBUF_WKCAM_OFFSET 8
+#define BIT_MASK_TXBUF_WKCAM_OFFSET 0x1fff
+#define BIT_TXBUF_WKCAM_OFFSET(x)                                              \
+	(((x) & BIT_MASK_TXBUF_WKCAM_OFFSET) << BIT_SHIFT_TXBUF_WKCAM_OFFSET)
+#define BITS_TXBUF_WKCAM_OFFSET                                                \
+	(BIT_MASK_TXBUF_WKCAM_OFFSET << BIT_SHIFT_TXBUF_WKCAM_OFFSET)
+#define BIT_CLEAR_TXBUF_WKCAM_OFFSET(x) ((x) & (~BITS_TXBUF_WKCAM_OFFSET))
+#define BIT_GET_TXBUF_WKCAM_OFFSET(x)                                          \
+	(((x) >> BIT_SHIFT_TXBUF_WKCAM_OFFSET) & BIT_MASK_TXBUF_WKCAM_OFFSET)
+#define BIT_SET_TXBUF_WKCAM_OFFSET(x, v)                                       \
+	(BIT_CLEAR_TXBUF_WKCAM_OFFSET(x) | BIT_TXBUF_WKCAM_OFFSET(v))
+
+#define BIT_SHIFT_PHYRD_WAIT_CNT 4
+#define BIT_MASK_PHYRD_WAIT_CNT 0xf
+#define BIT_PHYRD_WAIT_CNT(x)                                                  \
+	(((x) & BIT_MASK_PHYRD_WAIT_CNT) << BIT_SHIFT_PHYRD_WAIT_CNT)
+#define BITS_PHYRD_WAIT_CNT                                                    \
+	(BIT_MASK_PHYRD_WAIT_CNT << BIT_SHIFT_PHYRD_WAIT_CNT)
+#define BIT_CLEAR_PHYRD_WAIT_CNT(x) ((x) & (~BITS_PHYRD_WAIT_CNT))
+#define BIT_GET_PHYRD_WAIT_CNT(x)                                              \
+	(((x) >> BIT_SHIFT_PHYRD_WAIT_CNT) & BIT_MASK_PHYRD_WAIT_CNT)
+#define BIT_SET_PHYRD_WAIT_CNT(x, v)                                           \
+	(BIT_CLEAR_PHYRD_WAIT_CNT(x) | BIT_PHYRD_WAIT_CNT(v))
+
+#define BIT_SHIFT_H2CQ_PRI 0
+#define BIT_MASK_H2CQ_PRI 0x3
+#define BIT_H2CQ_PRI(x) (((x) & BIT_MASK_H2CQ_PRI) << BIT_SHIFT_H2CQ_PRI)
+#define BITS_H2CQ_PRI (BIT_MASK_H2CQ_PRI << BIT_SHIFT_H2CQ_PRI)
+#define BIT_CLEAR_H2CQ_PRI(x) ((x) & (~BITS_H2CQ_PRI))
+#define BIT_GET_H2CQ_PRI(x) (((x) >> BIT_SHIFT_H2CQ_PRI) & BIT_MASK_H2CQ_PRI)
+#define BIT_SET_H2CQ_PRI(x, v) (BIT_CLEAR_H2CQ_PRI(x) | BIT_H2CQ_PRI(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_RXDESC_BUFF_RPTR			(Offset 0x01B0) */
+
+#define BIT_SHIFT_RXDESC_BUFF_RPTR 0
+#define BIT_MASK_RXDESC_BUFF_RPTR 0xffffffffL
+#define BIT_RXDESC_BUFF_RPTR(x)                                                \
+	(((x) & BIT_MASK_RXDESC_BUFF_RPTR) << BIT_SHIFT_RXDESC_BUFF_RPTR)
+#define BITS_RXDESC_BUFF_RPTR                                                  \
+	(BIT_MASK_RXDESC_BUFF_RPTR << BIT_SHIFT_RXDESC_BUFF_RPTR)
+#define BIT_CLEAR_RXDESC_BUFF_RPTR(x) ((x) & (~BITS_RXDESC_BUFF_RPTR))
+#define BIT_GET_RXDESC_BUFF_RPTR(x)                                            \
+	(((x) >> BIT_SHIFT_RXDESC_BUFF_RPTR) & BIT_MASK_RXDESC_BUFF_RPTR)
+#define BIT_SET_RXDESC_BUFF_RPTR(x, v)                                         \
+	(BIT_CLEAR_RXDESC_BUFF_RPTR(x) | BIT_RXDESC_BUFF_RPTR(v))
+
+/* 2 REG_RXDESC_BUFF_WPTR			(Offset 0x01B4) */
+
+#define BIT_SHIFT_RXDESC_BUFF_WPTR 0
+#define BIT_MASK_RXDESC_BUFF_WPTR 0xffffffffL
+#define BIT_RXDESC_BUFF_WPTR(x)                                                \
+	(((x) & BIT_MASK_RXDESC_BUFF_WPTR) << BIT_SHIFT_RXDESC_BUFF_WPTR)
+#define BITS_RXDESC_BUFF_WPTR                                                  \
+	(BIT_MASK_RXDESC_BUFF_WPTR << BIT_SHIFT_RXDESC_BUFF_WPTR)
+#define BIT_CLEAR_RXDESC_BUFF_WPTR(x) ((x) & (~BITS_RXDESC_BUFF_WPTR))
+#define BIT_GET_RXDESC_BUFF_WPTR(x)                                            \
+	(((x) >> BIT_SHIFT_RXDESC_BUFF_WPTR) & BIT_MASK_RXDESC_BUFF_WPTR)
+#define BIT_SET_RXDESC_BUFF_WPTR(x, v)                                         \
+	(BIT_CLEAR_RXDESC_BUFF_WPTR(x) | BIT_RXDESC_BUFF_WPTR(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT || \
+     HALMAC_8881A_SUPPORT)
+
+/* 2 REG_SW_DEFINED_PAGE1			(Offset 0x01B8) */
+
+#define BIT_SHIFT_SW_DEFINED_PAGE1 0
+#define BIT_MASK_SW_DEFINED_PAGE1 0xffffffffffffffffL
+#define BIT_SW_DEFINED_PAGE1(x)                                                \
+	(((x) & BIT_MASK_SW_DEFINED_PAGE1) << BIT_SHIFT_SW_DEFINED_PAGE1)
+#define BITS_SW_DEFINED_PAGE1                                                  \
+	(BIT_MASK_SW_DEFINED_PAGE1 << BIT_SHIFT_SW_DEFINED_PAGE1)
+#define BIT_CLEAR_SW_DEFINED_PAGE1(x) ((x) & (~BITS_SW_DEFINED_PAGE1))
+#define BIT_GET_SW_DEFINED_PAGE1(x)                                            \
+	(((x) >> BIT_SHIFT_SW_DEFINED_PAGE1) & BIT_MASK_SW_DEFINED_PAGE1)
+#define BIT_SET_SW_DEFINED_PAGE1(x, v)                                         \
+	(BIT_CLEAR_SW_DEFINED_PAGE1(x) | BIT_SW_DEFINED_PAGE1(v))
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_SW_DEFINED_PAGE1			(Offset 0x01B8) */
+
+#define BIT_SHIFT_SW_DEFINED_PAGE1_V1 0
+#define BIT_MASK_SW_DEFINED_PAGE1_V1 0xffffffffL
+#define BIT_SW_DEFINED_PAGE1_V1(x)                                             \
+	(((x) & BIT_MASK_SW_DEFINED_PAGE1_V1) << BIT_SHIFT_SW_DEFINED_PAGE1_V1)
+#define BITS_SW_DEFINED_PAGE1_V1                                               \
+	(BIT_MASK_SW_DEFINED_PAGE1_V1 << BIT_SHIFT_SW_DEFINED_PAGE1_V1)
+#define BIT_CLEAR_SW_DEFINED_PAGE1_V1(x) ((x) & (~BITS_SW_DEFINED_PAGE1_V1))
+#define BIT_GET_SW_DEFINED_PAGE1_V1(x)                                         \
+	(((x) >> BIT_SHIFT_SW_DEFINED_PAGE1_V1) & BIT_MASK_SW_DEFINED_PAGE1_V1)
+#define BIT_SET_SW_DEFINED_PAGE1_V1(x, v)                                      \
+	(BIT_CLEAR_SW_DEFINED_PAGE1_V1(x) | BIT_SW_DEFINED_PAGE1_V1(v))
+
+/* 2 REG_SW_DEFINED_PAGE2			(Offset 0x01BC) */
+
+#define BIT_SHIFT_SW_DEFINED_PAGE2 0
+#define BIT_MASK_SW_DEFINED_PAGE2 0xffffffffL
+#define BIT_SW_DEFINED_PAGE2(x)                                                \
+	(((x) & BIT_MASK_SW_DEFINED_PAGE2) << BIT_SHIFT_SW_DEFINED_PAGE2)
+#define BITS_SW_DEFINED_PAGE2                                                  \
+	(BIT_MASK_SW_DEFINED_PAGE2 << BIT_SHIFT_SW_DEFINED_PAGE2)
+#define BIT_CLEAR_SW_DEFINED_PAGE2(x) ((x) & (~BITS_SW_DEFINED_PAGE2))
+#define BIT_GET_SW_DEFINED_PAGE2(x)                                            \
+	(((x) >> BIT_SHIFT_SW_DEFINED_PAGE2) & BIT_MASK_SW_DEFINED_PAGE2)
+#define BIT_SET_SW_DEFINED_PAGE2(x, v)                                         \
+	(BIT_CLEAR_SW_DEFINED_PAGE2(x) | BIT_SW_DEFINED_PAGE2(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_MCUTST_I				(Offset 0x01C0) */
+
+#define BIT_SHIFT_MCUDMSG_I 0
+#define BIT_MASK_MCUDMSG_I 0xffffffffL
+#define BIT_MCUDMSG_I(x) (((x) & BIT_MASK_MCUDMSG_I) << BIT_SHIFT_MCUDMSG_I)
+#define BITS_MCUDMSG_I (BIT_MASK_MCUDMSG_I << BIT_SHIFT_MCUDMSG_I)
+#define BIT_CLEAR_MCUDMSG_I(x) ((x) & (~BITS_MCUDMSG_I))
+#define BIT_GET_MCUDMSG_I(x) (((x) >> BIT_SHIFT_MCUDMSG_I) & BIT_MASK_MCUDMSG_I)
+#define BIT_SET_MCUDMSG_I(x, v) (BIT_CLEAR_MCUDMSG_I(x) | BIT_MCUDMSG_I(v))
+
+/* 2 REG_MCUTST_II				(Offset 0x01C4) */
+
+#define BIT_SHIFT_MCUDMSG_II 0
+#define BIT_MASK_MCUDMSG_II 0xffffffffL
+#define BIT_MCUDMSG_II(x) (((x) & BIT_MASK_MCUDMSG_II) << BIT_SHIFT_MCUDMSG_II)
+#define BITS_MCUDMSG_II (BIT_MASK_MCUDMSG_II << BIT_SHIFT_MCUDMSG_II)
+#define BIT_CLEAR_MCUDMSG_II(x) ((x) & (~BITS_MCUDMSG_II))
+#define BIT_GET_MCUDMSG_II(x)                                                  \
+	(((x) >> BIT_SHIFT_MCUDMSG_II) & BIT_MASK_MCUDMSG_II)
+#define BIT_SET_MCUDMSG_II(x, v) (BIT_CLEAR_MCUDMSG_II(x) | BIT_MCUDMSG_II(v))
+
+/* 2 REG_FMETHR				(Offset 0x01C8) */
+
+#define BIT_FMSG_INT BIT(31)
+
+#define BIT_SHIFT_FW_MSG 0
+#define BIT_MASK_FW_MSG 0xffffffffL
+#define BIT_FW_MSG(x) (((x) & BIT_MASK_FW_MSG) << BIT_SHIFT_FW_MSG)
+#define BITS_FW_MSG (BIT_MASK_FW_MSG << BIT_SHIFT_FW_MSG)
+#define BIT_CLEAR_FW_MSG(x) ((x) & (~BITS_FW_MSG))
+#define BIT_GET_FW_MSG(x) (((x) >> BIT_SHIFT_FW_MSG) & BIT_MASK_FW_MSG)
+#define BIT_SET_FW_MSG(x, v) (BIT_CLEAR_FW_MSG(x) | BIT_FW_MSG(v))
+
+/* 2 REG_HMETFR				(Offset 0x01CC) */
+
+#define BIT_SHIFT_HRCV_MSG 24
+#define BIT_MASK_HRCV_MSG 0xff
+#define BIT_HRCV_MSG(x) (((x) & BIT_MASK_HRCV_MSG) << BIT_SHIFT_HRCV_MSG)
+#define BITS_HRCV_MSG (BIT_MASK_HRCV_MSG << BIT_SHIFT_HRCV_MSG)
+#define BIT_CLEAR_HRCV_MSG(x) ((x) & (~BITS_HRCV_MSG))
+#define BIT_GET_HRCV_MSG(x) (((x) >> BIT_SHIFT_HRCV_MSG) & BIT_MASK_HRCV_MSG)
+#define BIT_SET_HRCV_MSG(x, v) (BIT_CLEAR_HRCV_MSG(x) | BIT_HRCV_MSG(v))
+
+#define BIT_INT_BOX3 BIT(3)
+#define BIT_INT_BOX2 BIT(2)
+#define BIT_INT_BOX1 BIT(1)
+#define BIT_INT_BOX0 BIT(0)
+
+/* 2 REG_HMEBOX0				(Offset 0x01D0) */
+
+#define BIT_SHIFT_HOST_MSG_0 0
+#define BIT_MASK_HOST_MSG_0 0xffffffffL
+#define BIT_HOST_MSG_0(x) (((x) & BIT_MASK_HOST_MSG_0) << BIT_SHIFT_HOST_MSG_0)
+#define BITS_HOST_MSG_0 (BIT_MASK_HOST_MSG_0 << BIT_SHIFT_HOST_MSG_0)
+#define BIT_CLEAR_HOST_MSG_0(x) ((x) & (~BITS_HOST_MSG_0))
+#define BIT_GET_HOST_MSG_0(x)                                                  \
+	(((x) >> BIT_SHIFT_HOST_MSG_0) & BIT_MASK_HOST_MSG_0)
+#define BIT_SET_HOST_MSG_0(x, v) (BIT_CLEAR_HOST_MSG_0(x) | BIT_HOST_MSG_0(v))
+
+/* 2 REG_HMEBOX1				(Offset 0x01D4) */
+
+#define BIT_SHIFT_HOST_MSG_1 0
+#define BIT_MASK_HOST_MSG_1 0xffffffffL
+#define BIT_HOST_MSG_1(x) (((x) & BIT_MASK_HOST_MSG_1) << BIT_SHIFT_HOST_MSG_1)
+#define BITS_HOST_MSG_1 (BIT_MASK_HOST_MSG_1 << BIT_SHIFT_HOST_MSG_1)
+#define BIT_CLEAR_HOST_MSG_1(x) ((x) & (~BITS_HOST_MSG_1))
+#define BIT_GET_HOST_MSG_1(x)                                                  \
+	(((x) >> BIT_SHIFT_HOST_MSG_1) & BIT_MASK_HOST_MSG_1)
+#define BIT_SET_HOST_MSG_1(x, v) (BIT_CLEAR_HOST_MSG_1(x) | BIT_HOST_MSG_1(v))
+
+/* 2 REG_HMEBOX2				(Offset 0x01D8) */
+
+#define BIT_SHIFT_HOST_MSG_2 0
+#define BIT_MASK_HOST_MSG_2 0xffffffffL
+#define BIT_HOST_MSG_2(x) (((x) & BIT_MASK_HOST_MSG_2) << BIT_SHIFT_HOST_MSG_2)
+#define BITS_HOST_MSG_2 (BIT_MASK_HOST_MSG_2 << BIT_SHIFT_HOST_MSG_2)
+#define BIT_CLEAR_HOST_MSG_2(x) ((x) & (~BITS_HOST_MSG_2))
+#define BIT_GET_HOST_MSG_2(x)                                                  \
+	(((x) >> BIT_SHIFT_HOST_MSG_2) & BIT_MASK_HOST_MSG_2)
+#define BIT_SET_HOST_MSG_2(x, v) (BIT_CLEAR_HOST_MSG_2(x) | BIT_HOST_MSG_2(v))
+
+/* 2 REG_HMEBOX3				(Offset 0x01DC) */
+
+#define BIT_SHIFT_HOST_MSG_3 0
+#define BIT_MASK_HOST_MSG_3 0xffffffffL
+#define BIT_HOST_MSG_3(x) (((x) & BIT_MASK_HOST_MSG_3) << BIT_SHIFT_HOST_MSG_3)
+#define BITS_HOST_MSG_3 (BIT_MASK_HOST_MSG_3 << BIT_SHIFT_HOST_MSG_3)
+#define BIT_CLEAR_HOST_MSG_3(x) ((x) & (~BITS_HOST_MSG_3))
+#define BIT_GET_HOST_MSG_3(x)                                                  \
+	(((x) >> BIT_SHIFT_HOST_MSG_3) & BIT_MASK_HOST_MSG_3)
+#define BIT_SET_HOST_MSG_3(x, v) (BIT_CLEAR_HOST_MSG_3(x) | BIT_HOST_MSG_3(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_RXDESC_BUFF_BNDY			(Offset 0x01E0) */
+
+#define BIT_FW_FIFO_PTR_RST BIT(18)
+#define BIT_PHY_FIFO_PTR_RST BIT(17)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT)
+
+/* 2 REG_LLT_INIT				(Offset 0x01E0) */
+
+#define BIT_SHIFT_LLTINI_PDATA_V1 16
+#define BIT_MASK_LLTINI_PDATA_V1 0xfff
+#define BIT_LLTINI_PDATA_V1(x)                                                 \
+	(((x) & BIT_MASK_LLTINI_PDATA_V1) << BIT_SHIFT_LLTINI_PDATA_V1)
+#define BITS_LLTINI_PDATA_V1                                                   \
+	(BIT_MASK_LLTINI_PDATA_V1 << BIT_SHIFT_LLTINI_PDATA_V1)
+#define BIT_CLEAR_LLTINI_PDATA_V1(x) ((x) & (~BITS_LLTINI_PDATA_V1))
+#define BIT_GET_LLTINI_PDATA_V1(x)                                             \
+	(((x) >> BIT_SHIFT_LLTINI_PDATA_V1) & BIT_MASK_LLTINI_PDATA_V1)
+#define BIT_SET_LLTINI_PDATA_V1(x, v)                                          \
+	(BIT_CLEAR_LLTINI_PDATA_V1(x) | BIT_LLTINI_PDATA_V1(v))
+
+#define BIT_SHIFT_LLTINI_HDATA_V1 0
+#define BIT_MASK_LLTINI_HDATA_V1 0xfff
+#define BIT_LLTINI_HDATA_V1(x)                                                 \
+	(((x) & BIT_MASK_LLTINI_HDATA_V1) << BIT_SHIFT_LLTINI_HDATA_V1)
+#define BITS_LLTINI_HDATA_V1                                                   \
+	(BIT_MASK_LLTINI_HDATA_V1 << BIT_SHIFT_LLTINI_HDATA_V1)
+#define BIT_CLEAR_LLTINI_HDATA_V1(x) ((x) & (~BITS_LLTINI_HDATA_V1))
+#define BIT_GET_LLTINI_HDATA_V1(x)                                             \
+	(((x) >> BIT_SHIFT_LLTINI_HDATA_V1) & BIT_MASK_LLTINI_HDATA_V1)
+#define BIT_SET_LLTINI_HDATA_V1(x, v)                                          \
+	(BIT_CLEAR_LLTINI_HDATA_V1(x) | BIT_LLTINI_HDATA_V1(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_RXDESC_BUFF_BNDY			(Offset 0x01E0) */
+
+#define BIT_SHIFT_RXDESC_BUFF_BNDY 0
+#define BIT_MASK_RXDESC_BUFF_BNDY 0xffffffffL
+#define BIT_RXDESC_BUFF_BNDY(x)                                                \
+	(((x) & BIT_MASK_RXDESC_BUFF_BNDY) << BIT_SHIFT_RXDESC_BUFF_BNDY)
+#define BITS_RXDESC_BUFF_BNDY                                                  \
+	(BIT_MASK_RXDESC_BUFF_BNDY << BIT_SHIFT_RXDESC_BUFF_BNDY)
+#define BIT_CLEAR_RXDESC_BUFF_BNDY(x) ((x) & (~BITS_RXDESC_BUFF_BNDY))
+#define BIT_GET_RXDESC_BUFF_BNDY(x)                                            \
+	(((x) >> BIT_SHIFT_RXDESC_BUFF_BNDY) & BIT_MASK_RXDESC_BUFF_BNDY)
+#define BIT_SET_RXDESC_BUFF_BNDY(x, v)                                         \
+	(BIT_CLEAR_RXDESC_BUFF_BNDY(x) | BIT_RXDESC_BUFF_BNDY(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_GENTST				(Offset 0x01E4) */
+
+#define BIT_SHIFT_GENTST 0
+#define BIT_MASK_GENTST 0xffffffffL
+#define BIT_GENTST(x) (((x) & BIT_MASK_GENTST) << BIT_SHIFT_GENTST)
+#define BITS_GENTST (BIT_MASK_GENTST << BIT_SHIFT_GENTST)
+#define BIT_CLEAR_GENTST(x) ((x) & (~BITS_GENTST))
+#define BIT_GET_GENTST(x) (((x) >> BIT_SHIFT_GENTST) & BIT_MASK_GENTST)
+#define BIT_SET_GENTST(x, v) (BIT_CLEAR_GENTST(x) | BIT_GENTST(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT)
+
+/* 2 REG_LLT_INIT_ADDR			(Offset 0x01E4) */
+
+#define BIT_SHIFT_LLTINI_ADDR_V1 0
+#define BIT_MASK_LLTINI_ADDR_V1 0xfff
+#define BIT_LLTINI_ADDR_V1(x)                                                  \
+	(((x) & BIT_MASK_LLTINI_ADDR_V1) << BIT_SHIFT_LLTINI_ADDR_V1)
+#define BITS_LLTINI_ADDR_V1                                                    \
+	(BIT_MASK_LLTINI_ADDR_V1 << BIT_SHIFT_LLTINI_ADDR_V1)
+#define BIT_CLEAR_LLTINI_ADDR_V1(x) ((x) & (~BITS_LLTINI_ADDR_V1))
+#define BIT_GET_LLTINI_ADDR_V1(x)                                              \
+	(((x) >> BIT_SHIFT_LLTINI_ADDR_V1) & BIT_MASK_LLTINI_ADDR_V1)
+#define BIT_SET_LLTINI_ADDR_V1(x, v)                                           \
+	(BIT_CLEAR_LLTINI_ADDR_V1(x) | BIT_LLTINI_ADDR_V1(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_BB_ACCESS_CTRL			(Offset 0x01E8) */
+
+#define BIT_SHIFT_BB_WRITE_READ 30
+#define BIT_MASK_BB_WRITE_READ 0x3
+#define BIT_BB_WRITE_READ(x)                                                   \
+	(((x) & BIT_MASK_BB_WRITE_READ) << BIT_SHIFT_BB_WRITE_READ)
+#define BITS_BB_WRITE_READ (BIT_MASK_BB_WRITE_READ << BIT_SHIFT_BB_WRITE_READ)
+#define BIT_CLEAR_BB_WRITE_READ(x) ((x) & (~BITS_BB_WRITE_READ))
+#define BIT_GET_BB_WRITE_READ(x)                                               \
+	(((x) >> BIT_SHIFT_BB_WRITE_READ) & BIT_MASK_BB_WRITE_READ)
+#define BIT_SET_BB_WRITE_READ(x, v)                                            \
+	(BIT_CLEAR_BB_WRITE_READ(x) | BIT_BB_WRITE_READ(v))
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_BB_ACCESS_CTRL			(Offset 0x01E8) */
+
+#define BIT_SHIFT_BB_WRITE_EN_V1 16
+#define BIT_MASK_BB_WRITE_EN_V1 0xf
+#define BIT_BB_WRITE_EN_V1(x)                                                  \
+	(((x) & BIT_MASK_BB_WRITE_EN_V1) << BIT_SHIFT_BB_WRITE_EN_V1)
+#define BITS_BB_WRITE_EN_V1                                                    \
+	(BIT_MASK_BB_WRITE_EN_V1 << BIT_SHIFT_BB_WRITE_EN_V1)
+#define BIT_CLEAR_BB_WRITE_EN_V1(x) ((x) & (~BITS_BB_WRITE_EN_V1))
+#define BIT_GET_BB_WRITE_EN_V1(x)                                              \
+	(((x) >> BIT_SHIFT_BB_WRITE_EN_V1) & BIT_MASK_BB_WRITE_EN_V1)
+#define BIT_SET_BB_WRITE_EN_V1(x, v)                                           \
+	(BIT_CLEAR_BB_WRITE_EN_V1(x) | BIT_BB_WRITE_EN_V1(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_BB_ACCESS_CTRL			(Offset 0x01E8) */
+
+#define BIT_SHIFT_BB_WRITE_EN 12
+#define BIT_MASK_BB_WRITE_EN 0xf
+#define BIT_BB_WRITE_EN(x)                                                     \
+	(((x) & BIT_MASK_BB_WRITE_EN) << BIT_SHIFT_BB_WRITE_EN)
+#define BITS_BB_WRITE_EN (BIT_MASK_BB_WRITE_EN << BIT_SHIFT_BB_WRITE_EN)
+#define BIT_CLEAR_BB_WRITE_EN(x) ((x) & (~BITS_BB_WRITE_EN))
+#define BIT_GET_BB_WRITE_EN(x)                                                 \
+	(((x) >> BIT_SHIFT_BB_WRITE_EN) & BIT_MASK_BB_WRITE_EN)
+#define BIT_SET_BB_WRITE_EN(x, v)                                              \
+	(BIT_CLEAR_BB_WRITE_EN(x) | BIT_BB_WRITE_EN(v))
+
+#define BIT_SHIFT_BB_ADDR 2
+#define BIT_MASK_BB_ADDR 0x1ff
+#define BIT_BB_ADDR(x) (((x) & BIT_MASK_BB_ADDR) << BIT_SHIFT_BB_ADDR)
+#define BITS_BB_ADDR (BIT_MASK_BB_ADDR << BIT_SHIFT_BB_ADDR)
+#define BIT_CLEAR_BB_ADDR(x) ((x) & (~BITS_BB_ADDR))
+#define BIT_GET_BB_ADDR(x) (((x) >> BIT_SHIFT_BB_ADDR) & BIT_MASK_BB_ADDR)
+#define BIT_SET_BB_ADDR(x, v) (BIT_CLEAR_BB_ADDR(x) | BIT_BB_ADDR(v))
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_BB_ACCESS_CTRL			(Offset 0x01E8) */
+
+#define BIT_SHIFT_BB_ADDR_V1 2
+#define BIT_MASK_BB_ADDR_V1 0xfff
+#define BIT_BB_ADDR_V1(x) (((x) & BIT_MASK_BB_ADDR_V1) << BIT_SHIFT_BB_ADDR_V1)
+#define BITS_BB_ADDR_V1 (BIT_MASK_BB_ADDR_V1 << BIT_SHIFT_BB_ADDR_V1)
+#define BIT_CLEAR_BB_ADDR_V1(x) ((x) & (~BITS_BB_ADDR_V1))
+#define BIT_GET_BB_ADDR_V1(x)                                                  \
+	(((x) >> BIT_SHIFT_BB_ADDR_V1) & BIT_MASK_BB_ADDR_V1)
+#define BIT_SET_BB_ADDR_V1(x, v) (BIT_CLEAR_BB_ADDR_V1(x) | BIT_BB_ADDR_V1(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_BB_ACCESS_CTRL			(Offset 0x01E8) */
+
+#define BIT_BB_ERRACC BIT(0)
+
+/* 2 REG_BB_ACCESS_DATA			(Offset 0x01EC) */
+
+#define BIT_SHIFT_BB_DATA 0
+#define BIT_MASK_BB_DATA 0xffffffffL
+#define BIT_BB_DATA(x) (((x) & BIT_MASK_BB_DATA) << BIT_SHIFT_BB_DATA)
+#define BITS_BB_DATA (BIT_MASK_BB_DATA << BIT_SHIFT_BB_DATA)
+#define BIT_CLEAR_BB_DATA(x) ((x) & (~BITS_BB_DATA))
+#define BIT_GET_BB_DATA(x) (((x) >> BIT_SHIFT_BB_DATA) & BIT_MASK_BB_DATA)
+#define BIT_SET_BB_DATA(x, v) (BIT_CLEAR_BB_DATA(x) | BIT_BB_DATA(v))
+
+/* 2 REG_HMEBOX_E0				(Offset 0x01F0) */
+
+#define BIT_SHIFT_HMEBOX_E0 0
+#define BIT_MASK_HMEBOX_E0 0xffffffffL
+#define BIT_HMEBOX_E0(x) (((x) & BIT_MASK_HMEBOX_E0) << BIT_SHIFT_HMEBOX_E0)
+#define BITS_HMEBOX_E0 (BIT_MASK_HMEBOX_E0 << BIT_SHIFT_HMEBOX_E0)
+#define BIT_CLEAR_HMEBOX_E0(x) ((x) & (~BITS_HMEBOX_E0))
+#define BIT_GET_HMEBOX_E0(x) (((x) >> BIT_SHIFT_HMEBOX_E0) & BIT_MASK_HMEBOX_E0)
+#define BIT_SET_HMEBOX_E0(x, v) (BIT_CLEAR_HMEBOX_E0(x) | BIT_HMEBOX_E0(v))
+
+/* 2 REG_HMEBOX_E1				(Offset 0x01F4) */
+
+#define BIT_SHIFT_HMEBOX_E1 0
+#define BIT_MASK_HMEBOX_E1 0xffffffffL
+#define BIT_HMEBOX_E1(x) (((x) & BIT_MASK_HMEBOX_E1) << BIT_SHIFT_HMEBOX_E1)
+#define BITS_HMEBOX_E1 (BIT_MASK_HMEBOX_E1 << BIT_SHIFT_HMEBOX_E1)
+#define BIT_CLEAR_HMEBOX_E1(x) ((x) & (~BITS_HMEBOX_E1))
+#define BIT_GET_HMEBOX_E1(x) (((x) >> BIT_SHIFT_HMEBOX_E1) & BIT_MASK_HMEBOX_E1)
+#define BIT_SET_HMEBOX_E1(x, v) (BIT_CLEAR_HMEBOX_E1(x) | BIT_HMEBOX_E1(v))
+
+/* 2 REG_HMEBOX_E2				(Offset 0x01F8) */
+
+#define BIT_SHIFT_HMEBOX_E2 0
+#define BIT_MASK_HMEBOX_E2 0xffffffffL
+#define BIT_HMEBOX_E2(x) (((x) & BIT_MASK_HMEBOX_E2) << BIT_SHIFT_HMEBOX_E2)
+#define BITS_HMEBOX_E2 (BIT_MASK_HMEBOX_E2 << BIT_SHIFT_HMEBOX_E2)
+#define BIT_CLEAR_HMEBOX_E2(x) ((x) & (~BITS_HMEBOX_E2))
+#define BIT_GET_HMEBOX_E2(x) (((x) >> BIT_SHIFT_HMEBOX_E2) & BIT_MASK_HMEBOX_E2)
+#define BIT_SET_HMEBOX_E2(x, v) (BIT_CLEAR_HMEBOX_E2(x) | BIT_HMEBOX_E2(v))
+
+/* 2 REG_HMEBOX_E3				(Offset 0x01FC) */
+
+#define BIT_SHIFT_HMEBOX_E3 0
+#define BIT_MASK_HMEBOX_E3 0xffffffffL
+#define BIT_HMEBOX_E3(x) (((x) & BIT_MASK_HMEBOX_E3) << BIT_SHIFT_HMEBOX_E3)
+#define BITS_HMEBOX_E3 (BIT_MASK_HMEBOX_E3 << BIT_SHIFT_HMEBOX_E3)
+#define BIT_CLEAR_HMEBOX_E3(x) ((x) & (~BITS_HMEBOX_E3))
+#define BIT_GET_HMEBOX_E3(x) (((x) >> BIT_SHIFT_HMEBOX_E3) & BIT_MASK_HMEBOX_E3)
+#define BIT_SET_HMEBOX_E3(x, v) (BIT_CLEAR_HMEBOX_E3(x) | BIT_HMEBOX_E3(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_BCN_CTRL_0				(Offset 0x0200) */
+
+#define BIT_BCN1_VALID BIT(31)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_RQPN_CTRL_HLPQ			(Offset 0x0200) */
+
+#define BIT_EP2Q_PUBLIC_DIS BIT(29)
+#define BIT_EP1Q_PUBLIC_DIS BIT(28)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_RQPN_CTRL_HLPQ			(Offset 0x0200) */
+
+#define BIT_EPQ_PUBLIC_DIS BIT(27)
+#define BIT_NPQ_PUBLIC_DIS BIT(26)
+#define BIT_LPQ_PUBLIC_DIS BIT(25)
+#define BIT_HPQ_PUBLIC_DIS BIT(24)
+
+#define BIT_SHIFT_PUBQ 16
+#define BIT_MASK_PUBQ 0xff
+#define BIT_PUBQ(x) (((x) & BIT_MASK_PUBQ) << BIT_SHIFT_PUBQ)
+#define BITS_PUBQ (BIT_MASK_PUBQ << BIT_SHIFT_PUBQ)
+#define BIT_CLEAR_PUBQ(x) ((x) & (~BITS_PUBQ))
+#define BIT_GET_PUBQ(x) (((x) >> BIT_SHIFT_PUBQ) & BIT_MASK_PUBQ)
+#define BIT_SET_PUBQ(x, v) (BIT_CLEAR_PUBQ(x) | BIT_PUBQ(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FIFOPAGE_CTRL_1			(Offset 0x0200) */
+
+#define BIT_SHIFT_TX_OQT_HE_FREE_SPACE_V1 16
+#define BIT_MASK_TX_OQT_HE_FREE_SPACE_V1 0xff
+#define BIT_TX_OQT_HE_FREE_SPACE_V1(x)                                         \
+	(((x) & BIT_MASK_TX_OQT_HE_FREE_SPACE_V1)                              \
+	 << BIT_SHIFT_TX_OQT_HE_FREE_SPACE_V1)
+#define BITS_TX_OQT_HE_FREE_SPACE_V1                                           \
+	(BIT_MASK_TX_OQT_HE_FREE_SPACE_V1 << BIT_SHIFT_TX_OQT_HE_FREE_SPACE_V1)
+#define BIT_CLEAR_TX_OQT_HE_FREE_SPACE_V1(x)                                   \
+	((x) & (~BITS_TX_OQT_HE_FREE_SPACE_V1))
+#define BIT_GET_TX_OQT_HE_FREE_SPACE_V1(x)                                     \
+	(((x) >> BIT_SHIFT_TX_OQT_HE_FREE_SPACE_V1) &                          \
+	 BIT_MASK_TX_OQT_HE_FREE_SPACE_V1)
+#define BIT_SET_TX_OQT_HE_FREE_SPACE_V1(x, v)                                  \
+	(BIT_CLEAR_TX_OQT_HE_FREE_SPACE_V1(x) | BIT_TX_OQT_HE_FREE_SPACE_V1(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_BCN_CTRL_0				(Offset 0x0200) */
+
+#define BIT_SHIFT_BCN1_HEAD 16
+#define BIT_MASK_BCN1_HEAD 0xfff
+#define BIT_BCN1_HEAD(x) (((x) & BIT_MASK_BCN1_HEAD) << BIT_SHIFT_BCN1_HEAD)
+#define BITS_BCN1_HEAD (BIT_MASK_BCN1_HEAD << BIT_SHIFT_BCN1_HEAD)
+#define BIT_CLEAR_BCN1_HEAD(x) ((x) & (~BITS_BCN1_HEAD))
+#define BIT_GET_BCN1_HEAD(x) (((x) >> BIT_SHIFT_BCN1_HEAD) & BIT_MASK_BCN1_HEAD)
+#define BIT_SET_BCN1_HEAD(x, v) (BIT_CLEAR_BCN1_HEAD(x) | BIT_BCN1_HEAD(v))
+
+#define BIT_BCN0_VALID BIT(15)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_RQPN_CTRL_HLPQ			(Offset 0x0200) */
+
+#define BIT_SHIFT_LPQ 8
+#define BIT_MASK_LPQ 0xff
+#define BIT_LPQ(x) (((x) & BIT_MASK_LPQ) << BIT_SHIFT_LPQ)
+#define BITS_LPQ (BIT_MASK_LPQ << BIT_SHIFT_LPQ)
+#define BIT_CLEAR_LPQ(x) ((x) & (~BITS_LPQ))
+#define BIT_GET_LPQ(x) (((x) >> BIT_SHIFT_LPQ) & BIT_MASK_LPQ)
+#define BIT_SET_LPQ(x, v) (BIT_CLEAR_LPQ(x) | BIT_LPQ(v))
+
+#define BIT_SHIFT_HPQ 0
+#define BIT_MASK_HPQ 0xff
+#define BIT_HPQ(x) (((x) & BIT_MASK_HPQ) << BIT_SHIFT_HPQ)
+#define BITS_HPQ (BIT_MASK_HPQ << BIT_SHIFT_HPQ)
+#define BIT_CLEAR_HPQ(x) ((x) & (~BITS_HPQ))
+#define BIT_GET_HPQ(x) (((x) >> BIT_SHIFT_HPQ) & BIT_MASK_HPQ)
+#define BIT_SET_HPQ(x, v) (BIT_CLEAR_HPQ(x) | BIT_HPQ(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FIFOPAGE_CTRL_1			(Offset 0x0200) */
+
+#define BIT_SHIFT_TX_OQT_NL_FREE_SPACE_V1 0
+#define BIT_MASK_TX_OQT_NL_FREE_SPACE_V1 0xff
+#define BIT_TX_OQT_NL_FREE_SPACE_V1(x)                                         \
+	(((x) & BIT_MASK_TX_OQT_NL_FREE_SPACE_V1)                              \
+	 << BIT_SHIFT_TX_OQT_NL_FREE_SPACE_V1)
+#define BITS_TX_OQT_NL_FREE_SPACE_V1                                           \
+	(BIT_MASK_TX_OQT_NL_FREE_SPACE_V1 << BIT_SHIFT_TX_OQT_NL_FREE_SPACE_V1)
+#define BIT_CLEAR_TX_OQT_NL_FREE_SPACE_V1(x)                                   \
+	((x) & (~BITS_TX_OQT_NL_FREE_SPACE_V1))
+#define BIT_GET_TX_OQT_NL_FREE_SPACE_V1(x)                                     \
+	(((x) >> BIT_SHIFT_TX_OQT_NL_FREE_SPACE_V1) &                          \
+	 BIT_MASK_TX_OQT_NL_FREE_SPACE_V1)
+#define BIT_SET_TX_OQT_NL_FREE_SPACE_V1(x, v)                                  \
+	(BIT_CLEAR_TX_OQT_NL_FREE_SPACE_V1(x) | BIT_TX_OQT_NL_FREE_SPACE_V1(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_BCN_CTRL_0				(Offset 0x0200) */
+
+#define BIT_SHIFT_BCN0_HEAD 0
+#define BIT_MASK_BCN0_HEAD 0xfff
+#define BIT_BCN0_HEAD(x) (((x) & BIT_MASK_BCN0_HEAD) << BIT_SHIFT_BCN0_HEAD)
+#define BITS_BCN0_HEAD (BIT_MASK_BCN0_HEAD << BIT_SHIFT_BCN0_HEAD)
+#define BIT_CLEAR_BCN0_HEAD(x) ((x) & (~BITS_BCN0_HEAD))
+#define BIT_GET_BCN0_HEAD(x) (((x) >> BIT_SHIFT_BCN0_HEAD) & BIT_MASK_BCN0_HEAD)
+#define BIT_SET_BCN0_HEAD(x, v) (BIT_CLEAR_BCN0_HEAD(x) | BIT_BCN0_HEAD(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FIFOPAGE_CTRL_2			(Offset 0x0204) */
+
+#define BIT_BCN_VALID_1_V1 BIT(31)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_BCN_CTRL_1				(Offset 0x0204) */
+
+#define BIT_BCN3_VALID BIT(31)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_FIFOPAGE_INFO			(Offset 0x0204) */
+
+#define BIT_SHIFT_TXPKTNUM 24
+#define BIT_MASK_TXPKTNUM 0xff
+#define BIT_TXPKTNUM(x) (((x) & BIT_MASK_TXPKTNUM) << BIT_SHIFT_TXPKTNUM)
+#define BITS_TXPKTNUM (BIT_MASK_TXPKTNUM << BIT_SHIFT_TXPKTNUM)
+#define BIT_CLEAR_TXPKTNUM(x) ((x) & (~BITS_TXPKTNUM))
+#define BIT_GET_TXPKTNUM(x) (((x) >> BIT_SHIFT_TXPKTNUM) & BIT_MASK_TXPKTNUM)
+#define BIT_SET_TXPKTNUM(x, v) (BIT_CLEAR_TXPKTNUM(x) | BIT_TXPKTNUM(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_BCN_CTRL_1				(Offset 0x0204) */
+
+#define BIT_SHIFT_R_BCN_HEAD_SEL_V1 20
+#define BIT_MASK_R_BCN_HEAD_SEL_V1 0x7
+#define BIT_R_BCN_HEAD_SEL_V1(x)                                               \
+	(((x) & BIT_MASK_R_BCN_HEAD_SEL_V1) << BIT_SHIFT_R_BCN_HEAD_SEL_V1)
+#define BITS_R_BCN_HEAD_SEL_V1                                                 \
+	(BIT_MASK_R_BCN_HEAD_SEL_V1 << BIT_SHIFT_R_BCN_HEAD_SEL_V1)
+#define BIT_CLEAR_R_BCN_HEAD_SEL_V1(x) ((x) & (~BITS_R_BCN_HEAD_SEL_V1))
+#define BIT_GET_R_BCN_HEAD_SEL_V1(x)                                           \
+	(((x) >> BIT_SHIFT_R_BCN_HEAD_SEL_V1) & BIT_MASK_R_BCN_HEAD_SEL_V1)
+#define BIT_SET_R_BCN_HEAD_SEL_V1(x, v)                                        \
+	(BIT_CLEAR_R_BCN_HEAD_SEL_V1(x) | BIT_R_BCN_HEAD_SEL_V1(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_FIFOPAGE_INFO			(Offset 0x0204) */
+
+#define BIT_SHIFT_PUBQ_AVAL_PG 16
+#define BIT_MASK_PUBQ_AVAL_PG 0xff
+#define BIT_PUBQ_AVAL_PG(x)                                                    \
+	(((x) & BIT_MASK_PUBQ_AVAL_PG) << BIT_SHIFT_PUBQ_AVAL_PG)
+#define BITS_PUBQ_AVAL_PG (BIT_MASK_PUBQ_AVAL_PG << BIT_SHIFT_PUBQ_AVAL_PG)
+#define BIT_CLEAR_PUBQ_AVAL_PG(x) ((x) & (~BITS_PUBQ_AVAL_PG))
+#define BIT_GET_PUBQ_AVAL_PG(x)                                                \
+	(((x) >> BIT_SHIFT_PUBQ_AVAL_PG) & BIT_MASK_PUBQ_AVAL_PG)
+#define BIT_SET_PUBQ_AVAL_PG(x, v)                                             \
+	(BIT_CLEAR_PUBQ_AVAL_PG(x) | BIT_PUBQ_AVAL_PG(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FIFOPAGE_CTRL_2			(Offset 0x0204) */
+
+#define BIT_SHIFT_BCN_HEAD_1_V1 16
+#define BIT_MASK_BCN_HEAD_1_V1 0xfff
+#define BIT_BCN_HEAD_1_V1(x)                                                   \
+	(((x) & BIT_MASK_BCN_HEAD_1_V1) << BIT_SHIFT_BCN_HEAD_1_V1)
+#define BITS_BCN_HEAD_1_V1 (BIT_MASK_BCN_HEAD_1_V1 << BIT_SHIFT_BCN_HEAD_1_V1)
+#define BIT_CLEAR_BCN_HEAD_1_V1(x) ((x) & (~BITS_BCN_HEAD_1_V1))
+#define BIT_GET_BCN_HEAD_1_V1(x)                                               \
+	(((x) >> BIT_SHIFT_BCN_HEAD_1_V1) & BIT_MASK_BCN_HEAD_1_V1)
+#define BIT_SET_BCN_HEAD_1_V1(x, v)                                            \
+	(BIT_CLEAR_BCN_HEAD_1_V1(x) | BIT_BCN_HEAD_1_V1(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_BCN_CTRL_1				(Offset 0x0204) */
+
+#define BIT_SHIFT_BCN3_HEAD 16
+#define BIT_MASK_BCN3_HEAD 0xfff
+#define BIT_BCN3_HEAD(x) (((x) & BIT_MASK_BCN3_HEAD) << BIT_SHIFT_BCN3_HEAD)
+#define BITS_BCN3_HEAD (BIT_MASK_BCN3_HEAD << BIT_SHIFT_BCN3_HEAD)
+#define BIT_CLEAR_BCN3_HEAD(x) ((x) & (~BITS_BCN3_HEAD))
+#define BIT_GET_BCN3_HEAD(x) (((x) >> BIT_SHIFT_BCN3_HEAD) & BIT_MASK_BCN3_HEAD)
+#define BIT_SET_BCN3_HEAD(x, v) (BIT_CLEAR_BCN3_HEAD(x) | BIT_BCN3_HEAD(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FIFOPAGE_CTRL_2			(Offset 0x0204) */
+
+#define BIT_BCN_VALID_V1 BIT(15)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_BCN_CTRL_1				(Offset 0x0204) */
+
+#define BIT_BCN2_VALID BIT(15)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_FIFOPAGE_INFO			(Offset 0x0204) */
+
+#define BIT_SHIFT_LPQ_AVAL_PG 8
+#define BIT_MASK_LPQ_AVAL_PG 0xff
+#define BIT_LPQ_AVAL_PG(x)                                                     \
+	(((x) & BIT_MASK_LPQ_AVAL_PG) << BIT_SHIFT_LPQ_AVAL_PG)
+#define BITS_LPQ_AVAL_PG (BIT_MASK_LPQ_AVAL_PG << BIT_SHIFT_LPQ_AVAL_PG)
+#define BIT_CLEAR_LPQ_AVAL_PG(x) ((x) & (~BITS_LPQ_AVAL_PG))
+#define BIT_GET_LPQ_AVAL_PG(x)                                                 \
+	(((x) >> BIT_SHIFT_LPQ_AVAL_PG) & BIT_MASK_LPQ_AVAL_PG)
+#define BIT_SET_LPQ_AVAL_PG(x, v)                                              \
+	(BIT_CLEAR_LPQ_AVAL_PG(x) | BIT_LPQ_AVAL_PG(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_BCN_CTRL_1				(Offset 0x0204) */
+
+#define BIT_TDE_ERROR_STOP BIT(3)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_FIFOPAGE_INFO			(Offset 0x0204) */
+
+#define BIT_SHIFT_HPQ_AVAL_PG 0
+#define BIT_MASK_HPQ_AVAL_PG 0xff
+#define BIT_HPQ_AVAL_PG(x)                                                     \
+	(((x) & BIT_MASK_HPQ_AVAL_PG) << BIT_SHIFT_HPQ_AVAL_PG)
+#define BITS_HPQ_AVAL_PG (BIT_MASK_HPQ_AVAL_PG << BIT_SHIFT_HPQ_AVAL_PG)
+#define BIT_CLEAR_HPQ_AVAL_PG(x) ((x) & (~BITS_HPQ_AVAL_PG))
+#define BIT_GET_HPQ_AVAL_PG(x)                                                 \
+	(((x) >> BIT_SHIFT_HPQ_AVAL_PG) & BIT_MASK_HPQ_AVAL_PG)
+#define BIT_SET_HPQ_AVAL_PG(x, v)                                              \
+	(BIT_CLEAR_HPQ_AVAL_PG(x) | BIT_HPQ_AVAL_PG(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FIFOPAGE_CTRL_2			(Offset 0x0204) */
+
+#define BIT_SHIFT_BCN_HEAD_V1 0
+#define BIT_MASK_BCN_HEAD_V1 0xfff
+#define BIT_BCN_HEAD_V1(x)                                                     \
+	(((x) & BIT_MASK_BCN_HEAD_V1) << BIT_SHIFT_BCN_HEAD_V1)
+#define BITS_BCN_HEAD_V1 (BIT_MASK_BCN_HEAD_V1 << BIT_SHIFT_BCN_HEAD_V1)
+#define BIT_CLEAR_BCN_HEAD_V1(x) ((x) & (~BITS_BCN_HEAD_V1))
+#define BIT_GET_BCN_HEAD_V1(x)                                                 \
+	(((x) >> BIT_SHIFT_BCN_HEAD_V1) & BIT_MASK_BCN_HEAD_V1)
+#define BIT_SET_BCN_HEAD_V1(x, v)                                              \
+	(BIT_CLEAR_BCN_HEAD_V1(x) | BIT_BCN_HEAD_V1(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_BCN_CTRL_1				(Offset 0x0204) */
+
+#define BIT_SHIFT_BCN2_HEAD 0
+#define BIT_MASK_BCN2_HEAD 0xfff
+#define BIT_BCN2_HEAD(x) (((x) & BIT_MASK_BCN2_HEAD) << BIT_SHIFT_BCN2_HEAD)
+#define BITS_BCN2_HEAD (BIT_MASK_BCN2_HEAD << BIT_SHIFT_BCN2_HEAD)
+#define BIT_CLEAR_BCN2_HEAD(x) ((x) & (~BITS_BCN2_HEAD))
+#define BIT_GET_BCN2_HEAD(x) (((x) >> BIT_SHIFT_BCN2_HEAD) & BIT_MASK_BCN2_HEAD)
+#define BIT_SET_BCN2_HEAD(x, v) (BIT_CLEAR_BCN2_HEAD(x) | BIT_BCN2_HEAD(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_DWBCN0_CTRL				(Offset 0x0208) */
+
+#define BIT_SHIFT_LLT_FREE_PAGE 24
+#define BIT_MASK_LLT_FREE_PAGE 0xff
+#define BIT_LLT_FREE_PAGE(x)                                                   \
+	(((x) & BIT_MASK_LLT_FREE_PAGE) << BIT_SHIFT_LLT_FREE_PAGE)
+#define BITS_LLT_FREE_PAGE (BIT_MASK_LLT_FREE_PAGE << BIT_SHIFT_LLT_FREE_PAGE)
+#define BIT_CLEAR_LLT_FREE_PAGE(x) ((x) & (~BITS_LLT_FREE_PAGE))
+#define BIT_GET_LLT_FREE_PAGE(x)                                               \
+	(((x) >> BIT_SHIFT_LLT_FREE_PAGE) & BIT_MASK_LLT_FREE_PAGE)
+#define BIT_SET_LLT_FREE_PAGE(x, v)                                            \
+	(BIT_CLEAR_LLT_FREE_PAGE(x) | BIT_LLT_FREE_PAGE(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+
+/* 2 REG_AUTO_LLT_V1				(Offset 0x0208) */
+
+#define BIT_SHIFT_MAX_TX_PKT_FOR_USB_AND_SDIO_V1 24
+#define BIT_MASK_MAX_TX_PKT_FOR_USB_AND_SDIO_V1 0xff
+#define BIT_MAX_TX_PKT_FOR_USB_AND_SDIO_V1(x)                                  \
+	(((x) & BIT_MASK_MAX_TX_PKT_FOR_USB_AND_SDIO_V1)                       \
+	 << BIT_SHIFT_MAX_TX_PKT_FOR_USB_AND_SDIO_V1)
+#define BITS_MAX_TX_PKT_FOR_USB_AND_SDIO_V1                                    \
+	(BIT_MASK_MAX_TX_PKT_FOR_USB_AND_SDIO_V1                               \
+	 << BIT_SHIFT_MAX_TX_PKT_FOR_USB_AND_SDIO_V1)
+#define BIT_CLEAR_MAX_TX_PKT_FOR_USB_AND_SDIO_V1(x)                            \
+	((x) & (~BITS_MAX_TX_PKT_FOR_USB_AND_SDIO_V1))
+#define BIT_GET_MAX_TX_PKT_FOR_USB_AND_SDIO_V1(x)                              \
+	(((x) >> BIT_SHIFT_MAX_TX_PKT_FOR_USB_AND_SDIO_V1) &                   \
+	 BIT_MASK_MAX_TX_PKT_FOR_USB_AND_SDIO_V1)
+#define BIT_SET_MAX_TX_PKT_FOR_USB_AND_SDIO_V1(x, v)                           \
+	(BIT_CLEAR_MAX_TX_PKT_FOR_USB_AND_SDIO_V1(x) |                         \
+	 BIT_MAX_TX_PKT_FOR_USB_AND_SDIO_V1(v))
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_AUTO_LLT_V1				(Offset 0x0208) */
+
+#define BIT_SHIFT_MAX_TX_PKT_V1 24
+#define BIT_MASK_MAX_TX_PKT_V1 0xff
+#define BIT_MAX_TX_PKT_V1(x)                                                   \
+	(((x) & BIT_MASK_MAX_TX_PKT_V1) << BIT_SHIFT_MAX_TX_PKT_V1)
+#define BITS_MAX_TX_PKT_V1 (BIT_MASK_MAX_TX_PKT_V1 << BIT_SHIFT_MAX_TX_PKT_V1)
+#define BIT_CLEAR_MAX_TX_PKT_V1(x) ((x) & (~BITS_MAX_TX_PKT_V1))
+#define BIT_GET_MAX_TX_PKT_V1(x)                                               \
+	(((x) >> BIT_SHIFT_MAX_TX_PKT_V1) & BIT_MASK_MAX_TX_PKT_V1)
+#define BIT_SET_MAX_TX_PKT_V1(x, v)                                            \
+	(BIT_CLEAR_MAX_TX_PKT_V1(x) | BIT_MAX_TX_PKT_V1(v))
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_AUTO_LLT_V1				(Offset 0x0208) */
+
+#define BIT_TDE_ERROR_STOP_V1 BIT(23)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_DWBCN0_CTRL				(Offset 0x0208) */
+
+#define BIT_BCN_VALID BIT(16)
+
+#define BIT_SHIFT_BCN_HEAD 8
+#define BIT_MASK_BCN_HEAD 0xff
+#define BIT_BCN_HEAD(x) (((x) & BIT_MASK_BCN_HEAD) << BIT_SHIFT_BCN_HEAD)
+#define BITS_BCN_HEAD (BIT_MASK_BCN_HEAD << BIT_SHIFT_BCN_HEAD)
+#define BIT_CLEAR_BCN_HEAD(x) ((x) & (~BITS_BCN_HEAD))
+#define BIT_GET_BCN_HEAD(x) (((x) >> BIT_SHIFT_BCN_HEAD) & BIT_MASK_BCN_HEAD)
+#define BIT_SET_BCN_HEAD(x, v) (BIT_CLEAR_BCN_HEAD(x) | BIT_BCN_HEAD(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+
+/* 2 REG_AUTO_LLT_V1				(Offset 0x0208) */
+
+#define BIT_SHIFT_LLT_FREE_PAGE_V1 8
+#define BIT_MASK_LLT_FREE_PAGE_V1 0xffff
+#define BIT_LLT_FREE_PAGE_V1(x)                                                \
+	(((x) & BIT_MASK_LLT_FREE_PAGE_V1) << BIT_SHIFT_LLT_FREE_PAGE_V1)
+#define BITS_LLT_FREE_PAGE_V1                                                  \
+	(BIT_MASK_LLT_FREE_PAGE_V1 << BIT_SHIFT_LLT_FREE_PAGE_V1)
+#define BIT_CLEAR_LLT_FREE_PAGE_V1(x) ((x) & (~BITS_LLT_FREE_PAGE_V1))
+#define BIT_GET_LLT_FREE_PAGE_V1(x)                                            \
+	(((x) >> BIT_SHIFT_LLT_FREE_PAGE_V1) & BIT_MASK_LLT_FREE_PAGE_V1)
+#define BIT_SET_LLT_FREE_PAGE_V1(x, v)                                         \
+	(BIT_CLEAR_LLT_FREE_PAGE_V1(x) | BIT_LLT_FREE_PAGE_V1(v))
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_AUTO_LLT_V1				(Offset 0x0208) */
+
+#define BIT_SHIFT_LLT_FREE_PAGE_V2 8
+#define BIT_MASK_LLT_FREE_PAGE_V2 0xfff
+#define BIT_LLT_FREE_PAGE_V2(x)                                                \
+	(((x) & BIT_MASK_LLT_FREE_PAGE_V2) << BIT_SHIFT_LLT_FREE_PAGE_V2)
+#define BITS_LLT_FREE_PAGE_V2                                                  \
+	(BIT_MASK_LLT_FREE_PAGE_V2 << BIT_SHIFT_LLT_FREE_PAGE_V2)
+#define BIT_CLEAR_LLT_FREE_PAGE_V2(x) ((x) & (~BITS_LLT_FREE_PAGE_V2))
+#define BIT_GET_LLT_FREE_PAGE_V2(x)                                            \
+	(((x) >> BIT_SHIFT_LLT_FREE_PAGE_V2) & BIT_MASK_LLT_FREE_PAGE_V2)
+#define BIT_SET_LLT_FREE_PAGE_V2(x, v)                                         \
+	(BIT_CLEAR_LLT_FREE_PAGE_V2(x) | BIT_LLT_FREE_PAGE_V2(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_AUTO_LLT_V1				(Offset 0x0208) */
+
+#define BIT_SHIFT_BLK_DESC_NUM 4
+#define BIT_MASK_BLK_DESC_NUM 0xf
+#define BIT_BLK_DESC_NUM(x)                                                    \
+	(((x) & BIT_MASK_BLK_DESC_NUM) << BIT_SHIFT_BLK_DESC_NUM)
+#define BITS_BLK_DESC_NUM (BIT_MASK_BLK_DESC_NUM << BIT_SHIFT_BLK_DESC_NUM)
+#define BIT_CLEAR_BLK_DESC_NUM(x) ((x) & (~BITS_BLK_DESC_NUM))
+#define BIT_GET_BLK_DESC_NUM(x)                                                \
+	(((x) >> BIT_SHIFT_BLK_DESC_NUM) & BIT_MASK_BLK_DESC_NUM)
+#define BIT_SET_BLK_DESC_NUM(x, v)                                             \
+	(BIT_CLEAR_BLK_DESC_NUM(x) | BIT_BLK_DESC_NUM(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_AUTO_LLT_V1				(Offset 0x0208) */
+
+#define BIT_R_BCN_HEAD_SEL BIT(3)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_AUTO_LLT_V1				(Offset 0x0208) */
+
+#define BIT_R_EN_BCN_SW_HEAD_SEL BIT(2)
+#define BIT_LLT_DBG_SEL BIT(1)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_DWBCN0_CTRL				(Offset 0x0208) */
+
+#define BIT_BLK_DESC_OPT BIT(0)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_AUTO_LLT_V1				(Offset 0x0208) */
+
+#define BIT_AUTO_INIT_LLT_V1 BIT(0)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_TXDMA_OFFSET_CHK			(Offset 0x020C) */
+
+#define BIT_EM_CHKSUM_FIN BIT(31)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_TXDMA_OFFSET_CHK			(Offset 0x020C) */
+
+#define BIT_EN_CHKSUM_ERR_FIN BIT(31)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_TXDMA_OFFSET_CHK			(Offset 0x020C) */
+
+#define BIT_EMN_PCIE_DMA_MOD BIT(30)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_TXDMA_OFFSET_CHK			(Offset 0x020C) */
+
+#define BIT_EN_PCIE_DMA_MOD BIT(30)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_TXDMA_OFFSET_CHK			(Offset 0x020C) */
+
+#define BIT_EN_TXQUE_CLR BIT(29)
+#define BIT_EN_PCIE_FIFO_MODE BIT(28)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_TXDMA_OFFSET_CHK			(Offset 0x020C) */
+
+#define BIT_SHIFT_PG_UNDER_TH 16
+#define BIT_MASK_PG_UNDER_TH 0xff
+#define BIT_PG_UNDER_TH(x)                                                     \
+	(((x) & BIT_MASK_PG_UNDER_TH) << BIT_SHIFT_PG_UNDER_TH)
+#define BITS_PG_UNDER_TH (BIT_MASK_PG_UNDER_TH << BIT_SHIFT_PG_UNDER_TH)
+#define BIT_CLEAR_PG_UNDER_TH(x) ((x) & (~BITS_PG_UNDER_TH))
+#define BIT_GET_PG_UNDER_TH(x)                                                 \
+	(((x) >> BIT_SHIFT_PG_UNDER_TH) & BIT_MASK_PG_UNDER_TH)
+#define BIT_SET_PG_UNDER_TH(x, v)                                              \
+	(BIT_CLEAR_PG_UNDER_TH(x) | BIT_PG_UNDER_TH(v))
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_TXDMA_OFFSET_CHK			(Offset 0x020C) */
+
+#define BIT_SHIFT_PG_UNDER_TH_V2 16
+#define BIT_MASK_PG_UNDER_TH_V2 0xff
+#define BIT_PG_UNDER_TH_V2(x)                                                  \
+	(((x) & BIT_MASK_PG_UNDER_TH_V2) << BIT_SHIFT_PG_UNDER_TH_V2)
+#define BITS_PG_UNDER_TH_V2                                                    \
+	(BIT_MASK_PG_UNDER_TH_V2 << BIT_SHIFT_PG_UNDER_TH_V2)
+#define BIT_CLEAR_PG_UNDER_TH_V2(x) ((x) & (~BITS_PG_UNDER_TH_V2))
+#define BIT_GET_PG_UNDER_TH_V2(x)                                              \
+	(((x) >> BIT_SHIFT_PG_UNDER_TH_V2) & BIT_MASK_PG_UNDER_TH_V2)
+#define BIT_SET_PG_UNDER_TH_V2(x, v)                                           \
+	(BIT_CLEAR_PG_UNDER_TH_V2(x) | BIT_PG_UNDER_TH_V2(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_TXDMA_OFFSET_CHK			(Offset 0x020C) */
+
+#define BIT_SHIFT_PG_UNDER_TH_V1 16
+#define BIT_MASK_PG_UNDER_TH_V1 0xfff
+#define BIT_PG_UNDER_TH_V1(x)                                                  \
+	(((x) & BIT_MASK_PG_UNDER_TH_V1) << BIT_SHIFT_PG_UNDER_TH_V1)
+#define BITS_PG_UNDER_TH_V1                                                    \
+	(BIT_MASK_PG_UNDER_TH_V1 << BIT_SHIFT_PG_UNDER_TH_V1)
+#define BIT_CLEAR_PG_UNDER_TH_V1(x) ((x) & (~BITS_PG_UNDER_TH_V1))
+#define BIT_GET_PG_UNDER_TH_V1(x)                                              \
+	(((x) >> BIT_SHIFT_PG_UNDER_TH_V1) & BIT_MASK_PG_UNDER_TH_V1)
+#define BIT_SET_PG_UNDER_TH_V1(x, v)                                           \
+	(BIT_CLEAR_PG_UNDER_TH_V1(x) | BIT_PG_UNDER_TH_V1(v))
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_TXDMA_OFFSET_CHK			(Offset 0x020C) */
+
+#define BIT_EN_RESTORE_H2C_BY_RST BIT(15)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT)
+
+/* 2 REG_TXDMA_OFFSET_CHK			(Offset 0x020C) */
+
+#define BIT_EN_RESET_RESTORE_H2C BIT(15)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_TXDMA_OFFSET_CHK			(Offset 0x020C) */
+
+#define BIT_R_EN_RESET_RESTORE_H2C BIT(15)
+
+#endif
+
+#if (HALMAC_8822B_SUPPORT)
+
+/* 2 REG_TXDMA_OFFSET_CHK			(Offset 0x020C) */
+
+#define BIT_RESTORE_H2C_ADDRESS BIT(15)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_TXDMA_OFFSET_CHK			(Offset 0x020C) */
+
+#define BIT_SDIO_TDE_FINISH BIT(14)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_TXDMA_OFFSET_CHK			(Offset 0x020C) */
+
+#define BIT_SDIO_TXDESC_CHKSUM_EN BIT(13)
+#define BIT_RST_RDPTR BIT(12)
+#define BIT_RST_WRPTR BIT(11)
+#define BIT_CHK_PG_TH_EN BIT(10)
+#define BIT_DROP_DATA_EN BIT(9)
+#define BIT_CHECK_OFFSET_EN BIT(8)
+
+#define BIT_SHIFT_CHECK_OFFSET 0
+#define BIT_MASK_CHECK_OFFSET 0xff
+#define BIT_CHECK_OFFSET(x)                                                    \
+	(((x) & BIT_MASK_CHECK_OFFSET) << BIT_SHIFT_CHECK_OFFSET)
+#define BITS_CHECK_OFFSET (BIT_MASK_CHECK_OFFSET << BIT_SHIFT_CHECK_OFFSET)
+#define BIT_CLEAR_CHECK_OFFSET(x) ((x) & (~BITS_CHECK_OFFSET))
+#define BIT_GET_CHECK_OFFSET(x)                                                \
+	(((x) >> BIT_SHIFT_CHECK_OFFSET) & BIT_MASK_CHECK_OFFSET)
+#define BIT_SET_CHECK_OFFSET(x, v)                                             \
+	(BIT_CLEAR_CHECK_OFFSET(x) | BIT_CHECK_OFFSET(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_TXDMA_STATUS			(Offset 0x0210) */
+
+#define BIT_LD_RQPN BIT(31)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_TXDMA_STATUS			(Offset 0x0210) */
+
+#define BIT_AMSDU_PKT_SIZE_ERR BIT(31)
+#define BIT_AMSDU_EN_ERR BIT(30)
+#define BIT_CHKSUM_AMSDU_EN_ERR BIT(29)
+#define BIT_TXPKTBF_REQ_ERR BIT(28)
+#define BIT_OQT_UDN_16 BIT(27)
+#define BIT_OQT_OVF_16 BIT(26)
+#define BIT_OQT_UDN_14_15 BIT(25)
+#define BIT_OQT_OVF_14_15 BIT(24)
+#define BIT_OQT_UDN_13 BIT(23)
+#define BIT_OQT_OVF_13 BIT(22)
+#define BIT_OQT_UDN_12 BIT(21)
+#define BIT_OQT_OVF_12 BIT(20)
+#define BIT_OQT_UDN_8_11 BIT(19)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_TXDMA_STATUS			(Offset 0x0210) */
+
+#define BIT_TXPKTBUF_REQ_ERR BIT(18)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_TXDMA_STATUS			(Offset 0x0210) */
+
+#define BIT_OQT_OVF_8_11 BIT(18)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_TXDMA_STATUS			(Offset 0x0210) */
+
+#define BIT_HI_OQT_UDN BIT(17)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_TXDMA_STATUS			(Offset 0x0210) */
+
+#define BIT_OQT_UDN_4_7 BIT(17)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_TXDMA_STATUS			(Offset 0x0210) */
+
+#define BIT_HI_OQT_OVF BIT(16)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_TXDMA_STATUS			(Offset 0x0210) */
+
+#define BIT_OQT_OVF_4_7 BIT(16)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_TXDMA_STATUS			(Offset 0x0210) */
+
+#define BIT_PAYLOAD_CHKSUM_ERR BIT(15)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_TXDMA_STATUS			(Offset 0x0210) */
+
+#define BIT_RX_CLOSE_EN BIT(15)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_TXDMA_STATUS			(Offset 0x0210) */
+
+#define BIT_PAYLOAD_UDN BIT(14)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_TXDMA_STATUS			(Offset 0x0210) */
+
+#define BIT_STOP_BCNQ BIT(14)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_TXDMA_STATUS			(Offset 0x0210) */
+
+#define BIT_PAYLOAD_OVF BIT(13)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_TXDMA_STATUS			(Offset 0x0210) */
+
+#define BIT_STOP_MGQ BIT(13)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_TXDMA_STATUS			(Offset 0x0210) */
+
+#define BIT_DSC_CHKSUM_FAIL BIT(12)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_TXDMA_STATUS			(Offset 0x0210) */
+
+#define BIT_STOP_VOQ BIT(12)
+#define BIT_UNKNOWN_QSEL BIT(11)
+#define BIT_STOP_VIQ BIT(11)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_TXDMA_STATUS			(Offset 0x0210) */
+
+#define BIT_EP_QSEL_DIFF BIT(10)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_TXDMA_STATUS			(Offset 0x0210) */
+
+#define BIT_STOP_BEQ BIT(10)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_TXDMA_STATUS			(Offset 0x0210) */
+
+#define BIT_TX_OFFS_UNMATCH BIT(9)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_TXDMA_STATUS			(Offset 0x0210) */
+
+#define BIT_STOP_BKQ BIT(9)
+#define BIT_TXOQT_UDN BIT(8)
+#define BIT_STOP_RXQ BIT(8)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_TXDMA_STATUS			(Offset 0x0210) */
+
+#define BIT_TXOQT_UDN_0_3 BIT(8)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_TXDMA_STATUS			(Offset 0x0210) */
+
+#define BIT_TXOQT_OVF BIT(7)
+#define BIT_STOP_HI7Q BIT(7)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_TXDMA_STATUS			(Offset 0x0210) */
+
+#define BIT_TXOQT_OVF_0_3 BIT(7)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_TXDMA_STATUS			(Offset 0x0210) */
+
+#define BIT_TXDMA_SFF_UDN BIT(6)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_TXDMA_STATUS			(Offset 0x0210) */
+
+#define BIT_STOP_HI6Q BIT(6)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_TXDMA_STATUS			(Offset 0x0210) */
+
+#define BIT_TXDMA_SFF_OVF BIT(5)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_TXDMA_STATUS			(Offset 0x0210) */
+
+#define BIT_STOP_HI5Q BIT(5)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_TXDMA_STATUS			(Offset 0x0210) */
+
+#define BIT_LLT_NULL_PG BIT(4)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_TXDMA_STATUS			(Offset 0x0210) */
+
+#define BIT_STOP_HI4Q BIT(4)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_TXDMA_STATUS			(Offset 0x0210) */
+
+#define BIT_PAGE_UDN BIT(3)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_TXDMA_STATUS			(Offset 0x0210) */
+
+#define BIT_STOP_HI3Q BIT(3)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_TXDMA_STATUS			(Offset 0x0210) */
+
+#define BIT_PAGE_OVF BIT(2)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_TXDMA_STATUS			(Offset 0x0210) */
+
+#define BIT_STOP_HI2Q BIT(2)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_TXDMA_STATUS			(Offset 0x0210) */
+
+#define BIT_TXFF_PG_UDN BIT(1)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_TXDMA_STATUS			(Offset 0x0210) */
+
+#define BIT_STOP_HI1Q BIT(1)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_TXDMA_STATUS			(Offset 0x0210) */
+
+#define BIT_TXFF_PG_OVF BIT(0)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_TXDMA_STATUS			(Offset 0x0210) */
+
+#define BIT_STOP_HI0Q BIT(0)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_RQPN_NPQ				(Offset 0x0214) */
+
+#define BIT_SHIFT_EXQ_AVAL_PG 24
+#define BIT_MASK_EXQ_AVAL_PG 0xff
+#define BIT_EXQ_AVAL_PG(x)                                                     \
+	(((x) & BIT_MASK_EXQ_AVAL_PG) << BIT_SHIFT_EXQ_AVAL_PG)
+#define BITS_EXQ_AVAL_PG (BIT_MASK_EXQ_AVAL_PG << BIT_SHIFT_EXQ_AVAL_PG)
+#define BIT_CLEAR_EXQ_AVAL_PG(x) ((x) & (~BITS_EXQ_AVAL_PG))
+#define BIT_GET_EXQ_AVAL_PG(x)                                                 \
+	(((x) >> BIT_SHIFT_EXQ_AVAL_PG) & BIT_MASK_EXQ_AVAL_PG)
+#define BIT_SET_EXQ_AVAL_PG(x, v)                                              \
+	(BIT_CLEAR_EXQ_AVAL_PG(x) | BIT_EXQ_AVAL_PG(v))
+
+#define BIT_SHIFT_EXQ 16
+#define BIT_MASK_EXQ 0xff
+#define BIT_EXQ(x) (((x) & BIT_MASK_EXQ) << BIT_SHIFT_EXQ)
+#define BITS_EXQ (BIT_MASK_EXQ << BIT_SHIFT_EXQ)
+#define BIT_CLEAR_EXQ(x) ((x) & (~BITS_EXQ))
+#define BIT_GET_EXQ(x) (((x) >> BIT_SHIFT_EXQ) & BIT_MASK_EXQ)
+#define BIT_SET_EXQ(x, v) (BIT_CLEAR_EXQ(x) | BIT_EXQ(v))
+
+#define BIT_SHIFT_NPQ 0
+#define BIT_MASK_NPQ 0xff
+#define BIT_NPQ(x) (((x) & BIT_MASK_NPQ) << BIT_SHIFT_NPQ)
+#define BITS_NPQ (BIT_MASK_NPQ << BIT_SHIFT_NPQ)
+#define BIT_CLEAR_NPQ(x) ((x) & (~BITS_NPQ))
+#define BIT_GET_NPQ(x) (((x) >> BIT_SHIFT_NPQ) & BIT_MASK_NPQ)
+#define BIT_SET_NPQ(x, v) (BIT_CLEAR_NPQ(x) | BIT_NPQ(v))
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_TQPNT1				(Offset 0x0218) */
+
+#define BIT_HPQ_INT_EN BIT(31)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_TQPNT1				(Offset 0x0218) */
+
+#define BIT_SHIFT_NPQ_HIGH_TH 24
+#define BIT_MASK_NPQ_HIGH_TH 0xff
+#define BIT_NPQ_HIGH_TH(x)                                                     \
+	(((x) & BIT_MASK_NPQ_HIGH_TH) << BIT_SHIFT_NPQ_HIGH_TH)
+#define BITS_NPQ_HIGH_TH (BIT_MASK_NPQ_HIGH_TH << BIT_SHIFT_NPQ_HIGH_TH)
+#define BIT_CLEAR_NPQ_HIGH_TH(x) ((x) & (~BITS_NPQ_HIGH_TH))
+#define BIT_GET_NPQ_HIGH_TH(x)                                                 \
+	(((x) >> BIT_SHIFT_NPQ_HIGH_TH) & BIT_MASK_NPQ_HIGH_TH)
+#define BIT_SET_NPQ_HIGH_TH(x, v)                                              \
+	(BIT_CLEAR_NPQ_HIGH_TH(x) | BIT_NPQ_HIGH_TH(v))
+
+#define BIT_SHIFT_NPQ_LOW_TH 16
+#define BIT_MASK_NPQ_LOW_TH 0xff
+#define BIT_NPQ_LOW_TH(x) (((x) & BIT_MASK_NPQ_LOW_TH) << BIT_SHIFT_NPQ_LOW_TH)
+#define BITS_NPQ_LOW_TH (BIT_MASK_NPQ_LOW_TH << BIT_SHIFT_NPQ_LOW_TH)
+#define BIT_CLEAR_NPQ_LOW_TH(x) ((x) & (~BITS_NPQ_LOW_TH))
+#define BIT_GET_NPQ_LOW_TH(x)                                                  \
+	(((x) >> BIT_SHIFT_NPQ_LOW_TH) & BIT_MASK_NPQ_LOW_TH)
+#define BIT_SET_NPQ_LOW_TH(x, v) (BIT_CLEAR_NPQ_LOW_TH(x) | BIT_NPQ_LOW_TH(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_TQPNT1				(Offset 0x0218) */
+
+#define BIT_SHIFT_HPQ_HIGH_TH_V1 16
+#define BIT_MASK_HPQ_HIGH_TH_V1 0xfff
+#define BIT_HPQ_HIGH_TH_V1(x)                                                  \
+	(((x) & BIT_MASK_HPQ_HIGH_TH_V1) << BIT_SHIFT_HPQ_HIGH_TH_V1)
+#define BITS_HPQ_HIGH_TH_V1                                                    \
+	(BIT_MASK_HPQ_HIGH_TH_V1 << BIT_SHIFT_HPQ_HIGH_TH_V1)
+#define BIT_CLEAR_HPQ_HIGH_TH_V1(x) ((x) & (~BITS_HPQ_HIGH_TH_V1))
+#define BIT_GET_HPQ_HIGH_TH_V1(x)                                              \
+	(((x) >> BIT_SHIFT_HPQ_HIGH_TH_V1) & BIT_MASK_HPQ_HIGH_TH_V1)
+#define BIT_SET_HPQ_HIGH_TH_V1(x, v)                                           \
+	(BIT_CLEAR_HPQ_HIGH_TH_V1(x) | BIT_HPQ_HIGH_TH_V1(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_DMA_RQPN_INFO_PUB			(Offset 0x0218) */
+
+#define BIT_SHIFT_PUB_AVAL_PG 16
+#define BIT_MASK_PUB_AVAL_PG 0xfff
+#define BIT_PUB_AVAL_PG(x)                                                     \
+	(((x) & BIT_MASK_PUB_AVAL_PG) << BIT_SHIFT_PUB_AVAL_PG)
+#define BITS_PUB_AVAL_PG (BIT_MASK_PUB_AVAL_PG << BIT_SHIFT_PUB_AVAL_PG)
+#define BIT_CLEAR_PUB_AVAL_PG(x) ((x) & (~BITS_PUB_AVAL_PG))
+#define BIT_GET_PUB_AVAL_PG(x)                                                 \
+	(((x) >> BIT_SHIFT_PUB_AVAL_PG) & BIT_MASK_PUB_AVAL_PG)
+#define BIT_SET_PUB_AVAL_PG(x, v)                                              \
+	(BIT_CLEAR_PUB_AVAL_PG(x) | BIT_PUB_AVAL_PG(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_TQPNT1				(Offset 0x0218) */
+
+#define BIT_SHIFT_HPQ_HIGH_TH 8
+#define BIT_MASK_HPQ_HIGH_TH 0xff
+#define BIT_HPQ_HIGH_TH(x)                                                     \
+	(((x) & BIT_MASK_HPQ_HIGH_TH) << BIT_SHIFT_HPQ_HIGH_TH)
+#define BITS_HPQ_HIGH_TH (BIT_MASK_HPQ_HIGH_TH << BIT_SHIFT_HPQ_HIGH_TH)
+#define BIT_CLEAR_HPQ_HIGH_TH(x) ((x) & (~BITS_HPQ_HIGH_TH))
+#define BIT_GET_HPQ_HIGH_TH(x)                                                 \
+	(((x) >> BIT_SHIFT_HPQ_HIGH_TH) & BIT_MASK_HPQ_HIGH_TH)
+#define BIT_SET_HPQ_HIGH_TH(x, v)                                              \
+	(BIT_CLEAR_HPQ_HIGH_TH(x) | BIT_HPQ_HIGH_TH(v))
+
+#define BIT_SHIFT_HPQ_LOW_TH 0
+#define BIT_MASK_HPQ_LOW_TH 0xff
+#define BIT_HPQ_LOW_TH(x) (((x) & BIT_MASK_HPQ_LOW_TH) << BIT_SHIFT_HPQ_LOW_TH)
+#define BITS_HPQ_LOW_TH (BIT_MASK_HPQ_LOW_TH << BIT_SHIFT_HPQ_LOW_TH)
+#define BIT_CLEAR_HPQ_LOW_TH(x) ((x) & (~BITS_HPQ_LOW_TH))
+#define BIT_GET_HPQ_LOW_TH(x)                                                  \
+	(((x) >> BIT_SHIFT_HPQ_LOW_TH) & BIT_MASK_HPQ_LOW_TH)
+#define BIT_SET_HPQ_LOW_TH(x, v) (BIT_CLEAR_HPQ_LOW_TH(x) | BIT_HPQ_LOW_TH(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_TQPNT1				(Offset 0x0218) */
+
+#define BIT_SHIFT_HPQ_LOW_TH_V1 0
+#define BIT_MASK_HPQ_LOW_TH_V1 0xfff
+#define BIT_HPQ_LOW_TH_V1(x)                                                   \
+	(((x) & BIT_MASK_HPQ_LOW_TH_V1) << BIT_SHIFT_HPQ_LOW_TH_V1)
+#define BITS_HPQ_LOW_TH_V1 (BIT_MASK_HPQ_LOW_TH_V1 << BIT_SHIFT_HPQ_LOW_TH_V1)
+#define BIT_CLEAR_HPQ_LOW_TH_V1(x) ((x) & (~BITS_HPQ_LOW_TH_V1))
+#define BIT_GET_HPQ_LOW_TH_V1(x)                                               \
+	(((x) >> BIT_SHIFT_HPQ_LOW_TH_V1) & BIT_MASK_HPQ_LOW_TH_V1)
+#define BIT_SET_HPQ_LOW_TH_V1(x, v)                                            \
+	(BIT_CLEAR_HPQ_LOW_TH_V1(x) | BIT_HPQ_LOW_TH_V1(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_DMA_RQPN_INFO_PUB			(Offset 0x0218) */
+
+#define BIT_SHIFT_PUB_RSVD_PG 0
+#define BIT_MASK_PUB_RSVD_PG 0xfff
+#define BIT_PUB_RSVD_PG(x)                                                     \
+	(((x) & BIT_MASK_PUB_RSVD_PG) << BIT_SHIFT_PUB_RSVD_PG)
+#define BITS_PUB_RSVD_PG (BIT_MASK_PUB_RSVD_PG << BIT_SHIFT_PUB_RSVD_PG)
+#define BIT_CLEAR_PUB_RSVD_PG(x) ((x) & (~BITS_PUB_RSVD_PG))
+#define BIT_GET_PUB_RSVD_PG(x)                                                 \
+	(((x) >> BIT_SHIFT_PUB_RSVD_PG) & BIT_MASK_PUB_RSVD_PG)
+#define BIT_SET_PUB_RSVD_PG(x, v)                                              \
+	(BIT_CLEAR_PUB_RSVD_PG(x) | BIT_PUB_RSVD_PG(v))
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_TQPNT2				(Offset 0x021C) */
+
+#define BIT_NPQ_INT_EN BIT(31)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_RQPN_CTRL_2_V1			(Offset 0x021C) */
+
+#define BIT_LD_RQPN_V1 BIT(31)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_TQPNT2				(Offset 0x021C) */
+
+#define BIT_SHIFT_EXQ_HIGH_TH 24
+#define BIT_MASK_EXQ_HIGH_TH 0xff
+#define BIT_EXQ_HIGH_TH(x)                                                     \
+	(((x) & BIT_MASK_EXQ_HIGH_TH) << BIT_SHIFT_EXQ_HIGH_TH)
+#define BITS_EXQ_HIGH_TH (BIT_MASK_EXQ_HIGH_TH << BIT_SHIFT_EXQ_HIGH_TH)
+#define BIT_CLEAR_EXQ_HIGH_TH(x) ((x) & (~BITS_EXQ_HIGH_TH))
+#define BIT_GET_EXQ_HIGH_TH(x)                                                 \
+	(((x) >> BIT_SHIFT_EXQ_HIGH_TH) & BIT_MASK_EXQ_HIGH_TH)
+#define BIT_SET_EXQ_HIGH_TH(x, v)                                              \
+	(BIT_CLEAR_EXQ_HIGH_TH(x) | BIT_EXQ_HIGH_TH(v))
+
+#define BIT_SHIFT_EXQ_LOW_TH 16
+#define BIT_MASK_EXQ_LOW_TH 0xff
+#define BIT_EXQ_LOW_TH(x) (((x) & BIT_MASK_EXQ_LOW_TH) << BIT_SHIFT_EXQ_LOW_TH)
+#define BITS_EXQ_LOW_TH (BIT_MASK_EXQ_LOW_TH << BIT_SHIFT_EXQ_LOW_TH)
+#define BIT_CLEAR_EXQ_LOW_TH(x) ((x) & (~BITS_EXQ_LOW_TH))
+#define BIT_GET_EXQ_LOW_TH(x)                                                  \
+	(((x) >> BIT_SHIFT_EXQ_LOW_TH) & BIT_MASK_EXQ_LOW_TH)
+#define BIT_SET_EXQ_LOW_TH(x, v) (BIT_CLEAR_EXQ_LOW_TH(x) | BIT_EXQ_LOW_TH(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_TQPNT2				(Offset 0x021C) */
+
+#define BIT_SHIFT_NPQ_HIGH_TH_V1 16
+#define BIT_MASK_NPQ_HIGH_TH_V1 0xfff
+#define BIT_NPQ_HIGH_TH_V1(x)                                                  \
+	(((x) & BIT_MASK_NPQ_HIGH_TH_V1) << BIT_SHIFT_NPQ_HIGH_TH_V1)
+#define BITS_NPQ_HIGH_TH_V1                                                    \
+	(BIT_MASK_NPQ_HIGH_TH_V1 << BIT_SHIFT_NPQ_HIGH_TH_V1)
+#define BIT_CLEAR_NPQ_HIGH_TH_V1(x) ((x) & (~BITS_NPQ_HIGH_TH_V1))
+#define BIT_GET_NPQ_HIGH_TH_V1(x)                                              \
+	(((x) >> BIT_SHIFT_NPQ_HIGH_TH_V1) & BIT_MASK_NPQ_HIGH_TH_V1)
+#define BIT_SET_NPQ_HIGH_TH_V1(x, v)                                           \
+	(BIT_CLEAR_NPQ_HIGH_TH_V1(x) | BIT_NPQ_HIGH_TH_V1(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_RQPN_CTRL_2_V1			(Offset 0x021C) */
+
+#define BIT_CH16_PUBLIC_DIS BIT(16)
+#define BIT_CH15_PUBLIC_DIS BIT(15)
+#define BIT_CH14_PUBLIC_DIS BIT(14)
+#define BIT_CH13_PUBLIC_DIS BIT(13)
+#define BIT_CH12_PUBLIC_DIS BIT(12)
+#define BIT_CH11_PUBLIC_DIS BIT(11)
+#define BIT_CH10_PUBLIC_DIS BIT(10)
+#define BIT_CH9_PUBLIC_DIS BIT(9)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_TQPNT2				(Offset 0x021C) */
+
+#define BIT_SHIFT_LPQ_HIGH_TH 8
+#define BIT_MASK_LPQ_HIGH_TH 0xff
+#define BIT_LPQ_HIGH_TH(x)                                                     \
+	(((x) & BIT_MASK_LPQ_HIGH_TH) << BIT_SHIFT_LPQ_HIGH_TH)
+#define BITS_LPQ_HIGH_TH (BIT_MASK_LPQ_HIGH_TH << BIT_SHIFT_LPQ_HIGH_TH)
+#define BIT_CLEAR_LPQ_HIGH_TH(x) ((x) & (~BITS_LPQ_HIGH_TH))
+#define BIT_GET_LPQ_HIGH_TH(x)                                                 \
+	(((x) >> BIT_SHIFT_LPQ_HIGH_TH) & BIT_MASK_LPQ_HIGH_TH)
+#define BIT_SET_LPQ_HIGH_TH(x, v)                                              \
+	(BIT_CLEAR_LPQ_HIGH_TH(x) | BIT_LPQ_HIGH_TH(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_RQPN_CTRL_2_V1			(Offset 0x021C) */
+
+#define BIT_CH8_PUBLIC_DIS BIT(8)
+#define BIT_CH7_PUBLIC_DIS BIT(7)
+#define BIT_CH6_PUBLIC_DIS BIT(6)
+#define BIT_CH5_PUBLIC_DIS BIT(5)
+#define BIT_CH4_PUBLIC_DIS BIT(4)
+#define BIT_CH3_PUBLIC_DIS BIT(3)
+#define BIT_CH2_PUBLIC_DIS BIT(2)
+#define BIT_CH1_PUBLIC_DIS BIT(1)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_TQPNT2				(Offset 0x021C) */
+
+#define BIT_SHIFT_LPQ_LOW_TH 0
+#define BIT_MASK_LPQ_LOW_TH 0xff
+#define BIT_LPQ_LOW_TH(x) (((x) & BIT_MASK_LPQ_LOW_TH) << BIT_SHIFT_LPQ_LOW_TH)
+#define BITS_LPQ_LOW_TH (BIT_MASK_LPQ_LOW_TH << BIT_SHIFT_LPQ_LOW_TH)
+#define BIT_CLEAR_LPQ_LOW_TH(x) ((x) & (~BITS_LPQ_LOW_TH))
+#define BIT_GET_LPQ_LOW_TH(x)                                                  \
+	(((x) >> BIT_SHIFT_LPQ_LOW_TH) & BIT_MASK_LPQ_LOW_TH)
+#define BIT_SET_LPQ_LOW_TH(x, v) (BIT_CLEAR_LPQ_LOW_TH(x) | BIT_LPQ_LOW_TH(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_TQPNT2				(Offset 0x021C) */
+
+#define BIT_SHIFT_NPQ_LOW_TH_V1 0
+#define BIT_MASK_NPQ_LOW_TH_V1 0xfff
+#define BIT_NPQ_LOW_TH_V1(x)                                                   \
+	(((x) & BIT_MASK_NPQ_LOW_TH_V1) << BIT_SHIFT_NPQ_LOW_TH_V1)
+#define BITS_NPQ_LOW_TH_V1 (BIT_MASK_NPQ_LOW_TH_V1 << BIT_SHIFT_NPQ_LOW_TH_V1)
+#define BIT_CLEAR_NPQ_LOW_TH_V1(x) ((x) & (~BITS_NPQ_LOW_TH_V1))
+#define BIT_GET_NPQ_LOW_TH_V1(x)                                               \
+	(((x) >> BIT_SHIFT_NPQ_LOW_TH_V1) & BIT_MASK_NPQ_LOW_TH_V1)
+#define BIT_SET_NPQ_LOW_TH_V1(x, v)                                            \
+	(BIT_CLEAR_NPQ_LOW_TH_V1(x) | BIT_NPQ_LOW_TH_V1(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_RQPN_CTRL_2_V1			(Offset 0x021C) */
+
+#define BIT_CH0_PUBLIC_DIS BIT(0)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_TQPNT3				(Offset 0x0220) */
+
+#define BIT_LPQ_INT_EN BIT(31)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_BCN_CTRL_2				(Offset 0x0220) */
+
+#define BIT_BCN0_EXT_VALID BIT(31)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_TQPNT3				(Offset 0x0220) */
+
+#define BIT_SHIFT_LPQ_HIGH_TH_V1 16
+#define BIT_MASK_LPQ_HIGH_TH_V1 0xfff
+#define BIT_LPQ_HIGH_TH_V1(x)                                                  \
+	(((x) & BIT_MASK_LPQ_HIGH_TH_V1) << BIT_SHIFT_LPQ_HIGH_TH_V1)
+#define BITS_LPQ_HIGH_TH_V1                                                    \
+	(BIT_MASK_LPQ_HIGH_TH_V1 << BIT_SHIFT_LPQ_HIGH_TH_V1)
+#define BIT_CLEAR_LPQ_HIGH_TH_V1(x) ((x) & (~BITS_LPQ_HIGH_TH_V1))
+#define BIT_GET_LPQ_HIGH_TH_V1(x)                                              \
+	(((x) >> BIT_SHIFT_LPQ_HIGH_TH_V1) & BIT_MASK_LPQ_HIGH_TH_V1)
+#define BIT_SET_LPQ_HIGH_TH_V1(x, v)                                           \
+	(BIT_CLEAR_LPQ_HIGH_TH_V1(x) | BIT_LPQ_HIGH_TH_V1(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_BCN_CTRL_2				(Offset 0x0220) */
+
+#define BIT_SHIFT_BCN0_EXT_HEAD 16
+#define BIT_MASK_BCN0_EXT_HEAD 0xfff
+#define BIT_BCN0_EXT_HEAD(x)                                                   \
+	(((x) & BIT_MASK_BCN0_EXT_HEAD) << BIT_SHIFT_BCN0_EXT_HEAD)
+#define BITS_BCN0_EXT_HEAD (BIT_MASK_BCN0_EXT_HEAD << BIT_SHIFT_BCN0_EXT_HEAD)
+#define BIT_CLEAR_BCN0_EXT_HEAD(x) ((x) & (~BITS_BCN0_EXT_HEAD))
+#define BIT_GET_BCN0_EXT_HEAD(x)                                               \
+	(((x) >> BIT_SHIFT_BCN0_EXT_HEAD) & BIT_MASK_BCN0_EXT_HEAD)
+#define BIT_SET_BCN0_EXT_HEAD(x, v)                                            \
+	(BIT_CLEAR_BCN0_EXT_HEAD(x) | BIT_BCN0_EXT_HEAD(v))
+
+#define BIT_SHIFT_TXPKTNUM_CH4_7 16
+#define BIT_MASK_TXPKTNUM_CH4_7 0xfff
+#define BIT_TXPKTNUM_CH4_7(x)                                                  \
+	(((x) & BIT_MASK_TXPKTNUM_CH4_7) << BIT_SHIFT_TXPKTNUM_CH4_7)
+#define BITS_TXPKTNUM_CH4_7                                                    \
+	(BIT_MASK_TXPKTNUM_CH4_7 << BIT_SHIFT_TXPKTNUM_CH4_7)
+#define BIT_CLEAR_TXPKTNUM_CH4_7(x) ((x) & (~BITS_TXPKTNUM_CH4_7))
+#define BIT_GET_TXPKTNUM_CH4_7(x)                                              \
+	(((x) >> BIT_SHIFT_TXPKTNUM_CH4_7) & BIT_MASK_TXPKTNUM_CH4_7)
+#define BIT_SET_TXPKTNUM_CH4_7(x, v)                                           \
+	(BIT_CLEAR_TXPKTNUM_CH4_7(x) | BIT_TXPKTNUM_CH4_7(v))
+
+#define BIT_SHIFT_TXPKTNUM_CH12 16
+#define BIT_MASK_TXPKTNUM_CH12 0xfff
+#define BIT_TXPKTNUM_CH12(x)                                                   \
+	(((x) & BIT_MASK_TXPKTNUM_CH12) << BIT_SHIFT_TXPKTNUM_CH12)
+#define BITS_TXPKTNUM_CH12 (BIT_MASK_TXPKTNUM_CH12 << BIT_SHIFT_TXPKTNUM_CH12)
+#define BIT_CLEAR_TXPKTNUM_CH12(x) ((x) & (~BITS_TXPKTNUM_CH12))
+#define BIT_GET_TXPKTNUM_CH12(x)                                               \
+	(((x) >> BIT_SHIFT_TXPKTNUM_CH12) & BIT_MASK_TXPKTNUM_CH12)
+#define BIT_SET_TXPKTNUM_CH12(x, v)                                            \
+	(BIT_CLEAR_TXPKTNUM_CH12(x) | BIT_TXPKTNUM_CH12(v))
+
+#define BIT_SHIFT_TXPKTNUM_CH14_15 16
+#define BIT_MASK_TXPKTNUM_CH14_15 0xfff
+#define BIT_TXPKTNUM_CH14_15(x)                                                \
+	(((x) & BIT_MASK_TXPKTNUM_CH14_15) << BIT_SHIFT_TXPKTNUM_CH14_15)
+#define BITS_TXPKTNUM_CH14_15                                                  \
+	(BIT_MASK_TXPKTNUM_CH14_15 << BIT_SHIFT_TXPKTNUM_CH14_15)
+#define BIT_CLEAR_TXPKTNUM_CH14_15(x) ((x) & (~BITS_TXPKTNUM_CH14_15))
+#define BIT_GET_TXPKTNUM_CH14_15(x)                                            \
+	(((x) >> BIT_SHIFT_TXPKTNUM_CH14_15) & BIT_MASK_TXPKTNUM_CH14_15)
+#define BIT_SET_TXPKTNUM_CH14_15(x, v)                                         \
+	(BIT_CLEAR_TXPKTNUM_CH14_15(x) | BIT_TXPKTNUM_CH14_15(v))
+
+#define BIT_BCN4_VALID BIT(15)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_TDE_DEBUG				(Offset 0x0220) */
+
+#define BIT_SHIFT_TDE_DEBUG 0
+#define BIT_MASK_TDE_DEBUG 0xffffffffL
+#define BIT_TDE_DEBUG(x) (((x) & BIT_MASK_TDE_DEBUG) << BIT_SHIFT_TDE_DEBUG)
+#define BITS_TDE_DEBUG (BIT_MASK_TDE_DEBUG << BIT_SHIFT_TDE_DEBUG)
+#define BIT_CLEAR_TDE_DEBUG(x) ((x) & (~BITS_TDE_DEBUG))
+#define BIT_GET_TDE_DEBUG(x) (((x) >> BIT_SHIFT_TDE_DEBUG) & BIT_MASK_TDE_DEBUG)
+#define BIT_SET_TDE_DEBUG(x, v) (BIT_CLEAR_TDE_DEBUG(x) | BIT_TDE_DEBUG(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_TQPNT3				(Offset 0x0220) */
+
+#define BIT_SHIFT_LPQ_LOW_TH_V1 0
+#define BIT_MASK_LPQ_LOW_TH_V1 0xfff
+#define BIT_LPQ_LOW_TH_V1(x)                                                   \
+	(((x) & BIT_MASK_LPQ_LOW_TH_V1) << BIT_SHIFT_LPQ_LOW_TH_V1)
+#define BITS_LPQ_LOW_TH_V1 (BIT_MASK_LPQ_LOW_TH_V1 << BIT_SHIFT_LPQ_LOW_TH_V1)
+#define BIT_CLEAR_LPQ_LOW_TH_V1(x) ((x) & (~BITS_LPQ_LOW_TH_V1))
+#define BIT_GET_LPQ_LOW_TH_V1(x)                                               \
+	(((x) >> BIT_SHIFT_LPQ_LOW_TH_V1) & BIT_MASK_LPQ_LOW_TH_V1)
+#define BIT_SET_LPQ_LOW_TH_V1(x, v)                                            \
+	(BIT_CLEAR_LPQ_LOW_TH_V1(x) | BIT_LPQ_LOW_TH_V1(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_BCN_CTRL_2				(Offset 0x0220) */
+
+#define BIT_SHIFT_BCN4_HEAD 0
+#define BIT_MASK_BCN4_HEAD 0xfff
+#define BIT_BCN4_HEAD(x) (((x) & BIT_MASK_BCN4_HEAD) << BIT_SHIFT_BCN4_HEAD)
+#define BITS_BCN4_HEAD (BIT_MASK_BCN4_HEAD << BIT_SHIFT_BCN4_HEAD)
+#define BIT_CLEAR_BCN4_HEAD(x) ((x) & (~BITS_BCN4_HEAD))
+#define BIT_GET_BCN4_HEAD(x) (((x) >> BIT_SHIFT_BCN4_HEAD) & BIT_MASK_BCN4_HEAD)
+#define BIT_SET_BCN4_HEAD(x, v) (BIT_CLEAR_BCN4_HEAD(x) | BIT_BCN4_HEAD(v))
+
+#define BIT_SHIFT_TXPKTNUM_CH0_3 0
+#define BIT_MASK_TXPKTNUM_CH0_3 0xfff
+#define BIT_TXPKTNUM_CH0_3(x)                                                  \
+	(((x) & BIT_MASK_TXPKTNUM_CH0_3) << BIT_SHIFT_TXPKTNUM_CH0_3)
+#define BITS_TXPKTNUM_CH0_3                                                    \
+	(BIT_MASK_TXPKTNUM_CH0_3 << BIT_SHIFT_TXPKTNUM_CH0_3)
+#define BIT_CLEAR_TXPKTNUM_CH0_3(x) ((x) & (~BITS_TXPKTNUM_CH0_3))
+#define BIT_GET_TXPKTNUM_CH0_3(x)                                              \
+	(((x) >> BIT_SHIFT_TXPKTNUM_CH0_3) & BIT_MASK_TXPKTNUM_CH0_3)
+#define BIT_SET_TXPKTNUM_CH0_3(x, v)                                           \
+	(BIT_CLEAR_TXPKTNUM_CH0_3(x) | BIT_TXPKTNUM_CH0_3(v))
+
+#define BIT_SHIFT_TXPKTNUM_CH8_11 0
+#define BIT_MASK_TXPKTNUM_CH8_11 0xfff
+#define BIT_TXPKTNUM_CH8_11(x)                                                 \
+	(((x) & BIT_MASK_TXPKTNUM_CH8_11) << BIT_SHIFT_TXPKTNUM_CH8_11)
+#define BITS_TXPKTNUM_CH8_11                                                   \
+	(BIT_MASK_TXPKTNUM_CH8_11 << BIT_SHIFT_TXPKTNUM_CH8_11)
+#define BIT_CLEAR_TXPKTNUM_CH8_11(x) ((x) & (~BITS_TXPKTNUM_CH8_11))
+#define BIT_GET_TXPKTNUM_CH8_11(x)                                             \
+	(((x) >> BIT_SHIFT_TXPKTNUM_CH8_11) & BIT_MASK_TXPKTNUM_CH8_11)
+#define BIT_SET_TXPKTNUM_CH8_11(x, v)                                          \
+	(BIT_CLEAR_TXPKTNUM_CH8_11(x) | BIT_TXPKTNUM_CH8_11(v))
+
+#define BIT_SHIFT_TXPKTNUM_CH13 0
+#define BIT_MASK_TXPKTNUM_CH13 0xfff
+#define BIT_TXPKTNUM_CH13(x)                                                   \
+	(((x) & BIT_MASK_TXPKTNUM_CH13) << BIT_SHIFT_TXPKTNUM_CH13)
+#define BITS_TXPKTNUM_CH13 (BIT_MASK_TXPKTNUM_CH13 << BIT_SHIFT_TXPKTNUM_CH13)
+#define BIT_CLEAR_TXPKTNUM_CH13(x) ((x) & (~BITS_TXPKTNUM_CH13))
+#define BIT_GET_TXPKTNUM_CH13(x)                                               \
+	(((x) >> BIT_SHIFT_TXPKTNUM_CH13) & BIT_MASK_TXPKTNUM_CH13)
+#define BIT_SET_TXPKTNUM_CH13(x, v)                                            \
+	(BIT_CLEAR_TXPKTNUM_CH13(x) | BIT_TXPKTNUM_CH13(v))
+
+#define BIT_SHIFT_TXPKTNUM_CH16 0
+#define BIT_MASK_TXPKTNUM_CH16 0xfff
+#define BIT_TXPKTNUM_CH16(x)                                                   \
+	(((x) & BIT_MASK_TXPKTNUM_CH16) << BIT_SHIFT_TXPKTNUM_CH16)
+#define BITS_TXPKTNUM_CH16 (BIT_MASK_TXPKTNUM_CH16 << BIT_SHIFT_TXPKTNUM_CH16)
+#define BIT_CLEAR_TXPKTNUM_CH16(x) ((x) & (~BITS_TXPKTNUM_CH16))
+#define BIT_GET_TXPKTNUM_CH16(x)                                               \
+	(((x) >> BIT_SHIFT_TXPKTNUM_CH16) & BIT_MASK_TXPKTNUM_CH16)
+#define BIT_SET_TXPKTNUM_CH16(x, v)                                            \
+	(BIT_CLEAR_TXPKTNUM_CH16(x) | BIT_TXPKTNUM_CH16(v))
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_TQPNT4				(Offset 0x0224) */
+
+#define BIT_EXQ_INT_EN BIT(31)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_AUTO_LLT				(Offset 0x0224) */
+
+#define BIT_SHIFT_TXPKTNUM_V1 24
+#define BIT_MASK_TXPKTNUM_V1 0xff
+#define BIT_TXPKTNUM_V1(x)                                                     \
+	(((x) & BIT_MASK_TXPKTNUM_V1) << BIT_SHIFT_TXPKTNUM_V1)
+#define BITS_TXPKTNUM_V1 (BIT_MASK_TXPKTNUM_V1 << BIT_SHIFT_TXPKTNUM_V1)
+#define BIT_CLEAR_TXPKTNUM_V1(x) ((x) & (~BITS_TXPKTNUM_V1))
+#define BIT_GET_TXPKTNUM_V1(x)                                                 \
+	(((x) >> BIT_SHIFT_TXPKTNUM_V1) & BIT_MASK_TXPKTNUM_V1)
+#define BIT_SET_TXPKTNUM_V1(x, v)                                              \
+	(BIT_CLEAR_TXPKTNUM_V1(x) | BIT_TXPKTNUM_V1(v))
+
+#define BIT_TDE_DBG_SEL BIT(23)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_AUTO_LLT				(Offset 0x0224) */
+
+#define BIT_MASK_QSEL_DIFF BIT(22)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_AUTO_LLT				(Offset 0x0224) */
+
+#define BIT_AUTO_INIT_LLT BIT(16)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_TQPNT4				(Offset 0x0224) */
+
+#define BIT_SHIFT_EXQ_HIGH_TH_V1 16
+#define BIT_MASK_EXQ_HIGH_TH_V1 0xfff
+#define BIT_EXQ_HIGH_TH_V1(x)                                                  \
+	(((x) & BIT_MASK_EXQ_HIGH_TH_V1) << BIT_SHIFT_EXQ_HIGH_TH_V1)
+#define BITS_EXQ_HIGH_TH_V1                                                    \
+	(BIT_MASK_EXQ_HIGH_TH_V1 << BIT_SHIFT_EXQ_HIGH_TH_V1)
+#define BIT_CLEAR_EXQ_HIGH_TH_V1(x) ((x) & (~BITS_EXQ_HIGH_TH_V1))
+#define BIT_GET_EXQ_HIGH_TH_V1(x)                                              \
+	(((x) >> BIT_SHIFT_EXQ_HIGH_TH_V1) & BIT_MASK_EXQ_HIGH_TH_V1)
+#define BIT_SET_EXQ_HIGH_TH_V1(x, v)                                           \
+	(BIT_CLEAR_EXQ_HIGH_TH_V1(x) | BIT_EXQ_HIGH_TH_V1(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_AUTO_LLT				(Offset 0x0224) */
+
+#define BIT_SHIFT_TX_OQT_HE_FREE_SPACE 8
+#define BIT_MASK_TX_OQT_HE_FREE_SPACE 0xff
+#define BIT_TX_OQT_HE_FREE_SPACE(x)                                            \
+	(((x) & BIT_MASK_TX_OQT_HE_FREE_SPACE)                                 \
+	 << BIT_SHIFT_TX_OQT_HE_FREE_SPACE)
+#define BITS_TX_OQT_HE_FREE_SPACE                                              \
+	(BIT_MASK_TX_OQT_HE_FREE_SPACE << BIT_SHIFT_TX_OQT_HE_FREE_SPACE)
+#define BIT_CLEAR_TX_OQT_HE_FREE_SPACE(x) ((x) & (~BITS_TX_OQT_HE_FREE_SPACE))
+#define BIT_GET_TX_OQT_HE_FREE_SPACE(x)                                        \
+	(((x) >> BIT_SHIFT_TX_OQT_HE_FREE_SPACE) &                             \
+	 BIT_MASK_TX_OQT_HE_FREE_SPACE)
+#define BIT_SET_TX_OQT_HE_FREE_SPACE(x, v)                                     \
+	(BIT_CLEAR_TX_OQT_HE_FREE_SPACE(x) | BIT_TX_OQT_HE_FREE_SPACE(v))
+
+#define BIT_SHIFT_TX_OQT_NL_FREE_SPACE 0
+#define BIT_MASK_TX_OQT_NL_FREE_SPACE 0xff
+#define BIT_TX_OQT_NL_FREE_SPACE(x)                                            \
+	(((x) & BIT_MASK_TX_OQT_NL_FREE_SPACE)                                 \
+	 << BIT_SHIFT_TX_OQT_NL_FREE_SPACE)
+#define BITS_TX_OQT_NL_FREE_SPACE                                              \
+	(BIT_MASK_TX_OQT_NL_FREE_SPACE << BIT_SHIFT_TX_OQT_NL_FREE_SPACE)
+#define BIT_CLEAR_TX_OQT_NL_FREE_SPACE(x) ((x) & (~BITS_TX_OQT_NL_FREE_SPACE))
+#define BIT_GET_TX_OQT_NL_FREE_SPACE(x)                                        \
+	(((x) >> BIT_SHIFT_TX_OQT_NL_FREE_SPACE) &                             \
+	 BIT_MASK_TX_OQT_NL_FREE_SPACE)
+#define BIT_SET_TX_OQT_NL_FREE_SPACE(x, v)                                     \
+	(BIT_CLEAR_TX_OQT_NL_FREE_SPACE(x) | BIT_TX_OQT_NL_FREE_SPACE(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_TQPNT4				(Offset 0x0224) */
+
+#define BIT_SHIFT_EXQ_LOW_TH_V1 0
+#define BIT_MASK_EXQ_LOW_TH_V1 0xfff
+#define BIT_EXQ_LOW_TH_V1(x)                                                   \
+	(((x) & BIT_MASK_EXQ_LOW_TH_V1) << BIT_SHIFT_EXQ_LOW_TH_V1)
+#define BITS_EXQ_LOW_TH_V1 (BIT_MASK_EXQ_LOW_TH_V1 << BIT_SHIFT_EXQ_LOW_TH_V1)
+#define BIT_CLEAR_EXQ_LOW_TH_V1(x) ((x) & (~BITS_EXQ_LOW_TH_V1))
+#define BIT_GET_EXQ_LOW_TH_V1(x)                                               \
+	(((x) >> BIT_SHIFT_EXQ_LOW_TH_V1) & BIT_MASK_EXQ_LOW_TH_V1)
+#define BIT_SET_EXQ_LOW_TH_V1(x, v)                                            \
+	(BIT_CLEAR_EXQ_LOW_TH_V1(x) | BIT_EXQ_LOW_TH_V1(v))
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_DWBCN1_CTRL				(Offset 0x0228) */
+
+#define BIT_SHIFT_BCN_HEAD_2 24
+#define BIT_MASK_BCN_HEAD_2 0xff
+#define BIT_BCN_HEAD_2(x) (((x) & BIT_MASK_BCN_HEAD_2) << BIT_SHIFT_BCN_HEAD_2)
+#define BITS_BCN_HEAD_2 (BIT_MASK_BCN_HEAD_2 << BIT_SHIFT_BCN_HEAD_2)
+#define BIT_CLEAR_BCN_HEAD_2(x) ((x) & (~BITS_BCN_HEAD_2))
+#define BIT_GET_BCN_HEAD_2(x)                                                  \
+	(((x) >> BIT_SHIFT_BCN_HEAD_2) & BIT_MASK_BCN_HEAD_2)
+#define BIT_SET_BCN_HEAD_2(x, v) (BIT_CLEAR_BCN_HEAD_2(x) | BIT_BCN_HEAD_2(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_DWBCN1_CTRL				(Offset 0x0228) */
+
+#define BIT_SW_BCN_SEL BIT(20)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_DWBCN1_CTRL				(Offset 0x0228) */
+
+#define BIT_SHIFT_SW_BCN_SEL_V1 20
+#define BIT_MASK_SW_BCN_SEL_V1 0x3
+#define BIT_SW_BCN_SEL_V1(x)                                                   \
+	(((x) & BIT_MASK_SW_BCN_SEL_V1) << BIT_SHIFT_SW_BCN_SEL_V1)
+#define BITS_SW_BCN_SEL_V1 (BIT_MASK_SW_BCN_SEL_V1 << BIT_SHIFT_SW_BCN_SEL_V1)
+#define BIT_CLEAR_SW_BCN_SEL_V1(x) ((x) & (~BITS_SW_BCN_SEL_V1))
+#define BIT_GET_SW_BCN_SEL_V1(x)                                               \
+	(((x) >> BIT_SHIFT_SW_BCN_SEL_V1) & BIT_MASK_SW_BCN_SEL_V1)
+#define BIT_SET_SW_BCN_SEL_V1(x, v)                                            \
+	(BIT_CLEAR_SW_BCN_SEL_V1(x) | BIT_SW_BCN_SEL_V1(v))
+
+#define BIT_BCN_VALID_2 BIT(18)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_DWBCN1_CTRL				(Offset 0x0228) */
+
+#define BIT_SW_BCN_SEL_EN BIT(17)
+#define BIT_BCN_VALID_1 BIT(16)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+
+/* 2 REG_RQPN_CTRL_1				(Offset 0x0228) */
+
+#define BIT_SHIFT_TXPKTNUM_H 16
+#define BIT_MASK_TXPKTNUM_H 0xffff
+#define BIT_TXPKTNUM_H(x) (((x) & BIT_MASK_TXPKTNUM_H) << BIT_SHIFT_TXPKTNUM_H)
+#define BITS_TXPKTNUM_H (BIT_MASK_TXPKTNUM_H << BIT_SHIFT_TXPKTNUM_H)
+#define BIT_CLEAR_TXPKTNUM_H(x) ((x) & (~BITS_TXPKTNUM_H))
+#define BIT_GET_TXPKTNUM_H(x)                                                  \
+	(((x) >> BIT_SHIFT_TXPKTNUM_H) & BIT_MASK_TXPKTNUM_H)
+#define BIT_SET_TXPKTNUM_H(x, v) (BIT_CLEAR_TXPKTNUM_H(x) | BIT_TXPKTNUM_H(v))
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_RQPN_CTRL_1				(Offset 0x0228) */
+
+#define BIT_SHIFT_TXPKTNUM_H_V2 16
+#define BIT_MASK_TXPKTNUM_H_V2 0xfff
+#define BIT_TXPKTNUM_H_V2(x)                                                   \
+	(((x) & BIT_MASK_TXPKTNUM_H_V2) << BIT_SHIFT_TXPKTNUM_H_V2)
+#define BITS_TXPKTNUM_H_V2 (BIT_MASK_TXPKTNUM_H_V2 << BIT_SHIFT_TXPKTNUM_H_V2)
+#define BIT_CLEAR_TXPKTNUM_H_V2(x) ((x) & (~BITS_TXPKTNUM_H_V2))
+#define BIT_GET_TXPKTNUM_H_V2(x)                                               \
+	(((x) >> BIT_SHIFT_TXPKTNUM_H_V2) & BIT_MASK_TXPKTNUM_H_V2)
+#define BIT_SET_TXPKTNUM_H_V2(x, v)                                            \
+	(BIT_CLEAR_TXPKTNUM_H_V2(x) | BIT_TXPKTNUM_H_V2(v))
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_DWBCN1_CTRL				(Offset 0x0228) */
+
+#define BIT_ADJUSTABLE_SIZE_EN BIT(15)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_DWBCN1_CTRL				(Offset 0x0228) */
+
+#define BIT_SHIFT_BCN_HEAD_1 8
+#define BIT_MASK_BCN_HEAD_1 0xff
+#define BIT_BCN_HEAD_1(x) (((x) & BIT_MASK_BCN_HEAD_1) << BIT_SHIFT_BCN_HEAD_1)
+#define BITS_BCN_HEAD_1 (BIT_MASK_BCN_HEAD_1 << BIT_SHIFT_BCN_HEAD_1)
+#define BIT_CLEAR_BCN_HEAD_1(x) ((x) & (~BITS_BCN_HEAD_1))
+#define BIT_GET_BCN_HEAD_1(x)                                                  \
+	(((x) >> BIT_SHIFT_BCN_HEAD_1) & BIT_MASK_BCN_HEAD_1)
+#define BIT_SET_BCN_HEAD_1(x, v) (BIT_CLEAR_BCN_HEAD_1(x) | BIT_BCN_HEAD_1(v))
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_RQPN_CTRL_1				(Offset 0x0228) */
+
+#define BIT_RST_PGSUB_CNT BIT(1)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_DWBCN1_CTRL				(Offset 0x0228) */
+
+#define BIT_SHIFT_MAX_TX_PKT_FOR_USB_AND_SDIO 0
+#define BIT_MASK_MAX_TX_PKT_FOR_USB_AND_SDIO 0xff
+#define BIT_MAX_TX_PKT_FOR_USB_AND_SDIO(x)                                     \
+	(((x) & BIT_MASK_MAX_TX_PKT_FOR_USB_AND_SDIO)                          \
+	 << BIT_SHIFT_MAX_TX_PKT_FOR_USB_AND_SDIO)
+#define BITS_MAX_TX_PKT_FOR_USB_AND_SDIO                                       \
+	(BIT_MASK_MAX_TX_PKT_FOR_USB_AND_SDIO                                  \
+	 << BIT_SHIFT_MAX_TX_PKT_FOR_USB_AND_SDIO)
+#define BIT_CLEAR_MAX_TX_PKT_FOR_USB_AND_SDIO(x)                               \
+	((x) & (~BITS_MAX_TX_PKT_FOR_USB_AND_SDIO))
+#define BIT_GET_MAX_TX_PKT_FOR_USB_AND_SDIO(x)                                 \
+	(((x) >> BIT_SHIFT_MAX_TX_PKT_FOR_USB_AND_SDIO) &                      \
+	 BIT_MASK_MAX_TX_PKT_FOR_USB_AND_SDIO)
+#define BIT_SET_MAX_TX_PKT_FOR_USB_AND_SDIO(x, v)                              \
+	(BIT_CLEAR_MAX_TX_PKT_FOR_USB_AND_SDIO(x) |                            \
+	 BIT_MAX_TX_PKT_FOR_USB_AND_SDIO(v))
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_DWBCN1_CTRL				(Offset 0x0228) */
+
+#define BIT_SHIFT_ALIGNMENT_SIZE 0
+#define BIT_MASK_ALIGNMENT_SIZE 0xfff
+#define BIT_ALIGNMENT_SIZE(x)                                                  \
+	(((x) & BIT_MASK_ALIGNMENT_SIZE) << BIT_SHIFT_ALIGNMENT_SIZE)
+#define BITS_ALIGNMENT_SIZE                                                    \
+	(BIT_MASK_ALIGNMENT_SIZE << BIT_SHIFT_ALIGNMENT_SIZE)
+#define BIT_CLEAR_ALIGNMENT_SIZE(x) ((x) & (~BITS_ALIGNMENT_SIZE))
+#define BIT_GET_ALIGNMENT_SIZE(x)                                              \
+	(((x) >> BIT_SHIFT_ALIGNMENT_SIZE) & BIT_MASK_ALIGNMENT_SIZE)
+#define BIT_SET_ALIGNMENT_SIZE(x, v)                                           \
+	(BIT_CLEAR_ALIGNMENT_SIZE(x) | BIT_ALIGNMENT_SIZE(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_RQPN_CTRL_1				(Offset 0x0228) */
+
+#define BIT_SHIFT_TXPKTNUM_H_V1 0
+#define BIT_MASK_TXPKTNUM_H_V1 0xffff
+#define BIT_TXPKTNUM_H_V1(x)                                                   \
+	(((x) & BIT_MASK_TXPKTNUM_H_V1) << BIT_SHIFT_TXPKTNUM_H_V1)
+#define BITS_TXPKTNUM_H_V1 (BIT_MASK_TXPKTNUM_H_V1 << BIT_SHIFT_TXPKTNUM_H_V1)
+#define BIT_CLEAR_TXPKTNUM_H_V1(x) ((x) & (~BITS_TXPKTNUM_H_V1))
+#define BIT_GET_TXPKTNUM_H_V1(x)                                               \
+	(((x) >> BIT_SHIFT_TXPKTNUM_H_V1) & BIT_MASK_TXPKTNUM_H_V1)
+#define BIT_SET_TXPKTNUM_H_V1(x, v)                                            \
+	(BIT_CLEAR_TXPKTNUM_H_V1(x) | BIT_TXPKTNUM_H_V1(v))
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_RQPN_CTRL_1				(Offset 0x0228) */
+
+#define BIT_SHIFT_TXPKTNUM_V3 0
+#define BIT_MASK_TXPKTNUM_V3 0xfff
+#define BIT_TXPKTNUM_V3(x)                                                     \
+	(((x) & BIT_MASK_TXPKTNUM_V3) << BIT_SHIFT_TXPKTNUM_V3)
+#define BITS_TXPKTNUM_V3 (BIT_MASK_TXPKTNUM_V3 << BIT_SHIFT_TXPKTNUM_V3)
+#define BIT_CLEAR_TXPKTNUM_V3(x) ((x) & (~BITS_TXPKTNUM_V3))
+#define BIT_GET_TXPKTNUM_V3(x)                                                 \
+	(((x) >> BIT_SHIFT_TXPKTNUM_V3) & BIT_MASK_TXPKTNUM_V3)
+#define BIT_SET_TXPKTNUM_V3(x, v)                                              \
+	(BIT_CLEAR_TXPKTNUM_V3(x) | BIT_TXPKTNUM_V3(v))
+
+#define BIT_PGSUB_CNT_EN BIT(0)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT)
+
+/* 2 REG_RQPN_CTRL_1				(Offset 0x0228) */
+
+#define BIT_SHIFT_TXPKTNUM_V2 0
+#define BIT_MASK_TXPKTNUM_V2 0xffff
+#define BIT_TXPKTNUM_V2(x)                                                     \
+	(((x) & BIT_MASK_TXPKTNUM_V2) << BIT_SHIFT_TXPKTNUM_V2)
+#define BITS_TXPKTNUM_V2 (BIT_MASK_TXPKTNUM_V2 << BIT_SHIFT_TXPKTNUM_V2)
+#define BIT_CLEAR_TXPKTNUM_V2(x) ((x) & (~BITS_TXPKTNUM_V2))
+#define BIT_GET_TXPKTNUM_V2(x)                                                 \
+	(((x) >> BIT_SHIFT_TXPKTNUM_V2) & BIT_MASK_TXPKTNUM_V2)
+#define BIT_SET_TXPKTNUM_V2(x, v)                                              \
+	(BIT_CLEAR_TXPKTNUM_V2(x) | BIT_TXPKTNUM_V2(v))
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+/* 2 REG_RQPN_CTRL_2				(Offset 0x022C) */
+
+#define BIT_EX2Q_PUBLIC_DIS_V1 BIT(21)
+#define BIT_EX1Q_PUBLIC_DIS_V1 BIT(20)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_RQPN_CTRL_2				(Offset 0x022C) */
+
+#define BIT_EXQ_PUBLIC_DIS_V1 BIT(19)
+#define BIT_NPQ_PUBLIC_DIS_V1 BIT(18)
+#define BIT_LPQ_PUBLIC_DIS_V1 BIT(17)
+#define BIT_HPQ_PUBLIC_DIS_V1 BIT(16)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_RQPN_CTRL_2				(Offset 0x022C) */
+
+#define BIT_SDIO_TXAGG_ALIGN_ADJUST_EN BIT(15)
+
+#define BIT_SHIFT_SDIO_TXAGG_ALIGN_SIZE 0
+#define BIT_MASK_SDIO_TXAGG_ALIGN_SIZE 0xfff
+#define BIT_SDIO_TXAGG_ALIGN_SIZE(x)                                           \
+	(((x) & BIT_MASK_SDIO_TXAGG_ALIGN_SIZE)                                \
+	 << BIT_SHIFT_SDIO_TXAGG_ALIGN_SIZE)
+#define BITS_SDIO_TXAGG_ALIGN_SIZE                                             \
+	(BIT_MASK_SDIO_TXAGG_ALIGN_SIZE << BIT_SHIFT_SDIO_TXAGG_ALIGN_SIZE)
+#define BIT_CLEAR_SDIO_TXAGG_ALIGN_SIZE(x) ((x) & (~BITS_SDIO_TXAGG_ALIGN_SIZE))
+#define BIT_GET_SDIO_TXAGG_ALIGN_SIZE(x)                                       \
+	(((x) >> BIT_SHIFT_SDIO_TXAGG_ALIGN_SIZE) &                            \
+	 BIT_MASK_SDIO_TXAGG_ALIGN_SIZE)
+#define BIT_SET_SDIO_TXAGG_ALIGN_SIZE(x, v)                                    \
+	(BIT_CLEAR_SDIO_TXAGG_ALIGN_SIZE(x) | BIT_SDIO_TXAGG_ALIGN_SIZE(v))
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_RQPN_EXQ1_EXQ2			(Offset 0x0230) */
+
+#define BIT_SHIFT_EXQ2_AVAL_PG 24
+#define BIT_MASK_EXQ2_AVAL_PG 0xff
+#define BIT_EXQ2_AVAL_PG(x)                                                    \
+	(((x) & BIT_MASK_EXQ2_AVAL_PG) << BIT_SHIFT_EXQ2_AVAL_PG)
+#define BITS_EXQ2_AVAL_PG (BIT_MASK_EXQ2_AVAL_PG << BIT_SHIFT_EXQ2_AVAL_PG)
+#define BIT_CLEAR_EXQ2_AVAL_PG(x) ((x) & (~BITS_EXQ2_AVAL_PG))
+#define BIT_GET_EXQ2_AVAL_PG(x)                                                \
+	(((x) >> BIT_SHIFT_EXQ2_AVAL_PG) & BIT_MASK_EXQ2_AVAL_PG)
+#define BIT_SET_EXQ2_AVAL_PG(x, v)                                             \
+	(BIT_CLEAR_EXQ2_AVAL_PG(x) | BIT_EXQ2_AVAL_PG(v))
+
+#define BIT_SHIFT_EXQ2 16
+#define BIT_MASK_EXQ2 0xff
+#define BIT_EXQ2(x) (((x) & BIT_MASK_EXQ2) << BIT_SHIFT_EXQ2)
+#define BITS_EXQ2 (BIT_MASK_EXQ2 << BIT_SHIFT_EXQ2)
+#define BIT_CLEAR_EXQ2(x) ((x) & (~BITS_EXQ2))
+#define BIT_GET_EXQ2(x) (((x) >> BIT_SHIFT_EXQ2) & BIT_MASK_EXQ2)
+#define BIT_SET_EXQ2(x, v) (BIT_CLEAR_EXQ2(x) | BIT_EXQ2(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FIFOPAGE_INFO_1			(Offset 0x0230) */
+
+#define BIT_SHIFT_HPQ_AVAL_PG_V1 16
+#define BIT_MASK_HPQ_AVAL_PG_V1 0xfff
+#define BIT_HPQ_AVAL_PG_V1(x)                                                  \
+	(((x) & BIT_MASK_HPQ_AVAL_PG_V1) << BIT_SHIFT_HPQ_AVAL_PG_V1)
+#define BITS_HPQ_AVAL_PG_V1                                                    \
+	(BIT_MASK_HPQ_AVAL_PG_V1 << BIT_SHIFT_HPQ_AVAL_PG_V1)
+#define BIT_CLEAR_HPQ_AVAL_PG_V1(x) ((x) & (~BITS_HPQ_AVAL_PG_V1))
+#define BIT_GET_HPQ_AVAL_PG_V1(x)                                              \
+	(((x) >> BIT_SHIFT_HPQ_AVAL_PG_V1) & BIT_MASK_HPQ_AVAL_PG_V1)
+#define BIT_SET_HPQ_AVAL_PG_V1(x, v)                                           \
+	(BIT_CLEAR_HPQ_AVAL_PG_V1(x) | BIT_HPQ_AVAL_PG_V1(v))
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_RQPN_EXQ1_EXQ2			(Offset 0x0230) */
+
+#define BIT_SHIFT_EXQ1_AVAL_PG 8
+#define BIT_MASK_EXQ1_AVAL_PG 0xff
+#define BIT_EXQ1_AVAL_PG(x)                                                    \
+	(((x) & BIT_MASK_EXQ1_AVAL_PG) << BIT_SHIFT_EXQ1_AVAL_PG)
+#define BITS_EXQ1_AVAL_PG (BIT_MASK_EXQ1_AVAL_PG << BIT_SHIFT_EXQ1_AVAL_PG)
+#define BIT_CLEAR_EXQ1_AVAL_PG(x) ((x) & (~BITS_EXQ1_AVAL_PG))
+#define BIT_GET_EXQ1_AVAL_PG(x)                                                \
+	(((x) >> BIT_SHIFT_EXQ1_AVAL_PG) & BIT_MASK_EXQ1_AVAL_PG)
+#define BIT_SET_EXQ1_AVAL_PG(x, v)                                             \
+	(BIT_CLEAR_EXQ1_AVAL_PG(x) | BIT_EXQ1_AVAL_PG(v))
+
+#define BIT_SHIFT_EXQ1 0
+#define BIT_MASK_EXQ1 0xff
+#define BIT_EXQ1(x) (((x) & BIT_MASK_EXQ1) << BIT_SHIFT_EXQ1)
+#define BITS_EXQ1 (BIT_MASK_EXQ1 << BIT_SHIFT_EXQ1)
+#define BIT_CLEAR_EXQ1(x) ((x) & (~BITS_EXQ1))
+#define BIT_GET_EXQ1(x) (((x) >> BIT_SHIFT_EXQ1) & BIT_MASK_EXQ1)
+#define BIT_SET_EXQ1(x, v) (BIT_CLEAR_EXQ1(x) | BIT_EXQ1(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FIFOPAGE_INFO_1			(Offset 0x0230) */
+
+#define BIT_SHIFT_HPQ_V1 0
+#define BIT_MASK_HPQ_V1 0xfff
+#define BIT_HPQ_V1(x) (((x) & BIT_MASK_HPQ_V1) << BIT_SHIFT_HPQ_V1)
+#define BITS_HPQ_V1 (BIT_MASK_HPQ_V1 << BIT_SHIFT_HPQ_V1)
+#define BIT_CLEAR_HPQ_V1(x) ((x) & (~BITS_HPQ_V1))
+#define BIT_GET_HPQ_V1(x) (((x) >> BIT_SHIFT_HPQ_V1) & BIT_MASK_HPQ_V1)
+#define BIT_SET_HPQ_V1(x, v) (BIT_CLEAR_HPQ_V1(x) | BIT_HPQ_V1(v))
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_TQPNT3_V1				(Offset 0x0234) */
+
+#define BIT_SHIFT_EXQ2_HIGH_TH 24
+#define BIT_MASK_EXQ2_HIGH_TH 0xff
+#define BIT_EXQ2_HIGH_TH(x)                                                    \
+	(((x) & BIT_MASK_EXQ2_HIGH_TH) << BIT_SHIFT_EXQ2_HIGH_TH)
+#define BITS_EXQ2_HIGH_TH (BIT_MASK_EXQ2_HIGH_TH << BIT_SHIFT_EXQ2_HIGH_TH)
+#define BIT_CLEAR_EXQ2_HIGH_TH(x) ((x) & (~BITS_EXQ2_HIGH_TH))
+#define BIT_GET_EXQ2_HIGH_TH(x)                                                \
+	(((x) >> BIT_SHIFT_EXQ2_HIGH_TH) & BIT_MASK_EXQ2_HIGH_TH)
+#define BIT_SET_EXQ2_HIGH_TH(x, v)                                             \
+	(BIT_CLEAR_EXQ2_HIGH_TH(x) | BIT_EXQ2_HIGH_TH(v))
+
+#define BIT_SHIFT_EXQ2_LOW_TH 16
+#define BIT_MASK_EXQ2_LOW_TH 0xff
+#define BIT_EXQ2_LOW_TH(x)                                                     \
+	(((x) & BIT_MASK_EXQ2_LOW_TH) << BIT_SHIFT_EXQ2_LOW_TH)
+#define BITS_EXQ2_LOW_TH (BIT_MASK_EXQ2_LOW_TH << BIT_SHIFT_EXQ2_LOW_TH)
+#define BIT_CLEAR_EXQ2_LOW_TH(x) ((x) & (~BITS_EXQ2_LOW_TH))
+#define BIT_GET_EXQ2_LOW_TH(x)                                                 \
+	(((x) >> BIT_SHIFT_EXQ2_LOW_TH) & BIT_MASK_EXQ2_LOW_TH)
+#define BIT_SET_EXQ2_LOW_TH(x, v)                                              \
+	(BIT_CLEAR_EXQ2_LOW_TH(x) | BIT_EXQ2_LOW_TH(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FIFOPAGE_INFO_2			(Offset 0x0234) */
+
+#define BIT_SHIFT_LPQ_AVAL_PG_V1 16
+#define BIT_MASK_LPQ_AVAL_PG_V1 0xfff
+#define BIT_LPQ_AVAL_PG_V1(x)                                                  \
+	(((x) & BIT_MASK_LPQ_AVAL_PG_V1) << BIT_SHIFT_LPQ_AVAL_PG_V1)
+#define BITS_LPQ_AVAL_PG_V1                                                    \
+	(BIT_MASK_LPQ_AVAL_PG_V1 << BIT_SHIFT_LPQ_AVAL_PG_V1)
+#define BIT_CLEAR_LPQ_AVAL_PG_V1(x) ((x) & (~BITS_LPQ_AVAL_PG_V1))
+#define BIT_GET_LPQ_AVAL_PG_V1(x)                                              \
+	(((x) >> BIT_SHIFT_LPQ_AVAL_PG_V1) & BIT_MASK_LPQ_AVAL_PG_V1)
+#define BIT_SET_LPQ_AVAL_PG_V1(x, v)                                           \
+	(BIT_CLEAR_LPQ_AVAL_PG_V1(x) | BIT_LPQ_AVAL_PG_V1(v))
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_TQPNT3_V1				(Offset 0x0234) */
+
+#define BIT_SHIFT_EXQ1_HIGH_TH 8
+#define BIT_MASK_EXQ1_HIGH_TH 0xff
+#define BIT_EXQ1_HIGH_TH(x)                                                    \
+	(((x) & BIT_MASK_EXQ1_HIGH_TH) << BIT_SHIFT_EXQ1_HIGH_TH)
+#define BITS_EXQ1_HIGH_TH (BIT_MASK_EXQ1_HIGH_TH << BIT_SHIFT_EXQ1_HIGH_TH)
+#define BIT_CLEAR_EXQ1_HIGH_TH(x) ((x) & (~BITS_EXQ1_HIGH_TH))
+#define BIT_GET_EXQ1_HIGH_TH(x)                                                \
+	(((x) >> BIT_SHIFT_EXQ1_HIGH_TH) & BIT_MASK_EXQ1_HIGH_TH)
+#define BIT_SET_EXQ1_HIGH_TH(x, v)                                             \
+	(BIT_CLEAR_EXQ1_HIGH_TH(x) | BIT_EXQ1_HIGH_TH(v))
+
+#define BIT_SHIFT_EXQ1_LOW_TH 0
+#define BIT_MASK_EXQ1_LOW_TH 0xff
+#define BIT_EXQ1_LOW_TH(x)                                                     \
+	(((x) & BIT_MASK_EXQ1_LOW_TH) << BIT_SHIFT_EXQ1_LOW_TH)
+#define BITS_EXQ1_LOW_TH (BIT_MASK_EXQ1_LOW_TH << BIT_SHIFT_EXQ1_LOW_TH)
+#define BIT_CLEAR_EXQ1_LOW_TH(x) ((x) & (~BITS_EXQ1_LOW_TH))
+#define BIT_GET_EXQ1_LOW_TH(x)                                                 \
+	(((x) >> BIT_SHIFT_EXQ1_LOW_TH) & BIT_MASK_EXQ1_LOW_TH)
+#define BIT_SET_EXQ1_LOW_TH(x, v)                                              \
+	(BIT_CLEAR_EXQ1_LOW_TH(x) | BIT_EXQ1_LOW_TH(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FIFOPAGE_INFO_2			(Offset 0x0234) */
+
+#define BIT_SHIFT_LPQ_V1 0
+#define BIT_MASK_LPQ_V1 0xfff
+#define BIT_LPQ_V1(x) (((x) & BIT_MASK_LPQ_V1) << BIT_SHIFT_LPQ_V1)
+#define BITS_LPQ_V1 (BIT_MASK_LPQ_V1 << BIT_SHIFT_LPQ_V1)
+#define BIT_CLEAR_LPQ_V1(x) ((x) & (~BITS_LPQ_V1))
+#define BIT_GET_LPQ_V1(x) (((x) >> BIT_SHIFT_LPQ_V1) & BIT_MASK_LPQ_V1)
+#define BIT_SET_LPQ_V1(x, v) (BIT_CLEAR_LPQ_V1(x) | BIT_LPQ_V1(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FIFOPAGE_INFO_3			(Offset 0x0238) */
+
+#define BIT_SHIFT_NPQ_AVAL_PG_V1 16
+#define BIT_MASK_NPQ_AVAL_PG_V1 0xfff
+#define BIT_NPQ_AVAL_PG_V1(x)                                                  \
+	(((x) & BIT_MASK_NPQ_AVAL_PG_V1) << BIT_SHIFT_NPQ_AVAL_PG_V1)
+#define BITS_NPQ_AVAL_PG_V1                                                    \
+	(BIT_MASK_NPQ_AVAL_PG_V1 << BIT_SHIFT_NPQ_AVAL_PG_V1)
+#define BIT_CLEAR_NPQ_AVAL_PG_V1(x) ((x) & (~BITS_NPQ_AVAL_PG_V1))
+#define BIT_GET_NPQ_AVAL_PG_V1(x)                                              \
+	(((x) >> BIT_SHIFT_NPQ_AVAL_PG_V1) & BIT_MASK_NPQ_AVAL_PG_V1)
+#define BIT_SET_NPQ_AVAL_PG_V1(x, v)                                           \
+	(BIT_CLEAR_NPQ_AVAL_PG_V1(x) | BIT_NPQ_AVAL_PG_V1(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FIFOPAGE_INFO_3			(Offset 0x0238) */
+
+#define BIT_SHIFT_NPQ_V1 0
+#define BIT_MASK_NPQ_V1 0xfff
+#define BIT_NPQ_V1(x) (((x) & BIT_MASK_NPQ_V1) << BIT_SHIFT_NPQ_V1)
+#define BITS_NPQ_V1 (BIT_MASK_NPQ_V1 << BIT_SHIFT_NPQ_V1)
+#define BIT_CLEAR_NPQ_V1(x) ((x) & (~BITS_NPQ_V1))
+#define BIT_GET_NPQ_V1(x) (((x) >> BIT_SHIFT_NPQ_V1) & BIT_MASK_NPQ_V1)
+#define BIT_SET_NPQ_V1(x, v) (BIT_CLEAR_NPQ_V1(x) | BIT_NPQ_V1(v))
+
+/* 2 REG_FIFOPAGE_INFO_4			(Offset 0x023C) */
+
+#define BIT_SHIFT_EXQ_AVAL_PG_V1 16
+#define BIT_MASK_EXQ_AVAL_PG_V1 0xfff
+#define BIT_EXQ_AVAL_PG_V1(x)                                                  \
+	(((x) & BIT_MASK_EXQ_AVAL_PG_V1) << BIT_SHIFT_EXQ_AVAL_PG_V1)
+#define BITS_EXQ_AVAL_PG_V1                                                    \
+	(BIT_MASK_EXQ_AVAL_PG_V1 << BIT_SHIFT_EXQ_AVAL_PG_V1)
+#define BIT_CLEAR_EXQ_AVAL_PG_V1(x) ((x) & (~BITS_EXQ_AVAL_PG_V1))
+#define BIT_GET_EXQ_AVAL_PG_V1(x)                                              \
+	(((x) >> BIT_SHIFT_EXQ_AVAL_PG_V1) & BIT_MASK_EXQ_AVAL_PG_V1)
+#define BIT_SET_EXQ_AVAL_PG_V1(x, v)                                           \
+	(BIT_CLEAR_EXQ_AVAL_PG_V1(x) | BIT_EXQ_AVAL_PG_V1(v))
+
+#define BIT_SHIFT_EXQ_V1 0
+#define BIT_MASK_EXQ_V1 0xfff
+#define BIT_EXQ_V1(x) (((x) & BIT_MASK_EXQ_V1) << BIT_SHIFT_EXQ_V1)
+#define BITS_EXQ_V1 (BIT_MASK_EXQ_V1 << BIT_SHIFT_EXQ_V1)
+#define BIT_CLEAR_EXQ_V1(x) ((x) & (~BITS_EXQ_V1))
+#define BIT_GET_EXQ_V1(x) (((x) >> BIT_SHIFT_EXQ_V1) & BIT_MASK_EXQ_V1)
+#define BIT_SET_EXQ_V1(x, v) (BIT_CLEAR_EXQ_V1(x) | BIT_EXQ_V1(v))
+
+/* 2 REG_FIFOPAGE_INFO_5			(Offset 0x0240) */
+
+#define BIT_SHIFT_PUBQ_AVAL_PG_V1 16
+#define BIT_MASK_PUBQ_AVAL_PG_V1 0xfff
+#define BIT_PUBQ_AVAL_PG_V1(x)                                                 \
+	(((x) & BIT_MASK_PUBQ_AVAL_PG_V1) << BIT_SHIFT_PUBQ_AVAL_PG_V1)
+#define BITS_PUBQ_AVAL_PG_V1                                                   \
+	(BIT_MASK_PUBQ_AVAL_PG_V1 << BIT_SHIFT_PUBQ_AVAL_PG_V1)
+#define BIT_CLEAR_PUBQ_AVAL_PG_V1(x) ((x) & (~BITS_PUBQ_AVAL_PG_V1))
+#define BIT_GET_PUBQ_AVAL_PG_V1(x)                                             \
+	(((x) >> BIT_SHIFT_PUBQ_AVAL_PG_V1) & BIT_MASK_PUBQ_AVAL_PG_V1)
+#define BIT_SET_PUBQ_AVAL_PG_V1(x, v)                                          \
+	(BIT_CLEAR_PUBQ_AVAL_PG_V1(x) | BIT_PUBQ_AVAL_PG_V1(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_TX_AGG_ALIGN			(Offset 0x0240) */
+
+#define BIT_SHIFT_HW_FLOW_CTL_EN 16
+#define BIT_MASK_HW_FLOW_CTL_EN 0xffff
+#define BIT_HW_FLOW_CTL_EN(x)                                                  \
+	(((x) & BIT_MASK_HW_FLOW_CTL_EN) << BIT_SHIFT_HW_FLOW_CTL_EN)
+#define BITS_HW_FLOW_CTL_EN                                                    \
+	(BIT_MASK_HW_FLOW_CTL_EN << BIT_SHIFT_HW_FLOW_CTL_EN)
+#define BIT_CLEAR_HW_FLOW_CTL_EN(x) ((x) & (~BITS_HW_FLOW_CTL_EN))
+#define BIT_GET_HW_FLOW_CTL_EN(x)                                              \
+	(((x) >> BIT_SHIFT_HW_FLOW_CTL_EN) & BIT_MASK_HW_FLOW_CTL_EN)
+#define BIT_SET_HW_FLOW_CTL_EN(x, v)                                           \
+	(BIT_CLEAR_HW_FLOW_CTL_EN(x) | BIT_HW_FLOW_CTL_EN(v))
+
+#define BIT_SDIO_TXAGG_ALIGN_ADJUST_EN_V1 BIT(15)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FIFOPAGE_INFO_5			(Offset 0x0240) */
+
+#define BIT_SHIFT_PUBQ_V1 0
+#define BIT_MASK_PUBQ_V1 0xfff
+#define BIT_PUBQ_V1(x) (((x) & BIT_MASK_PUBQ_V1) << BIT_SHIFT_PUBQ_V1)
+#define BITS_PUBQ_V1 (BIT_MASK_PUBQ_V1 << BIT_SHIFT_PUBQ_V1)
+#define BIT_CLEAR_PUBQ_V1(x) ((x) & (~BITS_PUBQ_V1))
+#define BIT_GET_PUBQ_V1(x) (((x) >> BIT_SHIFT_PUBQ_V1) & BIT_MASK_PUBQ_V1)
+#define BIT_SET_PUBQ_V1(x, v) (BIT_CLEAR_PUBQ_V1(x) | BIT_PUBQ_V1(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_TX_AGG_ALIGN			(Offset 0x0240) */
+
+#define BIT_SHIFT_SDIO_TXAGG_ALIGN_SIZE_V1 0
+#define BIT_MASK_SDIO_TXAGG_ALIGN_SIZE_V1 0xfff
+#define BIT_SDIO_TXAGG_ALIGN_SIZE_V1(x)                                        \
+	(((x) & BIT_MASK_SDIO_TXAGG_ALIGN_SIZE_V1)                             \
+	 << BIT_SHIFT_SDIO_TXAGG_ALIGN_SIZE_V1)
+#define BITS_SDIO_TXAGG_ALIGN_SIZE_V1                                          \
+	(BIT_MASK_SDIO_TXAGG_ALIGN_SIZE_V1                                     \
+	 << BIT_SHIFT_SDIO_TXAGG_ALIGN_SIZE_V1)
+#define BIT_CLEAR_SDIO_TXAGG_ALIGN_SIZE_V1(x)                                  \
+	((x) & (~BITS_SDIO_TXAGG_ALIGN_SIZE_V1))
+#define BIT_GET_SDIO_TXAGG_ALIGN_SIZE_V1(x)                                    \
+	(((x) >> BIT_SHIFT_SDIO_TXAGG_ALIGN_SIZE_V1) &                         \
+	 BIT_MASK_SDIO_TXAGG_ALIGN_SIZE_V1)
+#define BIT_SET_SDIO_TXAGG_ALIGN_SIZE_V1(x, v)                                 \
+	(BIT_CLEAR_SDIO_TXAGG_ALIGN_SIZE_V1(x) |                               \
+	 BIT_SDIO_TXAGG_ALIGN_SIZE_V1(v))
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_H2C_HEAD				(Offset 0x0244) */
+
+#define BIT_SHIFT_H2C_HEAD_V2 0
+#define BIT_MASK_H2C_HEAD_V2 0xffff
+#define BIT_H2C_HEAD_V2(x)                                                     \
+	(((x) & BIT_MASK_H2C_HEAD_V2) << BIT_SHIFT_H2C_HEAD_V2)
+#define BITS_H2C_HEAD_V2 (BIT_MASK_H2C_HEAD_V2 << BIT_SHIFT_H2C_HEAD_V2)
+#define BIT_CLEAR_H2C_HEAD_V2(x) ((x) & (~BITS_H2C_HEAD_V2))
+#define BIT_GET_H2C_HEAD_V2(x)                                                 \
+	(((x) >> BIT_SHIFT_H2C_HEAD_V2) & BIT_MASK_H2C_HEAD_V2)
+#define BIT_SET_H2C_HEAD_V2(x, v)                                              \
+	(BIT_CLEAR_H2C_HEAD_V2(x) | BIT_H2C_HEAD_V2(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_H2C_HEAD				(Offset 0x0244) */
+
+#define BIT_SHIFT_H2C_HEAD 0
+#define BIT_MASK_H2C_HEAD 0x3ffff
+#define BIT_H2C_HEAD(x) (((x) & BIT_MASK_H2C_HEAD) << BIT_SHIFT_H2C_HEAD)
+#define BITS_H2C_HEAD (BIT_MASK_H2C_HEAD << BIT_SHIFT_H2C_HEAD)
+#define BIT_CLEAR_H2C_HEAD(x) ((x) & (~BITS_H2C_HEAD))
+#define BIT_GET_H2C_HEAD(x) (((x) >> BIT_SHIFT_H2C_HEAD) & BIT_MASK_H2C_HEAD)
+#define BIT_SET_H2C_HEAD(x, v) (BIT_CLEAR_H2C_HEAD(x) | BIT_H2C_HEAD(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_H2C_HEAD				(Offset 0x0244) */
+
+#define BIT_SHIFT_H2C_HEAD_V1 0
+#define BIT_MASK_H2C_HEAD_V1 0x7ffff
+#define BIT_H2C_HEAD_V1(x)                                                     \
+	(((x) & BIT_MASK_H2C_HEAD_V1) << BIT_SHIFT_H2C_HEAD_V1)
+#define BITS_H2C_HEAD_V1 (BIT_MASK_H2C_HEAD_V1 << BIT_SHIFT_H2C_HEAD_V1)
+#define BIT_CLEAR_H2C_HEAD_V1(x) ((x) & (~BITS_H2C_HEAD_V1))
+#define BIT_GET_H2C_HEAD_V1(x)                                                 \
+	(((x) >> BIT_SHIFT_H2C_HEAD_V1) & BIT_MASK_H2C_HEAD_V1)
+#define BIT_SET_H2C_HEAD_V1(x, v)                                              \
+	(BIT_CLEAR_H2C_HEAD_V1(x) | BIT_H2C_HEAD_V1(v))
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_H2C_TAIL				(Offset 0x0248) */
+
+#define BIT_SHIFT_H2C_TAIL_V2 0
+#define BIT_MASK_H2C_TAIL_V2 0xffff
+#define BIT_H2C_TAIL_V2(x)                                                     \
+	(((x) & BIT_MASK_H2C_TAIL_V2) << BIT_SHIFT_H2C_TAIL_V2)
+#define BITS_H2C_TAIL_V2 (BIT_MASK_H2C_TAIL_V2 << BIT_SHIFT_H2C_TAIL_V2)
+#define BIT_CLEAR_H2C_TAIL_V2(x) ((x) & (~BITS_H2C_TAIL_V2))
+#define BIT_GET_H2C_TAIL_V2(x)                                                 \
+	(((x) >> BIT_SHIFT_H2C_TAIL_V2) & BIT_MASK_H2C_TAIL_V2)
+#define BIT_SET_H2C_TAIL_V2(x, v)                                              \
+	(BIT_CLEAR_H2C_TAIL_V2(x) | BIT_H2C_TAIL_V2(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_H2C_TAIL				(Offset 0x0248) */
+
+#define BIT_SHIFT_H2C_TAIL 0
+#define BIT_MASK_H2C_TAIL 0x3ffff
+#define BIT_H2C_TAIL(x) (((x) & BIT_MASK_H2C_TAIL) << BIT_SHIFT_H2C_TAIL)
+#define BITS_H2C_TAIL (BIT_MASK_H2C_TAIL << BIT_SHIFT_H2C_TAIL)
+#define BIT_CLEAR_H2C_TAIL(x) ((x) & (~BITS_H2C_TAIL))
+#define BIT_GET_H2C_TAIL(x) (((x) >> BIT_SHIFT_H2C_TAIL) & BIT_MASK_H2C_TAIL)
+#define BIT_SET_H2C_TAIL(x, v) (BIT_CLEAR_H2C_TAIL(x) | BIT_H2C_TAIL(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_H2C_TAIL				(Offset 0x0248) */
+
+#define BIT_SHIFT_H2C_TAIL_V1 0
+#define BIT_MASK_H2C_TAIL_V1 0x7ffff
+#define BIT_H2C_TAIL_V1(x)                                                     \
+	(((x) & BIT_MASK_H2C_TAIL_V1) << BIT_SHIFT_H2C_TAIL_V1)
+#define BITS_H2C_TAIL_V1 (BIT_MASK_H2C_TAIL_V1 << BIT_SHIFT_H2C_TAIL_V1)
+#define BIT_CLEAR_H2C_TAIL_V1(x) ((x) & (~BITS_H2C_TAIL_V1))
+#define BIT_GET_H2C_TAIL_V1(x)                                                 \
+	(((x) >> BIT_SHIFT_H2C_TAIL_V1) & BIT_MASK_H2C_TAIL_V1)
+#define BIT_SET_H2C_TAIL_V1(x, v)                                              \
+	(BIT_CLEAR_H2C_TAIL_V1(x) | BIT_H2C_TAIL_V1(v))
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_H2C_READ_ADDR			(Offset 0x024C) */
+
+#define BIT_SHIFT_H2C_READ_ADDR_V2 0
+#define BIT_MASK_H2C_READ_ADDR_V2 0xffff
+#define BIT_H2C_READ_ADDR_V2(x)                                                \
+	(((x) & BIT_MASK_H2C_READ_ADDR_V2) << BIT_SHIFT_H2C_READ_ADDR_V2)
+#define BITS_H2C_READ_ADDR_V2                                                  \
+	(BIT_MASK_H2C_READ_ADDR_V2 << BIT_SHIFT_H2C_READ_ADDR_V2)
+#define BIT_CLEAR_H2C_READ_ADDR_V2(x) ((x) & (~BITS_H2C_READ_ADDR_V2))
+#define BIT_GET_H2C_READ_ADDR_V2(x)                                            \
+	(((x) >> BIT_SHIFT_H2C_READ_ADDR_V2) & BIT_MASK_H2C_READ_ADDR_V2)
+#define BIT_SET_H2C_READ_ADDR_V2(x, v)                                         \
+	(BIT_CLEAR_H2C_READ_ADDR_V2(x) | BIT_H2C_READ_ADDR_V2(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_H2C_READ_ADDR			(Offset 0x024C) */
+
+#define BIT_SHIFT_H2C_READ_ADDR 0
+#define BIT_MASK_H2C_READ_ADDR 0x3ffff
+#define BIT_H2C_READ_ADDR(x)                                                   \
+	(((x) & BIT_MASK_H2C_READ_ADDR) << BIT_SHIFT_H2C_READ_ADDR)
+#define BITS_H2C_READ_ADDR (BIT_MASK_H2C_READ_ADDR << BIT_SHIFT_H2C_READ_ADDR)
+#define BIT_CLEAR_H2C_READ_ADDR(x) ((x) & (~BITS_H2C_READ_ADDR))
+#define BIT_GET_H2C_READ_ADDR(x)                                               \
+	(((x) >> BIT_SHIFT_H2C_READ_ADDR) & BIT_MASK_H2C_READ_ADDR)
+#define BIT_SET_H2C_READ_ADDR(x, v)                                            \
+	(BIT_CLEAR_H2C_READ_ADDR(x) | BIT_H2C_READ_ADDR(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_H2C_READ_ADDR			(Offset 0x024C) */
+
+#define BIT_SHIFT_H2C_READ_ADDR_V1 0
+#define BIT_MASK_H2C_READ_ADDR_V1 0x7ffff
+#define BIT_H2C_READ_ADDR_V1(x)                                                \
+	(((x) & BIT_MASK_H2C_READ_ADDR_V1) << BIT_SHIFT_H2C_READ_ADDR_V1)
+#define BITS_H2C_READ_ADDR_V1                                                  \
+	(BIT_MASK_H2C_READ_ADDR_V1 << BIT_SHIFT_H2C_READ_ADDR_V1)
+#define BIT_CLEAR_H2C_READ_ADDR_V1(x) ((x) & (~BITS_H2C_READ_ADDR_V1))
+#define BIT_GET_H2C_READ_ADDR_V1(x)                                            \
+	(((x) >> BIT_SHIFT_H2C_READ_ADDR_V1) & BIT_MASK_H2C_READ_ADDR_V1)
+#define BIT_SET_H2C_READ_ADDR_V1(x, v)                                         \
+	(BIT_CLEAR_H2C_READ_ADDR_V1(x) | BIT_H2C_READ_ADDR_V1(v))
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_H2C_WR_ADDR				(Offset 0x0250) */
+
+#define BIT_SHIFT_H2C_WR_ADDR_V2 0
+#define BIT_MASK_H2C_WR_ADDR_V2 0xffff
+#define BIT_H2C_WR_ADDR_V2(x)                                                  \
+	(((x) & BIT_MASK_H2C_WR_ADDR_V2) << BIT_SHIFT_H2C_WR_ADDR_V2)
+#define BITS_H2C_WR_ADDR_V2                                                    \
+	(BIT_MASK_H2C_WR_ADDR_V2 << BIT_SHIFT_H2C_WR_ADDR_V2)
+#define BIT_CLEAR_H2C_WR_ADDR_V2(x) ((x) & (~BITS_H2C_WR_ADDR_V2))
+#define BIT_GET_H2C_WR_ADDR_V2(x)                                              \
+	(((x) >> BIT_SHIFT_H2C_WR_ADDR_V2) & BIT_MASK_H2C_WR_ADDR_V2)
+#define BIT_SET_H2C_WR_ADDR_V2(x, v)                                           \
+	(BIT_CLEAR_H2C_WR_ADDR_V2(x) | BIT_H2C_WR_ADDR_V2(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_H2C_WR_ADDR				(Offset 0x0250) */
+
+#define BIT_SHIFT_H2C_WR_ADDR 0
+#define BIT_MASK_H2C_WR_ADDR 0x3ffff
+#define BIT_H2C_WR_ADDR(x)                                                     \
+	(((x) & BIT_MASK_H2C_WR_ADDR) << BIT_SHIFT_H2C_WR_ADDR)
+#define BITS_H2C_WR_ADDR (BIT_MASK_H2C_WR_ADDR << BIT_SHIFT_H2C_WR_ADDR)
+#define BIT_CLEAR_H2C_WR_ADDR(x) ((x) & (~BITS_H2C_WR_ADDR))
+#define BIT_GET_H2C_WR_ADDR(x)                                                 \
+	(((x) >> BIT_SHIFT_H2C_WR_ADDR) & BIT_MASK_H2C_WR_ADDR)
+#define BIT_SET_H2C_WR_ADDR(x, v)                                              \
+	(BIT_CLEAR_H2C_WR_ADDR(x) | BIT_H2C_WR_ADDR(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_H2C_WR_ADDR				(Offset 0x0250) */
+
+#define BIT_SHIFT_H2C_WR_ADDR_V1 0
+#define BIT_MASK_H2C_WR_ADDR_V1 0x7ffff
+#define BIT_H2C_WR_ADDR_V1(x)                                                  \
+	(((x) & BIT_MASK_H2C_WR_ADDR_V1) << BIT_SHIFT_H2C_WR_ADDR_V1)
+#define BITS_H2C_WR_ADDR_V1                                                    \
+	(BIT_MASK_H2C_WR_ADDR_V1 << BIT_SHIFT_H2C_WR_ADDR_V1)
+#define BIT_CLEAR_H2C_WR_ADDR_V1(x) ((x) & (~BITS_H2C_WR_ADDR_V1))
+#define BIT_GET_H2C_WR_ADDR_V1(x)                                              \
+	(((x) >> BIT_SHIFT_H2C_WR_ADDR_V1) & BIT_MASK_H2C_WR_ADDR_V1)
+#define BIT_SET_H2C_WR_ADDR_V1(x, v)                                           \
+	(BIT_CLEAR_H2C_WR_ADDR_V1(x) | BIT_H2C_WR_ADDR_V1(v))
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_H2C_INFO				(Offset 0x0254) */
+
+#define BIT_SHIFT_MDIO_PHY_ADDR 24
+#define BIT_MASK_MDIO_PHY_ADDR 0x1f
+#define BIT_MDIO_PHY_ADDR(x)                                                   \
+	(((x) & BIT_MASK_MDIO_PHY_ADDR) << BIT_SHIFT_MDIO_PHY_ADDR)
+#define BITS_MDIO_PHY_ADDR (BIT_MASK_MDIO_PHY_ADDR << BIT_SHIFT_MDIO_PHY_ADDR)
+#define BIT_CLEAR_MDIO_PHY_ADDR(x) ((x) & (~BITS_MDIO_PHY_ADDR))
+#define BIT_GET_MDIO_PHY_ADDR(x)                                               \
+	(((x) >> BIT_SHIFT_MDIO_PHY_ADDR) & BIT_MASK_MDIO_PHY_ADDR)
+#define BIT_SET_MDIO_PHY_ADDR(x, v)                                            \
+	(BIT_CLEAR_MDIO_PHY_ADDR(x) | BIT_MDIO_PHY_ADDR(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT)
+
+/* 2 REG_H2C_INFO				(Offset 0x0254) */
+
+#define BIT_SHIFT_VI_PUB_LIMIT 16
+#define BIT_MASK_VI_PUB_LIMIT 0xfff
+#define BIT_VI_PUB_LIMIT(x)                                                    \
+	(((x) & BIT_MASK_VI_PUB_LIMIT) << BIT_SHIFT_VI_PUB_LIMIT)
+#define BITS_VI_PUB_LIMIT (BIT_MASK_VI_PUB_LIMIT << BIT_SHIFT_VI_PUB_LIMIT)
+#define BIT_CLEAR_VI_PUB_LIMIT(x) ((x) & (~BITS_VI_PUB_LIMIT))
+#define BIT_GET_VI_PUB_LIMIT(x)                                                \
+	(((x) >> BIT_SHIFT_VI_PUB_LIMIT) & BIT_MASK_VI_PUB_LIMIT)
+#define BIT_SET_VI_PUB_LIMIT(x, v)                                             \
+	(BIT_CLEAR_VI_PUB_LIMIT(x) | BIT_VI_PUB_LIMIT(v))
+
+#define BIT_SHIFT_BK_PUB_LIMIT 16
+#define BIT_MASK_BK_PUB_LIMIT 0xfff
+#define BIT_BK_PUB_LIMIT(x)                                                    \
+	(((x) & BIT_MASK_BK_PUB_LIMIT) << BIT_SHIFT_BK_PUB_LIMIT)
+#define BITS_BK_PUB_LIMIT (BIT_MASK_BK_PUB_LIMIT << BIT_SHIFT_BK_PUB_LIMIT)
+#define BIT_CLEAR_BK_PUB_LIMIT(x) ((x) & (~BITS_BK_PUB_LIMIT))
+#define BIT_GET_BK_PUB_LIMIT(x)                                                \
+	(((x) >> BIT_SHIFT_BK_PUB_LIMIT) & BIT_MASK_BK_PUB_LIMIT)
+#define BIT_SET_BK_PUB_LIMIT(x, v)                                             \
+	(BIT_CLEAR_BK_PUB_LIMIT(x) | BIT_BK_PUB_LIMIT(v))
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+/* 2 REG_H2C_INFO				(Offset 0x0254) */
+
+#define BIT_EX2Q_EN_PUBLIC_LIMIT BIT(13)
+#define BIT_EX1Q_EN_PUBLIC_LIMIT BIT(12)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT)
+
+/* 2 REG_H2C_INFO				(Offset 0x0254) */
+
+#define BIT_EXQ_EN_PUBLIC_LIMIT BIT(11)
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+/* 2 REG_H2C_INFO				(Offset 0x0254) */
+
+#define BIT_EQ_EN_PUBLIC_LIMIT BIT(11)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT)
+
+/* 2 REG_H2C_INFO				(Offset 0x0254) */
+
+#define BIT_NPQ_EN_PUBLIC_LIMIT BIT(10)
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+/* 2 REG_H2C_INFO				(Offset 0x0254) */
+
+#define BIT_NQ_EN_PUBLIC_LIMIT BIT(10)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT)
+
+/* 2 REG_H2C_INFO				(Offset 0x0254) */
+
+#define BIT_LPQ_EN_PUBLIC_LIMIT BIT(9)
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+/* 2 REG_H2C_INFO				(Offset 0x0254) */
+
+#define BIT_LQ_EN_PUBLIC_LIMIT BIT(9)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT)
+
+/* 2 REG_H2C_INFO				(Offset 0x0254) */
+
+#define BIT_HPQ_EN_PUBLIC_LIMIT BIT(8)
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+/* 2 REG_H2C_INFO				(Offset 0x0254) */
+
+#define BIT_HQ_EN_PUBLIC_LIMIT BIT(8)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_H2C_INFO				(Offset 0x0254) */
+
+#define BIT_H2C_SPACE_VLD BIT(3)
+#define BIT_H2C_WR_ADDR_RST BIT(2)
+
+#define BIT_SHIFT_H2C_LEN_SEL 0
+#define BIT_MASK_H2C_LEN_SEL 0x3
+#define BIT_H2C_LEN_SEL(x)                                                     \
+	(((x) & BIT_MASK_H2C_LEN_SEL) << BIT_SHIFT_H2C_LEN_SEL)
+#define BITS_H2C_LEN_SEL (BIT_MASK_H2C_LEN_SEL << BIT_SHIFT_H2C_LEN_SEL)
+#define BIT_CLEAR_H2C_LEN_SEL(x) ((x) & (~BITS_H2C_LEN_SEL))
+#define BIT_GET_H2C_LEN_SEL(x)                                                 \
+	(((x) >> BIT_SHIFT_H2C_LEN_SEL) & BIT_MASK_H2C_LEN_SEL)
+#define BIT_SET_H2C_LEN_SEL(x, v)                                              \
+	(BIT_CLEAR_H2C_LEN_SEL(x) | BIT_H2C_LEN_SEL(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT)
+
+/* 2 REG_H2C_INFO				(Offset 0x0254) */
+
+#define BIT_SHIFT_VO_PUB_LIMIT 0
+#define BIT_MASK_VO_PUB_LIMIT 0xfff
+#define BIT_VO_PUB_LIMIT(x)                                                    \
+	(((x) & BIT_MASK_VO_PUB_LIMIT) << BIT_SHIFT_VO_PUB_LIMIT)
+#define BITS_VO_PUB_LIMIT (BIT_MASK_VO_PUB_LIMIT << BIT_SHIFT_VO_PUB_LIMIT)
+#define BIT_CLEAR_VO_PUB_LIMIT(x) ((x) & (~BITS_VO_PUB_LIMIT))
+#define BIT_GET_VO_PUB_LIMIT(x)                                                \
+	(((x) >> BIT_SHIFT_VO_PUB_LIMIT) & BIT_MASK_VO_PUB_LIMIT)
+#define BIT_SET_VO_PUB_LIMIT(x, v)                                             \
+	(BIT_CLEAR_VO_PUB_LIMIT(x) | BIT_VO_PUB_LIMIT(v))
+
+#define BIT_SHIFT_BE_PUB_LIMIT 0
+#define BIT_MASK_BE_PUB_LIMIT 0xfff
+#define BIT_BE_PUB_LIMIT(x)                                                    \
+	(((x) & BIT_MASK_BE_PUB_LIMIT) << BIT_SHIFT_BE_PUB_LIMIT)
+#define BITS_BE_PUB_LIMIT (BIT_MASK_BE_PUB_LIMIT << BIT_SHIFT_BE_PUB_LIMIT)
+#define BIT_CLEAR_BE_PUB_LIMIT(x) ((x) & (~BITS_BE_PUB_LIMIT))
+#define BIT_GET_BE_PUB_LIMIT(x)                                                \
+	(((x) >> BIT_SHIFT_BE_PUB_LIMIT) & BIT_MASK_BE_PUB_LIMIT)
+#define BIT_SET_BE_PUB_LIMIT(x, v)                                             \
+	(BIT_CLEAR_BE_PUB_LIMIT(x) | BIT_BE_PUB_LIMIT(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_DMA_OQT_0				(Offset 0x0260) */
+
+#define BIT_SHIFT_TX_OQT_12_FREE_SPACE 24
+#define BIT_MASK_TX_OQT_12_FREE_SPACE 0xff
+#define BIT_TX_OQT_12_FREE_SPACE(x)                                            \
+	(((x) & BIT_MASK_TX_OQT_12_FREE_SPACE)                                 \
+	 << BIT_SHIFT_TX_OQT_12_FREE_SPACE)
+#define BITS_TX_OQT_12_FREE_SPACE                                              \
+	(BIT_MASK_TX_OQT_12_FREE_SPACE << BIT_SHIFT_TX_OQT_12_FREE_SPACE)
+#define BIT_CLEAR_TX_OQT_12_FREE_SPACE(x) ((x) & (~BITS_TX_OQT_12_FREE_SPACE))
+#define BIT_GET_TX_OQT_12_FREE_SPACE(x)                                        \
+	(((x) >> BIT_SHIFT_TX_OQT_12_FREE_SPACE) &                             \
+	 BIT_MASK_TX_OQT_12_FREE_SPACE)
+#define BIT_SET_TX_OQT_12_FREE_SPACE(x, v)                                     \
+	(BIT_CLEAR_TX_OQT_12_FREE_SPACE(x) | BIT_TX_OQT_12_FREE_SPACE(v))
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+/* 2 REG_TQPNT5				(Offset 0x0260) */
+
+#define BIT_SHIFT_EX1Q_HIGH_TH_V1 16
+#define BIT_MASK_EX1Q_HIGH_TH_V1 0xfff
+#define BIT_EX1Q_HIGH_TH_V1(x)                                                 \
+	(((x) & BIT_MASK_EX1Q_HIGH_TH_V1) << BIT_SHIFT_EX1Q_HIGH_TH_V1)
+#define BITS_EX1Q_HIGH_TH_V1                                                   \
+	(BIT_MASK_EX1Q_HIGH_TH_V1 << BIT_SHIFT_EX1Q_HIGH_TH_V1)
+#define BIT_CLEAR_EX1Q_HIGH_TH_V1(x) ((x) & (~BITS_EX1Q_HIGH_TH_V1))
+#define BIT_GET_EX1Q_HIGH_TH_V1(x)                                             \
+	(((x) >> BIT_SHIFT_EX1Q_HIGH_TH_V1) & BIT_MASK_EX1Q_HIGH_TH_V1)
+#define BIT_SET_EX1Q_HIGH_TH_V1(x, v)                                          \
+	(BIT_CLEAR_EX1Q_HIGH_TH_V1(x) | BIT_EX1Q_HIGH_TH_V1(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_DMA_OQT_0				(Offset 0x0260) */
+
+#define BIT_SHIFT_TX_OQT_8_11_FREE_SPACE 16
+#define BIT_MASK_TX_OQT_8_11_FREE_SPACE 0xff
+#define BIT_TX_OQT_8_11_FREE_SPACE(x)                                          \
+	(((x) & BIT_MASK_TX_OQT_8_11_FREE_SPACE)                               \
+	 << BIT_SHIFT_TX_OQT_8_11_FREE_SPACE)
+#define BITS_TX_OQT_8_11_FREE_SPACE                                            \
+	(BIT_MASK_TX_OQT_8_11_FREE_SPACE << BIT_SHIFT_TX_OQT_8_11_FREE_SPACE)
+#define BIT_CLEAR_TX_OQT_8_11_FREE_SPACE(x)                                    \
+	((x) & (~BITS_TX_OQT_8_11_FREE_SPACE))
+#define BIT_GET_TX_OQT_8_11_FREE_SPACE(x)                                      \
+	(((x) >> BIT_SHIFT_TX_OQT_8_11_FREE_SPACE) &                           \
+	 BIT_MASK_TX_OQT_8_11_FREE_SPACE)
+#define BIT_SET_TX_OQT_8_11_FREE_SPACE(x, v)                                   \
+	(BIT_CLEAR_TX_OQT_8_11_FREE_SPACE(x) | BIT_TX_OQT_8_11_FREE_SPACE(v))
+
+#define BIT_SHIFT_TX_OQT_16_FREE_SPACE 16
+#define BIT_MASK_TX_OQT_16_FREE_SPACE 0xff
+#define BIT_TX_OQT_16_FREE_SPACE(x)                                            \
+	(((x) & BIT_MASK_TX_OQT_16_FREE_SPACE)                                 \
+	 << BIT_SHIFT_TX_OQT_16_FREE_SPACE)
+#define BITS_TX_OQT_16_FREE_SPACE                                              \
+	(BIT_MASK_TX_OQT_16_FREE_SPACE << BIT_SHIFT_TX_OQT_16_FREE_SPACE)
+#define BIT_CLEAR_TX_OQT_16_FREE_SPACE(x) ((x) & (~BITS_TX_OQT_16_FREE_SPACE))
+#define BIT_GET_TX_OQT_16_FREE_SPACE(x)                                        \
+	(((x) >> BIT_SHIFT_TX_OQT_16_FREE_SPACE) &                             \
+	 BIT_MASK_TX_OQT_16_FREE_SPACE)
+#define BIT_SET_TX_OQT_16_FREE_SPACE(x, v)                                     \
+	(BIT_CLEAR_TX_OQT_16_FREE_SPACE(x) | BIT_TX_OQT_16_FREE_SPACE(v))
+
+#define BIT_SHIFT_TX_OQT_4_7_FREE_SPACE 8
+#define BIT_MASK_TX_OQT_4_7_FREE_SPACE 0xff
+#define BIT_TX_OQT_4_7_FREE_SPACE(x)                                           \
+	(((x) & BIT_MASK_TX_OQT_4_7_FREE_SPACE)                                \
+	 << BIT_SHIFT_TX_OQT_4_7_FREE_SPACE)
+#define BITS_TX_OQT_4_7_FREE_SPACE                                             \
+	(BIT_MASK_TX_OQT_4_7_FREE_SPACE << BIT_SHIFT_TX_OQT_4_7_FREE_SPACE)
+#define BIT_CLEAR_TX_OQT_4_7_FREE_SPACE(x) ((x) & (~BITS_TX_OQT_4_7_FREE_SPACE))
+#define BIT_GET_TX_OQT_4_7_FREE_SPACE(x)                                       \
+	(((x) >> BIT_SHIFT_TX_OQT_4_7_FREE_SPACE) &                            \
+	 BIT_MASK_TX_OQT_4_7_FREE_SPACE)
+#define BIT_SET_TX_OQT_4_7_FREE_SPACE(x, v)                                    \
+	(BIT_CLEAR_TX_OQT_4_7_FREE_SPACE(x) | BIT_TX_OQT_4_7_FREE_SPACE(v))
+
+#define BIT_SHIFT_TX_OQT_14_15_FREE_SPACE 8
+#define BIT_MASK_TX_OQT_14_15_FREE_SPACE 0xff
+#define BIT_TX_OQT_14_15_FREE_SPACE(x)                                         \
+	(((x) & BIT_MASK_TX_OQT_14_15_FREE_SPACE)                              \
+	 << BIT_SHIFT_TX_OQT_14_15_FREE_SPACE)
+#define BITS_TX_OQT_14_15_FREE_SPACE                                           \
+	(BIT_MASK_TX_OQT_14_15_FREE_SPACE << BIT_SHIFT_TX_OQT_14_15_FREE_SPACE)
+#define BIT_CLEAR_TX_OQT_14_15_FREE_SPACE(x)                                   \
+	((x) & (~BITS_TX_OQT_14_15_FREE_SPACE))
+#define BIT_GET_TX_OQT_14_15_FREE_SPACE(x)                                     \
+	(((x) >> BIT_SHIFT_TX_OQT_14_15_FREE_SPACE) &                          \
+	 BIT_MASK_TX_OQT_14_15_FREE_SPACE)
+#define BIT_SET_TX_OQT_14_15_FREE_SPACE(x, v)                                  \
+	(BIT_CLEAR_TX_OQT_14_15_FREE_SPACE(x) | BIT_TX_OQT_14_15_FREE_SPACE(v))
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+/* 2 REG_TQPNT5				(Offset 0x0260) */
+
+#define BIT_SHIFT_EX1Q_LOW_TH_V1 0
+#define BIT_MASK_EX1Q_LOW_TH_V1 0xfff
+#define BIT_EX1Q_LOW_TH_V1(x)                                                  \
+	(((x) & BIT_MASK_EX1Q_LOW_TH_V1) << BIT_SHIFT_EX1Q_LOW_TH_V1)
+#define BITS_EX1Q_LOW_TH_V1                                                    \
+	(BIT_MASK_EX1Q_LOW_TH_V1 << BIT_SHIFT_EX1Q_LOW_TH_V1)
+#define BIT_CLEAR_EX1Q_LOW_TH_V1(x) ((x) & (~BITS_EX1Q_LOW_TH_V1))
+#define BIT_GET_EX1Q_LOW_TH_V1(x)                                              \
+	(((x) >> BIT_SHIFT_EX1Q_LOW_TH_V1) & BIT_MASK_EX1Q_LOW_TH_V1)
+#define BIT_SET_EX1Q_LOW_TH_V1(x, v)                                           \
+	(BIT_CLEAR_EX1Q_LOW_TH_V1(x) | BIT_EX1Q_LOW_TH_V1(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_DMA_OQT_0				(Offset 0x0260) */
+
+#define BIT_SHIFT_TX_OQT_0_3_FREE_SPACE 0
+#define BIT_MASK_TX_OQT_0_3_FREE_SPACE 0xff
+#define BIT_TX_OQT_0_3_FREE_SPACE(x)                                           \
+	(((x) & BIT_MASK_TX_OQT_0_3_FREE_SPACE)                                \
+	 << BIT_SHIFT_TX_OQT_0_3_FREE_SPACE)
+#define BITS_TX_OQT_0_3_FREE_SPACE                                             \
+	(BIT_MASK_TX_OQT_0_3_FREE_SPACE << BIT_SHIFT_TX_OQT_0_3_FREE_SPACE)
+#define BIT_CLEAR_TX_OQT_0_3_FREE_SPACE(x) ((x) & (~BITS_TX_OQT_0_3_FREE_SPACE))
+#define BIT_GET_TX_OQT_0_3_FREE_SPACE(x)                                       \
+	(((x) >> BIT_SHIFT_TX_OQT_0_3_FREE_SPACE) &                            \
+	 BIT_MASK_TX_OQT_0_3_FREE_SPACE)
+#define BIT_SET_TX_OQT_0_3_FREE_SPACE(x, v)                                    \
+	(BIT_CLEAR_TX_OQT_0_3_FREE_SPACE(x) | BIT_TX_OQT_0_3_FREE_SPACE(v))
+
+#define BIT_SHIFT_TX_OQT_13_FREE_SPACE 0
+#define BIT_MASK_TX_OQT_13_FREE_SPACE 0xff
+#define BIT_TX_OQT_13_FREE_SPACE(x)                                            \
+	(((x) & BIT_MASK_TX_OQT_13_FREE_SPACE)                                 \
+	 << BIT_SHIFT_TX_OQT_13_FREE_SPACE)
+#define BITS_TX_OQT_13_FREE_SPACE                                              \
+	(BIT_MASK_TX_OQT_13_FREE_SPACE << BIT_SHIFT_TX_OQT_13_FREE_SPACE)
+#define BIT_CLEAR_TX_OQT_13_FREE_SPACE(x) ((x) & (~BITS_TX_OQT_13_FREE_SPACE))
+#define BIT_GET_TX_OQT_13_FREE_SPACE(x)                                        \
+	(((x) >> BIT_SHIFT_TX_OQT_13_FREE_SPACE) &                             \
+	 BIT_MASK_TX_OQT_13_FREE_SPACE)
+#define BIT_SET_TX_OQT_13_FREE_SPACE(x, v)                                     \
+	(BIT_CLEAR_TX_OQT_13_FREE_SPACE(x) | BIT_TX_OQT_13_FREE_SPACE(v))
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+/* 2 REG_TQPNT6				(Offset 0x0264) */
+
+#define BIT_SHIFT_EX2Q_HIGH_TH_V1 16
+#define BIT_MASK_EX2Q_HIGH_TH_V1 0xfff
+#define BIT_EX2Q_HIGH_TH_V1(x)                                                 \
+	(((x) & BIT_MASK_EX2Q_HIGH_TH_V1) << BIT_SHIFT_EX2Q_HIGH_TH_V1)
+#define BITS_EX2Q_HIGH_TH_V1                                                   \
+	(BIT_MASK_EX2Q_HIGH_TH_V1 << BIT_SHIFT_EX2Q_HIGH_TH_V1)
+#define BIT_CLEAR_EX2Q_HIGH_TH_V1(x) ((x) & (~BITS_EX2Q_HIGH_TH_V1))
+#define BIT_GET_EX2Q_HIGH_TH_V1(x)                                             \
+	(((x) >> BIT_SHIFT_EX2Q_HIGH_TH_V1) & BIT_MASK_EX2Q_HIGH_TH_V1)
+#define BIT_SET_EX2Q_HIGH_TH_V1(x, v)                                          \
+	(BIT_CLEAR_EX2Q_HIGH_TH_V1(x) | BIT_EX2Q_HIGH_TH_V1(v))
+
+#define BIT_SHIFT_EX2Q_LOW_TH_V1 0
+#define BIT_MASK_EX2Q_LOW_TH_V1 0xfff
+#define BIT_EX2Q_LOW_TH_V1(x)                                                  \
+	(((x) & BIT_MASK_EX2Q_LOW_TH_V1) << BIT_SHIFT_EX2Q_LOW_TH_V1)
+#define BITS_EX2Q_LOW_TH_V1                                                    \
+	(BIT_MASK_EX2Q_LOW_TH_V1 << BIT_SHIFT_EX2Q_LOW_TH_V1)
+#define BIT_CLEAR_EX2Q_LOW_TH_V1(x) ((x) & (~BITS_EX2Q_LOW_TH_V1))
+#define BIT_GET_EX2Q_LOW_TH_V1(x)                                              \
+	(((x) >> BIT_SHIFT_EX2Q_LOW_TH_V1) & BIT_MASK_EX2Q_LOW_TH_V1)
+#define BIT_SET_EX2Q_LOW_TH_V1(x, v)                                           \
+	(BIT_CLEAR_EX2Q_LOW_TH_V1(x) | BIT_EX2Q_LOW_TH_V1(v))
+
+/* 2 REG_FIFOPAGE_INFO_6			(Offset 0x0268) */
+
+#define BIT_SHIFT_EX1Q_AVAL_PG_V1 16
+#define BIT_MASK_EX1Q_AVAL_PG_V1 0xfff
+#define BIT_EX1Q_AVAL_PG_V1(x)                                                 \
+	(((x) & BIT_MASK_EX1Q_AVAL_PG_V1) << BIT_SHIFT_EX1Q_AVAL_PG_V1)
+#define BITS_EX1Q_AVAL_PG_V1                                                   \
+	(BIT_MASK_EX1Q_AVAL_PG_V1 << BIT_SHIFT_EX1Q_AVAL_PG_V1)
+#define BIT_CLEAR_EX1Q_AVAL_PG_V1(x) ((x) & (~BITS_EX1Q_AVAL_PG_V1))
+#define BIT_GET_EX1Q_AVAL_PG_V1(x)                                             \
+	(((x) >> BIT_SHIFT_EX1Q_AVAL_PG_V1) & BIT_MASK_EX1Q_AVAL_PG_V1)
+#define BIT_SET_EX1Q_AVAL_PG_V1(x, v)                                          \
+	(BIT_CLEAR_EX1Q_AVAL_PG_V1(x) | BIT_EX1Q_AVAL_PG_V1(v))
+
+#define BIT_SHIFT_EX1Q_V1 0
+#define BIT_MASK_EX1Q_V1 0xfff
+#define BIT_EX1Q_V1(x) (((x) & BIT_MASK_EX1Q_V1) << BIT_SHIFT_EX1Q_V1)
+#define BITS_EX1Q_V1 (BIT_MASK_EX1Q_V1 << BIT_SHIFT_EX1Q_V1)
+#define BIT_CLEAR_EX1Q_V1(x) ((x) & (~BITS_EX1Q_V1))
+#define BIT_GET_EX1Q_V1(x) (((x) >> BIT_SHIFT_EX1Q_V1) & BIT_MASK_EX1Q_V1)
+#define BIT_SET_EX1Q_V1(x, v) (BIT_CLEAR_EX1Q_V1(x) | BIT_EX1Q_V1(v))
+
+/* 2 REG_FIFOPAGE_INFO_7			(Offset 0x026C) */
+
+#define BIT_SHIFT_EX2Q_AVAL_PG_V1 16
+#define BIT_MASK_EX2Q_AVAL_PG_V1 0xfff
+#define BIT_EX2Q_AVAL_PG_V1(x)                                                 \
+	(((x) & BIT_MASK_EX2Q_AVAL_PG_V1) << BIT_SHIFT_EX2Q_AVAL_PG_V1)
+#define BITS_EX2Q_AVAL_PG_V1                                                   \
+	(BIT_MASK_EX2Q_AVAL_PG_V1 << BIT_SHIFT_EX2Q_AVAL_PG_V1)
+#define BIT_CLEAR_EX2Q_AVAL_PG_V1(x) ((x) & (~BITS_EX2Q_AVAL_PG_V1))
+#define BIT_GET_EX2Q_AVAL_PG_V1(x)                                             \
+	(((x) >> BIT_SHIFT_EX2Q_AVAL_PG_V1) & BIT_MASK_EX2Q_AVAL_PG_V1)
+#define BIT_SET_EX2Q_AVAL_PG_V1(x, v)                                          \
+	(BIT_CLEAR_EX2Q_AVAL_PG_V1(x) | BIT_EX2Q_AVAL_PG_V1(v))
+
+#define BIT_SHIFT_EX2Q_V1 0
+#define BIT_MASK_EX2Q_V1 0xfff
+#define BIT_EX2Q_V1(x) (((x) & BIT_MASK_EX2Q_V1) << BIT_SHIFT_EX2Q_V1)
+#define BITS_EX2Q_V1 (BIT_MASK_EX2Q_V1 << BIT_SHIFT_EX2Q_V1)
+#define BIT_CLEAR_EX2Q_V1(x) ((x) & (~BITS_EX2Q_V1))
+#define BIT_GET_EX2Q_V1(x) (((x) >> BIT_SHIFT_EX2Q_V1) & BIT_MASK_EX2Q_V1)
+#define BIT_SET_EX2Q_V1(x, v) (BIT_CLEAR_EX2Q_V1(x) | BIT_EX2Q_V1(v))
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_PGSUB_H				(Offset 0x0270) */
+
+#define BIT_SHIFT_HPQ_PGSUB_CNT 0
+#define BIT_MASK_HPQ_PGSUB_CNT 0xffffffffL
+#define BIT_HPQ_PGSUB_CNT(x)                                                   \
+	(((x) & BIT_MASK_HPQ_PGSUB_CNT) << BIT_SHIFT_HPQ_PGSUB_CNT)
+#define BITS_HPQ_PGSUB_CNT (BIT_MASK_HPQ_PGSUB_CNT << BIT_SHIFT_HPQ_PGSUB_CNT)
+#define BIT_CLEAR_HPQ_PGSUB_CNT(x) ((x) & (~BITS_HPQ_PGSUB_CNT))
+#define BIT_GET_HPQ_PGSUB_CNT(x)                                               \
+	(((x) >> BIT_SHIFT_HPQ_PGSUB_CNT) & BIT_MASK_HPQ_PGSUB_CNT)
+#define BIT_SET_HPQ_PGSUB_CNT(x, v)                                            \
+	(BIT_CLEAR_HPQ_PGSUB_CNT(x) | BIT_HPQ_PGSUB_CNT(v))
+
+/* 2 REG_PGSUB_N				(Offset 0x0274) */
+
+#define BIT_SHIFT_NPQ_PGSUB_CNT 0
+#define BIT_MASK_NPQ_PGSUB_CNT 0xffffffffL
+#define BIT_NPQ_PGSUB_CNT(x)                                                   \
+	(((x) & BIT_MASK_NPQ_PGSUB_CNT) << BIT_SHIFT_NPQ_PGSUB_CNT)
+#define BITS_NPQ_PGSUB_CNT (BIT_MASK_NPQ_PGSUB_CNT << BIT_SHIFT_NPQ_PGSUB_CNT)
+#define BIT_CLEAR_NPQ_PGSUB_CNT(x) ((x) & (~BITS_NPQ_PGSUB_CNT))
+#define BIT_GET_NPQ_PGSUB_CNT(x)                                               \
+	(((x) >> BIT_SHIFT_NPQ_PGSUB_CNT) & BIT_MASK_NPQ_PGSUB_CNT)
+#define BIT_SET_NPQ_PGSUB_CNT(x, v)                                            \
+	(BIT_CLEAR_NPQ_PGSUB_CNT(x) | BIT_NPQ_PGSUB_CNT(v))
+
+/* 2 REG_PGSUB_L				(Offset 0x0278) */
+
+#define BIT_SHIFT_LPQ_PGSUB_CNT 0
+#define BIT_MASK_LPQ_PGSUB_CNT 0xffffffffL
+#define BIT_LPQ_PGSUB_CNT(x)                                                   \
+	(((x) & BIT_MASK_LPQ_PGSUB_CNT) << BIT_SHIFT_LPQ_PGSUB_CNT)
+#define BITS_LPQ_PGSUB_CNT (BIT_MASK_LPQ_PGSUB_CNT << BIT_SHIFT_LPQ_PGSUB_CNT)
+#define BIT_CLEAR_LPQ_PGSUB_CNT(x) ((x) & (~BITS_LPQ_PGSUB_CNT))
+#define BIT_GET_LPQ_PGSUB_CNT(x)                                               \
+	(((x) >> BIT_SHIFT_LPQ_PGSUB_CNT) & BIT_MASK_LPQ_PGSUB_CNT)
+#define BIT_SET_LPQ_PGSUB_CNT(x, v)                                            \
+	(BIT_CLEAR_LPQ_PGSUB_CNT(x) | BIT_LPQ_PGSUB_CNT(v))
+
+/* 2 REG_PGSUB_E				(Offset 0x027C) */
+
+#define BIT_SHIFT_EPQ_PGSUB_CNT 0
+#define BIT_MASK_EPQ_PGSUB_CNT 0xffffffffL
+#define BIT_EPQ_PGSUB_CNT(x)                                                   \
+	(((x) & BIT_MASK_EPQ_PGSUB_CNT) << BIT_SHIFT_EPQ_PGSUB_CNT)
+#define BITS_EPQ_PGSUB_CNT (BIT_MASK_EPQ_PGSUB_CNT << BIT_SHIFT_EPQ_PGSUB_CNT)
+#define BIT_CLEAR_EPQ_PGSUB_CNT(x) ((x) & (~BITS_EPQ_PGSUB_CNT))
+#define BIT_GET_EPQ_PGSUB_CNT(x)                                               \
+	(((x) >> BIT_SHIFT_EPQ_PGSUB_CNT) & BIT_MASK_EPQ_PGSUB_CNT)
+#define BIT_SET_EPQ_PGSUB_CNT(x, v)                                            \
+	(BIT_CLEAR_EPQ_PGSUB_CNT(x) | BIT_EPQ_PGSUB_CNT(v))
+
+#define BIT_SHIFT_FWFF_PKT_STR_ADDR_V2 0
+#define BIT_MASK_FWFF_PKT_STR_ADDR_V2 0x3fff
+#define BIT_FWFF_PKT_STR_ADDR_V2(x)                                            \
+	(((x) & BIT_MASK_FWFF_PKT_STR_ADDR_V2)                                 \
+	 << BIT_SHIFT_FWFF_PKT_STR_ADDR_V2)
+#define BITS_FWFF_PKT_STR_ADDR_V2                                              \
+	(BIT_MASK_FWFF_PKT_STR_ADDR_V2 << BIT_SHIFT_FWFF_PKT_STR_ADDR_V2)
+#define BIT_CLEAR_FWFF_PKT_STR_ADDR_V2(x) ((x) & (~BITS_FWFF_PKT_STR_ADDR_V2))
+#define BIT_GET_FWFF_PKT_STR_ADDR_V2(x)                                        \
+	(((x) >> BIT_SHIFT_FWFF_PKT_STR_ADDR_V2) &                             \
+	 BIT_MASK_FWFF_PKT_STR_ADDR_V2)
+#define BIT_SET_FWFF_PKT_STR_ADDR_V2(x, v)                                     \
+	(BIT_CLEAR_FWFF_PKT_STR_ADDR_V2(x) | BIT_FWFF_PKT_STR_ADDR_V2(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_RXDMA_AGG_PG_TH			(Offset 0x0280) */
+
+#define BIT_USB_RXDMA_AGG_EN BIT(31)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_RXDMA_AGG_PG_TH			(Offset 0x0280) */
+
+#define BIT_RXDMA_AGG_OLD_MOD_V1 BIT(31)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT)
+
+/* 2 REG_RXDMA_AGG_PG_TH			(Offset 0x0280) */
+
+#define BIT_DMA_STORE_MODE BIT(31)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_RXDMA_AGG_PG_TH			(Offset 0x0280) */
+
+#define BIT_DMA_STORE BIT(31)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_RXDMA_AGG_PG_TH			(Offset 0x0280) */
+
+#define BIT_EN_FW_ADD BIT(30)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_RXDMA_AGG_PG_TH			(Offset 0x0280) */
+
+#define BIT_RXAGG_TH_MODE BIT(29)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_RXDMA_AGG_PG_TH			(Offset 0x0280) */
+
+#define BIT_EN_PRE_CALC BIT(29)
+#define BIT_RXAGG_SW_EN BIT(28)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_RXDMA_AGG_PG_TH			(Offset 0x0280) */
+
+#define BIT_RXAGG_SW_TRIG BIT(27)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_RXDMA_AGG_PG_TH			(Offset 0x0280) */
+
+#define BIT_SHIFT_RXDMA_AGG_OLD_MOD 24
+#define BIT_MASK_RXDMA_AGG_OLD_MOD 0xff
+#define BIT_RXDMA_AGG_OLD_MOD(x)                                               \
+	(((x) & BIT_MASK_RXDMA_AGG_OLD_MOD) << BIT_SHIFT_RXDMA_AGG_OLD_MOD)
+#define BITS_RXDMA_AGG_OLD_MOD                                                 \
+	(BIT_MASK_RXDMA_AGG_OLD_MOD << BIT_SHIFT_RXDMA_AGG_OLD_MOD)
+#define BIT_CLEAR_RXDMA_AGG_OLD_MOD(x) ((x) & (~BITS_RXDMA_AGG_OLD_MOD))
+#define BIT_GET_RXDMA_AGG_OLD_MOD(x)                                           \
+	(((x) >> BIT_SHIFT_RXDMA_AGG_OLD_MOD) & BIT_MASK_RXDMA_AGG_OLD_MOD)
+#define BIT_SET_RXDMA_AGG_OLD_MOD(x, v)                                        \
+	(BIT_CLEAR_RXDMA_AGG_OLD_MOD(x) | BIT_RXDMA_AGG_OLD_MOD(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_RXDMA_AGG_PG_TH			(Offset 0x0280) */
+
+#define BIT_SHIFT_PKT_NUM_WOL 16
+#define BIT_MASK_PKT_NUM_WOL 0xff
+#define BIT_PKT_NUM_WOL(x)                                                     \
+	(((x) & BIT_MASK_PKT_NUM_WOL) << BIT_SHIFT_PKT_NUM_WOL)
+#define BITS_PKT_NUM_WOL (BIT_MASK_PKT_NUM_WOL << BIT_SHIFT_PKT_NUM_WOL)
+#define BIT_CLEAR_PKT_NUM_WOL(x) ((x) & (~BITS_PKT_NUM_WOL))
+#define BIT_GET_PKT_NUM_WOL(x)                                                 \
+	(((x) >> BIT_SHIFT_PKT_NUM_WOL) & BIT_MASK_PKT_NUM_WOL)
+#define BIT_SET_PKT_NUM_WOL(x, v)                                              \
+	(BIT_CLEAR_PKT_NUM_WOL(x) | BIT_PKT_NUM_WOL(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8881A_SUPPORT)
+
+/* 2 REG_RXDMA_AGG_PG_TH			(Offset 0x0280) */
+
+#define BIT_SHIFT_DMA_AGG_TO_V1 8
+#define BIT_MASK_DMA_AGG_TO_V1 0xff
+#define BIT_DMA_AGG_TO_V1(x)                                                   \
+	(((x) & BIT_MASK_DMA_AGG_TO_V1) << BIT_SHIFT_DMA_AGG_TO_V1)
+#define BITS_DMA_AGG_TO_V1 (BIT_MASK_DMA_AGG_TO_V1 << BIT_SHIFT_DMA_AGG_TO_V1)
+#define BIT_CLEAR_DMA_AGG_TO_V1(x) ((x) & (~BITS_DMA_AGG_TO_V1))
+#define BIT_GET_DMA_AGG_TO_V1(x)                                               \
+	(((x) >> BIT_SHIFT_DMA_AGG_TO_V1) & BIT_MASK_DMA_AGG_TO_V1)
+#define BIT_SET_DMA_AGG_TO_V1(x, v)                                            \
+	(BIT_CLEAR_DMA_AGG_TO_V1(x) | BIT_DMA_AGG_TO_V1(v))
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_RXDMA_AGG_PG_TH			(Offset 0x0280) */
+
+#define BIT_SHIFT_DMA_AGG_TO 8
+#define BIT_MASK_DMA_AGG_TO 0xf
+#define BIT_DMA_AGG_TO(x) (((x) & BIT_MASK_DMA_AGG_TO) << BIT_SHIFT_DMA_AGG_TO)
+#define BITS_DMA_AGG_TO (BIT_MASK_DMA_AGG_TO << BIT_SHIFT_DMA_AGG_TO)
+#define BIT_CLEAR_DMA_AGG_TO(x) ((x) & (~BITS_DMA_AGG_TO))
+#define BIT_GET_DMA_AGG_TO(x)                                                  \
+	(((x) >> BIT_SHIFT_DMA_AGG_TO) & BIT_MASK_DMA_AGG_TO)
+#define BIT_SET_DMA_AGG_TO(x, v) (BIT_CLEAR_DMA_AGG_TO(x) | BIT_DMA_AGG_TO(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_RXDMA_AGG_PG_TH			(Offset 0x0280) */
+
+#define BIT_SHIFT_RXDMA_AGG_PG_TH_V1 0
+#define BIT_MASK_RXDMA_AGG_PG_TH_V1 0xf
+#define BIT_RXDMA_AGG_PG_TH_V1(x)                                              \
+	(((x) & BIT_MASK_RXDMA_AGG_PG_TH_V1) << BIT_SHIFT_RXDMA_AGG_PG_TH_V1)
+#define BITS_RXDMA_AGG_PG_TH_V1                                                \
+	(BIT_MASK_RXDMA_AGG_PG_TH_V1 << BIT_SHIFT_RXDMA_AGG_PG_TH_V1)
+#define BIT_CLEAR_RXDMA_AGG_PG_TH_V1(x) ((x) & (~BITS_RXDMA_AGG_PG_TH_V1))
+#define BIT_GET_RXDMA_AGG_PG_TH_V1(x)                                          \
+	(((x) >> BIT_SHIFT_RXDMA_AGG_PG_TH_V1) & BIT_MASK_RXDMA_AGG_PG_TH_V1)
+#define BIT_SET_RXDMA_AGG_PG_TH_V1(x, v)                                       \
+	(BIT_CLEAR_RXDMA_AGG_PG_TH_V1(x) | BIT_RXDMA_AGG_PG_TH_V1(v))
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_RXDMA_AGG_PG_TH			(Offset 0x0280) */
+
+#define BIT_SHIFT_RXDMA_AGG_PG_TH 0
+#define BIT_MASK_RXDMA_AGG_PG_TH 0xff
+#define BIT_RXDMA_AGG_PG_TH(x)                                                 \
+	(((x) & BIT_MASK_RXDMA_AGG_PG_TH) << BIT_SHIFT_RXDMA_AGG_PG_TH)
+#define BITS_RXDMA_AGG_PG_TH                                                   \
+	(BIT_MASK_RXDMA_AGG_PG_TH << BIT_SHIFT_RXDMA_AGG_PG_TH)
+#define BIT_CLEAR_RXDMA_AGG_PG_TH(x) ((x) & (~BITS_RXDMA_AGG_PG_TH))
+#define BIT_GET_RXDMA_AGG_PG_TH(x)                                             \
+	(((x) >> BIT_SHIFT_RXDMA_AGG_PG_TH) & BIT_MASK_RXDMA_AGG_PG_TH)
+#define BIT_SET_RXDMA_AGG_PG_TH(x, v)                                          \
+	(BIT_CLEAR_RXDMA_AGG_PG_TH(x) | BIT_RXDMA_AGG_PG_TH(v))
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_RXDMA_AGG_PG_TH			(Offset 0x0280) */
+
+#define BIT_SHIFT_QINFO_INDEX 0
+#define BIT_MASK_QINFO_INDEX 0x1f
+#define BIT_QINFO_INDEX(x)                                                     \
+	(((x) & BIT_MASK_QINFO_INDEX) << BIT_SHIFT_QINFO_INDEX)
+#define BITS_QINFO_INDEX (BIT_MASK_QINFO_INDEX << BIT_SHIFT_QINFO_INDEX)
+#define BIT_CLEAR_QINFO_INDEX(x) ((x) & (~BITS_QINFO_INDEX))
+#define BIT_GET_QINFO_INDEX(x)                                                 \
+	(((x) >> BIT_SHIFT_QINFO_INDEX) & BIT_MASK_QINFO_INDEX)
+#define BIT_SET_QINFO_INDEX(x, v)                                              \
+	(BIT_CLEAR_QINFO_INDEX(x) | BIT_QINFO_INDEX(v))
+
+#endif
+
+#if (HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_RXDMA_AGG_PG_TH			(Offset 0x0280) */
+
+#define BIT_SHIFT_RXDMA_AGG_PG_TH_V2 0
+#define BIT_MASK_RXDMA_AGG_PG_TH_V2 0xff
+#define BIT_RXDMA_AGG_PG_TH_V2(x)                                              \
+	(((x) & BIT_MASK_RXDMA_AGG_PG_TH_V2) << BIT_SHIFT_RXDMA_AGG_PG_TH_V2)
+#define BITS_RXDMA_AGG_PG_TH_V2                                                \
+	(BIT_MASK_RXDMA_AGG_PG_TH_V2 << BIT_SHIFT_RXDMA_AGG_PG_TH_V2)
+#define BIT_CLEAR_RXDMA_AGG_PG_TH_V2(x) ((x) & (~BITS_RXDMA_AGG_PG_TH_V2))
+#define BIT_GET_RXDMA_AGG_PG_TH_V2(x)                                          \
+	(((x) >> BIT_SHIFT_RXDMA_AGG_PG_TH_V2) & BIT_MASK_RXDMA_AGG_PG_TH_V2)
+#define BIT_SET_RXDMA_AGG_PG_TH_V2(x, v)                                       \
+	(BIT_CLEAR_RXDMA_AGG_PG_TH_V2(x) | BIT_RXDMA_AGG_PG_TH_V2(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_RXPKT_NUM				(Offset 0x0284) */
+
+#define BIT_SHIFT_RXPKT_NUM 24
+#define BIT_MASK_RXPKT_NUM 0xff
+#define BIT_RXPKT_NUM(x) (((x) & BIT_MASK_RXPKT_NUM) << BIT_SHIFT_RXPKT_NUM)
+#define BITS_RXPKT_NUM (BIT_MASK_RXPKT_NUM << BIT_SHIFT_RXPKT_NUM)
+#define BIT_CLEAR_RXPKT_NUM(x) ((x) & (~BITS_RXPKT_NUM))
+#define BIT_GET_RXPKT_NUM(x) (((x) >> BIT_SHIFT_RXPKT_NUM) & BIT_MASK_RXPKT_NUM)
+#define BIT_SET_RXPKT_NUM(x, v) (BIT_CLEAR_RXPKT_NUM(x) | BIT_RXPKT_NUM(v))
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_RXPKT_NUM				(Offset 0x0284) */
+
+#define BIT_STOP_RXDMA BIT(20)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_RXPKT_NUM				(Offset 0x0284) */
+
+#define BIT_SHIFT_FW_UPD_RDPTR19_TO_16 20
+#define BIT_MASK_FW_UPD_RDPTR19_TO_16 0xf
+#define BIT_FW_UPD_RDPTR19_TO_16(x)                                            \
+	(((x) & BIT_MASK_FW_UPD_RDPTR19_TO_16)                                 \
+	 << BIT_SHIFT_FW_UPD_RDPTR19_TO_16)
+#define BITS_FW_UPD_RDPTR19_TO_16                                              \
+	(BIT_MASK_FW_UPD_RDPTR19_TO_16 << BIT_SHIFT_FW_UPD_RDPTR19_TO_16)
+#define BIT_CLEAR_FW_UPD_RDPTR19_TO_16(x) ((x) & (~BITS_FW_UPD_RDPTR19_TO_16))
+#define BIT_GET_FW_UPD_RDPTR19_TO_16(x)                                        \
+	(((x) >> BIT_SHIFT_FW_UPD_RDPTR19_TO_16) &                             \
+	 BIT_MASK_FW_UPD_RDPTR19_TO_16)
+#define BIT_SET_FW_UPD_RDPTR19_TO_16(x, v)                                     \
+	(BIT_CLEAR_FW_UPD_RDPTR19_TO_16(x) | BIT_FW_UPD_RDPTR19_TO_16(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_RXPKT_NUM				(Offset 0x0284) */
+
+#define BIT_RXDMA_REQ BIT(19)
+#define BIT_RW_RELEASE_EN BIT(18)
+#define BIT_RXDMA_IDLE BIT(17)
+#define BIT_RXPKT_RELEASE_POLL BIT(16)
+
+#define BIT_SHIFT_FW_UPD_RDPTR 0
+#define BIT_MASK_FW_UPD_RDPTR 0xffff
+#define BIT_FW_UPD_RDPTR(x)                                                    \
+	(((x) & BIT_MASK_FW_UPD_RDPTR) << BIT_SHIFT_FW_UPD_RDPTR)
+#define BITS_FW_UPD_RDPTR (BIT_MASK_FW_UPD_RDPTR << BIT_SHIFT_FW_UPD_RDPTR)
+#define BIT_CLEAR_FW_UPD_RDPTR(x) ((x) & (~BITS_FW_UPD_RDPTR))
+#define BIT_GET_FW_UPD_RDPTR(x)                                                \
+	(((x) >> BIT_SHIFT_FW_UPD_RDPTR) & BIT_MASK_FW_UPD_RDPTR)
+#define BIT_SET_FW_UPD_RDPTR(x, v)                                             \
+	(BIT_CLEAR_FW_UPD_RDPTR(x) | BIT_FW_UPD_RDPTR(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT)
+
+/* 2 REG_RXDMA_STATUS			(Offset 0x0288) */
+
+#define BIT_FC2H_PKT_OVERFLOW BIT(8)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_RXDMA_STATUS			(Offset 0x0288) */
+
+#define BIT_C2H_PKT_OVF BIT(7)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_RXDMA_STATUS			(Offset 0x0288) */
+
+#define BIT_AGG_CFG_ISSUE BIT(6)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_RXDMA_STATUS			(Offset 0x0288) */
+
+#define BIT_AGG_CONFGI_ISSUE BIT(6)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_RXDMA_STATUS			(Offset 0x0288) */
+
+#define BIT_FW_POLL_ISSUE BIT(5)
+#define BIT_RX_DATA_UDN BIT(4)
+#define BIT_RX_SFF_UDN BIT(3)
+#define BIT_RX_SFF_OVF BIT(2)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_RXDMA_STATUS			(Offset 0x0288) */
+
+#define BIT_USB_REQ_LEN_OVF BIT(1)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_RXDMA_STATUS			(Offset 0x0288) */
+
+#define BIT_RXPKT_OVF BIT(0)
+
+/* 2 REG_RXDMA_DPR				(Offset 0x028C) */
+
+#define BIT_SHIFT_RDE_DEBUG 0
+#define BIT_MASK_RDE_DEBUG 0xffffffffL
+#define BIT_RDE_DEBUG(x) (((x) & BIT_MASK_RDE_DEBUG) << BIT_SHIFT_RDE_DEBUG)
+#define BITS_RDE_DEBUG (BIT_MASK_RDE_DEBUG << BIT_SHIFT_RDE_DEBUG)
+#define BIT_CLEAR_RDE_DEBUG(x) ((x) & (~BITS_RDE_DEBUG))
+#define BIT_GET_RDE_DEBUG(x) (((x) >> BIT_SHIFT_RDE_DEBUG) & BIT_MASK_RDE_DEBUG)
+#define BIT_SET_RDE_DEBUG(x, v) (BIT_CLEAR_RDE_DEBUG(x) | BIT_RDE_DEBUG(v))
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_RXDMA_MODE				(Offset 0x0290) */
+
+#define BIT_SHIFT_PKTNUM_TH_V2 24
+#define BIT_MASK_PKTNUM_TH_V2 0x1f
+#define BIT_PKTNUM_TH_V2(x)                                                    \
+	(((x) & BIT_MASK_PKTNUM_TH_V2) << BIT_SHIFT_PKTNUM_TH_V2)
+#define BITS_PKTNUM_TH_V2 (BIT_MASK_PKTNUM_TH_V2 << BIT_SHIFT_PKTNUM_TH_V2)
+#define BIT_CLEAR_PKTNUM_TH_V2(x) ((x) & (~BITS_PKTNUM_TH_V2))
+#define BIT_GET_PKTNUM_TH_V2(x)                                                \
+	(((x) >> BIT_SHIFT_PKTNUM_TH_V2) & BIT_MASK_PKTNUM_TH_V2)
+#define BIT_SET_PKTNUM_TH_V2(x, v)                                             \
+	(BIT_CLEAR_PKTNUM_TH_V2(x) | BIT_PKTNUM_TH_V2(v))
+
+#define BIT_TXBA_BREAK_USBAGG BIT(23)
+
+#define BIT_SHIFT_PKTLEN_PARA 16
+#define BIT_MASK_PKTLEN_PARA 0x7
+#define BIT_PKTLEN_PARA(x)                                                     \
+	(((x) & BIT_MASK_PKTLEN_PARA) << BIT_SHIFT_PKTLEN_PARA)
+#define BITS_PKTLEN_PARA (BIT_MASK_PKTLEN_PARA << BIT_SHIFT_PKTLEN_PARA)
+#define BIT_CLEAR_PKTLEN_PARA(x) ((x) & (~BITS_PKTLEN_PARA))
+#define BIT_GET_PKTLEN_PARA(x)                                                 \
+	(((x) >> BIT_SHIFT_PKTLEN_PARA) & BIT_MASK_PKTLEN_PARA)
+#define BIT_SET_PKTLEN_PARA(x, v)                                              \
+	(BIT_CLEAR_PKTLEN_PARA(x) | BIT_PKTLEN_PARA(v))
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+/* 2 REG_RXDMA_MODE				(Offset 0x0290) */
+
+#define BIT_EN_SDIO_FAIL BIT(9)
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_RXDMA_MODE				(Offset 0x0290) */
+
+#define BIT_GRAYCODE_SYNC_WITH_BIN BIT(8)
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+/* 2 REG_RXDMA_MODE				(Offset 0x0290) */
+
+#define BIT_RXDMA_DBD_SEL BIT(7)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_RXDMA_MODE				(Offset 0x0290) */
+
+#define BIT_RX_DBG_SEL BIT(7)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_RXDMA_MODE				(Offset 0x0290) */
+
+#define BIT_EN_SPD BIT(6)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_RXDMA_MODE				(Offset 0x0290) */
+
+#define BIT_SHIFT_BURST_SIZE 4
+#define BIT_MASK_BURST_SIZE 0x3
+#define BIT_BURST_SIZE(x) (((x) & BIT_MASK_BURST_SIZE) << BIT_SHIFT_BURST_SIZE)
+#define BITS_BURST_SIZE (BIT_MASK_BURST_SIZE << BIT_SHIFT_BURST_SIZE)
+#define BIT_CLEAR_BURST_SIZE(x) ((x) & (~BITS_BURST_SIZE))
+#define BIT_GET_BURST_SIZE(x)                                                  \
+	(((x) >> BIT_SHIFT_BURST_SIZE) & BIT_MASK_BURST_SIZE)
+#define BIT_SET_BURST_SIZE(x, v) (BIT_CLEAR_BURST_SIZE(x) | BIT_BURST_SIZE(v))
+
+#define BIT_SHIFT_BURST_CNT 2
+#define BIT_MASK_BURST_CNT 0x3
+#define BIT_BURST_CNT(x) (((x) & BIT_MASK_BURST_CNT) << BIT_SHIFT_BURST_CNT)
+#define BITS_BURST_CNT (BIT_MASK_BURST_CNT << BIT_SHIFT_BURST_CNT)
+#define BIT_CLEAR_BURST_CNT(x) ((x) & (~BITS_BURST_CNT))
+#define BIT_GET_BURST_CNT(x) (((x) >> BIT_SHIFT_BURST_CNT) & BIT_MASK_BURST_CNT)
+#define BIT_SET_BURST_CNT(x, v) (BIT_CLEAR_BURST_CNT(x) | BIT_BURST_CNT(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_RXDMA_MODE				(Offset 0x0290) */
+
+#define BIT_DAM_MODE BIT(1)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_RXDMA_MODE				(Offset 0x0290) */
+
+#define BIT_DMA_MODE BIT(1)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_C2H_PKT				(Offset 0x0294) */
+
+#define BIT_SHIFT_R_C2H_STR_ADDR_16_TO_19 24
+#define BIT_MASK_R_C2H_STR_ADDR_16_TO_19 0xf
+#define BIT_R_C2H_STR_ADDR_16_TO_19(x)                                         \
+	(((x) & BIT_MASK_R_C2H_STR_ADDR_16_TO_19)                              \
+	 << BIT_SHIFT_R_C2H_STR_ADDR_16_TO_19)
+#define BITS_R_C2H_STR_ADDR_16_TO_19                                           \
+	(BIT_MASK_R_C2H_STR_ADDR_16_TO_19 << BIT_SHIFT_R_C2H_STR_ADDR_16_TO_19)
+#define BIT_CLEAR_R_C2H_STR_ADDR_16_TO_19(x)                                   \
+	((x) & (~BITS_R_C2H_STR_ADDR_16_TO_19))
+#define BIT_GET_R_C2H_STR_ADDR_16_TO_19(x)                                     \
+	(((x) >> BIT_SHIFT_R_C2H_STR_ADDR_16_TO_19) &                          \
+	 BIT_MASK_R_C2H_STR_ADDR_16_TO_19)
+#define BIT_SET_R_C2H_STR_ADDR_16_TO_19(x, v)                                  \
+	(BIT_CLEAR_R_C2H_STR_ADDR_16_TO_19(x) | BIT_R_C2H_STR_ADDR_16_TO_19(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_C2H_PKT				(Offset 0x0294) */
+
+#define BIT_R_C2H_PKT_REQ BIT(16)
+
+#define BIT_SHIFT_R_C2H_STR_ADDR 0
+#define BIT_MASK_R_C2H_STR_ADDR 0xffff
+#define BIT_R_C2H_STR_ADDR(x)                                                  \
+	(((x) & BIT_MASK_R_C2H_STR_ADDR) << BIT_SHIFT_R_C2H_STR_ADDR)
+#define BITS_R_C2H_STR_ADDR                                                    \
+	(BIT_MASK_R_C2H_STR_ADDR << BIT_SHIFT_R_C2H_STR_ADDR)
+#define BIT_CLEAR_R_C2H_STR_ADDR(x) ((x) & (~BITS_R_C2H_STR_ADDR))
+#define BIT_GET_R_C2H_STR_ADDR(x)                                              \
+	(((x) >> BIT_SHIFT_R_C2H_STR_ADDR) & BIT_MASK_R_C2H_STR_ADDR)
+#define BIT_SET_R_C2H_STR_ADDR(x, v)                                           \
+	(BIT_CLEAR_R_C2H_STR_ADDR(x) | BIT_R_C2H_STR_ADDR(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FWFF_C2H				(Offset 0x0298) */
+
+#define BIT_SHIFT_C2H_DMA_ADDR 0
+#define BIT_MASK_C2H_DMA_ADDR 0x3ffff
+#define BIT_C2H_DMA_ADDR(x)                                                    \
+	(((x) & BIT_MASK_C2H_DMA_ADDR) << BIT_SHIFT_C2H_DMA_ADDR)
+#define BITS_C2H_DMA_ADDR (BIT_MASK_C2H_DMA_ADDR << BIT_SHIFT_C2H_DMA_ADDR)
+#define BIT_CLEAR_C2H_DMA_ADDR(x) ((x) & (~BITS_C2H_DMA_ADDR))
+#define BIT_GET_C2H_DMA_ADDR(x)                                                \
+	(((x) >> BIT_SHIFT_C2H_DMA_ADDR) & BIT_MASK_C2H_DMA_ADDR)
+#define BIT_SET_C2H_DMA_ADDR(x, v)                                             \
+	(BIT_CLEAR_C2H_DMA_ADDR(x) | BIT_C2H_DMA_ADDR(v))
+
+/* 2 REG_FWFF_CTRL				(Offset 0x029C) */
+
+#define BIT_FWFF_DMAPKT_REQ BIT(31)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FWFF_CTRL				(Offset 0x029C) */
+
+#define BIT_SHIFT_FWFF_DMA_PKT_NUM 16
+#define BIT_MASK_FWFF_DMA_PKT_NUM 0xff
+#define BIT_FWFF_DMA_PKT_NUM(x)                                                \
+	(((x) & BIT_MASK_FWFF_DMA_PKT_NUM) << BIT_SHIFT_FWFF_DMA_PKT_NUM)
+#define BITS_FWFF_DMA_PKT_NUM                                                  \
+	(BIT_MASK_FWFF_DMA_PKT_NUM << BIT_SHIFT_FWFF_DMA_PKT_NUM)
+#define BIT_CLEAR_FWFF_DMA_PKT_NUM(x) ((x) & (~BITS_FWFF_DMA_PKT_NUM))
+#define BIT_GET_FWFF_DMA_PKT_NUM(x)                                            \
+	(((x) >> BIT_SHIFT_FWFF_DMA_PKT_NUM) & BIT_MASK_FWFF_DMA_PKT_NUM)
+#define BIT_SET_FWFF_DMA_PKT_NUM(x, v)                                         \
+	(BIT_CLEAR_FWFF_DMA_PKT_NUM(x) | BIT_FWFF_DMA_PKT_NUM(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_FWFF_CTRL				(Offset 0x029C) */
+
+#define BIT_SHIFT_FWFF_DMA_PKT_NUM_V1 16
+#define BIT_MASK_FWFF_DMA_PKT_NUM_V1 0x7fff
+#define BIT_FWFF_DMA_PKT_NUM_V1(x)                                             \
+	(((x) & BIT_MASK_FWFF_DMA_PKT_NUM_V1) << BIT_SHIFT_FWFF_DMA_PKT_NUM_V1)
+#define BITS_FWFF_DMA_PKT_NUM_V1                                               \
+	(BIT_MASK_FWFF_DMA_PKT_NUM_V1 << BIT_SHIFT_FWFF_DMA_PKT_NUM_V1)
+#define BIT_CLEAR_FWFF_DMA_PKT_NUM_V1(x) ((x) & (~BITS_FWFF_DMA_PKT_NUM_V1))
+#define BIT_GET_FWFF_DMA_PKT_NUM_V1(x)                                         \
+	(((x) >> BIT_SHIFT_FWFF_DMA_PKT_NUM_V1) & BIT_MASK_FWFF_DMA_PKT_NUM_V1)
+#define BIT_SET_FWFF_DMA_PKT_NUM_V1(x, v)                                      \
+	(BIT_CLEAR_FWFF_DMA_PKT_NUM_V1(x) | BIT_FWFF_DMA_PKT_NUM_V1(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FWFF_CTRL				(Offset 0x029C) */
+
+#define BIT_SHIFT_FWFF_STR_ADDR 0
+#define BIT_MASK_FWFF_STR_ADDR 0xffff
+#define BIT_FWFF_STR_ADDR(x)                                                   \
+	(((x) & BIT_MASK_FWFF_STR_ADDR) << BIT_SHIFT_FWFF_STR_ADDR)
+#define BITS_FWFF_STR_ADDR (BIT_MASK_FWFF_STR_ADDR << BIT_SHIFT_FWFF_STR_ADDR)
+#define BIT_CLEAR_FWFF_STR_ADDR(x) ((x) & (~BITS_FWFF_STR_ADDR))
+#define BIT_GET_FWFF_STR_ADDR(x)                                               \
+	(((x) >> BIT_SHIFT_FWFF_STR_ADDR) & BIT_MASK_FWFF_STR_ADDR)
+#define BIT_SET_FWFF_STR_ADDR(x, v)                                            \
+	(BIT_CLEAR_FWFF_STR_ADDR(x) | BIT_FWFF_STR_ADDR(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FWFF_PKT_INFO			(Offset 0x02A0) */
+
+#define BIT_SHIFT_FWFF_PKT_QUEUED 16
+#define BIT_MASK_FWFF_PKT_QUEUED 0xff
+#define BIT_FWFF_PKT_QUEUED(x)                                                 \
+	(((x) & BIT_MASK_FWFF_PKT_QUEUED) << BIT_SHIFT_FWFF_PKT_QUEUED)
+#define BITS_FWFF_PKT_QUEUED                                                   \
+	(BIT_MASK_FWFF_PKT_QUEUED << BIT_SHIFT_FWFF_PKT_QUEUED)
+#define BIT_CLEAR_FWFF_PKT_QUEUED(x) ((x) & (~BITS_FWFF_PKT_QUEUED))
+#define BIT_GET_FWFF_PKT_QUEUED(x)                                             \
+	(((x) >> BIT_SHIFT_FWFF_PKT_QUEUED) & BIT_MASK_FWFF_PKT_QUEUED)
+#define BIT_SET_FWFF_PKT_QUEUED(x, v)                                          \
+	(BIT_CLEAR_FWFF_PKT_QUEUED(x) | BIT_FWFF_PKT_QUEUED(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_FWFF_PKT_INFO			(Offset 0x02A0) */
+
+#define BIT_SHIFT_FWFF_PKT_READ_ADDR 16
+#define BIT_MASK_FWFF_PKT_READ_ADDR 0xffff
+#define BIT_FWFF_PKT_READ_ADDR(x)                                              \
+	(((x) & BIT_MASK_FWFF_PKT_READ_ADDR) << BIT_SHIFT_FWFF_PKT_READ_ADDR)
+#define BITS_FWFF_PKT_READ_ADDR                                                \
+	(BIT_MASK_FWFF_PKT_READ_ADDR << BIT_SHIFT_FWFF_PKT_READ_ADDR)
+#define BIT_CLEAR_FWFF_PKT_READ_ADDR(x) ((x) & (~BITS_FWFF_PKT_READ_ADDR))
+#define BIT_GET_FWFF_PKT_READ_ADDR(x)                                          \
+	(((x) >> BIT_SHIFT_FWFF_PKT_READ_ADDR) & BIT_MASK_FWFF_PKT_READ_ADDR)
+#define BIT_SET_FWFF_PKT_READ_ADDR(x, v)                                       \
+	(BIT_CLEAR_FWFF_PKT_READ_ADDR(x) | BIT_FWFF_PKT_READ_ADDR(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+
+/* 2 REG_FWFF_PKT_INFO			(Offset 0x02A0) */
+
+#define BIT_SHIFT_FWFF_PKT_STR_ADDR 0
+#define BIT_MASK_FWFF_PKT_STR_ADDR 0xffff
+#define BIT_FWFF_PKT_STR_ADDR(x)                                               \
+	(((x) & BIT_MASK_FWFF_PKT_STR_ADDR) << BIT_SHIFT_FWFF_PKT_STR_ADDR)
+#define BITS_FWFF_PKT_STR_ADDR                                                 \
+	(BIT_MASK_FWFF_PKT_STR_ADDR << BIT_SHIFT_FWFF_PKT_STR_ADDR)
+#define BIT_CLEAR_FWFF_PKT_STR_ADDR(x) ((x) & (~BITS_FWFF_PKT_STR_ADDR))
+#define BIT_GET_FWFF_PKT_STR_ADDR(x)                                           \
+	(((x) >> BIT_SHIFT_FWFF_PKT_STR_ADDR) & BIT_MASK_FWFF_PKT_STR_ADDR)
+#define BIT_SET_FWFF_PKT_STR_ADDR(x, v)                                        \
+	(BIT_CLEAR_FWFF_PKT_STR_ADDR(x) | BIT_FWFF_PKT_STR_ADDR(v))
+
+#endif
+
+#if (HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_FWFF_PKT_INFO			(Offset 0x02A0) */
+
+#define BIT_SHIFT_FWFF_PKT_STR_ADDR_V1 0
+#define BIT_MASK_FWFF_PKT_STR_ADDR_V1 0x7ff
+#define BIT_FWFF_PKT_STR_ADDR_V1(x)                                            \
+	(((x) & BIT_MASK_FWFF_PKT_STR_ADDR_V1)                                 \
+	 << BIT_SHIFT_FWFF_PKT_STR_ADDR_V1)
+#define BITS_FWFF_PKT_STR_ADDR_V1                                              \
+	(BIT_MASK_FWFF_PKT_STR_ADDR_V1 << BIT_SHIFT_FWFF_PKT_STR_ADDR_V1)
+#define BIT_CLEAR_FWFF_PKT_STR_ADDR_V1(x) ((x) & (~BITS_FWFF_PKT_STR_ADDR_V1))
+#define BIT_GET_FWFF_PKT_STR_ADDR_V1(x)                                        \
+	(((x) >> BIT_SHIFT_FWFF_PKT_STR_ADDR_V1) &                             \
+	 BIT_MASK_FWFF_PKT_STR_ADDR_V1)
+#define BIT_SET_FWFF_PKT_STR_ADDR_V1(x, v)                                     \
+	(BIT_CLEAR_FWFF_PKT_STR_ADDR_V1(x) | BIT_FWFF_PKT_STR_ADDR_V1(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_FWFF_PKT_INFO			(Offset 0x02A0) */
+
+#define BIT_SHIFT_FWFF_PKT_WRITE_ADDR 0
+#define BIT_MASK_FWFF_PKT_WRITE_ADDR 0xffff
+#define BIT_FWFF_PKT_WRITE_ADDR(x)                                             \
+	(((x) & BIT_MASK_FWFF_PKT_WRITE_ADDR) << BIT_SHIFT_FWFF_PKT_WRITE_ADDR)
+#define BITS_FWFF_PKT_WRITE_ADDR                                               \
+	(BIT_MASK_FWFF_PKT_WRITE_ADDR << BIT_SHIFT_FWFF_PKT_WRITE_ADDR)
+#define BIT_CLEAR_FWFF_PKT_WRITE_ADDR(x) ((x) & (~BITS_FWFF_PKT_WRITE_ADDR))
+#define BIT_GET_FWFF_PKT_WRITE_ADDR(x)                                         \
+	(((x) >> BIT_SHIFT_FWFF_PKT_WRITE_ADDR) & BIT_MASK_FWFF_PKT_WRITE_ADDR)
+#define BIT_SET_FWFF_PKT_WRITE_ADDR(x, v)                                      \
+	(BIT_CLEAR_FWFF_PKT_WRITE_ADDR(x) | BIT_FWFF_PKT_WRITE_ADDR(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT)
+
+/* 2 REG_FC2H_INFO				(Offset 0x02A4) */
+
+#define BIT_FC2H_PKT_REQ BIT(16)
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+/* 2 REG_FC2H_INFO				(Offset 0x02A4) */
+
+#define BIT_FC2H_DMAPKT_REQ BIT(16)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_FC2H_INFO				(Offset 0x02A4) */
+
+#define BIT_SHIFT_FC2H_STR_ADDR 0
+#define BIT_MASK_FC2H_STR_ADDR 0xffff
+#define BIT_FC2H_STR_ADDR(x)                                                   \
+	(((x) & BIT_MASK_FC2H_STR_ADDR) << BIT_SHIFT_FC2H_STR_ADDR)
+#define BITS_FC2H_STR_ADDR (BIT_MASK_FC2H_STR_ADDR << BIT_SHIFT_FC2H_STR_ADDR)
+#define BIT_CLEAR_FC2H_STR_ADDR(x) ((x) & (~BITS_FC2H_STR_ADDR))
+#define BIT_GET_FC2H_STR_ADDR(x)                                               \
+	(((x) >> BIT_SHIFT_FC2H_STR_ADDR) & BIT_MASK_FC2H_STR_ADDR)
+#define BIT_SET_FC2H_STR_ADDR(x, v)                                            \
+	(BIT_CLEAR_FC2H_STR_ADDR(x) | BIT_FC2H_STR_ADDR(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_FWFF_PKT_INFO2			(Offset 0x02A4) */
+
+#define BIT_SHIFT_FWFF_PKT_QUEUED_V1 0
+#define BIT_MASK_FWFF_PKT_QUEUED_V1 0xffff
+#define BIT_FWFF_PKT_QUEUED_V1(x)                                              \
+	(((x) & BIT_MASK_FWFF_PKT_QUEUED_V1) << BIT_SHIFT_FWFF_PKT_QUEUED_V1)
+#define BITS_FWFF_PKT_QUEUED_V1                                                \
+	(BIT_MASK_FWFF_PKT_QUEUED_V1 << BIT_SHIFT_FWFF_PKT_QUEUED_V1)
+#define BIT_CLEAR_FWFF_PKT_QUEUED_V1(x) ((x) & (~BITS_FWFF_PKT_QUEUED_V1))
+#define BIT_GET_FWFF_PKT_QUEUED_V1(x)                                          \
+	(((x) >> BIT_SHIFT_FWFF_PKT_QUEUED_V1) & BIT_MASK_FWFF_PKT_QUEUED_V1)
+#define BIT_SET_FWFF_PKT_QUEUED_V1(x, v)                                       \
+	(BIT_CLEAR_FWFF_PKT_QUEUED_V1(x) | BIT_FWFF_PKT_QUEUED_V1(v))
+
+#define BIT_SHIFT_FW_UPD_RXDES_RD_PTR 0
+#define BIT_MASK_FW_UPD_RXDES_RD_PTR 0x3ffff
+#define BIT_FW_UPD_RXDES_RD_PTR(x)                                             \
+	(((x) & BIT_MASK_FW_UPD_RXDES_RD_PTR) << BIT_SHIFT_FW_UPD_RXDES_RD_PTR)
+#define BITS_FW_UPD_RXDES_RD_PTR                                               \
+	(BIT_MASK_FW_UPD_RXDES_RD_PTR << BIT_SHIFT_FW_UPD_RXDES_RD_PTR)
+#define BIT_CLEAR_FW_UPD_RXDES_RD_PTR(x) ((x) & (~BITS_FW_UPD_RXDES_RD_PTR))
+#define BIT_GET_FW_UPD_RXDES_RD_PTR(x)                                         \
+	(((x) >> BIT_SHIFT_FW_UPD_RXDES_RD_PTR) & BIT_MASK_FW_UPD_RXDES_RD_PTR)
+#define BIT_SET_FW_UPD_RXDES_RD_PTR(x, v)                                      \
+	(BIT_CLEAR_FW_UPD_RXDES_RD_PTR(x) | BIT_FW_UPD_RXDES_RD_PTR(v))
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_RXPKTNUM				(Offset 0x02B0) */
+
+#define BIT_SHIFT_PKT_NUM_WOL_V1 16
+#define BIT_MASK_PKT_NUM_WOL_V1 0xffff
+#define BIT_PKT_NUM_WOL_V1(x)                                                  \
+	(((x) & BIT_MASK_PKT_NUM_WOL_V1) << BIT_SHIFT_PKT_NUM_WOL_V1)
+#define BITS_PKT_NUM_WOL_V1                                                    \
+	(BIT_MASK_PKT_NUM_WOL_V1 << BIT_SHIFT_PKT_NUM_WOL_V1)
+#define BIT_CLEAR_PKT_NUM_WOL_V1(x) ((x) & (~BITS_PKT_NUM_WOL_V1))
+#define BIT_GET_PKT_NUM_WOL_V1(x)                                              \
+	(((x) >> BIT_SHIFT_PKT_NUM_WOL_V1) & BIT_MASK_PKT_NUM_WOL_V1)
+#define BIT_SET_PKT_NUM_WOL_V1(x, v)                                           \
+	(BIT_CLEAR_PKT_NUM_WOL_V1(x) | BIT_PKT_NUM_WOL_V1(v))
+
+#define BIT_SHIFT_RXPKT_NUM_V1 0
+#define BIT_MASK_RXPKT_NUM_V1 0xffff
+#define BIT_RXPKT_NUM_V1(x)                                                    \
+	(((x) & BIT_MASK_RXPKT_NUM_V1) << BIT_SHIFT_RXPKT_NUM_V1)
+#define BITS_RXPKT_NUM_V1 (BIT_MASK_RXPKT_NUM_V1 << BIT_SHIFT_RXPKT_NUM_V1)
+#define BIT_CLEAR_RXPKT_NUM_V1(x) ((x) & (~BITS_RXPKT_NUM_V1))
+#define BIT_GET_RXPKT_NUM_V1(x)                                                \
+	(((x) >> BIT_SHIFT_RXPKT_NUM_V1) & BIT_MASK_RXPKT_NUM_V1)
+#define BIT_SET_RXPKT_NUM_V1(x, v)                                             \
+	(BIT_CLEAR_RXPKT_NUM_V1(x) | BIT_RXPKT_NUM_V1(v))
+
+#define BIT_SHIFT_RXPKT_NUM_TH 0
+#define BIT_MASK_RXPKT_NUM_TH 0xff
+#define BIT_RXPKT_NUM_TH(x)                                                    \
+	(((x) & BIT_MASK_RXPKT_NUM_TH) << BIT_SHIFT_RXPKT_NUM_TH)
+#define BITS_RXPKT_NUM_TH (BIT_MASK_RXPKT_NUM_TH << BIT_SHIFT_RXPKT_NUM_TH)
+#define BIT_CLEAR_RXPKT_NUM_TH(x) ((x) & (~BITS_RXPKT_NUM_TH))
+#define BIT_GET_RXPKT_NUM_TH(x)                                                \
+	(((x) >> BIT_SHIFT_RXPKT_NUM_TH) & BIT_MASK_RXPKT_NUM_TH)
+#define BIT_SET_RXPKT_NUM_TH(x, v)                                             \
+	(BIT_CLEAR_RXPKT_NUM_TH(x) | BIT_RXPKT_NUM_TH(v))
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FW_MSG1				(Offset 0x02E0) */
+
+#define BIT_SHIFT_FW_MSG_REG1 0
+#define BIT_MASK_FW_MSG_REG1 0xffffffffL
+#define BIT_FW_MSG_REG1(x)                                                     \
+	(((x) & BIT_MASK_FW_MSG_REG1) << BIT_SHIFT_FW_MSG_REG1)
+#define BITS_FW_MSG_REG1 (BIT_MASK_FW_MSG_REG1 << BIT_SHIFT_FW_MSG_REG1)
+#define BIT_CLEAR_FW_MSG_REG1(x) ((x) & (~BITS_FW_MSG_REG1))
+#define BIT_GET_FW_MSG_REG1(x)                                                 \
+	(((x) >> BIT_SHIFT_FW_MSG_REG1) & BIT_MASK_FW_MSG_REG1)
+#define BIT_SET_FW_MSG_REG1(x, v)                                              \
+	(BIT_CLEAR_FW_MSG_REG1(x) | BIT_FW_MSG_REG1(v))
+
+/* 2 REG_FW_MSG2				(Offset 0x02E4) */
+
+#define BIT_SHIFT_FW_MSG_REG2 0
+#define BIT_MASK_FW_MSG_REG2 0xffffffffL
+#define BIT_FW_MSG_REG2(x)                                                     \
+	(((x) & BIT_MASK_FW_MSG_REG2) << BIT_SHIFT_FW_MSG_REG2)
+#define BITS_FW_MSG_REG2 (BIT_MASK_FW_MSG_REG2 << BIT_SHIFT_FW_MSG_REG2)
+#define BIT_CLEAR_FW_MSG_REG2(x) ((x) & (~BITS_FW_MSG_REG2))
+#define BIT_GET_FW_MSG_REG2(x)                                                 \
+	(((x) >> BIT_SHIFT_FW_MSG_REG2) & BIT_MASK_FW_MSG_REG2)
+#define BIT_SET_FW_MSG_REG2(x, v)                                              \
+	(BIT_CLEAR_FW_MSG_REG2(x) | BIT_FW_MSG_REG2(v))
+
+/* 2 REG_FW_MSG3				(Offset 0x02E8) */
+
+#define BIT_SHIFT_FW_MSG_REG3 0
+#define BIT_MASK_FW_MSG_REG3 0xffffffffL
+#define BIT_FW_MSG_REG3(x)                                                     \
+	(((x) & BIT_MASK_FW_MSG_REG3) << BIT_SHIFT_FW_MSG_REG3)
+#define BITS_FW_MSG_REG3 (BIT_MASK_FW_MSG_REG3 << BIT_SHIFT_FW_MSG_REG3)
+#define BIT_CLEAR_FW_MSG_REG3(x) ((x) & (~BITS_FW_MSG_REG3))
+#define BIT_GET_FW_MSG_REG3(x)                                                 \
+	(((x) >> BIT_SHIFT_FW_MSG_REG3) & BIT_MASK_FW_MSG_REG3)
+#define BIT_SET_FW_MSG_REG3(x, v)                                              \
+	(BIT_CLEAR_FW_MSG_REG3(x) | BIT_FW_MSG_REG3(v))
+
+/* 2 REG_FW_MSG4				(Offset 0x02EC) */
+
+#define BIT_SHIFT_FW_MSG_REG4 0
+#define BIT_MASK_FW_MSG_REG4 0xffffffffL
+#define BIT_FW_MSG_REG4(x)                                                     \
+	(((x) & BIT_MASK_FW_MSG_REG4) << BIT_SHIFT_FW_MSG_REG4)
+#define BITS_FW_MSG_REG4 (BIT_MASK_FW_MSG_REG4 << BIT_SHIFT_FW_MSG_REG4)
+#define BIT_CLEAR_FW_MSG_REG4(x) ((x) & (~BITS_FW_MSG_REG4))
+#define BIT_GET_FW_MSG_REG4(x)                                                 \
+	(((x) >> BIT_SHIFT_FW_MSG_REG4) & BIT_MASK_FW_MSG_REG4)
+#define BIT_SET_FW_MSG_REG4(x, v)                                              \
+	(BIT_CLEAR_FW_MSG_REG4(x) | BIT_FW_MSG_REG4(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_PCIE_CTRL				(Offset 0x0300) */
+
+#define BIT_PCIEIO_PERSTB_SEL BIT(31)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_HCI_CTRL				(Offset 0x0300) */
+
+#define BIT_HCIIO_PERSTB_SEL BIT(31)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_PCIE_CTRL				(Offset 0x0300) */
+
+#define BIT_SHIFT_PCIE_MAX_RXDMA 28
+#define BIT_MASK_PCIE_MAX_RXDMA 0x7
+#define BIT_PCIE_MAX_RXDMA(x)                                                  \
+	(((x) & BIT_MASK_PCIE_MAX_RXDMA) << BIT_SHIFT_PCIE_MAX_RXDMA)
+#define BITS_PCIE_MAX_RXDMA                                                    \
+	(BIT_MASK_PCIE_MAX_RXDMA << BIT_SHIFT_PCIE_MAX_RXDMA)
+#define BIT_CLEAR_PCIE_MAX_RXDMA(x) ((x) & (~BITS_PCIE_MAX_RXDMA))
+#define BIT_GET_PCIE_MAX_RXDMA(x)                                              \
+	(((x) >> BIT_SHIFT_PCIE_MAX_RXDMA) & BIT_MASK_PCIE_MAX_RXDMA)
+#define BIT_SET_PCIE_MAX_RXDMA(x, v)                                           \
+	(BIT_CLEAR_PCIE_MAX_RXDMA(x) | BIT_PCIE_MAX_RXDMA(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_HCI_CTRL				(Offset 0x0300) */
+
+#define BIT_SHIFT_HCI_MAX_RXDMA 28
+#define BIT_MASK_HCI_MAX_RXDMA 0x7
+#define BIT_HCI_MAX_RXDMA(x)                                                   \
+	(((x) & BIT_MASK_HCI_MAX_RXDMA) << BIT_SHIFT_HCI_MAX_RXDMA)
+#define BITS_HCI_MAX_RXDMA (BIT_MASK_HCI_MAX_RXDMA << BIT_SHIFT_HCI_MAX_RXDMA)
+#define BIT_CLEAR_HCI_MAX_RXDMA(x) ((x) & (~BITS_HCI_MAX_RXDMA))
+#define BIT_GET_HCI_MAX_RXDMA(x)                                               \
+	(((x) >> BIT_SHIFT_HCI_MAX_RXDMA) & BIT_MASK_HCI_MAX_RXDMA)
+#define BIT_SET_HCI_MAX_RXDMA(x, v)                                            \
+	(BIT_CLEAR_HCI_MAX_RXDMA(x) | BIT_HCI_MAX_RXDMA(v))
+
+#endif
+
+#if (HALMAC_8881A_SUPPORT)
+
+/* 2 REG_LX_CTRL1				(Offset 0x0300) */
+
+#define BIT_RX_LIT_EDN_SEL BIT(27)
+#define BIT_TX_LIT_EDN_SEL BIT(26)
+#define BIT_WT_LIT_EDN BIT(25)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_PCIE_CTRL				(Offset 0x0300) */
+
+#define BIT_SHIFT_PCIE_MAX_TXDMA 24
+#define BIT_MASK_PCIE_MAX_TXDMA 0x7
+#define BIT_PCIE_MAX_TXDMA(x)                                                  \
+	(((x) & BIT_MASK_PCIE_MAX_TXDMA) << BIT_SHIFT_PCIE_MAX_TXDMA)
+#define BITS_PCIE_MAX_TXDMA                                                    \
+	(BIT_MASK_PCIE_MAX_TXDMA << BIT_SHIFT_PCIE_MAX_TXDMA)
+#define BIT_CLEAR_PCIE_MAX_TXDMA(x) ((x) & (~BITS_PCIE_MAX_TXDMA))
+#define BIT_GET_PCIE_MAX_TXDMA(x)                                              \
+	(((x) >> BIT_SHIFT_PCIE_MAX_TXDMA) & BIT_MASK_PCIE_MAX_TXDMA)
+#define BIT_SET_PCIE_MAX_TXDMA(x, v)                                           \
+	(BIT_CLEAR_PCIE_MAX_TXDMA(x) | BIT_PCIE_MAX_TXDMA(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_HCI_CTRL				(Offset 0x0300) */
+
+#define BIT_SHIFT_HCI_MAX_TXDMA 24
+#define BIT_MASK_HCI_MAX_TXDMA 0x7
+#define BIT_HCI_MAX_TXDMA(x)                                                   \
+	(((x) & BIT_MASK_HCI_MAX_TXDMA) << BIT_SHIFT_HCI_MAX_TXDMA)
+#define BITS_HCI_MAX_TXDMA (BIT_MASK_HCI_MAX_TXDMA << BIT_SHIFT_HCI_MAX_TXDMA)
+#define BIT_CLEAR_HCI_MAX_TXDMA(x) ((x) & (~BITS_HCI_MAX_TXDMA))
+#define BIT_GET_HCI_MAX_TXDMA(x)                                               \
+	(((x) >> BIT_SHIFT_HCI_MAX_TXDMA) & BIT_MASK_HCI_MAX_TXDMA)
+#define BIT_SET_HCI_MAX_TXDMA(x, v)                                            \
+	(BIT_CLEAR_HCI_MAX_TXDMA(x) | BIT_HCI_MAX_TXDMA(v))
+
+#endif
+
+#if (HALMAC_8881A_SUPPORT)
+
+/* 2 REG_LX_CTRL1				(Offset 0x0300) */
+
+#define BIT_RD_LITT_EDN BIT(24)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_PCIE_CTRL				(Offset 0x0300) */
+
+#define BIT_PWR_SCALE_START_PS BIT(23)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_PCIE_CTRL				(Offset 0x0300) */
+
+#define BIT_PCIE_RST_TRXDMA_INTF BIT(20)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_HCI_CTRL				(Offset 0x0300) */
+
+#define BIT_HCI_RST_TRXDMA_INTF BIT(20)
+
+#endif
+
+#if (HALMAC_8881A_SUPPORT)
+
+/* 2 REG_LX_CTRL1				(Offset 0x0300) */
+
+#define BIT_SHIFT_MAX_RXDMA 20
+#define BIT_MASK_MAX_RXDMA 0x7
+#define BIT_MAX_RXDMA(x) (((x) & BIT_MASK_MAX_RXDMA) << BIT_SHIFT_MAX_RXDMA)
+#define BITS_MAX_RXDMA (BIT_MASK_MAX_RXDMA << BIT_SHIFT_MAX_RXDMA)
+#define BIT_CLEAR_MAX_RXDMA(x) ((x) & (~BITS_MAX_RXDMA))
+#define BIT_GET_MAX_RXDMA(x) (((x) >> BIT_SHIFT_MAX_RXDMA) & BIT_MASK_MAX_RXDMA)
+#define BIT_SET_MAX_RXDMA(x, v) (BIT_CLEAR_MAX_RXDMA(x) | BIT_MAX_RXDMA(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_PCIE_CTRL				(Offset 0x0300) */
+
+#define BIT_PCIE_EN_SWENT_L23 BIT(17)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_HCI_CTRL				(Offset 0x0300) */
+
+#define BIT_HCI_EN_SWENT_L23 BIT(17)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_PCIE_CTRL				(Offset 0x0300) */
+
+#define BIT_PCIE_EN_HWEXT_L1 BIT(16)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_HCI_CTRL				(Offset 0x0300) */
+
+#define BIT_HCI_EN_HWEXT_L1 BIT(16)
+
+#endif
+
+#if (HALMAC_8881A_SUPPORT)
+
+/* 2 REG_LX_CTRL1				(Offset 0x0300) */
+
+#define BIT_SHIFT_MAX_TXDMA 16
+#define BIT_MASK_MAX_TXDMA 0x7
+#define BIT_MAX_TXDMA(x) (((x) & BIT_MASK_MAX_TXDMA) << BIT_SHIFT_MAX_TXDMA)
+#define BITS_MAX_TXDMA (BIT_MASK_MAX_TXDMA << BIT_SHIFT_MAX_TXDMA)
+#define BIT_CLEAR_MAX_TXDMA(x) ((x) & (~BITS_MAX_TXDMA))
+#define BIT_GET_MAX_TXDMA(x) (((x) >> BIT_SHIFT_MAX_TXDMA) & BIT_MASK_MAX_TXDMA)
+#define BIT_SET_MAX_TXDMA(x, v) (BIT_CLEAR_MAX_TXDMA(x) | BIT_MAX_TXDMA(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_PCIE_CTRL				(Offset 0x0300) */
+
+#define BIT_STOP_P0_MPRT_BCNQ4 BIT(6)
+#define BIT_STOP_P0_MPRT_BCNQ3 BIT(4)
+#define BIT_STOP_P0_MPRT_BCNQ2 BIT(2)
+#define BIT_STOP_P0_MPRT_BCNQ1 BIT(0)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8881A_SUPPORT)
+
+/* 2 REG_INT_MIG				(Offset 0x0304) */
+
+#define BIT_SHIFT_TXTTIMER_MATCH_NUM 28
+#define BIT_MASK_TXTTIMER_MATCH_NUM 0xf
+#define BIT_TXTTIMER_MATCH_NUM(x)                                              \
+	(((x) & BIT_MASK_TXTTIMER_MATCH_NUM) << BIT_SHIFT_TXTTIMER_MATCH_NUM)
+#define BITS_TXTTIMER_MATCH_NUM                                                \
+	(BIT_MASK_TXTTIMER_MATCH_NUM << BIT_SHIFT_TXTTIMER_MATCH_NUM)
+#define BIT_CLEAR_TXTTIMER_MATCH_NUM(x) ((x) & (~BITS_TXTTIMER_MATCH_NUM))
+#define BIT_GET_TXTTIMER_MATCH_NUM(x)                                          \
+	(((x) >> BIT_SHIFT_TXTTIMER_MATCH_NUM) & BIT_MASK_TXTTIMER_MATCH_NUM)
+#define BIT_SET_TXTTIMER_MATCH_NUM(x, v)                                       \
+	(BIT_CLEAR_TXTTIMER_MATCH_NUM(x) | BIT_TXTTIMER_MATCH_NUM(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_ACH_CTRL				(Offset 0x0304) */
+
+#define BIT_STOP_P0HIQ19 BIT(27)
+#define BIT_STOP_P0HIQ18 BIT(26)
+#define BIT_STOP_P0HIQ17 BIT(25)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8881A_SUPPORT)
+
+/* 2 REG_INT_MIG				(Offset 0x0304) */
+
+#define BIT_SHIFT_TXPKT_NUM_MATCH 24
+#define BIT_MASK_TXPKT_NUM_MATCH 0xf
+#define BIT_TXPKT_NUM_MATCH(x)                                                 \
+	(((x) & BIT_MASK_TXPKT_NUM_MATCH) << BIT_SHIFT_TXPKT_NUM_MATCH)
+#define BITS_TXPKT_NUM_MATCH                                                   \
+	(BIT_MASK_TXPKT_NUM_MATCH << BIT_SHIFT_TXPKT_NUM_MATCH)
+#define BIT_CLEAR_TXPKT_NUM_MATCH(x) ((x) & (~BITS_TXPKT_NUM_MATCH))
+#define BIT_GET_TXPKT_NUM_MATCH(x)                                             \
+	(((x) >> BIT_SHIFT_TXPKT_NUM_MATCH) & BIT_MASK_TXPKT_NUM_MATCH)
+#define BIT_SET_TXPKT_NUM_MATCH(x, v)                                          \
+	(BIT_CLEAR_TXPKT_NUM_MATCH(x) | BIT_TXPKT_NUM_MATCH(v))
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_INT_MIG				(Offset 0x0304) */
+
+#define BIT_SHIFT_TRXCOUNTER_MATCH 24
+#define BIT_MASK_TRXCOUNTER_MATCH 0xff
+#define BIT_TRXCOUNTER_MATCH(x)                                                \
+	(((x) & BIT_MASK_TRXCOUNTER_MATCH) << BIT_SHIFT_TRXCOUNTER_MATCH)
+#define BITS_TRXCOUNTER_MATCH                                                  \
+	(BIT_MASK_TRXCOUNTER_MATCH << BIT_SHIFT_TRXCOUNTER_MATCH)
+#define BIT_CLEAR_TRXCOUNTER_MATCH(x) ((x) & (~BITS_TRXCOUNTER_MATCH))
+#define BIT_GET_TRXCOUNTER_MATCH(x)                                            \
+	(((x) >> BIT_SHIFT_TRXCOUNTER_MATCH) & BIT_MASK_TRXCOUNTER_MATCH)
+#define BIT_SET_TRXCOUNTER_MATCH(x, v)                                         \
+	(BIT_CLEAR_TRXCOUNTER_MATCH(x) | BIT_TRXCOUNTER_MATCH(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_ACH_CTRL				(Offset 0x0304) */
+
+#define BIT_STOP_P0HIQ16 BIT(24)
+#define BIT_RX_CLOSE_EN_V1 BIT(21)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8881A_SUPPORT)
+
+/* 2 REG_INT_MIG				(Offset 0x0304) */
+
+#define BIT_SHIFT_RXTTIMER_MATCH_NUM 20
+#define BIT_MASK_RXTTIMER_MATCH_NUM 0xf
+#define BIT_RXTTIMER_MATCH_NUM(x)                                              \
+	(((x) & BIT_MASK_RXTTIMER_MATCH_NUM) << BIT_SHIFT_RXTTIMER_MATCH_NUM)
+#define BITS_RXTTIMER_MATCH_NUM                                                \
+	(BIT_MASK_RXTTIMER_MATCH_NUM << BIT_SHIFT_RXTTIMER_MATCH_NUM)
+#define BIT_CLEAR_RXTTIMER_MATCH_NUM(x) ((x) & (~BITS_RXTTIMER_MATCH_NUM))
+#define BIT_GET_RXTTIMER_MATCH_NUM(x)                                          \
+	(((x) >> BIT_SHIFT_RXTTIMER_MATCH_NUM) & BIT_MASK_RXTTIMER_MATCH_NUM)
+#define BIT_SET_RXTTIMER_MATCH_NUM(x, v)                                       \
+	(BIT_CLEAR_RXTTIMER_MATCH_NUM(x) | BIT_RXTTIMER_MATCH_NUM(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_ACH_CTRL				(Offset 0x0304) */
+
+#define BIT_STOP_FWCMDQ BIT(20)
+#define BIT_STOP_P0BCNQ BIT(18)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8881A_SUPPORT)
+
+/* 2 REG_INT_MIG				(Offset 0x0304) */
+
+#define BIT_SHIFT_RXPKT_NUM_MATCH 16
+#define BIT_MASK_RXPKT_NUM_MATCH 0xf
+#define BIT_RXPKT_NUM_MATCH(x)                                                 \
+	(((x) & BIT_MASK_RXPKT_NUM_MATCH) << BIT_SHIFT_RXPKT_NUM_MATCH)
+#define BITS_RXPKT_NUM_MATCH                                                   \
+	(BIT_MASK_RXPKT_NUM_MATCH << BIT_SHIFT_RXPKT_NUM_MATCH)
+#define BIT_CLEAR_RXPKT_NUM_MATCH(x) ((x) & (~BITS_RXPKT_NUM_MATCH))
+#define BIT_GET_RXPKT_NUM_MATCH(x)                                             \
+	(((x) >> BIT_SHIFT_RXPKT_NUM_MATCH) & BIT_MASK_RXPKT_NUM_MATCH)
+#define BIT_SET_RXPKT_NUM_MATCH(x, v)                                          \
+	(BIT_CLEAR_RXPKT_NUM_MATCH(x) | BIT_RXPKT_NUM_MATCH(v))
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_INT_MIG				(Offset 0x0304) */
+
+#define BIT_SHIFT_TRXTIMER_MATCH 16
+#define BIT_MASK_TRXTIMER_MATCH 0xff
+#define BIT_TRXTIMER_MATCH(x)                                                  \
+	(((x) & BIT_MASK_TRXTIMER_MATCH) << BIT_SHIFT_TRXTIMER_MATCH)
+#define BITS_TRXTIMER_MATCH                                                    \
+	(BIT_MASK_TRXTIMER_MATCH << BIT_SHIFT_TRXTIMER_MATCH)
+#define BIT_CLEAR_TRXTIMER_MATCH(x) ((x) & (~BITS_TRXTIMER_MATCH))
+#define BIT_GET_TRXTIMER_MATCH(x)                                              \
+	(((x) >> BIT_SHIFT_TRXTIMER_MATCH) & BIT_MASK_TRXTIMER_MATCH)
+#define BIT_SET_TRXTIMER_MATCH(x, v)                                           \
+	(BIT_CLEAR_TRXTIMER_MATCH(x) | BIT_TRXTIMER_MATCH(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_ACH_CTRL				(Offset 0x0304) */
+
+#define BIT_STOP_P0MGQ BIT(16)
+#define BIT_STOP_ACH13 BIT(15)
+#define BIT_STOP_ACH12 BIT(14)
+#define BIT_STOP_ACH11 BIT(13)
+#define BIT_STOP_ACH10 BIT(12)
+#define BIT_STOP_ACH9 BIT(11)
+#define BIT_STOP_ACH8 BIT(10)
+#define BIT_STOP_ACH7 BIT(9)
+#define BIT_STOP_ACH6 BIT(8)
+#define BIT_STOP_ACH5 BIT(7)
+#define BIT_STOP_ACH4 BIT(6)
+#define BIT_STOP_ACH3 BIT(5)
+#define BIT_STOP_ACH2 BIT(4)
+#define BIT_STOP_ACH1 BIT(3)
+#define BIT_STOP_ACH0 BIT(2)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8881A_SUPPORT)
+
+/* 2 REG_INT_MIG				(Offset 0x0304) */
+
+#define BIT_SHIFT_MIGRATE_TIMER 0
+#define BIT_MASK_MIGRATE_TIMER 0xffff
+#define BIT_MIGRATE_TIMER(x)                                                   \
+	(((x) & BIT_MASK_MIGRATE_TIMER) << BIT_SHIFT_MIGRATE_TIMER)
+#define BITS_MIGRATE_TIMER (BIT_MASK_MIGRATE_TIMER << BIT_SHIFT_MIGRATE_TIMER)
+#define BIT_CLEAR_MIGRATE_TIMER(x) ((x) & (~BITS_MIGRATE_TIMER))
+#define BIT_GET_MIGRATE_TIMER(x)                                               \
+	(((x) >> BIT_SHIFT_MIGRATE_TIMER) & BIT_MASK_MIGRATE_TIMER)
+#define BIT_SET_MIGRATE_TIMER(x, v)                                            \
+	(BIT_CLEAR_MIGRATE_TIMER(x) | BIT_MIGRATE_TIMER(v))
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_INT_MIG				(Offset 0x0304) */
+
+#define BIT_SHIFT_TRXTIMER_UNIT 0
+#define BIT_MASK_TRXTIMER_UNIT 0x3
+#define BIT_TRXTIMER_UNIT(x)                                                   \
+	(((x) & BIT_MASK_TRXTIMER_UNIT) << BIT_SHIFT_TRXTIMER_UNIT)
+#define BITS_TRXTIMER_UNIT (BIT_MASK_TRXTIMER_UNIT << BIT_SHIFT_TRXTIMER_UNIT)
+#define BIT_CLEAR_TRXTIMER_UNIT(x) ((x) & (~BITS_TRXTIMER_UNIT))
+#define BIT_GET_TRXTIMER_UNIT(x)                                               \
+	(((x) >> BIT_SHIFT_TRXTIMER_UNIT) & BIT_MASK_TRXTIMER_UNIT)
+#define BIT_SET_TRXTIMER_UNIT(x, v)                                            \
+	(BIT_CLEAR_TRXTIMER_UNIT(x) | BIT_TRXTIMER_UNIT(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_ACH_CTRL				(Offset 0x0304) */
+
+#define BIT_STOP_P0RX BIT(0)
+
+/* 2 REG_HIQ_CTRL				(Offset 0x0308) */
+
+#define BIT_STOP_P0HIQ15 BIT(15)
+#define BIT_STOP_P0HIQ14 BIT(14)
+#define BIT_STOP_P0HIQ13 BIT(13)
+#define BIT_STOP_P0HIQ12 BIT(12)
+#define BIT_STOP_P0HIQ11 BIT(11)
+#define BIT_STOP_P0HIQ10 BIT(10)
+#define BIT_STOP_P0HIQ9 BIT(9)
+#define BIT_STOP_P0HIQ8 BIT(8)
+#define BIT_STOP_P0HIQ7 BIT(7)
+#define BIT_STOP_P0HIQ6 BIT(6)
+#define BIT_STOP_P0HIQ5 BIT(5)
+#define BIT_STOP_P0HIQ4 BIT(4)
+#define BIT_STOP_P0HIQ3 BIT(3)
+#define BIT_STOP_P0HIQ2 BIT(2)
+#define BIT_STOP_P0HIQ1 BIT(1)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_BCNQ_TXBD_DESA			(Offset 0x0308) */
+
+#define BIT_SHIFT_BCNQ_TXBD_DESA 0
+#define BIT_MASK_BCNQ_TXBD_DESA 0xffffffffffffffffL
+#define BIT_BCNQ_TXBD_DESA(x)                                                  \
+	(((x) & BIT_MASK_BCNQ_TXBD_DESA) << BIT_SHIFT_BCNQ_TXBD_DESA)
+#define BITS_BCNQ_TXBD_DESA                                                    \
+	(BIT_MASK_BCNQ_TXBD_DESA << BIT_SHIFT_BCNQ_TXBD_DESA)
+#define BIT_CLEAR_BCNQ_TXBD_DESA(x) ((x) & (~BITS_BCNQ_TXBD_DESA))
+#define BIT_GET_BCNQ_TXBD_DESA(x)                                              \
+	(((x) >> BIT_SHIFT_BCNQ_TXBD_DESA) & BIT_MASK_BCNQ_TXBD_DESA)
+#define BIT_SET_BCNQ_TXBD_DESA(x, v)                                           \
+	(BIT_CLEAR_BCNQ_TXBD_DESA(x) | BIT_BCNQ_TXBD_DESA(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_HIQ_CTRL				(Offset 0x0308) */
+
+#define BIT_STOP_P0HIQ0 BIT(0)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_MGQ_TXBD_DESA			(Offset 0x0310) */
+
+#define BIT_SHIFT_MGQ_TXBD_DESA 0
+#define BIT_MASK_MGQ_TXBD_DESA 0xffffffffffffffffL
+#define BIT_MGQ_TXBD_DESA(x)                                                   \
+	(((x) & BIT_MASK_MGQ_TXBD_DESA) << BIT_SHIFT_MGQ_TXBD_DESA)
+#define BITS_MGQ_TXBD_DESA (BIT_MASK_MGQ_TXBD_DESA << BIT_SHIFT_MGQ_TXBD_DESA)
+#define BIT_CLEAR_MGQ_TXBD_DESA(x) ((x) & (~BITS_MGQ_TXBD_DESA))
+#define BIT_GET_MGQ_TXBD_DESA(x)                                               \
+	(((x) >> BIT_SHIFT_MGQ_TXBD_DESA) & BIT_MASK_MGQ_TXBD_DESA)
+#define BIT_SET_MGQ_TXBD_DESA(x, v)                                            \
+	(BIT_CLEAR_MGQ_TXBD_DESA(x) | BIT_MGQ_TXBD_DESA(v))
+
+/* 2 REG_VOQ_TXBD_DESA			(Offset 0x0318) */
+
+#define BIT_SHIFT_VOQ_TXBD_DESA 0
+#define BIT_MASK_VOQ_TXBD_DESA 0xffffffffffffffffL
+#define BIT_VOQ_TXBD_DESA(x)                                                   \
+	(((x) & BIT_MASK_VOQ_TXBD_DESA) << BIT_SHIFT_VOQ_TXBD_DESA)
+#define BITS_VOQ_TXBD_DESA (BIT_MASK_VOQ_TXBD_DESA << BIT_SHIFT_VOQ_TXBD_DESA)
+#define BIT_CLEAR_VOQ_TXBD_DESA(x) ((x) & (~BITS_VOQ_TXBD_DESA))
+#define BIT_GET_VOQ_TXBD_DESA(x)                                               \
+	(((x) >> BIT_SHIFT_VOQ_TXBD_DESA) & BIT_MASK_VOQ_TXBD_DESA)
+#define BIT_SET_VOQ_TXBD_DESA(x, v)                                            \
+	(BIT_CLEAR_VOQ_TXBD_DESA(x) | BIT_VOQ_TXBD_DESA(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_ACH0_TXBD_DESA_L			(Offset 0x0318) */
+
+#define BIT_SHIFT_ACH0_TXBD_DESA_L 0
+#define BIT_MASK_ACH0_TXBD_DESA_L 0xffffffffL
+#define BIT_ACH0_TXBD_DESA_L(x)                                                \
+	(((x) & BIT_MASK_ACH0_TXBD_DESA_L) << BIT_SHIFT_ACH0_TXBD_DESA_L)
+#define BITS_ACH0_TXBD_DESA_L                                                  \
+	(BIT_MASK_ACH0_TXBD_DESA_L << BIT_SHIFT_ACH0_TXBD_DESA_L)
+#define BIT_CLEAR_ACH0_TXBD_DESA_L(x) ((x) & (~BITS_ACH0_TXBD_DESA_L))
+#define BIT_GET_ACH0_TXBD_DESA_L(x)                                            \
+	(((x) >> BIT_SHIFT_ACH0_TXBD_DESA_L) & BIT_MASK_ACH0_TXBD_DESA_L)
+#define BIT_SET_ACH0_TXBD_DESA_L(x, v)                                         \
+	(BIT_CLEAR_ACH0_TXBD_DESA_L(x) | BIT_ACH0_TXBD_DESA_L(v))
+
+/* 2 REG_ACH0_TXBD_DESA_H			(Offset 0x031C) */
+
+#define BIT_SHIFT_ACH0_TXBD_DESA_H 0
+#define BIT_MASK_ACH0_TXBD_DESA_H 0xffffffffL
+#define BIT_ACH0_TXBD_DESA_H(x)                                                \
+	(((x) & BIT_MASK_ACH0_TXBD_DESA_H) << BIT_SHIFT_ACH0_TXBD_DESA_H)
+#define BITS_ACH0_TXBD_DESA_H                                                  \
+	(BIT_MASK_ACH0_TXBD_DESA_H << BIT_SHIFT_ACH0_TXBD_DESA_H)
+#define BIT_CLEAR_ACH0_TXBD_DESA_H(x) ((x) & (~BITS_ACH0_TXBD_DESA_H))
+#define BIT_GET_ACH0_TXBD_DESA_H(x)                                            \
+	(((x) >> BIT_SHIFT_ACH0_TXBD_DESA_H) & BIT_MASK_ACH0_TXBD_DESA_H)
+#define BIT_SET_ACH0_TXBD_DESA_H(x, v)                                         \
+	(BIT_CLEAR_ACH0_TXBD_DESA_H(x) | BIT_ACH0_TXBD_DESA_H(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_VIQ_TXBD_DESA			(Offset 0x0320) */
+
+#define BIT_SHIFT_VIQ_TXBD_DESA 0
+#define BIT_MASK_VIQ_TXBD_DESA 0xffffffffffffffffL
+#define BIT_VIQ_TXBD_DESA(x)                                                   \
+	(((x) & BIT_MASK_VIQ_TXBD_DESA) << BIT_SHIFT_VIQ_TXBD_DESA)
+#define BITS_VIQ_TXBD_DESA (BIT_MASK_VIQ_TXBD_DESA << BIT_SHIFT_VIQ_TXBD_DESA)
+#define BIT_CLEAR_VIQ_TXBD_DESA(x) ((x) & (~BITS_VIQ_TXBD_DESA))
+#define BIT_GET_VIQ_TXBD_DESA(x)                                               \
+	(((x) >> BIT_SHIFT_VIQ_TXBD_DESA) & BIT_MASK_VIQ_TXBD_DESA)
+#define BIT_SET_VIQ_TXBD_DESA(x, v)                                            \
+	(BIT_CLEAR_VIQ_TXBD_DESA(x) | BIT_VIQ_TXBD_DESA(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_ACH1_TXBD_DESA_L			(Offset 0x0320) */
+
+#define BIT_SHIFT_ACH1_TXBD_DESA_L 0
+#define BIT_MASK_ACH1_TXBD_DESA_L 0xffffffffL
+#define BIT_ACH1_TXBD_DESA_L(x)                                                \
+	(((x) & BIT_MASK_ACH1_TXBD_DESA_L) << BIT_SHIFT_ACH1_TXBD_DESA_L)
+#define BITS_ACH1_TXBD_DESA_L                                                  \
+	(BIT_MASK_ACH1_TXBD_DESA_L << BIT_SHIFT_ACH1_TXBD_DESA_L)
+#define BIT_CLEAR_ACH1_TXBD_DESA_L(x) ((x) & (~BITS_ACH1_TXBD_DESA_L))
+#define BIT_GET_ACH1_TXBD_DESA_L(x)                                            \
+	(((x) >> BIT_SHIFT_ACH1_TXBD_DESA_L) & BIT_MASK_ACH1_TXBD_DESA_L)
+#define BIT_SET_ACH1_TXBD_DESA_L(x, v)                                         \
+	(BIT_CLEAR_ACH1_TXBD_DESA_L(x) | BIT_ACH1_TXBD_DESA_L(v))
+
+/* 2 REG_ACH1_TXBD_DESA_H			(Offset 0x0324) */
+
+#define BIT_SHIFT_ACH1_TXBD_DESA_H 0
+#define BIT_MASK_ACH1_TXBD_DESA_H 0xffffffffL
+#define BIT_ACH1_TXBD_DESA_H(x)                                                \
+	(((x) & BIT_MASK_ACH1_TXBD_DESA_H) << BIT_SHIFT_ACH1_TXBD_DESA_H)
+#define BITS_ACH1_TXBD_DESA_H                                                  \
+	(BIT_MASK_ACH1_TXBD_DESA_H << BIT_SHIFT_ACH1_TXBD_DESA_H)
+#define BIT_CLEAR_ACH1_TXBD_DESA_H(x) ((x) & (~BITS_ACH1_TXBD_DESA_H))
+#define BIT_GET_ACH1_TXBD_DESA_H(x)                                            \
+	(((x) >> BIT_SHIFT_ACH1_TXBD_DESA_H) & BIT_MASK_ACH1_TXBD_DESA_H)
+#define BIT_SET_ACH1_TXBD_DESA_H(x, v)                                         \
+	(BIT_CLEAR_ACH1_TXBD_DESA_H(x) | BIT_ACH1_TXBD_DESA_H(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_BEQ_TXBD_DESA			(Offset 0x0328) */
+
+#define BIT_SHIFT_BEQ_TXBD_DESA 0
+#define BIT_MASK_BEQ_TXBD_DESA 0xffffffffffffffffL
+#define BIT_BEQ_TXBD_DESA(x)                                                   \
+	(((x) & BIT_MASK_BEQ_TXBD_DESA) << BIT_SHIFT_BEQ_TXBD_DESA)
+#define BITS_BEQ_TXBD_DESA (BIT_MASK_BEQ_TXBD_DESA << BIT_SHIFT_BEQ_TXBD_DESA)
+#define BIT_CLEAR_BEQ_TXBD_DESA(x) ((x) & (~BITS_BEQ_TXBD_DESA))
+#define BIT_GET_BEQ_TXBD_DESA(x)                                               \
+	(((x) >> BIT_SHIFT_BEQ_TXBD_DESA) & BIT_MASK_BEQ_TXBD_DESA)
+#define BIT_SET_BEQ_TXBD_DESA(x, v)                                            \
+	(BIT_CLEAR_BEQ_TXBD_DESA(x) | BIT_BEQ_TXBD_DESA(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_ACH2_TXBD_DESA_L			(Offset 0x0328) */
+
+#define BIT_SHIFT_ACH2_TXBD_DESA_L 0
+#define BIT_MASK_ACH2_TXBD_DESA_L 0xffffffffL
+#define BIT_ACH2_TXBD_DESA_L(x)                                                \
+	(((x) & BIT_MASK_ACH2_TXBD_DESA_L) << BIT_SHIFT_ACH2_TXBD_DESA_L)
+#define BITS_ACH2_TXBD_DESA_L                                                  \
+	(BIT_MASK_ACH2_TXBD_DESA_L << BIT_SHIFT_ACH2_TXBD_DESA_L)
+#define BIT_CLEAR_ACH2_TXBD_DESA_L(x) ((x) & (~BITS_ACH2_TXBD_DESA_L))
+#define BIT_GET_ACH2_TXBD_DESA_L(x)                                            \
+	(((x) >> BIT_SHIFT_ACH2_TXBD_DESA_L) & BIT_MASK_ACH2_TXBD_DESA_L)
+#define BIT_SET_ACH2_TXBD_DESA_L(x, v)                                         \
+	(BIT_CLEAR_ACH2_TXBD_DESA_L(x) | BIT_ACH2_TXBD_DESA_L(v))
+
+/* 2 REG_ACH2_TXBD_DESA_H			(Offset 0x032C) */
+
+#define BIT_SHIFT_ACH2_TXBD_DESA_H 0
+#define BIT_MASK_ACH2_TXBD_DESA_H 0xffffffffL
+#define BIT_ACH2_TXBD_DESA_H(x)                                                \
+	(((x) & BIT_MASK_ACH2_TXBD_DESA_H) << BIT_SHIFT_ACH2_TXBD_DESA_H)
+#define BITS_ACH2_TXBD_DESA_H                                                  \
+	(BIT_MASK_ACH2_TXBD_DESA_H << BIT_SHIFT_ACH2_TXBD_DESA_H)
+#define BIT_CLEAR_ACH2_TXBD_DESA_H(x) ((x) & (~BITS_ACH2_TXBD_DESA_H))
+#define BIT_GET_ACH2_TXBD_DESA_H(x)                                            \
+	(((x) >> BIT_SHIFT_ACH2_TXBD_DESA_H) & BIT_MASK_ACH2_TXBD_DESA_H)
+#define BIT_SET_ACH2_TXBD_DESA_H(x, v)                                         \
+	(BIT_CLEAR_ACH2_TXBD_DESA_H(x) | BIT_ACH2_TXBD_DESA_H(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_BKQ_TXBD_DESA			(Offset 0x0330) */
+
+#define BIT_SHIFT_BKQ_TXBD_DESA 0
+#define BIT_MASK_BKQ_TXBD_DESA 0xffffffffffffffffL
+#define BIT_BKQ_TXBD_DESA(x)                                                   \
+	(((x) & BIT_MASK_BKQ_TXBD_DESA) << BIT_SHIFT_BKQ_TXBD_DESA)
+#define BITS_BKQ_TXBD_DESA (BIT_MASK_BKQ_TXBD_DESA << BIT_SHIFT_BKQ_TXBD_DESA)
+#define BIT_CLEAR_BKQ_TXBD_DESA(x) ((x) & (~BITS_BKQ_TXBD_DESA))
+#define BIT_GET_BKQ_TXBD_DESA(x)                                               \
+	(((x) >> BIT_SHIFT_BKQ_TXBD_DESA) & BIT_MASK_BKQ_TXBD_DESA)
+#define BIT_SET_BKQ_TXBD_DESA(x, v)                                            \
+	(BIT_CLEAR_BKQ_TXBD_DESA(x) | BIT_BKQ_TXBD_DESA(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_ACH3_TXBD_DESA_L			(Offset 0x0330) */
+
+#define BIT_SHIFT_ACH3_TXBD_DESA_L 0
+#define BIT_MASK_ACH3_TXBD_DESA_L 0xffffffffL
+#define BIT_ACH3_TXBD_DESA_L(x)                                                \
+	(((x) & BIT_MASK_ACH3_TXBD_DESA_L) << BIT_SHIFT_ACH3_TXBD_DESA_L)
+#define BITS_ACH3_TXBD_DESA_L                                                  \
+	(BIT_MASK_ACH3_TXBD_DESA_L << BIT_SHIFT_ACH3_TXBD_DESA_L)
+#define BIT_CLEAR_ACH3_TXBD_DESA_L(x) ((x) & (~BITS_ACH3_TXBD_DESA_L))
+#define BIT_GET_ACH3_TXBD_DESA_L(x)                                            \
+	(((x) >> BIT_SHIFT_ACH3_TXBD_DESA_L) & BIT_MASK_ACH3_TXBD_DESA_L)
+#define BIT_SET_ACH3_TXBD_DESA_L(x, v)                                         \
+	(BIT_CLEAR_ACH3_TXBD_DESA_L(x) | BIT_ACH3_TXBD_DESA_L(v))
+
+/* 2 REG_ACH3_TXBD_DESA_H			(Offset 0x0334) */
+
+#define BIT_SHIFT_ACH3_TXBD_DESA_H 0
+#define BIT_MASK_ACH3_TXBD_DESA_H 0xffffffffL
+#define BIT_ACH3_TXBD_DESA_H(x)                                                \
+	(((x) & BIT_MASK_ACH3_TXBD_DESA_H) << BIT_SHIFT_ACH3_TXBD_DESA_H)
+#define BITS_ACH3_TXBD_DESA_H                                                  \
+	(BIT_MASK_ACH3_TXBD_DESA_H << BIT_SHIFT_ACH3_TXBD_DESA_H)
+#define BIT_CLEAR_ACH3_TXBD_DESA_H(x) ((x) & (~BITS_ACH3_TXBD_DESA_H))
+#define BIT_GET_ACH3_TXBD_DESA_H(x)                                            \
+	(((x) >> BIT_SHIFT_ACH3_TXBD_DESA_H) & BIT_MASK_ACH3_TXBD_DESA_H)
+#define BIT_SET_ACH3_TXBD_DESA_H(x, v)                                         \
+	(BIT_CLEAR_ACH3_TXBD_DESA_H(x) | BIT_ACH3_TXBD_DESA_H(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_RXQ_RXBD_DESA			(Offset 0x0338) */
+
+#define BIT_SHIFT_RXQ_RXBD_DESA 0
+#define BIT_MASK_RXQ_RXBD_DESA 0xffffffffffffffffL
+#define BIT_RXQ_RXBD_DESA(x)                                                   \
+	(((x) & BIT_MASK_RXQ_RXBD_DESA) << BIT_SHIFT_RXQ_RXBD_DESA)
+#define BITS_RXQ_RXBD_DESA (BIT_MASK_RXQ_RXBD_DESA << BIT_SHIFT_RXQ_RXBD_DESA)
+#define BIT_CLEAR_RXQ_RXBD_DESA(x) ((x) & (~BITS_RXQ_RXBD_DESA))
+#define BIT_GET_RXQ_RXBD_DESA(x)                                               \
+	(((x) >> BIT_SHIFT_RXQ_RXBD_DESA) & BIT_MASK_RXQ_RXBD_DESA)
+#define BIT_SET_RXQ_RXBD_DESA(x, v)                                            \
+	(BIT_CLEAR_RXQ_RXBD_DESA(x) | BIT_RXQ_RXBD_DESA(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_P0RXQ_RXBD_DESA_L			(Offset 0x0338) */
+
+#define BIT_SHIFT_P0RXQ_RXBD_DESA_L 0
+#define BIT_MASK_P0RXQ_RXBD_DESA_L 0xffffffffL
+#define BIT_P0RXQ_RXBD_DESA_L(x)                                               \
+	(((x) & BIT_MASK_P0RXQ_RXBD_DESA_L) << BIT_SHIFT_P0RXQ_RXBD_DESA_L)
+#define BITS_P0RXQ_RXBD_DESA_L                                                 \
+	(BIT_MASK_P0RXQ_RXBD_DESA_L << BIT_SHIFT_P0RXQ_RXBD_DESA_L)
+#define BIT_CLEAR_P0RXQ_RXBD_DESA_L(x) ((x) & (~BITS_P0RXQ_RXBD_DESA_L))
+#define BIT_GET_P0RXQ_RXBD_DESA_L(x)                                           \
+	(((x) >> BIT_SHIFT_P0RXQ_RXBD_DESA_L) & BIT_MASK_P0RXQ_RXBD_DESA_L)
+#define BIT_SET_P0RXQ_RXBD_DESA_L(x, v)                                        \
+	(BIT_CLEAR_P0RXQ_RXBD_DESA_L(x) | BIT_P0RXQ_RXBD_DESA_L(v))
+
+/* 2 REG_P0RXQ_RXBD_DESA_H			(Offset 0x033C) */
+
+#define BIT_SHIFT_P0RXQ_RXBD_DESA_H 0
+#define BIT_MASK_P0RXQ_RXBD_DESA_H 0xffffffffL
+#define BIT_P0RXQ_RXBD_DESA_H(x)                                               \
+	(((x) & BIT_MASK_P0RXQ_RXBD_DESA_H) << BIT_SHIFT_P0RXQ_RXBD_DESA_H)
+#define BITS_P0RXQ_RXBD_DESA_H                                                 \
+	(BIT_MASK_P0RXQ_RXBD_DESA_H << BIT_SHIFT_P0RXQ_RXBD_DESA_H)
+#define BIT_CLEAR_P0RXQ_RXBD_DESA_H(x) ((x) & (~BITS_P0RXQ_RXBD_DESA_H))
+#define BIT_GET_P0RXQ_RXBD_DESA_H(x)                                           \
+	(((x) >> BIT_SHIFT_P0RXQ_RXBD_DESA_H) & BIT_MASK_P0RXQ_RXBD_DESA_H)
+#define BIT_SET_P0RXQ_RXBD_DESA_H(x, v)                                        \
+	(BIT_CLEAR_P0RXQ_RXBD_DESA_H(x) | BIT_P0RXQ_RXBD_DESA_H(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_HI0Q_TXBD_DESA			(Offset 0x0340) */
+
+#define BIT_SHIFT_HI0Q_TXBD_DESA 0
+#define BIT_MASK_HI0Q_TXBD_DESA 0xffffffffffffffffL
+#define BIT_HI0Q_TXBD_DESA(x)                                                  \
+	(((x) & BIT_MASK_HI0Q_TXBD_DESA) << BIT_SHIFT_HI0Q_TXBD_DESA)
+#define BITS_HI0Q_TXBD_DESA                                                    \
+	(BIT_MASK_HI0Q_TXBD_DESA << BIT_SHIFT_HI0Q_TXBD_DESA)
+#define BIT_CLEAR_HI0Q_TXBD_DESA(x) ((x) & (~BITS_HI0Q_TXBD_DESA))
+#define BIT_GET_HI0Q_TXBD_DESA(x)                                              \
+	(((x) >> BIT_SHIFT_HI0Q_TXBD_DESA) & BIT_MASK_HI0Q_TXBD_DESA)
+#define BIT_SET_HI0Q_TXBD_DESA(x, v)                                           \
+	(BIT_CLEAR_HI0Q_TXBD_DESA(x) | BIT_HI0Q_TXBD_DESA(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_P0BCNQ_TXBD_DESA_L			(Offset 0x0340) */
+
+#define BIT_SHIFT_P0BCNQ_TXBD_DESA_L 0
+#define BIT_MASK_P0BCNQ_TXBD_DESA_L 0xffffffffL
+#define BIT_P0BCNQ_TXBD_DESA_L(x)                                              \
+	(((x) & BIT_MASK_P0BCNQ_TXBD_DESA_L) << BIT_SHIFT_P0BCNQ_TXBD_DESA_L)
+#define BITS_P0BCNQ_TXBD_DESA_L                                                \
+	(BIT_MASK_P0BCNQ_TXBD_DESA_L << BIT_SHIFT_P0BCNQ_TXBD_DESA_L)
+#define BIT_CLEAR_P0BCNQ_TXBD_DESA_L(x) ((x) & (~BITS_P0BCNQ_TXBD_DESA_L))
+#define BIT_GET_P0BCNQ_TXBD_DESA_L(x)                                          \
+	(((x) >> BIT_SHIFT_P0BCNQ_TXBD_DESA_L) & BIT_MASK_P0BCNQ_TXBD_DESA_L)
+#define BIT_SET_P0BCNQ_TXBD_DESA_L(x, v)                                       \
+	(BIT_CLEAR_P0BCNQ_TXBD_DESA_L(x) | BIT_P0BCNQ_TXBD_DESA_L(v))
+
+/* 2 REG_P0BCNQ_TXBD_DESA_H			(Offset 0x0344) */
+
+#define BIT_SHIFT_P0BCNQ_TXBD_DESA_H 0
+#define BIT_MASK_P0BCNQ_TXBD_DESA_H 0xffffffffL
+#define BIT_P0BCNQ_TXBD_DESA_H(x)                                              \
+	(((x) & BIT_MASK_P0BCNQ_TXBD_DESA_H) << BIT_SHIFT_P0BCNQ_TXBD_DESA_H)
+#define BITS_P0BCNQ_TXBD_DESA_H                                                \
+	(BIT_MASK_P0BCNQ_TXBD_DESA_H << BIT_SHIFT_P0BCNQ_TXBD_DESA_H)
+#define BIT_CLEAR_P0BCNQ_TXBD_DESA_H(x) ((x) & (~BITS_P0BCNQ_TXBD_DESA_H))
+#define BIT_GET_P0BCNQ_TXBD_DESA_H(x)                                          \
+	(((x) >> BIT_SHIFT_P0BCNQ_TXBD_DESA_H) & BIT_MASK_P0BCNQ_TXBD_DESA_H)
+#define BIT_SET_P0BCNQ_TXBD_DESA_H(x, v)                                       \
+	(BIT_CLEAR_P0BCNQ_TXBD_DESA_H(x) | BIT_P0BCNQ_TXBD_DESA_H(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_HI1Q_TXBD_DESA			(Offset 0x0348) */
+
+#define BIT_SHIFT_HI1Q_TXBD_DESA 0
+#define BIT_MASK_HI1Q_TXBD_DESA 0xffffffffffffffffL
+#define BIT_HI1Q_TXBD_DESA(x)                                                  \
+	(((x) & BIT_MASK_HI1Q_TXBD_DESA) << BIT_SHIFT_HI1Q_TXBD_DESA)
+#define BITS_HI1Q_TXBD_DESA                                                    \
+	(BIT_MASK_HI1Q_TXBD_DESA << BIT_SHIFT_HI1Q_TXBD_DESA)
+#define BIT_CLEAR_HI1Q_TXBD_DESA(x) ((x) & (~BITS_HI1Q_TXBD_DESA))
+#define BIT_GET_HI1Q_TXBD_DESA(x)                                              \
+	(((x) >> BIT_SHIFT_HI1Q_TXBD_DESA) & BIT_MASK_HI1Q_TXBD_DESA)
+#define BIT_SET_HI1Q_TXBD_DESA(x, v)                                           \
+	(BIT_CLEAR_HI1Q_TXBD_DESA(x) | BIT_HI1Q_TXBD_DESA(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_FWCMDQ_TXBD_DESA_L			(Offset 0x0348) */
+
+#define BIT_SHIFT_FWCMDQ_TXBD_DESA_L 0
+#define BIT_MASK_FWCMDQ_TXBD_DESA_L 0xffffffffL
+#define BIT_FWCMDQ_TXBD_DESA_L(x)                                              \
+	(((x) & BIT_MASK_FWCMDQ_TXBD_DESA_L) << BIT_SHIFT_FWCMDQ_TXBD_DESA_L)
+#define BITS_FWCMDQ_TXBD_DESA_L                                                \
+	(BIT_MASK_FWCMDQ_TXBD_DESA_L << BIT_SHIFT_FWCMDQ_TXBD_DESA_L)
+#define BIT_CLEAR_FWCMDQ_TXBD_DESA_L(x) ((x) & (~BITS_FWCMDQ_TXBD_DESA_L))
+#define BIT_GET_FWCMDQ_TXBD_DESA_L(x)                                          \
+	(((x) >> BIT_SHIFT_FWCMDQ_TXBD_DESA_L) & BIT_MASK_FWCMDQ_TXBD_DESA_L)
+#define BIT_SET_FWCMDQ_TXBD_DESA_L(x, v)                                       \
+	(BIT_CLEAR_FWCMDQ_TXBD_DESA_L(x) | BIT_FWCMDQ_TXBD_DESA_L(v))
+
+/* 2 REG_FWCMDQ_TXBD_DESA_H			(Offset 0x034C) */
+
+#define BIT_SHIFT_FWCMDQ_TXBD_DESA_H 0
+#define BIT_MASK_FWCMDQ_TXBD_DESA_H 0xffffffffL
+#define BIT_FWCMDQ_TXBD_DESA_H(x)                                              \
+	(((x) & BIT_MASK_FWCMDQ_TXBD_DESA_H) << BIT_SHIFT_FWCMDQ_TXBD_DESA_H)
+#define BITS_FWCMDQ_TXBD_DESA_H                                                \
+	(BIT_MASK_FWCMDQ_TXBD_DESA_H << BIT_SHIFT_FWCMDQ_TXBD_DESA_H)
+#define BIT_CLEAR_FWCMDQ_TXBD_DESA_H(x) ((x) & (~BITS_FWCMDQ_TXBD_DESA_H))
+#define BIT_GET_FWCMDQ_TXBD_DESA_H(x)                                          \
+	(((x) >> BIT_SHIFT_FWCMDQ_TXBD_DESA_H) & BIT_MASK_FWCMDQ_TXBD_DESA_H)
+#define BIT_SET_FWCMDQ_TXBD_DESA_H(x, v)                                       \
+	(BIT_CLEAR_FWCMDQ_TXBD_DESA_H(x) | BIT_FWCMDQ_TXBD_DESA_H(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_HI2Q_TXBD_DESA			(Offset 0x0350) */
+
+#define BIT_SHIFT_HI2Q_TXBD_DESA 0
+#define BIT_MASK_HI2Q_TXBD_DESA 0xffffffffffffffffL
+#define BIT_HI2Q_TXBD_DESA(x)                                                  \
+	(((x) & BIT_MASK_HI2Q_TXBD_DESA) << BIT_SHIFT_HI2Q_TXBD_DESA)
+#define BITS_HI2Q_TXBD_DESA                                                    \
+	(BIT_MASK_HI2Q_TXBD_DESA << BIT_SHIFT_HI2Q_TXBD_DESA)
+#define BIT_CLEAR_HI2Q_TXBD_DESA(x) ((x) & (~BITS_HI2Q_TXBD_DESA))
+#define BIT_GET_HI2Q_TXBD_DESA(x)                                              \
+	(((x) >> BIT_SHIFT_HI2Q_TXBD_DESA) & BIT_MASK_HI2Q_TXBD_DESA)
+#define BIT_SET_HI2Q_TXBD_DESA(x, v)                                           \
+	(BIT_CLEAR_HI2Q_TXBD_DESA(x) | BIT_HI2Q_TXBD_DESA(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_PCIE_HRPWM1_HCPWM1_DCPU		(Offset 0x0354) */
+
+#define BIT_SHIFT_PCIE_HCPWM1_DCPU 16
+#define BIT_MASK_PCIE_HCPWM1_DCPU 0xff
+#define BIT_PCIE_HCPWM1_DCPU(x)                                                \
+	(((x) & BIT_MASK_PCIE_HCPWM1_DCPU) << BIT_SHIFT_PCIE_HCPWM1_DCPU)
+#define BITS_PCIE_HCPWM1_DCPU                                                  \
+	(BIT_MASK_PCIE_HCPWM1_DCPU << BIT_SHIFT_PCIE_HCPWM1_DCPU)
+#define BIT_CLEAR_PCIE_HCPWM1_DCPU(x) ((x) & (~BITS_PCIE_HCPWM1_DCPU))
+#define BIT_GET_PCIE_HCPWM1_DCPU(x)                                            \
+	(((x) >> BIT_SHIFT_PCIE_HCPWM1_DCPU) & BIT_MASK_PCIE_HCPWM1_DCPU)
+#define BIT_SET_PCIE_HCPWM1_DCPU(x, v)                                         \
+	(BIT_CLEAR_PCIE_HCPWM1_DCPU(x) | BIT_PCIE_HCPWM1_DCPU(v))
+
+#define BIT_SHIFT_PCIE_HRPWM1_DCPU 8
+#define BIT_MASK_PCIE_HRPWM1_DCPU 0xff
+#define BIT_PCIE_HRPWM1_DCPU(x)                                                \
+	(((x) & BIT_MASK_PCIE_HRPWM1_DCPU) << BIT_SHIFT_PCIE_HRPWM1_DCPU)
+#define BITS_PCIE_HRPWM1_DCPU                                                  \
+	(BIT_MASK_PCIE_HRPWM1_DCPU << BIT_SHIFT_PCIE_HRPWM1_DCPU)
+#define BIT_CLEAR_PCIE_HRPWM1_DCPU(x) ((x) & (~BITS_PCIE_HRPWM1_DCPU))
+#define BIT_GET_PCIE_HRPWM1_DCPU(x)                                            \
+	(((x) >> BIT_SHIFT_PCIE_HRPWM1_DCPU) & BIT_MASK_PCIE_HRPWM1_DCPU)
+#define BIT_SET_PCIE_HRPWM1_DCPU(x, v)                                         \
+	(BIT_CLEAR_PCIE_HRPWM1_DCPU(x) | BIT_PCIE_HRPWM1_DCPU(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_HI3Q_TXBD_DESA			(Offset 0x0358) */
+
+#define BIT_SHIFT_HI3Q_TXBD_DESA 0
+#define BIT_MASK_HI3Q_TXBD_DESA 0xffffffffffffffffL
+#define BIT_HI3Q_TXBD_DESA(x)                                                  \
+	(((x) & BIT_MASK_HI3Q_TXBD_DESA) << BIT_SHIFT_HI3Q_TXBD_DESA)
+#define BITS_HI3Q_TXBD_DESA                                                    \
+	(BIT_MASK_HI3Q_TXBD_DESA << BIT_SHIFT_HI3Q_TXBD_DESA)
+#define BIT_CLEAR_HI3Q_TXBD_DESA(x) ((x) & (~BITS_HI3Q_TXBD_DESA))
+#define BIT_GET_HI3Q_TXBD_DESA(x)                                              \
+	(((x) >> BIT_SHIFT_HI3Q_TXBD_DESA) & BIT_MASK_HI3Q_TXBD_DESA)
+#define BIT_SET_HI3Q_TXBD_DESA(x, v)                                           \
+	(BIT_CLEAR_HI3Q_TXBD_DESA(x) | BIT_HI3Q_TXBD_DESA(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_P0_MPRT_BCNQ_TXBD_DESA_L		(Offset 0x0358) */
+
+#define BIT_SHIFT_P0_MPRT_BCNQ_TXBD_DESA_L 0
+#define BIT_MASK_P0_MPRT_BCNQ_TXBD_DESA_L 0xffffffffL
+#define BIT_P0_MPRT_BCNQ_TXBD_DESA_L(x)                                        \
+	(((x) & BIT_MASK_P0_MPRT_BCNQ_TXBD_DESA_L)                             \
+	 << BIT_SHIFT_P0_MPRT_BCNQ_TXBD_DESA_L)
+#define BITS_P0_MPRT_BCNQ_TXBD_DESA_L                                          \
+	(BIT_MASK_P0_MPRT_BCNQ_TXBD_DESA_L                                     \
+	 << BIT_SHIFT_P0_MPRT_BCNQ_TXBD_DESA_L)
+#define BIT_CLEAR_P0_MPRT_BCNQ_TXBD_DESA_L(x)                                  \
+	((x) & (~BITS_P0_MPRT_BCNQ_TXBD_DESA_L))
+#define BIT_GET_P0_MPRT_BCNQ_TXBD_DESA_L(x)                                    \
+	(((x) >> BIT_SHIFT_P0_MPRT_BCNQ_TXBD_DESA_L) &                         \
+	 BIT_MASK_P0_MPRT_BCNQ_TXBD_DESA_L)
+#define BIT_SET_P0_MPRT_BCNQ_TXBD_DESA_L(x, v)                                 \
+	(BIT_CLEAR_P0_MPRT_BCNQ_TXBD_DESA_L(x) |                               \
+	 BIT_P0_MPRT_BCNQ_TXBD_DESA_L(v))
+
+/* 2 REG_P0_MPRT_BCNQ_TXBD_DESA_H		(Offset 0x035C) */
+
+#define BIT_CLR_P0HI15Q_HW_IDX BIT(29)
+#define BIT_CLR_P0HI14Q_HW_IDX BIT(28)
+#define BIT_CLR_P0HI13Q_HW_IDX BIT(27)
+#define BIT_CLR_P0HI12Q_HW_IDX BIT(26)
+#define BIT_CLR_P0HI11Q_HW_IDX BIT(25)
+#define BIT_CLR_P0HI10Q_HW_IDX BIT(24)
+#define BIT_CLR_P0HI9Q_HW_IDX BIT(23)
+#define BIT_CLR_P0HI8Q_HW_IDX BIT(22)
+#define BIT_CLR_ACH7_HW_IDX BIT(21)
+#define BIT_CLR_ACH13_HW_IDX BIT(21)
+#define BIT_CLR_ACH6_HW_IDX BIT(20)
+#define BIT_CLR_ACH12_HW_IDX BIT(20)
+#define BIT_CLR_ACH5_HW_IDX BIT(19)
+#define BIT_CLR_ACH11_HW_IDX BIT(19)
+#define BIT_CLR_ACH4_HW_IDX BIT(18)
+#define BIT_CLR_ACH10_HW_IDX BIT(18)
+#define BIT_CLR_ACH9_HW_IDX BIT(17)
+#define BIT_CLR_ACH8_HW_IDX BIT(16)
+
+#define BIT_SHIFT_P0_MPRT_BCNQ_DESC_MODE 13
+#define BIT_MASK_P0_MPRT_BCNQ_DESC_MODE 0x3
+#define BIT_P0_MPRT_BCNQ_DESC_MODE(x)                                          \
+	(((x) & BIT_MASK_P0_MPRT_BCNQ_DESC_MODE)                               \
+	 << BIT_SHIFT_P0_MPRT_BCNQ_DESC_MODE)
+#define BITS_P0_MPRT_BCNQ_DESC_MODE                                            \
+	(BIT_MASK_P0_MPRT_BCNQ_DESC_MODE << BIT_SHIFT_P0_MPRT_BCNQ_DESC_MODE)
+#define BIT_CLEAR_P0_MPRT_BCNQ_DESC_MODE(x)                                    \
+	((x) & (~BITS_P0_MPRT_BCNQ_DESC_MODE))
+#define BIT_GET_P0_MPRT_BCNQ_DESC_MODE(x)                                      \
+	(((x) >> BIT_SHIFT_P0_MPRT_BCNQ_DESC_MODE) &                           \
+	 BIT_MASK_P0_MPRT_BCNQ_DESC_MODE)
+#define BIT_SET_P0_MPRT_BCNQ_DESC_MODE(x, v)                                   \
+	(BIT_CLEAR_P0_MPRT_BCNQ_DESC_MODE(x) | BIT_P0_MPRT_BCNQ_DESC_MODE(v))
+
+#define BIT_CLR_P0HI15Q_HOST_IDX BIT(13)
+#define BIT_CLR_P0HI14Q_HOST_IDX BIT(12)
+#define BIT_PCIE_P0MPRT_BCNQ4_FLAG BIT(11)
+#define BIT_CLR_P0HI13Q_HOST_IDX BIT(11)
+#define BIT_PCIE_P0MPRT_BCNQ3_FLAG BIT(10)
+#define BIT_CLR_P0HI12Q_HOST_IDX BIT(10)
+#define BIT_PCIE_P0MPRT_BCNQ2_FLAG BIT(9)
+#define BIT_CLR_P0HI11Q_HOST_IDX BIT(9)
+#define BIT_PCIE_P0MPRT_BCNQ1_FLAG BIT(8)
+#define BIT_CLR_P0HI10Q_HOST_IDX BIT(8)
+#define BIT_CLR_P0HI9Q_HOST_IDX BIT(7)
+#define BIT_CLR_P0HI8Q_HOST_IDX BIT(6)
+#define BIT_CLR_ACH7_HOST_IDX BIT(5)
+#define BIT_CLR_ACH13_HOST_IDX BIT(5)
+#define BIT_CLR_ACH6_HOST_IDX BIT(4)
+#define BIT_CLR_ACH12_HOST_IDX BIT(4)
+#define BIT_CLR_ACH5_HOST_IDX BIT(3)
+#define BIT_CLR_ACH11_HOST_IDX BIT(3)
+#define BIT_CLR_ACH4_HOST_IDX BIT(2)
+#define BIT_CLR_ACH10_HOST_IDX BIT(2)
+#define BIT_EPHY_CAL_DONE BIT(1)
+#define BIT_CLR_ACH9_HOST_IDX BIT(1)
+
+#define BIT_SHIFT_P0_MPRT_BCNQ_TXBD_DESA_H 0
+#define BIT_MASK_P0_MPRT_BCNQ_TXBD_DESA_H 0xffffffffL
+#define BIT_P0_MPRT_BCNQ_TXBD_DESA_H(x)                                        \
+	(((x) & BIT_MASK_P0_MPRT_BCNQ_TXBD_DESA_H)                             \
+	 << BIT_SHIFT_P0_MPRT_BCNQ_TXBD_DESA_H)
+#define BITS_P0_MPRT_BCNQ_TXBD_DESA_H                                          \
+	(BIT_MASK_P0_MPRT_BCNQ_TXBD_DESA_H                                     \
+	 << BIT_SHIFT_P0_MPRT_BCNQ_TXBD_DESA_H)
+#define BIT_CLEAR_P0_MPRT_BCNQ_TXBD_DESA_H(x)                                  \
+	((x) & (~BITS_P0_MPRT_BCNQ_TXBD_DESA_H))
+#define BIT_GET_P0_MPRT_BCNQ_TXBD_DESA_H(x)                                    \
+	(((x) >> BIT_SHIFT_P0_MPRT_BCNQ_TXBD_DESA_H) &                         \
+	 BIT_MASK_P0_MPRT_BCNQ_TXBD_DESA_H)
+#define BIT_SET_P0_MPRT_BCNQ_TXBD_DESA_H(x, v)                                 \
+	(BIT_CLEAR_P0_MPRT_BCNQ_TXBD_DESA_H(x) |                               \
+	 BIT_P0_MPRT_BCNQ_TXBD_DESA_H(v))
+
+#define BIT_RESET_APHY BIT(0)
+#define BIT_CLR_ACH8_HOST_IDX BIT(0)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_HI4Q_TXBD_DESA			(Offset 0x0360) */
+
+#define BIT_SHIFT_HI4Q_TXBD_DESA 0
+#define BIT_MASK_HI4Q_TXBD_DESA 0xffffffffffffffffL
+#define BIT_HI4Q_TXBD_DESA(x)                                                  \
+	(((x) & BIT_MASK_HI4Q_TXBD_DESA) << BIT_SHIFT_HI4Q_TXBD_DESA)
+#define BITS_HI4Q_TXBD_DESA                                                    \
+	(BIT_MASK_HI4Q_TXBD_DESA << BIT_SHIFT_HI4Q_TXBD_DESA)
+#define BIT_CLEAR_HI4Q_TXBD_DESA(x) ((x) & (~BITS_HI4Q_TXBD_DESA))
+#define BIT_GET_HI4Q_TXBD_DESA(x)                                              \
+	(((x) >> BIT_SHIFT_HI4Q_TXBD_DESA) & BIT_MASK_HI4Q_TXBD_DESA)
+#define BIT_SET_HI4Q_TXBD_DESA(x, v)                                           \
+	(BIT_CLEAR_HI4Q_TXBD_DESA(x) | BIT_HI4Q_TXBD_DESA(v))
+
+/* 2 REG_HI5Q_TXBD_DESA			(Offset 0x0368) */
+
+#define BIT_SHIFT_HI5Q_TXBD_DESA 0
+#define BIT_MASK_HI5Q_TXBD_DESA 0xffffffffffffffffL
+#define BIT_HI5Q_TXBD_DESA(x)                                                  \
+	(((x) & BIT_MASK_HI5Q_TXBD_DESA) << BIT_SHIFT_HI5Q_TXBD_DESA)
+#define BITS_HI5Q_TXBD_DESA                                                    \
+	(BIT_MASK_HI5Q_TXBD_DESA << BIT_SHIFT_HI5Q_TXBD_DESA)
+#define BIT_CLEAR_HI5Q_TXBD_DESA(x) ((x) & (~BITS_HI5Q_TXBD_DESA))
+#define BIT_GET_HI5Q_TXBD_DESA(x)                                              \
+	(((x) >> BIT_SHIFT_HI5Q_TXBD_DESA) & BIT_MASK_HI5Q_TXBD_DESA)
+#define BIT_SET_HI5Q_TXBD_DESA(x, v)                                           \
+	(BIT_CLEAR_HI5Q_TXBD_DESA(x) | BIT_HI5Q_TXBD_DESA(v))
+
+/* 2 REG_HI6Q_TXBD_DESA			(Offset 0x0370) */
+
+#define BIT_SHIFT_HI6Q_TXBD_DESA 0
+#define BIT_MASK_HI6Q_TXBD_DESA 0xffffffffffffffffL
+#define BIT_HI6Q_TXBD_DESA(x)                                                  \
+	(((x) & BIT_MASK_HI6Q_TXBD_DESA) << BIT_SHIFT_HI6Q_TXBD_DESA)
+#define BITS_HI6Q_TXBD_DESA                                                    \
+	(BIT_MASK_HI6Q_TXBD_DESA << BIT_SHIFT_HI6Q_TXBD_DESA)
+#define BIT_CLEAR_HI6Q_TXBD_DESA(x) ((x) & (~BITS_HI6Q_TXBD_DESA))
+#define BIT_GET_HI6Q_TXBD_DESA(x)                                              \
+	(((x) >> BIT_SHIFT_HI6Q_TXBD_DESA) & BIT_MASK_HI6Q_TXBD_DESA)
+#define BIT_SET_HI6Q_TXBD_DESA(x, v)                                           \
+	(BIT_CLEAR_HI6Q_TXBD_DESA(x) | BIT_HI6Q_TXBD_DESA(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_P0MGQ_RXQ_TXRXBD_NUM		(Offset 0x0378) */
+
+#define BIT_SYS_32_64_V1 BIT(31)
+
+#define BIT_SHIFT_P0BCNQ_DESC_MODE 29
+#define BIT_MASK_P0BCNQ_DESC_MODE 0x3
+#define BIT_P0BCNQ_DESC_MODE(x)                                                \
+	(((x) & BIT_MASK_P0BCNQ_DESC_MODE) << BIT_SHIFT_P0BCNQ_DESC_MODE)
+#define BITS_P0BCNQ_DESC_MODE                                                  \
+	(BIT_MASK_P0BCNQ_DESC_MODE << BIT_SHIFT_P0BCNQ_DESC_MODE)
+#define BIT_CLEAR_P0BCNQ_DESC_MODE(x) ((x) & (~BITS_P0BCNQ_DESC_MODE))
+#define BIT_GET_P0BCNQ_DESC_MODE(x)                                            \
+	(((x) >> BIT_SHIFT_P0BCNQ_DESC_MODE) & BIT_MASK_P0BCNQ_DESC_MODE)
+#define BIT_SET_P0BCNQ_DESC_MODE(x, v)                                         \
+	(BIT_CLEAR_P0BCNQ_DESC_MODE(x) | BIT_P0BCNQ_DESC_MODE(v))
+
+#define BIT_PCIE_P0BCNQ_FLAG BIT(28)
+
+#define BIT_SHIFT_P0RXQ_DESC_NUM 16
+#define BIT_MASK_P0RXQ_DESC_NUM 0xfff
+#define BIT_P0RXQ_DESC_NUM(x)                                                  \
+	(((x) & BIT_MASK_P0RXQ_DESC_NUM) << BIT_SHIFT_P0RXQ_DESC_NUM)
+#define BITS_P0RXQ_DESC_NUM                                                    \
+	(BIT_MASK_P0RXQ_DESC_NUM << BIT_SHIFT_P0RXQ_DESC_NUM)
+#define BIT_CLEAR_P0RXQ_DESC_NUM(x) ((x) & (~BITS_P0RXQ_DESC_NUM))
+#define BIT_GET_P0RXQ_DESC_NUM(x)                                              \
+	(((x) >> BIT_SHIFT_P0RXQ_DESC_NUM) & BIT_MASK_P0RXQ_DESC_NUM)
+#define BIT_SET_P0RXQ_DESC_NUM(x, v)                                           \
+	(BIT_CLEAR_P0RXQ_DESC_NUM(x) | BIT_P0RXQ_DESC_NUM(v))
+
+#define BIT_PCIE_P0MGQ_FLAG BIT(14)
+
+#define BIT_SHIFT_P0MGQ_DESC_MODE 12
+#define BIT_MASK_P0MGQ_DESC_MODE 0x3
+#define BIT_P0MGQ_DESC_MODE(x)                                                 \
+	(((x) & BIT_MASK_P0MGQ_DESC_MODE) << BIT_SHIFT_P0MGQ_DESC_MODE)
+#define BITS_P0MGQ_DESC_MODE                                                   \
+	(BIT_MASK_P0MGQ_DESC_MODE << BIT_SHIFT_P0MGQ_DESC_MODE)
+#define BIT_CLEAR_P0MGQ_DESC_MODE(x) ((x) & (~BITS_P0MGQ_DESC_MODE))
+#define BIT_GET_P0MGQ_DESC_MODE(x)                                             \
+	(((x) >> BIT_SHIFT_P0MGQ_DESC_MODE) & BIT_MASK_P0MGQ_DESC_MODE)
+#define BIT_SET_P0MGQ_DESC_MODE(x, v)                                          \
+	(BIT_CLEAR_P0MGQ_DESC_MODE(x) | BIT_P0MGQ_DESC_MODE(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_HI7Q_TXBD_DESA			(Offset 0x0378) */
+
+#define BIT_SHIFT_HI7Q_TXBD_DESA 0
+#define BIT_MASK_HI7Q_TXBD_DESA 0xffffffffffffffffL
+#define BIT_HI7Q_TXBD_DESA(x)                                                  \
+	(((x) & BIT_MASK_HI7Q_TXBD_DESA) << BIT_SHIFT_HI7Q_TXBD_DESA)
+#define BITS_HI7Q_TXBD_DESA                                                    \
+	(BIT_MASK_HI7Q_TXBD_DESA << BIT_SHIFT_HI7Q_TXBD_DESA)
+#define BIT_CLEAR_HI7Q_TXBD_DESA(x) ((x) & (~BITS_HI7Q_TXBD_DESA))
+#define BIT_GET_HI7Q_TXBD_DESA(x)                                              \
+	(((x) >> BIT_SHIFT_HI7Q_TXBD_DESA) & BIT_MASK_HI7Q_TXBD_DESA)
+#define BIT_SET_HI7Q_TXBD_DESA(x, v)                                           \
+	(BIT_CLEAR_HI7Q_TXBD_DESA(x) | BIT_HI7Q_TXBD_DESA(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_P0MGQ_RXQ_TXRXBD_NUM		(Offset 0x0378) */
+
+#define BIT_SHIFT_P0MGQ_DESC_NUM 0
+#define BIT_MASK_P0MGQ_DESC_NUM 0xfff
+#define BIT_P0MGQ_DESC_NUM(x)                                                  \
+	(((x) & BIT_MASK_P0MGQ_DESC_NUM) << BIT_SHIFT_P0MGQ_DESC_NUM)
+#define BITS_P0MGQ_DESC_NUM                                                    \
+	(BIT_MASK_P0MGQ_DESC_NUM << BIT_SHIFT_P0MGQ_DESC_NUM)
+#define BIT_CLEAR_P0MGQ_DESC_NUM(x) ((x) & (~BITS_P0MGQ_DESC_NUM))
+#define BIT_GET_P0MGQ_DESC_NUM(x)                                              \
+	(((x) >> BIT_SHIFT_P0MGQ_DESC_NUM) & BIT_MASK_P0MGQ_DESC_NUM)
+#define BIT_SET_P0MGQ_DESC_NUM(x, v)                                           \
+	(BIT_CLEAR_P0MGQ_DESC_NUM(x) | BIT_P0MGQ_DESC_NUM(v))
+
+/* 2 REG_CHNL_DMA_CFG			(Offset 0x037C) */
+
+#define BIT_TXHCI_EN BIT(26)
+#define BIT_TXHCI_IDLE BIT(25)
+#define BIT_DMA_PRI_EN BIT(24)
+#define BIT_PCIE_FWCMDQ_FLAG BIT(14)
+
+#define BIT_SHIFT_FWCMDQ_DESC_MODE 12
+#define BIT_MASK_FWCMDQ_DESC_MODE 0x3
+#define BIT_FWCMDQ_DESC_MODE(x)                                                \
+	(((x) & BIT_MASK_FWCMDQ_DESC_MODE) << BIT_SHIFT_FWCMDQ_DESC_MODE)
+#define BITS_FWCMDQ_DESC_MODE                                                  \
+	(BIT_MASK_FWCMDQ_DESC_MODE << BIT_SHIFT_FWCMDQ_DESC_MODE)
+#define BIT_CLEAR_FWCMDQ_DESC_MODE(x) ((x) & (~BITS_FWCMDQ_DESC_MODE))
+#define BIT_GET_FWCMDQ_DESC_MODE(x)                                            \
+	(((x) >> BIT_SHIFT_FWCMDQ_DESC_MODE) & BIT_MASK_FWCMDQ_DESC_MODE)
+#define BIT_SET_FWCMDQ_DESC_MODE(x, v)                                         \
+	(BIT_CLEAR_FWCMDQ_DESC_MODE(x) | BIT_FWCMDQ_DESC_MODE(v))
+
+#define BIT_SHIFT_FWCMDQ_DESC_NUM 0
+#define BIT_MASK_FWCMDQ_DESC_NUM 0xfff
+#define BIT_FWCMDQ_DESC_NUM(x)                                                 \
+	(((x) & BIT_MASK_FWCMDQ_DESC_NUM) << BIT_SHIFT_FWCMDQ_DESC_NUM)
+#define BITS_FWCMDQ_DESC_NUM                                                   \
+	(BIT_MASK_FWCMDQ_DESC_NUM << BIT_SHIFT_FWCMDQ_DESC_NUM)
+#define BIT_CLEAR_FWCMDQ_DESC_NUM(x) ((x) & (~BITS_FWCMDQ_DESC_NUM))
+#define BIT_GET_FWCMDQ_DESC_NUM(x)                                             \
+	(((x) >> BIT_SHIFT_FWCMDQ_DESC_NUM) & BIT_MASK_FWCMDQ_DESC_NUM)
+#define BIT_SET_FWCMDQ_DESC_NUM(x, v)                                          \
+	(BIT_CLEAR_FWCMDQ_DESC_NUM(x) | BIT_FWCMDQ_DESC_NUM(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_MGQ_TXBD_NUM			(Offset 0x0380) */
+
+#define BIT_PCIE_MGQ_FLAG BIT(14)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_MGQ_TXBD_NUM			(Offset 0x0380) */
+
+#define BIT_HCI_MGQ_FLAG BIT(14)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_MGQ_TXBD_NUM			(Offset 0x0380) */
+
+#define BIT_SHIFT_MGQ_DESC_MODE 12
+#define BIT_MASK_MGQ_DESC_MODE 0x3
+#define BIT_MGQ_DESC_MODE(x)                                                   \
+	(((x) & BIT_MASK_MGQ_DESC_MODE) << BIT_SHIFT_MGQ_DESC_MODE)
+#define BITS_MGQ_DESC_MODE (BIT_MASK_MGQ_DESC_MODE << BIT_SHIFT_MGQ_DESC_MODE)
+#define BIT_CLEAR_MGQ_DESC_MODE(x) ((x) & (~BITS_MGQ_DESC_MODE))
+#define BIT_GET_MGQ_DESC_MODE(x)                                               \
+	(((x) >> BIT_SHIFT_MGQ_DESC_MODE) & BIT_MASK_MGQ_DESC_MODE)
+#define BIT_SET_MGQ_DESC_MODE(x, v)                                            \
+	(BIT_CLEAR_MGQ_DESC_MODE(x) | BIT_MGQ_DESC_MODE(v))
+
+#define BIT_SHIFT_MGQ_DESC_NUM 0
+#define BIT_MASK_MGQ_DESC_NUM 0xfff
+#define BIT_MGQ_DESC_NUM(x)                                                    \
+	(((x) & BIT_MASK_MGQ_DESC_NUM) << BIT_SHIFT_MGQ_DESC_NUM)
+#define BITS_MGQ_DESC_NUM (BIT_MASK_MGQ_DESC_NUM << BIT_SHIFT_MGQ_DESC_NUM)
+#define BIT_CLEAR_MGQ_DESC_NUM(x) ((x) & (~BITS_MGQ_DESC_NUM))
+#define BIT_GET_MGQ_DESC_NUM(x)                                                \
+	(((x) >> BIT_SHIFT_MGQ_DESC_NUM) & BIT_MASK_MGQ_DESC_NUM)
+#define BIT_SET_MGQ_DESC_NUM(x, v)                                             \
+	(BIT_CLEAR_MGQ_DESC_NUM(x) | BIT_MGQ_DESC_NUM(v))
+
+/* 2 REG_RX_RXBD_NUM				(Offset 0x0382) */
+
+#define BIT_SYS_32_64 BIT(15)
+
+#define BIT_SHIFT_BCNQ_DESC_MODE 13
+#define BIT_MASK_BCNQ_DESC_MODE 0x3
+#define BIT_BCNQ_DESC_MODE(x)                                                  \
+	(((x) & BIT_MASK_BCNQ_DESC_MODE) << BIT_SHIFT_BCNQ_DESC_MODE)
+#define BITS_BCNQ_DESC_MODE                                                    \
+	(BIT_MASK_BCNQ_DESC_MODE << BIT_SHIFT_BCNQ_DESC_MODE)
+#define BIT_CLEAR_BCNQ_DESC_MODE(x) ((x) & (~BITS_BCNQ_DESC_MODE))
+#define BIT_GET_BCNQ_DESC_MODE(x)                                              \
+	(((x) >> BIT_SHIFT_BCNQ_DESC_MODE) & BIT_MASK_BCNQ_DESC_MODE)
+#define BIT_SET_BCNQ_DESC_MODE(x, v)                                           \
+	(BIT_CLEAR_BCNQ_DESC_MODE(x) | BIT_BCNQ_DESC_MODE(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_RX_RXBD_NUM				(Offset 0x0382) */
+
+#define BIT_PCIE_BCNQ_FLAG BIT(12)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_RX_RXBD_NUM				(Offset 0x0382) */
+
+#define BIT_HCI_BCNQ_FLAG BIT(12)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_RX_RXBD_NUM				(Offset 0x0382) */
+
+#define BIT_SHIFT_RXQ_DESC_NUM 0
+#define BIT_MASK_RXQ_DESC_NUM 0xfff
+#define BIT_RXQ_DESC_NUM(x)                                                    \
+	(((x) & BIT_MASK_RXQ_DESC_NUM) << BIT_SHIFT_RXQ_DESC_NUM)
+#define BITS_RXQ_DESC_NUM (BIT_MASK_RXQ_DESC_NUM << BIT_SHIFT_RXQ_DESC_NUM)
+#define BIT_CLEAR_RXQ_DESC_NUM(x) ((x) & (~BITS_RXQ_DESC_NUM))
+#define BIT_GET_RXQ_DESC_NUM(x)                                                \
+	(((x) >> BIT_SHIFT_RXQ_DESC_NUM) & BIT_MASK_RXQ_DESC_NUM)
+#define BIT_SET_RXQ_DESC_NUM(x, v)                                             \
+	(BIT_CLEAR_RXQ_DESC_NUM(x) | BIT_RXQ_DESC_NUM(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_ACH0_ACH1_TXBD_NUM			(Offset 0x0384) */
+
+#define BIT_PCIE_ACH1_FLAG_V1 BIT(30)
+
+#define BIT_SHIFT_ACH1_DESC_MODE_V1 28
+#define BIT_MASK_ACH1_DESC_MODE_V1 0x3
+#define BIT_ACH1_DESC_MODE_V1(x)                                               \
+	(((x) & BIT_MASK_ACH1_DESC_MODE_V1) << BIT_SHIFT_ACH1_DESC_MODE_V1)
+#define BITS_ACH1_DESC_MODE_V1                                                 \
+	(BIT_MASK_ACH1_DESC_MODE_V1 << BIT_SHIFT_ACH1_DESC_MODE_V1)
+#define BIT_CLEAR_ACH1_DESC_MODE_V1(x) ((x) & (~BITS_ACH1_DESC_MODE_V1))
+#define BIT_GET_ACH1_DESC_MODE_V1(x)                                           \
+	(((x) >> BIT_SHIFT_ACH1_DESC_MODE_V1) & BIT_MASK_ACH1_DESC_MODE_V1)
+#define BIT_SET_ACH1_DESC_MODE_V1(x, v)                                        \
+	(BIT_CLEAR_ACH1_DESC_MODE_V1(x) | BIT_ACH1_DESC_MODE_V1(v))
+
+#define BIT_SHIFT_ACH1_DESC_NUM_V1 16
+#define BIT_MASK_ACH1_DESC_NUM_V1 0xfff
+#define BIT_ACH1_DESC_NUM_V1(x)                                                \
+	(((x) & BIT_MASK_ACH1_DESC_NUM_V1) << BIT_SHIFT_ACH1_DESC_NUM_V1)
+#define BITS_ACH1_DESC_NUM_V1                                                  \
+	(BIT_MASK_ACH1_DESC_NUM_V1 << BIT_SHIFT_ACH1_DESC_NUM_V1)
+#define BIT_CLEAR_ACH1_DESC_NUM_V1(x) ((x) & (~BITS_ACH1_DESC_NUM_V1))
+#define BIT_GET_ACH1_DESC_NUM_V1(x)                                            \
+	(((x) >> BIT_SHIFT_ACH1_DESC_NUM_V1) & BIT_MASK_ACH1_DESC_NUM_V1)
+#define BIT_SET_ACH1_DESC_NUM_V1(x, v)                                         \
+	(BIT_CLEAR_ACH1_DESC_NUM_V1(x) | BIT_ACH1_DESC_NUM_V1(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_VOQ_TXBD_NUM			(Offset 0x0384) */
+
+#define BIT_PCIE_VOQ_FLAG BIT(14)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_VOQ_TXBD_NUM			(Offset 0x0384) */
+
+#define BIT_HCI_VOQ_FLAG BIT(14)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_ACH0_ACH1_TXBD_NUM			(Offset 0x0384) */
+
+#define BIT_PCIE_ACH0_FLAG BIT(14)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_VOQ_TXBD_NUM			(Offset 0x0384) */
+
+#define BIT_SHIFT_VOQ_DESC_MODE 12
+#define BIT_MASK_VOQ_DESC_MODE 0x3
+#define BIT_VOQ_DESC_MODE(x)                                                   \
+	(((x) & BIT_MASK_VOQ_DESC_MODE) << BIT_SHIFT_VOQ_DESC_MODE)
+#define BITS_VOQ_DESC_MODE (BIT_MASK_VOQ_DESC_MODE << BIT_SHIFT_VOQ_DESC_MODE)
+#define BIT_CLEAR_VOQ_DESC_MODE(x) ((x) & (~BITS_VOQ_DESC_MODE))
+#define BIT_GET_VOQ_DESC_MODE(x)                                               \
+	(((x) >> BIT_SHIFT_VOQ_DESC_MODE) & BIT_MASK_VOQ_DESC_MODE)
+#define BIT_SET_VOQ_DESC_MODE(x, v)                                            \
+	(BIT_CLEAR_VOQ_DESC_MODE(x) | BIT_VOQ_DESC_MODE(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_ACH0_ACH1_TXBD_NUM			(Offset 0x0384) */
+
+#define BIT_SHIFT_ACH0_DESC_MODE 12
+#define BIT_MASK_ACH0_DESC_MODE 0x3
+#define BIT_ACH0_DESC_MODE(x)                                                  \
+	(((x) & BIT_MASK_ACH0_DESC_MODE) << BIT_SHIFT_ACH0_DESC_MODE)
+#define BITS_ACH0_DESC_MODE                                                    \
+	(BIT_MASK_ACH0_DESC_MODE << BIT_SHIFT_ACH0_DESC_MODE)
+#define BIT_CLEAR_ACH0_DESC_MODE(x) ((x) & (~BITS_ACH0_DESC_MODE))
+#define BIT_GET_ACH0_DESC_MODE(x)                                              \
+	(((x) >> BIT_SHIFT_ACH0_DESC_MODE) & BIT_MASK_ACH0_DESC_MODE)
+#define BIT_SET_ACH0_DESC_MODE(x, v)                                           \
+	(BIT_CLEAR_ACH0_DESC_MODE(x) | BIT_ACH0_DESC_MODE(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_VOQ_TXBD_NUM			(Offset 0x0384) */
+
+#define BIT_SHIFT_VOQ_DESC_NUM 0
+#define BIT_MASK_VOQ_DESC_NUM 0xfff
+#define BIT_VOQ_DESC_NUM(x)                                                    \
+	(((x) & BIT_MASK_VOQ_DESC_NUM) << BIT_SHIFT_VOQ_DESC_NUM)
+#define BITS_VOQ_DESC_NUM (BIT_MASK_VOQ_DESC_NUM << BIT_SHIFT_VOQ_DESC_NUM)
+#define BIT_CLEAR_VOQ_DESC_NUM(x) ((x) & (~BITS_VOQ_DESC_NUM))
+#define BIT_GET_VOQ_DESC_NUM(x)                                                \
+	(((x) >> BIT_SHIFT_VOQ_DESC_NUM) & BIT_MASK_VOQ_DESC_NUM)
+#define BIT_SET_VOQ_DESC_NUM(x, v)                                             \
+	(BIT_CLEAR_VOQ_DESC_NUM(x) | BIT_VOQ_DESC_NUM(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_ACH0_ACH1_TXBD_NUM			(Offset 0x0384) */
+
+#define BIT_SHIFT_ACH0_DESC_NUM 0
+#define BIT_MASK_ACH0_DESC_NUM 0xfff
+#define BIT_ACH0_DESC_NUM(x)                                                   \
+	(((x) & BIT_MASK_ACH0_DESC_NUM) << BIT_SHIFT_ACH0_DESC_NUM)
+#define BITS_ACH0_DESC_NUM (BIT_MASK_ACH0_DESC_NUM << BIT_SHIFT_ACH0_DESC_NUM)
+#define BIT_CLEAR_ACH0_DESC_NUM(x) ((x) & (~BITS_ACH0_DESC_NUM))
+#define BIT_GET_ACH0_DESC_NUM(x)                                               \
+	(((x) >> BIT_SHIFT_ACH0_DESC_NUM) & BIT_MASK_ACH0_DESC_NUM)
+#define BIT_SET_ACH0_DESC_NUM(x, v)                                            \
+	(BIT_CLEAR_ACH0_DESC_NUM(x) | BIT_ACH0_DESC_NUM(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_VIQ_TXBD_NUM			(Offset 0x0386) */
+
+#define BIT_PCIE_VIQ_FLAG BIT(14)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_VIQ_TXBD_NUM			(Offset 0x0386) */
+
+#define BIT_HCI_VIQ_FLAG BIT(14)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_VIQ_TXBD_NUM			(Offset 0x0386) */
+
+#define BIT_SHIFT_VIQ_DESC_MODE 12
+#define BIT_MASK_VIQ_DESC_MODE 0x3
+#define BIT_VIQ_DESC_MODE(x)                                                   \
+	(((x) & BIT_MASK_VIQ_DESC_MODE) << BIT_SHIFT_VIQ_DESC_MODE)
+#define BITS_VIQ_DESC_MODE (BIT_MASK_VIQ_DESC_MODE << BIT_SHIFT_VIQ_DESC_MODE)
+#define BIT_CLEAR_VIQ_DESC_MODE(x) ((x) & (~BITS_VIQ_DESC_MODE))
+#define BIT_GET_VIQ_DESC_MODE(x)                                               \
+	(((x) >> BIT_SHIFT_VIQ_DESC_MODE) & BIT_MASK_VIQ_DESC_MODE)
+#define BIT_SET_VIQ_DESC_MODE(x, v)                                            \
+	(BIT_CLEAR_VIQ_DESC_MODE(x) | BIT_VIQ_DESC_MODE(v))
+
+#define BIT_SHIFT_VIQ_DESC_NUM 0
+#define BIT_MASK_VIQ_DESC_NUM 0xfff
+#define BIT_VIQ_DESC_NUM(x)                                                    \
+	(((x) & BIT_MASK_VIQ_DESC_NUM) << BIT_SHIFT_VIQ_DESC_NUM)
+#define BITS_VIQ_DESC_NUM (BIT_MASK_VIQ_DESC_NUM << BIT_SHIFT_VIQ_DESC_NUM)
+#define BIT_CLEAR_VIQ_DESC_NUM(x) ((x) & (~BITS_VIQ_DESC_NUM))
+#define BIT_GET_VIQ_DESC_NUM(x)                                                \
+	(((x) >> BIT_SHIFT_VIQ_DESC_NUM) & BIT_MASK_VIQ_DESC_NUM)
+#define BIT_SET_VIQ_DESC_NUM(x, v)                                             \
+	(BIT_CLEAR_VIQ_DESC_NUM(x) | BIT_VIQ_DESC_NUM(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_ACH2_ACH3_TXBD_NUM			(Offset 0x0388) */
+
+#define BIT_PCIE_ACH3_FLAG_V1 BIT(30)
+
+#define BIT_SHIFT_ACH3_DESC_MODE_V1 28
+#define BIT_MASK_ACH3_DESC_MODE_V1 0x3
+#define BIT_ACH3_DESC_MODE_V1(x)                                               \
+	(((x) & BIT_MASK_ACH3_DESC_MODE_V1) << BIT_SHIFT_ACH3_DESC_MODE_V1)
+#define BITS_ACH3_DESC_MODE_V1                                                 \
+	(BIT_MASK_ACH3_DESC_MODE_V1 << BIT_SHIFT_ACH3_DESC_MODE_V1)
+#define BIT_CLEAR_ACH3_DESC_MODE_V1(x) ((x) & (~BITS_ACH3_DESC_MODE_V1))
+#define BIT_GET_ACH3_DESC_MODE_V1(x)                                           \
+	(((x) >> BIT_SHIFT_ACH3_DESC_MODE_V1) & BIT_MASK_ACH3_DESC_MODE_V1)
+#define BIT_SET_ACH3_DESC_MODE_V1(x, v)                                        \
+	(BIT_CLEAR_ACH3_DESC_MODE_V1(x) | BIT_ACH3_DESC_MODE_V1(v))
+
+#define BIT_SHIFT_ACH3_DESC_NUM_V1 16
+#define BIT_MASK_ACH3_DESC_NUM_V1 0xfff
+#define BIT_ACH3_DESC_NUM_V1(x)                                                \
+	(((x) & BIT_MASK_ACH3_DESC_NUM_V1) << BIT_SHIFT_ACH3_DESC_NUM_V1)
+#define BITS_ACH3_DESC_NUM_V1                                                  \
+	(BIT_MASK_ACH3_DESC_NUM_V1 << BIT_SHIFT_ACH3_DESC_NUM_V1)
+#define BIT_CLEAR_ACH3_DESC_NUM_V1(x) ((x) & (~BITS_ACH3_DESC_NUM_V1))
+#define BIT_GET_ACH3_DESC_NUM_V1(x)                                            \
+	(((x) >> BIT_SHIFT_ACH3_DESC_NUM_V1) & BIT_MASK_ACH3_DESC_NUM_V1)
+#define BIT_SET_ACH3_DESC_NUM_V1(x, v)                                         \
+	(BIT_CLEAR_ACH3_DESC_NUM_V1(x) | BIT_ACH3_DESC_NUM_V1(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_BEQ_TXBD_NUM			(Offset 0x0388) */
+
+#define BIT_PCIE_BEQ_FLAG BIT(14)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_BEQ_TXBD_NUM			(Offset 0x0388) */
+
+#define BIT_HCI_BEQ_FLAG BIT(14)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_ACH2_ACH3_TXBD_NUM			(Offset 0x0388) */
+
+#define BIT_PCIE_ACH2_FLAG BIT(14)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_BEQ_TXBD_NUM			(Offset 0x0388) */
+
+#define BIT_SHIFT_BEQ_DESC_MODE 12
+#define BIT_MASK_BEQ_DESC_MODE 0x3
+#define BIT_BEQ_DESC_MODE(x)                                                   \
+	(((x) & BIT_MASK_BEQ_DESC_MODE) << BIT_SHIFT_BEQ_DESC_MODE)
+#define BITS_BEQ_DESC_MODE (BIT_MASK_BEQ_DESC_MODE << BIT_SHIFT_BEQ_DESC_MODE)
+#define BIT_CLEAR_BEQ_DESC_MODE(x) ((x) & (~BITS_BEQ_DESC_MODE))
+#define BIT_GET_BEQ_DESC_MODE(x)                                               \
+	(((x) >> BIT_SHIFT_BEQ_DESC_MODE) & BIT_MASK_BEQ_DESC_MODE)
+#define BIT_SET_BEQ_DESC_MODE(x, v)                                            \
+	(BIT_CLEAR_BEQ_DESC_MODE(x) | BIT_BEQ_DESC_MODE(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_ACH2_ACH3_TXBD_NUM			(Offset 0x0388) */
+
+#define BIT_SHIFT_ACH2_DESC_MODE 12
+#define BIT_MASK_ACH2_DESC_MODE 0x3
+#define BIT_ACH2_DESC_MODE(x)                                                  \
+	(((x) & BIT_MASK_ACH2_DESC_MODE) << BIT_SHIFT_ACH2_DESC_MODE)
+#define BITS_ACH2_DESC_MODE                                                    \
+	(BIT_MASK_ACH2_DESC_MODE << BIT_SHIFT_ACH2_DESC_MODE)
+#define BIT_CLEAR_ACH2_DESC_MODE(x) ((x) & (~BITS_ACH2_DESC_MODE))
+#define BIT_GET_ACH2_DESC_MODE(x)                                              \
+	(((x) >> BIT_SHIFT_ACH2_DESC_MODE) & BIT_MASK_ACH2_DESC_MODE)
+#define BIT_SET_ACH2_DESC_MODE(x, v)                                           \
+	(BIT_CLEAR_ACH2_DESC_MODE(x) | BIT_ACH2_DESC_MODE(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_BEQ_TXBD_NUM			(Offset 0x0388) */
+
+#define BIT_SHIFT_BEQ_DESC_NUM 0
+#define BIT_MASK_BEQ_DESC_NUM 0xfff
+#define BIT_BEQ_DESC_NUM(x)                                                    \
+	(((x) & BIT_MASK_BEQ_DESC_NUM) << BIT_SHIFT_BEQ_DESC_NUM)
+#define BITS_BEQ_DESC_NUM (BIT_MASK_BEQ_DESC_NUM << BIT_SHIFT_BEQ_DESC_NUM)
+#define BIT_CLEAR_BEQ_DESC_NUM(x) ((x) & (~BITS_BEQ_DESC_NUM))
+#define BIT_GET_BEQ_DESC_NUM(x)                                                \
+	(((x) >> BIT_SHIFT_BEQ_DESC_NUM) & BIT_MASK_BEQ_DESC_NUM)
+#define BIT_SET_BEQ_DESC_NUM(x, v)                                             \
+	(BIT_CLEAR_BEQ_DESC_NUM(x) | BIT_BEQ_DESC_NUM(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_ACH2_ACH3_TXBD_NUM			(Offset 0x0388) */
+
+#define BIT_SHIFT_ACH2_DESC_NUM 0
+#define BIT_MASK_ACH2_DESC_NUM 0xfff
+#define BIT_ACH2_DESC_NUM(x)                                                   \
+	(((x) & BIT_MASK_ACH2_DESC_NUM) << BIT_SHIFT_ACH2_DESC_NUM)
+#define BITS_ACH2_DESC_NUM (BIT_MASK_ACH2_DESC_NUM << BIT_SHIFT_ACH2_DESC_NUM)
+#define BIT_CLEAR_ACH2_DESC_NUM(x) ((x) & (~BITS_ACH2_DESC_NUM))
+#define BIT_GET_ACH2_DESC_NUM(x)                                               \
+	(((x) >> BIT_SHIFT_ACH2_DESC_NUM) & BIT_MASK_ACH2_DESC_NUM)
+#define BIT_SET_ACH2_DESC_NUM(x, v)                                            \
+	(BIT_CLEAR_ACH2_DESC_NUM(x) | BIT_ACH2_DESC_NUM(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_BKQ_TXBD_NUM			(Offset 0x038A) */
+
+#define BIT_PCIE_BKQ_FLAG BIT(14)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_BKQ_TXBD_NUM			(Offset 0x038A) */
+
+#define BIT_HCI_BKQ_FLAG BIT(14)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_BKQ_TXBD_NUM			(Offset 0x038A) */
+
+#define BIT_SHIFT_BKQ_DESC_MODE 12
+#define BIT_MASK_BKQ_DESC_MODE 0x3
+#define BIT_BKQ_DESC_MODE(x)                                                   \
+	(((x) & BIT_MASK_BKQ_DESC_MODE) << BIT_SHIFT_BKQ_DESC_MODE)
+#define BITS_BKQ_DESC_MODE (BIT_MASK_BKQ_DESC_MODE << BIT_SHIFT_BKQ_DESC_MODE)
+#define BIT_CLEAR_BKQ_DESC_MODE(x) ((x) & (~BITS_BKQ_DESC_MODE))
+#define BIT_GET_BKQ_DESC_MODE(x)                                               \
+	(((x) >> BIT_SHIFT_BKQ_DESC_MODE) & BIT_MASK_BKQ_DESC_MODE)
+#define BIT_SET_BKQ_DESC_MODE(x, v)                                            \
+	(BIT_CLEAR_BKQ_DESC_MODE(x) | BIT_BKQ_DESC_MODE(v))
+
+#define BIT_SHIFT_BKQ_DESC_NUM 0
+#define BIT_MASK_BKQ_DESC_NUM 0xfff
+#define BIT_BKQ_DESC_NUM(x)                                                    \
+	(((x) & BIT_MASK_BKQ_DESC_NUM) << BIT_SHIFT_BKQ_DESC_NUM)
+#define BITS_BKQ_DESC_NUM (BIT_MASK_BKQ_DESC_NUM << BIT_SHIFT_BKQ_DESC_NUM)
+#define BIT_CLEAR_BKQ_DESC_NUM(x) ((x) & (~BITS_BKQ_DESC_NUM))
+#define BIT_GET_BKQ_DESC_NUM(x)                                                \
+	(((x) >> BIT_SHIFT_BKQ_DESC_NUM) & BIT_MASK_BKQ_DESC_NUM)
+#define BIT_SET_BKQ_DESC_NUM(x, v)                                             \
+	(BIT_CLEAR_BKQ_DESC_NUM(x) | BIT_BKQ_DESC_NUM(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_P0HI0Q_HI1Q_TXBD_NUM		(Offset 0x038C) */
+
+#define BIT_P0HI1Q_FLAG BIT(30)
+
+#define BIT_SHIFT_P0HI1Q_DESC_MODE 28
+#define BIT_MASK_P0HI1Q_DESC_MODE 0x3
+#define BIT_P0HI1Q_DESC_MODE(x)                                                \
+	(((x) & BIT_MASK_P0HI1Q_DESC_MODE) << BIT_SHIFT_P0HI1Q_DESC_MODE)
+#define BITS_P0HI1Q_DESC_MODE                                                  \
+	(BIT_MASK_P0HI1Q_DESC_MODE << BIT_SHIFT_P0HI1Q_DESC_MODE)
+#define BIT_CLEAR_P0HI1Q_DESC_MODE(x) ((x) & (~BITS_P0HI1Q_DESC_MODE))
+#define BIT_GET_P0HI1Q_DESC_MODE(x)                                            \
+	(((x) >> BIT_SHIFT_P0HI1Q_DESC_MODE) & BIT_MASK_P0HI1Q_DESC_MODE)
+#define BIT_SET_P0HI1Q_DESC_MODE(x, v)                                         \
+	(BIT_CLEAR_P0HI1Q_DESC_MODE(x) | BIT_P0HI1Q_DESC_MODE(v))
+
+#define BIT_SHIFT_P0HI1Q_DESC_NUM 16
+#define BIT_MASK_P0HI1Q_DESC_NUM 0xfff
+#define BIT_P0HI1Q_DESC_NUM(x)                                                 \
+	(((x) & BIT_MASK_P0HI1Q_DESC_NUM) << BIT_SHIFT_P0HI1Q_DESC_NUM)
+#define BITS_P0HI1Q_DESC_NUM                                                   \
+	(BIT_MASK_P0HI1Q_DESC_NUM << BIT_SHIFT_P0HI1Q_DESC_NUM)
+#define BIT_CLEAR_P0HI1Q_DESC_NUM(x) ((x) & (~BITS_P0HI1Q_DESC_NUM))
+#define BIT_GET_P0HI1Q_DESC_NUM(x)                                             \
+	(((x) >> BIT_SHIFT_P0HI1Q_DESC_NUM) & BIT_MASK_P0HI1Q_DESC_NUM)
+#define BIT_SET_P0HI1Q_DESC_NUM(x, v)                                          \
+	(BIT_CLEAR_P0HI1Q_DESC_NUM(x) | BIT_P0HI1Q_DESC_NUM(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_HI0Q_TXBD_NUM			(Offset 0x038C) */
+
+#define BIT_HI0Q_FLAG BIT(14)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_P0HI0Q_HI1Q_TXBD_NUM		(Offset 0x038C) */
+
+#define BIT_P0HI0Q_FLAG BIT(14)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_HI0Q_TXBD_NUM			(Offset 0x038C) */
+
+#define BIT_SHIFT_HI0Q_DESC_MODE 12
+#define BIT_MASK_HI0Q_DESC_MODE 0x3
+#define BIT_HI0Q_DESC_MODE(x)                                                  \
+	(((x) & BIT_MASK_HI0Q_DESC_MODE) << BIT_SHIFT_HI0Q_DESC_MODE)
+#define BITS_HI0Q_DESC_MODE                                                    \
+	(BIT_MASK_HI0Q_DESC_MODE << BIT_SHIFT_HI0Q_DESC_MODE)
+#define BIT_CLEAR_HI0Q_DESC_MODE(x) ((x) & (~BITS_HI0Q_DESC_MODE))
+#define BIT_GET_HI0Q_DESC_MODE(x)                                              \
+	(((x) >> BIT_SHIFT_HI0Q_DESC_MODE) & BIT_MASK_HI0Q_DESC_MODE)
+#define BIT_SET_HI0Q_DESC_MODE(x, v)                                           \
+	(BIT_CLEAR_HI0Q_DESC_MODE(x) | BIT_HI0Q_DESC_MODE(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_P0HI0Q_HI1Q_TXBD_NUM		(Offset 0x038C) */
+
+#define BIT_SHIFT_P0HI0Q_DESC_MODE 12
+#define BIT_MASK_P0HI0Q_DESC_MODE 0x3
+#define BIT_P0HI0Q_DESC_MODE(x)                                                \
+	(((x) & BIT_MASK_P0HI0Q_DESC_MODE) << BIT_SHIFT_P0HI0Q_DESC_MODE)
+#define BITS_P0HI0Q_DESC_MODE                                                  \
+	(BIT_MASK_P0HI0Q_DESC_MODE << BIT_SHIFT_P0HI0Q_DESC_MODE)
+#define BIT_CLEAR_P0HI0Q_DESC_MODE(x) ((x) & (~BITS_P0HI0Q_DESC_MODE))
+#define BIT_GET_P0HI0Q_DESC_MODE(x)                                            \
+	(((x) >> BIT_SHIFT_P0HI0Q_DESC_MODE) & BIT_MASK_P0HI0Q_DESC_MODE)
+#define BIT_SET_P0HI0Q_DESC_MODE(x, v)                                         \
+	(BIT_CLEAR_P0HI0Q_DESC_MODE(x) | BIT_P0HI0Q_DESC_MODE(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_HI0Q_TXBD_NUM			(Offset 0x038C) */
+
+#define BIT_SHIFT_HI0Q_DESC_NUM 0
+#define BIT_MASK_HI0Q_DESC_NUM 0xfff
+#define BIT_HI0Q_DESC_NUM(x)                                                   \
+	(((x) & BIT_MASK_HI0Q_DESC_NUM) << BIT_SHIFT_HI0Q_DESC_NUM)
+#define BITS_HI0Q_DESC_NUM (BIT_MASK_HI0Q_DESC_NUM << BIT_SHIFT_HI0Q_DESC_NUM)
+#define BIT_CLEAR_HI0Q_DESC_NUM(x) ((x) & (~BITS_HI0Q_DESC_NUM))
+#define BIT_GET_HI0Q_DESC_NUM(x)                                               \
+	(((x) >> BIT_SHIFT_HI0Q_DESC_NUM) & BIT_MASK_HI0Q_DESC_NUM)
+#define BIT_SET_HI0Q_DESC_NUM(x, v)                                            \
+	(BIT_CLEAR_HI0Q_DESC_NUM(x) | BIT_HI0Q_DESC_NUM(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_P0HI0Q_HI1Q_TXBD_NUM		(Offset 0x038C) */
+
+#define BIT_SHIFT_P0HI0Q_DESC_NUM 0
+#define BIT_MASK_P0HI0Q_DESC_NUM 0xfff
+#define BIT_P0HI0Q_DESC_NUM(x)                                                 \
+	(((x) & BIT_MASK_P0HI0Q_DESC_NUM) << BIT_SHIFT_P0HI0Q_DESC_NUM)
+#define BITS_P0HI0Q_DESC_NUM                                                   \
+	(BIT_MASK_P0HI0Q_DESC_NUM << BIT_SHIFT_P0HI0Q_DESC_NUM)
+#define BIT_CLEAR_P0HI0Q_DESC_NUM(x) ((x) & (~BITS_P0HI0Q_DESC_NUM))
+#define BIT_GET_P0HI0Q_DESC_NUM(x)                                             \
+	(((x) >> BIT_SHIFT_P0HI0Q_DESC_NUM) & BIT_MASK_P0HI0Q_DESC_NUM)
+#define BIT_SET_P0HI0Q_DESC_NUM(x, v)                                          \
+	(BIT_CLEAR_P0HI0Q_DESC_NUM(x) | BIT_P0HI0Q_DESC_NUM(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_HI1Q_TXBD_NUM			(Offset 0x038E) */
+
+#define BIT_HI1Q_FLAG BIT(14)
+
+#define BIT_SHIFT_HI1Q_DESC_MODE 12
+#define BIT_MASK_HI1Q_DESC_MODE 0x3
+#define BIT_HI1Q_DESC_MODE(x)                                                  \
+	(((x) & BIT_MASK_HI1Q_DESC_MODE) << BIT_SHIFT_HI1Q_DESC_MODE)
+#define BITS_HI1Q_DESC_MODE                                                    \
+	(BIT_MASK_HI1Q_DESC_MODE << BIT_SHIFT_HI1Q_DESC_MODE)
+#define BIT_CLEAR_HI1Q_DESC_MODE(x) ((x) & (~BITS_HI1Q_DESC_MODE))
+#define BIT_GET_HI1Q_DESC_MODE(x)                                              \
+	(((x) >> BIT_SHIFT_HI1Q_DESC_MODE) & BIT_MASK_HI1Q_DESC_MODE)
+#define BIT_SET_HI1Q_DESC_MODE(x, v)                                           \
+	(BIT_CLEAR_HI1Q_DESC_MODE(x) | BIT_HI1Q_DESC_MODE(v))
+
+#define BIT_SHIFT_HI1Q_DESC_NUM 0
+#define BIT_MASK_HI1Q_DESC_NUM 0xfff
+#define BIT_HI1Q_DESC_NUM(x)                                                   \
+	(((x) & BIT_MASK_HI1Q_DESC_NUM) << BIT_SHIFT_HI1Q_DESC_NUM)
+#define BITS_HI1Q_DESC_NUM (BIT_MASK_HI1Q_DESC_NUM << BIT_SHIFT_HI1Q_DESC_NUM)
+#define BIT_CLEAR_HI1Q_DESC_NUM(x) ((x) & (~BITS_HI1Q_DESC_NUM))
+#define BIT_GET_HI1Q_DESC_NUM(x)                                               \
+	(((x) >> BIT_SHIFT_HI1Q_DESC_NUM) & BIT_MASK_HI1Q_DESC_NUM)
+#define BIT_SET_HI1Q_DESC_NUM(x, v)                                            \
+	(BIT_CLEAR_HI1Q_DESC_NUM(x) | BIT_HI1Q_DESC_NUM(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_P0HI2Q_HI3Q_TXBD_NUM		(Offset 0x0390) */
+
+#define BIT_P0HI3Q_FLAG BIT(30)
+
+#define BIT_SHIFT_P0HI3Q_DESC_MODE 28
+#define BIT_MASK_P0HI3Q_DESC_MODE 0x3
+#define BIT_P0HI3Q_DESC_MODE(x)                                                \
+	(((x) & BIT_MASK_P0HI3Q_DESC_MODE) << BIT_SHIFT_P0HI3Q_DESC_MODE)
+#define BITS_P0HI3Q_DESC_MODE                                                  \
+	(BIT_MASK_P0HI3Q_DESC_MODE << BIT_SHIFT_P0HI3Q_DESC_MODE)
+#define BIT_CLEAR_P0HI3Q_DESC_MODE(x) ((x) & (~BITS_P0HI3Q_DESC_MODE))
+#define BIT_GET_P0HI3Q_DESC_MODE(x)                                            \
+	(((x) >> BIT_SHIFT_P0HI3Q_DESC_MODE) & BIT_MASK_P0HI3Q_DESC_MODE)
+#define BIT_SET_P0HI3Q_DESC_MODE(x, v)                                         \
+	(BIT_CLEAR_P0HI3Q_DESC_MODE(x) | BIT_P0HI3Q_DESC_MODE(v))
+
+#define BIT_SHIFT_P0HI3Q_DESC_NUM 16
+#define BIT_MASK_P0HI3Q_DESC_NUM 0xfff
+#define BIT_P0HI3Q_DESC_NUM(x)                                                 \
+	(((x) & BIT_MASK_P0HI3Q_DESC_NUM) << BIT_SHIFT_P0HI3Q_DESC_NUM)
+#define BITS_P0HI3Q_DESC_NUM                                                   \
+	(BIT_MASK_P0HI3Q_DESC_NUM << BIT_SHIFT_P0HI3Q_DESC_NUM)
+#define BIT_CLEAR_P0HI3Q_DESC_NUM(x) ((x) & (~BITS_P0HI3Q_DESC_NUM))
+#define BIT_GET_P0HI3Q_DESC_NUM(x)                                             \
+	(((x) >> BIT_SHIFT_P0HI3Q_DESC_NUM) & BIT_MASK_P0HI3Q_DESC_NUM)
+#define BIT_SET_P0HI3Q_DESC_NUM(x, v)                                          \
+	(BIT_CLEAR_P0HI3Q_DESC_NUM(x) | BIT_P0HI3Q_DESC_NUM(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_HI2Q_TXBD_NUM			(Offset 0x0390) */
+
+#define BIT_HI2Q_FLAG BIT(14)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_P0HI2Q_HI3Q_TXBD_NUM		(Offset 0x0390) */
+
+#define BIT_P0HI2Q_FLAG BIT(14)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_HI2Q_TXBD_NUM			(Offset 0x0390) */
+
+#define BIT_SHIFT_HI2Q_DESC_MODE 12
+#define BIT_MASK_HI2Q_DESC_MODE 0x3
+#define BIT_HI2Q_DESC_MODE(x)                                                  \
+	(((x) & BIT_MASK_HI2Q_DESC_MODE) << BIT_SHIFT_HI2Q_DESC_MODE)
+#define BITS_HI2Q_DESC_MODE                                                    \
+	(BIT_MASK_HI2Q_DESC_MODE << BIT_SHIFT_HI2Q_DESC_MODE)
+#define BIT_CLEAR_HI2Q_DESC_MODE(x) ((x) & (~BITS_HI2Q_DESC_MODE))
+#define BIT_GET_HI2Q_DESC_MODE(x)                                              \
+	(((x) >> BIT_SHIFT_HI2Q_DESC_MODE) & BIT_MASK_HI2Q_DESC_MODE)
+#define BIT_SET_HI2Q_DESC_MODE(x, v)                                           \
+	(BIT_CLEAR_HI2Q_DESC_MODE(x) | BIT_HI2Q_DESC_MODE(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_P0HI2Q_HI3Q_TXBD_NUM		(Offset 0x0390) */
+
+#define BIT_SHIFT_P0HI2Q_DESC_MODE 12
+#define BIT_MASK_P0HI2Q_DESC_MODE 0x3
+#define BIT_P0HI2Q_DESC_MODE(x)                                                \
+	(((x) & BIT_MASK_P0HI2Q_DESC_MODE) << BIT_SHIFT_P0HI2Q_DESC_MODE)
+#define BITS_P0HI2Q_DESC_MODE                                                  \
+	(BIT_MASK_P0HI2Q_DESC_MODE << BIT_SHIFT_P0HI2Q_DESC_MODE)
+#define BIT_CLEAR_P0HI2Q_DESC_MODE(x) ((x) & (~BITS_P0HI2Q_DESC_MODE))
+#define BIT_GET_P0HI2Q_DESC_MODE(x)                                            \
+	(((x) >> BIT_SHIFT_P0HI2Q_DESC_MODE) & BIT_MASK_P0HI2Q_DESC_MODE)
+#define BIT_SET_P0HI2Q_DESC_MODE(x, v)                                         \
+	(BIT_CLEAR_P0HI2Q_DESC_MODE(x) | BIT_P0HI2Q_DESC_MODE(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_HI2Q_TXBD_NUM			(Offset 0x0390) */
+
+#define BIT_SHIFT_HI2Q_DESC_NUM 0
+#define BIT_MASK_HI2Q_DESC_NUM 0xfff
+#define BIT_HI2Q_DESC_NUM(x)                                                   \
+	(((x) & BIT_MASK_HI2Q_DESC_NUM) << BIT_SHIFT_HI2Q_DESC_NUM)
+#define BITS_HI2Q_DESC_NUM (BIT_MASK_HI2Q_DESC_NUM << BIT_SHIFT_HI2Q_DESC_NUM)
+#define BIT_CLEAR_HI2Q_DESC_NUM(x) ((x) & (~BITS_HI2Q_DESC_NUM))
+#define BIT_GET_HI2Q_DESC_NUM(x)                                               \
+	(((x) >> BIT_SHIFT_HI2Q_DESC_NUM) & BIT_MASK_HI2Q_DESC_NUM)
+#define BIT_SET_HI2Q_DESC_NUM(x, v)                                            \
+	(BIT_CLEAR_HI2Q_DESC_NUM(x) | BIT_HI2Q_DESC_NUM(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_P0HI2Q_HI3Q_TXBD_NUM		(Offset 0x0390) */
+
+#define BIT_SHIFT_P0HI2Q_DESC_NUM 0
+#define BIT_MASK_P0HI2Q_DESC_NUM 0xfff
+#define BIT_P0HI2Q_DESC_NUM(x)                                                 \
+	(((x) & BIT_MASK_P0HI2Q_DESC_NUM) << BIT_SHIFT_P0HI2Q_DESC_NUM)
+#define BITS_P0HI2Q_DESC_NUM                                                   \
+	(BIT_MASK_P0HI2Q_DESC_NUM << BIT_SHIFT_P0HI2Q_DESC_NUM)
+#define BIT_CLEAR_P0HI2Q_DESC_NUM(x) ((x) & (~BITS_P0HI2Q_DESC_NUM))
+#define BIT_GET_P0HI2Q_DESC_NUM(x)                                             \
+	(((x) >> BIT_SHIFT_P0HI2Q_DESC_NUM) & BIT_MASK_P0HI2Q_DESC_NUM)
+#define BIT_SET_P0HI2Q_DESC_NUM(x, v)                                          \
+	(BIT_CLEAR_P0HI2Q_DESC_NUM(x) | BIT_P0HI2Q_DESC_NUM(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_HI3Q_TXBD_NUM			(Offset 0x0392) */
+
+#define BIT_HI3Q_FLAG BIT(14)
+
+#define BIT_SHIFT_HI3Q_DESC_MODE 12
+#define BIT_MASK_HI3Q_DESC_MODE 0x3
+#define BIT_HI3Q_DESC_MODE(x)                                                  \
+	(((x) & BIT_MASK_HI3Q_DESC_MODE) << BIT_SHIFT_HI3Q_DESC_MODE)
+#define BITS_HI3Q_DESC_MODE                                                    \
+	(BIT_MASK_HI3Q_DESC_MODE << BIT_SHIFT_HI3Q_DESC_MODE)
+#define BIT_CLEAR_HI3Q_DESC_MODE(x) ((x) & (~BITS_HI3Q_DESC_MODE))
+#define BIT_GET_HI3Q_DESC_MODE(x)                                              \
+	(((x) >> BIT_SHIFT_HI3Q_DESC_MODE) & BIT_MASK_HI3Q_DESC_MODE)
+#define BIT_SET_HI3Q_DESC_MODE(x, v)                                           \
+	(BIT_CLEAR_HI3Q_DESC_MODE(x) | BIT_HI3Q_DESC_MODE(v))
+
+#define BIT_SHIFT_HI3Q_DESC_NUM 0
+#define BIT_MASK_HI3Q_DESC_NUM 0xfff
+#define BIT_HI3Q_DESC_NUM(x)                                                   \
+	(((x) & BIT_MASK_HI3Q_DESC_NUM) << BIT_SHIFT_HI3Q_DESC_NUM)
+#define BITS_HI3Q_DESC_NUM (BIT_MASK_HI3Q_DESC_NUM << BIT_SHIFT_HI3Q_DESC_NUM)
+#define BIT_CLEAR_HI3Q_DESC_NUM(x) ((x) & (~BITS_HI3Q_DESC_NUM))
+#define BIT_GET_HI3Q_DESC_NUM(x)                                               \
+	(((x) >> BIT_SHIFT_HI3Q_DESC_NUM) & BIT_MASK_HI3Q_DESC_NUM)
+#define BIT_SET_HI3Q_DESC_NUM(x, v)                                            \
+	(BIT_CLEAR_HI3Q_DESC_NUM(x) | BIT_HI3Q_DESC_NUM(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_P0HI4Q_HI5Q_TXBD_NUM		(Offset 0x0394) */
+
+#define BIT_P0HI5Q_FLAG BIT(30)
+
+#define BIT_SHIFT_P0HI5Q_DESC_MODE 28
+#define BIT_MASK_P0HI5Q_DESC_MODE 0x3
+#define BIT_P0HI5Q_DESC_MODE(x)                                                \
+	(((x) & BIT_MASK_P0HI5Q_DESC_MODE) << BIT_SHIFT_P0HI5Q_DESC_MODE)
+#define BITS_P0HI5Q_DESC_MODE                                                  \
+	(BIT_MASK_P0HI5Q_DESC_MODE << BIT_SHIFT_P0HI5Q_DESC_MODE)
+#define BIT_CLEAR_P0HI5Q_DESC_MODE(x) ((x) & (~BITS_P0HI5Q_DESC_MODE))
+#define BIT_GET_P0HI5Q_DESC_MODE(x)                                            \
+	(((x) >> BIT_SHIFT_P0HI5Q_DESC_MODE) & BIT_MASK_P0HI5Q_DESC_MODE)
+#define BIT_SET_P0HI5Q_DESC_MODE(x, v)                                         \
+	(BIT_CLEAR_P0HI5Q_DESC_MODE(x) | BIT_P0HI5Q_DESC_MODE(v))
+
+#define BIT_SHIFT_P0HI5Q_DESC_NUM 16
+#define BIT_MASK_P0HI5Q_DESC_NUM 0xfff
+#define BIT_P0HI5Q_DESC_NUM(x)                                                 \
+	(((x) & BIT_MASK_P0HI5Q_DESC_NUM) << BIT_SHIFT_P0HI5Q_DESC_NUM)
+#define BITS_P0HI5Q_DESC_NUM                                                   \
+	(BIT_MASK_P0HI5Q_DESC_NUM << BIT_SHIFT_P0HI5Q_DESC_NUM)
+#define BIT_CLEAR_P0HI5Q_DESC_NUM(x) ((x) & (~BITS_P0HI5Q_DESC_NUM))
+#define BIT_GET_P0HI5Q_DESC_NUM(x)                                             \
+	(((x) >> BIT_SHIFT_P0HI5Q_DESC_NUM) & BIT_MASK_P0HI5Q_DESC_NUM)
+#define BIT_SET_P0HI5Q_DESC_NUM(x, v)                                          \
+	(BIT_CLEAR_P0HI5Q_DESC_NUM(x) | BIT_P0HI5Q_DESC_NUM(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_HI4Q_TXBD_NUM			(Offset 0x0394) */
+
+#define BIT_HI4Q_FLAG BIT(14)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_P0HI4Q_HI5Q_TXBD_NUM		(Offset 0x0394) */
+
+#define BIT_P0HI4Q_FLAG BIT(14)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_HI4Q_TXBD_NUM			(Offset 0x0394) */
+
+#define BIT_SHIFT_HI4Q_DESC_MODE 12
+#define BIT_MASK_HI4Q_DESC_MODE 0x3
+#define BIT_HI4Q_DESC_MODE(x)                                                  \
+	(((x) & BIT_MASK_HI4Q_DESC_MODE) << BIT_SHIFT_HI4Q_DESC_MODE)
+#define BITS_HI4Q_DESC_MODE                                                    \
+	(BIT_MASK_HI4Q_DESC_MODE << BIT_SHIFT_HI4Q_DESC_MODE)
+#define BIT_CLEAR_HI4Q_DESC_MODE(x) ((x) & (~BITS_HI4Q_DESC_MODE))
+#define BIT_GET_HI4Q_DESC_MODE(x)                                              \
+	(((x) >> BIT_SHIFT_HI4Q_DESC_MODE) & BIT_MASK_HI4Q_DESC_MODE)
+#define BIT_SET_HI4Q_DESC_MODE(x, v)                                           \
+	(BIT_CLEAR_HI4Q_DESC_MODE(x) | BIT_HI4Q_DESC_MODE(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_P0HI4Q_HI5Q_TXBD_NUM		(Offset 0x0394) */
+
+#define BIT_SHIFT_P0HI4Q_DESC_MODE 12
+#define BIT_MASK_P0HI4Q_DESC_MODE 0x3
+#define BIT_P0HI4Q_DESC_MODE(x)                                                \
+	(((x) & BIT_MASK_P0HI4Q_DESC_MODE) << BIT_SHIFT_P0HI4Q_DESC_MODE)
+#define BITS_P0HI4Q_DESC_MODE                                                  \
+	(BIT_MASK_P0HI4Q_DESC_MODE << BIT_SHIFT_P0HI4Q_DESC_MODE)
+#define BIT_CLEAR_P0HI4Q_DESC_MODE(x) ((x) & (~BITS_P0HI4Q_DESC_MODE))
+#define BIT_GET_P0HI4Q_DESC_MODE(x)                                            \
+	(((x) >> BIT_SHIFT_P0HI4Q_DESC_MODE) & BIT_MASK_P0HI4Q_DESC_MODE)
+#define BIT_SET_P0HI4Q_DESC_MODE(x, v)                                         \
+	(BIT_CLEAR_P0HI4Q_DESC_MODE(x) | BIT_P0HI4Q_DESC_MODE(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_HI4Q_TXBD_NUM			(Offset 0x0394) */
+
+#define BIT_SHIFT_HI4Q_DESC_NUM 0
+#define BIT_MASK_HI4Q_DESC_NUM 0xfff
+#define BIT_HI4Q_DESC_NUM(x)                                                   \
+	(((x) & BIT_MASK_HI4Q_DESC_NUM) << BIT_SHIFT_HI4Q_DESC_NUM)
+#define BITS_HI4Q_DESC_NUM (BIT_MASK_HI4Q_DESC_NUM << BIT_SHIFT_HI4Q_DESC_NUM)
+#define BIT_CLEAR_HI4Q_DESC_NUM(x) ((x) & (~BITS_HI4Q_DESC_NUM))
+#define BIT_GET_HI4Q_DESC_NUM(x)                                               \
+	(((x) >> BIT_SHIFT_HI4Q_DESC_NUM) & BIT_MASK_HI4Q_DESC_NUM)
+#define BIT_SET_HI4Q_DESC_NUM(x, v)                                            \
+	(BIT_CLEAR_HI4Q_DESC_NUM(x) | BIT_HI4Q_DESC_NUM(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_P0HI4Q_HI5Q_TXBD_NUM		(Offset 0x0394) */
+
+#define BIT_SHIFT_P0HI4Q_DESC_NUM 0
+#define BIT_MASK_P0HI4Q_DESC_NUM 0xfff
+#define BIT_P0HI4Q_DESC_NUM(x)                                                 \
+	(((x) & BIT_MASK_P0HI4Q_DESC_NUM) << BIT_SHIFT_P0HI4Q_DESC_NUM)
+#define BITS_P0HI4Q_DESC_NUM                                                   \
+	(BIT_MASK_P0HI4Q_DESC_NUM << BIT_SHIFT_P0HI4Q_DESC_NUM)
+#define BIT_CLEAR_P0HI4Q_DESC_NUM(x) ((x) & (~BITS_P0HI4Q_DESC_NUM))
+#define BIT_GET_P0HI4Q_DESC_NUM(x)                                             \
+	(((x) >> BIT_SHIFT_P0HI4Q_DESC_NUM) & BIT_MASK_P0HI4Q_DESC_NUM)
+#define BIT_SET_P0HI4Q_DESC_NUM(x, v)                                          \
+	(BIT_CLEAR_P0HI4Q_DESC_NUM(x) | BIT_P0HI4Q_DESC_NUM(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_HI5Q_TXBD_NUM			(Offset 0x0396) */
+
+#define BIT_HI5Q_FLAG BIT(14)
+
+#define BIT_SHIFT_HI5Q_DESC_MODE 12
+#define BIT_MASK_HI5Q_DESC_MODE 0x3
+#define BIT_HI5Q_DESC_MODE(x)                                                  \
+	(((x) & BIT_MASK_HI5Q_DESC_MODE) << BIT_SHIFT_HI5Q_DESC_MODE)
+#define BITS_HI5Q_DESC_MODE                                                    \
+	(BIT_MASK_HI5Q_DESC_MODE << BIT_SHIFT_HI5Q_DESC_MODE)
+#define BIT_CLEAR_HI5Q_DESC_MODE(x) ((x) & (~BITS_HI5Q_DESC_MODE))
+#define BIT_GET_HI5Q_DESC_MODE(x)                                              \
+	(((x) >> BIT_SHIFT_HI5Q_DESC_MODE) & BIT_MASK_HI5Q_DESC_MODE)
+#define BIT_SET_HI5Q_DESC_MODE(x, v)                                           \
+	(BIT_CLEAR_HI5Q_DESC_MODE(x) | BIT_HI5Q_DESC_MODE(v))
+
+#define BIT_SHIFT_HI5Q_DESC_NUM 0
+#define BIT_MASK_HI5Q_DESC_NUM 0xfff
+#define BIT_HI5Q_DESC_NUM(x)                                                   \
+	(((x) & BIT_MASK_HI5Q_DESC_NUM) << BIT_SHIFT_HI5Q_DESC_NUM)
+#define BITS_HI5Q_DESC_NUM (BIT_MASK_HI5Q_DESC_NUM << BIT_SHIFT_HI5Q_DESC_NUM)
+#define BIT_CLEAR_HI5Q_DESC_NUM(x) ((x) & (~BITS_HI5Q_DESC_NUM))
+#define BIT_GET_HI5Q_DESC_NUM(x)                                               \
+	(((x) >> BIT_SHIFT_HI5Q_DESC_NUM) & BIT_MASK_HI5Q_DESC_NUM)
+#define BIT_SET_HI5Q_DESC_NUM(x, v)                                            \
+	(BIT_CLEAR_HI5Q_DESC_NUM(x) | BIT_HI5Q_DESC_NUM(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_P0HI6Q_HI7Q_TXBD_NUM		(Offset 0x0398) */
+
+#define BIT_P0HI7Q_FLAG BIT(30)
+#define BIT_CLR_FWCMDQ_HW_IDX BIT(30)
+#define BIT_CLR_P0HI7Q_HW_IDX BIT(29)
+
+#define BIT_SHIFT_P0HI7Q_DESC_MODE 28
+#define BIT_MASK_P0HI7Q_DESC_MODE 0x3
+#define BIT_P0HI7Q_DESC_MODE(x)                                                \
+	(((x) & BIT_MASK_P0HI7Q_DESC_MODE) << BIT_SHIFT_P0HI7Q_DESC_MODE)
+#define BITS_P0HI7Q_DESC_MODE                                                  \
+	(BIT_MASK_P0HI7Q_DESC_MODE << BIT_SHIFT_P0HI7Q_DESC_MODE)
+#define BIT_CLEAR_P0HI7Q_DESC_MODE(x) ((x) & (~BITS_P0HI7Q_DESC_MODE))
+#define BIT_GET_P0HI7Q_DESC_MODE(x)                                            \
+	(((x) >> BIT_SHIFT_P0HI7Q_DESC_MODE) & BIT_MASK_P0HI7Q_DESC_MODE)
+#define BIT_SET_P0HI7Q_DESC_MODE(x, v)                                         \
+	(BIT_CLEAR_P0HI7Q_DESC_MODE(x) | BIT_P0HI7Q_DESC_MODE(v))
+
+#define BIT_CLR_P0HI6Q_HW_IDX BIT(28)
+#define BIT_CLR_P0HI5Q_HW_IDX BIT(27)
+#define BIT_CLR_P0HI4Q_HW_IDX BIT(26)
+#define BIT_CLR_P0HI3Q_HW_IDX BIT(25)
+#define BIT_CLR_P0HI2Q_HW_IDX BIT(24)
+#define BIT_CLR_P0HI1Q_HW_IDX BIT(23)
+#define BIT_CLR_P0HI0Q_HW_IDX BIT(22)
+#define BIT_CLR_ACH3_HW_IDX BIT(21)
+#define BIT_CLR_ACH2_HW_IDX BIT(20)
+#define BIT_CLR_ACH1_HW_IDX BIT(19)
+#define BIT_CLR_ACH0_HW_IDX BIT(18)
+#define BIT_CLR_P0MGQ_HW_IDX BIT(17)
+
+#define BIT_SHIFT_P0HI7Q_DESC_NUM 16
+#define BIT_MASK_P0HI7Q_DESC_NUM 0xfff
+#define BIT_P0HI7Q_DESC_NUM(x)                                                 \
+	(((x) & BIT_MASK_P0HI7Q_DESC_NUM) << BIT_SHIFT_P0HI7Q_DESC_NUM)
+#define BITS_P0HI7Q_DESC_NUM                                                   \
+	(BIT_MASK_P0HI7Q_DESC_NUM << BIT_SHIFT_P0HI7Q_DESC_NUM)
+#define BIT_CLEAR_P0HI7Q_DESC_NUM(x) ((x) & (~BITS_P0HI7Q_DESC_NUM))
+#define BIT_GET_P0HI7Q_DESC_NUM(x)                                             \
+	(((x) >> BIT_SHIFT_P0HI7Q_DESC_NUM) & BIT_MASK_P0HI7Q_DESC_NUM)
+#define BIT_SET_P0HI7Q_DESC_NUM(x, v)                                          \
+	(BIT_CLEAR_P0HI7Q_DESC_NUM(x) | BIT_P0HI7Q_DESC_NUM(v))
+
+#define BIT_CLR_P0RXQ_HW_IDX BIT(16)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_HI6Q_TXBD_NUM			(Offset 0x0398) */
+
+#define BIT_HI6Q_FLAG BIT(14)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_P0HI6Q_HI7Q_TXBD_NUM		(Offset 0x0398) */
+
+#define BIT_P0HI6Q_FLAG BIT(14)
+#define BIT_CLR_PFWCMDQ_HOST_IDX BIT(14)
+#define BIT_CLR_P0HI7Q_HOST_IDX BIT(13)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_HI6Q_TXBD_NUM			(Offset 0x0398) */
+
+#define BIT_SHIFT_HI6Q_DESC_MODE 12
+#define BIT_MASK_HI6Q_DESC_MODE 0x3
+#define BIT_HI6Q_DESC_MODE(x)                                                  \
+	(((x) & BIT_MASK_HI6Q_DESC_MODE) << BIT_SHIFT_HI6Q_DESC_MODE)
+#define BITS_HI6Q_DESC_MODE                                                    \
+	(BIT_MASK_HI6Q_DESC_MODE << BIT_SHIFT_HI6Q_DESC_MODE)
+#define BIT_CLEAR_HI6Q_DESC_MODE(x) ((x) & (~BITS_HI6Q_DESC_MODE))
+#define BIT_GET_HI6Q_DESC_MODE(x)                                              \
+	(((x) >> BIT_SHIFT_HI6Q_DESC_MODE) & BIT_MASK_HI6Q_DESC_MODE)
+#define BIT_SET_HI6Q_DESC_MODE(x, v)                                           \
+	(BIT_CLEAR_HI6Q_DESC_MODE(x) | BIT_HI6Q_DESC_MODE(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_P0HI6Q_HI7Q_TXBD_NUM		(Offset 0x0398) */
+
+#define BIT_SHIFT_P0HI6Q_DESC_MODE 12
+#define BIT_MASK_P0HI6Q_DESC_MODE 0x3
+#define BIT_P0HI6Q_DESC_MODE(x)                                                \
+	(((x) & BIT_MASK_P0HI6Q_DESC_MODE) << BIT_SHIFT_P0HI6Q_DESC_MODE)
+#define BITS_P0HI6Q_DESC_MODE                                                  \
+	(BIT_MASK_P0HI6Q_DESC_MODE << BIT_SHIFT_P0HI6Q_DESC_MODE)
+#define BIT_CLEAR_P0HI6Q_DESC_MODE(x) ((x) & (~BITS_P0HI6Q_DESC_MODE))
+#define BIT_GET_P0HI6Q_DESC_MODE(x)                                            \
+	(((x) >> BIT_SHIFT_P0HI6Q_DESC_MODE) & BIT_MASK_P0HI6Q_DESC_MODE)
+#define BIT_SET_P0HI6Q_DESC_MODE(x, v)                                         \
+	(BIT_CLEAR_P0HI6Q_DESC_MODE(x) | BIT_P0HI6Q_DESC_MODE(v))
+
+#define BIT_CLR_P0HI6Q_HOST_IDX BIT(12)
+#define BIT_CLR_P0HI5Q_HOST_IDX BIT(11)
+#define BIT_CLR_P0HI4Q_HOST_IDX BIT(10)
+#define BIT_CLR_P0HI3Q_HOST_IDX BIT(9)
+#define BIT_CLR_P0HI2Q_HOST_IDX BIT(8)
+#define BIT_CLR_P0HI1Q_HOST_IDX BIT(7)
+#define BIT_CLR_P0HI0Q_HOST_IDX BIT(6)
+#define BIT_CLR_ACH3_HOST_IDX BIT(5)
+#define BIT_CLR_ACH2_HOST_IDX BIT(4)
+#define BIT_CLR_ACH1_HOST_IDX BIT(3)
+#define BIT_CLR_ACH0_HOST_IDX BIT(2)
+#define BIT_CLR_P0MGQ_HOST_IDX BIT(1)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_HI6Q_TXBD_NUM			(Offset 0x0398) */
+
+#define BIT_SHIFT_HI6Q_DESC_NUM 0
+#define BIT_MASK_HI6Q_DESC_NUM 0xfff
+#define BIT_HI6Q_DESC_NUM(x)                                                   \
+	(((x) & BIT_MASK_HI6Q_DESC_NUM) << BIT_SHIFT_HI6Q_DESC_NUM)
+#define BITS_HI6Q_DESC_NUM (BIT_MASK_HI6Q_DESC_NUM << BIT_SHIFT_HI6Q_DESC_NUM)
+#define BIT_CLEAR_HI6Q_DESC_NUM(x) ((x) & (~BITS_HI6Q_DESC_NUM))
+#define BIT_GET_HI6Q_DESC_NUM(x)                                               \
+	(((x) >> BIT_SHIFT_HI6Q_DESC_NUM) & BIT_MASK_HI6Q_DESC_NUM)
+#define BIT_SET_HI6Q_DESC_NUM(x, v)                                            \
+	(BIT_CLEAR_HI6Q_DESC_NUM(x) | BIT_HI6Q_DESC_NUM(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_P0HI6Q_HI7Q_TXBD_NUM		(Offset 0x0398) */
+
+#define BIT_SHIFT_P0HI6Q_DESC_NUM 0
+#define BIT_MASK_P0HI6Q_DESC_NUM 0xfff
+#define BIT_P0HI6Q_DESC_NUM(x)                                                 \
+	(((x) & BIT_MASK_P0HI6Q_DESC_NUM) << BIT_SHIFT_P0HI6Q_DESC_NUM)
+#define BITS_P0HI6Q_DESC_NUM                                                   \
+	(BIT_MASK_P0HI6Q_DESC_NUM << BIT_SHIFT_P0HI6Q_DESC_NUM)
+#define BIT_CLEAR_P0HI6Q_DESC_NUM(x) ((x) & (~BITS_P0HI6Q_DESC_NUM))
+#define BIT_GET_P0HI6Q_DESC_NUM(x)                                             \
+	(((x) >> BIT_SHIFT_P0HI6Q_DESC_NUM) & BIT_MASK_P0HI6Q_DESC_NUM)
+#define BIT_SET_P0HI6Q_DESC_NUM(x, v)                                          \
+	(BIT_CLEAR_P0HI6Q_DESC_NUM(x) | BIT_P0HI6Q_DESC_NUM(v))
+
+#define BIT_CLR_P0RXQ_HOST_IDX BIT(0)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_HI7Q_TXBD_NUM			(Offset 0x039A) */
+
+#define BIT_HI7Q_FLAG BIT(14)
+
+#define BIT_SHIFT_HI7Q_DESC_MODE 12
+#define BIT_MASK_HI7Q_DESC_MODE 0x3
+#define BIT_HI7Q_DESC_MODE(x)                                                  \
+	(((x) & BIT_MASK_HI7Q_DESC_MODE) << BIT_SHIFT_HI7Q_DESC_MODE)
+#define BITS_HI7Q_DESC_MODE                                                    \
+	(BIT_MASK_HI7Q_DESC_MODE << BIT_SHIFT_HI7Q_DESC_MODE)
+#define BIT_CLEAR_HI7Q_DESC_MODE(x) ((x) & (~BITS_HI7Q_DESC_MODE))
+#define BIT_GET_HI7Q_DESC_MODE(x)                                              \
+	(((x) >> BIT_SHIFT_HI7Q_DESC_MODE) & BIT_MASK_HI7Q_DESC_MODE)
+#define BIT_SET_HI7Q_DESC_MODE(x, v)                                           \
+	(BIT_CLEAR_HI7Q_DESC_MODE(x) | BIT_HI7Q_DESC_MODE(v))
+
+#define BIT_SHIFT_HI7Q_DESC_NUM 0
+#define BIT_MASK_HI7Q_DESC_NUM 0xfff
+#define BIT_HI7Q_DESC_NUM(x)                                                   \
+	(((x) & BIT_MASK_HI7Q_DESC_NUM) << BIT_SHIFT_HI7Q_DESC_NUM)
+#define BITS_HI7Q_DESC_NUM (BIT_MASK_HI7Q_DESC_NUM << BIT_SHIFT_HI7Q_DESC_NUM)
+#define BIT_CLEAR_HI7Q_DESC_NUM(x) ((x) & (~BITS_HI7Q_DESC_NUM))
+#define BIT_GET_HI7Q_DESC_NUM(x)                                               \
+	(((x) >> BIT_SHIFT_HI7Q_DESC_NUM) & BIT_MASK_HI7Q_DESC_NUM)
+#define BIT_SET_HI7Q_DESC_NUM(x, v)                                            \
+	(BIT_CLEAR_HI7Q_DESC_NUM(x) | BIT_HI7Q_DESC_NUM(v))
+
+/* 2 REG_BD_RWPTR_CLR			(Offset 0x039C) */
+
+#define BIT_CLR_HI7Q_HW_IDX BIT(29)
+#define BIT_CLR_HI6Q_HW_IDX BIT(28)
+#define BIT_CLR_HI5Q_HW_IDX BIT(27)
+#define BIT_CLR_HI4Q_HW_IDX BIT(26)
+#define BIT_CLR_HI3Q_HW_IDX BIT(25)
+#define BIT_CLR_HI2Q_HW_IDX BIT(24)
+#define BIT_CLR_HI1Q_HW_IDX BIT(23)
+
+#endif
+
+#if (HALMAC_8881A_SUPPORT)
+
+/* 2 REG_BD_RWPTR_CLR			(Offset 0x039C) */
+
+#define BIT_BCN7DOK BIT(23)
+#define BIT_BCN7DOKM BIT(23)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_BD_RWPTR_CLR			(Offset 0x039C) */
+
+#define BIT_CLR_HI0Q_HW_IDX BIT(22)
+
+#endif
+
+#if (HALMAC_8881A_SUPPORT)
+
+/* 2 REG_BD_RWPTR_CLR			(Offset 0x039C) */
+
+#define BIT_BCN6DOK BIT(22)
+#define BIT_BCN6DOKM BIT(22)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_BD_RWPTR_CLR			(Offset 0x039C) */
+
+#define BIT_CLR_BKQ_HW_IDX BIT(21)
+
+#endif
+
+#if (HALMAC_8881A_SUPPORT)
+
+/* 2 REG_BD_RWPTR_CLR			(Offset 0x039C) */
+
+#define BIT_BCN5DOK BIT(21)
+#define BIT_BCN5DOKM BIT(21)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_BD_RWPTR_CLR			(Offset 0x039C) */
+
+#define BIT_CLR_BEQ_HW_IDX BIT(20)
+
+#endif
+
+#if (HALMAC_8881A_SUPPORT)
+
+/* 2 REG_BD_RWPTR_CLR			(Offset 0x039C) */
+
+#define BIT_BCN4DOK BIT(20)
+#define BIT_BCN4DOKM BIT(20)
+#define BIT_RX_OVER_RD_ERR BIT(20)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_BD_RWPTR_CLR			(Offset 0x039C) */
+
+#define BIT_CLR_VIQ_HW_IDX BIT(19)
+
+#endif
+
+#if (HALMAC_8881A_SUPPORT)
+
+/* 2 REG_BD_RWPTR_CLR			(Offset 0x039C) */
+
+#define BIT_BCN3DOK BIT(19)
+#define BIT_BCN3DOKM BIT(19)
+#define BIT_RXDMA_STUCK BIT(19)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_BD_RWPTR_CLR			(Offset 0x039C) */
+
+#define BIT_CLR_VOQ_HW_IDX BIT(18)
+
+#endif
+
+#if (HALMAC_8881A_SUPPORT)
+
+/* 2 REG_BD_RWPTR_CLR			(Offset 0x039C) */
+
+#define BIT_BCN2DOK BIT(18)
+#define BIT_BCN2DOKM BIT(18)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_BD_RWPTR_CLR			(Offset 0x039C) */
+
+#define BIT_CLR_MGQ_HW_IDX BIT(17)
+
+#endif
+
+#if (HALMAC_8881A_SUPPORT)
+
+/* 2 REG_BD_RWPTR_CLR			(Offset 0x039C) */
+
+#define BIT_BCN1DOK BIT(17)
+#define BIT_BCN1DOKM BIT(17)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_TSFTIMER_HCI			(Offset 0x039C) */
+
+#define BIT_SHIFT_TSFT2_HCI 16
+#define BIT_MASK_TSFT2_HCI 0xffff
+#define BIT_TSFT2_HCI(x) (((x) & BIT_MASK_TSFT2_HCI) << BIT_SHIFT_TSFT2_HCI)
+#define BITS_TSFT2_HCI (BIT_MASK_TSFT2_HCI << BIT_SHIFT_TSFT2_HCI)
+#define BIT_CLEAR_TSFT2_HCI(x) ((x) & (~BITS_TSFT2_HCI))
+#define BIT_GET_TSFT2_HCI(x) (((x) >> BIT_SHIFT_TSFT2_HCI) & BIT_MASK_TSFT2_HCI)
+#define BIT_SET_TSFT2_HCI(x, v) (BIT_CLEAR_TSFT2_HCI(x) | BIT_TSFT2_HCI(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_BD_RWPTR_CLR			(Offset 0x039C) */
+
+#define BIT_CLR_RXQ_HW_IDX BIT(16)
+
+#endif
+
+#if (HALMAC_8881A_SUPPORT)
+
+/* 2 REG_BD_RWPTR_CLR			(Offset 0x039C) */
+
+#define BIT_BCN0DOK BIT(16)
+#define BIT_BCN0DOKM BIT(16)
+
+#define BIT_SHIFT_RX_STATE 16
+#define BIT_MASK_RX_STATE 0x7
+#define BIT_RX_STATE(x) (((x) & BIT_MASK_RX_STATE) << BIT_SHIFT_RX_STATE)
+#define BITS_RX_STATE (BIT_MASK_RX_STATE << BIT_SHIFT_RX_STATE)
+#define BIT_CLEAR_RX_STATE(x) ((x) & (~BITS_RX_STATE))
+#define BIT_GET_RX_STATE(x) (((x) >> BIT_SHIFT_RX_STATE) & BIT_MASK_RX_STATE)
+#define BIT_SET_RX_STATE(x, v) (BIT_CLEAR_RX_STATE(x) | BIT_RX_STATE(v))
+
+#define BIT_SRST_TX BIT(15)
+#define BIT_M7DOK BIT(15)
+#define BIT_M7DOKM BIT(15)
+#define BIT_TDE_NO_IDLE BIT(15)
+#define BIT_SRST_RX BIT(14)
+#define BIT_M6DOK BIT(14)
+#define BIT_M6DOKM BIT(14)
+#define BIT_TXDMA_STUCK BIT(14)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_BD_RWPTR_CLR			(Offset 0x039C) */
+
+#define BIT_CLR_HI7Q_HOST_IDX BIT(13)
+
+#endif
+
+#if (HALMAC_8881A_SUPPORT)
+
+/* 2 REG_BD_RWPTR_CLR			(Offset 0x039C) */
+
+#define BIT_M5DOK BIT(13)
+#define BIT_M5DOKM BIT(13)
+#define BIT_TDE_FULL_ERR BIT(13)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_BD_RWPTR_CLR			(Offset 0x039C) */
+
+#define BIT_CLR_HI6Q_HOST_IDX BIT(12)
+
+#endif
+
+#if (HALMAC_8881A_SUPPORT)
+
+/* 2 REG_BD_RWPTR_CLR			(Offset 0x039C) */
+
+#define BIT_M4DOK BIT(12)
+#define BIT_M4DOKM BIT(12)
+#define BIT_HD_SIZE_ERR BIT(12)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_BD_RWPTR_CLR			(Offset 0x039C) */
+
+#define BIT_CLR_HI5Q_HOST_IDX BIT(11)
+
+#endif
+
+#if (HALMAC_8881A_SUPPORT)
+
+/* 2 REG_BD_RWPTR_CLR			(Offset 0x039C) */
+
+#define BIT_M3DOK BIT(11)
+#define BIT_M3DOKM BIT(11)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_BD_RWPTR_CLR			(Offset 0x039C) */
+
+#define BIT_CLR_HI4Q_HOST_IDX BIT(10)
+
+#endif
+
+#if (HALMAC_8881A_SUPPORT)
+
+/* 2 REG_BD_RWPTR_CLR			(Offset 0x039C) */
+
+#define BIT_M2DOK BIT(10)
+#define BIT_M2DOKM BIT(10)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_BD_RWPTR_CLR			(Offset 0x039C) */
+
+#define BIT_CLR_HI3Q_HOST_IDX BIT(9)
+
+#endif
+
+#if (HALMAC_8881A_SUPPORT)
+
+/* 2 REG_BD_RWPTR_CLR			(Offset 0x039C) */
+
+#define BIT_M1DOK BIT(9)
+#define BIT_M1DOKM BIT(9)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_BD_RWPTR_CLR			(Offset 0x039C) */
+
+#define BIT_CLR_HI2Q_HOST_IDX BIT(8)
+
+#endif
+
+#if (HALMAC_8881A_SUPPORT)
+
+/* 2 REG_BD_RWPTR_CLR			(Offset 0x039C) */
+
+#define BIT_M0DOK BIT(8)
+#define BIT_M0DOKM BIT(8)
+
+#define BIT_SHIFT_TX_STATE 8
+#define BIT_MASK_TX_STATE 0xf
+#define BIT_TX_STATE(x) (((x) & BIT_MASK_TX_STATE) << BIT_SHIFT_TX_STATE)
+#define BITS_TX_STATE (BIT_MASK_TX_STATE << BIT_SHIFT_TX_STATE)
+#define BIT_CLEAR_TX_STATE(x) ((x) & (~BITS_TX_STATE))
+#define BIT_GET_TX_STATE(x) (((x) >> BIT_SHIFT_TX_STATE) & BIT_MASK_TX_STATE)
+#define BIT_SET_TX_STATE(x, v) (BIT_CLEAR_TX_STATE(x) | BIT_TX_STATE(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_BD_RWPTR_CLR			(Offset 0x039C) */
+
+#define BIT_CLR_HI1Q_HOST_IDX BIT(7)
+#define BIT_CLR_HI0Q_HOST_IDX BIT(6)
+
+#endif
+
+#if (HALMAC_8881A_SUPPORT)
+
+/* 2 REG_BD_RWPTR_CLR			(Offset 0x039C) */
+
+#define BIT_MGQDOK BIT(6)
+#define BIT_MGQDOKM BIT(6)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_BD_RWPTR_CLR			(Offset 0x039C) */
+
+#define BIT_CLR_BKQ_HOST_IDX BIT(5)
+
+#endif
+
+#if (HALMAC_8881A_SUPPORT)
+
+/* 2 REG_BD_RWPTR_CLR			(Offset 0x039C) */
+
+#define BIT_BKQDOK BIT(5)
+#define BIT_BKQDOKM BIT(5)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_BD_RWPTR_CLR			(Offset 0x039C) */
+
+#define BIT_CLR_BEQ_HOST_IDX BIT(4)
+
+#endif
+
+#if (HALMAC_8881A_SUPPORT)
+
+/* 2 REG_BD_RWPTR_CLR			(Offset 0x039C) */
+
+#define BIT_SHIFT_HPS_CLKR 4
+#define BIT_MASK_HPS_CLKR 0x3
+#define BIT_HPS_CLKR(x) (((x) & BIT_MASK_HPS_CLKR) << BIT_SHIFT_HPS_CLKR)
+#define BITS_HPS_CLKR (BIT_MASK_HPS_CLKR << BIT_SHIFT_HPS_CLKR)
+#define BIT_CLEAR_HPS_CLKR(x) ((x) & (~BITS_HPS_CLKR))
+#define BIT_GET_HPS_CLKR(x) (((x) >> BIT_SHIFT_HPS_CLKR) & BIT_MASK_HPS_CLKR)
+#define BIT_SET_HPS_CLKR(x, v) (BIT_CLEAR_HPS_CLKR(x) | BIT_HPS_CLKR(v))
+
+#define BIT_BEQDOK BIT(4)
+#define BIT_BEQDOKM BIT(4)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_BD_RWPTR_CLR			(Offset 0x039C) */
+
+#define BIT_CLR_VIQ_HOST_IDX BIT(3)
+
+#endif
+
+#if (HALMAC_8881A_SUPPORT)
+
+/* 2 REG_BD_RWPTR_CLR			(Offset 0x039C) */
+
+#define BIT_LX_INT BIT(3)
+#define BIT_VIQDOK BIT(3)
+#define BIT_VIQDOKM BIT(3)
+#define BIT_MST_BUSY BIT(3)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_BD_RWPTR_CLR			(Offset 0x039C) */
+
+#define BIT_CLR_VOQ_HOST_IDX BIT(2)
+
+#endif
+
+#if (HALMAC_8881A_SUPPORT)
+
+/* 2 REG_BD_RWPTR_CLR			(Offset 0x039C) */
+
+#define BIT_VOQDOK BIT(2)
+#define BIT_VOQDOKM BIT(2)
+#define BIT_SLV_BUSY BIT(2)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_BD_RWPTR_CLR			(Offset 0x039C) */
+
+#define BIT_CLR_MGQ_HOST_IDX BIT(1)
+
+#endif
+
+#if (HALMAC_8881A_SUPPORT)
+
+/* 2 REG_BD_RWPTR_CLR			(Offset 0x039C) */
+
+#define BIT_RDUM BIT(1)
+#define BIT_RXDES_UNAVAIL BIT(1)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_TSFTIMER_HCI			(Offset 0x039C) */
+
+#define BIT_SHIFT_TSFT1_HCI 0
+#define BIT_MASK_TSFT1_HCI 0xffff
+#define BIT_TSFT1_HCI(x) (((x) & BIT_MASK_TSFT1_HCI) << BIT_SHIFT_TSFT1_HCI)
+#define BITS_TSFT1_HCI (BIT_MASK_TSFT1_HCI << BIT_SHIFT_TSFT1_HCI)
+#define BIT_CLEAR_TSFT1_HCI(x) ((x) & (~BITS_TSFT1_HCI))
+#define BIT_GET_TSFT1_HCI(x) (((x) >> BIT_SHIFT_TSFT1_HCI) & BIT_MASK_TSFT1_HCI)
+#define BIT_SET_TSFT1_HCI(x, v) (BIT_CLEAR_TSFT1_HCI(x) | BIT_TSFT1_HCI(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_BD_RWPTR_CLR			(Offset 0x039C) */
+
+#define BIT_CLR_RXQ_HOST_IDX BIT(0)
+
+#endif
+
+#if (HALMAC_8881A_SUPPORT)
+
+/* 2 REG_BD_RWPTR_CLR			(Offset 0x039C) */
+
+#define BIT_RXDOK BIT(0)
+#define BIT_RXDOKM BIT(0)
+#define BIT_EN_DBG_STUCK BIT(0)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_VOQ_TXBD_IDX			(Offset 0x03A0) */
+
+#define BIT_SHIFT_VOQ_HW_IDX 16
+#define BIT_MASK_VOQ_HW_IDX 0xfff
+#define BIT_VOQ_HW_IDX(x) (((x) & BIT_MASK_VOQ_HW_IDX) << BIT_SHIFT_VOQ_HW_IDX)
+#define BITS_VOQ_HW_IDX (BIT_MASK_VOQ_HW_IDX << BIT_SHIFT_VOQ_HW_IDX)
+#define BIT_CLEAR_VOQ_HW_IDX(x) ((x) & (~BITS_VOQ_HW_IDX))
+#define BIT_GET_VOQ_HW_IDX(x)                                                  \
+	(((x) >> BIT_SHIFT_VOQ_HW_IDX) & BIT_MASK_VOQ_HW_IDX)
+#define BIT_SET_VOQ_HW_IDX(x, v) (BIT_CLEAR_VOQ_HW_IDX(x) | BIT_VOQ_HW_IDX(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_ACH0_TXBD_IDX			(Offset 0x03A0) */
+
+#define BIT_SHIFT_ACH0_HW_IDX 16
+#define BIT_MASK_ACH0_HW_IDX 0xfff
+#define BIT_ACH0_HW_IDX(x)                                                     \
+	(((x) & BIT_MASK_ACH0_HW_IDX) << BIT_SHIFT_ACH0_HW_IDX)
+#define BITS_ACH0_HW_IDX (BIT_MASK_ACH0_HW_IDX << BIT_SHIFT_ACH0_HW_IDX)
+#define BIT_CLEAR_ACH0_HW_IDX(x) ((x) & (~BITS_ACH0_HW_IDX))
+#define BIT_GET_ACH0_HW_IDX(x)                                                 \
+	(((x) >> BIT_SHIFT_ACH0_HW_IDX) & BIT_MASK_ACH0_HW_IDX)
+#define BIT_SET_ACH0_HW_IDX(x, v)                                              \
+	(BIT_CLEAR_ACH0_HW_IDX(x) | BIT_ACH0_HW_IDX(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_VOQ_TXBD_IDX			(Offset 0x03A0) */
+
+#define BIT_SHIFT_VOQ_HOST_IDX 0
+#define BIT_MASK_VOQ_HOST_IDX 0xfff
+#define BIT_VOQ_HOST_IDX(x)                                                    \
+	(((x) & BIT_MASK_VOQ_HOST_IDX) << BIT_SHIFT_VOQ_HOST_IDX)
+#define BITS_VOQ_HOST_IDX (BIT_MASK_VOQ_HOST_IDX << BIT_SHIFT_VOQ_HOST_IDX)
+#define BIT_CLEAR_VOQ_HOST_IDX(x) ((x) & (~BITS_VOQ_HOST_IDX))
+#define BIT_GET_VOQ_HOST_IDX(x)                                                \
+	(((x) >> BIT_SHIFT_VOQ_HOST_IDX) & BIT_MASK_VOQ_HOST_IDX)
+#define BIT_SET_VOQ_HOST_IDX(x, v)                                             \
+	(BIT_CLEAR_VOQ_HOST_IDX(x) | BIT_VOQ_HOST_IDX(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_ACH0_TXBD_IDX			(Offset 0x03A0) */
+
+#define BIT_SHIFT_ACH0_HOST_IDX 0
+#define BIT_MASK_ACH0_HOST_IDX 0xfff
+#define BIT_ACH0_HOST_IDX(x)                                                   \
+	(((x) & BIT_MASK_ACH0_HOST_IDX) << BIT_SHIFT_ACH0_HOST_IDX)
+#define BITS_ACH0_HOST_IDX (BIT_MASK_ACH0_HOST_IDX << BIT_SHIFT_ACH0_HOST_IDX)
+#define BIT_CLEAR_ACH0_HOST_IDX(x) ((x) & (~BITS_ACH0_HOST_IDX))
+#define BIT_GET_ACH0_HOST_IDX(x)                                               \
+	(((x) >> BIT_SHIFT_ACH0_HOST_IDX) & BIT_MASK_ACH0_HOST_IDX)
+#define BIT_SET_ACH0_HOST_IDX(x, v)                                            \
+	(BIT_CLEAR_ACH0_HOST_IDX(x) | BIT_ACH0_HOST_IDX(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_VIQ_TXBD_IDX			(Offset 0x03A4) */
+
+#define BIT_SHIFT_VIQ_HW_IDX 16
+#define BIT_MASK_VIQ_HW_IDX 0xfff
+#define BIT_VIQ_HW_IDX(x) (((x) & BIT_MASK_VIQ_HW_IDX) << BIT_SHIFT_VIQ_HW_IDX)
+#define BITS_VIQ_HW_IDX (BIT_MASK_VIQ_HW_IDX << BIT_SHIFT_VIQ_HW_IDX)
+#define BIT_CLEAR_VIQ_HW_IDX(x) ((x) & (~BITS_VIQ_HW_IDX))
+#define BIT_GET_VIQ_HW_IDX(x)                                                  \
+	(((x) >> BIT_SHIFT_VIQ_HW_IDX) & BIT_MASK_VIQ_HW_IDX)
+#define BIT_SET_VIQ_HW_IDX(x, v) (BIT_CLEAR_VIQ_HW_IDX(x) | BIT_VIQ_HW_IDX(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_ACH1_TXBD_IDX			(Offset 0x03A4) */
+
+#define BIT_SHIFT_ACH1_HW_IDX 16
+#define BIT_MASK_ACH1_HW_IDX 0xfff
+#define BIT_ACH1_HW_IDX(x)                                                     \
+	(((x) & BIT_MASK_ACH1_HW_IDX) << BIT_SHIFT_ACH1_HW_IDX)
+#define BITS_ACH1_HW_IDX (BIT_MASK_ACH1_HW_IDX << BIT_SHIFT_ACH1_HW_IDX)
+#define BIT_CLEAR_ACH1_HW_IDX(x) ((x) & (~BITS_ACH1_HW_IDX))
+#define BIT_GET_ACH1_HW_IDX(x)                                                 \
+	(((x) >> BIT_SHIFT_ACH1_HW_IDX) & BIT_MASK_ACH1_HW_IDX)
+#define BIT_SET_ACH1_HW_IDX(x, v)                                              \
+	(BIT_CLEAR_ACH1_HW_IDX(x) | BIT_ACH1_HW_IDX(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_VIQ_TXBD_IDX			(Offset 0x03A4) */
+
+#define BIT_SHIFT_VIQ_HOST_IDX 0
+#define BIT_MASK_VIQ_HOST_IDX 0xfff
+#define BIT_VIQ_HOST_IDX(x)                                                    \
+	(((x) & BIT_MASK_VIQ_HOST_IDX) << BIT_SHIFT_VIQ_HOST_IDX)
+#define BITS_VIQ_HOST_IDX (BIT_MASK_VIQ_HOST_IDX << BIT_SHIFT_VIQ_HOST_IDX)
+#define BIT_CLEAR_VIQ_HOST_IDX(x) ((x) & (~BITS_VIQ_HOST_IDX))
+#define BIT_GET_VIQ_HOST_IDX(x)                                                \
+	(((x) >> BIT_SHIFT_VIQ_HOST_IDX) & BIT_MASK_VIQ_HOST_IDX)
+#define BIT_SET_VIQ_HOST_IDX(x, v)                                             \
+	(BIT_CLEAR_VIQ_HOST_IDX(x) | BIT_VIQ_HOST_IDX(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_ACH1_TXBD_IDX			(Offset 0x03A4) */
+
+#define BIT_SHIFT_ACH1_HOST_IDX 0
+#define BIT_MASK_ACH1_HOST_IDX 0xfff
+#define BIT_ACH1_HOST_IDX(x)                                                   \
+	(((x) & BIT_MASK_ACH1_HOST_IDX) << BIT_SHIFT_ACH1_HOST_IDX)
+#define BITS_ACH1_HOST_IDX (BIT_MASK_ACH1_HOST_IDX << BIT_SHIFT_ACH1_HOST_IDX)
+#define BIT_CLEAR_ACH1_HOST_IDX(x) ((x) & (~BITS_ACH1_HOST_IDX))
+#define BIT_GET_ACH1_HOST_IDX(x)                                               \
+	(((x) >> BIT_SHIFT_ACH1_HOST_IDX) & BIT_MASK_ACH1_HOST_IDX)
+#define BIT_SET_ACH1_HOST_IDX(x, v)                                            \
+	(BIT_CLEAR_ACH1_HOST_IDX(x) | BIT_ACH1_HOST_IDX(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_BEQ_TXBD_IDX			(Offset 0x03A8) */
+
+#define BIT_SHIFT_BEQ_HW_IDX 16
+#define BIT_MASK_BEQ_HW_IDX 0xfff
+#define BIT_BEQ_HW_IDX(x) (((x) & BIT_MASK_BEQ_HW_IDX) << BIT_SHIFT_BEQ_HW_IDX)
+#define BITS_BEQ_HW_IDX (BIT_MASK_BEQ_HW_IDX << BIT_SHIFT_BEQ_HW_IDX)
+#define BIT_CLEAR_BEQ_HW_IDX(x) ((x) & (~BITS_BEQ_HW_IDX))
+#define BIT_GET_BEQ_HW_IDX(x)                                                  \
+	(((x) >> BIT_SHIFT_BEQ_HW_IDX) & BIT_MASK_BEQ_HW_IDX)
+#define BIT_SET_BEQ_HW_IDX(x, v) (BIT_CLEAR_BEQ_HW_IDX(x) | BIT_BEQ_HW_IDX(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_ACH2_TXBD_IDX			(Offset 0x03A8) */
+
+#define BIT_SHIFT_ACH2_HW_IDX 16
+#define BIT_MASK_ACH2_HW_IDX 0xfff
+#define BIT_ACH2_HW_IDX(x)                                                     \
+	(((x) & BIT_MASK_ACH2_HW_IDX) << BIT_SHIFT_ACH2_HW_IDX)
+#define BITS_ACH2_HW_IDX (BIT_MASK_ACH2_HW_IDX << BIT_SHIFT_ACH2_HW_IDX)
+#define BIT_CLEAR_ACH2_HW_IDX(x) ((x) & (~BITS_ACH2_HW_IDX))
+#define BIT_GET_ACH2_HW_IDX(x)                                                 \
+	(((x) >> BIT_SHIFT_ACH2_HW_IDX) & BIT_MASK_ACH2_HW_IDX)
+#define BIT_SET_ACH2_HW_IDX(x, v)                                              \
+	(BIT_CLEAR_ACH2_HW_IDX(x) | BIT_ACH2_HW_IDX(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_BEQ_TXBD_IDX			(Offset 0x03A8) */
+
+#define BIT_SHIFT_BEQ_HOST_IDX 0
+#define BIT_MASK_BEQ_HOST_IDX 0xfff
+#define BIT_BEQ_HOST_IDX(x)                                                    \
+	(((x) & BIT_MASK_BEQ_HOST_IDX) << BIT_SHIFT_BEQ_HOST_IDX)
+#define BITS_BEQ_HOST_IDX (BIT_MASK_BEQ_HOST_IDX << BIT_SHIFT_BEQ_HOST_IDX)
+#define BIT_CLEAR_BEQ_HOST_IDX(x) ((x) & (~BITS_BEQ_HOST_IDX))
+#define BIT_GET_BEQ_HOST_IDX(x)                                                \
+	(((x) >> BIT_SHIFT_BEQ_HOST_IDX) & BIT_MASK_BEQ_HOST_IDX)
+#define BIT_SET_BEQ_HOST_IDX(x, v)                                             \
+	(BIT_CLEAR_BEQ_HOST_IDX(x) | BIT_BEQ_HOST_IDX(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_ACH2_TXBD_IDX			(Offset 0x03A8) */
+
+#define BIT_SHIFT_ACH2_HOST_IDX 0
+#define BIT_MASK_ACH2_HOST_IDX 0xfff
+#define BIT_ACH2_HOST_IDX(x)                                                   \
+	(((x) & BIT_MASK_ACH2_HOST_IDX) << BIT_SHIFT_ACH2_HOST_IDX)
+#define BITS_ACH2_HOST_IDX (BIT_MASK_ACH2_HOST_IDX << BIT_SHIFT_ACH2_HOST_IDX)
+#define BIT_CLEAR_ACH2_HOST_IDX(x) ((x) & (~BITS_ACH2_HOST_IDX))
+#define BIT_GET_ACH2_HOST_IDX(x)                                               \
+	(((x) >> BIT_SHIFT_ACH2_HOST_IDX) & BIT_MASK_ACH2_HOST_IDX)
+#define BIT_SET_ACH2_HOST_IDX(x, v)                                            \
+	(BIT_CLEAR_ACH2_HOST_IDX(x) | BIT_ACH2_HOST_IDX(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_BKQ_TXBD_IDX			(Offset 0x03AC) */
+
+#define BIT_SHIFT_BKQ_HW_IDX 16
+#define BIT_MASK_BKQ_HW_IDX 0xfff
+#define BIT_BKQ_HW_IDX(x) (((x) & BIT_MASK_BKQ_HW_IDX) << BIT_SHIFT_BKQ_HW_IDX)
+#define BITS_BKQ_HW_IDX (BIT_MASK_BKQ_HW_IDX << BIT_SHIFT_BKQ_HW_IDX)
+#define BIT_CLEAR_BKQ_HW_IDX(x) ((x) & (~BITS_BKQ_HW_IDX))
+#define BIT_GET_BKQ_HW_IDX(x)                                                  \
+	(((x) >> BIT_SHIFT_BKQ_HW_IDX) & BIT_MASK_BKQ_HW_IDX)
+#define BIT_SET_BKQ_HW_IDX(x, v) (BIT_CLEAR_BKQ_HW_IDX(x) | BIT_BKQ_HW_IDX(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_ACH3_TXBD_IDX			(Offset 0x03AC) */
+
+#define BIT_SHIFT_ACH3_HW_IDX 16
+#define BIT_MASK_ACH3_HW_IDX 0xfff
+#define BIT_ACH3_HW_IDX(x)                                                     \
+	(((x) & BIT_MASK_ACH3_HW_IDX) << BIT_SHIFT_ACH3_HW_IDX)
+#define BITS_ACH3_HW_IDX (BIT_MASK_ACH3_HW_IDX << BIT_SHIFT_ACH3_HW_IDX)
+#define BIT_CLEAR_ACH3_HW_IDX(x) ((x) & (~BITS_ACH3_HW_IDX))
+#define BIT_GET_ACH3_HW_IDX(x)                                                 \
+	(((x) >> BIT_SHIFT_ACH3_HW_IDX) & BIT_MASK_ACH3_HW_IDX)
+#define BIT_SET_ACH3_HW_IDX(x, v)                                              \
+	(BIT_CLEAR_ACH3_HW_IDX(x) | BIT_ACH3_HW_IDX(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_BKQ_TXBD_IDX			(Offset 0x03AC) */
+
+#define BIT_SHIFT_BKQ_HOST_IDX 0
+#define BIT_MASK_BKQ_HOST_IDX 0xfff
+#define BIT_BKQ_HOST_IDX(x)                                                    \
+	(((x) & BIT_MASK_BKQ_HOST_IDX) << BIT_SHIFT_BKQ_HOST_IDX)
+#define BITS_BKQ_HOST_IDX (BIT_MASK_BKQ_HOST_IDX << BIT_SHIFT_BKQ_HOST_IDX)
+#define BIT_CLEAR_BKQ_HOST_IDX(x) ((x) & (~BITS_BKQ_HOST_IDX))
+#define BIT_GET_BKQ_HOST_IDX(x)                                                \
+	(((x) >> BIT_SHIFT_BKQ_HOST_IDX) & BIT_MASK_BKQ_HOST_IDX)
+#define BIT_SET_BKQ_HOST_IDX(x, v)                                             \
+	(BIT_CLEAR_BKQ_HOST_IDX(x) | BIT_BKQ_HOST_IDX(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_ACH3_TXBD_IDX			(Offset 0x03AC) */
+
+#define BIT_SHIFT_ACH3_HOST_IDX 0
+#define BIT_MASK_ACH3_HOST_IDX 0xfff
+#define BIT_ACH3_HOST_IDX(x)                                                   \
+	(((x) & BIT_MASK_ACH3_HOST_IDX) << BIT_SHIFT_ACH3_HOST_IDX)
+#define BITS_ACH3_HOST_IDX (BIT_MASK_ACH3_HOST_IDX << BIT_SHIFT_ACH3_HOST_IDX)
+#define BIT_CLEAR_ACH3_HOST_IDX(x) ((x) & (~BITS_ACH3_HOST_IDX))
+#define BIT_GET_ACH3_HOST_IDX(x)                                               \
+	(((x) >> BIT_SHIFT_ACH3_HOST_IDX) & BIT_MASK_ACH3_HOST_IDX)
+#define BIT_SET_ACH3_HOST_IDX(x, v)                                            \
+	(BIT_CLEAR_ACH3_HOST_IDX(x) | BIT_ACH3_HOST_IDX(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_MGQ_TXBD_IDX			(Offset 0x03B0) */
+
+#define BIT_SHIFT_MGQ_HW_IDX 16
+#define BIT_MASK_MGQ_HW_IDX 0xfff
+#define BIT_MGQ_HW_IDX(x) (((x) & BIT_MASK_MGQ_HW_IDX) << BIT_SHIFT_MGQ_HW_IDX)
+#define BITS_MGQ_HW_IDX (BIT_MASK_MGQ_HW_IDX << BIT_SHIFT_MGQ_HW_IDX)
+#define BIT_CLEAR_MGQ_HW_IDX(x) ((x) & (~BITS_MGQ_HW_IDX))
+#define BIT_GET_MGQ_HW_IDX(x)                                                  \
+	(((x) >> BIT_SHIFT_MGQ_HW_IDX) & BIT_MASK_MGQ_HW_IDX)
+#define BIT_SET_MGQ_HW_IDX(x, v) (BIT_CLEAR_MGQ_HW_IDX(x) | BIT_MGQ_HW_IDX(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_P0MGQ_TXBD_IDX			(Offset 0x03B0) */
+
+#define BIT_SHIFT_P0MGQ_HW_IDX 16
+#define BIT_MASK_P0MGQ_HW_IDX 0xfff
+#define BIT_P0MGQ_HW_IDX(x)                                                    \
+	(((x) & BIT_MASK_P0MGQ_HW_IDX) << BIT_SHIFT_P0MGQ_HW_IDX)
+#define BITS_P0MGQ_HW_IDX (BIT_MASK_P0MGQ_HW_IDX << BIT_SHIFT_P0MGQ_HW_IDX)
+#define BIT_CLEAR_P0MGQ_HW_IDX(x) ((x) & (~BITS_P0MGQ_HW_IDX))
+#define BIT_GET_P0MGQ_HW_IDX(x)                                                \
+	(((x) >> BIT_SHIFT_P0MGQ_HW_IDX) & BIT_MASK_P0MGQ_HW_IDX)
+#define BIT_SET_P0MGQ_HW_IDX(x, v)                                             \
+	(BIT_CLEAR_P0MGQ_HW_IDX(x) | BIT_P0MGQ_HW_IDX(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_MGQ_TXBD_IDX			(Offset 0x03B0) */
+
+#define BIT_SHIFT_MGQ_HOST_IDX 0
+#define BIT_MASK_MGQ_HOST_IDX 0xfff
+#define BIT_MGQ_HOST_IDX(x)                                                    \
+	(((x) & BIT_MASK_MGQ_HOST_IDX) << BIT_SHIFT_MGQ_HOST_IDX)
+#define BITS_MGQ_HOST_IDX (BIT_MASK_MGQ_HOST_IDX << BIT_SHIFT_MGQ_HOST_IDX)
+#define BIT_CLEAR_MGQ_HOST_IDX(x) ((x) & (~BITS_MGQ_HOST_IDX))
+#define BIT_GET_MGQ_HOST_IDX(x)                                                \
+	(((x) >> BIT_SHIFT_MGQ_HOST_IDX) & BIT_MASK_MGQ_HOST_IDX)
+#define BIT_SET_MGQ_HOST_IDX(x, v)                                             \
+	(BIT_CLEAR_MGQ_HOST_IDX(x) | BIT_MGQ_HOST_IDX(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_P0MGQ_TXBD_IDX			(Offset 0x03B0) */
+
+#define BIT_SHIFT_P0MGQ_HOST_IDX 0
+#define BIT_MASK_P0MGQ_HOST_IDX 0xfff
+#define BIT_P0MGQ_HOST_IDX(x)                                                  \
+	(((x) & BIT_MASK_P0MGQ_HOST_IDX) << BIT_SHIFT_P0MGQ_HOST_IDX)
+#define BITS_P0MGQ_HOST_IDX                                                    \
+	(BIT_MASK_P0MGQ_HOST_IDX << BIT_SHIFT_P0MGQ_HOST_IDX)
+#define BIT_CLEAR_P0MGQ_HOST_IDX(x) ((x) & (~BITS_P0MGQ_HOST_IDX))
+#define BIT_GET_P0MGQ_HOST_IDX(x)                                              \
+	(((x) >> BIT_SHIFT_P0MGQ_HOST_IDX) & BIT_MASK_P0MGQ_HOST_IDX)
+#define BIT_SET_P0MGQ_HOST_IDX(x, v)                                           \
+	(BIT_CLEAR_P0MGQ_HOST_IDX(x) | BIT_P0MGQ_HOST_IDX(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_RXQ_RXBD_IDX			(Offset 0x03B4) */
+
+#define BIT_SHIFT_RXQ_HW_IDX 16
+#define BIT_MASK_RXQ_HW_IDX 0xfff
+#define BIT_RXQ_HW_IDX(x) (((x) & BIT_MASK_RXQ_HW_IDX) << BIT_SHIFT_RXQ_HW_IDX)
+#define BITS_RXQ_HW_IDX (BIT_MASK_RXQ_HW_IDX << BIT_SHIFT_RXQ_HW_IDX)
+#define BIT_CLEAR_RXQ_HW_IDX(x) ((x) & (~BITS_RXQ_HW_IDX))
+#define BIT_GET_RXQ_HW_IDX(x)                                                  \
+	(((x) >> BIT_SHIFT_RXQ_HW_IDX) & BIT_MASK_RXQ_HW_IDX)
+#define BIT_SET_RXQ_HW_IDX(x, v) (BIT_CLEAR_RXQ_HW_IDX(x) | BIT_RXQ_HW_IDX(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_P0RXQ_RXBD_IDX			(Offset 0x03B4) */
+
+#define BIT_SHIFT_P0RXQ_HW_IDX 16
+#define BIT_MASK_P0RXQ_HW_IDX 0xfff
+#define BIT_P0RXQ_HW_IDX(x)                                                    \
+	(((x) & BIT_MASK_P0RXQ_HW_IDX) << BIT_SHIFT_P0RXQ_HW_IDX)
+#define BITS_P0RXQ_HW_IDX (BIT_MASK_P0RXQ_HW_IDX << BIT_SHIFT_P0RXQ_HW_IDX)
+#define BIT_CLEAR_P0RXQ_HW_IDX(x) ((x) & (~BITS_P0RXQ_HW_IDX))
+#define BIT_GET_P0RXQ_HW_IDX(x)                                                \
+	(((x) >> BIT_SHIFT_P0RXQ_HW_IDX) & BIT_MASK_P0RXQ_HW_IDX)
+#define BIT_SET_P0RXQ_HW_IDX(x, v)                                             \
+	(BIT_CLEAR_P0RXQ_HW_IDX(x) | BIT_P0RXQ_HW_IDX(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_RXQ_RXBD_IDX			(Offset 0x03B4) */
+
+#define BIT_SHIFT_RXQ_HOST_IDX 0
+#define BIT_MASK_RXQ_HOST_IDX 0xfff
+#define BIT_RXQ_HOST_IDX(x)                                                    \
+	(((x) & BIT_MASK_RXQ_HOST_IDX) << BIT_SHIFT_RXQ_HOST_IDX)
+#define BITS_RXQ_HOST_IDX (BIT_MASK_RXQ_HOST_IDX << BIT_SHIFT_RXQ_HOST_IDX)
+#define BIT_CLEAR_RXQ_HOST_IDX(x) ((x) & (~BITS_RXQ_HOST_IDX))
+#define BIT_GET_RXQ_HOST_IDX(x)                                                \
+	(((x) >> BIT_SHIFT_RXQ_HOST_IDX) & BIT_MASK_RXQ_HOST_IDX)
+#define BIT_SET_RXQ_HOST_IDX(x, v)                                             \
+	(BIT_CLEAR_RXQ_HOST_IDX(x) | BIT_RXQ_HOST_IDX(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_P0RXQ_RXBD_IDX			(Offset 0x03B4) */
+
+#define BIT_SHIFT_P0RXQ_HOST_IDX 0
+#define BIT_MASK_P0RXQ_HOST_IDX 0xfff
+#define BIT_P0RXQ_HOST_IDX(x)                                                  \
+	(((x) & BIT_MASK_P0RXQ_HOST_IDX) << BIT_SHIFT_P0RXQ_HOST_IDX)
+#define BITS_P0RXQ_HOST_IDX                                                    \
+	(BIT_MASK_P0RXQ_HOST_IDX << BIT_SHIFT_P0RXQ_HOST_IDX)
+#define BIT_CLEAR_P0RXQ_HOST_IDX(x) ((x) & (~BITS_P0RXQ_HOST_IDX))
+#define BIT_GET_P0RXQ_HOST_IDX(x)                                              \
+	(((x) >> BIT_SHIFT_P0RXQ_HOST_IDX) & BIT_MASK_P0RXQ_HOST_IDX)
+#define BIT_SET_P0RXQ_HOST_IDX(x, v)                                           \
+	(BIT_CLEAR_P0RXQ_HOST_IDX(x) | BIT_P0RXQ_HOST_IDX(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_HI0Q_TXBD_IDX			(Offset 0x03B8) */
+
+#define BIT_SHIFT_HI0Q_HW_IDX 16
+#define BIT_MASK_HI0Q_HW_IDX 0xfff
+#define BIT_HI0Q_HW_IDX(x)                                                     \
+	(((x) & BIT_MASK_HI0Q_HW_IDX) << BIT_SHIFT_HI0Q_HW_IDX)
+#define BITS_HI0Q_HW_IDX (BIT_MASK_HI0Q_HW_IDX << BIT_SHIFT_HI0Q_HW_IDX)
+#define BIT_CLEAR_HI0Q_HW_IDX(x) ((x) & (~BITS_HI0Q_HW_IDX))
+#define BIT_GET_HI0Q_HW_IDX(x)                                                 \
+	(((x) >> BIT_SHIFT_HI0Q_HW_IDX) & BIT_MASK_HI0Q_HW_IDX)
+#define BIT_SET_HI0Q_HW_IDX(x, v)                                              \
+	(BIT_CLEAR_HI0Q_HW_IDX(x) | BIT_HI0Q_HW_IDX(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_P0HI0Q_TXBD_IDX			(Offset 0x03B8) */
+
+#define BIT_SHIFT_P0HI0Q_HW_IDX 16
+#define BIT_MASK_P0HI0Q_HW_IDX 0xfff
+#define BIT_P0HI0Q_HW_IDX(x)                                                   \
+	(((x) & BIT_MASK_P0HI0Q_HW_IDX) << BIT_SHIFT_P0HI0Q_HW_IDX)
+#define BITS_P0HI0Q_HW_IDX (BIT_MASK_P0HI0Q_HW_IDX << BIT_SHIFT_P0HI0Q_HW_IDX)
+#define BIT_CLEAR_P0HI0Q_HW_IDX(x) ((x) & (~BITS_P0HI0Q_HW_IDX))
+#define BIT_GET_P0HI0Q_HW_IDX(x)                                               \
+	(((x) >> BIT_SHIFT_P0HI0Q_HW_IDX) & BIT_MASK_P0HI0Q_HW_IDX)
+#define BIT_SET_P0HI0Q_HW_IDX(x, v)                                            \
+	(BIT_CLEAR_P0HI0Q_HW_IDX(x) | BIT_P0HI0Q_HW_IDX(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_HI0Q_TXBD_IDX			(Offset 0x03B8) */
+
+#define BIT_SHIFT_HI0Q_HOST_IDX 0
+#define BIT_MASK_HI0Q_HOST_IDX 0xfff
+#define BIT_HI0Q_HOST_IDX(x)                                                   \
+	(((x) & BIT_MASK_HI0Q_HOST_IDX) << BIT_SHIFT_HI0Q_HOST_IDX)
+#define BITS_HI0Q_HOST_IDX (BIT_MASK_HI0Q_HOST_IDX << BIT_SHIFT_HI0Q_HOST_IDX)
+#define BIT_CLEAR_HI0Q_HOST_IDX(x) ((x) & (~BITS_HI0Q_HOST_IDX))
+#define BIT_GET_HI0Q_HOST_IDX(x)                                               \
+	(((x) >> BIT_SHIFT_HI0Q_HOST_IDX) & BIT_MASK_HI0Q_HOST_IDX)
+#define BIT_SET_HI0Q_HOST_IDX(x, v)                                            \
+	(BIT_CLEAR_HI0Q_HOST_IDX(x) | BIT_HI0Q_HOST_IDX(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_P0HI0Q_TXBD_IDX			(Offset 0x03B8) */
+
+#define BIT_SHIFT_P0HI0Q_HOST_IDX 0
+#define BIT_MASK_P0HI0Q_HOST_IDX 0xfff
+#define BIT_P0HI0Q_HOST_IDX(x)                                                 \
+	(((x) & BIT_MASK_P0HI0Q_HOST_IDX) << BIT_SHIFT_P0HI0Q_HOST_IDX)
+#define BITS_P0HI0Q_HOST_IDX                                                   \
+	(BIT_MASK_P0HI0Q_HOST_IDX << BIT_SHIFT_P0HI0Q_HOST_IDX)
+#define BIT_CLEAR_P0HI0Q_HOST_IDX(x) ((x) & (~BITS_P0HI0Q_HOST_IDX))
+#define BIT_GET_P0HI0Q_HOST_IDX(x)                                             \
+	(((x) >> BIT_SHIFT_P0HI0Q_HOST_IDX) & BIT_MASK_P0HI0Q_HOST_IDX)
+#define BIT_SET_P0HI0Q_HOST_IDX(x, v)                                          \
+	(BIT_CLEAR_P0HI0Q_HOST_IDX(x) | BIT_P0HI0Q_HOST_IDX(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_HI1Q_TXBD_IDX			(Offset 0x03BC) */
+
+#define BIT_SHIFT_HI1Q_HW_IDX 16
+#define BIT_MASK_HI1Q_HW_IDX 0xfff
+#define BIT_HI1Q_HW_IDX(x)                                                     \
+	(((x) & BIT_MASK_HI1Q_HW_IDX) << BIT_SHIFT_HI1Q_HW_IDX)
+#define BITS_HI1Q_HW_IDX (BIT_MASK_HI1Q_HW_IDX << BIT_SHIFT_HI1Q_HW_IDX)
+#define BIT_CLEAR_HI1Q_HW_IDX(x) ((x) & (~BITS_HI1Q_HW_IDX))
+#define BIT_GET_HI1Q_HW_IDX(x)                                                 \
+	(((x) >> BIT_SHIFT_HI1Q_HW_IDX) & BIT_MASK_HI1Q_HW_IDX)
+#define BIT_SET_HI1Q_HW_IDX(x, v)                                              \
+	(BIT_CLEAR_HI1Q_HW_IDX(x) | BIT_HI1Q_HW_IDX(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_P0HI1Q_TXBD_IDX			(Offset 0x03BC) */
+
+#define BIT_SHIFT_P0HI1Q_HW_IDX 16
+#define BIT_MASK_P0HI1Q_HW_IDX 0xfff
+#define BIT_P0HI1Q_HW_IDX(x)                                                   \
+	(((x) & BIT_MASK_P0HI1Q_HW_IDX) << BIT_SHIFT_P0HI1Q_HW_IDX)
+#define BITS_P0HI1Q_HW_IDX (BIT_MASK_P0HI1Q_HW_IDX << BIT_SHIFT_P0HI1Q_HW_IDX)
+#define BIT_CLEAR_P0HI1Q_HW_IDX(x) ((x) & (~BITS_P0HI1Q_HW_IDX))
+#define BIT_GET_P0HI1Q_HW_IDX(x)                                               \
+	(((x) >> BIT_SHIFT_P0HI1Q_HW_IDX) & BIT_MASK_P0HI1Q_HW_IDX)
+#define BIT_SET_P0HI1Q_HW_IDX(x, v)                                            \
+	(BIT_CLEAR_P0HI1Q_HW_IDX(x) | BIT_P0HI1Q_HW_IDX(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_HI1Q_TXBD_IDX			(Offset 0x03BC) */
+
+#define BIT_SHIFT_HI1Q_HOST_IDX 0
+#define BIT_MASK_HI1Q_HOST_IDX 0xfff
+#define BIT_HI1Q_HOST_IDX(x)                                                   \
+	(((x) & BIT_MASK_HI1Q_HOST_IDX) << BIT_SHIFT_HI1Q_HOST_IDX)
+#define BITS_HI1Q_HOST_IDX (BIT_MASK_HI1Q_HOST_IDX << BIT_SHIFT_HI1Q_HOST_IDX)
+#define BIT_CLEAR_HI1Q_HOST_IDX(x) ((x) & (~BITS_HI1Q_HOST_IDX))
+#define BIT_GET_HI1Q_HOST_IDX(x)                                               \
+	(((x) >> BIT_SHIFT_HI1Q_HOST_IDX) & BIT_MASK_HI1Q_HOST_IDX)
+#define BIT_SET_HI1Q_HOST_IDX(x, v)                                            \
+	(BIT_CLEAR_HI1Q_HOST_IDX(x) | BIT_HI1Q_HOST_IDX(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_P0HI1Q_TXBD_IDX			(Offset 0x03BC) */
+
+#define BIT_SHIFT_P0HI1Q_HOST_IDX 0
+#define BIT_MASK_P0HI1Q_HOST_IDX 0xfff
+#define BIT_P0HI1Q_HOST_IDX(x)                                                 \
+	(((x) & BIT_MASK_P0HI1Q_HOST_IDX) << BIT_SHIFT_P0HI1Q_HOST_IDX)
+#define BITS_P0HI1Q_HOST_IDX                                                   \
+	(BIT_MASK_P0HI1Q_HOST_IDX << BIT_SHIFT_P0HI1Q_HOST_IDX)
+#define BIT_CLEAR_P0HI1Q_HOST_IDX(x) ((x) & (~BITS_P0HI1Q_HOST_IDX))
+#define BIT_GET_P0HI1Q_HOST_IDX(x)                                             \
+	(((x) >> BIT_SHIFT_P0HI1Q_HOST_IDX) & BIT_MASK_P0HI1Q_HOST_IDX)
+#define BIT_SET_P0HI1Q_HOST_IDX(x, v)                                          \
+	(BIT_CLEAR_P0HI1Q_HOST_IDX(x) | BIT_P0HI1Q_HOST_IDX(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_HI2Q_TXBD_IDX			(Offset 0x03C0) */
+
+#define BIT_SHIFT_HI2Q_HW_IDX 16
+#define BIT_MASK_HI2Q_HW_IDX 0xfff
+#define BIT_HI2Q_HW_IDX(x)                                                     \
+	(((x) & BIT_MASK_HI2Q_HW_IDX) << BIT_SHIFT_HI2Q_HW_IDX)
+#define BITS_HI2Q_HW_IDX (BIT_MASK_HI2Q_HW_IDX << BIT_SHIFT_HI2Q_HW_IDX)
+#define BIT_CLEAR_HI2Q_HW_IDX(x) ((x) & (~BITS_HI2Q_HW_IDX))
+#define BIT_GET_HI2Q_HW_IDX(x)                                                 \
+	(((x) >> BIT_SHIFT_HI2Q_HW_IDX) & BIT_MASK_HI2Q_HW_IDX)
+#define BIT_SET_HI2Q_HW_IDX(x, v)                                              \
+	(BIT_CLEAR_HI2Q_HW_IDX(x) | BIT_HI2Q_HW_IDX(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_P0HI2Q_TXBD_IDX			(Offset 0x03C0) */
+
+#define BIT_SHIFT_P0HI2Q_HW_IDX 16
+#define BIT_MASK_P0HI2Q_HW_IDX 0xfff
+#define BIT_P0HI2Q_HW_IDX(x)                                                   \
+	(((x) & BIT_MASK_P0HI2Q_HW_IDX) << BIT_SHIFT_P0HI2Q_HW_IDX)
+#define BITS_P0HI2Q_HW_IDX (BIT_MASK_P0HI2Q_HW_IDX << BIT_SHIFT_P0HI2Q_HW_IDX)
+#define BIT_CLEAR_P0HI2Q_HW_IDX(x) ((x) & (~BITS_P0HI2Q_HW_IDX))
+#define BIT_GET_P0HI2Q_HW_IDX(x)                                               \
+	(((x) >> BIT_SHIFT_P0HI2Q_HW_IDX) & BIT_MASK_P0HI2Q_HW_IDX)
+#define BIT_SET_P0HI2Q_HW_IDX(x, v)                                            \
+	(BIT_CLEAR_P0HI2Q_HW_IDX(x) | BIT_P0HI2Q_HW_IDX(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_HI2Q_TXBD_IDX			(Offset 0x03C0) */
+
+#define BIT_SHIFT_HI2Q_HOST_IDX 0
+#define BIT_MASK_HI2Q_HOST_IDX 0xfff
+#define BIT_HI2Q_HOST_IDX(x)                                                   \
+	(((x) & BIT_MASK_HI2Q_HOST_IDX) << BIT_SHIFT_HI2Q_HOST_IDX)
+#define BITS_HI2Q_HOST_IDX (BIT_MASK_HI2Q_HOST_IDX << BIT_SHIFT_HI2Q_HOST_IDX)
+#define BIT_CLEAR_HI2Q_HOST_IDX(x) ((x) & (~BITS_HI2Q_HOST_IDX))
+#define BIT_GET_HI2Q_HOST_IDX(x)                                               \
+	(((x) >> BIT_SHIFT_HI2Q_HOST_IDX) & BIT_MASK_HI2Q_HOST_IDX)
+#define BIT_SET_HI2Q_HOST_IDX(x, v)                                            \
+	(BIT_CLEAR_HI2Q_HOST_IDX(x) | BIT_HI2Q_HOST_IDX(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_P0HI2Q_TXBD_IDX			(Offset 0x03C0) */
+
+#define BIT_SHIFT_P0HI2Q_HOST_IDX 0
+#define BIT_MASK_P0HI2Q_HOST_IDX 0xfff
+#define BIT_P0HI2Q_HOST_IDX(x)                                                 \
+	(((x) & BIT_MASK_P0HI2Q_HOST_IDX) << BIT_SHIFT_P0HI2Q_HOST_IDX)
+#define BITS_P0HI2Q_HOST_IDX                                                   \
+	(BIT_MASK_P0HI2Q_HOST_IDX << BIT_SHIFT_P0HI2Q_HOST_IDX)
+#define BIT_CLEAR_P0HI2Q_HOST_IDX(x) ((x) & (~BITS_P0HI2Q_HOST_IDX))
+#define BIT_GET_P0HI2Q_HOST_IDX(x)                                             \
+	(((x) >> BIT_SHIFT_P0HI2Q_HOST_IDX) & BIT_MASK_P0HI2Q_HOST_IDX)
+#define BIT_SET_P0HI2Q_HOST_IDX(x, v)                                          \
+	(BIT_CLEAR_P0HI2Q_HOST_IDX(x) | BIT_P0HI2Q_HOST_IDX(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_HI3Q_TXBD_IDX			(Offset 0x03C4) */
+
+#define BIT_SHIFT_HI3Q_HW_IDX 16
+#define BIT_MASK_HI3Q_HW_IDX 0xfff
+#define BIT_HI3Q_HW_IDX(x)                                                     \
+	(((x) & BIT_MASK_HI3Q_HW_IDX) << BIT_SHIFT_HI3Q_HW_IDX)
+#define BITS_HI3Q_HW_IDX (BIT_MASK_HI3Q_HW_IDX << BIT_SHIFT_HI3Q_HW_IDX)
+#define BIT_CLEAR_HI3Q_HW_IDX(x) ((x) & (~BITS_HI3Q_HW_IDX))
+#define BIT_GET_HI3Q_HW_IDX(x)                                                 \
+	(((x) >> BIT_SHIFT_HI3Q_HW_IDX) & BIT_MASK_HI3Q_HW_IDX)
+#define BIT_SET_HI3Q_HW_IDX(x, v)                                              \
+	(BIT_CLEAR_HI3Q_HW_IDX(x) | BIT_HI3Q_HW_IDX(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_P0HI3Q_TXBD_IDX			(Offset 0x03C4) */
+
+#define BIT_SHIFT_P0HI3Q_HW_IDX 16
+#define BIT_MASK_P0HI3Q_HW_IDX 0xfff
+#define BIT_P0HI3Q_HW_IDX(x)                                                   \
+	(((x) & BIT_MASK_P0HI3Q_HW_IDX) << BIT_SHIFT_P0HI3Q_HW_IDX)
+#define BITS_P0HI3Q_HW_IDX (BIT_MASK_P0HI3Q_HW_IDX << BIT_SHIFT_P0HI3Q_HW_IDX)
+#define BIT_CLEAR_P0HI3Q_HW_IDX(x) ((x) & (~BITS_P0HI3Q_HW_IDX))
+#define BIT_GET_P0HI3Q_HW_IDX(x)                                               \
+	(((x) >> BIT_SHIFT_P0HI3Q_HW_IDX) & BIT_MASK_P0HI3Q_HW_IDX)
+#define BIT_SET_P0HI3Q_HW_IDX(x, v)                                            \
+	(BIT_CLEAR_P0HI3Q_HW_IDX(x) | BIT_P0HI3Q_HW_IDX(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_HI3Q_TXBD_IDX			(Offset 0x03C4) */
+
+#define BIT_SHIFT_HI3Q_HOST_IDX 0
+#define BIT_MASK_HI3Q_HOST_IDX 0xfff
+#define BIT_HI3Q_HOST_IDX(x)                                                   \
+	(((x) & BIT_MASK_HI3Q_HOST_IDX) << BIT_SHIFT_HI3Q_HOST_IDX)
+#define BITS_HI3Q_HOST_IDX (BIT_MASK_HI3Q_HOST_IDX << BIT_SHIFT_HI3Q_HOST_IDX)
+#define BIT_CLEAR_HI3Q_HOST_IDX(x) ((x) & (~BITS_HI3Q_HOST_IDX))
+#define BIT_GET_HI3Q_HOST_IDX(x)                                               \
+	(((x) >> BIT_SHIFT_HI3Q_HOST_IDX) & BIT_MASK_HI3Q_HOST_IDX)
+#define BIT_SET_HI3Q_HOST_IDX(x, v)                                            \
+	(BIT_CLEAR_HI3Q_HOST_IDX(x) | BIT_HI3Q_HOST_IDX(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_P0HI3Q_TXBD_IDX			(Offset 0x03C4) */
+
+#define BIT_SHIFT_P0HI3Q_HOST_IDX 0
+#define BIT_MASK_P0HI3Q_HOST_IDX 0xfff
+#define BIT_P0HI3Q_HOST_IDX(x)                                                 \
+	(((x) & BIT_MASK_P0HI3Q_HOST_IDX) << BIT_SHIFT_P0HI3Q_HOST_IDX)
+#define BITS_P0HI3Q_HOST_IDX                                                   \
+	(BIT_MASK_P0HI3Q_HOST_IDX << BIT_SHIFT_P0HI3Q_HOST_IDX)
+#define BIT_CLEAR_P0HI3Q_HOST_IDX(x) ((x) & (~BITS_P0HI3Q_HOST_IDX))
+#define BIT_GET_P0HI3Q_HOST_IDX(x)                                             \
+	(((x) >> BIT_SHIFT_P0HI3Q_HOST_IDX) & BIT_MASK_P0HI3Q_HOST_IDX)
+#define BIT_SET_P0HI3Q_HOST_IDX(x, v)                                          \
+	(BIT_CLEAR_P0HI3Q_HOST_IDX(x) | BIT_P0HI3Q_HOST_IDX(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_HI4Q_TXBD_IDX			(Offset 0x03C8) */
+
+#define BIT_SHIFT_HI4Q_HW_IDX 16
+#define BIT_MASK_HI4Q_HW_IDX 0xfff
+#define BIT_HI4Q_HW_IDX(x)                                                     \
+	(((x) & BIT_MASK_HI4Q_HW_IDX) << BIT_SHIFT_HI4Q_HW_IDX)
+#define BITS_HI4Q_HW_IDX (BIT_MASK_HI4Q_HW_IDX << BIT_SHIFT_HI4Q_HW_IDX)
+#define BIT_CLEAR_HI4Q_HW_IDX(x) ((x) & (~BITS_HI4Q_HW_IDX))
+#define BIT_GET_HI4Q_HW_IDX(x)                                                 \
+	(((x) >> BIT_SHIFT_HI4Q_HW_IDX) & BIT_MASK_HI4Q_HW_IDX)
+#define BIT_SET_HI4Q_HW_IDX(x, v)                                              \
+	(BIT_CLEAR_HI4Q_HW_IDX(x) | BIT_HI4Q_HW_IDX(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_P0HI4Q_TXBD_IDX			(Offset 0x03C8) */
+
+#define BIT_SHIFT_P0HI4Q_HW_IDX 16
+#define BIT_MASK_P0HI4Q_HW_IDX 0xfff
+#define BIT_P0HI4Q_HW_IDX(x)                                                   \
+	(((x) & BIT_MASK_P0HI4Q_HW_IDX) << BIT_SHIFT_P0HI4Q_HW_IDX)
+#define BITS_P0HI4Q_HW_IDX (BIT_MASK_P0HI4Q_HW_IDX << BIT_SHIFT_P0HI4Q_HW_IDX)
+#define BIT_CLEAR_P0HI4Q_HW_IDX(x) ((x) & (~BITS_P0HI4Q_HW_IDX))
+#define BIT_GET_P0HI4Q_HW_IDX(x)                                               \
+	(((x) >> BIT_SHIFT_P0HI4Q_HW_IDX) & BIT_MASK_P0HI4Q_HW_IDX)
+#define BIT_SET_P0HI4Q_HW_IDX(x, v)                                            \
+	(BIT_CLEAR_P0HI4Q_HW_IDX(x) | BIT_P0HI4Q_HW_IDX(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_HI4Q_TXBD_IDX			(Offset 0x03C8) */
+
+#define BIT_SHIFT_HI4Q_HOST_IDX 0
+#define BIT_MASK_HI4Q_HOST_IDX 0xfff
+#define BIT_HI4Q_HOST_IDX(x)                                                   \
+	(((x) & BIT_MASK_HI4Q_HOST_IDX) << BIT_SHIFT_HI4Q_HOST_IDX)
+#define BITS_HI4Q_HOST_IDX (BIT_MASK_HI4Q_HOST_IDX << BIT_SHIFT_HI4Q_HOST_IDX)
+#define BIT_CLEAR_HI4Q_HOST_IDX(x) ((x) & (~BITS_HI4Q_HOST_IDX))
+#define BIT_GET_HI4Q_HOST_IDX(x)                                               \
+	(((x) >> BIT_SHIFT_HI4Q_HOST_IDX) & BIT_MASK_HI4Q_HOST_IDX)
+#define BIT_SET_HI4Q_HOST_IDX(x, v)                                            \
+	(BIT_CLEAR_HI4Q_HOST_IDX(x) | BIT_HI4Q_HOST_IDX(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_P0HI4Q_TXBD_IDX			(Offset 0x03C8) */
+
+#define BIT_SHIFT_P0HI4Q_HOST_IDX 0
+#define BIT_MASK_P0HI4Q_HOST_IDX 0xfff
+#define BIT_P0HI4Q_HOST_IDX(x)                                                 \
+	(((x) & BIT_MASK_P0HI4Q_HOST_IDX) << BIT_SHIFT_P0HI4Q_HOST_IDX)
+#define BITS_P0HI4Q_HOST_IDX                                                   \
+	(BIT_MASK_P0HI4Q_HOST_IDX << BIT_SHIFT_P0HI4Q_HOST_IDX)
+#define BIT_CLEAR_P0HI4Q_HOST_IDX(x) ((x) & (~BITS_P0HI4Q_HOST_IDX))
+#define BIT_GET_P0HI4Q_HOST_IDX(x)                                             \
+	(((x) >> BIT_SHIFT_P0HI4Q_HOST_IDX) & BIT_MASK_P0HI4Q_HOST_IDX)
+#define BIT_SET_P0HI4Q_HOST_IDX(x, v)                                          \
+	(BIT_CLEAR_P0HI4Q_HOST_IDX(x) | BIT_P0HI4Q_HOST_IDX(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_HI5Q_TXBD_IDX			(Offset 0x03CC) */
+
+#define BIT_SHIFT_HI5Q_HW_IDX 16
+#define BIT_MASK_HI5Q_HW_IDX 0xfff
+#define BIT_HI5Q_HW_IDX(x)                                                     \
+	(((x) & BIT_MASK_HI5Q_HW_IDX) << BIT_SHIFT_HI5Q_HW_IDX)
+#define BITS_HI5Q_HW_IDX (BIT_MASK_HI5Q_HW_IDX << BIT_SHIFT_HI5Q_HW_IDX)
+#define BIT_CLEAR_HI5Q_HW_IDX(x) ((x) & (~BITS_HI5Q_HW_IDX))
+#define BIT_GET_HI5Q_HW_IDX(x)                                                 \
+	(((x) >> BIT_SHIFT_HI5Q_HW_IDX) & BIT_MASK_HI5Q_HW_IDX)
+#define BIT_SET_HI5Q_HW_IDX(x, v)                                              \
+	(BIT_CLEAR_HI5Q_HW_IDX(x) | BIT_HI5Q_HW_IDX(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_P0HI5Q_TXBD_IDX			(Offset 0x03CC) */
+
+#define BIT_SHIFT_P0HI5Q_HW_IDX 16
+#define BIT_MASK_P0HI5Q_HW_IDX 0xfff
+#define BIT_P0HI5Q_HW_IDX(x)                                                   \
+	(((x) & BIT_MASK_P0HI5Q_HW_IDX) << BIT_SHIFT_P0HI5Q_HW_IDX)
+#define BITS_P0HI5Q_HW_IDX (BIT_MASK_P0HI5Q_HW_IDX << BIT_SHIFT_P0HI5Q_HW_IDX)
+#define BIT_CLEAR_P0HI5Q_HW_IDX(x) ((x) & (~BITS_P0HI5Q_HW_IDX))
+#define BIT_GET_P0HI5Q_HW_IDX(x)                                               \
+	(((x) >> BIT_SHIFT_P0HI5Q_HW_IDX) & BIT_MASK_P0HI5Q_HW_IDX)
+#define BIT_SET_P0HI5Q_HW_IDX(x, v)                                            \
+	(BIT_CLEAR_P0HI5Q_HW_IDX(x) | BIT_P0HI5Q_HW_IDX(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_HI5Q_TXBD_IDX			(Offset 0x03CC) */
+
+#define BIT_SHIFT_HI5Q_HOST_IDX 0
+#define BIT_MASK_HI5Q_HOST_IDX 0xfff
+#define BIT_HI5Q_HOST_IDX(x)                                                   \
+	(((x) & BIT_MASK_HI5Q_HOST_IDX) << BIT_SHIFT_HI5Q_HOST_IDX)
+#define BITS_HI5Q_HOST_IDX (BIT_MASK_HI5Q_HOST_IDX << BIT_SHIFT_HI5Q_HOST_IDX)
+#define BIT_CLEAR_HI5Q_HOST_IDX(x) ((x) & (~BITS_HI5Q_HOST_IDX))
+#define BIT_GET_HI5Q_HOST_IDX(x)                                               \
+	(((x) >> BIT_SHIFT_HI5Q_HOST_IDX) & BIT_MASK_HI5Q_HOST_IDX)
+#define BIT_SET_HI5Q_HOST_IDX(x, v)                                            \
+	(BIT_CLEAR_HI5Q_HOST_IDX(x) | BIT_HI5Q_HOST_IDX(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_P0HI5Q_TXBD_IDX			(Offset 0x03CC) */
+
+#define BIT_SHIFT_P0HI5Q_HOST_IDX 0
+#define BIT_MASK_P0HI5Q_HOST_IDX 0xfff
+#define BIT_P0HI5Q_HOST_IDX(x)                                                 \
+	(((x) & BIT_MASK_P0HI5Q_HOST_IDX) << BIT_SHIFT_P0HI5Q_HOST_IDX)
+#define BITS_P0HI5Q_HOST_IDX                                                   \
+	(BIT_MASK_P0HI5Q_HOST_IDX << BIT_SHIFT_P0HI5Q_HOST_IDX)
+#define BIT_CLEAR_P0HI5Q_HOST_IDX(x) ((x) & (~BITS_P0HI5Q_HOST_IDX))
+#define BIT_GET_P0HI5Q_HOST_IDX(x)                                             \
+	(((x) >> BIT_SHIFT_P0HI5Q_HOST_IDX) & BIT_MASK_P0HI5Q_HOST_IDX)
+#define BIT_SET_P0HI5Q_HOST_IDX(x, v)                                          \
+	(BIT_CLEAR_P0HI5Q_HOST_IDX(x) | BIT_P0HI5Q_HOST_IDX(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_HI6Q_TXBD_IDX			(Offset 0x03D0) */
+
+#define BIT_SHIFT_HI6Q_HW_IDX 16
+#define BIT_MASK_HI6Q_HW_IDX 0xfff
+#define BIT_HI6Q_HW_IDX(x)                                                     \
+	(((x) & BIT_MASK_HI6Q_HW_IDX) << BIT_SHIFT_HI6Q_HW_IDX)
+#define BITS_HI6Q_HW_IDX (BIT_MASK_HI6Q_HW_IDX << BIT_SHIFT_HI6Q_HW_IDX)
+#define BIT_CLEAR_HI6Q_HW_IDX(x) ((x) & (~BITS_HI6Q_HW_IDX))
+#define BIT_GET_HI6Q_HW_IDX(x)                                                 \
+	(((x) >> BIT_SHIFT_HI6Q_HW_IDX) & BIT_MASK_HI6Q_HW_IDX)
+#define BIT_SET_HI6Q_HW_IDX(x, v)                                              \
+	(BIT_CLEAR_HI6Q_HW_IDX(x) | BIT_HI6Q_HW_IDX(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_P0HI6Q_TXBD_IDX			(Offset 0x03D0) */
+
+#define BIT_SHIFT_P0HI6Q_HW_IDX 16
+#define BIT_MASK_P0HI6Q_HW_IDX 0xfff
+#define BIT_P0HI6Q_HW_IDX(x)                                                   \
+	(((x) & BIT_MASK_P0HI6Q_HW_IDX) << BIT_SHIFT_P0HI6Q_HW_IDX)
+#define BITS_P0HI6Q_HW_IDX (BIT_MASK_P0HI6Q_HW_IDX << BIT_SHIFT_P0HI6Q_HW_IDX)
+#define BIT_CLEAR_P0HI6Q_HW_IDX(x) ((x) & (~BITS_P0HI6Q_HW_IDX))
+#define BIT_GET_P0HI6Q_HW_IDX(x)                                               \
+	(((x) >> BIT_SHIFT_P0HI6Q_HW_IDX) & BIT_MASK_P0HI6Q_HW_IDX)
+#define BIT_SET_P0HI6Q_HW_IDX(x, v)                                            \
+	(BIT_CLEAR_P0HI6Q_HW_IDX(x) | BIT_P0HI6Q_HW_IDX(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_HI6Q_TXBD_IDX			(Offset 0x03D0) */
+
+#define BIT_SHIFT_HI6Q_HOST_IDX 0
+#define BIT_MASK_HI6Q_HOST_IDX 0xfff
+#define BIT_HI6Q_HOST_IDX(x)                                                   \
+	(((x) & BIT_MASK_HI6Q_HOST_IDX) << BIT_SHIFT_HI6Q_HOST_IDX)
+#define BITS_HI6Q_HOST_IDX (BIT_MASK_HI6Q_HOST_IDX << BIT_SHIFT_HI6Q_HOST_IDX)
+#define BIT_CLEAR_HI6Q_HOST_IDX(x) ((x) & (~BITS_HI6Q_HOST_IDX))
+#define BIT_GET_HI6Q_HOST_IDX(x)                                               \
+	(((x) >> BIT_SHIFT_HI6Q_HOST_IDX) & BIT_MASK_HI6Q_HOST_IDX)
+#define BIT_SET_HI6Q_HOST_IDX(x, v)                                            \
+	(BIT_CLEAR_HI6Q_HOST_IDX(x) | BIT_HI6Q_HOST_IDX(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_P0HI6Q_TXBD_IDX			(Offset 0x03D0) */
+
+#define BIT_SHIFT_P0HI6Q_HOST_IDX 0
+#define BIT_MASK_P0HI6Q_HOST_IDX 0xfff
+#define BIT_P0HI6Q_HOST_IDX(x)                                                 \
+	(((x) & BIT_MASK_P0HI6Q_HOST_IDX) << BIT_SHIFT_P0HI6Q_HOST_IDX)
+#define BITS_P0HI6Q_HOST_IDX                                                   \
+	(BIT_MASK_P0HI6Q_HOST_IDX << BIT_SHIFT_P0HI6Q_HOST_IDX)
+#define BIT_CLEAR_P0HI6Q_HOST_IDX(x) ((x) & (~BITS_P0HI6Q_HOST_IDX))
+#define BIT_GET_P0HI6Q_HOST_IDX(x)                                             \
+	(((x) >> BIT_SHIFT_P0HI6Q_HOST_IDX) & BIT_MASK_P0HI6Q_HOST_IDX)
+#define BIT_SET_P0HI6Q_HOST_IDX(x, v)                                          \
+	(BIT_CLEAR_P0HI6Q_HOST_IDX(x) | BIT_P0HI6Q_HOST_IDX(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_HI7Q_TXBD_IDX			(Offset 0x03D4) */
+
+#define BIT_SHIFT_HI7Q_HW_IDX 16
+#define BIT_MASK_HI7Q_HW_IDX 0xfff
+#define BIT_HI7Q_HW_IDX(x)                                                     \
+	(((x) & BIT_MASK_HI7Q_HW_IDX) << BIT_SHIFT_HI7Q_HW_IDX)
+#define BITS_HI7Q_HW_IDX (BIT_MASK_HI7Q_HW_IDX << BIT_SHIFT_HI7Q_HW_IDX)
+#define BIT_CLEAR_HI7Q_HW_IDX(x) ((x) & (~BITS_HI7Q_HW_IDX))
+#define BIT_GET_HI7Q_HW_IDX(x)                                                 \
+	(((x) >> BIT_SHIFT_HI7Q_HW_IDX) & BIT_MASK_HI7Q_HW_IDX)
+#define BIT_SET_HI7Q_HW_IDX(x, v)                                              \
+	(BIT_CLEAR_HI7Q_HW_IDX(x) | BIT_HI7Q_HW_IDX(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_P0HI7Q_TXBD_IDX			(Offset 0x03D4) */
+
+#define BIT_SHIFT_P0HI7Q_HW_IDX 16
+#define BIT_MASK_P0HI7Q_HW_IDX 0xfff
+#define BIT_P0HI7Q_HW_IDX(x)                                                   \
+	(((x) & BIT_MASK_P0HI7Q_HW_IDX) << BIT_SHIFT_P0HI7Q_HW_IDX)
+#define BITS_P0HI7Q_HW_IDX (BIT_MASK_P0HI7Q_HW_IDX << BIT_SHIFT_P0HI7Q_HW_IDX)
+#define BIT_CLEAR_P0HI7Q_HW_IDX(x) ((x) & (~BITS_P0HI7Q_HW_IDX))
+#define BIT_GET_P0HI7Q_HW_IDX(x)                                               \
+	(((x) >> BIT_SHIFT_P0HI7Q_HW_IDX) & BIT_MASK_P0HI7Q_HW_IDX)
+#define BIT_SET_P0HI7Q_HW_IDX(x, v)                                            \
+	(BIT_CLEAR_P0HI7Q_HW_IDX(x) | BIT_P0HI7Q_HW_IDX(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_HI7Q_TXBD_IDX			(Offset 0x03D4) */
+
+#define BIT_SHIFT_HI7Q_HOST_IDX 0
+#define BIT_MASK_HI7Q_HOST_IDX 0xfff
+#define BIT_HI7Q_HOST_IDX(x)                                                   \
+	(((x) & BIT_MASK_HI7Q_HOST_IDX) << BIT_SHIFT_HI7Q_HOST_IDX)
+#define BITS_HI7Q_HOST_IDX (BIT_MASK_HI7Q_HOST_IDX << BIT_SHIFT_HI7Q_HOST_IDX)
+#define BIT_CLEAR_HI7Q_HOST_IDX(x) ((x) & (~BITS_HI7Q_HOST_IDX))
+#define BIT_GET_HI7Q_HOST_IDX(x)                                               \
+	(((x) >> BIT_SHIFT_HI7Q_HOST_IDX) & BIT_MASK_HI7Q_HOST_IDX)
+#define BIT_SET_HI7Q_HOST_IDX(x, v)                                            \
+	(BIT_CLEAR_HI7Q_HOST_IDX(x) | BIT_HI7Q_HOST_IDX(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_P0HI7Q_TXBD_IDX			(Offset 0x03D4) */
+
+#define BIT_SHIFT_P0HI7Q_HOST_IDX 0
+#define BIT_MASK_P0HI7Q_HOST_IDX 0xfff
+#define BIT_P0HI7Q_HOST_IDX(x)                                                 \
+	(((x) & BIT_MASK_P0HI7Q_HOST_IDX) << BIT_SHIFT_P0HI7Q_HOST_IDX)
+#define BITS_P0HI7Q_HOST_IDX                                                   \
+	(BIT_MASK_P0HI7Q_HOST_IDX << BIT_SHIFT_P0HI7Q_HOST_IDX)
+#define BIT_CLEAR_P0HI7Q_HOST_IDX(x) ((x) & (~BITS_P0HI7Q_HOST_IDX))
+#define BIT_GET_P0HI7Q_HOST_IDX(x)                                             \
+	(((x) >> BIT_SHIFT_P0HI7Q_HOST_IDX) & BIT_MASK_P0HI7Q_HOST_IDX)
+#define BIT_SET_P0HI7Q_HOST_IDX(x, v)                                          \
+	(BIT_CLEAR_P0HI7Q_HOST_IDX(x) | BIT_P0HI7Q_HOST_IDX(v))
+
+/* 2 REG_DBGSEL_PCIE_HRPWM1_HCPWM1_V1	(Offset 0x03D8) */
+
+#define BIT_DIS_TXDMA_PRE_V1 BIT(31)
+#define BIT_DIS_RXDMA_PRE_V1 BIT(30)
+
+#define BIT_SHIFT_HPS_CLKR_PCIE_V1 28
+#define BIT_MASK_HPS_CLKR_PCIE_V1 0x3
+#define BIT_HPS_CLKR_PCIE_V1(x)                                                \
+	(((x) & BIT_MASK_HPS_CLKR_PCIE_V1) << BIT_SHIFT_HPS_CLKR_PCIE_V1)
+#define BITS_HPS_CLKR_PCIE_V1                                                  \
+	(BIT_MASK_HPS_CLKR_PCIE_V1 << BIT_SHIFT_HPS_CLKR_PCIE_V1)
+#define BIT_CLEAR_HPS_CLKR_PCIE_V1(x) ((x) & (~BITS_HPS_CLKR_PCIE_V1))
+#define BIT_GET_HPS_CLKR_PCIE_V1(x)                                            \
+	(((x) >> BIT_SHIFT_HPS_CLKR_PCIE_V1) & BIT_MASK_HPS_CLKR_PCIE_V1)
+#define BIT_SET_HPS_CLKR_PCIE_V1(x, v)                                         \
+	(BIT_CLEAR_HPS_CLKR_PCIE_V1(x) | BIT_HPS_CLKR_PCIE_V1(v))
+
+#define BIT_PCIE_INT_V1 BIT(27)
+#define BIT_TXFLAG_EXIT_L1_EN_V1 BIT(26)
+#define BIT_EN_RXDMA_ALIGN_V2 BIT(25)
+#define BIT_EN_TXDMA_ALIGN_V2 BIT(24)
+
+#define BIT_SHIFT_PCIE_HCPWM_V1 16
+#define BIT_MASK_PCIE_HCPWM_V1 0xff
+#define BIT_PCIE_HCPWM_V1(x)                                                   \
+	(((x) & BIT_MASK_PCIE_HCPWM_V1) << BIT_SHIFT_PCIE_HCPWM_V1)
+#define BITS_PCIE_HCPWM_V1 (BIT_MASK_PCIE_HCPWM_V1 << BIT_SHIFT_PCIE_HCPWM_V1)
+#define BIT_CLEAR_PCIE_HCPWM_V1(x) ((x) & (~BITS_PCIE_HCPWM_V1))
+#define BIT_GET_PCIE_HCPWM_V1(x)                                               \
+	(((x) >> BIT_SHIFT_PCIE_HCPWM_V1) & BIT_MASK_PCIE_HCPWM_V1)
+#define BIT_SET_PCIE_HCPWM_V1(x, v)                                            \
+	(BIT_CLEAR_PCIE_HCPWM_V1(x) | BIT_PCIE_HCPWM_V1(v))
+
+#define BIT_SHIFT_PCIE_HRPWM_V1 8
+#define BIT_MASK_PCIE_HRPWM_V1 0xff
+#define BIT_PCIE_HRPWM_V1(x)                                                   \
+	(((x) & BIT_MASK_PCIE_HRPWM_V1) << BIT_SHIFT_PCIE_HRPWM_V1)
+#define BITS_PCIE_HRPWM_V1 (BIT_MASK_PCIE_HRPWM_V1 << BIT_SHIFT_PCIE_HRPWM_V1)
+#define BIT_CLEAR_PCIE_HRPWM_V1(x) ((x) & (~BITS_PCIE_HRPWM_V1))
+#define BIT_GET_PCIE_HRPWM_V1(x)                                               \
+	(((x) >> BIT_SHIFT_PCIE_HRPWM_V1) & BIT_MASK_PCIE_HRPWM_V1)
+#define BIT_SET_PCIE_HRPWM_V1(x, v)                                            \
+	(BIT_CLEAR_PCIE_HRPWM_V1(x) | BIT_PCIE_HRPWM_V1(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_DBG_SEL_V1				(Offset 0x03D8) */
+
+#define BIT_SHIFT_DBG_SEL 0
+#define BIT_MASK_DBG_SEL 0xff
+#define BIT_DBG_SEL(x) (((x) & BIT_MASK_DBG_SEL) << BIT_SHIFT_DBG_SEL)
+#define BITS_DBG_SEL (BIT_MASK_DBG_SEL << BIT_SHIFT_DBG_SEL)
+#define BIT_CLEAR_DBG_SEL(x) ((x) & (~BITS_DBG_SEL))
+#define BIT_GET_DBG_SEL(x) (((x) >> BIT_SHIFT_DBG_SEL) & BIT_MASK_DBG_SEL)
+#define BIT_SET_DBG_SEL(x, v) (BIT_CLEAR_DBG_SEL(x) | BIT_DBG_SEL(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_PCIE_HRPWM1_V1			(Offset 0x03D9) */
+
+#define BIT_SHIFT_PCIE_HRPWM 0
+#define BIT_MASK_PCIE_HRPWM 0xff
+#define BIT_PCIE_HRPWM(x) (((x) & BIT_MASK_PCIE_HRPWM) << BIT_SHIFT_PCIE_HRPWM)
+#define BITS_PCIE_HRPWM (BIT_MASK_PCIE_HRPWM << BIT_SHIFT_PCIE_HRPWM)
+#define BIT_CLEAR_PCIE_HRPWM(x) ((x) & (~BITS_PCIE_HRPWM))
+#define BIT_GET_PCIE_HRPWM(x)                                                  \
+	(((x) >> BIT_SHIFT_PCIE_HRPWM) & BIT_MASK_PCIE_HRPWM)
+#define BIT_SET_PCIE_HRPWM(x, v) (BIT_CLEAR_PCIE_HRPWM(x) | BIT_PCIE_HRPWM(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_HCI_HRPWM1_V1			(Offset 0x03D9) */
+
+#define BIT_SHIFT_HCI_HRPWM 0
+#define BIT_MASK_HCI_HRPWM 0xff
+#define BIT_HCI_HRPWM(x) (((x) & BIT_MASK_HCI_HRPWM) << BIT_SHIFT_HCI_HRPWM)
+#define BITS_HCI_HRPWM (BIT_MASK_HCI_HRPWM << BIT_SHIFT_HCI_HRPWM)
+#define BIT_CLEAR_HCI_HRPWM(x) ((x) & (~BITS_HCI_HRPWM))
+#define BIT_GET_HCI_HRPWM(x) (((x) >> BIT_SHIFT_HCI_HRPWM) & BIT_MASK_HCI_HRPWM)
+#define BIT_SET_HCI_HRPWM(x, v) (BIT_CLEAR_HCI_HRPWM(x) | BIT_HCI_HRPWM(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_PCIE_HCPWM1_V1			(Offset 0x03DA) */
+
+#define BIT_SHIFT_PCIE_HCPWM 0
+#define BIT_MASK_PCIE_HCPWM 0xff
+#define BIT_PCIE_HCPWM(x) (((x) & BIT_MASK_PCIE_HCPWM) << BIT_SHIFT_PCIE_HCPWM)
+#define BITS_PCIE_HCPWM (BIT_MASK_PCIE_HCPWM << BIT_SHIFT_PCIE_HCPWM)
+#define BIT_CLEAR_PCIE_HCPWM(x) ((x) & (~BITS_PCIE_HCPWM))
+#define BIT_GET_PCIE_HCPWM(x)                                                  \
+	(((x) >> BIT_SHIFT_PCIE_HCPWM) & BIT_MASK_PCIE_HCPWM)
+#define BIT_SET_PCIE_HCPWM(x, v) (BIT_CLEAR_PCIE_HCPWM(x) | BIT_PCIE_HCPWM(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_HCI_HCPWM1_V1			(Offset 0x03DA) */
+
+#define BIT_SHIFT_HCI_HCPWM 0
+#define BIT_MASK_HCI_HCPWM 0xff
+#define BIT_HCI_HCPWM(x) (((x) & BIT_MASK_HCI_HCPWM) << BIT_SHIFT_HCI_HCPWM)
+#define BITS_HCI_HCPWM (BIT_MASK_HCI_HCPWM << BIT_SHIFT_HCI_HCPWM)
+#define BIT_CLEAR_HCI_HCPWM(x) ((x) & (~BITS_HCI_HCPWM))
+#define BIT_GET_HCI_HCPWM(x) (((x) >> BIT_SHIFT_HCI_HCPWM) & BIT_MASK_HCI_HCPWM)
+#define BIT_SET_HCI_HCPWM(x, v) (BIT_CLEAR_HCI_HCPWM(x) | BIT_HCI_HCPWM(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_PCIE_CTRL2				(Offset 0x03DB) */
+
+#define BIT_SHIFT_HPS_CLKR_PCIE 4
+#define BIT_MASK_HPS_CLKR_PCIE 0x3
+#define BIT_HPS_CLKR_PCIE(x)                                                   \
+	(((x) & BIT_MASK_HPS_CLKR_PCIE) << BIT_SHIFT_HPS_CLKR_PCIE)
+#define BITS_HPS_CLKR_PCIE (BIT_MASK_HPS_CLKR_PCIE << BIT_SHIFT_HPS_CLKR_PCIE)
+#define BIT_CLEAR_HPS_CLKR_PCIE(x) ((x) & (~BITS_HPS_CLKR_PCIE))
+#define BIT_GET_HPS_CLKR_PCIE(x)                                               \
+	(((x) >> BIT_SHIFT_HPS_CLKR_PCIE) & BIT_MASK_HPS_CLKR_PCIE)
+#define BIT_SET_HPS_CLKR_PCIE(x, v)                                            \
+	(BIT_CLEAR_HPS_CLKR_PCIE(x) | BIT_HPS_CLKR_PCIE(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_HCI_CTRL2				(Offset 0x03DB) */
+
+#define BIT_SHIFT_HPS_CLKR_HCI 4
+#define BIT_MASK_HPS_CLKR_HCI 0x3
+#define BIT_HPS_CLKR_HCI(x)                                                    \
+	(((x) & BIT_MASK_HPS_CLKR_HCI) << BIT_SHIFT_HPS_CLKR_HCI)
+#define BITS_HPS_CLKR_HCI (BIT_MASK_HPS_CLKR_HCI << BIT_SHIFT_HPS_CLKR_HCI)
+#define BIT_CLEAR_HPS_CLKR_HCI(x) ((x) & (~BITS_HPS_CLKR_HCI))
+#define BIT_GET_HPS_CLKR_HCI(x)                                                \
+	(((x) >> BIT_SHIFT_HPS_CLKR_HCI) & BIT_MASK_HPS_CLKR_HCI)
+#define BIT_SET_HPS_CLKR_HCI(x, v)                                             \
+	(BIT_CLEAR_HPS_CLKR_HCI(x) | BIT_HPS_CLKR_HCI(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_PCIE_CTRL2				(Offset 0x03DB) */
+
+#define BIT_PCIE_INT BIT(3)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_HCI_CTRL2				(Offset 0x03DB) */
+
+#define BIT_HCI_INT BIT(3)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_PCIE_CTRL2				(Offset 0x03DB) */
+
+#define BIT_EN_RXDMA_ALIGN BIT(1)
+#define BIT_EN_TXDMA_ALIGN BIT(0)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_PCIE_HRPWM2_HCPWM2_V1		(Offset 0x03DC) */
+
+#define BIT_SHIFT_PCIE_HCPWM2_V1 16
+#define BIT_MASK_PCIE_HCPWM2_V1 0xffff
+#define BIT_PCIE_HCPWM2_V1(x)                                                  \
+	(((x) & BIT_MASK_PCIE_HCPWM2_V1) << BIT_SHIFT_PCIE_HCPWM2_V1)
+#define BITS_PCIE_HCPWM2_V1                                                    \
+	(BIT_MASK_PCIE_HCPWM2_V1 << BIT_SHIFT_PCIE_HCPWM2_V1)
+#define BIT_CLEAR_PCIE_HCPWM2_V1(x) ((x) & (~BITS_PCIE_HCPWM2_V1))
+#define BIT_GET_PCIE_HCPWM2_V1(x)                                              \
+	(((x) >> BIT_SHIFT_PCIE_HCPWM2_V1) & BIT_MASK_PCIE_HCPWM2_V1)
+#define BIT_SET_PCIE_HCPWM2_V1(x, v)                                           \
+	(BIT_CLEAR_PCIE_HCPWM2_V1(x) | BIT_PCIE_HCPWM2_V1(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8881A_SUPPORT)
+
+/* 2 REG_PCIE_HRPWM2_V1			(Offset 0x03DC) */
+
+#define BIT_SHIFT_PCIE_HRPWM2 0
+#define BIT_MASK_PCIE_HRPWM2 0xffff
+#define BIT_PCIE_HRPWM2(x)                                                     \
+	(((x) & BIT_MASK_PCIE_HRPWM2) << BIT_SHIFT_PCIE_HRPWM2)
+#define BITS_PCIE_HRPWM2 (BIT_MASK_PCIE_HRPWM2 << BIT_SHIFT_PCIE_HRPWM2)
+#define BIT_CLEAR_PCIE_HRPWM2(x) ((x) & (~BITS_PCIE_HRPWM2))
+#define BIT_GET_PCIE_HRPWM2(x)                                                 \
+	(((x) >> BIT_SHIFT_PCIE_HRPWM2) & BIT_MASK_PCIE_HRPWM2)
+#define BIT_SET_PCIE_HRPWM2(x, v)                                              \
+	(BIT_CLEAR_PCIE_HRPWM2(x) | BIT_PCIE_HRPWM2(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_HCI_HRPWM2_V1			(Offset 0x03DC) */
+
+#define BIT_SHIFT_HCI_HRPWM2 0
+#define BIT_MASK_HCI_HRPWM2 0xffff
+#define BIT_HCI_HRPWM2(x) (((x) & BIT_MASK_HCI_HRPWM2) << BIT_SHIFT_HCI_HRPWM2)
+#define BITS_HCI_HRPWM2 (BIT_MASK_HCI_HRPWM2 << BIT_SHIFT_HCI_HRPWM2)
+#define BIT_CLEAR_HCI_HRPWM2(x) ((x) & (~BITS_HCI_HRPWM2))
+#define BIT_GET_HCI_HRPWM2(x)                                                  \
+	(((x) >> BIT_SHIFT_HCI_HRPWM2) & BIT_MASK_HCI_HRPWM2)
+#define BIT_SET_HCI_HRPWM2(x, v) (BIT_CLEAR_HCI_HRPWM2(x) | BIT_HCI_HRPWM2(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_PCIE_HCPWM2_V1			(Offset 0x03DE) */
+
+#define BIT_SHIFT_PCIE_HCPWM2 0
+#define BIT_MASK_PCIE_HCPWM2 0xffff
+#define BIT_PCIE_HCPWM2(x)                                                     \
+	(((x) & BIT_MASK_PCIE_HCPWM2) << BIT_SHIFT_PCIE_HCPWM2)
+#define BITS_PCIE_HCPWM2 (BIT_MASK_PCIE_HCPWM2 << BIT_SHIFT_PCIE_HCPWM2)
+#define BIT_CLEAR_PCIE_HCPWM2(x) ((x) & (~BITS_PCIE_HCPWM2))
+#define BIT_GET_PCIE_HCPWM2(x)                                                 \
+	(((x) >> BIT_SHIFT_PCIE_HCPWM2) & BIT_MASK_PCIE_HCPWM2)
+#define BIT_SET_PCIE_HCPWM2(x, v)                                              \
+	(BIT_CLEAR_PCIE_HCPWM2(x) | BIT_PCIE_HCPWM2(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_HCI_HCPWM2_V1			(Offset 0x03DE) */
+
+#define BIT_SHIFT_HCI_HCPWM2 0
+#define BIT_MASK_HCI_HCPWM2 0xffff
+#define BIT_HCI_HCPWM2(x) (((x) & BIT_MASK_HCI_HCPWM2) << BIT_SHIFT_HCI_HCPWM2)
+#define BITS_HCI_HCPWM2 (BIT_MASK_HCI_HCPWM2 << BIT_SHIFT_HCI_HCPWM2)
+#define BIT_CLEAR_HCI_HCPWM2(x) ((x) & (~BITS_HCI_HCPWM2))
+#define BIT_GET_HCI_HCPWM2(x)                                                  \
+	(((x) >> BIT_SHIFT_HCI_HCPWM2) & BIT_MASK_HCI_HCPWM2)
+#define BIT_SET_HCI_HCPWM2(x, v) (BIT_CLEAR_HCI_HCPWM2(x) | BIT_HCI_HCPWM2(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_PCIE_H2C_MSG_V1			(Offset 0x03E0) */
+
+#define BIT_AC7Q_EMPTY BIT(7)
+#define BIT_AC6Q_EMPTY BIT(6)
+#define BIT_AC5Q_EMPTY BIT(5)
+#define BIT_AC4Q_EMPTY BIT(4)
+#define BIT_AC3Q_EMPTY BIT(3)
+#define BIT_AC2Q_EMPTY BIT(2)
+#define BIT_AC1Q_EMPTY BIT(1)
+
+#define BIT_SHIFT_DRV2FW_INFO 0
+#define BIT_MASK_DRV2FW_INFO 0xffffffffL
+#define BIT_DRV2FW_INFO(x)                                                     \
+	(((x) & BIT_MASK_DRV2FW_INFO) << BIT_SHIFT_DRV2FW_INFO)
+#define BITS_DRV2FW_INFO (BIT_MASK_DRV2FW_INFO << BIT_SHIFT_DRV2FW_INFO)
+#define BIT_CLEAR_DRV2FW_INFO(x) ((x) & (~BITS_DRV2FW_INFO))
+#define BIT_GET_DRV2FW_INFO(x)                                                 \
+	(((x) >> BIT_SHIFT_DRV2FW_INFO) & BIT_MASK_DRV2FW_INFO)
+#define BIT_SET_DRV2FW_INFO(x, v)                                              \
+	(BIT_CLEAR_DRV2FW_INFO(x) | BIT_DRV2FW_INFO(v))
+
+#define BIT_AC0Q_EMPTY BIT(0)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8881A_SUPPORT)
+
+/* 2 REG_PCIE_C2H_MSG_V1			(Offset 0x03E4) */
+
+#define BIT_SHIFT_HCI_PCIE_C2H_MSG 0
+#define BIT_MASK_HCI_PCIE_C2H_MSG 0xffffffffL
+#define BIT_HCI_PCIE_C2H_MSG(x)                                                \
+	(((x) & BIT_MASK_HCI_PCIE_C2H_MSG) << BIT_SHIFT_HCI_PCIE_C2H_MSG)
+#define BITS_HCI_PCIE_C2H_MSG                                                  \
+	(BIT_MASK_HCI_PCIE_C2H_MSG << BIT_SHIFT_HCI_PCIE_C2H_MSG)
+#define BIT_CLEAR_HCI_PCIE_C2H_MSG(x) ((x) & (~BITS_HCI_PCIE_C2H_MSG))
+#define BIT_GET_HCI_PCIE_C2H_MSG(x)                                            \
+	(((x) >> BIT_SHIFT_HCI_PCIE_C2H_MSG) & BIT_MASK_HCI_PCIE_C2H_MSG)
+#define BIT_SET_HCI_PCIE_C2H_MSG(x, v)                                         \
+	(BIT_CLEAR_HCI_PCIE_C2H_MSG(x) | BIT_HCI_PCIE_C2H_MSG(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_HCI_C2H_MSG_V1			(Offset 0x03E4) */
+
+#define BIT_SHIFT_HCI_C2H_MSG 0
+#define BIT_MASK_HCI_C2H_MSG 0xffffffffL
+#define BIT_HCI_C2H_MSG(x)                                                     \
+	(((x) & BIT_MASK_HCI_C2H_MSG) << BIT_SHIFT_HCI_C2H_MSG)
+#define BITS_HCI_C2H_MSG (BIT_MASK_HCI_C2H_MSG << BIT_SHIFT_HCI_C2H_MSG)
+#define BIT_CLEAR_HCI_C2H_MSG(x) ((x) & (~BITS_HCI_C2H_MSG))
+#define BIT_GET_HCI_C2H_MSG(x)                                                 \
+	(((x) >> BIT_SHIFT_HCI_C2H_MSG) & BIT_MASK_HCI_C2H_MSG)
+#define BIT_SET_HCI_C2H_MSG(x, v)                                              \
+	(BIT_CLEAR_HCI_C2H_MSG(x) | BIT_HCI_C2H_MSG(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_DBI_WDATA_V1			(Offset 0x03E8) */
+
+#define BIT_SHIFT_DBI_WDATA 0
+#define BIT_MASK_DBI_WDATA 0xffffffffL
+#define BIT_DBI_WDATA(x) (((x) & BIT_MASK_DBI_WDATA) << BIT_SHIFT_DBI_WDATA)
+#define BITS_DBI_WDATA (BIT_MASK_DBI_WDATA << BIT_SHIFT_DBI_WDATA)
+#define BIT_CLEAR_DBI_WDATA(x) ((x) & (~BITS_DBI_WDATA))
+#define BIT_GET_DBI_WDATA(x) (((x) >> BIT_SHIFT_DBI_WDATA) & BIT_MASK_DBI_WDATA)
+#define BIT_SET_DBI_WDATA(x, v) (BIT_CLEAR_DBI_WDATA(x) | BIT_DBI_WDATA(v))
+
+/* 2 REG_DBI_RDATA_V1			(Offset 0x03EC) */
+
+#define BIT_SHIFT_DBI_RDATA 0
+#define BIT_MASK_DBI_RDATA 0xffffffffL
+#define BIT_DBI_RDATA(x) (((x) & BIT_MASK_DBI_RDATA) << BIT_SHIFT_DBI_RDATA)
+#define BITS_DBI_RDATA (BIT_MASK_DBI_RDATA << BIT_SHIFT_DBI_RDATA)
+#define BIT_CLEAR_DBI_RDATA(x) ((x) & (~BITS_DBI_RDATA))
+#define BIT_GET_DBI_RDATA(x) (((x) >> BIT_SHIFT_DBI_RDATA) & BIT_MASK_DBI_RDATA)
+#define BIT_SET_DBI_RDATA(x, v) (BIT_CLEAR_DBI_RDATA(x) | BIT_DBI_RDATA(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_DBI_FLAG_V1				(Offset 0x03F0) */
+
+#define BIT_SHIFT_LOOPBACK_DBG_SEL 28
+#define BIT_MASK_LOOPBACK_DBG_SEL 0xf
+#define BIT_LOOPBACK_DBG_SEL(x)                                                \
+	(((x) & BIT_MASK_LOOPBACK_DBG_SEL) << BIT_SHIFT_LOOPBACK_DBG_SEL)
+#define BITS_LOOPBACK_DBG_SEL                                                  \
+	(BIT_MASK_LOOPBACK_DBG_SEL << BIT_SHIFT_LOOPBACK_DBG_SEL)
+#define BIT_CLEAR_LOOPBACK_DBG_SEL(x) ((x) & (~BITS_LOOPBACK_DBG_SEL))
+#define BIT_GET_LOOPBACK_DBG_SEL(x)                                            \
+	(((x) >> BIT_SHIFT_LOOPBACK_DBG_SEL) & BIT_MASK_LOOPBACK_DBG_SEL)
+#define BIT_SET_LOOPBACK_DBG_SEL(x, v)                                         \
+	(BIT_CLEAR_LOOPBACK_DBG_SEL(x) | BIT_LOOPBACK_DBG_SEL(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_DBI_FLAG_V1				(Offset 0x03F0) */
+
+#define BIT_EN_STUCK_DBG BIT(26)
+#define BIT_RX_STUCK BIT(25)
+#define BIT_TX_STUCK BIT(24)
+#define BIT_DBI_RFLAG BIT(17)
+#define BIT_DBI_WFLAG BIT(16)
+
+#define BIT_SHIFT_DBI_WREN 12
+#define BIT_MASK_DBI_WREN 0xf
+#define BIT_DBI_WREN(x) (((x) & BIT_MASK_DBI_WREN) << BIT_SHIFT_DBI_WREN)
+#define BITS_DBI_WREN (BIT_MASK_DBI_WREN << BIT_SHIFT_DBI_WREN)
+#define BIT_CLEAR_DBI_WREN(x) ((x) & (~BITS_DBI_WREN))
+#define BIT_GET_DBI_WREN(x) (((x) >> BIT_SHIFT_DBI_WREN) & BIT_MASK_DBI_WREN)
+#define BIT_SET_DBI_WREN(x, v) (BIT_CLEAR_DBI_WREN(x) | BIT_DBI_WREN(v))
+
+#define BIT_SHIFT_DBI_ADDR 0
+#define BIT_MASK_DBI_ADDR 0xfff
+#define BIT_DBI_ADDR(x) (((x) & BIT_MASK_DBI_ADDR) << BIT_SHIFT_DBI_ADDR)
+#define BITS_DBI_ADDR (BIT_MASK_DBI_ADDR << BIT_SHIFT_DBI_ADDR)
+#define BIT_CLEAR_DBI_ADDR(x) ((x) & (~BITS_DBI_ADDR))
+#define BIT_GET_DBI_ADDR(x) (((x) >> BIT_SHIFT_DBI_ADDR) & BIT_MASK_DBI_ADDR)
+#define BIT_SET_DBI_ADDR(x, v) (BIT_CLEAR_DBI_ADDR(x) | BIT_DBI_ADDR(v))
+
+/* 2 REG_MDIO_V1				(Offset 0x03F4) */
+
+#define BIT_SHIFT_MDIO_RDATA 16
+#define BIT_MASK_MDIO_RDATA 0xffff
+#define BIT_MDIO_RDATA(x) (((x) & BIT_MASK_MDIO_RDATA) << BIT_SHIFT_MDIO_RDATA)
+#define BITS_MDIO_RDATA (BIT_MASK_MDIO_RDATA << BIT_SHIFT_MDIO_RDATA)
+#define BIT_CLEAR_MDIO_RDATA(x) ((x) & (~BITS_MDIO_RDATA))
+#define BIT_GET_MDIO_RDATA(x)                                                  \
+	(((x) >> BIT_SHIFT_MDIO_RDATA) & BIT_MASK_MDIO_RDATA)
+#define BIT_SET_MDIO_RDATA(x, v) (BIT_CLEAR_MDIO_RDATA(x) | BIT_MDIO_RDATA(v))
+
+#define BIT_SHIFT_MDIO_WDATA 0
+#define BIT_MASK_MDIO_WDATA 0xffff
+#define BIT_MDIO_WDATA(x) (((x) & BIT_MASK_MDIO_WDATA) << BIT_SHIFT_MDIO_WDATA)
+#define BITS_MDIO_WDATA (BIT_MASK_MDIO_WDATA << BIT_SHIFT_MDIO_WDATA)
+#define BIT_CLEAR_MDIO_WDATA(x) ((x) & (~BITS_MDIO_WDATA))
+#define BIT_GET_MDIO_WDATA(x)                                                  \
+	(((x) >> BIT_SHIFT_MDIO_WDATA) & BIT_MASK_MDIO_WDATA)
+#define BIT_SET_MDIO_WDATA(x, v) (BIT_CLEAR_MDIO_WDATA(x) | BIT_MDIO_WDATA(v))
+
+#endif
+
+#if (HALMAC_8881A_SUPPORT)
+
+/* 2 REG_BUS_MIX_CFG				(Offset 0x03F8) */
+
+#define BIT_SHIFT_DELAY_TIME 24
+#define BIT_MASK_DELAY_TIME 0xff
+#define BIT_DELAY_TIME(x) (((x) & BIT_MASK_DELAY_TIME) << BIT_SHIFT_DELAY_TIME)
+#define BITS_DELAY_TIME (BIT_MASK_DELAY_TIME << BIT_SHIFT_DELAY_TIME)
+#define BIT_CLEAR_DELAY_TIME(x) ((x) & (~BITS_DELAY_TIME))
+#define BIT_GET_DELAY_TIME(x)                                                  \
+	(((x) >> BIT_SHIFT_DELAY_TIME) & BIT_MASK_DELAY_TIME)
+#define BIT_SET_DELAY_TIME(x, v) (BIT_CLEAR_DELAY_TIME(x) | BIT_DELAY_TIME(v))
+
+#define BIT_RX_TIMER_DELAY_EN BIT(17)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_PCIE_MIX_CFG			(Offset 0x03F8) */
+
+#define BIT_EN_WATCH_DOG BIT(8)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8814B_SUPPORT)
+
+/* 2 REG_MDIO2_V1				(Offset 0x03F8) */
+
+#define BIT_ECRC_EN BIT(7)
+#define BIT_MDIO_RFLAG BIT(6)
+#define BIT_MDIO_WFLAG BIT(5)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT)
+
+/* 2 REG_MDIO2_V1				(Offset 0x03F8) */
+
+#define BIT_SHIFT_MDIO_ADDR 0
+#define BIT_MASK_MDIO_ADDR 0x1f
+#define BIT_MDIO_ADDR(x) (((x) & BIT_MASK_MDIO_ADDR) << BIT_SHIFT_MDIO_ADDR)
+#define BITS_MDIO_ADDR (BIT_MASK_MDIO_ADDR << BIT_SHIFT_MDIO_ADDR)
+#define BIT_CLEAR_MDIO_ADDR(x) ((x) & (~BITS_MDIO_ADDR))
+#define BIT_GET_MDIO_ADDR(x) (((x) >> BIT_SHIFT_MDIO_ADDR) & BIT_MASK_MDIO_ADDR)
+#define BIT_SET_MDIO_ADDR(x, v) (BIT_CLEAR_MDIO_ADDR(x) | BIT_MDIO_ADDR(v))
+
+#define BIT_SHIFT_TXFAIL_DROPCNT 0
+#define BIT_MASK_TXFAIL_DROPCNT 0xffff
+#define BIT_TXFAIL_DROPCNT(x)                                                  \
+	(((x) & BIT_MASK_TXFAIL_DROPCNT) << BIT_SHIFT_TXFAIL_DROPCNT)
+#define BITS_TXFAIL_DROPCNT                                                    \
+	(BIT_MASK_TXFAIL_DROPCNT << BIT_SHIFT_TXFAIL_DROPCNT)
+#define BIT_CLEAR_TXFAIL_DROPCNT(x) ((x) & (~BITS_TXFAIL_DROPCNT))
+#define BIT_GET_TXFAIL_DROPCNT(x)                                              \
+	(((x) >> BIT_SHIFT_TXFAIL_DROPCNT) & BIT_MASK_TXFAIL_DROPCNT)
+#define BIT_SET_TXFAIL_DROPCNT(x, v)                                           \
+	(BIT_CLEAR_TXFAIL_DROPCNT(x) | BIT_TXFAIL_DROPCNT(v))
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_PCIE_MIX_CFG			(Offset 0x03F8) */
+
+#define BIT_SHIFT_MDIO_REG_ADDR_V1 0
+#define BIT_MASK_MDIO_REG_ADDR_V1 0x1f
+#define BIT_MDIO_REG_ADDR_V1(x)                                                \
+	(((x) & BIT_MASK_MDIO_REG_ADDR_V1) << BIT_SHIFT_MDIO_REG_ADDR_V1)
+#define BITS_MDIO_REG_ADDR_V1                                                  \
+	(BIT_MASK_MDIO_REG_ADDR_V1 << BIT_SHIFT_MDIO_REG_ADDR_V1)
+#define BIT_CLEAR_MDIO_REG_ADDR_V1(x) ((x) & (~BITS_MDIO_REG_ADDR_V1))
+#define BIT_GET_MDIO_REG_ADDR_V1(x)                                            \
+	(((x) >> BIT_SHIFT_MDIO_REG_ADDR_V1) & BIT_MASK_MDIO_REG_ADDR_V1)
+#define BIT_SET_MDIO_REG_ADDR_V1(x, v)                                         \
+	(BIT_CLEAR_MDIO_REG_ADDR_V1(x) | BIT_MDIO_REG_ADDR_V1(v))
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_HCI_MIX_CFG				(Offset 0x03FC) */
+
+#define BIT_RXRST_BACKDOOR BIT(31)
+#define BIT_TXRST_BACKDOOR BIT(30)
+#define BIT_RXIDX_RSTB BIT(29)
+#define BIT_TXIDX_RSTB BIT(28)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_HCI_MIX_CFG				(Offset 0x03FC) */
+
+#define BIT_SHIFT_WATCH_DOG_TIMER 28
+#define BIT_MASK_WATCH_DOG_TIMER 0xf
+#define BIT_WATCH_DOG_TIMER(x)                                                 \
+	(((x) & BIT_MASK_WATCH_DOG_TIMER) << BIT_SHIFT_WATCH_DOG_TIMER)
+#define BITS_WATCH_DOG_TIMER                                                   \
+	(BIT_MASK_WATCH_DOG_TIMER << BIT_SHIFT_WATCH_DOG_TIMER)
+#define BIT_CLEAR_WATCH_DOG_TIMER(x) ((x) & (~BITS_WATCH_DOG_TIMER))
+#define BIT_GET_WATCH_DOG_TIMER(x)                                             \
+	(((x) >> BIT_SHIFT_WATCH_DOG_TIMER) & BIT_MASK_WATCH_DOG_TIMER)
+#define BIT_SET_WATCH_DOG_TIMER(x, v)                                          \
+	(BIT_CLEAR_WATCH_DOG_TIMER(x) | BIT_WATCH_DOG_TIMER(v))
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_HCI_MIX_CFG				(Offset 0x03FC) */
+
+#define BIT_DROP_NEXT_RXPKT BIT(27)
+#define BIT_SHORT_CORE_RST_SEL BIT(26)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_HCI_MIX_CFG				(Offset 0x03FC) */
+
+#define BIT_EXCEPT_RESUME_EN BIT(25)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_HCI_MIX_CFG				(Offset 0x03FC) */
+
+#define BIT_EXCEPT_FLAG BIT(24)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_HCI_MIX_CFG				(Offset 0x03FC) */
+
+#define BIT_EXCEPT_RESUME_FLAG BIT(24)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_HCI_MIX_CFG				(Offset 0x03FC) */
+
+#define BIT_ALIGN_MTU BIT(23)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_HCI_MIX_CFG				(Offset 0x03FC) */
+
+#define BIT_EN_ALIGN_MTU BIT(23)
+
+#endif
+
+#if (HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_HCI_MIX_CFG				(Offset 0x03FC) */
+
+#define BIT_EARLY_TAG_RETURN BIT(22)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_HCI_MIX_CFG				(Offset 0x03FC) */
+
+#define BIT_SHIFT_LATENCY_CONTROL 21
+#define BIT_MASK_LATENCY_CONTROL 0x3
+#define BIT_LATENCY_CONTROL(x)                                                 \
+	(((x) & BIT_MASK_LATENCY_CONTROL) << BIT_SHIFT_LATENCY_CONTROL)
+#define BITS_LATENCY_CONTROL                                                   \
+	(BIT_MASK_LATENCY_CONTROL << BIT_SHIFT_LATENCY_CONTROL)
+#define BIT_CLEAR_LATENCY_CONTROL(x) ((x) & (~BITS_LATENCY_CONTROL))
+#define BIT_GET_LATENCY_CONTROL(x)                                             \
+	(((x) >> BIT_SHIFT_LATENCY_CONTROL) & BIT_MASK_LATENCY_CONTROL)
+#define BIT_SET_LATENCY_CONTROL(x, v)                                          \
+	(BIT_CLEAR_LATENCY_CONTROL(x) | BIT_LATENCY_CONTROL(v))
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_HCI_MIX_CFG				(Offset 0x03FC) */
+
+#define BIT_HOST_GEN2_SUPPORT BIT(20)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT)
+
+/* 2 REG_HCI_MIX_CFG				(Offset 0x03FC) */
+
+#define BIT_SHIFT_TXDMA_ERR_FLAG 16
+#define BIT_MASK_TXDMA_ERR_FLAG 0xf
+#define BIT_TXDMA_ERR_FLAG(x)                                                  \
+	(((x) & BIT_MASK_TXDMA_ERR_FLAG) << BIT_SHIFT_TXDMA_ERR_FLAG)
+#define BITS_TXDMA_ERR_FLAG                                                    \
+	(BIT_MASK_TXDMA_ERR_FLAG << BIT_SHIFT_TXDMA_ERR_FLAG)
+#define BIT_CLEAR_TXDMA_ERR_FLAG(x) ((x) & (~BITS_TXDMA_ERR_FLAG))
+#define BIT_GET_TXDMA_ERR_FLAG(x)                                              \
+	(((x) >> BIT_SHIFT_TXDMA_ERR_FLAG) & BIT_MASK_TXDMA_ERR_FLAG)
+#define BIT_SET_TXDMA_ERR_FLAG(x, v)                                           \
+	(BIT_CLEAR_TXDMA_ERR_FLAG(x) | BIT_TXDMA_ERR_FLAG(v))
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_HCI_MIX_CFG				(Offset 0x03FC) */
+
+#define BIT_SHIFT_TXDMA_ERR_FLAG_V1 15
+#define BIT_MASK_TXDMA_ERR_FLAG_V1 0x1f
+#define BIT_TXDMA_ERR_FLAG_V1(x)                                               \
+	(((x) & BIT_MASK_TXDMA_ERR_FLAG_V1) << BIT_SHIFT_TXDMA_ERR_FLAG_V1)
+#define BITS_TXDMA_ERR_FLAG_V1                                                 \
+	(BIT_MASK_TXDMA_ERR_FLAG_V1 << BIT_SHIFT_TXDMA_ERR_FLAG_V1)
+#define BIT_CLEAR_TXDMA_ERR_FLAG_V1(x) ((x) & (~BITS_TXDMA_ERR_FLAG_V1))
+#define BIT_GET_TXDMA_ERR_FLAG_V1(x)                                           \
+	(((x) >> BIT_SHIFT_TXDMA_ERR_FLAG_V1) & BIT_MASK_TXDMA_ERR_FLAG_V1)
+#define BIT_SET_TXDMA_ERR_FLAG_V1(x, v)                                        \
+	(BIT_CLEAR_TXDMA_ERR_FLAG_V1(x) | BIT_TXDMA_ERR_FLAG_V1(v))
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT)
+
+/* 2 REG_HCI_MIX_CFG				(Offset 0x03FC) */
+
+#define BIT_SHIFT_EARLY_MODE_SEL 12
+#define BIT_MASK_EARLY_MODE_SEL 0xf
+#define BIT_EARLY_MODE_SEL(x)                                                  \
+	(((x) & BIT_MASK_EARLY_MODE_SEL) << BIT_SHIFT_EARLY_MODE_SEL)
+#define BITS_EARLY_MODE_SEL                                                    \
+	(BIT_MASK_EARLY_MODE_SEL << BIT_SHIFT_EARLY_MODE_SEL)
+#define BIT_CLEAR_EARLY_MODE_SEL(x) ((x) & (~BITS_EARLY_MODE_SEL))
+#define BIT_GET_EARLY_MODE_SEL(x)                                              \
+	(((x) >> BIT_SHIFT_EARLY_MODE_SEL) & BIT_MASK_EARLY_MODE_SEL)
+#define BIT_SET_EARLY_MODE_SEL(x, v)                                           \
+	(BIT_CLEAR_EARLY_MODE_SEL(x) | BIT_EARLY_MODE_SEL(v))
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_HCI_MIX_CFG				(Offset 0x03FC) */
+
+#define BIT_EPHY_RX50_EN BIT(11)
+
+#define BIT_SHIFT_MSI_TIMEOUT_ID_V1 8
+#define BIT_MASK_MSI_TIMEOUT_ID_V1 0x7
+#define BIT_MSI_TIMEOUT_ID_V1(x)                                               \
+	(((x) & BIT_MASK_MSI_TIMEOUT_ID_V1) << BIT_SHIFT_MSI_TIMEOUT_ID_V1)
+#define BITS_MSI_TIMEOUT_ID_V1                                                 \
+	(BIT_MASK_MSI_TIMEOUT_ID_V1 << BIT_SHIFT_MSI_TIMEOUT_ID_V1)
+#define BIT_CLEAR_MSI_TIMEOUT_ID_V1(x) ((x) & (~BITS_MSI_TIMEOUT_ID_V1))
+#define BIT_GET_MSI_TIMEOUT_ID_V1(x)                                           \
+	(((x) >> BIT_SHIFT_MSI_TIMEOUT_ID_V1) & BIT_MASK_MSI_TIMEOUT_ID_V1)
+#define BIT_SET_MSI_TIMEOUT_ID_V1(x, v)                                        \
+	(BIT_CLEAR_MSI_TIMEOUT_ID_V1(x) | BIT_MSI_TIMEOUT_ID_V1(v))
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_HCI_MIX_CFG				(Offset 0x03FC) */
+
+#define BIT_SHIFT_RXDMA_ERR_CNT 8
+#define BIT_MASK_RXDMA_ERR_CNT 0xff
+#define BIT_RXDMA_ERR_CNT(x)                                                   \
+	(((x) & BIT_MASK_RXDMA_ERR_CNT) << BIT_SHIFT_RXDMA_ERR_CNT)
+#define BITS_RXDMA_ERR_CNT (BIT_MASK_RXDMA_ERR_CNT << BIT_SHIFT_RXDMA_ERR_CNT)
+#define BIT_CLEAR_RXDMA_ERR_CNT(x) ((x) & (~BITS_RXDMA_ERR_CNT))
+#define BIT_GET_RXDMA_ERR_CNT(x)                                               \
+	(((x) >> BIT_SHIFT_RXDMA_ERR_CNT) & BIT_MASK_RXDMA_ERR_CNT)
+#define BIT_SET_RXDMA_ERR_CNT(x, v)                                            \
+	(BIT_CLEAR_RXDMA_ERR_CNT(x) | BIT_RXDMA_ERR_CNT(v))
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_HCI_MIX_CFG				(Offset 0x03FC) */
+
+#define BIT_RADDR_RD BIT(7)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_HCI_MIX_CFG				(Offset 0x03FC) */
+
+#define BIT_TXDMA_ERR_HANDLE_REQ BIT(7)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT)
+
+/* 2 REG_HCI_MIX_CFG				(Offset 0x03FC) */
+
+#define BIT_EN_MUL_TAG BIT(6)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_HCI_MIX_CFG				(Offset 0x03FC) */
+
+#define BIT_TXDMA_ERROR_PS BIT(6)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_HCI_MIX_CFG				(Offset 0x03FC) */
+
+#define BIT_L1OFF_PWR_OFF_EN BIT(6)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT)
+
+/* 2 REG_HCI_MIX_CFG				(Offset 0x03FC) */
+
+#define BIT_EN_EARLY_MODE BIT(5)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_HCI_MIX_CFG				(Offset 0x03FC) */
+
+#define BIT_EN_TXDMA_STUCK_ERR_HANDLE BIT(5)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_HCI_MIX_CFG				(Offset 0x03FC) */
+
+#define BIT_L0S_LINK_OFF BIT(4)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_HCI_MIX_CFG				(Offset 0x03FC) */
+
+#define BIT_EN_TXDMA_RTN_ERR_HANDLE BIT(4)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_HCI_MIX_CFG				(Offset 0x03FC) */
+
+#define BIT_ACT_LINK_OFF BIT(3)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_HCI_MIX_CFG				(Offset 0x03FC) */
+
+#define BIT_RXDMA_ERR_HANDLE_REQ BIT(3)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_HCI_MIX_CFG				(Offset 0x03FC) */
+
+#define BIT_EN_SLOW_MAC_TX BIT(2)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_HCI_MIX_CFG				(Offset 0x03FC) */
+
+#define BIT_RXDMA_ERROR_PS BIT(2)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_HCI_MIX_CFG				(Offset 0x03FC) */
+
+#define BIT_EN_SLOW_MAC_RX BIT(1)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_HCI_MIX_CFG				(Offset 0x03FC) */
+
+#define BIT_EN_RXDMA_STUCK_ERR_HANDLE BIT(1)
+#define BIT_EN_SLOW_MAC_HW BIT(0)
+#define BIT_EN_RXDMA_RTN_ERR_HANDLE BIT(0)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_Q0_INFO				(Offset 0x0400) */
+
+#define BIT_SHIFT_QUEUEMACID_Q0_V1 25
+#define BIT_MASK_QUEUEMACID_Q0_V1 0x7f
+#define BIT_QUEUEMACID_Q0_V1(x)                                                \
+	(((x) & BIT_MASK_QUEUEMACID_Q0_V1) << BIT_SHIFT_QUEUEMACID_Q0_V1)
+#define BITS_QUEUEMACID_Q0_V1                                                  \
+	(BIT_MASK_QUEUEMACID_Q0_V1 << BIT_SHIFT_QUEUEMACID_Q0_V1)
+#define BIT_CLEAR_QUEUEMACID_Q0_V1(x) ((x) & (~BITS_QUEUEMACID_Q0_V1))
+#define BIT_GET_QUEUEMACID_Q0_V1(x)                                            \
+	(((x) >> BIT_SHIFT_QUEUEMACID_Q0_V1) & BIT_MASK_QUEUEMACID_Q0_V1)
+#define BIT_SET_QUEUEMACID_Q0_V1(x, v)                                         \
+	(BIT_CLEAR_QUEUEMACID_Q0_V1(x) | BIT_QUEUEMACID_Q0_V1(v))
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+/* 2 REG_QUEUE_INFO1				(Offset 0x0400) */
+
+#define BIT_SHIFT_QUEUEMACID 25
+#define BIT_MASK_QUEUEMACID 0x7f
+#define BIT_QUEUEMACID(x) (((x) & BIT_MASK_QUEUEMACID) << BIT_SHIFT_QUEUEMACID)
+#define BITS_QUEUEMACID (BIT_MASK_QUEUEMACID << BIT_SHIFT_QUEUEMACID)
+#define BIT_CLEAR_QUEUEMACID(x) ((x) & (~BITS_QUEUEMACID))
+#define BIT_GET_QUEUEMACID(x)                                                  \
+	(((x) >> BIT_SHIFT_QUEUEMACID) & BIT_MASK_QUEUEMACID)
+#define BIT_SET_QUEUEMACID(x, v) (BIT_CLEAR_QUEUEMACID(x) | BIT_QUEUEMACID(v))
+
+#define BIT_DONE BIT(24)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_Q0_INFO				(Offset 0x0400) */
+
+#define BIT_SHIFT_QUEUEAC_Q0_V1 23
+#define BIT_MASK_QUEUEAC_Q0_V1 0x3
+#define BIT_QUEUEAC_Q0_V1(x)                                                   \
+	(((x) & BIT_MASK_QUEUEAC_Q0_V1) << BIT_SHIFT_QUEUEAC_Q0_V1)
+#define BITS_QUEUEAC_Q0_V1 (BIT_MASK_QUEUEAC_Q0_V1 << BIT_SHIFT_QUEUEAC_Q0_V1)
+#define BIT_CLEAR_QUEUEAC_Q0_V1(x) ((x) & (~BITS_QUEUEAC_Q0_V1))
+#define BIT_GET_QUEUEAC_Q0_V1(x)                                               \
+	(((x) >> BIT_SHIFT_QUEUEAC_Q0_V1) & BIT_MASK_QUEUEAC_Q0_V1)
+#define BIT_SET_QUEUEAC_Q0_V1(x, v)                                            \
+	(BIT_CLEAR_QUEUEAC_Q0_V1(x) | BIT_QUEUEAC_Q0_V1(v))
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+/* 2 REG_QUEUE_INFO1				(Offset 0x0400) */
+
+#define BIT_SHIFT_QUEUEAC 23
+#define BIT_MASK_QUEUEAC 0x3
+#define BIT_QUEUEAC(x) (((x) & BIT_MASK_QUEUEAC) << BIT_SHIFT_QUEUEAC)
+#define BITS_QUEUEAC (BIT_MASK_QUEUEAC << BIT_SHIFT_QUEUEAC)
+#define BIT_CLEAR_QUEUEAC(x) ((x) & (~BITS_QUEUEAC))
+#define BIT_GET_QUEUEAC(x) (((x) >> BIT_SHIFT_QUEUEAC) & BIT_MASK_QUEUEAC)
+#define BIT_SET_QUEUEAC(x, v) (BIT_CLEAR_QUEUEAC(x) | BIT_QUEUEAC(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_Q0_INFO				(Offset 0x0400) */
+
+#define BIT_TIDEMPTY_Q0_V1 BIT(22)
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+/* 2 REG_QUEUE_INFO1				(Offset 0x0400) */
+
+#define BIT_TIDEMPTY BIT(22)
+
+#define BIT_SHIFT_ACCWBITEN 20
+#define BIT_MASK_ACCWBITEN 0xf
+#define BIT_ACCWBITEN(x) (((x) & BIT_MASK_ACCWBITEN) << BIT_SHIFT_ACCWBITEN)
+#define BITS_ACCWBITEN (BIT_MASK_ACCWBITEN << BIT_SHIFT_ACCWBITEN)
+#define BIT_CLEAR_ACCWBITEN(x) ((x) & (~BITS_ACCWBITEN))
+#define BIT_GET_ACCWBITEN(x) (((x) >> BIT_SHIFT_ACCWBITEN) & BIT_MASK_ACCWBITEN)
+#define BIT_SET_ACCWBITEN(x, v) (BIT_CLEAR_ACCWBITEN(x) | BIT_ACCWBITEN(v))
+
+#define BIT_BCNQ_EMPTY_V1 BIT(19)
+#define BIT_HIQ_EMPTY_V1 BIT(18)
+#define BIT_MQQ_EMPTY_V1 BIT(17)
+
+#define BIT_SHIFT_COL_CNT 16
+#define BIT_MASK_COL_CNT 0xf
+#define BIT_COL_CNT(x) (((x) & BIT_MASK_COL_CNT) << BIT_SHIFT_COL_CNT)
+#define BITS_COL_CNT (BIT_MASK_COL_CNT << BIT_SHIFT_COL_CNT)
+#define BIT_CLEAR_COL_CNT(x) ((x) & (~BITS_COL_CNT))
+#define BIT_GET_COL_CNT(x) (((x) >> BIT_SHIFT_COL_CNT) & BIT_MASK_COL_CNT)
+#define BIT_SET_COL_CNT(x, v) (BIT_CLEAR_COL_CNT(x) | BIT_COL_CNT(v))
+
+#define BIT_CPU_MGT_EMPTY BIT(16)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_Q0_INFO				(Offset 0x0400) */
+
+#define BIT_SHIFT_TAIL_PKT_Q0_V1 15
+#define BIT_MASK_TAIL_PKT_Q0_V1 0xff
+#define BIT_TAIL_PKT_Q0_V1(x)                                                  \
+	(((x) & BIT_MASK_TAIL_PKT_Q0_V1) << BIT_SHIFT_TAIL_PKT_Q0_V1)
+#define BITS_TAIL_PKT_Q0_V1                                                    \
+	(BIT_MASK_TAIL_PKT_Q0_V1 << BIT_SHIFT_TAIL_PKT_Q0_V1)
+#define BIT_CLEAR_TAIL_PKT_Q0_V1(x) ((x) & (~BITS_TAIL_PKT_Q0_V1))
+#define BIT_GET_TAIL_PKT_Q0_V1(x)                                              \
+	(((x) >> BIT_SHIFT_TAIL_PKT_Q0_V1) & BIT_MASK_TAIL_PKT_Q0_V1)
+#define BIT_SET_TAIL_PKT_Q0_V1(x, v)                                           \
+	(BIT_CLEAR_TAIL_PKT_Q0_V1(x) | BIT_TAIL_PKT_Q0_V1(v))
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+/* 2 REG_QUEUE_INFO1				(Offset 0x0400) */
+
+#define BIT_AC_MACID_NOT_SAME BIT(15)
+
+#define BIT_SHIFT_GROUP_TABLE_ID 12
+#define BIT_MASK_GROUP_TABLE_ID 0x7
+#define BIT_GROUP_TABLE_ID(x)                                                  \
+	(((x) & BIT_MASK_GROUP_TABLE_ID) << BIT_SHIFT_GROUP_TABLE_ID)
+#define BITS_GROUP_TABLE_ID                                                    \
+	(BIT_MASK_GROUP_TABLE_ID << BIT_SHIFT_GROUP_TABLE_ID)
+#define BIT_CLEAR_GROUP_TABLE_ID(x) ((x) & (~BITS_GROUP_TABLE_ID))
+#define BIT_GET_GROUP_TABLE_ID(x)                                              \
+	(((x) >> BIT_SHIFT_GROUP_TABLE_ID) & BIT_MASK_GROUP_TABLE_ID)
+#define BIT_SET_GROUP_TABLE_ID(x, v)                                           \
+	(BIT_CLEAR_GROUP_TABLE_ID(x) | BIT_GROUP_TABLE_ID(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_Q0_INFO				(Offset 0x0400) */
+
+#define BIT_SHIFT_TAIL_PKT_Q0_V2 11
+#define BIT_MASK_TAIL_PKT_Q0_V2 0x7ff
+#define BIT_TAIL_PKT_Q0_V2(x)                                                  \
+	(((x) & BIT_MASK_TAIL_PKT_Q0_V2) << BIT_SHIFT_TAIL_PKT_Q0_V2)
+#define BITS_TAIL_PKT_Q0_V2                                                    \
+	(BIT_MASK_TAIL_PKT_Q0_V2 << BIT_SHIFT_TAIL_PKT_Q0_V2)
+#define BIT_CLEAR_TAIL_PKT_Q0_V2(x) ((x) & (~BITS_TAIL_PKT_Q0_V2))
+#define BIT_GET_TAIL_PKT_Q0_V2(x)                                              \
+	(((x) >> BIT_SHIFT_TAIL_PKT_Q0_V2) & BIT_MASK_TAIL_PKT_Q0_V2)
+#define BIT_SET_TAIL_PKT_Q0_V2(x, v)                                           \
+	(BIT_CLEAR_TAIL_PKT_Q0_V2(x) | BIT_TAIL_PKT_Q0_V2(v))
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+/* 2 REG_QUEUE_INFO1				(Offset 0x0400) */
+
+#define BIT_SHIFT_TAIL_PKT 11
+#define BIT_MASK_TAIL_PKT 0x7ff
+#define BIT_TAIL_PKT(x) (((x) & BIT_MASK_TAIL_PKT) << BIT_SHIFT_TAIL_PKT)
+#define BITS_TAIL_PKT (BIT_MASK_TAIL_PKT << BIT_SHIFT_TAIL_PKT)
+#define BIT_CLEAR_TAIL_PKT(x) ((x) & (~BITS_TAIL_PKT))
+#define BIT_GET_TAIL_PKT(x) (((x) >> BIT_SHIFT_TAIL_PKT) & BIT_MASK_TAIL_PKT)
+#define BIT_SET_TAIL_PKT(x, v) (BIT_CLEAR_TAIL_PKT(x) | BIT_TAIL_PKT(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_Q0_INFO				(Offset 0x0400) */
+
+#define BIT_SHIFT_PKT_NUM_Q0_V1 8
+#define BIT_MASK_PKT_NUM_Q0_V1 0x7f
+#define BIT_PKT_NUM_Q0_V1(x)                                                   \
+	(((x) & BIT_MASK_PKT_NUM_Q0_V1) << BIT_SHIFT_PKT_NUM_Q0_V1)
+#define BITS_PKT_NUM_Q0_V1 (BIT_MASK_PKT_NUM_Q0_V1 << BIT_SHIFT_PKT_NUM_Q0_V1)
+#define BIT_CLEAR_PKT_NUM_Q0_V1(x) ((x) & (~BITS_PKT_NUM_Q0_V1))
+#define BIT_GET_PKT_NUM_Q0_V1(x)                                               \
+	(((x) >> BIT_SHIFT_PKT_NUM_Q0_V1) & BIT_MASK_PKT_NUM_Q0_V1)
+#define BIT_SET_PKT_NUM_Q0_V1(x, v)                                            \
+	(BIT_CLEAR_PKT_NUM_Q0_V1(x) | BIT_PKT_NUM_Q0_V1(v))
+
+#define BIT_SHIFT_HEAD_PKT_Q0 0
+#define BIT_MASK_HEAD_PKT_Q0 0xff
+#define BIT_HEAD_PKT_Q0(x)                                                     \
+	(((x) & BIT_MASK_HEAD_PKT_Q0) << BIT_SHIFT_HEAD_PKT_Q0)
+#define BITS_HEAD_PKT_Q0 (BIT_MASK_HEAD_PKT_Q0 << BIT_SHIFT_HEAD_PKT_Q0)
+#define BIT_CLEAR_HEAD_PKT_Q0(x) ((x) & (~BITS_HEAD_PKT_Q0))
+#define BIT_GET_HEAD_PKT_Q0(x)                                                 \
+	(((x) >> BIT_SHIFT_HEAD_PKT_Q0) & BIT_MASK_HEAD_PKT_Q0)
+#define BIT_SET_HEAD_PKT_Q0(x, v)                                              \
+	(BIT_CLEAR_HEAD_PKT_Q0(x) | BIT_HEAD_PKT_Q0(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_Q0_INFO				(Offset 0x0400) */
+
+#define BIT_SHIFT_HEAD_PKT_Q0_V1 0
+#define BIT_MASK_HEAD_PKT_Q0_V1 0x7ff
+#define BIT_HEAD_PKT_Q0_V1(x)                                                  \
+	(((x) & BIT_MASK_HEAD_PKT_Q0_V1) << BIT_SHIFT_HEAD_PKT_Q0_V1)
+#define BITS_HEAD_PKT_Q0_V1                                                    \
+	(BIT_MASK_HEAD_PKT_Q0_V1 << BIT_SHIFT_HEAD_PKT_Q0_V1)
+#define BIT_CLEAR_HEAD_PKT_Q0_V1(x) ((x) & (~BITS_HEAD_PKT_Q0_V1))
+#define BIT_GET_HEAD_PKT_Q0_V1(x)                                              \
+	(((x) >> BIT_SHIFT_HEAD_PKT_Q0_V1) & BIT_MASK_HEAD_PKT_Q0_V1)
+#define BIT_SET_HEAD_PKT_Q0_V1(x, v)                                           \
+	(BIT_CLEAR_HEAD_PKT_Q0_V1(x) | BIT_HEAD_PKT_Q0_V1(v))
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+/* 2 REG_QUEUE_INFO1				(Offset 0x0400) */
+
+#define BIT_SHIFT_HEAD_PKT 0
+#define BIT_MASK_HEAD_PKT 0x7ff
+#define BIT_HEAD_PKT(x) (((x) & BIT_MASK_HEAD_PKT) << BIT_SHIFT_HEAD_PKT)
+#define BITS_HEAD_PKT (BIT_MASK_HEAD_PKT << BIT_SHIFT_HEAD_PKT)
+#define BIT_CLEAR_HEAD_PKT(x) ((x) & (~BITS_HEAD_PKT))
+#define BIT_GET_HEAD_PKT(x) (((x) >> BIT_SHIFT_HEAD_PKT) & BIT_MASK_HEAD_PKT)
+#define BIT_SET_HEAD_PKT(x, v) (BIT_CLEAR_HEAD_PKT(x) | BIT_HEAD_PKT(v))
+
+#define BIT_SHIFT_PKT_NUMBER 0
+#define BIT_MASK_PKT_NUMBER 0xfff
+#define BIT_PKT_NUMBER(x) (((x) & BIT_MASK_PKT_NUMBER) << BIT_SHIFT_PKT_NUMBER)
+#define BITS_PKT_NUMBER (BIT_MASK_PKT_NUMBER << BIT_SHIFT_PKT_NUMBER)
+#define BIT_CLEAR_PKT_NUMBER(x) ((x) & (~BITS_PKT_NUMBER))
+#define BIT_GET_PKT_NUMBER(x)                                                  \
+	(((x) >> BIT_SHIFT_PKT_NUMBER) & BIT_MASK_PKT_NUMBER)
+#define BIT_SET_PKT_NUMBER(x, v) (BIT_CLEAR_PKT_NUMBER(x) | BIT_PKT_NUMBER(v))
+
+#define BIT_SHIFT_ACCW 0
+#define BIT_MASK_ACCW 0x3ff
+#define BIT_ACCW(x) (((x) & BIT_MASK_ACCW) << BIT_SHIFT_ACCW)
+#define BITS_ACCW (BIT_MASK_ACCW << BIT_SHIFT_ACCW)
+#define BIT_CLEAR_ACCW(x) ((x) & (~BITS_ACCW))
+#define BIT_GET_ACCW(x) (((x) >> BIT_SHIFT_ACCW) & BIT_MASK_ACCW)
+#define BIT_SET_ACCW(x, v) (BIT_CLEAR_ACCW(x) | BIT_ACCW(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_QUEUELIST_INFO0			(Offset 0x0400) */
+
+#define BIT_SHIFT_QINFO0 0
+#define BIT_MASK_QINFO0 0xffffffffL
+#define BIT_QINFO0(x) (((x) & BIT_MASK_QINFO0) << BIT_SHIFT_QINFO0)
+#define BITS_QINFO0 (BIT_MASK_QINFO0 << BIT_SHIFT_QINFO0)
+#define BIT_CLEAR_QINFO0(x) ((x) & (~BITS_QINFO0))
+#define BIT_GET_QINFO0(x) (((x) >> BIT_SHIFT_QINFO0) & BIT_MASK_QINFO0)
+#define BIT_SET_QINFO0(x, v) (BIT_CLEAR_QINFO0(x) | BIT_QINFO0(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_Q1_INFO				(Offset 0x0404) */
+
+#define BIT_SHIFT_QUEUEMACID_Q1_V1 25
+#define BIT_MASK_QUEUEMACID_Q1_V1 0x7f
+#define BIT_QUEUEMACID_Q1_V1(x)                                                \
+	(((x) & BIT_MASK_QUEUEMACID_Q1_V1) << BIT_SHIFT_QUEUEMACID_Q1_V1)
+#define BITS_QUEUEMACID_Q1_V1                                                  \
+	(BIT_MASK_QUEUEMACID_Q1_V1 << BIT_SHIFT_QUEUEMACID_Q1_V1)
+#define BIT_CLEAR_QUEUEMACID_Q1_V1(x) ((x) & (~BITS_QUEUEMACID_Q1_V1))
+#define BIT_GET_QUEUEMACID_Q1_V1(x)                                            \
+	(((x) >> BIT_SHIFT_QUEUEMACID_Q1_V1) & BIT_MASK_QUEUEMACID_Q1_V1)
+#define BIT_SET_QUEUEMACID_Q1_V1(x, v)                                         \
+	(BIT_CLEAR_QUEUEMACID_Q1_V1(x) | BIT_QUEUEMACID_Q1_V1(v))
+
+#define BIT_SHIFT_QUEUEAC_Q1_V1 23
+#define BIT_MASK_QUEUEAC_Q1_V1 0x3
+#define BIT_QUEUEAC_Q1_V1(x)                                                   \
+	(((x) & BIT_MASK_QUEUEAC_Q1_V1) << BIT_SHIFT_QUEUEAC_Q1_V1)
+#define BITS_QUEUEAC_Q1_V1 (BIT_MASK_QUEUEAC_Q1_V1 << BIT_SHIFT_QUEUEAC_Q1_V1)
+#define BIT_CLEAR_QUEUEAC_Q1_V1(x) ((x) & (~BITS_QUEUEAC_Q1_V1))
+#define BIT_GET_QUEUEAC_Q1_V1(x)                                               \
+	(((x) >> BIT_SHIFT_QUEUEAC_Q1_V1) & BIT_MASK_QUEUEAC_Q1_V1)
+#define BIT_SET_QUEUEAC_Q1_V1(x, v)                                            \
+	(BIT_CLEAR_QUEUEAC_Q1_V1(x) | BIT_QUEUEAC_Q1_V1(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_Q1_INFO				(Offset 0x0404) */
+
+#define BIT_TIDEMPTY_Q1_V1 BIT(22)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_Q1_INFO				(Offset 0x0404) */
+
+#define BIT_SHIFT_TAIL_PKT_Q1_V1 15
+#define BIT_MASK_TAIL_PKT_Q1_V1 0xff
+#define BIT_TAIL_PKT_Q1_V1(x)                                                  \
+	(((x) & BIT_MASK_TAIL_PKT_Q1_V1) << BIT_SHIFT_TAIL_PKT_Q1_V1)
+#define BITS_TAIL_PKT_Q1_V1                                                    \
+	(BIT_MASK_TAIL_PKT_Q1_V1 << BIT_SHIFT_TAIL_PKT_Q1_V1)
+#define BIT_CLEAR_TAIL_PKT_Q1_V1(x) ((x) & (~BITS_TAIL_PKT_Q1_V1))
+#define BIT_GET_TAIL_PKT_Q1_V1(x)                                              \
+	(((x) >> BIT_SHIFT_TAIL_PKT_Q1_V1) & BIT_MASK_TAIL_PKT_Q1_V1)
+#define BIT_SET_TAIL_PKT_Q1_V1(x, v)                                           \
+	(BIT_CLEAR_TAIL_PKT_Q1_V1(x) | BIT_TAIL_PKT_Q1_V1(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_Q1_INFO				(Offset 0x0404) */
+
+#define BIT_SHIFT_TAIL_PKT_Q1_V2 11
+#define BIT_MASK_TAIL_PKT_Q1_V2 0x7ff
+#define BIT_TAIL_PKT_Q1_V2(x)                                                  \
+	(((x) & BIT_MASK_TAIL_PKT_Q1_V2) << BIT_SHIFT_TAIL_PKT_Q1_V2)
+#define BITS_TAIL_PKT_Q1_V2                                                    \
+	(BIT_MASK_TAIL_PKT_Q1_V2 << BIT_SHIFT_TAIL_PKT_Q1_V2)
+#define BIT_CLEAR_TAIL_PKT_Q1_V2(x) ((x) & (~BITS_TAIL_PKT_Q1_V2))
+#define BIT_GET_TAIL_PKT_Q1_V2(x)                                              \
+	(((x) >> BIT_SHIFT_TAIL_PKT_Q1_V2) & BIT_MASK_TAIL_PKT_Q1_V2)
+#define BIT_SET_TAIL_PKT_Q1_V2(x, v)                                           \
+	(BIT_CLEAR_TAIL_PKT_Q1_V2(x) | BIT_TAIL_PKT_Q1_V2(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_Q1_INFO				(Offset 0x0404) */
+
+#define BIT_SHIFT_PKT_NUM_Q1_V1 8
+#define BIT_MASK_PKT_NUM_Q1_V1 0x7f
+#define BIT_PKT_NUM_Q1_V1(x)                                                   \
+	(((x) & BIT_MASK_PKT_NUM_Q1_V1) << BIT_SHIFT_PKT_NUM_Q1_V1)
+#define BITS_PKT_NUM_Q1_V1 (BIT_MASK_PKT_NUM_Q1_V1 << BIT_SHIFT_PKT_NUM_Q1_V1)
+#define BIT_CLEAR_PKT_NUM_Q1_V1(x) ((x) & (~BITS_PKT_NUM_Q1_V1))
+#define BIT_GET_PKT_NUM_Q1_V1(x)                                               \
+	(((x) >> BIT_SHIFT_PKT_NUM_Q1_V1) & BIT_MASK_PKT_NUM_Q1_V1)
+#define BIT_SET_PKT_NUM_Q1_V1(x, v)                                            \
+	(BIT_CLEAR_PKT_NUM_Q1_V1(x) | BIT_PKT_NUM_Q1_V1(v))
+
+#define BIT_SHIFT_HEAD_PKT_Q1 0
+#define BIT_MASK_HEAD_PKT_Q1 0xff
+#define BIT_HEAD_PKT_Q1(x)                                                     \
+	(((x) & BIT_MASK_HEAD_PKT_Q1) << BIT_SHIFT_HEAD_PKT_Q1)
+#define BITS_HEAD_PKT_Q1 (BIT_MASK_HEAD_PKT_Q1 << BIT_SHIFT_HEAD_PKT_Q1)
+#define BIT_CLEAR_HEAD_PKT_Q1(x) ((x) & (~BITS_HEAD_PKT_Q1))
+#define BIT_GET_HEAD_PKT_Q1(x)                                                 \
+	(((x) >> BIT_SHIFT_HEAD_PKT_Q1) & BIT_MASK_HEAD_PKT_Q1)
+#define BIT_SET_HEAD_PKT_Q1(x, v)                                              \
+	(BIT_CLEAR_HEAD_PKT_Q1(x) | BIT_HEAD_PKT_Q1(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_Q1_INFO				(Offset 0x0404) */
+
+#define BIT_SHIFT_HEAD_PKT_Q1_V1 0
+#define BIT_MASK_HEAD_PKT_Q1_V1 0x7ff
+#define BIT_HEAD_PKT_Q1_V1(x)                                                  \
+	(((x) & BIT_MASK_HEAD_PKT_Q1_V1) << BIT_SHIFT_HEAD_PKT_Q1_V1)
+#define BITS_HEAD_PKT_Q1_V1                                                    \
+	(BIT_MASK_HEAD_PKT_Q1_V1 << BIT_SHIFT_HEAD_PKT_Q1_V1)
+#define BIT_CLEAR_HEAD_PKT_Q1_V1(x) ((x) & (~BITS_HEAD_PKT_Q1_V1))
+#define BIT_GET_HEAD_PKT_Q1_V1(x)                                              \
+	(((x) >> BIT_SHIFT_HEAD_PKT_Q1_V1) & BIT_MASK_HEAD_PKT_Q1_V1)
+#define BIT_SET_HEAD_PKT_Q1_V1(x, v)                                           \
+	(BIT_CLEAR_HEAD_PKT_Q1_V1(x) | BIT_HEAD_PKT_Q1_V1(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_QUEUELIST_INFO1			(Offset 0x0404) */
+
+#define BIT_SHIFT_QINFO1 0
+#define BIT_MASK_QINFO1 0xffffffffL
+#define BIT_QINFO1(x) (((x) & BIT_MASK_QINFO1) << BIT_SHIFT_QINFO1)
+#define BITS_QINFO1 (BIT_MASK_QINFO1 << BIT_SHIFT_QINFO1)
+#define BIT_CLEAR_QINFO1(x) ((x) & (~BITS_QINFO1))
+#define BIT_GET_QINFO1(x) (((x) >> BIT_SHIFT_QINFO1) & BIT_MASK_QINFO1)
+#define BIT_SET_QINFO1(x, v) (BIT_CLEAR_QINFO1(x) | BIT_QINFO1(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_Q2_INFO				(Offset 0x0408) */
+
+#define BIT_SHIFT_QUEUEMACID_Q2_V1 25
+#define BIT_MASK_QUEUEMACID_Q2_V1 0x7f
+#define BIT_QUEUEMACID_Q2_V1(x)                                                \
+	(((x) & BIT_MASK_QUEUEMACID_Q2_V1) << BIT_SHIFT_QUEUEMACID_Q2_V1)
+#define BITS_QUEUEMACID_Q2_V1                                                  \
+	(BIT_MASK_QUEUEMACID_Q2_V1 << BIT_SHIFT_QUEUEMACID_Q2_V1)
+#define BIT_CLEAR_QUEUEMACID_Q2_V1(x) ((x) & (~BITS_QUEUEMACID_Q2_V1))
+#define BIT_GET_QUEUEMACID_Q2_V1(x)                                            \
+	(((x) >> BIT_SHIFT_QUEUEMACID_Q2_V1) & BIT_MASK_QUEUEMACID_Q2_V1)
+#define BIT_SET_QUEUEMACID_Q2_V1(x, v)                                         \
+	(BIT_CLEAR_QUEUEMACID_Q2_V1(x) | BIT_QUEUEMACID_Q2_V1(v))
+
+#define BIT_SHIFT_QUEUEAC_Q2_V1 23
+#define BIT_MASK_QUEUEAC_Q2_V1 0x3
+#define BIT_QUEUEAC_Q2_V1(x)                                                   \
+	(((x) & BIT_MASK_QUEUEAC_Q2_V1) << BIT_SHIFT_QUEUEAC_Q2_V1)
+#define BITS_QUEUEAC_Q2_V1 (BIT_MASK_QUEUEAC_Q2_V1 << BIT_SHIFT_QUEUEAC_Q2_V1)
+#define BIT_CLEAR_QUEUEAC_Q2_V1(x) ((x) & (~BITS_QUEUEAC_Q2_V1))
+#define BIT_GET_QUEUEAC_Q2_V1(x)                                               \
+	(((x) >> BIT_SHIFT_QUEUEAC_Q2_V1) & BIT_MASK_QUEUEAC_Q2_V1)
+#define BIT_SET_QUEUEAC_Q2_V1(x, v)                                            \
+	(BIT_CLEAR_QUEUEAC_Q2_V1(x) | BIT_QUEUEAC_Q2_V1(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_Q2_INFO				(Offset 0x0408) */
+
+#define BIT_TIDEMPTY_Q2_V1 BIT(22)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_Q2_INFO				(Offset 0x0408) */
+
+#define BIT_SHIFT_TAIL_PKT_Q2_V1 15
+#define BIT_MASK_TAIL_PKT_Q2_V1 0xff
+#define BIT_TAIL_PKT_Q2_V1(x)                                                  \
+	(((x) & BIT_MASK_TAIL_PKT_Q2_V1) << BIT_SHIFT_TAIL_PKT_Q2_V1)
+#define BITS_TAIL_PKT_Q2_V1                                                    \
+	(BIT_MASK_TAIL_PKT_Q2_V1 << BIT_SHIFT_TAIL_PKT_Q2_V1)
+#define BIT_CLEAR_TAIL_PKT_Q2_V1(x) ((x) & (~BITS_TAIL_PKT_Q2_V1))
+#define BIT_GET_TAIL_PKT_Q2_V1(x)                                              \
+	(((x) >> BIT_SHIFT_TAIL_PKT_Q2_V1) & BIT_MASK_TAIL_PKT_Q2_V1)
+#define BIT_SET_TAIL_PKT_Q2_V1(x, v)                                           \
+	(BIT_CLEAR_TAIL_PKT_Q2_V1(x) | BIT_TAIL_PKT_Q2_V1(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_Q2_INFO				(Offset 0x0408) */
+
+#define BIT_SHIFT_TAIL_PKT_Q2_V2 11
+#define BIT_MASK_TAIL_PKT_Q2_V2 0x7ff
+#define BIT_TAIL_PKT_Q2_V2(x)                                                  \
+	(((x) & BIT_MASK_TAIL_PKT_Q2_V2) << BIT_SHIFT_TAIL_PKT_Q2_V2)
+#define BITS_TAIL_PKT_Q2_V2                                                    \
+	(BIT_MASK_TAIL_PKT_Q2_V2 << BIT_SHIFT_TAIL_PKT_Q2_V2)
+#define BIT_CLEAR_TAIL_PKT_Q2_V2(x) ((x) & (~BITS_TAIL_PKT_Q2_V2))
+#define BIT_GET_TAIL_PKT_Q2_V2(x)                                              \
+	(((x) >> BIT_SHIFT_TAIL_PKT_Q2_V2) & BIT_MASK_TAIL_PKT_Q2_V2)
+#define BIT_SET_TAIL_PKT_Q2_V2(x, v)                                           \
+	(BIT_CLEAR_TAIL_PKT_Q2_V2(x) | BIT_TAIL_PKT_Q2_V2(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_Q2_INFO				(Offset 0x0408) */
+
+#define BIT_SHIFT_PKT_NUM_Q2_V1 8
+#define BIT_MASK_PKT_NUM_Q2_V1 0x7f
+#define BIT_PKT_NUM_Q2_V1(x)                                                   \
+	(((x) & BIT_MASK_PKT_NUM_Q2_V1) << BIT_SHIFT_PKT_NUM_Q2_V1)
+#define BITS_PKT_NUM_Q2_V1 (BIT_MASK_PKT_NUM_Q2_V1 << BIT_SHIFT_PKT_NUM_Q2_V1)
+#define BIT_CLEAR_PKT_NUM_Q2_V1(x) ((x) & (~BITS_PKT_NUM_Q2_V1))
+#define BIT_GET_PKT_NUM_Q2_V1(x)                                               \
+	(((x) >> BIT_SHIFT_PKT_NUM_Q2_V1) & BIT_MASK_PKT_NUM_Q2_V1)
+#define BIT_SET_PKT_NUM_Q2_V1(x, v)                                            \
+	(BIT_CLEAR_PKT_NUM_Q2_V1(x) | BIT_PKT_NUM_Q2_V1(v))
+
+#define BIT_SHIFT_HEAD_PKT_Q2 0
+#define BIT_MASK_HEAD_PKT_Q2 0xff
+#define BIT_HEAD_PKT_Q2(x)                                                     \
+	(((x) & BIT_MASK_HEAD_PKT_Q2) << BIT_SHIFT_HEAD_PKT_Q2)
+#define BITS_HEAD_PKT_Q2 (BIT_MASK_HEAD_PKT_Q2 << BIT_SHIFT_HEAD_PKT_Q2)
+#define BIT_CLEAR_HEAD_PKT_Q2(x) ((x) & (~BITS_HEAD_PKT_Q2))
+#define BIT_GET_HEAD_PKT_Q2(x)                                                 \
+	(((x) >> BIT_SHIFT_HEAD_PKT_Q2) & BIT_MASK_HEAD_PKT_Q2)
+#define BIT_SET_HEAD_PKT_Q2(x, v)                                              \
+	(BIT_CLEAR_HEAD_PKT_Q2(x) | BIT_HEAD_PKT_Q2(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_Q2_INFO				(Offset 0x0408) */
+
+#define BIT_SHIFT_HEAD_PKT_Q2_V1 0
+#define BIT_MASK_HEAD_PKT_Q2_V1 0x7ff
+#define BIT_HEAD_PKT_Q2_V1(x)                                                  \
+	(((x) & BIT_MASK_HEAD_PKT_Q2_V1) << BIT_SHIFT_HEAD_PKT_Q2_V1)
+#define BITS_HEAD_PKT_Q2_V1                                                    \
+	(BIT_MASK_HEAD_PKT_Q2_V1 << BIT_SHIFT_HEAD_PKT_Q2_V1)
+#define BIT_CLEAR_HEAD_PKT_Q2_V1(x) ((x) & (~BITS_HEAD_PKT_Q2_V1))
+#define BIT_GET_HEAD_PKT_Q2_V1(x)                                              \
+	(((x) >> BIT_SHIFT_HEAD_PKT_Q2_V1) & BIT_MASK_HEAD_PKT_Q2_V1)
+#define BIT_SET_HEAD_PKT_Q2_V1(x, v)                                           \
+	(BIT_CLEAR_HEAD_PKT_Q2_V1(x) | BIT_HEAD_PKT_Q2_V1(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_QUEUELIST_INFO2			(Offset 0x0408) */
+
+#define BIT_SHIFT_QINFO2 0
+#define BIT_MASK_QINFO2 0xffffffffL
+#define BIT_QINFO2(x) (((x) & BIT_MASK_QINFO2) << BIT_SHIFT_QINFO2)
+#define BITS_QINFO2 (BIT_MASK_QINFO2 << BIT_SHIFT_QINFO2)
+#define BIT_CLEAR_QINFO2(x) ((x) & (~BITS_QINFO2))
+#define BIT_GET_QINFO2(x) (((x) >> BIT_SHIFT_QINFO2) & BIT_MASK_QINFO2)
+#define BIT_SET_QINFO2(x, v) (BIT_CLEAR_QINFO2(x) | BIT_QINFO2(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_Q3_INFO				(Offset 0x040C) */
+
+#define BIT_SHIFT_QUEUEMACID_Q3_V1 25
+#define BIT_MASK_QUEUEMACID_Q3_V1 0x7f
+#define BIT_QUEUEMACID_Q3_V1(x)                                                \
+	(((x) & BIT_MASK_QUEUEMACID_Q3_V1) << BIT_SHIFT_QUEUEMACID_Q3_V1)
+#define BITS_QUEUEMACID_Q3_V1                                                  \
+	(BIT_MASK_QUEUEMACID_Q3_V1 << BIT_SHIFT_QUEUEMACID_Q3_V1)
+#define BIT_CLEAR_QUEUEMACID_Q3_V1(x) ((x) & (~BITS_QUEUEMACID_Q3_V1))
+#define BIT_GET_QUEUEMACID_Q3_V1(x)                                            \
+	(((x) >> BIT_SHIFT_QUEUEMACID_Q3_V1) & BIT_MASK_QUEUEMACID_Q3_V1)
+#define BIT_SET_QUEUEMACID_Q3_V1(x, v)                                         \
+	(BIT_CLEAR_QUEUEMACID_Q3_V1(x) | BIT_QUEUEMACID_Q3_V1(v))
+
+#define BIT_SHIFT_QUEUEAC_Q3_V1 23
+#define BIT_MASK_QUEUEAC_Q3_V1 0x3
+#define BIT_QUEUEAC_Q3_V1(x)                                                   \
+	(((x) & BIT_MASK_QUEUEAC_Q3_V1) << BIT_SHIFT_QUEUEAC_Q3_V1)
+#define BITS_QUEUEAC_Q3_V1 (BIT_MASK_QUEUEAC_Q3_V1 << BIT_SHIFT_QUEUEAC_Q3_V1)
+#define BIT_CLEAR_QUEUEAC_Q3_V1(x) ((x) & (~BITS_QUEUEAC_Q3_V1))
+#define BIT_GET_QUEUEAC_Q3_V1(x)                                               \
+	(((x) >> BIT_SHIFT_QUEUEAC_Q3_V1) & BIT_MASK_QUEUEAC_Q3_V1)
+#define BIT_SET_QUEUEAC_Q3_V1(x, v)                                            \
+	(BIT_CLEAR_QUEUEAC_Q3_V1(x) | BIT_QUEUEAC_Q3_V1(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_Q3_INFO				(Offset 0x040C) */
+
+#define BIT_TIDEMPTY_Q3_V1 BIT(22)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_Q3_INFO				(Offset 0x040C) */
+
+#define BIT_SHIFT_TAIL_PKT_Q3_V1 15
+#define BIT_MASK_TAIL_PKT_Q3_V1 0xff
+#define BIT_TAIL_PKT_Q3_V1(x)                                                  \
+	(((x) & BIT_MASK_TAIL_PKT_Q3_V1) << BIT_SHIFT_TAIL_PKT_Q3_V1)
+#define BITS_TAIL_PKT_Q3_V1                                                    \
+	(BIT_MASK_TAIL_PKT_Q3_V1 << BIT_SHIFT_TAIL_PKT_Q3_V1)
+#define BIT_CLEAR_TAIL_PKT_Q3_V1(x) ((x) & (~BITS_TAIL_PKT_Q3_V1))
+#define BIT_GET_TAIL_PKT_Q3_V1(x)                                              \
+	(((x) >> BIT_SHIFT_TAIL_PKT_Q3_V1) & BIT_MASK_TAIL_PKT_Q3_V1)
+#define BIT_SET_TAIL_PKT_Q3_V1(x, v)                                           \
+	(BIT_CLEAR_TAIL_PKT_Q3_V1(x) | BIT_TAIL_PKT_Q3_V1(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_Q3_INFO				(Offset 0x040C) */
+
+#define BIT_SHIFT_TAIL_PKT_Q3_V2 11
+#define BIT_MASK_TAIL_PKT_Q3_V2 0x7ff
+#define BIT_TAIL_PKT_Q3_V2(x)                                                  \
+	(((x) & BIT_MASK_TAIL_PKT_Q3_V2) << BIT_SHIFT_TAIL_PKT_Q3_V2)
+#define BITS_TAIL_PKT_Q3_V2                                                    \
+	(BIT_MASK_TAIL_PKT_Q3_V2 << BIT_SHIFT_TAIL_PKT_Q3_V2)
+#define BIT_CLEAR_TAIL_PKT_Q3_V2(x) ((x) & (~BITS_TAIL_PKT_Q3_V2))
+#define BIT_GET_TAIL_PKT_Q3_V2(x)                                              \
+	(((x) >> BIT_SHIFT_TAIL_PKT_Q3_V2) & BIT_MASK_TAIL_PKT_Q3_V2)
+#define BIT_SET_TAIL_PKT_Q3_V2(x, v)                                           \
+	(BIT_CLEAR_TAIL_PKT_Q3_V2(x) | BIT_TAIL_PKT_Q3_V2(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_Q3_INFO				(Offset 0x040C) */
+
+#define BIT_SHIFT_PKT_NUM_Q3_V1 8
+#define BIT_MASK_PKT_NUM_Q3_V1 0x7f
+#define BIT_PKT_NUM_Q3_V1(x)                                                   \
+	(((x) & BIT_MASK_PKT_NUM_Q3_V1) << BIT_SHIFT_PKT_NUM_Q3_V1)
+#define BITS_PKT_NUM_Q3_V1 (BIT_MASK_PKT_NUM_Q3_V1 << BIT_SHIFT_PKT_NUM_Q3_V1)
+#define BIT_CLEAR_PKT_NUM_Q3_V1(x) ((x) & (~BITS_PKT_NUM_Q3_V1))
+#define BIT_GET_PKT_NUM_Q3_V1(x)                                               \
+	(((x) >> BIT_SHIFT_PKT_NUM_Q3_V1) & BIT_MASK_PKT_NUM_Q3_V1)
+#define BIT_SET_PKT_NUM_Q3_V1(x, v)                                            \
+	(BIT_CLEAR_PKT_NUM_Q3_V1(x) | BIT_PKT_NUM_Q3_V1(v))
+
+#define BIT_SHIFT_HEAD_PKT_Q3 0
+#define BIT_MASK_HEAD_PKT_Q3 0xff
+#define BIT_HEAD_PKT_Q3(x)                                                     \
+	(((x) & BIT_MASK_HEAD_PKT_Q3) << BIT_SHIFT_HEAD_PKT_Q3)
+#define BITS_HEAD_PKT_Q3 (BIT_MASK_HEAD_PKT_Q3 << BIT_SHIFT_HEAD_PKT_Q3)
+#define BIT_CLEAR_HEAD_PKT_Q3(x) ((x) & (~BITS_HEAD_PKT_Q3))
+#define BIT_GET_HEAD_PKT_Q3(x)                                                 \
+	(((x) >> BIT_SHIFT_HEAD_PKT_Q3) & BIT_MASK_HEAD_PKT_Q3)
+#define BIT_SET_HEAD_PKT_Q3(x, v)                                              \
+	(BIT_CLEAR_HEAD_PKT_Q3(x) | BIT_HEAD_PKT_Q3(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_Q3_INFO				(Offset 0x040C) */
+
+#define BIT_SHIFT_HEAD_PKT_Q3_V1 0
+#define BIT_MASK_HEAD_PKT_Q3_V1 0x7ff
+#define BIT_HEAD_PKT_Q3_V1(x)                                                  \
+	(((x) & BIT_MASK_HEAD_PKT_Q3_V1) << BIT_SHIFT_HEAD_PKT_Q3_V1)
+#define BITS_HEAD_PKT_Q3_V1                                                    \
+	(BIT_MASK_HEAD_PKT_Q3_V1 << BIT_SHIFT_HEAD_PKT_Q3_V1)
+#define BIT_CLEAR_HEAD_PKT_Q3_V1(x) ((x) & (~BITS_HEAD_PKT_Q3_V1))
+#define BIT_GET_HEAD_PKT_Q3_V1(x)                                              \
+	(((x) >> BIT_SHIFT_HEAD_PKT_Q3_V1) & BIT_MASK_HEAD_PKT_Q3_V1)
+#define BIT_SET_HEAD_PKT_Q3_V1(x, v)                                           \
+	(BIT_CLEAR_HEAD_PKT_Q3_V1(x) | BIT_HEAD_PKT_Q3_V1(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_QUEUELIST_INFO3			(Offset 0x040C) */
+
+#define BIT_SHIFT_QINFO3 0
+#define BIT_MASK_QINFO3 0xffffffffL
+#define BIT_QINFO3(x) (((x) & BIT_MASK_QINFO3) << BIT_SHIFT_QINFO3)
+#define BITS_QINFO3 (BIT_MASK_QINFO3 << BIT_SHIFT_QINFO3)
+#define BIT_CLEAR_QINFO3(x) ((x) & (~BITS_QINFO3))
+#define BIT_GET_QINFO3(x) (((x) >> BIT_SHIFT_QINFO3) & BIT_MASK_QINFO3)
+#define BIT_SET_QINFO3(x, v) (BIT_CLEAR_QINFO3(x) | BIT_QINFO3(v))
+
+/* 2 REG_QUEUELIST_INFO_EMPTY		(Offset 0x0410) */
+
+#define BIT_FWCMDQ_EMPTY BIT(31)
+#define BIT_MGQ_CPU_EMPTY_V1 BIT(30)
+#define BIT_BCNQ_EMPTY_EXTP0 BIT(29)
+#define BIT_BCNQ_EMPTY_PORT4 BIT(28)
+#define BIT_BCNQ_EMPTY_PORT3 BIT(27)
+#define BIT_BCNQ_EMPTY_PORT2 BIT(26)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_MGQ_INFO				(Offset 0x0410) */
+
+#define BIT_SHIFT_QUEUEMACID_MGQ_V1 25
+#define BIT_MASK_QUEUEMACID_MGQ_V1 0x7f
+#define BIT_QUEUEMACID_MGQ_V1(x)                                               \
+	(((x) & BIT_MASK_QUEUEMACID_MGQ_V1) << BIT_SHIFT_QUEUEMACID_MGQ_V1)
+#define BITS_QUEUEMACID_MGQ_V1                                                 \
+	(BIT_MASK_QUEUEMACID_MGQ_V1 << BIT_SHIFT_QUEUEMACID_MGQ_V1)
+#define BIT_CLEAR_QUEUEMACID_MGQ_V1(x) ((x) & (~BITS_QUEUEMACID_MGQ_V1))
+#define BIT_GET_QUEUEMACID_MGQ_V1(x)                                           \
+	(((x) >> BIT_SHIFT_QUEUEMACID_MGQ_V1) & BIT_MASK_QUEUEMACID_MGQ_V1)
+#define BIT_SET_QUEUEMACID_MGQ_V1(x, v)                                        \
+	(BIT_CLEAR_QUEUEMACID_MGQ_V1(x) | BIT_QUEUEMACID_MGQ_V1(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_QUEUELIST_INFO_EMPTY		(Offset 0x0410) */
+
+#define BIT_BCNQ_EMPTY_PORT1 BIT(25)
+#define BIT_BCNQ_EMPTY_PORT0 BIT(24)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_MGQ_INFO				(Offset 0x0410) */
+
+#define BIT_SHIFT_QUEUEAC_MGQ_V1 23
+#define BIT_MASK_QUEUEAC_MGQ_V1 0x3
+#define BIT_QUEUEAC_MGQ_V1(x)                                                  \
+	(((x) & BIT_MASK_QUEUEAC_MGQ_V1) << BIT_SHIFT_QUEUEAC_MGQ_V1)
+#define BITS_QUEUEAC_MGQ_V1                                                    \
+	(BIT_MASK_QUEUEAC_MGQ_V1 << BIT_SHIFT_QUEUEAC_MGQ_V1)
+#define BIT_CLEAR_QUEUEAC_MGQ_V1(x) ((x) & (~BITS_QUEUEAC_MGQ_V1))
+#define BIT_GET_QUEUEAC_MGQ_V1(x)                                              \
+	(((x) >> BIT_SHIFT_QUEUEAC_MGQ_V1) & BIT_MASK_QUEUEAC_MGQ_V1)
+#define BIT_SET_QUEUEAC_MGQ_V1(x, v)                                           \
+	(BIT_CLEAR_QUEUEAC_MGQ_V1(x) | BIT_QUEUEAC_MGQ_V1(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_QUEUELIST_INFO_EMPTY		(Offset 0x0410) */
+
+#define BIT_HQQ_EMPTY_V1 BIT(23)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_MGQ_INFO				(Offset 0x0410) */
+
+#define BIT_TIDEMPTY_MGQ_V1 BIT(22)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_QUEUELIST_INFO_EMPTY		(Offset 0x0410) */
+
+#define BIT_MQQ_EMPTY_V2 BIT(22)
+#define BIT_S1_EMPTY BIT(21)
+#define BIT_S0_EMPTY BIT(20)
+#define BIT_AC19Q_EMPTY BIT(19)
+#define BIT_AC18Q_EMPTY BIT(18)
+#define BIT_AC17Q_EMPTY BIT(17)
+#define BIT_AC16Q_EMPTY BIT(16)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_MGQ_INFO				(Offset 0x0410) */
+
+#define BIT_SHIFT_TAIL_PKT_MGQ_V1 15
+#define BIT_MASK_TAIL_PKT_MGQ_V1 0xff
+#define BIT_TAIL_PKT_MGQ_V1(x)                                                 \
+	(((x) & BIT_MASK_TAIL_PKT_MGQ_V1) << BIT_SHIFT_TAIL_PKT_MGQ_V1)
+#define BITS_TAIL_PKT_MGQ_V1                                                   \
+	(BIT_MASK_TAIL_PKT_MGQ_V1 << BIT_SHIFT_TAIL_PKT_MGQ_V1)
+#define BIT_CLEAR_TAIL_PKT_MGQ_V1(x) ((x) & (~BITS_TAIL_PKT_MGQ_V1))
+#define BIT_GET_TAIL_PKT_MGQ_V1(x)                                             \
+	(((x) >> BIT_SHIFT_TAIL_PKT_MGQ_V1) & BIT_MASK_TAIL_PKT_MGQ_V1)
+#define BIT_SET_TAIL_PKT_MGQ_V1(x, v)                                          \
+	(BIT_CLEAR_TAIL_PKT_MGQ_V1(x) | BIT_TAIL_PKT_MGQ_V1(v))
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT)
+
+/* 2 REG_QUEUELIST_INFO_EMPTY		(Offset 0x0410) */
+
+#define BIT_AC15Q_EMPTY BIT(15)
+#define BIT_AC14Q_EMPTY BIT(14)
+#define BIT_AC13Q_EMPTY BIT(13)
+#define BIT_AC12Q_EMPTY BIT(12)
+#define BIT_AC11Q_EMPTY BIT(11)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_MGQ_INFO				(Offset 0x0410) */
+
+#define BIT_SHIFT_TAIL_PKT_MGQ_V2 11
+#define BIT_MASK_TAIL_PKT_MGQ_V2 0x7ff
+#define BIT_TAIL_PKT_MGQ_V2(x)                                                 \
+	(((x) & BIT_MASK_TAIL_PKT_MGQ_V2) << BIT_SHIFT_TAIL_PKT_MGQ_V2)
+#define BITS_TAIL_PKT_MGQ_V2                                                   \
+	(BIT_MASK_TAIL_PKT_MGQ_V2 << BIT_SHIFT_TAIL_PKT_MGQ_V2)
+#define BIT_CLEAR_TAIL_PKT_MGQ_V2(x) ((x) & (~BITS_TAIL_PKT_MGQ_V2))
+#define BIT_GET_TAIL_PKT_MGQ_V2(x)                                             \
+	(((x) >> BIT_SHIFT_TAIL_PKT_MGQ_V2) & BIT_MASK_TAIL_PKT_MGQ_V2)
+#define BIT_SET_TAIL_PKT_MGQ_V2(x, v)                                          \
+	(BIT_CLEAR_TAIL_PKT_MGQ_V2(x) | BIT_TAIL_PKT_MGQ_V2(v))
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT)
+
+/* 2 REG_QUEUELIST_INFO_EMPTY		(Offset 0x0410) */
+
+#define BIT_AC10Q_EMPTY BIT(10)
+#define BIT_AC9Q_EMPTY BIT(9)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_MGQ_INFO				(Offset 0x0410) */
+
+#define BIT_SHIFT_PKT_NUM_MGQ_V1 8
+#define BIT_MASK_PKT_NUM_MGQ_V1 0x7f
+#define BIT_PKT_NUM_MGQ_V1(x)                                                  \
+	(((x) & BIT_MASK_PKT_NUM_MGQ_V1) << BIT_SHIFT_PKT_NUM_MGQ_V1)
+#define BITS_PKT_NUM_MGQ_V1                                                    \
+	(BIT_MASK_PKT_NUM_MGQ_V1 << BIT_SHIFT_PKT_NUM_MGQ_V1)
+#define BIT_CLEAR_PKT_NUM_MGQ_V1(x) ((x) & (~BITS_PKT_NUM_MGQ_V1))
+#define BIT_GET_PKT_NUM_MGQ_V1(x)                                              \
+	(((x) >> BIT_SHIFT_PKT_NUM_MGQ_V1) & BIT_MASK_PKT_NUM_MGQ_V1)
+#define BIT_SET_PKT_NUM_MGQ_V1(x, v)                                           \
+	(BIT_CLEAR_PKT_NUM_MGQ_V1(x) | BIT_PKT_NUM_MGQ_V1(v))
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT)
+
+/* 2 REG_QUEUELIST_INFO_EMPTY		(Offset 0x0410) */
+
+#define BIT_AC8Q_EMPTY BIT(8)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_MGQ_INFO				(Offset 0x0410) */
+
+#define BIT_SHIFT_HEAD_PKT_MGQ 0
+#define BIT_MASK_HEAD_PKT_MGQ 0xff
+#define BIT_HEAD_PKT_MGQ(x)                                                    \
+	(((x) & BIT_MASK_HEAD_PKT_MGQ) << BIT_SHIFT_HEAD_PKT_MGQ)
+#define BITS_HEAD_PKT_MGQ (BIT_MASK_HEAD_PKT_MGQ << BIT_SHIFT_HEAD_PKT_MGQ)
+#define BIT_CLEAR_HEAD_PKT_MGQ(x) ((x) & (~BITS_HEAD_PKT_MGQ))
+#define BIT_GET_HEAD_PKT_MGQ(x)                                                \
+	(((x) >> BIT_SHIFT_HEAD_PKT_MGQ) & BIT_MASK_HEAD_PKT_MGQ)
+#define BIT_SET_HEAD_PKT_MGQ(x, v)                                             \
+	(BIT_CLEAR_HEAD_PKT_MGQ(x) | BIT_HEAD_PKT_MGQ(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_MGQ_INFO				(Offset 0x0410) */
+
+#define BIT_SHIFT_HEAD_PKT_MGQ_V1 0
+#define BIT_MASK_HEAD_PKT_MGQ_V1 0x7ff
+#define BIT_HEAD_PKT_MGQ_V1(x)                                                 \
+	(((x) & BIT_MASK_HEAD_PKT_MGQ_V1) << BIT_SHIFT_HEAD_PKT_MGQ_V1)
+#define BITS_HEAD_PKT_MGQ_V1                                                   \
+	(BIT_MASK_HEAD_PKT_MGQ_V1 << BIT_SHIFT_HEAD_PKT_MGQ_V1)
+#define BIT_CLEAR_HEAD_PKT_MGQ_V1(x) ((x) & (~BITS_HEAD_PKT_MGQ_V1))
+#define BIT_GET_HEAD_PKT_MGQ_V1(x)                                             \
+	(((x) >> BIT_SHIFT_HEAD_PKT_MGQ_V1) & BIT_MASK_HEAD_PKT_MGQ_V1)
+#define BIT_SET_HEAD_PKT_MGQ_V1(x, v)                                          \
+	(BIT_CLEAR_HEAD_PKT_MGQ_V1(x) | BIT_HEAD_PKT_MGQ_V1(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_HIQ_INFO				(Offset 0x0414) */
+
+#define BIT_SHIFT_QUEUEMACID_HIQ_V1 25
+#define BIT_MASK_QUEUEMACID_HIQ_V1 0x7f
+#define BIT_QUEUEMACID_HIQ_V1(x)                                               \
+	(((x) & BIT_MASK_QUEUEMACID_HIQ_V1) << BIT_SHIFT_QUEUEMACID_HIQ_V1)
+#define BITS_QUEUEMACID_HIQ_V1                                                 \
+	(BIT_MASK_QUEUEMACID_HIQ_V1 << BIT_SHIFT_QUEUEMACID_HIQ_V1)
+#define BIT_CLEAR_QUEUEMACID_HIQ_V1(x) ((x) & (~BITS_QUEUEMACID_HIQ_V1))
+#define BIT_GET_QUEUEMACID_HIQ_V1(x)                                           \
+	(((x) >> BIT_SHIFT_QUEUEMACID_HIQ_V1) & BIT_MASK_QUEUEMACID_HIQ_V1)
+#define BIT_SET_QUEUEMACID_HIQ_V1(x, v)                                        \
+	(BIT_CLEAR_QUEUEMACID_HIQ_V1(x) | BIT_QUEUEMACID_HIQ_V1(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_QUEUELIST_ACQ_EN			(Offset 0x0414) */
+
+#define BIT_SHIFT_QINFO_CTRL 24
+#define BIT_MASK_QINFO_CTRL 0x3f
+#define BIT_QINFO_CTRL(x) (((x) & BIT_MASK_QINFO_CTRL) << BIT_SHIFT_QINFO_CTRL)
+#define BITS_QINFO_CTRL (BIT_MASK_QINFO_CTRL << BIT_SHIFT_QINFO_CTRL)
+#define BIT_CLEAR_QINFO_CTRL(x) ((x) & (~BITS_QINFO_CTRL))
+#define BIT_GET_QINFO_CTRL(x)                                                  \
+	(((x) >> BIT_SHIFT_QINFO_CTRL) & BIT_MASK_QINFO_CTRL)
+#define BIT_SET_QINFO_CTRL(x, v) (BIT_CLEAR_QINFO_CTRL(x) | BIT_QINFO_CTRL(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_HIQ_INFO				(Offset 0x0414) */
+
+#define BIT_SHIFT_QUEUEAC_HIQ_V1 23
+#define BIT_MASK_QUEUEAC_HIQ_V1 0x3
+#define BIT_QUEUEAC_HIQ_V1(x)                                                  \
+	(((x) & BIT_MASK_QUEUEAC_HIQ_V1) << BIT_SHIFT_QUEUEAC_HIQ_V1)
+#define BITS_QUEUEAC_HIQ_V1                                                    \
+	(BIT_MASK_QUEUEAC_HIQ_V1 << BIT_SHIFT_QUEUEAC_HIQ_V1)
+#define BIT_CLEAR_QUEUEAC_HIQ_V1(x) ((x) & (~BITS_QUEUEAC_HIQ_V1))
+#define BIT_GET_QUEUEAC_HIQ_V1(x)                                              \
+	(((x) >> BIT_SHIFT_QUEUEAC_HIQ_V1) & BIT_MASK_QUEUEAC_HIQ_V1)
+#define BIT_SET_QUEUEAC_HIQ_V1(x, v)                                           \
+	(BIT_CLEAR_QUEUEAC_HIQ_V1(x) | BIT_QUEUEAC_HIQ_V1(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_HIQ_INFO				(Offset 0x0414) */
+
+#define BIT_TIDEMPTY_HIQ_V1 BIT(22)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_QUEUELIST_ACQ_EN			(Offset 0x0414) */
+
+#define BIT_SHIFT_QINFO_MODE_BAND 20
+#define BIT_MASK_QINFO_MODE_BAND 0x7
+#define BIT_QINFO_MODE_BAND(x)                                                 \
+	(((x) & BIT_MASK_QINFO_MODE_BAND) << BIT_SHIFT_QINFO_MODE_BAND)
+#define BITS_QINFO_MODE_BAND                                                   \
+	(BIT_MASK_QINFO_MODE_BAND << BIT_SHIFT_QINFO_MODE_BAND)
+#define BIT_CLEAR_QINFO_MODE_BAND(x) ((x) & (~BITS_QINFO_MODE_BAND))
+#define BIT_GET_QINFO_MODE_BAND(x)                                             \
+	(((x) >> BIT_SHIFT_QINFO_MODE_BAND) & BIT_MASK_QINFO_MODE_BAND)
+#define BIT_SET_QINFO_MODE_BAND(x, v)                                          \
+	(BIT_CLEAR_QINFO_MODE_BAND(x) | BIT_QINFO_MODE_BAND(v))
+
+#define BIT_ACQ19_ENABLE BIT(19)
+#define BIT_ACQ18_ENABLE BIT(18)
+#define BIT_ACQ17_ENABLE BIT(17)
+#define BIT_ACQ16_ENABLE BIT(16)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_HIQ_INFO				(Offset 0x0414) */
+
+#define BIT_SHIFT_TAIL_PKT_HIQ_V1 15
+#define BIT_MASK_TAIL_PKT_HIQ_V1 0xff
+#define BIT_TAIL_PKT_HIQ_V1(x)                                                 \
+	(((x) & BIT_MASK_TAIL_PKT_HIQ_V1) << BIT_SHIFT_TAIL_PKT_HIQ_V1)
+#define BITS_TAIL_PKT_HIQ_V1                                                   \
+	(BIT_MASK_TAIL_PKT_HIQ_V1 << BIT_SHIFT_TAIL_PKT_HIQ_V1)
+#define BIT_CLEAR_TAIL_PKT_HIQ_V1(x) ((x) & (~BITS_TAIL_PKT_HIQ_V1))
+#define BIT_GET_TAIL_PKT_HIQ_V1(x)                                             \
+	(((x) >> BIT_SHIFT_TAIL_PKT_HIQ_V1) & BIT_MASK_TAIL_PKT_HIQ_V1)
+#define BIT_SET_TAIL_PKT_HIQ_V1(x, v)                                          \
+	(BIT_CLEAR_TAIL_PKT_HIQ_V1(x) | BIT_TAIL_PKT_HIQ_V1(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_QUEUELIST_ACQ_EN			(Offset 0x0414) */
+
+#define BIT_ACQ15_ENABLE BIT(15)
+#define BIT_ACQ14_ENABLE BIT(14)
+#define BIT_ACQ13_ENABLE BIT(13)
+#define BIT_ACQ12_ENABLE BIT(12)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_HIQ_INFO				(Offset 0x0414) */
+
+#define BIT_SHIFT_TAIL_PKT_HIQ_V2 11
+#define BIT_MASK_TAIL_PKT_HIQ_V2 0x7ff
+#define BIT_TAIL_PKT_HIQ_V2(x)                                                 \
+	(((x) & BIT_MASK_TAIL_PKT_HIQ_V2) << BIT_SHIFT_TAIL_PKT_HIQ_V2)
+#define BITS_TAIL_PKT_HIQ_V2                                                   \
+	(BIT_MASK_TAIL_PKT_HIQ_V2 << BIT_SHIFT_TAIL_PKT_HIQ_V2)
+#define BIT_CLEAR_TAIL_PKT_HIQ_V2(x) ((x) & (~BITS_TAIL_PKT_HIQ_V2))
+#define BIT_GET_TAIL_PKT_HIQ_V2(x)                                             \
+	(((x) >> BIT_SHIFT_TAIL_PKT_HIQ_V2) & BIT_MASK_TAIL_PKT_HIQ_V2)
+#define BIT_SET_TAIL_PKT_HIQ_V2(x, v)                                          \
+	(BIT_CLEAR_TAIL_PKT_HIQ_V2(x) | BIT_TAIL_PKT_HIQ_V2(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_QUEUELIST_ACQ_EN			(Offset 0x0414) */
+
+#define BIT_ACQ11_ENABLE BIT(11)
+#define BIT_ACQ10_ENABLE BIT(10)
+#define BIT_ACQ9_ENABLE BIT(9)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_HIQ_INFO				(Offset 0x0414) */
+
+#define BIT_SHIFT_PKT_NUM_HIQ_V1 8
+#define BIT_MASK_PKT_NUM_HIQ_V1 0x7f
+#define BIT_PKT_NUM_HIQ_V1(x)                                                  \
+	(((x) & BIT_MASK_PKT_NUM_HIQ_V1) << BIT_SHIFT_PKT_NUM_HIQ_V1)
+#define BITS_PKT_NUM_HIQ_V1                                                    \
+	(BIT_MASK_PKT_NUM_HIQ_V1 << BIT_SHIFT_PKT_NUM_HIQ_V1)
+#define BIT_CLEAR_PKT_NUM_HIQ_V1(x) ((x) & (~BITS_PKT_NUM_HIQ_V1))
+#define BIT_GET_PKT_NUM_HIQ_V1(x)                                              \
+	(((x) >> BIT_SHIFT_PKT_NUM_HIQ_V1) & BIT_MASK_PKT_NUM_HIQ_V1)
+#define BIT_SET_PKT_NUM_HIQ_V1(x, v)                                           \
+	(BIT_CLEAR_PKT_NUM_HIQ_V1(x) | BIT_PKT_NUM_HIQ_V1(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_QUEUELIST_ACQ_EN			(Offset 0x0414) */
+
+#define BIT_ACQ8_ENABLE BIT(8)
+#define BIT_ACQ7_ENABLE BIT(7)
+#define BIT_ACQ6_ENABLE BIT(6)
+#define BIT_ACQ5_ENABLE BIT(5)
+#define BIT_ACQ4_ENABLE BIT(4)
+#define BIT_ACQ3_ENABLE BIT(3)
+#define BIT_ACQ2_ENABLE BIT(2)
+#define BIT_ACQ1_ENABLE BIT(1)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_HIQ_INFO				(Offset 0x0414) */
+
+#define BIT_SHIFT_HEAD_PKT_HIQ 0
+#define BIT_MASK_HEAD_PKT_HIQ 0xff
+#define BIT_HEAD_PKT_HIQ(x)                                                    \
+	(((x) & BIT_MASK_HEAD_PKT_HIQ) << BIT_SHIFT_HEAD_PKT_HIQ)
+#define BITS_HEAD_PKT_HIQ (BIT_MASK_HEAD_PKT_HIQ << BIT_SHIFT_HEAD_PKT_HIQ)
+#define BIT_CLEAR_HEAD_PKT_HIQ(x) ((x) & (~BITS_HEAD_PKT_HIQ))
+#define BIT_GET_HEAD_PKT_HIQ(x)                                                \
+	(((x) >> BIT_SHIFT_HEAD_PKT_HIQ) & BIT_MASK_HEAD_PKT_HIQ)
+#define BIT_SET_HEAD_PKT_HIQ(x, v)                                             \
+	(BIT_CLEAR_HEAD_PKT_HIQ(x) | BIT_HEAD_PKT_HIQ(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_HIQ_INFO				(Offset 0x0414) */
+
+#define BIT_SHIFT_HEAD_PKT_HIQ_V1 0
+#define BIT_MASK_HEAD_PKT_HIQ_V1 0x7ff
+#define BIT_HEAD_PKT_HIQ_V1(x)                                                 \
+	(((x) & BIT_MASK_HEAD_PKT_HIQ_V1) << BIT_SHIFT_HEAD_PKT_HIQ_V1)
+#define BITS_HEAD_PKT_HIQ_V1                                                   \
+	(BIT_MASK_HEAD_PKT_HIQ_V1 << BIT_SHIFT_HEAD_PKT_HIQ_V1)
+#define BIT_CLEAR_HEAD_PKT_HIQ_V1(x) ((x) & (~BITS_HEAD_PKT_HIQ_V1))
+#define BIT_GET_HEAD_PKT_HIQ_V1(x)                                             \
+	(((x) >> BIT_SHIFT_HEAD_PKT_HIQ_V1) & BIT_MASK_HEAD_PKT_HIQ_V1)
+#define BIT_SET_HEAD_PKT_HIQ_V1(x, v)                                          \
+	(BIT_CLEAR_HEAD_PKT_HIQ_V1(x) | BIT_HEAD_PKT_HIQ_V1(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_QUEUELIST_ACQ_EN			(Offset 0x0414) */
+
+#define BIT_ACQ0_ENABLE BIT(0)
+
+/* 2 REG_BCNQ_BDNY_V2			(Offset 0x0418) */
+
+#define BIT_SHIFT_BCNQ_PGBNDY_WSEL 28
+#define BIT_MASK_BCNQ_PGBNDY_WSEL 0x7
+#define BIT_BCNQ_PGBNDY_WSEL(x)                                                \
+	(((x) & BIT_MASK_BCNQ_PGBNDY_WSEL) << BIT_SHIFT_BCNQ_PGBNDY_WSEL)
+#define BITS_BCNQ_PGBNDY_WSEL                                                  \
+	(BIT_MASK_BCNQ_PGBNDY_WSEL << BIT_SHIFT_BCNQ_PGBNDY_WSEL)
+#define BIT_CLEAR_BCNQ_PGBNDY_WSEL(x) ((x) & (~BITS_BCNQ_PGBNDY_WSEL))
+#define BIT_GET_BCNQ_PGBNDY_WSEL(x)                                            \
+	(((x) >> BIT_SHIFT_BCNQ_PGBNDY_WSEL) & BIT_MASK_BCNQ_PGBNDY_WSEL)
+#define BIT_SET_BCNQ_PGBNDY_WSEL(x, v)                                         \
+	(BIT_CLEAR_BCNQ_PGBNDY_WSEL(x) | BIT_BCNQ_PGBNDY_WSEL(v))
+
+#define BIT_SHIFT_BCNQ_PGBNDY_RCONTENT 12
+#define BIT_MASK_BCNQ_PGBNDY_RCONTENT 0xfff
+#define BIT_BCNQ_PGBNDY_RCONTENT(x)                                            \
+	(((x) & BIT_MASK_BCNQ_PGBNDY_RCONTENT)                                 \
+	 << BIT_SHIFT_BCNQ_PGBNDY_RCONTENT)
+#define BITS_BCNQ_PGBNDY_RCONTENT                                              \
+	(BIT_MASK_BCNQ_PGBNDY_RCONTENT << BIT_SHIFT_BCNQ_PGBNDY_RCONTENT)
+#define BIT_CLEAR_BCNQ_PGBNDY_RCONTENT(x) ((x) & (~BITS_BCNQ_PGBNDY_RCONTENT))
+#define BIT_GET_BCNQ_PGBNDY_RCONTENT(x)                                        \
+	(((x) >> BIT_SHIFT_BCNQ_PGBNDY_RCONTENT) &                             \
+	 BIT_MASK_BCNQ_PGBNDY_RCONTENT)
+#define BIT_SET_BCNQ_PGBNDY_RCONTENT(x, v)                                     \
+	(BIT_CLEAR_BCNQ_PGBNDY_RCONTENT(x) | BIT_BCNQ_PGBNDY_RCONTENT(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_BCNQ_INFO				(Offset 0x0418) */
+
+#define BIT_SHIFT_PKT_NUM_BCNQ 8
+#define BIT_MASK_PKT_NUM_BCNQ 0xff
+#define BIT_PKT_NUM_BCNQ(x)                                                    \
+	(((x) & BIT_MASK_PKT_NUM_BCNQ) << BIT_SHIFT_PKT_NUM_BCNQ)
+#define BITS_PKT_NUM_BCNQ (BIT_MASK_PKT_NUM_BCNQ << BIT_SHIFT_PKT_NUM_BCNQ)
+#define BIT_CLEAR_PKT_NUM_BCNQ(x) ((x) & (~BITS_PKT_NUM_BCNQ))
+#define BIT_GET_PKT_NUM_BCNQ(x)                                                \
+	(((x) >> BIT_SHIFT_PKT_NUM_BCNQ) & BIT_MASK_PKT_NUM_BCNQ)
+#define BIT_SET_PKT_NUM_BCNQ(x, v)                                             \
+	(BIT_CLEAR_PKT_NUM_BCNQ(x) | BIT_PKT_NUM_BCNQ(v))
+
+#define BIT_SHIFT_BCNQ_HEAD_PG 0
+#define BIT_MASK_BCNQ_HEAD_PG 0xff
+#define BIT_BCNQ_HEAD_PG(x)                                                    \
+	(((x) & BIT_MASK_BCNQ_HEAD_PG) << BIT_SHIFT_BCNQ_HEAD_PG)
+#define BITS_BCNQ_HEAD_PG (BIT_MASK_BCNQ_HEAD_PG << BIT_SHIFT_BCNQ_HEAD_PG)
+#define BIT_CLEAR_BCNQ_HEAD_PG(x) ((x) & (~BITS_BCNQ_HEAD_PG))
+#define BIT_GET_BCNQ_HEAD_PG(x)                                                \
+	(((x) >> BIT_SHIFT_BCNQ_HEAD_PG) & BIT_MASK_BCNQ_HEAD_PG)
+#define BIT_SET_BCNQ_HEAD_PG(x, v)                                             \
+	(BIT_CLEAR_BCNQ_HEAD_PG(x) | BIT_BCNQ_HEAD_PG(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_BCNQ_INFO				(Offset 0x0418) */
+
+#define BIT_SHIFT_BCNQ_HEAD_PG_V1 0
+#define BIT_MASK_BCNQ_HEAD_PG_V1 0xfff
+#define BIT_BCNQ_HEAD_PG_V1(x)                                                 \
+	(((x) & BIT_MASK_BCNQ_HEAD_PG_V1) << BIT_SHIFT_BCNQ_HEAD_PG_V1)
+#define BITS_BCNQ_HEAD_PG_V1                                                   \
+	(BIT_MASK_BCNQ_HEAD_PG_V1 << BIT_SHIFT_BCNQ_HEAD_PG_V1)
+#define BIT_CLEAR_BCNQ_HEAD_PG_V1(x) ((x) & (~BITS_BCNQ_HEAD_PG_V1))
+#define BIT_GET_BCNQ_HEAD_PG_V1(x)                                             \
+	(((x) >> BIT_SHIFT_BCNQ_HEAD_PG_V1) & BIT_MASK_BCNQ_HEAD_PG_V1)
+#define BIT_SET_BCNQ_HEAD_PG_V1(x, v)                                          \
+	(BIT_CLEAR_BCNQ_HEAD_PG_V1(x) | BIT_BCNQ_HEAD_PG_V1(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_BCNQ_BDNY_V2			(Offset 0x0418) */
+
+#define BIT_SHIFT_BCNQ_PGBNDY_WCONTENT 0
+#define BIT_MASK_BCNQ_PGBNDY_WCONTENT 0xfff
+#define BIT_BCNQ_PGBNDY_WCONTENT(x)                                            \
+	(((x) & BIT_MASK_BCNQ_PGBNDY_WCONTENT)                                 \
+	 << BIT_SHIFT_BCNQ_PGBNDY_WCONTENT)
+#define BITS_BCNQ_PGBNDY_WCONTENT                                              \
+	(BIT_MASK_BCNQ_PGBNDY_WCONTENT << BIT_SHIFT_BCNQ_PGBNDY_WCONTENT)
+#define BIT_CLEAR_BCNQ_PGBNDY_WCONTENT(x) ((x) & (~BITS_BCNQ_PGBNDY_WCONTENT))
+#define BIT_GET_BCNQ_PGBNDY_WCONTENT(x)                                        \
+	(((x) >> BIT_SHIFT_BCNQ_PGBNDY_WCONTENT) &                             \
+	 BIT_MASK_BCNQ_PGBNDY_WCONTENT)
+#define BIT_SET_BCNQ_PGBNDY_WCONTENT(x, v)                                     \
+	(BIT_CLEAR_BCNQ_PGBNDY_WCONTENT(x) | BIT_BCNQ_PGBNDY_WCONTENT(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_TXPKT_EMPTY				(Offset 0x041A) */
+
+#define BIT_BCNQ_EMPTY BIT(11)
+#define BIT_HQQ_EMPTY BIT(10)
+#define BIT_MQQ_EMPTY BIT(9)
+#define BIT_MGQ_CPU_EMPTY BIT(8)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_CPU_MGQ_INFO			(Offset 0x041C) */
+
+#define BIT_BCN_POLL2 BIT(31)
+#define BIT_BCN_POLL1 BIT(30)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_CPU_MGQ_INFO			(Offset 0x041C) */
+
+#define BIT_BCN1_POLL BIT(30)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_CPU_MGQ_INFO			(Offset 0x041C) */
+
+#define BIT_CPUMGT_CLR_V1 BIT(30)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_CPU_MGQ_INFO			(Offset 0x041C) */
+
+#define BIT_CPUMGT_POLL BIT(29)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_CPU_MGQ_INFO			(Offset 0x041C) */
+
+#define BIT_CPUMGT_POLL_SET BIT(29)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_CPU_MGQ_INFO			(Offset 0x041C) */
+
+#define BIT_BCN_POLL BIT(28)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_CPU_MGQ_INFO			(Offset 0x041C) */
+
+#define BIT_CPUMGT_POLL_CLR BIT(27)
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+/* 2 REG_CPU_MGQ_INFO			(Offset 0x041C) */
+
+#define BIT_CPUMGT_CLR BIT(27)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_CPU_MGQ_INFO			(Offset 0x041C) */
+
+#define BIT_EVTQ_VALID BIT(26)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_CPU_MGQ_INFO			(Offset 0x041C) */
+
+#define BIT_BCN_EXT_POLL BIT(21)
+#define BIT_BCN4_POLL BIT(20)
+#define BIT_BCN3_POLL BIT(19)
+#define BIT_BCN2_POLL BIT(18)
+#define BIT_BCN1_POLL_V1 BIT(17)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_CPU_MGQ_INFO			(Offset 0x041C) */
+
+#define BIT_EN_RTY_BK_COND BIT(16)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_CPU_MGQ_INFO			(Offset 0x041C) */
+
+#define BIT_BCN_POLL_V1 BIT(16)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_CPU_MGQ_INFO			(Offset 0x041C) */
+
+#define BIT_CPUMGQ_FW_NUM_V1 BIT(12)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_CPU_MGQ_INFO			(Offset 0x041C) */
+
+#define BIT_CPUMGQ_FW_NUM BIT(8)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_CPU_MGQ_INFO			(Offset 0x041C) */
+
+#define BIT_EN_EVTQ_RPT BIT(2)
+#define BIT_HWSEQ_EVTQ_EN BIT(1)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_CPU_MGQ_INFO			(Offset 0x041C) */
+
+#define BIT_SHIFT_CPUMGQ_HEAD_PG 0
+#define BIT_MASK_CPUMGQ_HEAD_PG 0xff
+#define BIT_CPUMGQ_HEAD_PG(x)                                                  \
+	(((x) & BIT_MASK_CPUMGQ_HEAD_PG) << BIT_SHIFT_CPUMGQ_HEAD_PG)
+#define BITS_CPUMGQ_HEAD_PG                                                    \
+	(BIT_MASK_CPUMGQ_HEAD_PG << BIT_SHIFT_CPUMGQ_HEAD_PG)
+#define BIT_CLEAR_CPUMGQ_HEAD_PG(x) ((x) & (~BITS_CPUMGQ_HEAD_PG))
+#define BIT_GET_CPUMGQ_HEAD_PG(x)                                              \
+	(((x) >> BIT_SHIFT_CPUMGQ_HEAD_PG) & BIT_MASK_CPUMGQ_HEAD_PG)
+#define BIT_SET_CPUMGQ_HEAD_PG(x, v)                                           \
+	(BIT_CLEAR_CPUMGQ_HEAD_PG(x) | BIT_CPUMGQ_HEAD_PG(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_CPU_MGQ_INFO			(Offset 0x041C) */
+
+#define BIT_SHIFT_FW_FREE_TAIL_V1 0
+#define BIT_MASK_FW_FREE_TAIL_V1 0xfff
+#define BIT_FW_FREE_TAIL_V1(x)                                                 \
+	(((x) & BIT_MASK_FW_FREE_TAIL_V1) << BIT_SHIFT_FW_FREE_TAIL_V1)
+#define BITS_FW_FREE_TAIL_V1                                                   \
+	(BIT_MASK_FW_FREE_TAIL_V1 << BIT_SHIFT_FW_FREE_TAIL_V1)
+#define BIT_CLEAR_FW_FREE_TAIL_V1(x) ((x) & (~BITS_FW_FREE_TAIL_V1))
+#define BIT_GET_FW_FREE_TAIL_V1(x)                                             \
+	(((x) >> BIT_SHIFT_FW_FREE_TAIL_V1) & BIT_MASK_FW_FREE_TAIL_V1)
+#define BIT_SET_FW_FREE_TAIL_V1(x, v)                                          \
+	(BIT_CLEAR_FW_FREE_TAIL_V1(x) | BIT_FW_FREE_TAIL_V1(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_CPU_MGQ_INFO			(Offset 0x041C) */
+
+#define BIT_SHIFT_FREE_TAIL_PAGE 0
+#define BIT_MASK_FREE_TAIL_PAGE 0xfff
+#define BIT_FREE_TAIL_PAGE(x)                                                  \
+	(((x) & BIT_MASK_FREE_TAIL_PAGE) << BIT_SHIFT_FREE_TAIL_PAGE)
+#define BITS_FREE_TAIL_PAGE                                                    \
+	(BIT_MASK_FREE_TAIL_PAGE << BIT_SHIFT_FREE_TAIL_PAGE)
+#define BIT_CLEAR_FREE_TAIL_PAGE(x) ((x) & (~BITS_FREE_TAIL_PAGE))
+#define BIT_GET_FREE_TAIL_PAGE(x)                                              \
+	(((x) >> BIT_SHIFT_FREE_TAIL_PAGE) & BIT_MASK_FREE_TAIL_PAGE)
+#define BIT_SET_FREE_TAIL_PAGE(x, v)                                           \
+	(BIT_CLEAR_FREE_TAIL_PAGE(x) | BIT_FREE_TAIL_PAGE(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_FWHW_TXQ_CTRL			(Offset 0x0420) */
+
+#define BIT_RTS_LIMIT_IN_OFDM BIT(23)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_FWHW_TXQ_CTRL			(Offset 0x0420) */
+
+#define BIT_EN_BCNQ_DL BIT(22)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_FWHW_TXQ_CTRL			(Offset 0x0420) */
+
+#define BIT_EN_RD_RESP_NAV_BK BIT(21)
+#define BIT_EN_WR_FREE_TAIL BIT(20)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_FWHW_TXQ_CTRL			(Offset 0x0420) */
+
+#define BIT_TXRPT_DIS BIT(19)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FWHW_TXQ_CTRL			(Offset 0x0420) */
+
+#define BIT_NOTXRPT_USERATE_EN BIT(19)
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FWHW_TXQ_CTRL			(Offset 0x0420) */
+
+#define BIT_DIS_TXFAIL_RPT BIT(18)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FWHW_TXQ_CTRL			(Offset 0x0420) */
+
+#define BIT_FTM_TIMEOUT_BYPASS BIT(16)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_FWHW_TXQ_CTRL			(Offset 0x0420) */
+
+#define BIT_EN_BCNQ_DL5 BIT(13)
+#define BIT_EN_BCNQ_DL4 BIT(12)
+#define BIT_EN_BCNQ_DL3 BIT(11)
+#define BIT_EN_BCNQ_DL2 BIT(10)
+#define BIT_EN_BCNQ_DL1 BIT(9)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_FWHW_TXQ_CTRL			(Offset 0x0420) */
+
+#define BIT_SHIFT_EN_QUEUE_RPT 8
+#define BIT_MASK_EN_QUEUE_RPT 0xff
+#define BIT_EN_QUEUE_RPT(x)                                                    \
+	(((x) & BIT_MASK_EN_QUEUE_RPT) << BIT_SHIFT_EN_QUEUE_RPT)
+#define BITS_EN_QUEUE_RPT (BIT_MASK_EN_QUEUE_RPT << BIT_SHIFT_EN_QUEUE_RPT)
+#define BIT_CLEAR_EN_QUEUE_RPT(x) ((x) & (~BITS_EN_QUEUE_RPT))
+#define BIT_GET_EN_QUEUE_RPT(x)                                                \
+	(((x) >> BIT_SHIFT_EN_QUEUE_RPT) & BIT_MASK_EN_QUEUE_RPT)
+#define BIT_SET_EN_QUEUE_RPT(x, v)                                             \
+	(BIT_CLEAR_EN_QUEUE_RPT(x) | BIT_EN_QUEUE_RPT(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_FWHW_TXQ_CTRL			(Offset 0x0420) */
+
+#define BIT_EN_BCNQ_DL0 BIT(8)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_FWHW_TXQ_CTRL			(Offset 0x0420) */
+
+#define BIT_EN_RTY_BK BIT(7)
+#define BIT_EN_USE_INI_RAT BIT(6)
+#define BIT_EN_RTS_NAV_BK BIT(5)
+#define BIT_DIS_SSN_CHECK BIT(4)
+#define BIT_MACID_MATCH_RTS BIT(3)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FWHW_TXQ_CTRL			(Offset 0x0420) */
+
+#define BIT_EN_BCN_TRXRPT_V1 BIT(2)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_FWHW_TXQ_CTRL			(Offset 0x0420) */
+
+#define BIT_R_EN_FTMRPT BIT(1)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FWHW_TXQ_CTRL			(Offset 0x0420) */
+
+#define BIT_R_EN_FTMRPT_V1 BIT(1)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_FWHW_TXQ_CTRL			(Offset 0x0420) */
+
+#define BIT_EN_FTMRPT_V1 BIT(1)
+
+#endif
+
+#if (HALMAC_8822B_SUPPORT)
+
+/* 2 REG_FWHW_TXQ_CTRL			(Offset 0x0420) */
+
+#define BIT_EN_FTMACKRPT BIT(1)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FWHW_TXQ_CTRL			(Offset 0x0420) */
+
+#define BIT_R_BMC_NAV_PROTECT BIT(0)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_FWHW_TXQ_CTRL			(Offset 0x0420) */
+
+#define BIT_BMC_NAV_PROTECT BIT(0)
+
+#endif
+
+#if (HALMAC_8822B_SUPPORT)
+
+/* 2 REG_FWHW_TXQ_CTRL			(Offset 0x0420) */
+
+#define BIT_EN_FTMRPT BIT(0)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_HWSEQ_CTRL				(Offset 0x0423) */
+
+#define BIT_HWSEQ_CPUM_EN BIT(7)
+#define BIT_HWSEQ_BCN_EN BIT(6)
+#define BIT_HWSEQ_HI_EN BIT(5)
+#define BIT_HWSEQ_MGT_EN BIT(4)
+#define BIT_HWSEQ_BK_EN BIT(3)
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+/* 2 REG_DATAFB_SEL				(Offset 0x0423) */
+
+#define BIT_R_BROADCAST_RETRY_EN BIT(3)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_DATAFB_SEL				(Offset 0x0423) */
+
+#define BIT_BROADCAST_RTY_EN BIT(3)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_HWSEQ_CTRL				(Offset 0x0423) */
+
+#define BIT_HWSEQ_BE_EN BIT(2)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_DATAFB_SEL				(Offset 0x0423) */
+
+#define BIT__R_EN_RTY_BK_COD BIT(2)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_DATAFB_SEL				(Offset 0x0423) */
+
+#define BIT_EN_RTY_BK_COD BIT(2)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_HWSEQ_CTRL				(Offset 0x0423) */
+
+#define BIT_HWSEQ_VI_EN BIT(1)
+#define BIT_HWSEQ_VO_EN BIT(0)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_DATAFB_SEL				(Offset 0x0423) */
+
+#define BIT_SHIFT__R_DATA_FALLBACK_SEL 0
+#define BIT_MASK__R_DATA_FALLBACK_SEL 0x3
+#define BIT__R_DATA_FALLBACK_SEL(x)                                            \
+	(((x) & BIT_MASK__R_DATA_FALLBACK_SEL)                                 \
+	 << BIT_SHIFT__R_DATA_FALLBACK_SEL)
+#define BITS__R_DATA_FALLBACK_SEL                                              \
+	(BIT_MASK__R_DATA_FALLBACK_SEL << BIT_SHIFT__R_DATA_FALLBACK_SEL)
+#define BIT_CLEAR__R_DATA_FALLBACK_SEL(x) ((x) & (~BITS__R_DATA_FALLBACK_SEL))
+#define BIT_GET__R_DATA_FALLBACK_SEL(x)                                        \
+	(((x) >> BIT_SHIFT__R_DATA_FALLBACK_SEL) &                             \
+	 BIT_MASK__R_DATA_FALLBACK_SEL)
+#define BIT_SET__R_DATA_FALLBACK_SEL(x, v)                                     \
+	(BIT_CLEAR__R_DATA_FALLBACK_SEL(x) | BIT__R_DATA_FALLBACK_SEL(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_DATAFB_SEL				(Offset 0x0423) */
+
+#define BIT_SHIFT__DATA_FALLBACK_SEL 0
+#define BIT_MASK__DATA_FALLBACK_SEL 0x3
+#define BIT__DATA_FALLBACK_SEL(x)                                              \
+	(((x) & BIT_MASK__DATA_FALLBACK_SEL) << BIT_SHIFT__DATA_FALLBACK_SEL)
+#define BITS__DATA_FALLBACK_SEL                                                \
+	(BIT_MASK__DATA_FALLBACK_SEL << BIT_SHIFT__DATA_FALLBACK_SEL)
+#define BIT_CLEAR__DATA_FALLBACK_SEL(x) ((x) & (~BITS__DATA_FALLBACK_SEL))
+#define BIT_GET__DATA_FALLBACK_SEL(x)                                          \
+	(((x) >> BIT_SHIFT__DATA_FALLBACK_SEL) & BIT_MASK__DATA_FALLBACK_SEL)
+#define BIT_SET__DATA_FALLBACK_SEL(x, v)                                       \
+	(BIT_CLEAR__DATA_FALLBACK_SEL(x) | BIT__DATA_FALLBACK_SEL(v))
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_BCNQ_BDNY				(Offset 0x0424) */
+
+#define BIT_SHIFT_MGQ_PGBNDY_V2 8
+#define BIT_MASK_MGQ_PGBNDY_V2 0xff
+#define BIT_MGQ_PGBNDY_V2(x)                                                   \
+	(((x) & BIT_MASK_MGQ_PGBNDY_V2) << BIT_SHIFT_MGQ_PGBNDY_V2)
+#define BITS_MGQ_PGBNDY_V2 (BIT_MASK_MGQ_PGBNDY_V2 << BIT_SHIFT_MGQ_PGBNDY_V2)
+#define BIT_CLEAR_MGQ_PGBNDY_V2(x) ((x) & (~BITS_MGQ_PGBNDY_V2))
+#define BIT_GET_MGQ_PGBNDY_V2(x)                                               \
+	(((x) >> BIT_SHIFT_MGQ_PGBNDY_V2) & BIT_MASK_MGQ_PGBNDY_V2)
+#define BIT_SET_MGQ_PGBNDY_V2(x, v)                                            \
+	(BIT_CLEAR_MGQ_PGBNDY_V2(x) | BIT_MGQ_PGBNDY_V2(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_BCNQ_BDNY				(Offset 0x0424) */
+
+#define BIT_SHIFT_BCNQ_PGBNDY 0
+#define BIT_MASK_BCNQ_PGBNDY 0xff
+#define BIT_BCNQ_PGBNDY(x)                                                     \
+	(((x) & BIT_MASK_BCNQ_PGBNDY) << BIT_SHIFT_BCNQ_PGBNDY)
+#define BITS_BCNQ_PGBNDY (BIT_MASK_BCNQ_PGBNDY << BIT_SHIFT_BCNQ_PGBNDY)
+#define BIT_CLEAR_BCNQ_PGBNDY(x) ((x) & (~BITS_BCNQ_PGBNDY))
+#define BIT_GET_BCNQ_PGBNDY(x)                                                 \
+	(((x) >> BIT_SHIFT_BCNQ_PGBNDY) & BIT_MASK_BCNQ_PGBNDY)
+#define BIT_SET_BCNQ_PGBNDY(x, v)                                              \
+	(BIT_CLEAR_BCNQ_PGBNDY(x) | BIT_BCNQ_PGBNDY(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_BCNQ_BDNY_V1			(Offset 0x0424) */
+
+#define BIT_SHIFT_BCNQ_PGBNDY_V1 0
+#define BIT_MASK_BCNQ_PGBNDY_V1 0xfff
+#define BIT_BCNQ_PGBNDY_V1(x)                                                  \
+	(((x) & BIT_MASK_BCNQ_PGBNDY_V1) << BIT_SHIFT_BCNQ_PGBNDY_V1)
+#define BITS_BCNQ_PGBNDY_V1                                                    \
+	(BIT_MASK_BCNQ_PGBNDY_V1 << BIT_SHIFT_BCNQ_PGBNDY_V1)
+#define BIT_CLEAR_BCNQ_PGBNDY_V1(x) ((x) & (~BITS_BCNQ_PGBNDY_V1))
+#define BIT_GET_BCNQ_PGBNDY_V1(x)                                              \
+	(((x) >> BIT_SHIFT_BCNQ_PGBNDY_V1) & BIT_MASK_BCNQ_PGBNDY_V1)
+#define BIT_SET_BCNQ_PGBNDY_V1(x, v)                                           \
+	(BIT_CLEAR_BCNQ_PGBNDY_V1(x) | BIT_BCNQ_PGBNDY_V1(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_TXBDNY				(Offset 0x0424) */
+
+#define BIT_SHIFT_TXBNDY 0
+#define BIT_MASK_TXBNDY 0xfff
+#define BIT_TXBNDY(x) (((x) & BIT_MASK_TXBNDY) << BIT_SHIFT_TXBNDY)
+#define BITS_TXBNDY (BIT_MASK_TXBNDY << BIT_SHIFT_TXBNDY)
+#define BIT_CLEAR_TXBNDY(x) ((x) & (~BITS_TXBNDY))
+#define BIT_GET_TXBNDY(x) (((x) >> BIT_SHIFT_TXBNDY) & BIT_MASK_TXBNDY)
+#define BIT_SET_TXBNDY(x, v) (BIT_CLEAR_TXBNDY(x) | BIT_TXBNDY(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_MGQ_BDNY				(Offset 0x0425) */
+
+#define BIT_SHIFT_MGQ_PGBNDY 0
+#define BIT_MASK_MGQ_PGBNDY 0xff
+#define BIT_MGQ_PGBNDY(x) (((x) & BIT_MASK_MGQ_PGBNDY) << BIT_SHIFT_MGQ_PGBNDY)
+#define BITS_MGQ_PGBNDY (BIT_MASK_MGQ_PGBNDY << BIT_SHIFT_MGQ_PGBNDY)
+#define BIT_CLEAR_MGQ_PGBNDY(x) ((x) & (~BITS_MGQ_PGBNDY))
+#define BIT_GET_MGQ_PGBNDY(x)                                                  \
+	(((x) >> BIT_SHIFT_MGQ_PGBNDY) & BIT_MASK_MGQ_PGBNDY)
+#define BIT_SET_MGQ_PGBNDY(x, v) (BIT_CLEAR_MGQ_PGBNDY(x) | BIT_MGQ_PGBNDY(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_LIFETIME_EN				(Offset 0x0426) */
+
+#define BIT_BT_INT_CPU BIT(7)
+#define BIT_BT_INT_PTA BIT(6)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_LIFETIME_EN				(Offset 0x0426) */
+
+#define BIT_SPERPT_ENTRY BIT(5)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_LIFETIME_EN				(Offset 0x0426) */
+
+#define BIT_RTYCNT_FB BIT(4)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_LIFETIME_EN				(Offset 0x0426) */
+
+#define BIT_EN_CTRL_RTYBIT BIT(4)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_LIFETIME_EN				(Offset 0x0426) */
+
+#define BIT_LIFETIME_BK_EN BIT(3)
+#define BIT_LIFETIME_BE_EN BIT(2)
+#define BIT_LIFETIME_VI_EN BIT(1)
+#define BIT_LIFETIME_VO_EN BIT(0)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_FW_FREE_TAIL			(Offset 0x0427) */
+
+#define BIT_SHIFT_FW_FREE_TAIL 0
+#define BIT_MASK_FW_FREE_TAIL 0xff
+#define BIT_FW_FREE_TAIL(x)                                                    \
+	(((x) & BIT_MASK_FW_FREE_TAIL) << BIT_SHIFT_FW_FREE_TAIL)
+#define BITS_FW_FREE_TAIL (BIT_MASK_FW_FREE_TAIL << BIT_SHIFT_FW_FREE_TAIL)
+#define BIT_CLEAR_FW_FREE_TAIL(x) ((x) & (~BITS_FW_FREE_TAIL))
+#define BIT_GET_FW_FREE_TAIL(x)                                                \
+	(((x) >> BIT_SHIFT_FW_FREE_TAIL) & BIT_MASK_FW_FREE_TAIL)
+#define BIT_SET_FW_FREE_TAIL(x, v)                                             \
+	(BIT_CLEAR_FW_FREE_TAIL(x) | BIT_FW_FREE_TAIL(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_SPEC_SIFS				(Offset 0x0428) */
+
+#define BIT_SHIFT_SPEC_SIFS_OFDM_PTCL 8
+#define BIT_MASK_SPEC_SIFS_OFDM_PTCL 0xff
+#define BIT_SPEC_SIFS_OFDM_PTCL(x)                                             \
+	(((x) & BIT_MASK_SPEC_SIFS_OFDM_PTCL) << BIT_SHIFT_SPEC_SIFS_OFDM_PTCL)
+#define BITS_SPEC_SIFS_OFDM_PTCL                                               \
+	(BIT_MASK_SPEC_SIFS_OFDM_PTCL << BIT_SHIFT_SPEC_SIFS_OFDM_PTCL)
+#define BIT_CLEAR_SPEC_SIFS_OFDM_PTCL(x) ((x) & (~BITS_SPEC_SIFS_OFDM_PTCL))
+#define BIT_GET_SPEC_SIFS_OFDM_PTCL(x)                                         \
+	(((x) >> BIT_SHIFT_SPEC_SIFS_OFDM_PTCL) & BIT_MASK_SPEC_SIFS_OFDM_PTCL)
+#define BIT_SET_SPEC_SIFS_OFDM_PTCL(x, v)                                      \
+	(BIT_CLEAR_SPEC_SIFS_OFDM_PTCL(x) | BIT_SPEC_SIFS_OFDM_PTCL(v))
+
+#define BIT_SHIFT_SPEC_SIFS_CCK_PTCL 0
+#define BIT_MASK_SPEC_SIFS_CCK_PTCL 0xff
+#define BIT_SPEC_SIFS_CCK_PTCL(x)                                              \
+	(((x) & BIT_MASK_SPEC_SIFS_CCK_PTCL) << BIT_SHIFT_SPEC_SIFS_CCK_PTCL)
+#define BITS_SPEC_SIFS_CCK_PTCL                                                \
+	(BIT_MASK_SPEC_SIFS_CCK_PTCL << BIT_SHIFT_SPEC_SIFS_CCK_PTCL)
+#define BIT_CLEAR_SPEC_SIFS_CCK_PTCL(x) ((x) & (~BITS_SPEC_SIFS_CCK_PTCL))
+#define BIT_GET_SPEC_SIFS_CCK_PTCL(x)                                          \
+	(((x) >> BIT_SHIFT_SPEC_SIFS_CCK_PTCL) & BIT_MASK_SPEC_SIFS_CCK_PTCL)
+#define BIT_SET_SPEC_SIFS_CCK_PTCL(x, v)                                       \
+	(BIT_CLEAR_SPEC_SIFS_CCK_PTCL(x) | BIT_SPEC_SIFS_CCK_PTCL(v))
+
+/* 2 REG_RETRY_LIMIT				(Offset 0x042A) */
+
+#define BIT_SHIFT_SRL 8
+#define BIT_MASK_SRL 0x3f
+#define BIT_SRL(x) (((x) & BIT_MASK_SRL) << BIT_SHIFT_SRL)
+#define BITS_SRL (BIT_MASK_SRL << BIT_SHIFT_SRL)
+#define BIT_CLEAR_SRL(x) ((x) & (~BITS_SRL))
+#define BIT_GET_SRL(x) (((x) >> BIT_SHIFT_SRL) & BIT_MASK_SRL)
+#define BIT_SET_SRL(x, v) (BIT_CLEAR_SRL(x) | BIT_SRL(v))
+
+#define BIT_SHIFT_LRL 0
+#define BIT_MASK_LRL 0x3f
+#define BIT_LRL(x) (((x) & BIT_MASK_LRL) << BIT_SHIFT_LRL)
+#define BITS_LRL (BIT_MASK_LRL << BIT_SHIFT_LRL)
+#define BIT_CLEAR_LRL(x) ((x) & (~BITS_LRL))
+#define BIT_GET_LRL(x) (((x) >> BIT_SHIFT_LRL) & BIT_MASK_LRL)
+#define BIT_SET_LRL(x, v) (BIT_CLEAR_LRL(x) | BIT_LRL(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8881A_SUPPORT)
+
+/* 2 REG_TXBF_CTRL				(Offset 0x042C) */
+
+#define BIT_R_ENABLE_NDPA BIT(31)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8814B_SUPPORT)
+
+/* 2 REG_TXBF_CTRL				(Offset 0x042C) */
+
+#define BIT_ENABLE_NDPA BIT(31)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8881A_SUPPORT)
+
+/* 2 REG_TXBF_CTRL				(Offset 0x042C) */
+
+#define BIT_USE_NDPA_PARAMETER BIT(30)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8814B_SUPPORT)
+
+/* 2 REG_TXBF_CTRL				(Offset 0x042C) */
+
+#define BIT_NDPA_PARA BIT(30)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8881A_SUPPORT)
+
+/* 2 REG_TXBF_CTRL				(Offset 0x042C) */
+
+#define BIT_R_PROP_TXBF BIT(29)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8814B_SUPPORT)
+
+/* 2 REG_TXBF_CTRL				(Offset 0x042C) */
+
+#define BIT_PROP_TXBF BIT(29)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8881A_SUPPORT)
+
+/* 2 REG_TXBF_CTRL				(Offset 0x042C) */
+
+#define BIT_R_EN_NDPA_INT BIT(28)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8814B_SUPPORT)
+
+/* 2 REG_TXBF_CTRL				(Offset 0x042C) */
+
+#define BIT_EN_NDPA_INT BIT(28)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8881A_SUPPORT)
+
+/* 2 REG_TXBF_CTRL				(Offset 0x042C) */
+
+#define BIT_R_TXBF1_80M BIT(27)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_TXBF_CTRL				(Offset 0x042C) */
+
+#define BIT_TXBF1_80M BIT(27)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_TXBF_CTRL				(Offset 0x042C) */
+
+#define BIT_TXBF1_80M_160M BIT(27)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8881A_SUPPORT)
+
+/* 2 REG_TXBF_CTRL				(Offset 0x042C) */
+
+#define BIT_R_TXBF1_40M BIT(26)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8814B_SUPPORT)
+
+/* 2 REG_TXBF_CTRL				(Offset 0x042C) */
+
+#define BIT_TXBF1_40M BIT(26)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8881A_SUPPORT)
+
+/* 2 REG_TXBF_CTRL				(Offset 0x042C) */
+
+#define BIT_R_TXBF1_20M BIT(25)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8814B_SUPPORT)
+
+/* 2 REG_TXBF_CTRL				(Offset 0x042C) */
+
+#define BIT_TXBF1_20M BIT(25)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8881A_SUPPORT)
+
+/* 2 REG_TXBF_CTRL				(Offset 0x042C) */
+
+#define BIT_SHIFT_R_TXBF1_AID 16
+#define BIT_MASK_R_TXBF1_AID 0x1ff
+#define BIT_R_TXBF1_AID(x)                                                     \
+	(((x) & BIT_MASK_R_TXBF1_AID) << BIT_SHIFT_R_TXBF1_AID)
+#define BITS_R_TXBF1_AID (BIT_MASK_R_TXBF1_AID << BIT_SHIFT_R_TXBF1_AID)
+#define BIT_CLEAR_R_TXBF1_AID(x) ((x) & (~BITS_R_TXBF1_AID))
+#define BIT_GET_R_TXBF1_AID(x)                                                 \
+	(((x) >> BIT_SHIFT_R_TXBF1_AID) & BIT_MASK_R_TXBF1_AID)
+#define BIT_SET_R_TXBF1_AID(x, v)                                              \
+	(BIT_CLEAR_R_TXBF1_AID(x) | BIT_R_TXBF1_AID(v))
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8814B_SUPPORT)
+
+/* 2 REG_TXBF_CTRL				(Offset 0x042C) */
+
+#define BIT_SHIFT_TXBF1_AID 16
+#define BIT_MASK_TXBF1_AID 0x1ff
+#define BIT_TXBF1_AID(x) (((x) & BIT_MASK_TXBF1_AID) << BIT_SHIFT_TXBF1_AID)
+#define BITS_TXBF1_AID (BIT_MASK_TXBF1_AID << BIT_SHIFT_TXBF1_AID)
+#define BIT_CLEAR_TXBF1_AID(x) ((x) & (~BITS_TXBF1_AID))
+#define BIT_GET_TXBF1_AID(x) (((x) >> BIT_SHIFT_TXBF1_AID) & BIT_MASK_TXBF1_AID)
+#define BIT_SET_TXBF1_AID(x, v) (BIT_CLEAR_TXBF1_AID(x) | BIT_TXBF1_AID(v))
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_TXBF_CTRL				(Offset 0x042C) */
+
+#define BIT_DIS_NDP_BFEN BIT(15)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8814B_SUPPORT)
+
+/* 2 REG_TXBF_CTRL				(Offset 0x042C) */
+
+#define BIT_TXBCN_NOBLOCK_NDP BIT(14)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_TXBF_CTRL				(Offset 0x042C) */
+
+#define BIT_R_TXBCN_NOBLOCK_NDP BIT(14)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8881A_SUPPORT)
+
+/* 2 REG_TXBF_CTRL				(Offset 0x042C) */
+
+#define BIT_R_TXBF0_80M BIT(11)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_TXBF_CTRL				(Offset 0x042C) */
+
+#define BIT_TXBF0_80M BIT(11)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_TXBF_CTRL				(Offset 0x042C) */
+
+#define BIT_TXBF0_80M_160M BIT(11)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8881A_SUPPORT)
+
+/* 2 REG_TXBF_CTRL				(Offset 0x042C) */
+
+#define BIT_R_TXBF0_40M BIT(10)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8814B_SUPPORT)
+
+/* 2 REG_TXBF_CTRL				(Offset 0x042C) */
+
+#define BIT_TXBF0_40M BIT(10)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8881A_SUPPORT)
+
+/* 2 REG_TXBF_CTRL				(Offset 0x042C) */
+
+#define BIT_R_TXBF0_20M BIT(9)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8814B_SUPPORT)
+
+/* 2 REG_TXBF_CTRL				(Offset 0x042C) */
+
+#define BIT_TXBF0_20M BIT(9)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8881A_SUPPORT)
+
+/* 2 REG_TXBF_CTRL				(Offset 0x042C) */
+
+#define BIT_SHIFT_R_TXBF0_AID 0
+#define BIT_MASK_R_TXBF0_AID 0x1ff
+#define BIT_R_TXBF0_AID(x)                                                     \
+	(((x) & BIT_MASK_R_TXBF0_AID) << BIT_SHIFT_R_TXBF0_AID)
+#define BITS_R_TXBF0_AID (BIT_MASK_R_TXBF0_AID << BIT_SHIFT_R_TXBF0_AID)
+#define BIT_CLEAR_R_TXBF0_AID(x) ((x) & (~BITS_R_TXBF0_AID))
+#define BIT_GET_R_TXBF0_AID(x)                                                 \
+	(((x) >> BIT_SHIFT_R_TXBF0_AID) & BIT_MASK_R_TXBF0_AID)
+#define BIT_SET_R_TXBF0_AID(x, v)                                              \
+	(BIT_CLEAR_R_TXBF0_AID(x) | BIT_R_TXBF0_AID(v))
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8814B_SUPPORT)
+
+/* 2 REG_TXBF_CTRL				(Offset 0x042C) */
+
+#define BIT_SHIFT_TXBF0_AID 0
+#define BIT_MASK_TXBF0_AID 0x1ff
+#define BIT_TXBF0_AID(x) (((x) & BIT_MASK_TXBF0_AID) << BIT_SHIFT_TXBF0_AID)
+#define BITS_TXBF0_AID (BIT_MASK_TXBF0_AID << BIT_SHIFT_TXBF0_AID)
+#define BIT_CLEAR_TXBF0_AID(x) ((x) & (~BITS_TXBF0_AID))
+#define BIT_GET_TXBF0_AID(x) (((x) >> BIT_SHIFT_TXBF0_AID) & BIT_MASK_TXBF0_AID)
+#define BIT_SET_TXBF0_AID(x, v) (BIT_CLEAR_TXBF0_AID(x) | BIT_TXBF0_AID(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_DARFRC				(Offset 0x0430) */
+
+#define BIT_SHIFT_DARF_RC8 (56 & CPU_OPT_WIDTH)
+#define BIT_MASK_DARF_RC8 0x1f
+#define BIT_DARF_RC8(x) (((x) & BIT_MASK_DARF_RC8) << BIT_SHIFT_DARF_RC8)
+#define BITS_DARF_RC8 (BIT_MASK_DARF_RC8 << BIT_SHIFT_DARF_RC8)
+#define BIT_CLEAR_DARF_RC8(x) ((x) & (~BITS_DARF_RC8))
+#define BIT_GET_DARF_RC8(x) (((x) >> BIT_SHIFT_DARF_RC8) & BIT_MASK_DARF_RC8)
+#define BIT_SET_DARF_RC8(x, v) (BIT_CLEAR_DARF_RC8(x) | BIT_DARF_RC8(v))
+
+#define BIT_SHIFT_DARF_RC7 (48 & CPU_OPT_WIDTH)
+#define BIT_MASK_DARF_RC7 0x1f
+#define BIT_DARF_RC7(x) (((x) & BIT_MASK_DARF_RC7) << BIT_SHIFT_DARF_RC7)
+#define BITS_DARF_RC7 (BIT_MASK_DARF_RC7 << BIT_SHIFT_DARF_RC7)
+#define BIT_CLEAR_DARF_RC7(x) ((x) & (~BITS_DARF_RC7))
+#define BIT_GET_DARF_RC7(x) (((x) >> BIT_SHIFT_DARF_RC7) & BIT_MASK_DARF_RC7)
+#define BIT_SET_DARF_RC7(x, v) (BIT_CLEAR_DARF_RC7(x) | BIT_DARF_RC7(v))
+
+#define BIT_SHIFT_DARF_RC6 (40 & CPU_OPT_WIDTH)
+#define BIT_MASK_DARF_RC6 0x1f
+#define BIT_DARF_RC6(x) (((x) & BIT_MASK_DARF_RC6) << BIT_SHIFT_DARF_RC6)
+#define BITS_DARF_RC6 (BIT_MASK_DARF_RC6 << BIT_SHIFT_DARF_RC6)
+#define BIT_CLEAR_DARF_RC6(x) ((x) & (~BITS_DARF_RC6))
+#define BIT_GET_DARF_RC6(x) (((x) >> BIT_SHIFT_DARF_RC6) & BIT_MASK_DARF_RC6)
+#define BIT_SET_DARF_RC6(x, v) (BIT_CLEAR_DARF_RC6(x) | BIT_DARF_RC6(v))
+
+#define BIT_SHIFT_DARF_RC5 (32 & CPU_OPT_WIDTH)
+#define BIT_MASK_DARF_RC5 0x1f
+#define BIT_DARF_RC5(x) (((x) & BIT_MASK_DARF_RC5) << BIT_SHIFT_DARF_RC5)
+#define BITS_DARF_RC5 (BIT_MASK_DARF_RC5 << BIT_SHIFT_DARF_RC5)
+#define BIT_CLEAR_DARF_RC5(x) ((x) & (~BITS_DARF_RC5))
+#define BIT_GET_DARF_RC5(x) (((x) >> BIT_SHIFT_DARF_RC5) & BIT_MASK_DARF_RC5)
+#define BIT_SET_DARF_RC5(x, v) (BIT_CLEAR_DARF_RC5(x) | BIT_DARF_RC5(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_DARFRC				(Offset 0x0430) */
+
+#define BIT_SHIFT_DARF_RC4 24
+#define BIT_MASK_DARF_RC4 0x1f
+#define BIT_DARF_RC4(x) (((x) & BIT_MASK_DARF_RC4) << BIT_SHIFT_DARF_RC4)
+#define BITS_DARF_RC4 (BIT_MASK_DARF_RC4 << BIT_SHIFT_DARF_RC4)
+#define BIT_CLEAR_DARF_RC4(x) ((x) & (~BITS_DARF_RC4))
+#define BIT_GET_DARF_RC4(x) (((x) >> BIT_SHIFT_DARF_RC4) & BIT_MASK_DARF_RC4)
+#define BIT_SET_DARF_RC4(x, v) (BIT_CLEAR_DARF_RC4(x) | BIT_DARF_RC4(v))
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_DARFRC				(Offset 0x0430) */
+
+#define BIT_SHIFT_DARF_RC4_V2 24
+#define BIT_MASK_DARF_RC4_V2 0x1f
+#define BIT_DARF_RC4_V2(x)                                                     \
+	(((x) & BIT_MASK_DARF_RC4_V2) << BIT_SHIFT_DARF_RC4_V2)
+#define BITS_DARF_RC4_V2 (BIT_MASK_DARF_RC4_V2 << BIT_SHIFT_DARF_RC4_V2)
+#define BIT_CLEAR_DARF_RC4_V2(x) ((x) & (~BITS_DARF_RC4_V2))
+#define BIT_GET_DARF_RC4_V2(x)                                                 \
+	(((x) >> BIT_SHIFT_DARF_RC4_V2) & BIT_MASK_DARF_RC4_V2)
+#define BIT_SET_DARF_RC4_V2(x, v)                                              \
+	(BIT_CLEAR_DARF_RC4_V2(x) | BIT_DARF_RC4_V2(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT)
+
+/* 2 REG_DARFRC				(Offset 0x0430) */
+
+#define BIT_SHIFT_DARF_RC4_V1 24
+#define BIT_MASK_DARF_RC4_V1 0x3f
+#define BIT_DARF_RC4_V1(x)                                                     \
+	(((x) & BIT_MASK_DARF_RC4_V1) << BIT_SHIFT_DARF_RC4_V1)
+#define BITS_DARF_RC4_V1 (BIT_MASK_DARF_RC4_V1 << BIT_SHIFT_DARF_RC4_V1)
+#define BIT_CLEAR_DARF_RC4_V1(x) ((x) & (~BITS_DARF_RC4_V1))
+#define BIT_GET_DARF_RC4_V1(x)                                                 \
+	(((x) >> BIT_SHIFT_DARF_RC4_V1) & BIT_MASK_DARF_RC4_V1)
+#define BIT_SET_DARF_RC4_V1(x, v)                                              \
+	(BIT_CLEAR_DARF_RC4_V1(x) | BIT_DARF_RC4_V1(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_DARFRC				(Offset 0x0430) */
+
+#define BIT_SHIFT_DARF_RC3 16
+#define BIT_MASK_DARF_RC3 0x1f
+#define BIT_DARF_RC3(x) (((x) & BIT_MASK_DARF_RC3) << BIT_SHIFT_DARF_RC3)
+#define BITS_DARF_RC3 (BIT_MASK_DARF_RC3 << BIT_SHIFT_DARF_RC3)
+#define BIT_CLEAR_DARF_RC3(x) ((x) & (~BITS_DARF_RC3))
+#define BIT_GET_DARF_RC3(x) (((x) >> BIT_SHIFT_DARF_RC3) & BIT_MASK_DARF_RC3)
+#define BIT_SET_DARF_RC3(x, v) (BIT_CLEAR_DARF_RC3(x) | BIT_DARF_RC3(v))
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_DARFRC				(Offset 0x0430) */
+
+#define BIT_SHIFT_DARF_RC3_V2 16
+#define BIT_MASK_DARF_RC3_V2 0x1f
+#define BIT_DARF_RC3_V2(x)                                                     \
+	(((x) & BIT_MASK_DARF_RC3_V2) << BIT_SHIFT_DARF_RC3_V2)
+#define BITS_DARF_RC3_V2 (BIT_MASK_DARF_RC3_V2 << BIT_SHIFT_DARF_RC3_V2)
+#define BIT_CLEAR_DARF_RC3_V2(x) ((x) & (~BITS_DARF_RC3_V2))
+#define BIT_GET_DARF_RC3_V2(x)                                                 \
+	(((x) >> BIT_SHIFT_DARF_RC3_V2) & BIT_MASK_DARF_RC3_V2)
+#define BIT_SET_DARF_RC3_V2(x, v)                                              \
+	(BIT_CLEAR_DARF_RC3_V2(x) | BIT_DARF_RC3_V2(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT)
+
+/* 2 REG_DARFRC				(Offset 0x0430) */
+
+#define BIT_SHIFT_DARF_RC3_V1 16
+#define BIT_MASK_DARF_RC3_V1 0x3f
+#define BIT_DARF_RC3_V1(x)                                                     \
+	(((x) & BIT_MASK_DARF_RC3_V1) << BIT_SHIFT_DARF_RC3_V1)
+#define BITS_DARF_RC3_V1 (BIT_MASK_DARF_RC3_V1 << BIT_SHIFT_DARF_RC3_V1)
+#define BIT_CLEAR_DARF_RC3_V1(x) ((x) & (~BITS_DARF_RC3_V1))
+#define BIT_GET_DARF_RC3_V1(x)                                                 \
+	(((x) >> BIT_SHIFT_DARF_RC3_V1) & BIT_MASK_DARF_RC3_V1)
+#define BIT_SET_DARF_RC3_V1(x, v)                                              \
+	(BIT_CLEAR_DARF_RC3_V1(x) | BIT_DARF_RC3_V1(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_DARFRC				(Offset 0x0430) */
+
+#define BIT_SHIFT_DARF_RC2 8
+#define BIT_MASK_DARF_RC2 0x1f
+#define BIT_DARF_RC2(x) (((x) & BIT_MASK_DARF_RC2) << BIT_SHIFT_DARF_RC2)
+#define BITS_DARF_RC2 (BIT_MASK_DARF_RC2 << BIT_SHIFT_DARF_RC2)
+#define BIT_CLEAR_DARF_RC2(x) ((x) & (~BITS_DARF_RC2))
+#define BIT_GET_DARF_RC2(x) (((x) >> BIT_SHIFT_DARF_RC2) & BIT_MASK_DARF_RC2)
+#define BIT_SET_DARF_RC2(x, v) (BIT_CLEAR_DARF_RC2(x) | BIT_DARF_RC2(v))
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_DARFRC				(Offset 0x0430) */
+
+#define BIT_SHIFT_DARF_RC2_V2 8
+#define BIT_MASK_DARF_RC2_V2 0x1f
+#define BIT_DARF_RC2_V2(x)                                                     \
+	(((x) & BIT_MASK_DARF_RC2_V2) << BIT_SHIFT_DARF_RC2_V2)
+#define BITS_DARF_RC2_V2 (BIT_MASK_DARF_RC2_V2 << BIT_SHIFT_DARF_RC2_V2)
+#define BIT_CLEAR_DARF_RC2_V2(x) ((x) & (~BITS_DARF_RC2_V2))
+#define BIT_GET_DARF_RC2_V2(x)                                                 \
+	(((x) >> BIT_SHIFT_DARF_RC2_V2) & BIT_MASK_DARF_RC2_V2)
+#define BIT_SET_DARF_RC2_V2(x, v)                                              \
+	(BIT_CLEAR_DARF_RC2_V2(x) | BIT_DARF_RC2_V2(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT)
+
+/* 2 REG_DARFRC				(Offset 0x0430) */
+
+#define BIT_SHIFT_DARF_RC2_V1 8
+#define BIT_MASK_DARF_RC2_V1 0x3f
+#define BIT_DARF_RC2_V1(x)                                                     \
+	(((x) & BIT_MASK_DARF_RC2_V1) << BIT_SHIFT_DARF_RC2_V1)
+#define BITS_DARF_RC2_V1 (BIT_MASK_DARF_RC2_V1 << BIT_SHIFT_DARF_RC2_V1)
+#define BIT_CLEAR_DARF_RC2_V1(x) ((x) & (~BITS_DARF_RC2_V1))
+#define BIT_GET_DARF_RC2_V1(x)                                                 \
+	(((x) >> BIT_SHIFT_DARF_RC2_V1) & BIT_MASK_DARF_RC2_V1)
+#define BIT_SET_DARF_RC2_V1(x, v)                                              \
+	(BIT_CLEAR_DARF_RC2_V1(x) | BIT_DARF_RC2_V1(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_DARFRC				(Offset 0x0430) */
+
+#define BIT_SHIFT_DARF_RC1 0
+#define BIT_MASK_DARF_RC1 0x1f
+#define BIT_DARF_RC1(x) (((x) & BIT_MASK_DARF_RC1) << BIT_SHIFT_DARF_RC1)
+#define BITS_DARF_RC1 (BIT_MASK_DARF_RC1 << BIT_SHIFT_DARF_RC1)
+#define BIT_CLEAR_DARF_RC1(x) ((x) & (~BITS_DARF_RC1))
+#define BIT_GET_DARF_RC1(x) (((x) >> BIT_SHIFT_DARF_RC1) & BIT_MASK_DARF_RC1)
+#define BIT_SET_DARF_RC1(x, v) (BIT_CLEAR_DARF_RC1(x) | BIT_DARF_RC1(v))
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_DARFRC				(Offset 0x0430) */
+
+#define BIT_SHIFT_DARF_RC1_V2 0
+#define BIT_MASK_DARF_RC1_V2 0x1f
+#define BIT_DARF_RC1_V2(x)                                                     \
+	(((x) & BIT_MASK_DARF_RC1_V2) << BIT_SHIFT_DARF_RC1_V2)
+#define BITS_DARF_RC1_V2 (BIT_MASK_DARF_RC1_V2 << BIT_SHIFT_DARF_RC1_V2)
+#define BIT_CLEAR_DARF_RC1_V2(x) ((x) & (~BITS_DARF_RC1_V2))
+#define BIT_GET_DARF_RC1_V2(x)                                                 \
+	(((x) >> BIT_SHIFT_DARF_RC1_V2) & BIT_MASK_DARF_RC1_V2)
+#define BIT_SET_DARF_RC1_V2(x, v)                                              \
+	(BIT_CLEAR_DARF_RC1_V2(x) | BIT_DARF_RC1_V2(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT)
+
+/* 2 REG_DARFRC				(Offset 0x0430) */
+
+#define BIT_SHIFT_DARF_RC1_V1 0
+#define BIT_MASK_DARF_RC1_V1 0x3f
+#define BIT_DARF_RC1_V1(x)                                                     \
+	(((x) & BIT_MASK_DARF_RC1_V1) << BIT_SHIFT_DARF_RC1_V1)
+#define BITS_DARF_RC1_V1 (BIT_MASK_DARF_RC1_V1 << BIT_SHIFT_DARF_RC1_V1)
+#define BIT_CLEAR_DARF_RC1_V1(x) ((x) & (~BITS_DARF_RC1_V1))
+#define BIT_GET_DARF_RC1_V1(x)                                                 \
+	(((x) >> BIT_SHIFT_DARF_RC1_V1) & BIT_MASK_DARF_RC1_V1)
+#define BIT_SET_DARF_RC1_V1(x, v)                                              \
+	(BIT_CLEAR_DARF_RC1_V1(x) | BIT_DARF_RC1_V1(v))
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_DARFRCH				(Offset 0x0434) */
+
+#define BIT_SHIFT_DARF_RC8_V3 24
+#define BIT_MASK_DARF_RC8_V3 0x1f
+#define BIT_DARF_RC8_V3(x)                                                     \
+	(((x) & BIT_MASK_DARF_RC8_V3) << BIT_SHIFT_DARF_RC8_V3)
+#define BITS_DARF_RC8_V3 (BIT_MASK_DARF_RC8_V3 << BIT_SHIFT_DARF_RC8_V3)
+#define BIT_CLEAR_DARF_RC8_V3(x) ((x) & (~BITS_DARF_RC8_V3))
+#define BIT_GET_DARF_RC8_V3(x)                                                 \
+	(((x) >> BIT_SHIFT_DARF_RC8_V3) & BIT_MASK_DARF_RC8_V3)
+#define BIT_SET_DARF_RC8_V3(x, v)                                              \
+	(BIT_CLEAR_DARF_RC8_V3(x) | BIT_DARF_RC8_V3(v))
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_DARFRCH				(Offset 0x0434) */
+
+#define BIT_SHIFT_DARF_RC8_V1 24
+#define BIT_MASK_DARF_RC8_V1 0x1f
+#define BIT_DARF_RC8_V1(x)                                                     \
+	(((x) & BIT_MASK_DARF_RC8_V1) << BIT_SHIFT_DARF_RC8_V1)
+#define BITS_DARF_RC8_V1 (BIT_MASK_DARF_RC8_V1 << BIT_SHIFT_DARF_RC8_V1)
+#define BIT_CLEAR_DARF_RC8_V1(x) ((x) & (~BITS_DARF_RC8_V1))
+#define BIT_GET_DARF_RC8_V1(x)                                                 \
+	(((x) >> BIT_SHIFT_DARF_RC8_V1) & BIT_MASK_DARF_RC8_V1)
+#define BIT_SET_DARF_RC8_V1(x, v)                                              \
+	(BIT_CLEAR_DARF_RC8_V1(x) | BIT_DARF_RC8_V1(v))
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_DARFRCH				(Offset 0x0434) */
+
+#define BIT_SHIFT_DARF_RC7_V3 16
+#define BIT_MASK_DARF_RC7_V3 0x1f
+#define BIT_DARF_RC7_V3(x)                                                     \
+	(((x) & BIT_MASK_DARF_RC7_V3) << BIT_SHIFT_DARF_RC7_V3)
+#define BITS_DARF_RC7_V3 (BIT_MASK_DARF_RC7_V3 << BIT_SHIFT_DARF_RC7_V3)
+#define BIT_CLEAR_DARF_RC7_V3(x) ((x) & (~BITS_DARF_RC7_V3))
+#define BIT_GET_DARF_RC7_V3(x)                                                 \
+	(((x) >> BIT_SHIFT_DARF_RC7_V3) & BIT_MASK_DARF_RC7_V3)
+#define BIT_SET_DARF_RC7_V3(x, v)                                              \
+	(BIT_CLEAR_DARF_RC7_V3(x) | BIT_DARF_RC7_V3(v))
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_DARFRCH				(Offset 0x0434) */
+
+#define BIT_SHIFT_DARF_RC7_V1 16
+#define BIT_MASK_DARF_RC7_V1 0x1f
+#define BIT_DARF_RC7_V1(x)                                                     \
+	(((x) & BIT_MASK_DARF_RC7_V1) << BIT_SHIFT_DARF_RC7_V1)
+#define BITS_DARF_RC7_V1 (BIT_MASK_DARF_RC7_V1 << BIT_SHIFT_DARF_RC7_V1)
+#define BIT_CLEAR_DARF_RC7_V1(x) ((x) & (~BITS_DARF_RC7_V1))
+#define BIT_GET_DARF_RC7_V1(x)                                                 \
+	(((x) >> BIT_SHIFT_DARF_RC7_V1) & BIT_MASK_DARF_RC7_V1)
+#define BIT_SET_DARF_RC7_V1(x, v)                                              \
+	(BIT_CLEAR_DARF_RC7_V1(x) | BIT_DARF_RC7_V1(v))
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_DARFRCH				(Offset 0x0434) */
+
+#define BIT_SHIFT_DARF_RC6_V3 8
+#define BIT_MASK_DARF_RC6_V3 0x1f
+#define BIT_DARF_RC6_V3(x)                                                     \
+	(((x) & BIT_MASK_DARF_RC6_V3) << BIT_SHIFT_DARF_RC6_V3)
+#define BITS_DARF_RC6_V3 (BIT_MASK_DARF_RC6_V3 << BIT_SHIFT_DARF_RC6_V3)
+#define BIT_CLEAR_DARF_RC6_V3(x) ((x) & (~BITS_DARF_RC6_V3))
+#define BIT_GET_DARF_RC6_V3(x)                                                 \
+	(((x) >> BIT_SHIFT_DARF_RC6_V3) & BIT_MASK_DARF_RC6_V3)
+#define BIT_SET_DARF_RC6_V3(x, v)                                              \
+	(BIT_CLEAR_DARF_RC6_V3(x) | BIT_DARF_RC6_V3(v))
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_DARFRCH				(Offset 0x0434) */
+
+#define BIT_SHIFT_DARF_RC6_V1 8
+#define BIT_MASK_DARF_RC6_V1 0x1f
+#define BIT_DARF_RC6_V1(x)                                                     \
+	(((x) & BIT_MASK_DARF_RC6_V1) << BIT_SHIFT_DARF_RC6_V1)
+#define BITS_DARF_RC6_V1 (BIT_MASK_DARF_RC6_V1 << BIT_SHIFT_DARF_RC6_V1)
+#define BIT_CLEAR_DARF_RC6_V1(x) ((x) & (~BITS_DARF_RC6_V1))
+#define BIT_GET_DARF_RC6_V1(x)                                                 \
+	(((x) >> BIT_SHIFT_DARF_RC6_V1) & BIT_MASK_DARF_RC6_V1)
+#define BIT_SET_DARF_RC6_V1(x, v)                                              \
+	(BIT_CLEAR_DARF_RC6_V1(x) | BIT_DARF_RC6_V1(v))
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_DARFRCH				(Offset 0x0434) */
+
+#define BIT_SHIFT_DARF_RC5_V3 0
+#define BIT_MASK_DARF_RC5_V3 0x1f
+#define BIT_DARF_RC5_V3(x)                                                     \
+	(((x) & BIT_MASK_DARF_RC5_V3) << BIT_SHIFT_DARF_RC5_V3)
+#define BITS_DARF_RC5_V3 (BIT_MASK_DARF_RC5_V3 << BIT_SHIFT_DARF_RC5_V3)
+#define BIT_CLEAR_DARF_RC5_V3(x) ((x) & (~BITS_DARF_RC5_V3))
+#define BIT_GET_DARF_RC5_V3(x)                                                 \
+	(((x) >> BIT_SHIFT_DARF_RC5_V3) & BIT_MASK_DARF_RC5_V3)
+#define BIT_SET_DARF_RC5_V3(x, v)                                              \
+	(BIT_CLEAR_DARF_RC5_V3(x) | BIT_DARF_RC5_V3(v))
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_DARFRCH				(Offset 0x0434) */
+
+#define BIT_SHIFT_DARF_RC5_V1 0
+#define BIT_MASK_DARF_RC5_V1 0x1f
+#define BIT_DARF_RC5_V1(x)                                                     \
+	(((x) & BIT_MASK_DARF_RC5_V1) << BIT_SHIFT_DARF_RC5_V1)
+#define BITS_DARF_RC5_V1 (BIT_MASK_DARF_RC5_V1 << BIT_SHIFT_DARF_RC5_V1)
+#define BIT_CLEAR_DARF_RC5_V1(x) ((x) & (~BITS_DARF_RC5_V1))
+#define BIT_GET_DARF_RC5_V1(x)                                                 \
+	(((x) >> BIT_SHIFT_DARF_RC5_V1) & BIT_MASK_DARF_RC5_V1)
+#define BIT_SET_DARF_RC5_V1(x, v)                                              \
+	(BIT_CLEAR_DARF_RC5_V1(x) | BIT_DARF_RC5_V1(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT || \
+     HALMAC_8881A_SUPPORT)
+
+/* 2 REG_RARFRC				(Offset 0x0438) */
+
+#define BIT_SHIFT_RARF_RC8 (56 & CPU_OPT_WIDTH)
+#define BIT_MASK_RARF_RC8 0x1f
+#define BIT_RARF_RC8(x) (((x) & BIT_MASK_RARF_RC8) << BIT_SHIFT_RARF_RC8)
+#define BITS_RARF_RC8 (BIT_MASK_RARF_RC8 << BIT_SHIFT_RARF_RC8)
+#define BIT_CLEAR_RARF_RC8(x) ((x) & (~BITS_RARF_RC8))
+#define BIT_GET_RARF_RC8(x) (((x) >> BIT_SHIFT_RARF_RC8) & BIT_MASK_RARF_RC8)
+#define BIT_SET_RARF_RC8(x, v) (BIT_CLEAR_RARF_RC8(x) | BIT_RARF_RC8(v))
+
+#define BIT_SHIFT_RARF_RC7 (48 & CPU_OPT_WIDTH)
+#define BIT_MASK_RARF_RC7 0x1f
+#define BIT_RARF_RC7(x) (((x) & BIT_MASK_RARF_RC7) << BIT_SHIFT_RARF_RC7)
+#define BITS_RARF_RC7 (BIT_MASK_RARF_RC7 << BIT_SHIFT_RARF_RC7)
+#define BIT_CLEAR_RARF_RC7(x) ((x) & (~BITS_RARF_RC7))
+#define BIT_GET_RARF_RC7(x) (((x) >> BIT_SHIFT_RARF_RC7) & BIT_MASK_RARF_RC7)
+#define BIT_SET_RARF_RC7(x, v) (BIT_CLEAR_RARF_RC7(x) | BIT_RARF_RC7(v))
+
+#define BIT_SHIFT_RARF_RC6 (40 & CPU_OPT_WIDTH)
+#define BIT_MASK_RARF_RC6 0x1f
+#define BIT_RARF_RC6(x) (((x) & BIT_MASK_RARF_RC6) << BIT_SHIFT_RARF_RC6)
+#define BITS_RARF_RC6 (BIT_MASK_RARF_RC6 << BIT_SHIFT_RARF_RC6)
+#define BIT_CLEAR_RARF_RC6(x) ((x) & (~BITS_RARF_RC6))
+#define BIT_GET_RARF_RC6(x) (((x) >> BIT_SHIFT_RARF_RC6) & BIT_MASK_RARF_RC6)
+#define BIT_SET_RARF_RC6(x, v) (BIT_CLEAR_RARF_RC6(x) | BIT_RARF_RC6(v))
+
+#define BIT_SHIFT_RARF_RC5 (32 & CPU_OPT_WIDTH)
+#define BIT_MASK_RARF_RC5 0x1f
+#define BIT_RARF_RC5(x) (((x) & BIT_MASK_RARF_RC5) << BIT_SHIFT_RARF_RC5)
+#define BITS_RARF_RC5 (BIT_MASK_RARF_RC5 << BIT_SHIFT_RARF_RC5)
+#define BIT_CLEAR_RARF_RC5(x) ((x) & (~BITS_RARF_RC5))
+#define BIT_GET_RARF_RC5(x) (((x) >> BIT_SHIFT_RARF_RC5) & BIT_MASK_RARF_RC5)
+#define BIT_SET_RARF_RC5(x, v) (BIT_CLEAR_RARF_RC5(x) | BIT_RARF_RC5(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_RARFRC				(Offset 0x0438) */
+
+#define BIT_SHIFT_RARF_RC4 24
+#define BIT_MASK_RARF_RC4 0x1f
+#define BIT_RARF_RC4(x) (((x) & BIT_MASK_RARF_RC4) << BIT_SHIFT_RARF_RC4)
+#define BITS_RARF_RC4 (BIT_MASK_RARF_RC4 << BIT_SHIFT_RARF_RC4)
+#define BIT_CLEAR_RARF_RC4(x) ((x) & (~BITS_RARF_RC4))
+#define BIT_GET_RARF_RC4(x) (((x) >> BIT_SHIFT_RARF_RC4) & BIT_MASK_RARF_RC4)
+#define BIT_SET_RARF_RC4(x, v) (BIT_CLEAR_RARF_RC4(x) | BIT_RARF_RC4(v))
+
+#define BIT_SHIFT_RARF_RC3 16
+#define BIT_MASK_RARF_RC3 0x1f
+#define BIT_RARF_RC3(x) (((x) & BIT_MASK_RARF_RC3) << BIT_SHIFT_RARF_RC3)
+#define BITS_RARF_RC3 (BIT_MASK_RARF_RC3 << BIT_SHIFT_RARF_RC3)
+#define BIT_CLEAR_RARF_RC3(x) ((x) & (~BITS_RARF_RC3))
+#define BIT_GET_RARF_RC3(x) (((x) >> BIT_SHIFT_RARF_RC3) & BIT_MASK_RARF_RC3)
+#define BIT_SET_RARF_RC3(x, v) (BIT_CLEAR_RARF_RC3(x) | BIT_RARF_RC3(v))
+
+#define BIT_SHIFT_RARF_RC2 8
+#define BIT_MASK_RARF_RC2 0x1f
+#define BIT_RARF_RC2(x) (((x) & BIT_MASK_RARF_RC2) << BIT_SHIFT_RARF_RC2)
+#define BITS_RARF_RC2 (BIT_MASK_RARF_RC2 << BIT_SHIFT_RARF_RC2)
+#define BIT_CLEAR_RARF_RC2(x) ((x) & (~BITS_RARF_RC2))
+#define BIT_GET_RARF_RC2(x) (((x) >> BIT_SHIFT_RARF_RC2) & BIT_MASK_RARF_RC2)
+#define BIT_SET_RARF_RC2(x, v) (BIT_CLEAR_RARF_RC2(x) | BIT_RARF_RC2(v))
+
+#define BIT_SHIFT_RARF_RC1 0
+#define BIT_MASK_RARF_RC1 0x1f
+#define BIT_RARF_RC1(x) (((x) & BIT_MASK_RARF_RC1) << BIT_SHIFT_RARF_RC1)
+#define BITS_RARF_RC1 (BIT_MASK_RARF_RC1 << BIT_SHIFT_RARF_RC1)
+#define BIT_CLEAR_RARF_RC1(x) ((x) & (~BITS_RARF_RC1))
+#define BIT_GET_RARF_RC1(x) (((x) >> BIT_SHIFT_RARF_RC1) & BIT_MASK_RARF_RC1)
+#define BIT_SET_RARF_RC1(x, v) (BIT_CLEAR_RARF_RC1(x) | BIT_RARF_RC1(v))
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_RARFRCH				(Offset 0x043C) */
+
+#define BIT_SHIFT_RARF_RC8_V1 24
+#define BIT_MASK_RARF_RC8_V1 0x1f
+#define BIT_RARF_RC8_V1(x)                                                     \
+	(((x) & BIT_MASK_RARF_RC8_V1) << BIT_SHIFT_RARF_RC8_V1)
+#define BITS_RARF_RC8_V1 (BIT_MASK_RARF_RC8_V1 << BIT_SHIFT_RARF_RC8_V1)
+#define BIT_CLEAR_RARF_RC8_V1(x) ((x) & (~BITS_RARF_RC8_V1))
+#define BIT_GET_RARF_RC8_V1(x)                                                 \
+	(((x) >> BIT_SHIFT_RARF_RC8_V1) & BIT_MASK_RARF_RC8_V1)
+#define BIT_SET_RARF_RC8_V1(x, v)                                              \
+	(BIT_CLEAR_RARF_RC8_V1(x) | BIT_RARF_RC8_V1(v))
+
+#define BIT_SHIFT_RARF_RC7_V1 16
+#define BIT_MASK_RARF_RC7_V1 0x1f
+#define BIT_RARF_RC7_V1(x)                                                     \
+	(((x) & BIT_MASK_RARF_RC7_V1) << BIT_SHIFT_RARF_RC7_V1)
+#define BITS_RARF_RC7_V1 (BIT_MASK_RARF_RC7_V1 << BIT_SHIFT_RARF_RC7_V1)
+#define BIT_CLEAR_RARF_RC7_V1(x) ((x) & (~BITS_RARF_RC7_V1))
+#define BIT_GET_RARF_RC7_V1(x)                                                 \
+	(((x) >> BIT_SHIFT_RARF_RC7_V1) & BIT_MASK_RARF_RC7_V1)
+#define BIT_SET_RARF_RC7_V1(x, v)                                              \
+	(BIT_CLEAR_RARF_RC7_V1(x) | BIT_RARF_RC7_V1(v))
+
+#define BIT_SHIFT_RARF_RC6_V1 8
+#define BIT_MASK_RARF_RC6_V1 0x1f
+#define BIT_RARF_RC6_V1(x)                                                     \
+	(((x) & BIT_MASK_RARF_RC6_V1) << BIT_SHIFT_RARF_RC6_V1)
+#define BITS_RARF_RC6_V1 (BIT_MASK_RARF_RC6_V1 << BIT_SHIFT_RARF_RC6_V1)
+#define BIT_CLEAR_RARF_RC6_V1(x) ((x) & (~BITS_RARF_RC6_V1))
+#define BIT_GET_RARF_RC6_V1(x)                                                 \
+	(((x) >> BIT_SHIFT_RARF_RC6_V1) & BIT_MASK_RARF_RC6_V1)
+#define BIT_SET_RARF_RC6_V1(x, v)                                              \
+	(BIT_CLEAR_RARF_RC6_V1(x) | BIT_RARF_RC6_V1(v))
+
+#define BIT_SHIFT_RARF_RC5_V1 0
+#define BIT_MASK_RARF_RC5_V1 0x1f
+#define BIT_RARF_RC5_V1(x)                                                     \
+	(((x) & BIT_MASK_RARF_RC5_V1) << BIT_SHIFT_RARF_RC5_V1)
+#define BITS_RARF_RC5_V1 (BIT_MASK_RARF_RC5_V1 << BIT_SHIFT_RARF_RC5_V1)
+#define BIT_CLEAR_RARF_RC5_V1(x) ((x) & (~BITS_RARF_RC5_V1))
+#define BIT_GET_RARF_RC5_V1(x)                                                 \
+	(((x) >> BIT_SHIFT_RARF_RC5_V1) & BIT_MASK_RARF_RC5_V1)
+#define BIT_SET_RARF_RC5_V1(x, v)                                              \
+	(BIT_CLEAR_RARF_RC5_V1(x) | BIT_RARF_RC5_V1(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_RRSR				(Offset 0x0440) */
+
+#define BIT_EN_VHTBW_FALL BIT(31)
+#define BIT_EN_HTBW_FALL BIT(30)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_RRSR				(Offset 0x0440) */
+
+#define BIT_SHIFT_RRSR_RSC 21
+#define BIT_MASK_RRSR_RSC 0x3
+#define BIT_RRSR_RSC(x) (((x) & BIT_MASK_RRSR_RSC) << BIT_SHIFT_RRSR_RSC)
+#define BITS_RRSR_RSC (BIT_MASK_RRSR_RSC << BIT_SHIFT_RRSR_RSC)
+#define BIT_CLEAR_RRSR_RSC(x) ((x) & (~BITS_RRSR_RSC))
+#define BIT_GET_RRSR_RSC(x) (((x) >> BIT_SHIFT_RRSR_RSC) & BIT_MASK_RRSR_RSC)
+#define BIT_SET_RRSR_RSC(x, v) (BIT_CLEAR_RRSR_RSC(x) | BIT_RRSR_RSC(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT || \
+     HALMAC_8881A_SUPPORT)
+
+/* 2 REG_RRSR				(Offset 0x0440) */
+
+#define BIT_RRSR_BW BIT(20)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_RRSR				(Offset 0x0440) */
+
+#define BIT_SHIFT_RRSC_BITMAP 0
+#define BIT_MASK_RRSC_BITMAP 0xfffff
+#define BIT_RRSC_BITMAP(x)                                                     \
+	(((x) & BIT_MASK_RRSC_BITMAP) << BIT_SHIFT_RRSC_BITMAP)
+#define BITS_RRSC_BITMAP (BIT_MASK_RRSC_BITMAP << BIT_SHIFT_RRSC_BITMAP)
+#define BIT_CLEAR_RRSC_BITMAP(x) ((x) & (~BITS_RRSC_BITMAP))
+#define BIT_GET_RRSC_BITMAP(x)                                                 \
+	(((x) >> BIT_SHIFT_RRSC_BITMAP) & BIT_MASK_RRSC_BITMAP)
+#define BIT_SET_RRSC_BITMAP(x, v)                                              \
+	(BIT_CLEAR_RRSC_BITMAP(x) | BIT_RRSC_BITMAP(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT || \
+     HALMAC_8881A_SUPPORT)
+
+/* 2 REG_ARFR0				(Offset 0x0444) */
+
+#define BIT_SHIFT_ARFR0_V1 0
+#define BIT_MASK_ARFR0_V1 0xffffffffffffffffL
+#define BIT_ARFR0_V1(x) (((x) & BIT_MASK_ARFR0_V1) << BIT_SHIFT_ARFR0_V1)
+#define BITS_ARFR0_V1 (BIT_MASK_ARFR0_V1 << BIT_SHIFT_ARFR0_V1)
+#define BIT_CLEAR_ARFR0_V1(x) ((x) & (~BITS_ARFR0_V1))
+#define BIT_GET_ARFR0_V1(x) (((x) >> BIT_SHIFT_ARFR0_V1) & BIT_MASK_ARFR0_V1)
+#define BIT_SET_ARFR0_V1(x, v) (BIT_CLEAR_ARFR0_V1(x) | BIT_ARFR0_V1(v))
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_ARFR0				(Offset 0x0444) */
+
+#define BIT_SHIFT_ARFRL0 0
+#define BIT_MASK_ARFRL0 0xffffffffL
+#define BIT_ARFRL0(x) (((x) & BIT_MASK_ARFRL0) << BIT_SHIFT_ARFRL0)
+#define BITS_ARFRL0 (BIT_MASK_ARFRL0 << BIT_SHIFT_ARFRL0)
+#define BIT_CLEAR_ARFRL0(x) ((x) & (~BITS_ARFRL0))
+#define BIT_GET_ARFRL0(x) (((x) >> BIT_SHIFT_ARFRL0) & BIT_MASK_ARFRL0)
+#define BIT_SET_ARFRL0(x, v) (BIT_CLEAR_ARFRL0(x) | BIT_ARFRL0(v))
+
+/* 2 REG_ARFRH0				(Offset 0x0448) */
+
+#define BIT_SHIFT_ARFRH0 0
+#define BIT_MASK_ARFRH0 0xffffffffL
+#define BIT_ARFRH0(x) (((x) & BIT_MASK_ARFRH0) << BIT_SHIFT_ARFRH0)
+#define BITS_ARFRH0 (BIT_MASK_ARFRH0 << BIT_SHIFT_ARFRH0)
+#define BIT_CLEAR_ARFRH0(x) ((x) & (~BITS_ARFRH0))
+#define BIT_GET_ARFRH0(x) (((x) >> BIT_SHIFT_ARFRH0) & BIT_MASK_ARFRH0)
+#define BIT_SET_ARFRH0(x, v) (BIT_CLEAR_ARFRH0(x) | BIT_ARFRH0(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_REG_ARFR_WT0			(Offset 0x044C) */
+
+#define BIT_SHIFT_RATE7_WEIGHTING 28
+#define BIT_MASK_RATE7_WEIGHTING 0xf
+#define BIT_RATE7_WEIGHTING(x)                                                 \
+	(((x) & BIT_MASK_RATE7_WEIGHTING) << BIT_SHIFT_RATE7_WEIGHTING)
+#define BITS_RATE7_WEIGHTING                                                   \
+	(BIT_MASK_RATE7_WEIGHTING << BIT_SHIFT_RATE7_WEIGHTING)
+#define BIT_CLEAR_RATE7_WEIGHTING(x) ((x) & (~BITS_RATE7_WEIGHTING))
+#define BIT_GET_RATE7_WEIGHTING(x)                                             \
+	(((x) >> BIT_SHIFT_RATE7_WEIGHTING) & BIT_MASK_RATE7_WEIGHTING)
+#define BIT_SET_RATE7_WEIGHTING(x, v)                                          \
+	(BIT_CLEAR_RATE7_WEIGHTING(x) | BIT_RATE7_WEIGHTING(v))
+
+#define BIT_SHIFT_RATE6_WEIGHTING 24
+#define BIT_MASK_RATE6_WEIGHTING 0xf
+#define BIT_RATE6_WEIGHTING(x)                                                 \
+	(((x) & BIT_MASK_RATE6_WEIGHTING) << BIT_SHIFT_RATE6_WEIGHTING)
+#define BITS_RATE6_WEIGHTING                                                   \
+	(BIT_MASK_RATE6_WEIGHTING << BIT_SHIFT_RATE6_WEIGHTING)
+#define BIT_CLEAR_RATE6_WEIGHTING(x) ((x) & (~BITS_RATE6_WEIGHTING))
+#define BIT_GET_RATE6_WEIGHTING(x)                                             \
+	(((x) >> BIT_SHIFT_RATE6_WEIGHTING) & BIT_MASK_RATE6_WEIGHTING)
+#define BIT_SET_RATE6_WEIGHTING(x, v)                                          \
+	(BIT_CLEAR_RATE6_WEIGHTING(x) | BIT_RATE6_WEIGHTING(v))
+
+#define BIT_SHIFT_RATE5_WEIGHTING 20
+#define BIT_MASK_RATE5_WEIGHTING 0xf
+#define BIT_RATE5_WEIGHTING(x)                                                 \
+	(((x) & BIT_MASK_RATE5_WEIGHTING) << BIT_SHIFT_RATE5_WEIGHTING)
+#define BITS_RATE5_WEIGHTING                                                   \
+	(BIT_MASK_RATE5_WEIGHTING << BIT_SHIFT_RATE5_WEIGHTING)
+#define BIT_CLEAR_RATE5_WEIGHTING(x) ((x) & (~BITS_RATE5_WEIGHTING))
+#define BIT_GET_RATE5_WEIGHTING(x)                                             \
+	(((x) >> BIT_SHIFT_RATE5_WEIGHTING) & BIT_MASK_RATE5_WEIGHTING)
+#define BIT_SET_RATE5_WEIGHTING(x, v)                                          \
+	(BIT_CLEAR_RATE5_WEIGHTING(x) | BIT_RATE5_WEIGHTING(v))
+
+#define BIT_SHIFT_RATE4_WEIGHTING 16
+#define BIT_MASK_RATE4_WEIGHTING 0xf
+#define BIT_RATE4_WEIGHTING(x)                                                 \
+	(((x) & BIT_MASK_RATE4_WEIGHTING) << BIT_SHIFT_RATE4_WEIGHTING)
+#define BITS_RATE4_WEIGHTING                                                   \
+	(BIT_MASK_RATE4_WEIGHTING << BIT_SHIFT_RATE4_WEIGHTING)
+#define BIT_CLEAR_RATE4_WEIGHTING(x) ((x) & (~BITS_RATE4_WEIGHTING))
+#define BIT_GET_RATE4_WEIGHTING(x)                                             \
+	(((x) >> BIT_SHIFT_RATE4_WEIGHTING) & BIT_MASK_RATE4_WEIGHTING)
+#define BIT_SET_RATE4_WEIGHTING(x, v)                                          \
+	(BIT_CLEAR_RATE4_WEIGHTING(x) | BIT_RATE4_WEIGHTING(v))
+
+#define BIT_SHIFT_RATE3_WEIGHTING 12
+#define BIT_MASK_RATE3_WEIGHTING 0xf
+#define BIT_RATE3_WEIGHTING(x)                                                 \
+	(((x) & BIT_MASK_RATE3_WEIGHTING) << BIT_SHIFT_RATE3_WEIGHTING)
+#define BITS_RATE3_WEIGHTING                                                   \
+	(BIT_MASK_RATE3_WEIGHTING << BIT_SHIFT_RATE3_WEIGHTING)
+#define BIT_CLEAR_RATE3_WEIGHTING(x) ((x) & (~BITS_RATE3_WEIGHTING))
+#define BIT_GET_RATE3_WEIGHTING(x)                                             \
+	(((x) >> BIT_SHIFT_RATE3_WEIGHTING) & BIT_MASK_RATE3_WEIGHTING)
+#define BIT_SET_RATE3_WEIGHTING(x, v)                                          \
+	(BIT_CLEAR_RATE3_WEIGHTING(x) | BIT_RATE3_WEIGHTING(v))
+
+#define BIT_SHIFT_RATE2_WEIGHTING 8
+#define BIT_MASK_RATE2_WEIGHTING 0xf
+#define BIT_RATE2_WEIGHTING(x)                                                 \
+	(((x) & BIT_MASK_RATE2_WEIGHTING) << BIT_SHIFT_RATE2_WEIGHTING)
+#define BITS_RATE2_WEIGHTING                                                   \
+	(BIT_MASK_RATE2_WEIGHTING << BIT_SHIFT_RATE2_WEIGHTING)
+#define BIT_CLEAR_RATE2_WEIGHTING(x) ((x) & (~BITS_RATE2_WEIGHTING))
+#define BIT_GET_RATE2_WEIGHTING(x)                                             \
+	(((x) >> BIT_SHIFT_RATE2_WEIGHTING) & BIT_MASK_RATE2_WEIGHTING)
+#define BIT_SET_RATE2_WEIGHTING(x, v)                                          \
+	(BIT_CLEAR_RATE2_WEIGHTING(x) | BIT_RATE2_WEIGHTING(v))
+
+#define BIT_SHIFT_RATE1_WEIGHTING 4
+#define BIT_MASK_RATE1_WEIGHTING 0xf
+#define BIT_RATE1_WEIGHTING(x)                                                 \
+	(((x) & BIT_MASK_RATE1_WEIGHTING) << BIT_SHIFT_RATE1_WEIGHTING)
+#define BITS_RATE1_WEIGHTING                                                   \
+	(BIT_MASK_RATE1_WEIGHTING << BIT_SHIFT_RATE1_WEIGHTING)
+#define BIT_CLEAR_RATE1_WEIGHTING(x) ((x) & (~BITS_RATE1_WEIGHTING))
+#define BIT_GET_RATE1_WEIGHTING(x)                                             \
+	(((x) >> BIT_SHIFT_RATE1_WEIGHTING) & BIT_MASK_RATE1_WEIGHTING)
+#define BIT_SET_RATE1_WEIGHTING(x, v)                                          \
+	(BIT_CLEAR_RATE1_WEIGHTING(x) | BIT_RATE1_WEIGHTING(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT || \
+     HALMAC_8881A_SUPPORT)
+
+/* 2 REG_ARFR1_V1				(Offset 0x044C) */
+
+#define BIT_SHIFT_ARFR1_V1 0
+#define BIT_MASK_ARFR1_V1 0xffffffffffffffffL
+#define BIT_ARFR1_V1(x) (((x) & BIT_MASK_ARFR1_V1) << BIT_SHIFT_ARFR1_V1)
+#define BITS_ARFR1_V1 (BIT_MASK_ARFR1_V1 << BIT_SHIFT_ARFR1_V1)
+#define BIT_CLEAR_ARFR1_V1(x) ((x) & (~BITS_ARFR1_V1))
+#define BIT_GET_ARFR1_V1(x) (((x) >> BIT_SHIFT_ARFR1_V1) & BIT_MASK_ARFR1_V1)
+#define BIT_SET_ARFR1_V1(x, v) (BIT_CLEAR_ARFR1_V1(x) | BIT_ARFR1_V1(v))
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_ARFR1_V1				(Offset 0x044C) */
+
+#define BIT_SHIFT_ARFRL1 0
+#define BIT_MASK_ARFRL1 0xffffffffL
+#define BIT_ARFRL1(x) (((x) & BIT_MASK_ARFRL1) << BIT_SHIFT_ARFRL1)
+#define BITS_ARFRL1 (BIT_MASK_ARFRL1 << BIT_SHIFT_ARFRL1)
+#define BIT_CLEAR_ARFRL1(x) ((x) & (~BITS_ARFRL1))
+#define BIT_GET_ARFRL1(x) (((x) >> BIT_SHIFT_ARFRL1) & BIT_MASK_ARFRL1)
+#define BIT_SET_ARFRL1(x, v) (BIT_CLEAR_ARFRL1(x) | BIT_ARFRL1(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_REG_ARFR_WT0			(Offset 0x044C) */
+
+#define BIT_SHIFT_RATE0_WEIGHTING 0
+#define BIT_MASK_RATE0_WEIGHTING 0xf
+#define BIT_RATE0_WEIGHTING(x)                                                 \
+	(((x) & BIT_MASK_RATE0_WEIGHTING) << BIT_SHIFT_RATE0_WEIGHTING)
+#define BITS_RATE0_WEIGHTING                                                   \
+	(BIT_MASK_RATE0_WEIGHTING << BIT_SHIFT_RATE0_WEIGHTING)
+#define BIT_CLEAR_RATE0_WEIGHTING(x) ((x) & (~BITS_RATE0_WEIGHTING))
+#define BIT_GET_RATE0_WEIGHTING(x)                                             \
+	(((x) >> BIT_SHIFT_RATE0_WEIGHTING) & BIT_MASK_RATE0_WEIGHTING)
+#define BIT_SET_RATE0_WEIGHTING(x, v)                                          \
+	(BIT_CLEAR_RATE0_WEIGHTING(x) | BIT_RATE0_WEIGHTING(v))
+
+/* 2 REG_REG_ARFR_WT1			(Offset 0x0450) */
+
+#define BIT_SHIFT_RATE15_WEIGHTING 28
+#define BIT_MASK_RATE15_WEIGHTING 0xf
+#define BIT_RATE15_WEIGHTING(x)                                                \
+	(((x) & BIT_MASK_RATE15_WEIGHTING) << BIT_SHIFT_RATE15_WEIGHTING)
+#define BITS_RATE15_WEIGHTING                                                  \
+	(BIT_MASK_RATE15_WEIGHTING << BIT_SHIFT_RATE15_WEIGHTING)
+#define BIT_CLEAR_RATE15_WEIGHTING(x) ((x) & (~BITS_RATE15_WEIGHTING))
+#define BIT_GET_RATE15_WEIGHTING(x)                                            \
+	(((x) >> BIT_SHIFT_RATE15_WEIGHTING) & BIT_MASK_RATE15_WEIGHTING)
+#define BIT_SET_RATE15_WEIGHTING(x, v)                                         \
+	(BIT_CLEAR_RATE15_WEIGHTING(x) | BIT_RATE15_WEIGHTING(v))
+
+#define BIT_SHIFT_RATE14_WEIGHTING 24
+#define BIT_MASK_RATE14_WEIGHTING 0xf
+#define BIT_RATE14_WEIGHTING(x)                                                \
+	(((x) & BIT_MASK_RATE14_WEIGHTING) << BIT_SHIFT_RATE14_WEIGHTING)
+#define BITS_RATE14_WEIGHTING                                                  \
+	(BIT_MASK_RATE14_WEIGHTING << BIT_SHIFT_RATE14_WEIGHTING)
+#define BIT_CLEAR_RATE14_WEIGHTING(x) ((x) & (~BITS_RATE14_WEIGHTING))
+#define BIT_GET_RATE14_WEIGHTING(x)                                            \
+	(((x) >> BIT_SHIFT_RATE14_WEIGHTING) & BIT_MASK_RATE14_WEIGHTING)
+#define BIT_SET_RATE14_WEIGHTING(x, v)                                         \
+	(BIT_CLEAR_RATE14_WEIGHTING(x) | BIT_RATE14_WEIGHTING(v))
+
+#define BIT_SHIFT_RATE13_WEIGHTING 20
+#define BIT_MASK_RATE13_WEIGHTING 0xf
+#define BIT_RATE13_WEIGHTING(x)                                                \
+	(((x) & BIT_MASK_RATE13_WEIGHTING) << BIT_SHIFT_RATE13_WEIGHTING)
+#define BITS_RATE13_WEIGHTING                                                  \
+	(BIT_MASK_RATE13_WEIGHTING << BIT_SHIFT_RATE13_WEIGHTING)
+#define BIT_CLEAR_RATE13_WEIGHTING(x) ((x) & (~BITS_RATE13_WEIGHTING))
+#define BIT_GET_RATE13_WEIGHTING(x)                                            \
+	(((x) >> BIT_SHIFT_RATE13_WEIGHTING) & BIT_MASK_RATE13_WEIGHTING)
+#define BIT_SET_RATE13_WEIGHTING(x, v)                                         \
+	(BIT_CLEAR_RATE13_WEIGHTING(x) | BIT_RATE13_WEIGHTING(v))
+
+#define BIT_SHIFT_RATE12_WEIGHTING 16
+#define BIT_MASK_RATE12_WEIGHTING 0xf
+#define BIT_RATE12_WEIGHTING(x)                                                \
+	(((x) & BIT_MASK_RATE12_WEIGHTING) << BIT_SHIFT_RATE12_WEIGHTING)
+#define BITS_RATE12_WEIGHTING                                                  \
+	(BIT_MASK_RATE12_WEIGHTING << BIT_SHIFT_RATE12_WEIGHTING)
+#define BIT_CLEAR_RATE12_WEIGHTING(x) ((x) & (~BITS_RATE12_WEIGHTING))
+#define BIT_GET_RATE12_WEIGHTING(x)                                            \
+	(((x) >> BIT_SHIFT_RATE12_WEIGHTING) & BIT_MASK_RATE12_WEIGHTING)
+#define BIT_SET_RATE12_WEIGHTING(x, v)                                         \
+	(BIT_CLEAR_RATE12_WEIGHTING(x) | BIT_RATE12_WEIGHTING(v))
+
+#define BIT_SHIFT_RATE11_WEIGHTING 12
+#define BIT_MASK_RATE11_WEIGHTING 0xf
+#define BIT_RATE11_WEIGHTING(x)                                                \
+	(((x) & BIT_MASK_RATE11_WEIGHTING) << BIT_SHIFT_RATE11_WEIGHTING)
+#define BITS_RATE11_WEIGHTING                                                  \
+	(BIT_MASK_RATE11_WEIGHTING << BIT_SHIFT_RATE11_WEIGHTING)
+#define BIT_CLEAR_RATE11_WEIGHTING(x) ((x) & (~BITS_RATE11_WEIGHTING))
+#define BIT_GET_RATE11_WEIGHTING(x)                                            \
+	(((x) >> BIT_SHIFT_RATE11_WEIGHTING) & BIT_MASK_RATE11_WEIGHTING)
+#define BIT_SET_RATE11_WEIGHTING(x, v)                                         \
+	(BIT_CLEAR_RATE11_WEIGHTING(x) | BIT_RATE11_WEIGHTING(v))
+
+#define BIT_SHIFT_RATE10_WEIGHTING 8
+#define BIT_MASK_RATE10_WEIGHTING 0xf
+#define BIT_RATE10_WEIGHTING(x)                                                \
+	(((x) & BIT_MASK_RATE10_WEIGHTING) << BIT_SHIFT_RATE10_WEIGHTING)
+#define BITS_RATE10_WEIGHTING                                                  \
+	(BIT_MASK_RATE10_WEIGHTING << BIT_SHIFT_RATE10_WEIGHTING)
+#define BIT_CLEAR_RATE10_WEIGHTING(x) ((x) & (~BITS_RATE10_WEIGHTING))
+#define BIT_GET_RATE10_WEIGHTING(x)                                            \
+	(((x) >> BIT_SHIFT_RATE10_WEIGHTING) & BIT_MASK_RATE10_WEIGHTING)
+#define BIT_SET_RATE10_WEIGHTING(x, v)                                         \
+	(BIT_CLEAR_RATE10_WEIGHTING(x) | BIT_RATE10_WEIGHTING(v))
+
+#define BIT_SHIFT_RATE9_WEIGHTING 4
+#define BIT_MASK_RATE9_WEIGHTING 0xf
+#define BIT_RATE9_WEIGHTING(x)                                                 \
+	(((x) & BIT_MASK_RATE9_WEIGHTING) << BIT_SHIFT_RATE9_WEIGHTING)
+#define BITS_RATE9_WEIGHTING                                                   \
+	(BIT_MASK_RATE9_WEIGHTING << BIT_SHIFT_RATE9_WEIGHTING)
+#define BIT_CLEAR_RATE9_WEIGHTING(x) ((x) & (~BITS_RATE9_WEIGHTING))
+#define BIT_GET_RATE9_WEIGHTING(x)                                             \
+	(((x) >> BIT_SHIFT_RATE9_WEIGHTING) & BIT_MASK_RATE9_WEIGHTING)
+#define BIT_SET_RATE9_WEIGHTING(x, v)                                          \
+	(BIT_CLEAR_RATE9_WEIGHTING(x) | BIT_RATE9_WEIGHTING(v))
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_ARFRH1				(Offset 0x0450) */
+
+#define BIT_SHIFT_ARFRH1 0
+#define BIT_MASK_ARFRH1 0xffffffffL
+#define BIT_ARFRH1(x) (((x) & BIT_MASK_ARFRH1) << BIT_SHIFT_ARFRH1)
+#define BITS_ARFRH1 (BIT_MASK_ARFRH1 << BIT_SHIFT_ARFRH1)
+#define BIT_CLEAR_ARFRH1(x) ((x) & (~BITS_ARFRH1))
+#define BIT_GET_ARFRH1(x) (((x) >> BIT_SHIFT_ARFRH1) & BIT_MASK_ARFRH1)
+#define BIT_SET_ARFRH1(x, v) (BIT_CLEAR_ARFRH1(x) | BIT_ARFRH1(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_REG_ARFR_WT1			(Offset 0x0450) */
+
+#define BIT_SHIFT_RATE8_WEIGHTING 0
+#define BIT_MASK_RATE8_WEIGHTING 0xf
+#define BIT_RATE8_WEIGHTING(x)                                                 \
+	(((x) & BIT_MASK_RATE8_WEIGHTING) << BIT_SHIFT_RATE8_WEIGHTING)
+#define BITS_RATE8_WEIGHTING                                                   \
+	(BIT_MASK_RATE8_WEIGHTING << BIT_SHIFT_RATE8_WEIGHTING)
+#define BIT_CLEAR_RATE8_WEIGHTING(x) ((x) & (~BITS_RATE8_WEIGHTING))
+#define BIT_GET_RATE8_WEIGHTING(x)                                             \
+	(((x) >> BIT_SHIFT_RATE8_WEIGHTING) & BIT_MASK_RATE8_WEIGHTING)
+#define BIT_SET_RATE8_WEIGHTING(x, v)                                          \
+	(BIT_CLEAR_RATE8_WEIGHTING(x) | BIT_RATE8_WEIGHTING(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_CCK_CHECK				(Offset 0x0454) */
+
+#define BIT_CHECK_CCK_EN BIT(7)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_CCK_CHECK				(Offset 0x0454) */
+
+#define BIT_EN_BCN_PKT_REL BIT(6)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_CCK_CHECK				(Offset 0x0454) */
+
+#define BIT_EN_BCN_PKT_REL_P0 BIT(6)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_CCK_CHECK				(Offset 0x0454) */
+
+#define BIT_BCN_PORT_SEL BIT(5)
+#define BIT_MOREDATA_BYPASS BIT(4)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_CCK_CHECK				(Offset 0x0454) */
+
+#define BIT_EN_CLR_CMD_REL_BCN_PKT BIT(3)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_CCK_CHECK				(Offset 0x0454) */
+
+#define BIT_EN_CLR_CMD_REL_BCN_PKT_P0 BIT(3)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8814B_SUPPORT)
+
+/* 2 REG_CCK_CHECK				(Offset 0x0454) */
+
+#define BIT_EN_SET_MOREDATA BIT(2)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_CCK_CHECK				(Offset 0x0454) */
+
+#define BIT_R_EN_SET_MOREDATA BIT(2)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_CCK_CHECK				(Offset 0x0454) */
+
+#define BIT__R_DIS_CLEAR_MACID_RELEASE BIT(1)
+#define BIT__R_MACID_RELEASE_EN BIT(0)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_AMPDU_MAX_TIME_V1			(Offset 0x0455) */
+
+#define BIT_SHIFT_AMPDU_MAX_TIME 0
+#define BIT_MASK_AMPDU_MAX_TIME 0xff
+#define BIT_AMPDU_MAX_TIME(x)                                                  \
+	(((x) & BIT_MASK_AMPDU_MAX_TIME) << BIT_SHIFT_AMPDU_MAX_TIME)
+#define BITS_AMPDU_MAX_TIME                                                    \
+	(BIT_MASK_AMPDU_MAX_TIME << BIT_SHIFT_AMPDU_MAX_TIME)
+#define BIT_CLEAR_AMPDU_MAX_TIME(x) ((x) & (~BITS_AMPDU_MAX_TIME))
+#define BIT_GET_AMPDU_MAX_TIME(x)                                              \
+	(((x) >> BIT_SHIFT_AMPDU_MAX_TIME) & BIT_MASK_AMPDU_MAX_TIME)
+#define BIT_SET_AMPDU_MAX_TIME(x, v)                                           \
+	(BIT_CLEAR_AMPDU_MAX_TIME(x) | BIT_AMPDU_MAX_TIME(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_AMPDU_BURST_CTRL			(Offset 0x0455) */
+
+#define BIT_AMPDU_BURST_GLOBAL_EN BIT(0)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_BCNQ2_HEAD				(Offset 0x0455) */
+
+#define BIT_SHIFT_BCNQ2_HEAD 0
+#define BIT_MASK_BCNQ2_HEAD 0xff
+#define BIT_BCNQ2_HEAD(x) (((x) & BIT_MASK_BCNQ2_HEAD) << BIT_SHIFT_BCNQ2_HEAD)
+#define BITS_BCNQ2_HEAD (BIT_MASK_BCNQ2_HEAD << BIT_SHIFT_BCNQ2_HEAD)
+#define BIT_CLEAR_BCNQ2_HEAD(x) ((x) & (~BITS_BCNQ2_HEAD))
+#define BIT_GET_BCNQ2_HEAD(x)                                                  \
+	(((x) >> BIT_SHIFT_BCNQ2_HEAD) & BIT_MASK_BCNQ2_HEAD)
+#define BIT_SET_BCNQ2_HEAD(x, v) (BIT_CLEAR_BCNQ2_HEAD(x) | BIT_BCNQ2_HEAD(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_BCNQ1_BDNY_V1			(Offset 0x0456) */
+
+#define BIT_SHIFT_BCNQ1_PGBNDY_V1 0
+#define BIT_MASK_BCNQ1_PGBNDY_V1 0xfff
+#define BIT_BCNQ1_PGBNDY_V1(x)                                                 \
+	(((x) & BIT_MASK_BCNQ1_PGBNDY_V1) << BIT_SHIFT_BCNQ1_PGBNDY_V1)
+#define BITS_BCNQ1_PGBNDY_V1                                                   \
+	(BIT_MASK_BCNQ1_PGBNDY_V1 << BIT_SHIFT_BCNQ1_PGBNDY_V1)
+#define BIT_CLEAR_BCNQ1_PGBNDY_V1(x) ((x) & (~BITS_BCNQ1_PGBNDY_V1))
+#define BIT_GET_BCNQ1_PGBNDY_V1(x)                                             \
+	(((x) >> BIT_SHIFT_BCNQ1_PGBNDY_V1) & BIT_MASK_BCNQ1_PGBNDY_V1)
+#define BIT_SET_BCNQ1_PGBNDY_V1(x, v)                                          \
+	(BIT_CLEAR_BCNQ1_PGBNDY_V1(x) | BIT_BCNQ1_PGBNDY_V1(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_TAB_SEL				(Offset 0x0456) */
+
+#define BIT_SHIFT_RATE_SEL 0
+#define BIT_MASK_RATE_SEL 0xf
+#define BIT_RATE_SEL(x) (((x) & BIT_MASK_RATE_SEL) << BIT_SHIFT_RATE_SEL)
+#define BITS_RATE_SEL (BIT_MASK_RATE_SEL << BIT_SHIFT_RATE_SEL)
+#define BIT_CLEAR_RATE_SEL(x) ((x) & (~BITS_RATE_SEL))
+#define BIT_GET_RATE_SEL(x) (((x) >> BIT_SHIFT_RATE_SEL) & BIT_MASK_RATE_SEL)
+#define BIT_SET_RATE_SEL(x, v) (BIT_CLEAR_RATE_SEL(x) | BIT_RATE_SEL(v))
+
+/* 2 REG_BCN_INVALID_CTRL			(Offset 0x0457) */
+
+#define BIT_EN_CLR_CMD_REL_BCN_PKT_P4 BIT(7)
+#define BIT_EN_BCN_PKT_REL_P4 BIT(6)
+#define BIT_EN_CLR_CMD_REL_BCN_PKT_P3 BIT(5)
+#define BIT_EN_BCN_PKT_REL_P3 BIT(4)
+#define BIT_EN_CLR_CMD_REL_BCN_PKT_P2 BIT(3)
+#define BIT_EN_BCN_PKT_REL_P2 BIT(2)
+#define BIT_EN_CLR_CMD_REL_BCN_PKT_P1 BIT(1)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_BCNQ1_BDNY				(Offset 0x0457) */
+
+#define BIT_SHIFT_BCNQ1_PGBNDY 0
+#define BIT_MASK_BCNQ1_PGBNDY 0xff
+#define BIT_BCNQ1_PGBNDY(x)                                                    \
+	(((x) & BIT_MASK_BCNQ1_PGBNDY) << BIT_SHIFT_BCNQ1_PGBNDY)
+#define BITS_BCNQ1_PGBNDY (BIT_MASK_BCNQ1_PGBNDY << BIT_SHIFT_BCNQ1_PGBNDY)
+#define BIT_CLEAR_BCNQ1_PGBNDY(x) ((x) & (~BITS_BCNQ1_PGBNDY))
+#define BIT_GET_BCNQ1_PGBNDY(x)                                                \
+	(((x) >> BIT_SHIFT_BCNQ1_PGBNDY) & BIT_MASK_BCNQ1_PGBNDY)
+#define BIT_SET_BCNQ1_PGBNDY(x, v)                                             \
+	(BIT_CLEAR_BCNQ1_PGBNDY(x) | BIT_BCNQ1_PGBNDY(v))
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_BCNQ1_BDNY				(Offset 0x0457) */
+
+#define BIT_SHIFT_BCNQ1_HEAD 0
+#define BIT_MASK_BCNQ1_HEAD 0xff
+#define BIT_BCNQ1_HEAD(x) (((x) & BIT_MASK_BCNQ1_HEAD) << BIT_SHIFT_BCNQ1_HEAD)
+#define BITS_BCNQ1_HEAD (BIT_MASK_BCNQ1_HEAD << BIT_SHIFT_BCNQ1_HEAD)
+#define BIT_CLEAR_BCNQ1_HEAD(x) ((x) & (~BITS_BCNQ1_HEAD))
+#define BIT_GET_BCNQ1_HEAD(x)                                                  \
+	(((x) >> BIT_SHIFT_BCNQ1_HEAD) & BIT_MASK_BCNQ1_HEAD)
+#define BIT_SET_BCNQ1_HEAD(x, v) (BIT_CLEAR_BCNQ1_HEAD(x) | BIT_BCNQ1_HEAD(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_BCN_INVALID_CTRL			(Offset 0x0457) */
+
+#define BIT_EN_BCN_PKT_REL_P1 BIT(0)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_AMPDU_MAX_LENGTH			(Offset 0x0458) */
+
+#define BIT_SHIFT_AMPDU_MAX_LENGTH 0
+#define BIT_MASK_AMPDU_MAX_LENGTH 0xffffffffL
+#define BIT_AMPDU_MAX_LENGTH(x)                                                \
+	(((x) & BIT_MASK_AMPDU_MAX_LENGTH) << BIT_SHIFT_AMPDU_MAX_LENGTH)
+#define BITS_AMPDU_MAX_LENGTH                                                  \
+	(BIT_MASK_AMPDU_MAX_LENGTH << BIT_SHIFT_AMPDU_MAX_LENGTH)
+#define BIT_CLEAR_AMPDU_MAX_LENGTH(x) ((x) & (~BITS_AMPDU_MAX_LENGTH))
+#define BIT_GET_AMPDU_MAX_LENGTH(x)                                            \
+	(((x) >> BIT_SHIFT_AMPDU_MAX_LENGTH) & BIT_MASK_AMPDU_MAX_LENGTH)
+#define BIT_SET_AMPDU_MAX_LENGTH(x, v)                                         \
+	(BIT_CLEAR_AMPDU_MAX_LENGTH(x) | BIT_AMPDU_MAX_LENGTH(v))
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_AMPDU_MAX_LENGTH_HT			(Offset 0x0458) */
+
+#define BIT_SHIFT_AMPDU_MAX_LENGTH_HT 0
+#define BIT_MASK_AMPDU_MAX_LENGTH_HT 0xffff
+#define BIT_AMPDU_MAX_LENGTH_HT(x)                                             \
+	(((x) & BIT_MASK_AMPDU_MAX_LENGTH_HT) << BIT_SHIFT_AMPDU_MAX_LENGTH_HT)
+#define BITS_AMPDU_MAX_LENGTH_HT                                               \
+	(BIT_MASK_AMPDU_MAX_LENGTH_HT << BIT_SHIFT_AMPDU_MAX_LENGTH_HT)
+#define BIT_CLEAR_AMPDU_MAX_LENGTH_HT(x) ((x) & (~BITS_AMPDU_MAX_LENGTH_HT))
+#define BIT_GET_AMPDU_MAX_LENGTH_HT(x)                                         \
+	(((x) >> BIT_SHIFT_AMPDU_MAX_LENGTH_HT) & BIT_MASK_AMPDU_MAX_LENGTH_HT)
+#define BIT_SET_AMPDU_MAX_LENGTH_HT(x, v)                                      \
+	(BIT_CLEAR_AMPDU_MAX_LENGTH_HT(x) | BIT_AMPDU_MAX_LENGTH_HT(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_ACQ_STOP				(Offset 0x045C) */
+
+#define BIT_AC7Q_STOP BIT(7)
+#define BIT_AC6Q_STOP BIT(6)
+#define BIT_AC5Q_STOP BIT(5)
+#define BIT_AC4Q_STOP BIT(4)
+#define BIT_AC3Q_STOP BIT(3)
+#define BIT_AC2Q_STOP BIT(2)
+#define BIT_AC1Q_STOP BIT(1)
+#define BIT_AC0Q_STOP BIT(0)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_WMAC_LBK_BUF_HD			(Offset 0x045D) */
+
+#define BIT_SHIFT_WMAC_LBK_BUF_HEAD 0
+#define BIT_MASK_WMAC_LBK_BUF_HEAD 0xff
+#define BIT_WMAC_LBK_BUF_HEAD(x)                                               \
+	(((x) & BIT_MASK_WMAC_LBK_BUF_HEAD) << BIT_SHIFT_WMAC_LBK_BUF_HEAD)
+#define BITS_WMAC_LBK_BUF_HEAD                                                 \
+	(BIT_MASK_WMAC_LBK_BUF_HEAD << BIT_SHIFT_WMAC_LBK_BUF_HEAD)
+#define BIT_CLEAR_WMAC_LBK_BUF_HEAD(x) ((x) & (~BITS_WMAC_LBK_BUF_HEAD))
+#define BIT_GET_WMAC_LBK_BUF_HEAD(x)                                           \
+	(((x) >> BIT_SHIFT_WMAC_LBK_BUF_HEAD) & BIT_MASK_WMAC_LBK_BUF_HEAD)
+#define BIT_SET_WMAC_LBK_BUF_HEAD(x, v)                                        \
+	(BIT_CLEAR_WMAC_LBK_BUF_HEAD(x) | BIT_WMAC_LBK_BUF_HEAD(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_NDPA_RATE				(Offset 0x045D) */
+
+#define BIT_SHIFT_R_NDPA_RATE_V1 0
+#define BIT_MASK_R_NDPA_RATE_V1 0xff
+#define BIT_R_NDPA_RATE_V1(x)                                                  \
+	(((x) & BIT_MASK_R_NDPA_RATE_V1) << BIT_SHIFT_R_NDPA_RATE_V1)
+#define BITS_R_NDPA_RATE_V1                                                    \
+	(BIT_MASK_R_NDPA_RATE_V1 << BIT_SHIFT_R_NDPA_RATE_V1)
+#define BIT_CLEAR_R_NDPA_RATE_V1(x) ((x) & (~BITS_R_NDPA_RATE_V1))
+#define BIT_GET_R_NDPA_RATE_V1(x)                                              \
+	(((x) >> BIT_SHIFT_R_NDPA_RATE_V1) & BIT_MASK_R_NDPA_RATE_V1)
+#define BIT_SET_R_NDPA_RATE_V1(x, v)                                           \
+	(BIT_CLEAR_R_NDPA_RATE_V1(x) | BIT_R_NDPA_RATE_V1(v))
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8814B_SUPPORT)
+
+/* 2 REG_TX_HANG_CTRL			(Offset 0x045E) */
+
+#define BIT_EN_GNT_BT_AWAKE BIT(3)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_TX_HANG_CTRL			(Offset 0x045E) */
+
+#define BIT_R_EN_GNT_BT_AWAKE BIT(3)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_TX_HANG_CTRL			(Offset 0x045E) */
+
+#define BIT_DIS_RELEASE_RETRY BIT(2)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_TX_HANG_CTRL			(Offset 0x045E) */
+
+#define BIT_EN_EOF_V1 BIT(2)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_TX_HANG_CTRL			(Offset 0x045E) */
+
+#define BIT_DIS_OQT_BLOCK BIT(1)
+#define BIT_SEARCH_QUEUE_EN BIT(0)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_NDPA_OPT_CTRL			(Offset 0x045F) */
+
+#define BIT_R_DIS_MACID_RELEASE_RTY BIT(5)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_NDPA_OPT_CTRL			(Offset 0x045F) */
+
+#define BIT_DIS_MACID_RELEASE_RTY BIT(5)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_NDPA_OPT_CTRL			(Offset 0x045F) */
+
+#define BIT_SHIFT_BW_SIGTA 3
+#define BIT_MASK_BW_SIGTA 0x3
+#define BIT_BW_SIGTA(x) (((x) & BIT_MASK_BW_SIGTA) << BIT_SHIFT_BW_SIGTA)
+#define BITS_BW_SIGTA (BIT_MASK_BW_SIGTA << BIT_SHIFT_BW_SIGTA)
+#define BIT_CLEAR_BW_SIGTA(x) ((x) & (~BITS_BW_SIGTA))
+#define BIT_GET_BW_SIGTA(x) (((x) >> BIT_SHIFT_BW_SIGTA) & BIT_MASK_BW_SIGTA)
+#define BIT_SET_BW_SIGTA(x, v) (BIT_CLEAR_BW_SIGTA(x) | BIT_BW_SIGTA(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_NDPA_OPT_CTRL			(Offset 0x045F) */
+
+#define BIT_SHIFT_R_NDPA_RATE 2
+#define BIT_MASK_R_NDPA_RATE 0x3f
+#define BIT_R_NDPA_RATE(x)                                                     \
+	(((x) & BIT_MASK_R_NDPA_RATE) << BIT_SHIFT_R_NDPA_RATE)
+#define BITS_R_NDPA_RATE (BIT_MASK_R_NDPA_RATE << BIT_SHIFT_R_NDPA_RATE)
+#define BIT_CLEAR_R_NDPA_RATE(x) ((x) & (~BITS_R_NDPA_RATE))
+#define BIT_GET_R_NDPA_RATE(x)                                                 \
+	(((x) >> BIT_SHIFT_R_NDPA_RATE) & BIT_MASK_R_NDPA_RATE)
+#define BIT_SET_R_NDPA_RATE(x, v)                                              \
+	(BIT_CLEAR_R_NDPA_RATE(x) | BIT_R_NDPA_RATE(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_NDPA_OPT_CTRL			(Offset 0x045F) */
+
+#define BIT_EN_BAR_SIGTA BIT(2)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8881A_SUPPORT)
+
+/* 2 REG_NDPA_OPT_CTRL			(Offset 0x045F) */
+
+#define BIT_SHIFT_R_NDPA_BW 0
+#define BIT_MASK_R_NDPA_BW 0x3
+#define BIT_R_NDPA_BW(x) (((x) & BIT_MASK_R_NDPA_BW) << BIT_SHIFT_R_NDPA_BW)
+#define BITS_R_NDPA_BW (BIT_MASK_R_NDPA_BW << BIT_SHIFT_R_NDPA_BW)
+#define BIT_CLEAR_R_NDPA_BW(x) ((x) & (~BITS_R_NDPA_BW))
+#define BIT_GET_R_NDPA_BW(x) (((x) >> BIT_SHIFT_R_NDPA_BW) & BIT_MASK_R_NDPA_BW)
+#define BIT_SET_R_NDPA_BW(x, v) (BIT_CLEAR_R_NDPA_BW(x) | BIT_R_NDPA_BW(v))
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8814B_SUPPORT)
+
+/* 2 REG_NDPA_OPT_CTRL			(Offset 0x045F) */
+
+#define BIT_SHIFT_NDPA_BW 0
+#define BIT_MASK_NDPA_BW 0x3
+#define BIT_NDPA_BW(x) (((x) & BIT_MASK_NDPA_BW) << BIT_SHIFT_NDPA_BW)
+#define BITS_NDPA_BW (BIT_MASK_NDPA_BW << BIT_SHIFT_NDPA_BW)
+#define BIT_CLEAR_NDPA_BW(x) ((x) & (~BITS_NDPA_BW))
+#define BIT_GET_NDPA_BW(x) (((x) >> BIT_SHIFT_NDPA_BW) & BIT_MASK_NDPA_BW)
+#define BIT_SET_NDPA_BW(x, v) (BIT_CLEAR_NDPA_BW(x) | BIT_NDPA_BW(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_FAST_EDCA_CTRL			(Offset 0x0460) */
+
+#define BIT_SHIFT_FAST_EDCA_TO_V1 16
+#define BIT_MASK_FAST_EDCA_TO_V1 0xff
+#define BIT_FAST_EDCA_TO_V1(x)                                                 \
+	(((x) & BIT_MASK_FAST_EDCA_TO_V1) << BIT_SHIFT_FAST_EDCA_TO_V1)
+#define BITS_FAST_EDCA_TO_V1                                                   \
+	(BIT_MASK_FAST_EDCA_TO_V1 << BIT_SHIFT_FAST_EDCA_TO_V1)
+#define BIT_CLEAR_FAST_EDCA_TO_V1(x) ((x) & (~BITS_FAST_EDCA_TO_V1))
+#define BIT_GET_FAST_EDCA_TO_V1(x)                                             \
+	(((x) >> BIT_SHIFT_FAST_EDCA_TO_V1) & BIT_MASK_FAST_EDCA_TO_V1)
+#define BIT_SET_FAST_EDCA_TO_V1(x, v)                                          \
+	(BIT_CLEAR_FAST_EDCA_TO_V1(x) | BIT_FAST_EDCA_TO_V1(v))
+
+#define BIT_SHIFT_AC3_AC7_FAST_EDCA_PKT_TH 12
+#define BIT_MASK_AC3_AC7_FAST_EDCA_PKT_TH 0xf
+#define BIT_AC3_AC7_FAST_EDCA_PKT_TH(x)                                        \
+	(((x) & BIT_MASK_AC3_AC7_FAST_EDCA_PKT_TH)                             \
+	 << BIT_SHIFT_AC3_AC7_FAST_EDCA_PKT_TH)
+#define BITS_AC3_AC7_FAST_EDCA_PKT_TH                                          \
+	(BIT_MASK_AC3_AC7_FAST_EDCA_PKT_TH                                     \
+	 << BIT_SHIFT_AC3_AC7_FAST_EDCA_PKT_TH)
+#define BIT_CLEAR_AC3_AC7_FAST_EDCA_PKT_TH(x)                                  \
+	((x) & (~BITS_AC3_AC7_FAST_EDCA_PKT_TH))
+#define BIT_GET_AC3_AC7_FAST_EDCA_PKT_TH(x)                                    \
+	(((x) >> BIT_SHIFT_AC3_AC7_FAST_EDCA_PKT_TH) &                         \
+	 BIT_MASK_AC3_AC7_FAST_EDCA_PKT_TH)
+#define BIT_SET_AC3_AC7_FAST_EDCA_PKT_TH(x, v)                                 \
+	(BIT_CLEAR_AC3_AC7_FAST_EDCA_PKT_TH(x) |                               \
+	 BIT_AC3_AC7_FAST_EDCA_PKT_TH(v))
+
+#define BIT_SHIFT_AC2_FAST_EDCA_PKT_TH 8
+#define BIT_MASK_AC2_FAST_EDCA_PKT_TH 0xf
+#define BIT_AC2_FAST_EDCA_PKT_TH(x)                                            \
+	(((x) & BIT_MASK_AC2_FAST_EDCA_PKT_TH)                                 \
+	 << BIT_SHIFT_AC2_FAST_EDCA_PKT_TH)
+#define BITS_AC2_FAST_EDCA_PKT_TH                                              \
+	(BIT_MASK_AC2_FAST_EDCA_PKT_TH << BIT_SHIFT_AC2_FAST_EDCA_PKT_TH)
+#define BIT_CLEAR_AC2_FAST_EDCA_PKT_TH(x) ((x) & (~BITS_AC2_FAST_EDCA_PKT_TH))
+#define BIT_GET_AC2_FAST_EDCA_PKT_TH(x)                                        \
+	(((x) >> BIT_SHIFT_AC2_FAST_EDCA_PKT_TH) &                             \
+	 BIT_MASK_AC2_FAST_EDCA_PKT_TH)
+#define BIT_SET_AC2_FAST_EDCA_PKT_TH(x, v)                                     \
+	(BIT_CLEAR_AC2_FAST_EDCA_PKT_TH(x) | BIT_AC2_FAST_EDCA_PKT_TH(v))
+
+#define BIT_SHIFT_AC1_FAST_EDCA_PKT_TH 4
+#define BIT_MASK_AC1_FAST_EDCA_PKT_TH 0xf
+#define BIT_AC1_FAST_EDCA_PKT_TH(x)                                            \
+	(((x) & BIT_MASK_AC1_FAST_EDCA_PKT_TH)                                 \
+	 << BIT_SHIFT_AC1_FAST_EDCA_PKT_TH)
+#define BITS_AC1_FAST_EDCA_PKT_TH                                              \
+	(BIT_MASK_AC1_FAST_EDCA_PKT_TH << BIT_SHIFT_AC1_FAST_EDCA_PKT_TH)
+#define BIT_CLEAR_AC1_FAST_EDCA_PKT_TH(x) ((x) & (~BITS_AC1_FAST_EDCA_PKT_TH))
+#define BIT_GET_AC1_FAST_EDCA_PKT_TH(x)                                        \
+	(((x) >> BIT_SHIFT_AC1_FAST_EDCA_PKT_TH) &                             \
+	 BIT_MASK_AC1_FAST_EDCA_PKT_TH)
+#define BIT_SET_AC1_FAST_EDCA_PKT_TH(x, v)                                     \
+	(BIT_CLEAR_AC1_FAST_EDCA_PKT_TH(x) | BIT_AC1_FAST_EDCA_PKT_TH(v))
+
+#define BIT_SHIFT_AC0_FAST_EDCA_PKT_TH 0
+#define BIT_MASK_AC0_FAST_EDCA_PKT_TH 0xf
+#define BIT_AC0_FAST_EDCA_PKT_TH(x)                                            \
+	(((x) & BIT_MASK_AC0_FAST_EDCA_PKT_TH)                                 \
+	 << BIT_SHIFT_AC0_FAST_EDCA_PKT_TH)
+#define BITS_AC0_FAST_EDCA_PKT_TH                                              \
+	(BIT_MASK_AC0_FAST_EDCA_PKT_TH << BIT_SHIFT_AC0_FAST_EDCA_PKT_TH)
+#define BIT_CLEAR_AC0_FAST_EDCA_PKT_TH(x) ((x) & (~BITS_AC0_FAST_EDCA_PKT_TH))
+#define BIT_GET_AC0_FAST_EDCA_PKT_TH(x)                                        \
+	(((x) >> BIT_SHIFT_AC0_FAST_EDCA_PKT_TH) &                             \
+	 BIT_MASK_AC0_FAST_EDCA_PKT_TH)
+#define BIT_SET_AC0_FAST_EDCA_PKT_TH(x, v)                                     \
+	(BIT_CLEAR_AC0_FAST_EDCA_PKT_TH(x) | BIT_AC0_FAST_EDCA_PKT_TH(v))
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_AMPDU_MAX_LENGTH_VHT		(Offset 0x0460) */
+
+#define BIT_SHIFT_AMPDU_MAX_LENGTH_VHT_V1 0
+#define BIT_MASK_AMPDU_MAX_LENGTH_VHT_V1 0xfffff
+#define BIT_AMPDU_MAX_LENGTH_VHT_V1(x)                                         \
+	(((x) & BIT_MASK_AMPDU_MAX_LENGTH_VHT_V1)                              \
+	 << BIT_SHIFT_AMPDU_MAX_LENGTH_VHT_V1)
+#define BITS_AMPDU_MAX_LENGTH_VHT_V1                                           \
+	(BIT_MASK_AMPDU_MAX_LENGTH_VHT_V1 << BIT_SHIFT_AMPDU_MAX_LENGTH_VHT_V1)
+#define BIT_CLEAR_AMPDU_MAX_LENGTH_VHT_V1(x)                                   \
+	((x) & (~BITS_AMPDU_MAX_LENGTH_VHT_V1))
+#define BIT_GET_AMPDU_MAX_LENGTH_VHT_V1(x)                                     \
+	(((x) >> BIT_SHIFT_AMPDU_MAX_LENGTH_VHT_V1) &                          \
+	 BIT_MASK_AMPDU_MAX_LENGTH_VHT_V1)
+#define BIT_SET_AMPDU_MAX_LENGTH_VHT_V1(x, v)                                  \
+	(BIT_CLEAR_AMPDU_MAX_LENGTH_VHT_V1(x) | BIT_AMPDU_MAX_LENGTH_VHT_V1(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_AMPDU_MAX_LENGTH_VHT		(Offset 0x0460) */
+
+#define BIT_SHIFT_AMPDU_MAX_LENGTH_VHT 0
+#define BIT_MASK_AMPDU_MAX_LENGTH_VHT 0x3ffff
+#define BIT_AMPDU_MAX_LENGTH_VHT(x)                                            \
+	(((x) & BIT_MASK_AMPDU_MAX_LENGTH_VHT)                                 \
+	 << BIT_SHIFT_AMPDU_MAX_LENGTH_VHT)
+#define BITS_AMPDU_MAX_LENGTH_VHT                                              \
+	(BIT_MASK_AMPDU_MAX_LENGTH_VHT << BIT_SHIFT_AMPDU_MAX_LENGTH_VHT)
+#define BIT_CLEAR_AMPDU_MAX_LENGTH_VHT(x) ((x) & (~BITS_AMPDU_MAX_LENGTH_VHT))
+#define BIT_GET_AMPDU_MAX_LENGTH_VHT(x)                                        \
+	(((x) >> BIT_SHIFT_AMPDU_MAX_LENGTH_VHT) &                             \
+	 BIT_MASK_AMPDU_MAX_LENGTH_VHT)
+#define BIT_SET_AMPDU_MAX_LENGTH_VHT(x, v)                                     \
+	(BIT_CLEAR_AMPDU_MAX_LENGTH_VHT(x) | BIT_AMPDU_MAX_LENGTH_VHT(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_RD_RESP_PKT_TH			(Offset 0x0463) */
+
+#define BIT_SHIFT_RD_RESP_PKT_TH 0
+#define BIT_MASK_RD_RESP_PKT_TH 0x1f
+#define BIT_RD_RESP_PKT_TH(x)                                                  \
+	(((x) & BIT_MASK_RD_RESP_PKT_TH) << BIT_SHIFT_RD_RESP_PKT_TH)
+#define BITS_RD_RESP_PKT_TH                                                    \
+	(BIT_MASK_RD_RESP_PKT_TH << BIT_SHIFT_RD_RESP_PKT_TH)
+#define BIT_CLEAR_RD_RESP_PKT_TH(x) ((x) & (~BITS_RD_RESP_PKT_TH))
+#define BIT_GET_RD_RESP_PKT_TH(x)                                              \
+	(((x) >> BIT_SHIFT_RD_RESP_PKT_TH) & BIT_MASK_RD_RESP_PKT_TH)
+#define BIT_SET_RD_RESP_PKT_TH(x, v)                                           \
+	(BIT_CLEAR_RD_RESP_PKT_TH(x) | BIT_RD_RESP_PKT_TH(v))
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_RD_RESP_PKT_TH			(Offset 0x0463) */
+
+#define BIT_SHIFT_RD_RESP_PKT_TH_V1 0
+#define BIT_MASK_RD_RESP_PKT_TH_V1 0x3f
+#define BIT_RD_RESP_PKT_TH_V1(x)                                               \
+	(((x) & BIT_MASK_RD_RESP_PKT_TH_V1) << BIT_SHIFT_RD_RESP_PKT_TH_V1)
+#define BITS_RD_RESP_PKT_TH_V1                                                 \
+	(BIT_MASK_RD_RESP_PKT_TH_V1 << BIT_SHIFT_RD_RESP_PKT_TH_V1)
+#define BIT_CLEAR_RD_RESP_PKT_TH_V1(x) ((x) & (~BITS_RD_RESP_PKT_TH_V1))
+#define BIT_GET_RD_RESP_PKT_TH_V1(x)                                           \
+	(((x) >> BIT_SHIFT_RD_RESP_PKT_TH_V1) & BIT_MASK_RD_RESP_PKT_TH_V1)
+#define BIT_SET_RD_RESP_PKT_TH_V1(x, v)                                        \
+	(BIT_CLEAR_RD_RESP_PKT_TH_V1(x) | BIT_RD_RESP_PKT_TH_V1(v))
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_CMDQ_INFO				(Offset 0x0464) */
+
+#define BIT_SHIFT_QUEUEMACID_CMDQ_V1 25
+#define BIT_MASK_QUEUEMACID_CMDQ_V1 0x7f
+#define BIT_QUEUEMACID_CMDQ_V1(x)                                              \
+	(((x) & BIT_MASK_QUEUEMACID_CMDQ_V1) << BIT_SHIFT_QUEUEMACID_CMDQ_V1)
+#define BITS_QUEUEMACID_CMDQ_V1                                                \
+	(BIT_MASK_QUEUEMACID_CMDQ_V1 << BIT_SHIFT_QUEUEMACID_CMDQ_V1)
+#define BIT_CLEAR_QUEUEMACID_CMDQ_V1(x) ((x) & (~BITS_QUEUEMACID_CMDQ_V1))
+#define BIT_GET_QUEUEMACID_CMDQ_V1(x)                                          \
+	(((x) >> BIT_SHIFT_QUEUEMACID_CMDQ_V1) & BIT_MASK_QUEUEMACID_CMDQ_V1)
+#define BIT_SET_QUEUEMACID_CMDQ_V1(x, v)                                       \
+	(BIT_CLEAR_QUEUEMACID_CMDQ_V1(x) | BIT_QUEUEMACID_CMDQ_V1(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_CMDQ_INFO				(Offset 0x0464) */
+
+#define BIT_SHIFT_PKT_NUM_CMDQ_V2 24
+#define BIT_MASK_PKT_NUM_CMDQ_V2 0xff
+#define BIT_PKT_NUM_CMDQ_V2(x)                                                 \
+	(((x) & BIT_MASK_PKT_NUM_CMDQ_V2) << BIT_SHIFT_PKT_NUM_CMDQ_V2)
+#define BITS_PKT_NUM_CMDQ_V2                                                   \
+	(BIT_MASK_PKT_NUM_CMDQ_V2 << BIT_SHIFT_PKT_NUM_CMDQ_V2)
+#define BIT_CLEAR_PKT_NUM_CMDQ_V2(x) ((x) & (~BITS_PKT_NUM_CMDQ_V2))
+#define BIT_GET_PKT_NUM_CMDQ_V2(x)                                             \
+	(((x) >> BIT_SHIFT_PKT_NUM_CMDQ_V2) & BIT_MASK_PKT_NUM_CMDQ_V2)
+#define BIT_SET_PKT_NUM_CMDQ_V2(x, v)                                          \
+	(BIT_CLEAR_PKT_NUM_CMDQ_V2(x) | BIT_PKT_NUM_CMDQ_V2(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT)
+
+/* 2 REG_CMDQ_INFO				(Offset 0x0464) */
+
+#define BIT_SHIFT_PKT_NUM 23
+#define BIT_MASK_PKT_NUM 0x1ff
+#define BIT_PKT_NUM(x) (((x) & BIT_MASK_PKT_NUM) << BIT_SHIFT_PKT_NUM)
+#define BITS_PKT_NUM (BIT_MASK_PKT_NUM << BIT_SHIFT_PKT_NUM)
+#define BIT_CLEAR_PKT_NUM(x) ((x) & (~BITS_PKT_NUM))
+#define BIT_GET_PKT_NUM(x) (((x) >> BIT_SHIFT_PKT_NUM) & BIT_MASK_PKT_NUM)
+#define BIT_SET_PKT_NUM(x, v) (BIT_CLEAR_PKT_NUM(x) | BIT_PKT_NUM(v))
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_CMDQ_INFO				(Offset 0x0464) */
+
+#define BIT_SHIFT_QUEUEAC_CMDQ_V1 23
+#define BIT_MASK_QUEUEAC_CMDQ_V1 0x3
+#define BIT_QUEUEAC_CMDQ_V1(x)                                                 \
+	(((x) & BIT_MASK_QUEUEAC_CMDQ_V1) << BIT_SHIFT_QUEUEAC_CMDQ_V1)
+#define BITS_QUEUEAC_CMDQ_V1                                                   \
+	(BIT_MASK_QUEUEAC_CMDQ_V1 << BIT_SHIFT_QUEUEAC_CMDQ_V1)
+#define BIT_CLEAR_QUEUEAC_CMDQ_V1(x) ((x) & (~BITS_QUEUEAC_CMDQ_V1))
+#define BIT_GET_QUEUEAC_CMDQ_V1(x)                                             \
+	(((x) >> BIT_SHIFT_QUEUEAC_CMDQ_V1) & BIT_MASK_QUEUEAC_CMDQ_V1)
+#define BIT_SET_QUEUEAC_CMDQ_V1(x, v)                                          \
+	(BIT_CLEAR_QUEUEAC_CMDQ_V1(x) | BIT_QUEUEAC_CMDQ_V1(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_CMDQ_INFO				(Offset 0x0464) */
+
+#define BIT_TIDEMPTY_CMDQ_V1 BIT(22)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_CMDQ_INFO				(Offset 0x0464) */
+
+#define BIT_SHIFT_TAIL_PKT_CMDQ 16
+#define BIT_MASK_TAIL_PKT_CMDQ 0xff
+#define BIT_TAIL_PKT_CMDQ(x)                                                   \
+	(((x) & BIT_MASK_TAIL_PKT_CMDQ) << BIT_SHIFT_TAIL_PKT_CMDQ)
+#define BITS_TAIL_PKT_CMDQ (BIT_MASK_TAIL_PKT_CMDQ << BIT_SHIFT_TAIL_PKT_CMDQ)
+#define BIT_CLEAR_TAIL_PKT_CMDQ(x) ((x) & (~BITS_TAIL_PKT_CMDQ))
+#define BIT_GET_TAIL_PKT_CMDQ(x)                                               \
+	(((x) >> BIT_SHIFT_TAIL_PKT_CMDQ) & BIT_MASK_TAIL_PKT_CMDQ)
+#define BIT_SET_TAIL_PKT_CMDQ(x, v)                                            \
+	(BIT_CLEAR_TAIL_PKT_CMDQ(x) | BIT_TAIL_PKT_CMDQ(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8822B_SUPPORT)
+
+/* 2 REG_CMDQ_INFO				(Offset 0x0464) */
+
+#define BIT_SHIFT_TAIL_PKT_CMDQ_V2 11
+#define BIT_MASK_TAIL_PKT_CMDQ_V2 0x7ff
+#define BIT_TAIL_PKT_CMDQ_V2(x)                                                \
+	(((x) & BIT_MASK_TAIL_PKT_CMDQ_V2) << BIT_SHIFT_TAIL_PKT_CMDQ_V2)
+#define BITS_TAIL_PKT_CMDQ_V2                                                  \
+	(BIT_MASK_TAIL_PKT_CMDQ_V2 << BIT_SHIFT_TAIL_PKT_CMDQ_V2)
+#define BIT_CLEAR_TAIL_PKT_CMDQ_V2(x) ((x) & (~BITS_TAIL_PKT_CMDQ_V2))
+#define BIT_GET_TAIL_PKT_CMDQ_V2(x)                                            \
+	(((x) >> BIT_SHIFT_TAIL_PKT_CMDQ_V2) & BIT_MASK_TAIL_PKT_CMDQ_V2)
+#define BIT_SET_TAIL_PKT_CMDQ_V2(x, v)                                         \
+	(BIT_CLEAR_TAIL_PKT_CMDQ_V2(x) | BIT_TAIL_PKT_CMDQ_V2(v))
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT)
+
+/* 2 REG_NEW_EDCA_CTRL_V1			(Offset 0x0464) */
+
+#define BIT_SHIFT_RANDOM_VALUE_SHIFT 9
+#define BIT_MASK_RANDOM_VALUE_SHIFT 0x7
+#define BIT_RANDOM_VALUE_SHIFT(x)                                              \
+	(((x) & BIT_MASK_RANDOM_VALUE_SHIFT) << BIT_SHIFT_RANDOM_VALUE_SHIFT)
+#define BITS_RANDOM_VALUE_SHIFT                                                \
+	(BIT_MASK_RANDOM_VALUE_SHIFT << BIT_SHIFT_RANDOM_VALUE_SHIFT)
+#define BIT_CLEAR_RANDOM_VALUE_SHIFT(x) ((x) & (~BITS_RANDOM_VALUE_SHIFT))
+#define BIT_GET_RANDOM_VALUE_SHIFT(x)                                          \
+	(((x) >> BIT_SHIFT_RANDOM_VALUE_SHIFT) & BIT_MASK_RANDOM_VALUE_SHIFT)
+#define BIT_SET_RANDOM_VALUE_SHIFT(x, v)                                       \
+	(BIT_CLEAR_RANDOM_VALUE_SHIFT(x) | BIT_RANDOM_VALUE_SHIFT(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_CMDQ_INFO				(Offset 0x0464) */
+
+#define BIT_SHIFT_PKT_NUM_CMDQ 8
+#define BIT_MASK_PKT_NUM_CMDQ 0xff
+#define BIT_PKT_NUM_CMDQ(x)                                                    \
+	(((x) & BIT_MASK_PKT_NUM_CMDQ) << BIT_SHIFT_PKT_NUM_CMDQ)
+#define BITS_PKT_NUM_CMDQ (BIT_MASK_PKT_NUM_CMDQ << BIT_SHIFT_PKT_NUM_CMDQ)
+#define BIT_CLEAR_PKT_NUM_CMDQ(x) ((x) & (~BITS_PKT_NUM_CMDQ))
+#define BIT_GET_PKT_NUM_CMDQ(x)                                                \
+	(((x) >> BIT_SHIFT_PKT_NUM_CMDQ) & BIT_MASK_PKT_NUM_CMDQ)
+#define BIT_SET_PKT_NUM_CMDQ(x, v)                                             \
+	(BIT_CLEAR_PKT_NUM_CMDQ(x) | BIT_PKT_NUM_CMDQ(v))
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT)
+
+/* 2 REG_NEW_EDCA_CTRL_V1			(Offset 0x0464) */
+
+#define BIT_ENABLE_NEW_EDCA BIT(8)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_CMDQ_INFO				(Offset 0x0464) */
+
+#define BIT_SHIFT_HEAD_PKT_CMDQ 0
+#define BIT_MASK_HEAD_PKT_CMDQ 0xff
+#define BIT_HEAD_PKT_CMDQ(x)                                                   \
+	(((x) & BIT_MASK_HEAD_PKT_CMDQ) << BIT_SHIFT_HEAD_PKT_CMDQ)
+#define BITS_HEAD_PKT_CMDQ (BIT_MASK_HEAD_PKT_CMDQ << BIT_SHIFT_HEAD_PKT_CMDQ)
+#define BIT_CLEAR_HEAD_PKT_CMDQ(x) ((x) & (~BITS_HEAD_PKT_CMDQ))
+#define BIT_GET_HEAD_PKT_CMDQ(x)                                               \
+	(((x) >> BIT_SHIFT_HEAD_PKT_CMDQ) & BIT_MASK_HEAD_PKT_CMDQ)
+#define BIT_SET_HEAD_PKT_CMDQ(x, v)                                            \
+	(BIT_CLEAR_HEAD_PKT_CMDQ(x) | BIT_HEAD_PKT_CMDQ(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_CMDQ_INFO				(Offset 0x0464) */
+
+#define BIT_SHIFT_HEAD_PKT_CMDQ_V1 0
+#define BIT_MASK_HEAD_PKT_CMDQ_V1 0x7ff
+#define BIT_HEAD_PKT_CMDQ_V1(x)                                                \
+	(((x) & BIT_MASK_HEAD_PKT_CMDQ_V1) << BIT_SHIFT_HEAD_PKT_CMDQ_V1)
+#define BITS_HEAD_PKT_CMDQ_V1                                                  \
+	(BIT_MASK_HEAD_PKT_CMDQ_V1 << BIT_SHIFT_HEAD_PKT_CMDQ_V1)
+#define BIT_CLEAR_HEAD_PKT_CMDQ_V1(x) ((x) & (~BITS_HEAD_PKT_CMDQ_V1))
+#define BIT_GET_HEAD_PKT_CMDQ_V1(x)                                            \
+	(((x) >> BIT_SHIFT_HEAD_PKT_CMDQ_V1) & BIT_MASK_HEAD_PKT_CMDQ_V1)
+#define BIT_SET_HEAD_PKT_CMDQ_V1(x, v)                                         \
+	(BIT_CLEAR_HEAD_PKT_CMDQ_V1(x) | BIT_HEAD_PKT_CMDQ_V1(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_NEW_EDCA_CTRL_V1			(Offset 0x0464) */
+
+#define BIT_SHIFT_MEDIUM_HAS_IDKE_TRIGGER 0
+#define BIT_MASK_MEDIUM_HAS_IDKE_TRIGGER 0xff
+#define BIT_MEDIUM_HAS_IDKE_TRIGGER(x)                                         \
+	(((x) & BIT_MASK_MEDIUM_HAS_IDKE_TRIGGER)                              \
+	 << BIT_SHIFT_MEDIUM_HAS_IDKE_TRIGGER)
+#define BITS_MEDIUM_HAS_IDKE_TRIGGER                                           \
+	(BIT_MASK_MEDIUM_HAS_IDKE_TRIGGER << BIT_SHIFT_MEDIUM_HAS_IDKE_TRIGGER)
+#define BIT_CLEAR_MEDIUM_HAS_IDKE_TRIGGER(x)                                   \
+	((x) & (~BITS_MEDIUM_HAS_IDKE_TRIGGER))
+#define BIT_GET_MEDIUM_HAS_IDKE_TRIGGER(x)                                     \
+	(((x) >> BIT_SHIFT_MEDIUM_HAS_IDKE_TRIGGER) &                          \
+	 BIT_MASK_MEDIUM_HAS_IDKE_TRIGGER)
+#define BIT_SET_MEDIUM_HAS_IDKE_TRIGGER(x, v)                                  \
+	(BIT_CLEAR_MEDIUM_HAS_IDKE_TRIGGER(x) | BIT_MEDIUM_HAS_IDKE_TRIGGER(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_Q4_INFO				(Offset 0x0468) */
+
+#define BIT_SHIFT_QUEUEMACID_Q4_V1 25
+#define BIT_MASK_QUEUEMACID_Q4_V1 0x7f
+#define BIT_QUEUEMACID_Q4_V1(x)                                                \
+	(((x) & BIT_MASK_QUEUEMACID_Q4_V1) << BIT_SHIFT_QUEUEMACID_Q4_V1)
+#define BITS_QUEUEMACID_Q4_V1                                                  \
+	(BIT_MASK_QUEUEMACID_Q4_V1 << BIT_SHIFT_QUEUEMACID_Q4_V1)
+#define BIT_CLEAR_QUEUEMACID_Q4_V1(x) ((x) & (~BITS_QUEUEMACID_Q4_V1))
+#define BIT_GET_QUEUEMACID_Q4_V1(x)                                            \
+	(((x) >> BIT_SHIFT_QUEUEMACID_Q4_V1) & BIT_MASK_QUEUEMACID_Q4_V1)
+#define BIT_SET_QUEUEMACID_Q4_V1(x, v)                                         \
+	(BIT_CLEAR_QUEUEMACID_Q4_V1(x) | BIT_QUEUEMACID_Q4_V1(v))
+
+#define BIT_SHIFT_QUEUEAC_Q4_V1 23
+#define BIT_MASK_QUEUEAC_Q4_V1 0x3
+#define BIT_QUEUEAC_Q4_V1(x)                                                   \
+	(((x) & BIT_MASK_QUEUEAC_Q4_V1) << BIT_SHIFT_QUEUEAC_Q4_V1)
+#define BITS_QUEUEAC_Q4_V1 (BIT_MASK_QUEUEAC_Q4_V1 << BIT_SHIFT_QUEUEAC_Q4_V1)
+#define BIT_CLEAR_QUEUEAC_Q4_V1(x) ((x) & (~BITS_QUEUEAC_Q4_V1))
+#define BIT_GET_QUEUEAC_Q4_V1(x)                                               \
+	(((x) >> BIT_SHIFT_QUEUEAC_Q4_V1) & BIT_MASK_QUEUEAC_Q4_V1)
+#define BIT_SET_QUEUEAC_Q4_V1(x, v)                                            \
+	(BIT_CLEAR_QUEUEAC_Q4_V1(x) | BIT_QUEUEAC_Q4_V1(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_Q4_INFO				(Offset 0x0468) */
+
+#define BIT_TIDEMPTY_Q4_V1 BIT(22)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_ACQ_STOP_V2				(Offset 0x0468) */
+
+#define BIT_AC19Q_STOP BIT(19)
+#define BIT_AC18Q_STOP BIT(18)
+#define BIT_AC17Q_STOP BIT(17)
+#define BIT_AC16Q_STOP BIT(16)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_Q4_INFO				(Offset 0x0468) */
+
+#define BIT_SHIFT_TAIL_PKT_Q4_V1 15
+#define BIT_MASK_TAIL_PKT_Q4_V1 0xff
+#define BIT_TAIL_PKT_Q4_V1(x)                                                  \
+	(((x) & BIT_MASK_TAIL_PKT_Q4_V1) << BIT_SHIFT_TAIL_PKT_Q4_V1)
+#define BITS_TAIL_PKT_Q4_V1                                                    \
+	(BIT_MASK_TAIL_PKT_Q4_V1 << BIT_SHIFT_TAIL_PKT_Q4_V1)
+#define BIT_CLEAR_TAIL_PKT_Q4_V1(x) ((x) & (~BITS_TAIL_PKT_Q4_V1))
+#define BIT_GET_TAIL_PKT_Q4_V1(x)                                              \
+	(((x) >> BIT_SHIFT_TAIL_PKT_Q4_V1) & BIT_MASK_TAIL_PKT_Q4_V1)
+#define BIT_SET_TAIL_PKT_Q4_V1(x, v)                                           \
+	(BIT_CLEAR_TAIL_PKT_Q4_V1(x) | BIT_TAIL_PKT_Q4_V1(v))
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT)
+
+/* 2 REG_ACQ_STOP_V2				(Offset 0x0468) */
+
+#define BIT_AC15Q_STOP BIT(15)
+#define BIT_AC14Q_STOP BIT(14)
+#define BIT_AC13Q_STOP BIT(13)
+#define BIT_AC12Q_STOP BIT(12)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_Q4_INFO				(Offset 0x0468) */
+
+#define BIT_SHIFT_TAIL_PKT_Q4_V2 11
+#define BIT_MASK_TAIL_PKT_Q4_V2 0x7ff
+#define BIT_TAIL_PKT_Q4_V2(x)                                                  \
+	(((x) & BIT_MASK_TAIL_PKT_Q4_V2) << BIT_SHIFT_TAIL_PKT_Q4_V2)
+#define BITS_TAIL_PKT_Q4_V2                                                    \
+	(BIT_MASK_TAIL_PKT_Q4_V2 << BIT_SHIFT_TAIL_PKT_Q4_V2)
+#define BIT_CLEAR_TAIL_PKT_Q4_V2(x) ((x) & (~BITS_TAIL_PKT_Q4_V2))
+#define BIT_GET_TAIL_PKT_Q4_V2(x)                                              \
+	(((x) >> BIT_SHIFT_TAIL_PKT_Q4_V2) & BIT_MASK_TAIL_PKT_Q4_V2)
+#define BIT_SET_TAIL_PKT_Q4_V2(x, v)                                           \
+	(BIT_CLEAR_TAIL_PKT_Q4_V2(x) | BIT_TAIL_PKT_Q4_V2(v))
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT)
+
+/* 2 REG_ACQ_STOP_V2				(Offset 0x0468) */
+
+#define BIT_AC11Q_STOP BIT(11)
+#define BIT_AC10Q_STOP BIT(10)
+#define BIT_AC9Q_STOP BIT(9)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_Q4_INFO				(Offset 0x0468) */
+
+#define BIT_SHIFT_PKT_NUM_Q4_V1 8
+#define BIT_MASK_PKT_NUM_Q4_V1 0x7f
+#define BIT_PKT_NUM_Q4_V1(x)                                                   \
+	(((x) & BIT_MASK_PKT_NUM_Q4_V1) << BIT_SHIFT_PKT_NUM_Q4_V1)
+#define BITS_PKT_NUM_Q4_V1 (BIT_MASK_PKT_NUM_Q4_V1 << BIT_SHIFT_PKT_NUM_Q4_V1)
+#define BIT_CLEAR_PKT_NUM_Q4_V1(x) ((x) & (~BITS_PKT_NUM_Q4_V1))
+#define BIT_GET_PKT_NUM_Q4_V1(x)                                               \
+	(((x) >> BIT_SHIFT_PKT_NUM_Q4_V1) & BIT_MASK_PKT_NUM_Q4_V1)
+#define BIT_SET_PKT_NUM_Q4_V1(x, v)                                            \
+	(BIT_CLEAR_PKT_NUM_Q4_V1(x) | BIT_PKT_NUM_Q4_V1(v))
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT)
+
+/* 2 REG_ACQ_STOP_V2				(Offset 0x0468) */
+
+#define BIT_AC8Q_STOP BIT(8)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_Q4_INFO				(Offset 0x0468) */
+
+#define BIT_SHIFT_HEAD_PKT_Q4 0
+#define BIT_MASK_HEAD_PKT_Q4 0xff
+#define BIT_HEAD_PKT_Q4(x)                                                     \
+	(((x) & BIT_MASK_HEAD_PKT_Q4) << BIT_SHIFT_HEAD_PKT_Q4)
+#define BITS_HEAD_PKT_Q4 (BIT_MASK_HEAD_PKT_Q4 << BIT_SHIFT_HEAD_PKT_Q4)
+#define BIT_CLEAR_HEAD_PKT_Q4(x) ((x) & (~BITS_HEAD_PKT_Q4))
+#define BIT_GET_HEAD_PKT_Q4(x)                                                 \
+	(((x) >> BIT_SHIFT_HEAD_PKT_Q4) & BIT_MASK_HEAD_PKT_Q4)
+#define BIT_SET_HEAD_PKT_Q4(x, v)                                              \
+	(BIT_CLEAR_HEAD_PKT_Q4(x) | BIT_HEAD_PKT_Q4(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_Q4_INFO				(Offset 0x0468) */
+
+#define BIT_SHIFT_HEAD_PKT_Q4_V1 0
+#define BIT_MASK_HEAD_PKT_Q4_V1 0x7ff
+#define BIT_HEAD_PKT_Q4_V1(x)                                                  \
+	(((x) & BIT_MASK_HEAD_PKT_Q4_V1) << BIT_SHIFT_HEAD_PKT_Q4_V1)
+#define BITS_HEAD_PKT_Q4_V1                                                    \
+	(BIT_MASK_HEAD_PKT_Q4_V1 << BIT_SHIFT_HEAD_PKT_Q4_V1)
+#define BIT_CLEAR_HEAD_PKT_Q4_V1(x) ((x) & (~BITS_HEAD_PKT_Q4_V1))
+#define BIT_GET_HEAD_PKT_Q4_V1(x)                                              \
+	(((x) >> BIT_SHIFT_HEAD_PKT_Q4_V1) & BIT_MASK_HEAD_PKT_Q4_V1)
+#define BIT_SET_HEAD_PKT_Q4_V1(x, v)                                           \
+	(BIT_CLEAR_HEAD_PKT_Q4_V1(x) | BIT_HEAD_PKT_Q4_V1(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_Q5_INFO				(Offset 0x046C) */
+
+#define BIT_SHIFT_QUEUEMACID_Q5_V1 25
+#define BIT_MASK_QUEUEMACID_Q5_V1 0x7f
+#define BIT_QUEUEMACID_Q5_V1(x)                                                \
+	(((x) & BIT_MASK_QUEUEMACID_Q5_V1) << BIT_SHIFT_QUEUEMACID_Q5_V1)
+#define BITS_QUEUEMACID_Q5_V1                                                  \
+	(BIT_MASK_QUEUEMACID_Q5_V1 << BIT_SHIFT_QUEUEMACID_Q5_V1)
+#define BIT_CLEAR_QUEUEMACID_Q5_V1(x) ((x) & (~BITS_QUEUEMACID_Q5_V1))
+#define BIT_GET_QUEUEMACID_Q5_V1(x)                                            \
+	(((x) >> BIT_SHIFT_QUEUEMACID_Q5_V1) & BIT_MASK_QUEUEMACID_Q5_V1)
+#define BIT_SET_QUEUEMACID_Q5_V1(x, v)                                         \
+	(BIT_CLEAR_QUEUEMACID_Q5_V1(x) | BIT_QUEUEMACID_Q5_V1(v))
+
+#define BIT_SHIFT_QUEUEAC_Q5_V1 23
+#define BIT_MASK_QUEUEAC_Q5_V1 0x3
+#define BIT_QUEUEAC_Q5_V1(x)                                                   \
+	(((x) & BIT_MASK_QUEUEAC_Q5_V1) << BIT_SHIFT_QUEUEAC_Q5_V1)
+#define BITS_QUEUEAC_Q5_V1 (BIT_MASK_QUEUEAC_Q5_V1 << BIT_SHIFT_QUEUEAC_Q5_V1)
+#define BIT_CLEAR_QUEUEAC_Q5_V1(x) ((x) & (~BITS_QUEUEAC_Q5_V1))
+#define BIT_GET_QUEUEAC_Q5_V1(x)                                               \
+	(((x) >> BIT_SHIFT_QUEUEAC_Q5_V1) & BIT_MASK_QUEUEAC_Q5_V1)
+#define BIT_SET_QUEUEAC_Q5_V1(x, v)                                            \
+	(BIT_CLEAR_QUEUEAC_Q5_V1(x) | BIT_QUEUEAC_Q5_V1(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_Q5_INFO				(Offset 0x046C) */
+
+#define BIT_TIDEMPTY_Q5_V1 BIT(22)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_Q5_INFO				(Offset 0x046C) */
+
+#define BIT_SHIFT_TAIL_PKT_Q5_V1 15
+#define BIT_MASK_TAIL_PKT_Q5_V1 0xff
+#define BIT_TAIL_PKT_Q5_V1(x)                                                  \
+	(((x) & BIT_MASK_TAIL_PKT_Q5_V1) << BIT_SHIFT_TAIL_PKT_Q5_V1)
+#define BITS_TAIL_PKT_Q5_V1                                                    \
+	(BIT_MASK_TAIL_PKT_Q5_V1 << BIT_SHIFT_TAIL_PKT_Q5_V1)
+#define BIT_CLEAR_TAIL_PKT_Q5_V1(x) ((x) & (~BITS_TAIL_PKT_Q5_V1))
+#define BIT_GET_TAIL_PKT_Q5_V1(x)                                              \
+	(((x) >> BIT_SHIFT_TAIL_PKT_Q5_V1) & BIT_MASK_TAIL_PKT_Q5_V1)
+#define BIT_SET_TAIL_PKT_Q5_V1(x, v)                                           \
+	(BIT_CLEAR_TAIL_PKT_Q5_V1(x) | BIT_TAIL_PKT_Q5_V1(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_Q5_INFO				(Offset 0x046C) */
+
+#define BIT_SHIFT_TAIL_PKT_Q5_V2 11
+#define BIT_MASK_TAIL_PKT_Q5_V2 0x7ff
+#define BIT_TAIL_PKT_Q5_V2(x)                                                  \
+	(((x) & BIT_MASK_TAIL_PKT_Q5_V2) << BIT_SHIFT_TAIL_PKT_Q5_V2)
+#define BITS_TAIL_PKT_Q5_V2                                                    \
+	(BIT_MASK_TAIL_PKT_Q5_V2 << BIT_SHIFT_TAIL_PKT_Q5_V2)
+#define BIT_CLEAR_TAIL_PKT_Q5_V2(x) ((x) & (~BITS_TAIL_PKT_Q5_V2))
+#define BIT_GET_TAIL_PKT_Q5_V2(x)                                              \
+	(((x) >> BIT_SHIFT_TAIL_PKT_Q5_V2) & BIT_MASK_TAIL_PKT_Q5_V2)
+#define BIT_SET_TAIL_PKT_Q5_V2(x, v)                                           \
+	(BIT_CLEAR_TAIL_PKT_Q5_V2(x) | BIT_TAIL_PKT_Q5_V2(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_Q5_INFO				(Offset 0x046C) */
+
+#define BIT_SHIFT_PKT_NUM_Q5_V1 8
+#define BIT_MASK_PKT_NUM_Q5_V1 0x7f
+#define BIT_PKT_NUM_Q5_V1(x)                                                   \
+	(((x) & BIT_MASK_PKT_NUM_Q5_V1) << BIT_SHIFT_PKT_NUM_Q5_V1)
+#define BITS_PKT_NUM_Q5_V1 (BIT_MASK_PKT_NUM_Q5_V1 << BIT_SHIFT_PKT_NUM_Q5_V1)
+#define BIT_CLEAR_PKT_NUM_Q5_V1(x) ((x) & (~BITS_PKT_NUM_Q5_V1))
+#define BIT_GET_PKT_NUM_Q5_V1(x)                                               \
+	(((x) >> BIT_SHIFT_PKT_NUM_Q5_V1) & BIT_MASK_PKT_NUM_Q5_V1)
+#define BIT_SET_PKT_NUM_Q5_V1(x, v)                                            \
+	(BIT_CLEAR_PKT_NUM_Q5_V1(x) | BIT_PKT_NUM_Q5_V1(v))
+
+#define BIT_SHIFT_HEAD_PKT_Q5 0
+#define BIT_MASK_HEAD_PKT_Q5 0xff
+#define BIT_HEAD_PKT_Q5(x)                                                     \
+	(((x) & BIT_MASK_HEAD_PKT_Q5) << BIT_SHIFT_HEAD_PKT_Q5)
+#define BITS_HEAD_PKT_Q5 (BIT_MASK_HEAD_PKT_Q5 << BIT_SHIFT_HEAD_PKT_Q5)
+#define BIT_CLEAR_HEAD_PKT_Q5(x) ((x) & (~BITS_HEAD_PKT_Q5))
+#define BIT_GET_HEAD_PKT_Q5(x)                                                 \
+	(((x) >> BIT_SHIFT_HEAD_PKT_Q5) & BIT_MASK_HEAD_PKT_Q5)
+#define BIT_SET_HEAD_PKT_Q5(x, v)                                              \
+	(BIT_CLEAR_HEAD_PKT_Q5(x) | BIT_HEAD_PKT_Q5(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_Q5_INFO				(Offset 0x046C) */
+
+#define BIT_SHIFT_HEAD_PKT_Q5_V1 0
+#define BIT_MASK_HEAD_PKT_Q5_V1 0x7ff
+#define BIT_HEAD_PKT_Q5_V1(x)                                                  \
+	(((x) & BIT_MASK_HEAD_PKT_Q5_V1) << BIT_SHIFT_HEAD_PKT_Q5_V1)
+#define BITS_HEAD_PKT_Q5_V1                                                    \
+	(BIT_MASK_HEAD_PKT_Q5_V1 << BIT_SHIFT_HEAD_PKT_Q5_V1)
+#define BIT_CLEAR_HEAD_PKT_Q5_V1(x) ((x) & (~BITS_HEAD_PKT_Q5_V1))
+#define BIT_GET_HEAD_PKT_Q5_V1(x)                                              \
+	(((x) >> BIT_SHIFT_HEAD_PKT_Q5_V1) & BIT_MASK_HEAD_PKT_Q5_V1)
+#define BIT_SET_HEAD_PKT_Q5_V1(x, v)                                           \
+	(BIT_CLEAR_HEAD_PKT_Q5_V1(x) | BIT_HEAD_PKT_Q5_V1(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_Q6_INFO				(Offset 0x0470) */
+
+#define BIT_SHIFT_QUEUEMACID_Q6_V1 25
+#define BIT_MASK_QUEUEMACID_Q6_V1 0x7f
+#define BIT_QUEUEMACID_Q6_V1(x)                                                \
+	(((x) & BIT_MASK_QUEUEMACID_Q6_V1) << BIT_SHIFT_QUEUEMACID_Q6_V1)
+#define BITS_QUEUEMACID_Q6_V1                                                  \
+	(BIT_MASK_QUEUEMACID_Q6_V1 << BIT_SHIFT_QUEUEMACID_Q6_V1)
+#define BIT_CLEAR_QUEUEMACID_Q6_V1(x) ((x) & (~BITS_QUEUEMACID_Q6_V1))
+#define BIT_GET_QUEUEMACID_Q6_V1(x)                                            \
+	(((x) >> BIT_SHIFT_QUEUEMACID_Q6_V1) & BIT_MASK_QUEUEMACID_Q6_V1)
+#define BIT_SET_QUEUEMACID_Q6_V1(x, v)                                         \
+	(BIT_CLEAR_QUEUEMACID_Q6_V1(x) | BIT_QUEUEMACID_Q6_V1(v))
+
+#define BIT_SHIFT_QUEUEAC_Q6_V1 23
+#define BIT_MASK_QUEUEAC_Q6_V1 0x3
+#define BIT_QUEUEAC_Q6_V1(x)                                                   \
+	(((x) & BIT_MASK_QUEUEAC_Q6_V1) << BIT_SHIFT_QUEUEAC_Q6_V1)
+#define BITS_QUEUEAC_Q6_V1 (BIT_MASK_QUEUEAC_Q6_V1 << BIT_SHIFT_QUEUEAC_Q6_V1)
+#define BIT_CLEAR_QUEUEAC_Q6_V1(x) ((x) & (~BITS_QUEUEAC_Q6_V1))
+#define BIT_GET_QUEUEAC_Q6_V1(x)                                               \
+	(((x) >> BIT_SHIFT_QUEUEAC_Q6_V1) & BIT_MASK_QUEUEAC_Q6_V1)
+#define BIT_SET_QUEUEAC_Q6_V1(x, v)                                            \
+	(BIT_CLEAR_QUEUEAC_Q6_V1(x) | BIT_QUEUEAC_Q6_V1(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_Q6_INFO				(Offset 0x0470) */
+
+#define BIT_TIDEMPTY_Q6_V1 BIT(22)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_Q6_INFO				(Offset 0x0470) */
+
+#define BIT_SHIFT_TAIL_PKT_Q6_V1 15
+#define BIT_MASK_TAIL_PKT_Q6_V1 0xff
+#define BIT_TAIL_PKT_Q6_V1(x)                                                  \
+	(((x) & BIT_MASK_TAIL_PKT_Q6_V1) << BIT_SHIFT_TAIL_PKT_Q6_V1)
+#define BITS_TAIL_PKT_Q6_V1                                                    \
+	(BIT_MASK_TAIL_PKT_Q6_V1 << BIT_SHIFT_TAIL_PKT_Q6_V1)
+#define BIT_CLEAR_TAIL_PKT_Q6_V1(x) ((x) & (~BITS_TAIL_PKT_Q6_V1))
+#define BIT_GET_TAIL_PKT_Q6_V1(x)                                              \
+	(((x) >> BIT_SHIFT_TAIL_PKT_Q6_V1) & BIT_MASK_TAIL_PKT_Q6_V1)
+#define BIT_SET_TAIL_PKT_Q6_V1(x, v)                                           \
+	(BIT_CLEAR_TAIL_PKT_Q6_V1(x) | BIT_TAIL_PKT_Q6_V1(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_Q6_INFO				(Offset 0x0470) */
+
+#define BIT_SHIFT_TAIL_PKT_Q6_V2 11
+#define BIT_MASK_TAIL_PKT_Q6_V2 0x7ff
+#define BIT_TAIL_PKT_Q6_V2(x)                                                  \
+	(((x) & BIT_MASK_TAIL_PKT_Q6_V2) << BIT_SHIFT_TAIL_PKT_Q6_V2)
+#define BITS_TAIL_PKT_Q6_V2                                                    \
+	(BIT_MASK_TAIL_PKT_Q6_V2 << BIT_SHIFT_TAIL_PKT_Q6_V2)
+#define BIT_CLEAR_TAIL_PKT_Q6_V2(x) ((x) & (~BITS_TAIL_PKT_Q6_V2))
+#define BIT_GET_TAIL_PKT_Q6_V2(x)                                              \
+	(((x) >> BIT_SHIFT_TAIL_PKT_Q6_V2) & BIT_MASK_TAIL_PKT_Q6_V2)
+#define BIT_SET_TAIL_PKT_Q6_V2(x, v)                                           \
+	(BIT_CLEAR_TAIL_PKT_Q6_V2(x) | BIT_TAIL_PKT_Q6_V2(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_Q6_INFO				(Offset 0x0470) */
+
+#define BIT_SHIFT_PKT_NUM_Q6_V1 8
+#define BIT_MASK_PKT_NUM_Q6_V1 0x7f
+#define BIT_PKT_NUM_Q6_V1(x)                                                   \
+	(((x) & BIT_MASK_PKT_NUM_Q6_V1) << BIT_SHIFT_PKT_NUM_Q6_V1)
+#define BITS_PKT_NUM_Q6_V1 (BIT_MASK_PKT_NUM_Q6_V1 << BIT_SHIFT_PKT_NUM_Q6_V1)
+#define BIT_CLEAR_PKT_NUM_Q6_V1(x) ((x) & (~BITS_PKT_NUM_Q6_V1))
+#define BIT_GET_PKT_NUM_Q6_V1(x)                                               \
+	(((x) >> BIT_SHIFT_PKT_NUM_Q6_V1) & BIT_MASK_PKT_NUM_Q6_V1)
+#define BIT_SET_PKT_NUM_Q6_V1(x, v)                                            \
+	(BIT_CLEAR_PKT_NUM_Q6_V1(x) | BIT_PKT_NUM_Q6_V1(v))
+
+#define BIT_SHIFT_HEAD_PKT_Q6 0
+#define BIT_MASK_HEAD_PKT_Q6 0xff
+#define BIT_HEAD_PKT_Q6(x)                                                     \
+	(((x) & BIT_MASK_HEAD_PKT_Q6) << BIT_SHIFT_HEAD_PKT_Q6)
+#define BITS_HEAD_PKT_Q6 (BIT_MASK_HEAD_PKT_Q6 << BIT_SHIFT_HEAD_PKT_Q6)
+#define BIT_CLEAR_HEAD_PKT_Q6(x) ((x) & (~BITS_HEAD_PKT_Q6))
+#define BIT_GET_HEAD_PKT_Q6(x)                                                 \
+	(((x) >> BIT_SHIFT_HEAD_PKT_Q6) & BIT_MASK_HEAD_PKT_Q6)
+#define BIT_SET_HEAD_PKT_Q6(x, v)                                              \
+	(BIT_CLEAR_HEAD_PKT_Q6(x) | BIT_HEAD_PKT_Q6(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_Q6_INFO				(Offset 0x0470) */
+
+#define BIT_SHIFT_HEAD_PKT_Q6_V1 0
+#define BIT_MASK_HEAD_PKT_Q6_V1 0x7ff
+#define BIT_HEAD_PKT_Q6_V1(x)                                                  \
+	(((x) & BIT_MASK_HEAD_PKT_Q6_V1) << BIT_SHIFT_HEAD_PKT_Q6_V1)
+#define BITS_HEAD_PKT_Q6_V1                                                    \
+	(BIT_MASK_HEAD_PKT_Q6_V1 << BIT_SHIFT_HEAD_PKT_Q6_V1)
+#define BIT_CLEAR_HEAD_PKT_Q6_V1(x) ((x) & (~BITS_HEAD_PKT_Q6_V1))
+#define BIT_GET_HEAD_PKT_Q6_V1(x)                                              \
+	(((x) >> BIT_SHIFT_HEAD_PKT_Q6_V1) & BIT_MASK_HEAD_PKT_Q6_V1)
+#define BIT_SET_HEAD_PKT_Q6_V1(x, v)                                           \
+	(BIT_CLEAR_HEAD_PKT_Q6_V1(x) | BIT_HEAD_PKT_Q6_V1(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_Q7_INFO				(Offset 0x0474) */
+
+#define BIT_SHIFT_QUEUEMACID_Q7_V1 25
+#define BIT_MASK_QUEUEMACID_Q7_V1 0x7f
+#define BIT_QUEUEMACID_Q7_V1(x)                                                \
+	(((x) & BIT_MASK_QUEUEMACID_Q7_V1) << BIT_SHIFT_QUEUEMACID_Q7_V1)
+#define BITS_QUEUEMACID_Q7_V1                                                  \
+	(BIT_MASK_QUEUEMACID_Q7_V1 << BIT_SHIFT_QUEUEMACID_Q7_V1)
+#define BIT_CLEAR_QUEUEMACID_Q7_V1(x) ((x) & (~BITS_QUEUEMACID_Q7_V1))
+#define BIT_GET_QUEUEMACID_Q7_V1(x)                                            \
+	(((x) >> BIT_SHIFT_QUEUEMACID_Q7_V1) & BIT_MASK_QUEUEMACID_Q7_V1)
+#define BIT_SET_QUEUEMACID_Q7_V1(x, v)                                         \
+	(BIT_CLEAR_QUEUEMACID_Q7_V1(x) | BIT_QUEUEMACID_Q7_V1(v))
+
+#define BIT_SHIFT_QUEUEAC_Q7_V1 23
+#define BIT_MASK_QUEUEAC_Q7_V1 0x3
+#define BIT_QUEUEAC_Q7_V1(x)                                                   \
+	(((x) & BIT_MASK_QUEUEAC_Q7_V1) << BIT_SHIFT_QUEUEAC_Q7_V1)
+#define BITS_QUEUEAC_Q7_V1 (BIT_MASK_QUEUEAC_Q7_V1 << BIT_SHIFT_QUEUEAC_Q7_V1)
+#define BIT_CLEAR_QUEUEAC_Q7_V1(x) ((x) & (~BITS_QUEUEAC_Q7_V1))
+#define BIT_GET_QUEUEAC_Q7_V1(x)                                               \
+	(((x) >> BIT_SHIFT_QUEUEAC_Q7_V1) & BIT_MASK_QUEUEAC_Q7_V1)
+#define BIT_SET_QUEUEAC_Q7_V1(x, v)                                            \
+	(BIT_CLEAR_QUEUEAC_Q7_V1(x) | BIT_QUEUEAC_Q7_V1(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_Q7_INFO				(Offset 0x0474) */
+
+#define BIT_TIDEMPTY_Q7_V1 BIT(22)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_Q7_INFO				(Offset 0x0474) */
+
+#define BIT_SHIFT_TAIL_PKT_Q7_V1 15
+#define BIT_MASK_TAIL_PKT_Q7_V1 0xff
+#define BIT_TAIL_PKT_Q7_V1(x)                                                  \
+	(((x) & BIT_MASK_TAIL_PKT_Q7_V1) << BIT_SHIFT_TAIL_PKT_Q7_V1)
+#define BITS_TAIL_PKT_Q7_V1                                                    \
+	(BIT_MASK_TAIL_PKT_Q7_V1 << BIT_SHIFT_TAIL_PKT_Q7_V1)
+#define BIT_CLEAR_TAIL_PKT_Q7_V1(x) ((x) & (~BITS_TAIL_PKT_Q7_V1))
+#define BIT_GET_TAIL_PKT_Q7_V1(x)                                              \
+	(((x) >> BIT_SHIFT_TAIL_PKT_Q7_V1) & BIT_MASK_TAIL_PKT_Q7_V1)
+#define BIT_SET_TAIL_PKT_Q7_V1(x, v)                                           \
+	(BIT_CLEAR_TAIL_PKT_Q7_V1(x) | BIT_TAIL_PKT_Q7_V1(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_Q7_INFO				(Offset 0x0474) */
+
+#define BIT_SHIFT_TAIL_PKT_Q7_V2 11
+#define BIT_MASK_TAIL_PKT_Q7_V2 0x7ff
+#define BIT_TAIL_PKT_Q7_V2(x)                                                  \
+	(((x) & BIT_MASK_TAIL_PKT_Q7_V2) << BIT_SHIFT_TAIL_PKT_Q7_V2)
+#define BITS_TAIL_PKT_Q7_V2                                                    \
+	(BIT_MASK_TAIL_PKT_Q7_V2 << BIT_SHIFT_TAIL_PKT_Q7_V2)
+#define BIT_CLEAR_TAIL_PKT_Q7_V2(x) ((x) & (~BITS_TAIL_PKT_Q7_V2))
+#define BIT_GET_TAIL_PKT_Q7_V2(x)                                              \
+	(((x) >> BIT_SHIFT_TAIL_PKT_Q7_V2) & BIT_MASK_TAIL_PKT_Q7_V2)
+#define BIT_SET_TAIL_PKT_Q7_V2(x, v)                                           \
+	(BIT_CLEAR_TAIL_PKT_Q7_V2(x) | BIT_TAIL_PKT_Q7_V2(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_Q7_INFO				(Offset 0x0474) */
+
+#define BIT_SHIFT_PKT_NUM_Q7_V1 8
+#define BIT_MASK_PKT_NUM_Q7_V1 0x7f
+#define BIT_PKT_NUM_Q7_V1(x)                                                   \
+	(((x) & BIT_MASK_PKT_NUM_Q7_V1) << BIT_SHIFT_PKT_NUM_Q7_V1)
+#define BITS_PKT_NUM_Q7_V1 (BIT_MASK_PKT_NUM_Q7_V1 << BIT_SHIFT_PKT_NUM_Q7_V1)
+#define BIT_CLEAR_PKT_NUM_Q7_V1(x) ((x) & (~BITS_PKT_NUM_Q7_V1))
+#define BIT_GET_PKT_NUM_Q7_V1(x)                                               \
+	(((x) >> BIT_SHIFT_PKT_NUM_Q7_V1) & BIT_MASK_PKT_NUM_Q7_V1)
+#define BIT_SET_PKT_NUM_Q7_V1(x, v)                                            \
+	(BIT_CLEAR_PKT_NUM_Q7_V1(x) | BIT_PKT_NUM_Q7_V1(v))
+
+#define BIT_SHIFT_HEAD_PKT_Q7 0
+#define BIT_MASK_HEAD_PKT_Q7 0xff
+#define BIT_HEAD_PKT_Q7(x)                                                     \
+	(((x) & BIT_MASK_HEAD_PKT_Q7) << BIT_SHIFT_HEAD_PKT_Q7)
+#define BITS_HEAD_PKT_Q7 (BIT_MASK_HEAD_PKT_Q7 << BIT_SHIFT_HEAD_PKT_Q7)
+#define BIT_CLEAR_HEAD_PKT_Q7(x) ((x) & (~BITS_HEAD_PKT_Q7))
+#define BIT_GET_HEAD_PKT_Q7(x)                                                 \
+	(((x) >> BIT_SHIFT_HEAD_PKT_Q7) & BIT_MASK_HEAD_PKT_Q7)
+#define BIT_SET_HEAD_PKT_Q7(x, v)                                              \
+	(BIT_CLEAR_HEAD_PKT_Q7(x) | BIT_HEAD_PKT_Q7(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_Q7_INFO				(Offset 0x0474) */
+
+#define BIT_SHIFT_HEAD_PKT_Q7_V1 0
+#define BIT_MASK_HEAD_PKT_Q7_V1 0x7ff
+#define BIT_HEAD_PKT_Q7_V1(x)                                                  \
+	(((x) & BIT_MASK_HEAD_PKT_Q7_V1) << BIT_SHIFT_HEAD_PKT_Q7_V1)
+#define BITS_HEAD_PKT_Q7_V1                                                    \
+	(BIT_MASK_HEAD_PKT_Q7_V1 << BIT_SHIFT_HEAD_PKT_Q7_V1)
+#define BIT_CLEAR_HEAD_PKT_Q7_V1(x) ((x) & (~BITS_HEAD_PKT_Q7_V1))
+#define BIT_GET_HEAD_PKT_Q7_V1(x)                                              \
+	(((x) >> BIT_SHIFT_HEAD_PKT_Q7_V1) & BIT_MASK_HEAD_PKT_Q7_V1)
+#define BIT_SET_HEAD_PKT_Q7_V1(x, v)                                           \
+	(BIT_CLEAR_HEAD_PKT_Q7_V1(x) | BIT_HEAD_PKT_Q7_V1(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_WMAC_LBK_BUF_HD_V1			(Offset 0x0478) */
+
+#define BIT_SHIFT_WMAC_LBK_BUF_HEAD_V1 0
+#define BIT_MASK_WMAC_LBK_BUF_HEAD_V1 0xfff
+#define BIT_WMAC_LBK_BUF_HEAD_V1(x)                                            \
+	(((x) & BIT_MASK_WMAC_LBK_BUF_HEAD_V1)                                 \
+	 << BIT_SHIFT_WMAC_LBK_BUF_HEAD_V1)
+#define BITS_WMAC_LBK_BUF_HEAD_V1                                              \
+	(BIT_MASK_WMAC_LBK_BUF_HEAD_V1 << BIT_SHIFT_WMAC_LBK_BUF_HEAD_V1)
+#define BIT_CLEAR_WMAC_LBK_BUF_HEAD_V1(x) ((x) & (~BITS_WMAC_LBK_BUF_HEAD_V1))
+#define BIT_GET_WMAC_LBK_BUF_HEAD_V1(x)                                        \
+	(((x) >> BIT_SHIFT_WMAC_LBK_BUF_HEAD_V1) &                             \
+	 BIT_MASK_WMAC_LBK_BUF_HEAD_V1)
+#define BIT_SET_WMAC_LBK_BUF_HEAD_V1(x, v)                                     \
+	(BIT_CLEAR_WMAC_LBK_BUF_HEAD_V1(x) | BIT_WMAC_LBK_BUF_HEAD_V1(v))
+
+/* 2 REG_MGQ_BDNY_V1				(Offset 0x047A) */
+
+#define BIT_SHIFT_MGQ_PGBNDY_V1 0
+#define BIT_MASK_MGQ_PGBNDY_V1 0xfff
+#define BIT_MGQ_PGBNDY_V1(x)                                                   \
+	(((x) & BIT_MASK_MGQ_PGBNDY_V1) << BIT_SHIFT_MGQ_PGBNDY_V1)
+#define BITS_MGQ_PGBNDY_V1 (BIT_MASK_MGQ_PGBNDY_V1 << BIT_SHIFT_MGQ_PGBNDY_V1)
+#define BIT_CLEAR_MGQ_PGBNDY_V1(x) ((x) & (~BITS_MGQ_PGBNDY_V1))
+#define BIT_GET_MGQ_PGBNDY_V1(x)                                               \
+	(((x) >> BIT_SHIFT_MGQ_PGBNDY_V1) & BIT_MASK_MGQ_PGBNDY_V1)
+#define BIT_SET_MGQ_PGBNDY_V1(x, v)                                            \
+	(BIT_CLEAR_MGQ_PGBNDY_V1(x) | BIT_MGQ_PGBNDY_V1(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_TXRPT_CTRL				(Offset 0x047C) */
+
+#define BIT_SHIFT_SPC_READ_PTR 24
+#define BIT_MASK_SPC_READ_PTR 0xf
+#define BIT_SPC_READ_PTR(x)                                                    \
+	(((x) & BIT_MASK_SPC_READ_PTR) << BIT_SHIFT_SPC_READ_PTR)
+#define BITS_SPC_READ_PTR (BIT_MASK_SPC_READ_PTR << BIT_SHIFT_SPC_READ_PTR)
+#define BIT_CLEAR_SPC_READ_PTR(x) ((x) & (~BITS_SPC_READ_PTR))
+#define BIT_GET_SPC_READ_PTR(x)                                                \
+	(((x) >> BIT_SHIFT_SPC_READ_PTR) & BIT_MASK_SPC_READ_PTR)
+#define BIT_SET_SPC_READ_PTR(x, v)                                             \
+	(BIT_CLEAR_SPC_READ_PTR(x) | BIT_SPC_READ_PTR(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_TXRPT_CTRL				(Offset 0x047C) */
+
+#define BIT_SHIFT_TRXRPT_TIMER_TH 24
+#define BIT_MASK_TRXRPT_TIMER_TH 0xff
+#define BIT_TRXRPT_TIMER_TH(x)                                                 \
+	(((x) & BIT_MASK_TRXRPT_TIMER_TH) << BIT_SHIFT_TRXRPT_TIMER_TH)
+#define BITS_TRXRPT_TIMER_TH                                                   \
+	(BIT_MASK_TRXRPT_TIMER_TH << BIT_SHIFT_TRXRPT_TIMER_TH)
+#define BIT_CLEAR_TRXRPT_TIMER_TH(x) ((x) & (~BITS_TRXRPT_TIMER_TH))
+#define BIT_GET_TRXRPT_TIMER_TH(x)                                             \
+	(((x) >> BIT_SHIFT_TRXRPT_TIMER_TH) & BIT_MASK_TRXRPT_TIMER_TH)
+#define BIT_SET_TRXRPT_TIMER_TH(x, v)                                          \
+	(BIT_CLEAR_TRXRPT_TIMER_TH(x) | BIT_TRXRPT_TIMER_TH(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_TXRPT_CTRL				(Offset 0x047C) */
+
+#define BIT_SHIFT_SPC_WRITE_PTR 16
+#define BIT_MASK_SPC_WRITE_PTR 0xf
+#define BIT_SPC_WRITE_PTR(x)                                                   \
+	(((x) & BIT_MASK_SPC_WRITE_PTR) << BIT_SHIFT_SPC_WRITE_PTR)
+#define BITS_SPC_WRITE_PTR (BIT_MASK_SPC_WRITE_PTR << BIT_SHIFT_SPC_WRITE_PTR)
+#define BIT_CLEAR_SPC_WRITE_PTR(x) ((x) & (~BITS_SPC_WRITE_PTR))
+#define BIT_GET_SPC_WRITE_PTR(x)                                               \
+	(((x) >> BIT_SHIFT_SPC_WRITE_PTR) & BIT_MASK_SPC_WRITE_PTR)
+#define BIT_SET_SPC_WRITE_PTR(x, v)                                            \
+	(BIT_CLEAR_SPC_WRITE_PTR(x) | BIT_SPC_WRITE_PTR(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_TXRPT_CTRL				(Offset 0x047C) */
+
+#define BIT_SHIFT_TRXRPT_LEN_TH 16
+#define BIT_MASK_TRXRPT_LEN_TH 0xff
+#define BIT_TRXRPT_LEN_TH(x)                                                   \
+	(((x) & BIT_MASK_TRXRPT_LEN_TH) << BIT_SHIFT_TRXRPT_LEN_TH)
+#define BITS_TRXRPT_LEN_TH (BIT_MASK_TRXRPT_LEN_TH << BIT_SHIFT_TRXRPT_LEN_TH)
+#define BIT_CLEAR_TRXRPT_LEN_TH(x) ((x) & (~BITS_TRXRPT_LEN_TH))
+#define BIT_GET_TRXRPT_LEN_TH(x)                                               \
+	(((x) >> BIT_SHIFT_TRXRPT_LEN_TH) & BIT_MASK_TRXRPT_LEN_TH)
+#define BIT_SET_TRXRPT_LEN_TH(x, v)                                            \
+	(BIT_CLEAR_TRXRPT_LEN_TH(x) | BIT_TRXRPT_LEN_TH(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_TXRPT_CTRL				(Offset 0x047C) */
+
+#define BIT_SHIFT_AC_READ_PTR 8
+#define BIT_MASK_AC_READ_PTR 0xf
+#define BIT_AC_READ_PTR(x)                                                     \
+	(((x) & BIT_MASK_AC_READ_PTR) << BIT_SHIFT_AC_READ_PTR)
+#define BITS_AC_READ_PTR (BIT_MASK_AC_READ_PTR << BIT_SHIFT_AC_READ_PTR)
+#define BIT_CLEAR_AC_READ_PTR(x) ((x) & (~BITS_AC_READ_PTR))
+#define BIT_GET_AC_READ_PTR(x)                                                 \
+	(((x) >> BIT_SHIFT_AC_READ_PTR) & BIT_MASK_AC_READ_PTR)
+#define BIT_SET_AC_READ_PTR(x, v)                                              \
+	(BIT_CLEAR_AC_READ_PTR(x) | BIT_AC_READ_PTR(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_TXRPT_CTRL				(Offset 0x047C) */
+
+#define BIT_SHIFT_TRXRPT_READ_PTR 8
+#define BIT_MASK_TRXRPT_READ_PTR 0xff
+#define BIT_TRXRPT_READ_PTR(x)                                                 \
+	(((x) & BIT_MASK_TRXRPT_READ_PTR) << BIT_SHIFT_TRXRPT_READ_PTR)
+#define BITS_TRXRPT_READ_PTR                                                   \
+	(BIT_MASK_TRXRPT_READ_PTR << BIT_SHIFT_TRXRPT_READ_PTR)
+#define BIT_CLEAR_TRXRPT_READ_PTR(x) ((x) & (~BITS_TRXRPT_READ_PTR))
+#define BIT_GET_TRXRPT_READ_PTR(x)                                             \
+	(((x) >> BIT_SHIFT_TRXRPT_READ_PTR) & BIT_MASK_TRXRPT_READ_PTR)
+#define BIT_SET_TRXRPT_READ_PTR(x, v)                                          \
+	(BIT_CLEAR_TRXRPT_READ_PTR(x) | BIT_TRXRPT_READ_PTR(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_TXRPT_CTRL				(Offset 0x047C) */
+
+#define BIT_SHIFT_AC_WRITE_PTR 0
+#define BIT_MASK_AC_WRITE_PTR 0xf
+#define BIT_AC_WRITE_PTR(x)                                                    \
+	(((x) & BIT_MASK_AC_WRITE_PTR) << BIT_SHIFT_AC_WRITE_PTR)
+#define BITS_AC_WRITE_PTR (BIT_MASK_AC_WRITE_PTR << BIT_SHIFT_AC_WRITE_PTR)
+#define BIT_CLEAR_AC_WRITE_PTR(x) ((x) & (~BITS_AC_WRITE_PTR))
+#define BIT_GET_AC_WRITE_PTR(x)                                                \
+	(((x) >> BIT_SHIFT_AC_WRITE_PTR) & BIT_MASK_AC_WRITE_PTR)
+#define BIT_SET_AC_WRITE_PTR(x, v)                                             \
+	(BIT_CLEAR_AC_WRITE_PTR(x) | BIT_AC_WRITE_PTR(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_TXRPT_CTRL				(Offset 0x047C) */
+
+#define BIT_SHIFT_TRXRPT_WRITE_PTR 0
+#define BIT_MASK_TRXRPT_WRITE_PTR 0xff
+#define BIT_TRXRPT_WRITE_PTR(x)                                                \
+	(((x) & BIT_MASK_TRXRPT_WRITE_PTR) << BIT_SHIFT_TRXRPT_WRITE_PTR)
+#define BITS_TRXRPT_WRITE_PTR                                                  \
+	(BIT_MASK_TRXRPT_WRITE_PTR << BIT_SHIFT_TRXRPT_WRITE_PTR)
+#define BIT_CLEAR_TRXRPT_WRITE_PTR(x) ((x) & (~BITS_TRXRPT_WRITE_PTR))
+#define BIT_GET_TRXRPT_WRITE_PTR(x)                                            \
+	(((x) >> BIT_SHIFT_TRXRPT_WRITE_PTR) & BIT_MASK_TRXRPT_WRITE_PTR)
+#define BIT_SET_TRXRPT_WRITE_PTR(x, v)                                         \
+	(BIT_CLEAR_TRXRPT_WRITE_PTR(x) | BIT_TRXRPT_WRITE_PTR(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_INIRTS_RATE_SEL			(Offset 0x0480) */
+
+#define BIT_LEAG_RTS_BW_DUP BIT(5)
+
+/* 2 REG_BASIC_CFEND_RATE			(Offset 0x0481) */
+
+#define BIT_SHIFT_BASIC_CFEND_RATE 0
+#define BIT_MASK_BASIC_CFEND_RATE 0x1f
+#define BIT_BASIC_CFEND_RATE(x)                                                \
+	(((x) & BIT_MASK_BASIC_CFEND_RATE) << BIT_SHIFT_BASIC_CFEND_RATE)
+#define BITS_BASIC_CFEND_RATE                                                  \
+	(BIT_MASK_BASIC_CFEND_RATE << BIT_SHIFT_BASIC_CFEND_RATE)
+#define BIT_CLEAR_BASIC_CFEND_RATE(x) ((x) & (~BITS_BASIC_CFEND_RATE))
+#define BIT_GET_BASIC_CFEND_RATE(x)                                            \
+	(((x) >> BIT_SHIFT_BASIC_CFEND_RATE) & BIT_MASK_BASIC_CFEND_RATE)
+#define BIT_SET_BASIC_CFEND_RATE(x, v)                                         \
+	(BIT_CLEAR_BASIC_CFEND_RATE(x) | BIT_BASIC_CFEND_RATE(v))
+
+/* 2 REG_STBC_CFEND_RATE			(Offset 0x0482) */
+
+#define BIT_SHIFT_STBC_CFEND_RATE 0
+#define BIT_MASK_STBC_CFEND_RATE 0x1f
+#define BIT_STBC_CFEND_RATE(x)                                                 \
+	(((x) & BIT_MASK_STBC_CFEND_RATE) << BIT_SHIFT_STBC_CFEND_RATE)
+#define BITS_STBC_CFEND_RATE                                                   \
+	(BIT_MASK_STBC_CFEND_RATE << BIT_SHIFT_STBC_CFEND_RATE)
+#define BIT_CLEAR_STBC_CFEND_RATE(x) ((x) & (~BITS_STBC_CFEND_RATE))
+#define BIT_GET_STBC_CFEND_RATE(x)                                             \
+	(((x) >> BIT_SHIFT_STBC_CFEND_RATE) & BIT_MASK_STBC_CFEND_RATE)
+#define BIT_SET_STBC_CFEND_RATE(x, v)                                          \
+	(BIT_CLEAR_STBC_CFEND_RATE(x) | BIT_STBC_CFEND_RATE(v))
+
+/* 2 REG_DATA_SC				(Offset 0x0483) */
+
+#define BIT_SHIFT_TXSC_40M 4
+#define BIT_MASK_TXSC_40M 0xf
+#define BIT_TXSC_40M(x) (((x) & BIT_MASK_TXSC_40M) << BIT_SHIFT_TXSC_40M)
+#define BITS_TXSC_40M (BIT_MASK_TXSC_40M << BIT_SHIFT_TXSC_40M)
+#define BIT_CLEAR_TXSC_40M(x) ((x) & (~BITS_TXSC_40M))
+#define BIT_GET_TXSC_40M(x) (((x) >> BIT_SHIFT_TXSC_40M) & BIT_MASK_TXSC_40M)
+#define BIT_SET_TXSC_40M(x, v) (BIT_CLEAR_TXSC_40M(x) | BIT_TXSC_40M(v))
+
+#define BIT_SHIFT_TXSC_20M 0
+#define BIT_MASK_TXSC_20M 0xf
+#define BIT_TXSC_20M(x) (((x) & BIT_MASK_TXSC_20M) << BIT_SHIFT_TXSC_20M)
+#define BITS_TXSC_20M (BIT_MASK_TXSC_20M << BIT_SHIFT_TXSC_20M)
+#define BIT_CLEAR_TXSC_20M(x) ((x) & (~BITS_TXSC_20M))
+#define BIT_GET_TXSC_20M(x) (((x) >> BIT_SHIFT_TXSC_20M) & BIT_MASK_TXSC_20M)
+#define BIT_SET_TXSC_20M(x, v) (BIT_CLEAR_TXSC_20M(x) | BIT_TXSC_20M(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8881A_SUPPORT)
+
+/* 2 REG_MACID_SLEEP3			(Offset 0x0484) */
+
+#define BIT_SHIFT_MACID127_96_PKTSLEEP 0
+#define BIT_MASK_MACID127_96_PKTSLEEP 0xffffffffL
+#define BIT_MACID127_96_PKTSLEEP(x)                                            \
+	(((x) & BIT_MASK_MACID127_96_PKTSLEEP)                                 \
+	 << BIT_SHIFT_MACID127_96_PKTSLEEP)
+#define BITS_MACID127_96_PKTSLEEP                                              \
+	(BIT_MASK_MACID127_96_PKTSLEEP << BIT_SHIFT_MACID127_96_PKTSLEEP)
+#define BIT_CLEAR_MACID127_96_PKTSLEEP(x) ((x) & (~BITS_MACID127_96_PKTSLEEP))
+#define BIT_GET_MACID127_96_PKTSLEEP(x)                                        \
+	(((x) >> BIT_SHIFT_MACID127_96_PKTSLEEP) &                             \
+	 BIT_MASK_MACID127_96_PKTSLEEP)
+#define BIT_SET_MACID127_96_PKTSLEEP(x, v)                                     \
+	(BIT_CLEAR_MACID127_96_PKTSLEEP(x) | BIT_MACID127_96_PKTSLEEP(v))
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_MACID_SLEEP3			(Offset 0x0484) */
+
+#define BIT_SHIFT_MACID103_96_PKTSLEEP 0
+#define BIT_MASK_MACID103_96_PKTSLEEP 0xff
+#define BIT_MACID103_96_PKTSLEEP(x)                                            \
+	(((x) & BIT_MASK_MACID103_96_PKTSLEEP)                                 \
+	 << BIT_SHIFT_MACID103_96_PKTSLEEP)
+#define BITS_MACID103_96_PKTSLEEP                                              \
+	(BIT_MASK_MACID103_96_PKTSLEEP << BIT_SHIFT_MACID103_96_PKTSLEEP)
+#define BIT_CLEAR_MACID103_96_PKTSLEEP(x) ((x) & (~BITS_MACID103_96_PKTSLEEP))
+#define BIT_GET_MACID103_96_PKTSLEEP(x)                                        \
+	(((x) >> BIT_SHIFT_MACID103_96_PKTSLEEP) &                             \
+	 BIT_MASK_MACID103_96_PKTSLEEP)
+#define BIT_SET_MACID103_96_PKTSLEEP(x, v)                                     \
+	(BIT_CLEAR_MACID103_96_PKTSLEEP(x) | BIT_MACID103_96_PKTSLEEP(v))
+
+/* 2 REG_MACID_SLEEP4			(Offset 0x0485) */
+
+#define BIT_SHIFT_MACID119_104_PKTSLEEP 0
+#define BIT_MASK_MACID119_104_PKTSLEEP 0xffff
+#define BIT_MACID119_104_PKTSLEEP(x)                                           \
+	(((x) & BIT_MASK_MACID119_104_PKTSLEEP)                                \
+	 << BIT_SHIFT_MACID119_104_PKTSLEEP)
+#define BITS_MACID119_104_PKTSLEEP                                             \
+	(BIT_MASK_MACID119_104_PKTSLEEP << BIT_SHIFT_MACID119_104_PKTSLEEP)
+#define BIT_CLEAR_MACID119_104_PKTSLEEP(x) ((x) & (~BITS_MACID119_104_PKTSLEEP))
+#define BIT_GET_MACID119_104_PKTSLEEP(x)                                       \
+	(((x) >> BIT_SHIFT_MACID119_104_PKTSLEEP) &                            \
+	 BIT_MASK_MACID119_104_PKTSLEEP)
+#define BIT_SET_MACID119_104_PKTSLEEP(x, v)                                    \
+	(BIT_CLEAR_MACID119_104_PKTSLEEP(x) | BIT_MACID119_104_PKTSLEEP(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_DATA_SC1				(Offset 0x0487) */
+
+#define BIT_SHIFT_TXSC_160M 4
+#define BIT_MASK_TXSC_160M 0xf
+#define BIT_TXSC_160M(x) (((x) & BIT_MASK_TXSC_160M) << BIT_SHIFT_TXSC_160M)
+#define BITS_TXSC_160M (BIT_MASK_TXSC_160M << BIT_SHIFT_TXSC_160M)
+#define BIT_CLEAR_TXSC_160M(x) ((x) & (~BITS_TXSC_160M))
+#define BIT_GET_TXSC_160M(x) (((x) >> BIT_SHIFT_TXSC_160M) & BIT_MASK_TXSC_160M)
+#define BIT_SET_TXSC_160M(x, v) (BIT_CLEAR_TXSC_160M(x) | BIT_TXSC_160M(v))
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_MACID_SLEEP5			(Offset 0x0487) */
+
+#define BIT_SHIFT_MACID127_120_PKTSLEEP 0
+#define BIT_MASK_MACID127_120_PKTSLEEP 0xff
+#define BIT_MACID127_120_PKTSLEEP(x)                                           \
+	(((x) & BIT_MASK_MACID127_120_PKTSLEEP)                                \
+	 << BIT_SHIFT_MACID127_120_PKTSLEEP)
+#define BITS_MACID127_120_PKTSLEEP                                             \
+	(BIT_MASK_MACID127_120_PKTSLEEP << BIT_SHIFT_MACID127_120_PKTSLEEP)
+#define BIT_CLEAR_MACID127_120_PKTSLEEP(x) ((x) & (~BITS_MACID127_120_PKTSLEEP))
+#define BIT_GET_MACID127_120_PKTSLEEP(x)                                       \
+	(((x) >> BIT_SHIFT_MACID127_120_PKTSLEEP) &                            \
+	 BIT_MASK_MACID127_120_PKTSLEEP)
+#define BIT_SET_MACID127_120_PKTSLEEP(x, v)                                    \
+	(BIT_CLEAR_MACID127_120_PKTSLEEP(x) | BIT_MACID127_120_PKTSLEEP(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_DATA_SC1				(Offset 0x0487) */
+
+#define BIT_SHIFT_TXSC_80M 0
+#define BIT_MASK_TXSC_80M 0xf
+#define BIT_TXSC_80M(x) (((x) & BIT_MASK_TXSC_80M) << BIT_SHIFT_TXSC_80M)
+#define BITS_TXSC_80M (BIT_MASK_TXSC_80M << BIT_SHIFT_TXSC_80M)
+#define BIT_CLEAR_TXSC_80M(x) ((x) & (~BITS_TXSC_80M))
+#define BIT_GET_TXSC_80M(x) (((x) >> BIT_SHIFT_TXSC_80M) & BIT_MASK_TXSC_80M)
+#define BIT_SET_TXSC_80M(x, v) (BIT_CLEAR_TXSC_80M(x) | BIT_TXSC_80M(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_MACID_SLEEP1			(Offset 0x0488) */
+
+#define BIT_SHIFT_MACID63_32_PKTSLEEP 0
+#define BIT_MASK_MACID63_32_PKTSLEEP 0xffffffffL
+#define BIT_MACID63_32_PKTSLEEP(x)                                             \
+	(((x) & BIT_MASK_MACID63_32_PKTSLEEP) << BIT_SHIFT_MACID63_32_PKTSLEEP)
+#define BITS_MACID63_32_PKTSLEEP                                               \
+	(BIT_MASK_MACID63_32_PKTSLEEP << BIT_SHIFT_MACID63_32_PKTSLEEP)
+#define BIT_CLEAR_MACID63_32_PKTSLEEP(x) ((x) & (~BITS_MACID63_32_PKTSLEEP))
+#define BIT_GET_MACID63_32_PKTSLEEP(x)                                         \
+	(((x) >> BIT_SHIFT_MACID63_32_PKTSLEEP) & BIT_MASK_MACID63_32_PKTSLEEP)
+#define BIT_SET_MACID63_32_PKTSLEEP(x, v)                                      \
+	(BIT_CLEAR_MACID63_32_PKTSLEEP(x) | BIT_MACID63_32_PKTSLEEP(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT || \
+     HALMAC_8881A_SUPPORT)
+
+/* 2 REG_ARFR2_V1				(Offset 0x048C) */
+
+#define BIT_SHIFT_ARFR2_V1 0
+#define BIT_MASK_ARFR2_V1 0xffffffffffffffffL
+#define BIT_ARFR2_V1(x) (((x) & BIT_MASK_ARFR2_V1) << BIT_SHIFT_ARFR2_V1)
+#define BITS_ARFR2_V1 (BIT_MASK_ARFR2_V1 << BIT_SHIFT_ARFR2_V1)
+#define BIT_CLEAR_ARFR2_V1(x) ((x) & (~BITS_ARFR2_V1))
+#define BIT_GET_ARFR2_V1(x) (((x) >> BIT_SHIFT_ARFR2_V1) & BIT_MASK_ARFR2_V1)
+#define BIT_SET_ARFR2_V1(x, v) (BIT_CLEAR_ARFR2_V1(x) | BIT_ARFR2_V1(v))
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_ARFR2				(Offset 0x048C) */
+
+#define BIT_SHIFT_ARFRL2 0
+#define BIT_MASK_ARFRL2 0xffffffffL
+#define BIT_ARFRL2(x) (((x) & BIT_MASK_ARFRL2) << BIT_SHIFT_ARFRL2)
+#define BITS_ARFRL2 (BIT_MASK_ARFRL2 << BIT_SHIFT_ARFRL2)
+#define BIT_CLEAR_ARFRL2(x) ((x) & (~BITS_ARFRL2))
+#define BIT_GET_ARFRL2(x) (((x) >> BIT_SHIFT_ARFRL2) & BIT_MASK_ARFRL2)
+#define BIT_SET_ARFRL2(x, v) (BIT_CLEAR_ARFRL2(x) | BIT_ARFRL2(v))
+
+/* 2 REG_ARFRH2				(Offset 0x0490) */
+
+#define BIT_SHIFT_ARFRH2 0
+#define BIT_MASK_ARFRH2 0xffffffffL
+#define BIT_ARFRH2(x) (((x) & BIT_MASK_ARFRH2) << BIT_SHIFT_ARFRH2)
+#define BITS_ARFRH2 (BIT_MASK_ARFRH2 << BIT_SHIFT_ARFRH2)
+#define BIT_CLEAR_ARFRH2(x) ((x) & (~BITS_ARFRH2))
+#define BIT_GET_ARFRH2(x) (((x) >> BIT_SHIFT_ARFRH2) & BIT_MASK_ARFRH2)
+#define BIT_SET_ARFRH2(x, v) (BIT_CLEAR_ARFRH2(x) | BIT_ARFRH2(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT || \
+     HALMAC_8881A_SUPPORT)
+
+/* 2 REG_ARFR3_V1				(Offset 0x0494) */
+
+#define BIT_SHIFT_ARFR3_V1 0
+#define BIT_MASK_ARFR3_V1 0xffffffffffffffffL
+#define BIT_ARFR3_V1(x) (((x) & BIT_MASK_ARFR3_V1) << BIT_SHIFT_ARFR3_V1)
+#define BITS_ARFR3_V1 (BIT_MASK_ARFR3_V1 << BIT_SHIFT_ARFR3_V1)
+#define BIT_CLEAR_ARFR3_V1(x) ((x) & (~BITS_ARFR3_V1))
+#define BIT_GET_ARFR3_V1(x) (((x) >> BIT_SHIFT_ARFR3_V1) & BIT_MASK_ARFR3_V1)
+#define BIT_SET_ARFR3_V1(x, v) (BIT_CLEAR_ARFR3_V1(x) | BIT_ARFR3_V1(v))
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_ARFR3				(Offset 0x0494) */
+
+#define BIT_SHIFT_ARFRL3 0
+#define BIT_MASK_ARFRL3 0xffffffffL
+#define BIT_ARFRL3(x) (((x) & BIT_MASK_ARFRL3) << BIT_SHIFT_ARFRL3)
+#define BITS_ARFRL3 (BIT_MASK_ARFRL3 << BIT_SHIFT_ARFRL3)
+#define BIT_CLEAR_ARFRL3(x) ((x) & (~BITS_ARFRL3))
+#define BIT_GET_ARFRL3(x) (((x) >> BIT_SHIFT_ARFRL3) & BIT_MASK_ARFRL3)
+#define BIT_SET_ARFRL3(x, v) (BIT_CLEAR_ARFRL3(x) | BIT_ARFRL3(v))
+
+/* 2 REG_ARFRH3_V1				(Offset 0x0498) */
+
+#define BIT_SHIFT_ARFRH3 0
+#define BIT_MASK_ARFRH3 0xffffffffL
+#define BIT_ARFRH3(x) (((x) & BIT_MASK_ARFRH3) << BIT_SHIFT_ARFRH3)
+#define BITS_ARFRH3 (BIT_MASK_ARFRH3 << BIT_SHIFT_ARFRH3)
+#define BIT_CLEAR_ARFRH3(x) ((x) & (~BITS_ARFRH3))
+#define BIT_GET_ARFRH3(x) (((x) >> BIT_SHIFT_ARFRH3) & BIT_MASK_ARFRH3)
+#define BIT_SET_ARFRH3(x, v) (BIT_CLEAR_ARFRH3(x) | BIT_ARFRH3(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT || \
+     HALMAC_8881A_SUPPORT)
+
+/* 2 REG_ARFR4				(Offset 0x049C) */
+
+#define BIT_SHIFT_ARFR4 0
+#define BIT_MASK_ARFR4 0xffffffffffffffffL
+#define BIT_ARFR4(x) (((x) & BIT_MASK_ARFR4) << BIT_SHIFT_ARFR4)
+#define BITS_ARFR4 (BIT_MASK_ARFR4 << BIT_SHIFT_ARFR4)
+#define BIT_CLEAR_ARFR4(x) ((x) & (~BITS_ARFR4))
+#define BIT_GET_ARFR4(x) (((x) >> BIT_SHIFT_ARFR4) & BIT_MASK_ARFR4)
+#define BIT_SET_ARFR4(x, v) (BIT_CLEAR_ARFR4(x) | BIT_ARFR4(v))
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_ARFR4				(Offset 0x049C) */
+
+#define BIT_SHIFT_ARFRL4 0
+#define BIT_MASK_ARFRL4 0xffffffffL
+#define BIT_ARFRL4(x) (((x) & BIT_MASK_ARFRL4) << BIT_SHIFT_ARFRL4)
+#define BITS_ARFRL4 (BIT_MASK_ARFRL4 << BIT_SHIFT_ARFRL4)
+#define BIT_CLEAR_ARFRL4(x) ((x) & (~BITS_ARFRL4))
+#define BIT_GET_ARFRL4(x) (((x) >> BIT_SHIFT_ARFRL4) & BIT_MASK_ARFRL4)
+#define BIT_SET_ARFRL4(x, v) (BIT_CLEAR_ARFRL4(x) | BIT_ARFRL4(v))
+
+/* 2 REG_ARFRH4				(Offset 0x04A0) */
+
+#define BIT_SHIFT_ARFRH4 0
+#define BIT_MASK_ARFRH4 0xffffffffL
+#define BIT_ARFRH4(x) (((x) & BIT_MASK_ARFRH4) << BIT_SHIFT_ARFRH4)
+#define BITS_ARFRH4 (BIT_MASK_ARFRH4 << BIT_SHIFT_ARFRH4)
+#define BIT_CLEAR_ARFRH4(x) ((x) & (~BITS_ARFRH4))
+#define BIT_GET_ARFRH4(x) (((x) >> BIT_SHIFT_ARFRH4) & BIT_MASK_ARFRH4)
+#define BIT_SET_ARFRH4(x, v) (BIT_CLEAR_ARFRH4(x) | BIT_ARFRH4(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT || \
+     HALMAC_8881A_SUPPORT)
+
+/* 2 REG_ARFR5				(Offset 0x04A4) */
+
+#define BIT_SHIFT_ARFR5 0
+#define BIT_MASK_ARFR5 0xffffffffffffffffL
+#define BIT_ARFR5(x) (((x) & BIT_MASK_ARFR5) << BIT_SHIFT_ARFR5)
+#define BITS_ARFR5 (BIT_MASK_ARFR5 << BIT_SHIFT_ARFR5)
+#define BIT_CLEAR_ARFR5(x) ((x) & (~BITS_ARFR5))
+#define BIT_GET_ARFR5(x) (((x) >> BIT_SHIFT_ARFR5) & BIT_MASK_ARFR5)
+#define BIT_SET_ARFR5(x, v) (BIT_CLEAR_ARFR5(x) | BIT_ARFR5(v))
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_ARFR5				(Offset 0x04A4) */
+
+#define BIT_SHIFT_ARFRL5 0
+#define BIT_MASK_ARFRL5 0xffffffffL
+#define BIT_ARFRL5(x) (((x) & BIT_MASK_ARFRL5) << BIT_SHIFT_ARFRL5)
+#define BITS_ARFRL5 (BIT_MASK_ARFRL5 << BIT_SHIFT_ARFRL5)
+#define BIT_CLEAR_ARFRL5(x) ((x) & (~BITS_ARFRL5))
+#define BIT_GET_ARFRL5(x) (((x) >> BIT_SHIFT_ARFRL5) & BIT_MASK_ARFRL5)
+#define BIT_SET_ARFRL5(x, v) (BIT_CLEAR_ARFRL5(x) | BIT_ARFRL5(v))
+
+/* 2 REG_ARFRH5				(Offset 0x04A8) */
+
+#define BIT_SHIFT_ARFRH5 0
+#define BIT_MASK_ARFRH5 0xffffffffL
+#define BIT_ARFRH5(x) (((x) & BIT_MASK_ARFRH5) << BIT_SHIFT_ARFRH5)
+#define BITS_ARFRH5 (BIT_MASK_ARFRH5 << BIT_SHIFT_ARFRH5)
+#define BIT_CLEAR_ARFRH5(x) ((x) & (~BITS_ARFRH5))
+#define BIT_GET_ARFRH5(x) (((x) >> BIT_SHIFT_ARFRH5) & BIT_MASK_ARFRH5)
+#define BIT_SET_ARFRH5(x, v) (BIT_CLEAR_ARFRH5(x) | BIT_ARFRH5(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_TXRPT_START_OFFSET			(Offset 0x04AC) */
+
+#define BIT_RPTFIFO_RPTNUM_OPT BIT(31)
+
+#define BIT_SHIFT_MISSED_RPT_NUM 28
+#define BIT_MASK_MISSED_RPT_NUM 0x7
+#define BIT_MISSED_RPT_NUM(x)                                                  \
+	(((x) & BIT_MASK_MISSED_RPT_NUM) << BIT_SHIFT_MISSED_RPT_NUM)
+#define BITS_MISSED_RPT_NUM                                                    \
+	(BIT_MASK_MISSED_RPT_NUM << BIT_SHIFT_MISSED_RPT_NUM)
+#define BIT_CLEAR_MISSED_RPT_NUM(x) ((x) & (~BITS_MISSED_RPT_NUM))
+#define BIT_GET_MISSED_RPT_NUM(x)                                              \
+	(((x) >> BIT_SHIFT_MISSED_RPT_NUM) & BIT_MASK_MISSED_RPT_NUM)
+#define BIT_SET_MISSED_RPT_NUM(x, v)                                           \
+	(BIT_CLEAR_MISSED_RPT_NUM(x) | BIT_MISSED_RPT_NUM(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_TXRPT_START_OFFSET			(Offset 0x04AC) */
+
+#define BIT_SHCUT_PARSE_DASA BIT(25)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_TXRPT_START_OFFSET			(Offset 0x04AC) */
+
+#define BIT_SHIFT_INDEX_15 24
+#define BIT_MASK_INDEX_15 0xff
+#define BIT_INDEX_15(x) (((x) & BIT_MASK_INDEX_15) << BIT_SHIFT_INDEX_15)
+#define BITS_INDEX_15 (BIT_MASK_INDEX_15 << BIT_SHIFT_INDEX_15)
+#define BIT_CLEAR_INDEX_15(x) ((x) & (~BITS_INDEX_15))
+#define BIT_GET_INDEX_15(x) (((x) >> BIT_SHIFT_INDEX_15) & BIT_MASK_INDEX_15)
+#define BIT_SET_INDEX_15(x, v) (BIT_CLEAR_INDEX_15(x) | BIT_INDEX_15(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_TXRPT_START_OFFSET			(Offset 0x04AC) */
+
+#define BIT_SHIFT_LOC_AMPDU_BURST_CTRL 24
+#define BIT_MASK_LOC_AMPDU_BURST_CTRL 0xff
+#define BIT_LOC_AMPDU_BURST_CTRL(x)                                            \
+	(((x) & BIT_MASK_LOC_AMPDU_BURST_CTRL)                                 \
+	 << BIT_SHIFT_LOC_AMPDU_BURST_CTRL)
+#define BITS_LOC_AMPDU_BURST_CTRL                                              \
+	(BIT_MASK_LOC_AMPDU_BURST_CTRL << BIT_SHIFT_LOC_AMPDU_BURST_CTRL)
+#define BIT_CLEAR_LOC_AMPDU_BURST_CTRL(x) ((x) & (~BITS_LOC_AMPDU_BURST_CTRL))
+#define BIT_GET_LOC_AMPDU_BURST_CTRL(x)                                        \
+	(((x) >> BIT_SHIFT_LOC_AMPDU_BURST_CTRL) &                             \
+	 BIT_MASK_LOC_AMPDU_BURST_CTRL)
+#define BIT_SET_LOC_AMPDU_BURST_CTRL(x, v)                                     \
+	(BIT_CLEAR_LOC_AMPDU_BURST_CTRL(x) | BIT_LOC_AMPDU_BURST_CTRL(v))
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_TXRPT_START_OFFSET			(Offset 0x04AC) */
+
+#define BIT_SHIFT_LOC_SWPS_RPT_CTRL 24
+#define BIT_MASK_LOC_SWPS_RPT_CTRL 0xff
+#define BIT_LOC_SWPS_RPT_CTRL(x)                                               \
+	(((x) & BIT_MASK_LOC_SWPS_RPT_CTRL) << BIT_SHIFT_LOC_SWPS_RPT_CTRL)
+#define BITS_LOC_SWPS_RPT_CTRL                                                 \
+	(BIT_MASK_LOC_SWPS_RPT_CTRL << BIT_SHIFT_LOC_SWPS_RPT_CTRL)
+#define BIT_CLEAR_LOC_SWPS_RPT_CTRL(x) ((x) & (~BITS_LOC_SWPS_RPT_CTRL))
+#define BIT_GET_LOC_SWPS_RPT_CTRL(x)                                           \
+	(((x) >> BIT_SHIFT_LOC_SWPS_RPT_CTRL) & BIT_MASK_LOC_SWPS_RPT_CTRL)
+#define BIT_SET_LOC_SWPS_RPT_CTRL(x, v)                                        \
+	(BIT_CLEAR_LOC_SWPS_RPT_CTRL(x) | BIT_LOC_SWPS_RPT_CTRL(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_TXRPT_START_OFFSET			(Offset 0x04AC) */
+
+#define BIT_SHCUT_BYPASS BIT(24)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_TXRPT_START_OFFSET			(Offset 0x04AC) */
+
+#define BIT_SHIFT_MACID_MURATE_OFFSET 24
+#define BIT_MASK_MACID_MURATE_OFFSET 0xff
+#define BIT_MACID_MURATE_OFFSET(x)                                             \
+	(((x) & BIT_MASK_MACID_MURATE_OFFSET) << BIT_SHIFT_MACID_MURATE_OFFSET)
+#define BITS_MACID_MURATE_OFFSET                                               \
+	(BIT_MASK_MACID_MURATE_OFFSET << BIT_SHIFT_MACID_MURATE_OFFSET)
+#define BIT_CLEAR_MACID_MURATE_OFFSET(x) ((x) & (~BITS_MACID_MURATE_OFFSET))
+#define BIT_GET_MACID_MURATE_OFFSET(x)                                         \
+	(((x) >> BIT_SHIFT_MACID_MURATE_OFFSET) & BIT_MASK_MACID_MURATE_OFFSET)
+#define BIT_SET_MACID_MURATE_OFFSET(x, v)                                      \
+	(BIT_CLEAR_MACID_MURATE_OFFSET(x) | BIT_MACID_MURATE_OFFSET(v))
+
+#endif
+
+#if (HALMAC_8821C_SUPPORT)
+
+/* 2 REG_TXRPT_START_OFFSET			(Offset 0x04AC) */
+
+#define BIT_SHIFT_R_MUTAB_TXRPT_OFFSET 24
+#define BIT_MASK_R_MUTAB_TXRPT_OFFSET 0xff
+#define BIT_R_MUTAB_TXRPT_OFFSET(x)                                            \
+	(((x) & BIT_MASK_R_MUTAB_TXRPT_OFFSET)                                 \
+	 << BIT_SHIFT_R_MUTAB_TXRPT_OFFSET)
+#define BITS_R_MUTAB_TXRPT_OFFSET                                              \
+	(BIT_MASK_R_MUTAB_TXRPT_OFFSET << BIT_SHIFT_R_MUTAB_TXRPT_OFFSET)
+#define BIT_CLEAR_R_MUTAB_TXRPT_OFFSET(x) ((x) & (~BITS_R_MUTAB_TXRPT_OFFSET))
+#define BIT_GET_R_MUTAB_TXRPT_OFFSET(x)                                        \
+	(((x) >> BIT_SHIFT_R_MUTAB_TXRPT_OFFSET) &                             \
+	 BIT_MASK_R_MUTAB_TXRPT_OFFSET)
+#define BIT_SET_R_MUTAB_TXRPT_OFFSET(x, v)                                     \
+	(BIT_CLEAR_R_MUTAB_TXRPT_OFFSET(x) | BIT_R_MUTAB_TXRPT_OFFSET(v))
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_TXRPT_START_OFFSET			(Offset 0x04AC) */
+
+#define BIT_SHIFT_TXRPT_MISS_COUNT 17
+#define BIT_MASK_TXRPT_MISS_COUNT 0x7
+#define BIT_TXRPT_MISS_COUNT(x)                                                \
+	(((x) & BIT_MASK_TXRPT_MISS_COUNT) << BIT_SHIFT_TXRPT_MISS_COUNT)
+#define BITS_TXRPT_MISS_COUNT                                                  \
+	(BIT_MASK_TXRPT_MISS_COUNT << BIT_SHIFT_TXRPT_MISS_COUNT)
+#define BIT_CLEAR_TXRPT_MISS_COUNT(x) ((x) & (~BITS_TXRPT_MISS_COUNT))
+#define BIT_GET_TXRPT_MISS_COUNT(x)                                            \
+	(((x) >> BIT_SHIFT_TXRPT_MISS_COUNT) & BIT_MASK_TXRPT_MISS_COUNT)
+#define BIT_SET_TXRPT_MISS_COUNT(x, v)                                         \
+	(BIT_CLEAR_TXRPT_MISS_COUNT(x) | BIT_TXRPT_MISS_COUNT(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_TXRPT_START_OFFSET			(Offset 0x04AC) */
+
+#define BIT_SHIFT_LOC_BCN_RPT 16
+#define BIT_MASK_LOC_BCN_RPT 0xff
+#define BIT_LOC_BCN_RPT(x)                                                     \
+	(((x) & BIT_MASK_LOC_BCN_RPT) << BIT_SHIFT_LOC_BCN_RPT)
+#define BITS_LOC_BCN_RPT (BIT_MASK_LOC_BCN_RPT << BIT_SHIFT_LOC_BCN_RPT)
+#define BIT_CLEAR_LOC_BCN_RPT(x) ((x) & (~BITS_LOC_BCN_RPT))
+#define BIT_GET_LOC_BCN_RPT(x)                                                 \
+	(((x) >> BIT_SHIFT_LOC_BCN_RPT) & BIT_MASK_LOC_BCN_RPT)
+#define BIT_SET_LOC_BCN_RPT(x, v)                                              \
+	(BIT_CLEAR_LOC_BCN_RPT(x) | BIT_LOC_BCN_RPT(v))
+
+#define BIT_SHIFT_INDEX_14 16
+#define BIT_MASK_INDEX_14 0xff
+#define BIT_INDEX_14(x) (((x) & BIT_MASK_INDEX_14) << BIT_SHIFT_INDEX_14)
+#define BITS_INDEX_14 (BIT_MASK_INDEX_14 << BIT_SHIFT_INDEX_14)
+#define BIT_CLEAR_INDEX_14(x) ((x) & (~BITS_INDEX_14))
+#define BIT_GET_INDEX_14(x) (((x) >> BIT_SHIFT_INDEX_14) & BIT_MASK_INDEX_14)
+#define BIT_SET_INDEX_14(x, v) (BIT_CLEAR_INDEX_14(x) | BIT_INDEX_14(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT)
+
+/* 2 REG_TXRPT_START_OFFSET			(Offset 0x04AC) */
+
+#define BIT__R_RPTFIFO_1K BIT(16)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_TXRPT_START_OFFSET			(Offset 0x04AC) */
+
+#define BIT_RPTFIFO_SIZE_OPT BIT(16)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_TXRPT_START_OFFSET			(Offset 0x04AC) */
+
+#define BIT_SHIFT_MACID_SHCUT_OFFSET 16
+#define BIT_MASK_MACID_SHCUT_OFFSET 0xff
+#define BIT_MACID_SHCUT_OFFSET(x)                                              \
+	(((x) & BIT_MASK_MACID_SHCUT_OFFSET) << BIT_SHIFT_MACID_SHCUT_OFFSET)
+#define BITS_MACID_SHCUT_OFFSET                                                \
+	(BIT_MASK_MACID_SHCUT_OFFSET << BIT_SHIFT_MACID_SHCUT_OFFSET)
+#define BIT_CLEAR_MACID_SHCUT_OFFSET(x) ((x) & (~BITS_MACID_SHCUT_OFFSET))
+#define BIT_GET_MACID_SHCUT_OFFSET(x)                                          \
+	(((x) >> BIT_SHIFT_MACID_SHCUT_OFFSET) & BIT_MASK_MACID_SHCUT_OFFSET)
+#define BIT_SET_MACID_SHCUT_OFFSET(x, v)                                       \
+	(BIT_CLEAR_MACID_SHCUT_OFFSET(x) | BIT_MACID_SHCUT_OFFSET(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_TXRPT_START_OFFSET			(Offset 0x04AC) */
+
+#define BIT_SHIFT_MACID_CTRL_OFFSET_V1 16
+#define BIT_MASK_MACID_CTRL_OFFSET_V1 0x1ff
+#define BIT_MACID_CTRL_OFFSET_V1(x)                                            \
+	(((x) & BIT_MASK_MACID_CTRL_OFFSET_V1)                                 \
+	 << BIT_SHIFT_MACID_CTRL_OFFSET_V1)
+#define BITS_MACID_CTRL_OFFSET_V1                                              \
+	(BIT_MASK_MACID_CTRL_OFFSET_V1 << BIT_SHIFT_MACID_CTRL_OFFSET_V1)
+#define BIT_CLEAR_MACID_CTRL_OFFSET_V1(x) ((x) & (~BITS_MACID_CTRL_OFFSET_V1))
+#define BIT_GET_MACID_CTRL_OFFSET_V1(x)                                        \
+	(((x) >> BIT_SHIFT_MACID_CTRL_OFFSET_V1) &                             \
+	 BIT_MASK_MACID_CTRL_OFFSET_V1)
+#define BIT_SET_MACID_CTRL_OFFSET_V1(x, v)                                     \
+	(BIT_CLEAR_MACID_CTRL_OFFSET_V1(x) | BIT_MACID_CTRL_OFFSET_V1(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_TXRPT_START_OFFSET			(Offset 0x04AC) */
+
+#define BIT_SHIFT_LOC_TXRPT 8
+#define BIT_MASK_LOC_TXRPT 0xff
+#define BIT_LOC_TXRPT(x) (((x) & BIT_MASK_LOC_TXRPT) << BIT_SHIFT_LOC_TXRPT)
+#define BITS_LOC_TXRPT (BIT_MASK_LOC_TXRPT << BIT_SHIFT_LOC_TXRPT)
+#define BIT_CLEAR_LOC_TXRPT(x) ((x) & (~BITS_LOC_TXRPT))
+#define BIT_GET_LOC_TXRPT(x) (((x) >> BIT_SHIFT_LOC_TXRPT) & BIT_MASK_LOC_TXRPT)
+#define BIT_SET_LOC_TXRPT(x, v) (BIT_CLEAR_LOC_TXRPT(x) | BIT_LOC_TXRPT(v))
+
+#define BIT_SHIFT_INDEX_13 8
+#define BIT_MASK_INDEX_13 0xff
+#define BIT_INDEX_13(x) (((x) & BIT_MASK_INDEX_13) << BIT_SHIFT_INDEX_13)
+#define BITS_INDEX_13 (BIT_MASK_INDEX_13 << BIT_SHIFT_INDEX_13)
+#define BIT_CLEAR_INDEX_13(x) ((x) & (~BITS_INDEX_13))
+#define BIT_GET_INDEX_13(x) (((x) >> BIT_SHIFT_INDEX_13) & BIT_MASK_INDEX_13)
+#define BIT_SET_INDEX_13(x, v) (BIT_CLEAR_INDEX_13(x) | BIT_INDEX_13(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_TXRPT_START_OFFSET			(Offset 0x04AC) */
+
+#define BIT_SHIFT_MACID_CTRL_OFFSET 8
+#define BIT_MASK_MACID_CTRL_OFFSET 0xff
+#define BIT_MACID_CTRL_OFFSET(x)                                               \
+	(((x) & BIT_MASK_MACID_CTRL_OFFSET) << BIT_SHIFT_MACID_CTRL_OFFSET)
+#define BITS_MACID_CTRL_OFFSET                                                 \
+	(BIT_MASK_MACID_CTRL_OFFSET << BIT_SHIFT_MACID_CTRL_OFFSET)
+#define BIT_CLEAR_MACID_CTRL_OFFSET(x) ((x) & (~BITS_MACID_CTRL_OFFSET))
+#define BIT_GET_MACID_CTRL_OFFSET(x)                                           \
+	(((x) >> BIT_SHIFT_MACID_CTRL_OFFSET) & BIT_MASK_MACID_CTRL_OFFSET)
+#define BIT_SET_MACID_CTRL_OFFSET(x, v)                                        \
+	(BIT_CLEAR_MACID_CTRL_OFFSET(x) | BIT_MACID_CTRL_OFFSET(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_TXRPT_START_OFFSET			(Offset 0x04AC) */
+
+#define BIT_SHIFT_LOC_SRFF 0
+#define BIT_MASK_LOC_SRFF 0xff
+#define BIT_LOC_SRFF(x) (((x) & BIT_MASK_LOC_SRFF) << BIT_SHIFT_LOC_SRFF)
+#define BITS_LOC_SRFF (BIT_MASK_LOC_SRFF << BIT_SHIFT_LOC_SRFF)
+#define BIT_CLEAR_LOC_SRFF(x) ((x) & (~BITS_LOC_SRFF))
+#define BIT_GET_LOC_SRFF(x) (((x) >> BIT_SHIFT_LOC_SRFF) & BIT_MASK_LOC_SRFF)
+#define BIT_SET_LOC_SRFF(x, v) (BIT_CLEAR_LOC_SRFF(x) | BIT_LOC_SRFF(v))
+
+#define BIT_SHIFT_INDEX_12 0
+#define BIT_MASK_INDEX_12 0xff
+#define BIT_INDEX_12(x) (((x) & BIT_MASK_INDEX_12) << BIT_SHIFT_INDEX_12)
+#define BITS_INDEX_12 (BIT_MASK_INDEX_12 << BIT_SHIFT_INDEX_12)
+#define BIT_CLEAR_INDEX_12(x) ((x) & (~BITS_INDEX_12))
+#define BIT_GET_INDEX_12(x) (((x) >> BIT_SHIFT_INDEX_12) & BIT_MASK_INDEX_12)
+#define BIT_SET_INDEX_12(x, v) (BIT_CLEAR_INDEX_12(x) | BIT_INDEX_12(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_TXRPT_START_OFFSET			(Offset 0x04AC) */
+
+#define BIT_SHIFT_RA_TRY_RATE_AGG_LMT 0
+#define BIT_MASK_RA_TRY_RATE_AGG_LMT 0x1f
+#define BIT_RA_TRY_RATE_AGG_LMT(x)                                             \
+	(((x) & BIT_MASK_RA_TRY_RATE_AGG_LMT) << BIT_SHIFT_RA_TRY_RATE_AGG_LMT)
+#define BITS_RA_TRY_RATE_AGG_LMT                                               \
+	(BIT_MASK_RA_TRY_RATE_AGG_LMT << BIT_SHIFT_RA_TRY_RATE_AGG_LMT)
+#define BIT_CLEAR_RA_TRY_RATE_AGG_LMT(x) ((x) & (~BITS_RA_TRY_RATE_AGG_LMT))
+#define BIT_GET_RA_TRY_RATE_AGG_LMT(x)                                         \
+	(((x) >> BIT_SHIFT_RA_TRY_RATE_AGG_LMT) & BIT_MASK_RA_TRY_RATE_AGG_LMT)
+#define BIT_SET_RA_TRY_RATE_AGG_LMT(x, v)                                      \
+	(BIT_CLEAR_RA_TRY_RATE_AGG_LMT(x) | BIT_RA_TRY_RATE_AGG_LMT(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_TXRPT_START_OFFSET			(Offset 0x04AC) */
+
+#define BIT_SHIFT_AMPDU_TXRPT_OFFSET 0
+#define BIT_MASK_AMPDU_TXRPT_OFFSET 0xff
+#define BIT_AMPDU_TXRPT_OFFSET(x)                                              \
+	(((x) & BIT_MASK_AMPDU_TXRPT_OFFSET) << BIT_SHIFT_AMPDU_TXRPT_OFFSET)
+#define BITS_AMPDU_TXRPT_OFFSET                                                \
+	(BIT_MASK_AMPDU_TXRPT_OFFSET << BIT_SHIFT_AMPDU_TXRPT_OFFSET)
+#define BIT_CLEAR_AMPDU_TXRPT_OFFSET(x) ((x) & (~BITS_AMPDU_TXRPT_OFFSET))
+#define BIT_GET_AMPDU_TXRPT_OFFSET(x)                                          \
+	(((x) >> BIT_SHIFT_AMPDU_TXRPT_OFFSET) & BIT_MASK_AMPDU_TXRPT_OFFSET)
+#define BIT_SET_AMPDU_TXRPT_OFFSET(x, v)                                       \
+	(BIT_CLEAR_AMPDU_TXRPT_OFFSET(x) | BIT_AMPDU_TXRPT_OFFSET(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_TXRPT_START_OFFSET			(Offset 0x04AC) */
+
+#define BIT_SHIFT_AMPDU_TXRPT_OFFSET_V1 0
+#define BIT_MASK_AMPDU_TXRPT_OFFSET_V1 0x1ff
+#define BIT_AMPDU_TXRPT_OFFSET_V1(x)                                           \
+	(((x) & BIT_MASK_AMPDU_TXRPT_OFFSET_V1)                                \
+	 << BIT_SHIFT_AMPDU_TXRPT_OFFSET_V1)
+#define BITS_AMPDU_TXRPT_OFFSET_V1                                             \
+	(BIT_MASK_AMPDU_TXRPT_OFFSET_V1 << BIT_SHIFT_AMPDU_TXRPT_OFFSET_V1)
+#define BIT_CLEAR_AMPDU_TXRPT_OFFSET_V1(x) ((x) & (~BITS_AMPDU_TXRPT_OFFSET_V1))
+#define BIT_GET_AMPDU_TXRPT_OFFSET_V1(x)                                       \
+	(((x) >> BIT_SHIFT_AMPDU_TXRPT_OFFSET_V1) &                            \
+	 BIT_MASK_AMPDU_TXRPT_OFFSET_V1)
+#define BIT_SET_AMPDU_TXRPT_OFFSET_V1(x, v)                                    \
+	(BIT_CLEAR_AMPDU_TXRPT_OFFSET_V1(x) | BIT_AMPDU_TXRPT_OFFSET_V1(v))
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT)
+
+/* 2 REG_RRSR_CTS				(Offset 0x04B0) */
+
+#define BIT_SHIFT_RRCTSSR_RSC 21
+#define BIT_MASK_RRCTSSR_RSC 0x3
+#define BIT_RRCTSSR_RSC(x)                                                     \
+	(((x) & BIT_MASK_RRCTSSR_RSC) << BIT_SHIFT_RRCTSSR_RSC)
+#define BITS_RRCTSSR_RSC (BIT_MASK_RRCTSSR_RSC << BIT_SHIFT_RRCTSSR_RSC)
+#define BIT_CLEAR_RRCTSSR_RSC(x) ((x) & (~BITS_RRCTSSR_RSC))
+#define BIT_GET_RRCTSSR_RSC(x)                                                 \
+	(((x) >> BIT_SHIFT_RRCTSSR_RSC) & BIT_MASK_RRCTSSR_RSC)
+#define BIT_SET_RRCTSSR_RSC(x, v)                                              \
+	(BIT_CLEAR_RRCTSSR_RSC(x) | BIT_RRCTSSR_RSC(v))
+
+#define BIT_SHIFT_RRCTSSC_BITMAP 0
+#define BIT_MASK_RRCTSSC_BITMAP 0xfffff
+#define BIT_RRCTSSC_BITMAP(x)                                                  \
+	(((x) & BIT_MASK_RRCTSSC_BITMAP) << BIT_SHIFT_RRCTSSC_BITMAP)
+#define BITS_RRCTSSC_BITMAP                                                    \
+	(BIT_MASK_RRCTSSC_BITMAP << BIT_SHIFT_RRCTSSC_BITMAP)
+#define BIT_CLEAR_RRCTSSC_BITMAP(x) ((x) & (~BITS_RRCTSSC_BITMAP))
+#define BIT_GET_RRCTSSC_BITMAP(x)                                              \
+	(((x) >> BIT_SHIFT_RRCTSSC_BITMAP) & BIT_MASK_RRCTSSC_BITMAP)
+#define BIT_SET_RRCTSSC_BITMAP(x, v)                                           \
+	(BIT_CLEAR_RRCTSSC_BITMAP(x) | BIT_RRCTSSC_BITMAP(v))
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_POWER_STAGE1			(Offset 0x04B4) */
+
+#define BIT_PTA_WL_PRI_MASK_CPU_MGQ BIT(31)
+#define BIT_PTA_WL_PRI_MASK_BCNQ BIT(30)
+#define BIT_PTA_WL_PRI_MASK_HIQ BIT(29)
+#define BIT_PTA_WL_PRI_MASK_MGQ BIT(28)
+#define BIT_PTA_WL_PRI_MASK_BK BIT(27)
+#define BIT_PTA_WL_PRI_MASK_BE BIT(26)
+#define BIT_PTA_WL_PRI_MASK_VI BIT(25)
+#define BIT_PTA_WL_PRI_MASK_VO BIT(24)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_POWER_STAGE1			(Offset 0x04B4) */
+
+#define BIT_SHIFT_POWER_STAGE1 0
+#define BIT_MASK_POWER_STAGE1 0xffffff
+#define BIT_POWER_STAGE1(x)                                                    \
+	(((x) & BIT_MASK_POWER_STAGE1) << BIT_SHIFT_POWER_STAGE1)
+#define BITS_POWER_STAGE1 (BIT_MASK_POWER_STAGE1 << BIT_SHIFT_POWER_STAGE1)
+#define BIT_CLEAR_POWER_STAGE1(x) ((x) & (~BITS_POWER_STAGE1))
+#define BIT_GET_POWER_STAGE1(x)                                                \
+	(((x) >> BIT_SHIFT_POWER_STAGE1) & BIT_MASK_POWER_STAGE1)
+#define BIT_SET_POWER_STAGE1(x, v)                                             \
+	(BIT_CLEAR_POWER_STAGE1(x) | BIT_POWER_STAGE1(v))
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_POWER_STAGE2			(Offset 0x04B8) */
+
+#define BIT_SHIFT_EVTQ_TXRPT 27
+#define BIT_MASK_EVTQ_TXRPT 0x7
+#define BIT_EVTQ_TXRPT(x) (((x) & BIT_MASK_EVTQ_TXRPT) << BIT_SHIFT_EVTQ_TXRPT)
+#define BITS_EVTQ_TXRPT (BIT_MASK_EVTQ_TXRPT << BIT_SHIFT_EVTQ_TXRPT)
+#define BIT_CLEAR_EVTQ_TXRPT(x) ((x) & (~BITS_EVTQ_TXRPT))
+#define BIT_GET_EVTQ_TXRPT(x)                                                  \
+	(((x) >> BIT_SHIFT_EVTQ_TXRPT) & BIT_MASK_EVTQ_TXRPT)
+#define BIT_SET_EVTQ_TXRPT(x, v) (BIT_CLEAR_EVTQ_TXRPT(x) | BIT_EVTQ_TXRPT(v))
+
+#define BIT_PTA_WL_PRI_MASK_EVT BIT(25)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8814B_SUPPORT)
+
+/* 2 REG_POWER_STAGE2			(Offset 0x04B8) */
+
+#define BIT__CTRL_PKT_POW_ADJ BIT(24)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_POWER_STAGE2			(Offset 0x04B8) */
+
+#define BIT__R_CTRL_PKT_POW_ADJ BIT(24)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_POWER_STAGE2			(Offset 0x04B8) */
+
+#define BIT_SHIFT_POWER_STAGE2 0
+#define BIT_MASK_POWER_STAGE2 0xffffff
+#define BIT_POWER_STAGE2(x)                                                    \
+	(((x) & BIT_MASK_POWER_STAGE2) << BIT_SHIFT_POWER_STAGE2)
+#define BITS_POWER_STAGE2 (BIT_MASK_POWER_STAGE2 << BIT_SHIFT_POWER_STAGE2)
+#define BIT_CLEAR_POWER_STAGE2(x) ((x) & (~BITS_POWER_STAGE2))
+#define BIT_GET_POWER_STAGE2(x)                                                \
+	(((x) >> BIT_SHIFT_POWER_STAGE2) & BIT_MASK_POWER_STAGE2)
+#define BIT_SET_POWER_STAGE2(x, v)                                             \
+	(BIT_CLEAR_POWER_STAGE2(x) | BIT_POWER_STAGE2(v))
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_SW_AMPDU_BURST_MODE_CTRL		(Offset 0x04BC) */
+
+#define BIT_SHIFT_EVTQ_HEAD 24
+#define BIT_MASK_EVTQ_HEAD 0xff
+#define BIT_EVTQ_HEAD(x) (((x) & BIT_MASK_EVTQ_HEAD) << BIT_SHIFT_EVTQ_HEAD)
+#define BITS_EVTQ_HEAD (BIT_MASK_EVTQ_HEAD << BIT_SHIFT_EVTQ_HEAD)
+#define BIT_CLEAR_EVTQ_HEAD(x) ((x) & (~BITS_EVTQ_HEAD))
+#define BIT_GET_EVTQ_HEAD(x) (((x) >> BIT_SHIFT_EVTQ_HEAD) & BIT_MASK_EVTQ_HEAD)
+#define BIT_SET_EVTQ_HEAD(x, v) (BIT_CLEAR_EVTQ_HEAD(x) | BIT_EVTQ_HEAD(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_SW_AMPDU_BURST_MODE_CTRL		(Offset 0x04BC) */
+
+#define BIT_SHIFT_PAD_NUM_THRES 24
+#define BIT_MASK_PAD_NUM_THRES 0x3f
+#define BIT_PAD_NUM_THRES(x)                                                   \
+	(((x) & BIT_MASK_PAD_NUM_THRES) << BIT_SHIFT_PAD_NUM_THRES)
+#define BITS_PAD_NUM_THRES (BIT_MASK_PAD_NUM_THRES << BIT_SHIFT_PAD_NUM_THRES)
+#define BIT_CLEAR_PAD_NUM_THRES(x) ((x) & (~BITS_PAD_NUM_THRES))
+#define BIT_GET_PAD_NUM_THRES(x)                                               \
+	(((x) >> BIT_SHIFT_PAD_NUM_THRES) & BIT_MASK_PAD_NUM_THRES)
+#define BIT_SET_PAD_NUM_THRES(x, v)                                            \
+	(BIT_CLEAR_PAD_NUM_THRES(x) | BIT_PAD_NUM_THRES(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8881A_SUPPORT)
+
+/* 2 REG_SW_AMPDU_BURST_MODE_CTRL		(Offset 0x04BC) */
+
+#define BIT_R_DMA_THIS_QUEUE_BK BIT(23)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_SW_AMPDU_BURST_MODE_CTRL		(Offset 0x04BC) */
+
+#define BIT_DMA_THIS_QUEUE_BK BIT(23)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8881A_SUPPORT)
+
+/* 2 REG_SW_AMPDU_BURST_MODE_CTRL		(Offset 0x04BC) */
+
+#define BIT_R_DMA_THIS_QUEUE_BE BIT(22)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_SW_AMPDU_BURST_MODE_CTRL		(Offset 0x04BC) */
+
+#define BIT_DMA_THIS_QUEUE_BE BIT(22)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8881A_SUPPORT)
+
+/* 2 REG_SW_AMPDU_BURST_MODE_CTRL		(Offset 0x04BC) */
+
+#define BIT_R_DMA_THIS_QUEUE_VI BIT(21)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_SW_AMPDU_BURST_MODE_CTRL		(Offset 0x04BC) */
+
+#define BIT_DMA_THIS_QUEUE_VI BIT(21)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8881A_SUPPORT)
+
+/* 2 REG_SW_AMPDU_BURST_MODE_CTRL		(Offset 0x04BC) */
+
+#define BIT_R_DMA_THIS_QUEUE_VO BIT(20)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_SW_AMPDU_BURST_MODE_CTRL		(Offset 0x04BC) */
+
+#define BIT_DMA_THIS_QUEUE_VO BIT(20)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8881A_SUPPORT)
+
+/* 2 REG_SW_AMPDU_BURST_MODE_CTRL		(Offset 0x04BC) */
+
+#define BIT_SHIFT_R_TOTAL_LEN_TH 8
+#define BIT_MASK_R_TOTAL_LEN_TH 0xfff
+#define BIT_R_TOTAL_LEN_TH(x)                                                  \
+	(((x) & BIT_MASK_R_TOTAL_LEN_TH) << BIT_SHIFT_R_TOTAL_LEN_TH)
+#define BITS_R_TOTAL_LEN_TH                                                    \
+	(BIT_MASK_R_TOTAL_LEN_TH << BIT_SHIFT_R_TOTAL_LEN_TH)
+#define BIT_CLEAR_R_TOTAL_LEN_TH(x) ((x) & (~BITS_R_TOTAL_LEN_TH))
+#define BIT_GET_R_TOTAL_LEN_TH(x)                                              \
+	(((x) >> BIT_SHIFT_R_TOTAL_LEN_TH) & BIT_MASK_R_TOTAL_LEN_TH)
+#define BIT_SET_R_TOTAL_LEN_TH(x, v)                                           \
+	(BIT_CLEAR_R_TOTAL_LEN_TH(x) | BIT_R_TOTAL_LEN_TH(v))
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8814B_SUPPORT)
+
+/* 2 REG_SW_AMPDU_BURST_MODE_CTRL		(Offset 0x04BC) */
+
+#define BIT_SHIFT_TOTAL_LEN_TH 8
+#define BIT_MASK_TOTAL_LEN_TH 0xfff
+#define BIT_TOTAL_LEN_TH(x)                                                    \
+	(((x) & BIT_MASK_TOTAL_LEN_TH) << BIT_SHIFT_TOTAL_LEN_TH)
+#define BITS_TOTAL_LEN_TH (BIT_MASK_TOTAL_LEN_TH << BIT_SHIFT_TOTAL_LEN_TH)
+#define BIT_CLEAR_TOTAL_LEN_TH(x) ((x) & (~BITS_TOTAL_LEN_TH))
+#define BIT_GET_TOTAL_LEN_TH(x)                                                \
+	(((x) >> BIT_SHIFT_TOTAL_LEN_TH) & BIT_MASK_TOTAL_LEN_TH)
+#define BIT_SET_TOTAL_LEN_TH(x, v)                                             \
+	(BIT_CLEAR_TOTAL_LEN_TH(x) | BIT_TOTAL_LEN_TH(v))
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_SW_AMPDU_BURST_MODE_CTRL		(Offset 0x04BC) */
+
+#define BIT_WEP_PRETX_EN BIT(7)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_SW_AMPDU_BURST_MODE_CTRL		(Offset 0x04BC) */
+
+#define BIT_EN_NEW_EARLY BIT(7)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_SW_AMPDU_BURST_MODE_CTRL		(Offset 0x04BC) */
+
+#define BIT_PRE_TX_CMD BIT(6)
+
+#define BIT_SHIFT_NUM_SCL_EN 4
+#define BIT_MASK_NUM_SCL_EN 0x3
+#define BIT_NUM_SCL_EN(x) (((x) & BIT_MASK_NUM_SCL_EN) << BIT_SHIFT_NUM_SCL_EN)
+#define BITS_NUM_SCL_EN (BIT_MASK_NUM_SCL_EN << BIT_SHIFT_NUM_SCL_EN)
+#define BIT_CLEAR_NUM_SCL_EN(x) ((x) & (~BITS_NUM_SCL_EN))
+#define BIT_GET_NUM_SCL_EN(x)                                                  \
+	(((x) >> BIT_SHIFT_NUM_SCL_EN) & BIT_MASK_NUM_SCL_EN)
+#define BIT_SET_NUM_SCL_EN(x, v) (BIT_CLEAR_NUM_SCL_EN(x) | BIT_NUM_SCL_EN(v))
+
+#define BIT_BK_EN BIT(3)
+#define BIT_BE_EN BIT(2)
+#define BIT_VI_EN BIT(1)
+#define BIT_VO_EN BIT(0)
+
+/* 2 REG_PKT_LIFE_TIME			(Offset 0x04C0) */
+
+#define BIT_SHIFT_PKT_LIFTIME_BEBK 16
+#define BIT_MASK_PKT_LIFTIME_BEBK 0xffff
+#define BIT_PKT_LIFTIME_BEBK(x)                                                \
+	(((x) & BIT_MASK_PKT_LIFTIME_BEBK) << BIT_SHIFT_PKT_LIFTIME_BEBK)
+#define BITS_PKT_LIFTIME_BEBK                                                  \
+	(BIT_MASK_PKT_LIFTIME_BEBK << BIT_SHIFT_PKT_LIFTIME_BEBK)
+#define BIT_CLEAR_PKT_LIFTIME_BEBK(x) ((x) & (~BITS_PKT_LIFTIME_BEBK))
+#define BIT_GET_PKT_LIFTIME_BEBK(x)                                            \
+	(((x) >> BIT_SHIFT_PKT_LIFTIME_BEBK) & BIT_MASK_PKT_LIFTIME_BEBK)
+#define BIT_SET_PKT_LIFTIME_BEBK(x, v)                                         \
+	(BIT_CLEAR_PKT_LIFTIME_BEBK(x) | BIT_PKT_LIFTIME_BEBK(v))
+
+#define BIT_SHIFT_PKT_LIFTIME_VOVI 0
+#define BIT_MASK_PKT_LIFTIME_VOVI 0xffff
+#define BIT_PKT_LIFTIME_VOVI(x)                                                \
+	(((x) & BIT_MASK_PKT_LIFTIME_VOVI) << BIT_SHIFT_PKT_LIFTIME_VOVI)
+#define BITS_PKT_LIFTIME_VOVI                                                  \
+	(BIT_MASK_PKT_LIFTIME_VOVI << BIT_SHIFT_PKT_LIFTIME_VOVI)
+#define BIT_CLEAR_PKT_LIFTIME_VOVI(x) ((x) & (~BITS_PKT_LIFTIME_VOVI))
+#define BIT_GET_PKT_LIFTIME_VOVI(x)                                            \
+	(((x) >> BIT_SHIFT_PKT_LIFTIME_VOVI) & BIT_MASK_PKT_LIFTIME_VOVI)
+#define BIT_SET_PKT_LIFTIME_VOVI(x, v)                                         \
+	(BIT_CLEAR_PKT_LIFTIME_VOVI(x) | BIT_PKT_LIFTIME_VOVI(v))
+
+/* 2 REG_STBC_SETTING			(Offset 0x04C4) */
+
+#define BIT_SHIFT_CDEND_TXTIME_L 4
+#define BIT_MASK_CDEND_TXTIME_L 0xf
+#define BIT_CDEND_TXTIME_L(x)                                                  \
+	(((x) & BIT_MASK_CDEND_TXTIME_L) << BIT_SHIFT_CDEND_TXTIME_L)
+#define BITS_CDEND_TXTIME_L                                                    \
+	(BIT_MASK_CDEND_TXTIME_L << BIT_SHIFT_CDEND_TXTIME_L)
+#define BIT_CLEAR_CDEND_TXTIME_L(x) ((x) & (~BITS_CDEND_TXTIME_L))
+#define BIT_GET_CDEND_TXTIME_L(x)                                              \
+	(((x) >> BIT_SHIFT_CDEND_TXTIME_L) & BIT_MASK_CDEND_TXTIME_L)
+#define BIT_SET_CDEND_TXTIME_L(x, v)                                           \
+	(BIT_CLEAR_CDEND_TXTIME_L(x) | BIT_CDEND_TXTIME_L(v))
+
+#define BIT_SHIFT_NESS 2
+#define BIT_MASK_NESS 0x3
+#define BIT_NESS(x) (((x) & BIT_MASK_NESS) << BIT_SHIFT_NESS)
+#define BITS_NESS (BIT_MASK_NESS << BIT_SHIFT_NESS)
+#define BIT_CLEAR_NESS(x) ((x) & (~BITS_NESS))
+#define BIT_GET_NESS(x) (((x) >> BIT_SHIFT_NESS) & BIT_MASK_NESS)
+#define BIT_SET_NESS(x, v) (BIT_CLEAR_NESS(x) | BIT_NESS(v))
+
+#define BIT_SHIFT_STBC_CFEND 0
+#define BIT_MASK_STBC_CFEND 0x3
+#define BIT_STBC_CFEND(x) (((x) & BIT_MASK_STBC_CFEND) << BIT_SHIFT_STBC_CFEND)
+#define BITS_STBC_CFEND (BIT_MASK_STBC_CFEND << BIT_SHIFT_STBC_CFEND)
+#define BIT_CLEAR_STBC_CFEND(x) ((x) & (~BITS_STBC_CFEND))
+#define BIT_GET_STBC_CFEND(x)                                                  \
+	(((x) >> BIT_SHIFT_STBC_CFEND) & BIT_MASK_STBC_CFEND)
+#define BIT_SET_STBC_CFEND(x, v) (BIT_CLEAR_STBC_CFEND(x) | BIT_STBC_CFEND(v))
+
+/* 2 REG_STBC_SETTING2			(Offset 0x04C5) */
+
+#define BIT_SHIFT_CDEND_TXTIME_H 0
+#define BIT_MASK_CDEND_TXTIME_H 0x1f
+#define BIT_CDEND_TXTIME_H(x)                                                  \
+	(((x) & BIT_MASK_CDEND_TXTIME_H) << BIT_SHIFT_CDEND_TXTIME_H)
+#define BITS_CDEND_TXTIME_H                                                    \
+	(BIT_MASK_CDEND_TXTIME_H << BIT_SHIFT_CDEND_TXTIME_H)
+#define BIT_CLEAR_CDEND_TXTIME_H(x) ((x) & (~BITS_CDEND_TXTIME_H))
+#define BIT_GET_CDEND_TXTIME_H(x)                                              \
+	(((x) >> BIT_SHIFT_CDEND_TXTIME_H) & BIT_MASK_CDEND_TXTIME_H)
+#define BIT_SET_CDEND_TXTIME_H(x, v)                                           \
+	(BIT_CLEAR_CDEND_TXTIME_H(x) | BIT_CDEND_TXTIME_H(v))
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_QUEUE_CTRL				(Offset 0x04C6) */
+
+#define BIT_FORCE_RND_PRI BIT(6)
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+/* 2 REG_QUEUE_CTRL				(Offset 0x04C6) */
+
+#define BIT_R_FORCE_RND_PRI BIT(6)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_QUEUE_CTRL				(Offset 0x04C6) */
+
+#define BIT_PTA_EDCCA_EN BIT(5)
+#define BIT_PTA_WL_TX_EN BIT(4)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8881A_SUPPORT)
+
+/* 2 REG_QUEUE_CTRL				(Offset 0x04C6) */
+
+#define BIT_R_USE_DATA_BW BIT(3)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8814B_SUPPORT)
+
+/* 2 REG_QUEUE_CTRL				(Offset 0x04C6) */
+
+#define BIT_USE_DATA_BW BIT(3)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_QUEUE_CTRL				(Offset 0x04C6) */
+
+#define BIT_TRI_PKT_INT_MODE1 BIT(2)
+#define BIT_TRI_PKT_INT_MODE0 BIT(1)
+#define BIT_ACQ_MODE_SEL BIT(0)
+
+/* 2 REG_SINGLE_AMPDU_CTRL			(Offset 0x04C7) */
+
+#define BIT_EN_SINGLE_APMDU BIT(7)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_SINGLE_AMPDU_CTRL			(Offset 0x04C7) */
+
+#define BIT_SHIFT_SNDTX_MAXTIME 0
+#define BIT_MASK_SNDTX_MAXTIME 0x7f
+#define BIT_SNDTX_MAXTIME(x)                                                   \
+	(((x) & BIT_MASK_SNDTX_MAXTIME) << BIT_SHIFT_SNDTX_MAXTIME)
+#define BITS_SNDTX_MAXTIME (BIT_MASK_SNDTX_MAXTIME << BIT_SHIFT_SNDTX_MAXTIME)
+#define BIT_CLEAR_SNDTX_MAXTIME(x) ((x) & (~BITS_SNDTX_MAXTIME))
+#define BIT_GET_SNDTX_MAXTIME(x)                                               \
+	(((x) >> BIT_SHIFT_SNDTX_MAXTIME) & BIT_MASK_SNDTX_MAXTIME)
+#define BIT_SET_SNDTX_MAXTIME(x, v)                                            \
+	(BIT_CLEAR_SNDTX_MAXTIME(x) | BIT_SNDTX_MAXTIME(v))
+
+/* 2 REG_PROT_MODE_CTRL			(Offset 0x04C8) */
+
+#define BIT_SND_SIFS_TXDATA BIT(31)
+#define BIT_TX_SND_MATCH_MACID BIT(30)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_PROT_MODE_CTRL			(Offset 0x04C8) */
+
+#define BIT_SHIFT_RTS_MAX_AGG_NUM 24
+#define BIT_MASK_RTS_MAX_AGG_NUM 0x3f
+#define BIT_RTS_MAX_AGG_NUM(x)                                                 \
+	(((x) & BIT_MASK_RTS_MAX_AGG_NUM) << BIT_SHIFT_RTS_MAX_AGG_NUM)
+#define BITS_RTS_MAX_AGG_NUM                                                   \
+	(BIT_MASK_RTS_MAX_AGG_NUM << BIT_SHIFT_RTS_MAX_AGG_NUM)
+#define BIT_CLEAR_RTS_MAX_AGG_NUM(x) ((x) & (~BITS_RTS_MAX_AGG_NUM))
+#define BIT_GET_RTS_MAX_AGG_NUM(x)                                             \
+	(((x) >> BIT_SHIFT_RTS_MAX_AGG_NUM) & BIT_MASK_RTS_MAX_AGG_NUM)
+#define BIT_SET_RTS_MAX_AGG_NUM(x, v)                                          \
+	(BIT_CLEAR_RTS_MAX_AGG_NUM(x) | BIT_RTS_MAX_AGG_NUM(v))
+
+#define BIT_SHIFT_MAX_AGG_NUM 16
+#define BIT_MASK_MAX_AGG_NUM 0x3f
+#define BIT_MAX_AGG_NUM(x)                                                     \
+	(((x) & BIT_MASK_MAX_AGG_NUM) << BIT_SHIFT_MAX_AGG_NUM)
+#define BITS_MAX_AGG_NUM (BIT_MASK_MAX_AGG_NUM << BIT_SHIFT_MAX_AGG_NUM)
+#define BIT_CLEAR_MAX_AGG_NUM(x) ((x) & (~BITS_MAX_AGG_NUM))
+#define BIT_GET_MAX_AGG_NUM(x)                                                 \
+	(((x) >> BIT_SHIFT_MAX_AGG_NUM) & BIT_MASK_MAX_AGG_NUM)
+#define BIT_SET_MAX_AGG_NUM(x, v)                                              \
+	(BIT_CLEAR_MAX_AGG_NUM(x) | BIT_MAX_AGG_NUM(v))
+
+#define BIT_SHIFT_RTS_TXTIME_TH 8
+#define BIT_MASK_RTS_TXTIME_TH 0xff
+#define BIT_RTS_TXTIME_TH(x)                                                   \
+	(((x) & BIT_MASK_RTS_TXTIME_TH) << BIT_SHIFT_RTS_TXTIME_TH)
+#define BITS_RTS_TXTIME_TH (BIT_MASK_RTS_TXTIME_TH << BIT_SHIFT_RTS_TXTIME_TH)
+#define BIT_CLEAR_RTS_TXTIME_TH(x) ((x) & (~BITS_RTS_TXTIME_TH))
+#define BIT_GET_RTS_TXTIME_TH(x)                                               \
+	(((x) >> BIT_SHIFT_RTS_TXTIME_TH) & BIT_MASK_RTS_TXTIME_TH)
+#define BIT_SET_RTS_TXTIME_TH(x, v)                                            \
+	(BIT_CLEAR_RTS_TXTIME_TH(x) | BIT_RTS_TXTIME_TH(v))
+
+#define BIT_SHIFT_RTS_LEN_TH 0
+#define BIT_MASK_RTS_LEN_TH 0xff
+#define BIT_RTS_LEN_TH(x) (((x) & BIT_MASK_RTS_LEN_TH) << BIT_SHIFT_RTS_LEN_TH)
+#define BITS_RTS_LEN_TH (BIT_MASK_RTS_LEN_TH << BIT_SHIFT_RTS_LEN_TH)
+#define BIT_CLEAR_RTS_LEN_TH(x) ((x) & (~BITS_RTS_LEN_TH))
+#define BIT_GET_RTS_LEN_TH(x)                                                  \
+	(((x) >> BIT_SHIFT_RTS_LEN_TH) & BIT_MASK_RTS_LEN_TH)
+#define BIT_SET_RTS_LEN_TH(x, v) (BIT_CLEAR_RTS_LEN_TH(x) | BIT_RTS_LEN_TH(v))
+
+/* 2 REG_BAR_MODE_CTRL			(Offset 0x04CC) */
+
+#define BIT_SHIFT_BAR_RTY_LMT 16
+#define BIT_MASK_BAR_RTY_LMT 0x3
+#define BIT_BAR_RTY_LMT(x)                                                     \
+	(((x) & BIT_MASK_BAR_RTY_LMT) << BIT_SHIFT_BAR_RTY_LMT)
+#define BITS_BAR_RTY_LMT (BIT_MASK_BAR_RTY_LMT << BIT_SHIFT_BAR_RTY_LMT)
+#define BIT_CLEAR_BAR_RTY_LMT(x) ((x) & (~BITS_BAR_RTY_LMT))
+#define BIT_GET_BAR_RTY_LMT(x)                                                 \
+	(((x) >> BIT_SHIFT_BAR_RTY_LMT) & BIT_MASK_BAR_RTY_LMT)
+#define BIT_SET_BAR_RTY_LMT(x, v)                                              \
+	(BIT_CLEAR_BAR_RTY_LMT(x) | BIT_BAR_RTY_LMT(v))
+
+#define BIT_SHIFT_BAR_PKT_TXTIME_TH 8
+#define BIT_MASK_BAR_PKT_TXTIME_TH 0xff
+#define BIT_BAR_PKT_TXTIME_TH(x)                                               \
+	(((x) & BIT_MASK_BAR_PKT_TXTIME_TH) << BIT_SHIFT_BAR_PKT_TXTIME_TH)
+#define BITS_BAR_PKT_TXTIME_TH                                                 \
+	(BIT_MASK_BAR_PKT_TXTIME_TH << BIT_SHIFT_BAR_PKT_TXTIME_TH)
+#define BIT_CLEAR_BAR_PKT_TXTIME_TH(x) ((x) & (~BITS_BAR_PKT_TXTIME_TH))
+#define BIT_GET_BAR_PKT_TXTIME_TH(x)                                           \
+	(((x) >> BIT_SHIFT_BAR_PKT_TXTIME_TH) & BIT_MASK_BAR_PKT_TXTIME_TH)
+#define BIT_SET_BAR_PKT_TXTIME_TH(x, v)                                        \
+	(BIT_CLEAR_BAR_PKT_TXTIME_TH(x) | BIT_BAR_PKT_TXTIME_TH(v))
+
+#define BIT_BAR_EN_V1 BIT(6)
+
+#define BIT_SHIFT_BAR_PKTNUM_TH_V1 0
+#define BIT_MASK_BAR_PKTNUM_TH_V1 0x3f
+#define BIT_BAR_PKTNUM_TH_V1(x)                                                \
+	(((x) & BIT_MASK_BAR_PKTNUM_TH_V1) << BIT_SHIFT_BAR_PKTNUM_TH_V1)
+#define BITS_BAR_PKTNUM_TH_V1                                                  \
+	(BIT_MASK_BAR_PKTNUM_TH_V1 << BIT_SHIFT_BAR_PKTNUM_TH_V1)
+#define BIT_CLEAR_BAR_PKTNUM_TH_V1(x) ((x) & (~BITS_BAR_PKTNUM_TH_V1))
+#define BIT_GET_BAR_PKTNUM_TH_V1(x)                                            \
+	(((x) >> BIT_SHIFT_BAR_PKTNUM_TH_V1) & BIT_MASK_BAR_PKTNUM_TH_V1)
+#define BIT_SET_BAR_PKTNUM_TH_V1(x, v)                                         \
+	(BIT_CLEAR_BAR_PKTNUM_TH_V1(x) | BIT_BAR_PKTNUM_TH_V1(v))
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_RA_TRY_RATE_AGG_LMT			(Offset 0x04CF) */
+
+#define BIT_SHIFT_RA_TRY_RATE_AGG_LMT_V1 0
+#define BIT_MASK_RA_TRY_RATE_AGG_LMT_V1 0x3f
+#define BIT_RA_TRY_RATE_AGG_LMT_V1(x)                                          \
+	(((x) & BIT_MASK_RA_TRY_RATE_AGG_LMT_V1)                               \
+	 << BIT_SHIFT_RA_TRY_RATE_AGG_LMT_V1)
+#define BITS_RA_TRY_RATE_AGG_LMT_V1                                            \
+	(BIT_MASK_RA_TRY_RATE_AGG_LMT_V1 << BIT_SHIFT_RA_TRY_RATE_AGG_LMT_V1)
+#define BIT_CLEAR_RA_TRY_RATE_AGG_LMT_V1(x)                                    \
+	((x) & (~BITS_RA_TRY_RATE_AGG_LMT_V1))
+#define BIT_GET_RA_TRY_RATE_AGG_LMT_V1(x)                                      \
+	(((x) >> BIT_SHIFT_RA_TRY_RATE_AGG_LMT_V1) &                           \
+	 BIT_MASK_RA_TRY_RATE_AGG_LMT_V1)
+#define BIT_SET_RA_TRY_RATE_AGG_LMT_V1(x, v)                                   \
+	(BIT_CLEAR_RA_TRY_RATE_AGG_LMT_V1(x) | BIT_RA_TRY_RATE_AGG_LMT_V1(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_MACID_SLEEP_CTRL			(Offset 0x04D0) */
+
+#define BIT_SHIFT_DEBUG_PROTOCOL 24
+#define BIT_MASK_DEBUG_PROTOCOL 0xff
+#define BIT_DEBUG_PROTOCOL(x)                                                  \
+	(((x) & BIT_MASK_DEBUG_PROTOCOL) << BIT_SHIFT_DEBUG_PROTOCOL)
+#define BITS_DEBUG_PROTOCOL                                                    \
+	(BIT_MASK_DEBUG_PROTOCOL << BIT_SHIFT_DEBUG_PROTOCOL)
+#define BIT_CLEAR_DEBUG_PROTOCOL(x) ((x) & (~BITS_DEBUG_PROTOCOL))
+#define BIT_GET_DEBUG_PROTOCOL(x)                                              \
+	(((x) >> BIT_SHIFT_DEBUG_PROTOCOL) & BIT_MASK_DEBUG_PROTOCOL)
+#define BIT_SET_DEBUG_PROTOCOL(x, v)                                           \
+	(BIT_CLEAR_DEBUG_PROTOCOL(x) | BIT_DEBUG_PROTOCOL(v))
+
+#define BIT_SHIFT_BCNQ_PGBNDY_RSEL 16
+#define BIT_MASK_BCNQ_PGBNDY_RSEL 0x7
+#define BIT_BCNQ_PGBNDY_RSEL(x)                                                \
+	(((x) & BIT_MASK_BCNQ_PGBNDY_RSEL) << BIT_SHIFT_BCNQ_PGBNDY_RSEL)
+#define BITS_BCNQ_PGBNDY_RSEL                                                  \
+	(BIT_MASK_BCNQ_PGBNDY_RSEL << BIT_SHIFT_BCNQ_PGBNDY_RSEL)
+#define BIT_CLEAR_BCNQ_PGBNDY_RSEL(x) ((x) & (~BITS_BCNQ_PGBNDY_RSEL))
+#define BIT_GET_BCNQ_PGBNDY_RSEL(x)                                            \
+	(((x) >> BIT_SHIFT_BCNQ_PGBNDY_RSEL) & BIT_MASK_BCNQ_PGBNDY_RSEL)
+#define BIT_SET_BCNQ_PGBNDY_RSEL(x, v)                                         \
+	(BIT_CLEAR_BCNQ_PGBNDY_RSEL(x) | BIT_BCNQ_PGBNDY_RSEL(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_MACID_SLEEP2			(Offset 0x04D0) */
+
+#define BIT_SHIFT_MACID95_64PKTSLEEP 0
+#define BIT_MASK_MACID95_64PKTSLEEP 0xffffffffL
+#define BIT_MACID95_64PKTSLEEP(x)                                              \
+	(((x) & BIT_MASK_MACID95_64PKTSLEEP) << BIT_SHIFT_MACID95_64PKTSLEEP)
+#define BITS_MACID95_64PKTSLEEP                                                \
+	(BIT_MASK_MACID95_64PKTSLEEP << BIT_SHIFT_MACID95_64PKTSLEEP)
+#define BIT_CLEAR_MACID95_64PKTSLEEP(x) ((x) & (~BITS_MACID95_64PKTSLEEP))
+#define BIT_GET_MACID95_64PKTSLEEP(x)                                          \
+	(((x) >> BIT_SHIFT_MACID95_64PKTSLEEP) & BIT_MASK_MACID95_64PKTSLEEP)
+#define BIT_SET_MACID95_64PKTSLEEP(x, v)                                       \
+	(BIT_CLEAR_MACID95_64PKTSLEEP(x) | BIT_MACID95_64PKTSLEEP(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_MACID_SLEEP_CTRL			(Offset 0x04D0) */
+
+#define BIT_SHIFT_MACID_SLEEP_SEL 0
+#define BIT_MASK_MACID_SLEEP_SEL 0x7
+#define BIT_MACID_SLEEP_SEL(x)                                                 \
+	(((x) & BIT_MASK_MACID_SLEEP_SEL) << BIT_SHIFT_MACID_SLEEP_SEL)
+#define BITS_MACID_SLEEP_SEL                                                   \
+	(BIT_MASK_MACID_SLEEP_SEL << BIT_SHIFT_MACID_SLEEP_SEL)
+#define BIT_CLEAR_MACID_SLEEP_SEL(x) ((x) & (~BITS_MACID_SLEEP_SEL))
+#define BIT_GET_MACID_SLEEP_SEL(x)                                             \
+	(((x) >> BIT_SHIFT_MACID_SLEEP_SEL) & BIT_MASK_MACID_SLEEP_SEL)
+#define BIT_SET_MACID_SLEEP_SEL(x, v)                                          \
+	(BIT_CLEAR_MACID_SLEEP_SEL(x) | BIT_MACID_SLEEP_SEL(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8881A_SUPPORT)
+
+/* 2 REG_MACID_SLEEP				(Offset 0x04D4) */
+
+#define BIT_SHIFT_MACID31_0_PKTSLEEP 0
+#define BIT_MASK_MACID31_0_PKTSLEEP 0xffffffffL
+#define BIT_MACID31_0_PKTSLEEP(x)                                              \
+	(((x) & BIT_MASK_MACID31_0_PKTSLEEP) << BIT_SHIFT_MACID31_0_PKTSLEEP)
+#define BITS_MACID31_0_PKTSLEEP                                                \
+	(BIT_MASK_MACID31_0_PKTSLEEP << BIT_SHIFT_MACID31_0_PKTSLEEP)
+#define BIT_CLEAR_MACID31_0_PKTSLEEP(x) ((x) & (~BITS_MACID31_0_PKTSLEEP))
+#define BIT_GET_MACID31_0_PKTSLEEP(x)                                          \
+	(((x) >> BIT_SHIFT_MACID31_0_PKTSLEEP) & BIT_MASK_MACID31_0_PKTSLEEP)
+#define BIT_SET_MACID31_0_PKTSLEEP(x, v)                                       \
+	(BIT_CLEAR_MACID31_0_PKTSLEEP(x) | BIT_MACID31_0_PKTSLEEP(v))
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_MACID_SLEEP				(Offset 0x04D4) */
+
+#define BIT_SHIFT_MACID31_0PKTSLEEP 0
+#define BIT_MASK_MACID31_0PKTSLEEP 0xffffffffL
+#define BIT_MACID31_0PKTSLEEP(x)                                               \
+	(((x) & BIT_MASK_MACID31_0PKTSLEEP) << BIT_SHIFT_MACID31_0PKTSLEEP)
+#define BITS_MACID31_0PKTSLEEP                                                 \
+	(BIT_MASK_MACID31_0PKTSLEEP << BIT_SHIFT_MACID31_0PKTSLEEP)
+#define BIT_CLEAR_MACID31_0PKTSLEEP(x) ((x) & (~BITS_MACID31_0PKTSLEEP))
+#define BIT_GET_MACID31_0PKTSLEEP(x)                                           \
+	(((x) >> BIT_SHIFT_MACID31_0PKTSLEEP) & BIT_MASK_MACID31_0PKTSLEEP)
+#define BIT_SET_MACID31_0PKTSLEEP(x, v)                                        \
+	(BIT_CLEAR_MACID31_0PKTSLEEP(x) | BIT_MACID31_0PKTSLEEP(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_MACID_SLEEP_INFO			(Offset 0x04D4) */
+
+#define BIT_SHIFT_MACID_SLEEP_INFO 0
+#define BIT_MASK_MACID_SLEEP_INFO 0xffffffffL
+#define BIT_MACID_SLEEP_INFO(x)                                                \
+	(((x) & BIT_MASK_MACID_SLEEP_INFO) << BIT_SHIFT_MACID_SLEEP_INFO)
+#define BITS_MACID_SLEEP_INFO                                                  \
+	(BIT_MASK_MACID_SLEEP_INFO << BIT_SHIFT_MACID_SLEEP_INFO)
+#define BIT_CLEAR_MACID_SLEEP_INFO(x) ((x) & (~BITS_MACID_SLEEP_INFO))
+#define BIT_GET_MACID_SLEEP_INFO(x)                                            \
+	(((x) >> BIT_SHIFT_MACID_SLEEP_INFO) & BIT_MASK_MACID_SLEEP_INFO)
+#define BIT_SET_MACID_SLEEP_INFO(x, v)                                         \
+	(BIT_CLEAR_MACID_SLEEP_INFO(x) | BIT_MACID_SLEEP_INFO(v))
+
+#define BIT_SHIFT_PTCL_TOTAL_PG_V3 0
+#define BIT_MASK_PTCL_TOTAL_PG_V3 0x1fff
+#define BIT_PTCL_TOTAL_PG_V3(x)                                                \
+	(((x) & BIT_MASK_PTCL_TOTAL_PG_V3) << BIT_SHIFT_PTCL_TOTAL_PG_V3)
+#define BITS_PTCL_TOTAL_PG_V3                                                  \
+	(BIT_MASK_PTCL_TOTAL_PG_V3 << BIT_SHIFT_PTCL_TOTAL_PG_V3)
+#define BIT_CLEAR_PTCL_TOTAL_PG_V3(x) ((x) & (~BITS_PTCL_TOTAL_PG_V3))
+#define BIT_GET_PTCL_TOTAL_PG_V3(x)                                            \
+	(((x) >> BIT_SHIFT_PTCL_TOTAL_PG_V3) & BIT_MASK_PTCL_TOTAL_PG_V3)
+#define BIT_SET_PTCL_TOTAL_PG_V3(x, v)                                         \
+	(BIT_CLEAR_PTCL_TOTAL_PG_V3(x) | BIT_PTCL_TOTAL_PG_V3(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8881A_SUPPORT)
+
+/* 2 REG_HW_SEQ0				(Offset 0x04D8) */
+
+#define BIT_SHIFT_HW_SSN_SEQ0 0
+#define BIT_MASK_HW_SSN_SEQ0 0xfff
+#define BIT_HW_SSN_SEQ0(x)                                                     \
+	(((x) & BIT_MASK_HW_SSN_SEQ0) << BIT_SHIFT_HW_SSN_SEQ0)
+#define BITS_HW_SSN_SEQ0 (BIT_MASK_HW_SSN_SEQ0 << BIT_SHIFT_HW_SSN_SEQ0)
+#define BIT_CLEAR_HW_SSN_SEQ0(x) ((x) & (~BITS_HW_SSN_SEQ0))
+#define BIT_GET_HW_SSN_SEQ0(x)                                                 \
+	(((x) >> BIT_SHIFT_HW_SSN_SEQ0) & BIT_MASK_HW_SSN_SEQ0)
+#define BIT_SET_HW_SSN_SEQ0(x, v)                                              \
+	(BIT_CLEAR_HW_SSN_SEQ0(x) | BIT_HW_SSN_SEQ0(v))
+
+/* 2 REG_HW_SEQ1				(Offset 0x04DA) */
+
+#define BIT_SHIFT_HW_SSN_SEQ1 0
+#define BIT_MASK_HW_SSN_SEQ1 0xfff
+#define BIT_HW_SSN_SEQ1(x)                                                     \
+	(((x) & BIT_MASK_HW_SSN_SEQ1) << BIT_SHIFT_HW_SSN_SEQ1)
+#define BITS_HW_SSN_SEQ1 (BIT_MASK_HW_SSN_SEQ1 << BIT_SHIFT_HW_SSN_SEQ1)
+#define BIT_CLEAR_HW_SSN_SEQ1(x) ((x) & (~BITS_HW_SSN_SEQ1))
+#define BIT_GET_HW_SSN_SEQ1(x)                                                 \
+	(((x) >> BIT_SHIFT_HW_SSN_SEQ1) & BIT_MASK_HW_SSN_SEQ1)
+#define BIT_SET_HW_SSN_SEQ1(x, v)                                              \
+	(BIT_CLEAR_HW_SSN_SEQ1(x) | BIT_HW_SSN_SEQ1(v))
+
+/* 2 REG_HW_SEQ2				(Offset 0x04DC) */
+
+#define BIT_SHIFT_HW_SSN_SEQ2 0
+#define BIT_MASK_HW_SSN_SEQ2 0xfff
+#define BIT_HW_SSN_SEQ2(x)                                                     \
+	(((x) & BIT_MASK_HW_SSN_SEQ2) << BIT_SHIFT_HW_SSN_SEQ2)
+#define BITS_HW_SSN_SEQ2 (BIT_MASK_HW_SSN_SEQ2 << BIT_SHIFT_HW_SSN_SEQ2)
+#define BIT_CLEAR_HW_SSN_SEQ2(x) ((x) & (~BITS_HW_SSN_SEQ2))
+#define BIT_GET_HW_SSN_SEQ2(x)                                                 \
+	(((x) >> BIT_SHIFT_HW_SSN_SEQ2) & BIT_MASK_HW_SSN_SEQ2)
+#define BIT_SET_HW_SSN_SEQ2(x, v)                                              \
+	(BIT_CLEAR_HW_SSN_SEQ2(x) | BIT_HW_SSN_SEQ2(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_HW_SEQ3				(Offset 0x04DE) */
+
+#define BIT_SHIFT_CSI_HWSSN_SEL 12
+#define BIT_MASK_CSI_HWSSN_SEL 0x3
+#define BIT_CSI_HWSSN_SEL(x)                                                   \
+	(((x) & BIT_MASK_CSI_HWSSN_SEL) << BIT_SHIFT_CSI_HWSSN_SEL)
+#define BITS_CSI_HWSSN_SEL (BIT_MASK_CSI_HWSSN_SEL << BIT_SHIFT_CSI_HWSSN_SEL)
+#define BIT_CLEAR_CSI_HWSSN_SEL(x) ((x) & (~BITS_CSI_HWSSN_SEL))
+#define BIT_GET_CSI_HWSSN_SEL(x)                                               \
+	(((x) >> BIT_SHIFT_CSI_HWSSN_SEL) & BIT_MASK_CSI_HWSSN_SEL)
+#define BIT_SET_CSI_HWSSN_SEL(x, v)                                            \
+	(BIT_CLEAR_CSI_HWSSN_SEL(x) | BIT_CSI_HWSSN_SEL(v))
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_HW_SEQ3				(Offset 0x04DE) */
+
+#define BIT_SHIFT_CSI_HWSEQ_SEL 12
+#define BIT_MASK_CSI_HWSEQ_SEL 0x3
+#define BIT_CSI_HWSEQ_SEL(x)                                                   \
+	(((x) & BIT_MASK_CSI_HWSEQ_SEL) << BIT_SHIFT_CSI_HWSEQ_SEL)
+#define BITS_CSI_HWSEQ_SEL (BIT_MASK_CSI_HWSEQ_SEL << BIT_SHIFT_CSI_HWSEQ_SEL)
+#define BIT_CLEAR_CSI_HWSEQ_SEL(x) ((x) & (~BITS_CSI_HWSEQ_SEL))
+#define BIT_GET_CSI_HWSEQ_SEL(x)                                               \
+	(((x) >> BIT_SHIFT_CSI_HWSEQ_SEL) & BIT_MASK_CSI_HWSEQ_SEL)
+#define BIT_SET_CSI_HWSEQ_SEL(x, v)                                            \
+	(BIT_CLEAR_CSI_HWSEQ_SEL(x) | BIT_CSI_HWSEQ_SEL(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8881A_SUPPORT)
+
+/* 2 REG_HW_SEQ3				(Offset 0x04DE) */
+
+#define BIT_SHIFT_HW_SSN_SEQ3 0
+#define BIT_MASK_HW_SSN_SEQ3 0xfff
+#define BIT_HW_SSN_SEQ3(x)                                                     \
+	(((x) & BIT_MASK_HW_SSN_SEQ3) << BIT_SHIFT_HW_SSN_SEQ3)
+#define BITS_HW_SSN_SEQ3 (BIT_MASK_HW_SSN_SEQ3 << BIT_SHIFT_HW_SSN_SEQ3)
+#define BIT_CLEAR_HW_SSN_SEQ3(x) ((x) & (~BITS_HW_SSN_SEQ3))
+#define BIT_GET_HW_SSN_SEQ3(x)                                                 \
+	(((x) >> BIT_SHIFT_HW_SSN_SEQ3) & BIT_MASK_HW_SSN_SEQ3)
+#define BIT_SET_HW_SSN_SEQ3(x, v)                                              \
+	(BIT_CLEAR_HW_SSN_SEQ3(x) | BIT_HW_SSN_SEQ3(v))
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_CSI_SEQ				(Offset 0x04DE) */
+
+#define BIT_SHIFT_HW_CSI_SEQ 0
+#define BIT_MASK_HW_CSI_SEQ 0xfff
+#define BIT_HW_CSI_SEQ(x) (((x) & BIT_MASK_HW_CSI_SEQ) << BIT_SHIFT_HW_CSI_SEQ)
+#define BITS_HW_CSI_SEQ (BIT_MASK_HW_CSI_SEQ << BIT_SHIFT_HW_CSI_SEQ)
+#define BIT_CLEAR_HW_CSI_SEQ(x) ((x) & (~BITS_HW_CSI_SEQ))
+#define BIT_GET_HW_CSI_SEQ(x)                                                  \
+	(((x) >> BIT_SHIFT_HW_CSI_SEQ) & BIT_MASK_HW_CSI_SEQ)
+#define BIT_SET_HW_CSI_SEQ(x, v) (BIT_CLEAR_HW_CSI_SEQ(x) | BIT_HW_CSI_SEQ(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_NULL_PKT_STATUS_V1			(Offset 0x04E0) */
+
+#define BIT_SHIFT_PTCL_TOTAL_PG_V1 2
+#define BIT_MASK_PTCL_TOTAL_PG_V1 0x1fff
+#define BIT_PTCL_TOTAL_PG_V1(x)                                                \
+	(((x) & BIT_MASK_PTCL_TOTAL_PG_V1) << BIT_SHIFT_PTCL_TOTAL_PG_V1)
+#define BITS_PTCL_TOTAL_PG_V1                                                  \
+	(BIT_MASK_PTCL_TOTAL_PG_V1 << BIT_SHIFT_PTCL_TOTAL_PG_V1)
+#define BIT_CLEAR_PTCL_TOTAL_PG_V1(x) ((x) & (~BITS_PTCL_TOTAL_PG_V1))
+#define BIT_GET_PTCL_TOTAL_PG_V1(x)                                            \
+	(((x) >> BIT_SHIFT_PTCL_TOTAL_PG_V1) & BIT_MASK_PTCL_TOTAL_PG_V1)
+#define BIT_SET_PTCL_TOTAL_PG_V1(x, v)                                         \
+	(BIT_CLEAR_PTCL_TOTAL_PG_V1(x) | BIT_PTCL_TOTAL_PG_V1(v))
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_NULL_PKT_STATUS_V1			(Offset 0x04E0) */
+
+#define BIT_SHIFT_PTCL_TOTAL_PG_V2 2
+#define BIT_MASK_PTCL_TOTAL_PG_V2 0x3fff
+#define BIT_PTCL_TOTAL_PG_V2(x)                                                \
+	(((x) & BIT_MASK_PTCL_TOTAL_PG_V2) << BIT_SHIFT_PTCL_TOTAL_PG_V2)
+#define BITS_PTCL_TOTAL_PG_V2                                                  \
+	(BIT_MASK_PTCL_TOTAL_PG_V2 << BIT_SHIFT_PTCL_TOTAL_PG_V2)
+#define BIT_CLEAR_PTCL_TOTAL_PG_V2(x) ((x) & (~BITS_PTCL_TOTAL_PG_V2))
+#define BIT_GET_PTCL_TOTAL_PG_V2(x)                                            \
+	(((x) >> BIT_SHIFT_PTCL_TOTAL_PG_V2) & BIT_MASK_PTCL_TOTAL_PG_V2)
+#define BIT_SET_PTCL_TOTAL_PG_V2(x, v)                                         \
+	(BIT_CLEAR_PTCL_TOTAL_PG_V2(x) | BIT_PTCL_TOTAL_PG_V2(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_NULL_PKT_STATUS			(Offset 0x04E0) */
+
+#define BIT_TX_NULL_1 BIT(1)
+#define BIT_TX_NULL_0 BIT(0)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_PTCL_ERR_STATUS_V1			(Offset 0x04E2) */
+
+#define BIT_MUARB_SEARCH_ERR BIT(14)
+#define BIT_MU_BFEN_ERR BIT(12)
+#define BIT_NDPA_DROPNULL_ERR BIT(11)
+#define BIT_NDPA_DROPPKT_ERR BIT(10)
+#define BIT_PTCL_PKYIN_ERR BIT(9)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_PTCL_ERR_STATUS_V1			(Offset 0x04E2) */
+
+#define BIT_SHIFT_PTCL_TOTAL_PG_V4 8
+#define BIT_MASK_PTCL_TOTAL_PG_V4 0xff
+#define BIT_PTCL_TOTAL_PG_V4(x)                                                \
+	(((x) & BIT_MASK_PTCL_TOTAL_PG_V4) << BIT_SHIFT_PTCL_TOTAL_PG_V4)
+#define BITS_PTCL_TOTAL_PG_V4                                                  \
+	(BIT_MASK_PTCL_TOTAL_PG_V4 << BIT_SHIFT_PTCL_TOTAL_PG_V4)
+#define BIT_CLEAR_PTCL_TOTAL_PG_V4(x) ((x) & (~BITS_PTCL_TOTAL_PG_V4))
+#define BIT_GET_PTCL_TOTAL_PG_V4(x)                                            \
+	(((x) >> BIT_SHIFT_PTCL_TOTAL_PG_V4) & BIT_MASK_PTCL_TOTAL_PG_V4)
+#define BIT_SET_PTCL_TOTAL_PG_V4(x, v)                                         \
+	(BIT_CLEAR_PTCL_TOTAL_PG_V4(x) | BIT_PTCL_TOTAL_PG_V4(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_PTCL_ERR_STATUS_V1			(Offset 0x04E2) */
+
+#define BIT_PTCL_QSELCNL_ERR BIT(8)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_PTCL_ERR_STATUS_V1			(Offset 0x04E2) */
+
+#define BIT_PTCL_TOTAL_PG_8 BIT(7)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_PTCL_ERR_STATUS_V1			(Offset 0x04E2) */
+
+#define BIT_PTCL_RATE_TABLE_INVALID BIT(7)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8881A_SUPPORT)
+
+/* 2 REG_PTCL_ERR_STATUS			(Offset 0x04E2) */
+
+#define BIT_P2P_OFF_DISTX_EN BIT(6)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_PTCL_ERR_STATUS_V1			(Offset 0x04E2) */
+
+#define BIT_PTCL_RATE_TABLE_INVALID_V1 BIT(6)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_PTCL_ERR_STATUS_V1			(Offset 0x04E2) */
+
+#define BIT_FTM_T2R_ERROR BIT(6)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8881A_SUPPORT)
+
+/* 2 REG_PTCL_ERR_STATUS			(Offset 0x04E2) */
+
+#define BIT_PTCL_ERR0 BIT(5)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8814B_SUPPORT)
+
+/* 2 REG_PTCL_ERR_STATUS_V1			(Offset 0x04E2) */
+
+#define BIT_TXTIMEOUT_ERR BIT(5)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8881A_SUPPORT)
+
+/* 2 REG_PTCL_ERR_STATUS			(Offset 0x04E2) */
+
+#define BIT_PTCL_ERR1 BIT(4)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8814B_SUPPORT)
+
+/* 2 REG_PTCL_ERR_STATUS_V1			(Offset 0x04E2) */
+
+#define BIT_NULLPAGE_ERR BIT(4)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8881A_SUPPORT)
+
+/* 2 REG_PTCL_ERR_STATUS			(Offset 0x04E2) */
+
+#define BIT_PTCL_ERR2 BIT(3)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8814B_SUPPORT)
+
+/* 2 REG_PTCL_ERR_STATUS_V1			(Offset 0x04E2) */
+
+#define BIT_CONTENTION_ERR BIT(3)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8881A_SUPPORT)
+
+/* 2 REG_PTCL_ERR_STATUS			(Offset 0x04E2) */
+
+#define BIT_PTCL_ERR3 BIT(2)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8814B_SUPPORT)
+
+/* 2 REG_PTCL_ERR_STATUS_V1			(Offset 0x04E2) */
+
+#define BIT_HEADNULL_ERR BIT(2)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8881A_SUPPORT)
+
+/* 2 REG_PTCL_ERR_STATUS			(Offset 0x04E2) */
+
+#define BIT_PTCL_ERR4 BIT(1)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8814B_SUPPORT)
+
+/* 2 REG_PTCL_ERR_STATUS_V1			(Offset 0x04E2) */
+
+#define BIT_OVERFLOW_ERR BIT(1)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8881A_SUPPORT)
+
+/* 2 REG_PTCL_ERR_STATUS			(Offset 0x04E2) */
+
+#define BIT_PTCL_ERR5 BIT(0)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8814B_SUPPORT)
+
+/* 2 REG_PTCL_ERR_STATUS_V1			(Offset 0x04E2) */
+
+#define BIT_QUEUE_INDEX_ERR BIT(0)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_NULL_PKT_STATUS_EXTEND		(Offset 0x04E3) */
+
+#define BIT_CLI3_TX_NULL_1 BIT(7)
+#define BIT_CLI3_TX_NULL_0 BIT(6)
+#define BIT_CLI2_TX_NULL_1 BIT(5)
+#define BIT_CLI2_TX_NULL_0 BIT(4)
+#define BIT_CLI1_TX_NULL_1 BIT(3)
+#define BIT_CLI1_TX_NULL_0 BIT(2)
+#define BIT_CLI0_TX_NULL_1 BIT(1)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_PTCL_PKT_NUM			(Offset 0x04E3) */
+
+#define BIT_SHIFT_PTCL_TOTAL_PG 0
+#define BIT_MASK_PTCL_TOTAL_PG 0xff
+#define BIT_PTCL_TOTAL_PG(x)                                                   \
+	(((x) & BIT_MASK_PTCL_TOTAL_PG) << BIT_SHIFT_PTCL_TOTAL_PG)
+#define BITS_PTCL_TOTAL_PG (BIT_MASK_PTCL_TOTAL_PG << BIT_SHIFT_PTCL_TOTAL_PG)
+#define BIT_CLEAR_PTCL_TOTAL_PG(x) ((x) & (~BITS_PTCL_TOTAL_PG))
+#define BIT_GET_PTCL_TOTAL_PG(x)                                               \
+	(((x) >> BIT_SHIFT_PTCL_TOTAL_PG) & BIT_MASK_PTCL_TOTAL_PG)
+#define BIT_SET_PTCL_TOTAL_PG(x, v)                                            \
+	(BIT_CLEAR_PTCL_TOTAL_PG(x) | BIT_PTCL_TOTAL_PG(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_NULL_PKT_STATUS_EXTEND		(Offset 0x04E3) */
+
+#define BIT_CLI0_TX_NULL_0 BIT(0)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_TRXRPT_MISS_CNT			(Offset 0x04E3) */
+
+#define BIT_SHIFT_TRXRPT_MISS_CNT 0
+#define BIT_MASK_TRXRPT_MISS_CNT 0x7
+#define BIT_TRXRPT_MISS_CNT(x)                                                 \
+	(((x) & BIT_MASK_TRXRPT_MISS_CNT) << BIT_SHIFT_TRXRPT_MISS_CNT)
+#define BITS_TRXRPT_MISS_CNT                                                   \
+	(BIT_MASK_TRXRPT_MISS_CNT << BIT_SHIFT_TRXRPT_MISS_CNT)
+#define BIT_CLEAR_TRXRPT_MISS_CNT(x) ((x) & (~BITS_TRXRPT_MISS_CNT))
+#define BIT_GET_TRXRPT_MISS_CNT(x)                                             \
+	(((x) >> BIT_SHIFT_TRXRPT_MISS_CNT) & BIT_MASK_TRXRPT_MISS_CNT)
+#define BIT_SET_TRXRPT_MISS_CNT(x, v)                                          \
+	(BIT_CLEAR_TRXRPT_MISS_CNT(x) | BIT_TRXRPT_MISS_CNT(v))
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+/* 2 REG_VIDEO_ENHANCEMENT_FUN		(Offset 0x04E4) */
+
+#define BIT_MAX_PRETX_AGGR_EN BIT(19)
+
+#define BIT_SHIFT_MAX_PRETX_AGGR_TIME 8
+#define BIT_MASK_MAX_PRETX_AGGR_TIME 0x7ff
+#define BIT_MAX_PRETX_AGGR_TIME(x)                                             \
+	(((x) & BIT_MASK_MAX_PRETX_AGGR_TIME) << BIT_SHIFT_MAX_PRETX_AGGR_TIME)
+#define BITS_MAX_PRETX_AGGR_TIME                                               \
+	(BIT_MASK_MAX_PRETX_AGGR_TIME << BIT_SHIFT_MAX_PRETX_AGGR_TIME)
+#define BIT_CLEAR_MAX_PRETX_AGGR_TIME(x) ((x) & (~BITS_MAX_PRETX_AGGR_TIME))
+#define BIT_GET_MAX_PRETX_AGGR_TIME(x)                                         \
+	(((x) >> BIT_SHIFT_MAX_PRETX_AGGR_TIME) & BIT_MASK_MAX_PRETX_AGGR_TIME)
+#define BIT_SET_MAX_PRETX_AGGR_TIME(x, v)                                      \
+	(BIT_CLEAR_MAX_PRETX_AGGR_TIME(x) | BIT_MAX_PRETX_AGGR_TIME(v))
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_NULL_PKT_STATUS_V2			(Offset 0x04E4) */
+
+#define BIT_HIQ_DROP BIT(7)
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+/* 2 REG_VIDEO_ENHANCEMENT_FUN		(Offset 0x04E4) */
+
+#define BIT_HGQ_DEL_EN BIT(7)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_NULL_PKT_STATUS_V2			(Offset 0x04E4) */
+
+#define BIT_MGQ_DROP BIT(6)
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+/* 2 REG_VIDEO_ENHANCEMENT_FUN		(Offset 0x04E4) */
+
+#define BIT_MGQ_DEL_EN BIT(6)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+
+/* 2 REG_VIDEO_ENHANCEMENT_FUN		(Offset 0x04E4) */
+
+#define BIT_VIDEO_JUST_DROP BIT(1)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_NULL_PKT_STATUS_V2			(Offset 0x04E4) */
+
+#define BIT_TX_NULL_1_V1 BIT(1)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+
+/* 2 REG_VIDEO_ENHANCEMENT_FUN		(Offset 0x04E4) */
+
+#define BIT_VIDEO_ENHANCEMENT_FUN_EN BIT(0)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_NULL_PKT_STATUS_V2			(Offset 0x04E4) */
+
+#define BIT_TX_NULL_0_V1 BIT(0)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT)
+
+/* 2 REG_PRECNT_CTRL				(Offset 0x04E5) */
+
+#define BIT_SHIFT_COLLISION_DETECT_TIME 12
+#define BIT_MASK_COLLISION_DETECT_TIME 0xf
+#define BIT_COLLISION_DETECT_TIME(x)                                           \
+	(((x) & BIT_MASK_COLLISION_DETECT_TIME)                                \
+	 << BIT_SHIFT_COLLISION_DETECT_TIME)
+#define BITS_COLLISION_DETECT_TIME                                             \
+	(BIT_MASK_COLLISION_DETECT_TIME << BIT_SHIFT_COLLISION_DETECT_TIME)
+#define BIT_CLEAR_COLLISION_DETECT_TIME(x) ((x) & (~BITS_COLLISION_DETECT_TIME))
+#define BIT_GET_COLLISION_DETECT_TIME(x)                                       \
+	(((x) >> BIT_SHIFT_COLLISION_DETECT_TIME) &                            \
+	 BIT_MASK_COLLISION_DETECT_TIME)
+#define BIT_SET_COLLISION_DETECT_TIME(x, v)                                    \
+	(BIT_CLEAR_COLLISION_DETECT_TIME(x) | BIT_COLLISION_DETECT_TIME(v))
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_PRECNT_CTRL				(Offset 0x04E5) */
+
+#define BIT_EN_PRECNT BIT(11)
+
+#define BIT_SHIFT_PRECNT_TH 0
+#define BIT_MASK_PRECNT_TH 0x7ff
+#define BIT_PRECNT_TH(x) (((x) & BIT_MASK_PRECNT_TH) << BIT_SHIFT_PRECNT_TH)
+#define BITS_PRECNT_TH (BIT_MASK_PRECNT_TH << BIT_SHIFT_PRECNT_TH)
+#define BIT_CLEAR_PRECNT_TH(x) ((x) & (~BITS_PRECNT_TH))
+#define BIT_GET_PRECNT_TH(x) (((x) >> BIT_SHIFT_PRECNT_TH) & BIT_MASK_PRECNT_TH)
+#define BIT_SET_PRECNT_TH(x, v) (BIT_CLEAR_PRECNT_TH(x) | BIT_PRECNT_TH(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_NULL_PKT_STATUS_EXTEND_V1		(Offset 0x04E7) */
+
+#define BIT_CLI3_TX_NULL_1_V1 BIT(7)
+#define BIT_CLI3_TX_NULL_0_V1 BIT(6)
+#define BIT_CLI2_TX_NULL_1_V1 BIT(5)
+#define BIT_CLI2_TX_NULL_0_V1 BIT(4)
+#define BIT_CLI1_TX_NULL_1_V1 BIT(3)
+#define BIT_CLI1_TX_NULL_0_V1 BIT(2)
+#define BIT_CLI0_TX_NULL_1_V1 BIT(1)
+#define BIT_CLI0_TX_NULL_0_V1 BIT(0)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_BT_POLLUTE_PKT_CNT			(Offset 0x04E8) */
+
+#define BIT_SHIFT_BT_POLLUTE_PKT_CNT 0
+#define BIT_MASK_BT_POLLUTE_PKT_CNT 0xffff
+#define BIT_BT_POLLUTE_PKT_CNT(x)                                              \
+	(((x) & BIT_MASK_BT_POLLUTE_PKT_CNT) << BIT_SHIFT_BT_POLLUTE_PKT_CNT)
+#define BITS_BT_POLLUTE_PKT_CNT                                                \
+	(BIT_MASK_BT_POLLUTE_PKT_CNT << BIT_SHIFT_BT_POLLUTE_PKT_CNT)
+#define BIT_CLEAR_BT_POLLUTE_PKT_CNT(x) ((x) & (~BITS_BT_POLLUTE_PKT_CNT))
+#define BIT_GET_BT_POLLUTE_PKT_CNT(x)                                          \
+	(((x) >> BIT_SHIFT_BT_POLLUTE_PKT_CNT) & BIT_MASK_BT_POLLUTE_PKT_CNT)
+#define BIT_SET_BT_POLLUTE_PKT_CNT(x, v)                                       \
+	(BIT_CLEAR_BT_POLLUTE_PKT_CNT(x) | BIT_BT_POLLUTE_PKT_CNT(v))
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_DROP_NUM				(Offset 0x04EC) */
+
+#define BIT_SHIFT_DROP_PKT_NUM 0
+#define BIT_MASK_DROP_PKT_NUM 0xffff
+#define BIT_DROP_PKT_NUM(x)                                                    \
+	(((x) & BIT_MASK_DROP_PKT_NUM) << BIT_SHIFT_DROP_PKT_NUM)
+#define BITS_DROP_PKT_NUM (BIT_MASK_DROP_PKT_NUM << BIT_SHIFT_DROP_PKT_NUM)
+#define BIT_CLEAR_DROP_PKT_NUM(x) ((x) & (~BITS_DROP_PKT_NUM))
+#define BIT_GET_DROP_PKT_NUM(x)                                                \
+	(((x) >> BIT_SHIFT_DROP_PKT_NUM) & BIT_MASK_DROP_PKT_NUM)
+#define BIT_SET_DROP_PKT_NUM(x, v)                                             \
+	(BIT_CLEAR_DROP_PKT_NUM(x) | BIT_DROP_PKT_NUM(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_PTCL_DBG_V1				(Offset 0x04EC) */
+
+#define BIT_SHIFT_PTCL_DBG 0
+#define BIT_MASK_PTCL_DBG 0xffffffffL
+#define BIT_PTCL_DBG(x) (((x) & BIT_MASK_PTCL_DBG) << BIT_SHIFT_PTCL_DBG)
+#define BITS_PTCL_DBG (BIT_MASK_PTCL_DBG << BIT_SHIFT_PTCL_DBG)
+#define BIT_CLEAR_PTCL_DBG(x) ((x) & (~BITS_PTCL_DBG))
+#define BIT_GET_PTCL_DBG(x) (((x) >> BIT_SHIFT_PTCL_DBG) & BIT_MASK_PTCL_DBG)
+#define BIT_SET_PTCL_DBG(x, v) (BIT_CLEAR_PTCL_DBG(x) | BIT_PTCL_DBG(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_PTCL_TX_RPT				(Offset 0x04F0) */
+
+#define BIT_SHIFT_AC_TX_RPT_INFO 0
+#define BIT_MASK_AC_TX_RPT_INFO 0xffffffffffffffffL
+#define BIT_AC_TX_RPT_INFO(x)                                                  \
+	(((x) & BIT_MASK_AC_TX_RPT_INFO) << BIT_SHIFT_AC_TX_RPT_INFO)
+#define BITS_AC_TX_RPT_INFO                                                    \
+	(BIT_MASK_AC_TX_RPT_INFO << BIT_SHIFT_AC_TX_RPT_INFO)
+#define BIT_CLEAR_AC_TX_RPT_INFO(x) ((x) & (~BITS_AC_TX_RPT_INFO))
+#define BIT_GET_AC_TX_RPT_INFO(x)                                              \
+	(((x) >> BIT_SHIFT_AC_TX_RPT_INFO) & BIT_MASK_AC_TX_RPT_INFO)
+#define BIT_SET_AC_TX_RPT_INFO(x, v)                                           \
+	(BIT_CLEAR_AC_TX_RPT_INFO(x) | BIT_AC_TX_RPT_INFO(v))
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_TX_RPT_INFO_L32			(Offset 0x04F0) */
+
+#define BIT_SHIFT_AC_TX_RPT_INFO_L32 0
+#define BIT_MASK_AC_TX_RPT_INFO_L32 0xffffffffL
+#define BIT_AC_TX_RPT_INFO_L32(x)                                              \
+	(((x) & BIT_MASK_AC_TX_RPT_INFO_L32) << BIT_SHIFT_AC_TX_RPT_INFO_L32)
+#define BITS_AC_TX_RPT_INFO_L32                                                \
+	(BIT_MASK_AC_TX_RPT_INFO_L32 << BIT_SHIFT_AC_TX_RPT_INFO_L32)
+#define BIT_CLEAR_AC_TX_RPT_INFO_L32(x) ((x) & (~BITS_AC_TX_RPT_INFO_L32))
+#define BIT_GET_AC_TX_RPT_INFO_L32(x)                                          \
+	(((x) >> BIT_SHIFT_AC_TX_RPT_INFO_L32) & BIT_MASK_AC_TX_RPT_INFO_L32)
+#define BIT_SET_AC_TX_RPT_INFO_L32(x, v)                                       \
+	(BIT_CLEAR_AC_TX_RPT_INFO_L32(x) | BIT_AC_TX_RPT_INFO_L32(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_TXOP_EXTRA_CTRL			(Offset 0x04F0) */
+
+#define BIT_TXOP_EFFICIENCY_EN BIT(0)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_BT_POLLUTE_PKTCNT			(Offset 0x04F0) */
+
+#define BIT_SHIFT_BT_POLLUTE_PKTCNT 0
+#define BIT_MASK_BT_POLLUTE_PKTCNT 0xffff
+#define BIT_BT_POLLUTE_PKTCNT(x)                                               \
+	(((x) & BIT_MASK_BT_POLLUTE_PKTCNT) << BIT_SHIFT_BT_POLLUTE_PKTCNT)
+#define BITS_BT_POLLUTE_PKTCNT                                                 \
+	(BIT_MASK_BT_POLLUTE_PKTCNT << BIT_SHIFT_BT_POLLUTE_PKTCNT)
+#define BIT_CLEAR_BT_POLLUTE_PKTCNT(x) ((x) & (~BITS_BT_POLLUTE_PKTCNT))
+#define BIT_GET_BT_POLLUTE_PKTCNT(x)                                           \
+	(((x) >> BIT_SHIFT_BT_POLLUTE_PKTCNT) & BIT_MASK_BT_POLLUTE_PKTCNT)
+#define BIT_SET_BT_POLLUTE_PKTCNT(x, v)                                        \
+	(BIT_CLEAR_BT_POLLUTE_PKTCNT(x) | BIT_BT_POLLUTE_PKTCNT(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_CPUMGQ_TIMER_CTRL2			(Offset 0x04F4) */
+
+#define BIT_SHIFT_TRI_HEAD_ADDR 16
+#define BIT_MASK_TRI_HEAD_ADDR 0xfff
+#define BIT_TRI_HEAD_ADDR(x)                                                   \
+	(((x) & BIT_MASK_TRI_HEAD_ADDR) << BIT_SHIFT_TRI_HEAD_ADDR)
+#define BITS_TRI_HEAD_ADDR (BIT_MASK_TRI_HEAD_ADDR << BIT_SHIFT_TRI_HEAD_ADDR)
+#define BIT_CLEAR_TRI_HEAD_ADDR(x) ((x) & (~BITS_TRI_HEAD_ADDR))
+#define BIT_GET_TRI_HEAD_ADDR(x)                                               \
+	(((x) >> BIT_SHIFT_TRI_HEAD_ADDR) & BIT_MASK_TRI_HEAD_ADDR)
+#define BIT_SET_TRI_HEAD_ADDR(x, v)                                            \
+	(BIT_CLEAR_TRI_HEAD_ADDR(x) | BIT_TRI_HEAD_ADDR(v))
+
+#define BIT_DROP_TH_EN BIT(8)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_TX_RPT_INFO_H32			(Offset 0x04F4) */
+
+#define BIT_SHIFT_AC_TX_RPT_INFO_H32 0
+#define BIT_MASK_AC_TX_RPT_INFO_H32 0xffffffffL
+#define BIT_AC_TX_RPT_INFO_H32(x)                                              \
+	(((x) & BIT_MASK_AC_TX_RPT_INFO_H32) << BIT_SHIFT_AC_TX_RPT_INFO_H32)
+#define BITS_AC_TX_RPT_INFO_H32                                                \
+	(BIT_MASK_AC_TX_RPT_INFO_H32 << BIT_SHIFT_AC_TX_RPT_INFO_H32)
+#define BIT_CLEAR_AC_TX_RPT_INFO_H32(x) ((x) & (~BITS_AC_TX_RPT_INFO_H32))
+#define BIT_GET_AC_TX_RPT_INFO_H32(x)                                          \
+	(((x) >> BIT_SHIFT_AC_TX_RPT_INFO_H32) & BIT_MASK_AC_TX_RPT_INFO_H32)
+#define BIT_SET_AC_TX_RPT_INFO_H32(x, v)                                       \
+	(BIT_CLEAR_AC_TX_RPT_INFO_H32(x) | BIT_AC_TX_RPT_INFO_H32(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_CPUMGQ_TIMER_CTRL2			(Offset 0x04F4) */
+
+#define BIT_SHIFT_DROP_TH 0
+#define BIT_MASK_DROP_TH 0xff
+#define BIT_DROP_TH(x) (((x) & BIT_MASK_DROP_TH) << BIT_SHIFT_DROP_TH)
+#define BITS_DROP_TH (BIT_MASK_DROP_TH << BIT_SHIFT_DROP_TH)
+#define BIT_CLEAR_DROP_TH(x) ((x) & (~BITS_DROP_TH))
+#define BIT_GET_DROP_TH(x) (((x) >> BIT_SHIFT_DROP_TH) & BIT_MASK_DROP_TH)
+#define BIT_SET_DROP_TH(x, v) (BIT_CLEAR_DROP_TH(x) | BIT_DROP_TH(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_PTCL_DBG_OUT			(Offset 0x04F8) */
+
+#define BIT_SHIFT_PTCL_DBG_OUT 0
+#define BIT_MASK_PTCL_DBG_OUT 0xffffffffL
+#define BIT_PTCL_DBG_OUT(x)                                                    \
+	(((x) & BIT_MASK_PTCL_DBG_OUT) << BIT_SHIFT_PTCL_DBG_OUT)
+#define BITS_PTCL_DBG_OUT (BIT_MASK_PTCL_DBG_OUT << BIT_SHIFT_PTCL_DBG_OUT)
+#define BIT_CLEAR_PTCL_DBG_OUT(x) ((x) & (~BITS_PTCL_DBG_OUT))
+#define BIT_GET_PTCL_DBG_OUT(x)                                                \
+	(((x) >> BIT_SHIFT_PTCL_DBG_OUT) & BIT_MASK_PTCL_DBG_OUT)
+#define BIT_SET_PTCL_DBG_OUT(x, v)                                             \
+	(BIT_CLEAR_PTCL_DBG_OUT(x) | BIT_PTCL_DBG_OUT(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT)
+
+/* 2 REG_DUMMY_PAGE4				(Offset 0x04FC) */
+
+#define BIT_MOREDATA_CTRL2_EN BIT(19)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_DUMMY_PAGE4				(Offset 0x04FC) */
+
+#define BIT_MOREDATA_CTRL2_EN_V2 BIT(19)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT)
+
+/* 2 REG_DUMMY_PAGE4				(Offset 0x04FC) */
+
+#define BIT_MOREDATA_CTRL1_EN BIT(18)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_DUMMY_PAGE4				(Offset 0x04FC) */
+
+#define BIT_MOREDATA_CTRL1_EN_V2 BIT(18)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_DUMMY_PAGE4				(Offset 0x04FC) */
+
+#define BIT_EN_BCN_TRXRPT BIT(17)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8881A_SUPPORT)
+
+/* 2 REG_DUMMY_PAGE4				(Offset 0x04FC) */
+
+#define BIT_PKTIN_MOREDATA_REPLACE_ENABLE BIT(16)
+
+#endif
+
+#if (HALMAC_8822B_SUPPORT)
+
+/* 2 REG_DUMMY_PAGE4_V1			(Offset 0x04FC) */
+
+#define BIT_BCN_EN_EXTHWSEQ BIT(1)
+#define BIT_BCN_EN_HWSEQ BIT(0)
+
+#define BIT_SHIFT_R_MU_STA_GTAB_POSITION 0
+#define BIT_MASK_R_MU_STA_GTAB_POSITION 0xffffffffffffffffL
+#define BIT_R_MU_STA_GTAB_POSITION(x)                                          \
+	(((x) & BIT_MASK_R_MU_STA_GTAB_POSITION)                               \
+	 << BIT_SHIFT_R_MU_STA_GTAB_POSITION)
+#define BITS_R_MU_STA_GTAB_POSITION                                            \
+	(BIT_MASK_R_MU_STA_GTAB_POSITION << BIT_SHIFT_R_MU_STA_GTAB_POSITION)
+#define BIT_CLEAR_R_MU_STA_GTAB_POSITION(x)                                    \
+	((x) & (~BITS_R_MU_STA_GTAB_POSITION))
+#define BIT_GET_R_MU_STA_GTAB_POSITION(x)                                      \
+	(((x) >> BIT_SHIFT_R_MU_STA_GTAB_POSITION) &                           \
+	 BIT_MASK_R_MU_STA_GTAB_POSITION)
+#define BIT_SET_R_MU_STA_GTAB_POSITION(x, v)                                   \
+	(BIT_CLEAR_R_MU_STA_GTAB_POSITION(x) | BIT_R_MU_STA_GTAB_POSITION(v))
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_MOREDATA				(Offset 0x04FE) */
+
+#define BIT_MOREDATA_CTRL2_EN_V1 BIT(3)
+#define BIT_MOREDATA_CTRL1_EN_V1 BIT(2)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_DUMMY_PAGE4_1			(Offset 0x04FE) */
+
+#define BIT_EN_BCN_TRXRPT_V2 BIT(1)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_MOREDATA				(Offset 0x04FE) */
+
+#define BIT_PKTIN_MOREDATA_REPLACE_ENABLE_V1 BIT(0)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_EDCA_VO_PARAM			(Offset 0x0500) */
+
+#define BIT_SHIFT_TXOPLIMIT 16
+#define BIT_MASK_TXOPLIMIT 0x7ff
+#define BIT_TXOPLIMIT(x) (((x) & BIT_MASK_TXOPLIMIT) << BIT_SHIFT_TXOPLIMIT)
+#define BITS_TXOPLIMIT (BIT_MASK_TXOPLIMIT << BIT_SHIFT_TXOPLIMIT)
+#define BIT_CLEAR_TXOPLIMIT(x) ((x) & (~BITS_TXOPLIMIT))
+#define BIT_GET_TXOPLIMIT(x) (((x) >> BIT_SHIFT_TXOPLIMIT) & BIT_MASK_TXOPLIMIT)
+#define BIT_SET_TXOPLIMIT(x, v) (BIT_CLEAR_TXOPLIMIT(x) | BIT_TXOPLIMIT(v))
+
+#define BIT_SHIFT_CW 8
+#define BIT_MASK_CW 0xff
+#define BIT_CW(x) (((x) & BIT_MASK_CW) << BIT_SHIFT_CW)
+#define BITS_CW (BIT_MASK_CW << BIT_SHIFT_CW)
+#define BIT_CLEAR_CW(x) ((x) & (~BITS_CW))
+#define BIT_GET_CW(x) (((x) >> BIT_SHIFT_CW) & BIT_MASK_CW)
+#define BIT_SET_CW(x, v) (BIT_CLEAR_CW(x) | BIT_CW(v))
+
+#define BIT_SHIFT_AIFS 0
+#define BIT_MASK_AIFS 0xff
+#define BIT_AIFS(x) (((x) & BIT_MASK_AIFS) << BIT_SHIFT_AIFS)
+#define BITS_AIFS (BIT_MASK_AIFS << BIT_SHIFT_AIFS)
+#define BIT_CLEAR_AIFS(x) ((x) & (~BITS_AIFS))
+#define BIT_GET_AIFS(x) (((x) >> BIT_SHIFT_AIFS) & BIT_MASK_AIFS)
+#define BIT_SET_AIFS(x, v) (BIT_CLEAR_AIFS(x) | BIT_AIFS(v))
+
+/* 2 REG_BCNTCFG				(Offset 0x0510) */
+
+#define BIT_SHIFT_BCNCW_MAX 12
+#define BIT_MASK_BCNCW_MAX 0xf
+#define BIT_BCNCW_MAX(x) (((x) & BIT_MASK_BCNCW_MAX) << BIT_SHIFT_BCNCW_MAX)
+#define BITS_BCNCW_MAX (BIT_MASK_BCNCW_MAX << BIT_SHIFT_BCNCW_MAX)
+#define BIT_CLEAR_BCNCW_MAX(x) ((x) & (~BITS_BCNCW_MAX))
+#define BIT_GET_BCNCW_MAX(x) (((x) >> BIT_SHIFT_BCNCW_MAX) & BIT_MASK_BCNCW_MAX)
+#define BIT_SET_BCNCW_MAX(x, v) (BIT_CLEAR_BCNCW_MAX(x) | BIT_BCNCW_MAX(v))
+
+#define BIT_SHIFT_BCNCW_MIN 8
+#define BIT_MASK_BCNCW_MIN 0xf
+#define BIT_BCNCW_MIN(x) (((x) & BIT_MASK_BCNCW_MIN) << BIT_SHIFT_BCNCW_MIN)
+#define BITS_BCNCW_MIN (BIT_MASK_BCNCW_MIN << BIT_SHIFT_BCNCW_MIN)
+#define BIT_CLEAR_BCNCW_MIN(x) ((x) & (~BITS_BCNCW_MIN))
+#define BIT_GET_BCNCW_MIN(x) (((x) >> BIT_SHIFT_BCNCW_MIN) & BIT_MASK_BCNCW_MIN)
+#define BIT_SET_BCNCW_MIN(x, v) (BIT_CLEAR_BCNCW_MIN(x) | BIT_BCNCW_MIN(v))
+
+#define BIT_SHIFT_BCNIFS 0
+#define BIT_MASK_BCNIFS 0xff
+#define BIT_BCNIFS(x) (((x) & BIT_MASK_BCNIFS) << BIT_SHIFT_BCNIFS)
+#define BITS_BCNIFS (BIT_MASK_BCNIFS << BIT_SHIFT_BCNIFS)
+#define BIT_CLEAR_BCNIFS(x) ((x) & (~BITS_BCNIFS))
+#define BIT_GET_BCNIFS(x) (((x) >> BIT_SHIFT_BCNIFS) & BIT_MASK_BCNIFS)
+#define BIT_SET_BCNIFS(x, v) (BIT_CLEAR_BCNIFS(x) | BIT_BCNIFS(v))
+
+/* 2 REG_PIFS				(Offset 0x0512) */
+
+#define BIT_SHIFT_PIFS 0
+#define BIT_MASK_PIFS 0xff
+#define BIT_PIFS(x) (((x) & BIT_MASK_PIFS) << BIT_SHIFT_PIFS)
+#define BITS_PIFS (BIT_MASK_PIFS << BIT_SHIFT_PIFS)
+#define BIT_CLEAR_PIFS(x) ((x) & (~BITS_PIFS))
+#define BIT_GET_PIFS(x) (((x) >> BIT_SHIFT_PIFS) & BIT_MASK_PIFS)
+#define BIT_SET_PIFS(x, v) (BIT_CLEAR_PIFS(x) | BIT_PIFS(v))
+
+/* 2 REG_RDG_PIFS				(Offset 0x0513) */
+
+#define BIT_SHIFT_RDG_PIFS 0
+#define BIT_MASK_RDG_PIFS 0xff
+#define BIT_RDG_PIFS(x) (((x) & BIT_MASK_RDG_PIFS) << BIT_SHIFT_RDG_PIFS)
+#define BITS_RDG_PIFS (BIT_MASK_RDG_PIFS << BIT_SHIFT_RDG_PIFS)
+#define BIT_CLEAR_RDG_PIFS(x) ((x) & (~BITS_RDG_PIFS))
+#define BIT_GET_RDG_PIFS(x) (((x) >> BIT_SHIFT_RDG_PIFS) & BIT_MASK_RDG_PIFS)
+#define BIT_SET_RDG_PIFS(x, v) (BIT_CLEAR_RDG_PIFS(x) | BIT_RDG_PIFS(v))
+
+/* 2 REG_SIFS				(Offset 0x0514) */
+
+#define BIT_SHIFT_SIFS_OFDM_TRX 24
+#define BIT_MASK_SIFS_OFDM_TRX 0xff
+#define BIT_SIFS_OFDM_TRX(x)                                                   \
+	(((x) & BIT_MASK_SIFS_OFDM_TRX) << BIT_SHIFT_SIFS_OFDM_TRX)
+#define BITS_SIFS_OFDM_TRX (BIT_MASK_SIFS_OFDM_TRX << BIT_SHIFT_SIFS_OFDM_TRX)
+#define BIT_CLEAR_SIFS_OFDM_TRX(x) ((x) & (~BITS_SIFS_OFDM_TRX))
+#define BIT_GET_SIFS_OFDM_TRX(x)                                               \
+	(((x) >> BIT_SHIFT_SIFS_OFDM_TRX) & BIT_MASK_SIFS_OFDM_TRX)
+#define BIT_SET_SIFS_OFDM_TRX(x, v)                                            \
+	(BIT_CLEAR_SIFS_OFDM_TRX(x) | BIT_SIFS_OFDM_TRX(v))
+
+#define BIT_SHIFT_SIFS_CCK_TRX 16
+#define BIT_MASK_SIFS_CCK_TRX 0xff
+#define BIT_SIFS_CCK_TRX(x)                                                    \
+	(((x) & BIT_MASK_SIFS_CCK_TRX) << BIT_SHIFT_SIFS_CCK_TRX)
+#define BITS_SIFS_CCK_TRX (BIT_MASK_SIFS_CCK_TRX << BIT_SHIFT_SIFS_CCK_TRX)
+#define BIT_CLEAR_SIFS_CCK_TRX(x) ((x) & (~BITS_SIFS_CCK_TRX))
+#define BIT_GET_SIFS_CCK_TRX(x)                                                \
+	(((x) >> BIT_SHIFT_SIFS_CCK_TRX) & BIT_MASK_SIFS_CCK_TRX)
+#define BIT_SET_SIFS_CCK_TRX(x, v)                                             \
+	(BIT_CLEAR_SIFS_CCK_TRX(x) | BIT_SIFS_CCK_TRX(v))
+
+#define BIT_SHIFT_SIFS_OFDM_CTX 8
+#define BIT_MASK_SIFS_OFDM_CTX 0xff
+#define BIT_SIFS_OFDM_CTX(x)                                                   \
+	(((x) & BIT_MASK_SIFS_OFDM_CTX) << BIT_SHIFT_SIFS_OFDM_CTX)
+#define BITS_SIFS_OFDM_CTX (BIT_MASK_SIFS_OFDM_CTX << BIT_SHIFT_SIFS_OFDM_CTX)
+#define BIT_CLEAR_SIFS_OFDM_CTX(x) ((x) & (~BITS_SIFS_OFDM_CTX))
+#define BIT_GET_SIFS_OFDM_CTX(x)                                               \
+	(((x) >> BIT_SHIFT_SIFS_OFDM_CTX) & BIT_MASK_SIFS_OFDM_CTX)
+#define BIT_SET_SIFS_OFDM_CTX(x, v)                                            \
+	(BIT_CLEAR_SIFS_OFDM_CTX(x) | BIT_SIFS_OFDM_CTX(v))
+
+#define BIT_SHIFT_SIFS_CCK_CTX 0
+#define BIT_MASK_SIFS_CCK_CTX 0xff
+#define BIT_SIFS_CCK_CTX(x)                                                    \
+	(((x) & BIT_MASK_SIFS_CCK_CTX) << BIT_SHIFT_SIFS_CCK_CTX)
+#define BITS_SIFS_CCK_CTX (BIT_MASK_SIFS_CCK_CTX << BIT_SHIFT_SIFS_CCK_CTX)
+#define BIT_CLEAR_SIFS_CCK_CTX(x) ((x) & (~BITS_SIFS_CCK_CTX))
+#define BIT_GET_SIFS_CCK_CTX(x)                                                \
+	(((x) >> BIT_SHIFT_SIFS_CCK_CTX) & BIT_MASK_SIFS_CCK_CTX)
+#define BIT_SET_SIFS_CCK_CTX(x, v)                                             \
+	(BIT_CLEAR_SIFS_CCK_CTX(x) | BIT_SIFS_CCK_CTX(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_TSFTR_SYN_OFFSET			(Offset 0x0518) */
+
+#define BIT_SHIFT_TSFTR_SNC_OFFSET 0
+#define BIT_MASK_TSFTR_SNC_OFFSET 0xffff
+#define BIT_TSFTR_SNC_OFFSET(x)                                                \
+	(((x) & BIT_MASK_TSFTR_SNC_OFFSET) << BIT_SHIFT_TSFTR_SNC_OFFSET)
+#define BITS_TSFTR_SNC_OFFSET                                                  \
+	(BIT_MASK_TSFTR_SNC_OFFSET << BIT_SHIFT_TSFTR_SNC_OFFSET)
+#define BIT_CLEAR_TSFTR_SNC_OFFSET(x) ((x) & (~BITS_TSFTR_SNC_OFFSET))
+#define BIT_GET_TSFTR_SNC_OFFSET(x)                                            \
+	(((x) >> BIT_SHIFT_TSFTR_SNC_OFFSET) & BIT_MASK_TSFTR_SNC_OFFSET)
+#define BIT_SET_TSFTR_SNC_OFFSET(x, v)                                         \
+	(BIT_CLEAR_TSFTR_SNC_OFFSET(x) | BIT_TSFTR_SNC_OFFSET(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_AGGR_BREAK_TIME			(Offset 0x051A) */
+
+#define BIT_SHIFT_AGGR_BK_TIME 0
+#define BIT_MASK_AGGR_BK_TIME 0xff
+#define BIT_AGGR_BK_TIME(x)                                                    \
+	(((x) & BIT_MASK_AGGR_BK_TIME) << BIT_SHIFT_AGGR_BK_TIME)
+#define BITS_AGGR_BK_TIME (BIT_MASK_AGGR_BK_TIME << BIT_SHIFT_AGGR_BK_TIME)
+#define BIT_CLEAR_AGGR_BK_TIME(x) ((x) & (~BITS_AGGR_BK_TIME))
+#define BIT_GET_AGGR_BK_TIME(x)                                                \
+	(((x) >> BIT_SHIFT_AGGR_BK_TIME) & BIT_MASK_AGGR_BK_TIME)
+#define BIT_SET_AGGR_BK_TIME(x, v)                                             \
+	(BIT_CLEAR_AGGR_BK_TIME(x) | BIT_AGGR_BK_TIME(v))
+
+/* 2 REG_SLOT				(Offset 0x051B) */
+
+#define BIT_SHIFT_SLOT 0
+#define BIT_MASK_SLOT 0xff
+#define BIT_SLOT(x) (((x) & BIT_MASK_SLOT) << BIT_SHIFT_SLOT)
+#define BITS_SLOT (BIT_MASK_SLOT << BIT_SHIFT_SLOT)
+#define BIT_CLEAR_SLOT(x) ((x) & (~BITS_SLOT))
+#define BIT_GET_SLOT(x) (((x) >> BIT_SHIFT_SLOT) & BIT_MASK_SLOT)
+#define BIT_SET_SLOT(x, v) (BIT_CLEAR_SLOT(x) | BIT_SLOT(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_EDCA_CPUMGQ_PARAM			(Offset 0x051C) */
+
+#define BIT_SHIFT_CW_V1 8
+#define BIT_MASK_CW_V1 0xff
+#define BIT_CW_V1(x) (((x) & BIT_MASK_CW_V1) << BIT_SHIFT_CW_V1)
+#define BITS_CW_V1 (BIT_MASK_CW_V1 << BIT_SHIFT_CW_V1)
+#define BIT_CLEAR_CW_V1(x) ((x) & (~BITS_CW_V1))
+#define BIT_GET_CW_V1(x) (((x) >> BIT_SHIFT_CW_V1) & BIT_MASK_CW_V1)
+#define BIT_SET_CW_V1(x, v) (BIT_CLEAR_CW_V1(x) | BIT_CW_V1(v))
+
+#define BIT_SHIFT_AIFS_V1 0
+#define BIT_MASK_AIFS_V1 0xff
+#define BIT_AIFS_V1(x) (((x) & BIT_MASK_AIFS_V1) << BIT_SHIFT_AIFS_V1)
+#define BITS_AIFS_V1 (BIT_MASK_AIFS_V1 << BIT_SHIFT_AIFS_V1)
+#define BIT_CLEAR_AIFS_V1(x) ((x) & (~BITS_AIFS_V1))
+#define BIT_GET_AIFS_V1(x) (((x) >> BIT_SHIFT_AIFS_V1) & BIT_MASK_AIFS_V1)
+#define BIT_SET_AIFS_V1(x, v) (BIT_CLEAR_AIFS_V1(x) | BIT_AIFS_V1(v))
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_NOA_OFF_ERLY_TIME			(Offset 0x051D) */
+
+#define BIT_SHIFT__NOA_OFF_ERLY_TIME 0
+#define BIT_MASK__NOA_OFF_ERLY_TIME 0xff
+#define BIT__NOA_OFF_ERLY_TIME(x)                                              \
+	(((x) & BIT_MASK__NOA_OFF_ERLY_TIME) << BIT_SHIFT__NOA_OFF_ERLY_TIME)
+#define BITS__NOA_OFF_ERLY_TIME                                                \
+	(BIT_MASK__NOA_OFF_ERLY_TIME << BIT_SHIFT__NOA_OFF_ERLY_TIME)
+#define BIT_CLEAR__NOA_OFF_ERLY_TIME(x) ((x) & (~BITS__NOA_OFF_ERLY_TIME))
+#define BIT_GET__NOA_OFF_ERLY_TIME(x)                                          \
+	(((x) >> BIT_SHIFT__NOA_OFF_ERLY_TIME) & BIT_MASK__NOA_OFF_ERLY_TIME)
+#define BIT_SET__NOA_OFF_ERLY_TIME(x, v)                                       \
+	(BIT_CLEAR__NOA_OFF_ERLY_TIME(x) | BIT__NOA_OFF_ERLY_TIME(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_CPUMGQ_PAUSE			(Offset 0x051E) */
+
+#define BIT_MAC_STOP_CPUMGQ_V1 BIT(0)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_PS_TIMER_CTRL			(Offset 0x051F) */
+
+#define BIT_PS_TIMER_B_EN_V1 BIT(7)
+
+#define BIT_SHIFT_PS_TIMER_B_TSF_SEL_V1 4
+#define BIT_MASK_PS_TIMER_B_TSF_SEL_V1 0x3
+#define BIT_PS_TIMER_B_TSF_SEL_V1(x)                                           \
+	(((x) & BIT_MASK_PS_TIMER_B_TSF_SEL_V1)                                \
+	 << BIT_SHIFT_PS_TIMER_B_TSF_SEL_V1)
+#define BITS_PS_TIMER_B_TSF_SEL_V1                                             \
+	(BIT_MASK_PS_TIMER_B_TSF_SEL_V1 << BIT_SHIFT_PS_TIMER_B_TSF_SEL_V1)
+#define BIT_CLEAR_PS_TIMER_B_TSF_SEL_V1(x) ((x) & (~BITS_PS_TIMER_B_TSF_SEL_V1))
+#define BIT_GET_PS_TIMER_B_TSF_SEL_V1(x)                                       \
+	(((x) >> BIT_SHIFT_PS_TIMER_B_TSF_SEL_V1) &                            \
+	 BIT_MASK_PS_TIMER_B_TSF_SEL_V1)
+#define BIT_SET_PS_TIMER_B_TSF_SEL_V1(x, v)                                    \
+	(BIT_CLEAR_PS_TIMER_B_TSF_SEL_V1(x) | BIT_PS_TIMER_B_TSF_SEL_V1(v))
+
+#define BIT_PS_TIMER_A_EN_V1 BIT(3)
+
+#define BIT_SHIFT_PS_TIMER_A_TSF_SEL_V1 0
+#define BIT_MASK_PS_TIMER_A_TSF_SEL_V1 0x3
+#define BIT_PS_TIMER_A_TSF_SEL_V1(x)                                           \
+	(((x) & BIT_MASK_PS_TIMER_A_TSF_SEL_V1)                                \
+	 << BIT_SHIFT_PS_TIMER_A_TSF_SEL_V1)
+#define BITS_PS_TIMER_A_TSF_SEL_V1                                             \
+	(BIT_MASK_PS_TIMER_A_TSF_SEL_V1 << BIT_SHIFT_PS_TIMER_A_TSF_SEL_V1)
+#define BIT_CLEAR_PS_TIMER_A_TSF_SEL_V1(x) ((x) & (~BITS_PS_TIMER_A_TSF_SEL_V1))
+#define BIT_GET_PS_TIMER_A_TSF_SEL_V1(x)                                       \
+	(((x) >> BIT_SHIFT_PS_TIMER_A_TSF_SEL_V1) &                            \
+	 BIT_MASK_PS_TIMER_A_TSF_SEL_V1)
+#define BIT_SET_PS_TIMER_A_TSF_SEL_V1(x, v)                                    \
+	(BIT_CLEAR_PS_TIMER_A_TSF_SEL_V1(x) | BIT_PS_TIMER_A_TSF_SEL_V1(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_TX_PTCL_CTRL			(Offset 0x0520) */
+
+#define BIT_DIS_EDCCA BIT(15)
+#define BIT_DIS_CCA BIT(14)
+#define BIT_LSIG_TXOP_TXCMD_NAV BIT(13)
+#define BIT_SIFS_BK_EN BIT(12)
+
+#define BIT_SHIFT_TXQ_NAV_MSK 8
+#define BIT_MASK_TXQ_NAV_MSK 0xf
+#define BIT_TXQ_NAV_MSK(x)                                                     \
+	(((x) & BIT_MASK_TXQ_NAV_MSK) << BIT_SHIFT_TXQ_NAV_MSK)
+#define BITS_TXQ_NAV_MSK (BIT_MASK_TXQ_NAV_MSK << BIT_SHIFT_TXQ_NAV_MSK)
+#define BIT_CLEAR_TXQ_NAV_MSK(x) ((x) & (~BITS_TXQ_NAV_MSK))
+#define BIT_GET_TXQ_NAV_MSK(x)                                                 \
+	(((x) >> BIT_SHIFT_TXQ_NAV_MSK) & BIT_MASK_TXQ_NAV_MSK)
+#define BIT_SET_TXQ_NAV_MSK(x, v)                                              \
+	(BIT_CLEAR_TXQ_NAV_MSK(x) | BIT_TXQ_NAV_MSK(v))
+
+#define BIT_DIS_CW BIT(7)
+#define BIT_NAV_END_TXOP BIT(6)
+#define BIT_RDG_END_TXOP BIT(5)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_TX_PTCL_CTRL			(Offset 0x0520) */
+
+#define BIT_AC_INBCN_HOLD BIT(4)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_TX_PTCL_CTRL			(Offset 0x0520) */
+
+#define BIT_MGTQ_TXOP_EN BIT(3)
+#define BIT_MGTQ_RTSMF_EN BIT(2)
+#define BIT_HIQ_RTSMF_EN BIT(1)
+#define BIT_BCN_RTSMF_EN BIT(0)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_TXPAUSE				(Offset 0x0522) */
+
+#define BIT_STOP_BCN_HI_MGT BIT(7)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_TXPAUSE				(Offset 0x0522) */
+
+#define BIT_MAC_STOPCPUMGQ BIT(7)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_TXPAUSE				(Offset 0x0522) */
+
+#define BIT_MAC_STOPBCNQ BIT(6)
+#define BIT_MAC_STOPHIQ BIT(5)
+#define BIT_MAC_STOPMGQ BIT(4)
+#define BIT_MAC_STOPBK BIT(3)
+#define BIT_MAC_STOPBE BIT(2)
+#define BIT_MAC_STOPVI BIT(1)
+#define BIT_MAC_STOPVO BIT(0)
+
+/* 2 REG_DIS_TXREQ_CLR			(Offset 0x0523) */
+
+#define BIT_DIS_BT_CCA BIT(7)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_DIS_TXREQ_CLR			(Offset 0x0523) */
+
+#define BIT_DIS_TXREQ_CLR_CPUMGQ BIT(6)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_DIS_TXREQ_CLR			(Offset 0x0523) */
+
+#define BIT_DIS_TXREQ_CLR_HI BIT(5)
+#define BIT_DIS_TXREQ_CLR_MGQ BIT(4)
+#define BIT_DIS_TXREQ_CLR_VO BIT(3)
+#define BIT_DIS_TXREQ_CLR_VI BIT(2)
+#define BIT_DIS_TXREQ_CLR_BE BIT(1)
+#define BIT_DIS_TXREQ_CLR_BK BIT(0)
+
+/* 2 REG_RD_CTRL				(Offset 0x0524) */
+
+#define BIT_EN_CLR_TXREQ_INCCA BIT(15)
+#define BIT_DIS_TX_OVER_BCNQ BIT(14)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8881A_SUPPORT)
+
+/* 2 REG_RD_CTRL				(Offset 0x0524) */
+
+#define BIT_EN_BCNERR_INCCCA BIT(13)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_RD_CTRL				(Offset 0x0524) */
+
+#define BIT_EN_BCNERR_INCCA BIT(13)
+#define BIT_EN_BCNERR_INEDCCA BIT(12)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_RD_CTRL				(Offset 0x0524) */
+
+#define BIT_EDCCA_MSK_CNTDOWN_EN BIT(11)
+#define BIT_DIS_TXOP_CFE BIT(10)
+#define BIT_DIS_LSIG_CFE BIT(9)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_RD_CTRL				(Offset 0x0524) */
+
+#define BIT_DIS_STBC_CFE BIT(8)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_RD_CTRL				(Offset 0x0524) */
+
+#define BIT_BKQ_RD_INIT_EN BIT(7)
+#define BIT_BEQ_RD_INIT_EN BIT(6)
+#define BIT_VIQ_RD_INIT_EN BIT(5)
+#define BIT_VOQ_RD_INIT_EN BIT(4)
+#define BIT_BKQ_RD_RESP_EN BIT(3)
+#define BIT_BEQ_RD_RESP_EN BIT(2)
+#define BIT_VIQ_RD_RESP_EN BIT(1)
+#define BIT_VOQ_RD_RESP_EN BIT(0)
+
+/* 2 REG_MBSSID_CTRL				(Offset 0x0526) */
+
+#define BIT_MBID_BCNQ7_EN BIT(7)
+#define BIT_MBID_BCNQ6_EN BIT(6)
+#define BIT_MBID_BCNQ5_EN BIT(5)
+#define BIT_MBID_BCNQ4_EN BIT(4)
+#define BIT_MBID_BCNQ3_EN BIT(3)
+#define BIT_MBID_BCNQ2_EN BIT(2)
+#define BIT_MBID_BCNQ1_EN BIT(1)
+#define BIT_MBID_BCNQ0_EN BIT(0)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_P2PPS_CTRL				(Offset 0x0527) */
+
+#define BIT_P2P_CTW_ALLSTASLEEP BIT(7)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_P2PPS_CTRL				(Offset 0x0527) */
+
+#define BIT_P2P_DISTX_SEL BIT(6)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_P2PPS_CTRL				(Offset 0x0527) */
+
+#define BIT_PWR_MGT_EN BIT(5)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_P2PPS_CTRL				(Offset 0x0527) */
+
+#define BIT_P2P_BCN_AREA_EN BIT(4)
+#define BIT_P2P_CTWND_EN BIT(3)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_P2PPS_CTRL				(Offset 0x0527) */
+
+#define BIT_P2P_NOA1_EN BIT(2)
+#define BIT_P2P_NOA0_EN BIT(1)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_P2PPS_CTRL				(Offset 0x0527) */
+
+#define BIT_P2P_BCN_SEL BIT(0)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8881A_SUPPORT)
+
+/* 2 REG_PKT_LIFETIME_CTRL			(Offset 0x0528) */
+
+#define BIT_EN_P2P_CTWND1 BIT(23)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_PKT_LIFETIME_CTRL			(Offset 0x0528) */
+
+#define BIT_EN_TBTT_AREA_FOR_BB BIT(23)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_PKT_LIFETIME_CTRL			(Offset 0x0528) */
+
+#define BIT_EN_BKF_CLR_TXREQ BIT(22)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_PKT_LIFETIME_CTRL			(Offset 0x0528) */
+
+#define BIT_EN_TSFBIT32_RST_P2P BIT(21)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_PKT_LIFETIME_CTRL			(Offset 0x0528) */
+
+#define BIT_EN_BCN_TX_BTCCA BIT(20)
+#define BIT_DIS_PKT_TX_ATIM BIT(19)
+#define BIT_DIS_BCN_DIS_CTN BIT(18)
+#define BIT_EN_NAVEND_RST_TXOP BIT(17)
+#define BIT_EN_FILTER_CCA BIT(16)
+
+#define BIT_SHIFT_CCA_FILTER_THRS 8
+#define BIT_MASK_CCA_FILTER_THRS 0xff
+#define BIT_CCA_FILTER_THRS(x)                                                 \
+	(((x) & BIT_MASK_CCA_FILTER_THRS) << BIT_SHIFT_CCA_FILTER_THRS)
+#define BITS_CCA_FILTER_THRS                                                   \
+	(BIT_MASK_CCA_FILTER_THRS << BIT_SHIFT_CCA_FILTER_THRS)
+#define BIT_CLEAR_CCA_FILTER_THRS(x) ((x) & (~BITS_CCA_FILTER_THRS))
+#define BIT_GET_CCA_FILTER_THRS(x)                                             \
+	(((x) >> BIT_SHIFT_CCA_FILTER_THRS) & BIT_MASK_CCA_FILTER_THRS)
+#define BIT_SET_CCA_FILTER_THRS(x, v)                                          \
+	(BIT_CLEAR_CCA_FILTER_THRS(x) | BIT_CCA_FILTER_THRS(v))
+
+#define BIT_SHIFT_EDCCA_THRS 0
+#define BIT_MASK_EDCCA_THRS 0xff
+#define BIT_EDCCA_THRS(x) (((x) & BIT_MASK_EDCCA_THRS) << BIT_SHIFT_EDCCA_THRS)
+#define BITS_EDCCA_THRS (BIT_MASK_EDCCA_THRS << BIT_SHIFT_EDCCA_THRS)
+#define BIT_CLEAR_EDCCA_THRS(x) ((x) & (~BITS_EDCCA_THRS))
+#define BIT_GET_EDCCA_THRS(x)                                                  \
+	(((x) >> BIT_SHIFT_EDCCA_THRS) & BIT_MASK_EDCCA_THRS)
+#define BIT_SET_EDCCA_THRS(x, v) (BIT_CLEAR_EDCCA_THRS(x) | BIT_EDCCA_THRS(v))
+
+/* 2 REG_P2PPS_SPEC_STATE			(Offset 0x052B) */
+
+#define BIT_SPEC_POWER_STATE BIT(7)
+#define BIT_SPEC_CTWINDOW_ON BIT(6)
+#define BIT_SPEC_BEACON_AREA_ON BIT(5)
+#define BIT_SPEC_CTWIN_EARLY_DISTX BIT(4)
+#define BIT_SPEC_NOA1_OFF_PERIOD BIT(3)
+#define BIT_SPEC_FORCE_DOZE1 BIT(2)
+#define BIT_SPEC_NOA0_OFF_PERIOD BIT(1)
+#define BIT_SPEC_FORCE_DOZE0 BIT(0)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_TXOP_LIMIT_CTRL			(Offset 0x052C) */
+
+#define BIT_SHIFT_TXOP_TBTT_CNT 24
+#define BIT_MASK_TXOP_TBTT_CNT 0xff
+#define BIT_TXOP_TBTT_CNT(x)                                                   \
+	(((x) & BIT_MASK_TXOP_TBTT_CNT) << BIT_SHIFT_TXOP_TBTT_CNT)
+#define BITS_TXOP_TBTT_CNT (BIT_MASK_TXOP_TBTT_CNT << BIT_SHIFT_TXOP_TBTT_CNT)
+#define BIT_CLEAR_TXOP_TBTT_CNT(x) ((x) & (~BITS_TXOP_TBTT_CNT))
+#define BIT_GET_TXOP_TBTT_CNT(x)                                               \
+	(((x) >> BIT_SHIFT_TXOP_TBTT_CNT) & BIT_MASK_TXOP_TBTT_CNT)
+#define BIT_SET_TXOP_TBTT_CNT(x, v)                                            \
+	(BIT_CLEAR_TXOP_TBTT_CNT(x) | BIT_TXOP_TBTT_CNT(v))
+
+#define BIT_SHIFT_TXOP_TBTT_CNT_SEL 20
+#define BIT_MASK_TXOP_TBTT_CNT_SEL 0xf
+#define BIT_TXOP_TBTT_CNT_SEL(x)                                               \
+	(((x) & BIT_MASK_TXOP_TBTT_CNT_SEL) << BIT_SHIFT_TXOP_TBTT_CNT_SEL)
+#define BITS_TXOP_TBTT_CNT_SEL                                                 \
+	(BIT_MASK_TXOP_TBTT_CNT_SEL << BIT_SHIFT_TXOP_TBTT_CNT_SEL)
+#define BIT_CLEAR_TXOP_TBTT_CNT_SEL(x) ((x) & (~BITS_TXOP_TBTT_CNT_SEL))
+#define BIT_GET_TXOP_TBTT_CNT_SEL(x)                                           \
+	(((x) >> BIT_SHIFT_TXOP_TBTT_CNT_SEL) & BIT_MASK_TXOP_TBTT_CNT_SEL)
+#define BIT_SET_TXOP_TBTT_CNT_SEL(x, v)                                        \
+	(BIT_CLEAR_TXOP_TBTT_CNT_SEL(x) | BIT_TXOP_TBTT_CNT_SEL(v))
+
+#define BIT_SHIFT_TXOP_LMT_EN 16
+#define BIT_MASK_TXOP_LMT_EN 0xf
+#define BIT_TXOP_LMT_EN(x)                                                     \
+	(((x) & BIT_MASK_TXOP_LMT_EN) << BIT_SHIFT_TXOP_LMT_EN)
+#define BITS_TXOP_LMT_EN (BIT_MASK_TXOP_LMT_EN << BIT_SHIFT_TXOP_LMT_EN)
+#define BIT_CLEAR_TXOP_LMT_EN(x) ((x) & (~BITS_TXOP_LMT_EN))
+#define BIT_GET_TXOP_LMT_EN(x)                                                 \
+	(((x) >> BIT_SHIFT_TXOP_LMT_EN) & BIT_MASK_TXOP_LMT_EN)
+#define BIT_SET_TXOP_LMT_EN(x, v)                                              \
+	(BIT_CLEAR_TXOP_LMT_EN(x) | BIT_TXOP_LMT_EN(v))
+
+#define BIT_SHIFT_TXOP_LMT_TX_TIME 8
+#define BIT_MASK_TXOP_LMT_TX_TIME 0xff
+#define BIT_TXOP_LMT_TX_TIME(x)                                                \
+	(((x) & BIT_MASK_TXOP_LMT_TX_TIME) << BIT_SHIFT_TXOP_LMT_TX_TIME)
+#define BITS_TXOP_LMT_TX_TIME                                                  \
+	(BIT_MASK_TXOP_LMT_TX_TIME << BIT_SHIFT_TXOP_LMT_TX_TIME)
+#define BIT_CLEAR_TXOP_LMT_TX_TIME(x) ((x) & (~BITS_TXOP_LMT_TX_TIME))
+#define BIT_GET_TXOP_LMT_TX_TIME(x)                                            \
+	(((x) >> BIT_SHIFT_TXOP_LMT_TX_TIME) & BIT_MASK_TXOP_LMT_TX_TIME)
+#define BIT_SET_TXOP_LMT_TX_TIME(x, v)                                         \
+	(BIT_CLEAR_TXOP_LMT_TX_TIME(x) | BIT_TXOP_LMT_TX_TIME(v))
+
+#define BIT_TXOP_CNT_TRIGGER_RESET BIT(7)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_PS_TIMER_A_V2			(Offset 0x052C) */
+
+#define BIT_SHIFT_PS_TIMER_A_V2 0
+#define BIT_MASK_PS_TIMER_A_V2 0xffffffffL
+#define BIT_PS_TIMER_A_V2(x)                                                   \
+	(((x) & BIT_MASK_PS_TIMER_A_V2) << BIT_SHIFT_PS_TIMER_A_V2)
+#define BITS_PS_TIMER_A_V2 (BIT_MASK_PS_TIMER_A_V2 << BIT_SHIFT_PS_TIMER_A_V2)
+#define BIT_CLEAR_PS_TIMER_A_V2(x) ((x) & (~BITS_PS_TIMER_A_V2))
+#define BIT_GET_PS_TIMER_A_V2(x)                                               \
+	(((x) >> BIT_SHIFT_PS_TIMER_A_V2) & BIT_MASK_PS_TIMER_A_V2)
+#define BIT_SET_PS_TIMER_A_V2(x, v)                                            \
+	(BIT_CLEAR_PS_TIMER_A_V2(x) | BIT_PS_TIMER_A_V2(v))
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_TXOP_LIMIT_CTRL			(Offset 0x052C) */
+
+#define BIT_SHIFT_TXOP_LMT_PKT_NUM 0
+#define BIT_MASK_TXOP_LMT_PKT_NUM 0x3f
+#define BIT_TXOP_LMT_PKT_NUM(x)                                                \
+	(((x) & BIT_MASK_TXOP_LMT_PKT_NUM) << BIT_SHIFT_TXOP_LMT_PKT_NUM)
+#define BITS_TXOP_LMT_PKT_NUM                                                  \
+	(BIT_MASK_TXOP_LMT_PKT_NUM << BIT_SHIFT_TXOP_LMT_PKT_NUM)
+#define BIT_CLEAR_TXOP_LMT_PKT_NUM(x) ((x) & (~BITS_TXOP_LMT_PKT_NUM))
+#define BIT_GET_TXOP_LMT_PKT_NUM(x)                                            \
+	(((x) >> BIT_SHIFT_TXOP_LMT_PKT_NUM) & BIT_MASK_TXOP_LMT_PKT_NUM)
+#define BIT_SET_TXOP_LMT_PKT_NUM(x, v)                                         \
+	(BIT_CLEAR_TXOP_LMT_PKT_NUM(x) | BIT_TXOP_LMT_PKT_NUM(v))
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_PS_TIMER_B_V2			(Offset 0x0534) */
+
+#define BIT_FTM_PTT_TSF_R2T_SEL_V1 BIT(24)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_CCA_TXEN_CNT			(Offset 0x0534) */
+
+#define BIT_ENABLE_STOP_UPDATE_NAV BIT(21)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_PS_TIMER_B_V2			(Offset 0x0534) */
+
+#define BIT_TBTT_DIG BIT(20)
+#define BIT_FTM_PTT_TSF_T2R_SEL_V1 BIT(20)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_CCA_TXEN_CNT			(Offset 0x0534) */
+
+#define BIT_ENABLE_GEN_RANDON_SLOT_TX BIT(20)
+#define BIT_ENABLE_RANDOM_SHIFT_TX BIT(19)
+#define BIT_ENABLE_EDCA_REF_FUNCTION BIT(18)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_CCA_TXEN_CNT			(Offset 0x0534) */
+
+#define BIT_CCA_TXEN_CNT_SWITCH BIT(17)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_PS_TIMER_B_V2			(Offset 0x0534) */
+
+#define BIT_FTM_PTT_TSF_SEL_V1 BIT(16)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_CCA_TXEN_CNT			(Offset 0x0534) */
+
+#define BIT_CCA_TXEN_CNT_EN BIT(16)
+
+#define BIT_SHIFT_CCA_TXEN_BIG_CNT 8
+#define BIT_MASK_CCA_TXEN_BIG_CNT 0xff
+#define BIT_CCA_TXEN_BIG_CNT(x)                                                \
+	(((x) & BIT_MASK_CCA_TXEN_BIG_CNT) << BIT_SHIFT_CCA_TXEN_BIG_CNT)
+#define BITS_CCA_TXEN_BIG_CNT                                                  \
+	(BIT_MASK_CCA_TXEN_BIG_CNT << BIT_SHIFT_CCA_TXEN_BIG_CNT)
+#define BIT_CLEAR_CCA_TXEN_BIG_CNT(x) ((x) & (~BITS_CCA_TXEN_BIG_CNT))
+#define BIT_GET_CCA_TXEN_BIG_CNT(x)                                            \
+	(((x) >> BIT_SHIFT_CCA_TXEN_BIG_CNT) & BIT_MASK_CCA_TXEN_BIG_CNT)
+#define BIT_SET_CCA_TXEN_BIG_CNT(x, v)                                         \
+	(BIT_CLEAR_CCA_TXEN_BIG_CNT(x) | BIT_CCA_TXEN_BIG_CNT(v))
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_PS_TIMER_B_V2			(Offset 0x0534) */
+
+#define BIT_SHIFT_PS_TIMER_B_V2 0
+#define BIT_MASK_PS_TIMER_B_V2 0xffffffffL
+#define BIT_PS_TIMER_B_V2(x)                                                   \
+	(((x) & BIT_MASK_PS_TIMER_B_V2) << BIT_SHIFT_PS_TIMER_B_V2)
+#define BITS_PS_TIMER_B_V2 (BIT_MASK_PS_TIMER_B_V2 << BIT_SHIFT_PS_TIMER_B_V2)
+#define BIT_CLEAR_PS_TIMER_B_V2(x) ((x) & (~BITS_PS_TIMER_B_V2))
+#define BIT_GET_PS_TIMER_B_V2(x)                                               \
+	(((x) >> BIT_SHIFT_PS_TIMER_B_V2) & BIT_MASK_PS_TIMER_B_V2)
+#define BIT_SET_PS_TIMER_B_V2(x, v)                                            \
+	(BIT_CLEAR_PS_TIMER_B_V2(x) | BIT_PS_TIMER_B_V2(v))
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_CCA_TXEN_CNT			(Offset 0x0534) */
+
+#define BIT_SHIFT_CCA_TXEN_SMALL_CNT 0
+#define BIT_MASK_CCA_TXEN_SMALL_CNT 0xff
+#define BIT_CCA_TXEN_SMALL_CNT(x)                                              \
+	(((x) & BIT_MASK_CCA_TXEN_SMALL_CNT) << BIT_SHIFT_CCA_TXEN_SMALL_CNT)
+#define BITS_CCA_TXEN_SMALL_CNT                                                \
+	(BIT_MASK_CCA_TXEN_SMALL_CNT << BIT_SHIFT_CCA_TXEN_SMALL_CNT)
+#define BIT_CLEAR_CCA_TXEN_SMALL_CNT(x) ((x) & (~BITS_CCA_TXEN_SMALL_CNT))
+#define BIT_GET_CCA_TXEN_SMALL_CNT(x)                                          \
+	(((x) >> BIT_SHIFT_CCA_TXEN_SMALL_CNT) & BIT_MASK_CCA_TXEN_SMALL_CNT)
+#define BIT_SET_CCA_TXEN_SMALL_CNT(x, v)                                       \
+	(BIT_CLEAR_CCA_TXEN_SMALL_CNT(x) | BIT_CCA_TXEN_SMALL_CNT(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822B_SUPPORT)
+
+/* 2 REG_QUEUE_INCOL_THR			(Offset 0x0538) */
+
+#define BIT_SHIFT_BK_QUEUE_THR 24
+#define BIT_MASK_BK_QUEUE_THR 0xff
+#define BIT_BK_QUEUE_THR(x)                                                    \
+	(((x) & BIT_MASK_BK_QUEUE_THR) << BIT_SHIFT_BK_QUEUE_THR)
+#define BITS_BK_QUEUE_THR (BIT_MASK_BK_QUEUE_THR << BIT_SHIFT_BK_QUEUE_THR)
+#define BIT_CLEAR_BK_QUEUE_THR(x) ((x) & (~BITS_BK_QUEUE_THR))
+#define BIT_GET_BK_QUEUE_THR(x)                                                \
+	(((x) >> BIT_SHIFT_BK_QUEUE_THR) & BIT_MASK_BK_QUEUE_THR)
+#define BIT_SET_BK_QUEUE_THR(x, v)                                             \
+	(BIT_CLEAR_BK_QUEUE_THR(x) | BIT_BK_QUEUE_THR(v))
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_MAX_INTER_COLLISION			(Offset 0x0538) */
+
+#define BIT_SHIFT_MAX_INTER_COLLISION_BK 24
+#define BIT_MASK_MAX_INTER_COLLISION_BK 0xff
+#define BIT_MAX_INTER_COLLISION_BK(x)                                          \
+	(((x) & BIT_MASK_MAX_INTER_COLLISION_BK)                               \
+	 << BIT_SHIFT_MAX_INTER_COLLISION_BK)
+#define BITS_MAX_INTER_COLLISION_BK                                            \
+	(BIT_MASK_MAX_INTER_COLLISION_BK << BIT_SHIFT_MAX_INTER_COLLISION_BK)
+#define BIT_CLEAR_MAX_INTER_COLLISION_BK(x)                                    \
+	((x) & (~BITS_MAX_INTER_COLLISION_BK))
+#define BIT_GET_MAX_INTER_COLLISION_BK(x)                                      \
+	(((x) >> BIT_SHIFT_MAX_INTER_COLLISION_BK) &                           \
+	 BIT_MASK_MAX_INTER_COLLISION_BK)
+#define BIT_SET_MAX_INTER_COLLISION_BK(x, v)                                   \
+	(BIT_CLEAR_MAX_INTER_COLLISION_BK(x) | BIT_MAX_INTER_COLLISION_BK(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822B_SUPPORT)
+
+/* 2 REG_QUEUE_INCOL_THR			(Offset 0x0538) */
+
+#define BIT_SHIFT_BE_QUEUE_THR 16
+#define BIT_MASK_BE_QUEUE_THR 0xff
+#define BIT_BE_QUEUE_THR(x)                                                    \
+	(((x) & BIT_MASK_BE_QUEUE_THR) << BIT_SHIFT_BE_QUEUE_THR)
+#define BITS_BE_QUEUE_THR (BIT_MASK_BE_QUEUE_THR << BIT_SHIFT_BE_QUEUE_THR)
+#define BIT_CLEAR_BE_QUEUE_THR(x) ((x) & (~BITS_BE_QUEUE_THR))
+#define BIT_GET_BE_QUEUE_THR(x)                                                \
+	(((x) >> BIT_SHIFT_BE_QUEUE_THR) & BIT_MASK_BE_QUEUE_THR)
+#define BIT_SET_BE_QUEUE_THR(x, v)                                             \
+	(BIT_CLEAR_BE_QUEUE_THR(x) | BIT_BE_QUEUE_THR(v))
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_MAX_INTER_COLLISION			(Offset 0x0538) */
+
+#define BIT_SHIFT_MAX_INTER_COLLISION_BE 16
+#define BIT_MASK_MAX_INTER_COLLISION_BE 0xff
+#define BIT_MAX_INTER_COLLISION_BE(x)                                          \
+	(((x) & BIT_MASK_MAX_INTER_COLLISION_BE)                               \
+	 << BIT_SHIFT_MAX_INTER_COLLISION_BE)
+#define BITS_MAX_INTER_COLLISION_BE                                            \
+	(BIT_MASK_MAX_INTER_COLLISION_BE << BIT_SHIFT_MAX_INTER_COLLISION_BE)
+#define BIT_CLEAR_MAX_INTER_COLLISION_BE(x)                                    \
+	((x) & (~BITS_MAX_INTER_COLLISION_BE))
+#define BIT_GET_MAX_INTER_COLLISION_BE(x)                                      \
+	(((x) >> BIT_SHIFT_MAX_INTER_COLLISION_BE) &                           \
+	 BIT_MASK_MAX_INTER_COLLISION_BE)
+#define BIT_SET_MAX_INTER_COLLISION_BE(x, v)                                   \
+	(BIT_CLEAR_MAX_INTER_COLLISION_BE(x) | BIT_MAX_INTER_COLLISION_BE(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822B_SUPPORT)
+
+/* 2 REG_QUEUE_INCOL_THR			(Offset 0x0538) */
+
+#define BIT_SHIFT_VI_QUEUE_THR 8
+#define BIT_MASK_VI_QUEUE_THR 0xff
+#define BIT_VI_QUEUE_THR(x)                                                    \
+	(((x) & BIT_MASK_VI_QUEUE_THR) << BIT_SHIFT_VI_QUEUE_THR)
+#define BITS_VI_QUEUE_THR (BIT_MASK_VI_QUEUE_THR << BIT_SHIFT_VI_QUEUE_THR)
+#define BIT_CLEAR_VI_QUEUE_THR(x) ((x) & (~BITS_VI_QUEUE_THR))
+#define BIT_GET_VI_QUEUE_THR(x)                                                \
+	(((x) >> BIT_SHIFT_VI_QUEUE_THR) & BIT_MASK_VI_QUEUE_THR)
+#define BIT_SET_VI_QUEUE_THR(x, v)                                             \
+	(BIT_CLEAR_VI_QUEUE_THR(x) | BIT_VI_QUEUE_THR(v))
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_MAX_INTER_COLLISION			(Offset 0x0538) */
+
+#define BIT_SHIFT_MAX_INTER_COLLISION_VI 8
+#define BIT_MASK_MAX_INTER_COLLISION_VI 0xff
+#define BIT_MAX_INTER_COLLISION_VI(x)                                          \
+	(((x) & BIT_MASK_MAX_INTER_COLLISION_VI)                               \
+	 << BIT_SHIFT_MAX_INTER_COLLISION_VI)
+#define BITS_MAX_INTER_COLLISION_VI                                            \
+	(BIT_MASK_MAX_INTER_COLLISION_VI << BIT_SHIFT_MAX_INTER_COLLISION_VI)
+#define BIT_CLEAR_MAX_INTER_COLLISION_VI(x)                                    \
+	((x) & (~BITS_MAX_INTER_COLLISION_VI))
+#define BIT_GET_MAX_INTER_COLLISION_VI(x)                                      \
+	(((x) >> BIT_SHIFT_MAX_INTER_COLLISION_VI) &                           \
+	 BIT_MASK_MAX_INTER_COLLISION_VI)
+#define BIT_SET_MAX_INTER_COLLISION_VI(x, v)                                   \
+	(BIT_CLEAR_MAX_INTER_COLLISION_VI(x) | BIT_MAX_INTER_COLLISION_VI(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822B_SUPPORT)
+
+/* 2 REG_QUEUE_INCOL_THR			(Offset 0x0538) */
+
+#define BIT_SHIFT_VO_QUEUE_THR 0
+#define BIT_MASK_VO_QUEUE_THR 0xff
+#define BIT_VO_QUEUE_THR(x)                                                    \
+	(((x) & BIT_MASK_VO_QUEUE_THR) << BIT_SHIFT_VO_QUEUE_THR)
+#define BITS_VO_QUEUE_THR (BIT_MASK_VO_QUEUE_THR << BIT_SHIFT_VO_QUEUE_THR)
+#define BIT_CLEAR_VO_QUEUE_THR(x) ((x) & (~BITS_VO_QUEUE_THR))
+#define BIT_GET_VO_QUEUE_THR(x)                                                \
+	(((x) >> BIT_SHIFT_VO_QUEUE_THR) & BIT_MASK_VO_QUEUE_THR)
+#define BIT_SET_VO_QUEUE_THR(x, v)                                             \
+	(BIT_CLEAR_VO_QUEUE_THR(x) | BIT_VO_QUEUE_THR(v))
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_MAX_INTER_COLLISION			(Offset 0x0538) */
+
+#define BIT_SHIFT_MAX_INTER_COLLISION_VO 0
+#define BIT_MASK_MAX_INTER_COLLISION_VO 0xff
+#define BIT_MAX_INTER_COLLISION_VO(x)                                          \
+	(((x) & BIT_MASK_MAX_INTER_COLLISION_VO)                               \
+	 << BIT_SHIFT_MAX_INTER_COLLISION_VO)
+#define BITS_MAX_INTER_COLLISION_VO                                            \
+	(BIT_MASK_MAX_INTER_COLLISION_VO << BIT_SHIFT_MAX_INTER_COLLISION_VO)
+#define BIT_CLEAR_MAX_INTER_COLLISION_VO(x)                                    \
+	((x) & (~BITS_MAX_INTER_COLLISION_VO))
+#define BIT_GET_MAX_INTER_COLLISION_VO(x)                                      \
+	(((x) >> BIT_SHIFT_MAX_INTER_COLLISION_VO) &                           \
+	 BIT_MASK_MAX_INTER_COLLISION_VO)
+#define BIT_SET_MAX_INTER_COLLISION_VO(x, v)                                   \
+	(BIT_CLEAR_MAX_INTER_COLLISION_VO(x) | BIT_MAX_INTER_COLLISION_VO(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822B_SUPPORT)
+
+/* 2 REG_QUEUE_INCOL_EN			(Offset 0x053C) */
+
+#define BIT_QUEUE_INCOL_EN BIT(16)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_MAX_INTER_COLLISION_CNT		(Offset 0x053C) */
+
+#define BIT_MAX_INTER_COLLISION_EN BIT(16)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_QUEUE_INCOL_EN			(Offset 0x053C) */
+
+#define BIT_SHIFT_BK_TRIGGER_NUM_V1 12
+#define BIT_MASK_BK_TRIGGER_NUM_V1 0xf
+#define BIT_BK_TRIGGER_NUM_V1(x)                                               \
+	(((x) & BIT_MASK_BK_TRIGGER_NUM_V1) << BIT_SHIFT_BK_TRIGGER_NUM_V1)
+#define BITS_BK_TRIGGER_NUM_V1                                                 \
+	(BIT_MASK_BK_TRIGGER_NUM_V1 << BIT_SHIFT_BK_TRIGGER_NUM_V1)
+#define BIT_CLEAR_BK_TRIGGER_NUM_V1(x) ((x) & (~BITS_BK_TRIGGER_NUM_V1))
+#define BIT_GET_BK_TRIGGER_NUM_V1(x)                                           \
+	(((x) >> BIT_SHIFT_BK_TRIGGER_NUM_V1) & BIT_MASK_BK_TRIGGER_NUM_V1)
+#define BIT_SET_BK_TRIGGER_NUM_V1(x, v)                                        \
+	(BIT_CLEAR_BK_TRIGGER_NUM_V1(x) | BIT_BK_TRIGGER_NUM_V1(v))
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_MAX_INTER_COLLISION_CNT		(Offset 0x053C) */
+
+#define BIT_SHIFT_MAX_INTER_COLLISION_CNT_BK 12
+#define BIT_MASK_MAX_INTER_COLLISION_CNT_BK 0xf
+#define BIT_MAX_INTER_COLLISION_CNT_BK(x)                                      \
+	(((x) & BIT_MASK_MAX_INTER_COLLISION_CNT_BK)                           \
+	 << BIT_SHIFT_MAX_INTER_COLLISION_CNT_BK)
+#define BITS_MAX_INTER_COLLISION_CNT_BK                                        \
+	(BIT_MASK_MAX_INTER_COLLISION_CNT_BK                                   \
+	 << BIT_SHIFT_MAX_INTER_COLLISION_CNT_BK)
+#define BIT_CLEAR_MAX_INTER_COLLISION_CNT_BK(x)                                \
+	((x) & (~BITS_MAX_INTER_COLLISION_CNT_BK))
+#define BIT_GET_MAX_INTER_COLLISION_CNT_BK(x)                                  \
+	(((x) >> BIT_SHIFT_MAX_INTER_COLLISION_CNT_BK) &                       \
+	 BIT_MASK_MAX_INTER_COLLISION_CNT_BK)
+#define BIT_SET_MAX_INTER_COLLISION_CNT_BK(x, v)                               \
+	(BIT_CLEAR_MAX_INTER_COLLISION_CNT_BK(x) |                             \
+	 BIT_MAX_INTER_COLLISION_CNT_BK(v))
+
+#endif
+
+#if (HALMAC_8822B_SUPPORT)
+
+/* 2 REG_QUEUE_INCOL_EN			(Offset 0x053C) */
+
+#define BIT_SHIFT_BE_TRIGGER_NUM 12
+#define BIT_MASK_BE_TRIGGER_NUM 0xf
+#define BIT_BE_TRIGGER_NUM(x)                                                  \
+	(((x) & BIT_MASK_BE_TRIGGER_NUM) << BIT_SHIFT_BE_TRIGGER_NUM)
+#define BITS_BE_TRIGGER_NUM                                                    \
+	(BIT_MASK_BE_TRIGGER_NUM << BIT_SHIFT_BE_TRIGGER_NUM)
+#define BIT_CLEAR_BE_TRIGGER_NUM(x) ((x) & (~BITS_BE_TRIGGER_NUM))
+#define BIT_GET_BE_TRIGGER_NUM(x)                                              \
+	(((x) >> BIT_SHIFT_BE_TRIGGER_NUM) & BIT_MASK_BE_TRIGGER_NUM)
+#define BIT_SET_BE_TRIGGER_NUM(x, v)                                           \
+	(BIT_CLEAR_BE_TRIGGER_NUM(x) | BIT_BE_TRIGGER_NUM(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_QUEUE_INCOL_EN			(Offset 0x053C) */
+
+#define BIT_SHIFT_BE_TRIGGER_NUM_V1 8
+#define BIT_MASK_BE_TRIGGER_NUM_V1 0xf
+#define BIT_BE_TRIGGER_NUM_V1(x)                                               \
+	(((x) & BIT_MASK_BE_TRIGGER_NUM_V1) << BIT_SHIFT_BE_TRIGGER_NUM_V1)
+#define BITS_BE_TRIGGER_NUM_V1                                                 \
+	(BIT_MASK_BE_TRIGGER_NUM_V1 << BIT_SHIFT_BE_TRIGGER_NUM_V1)
+#define BIT_CLEAR_BE_TRIGGER_NUM_V1(x) ((x) & (~BITS_BE_TRIGGER_NUM_V1))
+#define BIT_GET_BE_TRIGGER_NUM_V1(x)                                           \
+	(((x) >> BIT_SHIFT_BE_TRIGGER_NUM_V1) & BIT_MASK_BE_TRIGGER_NUM_V1)
+#define BIT_SET_BE_TRIGGER_NUM_V1(x, v)                                        \
+	(BIT_CLEAR_BE_TRIGGER_NUM_V1(x) | BIT_BE_TRIGGER_NUM_V1(v))
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_MAX_INTER_COLLISION_CNT		(Offset 0x053C) */
+
+#define BIT_SHIFT_MAX_INTER_COLLISION_CNT_BE 8
+#define BIT_MASK_MAX_INTER_COLLISION_CNT_BE 0xf
+#define BIT_MAX_INTER_COLLISION_CNT_BE(x)                                      \
+	(((x) & BIT_MASK_MAX_INTER_COLLISION_CNT_BE)                           \
+	 << BIT_SHIFT_MAX_INTER_COLLISION_CNT_BE)
+#define BITS_MAX_INTER_COLLISION_CNT_BE                                        \
+	(BIT_MASK_MAX_INTER_COLLISION_CNT_BE                                   \
+	 << BIT_SHIFT_MAX_INTER_COLLISION_CNT_BE)
+#define BIT_CLEAR_MAX_INTER_COLLISION_CNT_BE(x)                                \
+	((x) & (~BITS_MAX_INTER_COLLISION_CNT_BE))
+#define BIT_GET_MAX_INTER_COLLISION_CNT_BE(x)                                  \
+	(((x) >> BIT_SHIFT_MAX_INTER_COLLISION_CNT_BE) &                       \
+	 BIT_MASK_MAX_INTER_COLLISION_CNT_BE)
+#define BIT_SET_MAX_INTER_COLLISION_CNT_BE(x, v)                               \
+	(BIT_CLEAR_MAX_INTER_COLLISION_CNT_BE(x) |                             \
+	 BIT_MAX_INTER_COLLISION_CNT_BE(v))
+
+#endif
+
+#if (HALMAC_8822B_SUPPORT)
+
+/* 2 REG_QUEUE_INCOL_EN			(Offset 0x053C) */
+
+#define BIT_SHIFT_BK_TRIGGER_NUM 8
+#define BIT_MASK_BK_TRIGGER_NUM 0xf
+#define BIT_BK_TRIGGER_NUM(x)                                                  \
+	(((x) & BIT_MASK_BK_TRIGGER_NUM) << BIT_SHIFT_BK_TRIGGER_NUM)
+#define BITS_BK_TRIGGER_NUM                                                    \
+	(BIT_MASK_BK_TRIGGER_NUM << BIT_SHIFT_BK_TRIGGER_NUM)
+#define BIT_CLEAR_BK_TRIGGER_NUM(x) ((x) & (~BITS_BK_TRIGGER_NUM))
+#define BIT_GET_BK_TRIGGER_NUM(x)                                              \
+	(((x) >> BIT_SHIFT_BK_TRIGGER_NUM) & BIT_MASK_BK_TRIGGER_NUM)
+#define BIT_SET_BK_TRIGGER_NUM(x, v)                                           \
+	(BIT_CLEAR_BK_TRIGGER_NUM(x) | BIT_BK_TRIGGER_NUM(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822B_SUPPORT)
+
+/* 2 REG_QUEUE_INCOL_EN			(Offset 0x053C) */
+
+#define BIT_SHIFT_VI_TRIGGER_NUM 4
+#define BIT_MASK_VI_TRIGGER_NUM 0xf
+#define BIT_VI_TRIGGER_NUM(x)                                                  \
+	(((x) & BIT_MASK_VI_TRIGGER_NUM) << BIT_SHIFT_VI_TRIGGER_NUM)
+#define BITS_VI_TRIGGER_NUM                                                    \
+	(BIT_MASK_VI_TRIGGER_NUM << BIT_SHIFT_VI_TRIGGER_NUM)
+#define BIT_CLEAR_VI_TRIGGER_NUM(x) ((x) & (~BITS_VI_TRIGGER_NUM))
+#define BIT_GET_VI_TRIGGER_NUM(x)                                              \
+	(((x) >> BIT_SHIFT_VI_TRIGGER_NUM) & BIT_MASK_VI_TRIGGER_NUM)
+#define BIT_SET_VI_TRIGGER_NUM(x, v)                                           \
+	(BIT_CLEAR_VI_TRIGGER_NUM(x) | BIT_VI_TRIGGER_NUM(v))
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_MAX_INTER_COLLISION_CNT		(Offset 0x053C) */
+
+#define BIT_SHIFT_MAX_INTER_COLLISION_CNT_VI 4
+#define BIT_MASK_MAX_INTER_COLLISION_CNT_VI 0xf
+#define BIT_MAX_INTER_COLLISION_CNT_VI(x)                                      \
+	(((x) & BIT_MASK_MAX_INTER_COLLISION_CNT_VI)                           \
+	 << BIT_SHIFT_MAX_INTER_COLLISION_CNT_VI)
+#define BITS_MAX_INTER_COLLISION_CNT_VI                                        \
+	(BIT_MASK_MAX_INTER_COLLISION_CNT_VI                                   \
+	 << BIT_SHIFT_MAX_INTER_COLLISION_CNT_VI)
+#define BIT_CLEAR_MAX_INTER_COLLISION_CNT_VI(x)                                \
+	((x) & (~BITS_MAX_INTER_COLLISION_CNT_VI))
+#define BIT_GET_MAX_INTER_COLLISION_CNT_VI(x)                                  \
+	(((x) >> BIT_SHIFT_MAX_INTER_COLLISION_CNT_VI) &                       \
+	 BIT_MASK_MAX_INTER_COLLISION_CNT_VI)
+#define BIT_SET_MAX_INTER_COLLISION_CNT_VI(x, v)                               \
+	(BIT_CLEAR_MAX_INTER_COLLISION_CNT_VI(x) |                             \
+	 BIT_MAX_INTER_COLLISION_CNT_VI(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822B_SUPPORT)
+
+/* 2 REG_QUEUE_INCOL_EN			(Offset 0x053C) */
+
+#define BIT_SHIFT_VO_TRIGGER_NUM 0
+#define BIT_MASK_VO_TRIGGER_NUM 0xf
+#define BIT_VO_TRIGGER_NUM(x)                                                  \
+	(((x) & BIT_MASK_VO_TRIGGER_NUM) << BIT_SHIFT_VO_TRIGGER_NUM)
+#define BITS_VO_TRIGGER_NUM                                                    \
+	(BIT_MASK_VO_TRIGGER_NUM << BIT_SHIFT_VO_TRIGGER_NUM)
+#define BIT_CLEAR_VO_TRIGGER_NUM(x) ((x) & (~BITS_VO_TRIGGER_NUM))
+#define BIT_GET_VO_TRIGGER_NUM(x)                                              \
+	(((x) >> BIT_SHIFT_VO_TRIGGER_NUM) & BIT_MASK_VO_TRIGGER_NUM)
+#define BIT_SET_VO_TRIGGER_NUM(x, v)                                           \
+	(BIT_CLEAR_VO_TRIGGER_NUM(x) | BIT_VO_TRIGGER_NUM(v))
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_MAX_INTER_COLLISION_CNT		(Offset 0x053C) */
+
+#define BIT_SHIFT_MAX_INTER_COLLISION_CNT_VO 0
+#define BIT_MASK_MAX_INTER_COLLISION_CNT_VO 0xf
+#define BIT_MAX_INTER_COLLISION_CNT_VO(x)                                      \
+	(((x) & BIT_MASK_MAX_INTER_COLLISION_CNT_VO)                           \
+	 << BIT_SHIFT_MAX_INTER_COLLISION_CNT_VO)
+#define BITS_MAX_INTER_COLLISION_CNT_VO                                        \
+	(BIT_MASK_MAX_INTER_COLLISION_CNT_VO                                   \
+	 << BIT_SHIFT_MAX_INTER_COLLISION_CNT_VO)
+#define BIT_CLEAR_MAX_INTER_COLLISION_CNT_VO(x)                                \
+	((x) & (~BITS_MAX_INTER_COLLISION_CNT_VO))
+#define BIT_GET_MAX_INTER_COLLISION_CNT_VO(x)                                  \
+	(((x) >> BIT_SHIFT_MAX_INTER_COLLISION_CNT_VO) &                       \
+	 BIT_MASK_MAX_INTER_COLLISION_CNT_VO)
+#define BIT_SET_MAX_INTER_COLLISION_CNT_VO(x, v)                               \
+	(BIT_CLEAR_MAX_INTER_COLLISION_CNT_VO(x) |                             \
+	 BIT_MAX_INTER_COLLISION_CNT_VO(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_TBTT_PROHIBIT			(Offset 0x0540) */
+
+#define BIT_SHIFT_TBTT_HOLD_TIME_AP 8
+#define BIT_MASK_TBTT_HOLD_TIME_AP 0xfff
+#define BIT_TBTT_HOLD_TIME_AP(x)                                               \
+	(((x) & BIT_MASK_TBTT_HOLD_TIME_AP) << BIT_SHIFT_TBTT_HOLD_TIME_AP)
+#define BITS_TBTT_HOLD_TIME_AP                                                 \
+	(BIT_MASK_TBTT_HOLD_TIME_AP << BIT_SHIFT_TBTT_HOLD_TIME_AP)
+#define BIT_CLEAR_TBTT_HOLD_TIME_AP(x) ((x) & (~BITS_TBTT_HOLD_TIME_AP))
+#define BIT_GET_TBTT_HOLD_TIME_AP(x)                                           \
+	(((x) >> BIT_SHIFT_TBTT_HOLD_TIME_AP) & BIT_MASK_TBTT_HOLD_TIME_AP)
+#define BIT_SET_TBTT_HOLD_TIME_AP(x, v)                                        \
+	(BIT_CLEAR_TBTT_HOLD_TIME_AP(x) | BIT_TBTT_HOLD_TIME_AP(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_TBTT_PROHIBIT			(Offset 0x0540) */
+
+#define BIT_SHIFT_TBTT_HOLD_TIME_INFRA 4
+#define BIT_MASK_TBTT_HOLD_TIME_INFRA 0xf
+#define BIT_TBTT_HOLD_TIME_INFRA(x)                                            \
+	(((x) & BIT_MASK_TBTT_HOLD_TIME_INFRA)                                 \
+	 << BIT_SHIFT_TBTT_HOLD_TIME_INFRA)
+#define BITS_TBTT_HOLD_TIME_INFRA                                              \
+	(BIT_MASK_TBTT_HOLD_TIME_INFRA << BIT_SHIFT_TBTT_HOLD_TIME_INFRA)
+#define BIT_CLEAR_TBTT_HOLD_TIME_INFRA(x) ((x) & (~BITS_TBTT_HOLD_TIME_INFRA))
+#define BIT_GET_TBTT_HOLD_TIME_INFRA(x)                                        \
+	(((x) >> BIT_SHIFT_TBTT_HOLD_TIME_INFRA) &                             \
+	 BIT_MASK_TBTT_HOLD_TIME_INFRA)
+#define BIT_SET_TBTT_HOLD_TIME_INFRA(x, v)                                     \
+	(BIT_CLEAR_TBTT_HOLD_TIME_INFRA(x) | BIT_TBTT_HOLD_TIME_INFRA(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_P2PPS_STATE				(Offset 0x0543) */
+
+#define BIT_POWER_STATE BIT(7)
+#define BIT_CTWINDOW_ON BIT(6)
+#define BIT_BEACON_AREA_ON BIT(5)
+#define BIT_CTWIN_EARLY_DISTX BIT(4)
+#define BIT_NOA1_OFF_PERIOD BIT(3)
+#define BIT_FORCE_DOZE1 BIT(2)
+#define BIT_NOA0_OFF_PERIOD BIT(1)
+#define BIT_FORCE_DOZE0 BIT(0)
+
+/* 2 REG_RD_NAV_NXT				(Offset 0x0544) */
+
+#define BIT_SHIFT_RD_NAV_PROT_NXT 0
+#define BIT_MASK_RD_NAV_PROT_NXT 0xffff
+#define BIT_RD_NAV_PROT_NXT(x)                                                 \
+	(((x) & BIT_MASK_RD_NAV_PROT_NXT) << BIT_SHIFT_RD_NAV_PROT_NXT)
+#define BITS_RD_NAV_PROT_NXT                                                   \
+	(BIT_MASK_RD_NAV_PROT_NXT << BIT_SHIFT_RD_NAV_PROT_NXT)
+#define BIT_CLEAR_RD_NAV_PROT_NXT(x) ((x) & (~BITS_RD_NAV_PROT_NXT))
+#define BIT_GET_RD_NAV_PROT_NXT(x)                                             \
+	(((x) >> BIT_SHIFT_RD_NAV_PROT_NXT) & BIT_MASK_RD_NAV_PROT_NXT)
+#define BIT_SET_RD_NAV_PROT_NXT(x, v)                                          \
+	(BIT_CLEAR_RD_NAV_PROT_NXT(x) | BIT_RD_NAV_PROT_NXT(v))
+
+/* 2 REG_NAV_PROT_LEN			(Offset 0x0546) */
+
+#define BIT_SHIFT_NAV_PROT_LEN 0
+#define BIT_MASK_NAV_PROT_LEN 0xffff
+#define BIT_NAV_PROT_LEN(x)                                                    \
+	(((x) & BIT_MASK_NAV_PROT_LEN) << BIT_SHIFT_NAV_PROT_LEN)
+#define BITS_NAV_PROT_LEN (BIT_MASK_NAV_PROT_LEN << BIT_SHIFT_NAV_PROT_LEN)
+#define BIT_CLEAR_NAV_PROT_LEN(x) ((x) & (~BITS_NAV_PROT_LEN))
+#define BIT_GET_NAV_PROT_LEN(x)                                                \
+	(((x) >> BIT_SHIFT_NAV_PROT_LEN) & BIT_MASK_NAV_PROT_LEN)
+#define BIT_SET_NAV_PROT_LEN(x, v)                                             \
+	(BIT_CLEAR_NAV_PROT_LEN(x) | BIT_NAV_PROT_LEN(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_FTM_CTRL				(Offset 0x0548) */
+
+#define BIT_SHIFT_FTM_TSF_R2T_PORT 22
+#define BIT_MASK_FTM_TSF_R2T_PORT 0x7
+#define BIT_FTM_TSF_R2T_PORT(x)                                                \
+	(((x) & BIT_MASK_FTM_TSF_R2T_PORT) << BIT_SHIFT_FTM_TSF_R2T_PORT)
+#define BITS_FTM_TSF_R2T_PORT                                                  \
+	(BIT_MASK_FTM_TSF_R2T_PORT << BIT_SHIFT_FTM_TSF_R2T_PORT)
+#define BIT_CLEAR_FTM_TSF_R2T_PORT(x) ((x) & (~BITS_FTM_TSF_R2T_PORT))
+#define BIT_GET_FTM_TSF_R2T_PORT(x)                                            \
+	(((x) >> BIT_SHIFT_FTM_TSF_R2T_PORT) & BIT_MASK_FTM_TSF_R2T_PORT)
+#define BIT_SET_FTM_TSF_R2T_PORT(x, v)                                         \
+	(BIT_CLEAR_FTM_TSF_R2T_PORT(x) | BIT_FTM_TSF_R2T_PORT(v))
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FTM_PTT				(Offset 0x0548) */
+
+#define BIT_SHIFT_FTM_PTT_TSF_R2T_SEL 22
+#define BIT_MASK_FTM_PTT_TSF_R2T_SEL 0x7
+#define BIT_FTM_PTT_TSF_R2T_SEL(x)                                             \
+	(((x) & BIT_MASK_FTM_PTT_TSF_R2T_SEL) << BIT_SHIFT_FTM_PTT_TSF_R2T_SEL)
+#define BITS_FTM_PTT_TSF_R2T_SEL                                               \
+	(BIT_MASK_FTM_PTT_TSF_R2T_SEL << BIT_SHIFT_FTM_PTT_TSF_R2T_SEL)
+#define BIT_CLEAR_FTM_PTT_TSF_R2T_SEL(x) ((x) & (~BITS_FTM_PTT_TSF_R2T_SEL))
+#define BIT_GET_FTM_PTT_TSF_R2T_SEL(x)                                         \
+	(((x) >> BIT_SHIFT_FTM_PTT_TSF_R2T_SEL) & BIT_MASK_FTM_PTT_TSF_R2T_SEL)
+#define BIT_SET_FTM_PTT_TSF_R2T_SEL(x, v)                                      \
+	(BIT_CLEAR_FTM_PTT_TSF_R2T_SEL(x) | BIT_FTM_PTT_TSF_R2T_SEL(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_FTM_CTRL				(Offset 0x0548) */
+
+#define BIT_SHIFT_FTM_TSF_T2R_PORT 19
+#define BIT_MASK_FTM_TSF_T2R_PORT 0x7
+#define BIT_FTM_TSF_T2R_PORT(x)                                                \
+	(((x) & BIT_MASK_FTM_TSF_T2R_PORT) << BIT_SHIFT_FTM_TSF_T2R_PORT)
+#define BITS_FTM_TSF_T2R_PORT                                                  \
+	(BIT_MASK_FTM_TSF_T2R_PORT << BIT_SHIFT_FTM_TSF_T2R_PORT)
+#define BIT_CLEAR_FTM_TSF_T2R_PORT(x) ((x) & (~BITS_FTM_TSF_T2R_PORT))
+#define BIT_GET_FTM_TSF_T2R_PORT(x)                                            \
+	(((x) >> BIT_SHIFT_FTM_TSF_T2R_PORT) & BIT_MASK_FTM_TSF_T2R_PORT)
+#define BIT_SET_FTM_TSF_T2R_PORT(x, v)                                         \
+	(BIT_CLEAR_FTM_TSF_T2R_PORT(x) | BIT_FTM_TSF_T2R_PORT(v))
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FTM_PTT				(Offset 0x0548) */
+
+#define BIT_SHIFT_FTM_PTT_TSF_T2R_SEL 19
+#define BIT_MASK_FTM_PTT_TSF_T2R_SEL 0x7
+#define BIT_FTM_PTT_TSF_T2R_SEL(x)                                             \
+	(((x) & BIT_MASK_FTM_PTT_TSF_T2R_SEL) << BIT_SHIFT_FTM_PTT_TSF_T2R_SEL)
+#define BITS_FTM_PTT_TSF_T2R_SEL                                               \
+	(BIT_MASK_FTM_PTT_TSF_T2R_SEL << BIT_SHIFT_FTM_PTT_TSF_T2R_SEL)
+#define BIT_CLEAR_FTM_PTT_TSF_T2R_SEL(x) ((x) & (~BITS_FTM_PTT_TSF_T2R_SEL))
+#define BIT_GET_FTM_PTT_TSF_T2R_SEL(x)                                         \
+	(((x) >> BIT_SHIFT_FTM_PTT_TSF_T2R_SEL) & BIT_MASK_FTM_PTT_TSF_T2R_SEL)
+#define BIT_SET_FTM_PTT_TSF_T2R_SEL(x, v)                                      \
+	(BIT_CLEAR_FTM_PTT_TSF_T2R_SEL(x) | BIT_FTM_PTT_TSF_T2R_SEL(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_FTM_CTRL				(Offset 0x0548) */
+
+#define BIT_SHIFT_FTM_PTT_PORT 16
+#define BIT_MASK_FTM_PTT_PORT 0x7
+#define BIT_FTM_PTT_PORT(x)                                                    \
+	(((x) & BIT_MASK_FTM_PTT_PORT) << BIT_SHIFT_FTM_PTT_PORT)
+#define BITS_FTM_PTT_PORT (BIT_MASK_FTM_PTT_PORT << BIT_SHIFT_FTM_PTT_PORT)
+#define BIT_CLEAR_FTM_PTT_PORT(x) ((x) & (~BITS_FTM_PTT_PORT))
+#define BIT_GET_FTM_PTT_PORT(x)                                                \
+	(((x) >> BIT_SHIFT_FTM_PTT_PORT) & BIT_MASK_FTM_PTT_PORT)
+#define BIT_SET_FTM_PTT_PORT(x, v)                                             \
+	(BIT_CLEAR_FTM_PTT_PORT(x) | BIT_FTM_PTT_PORT(v))
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FTM_PTT				(Offset 0x0548) */
+
+#define BIT_SHIFT_FTM_PTT_TSF_SEL 16
+#define BIT_MASK_FTM_PTT_TSF_SEL 0x7
+#define BIT_FTM_PTT_TSF_SEL(x)                                                 \
+	(((x) & BIT_MASK_FTM_PTT_TSF_SEL) << BIT_SHIFT_FTM_PTT_TSF_SEL)
+#define BITS_FTM_PTT_TSF_SEL                                                   \
+	(BIT_MASK_FTM_PTT_TSF_SEL << BIT_SHIFT_FTM_PTT_TSF_SEL)
+#define BIT_CLEAR_FTM_PTT_TSF_SEL(x) ((x) & (~BITS_FTM_PTT_TSF_SEL))
+#define BIT_GET_FTM_PTT_TSF_SEL(x)                                             \
+	(((x) >> BIT_SHIFT_FTM_PTT_TSF_SEL) & BIT_MASK_FTM_PTT_TSF_SEL)
+#define BIT_SET_FTM_PTT_TSF_SEL(x, v)                                          \
+	(BIT_CLEAR_FTM_PTT_TSF_SEL(x) | BIT_FTM_PTT_TSF_SEL(v))
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_FTM_CTRL				(Offset 0x0548) */
+
+#define BIT_SHIFT_FTM_PTT 0
+#define BIT_MASK_FTM_PTT 0xffff
+#define BIT_FTM_PTT(x) (((x) & BIT_MASK_FTM_PTT) << BIT_SHIFT_FTM_PTT)
+#define BITS_FTM_PTT (BIT_MASK_FTM_PTT << BIT_SHIFT_FTM_PTT)
+#define BIT_CLEAR_FTM_PTT(x) ((x) & (~BITS_FTM_PTT))
+#define BIT_GET_FTM_PTT(x) (((x) >> BIT_SHIFT_FTM_PTT) & BIT_MASK_FTM_PTT)
+#define BIT_SET_FTM_PTT(x, v) (BIT_CLEAR_FTM_PTT(x) | BIT_FTM_PTT(v))
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FTM_PTT				(Offset 0x0548) */
+
+#define BIT_SHIFT_FTM_PTT_VALUE 0
+#define BIT_MASK_FTM_PTT_VALUE 0xffff
+#define BIT_FTM_PTT_VALUE(x)                                                   \
+	(((x) & BIT_MASK_FTM_PTT_VALUE) << BIT_SHIFT_FTM_PTT_VALUE)
+#define BITS_FTM_PTT_VALUE (BIT_MASK_FTM_PTT_VALUE << BIT_SHIFT_FTM_PTT_VALUE)
+#define BIT_CLEAR_FTM_PTT_VALUE(x) ((x) & (~BITS_FTM_PTT_VALUE))
+#define BIT_GET_FTM_PTT_VALUE(x)                                               \
+	(((x) >> BIT_SHIFT_FTM_PTT_VALUE) & BIT_MASK_FTM_PTT_VALUE)
+#define BIT_SET_FTM_PTT_VALUE(x, v)                                            \
+	(BIT_CLEAR_FTM_PTT_VALUE(x) | BIT_FTM_PTT_VALUE(v))
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_FTM_TSF_CNT				(Offset 0x054C) */
+
+#define BIT_SHIFT_FTM_TSF_R2T 16
+#define BIT_MASK_FTM_TSF_R2T 0xffff
+#define BIT_FTM_TSF_R2T(x)                                                     \
+	(((x) & BIT_MASK_FTM_TSF_R2T) << BIT_SHIFT_FTM_TSF_R2T)
+#define BITS_FTM_TSF_R2T (BIT_MASK_FTM_TSF_R2T << BIT_SHIFT_FTM_TSF_R2T)
+#define BIT_CLEAR_FTM_TSF_R2T(x) ((x) & (~BITS_FTM_TSF_R2T))
+#define BIT_GET_FTM_TSF_R2T(x)                                                 \
+	(((x) >> BIT_SHIFT_FTM_TSF_R2T) & BIT_MASK_FTM_TSF_R2T)
+#define BIT_SET_FTM_TSF_R2T(x, v)                                              \
+	(BIT_CLEAR_FTM_TSF_R2T(x) | BIT_FTM_TSF_R2T(v))
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FTM_TSF				(Offset 0x054C) */
+
+#define BIT_SHIFT_FTM_T2_TSF 16
+#define BIT_MASK_FTM_T2_TSF 0xffff
+#define BIT_FTM_T2_TSF(x) (((x) & BIT_MASK_FTM_T2_TSF) << BIT_SHIFT_FTM_T2_TSF)
+#define BITS_FTM_T2_TSF (BIT_MASK_FTM_T2_TSF << BIT_SHIFT_FTM_T2_TSF)
+#define BIT_CLEAR_FTM_T2_TSF(x) ((x) & (~BITS_FTM_T2_TSF))
+#define BIT_GET_FTM_T2_TSF(x)                                                  \
+	(((x) >> BIT_SHIFT_FTM_T2_TSF) & BIT_MASK_FTM_T2_TSF)
+#define BIT_SET_FTM_T2_TSF(x, v) (BIT_CLEAR_FTM_T2_TSF(x) | BIT_FTM_T2_TSF(v))
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_FTM_TSF_CNT				(Offset 0x054C) */
+
+#define BIT_SHIFT_FTM_TSF_T2R 0
+#define BIT_MASK_FTM_TSF_T2R 0xffff
+#define BIT_FTM_TSF_T2R(x)                                                     \
+	(((x) & BIT_MASK_FTM_TSF_T2R) << BIT_SHIFT_FTM_TSF_T2R)
+#define BITS_FTM_TSF_T2R (BIT_MASK_FTM_TSF_T2R << BIT_SHIFT_FTM_TSF_T2R)
+#define BIT_CLEAR_FTM_TSF_T2R(x) ((x) & (~BITS_FTM_TSF_T2R))
+#define BIT_GET_FTM_TSF_T2R(x)                                                 \
+	(((x) >> BIT_SHIFT_FTM_TSF_T2R) & BIT_MASK_FTM_TSF_T2R)
+#define BIT_SET_FTM_TSF_T2R(x, v)                                              \
+	(BIT_CLEAR_FTM_TSF_T2R(x) | BIT_FTM_TSF_T2R(v))
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FTM_TSF				(Offset 0x054C) */
+
+#define BIT_SHIFT_FTM_T1_TSF 0
+#define BIT_MASK_FTM_T1_TSF 0xffff
+#define BIT_FTM_T1_TSF(x) (((x) & BIT_MASK_FTM_T1_TSF) << BIT_SHIFT_FTM_T1_TSF)
+#define BITS_FTM_T1_TSF (BIT_MASK_FTM_T1_TSF << BIT_SHIFT_FTM_T1_TSF)
+#define BIT_CLEAR_FTM_T1_TSF(x) ((x) & (~BITS_FTM_T1_TSF))
+#define BIT_GET_FTM_T1_TSF(x)                                                  \
+	(((x) >> BIT_SHIFT_FTM_T1_TSF) & BIT_MASK_FTM_T1_TSF)
+#define BIT_SET_FTM_T1_TSF(x, v) (BIT_CLEAR_FTM_T1_TSF(x) | BIT_FTM_T1_TSF(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_BCN_CTRL				(Offset 0x0550) */
+
+#define BIT_P0_EN_TXBCN_RPT BIT(5)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_BCN_CTRL				(Offset 0x0550) */
+
+#define BIT_EN_BCN_FUNCTION BIT(3)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_BCN_CTRL				(Offset 0x0550) */
+
+#define BIT_EN_TXBCN_RPT BIT(2)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_BCN_CTRL				(Offset 0x0550) */
+
+#define BIT_P0_EN_RXBCN_RPT BIT(2)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_BCN_CTRL				(Offset 0x0550) */
+
+#define BIT_DIS_BCNQ_SUB BIT(1)
+
+/* 2 REG_BCN_CTRL1				(Offset 0x0551) */
+
+#define BIT_DIS_RX_BSSID_FIT1 BIT(6)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_BCN_CTRL_CLINT0			(Offset 0x0551) */
+
+#define BIT_CLI0_DIS_RX_BSSID_FIT BIT(6)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_BCN_CTRL1				(Offset 0x0551) */
+
+#define BIT_DIS_TSF1_UDT BIT(4)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_BCN_CTRL_CLINT0			(Offset 0x0551) */
+
+#define BIT_CLI0_DIS_TSF_UDT BIT(4)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_BCN_CTRL1				(Offset 0x0551) */
+
+#define BIT_EN_BCN1_FUNCTION BIT(3)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_BCN_CTRL_CLINT0			(Offset 0x0551) */
+
+#define BIT_CLI0_EN_BCN_FUNCTION BIT(3)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_BCN_CTRL1				(Offset 0x0551) */
+
+#define BIT_EN_TXBCN1_RPT BIT(2)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_BCN_CTRL_CLINT0			(Offset 0x0551) */
+
+#define BIT_CLI0_EN_RXBCN_RPT BIT(2)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_BCN_CTRL_CLINT0			(Offset 0x0551) */
+
+#define BIT_CLI0_EN_BCN_RPT BIT(2)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_BCN_CTRL1				(Offset 0x0551) */
+
+#define BIT_DIS_BCNQ1_SUB BIT(1)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_BCN_CTRL_CLINT0			(Offset 0x0551) */
+
+#define BIT_CLI0_ENP2P_CTWINDOW BIT(1)
+#define BIT_CLI0_ENP2P_BCNQ_AREA BIT(0)
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+/* 2 REG_MBID_NUM				(Offset 0x0552) */
+
+#define BIT_SHIFT_MBID_BCN_NUM_V2 4
+#define BIT_MASK_MBID_BCN_NUM_V2 0xf
+#define BIT_MBID_BCN_NUM_V2(x)                                                 \
+	(((x) & BIT_MASK_MBID_BCN_NUM_V2) << BIT_SHIFT_MBID_BCN_NUM_V2)
+#define BITS_MBID_BCN_NUM_V2                                                   \
+	(BIT_MASK_MBID_BCN_NUM_V2 << BIT_SHIFT_MBID_BCN_NUM_V2)
+#define BIT_CLEAR_MBID_BCN_NUM_V2(x) ((x) & (~BITS_MBID_BCN_NUM_V2))
+#define BIT_GET_MBID_BCN_NUM_V2(x)                                             \
+	(((x) >> BIT_SHIFT_MBID_BCN_NUM_V2) & BIT_MASK_MBID_BCN_NUM_V2)
+#define BIT_SET_MBID_BCN_NUM_V2(x, v)                                          \
+	(BIT_CLEAR_MBID_BCN_NUM_V2(x) | BIT_MBID_BCN_NUM_V2(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_MBID_NUM				(Offset 0x0552) */
+
+#define BIT_EN_PRE_DL_BEACON BIT(3)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8881A_SUPPORT)
+
+/* 2 REG_MBID_NUM				(Offset 0x0552) */
+
+#define BIT_SHIFT_MBID_BCN_NUM 0
+#define BIT_MASK_MBID_BCN_NUM 0x7
+#define BIT_MBID_BCN_NUM(x)                                                    \
+	(((x) & BIT_MASK_MBID_BCN_NUM) << BIT_SHIFT_MBID_BCN_NUM)
+#define BITS_MBID_BCN_NUM (BIT_MASK_MBID_BCN_NUM << BIT_SHIFT_MBID_BCN_NUM)
+#define BIT_CLEAR_MBID_BCN_NUM(x) ((x) & (~BITS_MBID_BCN_NUM))
+#define BIT_GET_MBID_BCN_NUM(x)                                                \
+	(((x) >> BIT_SHIFT_MBID_BCN_NUM) & BIT_MASK_MBID_BCN_NUM)
+#define BIT_SET_MBID_BCN_NUM(x, v)                                             \
+	(BIT_CLEAR_MBID_BCN_NUM(x) | BIT_MBID_BCN_NUM(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_DUAL_TSF_RST			(Offset 0x0553) */
+
+#define BIT_P2P_PWR_RST1 BIT(6)
+#define BIT_SCHEDULER_RST BIT(5)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_DUAL_TSF_RST			(Offset 0x0553) */
+
+#define BIT_FREECNT_RST BIT(5)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_DUAL_TSF_RST			(Offset 0x0553) */
+
+#define BIT_P2P_PWR_RST0 BIT(4)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_DUAL_TSF_RST			(Offset 0x0553) */
+
+#define BIT_TSFTR_CLI3_RST BIT(4)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_DUAL_TSF_RST			(Offset 0x0553) */
+
+#define BIT_TSFTR1_SYNC_EN BIT(3)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_DUAL_TSF_RST			(Offset 0x0553) */
+
+#define BIT_TSFTR_CLI2_RST BIT(3)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_DUAL_TSF_RST			(Offset 0x0553) */
+
+#define BIT_TSFTR_SYNC_EN BIT(2)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_DUAL_TSF_RST			(Offset 0x0553) */
+
+#define BIT_TSFTR_CLI1_RST BIT(2)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_DUAL_TSF_RST			(Offset 0x0553) */
+
+#define BIT_TSFTR1_RST BIT(1)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_DUAL_TSF_RST			(Offset 0x0553) */
+
+#define BIT_TSFTR_CLI0_RST BIT(1)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_DUAL_TSF_RST			(Offset 0x0553) */
+
+#define BIT_TSFTR_RST BIT(0)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_MBSSID_BCN_SPACE			(Offset 0x0554) */
+
+#define BIT_SHIFT_BCN_TIMER_SEL_FWRD 28
+#define BIT_MASK_BCN_TIMER_SEL_FWRD 0x7
+#define BIT_BCN_TIMER_SEL_FWRD(x)                                              \
+	(((x) & BIT_MASK_BCN_TIMER_SEL_FWRD) << BIT_SHIFT_BCN_TIMER_SEL_FWRD)
+#define BITS_BCN_TIMER_SEL_FWRD                                                \
+	(BIT_MASK_BCN_TIMER_SEL_FWRD << BIT_SHIFT_BCN_TIMER_SEL_FWRD)
+#define BIT_CLEAR_BCN_TIMER_SEL_FWRD(x) ((x) & (~BITS_BCN_TIMER_SEL_FWRD))
+#define BIT_GET_BCN_TIMER_SEL_FWRD(x)                                          \
+	(((x) >> BIT_SHIFT_BCN_TIMER_SEL_FWRD) & BIT_MASK_BCN_TIMER_SEL_FWRD)
+#define BIT_SET_BCN_TIMER_SEL_FWRD(x, v)                                       \
+	(BIT_CLEAR_BCN_TIMER_SEL_FWRD(x) | BIT_BCN_TIMER_SEL_FWRD(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_MBSSID_BCN_SPACE			(Offset 0x0554) */
+
+#define BIT_SHIFT_BCN_SPACE1 16
+#define BIT_MASK_BCN_SPACE1 0xffff
+#define BIT_BCN_SPACE1(x) (((x) & BIT_MASK_BCN_SPACE1) << BIT_SHIFT_BCN_SPACE1)
+#define BITS_BCN_SPACE1 (BIT_MASK_BCN_SPACE1 << BIT_SHIFT_BCN_SPACE1)
+#define BIT_CLEAR_BCN_SPACE1(x) ((x) & (~BITS_BCN_SPACE1))
+#define BIT_GET_BCN_SPACE1(x)                                                  \
+	(((x) >> BIT_SHIFT_BCN_SPACE1) & BIT_MASK_BCN_SPACE1)
+#define BIT_SET_BCN_SPACE1(x, v) (BIT_CLEAR_BCN_SPACE1(x) | BIT_BCN_SPACE1(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_MBSSID_BCN_SPACE			(Offset 0x0554) */
+
+#define BIT_SHIFT_BCN_SPACE_CLINT0 16
+#define BIT_MASK_BCN_SPACE_CLINT0 0xfff
+#define BIT_BCN_SPACE_CLINT0(x)                                                \
+	(((x) & BIT_MASK_BCN_SPACE_CLINT0) << BIT_SHIFT_BCN_SPACE_CLINT0)
+#define BITS_BCN_SPACE_CLINT0                                                  \
+	(BIT_MASK_BCN_SPACE_CLINT0 << BIT_SHIFT_BCN_SPACE_CLINT0)
+#define BIT_CLEAR_BCN_SPACE_CLINT0(x) ((x) & (~BITS_BCN_SPACE_CLINT0))
+#define BIT_GET_BCN_SPACE_CLINT0(x)                                            \
+	(((x) >> BIT_SHIFT_BCN_SPACE_CLINT0) & BIT_MASK_BCN_SPACE_CLINT0)
+#define BIT_SET_BCN_SPACE_CLINT0(x, v)                                         \
+	(BIT_CLEAR_BCN_SPACE_CLINT0(x) | BIT_BCN_SPACE_CLINT0(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_MBSSID_BCN_SPACE			(Offset 0x0554) */
+
+#define BIT_SHIFT_BCN_SPACE0 0
+#define BIT_MASK_BCN_SPACE0 0xffff
+#define BIT_BCN_SPACE0(x) (((x) & BIT_MASK_BCN_SPACE0) << BIT_SHIFT_BCN_SPACE0)
+#define BITS_BCN_SPACE0 (BIT_MASK_BCN_SPACE0 << BIT_SHIFT_BCN_SPACE0)
+#define BIT_CLEAR_BCN_SPACE0(x) ((x) & (~BITS_BCN_SPACE0))
+#define BIT_GET_BCN_SPACE0(x)                                                  \
+	(((x) >> BIT_SHIFT_BCN_SPACE0) & BIT_MASK_BCN_SPACE0)
+#define BIT_SET_BCN_SPACE0(x, v) (BIT_CLEAR_BCN_SPACE0(x) | BIT_BCN_SPACE0(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_ATIMWND				(Offset 0x055A) */
+
+#define BIT_SHIFT_ATIMWND 0
+#define BIT_MASK_ATIMWND 0xffff
+#define BIT_ATIMWND(x) (((x) & BIT_MASK_ATIMWND) << BIT_SHIFT_ATIMWND)
+#define BITS_ATIMWND (BIT_MASK_ATIMWND << BIT_SHIFT_ATIMWND)
+#define BIT_CLEAR_ATIMWND(x) ((x) & (~BITS_ATIMWND))
+#define BIT_GET_ATIMWND(x) (((x) >> BIT_SHIFT_ATIMWND) & BIT_MASK_ATIMWND)
+#define BIT_SET_ATIMWND(x, v) (BIT_CLEAR_ATIMWND(x) | BIT_ATIMWND(v))
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_ATIMWND				(Offset 0x055A) */
+
+#define BIT_SHIFT_ATIMWND0 0
+#define BIT_MASK_ATIMWND0 0xffff
+#define BIT_ATIMWND0(x) (((x) & BIT_MASK_ATIMWND0) << BIT_SHIFT_ATIMWND0)
+#define BITS_ATIMWND0 (BIT_MASK_ATIMWND0 << BIT_SHIFT_ATIMWND0)
+#define BIT_CLEAR_ATIMWND0(x) ((x) & (~BITS_ATIMWND0))
+#define BIT_GET_ATIMWND0(x) (((x) >> BIT_SHIFT_ATIMWND0) & BIT_MASK_ATIMWND0)
+#define BIT_SET_ATIMWND0(x, v) (BIT_CLEAR_ATIMWND0(x) | BIT_ATIMWND0(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_USTIME_TSF				(Offset 0x055C) */
+
+#define BIT_SHIFT_USTIME_TSF_V1 0
+#define BIT_MASK_USTIME_TSF_V1 0xff
+#define BIT_USTIME_TSF_V1(x)                                                   \
+	(((x) & BIT_MASK_USTIME_TSF_V1) << BIT_SHIFT_USTIME_TSF_V1)
+#define BITS_USTIME_TSF_V1 (BIT_MASK_USTIME_TSF_V1 << BIT_SHIFT_USTIME_TSF_V1)
+#define BIT_CLEAR_USTIME_TSF_V1(x) ((x) & (~BITS_USTIME_TSF_V1))
+#define BIT_GET_USTIME_TSF_V1(x)                                               \
+	(((x) >> BIT_SHIFT_USTIME_TSF_V1) & BIT_MASK_USTIME_TSF_V1)
+#define BIT_SET_USTIME_TSF_V1(x, v)                                            \
+	(BIT_CLEAR_USTIME_TSF_V1(x) | BIT_USTIME_TSF_V1(v))
+
+/* 2 REG_BCN_MAX_ERR				(Offset 0x055D) */
+
+#define BIT_SHIFT_BCN_MAX_ERR 0
+#define BIT_MASK_BCN_MAX_ERR 0xff
+#define BIT_BCN_MAX_ERR(x)                                                     \
+	(((x) & BIT_MASK_BCN_MAX_ERR) << BIT_SHIFT_BCN_MAX_ERR)
+#define BITS_BCN_MAX_ERR (BIT_MASK_BCN_MAX_ERR << BIT_SHIFT_BCN_MAX_ERR)
+#define BIT_CLEAR_BCN_MAX_ERR(x) ((x) & (~BITS_BCN_MAX_ERR))
+#define BIT_GET_BCN_MAX_ERR(x)                                                 \
+	(((x) >> BIT_SHIFT_BCN_MAX_ERR) & BIT_MASK_BCN_MAX_ERR)
+#define BIT_SET_BCN_MAX_ERR(x, v)                                              \
+	(BIT_CLEAR_BCN_MAX_ERR(x) | BIT_BCN_MAX_ERR(v))
+
+/* 2 REG_RXTSF_OFFSET_CCK			(Offset 0x055E) */
+
+#define BIT_SHIFT_CCK_RXTSF_OFFSET 0
+#define BIT_MASK_CCK_RXTSF_OFFSET 0xff
+#define BIT_CCK_RXTSF_OFFSET(x)                                                \
+	(((x) & BIT_MASK_CCK_RXTSF_OFFSET) << BIT_SHIFT_CCK_RXTSF_OFFSET)
+#define BITS_CCK_RXTSF_OFFSET                                                  \
+	(BIT_MASK_CCK_RXTSF_OFFSET << BIT_SHIFT_CCK_RXTSF_OFFSET)
+#define BIT_CLEAR_CCK_RXTSF_OFFSET(x) ((x) & (~BITS_CCK_RXTSF_OFFSET))
+#define BIT_GET_CCK_RXTSF_OFFSET(x)                                            \
+	(((x) >> BIT_SHIFT_CCK_RXTSF_OFFSET) & BIT_MASK_CCK_RXTSF_OFFSET)
+#define BIT_SET_CCK_RXTSF_OFFSET(x, v)                                         \
+	(BIT_CLEAR_CCK_RXTSF_OFFSET(x) | BIT_CCK_RXTSF_OFFSET(v))
+
+/* 2 REG_RXTSF_OFFSET_OFDM			(Offset 0x055F) */
+
+#define BIT_SHIFT_OFDM_RXTSF_OFFSET 0
+#define BIT_MASK_OFDM_RXTSF_OFFSET 0xff
+#define BIT_OFDM_RXTSF_OFFSET(x)                                               \
+	(((x) & BIT_MASK_OFDM_RXTSF_OFFSET) << BIT_SHIFT_OFDM_RXTSF_OFFSET)
+#define BITS_OFDM_RXTSF_OFFSET                                                 \
+	(BIT_MASK_OFDM_RXTSF_OFFSET << BIT_SHIFT_OFDM_RXTSF_OFFSET)
+#define BIT_CLEAR_OFDM_RXTSF_OFFSET(x) ((x) & (~BITS_OFDM_RXTSF_OFFSET))
+#define BIT_GET_OFDM_RXTSF_OFFSET(x)                                           \
+	(((x) >> BIT_SHIFT_OFDM_RXTSF_OFFSET) & BIT_MASK_OFDM_RXTSF_OFFSET)
+#define BIT_SET_OFDM_RXTSF_OFFSET(x, v)                                        \
+	(BIT_CLEAR_OFDM_RXTSF_OFFSET(x) | BIT_OFDM_RXTSF_OFFSET(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT || \
+     HALMAC_8881A_SUPPORT)
+
+/* 2 REG_TSFTR				(Offset 0x0560) */
+
+#define BIT_SHIFT_TSF_TIMER 0
+#define BIT_MASK_TSF_TIMER 0xffffffffffffffffL
+#define BIT_TSF_TIMER(x) (((x) & BIT_MASK_TSF_TIMER) << BIT_SHIFT_TSF_TIMER)
+#define BITS_TSF_TIMER (BIT_MASK_TSF_TIMER << BIT_SHIFT_TSF_TIMER)
+#define BIT_CLEAR_TSF_TIMER(x) ((x) & (~BITS_TSF_TIMER))
+#define BIT_GET_TSF_TIMER(x) (((x) >> BIT_SHIFT_TSF_TIMER) & BIT_MASK_TSF_TIMER)
+#define BIT_SET_TSF_TIMER(x, v) (BIT_CLEAR_TSF_TIMER(x) | BIT_TSF_TIMER(v))
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_TSFTR0_L				(Offset 0x0560) */
+
+#define BIT_SHIFT_TSF0_TIMER_L 0
+#define BIT_MASK_TSF0_TIMER_L 0xffffffffL
+#define BIT_TSF0_TIMER_L(x)                                                    \
+	(((x) & BIT_MASK_TSF0_TIMER_L) << BIT_SHIFT_TSF0_TIMER_L)
+#define BITS_TSF0_TIMER_L (BIT_MASK_TSF0_TIMER_L << BIT_SHIFT_TSF0_TIMER_L)
+#define BIT_CLEAR_TSF0_TIMER_L(x) ((x) & (~BITS_TSF0_TIMER_L))
+#define BIT_GET_TSF0_TIMER_L(x)                                                \
+	(((x) >> BIT_SHIFT_TSF0_TIMER_L) & BIT_MASK_TSF0_TIMER_L)
+#define BIT_SET_TSF0_TIMER_L(x, v)                                             \
+	(BIT_CLEAR_TSF0_TIMER_L(x) | BIT_TSF0_TIMER_L(v))
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_TSFTR				(Offset 0x0560) */
+
+#define BIT_SHIFT_TSF_TIMER_V1 0
+#define BIT_MASK_TSF_TIMER_V1 0xffffffffL
+#define BIT_TSF_TIMER_V1(x)                                                    \
+	(((x) & BIT_MASK_TSF_TIMER_V1) << BIT_SHIFT_TSF_TIMER_V1)
+#define BITS_TSF_TIMER_V1 (BIT_MASK_TSF_TIMER_V1 << BIT_SHIFT_TSF_TIMER_V1)
+#define BIT_CLEAR_TSF_TIMER_V1(x) ((x) & (~BITS_TSF_TIMER_V1))
+#define BIT_GET_TSF_TIMER_V1(x)                                                \
+	(((x) >> BIT_SHIFT_TSF_TIMER_V1) & BIT_MASK_TSF_TIMER_V1)
+#define BIT_SET_TSF_TIMER_V1(x, v)                                             \
+	(BIT_CLEAR_TSF_TIMER_V1(x) | BIT_TSF_TIMER_V1(v))
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_TSFTR0_H				(Offset 0x0564) */
+
+#define BIT_SHIFT_TSF0_TIMER_H 0
+#define BIT_MASK_TSF0_TIMER_H 0xffffffffL
+#define BIT_TSF0_TIMER_H(x)                                                    \
+	(((x) & BIT_MASK_TSF0_TIMER_H) << BIT_SHIFT_TSF0_TIMER_H)
+#define BITS_TSF0_TIMER_H (BIT_MASK_TSF0_TIMER_H << BIT_SHIFT_TSF0_TIMER_H)
+#define BIT_CLEAR_TSF0_TIMER_H(x) ((x) & (~BITS_TSF0_TIMER_H))
+#define BIT_GET_TSF0_TIMER_H(x)                                                \
+	(((x) >> BIT_SHIFT_TSF0_TIMER_H) & BIT_MASK_TSF0_TIMER_H)
+#define BIT_SET_TSF0_TIMER_H(x, v)                                             \
+	(BIT_CLEAR_TSF0_TIMER_H(x) | BIT_TSF0_TIMER_H(v))
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_TSFTR_1				(Offset 0x0564) */
+
+#define BIT_SHIFT_TSF_TIMER_V2 0
+#define BIT_MASK_TSF_TIMER_V2 0xffffffffL
+#define BIT_TSF_TIMER_V2(x)                                                    \
+	(((x) & BIT_MASK_TSF_TIMER_V2) << BIT_SHIFT_TSF_TIMER_V2)
+#define BITS_TSF_TIMER_V2 (BIT_MASK_TSF_TIMER_V2 << BIT_SHIFT_TSF_TIMER_V2)
+#define BIT_CLEAR_TSF_TIMER_V2(x) ((x) & (~BITS_TSF_TIMER_V2))
+#define BIT_GET_TSF_TIMER_V2(x)                                                \
+	(((x) >> BIT_SHIFT_TSF_TIMER_V2) & BIT_MASK_TSF_TIMER_V2)
+#define BIT_SET_TSF_TIMER_V2(x, v)                                             \
+	(BIT_CLEAR_TSF_TIMER_V2(x) | BIT_TSF_TIMER_V2(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_TSFTR1				(Offset 0x0568) */
+
+#define BIT_SHIFT_TSF_TIMER1 0
+#define BIT_MASK_TSF_TIMER1 0xffffffffffffffffL
+#define BIT_TSF_TIMER1(x) (((x) & BIT_MASK_TSF_TIMER1) << BIT_SHIFT_TSF_TIMER1)
+#define BITS_TSF_TIMER1 (BIT_MASK_TSF_TIMER1 << BIT_SHIFT_TSF_TIMER1)
+#define BIT_CLEAR_TSF_TIMER1(x) ((x) & (~BITS_TSF_TIMER1))
+#define BIT_GET_TSF_TIMER1(x)                                                  \
+	(((x) >> BIT_SHIFT_TSF_TIMER1) & BIT_MASK_TSF_TIMER1)
+#define BIT_SET_TSF_TIMER1(x, v) (BIT_CLEAR_TSF_TIMER1(x) | BIT_TSF_TIMER1(v))
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_TSFTR1_L				(Offset 0x0568) */
+
+#define BIT_SHIFT_TSF1_TIMER_L 0
+#define BIT_MASK_TSF1_TIMER_L 0xffffffffL
+#define BIT_TSF1_TIMER_L(x)                                                    \
+	(((x) & BIT_MASK_TSF1_TIMER_L) << BIT_SHIFT_TSF1_TIMER_L)
+#define BITS_TSF1_TIMER_L (BIT_MASK_TSF1_TIMER_L << BIT_SHIFT_TSF1_TIMER_L)
+#define BIT_CLEAR_TSF1_TIMER_L(x) ((x) & (~BITS_TSF1_TIMER_L))
+#define BIT_GET_TSF1_TIMER_L(x)                                                \
+	(((x) >> BIT_SHIFT_TSF1_TIMER_L) & BIT_MASK_TSF1_TIMER_L)
+#define BIT_SET_TSF1_TIMER_L(x, v)                                             \
+	(BIT_CLEAR_TSF1_TIMER_L(x) | BIT_TSF1_TIMER_L(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT)
+
+/* 2 REG_FREERUN_CNT				(Offset 0x0568) */
+
+#define BIT_SHIFT_FREERUN_CNT 0
+#define BIT_MASK_FREERUN_CNT 0xffffffffffffffffL
+#define BIT_FREERUN_CNT(x)                                                     \
+	(((x) & BIT_MASK_FREERUN_CNT) << BIT_SHIFT_FREERUN_CNT)
+#define BITS_FREERUN_CNT (BIT_MASK_FREERUN_CNT << BIT_SHIFT_FREERUN_CNT)
+#define BIT_CLEAR_FREERUN_CNT(x) ((x) & (~BITS_FREERUN_CNT))
+#define BIT_GET_FREERUN_CNT(x)                                                 \
+	(((x) >> BIT_SHIFT_FREERUN_CNT) & BIT_MASK_FREERUN_CNT)
+#define BIT_SET_FREERUN_CNT(x, v)                                              \
+	(BIT_CLEAR_FREERUN_CNT(x) | BIT_FREERUN_CNT(v))
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FREERUN_CNT				(Offset 0x0568) */
+
+#define BIT_SHIFT_FREERUN_CNT_V1 0
+#define BIT_MASK_FREERUN_CNT_V1 0xffffffffL
+#define BIT_FREERUN_CNT_V1(x)                                                  \
+	(((x) & BIT_MASK_FREERUN_CNT_V1) << BIT_SHIFT_FREERUN_CNT_V1)
+#define BITS_FREERUN_CNT_V1                                                    \
+	(BIT_MASK_FREERUN_CNT_V1 << BIT_SHIFT_FREERUN_CNT_V1)
+#define BIT_CLEAR_FREERUN_CNT_V1(x) ((x) & (~BITS_FREERUN_CNT_V1))
+#define BIT_GET_FREERUN_CNT_V1(x)                                              \
+	(((x) >> BIT_SHIFT_FREERUN_CNT_V1) & BIT_MASK_FREERUN_CNT_V1)
+#define BIT_SET_FREERUN_CNT_V1(x, v)                                           \
+	(BIT_CLEAR_FREERUN_CNT_V1(x) | BIT_FREERUN_CNT_V1(v))
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_TSFTR1_H				(Offset 0x056C) */
+
+#define BIT_SHIFT_TSF1_TIMER_H 0
+#define BIT_MASK_TSF1_TIMER_H 0xffffffffL
+#define BIT_TSF1_TIMER_H(x)                                                    \
+	(((x) & BIT_MASK_TSF1_TIMER_H) << BIT_SHIFT_TSF1_TIMER_H)
+#define BITS_TSF1_TIMER_H (BIT_MASK_TSF1_TIMER_H << BIT_SHIFT_TSF1_TIMER_H)
+#define BIT_CLEAR_TSF1_TIMER_H(x) ((x) & (~BITS_TSF1_TIMER_H))
+#define BIT_GET_TSF1_TIMER_H(x)                                                \
+	(((x) >> BIT_SHIFT_TSF1_TIMER_H) & BIT_MASK_TSF1_TIMER_H)
+#define BIT_SET_TSF1_TIMER_H(x, v)                                             \
+	(BIT_CLEAR_TSF1_TIMER_H(x) | BIT_TSF1_TIMER_H(v))
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FREERUN_CNT_1			(Offset 0x056C) */
+
+#define BIT_SHIFT_FREERUN_CNT_V2 0
+#define BIT_MASK_FREERUN_CNT_V2 0xffffffffL
+#define BIT_FREERUN_CNT_V2(x)                                                  \
+	(((x) & BIT_MASK_FREERUN_CNT_V2) << BIT_SHIFT_FREERUN_CNT_V2)
+#define BITS_FREERUN_CNT_V2                                                    \
+	(BIT_MASK_FREERUN_CNT_V2 << BIT_SHIFT_FREERUN_CNT_V2)
+#define BIT_CLEAR_FREERUN_CNT_V2(x) ((x) & (~BITS_FREERUN_CNT_V2))
+#define BIT_GET_FREERUN_CNT_V2(x)                                              \
+	(((x) >> BIT_SHIFT_FREERUN_CNT_V2) & BIT_MASK_FREERUN_CNT_V2)
+#define BIT_SET_FREERUN_CNT_V2(x, v)                                           \
+	(BIT_CLEAR_FREERUN_CNT_V2(x) | BIT_FREERUN_CNT_V2(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_ATIMWND1				(Offset 0x0570) */
+
+#define BIT_SHIFT_ATIMWND1 0
+#define BIT_MASK_ATIMWND1 0xffff
+#define BIT_ATIMWND1(x) (((x) & BIT_MASK_ATIMWND1) << BIT_SHIFT_ATIMWND1)
+#define BITS_ATIMWND1 (BIT_MASK_ATIMWND1 << BIT_SHIFT_ATIMWND1)
+#define BIT_CLEAR_ATIMWND1(x) ((x) & (~BITS_ATIMWND1))
+#define BIT_GET_ATIMWND1(x) (((x) >> BIT_SHIFT_ATIMWND1) & BIT_MASK_ATIMWND1)
+#define BIT_SET_ATIMWND1(x, v) (BIT_CLEAR_ATIMWND1(x) | BIT_ATIMWND1(v))
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_ATIMWND1_V1				(Offset 0x0570) */
+
+#define BIT_SHIFT_ATIMWND1_V2 0
+#define BIT_MASK_ATIMWND1_V2 0xffff
+#define BIT_ATIMWND1_V2(x)                                                     \
+	(((x) & BIT_MASK_ATIMWND1_V2) << BIT_SHIFT_ATIMWND1_V2)
+#define BITS_ATIMWND1_V2 (BIT_MASK_ATIMWND1_V2 << BIT_SHIFT_ATIMWND1_V2)
+#define BIT_CLEAR_ATIMWND1_V2(x) ((x) & (~BITS_ATIMWND1_V2))
+#define BIT_GET_ATIMWND1_V2(x)                                                 \
+	(((x) >> BIT_SHIFT_ATIMWND1_V2) & BIT_MASK_ATIMWND1_V2)
+#define BIT_SET_ATIMWND1_V2(x, v)                                              \
+	(BIT_CLEAR_ATIMWND1_V2(x) | BIT_ATIMWND1_V2(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_ATIMWND1_V1				(Offset 0x0570) */
+
+#define BIT_SHIFT_ATIMWND1_V1 0
+#define BIT_MASK_ATIMWND1_V1 0xff
+#define BIT_ATIMWND1_V1(x)                                                     \
+	(((x) & BIT_MASK_ATIMWND1_V1) << BIT_SHIFT_ATIMWND1_V1)
+#define BITS_ATIMWND1_V1 (BIT_MASK_ATIMWND1_V1 << BIT_SHIFT_ATIMWND1_V1)
+#define BIT_CLEAR_ATIMWND1_V1(x) ((x) & (~BITS_ATIMWND1_V1))
+#define BIT_GET_ATIMWND1_V1(x)                                                 \
+	(((x) >> BIT_SHIFT_ATIMWND1_V1) & BIT_MASK_ATIMWND1_V1)
+#define BIT_SET_ATIMWND1_V1(x, v)                                              \
+	(BIT_CLEAR_ATIMWND1_V1(x) | BIT_ATIMWND1_V1(v))
+
+/* 2 REG_TBTT_PROHIBIT_INFRA			(Offset 0x0571) */
+
+#define BIT_SHIFT_TBTT_PROHIBIT_INFRA 0
+#define BIT_MASK_TBTT_PROHIBIT_INFRA 0xff
+#define BIT_TBTT_PROHIBIT_INFRA(x)                                             \
+	(((x) & BIT_MASK_TBTT_PROHIBIT_INFRA) << BIT_SHIFT_TBTT_PROHIBIT_INFRA)
+#define BITS_TBTT_PROHIBIT_INFRA                                               \
+	(BIT_MASK_TBTT_PROHIBIT_INFRA << BIT_SHIFT_TBTT_PROHIBIT_INFRA)
+#define BIT_CLEAR_TBTT_PROHIBIT_INFRA(x) ((x) & (~BITS_TBTT_PROHIBIT_INFRA))
+#define BIT_GET_TBTT_PROHIBIT_INFRA(x)                                         \
+	(((x) >> BIT_SHIFT_TBTT_PROHIBIT_INFRA) & BIT_MASK_TBTT_PROHIBIT_INFRA)
+#define BIT_SET_TBTT_PROHIBIT_INFRA(x, v)                                      \
+	(BIT_CLEAR_TBTT_PROHIBIT_INFRA(x) | BIT_TBTT_PROHIBIT_INFRA(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_BCNIVLCUNT				(Offset 0x0573) */
+
+#define BIT_SHIFT_BCNIVLCUNT 0
+#define BIT_MASK_BCNIVLCUNT 0x7f
+#define BIT_BCNIVLCUNT(x) (((x) & BIT_MASK_BCNIVLCUNT) << BIT_SHIFT_BCNIVLCUNT)
+#define BITS_BCNIVLCUNT (BIT_MASK_BCNIVLCUNT << BIT_SHIFT_BCNIVLCUNT)
+#define BIT_CLEAR_BCNIVLCUNT(x) ((x) & (~BITS_BCNIVLCUNT))
+#define BIT_GET_BCNIVLCUNT(x)                                                  \
+	(((x) >> BIT_SHIFT_BCNIVLCUNT) & BIT_MASK_BCNIVLCUNT)
+#define BIT_SET_BCNIVLCUNT(x, v) (BIT_CLEAR_BCNIVLCUNT(x) | BIT_BCNIVLCUNT(v))
+
+/* 2 REG_BCNDROPCTRL				(Offset 0x0574) */
+
+#define BIT_BEACON_DROP_EN BIT(7)
+
+#define BIT_SHIFT_BEACON_DROP_IVL 0
+#define BIT_MASK_BEACON_DROP_IVL 0x7f
+#define BIT_BEACON_DROP_IVL(x)                                                 \
+	(((x) & BIT_MASK_BEACON_DROP_IVL) << BIT_SHIFT_BEACON_DROP_IVL)
+#define BITS_BEACON_DROP_IVL                                                   \
+	(BIT_MASK_BEACON_DROP_IVL << BIT_SHIFT_BEACON_DROP_IVL)
+#define BIT_CLEAR_BEACON_DROP_IVL(x) ((x) & (~BITS_BEACON_DROP_IVL))
+#define BIT_GET_BEACON_DROP_IVL(x)                                             \
+	(((x) >> BIT_SHIFT_BEACON_DROP_IVL) & BIT_MASK_BEACON_DROP_IVL)
+#define BIT_SET_BEACON_DROP_IVL(x, v)                                          \
+	(BIT_CLEAR_BEACON_DROP_IVL(x) | BIT_BEACON_DROP_IVL(v))
+
+/* 2 REG_HGQ_TIMEOUT_PERIOD			(Offset 0x0575) */
+
+#define BIT_SHIFT_HGQ_TIMEOUT_PERIOD 0
+#define BIT_MASK_HGQ_TIMEOUT_PERIOD 0xff
+#define BIT_HGQ_TIMEOUT_PERIOD(x)                                              \
+	(((x) & BIT_MASK_HGQ_TIMEOUT_PERIOD) << BIT_SHIFT_HGQ_TIMEOUT_PERIOD)
+#define BITS_HGQ_TIMEOUT_PERIOD                                                \
+	(BIT_MASK_HGQ_TIMEOUT_PERIOD << BIT_SHIFT_HGQ_TIMEOUT_PERIOD)
+#define BIT_CLEAR_HGQ_TIMEOUT_PERIOD(x) ((x) & (~BITS_HGQ_TIMEOUT_PERIOD))
+#define BIT_GET_HGQ_TIMEOUT_PERIOD(x)                                          \
+	(((x) >> BIT_SHIFT_HGQ_TIMEOUT_PERIOD) & BIT_MASK_HGQ_TIMEOUT_PERIOD)
+#define BIT_SET_HGQ_TIMEOUT_PERIOD(x, v)                                       \
+	(BIT_CLEAR_HGQ_TIMEOUT_PERIOD(x) | BIT_HGQ_TIMEOUT_PERIOD(v))
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_TXCMD_TIMEOUT_PERIOD		(Offset 0x0576) */
+
+#define BIT_SHIFT_TXCMD_TIMEOUT_PERIOD 0
+#define BIT_MASK_TXCMD_TIMEOUT_PERIOD 0xff
+#define BIT_TXCMD_TIMEOUT_PERIOD(x)                                            \
+	(((x) & BIT_MASK_TXCMD_TIMEOUT_PERIOD)                                 \
+	 << BIT_SHIFT_TXCMD_TIMEOUT_PERIOD)
+#define BITS_TXCMD_TIMEOUT_PERIOD                                              \
+	(BIT_MASK_TXCMD_TIMEOUT_PERIOD << BIT_SHIFT_TXCMD_TIMEOUT_PERIOD)
+#define BIT_CLEAR_TXCMD_TIMEOUT_PERIOD(x) ((x) & (~BITS_TXCMD_TIMEOUT_PERIOD))
+#define BIT_GET_TXCMD_TIMEOUT_PERIOD(x)                                        \
+	(((x) >> BIT_SHIFT_TXCMD_TIMEOUT_PERIOD) &                             \
+	 BIT_MASK_TXCMD_TIMEOUT_PERIOD)
+#define BIT_SET_TXCMD_TIMEOUT_PERIOD(x, v)                                     \
+	(BIT_CLEAR_TXCMD_TIMEOUT_PERIOD(x) | BIT_TXCMD_TIMEOUT_PERIOD(v))
+
+#define BIT_SHIFT_EARLY_128US 0
+#define BIT_MASK_EARLY_128US 0x7
+#define BIT_EARLY_128US(x)                                                     \
+	(((x) & BIT_MASK_EARLY_128US) << BIT_SHIFT_EARLY_128US)
+#define BITS_EARLY_128US (BIT_MASK_EARLY_128US << BIT_SHIFT_EARLY_128US)
+#define BIT_CLEAR_EARLY_128US(x) ((x) & (~BITS_EARLY_128US))
+#define BIT_GET_EARLY_128US(x)                                                 \
+	(((x) >> BIT_SHIFT_EARLY_128US) & BIT_MASK_EARLY_128US)
+#define BIT_SET_EARLY_128US(x, v)                                              \
+	(BIT_CLEAR_EARLY_128US(x) | BIT_EARLY_128US(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_MISC_CTRL				(Offset 0x0577) */
+
+#define BIT_DIS_MARK_TSF_US BIT(7)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_MISC_CTRL				(Offset 0x0577) */
+
+#define BIT_DIS_MARK_TSF_US_V2 BIT(7)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_MISC_CTRL				(Offset 0x0577) */
+
+#define BIT_EN_TSFAUTO_SYNC BIT(6)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_MISC_CTRL				(Offset 0x0577) */
+
+#define BIT_AUTO_SYNC_BY_TBTT BIT(6)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_MISC_CTRL				(Offset 0x0577) */
+
+#define BIT_DIS_TRX_CAL_BCN BIT(5)
+#define BIT_DIS_TX_CAL_TBTT BIT(4)
+#define BIT_EN_FREECNT BIT(3)
+#define BIT_BCN_AGGRESSION BIT(2)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_MISC_CTRL				(Offset 0x0577) */
+
+#define BIT_DIS_SECONDARY_CCA_80M BIT(2)
+#define BIT_DIS_SECONDARY_CCA_40M BIT(1)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_MISC_CTRL				(Offset 0x0577) */
+
+#define BIT_SHIFT_DIS_SECONDARY_CCA 0
+#define BIT_MASK_DIS_SECONDARY_CCA 0x3
+#define BIT_DIS_SECONDARY_CCA(x)                                               \
+	(((x) & BIT_MASK_DIS_SECONDARY_CCA) << BIT_SHIFT_DIS_SECONDARY_CCA)
+#define BITS_DIS_SECONDARY_CCA                                                 \
+	(BIT_MASK_DIS_SECONDARY_CCA << BIT_SHIFT_DIS_SECONDARY_CCA)
+#define BIT_CLEAR_DIS_SECONDARY_CCA(x) ((x) & (~BITS_DIS_SECONDARY_CCA))
+#define BIT_GET_DIS_SECONDARY_CCA(x)                                           \
+	(((x) >> BIT_SHIFT_DIS_SECONDARY_CCA) & BIT_MASK_DIS_SECONDARY_CCA)
+#define BIT_SET_DIS_SECONDARY_CCA(x, v)                                        \
+	(BIT_CLEAR_DIS_SECONDARY_CCA(x) | BIT_DIS_SECONDARY_CCA(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_MISC_CTRL				(Offset 0x0577) */
+
+#define BIT_DIS_SECONDARY_CCA_20M BIT(0)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_BCN_CTRL_CLINT1			(Offset 0x0578) */
+
+#define BIT_CLI1_DIS_RX_BSSID_FIT BIT(6)
+#define BIT_CLI1_DIS_TSF_UDT BIT(4)
+#define BIT_CLI1_EN_BCN_FUNCTION BIT(3)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_BCN_CTRL_CLINT1			(Offset 0x0578) */
+
+#define BIT_CLI1_EN_RXBCN_RPT BIT(2)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_BCN_CTRL_CLINT1			(Offset 0x0578) */
+
+#define BIT_CLI1_EN_BCN_RPT BIT(2)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_BCN_CTRL_CLINT1			(Offset 0x0578) */
+
+#define BIT_CLI1_ENP2P_CTWINDOW BIT(1)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_TSFTR2_L				(Offset 0x0578) */
+
+#define BIT_SHIFT_TSF2_TIMER_L 0
+#define BIT_MASK_TSF2_TIMER_L 0xffffffffL
+#define BIT_TSF2_TIMER_L(x)                                                    \
+	(((x) & BIT_MASK_TSF2_TIMER_L) << BIT_SHIFT_TSF2_TIMER_L)
+#define BITS_TSF2_TIMER_L (BIT_MASK_TSF2_TIMER_L << BIT_SHIFT_TSF2_TIMER_L)
+#define BIT_CLEAR_TSF2_TIMER_L(x) ((x) & (~BITS_TSF2_TIMER_L))
+#define BIT_GET_TSF2_TIMER_L(x)                                                \
+	(((x) >> BIT_SHIFT_TSF2_TIMER_L) & BIT_MASK_TSF2_TIMER_L)
+#define BIT_SET_TSF2_TIMER_L(x, v)                                             \
+	(BIT_CLEAR_TSF2_TIMER_L(x) | BIT_TSF2_TIMER_L(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_BCN_CTRL_CLINT1			(Offset 0x0578) */
+
+#define BIT_CLI1_ENP2P_BCNQ_AREA BIT(0)
+
+/* 2 REG_BCN_CTRL_CLINT2			(Offset 0x0579) */
+
+#define BIT_CLI2_DIS_RX_BSSID_FIT BIT(6)
+#define BIT_CLI2_DIS_TSF_UDT BIT(4)
+#define BIT_CLI2_EN_BCN_FUNCTION BIT(3)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_BCN_CTRL_CLINT2			(Offset 0x0579) */
+
+#define BIT_CLI2_EN_RXBCN_RPT BIT(2)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_BCN_CTRL_CLINT2			(Offset 0x0579) */
+
+#define BIT_CLI2_EN_BCN_RPT BIT(2)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_BCN_CTRL_CLINT2			(Offset 0x0579) */
+
+#define BIT_CLI2_ENP2P_CTWINDOW BIT(1)
+#define BIT_CLI2_ENP2P_BCNQ_AREA BIT(0)
+
+/* 2 REG_BCN_CTRL_CLINT3			(Offset 0x057A) */
+
+#define BIT_CLI3_DIS_RX_BSSID_FIT BIT(6)
+#define BIT_CLI3_DIS_TSF_UDT BIT(4)
+#define BIT_CLI3_EN_BCN_FUNCTION BIT(3)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_BCN_CTRL_CLINT3			(Offset 0x057A) */
+
+#define BIT_CLI3_EN_RXBCN_RPT BIT(2)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_BCN_CTRL_CLINT3			(Offset 0x057A) */
+
+#define BIT_CLI3_EN_BCN_RPT BIT(2)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_BCN_CTRL_CLINT3			(Offset 0x057A) */
+
+#define BIT_CLI3_ENP2P_CTWINDOW BIT(1)
+#define BIT_CLI3_ENP2P_BCNQ_AREA BIT(0)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_EXTEND_CTRL				(Offset 0x057B) */
+
+#define BIT_EN_TSFBIT32_RST_P2P2 BIT(5)
+#define BIT_EN_TSFBIT32_RST_P2P1 BIT(4)
+
+#define BIT_SHIFT_PORT_SEL 0
+#define BIT_MASK_PORT_SEL 0x7
+#define BIT_PORT_SEL(x) (((x) & BIT_MASK_PORT_SEL) << BIT_SHIFT_PORT_SEL)
+#define BITS_PORT_SEL (BIT_MASK_PORT_SEL << BIT_SHIFT_PORT_SEL)
+#define BIT_CLEAR_PORT_SEL(x) ((x) & (~BITS_PORT_SEL))
+#define BIT_GET_PORT_SEL(x) (((x) >> BIT_SHIFT_PORT_SEL) & BIT_MASK_PORT_SEL)
+#define BIT_SET_PORT_SEL(x, v) (BIT_CLEAR_PORT_SEL(x) | BIT_PORT_SEL(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_P2PPS1_SPEC_STATE			(Offset 0x057C) */
+
+#define BIT_P2P1_SPEC_POWER_STATE BIT(7)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_P2PPS1_SPEC_STATE			(Offset 0x057C) */
+
+#define BIT_P2P1_SPEC_CTWINDOW_ON BIT(6)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_P2PPS1_SPEC_STATE			(Offset 0x057C) */
+
+#define BIT_P2P1_SPEC_BCN_AREA_ON BIT(5)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_P2PPS1_SPEC_STATE			(Offset 0x057C) */
+
+#define BIT_P2P1_SPEC_CTWIN_EARLY_DISTX BIT(4)
+#define BIT_P2P1_SPEC_NOA1_OFF_PERIOD BIT(3)
+#define BIT_P2P1_SPEC_FORCE_DOZE1 BIT(2)
+#define BIT_P2P1_SPEC_NOA0_OFF_PERIOD BIT(1)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_TSFTR2_H				(Offset 0x057C) */
+
+#define BIT_SHIFT_TSF2_TIMER_H 0
+#define BIT_MASK_TSF2_TIMER_H 0xffffffffL
+#define BIT_TSF2_TIMER_H(x)                                                    \
+	(((x) & BIT_MASK_TSF2_TIMER_H) << BIT_SHIFT_TSF2_TIMER_H)
+#define BITS_TSF2_TIMER_H (BIT_MASK_TSF2_TIMER_H << BIT_SHIFT_TSF2_TIMER_H)
+#define BIT_CLEAR_TSF2_TIMER_H(x) ((x) & (~BITS_TSF2_TIMER_H))
+#define BIT_GET_TSF2_TIMER_H(x)                                                \
+	(((x) >> BIT_SHIFT_TSF2_TIMER_H) & BIT_MASK_TSF2_TIMER_H)
+#define BIT_SET_TSF2_TIMER_H(x, v)                                             \
+	(BIT_CLEAR_TSF2_TIMER_H(x) | BIT_TSF2_TIMER_H(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_P2PPS1_SPEC_STATE			(Offset 0x057C) */
+
+#define BIT_P2P1_SPEC_FORCE_DOZE0 BIT(0)
+
+/* 2 REG_P2PPS1_STATE			(Offset 0x057D) */
+
+#define BIT_P2P1_POWER_STATE BIT(7)
+#define BIT_P2P1_CTWINDOW_ON BIT(6)
+#define BIT_P2P1_BEACON_AREA_ON BIT(5)
+#define BIT_P2P1_CTWIN_EARLY_DISTX BIT(4)
+#define BIT_P2P1_NOA1_OFF_PERIOD BIT(3)
+#define BIT_P2P1_FORCE_DOZE1 BIT(2)
+#define BIT_P2P1_NOA0_OFF_PERIOD BIT(1)
+#define BIT_P2P1_FORCE_DOZE0 BIT(0)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_P2PPS2_SPEC_STATE			(Offset 0x057E) */
+
+#define BIT_P2P2_SPEC_POWER_STATE BIT(7)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_P2PPS2_SPEC_STATE			(Offset 0x057E) */
+
+#define BIT_P2P2_SPEC_CTWINDOW_ON BIT(6)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_P2PPS2_SPEC_STATE			(Offset 0x057E) */
+
+#define BIT_P2P2_SPEC_BCN_AREA_ON BIT(5)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_P2PPS2_SPEC_STATE			(Offset 0x057E) */
+
+#define BIT_P2P2_SPEC_CTWIN_EARLY_DISTX BIT(4)
+#define BIT_P2P2_SPEC_NOA1_OFF_PERIOD BIT(3)
+#define BIT_P2P2_SPEC_FORCE_DOZE1 BIT(2)
+#define BIT_P2P2_SPEC_NOA0_OFF_PERIOD BIT(1)
+#define BIT_P2P2_SPEC_FORCE_DOZE0 BIT(0)
+
+/* 2 REG_P2PPS2_STATE			(Offset 0x057F) */
+
+#define BIT_P2P2_POWER_STATE BIT(7)
+#define BIT_P2P2_CTWINDOW_ON BIT(6)
+#define BIT_P2P2_BEACON_AREA_ON BIT(5)
+#define BIT_P2P2_CTWIN_EARLY_DISTX BIT(4)
+#define BIT_P2P2_NOA1_OFF_PERIOD BIT(3)
+#define BIT_P2P2_FORCE_DOZE1 BIT(2)
+#define BIT_P2P2_NOA0_OFF_PERIOD BIT(1)
+#define BIT_P2P2_FORCE_DOZE0 BIT(0)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_PS_TIMER				(Offset 0x0580) */
+
+#define BIT_SHIFT_PSTIMER 5
+#define BIT_MASK_PSTIMER 0x7ffffff
+#define BIT_PSTIMER(x) (((x) & BIT_MASK_PSTIMER) << BIT_SHIFT_PSTIMER)
+#define BITS_PSTIMER (BIT_MASK_PSTIMER << BIT_SHIFT_PSTIMER)
+#define BIT_CLEAR_PSTIMER(x) ((x) & (~BITS_PSTIMER))
+#define BIT_GET_PSTIMER(x) (((x) >> BIT_SHIFT_PSTIMER) & BIT_MASK_PSTIMER)
+#define BIT_SET_PSTIMER(x, v) (BIT_CLEAR_PSTIMER(x) | BIT_PSTIMER(v))
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_PS_TIMER0				(Offset 0x0580) */
+
+#define BIT_SHIFT_PSTIMER0_INT 5
+#define BIT_MASK_PSTIMER0_INT 0x7ffffff
+#define BIT_PSTIMER0_INT(x)                                                    \
+	(((x) & BIT_MASK_PSTIMER0_INT) << BIT_SHIFT_PSTIMER0_INT)
+#define BITS_PSTIMER0_INT (BIT_MASK_PSTIMER0_INT << BIT_SHIFT_PSTIMER0_INT)
+#define BIT_CLEAR_PSTIMER0_INT(x) ((x) & (~BITS_PSTIMER0_INT))
+#define BIT_GET_PSTIMER0_INT(x)                                                \
+	(((x) >> BIT_SHIFT_PSTIMER0_INT) & BIT_MASK_PSTIMER0_INT)
+#define BIT_SET_PSTIMER0_INT(x, v)                                             \
+	(BIT_CLEAR_PSTIMER0_INT(x) | BIT_PSTIMER0_INT(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_TIMER0				(Offset 0x0584) */
+
+#define BIT_SHIFT_TIMER0_INT 5
+#define BIT_MASK_TIMER0_INT 0x7ffffff
+#define BIT_TIMER0_INT(x) (((x) & BIT_MASK_TIMER0_INT) << BIT_SHIFT_TIMER0_INT)
+#define BITS_TIMER0_INT (BIT_MASK_TIMER0_INT << BIT_SHIFT_TIMER0_INT)
+#define BIT_CLEAR_TIMER0_INT(x) ((x) & (~BITS_TIMER0_INT))
+#define BIT_GET_TIMER0_INT(x)                                                  \
+	(((x) >> BIT_SHIFT_TIMER0_INT) & BIT_MASK_TIMER0_INT)
+#define BIT_SET_TIMER0_INT(x, v) (BIT_CLEAR_TIMER0_INT(x) | BIT_TIMER0_INT(v))
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_PS_TIMER1				(Offset 0x0584) */
+
+#define BIT_SHIFT_PSTIMER1_INT 5
+#define BIT_MASK_PSTIMER1_INT 0x7ffffff
+#define BIT_PSTIMER1_INT(x)                                                    \
+	(((x) & BIT_MASK_PSTIMER1_INT) << BIT_SHIFT_PSTIMER1_INT)
+#define BITS_PSTIMER1_INT (BIT_MASK_PSTIMER1_INT << BIT_SHIFT_PSTIMER1_INT)
+#define BIT_CLEAR_PSTIMER1_INT(x) ((x) & (~BITS_PSTIMER1_INT))
+#define BIT_GET_PSTIMER1_INT(x)                                                \
+	(((x) >> BIT_SHIFT_PSTIMER1_INT) & BIT_MASK_PSTIMER1_INT)
+#define BIT_SET_PSTIMER1_INT(x, v)                                             \
+	(BIT_CLEAR_PSTIMER1_INT(x) | BIT_PSTIMER1_INT(v))
+
+/* 2 REG_PS_TIMER2				(Offset 0x0588) */
+
+#define BIT_SHIFT_INFO_INDEX_OFFSET 16
+#define BIT_MASK_INFO_INDEX_OFFSET 0x1fff
+#define BIT_INFO_INDEX_OFFSET(x)                                               \
+	(((x) & BIT_MASK_INFO_INDEX_OFFSET) << BIT_SHIFT_INFO_INDEX_OFFSET)
+#define BITS_INFO_INDEX_OFFSET                                                 \
+	(BIT_MASK_INFO_INDEX_OFFSET << BIT_SHIFT_INFO_INDEX_OFFSET)
+#define BIT_CLEAR_INFO_INDEX_OFFSET(x) ((x) & (~BITS_INFO_INDEX_OFFSET))
+#define BIT_GET_INFO_INDEX_OFFSET(x)                                           \
+	(((x) >> BIT_SHIFT_INFO_INDEX_OFFSET) & BIT_MASK_INFO_INDEX_OFFSET)
+#define BIT_SET_INFO_INDEX_OFFSET(x, v)                                        \
+	(BIT_CLEAR_INFO_INDEX_OFFSET(x) | BIT_INFO_INDEX_OFFSET(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_TIMER1				(Offset 0x0588) */
+
+#define BIT_SHIFT_TIMER1_INT 5
+#define BIT_MASK_TIMER1_INT 0x7ffffff
+#define BIT_TIMER1_INT(x) (((x) & BIT_MASK_TIMER1_INT) << BIT_SHIFT_TIMER1_INT)
+#define BITS_TIMER1_INT (BIT_MASK_TIMER1_INT << BIT_SHIFT_TIMER1_INT)
+#define BIT_CLEAR_TIMER1_INT(x) ((x) & (~BITS_TIMER1_INT))
+#define BIT_GET_TIMER1_INT(x)                                                  \
+	(((x) >> BIT_SHIFT_TIMER1_INT) & BIT_MASK_TIMER1_INT)
+#define BIT_SET_TIMER1_INT(x, v) (BIT_CLEAR_TIMER1_INT(x) | BIT_TIMER1_INT(v))
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_PS_TIMER2				(Offset 0x0588) */
+
+#define BIT_SHIFT_PSTIMER2_INT 5
+#define BIT_MASK_PSTIMER2_INT 0x7ffffff
+#define BIT_PSTIMER2_INT(x)                                                    \
+	(((x) & BIT_MASK_PSTIMER2_INT) << BIT_SHIFT_PSTIMER2_INT)
+#define BITS_PSTIMER2_INT (BIT_MASK_PSTIMER2_INT << BIT_SHIFT_PSTIMER2_INT)
+#define BIT_CLEAR_PSTIMER2_INT(x) ((x) & (~BITS_PSTIMER2_INT))
+#define BIT_GET_PSTIMER2_INT(x)                                                \
+	(((x) >> BIT_SHIFT_PSTIMER2_INT) & BIT_MASK_PSTIMER2_INT)
+#define BIT_SET_PSTIMER2_INT(x, v)                                             \
+	(BIT_CLEAR_PSTIMER2_INT(x) | BIT_PSTIMER2_INT(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_TBTT_CTN_AREA			(Offset 0x058C) */
+
+#define BIT_SHIFT_TBTT_CTN_AREA 0
+#define BIT_MASK_TBTT_CTN_AREA 0xff
+#define BIT_TBTT_CTN_AREA(x)                                                   \
+	(((x) & BIT_MASK_TBTT_CTN_AREA) << BIT_SHIFT_TBTT_CTN_AREA)
+#define BITS_TBTT_CTN_AREA (BIT_MASK_TBTT_CTN_AREA << BIT_SHIFT_TBTT_CTN_AREA)
+#define BIT_CLEAR_TBTT_CTN_AREA(x) ((x) & (~BITS_TBTT_CTN_AREA))
+#define BIT_GET_TBTT_CTN_AREA(x)                                               \
+	(((x) >> BIT_SHIFT_TBTT_CTN_AREA) & BIT_MASK_TBTT_CTN_AREA)
+#define BIT_SET_TBTT_CTN_AREA(x, v)                                            \
+	(BIT_CLEAR_TBTT_CTN_AREA(x) | BIT_TBTT_CTN_AREA(v))
+
+/* 2 REG_FORCE_BCN_IFS			(Offset 0x058E) */
+
+#define BIT_SHIFT_FORCE_BCN_IFS 0
+#define BIT_MASK_FORCE_BCN_IFS 0xff
+#define BIT_FORCE_BCN_IFS(x)                                                   \
+	(((x) & BIT_MASK_FORCE_BCN_IFS) << BIT_SHIFT_FORCE_BCN_IFS)
+#define BITS_FORCE_BCN_IFS (BIT_MASK_FORCE_BCN_IFS << BIT_SHIFT_FORCE_BCN_IFS)
+#define BIT_CLEAR_FORCE_BCN_IFS(x) ((x) & (~BITS_FORCE_BCN_IFS))
+#define BIT_GET_FORCE_BCN_IFS(x)                                               \
+	(((x) >> BIT_SHIFT_FORCE_BCN_IFS) & BIT_MASK_FORCE_BCN_IFS)
+#define BIT_SET_FORCE_BCN_IFS(x, v)                                            \
+	(BIT_CLEAR_FORCE_BCN_IFS(x) | BIT_FORCE_BCN_IFS(v))
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_DRVERLYINT_V1			(Offset 0x058F) */
+
+#define BIT_SHIFT_PRE_BCN_DMATIM 0
+#define BIT_MASK_PRE_BCN_DMATIM 0xff
+#define BIT_PRE_BCN_DMATIM(x)                                                  \
+	(((x) & BIT_MASK_PRE_BCN_DMATIM) << BIT_SHIFT_PRE_BCN_DMATIM)
+#define BITS_PRE_BCN_DMATIM                                                    \
+	(BIT_MASK_PRE_BCN_DMATIM << BIT_SHIFT_PRE_BCN_DMATIM)
+#define BIT_CLEAR_PRE_BCN_DMATIM(x) ((x) & (~BITS_PRE_BCN_DMATIM))
+#define BIT_GET_PRE_BCN_DMATIM(x)                                              \
+	(((x) >> BIT_SHIFT_PRE_BCN_DMATIM) & BIT_MASK_PRE_BCN_DMATIM)
+#define BIT_SET_PRE_BCN_DMATIM(x, v)                                           \
+	(BIT_CLEAR_PRE_BCN_DMATIM(x) | BIT_PRE_BCN_DMATIM(v))
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_TXOP_MIN				(Offset 0x0590) */
+
+#define BIT_NAV_BLK_HGQ BIT(15)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_TXOP_MIN				(Offset 0x0590) */
+
+#define BIT_HIQ_NAV_BREAK_EN BIT(15)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_TXOP_MIN				(Offset 0x0590) */
+
+#define BIT_NAV_BLK_MGQ BIT(14)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_TXOP_MIN				(Offset 0x0590) */
+
+#define BIT_MGQ_NAV_BREAK_EN BIT(14)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_TXOP_MIN				(Offset 0x0590) */
+
+#define BIT_SHIFT_TXOP_MIN 0
+#define BIT_MASK_TXOP_MIN 0x3fff
+#define BIT_TXOP_MIN(x) (((x) & BIT_MASK_TXOP_MIN) << BIT_SHIFT_TXOP_MIN)
+#define BITS_TXOP_MIN (BIT_MASK_TXOP_MIN << BIT_SHIFT_TXOP_MIN)
+#define BIT_CLEAR_TXOP_MIN(x) ((x) & (~BITS_TXOP_MIN))
+#define BIT_GET_TXOP_MIN(x) (((x) >> BIT_SHIFT_TXOP_MIN) & BIT_MASK_TXOP_MIN)
+#define BIT_SET_TXOP_MIN(x, v) (BIT_CLEAR_TXOP_MIN(x) | BIT_TXOP_MIN(v))
+
+/* 2 REG_PRE_BKF_TIME			(Offset 0x0592) */
+
+#define BIT_SHIFT_PRE_BKF_TIME 0
+#define BIT_MASK_PRE_BKF_TIME 0xff
+#define BIT_PRE_BKF_TIME(x)                                                    \
+	(((x) & BIT_MASK_PRE_BKF_TIME) << BIT_SHIFT_PRE_BKF_TIME)
+#define BITS_PRE_BKF_TIME (BIT_MASK_PRE_BKF_TIME << BIT_SHIFT_PRE_BKF_TIME)
+#define BIT_CLEAR_PRE_BKF_TIME(x) ((x) & (~BITS_PRE_BKF_TIME))
+#define BIT_GET_PRE_BKF_TIME(x)                                                \
+	(((x) >> BIT_SHIFT_PRE_BKF_TIME) & BIT_MASK_PRE_BKF_TIME)
+#define BIT_SET_PRE_BKF_TIME(x, v)                                             \
+	(BIT_CLEAR_PRE_BKF_TIME(x) | BIT_PRE_BKF_TIME(v))
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_CROSS_TXOP_CTRL			(Offset 0x0593) */
+
+#define BIT_NOPKT_END_RTSMF BIT(7)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_CROSS_TXOP_CTRL			(Offset 0x0593) */
+
+#define BIT_TBTT_RETRY BIT(4)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_CROSS_TXOP_CTRL			(Offset 0x0593) */
+
+#define BIT_SHIFT_PRETX_US 3
+#define BIT_MASK_PRETX_US 0xf
+#define BIT_PRETX_US(x) (((x) & BIT_MASK_PRETX_US) << BIT_SHIFT_PRETX_US)
+#define BITS_PRETX_US (BIT_MASK_PRETX_US << BIT_SHIFT_PRETX_US)
+#define BIT_CLEAR_PRETX_US(x) ((x) & (~BITS_PRETX_US))
+#define BIT_GET_PRETX_US(x) (((x) >> BIT_SHIFT_PRETX_US) & BIT_MASK_PRETX_US)
+#define BIT_SET_PRETX_US(x, v) (BIT_CLEAR_PRETX_US(x) | BIT_PRETX_US(v))
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+/* 2 REG_CROSS_TXOP_CTRL			(Offset 0x0593) */
+
+#define BIT_TXOP_FAIL_BREAK BIT(3)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_CROSS_TXOP_CTRL			(Offset 0x0593) */
+
+#define BIT_TXFAIL_BREACK_TXOP_EN BIT(3)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_CROSS_TXOP_CTRL			(Offset 0x0593) */
+
+#define BIT_DTIM_BYPASS BIT(2)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_CROSS_TXOP_CTRL			(Offset 0x0593) */
+
+#define BIT_RTS_NAV_TXOP BIT(1)
+#define BIT_NOT_CROSS_TXOP BIT(0)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_TBTT_INT_SHIFT_CLI0			(Offset 0x0594) */
+
+#define BIT_TBTT_INT_SHIFT_DIR_CLI0 BIT(7)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_FREERUN_CNT_L			(Offset 0x0594) */
+
+#define BIT_SHIFT_FREERUN_CNT_L 0
+#define BIT_MASK_FREERUN_CNT_L 0xffffffffL
+#define BIT_FREERUN_CNT_L(x)                                                   \
+	(((x) & BIT_MASK_FREERUN_CNT_L) << BIT_SHIFT_FREERUN_CNT_L)
+#define BITS_FREERUN_CNT_L (BIT_MASK_FREERUN_CNT_L << BIT_SHIFT_FREERUN_CNT_L)
+#define BIT_CLEAR_FREERUN_CNT_L(x) ((x) & (~BITS_FREERUN_CNT_L))
+#define BIT_GET_FREERUN_CNT_L(x)                                               \
+	(((x) >> BIT_SHIFT_FREERUN_CNT_L) & BIT_MASK_FREERUN_CNT_L)
+#define BIT_SET_FREERUN_CNT_L(x, v)                                            \
+	(BIT_CLEAR_FREERUN_CNT_L(x) | BIT_FREERUN_CNT_L(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_TBTT_INT_SHIFT_CLI0			(Offset 0x0594) */
+
+#define BIT_SHIFT_TBTT_INT_SHIFT_CLI0 0
+#define BIT_MASK_TBTT_INT_SHIFT_CLI0 0x7f
+#define BIT_TBTT_INT_SHIFT_CLI0(x)                                             \
+	(((x) & BIT_MASK_TBTT_INT_SHIFT_CLI0) << BIT_SHIFT_TBTT_INT_SHIFT_CLI0)
+#define BITS_TBTT_INT_SHIFT_CLI0                                               \
+	(BIT_MASK_TBTT_INT_SHIFT_CLI0 << BIT_SHIFT_TBTT_INT_SHIFT_CLI0)
+#define BIT_CLEAR_TBTT_INT_SHIFT_CLI0(x) ((x) & (~BITS_TBTT_INT_SHIFT_CLI0))
+#define BIT_GET_TBTT_INT_SHIFT_CLI0(x)                                         \
+	(((x) >> BIT_SHIFT_TBTT_INT_SHIFT_CLI0) & BIT_MASK_TBTT_INT_SHIFT_CLI0)
+#define BIT_SET_TBTT_INT_SHIFT_CLI0(x, v)                                      \
+	(BIT_CLEAR_TBTT_INT_SHIFT_CLI0(x) | BIT_TBTT_INT_SHIFT_CLI0(v))
+
+/* 2 REG_TBTT_INT_SHIFT_CLI1			(Offset 0x0595) */
+
+#define BIT_TBTT_INT_SHIFT_DIR_CLI1 BIT(7)
+
+#define BIT_SHIFT_TBTT_INT_SHIFT_CLI1 0
+#define BIT_MASK_TBTT_INT_SHIFT_CLI1 0x7f
+#define BIT_TBTT_INT_SHIFT_CLI1(x)                                             \
+	(((x) & BIT_MASK_TBTT_INT_SHIFT_CLI1) << BIT_SHIFT_TBTT_INT_SHIFT_CLI1)
+#define BITS_TBTT_INT_SHIFT_CLI1                                               \
+	(BIT_MASK_TBTT_INT_SHIFT_CLI1 << BIT_SHIFT_TBTT_INT_SHIFT_CLI1)
+#define BIT_CLEAR_TBTT_INT_SHIFT_CLI1(x) ((x) & (~BITS_TBTT_INT_SHIFT_CLI1))
+#define BIT_GET_TBTT_INT_SHIFT_CLI1(x)                                         \
+	(((x) >> BIT_SHIFT_TBTT_INT_SHIFT_CLI1) & BIT_MASK_TBTT_INT_SHIFT_CLI1)
+#define BIT_SET_TBTT_INT_SHIFT_CLI1(x, v)                                      \
+	(BIT_CLEAR_TBTT_INT_SHIFT_CLI1(x) | BIT_TBTT_INT_SHIFT_CLI1(v))
+
+/* 2 REG_TBTT_INT_SHIFT_CLI2			(Offset 0x0596) */
+
+#define BIT_TBTT_INT_SHIFT_DIR_CLI2 BIT(7)
+
+#define BIT_SHIFT_TBTT_INT_SHIFT_CLI2 0
+#define BIT_MASK_TBTT_INT_SHIFT_CLI2 0x7f
+#define BIT_TBTT_INT_SHIFT_CLI2(x)                                             \
+	(((x) & BIT_MASK_TBTT_INT_SHIFT_CLI2) << BIT_SHIFT_TBTT_INT_SHIFT_CLI2)
+#define BITS_TBTT_INT_SHIFT_CLI2                                               \
+	(BIT_MASK_TBTT_INT_SHIFT_CLI2 << BIT_SHIFT_TBTT_INT_SHIFT_CLI2)
+#define BIT_CLEAR_TBTT_INT_SHIFT_CLI2(x) ((x) & (~BITS_TBTT_INT_SHIFT_CLI2))
+#define BIT_GET_TBTT_INT_SHIFT_CLI2(x)                                         \
+	(((x) >> BIT_SHIFT_TBTT_INT_SHIFT_CLI2) & BIT_MASK_TBTT_INT_SHIFT_CLI2)
+#define BIT_SET_TBTT_INT_SHIFT_CLI2(x, v)                                      \
+	(BIT_CLEAR_TBTT_INT_SHIFT_CLI2(x) | BIT_TBTT_INT_SHIFT_CLI2(v))
+
+/* 2 REG_TBTT_INT_SHIFT_CLI3			(Offset 0x0597) */
+
+#define BIT_TBTT_INT_SHIFT_DIR_CLI3 BIT(7)
+
+#define BIT_SHIFT_TBTT_INT_SHIFT_CLI3 0
+#define BIT_MASK_TBTT_INT_SHIFT_CLI3 0x7f
+#define BIT_TBTT_INT_SHIFT_CLI3(x)                                             \
+	(((x) & BIT_MASK_TBTT_INT_SHIFT_CLI3) << BIT_SHIFT_TBTT_INT_SHIFT_CLI3)
+#define BITS_TBTT_INT_SHIFT_CLI3                                               \
+	(BIT_MASK_TBTT_INT_SHIFT_CLI3 << BIT_SHIFT_TBTT_INT_SHIFT_CLI3)
+#define BIT_CLEAR_TBTT_INT_SHIFT_CLI3(x) ((x) & (~BITS_TBTT_INT_SHIFT_CLI3))
+#define BIT_GET_TBTT_INT_SHIFT_CLI3(x)                                         \
+	(((x) >> BIT_SHIFT_TBTT_INT_SHIFT_CLI3) & BIT_MASK_TBTT_INT_SHIFT_CLI3)
+#define BIT_SET_TBTT_INT_SHIFT_CLI3(x, v)                                      \
+	(BIT_CLEAR_TBTT_INT_SHIFT_CLI3(x) | BIT_TBTT_INT_SHIFT_CLI3(v))
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_RX_TBTT_SHIFT_V1			(Offset 0x0598) */
+
+#define BIT_RX_TBTT_SHIFT_RW_FLAG_V1 BIT(31)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_TBTT_INT_SHIFT_ENABLE		(Offset 0x0598) */
+
+#define BIT_BCNERR_CNT_EN BIT(20)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_RX_TBTT_SHIFT_V1			(Offset 0x0598) */
+
+#define BIT_SHIFT_RX_TBTT_SHIFT_OFFSET_V1 16
+#define BIT_MASK_RX_TBTT_SHIFT_OFFSET_V1 0xfff
+#define BIT_RX_TBTT_SHIFT_OFFSET_V1(x)                                         \
+	(((x) & BIT_MASK_RX_TBTT_SHIFT_OFFSET_V1)                              \
+	 << BIT_SHIFT_RX_TBTT_SHIFT_OFFSET_V1)
+#define BITS_RX_TBTT_SHIFT_OFFSET_V1                                           \
+	(BIT_MASK_RX_TBTT_SHIFT_OFFSET_V1 << BIT_SHIFT_RX_TBTT_SHIFT_OFFSET_V1)
+#define BIT_CLEAR_RX_TBTT_SHIFT_OFFSET_V1(x)                                   \
+	((x) & (~BITS_RX_TBTT_SHIFT_OFFSET_V1))
+#define BIT_GET_RX_TBTT_SHIFT_OFFSET_V1(x)                                     \
+	(((x) >> BIT_SHIFT_RX_TBTT_SHIFT_OFFSET_V1) &                          \
+	 BIT_MASK_RX_TBTT_SHIFT_OFFSET_V1)
+#define BIT_SET_RX_TBTT_SHIFT_OFFSET_V1(x, v)                                  \
+	(BIT_CLEAR_RX_TBTT_SHIFT_OFFSET_V1(x) | BIT_RX_TBTT_SHIFT_OFFSET_V1(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_TBTT_INT_SHIFT_ENABLE		(Offset 0x0598) */
+
+#define BIT_CHANGE_POW_BCN_AREA BIT(9)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_RX_TBTT_SHIFT_V1			(Offset 0x0598) */
+
+#define BIT_SHIFT_RX_TBTT_SHIFT_SEL_V1 8
+#define BIT_MASK_RX_TBTT_SHIFT_SEL_V1 0x7
+#define BIT_RX_TBTT_SHIFT_SEL_V1(x)                                            \
+	(((x) & BIT_MASK_RX_TBTT_SHIFT_SEL_V1)                                 \
+	 << BIT_SHIFT_RX_TBTT_SHIFT_SEL_V1)
+#define BITS_RX_TBTT_SHIFT_SEL_V1                                              \
+	(BIT_MASK_RX_TBTT_SHIFT_SEL_V1 << BIT_SHIFT_RX_TBTT_SHIFT_SEL_V1)
+#define BIT_CLEAR_RX_TBTT_SHIFT_SEL_V1(x) ((x) & (~BITS_RX_TBTT_SHIFT_SEL_V1))
+#define BIT_GET_RX_TBTT_SHIFT_SEL_V1(x)                                        \
+	(((x) >> BIT_SHIFT_RX_TBTT_SHIFT_SEL_V1) &                             \
+	 BIT_MASK_RX_TBTT_SHIFT_SEL_V1)
+#define BIT_SET_RX_TBTT_SHIFT_SEL_V1(x, v)                                     \
+	(BIT_CLEAR_RX_TBTT_SHIFT_SEL_V1(x) | BIT_RX_TBTT_SHIFT_SEL_V1(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_TBTT_INT_SHIFT_ENABLE		(Offset 0x0598) */
+
+#define BIT_EN_TBTT_RTY BIT(1)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_FREERUN_CNT_H			(Offset 0x0598) */
+
+#define BIT_SHIFT_FREERUN_CNT_H 0
+#define BIT_MASK_FREERUN_CNT_H 0xffffffffL
+#define BIT_FREERUN_CNT_H(x)                                                   \
+	(((x) & BIT_MASK_FREERUN_CNT_H) << BIT_SHIFT_FREERUN_CNT_H)
+#define BITS_FREERUN_CNT_H (BIT_MASK_FREERUN_CNT_H << BIT_SHIFT_FREERUN_CNT_H)
+#define BIT_CLEAR_FREERUN_CNT_H(x) ((x) & (~BITS_FREERUN_CNT_H))
+#define BIT_GET_FREERUN_CNT_H(x)                                               \
+	(((x) >> BIT_SHIFT_FREERUN_CNT_H) & BIT_MASK_FREERUN_CNT_H)
+#define BIT_SET_FREERUN_CNT_H(x, v)                                            \
+	(BIT_CLEAR_FREERUN_CNT_H(x) | BIT_FREERUN_CNT_H(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_TBTT_INT_SHIFT_ENABLE		(Offset 0x0598) */
+
+#define BIT_TBTT_INT_SHIFT_ENABLE BIT(0)
+
+#define BIT_SHIFT_BCN_ELY_ADJ 0
+#define BIT_MASK_BCN_ELY_ADJ 0xffff
+#define BIT_BCN_ELY_ADJ(x)                                                     \
+	(((x) & BIT_MASK_BCN_ELY_ADJ) << BIT_SHIFT_BCN_ELY_ADJ)
+#define BITS_BCN_ELY_ADJ (BIT_MASK_BCN_ELY_ADJ << BIT_SHIFT_BCN_ELY_ADJ)
+#define BIT_CLEAR_BCN_ELY_ADJ(x) ((x) & (~BITS_BCN_ELY_ADJ))
+#define BIT_GET_BCN_ELY_ADJ(x)                                                 \
+	(((x) >> BIT_SHIFT_BCN_ELY_ADJ) & BIT_MASK_BCN_ELY_ADJ)
+#define BIT_SET_BCN_ELY_ADJ(x, v)                                              \
+	(BIT_CLEAR_BCN_ELY_ADJ(x) | BIT_BCN_ELY_ADJ(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8881A_SUPPORT)
+
+/* 2 REG_ATIMWND2				(Offset 0x05A0) */
+
+#define BIT_SHIFT_ATIMWND2 0
+#define BIT_MASK_ATIMWND2 0xff
+#define BIT_ATIMWND2(x) (((x) & BIT_MASK_ATIMWND2) << BIT_SHIFT_ATIMWND2)
+#define BITS_ATIMWND2 (BIT_MASK_ATIMWND2 << BIT_SHIFT_ATIMWND2)
+#define BIT_CLEAR_ATIMWND2(x) ((x) & (~BITS_ATIMWND2))
+#define BIT_GET_ATIMWND2(x) (((x) >> BIT_SHIFT_ATIMWND2) & BIT_MASK_ATIMWND2)
+#define BIT_SET_ATIMWND2(x, v) (BIT_CLEAR_ATIMWND2(x) | BIT_ATIMWND2(v))
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+/* 2 REG_ATIMWND_GROUP1			(Offset 0x05A0) */
+
+#define BIT_SHIFT_ATIMWND_GROUP1 0
+#define BIT_MASK_ATIMWND_GROUP1 0xff
+#define BIT_ATIMWND_GROUP1(x)                                                  \
+	(((x) & BIT_MASK_ATIMWND_GROUP1) << BIT_SHIFT_ATIMWND_GROUP1)
+#define BITS_ATIMWND_GROUP1                                                    \
+	(BIT_MASK_ATIMWND_GROUP1 << BIT_SHIFT_ATIMWND_GROUP1)
+#define BIT_CLEAR_ATIMWND_GROUP1(x) ((x) & (~BITS_ATIMWND_GROUP1))
+#define BIT_GET_ATIMWND_GROUP1(x)                                              \
+	(((x) >> BIT_SHIFT_ATIMWND_GROUP1) & BIT_MASK_ATIMWND_GROUP1)
+#define BIT_SET_ATIMWND_GROUP1(x, v)                                           \
+	(BIT_CLEAR_ATIMWND_GROUP1(x) | BIT_ATIMWND_GROUP1(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8881A_SUPPORT)
+
+/* 2 REG_ATIMWND3				(Offset 0x05A1) */
+
+#define BIT_SHIFT_ATIMWND3 0
+#define BIT_MASK_ATIMWND3 0xff
+#define BIT_ATIMWND3(x) (((x) & BIT_MASK_ATIMWND3) << BIT_SHIFT_ATIMWND3)
+#define BITS_ATIMWND3 (BIT_MASK_ATIMWND3 << BIT_SHIFT_ATIMWND3)
+#define BIT_CLEAR_ATIMWND3(x) ((x) & (~BITS_ATIMWND3))
+#define BIT_GET_ATIMWND3(x) (((x) >> BIT_SHIFT_ATIMWND3) & BIT_MASK_ATIMWND3)
+#define BIT_SET_ATIMWND3(x, v) (BIT_CLEAR_ATIMWND3(x) | BIT_ATIMWND3(v))
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+/* 2 REG_ATIMWND_GROUP2			(Offset 0x05A1) */
+
+#define BIT_SHIFT_ATIMWND_GROUP2 0
+#define BIT_MASK_ATIMWND_GROUP2 0xff
+#define BIT_ATIMWND_GROUP2(x)                                                  \
+	(((x) & BIT_MASK_ATIMWND_GROUP2) << BIT_SHIFT_ATIMWND_GROUP2)
+#define BITS_ATIMWND_GROUP2                                                    \
+	(BIT_MASK_ATIMWND_GROUP2 << BIT_SHIFT_ATIMWND_GROUP2)
+#define BIT_CLEAR_ATIMWND_GROUP2(x) ((x) & (~BITS_ATIMWND_GROUP2))
+#define BIT_GET_ATIMWND_GROUP2(x)                                              \
+	(((x) >> BIT_SHIFT_ATIMWND_GROUP2) & BIT_MASK_ATIMWND_GROUP2)
+#define BIT_SET_ATIMWND_GROUP2(x, v)                                           \
+	(BIT_CLEAR_ATIMWND_GROUP2(x) | BIT_ATIMWND_GROUP2(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8881A_SUPPORT)
+
+/* 2 REG_ATIMWND4				(Offset 0x05A2) */
+
+#define BIT_SHIFT_ATIMWND4 0
+#define BIT_MASK_ATIMWND4 0xff
+#define BIT_ATIMWND4(x) (((x) & BIT_MASK_ATIMWND4) << BIT_SHIFT_ATIMWND4)
+#define BITS_ATIMWND4 (BIT_MASK_ATIMWND4 << BIT_SHIFT_ATIMWND4)
+#define BIT_CLEAR_ATIMWND4(x) ((x) & (~BITS_ATIMWND4))
+#define BIT_GET_ATIMWND4(x) (((x) >> BIT_SHIFT_ATIMWND4) & BIT_MASK_ATIMWND4)
+#define BIT_SET_ATIMWND4(x, v) (BIT_CLEAR_ATIMWND4(x) | BIT_ATIMWND4(v))
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+/* 2 REG_ATIMWND_GROUP3			(Offset 0x05A2) */
+
+#define BIT_SHIFT_ATIMWND_GROUP3 0
+#define BIT_MASK_ATIMWND_GROUP3 0xff
+#define BIT_ATIMWND_GROUP3(x)                                                  \
+	(((x) & BIT_MASK_ATIMWND_GROUP3) << BIT_SHIFT_ATIMWND_GROUP3)
+#define BITS_ATIMWND_GROUP3                                                    \
+	(BIT_MASK_ATIMWND_GROUP3 << BIT_SHIFT_ATIMWND_GROUP3)
+#define BIT_CLEAR_ATIMWND_GROUP3(x) ((x) & (~BITS_ATIMWND_GROUP3))
+#define BIT_GET_ATIMWND_GROUP3(x)                                              \
+	(((x) >> BIT_SHIFT_ATIMWND_GROUP3) & BIT_MASK_ATIMWND_GROUP3)
+#define BIT_SET_ATIMWND_GROUP3(x, v)                                           \
+	(BIT_CLEAR_ATIMWND_GROUP3(x) | BIT_ATIMWND_GROUP3(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8881A_SUPPORT)
+
+/* 2 REG_ATIMWND5				(Offset 0x05A3) */
+
+#define BIT_SHIFT_ATIMWND5 0
+#define BIT_MASK_ATIMWND5 0xff
+#define BIT_ATIMWND5(x) (((x) & BIT_MASK_ATIMWND5) << BIT_SHIFT_ATIMWND5)
+#define BITS_ATIMWND5 (BIT_MASK_ATIMWND5 << BIT_SHIFT_ATIMWND5)
+#define BIT_CLEAR_ATIMWND5(x) ((x) & (~BITS_ATIMWND5))
+#define BIT_GET_ATIMWND5(x) (((x) >> BIT_SHIFT_ATIMWND5) & BIT_MASK_ATIMWND5)
+#define BIT_SET_ATIMWND5(x, v) (BIT_CLEAR_ATIMWND5(x) | BIT_ATIMWND5(v))
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+/* 2 REG_ATIMWND_GROUP4			(Offset 0x05A3) */
+
+#define BIT_SHIFT_ATIMWND_GROUP4 0
+#define BIT_MASK_ATIMWND_GROUP4 0xff
+#define BIT_ATIMWND_GROUP4(x)                                                  \
+	(((x) & BIT_MASK_ATIMWND_GROUP4) << BIT_SHIFT_ATIMWND_GROUP4)
+#define BITS_ATIMWND_GROUP4                                                    \
+	(BIT_MASK_ATIMWND_GROUP4 << BIT_SHIFT_ATIMWND_GROUP4)
+#define BIT_CLEAR_ATIMWND_GROUP4(x) ((x) & (~BITS_ATIMWND_GROUP4))
+#define BIT_GET_ATIMWND_GROUP4(x)                                              \
+	(((x) >> BIT_SHIFT_ATIMWND_GROUP4) & BIT_MASK_ATIMWND_GROUP4)
+#define BIT_SET_ATIMWND_GROUP4(x, v)                                           \
+	(BIT_CLEAR_ATIMWND_GROUP4(x) | BIT_ATIMWND_GROUP4(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8881A_SUPPORT)
+
+/* 2 REG_ATIMWND6				(Offset 0x05A4) */
+
+#define BIT_SHIFT_ATIMWND6 0
+#define BIT_MASK_ATIMWND6 0xff
+#define BIT_ATIMWND6(x) (((x) & BIT_MASK_ATIMWND6) << BIT_SHIFT_ATIMWND6)
+#define BITS_ATIMWND6 (BIT_MASK_ATIMWND6 << BIT_SHIFT_ATIMWND6)
+#define BIT_CLEAR_ATIMWND6(x) ((x) & (~BITS_ATIMWND6))
+#define BIT_GET_ATIMWND6(x) (((x) >> BIT_SHIFT_ATIMWND6) & BIT_MASK_ATIMWND6)
+#define BIT_SET_ATIMWND6(x, v) (BIT_CLEAR_ATIMWND6(x) | BIT_ATIMWND6(v))
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+/* 2 REG_DTIM_COUNT_GROUP1			(Offset 0x05A4) */
+
+#define BIT_SHIFT_DTIM_COUNT_GROUP1 0
+#define BIT_MASK_DTIM_COUNT_GROUP1 0xff
+#define BIT_DTIM_COUNT_GROUP1(x)                                               \
+	(((x) & BIT_MASK_DTIM_COUNT_GROUP1) << BIT_SHIFT_DTIM_COUNT_GROUP1)
+#define BITS_DTIM_COUNT_GROUP1                                                 \
+	(BIT_MASK_DTIM_COUNT_GROUP1 << BIT_SHIFT_DTIM_COUNT_GROUP1)
+#define BIT_CLEAR_DTIM_COUNT_GROUP1(x) ((x) & (~BITS_DTIM_COUNT_GROUP1))
+#define BIT_GET_DTIM_COUNT_GROUP1(x)                                           \
+	(((x) >> BIT_SHIFT_DTIM_COUNT_GROUP1) & BIT_MASK_DTIM_COUNT_GROUP1)
+#define BIT_SET_DTIM_COUNT_GROUP1(x, v)                                        \
+	(BIT_CLEAR_DTIM_COUNT_GROUP1(x) | BIT_DTIM_COUNT_GROUP1(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8881A_SUPPORT)
+
+/* 2 REG_ATIMWND7				(Offset 0x05A5) */
+
+#define BIT_SHIFT_ATIMWND7 0
+#define BIT_MASK_ATIMWND7 0xff
+#define BIT_ATIMWND7(x) (((x) & BIT_MASK_ATIMWND7) << BIT_SHIFT_ATIMWND7)
+#define BITS_ATIMWND7 (BIT_MASK_ATIMWND7 << BIT_SHIFT_ATIMWND7)
+#define BIT_CLEAR_ATIMWND7(x) ((x) & (~BITS_ATIMWND7))
+#define BIT_GET_ATIMWND7(x) (((x) >> BIT_SHIFT_ATIMWND7) & BIT_MASK_ATIMWND7)
+#define BIT_SET_ATIMWND7(x, v) (BIT_CLEAR_ATIMWND7(x) | BIT_ATIMWND7(v))
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+/* 2 REG_DTIM_COUNT_GROUP2			(Offset 0x05A5) */
+
+#define BIT_SHIFT_DTIM_COUNT_GROUP2 0
+#define BIT_MASK_DTIM_COUNT_GROUP2 0xff
+#define BIT_DTIM_COUNT_GROUP2(x)                                               \
+	(((x) & BIT_MASK_DTIM_COUNT_GROUP2) << BIT_SHIFT_DTIM_COUNT_GROUP2)
+#define BITS_DTIM_COUNT_GROUP2                                                 \
+	(BIT_MASK_DTIM_COUNT_GROUP2 << BIT_SHIFT_DTIM_COUNT_GROUP2)
+#define BIT_CLEAR_DTIM_COUNT_GROUP2(x) ((x) & (~BITS_DTIM_COUNT_GROUP2))
+#define BIT_GET_DTIM_COUNT_GROUP2(x)                                           \
+	(((x) >> BIT_SHIFT_DTIM_COUNT_GROUP2) & BIT_MASK_DTIM_COUNT_GROUP2)
+#define BIT_SET_DTIM_COUNT_GROUP2(x, v)                                        \
+	(BIT_CLEAR_DTIM_COUNT_GROUP2(x) | BIT_DTIM_COUNT_GROUP2(v))
+
+/* 2 REG_DTIM_COUNT_GROUP3			(Offset 0x05A6) */
+
+#define BIT_SHIFT_DTIM_COUNT_GROUP3 0
+#define BIT_MASK_DTIM_COUNT_GROUP3 0xff
+#define BIT_DTIM_COUNT_GROUP3(x)                                               \
+	(((x) & BIT_MASK_DTIM_COUNT_GROUP3) << BIT_SHIFT_DTIM_COUNT_GROUP3)
+#define BITS_DTIM_COUNT_GROUP3                                                 \
+	(BIT_MASK_DTIM_COUNT_GROUP3 << BIT_SHIFT_DTIM_COUNT_GROUP3)
+#define BIT_CLEAR_DTIM_COUNT_GROUP3(x) ((x) & (~BITS_DTIM_COUNT_GROUP3))
+#define BIT_GET_DTIM_COUNT_GROUP3(x)                                           \
+	(((x) >> BIT_SHIFT_DTIM_COUNT_GROUP3) & BIT_MASK_DTIM_COUNT_GROUP3)
+#define BIT_SET_DTIM_COUNT_GROUP3(x, v)                                        \
+	(BIT_CLEAR_DTIM_COUNT_GROUP3(x) | BIT_DTIM_COUNT_GROUP3(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_HIQ_NO_LMT_EN			(Offset 0x05A7) */
+
+#define BIT_HIQ_NO_LMT_EN_VAP7 BIT(7)
+#define BIT_HIQ_NO_LMT_EN_VAP6 BIT(6)
+#define BIT_HIQ_NO_LMT_EN_VAP5 BIT(5)
+#define BIT_HIQ_NO_LMT_EN_VAP4 BIT(4)
+#define BIT_HIQ_NO_LMT_EN_VAP3 BIT(3)
+#define BIT_HIQ_NO_LMT_EN_VAP2 BIT(2)
+#define BIT_HIQ_NO_LMT_EN_VAP1 BIT(1)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_HIQ_NO_LMT_EN			(Offset 0x05A7) */
+
+#define BIT_HIQ_NO_LMT_EN_ROOT BIT(0)
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+/* 2 REG_DTIM_COUNT_GROUP4			(Offset 0x05A7) */
+
+#define BIT_SHIFT_DTIM_COUNT_GROUP4 0
+#define BIT_MASK_DTIM_COUNT_GROUP4 0xff
+#define BIT_DTIM_COUNT_GROUP4(x)                                               \
+	(((x) & BIT_MASK_DTIM_COUNT_GROUP4) << BIT_SHIFT_DTIM_COUNT_GROUP4)
+#define BITS_DTIM_COUNT_GROUP4                                                 \
+	(BIT_MASK_DTIM_COUNT_GROUP4 << BIT_SHIFT_DTIM_COUNT_GROUP4)
+#define BIT_CLEAR_DTIM_COUNT_GROUP4(x) ((x) & (~BITS_DTIM_COUNT_GROUP4))
+#define BIT_GET_DTIM_COUNT_GROUP4(x)                                           \
+	(((x) >> BIT_SHIFT_DTIM_COUNT_GROUP4) & BIT_MASK_DTIM_COUNT_GROUP4)
+#define BIT_SET_DTIM_COUNT_GROUP4(x, v)                                        \
+	(BIT_CLEAR_DTIM_COUNT_GROUP4(x) | BIT_DTIM_COUNT_GROUP4(v))
+
+/* 2 REG_HIQ_NO_LMT_EN_V2			(Offset 0x05A8) */
+
+#define BIT_SHIFT_ATIM_CFG_SEL 24
+#define BIT_MASK_ATIM_CFG_SEL 0x3
+#define BIT_ATIM_CFG_SEL(x)                                                    \
+	(((x) & BIT_MASK_ATIM_CFG_SEL) << BIT_SHIFT_ATIM_CFG_SEL)
+#define BITS_ATIM_CFG_SEL (BIT_MASK_ATIM_CFG_SEL << BIT_SHIFT_ATIM_CFG_SEL)
+#define BIT_CLEAR_ATIM_CFG_SEL(x) ((x) & (~BITS_ATIM_CFG_SEL))
+#define BIT_GET_ATIM_CFG_SEL(x)                                                \
+	(((x) >> BIT_SHIFT_ATIM_CFG_SEL) & BIT_MASK_ATIM_CFG_SEL)
+#define BIT_SET_ATIM_CFG_SEL(x, v)                                             \
+	(BIT_CLEAR_ATIM_CFG_SEL(x) | BIT_ATIM_CFG_SEL(v))
+
+#define BIT_SHIFT_DIS_ATIM 16
+#define BIT_MASK_DIS_ATIM 0xffff
+#define BIT_DIS_ATIM(x) (((x) & BIT_MASK_DIS_ATIM) << BIT_SHIFT_DIS_ATIM)
+#define BITS_DIS_ATIM (BIT_MASK_DIS_ATIM << BIT_SHIFT_DIS_ATIM)
+#define BIT_CLEAR_DIS_ATIM(x) ((x) & (~BITS_DIS_ATIM))
+#define BIT_GET_DIS_ATIM(x) (((x) >> BIT_SHIFT_DIS_ATIM) & BIT_MASK_DIS_ATIM)
+#define BIT_SET_DIS_ATIM(x, v) (BIT_CLEAR_DIS_ATIM(x) | BIT_DIS_ATIM(v))
+
+#define BIT_SHIFT_ATIM_URGENT_V1 16
+#define BIT_MASK_ATIM_URGENT_V1 0xff
+#define BIT_ATIM_URGENT_V1(x)                                                  \
+	(((x) & BIT_MASK_ATIM_URGENT_V1) << BIT_SHIFT_ATIM_URGENT_V1)
+#define BITS_ATIM_URGENT_V1                                                    \
+	(BIT_MASK_ATIM_URGENT_V1 << BIT_SHIFT_ATIM_URGENT_V1)
+#define BIT_CLEAR_ATIM_URGENT_V1(x) ((x) & (~BITS_ATIM_URGENT_V1))
+#define BIT_GET_ATIM_URGENT_V1(x)                                              \
+	(((x) >> BIT_SHIFT_ATIM_URGENT_V1) & BIT_MASK_ATIM_URGENT_V1)
+#define BIT_SET_ATIM_URGENT_V1(x, v)                                           \
+	(BIT_CLEAR_ATIM_URGENT_V1(x) | BIT_ATIM_URGENT_V1(v))
+
+#define BIT_SHIFT_BCNERR_PORT_SEL_V1 16
+#define BIT_MASK_BCNERR_PORT_SEL_V1 0xf
+#define BIT_BCNERR_PORT_SEL_V1(x)                                              \
+	(((x) & BIT_MASK_BCNERR_PORT_SEL_V1) << BIT_SHIFT_BCNERR_PORT_SEL_V1)
+#define BITS_BCNERR_PORT_SEL_V1                                                \
+	(BIT_MASK_BCNERR_PORT_SEL_V1 << BIT_SHIFT_BCNERR_PORT_SEL_V1)
+#define BIT_CLEAR_BCNERR_PORT_SEL_V1(x) ((x) & (~BITS_BCNERR_PORT_SEL_V1))
+#define BIT_GET_BCNERR_PORT_SEL_V1(x)                                          \
+	(((x) >> BIT_SHIFT_BCNERR_PORT_SEL_V1) & BIT_MASK_BCNERR_PORT_SEL_V1)
+#define BIT_SET_BCNERR_PORT_SEL_V1(x, v)                                       \
+	(BIT_CLEAR_BCNERR_PORT_SEL_V1(x) | BIT_BCNERR_PORT_SEL_V1(v))
+
+#define BIT_DIS_NDPA_NAV_CHK BIT(8)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8881A_SUPPORT)
+
+/* 2 REG_DTIM_COUNTER_ROOT			(Offset 0x05A8) */
+
+#define BIT_SHIFT_DTIM_COUNT_ROOT 0
+#define BIT_MASK_DTIM_COUNT_ROOT 0xff
+#define BIT_DTIM_COUNT_ROOT(x)                                                 \
+	(((x) & BIT_MASK_DTIM_COUNT_ROOT) << BIT_SHIFT_DTIM_COUNT_ROOT)
+#define BITS_DTIM_COUNT_ROOT                                                   \
+	(BIT_MASK_DTIM_COUNT_ROOT << BIT_SHIFT_DTIM_COUNT_ROOT)
+#define BIT_CLEAR_DTIM_COUNT_ROOT(x) ((x) & (~BITS_DTIM_COUNT_ROOT))
+#define BIT_GET_DTIM_COUNT_ROOT(x)                                             \
+	(((x) >> BIT_SHIFT_DTIM_COUNT_ROOT) & BIT_MASK_DTIM_COUNT_ROOT)
+#define BIT_SET_DTIM_COUNT_ROOT(x, v)                                          \
+	(BIT_CLEAR_DTIM_COUNT_ROOT(x) | BIT_DTIM_COUNT_ROOT(v))
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+/* 2 REG_HIQ_NO_LMT_EN_V2			(Offset 0x05A8) */
+
+#define BIT_SHIFT_MBID_BCNQ_EN 0
+#define BIT_MASK_MBID_BCNQ_EN 0xffff
+#define BIT_MBID_BCNQ_EN(x)                                                    \
+	(((x) & BIT_MASK_MBID_BCNQ_EN) << BIT_SHIFT_MBID_BCNQ_EN)
+#define BITS_MBID_BCNQ_EN (BIT_MASK_MBID_BCNQ_EN << BIT_SHIFT_MBID_BCNQ_EN)
+#define BIT_CLEAR_MBID_BCNQ_EN(x) ((x) & (~BITS_MBID_BCNQ_EN))
+#define BIT_GET_MBID_BCNQ_EN(x)                                                \
+	(((x) >> BIT_SHIFT_MBID_BCNQ_EN) & BIT_MASK_MBID_BCNQ_EN)
+#define BIT_SET_MBID_BCNQ_EN(x, v)                                             \
+	(BIT_CLEAR_MBID_BCNQ_EN(x) | BIT_MBID_BCNQ_EN(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8881A_SUPPORT)
+
+/* 2 REG_DTIM_COUNTER_VAP1			(Offset 0x05A9) */
+
+#define BIT_SHIFT_DTIM_COUNT_VAP1 0
+#define BIT_MASK_DTIM_COUNT_VAP1 0xff
+#define BIT_DTIM_COUNT_VAP1(x)                                                 \
+	(((x) & BIT_MASK_DTIM_COUNT_VAP1) << BIT_SHIFT_DTIM_COUNT_VAP1)
+#define BITS_DTIM_COUNT_VAP1                                                   \
+	(BIT_MASK_DTIM_COUNT_VAP1 << BIT_SHIFT_DTIM_COUNT_VAP1)
+#define BIT_CLEAR_DTIM_COUNT_VAP1(x) ((x) & (~BITS_DTIM_COUNT_VAP1))
+#define BIT_GET_DTIM_COUNT_VAP1(x)                                             \
+	(((x) >> BIT_SHIFT_DTIM_COUNT_VAP1) & BIT_MASK_DTIM_COUNT_VAP1)
+#define BIT_SET_DTIM_COUNT_VAP1(x, v)                                          \
+	(BIT_CLEAR_DTIM_COUNT_VAP1(x) | BIT_DTIM_COUNT_VAP1(v))
+
+/* 2 REG_DTIM_COUNTER_VAP2			(Offset 0x05AA) */
+
+#define BIT_SHIFT_DTIM_COUNT_VAP2 0
+#define BIT_MASK_DTIM_COUNT_VAP2 0xff
+#define BIT_DTIM_COUNT_VAP2(x)                                                 \
+	(((x) & BIT_MASK_DTIM_COUNT_VAP2) << BIT_SHIFT_DTIM_COUNT_VAP2)
+#define BITS_DTIM_COUNT_VAP2                                                   \
+	(BIT_MASK_DTIM_COUNT_VAP2 << BIT_SHIFT_DTIM_COUNT_VAP2)
+#define BIT_CLEAR_DTIM_COUNT_VAP2(x) ((x) & (~BITS_DTIM_COUNT_VAP2))
+#define BIT_GET_DTIM_COUNT_VAP2(x)                                             \
+	(((x) >> BIT_SHIFT_DTIM_COUNT_VAP2) & BIT_MASK_DTIM_COUNT_VAP2)
+#define BIT_SET_DTIM_COUNT_VAP2(x, v)                                          \
+	(BIT_CLEAR_DTIM_COUNT_VAP2(x) | BIT_DTIM_COUNT_VAP2(v))
+
+/* 2 REG_DTIM_COUNTER_VAP3			(Offset 0x05AB) */
+
+#define BIT_SHIFT_DTIM_COUNT_VAP3 0
+#define BIT_MASK_DTIM_COUNT_VAP3 0xff
+#define BIT_DTIM_COUNT_VAP3(x)                                                 \
+	(((x) & BIT_MASK_DTIM_COUNT_VAP3) << BIT_SHIFT_DTIM_COUNT_VAP3)
+#define BITS_DTIM_COUNT_VAP3                                                   \
+	(BIT_MASK_DTIM_COUNT_VAP3 << BIT_SHIFT_DTIM_COUNT_VAP3)
+#define BIT_CLEAR_DTIM_COUNT_VAP3(x) ((x) & (~BITS_DTIM_COUNT_VAP3))
+#define BIT_GET_DTIM_COUNT_VAP3(x)                                             \
+	(((x) >> BIT_SHIFT_DTIM_COUNT_VAP3) & BIT_MASK_DTIM_COUNT_VAP3)
+#define BIT_SET_DTIM_COUNT_VAP3(x, v)                                          \
+	(BIT_CLEAR_DTIM_COUNT_VAP3(x) | BIT_DTIM_COUNT_VAP3(v))
+
+/* 2 REG_DTIM_COUNTER_VAP4			(Offset 0x05AC) */
+
+#define BIT_SHIFT_DTIM_COUNT_VAP4 0
+#define BIT_MASK_DTIM_COUNT_VAP4 0xff
+#define BIT_DTIM_COUNT_VAP4(x)                                                 \
+	(((x) & BIT_MASK_DTIM_COUNT_VAP4) << BIT_SHIFT_DTIM_COUNT_VAP4)
+#define BITS_DTIM_COUNT_VAP4                                                   \
+	(BIT_MASK_DTIM_COUNT_VAP4 << BIT_SHIFT_DTIM_COUNT_VAP4)
+#define BIT_CLEAR_DTIM_COUNT_VAP4(x) ((x) & (~BITS_DTIM_COUNT_VAP4))
+#define BIT_GET_DTIM_COUNT_VAP4(x)                                             \
+	(((x) >> BIT_SHIFT_DTIM_COUNT_VAP4) & BIT_MASK_DTIM_COUNT_VAP4)
+#define BIT_SET_DTIM_COUNT_VAP4(x, v)                                          \
+	(BIT_CLEAR_DTIM_COUNT_VAP4(x) | BIT_DTIM_COUNT_VAP4(v))
+
+/* 2 REG_DTIM_COUNTER_VAP5			(Offset 0x05AD) */
+
+#define BIT_SHIFT_DTIM_COUNT_VAP5 0
+#define BIT_MASK_DTIM_COUNT_VAP5 0xff
+#define BIT_DTIM_COUNT_VAP5(x)                                                 \
+	(((x) & BIT_MASK_DTIM_COUNT_VAP5) << BIT_SHIFT_DTIM_COUNT_VAP5)
+#define BITS_DTIM_COUNT_VAP5                                                   \
+	(BIT_MASK_DTIM_COUNT_VAP5 << BIT_SHIFT_DTIM_COUNT_VAP5)
+#define BIT_CLEAR_DTIM_COUNT_VAP5(x) ((x) & (~BITS_DTIM_COUNT_VAP5))
+#define BIT_GET_DTIM_COUNT_VAP5(x)                                             \
+	(((x) >> BIT_SHIFT_DTIM_COUNT_VAP5) & BIT_MASK_DTIM_COUNT_VAP5)
+#define BIT_SET_DTIM_COUNT_VAP5(x, v)                                          \
+	(BIT_CLEAR_DTIM_COUNT_VAP5(x) | BIT_DTIM_COUNT_VAP5(v))
+
+/* 2 REG_DTIM_COUNTER_VAP6			(Offset 0x05AE) */
+
+#define BIT_SHIFT_DTIM_COUNT_VAP6 0
+#define BIT_MASK_DTIM_COUNT_VAP6 0xff
+#define BIT_DTIM_COUNT_VAP6(x)                                                 \
+	(((x) & BIT_MASK_DTIM_COUNT_VAP6) << BIT_SHIFT_DTIM_COUNT_VAP6)
+#define BITS_DTIM_COUNT_VAP6                                                   \
+	(BIT_MASK_DTIM_COUNT_VAP6 << BIT_SHIFT_DTIM_COUNT_VAP6)
+#define BIT_CLEAR_DTIM_COUNT_VAP6(x) ((x) & (~BITS_DTIM_COUNT_VAP6))
+#define BIT_GET_DTIM_COUNT_VAP6(x)                                             \
+	(((x) >> BIT_SHIFT_DTIM_COUNT_VAP6) & BIT_MASK_DTIM_COUNT_VAP6)
+#define BIT_SET_DTIM_COUNT_VAP6(x, v)                                          \
+	(BIT_CLEAR_DTIM_COUNT_VAP6(x) | BIT_DTIM_COUNT_VAP6(v))
+
+/* 2 REG_DTIM_COUNTER_VAP7			(Offset 0x05AF) */
+
+#define BIT_SHIFT_DTIM_COUNT_VAP7 0
+#define BIT_MASK_DTIM_COUNT_VAP7 0xff
+#define BIT_DTIM_COUNT_VAP7(x)                                                 \
+	(((x) & BIT_MASK_DTIM_COUNT_VAP7) << BIT_SHIFT_DTIM_COUNT_VAP7)
+#define BITS_DTIM_COUNT_VAP7                                                   \
+	(BIT_MASK_DTIM_COUNT_VAP7 << BIT_SHIFT_DTIM_COUNT_VAP7)
+#define BIT_CLEAR_DTIM_COUNT_VAP7(x) ((x) & (~BITS_DTIM_COUNT_VAP7))
+#define BIT_GET_DTIM_COUNT_VAP7(x)                                             \
+	(((x) >> BIT_SHIFT_DTIM_COUNT_VAP7) & BIT_MASK_DTIM_COUNT_VAP7)
+#define BIT_SET_DTIM_COUNT_VAP7(x, v)                                          \
+	(BIT_CLEAR_DTIM_COUNT_VAP7(x) | BIT_DTIM_COUNT_VAP7(v))
+
+/* 2 REG_DIS_ATIM				(Offset 0x05B0) */
+
+#define BIT_MBIDCAM_VALID BIT(23)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_DIS_ATIM				(Offset 0x05B0) */
+
+#define BIT_DIS_ATIM_VAP7 BIT(7)
+#define BIT_DIS_ATIM_VAP6 BIT(6)
+#define BIT_DIS_ATIM_VAP5 BIT(5)
+#define BIT_DIS_ATIM_VAP4 BIT(4)
+#define BIT_DIS_ATIM_VAP3 BIT(3)
+#define BIT_DIS_ATIM_VAP2 BIT(2)
+#define BIT_DIS_ATIM_VAP1 BIT(1)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8881A_SUPPORT)
+
+/* 2 REG_DIS_ATIM				(Offset 0x05B0) */
+
+#define BIT_DIS_ATIM_ROOT BIT(0)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_EARLY_128US				(Offset 0x05B1) */
+
+#define BIT_SHIFT_EARLY_128US_2ST 3
+#define BIT_MASK_EARLY_128US_2ST 0x7
+#define BIT_EARLY_128US_2ST(x)                                                 \
+	(((x) & BIT_MASK_EARLY_128US_2ST) << BIT_SHIFT_EARLY_128US_2ST)
+#define BITS_EARLY_128US_2ST                                                   \
+	(BIT_MASK_EARLY_128US_2ST << BIT_SHIFT_EARLY_128US_2ST)
+#define BIT_CLEAR_EARLY_128US_2ST(x) ((x) & (~BITS_EARLY_128US_2ST))
+#define BIT_GET_EARLY_128US_2ST(x)                                             \
+	(((x) >> BIT_SHIFT_EARLY_128US_2ST) & BIT_MASK_EARLY_128US_2ST)
+#define BIT_SET_EARLY_128US_2ST(x, v)                                          \
+	(BIT_CLEAR_EARLY_128US_2ST(x) | BIT_EARLY_128US_2ST(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_EARLY_128US				(Offset 0x05B1) */
+
+#define BIT_SHIFT_TSFT_SEL_TIMER1 3
+#define BIT_MASK_TSFT_SEL_TIMER1 0x7
+#define BIT_TSFT_SEL_TIMER1(x)                                                 \
+	(((x) & BIT_MASK_TSFT_SEL_TIMER1) << BIT_SHIFT_TSFT_SEL_TIMER1)
+#define BITS_TSFT_SEL_TIMER1                                                   \
+	(BIT_MASK_TSFT_SEL_TIMER1 << BIT_SHIFT_TSFT_SEL_TIMER1)
+#define BIT_CLEAR_TSFT_SEL_TIMER1(x) ((x) & (~BITS_TSFT_SEL_TIMER1))
+#define BIT_GET_TSFT_SEL_TIMER1(x)                                             \
+	(((x) >> BIT_SHIFT_TSFT_SEL_TIMER1) & BIT_MASK_TSFT_SEL_TIMER1)
+#define BIT_SET_TSFT_SEL_TIMER1(x, v)                                          \
+	(BIT_CLEAR_TSFT_SEL_TIMER1(x) | BIT_TSFT_SEL_TIMER1(v))
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_TBTT_HOLD_PREDICT_P1		(Offset 0x05B2) */
+
+#define BIT_DIS_BCN_3RD BIT(7)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_P2PPS1_CTRL				(Offset 0x05B2) */
+
+#define BIT_P2P1_CTW_ALLSTASLEEP BIT(7)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_TBTT_HOLD_PREDICT_P1		(Offset 0x05B2) */
+
+#define BIT_DIS_BCN_2ST BIT(6)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_P2PPS1_CTRL				(Offset 0x05B2) */
+
+#define BIT_P2P1_OFF_DISTX_EN BIT(6)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_TBTT_HOLD_PREDICT_P1		(Offset 0x05B2) */
+
+#define BIT_DIS_BCN_1ST BIT(5)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_P2PPS1_CTRL				(Offset 0x05B2) */
+
+#define BIT_P2P1_PWR_MGT_EN BIT(5)
+#define BIT_P2P1_NOA1_EN BIT(2)
+#define BIT_P2P1_NOA0_EN BIT(1)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_TBTT_HOLD_PREDICT_P1		(Offset 0x05B2) */
+
+#define BIT_SHIFT_TBTT_HOLD_PREDICT_P1 0
+#define BIT_MASK_TBTT_HOLD_PREDICT_P1 0x1f
+#define BIT_TBTT_HOLD_PREDICT_P1(x)                                            \
+	(((x) & BIT_MASK_TBTT_HOLD_PREDICT_P1)                                 \
+	 << BIT_SHIFT_TBTT_HOLD_PREDICT_P1)
+#define BITS_TBTT_HOLD_PREDICT_P1                                              \
+	(BIT_MASK_TBTT_HOLD_PREDICT_P1 << BIT_SHIFT_TBTT_HOLD_PREDICT_P1)
+#define BIT_CLEAR_TBTT_HOLD_PREDICT_P1(x) ((x) & (~BITS_TBTT_HOLD_PREDICT_P1))
+#define BIT_GET_TBTT_HOLD_PREDICT_P1(x)                                        \
+	(((x) >> BIT_SHIFT_TBTT_HOLD_PREDICT_P1) &                             \
+	 BIT_MASK_TBTT_HOLD_PREDICT_P1)
+#define BIT_SET_TBTT_HOLD_PREDICT_P1(x, v)                                     \
+	(BIT_CLEAR_TBTT_HOLD_PREDICT_P1(x) | BIT_TBTT_HOLD_PREDICT_P1(v))
+
+/* 2 REG_MULTI_BCN_CS			(Offset 0x05B3) */
+
+#define BIT_EN_FREECNT_V2 BIT(13)
+#define BIT_RESET_FREECNT_P BIT(12)
+#define BIT_TSFTR3_SYNC_EN BIT(7)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_P2PPS2_CTRL				(Offset 0x05B3) */
+
+#define BIT_P2P2_CTW_ALLSTASLEEP BIT(7)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_MULTI_BCN_CS			(Offset 0x05B3) */
+
+#define BIT_SHIFT_P1_TSFT_SHIFT 6
+#define BIT_MASK_P1_TSFT_SHIFT 0x3f
+#define BIT_P1_TSFT_SHIFT(x)                                                   \
+	(((x) & BIT_MASK_P1_TSFT_SHIFT) << BIT_SHIFT_P1_TSFT_SHIFT)
+#define BITS_P1_TSFT_SHIFT (BIT_MASK_P1_TSFT_SHIFT << BIT_SHIFT_P1_TSFT_SHIFT)
+#define BIT_CLEAR_P1_TSFT_SHIFT(x) ((x) & (~BITS_P1_TSFT_SHIFT))
+#define BIT_GET_P1_TSFT_SHIFT(x)                                               \
+	(((x) >> BIT_SHIFT_P1_TSFT_SHIFT) & BIT_MASK_P1_TSFT_SHIFT)
+#define BIT_SET_P1_TSFT_SHIFT(x, v)                                            \
+	(BIT_CLEAR_P1_TSFT_SHIFT(x) | BIT_P1_TSFT_SHIFT(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_P2PPS2_CTRL				(Offset 0x05B3) */
+
+#define BIT_P2P2_OFF_DISTX_EN BIT(6)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_MULTI_BCN_CS			(Offset 0x05B3) */
+
+#define BIT_TSFTR2_SYNC_EN BIT(5)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_P2PPS2_CTRL				(Offset 0x05B3) */
+
+#define BIT_P2P2_PWR_MGT_EN BIT(5)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_MULTI_BCN_CS			(Offset 0x05B3) */
+
+#define BIT_TSFTR2_RST BIT(4)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_P2PPS2_CTRL				(Offset 0x05B3) */
+
+#define BIT_P2P2_NOA1_EN BIT(2)
+#define BIT_P2P2_NOA0_EN BIT(1)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_MULTI_BCN_CS			(Offset 0x05B3) */
+
+#define BIT_SHIFT_MULTI_BCN_CS 0
+#define BIT_MASK_MULTI_BCN_CS 0xf
+#define BIT_MULTI_BCN_CS(x)                                                    \
+	(((x) & BIT_MASK_MULTI_BCN_CS) << BIT_SHIFT_MULTI_BCN_CS)
+#define BITS_MULTI_BCN_CS (BIT_MASK_MULTI_BCN_CS << BIT_SHIFT_MULTI_BCN_CS)
+#define BIT_CLEAR_MULTI_BCN_CS(x) ((x) & (~BITS_MULTI_BCN_CS))
+#define BIT_GET_MULTI_BCN_CS(x)                                                \
+	(((x) >> BIT_SHIFT_MULTI_BCN_CS) & BIT_MASK_MULTI_BCN_CS)
+#define BIT_SET_MULTI_BCN_CS(x, v)                                             \
+	(BIT_CLEAR_MULTI_BCN_CS(x) | BIT_MULTI_BCN_CS(v))
+
+#define BIT_SHIFT_P0_TSFT_SHIFT 0
+#define BIT_MASK_P0_TSFT_SHIFT 0x3f
+#define BIT_P0_TSFT_SHIFT(x)                                                   \
+	(((x) & BIT_MASK_P0_TSFT_SHIFT) << BIT_SHIFT_P0_TSFT_SHIFT)
+#define BITS_P0_TSFT_SHIFT (BIT_MASK_P0_TSFT_SHIFT << BIT_SHIFT_P0_TSFT_SHIFT)
+#define BIT_CLEAR_P0_TSFT_SHIFT(x) ((x) & (~BITS_P0_TSFT_SHIFT))
+#define BIT_GET_P0_TSFT_SHIFT(x)                                               \
+	(((x) >> BIT_SHIFT_P0_TSFT_SHIFT) & BIT_MASK_P0_TSFT_SHIFT)
+#define BIT_SET_P0_TSFT_SHIFT(x, v)                                            \
+	(BIT_CLEAR_P0_TSFT_SHIFT(x) | BIT_P0_TSFT_SHIFT(v))
+
+#define BIT_DIS_NDPA_NAV_CHK_V1 BIT(0)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_TIMER0_SRC_SEL			(Offset 0x05B4) */
+
+#define BIT_SHIFT_SYNC_CLI_SEL 4
+#define BIT_MASK_SYNC_CLI_SEL 0x7
+#define BIT_SYNC_CLI_SEL(x)                                                    \
+	(((x) & BIT_MASK_SYNC_CLI_SEL) << BIT_SHIFT_SYNC_CLI_SEL)
+#define BITS_SYNC_CLI_SEL (BIT_MASK_SYNC_CLI_SEL << BIT_SHIFT_SYNC_CLI_SEL)
+#define BIT_CLEAR_SYNC_CLI_SEL(x) ((x) & (~BITS_SYNC_CLI_SEL))
+#define BIT_GET_SYNC_CLI_SEL(x)                                                \
+	(((x) >> BIT_SHIFT_SYNC_CLI_SEL) & BIT_MASK_SYNC_CLI_SEL)
+#define BIT_SET_SYNC_CLI_SEL(x, v)                                             \
+	(BIT_CLEAR_SYNC_CLI_SEL(x) | BIT_SYNC_CLI_SEL(v))
+
+#define BIT_SHIFT_TSFT_SEL_TIMER0 0
+#define BIT_MASK_TSFT_SEL_TIMER0 0x7
+#define BIT_TSFT_SEL_TIMER0(x)                                                 \
+	(((x) & BIT_MASK_TSFT_SEL_TIMER0) << BIT_SHIFT_TSFT_SEL_TIMER0)
+#define BITS_TSFT_SEL_TIMER0                                                   \
+	(BIT_MASK_TSFT_SEL_TIMER0 << BIT_SHIFT_TSFT_SEL_TIMER0)
+#define BIT_CLEAR_TSFT_SEL_TIMER0(x) ((x) & (~BITS_TSFT_SEL_TIMER0))
+#define BIT_GET_TSFT_SEL_TIMER0(x)                                             \
+	(((x) >> BIT_SHIFT_TSFT_SEL_TIMER0) & BIT_MASK_TSFT_SEL_TIMER0)
+#define BIT_SET_TSFT_SEL_TIMER0(x, v)                                          \
+	(BIT_CLEAR_TSFT_SEL_TIMER0(x) | BIT_TSFT_SEL_TIMER0(v))
+
+/* 2 REG_NOA_UNIT_SEL			(Offset 0x05B5) */
+
+#define BIT_SHIFT_NOA_UNIT2_SEL 8
+#define BIT_MASK_NOA_UNIT2_SEL 0x7
+#define BIT_NOA_UNIT2_SEL(x)                                                   \
+	(((x) & BIT_MASK_NOA_UNIT2_SEL) << BIT_SHIFT_NOA_UNIT2_SEL)
+#define BITS_NOA_UNIT2_SEL (BIT_MASK_NOA_UNIT2_SEL << BIT_SHIFT_NOA_UNIT2_SEL)
+#define BIT_CLEAR_NOA_UNIT2_SEL(x) ((x) & (~BITS_NOA_UNIT2_SEL))
+#define BIT_GET_NOA_UNIT2_SEL(x)                                               \
+	(((x) >> BIT_SHIFT_NOA_UNIT2_SEL) & BIT_MASK_NOA_UNIT2_SEL)
+#define BIT_SET_NOA_UNIT2_SEL(x, v)                                            \
+	(BIT_CLEAR_NOA_UNIT2_SEL(x) | BIT_NOA_UNIT2_SEL(v))
+
+#define BIT_SHIFT_NOA_UNIT1_SEL 4
+#define BIT_MASK_NOA_UNIT1_SEL 0x7
+#define BIT_NOA_UNIT1_SEL(x)                                                   \
+	(((x) & BIT_MASK_NOA_UNIT1_SEL) << BIT_SHIFT_NOA_UNIT1_SEL)
+#define BITS_NOA_UNIT1_SEL (BIT_MASK_NOA_UNIT1_SEL << BIT_SHIFT_NOA_UNIT1_SEL)
+#define BIT_CLEAR_NOA_UNIT1_SEL(x) ((x) & (~BITS_NOA_UNIT1_SEL))
+#define BIT_GET_NOA_UNIT1_SEL(x)                                               \
+	(((x) >> BIT_SHIFT_NOA_UNIT1_SEL) & BIT_MASK_NOA_UNIT1_SEL)
+#define BIT_SET_NOA_UNIT1_SEL(x, v)                                            \
+	(BIT_CLEAR_NOA_UNIT1_SEL(x) | BIT_NOA_UNIT1_SEL(v))
+
+#define BIT_SHIFT_NOA_UNIT0_SEL 0
+#define BIT_MASK_NOA_UNIT0_SEL 0x7
+#define BIT_NOA_UNIT0_SEL(x)                                                   \
+	(((x) & BIT_MASK_NOA_UNIT0_SEL) << BIT_SHIFT_NOA_UNIT0_SEL)
+#define BITS_NOA_UNIT0_SEL (BIT_MASK_NOA_UNIT0_SEL << BIT_SHIFT_NOA_UNIT0_SEL)
+#define BIT_CLEAR_NOA_UNIT0_SEL(x) ((x) & (~BITS_NOA_UNIT0_SEL))
+#define BIT_GET_NOA_UNIT0_SEL(x)                                               \
+	(((x) >> BIT_SHIFT_NOA_UNIT0_SEL) & BIT_MASK_NOA_UNIT0_SEL)
+#define BIT_SET_NOA_UNIT0_SEL(x, v)                                            \
+	(BIT_CLEAR_NOA_UNIT0_SEL(x) | BIT_NOA_UNIT0_SEL(v))
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_P2POFF_DIS_TXTIME			(Offset 0x05B7) */
+
+#define BIT_SHIFT_P2POFF_DIS_TXTIME 0
+#define BIT_MASK_P2POFF_DIS_TXTIME 0xff
+#define BIT_P2POFF_DIS_TXTIME(x)                                               \
+	(((x) & BIT_MASK_P2POFF_DIS_TXTIME) << BIT_SHIFT_P2POFF_DIS_TXTIME)
+#define BITS_P2POFF_DIS_TXTIME                                                 \
+	(BIT_MASK_P2POFF_DIS_TXTIME << BIT_SHIFT_P2POFF_DIS_TXTIME)
+#define BIT_CLEAR_P2POFF_DIS_TXTIME(x) ((x) & (~BITS_P2POFF_DIS_TXTIME))
+#define BIT_GET_P2POFF_DIS_TXTIME(x)                                           \
+	(((x) >> BIT_SHIFT_P2POFF_DIS_TXTIME) & BIT_MASK_P2POFF_DIS_TXTIME)
+#define BIT_SET_P2POFF_DIS_TXTIME(x, v)                                        \
+	(BIT_CLEAR_P2POFF_DIS_TXTIME(x) | BIT_P2POFF_DIS_TXTIME(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_MBSSID_BCN_SPACE2			(Offset 0x05B8) */
+
+#define BIT_SHIFT_BCN_SPACE_CLINT2 16
+#define BIT_MASK_BCN_SPACE_CLINT2 0xfff
+#define BIT_BCN_SPACE_CLINT2(x)                                                \
+	(((x) & BIT_MASK_BCN_SPACE_CLINT2) << BIT_SHIFT_BCN_SPACE_CLINT2)
+#define BITS_BCN_SPACE_CLINT2                                                  \
+	(BIT_MASK_BCN_SPACE_CLINT2 << BIT_SHIFT_BCN_SPACE_CLINT2)
+#define BIT_CLEAR_BCN_SPACE_CLINT2(x) ((x) & (~BITS_BCN_SPACE_CLINT2))
+#define BIT_GET_BCN_SPACE_CLINT2(x)                                            \
+	(((x) >> BIT_SHIFT_BCN_SPACE_CLINT2) & BIT_MASK_BCN_SPACE_CLINT2)
+#define BIT_SET_BCN_SPACE_CLINT2(x, v)                                         \
+	(BIT_CLEAR_BCN_SPACE_CLINT2(x) | BIT_BCN_SPACE_CLINT2(v))
+
+#define BIT_SHIFT_BCN_SPACE_CLINT1 0
+#define BIT_MASK_BCN_SPACE_CLINT1 0xfff
+#define BIT_BCN_SPACE_CLINT1(x)                                                \
+	(((x) & BIT_MASK_BCN_SPACE_CLINT1) << BIT_SHIFT_BCN_SPACE_CLINT1)
+#define BITS_BCN_SPACE_CLINT1                                                  \
+	(BIT_MASK_BCN_SPACE_CLINT1 << BIT_SHIFT_BCN_SPACE_CLINT1)
+#define BIT_CLEAR_BCN_SPACE_CLINT1(x) ((x) & (~BITS_BCN_SPACE_CLINT1))
+#define BIT_GET_BCN_SPACE_CLINT1(x)                                            \
+	(((x) >> BIT_SHIFT_BCN_SPACE_CLINT1) & BIT_MASK_BCN_SPACE_CLINT1)
+#define BIT_SET_BCN_SPACE_CLINT1(x, v)                                         \
+	(BIT_CLEAR_BCN_SPACE_CLINT1(x) | BIT_BCN_SPACE_CLINT1(v))
+
+/* 2 REG_MBSSID_BCN_SPACE3			(Offset 0x05BC) */
+
+#define BIT_SHIFT_SUB_BCN_SPACE 16
+#define BIT_MASK_SUB_BCN_SPACE 0xff
+#define BIT_SUB_BCN_SPACE(x)                                                   \
+	(((x) & BIT_MASK_SUB_BCN_SPACE) << BIT_SHIFT_SUB_BCN_SPACE)
+#define BITS_SUB_BCN_SPACE (BIT_MASK_SUB_BCN_SPACE << BIT_SHIFT_SUB_BCN_SPACE)
+#define BIT_CLEAR_SUB_BCN_SPACE(x) ((x) & (~BITS_SUB_BCN_SPACE))
+#define BIT_GET_SUB_BCN_SPACE(x)                                               \
+	(((x) >> BIT_SHIFT_SUB_BCN_SPACE) & BIT_MASK_SUB_BCN_SPACE)
+#define BIT_SET_SUB_BCN_SPACE(x, v)                                            \
+	(BIT_CLEAR_SUB_BCN_SPACE(x) | BIT_SUB_BCN_SPACE(v))
+
+#define BIT_SHIFT_BCN_SPACE_CLINT3 0
+#define BIT_MASK_BCN_SPACE_CLINT3 0xfff
+#define BIT_BCN_SPACE_CLINT3(x)                                                \
+	(((x) & BIT_MASK_BCN_SPACE_CLINT3) << BIT_SHIFT_BCN_SPACE_CLINT3)
+#define BITS_BCN_SPACE_CLINT3                                                  \
+	(BIT_MASK_BCN_SPACE_CLINT3 << BIT_SHIFT_BCN_SPACE_CLINT3)
+#define BIT_CLEAR_BCN_SPACE_CLINT3(x) ((x) & (~BITS_BCN_SPACE_CLINT3))
+#define BIT_GET_BCN_SPACE_CLINT3(x)                                            \
+	(((x) >> BIT_SHIFT_BCN_SPACE_CLINT3) & BIT_MASK_BCN_SPACE_CLINT3)
+#define BIT_SET_BCN_SPACE_CLINT3(x, v)                                         \
+	(BIT_CLEAR_BCN_SPACE_CLINT3(x) | BIT_BCN_SPACE_CLINT3(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_ACMHWCTRL				(Offset 0x05C0) */
+
+#define BIT_BEQ_ACM_STATUS BIT(7)
+#define BIT_VIQ_ACM_STATUS BIT(6)
+#define BIT_VOQ_ACM_STATUS BIT(5)
+#define BIT_BEQ_ACM_EN BIT(3)
+#define BIT_VIQ_ACM_EN BIT(2)
+#define BIT_VOQ_ACM_EN BIT(1)
+#define BIT_ACMHWEN BIT(0)
+
+/* 2 REG_ACMRSTCTRL				(Offset 0x05C1) */
+
+#define BIT_BE_ACM_RESET_USED_TIME BIT(2)
+#define BIT_VI_ACM_RESET_USED_TIME BIT(1)
+#define BIT_VO_ACM_RESET_USED_TIME BIT(0)
+
+/* 2 REG_ACMAVG				(Offset 0x05C2) */
+
+#define BIT_SHIFT_AVGPERIOD 0
+#define BIT_MASK_AVGPERIOD 0xffff
+#define BIT_AVGPERIOD(x) (((x) & BIT_MASK_AVGPERIOD) << BIT_SHIFT_AVGPERIOD)
+#define BITS_AVGPERIOD (BIT_MASK_AVGPERIOD << BIT_SHIFT_AVGPERIOD)
+#define BIT_CLEAR_AVGPERIOD(x) ((x) & (~BITS_AVGPERIOD))
+#define BIT_GET_AVGPERIOD(x) (((x) >> BIT_SHIFT_AVGPERIOD) & BIT_MASK_AVGPERIOD)
+#define BIT_SET_AVGPERIOD(x, v) (BIT_CLEAR_AVGPERIOD(x) | BIT_AVGPERIOD(v))
+
+/* 2 REG_VO_ADMTIME				(Offset 0x05C4) */
+
+#define BIT_SHIFT_VO_ADMITTED_TIME 0
+#define BIT_MASK_VO_ADMITTED_TIME 0xffff
+#define BIT_VO_ADMITTED_TIME(x)                                                \
+	(((x) & BIT_MASK_VO_ADMITTED_TIME) << BIT_SHIFT_VO_ADMITTED_TIME)
+#define BITS_VO_ADMITTED_TIME                                                  \
+	(BIT_MASK_VO_ADMITTED_TIME << BIT_SHIFT_VO_ADMITTED_TIME)
+#define BIT_CLEAR_VO_ADMITTED_TIME(x) ((x) & (~BITS_VO_ADMITTED_TIME))
+#define BIT_GET_VO_ADMITTED_TIME(x)                                            \
+	(((x) >> BIT_SHIFT_VO_ADMITTED_TIME) & BIT_MASK_VO_ADMITTED_TIME)
+#define BIT_SET_VO_ADMITTED_TIME(x, v)                                         \
+	(BIT_CLEAR_VO_ADMITTED_TIME(x) | BIT_VO_ADMITTED_TIME(v))
+
+/* 2 REG_VI_ADMTIME				(Offset 0x05C6) */
+
+#define BIT_SHIFT_VI_ADMITTED_TIME 0
+#define BIT_MASK_VI_ADMITTED_TIME 0xffff
+#define BIT_VI_ADMITTED_TIME(x)                                                \
+	(((x) & BIT_MASK_VI_ADMITTED_TIME) << BIT_SHIFT_VI_ADMITTED_TIME)
+#define BITS_VI_ADMITTED_TIME                                                  \
+	(BIT_MASK_VI_ADMITTED_TIME << BIT_SHIFT_VI_ADMITTED_TIME)
+#define BIT_CLEAR_VI_ADMITTED_TIME(x) ((x) & (~BITS_VI_ADMITTED_TIME))
+#define BIT_GET_VI_ADMITTED_TIME(x)                                            \
+	(((x) >> BIT_SHIFT_VI_ADMITTED_TIME) & BIT_MASK_VI_ADMITTED_TIME)
+#define BIT_SET_VI_ADMITTED_TIME(x, v)                                         \
+	(BIT_CLEAR_VI_ADMITTED_TIME(x) | BIT_VI_ADMITTED_TIME(v))
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_BE_ADMTIME				(Offset 0x05C8) */
+
+#define BIT_PRETX_ERRHDL_EN BIT(15)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_BE_ADMTIME				(Offset 0x05C8) */
+
+#define BIT_SHIFT_BE_ADMITTED_TIME 0
+#define BIT_MASK_BE_ADMITTED_TIME 0xffff
+#define BIT_BE_ADMITTED_TIME(x)                                                \
+	(((x) & BIT_MASK_BE_ADMITTED_TIME) << BIT_SHIFT_BE_ADMITTED_TIME)
+#define BITS_BE_ADMITTED_TIME                                                  \
+	(BIT_MASK_BE_ADMITTED_TIME << BIT_SHIFT_BE_ADMITTED_TIME)
+#define BIT_CLEAR_BE_ADMITTED_TIME(x) ((x) & (~BITS_BE_ADMITTED_TIME))
+#define BIT_GET_BE_ADMITTED_TIME(x)                                            \
+	(((x) >> BIT_SHIFT_BE_ADMITTED_TIME) & BIT_MASK_BE_ADMITTED_TIME)
+#define BIT_SET_BE_ADMITTED_TIME(x, v)                                         \
+	(BIT_CLEAR_BE_ADMITTED_TIME(x) | BIT_BE_ADMITTED_TIME(v))
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_BE_ADMTIME				(Offset 0x05C8) */
+
+#define BIT_SHIFT_MHDR_NAV_OFFSET 0
+#define BIT_MASK_MHDR_NAV_OFFSET 0xff
+#define BIT_MHDR_NAV_OFFSET(x)                                                 \
+	(((x) & BIT_MASK_MHDR_NAV_OFFSET) << BIT_SHIFT_MHDR_NAV_OFFSET)
+#define BITS_MHDR_NAV_OFFSET                                                   \
+	(BIT_MASK_MHDR_NAV_OFFSET << BIT_SHIFT_MHDR_NAV_OFFSET)
+#define BIT_CLEAR_MHDR_NAV_OFFSET(x) ((x) & (~BITS_MHDR_NAV_OFFSET))
+#define BIT_GET_MHDR_NAV_OFFSET(x)                                             \
+	(((x) >> BIT_SHIFT_MHDR_NAV_OFFSET) & BIT_MASK_MHDR_NAV_OFFSET)
+#define BIT_SET_MHDR_NAV_OFFSET(x, v)                                          \
+	(BIT_CLEAR_MHDR_NAV_OFFSET(x) | BIT_MHDR_NAV_OFFSET(v))
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_MAC_HEADER_NAV_OFFSET		(Offset 0x05CA) */
+
+#define BIT_SHIFT_MAC_HEADER_NAV_OFFSET 0
+#define BIT_MASK_MAC_HEADER_NAV_OFFSET 0xff
+#define BIT_MAC_HEADER_NAV_OFFSET(x)                                           \
+	(((x) & BIT_MASK_MAC_HEADER_NAV_OFFSET)                                \
+	 << BIT_SHIFT_MAC_HEADER_NAV_OFFSET)
+#define BITS_MAC_HEADER_NAV_OFFSET                                             \
+	(BIT_MASK_MAC_HEADER_NAV_OFFSET << BIT_SHIFT_MAC_HEADER_NAV_OFFSET)
+#define BIT_CLEAR_MAC_HEADER_NAV_OFFSET(x) ((x) & (~BITS_MAC_HEADER_NAV_OFFSET))
+#define BIT_GET_MAC_HEADER_NAV_OFFSET(x)                                       \
+	(((x) >> BIT_SHIFT_MAC_HEADER_NAV_OFFSET) &                            \
+	 BIT_MASK_MAC_HEADER_NAV_OFFSET)
+#define BIT_SET_MAC_HEADER_NAV_OFFSET(x, v)                                    \
+	(BIT_CLEAR_MAC_HEADER_NAV_OFFSET(x) | BIT_MAC_HEADER_NAV_OFFSET(v))
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_DIS_NDPA_NAV_CHECK			(Offset 0x05CB) */
+
+#define BIT_CHG_POWER_BCN_AREA_V1 BIT(1)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_DIS_NDPA_NAV_CHECK			(Offset 0x05CB) */
+
+#define BIT_DIS_NDPA_NAV_CHECK BIT(0)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_EDCA_RANDOM_GEN			(Offset 0x05CC) */
+
+#define BIT_SHIFT_RANDOM_GEN 0
+#define BIT_MASK_RANDOM_GEN 0xffffff
+#define BIT_RANDOM_GEN(x) (((x) & BIT_MASK_RANDOM_GEN) << BIT_SHIFT_RANDOM_GEN)
+#define BITS_RANDOM_GEN (BIT_MASK_RANDOM_GEN << BIT_SHIFT_RANDOM_GEN)
+#define BIT_CLEAR_RANDOM_GEN(x) ((x) & (~BITS_RANDOM_GEN))
+#define BIT_GET_RANDOM_GEN(x)                                                  \
+	(((x) >> BIT_SHIFT_RANDOM_GEN) & BIT_MASK_RANDOM_GEN)
+#define BIT_SET_RANDOM_GEN(x, v) (BIT_CLEAR_RANDOM_GEN(x) | BIT_RANDOM_GEN(v))
+
+#define BIT_SHIFT_TXCMD_SEG_SEL 0
+#define BIT_MASK_TXCMD_SEG_SEL 0xf
+#define BIT_TXCMD_SEG_SEL(x)                                                   \
+	(((x) & BIT_MASK_TXCMD_SEG_SEL) << BIT_SHIFT_TXCMD_SEG_SEL)
+#define BITS_TXCMD_SEG_SEL (BIT_MASK_TXCMD_SEG_SEL << BIT_SHIFT_TXCMD_SEG_SEL)
+#define BIT_CLEAR_TXCMD_SEG_SEL(x) ((x) & (~BITS_TXCMD_SEG_SEL))
+#define BIT_GET_TXCMD_SEG_SEL(x)                                               \
+	(((x) >> BIT_SHIFT_TXCMD_SEG_SEL) & BIT_MASK_TXCMD_SEG_SEL)
+#define BIT_SET_TXCMD_SEG_SEL(x, v)                                            \
+	(BIT_CLEAR_TXCMD_SEG_SEL(x) | BIT_TXCMD_SEG_SEL(v))
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_TXCMD_NOA_SEL			(Offset 0x05CF) */
+
+#define BIT_SHIFT_EVTQ_EARLY 5
+#define BIT_MASK_EVTQ_EARLY 0x7
+#define BIT_EVTQ_EARLY(x) (((x) & BIT_MASK_EVTQ_EARLY) << BIT_SHIFT_EVTQ_EARLY)
+#define BITS_EVTQ_EARLY (BIT_MASK_EVTQ_EARLY << BIT_SHIFT_EVTQ_EARLY)
+#define BIT_CLEAR_EVTQ_EARLY(x) ((x) & (~BITS_EVTQ_EARLY))
+#define BIT_GET_EVTQ_EARLY(x)                                                  \
+	(((x) >> BIT_SHIFT_EVTQ_EARLY) & BIT_MASK_EVTQ_EARLY)
+#define BIT_SET_EVTQ_EARLY(x, v) (BIT_CLEAR_EVTQ_EARLY(x) | BIT_EVTQ_EARLY(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_TXCMD_NOA_SEL			(Offset 0x05CF) */
+
+#define BIT_NOA_SEL BIT(4)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_TXCMD_NOA_SEL			(Offset 0x05CF) */
+
+#define BIT_SHIFT_NOA_SEL_V2 4
+#define BIT_MASK_NOA_SEL_V2 0x7
+#define BIT_NOA_SEL_V2(x) (((x) & BIT_MASK_NOA_SEL_V2) << BIT_SHIFT_NOA_SEL_V2)
+#define BITS_NOA_SEL_V2 (BIT_MASK_NOA_SEL_V2 << BIT_SHIFT_NOA_SEL_V2)
+#define BIT_CLEAR_NOA_SEL_V2(x) ((x) & (~BITS_NOA_SEL_V2))
+#define BIT_GET_NOA_SEL_V2(x)                                                  \
+	(((x) >> BIT_SHIFT_NOA_SEL_V2) & BIT_MASK_NOA_SEL_V2)
+#define BIT_SET_NOA_SEL_V2(x, v) (BIT_CLEAR_NOA_SEL_V2(x) | BIT_NOA_SEL_V2(v))
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_32K_CLK_SEL				(Offset 0x05D0) */
+
+#define BIT_R_BCNERR_CNT_EN BIT(20)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_DRVERLYINT2				(Offset 0x05D0) */
+
+#define BIT_SHIFT_TSF_DIFF_P1P2 16
+#define BIT_MASK_TSF_DIFF_P1P2 0xffff
+#define BIT_TSF_DIFF_P1P2(x)                                                   \
+	(((x) & BIT_MASK_TSF_DIFF_P1P2) << BIT_SHIFT_TSF_DIFF_P1P2)
+#define BITS_TSF_DIFF_P1P2 (BIT_MASK_TSF_DIFF_P1P2 << BIT_SHIFT_TSF_DIFF_P1P2)
+#define BIT_CLEAR_TSF_DIFF_P1P2(x) ((x) & (~BITS_TSF_DIFF_P1P2))
+#define BIT_GET_TSF_DIFF_P1P2(x)                                               \
+	(((x) >> BIT_SHIFT_TSF_DIFF_P1P2) & BIT_MASK_TSF_DIFF_P1P2)
+#define BIT_SET_TSF_DIFF_P1P2(x, v)                                            \
+	(BIT_CLEAR_TSF_DIFF_P1P2(x) | BIT_TSF_DIFF_P1P2(v))
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_32K_CLK_SEL				(Offset 0x05D0) */
+
+#define BIT_SHIFT_R_BCNERR_PORT_SEL 16
+#define BIT_MASK_R_BCNERR_PORT_SEL 0x7
+#define BIT_R_BCNERR_PORT_SEL(x)                                               \
+	(((x) & BIT_MASK_R_BCNERR_PORT_SEL) << BIT_SHIFT_R_BCNERR_PORT_SEL)
+#define BITS_R_BCNERR_PORT_SEL                                                 \
+	(BIT_MASK_R_BCNERR_PORT_SEL << BIT_SHIFT_R_BCNERR_PORT_SEL)
+#define BIT_CLEAR_R_BCNERR_PORT_SEL(x) ((x) & (~BITS_R_BCNERR_PORT_SEL))
+#define BIT_GET_R_BCNERR_PORT_SEL(x)                                           \
+	(((x) >> BIT_SHIFT_R_BCNERR_PORT_SEL) & BIT_MASK_R_BCNERR_PORT_SEL)
+#define BIT_SET_R_BCNERR_PORT_SEL(x, v)                                        \
+	(BIT_CLEAR_R_BCNERR_PORT_SEL(x) | BIT_R_BCNERR_PORT_SEL(v))
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_DRVERLYINT2				(Offset 0x05D0) */
+
+#define BIT_SHIFT_TXPAUSE1 8
+#define BIT_MASK_TXPAUSE1 0xff
+#define BIT_TXPAUSE1(x) (((x) & BIT_MASK_TXPAUSE1) << BIT_SHIFT_TXPAUSE1)
+#define BITS_TXPAUSE1 (BIT_MASK_TXPAUSE1 << BIT_SHIFT_TXPAUSE1)
+#define BIT_CLEAR_TXPAUSE1(x) ((x) & (~BITS_TXPAUSE1))
+#define BIT_GET_TXPAUSE1(x) (((x) >> BIT_SHIFT_TXPAUSE1) & BIT_MASK_TXPAUSE1)
+#define BIT_SET_TXPAUSE1(x, v) (BIT_CLEAR_TXPAUSE1(x) | BIT_TXPAUSE1(v))
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_32K_CLK_SEL				(Offset 0x05D0) */
+
+#define BIT_SHIFT_R_TXPAUSE1 8
+#define BIT_MASK_R_TXPAUSE1 0xff
+#define BIT_R_TXPAUSE1(x) (((x) & BIT_MASK_R_TXPAUSE1) << BIT_SHIFT_R_TXPAUSE1)
+#define BITS_R_TXPAUSE1 (BIT_MASK_R_TXPAUSE1 << BIT_SHIFT_R_TXPAUSE1)
+#define BIT_CLEAR_R_TXPAUSE1(x) ((x) & (~BITS_R_TXPAUSE1))
+#define BIT_GET_R_TXPAUSE1(x)                                                  \
+	(((x) >> BIT_SHIFT_R_TXPAUSE1) & BIT_MASK_R_TXPAUSE1)
+#define BIT_SET_R_TXPAUSE1(x, v) (BIT_CLEAR_R_TXPAUSE1(x) | BIT_R_TXPAUSE1(v))
+
+#define BIT_SLEEP_32K_EN_V1 BIT(2)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_DRVERLYINT2				(Offset 0x05D0) */
+
+#define BIT_SHIFT_DRVERLYITV2 0
+#define BIT_MASK_DRVERLYITV2 0xff
+#define BIT_DRVERLYITV2(x)                                                     \
+	(((x) & BIT_MASK_DRVERLYITV2) << BIT_SHIFT_DRVERLYITV2)
+#define BITS_DRVERLYITV2 (BIT_MASK_DRVERLYITV2 << BIT_SHIFT_DRVERLYITV2)
+#define BIT_CLEAR_DRVERLYITV2(x) ((x) & (~BITS_DRVERLYITV2))
+#define BIT_GET_DRVERLYITV2(x)                                                 \
+	(((x) >> BIT_SHIFT_DRVERLYITV2) & BIT_MASK_DRVERLYITV2)
+#define BIT_SET_DRVERLYITV2(x, v)                                              \
+	(BIT_CLEAR_DRVERLYITV2(x) | BIT_DRVERLYITV2(v))
+
+/* 2 REG_NAN_SETTING				(Offset 0x05D4) */
+
+#define BIT_EN_MULTI_BCN BIT(31)
+#define BIT_ENP2P_DW_AREA BIT(30)
+
+#define BIT_SHIFT_TBTT_PROHIBIT_HOLD_P2 18
+#define BIT_MASK_TBTT_PROHIBIT_HOLD_P2 0xfff
+#define BIT_TBTT_PROHIBIT_HOLD_P2(x)                                           \
+	(((x) & BIT_MASK_TBTT_PROHIBIT_HOLD_P2)                                \
+	 << BIT_SHIFT_TBTT_PROHIBIT_HOLD_P2)
+#define BITS_TBTT_PROHIBIT_HOLD_P2                                             \
+	(BIT_MASK_TBTT_PROHIBIT_HOLD_P2 << BIT_SHIFT_TBTT_PROHIBIT_HOLD_P2)
+#define BIT_CLEAR_TBTT_PROHIBIT_HOLD_P2(x) ((x) & (~BITS_TBTT_PROHIBIT_HOLD_P2))
+#define BIT_GET_TBTT_PROHIBIT_HOLD_P2(x)                                       \
+	(((x) >> BIT_SHIFT_TBTT_PROHIBIT_HOLD_P2) &                            \
+	 BIT_MASK_TBTT_PROHIBIT_HOLD_P2)
+#define BIT_SET_TBTT_PROHIBIT_HOLD_P2(x, v)                                    \
+	(BIT_CLEAR_TBTT_PROHIBIT_HOLD_P2(x) | BIT_TBTT_PROHIBIT_HOLD_P2(v))
+
+#define BIT_SHIFT_BCN_PORT_PRI 16
+#define BIT_MASK_BCN_PORT_PRI 0x3
+#define BIT_BCN_PORT_PRI(x)                                                    \
+	(((x) & BIT_MASK_BCN_PORT_PRI) << BIT_SHIFT_BCN_PORT_PRI)
+#define BITS_BCN_PORT_PRI (BIT_MASK_BCN_PORT_PRI << BIT_SHIFT_BCN_PORT_PRI)
+#define BIT_CLEAR_BCN_PORT_PRI(x) ((x) & (~BITS_BCN_PORT_PRI))
+#define BIT_GET_BCN_PORT_PRI(x)                                                \
+	(((x) >> BIT_SHIFT_BCN_PORT_PRI) & BIT_MASK_BCN_PORT_PRI)
+#define BIT_SET_BCN_PORT_PRI(x, v)                                             \
+	(BIT_CLEAR_BCN_PORT_PRI(x) | BIT_BCN_PORT_PRI(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_EARLYINT_ADJUST			(Offset 0x05D4) */
+
+#define BIT_SHIFT_RXBCN_TIMER 16
+#define BIT_MASK_RXBCN_TIMER 0xffff
+#define BIT_RXBCN_TIMER(x)                                                     \
+	(((x) & BIT_MASK_RXBCN_TIMER) << BIT_SHIFT_RXBCN_TIMER)
+#define BITS_RXBCN_TIMER (BIT_MASK_RXBCN_TIMER << BIT_SHIFT_RXBCN_TIMER)
+#define BIT_CLEAR_RXBCN_TIMER(x) ((x) & (~BITS_RXBCN_TIMER))
+#define BIT_GET_RXBCN_TIMER(x)                                                 \
+	(((x) >> BIT_SHIFT_RXBCN_TIMER) & BIT_MASK_RXBCN_TIMER)
+#define BIT_SET_RXBCN_TIMER(x, v)                                              \
+	(BIT_CLEAR_RXBCN_TIMER(x) | BIT_RXBCN_TIMER(v))
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_NAN_SETTING				(Offset 0x05D4) */
+
+#define BIT_SHIFT_DRVERLYITV1 8
+#define BIT_MASK_DRVERLYITV1 0xff
+#define BIT_DRVERLYITV1(x)                                                     \
+	(((x) & BIT_MASK_DRVERLYITV1) << BIT_SHIFT_DRVERLYITV1)
+#define BITS_DRVERLYITV1 (BIT_MASK_DRVERLYITV1 << BIT_SHIFT_DRVERLYITV1)
+#define BIT_CLEAR_DRVERLYITV1(x) ((x) & (~BITS_DRVERLYITV1))
+#define BIT_GET_DRVERLYITV1(x)                                                 \
+	(((x) >> BIT_SHIFT_DRVERLYITV1) & BIT_MASK_DRVERLYITV1)
+#define BIT_SET_DRVERLYITV1(x, v)                                              \
+	(BIT_CLEAR_DRVERLYITV1(x) | BIT_DRVERLYITV1(v))
+
+#define BIT_DIS_RX_BSSID_FIT2 BIT(6)
+#define BIT_DIS_TSF2_UDT BIT(4)
+#define BIT_EN_BCN2_FUNCTION BIT(3)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_EARLYINT_ADJUST			(Offset 0x05D4) */
+
+#define BIT_SHIFT_R_ERLYINTADJ 0
+#define BIT_MASK_R_ERLYINTADJ 0xffff
+#define BIT_R_ERLYINTADJ(x)                                                    \
+	(((x) & BIT_MASK_R_ERLYINTADJ) << BIT_SHIFT_R_ERLYINTADJ)
+#define BITS_R_ERLYINTADJ (BIT_MASK_R_ERLYINTADJ << BIT_SHIFT_R_ERLYINTADJ)
+#define BIT_CLEAR_R_ERLYINTADJ(x) ((x) & (~BITS_R_ERLYINTADJ))
+#define BIT_GET_R_ERLYINTADJ(x)                                                \
+	(((x) >> BIT_SHIFT_R_ERLYINTADJ) & BIT_MASK_R_ERLYINTADJ)
+#define BIT_SET_R_ERLYINTADJ(x, v)                                             \
+	(BIT_CLEAR_R_ERLYINTADJ(x) | BIT_R_ERLYINTADJ(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_BCNERR_CNT				(Offset 0x05D8) */
+
+#define BIT_SHIFT_BCNERR_CNT_OTHERS 24
+#define BIT_MASK_BCNERR_CNT_OTHERS 0xff
+#define BIT_BCNERR_CNT_OTHERS(x)                                               \
+	(((x) & BIT_MASK_BCNERR_CNT_OTHERS) << BIT_SHIFT_BCNERR_CNT_OTHERS)
+#define BITS_BCNERR_CNT_OTHERS                                                 \
+	(BIT_MASK_BCNERR_CNT_OTHERS << BIT_SHIFT_BCNERR_CNT_OTHERS)
+#define BIT_CLEAR_BCNERR_CNT_OTHERS(x) ((x) & (~BITS_BCNERR_CNT_OTHERS))
+#define BIT_GET_BCNERR_CNT_OTHERS(x)                                           \
+	(((x) >> BIT_SHIFT_BCNERR_CNT_OTHERS) & BIT_MASK_BCNERR_CNT_OTHERS)
+#define BIT_SET_BCNERR_CNT_OTHERS(x, v)                                        \
+	(BIT_CLEAR_BCNERR_CNT_OTHERS(x) | BIT_BCNERR_CNT_OTHERS(v))
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_NAN_BCNSPACE			(Offset 0x05D8) */
+
+#define BIT_SHIFT_BCN_SPACE4 16
+#define BIT_MASK_BCN_SPACE4 0xffff
+#define BIT_BCN_SPACE4(x) (((x) & BIT_MASK_BCN_SPACE4) << BIT_SHIFT_BCN_SPACE4)
+#define BITS_BCN_SPACE4 (BIT_MASK_BCN_SPACE4 << BIT_SHIFT_BCN_SPACE4)
+#define BIT_CLEAR_BCN_SPACE4(x) ((x) & (~BITS_BCN_SPACE4))
+#define BIT_GET_BCN_SPACE4(x)                                                  \
+	(((x) >> BIT_SHIFT_BCN_SPACE4) & BIT_MASK_BCN_SPACE4)
+#define BIT_SET_BCN_SPACE4(x, v) (BIT_CLEAR_BCN_SPACE4(x) | BIT_BCN_SPACE4(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_BCNERR_CNT				(Offset 0x05D8) */
+
+#define BIT_SHIFT_BCNERR_CNT_INVALID 16
+#define BIT_MASK_BCNERR_CNT_INVALID 0xff
+#define BIT_BCNERR_CNT_INVALID(x)                                              \
+	(((x) & BIT_MASK_BCNERR_CNT_INVALID) << BIT_SHIFT_BCNERR_CNT_INVALID)
+#define BITS_BCNERR_CNT_INVALID                                                \
+	(BIT_MASK_BCNERR_CNT_INVALID << BIT_SHIFT_BCNERR_CNT_INVALID)
+#define BIT_CLEAR_BCNERR_CNT_INVALID(x) ((x) & (~BITS_BCNERR_CNT_INVALID))
+#define BIT_GET_BCNERR_CNT_INVALID(x)                                          \
+	(((x) >> BIT_SHIFT_BCNERR_CNT_INVALID) & BIT_MASK_BCNERR_CNT_INVALID)
+#define BIT_SET_BCNERR_CNT_INVALID(x, v)                                       \
+	(BIT_CLEAR_BCNERR_CNT_INVALID(x) | BIT_BCNERR_CNT_INVALID(v))
+
+#define BIT_SHIFT_BCNERR_CNT_MAC 8
+#define BIT_MASK_BCNERR_CNT_MAC 0xff
+#define BIT_BCNERR_CNT_MAC(x)                                                  \
+	(((x) & BIT_MASK_BCNERR_CNT_MAC) << BIT_SHIFT_BCNERR_CNT_MAC)
+#define BITS_BCNERR_CNT_MAC                                                    \
+	(BIT_MASK_BCNERR_CNT_MAC << BIT_SHIFT_BCNERR_CNT_MAC)
+#define BIT_CLEAR_BCNERR_CNT_MAC(x) ((x) & (~BITS_BCNERR_CNT_MAC))
+#define BIT_GET_BCNERR_CNT_MAC(x)                                              \
+	(((x) >> BIT_SHIFT_BCNERR_CNT_MAC) & BIT_MASK_BCNERR_CNT_MAC)
+#define BIT_SET_BCNERR_CNT_MAC(x, v)                                           \
+	(BIT_CLEAR_BCNERR_CNT_MAC(x) | BIT_BCNERR_CNT_MAC(v))
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_NAN_BCNSPACE			(Offset 0x05D8) */
+
+#define BIT_SHIFT_BCN_SPACE3 0
+#define BIT_MASK_BCN_SPACE3 0xffff
+#define BIT_BCN_SPACE3(x) (((x) & BIT_MASK_BCN_SPACE3) << BIT_SHIFT_BCN_SPACE3)
+#define BITS_BCN_SPACE3 (BIT_MASK_BCN_SPACE3 << BIT_SHIFT_BCN_SPACE3)
+#define BIT_CLEAR_BCN_SPACE3(x) ((x) & (~BITS_BCN_SPACE3))
+#define BIT_GET_BCN_SPACE3(x)                                                  \
+	(((x) >> BIT_SHIFT_BCN_SPACE3) & BIT_MASK_BCN_SPACE3)
+#define BIT_SET_BCN_SPACE3(x, v) (BIT_CLEAR_BCN_SPACE3(x) | BIT_BCN_SPACE3(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_BCNERR_CNT				(Offset 0x05D8) */
+
+#define BIT_SHIFT_BCNERR_CNT_CCA 0
+#define BIT_MASK_BCNERR_CNT_CCA 0xff
+#define BIT_BCNERR_CNT_CCA(x)                                                  \
+	(((x) & BIT_MASK_BCNERR_CNT_CCA) << BIT_SHIFT_BCNERR_CNT_CCA)
+#define BITS_BCNERR_CNT_CCA                                                    \
+	(BIT_MASK_BCNERR_CNT_CCA << BIT_SHIFT_BCNERR_CNT_CCA)
+#define BIT_CLEAR_BCNERR_CNT_CCA(x) ((x) & (~BITS_BCNERR_CNT_CCA))
+#define BIT_GET_BCNERR_CNT_CCA(x)                                              \
+	(((x) >> BIT_SHIFT_BCNERR_CNT_CCA) & BIT_MASK_BCNERR_CNT_CCA)
+#define BIT_SET_BCNERR_CNT_CCA(x, v)                                           \
+	(BIT_CLEAR_BCNERR_CNT_CCA(x) | BIT_BCNERR_CNT_CCA(v))
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_NAN_SETTING1			(Offset 0x05DC) */
+
+#define BIT_SHIFT_SYNCBCN_RXNUM 27
+#define BIT_MASK_SYNCBCN_RXNUM 0x1f
+#define BIT_SYNCBCN_RXNUM(x)                                                   \
+	(((x) & BIT_MASK_SYNCBCN_RXNUM) << BIT_SHIFT_SYNCBCN_RXNUM)
+#define BITS_SYNCBCN_RXNUM (BIT_MASK_SYNCBCN_RXNUM << BIT_SHIFT_SYNCBCN_RXNUM)
+#define BIT_CLEAR_SYNCBCN_RXNUM(x) ((x) & (~BITS_SYNCBCN_RXNUM))
+#define BIT_GET_SYNCBCN_RXNUM(x)                                               \
+	(((x) >> BIT_SHIFT_SYNCBCN_RXNUM) & BIT_MASK_SYNCBCN_RXNUM)
+#define BIT_SET_SYNCBCN_RXNUM(x, v)                                            \
+	(BIT_CLEAR_SYNCBCN_RXNUM(x) | BIT_SYNCBCN_RXNUM(v))
+
+#define BIT_DW_END_EARLY BIT(26)
+
+#define BIT_SHIFT_NAN_ROLE 24
+#define BIT_MASK_NAN_ROLE 0x3
+#define BIT_NAN_ROLE(x) (((x) & BIT_MASK_NAN_ROLE) << BIT_SHIFT_NAN_ROLE)
+#define BITS_NAN_ROLE (BIT_MASK_NAN_ROLE << BIT_SHIFT_NAN_ROLE)
+#define BIT_CLEAR_NAN_ROLE(x) ((x) & (~BITS_NAN_ROLE))
+#define BIT_GET_NAN_ROLE(x) (((x) >> BIT_SHIFT_NAN_ROLE) & BIT_MASK_NAN_ROLE)
+#define BIT_SET_NAN_ROLE(x, v) (BIT_CLEAR_NAN_ROLE(x) | BIT_NAN_ROLE(v))
+
+#define BIT_SHIFT_MSLOT_EVTQ 16
+#define BIT_MASK_MSLOT_EVTQ 0xff
+#define BIT_MSLOT_EVTQ(x) (((x) & BIT_MASK_MSLOT_EVTQ) << BIT_SHIFT_MSLOT_EVTQ)
+#define BITS_MSLOT_EVTQ (BIT_MASK_MSLOT_EVTQ << BIT_SHIFT_MSLOT_EVTQ)
+#define BIT_CLEAR_MSLOT_EVTQ(x) ((x) & (~BITS_MSLOT_EVTQ))
+#define BIT_GET_MSLOT_EVTQ(x)                                                  \
+	(((x) >> BIT_SHIFT_MSLOT_EVTQ) & BIT_MASK_MSLOT_EVTQ)
+#define BIT_SET_MSLOT_EVTQ(x, v) (BIT_CLEAR_MSLOT_EVTQ(x) | BIT_MSLOT_EVTQ(v))
+
+#define BIT_SHIFT_MDW_EVTQ 8
+#define BIT_MASK_MDW_EVTQ 0xff
+#define BIT_MDW_EVTQ(x) (((x) & BIT_MASK_MDW_EVTQ) << BIT_SHIFT_MDW_EVTQ)
+#define BITS_MDW_EVTQ (BIT_MASK_MDW_EVTQ << BIT_SHIFT_MDW_EVTQ)
+#define BIT_CLEAR_MDW_EVTQ(x) ((x) & (~BITS_MDW_EVTQ))
+#define BIT_GET_MDW_EVTQ(x) (((x) >> BIT_SHIFT_MDW_EVTQ) & BIT_MASK_MDW_EVTQ)
+#define BIT_SET_MDW_EVTQ(x, v) (BIT_CLEAR_MDW_EVTQ(x) | BIT_MDW_EVTQ(v))
+
+#define BIT_SHIFT_HC 0
+#define BIT_MASK_HC 0xff
+#define BIT_HC(x) (((x) & BIT_MASK_HC) << BIT_SHIFT_HC)
+#define BITS_HC (BIT_MASK_HC << BIT_SHIFT_HC)
+#define BIT_CLEAR_HC(x) ((x) & (~BITS_HC))
+#define BIT_GET_HC(x) (((x) >> BIT_SHIFT_HC) & BIT_MASK_HC)
+#define BIT_SET_HC(x, v) (BIT_CLEAR_HC(x) | BIT_HC(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT || \
+     HALMAC_8881A_SUPPORT)
+
+/* 2 REG_NOA_PARAM				(Offset 0x05E0) */
+
+#define BIT_SHIFT_NOA_COUNT (96 & CPU_OPT_WIDTH)
+#define BIT_MASK_NOA_COUNT 0xff
+#define BIT_NOA_COUNT(x) (((x) & BIT_MASK_NOA_COUNT) << BIT_SHIFT_NOA_COUNT)
+#define BITS_NOA_COUNT (BIT_MASK_NOA_COUNT << BIT_SHIFT_NOA_COUNT)
+#define BIT_CLEAR_NOA_COUNT(x) ((x) & (~BITS_NOA_COUNT))
+#define BIT_GET_NOA_COUNT(x) (((x) >> BIT_SHIFT_NOA_COUNT) & BIT_MASK_NOA_COUNT)
+#define BIT_SET_NOA_COUNT(x, v) (BIT_CLEAR_NOA_COUNT(x) | BIT_NOA_COUNT(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_NOA_PARAM				(Offset 0x05E0) */
+
+#define BIT_SHIFT_NOA_DURATION 0
+#define BIT_MASK_NOA_DURATION 0xffffffffL
+#define BIT_NOA_DURATION(x)                                                    \
+	(((x) & BIT_MASK_NOA_DURATION) << BIT_SHIFT_NOA_DURATION)
+#define BITS_NOA_DURATION (BIT_MASK_NOA_DURATION << BIT_SHIFT_NOA_DURATION)
+#define BIT_CLEAR_NOA_DURATION(x) ((x) & (~BITS_NOA_DURATION))
+#define BIT_GET_NOA_DURATION(x)                                                \
+	(((x) >> BIT_SHIFT_NOA_DURATION) & BIT_MASK_NOA_DURATION)
+#define BIT_SET_NOA_DURATION(x, v)                                             \
+	(BIT_CLEAR_NOA_DURATION(x) | BIT_NOA_DURATION(v))
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_NOA_PARAM				(Offset 0x05E0) */
+
+#define BIT_SHIFT_NOA_DURATION_V1 0
+#define BIT_MASK_NOA_DURATION_V1 0xffffffffL
+#define BIT_NOA_DURATION_V1(x)                                                 \
+	(((x) & BIT_MASK_NOA_DURATION_V1) << BIT_SHIFT_NOA_DURATION_V1)
+#define BITS_NOA_DURATION_V1                                                   \
+	(BIT_MASK_NOA_DURATION_V1 << BIT_SHIFT_NOA_DURATION_V1)
+#define BIT_CLEAR_NOA_DURATION_V1(x) ((x) & (~BITS_NOA_DURATION_V1))
+#define BIT_GET_NOA_DURATION_V1(x)                                             \
+	(((x) >> BIT_SHIFT_NOA_DURATION_V1) & BIT_MASK_NOA_DURATION_V1)
+#define BIT_SET_NOA_DURATION_V1(x, v)                                          \
+	(BIT_CLEAR_NOA_DURATION_V1(x) | BIT_NOA_DURATION_V1(v))
+
+/* 2 REG_NOA_PARAM_1				(Offset 0x05E4) */
+
+#define BIT_SHIFT_NOA_INTERVAL_V1 0
+#define BIT_MASK_NOA_INTERVAL_V1 0xffffffffL
+#define BIT_NOA_INTERVAL_V1(x)                                                 \
+	(((x) & BIT_MASK_NOA_INTERVAL_V1) << BIT_SHIFT_NOA_INTERVAL_V1)
+#define BITS_NOA_INTERVAL_V1                                                   \
+	(BIT_MASK_NOA_INTERVAL_V1 << BIT_SHIFT_NOA_INTERVAL_V1)
+#define BIT_CLEAR_NOA_INTERVAL_V1(x) ((x) & (~BITS_NOA_INTERVAL_V1))
+#define BIT_GET_NOA_INTERVAL_V1(x)                                             \
+	(((x) >> BIT_SHIFT_NOA_INTERVAL_V1) & BIT_MASK_NOA_INTERVAL_V1)
+#define BIT_SET_NOA_INTERVAL_V1(x, v)                                          \
+	(BIT_CLEAR_NOA_INTERVAL_V1(x) | BIT_NOA_INTERVAL_V1(v))
+
+/* 2 REG_NOA_PARAM_2				(Offset 0x05E8) */
+
+#define BIT_SHIFT_NOA_START_TIME_V1 0
+#define BIT_MASK_NOA_START_TIME_V1 0xffffffffL
+#define BIT_NOA_START_TIME_V1(x)                                               \
+	(((x) & BIT_MASK_NOA_START_TIME_V1) << BIT_SHIFT_NOA_START_TIME_V1)
+#define BITS_NOA_START_TIME_V1                                                 \
+	(BIT_MASK_NOA_START_TIME_V1 << BIT_SHIFT_NOA_START_TIME_V1)
+#define BIT_CLEAR_NOA_START_TIME_V1(x) ((x) & (~BITS_NOA_START_TIME_V1))
+#define BIT_GET_NOA_START_TIME_V1(x)                                           \
+	(((x) >> BIT_SHIFT_NOA_START_TIME_V1) & BIT_MASK_NOA_START_TIME_V1)
+#define BIT_SET_NOA_START_TIME_V1(x, v)                                        \
+	(BIT_CLEAR_NOA_START_TIME_V1(x) | BIT_NOA_START_TIME_V1(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_MU_DBG_INFO				(Offset 0x05E8) */
+
+#define BIT_SHIFT_MU_DBG_INFO 0
+#define BIT_MASK_MU_DBG_INFO 0xffffffffL
+#define BIT_MU_DBG_INFO(x)                                                     \
+	(((x) & BIT_MASK_MU_DBG_INFO) << BIT_SHIFT_MU_DBG_INFO)
+#define BITS_MU_DBG_INFO (BIT_MASK_MU_DBG_INFO << BIT_SHIFT_MU_DBG_INFO)
+#define BIT_CLEAR_MU_DBG_INFO(x) ((x) & (~BITS_MU_DBG_INFO))
+#define BIT_GET_MU_DBG_INFO(x)                                                 \
+	(((x) >> BIT_SHIFT_MU_DBG_INFO) & BIT_MASK_MU_DBG_INFO)
+#define BIT_SET_MU_DBG_INFO(x, v)                                              \
+	(BIT_CLEAR_MU_DBG_INFO(x) | BIT_MU_DBG_INFO(v))
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_NOA_PARAM_3				(Offset 0x05EC) */
+
+#define BIT_SHIFT_NOA_COUNT_V3 0
+#define BIT_MASK_NOA_COUNT_V3 0xff
+#define BIT_NOA_COUNT_V3(x)                                                    \
+	(((x) & BIT_MASK_NOA_COUNT_V3) << BIT_SHIFT_NOA_COUNT_V3)
+#define BITS_NOA_COUNT_V3 (BIT_MASK_NOA_COUNT_V3 << BIT_SHIFT_NOA_COUNT_V3)
+#define BIT_CLEAR_NOA_COUNT_V3(x) ((x) & (~BITS_NOA_COUNT_V3))
+#define BIT_GET_NOA_COUNT_V3(x)                                                \
+	(((x) >> BIT_SHIFT_NOA_COUNT_V3) & BIT_MASK_NOA_COUNT_V3)
+#define BIT_SET_NOA_COUNT_V3(x, v)                                             \
+	(BIT_CLEAR_NOA_COUNT_V3(x) | BIT_NOA_COUNT_V3(v))
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_NOA_PARAM_3				(Offset 0x05EC) */
+
+#define BIT_SHIFT_NOA_COUNT_V1 0
+#define BIT_MASK_NOA_COUNT_V1 0xffffffffL
+#define BIT_NOA_COUNT_V1(x)                                                    \
+	(((x) & BIT_MASK_NOA_COUNT_V1) << BIT_SHIFT_NOA_COUNT_V1)
+#define BITS_NOA_COUNT_V1 (BIT_MASK_NOA_COUNT_V1 << BIT_SHIFT_NOA_COUNT_V1)
+#define BIT_CLEAR_NOA_COUNT_V1(x) ((x) & (~BITS_NOA_COUNT_V1))
+#define BIT_GET_NOA_COUNT_V1(x)                                                \
+	(((x) >> BIT_SHIFT_NOA_COUNT_V1) & BIT_MASK_NOA_COUNT_V1)
+#define BIT_SET_NOA_COUNT_V1(x, v)                                             \
+	(BIT_CLEAR_NOA_COUNT_V1(x) | BIT_NOA_COUNT_V1(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_MU_DBG_INFO_1			(Offset 0x05EC) */
+
+#define BIT_SHIFT_MU_DBG_INFO_1 0
+#define BIT_MASK_MU_DBG_INFO_1 0xffffffffL
+#define BIT_MU_DBG_INFO_1(x)                                                   \
+	(((x) & BIT_MASK_MU_DBG_INFO_1) << BIT_SHIFT_MU_DBG_INFO_1)
+#define BITS_MU_DBG_INFO_1 (BIT_MASK_MU_DBG_INFO_1 << BIT_SHIFT_MU_DBG_INFO_1)
+#define BIT_CLEAR_MU_DBG_INFO_1(x) ((x) & (~BITS_MU_DBG_INFO_1))
+#define BIT_GET_MU_DBG_INFO_1(x)                                               \
+	(((x) >> BIT_SHIFT_MU_DBG_INFO_1) & BIT_MASK_MU_DBG_INFO_1)
+#define BIT_SET_MU_DBG_INFO_1(x, v)                                            \
+	(BIT_CLEAR_MU_DBG_INFO_1(x) | BIT_MU_DBG_INFO_1(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_NOA_SUBIE				(Offset 0x05ED) */
+
+#define BIT_MORE_NOA_DESC BIT(19)
+#define BIT_NOA_DESC1_VALID BIT(18)
+#define BIT_NOA_DESC0_VALID BIT(17)
+#define BIT_NOA_HEAD_VALID BIT(16)
+#define BIT_NOA_OPP_PS BIT(15)
+
+#define BIT_SHIFT_NOA_CTW 8
+#define BIT_MASK_NOA_CTW 0x7f
+#define BIT_NOA_CTW(x) (((x) & BIT_MASK_NOA_CTW) << BIT_SHIFT_NOA_CTW)
+#define BITS_NOA_CTW (BIT_MASK_NOA_CTW << BIT_SHIFT_NOA_CTW)
+#define BIT_CLEAR_NOA_CTW(x) ((x) & (~BITS_NOA_CTW))
+#define BIT_GET_NOA_CTW(x) (((x) >> BIT_SHIFT_NOA_CTW) & BIT_MASK_NOA_CTW)
+#define BIT_SET_NOA_CTW(x, v) (BIT_CLEAR_NOA_CTW(x) | BIT_NOA_CTW(v))
+
+#define BIT_SHIFT_NOA_INDEX 0
+#define BIT_MASK_NOA_INDEX 0xff
+#define BIT_NOA_INDEX(x) (((x) & BIT_MASK_NOA_INDEX) << BIT_SHIFT_NOA_INDEX)
+#define BITS_NOA_INDEX (BIT_MASK_NOA_INDEX << BIT_SHIFT_NOA_INDEX)
+#define BIT_CLEAR_NOA_INDEX(x) ((x) & (~BITS_NOA_INDEX))
+#define BIT_GET_NOA_INDEX(x) (((x) >> BIT_SHIFT_NOA_INDEX) & BIT_MASK_NOA_INDEX)
+#define BIT_SET_NOA_INDEX(x, v) (BIT_CLEAR_NOA_INDEX(x) | BIT_NOA_INDEX(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_P2P_RST				(Offset 0x05F0) */
+
+#define BIT_P2P2_PWR_RST1 BIT(5)
+#define BIT_P2P2_PWR_RST0 BIT(4)
+#define BIT_P2P1_PWR_RST1 BIT(3)
+#define BIT_P2P1_PWR_RST0 BIT(2)
+#define BIT_P2P_PWR_RST1_V1 BIT(1)
+#define BIT_P2P_PWR_RST0_V1 BIT(0)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_SCH_DBG_SEL				(Offset 0x05F0) */
+
+#define BIT_SHIFT_SCH_DBG_SEL 0
+#define BIT_MASK_SCH_DBG_SEL 0xff
+#define BIT_SCH_DBG_SEL(x)                                                     \
+	(((x) & BIT_MASK_SCH_DBG_SEL) << BIT_SHIFT_SCH_DBG_SEL)
+#define BITS_SCH_DBG_SEL (BIT_MASK_SCH_DBG_SEL << BIT_SHIFT_SCH_DBG_SEL)
+#define BIT_CLEAR_SCH_DBG_SEL(x) ((x) & (~BITS_SCH_DBG_SEL))
+#define BIT_GET_SCH_DBG_SEL(x)                                                 \
+	(((x) >> BIT_SHIFT_SCH_DBG_SEL) & BIT_MASK_SCH_DBG_SEL)
+#define BIT_SET_SCH_DBG_SEL(x, v)                                              \
+	(BIT_CLEAR_SCH_DBG_SEL(x) | BIT_SCH_DBG_SEL(v))
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_SCHEDULER_RST			(Offset 0x05F1) */
+
+#define BIT_MAC_STOP_CPUMGQ BIT(16)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_SCHEDULER_RST			(Offset 0x05F1) */
+
+#define BIT_SYNC_TSF_NOW BIT(2)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_SCHEDULER_RST			(Offset 0x05F1) */
+
+#define BIT_SYNC_CLI_ONCE_RIGHT_NOW BIT(2)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_SCHEDULER_RST			(Offset 0x05F1) */
+
+#define BIT_EN_P2P_CTWINDOW BIT(1)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_SCHEDULER_RST			(Offset 0x05F1) */
+
+#define BIT_SYNC_CLI BIT(1)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_SCHEDULER_RST			(Offset 0x05F1) */
+
+#define BIT_SYNC_CLI_ONCE_BY_TBTT BIT(1)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_SCHEDULER_RST			(Offset 0x05F1) */
+
+#define BIT_SCHEDULER_RST_V1 BIT(0)
+#define BIT_EN_P2P_BCNQ_AREA BIT(0)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_MU_DBG_ERR_FLAG			(Offset 0x05F2) */
+
+#define BIT_BCN_PORTID_ERR BIT(2)
+
+#define BIT_SHIFT_MU_DBG_ERR_FLAG 0
+#define BIT_MASK_MU_DBG_ERR_FLAG 0x3
+#define BIT_MU_DBG_ERR_FLAG(x)                                                 \
+	(((x) & BIT_MASK_MU_DBG_ERR_FLAG) << BIT_SHIFT_MU_DBG_ERR_FLAG)
+#define BITS_MU_DBG_ERR_FLAG                                                   \
+	(BIT_MASK_MU_DBG_ERR_FLAG << BIT_SHIFT_MU_DBG_ERR_FLAG)
+#define BIT_CLEAR_MU_DBG_ERR_FLAG(x) ((x) & (~BITS_MU_DBG_ERR_FLAG))
+#define BIT_GET_MU_DBG_ERR_FLAG(x)                                             \
+	(((x) >> BIT_SHIFT_MU_DBG_ERR_FLAG) & BIT_MASK_MU_DBG_ERR_FLAG)
+#define BIT_SET_MU_DBG_ERR_FLAG(x, v)                                          \
+	(BIT_CLEAR_MU_DBG_ERR_FLAG(x) | BIT_MU_DBG_ERR_FLAG(v))
+
+/* 2 REG_TX_ERR_RECOVERY_RST			(Offset 0x05F3) */
+
+#define BIT_SHIFT_ERR_RECOVER_CNT 4
+#define BIT_MASK_ERR_RECOVER_CNT 0xf
+#define BIT_ERR_RECOVER_CNT(x)                                                 \
+	(((x) & BIT_MASK_ERR_RECOVER_CNT) << BIT_SHIFT_ERR_RECOVER_CNT)
+#define BITS_ERR_RECOVER_CNT                                                   \
+	(BIT_MASK_ERR_RECOVER_CNT << BIT_SHIFT_ERR_RECOVER_CNT)
+#define BIT_CLEAR_ERR_RECOVER_CNT(x) ((x) & (~BITS_ERR_RECOVER_CNT))
+#define BIT_GET_ERR_RECOVER_CNT(x)                                             \
+	(((x) >> BIT_SHIFT_ERR_RECOVER_CNT) & BIT_MASK_ERR_RECOVER_CNT)
+#define BIT_SET_ERR_RECOVER_CNT(x, v)                                          \
+	(BIT_CLEAR_ERR_RECOVER_CNT(x) | BIT_ERR_RECOVER_CNT(v))
+
+#define BIT_RX_HANG_ERR BIT(2)
+#define BIT_TX_HANG_ERR BIT(1)
+#define BIT_TX_ERR_RECOVERY_RST BIT(0)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_SCH_DBG				(Offset 0x05F4) */
+
+#define BIT_SHIFT_SCH_DBG 0
+#define BIT_MASK_SCH_DBG 0xffffffffL
+#define BIT_SCH_DBG(x) (((x) & BIT_MASK_SCH_DBG) << BIT_SHIFT_SCH_DBG)
+#define BITS_SCH_DBG (BIT_MASK_SCH_DBG << BIT_SHIFT_SCH_DBG)
+#define BIT_CLEAR_SCH_DBG(x) ((x) & (~BITS_SCH_DBG))
+#define BIT_GET_SCH_DBG(x) (((x) >> BIT_SHIFT_SCH_DBG) & BIT_MASK_SCH_DBG)
+#define BIT_SET_SCH_DBG(x, v) (BIT_CLEAR_SCH_DBG(x) | BIT_SCH_DBG(v))
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_SCH_DBG_VALUE			(Offset 0x05F4) */
+
+#define BIT_SHIFT_SCH_DBG_VALUE 0
+#define BIT_MASK_SCH_DBG_VALUE 0xffffffffL
+#define BIT_SCH_DBG_VALUE(x)                                                   \
+	(((x) & BIT_MASK_SCH_DBG_VALUE) << BIT_SHIFT_SCH_DBG_VALUE)
+#define BITS_SCH_DBG_VALUE (BIT_MASK_SCH_DBG_VALUE << BIT_SHIFT_SCH_DBG_VALUE)
+#define BIT_CLEAR_SCH_DBG_VALUE(x) ((x) & (~BITS_SCH_DBG_VALUE))
+#define BIT_GET_SCH_DBG_VALUE(x)                                               \
+	(((x) >> BIT_SHIFT_SCH_DBG_VALUE) & BIT_MASK_SCH_DBG_VALUE)
+#define BIT_SET_SCH_DBG_VALUE(x, v)                                            \
+	(BIT_CLEAR_SCH_DBG_VALUE(x) | BIT_SCH_DBG_VALUE(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_SCH_TXCMD				(Offset 0x05F8) */
+
+#define BIT_DIS_RX_BSSID_FIT BIT(6)
+#define BIT_DIS_TSF_UDT BIT(4)
+
+#define BIT_SHIFT_SCH_TXCMD 0
+#define BIT_MASK_SCH_TXCMD 0xffffffffL
+#define BIT_SCH_TXCMD(x) (((x) & BIT_MASK_SCH_TXCMD) << BIT_SHIFT_SCH_TXCMD)
+#define BITS_SCH_TXCMD (BIT_MASK_SCH_TXCMD << BIT_SHIFT_SCH_TXCMD)
+#define BIT_CLEAR_SCH_TXCMD(x) ((x) & (~BITS_SCH_TXCMD))
+#define BIT_GET_SCH_TXCMD(x) (((x) >> BIT_SHIFT_SCH_TXCMD) & BIT_MASK_SCH_TXCMD)
+#define BIT_SET_SCH_TXCMD(x, v) (BIT_CLEAR_SCH_TXCMD(x) | BIT_SCH_TXCMD(v))
+
+#define BIT_SHIFT_TBTT_PROHIBIT_SETUP 0
+#define BIT_MASK_TBTT_PROHIBIT_SETUP 0xf
+#define BIT_TBTT_PROHIBIT_SETUP(x)                                             \
+	(((x) & BIT_MASK_TBTT_PROHIBIT_SETUP) << BIT_SHIFT_TBTT_PROHIBIT_SETUP)
+#define BITS_TBTT_PROHIBIT_SETUP                                               \
+	(BIT_MASK_TBTT_PROHIBIT_SETUP << BIT_SHIFT_TBTT_PROHIBIT_SETUP)
+#define BIT_CLEAR_TBTT_PROHIBIT_SETUP(x) ((x) & (~BITS_TBTT_PROHIBIT_SETUP))
+#define BIT_GET_TBTT_PROHIBIT_SETUP(x)                                         \
+	(((x) >> BIT_SHIFT_TBTT_PROHIBIT_SETUP) & BIT_MASK_TBTT_PROHIBIT_SETUP)
+#define BIT_SET_TBTT_PROHIBIT_SETUP(x, v)                                      \
+	(BIT_CLEAR_TBTT_PROHIBIT_SETUP(x) | BIT_TBTT_PROHIBIT_SETUP(v))
+
+#define BIT_SHIFT_DRVERLYITV 0
+#define BIT_MASK_DRVERLYITV 0xff
+#define BIT_DRVERLYITV(x) (((x) & BIT_MASK_DRVERLYITV) << BIT_SHIFT_DRVERLYITV)
+#define BITS_DRVERLYITV (BIT_MASK_DRVERLYITV << BIT_SHIFT_DRVERLYITV)
+#define BIT_CLEAR_DRVERLYITV(x) ((x) & (~BITS_DRVERLYITV))
+#define BIT_GET_DRVERLYITV(x)                                                  \
+	(((x) >> BIT_SHIFT_DRVERLYITV) & BIT_MASK_DRVERLYITV)
+#define BIT_SET_DRVERLYITV(x, v) (BIT_CLEAR_DRVERLYITV(x) | BIT_DRVERLYITV(v))
+
+#define BIT_SHIFT_BCNDMATIM 0
+#define BIT_MASK_BCNDMATIM 0xff
+#define BIT_BCNDMATIM(x) (((x) & BIT_MASK_BCNDMATIM) << BIT_SHIFT_BCNDMATIM)
+#define BITS_BCNDMATIM (BIT_MASK_BCNDMATIM << BIT_SHIFT_BCNDMATIM)
+#define BIT_CLEAR_BCNDMATIM(x) ((x) & (~BITS_BCNDMATIM))
+#define BIT_GET_BCNDMATIM(x) (((x) >> BIT_SHIFT_BCNDMATIM) & BIT_MASK_BCNDMATIM)
+#define BIT_SET_BCNDMATIM(x, v) (BIT_CLEAR_BCNDMATIM(x) | BIT_BCNDMATIM(v))
+
+#define BIT_SHIFT_CTWND 0
+#define BIT_MASK_CTWND 0xff
+#define BIT_CTWND(x) (((x) & BIT_MASK_CTWND) << BIT_SHIFT_CTWND)
+#define BITS_CTWND (BIT_MASK_CTWND << BIT_SHIFT_CTWND)
+#define BIT_CLEAR_CTWND(x) ((x) & (~BITS_CTWND))
+#define BIT_GET_CTWND(x) (((x) >> BIT_SHIFT_CTWND) & BIT_MASK_CTWND)
+#define BIT_SET_CTWND(x, v) (BIT_CLEAR_CTWND(x) | BIT_CTWND(v))
+
+#endif
+
+#if (HALMAC_8821C_SUPPORT)
+
+/* 2 REG_PAGE5_DUMMY				(Offset 0x05FC) */
+
+#define BIT_ECO_TXOP_BREAK_FORCE_CFEND BIT(0)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_WMAC_CR				(Offset 0x0600) */
+
+#define BIT_APSDOFF_STATUS BIT(7)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_WMAC_CR				(Offset 0x0600) */
+
+#define BIT_APSDOFF BIT(6)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_WMAC_CR				(Offset 0x0600) */
+
+#define BIT_STANDBY_STATUS BIT(5)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_WMAC_CR				(Offset 0x0600) */
+
+#define BIT_IC_MACPHY_M BIT(0)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_WMAC_FWPKT_CR			(Offset 0x0601) */
+
+#define BIT_FWEN BIT(7)
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+/* 2 REG_WMAC_FWPKT_CR			(Offset 0x0601) */
+
+#define BIT_FWRX_EN BIT(7)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_WMAC_FWPKT_CR			(Offset 0x0601) */
+
+#define BIT_PHYSTS_PKT_CTRL BIT(6)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT)
+
+/* 2 REG_WMAC_FWPKT_CR			(Offset 0x0601) */
+
+#define BIT_FWFULL_TO_RXFF_EN BIT(5)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_WMAC_FWPKT_CR			(Offset 0x0601) */
+
+#define BIT_APPHDR_MIDSRCH_FAIL BIT(4)
+#define BIT_FWPARSING_EN BIT(3)
+
+#define BIT_SHIFT_APPEND_MHDR_LEN 0
+#define BIT_MASK_APPEND_MHDR_LEN 0x7
+#define BIT_APPEND_MHDR_LEN(x)                                                 \
+	(((x) & BIT_MASK_APPEND_MHDR_LEN) << BIT_SHIFT_APPEND_MHDR_LEN)
+#define BITS_APPEND_MHDR_LEN                                                   \
+	(BIT_MASK_APPEND_MHDR_LEN << BIT_SHIFT_APPEND_MHDR_LEN)
+#define BIT_CLEAR_APPEND_MHDR_LEN(x) ((x) & (~BITS_APPEND_MHDR_LEN))
+#define BIT_GET_APPEND_MHDR_LEN(x)                                             \
+	(((x) >> BIT_SHIFT_APPEND_MHDR_LEN) & BIT_MASK_APPEND_MHDR_LEN)
+#define BIT_SET_APPEND_MHDR_LEN(x, v)                                          \
+	(BIT_CLEAR_APPEND_MHDR_LEN(x) | BIT_APPEND_MHDR_LEN(v))
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+/* 2 REG_BWOPMODE				(Offset 0x0603) */
+
+#define BIT_WMAC_20MHZBW BIT(2)
+#define BIT_WMAC_M11J BIT(0)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_TCR					(Offset 0x0604) */
+
+#define BIT_WMAC_EN_RTS_ADDR BIT(31)
+#define BIT_WMAC_DISABLE_CCK BIT(30)
+#define BIT_WMAC_RAW_LEN BIT(29)
+#define BIT_WMAC_NOTX_IN_RXNDP BIT(28)
+#define BIT_WMAC_EN_EOF BIT(27)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_TCR					(Offset 0x0604) */
+
+#define BIT_WMAC_TCRPWRMGT_HWCTL_V1 BIT(26)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_TCR					(Offset 0x0604) */
+
+#define BIT_WMAC_BF_SEL BIT(26)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_TCR					(Offset 0x0604) */
+
+#define BIT_BF_SEL BIT(25)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_TCR					(Offset 0x0604) */
+
+#define BIT_WMAC_ANTMODE_SEL BIT(25)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8814A_SUPPORT)
+
+/* 2 REG_TCR					(Offset 0x0604) */
+
+#define BIT_RXLEN_SEL BIT(24)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_TCR					(Offset 0x0604) */
+
+#define BIT_WMAC_TCRPWRMGT_HWCTL BIT(24)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_TCR					(Offset 0x0604) */
+
+#define BIT_WMAC_TCRPWRMGT_HWCTL_EN BIT(24)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_TCR					(Offset 0x0604) */
+
+#define BIT_WMAC_SMOOTH_VAL BIT(23)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_TCR					(Offset 0x0604) */
+
+#define BIT_WMAC_EN_SCRAM_INC BIT(22)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_TCR					(Offset 0x0604) */
+
+#define BIT_UNDERFLOWEN_CMPLEN_SEL BIT(21)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_TCR					(Offset 0x0604) */
+
+#define BIT_SHIFT_TSFT_CMP 20
+#define BIT_MASK_TSFT_CMP 0xf
+#define BIT_TSFT_CMP(x) (((x) & BIT_MASK_TSFT_CMP) << BIT_SHIFT_TSFT_CMP)
+#define BITS_TSFT_CMP (BIT_MASK_TSFT_CMP << BIT_SHIFT_TSFT_CMP)
+#define BIT_CLEAR_TSFT_CMP(x) ((x) & (~BITS_TSFT_CMP))
+#define BIT_GET_TSFT_CMP(x) (((x) >> BIT_SHIFT_TSFT_CMP) & BIT_MASK_TSFT_CMP)
+#define BIT_SET_TSFT_CMP(x, v) (BIT_CLEAR_TSFT_CMP(x) | BIT_TSFT_CMP(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_TCR					(Offset 0x0604) */
+
+#define BIT_FETCH_MPDU_AFTER_WSEC_RDY BIT(20)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_TCR					(Offset 0x0604) */
+
+#define BIT_WMAC_TCR_EN_20MST BIT(19)
+#define BIT_WMAC_DIS_SIGTA BIT(18)
+#define BIT_WMAC_DIS_A2B0 BIT(17)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_TCR					(Offset 0x0604) */
+
+#define BIT_SHIFT_TSFT_CMP_CCK 16
+#define BIT_MASK_TSFT_CMP_CCK 0xf
+#define BIT_TSFT_CMP_CCK(x)                                                    \
+	(((x) & BIT_MASK_TSFT_CMP_CCK) << BIT_SHIFT_TSFT_CMP_CCK)
+#define BITS_TSFT_CMP_CCK (BIT_MASK_TSFT_CMP_CCK << BIT_SHIFT_TSFT_CMP_CCK)
+#define BIT_CLEAR_TSFT_CMP_CCK(x) ((x) & (~BITS_TSFT_CMP_CCK))
+#define BIT_GET_TSFT_CMP_CCK(x)                                                \
+	(((x) >> BIT_SHIFT_TSFT_CMP_CCK) & BIT_MASK_TSFT_CMP_CCK)
+#define BIT_SET_TSFT_CMP_CCK(x, v)                                             \
+	(BIT_CLEAR_TSFT_CMP_CCK(x) | BIT_TSFT_CMP_CCK(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_TCR					(Offset 0x0604) */
+
+#define BIT_WMAC_MSK_SIGBCRC BIT(16)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_TCR					(Offset 0x0604) */
+
+#define BIT_WMAC_TCR_ERRSTEN_3 BIT(15)
+#define BIT_WMAC_TCR_ERRSTEN_2 BIT(14)
+#define BIT_WMAC_TCR_ERRSTEN_1 BIT(13)
+#define BIT_WMAC_TCR_ERRSTEN_0 BIT(12)
+#define BIT_WMAC_TCR_TXSK_PERPKT BIT(11)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_TCR					(Offset 0x0604) */
+
+#define BIT__TXSK_PERPKT BIT(11)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_TCR					(Offset 0x0604) */
+
+#define BIT_ICV BIT(10)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8881A_SUPPORT)
+
+/* 2 REG_TCR					(Offset 0x0604) */
+
+#define BIT_CFEND_FORMAT BIT(9)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_TCR					(Offset 0x0604) */
+
+#define BIT_CFENDFORM BIT(9)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_TCR					(Offset 0x0604) */
+
+#define BIT_CRC BIT(8)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_TCR					(Offset 0x0604) */
+
+#define BIT_PWRBIT_OW_EN BIT(7)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_TCR					(Offset 0x0604) */
+
+#define BIT_PWRMGT_CTL BIT(7)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_TCR					(Offset 0x0604) */
+
+#define BIT_WMAC_TCRPWRMGT_HWDATA_EN BIT(7)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_TCR					(Offset 0x0604) */
+
+#define BIT_PWR_ST BIT(6)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_TCR					(Offset 0x0604) */
+
+#define BIT_PWRMGT_VAL BIT(6)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_TCR					(Offset 0x0604) */
+
+#define BIT_WMAC_TCR_UPD_TIMIE BIT(5)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_TCR					(Offset 0x0604) */
+
+#define BIT_UPD_TIMIE BIT(5)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_TCR					(Offset 0x0604) */
+
+#define BIT_WMAC_TCR_UPD_HGQMD BIT(4)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_TCR					(Offset 0x0604) */
+
+#define BIT_UPD_HGQMD BIT(4)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_TCR					(Offset 0x0604) */
+
+#define BIT_VHTSIGA1_TXPS BIT(3)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_TCR					(Offset 0x0604) */
+
+#define BIT_PAD_SEL BIT(2)
+#define BIT_DIS_GCLK BIT(1)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_TCR					(Offset 0x0604) */
+
+#define BIT_TSFRST BIT(0)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_TCR					(Offset 0x0604) */
+
+#define BIT_WMAC_TCRPWRMGT_HWACT_EN BIT(0)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_TCR					(Offset 0x0604) */
+
+#define BIT_R_WMAC_TCR_LSIG BIT(0)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_RCR					(Offset 0x0608) */
+
+#define BIT_APP_FCS BIT(31)
+#define BIT_APP_MIC BIT(30)
+#define BIT_APP_ICV BIT(29)
+#define BIT_APP_PHYSTS BIT(28)
+#define BIT_APP_BASSN BIT(27)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_RCR					(Offset 0x0608) */
+
+#define BIT_VHT_DACK BIT(26)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_RCR					(Offset 0x0608) */
+
+#define BIT_TCPOFLD_EN BIT(25)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_RCR					(Offset 0x0608) */
+
+#define BIT_ENMBID BIT(24)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_RCR					(Offset 0x0608) */
+
+#define BIT_ENADDRCAM BIT(24)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_RCR					(Offset 0x0608) */
+
+#define BIT_LSIGEN BIT(23)
+#define BIT_MFBEN BIT(22)
+#define BIT_DISCHKPPDLLEN BIT(21)
+#define BIT_PKTCTL_DLEN BIT(20)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_RCR					(Offset 0x0608) */
+
+#define BIT_DISGCLK BIT(19)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_RCR					(Offset 0x0608) */
+
+#define BIT_TIM_PARSER_EN BIT(18)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_RCR					(Offset 0x0608) */
+
+#define BIT_TIMPSR_EN BIT(18)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_RCR					(Offset 0x0608) */
+
+#define BIT_BC_MD_EN BIT(17)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_RCR					(Offset 0x0608) */
+
+#define BIT_BCMDINT_EN BIT(17)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_RCR					(Offset 0x0608) */
+
+#define BIT_UC_MD_EN BIT(16)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_RCR					(Offset 0x0608) */
+
+#define BIT_UCMDINT_EN BIT(16)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_RCR					(Offset 0x0608) */
+
+#define BIT_RXSK_PERPKT BIT(15)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_RCR					(Offset 0x0608) */
+
+#define BIT_HTC_LOC_CTRL BIT(14)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_RCR					(Offset 0x0608) */
+
+#define BIT_HTCBFMC BIT(14)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_RCR					(Offset 0x0608) */
+
+#define BIT_AMF BIT(13)
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+/* 2 REG_RCR					(Offset 0x0608) */
+
+#define BIT_CHK_PREVTCA2 BIT(13)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_RCR					(Offset 0x0608) */
+
+#define BIT_ACK_WITH_CBSSID_DATA_OPTION BIT(13)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_RCR					(Offset 0x0608) */
+
+#define BIT_ACF BIT(12)
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_RCR					(Offset 0x0608) */
+
+#define BIT_RPFM_CAM_ENABLE BIT(12)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_RCR					(Offset 0x0608) */
+
+#define BIT_ADF BIT(11)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_RCR					(Offset 0x0608) */
+
+#define BIT_TA_BCN BIT(11)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_RCR					(Offset 0x0608) */
+
+#define BIT_DISDECMYPKT BIT(10)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_RCR					(Offset 0x0608) */
+
+#define BIT_DISDECNMYPKT BIT(10)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_RCR					(Offset 0x0608) */
+
+#define BIT_AICV BIT(9)
+#define BIT_ACRC32 BIT(8)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_RCR					(Offset 0x0608) */
+
+#define BIT_CBSSID_BCN BIT(7)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_RCR					(Offset 0x0608) */
+
+#define BIT_CBSSID_MGNT BIT(7)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_RCR					(Offset 0x0608) */
+
+#define BIT_CBSSID_DATA BIT(6)
+#define BIT_APWRMGT BIT(5)
+#define BIT_ADD3 BIT(4)
+#define BIT_AB BIT(3)
+#define BIT_AM BIT(2)
+#define BIT_APM BIT(1)
+#define BIT_AAP BIT(0)
+
+#define BIT_SHIFT_RXPKTLMT 0
+#define BIT_MASK_RXPKTLMT 0x3f
+#define BIT_RXPKTLMT(x) (((x) & BIT_MASK_RXPKTLMT) << BIT_SHIFT_RXPKTLMT)
+#define BITS_RXPKTLMT (BIT_MASK_RXPKTLMT << BIT_SHIFT_RXPKTLMT)
+#define BIT_CLEAR_RXPKTLMT(x) ((x) & (~BITS_RXPKTLMT))
+#define BIT_GET_RXPKTLMT(x) (((x) >> BIT_SHIFT_RXPKTLMT) & BIT_MASK_RXPKTLMT)
+#define BIT_SET_RXPKTLMT(x, v) (BIT_CLEAR_RXPKTLMT(x) | BIT_RXPKTLMT(v))
+
+/* 2 REG_RX_DLK_TIME				(Offset 0x060D) */
+
+#define BIT_SHIFT_RX_DLK_TIME 0
+#define BIT_MASK_RX_DLK_TIME 0xff
+#define BIT_RX_DLK_TIME(x)                                                     \
+	(((x) & BIT_MASK_RX_DLK_TIME) << BIT_SHIFT_RX_DLK_TIME)
+#define BITS_RX_DLK_TIME (BIT_MASK_RX_DLK_TIME << BIT_SHIFT_RX_DLK_TIME)
+#define BIT_CLEAR_RX_DLK_TIME(x) ((x) & (~BITS_RX_DLK_TIME))
+#define BIT_GET_RX_DLK_TIME(x)                                                 \
+	(((x) >> BIT_SHIFT_RX_DLK_TIME) & BIT_MASK_RX_DLK_TIME)
+#define BIT_SET_RX_DLK_TIME(x, v)                                              \
+	(BIT_CLEAR_RX_DLK_TIME(x) | BIT_RX_DLK_TIME(v))
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_SDIO_RXINT_LEN_TH			(Offset 0x1025060E) */
+
+#define BIT_SHIFT_SDIO_RXINT_LEN_TH 0
+#define BIT_MASK_SDIO_RXINT_LEN_TH 0xff
+#define BIT_SDIO_RXINT_LEN_TH(x)                                               \
+	(((x) & BIT_MASK_SDIO_RXINT_LEN_TH) << BIT_SHIFT_SDIO_RXINT_LEN_TH)
+#define BITS_SDIO_RXINT_LEN_TH                                                 \
+	(BIT_MASK_SDIO_RXINT_LEN_TH << BIT_SHIFT_SDIO_RXINT_LEN_TH)
+#define BIT_CLEAR_SDIO_RXINT_LEN_TH(x) ((x) & (~BITS_SDIO_RXINT_LEN_TH))
+#define BIT_GET_SDIO_RXINT_LEN_TH(x)                                           \
+	(((x) >> BIT_SHIFT_SDIO_RXINT_LEN_TH) & BIT_MASK_SDIO_RXINT_LEN_TH)
+#define BIT_SET_SDIO_RXINT_LEN_TH(x, v)                                        \
+	(BIT_CLEAR_SDIO_RXINT_LEN_TH(x) | BIT_SDIO_RXINT_LEN_TH(v))
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_RX_DRVINFO_SZ			(Offset 0x060F) */
+
+#define BIT_APP_PHYSTS_PER_SUBMPDU BIT(7)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_RX_DRVINFO_SZ			(Offset 0x060F) */
+
+#define BIT_PHYSTS_PER_PKT_MODE BIT(7)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_RX_DRVINFO_SZ			(Offset 0x060F) */
+
+#define BIT_APP_MH_SHIFT_VAL BIT(6)
+#define BIT_WMAC_ENSHIFT BIT(5)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_RX_DRVINFO_SZ			(Offset 0x060F) */
+
+#define BIT_SHIFT_BITMAP_SSNBK_COUNTER 2
+#define BIT_MASK_BITMAP_SSNBK_COUNTER 0x3f
+#define BIT_BITMAP_SSNBK_COUNTER(x)                                            \
+	(((x) & BIT_MASK_BITMAP_SSNBK_COUNTER)                                 \
+	 << BIT_SHIFT_BITMAP_SSNBK_COUNTER)
+#define BITS_BITMAP_SSNBK_COUNTER                                              \
+	(BIT_MASK_BITMAP_SSNBK_COUNTER << BIT_SHIFT_BITMAP_SSNBK_COUNTER)
+#define BIT_CLEAR_BITMAP_SSNBK_COUNTER(x) ((x) & (~BITS_BITMAP_SSNBK_COUNTER))
+#define BIT_GET_BITMAP_SSNBK_COUNTER(x)                                        \
+	(((x) >> BIT_SHIFT_BITMAP_SSNBK_COUNTER) &                             \
+	 BIT_MASK_BITMAP_SSNBK_COUNTER)
+#define BIT_SET_BITMAP_SSNBK_COUNTER(x, v)                                     \
+	(BIT_CLEAR_BITMAP_SSNBK_COUNTER(x) | BIT_BITMAP_SSNBK_COUNTER(v))
+
+#define BIT_BITMAP_EN BIT(1)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8881A_SUPPORT)
+
+/* 2 REG_RX_DRVINFO_SZ			(Offset 0x060F) */
+
+#define BIT_SHIFT_DRVINFO_SZ 0
+#define BIT_MASK_DRVINFO_SZ 0xff
+#define BIT_DRVINFO_SZ(x) (((x) & BIT_MASK_DRVINFO_SZ) << BIT_SHIFT_DRVINFO_SZ)
+#define BITS_DRVINFO_SZ (BIT_MASK_DRVINFO_SZ << BIT_SHIFT_DRVINFO_SZ)
+#define BIT_CLEAR_DRVINFO_SZ(x) ((x) & (~BITS_DRVINFO_SZ))
+#define BIT_GET_DRVINFO_SZ(x)                                                  \
+	(((x) >> BIT_SHIFT_DRVINFO_SZ) & BIT_MASK_DRVINFO_SZ)
+#define BIT_SET_DRVINFO_SZ(x, v) (BIT_CLEAR_DRVINFO_SZ(x) | BIT_DRVINFO_SZ(v))
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_RX_DRVINFO_SZ			(Offset 0x060F) */
+
+#define BIT_SHIFT_DRVINFO_SZ_V1 0
+#define BIT_MASK_DRVINFO_SZ_V1 0xf
+#define BIT_DRVINFO_SZ_V1(x)                                                   \
+	(((x) & BIT_MASK_DRVINFO_SZ_V1) << BIT_SHIFT_DRVINFO_SZ_V1)
+#define BITS_DRVINFO_SZ_V1 (BIT_MASK_DRVINFO_SZ_V1 << BIT_SHIFT_DRVINFO_SZ_V1)
+#define BIT_CLEAR_DRVINFO_SZ_V1(x) ((x) & (~BITS_DRVINFO_SZ_V1))
+#define BIT_GET_DRVINFO_SZ_V1(x)                                               \
+	(((x) >> BIT_SHIFT_DRVINFO_SZ_V1) & BIT_MASK_DRVINFO_SZ_V1)
+#define BIT_SET_DRVINFO_SZ_V1(x, v)                                            \
+	(BIT_CLEAR_DRVINFO_SZ_V1(x) | BIT_DRVINFO_SZ_V1(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT || \
+     HALMAC_8881A_SUPPORT)
+
+/* 2 REG_MACID				(Offset 0x0610) */
+
+#define BIT_SHIFT_MACID 0
+#define BIT_MASK_MACID 0xffffffffffffL
+#define BIT_MACID(x) (((x) & BIT_MASK_MACID) << BIT_SHIFT_MACID)
+#define BITS_MACID (BIT_MASK_MACID << BIT_SHIFT_MACID)
+#define BIT_CLEAR_MACID(x) ((x) & (~BITS_MACID))
+#define BIT_GET_MACID(x) (((x) >> BIT_SHIFT_MACID) & BIT_MASK_MACID)
+#define BIT_SET_MACID(x, v) (BIT_CLEAR_MACID(x) | BIT_MACID(v))
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_MACID				(Offset 0x0610) */
+
+#define BIT_SHIFT_MACID_V1 0
+#define BIT_MASK_MACID_V1 0xffffffffL
+#define BIT_MACID_V1(x) (((x) & BIT_MASK_MACID_V1) << BIT_SHIFT_MACID_V1)
+#define BITS_MACID_V1 (BIT_MASK_MACID_V1 << BIT_SHIFT_MACID_V1)
+#define BIT_CLEAR_MACID_V1(x) ((x) & (~BITS_MACID_V1))
+#define BIT_GET_MACID_V1(x) (((x) >> BIT_SHIFT_MACID_V1) & BIT_MASK_MACID_V1)
+#define BIT_SET_MACID_V1(x, v) (BIT_CLEAR_MACID_V1(x) | BIT_MACID_V1(v))
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_MACID_H				(Offset 0x0614) */
+
+#define BIT_SHIFT_MACID_H 0
+#define BIT_MASK_MACID_H 0xffff
+#define BIT_MACID_H(x) (((x) & BIT_MASK_MACID_H) << BIT_SHIFT_MACID_H)
+#define BITS_MACID_H (BIT_MASK_MACID_H << BIT_SHIFT_MACID_H)
+#define BIT_CLEAR_MACID_H(x) ((x) & (~BITS_MACID_H))
+#define BIT_GET_MACID_H(x) (((x) >> BIT_SHIFT_MACID_H) & BIT_MASK_MACID_H)
+#define BIT_SET_MACID_H(x, v) (BIT_CLEAR_MACID_H(x) | BIT_MACID_H(v))
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_MACID_H				(Offset 0x0614) */
+
+#define BIT_SHIFT_MACID_H_V1 0
+#define BIT_MASK_MACID_H_V1 0xffff
+#define BIT_MACID_H_V1(x) (((x) & BIT_MASK_MACID_H_V1) << BIT_SHIFT_MACID_H_V1)
+#define BITS_MACID_H_V1 (BIT_MASK_MACID_H_V1 << BIT_SHIFT_MACID_H_V1)
+#define BIT_CLEAR_MACID_H_V1(x) ((x) & (~BITS_MACID_H_V1))
+#define BIT_GET_MACID_H_V1(x)                                                  \
+	(((x) >> BIT_SHIFT_MACID_H_V1) & BIT_MASK_MACID_H_V1)
+#define BIT_SET_MACID_H_V1(x, v) (BIT_CLEAR_MACID_H_V1(x) | BIT_MACID_H_V1(v))
+
+#define BIT_SHIFT_BSSID_H_V1 0
+#define BIT_MASK_BSSID_H_V1 0xffff
+#define BIT_BSSID_H_V1(x) (((x) & BIT_MASK_BSSID_H_V1) << BIT_SHIFT_BSSID_H_V1)
+#define BITS_BSSID_H_V1 (BIT_MASK_BSSID_H_V1 << BIT_SHIFT_BSSID_H_V1)
+#define BIT_CLEAR_BSSID_H_V1(x) ((x) & (~BITS_BSSID_H_V1))
+#define BIT_GET_BSSID_H_V1(x)                                                  \
+	(((x) >> BIT_SHIFT_BSSID_H_V1) & BIT_MASK_BSSID_H_V1)
+#define BIT_SET_BSSID_H_V1(x, v) (BIT_CLEAR_BSSID_H_V1(x) | BIT_BSSID_H_V1(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT || \
+     HALMAC_8881A_SUPPORT)
+
+/* 2 REG_BSSID				(Offset 0x0618) */
+
+#define BIT_SHIFT_BSSID 0
+#define BIT_MASK_BSSID 0xffffffffffffL
+#define BIT_BSSID(x) (((x) & BIT_MASK_BSSID) << BIT_SHIFT_BSSID)
+#define BITS_BSSID (BIT_MASK_BSSID << BIT_SHIFT_BSSID)
+#define BIT_CLEAR_BSSID(x) ((x) & (~BITS_BSSID))
+#define BIT_GET_BSSID(x) (((x) >> BIT_SHIFT_BSSID) & BIT_MASK_BSSID)
+#define BIT_SET_BSSID(x, v) (BIT_CLEAR_BSSID(x) | BIT_BSSID(v))
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_BSSID				(Offset 0x0618) */
+
+#define BIT_SHIFT_BSSID_V1 0
+#define BIT_MASK_BSSID_V1 0xffffffffL
+#define BIT_BSSID_V1(x) (((x) & BIT_MASK_BSSID_V1) << BIT_SHIFT_BSSID_V1)
+#define BITS_BSSID_V1 (BIT_MASK_BSSID_V1 << BIT_SHIFT_BSSID_V1)
+#define BIT_CLEAR_BSSID_V1(x) ((x) & (~BITS_BSSID_V1))
+#define BIT_GET_BSSID_V1(x) (((x) >> BIT_SHIFT_BSSID_V1) & BIT_MASK_BSSID_V1)
+#define BIT_SET_BSSID_V1(x, v) (BIT_CLEAR_BSSID_V1(x) | BIT_BSSID_V1(v))
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_BSSID_H				(Offset 0x061C) */
+
+#define BIT_SHIFT_BSSID_H 0
+#define BIT_MASK_BSSID_H 0xffff
+#define BIT_BSSID_H(x) (((x) & BIT_MASK_BSSID_H) << BIT_SHIFT_BSSID_H)
+#define BITS_BSSID_H (BIT_MASK_BSSID_H << BIT_SHIFT_BSSID_H)
+#define BIT_CLEAR_BSSID_H(x) ((x) & (~BITS_BSSID_H))
+#define BIT_GET_BSSID_H(x) (((x) >> BIT_SHIFT_BSSID_H) & BIT_MASK_BSSID_H)
+#define BIT_SET_BSSID_H(x, v) (BIT_CLEAR_BSSID_H(x) | BIT_BSSID_H(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT || \
+     HALMAC_8881A_SUPPORT)
+
+/* 2 REG_MAR					(Offset 0x0620) */
+
+#define BIT_SHIFT_MAR 0
+#define BIT_MASK_MAR 0xffffffffffffffffL
+#define BIT_MAR(x) (((x) & BIT_MASK_MAR) << BIT_SHIFT_MAR)
+#define BITS_MAR (BIT_MASK_MAR << BIT_SHIFT_MAR)
+#define BIT_CLEAR_MAR(x) ((x) & (~BITS_MAR))
+#define BIT_GET_MAR(x) (((x) >> BIT_SHIFT_MAR) & BIT_MASK_MAR)
+#define BIT_SET_MAR(x, v) (BIT_CLEAR_MAR(x) | BIT_MAR(v))
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_MAR					(Offset 0x0620) */
+
+#define BIT_SHIFT_MAR_V1 0
+#define BIT_MASK_MAR_V1 0xffffffffL
+#define BIT_MAR_V1(x) (((x) & BIT_MASK_MAR_V1) << BIT_SHIFT_MAR_V1)
+#define BITS_MAR_V1 (BIT_MASK_MAR_V1 << BIT_SHIFT_MAR_V1)
+#define BIT_CLEAR_MAR_V1(x) ((x) & (~BITS_MAR_V1))
+#define BIT_GET_MAR_V1(x) (((x) >> BIT_SHIFT_MAR_V1) & BIT_MASK_MAR_V1)
+#define BIT_SET_MAR_V1(x, v) (BIT_CLEAR_MAR_V1(x) | BIT_MAR_V1(v))
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_MAR_H				(Offset 0x0624) */
+
+#define BIT_SHIFT_MAR_H 0
+#define BIT_MASK_MAR_H 0xffffffffL
+#define BIT_MAR_H(x) (((x) & BIT_MASK_MAR_H) << BIT_SHIFT_MAR_H)
+#define BITS_MAR_H (BIT_MASK_MAR_H << BIT_SHIFT_MAR_H)
+#define BIT_CLEAR_MAR_H(x) ((x) & (~BITS_MAR_H))
+#define BIT_GET_MAR_H(x) (((x) >> BIT_SHIFT_MAR_H) & BIT_MASK_MAR_H)
+#define BIT_SET_MAR_H(x, v) (BIT_CLEAR_MAR_H(x) | BIT_MAR_H(v))
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_MAR_H				(Offset 0x0624) */
+
+#define BIT_SHIFT_MAR_H_V1 0
+#define BIT_MASK_MAR_H_V1 0xffffffffL
+#define BIT_MAR_H_V1(x) (((x) & BIT_MASK_MAR_H_V1) << BIT_SHIFT_MAR_H_V1)
+#define BITS_MAR_H_V1 (BIT_MASK_MAR_H_V1 << BIT_SHIFT_MAR_H_V1)
+#define BIT_CLEAR_MAR_H_V1(x) ((x) & (~BITS_MAR_H_V1))
+#define BIT_GET_MAR_H_V1(x) (((x) >> BIT_SHIFT_MAR_H_V1) & BIT_MASK_MAR_H_V1)
+#define BIT_SET_MAR_H_V1(x, v) (BIT_CLEAR_MAR_H_V1(x) | BIT_MAR_H_V1(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_MBIDCAMCFG_1			(Offset 0x0628) */
+
+#define BIT_MBIDCAM_POLL BIT(31)
+#define BIT_MBIDCAM_WT_EN BIT(30)
+#define BIT_LSIC_TXOP_EN BIT(17)
+
+#define BIT_SHIFT_MBIDCAM_RWDATA_L 0
+#define BIT_MASK_MBIDCAM_RWDATA_L 0xffffffffL
+#define BIT_MBIDCAM_RWDATA_L(x)                                                \
+	(((x) & BIT_MASK_MBIDCAM_RWDATA_L) << BIT_SHIFT_MBIDCAM_RWDATA_L)
+#define BITS_MBIDCAM_RWDATA_L                                                  \
+	(BIT_MASK_MBIDCAM_RWDATA_L << BIT_SHIFT_MBIDCAM_RWDATA_L)
+#define BIT_CLEAR_MBIDCAM_RWDATA_L(x) ((x) & (~BITS_MBIDCAM_RWDATA_L))
+#define BIT_GET_MBIDCAM_RWDATA_L(x)                                            \
+	(((x) >> BIT_SHIFT_MBIDCAM_RWDATA_L) & BIT_MASK_MBIDCAM_RWDATA_L)
+#define BIT_SET_MBIDCAM_RWDATA_L(x, v)                                         \
+	(BIT_CLEAR_MBIDCAM_RWDATA_L(x) | BIT_MBIDCAM_RWDATA_L(v))
+
+#define BIT_SHIFT_MBIDCAM_RWDATA_H 0
+#define BIT_MASK_MBIDCAM_RWDATA_H 0xffff
+#define BIT_MBIDCAM_RWDATA_H(x)                                                \
+	(((x) & BIT_MASK_MBIDCAM_RWDATA_H) << BIT_SHIFT_MBIDCAM_RWDATA_H)
+#define BITS_MBIDCAM_RWDATA_H                                                  \
+	(BIT_MASK_MBIDCAM_RWDATA_H << BIT_SHIFT_MBIDCAM_RWDATA_H)
+#define BIT_CLEAR_MBIDCAM_RWDATA_H(x) ((x) & (~BITS_MBIDCAM_RWDATA_H))
+#define BIT_GET_MBIDCAM_RWDATA_H(x)                                            \
+	(((x) >> BIT_SHIFT_MBIDCAM_RWDATA_H) & BIT_MASK_MBIDCAM_RWDATA_H)
+#define BIT_SET_MBIDCAM_RWDATA_H(x, v)                                         \
+	(BIT_CLEAR_MBIDCAM_RWDATA_H(x) | BIT_MBIDCAM_RWDATA_H(v))
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_MBIDCAM_CFG				(Offset 0x062C) */
+
+#define BIT_MBIDCAM_RST_V1 BIT(29)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_MBIDCAMCFG_2			(Offset 0x062C) */
+
+#define BIT_SHIFT_MBIDCAM_ADDR_V1 24
+#define BIT_MASK_MBIDCAM_ADDR_V1 0x3f
+#define BIT_MBIDCAM_ADDR_V1(x)                                                 \
+	(((x) & BIT_MASK_MBIDCAM_ADDR_V1) << BIT_SHIFT_MBIDCAM_ADDR_V1)
+#define BITS_MBIDCAM_ADDR_V1                                                   \
+	(BIT_MASK_MBIDCAM_ADDR_V1 << BIT_SHIFT_MBIDCAM_ADDR_V1)
+#define BIT_CLEAR_MBIDCAM_ADDR_V1(x) ((x) & (~BITS_MBIDCAM_ADDR_V1))
+#define BIT_GET_MBIDCAM_ADDR_V1(x)                                             \
+	(((x) >> BIT_SHIFT_MBIDCAM_ADDR_V1) & BIT_MASK_MBIDCAM_ADDR_V1)
+#define BIT_SET_MBIDCAM_ADDR_V1(x, v)                                          \
+	(BIT_CLEAR_MBIDCAM_ADDR_V1(x) | BIT_MBIDCAM_ADDR_V1(v))
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+/* 2 REG_MBIDCAMCFG_2			(Offset 0x062C) */
+
+#define BIT_SHIFT_MBIDCAM_ADDR_V2 23
+#define BIT_MASK_MBIDCAM_ADDR_V2 0x7f
+#define BIT_MBIDCAM_ADDR_V2(x)                                                 \
+	(((x) & BIT_MASK_MBIDCAM_ADDR_V2) << BIT_SHIFT_MBIDCAM_ADDR_V2)
+#define BITS_MBIDCAM_ADDR_V2                                                   \
+	(BIT_MASK_MBIDCAM_ADDR_V2 << BIT_SHIFT_MBIDCAM_ADDR_V2)
+#define BIT_CLEAR_MBIDCAM_ADDR_V2(x) ((x) & (~BITS_MBIDCAM_ADDR_V2))
+#define BIT_GET_MBIDCAM_ADDR_V2(x)                                             \
+	(((x) >> BIT_SHIFT_MBIDCAM_ADDR_V2) & BIT_MASK_MBIDCAM_ADDR_V2)
+#define BIT_SET_MBIDCAM_ADDR_V2(x, v)                                          \
+	(BIT_CLEAR_MBIDCAM_ADDR_V2(x) | BIT_MBIDCAM_ADDR_V2(v))
+
+#define BIT_MBIDCAM_RST BIT(19)
+#define BIT_MBIDCAM_VALID_V1 BIT(18)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_MBIDCAMCFG_2			(Offset 0x062C) */
+
+#define BIT_REPEAT_MODE_EN BIT(16)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_WMAC_DEBUG_SEL			(Offset 0x062C) */
+
+#define BIT_SHIFT_WMAC_ARB_DBG_SEL 3
+#define BIT_MASK_WMAC_ARB_DBG_SEL 0x3
+#define BIT_WMAC_ARB_DBG_SEL(x)                                                \
+	(((x) & BIT_MASK_WMAC_ARB_DBG_SEL) << BIT_SHIFT_WMAC_ARB_DBG_SEL)
+#define BITS_WMAC_ARB_DBG_SEL                                                  \
+	(BIT_MASK_WMAC_ARB_DBG_SEL << BIT_SHIFT_WMAC_ARB_DBG_SEL)
+#define BIT_CLEAR_WMAC_ARB_DBG_SEL(x) ((x) & (~BITS_WMAC_ARB_DBG_SEL))
+#define BIT_GET_WMAC_ARB_DBG_SEL(x)                                            \
+	(((x) >> BIT_SHIFT_WMAC_ARB_DBG_SEL) & BIT_MASK_WMAC_ARB_DBG_SEL)
+#define BIT_SET_WMAC_ARB_DBG_SEL(x, v)                                         \
+	(BIT_CLEAR_WMAC_ARB_DBG_SEL(x) | BIT_WMAC_ARB_DBG_SEL(v))
+
+#define BIT_WMAC_EXT_DBG_SEL BIT(2)
+
+#define BIT_SHIFT_WMAC_MU_DBGSEL_V1 0
+#define BIT_MASK_WMAC_MU_DBGSEL_V1 0x3
+#define BIT_WMAC_MU_DBGSEL_V1(x)                                               \
+	(((x) & BIT_MASK_WMAC_MU_DBGSEL_V1) << BIT_SHIFT_WMAC_MU_DBGSEL_V1)
+#define BITS_WMAC_MU_DBGSEL_V1                                                 \
+	(BIT_MASK_WMAC_MU_DBGSEL_V1 << BIT_SHIFT_WMAC_MU_DBGSEL_V1)
+#define BIT_CLEAR_WMAC_MU_DBGSEL_V1(x) ((x) & (~BITS_WMAC_MU_DBGSEL_V1))
+#define BIT_GET_WMAC_MU_DBGSEL_V1(x)                                           \
+	(((x) >> BIT_SHIFT_WMAC_MU_DBGSEL_V1) & BIT_MASK_WMAC_MU_DBGSEL_V1)
+#define BIT_SET_WMAC_MU_DBGSEL_V1(x, v)                                        \
+	(BIT_CLEAR_WMAC_MU_DBGSEL_V1(x) | BIT_WMAC_MU_DBGSEL_V1(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_MCU_TEST_1				(Offset 0x0630) */
+
+#define BIT_SHIFT_MCU_RSVD 0
+#define BIT_MASK_MCU_RSVD 0xffffffffL
+#define BIT_MCU_RSVD(x) (((x) & BIT_MASK_MCU_RSVD) << BIT_SHIFT_MCU_RSVD)
+#define BITS_MCU_RSVD (BIT_MASK_MCU_RSVD << BIT_SHIFT_MCU_RSVD)
+#define BIT_CLEAR_MCU_RSVD(x) ((x) & (~BITS_MCU_RSVD))
+#define BIT_GET_MCU_RSVD(x) (((x) >> BIT_SHIFT_MCU_RSVD) & BIT_MASK_MCU_RSVD)
+#define BIT_SET_MCU_RSVD(x, v) (BIT_CLEAR_MCU_RSVD(x) | BIT_MCU_RSVD(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_WMAC_TCR_TSFT_OFS			(Offset 0x0630) */
+
+#define BIT_SHIFT_WMAC_TCR_TSFT_OFS 0
+#define BIT_MASK_WMAC_TCR_TSFT_OFS 0xffff
+#define BIT_WMAC_TCR_TSFT_OFS(x)                                               \
+	(((x) & BIT_MASK_WMAC_TCR_TSFT_OFS) << BIT_SHIFT_WMAC_TCR_TSFT_OFS)
+#define BITS_WMAC_TCR_TSFT_OFS                                                 \
+	(BIT_MASK_WMAC_TCR_TSFT_OFS << BIT_SHIFT_WMAC_TCR_TSFT_OFS)
+#define BIT_CLEAR_WMAC_TCR_TSFT_OFS(x) ((x) & (~BITS_WMAC_TCR_TSFT_OFS))
+#define BIT_GET_WMAC_TCR_TSFT_OFS(x)                                           \
+	(((x) >> BIT_SHIFT_WMAC_TCR_TSFT_OFS) & BIT_MASK_WMAC_TCR_TSFT_OFS)
+#define BIT_SET_WMAC_TCR_TSFT_OFS(x, v)                                        \
+	(BIT_CLEAR_WMAC_TCR_TSFT_OFS(x) | BIT_WMAC_TCR_TSFT_OFS(v))
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_UDF_THSD				(Offset 0x0632) */
+
+#define BIT_UDF_THSD_V1 BIT(7)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+
+/* 2 REG_UDF_THSD				(Offset 0x0632) */
+
+#define BIT_SHIFT_UDF_THSD 0
+#define BIT_MASK_UDF_THSD 0xff
+#define BIT_UDF_THSD(x) (((x) & BIT_MASK_UDF_THSD) << BIT_SHIFT_UDF_THSD)
+#define BITS_UDF_THSD (BIT_MASK_UDF_THSD << BIT_SHIFT_UDF_THSD)
+#define BIT_CLEAR_UDF_THSD(x) ((x) & (~BITS_UDF_THSD))
+#define BIT_GET_UDF_THSD(x) (((x) >> BIT_SHIFT_UDF_THSD) & BIT_MASK_UDF_THSD)
+#define BIT_SET_UDF_THSD(x, v) (BIT_CLEAR_UDF_THSD(x) | BIT_UDF_THSD(v))
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_UDF_THSD				(Offset 0x0632) */
+
+#define BIT_SHIFT_UDF_THSD_VALUE 0
+#define BIT_MASK_UDF_THSD_VALUE 0x7f
+#define BIT_UDF_THSD_VALUE(x)                                                  \
+	(((x) & BIT_MASK_UDF_THSD_VALUE) << BIT_SHIFT_UDF_THSD_VALUE)
+#define BITS_UDF_THSD_VALUE                                                    \
+	(BIT_MASK_UDF_THSD_VALUE << BIT_SHIFT_UDF_THSD_VALUE)
+#define BIT_CLEAR_UDF_THSD_VALUE(x) ((x) & (~BITS_UDF_THSD_VALUE))
+#define BIT_GET_UDF_THSD_VALUE(x)                                              \
+	(((x) >> BIT_SHIFT_UDF_THSD_VALUE) & BIT_MASK_UDF_THSD_VALUE)
+#define BIT_SET_UDF_THSD_VALUE(x, v)                                           \
+	(BIT_CLEAR_UDF_THSD_VALUE(x) | BIT_UDF_THSD_VALUE(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_ZLD_NUM				(Offset 0x0633) */
+
+#define BIT_SHIFT_ZLD_NUM 0
+#define BIT_MASK_ZLD_NUM 0xff
+#define BIT_ZLD_NUM(x) (((x) & BIT_MASK_ZLD_NUM) << BIT_SHIFT_ZLD_NUM)
+#define BITS_ZLD_NUM (BIT_MASK_ZLD_NUM << BIT_SHIFT_ZLD_NUM)
+#define BIT_CLEAR_ZLD_NUM(x) ((x) & (~BITS_ZLD_NUM))
+#define BIT_GET_ZLD_NUM(x) (((x) >> BIT_SHIFT_ZLD_NUM) & BIT_MASK_ZLD_NUM)
+#define BIT_SET_ZLD_NUM(x, v) (BIT_CLEAR_ZLD_NUM(x) | BIT_ZLD_NUM(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_MCU_TEST_2				(Offset 0x0634) */
+
+#define BIT_SHIFT_MCU_RSVD_2 0
+#define BIT_MASK_MCU_RSVD_2 0xffffffffL
+#define BIT_MCU_RSVD_2(x) (((x) & BIT_MASK_MCU_RSVD_2) << BIT_SHIFT_MCU_RSVD_2)
+#define BITS_MCU_RSVD_2 (BIT_MASK_MCU_RSVD_2 << BIT_SHIFT_MCU_RSVD_2)
+#define BIT_CLEAR_MCU_RSVD_2(x) ((x) & (~BITS_MCU_RSVD_2))
+#define BIT_GET_MCU_RSVD_2(x)                                                  \
+	(((x) >> BIT_SHIFT_MCU_RSVD_2) & BIT_MASK_MCU_RSVD_2)
+#define BIT_SET_MCU_RSVD_2(x, v) (BIT_CLEAR_MCU_RSVD_2(x) | BIT_MCU_RSVD_2(v))
+
+#define BIT_SHIFT_WKFCAM_NUM 0
+#define BIT_MASK_WKFCAM_NUM 0x7f
+#define BIT_WKFCAM_NUM(x) (((x) & BIT_MASK_WKFCAM_NUM) << BIT_SHIFT_WKFCAM_NUM)
+#define BITS_WKFCAM_NUM (BIT_MASK_WKFCAM_NUM << BIT_SHIFT_WKFCAM_NUM)
+#define BIT_CLEAR_WKFCAM_NUM(x) ((x) & (~BITS_WKFCAM_NUM))
+#define BIT_GET_WKFCAM_NUM(x)                                                  \
+	(((x) >> BIT_SHIFT_WKFCAM_NUM) & BIT_MASK_WKFCAM_NUM)
+#define BIT_SET_WKFCAM_NUM(x, v) (BIT_CLEAR_WKFCAM_NUM(x) | BIT_WKFCAM_NUM(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_STMP_THSD				(Offset 0x0634) */
+
+#define BIT_SHIFT_STMP_THSD 0
+#define BIT_MASK_STMP_THSD 0xff
+#define BIT_STMP_THSD(x) (((x) & BIT_MASK_STMP_THSD) << BIT_SHIFT_STMP_THSD)
+#define BITS_STMP_THSD (BIT_MASK_STMP_THSD << BIT_SHIFT_STMP_THSD)
+#define BIT_CLEAR_STMP_THSD(x) ((x) & (~BITS_STMP_THSD))
+#define BIT_GET_STMP_THSD(x) (((x) >> BIT_SHIFT_STMP_THSD) & BIT_MASK_STMP_THSD)
+#define BIT_SET_STMP_THSD(x, v) (BIT_CLEAR_STMP_THSD(x) | BIT_STMP_THSD(v))
+
+/* 2 REG_WMAC_TXTIMEOUT			(Offset 0x0635) */
+
+#define BIT_SHIFT_WMAC_TXTIMEOUT 0
+#define BIT_MASK_WMAC_TXTIMEOUT 0xff
+#define BIT_WMAC_TXTIMEOUT(x)                                                  \
+	(((x) & BIT_MASK_WMAC_TXTIMEOUT) << BIT_SHIFT_WMAC_TXTIMEOUT)
+#define BITS_WMAC_TXTIMEOUT                                                    \
+	(BIT_MASK_WMAC_TXTIMEOUT << BIT_SHIFT_WMAC_TXTIMEOUT)
+#define BIT_CLEAR_WMAC_TXTIMEOUT(x) ((x) & (~BITS_WMAC_TXTIMEOUT))
+#define BIT_GET_WMAC_TXTIMEOUT(x)                                              \
+	(((x) >> BIT_SHIFT_WMAC_TXTIMEOUT) & BIT_MASK_WMAC_TXTIMEOUT)
+#define BIT_SET_WMAC_TXTIMEOUT(x, v)                                           \
+	(BIT_CLEAR_WMAC_TXTIMEOUT(x) | BIT_WMAC_TXTIMEOUT(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT)
+
+/* 2 REG_MCU_TEST_2_V1			(Offset 0x0636) */
+
+#define BIT_SHIFT_MCU_RSVD_2_V1 0
+#define BIT_MASK_MCU_RSVD_2_V1 0xffff
+#define BIT_MCU_RSVD_2_V1(x)                                                   \
+	(((x) & BIT_MASK_MCU_RSVD_2_V1) << BIT_SHIFT_MCU_RSVD_2_V1)
+#define BITS_MCU_RSVD_2_V1 (BIT_MASK_MCU_RSVD_2_V1 << BIT_SHIFT_MCU_RSVD_2_V1)
+#define BIT_CLEAR_MCU_RSVD_2_V1(x) ((x) & (~BITS_MCU_RSVD_2_V1))
+#define BIT_GET_MCU_RSVD_2_V1(x)                                               \
+	(((x) >> BIT_SHIFT_MCU_RSVD_2_V1) & BIT_MASK_MCU_RSVD_2_V1)
+#define BIT_SET_MCU_RSVD_2_V1(x, v)                                            \
+	(BIT_CLEAR_MCU_RSVD_2_V1(x) | BIT_MCU_RSVD_2_V1(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814B_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_USTIME_EDCA				(Offset 0x0638) */
+
+#define BIT_SHIFT_USTIME_EDCA 0
+#define BIT_MASK_USTIME_EDCA 0xff
+#define BIT_USTIME_EDCA(x)                                                     \
+	(((x) & BIT_MASK_USTIME_EDCA) << BIT_SHIFT_USTIME_EDCA)
+#define BITS_USTIME_EDCA (BIT_MASK_USTIME_EDCA << BIT_SHIFT_USTIME_EDCA)
+#define BIT_CLEAR_USTIME_EDCA(x) ((x) & (~BITS_USTIME_EDCA))
+#define BIT_GET_USTIME_EDCA(x)                                                 \
+	(((x) >> BIT_SHIFT_USTIME_EDCA) & BIT_MASK_USTIME_EDCA)
+#define BIT_SET_USTIME_EDCA(x, v)                                              \
+	(BIT_CLEAR_USTIME_EDCA(x) | BIT_USTIME_EDCA(v))
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_USTIME_EDCA				(Offset 0x0638) */
+
+#define BIT_SHIFT_USTIME 0
+#define BIT_MASK_USTIME 0xff
+#define BIT_USTIME(x) (((x) & BIT_MASK_USTIME) << BIT_SHIFT_USTIME)
+#define BITS_USTIME (BIT_MASK_USTIME << BIT_SHIFT_USTIME)
+#define BIT_CLEAR_USTIME(x) ((x) & (~BITS_USTIME))
+#define BIT_GET_USTIME(x) (((x) >> BIT_SHIFT_USTIME) & BIT_MASK_USTIME)
+#define BIT_SET_USTIME(x, v) (BIT_CLEAR_USTIME(x) | BIT_USTIME(v))
+
+#endif
+
+#if (HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT)
+
+/* 2 REG_USTIME_EDCA				(Offset 0x0638) */
+
+#define BIT_SHIFT_USTIME_EDCA_V1 0
+#define BIT_MASK_USTIME_EDCA_V1 0x1ff
+#define BIT_USTIME_EDCA_V1(x)                                                  \
+	(((x) & BIT_MASK_USTIME_EDCA_V1) << BIT_SHIFT_USTIME_EDCA_V1)
+#define BITS_USTIME_EDCA_V1                                                    \
+	(BIT_MASK_USTIME_EDCA_V1 << BIT_SHIFT_USTIME_EDCA_V1)
+#define BIT_CLEAR_USTIME_EDCA_V1(x) ((x) & (~BITS_USTIME_EDCA_V1))
+#define BIT_GET_USTIME_EDCA_V1(x)                                              \
+	(((x) >> BIT_SHIFT_USTIME_EDCA_V1) & BIT_MASK_USTIME_EDCA_V1)
+#define BIT_SET_USTIME_EDCA_V1(x, v)                                           \
+	(BIT_CLEAR_USTIME_EDCA_V1(x) | BIT_USTIME_EDCA_V1(v))
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_ACKTO_CCK				(Offset 0x0639) */
+
+#define BIT_SHIFT_ACKTO_CCK 0
+#define BIT_MASK_ACKTO_CCK 0xff
+#define BIT_ACKTO_CCK(x) (((x) & BIT_MASK_ACKTO_CCK) << BIT_SHIFT_ACKTO_CCK)
+#define BITS_ACKTO_CCK (BIT_MASK_ACKTO_CCK << BIT_SHIFT_ACKTO_CCK)
+#define BIT_CLEAR_ACKTO_CCK(x) ((x) & (~BITS_ACKTO_CCK))
+#define BIT_GET_ACKTO_CCK(x) (((x) >> BIT_SHIFT_ACKTO_CCK) & BIT_MASK_ACKTO_CCK)
+#define BIT_SET_ACKTO_CCK(x, v) (BIT_CLEAR_ACKTO_CCK(x) | BIT_ACKTO_CCK(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_MAC_SPEC_SIFS			(Offset 0x063A) */
+
+#define BIT_SHIFT_SPEC_SIFS_OFDM 8
+#define BIT_MASK_SPEC_SIFS_OFDM 0xff
+#define BIT_SPEC_SIFS_OFDM(x)                                                  \
+	(((x) & BIT_MASK_SPEC_SIFS_OFDM) << BIT_SHIFT_SPEC_SIFS_OFDM)
+#define BITS_SPEC_SIFS_OFDM                                                    \
+	(BIT_MASK_SPEC_SIFS_OFDM << BIT_SHIFT_SPEC_SIFS_OFDM)
+#define BIT_CLEAR_SPEC_SIFS_OFDM(x) ((x) & (~BITS_SPEC_SIFS_OFDM))
+#define BIT_GET_SPEC_SIFS_OFDM(x)                                              \
+	(((x) >> BIT_SHIFT_SPEC_SIFS_OFDM) & BIT_MASK_SPEC_SIFS_OFDM)
+#define BIT_SET_SPEC_SIFS_OFDM(x, v)                                           \
+	(BIT_CLEAR_SPEC_SIFS_OFDM(x) | BIT_SPEC_SIFS_OFDM(v))
+
+#define BIT_SHIFT_SPEC_SIFS_CCK 0
+#define BIT_MASK_SPEC_SIFS_CCK 0xff
+#define BIT_SPEC_SIFS_CCK(x)                                                   \
+	(((x) & BIT_MASK_SPEC_SIFS_CCK) << BIT_SHIFT_SPEC_SIFS_CCK)
+#define BITS_SPEC_SIFS_CCK (BIT_MASK_SPEC_SIFS_CCK << BIT_SHIFT_SPEC_SIFS_CCK)
+#define BIT_CLEAR_SPEC_SIFS_CCK(x) ((x) & (~BITS_SPEC_SIFS_CCK))
+#define BIT_GET_SPEC_SIFS_CCK(x)                                               \
+	(((x) >> BIT_SHIFT_SPEC_SIFS_CCK) & BIT_MASK_SPEC_SIFS_CCK)
+#define BIT_SET_SPEC_SIFS_CCK(x, v)                                            \
+	(BIT_CLEAR_SPEC_SIFS_CCK(x) | BIT_SPEC_SIFS_CCK(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_RESP_SIFS_CCK			(Offset 0x063C) */
+
+#define BIT_SHIFT_SIFS_R2T_CCK 8
+#define BIT_MASK_SIFS_R2T_CCK 0xff
+#define BIT_SIFS_R2T_CCK(x)                                                    \
+	(((x) & BIT_MASK_SIFS_R2T_CCK) << BIT_SHIFT_SIFS_R2T_CCK)
+#define BITS_SIFS_R2T_CCK (BIT_MASK_SIFS_R2T_CCK << BIT_SHIFT_SIFS_R2T_CCK)
+#define BIT_CLEAR_SIFS_R2T_CCK(x) ((x) & (~BITS_SIFS_R2T_CCK))
+#define BIT_GET_SIFS_R2T_CCK(x)                                                \
+	(((x) >> BIT_SHIFT_SIFS_R2T_CCK) & BIT_MASK_SIFS_R2T_CCK)
+#define BIT_SET_SIFS_R2T_CCK(x, v)                                             \
+	(BIT_CLEAR_SIFS_R2T_CCK(x) | BIT_SIFS_R2T_CCK(v))
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_RESP_SIFS_CCK			(Offset 0x063C) */
+
+#define BIT_SHIFT_R2T_SIFS_CCK 8
+#define BIT_MASK_R2T_SIFS_CCK 0xff
+#define BIT_R2T_SIFS_CCK(x)                                                    \
+	(((x) & BIT_MASK_R2T_SIFS_CCK) << BIT_SHIFT_R2T_SIFS_CCK)
+#define BITS_R2T_SIFS_CCK (BIT_MASK_R2T_SIFS_CCK << BIT_SHIFT_R2T_SIFS_CCK)
+#define BIT_CLEAR_R2T_SIFS_CCK(x) ((x) & (~BITS_R2T_SIFS_CCK))
+#define BIT_GET_R2T_SIFS_CCK(x)                                                \
+	(((x) >> BIT_SHIFT_R2T_SIFS_CCK) & BIT_MASK_R2T_SIFS_CCK)
+#define BIT_SET_R2T_SIFS_CCK(x, v)                                             \
+	(BIT_CLEAR_R2T_SIFS_CCK(x) | BIT_R2T_SIFS_CCK(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_RESP_SIFS_CCK			(Offset 0x063C) */
+
+#define BIT_SHIFT_SIFS_T2T_CCK 0
+#define BIT_MASK_SIFS_T2T_CCK 0xff
+#define BIT_SIFS_T2T_CCK(x)                                                    \
+	(((x) & BIT_MASK_SIFS_T2T_CCK) << BIT_SHIFT_SIFS_T2T_CCK)
+#define BITS_SIFS_T2T_CCK (BIT_MASK_SIFS_T2T_CCK << BIT_SHIFT_SIFS_T2T_CCK)
+#define BIT_CLEAR_SIFS_T2T_CCK(x) ((x) & (~BITS_SIFS_T2T_CCK))
+#define BIT_GET_SIFS_T2T_CCK(x)                                                \
+	(((x) >> BIT_SHIFT_SIFS_T2T_CCK) & BIT_MASK_SIFS_T2T_CCK)
+#define BIT_SET_SIFS_T2T_CCK(x, v)                                             \
+	(BIT_CLEAR_SIFS_T2T_CCK(x) | BIT_SIFS_T2T_CCK(v))
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_RESP_SIFS_CCK			(Offset 0x063C) */
+
+#define BIT_SHIFT_T2T_SIFS_CCK 0
+#define BIT_MASK_T2T_SIFS_CCK 0xff
+#define BIT_T2T_SIFS_CCK(x)                                                    \
+	(((x) & BIT_MASK_T2T_SIFS_CCK) << BIT_SHIFT_T2T_SIFS_CCK)
+#define BITS_T2T_SIFS_CCK (BIT_MASK_T2T_SIFS_CCK << BIT_SHIFT_T2T_SIFS_CCK)
+#define BIT_CLEAR_T2T_SIFS_CCK(x) ((x) & (~BITS_T2T_SIFS_CCK))
+#define BIT_GET_T2T_SIFS_CCK(x)                                                \
+	(((x) >> BIT_SHIFT_T2T_SIFS_CCK) & BIT_MASK_T2T_SIFS_CCK)
+#define BIT_SET_T2T_SIFS_CCK(x, v)                                             \
+	(BIT_CLEAR_T2T_SIFS_CCK(x) | BIT_T2T_SIFS_CCK(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_RESP_SIFS_OFDM			(Offset 0x063E) */
+
+#define BIT_SHIFT_SIFS_R2T_OFDM 8
+#define BIT_MASK_SIFS_R2T_OFDM 0xff
+#define BIT_SIFS_R2T_OFDM(x)                                                   \
+	(((x) & BIT_MASK_SIFS_R2T_OFDM) << BIT_SHIFT_SIFS_R2T_OFDM)
+#define BITS_SIFS_R2T_OFDM (BIT_MASK_SIFS_R2T_OFDM << BIT_SHIFT_SIFS_R2T_OFDM)
+#define BIT_CLEAR_SIFS_R2T_OFDM(x) ((x) & (~BITS_SIFS_R2T_OFDM))
+#define BIT_GET_SIFS_R2T_OFDM(x)                                               \
+	(((x) >> BIT_SHIFT_SIFS_R2T_OFDM) & BIT_MASK_SIFS_R2T_OFDM)
+#define BIT_SET_SIFS_R2T_OFDM(x, v)                                            \
+	(BIT_CLEAR_SIFS_R2T_OFDM(x) | BIT_SIFS_R2T_OFDM(v))
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_RESP_SIFS_OFDM			(Offset 0x063E) */
+
+#define BIT_SHIFT_R2T_SIFS_OFDM 8
+#define BIT_MASK_R2T_SIFS_OFDM 0xff
+#define BIT_R2T_SIFS_OFDM(x)                                                   \
+	(((x) & BIT_MASK_R2T_SIFS_OFDM) << BIT_SHIFT_R2T_SIFS_OFDM)
+#define BITS_R2T_SIFS_OFDM (BIT_MASK_R2T_SIFS_OFDM << BIT_SHIFT_R2T_SIFS_OFDM)
+#define BIT_CLEAR_R2T_SIFS_OFDM(x) ((x) & (~BITS_R2T_SIFS_OFDM))
+#define BIT_GET_R2T_SIFS_OFDM(x)                                               \
+	(((x) >> BIT_SHIFT_R2T_SIFS_OFDM) & BIT_MASK_R2T_SIFS_OFDM)
+#define BIT_SET_R2T_SIFS_OFDM(x, v)                                            \
+	(BIT_CLEAR_R2T_SIFS_OFDM(x) | BIT_R2T_SIFS_OFDM(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_RESP_SIFS_OFDM			(Offset 0x063E) */
+
+#define BIT_SHIFT_SIFS_T2T_OFDM 0
+#define BIT_MASK_SIFS_T2T_OFDM 0xff
+#define BIT_SIFS_T2T_OFDM(x)                                                   \
+	(((x) & BIT_MASK_SIFS_T2T_OFDM) << BIT_SHIFT_SIFS_T2T_OFDM)
+#define BITS_SIFS_T2T_OFDM (BIT_MASK_SIFS_T2T_OFDM << BIT_SHIFT_SIFS_T2T_OFDM)
+#define BIT_CLEAR_SIFS_T2T_OFDM(x) ((x) & (~BITS_SIFS_T2T_OFDM))
+#define BIT_GET_SIFS_T2T_OFDM(x)                                               \
+	(((x) >> BIT_SHIFT_SIFS_T2T_OFDM) & BIT_MASK_SIFS_T2T_OFDM)
+#define BIT_SET_SIFS_T2T_OFDM(x, v)                                            \
+	(BIT_CLEAR_SIFS_T2T_OFDM(x) | BIT_SIFS_T2T_OFDM(v))
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_RESP_SIFS_OFDM			(Offset 0x063E) */
+
+#define BIT_SHIFT_T2T_SIFS_OFDM 0
+#define BIT_MASK_T2T_SIFS_OFDM 0xff
+#define BIT_T2T_SIFS_OFDM(x)                                                   \
+	(((x) & BIT_MASK_T2T_SIFS_OFDM) << BIT_SHIFT_T2T_SIFS_OFDM)
+#define BITS_T2T_SIFS_OFDM (BIT_MASK_T2T_SIFS_OFDM << BIT_SHIFT_T2T_SIFS_OFDM)
+#define BIT_CLEAR_T2T_SIFS_OFDM(x) ((x) & (~BITS_T2T_SIFS_OFDM))
+#define BIT_GET_T2T_SIFS_OFDM(x)                                               \
+	(((x) >> BIT_SHIFT_T2T_SIFS_OFDM) & BIT_MASK_T2T_SIFS_OFDM)
+#define BIT_SET_T2T_SIFS_OFDM(x, v)                                            \
+	(BIT_CLEAR_T2T_SIFS_OFDM(x) | BIT_T2T_SIFS_OFDM(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_ACKTO				(Offset 0x0640) */
+
+#define BIT_SHIFT_ACKTO 0
+#define BIT_MASK_ACKTO 0xff
+#define BIT_ACKTO(x) (((x) & BIT_MASK_ACKTO) << BIT_SHIFT_ACKTO)
+#define BITS_ACKTO (BIT_MASK_ACKTO << BIT_SHIFT_ACKTO)
+#define BIT_CLEAR_ACKTO(x) ((x) & (~BITS_ACKTO))
+#define BIT_GET_ACKTO(x) (((x) >> BIT_SHIFT_ACKTO) & BIT_MASK_ACKTO)
+#define BIT_SET_ACKTO(x, v) (BIT_CLEAR_ACKTO(x) | BIT_ACKTO(v))
+
+/* 2 REG_CTS2TO				(Offset 0x0641) */
+
+#define BIT_SHIFT_CTS2TO 0
+#define BIT_MASK_CTS2TO 0xff
+#define BIT_CTS2TO(x) (((x) & BIT_MASK_CTS2TO) << BIT_SHIFT_CTS2TO)
+#define BITS_CTS2TO (BIT_MASK_CTS2TO << BIT_SHIFT_CTS2TO)
+#define BIT_CLEAR_CTS2TO(x) ((x) & (~BITS_CTS2TO))
+#define BIT_GET_CTS2TO(x) (((x) >> BIT_SHIFT_CTS2TO) & BIT_MASK_CTS2TO)
+#define BIT_SET_CTS2TO(x, v) (BIT_CLEAR_CTS2TO(x) | BIT_CTS2TO(v))
+
+/* 2 REG_EIFS				(Offset 0x0642) */
+
+#define BIT_SHIFT_EIFS 0
+#define BIT_MASK_EIFS 0xffff
+#define BIT_EIFS(x) (((x) & BIT_MASK_EIFS) << BIT_SHIFT_EIFS)
+#define BITS_EIFS (BIT_MASK_EIFS << BIT_SHIFT_EIFS)
+#define BIT_CLEAR_EIFS(x) ((x) & (~BITS_EIFS))
+#define BIT_GET_EIFS(x) (((x) >> BIT_SHIFT_EIFS) & BIT_MASK_EIFS)
+#define BIT_SET_EIFS(x, v) (BIT_CLEAR_EIFS(x) | BIT_EIFS(v))
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_RPFM_MAP0				(Offset 0x0644) */
+
+#define BIT_MGT_RPFM15EN BIT(15)
+#define BIT_MGT_RPFM14EN BIT(14)
+#define BIT_MGT_RPFM13EN BIT(13)
+#define BIT_MGT_RPFM12EN BIT(12)
+#define BIT_MGT_RPFM11EN BIT(11)
+#define BIT_MGT_RPFM10EN BIT(10)
+#define BIT_MGT_RPFM9EN BIT(9)
+#define BIT_MGT_RPFM8EN BIT(8)
+#define BIT_MGT_RPFM7EN BIT(7)
+#define BIT_MGT_RPFM6EN BIT(6)
+#define BIT_MGT_RPFM5EN BIT(5)
+#define BIT_MGT_RPFM4EN BIT(4)
+#define BIT_MGT_RPFM3EN BIT(3)
+#define BIT_MGT_RPFM2EN BIT(2)
+#define BIT_MGT_RPFM1EN BIT(1)
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+/* 2 REG_RPFM_MAP0				(Offset 0x0644) */
+
+#define BIT_SHIFT_RPFM_MAP0 0
+#define BIT_MASK_RPFM_MAP0 0xffff
+#define BIT_RPFM_MAP0(x) (((x) & BIT_MASK_RPFM_MAP0) << BIT_SHIFT_RPFM_MAP0)
+#define BITS_RPFM_MAP0 (BIT_MASK_RPFM_MAP0 << BIT_SHIFT_RPFM_MAP0)
+#define BIT_CLEAR_RPFM_MAP0(x) ((x) & (~BITS_RPFM_MAP0))
+#define BIT_GET_RPFM_MAP0(x) (((x) >> BIT_SHIFT_RPFM_MAP0) & BIT_MASK_RPFM_MAP0)
+#define BIT_SET_RPFM_MAP0(x, v) (BIT_CLEAR_RPFM_MAP0(x) | BIT_RPFM_MAP0(v))
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_RPFM_MAP0				(Offset 0x0644) */
+
+#define BIT_MGT_RPFM0EN BIT(0)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_RPFM_MAP1_V1			(Offset 0x0646) */
+
+#define BIT_DATA_RPFM15EN BIT(15)
+#define BIT_DATA_RPFM14EN BIT(14)
+#define BIT_DATA_RPFM13EN BIT(13)
+#define BIT_DATA_RPFM12EN BIT(12)
+#define BIT_DATA_RPFM11EN BIT(11)
+#define BIT_DATA_RPFM10EN BIT(10)
+#define BIT_DATA_RPFM9EN BIT(9)
+#define BIT_DATA_RPFM8EN BIT(8)
+#define BIT_DATA_RPFM7EN BIT(7)
+#define BIT_DATA_RPFM6EN BIT(6)
+#define BIT_DATA_RPFM5EN BIT(5)
+#define BIT_DATA_RPFM4EN BIT(4)
+#define BIT_DATA_RPFM3EN BIT(3)
+#define BIT_DATA_RPFM2EN BIT(2)
+#define BIT_DATA_RPFM1EN BIT(1)
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+/* 2 REG_RPFM_MAP1				(Offset 0x0646) */
+
+#define BIT_SHIFT_RPFM_MAP1 0
+#define BIT_MASK_RPFM_MAP1 0xffff
+#define BIT_RPFM_MAP1(x) (((x) & BIT_MASK_RPFM_MAP1) << BIT_SHIFT_RPFM_MAP1)
+#define BITS_RPFM_MAP1 (BIT_MASK_RPFM_MAP1 << BIT_SHIFT_RPFM_MAP1)
+#define BIT_CLEAR_RPFM_MAP1(x) ((x) & (~BITS_RPFM_MAP1))
+#define BIT_GET_RPFM_MAP1(x) (((x) >> BIT_SHIFT_RPFM_MAP1) & BIT_MASK_RPFM_MAP1)
+#define BIT_SET_RPFM_MAP1(x, v) (BIT_CLEAR_RPFM_MAP1(x) | BIT_RPFM_MAP1(v))
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_RPFM_MAP1_V1			(Offset 0x0646) */
+
+#define BIT_DATA_RPFM0EN BIT(0)
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_RPFM_CAM_CMD			(Offset 0x0648) */
+
+#define BIT_RPFM_CAM_POLLING BIT(31)
+#define BIT_RPFM_CAM_CLR BIT(30)
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+/* 2 REG_RPFM_CAM_CMD			(Offset 0x0648) */
+
+#define BIT_RPFM_CAM_WR BIT(16)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_RPFM_CAM_CMD			(Offset 0x0648) */
+
+#define BIT_RPFM_CAM_WE BIT(16)
+#define BIT_RPT_VALID BIT(13)
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_RPFM_CAM_CMD			(Offset 0x0648) */
+
+#define BIT_SHIFT_RPFM_CAM_ADDR 0
+#define BIT_MASK_RPFM_CAM_ADDR 0x7f
+#define BIT_RPFM_CAM_ADDR(x)                                                   \
+	(((x) & BIT_MASK_RPFM_CAM_ADDR) << BIT_SHIFT_RPFM_CAM_ADDR)
+#define BITS_RPFM_CAM_ADDR (BIT_MASK_RPFM_CAM_ADDR << BIT_SHIFT_RPFM_CAM_ADDR)
+#define BIT_CLEAR_RPFM_CAM_ADDR(x) ((x) & (~BITS_RPFM_CAM_ADDR))
+#define BIT_GET_RPFM_CAM_ADDR(x)                                               \
+	(((x) >> BIT_SHIFT_RPFM_CAM_ADDR) & BIT_MASK_RPFM_CAM_ADDR)
+#define BIT_SET_RPFM_CAM_ADDR(x, v)                                            \
+	(BIT_CLEAR_RPFM_CAM_ADDR(x) | BIT_RPFM_CAM_ADDR(v))
+
+/* 2 REG_RPFM_CAM_RWD			(Offset 0x064C) */
+
+#define BIT_SHIFT_RPFM_CAM_RWD 0
+#define BIT_MASK_RPFM_CAM_RWD 0xffffffffL
+#define BIT_RPFM_CAM_RWD(x)                                                    \
+	(((x) & BIT_MASK_RPFM_CAM_RWD) << BIT_SHIFT_RPFM_CAM_RWD)
+#define BITS_RPFM_CAM_RWD (BIT_MASK_RPFM_CAM_RWD << BIT_SHIFT_RPFM_CAM_RWD)
+#define BIT_CLEAR_RPFM_CAM_RWD(x) ((x) & (~BITS_RPFM_CAM_RWD))
+#define BIT_GET_RPFM_CAM_RWD(x)                                                \
+	(((x) >> BIT_SHIFT_RPFM_CAM_RWD) & BIT_MASK_RPFM_CAM_RWD)
+#define BIT_SET_RPFM_CAM_RWD(x, v)                                             \
+	(BIT_CLEAR_RPFM_CAM_RWD(x) | BIT_RPFM_CAM_RWD(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_NAV_CTRL				(Offset 0x0650) */
+
+#define BIT_SHIFT_NAV_UPPER 16
+#define BIT_MASK_NAV_UPPER 0xff
+#define BIT_NAV_UPPER(x) (((x) & BIT_MASK_NAV_UPPER) << BIT_SHIFT_NAV_UPPER)
+#define BITS_NAV_UPPER (BIT_MASK_NAV_UPPER << BIT_SHIFT_NAV_UPPER)
+#define BIT_CLEAR_NAV_UPPER(x) ((x) & (~BITS_NAV_UPPER))
+#define BIT_GET_NAV_UPPER(x) (((x) >> BIT_SHIFT_NAV_UPPER) & BIT_MASK_NAV_UPPER)
+#define BIT_SET_NAV_UPPER(x, v) (BIT_CLEAR_NAV_UPPER(x) | BIT_NAV_UPPER(v))
+
+#define BIT_SHIFT_RXMYRTS_NAV 8
+#define BIT_MASK_RXMYRTS_NAV 0xf
+#define BIT_RXMYRTS_NAV(x)                                                     \
+	(((x) & BIT_MASK_RXMYRTS_NAV) << BIT_SHIFT_RXMYRTS_NAV)
+#define BITS_RXMYRTS_NAV (BIT_MASK_RXMYRTS_NAV << BIT_SHIFT_RXMYRTS_NAV)
+#define BIT_CLEAR_RXMYRTS_NAV(x) ((x) & (~BITS_RXMYRTS_NAV))
+#define BIT_GET_RXMYRTS_NAV(x)                                                 \
+	(((x) >> BIT_SHIFT_RXMYRTS_NAV) & BIT_MASK_RXMYRTS_NAV)
+#define BIT_SET_RXMYRTS_NAV(x, v)                                              \
+	(BIT_CLEAR_RXMYRTS_NAV(x) | BIT_RXMYRTS_NAV(v))
+
+#define BIT_SHIFT_RTSRST 0
+#define BIT_MASK_RTSRST 0xff
+#define BIT_RTSRST(x) (((x) & BIT_MASK_RTSRST) << BIT_SHIFT_RTSRST)
+#define BITS_RTSRST (BIT_MASK_RTSRST << BIT_SHIFT_RTSRST)
+#define BIT_CLEAR_RTSRST(x) ((x) & (~BITS_RTSRST))
+#define BIT_GET_RTSRST(x) (((x) >> BIT_SHIFT_RTSRST) & BIT_MASK_RTSRST)
+#define BIT_SET_RTSRST(x, v) (BIT_CLEAR_RTSRST(x) | BIT_RTSRST(v))
+
+/* 2 REG_BACAMCMD				(Offset 0x0654) */
+
+#define BIT_BACAM_POLL BIT(31)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_BACAMCMD				(Offset 0x0654) */
+
+#define BIT_BACAM_RST BIT(17)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_BACAMCMD				(Offset 0x0654) */
+
+#define BIT_BACAM_RW BIT(16)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_BACAMCMD				(Offset 0x0654) */
+
+#define BIT_SHIFT_TXSBM 14
+#define BIT_MASK_TXSBM 0x3
+#define BIT_TXSBM(x) (((x) & BIT_MASK_TXSBM) << BIT_SHIFT_TXSBM)
+#define BITS_TXSBM (BIT_MASK_TXSBM << BIT_SHIFT_TXSBM)
+#define BIT_CLEAR_TXSBM(x) ((x) & (~BITS_TXSBM))
+#define BIT_GET_TXSBM(x) (((x) >> BIT_SHIFT_TXSBM) & BIT_MASK_TXSBM)
+#define BIT_SET_TXSBM(x, v) (BIT_CLEAR_TXSBM(x) | BIT_TXSBM(v))
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_BACAMCMD				(Offset 0x0654) */
+
+#define BIT_SHIFT_TXSBMPMOD 14
+#define BIT_MASK_TXSBMPMOD 0x3
+#define BIT_TXSBMPMOD(x) (((x) & BIT_MASK_TXSBMPMOD) << BIT_SHIFT_TXSBMPMOD)
+#define BITS_TXSBMPMOD (BIT_MASK_TXSBMPMOD << BIT_SHIFT_TXSBMPMOD)
+#define BIT_CLEAR_TXSBMPMOD(x) ((x) & (~BITS_TXSBMPMOD))
+#define BIT_GET_TXSBMPMOD(x) (((x) >> BIT_SHIFT_TXSBMPMOD) & BIT_MASK_TXSBMPMOD)
+#define BIT_SET_TXSBMPMOD(x, v) (BIT_CLEAR_TXSBMPMOD(x) | BIT_TXSBMPMOD(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_BACAMCMD				(Offset 0x0654) */
+
+#define BIT_SHIFT_BACAM_ADDR 0
+#define BIT_MASK_BACAM_ADDR 0x3f
+#define BIT_BACAM_ADDR(x) (((x) & BIT_MASK_BACAM_ADDR) << BIT_SHIFT_BACAM_ADDR)
+#define BITS_BACAM_ADDR (BIT_MASK_BACAM_ADDR << BIT_SHIFT_BACAM_ADDR)
+#define BIT_CLEAR_BACAM_ADDR(x) ((x) & (~BITS_BACAM_ADDR))
+#define BIT_GET_BACAM_ADDR(x)                                                  \
+	(((x) >> BIT_SHIFT_BACAM_ADDR) & BIT_MASK_BACAM_ADDR)
+#define BIT_SET_BACAM_ADDR(x, v) (BIT_CLEAR_BACAM_ADDR(x) | BIT_BACAM_ADDR(v))
+
+#define BIT_SHIFT_BA_CONTENT_L 0
+#define BIT_MASK_BA_CONTENT_L 0xffffffffL
+#define BIT_BA_CONTENT_L(x)                                                    \
+	(((x) & BIT_MASK_BA_CONTENT_L) << BIT_SHIFT_BA_CONTENT_L)
+#define BITS_BA_CONTENT_L (BIT_MASK_BA_CONTENT_L << BIT_SHIFT_BA_CONTENT_L)
+#define BIT_CLEAR_BA_CONTENT_L(x) ((x) & (~BITS_BA_CONTENT_L))
+#define BIT_GET_BA_CONTENT_L(x)                                                \
+	(((x) >> BIT_SHIFT_BA_CONTENT_L) & BIT_MASK_BA_CONTENT_L)
+#define BIT_SET_BA_CONTENT_L(x, v)                                             \
+	(BIT_CLEAR_BA_CONTENT_L(x) | BIT_BA_CONTENT_L(v))
+
+#define BIT_SHIFT_LBDLY 0
+#define BIT_MASK_LBDLY 0x1f
+#define BIT_LBDLY(x) (((x) & BIT_MASK_LBDLY) << BIT_SHIFT_LBDLY)
+#define BITS_LBDLY (BIT_MASK_LBDLY << BIT_SHIFT_LBDLY)
+#define BIT_CLEAR_LBDLY(x) ((x) & (~BITS_LBDLY))
+#define BIT_GET_LBDLY(x) (((x) >> BIT_SHIFT_LBDLY) & BIT_MASK_LBDLY)
+#define BIT_SET_LBDLY(x, v) (BIT_CLEAR_LBDLY(x) | BIT_LBDLY(v))
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_BITMAP_CMD				(Offset 0x0661) */
+
+#define BIT_BACAM_RPMEN BIT(0)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_WMAC_BACAM_RPMEN			(Offset 0x0661) */
+
+#define BIT_WMAC_BACAM_RPMEN BIT(0)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_TX_RX				(Offset 0x0662) */
+
+#define BIT_SHIFT_RXPKT_TYPE 2
+#define BIT_MASK_RXPKT_TYPE 0x3f
+#define BIT_RXPKT_TYPE(x) (((x) & BIT_MASK_RXPKT_TYPE) << BIT_SHIFT_RXPKT_TYPE)
+#define BITS_RXPKT_TYPE (BIT_MASK_RXPKT_TYPE << BIT_SHIFT_RXPKT_TYPE)
+#define BIT_CLEAR_RXPKT_TYPE(x) ((x) & (~BITS_RXPKT_TYPE))
+#define BIT_GET_RXPKT_TYPE(x)                                                  \
+	(((x) >> BIT_SHIFT_RXPKT_TYPE) & BIT_MASK_RXPKT_TYPE)
+#define BIT_SET_RXPKT_TYPE(x, v) (BIT_CLEAR_RXPKT_TYPE(x) | BIT_RXPKT_TYPE(v))
+
+#define BIT_TXACT_IND BIT(1)
+#define BIT_RXACT_IND BIT(0)
+
+/* 2 REG_WMAC_BITMAP_CTL			(Offset 0x0663) */
+
+#define BIT_BITMAP_VO BIT(7)
+#define BIT_BITMAP_VI BIT(6)
+#define BIT_BITMAP_BE BIT(5)
+#define BIT_BITMAP_BK BIT(4)
+
+#define BIT_SHIFT_BITMAP_CONDITION 2
+#define BIT_MASK_BITMAP_CONDITION 0x3
+#define BIT_BITMAP_CONDITION(x)                                                \
+	(((x) & BIT_MASK_BITMAP_CONDITION) << BIT_SHIFT_BITMAP_CONDITION)
+#define BITS_BITMAP_CONDITION                                                  \
+	(BIT_MASK_BITMAP_CONDITION << BIT_SHIFT_BITMAP_CONDITION)
+#define BIT_CLEAR_BITMAP_CONDITION(x) ((x) & (~BITS_BITMAP_CONDITION))
+#define BIT_GET_BITMAP_CONDITION(x)                                            \
+	(((x) >> BIT_SHIFT_BITMAP_CONDITION) & BIT_MASK_BITMAP_CONDITION)
+#define BIT_SET_BITMAP_CONDITION(x, v)                                         \
+	(BIT_CLEAR_BITMAP_CONDITION(x) | BIT_BITMAP_CONDITION(v))
+
+#define BIT_BITMAP_SSNBK_COUNTER_CLR BIT(1)
+#define BIT_BITMAP_FORCE BIT(0)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_RXERR_RPT				(Offset 0x0664) */
+
+#define BIT_SHIFT_RXERR_RPT_SEL_V1_3_0 28
+#define BIT_MASK_RXERR_RPT_SEL_V1_3_0 0xf
+#define BIT_RXERR_RPT_SEL_V1_3_0(x)                                            \
+	(((x) & BIT_MASK_RXERR_RPT_SEL_V1_3_0)                                 \
+	 << BIT_SHIFT_RXERR_RPT_SEL_V1_3_0)
+#define BITS_RXERR_RPT_SEL_V1_3_0                                              \
+	(BIT_MASK_RXERR_RPT_SEL_V1_3_0 << BIT_SHIFT_RXERR_RPT_SEL_V1_3_0)
+#define BIT_CLEAR_RXERR_RPT_SEL_V1_3_0(x) ((x) & (~BITS_RXERR_RPT_SEL_V1_3_0))
+#define BIT_GET_RXERR_RPT_SEL_V1_3_0(x)                                        \
+	(((x) >> BIT_SHIFT_RXERR_RPT_SEL_V1_3_0) &                             \
+	 BIT_MASK_RXERR_RPT_SEL_V1_3_0)
+#define BIT_SET_RXERR_RPT_SEL_V1_3_0(x, v)                                     \
+	(BIT_CLEAR_RXERR_RPT_SEL_V1_3_0(x) | BIT_RXERR_RPT_SEL_V1_3_0(v))
+
+#endif
+
+#if (HALMAC_8881A_SUPPORT)
+
+/* 2 REG_RXERR_RPT				(Offset 0x0664) */
+
+#define BIT_SHIFT_RXERR_RPT_SEL 28
+#define BIT_MASK_RXERR_RPT_SEL 0xf
+#define BIT_RXERR_RPT_SEL(x)                                                   \
+	(((x) & BIT_MASK_RXERR_RPT_SEL) << BIT_SHIFT_RXERR_RPT_SEL)
+#define BITS_RXERR_RPT_SEL (BIT_MASK_RXERR_RPT_SEL << BIT_SHIFT_RXERR_RPT_SEL)
+#define BIT_CLEAR_RXERR_RPT_SEL(x) ((x) & (~BITS_RXERR_RPT_SEL))
+#define BIT_GET_RXERR_RPT_SEL(x)                                               \
+	(((x) >> BIT_SHIFT_RXERR_RPT_SEL) & BIT_MASK_RXERR_RPT_SEL)
+#define BIT_SET_RXERR_RPT_SEL(x, v)                                            \
+	(BIT_CLEAR_RXERR_RPT_SEL(x) | BIT_RXERR_RPT_SEL(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_RXERR_RPT				(Offset 0x0664) */
+
+#define BIT_RXERR_RPT_RST BIT(27)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_RXERR_RPT				(Offset 0x0664) */
+
+#define BIT_RXERR_RPT_SEL_V1_4 BIT(26)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_RXERR_RPT				(Offset 0x0664) */
+
+#define BIT_SHIFT_UD_SELECT_BSSID_2_1 24
+#define BIT_MASK_UD_SELECT_BSSID_2_1 0x3
+#define BIT_UD_SELECT_BSSID_2_1(x)                                             \
+	(((x) & BIT_MASK_UD_SELECT_BSSID_2_1) << BIT_SHIFT_UD_SELECT_BSSID_2_1)
+#define BITS_UD_SELECT_BSSID_2_1                                               \
+	(BIT_MASK_UD_SELECT_BSSID_2_1 << BIT_SHIFT_UD_SELECT_BSSID_2_1)
+#define BIT_CLEAR_UD_SELECT_BSSID_2_1(x) ((x) & (~BITS_UD_SELECT_BSSID_2_1))
+#define BIT_GET_UD_SELECT_BSSID_2_1(x)                                         \
+	(((x) >> BIT_SHIFT_UD_SELECT_BSSID_2_1) & BIT_MASK_UD_SELECT_BSSID_2_1)
+#define BIT_SET_UD_SELECT_BSSID_2_1(x, v)                                      \
+	(BIT_CLEAR_UD_SELECT_BSSID_2_1(x) | BIT_UD_SELECT_BSSID_2_1(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_RXERR_RPT				(Offset 0x0664) */
+
+#define BIT_W1S BIT(23)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_RXERR_RPT				(Offset 0x0664) */
+
+#define BIT_UD_SELECT_BSSID BIT(22)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_RXERR_RPT				(Offset 0x0664) */
+
+#define BIT_UD_SELECT_BSSID_0 BIT(22)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_RXERR_RPT				(Offset 0x0664) */
+
+#define BIT_SHIFT_UD_SUB_TYPE 18
+#define BIT_MASK_UD_SUB_TYPE 0xf
+#define BIT_UD_SUB_TYPE(x)                                                     \
+	(((x) & BIT_MASK_UD_SUB_TYPE) << BIT_SHIFT_UD_SUB_TYPE)
+#define BITS_UD_SUB_TYPE (BIT_MASK_UD_SUB_TYPE << BIT_SHIFT_UD_SUB_TYPE)
+#define BIT_CLEAR_UD_SUB_TYPE(x) ((x) & (~BITS_UD_SUB_TYPE))
+#define BIT_GET_UD_SUB_TYPE(x)                                                 \
+	(((x) >> BIT_SHIFT_UD_SUB_TYPE) & BIT_MASK_UD_SUB_TYPE)
+#define BIT_SET_UD_SUB_TYPE(x, v)                                              \
+	(BIT_CLEAR_UD_SUB_TYPE(x) | BIT_UD_SUB_TYPE(v))
+
+#define BIT_SHIFT_UD_TYPE 16
+#define BIT_MASK_UD_TYPE 0x3
+#define BIT_UD_TYPE(x) (((x) & BIT_MASK_UD_TYPE) << BIT_SHIFT_UD_TYPE)
+#define BITS_UD_TYPE (BIT_MASK_UD_TYPE << BIT_SHIFT_UD_TYPE)
+#define BIT_CLEAR_UD_TYPE(x) ((x) & (~BITS_UD_TYPE))
+#define BIT_GET_UD_TYPE(x) (((x) >> BIT_SHIFT_UD_TYPE) & BIT_MASK_UD_TYPE)
+#define BIT_SET_UD_TYPE(x, v) (BIT_CLEAR_UD_TYPE(x) | BIT_UD_TYPE(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_RXERR_RPT				(Offset 0x0664) */
+
+#define BIT_CTRLFLT5EN BIT(5)
+#define BIT_CTRLFLT4EN BIT(4)
+#define BIT_CTRLFLT3EN BIT(3)
+#define BIT_CTRLFLT2EN BIT(2)
+#define BIT_CTRLFLT1EN BIT(1)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_RXERR_RPT				(Offset 0x0664) */
+
+#define BIT_SHIFT_RPT_COUNTER 0
+#define BIT_MASK_RPT_COUNTER 0xffff
+#define BIT_RPT_COUNTER(x)                                                     \
+	(((x) & BIT_MASK_RPT_COUNTER) << BIT_SHIFT_RPT_COUNTER)
+#define BITS_RPT_COUNTER (BIT_MASK_RPT_COUNTER << BIT_SHIFT_RPT_COUNTER)
+#define BIT_CLEAR_RPT_COUNTER(x) ((x) & (~BITS_RPT_COUNTER))
+#define BIT_GET_RPT_COUNTER(x)                                                 \
+	(((x) >> BIT_SHIFT_RPT_COUNTER) & BIT_MASK_RPT_COUNTER)
+#define BIT_SET_RPT_COUNTER(x, v)                                              \
+	(BIT_CLEAR_RPT_COUNTER(x) | BIT_RPT_COUNTER(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_RXERR_RPT				(Offset 0x0664) */
+
+#define BIT_CTRLFLT0EN BIT(0)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822B_SUPPORT)
+
+/* 2 REG_WMAC_TRXPTCL_CTL			(Offset 0x0668) */
+
+#define BIT_RXBA_IGNOREA2 BIT(42)
+#define BIT_EN_SAVE_ALL_TXOPADDR BIT(41)
+#define BIT_EN_TXCTS_TO_TXOPOWNER_INRXNAV BIT(40)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT || \
+     HALMAC_8881A_SUPPORT)
+
+/* 2 REG_WMAC_TRXPTCL_CTL			(Offset 0x0668) */
+
+#define BIT_DIS_TXBA_AMPDUFCSERR BIT(39)
+#define BIT_DIS_TXBA_RXBARINFULL BIT(38)
+#define BIT_DIS_TXCFE_INFULL BIT(37)
+#define BIT_DIS_TXCTS_INFULL BIT(36)
+#define BIT_EN_TXACKBA_IN_TX_RDG BIT(35)
+#define BIT_EN_TXACKBA_IN_TXOP BIT(34)
+#define BIT_EN_TXCTS_IN_RXNAV BIT(33)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_WMAC_TRXPTCL_CTL			(Offset 0x0668) */
+
+#define BIT_EN_TXCTS_INTXOP BIT(32)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8881A_SUPPORT)
+
+/* 2 REG_WMAC_TRXPTCL_CTL			(Offset 0x0668) */
+
+#define BIT_BLK_EDCA_BBSLP BIT(31)
+#define BIT_BLK_EDCA_BBSBY BIT(30)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_WMAC_TRXPTCL_CTL			(Offset 0x0668) */
+
+#define BIT_ACKTO_BLOCK_SCH_EN BIT(27)
+#define BIT_EIFS_BLOCK_SCH_EN BIT(26)
+#define BIT_PLCPCHK_RST_EIFS BIT(25)
+#define BIT_CCA_RST_EIFS BIT(24)
+#define BIT_DIS_UPD_MYRXPKTNAV BIT(23)
+#define BIT_EARLY_TXBA BIT(22)
+
+#define BIT_SHIFT_RESP_CHNBUSY 20
+#define BIT_MASK_RESP_CHNBUSY 0x3
+#define BIT_RESP_CHNBUSY(x)                                                    \
+	(((x) & BIT_MASK_RESP_CHNBUSY) << BIT_SHIFT_RESP_CHNBUSY)
+#define BITS_RESP_CHNBUSY (BIT_MASK_RESP_CHNBUSY << BIT_SHIFT_RESP_CHNBUSY)
+#define BIT_CLEAR_RESP_CHNBUSY(x) ((x) & (~BITS_RESP_CHNBUSY))
+#define BIT_GET_RESP_CHNBUSY(x)                                                \
+	(((x) >> BIT_SHIFT_RESP_CHNBUSY) & BIT_MASK_RESP_CHNBUSY)
+#define BIT_SET_RESP_CHNBUSY(x, v)                                             \
+	(BIT_CLEAR_RESP_CHNBUSY(x) | BIT_RESP_CHNBUSY(v))
+
+#define BIT_RESP_DCTS_EN BIT(19)
+#define BIT_RESP_DCFE_EN BIT(18)
+#define BIT_RESP_SPLCPEN BIT(17)
+#define BIT_RESP_SGIEN BIT(16)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_WMAC_TRXPTCL_CTL			(Offset 0x0668) */
+
+#define BIT_RESP_LDPC_EN BIT(15)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_WMAC_TRXPTCL_CTL			(Offset 0x0668) */
+
+#define BIT_MGTFLT15EN BIT(15)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_WMAC_TRXPTCL_CTL			(Offset 0x0668) */
+
+#define BIT_DIS_RESP_ACKINCCA BIT(14)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_WMAC_TRXPTCL_CTL			(Offset 0x0668) */
+
+#define BIT_MGTFLT14EN BIT(14)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_WMAC_TRXPTCL_CTL			(Offset 0x0668) */
+
+#define BIT_DIS_RESP_CTSINCCA BIT(13)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8881A_SUPPORT)
+
+/* 2 REG_WMAC_TRXPTCL_CTL			(Offset 0x0668) */
+
+#define BIT_SHIFT_R_WMAC_SECOND_CCA_TIMER 10
+#define BIT_MASK_R_WMAC_SECOND_CCA_TIMER 0x7
+#define BIT_R_WMAC_SECOND_CCA_TIMER(x)                                         \
+	(((x) & BIT_MASK_R_WMAC_SECOND_CCA_TIMER)                              \
+	 << BIT_SHIFT_R_WMAC_SECOND_CCA_TIMER)
+#define BITS_R_WMAC_SECOND_CCA_TIMER                                           \
+	(BIT_MASK_R_WMAC_SECOND_CCA_TIMER << BIT_SHIFT_R_WMAC_SECOND_CCA_TIMER)
+#define BIT_CLEAR_R_WMAC_SECOND_CCA_TIMER(x)                                   \
+	((x) & (~BITS_R_WMAC_SECOND_CCA_TIMER))
+#define BIT_GET_R_WMAC_SECOND_CCA_TIMER(x)                                     \
+	(((x) >> BIT_SHIFT_R_WMAC_SECOND_CCA_TIMER) &                          \
+	 BIT_MASK_R_WMAC_SECOND_CCA_TIMER)
+#define BIT_SET_R_WMAC_SECOND_CCA_TIMER(x, v)                                  \
+	(BIT_CLEAR_R_WMAC_SECOND_CCA_TIMER(x) | BIT_R_WMAC_SECOND_CCA_TIMER(v))
+
+#endif
+
+#if (HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_WMAC_TRXPTCL_CTL			(Offset 0x0668) */
+
+#define BIT_SHIFT_SECOND_CCA_CNT 10
+#define BIT_MASK_SECOND_CCA_CNT 0x7
+#define BIT_SECOND_CCA_CNT(x)                                                  \
+	(((x) & BIT_MASK_SECOND_CCA_CNT) << BIT_SHIFT_SECOND_CCA_CNT)
+#define BITS_SECOND_CCA_CNT                                                    \
+	(BIT_MASK_SECOND_CCA_CNT << BIT_SHIFT_SECOND_CCA_CNT)
+#define BIT_CLEAR_SECOND_CCA_CNT(x) ((x) & (~BITS_SECOND_CCA_CNT))
+#define BIT_GET_SECOND_CCA_CNT(x)                                              \
+	(((x) >> BIT_SHIFT_SECOND_CCA_CNT) & BIT_MASK_SECOND_CCA_CNT)
+#define BIT_SET_SECOND_CCA_CNT(x, v)                                           \
+	(BIT_CLEAR_SECOND_CCA_CNT(x) | BIT_SECOND_CCA_CNT(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8881A_SUPPORT)
+
+/* 2 REG_WMAC_TRXPTCL_CTL			(Offset 0x0668) */
+
+#define BIT_SHIFT_RFMOD 7
+#define BIT_MASK_RFMOD 0x3
+#define BIT_RFMOD(x) (((x) & BIT_MASK_RFMOD) << BIT_SHIFT_RFMOD)
+#define BITS_RFMOD (BIT_MASK_RFMOD << BIT_SHIFT_RFMOD)
+#define BIT_CLEAR_RFMOD(x) ((x) & (~BITS_RFMOD))
+#define BIT_GET_RFMOD(x) (((x) >> BIT_SHIFT_RFMOD) & BIT_MASK_RFMOD)
+#define BIT_SET_RFMOD(x, v) (BIT_CLEAR_RFMOD(x) | BIT_RFMOD(v))
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_WMAC_TRXPTCL_CTL			(Offset 0x0668) */
+
+#define BIT_MGTFLT7EN BIT(7)
+
+#endif
+
+#if (HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_WMAC_TRXPTCL_CTL			(Offset 0x0668) */
+
+#define BIT_SHIFT_RF_MOD 7
+#define BIT_MASK_RF_MOD 0x3
+#define BIT_RF_MOD(x) (((x) & BIT_MASK_RF_MOD) << BIT_SHIFT_RF_MOD)
+#define BITS_RF_MOD (BIT_MASK_RF_MOD << BIT_SHIFT_RF_MOD)
+#define BIT_CLEAR_RF_MOD(x) ((x) & (~BITS_RF_MOD))
+#define BIT_GET_RF_MOD(x) (((x) >> BIT_SHIFT_RF_MOD) & BIT_MASK_RF_MOD)
+#define BIT_SET_RF_MOD(x, v) (BIT_CLEAR_RF_MOD(x) | BIT_RF_MOD(v))
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_WMAC_TRXPTCL_CTL			(Offset 0x0668) */
+
+#define BIT_MGTFLT6EN BIT(6)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8881A_SUPPORT)
+
+/* 2 REG_WMAC_TRXPTCL_CTL			(Offset 0x0668) */
+
+#define BIT_SHIFT_RESP_CTS_DYNBW_SEL 5
+#define BIT_MASK_RESP_CTS_DYNBW_SEL 0x3
+#define BIT_RESP_CTS_DYNBW_SEL(x)                                              \
+	(((x) & BIT_MASK_RESP_CTS_DYNBW_SEL) << BIT_SHIFT_RESP_CTS_DYNBW_SEL)
+#define BITS_RESP_CTS_DYNBW_SEL                                                \
+	(BIT_MASK_RESP_CTS_DYNBW_SEL << BIT_SHIFT_RESP_CTS_DYNBW_SEL)
+#define BIT_CLEAR_RESP_CTS_DYNBW_SEL(x) ((x) & (~BITS_RESP_CTS_DYNBW_SEL))
+#define BIT_GET_RESP_CTS_DYNBW_SEL(x)                                          \
+	(((x) >> BIT_SHIFT_RESP_CTS_DYNBW_SEL) & BIT_MASK_RESP_CTS_DYNBW_SEL)
+#define BIT_SET_RESP_CTS_DYNBW_SEL(x, v)                                       \
+	(BIT_CLEAR_RESP_CTS_DYNBW_SEL(x) | BIT_RESP_CTS_DYNBW_SEL(v))
+
+#endif
+
+#if (HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_WMAC_TRXPTCL_CTL			(Offset 0x0668) */
+
+#define BIT_SHIFT_RESP_CTS_BW_DYNBW_SEL 5
+#define BIT_MASK_RESP_CTS_BW_DYNBW_SEL 0x3
+#define BIT_RESP_CTS_BW_DYNBW_SEL(x)                                           \
+	(((x) & BIT_MASK_RESP_CTS_BW_DYNBW_SEL)                                \
+	 << BIT_SHIFT_RESP_CTS_BW_DYNBW_SEL)
+#define BITS_RESP_CTS_BW_DYNBW_SEL                                             \
+	(BIT_MASK_RESP_CTS_BW_DYNBW_SEL << BIT_SHIFT_RESP_CTS_BW_DYNBW_SEL)
+#define BIT_CLEAR_RESP_CTS_BW_DYNBW_SEL(x) ((x) & (~BITS_RESP_CTS_BW_DYNBW_SEL))
+#define BIT_GET_RESP_CTS_BW_DYNBW_SEL(x)                                       \
+	(((x) >> BIT_SHIFT_RESP_CTS_BW_DYNBW_SEL) &                            \
+	 BIT_MASK_RESP_CTS_BW_DYNBW_SEL)
+#define BIT_SET_RESP_CTS_BW_DYNBW_SEL(x, v)                                    \
+	(BIT_CLEAR_RESP_CTS_BW_DYNBW_SEL(x) | BIT_RESP_CTS_BW_DYNBW_SEL(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8881A_SUPPORT)
+
+/* 2 REG_WMAC_TRXPTCL_CTL			(Offset 0x0668) */
+
+#define BIT_DLY_TX_WAIT_RXANTSEL BIT(4)
+
+#endif
+
+#if (HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_WMAC_TRXPTCL_CTL			(Offset 0x0668) */
+
+#define BIT_DELAY_TX_USE_RX_ANTSEL BIT(4)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8881A_SUPPORT)
+
+/* 2 REG_WMAC_TRXPTCL_CTL			(Offset 0x0668) */
+
+#define BIT_TXRESP_BY_RXANTSEL BIT(3)
+
+#endif
+
+#if (HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_WMAC_TRXPTCL_CTL			(Offset 0x0668) */
+
+#define BIT_TX_USE_RX_ANTSEL BIT(3)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_WMAC_TRXPTCL_CTL			(Offset 0x0668) */
+
+#define BIT_RESP_EARLY_TXACK_RWEPTKIP BIT(2)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_WMAC_TRXPTCL_CTL			(Offset 0x0668) */
+
+#define BIT_SHIFT_ORIG_DCTS_CHK 0
+#define BIT_MASK_ORIG_DCTS_CHK 0x3
+#define BIT_ORIG_DCTS_CHK(x)                                                   \
+	(((x) & BIT_MASK_ORIG_DCTS_CHK) << BIT_SHIFT_ORIG_DCTS_CHK)
+#define BITS_ORIG_DCTS_CHK (BIT_MASK_ORIG_DCTS_CHK << BIT_SHIFT_ORIG_DCTS_CHK)
+#define BIT_CLEAR_ORIG_DCTS_CHK(x) ((x) & (~BITS_ORIG_DCTS_CHK))
+#define BIT_GET_ORIG_DCTS_CHK(x)                                               \
+	(((x) >> BIT_SHIFT_ORIG_DCTS_CHK) & BIT_MASK_ORIG_DCTS_CHK)
+#define BIT_SET_ORIG_DCTS_CHK(x, v)                                            \
+	(BIT_CLEAR_ORIG_DCTS_CHK(x) | BIT_ORIG_DCTS_CHK(v))
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_WMAC_TRXPTCL_CTL_H			(Offset 0x066C) */
+
+#define BIT_RXBA_IGNOREA2_V1 BIT(10)
+#define BIT_EN_SAVE_ALL_TXOPADDR_V1 BIT(9)
+#define BIT_EN_TXCTS_TO_TXOPOWNER_INRXNAV_V1 BIT(8)
+#define BIT_DIS_TXBA_AMPDUFCSERR_V1 BIT(7)
+#define BIT_DIS_TXBA_RXBARINFULL_V1 BIT(6)
+#define BIT_DIS_TXCFE_INFULL_V1 BIT(5)
+#define BIT_DIS_TXCTS_INFULL_V1 BIT(4)
+#define BIT_EN_TXACKBA_IN_TX_RDG_V1 BIT(3)
+#define BIT_EN_TXACKBA_IN_TXOP_V1 BIT(2)
+#define BIT_EN_TXCTS_IN_RXNAV_V1 BIT(1)
+#define BIT_EN_TXCTS_INTXOP_V1 BIT(0)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_CAMCMD				(Offset 0x0670) */
+
+#define BIT_SECCAM_POLLING BIT(31)
+#define BIT_SECCAM_CLR BIT(30)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_CAMCMD				(Offset 0x0670) */
+
+#define BIT_MFBCAM_CLR BIT(29)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_CAMCMD				(Offset 0x0670) */
+
+#define BIT_SHIFT_RESP_TXPOWER 18
+#define BIT_MASK_RESP_TXPOWER 0x7
+#define BIT_RESP_TXPOWER(x)                                                    \
+	(((x) & BIT_MASK_RESP_TXPOWER) << BIT_SHIFT_RESP_TXPOWER)
+#define BITS_RESP_TXPOWER (BIT_MASK_RESP_TXPOWER << BIT_SHIFT_RESP_TXPOWER)
+#define BIT_CLEAR_RESP_TXPOWER(x) ((x) & (~BITS_RESP_TXPOWER))
+#define BIT_GET_RESP_TXPOWER(x)                                                \
+	(((x) >> BIT_SHIFT_RESP_TXPOWER) & BIT_MASK_RESP_TXPOWER)
+#define BIT_SET_RESP_TXPOWER(x, v)                                             \
+	(BIT_CLEAR_RESP_TXPOWER(x) | BIT_RESP_TXPOWER(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_CAMCMD				(Offset 0x0670) */
+
+#define BIT_SECCAM_WE BIT(16)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_CAMCMD				(Offset 0x0670) */
+
+#define BIT_SHIFT_SECCAM_ADDR_V1 0
+#define BIT_MASK_SECCAM_ADDR_V1 0xff
+#define BIT_SECCAM_ADDR_V1(x)                                                  \
+	(((x) & BIT_MASK_SECCAM_ADDR_V1) << BIT_SHIFT_SECCAM_ADDR_V1)
+#define BITS_SECCAM_ADDR_V1                                                    \
+	(BIT_MASK_SECCAM_ADDR_V1 << BIT_SHIFT_SECCAM_ADDR_V1)
+#define BIT_CLEAR_SECCAM_ADDR_V1(x) ((x) & (~BITS_SECCAM_ADDR_V1))
+#define BIT_GET_SECCAM_ADDR_V1(x)                                              \
+	(((x) >> BIT_SHIFT_SECCAM_ADDR_V1) & BIT_MASK_SECCAM_ADDR_V1)
+#define BIT_SET_SECCAM_ADDR_V1(x, v)                                           \
+	(BIT_CLEAR_SECCAM_ADDR_V1(x) | BIT_SECCAM_ADDR_V1(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_CAMCMD				(Offset 0x0670) */
+
+#define BIT_SHIFT_SECCAM_ADDR_V2 0
+#define BIT_MASK_SECCAM_ADDR_V2 0x3ff
+#define BIT_SECCAM_ADDR_V2(x)                                                  \
+	(((x) & BIT_MASK_SECCAM_ADDR_V2) << BIT_SHIFT_SECCAM_ADDR_V2)
+#define BITS_SECCAM_ADDR_V2                                                    \
+	(BIT_MASK_SECCAM_ADDR_V2 << BIT_SHIFT_SECCAM_ADDR_V2)
+#define BIT_CLEAR_SECCAM_ADDR_V2(x) ((x) & (~BITS_SECCAM_ADDR_V2))
+#define BIT_GET_SECCAM_ADDR_V2(x)                                              \
+	(((x) >> BIT_SHIFT_SECCAM_ADDR_V2) & BIT_MASK_SECCAM_ADDR_V2)
+#define BIT_SET_SECCAM_ADDR_V2(x, v)                                           \
+	(BIT_CLEAR_SECCAM_ADDR_V2(x) | BIT_SECCAM_ADDR_V2(v))
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_CAMCMD				(Offset 0x0670) */
+
+#define BIT_SHIFT_SECCAM_ADDR 0
+#define BIT_MASK_SECCAM_ADDR 0xff
+#define BIT_SECCAM_ADDR(x)                                                     \
+	(((x) & BIT_MASK_SECCAM_ADDR) << BIT_SHIFT_SECCAM_ADDR)
+#define BITS_SECCAM_ADDR (BIT_MASK_SECCAM_ADDR << BIT_SHIFT_SECCAM_ADDR)
+#define BIT_CLEAR_SECCAM_ADDR(x) ((x) & (~BITS_SECCAM_ADDR))
+#define BIT_GET_SECCAM_ADDR(x)                                                 \
+	(((x) >> BIT_SHIFT_SECCAM_ADDR) & BIT_MASK_SECCAM_ADDR)
+#define BIT_SET_SECCAM_ADDR(x, v)                                              \
+	(BIT_CLEAR_SECCAM_ADDR(x) | BIT_SECCAM_ADDR(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_CAMWRITE				(Offset 0x0674) */
+
+#define BIT_SHIFT_CAMW_DATA 0
+#define BIT_MASK_CAMW_DATA 0xffffffffL
+#define BIT_CAMW_DATA(x) (((x) & BIT_MASK_CAMW_DATA) << BIT_SHIFT_CAMW_DATA)
+#define BITS_CAMW_DATA (BIT_MASK_CAMW_DATA << BIT_SHIFT_CAMW_DATA)
+#define BIT_CLEAR_CAMW_DATA(x) ((x) & (~BITS_CAMW_DATA))
+#define BIT_GET_CAMW_DATA(x) (((x) >> BIT_SHIFT_CAMW_DATA) & BIT_MASK_CAMW_DATA)
+#define BIT_SET_CAMW_DATA(x, v) (BIT_CLEAR_CAMW_DATA(x) | BIT_CAMW_DATA(v))
+
+/* 2 REG_CAMREAD				(Offset 0x0678) */
+
+#define BIT_SHIFT_CAMR_DATA 0
+#define BIT_MASK_CAMR_DATA 0xffffffffL
+#define BIT_CAMR_DATA(x) (((x) & BIT_MASK_CAMR_DATA) << BIT_SHIFT_CAMR_DATA)
+#define BITS_CAMR_DATA (BIT_MASK_CAMR_DATA << BIT_SHIFT_CAMR_DATA)
+#define BIT_CLEAR_CAMR_DATA(x) ((x) & (~BITS_CAMR_DATA))
+#define BIT_GET_CAMR_DATA(x) (((x) >> BIT_SHIFT_CAMR_DATA) & BIT_MASK_CAMR_DATA)
+#define BIT_SET_CAMR_DATA(x, v) (BIT_CLEAR_CAMR_DATA(x) | BIT_CAMR_DATA(v))
+
+/* 2 REG_CAMDBG				(Offset 0x067C) */
+
+#define BIT_SECCAM_INFO BIT(31)
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+/* 2 REG_CAMDBG				(Offset 0x067C) */
+
+#define BIT_SEC_KEYFOUND_V1 BIT(19)
+
+#define BIT_SHIFT_CAMDBG_SEC_TYPE_V1 16
+#define BIT_MASK_CAMDBG_SEC_TYPE_V1 0x7
+#define BIT_CAMDBG_SEC_TYPE_V1(x)                                              \
+	(((x) & BIT_MASK_CAMDBG_SEC_TYPE_V1) << BIT_SHIFT_CAMDBG_SEC_TYPE_V1)
+#define BITS_CAMDBG_SEC_TYPE_V1                                                \
+	(BIT_MASK_CAMDBG_SEC_TYPE_V1 << BIT_SHIFT_CAMDBG_SEC_TYPE_V1)
+#define BIT_CLEAR_CAMDBG_SEC_TYPE_V1(x) ((x) & (~BITS_CAMDBG_SEC_TYPE_V1))
+#define BIT_GET_CAMDBG_SEC_TYPE_V1(x)                                          \
+	(((x) >> BIT_SHIFT_CAMDBG_SEC_TYPE_V1) & BIT_MASK_CAMDBG_SEC_TYPE_V1)
+#define BIT_SET_CAMDBG_SEC_TYPE_V1(x, v)                                       \
+	(BIT_CLEAR_CAMDBG_SEC_TYPE_V1(x) | BIT_CAMDBG_SEC_TYPE_V1(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_CAMDBG				(Offset 0x067C) */
+
+#define BIT_SEC_KEYFOUND BIT(15)
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+/* 2 REG_CAMDBG				(Offset 0x067C) */
+
+#define BIT_CAMDBG_EXT_SEC_TYPE_V1 BIT(15)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_CAMDBG				(Offset 0x067C) */
+
+#define BIT_SHIFT_CAMDBG_SEC_TYPE 12
+#define BIT_MASK_CAMDBG_SEC_TYPE 0x7
+#define BIT_CAMDBG_SEC_TYPE(x)                                                 \
+	(((x) & BIT_MASK_CAMDBG_SEC_TYPE) << BIT_SHIFT_CAMDBG_SEC_TYPE)
+#define BITS_CAMDBG_SEC_TYPE                                                   \
+	(BIT_MASK_CAMDBG_SEC_TYPE << BIT_SHIFT_CAMDBG_SEC_TYPE)
+#define BIT_CLEAR_CAMDBG_SEC_TYPE(x) ((x) & (~BITS_CAMDBG_SEC_TYPE))
+#define BIT_GET_CAMDBG_SEC_TYPE(x)                                             \
+	(((x) >> BIT_SHIFT_CAMDBG_SEC_TYPE) & BIT_MASK_CAMDBG_SEC_TYPE)
+#define BIT_SET_CAMDBG_SEC_TYPE(x, v)                                          \
+	(BIT_CLEAR_CAMDBG_SEC_TYPE(x) | BIT_CAMDBG_SEC_TYPE(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT)
+
+/* 2 REG_CAMDBG				(Offset 0x067C) */
+
+#define BIT_CAMDBG_EXT_SEC_TYPE BIT(11)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_CAMDBG				(Offset 0x067C) */
+
+#define BIT_CAMDBG_EXT_SECTYPE BIT(11)
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+/* 2 REG_CAMDBG				(Offset 0x067C) */
+
+#define BIT_SHIFT_CAMDBG_MIC_KEY_IDX_V1 7
+#define BIT_MASK_CAMDBG_MIC_KEY_IDX_V1 0x7f
+#define BIT_CAMDBG_MIC_KEY_IDX_V1(x)                                           \
+	(((x) & BIT_MASK_CAMDBG_MIC_KEY_IDX_V1)                                \
+	 << BIT_SHIFT_CAMDBG_MIC_KEY_IDX_V1)
+#define BITS_CAMDBG_MIC_KEY_IDX_V1                                             \
+	(BIT_MASK_CAMDBG_MIC_KEY_IDX_V1 << BIT_SHIFT_CAMDBG_MIC_KEY_IDX_V1)
+#define BIT_CLEAR_CAMDBG_MIC_KEY_IDX_V1(x) ((x) & (~BITS_CAMDBG_MIC_KEY_IDX_V1))
+#define BIT_GET_CAMDBG_MIC_KEY_IDX_V1(x)                                       \
+	(((x) >> BIT_SHIFT_CAMDBG_MIC_KEY_IDX_V1) &                            \
+	 BIT_MASK_CAMDBG_MIC_KEY_IDX_V1)
+#define BIT_SET_CAMDBG_MIC_KEY_IDX_V1(x, v)                                    \
+	(BIT_CLEAR_CAMDBG_MIC_KEY_IDX_V1(x) | BIT_CAMDBG_MIC_KEY_IDX_V1(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_CAMDBG				(Offset 0x067C) */
+
+#define BIT_SHIFT_CAMDBG_MIC_KEY_IDX 5
+#define BIT_MASK_CAMDBG_MIC_KEY_IDX 0x1f
+#define BIT_CAMDBG_MIC_KEY_IDX(x)                                              \
+	(((x) & BIT_MASK_CAMDBG_MIC_KEY_IDX) << BIT_SHIFT_CAMDBG_MIC_KEY_IDX)
+#define BITS_CAMDBG_MIC_KEY_IDX                                                \
+	(BIT_MASK_CAMDBG_MIC_KEY_IDX << BIT_SHIFT_CAMDBG_MIC_KEY_IDX)
+#define BIT_CLEAR_CAMDBG_MIC_KEY_IDX(x) ((x) & (~BITS_CAMDBG_MIC_KEY_IDX))
+#define BIT_GET_CAMDBG_MIC_KEY_IDX(x)                                          \
+	(((x) >> BIT_SHIFT_CAMDBG_MIC_KEY_IDX) & BIT_MASK_CAMDBG_MIC_KEY_IDX)
+#define BIT_SET_CAMDBG_MIC_KEY_IDX(x, v)                                       \
+	(BIT_CLEAR_CAMDBG_MIC_KEY_IDX(x) | BIT_CAMDBG_MIC_KEY_IDX(v))
+
+#define BIT_SHIFT_CAMDBG_SEC_KEY_IDX 0
+#define BIT_MASK_CAMDBG_SEC_KEY_IDX 0x1f
+#define BIT_CAMDBG_SEC_KEY_IDX(x)                                              \
+	(((x) & BIT_MASK_CAMDBG_SEC_KEY_IDX) << BIT_SHIFT_CAMDBG_SEC_KEY_IDX)
+#define BITS_CAMDBG_SEC_KEY_IDX                                                \
+	(BIT_MASK_CAMDBG_SEC_KEY_IDX << BIT_SHIFT_CAMDBG_SEC_KEY_IDX)
+#define BIT_CLEAR_CAMDBG_SEC_KEY_IDX(x) ((x) & (~BITS_CAMDBG_SEC_KEY_IDX))
+#define BIT_GET_CAMDBG_SEC_KEY_IDX(x)                                          \
+	(((x) >> BIT_SHIFT_CAMDBG_SEC_KEY_IDX) & BIT_MASK_CAMDBG_SEC_KEY_IDX)
+#define BIT_SET_CAMDBG_SEC_KEY_IDX(x, v)                                       \
+	(BIT_CLEAR_CAMDBG_SEC_KEY_IDX(x) | BIT_CAMDBG_SEC_KEY_IDX(v))
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+/* 2 REG_CAMDBG				(Offset 0x067C) */
+
+#define BIT_SHIFT_CAMDBG_SEC_KEY_IDX_V1 0
+#define BIT_MASK_CAMDBG_SEC_KEY_IDX_V1 0x7f
+#define BIT_CAMDBG_SEC_KEY_IDX_V1(x)                                           \
+	(((x) & BIT_MASK_CAMDBG_SEC_KEY_IDX_V1)                                \
+	 << BIT_SHIFT_CAMDBG_SEC_KEY_IDX_V1)
+#define BITS_CAMDBG_SEC_KEY_IDX_V1                                             \
+	(BIT_MASK_CAMDBG_SEC_KEY_IDX_V1 << BIT_SHIFT_CAMDBG_SEC_KEY_IDX_V1)
+#define BIT_CLEAR_CAMDBG_SEC_KEY_IDX_V1(x) ((x) & (~BITS_CAMDBG_SEC_KEY_IDX_V1))
+#define BIT_GET_CAMDBG_SEC_KEY_IDX_V1(x)                                       \
+	(((x) >> BIT_SHIFT_CAMDBG_SEC_KEY_IDX_V1) &                            \
+	 BIT_MASK_CAMDBG_SEC_KEY_IDX_V1)
+#define BIT_SET_CAMDBG_SEC_KEY_IDX_V1(x, v)                                    \
+	(BIT_CLEAR_CAMDBG_SEC_KEY_IDX_V1(x) | BIT_CAMDBG_SEC_KEY_IDX_V1(v))
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_SECCFG				(Offset 0x0680) */
+
+#define BIT_RXDEC_BM_MGNT_V1 BIT(19)
+#define BIT_TXENC_BM_MGNT_V1 BIT(18)
+#define BIT_RXDEC_UNI_MGNT_V1 BIT(17)
+#define BIT_TXENC_UNI_MGNT_V1 BIT(16)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_SECCFG				(Offset 0x0680) */
+
+#define BIT_DIS_GCLK_WAPI BIT(15)
+#define BIT_DIS_GCLK_AES BIT(14)
+#define BIT_DIS_GCLK_TKIP BIT(13)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_SECCFG				(Offset 0x0680) */
+
+#define BIT_AES_SEL_QC_1 BIT(12)
+#define BIT_AES_SEL_QC_0 BIT(11)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_SECCFG				(Offset 0x0680) */
+
+#define BIT_WMAC_CKECK_BMC BIT(9)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_SECCFG				(Offset 0x0680) */
+
+#define BIT_CHK_BMC BIT(9)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_SECCFG				(Offset 0x0680) */
+
+#define BIT_CHK_KEYID BIT(8)
+#define BIT_RXBCUSEDK BIT(7)
+#define BIT_TXBCUSEDK BIT(6)
+#define BIT_NOSKMC BIT(5)
+#define BIT_SKBYA2 BIT(4)
+#define BIT_RXDEC BIT(3)
+#define BIT_TXENC BIT(2)
+#define BIT_RXUHUSEDK BIT(1)
+#define BIT_TXUHUSEDK BIT(0)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_RXFILTER_CATEGORY_1			(Offset 0x0682) */
+
+#define BIT_SHIFT_RXFILTER_CATEGORY_1 0
+#define BIT_MASK_RXFILTER_CATEGORY_1 0xff
+#define BIT_RXFILTER_CATEGORY_1(x)                                             \
+	(((x) & BIT_MASK_RXFILTER_CATEGORY_1) << BIT_SHIFT_RXFILTER_CATEGORY_1)
+#define BITS_RXFILTER_CATEGORY_1                                               \
+	(BIT_MASK_RXFILTER_CATEGORY_1 << BIT_SHIFT_RXFILTER_CATEGORY_1)
+#define BIT_CLEAR_RXFILTER_CATEGORY_1(x) ((x) & (~BITS_RXFILTER_CATEGORY_1))
+#define BIT_GET_RXFILTER_CATEGORY_1(x)                                         \
+	(((x) >> BIT_SHIFT_RXFILTER_CATEGORY_1) & BIT_MASK_RXFILTER_CATEGORY_1)
+#define BIT_SET_RXFILTER_CATEGORY_1(x, v)                                      \
+	(BIT_CLEAR_RXFILTER_CATEGORY_1(x) | BIT_RXFILTER_CATEGORY_1(v))
+
+/* 2 REG_RXFILTER_ACTION_1			(Offset 0x0683) */
+
+#define BIT_SHIFT_RXFILTER_ACTION_1 0
+#define BIT_MASK_RXFILTER_ACTION_1 0xff
+#define BIT_RXFILTER_ACTION_1(x)                                               \
+	(((x) & BIT_MASK_RXFILTER_ACTION_1) << BIT_SHIFT_RXFILTER_ACTION_1)
+#define BITS_RXFILTER_ACTION_1                                                 \
+	(BIT_MASK_RXFILTER_ACTION_1 << BIT_SHIFT_RXFILTER_ACTION_1)
+#define BIT_CLEAR_RXFILTER_ACTION_1(x) ((x) & (~BITS_RXFILTER_ACTION_1))
+#define BIT_GET_RXFILTER_ACTION_1(x)                                           \
+	(((x) >> BIT_SHIFT_RXFILTER_ACTION_1) & BIT_MASK_RXFILTER_ACTION_1)
+#define BIT_SET_RXFILTER_ACTION_1(x, v)                                        \
+	(BIT_CLEAR_RXFILTER_ACTION_1(x) | BIT_RXFILTER_ACTION_1(v))
+
+/* 2 REG_RXFILTER_CATEGORY_2			(Offset 0x0684) */
+
+#define BIT_SHIFT_RXFILTER_CATEGORY_2 0
+#define BIT_MASK_RXFILTER_CATEGORY_2 0xff
+#define BIT_RXFILTER_CATEGORY_2(x)                                             \
+	(((x) & BIT_MASK_RXFILTER_CATEGORY_2) << BIT_SHIFT_RXFILTER_CATEGORY_2)
+#define BITS_RXFILTER_CATEGORY_2                                               \
+	(BIT_MASK_RXFILTER_CATEGORY_2 << BIT_SHIFT_RXFILTER_CATEGORY_2)
+#define BIT_CLEAR_RXFILTER_CATEGORY_2(x) ((x) & (~BITS_RXFILTER_CATEGORY_2))
+#define BIT_GET_RXFILTER_CATEGORY_2(x)                                         \
+	(((x) >> BIT_SHIFT_RXFILTER_CATEGORY_2) & BIT_MASK_RXFILTER_CATEGORY_2)
+#define BIT_SET_RXFILTER_CATEGORY_2(x, v)                                      \
+	(BIT_CLEAR_RXFILTER_CATEGORY_2(x) | BIT_RXFILTER_CATEGORY_2(v))
+
+/* 2 REG_RXFILTER_ACTION_2			(Offset 0x0685) */
+
+#define BIT_SHIFT_RXFILTER_ACTION_2 0
+#define BIT_MASK_RXFILTER_ACTION_2 0xff
+#define BIT_RXFILTER_ACTION_2(x)                                               \
+	(((x) & BIT_MASK_RXFILTER_ACTION_2) << BIT_SHIFT_RXFILTER_ACTION_2)
+#define BITS_RXFILTER_ACTION_2                                                 \
+	(BIT_MASK_RXFILTER_ACTION_2 << BIT_SHIFT_RXFILTER_ACTION_2)
+#define BIT_CLEAR_RXFILTER_ACTION_2(x) ((x) & (~BITS_RXFILTER_ACTION_2))
+#define BIT_GET_RXFILTER_ACTION_2(x)                                           \
+	(((x) >> BIT_SHIFT_RXFILTER_ACTION_2) & BIT_MASK_RXFILTER_ACTION_2)
+#define BIT_SET_RXFILTER_ACTION_2(x, v)                                        \
+	(BIT_CLEAR_RXFILTER_ACTION_2(x) | BIT_RXFILTER_ACTION_2(v))
+
+/* 2 REG_RXFILTER_CATEGORY_3			(Offset 0x0686) */
+
+#define BIT_SHIFT_RXFILTER_CATEGORY_3 0
+#define BIT_MASK_RXFILTER_CATEGORY_3 0xff
+#define BIT_RXFILTER_CATEGORY_3(x)                                             \
+	(((x) & BIT_MASK_RXFILTER_CATEGORY_3) << BIT_SHIFT_RXFILTER_CATEGORY_3)
+#define BITS_RXFILTER_CATEGORY_3                                               \
+	(BIT_MASK_RXFILTER_CATEGORY_3 << BIT_SHIFT_RXFILTER_CATEGORY_3)
+#define BIT_CLEAR_RXFILTER_CATEGORY_3(x) ((x) & (~BITS_RXFILTER_CATEGORY_3))
+#define BIT_GET_RXFILTER_CATEGORY_3(x)                                         \
+	(((x) >> BIT_SHIFT_RXFILTER_CATEGORY_3) & BIT_MASK_RXFILTER_CATEGORY_3)
+#define BIT_SET_RXFILTER_CATEGORY_3(x, v)                                      \
+	(BIT_CLEAR_RXFILTER_CATEGORY_3(x) | BIT_RXFILTER_CATEGORY_3(v))
+
+/* 2 REG_RXFILTER_ACTION_3			(Offset 0x0687) */
+
+#define BIT_SHIFT_RXFILTER_ACTION_3 0
+#define BIT_MASK_RXFILTER_ACTION_3 0xff
+#define BIT_RXFILTER_ACTION_3(x)                                               \
+	(((x) & BIT_MASK_RXFILTER_ACTION_3) << BIT_SHIFT_RXFILTER_ACTION_3)
+#define BITS_RXFILTER_ACTION_3                                                 \
+	(BIT_MASK_RXFILTER_ACTION_3 << BIT_SHIFT_RXFILTER_ACTION_3)
+#define BIT_CLEAR_RXFILTER_ACTION_3(x) ((x) & (~BITS_RXFILTER_ACTION_3))
+#define BIT_GET_RXFILTER_ACTION_3(x)                                           \
+	(((x) >> BIT_SHIFT_RXFILTER_ACTION_3) & BIT_MASK_RXFILTER_ACTION_3)
+#define BIT_SET_RXFILTER_ACTION_3(x, v)                                        \
+	(BIT_CLEAR_RXFILTER_ACTION_3(x) | BIT_RXFILTER_ACTION_3(v))
+
+/* 2 REG_RXFLTMAP3				(Offset 0x0688) */
+
+#define BIT_MGTFLT15EN_FW BIT(15)
+#define BIT_MGTFLT14EN_FW BIT(14)
+#define BIT_MGTFLT13EN_FW BIT(13)
+#define BIT_MGTFLT12EN_FW BIT(12)
+#define BIT_MGTFLT11EN_FW BIT(11)
+#define BIT_MGTFLT10EN_FW BIT(10)
+#define BIT_MGTFLT9EN_FW BIT(9)
+#define BIT_MGTFLT8EN_FW BIT(8)
+#define BIT_MGTFLT7EN_FW BIT(7)
+#define BIT_MGTFLT6EN_FW BIT(6)
+#define BIT_MGTFLT5EN_FW BIT(5)
+#define BIT_MGTFLT4EN_FW BIT(4)
+#define BIT_MGTFLT3EN_FW BIT(3)
+#define BIT_MGTFLT2EN_FW BIT(2)
+#define BIT_MGTFLT1EN_FW BIT(1)
+#define BIT_MGTFLT0EN_FW BIT(0)
+
+/* 2 REG_RXFLTMAP4				(Offset 0x068A) */
+
+#define BIT_CTRLFLT15EN_FW BIT(15)
+#define BIT_CTRLFLT14EN_FW BIT(14)
+#define BIT_CTRLFLT13EN_FW BIT(13)
+#define BIT_CTRLFLT12EN_FW BIT(12)
+#define BIT_CTRLFLT11EN_FW BIT(11)
+#define BIT_CTRLFLT10EN_FW BIT(10)
+#define BIT_CTRLFLT9EN_FW BIT(9)
+#define BIT_CTRLFLT8EN_FW BIT(8)
+#define BIT_CTRLFLT7EN_FW BIT(7)
+#define BIT_CTRLFLT6EN_FW BIT(6)
+#define BIT_CTRLFLT5EN_FW BIT(5)
+#define BIT_CTRLFLT4EN_FW BIT(4)
+#define BIT_CTRLFLT3EN_FW BIT(3)
+#define BIT_CTRLFLT2EN_FW BIT(2)
+#define BIT_CTRLFLT1EN_FW BIT(1)
+#define BIT_CTRLFLT0EN_FW BIT(0)
+
+/* 2 REG_RXFLTMAP5				(Offset 0x068C) */
+
+#define BIT_DATAFLT15EN_FW BIT(15)
+#define BIT_DATAFLT14EN_FW BIT(14)
+#define BIT_DATAFLT13EN_FW BIT(13)
+#define BIT_DATAFLT12EN_FW BIT(12)
+#define BIT_DATAFLT11EN_FW BIT(11)
+#define BIT_DATAFLT10EN_FW BIT(10)
+#define BIT_DATAFLT9EN_FW BIT(9)
+#define BIT_DATAFLT8EN_FW BIT(8)
+#define BIT_DATAFLT7EN_FW BIT(7)
+#define BIT_DATAFLT6EN_FW BIT(6)
+#define BIT_DATAFLT5EN_FW BIT(5)
+#define BIT_DATAFLT4EN_FW BIT(4)
+#define BIT_DATAFLT3EN_FW BIT(3)
+#define BIT_DATAFLT2EN_FW BIT(2)
+#define BIT_DATAFLT1EN_FW BIT(1)
+#define BIT_DATAFLT0EN_FW BIT(0)
+
+/* 2 REG_RXFLTMAP6				(Offset 0x068E) */
+
+#define BIT_ACTIONFLT15EN_FW BIT(15)
+#define BIT_ACTIONFLT14EN_FW BIT(14)
+#define BIT_ACTIONFLT13EN_FW BIT(13)
+#define BIT_ACTIONFLT12EN_FW BIT(12)
+#define BIT_ACTIONFLT11EN_FW BIT(11)
+#define BIT_ACTIONFLT10EN_FW BIT(10)
+#define BIT_ACTIONFLT9EN_FW BIT(9)
+#define BIT_ACTIONFLT8EN_FW BIT(8)
+#define BIT_ACTIONFLT7EN_FW BIT(7)
+#define BIT_ACTIONFLT6EN_FW BIT(6)
+#define BIT_ACTIONFLT5EN_FW BIT(5)
+#define BIT_ACTIONFLT4EN_FW BIT(4)
+#define BIT_ACTIONFLT3EN_FW BIT(3)
+#define BIT_ACTIONFLT2EN_FW BIT(2)
+#define BIT_ACTIONFLT1EN_FW BIT(1)
+#define BIT_ACTIONFLT0EN_FW BIT(0)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_WOW_CTRL				(Offset 0x0690) */
+
+#define BIT_SHIFT_PSF_BSSIDSEL_B2B1 6
+#define BIT_MASK_PSF_BSSIDSEL_B2B1 0x3
+#define BIT_PSF_BSSIDSEL_B2B1(x)                                               \
+	(((x) & BIT_MASK_PSF_BSSIDSEL_B2B1) << BIT_SHIFT_PSF_BSSIDSEL_B2B1)
+#define BITS_PSF_BSSIDSEL_B2B1                                                 \
+	(BIT_MASK_PSF_BSSIDSEL_B2B1 << BIT_SHIFT_PSF_BSSIDSEL_B2B1)
+#define BIT_CLEAR_PSF_BSSIDSEL_B2B1(x) ((x) & (~BITS_PSF_BSSIDSEL_B2B1))
+#define BIT_GET_PSF_BSSIDSEL_B2B1(x)                                           \
+	(((x) >> BIT_SHIFT_PSF_BSSIDSEL_B2B1) & BIT_MASK_PSF_BSSIDSEL_B2B1)
+#define BIT_SET_PSF_BSSIDSEL_B2B1(x, v)                                        \
+	(BIT_CLEAR_PSF_BSSIDSEL_B2B1(x) | BIT_PSF_BSSIDSEL_B2B1(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_WOW_CTRL				(Offset 0x0690) */
+
+#define BIT_WOWHCI BIT(5)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_WOW_CTRL				(Offset 0x0690) */
+
+#define BIT_PSF_BSSIDSEL BIT(4)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_WOW_CTRL				(Offset 0x0690) */
+
+#define BIT_PSF_BSSIDSEL_B0 BIT(4)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_WOW_CTRL				(Offset 0x0690) */
+
+#define BIT_UWF BIT(3)
+#define BIT_MAGIC BIT(2)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_WOW_CTRL				(Offset 0x0690) */
+
+#define BIT_WOWEN BIT(1)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_WOW_CTRL				(Offset 0x0690) */
+
+#define BIT_WFMSK BIT(1)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_WOW_CTRL				(Offset 0x0690) */
+
+#define BIT_FORCE_WAKEUP BIT(0)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_NAN_RX_TSF_FILTER			(Offset 0x0691) */
+
+#define BIT_CHK_TSF_TA BIT(2)
+#define BIT_CHK_TSF_CBSSID BIT(1)
+#define BIT_CHK_TSF_EN BIT(0)
+
+/* 2 REG_PS_RX_INFO				(Offset 0x0692) */
+
+#define BIT_SHIFT_PORTSEL__PS_RX_INFO 5
+#define BIT_MASK_PORTSEL__PS_RX_INFO 0x7
+#define BIT_PORTSEL__PS_RX_INFO(x)                                             \
+	(((x) & BIT_MASK_PORTSEL__PS_RX_INFO) << BIT_SHIFT_PORTSEL__PS_RX_INFO)
+#define BITS_PORTSEL__PS_RX_INFO                                               \
+	(BIT_MASK_PORTSEL__PS_RX_INFO << BIT_SHIFT_PORTSEL__PS_RX_INFO)
+#define BIT_CLEAR_PORTSEL__PS_RX_INFO(x) ((x) & (~BITS_PORTSEL__PS_RX_INFO))
+#define BIT_GET_PORTSEL__PS_RX_INFO(x)                                         \
+	(((x) >> BIT_SHIFT_PORTSEL__PS_RX_INFO) & BIT_MASK_PORTSEL__PS_RX_INFO)
+#define BIT_SET_PORTSEL__PS_RX_INFO(x, v)                                      \
+	(BIT_CLEAR_PORTSEL__PS_RX_INFO(x) | BIT_PORTSEL__PS_RX_INFO(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_PS_RX_INFO				(Offset 0x0692) */
+
+#define BIT_RXCTRLIN0 BIT(4)
+#define BIT_RXMGTIN0 BIT(3)
+#define BIT_RXDATAIN2 BIT(2)
+#define BIT_RXDATAIN1 BIT(1)
+#define BIT_RXDATAIN0 BIT(0)
+
+/* 2 REG_WMMPS_UAPSD_TID			(Offset 0x0693) */
+
+#define BIT_SHIFT_DTIM_CNT 24
+#define BIT_MASK_DTIM_CNT 0xff
+#define BIT_DTIM_CNT(x) (((x) & BIT_MASK_DTIM_CNT) << BIT_SHIFT_DTIM_CNT)
+#define BITS_DTIM_CNT (BIT_MASK_DTIM_CNT << BIT_SHIFT_DTIM_CNT)
+#define BIT_CLEAR_DTIM_CNT(x) ((x) & (~BITS_DTIM_CNT))
+#define BIT_GET_DTIM_CNT(x) (((x) >> BIT_SHIFT_DTIM_CNT) & BIT_MASK_DTIM_CNT)
+#define BIT_SET_DTIM_CNT(x, v) (BIT_CLEAR_DTIM_CNT(x) | BIT_DTIM_CNT(v))
+
+#define BIT_CTRLFLT15EN BIT(15)
+#define BIT_DATAFLT15EN BIT(15)
+#define BIT_CTRLFLT14EN BIT(14)
+#define BIT_DATAFLT14EN BIT(14)
+#define BIT_MGTFLT13EN BIT(13)
+#define BIT_CTRLFLT13EN BIT(13)
+#define BIT_DATAFLT13EN BIT(13)
+#define BIT_MGTFLT12EN BIT(12)
+#define BIT_CTRLFLT12EN BIT(12)
+#define BIT_DATAFLT12EN BIT(12)
+#define BIT_MGTFLT11EN BIT(11)
+#define BIT_CTRLFLT11EN BIT(11)
+#define BIT_DATAFLT11EN BIT(11)
+#define BIT_MGTFLT10EN BIT(10)
+#define BIT_CTRLFLT10EN BIT(10)
+#define BIT_DATAFLT10EN BIT(10)
+#define BIT_MGTFLT9EN BIT(9)
+#define BIT_CTRLFLT9EN BIT(9)
+#define BIT_DATAFLT9EN BIT(9)
+#define BIT_MGTFLT8EN BIT(8)
+#define BIT_CTRLFLT8EN BIT(8)
+#define BIT_DATAFLT8EN BIT(8)
+#define BIT_WMMPS_UAPSD_TID7 BIT(7)
+#define BIT_CTRLFLT7EN BIT(7)
+#define BIT_DATAFLT7EN BIT(7)
+#define BIT_WMMPS_UAPSD_TID6 BIT(6)
+#define BIT_CTRLFLT6EN BIT(6)
+#define BIT_DATAFLT6EN BIT(6)
+#define BIT_WMMPS_UAPSD_TID5 BIT(5)
+#define BIT_MGTFLT5EN BIT(5)
+#define BIT_DATAFLT5EN BIT(5)
+#define BIT_WMMPS_UAPSD_TID4 BIT(4)
+#define BIT_MGTFLT4EN BIT(4)
+#define BIT_DATAFLT4EN BIT(4)
+#define BIT_WMMPS_UAPSD_TID3 BIT(3)
+#define BIT_MGTFLT3EN BIT(3)
+#define BIT_DATAFLT3EN BIT(3)
+#define BIT_WMMPS_UAPSD_TID2 BIT(2)
+#define BIT_MGTFLT2EN BIT(2)
+#define BIT_DATAFLT2EN BIT(2)
+#define BIT_WMMPS_UAPSD_TID1 BIT(1)
+#define BIT_MGTFLT1EN BIT(1)
+#define BIT_DATAFLT1EN BIT(1)
+#define BIT_WMMPS_UAPSD_TID0 BIT(0)
+#define BIT_MGTFLT0EN BIT(0)
+#define BIT_DATAFLT0EN BIT(0)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_LPNAV_CTRL				(Offset 0x0694) */
+
+#define BIT_LPNAV_EN BIT(31)
+
+#define BIT_SHIFT_LPNAV_EARLY 16
+#define BIT_MASK_LPNAV_EARLY 0x7fff
+#define BIT_LPNAV_EARLY(x)                                                     \
+	(((x) & BIT_MASK_LPNAV_EARLY) << BIT_SHIFT_LPNAV_EARLY)
+#define BITS_LPNAV_EARLY (BIT_MASK_LPNAV_EARLY << BIT_SHIFT_LPNAV_EARLY)
+#define BIT_CLEAR_LPNAV_EARLY(x) ((x) & (~BITS_LPNAV_EARLY))
+#define BIT_GET_LPNAV_EARLY(x)                                                 \
+	(((x) >> BIT_SHIFT_LPNAV_EARLY) & BIT_MASK_LPNAV_EARLY)
+#define BIT_SET_LPNAV_EARLY(x, v)                                              \
+	(BIT_CLEAR_LPNAV_EARLY(x) | BIT_LPNAV_EARLY(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_LPNAV_CTRL				(Offset 0x0694) */
+
+#define BIT_SHIFT_LPNAV_TH 0
+#define BIT_MASK_LPNAV_TH 0xffff
+#define BIT_LPNAV_TH(x) (((x) & BIT_MASK_LPNAV_TH) << BIT_SHIFT_LPNAV_TH)
+#define BITS_LPNAV_TH (BIT_MASK_LPNAV_TH << BIT_SHIFT_LPNAV_TH)
+#define BIT_CLEAR_LPNAV_TH(x) ((x) & (~BITS_LPNAV_TH))
+#define BIT_GET_LPNAV_TH(x) (((x) >> BIT_SHIFT_LPNAV_TH) & BIT_MASK_LPNAV_TH)
+#define BIT_SET_LPNAV_TH(x, v) (BIT_CLEAR_LPNAV_TH(x) | BIT_LPNAV_TH(v))
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_LPNAV_CTRL				(Offset 0x0694) */
+
+#define BIT_SHIFT_LPNAV_THR 0
+#define BIT_MASK_LPNAV_THR 0xffff
+#define BIT_LPNAV_THR(x) (((x) & BIT_MASK_LPNAV_THR) << BIT_SHIFT_LPNAV_THR)
+#define BITS_LPNAV_THR (BIT_MASK_LPNAV_THR << BIT_SHIFT_LPNAV_THR)
+#define BIT_CLEAR_LPNAV_THR(x) ((x) & (~BITS_LPNAV_THR))
+#define BIT_GET_LPNAV_THR(x) (((x) >> BIT_SHIFT_LPNAV_THR) & BIT_MASK_LPNAV_THR)
+#define BIT_SET_LPNAV_THR(x, v) (BIT_CLEAR_LPNAV_THR(x) | BIT_LPNAV_THR(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_WKFMCAM_CMD				(Offset 0x0698) */
+
+#define BIT_WKFCAM_POLLING_V1 BIT(31)
+#define BIT_WKFCAM_CLR_V1 BIT(30)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_WKFMCAM_CMD				(Offset 0x0698) */
+
+#define BIT_WKFCAM_WE BIT(16)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_WKFMCAM_CMD				(Offset 0x0698) */
+
+#define BIT_SHIFT_WKFCAM_ADDR_V2 8
+#define BIT_MASK_WKFCAM_ADDR_V2 0xff
+#define BIT_WKFCAM_ADDR_V2(x)                                                  \
+	(((x) & BIT_MASK_WKFCAM_ADDR_V2) << BIT_SHIFT_WKFCAM_ADDR_V2)
+#define BITS_WKFCAM_ADDR_V2                                                    \
+	(BIT_MASK_WKFCAM_ADDR_V2 << BIT_SHIFT_WKFCAM_ADDR_V2)
+#define BIT_CLEAR_WKFCAM_ADDR_V2(x) ((x) & (~BITS_WKFCAM_ADDR_V2))
+#define BIT_GET_WKFCAM_ADDR_V2(x)                                              \
+	(((x) >> BIT_SHIFT_WKFCAM_ADDR_V2) & BIT_MASK_WKFCAM_ADDR_V2)
+#define BIT_SET_WKFCAM_ADDR_V2(x, v)                                           \
+	(BIT_CLEAR_WKFCAM_ADDR_V2(x) | BIT_WKFCAM_ADDR_V2(v))
+
+#define BIT_WMAC_RESP_NONSTA1_DIS BIT(7)
+
+#define BIT_SHIFT_WMAC_TXMU_ACKPOLICY 4
+#define BIT_MASK_WMAC_TXMU_ACKPOLICY 0x3
+#define BIT_WMAC_TXMU_ACKPOLICY(x)                                             \
+	(((x) & BIT_MASK_WMAC_TXMU_ACKPOLICY) << BIT_SHIFT_WMAC_TXMU_ACKPOLICY)
+#define BITS_WMAC_TXMU_ACKPOLICY                                               \
+	(BIT_MASK_WMAC_TXMU_ACKPOLICY << BIT_SHIFT_WMAC_TXMU_ACKPOLICY)
+#define BIT_CLEAR_WMAC_TXMU_ACKPOLICY(x) ((x) & (~BITS_WMAC_TXMU_ACKPOLICY))
+#define BIT_GET_WMAC_TXMU_ACKPOLICY(x)                                         \
+	(((x) >> BIT_SHIFT_WMAC_TXMU_ACKPOLICY) & BIT_MASK_WMAC_TXMU_ACKPOLICY)
+#define BIT_SET_WMAC_TXMU_ACKPOLICY(x, v)                                      \
+	(BIT_CLEAR_WMAC_TXMU_ACKPOLICY(x) | BIT_WMAC_TXMU_ACKPOLICY(v))
+
+#define BIT_SHIFT_WMAC_MU_BFEE_PORT_SEL 1
+#define BIT_MASK_WMAC_MU_BFEE_PORT_SEL 0x7
+#define BIT_WMAC_MU_BFEE_PORT_SEL(x)                                           \
+	(((x) & BIT_MASK_WMAC_MU_BFEE_PORT_SEL)                                \
+	 << BIT_SHIFT_WMAC_MU_BFEE_PORT_SEL)
+#define BITS_WMAC_MU_BFEE_PORT_SEL                                             \
+	(BIT_MASK_WMAC_MU_BFEE_PORT_SEL << BIT_SHIFT_WMAC_MU_BFEE_PORT_SEL)
+#define BIT_CLEAR_WMAC_MU_BFEE_PORT_SEL(x) ((x) & (~BITS_WMAC_MU_BFEE_PORT_SEL))
+#define BIT_GET_WMAC_MU_BFEE_PORT_SEL(x)                                       \
+	(((x) >> BIT_SHIFT_WMAC_MU_BFEE_PORT_SEL) &                            \
+	 BIT_MASK_WMAC_MU_BFEE_PORT_SEL)
+#define BIT_SET_WMAC_MU_BFEE_PORT_SEL(x, v)                                    \
+	(BIT_CLEAR_WMAC_MU_BFEE_PORT_SEL(x) | BIT_WMAC_MU_BFEE_PORT_SEL(v))
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_WKFMCAM_CMD				(Offset 0x0698) */
+
+#define BIT_SHIFT_WKFCAM_NUM_V1 0
+#define BIT_MASK_WKFCAM_NUM_V1 0xff
+#define BIT_WKFCAM_NUM_V1(x)                                                   \
+	(((x) & BIT_MASK_WKFCAM_NUM_V1) << BIT_SHIFT_WKFCAM_NUM_V1)
+#define BITS_WKFCAM_NUM_V1 (BIT_MASK_WKFCAM_NUM_V1 << BIT_SHIFT_WKFCAM_NUM_V1)
+#define BIT_CLEAR_WKFCAM_NUM_V1(x) ((x) & (~BITS_WKFCAM_NUM_V1))
+#define BIT_GET_WKFCAM_NUM_V1(x)                                               \
+	(((x) >> BIT_SHIFT_WKFCAM_NUM_V1) & BIT_MASK_WKFCAM_NUM_V1)
+#define BIT_SET_WKFCAM_NUM_V1(x, v)                                            \
+	(BIT_CLEAR_WKFCAM_NUM_V1(x) | BIT_WKFCAM_NUM_V1(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_WKFMCAM_CMD				(Offset 0x0698) */
+
+#define BIT_SHIFT_WKFCAM_CAM_NUM_V1 0
+#define BIT_MASK_WKFCAM_CAM_NUM_V1 0xff
+#define BIT_WKFCAM_CAM_NUM_V1(x)                                               \
+	(((x) & BIT_MASK_WKFCAM_CAM_NUM_V1) << BIT_SHIFT_WKFCAM_CAM_NUM_V1)
+#define BITS_WKFCAM_CAM_NUM_V1                                                 \
+	(BIT_MASK_WKFCAM_CAM_NUM_V1 << BIT_SHIFT_WKFCAM_CAM_NUM_V1)
+#define BIT_CLEAR_WKFCAM_CAM_NUM_V1(x) ((x) & (~BITS_WKFCAM_CAM_NUM_V1))
+#define BIT_GET_WKFCAM_CAM_NUM_V1(x)                                           \
+	(((x) >> BIT_SHIFT_WKFCAM_CAM_NUM_V1) & BIT_MASK_WKFCAM_CAM_NUM_V1)
+#define BIT_SET_WKFCAM_CAM_NUM_V1(x, v)                                        \
+	(BIT_CLEAR_WKFCAM_CAM_NUM_V1(x) | BIT_WKFCAM_CAM_NUM_V1(v))
+
+#define BIT_WMAC_MU_BFEE_DIS BIT(0)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_WKFMCAM_CMD				(Offset 0x0698) */
+
+#define BIT_SHIFT_WKFCAM_ADDR 0
+#define BIT_MASK_WKFCAM_ADDR 0x7f
+#define BIT_WKFCAM_ADDR(x)                                                     \
+	(((x) & BIT_MASK_WKFCAM_ADDR) << BIT_SHIFT_WKFCAM_ADDR)
+#define BITS_WKFCAM_ADDR (BIT_MASK_WKFCAM_ADDR << BIT_SHIFT_WKFCAM_ADDR)
+#define BIT_CLEAR_WKFCAM_ADDR(x) ((x) & (~BITS_WKFCAM_ADDR))
+#define BIT_GET_WKFCAM_ADDR(x)                                                 \
+	(((x) >> BIT_SHIFT_WKFCAM_ADDR) & BIT_MASK_WKFCAM_ADDR)
+#define BIT_SET_WKFCAM_ADDR(x, v)                                              \
+	(BIT_CLEAR_WKFCAM_ADDR(x) | BIT_WKFCAM_ADDR(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_WKFMCAM_RWD				(Offset 0x069C) */
+
+#define BIT_SHIFT_WKFMCAM_RWD 0
+#define BIT_MASK_WKFMCAM_RWD 0xffffffffL
+#define BIT_WKFMCAM_RWD(x)                                                     \
+	(((x) & BIT_MASK_WKFMCAM_RWD) << BIT_SHIFT_WKFMCAM_RWD)
+#define BITS_WKFMCAM_RWD (BIT_MASK_WKFMCAM_RWD << BIT_SHIFT_WKFMCAM_RWD)
+#define BIT_CLEAR_WKFMCAM_RWD(x) ((x) & (~BITS_WKFMCAM_RWD))
+#define BIT_GET_WKFMCAM_RWD(x)                                                 \
+	(((x) >> BIT_SHIFT_WKFMCAM_RWD) & BIT_MASK_WKFMCAM_RWD)
+#define BIT_SET_WKFMCAM_RWD(x, v)                                              \
+	(BIT_CLEAR_WKFMCAM_RWD(x) | BIT_WKFMCAM_RWD(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_BCN_PSR_RPT				(Offset 0x06A8) */
+
+#define BIT_SHIFT_DTIM_PERIOD 16
+#define BIT_MASK_DTIM_PERIOD 0xff
+#define BIT_DTIM_PERIOD(x)                                                     \
+	(((x) & BIT_MASK_DTIM_PERIOD) << BIT_SHIFT_DTIM_PERIOD)
+#define BITS_DTIM_PERIOD (BIT_MASK_DTIM_PERIOD << BIT_SHIFT_DTIM_PERIOD)
+#define BIT_CLEAR_DTIM_PERIOD(x) ((x) & (~BITS_DTIM_PERIOD))
+#define BIT_GET_DTIM_PERIOD(x)                                                 \
+	(((x) >> BIT_SHIFT_DTIM_PERIOD) & BIT_MASK_DTIM_PERIOD)
+#define BIT_SET_DTIM_PERIOD(x, v)                                              \
+	(BIT_CLEAR_DTIM_PERIOD(x) | BIT_DTIM_PERIOD(v))
+
+#define BIT_DTIM BIT(15)
+#define BIT_TIM BIT(14)
+
+#define BIT_SHIFT_PS_AID_0 0
+#define BIT_MASK_PS_AID_0 0x7ff
+#define BIT_PS_AID_0(x) (((x) & BIT_MASK_PS_AID_0) << BIT_SHIFT_PS_AID_0)
+#define BITS_PS_AID_0 (BIT_MASK_PS_AID_0 << BIT_SHIFT_PS_AID_0)
+#define BIT_CLEAR_PS_AID_0(x) ((x) & (~BITS_PS_AID_0))
+#define BIT_GET_PS_AID_0(x) (((x) >> BIT_SHIFT_PS_AID_0) & BIT_MASK_PS_AID_0)
+#define BIT_SET_PS_AID_0(x, v) (BIT_CLEAR_PS_AID_0(x) | BIT_PS_AID_0(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8881A_SUPPORT)
+
+/* 2 REG_FLC_RPC				(Offset 0x06AC) */
+
+#define BIT_SHIFT_FLC_RPC 0
+#define BIT_MASK_FLC_RPC 0xff
+#define BIT_FLC_RPC(x) (((x) & BIT_MASK_FLC_RPC) << BIT_SHIFT_FLC_RPC)
+#define BITS_FLC_RPC (BIT_MASK_FLC_RPC << BIT_SHIFT_FLC_RPC)
+#define BIT_CLEAR_FLC_RPC(x) ((x) & (~BITS_FLC_RPC))
+#define BIT_GET_FLC_RPC(x) (((x) >> BIT_SHIFT_FLC_RPC) & BIT_MASK_FLC_RPC)
+#define BIT_SET_FLC_RPC(x, v) (BIT_CLEAR_FLC_RPC(x) | BIT_FLC_RPC(v))
+
+/* 2 REG_FLC_RPCT				(Offset 0x06AD) */
+
+#define BIT_SHIFT_FLC_RPCT 0
+#define BIT_MASK_FLC_RPCT 0xff
+#define BIT_FLC_RPCT(x) (((x) & BIT_MASK_FLC_RPCT) << BIT_SHIFT_FLC_RPCT)
+#define BITS_FLC_RPCT (BIT_MASK_FLC_RPCT << BIT_SHIFT_FLC_RPCT)
+#define BIT_CLEAR_FLC_RPCT(x) ((x) & (~BITS_FLC_RPCT))
+#define BIT_GET_FLC_RPCT(x) (((x) >> BIT_SHIFT_FLC_RPCT) & BIT_MASK_FLC_RPCT)
+#define BIT_SET_FLC_RPCT(x, v) (BIT_CLEAR_FLC_RPCT(x) | BIT_FLC_RPCT(v))
+
+/* 2 REG_FLC_PTS				(Offset 0x06AE) */
+
+#define BIT_CMF BIT(2)
+#define BIT_CCF BIT(1)
+#define BIT_CDF BIT(0)
+
+/* 2 REG_FLC_TRPC				(Offset 0x06AF) */
+
+#define BIT_FLC_RPCT_V1 BIT(7)
+#define BIT_MODE BIT(6)
+
+#define BIT_SHIFT_TRPCD 0
+#define BIT_MASK_TRPCD 0x3f
+#define BIT_TRPCD(x) (((x) & BIT_MASK_TRPCD) << BIT_SHIFT_TRPCD)
+#define BITS_TRPCD (BIT_MASK_TRPCD << BIT_SHIFT_TRPCD)
+#define BIT_CLEAR_TRPCD(x) ((x) & (~BITS_TRPCD))
+#define BIT_GET_TRPCD(x) (((x) >> BIT_SHIFT_TRPCD) & BIT_MASK_TRPCD)
+#define BIT_SET_TRPCD(x, v) (BIT_CLEAR_TRPCD(x) | BIT_TRPCD(v))
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_RXPKTMON_CTRL			(Offset 0x06B0) */
+
+#define BIT_SHIFT_RXBKQPKT_SEQ 20
+#define BIT_MASK_RXBKQPKT_SEQ 0xf
+#define BIT_RXBKQPKT_SEQ(x)                                                    \
+	(((x) & BIT_MASK_RXBKQPKT_SEQ) << BIT_SHIFT_RXBKQPKT_SEQ)
+#define BITS_RXBKQPKT_SEQ (BIT_MASK_RXBKQPKT_SEQ << BIT_SHIFT_RXBKQPKT_SEQ)
+#define BIT_CLEAR_RXBKQPKT_SEQ(x) ((x) & (~BITS_RXBKQPKT_SEQ))
+#define BIT_GET_RXBKQPKT_SEQ(x)                                                \
+	(((x) >> BIT_SHIFT_RXBKQPKT_SEQ) & BIT_MASK_RXBKQPKT_SEQ)
+#define BIT_SET_RXBKQPKT_SEQ(x, v)                                             \
+	(BIT_CLEAR_RXBKQPKT_SEQ(x) | BIT_RXBKQPKT_SEQ(v))
+
+#define BIT_SHIFT_RXBEQPKT_SEQ 16
+#define BIT_MASK_RXBEQPKT_SEQ 0xf
+#define BIT_RXBEQPKT_SEQ(x)                                                    \
+	(((x) & BIT_MASK_RXBEQPKT_SEQ) << BIT_SHIFT_RXBEQPKT_SEQ)
+#define BITS_RXBEQPKT_SEQ (BIT_MASK_RXBEQPKT_SEQ << BIT_SHIFT_RXBEQPKT_SEQ)
+#define BIT_CLEAR_RXBEQPKT_SEQ(x) ((x) & (~BITS_RXBEQPKT_SEQ))
+#define BIT_GET_RXBEQPKT_SEQ(x)                                                \
+	(((x) >> BIT_SHIFT_RXBEQPKT_SEQ) & BIT_MASK_RXBEQPKT_SEQ)
+#define BIT_SET_RXBEQPKT_SEQ(x, v)                                             \
+	(BIT_CLEAR_RXBEQPKT_SEQ(x) | BIT_RXBEQPKT_SEQ(v))
+
+#define BIT_SHIFT_RXVIQPKT_SEQ 12
+#define BIT_MASK_RXVIQPKT_SEQ 0xf
+#define BIT_RXVIQPKT_SEQ(x)                                                    \
+	(((x) & BIT_MASK_RXVIQPKT_SEQ) << BIT_SHIFT_RXVIQPKT_SEQ)
+#define BITS_RXVIQPKT_SEQ (BIT_MASK_RXVIQPKT_SEQ << BIT_SHIFT_RXVIQPKT_SEQ)
+#define BIT_CLEAR_RXVIQPKT_SEQ(x) ((x) & (~BITS_RXVIQPKT_SEQ))
+#define BIT_GET_RXVIQPKT_SEQ(x)                                                \
+	(((x) >> BIT_SHIFT_RXVIQPKT_SEQ) & BIT_MASK_RXVIQPKT_SEQ)
+#define BIT_SET_RXVIQPKT_SEQ(x, v)                                             \
+	(BIT_CLEAR_RXVIQPKT_SEQ(x) | BIT_RXVIQPKT_SEQ(v))
+
+#define BIT_SHIFT_RXVOQPKT_SEQ 8
+#define BIT_MASK_RXVOQPKT_SEQ 0xf
+#define BIT_RXVOQPKT_SEQ(x)                                                    \
+	(((x) & BIT_MASK_RXVOQPKT_SEQ) << BIT_SHIFT_RXVOQPKT_SEQ)
+#define BITS_RXVOQPKT_SEQ (BIT_MASK_RXVOQPKT_SEQ << BIT_SHIFT_RXVOQPKT_SEQ)
+#define BIT_CLEAR_RXVOQPKT_SEQ(x) ((x) & (~BITS_RXVOQPKT_SEQ))
+#define BIT_GET_RXVOQPKT_SEQ(x)                                                \
+	(((x) >> BIT_SHIFT_RXVOQPKT_SEQ) & BIT_MASK_RXVOQPKT_SEQ)
+#define BIT_SET_RXVOQPKT_SEQ(x, v)                                             \
+	(BIT_CLEAR_RXVOQPKT_SEQ(x) | BIT_RXVOQPKT_SEQ(v))
+
+#define BIT_RXBKQPKT_ERR BIT(7)
+#define BIT_RXBEQPKT_ERR BIT(6)
+#define BIT_RXVIQPKT_ERR BIT(5)
+#define BIT_RXVOQPKT_ERR BIT(4)
+#define BIT_RXDMA_MON_EN BIT(2)
+#define BIT_RXPKT_MON_RST BIT(1)
+#define BIT_RXPKT_MON_EN BIT(0)
+
+/* 2 REG_STATE_MON				(Offset 0x06B4) */
+
+#define BIT_EN_TXRPTBUF_CLK BIT(31)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_STATE_MON				(Offset 0x06B4) */
+
+#define BIT_SHIFT_DMA_MON_EN 24
+#define BIT_MASK_DMA_MON_EN 0x1f
+#define BIT_DMA_MON_EN(x) (((x) & BIT_MASK_DMA_MON_EN) << BIT_SHIFT_DMA_MON_EN)
+#define BITS_DMA_MON_EN (BIT_MASK_DMA_MON_EN << BIT_SHIFT_DMA_MON_EN)
+#define BIT_CLEAR_DMA_MON_EN(x) ((x) & (~BITS_DMA_MON_EN))
+#define BIT_GET_DMA_MON_EN(x)                                                  \
+	(((x) >> BIT_SHIFT_DMA_MON_EN) & BIT_MASK_DMA_MON_EN)
+#define BIT_SET_DMA_MON_EN(x, v) (BIT_CLEAR_DMA_MON_EN(x) | BIT_DMA_MON_EN(v))
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_STATE_MON				(Offset 0x06B4) */
+
+#define BIT_SHIFT_STATE_SEL 24
+#define BIT_MASK_STATE_SEL 0x1f
+#define BIT_STATE_SEL(x) (((x) & BIT_MASK_STATE_SEL) << BIT_SHIFT_STATE_SEL)
+#define BITS_STATE_SEL (BIT_MASK_STATE_SEL << BIT_SHIFT_STATE_SEL)
+#define BIT_CLEAR_STATE_SEL(x) ((x) & (~BITS_STATE_SEL))
+#define BIT_GET_STATE_SEL(x) (((x) >> BIT_SHIFT_STATE_SEL) & BIT_MASK_STATE_SEL)
+#define BIT_SET_STATE_SEL(x, v) (BIT_CLEAR_STATE_SEL(x) | BIT_STATE_SEL(v))
+
+#define BIT_MACRX_ERR_1 BIT(17)
+#define BIT_MACRX_ERR_0 BIT(16)
+#define BIT_DIS_INFOSRCH BIT(14)
+
+#define BIT_SHIFT_STATE_INFO 8
+#define BIT_MASK_STATE_INFO 0xff
+#define BIT_STATE_INFO(x) (((x) & BIT_MASK_STATE_INFO) << BIT_SHIFT_STATE_INFO)
+#define BITS_STATE_INFO (BIT_MASK_STATE_INFO << BIT_SHIFT_STATE_INFO)
+#define BIT_CLEAR_STATE_INFO(x) ((x) & (~BITS_STATE_INFO))
+#define BIT_GET_STATE_INFO(x)                                                  \
+	(((x) >> BIT_SHIFT_STATE_INFO) & BIT_MASK_STATE_INFO)
+#define BIT_SET_STATE_INFO(x, v) (BIT_CLEAR_STATE_INFO(x) | BIT_STATE_INFO(v))
+
+#define BIT_UPD_NXT_STATE BIT(7)
+#define BIT_MACTX_ERR_3 BIT(3)
+#define BIT_MACTX_ERR_2 BIT(2)
+#define BIT_MACTX_ERR_1 BIT(1)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_STATE_MON				(Offset 0x06B4) */
+
+#define BIT_SHIFT_PKT_MON_EN 0
+#define BIT_MASK_PKT_MON_EN 0x7f
+#define BIT_PKT_MON_EN(x) (((x) & BIT_MASK_PKT_MON_EN) << BIT_SHIFT_PKT_MON_EN)
+#define BITS_PKT_MON_EN (BIT_MASK_PKT_MON_EN << BIT_SHIFT_PKT_MON_EN)
+#define BIT_CLEAR_PKT_MON_EN(x) ((x) & (~BITS_PKT_MON_EN))
+#define BIT_GET_PKT_MON_EN(x)                                                  \
+	(((x) >> BIT_SHIFT_PKT_MON_EN) & BIT_MASK_PKT_MON_EN)
+#define BIT_SET_PKT_MON_EN(x, v) (BIT_CLEAR_PKT_MON_EN(x) | BIT_PKT_MON_EN(v))
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_STATE_MON				(Offset 0x06B4) */
+
+#define BIT_SHIFT_CUR_STATE 0
+#define BIT_MASK_CUR_STATE 0x7f
+#define BIT_CUR_STATE(x) (((x) & BIT_MASK_CUR_STATE) << BIT_SHIFT_CUR_STATE)
+#define BITS_CUR_STATE (BIT_MASK_CUR_STATE << BIT_SHIFT_CUR_STATE)
+#define BIT_CLEAR_CUR_STATE(x) ((x) & (~BITS_CUR_STATE))
+#define BIT_GET_CUR_STATE(x) (((x) >> BIT_SHIFT_CUR_STATE) & BIT_MASK_CUR_STATE)
+#define BIT_SET_CUR_STATE(x, v) (BIT_CLEAR_CUR_STATE(x) | BIT_CUR_STATE(v))
+
+#define BIT_MACTX_ERR_0 BIT(0)
+
+#define BIT_SHIFT_INFO_ADDR_OFFSET 0
+#define BIT_MASK_INFO_ADDR_OFFSET 0x1fff
+#define BIT_INFO_ADDR_OFFSET(x)                                                \
+	(((x) & BIT_MASK_INFO_ADDR_OFFSET) << BIT_SHIFT_INFO_ADDR_OFFSET)
+#define BITS_INFO_ADDR_OFFSET                                                  \
+	(BIT_MASK_INFO_ADDR_OFFSET << BIT_SHIFT_INFO_ADDR_OFFSET)
+#define BIT_CLEAR_INFO_ADDR_OFFSET(x) ((x) & (~BITS_INFO_ADDR_OFFSET))
+#define BIT_GET_INFO_ADDR_OFFSET(x)                                            \
+	(((x) >> BIT_SHIFT_INFO_ADDR_OFFSET) & BIT_MASK_INFO_ADDR_OFFSET)
+#define BIT_SET_INFO_ADDR_OFFSET(x, v)                                         \
+	(BIT_CLEAR_INFO_ADDR_OFFSET(x) | BIT_INFO_ADDR_OFFSET(v))
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_ERROR_MON				(Offset 0x06B8) */
+
+#define BIT_CSIRPT_LEN_BB_MORE_THAN_MAC BIT(23)
+#define BIT_CSI_CHKSUM_ERROR BIT(22)
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+/* 2 REG_ERROR_MON				(Offset 0x06B8) */
+
+#define BIT_BFM_RPTNUM_ERROR BIT(21)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_ERROR_MON				(Offset 0x06B8) */
+
+#define BIT_MACRX_ERR_5 BIT(21)
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+/* 2 REG_ERROR_MON				(Offset 0x06B8) */
+
+#define BIT_BFM_CHECKSUM_ERROR BIT(20)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_ERROR_MON				(Offset 0x06B8) */
+
+#define BIT_MACRX_ERR_4 BIT(20)
+#define BIT_MACRX_ERR_3 BIT(19)
+#define BIT_MACRX_ERR_2 BIT(18)
+#define BIT_WMAC_PRETX_ERRHDL_EN BIT(15)
+#define BIT_MACTX_ERR_5 BIT(5)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT || \
+     HALMAC_8881A_SUPPORT)
+
+/* 2 REG_BT_COEX_TABLE			(Offset 0x06C0) */
+
+#define BIT_PRI_MASK_RX_RESP BIT(126)
+#define BIT_PRI_MASK_RXOFDM BIT(125)
+#define BIT_PRI_MASK_RXCCK BIT(124)
+#define BIT_PRI_MASK_CCK BIT(108)
+#define BIT_PRI_MASK_OFDM BIT(107)
+#define BIT_PRI_MASK_RTY BIT(106)
+#define BIT_OOB BIT(97)
+#define BIT_ANT_SEL BIT(96)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_BT_COEX_TABLE			(Offset 0x06C0) */
+
+#define BIT_SHIFT_R_WMAC_BFINFO_20M_1 16
+#define BIT_MASK_R_WMAC_BFINFO_20M_1 0xfff
+#define BIT_R_WMAC_BFINFO_20M_1(x)                                             \
+	(((x) & BIT_MASK_R_WMAC_BFINFO_20M_1) << BIT_SHIFT_R_WMAC_BFINFO_20M_1)
+#define BITS_R_WMAC_BFINFO_20M_1                                               \
+	(BIT_MASK_R_WMAC_BFINFO_20M_1 << BIT_SHIFT_R_WMAC_BFINFO_20M_1)
+#define BIT_CLEAR_R_WMAC_BFINFO_20M_1(x) ((x) & (~BITS_R_WMAC_BFINFO_20M_1))
+#define BIT_GET_R_WMAC_BFINFO_20M_1(x)                                         \
+	(((x) >> BIT_SHIFT_R_WMAC_BFINFO_20M_1) & BIT_MASK_R_WMAC_BFINFO_20M_1)
+#define BIT_SET_R_WMAC_BFINFO_20M_1(x, v)                                      \
+	(BIT_CLEAR_R_WMAC_BFINFO_20M_1(x) | BIT_R_WMAC_BFINFO_20M_1(v))
+
+#define BIT_SHIFT_COEX_TABLE_1 0
+#define BIT_MASK_COEX_TABLE_1 0xffffffffL
+#define BIT_COEX_TABLE_1(x)                                                    \
+	(((x) & BIT_MASK_COEX_TABLE_1) << BIT_SHIFT_COEX_TABLE_1)
+#define BITS_COEX_TABLE_1 (BIT_MASK_COEX_TABLE_1 << BIT_SHIFT_COEX_TABLE_1)
+#define BIT_CLEAR_COEX_TABLE_1(x) ((x) & (~BITS_COEX_TABLE_1))
+#define BIT_GET_COEX_TABLE_1(x)                                                \
+	(((x) >> BIT_SHIFT_COEX_TABLE_1) & BIT_MASK_COEX_TABLE_1)
+#define BIT_SET_COEX_TABLE_1(x, v)                                             \
+	(BIT_CLEAR_COEX_TABLE_1(x) | BIT_COEX_TABLE_1(v))
+
+#define BIT_SHIFT_R_WMAC_BFINFO_20M_0 0
+#define BIT_MASK_R_WMAC_BFINFO_20M_0 0xfff
+#define BIT_R_WMAC_BFINFO_20M_0(x)                                             \
+	(((x) & BIT_MASK_R_WMAC_BFINFO_20M_0) << BIT_SHIFT_R_WMAC_BFINFO_20M_0)
+#define BITS_R_WMAC_BFINFO_20M_0                                               \
+	(BIT_MASK_R_WMAC_BFINFO_20M_0 << BIT_SHIFT_R_WMAC_BFINFO_20M_0)
+#define BIT_CLEAR_R_WMAC_BFINFO_20M_0(x) ((x) & (~BITS_R_WMAC_BFINFO_20M_0))
+#define BIT_GET_R_WMAC_BFINFO_20M_0(x)                                         \
+	(((x) >> BIT_SHIFT_R_WMAC_BFINFO_20M_0) & BIT_MASK_R_WMAC_BFINFO_20M_0)
+#define BIT_SET_R_WMAC_BFINFO_20M_0(x, v)                                      \
+	(BIT_CLEAR_R_WMAC_BFINFO_20M_0(x) | BIT_R_WMAC_BFINFO_20M_0(v))
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_BT_COEX_TABLE_H			(Offset 0x06CC) */
+
+#define BIT_PRI_MASK_RX_RESP_V1 BIT(30)
+#define BIT_PRI_MASK_RXOFDM_V1 BIT(29)
+#define BIT_PRI_MASK_RXCCK_V1 BIT(28)
+#define BIT_PRI_MASK_CCK_V1 BIT(12)
+#define BIT_PRI_MASK_OFDM_V1 BIT(11)
+#define BIT_PRI_MASK_RTY_V1 BIT(10)
+#define BIT_OOB_V1 BIT(1)
+#define BIT_ANT_SEL_V1 BIT(0)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_RXCMD_0				(Offset 0x06D0) */
+
+#define BIT_RXCMD_EN BIT(31)
+
+#define BIT_SHIFT_RXCMD_INFO 0
+#define BIT_MASK_RXCMD_INFO 0x7fffffffL
+#define BIT_RXCMD_INFO(x) (((x) & BIT_MASK_RXCMD_INFO) << BIT_SHIFT_RXCMD_INFO)
+#define BITS_RXCMD_INFO (BIT_MASK_RXCMD_INFO << BIT_SHIFT_RXCMD_INFO)
+#define BIT_CLEAR_RXCMD_INFO(x) ((x) & (~BITS_RXCMD_INFO))
+#define BIT_GET_RXCMD_INFO(x)                                                  \
+	(((x) >> BIT_SHIFT_RXCMD_INFO) & BIT_MASK_RXCMD_INFO)
+#define BIT_SET_RXCMD_INFO(x, v) (BIT_CLEAR_RXCMD_INFO(x) | BIT_RXCMD_INFO(v))
+
+/* 2 REG_RXCMD_1				(Offset 0x06D4) */
+
+#define BIT_TXUSER_ID1 BIT(25)
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+/* 2 REG_RXCMD_1				(Offset 0x06D4) */
+
+#define BIT_SHIFT_CSI_RADDR_LATCH_V1 24
+#define BIT_MASK_CSI_RADDR_LATCH_V1 0x3f
+#define BIT_CSI_RADDR_LATCH_V1(x)                                              \
+	(((x) & BIT_MASK_CSI_RADDR_LATCH_V1) << BIT_SHIFT_CSI_RADDR_LATCH_V1)
+#define BITS_CSI_RADDR_LATCH_V1                                                \
+	(BIT_MASK_CSI_RADDR_LATCH_V1 << BIT_SHIFT_CSI_RADDR_LATCH_V1)
+#define BIT_CLEAR_CSI_RADDR_LATCH_V1(x) ((x) & (~BITS_CSI_RADDR_LATCH_V1))
+#define BIT_GET_CSI_RADDR_LATCH_V1(x)                                          \
+	(((x) >> BIT_SHIFT_CSI_RADDR_LATCH_V1) & BIT_MASK_CSI_RADDR_LATCH_V1)
+#define BIT_SET_CSI_RADDR_LATCH_V1(x, v)                                       \
+	(BIT_CLEAR_CSI_RADDR_LATCH_V1(x) | BIT_CSI_RADDR_LATCH_V1(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT)
+
+/* 2 REG_RXCMD_1				(Offset 0x06D4) */
+
+#define BIT_SHIFT_CSI_RADDR_LATCH 24
+#define BIT_MASK_CSI_RADDR_LATCH 0xff
+#define BIT_CSI_RADDR_LATCH(x)                                                 \
+	(((x) & BIT_MASK_CSI_RADDR_LATCH) << BIT_SHIFT_CSI_RADDR_LATCH)
+#define BITS_CSI_RADDR_LATCH                                                   \
+	(BIT_MASK_CSI_RADDR_LATCH << BIT_SHIFT_CSI_RADDR_LATCH)
+#define BIT_CLEAR_CSI_RADDR_LATCH(x) ((x) & (~BITS_CSI_RADDR_LATCH))
+#define BIT_GET_CSI_RADDR_LATCH(x)                                             \
+	(((x) >> BIT_SHIFT_CSI_RADDR_LATCH) & BIT_MASK_CSI_RADDR_LATCH)
+#define BIT_SET_CSI_RADDR_LATCH(x, v)                                          \
+	(BIT_CLEAR_CSI_RADDR_LATCH(x) | BIT_CSI_RADDR_LATCH(v))
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_RXCMD_1				(Offset 0x06D4) */
+
+#define BIT_SHIFT_AID1 16
+#define BIT_MASK_AID1 0x1ff
+#define BIT_AID1(x) (((x) & BIT_MASK_AID1) << BIT_SHIFT_AID1)
+#define BITS_AID1 (BIT_MASK_AID1 << BIT_SHIFT_AID1)
+#define BIT_CLEAR_AID1(x) ((x) & (~BITS_AID1))
+#define BIT_GET_AID1(x) (((x) >> BIT_SHIFT_AID1) & BIT_MASK_AID1)
+#define BIT_SET_AID1(x, v) (BIT_CLEAR_AID1(x) | BIT_AID1(v))
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+/* 2 REG_RXCMD_1				(Offset 0x06D4) */
+
+#define BIT_SHIFT_CSI_WADDR_LATCH_V1 16
+#define BIT_MASK_CSI_WADDR_LATCH_V1 0x3f
+#define BIT_CSI_WADDR_LATCH_V1(x)                                              \
+	(((x) & BIT_MASK_CSI_WADDR_LATCH_V1) << BIT_SHIFT_CSI_WADDR_LATCH_V1)
+#define BITS_CSI_WADDR_LATCH_V1                                                \
+	(BIT_MASK_CSI_WADDR_LATCH_V1 << BIT_SHIFT_CSI_WADDR_LATCH_V1)
+#define BIT_CLEAR_CSI_WADDR_LATCH_V1(x) ((x) & (~BITS_CSI_WADDR_LATCH_V1))
+#define BIT_GET_CSI_WADDR_LATCH_V1(x)                                          \
+	(((x) >> BIT_SHIFT_CSI_WADDR_LATCH_V1) & BIT_MASK_CSI_WADDR_LATCH_V1)
+#define BIT_SET_CSI_WADDR_LATCH_V1(x, v)                                       \
+	(BIT_CLEAR_CSI_WADDR_LATCH_V1(x) | BIT_CSI_WADDR_LATCH_V1(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT)
+
+/* 2 REG_RXCMD_1				(Offset 0x06D4) */
+
+#define BIT_SHIFT_CSI_WADDR_LATCH 16
+#define BIT_MASK_CSI_WADDR_LATCH 0xff
+#define BIT_CSI_WADDR_LATCH(x)                                                 \
+	(((x) & BIT_MASK_CSI_WADDR_LATCH) << BIT_SHIFT_CSI_WADDR_LATCH)
+#define BITS_CSI_WADDR_LATCH                                                   \
+	(BIT_MASK_CSI_WADDR_LATCH << BIT_SHIFT_CSI_WADDR_LATCH)
+#define BIT_CLEAR_CSI_WADDR_LATCH(x) ((x) & (~BITS_CSI_WADDR_LATCH))
+#define BIT_GET_CSI_WADDR_LATCH(x)                                             \
+	(((x) >> BIT_SHIFT_CSI_WADDR_LATCH) & BIT_MASK_CSI_WADDR_LATCH)
+#define BIT_SET_CSI_WADDR_LATCH(x, v)                                          \
+	(BIT_CLEAR_CSI_WADDR_LATCH(x) | BIT_CSI_WADDR_LATCH(v))
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_RXCMD_1				(Offset 0x06D4) */
+
+#define BIT_TXUSER_ID0 BIT(9)
+
+#define BIT_SHIFT_RXCMD_PRD 0
+#define BIT_MASK_RXCMD_PRD 0xffff
+#define BIT_RXCMD_PRD(x) (((x) & BIT_MASK_RXCMD_PRD) << BIT_SHIFT_RXCMD_PRD)
+#define BITS_RXCMD_PRD (BIT_MASK_RXCMD_PRD << BIT_SHIFT_RXCMD_PRD)
+#define BIT_CLEAR_RXCMD_PRD(x) ((x) & (~BITS_RXCMD_PRD))
+#define BIT_GET_RXCMD_PRD(x) (((x) >> BIT_SHIFT_RXCMD_PRD) & BIT_MASK_RXCMD_PRD)
+#define BIT_SET_RXCMD_PRD(x, v) (BIT_CLEAR_RXCMD_PRD(x) | BIT_RXCMD_PRD(v))
+
+#define BIT_SHIFT_AID0 0
+#define BIT_MASK_AID0 0x1ff
+#define BIT_AID0(x) (((x) & BIT_MASK_AID0) << BIT_SHIFT_AID0)
+#define BITS_AID0 (BIT_MASK_AID0 << BIT_SHIFT_AID0)
+#define BIT_CLEAR_AID0(x) ((x) & (~BITS_AID0))
+#define BIT_GET_AID0(x) (((x) >> BIT_SHIFT_AID0) & BIT_MASK_AID0)
+#define BIT_SET_AID0(x, v) (BIT_CLEAR_AID0(x) | BIT_AID0(v))
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_RESP_TXINFO_CFG			(Offset 0x06D8) */
+
+#define BIT_SHIFT_RESP_MFB 25
+#define BIT_MASK_RESP_MFB 0x7f
+#define BIT_RESP_MFB(x) (((x) & BIT_MASK_RESP_MFB) << BIT_SHIFT_RESP_MFB)
+#define BITS_RESP_MFB (BIT_MASK_RESP_MFB << BIT_SHIFT_RESP_MFB)
+#define BIT_CLEAR_RESP_MFB(x) ((x) & (~BITS_RESP_MFB))
+#define BIT_GET_RESP_MFB(x) (((x) >> BIT_SHIFT_RESP_MFB) & BIT_MASK_RESP_MFB)
+#define BIT_SET_RESP_MFB(x, v) (BIT_CLEAR_RESP_MFB(x) | BIT_RESP_MFB(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_WMAC_RESP_TXINFO			(Offset 0x06D8) */
+
+#define BIT_SHIFT_WMAC_RESP_MFB 25
+#define BIT_MASK_WMAC_RESP_MFB 0x7f
+#define BIT_WMAC_RESP_MFB(x)                                                   \
+	(((x) & BIT_MASK_WMAC_RESP_MFB) << BIT_SHIFT_WMAC_RESP_MFB)
+#define BITS_WMAC_RESP_MFB (BIT_MASK_WMAC_RESP_MFB << BIT_SHIFT_WMAC_RESP_MFB)
+#define BIT_CLEAR_WMAC_RESP_MFB(x) ((x) & (~BITS_WMAC_RESP_MFB))
+#define BIT_GET_WMAC_RESP_MFB(x)                                               \
+	(((x) >> BIT_SHIFT_WMAC_RESP_MFB) & BIT_MASK_WMAC_RESP_MFB)
+#define BIT_SET_WMAC_RESP_MFB(x, v)                                            \
+	(BIT_CLEAR_WMAC_RESP_MFB(x) | BIT_WMAC_RESP_MFB(v))
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_RESP_TXINFO_CFG			(Offset 0x06D8) */
+
+#define BIT_SHIFT_ANTINF_SEL 23
+#define BIT_MASK_ANTINF_SEL 0x3
+#define BIT_ANTINF_SEL(x) (((x) & BIT_MASK_ANTINF_SEL) << BIT_SHIFT_ANTINF_SEL)
+#define BITS_ANTINF_SEL (BIT_MASK_ANTINF_SEL << BIT_SHIFT_ANTINF_SEL)
+#define BIT_CLEAR_ANTINF_SEL(x) ((x) & (~BITS_ANTINF_SEL))
+#define BIT_GET_ANTINF_SEL(x)                                                  \
+	(((x) >> BIT_SHIFT_ANTINF_SEL) & BIT_MASK_ANTINF_SEL)
+#define BIT_SET_ANTINF_SEL(x, v) (BIT_CLEAR_ANTINF_SEL(x) | BIT_ANTINF_SEL(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_WMAC_RESP_TXINFO			(Offset 0x06D8) */
+
+#define BIT_SHIFT_WMAC_ANTINF_SEL 23
+#define BIT_MASK_WMAC_ANTINF_SEL 0x3
+#define BIT_WMAC_ANTINF_SEL(x)                                                 \
+	(((x) & BIT_MASK_WMAC_ANTINF_SEL) << BIT_SHIFT_WMAC_ANTINF_SEL)
+#define BITS_WMAC_ANTINF_SEL                                                   \
+	(BIT_MASK_WMAC_ANTINF_SEL << BIT_SHIFT_WMAC_ANTINF_SEL)
+#define BIT_CLEAR_WMAC_ANTINF_SEL(x) ((x) & (~BITS_WMAC_ANTINF_SEL))
+#define BIT_GET_WMAC_ANTINF_SEL(x)                                             \
+	(((x) >> BIT_SHIFT_WMAC_ANTINF_SEL) & BIT_MASK_WMAC_ANTINF_SEL)
+#define BIT_SET_WMAC_ANTINF_SEL(x, v)                                          \
+	(BIT_CLEAR_WMAC_ANTINF_SEL(x) | BIT_WMAC_ANTINF_SEL(v))
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_RESP_TXINFO_CFG			(Offset 0x06D8) */
+
+#define BIT_SHIFT_ANTSEL_SEL 21
+#define BIT_MASK_ANTSEL_SEL 0x3
+#define BIT_ANTSEL_SEL(x) (((x) & BIT_MASK_ANTSEL_SEL) << BIT_SHIFT_ANTSEL_SEL)
+#define BITS_ANTSEL_SEL (BIT_MASK_ANTSEL_SEL << BIT_SHIFT_ANTSEL_SEL)
+#define BIT_CLEAR_ANTSEL_SEL(x) ((x) & (~BITS_ANTSEL_SEL))
+#define BIT_GET_ANTSEL_SEL(x)                                                  \
+	(((x) >> BIT_SHIFT_ANTSEL_SEL) & BIT_MASK_ANTSEL_SEL)
+#define BIT_SET_ANTSEL_SEL(x, v) (BIT_CLEAR_ANTSEL_SEL(x) | BIT_ANTSEL_SEL(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_WMAC_RESP_TXINFO			(Offset 0x06D8) */
+
+#define BIT_SHIFT_WMAC_ANTSEL_SEL 21
+#define BIT_MASK_WMAC_ANTSEL_SEL 0x3
+#define BIT_WMAC_ANTSEL_SEL(x)                                                 \
+	(((x) & BIT_MASK_WMAC_ANTSEL_SEL) << BIT_SHIFT_WMAC_ANTSEL_SEL)
+#define BITS_WMAC_ANTSEL_SEL                                                   \
+	(BIT_MASK_WMAC_ANTSEL_SEL << BIT_SHIFT_WMAC_ANTSEL_SEL)
+#define BIT_CLEAR_WMAC_ANTSEL_SEL(x) ((x) & (~BITS_WMAC_ANTSEL_SEL))
+#define BIT_GET_WMAC_ANTSEL_SEL(x)                                             \
+	(((x) >> BIT_SHIFT_WMAC_ANTSEL_SEL) & BIT_MASK_WMAC_ANTSEL_SEL)
+#define BIT_SET_WMAC_ANTSEL_SEL(x, v)                                          \
+	(BIT_CLEAR_WMAC_ANTSEL_SEL(x) | BIT_WMAC_ANTSEL_SEL(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+
+/* 2 REG_WMAC_RESP_TXINFO			(Offset 0x06D8) */
+
+#define BIT_SHIFT_R_WMAC_RESP_TXPOWER 18
+#define BIT_MASK_R_WMAC_RESP_TXPOWER 0x7
+#define BIT_R_WMAC_RESP_TXPOWER(x)                                             \
+	(((x) & BIT_MASK_R_WMAC_RESP_TXPOWER) << BIT_SHIFT_R_WMAC_RESP_TXPOWER)
+#define BITS_R_WMAC_RESP_TXPOWER                                               \
+	(BIT_MASK_R_WMAC_RESP_TXPOWER << BIT_SHIFT_R_WMAC_RESP_TXPOWER)
+#define BIT_CLEAR_R_WMAC_RESP_TXPOWER(x) ((x) & (~BITS_R_WMAC_RESP_TXPOWER))
+#define BIT_GET_R_WMAC_RESP_TXPOWER(x)                                         \
+	(((x) >> BIT_SHIFT_R_WMAC_RESP_TXPOWER) & BIT_MASK_R_WMAC_RESP_TXPOWER)
+#define BIT_SET_R_WMAC_RESP_TXPOWER(x, v)                                      \
+	(BIT_CLEAR_R_WMAC_RESP_TXPOWER(x) | BIT_R_WMAC_RESP_TXPOWER(v))
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_WMAC_RESP_TXINFO			(Offset 0x06D8) */
+
+#define BIT_SHIFT_WMAC_RESP_TXPOWER_OFFSET_TYPE 18
+#define BIT_MASK_WMAC_RESP_TXPOWER_OFFSET_TYPE 0x3
+#define BIT_WMAC_RESP_TXPOWER_OFFSET_TYPE(x)                                   \
+	(((x) & BIT_MASK_WMAC_RESP_TXPOWER_OFFSET_TYPE)                        \
+	 << BIT_SHIFT_WMAC_RESP_TXPOWER_OFFSET_TYPE)
+#define BITS_WMAC_RESP_TXPOWER_OFFSET_TYPE                                     \
+	(BIT_MASK_WMAC_RESP_TXPOWER_OFFSET_TYPE                                \
+	 << BIT_SHIFT_WMAC_RESP_TXPOWER_OFFSET_TYPE)
+#define BIT_CLEAR_WMAC_RESP_TXPOWER_OFFSET_TYPE(x)                             \
+	((x) & (~BITS_WMAC_RESP_TXPOWER_OFFSET_TYPE))
+#define BIT_GET_WMAC_RESP_TXPOWER_OFFSET_TYPE(x)                               \
+	(((x) >> BIT_SHIFT_WMAC_RESP_TXPOWER_OFFSET_TYPE) &                    \
+	 BIT_MASK_WMAC_RESP_TXPOWER_OFFSET_TYPE)
+#define BIT_SET_WMAC_RESP_TXPOWER_OFFSET_TYPE(x, v)                            \
+	(BIT_CLEAR_WMAC_RESP_TXPOWER_OFFSET_TYPE(x) |                          \
+	 BIT_WMAC_RESP_TXPOWER_OFFSET_TYPE(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_WMAC_RESP_TXINFO			(Offset 0x06D8) */
+
+#define BIT_SHIFT_RESP_TXAGC_B 13
+#define BIT_MASK_RESP_TXAGC_B 0x1f
+#define BIT_RESP_TXAGC_B(x)                                                    \
+	(((x) & BIT_MASK_RESP_TXAGC_B) << BIT_SHIFT_RESP_TXAGC_B)
+#define BITS_RESP_TXAGC_B (BIT_MASK_RESP_TXAGC_B << BIT_SHIFT_RESP_TXAGC_B)
+#define BIT_CLEAR_RESP_TXAGC_B(x) ((x) & (~BITS_RESP_TXAGC_B))
+#define BIT_GET_RESP_TXAGC_B(x)                                                \
+	(((x) >> BIT_SHIFT_RESP_TXAGC_B) & BIT_MASK_RESP_TXAGC_B)
+#define BIT_SET_RESP_TXAGC_B(x, v)                                             \
+	(BIT_CLEAR_RESP_TXAGC_B(x) | BIT_RESP_TXAGC_B(v))
+
+#define BIT_SHIFT_RESP_TXAGC_A 8
+#define BIT_MASK_RESP_TXAGC_A 0x1f
+#define BIT_RESP_TXAGC_A(x)                                                    \
+	(((x) & BIT_MASK_RESP_TXAGC_A) << BIT_SHIFT_RESP_TXAGC_A)
+#define BITS_RESP_TXAGC_A (BIT_MASK_RESP_TXAGC_A << BIT_SHIFT_RESP_TXAGC_A)
+#define BIT_CLEAR_RESP_TXAGC_A(x) ((x) & (~BITS_RESP_TXAGC_A))
+#define BIT_GET_RESP_TXAGC_A(x)                                                \
+	(((x) >> BIT_SHIFT_RESP_TXAGC_A) & BIT_MASK_RESP_TXAGC_A)
+#define BIT_SET_RESP_TXAGC_A(x, v)                                             \
+	(BIT_CLEAR_RESP_TXAGC_A(x) | BIT_RESP_TXAGC_A(v))
+
+#define BIT_RESP_ANTSEL_B BIT(7)
+#define BIT_RESP_ANTSEL_A BIT(6)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_WMAC_RESP_TXINFO			(Offset 0x06D8) */
+
+#define BIT_SHIFT_WMAC_RESP_TXANT_V1 6
+#define BIT_MASK_WMAC_RESP_TXANT_V1 0xfff
+#define BIT_WMAC_RESP_TXANT_V1(x)                                              \
+	(((x) & BIT_MASK_WMAC_RESP_TXANT_V1) << BIT_SHIFT_WMAC_RESP_TXANT_V1)
+#define BITS_WMAC_RESP_TXANT_V1                                                \
+	(BIT_MASK_WMAC_RESP_TXANT_V1 << BIT_SHIFT_WMAC_RESP_TXANT_V1)
+#define BIT_CLEAR_WMAC_RESP_TXANT_V1(x) ((x) & (~BITS_WMAC_RESP_TXANT_V1))
+#define BIT_GET_WMAC_RESP_TXANT_V1(x)                                          \
+	(((x) >> BIT_SHIFT_WMAC_RESP_TXANT_V1) & BIT_MASK_WMAC_RESP_TXANT_V1)
+#define BIT_SET_WMAC_RESP_TXANT_V1(x, v)                                       \
+	(BIT_CLEAR_WMAC_RESP_TXANT_V1(x) | BIT_WMAC_RESP_TXANT_V1(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_WMAC_RESP_TXINFO			(Offset 0x06D8) */
+
+#define BIT_SHIFT_RESP_TXANT_CCK 4
+#define BIT_MASK_RESP_TXANT_CCK 0x3
+#define BIT_RESP_TXANT_CCK(x)                                                  \
+	(((x) & BIT_MASK_RESP_TXANT_CCK) << BIT_SHIFT_RESP_TXANT_CCK)
+#define BITS_RESP_TXANT_CCK                                                    \
+	(BIT_MASK_RESP_TXANT_CCK << BIT_SHIFT_RESP_TXANT_CCK)
+#define BIT_CLEAR_RESP_TXANT_CCK(x) ((x) & (~BITS_RESP_TXANT_CCK))
+#define BIT_GET_RESP_TXANT_CCK(x)                                              \
+	(((x) >> BIT_SHIFT_RESP_TXANT_CCK) & BIT_MASK_RESP_TXANT_CCK)
+#define BIT_SET_RESP_TXANT_CCK(x, v)                                           \
+	(BIT_CLEAR_RESP_TXANT_CCK(x) | BIT_RESP_TXANT_CCK(v))
+
+#define BIT_SHIFT_RESP_TXANT_L 2
+#define BIT_MASK_RESP_TXANT_L 0x3
+#define BIT_RESP_TXANT_L(x)                                                    \
+	(((x) & BIT_MASK_RESP_TXANT_L) << BIT_SHIFT_RESP_TXANT_L)
+#define BITS_RESP_TXANT_L (BIT_MASK_RESP_TXANT_L << BIT_SHIFT_RESP_TXANT_L)
+#define BIT_CLEAR_RESP_TXANT_L(x) ((x) & (~BITS_RESP_TXANT_L))
+#define BIT_GET_RESP_TXANT_L(x)                                                \
+	(((x) >> BIT_SHIFT_RESP_TXANT_L) & BIT_MASK_RESP_TXANT_L)
+#define BIT_SET_RESP_TXANT_L(x, v)                                             \
+	(BIT_CLEAR_RESP_TXANT_L(x) | BIT_RESP_TXANT_L(v))
+
+#define BIT_SHIFT_RESP_TXANT_HT 0
+#define BIT_MASK_RESP_TXANT_HT 0x3
+#define BIT_RESP_TXANT_HT(x)                                                   \
+	(((x) & BIT_MASK_RESP_TXANT_HT) << BIT_SHIFT_RESP_TXANT_HT)
+#define BITS_RESP_TXANT_HT (BIT_MASK_RESP_TXANT_HT << BIT_SHIFT_RESP_TXANT_HT)
+#define BIT_CLEAR_RESP_TXANT_HT(x) ((x) & (~BITS_RESP_TXANT_HT))
+#define BIT_GET_RESP_TXANT_HT(x)                                               \
+	(((x) >> BIT_SHIFT_RESP_TXANT_HT) & BIT_MASK_RESP_TXANT_HT)
+#define BIT_SET_RESP_TXANT_HT(x, v)                                            \
+	(BIT_CLEAR_RESP_TXANT_HT(x) | BIT_RESP_TXANT_HT(v))
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_RESP_TXINFO_CFG			(Offset 0x06D8) */
+
+#define BIT_SHIFT_RESP_TXANT 0
+#define BIT_MASK_RESP_TXANT 0x3ffff
+#define BIT_RESP_TXANT(x) (((x) & BIT_MASK_RESP_TXANT) << BIT_SHIFT_RESP_TXANT)
+#define BITS_RESP_TXANT (BIT_MASK_RESP_TXANT << BIT_SHIFT_RESP_TXANT)
+#define BIT_CLEAR_RESP_TXANT(x) ((x) & (~BITS_RESP_TXANT))
+#define BIT_GET_RESP_TXANT(x)                                                  \
+	(((x) >> BIT_SHIFT_RESP_TXANT) & BIT_MASK_RESP_TXANT)
+#define BIT_SET_RESP_TXANT(x, v) (BIT_CLEAR_RESP_TXANT(x) | BIT_RESP_TXANT(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+
+/* 2 REG_WMAC_RESP_TXINFO			(Offset 0x06D8) */
+
+#define BIT_SHIFT_WMAC_RESP_TXANT 0
+#define BIT_MASK_WMAC_RESP_TXANT 0x3ffff
+#define BIT_WMAC_RESP_TXANT(x)                                                 \
+	(((x) & BIT_MASK_WMAC_RESP_TXANT) << BIT_SHIFT_WMAC_RESP_TXANT)
+#define BITS_WMAC_RESP_TXANT                                                   \
+	(BIT_MASK_WMAC_RESP_TXANT << BIT_SHIFT_WMAC_RESP_TXANT)
+#define BIT_CLEAR_WMAC_RESP_TXANT(x) ((x) & (~BITS_WMAC_RESP_TXANT))
+#define BIT_GET_WMAC_RESP_TXANT(x)                                             \
+	(((x) >> BIT_SHIFT_WMAC_RESP_TXANT) & BIT_MASK_WMAC_RESP_TXANT)
+#define BIT_SET_WMAC_RESP_TXANT(x, v)                                          \
+	(BIT_CLEAR_WMAC_RESP_TXANT(x) | BIT_WMAC_RESP_TXANT(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_BBPSF_CTRL				(Offset 0x06DC) */
+
+#define BIT_CTL_IDLE_CLR_CSI_RPT BIT(31)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_BBPSF_CTRL				(Offset 0x06DC) */
+
+#define BIT_WMAC_USE_NDPARATE BIT(30)
+
+#define BIT_SHIFT_WMAC_CSI_RATE 24
+#define BIT_MASK_WMAC_CSI_RATE 0x3f
+#define BIT_WMAC_CSI_RATE(x)                                                   \
+	(((x) & BIT_MASK_WMAC_CSI_RATE) << BIT_SHIFT_WMAC_CSI_RATE)
+#define BITS_WMAC_CSI_RATE (BIT_MASK_WMAC_CSI_RATE << BIT_SHIFT_WMAC_CSI_RATE)
+#define BIT_CLEAR_WMAC_CSI_RATE(x) ((x) & (~BITS_WMAC_CSI_RATE))
+#define BIT_GET_WMAC_CSI_RATE(x)                                               \
+	(((x) >> BIT_SHIFT_WMAC_CSI_RATE) & BIT_MASK_WMAC_CSI_RATE)
+#define BIT_SET_WMAC_CSI_RATE(x, v)                                            \
+	(BIT_CLEAR_WMAC_CSI_RATE(x) | BIT_WMAC_CSI_RATE(v))
+
+#define BIT_SHIFT_WMAC_RESP_TXRATE 16
+#define BIT_MASK_WMAC_RESP_TXRATE 0xff
+#define BIT_WMAC_RESP_TXRATE(x)                                                \
+	(((x) & BIT_MASK_WMAC_RESP_TXRATE) << BIT_SHIFT_WMAC_RESP_TXRATE)
+#define BITS_WMAC_RESP_TXRATE                                                  \
+	(BIT_MASK_WMAC_RESP_TXRATE << BIT_SHIFT_WMAC_RESP_TXRATE)
+#define BIT_CLEAR_WMAC_RESP_TXRATE(x) ((x) & (~BITS_WMAC_RESP_TXRATE))
+#define BIT_GET_WMAC_RESP_TXRATE(x)                                            \
+	(((x) >> BIT_SHIFT_WMAC_RESP_TXRATE) & BIT_MASK_WMAC_RESP_TXRATE)
+#define BIT_SET_WMAC_RESP_TXRATE(x, v)                                         \
+	(BIT_CLEAR_WMAC_RESP_TXRATE(x) | BIT_WMAC_RESP_TXRATE(v))
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+/* 2 REG_BBPSF_CTRL				(Offset 0x06DC) */
+
+#define BIT_WMAC_CSI_RATE_FORCE_EN BIT(15)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT)
+
+/* 2 REG_BBPSF_CTRL				(Offset 0x06DC) */
+
+#define BIT_CSI_FORCE_RATE_EN BIT(15)
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+/* 2 REG_BBPSF_CTRL				(Offset 0x06DC) */
+
+#define BIT_SHIFT_WMAC_CSI_RSC_FORCE 13
+#define BIT_MASK_WMAC_CSI_RSC_FORCE 0x3
+#define BIT_WMAC_CSI_RSC_FORCE(x)                                              \
+	(((x) & BIT_MASK_WMAC_CSI_RSC_FORCE) << BIT_SHIFT_WMAC_CSI_RSC_FORCE)
+#define BITS_WMAC_CSI_RSC_FORCE                                                \
+	(BIT_MASK_WMAC_CSI_RSC_FORCE << BIT_SHIFT_WMAC_CSI_RSC_FORCE)
+#define BIT_CLEAR_WMAC_CSI_RSC_FORCE(x) ((x) & (~BITS_WMAC_CSI_RSC_FORCE))
+#define BIT_GET_WMAC_CSI_RSC_FORCE(x)                                          \
+	(((x) >> BIT_SHIFT_WMAC_CSI_RSC_FORCE) & BIT_MASK_WMAC_CSI_RSC_FORCE)
+#define BIT_SET_WMAC_CSI_RSC_FORCE(x, v)                                       \
+	(BIT_CLEAR_WMAC_CSI_RSC_FORCE(x) | BIT_WMAC_CSI_RSC_FORCE(v))
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_BBPSF_CTRL				(Offset 0x06DC) */
+
+#define BIT_SHIFT_CSI_RSC 13
+#define BIT_MASK_CSI_RSC 0x3
+#define BIT_CSI_RSC(x) (((x) & BIT_MASK_CSI_RSC) << BIT_SHIFT_CSI_RSC)
+#define BITS_CSI_RSC (BIT_MASK_CSI_RSC << BIT_SHIFT_CSI_RSC)
+#define BIT_CLEAR_CSI_RSC(x) ((x) & (~BITS_CSI_RSC))
+#define BIT_GET_CSI_RSC(x) (((x) >> BIT_SHIFT_CSI_RSC) & BIT_MASK_CSI_RSC)
+#define BIT_SET_CSI_RSC(x, v) (BIT_CLEAR_CSI_RSC(x) | BIT_CSI_RSC(v))
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+/* 2 REG_BBPSF_CTRL				(Offset 0x06DC) */
+
+#define BIT_WMAC_CSI_GID_SEL BIT(12)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_BBPSF_CTRL				(Offset 0x06DC) */
+
+#define BIT_CSI_GID_SEL BIT(12)
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT)
+
+/* 2 REG_BBPSF_CTRL				(Offset 0x06DC) */
+
+#define BIT_RDCSIMD_FLAG_TRIG_SEL BIT(11)
+#define BIT_NDPVLD_POS_RST_FFPTR_DIS_V1 BIT(10)
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_BBPSF_CTRL				(Offset 0x06DC) */
+
+#define BIT_NDPVLD_PROTECT_RDRDY_DIS BIT(9)
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+/* 2 REG_BBPSF_CTRL				(Offset 0x06DC) */
+
+#define BIT_CSIRD_EMPTY_APPZERO BIT(8)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_BBPSF_CTRL				(Offset 0x06DC) */
+
+#define BIT_RDCSI_EMPTY_APPZERO BIT(8)
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+/* 2 REG_BBPSF_CTRL				(Offset 0x06DC) */
+
+#define BIT_WMC_CSI_RATE_FB_EN BIT(7)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_BBPSF_CTRL				(Offset 0x06DC) */
+
+#define BIT_CSI_RATE_FB_EN BIT(7)
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_BBPSF_CTRL				(Offset 0x06DC) */
+
+#define BIT_RXFIFO_WRPTR_WO_CHKSUM BIT(6)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+
+/* 2 REG_BBPSF_CTRL				(Offset 0x06DC) */
+
+#define BIT_BBPSF_MPDUCHKEN BIT(5)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT)
+
+/* 2 REG_BBPSF_CTRL				(Offset 0x06DC) */
+
+#define BIT_BBPSF_MHCHKEN BIT(4)
+#define BIT_BBPSF_ERRCHKEN BIT(3)
+
+#define BIT_SHIFT_BBPSF_ERRTHR 0
+#define BIT_MASK_BBPSF_ERRTHR 0x7
+#define BIT_BBPSF_ERRTHR(x)                                                    \
+	(((x) & BIT_MASK_BBPSF_ERRTHR) << BIT_SHIFT_BBPSF_ERRTHR)
+#define BITS_BBPSF_ERRTHR (BIT_MASK_BBPSF_ERRTHR << BIT_SHIFT_BBPSF_ERRTHR)
+#define BIT_CLEAR_BBPSF_ERRTHR(x) ((x) & (~BITS_BBPSF_ERRTHR))
+#define BIT_GET_BBPSF_ERRTHR(x)                                                \
+	(((x) >> BIT_SHIFT_BBPSF_ERRTHR) & BIT_MASK_BBPSF_ERRTHR)
+#define BIT_SET_BBPSF_ERRTHR(x, v)                                             \
+	(BIT_CLEAR_BBPSF_ERRTHR(x) | BIT_BBPSF_ERRTHR(v))
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_RESP_TXINFO_RATE			(Offset 0x06DE) */
+
+#define BIT_USE_NDPARATE BIT(14)
+
+#define BIT_SHIFT_CSI_RATE 8
+#define BIT_MASK_CSI_RATE 0x3f
+#define BIT_CSI_RATE(x) (((x) & BIT_MASK_CSI_RATE) << BIT_SHIFT_CSI_RATE)
+#define BITS_CSI_RATE (BIT_MASK_CSI_RATE << BIT_SHIFT_CSI_RATE)
+#define BIT_CLEAR_CSI_RATE(x) ((x) & (~BITS_CSI_RATE))
+#define BIT_GET_CSI_RATE(x) (((x) >> BIT_SHIFT_CSI_RATE) & BIT_MASK_CSI_RATE)
+#define BIT_SET_CSI_RATE(x, v) (BIT_CLEAR_CSI_RATE(x) | BIT_CSI_RATE(v))
+
+#define BIT_SHIFT_RESP_TXRATE 0
+#define BIT_MASK_RESP_TXRATE 0xff
+#define BIT_RESP_TXRATE(x)                                                     \
+	(((x) & BIT_MASK_RESP_TXRATE) << BIT_SHIFT_RESP_TXRATE)
+#define BITS_RESP_TXRATE (BIT_MASK_RESP_TXRATE << BIT_SHIFT_RESP_TXRATE)
+#define BIT_CLEAR_RESP_TXRATE(x) ((x) & (~BITS_RESP_TXRATE))
+#define BIT_GET_RESP_TXRATE(x)                                                 \
+	(((x) >> BIT_SHIFT_RESP_TXRATE) & BIT_MASK_RESP_TXRATE)
+#define BIT_SET_RESP_TXRATE(x, v)                                              \
+	(BIT_CLEAR_RESP_TXRATE(x) | BIT_RESP_TXRATE(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_P2P_RX_BCN_NOA			(Offset 0x06E0) */
+
+#define BIT_NOA_PARSER_EN BIT(15)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_P2P_RX_BCN_NOA			(Offset 0x06E0) */
+
+#define BIT_BSSID_SEL BIT(14)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_P2P_RX_BCN_NOA			(Offset 0x06E0) */
+
+#define BIT_SHIFT_BSSID_SEL_V1 12
+#define BIT_MASK_BSSID_SEL_V1 0x7
+#define BIT_BSSID_SEL_V1(x)                                                    \
+	(((x) & BIT_MASK_BSSID_SEL_V1) << BIT_SHIFT_BSSID_SEL_V1)
+#define BITS_BSSID_SEL_V1 (BIT_MASK_BSSID_SEL_V1 << BIT_SHIFT_BSSID_SEL_V1)
+#define BIT_CLEAR_BSSID_SEL_V1(x) ((x) & (~BITS_BSSID_SEL_V1))
+#define BIT_GET_BSSID_SEL_V1(x)                                                \
+	(((x) >> BIT_SHIFT_BSSID_SEL_V1) & BIT_MASK_BSSID_SEL_V1)
+#define BIT_SET_BSSID_SEL_V1(x, v)                                             \
+	(BIT_CLEAR_BSSID_SEL_V1(x) | BIT_BSSID_SEL_V1(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_P2P_RX_BCN_NOA			(Offset 0x06E0) */
+
+#define BIT_SHIFT_P2P_OUI_TYPE 0
+#define BIT_MASK_P2P_OUI_TYPE 0xff
+#define BIT_P2P_OUI_TYPE(x)                                                    \
+	(((x) & BIT_MASK_P2P_OUI_TYPE) << BIT_SHIFT_P2P_OUI_TYPE)
+#define BITS_P2P_OUI_TYPE (BIT_MASK_P2P_OUI_TYPE << BIT_SHIFT_P2P_OUI_TYPE)
+#define BIT_CLEAR_P2P_OUI_TYPE(x) ((x) & (~BITS_P2P_OUI_TYPE))
+#define BIT_GET_P2P_OUI_TYPE(x)                                                \
+	(((x) >> BIT_SHIFT_P2P_OUI_TYPE) & BIT_MASK_P2P_OUI_TYPE)
+#define BIT_SET_P2P_OUI_TYPE(x, v)                                             \
+	(BIT_CLEAR_P2P_OUI_TYPE(x) | BIT_P2P_OUI_TYPE(v))
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_P2P_RX_BCN_NOA			(Offset 0x06E0) */
+
+#define BIT_SHIFT_INFO_TXRPT_OFFSET_V1 0
+#define BIT_MASK_INFO_TXRPT_OFFSET_V1 0x1fff
+#define BIT_INFO_TXRPT_OFFSET_V1(x)                                            \
+	(((x) & BIT_MASK_INFO_TXRPT_OFFSET_V1)                                 \
+	 << BIT_SHIFT_INFO_TXRPT_OFFSET_V1)
+#define BITS_INFO_TXRPT_OFFSET_V1                                              \
+	(BIT_MASK_INFO_TXRPT_OFFSET_V1 << BIT_SHIFT_INFO_TXRPT_OFFSET_V1)
+#define BIT_CLEAR_INFO_TXRPT_OFFSET_V1(x) ((x) & (~BITS_INFO_TXRPT_OFFSET_V1))
+#define BIT_GET_INFO_TXRPT_OFFSET_V1(x)                                        \
+	(((x) >> BIT_SHIFT_INFO_TXRPT_OFFSET_V1) &                             \
+	 BIT_MASK_INFO_TXRPT_OFFSET_V1)
+#define BIT_SET_INFO_TXRPT_OFFSET_V1(x, v)                                     \
+	(BIT_CLEAR_INFO_TXRPT_OFFSET_V1(x) | BIT_INFO_TXRPT_OFFSET_V1(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT || \
+     HALMAC_8881A_SUPPORT)
+
+/* 2 REG_ASSOCIATED_BFMER0_INFO		(Offset 0x06E4) */
+
+#define BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0 0
+#define BIT_MASK_R_WMAC_SOUNDING_RXADD_R0 0xffffffffffffL
+#define BIT_R_WMAC_SOUNDING_RXADD_R0(x)                                        \
+	(((x) & BIT_MASK_R_WMAC_SOUNDING_RXADD_R0)                             \
+	 << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0)
+#define BITS_R_WMAC_SOUNDING_RXADD_R0                                          \
+	(BIT_MASK_R_WMAC_SOUNDING_RXADD_R0                                     \
+	 << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0)
+#define BIT_CLEAR_R_WMAC_SOUNDING_RXADD_R0(x)                                  \
+	((x) & (~BITS_R_WMAC_SOUNDING_RXADD_R0))
+#define BIT_GET_R_WMAC_SOUNDING_RXADD_R0(x)                                    \
+	(((x) >> BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0) &                         \
+	 BIT_MASK_R_WMAC_SOUNDING_RXADD_R0)
+#define BIT_SET_R_WMAC_SOUNDING_RXADD_R0(x, v)                                 \
+	(BIT_CLEAR_R_WMAC_SOUNDING_RXADD_R0(x) |                               \
+	 BIT_R_WMAC_SOUNDING_RXADD_R0(v))
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_ASSOCIATED_BFMER0_INFO		(Offset 0x06E4) */
+
+#define BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0_V1 0
+#define BIT_MASK_R_WMAC_SOUNDING_RXADD_R0_V1 0xffffffffL
+#define BIT_R_WMAC_SOUNDING_RXADD_R0_V1(x)                                     \
+	(((x) & BIT_MASK_R_WMAC_SOUNDING_RXADD_R0_V1)                          \
+	 << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0_V1)
+#define BITS_R_WMAC_SOUNDING_RXADD_R0_V1                                       \
+	(BIT_MASK_R_WMAC_SOUNDING_RXADD_R0_V1                                  \
+	 << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0_V1)
+#define BIT_CLEAR_R_WMAC_SOUNDING_RXADD_R0_V1(x)                               \
+	((x) & (~BITS_R_WMAC_SOUNDING_RXADD_R0_V1))
+#define BIT_GET_R_WMAC_SOUNDING_RXADD_R0_V1(x)                                 \
+	(((x) >> BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0_V1) &                      \
+	 BIT_MASK_R_WMAC_SOUNDING_RXADD_R0_V1)
+#define BIT_SET_R_WMAC_SOUNDING_RXADD_R0_V1(x, v)                              \
+	(BIT_CLEAR_R_WMAC_SOUNDING_RXADD_R0_V1(x) |                            \
+	 BIT_R_WMAC_SOUNDING_RXADD_R0_V1(v))
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_SOUNDING_CFG1			(Offset 0x06E8) */
+
+#define BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0_H 0
+#define BIT_MASK_R_WMAC_SOUNDING_RXADD_R0_H 0xffff
+#define BIT_R_WMAC_SOUNDING_RXADD_R0_H(x)                                      \
+	(((x) & BIT_MASK_R_WMAC_SOUNDING_RXADD_R0_H)                           \
+	 << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0_H)
+#define BITS_R_WMAC_SOUNDING_RXADD_R0_H                                        \
+	(BIT_MASK_R_WMAC_SOUNDING_RXADD_R0_H                                   \
+	 << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0_H)
+#define BIT_CLEAR_R_WMAC_SOUNDING_RXADD_R0_H(x)                                \
+	((x) & (~BITS_R_WMAC_SOUNDING_RXADD_R0_H))
+#define BIT_GET_R_WMAC_SOUNDING_RXADD_R0_H(x)                                  \
+	(((x) >> BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0_H) &                       \
+	 BIT_MASK_R_WMAC_SOUNDING_RXADD_R0_H)
+#define BIT_SET_R_WMAC_SOUNDING_RXADD_R0_H(x, v)                               \
+	(BIT_CLEAR_R_WMAC_SOUNDING_RXADD_R0_H(x) |                             \
+	 BIT_R_WMAC_SOUNDING_RXADD_R0_H(v))
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_ASSOCIATED_BFMER0_INFO_H		(Offset 0x06E8) */
+
+#define BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0_H_V1 0
+#define BIT_MASK_R_WMAC_SOUNDING_RXADD_R0_H_V1 0xffff
+#define BIT_R_WMAC_SOUNDING_RXADD_R0_H_V1(x)                                   \
+	(((x) & BIT_MASK_R_WMAC_SOUNDING_RXADD_R0_H_V1)                        \
+	 << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0_H_V1)
+#define BITS_R_WMAC_SOUNDING_RXADD_R0_H_V1                                     \
+	(BIT_MASK_R_WMAC_SOUNDING_RXADD_R0_H_V1                                \
+	 << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0_H_V1)
+#define BIT_CLEAR_R_WMAC_SOUNDING_RXADD_R0_H_V1(x)                             \
+	((x) & (~BITS_R_WMAC_SOUNDING_RXADD_R0_H_V1))
+#define BIT_GET_R_WMAC_SOUNDING_RXADD_R0_H_V1(x)                               \
+	(((x) >> BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0_H_V1) &                    \
+	 BIT_MASK_R_WMAC_SOUNDING_RXADD_R0_H_V1)
+#define BIT_SET_R_WMAC_SOUNDING_RXADD_R0_H_V1(x, v)                            \
+	(BIT_CLEAR_R_WMAC_SOUNDING_RXADD_R0_H_V1(x) |                          \
+	 BIT_R_WMAC_SOUNDING_RXADD_R0_H_V1(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT || \
+     HALMAC_8881A_SUPPORT)
+
+/* 2 REG_ASSOCIATED_BFMER1_INFO		(Offset 0x06EC) */
+
+#define BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1 0
+#define BIT_MASK_R_WMAC_SOUNDING_RXADD_R1 0xffffffffffffL
+#define BIT_R_WMAC_SOUNDING_RXADD_R1(x)                                        \
+	(((x) & BIT_MASK_R_WMAC_SOUNDING_RXADD_R1)                             \
+	 << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1)
+#define BITS_R_WMAC_SOUNDING_RXADD_R1                                          \
+	(BIT_MASK_R_WMAC_SOUNDING_RXADD_R1                                     \
+	 << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1)
+#define BIT_CLEAR_R_WMAC_SOUNDING_RXADD_R1(x)                                  \
+	((x) & (~BITS_R_WMAC_SOUNDING_RXADD_R1))
+#define BIT_GET_R_WMAC_SOUNDING_RXADD_R1(x)                                    \
+	(((x) >> BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1) &                         \
+	 BIT_MASK_R_WMAC_SOUNDING_RXADD_R1)
+#define BIT_SET_R_WMAC_SOUNDING_RXADD_R1(x, v)                                 \
+	(BIT_CLEAR_R_WMAC_SOUNDING_RXADD_R1(x) |                               \
+	 BIT_R_WMAC_SOUNDING_RXADD_R1(v))
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_SOUNDING_CFG2			(Offset 0x06EC) */
+
+#define BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1_V2 0
+#define BIT_MASK_R_WMAC_SOUNDING_RXADD_R1_V2 0xffffffffL
+#define BIT_R_WMAC_SOUNDING_RXADD_R1_V2(x)                                     \
+	(((x) & BIT_MASK_R_WMAC_SOUNDING_RXADD_R1_V2)                          \
+	 << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1_V2)
+#define BITS_R_WMAC_SOUNDING_RXADD_R1_V2                                       \
+	(BIT_MASK_R_WMAC_SOUNDING_RXADD_R1_V2                                  \
+	 << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1_V2)
+#define BIT_CLEAR_R_WMAC_SOUNDING_RXADD_R1_V2(x)                               \
+	((x) & (~BITS_R_WMAC_SOUNDING_RXADD_R1_V2))
+#define BIT_GET_R_WMAC_SOUNDING_RXADD_R1_V2(x)                                 \
+	(((x) >> BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1_V2) &                      \
+	 BIT_MASK_R_WMAC_SOUNDING_RXADD_R1_V2)
+#define BIT_SET_R_WMAC_SOUNDING_RXADD_R1_V2(x, v)                              \
+	(BIT_CLEAR_R_WMAC_SOUNDING_RXADD_R1_V2(x) |                            \
+	 BIT_R_WMAC_SOUNDING_RXADD_R1_V2(v))
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_ASSOCIATED_BFMER1_INFO		(Offset 0x06EC) */
+
+#define BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1_V1 0
+#define BIT_MASK_R_WMAC_SOUNDING_RXADD_R1_V1 0xffffffffL
+#define BIT_R_WMAC_SOUNDING_RXADD_R1_V1(x)                                     \
+	(((x) & BIT_MASK_R_WMAC_SOUNDING_RXADD_R1_V1)                          \
+	 << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1_V1)
+#define BITS_R_WMAC_SOUNDING_RXADD_R1_V1                                       \
+	(BIT_MASK_R_WMAC_SOUNDING_RXADD_R1_V1                                  \
+	 << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1_V1)
+#define BIT_CLEAR_R_WMAC_SOUNDING_RXADD_R1_V1(x)                               \
+	((x) & (~BITS_R_WMAC_SOUNDING_RXADD_R1_V1))
+#define BIT_GET_R_WMAC_SOUNDING_RXADD_R1_V1(x)                                 \
+	(((x) >> BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1_V1) &                      \
+	 BIT_MASK_R_WMAC_SOUNDING_RXADD_R1_V1)
+#define BIT_SET_R_WMAC_SOUNDING_RXADD_R1_V1(x, v)                              \
+	(BIT_CLEAR_R_WMAC_SOUNDING_RXADD_R1_V1(x) |                            \
+	 BIT_R_WMAC_SOUNDING_RXADD_R1_V1(v))
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_SOUNDING_CFG3			(Offset 0x06F0) */
+
+#define BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1_H_V2 0
+#define BIT_MASK_R_WMAC_SOUNDING_RXADD_R1_H_V2 0xffff
+#define BIT_R_WMAC_SOUNDING_RXADD_R1_H_V2(x)                                   \
+	(((x) & BIT_MASK_R_WMAC_SOUNDING_RXADD_R1_H_V2)                        \
+	 << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1_H_V2)
+#define BITS_R_WMAC_SOUNDING_RXADD_R1_H_V2                                     \
+	(BIT_MASK_R_WMAC_SOUNDING_RXADD_R1_H_V2                                \
+	 << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1_H_V2)
+#define BIT_CLEAR_R_WMAC_SOUNDING_RXADD_R1_H_V2(x)                             \
+	((x) & (~BITS_R_WMAC_SOUNDING_RXADD_R1_H_V2))
+#define BIT_GET_R_WMAC_SOUNDING_RXADD_R1_H_V2(x)                               \
+	(((x) >> BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1_H_V2) &                    \
+	 BIT_MASK_R_WMAC_SOUNDING_RXADD_R1_H_V2)
+#define BIT_SET_R_WMAC_SOUNDING_RXADD_R1_H_V2(x, v)                            \
+	(BIT_CLEAR_R_WMAC_SOUNDING_RXADD_R1_H_V2(x) |                          \
+	 BIT_R_WMAC_SOUNDING_RXADD_R1_H_V2(v))
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_ASSOCIATED_BFMER1_INFO_H		(Offset 0x06F0) */
+
+#define BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1_H_V1 0
+#define BIT_MASK_R_WMAC_SOUNDING_RXADD_R1_H_V1 0xffff
+#define BIT_R_WMAC_SOUNDING_RXADD_R1_H_V1(x)                                   \
+	(((x) & BIT_MASK_R_WMAC_SOUNDING_RXADD_R1_H_V1)                        \
+	 << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1_H_V1)
+#define BITS_R_WMAC_SOUNDING_RXADD_R1_H_V1                                     \
+	(BIT_MASK_R_WMAC_SOUNDING_RXADD_R1_H_V1                                \
+	 << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1_H_V1)
+#define BIT_CLEAR_R_WMAC_SOUNDING_RXADD_R1_H_V1(x)                             \
+	((x) & (~BITS_R_WMAC_SOUNDING_RXADD_R1_H_V1))
+#define BIT_GET_R_WMAC_SOUNDING_RXADD_R1_H_V1(x)                               \
+	(((x) >> BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1_H_V1) &                    \
+	 BIT_MASK_R_WMAC_SOUNDING_RXADD_R1_H_V1)
+#define BIT_SET_R_WMAC_SOUNDING_RXADD_R1_H_V1(x, v)                            \
+	(BIT_CLEAR_R_WMAC_SOUNDING_RXADD_R1_H_V1(x) |                          \
+	 BIT_R_WMAC_SOUNDING_RXADD_R1_H_V1(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_TX_CSI_RPT_PARAM_BW40		(Offset 0x06F8) */
+
+#define BIT_SHIFT_R_WMAC_BFINFO_40M_1 13
+#define BIT_MASK_R_WMAC_BFINFO_40M_1 0x7fff
+#define BIT_R_WMAC_BFINFO_40M_1(x)                                             \
+	(((x) & BIT_MASK_R_WMAC_BFINFO_40M_1) << BIT_SHIFT_R_WMAC_BFINFO_40M_1)
+#define BITS_R_WMAC_BFINFO_40M_1                                               \
+	(BIT_MASK_R_WMAC_BFINFO_40M_1 << BIT_SHIFT_R_WMAC_BFINFO_40M_1)
+#define BIT_CLEAR_R_WMAC_BFINFO_40M_1(x) ((x) & (~BITS_R_WMAC_BFINFO_40M_1))
+#define BIT_GET_R_WMAC_BFINFO_40M_1(x)                                         \
+	(((x) >> BIT_SHIFT_R_WMAC_BFINFO_40M_1) & BIT_MASK_R_WMAC_BFINFO_40M_1)
+#define BIT_SET_R_WMAC_BFINFO_40M_1(x, v)                                      \
+	(BIT_CLEAR_R_WMAC_BFINFO_40M_1(x) | BIT_R_WMAC_BFINFO_40M_1(v))
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_TX_CSI_RPT_PARAM_BW40		(Offset 0x06F8) */
+
+#define BIT_SHIFT_WMAC_RESP_ANTD 12
+#define BIT_MASK_WMAC_RESP_ANTD 0xf
+#define BIT_WMAC_RESP_ANTD(x)                                                  \
+	(((x) & BIT_MASK_WMAC_RESP_ANTD) << BIT_SHIFT_WMAC_RESP_ANTD)
+#define BITS_WMAC_RESP_ANTD                                                    \
+	(BIT_MASK_WMAC_RESP_ANTD << BIT_SHIFT_WMAC_RESP_ANTD)
+#define BIT_CLEAR_WMAC_RESP_ANTD(x) ((x) & (~BITS_WMAC_RESP_ANTD))
+#define BIT_GET_WMAC_RESP_ANTD(x)                                              \
+	(((x) >> BIT_SHIFT_WMAC_RESP_ANTD) & BIT_MASK_WMAC_RESP_ANTD)
+#define BIT_SET_WMAC_RESP_ANTD(x, v)                                           \
+	(BIT_CLEAR_WMAC_RESP_ANTD(x) | BIT_WMAC_RESP_ANTD(v))
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_ANTCD_INFO				(Offset 0x06F8) */
+
+#define BIT_RESP_SMOOTH BIT(8)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_TX_CSI_RPT_PARAM_BW40		(Offset 0x06F8) */
+
+#define BIT_SHIFT_WMAC_RESP_ANTC 8
+#define BIT_MASK_WMAC_RESP_ANTC 0xf
+#define BIT_WMAC_RESP_ANTC(x)                                                  \
+	(((x) & BIT_MASK_WMAC_RESP_ANTC) << BIT_SHIFT_WMAC_RESP_ANTC)
+#define BITS_WMAC_RESP_ANTC                                                    \
+	(BIT_MASK_WMAC_RESP_ANTC << BIT_SHIFT_WMAC_RESP_ANTC)
+#define BIT_CLEAR_WMAC_RESP_ANTC(x) ((x) & (~BITS_WMAC_RESP_ANTC))
+#define BIT_GET_WMAC_RESP_ANTC(x)                                              \
+	(((x) >> BIT_SHIFT_WMAC_RESP_ANTC) & BIT_MASK_WMAC_RESP_ANTC)
+#define BIT_SET_WMAC_RESP_ANTC(x, v)                                           \
+	(BIT_CLEAR_WMAC_RESP_ANTC(x) | BIT_WMAC_RESP_ANTC(v))
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_ANTCD_INFO				(Offset 0x06F8) */
+
+#define BIT_SHIFT_POWER_STAGE2_NORETRY 6
+#define BIT_MASK_POWER_STAGE2_NORETRY 0x3
+#define BIT_POWER_STAGE2_NORETRY(x)                                            \
+	(((x) & BIT_MASK_POWER_STAGE2_NORETRY)                                 \
+	 << BIT_SHIFT_POWER_STAGE2_NORETRY)
+#define BITS_POWER_STAGE2_NORETRY                                              \
+	(BIT_MASK_POWER_STAGE2_NORETRY << BIT_SHIFT_POWER_STAGE2_NORETRY)
+#define BIT_CLEAR_POWER_STAGE2_NORETRY(x) ((x) & (~BITS_POWER_STAGE2_NORETRY))
+#define BIT_GET_POWER_STAGE2_NORETRY(x)                                        \
+	(((x) >> BIT_SHIFT_POWER_STAGE2_NORETRY) &                             \
+	 BIT_MASK_POWER_STAGE2_NORETRY)
+#define BIT_SET_POWER_STAGE2_NORETRY(x, v)                                     \
+	(BIT_CLEAR_POWER_STAGE2_NORETRY(x) | BIT_POWER_STAGE2_NORETRY(v))
+
+#define BIT_SHIFT_POWER_STAGE1_NORETRY 4
+#define BIT_MASK_POWER_STAGE1_NORETRY 0x3
+#define BIT_POWER_STAGE1_NORETRY(x)                                            \
+	(((x) & BIT_MASK_POWER_STAGE1_NORETRY)                                 \
+	 << BIT_SHIFT_POWER_STAGE1_NORETRY)
+#define BITS_POWER_STAGE1_NORETRY                                              \
+	(BIT_MASK_POWER_STAGE1_NORETRY << BIT_SHIFT_POWER_STAGE1_NORETRY)
+#define BIT_CLEAR_POWER_STAGE1_NORETRY(x) ((x) & (~BITS_POWER_STAGE1_NORETRY))
+#define BIT_GET_POWER_STAGE1_NORETRY(x)                                        \
+	(((x) >> BIT_SHIFT_POWER_STAGE1_NORETRY) &                             \
+	 BIT_MASK_POWER_STAGE1_NORETRY)
+#define BIT_SET_POWER_STAGE1_NORETRY(x, v)                                     \
+	(BIT_CLEAR_POWER_STAGE1_NORETRY(x) | BIT_POWER_STAGE1_NORETRY(v))
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_TX_CSI_RPT_PARAM_BW40		(Offset 0x06F8) */
+
+#define BIT_SHIFT_WMAC_RESP_ANTB 4
+#define BIT_MASK_WMAC_RESP_ANTB 0xf
+#define BIT_WMAC_RESP_ANTB(x)                                                  \
+	(((x) & BIT_MASK_WMAC_RESP_ANTB) << BIT_SHIFT_WMAC_RESP_ANTB)
+#define BITS_WMAC_RESP_ANTB                                                    \
+	(BIT_MASK_WMAC_RESP_ANTB << BIT_SHIFT_WMAC_RESP_ANTB)
+#define BIT_CLEAR_WMAC_RESP_ANTB(x) ((x) & (~BITS_WMAC_RESP_ANTB))
+#define BIT_GET_WMAC_RESP_ANTB(x)                                              \
+	(((x) >> BIT_SHIFT_WMAC_RESP_ANTB) & BIT_MASK_WMAC_RESP_ANTB)
+#define BIT_SET_WMAC_RESP_ANTB(x, v)                                           \
+	(BIT_CLEAR_WMAC_RESP_ANTB(x) | BIT_WMAC_RESP_ANTB(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_TX_CSI_RPT_PARAM_BW40		(Offset 0x06F8) */
+
+#define BIT_SHIFT_R_WMAC_BFINFO_40M_0 0
+#define BIT_MASK_R_WMAC_BFINFO_40M_0 0xfff
+#define BIT_R_WMAC_BFINFO_40M_0(x)                                             \
+	(((x) & BIT_MASK_R_WMAC_BFINFO_40M_0) << BIT_SHIFT_R_WMAC_BFINFO_40M_0)
+#define BITS_R_WMAC_BFINFO_40M_0                                               \
+	(BIT_MASK_R_WMAC_BFINFO_40M_0 << BIT_SHIFT_R_WMAC_BFINFO_40M_0)
+#define BIT_CLEAR_R_WMAC_BFINFO_40M_0(x) ((x) & (~BITS_R_WMAC_BFINFO_40M_0))
+#define BIT_GET_R_WMAC_BFINFO_40M_0(x)                                         \
+	(((x) >> BIT_SHIFT_R_WMAC_BFINFO_40M_0) & BIT_MASK_R_WMAC_BFINFO_40M_0)
+#define BIT_SET_R_WMAC_BFINFO_40M_0(x, v)                                      \
+	(BIT_CLEAR_R_WMAC_BFINFO_40M_0(x) | BIT_R_WMAC_BFINFO_40M_0(v))
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_ANTCD_INFO				(Offset 0x06F8) */
+
+#define BIT_SHIFT_RESP_ANTCD 0
+#define BIT_MASK_RESP_ANTCD 0xf
+#define BIT_RESP_ANTCD(x) (((x) & BIT_MASK_RESP_ANTCD) << BIT_SHIFT_RESP_ANTCD)
+#define BITS_RESP_ANTCD (BIT_MASK_RESP_ANTCD << BIT_SHIFT_RESP_ANTCD)
+#define BIT_CLEAR_RESP_ANTCD(x) ((x) & (~BITS_RESP_ANTCD))
+#define BIT_GET_RESP_ANTCD(x)                                                  \
+	(((x) >> BIT_SHIFT_RESP_ANTCD) & BIT_MASK_RESP_ANTCD)
+#define BIT_SET_RESP_ANTCD(x, v) (BIT_CLEAR_RESP_ANTCD(x) | BIT_RESP_ANTCD(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+
+/* 2 REG_TX_CSI_RPT_PARAM_BW40		(Offset 0x06F8) */
+
+#define BIT_SHIFT_WMAC_RESP_ANTCD 0
+#define BIT_MASK_WMAC_RESP_ANTCD 0xf
+#define BIT_WMAC_RESP_ANTCD(x)                                                 \
+	(((x) & BIT_MASK_WMAC_RESP_ANTCD) << BIT_SHIFT_WMAC_RESP_ANTCD)
+#define BITS_WMAC_RESP_ANTCD                                                   \
+	(BIT_MASK_WMAC_RESP_ANTCD << BIT_SHIFT_WMAC_RESP_ANTCD)
+#define BIT_CLEAR_WMAC_RESP_ANTCD(x) ((x) & (~BITS_WMAC_RESP_ANTCD))
+#define BIT_GET_WMAC_RESP_ANTCD(x)                                             \
+	(((x) >> BIT_SHIFT_WMAC_RESP_ANTCD) & BIT_MASK_WMAC_RESP_ANTCD)
+#define BIT_SET_WMAC_RESP_ANTCD(x, v)                                          \
+	(BIT_CLEAR_WMAC_RESP_ANTCD(x) | BIT_WMAC_RESP_ANTCD(v))
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_TX_CSI_RPT_PARAM_BW40		(Offset 0x06F8) */
+
+#define BIT_SHIFT_WMAC_RESP_ANTA 0
+#define BIT_MASK_WMAC_RESP_ANTA 0xf
+#define BIT_WMAC_RESP_ANTA(x)                                                  \
+	(((x) & BIT_MASK_WMAC_RESP_ANTA) << BIT_SHIFT_WMAC_RESP_ANTA)
+#define BITS_WMAC_RESP_ANTA                                                    \
+	(BIT_MASK_WMAC_RESP_ANTA << BIT_SHIFT_WMAC_RESP_ANTA)
+#define BIT_CLEAR_WMAC_RESP_ANTA(x) ((x) & (~BITS_WMAC_RESP_ANTA))
+#define BIT_GET_WMAC_RESP_ANTA(x)                                              \
+	(((x) >> BIT_SHIFT_WMAC_RESP_ANTA) & BIT_MASK_WMAC_RESP_ANTA)
+#define BIT_SET_WMAC_RESP_ANTA(x, v)                                           \
+	(BIT_CLEAR_WMAC_RESP_ANTA(x) | BIT_WMAC_RESP_ANTA(v))
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+/* 2 REG_CSI_RRSR_V1				(Offset 0x06FC) */
+
+#define BIT_WMAC_CSI_LDPC_EN BIT(29)
+#define BIT_WMAC_CSI_STBC_EN BIT(28)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8881A_SUPPORT)
+
+/* 2 REG_TX_CSI_RPT_PARAM_BW80		(Offset 0x06FC) */
+
+#define BIT_SHIFT_R_WMAC_BFINFO_80M_1 16
+#define BIT_MASK_R_WMAC_BFINFO_80M_1 0xfff
+#define BIT_R_WMAC_BFINFO_80M_1(x)                                             \
+	(((x) & BIT_MASK_R_WMAC_BFINFO_80M_1) << BIT_SHIFT_R_WMAC_BFINFO_80M_1)
+#define BITS_R_WMAC_BFINFO_80M_1                                               \
+	(BIT_MASK_R_WMAC_BFINFO_80M_1 << BIT_SHIFT_R_WMAC_BFINFO_80M_1)
+#define BIT_CLEAR_R_WMAC_BFINFO_80M_1(x) ((x) & (~BITS_R_WMAC_BFINFO_80M_1))
+#define BIT_GET_R_WMAC_BFINFO_80M_1(x)                                         \
+	(((x) >> BIT_SHIFT_R_WMAC_BFINFO_80M_1) & BIT_MASK_R_WMAC_BFINFO_80M_1)
+#define BIT_SET_R_WMAC_BFINFO_80M_1(x, v)                                      \
+	(BIT_CLEAR_R_WMAC_BFINFO_80M_1(x) | BIT_R_WMAC_BFINFO_80M_1(v))
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_CSI_PTR				(Offset 0x06FC) */
+
+#define BIT_SHIFT_CSI_RADDR_LATCH_V2 16
+#define BIT_MASK_CSI_RADDR_LATCH_V2 0xffff
+#define BIT_CSI_RADDR_LATCH_V2(x)                                              \
+	(((x) & BIT_MASK_CSI_RADDR_LATCH_V2) << BIT_SHIFT_CSI_RADDR_LATCH_V2)
+#define BITS_CSI_RADDR_LATCH_V2                                                \
+	(BIT_MASK_CSI_RADDR_LATCH_V2 << BIT_SHIFT_CSI_RADDR_LATCH_V2)
+#define BIT_CLEAR_CSI_RADDR_LATCH_V2(x) ((x) & (~BITS_CSI_RADDR_LATCH_V2))
+#define BIT_GET_CSI_RADDR_LATCH_V2(x)                                          \
+	(((x) >> BIT_SHIFT_CSI_RADDR_LATCH_V2) & BIT_MASK_CSI_RADDR_LATCH_V2)
+#define BIT_SET_CSI_RADDR_LATCH_V2(x, v)                                       \
+	(BIT_CLEAR_CSI_RADDR_LATCH_V2(x) | BIT_CSI_RADDR_LATCH_V2(v))
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+/* 2 REG_CSI_RRSR_V1				(Offset 0x06FC) */
+
+#define BIT_SHIFT_WMAC_CSI_RRSC_BITMAP 4
+#define BIT_MASK_WMAC_CSI_RRSC_BITMAP 0xffffff
+#define BIT_WMAC_CSI_RRSC_BITMAP(x)                                            \
+	(((x) & BIT_MASK_WMAC_CSI_RRSC_BITMAP)                                 \
+	 << BIT_SHIFT_WMAC_CSI_RRSC_BITMAP)
+#define BITS_WMAC_CSI_RRSC_BITMAP                                              \
+	(BIT_MASK_WMAC_CSI_RRSC_BITMAP << BIT_SHIFT_WMAC_CSI_RRSC_BITMAP)
+#define BIT_CLEAR_WMAC_CSI_RRSC_BITMAP(x) ((x) & (~BITS_WMAC_CSI_RRSC_BITMAP))
+#define BIT_GET_WMAC_CSI_RRSC_BITMAP(x)                                        \
+	(((x) >> BIT_SHIFT_WMAC_CSI_RRSC_BITMAP) &                             \
+	 BIT_MASK_WMAC_CSI_RRSC_BITMAP)
+#define BIT_SET_WMAC_CSI_RRSC_BITMAP(x, v)                                     \
+	(BIT_CLEAR_WMAC_CSI_RRSC_BITMAP(x) | BIT_WMAC_CSI_RRSC_BITMAP(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8881A_SUPPORT)
+
+/* 2 REG_TX_CSI_RPT_PARAM_BW80		(Offset 0x06FC) */
+
+#define BIT_SHIFT_R_WMAC_BFINFO_80M_0 0
+#define BIT_MASK_R_WMAC_BFINFO_80M_0 0xfff
+#define BIT_R_WMAC_BFINFO_80M_0(x)                                             \
+	(((x) & BIT_MASK_R_WMAC_BFINFO_80M_0) << BIT_SHIFT_R_WMAC_BFINFO_80M_0)
+#define BITS_R_WMAC_BFINFO_80M_0                                               \
+	(BIT_MASK_R_WMAC_BFINFO_80M_0 << BIT_SHIFT_R_WMAC_BFINFO_80M_0)
+#define BIT_CLEAR_R_WMAC_BFINFO_80M_0(x) ((x) & (~BITS_R_WMAC_BFINFO_80M_0))
+#define BIT_GET_R_WMAC_BFINFO_80M_0(x)                                         \
+	(((x) >> BIT_SHIFT_R_WMAC_BFINFO_80M_0) & BIT_MASK_R_WMAC_BFINFO_80M_0)
+#define BIT_SET_R_WMAC_BFINFO_80M_0(x, v)                                      \
+	(BIT_CLEAR_R_WMAC_BFINFO_80M_0(x) | BIT_R_WMAC_BFINFO_80M_0(v))
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+/* 2 REG_CSI_RRSR_V1				(Offset 0x06FC) */
+
+#define BIT_SHIFT_WMAC_CSI_OFDM_LEN_TH 0
+#define BIT_MASK_WMAC_CSI_OFDM_LEN_TH 0xf
+#define BIT_WMAC_CSI_OFDM_LEN_TH(x)                                            \
+	(((x) & BIT_MASK_WMAC_CSI_OFDM_LEN_TH)                                 \
+	 << BIT_SHIFT_WMAC_CSI_OFDM_LEN_TH)
+#define BITS_WMAC_CSI_OFDM_LEN_TH                                              \
+	(BIT_MASK_WMAC_CSI_OFDM_LEN_TH << BIT_SHIFT_WMAC_CSI_OFDM_LEN_TH)
+#define BIT_CLEAR_WMAC_CSI_OFDM_LEN_TH(x) ((x) & (~BITS_WMAC_CSI_OFDM_LEN_TH))
+#define BIT_GET_WMAC_CSI_OFDM_LEN_TH(x)                                        \
+	(((x) >> BIT_SHIFT_WMAC_CSI_OFDM_LEN_TH) &                             \
+	 BIT_MASK_WMAC_CSI_OFDM_LEN_TH)
+#define BIT_SET_WMAC_CSI_OFDM_LEN_TH(x, v)                                     \
+	(BIT_CLEAR_WMAC_CSI_OFDM_LEN_TH(x) | BIT_WMAC_CSI_OFDM_LEN_TH(v))
+
+#define BIT_SHIFT_CSI_PARA_RDY_DLYCNT 0
+#define BIT_MASK_CSI_PARA_RDY_DLYCNT 0x1f
+#define BIT_CSI_PARA_RDY_DLYCNT(x)                                             \
+	(((x) & BIT_MASK_CSI_PARA_RDY_DLYCNT) << BIT_SHIFT_CSI_PARA_RDY_DLYCNT)
+#define BITS_CSI_PARA_RDY_DLYCNT                                               \
+	(BIT_MASK_CSI_PARA_RDY_DLYCNT << BIT_SHIFT_CSI_PARA_RDY_DLYCNT)
+#define BIT_CLEAR_CSI_PARA_RDY_DLYCNT(x) ((x) & (~BITS_CSI_PARA_RDY_DLYCNT))
+#define BIT_GET_CSI_PARA_RDY_DLYCNT(x)                                         \
+	(((x) >> BIT_SHIFT_CSI_PARA_RDY_DLYCNT) & BIT_MASK_CSI_PARA_RDY_DLYCNT)
+#define BIT_SET_CSI_PARA_RDY_DLYCNT(x, v)                                      \
+	(BIT_CLEAR_CSI_PARA_RDY_DLYCNT(x) | BIT_CSI_PARA_RDY_DLYCNT(v))
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_CSI_PTR				(Offset 0x06FC) */
+
+#define BIT_SHIFT_CSI_WADDR_LATCH_V2 0
+#define BIT_MASK_CSI_WADDR_LATCH_V2 0xffff
+#define BIT_CSI_WADDR_LATCH_V2(x)                                              \
+	(((x) & BIT_MASK_CSI_WADDR_LATCH_V2) << BIT_SHIFT_CSI_WADDR_LATCH_V2)
+#define BITS_CSI_WADDR_LATCH_V2                                                \
+	(BIT_MASK_CSI_WADDR_LATCH_V2 << BIT_SHIFT_CSI_WADDR_LATCH_V2)
+#define BIT_CLEAR_CSI_WADDR_LATCH_V2(x) ((x) & (~BITS_CSI_WADDR_LATCH_V2))
+#define BIT_GET_CSI_WADDR_LATCH_V2(x)                                          \
+	(((x) >> BIT_SHIFT_CSI_WADDR_LATCH_V2) & BIT_MASK_CSI_WADDR_LATCH_V2)
+#define BIT_SET_CSI_WADDR_LATCH_V2(x, v)                                       \
+	(BIT_CLEAR_CSI_WADDR_LATCH_V2(x) | BIT_CSI_WADDR_LATCH_V2(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT || \
+     HALMAC_8881A_SUPPORT)
+
+/* 2 REG_MACID1				(Offset 0x0700) */
+
+#define BIT_SHIFT_MACID1 0
+#define BIT_MASK_MACID1 0xffffffffffffL
+#define BIT_MACID1(x) (((x) & BIT_MASK_MACID1) << BIT_SHIFT_MACID1)
+#define BITS_MACID1 (BIT_MASK_MACID1 << BIT_SHIFT_MACID1)
+#define BIT_CLEAR_MACID1(x) ((x) & (~BITS_MACID1))
+#define BIT_GET_MACID1(x) (((x) >> BIT_SHIFT_MACID1) & BIT_MASK_MACID1)
+#define BIT_SET_MACID1(x, v) (BIT_CLEAR_MACID1(x) | BIT_MACID1(v))
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_MACID1				(Offset 0x0700) */
+
+#define BIT_SHIFT_MACID1_0 0
+#define BIT_MASK_MACID1_0 0xffffffffL
+#define BIT_MACID1_0(x) (((x) & BIT_MASK_MACID1_0) << BIT_SHIFT_MACID1_0)
+#define BITS_MACID1_0 (BIT_MASK_MACID1_0 << BIT_SHIFT_MACID1_0)
+#define BIT_CLEAR_MACID1_0(x) ((x) & (~BITS_MACID1_0))
+#define BIT_GET_MACID1_0(x) (((x) >> BIT_SHIFT_MACID1_0) & BIT_MASK_MACID1_0)
+#define BIT_SET_MACID1_0(x, v) (BIT_CLEAR_MACID1_0(x) | BIT_MACID1_0(v))
+
+/* 2 REG_MACID1_1				(Offset 0x0704) */
+
+#define BIT_SHIFT_MACID1_1 0
+#define BIT_MASK_MACID1_1 0xffff
+#define BIT_MACID1_1(x) (((x) & BIT_MASK_MACID1_1) << BIT_SHIFT_MACID1_1)
+#define BITS_MACID1_1 (BIT_MASK_MACID1_1 << BIT_SHIFT_MACID1_1)
+#define BIT_CLEAR_MACID1_1(x) ((x) & (~BITS_MACID1_1))
+#define BIT_GET_MACID1_1(x) (((x) >> BIT_SHIFT_MACID1_1) & BIT_MASK_MACID1_1)
+#define BIT_SET_MACID1_1(x, v) (BIT_CLEAR_MACID1_1(x) | BIT_MACID1_1(v))
+
+/* 2 REG_BSSID1				(Offset 0x0708) */
+
+#define BIT_SHIFT_BSSID1_0 0
+#define BIT_MASK_BSSID1_0 0xffffffffL
+#define BIT_BSSID1_0(x) (((x) & BIT_MASK_BSSID1_0) << BIT_SHIFT_BSSID1_0)
+#define BITS_BSSID1_0 (BIT_MASK_BSSID1_0 << BIT_SHIFT_BSSID1_0)
+#define BIT_CLEAR_BSSID1_0(x) ((x) & (~BITS_BSSID1_0))
+#define BIT_GET_BSSID1_0(x) (((x) >> BIT_SHIFT_BSSID1_0) & BIT_MASK_BSSID1_0)
+#define BIT_SET_BSSID1_0(x, v) (BIT_CLEAR_BSSID1_0(x) | BIT_BSSID1_0(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT)
+
+/* 2 REG_BSSID1				(Offset 0x0708) */
+
+#define BIT_SHIFT_BSSID1 0
+#define BIT_MASK_BSSID1 0xffffffffffffL
+#define BIT_BSSID1(x) (((x) & BIT_MASK_BSSID1) << BIT_SHIFT_BSSID1)
+#define BITS_BSSID1 (BIT_MASK_BSSID1 << BIT_SHIFT_BSSID1)
+#define BIT_CLEAR_BSSID1(x) ((x) & (~BITS_BSSID1))
+#define BIT_GET_BSSID1(x) (((x) >> BIT_SHIFT_BSSID1) & BIT_MASK_BSSID1)
+#define BIT_SET_BSSID1(x, v) (BIT_CLEAR_BSSID1(x) | BIT_BSSID1(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_PCIE_CFG_FORCE_LINK_L		(Offset 0x0709) */
+
+#define BIT_PCIE_CFG_FORCE_EN BIT(7)
+
+/* 2 REG_PCIE_CFG_FORCE_LINK_H		(Offset 0x070A) */
+
+#define BIT_PCIE_CFG_TRXACT_DIS_IDLE_TIMER BIT(6)
+
+#define BIT_SHIFT_PCIE_CFG_LINK_STATE 0
+#define BIT_MASK_PCIE_CFG_LINK_STATE 0x3f
+#define BIT_PCIE_CFG_LINK_STATE(x)                                             \
+	(((x) & BIT_MASK_PCIE_CFG_LINK_STATE) << BIT_SHIFT_PCIE_CFG_LINK_STATE)
+#define BITS_PCIE_CFG_LINK_STATE                                               \
+	(BIT_MASK_PCIE_CFG_LINK_STATE << BIT_SHIFT_PCIE_CFG_LINK_STATE)
+#define BIT_CLEAR_PCIE_CFG_LINK_STATE(x) ((x) & (~BITS_PCIE_CFG_LINK_STATE))
+#define BIT_GET_PCIE_CFG_LINK_STATE(x)                                         \
+	(((x) >> BIT_SHIFT_PCIE_CFG_LINK_STATE) & BIT_MASK_PCIE_CFG_LINK_STATE)
+#define BIT_SET_PCIE_CFG_LINK_STATE(x, v)                                      \
+	(BIT_CLEAR_PCIE_CFG_LINK_STATE(x) | BIT_PCIE_CFG_LINK_STATE(v))
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_BSSID1_1				(Offset 0x070C) */
+
+#define BIT_SHIFT_BSSID1_1 0
+#define BIT_MASK_BSSID1_1 0xffff
+#define BIT_BSSID1_1(x) (((x) & BIT_MASK_BSSID1_1) << BIT_SHIFT_BSSID1_1)
+#define BITS_BSSID1_1 (BIT_MASK_BSSID1_1 << BIT_SHIFT_BSSID1_1)
+#define BIT_CLEAR_BSSID1_1(x) ((x) & (~BITS_BSSID1_1))
+#define BIT_GET_BSSID1_1(x) (((x) >> BIT_SHIFT_BSSID1_1) & BIT_MASK_BSSID1_1)
+#define BIT_SET_BSSID1_1(x, v) (BIT_CLEAR_BSSID1_1(x) | BIT_BSSID1_1(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_PCIE_CFG_DEFAULT_ACK_FREQUENCY	(Offset 0x070C) */
+
+#define BIT_SHIFT_PCIE_CFG_DEFAULT_ACK_FREQUENCY 0
+#define BIT_MASK_PCIE_CFG_DEFAULT_ACK_FREQUENCY 0xff
+#define BIT_PCIE_CFG_DEFAULT_ACK_FREQUENCY(x)                                  \
+	(((x) & BIT_MASK_PCIE_CFG_DEFAULT_ACK_FREQUENCY)                       \
+	 << BIT_SHIFT_PCIE_CFG_DEFAULT_ACK_FREQUENCY)
+#define BITS_PCIE_CFG_DEFAULT_ACK_FREQUENCY                                    \
+	(BIT_MASK_PCIE_CFG_DEFAULT_ACK_FREQUENCY                               \
+	 << BIT_SHIFT_PCIE_CFG_DEFAULT_ACK_FREQUENCY)
+#define BIT_CLEAR_PCIE_CFG_DEFAULT_ACK_FREQUENCY(x)                            \
+	((x) & (~BITS_PCIE_CFG_DEFAULT_ACK_FREQUENCY))
+#define BIT_GET_PCIE_CFG_DEFAULT_ACK_FREQUENCY(x)                              \
+	(((x) >> BIT_SHIFT_PCIE_CFG_DEFAULT_ACK_FREQUENCY) &                   \
+	 BIT_MASK_PCIE_CFG_DEFAULT_ACK_FREQUENCY)
+#define BIT_SET_PCIE_CFG_DEFAULT_ACK_FREQUENCY(x, v)                           \
+	(BIT_CLEAR_PCIE_CFG_DEFAULT_ACK_FREQUENCY(x) |                         \
+	 BIT_PCIE_CFG_DEFAULT_ACK_FREQUENCY(v))
+
+/* 2 REG_PCIE_CFG_CX_NFTS			(Offset 0x070D) */
+
+#define BIT_SHIFT_PCIE_CFG_CX_NFTS 0
+#define BIT_MASK_PCIE_CFG_CX_NFTS 0xff
+#define BIT_PCIE_CFG_CX_NFTS(x)                                                \
+	(((x) & BIT_MASK_PCIE_CFG_CX_NFTS) << BIT_SHIFT_PCIE_CFG_CX_NFTS)
+#define BITS_PCIE_CFG_CX_NFTS                                                  \
+	(BIT_MASK_PCIE_CFG_CX_NFTS << BIT_SHIFT_PCIE_CFG_CX_NFTS)
+#define BIT_CLEAR_PCIE_CFG_CX_NFTS(x) ((x) & (~BITS_PCIE_CFG_CX_NFTS))
+#define BIT_GET_PCIE_CFG_CX_NFTS(x)                                            \
+	(((x) >> BIT_SHIFT_PCIE_CFG_CX_NFTS) & BIT_MASK_PCIE_CFG_CX_NFTS)
+#define BIT_SET_PCIE_CFG_CX_NFTS(x, v)                                         \
+	(BIT_CLEAR_PCIE_CFG_CX_NFTS(x) | BIT_PCIE_CFG_CX_NFTS(v))
+
+/* 2 REG_PCIE_CFG_DEFAULT_ENTR_LATENCY	(Offset 0x070F) */
+
+#define BIT_PCIE_CFG_REAL_EN_L0S BIT(7)
+#define BIT_PCIE_CFG_ENTER_ASPM BIT(6)
+
+#define BIT_SHIFT_PCIE_CFG_DEFAULT_L1_ENTR_LATENCY 3
+#define BIT_MASK_PCIE_CFG_DEFAULT_L1_ENTR_LATENCY 0x7
+#define BIT_PCIE_CFG_DEFAULT_L1_ENTR_LATENCY(x)                                \
+	(((x) & BIT_MASK_PCIE_CFG_DEFAULT_L1_ENTR_LATENCY)                     \
+	 << BIT_SHIFT_PCIE_CFG_DEFAULT_L1_ENTR_LATENCY)
+#define BITS_PCIE_CFG_DEFAULT_L1_ENTR_LATENCY                                  \
+	(BIT_MASK_PCIE_CFG_DEFAULT_L1_ENTR_LATENCY                             \
+	 << BIT_SHIFT_PCIE_CFG_DEFAULT_L1_ENTR_LATENCY)
+#define BIT_CLEAR_PCIE_CFG_DEFAULT_L1_ENTR_LATENCY(x)                          \
+	((x) & (~BITS_PCIE_CFG_DEFAULT_L1_ENTR_LATENCY))
+#define BIT_GET_PCIE_CFG_DEFAULT_L1_ENTR_LATENCY(x)                            \
+	(((x) >> BIT_SHIFT_PCIE_CFG_DEFAULT_L1_ENTR_LATENCY) &                 \
+	 BIT_MASK_PCIE_CFG_DEFAULT_L1_ENTR_LATENCY)
+#define BIT_SET_PCIE_CFG_DEFAULT_L1_ENTR_LATENCY(x, v)                         \
+	(BIT_CLEAR_PCIE_CFG_DEFAULT_L1_ENTR_LATENCY(x) |                       \
+	 BIT_PCIE_CFG_DEFAULT_L1_ENTR_LATENCY(v))
+
+#define BIT_SHIFT_PCIE_CFG_DEFAULT_L0S_ENTR_LATENCY 0
+#define BIT_MASK_PCIE_CFG_DEFAULT_L0S_ENTR_LATENCY 0x7
+#define BIT_PCIE_CFG_DEFAULT_L0S_ENTR_LATENCY(x)                               \
+	(((x) & BIT_MASK_PCIE_CFG_DEFAULT_L0S_ENTR_LATENCY)                    \
+	 << BIT_SHIFT_PCIE_CFG_DEFAULT_L0S_ENTR_LATENCY)
+#define BITS_PCIE_CFG_DEFAULT_L0S_ENTR_LATENCY                                 \
+	(BIT_MASK_PCIE_CFG_DEFAULT_L0S_ENTR_LATENCY                            \
+	 << BIT_SHIFT_PCIE_CFG_DEFAULT_L0S_ENTR_LATENCY)
+#define BIT_CLEAR_PCIE_CFG_DEFAULT_L0S_ENTR_LATENCY(x)                         \
+	((x) & (~BITS_PCIE_CFG_DEFAULT_L0S_ENTR_LATENCY))
+#define BIT_GET_PCIE_CFG_DEFAULT_L0S_ENTR_LATENCY(x)                           \
+	(((x) >> BIT_SHIFT_PCIE_CFG_DEFAULT_L0S_ENTR_LATENCY) &                \
+	 BIT_MASK_PCIE_CFG_DEFAULT_L0S_ENTR_LATENCY)
+#define BIT_SET_PCIE_CFG_DEFAULT_L0S_ENTR_LATENCY(x, v)                        \
+	(BIT_CLEAR_PCIE_CFG_DEFAULT_L0S_ENTR_LATENCY(x) |                      \
+	 BIT_PCIE_CFG_DEFAULT_L0S_ENTR_LATENCY(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_BCN_PSR_RPT1			(Offset 0x0710) */
+
+#define BIT_SHIFT_DTIM_CNT1 24
+#define BIT_MASK_DTIM_CNT1 0xff
+#define BIT_DTIM_CNT1(x) (((x) & BIT_MASK_DTIM_CNT1) << BIT_SHIFT_DTIM_CNT1)
+#define BITS_DTIM_CNT1 (BIT_MASK_DTIM_CNT1 << BIT_SHIFT_DTIM_CNT1)
+#define BIT_CLEAR_DTIM_CNT1(x) ((x) & (~BITS_DTIM_CNT1))
+#define BIT_GET_DTIM_CNT1(x) (((x) >> BIT_SHIFT_DTIM_CNT1) & BIT_MASK_DTIM_CNT1)
+#define BIT_SET_DTIM_CNT1(x, v) (BIT_CLEAR_DTIM_CNT1(x) | BIT_DTIM_CNT1(v))
+
+#define BIT_SHIFT_DTIM_PERIOD1 16
+#define BIT_MASK_DTIM_PERIOD1 0xff
+#define BIT_DTIM_PERIOD1(x)                                                    \
+	(((x) & BIT_MASK_DTIM_PERIOD1) << BIT_SHIFT_DTIM_PERIOD1)
+#define BITS_DTIM_PERIOD1 (BIT_MASK_DTIM_PERIOD1 << BIT_SHIFT_DTIM_PERIOD1)
+#define BIT_CLEAR_DTIM_PERIOD1(x) ((x) & (~BITS_DTIM_PERIOD1))
+#define BIT_GET_DTIM_PERIOD1(x)                                                \
+	(((x) >> BIT_SHIFT_DTIM_PERIOD1) & BIT_MASK_DTIM_PERIOD1)
+#define BIT_SET_DTIM_PERIOD1(x, v)                                             \
+	(BIT_CLEAR_DTIM_PERIOD1(x) | BIT_DTIM_PERIOD1(v))
+
+#define BIT_DTIM1 BIT(15)
+#define BIT_TIM1 BIT(14)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_BCN_PSR_RPT1			(Offset 0x0710) */
+
+#define BIT_BCN_VALID_V2 BIT(13)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_BCN_PSR_RPT1			(Offset 0x0710) */
+
+#define BIT_SHIFT_PS_AID_1 0
+#define BIT_MASK_PS_AID_1 0x7ff
+#define BIT_PS_AID_1(x) (((x) & BIT_MASK_PS_AID_1) << BIT_SHIFT_PS_AID_1)
+#define BITS_PS_AID_1 (BIT_MASK_PS_AID_1 << BIT_SHIFT_PS_AID_1)
+#define BIT_CLEAR_PS_AID_1(x) ((x) & (~BITS_PS_AID_1))
+#define BIT_GET_PS_AID_1(x) (((x) >> BIT_SHIFT_PS_AID_1) & BIT_MASK_PS_AID_1)
+#define BIT_SET_PS_AID_1(x, v) (BIT_CLEAR_PS_AID_1(x) | BIT_PS_AID_1(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_PCIE_CFG_L1_MISC_SEL		(Offset 0x0711) */
+
+#define BIT_PCIE_CFG_L1_RIDLE_SEL BIT(6)
+#define BIT_PCIE_CFG_L1_TIMEOUT_SEL BIT(5)
+#define BIT_PCIE_CFG_L1_EIDLE_SEL BIT(4)
+
+#define BIT_SHIFT_PCIE_CFG_DEFAULT_LINK_RATE 0
+#define BIT_MASK_PCIE_CFG_DEFAULT_LINK_RATE 0xf
+#define BIT_PCIE_CFG_DEFAULT_LINK_RATE(x)                                      \
+	(((x) & BIT_MASK_PCIE_CFG_DEFAULT_LINK_RATE)                           \
+	 << BIT_SHIFT_PCIE_CFG_DEFAULT_LINK_RATE)
+#define BITS_PCIE_CFG_DEFAULT_LINK_RATE                                        \
+	(BIT_MASK_PCIE_CFG_DEFAULT_LINK_RATE                                   \
+	 << BIT_SHIFT_PCIE_CFG_DEFAULT_LINK_RATE)
+#define BIT_CLEAR_PCIE_CFG_DEFAULT_LINK_RATE(x)                                \
+	((x) & (~BITS_PCIE_CFG_DEFAULT_LINK_RATE))
+#define BIT_GET_PCIE_CFG_DEFAULT_LINK_RATE(x)                                  \
+	(((x) >> BIT_SHIFT_PCIE_CFG_DEFAULT_LINK_RATE) &                       \
+	 BIT_MASK_PCIE_CFG_DEFAULT_LINK_RATE)
+#define BIT_SET_PCIE_CFG_DEFAULT_LINK_RATE(x, v)                               \
+	(BIT_CLEAR_PCIE_CFG_DEFAULT_LINK_RATE(x) |                             \
+	 BIT_PCIE_CFG_DEFAULT_LINK_RATE(v))
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_ASSOCIATED_BFMEE_SEL		(Offset 0x0714) */
+
+#define BIT_SHIFT_RD_BF_SEL 29
+#define BIT_MASK_RD_BF_SEL 0x7
+#define BIT_RD_BF_SEL(x) (((x) & BIT_MASK_RD_BF_SEL) << BIT_SHIFT_RD_BF_SEL)
+#define BITS_RD_BF_SEL (BIT_MASK_RD_BF_SEL << BIT_SHIFT_RD_BF_SEL)
+#define BIT_CLEAR_RD_BF_SEL(x) ((x) & (~BITS_RD_BF_SEL))
+#define BIT_GET_RD_BF_SEL(x) (((x) >> BIT_SHIFT_RD_BF_SEL) & BIT_MASK_RD_BF_SEL)
+#define BIT_SET_RD_BF_SEL(x, v) (BIT_CLEAR_RD_BF_SEL(x) | BIT_RD_BF_SEL(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_SND_PTCL_CTRL			(Offset 0x0718) */
+
+#define BIT_SHIFT_NDP_RX_STANDBY_TIMER 24
+#define BIT_MASK_NDP_RX_STANDBY_TIMER 0xff
+#define BIT_NDP_RX_STANDBY_TIMER(x)                                            \
+	(((x) & BIT_MASK_NDP_RX_STANDBY_TIMER)                                 \
+	 << BIT_SHIFT_NDP_RX_STANDBY_TIMER)
+#define BITS_NDP_RX_STANDBY_TIMER                                              \
+	(BIT_MASK_NDP_RX_STANDBY_TIMER << BIT_SHIFT_NDP_RX_STANDBY_TIMER)
+#define BIT_CLEAR_NDP_RX_STANDBY_TIMER(x) ((x) & (~BITS_NDP_RX_STANDBY_TIMER))
+#define BIT_GET_NDP_RX_STANDBY_TIMER(x)                                        \
+	(((x) >> BIT_SHIFT_NDP_RX_STANDBY_TIMER) &                             \
+	 BIT_MASK_NDP_RX_STANDBY_TIMER)
+#define BIT_SET_NDP_RX_STANDBY_TIMER(x, v)                                     \
+	(BIT_CLEAR_NDP_RX_STANDBY_TIMER(x) | BIT_NDP_RX_STANDBY_TIMER(v))
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+/* 2 REG_SND_PTCL_CTRL			(Offset 0x0718) */
+
+#define BIT_WMAC_CHK_RPTPOLL_A2_DIS BIT(23)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_SND_PTCL_CTRL			(Offset 0x0718) */
+
+#define BIT_R_WMAC_CHK_RPTPOLL_A2_DIS BIT(23)
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+/* 2 REG_SND_PTCL_CTRL			(Offset 0x0718) */
+
+#define BIT_WMAC_CHK_UCNDPA_A2_DIS BIT(22)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_SND_PTCL_CTRL			(Offset 0x0718) */
+
+#define BIT_R_WMAC_CHK_UCNDPA_A2_DIS BIT(22)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_SND_PTCL_CTRL			(Offset 0x0718) */
+
+#define BIT_ANTTRN_SWITCH BIT(19)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT)
+
+/* 2 REG_SND_PTCL_CTRL			(Offset 0x0718) */
+
+#define BIT_SHIFT_CSI_RPT_OFFSET_HT 16
+#define BIT_MASK_CSI_RPT_OFFSET_HT 0xff
+#define BIT_CSI_RPT_OFFSET_HT(x)                                               \
+	(((x) & BIT_MASK_CSI_RPT_OFFSET_HT) << BIT_SHIFT_CSI_RPT_OFFSET_HT)
+#define BITS_CSI_RPT_OFFSET_HT                                                 \
+	(BIT_MASK_CSI_RPT_OFFSET_HT << BIT_SHIFT_CSI_RPT_OFFSET_HT)
+#define BIT_CLEAR_CSI_RPT_OFFSET_HT(x) ((x) & (~BITS_CSI_RPT_OFFSET_HT))
+#define BIT_GET_CSI_RPT_OFFSET_HT(x)                                           \
+	(((x) >> BIT_SHIFT_CSI_RPT_OFFSET_HT) & BIT_MASK_CSI_RPT_OFFSET_HT)
+#define BIT_SET_CSI_RPT_OFFSET_HT(x, v)                                        \
+	(BIT_CLEAR_CSI_RPT_OFFSET_HT(x) | BIT_CSI_RPT_OFFSET_HT(v))
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_SND_PTCL_CTRL			(Offset 0x0718) */
+
+#define BIT_SHIFT_CSI_RPT_OFFSET_HT_V1 16
+#define BIT_MASK_CSI_RPT_OFFSET_HT_V1 0x3f
+#define BIT_CSI_RPT_OFFSET_HT_V1(x)                                            \
+	(((x) & BIT_MASK_CSI_RPT_OFFSET_HT_V1)                                 \
+	 << BIT_SHIFT_CSI_RPT_OFFSET_HT_V1)
+#define BITS_CSI_RPT_OFFSET_HT_V1                                              \
+	(BIT_MASK_CSI_RPT_OFFSET_HT_V1 << BIT_SHIFT_CSI_RPT_OFFSET_HT_V1)
+#define BIT_CLEAR_CSI_RPT_OFFSET_HT_V1(x) ((x) & (~BITS_CSI_RPT_OFFSET_HT_V1))
+#define BIT_GET_CSI_RPT_OFFSET_HT_V1(x)                                        \
+	(((x) >> BIT_SHIFT_CSI_RPT_OFFSET_HT_V1) &                             \
+	 BIT_MASK_CSI_RPT_OFFSET_HT_V1)
+#define BIT_SET_CSI_RPT_OFFSET_HT_V1(x, v)                                     \
+	(BIT_CLEAR_CSI_RPT_OFFSET_HT_V1(x) | BIT_CSI_RPT_OFFSET_HT_V1(v))
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+/* 2 REG_SND_PTCL_CTRL			(Offset 0x0718) */
+
+#define BIT_WMAC_OFFSET_RPTPOLL_EN BIT(15)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_SND_PTCL_CTRL			(Offset 0x0718) */
+
+#define BIT_R_WMAC_OFFSET_RPTPOLL_EN BIT(15)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT || HALMAC_8822B_SUPPORT)
+
+/* 2 REG_SND_PTCL_CTRL			(Offset 0x0718) */
+
+#define BIT_VHTNDP_RPTPOLL_CSI_STR_OFFSET_SEL BIT(15)
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+/* 2 REG_SND_PTCL_CTRL			(Offset 0x0718) */
+
+#define BIT_WMAC_CSI_CHKSUM_DIS BIT(14)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_SND_PTCL_CTRL			(Offset 0x0718) */
+
+#define BIT_R_WMAC_CSI_CHKSUM_DIS BIT(14)
+
+#endif
+
+#if (HALMAC_8822B_SUPPORT)
+
+/* 2 REG_SND_PTCL_CTRL			(Offset 0x0718) */
+
+#define BIT_NDPVLD_POS_RST_FFPTR_DIS BIT(14)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8821C_SUPPORT)
+
+/* 2 REG_SND_PTCL_CTRL			(Offset 0x0718) */
+
+#define BIT_SHIFT_R_WMAC_VHT_CATEGORY 8
+#define BIT_MASK_R_WMAC_VHT_CATEGORY 0xff
+#define BIT_R_WMAC_VHT_CATEGORY(x)                                             \
+	(((x) & BIT_MASK_R_WMAC_VHT_CATEGORY) << BIT_SHIFT_R_WMAC_VHT_CATEGORY)
+#define BITS_R_WMAC_VHT_CATEGORY                                               \
+	(BIT_MASK_R_WMAC_VHT_CATEGORY << BIT_SHIFT_R_WMAC_VHT_CATEGORY)
+#define BIT_CLEAR_R_WMAC_VHT_CATEGORY(x) ((x) & (~BITS_R_WMAC_VHT_CATEGORY))
+#define BIT_GET_R_WMAC_VHT_CATEGORY(x)                                         \
+	(((x) >> BIT_SHIFT_R_WMAC_VHT_CATEGORY) & BIT_MASK_R_WMAC_VHT_CATEGORY)
+#define BIT_SET_R_WMAC_VHT_CATEGORY(x, v)                                      \
+	(BIT_CLEAR_R_WMAC_VHT_CATEGORY(x) | BIT_R_WMAC_VHT_CATEGORY(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_SND_PTCL_CTRL			(Offset 0x0718) */
+
+#define BIT_SHIFT_CSI_RPT_OFFSET_VHT 8
+#define BIT_MASK_CSI_RPT_OFFSET_VHT 0xff
+#define BIT_CSI_RPT_OFFSET_VHT(x)                                              \
+	(((x) & BIT_MASK_CSI_RPT_OFFSET_VHT) << BIT_SHIFT_CSI_RPT_OFFSET_VHT)
+#define BITS_CSI_RPT_OFFSET_VHT                                                \
+	(BIT_MASK_CSI_RPT_OFFSET_VHT << BIT_SHIFT_CSI_RPT_OFFSET_VHT)
+#define BIT_CLEAR_CSI_RPT_OFFSET_VHT(x) ((x) & (~BITS_CSI_RPT_OFFSET_VHT))
+#define BIT_GET_CSI_RPT_OFFSET_VHT(x)                                          \
+	(((x) >> BIT_SHIFT_CSI_RPT_OFFSET_VHT) & BIT_MASK_CSI_RPT_OFFSET_VHT)
+#define BIT_SET_CSI_RPT_OFFSET_VHT(x, v)                                       \
+	(BIT_CLEAR_CSI_RPT_OFFSET_VHT(x) | BIT_CSI_RPT_OFFSET_VHT(v))
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+/* 2 REG_SND_PTCL_CTRL			(Offset 0x0718) */
+
+#define BIT_SHIFT_CSI_RPT_OFFSET_VHT_V1 8
+#define BIT_MASK_CSI_RPT_OFFSET_VHT_V1 0x3f
+#define BIT_CSI_RPT_OFFSET_VHT_V1(x)                                           \
+	(((x) & BIT_MASK_CSI_RPT_OFFSET_VHT_V1)                                \
+	 << BIT_SHIFT_CSI_RPT_OFFSET_VHT_V1)
+#define BITS_CSI_RPT_OFFSET_VHT_V1                                             \
+	(BIT_MASK_CSI_RPT_OFFSET_VHT_V1 << BIT_SHIFT_CSI_RPT_OFFSET_VHT_V1)
+#define BIT_CLEAR_CSI_RPT_OFFSET_VHT_V1(x) ((x) & (~BITS_CSI_RPT_OFFSET_VHT_V1))
+#define BIT_GET_CSI_RPT_OFFSET_VHT_V1(x)                                       \
+	(((x) >> BIT_SHIFT_CSI_RPT_OFFSET_VHT_V1) &                            \
+	 BIT_MASK_CSI_RPT_OFFSET_VHT_V1)
+#define BIT_SET_CSI_RPT_OFFSET_VHT_V1(x, v)                                    \
+	(BIT_CLEAR_CSI_RPT_OFFSET_VHT_V1(x) | BIT_CSI_RPT_OFFSET_VHT_V1(v))
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_SND_PTCL_CTRL			(Offset 0x0718) */
+
+#define BIT_SHIFT_R_WMAC_VHT_CATEGORY_V1 8
+#define BIT_MASK_R_WMAC_VHT_CATEGORY_V1 0x3f
+#define BIT_R_WMAC_VHT_CATEGORY_V1(x)                                          \
+	(((x) & BIT_MASK_R_WMAC_VHT_CATEGORY_V1)                               \
+	 << BIT_SHIFT_R_WMAC_VHT_CATEGORY_V1)
+#define BITS_R_WMAC_VHT_CATEGORY_V1                                            \
+	(BIT_MASK_R_WMAC_VHT_CATEGORY_V1 << BIT_SHIFT_R_WMAC_VHT_CATEGORY_V1)
+#define BIT_CLEAR_R_WMAC_VHT_CATEGORY_V1(x)                                    \
+	((x) & (~BITS_R_WMAC_VHT_CATEGORY_V1))
+#define BIT_GET_R_WMAC_VHT_CATEGORY_V1(x)                                      \
+	(((x) >> BIT_SHIFT_R_WMAC_VHT_CATEGORY_V1) &                           \
+	 BIT_MASK_R_WMAC_VHT_CATEGORY_V1)
+#define BIT_SET_R_WMAC_VHT_CATEGORY_V1(x, v)                                   \
+	(BIT_CLEAR_R_WMAC_VHT_CATEGORY_V1(x) | BIT_R_WMAC_VHT_CATEGORY_V1(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT || HALMAC_8822B_SUPPORT)
+
+/* 2 REG_SND_PTCL_CTRL			(Offset 0x0718) */
+
+#define BIT_SHIFT_R_CSI_RPT_OFFSET_VHT_V1 8
+#define BIT_MASK_R_CSI_RPT_OFFSET_VHT_V1 0x3f
+#define BIT_R_CSI_RPT_OFFSET_VHT_V1(x)                                         \
+	(((x) & BIT_MASK_R_CSI_RPT_OFFSET_VHT_V1)                              \
+	 << BIT_SHIFT_R_CSI_RPT_OFFSET_VHT_V1)
+#define BITS_R_CSI_RPT_OFFSET_VHT_V1                                           \
+	(BIT_MASK_R_CSI_RPT_OFFSET_VHT_V1 << BIT_SHIFT_R_CSI_RPT_OFFSET_VHT_V1)
+#define BIT_CLEAR_R_CSI_RPT_OFFSET_VHT_V1(x)                                   \
+	((x) & (~BITS_R_CSI_RPT_OFFSET_VHT_V1))
+#define BIT_GET_R_CSI_RPT_OFFSET_VHT_V1(x)                                     \
+	(((x) >> BIT_SHIFT_R_CSI_RPT_OFFSET_VHT_V1) &                          \
+	 BIT_MASK_R_CSI_RPT_OFFSET_VHT_V1)
+#define BIT_SET_R_CSI_RPT_OFFSET_VHT_V1(x, v)                                  \
+	(BIT_CLEAR_R_CSI_RPT_OFFSET_VHT_V1(x) | BIT_R_CSI_RPT_OFFSET_VHT_V1(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_SND_PTCL_CTRL			(Offset 0x0718) */
+
+#define BIT_R_WMAC_USE_NSTS BIT(7)
+#define BIT_R_DISABLE_CHECK_VHTSIGB_CRC BIT(6)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_PCIE_CFG_TIMER_CTRL_MAX_FUNC_NUM_OFF (Offset 0x0718) */
+
+#define BIT_PCIE_CFG_REAL_PTM_ENABLE BIT(6)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_SND_PTCL_CTRL			(Offset 0x0718) */
+
+#define BIT_R_DISABLE_CHECK_VHTSIGA_CRC BIT(5)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_PCIE_CFG_TIMER_CTRL_MAX_FUNC_NUM_OFF (Offset 0x0718) */
+
+#define BIT_PCIE_CFG_REAL_EN_L1SUB BIT(5)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_SND_PTCL_CTRL			(Offset 0x0718) */
+
+#define BIT_R_WMAC_BFPARAM_SEL BIT(4)
+#define BIT_R_WMAC_CSISEQ_SEL BIT(3)
+#define BIT_R_WMAC_CSI_WITHHTC_EN BIT(2)
+#define BIT_R_WMAC_HT_NDPA_EN BIT(1)
+#define BIT_R_WMAC_VHT_NDPA_EN BIT(0)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_PCIE_CFG_TIMER_CTRL_MAX_FUNC_NUM_OFF (Offset 0x0718) */
+
+#define BIT_SHIFT_PCIE_CFG_MAX_FUNC_NUM 0
+#define BIT_MASK_PCIE_CFG_MAX_FUNC_NUM 0x7
+#define BIT_PCIE_CFG_MAX_FUNC_NUM(x)                                           \
+	(((x) & BIT_MASK_PCIE_CFG_MAX_FUNC_NUM)                                \
+	 << BIT_SHIFT_PCIE_CFG_MAX_FUNC_NUM)
+#define BITS_PCIE_CFG_MAX_FUNC_NUM                                             \
+	(BIT_MASK_PCIE_CFG_MAX_FUNC_NUM << BIT_SHIFT_PCIE_CFG_MAX_FUNC_NUM)
+#define BIT_CLEAR_PCIE_CFG_MAX_FUNC_NUM(x) ((x) & (~BITS_PCIE_CFG_MAX_FUNC_NUM))
+#define BIT_GET_PCIE_CFG_MAX_FUNC_NUM(x)                                       \
+	(((x) >> BIT_SHIFT_PCIE_CFG_MAX_FUNC_NUM) &                            \
+	 BIT_MASK_PCIE_CFG_MAX_FUNC_NUM)
+#define BIT_SET_PCIE_CFG_MAX_FUNC_NUM(x, v)                                    \
+	(BIT_CLEAR_PCIE_CFG_MAX_FUNC_NUM(x) | BIT_PCIE_CFG_MAX_FUNC_NUM(v))
+
+/* 2 REG_PCIE_CFG_FORCE_CLKREQ_N_PAD		(Offset 0x0719) */
+
+#define BIT_PCIE_CFG_REAL_EN_64BITS BIT(5)
+#define BIT_PCIE_CFG_REAL_EN_CLKREQ BIT(4)
+#define BIT_PCIE_CFG_REAL_EN_L1 BIT(3)
+#define BIT_PCIE_CFG_WAKE_N_EN BIT(2)
+#define BIT_PCIE_CFG_BYPASS_LTR_OPTION BIT(1)
+#define BIT_PCIE_CFG_FORCE_CLKREQ_N_PAD BIT(0)
+
+/* 2 REG_PCIE_CFG_TIMER_MODIFIER_FOR_ACK_NAK_LATENCY (Offset 0x071A) */
+
+#define BIT_SHIFT_PCIE_CFG_TIMER_MOD_ACK_NAK 0
+#define BIT_MASK_PCIE_CFG_TIMER_MOD_ACK_NAK 0xff
+#define BIT_PCIE_CFG_TIMER_MOD_ACK_NAK(x)                                      \
+	(((x) & BIT_MASK_PCIE_CFG_TIMER_MOD_ACK_NAK)                           \
+	 << BIT_SHIFT_PCIE_CFG_TIMER_MOD_ACK_NAK)
+#define BITS_PCIE_CFG_TIMER_MOD_ACK_NAK                                        \
+	(BIT_MASK_PCIE_CFG_TIMER_MOD_ACK_NAK                                   \
+	 << BIT_SHIFT_PCIE_CFG_TIMER_MOD_ACK_NAK)
+#define BIT_CLEAR_PCIE_CFG_TIMER_MOD_ACK_NAK(x)                                \
+	((x) & (~BITS_PCIE_CFG_TIMER_MOD_ACK_NAK))
+#define BIT_GET_PCIE_CFG_TIMER_MOD_ACK_NAK(x)                                  \
+	(((x) >> BIT_SHIFT_PCIE_CFG_TIMER_MOD_ACK_NAK) &                       \
+	 BIT_MASK_PCIE_CFG_TIMER_MOD_ACK_NAK)
+#define BIT_SET_PCIE_CFG_TIMER_MOD_ACK_NAK(x, v)                               \
+	(BIT_CLEAR_PCIE_CFG_TIMER_MOD_ACK_NAK(x) |                             \
+	 BIT_PCIE_CFG_TIMER_MOD_ACK_NAK(v))
+
+/* 2 REG_PCIE_CFG_TIMER_MODIFIER_FOR_FLOW_CONTROL_WATCHDOG (Offset 0x071B) */
+
+#define BIT_PCIE_CFG_BYPASS_L1_SUBSTATE_OPTION BIT(7)
+
+#define BIT_SHIFT_PCIE_CFG_FAST_LINK_SCALING_FACTOR 5
+#define BIT_MASK_PCIE_CFG_FAST_LINK_SCALING_FACTOR 0x3
+#define BIT_PCIE_CFG_FAST_LINK_SCALING_FACTOR(x)                               \
+	(((x) & BIT_MASK_PCIE_CFG_FAST_LINK_SCALING_FACTOR)                    \
+	 << BIT_SHIFT_PCIE_CFG_FAST_LINK_SCALING_FACTOR)
+#define BITS_PCIE_CFG_FAST_LINK_SCALING_FACTOR                                 \
+	(BIT_MASK_PCIE_CFG_FAST_LINK_SCALING_FACTOR                            \
+	 << BIT_SHIFT_PCIE_CFG_FAST_LINK_SCALING_FACTOR)
+#define BIT_CLEAR_PCIE_CFG_FAST_LINK_SCALING_FACTOR(x)                         \
+	((x) & (~BITS_PCIE_CFG_FAST_LINK_SCALING_FACTOR))
+#define BIT_GET_PCIE_CFG_FAST_LINK_SCALING_FACTOR(x)                           \
+	(((x) >> BIT_SHIFT_PCIE_CFG_FAST_LINK_SCALING_FACTOR) &                \
+	 BIT_MASK_PCIE_CFG_FAST_LINK_SCALING_FACTOR)
+#define BIT_SET_PCIE_CFG_FAST_LINK_SCALING_FACTOR(x, v)                        \
+	(BIT_CLEAR_PCIE_CFG_FAST_LINK_SCALING_FACTOR(x) |                      \
+	 BIT_PCIE_CFG_FAST_LINK_SCALING_FACTOR(v))
+
+#define BIT_SHIFT_PCIE_CFG_UPDATE_FREQ_TIMER 0
+#define BIT_MASK_PCIE_CFG_UPDATE_FREQ_TIMER 0x1f
+#define BIT_PCIE_CFG_UPDATE_FREQ_TIMER(x)                                      \
+	(((x) & BIT_MASK_PCIE_CFG_UPDATE_FREQ_TIMER)                           \
+	 << BIT_SHIFT_PCIE_CFG_UPDATE_FREQ_TIMER)
+#define BITS_PCIE_CFG_UPDATE_FREQ_TIMER                                        \
+	(BIT_MASK_PCIE_CFG_UPDATE_FREQ_TIMER                                   \
+	 << BIT_SHIFT_PCIE_CFG_UPDATE_FREQ_TIMER)
+#define BIT_CLEAR_PCIE_CFG_UPDATE_FREQ_TIMER(x)                                \
+	((x) & (~BITS_PCIE_CFG_UPDATE_FREQ_TIMER))
+#define BIT_GET_PCIE_CFG_UPDATE_FREQ_TIMER(x)                                  \
+	(((x) >> BIT_SHIFT_PCIE_CFG_UPDATE_FREQ_TIMER) &                       \
+	 BIT_MASK_PCIE_CFG_UPDATE_FREQ_TIMER)
+#define BIT_SET_PCIE_CFG_UPDATE_FREQ_TIMER(x, v)                               \
+	(BIT_CLEAR_PCIE_CFG_UPDATE_FREQ_TIMER(x) |                             \
+	 BIT_PCIE_CFG_UPDATE_FREQ_TIMER(v))
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_RX_CSI_RPT_INFO			(Offset 0x071C) */
+
+#define BIT_WMAC_CHECK_SOUNDING_SEQ BIT(30)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_PCIE_CFG_SKP_INTERVAL_VALUE_L	(Offset 0x071C) */
+
+#define BIT_SHIFT_PCIE_CFG_SKP_INTERVAL_VALUE_L 0
+#define BIT_MASK_PCIE_CFG_SKP_INTERVAL_VALUE_L 0xff
+#define BIT_PCIE_CFG_SKP_INTERVAL_VALUE_L(x)                                   \
+	(((x) & BIT_MASK_PCIE_CFG_SKP_INTERVAL_VALUE_L)                        \
+	 << BIT_SHIFT_PCIE_CFG_SKP_INTERVAL_VALUE_L)
+#define BITS_PCIE_CFG_SKP_INTERVAL_VALUE_L                                     \
+	(BIT_MASK_PCIE_CFG_SKP_INTERVAL_VALUE_L                                \
+	 << BIT_SHIFT_PCIE_CFG_SKP_INTERVAL_VALUE_L)
+#define BIT_CLEAR_PCIE_CFG_SKP_INTERVAL_VALUE_L(x)                             \
+	((x) & (~BITS_PCIE_CFG_SKP_INTERVAL_VALUE_L))
+#define BIT_GET_PCIE_CFG_SKP_INTERVAL_VALUE_L(x)                               \
+	(((x) >> BIT_SHIFT_PCIE_CFG_SKP_INTERVAL_VALUE_L) &                    \
+	 BIT_MASK_PCIE_CFG_SKP_INTERVAL_VALUE_L)
+#define BIT_SET_PCIE_CFG_SKP_INTERVAL_VALUE_L(x, v)                            \
+	(BIT_CLEAR_PCIE_CFG_SKP_INTERVAL_VALUE_L(x) |                          \
+	 BIT_PCIE_CFG_SKP_INTERVAL_VALUE_L(v))
+
+/* 2 REG_PCIE_CFG_SKP_INTERVAL_VALUE_H	(Offset 0x071D) */
+
+#define BIT_PCIE_CFG_DISABLE_FC_WATCHDOG_TIMER BIT(7)
+
+#define BIT_SHIFT_PCIE_CFG_SKP_INTERVAL_VALUE_H 0
+#define BIT_MASK_PCIE_CFG_SKP_INTERVAL_VALUE_H 0x7
+#define BIT_PCIE_CFG_SKP_INTERVAL_VALUE_H(x)                                   \
+	(((x) & BIT_MASK_PCIE_CFG_SKP_INTERVAL_VALUE_H)                        \
+	 << BIT_SHIFT_PCIE_CFG_SKP_INTERVAL_VALUE_H)
+#define BITS_PCIE_CFG_SKP_INTERVAL_VALUE_H                                     \
+	(BIT_MASK_PCIE_CFG_SKP_INTERVAL_VALUE_H                                \
+	 << BIT_SHIFT_PCIE_CFG_SKP_INTERVAL_VALUE_H)
+#define BIT_CLEAR_PCIE_CFG_SKP_INTERVAL_VALUE_H(x)                             \
+	((x) & (~BITS_PCIE_CFG_SKP_INTERVAL_VALUE_H))
+#define BIT_GET_PCIE_CFG_SKP_INTERVAL_VALUE_H(x)                               \
+	(((x) >> BIT_SHIFT_PCIE_CFG_SKP_INTERVAL_VALUE_H) &                    \
+	 BIT_MASK_PCIE_CFG_SKP_INTERVAL_VALUE_H)
+#define BIT_SET_PCIE_CFG_SKP_INTERVAL_VALUE_H(x, v)                            \
+	(BIT_CLEAR_PCIE_CFG_SKP_INTERVAL_VALUE_H(x) |                          \
+	 BIT_PCIE_CFG_SKP_INTERVAL_VALUE_H(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_NS_ARP_CTRL				(Offset 0x0720) */
+
+#define BIT_R_WMAC_NSARP_RSPEN BIT(15)
+#define BIT_R_WMAC_NSARP_RARP BIT(9)
+#define BIT_R_WMAC_NSARP_RIPV6 BIT(8)
+
+#define BIT_SHIFT_R_WMAC_NSARP_MODEN 6
+#define BIT_MASK_R_WMAC_NSARP_MODEN 0x3
+#define BIT_R_WMAC_NSARP_MODEN(x)                                              \
+	(((x) & BIT_MASK_R_WMAC_NSARP_MODEN) << BIT_SHIFT_R_WMAC_NSARP_MODEN)
+#define BITS_R_WMAC_NSARP_MODEN                                                \
+	(BIT_MASK_R_WMAC_NSARP_MODEN << BIT_SHIFT_R_WMAC_NSARP_MODEN)
+#define BIT_CLEAR_R_WMAC_NSARP_MODEN(x) ((x) & (~BITS_R_WMAC_NSARP_MODEN))
+#define BIT_GET_R_WMAC_NSARP_MODEN(x)                                          \
+	(((x) >> BIT_SHIFT_R_WMAC_NSARP_MODEN) & BIT_MASK_R_WMAC_NSARP_MODEN)
+#define BIT_SET_R_WMAC_NSARP_MODEN(x, v)                                       \
+	(BIT_CLEAR_R_WMAC_NSARP_MODEN(x) | BIT_R_WMAC_NSARP_MODEN(v))
+
+#define BIT_SHIFT_R_WMAC_NSARP_RSPFTP 4
+#define BIT_MASK_R_WMAC_NSARP_RSPFTP 0x3
+#define BIT_R_WMAC_NSARP_RSPFTP(x)                                             \
+	(((x) & BIT_MASK_R_WMAC_NSARP_RSPFTP) << BIT_SHIFT_R_WMAC_NSARP_RSPFTP)
+#define BITS_R_WMAC_NSARP_RSPFTP                                               \
+	(BIT_MASK_R_WMAC_NSARP_RSPFTP << BIT_SHIFT_R_WMAC_NSARP_RSPFTP)
+#define BIT_CLEAR_R_WMAC_NSARP_RSPFTP(x) ((x) & (~BITS_R_WMAC_NSARP_RSPFTP))
+#define BIT_GET_R_WMAC_NSARP_RSPFTP(x)                                         \
+	(((x) >> BIT_SHIFT_R_WMAC_NSARP_RSPFTP) & BIT_MASK_R_WMAC_NSARP_RSPFTP)
+#define BIT_SET_R_WMAC_NSARP_RSPFTP(x, v)                                      \
+	(BIT_CLEAR_R_WMAC_NSARP_RSPFTP(x) | BIT_R_WMAC_NSARP_RSPFTP(v))
+
+#define BIT_SHIFT_R_WMAC_NSARP_RSPSEC 0
+#define BIT_MASK_R_WMAC_NSARP_RSPSEC 0xf
+#define BIT_R_WMAC_NSARP_RSPSEC(x)                                             \
+	(((x) & BIT_MASK_R_WMAC_NSARP_RSPSEC) << BIT_SHIFT_R_WMAC_NSARP_RSPSEC)
+#define BITS_R_WMAC_NSARP_RSPSEC                                               \
+	(BIT_MASK_R_WMAC_NSARP_RSPSEC << BIT_SHIFT_R_WMAC_NSARP_RSPSEC)
+#define BIT_CLEAR_R_WMAC_NSARP_RSPSEC(x) ((x) & (~BITS_R_WMAC_NSARP_RSPSEC))
+#define BIT_GET_R_WMAC_NSARP_RSPSEC(x)                                         \
+	(((x) >> BIT_SHIFT_R_WMAC_NSARP_RSPSEC) & BIT_MASK_R_WMAC_NSARP_RSPSEC)
+#define BIT_SET_R_WMAC_NSARP_RSPSEC(x, v)                                      \
+	(BIT_CLEAR_R_WMAC_NSARP_RSPSEC(x) | BIT_R_WMAC_NSARP_RSPSEC(v))
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_NS_ARP_INFO				(Offset 0x0724) */
+
+#define BIT_REQ_IS_MCNS BIT(23)
+#define BIT_REQ_IS_UCNS BIT(22)
+#define BIT_REQ_IS_USNS BIT(21)
+#define BIT_REQ_IS_ARP BIT(20)
+#define BIT_EXPRSP_MH_WITHQC BIT(19)
+
+#define BIT_SHIFT_EXPRSP_SECTYPE 16
+#define BIT_MASK_EXPRSP_SECTYPE 0x7
+#define BIT_EXPRSP_SECTYPE(x)                                                  \
+	(((x) & BIT_MASK_EXPRSP_SECTYPE) << BIT_SHIFT_EXPRSP_SECTYPE)
+#define BITS_EXPRSP_SECTYPE                                                    \
+	(BIT_MASK_EXPRSP_SECTYPE << BIT_SHIFT_EXPRSP_SECTYPE)
+#define BIT_CLEAR_EXPRSP_SECTYPE(x) ((x) & (~BITS_EXPRSP_SECTYPE))
+#define BIT_GET_EXPRSP_SECTYPE(x)                                              \
+	(((x) >> BIT_SHIFT_EXPRSP_SECTYPE) & BIT_MASK_EXPRSP_SECTYPE)
+#define BIT_SET_EXPRSP_SECTYPE(x, v)                                           \
+	(BIT_CLEAR_EXPRSP_SECTYPE(x) | BIT_EXPRSP_SECTYPE(v))
+
+#define BIT_SHIFT_EXPRSP_CHKSM_7_TO_0 8
+#define BIT_MASK_EXPRSP_CHKSM_7_TO_0 0xff
+#define BIT_EXPRSP_CHKSM_7_TO_0(x)                                             \
+	(((x) & BIT_MASK_EXPRSP_CHKSM_7_TO_0) << BIT_SHIFT_EXPRSP_CHKSM_7_TO_0)
+#define BITS_EXPRSP_CHKSM_7_TO_0                                               \
+	(BIT_MASK_EXPRSP_CHKSM_7_TO_0 << BIT_SHIFT_EXPRSP_CHKSM_7_TO_0)
+#define BIT_CLEAR_EXPRSP_CHKSM_7_TO_0(x) ((x) & (~BITS_EXPRSP_CHKSM_7_TO_0))
+#define BIT_GET_EXPRSP_CHKSM_7_TO_0(x)                                         \
+	(((x) >> BIT_SHIFT_EXPRSP_CHKSM_7_TO_0) & BIT_MASK_EXPRSP_CHKSM_7_TO_0)
+#define BIT_SET_EXPRSP_CHKSM_7_TO_0(x, v)                                      \
+	(BIT_CLEAR_EXPRSP_CHKSM_7_TO_0(x) | BIT_EXPRSP_CHKSM_7_TO_0(v))
+
+#define BIT_SHIFT_EXPRSP_CHKSM_15_TO_8 0
+#define BIT_MASK_EXPRSP_CHKSM_15_TO_8 0xff
+#define BIT_EXPRSP_CHKSM_15_TO_8(x)                                            \
+	(((x) & BIT_MASK_EXPRSP_CHKSM_15_TO_8)                                 \
+	 << BIT_SHIFT_EXPRSP_CHKSM_15_TO_8)
+#define BITS_EXPRSP_CHKSM_15_TO_8                                              \
+	(BIT_MASK_EXPRSP_CHKSM_15_TO_8 << BIT_SHIFT_EXPRSP_CHKSM_15_TO_8)
+#define BIT_CLEAR_EXPRSP_CHKSM_15_TO_8(x) ((x) & (~BITS_EXPRSP_CHKSM_15_TO_8))
+#define BIT_GET_EXPRSP_CHKSM_15_TO_8(x)                                        \
+	(((x) >> BIT_SHIFT_EXPRSP_CHKSM_15_TO_8) &                             \
+	 BIT_MASK_EXPRSP_CHKSM_15_TO_8)
+#define BIT_SET_EXPRSP_CHKSM_15_TO_8(x, v)                                     \
+	(BIT_CLEAR_EXPRSP_CHKSM_15_TO_8(x) | BIT_EXPRSP_CHKSM_15_TO_8(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_PCIE_CFG_L1_UNIT_SEL		(Offset 0x0724) */
+
+#define BIT_SHIFT_PCIE_CFG_L1_UNIT_SEL 0
+#define BIT_MASK_PCIE_CFG_L1_UNIT_SEL 0xff
+#define BIT_PCIE_CFG_L1_UNIT_SEL(x)                                            \
+	(((x) & BIT_MASK_PCIE_CFG_L1_UNIT_SEL)                                 \
+	 << BIT_SHIFT_PCIE_CFG_L1_UNIT_SEL)
+#define BITS_PCIE_CFG_L1_UNIT_SEL                                              \
+	(BIT_MASK_PCIE_CFG_L1_UNIT_SEL << BIT_SHIFT_PCIE_CFG_L1_UNIT_SEL)
+#define BIT_CLEAR_PCIE_CFG_L1_UNIT_SEL(x) ((x) & (~BITS_PCIE_CFG_L1_UNIT_SEL))
+#define BIT_GET_PCIE_CFG_L1_UNIT_SEL(x)                                        \
+	(((x) >> BIT_SHIFT_PCIE_CFG_L1_UNIT_SEL) &                             \
+	 BIT_MASK_PCIE_CFG_L1_UNIT_SEL)
+#define BIT_SET_PCIE_CFG_L1_UNIT_SEL(x, v)                                     \
+	(BIT_CLEAR_PCIE_CFG_L1_UNIT_SEL(x) | BIT_PCIE_CFG_L1_UNIT_SEL(v))
+
+/* 2 REG_PCIE_CFG_MIN_CLKREQ_SEL		(Offset 0x0725) */
+
+#define BIT_SHIFT_PCIE_CFG_MIN_CLKREQ_SEL 0
+#define BIT_MASK_PCIE_CFG_MIN_CLKREQ_SEL 0xf
+#define BIT_PCIE_CFG_MIN_CLKREQ_SEL(x)                                         \
+	(((x) & BIT_MASK_PCIE_CFG_MIN_CLKREQ_SEL)                              \
+	 << BIT_SHIFT_PCIE_CFG_MIN_CLKREQ_SEL)
+#define BITS_PCIE_CFG_MIN_CLKREQ_SEL                                           \
+	(BIT_MASK_PCIE_CFG_MIN_CLKREQ_SEL << BIT_SHIFT_PCIE_CFG_MIN_CLKREQ_SEL)
+#define BIT_CLEAR_PCIE_CFG_MIN_CLKREQ_SEL(x)                                   \
+	((x) & (~BITS_PCIE_CFG_MIN_CLKREQ_SEL))
+#define BIT_GET_PCIE_CFG_MIN_CLKREQ_SEL(x)                                     \
+	(((x) >> BIT_SHIFT_PCIE_CFG_MIN_CLKREQ_SEL) &                          \
+	 BIT_MASK_PCIE_CFG_MIN_CLKREQ_SEL)
+#define BIT_SET_PCIE_CFG_MIN_CLKREQ_SEL(x, v)                                  \
+	(BIT_CLEAR_PCIE_CFG_MIN_CLKREQ_SEL(x) | BIT_PCIE_CFG_MIN_CLKREQ_SEL(v))
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_BEAMFORMING_INFO_NSARP_V1		(Offset 0x0728) */
+
+#define BIT_SHIFT_WMAC_ARPIP 0
+#define BIT_MASK_WMAC_ARPIP 0xffffffffL
+#define BIT_WMAC_ARPIP(x) (((x) & BIT_MASK_WMAC_ARPIP) << BIT_SHIFT_WMAC_ARPIP)
+#define BITS_WMAC_ARPIP (BIT_MASK_WMAC_ARPIP << BIT_SHIFT_WMAC_ARPIP)
+#define BIT_CLEAR_WMAC_ARPIP(x) ((x) & (~BITS_WMAC_ARPIP))
+#define BIT_GET_WMAC_ARPIP(x)                                                  \
+	(((x) >> BIT_SHIFT_WMAC_ARPIP) & BIT_MASK_WMAC_ARPIP)
+#define BIT_SET_WMAC_ARPIP(x, v) (BIT_CLEAR_WMAC_ARPIP(x) | BIT_WMAC_ARPIP(v))
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_BEAMFORMING_INFO_NSARP		(Offset 0x072C) */
+
+#define BIT_SHIFT_UPD_BFMEE_USERID 13
+#define BIT_MASK_UPD_BFMEE_USERID 0x7
+#define BIT_UPD_BFMEE_USERID(x)                                                \
+	(((x) & BIT_MASK_UPD_BFMEE_USERID) << BIT_SHIFT_UPD_BFMEE_USERID)
+#define BITS_UPD_BFMEE_USERID                                                  \
+	(BIT_MASK_UPD_BFMEE_USERID << BIT_SHIFT_UPD_BFMEE_USERID)
+#define BIT_CLEAR_UPD_BFMEE_USERID(x) ((x) & (~BITS_UPD_BFMEE_USERID))
+#define BIT_GET_UPD_BFMEE_USERID(x)                                            \
+	(((x) >> BIT_SHIFT_UPD_BFMEE_USERID) & BIT_MASK_UPD_BFMEE_USERID)
+#define BIT_SET_UPD_BFMEE_USERID(x, v)                                         \
+	(BIT_CLEAR_UPD_BFMEE_USERID(x) | BIT_UPD_BFMEE_USERID(v))
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_RX_CSI_RPT_INFO_V1			(Offset 0x072C) */
+
+#define BIT_WRITE_USERID BIT(12)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_BEAMFORMING_INFO_NSARP		(Offset 0x072C) */
+
+#define BIT_UPD_BFMEE_FBTP BIT(12)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_RX_CSI_RPT_INFO_V1			(Offset 0x072C) */
+
+#define BIT_SHIFT_WRITE_BW 10
+#define BIT_MASK_WRITE_BW 0x3
+#define BIT_WRITE_BW(x) (((x) & BIT_MASK_WRITE_BW) << BIT_SHIFT_WRITE_BW)
+#define BITS_WRITE_BW (BIT_MASK_WRITE_BW << BIT_SHIFT_WRITE_BW)
+#define BIT_CLEAR_WRITE_BW(x) ((x) & (~BITS_WRITE_BW))
+#define BIT_GET_WRITE_BW(x) (((x) >> BIT_SHIFT_WRITE_BW) & BIT_MASK_WRITE_BW)
+#define BIT_SET_WRITE_BW(x, v) (BIT_CLEAR_WRITE_BW(x) | BIT_WRITE_BW(v))
+
+#define BIT_SHIFT_WRITE_CB 8
+#define BIT_MASK_WRITE_CB 0x3
+#define BIT_WRITE_CB(x) (((x) & BIT_MASK_WRITE_CB) << BIT_SHIFT_WRITE_CB)
+#define BITS_WRITE_CB (BIT_MASK_WRITE_CB << BIT_SHIFT_WRITE_CB)
+#define BIT_CLEAR_WRITE_CB(x) ((x) & (~BITS_WRITE_CB))
+#define BIT_GET_WRITE_CB(x) (((x) >> BIT_SHIFT_WRITE_CB) & BIT_MASK_WRITE_CB)
+#define BIT_SET_WRITE_CB(x, v) (BIT_CLEAR_WRITE_CB(x) | BIT_WRITE_CB(v))
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_BEAMFORMING_INFO_NSARP		(Offset 0x072C) */
+
+#define BIT_SHIFT_UPD_BFMEE_CB 8
+#define BIT_MASK_UPD_BFMEE_CB 0x3
+#define BIT_UPD_BFMEE_CB(x)                                                    \
+	(((x) & BIT_MASK_UPD_BFMEE_CB) << BIT_SHIFT_UPD_BFMEE_CB)
+#define BITS_UPD_BFMEE_CB (BIT_MASK_UPD_BFMEE_CB << BIT_SHIFT_UPD_BFMEE_CB)
+#define BIT_CLEAR_UPD_BFMEE_CB(x) ((x) & (~BITS_UPD_BFMEE_CB))
+#define BIT_GET_UPD_BFMEE_CB(x)                                                \
+	(((x) >> BIT_SHIFT_UPD_BFMEE_CB) & BIT_MASK_UPD_BFMEE_CB)
+#define BIT_SET_UPD_BFMEE_CB(x, v)                                             \
+	(BIT_CLEAR_UPD_BFMEE_CB(x) | BIT_UPD_BFMEE_CB(v))
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_RX_CSI_RPT_INFO_V1			(Offset 0x072C) */
+
+#define BIT_SHIFT_WRITE_GROUPING 6
+#define BIT_MASK_WRITE_GROUPING 0x3
+#define BIT_WRITE_GROUPING(x)                                                  \
+	(((x) & BIT_MASK_WRITE_GROUPING) << BIT_SHIFT_WRITE_GROUPING)
+#define BITS_WRITE_GROUPING                                                    \
+	(BIT_MASK_WRITE_GROUPING << BIT_SHIFT_WRITE_GROUPING)
+#define BIT_CLEAR_WRITE_GROUPING(x) ((x) & (~BITS_WRITE_GROUPING))
+#define BIT_GET_WRITE_GROUPING(x)                                              \
+	(((x) >> BIT_SHIFT_WRITE_GROUPING) & BIT_MASK_WRITE_GROUPING)
+#define BIT_SET_WRITE_GROUPING(x, v)                                           \
+	(BIT_CLEAR_WRITE_GROUPING(x) | BIT_WRITE_GROUPING(v))
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_BEAMFORMING_INFO_NSARP		(Offset 0x072C) */
+
+#define BIT_SHIFT_UPD_BFMEE_NG 6
+#define BIT_MASK_UPD_BFMEE_NG 0x3
+#define BIT_UPD_BFMEE_NG(x)                                                    \
+	(((x) & BIT_MASK_UPD_BFMEE_NG) << BIT_SHIFT_UPD_BFMEE_NG)
+#define BITS_UPD_BFMEE_NG (BIT_MASK_UPD_BFMEE_NG << BIT_SHIFT_UPD_BFMEE_NG)
+#define BIT_CLEAR_UPD_BFMEE_NG(x) ((x) & (~BITS_UPD_BFMEE_NG))
+#define BIT_GET_UPD_BFMEE_NG(x)                                                \
+	(((x) >> BIT_SHIFT_UPD_BFMEE_NG) & BIT_MASK_UPD_BFMEE_NG)
+#define BIT_SET_UPD_BFMEE_NG(x, v)                                             \
+	(BIT_CLEAR_UPD_BFMEE_NG(x) | BIT_UPD_BFMEE_NG(v))
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_RX_CSI_RPT_INFO_V1			(Offset 0x072C) */
+
+#define BIT_SHIFT_WRITE_NR 3
+#define BIT_MASK_WRITE_NR 0x7
+#define BIT_WRITE_NR(x) (((x) & BIT_MASK_WRITE_NR) << BIT_SHIFT_WRITE_NR)
+#define BITS_WRITE_NR (BIT_MASK_WRITE_NR << BIT_SHIFT_WRITE_NR)
+#define BIT_CLEAR_WRITE_NR(x) ((x) & (~BITS_WRITE_NR))
+#define BIT_GET_WRITE_NR(x) (((x) >> BIT_SHIFT_WRITE_NR) & BIT_MASK_WRITE_NR)
+#define BIT_SET_WRITE_NR(x, v) (BIT_CLEAR_WRITE_NR(x) | BIT_WRITE_NR(v))
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_BEAMFORMING_INFO_NSARP		(Offset 0x072C) */
+
+#define BIT_SHIFT_UPD_BFMEE_NR 3
+#define BIT_MASK_UPD_BFMEE_NR 0x7
+#define BIT_UPD_BFMEE_NR(x)                                                    \
+	(((x) & BIT_MASK_UPD_BFMEE_NR) << BIT_SHIFT_UPD_BFMEE_NR)
+#define BITS_UPD_BFMEE_NR (BIT_MASK_UPD_BFMEE_NR << BIT_SHIFT_UPD_BFMEE_NR)
+#define BIT_CLEAR_UPD_BFMEE_NR(x) ((x) & (~BITS_UPD_BFMEE_NR))
+#define BIT_GET_UPD_BFMEE_NR(x)                                                \
+	(((x) >> BIT_SHIFT_UPD_BFMEE_NR) & BIT_MASK_UPD_BFMEE_NR)
+#define BIT_SET_UPD_BFMEE_NR(x, v)                                             \
+	(BIT_CLEAR_UPD_BFMEE_NR(x) | BIT_UPD_BFMEE_NR(v))
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_RX_CSI_RPT_INFO_V1			(Offset 0x072C) */
+
+#define BIT_SHIFT_WRITE_NC 0
+#define BIT_MASK_WRITE_NC 0x7
+#define BIT_WRITE_NC(x) (((x) & BIT_MASK_WRITE_NC) << BIT_SHIFT_WRITE_NC)
+#define BITS_WRITE_NC (BIT_MASK_WRITE_NC << BIT_SHIFT_WRITE_NC)
+#define BIT_CLEAR_WRITE_NC(x) ((x) & (~BITS_WRITE_NC))
+#define BIT_GET_WRITE_NC(x) (((x) >> BIT_SHIFT_WRITE_NC) & BIT_MASK_WRITE_NC)
+#define BIT_SET_WRITE_NC(x, v) (BIT_CLEAR_WRITE_NC(x) | BIT_WRITE_NC(v))
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+
+/* 2 REG_BEAMFORMING_INFO_NSARP		(Offset 0x072C) */
+
+#define BIT_SHIFT_BEAMFORMING_INFO 0
+#define BIT_MASK_BEAMFORMING_INFO 0xffffffffL
+#define BIT_BEAMFORMING_INFO(x)                                                \
+	(((x) & BIT_MASK_BEAMFORMING_INFO) << BIT_SHIFT_BEAMFORMING_INFO)
+#define BITS_BEAMFORMING_INFO                                                  \
+	(BIT_MASK_BEAMFORMING_INFO << BIT_SHIFT_BEAMFORMING_INFO)
+#define BIT_CLEAR_BEAMFORMING_INFO(x) ((x) & (~BITS_BEAMFORMING_INFO))
+#define BIT_GET_BEAMFORMING_INFO(x)                                            \
+	(((x) >> BIT_SHIFT_BEAMFORMING_INFO) & BIT_MASK_BEAMFORMING_INFO)
+#define BIT_SET_BEAMFORMING_INFO(x, v)                                         \
+	(BIT_CLEAR_BEAMFORMING_INFO(x) | BIT_BEAMFORMING_INFO(v))
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_BEAMFORMING_INFO_NSARP		(Offset 0x072C) */
+
+#define BIT_SHIFT_UPD_BFMEE_BW 0
+#define BIT_MASK_UPD_BFMEE_BW 0xfff
+#define BIT_UPD_BFMEE_BW(x)                                                    \
+	(((x) & BIT_MASK_UPD_BFMEE_BW) << BIT_SHIFT_UPD_BFMEE_BW)
+#define BITS_UPD_BFMEE_BW (BIT_MASK_UPD_BFMEE_BW << BIT_SHIFT_UPD_BFMEE_BW)
+#define BIT_CLEAR_UPD_BFMEE_BW(x) ((x) & (~BITS_UPD_BFMEE_BW))
+#define BIT_GET_UPD_BFMEE_BW(x)                                                \
+	(((x) >> BIT_SHIFT_UPD_BFMEE_BW) & BIT_MASK_UPD_BFMEE_BW)
+#define BIT_SET_UPD_BFMEE_BW(x, v)                                             \
+	(BIT_CLEAR_UPD_BFMEE_BW(x) | BIT_UPD_BFMEE_BW(v))
+
+#define BIT_SHIFT_UPD_BFMEE_NC 0
+#define BIT_MASK_UPD_BFMEE_NC 0x7
+#define BIT_UPD_BFMEE_NC(x)                                                    \
+	(((x) & BIT_MASK_UPD_BFMEE_NC) << BIT_SHIFT_UPD_BFMEE_NC)
+#define BITS_UPD_BFMEE_NC (BIT_MASK_UPD_BFMEE_NC << BIT_SHIFT_UPD_BFMEE_NC)
+#define BIT_CLEAR_UPD_BFMEE_NC(x) ((x) & (~BITS_UPD_BFMEE_NC))
+#define BIT_GET_UPD_BFMEE_NC(x)                                                \
+	(((x) >> BIT_SHIFT_UPD_BFMEE_NC) & BIT_MASK_UPD_BFMEE_NC)
+#define BIT_SET_UPD_BFMEE_NC(x, v)                                             \
+	(BIT_CLEAR_UPD_BFMEE_NC(x) | BIT_UPD_BFMEE_NC(v))
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_IPV6				(Offset 0x0730) */
+
+#define BIT_SHIFT_R_WMAC_IPV6_MYIPAD_0 0
+#define BIT_MASK_R_WMAC_IPV6_MYIPAD_0 0xffffffffL
+#define BIT_R_WMAC_IPV6_MYIPAD_0(x)                                            \
+	(((x) & BIT_MASK_R_WMAC_IPV6_MYIPAD_0)                                 \
+	 << BIT_SHIFT_R_WMAC_IPV6_MYIPAD_0)
+#define BITS_R_WMAC_IPV6_MYIPAD_0                                              \
+	(BIT_MASK_R_WMAC_IPV6_MYIPAD_0 << BIT_SHIFT_R_WMAC_IPV6_MYIPAD_0)
+#define BIT_CLEAR_R_WMAC_IPV6_MYIPAD_0(x) ((x) & (~BITS_R_WMAC_IPV6_MYIPAD_0))
+#define BIT_GET_R_WMAC_IPV6_MYIPAD_0(x)                                        \
+	(((x) >> BIT_SHIFT_R_WMAC_IPV6_MYIPAD_0) &                             \
+	 BIT_MASK_R_WMAC_IPV6_MYIPAD_0)
+#define BIT_SET_R_WMAC_IPV6_MYIPAD_0(x, v)                                     \
+	(BIT_CLEAR_R_WMAC_IPV6_MYIPAD_0(x) | BIT_R_WMAC_IPV6_MYIPAD_0(v))
+
+/* 2 REG_IPV6_1				(Offset 0x0734) */
+
+#define BIT_SHIFT_R_WMAC_IPV6_MYIPAD_1 0
+#define BIT_MASK_R_WMAC_IPV6_MYIPAD_1 0xffffffffL
+#define BIT_R_WMAC_IPV6_MYIPAD_1(x)                                            \
+	(((x) & BIT_MASK_R_WMAC_IPV6_MYIPAD_1)                                 \
+	 << BIT_SHIFT_R_WMAC_IPV6_MYIPAD_1)
+#define BITS_R_WMAC_IPV6_MYIPAD_1                                              \
+	(BIT_MASK_R_WMAC_IPV6_MYIPAD_1 << BIT_SHIFT_R_WMAC_IPV6_MYIPAD_1)
+#define BIT_CLEAR_R_WMAC_IPV6_MYIPAD_1(x) ((x) & (~BITS_R_WMAC_IPV6_MYIPAD_1))
+#define BIT_GET_R_WMAC_IPV6_MYIPAD_1(x)                                        \
+	(((x) >> BIT_SHIFT_R_WMAC_IPV6_MYIPAD_1) &                             \
+	 BIT_MASK_R_WMAC_IPV6_MYIPAD_1)
+#define BIT_SET_R_WMAC_IPV6_MYIPAD_1(x, v)                                     \
+	(BIT_CLEAR_R_WMAC_IPV6_MYIPAD_1(x) | BIT_R_WMAC_IPV6_MYIPAD_1(v))
+
+/* 2 REG_IPV6_2				(Offset 0x0738) */
+
+#define BIT_SHIFT_R_WMAC_IPV6_MYIPAD_2 0
+#define BIT_MASK_R_WMAC_IPV6_MYIPAD_2 0xffffffffL
+#define BIT_R_WMAC_IPV6_MYIPAD_2(x)                                            \
+	(((x) & BIT_MASK_R_WMAC_IPV6_MYIPAD_2)                                 \
+	 << BIT_SHIFT_R_WMAC_IPV6_MYIPAD_2)
+#define BITS_R_WMAC_IPV6_MYIPAD_2                                              \
+	(BIT_MASK_R_WMAC_IPV6_MYIPAD_2 << BIT_SHIFT_R_WMAC_IPV6_MYIPAD_2)
+#define BIT_CLEAR_R_WMAC_IPV6_MYIPAD_2(x) ((x) & (~BITS_R_WMAC_IPV6_MYIPAD_2))
+#define BIT_GET_R_WMAC_IPV6_MYIPAD_2(x)                                        \
+	(((x) >> BIT_SHIFT_R_WMAC_IPV6_MYIPAD_2) &                             \
+	 BIT_MASK_R_WMAC_IPV6_MYIPAD_2)
+#define BIT_SET_R_WMAC_IPV6_MYIPAD_2(x, v)                                     \
+	(BIT_CLEAR_R_WMAC_IPV6_MYIPAD_2(x) | BIT_R_WMAC_IPV6_MYIPAD_2(v))
+
+/* 2 REG_IPV6_3				(Offset 0x073C) */
+
+#define BIT_SHIFT_R_WMAC_IPV6_MYIPAD_3 0
+#define BIT_MASK_R_WMAC_IPV6_MYIPAD_3 0xffffffffL
+#define BIT_R_WMAC_IPV6_MYIPAD_3(x)                                            \
+	(((x) & BIT_MASK_R_WMAC_IPV6_MYIPAD_3)                                 \
+	 << BIT_SHIFT_R_WMAC_IPV6_MYIPAD_3)
+#define BITS_R_WMAC_IPV6_MYIPAD_3                                              \
+	(BIT_MASK_R_WMAC_IPV6_MYIPAD_3 << BIT_SHIFT_R_WMAC_IPV6_MYIPAD_3)
+#define BIT_CLEAR_R_WMAC_IPV6_MYIPAD_3(x) ((x) & (~BITS_R_WMAC_IPV6_MYIPAD_3))
+#define BIT_GET_R_WMAC_IPV6_MYIPAD_3(x)                                        \
+	(((x) >> BIT_SHIFT_R_WMAC_IPV6_MYIPAD_3) &                             \
+	 BIT_MASK_R_WMAC_IPV6_MYIPAD_3)
+#define BIT_SET_R_WMAC_IPV6_MYIPAD_3(x, v)                                     \
+	(BIT_CLEAR_R_WMAC_IPV6_MYIPAD_3(x) | BIT_R_WMAC_IPV6_MYIPAD_3(v))
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_WMAC_RTX_CTX_SUBTYPE_CFG		(Offset 0x0750) */
+
+#define BIT_SHIFT_R_WMAC_CTX_SUBTYPE 4
+#define BIT_MASK_R_WMAC_CTX_SUBTYPE 0xf
+#define BIT_R_WMAC_CTX_SUBTYPE(x)                                              \
+	(((x) & BIT_MASK_R_WMAC_CTX_SUBTYPE) << BIT_SHIFT_R_WMAC_CTX_SUBTYPE)
+#define BITS_R_WMAC_CTX_SUBTYPE                                                \
+	(BIT_MASK_R_WMAC_CTX_SUBTYPE << BIT_SHIFT_R_WMAC_CTX_SUBTYPE)
+#define BIT_CLEAR_R_WMAC_CTX_SUBTYPE(x) ((x) & (~BITS_R_WMAC_CTX_SUBTYPE))
+#define BIT_GET_R_WMAC_CTX_SUBTYPE(x)                                          \
+	(((x) >> BIT_SHIFT_R_WMAC_CTX_SUBTYPE) & BIT_MASK_R_WMAC_CTX_SUBTYPE)
+#define BIT_SET_R_WMAC_CTX_SUBTYPE(x, v)                                       \
+	(BIT_CLEAR_R_WMAC_CTX_SUBTYPE(x) | BIT_R_WMAC_CTX_SUBTYPE(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_WMAC_RTX_CTX_SUBTYPE_CFG		(Offset 0x0750) */
+
+#define BIT_SHIFT_R_WMAC_RTX_SUBTYPE 0
+#define BIT_MASK_R_WMAC_RTX_SUBTYPE 0xf
+#define BIT_R_WMAC_RTX_SUBTYPE(x)                                              \
+	(((x) & BIT_MASK_R_WMAC_RTX_SUBTYPE) << BIT_SHIFT_R_WMAC_RTX_SUBTYPE)
+#define BITS_R_WMAC_RTX_SUBTYPE                                                \
+	(BIT_MASK_R_WMAC_RTX_SUBTYPE << BIT_SHIFT_R_WMAC_RTX_SUBTYPE)
+#define BIT_CLEAR_R_WMAC_RTX_SUBTYPE(x) ((x) & (~BITS_R_WMAC_RTX_SUBTYPE))
+#define BIT_GET_R_WMAC_RTX_SUBTYPE(x)                                          \
+	(((x) >> BIT_SHIFT_R_WMAC_RTX_SUBTYPE) & BIT_MASK_R_WMAC_RTX_SUBTYPE)
+#define BIT_SET_R_WMAC_RTX_SUBTYPE(x, v)                                       \
+	(BIT_CLEAR_R_WMAC_RTX_SUBTYPE(x) | BIT_R_WMAC_RTX_SUBTYPE(v))
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_WMAC_SWAES_DIO_B63_B32		(Offset 0x0754) */
+
+#define BIT_SHIFT_WMAC_SWAES_DIO_B63_B32 0
+#define BIT_MASK_WMAC_SWAES_DIO_B63_B32 0xffffffffL
+#define BIT_WMAC_SWAES_DIO_B63_B32(x)                                          \
+	(((x) & BIT_MASK_WMAC_SWAES_DIO_B63_B32)                               \
+	 << BIT_SHIFT_WMAC_SWAES_DIO_B63_B32)
+#define BITS_WMAC_SWAES_DIO_B63_B32                                            \
+	(BIT_MASK_WMAC_SWAES_DIO_B63_B32 << BIT_SHIFT_WMAC_SWAES_DIO_B63_B32)
+#define BIT_CLEAR_WMAC_SWAES_DIO_B63_B32(x)                                    \
+	((x) & (~BITS_WMAC_SWAES_DIO_B63_B32))
+#define BIT_GET_WMAC_SWAES_DIO_B63_B32(x)                                      \
+	(((x) >> BIT_SHIFT_WMAC_SWAES_DIO_B63_B32) &                           \
+	 BIT_MASK_WMAC_SWAES_DIO_B63_B32)
+#define BIT_SET_WMAC_SWAES_DIO_B63_B32(x, v)                                   \
+	(BIT_CLEAR_WMAC_SWAES_DIO_B63_B32(x) | BIT_WMAC_SWAES_DIO_B63_B32(v))
+
+/* 2 REG_WMAC_SWAES_DIO_B95_B64		(Offset 0x0758) */
+
+#define BIT_SHIFT_WMAC_SWAES_DIO_B95_B64 0
+#define BIT_MASK_WMAC_SWAES_DIO_B95_B64 0xffffffffL
+#define BIT_WMAC_SWAES_DIO_B95_B64(x)                                          \
+	(((x) & BIT_MASK_WMAC_SWAES_DIO_B95_B64)                               \
+	 << BIT_SHIFT_WMAC_SWAES_DIO_B95_B64)
+#define BITS_WMAC_SWAES_DIO_B95_B64                                            \
+	(BIT_MASK_WMAC_SWAES_DIO_B95_B64 << BIT_SHIFT_WMAC_SWAES_DIO_B95_B64)
+#define BIT_CLEAR_WMAC_SWAES_DIO_B95_B64(x)                                    \
+	((x) & (~BITS_WMAC_SWAES_DIO_B95_B64))
+#define BIT_GET_WMAC_SWAES_DIO_B95_B64(x)                                      \
+	(((x) >> BIT_SHIFT_WMAC_SWAES_DIO_B95_B64) &                           \
+	 BIT_MASK_WMAC_SWAES_DIO_B95_B64)
+#define BIT_SET_WMAC_SWAES_DIO_B95_B64(x, v)                                   \
+	(BIT_CLEAR_WMAC_SWAES_DIO_B95_B64(x) | BIT_WMAC_SWAES_DIO_B95_B64(v))
+
+/* 2 REG_WMAC_SWAES_DIO_B127_B96		(Offset 0x075C) */
+
+#define BIT_SHIFT_WMAC_SWAES_DIO_B127_B96 0
+#define BIT_MASK_WMAC_SWAES_DIO_B127_B96 0xffffffffL
+#define BIT_WMAC_SWAES_DIO_B127_B96(x)                                         \
+	(((x) & BIT_MASK_WMAC_SWAES_DIO_B127_B96)                              \
+	 << BIT_SHIFT_WMAC_SWAES_DIO_B127_B96)
+#define BITS_WMAC_SWAES_DIO_B127_B96                                           \
+	(BIT_MASK_WMAC_SWAES_DIO_B127_B96 << BIT_SHIFT_WMAC_SWAES_DIO_B127_B96)
+#define BIT_CLEAR_WMAC_SWAES_DIO_B127_B96(x)                                   \
+	((x) & (~BITS_WMAC_SWAES_DIO_B127_B96))
+#define BIT_GET_WMAC_SWAES_DIO_B127_B96(x)                                     \
+	(((x) >> BIT_SHIFT_WMAC_SWAES_DIO_B127_B96) &                          \
+	 BIT_MASK_WMAC_SWAES_DIO_B127_B96)
+#define BIT_SET_WMAC_SWAES_DIO_B127_B96(x, v)                                  \
+	(BIT_CLEAR_WMAC_SWAES_DIO_B127_B96(x) | BIT_WMAC_SWAES_DIO_B127_B96(v))
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+/* 2 REG_WMAC_SWAES_CFG			(Offset 0x0760) */
+
+#define BIT_SWAES_REQ BIT(7)
+#define BIT_CLR_SWAES_REQ BIT(6)
+#define BIT_R_WMAC_SWAES_WE BIT(3)
+#define BIT_R_WMAC_SWAES_SEL BIT(0)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_BT_COEX_V2				(Offset 0x0762) */
+
+#define BIT_GNT_BT_POLARITY BIT(12)
+#define BIT_GNT_BT_BYPASS_PRIORITY BIT(8)
+
+#define BIT_SHIFT_TIMER 0
+#define BIT_MASK_TIMER 0xff
+#define BIT_TIMER(x) (((x) & BIT_MASK_TIMER) << BIT_SHIFT_TIMER)
+#define BITS_TIMER (BIT_MASK_TIMER << BIT_SHIFT_TIMER)
+#define BIT_CLEAR_TIMER(x) ((x) & (~BITS_TIMER))
+#define BIT_GET_TIMER(x) (((x) >> BIT_SHIFT_TIMER) & BIT_MASK_TIMER)
+#define BIT_SET_TIMER(x, v) (BIT_CLEAR_TIMER(x) | BIT_TIMER(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_BT_COEX				(Offset 0x0764) */
+
+#define BIT_R_GNT_BT_RFC_SW BIT(12)
+#define BIT_R_GNT_BT_RFC_SW_EN BIT(11)
+#define BIT_R_GNT_BT_BB_SW BIT(10)
+#define BIT_R_GNT_BT_BB_SW_EN BIT(9)
+#define BIT_R_BT_CNT_THREN BIT(8)
+
+#define BIT_SHIFT_R_BT_CNT_THR 0
+#define BIT_MASK_R_BT_CNT_THR 0xff
+#define BIT_R_BT_CNT_THR(x)                                                    \
+	(((x) & BIT_MASK_R_BT_CNT_THR) << BIT_SHIFT_R_BT_CNT_THR)
+#define BITS_R_BT_CNT_THR (BIT_MASK_R_BT_CNT_THR << BIT_SHIFT_R_BT_CNT_THR)
+#define BIT_CLEAR_R_BT_CNT_THR(x) ((x) & (~BITS_R_BT_CNT_THR))
+#define BIT_GET_R_BT_CNT_THR(x)                                                \
+	(((x) >> BIT_SHIFT_R_BT_CNT_THR) & BIT_MASK_R_BT_CNT_THR)
+#define BIT_SET_R_BT_CNT_THR(x, v)                                             \
+	(BIT_CLEAR_R_BT_CNT_THR(x) | BIT_R_BT_CNT_THR(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT)
+
+/* 2 REG_WLAN_ACT_MASK_CTRL			(Offset 0x0768) */
+
+#define BIT_WLRX_TER_BY_CTL BIT(43)
+#define BIT_WLRX_TER_BY_AD BIT(42)
+#define BIT_ANT_DIVERSITY_SEL BIT(41)
+#define BIT_ANTSEL_FOR_BT_CTRL_EN BIT(40)
+#define BIT_WLACT_LOW_GNTWL_EN BIT(34)
+#define BIT_WLACT_HIGH_GNTBT_EN BIT(33)
+
+#endif
+
+#if (HALMAC_8822B_SUPPORT)
+
+/* 2 REG_WLAN_ACT_MASK_CTRL			(Offset 0x0768) */
+
+#define BIT_NAV_UPPER_V1 BIT(32)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_WLAN_ACT_MASK_CTRL			(Offset 0x0768) */
+
+#define BIT_SHIFT_RXMYRTS_NAV_V1 8
+#define BIT_MASK_RXMYRTS_NAV_V1 0xff
+#define BIT_RXMYRTS_NAV_V1(x)                                                  \
+	(((x) & BIT_MASK_RXMYRTS_NAV_V1) << BIT_SHIFT_RXMYRTS_NAV_V1)
+#define BITS_RXMYRTS_NAV_V1                                                    \
+	(BIT_MASK_RXMYRTS_NAV_V1 << BIT_SHIFT_RXMYRTS_NAV_V1)
+#define BIT_CLEAR_RXMYRTS_NAV_V1(x) ((x) & (~BITS_RXMYRTS_NAV_V1))
+#define BIT_GET_RXMYRTS_NAV_V1(x)                                              \
+	(((x) >> BIT_SHIFT_RXMYRTS_NAV_V1) & BIT_MASK_RXMYRTS_NAV_V1)
+#define BIT_SET_RXMYRTS_NAV_V1(x, v)                                           \
+	(BIT_CLEAR_RXMYRTS_NAV_V1(x) | BIT_RXMYRTS_NAV_V1(v))
+
+#define BIT_SHIFT_RTSRST_V1 0
+#define BIT_MASK_RTSRST_V1 0xff
+#define BIT_RTSRST_V1(x) (((x) & BIT_MASK_RTSRST_V1) << BIT_SHIFT_RTSRST_V1)
+#define BITS_RTSRST_V1 (BIT_MASK_RTSRST_V1 << BIT_SHIFT_RTSRST_V1)
+#define BIT_CLEAR_RTSRST_V1(x) ((x) & (~BITS_RTSRST_V1))
+#define BIT_GET_RTSRST_V1(x) (((x) >> BIT_SHIFT_RTSRST_V1) & BIT_MASK_RTSRST_V1)
+#define BIT_SET_RTSRST_V1(x, v) (BIT_CLEAR_RTSRST_V1(x) | BIT_RTSRST_V1(v))
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_WLAN_ACT_MASK_CTRL_1		(Offset 0x076C) */
+
+#define BIT_WLRX_TER_BY_CTL_1 BIT(11)
+#define BIT_WLRX_TER_BY_AD_1 BIT(10)
+#define BIT_ANT_DIVERSITY_SEL_1 BIT(9)
+#define BIT_ANTSEL_FOR_BT_CTRL_EN_1 BIT(8)
+#define BIT_WLACT_LOW_GNTWL_EN_1 BIT(2)
+#define BIT_WLACT_HIGH_GNTBT_EN_1 BIT(1)
+#define BIT_NAV_UPPER_1_V1 BIT(0)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_BT_COEX_ENHANCED_INTR_CTRL		(Offset 0x076E) */
+
+#define BIT_SHIFT_BT_STAT_DELAY 12
+#define BIT_MASK_BT_STAT_DELAY 0xf
+#define BIT_BT_STAT_DELAY(x)                                                   \
+	(((x) & BIT_MASK_BT_STAT_DELAY) << BIT_SHIFT_BT_STAT_DELAY)
+#define BITS_BT_STAT_DELAY (BIT_MASK_BT_STAT_DELAY << BIT_SHIFT_BT_STAT_DELAY)
+#define BIT_CLEAR_BT_STAT_DELAY(x) ((x) & (~BITS_BT_STAT_DELAY))
+#define BIT_GET_BT_STAT_DELAY(x)                                               \
+	(((x) >> BIT_SHIFT_BT_STAT_DELAY) & BIT_MASK_BT_STAT_DELAY)
+#define BIT_SET_BT_STAT_DELAY(x, v)                                            \
+	(BIT_CLEAR_BT_STAT_DELAY(x) | BIT_BT_STAT_DELAY(v))
+
+#define BIT_SHIFT_BT_TRX_INIT_DETECT 8
+#define BIT_MASK_BT_TRX_INIT_DETECT 0xf
+#define BIT_BT_TRX_INIT_DETECT(x)                                              \
+	(((x) & BIT_MASK_BT_TRX_INIT_DETECT) << BIT_SHIFT_BT_TRX_INIT_DETECT)
+#define BITS_BT_TRX_INIT_DETECT                                                \
+	(BIT_MASK_BT_TRX_INIT_DETECT << BIT_SHIFT_BT_TRX_INIT_DETECT)
+#define BIT_CLEAR_BT_TRX_INIT_DETECT(x) ((x) & (~BITS_BT_TRX_INIT_DETECT))
+#define BIT_GET_BT_TRX_INIT_DETECT(x)                                          \
+	(((x) >> BIT_SHIFT_BT_TRX_INIT_DETECT) & BIT_MASK_BT_TRX_INIT_DETECT)
+#define BIT_SET_BT_TRX_INIT_DETECT(x, v)                                       \
+	(BIT_CLEAR_BT_TRX_INIT_DETECT(x) | BIT_BT_TRX_INIT_DETECT(v))
+
+#define BIT_SHIFT_BT_PRI_DETECT_TO 4
+#define BIT_MASK_BT_PRI_DETECT_TO 0xf
+#define BIT_BT_PRI_DETECT_TO(x)                                                \
+	(((x) & BIT_MASK_BT_PRI_DETECT_TO) << BIT_SHIFT_BT_PRI_DETECT_TO)
+#define BITS_BT_PRI_DETECT_TO                                                  \
+	(BIT_MASK_BT_PRI_DETECT_TO << BIT_SHIFT_BT_PRI_DETECT_TO)
+#define BIT_CLEAR_BT_PRI_DETECT_TO(x) ((x) & (~BITS_BT_PRI_DETECT_TO))
+#define BIT_GET_BT_PRI_DETECT_TO(x)                                            \
+	(((x) >> BIT_SHIFT_BT_PRI_DETECT_TO) & BIT_MASK_BT_PRI_DETECT_TO)
+#define BIT_SET_BT_PRI_DETECT_TO(x, v)                                         \
+	(BIT_CLEAR_BT_PRI_DETECT_TO(x) | BIT_BT_PRI_DETECT_TO(v))
+
+#define BIT_R_GRANTALL_WLMASK BIT(3)
+#define BIT_STATIS_BT_EN BIT(2)
+#define BIT_WL_ACT_MASK_ENABLE BIT(1)
+#define BIT_ENHANCED_BT BIT(0)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT)
+
+/* 2 REG_BT_ACT_STATISTICS			(Offset 0x0770) */
+
+#define BIT_SHIFT_STATIS_BT_LO_RX (48 & CPU_OPT_WIDTH)
+#define BIT_MASK_STATIS_BT_LO_RX 0xffff
+#define BIT_STATIS_BT_LO_RX(x)                                                 \
+	(((x) & BIT_MASK_STATIS_BT_LO_RX) << BIT_SHIFT_STATIS_BT_LO_RX)
+#define BITS_STATIS_BT_LO_RX                                                   \
+	(BIT_MASK_STATIS_BT_LO_RX << BIT_SHIFT_STATIS_BT_LO_RX)
+#define BIT_CLEAR_STATIS_BT_LO_RX(x) ((x) & (~BITS_STATIS_BT_LO_RX))
+#define BIT_GET_STATIS_BT_LO_RX(x)                                             \
+	(((x) >> BIT_SHIFT_STATIS_BT_LO_RX) & BIT_MASK_STATIS_BT_LO_RX)
+#define BIT_SET_STATIS_BT_LO_RX(x, v)                                          \
+	(BIT_CLEAR_STATIS_BT_LO_RX(x) | BIT_STATIS_BT_LO_RX(v))
+
+#define BIT_SHIFT_STATIS_BT_LO_TX (32 & CPU_OPT_WIDTH)
+#define BIT_MASK_STATIS_BT_LO_TX 0xffff
+#define BIT_STATIS_BT_LO_TX(x)                                                 \
+	(((x) & BIT_MASK_STATIS_BT_LO_TX) << BIT_SHIFT_STATIS_BT_LO_TX)
+#define BITS_STATIS_BT_LO_TX                                                   \
+	(BIT_MASK_STATIS_BT_LO_TX << BIT_SHIFT_STATIS_BT_LO_TX)
+#define BIT_CLEAR_STATIS_BT_LO_TX(x) ((x) & (~BITS_STATIS_BT_LO_TX))
+#define BIT_GET_STATIS_BT_LO_TX(x)                                             \
+	(((x) >> BIT_SHIFT_STATIS_BT_LO_TX) & BIT_MASK_STATIS_BT_LO_TX)
+#define BIT_SET_STATIS_BT_LO_TX(x, v)                                          \
+	(BIT_CLEAR_STATIS_BT_LO_TX(x) | BIT_STATIS_BT_LO_TX(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_BT_ACT_STATISTICS			(Offset 0x0770) */
+
+#define BIT_SHIFT_STATIS_BT_HI_RX 16
+#define BIT_MASK_STATIS_BT_HI_RX 0xffff
+#define BIT_STATIS_BT_HI_RX(x)                                                 \
+	(((x) & BIT_MASK_STATIS_BT_HI_RX) << BIT_SHIFT_STATIS_BT_HI_RX)
+#define BITS_STATIS_BT_HI_RX                                                   \
+	(BIT_MASK_STATIS_BT_HI_RX << BIT_SHIFT_STATIS_BT_HI_RX)
+#define BIT_CLEAR_STATIS_BT_HI_RX(x) ((x) & (~BITS_STATIS_BT_HI_RX))
+#define BIT_GET_STATIS_BT_HI_RX(x)                                             \
+	(((x) >> BIT_SHIFT_STATIS_BT_HI_RX) & BIT_MASK_STATIS_BT_HI_RX)
+#define BIT_SET_STATIS_BT_HI_RX(x, v)                                          \
+	(BIT_CLEAR_STATIS_BT_HI_RX(x) | BIT_STATIS_BT_HI_RX(v))
+
+#define BIT_SHIFT_STATIS_BT_HI_TX 0
+#define BIT_MASK_STATIS_BT_HI_TX 0xffff
+#define BIT_STATIS_BT_HI_TX(x)                                                 \
+	(((x) & BIT_MASK_STATIS_BT_HI_TX) << BIT_SHIFT_STATIS_BT_HI_TX)
+#define BITS_STATIS_BT_HI_TX                                                   \
+	(BIT_MASK_STATIS_BT_HI_TX << BIT_SHIFT_STATIS_BT_HI_TX)
+#define BIT_CLEAR_STATIS_BT_HI_TX(x) ((x) & (~BITS_STATIS_BT_HI_TX))
+#define BIT_GET_STATIS_BT_HI_TX(x)                                             \
+	(((x) >> BIT_SHIFT_STATIS_BT_HI_TX) & BIT_MASK_STATIS_BT_HI_TX)
+#define BIT_SET_STATIS_BT_HI_TX(x, v)                                          \
+	(BIT_CLEAR_STATIS_BT_HI_TX(x) | BIT_STATIS_BT_HI_TX(v))
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_BT_ACT_STATISTICS_1			(Offset 0x0774) */
+
+#define BIT_APPEND_MACID_IN_RESP_EN_1 BIT(18)
+#define BIT_ADDR2_MATCH_EN_1 BIT(17)
+
+#define BIT_SHIFT_STATIS_BT_LO_RX_1 16
+#define BIT_MASK_STATIS_BT_LO_RX_1 0xffff
+#define BIT_STATIS_BT_LO_RX_1(x)                                               \
+	(((x) & BIT_MASK_STATIS_BT_LO_RX_1) << BIT_SHIFT_STATIS_BT_LO_RX_1)
+#define BITS_STATIS_BT_LO_RX_1                                                 \
+	(BIT_MASK_STATIS_BT_LO_RX_1 << BIT_SHIFT_STATIS_BT_LO_RX_1)
+#define BIT_CLEAR_STATIS_BT_LO_RX_1(x) ((x) & (~BITS_STATIS_BT_LO_RX_1))
+#define BIT_GET_STATIS_BT_LO_RX_1(x)                                           \
+	(((x) >> BIT_SHIFT_STATIS_BT_LO_RX_1) & BIT_MASK_STATIS_BT_LO_RX_1)
+#define BIT_SET_STATIS_BT_LO_RX_1(x, v)                                        \
+	(BIT_CLEAR_STATIS_BT_LO_RX_1(x) | BIT_STATIS_BT_LO_RX_1(v))
+
+#define BIT_ANTTRN_EN_1 BIT(16)
+
+#define BIT_SHIFT_STATIS_BT_LO_TX_1 0
+#define BIT_MASK_STATIS_BT_LO_TX_1 0xffff
+#define BIT_STATIS_BT_LO_TX_1(x)                                               \
+	(((x) & BIT_MASK_STATIS_BT_LO_TX_1) << BIT_SHIFT_STATIS_BT_LO_TX_1)
+#define BITS_STATIS_BT_LO_TX_1                                                 \
+	(BIT_MASK_STATIS_BT_LO_TX_1 << BIT_SHIFT_STATIS_BT_LO_TX_1)
+#define BIT_CLEAR_STATIS_BT_LO_TX_1(x) ((x) & (~BITS_STATIS_BT_LO_TX_1))
+#define BIT_GET_STATIS_BT_LO_TX_1(x)                                           \
+	(((x) >> BIT_SHIFT_STATIS_BT_LO_TX_1) & BIT_MASK_STATIS_BT_LO_TX_1)
+#define BIT_SET_STATIS_BT_LO_TX_1(x, v)                                        \
+	(BIT_CLEAR_STATIS_BT_LO_TX_1(x) | BIT_STATIS_BT_LO_TX_1(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_BT_STATISTICS_CONTROL_REGISTER	(Offset 0x0778) */
+
+#define BIT_SHIFT_R_BT_CMD_RPT 16
+#define BIT_MASK_R_BT_CMD_RPT 0xffff
+#define BIT_R_BT_CMD_RPT(x)                                                    \
+	(((x) & BIT_MASK_R_BT_CMD_RPT) << BIT_SHIFT_R_BT_CMD_RPT)
+#define BITS_R_BT_CMD_RPT (BIT_MASK_R_BT_CMD_RPT << BIT_SHIFT_R_BT_CMD_RPT)
+#define BIT_CLEAR_R_BT_CMD_RPT(x) ((x) & (~BITS_R_BT_CMD_RPT))
+#define BIT_GET_R_BT_CMD_RPT(x)                                                \
+	(((x) >> BIT_SHIFT_R_BT_CMD_RPT) & BIT_MASK_R_BT_CMD_RPT)
+#define BIT_SET_R_BT_CMD_RPT(x, v)                                             \
+	(BIT_CLEAR_R_BT_CMD_RPT(x) | BIT_R_BT_CMD_RPT(v))
+
+#define BIT_SHIFT_R_RPT_FROM_BT 8
+#define BIT_MASK_R_RPT_FROM_BT 0xff
+#define BIT_R_RPT_FROM_BT(x)                                                   \
+	(((x) & BIT_MASK_R_RPT_FROM_BT) << BIT_SHIFT_R_RPT_FROM_BT)
+#define BITS_R_RPT_FROM_BT (BIT_MASK_R_RPT_FROM_BT << BIT_SHIFT_R_RPT_FROM_BT)
+#define BIT_CLEAR_R_RPT_FROM_BT(x) ((x) & (~BITS_R_RPT_FROM_BT))
+#define BIT_GET_R_RPT_FROM_BT(x)                                               \
+	(((x) >> BIT_SHIFT_R_RPT_FROM_BT) & BIT_MASK_R_RPT_FROM_BT)
+#define BIT_SET_R_RPT_FROM_BT(x, v)                                            \
+	(BIT_CLEAR_R_RPT_FROM_BT(x) | BIT_R_RPT_FROM_BT(v))
+
+#define BIT_SHIFT_BT_HID_ISR_SET 6
+#define BIT_MASK_BT_HID_ISR_SET 0x3
+#define BIT_BT_HID_ISR_SET(x)                                                  \
+	(((x) & BIT_MASK_BT_HID_ISR_SET) << BIT_SHIFT_BT_HID_ISR_SET)
+#define BITS_BT_HID_ISR_SET                                                    \
+	(BIT_MASK_BT_HID_ISR_SET << BIT_SHIFT_BT_HID_ISR_SET)
+#define BIT_CLEAR_BT_HID_ISR_SET(x) ((x) & (~BITS_BT_HID_ISR_SET))
+#define BIT_GET_BT_HID_ISR_SET(x)                                              \
+	(((x) >> BIT_SHIFT_BT_HID_ISR_SET) & BIT_MASK_BT_HID_ISR_SET)
+#define BIT_SET_BT_HID_ISR_SET(x, v)                                           \
+	(BIT_CLEAR_BT_HID_ISR_SET(x) | BIT_BT_HID_ISR_SET(v))
+
+#define BIT_TDMA_BT_START_NOTIFY BIT(5)
+#define BIT_ENABLE_TDMA_FW_MODE BIT(4)
+#define BIT_ENABLE_PTA_TDMA_MODE BIT(3)
+#define BIT_ENABLE_COEXIST_TAB_IN_TDMA BIT(2)
+#define BIT_GPIO2_GPIO3_EXANGE_OR_NO_BT_CCA BIT(1)
+#define BIT_RTK_BT_ENABLE BIT(0)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_BT_STATUS_REPORT_REGISTER		(Offset 0x077C) */
+
+#define BIT_SHIFT_BT_PROFILE 24
+#define BIT_MASK_BT_PROFILE 0xff
+#define BIT_BT_PROFILE(x) (((x) & BIT_MASK_BT_PROFILE) << BIT_SHIFT_BT_PROFILE)
+#define BITS_BT_PROFILE (BIT_MASK_BT_PROFILE << BIT_SHIFT_BT_PROFILE)
+#define BIT_CLEAR_BT_PROFILE(x) ((x) & (~BITS_BT_PROFILE))
+#define BIT_GET_BT_PROFILE(x)                                                  \
+	(((x) >> BIT_SHIFT_BT_PROFILE) & BIT_MASK_BT_PROFILE)
+#define BIT_SET_BT_PROFILE(x, v) (BIT_CLEAR_BT_PROFILE(x) | BIT_BT_PROFILE(v))
+
+#define BIT_SHIFT_BT_POWER 16
+#define BIT_MASK_BT_POWER 0xff
+#define BIT_BT_POWER(x) (((x) & BIT_MASK_BT_POWER) << BIT_SHIFT_BT_POWER)
+#define BITS_BT_POWER (BIT_MASK_BT_POWER << BIT_SHIFT_BT_POWER)
+#define BIT_CLEAR_BT_POWER(x) ((x) & (~BITS_BT_POWER))
+#define BIT_GET_BT_POWER(x) (((x) >> BIT_SHIFT_BT_POWER) & BIT_MASK_BT_POWER)
+#define BIT_SET_BT_POWER(x, v) (BIT_CLEAR_BT_POWER(x) | BIT_BT_POWER(v))
+
+#define BIT_SHIFT_BT_PREDECT_STATUS 8
+#define BIT_MASK_BT_PREDECT_STATUS 0xff
+#define BIT_BT_PREDECT_STATUS(x)                                               \
+	(((x) & BIT_MASK_BT_PREDECT_STATUS) << BIT_SHIFT_BT_PREDECT_STATUS)
+#define BITS_BT_PREDECT_STATUS                                                 \
+	(BIT_MASK_BT_PREDECT_STATUS << BIT_SHIFT_BT_PREDECT_STATUS)
+#define BIT_CLEAR_BT_PREDECT_STATUS(x) ((x) & (~BITS_BT_PREDECT_STATUS))
+#define BIT_GET_BT_PREDECT_STATUS(x)                                           \
+	(((x) >> BIT_SHIFT_BT_PREDECT_STATUS) & BIT_MASK_BT_PREDECT_STATUS)
+#define BIT_SET_BT_PREDECT_STATUS(x, v)                                        \
+	(BIT_CLEAR_BT_PREDECT_STATUS(x) | BIT_BT_PREDECT_STATUS(v))
+
+#define BIT_SHIFT_BT_CMD_INFO 0
+#define BIT_MASK_BT_CMD_INFO 0xff
+#define BIT_BT_CMD_INFO(x)                                                     \
+	(((x) & BIT_MASK_BT_CMD_INFO) << BIT_SHIFT_BT_CMD_INFO)
+#define BITS_BT_CMD_INFO (BIT_MASK_BT_CMD_INFO << BIT_SHIFT_BT_CMD_INFO)
+#define BIT_CLEAR_BT_CMD_INFO(x) ((x) & (~BITS_BT_CMD_INFO))
+#define BIT_GET_BT_CMD_INFO(x)                                                 \
+	(((x) >> BIT_SHIFT_BT_CMD_INFO) & BIT_MASK_BT_CMD_INFO)
+#define BIT_SET_BT_CMD_INFO(x, v)                                              \
+	(BIT_CLEAR_BT_CMD_INFO(x) | BIT_BT_CMD_INFO(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_BT_INTERRUPT_CONTROL_REGISTER	(Offset 0x0780) */
+
+#define BIT_EN_MAC_NULL_PKT_NOTIFY BIT(31)
+#define BIT_EN_WLAN_RPT_AND_BT_QUERY BIT(30)
+#define BIT_EN_BT_STSTUS_RPT BIT(29)
+#define BIT_EN_BT_POWER BIT(28)
+#define BIT_EN_BT_CHANNEL BIT(27)
+#define BIT_EN_BT_SLOT_CHANGE BIT(26)
+#define BIT_EN_BT_PROFILE_OR_HID BIT(25)
+#define BIT_WLAN_RPT_NOTIFY BIT(24)
+
+#define BIT_SHIFT_WLAN_RPT_DATA 16
+#define BIT_MASK_WLAN_RPT_DATA 0xff
+#define BIT_WLAN_RPT_DATA(x)                                                   \
+	(((x) & BIT_MASK_WLAN_RPT_DATA) << BIT_SHIFT_WLAN_RPT_DATA)
+#define BITS_WLAN_RPT_DATA (BIT_MASK_WLAN_RPT_DATA << BIT_SHIFT_WLAN_RPT_DATA)
+#define BIT_CLEAR_WLAN_RPT_DATA(x) ((x) & (~BITS_WLAN_RPT_DATA))
+#define BIT_GET_WLAN_RPT_DATA(x)                                               \
+	(((x) >> BIT_SHIFT_WLAN_RPT_DATA) & BIT_MASK_WLAN_RPT_DATA)
+#define BIT_SET_WLAN_RPT_DATA(x, v)                                            \
+	(BIT_CLEAR_WLAN_RPT_DATA(x) | BIT_WLAN_RPT_DATA(v))
+
+#define BIT_SHIFT_CMD_ID 8
+#define BIT_MASK_CMD_ID 0xff
+#define BIT_CMD_ID(x) (((x) & BIT_MASK_CMD_ID) << BIT_SHIFT_CMD_ID)
+#define BITS_CMD_ID (BIT_MASK_CMD_ID << BIT_SHIFT_CMD_ID)
+#define BIT_CLEAR_CMD_ID(x) ((x) & (~BITS_CMD_ID))
+#define BIT_GET_CMD_ID(x) (((x) >> BIT_SHIFT_CMD_ID) & BIT_MASK_CMD_ID)
+#define BIT_SET_CMD_ID(x, v) (BIT_CLEAR_CMD_ID(x) | BIT_CMD_ID(v))
+
+#define BIT_SHIFT_BT_DATA 0
+#define BIT_MASK_BT_DATA 0xff
+#define BIT_BT_DATA(x) (((x) & BIT_MASK_BT_DATA) << BIT_SHIFT_BT_DATA)
+#define BITS_BT_DATA (BIT_MASK_BT_DATA << BIT_SHIFT_BT_DATA)
+#define BIT_CLEAR_BT_DATA(x) ((x) & (~BITS_BT_DATA))
+#define BIT_GET_BT_DATA(x) (((x) >> BIT_SHIFT_BT_DATA) & BIT_MASK_BT_DATA)
+#define BIT_SET_BT_DATA(x, v) (BIT_CLEAR_BT_DATA(x) | BIT_BT_DATA(v))
+
+/* 2 REG_WLAN_REPORT_TIME_OUT_CONTROL_REGISTER (Offset 0x0784) */
+
+#define BIT_SHIFT_WLAN_RPT_TO 0
+#define BIT_MASK_WLAN_RPT_TO 0xff
+#define BIT_WLAN_RPT_TO(x)                                                     \
+	(((x) & BIT_MASK_WLAN_RPT_TO) << BIT_SHIFT_WLAN_RPT_TO)
+#define BITS_WLAN_RPT_TO (BIT_MASK_WLAN_RPT_TO << BIT_SHIFT_WLAN_RPT_TO)
+#define BIT_CLEAR_WLAN_RPT_TO(x) ((x) & (~BITS_WLAN_RPT_TO))
+#define BIT_GET_WLAN_RPT_TO(x)                                                 \
+	(((x) >> BIT_SHIFT_WLAN_RPT_TO) & BIT_MASK_WLAN_RPT_TO)
+#define BIT_SET_WLAN_RPT_TO(x, v)                                              \
+	(BIT_CLEAR_WLAN_RPT_TO(x) | BIT_WLAN_RPT_TO(v))
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_BT_ISOLATION_TABLE_REGISTER_REGISTER (Offset 0x0785) */
+
+#define BIT_SHIFT_ISOLATION_CHK_0 1
+#define BIT_MASK_ISOLATION_CHK_0 0x7fffff
+#define BIT_ISOLATION_CHK_0(x)                                                 \
+	(((x) & BIT_MASK_ISOLATION_CHK_0) << BIT_SHIFT_ISOLATION_CHK_0)
+#define BITS_ISOLATION_CHK_0                                                   \
+	(BIT_MASK_ISOLATION_CHK_0 << BIT_SHIFT_ISOLATION_CHK_0)
+#define BIT_CLEAR_ISOLATION_CHK_0(x) ((x) & (~BITS_ISOLATION_CHK_0))
+#define BIT_GET_ISOLATION_CHK_0(x)                                             \
+	(((x) >> BIT_SHIFT_ISOLATION_CHK_0) & BIT_MASK_ISOLATION_CHK_0)
+#define BIT_SET_ISOLATION_CHK_0(x, v)                                          \
+	(BIT_CLEAR_ISOLATION_CHK_0(x) | BIT_ISOLATION_CHK_0(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT)
+
+/* 2 REG_BT_ISOLATION_TABLE_REGISTER_REGISTER (Offset 0x0785) */
+
+#define BIT_SHIFT_ISOLATION_CHK 1
+#define BIT_MASK_ISOLATION_CHK 0x7fffffffffffffffffffL
+#define BIT_ISOLATION_CHK(x)                                                   \
+	(((x) & BIT_MASK_ISOLATION_CHK) << BIT_SHIFT_ISOLATION_CHK)
+#define BITS_ISOLATION_CHK (BIT_MASK_ISOLATION_CHK << BIT_SHIFT_ISOLATION_CHK)
+#define BIT_CLEAR_ISOLATION_CHK(x) ((x) & (~BITS_ISOLATION_CHK))
+#define BIT_GET_ISOLATION_CHK(x)                                               \
+	(((x) >> BIT_SHIFT_ISOLATION_CHK) & BIT_MASK_ISOLATION_CHK)
+#define BIT_SET_ISOLATION_CHK(x, v)                                            \
+	(BIT_CLEAR_ISOLATION_CHK(x) | BIT_ISOLATION_CHK(v))
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_BT_ISOLATION_TABLE_REGISTER_REGISTER (Offset 0x0785) */
+
+#define BIT_ISOLATION_EN BIT(0)
+
+#define BIT_SHIFT_R_CCK_LEN 0
+#define BIT_MASK_R_CCK_LEN 0xffff
+#define BIT_R_CCK_LEN(x) (((x) & BIT_MASK_R_CCK_LEN) << BIT_SHIFT_R_CCK_LEN)
+#define BITS_R_CCK_LEN (BIT_MASK_R_CCK_LEN << BIT_SHIFT_R_CCK_LEN)
+#define BIT_CLEAR_R_CCK_LEN(x) ((x) & (~BITS_R_CCK_LEN))
+#define BIT_GET_R_CCK_LEN(x) (((x) >> BIT_SHIFT_R_CCK_LEN) & BIT_MASK_R_CCK_LEN)
+#define BIT_SET_R_CCK_LEN(x, v) (BIT_CLEAR_R_CCK_LEN(x) | BIT_R_CCK_LEN(v))
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_BT_ISOLATION_TABLE_REGISTER_REGISTER_1 (Offset 0x0788) */
+
+#define BIT_SHIFT_ISOLATION_CHK_1 0
+#define BIT_MASK_ISOLATION_CHK_1 0xffffffffL
+#define BIT_ISOLATION_CHK_1(x)                                                 \
+	(((x) & BIT_MASK_ISOLATION_CHK_1) << BIT_SHIFT_ISOLATION_CHK_1)
+#define BITS_ISOLATION_CHK_1                                                   \
+	(BIT_MASK_ISOLATION_CHK_1 << BIT_SHIFT_ISOLATION_CHK_1)
+#define BIT_CLEAR_ISOLATION_CHK_1(x) ((x) & (~BITS_ISOLATION_CHK_1))
+#define BIT_GET_ISOLATION_CHK_1(x)                                             \
+	(((x) >> BIT_SHIFT_ISOLATION_CHK_1) & BIT_MASK_ISOLATION_CHK_1)
+#define BIT_SET_ISOLATION_CHK_1(x, v)                                          \
+	(BIT_CLEAR_ISOLATION_CHK_1(x) | BIT_ISOLATION_CHK_1(v))
+
+/* 2 REG_BT_ISOLATION_TABLE_REGISTER_REGISTER_2 (Offset 0x078C) */
+
+#define BIT_SHIFT_ISOLATION_CHK_2 0
+#define BIT_MASK_ISOLATION_CHK_2 0xffffff
+#define BIT_ISOLATION_CHK_2(x)                                                 \
+	(((x) & BIT_MASK_ISOLATION_CHK_2) << BIT_SHIFT_ISOLATION_CHK_2)
+#define BITS_ISOLATION_CHK_2                                                   \
+	(BIT_MASK_ISOLATION_CHK_2 << BIT_SHIFT_ISOLATION_CHK_2)
+#define BIT_CLEAR_ISOLATION_CHK_2(x) ((x) & (~BITS_ISOLATION_CHK_2))
+#define BIT_GET_ISOLATION_CHK_2(x)                                             \
+	(((x) >> BIT_SHIFT_ISOLATION_CHK_2) & BIT_MASK_ISOLATION_CHK_2)
+#define BIT_SET_ISOLATION_CHK_2(x, v)                                          \
+	(BIT_CLEAR_ISOLATION_CHK_2(x) | BIT_ISOLATION_CHK_2(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_BT_INTERRUPT_STATUS_REGISTER	(Offset 0x078F) */
+
+#define BIT_BT_HID_ISR BIT(7)
+#define BIT_BT_QUERY_ISR BIT(6)
+#define BIT_MAC_NULL_PKT_NOTIFY_ISR BIT(5)
+#define BIT_WLAN_RPT_ISR BIT(4)
+#define BIT_BT_POWER_ISR BIT(3)
+#define BIT_BT_CHANNEL_ISR BIT(2)
+#define BIT_BT_SLOT_CHANGE_ISR BIT(1)
+#define BIT_BT_PROFILE_ISR BIT(0)
+
+/* 2 REG_BT_TDMA_TIME_REGISTER		(Offset 0x0790) */
+
+#define BIT_SHIFT_BT_TIME 6
+#define BIT_MASK_BT_TIME 0x3ffffff
+#define BIT_BT_TIME(x) (((x) & BIT_MASK_BT_TIME) << BIT_SHIFT_BT_TIME)
+#define BITS_BT_TIME (BIT_MASK_BT_TIME << BIT_SHIFT_BT_TIME)
+#define BIT_CLEAR_BT_TIME(x) ((x) & (~BITS_BT_TIME))
+#define BIT_GET_BT_TIME(x) (((x) >> BIT_SHIFT_BT_TIME) & BIT_MASK_BT_TIME)
+#define BIT_SET_BT_TIME(x, v) (BIT_CLEAR_BT_TIME(x) | BIT_BT_TIME(v))
+
+#define BIT_SHIFT_BT_RPT_SAMPLE_RATE 0
+#define BIT_MASK_BT_RPT_SAMPLE_RATE 0x3f
+#define BIT_BT_RPT_SAMPLE_RATE(x)                                              \
+	(((x) & BIT_MASK_BT_RPT_SAMPLE_RATE) << BIT_SHIFT_BT_RPT_SAMPLE_RATE)
+#define BITS_BT_RPT_SAMPLE_RATE                                                \
+	(BIT_MASK_BT_RPT_SAMPLE_RATE << BIT_SHIFT_BT_RPT_SAMPLE_RATE)
+#define BIT_CLEAR_BT_RPT_SAMPLE_RATE(x) ((x) & (~BITS_BT_RPT_SAMPLE_RATE))
+#define BIT_GET_BT_RPT_SAMPLE_RATE(x)                                          \
+	(((x) >> BIT_SHIFT_BT_RPT_SAMPLE_RATE) & BIT_MASK_BT_RPT_SAMPLE_RATE)
+#define BIT_SET_BT_RPT_SAMPLE_RATE(x, v)                                       \
+	(BIT_CLEAR_BT_RPT_SAMPLE_RATE(x) | BIT_BT_RPT_SAMPLE_RATE(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT)
+
+/* 2 REG_BT_ACT_REGISTER			(Offset 0x0794) */
+
+#define BIT_SHIFT_R_OFDM_LEN 26
+#define BIT_MASK_R_OFDM_LEN 0x3f
+#define BIT_R_OFDM_LEN(x) (((x) & BIT_MASK_R_OFDM_LEN) << BIT_SHIFT_R_OFDM_LEN)
+#define BITS_R_OFDM_LEN (BIT_MASK_R_OFDM_LEN << BIT_SHIFT_R_OFDM_LEN)
+#define BIT_CLEAR_R_OFDM_LEN(x) ((x) & (~BITS_R_OFDM_LEN))
+#define BIT_GET_R_OFDM_LEN(x)                                                  \
+	(((x) >> BIT_SHIFT_R_OFDM_LEN) & BIT_MASK_R_OFDM_LEN)
+#define BIT_SET_R_OFDM_LEN(x, v) (BIT_CLEAR_R_OFDM_LEN(x) | BIT_R_OFDM_LEN(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_BT_ACT_REGISTER			(Offset 0x0794) */
+
+#define BIT_SHIFT_BT_EISR_EN 16
+#define BIT_MASK_BT_EISR_EN 0xff
+#define BIT_BT_EISR_EN(x) (((x) & BIT_MASK_BT_EISR_EN) << BIT_SHIFT_BT_EISR_EN)
+#define BITS_BT_EISR_EN (BIT_MASK_BT_EISR_EN << BIT_SHIFT_BT_EISR_EN)
+#define BIT_CLEAR_BT_EISR_EN(x) ((x) & (~BITS_BT_EISR_EN))
+#define BIT_GET_BT_EISR_EN(x)                                                  \
+	(((x) >> BIT_SHIFT_BT_EISR_EN) & BIT_MASK_BT_EISR_EN)
+#define BIT_SET_BT_EISR_EN(x, v) (BIT_CLEAR_BT_EISR_EN(x) | BIT_BT_EISR_EN(v))
+
+#define BIT_BT_ACT_FALLING_ISR BIT(10)
+#define BIT_BT_ACT_RISING_ISR BIT(9)
+#define BIT_TDMA_TO_ISR BIT(8)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT)
+
+/* 2 REG_BT_ACT_REGISTER			(Offset 0x0794) */
+
+#define BIT_SHIFT_BT_CH 0
+#define BIT_MASK_BT_CH 0xff
+#define BIT_BT_CH(x) (((x) & BIT_MASK_BT_CH) << BIT_SHIFT_BT_CH)
+#define BITS_BT_CH (BIT_MASK_BT_CH << BIT_SHIFT_BT_CH)
+#define BIT_CLEAR_BT_CH(x) ((x) & (~BITS_BT_CH))
+#define BIT_GET_BT_CH(x) (((x) >> BIT_SHIFT_BT_CH) & BIT_MASK_BT_CH)
+#define BIT_SET_BT_CH(x, v) (BIT_CLEAR_BT_CH(x) | BIT_BT_CH(v))
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_BT_ACT_REGISTER			(Offset 0x0794) */
+
+#define BIT_SHIFT_BT_CH_V1 0
+#define BIT_MASK_BT_CH_V1 0x7f
+#define BIT_BT_CH_V1(x) (((x) & BIT_MASK_BT_CH_V1) << BIT_SHIFT_BT_CH_V1)
+#define BITS_BT_CH_V1 (BIT_MASK_BT_CH_V1 << BIT_SHIFT_BT_CH_V1)
+#define BIT_CLEAR_BT_CH_V1(x) ((x) & (~BITS_BT_CH_V1))
+#define BIT_GET_BT_CH_V1(x) (((x) >> BIT_SHIFT_BT_CH_V1) & BIT_MASK_BT_CH_V1)
+#define BIT_SET_BT_CH_V1(x, v) (BIT_CLEAR_BT_CH_V1(x) | BIT_BT_CH_V1(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_OBFF_CTRL_BASIC			(Offset 0x0798) */
+
+#define BIT_OBFF_EN_V1 BIT(31)
+
+#define BIT_SHIFT_OBFF_STATE_V1 28
+#define BIT_MASK_OBFF_STATE_V1 0x3
+#define BIT_OBFF_STATE_V1(x)                                                   \
+	(((x) & BIT_MASK_OBFF_STATE_V1) << BIT_SHIFT_OBFF_STATE_V1)
+#define BITS_OBFF_STATE_V1 (BIT_MASK_OBFF_STATE_V1 << BIT_SHIFT_OBFF_STATE_V1)
+#define BIT_CLEAR_OBFF_STATE_V1(x) ((x) & (~BITS_OBFF_STATE_V1))
+#define BIT_GET_OBFF_STATE_V1(x)                                               \
+	(((x) >> BIT_SHIFT_OBFF_STATE_V1) & BIT_MASK_OBFF_STATE_V1)
+#define BIT_SET_OBFF_STATE_V1(x, v)                                            \
+	(BIT_CLEAR_OBFF_STATE_V1(x) | BIT_OBFF_STATE_V1(v))
+
+#define BIT_OBFF_ACT_RXDMA_EN BIT(27)
+#define BIT_OBFF_BLOCK_INT_EN BIT(26)
+#define BIT_OBFF_AUTOACT_EN BIT(25)
+#define BIT_OBFF_AUTOIDLE_EN BIT(24)
+
+#define BIT_SHIFT_WAKE_MAX_PLS 20
+#define BIT_MASK_WAKE_MAX_PLS 0x7
+#define BIT_WAKE_MAX_PLS(x)                                                    \
+	(((x) & BIT_MASK_WAKE_MAX_PLS) << BIT_SHIFT_WAKE_MAX_PLS)
+#define BITS_WAKE_MAX_PLS (BIT_MASK_WAKE_MAX_PLS << BIT_SHIFT_WAKE_MAX_PLS)
+#define BIT_CLEAR_WAKE_MAX_PLS(x) ((x) & (~BITS_WAKE_MAX_PLS))
+#define BIT_GET_WAKE_MAX_PLS(x)                                                \
+	(((x) >> BIT_SHIFT_WAKE_MAX_PLS) & BIT_MASK_WAKE_MAX_PLS)
+#define BIT_SET_WAKE_MAX_PLS(x, v)                                             \
+	(BIT_CLEAR_WAKE_MAX_PLS(x) | BIT_WAKE_MAX_PLS(v))
+
+#define BIT_SHIFT_WAKE_MIN_PLS 16
+#define BIT_MASK_WAKE_MIN_PLS 0x7
+#define BIT_WAKE_MIN_PLS(x)                                                    \
+	(((x) & BIT_MASK_WAKE_MIN_PLS) << BIT_SHIFT_WAKE_MIN_PLS)
+#define BITS_WAKE_MIN_PLS (BIT_MASK_WAKE_MIN_PLS << BIT_SHIFT_WAKE_MIN_PLS)
+#define BIT_CLEAR_WAKE_MIN_PLS(x) ((x) & (~BITS_WAKE_MIN_PLS))
+#define BIT_GET_WAKE_MIN_PLS(x)                                                \
+	(((x) >> BIT_SHIFT_WAKE_MIN_PLS) & BIT_MASK_WAKE_MIN_PLS)
+#define BIT_SET_WAKE_MIN_PLS(x, v)                                             \
+	(BIT_CLEAR_WAKE_MIN_PLS(x) | BIT_WAKE_MIN_PLS(v))
+
+#define BIT_SHIFT_WAKE_MAX_F2F 12
+#define BIT_MASK_WAKE_MAX_F2F 0x7
+#define BIT_WAKE_MAX_F2F(x)                                                    \
+	(((x) & BIT_MASK_WAKE_MAX_F2F) << BIT_SHIFT_WAKE_MAX_F2F)
+#define BITS_WAKE_MAX_F2F (BIT_MASK_WAKE_MAX_F2F << BIT_SHIFT_WAKE_MAX_F2F)
+#define BIT_CLEAR_WAKE_MAX_F2F(x) ((x) & (~BITS_WAKE_MAX_F2F))
+#define BIT_GET_WAKE_MAX_F2F(x)                                                \
+	(((x) >> BIT_SHIFT_WAKE_MAX_F2F) & BIT_MASK_WAKE_MAX_F2F)
+#define BIT_SET_WAKE_MAX_F2F(x, v)                                             \
+	(BIT_CLEAR_WAKE_MAX_F2F(x) | BIT_WAKE_MAX_F2F(v))
+
+#define BIT_SHIFT_WAKE_MIN_F2F 8
+#define BIT_MASK_WAKE_MIN_F2F 0x7
+#define BIT_WAKE_MIN_F2F(x)                                                    \
+	(((x) & BIT_MASK_WAKE_MIN_F2F) << BIT_SHIFT_WAKE_MIN_F2F)
+#define BITS_WAKE_MIN_F2F (BIT_MASK_WAKE_MIN_F2F << BIT_SHIFT_WAKE_MIN_F2F)
+#define BIT_CLEAR_WAKE_MIN_F2F(x) ((x) & (~BITS_WAKE_MIN_F2F))
+#define BIT_GET_WAKE_MIN_F2F(x)                                                \
+	(((x) >> BIT_SHIFT_WAKE_MIN_F2F) & BIT_MASK_WAKE_MIN_F2F)
+#define BIT_SET_WAKE_MIN_F2F(x, v)                                             \
+	(BIT_CLEAR_WAKE_MIN_F2F(x) | BIT_WAKE_MIN_F2F(v))
+
+#define BIT_APP_CPU_ACT_V1 BIT(3)
+#define BIT_APP_OBFF_V1 BIT(2)
+#define BIT_APP_IDLE_V1 BIT(1)
+#define BIT_APP_INIT_V1 BIT(0)
+
+/* 2 REG_OBFF_CTRL2_TIMER			(Offset 0x079C) */
+
+#define BIT_SHIFT_RX_HIGH_TIMER_IDX 24
+#define BIT_MASK_RX_HIGH_TIMER_IDX 0x7
+#define BIT_RX_HIGH_TIMER_IDX(x)                                               \
+	(((x) & BIT_MASK_RX_HIGH_TIMER_IDX) << BIT_SHIFT_RX_HIGH_TIMER_IDX)
+#define BITS_RX_HIGH_TIMER_IDX                                                 \
+	(BIT_MASK_RX_HIGH_TIMER_IDX << BIT_SHIFT_RX_HIGH_TIMER_IDX)
+#define BIT_CLEAR_RX_HIGH_TIMER_IDX(x) ((x) & (~BITS_RX_HIGH_TIMER_IDX))
+#define BIT_GET_RX_HIGH_TIMER_IDX(x)                                           \
+	(((x) >> BIT_SHIFT_RX_HIGH_TIMER_IDX) & BIT_MASK_RX_HIGH_TIMER_IDX)
+#define BIT_SET_RX_HIGH_TIMER_IDX(x, v)                                        \
+	(BIT_CLEAR_RX_HIGH_TIMER_IDX(x) | BIT_RX_HIGH_TIMER_IDX(v))
+
+#define BIT_SHIFT_RX_MED_TIMER_IDX 16
+#define BIT_MASK_RX_MED_TIMER_IDX 0x7
+#define BIT_RX_MED_TIMER_IDX(x)                                                \
+	(((x) & BIT_MASK_RX_MED_TIMER_IDX) << BIT_SHIFT_RX_MED_TIMER_IDX)
+#define BITS_RX_MED_TIMER_IDX                                                  \
+	(BIT_MASK_RX_MED_TIMER_IDX << BIT_SHIFT_RX_MED_TIMER_IDX)
+#define BIT_CLEAR_RX_MED_TIMER_IDX(x) ((x) & (~BITS_RX_MED_TIMER_IDX))
+#define BIT_GET_RX_MED_TIMER_IDX(x)                                            \
+	(((x) >> BIT_SHIFT_RX_MED_TIMER_IDX) & BIT_MASK_RX_MED_TIMER_IDX)
+#define BIT_SET_RX_MED_TIMER_IDX(x, v)                                         \
+	(BIT_CLEAR_RX_MED_TIMER_IDX(x) | BIT_RX_MED_TIMER_IDX(v))
+
+#define BIT_SHIFT_RX_LOW_TIMER_IDX 8
+#define BIT_MASK_RX_LOW_TIMER_IDX 0x7
+#define BIT_RX_LOW_TIMER_IDX(x)                                                \
+	(((x) & BIT_MASK_RX_LOW_TIMER_IDX) << BIT_SHIFT_RX_LOW_TIMER_IDX)
+#define BITS_RX_LOW_TIMER_IDX                                                  \
+	(BIT_MASK_RX_LOW_TIMER_IDX << BIT_SHIFT_RX_LOW_TIMER_IDX)
+#define BIT_CLEAR_RX_LOW_TIMER_IDX(x) ((x) & (~BITS_RX_LOW_TIMER_IDX))
+#define BIT_GET_RX_LOW_TIMER_IDX(x)                                            \
+	(((x) >> BIT_SHIFT_RX_LOW_TIMER_IDX) & BIT_MASK_RX_LOW_TIMER_IDX)
+#define BIT_SET_RX_LOW_TIMER_IDX(x, v)                                         \
+	(BIT_CLEAR_RX_LOW_TIMER_IDX(x) | BIT_RX_LOW_TIMER_IDX(v))
+
+#define BIT_SHIFT_OBFF_INT_TIMER_IDX 0
+#define BIT_MASK_OBFF_INT_TIMER_IDX 0x7
+#define BIT_OBFF_INT_TIMER_IDX(x)                                              \
+	(((x) & BIT_MASK_OBFF_INT_TIMER_IDX) << BIT_SHIFT_OBFF_INT_TIMER_IDX)
+#define BITS_OBFF_INT_TIMER_IDX                                                \
+	(BIT_MASK_OBFF_INT_TIMER_IDX << BIT_SHIFT_OBFF_INT_TIMER_IDX)
+#define BIT_CLEAR_OBFF_INT_TIMER_IDX(x) ((x) & (~BITS_OBFF_INT_TIMER_IDX))
+#define BIT_GET_OBFF_INT_TIMER_IDX(x)                                          \
+	(((x) >> BIT_SHIFT_OBFF_INT_TIMER_IDX) & BIT_MASK_OBFF_INT_TIMER_IDX)
+#define BIT_SET_OBFF_INT_TIMER_IDX(x, v)                                       \
+	(BIT_CLEAR_OBFF_INT_TIMER_IDX(x) | BIT_OBFF_INT_TIMER_IDX(v))
+
+/* 2 REG_LTR_CTRL_BASIC			(Offset 0x07A0) */
+
+#define BIT_LTR_EN_V1 BIT(31)
+#define BIT_LTR_HW_EN_V1 BIT(30)
+#define BIT_LRT_ACT_CTS_EN BIT(29)
+#define BIT_LTR_ACT_RXPKT_EN BIT(28)
+#define BIT_LTR_ACT_RXDMA_EN BIT(27)
+#define BIT_LTR_IDLE_NO_SNOOP BIT(26)
+#define BIT_SPDUP_MGTPKT BIT(25)
+#define BIT_RX_AGG_EN BIT(24)
+#define BIT_APP_LTR_ACT BIT(23)
+#define BIT_APP_LTR_IDLE BIT(22)
+
+#define BIT_SHIFT_HIGH_RATE_TRIG_SEL 20
+#define BIT_MASK_HIGH_RATE_TRIG_SEL 0x3
+#define BIT_HIGH_RATE_TRIG_SEL(x)                                              \
+	(((x) & BIT_MASK_HIGH_RATE_TRIG_SEL) << BIT_SHIFT_HIGH_RATE_TRIG_SEL)
+#define BITS_HIGH_RATE_TRIG_SEL                                                \
+	(BIT_MASK_HIGH_RATE_TRIG_SEL << BIT_SHIFT_HIGH_RATE_TRIG_SEL)
+#define BIT_CLEAR_HIGH_RATE_TRIG_SEL(x) ((x) & (~BITS_HIGH_RATE_TRIG_SEL))
+#define BIT_GET_HIGH_RATE_TRIG_SEL(x)                                          \
+	(((x) >> BIT_SHIFT_HIGH_RATE_TRIG_SEL) & BIT_MASK_HIGH_RATE_TRIG_SEL)
+#define BIT_SET_HIGH_RATE_TRIG_SEL(x, v)                                       \
+	(BIT_CLEAR_HIGH_RATE_TRIG_SEL(x) | BIT_HIGH_RATE_TRIG_SEL(v))
+
+#define BIT_SHIFT_MED_RATE_TRIG_SEL 18
+#define BIT_MASK_MED_RATE_TRIG_SEL 0x3
+#define BIT_MED_RATE_TRIG_SEL(x)                                               \
+	(((x) & BIT_MASK_MED_RATE_TRIG_SEL) << BIT_SHIFT_MED_RATE_TRIG_SEL)
+#define BITS_MED_RATE_TRIG_SEL                                                 \
+	(BIT_MASK_MED_RATE_TRIG_SEL << BIT_SHIFT_MED_RATE_TRIG_SEL)
+#define BIT_CLEAR_MED_RATE_TRIG_SEL(x) ((x) & (~BITS_MED_RATE_TRIG_SEL))
+#define BIT_GET_MED_RATE_TRIG_SEL(x)                                           \
+	(((x) >> BIT_SHIFT_MED_RATE_TRIG_SEL) & BIT_MASK_MED_RATE_TRIG_SEL)
+#define BIT_SET_MED_RATE_TRIG_SEL(x, v)                                        \
+	(BIT_CLEAR_MED_RATE_TRIG_SEL(x) | BIT_MED_RATE_TRIG_SEL(v))
+
+#define BIT_SHIFT_LOW_RATE_TRIG_SEL 16
+#define BIT_MASK_LOW_RATE_TRIG_SEL 0x3
+#define BIT_LOW_RATE_TRIG_SEL(x)                                               \
+	(((x) & BIT_MASK_LOW_RATE_TRIG_SEL) << BIT_SHIFT_LOW_RATE_TRIG_SEL)
+#define BITS_LOW_RATE_TRIG_SEL                                                 \
+	(BIT_MASK_LOW_RATE_TRIG_SEL << BIT_SHIFT_LOW_RATE_TRIG_SEL)
+#define BIT_CLEAR_LOW_RATE_TRIG_SEL(x) ((x) & (~BITS_LOW_RATE_TRIG_SEL))
+#define BIT_GET_LOW_RATE_TRIG_SEL(x)                                           \
+	(((x) >> BIT_SHIFT_LOW_RATE_TRIG_SEL) & BIT_MASK_LOW_RATE_TRIG_SEL)
+#define BIT_SET_LOW_RATE_TRIG_SEL(x, v)                                        \
+	(BIT_CLEAR_LOW_RATE_TRIG_SEL(x) | BIT_LOW_RATE_TRIG_SEL(v))
+
+#define BIT_SHIFT_HIGH_RATE_BD_IDX 8
+#define BIT_MASK_HIGH_RATE_BD_IDX 0x7f
+#define BIT_HIGH_RATE_BD_IDX(x)                                                \
+	(((x) & BIT_MASK_HIGH_RATE_BD_IDX) << BIT_SHIFT_HIGH_RATE_BD_IDX)
+#define BITS_HIGH_RATE_BD_IDX                                                  \
+	(BIT_MASK_HIGH_RATE_BD_IDX << BIT_SHIFT_HIGH_RATE_BD_IDX)
+#define BIT_CLEAR_HIGH_RATE_BD_IDX(x) ((x) & (~BITS_HIGH_RATE_BD_IDX))
+#define BIT_GET_HIGH_RATE_BD_IDX(x)                                            \
+	(((x) >> BIT_SHIFT_HIGH_RATE_BD_IDX) & BIT_MASK_HIGH_RATE_BD_IDX)
+#define BIT_SET_HIGH_RATE_BD_IDX(x, v)                                         \
+	(BIT_CLEAR_HIGH_RATE_BD_IDX(x) | BIT_HIGH_RATE_BD_IDX(v))
+
+#define BIT_SHIFT_LOW_RATE_BD_IDX 0
+#define BIT_MASK_LOW_RATE_BD_IDX 0x7f
+#define BIT_LOW_RATE_BD_IDX(x)                                                 \
+	(((x) & BIT_MASK_LOW_RATE_BD_IDX) << BIT_SHIFT_LOW_RATE_BD_IDX)
+#define BITS_LOW_RATE_BD_IDX                                                   \
+	(BIT_MASK_LOW_RATE_BD_IDX << BIT_SHIFT_LOW_RATE_BD_IDX)
+#define BIT_CLEAR_LOW_RATE_BD_IDX(x) ((x) & (~BITS_LOW_RATE_BD_IDX))
+#define BIT_GET_LOW_RATE_BD_IDX(x)                                             \
+	(((x) >> BIT_SHIFT_LOW_RATE_BD_IDX) & BIT_MASK_LOW_RATE_BD_IDX)
+#define BIT_SET_LOW_RATE_BD_IDX(x, v)                                          \
+	(BIT_CLEAR_LOW_RATE_BD_IDX(x) | BIT_LOW_RATE_BD_IDX(v))
+
+/* 2 REG_LTR_CTRL2_TIMER_THRESHOLD		(Offset 0x07A4) */
+
+#define BIT_SHIFT_RX_EMPTY_TIMER_IDX 24
+#define BIT_MASK_RX_EMPTY_TIMER_IDX 0x7
+#define BIT_RX_EMPTY_TIMER_IDX(x)                                              \
+	(((x) & BIT_MASK_RX_EMPTY_TIMER_IDX) << BIT_SHIFT_RX_EMPTY_TIMER_IDX)
+#define BITS_RX_EMPTY_TIMER_IDX                                                \
+	(BIT_MASK_RX_EMPTY_TIMER_IDX << BIT_SHIFT_RX_EMPTY_TIMER_IDX)
+#define BIT_CLEAR_RX_EMPTY_TIMER_IDX(x) ((x) & (~BITS_RX_EMPTY_TIMER_IDX))
+#define BIT_GET_RX_EMPTY_TIMER_IDX(x)                                          \
+	(((x) >> BIT_SHIFT_RX_EMPTY_TIMER_IDX) & BIT_MASK_RX_EMPTY_TIMER_IDX)
+#define BIT_SET_RX_EMPTY_TIMER_IDX(x, v)                                       \
+	(BIT_CLEAR_RX_EMPTY_TIMER_IDX(x) | BIT_RX_EMPTY_TIMER_IDX(v))
+
+#define BIT_SHIFT_RX_AFULL_TH_IDX 20
+#define BIT_MASK_RX_AFULL_TH_IDX 0x7
+#define BIT_RX_AFULL_TH_IDX(x)                                                 \
+	(((x) & BIT_MASK_RX_AFULL_TH_IDX) << BIT_SHIFT_RX_AFULL_TH_IDX)
+#define BITS_RX_AFULL_TH_IDX                                                   \
+	(BIT_MASK_RX_AFULL_TH_IDX << BIT_SHIFT_RX_AFULL_TH_IDX)
+#define BIT_CLEAR_RX_AFULL_TH_IDX(x) ((x) & (~BITS_RX_AFULL_TH_IDX))
+#define BIT_GET_RX_AFULL_TH_IDX(x)                                             \
+	(((x) >> BIT_SHIFT_RX_AFULL_TH_IDX) & BIT_MASK_RX_AFULL_TH_IDX)
+#define BIT_SET_RX_AFULL_TH_IDX(x, v)                                          \
+	(BIT_CLEAR_RX_AFULL_TH_IDX(x) | BIT_RX_AFULL_TH_IDX(v))
+
+#define BIT_SHIFT_RX_HIGH_TH_IDX 16
+#define BIT_MASK_RX_HIGH_TH_IDX 0x7
+#define BIT_RX_HIGH_TH_IDX(x)                                                  \
+	(((x) & BIT_MASK_RX_HIGH_TH_IDX) << BIT_SHIFT_RX_HIGH_TH_IDX)
+#define BITS_RX_HIGH_TH_IDX                                                    \
+	(BIT_MASK_RX_HIGH_TH_IDX << BIT_SHIFT_RX_HIGH_TH_IDX)
+#define BIT_CLEAR_RX_HIGH_TH_IDX(x) ((x) & (~BITS_RX_HIGH_TH_IDX))
+#define BIT_GET_RX_HIGH_TH_IDX(x)                                              \
+	(((x) >> BIT_SHIFT_RX_HIGH_TH_IDX) & BIT_MASK_RX_HIGH_TH_IDX)
+#define BIT_SET_RX_HIGH_TH_IDX(x, v)                                           \
+	(BIT_CLEAR_RX_HIGH_TH_IDX(x) | BIT_RX_HIGH_TH_IDX(v))
+
+#define BIT_SHIFT_RX_MED_TH_IDX 12
+#define BIT_MASK_RX_MED_TH_IDX 0x7
+#define BIT_RX_MED_TH_IDX(x)                                                   \
+	(((x) & BIT_MASK_RX_MED_TH_IDX) << BIT_SHIFT_RX_MED_TH_IDX)
+#define BITS_RX_MED_TH_IDX (BIT_MASK_RX_MED_TH_IDX << BIT_SHIFT_RX_MED_TH_IDX)
+#define BIT_CLEAR_RX_MED_TH_IDX(x) ((x) & (~BITS_RX_MED_TH_IDX))
+#define BIT_GET_RX_MED_TH_IDX(x)                                               \
+	(((x) >> BIT_SHIFT_RX_MED_TH_IDX) & BIT_MASK_RX_MED_TH_IDX)
+#define BIT_SET_RX_MED_TH_IDX(x, v)                                            \
+	(BIT_CLEAR_RX_MED_TH_IDX(x) | BIT_RX_MED_TH_IDX(v))
+
+#define BIT_SHIFT_RX_LOW_TH_IDX 8
+#define BIT_MASK_RX_LOW_TH_IDX 0x7
+#define BIT_RX_LOW_TH_IDX(x)                                                   \
+	(((x) & BIT_MASK_RX_LOW_TH_IDX) << BIT_SHIFT_RX_LOW_TH_IDX)
+#define BITS_RX_LOW_TH_IDX (BIT_MASK_RX_LOW_TH_IDX << BIT_SHIFT_RX_LOW_TH_IDX)
+#define BIT_CLEAR_RX_LOW_TH_IDX(x) ((x) & (~BITS_RX_LOW_TH_IDX))
+#define BIT_GET_RX_LOW_TH_IDX(x)                                               \
+	(((x) >> BIT_SHIFT_RX_LOW_TH_IDX) & BIT_MASK_RX_LOW_TH_IDX)
+#define BIT_SET_RX_LOW_TH_IDX(x, v)                                            \
+	(BIT_CLEAR_RX_LOW_TH_IDX(x) | BIT_RX_LOW_TH_IDX(v))
+
+#define BIT_SHIFT_LTR_SPACE_IDX 4
+#define BIT_MASK_LTR_SPACE_IDX 0x3
+#define BIT_LTR_SPACE_IDX(x)                                                   \
+	(((x) & BIT_MASK_LTR_SPACE_IDX) << BIT_SHIFT_LTR_SPACE_IDX)
+#define BITS_LTR_SPACE_IDX (BIT_MASK_LTR_SPACE_IDX << BIT_SHIFT_LTR_SPACE_IDX)
+#define BIT_CLEAR_LTR_SPACE_IDX(x) ((x) & (~BITS_LTR_SPACE_IDX))
+#define BIT_GET_LTR_SPACE_IDX(x)                                               \
+	(((x) >> BIT_SHIFT_LTR_SPACE_IDX) & BIT_MASK_LTR_SPACE_IDX)
+#define BIT_SET_LTR_SPACE_IDX(x, v)                                            \
+	(BIT_CLEAR_LTR_SPACE_IDX(x) | BIT_LTR_SPACE_IDX(v))
+
+#define BIT_SHIFT_LTR_IDLE_TIMER_IDX 0
+#define BIT_MASK_LTR_IDLE_TIMER_IDX 0x7
+#define BIT_LTR_IDLE_TIMER_IDX(x)                                              \
+	(((x) & BIT_MASK_LTR_IDLE_TIMER_IDX) << BIT_SHIFT_LTR_IDLE_TIMER_IDX)
+#define BITS_LTR_IDLE_TIMER_IDX                                                \
+	(BIT_MASK_LTR_IDLE_TIMER_IDX << BIT_SHIFT_LTR_IDLE_TIMER_IDX)
+#define BIT_CLEAR_LTR_IDLE_TIMER_IDX(x) ((x) & (~BITS_LTR_IDLE_TIMER_IDX))
+#define BIT_GET_LTR_IDLE_TIMER_IDX(x)                                          \
+	(((x) >> BIT_SHIFT_LTR_IDLE_TIMER_IDX) & BIT_MASK_LTR_IDLE_TIMER_IDX)
+#define BIT_SET_LTR_IDLE_TIMER_IDX(x, v)                                       \
+	(BIT_CLEAR_LTR_IDLE_TIMER_IDX(x) | BIT_LTR_IDLE_TIMER_IDX(v))
+
+/* 2 REG_LTR_IDLE_LATENCY_V1			(Offset 0x07A8) */
+
+#define BIT_SHIFT_LTR_IDLE_L 0
+#define BIT_MASK_LTR_IDLE_L 0xffffffffL
+#define BIT_LTR_IDLE_L(x) (((x) & BIT_MASK_LTR_IDLE_L) << BIT_SHIFT_LTR_IDLE_L)
+#define BITS_LTR_IDLE_L (BIT_MASK_LTR_IDLE_L << BIT_SHIFT_LTR_IDLE_L)
+#define BIT_CLEAR_LTR_IDLE_L(x) ((x) & (~BITS_LTR_IDLE_L))
+#define BIT_GET_LTR_IDLE_L(x)                                                  \
+	(((x) >> BIT_SHIFT_LTR_IDLE_L) & BIT_MASK_LTR_IDLE_L)
+#define BIT_SET_LTR_IDLE_L(x, v) (BIT_CLEAR_LTR_IDLE_L(x) | BIT_LTR_IDLE_L(v))
+
+/* 2 REG_LTR_ACTIVE_LATENCY_V1		(Offset 0x07AC) */
+
+#define BIT_SHIFT_LTR_ACT_L 0
+#define BIT_MASK_LTR_ACT_L 0xffffffffL
+#define BIT_LTR_ACT_L(x) (((x) & BIT_MASK_LTR_ACT_L) << BIT_SHIFT_LTR_ACT_L)
+#define BITS_LTR_ACT_L (BIT_MASK_LTR_ACT_L << BIT_SHIFT_LTR_ACT_L)
+#define BIT_CLEAR_LTR_ACT_L(x) ((x) & (~BITS_LTR_ACT_L))
+#define BIT_GET_LTR_ACT_L(x) (((x) >> BIT_SHIFT_LTR_ACT_L) & BIT_MASK_LTR_ACT_L)
+#define BIT_SET_LTR_ACT_L(x, v) (BIT_CLEAR_LTR_ACT_L(x) | BIT_LTR_ACT_L(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_LTR_ACTIVE_LATENCY_V1		(Offset 0x07AC) */
+
+#define BIT_SHIFT_ANT_ADDR2_1 0
+#define BIT_MASK_ANT_ADDR2_1 0xffffffffL
+#define BIT_ANT_ADDR2_1(x)                                                     \
+	(((x) & BIT_MASK_ANT_ADDR2_1) << BIT_SHIFT_ANT_ADDR2_1)
+#define BITS_ANT_ADDR2_1 (BIT_MASK_ANT_ADDR2_1 << BIT_SHIFT_ANT_ADDR2_1)
+#define BIT_CLEAR_ANT_ADDR2_1(x) ((x) & (~BITS_ANT_ADDR2_1))
+#define BIT_GET_ANT_ADDR2_1(x)                                                 \
+	(((x) >> BIT_SHIFT_ANT_ADDR2_1) & BIT_MASK_ANT_ADDR2_1)
+#define BIT_SET_ANT_ADDR2_1(x, v)                                              \
+	(BIT_CLEAR_ANT_ADDR2_1(x) | BIT_ANT_ADDR2_1(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT)
+
+/* 2 REG_ANTENNA_TRAINING_CONTROL_REGISTER	(Offset 0x07B0) */
+
+#define BIT_APPEND_MACID_IN_RESP_EN BIT(50)
+#define BIT_ADDR2_MATCH_EN BIT(49)
+#define BIT_ANTTRN_EN BIT(48)
+
+#define BIT_SHIFT_TRAIN_STA_ADDR 0
+#define BIT_MASK_TRAIN_STA_ADDR 0xffffffffffffL
+#define BIT_TRAIN_STA_ADDR(x)                                                  \
+	(((x) & BIT_MASK_TRAIN_STA_ADDR) << BIT_SHIFT_TRAIN_STA_ADDR)
+#define BITS_TRAIN_STA_ADDR                                                    \
+	(BIT_MASK_TRAIN_STA_ADDR << BIT_SHIFT_TRAIN_STA_ADDR)
+#define BIT_CLEAR_TRAIN_STA_ADDR(x) ((x) & (~BITS_TRAIN_STA_ADDR))
+#define BIT_GET_TRAIN_STA_ADDR(x)                                              \
+	(((x) >> BIT_SHIFT_TRAIN_STA_ADDR) & BIT_MASK_TRAIN_STA_ADDR)
+#define BIT_SET_TRAIN_STA_ADDR(x, v)                                           \
+	(BIT_CLEAR_TRAIN_STA_ADDR(x) | BIT_TRAIN_STA_ADDR(v))
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_ANTENNA_TRAINING_CONTROL_REGISTER	(Offset 0x07B0) */
+
+#define BIT_SHIFT_TRAIN_STA_ADDR_0 0
+#define BIT_MASK_TRAIN_STA_ADDR_0 0xffffffffL
+#define BIT_TRAIN_STA_ADDR_0(x)                                                \
+	(((x) & BIT_MASK_TRAIN_STA_ADDR_0) << BIT_SHIFT_TRAIN_STA_ADDR_0)
+#define BITS_TRAIN_STA_ADDR_0                                                  \
+	(BIT_MASK_TRAIN_STA_ADDR_0 << BIT_SHIFT_TRAIN_STA_ADDR_0)
+#define BIT_CLEAR_TRAIN_STA_ADDR_0(x) ((x) & (~BITS_TRAIN_STA_ADDR_0))
+#define BIT_GET_TRAIN_STA_ADDR_0(x)                                            \
+	(((x) >> BIT_SHIFT_TRAIN_STA_ADDR_0) & BIT_MASK_TRAIN_STA_ADDR_0)
+#define BIT_SET_TRAIN_STA_ADDR_0(x, v)                                         \
+	(BIT_CLEAR_TRAIN_STA_ADDR_0(x) | BIT_TRAIN_STA_ADDR_0(v))
+
+/* 2 REG_ANTENNA_TRAINING_CONTROL_REGISTER_1 (Offset 0x07B4) */
+
+#define BIT_SHIFT_TRAIN_STA_ADDR_1 0
+#define BIT_MASK_TRAIN_STA_ADDR_1 0xffff
+#define BIT_TRAIN_STA_ADDR_1(x)                                                \
+	(((x) & BIT_MASK_TRAIN_STA_ADDR_1) << BIT_SHIFT_TRAIN_STA_ADDR_1)
+#define BITS_TRAIN_STA_ADDR_1                                                  \
+	(BIT_MASK_TRAIN_STA_ADDR_1 << BIT_SHIFT_TRAIN_STA_ADDR_1)
+#define BIT_CLEAR_TRAIN_STA_ADDR_1(x) ((x) & (~BITS_TRAIN_STA_ADDR_1))
+#define BIT_GET_TRAIN_STA_ADDR_1(x)                                            \
+	(((x) >> BIT_SHIFT_TRAIN_STA_ADDR_1) & BIT_MASK_TRAIN_STA_ADDR_1)
+#define BIT_SET_TRAIN_STA_ADDR_1(x, v)                                         \
+	(BIT_CLEAR_TRAIN_STA_ADDR_1(x) | BIT_TRAIN_STA_ADDR_1(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_SMART_ANT_CTRL			(Offset 0x07B4) */
+
+#define BIT_SHIFT_ANT_ADDR2_2 0
+#define BIT_MASK_ANT_ADDR2_2 0xffff
+#define BIT_ANT_ADDR2_2(x)                                                     \
+	(((x) & BIT_MASK_ANT_ADDR2_2) << BIT_SHIFT_ANT_ADDR2_2)
+#define BITS_ANT_ADDR2_2 (BIT_MASK_ANT_ADDR2_2 << BIT_SHIFT_ANT_ADDR2_2)
+#define BIT_CLEAR_ANT_ADDR2_2(x) ((x) & (~BITS_ANT_ADDR2_2))
+#define BIT_GET_ANT_ADDR2_2(x)                                                 \
+	(((x) >> BIT_SHIFT_ANT_ADDR2_2) & BIT_MASK_ANT_ADDR2_2)
+#define BIT_SET_ANT_ADDR2_2(x, v)                                              \
+	(BIT_CLEAR_ANT_ADDR2_2(x) | BIT_ANT_ADDR2_2(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_WMAC_PKTCNT_RWD			(Offset 0x07B8) */
+
+#define BIT_SHIFT_PKTCNT_BSSIDMAP 4
+#define BIT_MASK_PKTCNT_BSSIDMAP 0xf
+#define BIT_PKTCNT_BSSIDMAP(x)                                                 \
+	(((x) & BIT_MASK_PKTCNT_BSSIDMAP) << BIT_SHIFT_PKTCNT_BSSIDMAP)
+#define BITS_PKTCNT_BSSIDMAP                                                   \
+	(BIT_MASK_PKTCNT_BSSIDMAP << BIT_SHIFT_PKTCNT_BSSIDMAP)
+#define BIT_CLEAR_PKTCNT_BSSIDMAP(x) ((x) & (~BITS_PKTCNT_BSSIDMAP))
+#define BIT_GET_PKTCNT_BSSIDMAP(x)                                             \
+	(((x) >> BIT_SHIFT_PKTCNT_BSSIDMAP) & BIT_MASK_PKTCNT_BSSIDMAP)
+#define BIT_SET_PKTCNT_BSSIDMAP(x, v)                                          \
+	(BIT_CLEAR_PKTCNT_BSSIDMAP(x) | BIT_PKTCNT_BSSIDMAP(v))
+
+#define BIT_PKTCNT_CNTRST BIT(1)
+#define BIT_PKTCNT_CNTEN BIT(0)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_CONTROL_FRAME_REPORT		(Offset 0x07B8) */
+
+#define BIT_SHIFT_CONTROL_FRAME_REPORT 0
+#define BIT_MASK_CONTROL_FRAME_REPORT 0xffffffffL
+#define BIT_CONTROL_FRAME_REPORT(x)                                            \
+	(((x) & BIT_MASK_CONTROL_FRAME_REPORT)                                 \
+	 << BIT_SHIFT_CONTROL_FRAME_REPORT)
+#define BITS_CONTROL_FRAME_REPORT                                              \
+	(BIT_MASK_CONTROL_FRAME_REPORT << BIT_SHIFT_CONTROL_FRAME_REPORT)
+#define BIT_CLEAR_CONTROL_FRAME_REPORT(x) ((x) & (~BITS_CONTROL_FRAME_REPORT))
+#define BIT_GET_CONTROL_FRAME_REPORT(x)                                        \
+	(((x) >> BIT_SHIFT_CONTROL_FRAME_REPORT) &                             \
+	 BIT_MASK_CONTROL_FRAME_REPORT)
+#define BIT_SET_CONTROL_FRAME_REPORT(x, v)                                     \
+	(BIT_CLEAR_CONTROL_FRAME_REPORT(x) | BIT_CONTROL_FRAME_REPORT(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_WMAC_PKTCNT_CTRL			(Offset 0x07BC) */
+
+#define BIT_WMAC_PKTCNT_TRST BIT(9)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_CONTROL_FRAME_CNT_CTRL		(Offset 0x07BC) */
+
+#define BIT_ALLCNTRST BIT(9)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_WMAC_PKTCNT_CTRL			(Offset 0x07BC) */
+
+#define BIT_WMAC_PKTCNT_FEN BIT(8)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_CONTROL_FRAME_CNT_CTRL		(Offset 0x07BC) */
+
+#define BIT__ALLCNTEN BIT(8)
+
+#define BIT_SHIFT_ADDR 4
+#define BIT_MASK_ADDR 0xf
+#define BIT_ADDR(x) (((x) & BIT_MASK_ADDR) << BIT_SHIFT_ADDR)
+#define BITS_ADDR (BIT_MASK_ADDR << BIT_SHIFT_ADDR)
+#define BIT_CLEAR_ADDR(x) ((x) & (~BITS_ADDR))
+#define BIT_GET_ADDR(x) (((x) >> BIT_SHIFT_ADDR) & BIT_MASK_ADDR)
+#define BIT_SET_ADDR(x, v) (BIT_CLEAR_ADDR(x) | BIT_ADDR(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_WMAC_PKTCNT_CTRL			(Offset 0x07BC) */
+
+#define BIT_SHIFT_WMAC_PKTCNT_CFGAD 0
+#define BIT_MASK_WMAC_PKTCNT_CFGAD 0xff
+#define BIT_WMAC_PKTCNT_CFGAD(x)                                               \
+	(((x) & BIT_MASK_WMAC_PKTCNT_CFGAD) << BIT_SHIFT_WMAC_PKTCNT_CFGAD)
+#define BITS_WMAC_PKTCNT_CFGAD                                                 \
+	(BIT_MASK_WMAC_PKTCNT_CFGAD << BIT_SHIFT_WMAC_PKTCNT_CFGAD)
+#define BIT_CLEAR_WMAC_PKTCNT_CFGAD(x) ((x) & (~BITS_WMAC_PKTCNT_CFGAD))
+#define BIT_GET_WMAC_PKTCNT_CFGAD(x)                                           \
+	(((x) >> BIT_SHIFT_WMAC_PKTCNT_CFGAD) & BIT_MASK_WMAC_PKTCNT_CFGAD)
+#define BIT_SET_WMAC_PKTCNT_CFGAD(x, v)                                        \
+	(BIT_CLEAR_WMAC_PKTCNT_CFGAD(x) | BIT_WMAC_PKTCNT_CFGAD(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_CONTROL_FRAME_CNT_CTRL		(Offset 0x07BC) */
+
+#define BIT_SHIFT_CTRL_SEL 0
+#define BIT_MASK_CTRL_SEL 0xf
+#define BIT_CTRL_SEL(x) (((x) & BIT_MASK_CTRL_SEL) << BIT_SHIFT_CTRL_SEL)
+#define BITS_CTRL_SEL (BIT_MASK_CTRL_SEL << BIT_SHIFT_CTRL_SEL)
+#define BIT_CLEAR_CTRL_SEL(x) ((x) & (~BITS_CTRL_SEL))
+#define BIT_GET_CTRL_SEL(x) (((x) >> BIT_SHIFT_CTRL_SEL) & BIT_MASK_CTRL_SEL)
+#define BIT_SET_CTRL_SEL(x, v) (BIT_CLEAR_CTRL_SEL(x) | BIT_CTRL_SEL(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT)
+
+/* 2 REG_IQ_DUMP				(Offset 0x07C0) */
+
+#define BIT_SHIFT_R_WMAC_MATCH_REF_MAC (64 & CPU_OPT_WIDTH)
+#define BIT_MASK_R_WMAC_MATCH_REF_MAC 0xffffffffL
+#define BIT_R_WMAC_MATCH_REF_MAC(x)                                            \
+	(((x) & BIT_MASK_R_WMAC_MATCH_REF_MAC)                                 \
+	 << BIT_SHIFT_R_WMAC_MATCH_REF_MAC)
+#define BITS_R_WMAC_MATCH_REF_MAC                                              \
+	(BIT_MASK_R_WMAC_MATCH_REF_MAC << BIT_SHIFT_R_WMAC_MATCH_REF_MAC)
+#define BIT_CLEAR_R_WMAC_MATCH_REF_MAC(x) ((x) & (~BITS_R_WMAC_MATCH_REF_MAC))
+#define BIT_GET_R_WMAC_MATCH_REF_MAC(x)                                        \
+	(((x) >> BIT_SHIFT_R_WMAC_MATCH_REF_MAC) &                             \
+	 BIT_MASK_R_WMAC_MATCH_REF_MAC)
+#define BIT_SET_R_WMAC_MATCH_REF_MAC(x, v)                                     \
+	(BIT_CLEAR_R_WMAC_MATCH_REF_MAC(x) | BIT_R_WMAC_MATCH_REF_MAC(v))
+
+#define BIT_SHIFT_R_WMAC_RXFIFO_FULL_TH (56 & CPU_OPT_WIDTH)
+#define BIT_MASK_R_WMAC_RXFIFO_FULL_TH 0xff
+#define BIT_R_WMAC_RXFIFO_FULL_TH(x)                                           \
+	(((x) & BIT_MASK_R_WMAC_RXFIFO_FULL_TH)                                \
+	 << BIT_SHIFT_R_WMAC_RXFIFO_FULL_TH)
+#define BITS_R_WMAC_RXFIFO_FULL_TH                                             \
+	(BIT_MASK_R_WMAC_RXFIFO_FULL_TH << BIT_SHIFT_R_WMAC_RXFIFO_FULL_TH)
+#define BIT_CLEAR_R_WMAC_RXFIFO_FULL_TH(x) ((x) & (~BITS_R_WMAC_RXFIFO_FULL_TH))
+#define BIT_GET_R_WMAC_RXFIFO_FULL_TH(x)                                       \
+	(((x) >> BIT_SHIFT_R_WMAC_RXFIFO_FULL_TH) &                            \
+	 BIT_MASK_R_WMAC_RXFIFO_FULL_TH)
+#define BIT_SET_R_WMAC_RXFIFO_FULL_TH(x, v)                                    \
+	(BIT_CLEAR_R_WMAC_RXFIFO_FULL_TH(x) | BIT_R_WMAC_RXFIFO_FULL_TH(v))
+
+#define BIT_R_WMAC_SRCH_TXRPT_TYPE BIT(51)
+#define BIT_R_WMAC_NDP_RST BIT(50)
+#define BIT_R_WMAC_POWINT_EN BIT(49)
+#define BIT_R_WMAC_SRCH_TXRPT_PERPKT BIT(48)
+#define BIT_R_WMAC_SRCH_TXRPT_MID BIT(47)
+#define BIT_R_WMAC_PFIN_TOEN BIT(46)
+#define BIT_R_WMAC_FIL_SECERR BIT(45)
+#define BIT_R_WMAC_FIL_CTLPKTLEN BIT(44)
+#define BIT_R_WMAC_FIL_FCTYPE BIT(43)
+#define BIT_R_WMAC_FIL_FCPROVER BIT(42)
+#define BIT_R_WMAC_PHYSTS_SNIF BIT(41)
+#define BIT_R_WMAC_PHYSTS_PLCP BIT(40)
+#define BIT_R_MAC_TCR_VBONF_RD BIT(39)
+#define BIT_R_WMAC_TCR_MPAR_NDP BIT(38)
+#define BIT_R_WMAC_NDP_FILTER BIT(37)
+#define BIT_R_WMAC_RXLEN_SEL BIT(36)
+#define BIT_R_WMAC_RXLEN_SEL1 BIT(35)
+#define BIT_R_OFDM_FILTER BIT(34)
+#define BIT_R_WMAC_CHK_OFDM_LEN BIT(33)
+
+#define BIT_SHIFT_R_WMAC_MASK_LA_MAC (32 & CPU_OPT_WIDTH)
+#define BIT_MASK_R_WMAC_MASK_LA_MAC 0xffffffffL
+#define BIT_R_WMAC_MASK_LA_MAC(x)                                              \
+	(((x) & BIT_MASK_R_WMAC_MASK_LA_MAC) << BIT_SHIFT_R_WMAC_MASK_LA_MAC)
+#define BITS_R_WMAC_MASK_LA_MAC                                                \
+	(BIT_MASK_R_WMAC_MASK_LA_MAC << BIT_SHIFT_R_WMAC_MASK_LA_MAC)
+#define BIT_CLEAR_R_WMAC_MASK_LA_MAC(x) ((x) & (~BITS_R_WMAC_MASK_LA_MAC))
+#define BIT_GET_R_WMAC_MASK_LA_MAC(x)                                          \
+	(((x) >> BIT_SHIFT_R_WMAC_MASK_LA_MAC) & BIT_MASK_R_WMAC_MASK_LA_MAC)
+#define BIT_SET_R_WMAC_MASK_LA_MAC(x, v)                                       \
+	(BIT_CLEAR_R_WMAC_MASK_LA_MAC(x) | BIT_R_WMAC_MASK_LA_MAC(v))
+
+#define BIT_R_WMAC_CHK_CCK_LEN BIT(32)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_WL2LTECOEX_INDIRECT_ACCESS_CTRL	(Offset 0x07C0) */
+
+#define BIT_LTECOEX_ACCESS_START BIT(31)
+#define BIT_LTECOEX_WRITE_MODE BIT(30)
+#define BIT_LTECOEX_READY_BIT BIT(29)
+
+#define BIT_SHIFT_WRITE_BYTE_EN 16
+#define BIT_MASK_WRITE_BYTE_EN 0xf
+#define BIT_WRITE_BYTE_EN(x)                                                   \
+	(((x) & BIT_MASK_WRITE_BYTE_EN) << BIT_SHIFT_WRITE_BYTE_EN)
+#define BITS_WRITE_BYTE_EN (BIT_MASK_WRITE_BYTE_EN << BIT_SHIFT_WRITE_BYTE_EN)
+#define BIT_CLEAR_WRITE_BYTE_EN(x) ((x) & (~BITS_WRITE_BYTE_EN))
+#define BIT_GET_WRITE_BYTE_EN(x)                                               \
+	(((x) >> BIT_SHIFT_WRITE_BYTE_EN) & BIT_MASK_WRITE_BYTE_EN)
+#define BIT_SET_WRITE_BYTE_EN(x, v)                                            \
+	(BIT_CLEAR_WRITE_BYTE_EN(x) | BIT_WRITE_BYTE_EN(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_IQ_DUMP				(Offset 0x07C0) */
+
+#define BIT_SHIFT_DUMP_OK_ADDR 16
+#define BIT_MASK_DUMP_OK_ADDR 0xffff
+#define BIT_DUMP_OK_ADDR(x)                                                    \
+	(((x) & BIT_MASK_DUMP_OK_ADDR) << BIT_SHIFT_DUMP_OK_ADDR)
+#define BITS_DUMP_OK_ADDR (BIT_MASK_DUMP_OK_ADDR << BIT_SHIFT_DUMP_OK_ADDR)
+#define BIT_CLEAR_DUMP_OK_ADDR(x) ((x) & (~BITS_DUMP_OK_ADDR))
+#define BIT_GET_DUMP_OK_ADDR(x)                                                \
+	(((x) >> BIT_SHIFT_DUMP_OK_ADDR) & BIT_MASK_DUMP_OK_ADDR)
+#define BIT_SET_DUMP_OK_ADDR(x, v)                                             \
+	(BIT_CLEAR_DUMP_OK_ADDR(x) | BIT_DUMP_OK_ADDR(v))
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_IQ_DUMP				(Offset 0x07C0) */
+
+#define BIT_MACDBG_TRIG_IQDUMP BIT(15)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_IQ_DUMP				(Offset 0x07C0) */
+
+#define BIT_SHIFT_R_TRIG_TIME_SEL 8
+#define BIT_MASK_R_TRIG_TIME_SEL 0x7f
+#define BIT_R_TRIG_TIME_SEL(x)                                                 \
+	(((x) & BIT_MASK_R_TRIG_TIME_SEL) << BIT_SHIFT_R_TRIG_TIME_SEL)
+#define BITS_R_TRIG_TIME_SEL                                                   \
+	(BIT_MASK_R_TRIG_TIME_SEL << BIT_SHIFT_R_TRIG_TIME_SEL)
+#define BIT_CLEAR_R_TRIG_TIME_SEL(x) ((x) & (~BITS_R_TRIG_TIME_SEL))
+#define BIT_GET_R_TRIG_TIME_SEL(x)                                             \
+	(((x) >> BIT_SHIFT_R_TRIG_TIME_SEL) & BIT_MASK_R_TRIG_TIME_SEL)
+#define BIT_SET_R_TRIG_TIME_SEL(x, v)                                          \
+	(BIT_CLEAR_R_TRIG_TIME_SEL(x) | BIT_R_TRIG_TIME_SEL(v))
+
+#define BIT_SHIFT_R_MAC_TRIG_SEL 6
+#define BIT_MASK_R_MAC_TRIG_SEL 0x3
+#define BIT_R_MAC_TRIG_SEL(x)                                                  \
+	(((x) & BIT_MASK_R_MAC_TRIG_SEL) << BIT_SHIFT_R_MAC_TRIG_SEL)
+#define BITS_R_MAC_TRIG_SEL                                                    \
+	(BIT_MASK_R_MAC_TRIG_SEL << BIT_SHIFT_R_MAC_TRIG_SEL)
+#define BIT_CLEAR_R_MAC_TRIG_SEL(x) ((x) & (~BITS_R_MAC_TRIG_SEL))
+#define BIT_GET_R_MAC_TRIG_SEL(x)                                              \
+	(((x) >> BIT_SHIFT_R_MAC_TRIG_SEL) & BIT_MASK_R_MAC_TRIG_SEL)
+#define BIT_SET_R_MAC_TRIG_SEL(x, v)                                           \
+	(BIT_CLEAR_R_MAC_TRIG_SEL(x) | BIT_R_MAC_TRIG_SEL(v))
+
+#define BIT_MAC_TRIG_REG BIT(5)
+
+#define BIT_SHIFT_R_LEVEL_PULSE_SEL 3
+#define BIT_MASK_R_LEVEL_PULSE_SEL 0x3
+#define BIT_R_LEVEL_PULSE_SEL(x)                                               \
+	(((x) & BIT_MASK_R_LEVEL_PULSE_SEL) << BIT_SHIFT_R_LEVEL_PULSE_SEL)
+#define BITS_R_LEVEL_PULSE_SEL                                                 \
+	(BIT_MASK_R_LEVEL_PULSE_SEL << BIT_SHIFT_R_LEVEL_PULSE_SEL)
+#define BIT_CLEAR_R_LEVEL_PULSE_SEL(x) ((x) & (~BITS_R_LEVEL_PULSE_SEL))
+#define BIT_GET_R_LEVEL_PULSE_SEL(x)                                           \
+	(((x) >> BIT_SHIFT_R_LEVEL_PULSE_SEL) & BIT_MASK_R_LEVEL_PULSE_SEL)
+#define BIT_SET_R_LEVEL_PULSE_SEL(x, v)                                        \
+	(BIT_CLEAR_R_LEVEL_PULSE_SEL(x) | BIT_R_LEVEL_PULSE_SEL(v))
+
+#define BIT_EN_LA_MAC BIT(2)
+#define BIT_R_EN_IQDUMP BIT(1)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_WL2LTECOEX_INDIRECT_ACCESS_CTRL	(Offset 0x07C0) */
+
+#define BIT_SHIFT_LTECOEX_REG_ADDR 0
+#define BIT_MASK_LTECOEX_REG_ADDR 0xffff
+#define BIT_LTECOEX_REG_ADDR(x)                                                \
+	(((x) & BIT_MASK_LTECOEX_REG_ADDR) << BIT_SHIFT_LTECOEX_REG_ADDR)
+#define BITS_LTECOEX_REG_ADDR                                                  \
+	(BIT_MASK_LTECOEX_REG_ADDR << BIT_SHIFT_LTECOEX_REG_ADDR)
+#define BIT_CLEAR_LTECOEX_REG_ADDR(x) ((x) & (~BITS_LTECOEX_REG_ADDR))
+#define BIT_GET_LTECOEX_REG_ADDR(x)                                            \
+	(((x) >> BIT_SHIFT_LTECOEX_REG_ADDR) & BIT_MASK_LTECOEX_REG_ADDR)
+#define BIT_SET_LTECOEX_REG_ADDR(x, v)                                         \
+	(BIT_CLEAR_LTECOEX_REG_ADDR(x) | BIT_LTECOEX_REG_ADDR(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_IQ_DUMP				(Offset 0x07C0) */
+
+#define BIT_R_IQDATA_DUMP BIT(0)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_WL2LTECOEX_INDIRECT_ACCESS_WRITE_DATA (Offset 0x07C4) */
+
+#define BIT_SHIFT_LTECOEX_W_DATA 0
+#define BIT_MASK_LTECOEX_W_DATA 0xffffffffL
+#define BIT_LTECOEX_W_DATA(x)                                                  \
+	(((x) & BIT_MASK_LTECOEX_W_DATA) << BIT_SHIFT_LTECOEX_W_DATA)
+#define BITS_LTECOEX_W_DATA                                                    \
+	(BIT_MASK_LTECOEX_W_DATA << BIT_SHIFT_LTECOEX_W_DATA)
+#define BIT_CLEAR_LTECOEX_W_DATA(x) ((x) & (~BITS_LTECOEX_W_DATA))
+#define BIT_GET_LTECOEX_W_DATA(x)                                              \
+	(((x) >> BIT_SHIFT_LTECOEX_W_DATA) & BIT_MASK_LTECOEX_W_DATA)
+#define BIT_SET_LTECOEX_W_DATA(x, v)                                           \
+	(BIT_CLEAR_LTECOEX_W_DATA(x) | BIT_LTECOEX_W_DATA(v))
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_IQ_DUMP_1				(Offset 0x07C4) */
+
+#define BIT_SHIFT_R_WMAC_MASK_LA_MAC_1 0
+#define BIT_MASK_R_WMAC_MASK_LA_MAC_1 0xffffffffL
+#define BIT_R_WMAC_MASK_LA_MAC_1(x)                                            \
+	(((x) & BIT_MASK_R_WMAC_MASK_LA_MAC_1)                                 \
+	 << BIT_SHIFT_R_WMAC_MASK_LA_MAC_1)
+#define BITS_R_WMAC_MASK_LA_MAC_1                                              \
+	(BIT_MASK_R_WMAC_MASK_LA_MAC_1 << BIT_SHIFT_R_WMAC_MASK_LA_MAC_1)
+#define BIT_CLEAR_R_WMAC_MASK_LA_MAC_1(x) ((x) & (~BITS_R_WMAC_MASK_LA_MAC_1))
+#define BIT_GET_R_WMAC_MASK_LA_MAC_1(x)                                        \
+	(((x) >> BIT_SHIFT_R_WMAC_MASK_LA_MAC_1) &                             \
+	 BIT_MASK_R_WMAC_MASK_LA_MAC_1)
+#define BIT_SET_R_WMAC_MASK_LA_MAC_1(x, v)                                     \
+	(BIT_CLEAR_R_WMAC_MASK_LA_MAC_1(x) | BIT_R_WMAC_MASK_LA_MAC_1(v))
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_WL2LTECOEX_INDIRECT_ACCESS_READ_DATA (Offset 0x07C8) */
+
+#define BIT_SHIFT_LTECOEX_R_DATA 0
+#define BIT_MASK_LTECOEX_R_DATA 0xffffffffL
+#define BIT_LTECOEX_R_DATA(x)                                                  \
+	(((x) & BIT_MASK_LTECOEX_R_DATA) << BIT_SHIFT_LTECOEX_R_DATA)
+#define BITS_LTECOEX_R_DATA                                                    \
+	(BIT_MASK_LTECOEX_R_DATA << BIT_SHIFT_LTECOEX_R_DATA)
+#define BIT_CLEAR_LTECOEX_R_DATA(x) ((x) & (~BITS_LTECOEX_R_DATA))
+#define BIT_GET_LTECOEX_R_DATA(x)                                              \
+	(((x) >> BIT_SHIFT_LTECOEX_R_DATA) & BIT_MASK_LTECOEX_R_DATA)
+#define BIT_SET_LTECOEX_R_DATA(x, v)                                           \
+	(BIT_CLEAR_LTECOEX_R_DATA(x) | BIT_LTECOEX_R_DATA(v))
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_IQ_DUMP_2				(Offset 0x07C8) */
+
+#define BIT_SHIFT_R_WMAC_MATCH_REF_MAC_2 0
+#define BIT_MASK_R_WMAC_MATCH_REF_MAC_2 0xffffffffL
+#define BIT_R_WMAC_MATCH_REF_MAC_2(x)                                          \
+	(((x) & BIT_MASK_R_WMAC_MATCH_REF_MAC_2)                               \
+	 << BIT_SHIFT_R_WMAC_MATCH_REF_MAC_2)
+#define BITS_R_WMAC_MATCH_REF_MAC_2                                            \
+	(BIT_MASK_R_WMAC_MATCH_REF_MAC_2 << BIT_SHIFT_R_WMAC_MATCH_REF_MAC_2)
+#define BIT_CLEAR_R_WMAC_MATCH_REF_MAC_2(x)                                    \
+	((x) & (~BITS_R_WMAC_MATCH_REF_MAC_2))
+#define BIT_GET_R_WMAC_MATCH_REF_MAC_2(x)                                      \
+	(((x) >> BIT_SHIFT_R_WMAC_MATCH_REF_MAC_2) &                           \
+	 BIT_MASK_R_WMAC_MATCH_REF_MAC_2)
+#define BIT_SET_R_WMAC_MATCH_REF_MAC_2(x, v)                                   \
+	(BIT_CLEAR_R_WMAC_MATCH_REF_MAC_2(x) | BIT_R_WMAC_MATCH_REF_MAC_2(v))
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_WMAC_FTM_CTL			(Offset 0x07CC) */
+
+#define BIT_SHIFT_RX_STOPRXDMA_RXPOINT 16
+#define BIT_MASK_RX_STOPRXDMA_RXPOINT 0xffff
+#define BIT_RX_STOPRXDMA_RXPOINT(x)                                            \
+	(((x) & BIT_MASK_RX_STOPRXDMA_RXPOINT)                                 \
+	 << BIT_SHIFT_RX_STOPRXDMA_RXPOINT)
+#define BITS_RX_STOPRXDMA_RXPOINT                                              \
+	(BIT_MASK_RX_STOPRXDMA_RXPOINT << BIT_SHIFT_RX_STOPRXDMA_RXPOINT)
+#define BIT_CLEAR_RX_STOPRXDMA_RXPOINT(x) ((x) & (~BITS_RX_STOPRXDMA_RXPOINT))
+#define BIT_GET_RX_STOPRXDMA_RXPOINT(x)                                        \
+	(((x) >> BIT_SHIFT_RX_STOPRXDMA_RXPOINT) &                             \
+	 BIT_MASK_RX_STOPRXDMA_RXPOINT)
+#define BIT_SET_RX_STOPRXDMA_RXPOINT(x, v)                                     \
+	(BIT_CLEAR_RX_STOPRXDMA_RXPOINT(x) | BIT_RX_STOPRXDMA_RXPOINT(v))
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_WMAC_FTM_CTL			(Offset 0x07CC) */
+
+#define BIT_RXFTM_TXACK_SC BIT(6)
+#define BIT_RXFTM_TXACK_BW BIT(5)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_WMAC_FTM_CTL			(Offset 0x07CC) */
+
+#define BIT_RXFTM_STOPRXDMAEN BIT(4)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_WMAC_FTM_CTL			(Offset 0x07CC) */
+
+#define BIT_RXFTM_EN BIT(3)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_WMAC_FTM_CTL			(Offset 0x07CC) */
+
+#define BIT_RXFTMREQ_STOPRXDMAEN BIT(2)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_WMAC_FTM_CTL			(Offset 0x07CC) */
+
+#define BIT_RXFTMREQ_BYDRV BIT(2)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_WMAC_FTM_CTL			(Offset 0x07CC) */
+
+#define BIT_RXFTMREQ_EN BIT(1)
+#define BIT_FTM_EN BIT(0)
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+/* 2 REG_IQ_DUMP_EXT				(Offset 0x07CF) */
+
+#define BIT_SHIFT_R_LA_MAC_TIMEOUT_UNIT_SEL 10
+#define BIT_MASK_R_LA_MAC_TIMEOUT_UNIT_SEL 0x3
+#define BIT_R_LA_MAC_TIMEOUT_UNIT_SEL(x)                                       \
+	(((x) & BIT_MASK_R_LA_MAC_TIMEOUT_UNIT_SEL)                            \
+	 << BIT_SHIFT_R_LA_MAC_TIMEOUT_UNIT_SEL)
+#define BITS_R_LA_MAC_TIMEOUT_UNIT_SEL                                         \
+	(BIT_MASK_R_LA_MAC_TIMEOUT_UNIT_SEL                                    \
+	 << BIT_SHIFT_R_LA_MAC_TIMEOUT_UNIT_SEL)
+#define BIT_CLEAR_R_LA_MAC_TIMEOUT_UNIT_SEL(x)                                 \
+	((x) & (~BITS_R_LA_MAC_TIMEOUT_UNIT_SEL))
+#define BIT_GET_R_LA_MAC_TIMEOUT_UNIT_SEL(x)                                   \
+	(((x) >> BIT_SHIFT_R_LA_MAC_TIMEOUT_UNIT_SEL) &                        \
+	 BIT_MASK_R_LA_MAC_TIMEOUT_UNIT_SEL)
+#define BIT_SET_R_LA_MAC_TIMEOUT_UNIT_SEL(x, v)                                \
+	(BIT_CLEAR_R_LA_MAC_TIMEOUT_UNIT_SEL(x) |                              \
+	 BIT_R_LA_MAC_TIMEOUT_UNIT_SEL(v))
+
+#define BIT_SHIFT_R_LA_MAC_TIMEOUT_VALUE 4
+#define BIT_MASK_R_LA_MAC_TIMEOUT_VALUE 0x3f
+#define BIT_R_LA_MAC_TIMEOUT_VALUE(x)                                          \
+	(((x) & BIT_MASK_R_LA_MAC_TIMEOUT_VALUE)                               \
+	 << BIT_SHIFT_R_LA_MAC_TIMEOUT_VALUE)
+#define BITS_R_LA_MAC_TIMEOUT_VALUE                                            \
+	(BIT_MASK_R_LA_MAC_TIMEOUT_VALUE << BIT_SHIFT_R_LA_MAC_TIMEOUT_VALUE)
+#define BIT_CLEAR_R_LA_MAC_TIMEOUT_VALUE(x)                                    \
+	((x) & (~BITS_R_LA_MAC_TIMEOUT_VALUE))
+#define BIT_GET_R_LA_MAC_TIMEOUT_VALUE(x)                                      \
+	(((x) >> BIT_SHIFT_R_LA_MAC_TIMEOUT_VALUE) &                           \
+	 BIT_MASK_R_LA_MAC_TIMEOUT_VALUE)
+#define BIT_SET_R_LA_MAC_TIMEOUT_VALUE(x, v)                                   \
+	(BIT_CLEAR_R_LA_MAC_TIMEOUT_VALUE(x) | BIT_R_LA_MAC_TIMEOUT_VALUE(v))
+
+#define BIT_R_LEVEL_PULSE_SEL_EXTL BIT(3)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_IQ_DUMP_EXT				(Offset 0x07CF) */
+
+#define BIT_SHIFT_R_TIME_UNIT_SEL 0
+#define BIT_MASK_R_TIME_UNIT_SEL 0x7
+#define BIT_R_TIME_UNIT_SEL(x)                                                 \
+	(((x) & BIT_MASK_R_TIME_UNIT_SEL) << BIT_SHIFT_R_TIME_UNIT_SEL)
+#define BITS_R_TIME_UNIT_SEL                                                   \
+	(BIT_MASK_R_TIME_UNIT_SEL << BIT_SHIFT_R_TIME_UNIT_SEL)
+#define BIT_CLEAR_R_TIME_UNIT_SEL(x) ((x) & (~BITS_R_TIME_UNIT_SEL))
+#define BIT_GET_R_TIME_UNIT_SEL(x)                                             \
+	(((x) >> BIT_SHIFT_R_TIME_UNIT_SEL) & BIT_MASK_R_TIME_UNIT_SEL)
+#define BIT_SET_R_TIME_UNIT_SEL(x, v)                                          \
+	(BIT_CLEAR_R_TIME_UNIT_SEL(x) | BIT_R_TIME_UNIT_SEL(v))
+
+#endif
+
+#if (HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_OFDM_CCK_LEN_MASK			(Offset 0x07D0) */
+
+#define BIT_MICICV_CLR BIT(86)
+#define BIT_MPDU_RDY_SET BIT(85)
+#define BIT_CLR_SEC_TYPE BIT(84)
+#define BIT_NEWPKT_IN BIT(83)
+#define BIT_FCS_END BIT(82)
+#define BIT_DEL_MESH_TYPE BIT(81)
+#define BIT_MASK_MESH_TYPE BIT(80)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_WMAC_OPTION_FUNCTION_1		(Offset 0x07D4) */
+
+#define BIT_SHIFT_R_WMAC_RXFIFO_FULL_TH_1 24
+#define BIT_MASK_R_WMAC_RXFIFO_FULL_TH_1 0xff
+#define BIT_R_WMAC_RXFIFO_FULL_TH_1(x)                                         \
+	(((x) & BIT_MASK_R_WMAC_RXFIFO_FULL_TH_1)                              \
+	 << BIT_SHIFT_R_WMAC_RXFIFO_FULL_TH_1)
+#define BITS_R_WMAC_RXFIFO_FULL_TH_1                                           \
+	(BIT_MASK_R_WMAC_RXFIFO_FULL_TH_1 << BIT_SHIFT_R_WMAC_RXFIFO_FULL_TH_1)
+#define BIT_CLEAR_R_WMAC_RXFIFO_FULL_TH_1(x)                                   \
+	((x) & (~BITS_R_WMAC_RXFIFO_FULL_TH_1))
+#define BIT_GET_R_WMAC_RXFIFO_FULL_TH_1(x)                                     \
+	(((x) >> BIT_SHIFT_R_WMAC_RXFIFO_FULL_TH_1) &                          \
+	 BIT_MASK_R_WMAC_RXFIFO_FULL_TH_1)
+#define BIT_SET_R_WMAC_RXFIFO_FULL_TH_1(x, v)                                  \
+	(BIT_CLEAR_R_WMAC_RXFIFO_FULL_TH_1(x) | BIT_R_WMAC_RXFIFO_FULL_TH_1(v))
+
+#define BIT_R_WMAC_RX_SYNCFIFO_SYNC_1 BIT(23)
+#define BIT_R_WMAC_RXRST_DLY_1 BIT(22)
+#define BIT_R_WMAC_SRCH_TXRPT_REF_DROP_1 BIT(21)
+#define BIT_R_WMAC_SRCH_TXRPT_UA1_1 BIT(20)
+#define BIT_R_WMAC_SRCH_TXRPT_TYPE_1 BIT(19)
+#define BIT_R_WMAC_NDP_RST_1 BIT(18)
+#define BIT_R_WMAC_POWINT_EN_1 BIT(17)
+#define BIT_R_WMAC_SRCH_TXRPT_PERPKT_1 BIT(16)
+#define BIT_R_WMAC_SRCH_TXRPT_MID_1 BIT(15)
+#define BIT_R_WMAC_PFIN_TOEN_1 BIT(14)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_FA_FILTER1				(Offset 0x07D4) */
+
+#define BIT_R_WMAC_FIL_SECERR_V1 BIT(13)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_WMAC_OPTION_FUNCTION_1		(Offset 0x07D4) */
+
+#define BIT_R_WMAC_FIL_SECERR_1 BIT(13)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_FA_FILTER1				(Offset 0x07D4) */
+
+#define BIT_R_WMAC_FIL_CTLPKTLEN_V1 BIT(12)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_WMAC_OPTION_FUNCTION_1		(Offset 0x07D4) */
+
+#define BIT_R_WMAC_FIL_CTLPKTLEN_1 BIT(12)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_FA_FILTER1				(Offset 0x07D4) */
+
+#define BIT_R_WMAC_FIL_FCTYPE_V1 BIT(11)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_WMAC_OPTION_FUNCTION_1		(Offset 0x07D4) */
+
+#define BIT_R_WMAC_FIL_FCTYPE_1 BIT(11)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_FA_FILTER1				(Offset 0x07D4) */
+
+#define BIT_R_WMAC_FIL_FCPROVER_V1 BIT(10)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_WMAC_OPTION_FUNCTION_1		(Offset 0x07D4) */
+
+#define BIT_R_WMAC_FIL_FCPROVER_1 BIT(10)
+#define BIT_R_WMAC_PHYSTS_SNIF_1 BIT(9)
+#define BIT_R_WMAC_PHYSTS_PLCP_1 BIT(8)
+#define BIT_R_MAC_TCR_VBONF_RD_1 BIT(7)
+#define BIT_R_WMAC_TCR_MPAR_NDP_1 BIT(6)
+#define BIT_R_WMAC_NDP_FILTER_1 BIT(5)
+#define BIT_R_WMAC_RXLEN_SEL_1 BIT(4)
+#define BIT_R_WMAC_RXLEN_SEL1_1 BIT(3)
+#define BIT_R_OFDM_FILTER_1 BIT(2)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_FA_FILTER1				(Offset 0x07D4) */
+
+#define BIT_R_WMAC_CHK_OFDM_LEN_V1 BIT(1)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_WMAC_OPTION_FUNCTION_1		(Offset 0x07D4) */
+
+#define BIT_R_WMAC_CHK_OFDM_LEN_1 BIT(1)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_FA_FILTER1				(Offset 0x07D4) */
+
+#define BIT_R_WMAC_CHK_CCK_LEN_V1 BIT(0)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_WMAC_OPTION_FUNCTION_1		(Offset 0x07D4) */
+
+#define BIT_R_WMAC_CHK_CCK_LEN_1 BIT(0)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_FA_FILTER2				(Offset 0x07D8) */
+
+#define BIT_DEL_MESH_TYPE_V1 BIT(17)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_WMAC_OPTION_FUNCTION_2		(Offset 0x07D8) */
+
+#define BIT_SHIFT_R_WMAC_RX_FIL_LEN_2 0
+#define BIT_MASK_R_WMAC_RX_FIL_LEN_2 0xffff
+#define BIT_R_WMAC_RX_FIL_LEN_2(x)                                             \
+	(((x) & BIT_MASK_R_WMAC_RX_FIL_LEN_2) << BIT_SHIFT_R_WMAC_RX_FIL_LEN_2)
+#define BITS_R_WMAC_RX_FIL_LEN_2                                               \
+	(BIT_MASK_R_WMAC_RX_FIL_LEN_2 << BIT_SHIFT_R_WMAC_RX_FIL_LEN_2)
+#define BIT_CLEAR_R_WMAC_RX_FIL_LEN_2(x) ((x) & (~BITS_R_WMAC_RX_FIL_LEN_2))
+#define BIT_GET_R_WMAC_RX_FIL_LEN_2(x)                                         \
+	(((x) >> BIT_SHIFT_R_WMAC_RX_FIL_LEN_2) & BIT_MASK_R_WMAC_RX_FIL_LEN_2)
+#define BIT_SET_R_WMAC_RX_FIL_LEN_2(x, v)                                      \
+	(BIT_CLEAR_R_WMAC_RX_FIL_LEN_2(x) | BIT_R_WMAC_RX_FIL_LEN_2(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_RX_FILTER_FUNCTION			(Offset 0x07DA) */
+
+#define BIT_R_WMAC_RXHANG_EN BIT(15)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_RX_FILTER_FUNCTION			(Offset 0x07DA) */
+
+#define BIT_RXHANG_EN BIT(15)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_RX_FILTER_FUNCTION			(Offset 0x07DA) */
+
+#define BIT_R_WMAC_MHRDDY_LATCH BIT(14)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_RX_FILTER_FUNCTION			(Offset 0x07DA) */
+
+#define BIT_R_MHRDDY_CLR BIT(13)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_RX_FILTER_FUNCTION			(Offset 0x07DA) */
+
+#define BIT_R_WMAC_MHRDDY_CLR BIT(13)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_RX_FILTER_FUNCTION			(Offset 0x07DA) */
+
+#define BIT_R_RXPKTCTL_FSM_BASED_MPDURDY1 BIT(12)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_RX_FILTER_FUNCTION			(Offset 0x07DA) */
+
+#define BIT_R_WMAC_DIS_VHT_PLCP_CHK_MU BIT(11)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_RX_FILTER_FUNCTION			(Offset 0x07DA) */
+
+#define BIT_WMAC_DIS_VHT_PLCP_CHK_MU BIT(11)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_RX_FILTER_FUNCTION			(Offset 0x07DA) */
+
+#define BIT_R_CHK_DELIMIT_LEN BIT(10)
+#define BIT_R_REAPTER_ADDR_MATCH BIT(9)
+#define BIT_R_RXPKTCTL_FSM_BASED_MPDURDY BIT(8)
+#define BIT_R_LATCH_MACHRDY BIT(7)
+#define BIT_R_WMAC_RXFIL_REND BIT(6)
+#define BIT_R_WMAC_MPDURDY_CLR BIT(5)
+#define BIT_R_WMAC_CLRRXSEC BIT(4)
+#define BIT_R_WMAC_RXFIL_RDEL BIT(3)
+#define BIT_R_WMAC_RXFIL_FCSE BIT(2)
+#define BIT_R_WMAC_RXFIL_MESH_DEL BIT(1)
+#define BIT_R_WMAC_RXFIL_MASKM BIT(0)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_NDP_SIG				(Offset 0x07E0) */
+
+#define BIT_SHIFT_R_WMAC_TXNDP_SIGB 0
+#define BIT_MASK_R_WMAC_TXNDP_SIGB 0x1fffff
+#define BIT_R_WMAC_TXNDP_SIGB(x)                                               \
+	(((x) & BIT_MASK_R_WMAC_TXNDP_SIGB) << BIT_SHIFT_R_WMAC_TXNDP_SIGB)
+#define BITS_R_WMAC_TXNDP_SIGB                                                 \
+	(BIT_MASK_R_WMAC_TXNDP_SIGB << BIT_SHIFT_R_WMAC_TXNDP_SIGB)
+#define BIT_CLEAR_R_WMAC_TXNDP_SIGB(x) ((x) & (~BITS_R_WMAC_TXNDP_SIGB))
+#define BIT_GET_R_WMAC_TXNDP_SIGB(x)                                           \
+	(((x) >> BIT_SHIFT_R_WMAC_TXNDP_SIGB) & BIT_MASK_R_WMAC_TXNDP_SIGB)
+#define BIT_SET_R_WMAC_TXNDP_SIGB(x, v)                                        \
+	(BIT_CLEAR_R_WMAC_TXNDP_SIGB(x) | BIT_R_WMAC_TXNDP_SIGB(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT)
+
+/* 2 REG_TXCMD_INFO_FOR_RSP_PKT		(Offset 0x07E4) */
+
+#define BIT_SHIFT_R_MAC_DEBUG (32 & CPU_OPT_WIDTH)
+#define BIT_MASK_R_MAC_DEBUG 0xffffffffL
+#define BIT_R_MAC_DEBUG(x)                                                     \
+	(((x) & BIT_MASK_R_MAC_DEBUG) << BIT_SHIFT_R_MAC_DEBUG)
+#define BITS_R_MAC_DEBUG (BIT_MASK_R_MAC_DEBUG << BIT_SHIFT_R_MAC_DEBUG)
+#define BIT_CLEAR_R_MAC_DEBUG(x) ((x) & (~BITS_R_MAC_DEBUG))
+#define BIT_GET_R_MAC_DEBUG(x)                                                 \
+	(((x) >> BIT_SHIFT_R_MAC_DEBUG) & BIT_MASK_R_MAC_DEBUG)
+#define BIT_SET_R_MAC_DEBUG(x, v)                                              \
+	(BIT_CLEAR_R_MAC_DEBUG(x) | BIT_R_MAC_DEBUG(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_TXCMD_INFO_FOR_RSP_PKT		(Offset 0x07E4) */
+
+#define BIT_SHIFT_R_MAC_DBG_SHIFT 8
+#define BIT_MASK_R_MAC_DBG_SHIFT 0x7
+#define BIT_R_MAC_DBG_SHIFT(x)                                                 \
+	(((x) & BIT_MASK_R_MAC_DBG_SHIFT) << BIT_SHIFT_R_MAC_DBG_SHIFT)
+#define BITS_R_MAC_DBG_SHIFT                                                   \
+	(BIT_MASK_R_MAC_DBG_SHIFT << BIT_SHIFT_R_MAC_DBG_SHIFT)
+#define BIT_CLEAR_R_MAC_DBG_SHIFT(x) ((x) & (~BITS_R_MAC_DBG_SHIFT))
+#define BIT_GET_R_MAC_DBG_SHIFT(x)                                             \
+	(((x) >> BIT_SHIFT_R_MAC_DBG_SHIFT) & BIT_MASK_R_MAC_DBG_SHIFT)
+#define BIT_SET_R_MAC_DBG_SHIFT(x, v)                                          \
+	(BIT_CLEAR_R_MAC_DBG_SHIFT(x) | BIT_R_MAC_DBG_SHIFT(v))
+
+#define BIT_SHIFT_R_MAC_DBG_SEL 0
+#define BIT_MASK_R_MAC_DBG_SEL 0x3
+#define BIT_R_MAC_DBG_SEL(x)                                                   \
+	(((x) & BIT_MASK_R_MAC_DBG_SEL) << BIT_SHIFT_R_MAC_DBG_SEL)
+#define BITS_R_MAC_DBG_SEL (BIT_MASK_R_MAC_DBG_SEL << BIT_SHIFT_R_MAC_DBG_SEL)
+#define BIT_CLEAR_R_MAC_DBG_SEL(x) ((x) & (~BITS_R_MAC_DBG_SEL))
+#define BIT_GET_R_MAC_DBG_SEL(x)                                               \
+	(((x) >> BIT_SHIFT_R_MAC_DBG_SEL) & BIT_MASK_R_MAC_DBG_SEL)
+#define BIT_SET_R_MAC_DBG_SEL(x, v)                                            \
+	(BIT_CLEAR_R_MAC_DBG_SEL(x) | BIT_R_MAC_DBG_SEL(v))
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_TXCMD_INFO_FOR_RSP_PKT_1		(Offset 0x07E8) */
+
+#define BIT_SHIFT_R_MAC_DEBUG_1 0
+#define BIT_MASK_R_MAC_DEBUG_1 0xffffffffL
+#define BIT_R_MAC_DEBUG_1(x)                                                   \
+	(((x) & BIT_MASK_R_MAC_DEBUG_1) << BIT_SHIFT_R_MAC_DEBUG_1)
+#define BITS_R_MAC_DEBUG_1 (BIT_MASK_R_MAC_DEBUG_1 << BIT_SHIFT_R_MAC_DEBUG_1)
+#define BIT_CLEAR_R_MAC_DEBUG_1(x) ((x) & (~BITS_R_MAC_DEBUG_1))
+#define BIT_GET_R_MAC_DEBUG_1(x)                                               \
+	(((x) >> BIT_SHIFT_R_MAC_DEBUG_1) & BIT_MASK_R_MAC_DEBUG_1)
+#define BIT_SET_R_MAC_DEBUG_1(x, v)                                            \
+	(BIT_CLEAR_R_MAC_DEBUG_1(x) | BIT_R_MAC_DEBUG_1(v))
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_WSEC_OPTION				(Offset 0x07EC) */
+
+#define BIT_RXDEC_BM_MGNT BIT(22)
+#define BIT_TXENC_BM_MGNT BIT(21)
+#define BIT_RXDEC_UNI_MGNT BIT(20)
+#define BIT_TXENC_UNI_MGNT BIT(19)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_SEC_OPT_V2				(Offset 0x07EC) */
+
+#define BIT_MASK_IV BIT(18)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_WSEC_OPTION				(Offset 0x07EC) */
+
+#define BIT_WMAC_SEC_MASKIV BIT(18)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_SEC_OPT_V2				(Offset 0x07EC) */
+
+#define BIT_EIVL_ENDIAN BIT(17)
+#define BIT_EIVH_ENDIAN BIT(16)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_WSEC_OPTION				(Offset 0x07EC) */
+
+#define BIT_SHIFT_WMAC_SEC_PN_SEL 16
+#define BIT_MASK_WMAC_SEC_PN_SEL 0x3
+#define BIT_WMAC_SEC_PN_SEL(x)                                                 \
+	(((x) & BIT_MASK_WMAC_SEC_PN_SEL) << BIT_SHIFT_WMAC_SEC_PN_SEL)
+#define BITS_WMAC_SEC_PN_SEL                                                   \
+	(BIT_MASK_WMAC_SEC_PN_SEL << BIT_SHIFT_WMAC_SEC_PN_SEL)
+#define BIT_CLEAR_WMAC_SEC_PN_SEL(x) ((x) & (~BITS_WMAC_SEC_PN_SEL))
+#define BIT_GET_WMAC_SEC_PN_SEL(x)                                             \
+	(((x) >> BIT_SHIFT_WMAC_SEC_PN_SEL) & BIT_MASK_WMAC_SEC_PN_SEL)
+#define BIT_SET_WMAC_SEC_PN_SEL(x, v)                                          \
+	(BIT_CLEAR_WMAC_SEC_PN_SEL(x) | BIT_WMAC_SEC_PN_SEL(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_WSEC_OPTION				(Offset 0x07EC) */
+
+#define BIT_SHIFT_BT_TIME_CNT 0
+#define BIT_MASK_BT_TIME_CNT 0xff
+#define BIT_BT_TIME_CNT(x)                                                     \
+	(((x) & BIT_MASK_BT_TIME_CNT) << BIT_SHIFT_BT_TIME_CNT)
+#define BITS_BT_TIME_CNT (BIT_MASK_BT_TIME_CNT << BIT_SHIFT_BT_TIME_CNT)
+#define BIT_CLEAR_BT_TIME_CNT(x) ((x) & (~BITS_BT_TIME_CNT))
+#define BIT_GET_BT_TIME_CNT(x)                                                 \
+	(((x) >> BIT_SHIFT_BT_TIME_CNT) & BIT_MASK_BT_TIME_CNT)
+#define BIT_SET_BT_TIME_CNT(x, v)                                              \
+	(BIT_CLEAR_BT_TIME_CNT(x) | BIT_BT_TIME_CNT(v))
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+/* 2 REG_RTS_ADDRESS_0			(Offset 0x07F0) */
+
+#define BIT_SHIFT_R_WMAC_RTS_ADDR0 0
+#define BIT_MASK_R_WMAC_RTS_ADDR0 0xffffffffffffL
+#define BIT_R_WMAC_RTS_ADDR0(x)                                                \
+	(((x) & BIT_MASK_R_WMAC_RTS_ADDR0) << BIT_SHIFT_R_WMAC_RTS_ADDR0)
+#define BITS_R_WMAC_RTS_ADDR0                                                  \
+	(BIT_MASK_R_WMAC_RTS_ADDR0 << BIT_SHIFT_R_WMAC_RTS_ADDR0)
+#define BIT_CLEAR_R_WMAC_RTS_ADDR0(x) ((x) & (~BITS_R_WMAC_RTS_ADDR0))
+#define BIT_GET_R_WMAC_RTS_ADDR0(x)                                            \
+	(((x) >> BIT_SHIFT_R_WMAC_RTS_ADDR0) & BIT_MASK_R_WMAC_RTS_ADDR0)
+#define BIT_SET_R_WMAC_RTS_ADDR0(x, v)                                         \
+	(BIT_CLEAR_R_WMAC_RTS_ADDR0(x) | BIT_R_WMAC_RTS_ADDR0(v))
+
+#endif
+
+#if (HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_RTS_ADDR0				(Offset 0x07F0) */
+
+#define BIT_SHIFT_RTS_ADDR0 0
+#define BIT_MASK_RTS_ADDR0 0xffffffffffffL
+#define BIT_RTS_ADDR0(x) (((x) & BIT_MASK_RTS_ADDR0) << BIT_SHIFT_RTS_ADDR0)
+#define BITS_RTS_ADDR0 (BIT_MASK_RTS_ADDR0 << BIT_SHIFT_RTS_ADDR0)
+#define BIT_CLEAR_RTS_ADDR0(x) ((x) & (~BITS_RTS_ADDR0))
+#define BIT_GET_RTS_ADDR0(x) (((x) >> BIT_SHIFT_RTS_ADDR0) & BIT_MASK_RTS_ADDR0)
+#define BIT_SET_RTS_ADDR0(x, v) (BIT_CLEAR_RTS_ADDR0(x) | BIT_RTS_ADDR0(v))
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+/* 2 REG_RTS_ADDRESS_1			(Offset 0x07F8) */
+
+#define BIT_SHIFT_R_WMAC_RTS_ADDR1 0
+#define BIT_MASK_R_WMAC_RTS_ADDR1 0xffffffffffffL
+#define BIT_R_WMAC_RTS_ADDR1(x)                                                \
+	(((x) & BIT_MASK_R_WMAC_RTS_ADDR1) << BIT_SHIFT_R_WMAC_RTS_ADDR1)
+#define BITS_R_WMAC_RTS_ADDR1                                                  \
+	(BIT_MASK_R_WMAC_RTS_ADDR1 << BIT_SHIFT_R_WMAC_RTS_ADDR1)
+#define BIT_CLEAR_R_WMAC_RTS_ADDR1(x) ((x) & (~BITS_R_WMAC_RTS_ADDR1))
+#define BIT_GET_R_WMAC_RTS_ADDR1(x)                                            \
+	(((x) >> BIT_SHIFT_R_WMAC_RTS_ADDR1) & BIT_MASK_R_WMAC_RTS_ADDR1)
+#define BIT_SET_R_WMAC_RTS_ADDR1(x, v)                                         \
+	(BIT_CLEAR_R_WMAC_RTS_ADDR1(x) | BIT_R_WMAC_RTS_ADDR1(v))
+
+#endif
+
+#if (HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_RTS_ADDR1				(Offset 0x07F8) */
+
+#define BIT_SHIFT_RTS_ADDR1 0
+#define BIT_MASK_RTS_ADDR1 0xffffffffffffL
+#define BIT_RTS_ADDR1(x) (((x) & BIT_MASK_RTS_ADDR1) << BIT_SHIFT_RTS_ADDR1)
+#define BITS_RTS_ADDR1 (BIT_MASK_RTS_ADDR1 << BIT_SHIFT_RTS_ADDR1)
+#define BIT_CLEAR_RTS_ADDR1(x) ((x) & (~BITS_RTS_ADDR1))
+#define BIT_GET_RTS_ADDR1(x) (((x) >> BIT_SHIFT_RTS_ADDR1) & BIT_MASK_RTS_ADDR1)
+#define BIT_SET_RTS_ADDR1(x, v) (BIT_CLEAR_RTS_ADDR1(x) | BIT_RTS_ADDR1(v))
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_SYS_CFG3				(Offset 0x1000) */
+
+#define BIT_FEN_BB_GLB_RSTN_V1 BIT(17)
+#define BIT_FEN_BBRSTB_V1 BIT(16)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT || HALMAC_8822B_SUPPORT)
+
+/* 2 REG_SYS_CFG3				(Offset 0x1000) */
+
+#define BIT_PWC_MA33V BIT(15)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_SYS_CFG3				(Offset 0x1000) */
+
+#define BIT_PWC_EV25V_1 BIT(14)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT || HALMAC_8822B_SUPPORT)
+
+/* 2 REG_SYS_CFG3				(Offset 0x1000) */
+
+#define BIT_PWC_MA12V BIT(14)
+#define BIT_PWC_MD12V BIT(13)
+#define BIT_PWC_PD12V BIT(12)
+#define BIT_PWC_UD12V BIT(11)
+#define BIT_ISO_MA2MD BIT(1)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_ANAPARSW_MAC_0			(Offset 0x1010) */
+
+#define BIT_OCP_L BIT(31)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_ANAPARSW_MAC_0			(Offset 0x1010) */
+
+#define BIT_OCP_L_0 BIT(31)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_ANAPARSW_MAC_0			(Offset 0x1010) */
+
+#define BIT_POWOCP_L BIT(30)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_ANAPARSW_MAC_0			(Offset 0x1010) */
+
+#define BIT_SHIFT_CF_L_V2 28
+#define BIT_MASK_CF_L_V2 0x3
+#define BIT_CF_L_V2(x) (((x) & BIT_MASK_CF_L_V2) << BIT_SHIFT_CF_L_V2)
+#define BITS_CF_L_V2 (BIT_MASK_CF_L_V2 << BIT_SHIFT_CF_L_V2)
+#define BIT_CLEAR_CF_L_V2(x) ((x) & (~BITS_CF_L_V2))
+#define BIT_GET_CF_L_V2(x) (((x) >> BIT_SHIFT_CF_L_V2) & BIT_MASK_CF_L_V2)
+#define BIT_SET_CF_L_V2(x, v) (BIT_CLEAR_CF_L_V2(x) | BIT_CF_L_V2(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_ANAPARSW_MAC_0			(Offset 0x1010) */
+
+#define BIT_SHIFT_CF_L_1_0 28
+#define BIT_MASK_CF_L_1_0 0x3
+#define BIT_CF_L_1_0(x) (((x) & BIT_MASK_CF_L_1_0) << BIT_SHIFT_CF_L_1_0)
+#define BITS_CF_L_1_0 (BIT_MASK_CF_L_1_0 << BIT_SHIFT_CF_L_1_0)
+#define BIT_CLEAR_CF_L_1_0(x) ((x) & (~BITS_CF_L_1_0))
+#define BIT_GET_CF_L_1_0(x) (((x) >> BIT_SHIFT_CF_L_1_0) & BIT_MASK_CF_L_1_0)
+#define BIT_SET_CF_L_1_0(x, v) (BIT_CLEAR_CF_L_1_0(x) | BIT_CF_L_1_0(v))
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_ANAPARSW_MAC_0			(Offset 0x1010) */
+
+#define BIT_SHIFT_CFC_L_V2 26
+#define BIT_MASK_CFC_L_V2 0x3
+#define BIT_CFC_L_V2(x) (((x) & BIT_MASK_CFC_L_V2) << BIT_SHIFT_CFC_L_V2)
+#define BITS_CFC_L_V2 (BIT_MASK_CFC_L_V2 << BIT_SHIFT_CFC_L_V2)
+#define BIT_CLEAR_CFC_L_V2(x) ((x) & (~BITS_CFC_L_V2))
+#define BIT_GET_CFC_L_V2(x) (((x) >> BIT_SHIFT_CFC_L_V2) & BIT_MASK_CFC_L_V2)
+#define BIT_SET_CFC_L_V2(x, v) (BIT_CLEAR_CFC_L_V2(x) | BIT_CFC_L_V2(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_ANAPARSW_MAC_0			(Offset 0x1010) */
+
+#define BIT_SHIFT_CFC_L_1_0 26
+#define BIT_MASK_CFC_L_1_0 0x3
+#define BIT_CFC_L_1_0(x) (((x) & BIT_MASK_CFC_L_1_0) << BIT_SHIFT_CFC_L_1_0)
+#define BITS_CFC_L_1_0 (BIT_MASK_CFC_L_1_0 << BIT_SHIFT_CFC_L_1_0)
+#define BIT_CLEAR_CFC_L_1_0(x) ((x) & (~BITS_CFC_L_1_0))
+#define BIT_GET_CFC_L_1_0(x) (((x) >> BIT_SHIFT_CFC_L_1_0) & BIT_MASK_CFC_L_1_0)
+#define BIT_SET_CFC_L_1_0(x, v) (BIT_CLEAR_CFC_L_1_0(x) | BIT_CFC_L_1_0(v))
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_ANAPARSW_MAC_0			(Offset 0x1010) */
+
+#define BIT_SHIFT_R3_L_V2 24
+#define BIT_MASK_R3_L_V2 0x3
+#define BIT_R3_L_V2(x) (((x) & BIT_MASK_R3_L_V2) << BIT_SHIFT_R3_L_V2)
+#define BITS_R3_L_V2 (BIT_MASK_R3_L_V2 << BIT_SHIFT_R3_L_V2)
+#define BIT_CLEAR_R3_L_V2(x) ((x) & (~BITS_R3_L_V2))
+#define BIT_GET_R3_L_V2(x) (((x) >> BIT_SHIFT_R3_L_V2) & BIT_MASK_R3_L_V2)
+#define BIT_SET_R3_L_V2(x, v) (BIT_CLEAR_R3_L_V2(x) | BIT_R3_L_V2(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_ANAPARSW_MAC_0			(Offset 0x1010) */
+
+#define BIT_SHIFT_R3_L_1_0 24
+#define BIT_MASK_R3_L_1_0 0x3
+#define BIT_R3_L_1_0(x) (((x) & BIT_MASK_R3_L_1_0) << BIT_SHIFT_R3_L_1_0)
+#define BITS_R3_L_1_0 (BIT_MASK_R3_L_1_0 << BIT_SHIFT_R3_L_1_0)
+#define BIT_CLEAR_R3_L_1_0(x) ((x) & (~BITS_R3_L_1_0))
+#define BIT_GET_R3_L_1_0(x) (((x) >> BIT_SHIFT_R3_L_1_0) & BIT_MASK_R3_L_1_0)
+#define BIT_SET_R3_L_1_0(x, v) (BIT_CLEAR_R3_L_1_0(x) | BIT_R3_L_1_0(v))
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_ANAPARSW_MAC_0			(Offset 0x1010) */
+
+#define BIT_SHIFT_R2_L 22
+#define BIT_MASK_R2_L 0x3
+#define BIT_R2_L(x) (((x) & BIT_MASK_R2_L) << BIT_SHIFT_R2_L)
+#define BITS_R2_L (BIT_MASK_R2_L << BIT_SHIFT_R2_L)
+#define BIT_CLEAR_R2_L(x) ((x) & (~BITS_R2_L))
+#define BIT_GET_R2_L(x) (((x) >> BIT_SHIFT_R2_L) & BIT_MASK_R2_L)
+#define BIT_SET_R2_L(x, v) (BIT_CLEAR_R2_L(x) | BIT_R2_L(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_ANAPARSW_MAC_0			(Offset 0x1010) */
+
+#define BIT_SHIFT_R2_L_1_0 22
+#define BIT_MASK_R2_L_1_0 0x3
+#define BIT_R2_L_1_0(x) (((x) & BIT_MASK_R2_L_1_0) << BIT_SHIFT_R2_L_1_0)
+#define BITS_R2_L_1_0 (BIT_MASK_R2_L_1_0 << BIT_SHIFT_R2_L_1_0)
+#define BIT_CLEAR_R2_L_1_0(x) ((x) & (~BITS_R2_L_1_0))
+#define BIT_GET_R2_L_1_0(x) (((x) >> BIT_SHIFT_R2_L_1_0) & BIT_MASK_R2_L_1_0)
+#define BIT_SET_R2_L_1_0(x, v) (BIT_CLEAR_R2_L_1_0(x) | BIT_R2_L_1_0(v))
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_ANAPARSW_MAC_0			(Offset 0x1010) */
+
+#define BIT_SHIFT_R1_L 20
+#define BIT_MASK_R1_L 0x3
+#define BIT_R1_L(x) (((x) & BIT_MASK_R1_L) << BIT_SHIFT_R1_L)
+#define BITS_R1_L (BIT_MASK_R1_L << BIT_SHIFT_R1_L)
+#define BIT_CLEAR_R1_L(x) ((x) & (~BITS_R1_L))
+#define BIT_GET_R1_L(x) (((x) >> BIT_SHIFT_R1_L) & BIT_MASK_R1_L)
+#define BIT_SET_R1_L(x, v) (BIT_CLEAR_R1_L(x) | BIT_R1_L(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_ANAPARSW_MAC_0			(Offset 0x1010) */
+
+#define BIT_SHIFT_R1_L_1_0 20
+#define BIT_MASK_R1_L_1_0 0x3
+#define BIT_R1_L_1_0(x) (((x) & BIT_MASK_R1_L_1_0) << BIT_SHIFT_R1_L_1_0)
+#define BITS_R1_L_1_0 (BIT_MASK_R1_L_1_0 << BIT_SHIFT_R1_L_1_0)
+#define BIT_CLEAR_R1_L_1_0(x) ((x) & (~BITS_R1_L_1_0))
+#define BIT_GET_R1_L_1_0(x) (((x) >> BIT_SHIFT_R1_L_1_0) & BIT_MASK_R1_L_1_0)
+#define BIT_SET_R1_L_1_0(x, v) (BIT_CLEAR_R1_L_1_0(x) | BIT_R1_L_1_0(v))
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_ANAPARSW_MAC_0			(Offset 0x1010) */
+
+#define BIT_SHIFT_C3_L 18
+#define BIT_MASK_C3_L 0x3
+#define BIT_C3_L(x) (((x) & BIT_MASK_C3_L) << BIT_SHIFT_C3_L)
+#define BITS_C3_L (BIT_MASK_C3_L << BIT_SHIFT_C3_L)
+#define BIT_CLEAR_C3_L(x) ((x) & (~BITS_C3_L))
+#define BIT_GET_C3_L(x) (((x) >> BIT_SHIFT_C3_L) & BIT_MASK_C3_L)
+#define BIT_SET_C3_L(x, v) (BIT_CLEAR_C3_L(x) | BIT_C3_L(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_ANAPARSW_MAC_0			(Offset 0x1010) */
+
+#define BIT_SHIFT_C3_L_1_0 18
+#define BIT_MASK_C3_L_1_0 0x3
+#define BIT_C3_L_1_0(x) (((x) & BIT_MASK_C3_L_1_0) << BIT_SHIFT_C3_L_1_0)
+#define BITS_C3_L_1_0 (BIT_MASK_C3_L_1_0 << BIT_SHIFT_C3_L_1_0)
+#define BIT_CLEAR_C3_L_1_0(x) ((x) & (~BITS_C3_L_1_0))
+#define BIT_GET_C3_L_1_0(x) (((x) >> BIT_SHIFT_C3_L_1_0) & BIT_MASK_C3_L_1_0)
+#define BIT_SET_C3_L_1_0(x, v) (BIT_CLEAR_C3_L_1_0(x) | BIT_C3_L_1_0(v))
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_ANAPARSW_MAC_0			(Offset 0x1010) */
+
+#define BIT_SHIFT_C2_L 16
+#define BIT_MASK_C2_L 0x3
+#define BIT_C2_L(x) (((x) & BIT_MASK_C2_L) << BIT_SHIFT_C2_L)
+#define BITS_C2_L (BIT_MASK_C2_L << BIT_SHIFT_C2_L)
+#define BIT_CLEAR_C2_L(x) ((x) & (~BITS_C2_L))
+#define BIT_GET_C2_L(x) (((x) >> BIT_SHIFT_C2_L) & BIT_MASK_C2_L)
+#define BIT_SET_C2_L(x, v) (BIT_CLEAR_C2_L(x) | BIT_C2_L(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_ANAPARSW_MAC_0			(Offset 0x1010) */
+
+#define BIT_SHIFT_C2_L_1_0 16
+#define BIT_MASK_C2_L_1_0 0x3
+#define BIT_C2_L_1_0(x) (((x) & BIT_MASK_C2_L_1_0) << BIT_SHIFT_C2_L_1_0)
+#define BITS_C2_L_1_0 (BIT_MASK_C2_L_1_0 << BIT_SHIFT_C2_L_1_0)
+#define BIT_CLEAR_C2_L_1_0(x) ((x) & (~BITS_C2_L_1_0))
+#define BIT_GET_C2_L_1_0(x) (((x) >> BIT_SHIFT_C2_L_1_0) & BIT_MASK_C2_L_1_0)
+#define BIT_SET_C2_L_1_0(x, v) (BIT_CLEAR_C2_L_1_0(x) | BIT_C2_L_1_0(v))
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_ANAPARSW_MAC_0			(Offset 0x1010) */
+
+#define BIT_SHIFT_C1_L_V2 14
+#define BIT_MASK_C1_L_V2 0x3
+#define BIT_C1_L_V2(x) (((x) & BIT_MASK_C1_L_V2) << BIT_SHIFT_C1_L_V2)
+#define BITS_C1_L_V2 (BIT_MASK_C1_L_V2 << BIT_SHIFT_C1_L_V2)
+#define BIT_CLEAR_C1_L_V2(x) ((x) & (~BITS_C1_L_V2))
+#define BIT_GET_C1_L_V2(x) (((x) >> BIT_SHIFT_C1_L_V2) & BIT_MASK_C1_L_V2)
+#define BIT_SET_C1_L_V2(x, v) (BIT_CLEAR_C1_L_V2(x) | BIT_C1_L_V2(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_ANAPARSW_MAC_0			(Offset 0x1010) */
+
+#define BIT_SHIFT_C1_L_1_0 14
+#define BIT_MASK_C1_L_1_0 0x3
+#define BIT_C1_L_1_0(x) (((x) & BIT_MASK_C1_L_1_0) << BIT_SHIFT_C1_L_1_0)
+#define BITS_C1_L_1_0 (BIT_MASK_C1_L_1_0 << BIT_SHIFT_C1_L_1_0)
+#define BIT_CLEAR_C1_L_1_0(x) ((x) & (~BITS_C1_L_1_0))
+#define BIT_GET_C1_L_1_0(x) (((x) >> BIT_SHIFT_C1_L_1_0) & BIT_MASK_C1_L_1_0)
+#define BIT_SET_C1_L_1_0(x, v) (BIT_CLEAR_C1_L_1_0(x) | BIT_C1_L_1_0(v))
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_ANAPARSW_MAC_0			(Offset 0x1010) */
+
+#define BIT_REG_TYPE_L_V2 BIT(13)
+#define BIT_REG_PWM_L BIT(12)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_ANAPARSW_MAC_0			(Offset 0x1010) */
+
+#define BIT_SHIFT_V15ADJ_L 9
+#define BIT_MASK_V15ADJ_L 0x7
+#define BIT_V15ADJ_L(x) (((x) & BIT_MASK_V15ADJ_L) << BIT_SHIFT_V15ADJ_L)
+#define BITS_V15ADJ_L (BIT_MASK_V15ADJ_L << BIT_SHIFT_V15ADJ_L)
+#define BIT_CLEAR_V15ADJ_L(x) ((x) & (~BITS_V15ADJ_L))
+#define BIT_GET_V15ADJ_L(x) (((x) >> BIT_SHIFT_V15ADJ_L) & BIT_MASK_V15ADJ_L)
+#define BIT_SET_V15ADJ_L(x, v) (BIT_CLEAR_V15ADJ_L(x) | BIT_V15ADJ_L(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_ANAPARSW_MAC_0			(Offset 0x1010) */
+
+#define BIT_SHIFT_V15ADJ_L_2_0 9
+#define BIT_MASK_V15ADJ_L_2_0 0x7
+#define BIT_V15ADJ_L_2_0(x)                                                    \
+	(((x) & BIT_MASK_V15ADJ_L_2_0) << BIT_SHIFT_V15ADJ_L_2_0)
+#define BITS_V15ADJ_L_2_0 (BIT_MASK_V15ADJ_L_2_0 << BIT_SHIFT_V15ADJ_L_2_0)
+#define BIT_CLEAR_V15ADJ_L_2_0(x) ((x) & (~BITS_V15ADJ_L_2_0))
+#define BIT_GET_V15ADJ_L_2_0(x)                                                \
+	(((x) >> BIT_SHIFT_V15ADJ_L_2_0) & BIT_MASK_V15ADJ_L_2_0)
+#define BIT_SET_V15ADJ_L_2_0(x, v)                                             \
+	(BIT_CLEAR_V15ADJ_L_2_0(x) | BIT_V15ADJ_L_2_0(v))
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_ANAPARSW_MAC_0			(Offset 0x1010) */
+
+#define BIT_SHIFT_IN_L 6
+#define BIT_MASK_IN_L 0x7
+#define BIT_IN_L(x) (((x) & BIT_MASK_IN_L) << BIT_SHIFT_IN_L)
+#define BITS_IN_L (BIT_MASK_IN_L << BIT_SHIFT_IN_L)
+#define BIT_CLEAR_IN_L(x) ((x) & (~BITS_IN_L))
+#define BIT_GET_IN_L(x) (((x) >> BIT_SHIFT_IN_L) & BIT_MASK_IN_L)
+#define BIT_SET_IN_L(x, v) (BIT_CLEAR_IN_L(x) | BIT_IN_L(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_ANAPARSW_MAC_0			(Offset 0x1010) */
+
+#define BIT_SHIFT_IN_L_2_0 6
+#define BIT_MASK_IN_L_2_0 0x7
+#define BIT_IN_L_2_0(x) (((x) & BIT_MASK_IN_L_2_0) << BIT_SHIFT_IN_L_2_0)
+#define BITS_IN_L_2_0 (BIT_MASK_IN_L_2_0 << BIT_SHIFT_IN_L_2_0)
+#define BIT_CLEAR_IN_L_2_0(x) ((x) & (~BITS_IN_L_2_0))
+#define BIT_GET_IN_L_2_0(x) (((x) >> BIT_SHIFT_IN_L_2_0) & BIT_MASK_IN_L_2_0)
+#define BIT_SET_IN_L_2_0(x, v) (BIT_CLEAR_IN_L_2_0(x) | BIT_IN_L_2_0(v))
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_ANAPARSW_MAC_0			(Offset 0x1010) */
+
+#define BIT_SHIFT_STD_L 4
+#define BIT_MASK_STD_L 0x3
+#define BIT_STD_L(x) (((x) & BIT_MASK_STD_L) << BIT_SHIFT_STD_L)
+#define BITS_STD_L (BIT_MASK_STD_L << BIT_SHIFT_STD_L)
+#define BIT_CLEAR_STD_L(x) ((x) & (~BITS_STD_L))
+#define BIT_GET_STD_L(x) (((x) >> BIT_SHIFT_STD_L) & BIT_MASK_STD_L)
+#define BIT_SET_STD_L(x, v) (BIT_CLEAR_STD_L(x) | BIT_STD_L(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_ANAPARSW_MAC_0			(Offset 0x1010) */
+
+#define BIT_SHIFT_STD_L_1_0 4
+#define BIT_MASK_STD_L_1_0 0x3
+#define BIT_STD_L_1_0(x) (((x) & BIT_MASK_STD_L_1_0) << BIT_SHIFT_STD_L_1_0)
+#define BITS_STD_L_1_0 (BIT_MASK_STD_L_1_0 << BIT_SHIFT_STD_L_1_0)
+#define BIT_CLEAR_STD_L_1_0(x) ((x) & (~BITS_STD_L_1_0))
+#define BIT_GET_STD_L_1_0(x) (((x) >> BIT_SHIFT_STD_L_1_0) & BIT_MASK_STD_L_1_0)
+#define BIT_SET_STD_L_1_0(x, v) (BIT_CLEAR_STD_L_1_0(x) | BIT_STD_L_1_0(v))
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_ANAPARSW_MAC_0			(Offset 0x1010) */
+
+#define BIT_SHIFT_VOL_L 0
+#define BIT_MASK_VOL_L 0xf
+#define BIT_VOL_L(x) (((x) & BIT_MASK_VOL_L) << BIT_SHIFT_VOL_L)
+#define BITS_VOL_L (BIT_MASK_VOL_L << BIT_SHIFT_VOL_L)
+#define BIT_CLEAR_VOL_L(x) ((x) & (~BITS_VOL_L))
+#define BIT_GET_VOL_L(x) (((x) >> BIT_SHIFT_VOL_L) & BIT_MASK_VOL_L)
+#define BIT_SET_VOL_L(x, v) (BIT_CLEAR_VOL_L(x) | BIT_VOL_L(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_ANAPARSW_MAC_0			(Offset 0x1010) */
+
+#define BIT_SHIFT_VOL_L_3_0 0
+#define BIT_MASK_VOL_L_3_0 0xf
+#define BIT_VOL_L_3_0(x) (((x) & BIT_MASK_VOL_L_3_0) << BIT_SHIFT_VOL_L_3_0)
+#define BITS_VOL_L_3_0 (BIT_MASK_VOL_L_3_0 << BIT_SHIFT_VOL_L_3_0)
+#define BIT_CLEAR_VOL_L_3_0(x) ((x) & (~BITS_VOL_L_3_0))
+#define BIT_GET_VOL_L_3_0(x) (((x) >> BIT_SHIFT_VOL_L_3_0) & BIT_MASK_VOL_L_3_0)
+#define BIT_SET_VOL_L_3_0(x, v) (BIT_CLEAR_VOL_L_3_0(x) | BIT_VOL_L_3_0(v))
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_ANAPARSW_MAC_1			(Offset 0x1014) */
+
+#define BIT_SHIFT_OCP_L_PFM 29
+#define BIT_MASK_OCP_L_PFM 0x7
+#define BIT_OCP_L_PFM(x) (((x) & BIT_MASK_OCP_L_PFM) << BIT_SHIFT_OCP_L_PFM)
+#define BITS_OCP_L_PFM (BIT_MASK_OCP_L_PFM << BIT_SHIFT_OCP_L_PFM)
+#define BIT_CLEAR_OCP_L_PFM(x) ((x) & (~BITS_OCP_L_PFM))
+#define BIT_GET_OCP_L_PFM(x) (((x) >> BIT_SHIFT_OCP_L_PFM) & BIT_MASK_OCP_L_PFM)
+#define BIT_SET_OCP_L_PFM(x, v) (BIT_CLEAR_OCP_L_PFM(x) | BIT_OCP_L_PFM(v))
+
+#define BIT_SHIFT_CFC_L_PFM 27
+#define BIT_MASK_CFC_L_PFM 0x3
+#define BIT_CFC_L_PFM(x) (((x) & BIT_MASK_CFC_L_PFM) << BIT_SHIFT_CFC_L_PFM)
+#define BITS_CFC_L_PFM (BIT_MASK_CFC_L_PFM << BIT_SHIFT_CFC_L_PFM)
+#define BIT_CLEAR_CFC_L_PFM(x) ((x) & (~BITS_CFC_L_PFM))
+#define BIT_GET_CFC_L_PFM(x) (((x) >> BIT_SHIFT_CFC_L_PFM) & BIT_MASK_CFC_L_PFM)
+#define BIT_SET_CFC_L_PFM(x, v) (BIT_CLEAR_CFC_L_PFM(x) | BIT_CFC_L_PFM(v))
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_ANAPARSW_MAC_1			(Offset 0x1014) */
+
+#define BIT_SHIFT_REG_FREQ_L_V1 20
+#define BIT_MASK_REG_FREQ_L_V1 0x7
+#define BIT_REG_FREQ_L_V1(x)                                                   \
+	(((x) & BIT_MASK_REG_FREQ_L_V1) << BIT_SHIFT_REG_FREQ_L_V1)
+#define BITS_REG_FREQ_L_V1 (BIT_MASK_REG_FREQ_L_V1 << BIT_SHIFT_REG_FREQ_L_V1)
+#define BIT_CLEAR_REG_FREQ_L_V1(x) ((x) & (~BITS_REG_FREQ_L_V1))
+#define BIT_GET_REG_FREQ_L_V1(x)                                               \
+	(((x) >> BIT_SHIFT_REG_FREQ_L_V1) & BIT_MASK_REG_FREQ_L_V1)
+#define BIT_SET_REG_FREQ_L_V1(x, v)                                            \
+	(BIT_CLEAR_REG_FREQ_L_V1(x) | BIT_REG_FREQ_L_V1(v))
+
+#define BIT_EN_DUTY BIT(19)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_ANAPARSW_MAC_1			(Offset 0x1014) */
+
+#define BIT_SHIFT_REG_MODE_V2 17
+#define BIT_MASK_REG_MODE_V2 0x3
+#define BIT_REG_MODE_V2(x)                                                     \
+	(((x) & BIT_MASK_REG_MODE_V2) << BIT_SHIFT_REG_MODE_V2)
+#define BITS_REG_MODE_V2 (BIT_MASK_REG_MODE_V2 << BIT_SHIFT_REG_MODE_V2)
+#define BIT_CLEAR_REG_MODE_V2(x) ((x) & (~BITS_REG_MODE_V2))
+#define BIT_GET_REG_MODE_V2(x)                                                 \
+	(((x) >> BIT_SHIFT_REG_MODE_V2) & BIT_MASK_REG_MODE_V2)
+#define BIT_SET_REG_MODE_V2(x, v)                                              \
+	(BIT_CLEAR_REG_MODE_V2(x) | BIT_REG_MODE_V2(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_ANAPARSW_MAC_1			(Offset 0x1014) */
+
+#define BIT_SHIFT_REG_MOS_HALF 17
+#define BIT_MASK_REG_MOS_HALF 0x3
+#define BIT_REG_MOS_HALF(x)                                                    \
+	(((x) & BIT_MASK_REG_MOS_HALF) << BIT_SHIFT_REG_MOS_HALF)
+#define BITS_REG_MOS_HALF (BIT_MASK_REG_MOS_HALF << BIT_SHIFT_REG_MOS_HALF)
+#define BIT_CLEAR_REG_MOS_HALF(x) ((x) & (~BITS_REG_MOS_HALF))
+#define BIT_GET_REG_MOS_HALF(x)                                                \
+	(((x) >> BIT_SHIFT_REG_MOS_HALF) & BIT_MASK_REG_MOS_HALF)
+#define BIT_SET_REG_MOS_HALF(x, v)                                             \
+	(BIT_CLEAR_REG_MOS_HALF(x) | BIT_REG_MOS_HALF(v))
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_ANAPARSW_MAC_1			(Offset 0x1014) */
+
+#define BIT_EN_SP BIT(16)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_ANAPARSW_MAC_1			(Offset 0x1014) */
+
+#define BIT_REG_AUTO_L_V2 BIT(15)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_ANAPARSW_MAC_1			(Offset 0x1014) */
+
+#define BIT_REG_AUTO_L_V1 BIT(15)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_ANAPARSW_MAC_1			(Offset 0x1014) */
+
+#define BIT_REG_LDOF_L_V2 BIT(14)
+#define BIT_REG_OCPS_L_V2 BIT(13)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_ANAPARSW_MAC_1			(Offset 0x1014) */
+
+#define BIT_VO15_V1P05_H BIT(12)
+#define BIT_ARENB_L_V2 BIT(11)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_ANAPARSW_MAC_1			(Offset 0x1014) */
+
+#define BIT_ARENB_L_V1 BIT(11)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_ANAPARSW_MAC_1			(Offset 0x1014) */
+
+#define BIT_SHIFT_TBOX_L1_V2 9
+#define BIT_MASK_TBOX_L1_V2 0x3
+#define BIT_TBOX_L1_V2(x) (((x) & BIT_MASK_TBOX_L1_V2) << BIT_SHIFT_TBOX_L1_V2)
+#define BITS_TBOX_L1_V2 (BIT_MASK_TBOX_L1_V2 << BIT_SHIFT_TBOX_L1_V2)
+#define BIT_CLEAR_TBOX_L1_V2(x) ((x) & (~BITS_TBOX_L1_V2))
+#define BIT_GET_TBOX_L1_V2(x)                                                  \
+	(((x) >> BIT_SHIFT_TBOX_L1_V2) & BIT_MASK_TBOX_L1_V2)
+#define BIT_SET_TBOX_L1_V2(x, v) (BIT_CLEAR_TBOX_L1_V2(x) | BIT_TBOX_L1_V2(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_ANAPARSW_MAC_1			(Offset 0x1014) */
+
+#define BIT_SHIFT_TBOX_L1_1_0 9
+#define BIT_MASK_TBOX_L1_1_0 0x3
+#define BIT_TBOX_L1_1_0(x)                                                     \
+	(((x) & BIT_MASK_TBOX_L1_1_0) << BIT_SHIFT_TBOX_L1_1_0)
+#define BITS_TBOX_L1_1_0 (BIT_MASK_TBOX_L1_1_0 << BIT_SHIFT_TBOX_L1_1_0)
+#define BIT_CLEAR_TBOX_L1_1_0(x) ((x) & (~BITS_TBOX_L1_1_0))
+#define BIT_GET_TBOX_L1_1_0(x)                                                 \
+	(((x) >> BIT_SHIFT_TBOX_L1_1_0) & BIT_MASK_TBOX_L1_1_0)
+#define BIT_SET_TBOX_L1_1_0(x, v)                                              \
+	(BIT_CLEAR_TBOX_L1_1_0(x) | BIT_TBOX_L1_1_0(v))
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_ANAPARSW_MAC_1			(Offset 0x1014) */
+
+#define BIT_SHIFT_REG_DELAY_L 7
+#define BIT_MASK_REG_DELAY_L 0x3
+#define BIT_REG_DELAY_L(x)                                                     \
+	(((x) & BIT_MASK_REG_DELAY_L) << BIT_SHIFT_REG_DELAY_L)
+#define BITS_REG_DELAY_L (BIT_MASK_REG_DELAY_L << BIT_SHIFT_REG_DELAY_L)
+#define BIT_CLEAR_REG_DELAY_L(x) ((x) & (~BITS_REG_DELAY_L))
+#define BIT_GET_REG_DELAY_L(x)                                                 \
+	(((x) >> BIT_SHIFT_REG_DELAY_L) & BIT_MASK_REG_DELAY_L)
+#define BIT_SET_REG_DELAY_L(x, v)                                              \
+	(BIT_CLEAR_REG_DELAY_L(x) | BIT_REG_DELAY_L(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_ANAPARSW_MAC_1			(Offset 0x1014) */
+
+#define BIT_SHIFT_REG_DELAY_L_1_0 7
+#define BIT_MASK_REG_DELAY_L_1_0 0x3
+#define BIT_REG_DELAY_L_1_0(x)                                                 \
+	(((x) & BIT_MASK_REG_DELAY_L_1_0) << BIT_SHIFT_REG_DELAY_L_1_0)
+#define BITS_REG_DELAY_L_1_0                                                   \
+	(BIT_MASK_REG_DELAY_L_1_0 << BIT_SHIFT_REG_DELAY_L_1_0)
+#define BIT_CLEAR_REG_DELAY_L_1_0(x) ((x) & (~BITS_REG_DELAY_L_1_0))
+#define BIT_GET_REG_DELAY_L_1_0(x)                                             \
+	(((x) >> BIT_SHIFT_REG_DELAY_L_1_0) & BIT_MASK_REG_DELAY_L_1_0)
+#define BIT_SET_REG_DELAY_L_1_0(x, v)                                          \
+	(BIT_CLEAR_REG_DELAY_L_1_0(x) | BIT_REG_DELAY_L_1_0(v))
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_ANAPARSW_MAC_1			(Offset 0x1014) */
+
+#define BIT_REG_CLAMP_D_L BIT(6)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_ANAPARSW_MAC_1			(Offset 0x1014) */
+
+#define BIT_REG_BYPASS_L_V2 BIT(5)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_ANAPARSW_MAC_1			(Offset 0x1014) */
+
+#define BIT_REG_BYPASS_L_V1 BIT(5)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_ANAPARSW_MAC_1			(Offset 0x1014) */
+
+#define BIT_REG_AUTOZCD_L BIT(4)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_ANAPARSW_MAC_1			(Offset 0x1014) */
+
+#define BIT_POW_ZCD_L_V2 BIT(3)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_ANAPARSW_MAC_1			(Offset 0x1014) */
+
+#define BIT_POW_ZCD_L_V1 BIT(3)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_ANAPARSW_MAC_1			(Offset 0x1014) */
+
+#define BIT_REG_HALF_L BIT(2)
+
+#define BIT_SHIFT_OCP_L_V2 0
+#define BIT_MASK_OCP_L_V2 0x3
+#define BIT_OCP_L_V2(x) (((x) & BIT_MASK_OCP_L_V2) << BIT_SHIFT_OCP_L_V2)
+#define BITS_OCP_L_V2 (BIT_MASK_OCP_L_V2 << BIT_SHIFT_OCP_L_V2)
+#define BIT_CLEAR_OCP_L_V2(x) ((x) & (~BITS_OCP_L_V2))
+#define BIT_GET_OCP_L_V2(x) (((x) >> BIT_SHIFT_OCP_L_V2) & BIT_MASK_OCP_L_V2)
+#define BIT_SET_OCP_L_V2(x, v) (BIT_CLEAR_OCP_L_V2(x) | BIT_OCP_L_V2(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_ANAPARSW_MAC_1			(Offset 0x1014) */
+
+#define BIT_SHIFT_OCP_L_2_1 0
+#define BIT_MASK_OCP_L_2_1 0x3
+#define BIT_OCP_L_2_1(x) (((x) & BIT_MASK_OCP_L_2_1) << BIT_SHIFT_OCP_L_2_1)
+#define BITS_OCP_L_2_1 (BIT_MASK_OCP_L_2_1 << BIT_SHIFT_OCP_L_2_1)
+#define BIT_CLEAR_OCP_L_2_1(x) ((x) & (~BITS_OCP_L_2_1))
+#define BIT_GET_OCP_L_2_1(x) (((x) >> BIT_SHIFT_OCP_L_2_1) & BIT_MASK_OCP_L_2_1)
+#define BIT_SET_OCP_L_2_1(x, v) (BIT_CLEAR_OCP_L_2_1(x) | BIT_OCP_L_2_1(v))
+
+/* 2 REG_ANAPAR_MAC_0			(Offset 0x1018) */
+
+#define BIT_SHIFT_LPF_C2_1_0 30
+#define BIT_MASK_LPF_C2_1_0 0x3
+#define BIT_LPF_C2_1_0(x) (((x) & BIT_MASK_LPF_C2_1_0) << BIT_SHIFT_LPF_C2_1_0)
+#define BITS_LPF_C2_1_0 (BIT_MASK_LPF_C2_1_0 << BIT_SHIFT_LPF_C2_1_0)
+#define BIT_CLEAR_LPF_C2_1_0(x) ((x) & (~BITS_LPF_C2_1_0))
+#define BIT_GET_LPF_C2_1_0(x)                                                  \
+	(((x) >> BIT_SHIFT_LPF_C2_1_0) & BIT_MASK_LPF_C2_1_0)
+#define BIT_SET_LPF_C2_1_0(x, v) (BIT_CLEAR_LPF_C2_1_0(x) | BIT_LPF_C2_1_0(v))
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_ANAPAR_MAC_0			(Offset 0x1018) */
+
+#define BIT_SHIFT_REG_LPF_R3 29
+#define BIT_MASK_REG_LPF_R3 0x7
+#define BIT_REG_LPF_R3(x) (((x) & BIT_MASK_REG_LPF_R3) << BIT_SHIFT_REG_LPF_R3)
+#define BITS_REG_LPF_R3 (BIT_MASK_REG_LPF_R3 << BIT_SHIFT_REG_LPF_R3)
+#define BIT_CLEAR_REG_LPF_R3(x) ((x) & (~BITS_REG_LPF_R3))
+#define BIT_GET_REG_LPF_R3(x)                                                  \
+	(((x) >> BIT_SHIFT_REG_LPF_R3) & BIT_MASK_REG_LPF_R3)
+#define BIT_SET_REG_LPF_R3(x, v) (BIT_CLEAR_REG_LPF_R3(x) | BIT_REG_LPF_R3(v))
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_ANAPAR_MAC_0			(Offset 0x1018) */
+
+#define BIT_EN_XTAL_AAC_TRIG BIT(28)
+#define BIT_EN_XTAL_AAC BIT(27)
+#define BIT_EN_XTAL_AAC_DIGI BIT(26)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_ANAPAR_MAC_0			(Offset 0x1018) */
+
+#define BIT_SHIFT_REG_LPF_R2 24
+#define BIT_MASK_REG_LPF_R2 0x1f
+#define BIT_REG_LPF_R2(x) (((x) & BIT_MASK_REG_LPF_R2) << BIT_SHIFT_REG_LPF_R2)
+#define BITS_REG_LPF_R2 (BIT_MASK_REG_LPF_R2 << BIT_SHIFT_REG_LPF_R2)
+#define BIT_CLEAR_REG_LPF_R2(x) ((x) & (~BITS_REG_LPF_R2))
+#define BIT_GET_REG_LPF_R2(x)                                                  \
+	(((x) >> BIT_SHIFT_REG_LPF_R2) & BIT_MASK_REG_LPF_R2)
+#define BIT_SET_REG_LPF_R2(x, v) (BIT_CLEAR_REG_LPF_R2(x) | BIT_REG_LPF_R2(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_ANAPAR_MAC_0			(Offset 0x1018) */
+
+#define BIT_SHIFT_LPF_C1_5_0 24
+#define BIT_MASK_LPF_C1_5_0 0x3f
+#define BIT_LPF_C1_5_0(x) (((x) & BIT_MASK_LPF_C1_5_0) << BIT_SHIFT_LPF_C1_5_0)
+#define BITS_LPF_C1_5_0 (BIT_MASK_LPF_C1_5_0 << BIT_SHIFT_LPF_C1_5_0)
+#define BIT_CLEAR_LPF_C1_5_0(x) ((x) & (~BITS_LPF_C1_5_0))
+#define BIT_GET_LPF_C1_5_0(x)                                                  \
+	(((x) >> BIT_SHIFT_LPF_C1_5_0) & BIT_MASK_LPF_C1_5_0)
+#define BIT_SET_LPF_C1_5_0(x, v) (BIT_CLEAR_LPF_C1_5_0(x) | BIT_LPF_C1_5_0(v))
+
+#define BIT_LPF_TIEL BIT(23)
+#define BIT_LPF_TIEH BIT(22)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_ANAPAR_MAC_0			(Offset 0x1018) */
+
+#define BIT_SHIFT_REG_LPF_C3 21
+#define BIT_MASK_REG_LPF_C3 0x7
+#define BIT_REG_LPF_C3(x) (((x) & BIT_MASK_REG_LPF_C3) << BIT_SHIFT_REG_LPF_C3)
+#define BITS_REG_LPF_C3 (BIT_MASK_REG_LPF_C3 << BIT_SHIFT_REG_LPF_C3)
+#define BIT_CLEAR_REG_LPF_C3(x) ((x) & (~BITS_REG_LPF_C3))
+#define BIT_GET_REG_LPF_C3(x)                                                  \
+	(((x) >> BIT_SHIFT_REG_LPF_C3) & BIT_MASK_REG_LPF_C3)
+#define BIT_SET_REG_LPF_C3(x, v) (BIT_CLEAR_REG_LPF_C3(x) | BIT_REG_LPF_C3(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_ANAPAR_MAC_0			(Offset 0x1018) */
+
+#define BIT_SHIFT_LOCKDET_VREF_L_1_0 20
+#define BIT_MASK_LOCKDET_VREF_L_1_0 0x3
+#define BIT_LOCKDET_VREF_L_1_0(x)                                              \
+	(((x) & BIT_MASK_LOCKDET_VREF_L_1_0) << BIT_SHIFT_LOCKDET_VREF_L_1_0)
+#define BITS_LOCKDET_VREF_L_1_0                                                \
+	(BIT_MASK_LOCKDET_VREF_L_1_0 << BIT_SHIFT_LOCKDET_VREF_L_1_0)
+#define BIT_CLEAR_LOCKDET_VREF_L_1_0(x) ((x) & (~BITS_LOCKDET_VREF_L_1_0))
+#define BIT_GET_LOCKDET_VREF_L_1_0(x)                                          \
+	(((x) >> BIT_SHIFT_LOCKDET_VREF_L_1_0) & BIT_MASK_LOCKDET_VREF_L_1_0)
+#define BIT_SET_LOCKDET_VREF_L_1_0(x, v)                                       \
+	(BIT_CLEAR_LOCKDET_VREF_L_1_0(x) | BIT_LOCKDET_VREF_L_1_0(v))
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_ANAPAR_MAC_0			(Offset 0x1018) */
+
+#define BIT_SHIFT_REG_LPF_C2 18
+#define BIT_MASK_REG_LPF_C2 0x7
+#define BIT_REG_LPF_C2(x) (((x) & BIT_MASK_REG_LPF_C2) << BIT_SHIFT_REG_LPF_C2)
+#define BITS_REG_LPF_C2 (BIT_MASK_REG_LPF_C2 << BIT_SHIFT_REG_LPF_C2)
+#define BIT_CLEAR_REG_LPF_C2(x) ((x) & (~BITS_REG_LPF_C2))
+#define BIT_GET_REG_LPF_C2(x)                                                  \
+	(((x) >> BIT_SHIFT_REG_LPF_C2) & BIT_MASK_REG_LPF_C2)
+#define BIT_SET_REG_LPF_C2(x, v) (BIT_CLEAR_REG_LPF_C2(x) | BIT_REG_LPF_C2(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_ANAPAR_MAC_0			(Offset 0x1018) */
+
+#define BIT_SHIFT_LOCKDET_VREF_H_1_0 18
+#define BIT_MASK_LOCKDET_VREF_H_1_0 0x3
+#define BIT_LOCKDET_VREF_H_1_0(x)                                              \
+	(((x) & BIT_MASK_LOCKDET_VREF_H_1_0) << BIT_SHIFT_LOCKDET_VREF_H_1_0)
+#define BITS_LOCKDET_VREF_H_1_0                                                \
+	(BIT_MASK_LOCKDET_VREF_H_1_0 << BIT_SHIFT_LOCKDET_VREF_H_1_0)
+#define BIT_CLEAR_LOCKDET_VREF_H_1_0(x) ((x) & (~BITS_LOCKDET_VREF_H_1_0))
+#define BIT_GET_LOCKDET_VREF_H_1_0(x)                                          \
+	(((x) >> BIT_SHIFT_LOCKDET_VREF_H_1_0) & BIT_MASK_LOCKDET_VREF_H_1_0)
+#define BIT_SET_LOCKDET_VREF_H_1_0(x, v)                                       \
+	(BIT_CLEAR_LOCKDET_VREF_H_1_0(x) | BIT_LOCKDET_VREF_H_1_0(v))
+
+#define BIT_SHIFT_LDO_SEL_1_0 16
+#define BIT_MASK_LDO_SEL_1_0 0x3
+#define BIT_LDO_SEL_1_0(x)                                                     \
+	(((x) & BIT_MASK_LDO_SEL_1_0) << BIT_SHIFT_LDO_SEL_1_0)
+#define BITS_LDO_SEL_1_0 (BIT_MASK_LDO_SEL_1_0 << BIT_SHIFT_LDO_SEL_1_0)
+#define BIT_CLEAR_LDO_SEL_1_0(x) ((x) & (~BITS_LDO_SEL_1_0))
+#define BIT_GET_LDO_SEL_1_0(x)                                                 \
+	(((x) >> BIT_SHIFT_LDO_SEL_1_0) & BIT_MASK_LDO_SEL_1_0)
+#define BIT_SET_LDO_SEL_1_0(x, v)                                              \
+	(BIT_CLEAR_LDO_SEL_1_0(x) | BIT_LDO_SEL_1_0(v))
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_ANAPAR_MAC_0			(Offset 0x1018) */
+
+#define BIT_SHIFT_REG_LPF_C1 15
+#define BIT_MASK_REG_LPF_C1 0x7
+#define BIT_REG_LPF_C1(x) (((x) & BIT_MASK_REG_LPF_C1) << BIT_SHIFT_REG_LPF_C1)
+#define BITS_REG_LPF_C1 (BIT_MASK_REG_LPF_C1 << BIT_SHIFT_REG_LPF_C1)
+#define BIT_CLEAR_REG_LPF_C1(x) ((x) & (~BITS_REG_LPF_C1))
+#define BIT_GET_REG_LPF_C1(x)                                                  \
+	(((x) >> BIT_SHIFT_REG_LPF_C1) & BIT_MASK_REG_LPF_C1)
+#define BIT_SET_REG_LPF_C1(x, v) (BIT_CLEAR_REG_LPF_C1(x) | BIT_REG_LPF_C1(v))
+
+#define BIT_SHIFT_REG_LDO_SEL_V1 13
+#define BIT_MASK_REG_LDO_SEL_V1 0x3
+#define BIT_REG_LDO_SEL_V1(x)                                                  \
+	(((x) & BIT_MASK_REG_LDO_SEL_V1) << BIT_SHIFT_REG_LDO_SEL_V1)
+#define BITS_REG_LDO_SEL_V1                                                    \
+	(BIT_MASK_REG_LDO_SEL_V1 << BIT_SHIFT_REG_LDO_SEL_V1)
+#define BIT_CLEAR_REG_LDO_SEL_V1(x) ((x) & (~BITS_REG_LDO_SEL_V1))
+#define BIT_GET_REG_LDO_SEL_V1(x)                                              \
+	(((x) >> BIT_SHIFT_REG_LDO_SEL_V1) & BIT_MASK_REG_LDO_SEL_V1)
+#define BIT_SET_REG_LDO_SEL_V1(x, v)                                           \
+	(BIT_CLEAR_REG_LDO_SEL_V1(x) | BIT_REG_LDO_SEL_V1(v))
+
+#define BIT_REG_CP_ICPX2 BIT(12)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_ANAPAR_MAC_0			(Offset 0x1018) */
+
+#define BIT_SHIFT_IOFFSET_5_0 10
+#define BIT_MASK_IOFFSET_5_0 0x3f
+#define BIT_IOFFSET_5_0(x)                                                     \
+	(((x) & BIT_MASK_IOFFSET_5_0) << BIT_SHIFT_IOFFSET_5_0)
+#define BITS_IOFFSET_5_0 (BIT_MASK_IOFFSET_5_0 << BIT_SHIFT_IOFFSET_5_0)
+#define BIT_CLEAR_IOFFSET_5_0(x) ((x) & (~BITS_IOFFSET_5_0))
+#define BIT_GET_IOFFSET_5_0(x)                                                 \
+	(((x) >> BIT_SHIFT_IOFFSET_5_0) & BIT_MASK_IOFFSET_5_0)
+#define BIT_SET_IOFFSET_5_0(x, v)                                              \
+	(BIT_CLEAR_IOFFSET_5_0(x) | BIT_IOFFSET_5_0(v))
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_ANAPAR_MAC_0			(Offset 0x1018) */
+
+#define BIT_SHIFT_REG_CP_ICP_SEL_FAST 9
+#define BIT_MASK_REG_CP_ICP_SEL_FAST 0x7
+#define BIT_REG_CP_ICP_SEL_FAST(x)                                             \
+	(((x) & BIT_MASK_REG_CP_ICP_SEL_FAST) << BIT_SHIFT_REG_CP_ICP_SEL_FAST)
+#define BITS_REG_CP_ICP_SEL_FAST                                               \
+	(BIT_MASK_REG_CP_ICP_SEL_FAST << BIT_SHIFT_REG_CP_ICP_SEL_FAST)
+#define BIT_CLEAR_REG_CP_ICP_SEL_FAST(x) ((x) & (~BITS_REG_CP_ICP_SEL_FAST))
+#define BIT_GET_REG_CP_ICP_SEL_FAST(x)                                         \
+	(((x) >> BIT_SHIFT_REG_CP_ICP_SEL_FAST) & BIT_MASK_REG_CP_ICP_SEL_FAST)
+#define BIT_SET_REG_CP_ICP_SEL_FAST(x, v)                                      \
+	(BIT_CLEAR_REG_CP_ICP_SEL_FAST(x) | BIT_REG_CP_ICP_SEL_FAST(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_ANAPAR_MAC_0			(Offset 0x1018) */
+
+#define BIT_CP_ICPX2 BIT(9)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_ANAPAR_MAC_0			(Offset 0x1018) */
+
+#define BIT_GM_STEP BIT(7)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_ANAPAR_MAC_0			(Offset 0x1018) */
+
+#define BIT_SHIFT_REG_CP_ICP_SEL 6
+#define BIT_MASK_REG_CP_ICP_SEL 0x7
+#define BIT_REG_CP_ICP_SEL(x)                                                  \
+	(((x) & BIT_MASK_REG_CP_ICP_SEL) << BIT_SHIFT_REG_CP_ICP_SEL)
+#define BITS_REG_CP_ICP_SEL                                                    \
+	(BIT_MASK_REG_CP_ICP_SEL << BIT_SHIFT_REG_CP_ICP_SEL)
+#define BIT_CLEAR_REG_CP_ICP_SEL(x) ((x) & (~BITS_REG_CP_ICP_SEL))
+#define BIT_GET_REG_CP_ICP_SEL(x)                                              \
+	(((x) >> BIT_SHIFT_REG_CP_ICP_SEL) & BIT_MASK_REG_CP_ICP_SEL)
+#define BIT_SET_REG_CP_ICP_SEL(x, v)                                           \
+	(BIT_CLEAR_REG_CP_ICP_SEL(x) | BIT_REG_CP_ICP_SEL(v))
+
+#define BIT_SHIFT_REG_IB_PI 4
+#define BIT_MASK_REG_IB_PI 0x3
+#define BIT_REG_IB_PI(x) (((x) & BIT_MASK_REG_IB_PI) << BIT_SHIFT_REG_IB_PI)
+#define BITS_REG_IB_PI (BIT_MASK_REG_IB_PI << BIT_SHIFT_REG_IB_PI)
+#define BIT_CLEAR_REG_IB_PI(x) ((x) & (~BITS_REG_IB_PI))
+#define BIT_GET_REG_IB_PI(x) (((x) >> BIT_SHIFT_REG_IB_PI) & BIT_MASK_REG_IB_PI)
+#define BIT_SET_REG_IB_PI(x, v) (BIT_CLEAR_REG_IB_PI(x) | BIT_REG_IB_PI(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_ANAPAR_MAC_0			(Offset 0x1018) */
+
+#define BIT_SHIFT_CP_ICP_SEL_4_0 4
+#define BIT_MASK_CP_ICP_SEL_4_0 0x1f
+#define BIT_CP_ICP_SEL_4_0(x)                                                  \
+	(((x) & BIT_MASK_CP_ICP_SEL_4_0) << BIT_SHIFT_CP_ICP_SEL_4_0)
+#define BITS_CP_ICP_SEL_4_0                                                    \
+	(BIT_MASK_CP_ICP_SEL_4_0 << BIT_SHIFT_CP_ICP_SEL_4_0)
+#define BIT_CLEAR_CP_ICP_SEL_4_0(x) ((x) & (~BITS_CP_ICP_SEL_4_0))
+#define BIT_GET_CP_ICP_SEL_4_0(x)                                              \
+	(((x) >> BIT_SHIFT_CP_ICP_SEL_4_0) & BIT_MASK_CP_ICP_SEL_4_0)
+#define BIT_SET_CP_ICP_SEL_4_0(x, v)                                           \
+	(BIT_CLEAR_CP_ICP_SEL_4_0(x) | BIT_CP_ICP_SEL_4_0(v))
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_ANAPAR_MAC_0			(Offset 0x1018) */
+
+#define BIT_LDO2PWRCUT BIT(3)
+#define BIT_VPULSE_LDO BIT(2)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_ANAPAR_MAC_0			(Offset 0x1018) */
+
+#define BIT_SHIFT_IB_PI_1_0 2
+#define BIT_MASK_IB_PI_1_0 0x3
+#define BIT_IB_PI_1_0(x) (((x) & BIT_MASK_IB_PI_1_0) << BIT_SHIFT_IB_PI_1_0)
+#define BITS_IB_PI_1_0 (BIT_MASK_IB_PI_1_0 << BIT_SHIFT_IB_PI_1_0)
+#define BIT_CLEAR_IB_PI_1_0(x) ((x) & (~BITS_IB_PI_1_0))
+#define BIT_GET_IB_PI_1_0(x) (((x) >> BIT_SHIFT_IB_PI_1_0) & BIT_MASK_IB_PI_1_0)
+#define BIT_SET_IB_PI_1_0(x, v) (BIT_CLEAR_IB_PI_1_0(x) | BIT_IB_PI_1_0(v))
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_ANAPAR_MAC_0			(Offset 0x1018) */
+
+#define BIT_OFFSET_PLUS BIT(1)
+
+#define BIT_SHIFT_LDO_VSEL 0
+#define BIT_MASK_LDO_VSEL 0x3
+#define BIT_LDO_VSEL(x) (((x) & BIT_MASK_LDO_VSEL) << BIT_SHIFT_LDO_VSEL)
+#define BITS_LDO_VSEL (BIT_MASK_LDO_VSEL << BIT_SHIFT_LDO_VSEL)
+#define BIT_CLEAR_LDO_VSEL(x) ((x) & (~BITS_LDO_VSEL))
+#define BIT_GET_LDO_VSEL(x) (((x) >> BIT_SHIFT_LDO_VSEL) & BIT_MASK_LDO_VSEL)
+#define BIT_SET_LDO_VSEL(x, v) (BIT_CLEAR_LDO_VSEL(x) | BIT_LDO_VSEL(v))
+
+#define BIT_RESET_N BIT(0)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_ANAPAR_MAC_1			(Offset 0x101C) */
+
+#define BIT_SHIFT_REG_CK_MON_SEL 29
+#define BIT_MASK_REG_CK_MON_SEL 0x7
+#define BIT_REG_CK_MON_SEL(x)                                                  \
+	(((x) & BIT_MASK_REG_CK_MON_SEL) << BIT_SHIFT_REG_CK_MON_SEL)
+#define BITS_REG_CK_MON_SEL                                                    \
+	(BIT_MASK_REG_CK_MON_SEL << BIT_SHIFT_REG_CK_MON_SEL)
+#define BIT_CLEAR_REG_CK_MON_SEL(x) ((x) & (~BITS_REG_CK_MON_SEL))
+#define BIT_GET_REG_CK_MON_SEL(x)                                              \
+	(((x) >> BIT_SHIFT_REG_CK_MON_SEL) & BIT_MASK_REG_CK_MON_SEL)
+#define BIT_SET_REG_CK_MON_SEL(x, v)                                           \
+	(BIT_CLEAR_REG_CK_MON_SEL(x) | BIT_REG_CK_MON_SEL(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_ANAPAR_MAC_1			(Offset 0x101C) */
+
+#define BIT_SHIFT_CKX_USB_IB_SEL 29
+#define BIT_MASK_CKX_USB_IB_SEL 0x7
+#define BIT_CKX_USB_IB_SEL(x)                                                  \
+	(((x) & BIT_MASK_CKX_USB_IB_SEL) << BIT_SHIFT_CKX_USB_IB_SEL)
+#define BITS_CKX_USB_IB_SEL                                                    \
+	(BIT_MASK_CKX_USB_IB_SEL << BIT_SHIFT_CKX_USB_IB_SEL)
+#define BIT_CLEAR_CKX_USB_IB_SEL(x) ((x) & (~BITS_CKX_USB_IB_SEL))
+#define BIT_GET_CKX_USB_IB_SEL(x)                                              \
+	(((x) >> BIT_SHIFT_CKX_USB_IB_SEL) & BIT_MASK_CKX_USB_IB_SEL)
+#define BIT_SET_CKX_USB_IB_SEL(x, v)                                           \
+	(BIT_CLEAR_CKX_USB_IB_SEL(x) | BIT_CKX_USB_IB_SEL(v))
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_ANAPAR_MAC_1			(Offset 0x101C) */
+
+#define BIT_REG_CK_MON_EN BIT(28)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_ANAPAR_MAC_1			(Offset 0x101C) */
+
+#define BIT_PFD_DN_GATED BIT(28)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_ANAPAR_MAC_1			(Offset 0x101C) */
+
+#define BIT_REG_XTAL_FREQ_SEL BIT(27)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_ANAPAR_MAC_1			(Offset 0x101C) */
+
+#define BIT_PFD_UP_GATED BIT(27)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_ANAPAR_MAC_1			(Offset 0x101C) */
+
+#define BIT_REG_XTAL_EDGE_SEL BIT(26)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_ANAPAR_MAC_1			(Offset 0x101C) */
+
+#define BIT_PFD_RESET_GATED BIT(26)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_ANAPAR_MAC_1			(Offset 0x101C) */
+
+#define BIT_REG_VCO_KVCO BIT(25)
+#define BIT_REG_SDM_EDGE_SEL BIT(24)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_ANAPAR_MAC_1			(Offset 0x101C) */
+
+#define BIT_SHIFT_PFD_OUT_DRV_1_0 24
+#define BIT_MASK_PFD_OUT_DRV_1_0 0x3
+#define BIT_PFD_OUT_DRV_1_0(x)                                                 \
+	(((x) & BIT_MASK_PFD_OUT_DRV_1_0) << BIT_SHIFT_PFD_OUT_DRV_1_0)
+#define BITS_PFD_OUT_DRV_1_0                                                   \
+	(BIT_MASK_PFD_OUT_DRV_1_0 << BIT_SHIFT_PFD_OUT_DRV_1_0)
+#define BIT_CLEAR_PFD_OUT_DRV_1_0(x) ((x) & (~BITS_PFD_OUT_DRV_1_0))
+#define BIT_GET_PFD_OUT_DRV_1_0(x)                                             \
+	(((x) >> BIT_SHIFT_PFD_OUT_DRV_1_0) & BIT_MASK_PFD_OUT_DRV_1_0)
+#define BIT_SET_PFD_OUT_DRV_1_0(x, v)                                          \
+	(BIT_CLEAR_PFD_OUT_DRV_1_0(x) | BIT_PFD_OUT_DRV_1_0(v))
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_ANAPAR_MAC_1			(Offset 0x101C) */
+
+#define BIT_REG_SDM_CK_SEL BIT(23)
+#define BIT_REG_SDM_CK_GATED BIT(22)
+#define BIT_REG_PFD_RESET_GATED BIT(21)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_ANAPAR_MAC_1			(Offset 0x101C) */
+
+#define BIT_SHIFT_LPF_TIEMID_2_0 20
+#define BIT_MASK_LPF_TIEMID_2_0 0x7
+#define BIT_LPF_TIEMID_2_0(x)                                                  \
+	(((x) & BIT_MASK_LPF_TIEMID_2_0) << BIT_SHIFT_LPF_TIEMID_2_0)
+#define BITS_LPF_TIEMID_2_0                                                    \
+	(BIT_MASK_LPF_TIEMID_2_0 << BIT_SHIFT_LPF_TIEMID_2_0)
+#define BIT_CLEAR_LPF_TIEMID_2_0(x) ((x) & (~BITS_LPF_TIEMID_2_0))
+#define BIT_GET_LPF_TIEMID_2_0(x)                                              \
+	(((x) >> BIT_SHIFT_LPF_TIEMID_2_0) & BIT_MASK_LPF_TIEMID_2_0)
+#define BIT_SET_LPF_TIEMID_2_0(x, v)                                           \
+	(BIT_CLEAR_LPF_TIEMID_2_0(x) | BIT_LPF_TIEMID_2_0(v))
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_ANAPAR_MAC_1			(Offset 0x101C) */
+
+#define BIT_SHIFT_REG_LPF_R3_FAST 16
+#define BIT_MASK_REG_LPF_R3_FAST 0x1f
+#define BIT_REG_LPF_R3_FAST(x)                                                 \
+	(((x) & BIT_MASK_REG_LPF_R3_FAST) << BIT_SHIFT_REG_LPF_R3_FAST)
+#define BITS_REG_LPF_R3_FAST                                                   \
+	(BIT_MASK_REG_LPF_R3_FAST << BIT_SHIFT_REG_LPF_R3_FAST)
+#define BIT_CLEAR_REG_LPF_R3_FAST(x) ((x) & (~BITS_REG_LPF_R3_FAST))
+#define BIT_GET_REG_LPF_R3_FAST(x)                                             \
+	(((x) >> BIT_SHIFT_REG_LPF_R3_FAST) & BIT_MASK_REG_LPF_R3_FAST)
+#define BIT_SET_REG_LPF_R3_FAST(x, v)                                          \
+	(BIT_CLEAR_REG_LPF_R3_FAST(x) | BIT_REG_LPF_R3_FAST(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_ANAPAR_MAC_1			(Offset 0x101C) */
+
+#define BIT_SHIFT_LPF_R3_4_0 15
+#define BIT_MASK_LPF_R3_4_0 0x1f
+#define BIT_LPF_R3_4_0(x) (((x) & BIT_MASK_LPF_R3_4_0) << BIT_SHIFT_LPF_R3_4_0)
+#define BITS_LPF_R3_4_0 (BIT_MASK_LPF_R3_4_0 << BIT_SHIFT_LPF_R3_4_0)
+#define BIT_CLEAR_LPF_R3_4_0(x) ((x) & (~BITS_LPF_R3_4_0))
+#define BIT_GET_LPF_R3_4_0(x)                                                  \
+	(((x) >> BIT_SHIFT_LPF_R3_4_0) & BIT_MASK_LPF_R3_4_0)
+#define BIT_SET_LPF_R3_4_0(x, v) (BIT_CLEAR_LPF_R3_4_0(x) | BIT_LPF_R3_4_0(v))
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_ANAPAR_MAC_1			(Offset 0x101C) */
+
+#define BIT_SHIFT_REG_LPF_R2_FAST 11
+#define BIT_MASK_REG_LPF_R2_FAST 0x1f
+#define BIT_REG_LPF_R2_FAST(x)                                                 \
+	(((x) & BIT_MASK_REG_LPF_R2_FAST) << BIT_SHIFT_REG_LPF_R2_FAST)
+#define BITS_REG_LPF_R2_FAST                                                   \
+	(BIT_MASK_REG_LPF_R2_FAST << BIT_SHIFT_REG_LPF_R2_FAST)
+#define BIT_CLEAR_REG_LPF_R2_FAST(x) ((x) & (~BITS_REG_LPF_R2_FAST))
+#define BIT_GET_REG_LPF_R2_FAST(x)                                             \
+	(((x) >> BIT_SHIFT_REG_LPF_R2_FAST) & BIT_MASK_REG_LPF_R2_FAST)
+#define BIT_SET_REG_LPF_R2_FAST(x, v)                                          \
+	(BIT_CLEAR_REG_LPF_R2_FAST(x) | BIT_REG_LPF_R2_FAST(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_ANAPAR_MAC_1			(Offset 0x101C) */
+
+#define BIT_SHIFT_LPF_R2_4_0 10
+#define BIT_MASK_LPF_R2_4_0 0x1f
+#define BIT_LPF_R2_4_0(x) (((x) & BIT_MASK_LPF_R2_4_0) << BIT_SHIFT_LPF_R2_4_0)
+#define BITS_LPF_R2_4_0 (BIT_MASK_LPF_R2_4_0 << BIT_SHIFT_LPF_R2_4_0)
+#define BIT_CLEAR_LPF_R2_4_0(x) ((x) & (~BITS_LPF_R2_4_0))
+#define BIT_GET_LPF_R2_4_0(x)                                                  \
+	(((x) >> BIT_SHIFT_LPF_R2_4_0) & BIT_MASK_LPF_R2_4_0)
+#define BIT_SET_LPF_R2_4_0(x, v) (BIT_CLEAR_LPF_R2_4_0(x) | BIT_LPF_R2_4_0(v))
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_ANAPAR_MAC_1			(Offset 0x101C) */
+
+#define BIT_SHIFT_REG_LPF_C3_FAST 8
+#define BIT_MASK_REG_LPF_C3_FAST 0x7
+#define BIT_REG_LPF_C3_FAST(x)                                                 \
+	(((x) & BIT_MASK_REG_LPF_C3_FAST) << BIT_SHIFT_REG_LPF_C3_FAST)
+#define BITS_REG_LPF_C3_FAST                                                   \
+	(BIT_MASK_REG_LPF_C3_FAST << BIT_SHIFT_REG_LPF_C3_FAST)
+#define BIT_CLEAR_REG_LPF_C3_FAST(x) ((x) & (~BITS_REG_LPF_C3_FAST))
+#define BIT_GET_REG_LPF_C3_FAST(x)                                             \
+	(((x) >> BIT_SHIFT_REG_LPF_C3_FAST) & BIT_MASK_REG_LPF_C3_FAST)
+#define BIT_SET_REG_LPF_C3_FAST(x, v)                                          \
+	(BIT_CLEAR_REG_LPF_C3_FAST(x) | BIT_REG_LPF_C3_FAST(v))
+
+#define BIT_SHIFT_REG_LPF_C2_FAST 5
+#define BIT_MASK_REG_LPF_C2_FAST 0x7
+#define BIT_REG_LPF_C2_FAST(x)                                                 \
+	(((x) & BIT_MASK_REG_LPF_C2_FAST) << BIT_SHIFT_REG_LPF_C2_FAST)
+#define BITS_REG_LPF_C2_FAST                                                   \
+	(BIT_MASK_REG_LPF_C2_FAST << BIT_SHIFT_REG_LPF_C2_FAST)
+#define BIT_CLEAR_REG_LPF_C2_FAST(x) ((x) & (~BITS_REG_LPF_C2_FAST))
+#define BIT_GET_REG_LPF_C2_FAST(x)                                             \
+	(((x) >> BIT_SHIFT_REG_LPF_C2_FAST) & BIT_MASK_REG_LPF_C2_FAST)
+#define BIT_SET_REG_LPF_C2_FAST(x, v)                                          \
+	(BIT_CLEAR_REG_LPF_C2_FAST(x) | BIT_REG_LPF_C2_FAST(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_ANAPAR_MAC_1			(Offset 0x101C) */
+
+#define BIT_SHIFT_LPF_C3_5_0 4
+#define BIT_MASK_LPF_C3_5_0 0x3f
+#define BIT_LPF_C3_5_0(x) (((x) & BIT_MASK_LPF_C3_5_0) << BIT_SHIFT_LPF_C3_5_0)
+#define BITS_LPF_C3_5_0 (BIT_MASK_LPF_C3_5_0 << BIT_SHIFT_LPF_C3_5_0)
+#define BIT_CLEAR_LPF_C3_5_0(x) ((x) & (~BITS_LPF_C3_5_0))
+#define BIT_GET_LPF_C3_5_0(x)                                                  \
+	(((x) >> BIT_SHIFT_LPF_C3_5_0) & BIT_MASK_LPF_C3_5_0)
+#define BIT_SET_LPF_C3_5_0(x, v) (BIT_CLEAR_LPF_C3_5_0(x) | BIT_LPF_C3_5_0(v))
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_ANAPAR_MAC_1			(Offset 0x101C) */
+
+#define BIT_SHIFT_REG_LPF_C1_FAST 2
+#define BIT_MASK_REG_LPF_C1_FAST 0x7
+#define BIT_REG_LPF_C1_FAST(x)                                                 \
+	(((x) & BIT_MASK_REG_LPF_C1_FAST) << BIT_SHIFT_REG_LPF_C1_FAST)
+#define BITS_REG_LPF_C1_FAST                                                   \
+	(BIT_MASK_REG_LPF_C1_FAST << BIT_SHIFT_REG_LPF_C1_FAST)
+#define BIT_CLEAR_REG_LPF_C1_FAST(x) ((x) & (~BITS_REG_LPF_C1_FAST))
+#define BIT_GET_REG_LPF_C1_FAST(x)                                             \
+	(((x) >> BIT_SHIFT_REG_LPF_C1_FAST) & BIT_MASK_REG_LPF_C1_FAST)
+#define BIT_SET_REG_LPF_C1_FAST(x, v)                                          \
+	(BIT_CLEAR_REG_LPF_C1_FAST(x) | BIT_REG_LPF_C1_FAST(v))
+
+#define BIT_SHIFT_REG_LPF_R3_V1 0
+#define BIT_MASK_REG_LPF_R3_V1 0x3
+#define BIT_REG_LPF_R3_V1(x)                                                   \
+	(((x) & BIT_MASK_REG_LPF_R3_V1) << BIT_SHIFT_REG_LPF_R3_V1)
+#define BITS_REG_LPF_R3_V1 (BIT_MASK_REG_LPF_R3_V1 << BIT_SHIFT_REG_LPF_R3_V1)
+#define BIT_CLEAR_REG_LPF_R3_V1(x) ((x) & (~BITS_REG_LPF_R3_V1))
+#define BIT_GET_REG_LPF_R3_V1(x)                                               \
+	(((x) >> BIT_SHIFT_REG_LPF_R3_V1) & BIT_MASK_REG_LPF_R3_V1)
+#define BIT_SET_REG_LPF_R3_V1(x, v)                                            \
+	(BIT_CLEAR_REG_LPF_R3_V1(x) | BIT_REG_LPF_R3_V1(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_ANAPAR_MAC_1			(Offset 0x101C) */
+
+#define BIT_SHIFT_LPF_C2_5_2 0
+#define BIT_MASK_LPF_C2_5_2 0xf
+#define BIT_LPF_C2_5_2(x) (((x) & BIT_MASK_LPF_C2_5_2) << BIT_SHIFT_LPF_C2_5_2)
+#define BITS_LPF_C2_5_2 (BIT_MASK_LPF_C2_5_2 << BIT_SHIFT_LPF_C2_5_2)
+#define BIT_CLEAR_LPF_C2_5_2(x) ((x) & (~BITS_LPF_C2_5_2))
+#define BIT_GET_LPF_C2_5_2(x)                                                  \
+	(((x) >> BIT_SHIFT_LPF_C2_5_2) & BIT_MASK_LPF_C2_5_2)
+#define BIT_SET_LPF_C2_5_2(x, v) (BIT_CLEAR_LPF_C2_5_2(x) | BIT_LPF_C2_5_2(v))
+
+/* 2 REG_ANAPAR_MAC_2			(Offset 0x1020) */
+
+#define BIT_CK_PHASE_SEL BIT(31)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_ANAPAR_MAC_2			(Offset 0x1020) */
+
+#define BIT_SHIFT_AGPIO_DRV_V1 30
+#define BIT_MASK_AGPIO_DRV_V1 0x3
+#define BIT_AGPIO_DRV_V1(x)                                                    \
+	(((x) & BIT_MASK_AGPIO_DRV_V1) << BIT_SHIFT_AGPIO_DRV_V1)
+#define BITS_AGPIO_DRV_V1 (BIT_MASK_AGPIO_DRV_V1 << BIT_SHIFT_AGPIO_DRV_V1)
+#define BIT_CLEAR_AGPIO_DRV_V1(x) ((x) & (~BITS_AGPIO_DRV_V1))
+#define BIT_GET_AGPIO_DRV_V1(x)                                                \
+	(((x) >> BIT_SHIFT_AGPIO_DRV_V1) & BIT_MASK_AGPIO_DRV_V1)
+#define BIT_SET_AGPIO_DRV_V1(x, v)                                             \
+	(BIT_CLEAR_AGPIO_DRV_V1(x) | BIT_AGPIO_DRV_V1(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_ANAPAR_MAC_2			(Offset 0x1020) */
+
+#define BIT_CK960M_EN BIT(30)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_ANAPAR_MAC_2			(Offset 0x1020) */
+
+#define BIT_AGPIO_GPO_V1 BIT(29)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_ANAPAR_MAC_2			(Offset 0x1020) */
+
+#define BIT_CK640M_EN BIT(29)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_ANAPAR_MAC_2			(Offset 0x1020) */
+
+#define BIT_AGPIO_GPE_V1 BIT(28)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_ANAPAR_MAC_2			(Offset 0x1020) */
+
+#define BIT_CK240M_EN BIT(28)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_ANAPAR_MAC_2			(Offset 0x1020) */
+
+#define BIT_SEL_CLK BIT(27)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_ANAPAR_MAC_2			(Offset 0x1020) */
+
+#define BIT_SHIFT_CK_MON_SEL_2_0 25
+#define BIT_MASK_CK_MON_SEL_2_0 0x7
+#define BIT_CK_MON_SEL_2_0(x)                                                  \
+	(((x) & BIT_MASK_CK_MON_SEL_2_0) << BIT_SHIFT_CK_MON_SEL_2_0)
+#define BITS_CK_MON_SEL_2_0                                                    \
+	(BIT_MASK_CK_MON_SEL_2_0 << BIT_SHIFT_CK_MON_SEL_2_0)
+#define BIT_CLEAR_CK_MON_SEL_2_0(x) ((x) & (~BITS_CK_MON_SEL_2_0))
+#define BIT_GET_CK_MON_SEL_2_0(x)                                              \
+	(((x) >> BIT_SHIFT_CK_MON_SEL_2_0) & BIT_MASK_CK_MON_SEL_2_0)
+#define BIT_SET_CK_MON_SEL_2_0(x, v)                                           \
+	(BIT_CLEAR_CK_MON_SEL_2_0(x) | BIT_CK_MON_SEL_2_0(v))
+
+#define BIT_CK_MON_EN_V1 BIT(24)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_ANAPAR_MAC_2			(Offset 0x1020) */
+
+#define BIT_SHIFT_LS_XTAL_SEL 23
+#define BIT_MASK_LS_XTAL_SEL 0xf
+#define BIT_LS_XTAL_SEL(x)                                                     \
+	(((x) & BIT_MASK_LS_XTAL_SEL) << BIT_SHIFT_LS_XTAL_SEL)
+#define BITS_LS_XTAL_SEL (BIT_MASK_LS_XTAL_SEL << BIT_SHIFT_LS_XTAL_SEL)
+#define BIT_CLEAR_LS_XTAL_SEL(x) ((x) & (~BITS_LS_XTAL_SEL))
+#define BIT_GET_LS_XTAL_SEL(x)                                                 \
+	(((x) >> BIT_SHIFT_LS_XTAL_SEL) & BIT_MASK_LS_XTAL_SEL)
+#define BIT_SET_LS_XTAL_SEL(x, v)                                              \
+	(BIT_CLEAR_LS_XTAL_SEL(x) | BIT_LS_XTAL_SEL(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_ANAPAR_MAC_2			(Offset 0x1020) */
+
+#define BIT_XTAL_SOURCE_SEL BIT(23)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_ANAPAR_MAC_2			(Offset 0x1020) */
+
+#define BIT_LS_SDM_ORDER_V1 BIT(22)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_ANAPAR_MAC_2			(Offset 0x1020) */
+
+#define BIT_XTAL_FREQ_SEL BIT(22)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_ANAPAR_MAC_2			(Offset 0x1020) */
+
+#define BIT_LS_DELAY_PH BIT(21)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_ANAPAR_MAC_2			(Offset 0x1020) */
+
+#define BIT_XTAL_EDGE_SEL BIT(21)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_ANAPAR_MAC_2			(Offset 0x1020) */
+
+#define BIT_DIVIDER_SEL BIT(20)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_ANAPAR_MAC_2			(Offset 0x1020) */
+
+#define BIT_XTAL_BUF_SEL BIT(20)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_ANAPAR_MAC_2			(Offset 0x1020) */
+
+#define BIT_SHIFT_PCODE 15
+#define BIT_MASK_PCODE 0x1f
+#define BIT_PCODE(x) (((x) & BIT_MASK_PCODE) << BIT_SHIFT_PCODE)
+#define BITS_PCODE (BIT_MASK_PCODE << BIT_SHIFT_PCODE)
+#define BIT_CLEAR_PCODE(x) ((x) & (~BITS_PCODE))
+#define BIT_GET_PCODE(x) (((x) >> BIT_SHIFT_PCODE) & BIT_MASK_PCODE)
+#define BIT_SET_PCODE(x, v) (BIT_CLEAR_PCODE(x) | BIT_PCODE(v))
+
+#define BIT_SHIFT_NCODE 7
+#define BIT_MASK_NCODE 0xff
+#define BIT_NCODE(x) (((x) & BIT_MASK_NCODE) << BIT_SHIFT_NCODE)
+#define BITS_NCODE (BIT_MASK_NCODE << BIT_SHIFT_NCODE)
+#define BIT_CLEAR_NCODE(x) ((x) & (~BITS_NCODE))
+#define BIT_GET_NCODE(x) (((x) >> BIT_SHIFT_NCODE) & BIT_MASK_NCODE)
+#define BIT_SET_NCODE(x, v) (BIT_CLEAR_NCODE(x) | BIT_NCODE(v))
+
+#define BIT_REG_BEACON BIT(6)
+#define BIT_REG_MBIASE BIT(5)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_ANAPAR_MAC_2			(Offset 0x1020) */
+
+#define BIT_SHIFT_VCO_CV_7_0 4
+#define BIT_MASK_VCO_CV_7_0 0xff
+#define BIT_VCO_CV_7_0(x) (((x) & BIT_MASK_VCO_CV_7_0) << BIT_SHIFT_VCO_CV_7_0)
+#define BITS_VCO_CV_7_0 (BIT_MASK_VCO_CV_7_0 << BIT_SHIFT_VCO_CV_7_0)
+#define BIT_CLEAR_VCO_CV_7_0(x) ((x) & (~BITS_VCO_CV_7_0))
+#define BIT_GET_VCO_CV_7_0(x)                                                  \
+	(((x) >> BIT_SHIFT_VCO_CV_7_0) & BIT_MASK_VCO_CV_7_0)
+#define BIT_SET_VCO_CV_7_0(x, v) (BIT_CLEAR_VCO_CV_7_0(x) | BIT_VCO_CV_7_0(v))
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_ANAPAR_MAC_2			(Offset 0x1020) */
+
+#define BIT_SHIFT_REG_FAST_SEL 3
+#define BIT_MASK_REG_FAST_SEL 0x3
+#define BIT_REG_FAST_SEL(x)                                                    \
+	(((x) & BIT_MASK_REG_FAST_SEL) << BIT_SHIFT_REG_FAST_SEL)
+#define BITS_REG_FAST_SEL (BIT_MASK_REG_FAST_SEL << BIT_SHIFT_REG_FAST_SEL)
+#define BIT_CLEAR_REG_FAST_SEL(x) ((x) & (~BITS_REG_FAST_SEL))
+#define BIT_GET_REG_FAST_SEL(x)                                                \
+	(((x) >> BIT_SHIFT_REG_FAST_SEL) & BIT_MASK_REG_FAST_SEL)
+#define BIT_SET_REG_FAST_SEL(x, v)                                             \
+	(BIT_CLEAR_REG_FAST_SEL(x) | BIT_REG_FAST_SEL(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_ANAPAR_MAC_2			(Offset 0x1020) */
+
+#define BIT_VCO_KVCO BIT(3)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_ANAPAR_MAC_2			(Offset 0x1020) */
+
+#define BIT_REG_CK960M_EN BIT(2)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_ANAPAR_MAC_2			(Offset 0x1020) */
+
+#define BIT_SDM_EDGE_SEL BIT(2)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_ANAPAR_MAC_2			(Offset 0x1020) */
+
+#define BIT_REG_CK320M_EN BIT(1)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_ANAPAR_MAC_2			(Offset 0x1020) */
+
+#define BIT_SDM_CK_SEL BIT(1)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_ANAPAR_MAC_2			(Offset 0x1020) */
+
+#define BIT_REG_CK_5M_EN BIT(0)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_ANAPAR_MAC_2			(Offset 0x1020) */
+
+#define BIT_SDM_CK_GATED BIT(0)
+
+/* 2 REG_ANAPAR_MAC_3			(Offset 0x1024) */
+
+#define BIT_SHIFT_LCK_WAIT_CYCLE_2_0 28
+#define BIT_MASK_LCK_WAIT_CYCLE_2_0 0x7
+#define BIT_LCK_WAIT_CYCLE_2_0(x)                                              \
+	(((x) & BIT_MASK_LCK_WAIT_CYCLE_2_0) << BIT_SHIFT_LCK_WAIT_CYCLE_2_0)
+#define BITS_LCK_WAIT_CYCLE_2_0                                                \
+	(BIT_MASK_LCK_WAIT_CYCLE_2_0 << BIT_SHIFT_LCK_WAIT_CYCLE_2_0)
+#define BIT_CLEAR_LCK_WAIT_CYCLE_2_0(x) ((x) & (~BITS_LCK_WAIT_CYCLE_2_0))
+#define BIT_GET_LCK_WAIT_CYCLE_2_0(x)                                          \
+	(((x) >> BIT_SHIFT_LCK_WAIT_CYCLE_2_0) & BIT_MASK_LCK_WAIT_CYCLE_2_0)
+#define BIT_SET_LCK_WAIT_CYCLE_2_0(x, v)                                       \
+	(BIT_CLEAR_LCK_WAIT_CYCLE_2_0(x) | BIT_LCK_WAIT_CYCLE_2_0(v))
+
+#define BIT_SHIFT_LCK_VCO_DIVISOR_1_0 26
+#define BIT_MASK_LCK_VCO_DIVISOR_1_0 0x3
+#define BIT_LCK_VCO_DIVISOR_1_0(x)                                             \
+	(((x) & BIT_MASK_LCK_VCO_DIVISOR_1_0) << BIT_SHIFT_LCK_VCO_DIVISOR_1_0)
+#define BITS_LCK_VCO_DIVISOR_1_0                                               \
+	(BIT_MASK_LCK_VCO_DIVISOR_1_0 << BIT_SHIFT_LCK_VCO_DIVISOR_1_0)
+#define BIT_CLEAR_LCK_VCO_DIVISOR_1_0(x) ((x) & (~BITS_LCK_VCO_DIVISOR_1_0))
+#define BIT_GET_LCK_VCO_DIVISOR_1_0(x)                                         \
+	(((x) >> BIT_SHIFT_LCK_VCO_DIVISOR_1_0) & BIT_MASK_LCK_VCO_DIVISOR_1_0)
+#define BIT_SET_LCK_VCO_DIVISOR_1_0(x, v)                                      \
+	(BIT_CLEAR_LCK_VCO_DIVISOR_1_0(x) | BIT_LCK_VCO_DIVISOR_1_0(v))
+
+#define BIT_SHIFT_LCK_SEARCH_MODE_1_0 24
+#define BIT_MASK_LCK_SEARCH_MODE_1_0 0x3
+#define BIT_LCK_SEARCH_MODE_1_0(x)                                             \
+	(((x) & BIT_MASK_LCK_SEARCH_MODE_1_0) << BIT_SHIFT_LCK_SEARCH_MODE_1_0)
+#define BITS_LCK_SEARCH_MODE_1_0                                               \
+	(BIT_MASK_LCK_SEARCH_MODE_1_0 << BIT_SHIFT_LCK_SEARCH_MODE_1_0)
+#define BIT_CLEAR_LCK_SEARCH_MODE_1_0(x) ((x) & (~BITS_LCK_SEARCH_MODE_1_0))
+#define BIT_GET_LCK_SEARCH_MODE_1_0(x)                                         \
+	(((x) >> BIT_SHIFT_LCK_SEARCH_MODE_1_0) & BIT_MASK_LCK_SEARCH_MODE_1_0)
+#define BIT_SET_LCK_SEARCH_MODE_1_0(x, v)                                      \
+	(BIT_CLEAR_LCK_SEARCH_MODE_1_0(x) | BIT_LCK_SEARCH_MODE_1_0(v))
+
+#define BIT_SHIFT_LS_CV_OFFSET_3_0 12
+#define BIT_MASK_LS_CV_OFFSET_3_0 0xf
+#define BIT_LS_CV_OFFSET_3_0(x)                                                \
+	(((x) & BIT_MASK_LS_CV_OFFSET_3_0) << BIT_SHIFT_LS_CV_OFFSET_3_0)
+#define BITS_LS_CV_OFFSET_3_0                                                  \
+	(BIT_MASK_LS_CV_OFFSET_3_0 << BIT_SHIFT_LS_CV_OFFSET_3_0)
+#define BIT_CLEAR_LS_CV_OFFSET_3_0(x) ((x) & (~BITS_LS_CV_OFFSET_3_0))
+#define BIT_GET_LS_CV_OFFSET_3_0(x)                                            \
+	(((x) >> BIT_SHIFT_LS_CV_OFFSET_3_0) & BIT_MASK_LS_CV_OFFSET_3_0)
+#define BIT_SET_LS_CV_OFFSET_3_0(x, v)                                         \
+	(BIT_CLEAR_LS_CV_OFFSET_3_0(x) | BIT_LS_CV_OFFSET_3_0(v))
+
+#define BIT_LS_EN_LC_CK40M BIT(11)
+#define BIT_LS__CV_MANUAL BIT(10)
+#define BIT_LS_PYPASS_PI BIT(9)
+#define BIT_MBIASE BIT(4)
+
+/* 2 REG_ANAPAR_MAC_4			(Offset 0x1028) */
+
+#define BIT_LS_TIE_MID_MODE BIT(28)
+
+#define BIT_SHIFT_LS_SYNC_CYCLE_1_0 26
+#define BIT_MASK_LS_SYNC_CYCLE_1_0 0x3
+#define BIT_LS_SYNC_CYCLE_1_0(x)                                               \
+	(((x) & BIT_MASK_LS_SYNC_CYCLE_1_0) << BIT_SHIFT_LS_SYNC_CYCLE_1_0)
+#define BITS_LS_SYNC_CYCLE_1_0                                                 \
+	(BIT_MASK_LS_SYNC_CYCLE_1_0 << BIT_SHIFT_LS_SYNC_CYCLE_1_0)
+#define BIT_CLEAR_LS_SYNC_CYCLE_1_0(x) ((x) & (~BITS_LS_SYNC_CYCLE_1_0))
+#define BIT_GET_LS_SYNC_CYCLE_1_0(x)                                           \
+	(((x) >> BIT_SHIFT_LS_SYNC_CYCLE_1_0) & BIT_MASK_LS_SYNC_CYCLE_1_0)
+#define BIT_SET_LS_SYNC_CYCLE_1_0(x, v)                                        \
+	(BIT_CLEAR_LS_SYNC_CYCLE_1_0(x) | BIT_LS_SYNC_CYCLE_1_0(v))
+
+#define BIT_LS_SDM_ORDER BIT(25)
+#define BIT_LS_RST_LC_CAL BIT(14)
+#define BIT_LS_RSTB BIT(13)
+#define BIT_LS_POW_LC_CAL_PREP BIT(11)
+
+#define BIT_SHIFT_LCK_XTAL_DIVISOR_1_0 0
+#define BIT_MASK_LCK_XTAL_DIVISOR_1_0 0x3
+#define BIT_LCK_XTAL_DIVISOR_1_0(x)                                            \
+	(((x) & BIT_MASK_LCK_XTAL_DIVISOR_1_0)                                 \
+	 << BIT_SHIFT_LCK_XTAL_DIVISOR_1_0)
+#define BITS_LCK_XTAL_DIVISOR_1_0                                              \
+	(BIT_MASK_LCK_XTAL_DIVISOR_1_0 << BIT_SHIFT_LCK_XTAL_DIVISOR_1_0)
+#define BIT_CLEAR_LCK_XTAL_DIVISOR_1_0(x) ((x) & (~BITS_LCK_XTAL_DIVISOR_1_0))
+#define BIT_GET_LCK_XTAL_DIVISOR_1_0(x)                                        \
+	(((x) >> BIT_SHIFT_LCK_XTAL_DIVISOR_1_0) &                             \
+	 BIT_MASK_LCK_XTAL_DIVISOR_1_0)
+#define BIT_SET_LCK_XTAL_DIVISOR_1_0(x, v)                                     \
+	(BIT_CLEAR_LCK_XTAL_DIVISOR_1_0(x) | BIT_LCK_XTAL_DIVISOR_1_0(v))
+
+/* 2 REG_ANAPAR_MAC_5			(Offset 0x102C) */
+
+#define BIT_SHIFT_LS_XTAL_SEL_3_0 0
+#define BIT_MASK_LS_XTAL_SEL_3_0 0xf
+#define BIT_LS_XTAL_SEL_3_0(x)                                                 \
+	(((x) & BIT_MASK_LS_XTAL_SEL_3_0) << BIT_SHIFT_LS_XTAL_SEL_3_0)
+#define BITS_LS_XTAL_SEL_3_0                                                   \
+	(BIT_MASK_LS_XTAL_SEL_3_0 << BIT_SHIFT_LS_XTAL_SEL_3_0)
+#define BIT_CLEAR_LS_XTAL_SEL_3_0(x) ((x) & (~BITS_LS_XTAL_SEL_3_0))
+#define BIT_GET_LS_XTAL_SEL_3_0(x)                                             \
+	(((x) >> BIT_SHIFT_LS_XTAL_SEL_3_0) & BIT_MASK_LS_XTAL_SEL_3_0)
+#define BIT_SET_LS_XTAL_SEL_3_0(x, v)                                          \
+	(BIT_CLEAR_LS_XTAL_SEL_3_0(x) | BIT_LS_XTAL_SEL_3_0(v))
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_SYS_CFG4				(Offset 0x1034) */
+
+#define BIT_EF_CSER_1 BIT(26)
+#define BIT_SW_PG_EN_1 BIT(10)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_ANAPAR_XTAL_0			(Offset 0x1040) */
+
+#define BIT_XTAL_SC_LPS BIT(31)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_ANAPAR_XTAL_0			(Offset 0x1040) */
+
+#define BIT_XTAL_DRV_RF1_0 BIT(31)
+#define BIT_XTAL_GATED_RF1N BIT(30)
+#define BIT_XTAL_GATED_RF1P BIT(29)
+#define BIT_XTAL_GM_SEP_V2 BIT(28)
+
+#define BIT_SHIFT_XTAL_LDO_1_0 26
+#define BIT_MASK_XTAL_LDO_1_0 0x3
+#define BIT_XTAL_LDO_1_0(x)                                                    \
+	(((x) & BIT_MASK_XTAL_LDO_1_0) << BIT_SHIFT_XTAL_LDO_1_0)
+#define BITS_XTAL_LDO_1_0 (BIT_MASK_XTAL_LDO_1_0 << BIT_SHIFT_XTAL_LDO_1_0)
+#define BIT_CLEAR_XTAL_LDO_1_0(x) ((x) & (~BITS_XTAL_LDO_1_0))
+#define BIT_GET_XTAL_LDO_1_0(x)                                                \
+	(((x) >> BIT_SHIFT_XTAL_LDO_1_0) & BIT_MASK_XTAL_LDO_1_0)
+#define BIT_SET_XTAL_LDO_1_0(x, v)                                             \
+	(BIT_CLEAR_XTAL_LDO_1_0(x) | BIT_XTAL_LDO_1_0(v))
+
+#define BIT_XQSEL_V1 BIT(25)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_ANAPAR_XTAL_0			(Offset 0x1040) */
+
+#define BIT_SHIFT_XTAL_SC_INIT 24
+#define BIT_MASK_XTAL_SC_INIT 0x7f
+#define BIT_XTAL_SC_INIT(x)                                                    \
+	(((x) & BIT_MASK_XTAL_SC_INIT) << BIT_SHIFT_XTAL_SC_INIT)
+#define BITS_XTAL_SC_INIT (BIT_MASK_XTAL_SC_INIT << BIT_SHIFT_XTAL_SC_INIT)
+#define BIT_CLEAR_XTAL_SC_INIT(x) ((x) & (~BITS_XTAL_SC_INIT))
+#define BIT_GET_XTAL_SC_INIT(x)                                                \
+	(((x) >> BIT_SHIFT_XTAL_SC_INIT) & BIT_MASK_XTAL_SC_INIT)
+#define BIT_SET_XTAL_SC_INIT(x, v)                                             \
+	(BIT_CLEAR_XTAL_SC_INIT(x) | BIT_XTAL_SC_INIT(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_ANAPAR_XTAL_0			(Offset 0x1040) */
+
+#define BIT_GATED_XTAL_OK0 BIT(24)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_ANAPAR_XTAL_0			(Offset 0x1040) */
+
+#define BIT_SHIFT_XTAL_SC_XO 17
+#define BIT_MASK_XTAL_SC_XO 0x7f
+#define BIT_XTAL_SC_XO(x) (((x) & BIT_MASK_XTAL_SC_XO) << BIT_SHIFT_XTAL_SC_XO)
+#define BITS_XTAL_SC_XO (BIT_MASK_XTAL_SC_XO << BIT_SHIFT_XTAL_SC_XO)
+#define BIT_CLEAR_XTAL_SC_XO(x) ((x) & (~BITS_XTAL_SC_XO))
+#define BIT_GET_XTAL_SC_XO(x)                                                  \
+	(((x) >> BIT_SHIFT_XTAL_SC_XO) & BIT_MASK_XTAL_SC_XO)
+#define BIT_SET_XTAL_SC_XO(x, v) (BIT_CLEAR_XTAL_SC_XO(x) | BIT_XTAL_SC_XO(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_ANAPAR_XTAL_0			(Offset 0x1040) */
+
+#define BIT_SHIFT_XTAL_SC_XO_6_0 17
+#define BIT_MASK_XTAL_SC_XO_6_0 0x7f
+#define BIT_XTAL_SC_XO_6_0(x)                                                  \
+	(((x) & BIT_MASK_XTAL_SC_XO_6_0) << BIT_SHIFT_XTAL_SC_XO_6_0)
+#define BITS_XTAL_SC_XO_6_0                                                    \
+	(BIT_MASK_XTAL_SC_XO_6_0 << BIT_SHIFT_XTAL_SC_XO_6_0)
+#define BIT_CLEAR_XTAL_SC_XO_6_0(x) ((x) & (~BITS_XTAL_SC_XO_6_0))
+#define BIT_GET_XTAL_SC_XO_6_0(x)                                              \
+	(((x) >> BIT_SHIFT_XTAL_SC_XO_6_0) & BIT_MASK_XTAL_SC_XO_6_0)
+#define BIT_SET_XTAL_SC_XO_6_0(x, v)                                           \
+	(BIT_CLEAR_XTAL_SC_XO_6_0(x) | BIT_XTAL_SC_XO_6_0(v))
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_ANAPAR_XTAL_0			(Offset 0x1040) */
+
+#define BIT_SHIFT_XTAL_SC_XI 10
+#define BIT_MASK_XTAL_SC_XI 0x7f
+#define BIT_XTAL_SC_XI(x) (((x) & BIT_MASK_XTAL_SC_XI) << BIT_SHIFT_XTAL_SC_XI)
+#define BITS_XTAL_SC_XI (BIT_MASK_XTAL_SC_XI << BIT_SHIFT_XTAL_SC_XI)
+#define BIT_CLEAR_XTAL_SC_XI(x) ((x) & (~BITS_XTAL_SC_XI))
+#define BIT_GET_XTAL_SC_XI(x)                                                  \
+	(((x) >> BIT_SHIFT_XTAL_SC_XI) & BIT_MASK_XTAL_SC_XI)
+#define BIT_SET_XTAL_SC_XI(x, v) (BIT_CLEAR_XTAL_SC_XI(x) | BIT_XTAL_SC_XI(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_ANAPAR_XTAL_0			(Offset 0x1040) */
+
+#define BIT_SHIFT_XTAL_SC_XI_6_0 10
+#define BIT_MASK_XTAL_SC_XI_6_0 0x7f
+#define BIT_XTAL_SC_XI_6_0(x)                                                  \
+	(((x) & BIT_MASK_XTAL_SC_XI_6_0) << BIT_SHIFT_XTAL_SC_XI_6_0)
+#define BITS_XTAL_SC_XI_6_0                                                    \
+	(BIT_MASK_XTAL_SC_XI_6_0 << BIT_SHIFT_XTAL_SC_XI_6_0)
+#define BIT_CLEAR_XTAL_SC_XI_6_0(x) ((x) & (~BITS_XTAL_SC_XI_6_0))
+#define BIT_GET_XTAL_SC_XI_6_0(x)                                              \
+	(((x) >> BIT_SHIFT_XTAL_SC_XI_6_0) & BIT_MASK_XTAL_SC_XI_6_0)
+#define BIT_SET_XTAL_SC_XI_6_0(x, v)                                           \
+	(BIT_CLEAR_XTAL_SC_XI_6_0(x) | BIT_XTAL_SC_XI_6_0(v))
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_ANAPAR_XTAL_0			(Offset 0x1040) */
+
+#define BIT_SHIFT_XTAL_GMN_V3 5
+#define BIT_MASK_XTAL_GMN_V3 0x1f
+#define BIT_XTAL_GMN_V3(x)                                                     \
+	(((x) & BIT_MASK_XTAL_GMN_V3) << BIT_SHIFT_XTAL_GMN_V3)
+#define BITS_XTAL_GMN_V3 (BIT_MASK_XTAL_GMN_V3 << BIT_SHIFT_XTAL_GMN_V3)
+#define BIT_CLEAR_XTAL_GMN_V3(x) ((x) & (~BITS_XTAL_GMN_V3))
+#define BIT_GET_XTAL_GMN_V3(x)                                                 \
+	(((x) >> BIT_SHIFT_XTAL_GMN_V3) & BIT_MASK_XTAL_GMN_V3)
+#define BIT_SET_XTAL_GMN_V3(x, v)                                              \
+	(BIT_CLEAR_XTAL_GMN_V3(x) | BIT_XTAL_GMN_V3(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_ANAPAR_XTAL_0			(Offset 0x1040) */
+
+#define BIT_SHIFT_XTAL_GMN_4_0 5
+#define BIT_MASK_XTAL_GMN_4_0 0x1f
+#define BIT_XTAL_GMN_4_0(x)                                                    \
+	(((x) & BIT_MASK_XTAL_GMN_4_0) << BIT_SHIFT_XTAL_GMN_4_0)
+#define BITS_XTAL_GMN_4_0 (BIT_MASK_XTAL_GMN_4_0 << BIT_SHIFT_XTAL_GMN_4_0)
+#define BIT_CLEAR_XTAL_GMN_4_0(x) ((x) & (~BITS_XTAL_GMN_4_0))
+#define BIT_GET_XTAL_GMN_4_0(x)                                                \
+	(((x) >> BIT_SHIFT_XTAL_GMN_4_0) & BIT_MASK_XTAL_GMN_4_0)
+#define BIT_SET_XTAL_GMN_4_0(x, v)                                             \
+	(BIT_CLEAR_XTAL_GMN_4_0(x) | BIT_XTAL_GMN_4_0(v))
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_ANAPAR_XTAL_0			(Offset 0x1040) */
+
+#define BIT_SHIFT_XTAL_GMP_V3 0
+#define BIT_MASK_XTAL_GMP_V3 0x1f
+#define BIT_XTAL_GMP_V3(x)                                                     \
+	(((x) & BIT_MASK_XTAL_GMP_V3) << BIT_SHIFT_XTAL_GMP_V3)
+#define BITS_XTAL_GMP_V3 (BIT_MASK_XTAL_GMP_V3 << BIT_SHIFT_XTAL_GMP_V3)
+#define BIT_CLEAR_XTAL_GMP_V3(x) ((x) & (~BITS_XTAL_GMP_V3))
+#define BIT_GET_XTAL_GMP_V3(x)                                                 \
+	(((x) >> BIT_SHIFT_XTAL_GMP_V3) & BIT_MASK_XTAL_GMP_V3)
+#define BIT_SET_XTAL_GMP_V3(x, v)                                              \
+	(BIT_CLEAR_XTAL_GMP_V3(x) | BIT_XTAL_GMP_V3(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_ANAPAR_XTAL_0			(Offset 0x1040) */
+
+#define BIT_SHIFT_XTAL_GMP_4_0 0
+#define BIT_MASK_XTAL_GMP_4_0 0x1f
+#define BIT_XTAL_GMP_4_0(x)                                                    \
+	(((x) & BIT_MASK_XTAL_GMP_4_0) << BIT_SHIFT_XTAL_GMP_4_0)
+#define BITS_XTAL_GMP_4_0 (BIT_MASK_XTAL_GMP_4_0 << BIT_SHIFT_XTAL_GMP_4_0)
+#define BIT_CLEAR_XTAL_GMP_4_0(x) ((x) & (~BITS_XTAL_GMP_4_0))
+#define BIT_GET_XTAL_GMP_4_0(x)                                                \
+	(((x) >> BIT_SHIFT_XTAL_GMP_4_0) & BIT_MASK_XTAL_GMP_4_0)
+#define BIT_SET_XTAL_GMP_4_0(x, v)                                             \
+	(BIT_CLEAR_XTAL_GMP_4_0(x) | BIT_XTAL_GMP_4_0(v))
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_ANAPAR_XTAL_1			(Offset 0x1044) */
+
+#define BIT_XTAL_SEL_TOK_V1 BIT(31)
+#define BIT_XTAL_DELAY_DIGI_V2 BIT(30)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_ANAPAR_XTAL_1			(Offset 0x1044) */
+
+#define BIT_SHIFT_XTAL_LDO_OK_1_0 30
+#define BIT_MASK_XTAL_LDO_OK_1_0 0x3
+#define BIT_XTAL_LDO_OK_1_0(x)                                                 \
+	(((x) & BIT_MASK_XTAL_LDO_OK_1_0) << BIT_SHIFT_XTAL_LDO_OK_1_0)
+#define BITS_XTAL_LDO_OK_1_0                                                   \
+	(BIT_MASK_XTAL_LDO_OK_1_0 << BIT_SHIFT_XTAL_LDO_OK_1_0)
+#define BIT_CLEAR_XTAL_LDO_OK_1_0(x) ((x) & (~BITS_XTAL_LDO_OK_1_0))
+#define BIT_GET_XTAL_LDO_OK_1_0(x)                                             \
+	(((x) >> BIT_SHIFT_XTAL_LDO_OK_1_0) & BIT_MASK_XTAL_LDO_OK_1_0)
+#define BIT_SET_XTAL_LDO_OK_1_0(x, v)                                          \
+	(BIT_CLEAR_XTAL_LDO_OK_1_0(x) | BIT_XTAL_LDO_OK_1_0(v))
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_ANAPAR_XTAL_1			(Offset 0x1044) */
+
+#define BIT_XTAL_DELAY_USB_V2 BIT(29)
+#define BIT_XTAL_DELAY_AFE_V2 BIT(28)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_ANAPAR_XTAL_1			(Offset 0x1044) */
+
+#define BIT_SHIFT_XTAL_XORES_SEL_2_0 27
+#define BIT_MASK_XTAL_XORES_SEL_2_0 0x7
+#define BIT_XTAL_XORES_SEL_2_0(x)                                              \
+	(((x) & BIT_MASK_XTAL_XORES_SEL_2_0) << BIT_SHIFT_XTAL_XORES_SEL_2_0)
+#define BITS_XTAL_XORES_SEL_2_0                                                \
+	(BIT_MASK_XTAL_XORES_SEL_2_0 << BIT_SHIFT_XTAL_XORES_SEL_2_0)
+#define BIT_CLEAR_XTAL_XORES_SEL_2_0(x) ((x) & (~BITS_XTAL_XORES_SEL_2_0))
+#define BIT_GET_XTAL_XORES_SEL_2_0(x)                                          \
+	(((x) >> BIT_SHIFT_XTAL_XORES_SEL_2_0) & BIT_MASK_XTAL_XORES_SEL_2_0)
+#define BIT_SET_XTAL_XORES_SEL_2_0(x, v)                                       \
+	(BIT_CLEAR_XTAL_XORES_SEL_2_0(x) | BIT_XTAL_XORES_SEL_2_0(v))
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_ANAPAR_XTAL_1			(Offset 0x1044) */
+
+#define BIT_SHIFT_XTAL_DRV_DIGI_V2 26
+#define BIT_MASK_XTAL_DRV_DIGI_V2 0x3
+#define BIT_XTAL_DRV_DIGI_V2(x)                                                \
+	(((x) & BIT_MASK_XTAL_DRV_DIGI_V2) << BIT_SHIFT_XTAL_DRV_DIGI_V2)
+#define BITS_XTAL_DRV_DIGI_V2                                                  \
+	(BIT_MASK_XTAL_DRV_DIGI_V2 << BIT_SHIFT_XTAL_DRV_DIGI_V2)
+#define BIT_CLEAR_XTAL_DRV_DIGI_V2(x) ((x) & (~BITS_XTAL_DRV_DIGI_V2))
+#define BIT_GET_XTAL_DRV_DIGI_V2(x)                                            \
+	(((x) >> BIT_SHIFT_XTAL_DRV_DIGI_V2) & BIT_MASK_XTAL_DRV_DIGI_V2)
+#define BIT_SET_XTAL_DRV_DIGI_V2(x, v)                                         \
+	(BIT_CLEAR_XTAL_DRV_DIGI_V2(x) | BIT_XTAL_DRV_DIGI_V2(v))
+
+#define BIT_EN_XTAL_DRV_LPS BIT(25)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_ANAPAR_XTAL_1			(Offset 0x1044) */
+
+#define BIT_SHIFT_XTAL_AAC_PK_SEL_1_0 25
+#define BIT_MASK_XTAL_AAC_PK_SEL_1_0 0x3
+#define BIT_XTAL_AAC_PK_SEL_1_0(x)                                             \
+	(((x) & BIT_MASK_XTAL_AAC_PK_SEL_1_0) << BIT_SHIFT_XTAL_AAC_PK_SEL_1_0)
+#define BITS_XTAL_AAC_PK_SEL_1_0                                               \
+	(BIT_MASK_XTAL_AAC_PK_SEL_1_0 << BIT_SHIFT_XTAL_AAC_PK_SEL_1_0)
+#define BIT_CLEAR_XTAL_AAC_PK_SEL_1_0(x) ((x) & (~BITS_XTAL_AAC_PK_SEL_1_0))
+#define BIT_GET_XTAL_AAC_PK_SEL_1_0(x)                                         \
+	(((x) >> BIT_SHIFT_XTAL_AAC_PK_SEL_1_0) & BIT_MASK_XTAL_AAC_PK_SEL_1_0)
+#define BIT_SET_XTAL_AAC_PK_SEL_1_0(x, v)                                      \
+	(BIT_CLEAR_XTAL_AAC_PK_SEL_1_0(x) | BIT_XTAL_AAC_PK_SEL_1_0(v))
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_ANAPAR_XTAL_1			(Offset 0x1044) */
+
+#define BIT_EN_XTAL_DRV_DIGI_V2 BIT(24)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_ANAPAR_XTAL_1			(Offset 0x1044) */
+
+#define BIT_EN_XTAL_AAC_PKDET BIT(24)
+#define BIT_EN_XTAL_AAC_GM BIT(23)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_ANAPAR_XTAL_1			(Offset 0x1044) */
+
+#define BIT_SHIFT_XTAL_DRV_USB 22
+#define BIT_MASK_XTAL_DRV_USB 0x3
+#define BIT_XTAL_DRV_USB(x)                                                    \
+	(((x) & BIT_MASK_XTAL_DRV_USB) << BIT_SHIFT_XTAL_DRV_USB)
+#define BITS_XTAL_DRV_USB (BIT_MASK_XTAL_DRV_USB << BIT_SHIFT_XTAL_DRV_USB)
+#define BIT_CLEAR_XTAL_DRV_USB(x) ((x) & (~BITS_XTAL_DRV_USB))
+#define BIT_GET_XTAL_DRV_USB(x)                                                \
+	(((x) >> BIT_SHIFT_XTAL_DRV_USB) & BIT_MASK_XTAL_DRV_USB)
+#define BIT_SET_XTAL_DRV_USB(x, v)                                             \
+	(BIT_CLEAR_XTAL_DRV_USB(x) | BIT_XTAL_DRV_USB(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_ANAPAR_XTAL_1			(Offset 0x1044) */
+
+#define BIT_XTAL_LPMODE BIT(22)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_ANAPAR_XTAL_1			(Offset 0x1044) */
+
+#define BIT_EN_XTAL_DRV_USB BIT(21)
+
+#define BIT_SHIFT_XTAL_DRV_AFE_V2 19
+#define BIT_MASK_XTAL_DRV_AFE_V2 0x3
+#define BIT_XTAL_DRV_AFE_V2(x)                                                 \
+	(((x) & BIT_MASK_XTAL_DRV_AFE_V2) << BIT_SHIFT_XTAL_DRV_AFE_V2)
+#define BITS_XTAL_DRV_AFE_V2                                                   \
+	(BIT_MASK_XTAL_DRV_AFE_V2 << BIT_SHIFT_XTAL_DRV_AFE_V2)
+#define BIT_CLEAR_XTAL_DRV_AFE_V2(x) ((x) & (~BITS_XTAL_DRV_AFE_V2))
+#define BIT_GET_XTAL_DRV_AFE_V2(x)                                             \
+	(((x) >> BIT_SHIFT_XTAL_DRV_AFE_V2) & BIT_MASK_XTAL_DRV_AFE_V2)
+#define BIT_SET_XTAL_DRV_AFE_V2(x, v)                                          \
+	(BIT_CLEAR_XTAL_DRV_AFE_V2(x) | BIT_XTAL_DRV_AFE_V2(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_ANAPAR_XTAL_1			(Offset 0x1044) */
+
+#define BIT_SHIFT_XTAL_SEL_TOK_2_0 19
+#define BIT_MASK_XTAL_SEL_TOK_2_0 0x7
+#define BIT_XTAL_SEL_TOK_2_0(x)                                                \
+	(((x) & BIT_MASK_XTAL_SEL_TOK_2_0) << BIT_SHIFT_XTAL_SEL_TOK_2_0)
+#define BITS_XTAL_SEL_TOK_2_0                                                  \
+	(BIT_MASK_XTAL_SEL_TOK_2_0 << BIT_SHIFT_XTAL_SEL_TOK_2_0)
+#define BIT_CLEAR_XTAL_SEL_TOK_2_0(x) ((x) & (~BITS_XTAL_SEL_TOK_2_0))
+#define BIT_GET_XTAL_SEL_TOK_2_0(x)                                            \
+	(((x) >> BIT_SHIFT_XTAL_SEL_TOK_2_0) & BIT_MASK_XTAL_SEL_TOK_2_0)
+#define BIT_SET_XTAL_SEL_TOK_2_0(x, v)                                         \
+	(BIT_CLEAR_XTAL_SEL_TOK_2_0(x) | BIT_XTAL_SEL_TOK_2_0(v))
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_ANAPAR_XTAL_1			(Offset 0x1044) */
+
+#define BIT_EN_XTAL_DRV_AFE BIT(18)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_ANAPAR_XTAL_1			(Offset 0x1044) */
+
+#define BIT_XQSEL_RF_AWAKE_V2 BIT(18)
+#define BIT_XQSEL_RF_INITIAL_V2 BIT(17)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_ANAPAR_XTAL_1			(Offset 0x1044) */
+
+#define BIT_SHIFT_XTAL_DRV_RF2_V2 16
+#define BIT_MASK_XTAL_DRV_RF2_V2 0x3
+#define BIT_XTAL_DRV_RF2_V2(x)                                                 \
+	(((x) & BIT_MASK_XTAL_DRV_RF2_V2) << BIT_SHIFT_XTAL_DRV_RF2_V2)
+#define BITS_XTAL_DRV_RF2_V2                                                   \
+	(BIT_MASK_XTAL_DRV_RF2_V2 << BIT_SHIFT_XTAL_DRV_RF2_V2)
+#define BIT_CLEAR_XTAL_DRV_RF2_V2(x) ((x) & (~BITS_XTAL_DRV_RF2_V2))
+#define BIT_GET_XTAL_DRV_RF2_V2(x)                                             \
+	(((x) >> BIT_SHIFT_XTAL_DRV_RF2_V2) & BIT_MASK_XTAL_DRV_RF2_V2)
+#define BIT_SET_XTAL_DRV_RF2_V2(x, v)                                          \
+	(BIT_CLEAR_XTAL_DRV_RF2_V2(x) | BIT_XTAL_DRV_RF2_V2(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_ANAPAR_XTAL_1			(Offset 0x1044) */
+
+#define BIT_XTAL_DELAY_USB_V1 BIT(16)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_ANAPAR_XTAL_1			(Offset 0x1044) */
+
+#define BIT_EN_XTAL_DRV_RF2 BIT(15)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_ANAPAR_XTAL_1			(Offset 0x1044) */
+
+#define BIT_XTAL_DELAY_DIGI_V1 BIT(15)
+#define BIT_XTAL_DELAY_AFE_V1 BIT(14)
+#define BIT_XTAL_DRV_RF_LATCH_V3 BIT(13)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_ANAPAR_XTAL_1			(Offset 0x1044) */
+
+#define BIT_EN_XTAL_DRV_RF1 BIT(12)
+#define BIT_XTAL_DRV_RF_LATCH_V4 BIT(11)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_ANAPAR_XTAL_1			(Offset 0x1044) */
+
+#define BIT_SHIFT_XTAL_DRV_DIGI_1_0 11
+#define BIT_MASK_XTAL_DRV_DIGI_1_0 0x3
+#define BIT_XTAL_DRV_DIGI_1_0(x)                                               \
+	(((x) & BIT_MASK_XTAL_DRV_DIGI_1_0) << BIT_SHIFT_XTAL_DRV_DIGI_1_0)
+#define BITS_XTAL_DRV_DIGI_1_0                                                 \
+	(BIT_MASK_XTAL_DRV_DIGI_1_0 << BIT_SHIFT_XTAL_DRV_DIGI_1_0)
+#define BIT_CLEAR_XTAL_DRV_DIGI_1_0(x) ((x) & (~BITS_XTAL_DRV_DIGI_1_0))
+#define BIT_GET_XTAL_DRV_DIGI_1_0(x)                                           \
+	(((x) >> BIT_SHIFT_XTAL_DRV_DIGI_1_0) & BIT_MASK_XTAL_DRV_DIGI_1_0)
+#define BIT_SET_XTAL_DRV_DIGI_1_0(x, v)                                        \
+	(BIT_CLEAR_XTAL_DRV_DIGI_1_0(x) | BIT_XTAL_DRV_DIGI_1_0(v))
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_ANAPAR_XTAL_1			(Offset 0x1044) */
+
+#define BIT_XTAL_GM_SEP_V3 BIT(10)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_ANAPAR_XTAL_1			(Offset 0x1044) */
+
+#define BIT_XTAL_GATED_DIGIN BIT(10)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_ANAPAR_XTAL_1			(Offset 0x1044) */
+
+#define BIT_XQSEL_RF_AWAKE_V3 BIT(9)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_ANAPAR_XTAL_1			(Offset 0x1044) */
+
+#define BIT_XTAL_GATED_DIGIP BIT(9)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_ANAPAR_XTAL_1			(Offset 0x1044) */
+
+#define BIT_XQSEL_RF_INITIAL_V3 BIT(8)
+#define BIT_XQSEL_V2 BIT(7)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_ANAPAR_XTAL_1			(Offset 0x1044) */
+
+#define BIT_SHIFT_XTAL_DRV_USB_1_0 7
+#define BIT_MASK_XTAL_DRV_USB_1_0 0x3
+#define BIT_XTAL_DRV_USB_1_0(x)                                                \
+	(((x) & BIT_MASK_XTAL_DRV_USB_1_0) << BIT_SHIFT_XTAL_DRV_USB_1_0)
+#define BITS_XTAL_DRV_USB_1_0                                                  \
+	(BIT_MASK_XTAL_DRV_USB_1_0 << BIT_SHIFT_XTAL_DRV_USB_1_0)
+#define BIT_CLEAR_XTAL_DRV_USB_1_0(x) ((x) & (~BITS_XTAL_DRV_USB_1_0))
+#define BIT_GET_XTAL_DRV_USB_1_0(x)                                            \
+	(((x) >> BIT_SHIFT_XTAL_DRV_USB_1_0) & BIT_MASK_XTAL_DRV_USB_1_0)
+#define BIT_SET_XTAL_DRV_USB_1_0(x, v)                                         \
+	(BIT_CLEAR_XTAL_DRV_USB_1_0(x) | BIT_XTAL_DRV_USB_1_0(v))
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_ANAPAR_XTAL_1			(Offset 0x1044) */
+
+#define BIT_GATED_XTAL_OK0_V2 BIT(6)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_ANAPAR_XTAL_1			(Offset 0x1044) */
+
+#define BIT_XTAL_GATED_USBN BIT(6)
+#define BIT_XTAL_GATED_USBP BIT(5)
+
+#define BIT_SHIFT_XTAL_DRV_AFE_1_0 3
+#define BIT_MASK_XTAL_DRV_AFE_1_0 0x3
+#define BIT_XTAL_DRV_AFE_1_0(x)                                                \
+	(((x) & BIT_MASK_XTAL_DRV_AFE_1_0) << BIT_SHIFT_XTAL_DRV_AFE_1_0)
+#define BITS_XTAL_DRV_AFE_1_0                                                  \
+	(BIT_MASK_XTAL_DRV_AFE_1_0 << BIT_SHIFT_XTAL_DRV_AFE_1_0)
+#define BIT_CLEAR_XTAL_DRV_AFE_1_0(x) ((x) & (~BITS_XTAL_DRV_AFE_1_0))
+#define BIT_GET_XTAL_DRV_AFE_1_0(x)                                            \
+	(((x) >> BIT_SHIFT_XTAL_DRV_AFE_1_0) & BIT_MASK_XTAL_DRV_AFE_1_0)
+#define BIT_SET_XTAL_DRV_AFE_1_0(x, v)                                         \
+	(BIT_CLEAR_XTAL_DRV_AFE_1_0(x) | BIT_XTAL_DRV_AFE_1_0(v))
+
+#define BIT_XTAL_GATED_AFEN BIT(2)
+#define BIT_XTAL_GATED_AFEP BIT(1)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_ANAPAR_XTAL_1			(Offset 0x1044) */
+
+#define BIT_SHIFT_XTAL_SC_LPS_V2 0
+#define BIT_MASK_XTAL_SC_LPS_V2 0x3f
+#define BIT_XTAL_SC_LPS_V2(x)                                                  \
+	(((x) & BIT_MASK_XTAL_SC_LPS_V2) << BIT_SHIFT_XTAL_SC_LPS_V2)
+#define BITS_XTAL_SC_LPS_V2                                                    \
+	(BIT_MASK_XTAL_SC_LPS_V2 << BIT_SHIFT_XTAL_SC_LPS_V2)
+#define BIT_CLEAR_XTAL_SC_LPS_V2(x) ((x) & (~BITS_XTAL_SC_LPS_V2))
+#define BIT_GET_XTAL_SC_LPS_V2(x)                                              \
+	(((x) >> BIT_SHIFT_XTAL_SC_LPS_V2) & BIT_MASK_XTAL_SC_LPS_V2)
+#define BIT_SET_XTAL_SC_LPS_V2(x, v)                                           \
+	(BIT_CLEAR_XTAL_SC_LPS_V2(x) | BIT_XTAL_SC_LPS_V2(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_ANAPAR_XTAL_1			(Offset 0x1044) */
+
+#define BIT_XTAL_DRV_RF1_1 BIT(0)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_ANAPAR_XTAL_2			(Offset 0x1048) */
+
+#define BIT_XTAL_AAC_CAP BIT(31)
+
+#define BIT_SHIFT_XTAL_PDSW 29
+#define BIT_MASK_XTAL_PDSW 0x3
+#define BIT_XTAL_PDSW(x) (((x) & BIT_MASK_XTAL_PDSW) << BIT_SHIFT_XTAL_PDSW)
+#define BITS_XTAL_PDSW (BIT_MASK_XTAL_PDSW << BIT_SHIFT_XTAL_PDSW)
+#define BIT_CLEAR_XTAL_PDSW(x) ((x) & (~BITS_XTAL_PDSW))
+#define BIT_GET_XTAL_PDSW(x) (((x) >> BIT_SHIFT_XTAL_PDSW) & BIT_MASK_XTAL_PDSW)
+#define BIT_SET_XTAL_PDSW(x, v) (BIT_CLEAR_XTAL_PDSW(x) | BIT_XTAL_PDSW(v))
+
+#define BIT_SHIFT_XTAL_LPS_BUF_VB 27
+#define BIT_MASK_XTAL_LPS_BUF_VB 0x3
+#define BIT_XTAL_LPS_BUF_VB(x)                                                 \
+	(((x) & BIT_MASK_XTAL_LPS_BUF_VB) << BIT_SHIFT_XTAL_LPS_BUF_VB)
+#define BITS_XTAL_LPS_BUF_VB                                                   \
+	(BIT_MASK_XTAL_LPS_BUF_VB << BIT_SHIFT_XTAL_LPS_BUF_VB)
+#define BIT_CLEAR_XTAL_LPS_BUF_VB(x) ((x) & (~BITS_XTAL_LPS_BUF_VB))
+#define BIT_GET_XTAL_LPS_BUF_VB(x)                                             \
+	(((x) >> BIT_SHIFT_XTAL_LPS_BUF_VB) & BIT_MASK_XTAL_LPS_BUF_VB)
+#define BIT_SET_XTAL_LPS_BUF_VB(x, v)                                          \
+	(BIT_CLEAR_XTAL_LPS_BUF_VB(x) | BIT_XTAL_LPS_BUF_VB(v))
+
+#define BIT_XTAL_PDCK_MANU BIT(26)
+#define BIT_XTAL_PDCK_OK_MANU BIT(25)
+
+#define BIT_SHIFT_XTAL_VREF_SEL 20
+#define BIT_MASK_XTAL_VREF_SEL 0x1f
+#define BIT_XTAL_VREF_SEL(x)                                                   \
+	(((x) & BIT_MASK_XTAL_VREF_SEL) << BIT_SHIFT_XTAL_VREF_SEL)
+#define BITS_XTAL_VREF_SEL (BIT_MASK_XTAL_VREF_SEL << BIT_SHIFT_XTAL_VREF_SEL)
+#define BIT_CLEAR_XTAL_VREF_SEL(x) ((x) & (~BITS_XTAL_VREF_SEL))
+#define BIT_GET_XTAL_VREF_SEL(x)                                               \
+	(((x) >> BIT_SHIFT_XTAL_VREF_SEL) & BIT_MASK_XTAL_VREF_SEL)
+#define BIT_SET_XTAL_VREF_SEL(x, v)                                            \
+	(BIT_CLEAR_XTAL_VREF_SEL(x) | BIT_XTAL_VREF_SEL(v))
+
+#define BIT_EN_XTAL_PDCK_VREF BIT(19)
+#define BIT_XTAL_SEL_PWR_V1 BIT(18)
+#define BIT_XTAL_LPS_DIVISOR BIT(17)
+#define BIT_XTAL_CKDIGI_SEL BIT(16)
+#define BIT_EN_XTAL_LPS_CLK BIT(15)
+#define BIT_EN_XTAL_SCHMITT BIT(14)
+#define BIT_XTAL_PK_SEL_OFFSET BIT(13)
+
+#define BIT_SHIFT_XTAL_MANU_PK_SEL 11
+#define BIT_MASK_XTAL_MANU_PK_SEL 0x3
+#define BIT_XTAL_MANU_PK_SEL(x)                                                \
+	(((x) & BIT_MASK_XTAL_MANU_PK_SEL) << BIT_SHIFT_XTAL_MANU_PK_SEL)
+#define BITS_XTAL_MANU_PK_SEL                                                  \
+	(BIT_MASK_XTAL_MANU_PK_SEL << BIT_SHIFT_XTAL_MANU_PK_SEL)
+#define BIT_CLEAR_XTAL_MANU_PK_SEL(x) ((x) & (~BITS_XTAL_MANU_PK_SEL))
+#define BIT_GET_XTAL_MANU_PK_SEL(x)                                            \
+	(((x) >> BIT_SHIFT_XTAL_MANU_PK_SEL) & BIT_MASK_XTAL_MANU_PK_SEL)
+#define BIT_SET_XTAL_MANU_PK_SEL(x, v)                                         \
+	(BIT_CLEAR_XTAL_MANU_PK_SEL(x) | BIT_XTAL_MANU_PK_SEL(v))
+
+#define BIT_XTAL_AACK_PK_MANU BIT(10)
+#define BIT_EN_XTAL_AAC_PKDET_V1 BIT(9)
+#define BIT_EN_XTAL_AAC_GM_V1 BIT(8)
+#define BIT_XTAL_LDO_OPVB_SEL BIT(7)
+
+#define BIT_SHIFT_XTAL_DUMMY_V1 7
+#define BIT_MASK_XTAL_DUMMY_V1 0x3f
+#define BIT_XTAL_DUMMY_V1(x)                                                   \
+	(((x) & BIT_MASK_XTAL_DUMMY_V1) << BIT_SHIFT_XTAL_DUMMY_V1)
+#define BITS_XTAL_DUMMY_V1 (BIT_MASK_XTAL_DUMMY_V1 << BIT_SHIFT_XTAL_DUMMY_V1)
+#define BIT_CLEAR_XTAL_DUMMY_V1(x) ((x) & (~BITS_XTAL_DUMMY_V1))
+#define BIT_GET_XTAL_DUMMY_V1(x)                                               \
+	(((x) >> BIT_SHIFT_XTAL_DUMMY_V1) & BIT_MASK_XTAL_DUMMY_V1)
+#define BIT_SET_XTAL_DUMMY_V1(x, v)                                            \
+	(BIT_CLEAR_XTAL_DUMMY_V1(x) | BIT_XTAL_DUMMY_V1(v))
+
+#define BIT_XTAL_LDO_NC BIT(6)
+#define BIT_XTAL_EN_LNBUF BIT(6)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_ANAPAR_XTAL_2			(Offset 0x1048) */
+
+#define BIT_XTAL_DRV_RF2_LATCH BIT(6)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_ANAPAR_XTAL_2			(Offset 0x1048) */
+
+#define BIT_XTAL__AAC_TIE_MID BIT(5)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_ANAPAR_XTAL_2			(Offset 0x1048) */
+
+#define BIT_SHIFT_XTAL_DRV_RF2_1_0 4
+#define BIT_MASK_XTAL_DRV_RF2_1_0 0x3
+#define BIT_XTAL_DRV_RF2_1_0(x)                                                \
+	(((x) & BIT_MASK_XTAL_DRV_RF2_1_0) << BIT_SHIFT_XTAL_DRV_RF2_1_0)
+#define BITS_XTAL_DRV_RF2_1_0                                                  \
+	(BIT_MASK_XTAL_DRV_RF2_1_0 << BIT_SHIFT_XTAL_DRV_RF2_1_0)
+#define BIT_CLEAR_XTAL_DRV_RF2_1_0(x) ((x) & (~BITS_XTAL_DRV_RF2_1_0))
+#define BIT_GET_XTAL_DRV_RF2_1_0(x)                                            \
+	(((x) >> BIT_SHIFT_XTAL_DRV_RF2_1_0) & BIT_MASK_XTAL_DRV_RF2_1_0)
+#define BIT_SET_XTAL_DRV_RF2_1_0(x, v)                                         \
+	(BIT_CLEAR_XTAL_DRV_RF2_1_0(x) | BIT_XTAL_DRV_RF2_1_0(v))
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_ANAPAR_XTAL_2			(Offset 0x1048) */
+
+#define BIT_SHIFT_XTAL_LDO_VREF_V2 3
+#define BIT_MASK_XTAL_LDO_VREF_V2 0x7
+#define BIT_XTAL_LDO_VREF_V2(x)                                                \
+	(((x) & BIT_MASK_XTAL_LDO_VREF_V2) << BIT_SHIFT_XTAL_LDO_VREF_V2)
+#define BITS_XTAL_LDO_VREF_V2                                                  \
+	(BIT_MASK_XTAL_LDO_VREF_V2 << BIT_SHIFT_XTAL_LDO_VREF_V2)
+#define BIT_CLEAR_XTAL_LDO_VREF_V2(x) ((x) & (~BITS_XTAL_LDO_VREF_V2))
+#define BIT_GET_XTAL_LDO_VREF_V2(x)                                            \
+	(((x) >> BIT_SHIFT_XTAL_LDO_VREF_V2) & BIT_MASK_XTAL_LDO_VREF_V2)
+#define BIT_SET_XTAL_LDO_VREF_V2(x, v)                                         \
+	(BIT_CLEAR_XTAL_LDO_VREF_V2(x) | BIT_XTAL_LDO_VREF_V2(v))
+
+#define BIT_SHIFT_XTAL_AAC_OPCUR 3
+#define BIT_MASK_XTAL_AAC_OPCUR 0x3
+#define BIT_XTAL_AAC_OPCUR(x)                                                  \
+	(((x) & BIT_MASK_XTAL_AAC_OPCUR) << BIT_SHIFT_XTAL_AAC_OPCUR)
+#define BITS_XTAL_AAC_OPCUR                                                    \
+	(BIT_MASK_XTAL_AAC_OPCUR << BIT_SHIFT_XTAL_AAC_OPCUR)
+#define BIT_CLEAR_XTAL_AAC_OPCUR(x) ((x) & (~BITS_XTAL_AAC_OPCUR))
+#define BIT_GET_XTAL_AAC_OPCUR(x)                                              \
+	(((x) >> BIT_SHIFT_XTAL_AAC_OPCUR) & BIT_MASK_XTAL_AAC_OPCUR)
+#define BIT_SET_XTAL_AAC_OPCUR(x, v)                                           \
+	(BIT_CLEAR_XTAL_AAC_OPCUR(x) | BIT_XTAL_AAC_OPCUR(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_ANAPAR_XTAL_2			(Offset 0x1048) */
+
+#define BIT_XTAL_GATED_RF2N BIT(3)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_ANAPAR_XTAL_2			(Offset 0x1048) */
+
+#define BIT_XTAL_LPMODE_V1 BIT(2)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_ANAPAR_XTAL_2			(Offset 0x1048) */
+
+#define BIT_XTAL_GATED_RF2P BIT(2)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_ANAPAR_XTAL_2			(Offset 0x1048) */
+
+#define BIT_SHIFT_XTAL_AAC_IOFFSET 1
+#define BIT_MASK_XTAL_AAC_IOFFSET 0x3
+#define BIT_XTAL_AAC_IOFFSET(x)                                                \
+	(((x) & BIT_MASK_XTAL_AAC_IOFFSET) << BIT_SHIFT_XTAL_AAC_IOFFSET)
+#define BITS_XTAL_AAC_IOFFSET                                                  \
+	(BIT_MASK_XTAL_AAC_IOFFSET << BIT_SHIFT_XTAL_AAC_IOFFSET)
+#define BIT_CLEAR_XTAL_AAC_IOFFSET(x) ((x) & (~BITS_XTAL_AAC_IOFFSET))
+#define BIT_GET_XTAL_AAC_IOFFSET(x)                                            \
+	(((x) >> BIT_SHIFT_XTAL_AAC_IOFFSET) & BIT_MASK_XTAL_AAC_IOFFSET)
+#define BIT_SET_XTAL_AAC_IOFFSET(x, v)                                         \
+	(BIT_CLEAR_XTAL_AAC_IOFFSET(x) | BIT_XTAL_AAC_IOFFSET(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_ANAPAR_XTAL_2			(Offset 0x1048) */
+
+#define BIT_XTAL_LDO_DI BIT(1)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_ANAPAR_XTAL_2			(Offset 0x1048) */
+
+#define BIT_SHIFT_XTAL_SEL_TOK_V3 0
+#define BIT_MASK_XTAL_SEL_TOK_V3 0x3
+#define BIT_XTAL_SEL_TOK_V3(x)                                                 \
+	(((x) & BIT_MASK_XTAL_SEL_TOK_V3) << BIT_SHIFT_XTAL_SEL_TOK_V3)
+#define BITS_XTAL_SEL_TOK_V3                                                   \
+	(BIT_MASK_XTAL_SEL_TOK_V3 << BIT_SHIFT_XTAL_SEL_TOK_V3)
+#define BIT_CLEAR_XTAL_SEL_TOK_V3(x) ((x) & (~BITS_XTAL_SEL_TOK_V3))
+#define BIT_GET_XTAL_SEL_TOK_V3(x)                                             \
+	(((x) >> BIT_SHIFT_XTAL_SEL_TOK_V3) & BIT_MASK_XTAL_SEL_TOK_V3)
+#define BIT_SET_XTAL_SEL_TOK_V3(x, v)                                          \
+	(BIT_CLEAR_XTAL_SEL_TOK_V3(x) | BIT_XTAL_SEL_TOK_V3(v))
+
+#define BIT_XTAL_AAC_CAP_V1 BIT(0)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_ANAPAR_XTAL_2			(Offset 0x1048) */
+
+#define BIT_XTAL_SEL_PWR BIT(0)
+
+/* 2 REG_ANAPAR_XTAL_AAC			(Offset 0x104C) */
+
+#define BIT_SHIFT_GM_MANUAL_4_0 21
+#define BIT_MASK_GM_MANUAL_4_0 0x1f
+#define BIT_GM_MANUAL_4_0(x)                                                   \
+	(((x) & BIT_MASK_GM_MANUAL_4_0) << BIT_SHIFT_GM_MANUAL_4_0)
+#define BITS_GM_MANUAL_4_0 (BIT_MASK_GM_MANUAL_4_0 << BIT_SHIFT_GM_MANUAL_4_0)
+#define BIT_CLEAR_GM_MANUAL_4_0(x) ((x) & (~BITS_GM_MANUAL_4_0))
+#define BIT_GET_GM_MANUAL_4_0(x)                                               \
+	(((x) >> BIT_SHIFT_GM_MANUAL_4_0) & BIT_MASK_GM_MANUAL_4_0)
+#define BIT_SET_GM_MANUAL_4_0(x, v)                                            \
+	(BIT_CLEAR_GM_MANUAL_4_0(x) | BIT_GM_MANUAL_4_0(v))
+
+#define BIT_SHIFT_GM_STUP_4_0 16
+#define BIT_MASK_GM_STUP_4_0 0x1f
+#define BIT_GM_STUP_4_0(x)                                                     \
+	(((x) & BIT_MASK_GM_STUP_4_0) << BIT_SHIFT_GM_STUP_4_0)
+#define BITS_GM_STUP_4_0 (BIT_MASK_GM_STUP_4_0 << BIT_SHIFT_GM_STUP_4_0)
+#define BIT_CLEAR_GM_STUP_4_0(x) ((x) & (~BITS_GM_STUP_4_0))
+#define BIT_GET_GM_STUP_4_0(x)                                                 \
+	(((x) >> BIT_SHIFT_GM_STUP_4_0) & BIT_MASK_GM_STUP_4_0)
+#define BIT_SET_GM_STUP_4_0(x, v)                                              \
+	(BIT_CLEAR_GM_STUP_4_0(x) | BIT_GM_STUP_4_0(v))
+
+#define BIT_SHIFT_XTAL_CK_SET_2_0 13
+#define BIT_MASK_XTAL_CK_SET_2_0 0x7
+#define BIT_XTAL_CK_SET_2_0(x)                                                 \
+	(((x) & BIT_MASK_XTAL_CK_SET_2_0) << BIT_SHIFT_XTAL_CK_SET_2_0)
+#define BITS_XTAL_CK_SET_2_0                                                   \
+	(BIT_MASK_XTAL_CK_SET_2_0 << BIT_SHIFT_XTAL_CK_SET_2_0)
+#define BIT_CLEAR_XTAL_CK_SET_2_0(x) ((x) & (~BITS_XTAL_CK_SET_2_0))
+#define BIT_GET_XTAL_CK_SET_2_0(x)                                             \
+	(((x) >> BIT_SHIFT_XTAL_CK_SET_2_0) & BIT_MASK_XTAL_CK_SET_2_0)
+#define BIT_SET_XTAL_CK_SET_2_0(x, v)                                          \
+	(BIT_CLEAR_XTAL_CK_SET_2_0(x) | BIT_XTAL_CK_SET_2_0(v))
+
+#define BIT_SHIFT_GM_INIT_4_0 8
+#define BIT_MASK_GM_INIT_4_0 0x1f
+#define BIT_GM_INIT_4_0(x)                                                     \
+	(((x) & BIT_MASK_GM_INIT_4_0) << BIT_SHIFT_GM_INIT_4_0)
+#define BITS_GM_INIT_4_0 (BIT_MASK_GM_INIT_4_0 << BIT_SHIFT_GM_INIT_4_0)
+#define BIT_CLEAR_GM_INIT_4_0(x) ((x) & (~BITS_GM_INIT_4_0))
+#define BIT_GET_GM_INIT_4_0(x)                                                 \
+	(((x) >> BIT_SHIFT_GM_INIT_4_0) & BIT_MASK_GM_INIT_4_0)
+#define BIT_SET_GM_INIT_4_0(x, v)                                              \
+	(BIT_CLEAR_GM_INIT_4_0(x) | BIT_GM_INIT_4_0(v))
+
+#define BIT_SHIFT_XAAC_GM_OFFSET_4_0 2
+#define BIT_MASK_XAAC_GM_OFFSET_4_0 0x1f
+#define BIT_XAAC_GM_OFFSET_4_0(x)                                              \
+	(((x) & BIT_MASK_XAAC_GM_OFFSET_4_0) << BIT_SHIFT_XAAC_GM_OFFSET_4_0)
+#define BITS_XAAC_GM_OFFSET_4_0                                                \
+	(BIT_MASK_XAAC_GM_OFFSET_4_0 << BIT_SHIFT_XAAC_GM_OFFSET_4_0)
+#define BIT_CLEAR_XAAC_GM_OFFSET_4_0(x) ((x) & (~BITS_XAAC_GM_OFFSET_4_0))
+#define BIT_GET_XAAC_GM_OFFSET_4_0(x)                                          \
+	(((x) >> BIT_SHIFT_XAAC_GM_OFFSET_4_0) & BIT_MASK_XAAC_GM_OFFSET_4_0)
+#define BIT_SET_XAAC_GM_OFFSET_4_0(x, v)                                       \
+	(BIT_CLEAR_XAAC_GM_OFFSET_4_0(x) | BIT_XAAC_GM_OFFSET_4_0(v))
+
+/* 2 REG_ANAPAR_XTAL_R_ONLY			(Offset 0x1050) */
+
+#define BIT_XTAL_PKDET_OUT BIT(6)
+
+#define BIT_SHIFT_XTAL_GM_AAC_4_0 1
+#define BIT_MASK_XTAL_GM_AAC_4_0 0x1f
+#define BIT_XTAL_GM_AAC_4_0(x)                                                 \
+	(((x) & BIT_MASK_XTAL_GM_AAC_4_0) << BIT_SHIFT_XTAL_GM_AAC_4_0)
+#define BITS_XTAL_GM_AAC_4_0                                                   \
+	(BIT_MASK_XTAL_GM_AAC_4_0 << BIT_SHIFT_XTAL_GM_AAC_4_0)
+#define BIT_CLEAR_XTAL_GM_AAC_4_0(x) ((x) & (~BITS_XTAL_GM_AAC_4_0))
+#define BIT_GET_XTAL_GM_AAC_4_0(x)                                             \
+	(((x) >> BIT_SHIFT_XTAL_GM_AAC_4_0) & BIT_MASK_XTAL_GM_AAC_4_0)
+#define BIT_SET_XTAL_GM_AAC_4_0(x, v)                                          \
+	(BIT_CLEAR_XTAL_GM_AAC_4_0(x) | BIT_XTAL_GM_AAC_4_0(v))
+
+#define BIT_XAAC_READY BIT(0)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_ANAPAR_XTAL_AACK_0			(Offset 0x1054) */
+
+#define BIT_XAAC_LPOW BIT(31)
+
+#define BIT_SHIFT_AAC_MODE 29
+#define BIT_MASK_AAC_MODE 0x3
+#define BIT_AAC_MODE(x) (((x) & BIT_MASK_AAC_MODE) << BIT_SHIFT_AAC_MODE)
+#define BITS_AAC_MODE (BIT_MASK_AAC_MODE << BIT_SHIFT_AAC_MODE)
+#define BIT_CLEAR_AAC_MODE(x) ((x) & (~BITS_AAC_MODE))
+#define BIT_GET_AAC_MODE(x) (((x) >> BIT_SHIFT_AAC_MODE) & BIT_MASK_AAC_MODE)
+#define BIT_SET_AAC_MODE(x, v) (BIT_CLEAR_AAC_MODE(x) | BIT_AAC_MODE(v))
+
+#define BIT_SHIFT_GM_MANUAL 21
+#define BIT_MASK_GM_MANUAL 0x1f
+#define BIT_GM_MANUAL(x) (((x) & BIT_MASK_GM_MANUAL) << BIT_SHIFT_GM_MANUAL)
+#define BITS_GM_MANUAL (BIT_MASK_GM_MANUAL << BIT_SHIFT_GM_MANUAL)
+#define BIT_CLEAR_GM_MANUAL(x) ((x) & (~BITS_GM_MANUAL))
+#define BIT_GET_GM_MANUAL(x) (((x) >> BIT_SHIFT_GM_MANUAL) & BIT_MASK_GM_MANUAL)
+#define BIT_SET_GM_MANUAL(x, v) (BIT_CLEAR_GM_MANUAL(x) | BIT_GM_MANUAL(v))
+
+#define BIT_SHIFT_XTAL_LDO_LPS 21
+#define BIT_MASK_XTAL_LDO_LPS 0x7
+#define BIT_XTAL_LDO_LPS(x)                                                    \
+	(((x) & BIT_MASK_XTAL_LDO_LPS) << BIT_SHIFT_XTAL_LDO_LPS)
+#define BITS_XTAL_LDO_LPS (BIT_MASK_XTAL_LDO_LPS << BIT_SHIFT_XTAL_LDO_LPS)
+#define BIT_CLEAR_XTAL_LDO_LPS(x) ((x) & (~BITS_XTAL_LDO_LPS))
+#define BIT_GET_XTAL_LDO_LPS(x)                                                \
+	(((x) >> BIT_SHIFT_XTAL_LDO_LPS) & BIT_MASK_XTAL_LDO_LPS)
+#define BIT_SET_XTAL_LDO_LPS(x, v)                                             \
+	(BIT_CLEAR_XTAL_LDO_LPS(x) | BIT_XTAL_LDO_LPS(v))
+
+#define BIT_SHIFT_GM_STUP 16
+#define BIT_MASK_GM_STUP 0x1f
+#define BIT_GM_STUP(x) (((x) & BIT_MASK_GM_STUP) << BIT_SHIFT_GM_STUP)
+#define BITS_GM_STUP (BIT_MASK_GM_STUP << BIT_SHIFT_GM_STUP)
+#define BIT_CLEAR_GM_STUP(x) ((x) & (~BITS_GM_STUP))
+#define BIT_GET_GM_STUP(x) (((x) >> BIT_SHIFT_GM_STUP) & BIT_MASK_GM_STUP)
+#define BIT_SET_GM_STUP(x, v) (BIT_CLEAR_GM_STUP(x) | BIT_GM_STUP(v))
+
+#define BIT_SHIFT_XTAL_WAIT_CYC 15
+#define BIT_MASK_XTAL_WAIT_CYC 0x3f
+#define BIT_XTAL_WAIT_CYC(x)                                                   \
+	(((x) & BIT_MASK_XTAL_WAIT_CYC) << BIT_SHIFT_XTAL_WAIT_CYC)
+#define BITS_XTAL_WAIT_CYC (BIT_MASK_XTAL_WAIT_CYC << BIT_SHIFT_XTAL_WAIT_CYC)
+#define BIT_CLEAR_XTAL_WAIT_CYC(x) ((x) & (~BITS_XTAL_WAIT_CYC))
+#define BIT_GET_XTAL_WAIT_CYC(x)                                               \
+	(((x) >> BIT_SHIFT_XTAL_WAIT_CYC) & BIT_MASK_XTAL_WAIT_CYC)
+#define BIT_SET_XTAL_WAIT_CYC(x, v)                                            \
+	(BIT_CLEAR_XTAL_WAIT_CYC(x) | BIT_XTAL_WAIT_CYC(v))
+
+#define BIT_SHIFT_XTAL_CK_SET 13
+#define BIT_MASK_XTAL_CK_SET 0x7
+#define BIT_XTAL_CK_SET(x)                                                     \
+	(((x) & BIT_MASK_XTAL_CK_SET) << BIT_SHIFT_XTAL_CK_SET)
+#define BITS_XTAL_CK_SET (BIT_MASK_XTAL_CK_SET << BIT_SHIFT_XTAL_CK_SET)
+#define BIT_CLEAR_XTAL_CK_SET(x) ((x) & (~BITS_XTAL_CK_SET))
+#define BIT_GET_XTAL_CK_SET(x)                                                 \
+	(((x) >> BIT_SHIFT_XTAL_CK_SET) & BIT_MASK_XTAL_CK_SET)
+#define BIT_SET_XTAL_CK_SET(x, v)                                              \
+	(BIT_CLEAR_XTAL_CK_SET(x) | BIT_XTAL_CK_SET(v))
+
+#define BIT_SHIFT_XTAL_LDO_OK 12
+#define BIT_MASK_XTAL_LDO_OK 0x7
+#define BIT_XTAL_LDO_OK(x)                                                     \
+	(((x) & BIT_MASK_XTAL_LDO_OK) << BIT_SHIFT_XTAL_LDO_OK)
+#define BITS_XTAL_LDO_OK (BIT_MASK_XTAL_LDO_OK << BIT_SHIFT_XTAL_LDO_OK)
+#define BIT_CLEAR_XTAL_LDO_OK(x) ((x) & (~BITS_XTAL_LDO_OK))
+#define BIT_GET_XTAL_LDO_OK(x)                                                 \
+	(((x) >> BIT_SHIFT_XTAL_LDO_OK) & BIT_MASK_XTAL_LDO_OK)
+#define BIT_SET_XTAL_LDO_OK(x, v)                                              \
+	(BIT_CLEAR_XTAL_LDO_OK(x) | BIT_XTAL_LDO_OK(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_CPHY_LDO				(Offset 0x1054) */
+
+#define BIT_SHIFT_CPHY_LDO_PD 12
+#define BIT_MASK_CPHY_LDO_PD 0x3
+#define BIT_CPHY_LDO_PD(x)                                                     \
+	(((x) & BIT_MASK_CPHY_LDO_PD) << BIT_SHIFT_CPHY_LDO_PD)
+#define BITS_CPHY_LDO_PD (BIT_MASK_CPHY_LDO_PD << BIT_SHIFT_CPHY_LDO_PD)
+#define BIT_CLEAR_CPHY_LDO_PD(x) ((x) & (~BITS_CPHY_LDO_PD))
+#define BIT_GET_CPHY_LDO_PD(x)                                                 \
+	(((x) >> BIT_SHIFT_CPHY_LDO_PD) & BIT_MASK_CPHY_LDO_PD)
+#define BIT_SET_CPHY_LDO_PD(x, v)                                              \
+	(BIT_CLEAR_CPHY_LDO_PD(x) | BIT_CPHY_LDO_PD(v))
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_ANAPAR_XTAL_AACK_0			(Offset 0x1054) */
+
+#define BIT_XTAL_MD_LPOW BIT(11)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_CPHY_LDO				(Offset 0x1054) */
+
+#define BIT_SHIFT_CPHY_LDO_SR 10
+#define BIT_MASK_CPHY_LDO_SR 0x3
+#define BIT_CPHY_LDO_SR(x)                                                     \
+	(((x) & BIT_MASK_CPHY_LDO_SR) << BIT_SHIFT_CPHY_LDO_SR)
+#define BITS_CPHY_LDO_SR (BIT_MASK_CPHY_LDO_SR << BIT_SHIFT_CPHY_LDO_SR)
+#define BIT_CLEAR_CPHY_LDO_SR(x) ((x) & (~BITS_CPHY_LDO_SR))
+#define BIT_GET_CPHY_LDO_SR(x)                                                 \
+	(((x) >> BIT_SHIFT_CPHY_LDO_SR) & BIT_MASK_CPHY_LDO_SR)
+#define BIT_SET_CPHY_LDO_SR(x, v)                                              \
+	(BIT_CLEAR_CPHY_LDO_SR(x) | BIT_CPHY_LDO_SR(v))
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_ANAPAR_XTAL_AACK_0			(Offset 0x1054) */
+
+#define BIT_SHIFT_XTAL_OV_RATIO 9
+#define BIT_MASK_XTAL_OV_RATIO 0x3
+#define BIT_XTAL_OV_RATIO(x)                                                   \
+	(((x) & BIT_MASK_XTAL_OV_RATIO) << BIT_SHIFT_XTAL_OV_RATIO)
+#define BITS_XTAL_OV_RATIO (BIT_MASK_XTAL_OV_RATIO << BIT_SHIFT_XTAL_OV_RATIO)
+#define BIT_CLEAR_XTAL_OV_RATIO(x) ((x) & (~BITS_XTAL_OV_RATIO))
+#define BIT_GET_XTAL_OV_RATIO(x)                                               \
+	(((x) >> BIT_SHIFT_XTAL_OV_RATIO) & BIT_MASK_XTAL_OV_RATIO)
+#define BIT_SET_XTAL_OV_RATIO(x, v)                                            \
+	(BIT_CLEAR_XTAL_OV_RATIO(x) | BIT_XTAL_OV_RATIO(v))
+
+#define BIT_SHIFT_GM_INIT 8
+#define BIT_MASK_GM_INIT 0x1f
+#define BIT_GM_INIT(x) (((x) & BIT_MASK_GM_INIT) << BIT_SHIFT_GM_INIT)
+#define BITS_GM_INIT (BIT_MASK_GM_INIT << BIT_SHIFT_GM_INIT)
+#define BIT_CLEAR_GM_INIT(x) ((x) & (~BITS_GM_INIT))
+#define BIT_GET_GM_INIT(x) (((x) >> BIT_SHIFT_GM_INIT) & BIT_MASK_GM_INIT)
+#define BIT_SET_GM_INIT(x, v) (BIT_CLEAR_GM_INIT(x) | BIT_GM_INIT(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_CPHY_LDO				(Offset 0x1054) */
+
+#define BIT_SHIFT_CPHY_LDO_TUNEREF 8
+#define BIT_MASK_CPHY_LDO_TUNEREF 0x3
+#define BIT_CPHY_LDO_TUNEREF(x)                                                \
+	(((x) & BIT_MASK_CPHY_LDO_TUNEREF) << BIT_SHIFT_CPHY_LDO_TUNEREF)
+#define BITS_CPHY_LDO_TUNEREF                                                  \
+	(BIT_MASK_CPHY_LDO_TUNEREF << BIT_SHIFT_CPHY_LDO_TUNEREF)
+#define BIT_CLEAR_CPHY_LDO_TUNEREF(x) ((x) & (~BITS_CPHY_LDO_TUNEREF))
+#define BIT_GET_CPHY_LDO_TUNEREF(x)                                            \
+	(((x) >> BIT_SHIFT_CPHY_LDO_TUNEREF) & BIT_MASK_CPHY_LDO_TUNEREF)
+#define BIT_SET_CPHY_LDO_TUNEREF(x, v)                                         \
+	(BIT_CLEAR_CPHY_LDO_TUNEREF(x) | BIT_CPHY_LDO_TUNEREF(v))
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_ANAPAR_XTAL_AACK_0			(Offset 0x1054) */
+
+#define BIT_SHIFT_XTAL_OV_UNIT 6
+#define BIT_MASK_XTAL_OV_UNIT 0x7
+#define BIT_XTAL_OV_UNIT(x)                                                    \
+	(((x) & BIT_MASK_XTAL_OV_UNIT) << BIT_SHIFT_XTAL_OV_UNIT)
+#define BITS_XTAL_OV_UNIT (BIT_MASK_XTAL_OV_UNIT << BIT_SHIFT_XTAL_OV_UNIT)
+#define BIT_CLEAR_XTAL_OV_UNIT(x) ((x) & (~BITS_XTAL_OV_UNIT))
+#define BIT_GET_XTAL_OV_UNIT(x)                                                \
+	(((x) >> BIT_SHIFT_XTAL_OV_UNIT) & BIT_MASK_XTAL_OV_UNIT)
+#define BIT_SET_XTAL_OV_UNIT(x, v)                                             \
+	(BIT_CLEAR_XTAL_OV_UNIT(x) | BIT_XTAL_OV_UNIT(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_CPHY_LDO				(Offset 0x1054) */
+
+#define BIT_SHIFT_CPHY_LDO_TUNE_VO 5
+#define BIT_MASK_CPHY_LDO_TUNE_VO 0x7
+#define BIT_CPHY_LDO_TUNE_VO(x)                                                \
+	(((x) & BIT_MASK_CPHY_LDO_TUNE_VO) << BIT_SHIFT_CPHY_LDO_TUNE_VO)
+#define BITS_CPHY_LDO_TUNE_VO                                                  \
+	(BIT_MASK_CPHY_LDO_TUNE_VO << BIT_SHIFT_CPHY_LDO_TUNE_VO)
+#define BIT_CLEAR_CPHY_LDO_TUNE_VO(x) ((x) & (~BITS_CPHY_LDO_TUNE_VO))
+#define BIT_GET_CPHY_LDO_TUNE_VO(x)                                            \
+	(((x) >> BIT_SHIFT_CPHY_LDO_TUNE_VO) & BIT_MASK_CPHY_LDO_TUNE_VO)
+#define BIT_SET_CPHY_LDO_TUNE_VO(x, v)                                         \
+	(BIT_CLEAR_CPHY_LDO_TUNE_VO(x) | BIT_CPHY_LDO_TUNE_VO(v))
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_ANAPAR_XTAL_AACK_0			(Offset 0x1054) */
+
+#define BIT_SHIFT_XTAL_MODE_MANUAL 4
+#define BIT_MASK_XTAL_MODE_MANUAL 0x3
+#define BIT_XTAL_MODE_MANUAL(x)                                                \
+	(((x) & BIT_MASK_XTAL_MODE_MANUAL) << BIT_SHIFT_XTAL_MODE_MANUAL)
+#define BITS_XTAL_MODE_MANUAL                                                  \
+	(BIT_MASK_XTAL_MODE_MANUAL << BIT_SHIFT_XTAL_MODE_MANUAL)
+#define BIT_CLEAR_XTAL_MODE_MANUAL(x) ((x) & (~BITS_XTAL_MODE_MANUAL))
+#define BIT_GET_XTAL_MODE_MANUAL(x)                                            \
+	(((x) >> BIT_SHIFT_XTAL_MODE_MANUAL) & BIT_MASK_XTAL_MODE_MANUAL)
+#define BIT_SET_XTAL_MODE_MANUAL(x, v)                                         \
+	(BIT_CLEAR_XTAL_MODE_MANUAL(x) | BIT_XTAL_MODE_MANUAL(v))
+
+#define BIT_SHIFT_PK_END_AR 3
+#define BIT_MASK_PK_END_AR 0x3
+#define BIT_PK_END_AR(x) (((x) & BIT_MASK_PK_END_AR) << BIT_SHIFT_PK_END_AR)
+#define BITS_PK_END_AR (BIT_MASK_PK_END_AR << BIT_SHIFT_PK_END_AR)
+#define BIT_CLEAR_PK_END_AR(x) ((x) & (~BITS_PK_END_AR))
+#define BIT_GET_PK_END_AR(x) (((x) >> BIT_SHIFT_PK_END_AR) & BIT_MASK_PK_END_AR)
+#define BIT_SET_PK_END_AR(x, v) (BIT_CLEAR_PK_END_AR(x) | BIT_PK_END_AR(v))
+
+#define BIT_XTAL_MANU_SEL BIT(3)
+
+#define BIT_SHIFT_XAAC_GM_OFFSET 2
+#define BIT_MASK_XAAC_GM_OFFSET 0x1f
+#define BIT_XAAC_GM_OFFSET(x)                                                  \
+	(((x) & BIT_MASK_XAAC_GM_OFFSET) << BIT_SHIFT_XAAC_GM_OFFSET)
+#define BITS_XAAC_GM_OFFSET                                                    \
+	(BIT_MASK_XAAC_GM_OFFSET << BIT_SHIFT_XAAC_GM_OFFSET)
+#define BIT_CLEAR_XAAC_GM_OFFSET(x) ((x) & (~BITS_XAAC_GM_OFFSET))
+#define BIT_GET_XAAC_GM_OFFSET(x)                                              \
+	(((x) >> BIT_SHIFT_XAAC_GM_OFFSET) & BIT_MASK_XAAC_GM_OFFSET)
+#define BIT_SET_XAAC_GM_OFFSET(x, v)                                           \
+	(BIT_CLEAR_XAAC_GM_OFFSET(x) | BIT_XAAC_GM_OFFSET(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_CPHY_LDO				(Offset 0x1054) */
+
+#define BIT_SHIFT_CPHY_LDO_OCP_VTH 2
+#define BIT_MASK_CPHY_LDO_OCP_VTH 0x7
+#define BIT_CPHY_LDO_OCP_VTH(x)                                                \
+	(((x) & BIT_MASK_CPHY_LDO_OCP_VTH) << BIT_SHIFT_CPHY_LDO_OCP_VTH)
+#define BITS_CPHY_LDO_OCP_VTH                                                  \
+	(BIT_MASK_CPHY_LDO_OCP_VTH << BIT_SHIFT_CPHY_LDO_OCP_VTH)
+#define BIT_CLEAR_CPHY_LDO_OCP_VTH(x) ((x) & (~BITS_CPHY_LDO_OCP_VTH))
+#define BIT_GET_CPHY_LDO_OCP_VTH(x)                                            \
+	(((x) >> BIT_SHIFT_CPHY_LDO_OCP_VTH) & BIT_MASK_CPHY_LDO_OCP_VTH)
+#define BIT_SET_CPHY_LDO_OCP_VTH(x, v)                                         \
+	(BIT_CLEAR_CPHY_LDO_OCP_VTH(x) | BIT_CPHY_LDO_OCP_VTH(v))
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_ANAPAR_XTAL_AACK_0			(Offset 0x1054) */
+
+#define BIT_SHIFT_PK_START_AR 1
+#define BIT_MASK_PK_START_AR 0x3
+#define BIT_PK_START_AR(x)                                                     \
+	(((x) & BIT_MASK_PK_START_AR) << BIT_SHIFT_PK_START_AR)
+#define BITS_PK_START_AR (BIT_MASK_PK_START_AR << BIT_SHIFT_PK_START_AR)
+#define BIT_CLEAR_PK_START_AR(x) ((x) & (~BITS_PK_START_AR))
+#define BIT_GET_PK_START_AR(x)                                                 \
+	(((x) >> BIT_SHIFT_PK_START_AR) & BIT_MASK_PK_START_AR)
+#define BIT_SET_PK_START_AR(x, v)                                              \
+	(BIT_CLEAR_PK_START_AR(x) | BIT_PK_START_AR(v))
+
+#define BIT_XTAL_MODE BIT(1)
+#define BIT_XAAC_LUT_MANUAL_EN BIT(0)
+#define BIT_RESET_N_DECODER BIT(0)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_CPHY_LDO				(Offset 0x1054) */
+
+#define BIT_SHIFT_VREF_LDO_OK 0
+#define BIT_MASK_VREF_LDO_OK 0x3
+#define BIT_VREF_LDO_OK(x)                                                     \
+	(((x) & BIT_MASK_VREF_LDO_OK) << BIT_SHIFT_VREF_LDO_OK)
+#define BITS_VREF_LDO_OK (BIT_MASK_VREF_LDO_OK << BIT_SHIFT_VREF_LDO_OK)
+#define BIT_CLEAR_VREF_LDO_OK(x) ((x) & (~BITS_VREF_LDO_OK))
+#define BIT_GET_VREF_LDO_OK(x)                                                 \
+	(((x) >> BIT_SHIFT_VREF_LDO_OK) & BIT_MASK_VREF_LDO_OK)
+#define BIT_SET_VREF_LDO_OK(x, v)                                              \
+	(BIT_CLEAR_VREF_LDO_OK(x) | BIT_VREF_LDO_OK(v))
+
+/* 2 REG_CPHY_BG				(Offset 0x1058) */
+
+#define BIT_TXBCN_OK_PORT4 BIT(31)
+#define BIT_ATIMEND_PORT4 BIT(31)
+#define BIT_TXBCN_OK_PORT3 BIT(30)
+#define BIT_ATIMEND_PORT3 BIT(30)
+#define BIT_TXBCN_OK_PORT2 BIT(29)
+#define BIT_ATIMEND_PORT2 BIT(29)
+#define BIT_TXBCN_OK_PORT1 BIT(28)
+#define BIT_ATIMEND_PORT1 BIT(28)
+#define BIT_TXBCN15OK BIT(23)
+#define BIT_BCNDMAINT15 BIT(23)
+#define BIT_ATIMEND15 BIT(23)
+#define BIT_TXBCN14OK BIT(22)
+#define BIT_BCNDMAINT14 BIT(22)
+#define BIT_ATIMEND14 BIT(22)
+#define BIT_TXBCN13OK BIT(21)
+#define BIT_BCNDMAINT13 BIT(21)
+#define BIT_ATIMEND13 BIT(21)
+#define BIT_TXBCN12OK BIT(20)
+#define BIT_BCNDMAINT12 BIT(20)
+#define BIT_ATIMEND12 BIT(20)
+#define BIT_TXBCN11OK BIT(19)
+#define BIT_BCNDMAINT11 BIT(19)
+#define BIT_ATIMEND11 BIT(19)
+#define BIT_TXBCN10OK BIT(18)
+#define BIT_BCNDMAINT10 BIT(18)
+#define BIT_ATIMEND10 BIT(18)
+#define BIT_TXBCN9OK BIT(17)
+#define BIT_BCNDMAINT9 BIT(17)
+#define BIT_ATIMEND9 BIT(17)
+#define BIT_TXBCN8OK BIT(16)
+#define BIT_BCNDMAINT8 BIT(16)
+#define BIT_ATIMEND8 BIT(16)
+#define BIT_BCNDERR_PORT4 BIT(15)
+#define BIT_BCNDERR_PORT3 BIT(14)
+#define BIT_BCNDERR_PORT2 BIT(13)
+#define BIT_BCNDERR_PORT1 BIT(12)
+#define BIT_TXBCN15ERR BIT(7)
+#define BIT_BCNDERR15 BIT(7)
+#define BIT_TXBCN14ERR BIT(6)
+#define BIT_BCNDERR14 BIT(6)
+#define BIT_TXBCN13ERR BIT(5)
+#define BIT_BCNDERR13 BIT(5)
+#define BIT_PS_TIMER_EARLY_INT_5 BIT(5)
+#define BIT_TXBCN12ERR BIT(4)
+#define BIT_BCNDERR12 BIT(4)
+#define BIT_PS_TIMER_EARLY_INT_4 BIT(4)
+#define BIT_TXBCN11ERR BIT(3)
+#define BIT_BCNDERR11 BIT(3)
+#define BIT_PS_TIMER_EARLY_INT_3 BIT(3)
+#define BIT_TXBCN10ERR BIT(2)
+#define BIT_BCNDERR10 BIT(2)
+#define BIT_PS_TIMER_EARLY_INT_2 BIT(2)
+#define BIT_TXBCN9ERR BIT(1)
+#define BIT_BCNDERR9 BIT(1)
+#define BIT_PS_TIMER_EARLY_INT_1 BIT(1)
+
+#define BIT_SHIFT_BG 0
+#define BIT_MASK_BG 0x7
+#define BIT_BG(x) (((x) & BIT_MASK_BG) << BIT_SHIFT_BG)
+#define BITS_BG (BIT_MASK_BG << BIT_SHIFT_BG)
+#define BIT_CLEAR_BG(x) ((x) & (~BITS_BG))
+#define BIT_GET_BG(x) (((x) >> BIT_SHIFT_BG) & BIT_MASK_BG)
+#define BIT_SET_BG(x, v) (BIT_CLEAR_BG(x) | BIT_BG(v))
+
+#define BIT_TXBCN8ERR BIT(0)
+#define BIT_BCNDERR8 BIT(0)
+#define BIT_PS_TIMER_EARLY_INT_0 BIT(0)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_SYS_CFG5				(Offset 0x1070) */
+
+#define BIT_LPS_STATUS BIT(3)
+#define BIT_HCI_TXDMA_BUSY BIT(2)
+#define BIT_HCI_TXDMA_ALLOW BIT(1)
+#define BIT_FW_CTRL_HCI_TXDMA_EN BIT(0)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT)
+
+/* 2 REG_REGU_32K_1				(Offset 0x1078) */
+
+#define BIT_OUT_SEL BIT(26)
+
+#define BIT_SHIFT_FREQ_SEL 24
+#define BIT_MASK_FREQ_SEL 0x3
+#define BIT_FREQ_SEL(x) (((x) & BIT_MASK_FREQ_SEL) << BIT_SHIFT_FREQ_SEL)
+#define BITS_FREQ_SEL (BIT_MASK_FREQ_SEL << BIT_SHIFT_FREQ_SEL)
+#define BIT_CLEAR_FREQ_SEL(x) ((x) & (~BITS_FREQ_SEL))
+#define BIT_GET_FREQ_SEL(x) (((x) >> BIT_SHIFT_FREQ_SEL) & BIT_MASK_FREQ_SEL)
+#define BIT_SET_FREQ_SEL(x, v) (BIT_CLEAR_FREQ_SEL(x) | BIT_FREQ_SEL(v))
+
+#define BIT_SHIFT_CLKGEN0 16
+#define BIT_MASK_CLKGEN0 0xff
+#define BIT_CLKGEN0(x) (((x) & BIT_MASK_CLKGEN0) << BIT_SHIFT_CLKGEN0)
+#define BITS_CLKGEN0 (BIT_MASK_CLKGEN0 << BIT_SHIFT_CLKGEN0)
+#define BIT_CLEAR_CLKGEN0(x) ((x) & (~BITS_CLKGEN0))
+#define BIT_GET_CLKGEN0(x) (((x) >> BIT_SHIFT_CLKGEN0) & BIT_MASK_CLKGEN0)
+#define BIT_SET_CLKGEN0(x, v) (BIT_CLEAR_CLKGEN0(x) | BIT_CLKGEN0(v))
+
+#define BIT_SHIFT_TEMP_COMP 12
+#define BIT_MASK_TEMP_COMP 0xf
+#define BIT_TEMP_COMP(x) (((x) & BIT_MASK_TEMP_COMP) << BIT_SHIFT_TEMP_COMP)
+#define BITS_TEMP_COMP (BIT_MASK_TEMP_COMP << BIT_SHIFT_TEMP_COMP)
+#define BIT_CLEAR_TEMP_COMP(x) ((x) & (~BITS_TEMP_COMP))
+#define BIT_GET_TEMP_COMP(x) (((x) >> BIT_SHIFT_TEMP_COMP) & BIT_MASK_TEMP_COMP)
+#define BIT_SET_TEMP_COMP(x, v) (BIT_CLEAR_TEMP_COMP(x) | BIT_TEMP_COMP(v))
+
+#define BIT_SHIFT_LDO_V18ADJ 8
+#define BIT_MASK_LDO_V18ADJ 0xf
+#define BIT_LDO_V18ADJ(x) (((x) & BIT_MASK_LDO_V18ADJ) << BIT_SHIFT_LDO_V18ADJ)
+#define BITS_LDO_V18ADJ (BIT_MASK_LDO_V18ADJ << BIT_SHIFT_LDO_V18ADJ)
+#define BIT_CLEAR_LDO_V18ADJ(x) ((x) & (~BITS_LDO_V18ADJ))
+#define BIT_GET_LDO_V18ADJ(x)                                                  \
+	(((x) >> BIT_SHIFT_LDO_V18ADJ) & BIT_MASK_LDO_V18ADJ)
+#define BIT_SET_LDO_V18ADJ(x, v) (BIT_CLEAR_LDO_V18ADJ(x) | BIT_LDO_V18ADJ(v))
+
+#define BIT_SHIFT_COMP_LOAD_CUR 5
+#define BIT_MASK_COMP_LOAD_CUR 0x3
+#define BIT_COMP_LOAD_CUR(x)                                                   \
+	(((x) & BIT_MASK_COMP_LOAD_CUR) << BIT_SHIFT_COMP_LOAD_CUR)
+#define BITS_COMP_LOAD_CUR (BIT_MASK_COMP_LOAD_CUR << BIT_SHIFT_COMP_LOAD_CUR)
+#define BIT_CLEAR_COMP_LOAD_CUR(x) ((x) & (~BITS_COMP_LOAD_CUR))
+#define BIT_GET_COMP_LOAD_CUR(x)                                               \
+	(((x) >> BIT_SHIFT_COMP_LOAD_CUR) & BIT_MASK_COMP_LOAD_CUR)
+#define BIT_SET_COMP_LOAD_CUR(x, v)                                            \
+	(BIT_CLEAR_COMP_LOAD_CUR(x) | BIT_COMP_LOAD_CUR(v))
+
+#define BIT_SHIFT_COMP_LATCH_CUR 3
+#define BIT_MASK_COMP_LATCH_CUR 0x3
+#define BIT_COMP_LATCH_CUR(x)                                                  \
+	(((x) & BIT_MASK_COMP_LATCH_CUR) << BIT_SHIFT_COMP_LATCH_CUR)
+#define BITS_COMP_LATCH_CUR                                                    \
+	(BIT_MASK_COMP_LATCH_CUR << BIT_SHIFT_COMP_LATCH_CUR)
+#define BIT_CLEAR_COMP_LATCH_CUR(x) ((x) & (~BITS_COMP_LATCH_CUR))
+#define BIT_GET_COMP_LATCH_CUR(x)                                              \
+	(((x) >> BIT_SHIFT_COMP_LATCH_CUR) & BIT_MASK_COMP_LATCH_CUR)
+#define BIT_SET_COMP_LATCH_CUR(x, v)                                           \
+	(BIT_CLEAR_COMP_LATCH_CUR(x) | BIT_COMP_LATCH_CUR(v))
+
+#define BIT_SHIFT_COMP_GM_CUR 1
+#define BIT_MASK_COMP_GM_CUR 0x3
+#define BIT_COMP_GM_CUR(x)                                                     \
+	(((x) & BIT_MASK_COMP_GM_CUR) << BIT_SHIFT_COMP_GM_CUR)
+#define BITS_COMP_GM_CUR (BIT_MASK_COMP_GM_CUR << BIT_SHIFT_COMP_GM_CUR)
+#define BIT_CLEAR_COMP_GM_CUR(x) ((x) & (~BITS_COMP_GM_CUR))
+#define BIT_GET_COMP_GM_CUR(x)                                                 \
+	(((x) >> BIT_SHIFT_COMP_GM_CUR) & BIT_MASK_COMP_GM_CUR)
+#define BIT_SET_COMP_GM_CUR(x, v)                                              \
+	(BIT_CLEAR_COMP_GM_CUR(x) | BIT_COMP_GM_CUR(v))
+
+/* 2 REG_REGU_32K_2				(Offset 0x107C) */
+
+#define BIT_SEL_RCAL_SOURCE BIT(16)
+
+#define BIT_SHIFT_RCAL 0
+#define BIT_MASK_RCAL 0x3f
+#define BIT_RCAL(x) (((x) & BIT_MASK_RCAL) << BIT_SHIFT_RCAL)
+#define BITS_RCAL (BIT_MASK_RCAL << BIT_SHIFT_RCAL)
+#define BIT_CLEAR_RCAL(x) ((x) & (~BITS_RCAL))
+#define BIT_GET_RCAL(x) (((x) >> BIT_SHIFT_RCAL) & BIT_MASK_RCAL)
+#define BIT_SET_RCAL(x, v) (BIT_CLEAR_RCAL(x) | BIT_RCAL(v))
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_CPU_DMEM_CON			(Offset 0x1080) */
+
+#define BIT_SCH_PHY_TXOP_SIFS_INT BIT(23)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_CPU_DMEM_CON			(Offset 0x1080) */
+
+#define BIT_WDT_AUTO_MODE BIT(22)
+#define BIT_WDT_PLATFORM_EN BIT(21)
+#define BIT_WDT_CPU_EN BIT(20)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_CPU_DMEM_CON			(Offset 0x1080) */
+
+#define BIT_WDT_OPT_IOWRAPPER BIT(19)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_CPU_DMEM_CON			(Offset 0x1080) */
+
+#define BIT_ANA_PORT_IDLE BIT(18)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_CPU_DMEM_CON			(Offset 0x1080) */
+
+#define BIT_TEST_EPHY_BY_REG BIT(17)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_CPU_DMEM_CON			(Offset 0x1080) */
+
+#define BIT_MAC_PORT_IDLE BIT(17)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_CPU_DMEM_CON			(Offset 0x1080) */
+
+#define BIT_SYM_FEN_WLPLT BIT(16)
+#define BIT_TEST_UPHY_BY_REG BIT(16)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_CPU_DMEM_CON			(Offset 0x1080) */
+
+#define BIT_WL_PLATFORM_RST BIT(16)
+#define BIT_WL_SECURITY_CLK BIT(15)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_CPU_DMEM_CON			(Offset 0x1080) */
+
+#define BIT_DDMA_EN BIT(8)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_CPU_DMEM_CON			(Offset 0x1080) */
+
+#define BIT_UPHY_SLB_HW_PRD BIT(7)
+#define BIT_UPHY_FS_SLB_OK BIT(6)
+#define BIT_UPHY_HS_SLB_OK BIT(5)
+#define BIT_UPHY_SLB_CMD BIT(4)
+#define BIT_UPHY_SLB_FAIL BIT(3)
+#define BIT_UPHY_SLB_DONE BIT(2)
+#define BIT_UPHY_FORCE_SLB BIT(1)
+
+#define BIT_SHIFT_SYM_CPU_DMEN_CON 0
+#define BIT_MASK_SYM_CPU_DMEN_CON 0xff
+#define BIT_SYM_CPU_DMEN_CON(x)                                                \
+	(((x) & BIT_MASK_SYM_CPU_DMEN_CON) << BIT_SHIFT_SYM_CPU_DMEN_CON)
+#define BITS_SYM_CPU_DMEN_CON                                                  \
+	(BIT_MASK_SYM_CPU_DMEN_CON << BIT_SHIFT_SYM_CPU_DMEN_CON)
+#define BIT_CLEAR_SYM_CPU_DMEN_CON(x) ((x) & (~BITS_SYM_CPU_DMEN_CON))
+#define BIT_GET_SYM_CPU_DMEN_CON(x)                                            \
+	(((x) >> BIT_SHIFT_SYM_CPU_DMEN_CON) & BIT_MASK_SYM_CPU_DMEN_CON)
+#define BIT_SET_SYM_CPU_DMEN_CON(x, v)                                         \
+	(BIT_CLEAR_SYM_CPU_DMEN_CON(x) | BIT_SYM_CPU_DMEN_CON(v))
+
+#define BIT_SHIFT_BCAM_CTRL 0
+#define BIT_MASK_BCAM_CTRL 0xffffffffL
+#define BIT_BCAM_CTRL(x) (((x) & BIT_MASK_BCAM_CTRL) << BIT_SHIFT_BCAM_CTRL)
+#define BITS_BCAM_CTRL (BIT_MASK_BCAM_CTRL << BIT_SHIFT_BCAM_CTRL)
+#define BIT_CLEAR_BCAM_CTRL(x) ((x) & (~BITS_BCAM_CTRL))
+#define BIT_GET_BCAM_CTRL(x) (((x) >> BIT_SHIFT_BCAM_CTRL) & BIT_MASK_BCAM_CTRL)
+#define BIT_SET_BCAM_CTRL(x, v) (BIT_CLEAR_BCAM_CTRL(x) | BIT_BCAM_CTRL(v))
+
+#define BIT_UPHY_SLB_HS BIT(0)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_CPU_DMEM_CON			(Offset 0x1080) */
+
+#define BIT_SHIFT_CPU_DMEM_CON 0
+#define BIT_MASK_CPU_DMEM_CON 0xff
+#define BIT_CPU_DMEM_CON(x)                                                    \
+	(((x) & BIT_MASK_CPU_DMEM_CON) << BIT_SHIFT_CPU_DMEM_CON)
+#define BITS_CPU_DMEM_CON (BIT_MASK_CPU_DMEM_CON << BIT_SHIFT_CPU_DMEM_CON)
+#define BIT_CLEAR_CPU_DMEM_CON(x) ((x) & (~BITS_CPU_DMEM_CON))
+#define BIT_GET_CPU_DMEM_CON(x)                                                \
+	(((x) >> BIT_SHIFT_CPU_DMEM_CON) & BIT_MASK_CPU_DMEM_CON)
+#define BIT_SET_CPU_DMEM_CON(x, v)                                             \
+	(BIT_CLEAR_CPU_DMEM_CON(x) | BIT_CPU_DMEM_CON(v))
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_BOOT_REASON				(Offset 0x1088) */
+
+#define BIT_SHIFT_BOOT_REASON_V1 0
+#define BIT_MASK_BOOT_REASON_V1 0x7
+#define BIT_BOOT_REASON_V1(x)                                                  \
+	(((x) & BIT_MASK_BOOT_REASON_V1) << BIT_SHIFT_BOOT_REASON_V1)
+#define BITS_BOOT_REASON_V1                                                    \
+	(BIT_MASK_BOOT_REASON_V1 << BIT_SHIFT_BOOT_REASON_V1)
+#define BIT_CLEAR_BOOT_REASON_V1(x) ((x) & (~BITS_BOOT_REASON_V1))
+#define BIT_GET_BOOT_REASON_V1(x)                                              \
+	(((x) >> BIT_SHIFT_BOOT_REASON_V1) & BIT_MASK_BOOT_REASON_V1)
+#define BIT_SET_BOOT_REASON_V1(x, v)                                           \
+	(BIT_CLEAR_BOOT_REASON_V1(x) | BIT_BOOT_REASON_V1(v))
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+/* 2 REG_HIMR4				(Offset 0x1090) */
+
+#define BIT_ATIM_END_INT16_MSK BIT(32)
+#define BIT_ATIM_END_INT15_MSK BIT(31)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_DATA_CPU_CTL0			(Offset 0x1090) */
+
+#define BIT_DATA_FW_READY BIT(31)
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+/* 2 REG_HIMR4				(Offset 0x1090) */
+
+#define BIT_ATIM_END_INT14_MSK BIT(30)
+#define BIT_ATIM_END_INT13_MSK BIT(29)
+#define BIT_ATIM_END_INT12_MSK BIT(28)
+#define BIT_ATIM_END_INT11_MSK BIT(27)
+#define BIT_ATIM_END_INT10_MSK BIT(26)
+#define BIT_ATIM_END_INT9_MSK BIT(25)
+#define BIT_ATIM_END_INT8_MSK BIT(24)
+#define BIT_TX_BCN_ERR_INT15_MSK BIT(23)
+#define BIT_TX_BCN_ERR_INT14_MSK BIT(22)
+#define BIT_TX_BCN_ERR_INT13_MSK BIT(21)
+#define BIT_TX_BCN_ERR_INT12_MSK BIT(20)
+#define BIT_TX_BCN_ERR_INT11_MSK BIT(19)
+#define BIT_TX_BCN_ERR_INT10_MSK BIT(18)
+#define BIT_TX_BCN_ERR_INT9_MSK BIT(17)
+#define BIT_TX_BCN_ERR_INT8_MSK BIT(16)
+#define BIT_TX_BCN_OK_INT15_MSK BIT(15)
+#define BIT_TX_BCN_OK_INT14_MSK BIT(14)
+#define BIT_TX_BCN_OK_INT13_MSK BIT(13)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_DATA_CPU_CTL0			(Offset 0x1090) */
+
+#define BIT_WDT_SYS_RST BIT(13)
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+/* 2 REG_HIMR4				(Offset 0x1090) */
+
+#define BIT_TX_BCN_OK_INT12_MSK BIT(12)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_DATA_CPU_CTL0			(Offset 0x1090) */
+
+#define BIT_WDT_ENABLE BIT(12)
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+/* 2 REG_HIMR4				(Offset 0x1090) */
+
+#define BIT_TX_BCN_OK_INT11_MSK BIT(11)
+#define BIT_TX_BCN_OK_INT10_MSK BIT(10)
+#define BIT_TX_BCN_OK_INT9_MSK BIT(9)
+#define BIT_TX_BCN_OK_INT8_MSK BIT(8)
+#define BIT_BCN_DMA_INT15_MSK BIT(7)
+#define BIT_BCN_DMA_INT14_MSK BIT(6)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_DATA_CPU_CTL0			(Offset 0x1090) */
+
+#define BIT_SHIFT_BOOT_SEL 6
+#define BIT_MASK_BOOT_SEL 0x3
+#define BIT_BOOT_SEL(x) (((x) & BIT_MASK_BOOT_SEL) << BIT_SHIFT_BOOT_SEL)
+#define BITS_BOOT_SEL (BIT_MASK_BOOT_SEL << BIT_SHIFT_BOOT_SEL)
+#define BIT_CLEAR_BOOT_SEL(x) ((x) & (~BITS_BOOT_SEL))
+#define BIT_GET_BOOT_SEL(x) (((x) >> BIT_SHIFT_BOOT_SEL) & BIT_MASK_BOOT_SEL)
+#define BIT_SET_BOOT_SEL(x, v) (BIT_CLEAR_BOOT_SEL(x) | BIT_BOOT_SEL(v))
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+/* 2 REG_HIMR4				(Offset 0x1090) */
+
+#define BIT_BCN_DMA_INT13_MSK BIT(5)
+#define BIT_BCN_DMA_INT12_MSK BIT(4)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_DATA_CPU_CTL0			(Offset 0x1090) */
+
+#define BIT_CLK_SEL BIT(4)
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+/* 2 REG_HIMR4				(Offset 0x1090) */
+
+#define BIT_BCN_DMA_INT11_MSK BIT(3)
+#define BIT_BCN_DMA_INT10_MSK BIT(2)
+#define BIT_BCN_DMA_INT9_MSK BIT(1)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_DATA_CPU_CTL0			(Offset 0x1090) */
+
+#define BIT_DATA_PLATFORM_RST BIT(1)
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+/* 2 REG_HIMR4				(Offset 0x1090) */
+
+#define BIT_BCN_DMA_INT8_MSK BIT(0)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_DATA_CPU_CTL0			(Offset 0x1090) */
+
+#define BIT_DATA_CPU_RST BIT(0)
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+/* 2 REG_HISR4				(Offset 0x1094) */
+
+#define BIT_TX_BCN_ERR_INT15 BIT(23)
+#define BIT_TX_BCN_ERR_INT14 BIT(22)
+#define BIT_TX_BCN_ERR_INT13 BIT(21)
+#define BIT_TX_BCN_ERR_INT12 BIT(20)
+#define BIT_TX_BCN_ERR_INT11 BIT(19)
+#define BIT_TX_BCN_ERR_INT10 BIT(18)
+#define BIT_TX_BCN_ERR_INT9 BIT(17)
+#define BIT_TX_BCN_ERR_INT8 BIT(16)
+#define BIT_TX_BCN_OK_INT15 BIT(15)
+#define BIT_TX_BCN_OK_INT14 BIT(14)
+#define BIT_TX_BCN_OK_INT13 BIT(13)
+#define BIT_TX_BCN_OK_INT12 BIT(12)
+#define BIT_TX_BCN_OK_INT11 BIT(11)
+#define BIT_TX_BCN_OK_INT10 BIT(10)
+#define BIT_TX_BCN_OK_INT9 BIT(9)
+#define BIT_TX_BCN_OK_INT8 BIT(8)
+#define BIT_BCN_DMA_INT15 BIT(7)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_DATA_CPU_CTL1			(Offset 0x1094) */
+
+#define BIT_HOST_INTERFACE_IO_PATH BIT(7)
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+/* 2 REG_HISR4				(Offset 0x1094) */
+
+#define BIT_BCN_DMA_INT14 BIT(6)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_DATA_CPU_CTL1			(Offset 0x1094) */
+
+#define BIT_EN_TXDMA_OFLD BIT(6)
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+/* 2 REG_HISR4				(Offset 0x1094) */
+
+#define BIT_BCN_DMA_INT13 BIT(5)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_DATA_CPU_CTL1			(Offset 0x1094) */
+
+#define BIT_EN_RXDMA_OFLD BIT(5)
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+/* 2 REG_HISR4				(Offset 0x1094) */
+
+#define BIT_BCN_DMA_INT12 BIT(4)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_DATA_CPU_CTL1			(Offset 0x1094) */
+
+#define BIT_EN_HCI_DMA_TX BIT(4)
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+/* 2 REG_HISR4				(Offset 0x1094) */
+
+#define BIT_BCN_DMA_INT11 BIT(3)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_DATA_CPU_CTL1			(Offset 0x1094) */
+
+#define BIT_EN_HCI_DMA_RX BIT(3)
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+/* 2 REG_HISR4				(Offset 0x1094) */
+
+#define BIT_BCN_DMA_INT10 BIT(2)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_DATA_CPU_CTL1			(Offset 0x1094) */
+
+#define BIT_EN_AXI_DMA_TX BIT(2)
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+/* 2 REG_HISR4				(Offset 0x1094) */
+
+#define BIT_BCN_DMA_INT9 BIT(1)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_DATA_CPU_CTL1			(Offset 0x1094) */
+
+#define BIT_EN_AXI_DMA_RX BIT(1)
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+/* 2 REG_HISR4				(Offset 0x1094) */
+
+#define BIT_BCN_DMA_INT8 BIT(0)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_DATA_CPU_CTL1			(Offset 0x1094) */
+
+#define BIT_EN_PKT_ENG BIT(0)
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+/* 2 REG_HIMR5				(Offset 0x1098) */
+
+#define BIT_BCN_QDMA_ERR_INT15_MSK BIT(7)
+#define BIT_BCN_QDMA_ERR_INT14_MSK BIT(6)
+#define BIT_BCN_QDMA_ERR_INT13_MSK BIT(5)
+#define BIT_BCN_QDMA_ERR_INT12_MSK BIT(4)
+#define BIT_BCN_QDMA_ERR_INT11_MSK BIT(3)
+#define BIT_BCN_QDMA_ERR_INT10_MSK BIT(2)
+#define BIT_BCN_QDMA_ERR_INT9_MSK BIT(1)
+#define BIT_BCN_QDMA_ERR_INT8_MSK BIT(0)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_TXDMA_STOP_HIMR			(Offset 0x1098) */
+
+#define BIT_SHIFT_NTH_TXDMA_STOP_INT_MSK 0
+#define BIT_MASK_NTH_TXDMA_STOP_INT_MSK 0x1ffff
+#define BIT_NTH_TXDMA_STOP_INT_MSK(x)                                          \
+	(((x) & BIT_MASK_NTH_TXDMA_STOP_INT_MSK)                               \
+	 << BIT_SHIFT_NTH_TXDMA_STOP_INT_MSK)
+#define BITS_NTH_TXDMA_STOP_INT_MSK                                            \
+	(BIT_MASK_NTH_TXDMA_STOP_INT_MSK << BIT_SHIFT_NTH_TXDMA_STOP_INT_MSK)
+#define BIT_CLEAR_NTH_TXDMA_STOP_INT_MSK(x)                                    \
+	((x) & (~BITS_NTH_TXDMA_STOP_INT_MSK))
+#define BIT_GET_NTH_TXDMA_STOP_INT_MSK(x)                                      \
+	(((x) >> BIT_SHIFT_NTH_TXDMA_STOP_INT_MSK) &                           \
+	 BIT_MASK_NTH_TXDMA_STOP_INT_MSK)
+#define BIT_SET_NTH_TXDMA_STOP_INT_MSK(x, v)                                   \
+	(BIT_CLEAR_NTH_TXDMA_STOP_INT_MSK(x) | BIT_NTH_TXDMA_STOP_INT_MSK(v))
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+/* 2 REG_HISR5				(Offset 0x109C) */
+
+#define BIT_BCN_QDMA_ERR_INT15 BIT(7)
+#define BIT_BCN_QDMA_ERR_INT14 BIT(6)
+#define BIT_BCN_QDMA_ERR_INT13 BIT(5)
+#define BIT_BCN_QDMA_ERR_INT12 BIT(4)
+#define BIT_BCN_QDMA_ERR_INT11 BIT(3)
+#define BIT_BCN_QDMA_ERR_INT10 BIT(2)
+#define BIT_BCN_QDMA_ERR_INT9 BIT(1)
+#define BIT_BCN_QDMA_ERR_INT8 BIT(0)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_TXDMA_STOP_HISR			(Offset 0x109C) */
+
+#define BIT_SHIFT_NTH_TXDMA_STOP_INT 0
+#define BIT_MASK_NTH_TXDMA_STOP_INT 0x1ffff
+#define BIT_NTH_TXDMA_STOP_INT(x)                                              \
+	(((x) & BIT_MASK_NTH_TXDMA_STOP_INT) << BIT_SHIFT_NTH_TXDMA_STOP_INT)
+#define BITS_NTH_TXDMA_STOP_INT                                                \
+	(BIT_MASK_NTH_TXDMA_STOP_INT << BIT_SHIFT_NTH_TXDMA_STOP_INT)
+#define BIT_CLEAR_NTH_TXDMA_STOP_INT(x) ((x) & (~BITS_NTH_TXDMA_STOP_INT))
+#define BIT_GET_NTH_TXDMA_STOP_INT(x)                                          \
+	(((x) >> BIT_SHIFT_NTH_TXDMA_STOP_INT) & BIT_MASK_NTH_TXDMA_STOP_INT)
+#define BIT_SET_NTH_TXDMA_STOP_INT(x, v)                                       \
+	(BIT_CLEAR_NTH_TXDMA_STOP_INT(x) | BIT_NTH_TXDMA_STOP_INT(v))
+
+/* 2 REG_TXDMA_START_HIMR			(Offset 0x10A0) */
+
+#define BIT_SHIFT_NTH_TXDMA_START_INT_MSK 0
+#define BIT_MASK_NTH_TXDMA_START_INT_MSK 0x1ffff
+#define BIT_NTH_TXDMA_START_INT_MSK(x)                                         \
+	(((x) & BIT_MASK_NTH_TXDMA_START_INT_MSK)                              \
+	 << BIT_SHIFT_NTH_TXDMA_START_INT_MSK)
+#define BITS_NTH_TXDMA_START_INT_MSK                                           \
+	(BIT_MASK_NTH_TXDMA_START_INT_MSK << BIT_SHIFT_NTH_TXDMA_START_INT_MSK)
+#define BIT_CLEAR_NTH_TXDMA_START_INT_MSK(x)                                   \
+	((x) & (~BITS_NTH_TXDMA_START_INT_MSK))
+#define BIT_GET_NTH_TXDMA_START_INT_MSK(x)                                     \
+	(((x) >> BIT_SHIFT_NTH_TXDMA_START_INT_MSK) &                          \
+	 BIT_MASK_NTH_TXDMA_START_INT_MSK)
+#define BIT_SET_NTH_TXDMA_START_INT_MSK(x, v)                                  \
+	(BIT_CLEAR_NTH_TXDMA_START_INT_MSK(x) | BIT_NTH_TXDMA_START_INT_MSK(v))
+
+/* 2 REG_TXDMA_START_HISR			(Offset 0x10A4) */
+
+#define BIT_SHIFT_NTH_TXDMA_START_INT 0
+#define BIT_MASK_NTH_TXDMA_START_INT 0x1ffff
+#define BIT_NTH_TXDMA_START_INT(x)                                             \
+	(((x) & BIT_MASK_NTH_TXDMA_START_INT) << BIT_SHIFT_NTH_TXDMA_START_INT)
+#define BITS_NTH_TXDMA_START_INT                                               \
+	(BIT_MASK_NTH_TXDMA_START_INT << BIT_SHIFT_NTH_TXDMA_START_INT)
+#define BIT_CLEAR_NTH_TXDMA_START_INT(x) ((x) & (~BITS_NTH_TXDMA_START_INT))
+#define BIT_GET_NTH_TXDMA_START_INT(x)                                         \
+	(((x) >> BIT_SHIFT_NTH_TXDMA_START_INT) & BIT_MASK_NTH_TXDMA_START_INT)
+#define BIT_SET_NTH_TXDMA_START_INT(x, v)                                      \
+	(BIT_CLEAR_NTH_TXDMA_START_INT(x) | BIT_NTH_TXDMA_START_INT(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+
+/* 2 REG_NFCPAD_CTRL				(Offset 0x10A8) */
+
+#define BIT_PAD_SHUTDW BIT(18)
+#define BIT_SYSON_NFC_PAD BIT(17)
+#define BIT_NFC_INT_PAD_CTRL BIT(16)
+#define BIT_NFC_RFDIS_PAD_CTRL BIT(15)
+#define BIT_NFC_CLK_PAD_CTRL BIT(14)
+#define BIT_NFC_DATA_PAD_CTRL BIT(13)
+#define BIT_NFC_PAD_PULL_CTRL BIT(12)
+
+#define BIT_SHIFT_NFCPAD_IO_SEL 8
+#define BIT_MASK_NFCPAD_IO_SEL 0xf
+#define BIT_NFCPAD_IO_SEL(x)                                                   \
+	(((x) & BIT_MASK_NFCPAD_IO_SEL) << BIT_SHIFT_NFCPAD_IO_SEL)
+#define BITS_NFCPAD_IO_SEL (BIT_MASK_NFCPAD_IO_SEL << BIT_SHIFT_NFCPAD_IO_SEL)
+#define BIT_CLEAR_NFCPAD_IO_SEL(x) ((x) & (~BITS_NFCPAD_IO_SEL))
+#define BIT_GET_NFCPAD_IO_SEL(x)                                               \
+	(((x) >> BIT_SHIFT_NFCPAD_IO_SEL) & BIT_MASK_NFCPAD_IO_SEL)
+#define BIT_SET_NFCPAD_IO_SEL(x, v)                                            \
+	(BIT_CLEAR_NFCPAD_IO_SEL(x) | BIT_NFCPAD_IO_SEL(v))
+
+#define BIT_SHIFT_NFCPAD_OUT 4
+#define BIT_MASK_NFCPAD_OUT 0xf
+#define BIT_NFCPAD_OUT(x) (((x) & BIT_MASK_NFCPAD_OUT) << BIT_SHIFT_NFCPAD_OUT)
+#define BITS_NFCPAD_OUT (BIT_MASK_NFCPAD_OUT << BIT_SHIFT_NFCPAD_OUT)
+#define BIT_CLEAR_NFCPAD_OUT(x) ((x) & (~BITS_NFCPAD_OUT))
+#define BIT_GET_NFCPAD_OUT(x)                                                  \
+	(((x) >> BIT_SHIFT_NFCPAD_OUT) & BIT_MASK_NFCPAD_OUT)
+#define BIT_SET_NFCPAD_OUT(x, v) (BIT_CLEAR_NFCPAD_OUT(x) | BIT_NFCPAD_OUT(v))
+
+#define BIT_SHIFT_NFCPAD_IN 0
+#define BIT_MASK_NFCPAD_IN 0xf
+#define BIT_NFCPAD_IN(x) (((x) & BIT_MASK_NFCPAD_IN) << BIT_SHIFT_NFCPAD_IN)
+#define BITS_NFCPAD_IN (BIT_MASK_NFCPAD_IN << BIT_SHIFT_NFCPAD_IN)
+#define BIT_CLEAR_NFCPAD_IN(x) ((x) & (~BITS_NFCPAD_IN))
+#define BIT_GET_NFCPAD_IN(x) (((x) >> BIT_SHIFT_NFCPAD_IN) & BIT_MASK_NFCPAD_IN)
+#define BIT_SET_NFCPAD_IN(x, v) (BIT_CLEAR_NFCPAD_IN(x) | BIT_NFCPAD_IN(v))
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_HIMR2				(Offset 0x10B0) */
+
+#define BIT_BCNDMAINT_P4_MSK BIT(31)
+#define BIT_BCNDMAINT_P4 BIT(31)
+#define BIT_BCNDMAINT_P3_MSK BIT(30)
+#define BIT_BCNDMAINT_P3 BIT(30)
+#define BIT_BCNDMAINT_P2_MSK BIT(29)
+#define BIT_BCNDMAINT_P2 BIT(29)
+#define BIT_BCNDMAINT_P1_MSK BIT(28)
+#define BIT_BCNDMAINT_P1 BIT(28)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_HIMR2				(Offset 0x10B0) */
+
+#define BIT_SCH_PHY_TXOP_SIFS_INT_MSK BIT(23)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_HIMR2				(Offset 0x10B0) */
+
+#define BIT_ATIMEND7_MSK BIT(22)
+#define BIT_ATIMEND7 BIT(22)
+#define BIT_ATIMEND6_MSK BIT(21)
+#define BIT_ATIMEND6 BIT(21)
+#define BIT_ATIMEND5_MSK BIT(20)
+#define BIT_ATIMEND5 BIT(20)
+#define BIT_ATIMEND4_MSK BIT(19)
+#define BIT_ATIMEND4 BIT(19)
+#define BIT_ATIMEND3_MSK BIT(18)
+#define BIT_ATIMEND3 BIT(18)
+#define BIT_ATIMEND2_MSK BIT(17)
+#define BIT_ATIMEND2 BIT(17)
+#define BIT_ATIMEND1_MSK BIT(16)
+#define BIT_ATIMEND1 BIT(16)
+#define BIT_TXBCN7OK_MSK BIT(14)
+#define BIT_TXBCN7OK BIT(14)
+#define BIT_TXBCN6OK_MSK BIT(13)
+#define BIT_TXBCN6OK BIT(13)
+#define BIT_TXBCN5OK_MSK BIT(12)
+#define BIT_TXBCN5OK BIT(12)
+#define BIT_TXBCN4OK_MSK BIT(11)
+#define BIT_TXBCN4OK BIT(11)
+#define BIT_TXBCN3OK_MSK BIT(10)
+#define BIT_TXBCN3OK BIT(10)
+#define BIT_TXBCN2OK_MSK BIT(9)
+#define BIT_TXBCN2OK BIT(9)
+#define BIT_TXBCN1OK_MSK_V1 BIT(8)
+#define BIT_TXBCN1OK BIT(8)
+#define BIT_TXBCN7ERR_MSK BIT(6)
+#define BIT_TXBCN7ERR BIT(6)
+#define BIT_TXBCN6ERR_MSK BIT(5)
+#define BIT_TXBCN6ERR BIT(5)
+#define BIT_TXBCN5ERR_MSK BIT(4)
+#define BIT_TXBCN5ERR BIT(4)
+#define BIT_TXBCN4ERR_MSK BIT(3)
+#define BIT_TXBCN4ERR BIT(3)
+#define BIT_TXBCN3ERR_MSK BIT(2)
+#define BIT_TXBCN3ERR BIT(2)
+#define BIT_TXBCN2ERR_MSK BIT(1)
+#define BIT_TXBCN2ERR BIT(1)
+#define BIT_TXBCN1ERR_MSK_V1 BIT(0)
+#define BIT_TXBCN1ERR BIT(0)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_HIMR3				(Offset 0x10B8) */
+
+#define BIT_GTINT12 BIT(24)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_HIMR3				(Offset 0x10B8) */
+
+#define BIT_GTINT12_MSK BIT(24)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_HIMR3				(Offset 0x10B8) */
+
+#define BIT_GTINT11 BIT(23)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_HIMR3				(Offset 0x10B8) */
+
+#define BIT_GTINT11_MSK BIT(23)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_HIMR3				(Offset 0x10B8) */
+
+#define BIT_GTINT10 BIT(22)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_HIMR3				(Offset 0x10B8) */
+
+#define BIT_GTINT10_MSK BIT(22)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_HIMR3				(Offset 0x10B8) */
+
+#define BIT_GTINT9 BIT(21)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_HIMR3				(Offset 0x10B8) */
+
+#define BIT_GTINT9_MSK BIT(21)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_HIMR3				(Offset 0x10B8) */
+
+#define BIT_RX_DESC_BUF_FULL BIT(20)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_HIMR3				(Offset 0x10B8) */
+
+#define BIT_RX_DESC_BUF_FULL_MSK BIT(20)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_HIMR3				(Offset 0x10B8) */
+
+#define BIT_CPHY_LDO_OCP_DET_INT BIT(19)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_HIMR3				(Offset 0x10B8) */
+
+#define BIT_CPHY_LDO_OCP_DET_INT_MSK BIT(19)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_HIMR3				(Offset 0x10B8) */
+
+#define BIT_WDT_PLATFORM_INT_MSK BIT(18)
+#define BIT_WDT_PLATFORM_INT BIT(18)
+#define BIT_WDT_CPU_INT_MSK BIT(17)
+#define BIT_WDT_CPU_INT BIT(17)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_HIMR3				(Offset 0x10B8) */
+
+#define BIT_SETH2CDOK_MASK BIT(16)
+#define BIT_SETH2CDOK BIT(16)
+#define BIT_H2C_CMD_FULL_MASK BIT(15)
+#define BIT_H2C_CMD_FULL BIT(15)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_HIMR3				(Offset 0x10B8) */
+
+#define BIT_PWR_INT_127_MASK BIT(14)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_HIMR3				(Offset 0x10B8) */
+
+#define BIT_PKT_TRANS_ERR BIT(14)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_HIMR3				(Offset 0x10B8) */
+
+#define BIT_PKT_TRANS_ERR_MASK BIT(14)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_HIMR3				(Offset 0x10B8) */
+
+#define BIT_TXSHORTCUT_TXDESUPDATEOK_MASK BIT(13)
+#define BIT_TXSHORTCUT_TXDESUPDATEOK BIT(13)
+#define BIT_TXSHORTCUT_BKUPDATEOK_MASK BIT(12)
+#define BIT_TXSHORTCUT_BKUPDATEOK BIT(12)
+#define BIT_TXSHORTCUT_BEUPDATEOK_MASK BIT(11)
+#define BIT_TXSHORTCUT_BEUPDATEOK BIT(11)
+#define BIT_TXSHORTCUT_VIUPDATEOK_MAS BIT(10)
+#define BIT_TXSHORTCUT_VIUPDATEOK BIT(10)
+#define BIT_TXSHORTCUT_VOUPDATEOK_MASK BIT(9)
+#define BIT_TXSHORTCUT_VOUPDATEOK BIT(9)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_HIMR3				(Offset 0x10B8) */
+
+#define BIT_PWR_INT_127_MASK_V1 BIT(8)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_HIMR3				(Offset 0x10B8) */
+
+#define BIT_SEARCH_FAIL BIT(8)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_HIMR3				(Offset 0x10B8) */
+
+#define BIT_SEARCH_FAIL_MSK BIT(8)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_HIMR3				(Offset 0x10B8) */
+
+#define BIT_PWR_INT_126TO96_MASK BIT(7)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_HIMR3				(Offset 0x10B8) */
+
+#define BIT_PWR_INT_127TO96 BIT(7)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_HIMR3				(Offset 0x10B8) */
+
+#define BIT_PWR_INT_127TO96_MASK BIT(7)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_HIMR3				(Offset 0x10B8) */
+
+#define BIT_PWR_INT_95TO64_MASK BIT(6)
+#define BIT_PWR_INT_95TO64 BIT(6)
+#define BIT_PWR_INT_63TO32_MASK BIT(5)
+#define BIT_PWR_INT_63TO32 BIT(5)
+#define BIT_PWR_INT_31TO0_MASK BIT(4)
+#define BIT_PWR_INT_31TO0 BIT(4)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_HIMR3				(Offset 0x10B8) */
+
+#define BIT_RX_DMA_STUCK_MSK BIT(3)
+#define BIT_RX_DMA_STUCK BIT(3)
+#define BIT_TX_DMA_STUCK_MSK BIT(2)
+#define BIT_TX_DMA_STUCK BIT(2)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_HIMR3				(Offset 0x10B8) */
+
+#define BIT_DDMA0_LP_INT_MSK BIT(1)
+#define BIT_DDMA0_LP_INT BIT(1)
+#define BIT_DDMA0_HP_INT_MSK BIT(0)
+#define BIT_DDMA0_HP_INT BIT(0)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_HISR3				(Offset 0x10BC) */
+
+#define BIT_PWR_INT_127 BIT(14)
+#define BIT_PWR_INT_127_V1 BIT(8)
+#define BIT_PWR_INT_126TO96 BIT(7)
+#define BIT_ECRC_EN_V1 BIT(7)
+#define BIT_MDIO_RFLAG_V1 BIT(6)
+#define BIT_MDIO_WFLAG_V1 BIT(5)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_SW_MDIO				(Offset 0x10C0) */
+
+#define BIT_WLDSS_RST_N_0 BIT(27)
+#define BIT_WLDSS_RST_N_1 BIT(27)
+#define BIT_WLDSS_RST_N_2 BIT(27)
+#define BIT_WLDSS_ENCLK_0 BIT(26)
+#define BIT_WLDSS_ENCLK_1 BIT(26)
+#define BIT_WLDSS_ENCLK_2 BIT(26)
+#define BIT_WLDSS_SPEED_EN_0 BIT(25)
+#define BIT_WLDSS_SPEED_EN_1 BIT(25)
+#define BIT_WLDSS_SPEED_EN_2 BIT(25)
+#define BIT_WLDSS_WIRE_SEL_0 BIT(24)
+#define BIT_WLDSS_WIRE_SEL_1 BIT(24)
+#define BIT_WLDSS_WIRE_SEL_2 BIT(24)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_SW_MDIO				(Offset 0x10C0) */
+
+#define BIT_DIS_TIMEOUT_IO BIT(24)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_SW_MDIO				(Offset 0x10C0) */
+
+#define BIT_WLDSS_READY_0 BIT(21)
+#define BIT_WLDSS_READY_1 BIT(21)
+#define BIT_WLDSS_READY_2 BIT(21)
+
+#define BIT_SHIFT_WLDSS_RO_SEL_0 20
+#define BIT_MASK_WLDSS_RO_SEL_0 0x7
+#define BIT_WLDSS_RO_SEL_0(x)                                                  \
+	(((x) & BIT_MASK_WLDSS_RO_SEL_0) << BIT_SHIFT_WLDSS_RO_SEL_0)
+#define BITS_WLDSS_RO_SEL_0                                                    \
+	(BIT_MASK_WLDSS_RO_SEL_0 << BIT_SHIFT_WLDSS_RO_SEL_0)
+#define BIT_CLEAR_WLDSS_RO_SEL_0(x) ((x) & (~BITS_WLDSS_RO_SEL_0))
+#define BIT_GET_WLDSS_RO_SEL_0(x)                                              \
+	(((x) >> BIT_SHIFT_WLDSS_RO_SEL_0) & BIT_MASK_WLDSS_RO_SEL_0)
+#define BIT_SET_WLDSS_RO_SEL_0(x, v)                                           \
+	(BIT_CLEAR_WLDSS_RO_SEL_0(x) | BIT_WLDSS_RO_SEL_0(v))
+
+#define BIT_WLDSS_WSORT_GO_0 BIT(20)
+
+#define BIT_SHIFT_WLDSS_RO_SEL_1 20
+#define BIT_MASK_WLDSS_RO_SEL_1 0x7
+#define BIT_WLDSS_RO_SEL_1(x)                                                  \
+	(((x) & BIT_MASK_WLDSS_RO_SEL_1) << BIT_SHIFT_WLDSS_RO_SEL_1)
+#define BITS_WLDSS_RO_SEL_1                                                    \
+	(BIT_MASK_WLDSS_RO_SEL_1 << BIT_SHIFT_WLDSS_RO_SEL_1)
+#define BIT_CLEAR_WLDSS_RO_SEL_1(x) ((x) & (~BITS_WLDSS_RO_SEL_1))
+#define BIT_GET_WLDSS_RO_SEL_1(x)                                              \
+	(((x) >> BIT_SHIFT_WLDSS_RO_SEL_1) & BIT_MASK_WLDSS_RO_SEL_1)
+#define BIT_SET_WLDSS_RO_SEL_1(x, v)                                           \
+	(BIT_CLEAR_WLDSS_RO_SEL_1(x) | BIT_WLDSS_RO_SEL_1(v))
+
+#define BIT_WLDSS_WSORT_GO_1 BIT(20)
+
+#define BIT_SHIFT_WLDSS_RO_SEL_2 20
+#define BIT_MASK_WLDSS_RO_SEL_2 0x7
+#define BIT_WLDSS_RO_SEL_2(x)                                                  \
+	(((x) & BIT_MASK_WLDSS_RO_SEL_2) << BIT_SHIFT_WLDSS_RO_SEL_2)
+#define BITS_WLDSS_RO_SEL_2                                                    \
+	(BIT_MASK_WLDSS_RO_SEL_2 << BIT_SHIFT_WLDSS_RO_SEL_2)
+#define BIT_CLEAR_WLDSS_RO_SEL_2(x) ((x) & (~BITS_WLDSS_RO_SEL_2))
+#define BIT_GET_WLDSS_RO_SEL_2(x)                                              \
+	(((x) >> BIT_SHIFT_WLDSS_RO_SEL_2) & BIT_MASK_WLDSS_RO_SEL_2)
+#define BIT_SET_WLDSS_RO_SEL_2(x, v)                                           \
+	(BIT_CLEAR_WLDSS_RO_SEL_2(x) | BIT_WLDSS_RO_SEL_2(v))
+
+#define BIT_WLDSS_WSORT_GO_2 BIT(20)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_SW_MDIO				(Offset 0x10C0) */
+
+#define BIT_SUS_PL BIT(18)
+#define BIT_SOP_ESUS BIT(17)
+#define BIT_SOP_DLDO BIT(16)
+#define BIT_R_OCP_ST_CLR BIT(8)
+#define BIT_SW_USB3_MD_SEL BIT(5)
+#define BIT_SW_PCIE_MD_SEL BIT(4)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_SW_MDIO				(Offset 0x10C0) */
+
+#define BIT_SYM_SW_PCIE_MDSL BIT(3)
+#define BIT_SYM_SW_PCIE_MDCK BIT(2)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_SW_MDIO				(Offset 0x10C0) */
+
+#define BIT_SW_MDCK BIT(2)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_SW_MDIO				(Offset 0x10C0) */
+
+#define BIT_SYM_SW_PCIE_MDI BIT(1)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_SW_MDIO				(Offset 0x10C0) */
+
+#define BIT_SW_MDI BIT(1)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_SW_MDIO				(Offset 0x10C0) */
+
+#define BIT_SYM_SW_PCIE_MDO BIT(0)
+
+#define BIT_SHIFT_WLDSS_DATA_IN_0 0
+#define BIT_MASK_WLDSS_DATA_IN_0 0xfffff
+#define BIT_WLDSS_DATA_IN_0(x)                                                 \
+	(((x) & BIT_MASK_WLDSS_DATA_IN_0) << BIT_SHIFT_WLDSS_DATA_IN_0)
+#define BITS_WLDSS_DATA_IN_0                                                   \
+	(BIT_MASK_WLDSS_DATA_IN_0 << BIT_SHIFT_WLDSS_DATA_IN_0)
+#define BIT_CLEAR_WLDSS_DATA_IN_0(x) ((x) & (~BITS_WLDSS_DATA_IN_0))
+#define BIT_GET_WLDSS_DATA_IN_0(x)                                             \
+	(((x) >> BIT_SHIFT_WLDSS_DATA_IN_0) & BIT_MASK_WLDSS_DATA_IN_0)
+#define BIT_SET_WLDSS_DATA_IN_0(x, v)                                          \
+	(BIT_CLEAR_WLDSS_DATA_IN_0(x) | BIT_WLDSS_DATA_IN_0(v))
+
+#define BIT_SHIFT_WLDSS_COUNT_OUT_0 0
+#define BIT_MASK_WLDSS_COUNT_OUT_0 0xfffff
+#define BIT_WLDSS_COUNT_OUT_0(x)                                               \
+	(((x) & BIT_MASK_WLDSS_COUNT_OUT_0) << BIT_SHIFT_WLDSS_COUNT_OUT_0)
+#define BITS_WLDSS_COUNT_OUT_0                                                 \
+	(BIT_MASK_WLDSS_COUNT_OUT_0 << BIT_SHIFT_WLDSS_COUNT_OUT_0)
+#define BIT_CLEAR_WLDSS_COUNT_OUT_0(x) ((x) & (~BITS_WLDSS_COUNT_OUT_0))
+#define BIT_GET_WLDSS_COUNT_OUT_0(x)                                           \
+	(((x) >> BIT_SHIFT_WLDSS_COUNT_OUT_0) & BIT_MASK_WLDSS_COUNT_OUT_0)
+#define BIT_SET_WLDSS_COUNT_OUT_0(x, v)                                        \
+	(BIT_CLEAR_WLDSS_COUNT_OUT_0(x) | BIT_WLDSS_COUNT_OUT_0(v))
+
+#define BIT_SHIFT_WLDSS_DATA_IN_1 0
+#define BIT_MASK_WLDSS_DATA_IN_1 0xfffff
+#define BIT_WLDSS_DATA_IN_1(x)                                                 \
+	(((x) & BIT_MASK_WLDSS_DATA_IN_1) << BIT_SHIFT_WLDSS_DATA_IN_1)
+#define BITS_WLDSS_DATA_IN_1                                                   \
+	(BIT_MASK_WLDSS_DATA_IN_1 << BIT_SHIFT_WLDSS_DATA_IN_1)
+#define BIT_CLEAR_WLDSS_DATA_IN_1(x) ((x) & (~BITS_WLDSS_DATA_IN_1))
+#define BIT_GET_WLDSS_DATA_IN_1(x)                                             \
+	(((x) >> BIT_SHIFT_WLDSS_DATA_IN_1) & BIT_MASK_WLDSS_DATA_IN_1)
+#define BIT_SET_WLDSS_DATA_IN_1(x, v)                                          \
+	(BIT_CLEAR_WLDSS_DATA_IN_1(x) | BIT_WLDSS_DATA_IN_1(v))
+
+#define BIT_SHIFT_WLDSS_COUNT_OUT_1 0
+#define BIT_MASK_WLDSS_COUNT_OUT_1 0xfffff
+#define BIT_WLDSS_COUNT_OUT_1(x)                                               \
+	(((x) & BIT_MASK_WLDSS_COUNT_OUT_1) << BIT_SHIFT_WLDSS_COUNT_OUT_1)
+#define BITS_WLDSS_COUNT_OUT_1                                                 \
+	(BIT_MASK_WLDSS_COUNT_OUT_1 << BIT_SHIFT_WLDSS_COUNT_OUT_1)
+#define BIT_CLEAR_WLDSS_COUNT_OUT_1(x) ((x) & (~BITS_WLDSS_COUNT_OUT_1))
+#define BIT_GET_WLDSS_COUNT_OUT_1(x)                                           \
+	(((x) >> BIT_SHIFT_WLDSS_COUNT_OUT_1) & BIT_MASK_WLDSS_COUNT_OUT_1)
+#define BIT_SET_WLDSS_COUNT_OUT_1(x, v)                                        \
+	(BIT_CLEAR_WLDSS_COUNT_OUT_1(x) | BIT_WLDSS_COUNT_OUT_1(v))
+
+#define BIT_SHIFT_WLDSS_DATA_IN_2 0
+#define BIT_MASK_WLDSS_DATA_IN_2 0xfffff
+#define BIT_WLDSS_DATA_IN_2(x)                                                 \
+	(((x) & BIT_MASK_WLDSS_DATA_IN_2) << BIT_SHIFT_WLDSS_DATA_IN_2)
+#define BITS_WLDSS_DATA_IN_2                                                   \
+	(BIT_MASK_WLDSS_DATA_IN_2 << BIT_SHIFT_WLDSS_DATA_IN_2)
+#define BIT_CLEAR_WLDSS_DATA_IN_2(x) ((x) & (~BITS_WLDSS_DATA_IN_2))
+#define BIT_GET_WLDSS_DATA_IN_2(x)                                             \
+	(((x) >> BIT_SHIFT_WLDSS_DATA_IN_2) & BIT_MASK_WLDSS_DATA_IN_2)
+#define BIT_SET_WLDSS_DATA_IN_2(x, v)                                          \
+	(BIT_CLEAR_WLDSS_DATA_IN_2(x) | BIT_WLDSS_DATA_IN_2(v))
+
+#define BIT_SHIFT_WLDSS_COUNT_OUT_2 0
+#define BIT_MASK_WLDSS_COUNT_OUT_2 0xfffff
+#define BIT_WLDSS_COUNT_OUT_2(x)                                               \
+	(((x) & BIT_MASK_WLDSS_COUNT_OUT_2) << BIT_SHIFT_WLDSS_COUNT_OUT_2)
+#define BITS_WLDSS_COUNT_OUT_2                                                 \
+	(BIT_MASK_WLDSS_COUNT_OUT_2 << BIT_SHIFT_WLDSS_COUNT_OUT_2)
+#define BIT_CLEAR_WLDSS_COUNT_OUT_2(x) ((x) & (~BITS_WLDSS_COUNT_OUT_2))
+#define BIT_GET_WLDSS_COUNT_OUT_2(x)                                           \
+	(((x) >> BIT_SHIFT_WLDSS_COUNT_OUT_2) & BIT_MASK_WLDSS_COUNT_OUT_2)
+#define BIT_SET_WLDSS_COUNT_OUT_2(x, v)                                        \
+	(BIT_CLEAR_WLDSS_COUNT_OUT_2(x) | BIT_WLDSS_COUNT_OUT_2(v))
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_SW_MDIO				(Offset 0x10C0) */
+
+#define BIT_MDO BIT(0)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT)
+
+/* 2 REG_SW_FLUSH				(Offset 0x10C4) */
+
+#define BIT_FLUSH_HOLDN_EN BIT(25)
+#define BIT_FLUSH_WR_EN BIT(24)
+#define BIT_SW_FLASH_CONTROL BIT(23)
+#define BIT_SW_FLASH_WEN_E BIT(19)
+#define BIT_SW_FLASH_HOLDN_E BIT(18)
+#define BIT_SW_FLASH_SO_E BIT(17)
+#define BIT_SW_FLASH_SI_E BIT(16)
+#define BIT_SW_FLASH_SK_O BIT(13)
+#define BIT_SW_FLASH_CEN_O BIT(12)
+#define BIT_SW_FLASH_WEN_O BIT(11)
+#define BIT_SW_FLASH_HOLDN_O BIT(10)
+#define BIT_SW_FLASH_SO_O BIT(9)
+#define BIT_SW_FLASH_SI_O BIT(8)
+#define BIT_SW_FLASH_WEN_I BIT(3)
+#define BIT_SW_FLASH_HOLDN_I BIT(2)
+#define BIT_SW_FLASH_SO_I BIT(1)
+#define BIT_SW_FLASH_SI_I BIT(0)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_HIMR_7				(Offset 0x10C8) */
+
+#define BIT_DATA_CPU_WDT_INT_MSK BIT(31)
+#define BIT_OFLD_TXDMA_ERR_MSK BIT(30)
+#define BIT_OFLD_TXDMA_FULL_MSK BIT(29)
+#define BIT_OFLD_RXDMA_OVR_MSK BIT(28)
+#define BIT_OFLD_RXDMA_ERR_MSK BIT(27)
+#define BIT_OFLD_RXDMA_DES_UA_MSK BIT(26)
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+/* 2 REG_DBG_GPIO_BMUX			(Offset 0x10C8) */
+
+#define BIT_SHIFT_WL_DSS_CLKEN_BACKDOOR 24
+#define BIT_MASK_WL_DSS_CLKEN_BACKDOOR 0x3
+#define BIT_WL_DSS_CLKEN_BACKDOOR(x)                                           \
+	(((x) & BIT_MASK_WL_DSS_CLKEN_BACKDOOR)                                \
+	 << BIT_SHIFT_WL_DSS_CLKEN_BACKDOOR)
+#define BITS_WL_DSS_CLKEN_BACKDOOR                                             \
+	(BIT_MASK_WL_DSS_CLKEN_BACKDOOR << BIT_SHIFT_WL_DSS_CLKEN_BACKDOOR)
+#define BIT_CLEAR_WL_DSS_CLKEN_BACKDOOR(x) ((x) & (~BITS_WL_DSS_CLKEN_BACKDOOR))
+#define BIT_GET_WL_DSS_CLKEN_BACKDOOR(x)                                       \
+	(((x) >> BIT_SHIFT_WL_DSS_CLKEN_BACKDOOR) &                            \
+	 BIT_MASK_WL_DSS_CLKEN_BACKDOOR)
+#define BIT_SET_WL_DSS_CLKEN_BACKDOOR(x, v)                                    \
+	(BIT_CLEAR_WL_DSS_CLKEN_BACKDOOR(x) | BIT_WL_DSS_CLKEN_BACKDOOR(v))
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_DBG_GPIO_BMUX			(Offset 0x10C8) */
+
+#define BIT_SHIFT_DBG_GPIO_BMUX_7 21
+#define BIT_MASK_DBG_GPIO_BMUX_7 0x7
+#define BIT_DBG_GPIO_BMUX_7(x)                                                 \
+	(((x) & BIT_MASK_DBG_GPIO_BMUX_7) << BIT_SHIFT_DBG_GPIO_BMUX_7)
+#define BITS_DBG_GPIO_BMUX_7                                                   \
+	(BIT_MASK_DBG_GPIO_BMUX_7 << BIT_SHIFT_DBG_GPIO_BMUX_7)
+#define BIT_CLEAR_DBG_GPIO_BMUX_7(x) ((x) & (~BITS_DBG_GPIO_BMUX_7))
+#define BIT_GET_DBG_GPIO_BMUX_7(x)                                             \
+	(((x) >> BIT_SHIFT_DBG_GPIO_BMUX_7) & BIT_MASK_DBG_GPIO_BMUX_7)
+#define BIT_SET_DBG_GPIO_BMUX_7(x, v)                                          \
+	(BIT_CLEAR_DBG_GPIO_BMUX_7(x) | BIT_DBG_GPIO_BMUX_7(v))
+
+#define BIT_SHIFT_DBG_GPIO_BMUX_6 18
+#define BIT_MASK_DBG_GPIO_BMUX_6 0x7
+#define BIT_DBG_GPIO_BMUX_6(x)                                                 \
+	(((x) & BIT_MASK_DBG_GPIO_BMUX_6) << BIT_SHIFT_DBG_GPIO_BMUX_6)
+#define BITS_DBG_GPIO_BMUX_6                                                   \
+	(BIT_MASK_DBG_GPIO_BMUX_6 << BIT_SHIFT_DBG_GPIO_BMUX_6)
+#define BIT_CLEAR_DBG_GPIO_BMUX_6(x) ((x) & (~BITS_DBG_GPIO_BMUX_6))
+#define BIT_GET_DBG_GPIO_BMUX_6(x)                                             \
+	(((x) >> BIT_SHIFT_DBG_GPIO_BMUX_6) & BIT_MASK_DBG_GPIO_BMUX_6)
+#define BIT_SET_DBG_GPIO_BMUX_6(x, v)                                          \
+	(BIT_CLEAR_DBG_GPIO_BMUX_6(x) | BIT_DBG_GPIO_BMUX_6(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_HIMR_7				(Offset 0x10C8) */
+
+#define BIT_TXDMAOK_CHANNEL_16_MSK BIT(16)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_DBG_GPIO_BMUX			(Offset 0x10C8) */
+
+#define BIT_SHIFT_DBG_GPIO_BMUX_5 15
+#define BIT_MASK_DBG_GPIO_BMUX_5 0x7
+#define BIT_DBG_GPIO_BMUX_5(x)                                                 \
+	(((x) & BIT_MASK_DBG_GPIO_BMUX_5) << BIT_SHIFT_DBG_GPIO_BMUX_5)
+#define BITS_DBG_GPIO_BMUX_5                                                   \
+	(BIT_MASK_DBG_GPIO_BMUX_5 << BIT_SHIFT_DBG_GPIO_BMUX_5)
+#define BIT_CLEAR_DBG_GPIO_BMUX_5(x) ((x) & (~BITS_DBG_GPIO_BMUX_5))
+#define BIT_GET_DBG_GPIO_BMUX_5(x)                                             \
+	(((x) >> BIT_SHIFT_DBG_GPIO_BMUX_5) & BIT_MASK_DBG_GPIO_BMUX_5)
+#define BIT_SET_DBG_GPIO_BMUX_5(x, v)                                          \
+	(BIT_CLEAR_DBG_GPIO_BMUX_5(x) | BIT_DBG_GPIO_BMUX_5(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_HIMR_7				(Offset 0x10C8) */
+
+#define BIT_TXDMAOK_CHANNEL_13_MSK BIT(13)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_DBG_GPIO_BMUX			(Offset 0x10C8) */
+
+#define BIT_SHIFT_DBG_GPIO_BMUX_4 12
+#define BIT_MASK_DBG_GPIO_BMUX_4 0x7
+#define BIT_DBG_GPIO_BMUX_4(x)                                                 \
+	(((x) & BIT_MASK_DBG_GPIO_BMUX_4) << BIT_SHIFT_DBG_GPIO_BMUX_4)
+#define BITS_DBG_GPIO_BMUX_4                                                   \
+	(BIT_MASK_DBG_GPIO_BMUX_4 << BIT_SHIFT_DBG_GPIO_BMUX_4)
+#define BIT_CLEAR_DBG_GPIO_BMUX_4(x) ((x) & (~BITS_DBG_GPIO_BMUX_4))
+#define BIT_GET_DBG_GPIO_BMUX_4(x)                                             \
+	(((x) >> BIT_SHIFT_DBG_GPIO_BMUX_4) & BIT_MASK_DBG_GPIO_BMUX_4)
+#define BIT_SET_DBG_GPIO_BMUX_4(x, v)                                          \
+	(BIT_CLEAR_DBG_GPIO_BMUX_4(x) | BIT_DBG_GPIO_BMUX_4(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_HIMR_7				(Offset 0x10C8) */
+
+#define BIT_TXDMAOK_CHANNEL_12_MSK BIT(12)
+#define BIT_TXDMAOK_CHANNEL_11_MSK BIT(11)
+#define BIT_TXDMAOK_CHANNEL_10_MSK BIT(10)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_DBG_GPIO_BMUX			(Offset 0x10C8) */
+
+#define BIT_SHIFT_DBG_GPIO_BMUX_3 9
+#define BIT_MASK_DBG_GPIO_BMUX_3 0x7
+#define BIT_DBG_GPIO_BMUX_3(x)                                                 \
+	(((x) & BIT_MASK_DBG_GPIO_BMUX_3) << BIT_SHIFT_DBG_GPIO_BMUX_3)
+#define BITS_DBG_GPIO_BMUX_3                                                   \
+	(BIT_MASK_DBG_GPIO_BMUX_3 << BIT_SHIFT_DBG_GPIO_BMUX_3)
+#define BIT_CLEAR_DBG_GPIO_BMUX_3(x) ((x) & (~BITS_DBG_GPIO_BMUX_3))
+#define BIT_GET_DBG_GPIO_BMUX_3(x)                                             \
+	(((x) >> BIT_SHIFT_DBG_GPIO_BMUX_3) & BIT_MASK_DBG_GPIO_BMUX_3)
+#define BIT_SET_DBG_GPIO_BMUX_3(x, v)                                          \
+	(BIT_CLEAR_DBG_GPIO_BMUX_3(x) | BIT_DBG_GPIO_BMUX_3(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_HIMR_7				(Offset 0x10C8) */
+
+#define BIT_TXDMAOK_CHANNEL_9_MSK BIT(9)
+#define BIT_TXDMAOK_CHANNEL_8_MSK BIT(8)
+#define BIT_TXDMAOK_CHANNEL_7_MSK BIT(7)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_DBG_GPIO_BMUX			(Offset 0x10C8) */
+
+#define BIT_SHIFT_DBG_GPIO_BMUX_2 6
+#define BIT_MASK_DBG_GPIO_BMUX_2 0x7
+#define BIT_DBG_GPIO_BMUX_2(x)                                                 \
+	(((x) & BIT_MASK_DBG_GPIO_BMUX_2) << BIT_SHIFT_DBG_GPIO_BMUX_2)
+#define BITS_DBG_GPIO_BMUX_2                                                   \
+	(BIT_MASK_DBG_GPIO_BMUX_2 << BIT_SHIFT_DBG_GPIO_BMUX_2)
+#define BIT_CLEAR_DBG_GPIO_BMUX_2(x) ((x) & (~BITS_DBG_GPIO_BMUX_2))
+#define BIT_GET_DBG_GPIO_BMUX_2(x)                                             \
+	(((x) >> BIT_SHIFT_DBG_GPIO_BMUX_2) & BIT_MASK_DBG_GPIO_BMUX_2)
+#define BIT_SET_DBG_GPIO_BMUX_2(x, v)                                          \
+	(BIT_CLEAR_DBG_GPIO_BMUX_2(x) | BIT_DBG_GPIO_BMUX_2(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_HIMR_7				(Offset 0x10C8) */
+
+#define BIT_TXDMAOK_CHANNEL_6_MSK BIT(6)
+#define BIT_TXDMAOK_CHANNEL_5_MSK BIT(5)
+#define BIT_TXDMAOK_CHANNEL_4_MSK BIT(4)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_DBG_GPIO_BMUX			(Offset 0x10C8) */
+
+#define BIT_SHIFT_DBG_GPIO_BMUX_1 3
+#define BIT_MASK_DBG_GPIO_BMUX_1 0x7
+#define BIT_DBG_GPIO_BMUX_1(x)                                                 \
+	(((x) & BIT_MASK_DBG_GPIO_BMUX_1) << BIT_SHIFT_DBG_GPIO_BMUX_1)
+#define BITS_DBG_GPIO_BMUX_1                                                   \
+	(BIT_MASK_DBG_GPIO_BMUX_1 << BIT_SHIFT_DBG_GPIO_BMUX_1)
+#define BIT_CLEAR_DBG_GPIO_BMUX_1(x) ((x) & (~BITS_DBG_GPIO_BMUX_1))
+#define BIT_GET_DBG_GPIO_BMUX_1(x)                                             \
+	(((x) >> BIT_SHIFT_DBG_GPIO_BMUX_1) & BIT_MASK_DBG_GPIO_BMUX_1)
+#define BIT_SET_DBG_GPIO_BMUX_1(x, v)                                          \
+	(BIT_CLEAR_DBG_GPIO_BMUX_1(x) | BIT_DBG_GPIO_BMUX_1(v))
+
+#define BIT_SHIFT_DBG_GPIO_BMUX_0 0
+#define BIT_MASK_DBG_GPIO_BMUX_0 0x7
+#define BIT_DBG_GPIO_BMUX_0(x)                                                 \
+	(((x) & BIT_MASK_DBG_GPIO_BMUX_0) << BIT_SHIFT_DBG_GPIO_BMUX_0)
+#define BITS_DBG_GPIO_BMUX_0                                                   \
+	(BIT_MASK_DBG_GPIO_BMUX_0 << BIT_SHIFT_DBG_GPIO_BMUX_0)
+#define BIT_CLEAR_DBG_GPIO_BMUX_0(x) ((x) & (~BITS_DBG_GPIO_BMUX_0))
+#define BIT_GET_DBG_GPIO_BMUX_0(x)                                             \
+	(((x) >> BIT_SHIFT_DBG_GPIO_BMUX_0) & BIT_MASK_DBG_GPIO_BMUX_0)
+#define BIT_SET_DBG_GPIO_BMUX_0(x, v)                                          \
+	(BIT_CLEAR_DBG_GPIO_BMUX_0(x) | BIT_DBG_GPIO_BMUX_0(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_HISR_7				(Offset 0x10CC) */
+
+#define BIT_DATA_CPU_WDT_INT BIT(31)
+#define BIT_OFLD_TXDMA_ERR BIT(30)
+#define BIT_OFLD_TXDMA_FULL BIT(29)
+#define BIT_OFLD_RXDMA_OVR BIT(28)
+#define BIT_OFLD_RXDMA_ERR BIT(27)
+#define BIT_OFLD_RXDMA_DES_UA BIT(26)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_FPGA_TAG				(Offset 0x10CC) */
+
+#define BIT_WL_DSS_SPEED_EN BIT(25)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_HISR_7				(Offset 0x10CC) */
+
+#define BIT_TXDMAOK_CHANNEL_16 BIT(16)
+#define BIT_TXDMAOK_CHANNEL_13 BIT(13)
+#define BIT_TXDMAOK_CHANNEL_12 BIT(12)
+#define BIT_TXDMAOK_CHANNEL_11 BIT(11)
+#define BIT_TXDMAOK_CHANNEL_10 BIT(10)
+#define BIT_TXDMAOK_CHANNEL_9 BIT(9)
+#define BIT_TXDMAOK_CHANNEL_8 BIT(8)
+#define BIT_TXDMAOK_CHANNEL_7 BIT(7)
+#define BIT_TXDMAOK_CHANNEL_6 BIT(6)
+#define BIT_TXDMAOK_CHANNEL_5 BIT(5)
+#define BIT_TXDMAOK_CHANNEL_4 BIT(4)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_FPGA_TAG				(Offset 0x10CC) */
+
+#define BIT_SHIFT_FPGA_TAG 0
+#define BIT_MASK_FPGA_TAG 0xffffffffL
+#define BIT_FPGA_TAG(x) (((x) & BIT_MASK_FPGA_TAG) << BIT_SHIFT_FPGA_TAG)
+#define BITS_FPGA_TAG (BIT_MASK_FPGA_TAG << BIT_SHIFT_FPGA_TAG)
+#define BIT_CLEAR_FPGA_TAG(x) ((x) & (~BITS_FPGA_TAG))
+#define BIT_GET_FPGA_TAG(x) (((x) >> BIT_SHIFT_FPGA_TAG) & BIT_MASK_FPGA_TAG)
+#define BIT_SET_FPGA_TAG(x, v) (BIT_CLEAR_FPGA_TAG(x) | BIT_FPGA_TAG(v))
+
+#define BIT_SHIFT_WL_DSS_COUNT_OUT 0
+#define BIT_MASK_WL_DSS_COUNT_OUT 0xfffff
+#define BIT_WL_DSS_COUNT_OUT(x)                                                \
+	(((x) & BIT_MASK_WL_DSS_COUNT_OUT) << BIT_SHIFT_WL_DSS_COUNT_OUT)
+#define BITS_WL_DSS_COUNT_OUT                                                  \
+	(BIT_MASK_WL_DSS_COUNT_OUT << BIT_SHIFT_WL_DSS_COUNT_OUT)
+#define BIT_CLEAR_WL_DSS_COUNT_OUT(x) ((x) & (~BITS_WL_DSS_COUNT_OUT))
+#define BIT_GET_WL_DSS_COUNT_OUT(x)                                            \
+	(((x) >> BIT_SHIFT_WL_DSS_COUNT_OUT) & BIT_MASK_WL_DSS_COUNT_OUT)
+#define BIT_SET_WL_DSS_COUNT_OUT(x, v)                                         \
+	(BIT_CLEAR_WL_DSS_COUNT_OUT(x) | BIT_WL_DSS_COUNT_OUT(v))
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+/* 2 REG_WL_DSS_CTRL0			(Offset 0x10D0) */
+
+#define BIT_SHIFT_WL_DSS_DBG0_5_0 26
+#define BIT_MASK_WL_DSS_DBG0_5_0 0x3f
+#define BIT_WL_DSS_DBG0_5_0(x)                                                 \
+	(((x) & BIT_MASK_WL_DSS_DBG0_5_0) << BIT_SHIFT_WL_DSS_DBG0_5_0)
+#define BITS_WL_DSS_DBG0_5_0                                                   \
+	(BIT_MASK_WL_DSS_DBG0_5_0 << BIT_SHIFT_WL_DSS_DBG0_5_0)
+#define BIT_CLEAR_WL_DSS_DBG0_5_0(x) ((x) & (~BITS_WL_DSS_DBG0_5_0))
+#define BIT_GET_WL_DSS_DBG0_5_0(x)                                             \
+	(((x) >> BIT_SHIFT_WL_DSS_DBG0_5_0) & BIT_MASK_WL_DSS_DBG0_5_0)
+#define BIT_SET_WL_DSS_DBG0_5_0(x, v)                                          \
+	(BIT_CLEAR_WL_DSS_DBG0_5_0(x) | BIT_WL_DSS_DBG0_5_0(v))
+
+#define BIT_SHIFT_WL_DSS_DATA_IN_V1 5
+#define BIT_MASK_WL_DSS_DATA_IN_V1 0xfffff
+#define BIT_WL_DSS_DATA_IN_V1(x)                                               \
+	(((x) & BIT_MASK_WL_DSS_DATA_IN_V1) << BIT_SHIFT_WL_DSS_DATA_IN_V1)
+#define BITS_WL_DSS_DATA_IN_V1                                                 \
+	(BIT_MASK_WL_DSS_DATA_IN_V1 << BIT_SHIFT_WL_DSS_DATA_IN_V1)
+#define BIT_CLEAR_WL_DSS_DATA_IN_V1(x) ((x) & (~BITS_WL_DSS_DATA_IN_V1))
+#define BIT_GET_WL_DSS_DATA_IN_V1(x)                                           \
+	(((x) >> BIT_SHIFT_WL_DSS_DATA_IN_V1) & BIT_MASK_WL_DSS_DATA_IN_V1)
+#define BIT_SET_WL_DSS_DATA_IN_V1(x, v)                                        \
+	(BIT_CLEAR_WL_DSS_DATA_IN_V1(x) | BIT_WL_DSS_DATA_IN_V1(v))
+
+#define BIT_WL_DSS_WIRE_SEL_V1 BIT(4)
+
+#define BIT_SHIFT_WL_DSS_RO_SEL_V1 1
+#define BIT_MASK_WL_DSS_RO_SEL_V1 0x7
+#define BIT_WL_DSS_RO_SEL_V1(x)                                                \
+	(((x) & BIT_MASK_WL_DSS_RO_SEL_V1) << BIT_SHIFT_WL_DSS_RO_SEL_V1)
+#define BITS_WL_DSS_RO_SEL_V1                                                  \
+	(BIT_MASK_WL_DSS_RO_SEL_V1 << BIT_SHIFT_WL_DSS_RO_SEL_V1)
+#define BIT_CLEAR_WL_DSS_RO_SEL_V1(x) ((x) & (~BITS_WL_DSS_RO_SEL_V1))
+#define BIT_GET_WL_DSS_RO_SEL_V1(x)                                            \
+	(((x) >> BIT_SHIFT_WL_DSS_RO_SEL_V1) & BIT_MASK_WL_DSS_RO_SEL_V1)
+#define BIT_SET_WL_DSS_RO_SEL_V1(x, v)                                         \
+	(BIT_CLEAR_WL_DSS_RO_SEL_V1(x) | BIT_WL_DSS_RO_SEL_V1(v))
+
+#define BIT_WL_DSS_RSTN_V1 BIT(0)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_H2C_PKT_READADDR			(Offset 0x10D0) */
+
+#define BIT_SHIFT_H2C_PKT_READADDR 0
+#define BIT_MASK_H2C_PKT_READADDR 0x3ffff
+#define BIT_H2C_PKT_READADDR(x)                                                \
+	(((x) & BIT_MASK_H2C_PKT_READADDR) << BIT_SHIFT_H2C_PKT_READADDR)
+#define BITS_H2C_PKT_READADDR                                                  \
+	(BIT_MASK_H2C_PKT_READADDR << BIT_SHIFT_H2C_PKT_READADDR)
+#define BIT_CLEAR_H2C_PKT_READADDR(x) ((x) & (~BITS_H2C_PKT_READADDR))
+#define BIT_GET_H2C_PKT_READADDR(x)                                            \
+	(((x) >> BIT_SHIFT_H2C_PKT_READADDR) & BIT_MASK_H2C_PKT_READADDR)
+#define BIT_SET_H2C_PKT_READADDR(x, v)                                         \
+	(BIT_CLEAR_H2C_PKT_READADDR(x) | BIT_H2C_PKT_READADDR(v))
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+/* 2 REG_WL_DSS_STATUS0			(Offset 0x10D4) */
+
+#define BIT_SHIFT_WL_DSS_DBG0_15_6 22
+#define BIT_MASK_WL_DSS_DBG0_15_6 0x3ff
+#define BIT_WL_DSS_DBG0_15_6(x)                                                \
+	(((x) & BIT_MASK_WL_DSS_DBG0_15_6) << BIT_SHIFT_WL_DSS_DBG0_15_6)
+#define BITS_WL_DSS_DBG0_15_6                                                  \
+	(BIT_MASK_WL_DSS_DBG0_15_6 << BIT_SHIFT_WL_DSS_DBG0_15_6)
+#define BIT_CLEAR_WL_DSS_DBG0_15_6(x) ((x) & (~BITS_WL_DSS_DBG0_15_6))
+#define BIT_GET_WL_DSS_DBG0_15_6(x)                                            \
+	(((x) >> BIT_SHIFT_WL_DSS_DBG0_15_6) & BIT_MASK_WL_DSS_DBG0_15_6)
+#define BIT_SET_WL_DSS_DBG0_15_6(x, v)                                         \
+	(BIT_CLEAR_WL_DSS_DBG0_15_6(x) | BIT_WL_DSS_DBG0_15_6(v))
+
+#define BIT_WL_DSS_WSORT_GO_V1 BIT(21)
+#define BIT_WL_DSS_READY_V1 BIT(20)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_H2C_PKT_WRITEADDR			(Offset 0x10D4) */
+
+#define BIT_SHIFT_H2C_PKT_WRITEADDR 0
+#define BIT_MASK_H2C_PKT_WRITEADDR 0x3ffff
+#define BIT_H2C_PKT_WRITEADDR(x)                                               \
+	(((x) & BIT_MASK_H2C_PKT_WRITEADDR) << BIT_SHIFT_H2C_PKT_WRITEADDR)
+#define BITS_H2C_PKT_WRITEADDR                                                 \
+	(BIT_MASK_H2C_PKT_WRITEADDR << BIT_SHIFT_H2C_PKT_WRITEADDR)
+#define BIT_CLEAR_H2C_PKT_WRITEADDR(x) ((x) & (~BITS_H2C_PKT_WRITEADDR))
+#define BIT_GET_H2C_PKT_WRITEADDR(x)                                           \
+	(((x) >> BIT_SHIFT_H2C_PKT_WRITEADDR) & BIT_MASK_H2C_PKT_WRITEADDR)
+#define BIT_SET_H2C_PKT_WRITEADDR(x, v)                                        \
+	(BIT_CLEAR_H2C_PKT_WRITEADDR(x) | BIT_H2C_PKT_WRITEADDR(v))
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+/* 2 REG_WL_DSS_CTRL1			(Offset 0x10D8) */
+
+#define BIT_SHIFT_WL_DSS_DBG1_5_0 26
+#define BIT_MASK_WL_DSS_DBG1_5_0 0x3f
+#define BIT_WL_DSS_DBG1_5_0(x)                                                 \
+	(((x) & BIT_MASK_WL_DSS_DBG1_5_0) << BIT_SHIFT_WL_DSS_DBG1_5_0)
+#define BITS_WL_DSS_DBG1_5_0                                                   \
+	(BIT_MASK_WL_DSS_DBG1_5_0 << BIT_SHIFT_WL_DSS_DBG1_5_0)
+#define BIT_CLEAR_WL_DSS_DBG1_5_0(x) ((x) & (~BITS_WL_DSS_DBG1_5_0))
+#define BIT_GET_WL_DSS_DBG1_5_0(x)                                             \
+	(((x) >> BIT_SHIFT_WL_DSS_DBG1_5_0) & BIT_MASK_WL_DSS_DBG1_5_0)
+#define BIT_SET_WL_DSS_DBG1_5_0(x, v)                                          \
+	(BIT_CLEAR_WL_DSS_DBG1_5_0(x) | BIT_WL_DSS_DBG1_5_0(v))
+
+#define BIT_WL_DSS_SPEED_EN1 BIT(25)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT)
+
+/* 2 REG_WL_DSS_CTRL1			(Offset 0x10D8) */
+
+#define BIT_WL_DSS_WIRE_SEL BIT(24)
+
+#define BIT_SHIFT_WL_DSS_RO_SEL 20
+#define BIT_MASK_WL_DSS_RO_SEL 0x7
+#define BIT_WL_DSS_RO_SEL(x)                                                   \
+	(((x) & BIT_MASK_WL_DSS_RO_SEL) << BIT_SHIFT_WL_DSS_RO_SEL)
+#define BITS_WL_DSS_RO_SEL (BIT_MASK_WL_DSS_RO_SEL << BIT_SHIFT_WL_DSS_RO_SEL)
+#define BIT_CLEAR_WL_DSS_RO_SEL(x) ((x) & (~BITS_WL_DSS_RO_SEL))
+#define BIT_GET_WL_DSS_RO_SEL(x)                                               \
+	(((x) >> BIT_SHIFT_WL_DSS_RO_SEL) & BIT_MASK_WL_DSS_RO_SEL)
+#define BIT_SET_WL_DSS_RO_SEL(x, v)                                            \
+	(BIT_CLEAR_WL_DSS_RO_SEL(x) | BIT_WL_DSS_RO_SEL(v))
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_MEM_PWR_CRTL			(Offset 0x10D8) */
+
+#define BIT_MEM_BB_SD BIT(17)
+#define BIT_MEM_BB_DS BIT(16)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_MEM_PWR_CRTL			(Offset 0x10D8) */
+
+#define BIT_MEM_DENG_LS BIT(13)
+#define BIT_MEM_DENG_DS BIT(12)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_MEM_PWR_CRTL			(Offset 0x10D8) */
+
+#define BIT_MEM_BT_DS BIT(10)
+#define BIT_MEM_SDIO_LS BIT(9)
+#define BIT_MEM_SDIO_DS BIT(8)
+#define BIT_MEM_USB_LS BIT(7)
+#define BIT_MEM_USB_DS BIT(6)
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+/* 2 REG_WL_DSS_CTRL1			(Offset 0x10D8) */
+
+#define BIT_SHIFT_WL_DSS_DATA_IN1 5
+#define BIT_MASK_WL_DSS_DATA_IN1 0xfffff
+#define BIT_WL_DSS_DATA_IN1(x)                                                 \
+	(((x) & BIT_MASK_WL_DSS_DATA_IN1) << BIT_SHIFT_WL_DSS_DATA_IN1)
+#define BITS_WL_DSS_DATA_IN1                                                   \
+	(BIT_MASK_WL_DSS_DATA_IN1 << BIT_SHIFT_WL_DSS_DATA_IN1)
+#define BIT_CLEAR_WL_DSS_DATA_IN1(x) ((x) & (~BITS_WL_DSS_DATA_IN1))
+#define BIT_GET_WL_DSS_DATA_IN1(x)                                             \
+	(((x) >> BIT_SHIFT_WL_DSS_DATA_IN1) & BIT_MASK_WL_DSS_DATA_IN1)
+#define BIT_SET_WL_DSS_DATA_IN1(x, v)                                          \
+	(BIT_CLEAR_WL_DSS_DATA_IN1(x) | BIT_WL_DSS_DATA_IN1(v))
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_MEM_PWR_CRTL			(Offset 0x10D8) */
+
+#define BIT_MEM_PCI_LS BIT(5)
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+/* 2 REG_WL_DSS_CTRL1			(Offset 0x10D8) */
+
+#define BIT_WL_DSS_WIRE_SEL1 BIT(4)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_MEM_PWR_CRTL			(Offset 0x10D8) */
+
+#define BIT_MEM_PCI_DS BIT(4)
+#define BIT_MEM_WLMAC_LS BIT(3)
+#define BIT_MEM_WLMAC_DS BIT(2)
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+/* 2 REG_WL_DSS_CTRL1			(Offset 0x10D8) */
+
+#define BIT_SHIFT_WL_DSS_RO_SEL1 1
+#define BIT_MASK_WL_DSS_RO_SEL1 0x7
+#define BIT_WL_DSS_RO_SEL1(x)                                                  \
+	(((x) & BIT_MASK_WL_DSS_RO_SEL1) << BIT_SHIFT_WL_DSS_RO_SEL1)
+#define BITS_WL_DSS_RO_SEL1                                                    \
+	(BIT_MASK_WL_DSS_RO_SEL1 << BIT_SHIFT_WL_DSS_RO_SEL1)
+#define BIT_CLEAR_WL_DSS_RO_SEL1(x) ((x) & (~BITS_WL_DSS_RO_SEL1))
+#define BIT_GET_WL_DSS_RO_SEL1(x)                                              \
+	(((x) >> BIT_SHIFT_WL_DSS_RO_SEL1) & BIT_MASK_WL_DSS_RO_SEL1)
+#define BIT_SET_WL_DSS_RO_SEL1(x, v)                                           \
+	(BIT_CLEAR_WL_DSS_RO_SEL1(x) | BIT_WL_DSS_RO_SEL1(v))
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_MEM_PWR_CRTL			(Offset 0x10D8) */
+
+#define BIT_MEM_WLMCU_LS BIT(1)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT)
+
+/* 2 REG_WL_DSS_CTRL1			(Offset 0x10D8) */
+
+#define BIT_SHIFT_WL_DSS_DATA_IN 0
+#define BIT_MASK_WL_DSS_DATA_IN 0xfffff
+#define BIT_WL_DSS_DATA_IN(x)                                                  \
+	(((x) & BIT_MASK_WL_DSS_DATA_IN) << BIT_SHIFT_WL_DSS_DATA_IN)
+#define BITS_WL_DSS_DATA_IN                                                    \
+	(BIT_MASK_WL_DSS_DATA_IN << BIT_SHIFT_WL_DSS_DATA_IN)
+#define BIT_CLEAR_WL_DSS_DATA_IN(x) ((x) & (~BITS_WL_DSS_DATA_IN))
+#define BIT_GET_WL_DSS_DATA_IN(x)                                              \
+	(((x) >> BIT_SHIFT_WL_DSS_DATA_IN) & BIT_MASK_WL_DSS_DATA_IN)
+#define BIT_SET_WL_DSS_DATA_IN(x, v)                                           \
+	(BIT_CLEAR_WL_DSS_DATA_IN(x) | BIT_WL_DSS_DATA_IN(v))
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+/* 2 REG_WL_DSS_CTRL1			(Offset 0x10D8) */
+
+#define BIT_WL_DSS_RSTN1 BIT(0)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_MEM_PWR_CRTL			(Offset 0x10D8) */
+
+#define BIT_MEM_WLMCU_DS BIT(0)
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+/* 2 REG_WL_DSS_STATUS1			(Offset 0x10DC) */
+
+#define BIT_SHIFT_WL_DSS_DBG1_15_6 22
+#define BIT_MASK_WL_DSS_DBG1_15_6 0x3ff
+#define BIT_WL_DSS_DBG1_15_6(x)                                                \
+	(((x) & BIT_MASK_WL_DSS_DBG1_15_6) << BIT_SHIFT_WL_DSS_DBG1_15_6)
+#define BITS_WL_DSS_DBG1_15_6                                                  \
+	(BIT_MASK_WL_DSS_DBG1_15_6 << BIT_SHIFT_WL_DSS_DBG1_15_6)
+#define BIT_CLEAR_WL_DSS_DBG1_15_6(x) ((x) & (~BITS_WL_DSS_DBG1_15_6))
+#define BIT_GET_WL_DSS_DBG1_15_6(x)                                            \
+	(((x) >> BIT_SHIFT_WL_DSS_DBG1_15_6) & BIT_MASK_WL_DSS_DBG1_15_6)
+#define BIT_SET_WL_DSS_DBG1_15_6(x, v)                                         \
+	(BIT_CLEAR_WL_DSS_DBG1_15_6(x) | BIT_WL_DSS_DBG1_15_6(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT)
+
+/* 2 REG_WL_DSS_STATUS1			(Offset 0x10DC) */
+
+#define BIT_WL_DSS_READY BIT(21)
+#define BIT_WL_DSS_WSORT_GO BIT(20)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_FW_DRV_HANDSHAKE			(Offset 0x10DC) */
+
+#define BIT_SHIFT_FW_DRV_HANDSHAKE 0
+#define BIT_MASK_FW_DRV_HANDSHAKE 0xffffffffL
+#define BIT_FW_DRV_HANDSHAKE(x)                                                \
+	(((x) & BIT_MASK_FW_DRV_HANDSHAKE) << BIT_SHIFT_FW_DRV_HANDSHAKE)
+#define BITS_FW_DRV_HANDSHAKE                                                  \
+	(BIT_MASK_FW_DRV_HANDSHAKE << BIT_SHIFT_FW_DRV_HANDSHAKE)
+#define BIT_CLEAR_FW_DRV_HANDSHAKE(x) ((x) & (~BITS_FW_DRV_HANDSHAKE))
+#define BIT_GET_FW_DRV_HANDSHAKE(x)                                            \
+	(((x) >> BIT_SHIFT_FW_DRV_HANDSHAKE) & BIT_MASK_FW_DRV_HANDSHAKE)
+#define BIT_SET_FW_DRV_HANDSHAKE(x, v)                                         \
+	(BIT_CLEAR_FW_DRV_HANDSHAKE(x) | BIT_FW_DRV_HANDSHAKE(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822B_SUPPORT)
+
+/* 2 REG_FW_DBG0				(Offset 0x10E0) */
+
+#define BIT_SHIFT_FW_DBG0 0
+#define BIT_MASK_FW_DBG0 0xffffffffL
+#define BIT_FW_DBG0(x) (((x) & BIT_MASK_FW_DBG0) << BIT_SHIFT_FW_DBG0)
+#define BITS_FW_DBG0 (BIT_MASK_FW_DBG0 << BIT_SHIFT_FW_DBG0)
+#define BIT_CLEAR_FW_DBG0(x) ((x) & (~BITS_FW_DBG0))
+#define BIT_GET_FW_DBG0(x) (((x) >> BIT_SHIFT_FW_DBG0) & BIT_MASK_FW_DBG0)
+#define BIT_SET_FW_DBG0(x, v) (BIT_CLEAR_FW_DBG0(x) | BIT_FW_DBG0(v))
+
+/* 2 REG_FW_DBG1				(Offset 0x10E4) */
+
+#define BIT_SHIFT_FW_DBG1 0
+#define BIT_MASK_FW_DBG1 0xffffffffL
+#define BIT_FW_DBG1(x) (((x) & BIT_MASK_FW_DBG1) << BIT_SHIFT_FW_DBG1)
+#define BITS_FW_DBG1 (BIT_MASK_FW_DBG1 << BIT_SHIFT_FW_DBG1)
+#define BIT_CLEAR_FW_DBG1(x) ((x) & (~BITS_FW_DBG1))
+#define BIT_GET_FW_DBG1(x) (((x) >> BIT_SHIFT_FW_DBG1) & BIT_MASK_FW_DBG1)
+#define BIT_SET_FW_DBG1(x, v) (BIT_CLEAR_FW_DBG1(x) | BIT_FW_DBG1(v))
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8822B_SUPPORT)
+
+/* 2 REG_FW_DBG2				(Offset 0x10E8) */
+
+#define BIT_SHIFT_FW_DBG2 0
+#define BIT_MASK_FW_DBG2 0xffffffffL
+#define BIT_FW_DBG2(x) (((x) & BIT_MASK_FW_DBG2) << BIT_SHIFT_FW_DBG2)
+#define BITS_FW_DBG2 (BIT_MASK_FW_DBG2 << BIT_SHIFT_FW_DBG2)
+#define BIT_CLEAR_FW_DBG2(x) ((x) & (~BITS_FW_DBG2))
+#define BIT_GET_FW_DBG2(x) (((x) >> BIT_SHIFT_FW_DBG2) & BIT_MASK_FW_DBG2)
+#define BIT_SET_FW_DBG2(x, v) (BIT_CLEAR_FW_DBG2(x) | BIT_FW_DBG2(v))
+
+/* 2 REG_FW_DBG3				(Offset 0x10EC) */
+
+#define BIT_SHIFT_FW_DBG3 0
+#define BIT_MASK_FW_DBG3 0xffffffffL
+#define BIT_FW_DBG3(x) (((x) & BIT_MASK_FW_DBG3) << BIT_SHIFT_FW_DBG3)
+#define BITS_FW_DBG3 (BIT_MASK_FW_DBG3 << BIT_SHIFT_FW_DBG3)
+#define BIT_CLEAR_FW_DBG3(x) ((x) & (~BITS_FW_DBG3))
+#define BIT_GET_FW_DBG3(x) (((x) >> BIT_SHIFT_FW_DBG3) & BIT_MASK_FW_DBG3)
+#define BIT_SET_FW_DBG3(x, v) (BIT_CLEAR_FW_DBG3(x) | BIT_FW_DBG3(v))
+
+/* 2 REG_FW_DBG4				(Offset 0x10F0) */
+
+#define BIT_SHIFT_FW_DBG4 0
+#define BIT_MASK_FW_DBG4 0xffffffffL
+#define BIT_FW_DBG4(x) (((x) & BIT_MASK_FW_DBG4) << BIT_SHIFT_FW_DBG4)
+#define BITS_FW_DBG4 (BIT_MASK_FW_DBG4 << BIT_SHIFT_FW_DBG4)
+#define BIT_CLEAR_FW_DBG4(x) ((x) & (~BITS_FW_DBG4))
+#define BIT_GET_FW_DBG4(x) (((x) >> BIT_SHIFT_FW_DBG4) & BIT_MASK_FW_DBG4)
+#define BIT_SET_FW_DBG4(x, v) (BIT_CLEAR_FW_DBG4(x) | BIT_FW_DBG4(v))
+
+/* 2 REG_FW_DBG5				(Offset 0x10F4) */
+
+#define BIT_SHIFT_FW_DBG5 0
+#define BIT_MASK_FW_DBG5 0xffffffffL
+#define BIT_FW_DBG5(x) (((x) & BIT_MASK_FW_DBG5) << BIT_SHIFT_FW_DBG5)
+#define BITS_FW_DBG5 (BIT_MASK_FW_DBG5 << BIT_SHIFT_FW_DBG5)
+#define BIT_CLEAR_FW_DBG5(x) ((x) & (~BITS_FW_DBG5))
+#define BIT_GET_FW_DBG5(x) (((x) >> BIT_SHIFT_FW_DBG5) & BIT_MASK_FW_DBG5)
+#define BIT_SET_FW_DBG5(x, v) (BIT_CLEAR_FW_DBG5(x) | BIT_FW_DBG5(v))
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FW_DBG6				(Offset 0x10F8) */
+
+#define BIT_SHIFT_FW_DBG6 0
+#define BIT_MASK_FW_DBG6 0xffffffffL
+#define BIT_FW_DBG6(x) (((x) & BIT_MASK_FW_DBG6) << BIT_SHIFT_FW_DBG6)
+#define BITS_FW_DBG6 (BIT_MASK_FW_DBG6 << BIT_SHIFT_FW_DBG6)
+#define BIT_CLEAR_FW_DBG6(x) ((x) & (~BITS_FW_DBG6))
+#define BIT_GET_FW_DBG6(x) (((x) >> BIT_SHIFT_FW_DBG6) & BIT_MASK_FW_DBG6)
+#define BIT_SET_FW_DBG6(x, v) (BIT_CLEAR_FW_DBG6(x) | BIT_FW_DBG6(v))
+
+/* 2 REG_FW_DBG7				(Offset 0x10FC) */
+
+#define BIT_SHIFT_FW_DBG7 0
+#define BIT_MASK_FW_DBG7 0xffffffffL
+#define BIT_FW_DBG7(x) (((x) & BIT_MASK_FW_DBG7) << BIT_SHIFT_FW_DBG7)
+#define BITS_FW_DBG7 (BIT_MASK_FW_DBG7 << BIT_SHIFT_FW_DBG7)
+#define BIT_CLEAR_FW_DBG7(x) ((x) & (~BITS_FW_DBG7))
+#define BIT_GET_FW_DBG7(x) (((x) >> BIT_SHIFT_FW_DBG7) & BIT_MASK_FW_DBG7)
+#define BIT_SET_FW_DBG7(x, v) (BIT_CLEAR_FW_DBG7(x) | BIT_FW_DBG7(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_CR_EXT				(Offset 0x1100) */
+
+#define BIT_SHIFT_PHY_REQ_DELAY 24
+#define BIT_MASK_PHY_REQ_DELAY 0xf
+#define BIT_PHY_REQ_DELAY(x)                                                   \
+	(((x) & BIT_MASK_PHY_REQ_DELAY) << BIT_SHIFT_PHY_REQ_DELAY)
+#define BITS_PHY_REQ_DELAY (BIT_MASK_PHY_REQ_DELAY << BIT_SHIFT_PHY_REQ_DELAY)
+#define BIT_CLEAR_PHY_REQ_DELAY(x) ((x) & (~BITS_PHY_REQ_DELAY))
+#define BIT_GET_PHY_REQ_DELAY(x)                                               \
+	(((x) >> BIT_SHIFT_PHY_REQ_DELAY) & BIT_MASK_PHY_REQ_DELAY)
+#define BIT_SET_PHY_REQ_DELAY(x, v)                                            \
+	(BIT_CLEAR_PHY_REQ_DELAY(x) | BIT_PHY_REQ_DELAY(v))
+
+#define BIT_SPD_DOWN BIT(16)
+
+#define BIT_SHIFT_NETYPE4 4
+#define BIT_MASK_NETYPE4 0x3
+#define BIT_NETYPE4(x) (((x) & BIT_MASK_NETYPE4) << BIT_SHIFT_NETYPE4)
+#define BITS_NETYPE4 (BIT_MASK_NETYPE4 << BIT_SHIFT_NETYPE4)
+#define BIT_CLEAR_NETYPE4(x) ((x) & (~BITS_NETYPE4))
+#define BIT_GET_NETYPE4(x) (((x) >> BIT_SHIFT_NETYPE4) & BIT_MASK_NETYPE4)
+#define BIT_SET_NETYPE4(x, v) (BIT_CLEAR_NETYPE4(x) | BIT_NETYPE4(v))
+
+#define BIT_SHIFT_NETYPE3 2
+#define BIT_MASK_NETYPE3 0x3
+#define BIT_NETYPE3(x) (((x) & BIT_MASK_NETYPE3) << BIT_SHIFT_NETYPE3)
+#define BITS_NETYPE3 (BIT_MASK_NETYPE3 << BIT_SHIFT_NETYPE3)
+#define BIT_CLEAR_NETYPE3(x) ((x) & (~BITS_NETYPE3))
+#define BIT_GET_NETYPE3(x) (((x) >> BIT_SHIFT_NETYPE3) & BIT_MASK_NETYPE3)
+#define BIT_SET_NETYPE3(x, v) (BIT_CLEAR_NETYPE3(x) | BIT_NETYPE3(v))
+
+#define BIT_SHIFT_NETYPE2 0
+#define BIT_MASK_NETYPE2 0x3
+#define BIT_NETYPE2(x) (((x) & BIT_MASK_NETYPE2) << BIT_SHIFT_NETYPE2)
+#define BITS_NETYPE2 (BIT_MASK_NETYPE2 << BIT_SHIFT_NETYPE2)
+#define BIT_CLEAR_NETYPE2(x) ((x) & (~BITS_NETYPE2))
+#define BIT_GET_NETYPE2(x) (((x) >> BIT_SHIFT_NETYPE2) & BIT_MASK_NETYPE2)
+#define BIT_SET_NETYPE2(x, v) (BIT_CLEAR_NETYPE2(x) | BIT_NETYPE2(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_TC9_CTRL				(Offset 0x1104) */
+
+#define BIT_TC9INT_EN BIT(26)
+#define BIT_TC9MODE BIT(25)
+#define BIT_TC9EN BIT(24)
+
+#define BIT_SHIFT_TC9DATA 0
+#define BIT_MASK_TC9DATA 0xffffff
+#define BIT_TC9DATA(x) (((x) & BIT_MASK_TC9DATA) << BIT_SHIFT_TC9DATA)
+#define BITS_TC9DATA (BIT_MASK_TC9DATA << BIT_SHIFT_TC9DATA)
+#define BIT_CLEAR_TC9DATA(x) ((x) & (~BITS_TC9DATA))
+#define BIT_GET_TC9DATA(x) (((x) >> BIT_SHIFT_TC9DATA) & BIT_MASK_TC9DATA)
+#define BIT_SET_TC9DATA(x, v) (BIT_CLEAR_TC9DATA(x) | BIT_TC9DATA(v))
+
+/* 2 REG_TC10_CTRL				(Offset 0x1108) */
+
+#define BIT_TC10INT_EN BIT(26)
+#define BIT_TC10MODE BIT(25)
+#define BIT_TC10EN BIT(24)
+
+#define BIT_SHIFT_TC10DATA 0
+#define BIT_MASK_TC10DATA 0xffffff
+#define BIT_TC10DATA(x) (((x) & BIT_MASK_TC10DATA) << BIT_SHIFT_TC10DATA)
+#define BITS_TC10DATA (BIT_MASK_TC10DATA << BIT_SHIFT_TC10DATA)
+#define BIT_CLEAR_TC10DATA(x) ((x) & (~BITS_TC10DATA))
+#define BIT_GET_TC10DATA(x) (((x) >> BIT_SHIFT_TC10DATA) & BIT_MASK_TC10DATA)
+#define BIT_SET_TC10DATA(x, v) (BIT_CLEAR_TC10DATA(x) | BIT_TC10DATA(v))
+
+/* 2 REG_TC11_CTRL				(Offset 0x110C) */
+
+#define BIT_TC11INT_EN BIT(26)
+#define BIT_TC11MODE BIT(25)
+#define BIT_TC11EN BIT(24)
+
+#define BIT_SHIFT_TC11DATA 0
+#define BIT_MASK_TC11DATA 0xffffff
+#define BIT_TC11DATA(x) (((x) & BIT_MASK_TC11DATA) << BIT_SHIFT_TC11DATA)
+#define BITS_TC11DATA (BIT_MASK_TC11DATA << BIT_SHIFT_TC11DATA)
+#define BIT_CLEAR_TC11DATA(x) ((x) & (~BITS_TC11DATA))
+#define BIT_GET_TC11DATA(x) (((x) >> BIT_SHIFT_TC11DATA) & BIT_MASK_TC11DATA)
+#define BIT_SET_TC11DATA(x, v) (BIT_CLEAR_TC11DATA(x) | BIT_TC11DATA(v))
+
+/* 2 REG_TC12_CTRL				(Offset 0x1110) */
+
+#define BIT_TC12INT_EN BIT(26)
+#define BIT_TC12MODE BIT(25)
+#define BIT_TC12EN BIT(24)
+#define BIT_P2P_PWROFF_NOA2_ERLY_INT BIT(22)
+#define BIT_P2P_PWROFF_NOA1_ERLY_INT BIT(21)
+#define BIT_P2P_PWROFF_NOA0_ERLY_INT BIT(20)
+
+#define BIT_SHIFT_TC12DATA 0
+#define BIT_MASK_TC12DATA 0xffffff
+#define BIT_TC12DATA(x) (((x) & BIT_MASK_TC12DATA) << BIT_SHIFT_TC12DATA)
+#define BITS_TC12DATA (BIT_MASK_TC12DATA << BIT_SHIFT_TC12DATA)
+#define BIT_CLEAR_TC12DATA(x) ((x) & (~BITS_TC12DATA))
+#define BIT_GET_TC12DATA(x) (((x) >> BIT_SHIFT_TC12DATA) & BIT_MASK_TC12DATA)
+#define BIT_SET_TC12DATA(x, v) (BIT_CLEAR_TC12DATA(x) | BIT_TC12DATA(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_FWFF				(Offset 0x1114) */
+
+#define BIT_SHIFT_PKTNUM_TH 24
+#define BIT_MASK_PKTNUM_TH 0xff
+#define BIT_PKTNUM_TH(x) (((x) & BIT_MASK_PKTNUM_TH) << BIT_SHIFT_PKTNUM_TH)
+#define BITS_PKTNUM_TH (BIT_MASK_PKTNUM_TH << BIT_SHIFT_PKTNUM_TH)
+#define BIT_CLEAR_PKTNUM_TH(x) ((x) & (~BITS_PKTNUM_TH))
+#define BIT_GET_PKTNUM_TH(x) (((x) >> BIT_SHIFT_PKTNUM_TH) & BIT_MASK_PKTNUM_TH)
+#define BIT_SET_PKTNUM_TH(x, v) (BIT_CLEAR_PKTNUM_TH(x) | BIT_PKTNUM_TH(v))
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FWFF				(Offset 0x1114) */
+
+#define BIT_SHIFT_PKTNUM_TH_V1 24
+#define BIT_MASK_PKTNUM_TH_V1 0xff
+#define BIT_PKTNUM_TH_V1(x)                                                    \
+	(((x) & BIT_MASK_PKTNUM_TH_V1) << BIT_SHIFT_PKTNUM_TH_V1)
+#define BITS_PKTNUM_TH_V1 (BIT_MASK_PKTNUM_TH_V1 << BIT_SHIFT_PKTNUM_TH_V1)
+#define BIT_CLEAR_PKTNUM_TH_V1(x) ((x) & (~BITS_PKTNUM_TH_V1))
+#define BIT_GET_PKTNUM_TH_V1(x)                                                \
+	(((x) >> BIT_SHIFT_PKTNUM_TH_V1) & BIT_MASK_PKTNUM_TH_V1)
+#define BIT_SET_PKTNUM_TH_V1(x, v)                                             \
+	(BIT_CLEAR_PKTNUM_TH_V1(x) | BIT_PKTNUM_TH_V1(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FWFF				(Offset 0x1114) */
+
+#define BIT_SHIFT_TIMER_TH 16
+#define BIT_MASK_TIMER_TH 0xff
+#define BIT_TIMER_TH(x) (((x) & BIT_MASK_TIMER_TH) << BIT_SHIFT_TIMER_TH)
+#define BITS_TIMER_TH (BIT_MASK_TIMER_TH << BIT_SHIFT_TIMER_TH)
+#define BIT_CLEAR_TIMER_TH(x) ((x) & (~BITS_TIMER_TH))
+#define BIT_GET_TIMER_TH(x) (((x) >> BIT_SHIFT_TIMER_TH) & BIT_MASK_TIMER_TH)
+#define BIT_SET_TIMER_TH(x, v) (BIT_CLEAR_TIMER_TH(x) | BIT_TIMER_TH(v))
+
+#define BIT_SHIFT_RXPKT1ENADDR 0
+#define BIT_MASK_RXPKT1ENADDR 0xffff
+#define BIT_RXPKT1ENADDR(x)                                                    \
+	(((x) & BIT_MASK_RXPKT1ENADDR) << BIT_SHIFT_RXPKT1ENADDR)
+#define BITS_RXPKT1ENADDR (BIT_MASK_RXPKT1ENADDR << BIT_SHIFT_RXPKT1ENADDR)
+#define BIT_CLEAR_RXPKT1ENADDR(x) ((x) & (~BITS_RXPKT1ENADDR))
+#define BIT_GET_RXPKT1ENADDR(x)                                                \
+	(((x) >> BIT_SHIFT_RXPKT1ENADDR) & BIT_MASK_RXPKT1ENADDR)
+#define BIT_SET_RXPKT1ENADDR(x, v)                                             \
+	(BIT_CLEAR_RXPKT1ENADDR(x) | BIT_RXPKT1ENADDR(v))
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FE2IMR				(Offset 0x1120) */
+
+#define BIT__FE4ISR__IND_MSK BIT(29)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FE2IMR				(Offset 0x1120) */
+
+#define BIT_FS_TXSC_DESC_DONE_INT_EN BIT(28)
+#define BIT_FS_TXSC_BKDONE_INT_EN BIT(27)
+#define BIT_FS_TXSC_BEDONE_INT_EN BIT(26)
+#define BIT_FS_TXSC_VIDONE_INT_EN BIT(25)
+#define BIT_FS_TXSC_VODONE_INT_EN BIT(24)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FE2IMR				(Offset 0x1120) */
+
+#define BIT_FS_ATIM_MB7_INT_EN BIT(23)
+#define BIT_FS_ATIM_MB6_INT_EN BIT(22)
+#define BIT_FS_ATIM_MB5_INT_EN BIT(21)
+#define BIT_FS_ATIM_MB4_INT_EN BIT(20)
+#define BIT_FS_ATIM_MB3_INT_EN BIT(19)
+#define BIT_FS_ATIM_MB2_INT_EN BIT(18)
+#define BIT_FS_ATIM_MB1_INT_EN BIT(17)
+#define BIT_FS_ATIM_MB0_INT_EN BIT(16)
+#define BIT_FS_TBTT4INT_EN BIT(11)
+#define BIT_FS_TBTT3INT_EN BIT(10)
+#define BIT_FS_TBTT2INT_EN BIT(9)
+#define BIT_FS_TBTT1INT_EN BIT(8)
+#define BIT_FS_TBTT0_MB7INT_EN BIT(7)
+#define BIT_FS_TBTT0_MB6INT_EN BIT(6)
+#define BIT_FS_TBTT0_MB5INT_EN BIT(5)
+#define BIT_FS_TBTT0_MB4INT_EN BIT(4)
+#define BIT_FS_TBTT0_MB3INT_EN BIT(3)
+#define BIT_FS_TBTT0_MB2INT_EN BIT(2)
+#define BIT_FS_TBTT0_MB1INT_EN BIT(1)
+#define BIT_FS_TBTT0_INT_EN BIT(0)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FE2ISR				(Offset 0x1124) */
+
+#define BIT__FE4ISR__IND_INT BIT(29)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FE2ISR				(Offset 0x1124) */
+
+#define BIT_FS_TXSC_DESC_DONE_INT BIT(28)
+#define BIT_FS_TXSC_BKDONE_INT BIT(27)
+#define BIT_FS_TXSC_BEDONE_INT BIT(26)
+#define BIT_FS_TXSC_VIDONE_INT BIT(25)
+#define BIT_FS_TXSC_VODONE_INT BIT(24)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FE2ISR				(Offset 0x1124) */
+
+#define BIT_FS_ATIM_MB7_INT BIT(23)
+#define BIT_FS_ATIM_MB6_INT BIT(22)
+#define BIT_FS_ATIM_MB5_INT BIT(21)
+#define BIT_FS_ATIM_MB4_INT BIT(20)
+#define BIT_FS_ATIM_MB3_INT BIT(19)
+#define BIT_FS_ATIM_MB2_INT BIT(18)
+#define BIT_FS_ATIM_MB1_INT BIT(17)
+#define BIT_FS_ATIM_MB0_INT BIT(16)
+#define BIT_FS_TBTT4INT BIT(11)
+#define BIT_FS_TBTT3INT BIT(10)
+#define BIT_FS_TBTT2INT BIT(9)
+#define BIT_FS_TBTT1INT BIT(8)
+#define BIT_FS_TBTT0_MB7INT BIT(7)
+#define BIT_FS_TBTT0_MB6INT BIT(6)
+#define BIT_FS_TBTT0_MB5INT BIT(5)
+#define BIT_FS_TBTT0_MB4INT BIT(4)
+#define BIT_FS_TBTT0_MB3INT BIT(3)
+#define BIT_FS_TBTT0_MB2INT BIT(2)
+#define BIT_FS_TBTT0_MB1INT BIT(1)
+#define BIT_FS_TBTT0_INT BIT(0)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_FE3IMR				(Offset 0x1128) */
+
+#define BIT_FS_BCNELY4_AGGR_INT_EN BIT(31)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FE3IMR				(Offset 0x1128) */
+
+#define BIT_FS_CLI3_MTI_BCNIVLEAR_INT__EN BIT(31)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_FE3IMR				(Offset 0x1128) */
+
+#define BIT_FS_BCNELY3_AGGR_INT_EN BIT(30)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FE3IMR				(Offset 0x1128) */
+
+#define BIT_FS_CLI2_MTI_BCNIVLEAR_INT__EN BIT(30)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_FE3IMR				(Offset 0x1128) */
+
+#define BIT_FS_BCNELY2_AGGR_INT_EN BIT(29)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FE3IMR				(Offset 0x1128) */
+
+#define BIT_FS_CLI1_MTI_BCNIVLEAR_INT__EN BIT(29)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_FE3IMR				(Offset 0x1128) */
+
+#define BIT_FS_BCNELY1_AGGR_INT_EN BIT(28)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FE3IMR				(Offset 0x1128) */
+
+#define BIT_FS_CLI0_MTI_BCNIVLEAR_INT__EN BIT(28)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FE3IMR				(Offset 0x1128) */
+
+#define BIT_FS_BCNDMA4_INT_EN BIT(27)
+#define BIT_FS_BCNDMA3_INT_EN BIT(26)
+#define BIT_FS_BCNDMA2_INT_EN BIT(25)
+#define BIT_FS_BCNDMA1_INT_EN BIT(24)
+#define BIT_FS_BCNDMA0_MB7_INT_EN BIT(23)
+#define BIT_FS_BCNDMA0_MB6_INT_EN BIT(22)
+#define BIT_FS_BCNDMA0_MB5_INT_EN BIT(21)
+#define BIT_FS_BCNDMA0_MB4_INT_EN BIT(20)
+#define BIT_FS_BCNDMA0_MB3_INT_EN BIT(19)
+#define BIT_FS_BCNDMA0_MB2_INT_EN BIT(18)
+#define BIT_FS_BCNDMA0_MB1_INT_EN BIT(17)
+#define BIT_FS_BCNDMA0_INT_EN BIT(16)
+#define BIT_FS_MTI_BCNIVLEAR_INT__EN BIT(15)
+#define BIT_FS_BCNERLY4_INT_EN BIT(11)
+#define BIT_FS_BCNERLY3_INT_EN BIT(10)
+#define BIT_FS_BCNERLY2_INT_EN BIT(9)
+#define BIT_FS_BCNERLY1_INT_EN BIT(8)
+#define BIT_FS_BCNERLY0_MB7INT_EN BIT(7)
+#define BIT_FS_BCNERLY0_MB6INT_EN BIT(6)
+#define BIT_FS_BCNERLY0_MB5INT_EN BIT(5)
+#define BIT_FS_BCNERLY0_MB4INT_EN BIT(4)
+#define BIT_FS_BCNERLY0_MB3INT_EN BIT(3)
+#define BIT_FS_BCNERLY0_MB2INT_EN BIT(2)
+#define BIT_FS_BCNERLY0_MB1INT_EN BIT(1)
+#define BIT_FS_BCNERLY0_INT_EN BIT(0)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_FE3ISR				(Offset 0x112C) */
+
+#define BIT_FS_BCNELY4_AGGR_INT BIT(31)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FE3ISR				(Offset 0x112C) */
+
+#define BIT_FS_CLI3_MTI_BCNIVLEAR_INT BIT(31)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_FE3ISR				(Offset 0x112C) */
+
+#define BIT_FS_BCNELY3_AGGR_INT BIT(30)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FE3ISR				(Offset 0x112C) */
+
+#define BIT_FS_CLI2_MTI_BCNIVLEAR_INT BIT(30)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_FE3ISR				(Offset 0x112C) */
+
+#define BIT_FS_BCNELY2_AGGR_INT BIT(29)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FE3ISR				(Offset 0x112C) */
+
+#define BIT_FS_CLI1_MTI_BCNIVLEAR_INT BIT(29)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_FE3ISR				(Offset 0x112C) */
+
+#define BIT_FS_BCNELY1_AGGR_INT BIT(28)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FE3ISR				(Offset 0x112C) */
+
+#define BIT_FS_CLI0_MTI_BCNIVLEAR_INT BIT(28)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FE3ISR				(Offset 0x112C) */
+
+#define BIT_FS_BCNDMA4_INT BIT(27)
+#define BIT_FS_BCNDMA3_INT BIT(26)
+#define BIT_FS_BCNDMA2_INT BIT(25)
+#define BIT_FS_BCNDMA1_INT BIT(24)
+#define BIT_FS_BCNDMA0_MB7_INT BIT(23)
+#define BIT_FS_BCNDMA0_MB6_INT BIT(22)
+#define BIT_FS_BCNDMA0_MB5_INT BIT(21)
+#define BIT_FS_BCNDMA0_MB4_INT BIT(20)
+#define BIT_FS_BCNDMA0_MB3_INT BIT(19)
+#define BIT_FS_BCNDMA0_MB2_INT BIT(18)
+#define BIT_FS_BCNDMA0_MB1_INT BIT(17)
+#define BIT_FS_BCNDMA0_INT BIT(16)
+#define BIT_FS_MTI_BCNIVLEAR_INT BIT(15)
+#define BIT_FS_BCNERLY4_INT BIT(11)
+#define BIT_FS_BCNERLY3_INT BIT(10)
+#define BIT_FS_BCNERLY2_INT BIT(9)
+#define BIT_FS_BCNERLY1_INT BIT(8)
+#define BIT_FS_BCNERLY0_MB7INT BIT(7)
+#define BIT_FS_BCNERLY0_MB6INT BIT(6)
+#define BIT_FS_BCNERLY0_MB5INT BIT(5)
+#define BIT_FS_BCNERLY0_MB4INT BIT(4)
+#define BIT_FS_BCNERLY0_MB3INT BIT(3)
+#define BIT_FS_BCNERLY0_MB2INT BIT(2)
+#define BIT_FS_BCNERLY0_MB1INT BIT(1)
+#define BIT_FS_BCNERLY0_INT BIT(0)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_FE4IMR				(Offset 0x1130) */
+
+#define BIT_PORT4_PKTIN_INT_EN BIT(19)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FE4IMR				(Offset 0x1130) */
+
+#define BIT_FS_CLI3_TXPKTIN_INT_EN BIT(19)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_FE4IMR				(Offset 0x1130) */
+
+#define BIT_PORT3_PKTIN_INT_EN BIT(18)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FE4IMR				(Offset 0x1130) */
+
+#define BIT_FS_CLI2_TXPKTIN_INT_EN BIT(18)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_FE4IMR				(Offset 0x1130) */
+
+#define BIT_PORT2_PKTIN_INT_EN BIT(17)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FE4IMR				(Offset 0x1130) */
+
+#define BIT_FS_CLI1_TXPKTIN_INT_EN BIT(17)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_FE4IMR				(Offset 0x1130) */
+
+#define BIT_PORT1_PKTIN_INT_EN BIT(16)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FE4IMR				(Offset 0x1130) */
+
+#define BIT_FS_CLI0_TXPKTIN_INT_EN BIT(16)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_FE4IMR				(Offset 0x1130) */
+
+#define BIT_PORT4_RXUCMD0_OK_INT_EN BIT(15)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FE4IMR				(Offset 0x1130) */
+
+#define BIT_FS_CLI3_RX_UMD0_INT_EN BIT(15)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_FE4IMR				(Offset 0x1130) */
+
+#define BIT_PORT4_RXUCMD1_OK_INT_EN BIT(14)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FE4IMR				(Offset 0x1130) */
+
+#define BIT_FS_CLI3_RX_UMD1_INT_EN BIT(14)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_FE4IMR				(Offset 0x1130) */
+
+#define BIT_PORT4_RXBCMD0_OK_INT_EN BIT(13)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FE4IMR				(Offset 0x1130) */
+
+#define BIT_FS_CLI3_RX_BMD0_INT_EN BIT(13)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_FE4IMR				(Offset 0x1130) */
+
+#define BIT_PORT4_RXBCMD1_OK_INT_EN BIT(12)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FE4IMR				(Offset 0x1130) */
+
+#define BIT_FS_CLI3_RX_BMD1_INT_EN BIT(12)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_FE4IMR				(Offset 0x1130) */
+
+#define BIT_PORT3_RXUCMD0_OK_INT_EN BIT(11)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FE4IMR				(Offset 0x1130) */
+
+#define BIT_FS_CLI2_RX_UMD0_INT_EN BIT(11)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_FE4IMR				(Offset 0x1130) */
+
+#define BIT_PORT3_RXUCMD1_OK_INT_EN BIT(10)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FE4IMR				(Offset 0x1130) */
+
+#define BIT_FS_CLI2_RX_UMD1_INT_EN BIT(10)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_FE4IMR				(Offset 0x1130) */
+
+#define BIT_PORT3_RXBCMD0_OK_INT_EN BIT(9)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FE4IMR				(Offset 0x1130) */
+
+#define BIT_FS_CLI2_RX_BMD0_INT_EN BIT(9)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_FE4IMR				(Offset 0x1130) */
+
+#define BIT_PORT3_RXBCMD1_OK_INT_EN BIT(8)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FE4IMR				(Offset 0x1130) */
+
+#define BIT_FS_CLI2_RX_BMD1_INT_EN BIT(8)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_FE4IMR				(Offset 0x1130) */
+
+#define BIT_PORT2_RXUCMD0_OK_INT_EN BIT(7)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FE4IMR				(Offset 0x1130) */
+
+#define BIT_FS_CLI1_RX_UMD0_INT_EN BIT(7)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_FE4IMR				(Offset 0x1130) */
+
+#define BIT_PORT2_RXUCMD1_OK_INT_EN BIT(6)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FE4IMR				(Offset 0x1130) */
+
+#define BIT_FS_CLI1_RX_UMD1_INT_EN BIT(6)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_FE4IMR				(Offset 0x1130) */
+
+#define BIT_PORT2_RXBCMD0_OK_INT_EN BIT(5)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FE4IMR				(Offset 0x1130) */
+
+#define BIT_FS_CLI1_RX_BMD0_INT_EN BIT(5)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_FE4IMR				(Offset 0x1130) */
+
+#define BIT_PORT2_RXBCMD1_OK_INT_EN BIT(4)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FE4IMR				(Offset 0x1130) */
+
+#define BIT_FS_CLI1_RX_BMD1_INT_EN BIT(4)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_FE4IMR				(Offset 0x1130) */
+
+#define BIT_PORT1_RXUCMD0_OK_INT_EN BIT(3)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FE4IMR				(Offset 0x1130) */
+
+#define BIT_FS_CLI0_RX_UMD0_INT_EN BIT(3)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_FE4IMR				(Offset 0x1130) */
+
+#define BIT_PORT1_RXUCMD1_OK_INT_EN BIT(2)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FE4IMR				(Offset 0x1130) */
+
+#define BIT_FS_CLI0_RX_UMD1_INT_EN BIT(2)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_FE4IMR				(Offset 0x1130) */
+
+#define BIT_FS_DMEM1_WPTR_UPDATE_INT_EN BIT(2)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_FE4IMR				(Offset 0x1130) */
+
+#define BIT_PORT1_RXBCMD0_OK_INT_EN BIT(1)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FE4IMR				(Offset 0x1130) */
+
+#define BIT_FS_CLI0_RX_BMD0_INT_EN BIT(1)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_FE4IMR				(Offset 0x1130) */
+
+#define BIT_PORT1_RXBCMD1_OK_INT_EN BIT(0)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FE4IMR				(Offset 0x1130) */
+
+#define BIT_FS_CLI0_RX_BMD1_INT_EN BIT(0)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_FE4ISR				(Offset 0x1134) */
+
+#define BIT_PORT4_PKTIN_INT BIT(19)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FE4ISR				(Offset 0x1134) */
+
+#define BIT_FS_CLI3_TXPKTIN_INT BIT(19)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_FE4ISR				(Offset 0x1134) */
+
+#define BIT_PORT3_PKTIN_INT BIT(18)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FE4ISR				(Offset 0x1134) */
+
+#define BIT_FS_CLI2_TXPKTIN_INT BIT(18)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_FE4ISR				(Offset 0x1134) */
+
+#define BIT_PORT2_PKTIN_INT BIT(17)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FE4ISR				(Offset 0x1134) */
+
+#define BIT_FS_CLI1_TXPKTIN_INT BIT(17)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_FE4ISR				(Offset 0x1134) */
+
+#define BIT_PORT1_PKTIN_INT BIT(16)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FE4ISR				(Offset 0x1134) */
+
+#define BIT_FS_CLI0_TXPKTIN_INT BIT(16)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_FE4ISR				(Offset 0x1134) */
+
+#define BIT_PORT4_RXUCMD0_OK_INT BIT(15)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FE4ISR				(Offset 0x1134) */
+
+#define BIT_FS_CLI3_RX_UMD0_INT BIT(15)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_FE4ISR				(Offset 0x1134) */
+
+#define BIT_PORT4_RXUCMD1_OK_INT BIT(14)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FE4ISR				(Offset 0x1134) */
+
+#define BIT_FS_CLI3_RX_UMD1_INT BIT(14)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_FE4ISR				(Offset 0x1134) */
+
+#define BIT_PORT4_RXBCMD0_OK_INT BIT(13)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FE4ISR				(Offset 0x1134) */
+
+#define BIT_FS_CLI3_RX_BMD0_INT BIT(13)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_FE4ISR				(Offset 0x1134) */
+
+#define BIT_PORT4_RXBCMD1_OK_INT BIT(12)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FE4ISR				(Offset 0x1134) */
+
+#define BIT_FS_CLI3_RX_BMD1_INT BIT(12)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_FE4ISR				(Offset 0x1134) */
+
+#define BIT_PORT3_RXUCMD0_OK_INT BIT(11)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FE4ISR				(Offset 0x1134) */
+
+#define BIT_FS_CLI2_RX_UMD0_INT BIT(11)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_FE4ISR				(Offset 0x1134) */
+
+#define BIT_PORT3_RXUCMD1_OK_INT BIT(10)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FE4ISR				(Offset 0x1134) */
+
+#define BIT_FS_CLI2_RX_UMD1_INT BIT(10)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_FE4ISR				(Offset 0x1134) */
+
+#define BIT_PORT3_RXBCMD0_OK_INT BIT(9)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FE4ISR				(Offset 0x1134) */
+
+#define BIT_FS_CLI2_RX_BMD0_INT BIT(9)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_FE4ISR				(Offset 0x1134) */
+
+#define BIT_PORT3_RXBCMD1_OK_INT BIT(8)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FE4ISR				(Offset 0x1134) */
+
+#define BIT_FS_CLI2_RX_BMD1_INT BIT(8)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_FE4ISR				(Offset 0x1134) */
+
+#define BIT_PORT2_RXUCMD0_OK_INT BIT(7)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FE4ISR				(Offset 0x1134) */
+
+#define BIT_FS_CLI1_RX_UMD0_INT BIT(7)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_FE4ISR				(Offset 0x1134) */
+
+#define BIT_PORT2_RXUCMD1_OK_INT BIT(6)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FE4ISR				(Offset 0x1134) */
+
+#define BIT_FS_CLI1_RX_UMD1_INT BIT(6)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_FE4ISR				(Offset 0x1134) */
+
+#define BIT_PORT2_RXBCMD0_OK_INT BIT(5)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FE4ISR				(Offset 0x1134) */
+
+#define BIT_FS_CLI1_RX_BMD0_INT BIT(5)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_FE4ISR				(Offset 0x1134) */
+
+#define BIT_PORT2_RXBCMD1_OK_INT BIT(4)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FE4ISR				(Offset 0x1134) */
+
+#define BIT_FS_CLI1_RX_BMD1_INT BIT(4)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_FE4ISR				(Offset 0x1134) */
+
+#define BIT_PORT1_RXUCMD0_OK_INT BIT(3)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FE4ISR				(Offset 0x1134) */
+
+#define BIT_FS_CLI0_RX_UMD0_INT BIT(3)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_FE4ISR				(Offset 0x1134) */
+
+#define BIT_PORT1_RXUCMD1_OK_INT BIT(2)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FE4ISR				(Offset 0x1134) */
+
+#define BIT_FS_CLI0_RX_UMD1_INT BIT(2)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_FE4ISR				(Offset 0x1134) */
+
+#define BIT_FS_DMEM1_WPTR_UPDATE_INT BIT(2)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_FE4ISR				(Offset 0x1134) */
+
+#define BIT_PORT1_RXBCMD0_OK_INT BIT(1)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FE4ISR				(Offset 0x1134) */
+
+#define BIT_FS_CLI0_RX_BMD0_INT BIT(1)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_FE4ISR				(Offset 0x1134) */
+
+#define BIT_PORT1_RXBCMD1_OK_INT BIT(0)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FE4ISR				(Offset 0x1134) */
+
+#define BIT_FS_CLI0_RX_BMD1_INT BIT(0)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FT1IMR				(Offset 0x1138) */
+
+#define BIT__FT2ISR__IND_MSK BIT(30)
+#define BIT_FTM_PTT_INT_EN BIT(29)
+#define BIT_RXFTMREQ_INT_EN BIT(28)
+#define BIT_RXFTM_INT_EN BIT(27)
+#define BIT_TXFTM_INT_EN BIT(26)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FT1IMR				(Offset 0x1138) */
+
+#define BIT_FS_H2C_CMD_OK_INT_EN BIT(25)
+#define BIT_FS_H2C_CMD_FULL_INT_EN BIT(24)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FT1IMR				(Offset 0x1138) */
+
+#define BIT_FS_MACID_PWRCHANGE5_INT_EN BIT(23)
+#define BIT_FS_MACID_PWRCHANGE4_INT_EN BIT(22)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_FT1IMR				(Offset 0x1138) */
+
+#define BIT_FS_MACID_SEARCH_FAIL_INT_EN BIT(22)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FT1IMR				(Offset 0x1138) */
+
+#define BIT_FS_MACID_PWRCHANGE3_INT_EN BIT(21)
+#define BIT_FS_MACID_PWRCHANGE2_INT_EN BIT(20)
+#define BIT_FS_MACID_PWRCHANGE1_INT_EN BIT(19)
+#define BIT_FS_MACID_PWRCHANGE0_INT_EN BIT(18)
+#define BIT_FS_CTWEND2_INT_EN BIT(17)
+#define BIT_FS_CTWEND1_INT_EN BIT(16)
+#define BIT_FS_CTWEND0_INT_EN BIT(15)
+#define BIT_FS_TX_NULL1_INT_EN BIT(14)
+#define BIT_FS_TX_NULL0_INT_EN BIT(13)
+#define BIT_FS_TSF_BIT32_TOGGLE_EN BIT(12)
+#define BIT_FS_P2P_RFON2_INT_EN BIT(11)
+#define BIT_FS_P2P_RFOFF2_INT_EN BIT(10)
+#define BIT_FS_P2P_RFON1_INT_EN BIT(9)
+#define BIT_FS_P2P_RFOFF1_INT_EN BIT(8)
+#define BIT_FS_P2P_RFON0_INT_EN BIT(7)
+#define BIT_FS_P2P_RFOFF0_INT_EN BIT(6)
+#define BIT_FS_RX_UAPSDMD1_EN BIT(5)
+#define BIT_FS_RX_UAPSDMD0_EN BIT(4)
+#define BIT_FS_TRIGGER_PKT_EN BIT(3)
+#define BIT_FS_EOSP_INT_EN BIT(2)
+#define BIT_FS_RPWM2_INT_EN BIT(1)
+#define BIT_FS_RPWM_INT_EN BIT(0)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FT1ISR				(Offset 0x113C) */
+
+#define BIT__FT2ISR__IND_INT BIT(30)
+#define BIT_FTM_PTT_INT BIT(29)
+#define BIT_RXFTMREQ_INT BIT(28)
+#define BIT_RXFTM_INT BIT(27)
+#define BIT_TXFTM_INT BIT(26)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FT1ISR				(Offset 0x113C) */
+
+#define BIT_FS_H2C_CMD_OK_INT BIT(25)
+#define BIT_FS_H2C_CMD_FULL_INT BIT(24)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FT1ISR				(Offset 0x113C) */
+
+#define BIT_FS_MACID_PWRCHANGE5_INT BIT(23)
+#define BIT_FS_MACID_PWRCHANGE4_INT BIT(22)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_FT1ISR				(Offset 0x113C) */
+
+#define BIT_FS_MACID_SEARCH_FAIL_INT BIT(22)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FT1ISR				(Offset 0x113C) */
+
+#define BIT_FS_MACID_PWRCHANGE3_INT BIT(21)
+#define BIT_FS_MACID_PWRCHANGE2_INT BIT(20)
+#define BIT_FS_MACID_PWRCHANGE1_INT BIT(19)
+#define BIT_FS_MACID_PWRCHANGE0_INT BIT(18)
+#define BIT_FS_CTWEND2_INT BIT(17)
+#define BIT_FS_CTWEND1_INT BIT(16)
+#define BIT_FS_CTWEND0_INT BIT(15)
+#define BIT_FS_TX_NULL1_INT BIT(14)
+#define BIT_FS_TX_NULL0_INT BIT(13)
+#define BIT_FS_TSF_BIT32_TOGGLE_INT BIT(12)
+#define BIT_FS_P2P_RFON2_INT BIT(11)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_FT1ISR				(Offset 0x113C) */
+
+#define BIT_FS_TXBCNOK_PORT4_INT_EN BIT(11)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FT1ISR				(Offset 0x113C) */
+
+#define BIT_FS_P2P_RFOFF2_INT BIT(10)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_FT1ISR				(Offset 0x113C) */
+
+#define BIT_FS_TXBCNOK_PORT3_INT_EN BIT(10)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FT1ISR				(Offset 0x113C) */
+
+#define BIT_FS_P2P_RFON1_INT BIT(9)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_FT1ISR				(Offset 0x113C) */
+
+#define BIT_FS_TXBCNOK_PORT2_INT_EN BIT(9)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FT1ISR				(Offset 0x113C) */
+
+#define BIT_FS_P2P_RFOFF1_INT BIT(8)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_FT1ISR				(Offset 0x113C) */
+
+#define BIT_FS_TXBCNOK_PORT1_INT_EN BIT(8)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FT1ISR				(Offset 0x113C) */
+
+#define BIT_FS_P2P_RFON0_INT BIT(7)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_FT1ISR				(Offset 0x113C) */
+
+#define BIT_FS_TXBCNERR_PORT4_INT_EN BIT(7)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FT1ISR				(Offset 0x113C) */
+
+#define BIT_FS_P2P_RFOFF0_INT BIT(6)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_FT1ISR				(Offset 0x113C) */
+
+#define BIT_FS_TXBCNERR_PORT3_INT_EN BIT(6)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FT1ISR				(Offset 0x113C) */
+
+#define BIT_FS_RX_UAPSDMD1_INT BIT(5)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_FT1ISR				(Offset 0x113C) */
+
+#define BIT_FS_TXBCNERR_PORT2_INT_EN BIT(5)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FT1ISR				(Offset 0x113C) */
+
+#define BIT_FS_RX_UAPSDMD0_INT BIT(4)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_FT1ISR				(Offset 0x113C) */
+
+#define BIT_FS_TXBCNERR_PORT1_INT_EN BIT(4)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FT1ISR				(Offset 0x113C) */
+
+#define BIT_FS_TRIGGER_PKT_INT BIT(3)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_FT1ISR				(Offset 0x113C) */
+
+#define BIT_FS_ATIM_PORT4_INT_EN BIT(3)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FT1ISR				(Offset 0x113C) */
+
+#define BIT_FS_EOSP_INT BIT(2)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_FT1ISR				(Offset 0x113C) */
+
+#define BIT_FS_ATIM_PORT3_INT_EN BIT(2)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FT1ISR				(Offset 0x113C) */
+
+#define BIT_FS_RPWM2_INT BIT(1)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_FT1ISR				(Offset 0x113C) */
+
+#define BIT_FS_ATIM_PORT2_INT_EN BIT(1)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FT1ISR				(Offset 0x113C) */
+
+#define BIT_FS_RPWM_INT BIT(0)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_FT1ISR				(Offset 0x113C) */
+
+#define BIT_FS_ATIM_PORT1_INT_EN BIT(0)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_SPWR0				(Offset 0x1140) */
+
+#define BIT_SHIFT_MID_31TO0 0
+#define BIT_MASK_MID_31TO0 0xffffffffL
+#define BIT_MID_31TO0(x) (((x) & BIT_MASK_MID_31TO0) << BIT_SHIFT_MID_31TO0)
+#define BITS_MID_31TO0 (BIT_MASK_MID_31TO0 << BIT_SHIFT_MID_31TO0)
+#define BIT_CLEAR_MID_31TO0(x) ((x) & (~BITS_MID_31TO0))
+#define BIT_GET_MID_31TO0(x) (((x) >> BIT_SHIFT_MID_31TO0) & BIT_MASK_MID_31TO0)
+#define BIT_SET_MID_31TO0(x, v) (BIT_CLEAR_MID_31TO0(x) | BIT_MID_31TO0(v))
+
+/* 2 REG_SPWR1				(Offset 0x1144) */
+
+#define BIT_SHIFT_MID_63TO32 0
+#define BIT_MASK_MID_63TO32 0xffffffffL
+#define BIT_MID_63TO32(x) (((x) & BIT_MASK_MID_63TO32) << BIT_SHIFT_MID_63TO32)
+#define BITS_MID_63TO32 (BIT_MASK_MID_63TO32 << BIT_SHIFT_MID_63TO32)
+#define BIT_CLEAR_MID_63TO32(x) ((x) & (~BITS_MID_63TO32))
+#define BIT_GET_MID_63TO32(x)                                                  \
+	(((x) >> BIT_SHIFT_MID_63TO32) & BIT_MASK_MID_63TO32)
+#define BIT_SET_MID_63TO32(x, v) (BIT_CLEAR_MID_63TO32(x) | BIT_MID_63TO32(v))
+
+/* 2 REG_SPWR2				(Offset 0x1148) */
+
+#define BIT_SHIFT_MID_95O64 0
+#define BIT_MASK_MID_95O64 0xffffffffL
+#define BIT_MID_95O64(x) (((x) & BIT_MASK_MID_95O64) << BIT_SHIFT_MID_95O64)
+#define BITS_MID_95O64 (BIT_MASK_MID_95O64 << BIT_SHIFT_MID_95O64)
+#define BIT_CLEAR_MID_95O64(x) ((x) & (~BITS_MID_95O64))
+#define BIT_GET_MID_95O64(x) (((x) >> BIT_SHIFT_MID_95O64) & BIT_MASK_MID_95O64)
+#define BIT_SET_MID_95O64(x, v) (BIT_CLEAR_MID_95O64(x) | BIT_MID_95O64(v))
+
+/* 2 REG_SPWR3				(Offset 0x114C) */
+
+#define BIT_SHIFT_MID_127TO96 0
+#define BIT_MASK_MID_127TO96 0xffffffffL
+#define BIT_MID_127TO96(x)                                                     \
+	(((x) & BIT_MASK_MID_127TO96) << BIT_SHIFT_MID_127TO96)
+#define BITS_MID_127TO96 (BIT_MASK_MID_127TO96 << BIT_SHIFT_MID_127TO96)
+#define BIT_CLEAR_MID_127TO96(x) ((x) & (~BITS_MID_127TO96))
+#define BIT_GET_MID_127TO96(x)                                                 \
+	(((x) >> BIT_SHIFT_MID_127TO96) & BIT_MASK_MID_127TO96)
+#define BIT_SET_MID_127TO96(x, v)                                              \
+	(BIT_CLEAR_MID_127TO96(x) | BIT_MID_127TO96(v))
+
+/* 2 REG_POWSEQ				(Offset 0x1150) */
+
+#define BIT_SHIFT_REF_MID 0
+#define BIT_MASK_REF_MID 0x7f
+#define BIT_REF_MID(x) (((x) & BIT_MASK_REF_MID) << BIT_SHIFT_REF_MID)
+#define BITS_REF_MID (BIT_MASK_REF_MID << BIT_SHIFT_REF_MID)
+#define BIT_CLEAR_REF_MID(x) ((x) & (~BITS_REF_MID))
+#define BIT_GET_REF_MID(x) (((x) >> BIT_SHIFT_REF_MID) & BIT_MASK_REF_MID)
+#define BIT_SET_REF_MID(x, v) (BIT_CLEAR_REF_MID(x) | BIT_REF_MID(v))
+
+/* 2 REG_TC7_CTRL_V1				(Offset 0x1158) */
+
+#define BIT_TC7INT_EN BIT(26)
+#define BIT_TC7MODE BIT(25)
+#define BIT_TC7EN BIT(24)
+
+#define BIT_SHIFT_TC7DATA 0
+#define BIT_MASK_TC7DATA 0xffffff
+#define BIT_TC7DATA(x) (((x) & BIT_MASK_TC7DATA) << BIT_SHIFT_TC7DATA)
+#define BITS_TC7DATA (BIT_MASK_TC7DATA << BIT_SHIFT_TC7DATA)
+#define BIT_CLEAR_TC7DATA(x) ((x) & (~BITS_TC7DATA))
+#define BIT_GET_TC7DATA(x) (((x) >> BIT_SHIFT_TC7DATA) & BIT_MASK_TC7DATA)
+#define BIT_SET_TC7DATA(x, v) (BIT_CLEAR_TC7DATA(x) | BIT_TC7DATA(v))
+
+/* 2 REG_TC8_CTRL_V1				(Offset 0x115C) */
+
+#define BIT_TC8INT_EN BIT(26)
+#define BIT_TC8MODE BIT(25)
+#define BIT_TC8EN BIT(24)
+
+#define BIT_SHIFT_TC8DATA 0
+#define BIT_MASK_TC8DATA 0xffffff
+#define BIT_TC8DATA(x) (((x) & BIT_MASK_TC8DATA) << BIT_SHIFT_TC8DATA)
+#define BITS_TC8DATA (BIT_MASK_TC8DATA << BIT_SHIFT_TC8DATA)
+#define BIT_CLEAR_TC8DATA(x) ((x) & (~BITS_TC8DATA))
+#define BIT_GET_TC8DATA(x) (((x) >> BIT_SHIFT_TC8DATA) & BIT_MASK_TC8DATA)
+#define BIT_SET_TC8DATA(x, v) (BIT_CLEAR_TC8DATA(x) | BIT_TC8DATA(v))
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+/* 2 REG_RXBCN_TBTT_INTERVAL_PORT0TO3	(Offset 0x1160) */
+
+#define BIT_SHIFT_PORT3_RXBCN_TBTT_INTERVAL 24
+#define BIT_MASK_PORT3_RXBCN_TBTT_INTERVAL 0xff
+#define BIT_PORT3_RXBCN_TBTT_INTERVAL(x)                                       \
+	(((x) & BIT_MASK_PORT3_RXBCN_TBTT_INTERVAL)                            \
+	 << BIT_SHIFT_PORT3_RXBCN_TBTT_INTERVAL)
+#define BITS_PORT3_RXBCN_TBTT_INTERVAL                                         \
+	(BIT_MASK_PORT3_RXBCN_TBTT_INTERVAL                                    \
+	 << BIT_SHIFT_PORT3_RXBCN_TBTT_INTERVAL)
+#define BIT_CLEAR_PORT3_RXBCN_TBTT_INTERVAL(x)                                 \
+	((x) & (~BITS_PORT3_RXBCN_TBTT_INTERVAL))
+#define BIT_GET_PORT3_RXBCN_TBTT_INTERVAL(x)                                   \
+	(((x) >> BIT_SHIFT_PORT3_RXBCN_TBTT_INTERVAL) &                        \
+	 BIT_MASK_PORT3_RXBCN_TBTT_INTERVAL)
+#define BIT_SET_PORT3_RXBCN_TBTT_INTERVAL(x, v)                                \
+	(BIT_CLEAR_PORT3_RXBCN_TBTT_INTERVAL(x) |                              \
+	 BIT_PORT3_RXBCN_TBTT_INTERVAL(v))
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_RX_BCN_TBTT_ITVL0			(Offset 0x1160) */
+
+#define BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT2 24
+#define BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT2 0xff
+#define BIT_RX_BCN_TBTT_ITVL_CLIENT2(x)                                        \
+	(((x) & BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT2)                             \
+	 << BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT2)
+#define BITS_RX_BCN_TBTT_ITVL_CLIENT2                                          \
+	(BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT2                                     \
+	 << BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT2)
+#define BIT_CLEAR_RX_BCN_TBTT_ITVL_CLIENT2(x)                                  \
+	((x) & (~BITS_RX_BCN_TBTT_ITVL_CLIENT2))
+#define BIT_GET_RX_BCN_TBTT_ITVL_CLIENT2(x)                                    \
+	(((x) >> BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT2) &                         \
+	 BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT2)
+#define BIT_SET_RX_BCN_TBTT_ITVL_CLIENT2(x, v)                                 \
+	(BIT_CLEAR_RX_BCN_TBTT_ITVL_CLIENT2(x) |                               \
+	 BIT_RX_BCN_TBTT_ITVL_CLIENT2(v))
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+/* 2 REG_RXBCN_TBTT_INTERVAL_PORT0TO3	(Offset 0x1160) */
+
+#define BIT_SHIFT_PORT2_RXBCN_TBTT_INTERVAL 16
+#define BIT_MASK_PORT2_RXBCN_TBTT_INTERVAL 0xff
+#define BIT_PORT2_RXBCN_TBTT_INTERVAL(x)                                       \
+	(((x) & BIT_MASK_PORT2_RXBCN_TBTT_INTERVAL)                            \
+	 << BIT_SHIFT_PORT2_RXBCN_TBTT_INTERVAL)
+#define BITS_PORT2_RXBCN_TBTT_INTERVAL                                         \
+	(BIT_MASK_PORT2_RXBCN_TBTT_INTERVAL                                    \
+	 << BIT_SHIFT_PORT2_RXBCN_TBTT_INTERVAL)
+#define BIT_CLEAR_PORT2_RXBCN_TBTT_INTERVAL(x)                                 \
+	((x) & (~BITS_PORT2_RXBCN_TBTT_INTERVAL))
+#define BIT_GET_PORT2_RXBCN_TBTT_INTERVAL(x)                                   \
+	(((x) >> BIT_SHIFT_PORT2_RXBCN_TBTT_INTERVAL) &                        \
+	 BIT_MASK_PORT2_RXBCN_TBTT_INTERVAL)
+#define BIT_SET_PORT2_RXBCN_TBTT_INTERVAL(x, v)                                \
+	(BIT_CLEAR_PORT2_RXBCN_TBTT_INTERVAL(x) |                              \
+	 BIT_PORT2_RXBCN_TBTT_INTERVAL(v))
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_RX_BCN_TBTT_ITVL0			(Offset 0x1160) */
+
+#define BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT1 16
+#define BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT1 0xff
+#define BIT_RX_BCN_TBTT_ITVL_CLIENT1(x)                                        \
+	(((x) & BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT1)                             \
+	 << BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT1)
+#define BITS_RX_BCN_TBTT_ITVL_CLIENT1                                          \
+	(BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT1                                     \
+	 << BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT1)
+#define BIT_CLEAR_RX_BCN_TBTT_ITVL_CLIENT1(x)                                  \
+	((x) & (~BITS_RX_BCN_TBTT_ITVL_CLIENT1))
+#define BIT_GET_RX_BCN_TBTT_ITVL_CLIENT1(x)                                    \
+	(((x) >> BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT1) &                         \
+	 BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT1)
+#define BIT_SET_RX_BCN_TBTT_ITVL_CLIENT1(x, v)                                 \
+	(BIT_CLEAR_RX_BCN_TBTT_ITVL_CLIENT1(x) |                               \
+	 BIT_RX_BCN_TBTT_ITVL_CLIENT1(v))
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+/* 2 REG_RXBCN_TBTT_INTERVAL_PORT0TO3	(Offset 0x1160) */
+
+#define BIT_SHIFT_PORT1_RXBCN_TBTT_INTERVAL 8
+#define BIT_MASK_PORT1_RXBCN_TBTT_INTERVAL 0xff
+#define BIT_PORT1_RXBCN_TBTT_INTERVAL(x)                                       \
+	(((x) & BIT_MASK_PORT1_RXBCN_TBTT_INTERVAL)                            \
+	 << BIT_SHIFT_PORT1_RXBCN_TBTT_INTERVAL)
+#define BITS_PORT1_RXBCN_TBTT_INTERVAL                                         \
+	(BIT_MASK_PORT1_RXBCN_TBTT_INTERVAL                                    \
+	 << BIT_SHIFT_PORT1_RXBCN_TBTT_INTERVAL)
+#define BIT_CLEAR_PORT1_RXBCN_TBTT_INTERVAL(x)                                 \
+	((x) & (~BITS_PORT1_RXBCN_TBTT_INTERVAL))
+#define BIT_GET_PORT1_RXBCN_TBTT_INTERVAL(x)                                   \
+	(((x) >> BIT_SHIFT_PORT1_RXBCN_TBTT_INTERVAL) &                        \
+	 BIT_MASK_PORT1_RXBCN_TBTT_INTERVAL)
+#define BIT_SET_PORT1_RXBCN_TBTT_INTERVAL(x, v)                                \
+	(BIT_CLEAR_PORT1_RXBCN_TBTT_INTERVAL(x) |                              \
+	 BIT_PORT1_RXBCN_TBTT_INTERVAL(v))
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_RX_BCN_TBTT_ITVL0			(Offset 0x1160) */
+
+#define BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT0 8
+#define BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT0 0xff
+#define BIT_RX_BCN_TBTT_ITVL_CLIENT0(x)                                        \
+	(((x) & BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT0)                             \
+	 << BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT0)
+#define BITS_RX_BCN_TBTT_ITVL_CLIENT0                                          \
+	(BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT0                                     \
+	 << BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT0)
+#define BIT_CLEAR_RX_BCN_TBTT_ITVL_CLIENT0(x)                                  \
+	((x) & (~BITS_RX_BCN_TBTT_ITVL_CLIENT0))
+#define BIT_GET_RX_BCN_TBTT_ITVL_CLIENT0(x)                                    \
+	(((x) >> BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT0) &                         \
+	 BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT0)
+#define BIT_SET_RX_BCN_TBTT_ITVL_CLIENT0(x, v)                                 \
+	(BIT_CLEAR_RX_BCN_TBTT_ITVL_CLIENT0(x) |                               \
+	 BIT_RX_BCN_TBTT_ITVL_CLIENT0(v))
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+/* 2 REG_RXBCN_TBTT_INTERVAL_PORT0TO3	(Offset 0x1160) */
+
+#define BIT_SHIFT_PORT0_RXBCN_TBTT_INTERVAL 0
+#define BIT_MASK_PORT0_RXBCN_TBTT_INTERVAL 0xff
+#define BIT_PORT0_RXBCN_TBTT_INTERVAL(x)                                       \
+	(((x) & BIT_MASK_PORT0_RXBCN_TBTT_INTERVAL)                            \
+	 << BIT_SHIFT_PORT0_RXBCN_TBTT_INTERVAL)
+#define BITS_PORT0_RXBCN_TBTT_INTERVAL                                         \
+	(BIT_MASK_PORT0_RXBCN_TBTT_INTERVAL                                    \
+	 << BIT_SHIFT_PORT0_RXBCN_TBTT_INTERVAL)
+#define BIT_CLEAR_PORT0_RXBCN_TBTT_INTERVAL(x)                                 \
+	((x) & (~BITS_PORT0_RXBCN_TBTT_INTERVAL))
+#define BIT_GET_PORT0_RXBCN_TBTT_INTERVAL(x)                                   \
+	(((x) >> BIT_SHIFT_PORT0_RXBCN_TBTT_INTERVAL) &                        \
+	 BIT_MASK_PORT0_RXBCN_TBTT_INTERVAL)
+#define BIT_SET_PORT0_RXBCN_TBTT_INTERVAL(x, v)                                \
+	(BIT_CLEAR_PORT0_RXBCN_TBTT_INTERVAL(x) |                              \
+	 BIT_PORT0_RXBCN_TBTT_INTERVAL(v))
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_RX_BCN_TBTT_ITVL0			(Offset 0x1160) */
+
+#define BIT_SHIFT_RX_BCN_TBTT_ITVL_PORT0 0
+#define BIT_MASK_RX_BCN_TBTT_ITVL_PORT0 0xff
+#define BIT_RX_BCN_TBTT_ITVL_PORT0(x)                                          \
+	(((x) & BIT_MASK_RX_BCN_TBTT_ITVL_PORT0)                               \
+	 << BIT_SHIFT_RX_BCN_TBTT_ITVL_PORT0)
+#define BITS_RX_BCN_TBTT_ITVL_PORT0                                            \
+	(BIT_MASK_RX_BCN_TBTT_ITVL_PORT0 << BIT_SHIFT_RX_BCN_TBTT_ITVL_PORT0)
+#define BIT_CLEAR_RX_BCN_TBTT_ITVL_PORT0(x)                                    \
+	((x) & (~BITS_RX_BCN_TBTT_ITVL_PORT0))
+#define BIT_GET_RX_BCN_TBTT_ITVL_PORT0(x)                                      \
+	(((x) >> BIT_SHIFT_RX_BCN_TBTT_ITVL_PORT0) &                           \
+	 BIT_MASK_RX_BCN_TBTT_ITVL_PORT0)
+#define BIT_SET_RX_BCN_TBTT_ITVL_PORT0(x, v)                                   \
+	(BIT_CLEAR_RX_BCN_TBTT_ITVL_PORT0(x) | BIT_RX_BCN_TBTT_ITVL_PORT0(v))
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+/* 2 REG_RXBCN_TBTT_INTERVAL_PORT4		(Offset 0x1164) */
+
+#define BIT_SHIFT_PORT4_RXBCN_TBTT_INTERVAL 0
+#define BIT_MASK_PORT4_RXBCN_TBTT_INTERVAL 0xff
+#define BIT_PORT4_RXBCN_TBTT_INTERVAL(x)                                       \
+	(((x) & BIT_MASK_PORT4_RXBCN_TBTT_INTERVAL)                            \
+	 << BIT_SHIFT_PORT4_RXBCN_TBTT_INTERVAL)
+#define BITS_PORT4_RXBCN_TBTT_INTERVAL                                         \
+	(BIT_MASK_PORT4_RXBCN_TBTT_INTERVAL                                    \
+	 << BIT_SHIFT_PORT4_RXBCN_TBTT_INTERVAL)
+#define BIT_CLEAR_PORT4_RXBCN_TBTT_INTERVAL(x)                                 \
+	((x) & (~BITS_PORT4_RXBCN_TBTT_INTERVAL))
+#define BIT_GET_PORT4_RXBCN_TBTT_INTERVAL(x)                                   \
+	(((x) >> BIT_SHIFT_PORT4_RXBCN_TBTT_INTERVAL) &                        \
+	 BIT_MASK_PORT4_RXBCN_TBTT_INTERVAL)
+#define BIT_SET_PORT4_RXBCN_TBTT_INTERVAL(x, v)                                \
+	(BIT_CLEAR_PORT4_RXBCN_TBTT_INTERVAL(x) |                              \
+	 BIT_PORT4_RXBCN_TBTT_INTERVAL(v))
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_RX_BCN_TBTT_ITVL1			(Offset 0x1164) */
+
+#define BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT3 0
+#define BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT3 0xff
+#define BIT_RX_BCN_TBTT_ITVL_CLIENT3(x)                                        \
+	(((x) & BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT3)                             \
+	 << BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT3)
+#define BITS_RX_BCN_TBTT_ITVL_CLIENT3                                          \
+	(BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT3                                     \
+	 << BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT3)
+#define BIT_CLEAR_RX_BCN_TBTT_ITVL_CLIENT3(x)                                  \
+	((x) & (~BITS_RX_BCN_TBTT_ITVL_CLIENT3))
+#define BIT_GET_RX_BCN_TBTT_ITVL_CLIENT3(x)                                    \
+	(((x) >> BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT3) &                         \
+	 BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT3)
+#define BIT_SET_RX_BCN_TBTT_ITVL_CLIENT3(x, v)                                 \
+	(BIT_CLEAR_RX_BCN_TBTT_ITVL_CLIENT3(x) |                               \
+	 BIT_RX_BCN_TBTT_ITVL_CLIENT3(v))
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT)
+
+/* 2 REG_FWIMR1				(Offset 0x1168) */
+
+#define BIT_FS_ATIM_MB15_INT_EN BIT(31)
+#define BIT_FS_ATIM_MB14_INT_EN BIT(30)
+#define BIT_FS_ATIM_MB13_INT_EN BIT(29)
+#define BIT_FS_ATIM_MB12_INT_EN BIT(28)
+#define BIT_FS_ATIM_MB11_INT_EN BIT(27)
+#define BIT_FS_ATIM_MB10_INT_EN BIT(26)
+#define BIT_FS_ATIM_MB9_INT_EN BIT(25)
+#define BIT_FS_ATIM_MB8_INT_EN BIT(24)
+#define BIT_FS_TXBCNERR_MB15_INT_EN BIT(23)
+#define BIT_FS_TXBCNERR_MB14_INT_EN BIT(22)
+#define BIT_FS_TXBCNERR_MB13_INT_EN BIT(21)
+#define BIT_FS_TXBCNERR_MB12_INT_EN BIT(20)
+#define BIT_FS_TXBCNERR_MB11_INT_EN BIT(19)
+#define BIT_FS_TXBCNERR_MB10_INT_EN BIT(18)
+#define BIT_FS_TXBCNERR_MB9_INT_EN BIT(17)
+#define BIT_FS_TXBCNERR_MB8_INT_EN BIT(16)
+#define BIT_FS_TXBCNOK_MB15_INT_EN BIT(15)
+#define BIT_FS_TXBCNOK_MB14_INT_EN BIT(14)
+#define BIT_FS_TXBCNOK_MB13_INT_EN BIT(13)
+#define BIT_FS_TXBCNOK_MB12_INT_EN BIT(12)
+#define BIT_FS_TXBCNOK_MB11_INT_EN BIT(11)
+#define BIT_FS_TXBCNOK_MB10_INT_EN BIT(10)
+#define BIT_FS_TXBCNOK_MB9_INT_EN BIT(9)
+#define BIT_FS_TXBCNOK_MB8_INT_EN BIT(8)
+#define BIT_FS_BCNERLY0_MB15INT_EN BIT(7)
+#define BIT_FS_BCNERLY0_MB14INT_EN BIT(6)
+#define BIT_FS_BCNERLY0_MB13INT_EN BIT(5)
+#define BIT_FS_BCNERLY0_MB12INT_EN BIT(4)
+#define BIT_FS_BCNERLY0_MB11INT_EN BIT(3)
+#define BIT_FS_BCNERLY0_MB10INT_EN BIT(2)
+#define BIT_FS_BCNERLY0_MB9INT_EN BIT(1)
+#define BIT_FS_BCNERLY0_MB8INT_EN BIT(0)
+
+/* 2 REG_FWISR1				(Offset 0x116C) */
+
+#define BIT_FS_ATIM_MB15_INT BIT(31)
+#define BIT_FS_ATIM_MB14_INT BIT(30)
+#define BIT_FS_ATIM_MB13_INT BIT(29)
+#define BIT_FS_ATIM_MB12_INT BIT(28)
+#define BIT_FS_ATIM_MB11_INT BIT(27)
+#define BIT_FS_ATIM_MB10_INT BIT(26)
+#define BIT_FS_ATIM_MB9_INT BIT(25)
+#define BIT_FS_ATIM_MB8_INT BIT(24)
+#define BIT_FS_TXBCNERR_MB15_INT BIT(23)
+#define BIT_FS_TXBCNERR_MB14_INT BIT(22)
+#define BIT_FS_TXBCNERR_MB13_INT BIT(21)
+#define BIT_FS_TXBCNERR_MB12_INT BIT(20)
+#define BIT_FS_TXBCNERR_MB11_INT BIT(19)
+#define BIT_FS_TXBCNERR_MB10_INT BIT(18)
+#define BIT_FS_TXBCNERR_MB9_INT BIT(17)
+#define BIT_FS_TXBCNERR_MB8_INT BIT(16)
+#define BIT_FS_TXBCNOK_MB15_INT BIT(15)
+#define BIT_FS_TXBCNOK_MB14_INT BIT(14)
+#define BIT_FS_TXBCNOK_MB13_INT BIT(13)
+#define BIT_FS_TXBCNOK_MB12_INT BIT(12)
+#define BIT_FS_TXBCNOK_MB11_INT BIT(11)
+#define BIT_FS_TXBCNOK_MB10_INT BIT(10)
+#define BIT_FS_TXBCNOK_MB9_INT BIT(9)
+#define BIT_FS_TXBCNOK_MB8_INT BIT(8)
+#define BIT_FS_BCNERLY0_MB15INT BIT(7)
+#define BIT_FS_BCNERLY0_MB14INT BIT(6)
+#define BIT_FS_BCNERLY0_MB13INT BIT(5)
+#define BIT_FS_BCNERLY0_MB12INT BIT(4)
+#define BIT_FS_BCNERLY0_MB11INT BIT(3)
+#define BIT_FS_BCNERLY0_MB10INT BIT(2)
+#define BIT_FS_BCNERLY0_MB9INT BIT(1)
+#define BIT_FS_BCNERLY0_MB8INT BIT(0)
+
+/* 2 REG_FWIMR2				(Offset 0x1170) */
+
+#define BIT_FS_BCNDMA0_MB15_INT_EN BIT(15)
+#define BIT_FS_BCNDMA0_MB14_INT_EN BIT(14)
+#define BIT_FS_BCNDMA0_MB13_INT_EN BIT(13)
+#define BIT_FS_BCNDMA0_MB12_INT_EN BIT(12)
+#define BIT_FS_BCNDMA0_MB11_INT_EN BIT(11)
+#define BIT_FS_BCNDMA0_MB10_INT_EN BIT(10)
+#define BIT_FS_BCNDMA0_MB9_INT_EN BIT(9)
+#define BIT_FS_BCNDMA0_MB8_INT_EN BIT(8)
+#define BIT_FS_TBTT0_MB15INT_EN BIT(7)
+#define BIT_FS_TBTT0_MB14INT_EN BIT(6)
+#define BIT_FS_TBTT0_MB13INT_EN BIT(5)
+#define BIT_FS_TBTT0_MB12INT_EN BIT(4)
+#define BIT_FS_TBTT0_MB11INT_EN BIT(3)
+#define BIT_FS_TBTT0_MB10INT_EN BIT(2)
+#define BIT_FS_TBTT0_MB9INT_EN BIT(1)
+#define BIT_FS_TBTT0_MB8INT_EN BIT(0)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_IO_WRAP_ERR_FLAG			(Offset 0x1170) */
+
+#define BIT_IO_WRAP_ERR BIT(0)
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT)
+
+/* 2 REG_FWISR2				(Offset 0x1174) */
+
+#define BIT_FS_BCNDMA0_MB15_INT BIT(15)
+#define BIT_FS_BCNDMA0_MB14_INT BIT(14)
+#define BIT_FS_BCNDMA0_MB13_INT BIT(13)
+#define BIT_FS_BCNDMA0_MB12_INT BIT(12)
+#define BIT_FS_BCNDMA0_MB11_INT BIT(11)
+#define BIT_FS_BCNDMA0_MB10_INT BIT(10)
+#define BIT_FS_BCNDMA0_MB9_INT BIT(9)
+#define BIT_FS_BCNDMA0_MB8_INT BIT(8)
+#define BIT_FS_TBTT0_MB15INT BIT(7)
+#define BIT_FS_TBTT0_MB14INT BIT(6)
+#define BIT_FS_TBTT0_MB13INT BIT(5)
+#define BIT_FS_TBTT0_MB12INT BIT(4)
+#define BIT_FS_TBTT0_MB11INT BIT(3)
+#define BIT_FS_TBTT0_MB10INT BIT(2)
+#define BIT_FS_TBTT0_MB9INT BIT(1)
+#define BIT_FS_TBTT0_MB8INT BIT(0)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_FWISR3				(Offset 0x117C) */
+
+#define BIT_FS_TXBCNOK_PORT4_INT BIT(11)
+#define BIT_FS_TXBCNOK_PORT3_INT BIT(10)
+#define BIT_FS_TXBCNOK_PORT2_INT BIT(9)
+#define BIT_FS_TXBCNOK_PORT1_INT BIT(8)
+#define BIT_FS_TXBCNERR_PORT4_INT BIT(7)
+#define BIT_FS_TXBCNERR_PORT3_INT BIT(6)
+#define BIT_FS_TXBCNERR_PORT2_INT BIT(5)
+#define BIT_FS_TXBCNERR_PORT1_INT BIT(4)
+#define BIT_FS_ATIM_PORT4_INT BIT(3)
+#define BIT_FS_ATIM_PORT3_INT BIT(2)
+#define BIT_FS_ATIM_PORT2_INT BIT(1)
+#define BIT_FS_ATIM_PORT1_INT BIT(0)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_SPEED_SENSOR			(Offset 0x1180) */
+
+#define BIT_DSS_1_RST_N BIT(31)
+#define BIT_DSS_1_SPEED_EN BIT(30)
+#define BIT_DSS_1_WIRE_SEL BIT(29)
+#define BIT_DSS_ENCLK BIT(28)
+
+#define BIT_SHIFT_DSS_1_RO_SEL 24
+#define BIT_MASK_DSS_1_RO_SEL 0x7
+#define BIT_DSS_1_RO_SEL(x)                                                    \
+	(((x) & BIT_MASK_DSS_1_RO_SEL) << BIT_SHIFT_DSS_1_RO_SEL)
+#define BITS_DSS_1_RO_SEL (BIT_MASK_DSS_1_RO_SEL << BIT_SHIFT_DSS_1_RO_SEL)
+#define BIT_CLEAR_DSS_1_RO_SEL(x) ((x) & (~BITS_DSS_1_RO_SEL))
+#define BIT_GET_DSS_1_RO_SEL(x)                                                \
+	(((x) >> BIT_SHIFT_DSS_1_RO_SEL) & BIT_MASK_DSS_1_RO_SEL)
+#define BIT_SET_DSS_1_RO_SEL(x, v)                                             \
+	(BIT_CLEAR_DSS_1_RO_SEL(x) | BIT_DSS_1_RO_SEL(v))
+
+#define BIT_SHIFT_DSS_1_DATA_IN 0
+#define BIT_MASK_DSS_1_DATA_IN 0xfffff
+#define BIT_DSS_1_DATA_IN(x)                                                   \
+	(((x) & BIT_MASK_DSS_1_DATA_IN) << BIT_SHIFT_DSS_1_DATA_IN)
+#define BITS_DSS_1_DATA_IN (BIT_MASK_DSS_1_DATA_IN << BIT_SHIFT_DSS_1_DATA_IN)
+#define BIT_CLEAR_DSS_1_DATA_IN(x) ((x) & (~BITS_DSS_1_DATA_IN))
+#define BIT_GET_DSS_1_DATA_IN(x)                                               \
+	(((x) >> BIT_SHIFT_DSS_1_DATA_IN) & BIT_MASK_DSS_1_DATA_IN)
+#define BIT_SET_DSS_1_DATA_IN(x, v)                                            \
+	(BIT_CLEAR_DSS_1_DATA_IN(x) | BIT_DSS_1_DATA_IN(v))
+
+/* 2 REG_SPEED_SENSOR1			(Offset 0x1184) */
+
+#define BIT_DSS_1_READY BIT(31)
+#define BIT_DSS_1_WSORT_GO BIT(30)
+
+#define BIT_SHIFT_DSS_1_COUNT_OUT 0
+#define BIT_MASK_DSS_1_COUNT_OUT 0xfffff
+#define BIT_DSS_1_COUNT_OUT(x)                                                 \
+	(((x) & BIT_MASK_DSS_1_COUNT_OUT) << BIT_SHIFT_DSS_1_COUNT_OUT)
+#define BITS_DSS_1_COUNT_OUT                                                   \
+	(BIT_MASK_DSS_1_COUNT_OUT << BIT_SHIFT_DSS_1_COUNT_OUT)
+#define BIT_CLEAR_DSS_1_COUNT_OUT(x) ((x) & (~BITS_DSS_1_COUNT_OUT))
+#define BIT_GET_DSS_1_COUNT_OUT(x)                                             \
+	(((x) >> BIT_SHIFT_DSS_1_COUNT_OUT) & BIT_MASK_DSS_1_COUNT_OUT)
+#define BIT_SET_DSS_1_COUNT_OUT(x, v)                                          \
+	(BIT_CLEAR_DSS_1_COUNT_OUT(x) | BIT_DSS_1_COUNT_OUT(v))
+
+/* 2 REG_SPEED_SENSOR2			(Offset 0x1188) */
+
+#define BIT_DSS_2_RST_N BIT(31)
+#define BIT_DSS_2_SPEED_EN BIT(30)
+#define BIT_DSS_2_WIRE_SEL BIT(29)
+
+#define BIT_SHIFT_DSS_2_RO_SEL 24
+#define BIT_MASK_DSS_2_RO_SEL 0x7
+#define BIT_DSS_2_RO_SEL(x)                                                    \
+	(((x) & BIT_MASK_DSS_2_RO_SEL) << BIT_SHIFT_DSS_2_RO_SEL)
+#define BITS_DSS_2_RO_SEL (BIT_MASK_DSS_2_RO_SEL << BIT_SHIFT_DSS_2_RO_SEL)
+#define BIT_CLEAR_DSS_2_RO_SEL(x) ((x) & (~BITS_DSS_2_RO_SEL))
+#define BIT_GET_DSS_2_RO_SEL(x)                                                \
+	(((x) >> BIT_SHIFT_DSS_2_RO_SEL) & BIT_MASK_DSS_2_RO_SEL)
+#define BIT_SET_DSS_2_RO_SEL(x, v)                                             \
+	(BIT_CLEAR_DSS_2_RO_SEL(x) | BIT_DSS_2_RO_SEL(v))
+
+#define BIT_SHIFT_DSS_2_DATA_IN 0
+#define BIT_MASK_DSS_2_DATA_IN 0xfffff
+#define BIT_DSS_2_DATA_IN(x)                                                   \
+	(((x) & BIT_MASK_DSS_2_DATA_IN) << BIT_SHIFT_DSS_2_DATA_IN)
+#define BITS_DSS_2_DATA_IN (BIT_MASK_DSS_2_DATA_IN << BIT_SHIFT_DSS_2_DATA_IN)
+#define BIT_CLEAR_DSS_2_DATA_IN(x) ((x) & (~BITS_DSS_2_DATA_IN))
+#define BIT_GET_DSS_2_DATA_IN(x)                                               \
+	(((x) >> BIT_SHIFT_DSS_2_DATA_IN) & BIT_MASK_DSS_2_DATA_IN)
+#define BIT_SET_DSS_2_DATA_IN(x, v)                                            \
+	(BIT_CLEAR_DSS_2_DATA_IN(x) | BIT_DSS_2_DATA_IN(v))
+
+/* 2 REG_SPEED_SENSOR3			(Offset 0x118C) */
+
+#define BIT_DSS_2_READY BIT(31)
+#define BIT_DSS_2_WSORT_GO BIT(30)
+
+#define BIT_SHIFT_DSS_2_COUNT_OUT 0
+#define BIT_MASK_DSS_2_COUNT_OUT 0xfffff
+#define BIT_DSS_2_COUNT_OUT(x)                                                 \
+	(((x) & BIT_MASK_DSS_2_COUNT_OUT) << BIT_SHIFT_DSS_2_COUNT_OUT)
+#define BITS_DSS_2_COUNT_OUT                                                   \
+	(BIT_MASK_DSS_2_COUNT_OUT << BIT_SHIFT_DSS_2_COUNT_OUT)
+#define BIT_CLEAR_DSS_2_COUNT_OUT(x) ((x) & (~BITS_DSS_2_COUNT_OUT))
+#define BIT_GET_DSS_2_COUNT_OUT(x)                                             \
+	(((x) >> BIT_SHIFT_DSS_2_COUNT_OUT) & BIT_MASK_DSS_2_COUNT_OUT)
+#define BIT_SET_DSS_2_COUNT_OUT(x, v)                                          \
+	(BIT_CLEAR_DSS_2_COUNT_OUT(x) | BIT_DSS_2_COUNT_OUT(v))
+
+/* 2 REG_SPEED_SENSOR4			(Offset 0x1190) */
+
+#define BIT_DSS_3_RST_N BIT(31)
+#define BIT_DSS_3_SPEED_EN BIT(30)
+#define BIT_DSS_3_WIRE_SEL BIT(29)
+
+#define BIT_SHIFT_DSS_3_RO_SEL 24
+#define BIT_MASK_DSS_3_RO_SEL 0x7
+#define BIT_DSS_3_RO_SEL(x)                                                    \
+	(((x) & BIT_MASK_DSS_3_RO_SEL) << BIT_SHIFT_DSS_3_RO_SEL)
+#define BITS_DSS_3_RO_SEL (BIT_MASK_DSS_3_RO_SEL << BIT_SHIFT_DSS_3_RO_SEL)
+#define BIT_CLEAR_DSS_3_RO_SEL(x) ((x) & (~BITS_DSS_3_RO_SEL))
+#define BIT_GET_DSS_3_RO_SEL(x)                                                \
+	(((x) >> BIT_SHIFT_DSS_3_RO_SEL) & BIT_MASK_DSS_3_RO_SEL)
+#define BIT_SET_DSS_3_RO_SEL(x, v)                                             \
+	(BIT_CLEAR_DSS_3_RO_SEL(x) | BIT_DSS_3_RO_SEL(v))
+
+#define BIT_SHIFT_DSS_3_DATA_IN 0
+#define BIT_MASK_DSS_3_DATA_IN 0xfffff
+#define BIT_DSS_3_DATA_IN(x)                                                   \
+	(((x) & BIT_MASK_DSS_3_DATA_IN) << BIT_SHIFT_DSS_3_DATA_IN)
+#define BITS_DSS_3_DATA_IN (BIT_MASK_DSS_3_DATA_IN << BIT_SHIFT_DSS_3_DATA_IN)
+#define BIT_CLEAR_DSS_3_DATA_IN(x) ((x) & (~BITS_DSS_3_DATA_IN))
+#define BIT_GET_DSS_3_DATA_IN(x)                                               \
+	(((x) >> BIT_SHIFT_DSS_3_DATA_IN) & BIT_MASK_DSS_3_DATA_IN)
+#define BIT_SET_DSS_3_DATA_IN(x, v)                                            \
+	(BIT_CLEAR_DSS_3_DATA_IN(x) | BIT_DSS_3_DATA_IN(v))
+
+/* 2 REG_SPEED_SENSOR5			(Offset 0x1194) */
+
+#define BIT_DSS_3_READY BIT(31)
+#define BIT_DSS_3_WSORT_GO BIT(30)
+
+#define BIT_SHIFT_DSS_3_COUNT_OUT 0
+#define BIT_MASK_DSS_3_COUNT_OUT 0xfffff
+#define BIT_DSS_3_COUNT_OUT(x)                                                 \
+	(((x) & BIT_MASK_DSS_3_COUNT_OUT) << BIT_SHIFT_DSS_3_COUNT_OUT)
+#define BITS_DSS_3_COUNT_OUT                                                   \
+	(BIT_MASK_DSS_3_COUNT_OUT << BIT_SHIFT_DSS_3_COUNT_OUT)
+#define BIT_CLEAR_DSS_3_COUNT_OUT(x) ((x) & (~BITS_DSS_3_COUNT_OUT))
+#define BIT_GET_DSS_3_COUNT_OUT(x)                                             \
+	(((x) >> BIT_SHIFT_DSS_3_COUNT_OUT) & BIT_MASK_DSS_3_COUNT_OUT)
+#define BIT_SET_DSS_3_COUNT_OUT(x, v)                                          \
+	(BIT_CLEAR_DSS_3_COUNT_OUT(x) | BIT_DSS_3_COUNT_OUT(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_RXPKTBUF_1_MAX_ADDR			(Offset 0x1198) */
+
+#define BIT_SHIFT_RXPKTBUF_SIZE 30
+#define BIT_MASK_RXPKTBUF_SIZE 0x3
+#define BIT_RXPKTBUF_SIZE(x)                                                   \
+	(((x) & BIT_MASK_RXPKTBUF_SIZE) << BIT_SHIFT_RXPKTBUF_SIZE)
+#define BITS_RXPKTBUF_SIZE (BIT_MASK_RXPKTBUF_SIZE << BIT_SHIFT_RXPKTBUF_SIZE)
+#define BIT_CLEAR_RXPKTBUF_SIZE(x) ((x) & (~BITS_RXPKTBUF_SIZE))
+#define BIT_GET_RXPKTBUF_SIZE(x)                                               \
+	(((x) >> BIT_SHIFT_RXPKTBUF_SIZE) & BIT_MASK_RXPKTBUF_SIZE)
+#define BIT_SET_RXPKTBUF_SIZE(x, v)                                            \
+	(BIT_CLEAR_RXPKTBUF_SIZE(x) | BIT_RXPKTBUF_SIZE(v))
+
+#define BIT_RXPKTBUF_DBG_SEL BIT(29)
+
+#define BIT_SHIFT_RXPKTBUF_1_MAX_ADDR 0
+#define BIT_MASK_RXPKTBUF_1_MAX_ADDR 0x3ffff
+#define BIT_RXPKTBUF_1_MAX_ADDR(x)                                             \
+	(((x) & BIT_MASK_RXPKTBUF_1_MAX_ADDR) << BIT_SHIFT_RXPKTBUF_1_MAX_ADDR)
+#define BITS_RXPKTBUF_1_MAX_ADDR                                               \
+	(BIT_MASK_RXPKTBUF_1_MAX_ADDR << BIT_SHIFT_RXPKTBUF_1_MAX_ADDR)
+#define BIT_CLEAR_RXPKTBUF_1_MAX_ADDR(x) ((x) & (~BITS_RXPKTBUF_1_MAX_ADDR))
+#define BIT_GET_RXPKTBUF_1_MAX_ADDR(x)                                         \
+	(((x) >> BIT_SHIFT_RXPKTBUF_1_MAX_ADDR) & BIT_MASK_RXPKTBUF_1_MAX_ADDR)
+#define BIT_SET_RXPKTBUF_1_MAX_ADDR(x, v)                                      \
+	(BIT_CLEAR_RXPKTBUF_1_MAX_ADDR(x) | BIT_RXPKTBUF_1_MAX_ADDR(v))
+
+/* 2 REG_RXFWBUF_1_MAX_ADDR			(Offset 0x119C) */
+
+#define BIT_SHIFT_RXFWBUF_1_MAX_ADDR 0
+#define BIT_MASK_RXFWBUF_1_MAX_ADDR 0xffff
+#define BIT_RXFWBUF_1_MAX_ADDR(x)                                              \
+	(((x) & BIT_MASK_RXFWBUF_1_MAX_ADDR) << BIT_SHIFT_RXFWBUF_1_MAX_ADDR)
+#define BITS_RXFWBUF_1_MAX_ADDR                                                \
+	(BIT_MASK_RXFWBUF_1_MAX_ADDR << BIT_SHIFT_RXFWBUF_1_MAX_ADDR)
+#define BIT_CLEAR_RXFWBUF_1_MAX_ADDR(x) ((x) & (~BITS_RXFWBUF_1_MAX_ADDR))
+#define BIT_GET_RXFWBUF_1_MAX_ADDR(x)                                          \
+	(((x) >> BIT_SHIFT_RXFWBUF_1_MAX_ADDR) & BIT_MASK_RXFWBUF_1_MAX_ADDR)
+#define BIT_SET_RXFWBUF_1_MAX_ADDR(x, v)                                       \
+	(BIT_CLEAR_RXFWBUF_1_MAX_ADDR(x) | BIT_RXFWBUF_1_MAX_ADDR(v))
+
+/* 2 REG_RXPKTBUF_1_READ			(Offset 0x11A4) */
+
+#define BIT_SHIFT_RXPKTBUF_1_READ 0
+#define BIT_MASK_RXPKTBUF_1_READ 0x3ffff
+#define BIT_RXPKTBUF_1_READ(x)                                                 \
+	(((x) & BIT_MASK_RXPKTBUF_1_READ) << BIT_SHIFT_RXPKTBUF_1_READ)
+#define BITS_RXPKTBUF_1_READ                                                   \
+	(BIT_MASK_RXPKTBUF_1_READ << BIT_SHIFT_RXPKTBUF_1_READ)
+#define BIT_CLEAR_RXPKTBUF_1_READ(x) ((x) & (~BITS_RXPKTBUF_1_READ))
+#define BIT_GET_RXPKTBUF_1_READ(x)                                             \
+	(((x) >> BIT_SHIFT_RXPKTBUF_1_READ) & BIT_MASK_RXPKTBUF_1_READ)
+#define BIT_SET_RXPKTBUF_1_READ(x, v)                                          \
+	(BIT_CLEAR_RXPKTBUF_1_READ(x) | BIT_RXPKTBUF_1_READ(v))
+
+/* 2 REG_RXPKTBUF_1_WRITE			(Offset 0x11A8) */
+
+#define BIT_SHIFT_R_OQT_DBG_SEL 16
+#define BIT_MASK_R_OQT_DBG_SEL 0xff
+#define BIT_R_OQT_DBG_SEL(x)                                                   \
+	(((x) & BIT_MASK_R_OQT_DBG_SEL) << BIT_SHIFT_R_OQT_DBG_SEL)
+#define BITS_R_OQT_DBG_SEL (BIT_MASK_R_OQT_DBG_SEL << BIT_SHIFT_R_OQT_DBG_SEL)
+#define BIT_CLEAR_R_OQT_DBG_SEL(x) ((x) & (~BITS_R_OQT_DBG_SEL))
+#define BIT_GET_R_OQT_DBG_SEL(x)                                               \
+	(((x) >> BIT_SHIFT_R_OQT_DBG_SEL) & BIT_MASK_R_OQT_DBG_SEL)
+#define BIT_SET_R_OQT_DBG_SEL(x, v)                                            \
+	(BIT_CLEAR_R_OQT_DBG_SEL(x) | BIT_R_OQT_DBG_SEL(v))
+
+#define BIT_SHIFT_R_TXPKTBF_DBG_SEL 8
+#define BIT_MASK_R_TXPKTBF_DBG_SEL 0x7
+#define BIT_R_TXPKTBF_DBG_SEL(x)                                               \
+	(((x) & BIT_MASK_R_TXPKTBF_DBG_SEL) << BIT_SHIFT_R_TXPKTBF_DBG_SEL)
+#define BITS_R_TXPKTBF_DBG_SEL                                                 \
+	(BIT_MASK_R_TXPKTBF_DBG_SEL << BIT_SHIFT_R_TXPKTBF_DBG_SEL)
+#define BIT_CLEAR_R_TXPKTBF_DBG_SEL(x) ((x) & (~BITS_R_TXPKTBF_DBG_SEL))
+#define BIT_GET_R_TXPKTBF_DBG_SEL(x)                                           \
+	(((x) >> BIT_SHIFT_R_TXPKTBF_DBG_SEL) & BIT_MASK_R_TXPKTBF_DBG_SEL)
+#define BIT_SET_R_TXPKTBF_DBG_SEL(x, v)                                        \
+	(BIT_CLEAR_R_TXPKTBF_DBG_SEL(x) | BIT_R_TXPKTBF_DBG_SEL(v))
+
+#define BIT_SHIFT_R_RXPKT_DBG_SEL 6
+#define BIT_MASK_R_RXPKT_DBG_SEL 0x3
+#define BIT_R_RXPKT_DBG_SEL(x)                                                 \
+	(((x) & BIT_MASK_R_RXPKT_DBG_SEL) << BIT_SHIFT_R_RXPKT_DBG_SEL)
+#define BITS_R_RXPKT_DBG_SEL                                                   \
+	(BIT_MASK_R_RXPKT_DBG_SEL << BIT_SHIFT_R_RXPKT_DBG_SEL)
+#define BIT_CLEAR_R_RXPKT_DBG_SEL(x) ((x) & (~BITS_R_RXPKT_DBG_SEL))
+#define BIT_GET_R_RXPKT_DBG_SEL(x)                                             \
+	(((x) >> BIT_SHIFT_R_RXPKT_DBG_SEL) & BIT_MASK_R_RXPKT_DBG_SEL)
+#define BIT_SET_R_RXPKT_DBG_SEL(x, v)                                          \
+	(BIT_CLEAR_R_RXPKT_DBG_SEL(x) | BIT_R_RXPKT_DBG_SEL(v))
+
+#define BIT_SHIFT_RXPKTBUF_1_WRITE 0
+#define BIT_MASK_RXPKTBUF_1_WRITE 0x3ffff
+#define BIT_RXPKTBUF_1_WRITE(x)                                                \
+	(((x) & BIT_MASK_RXPKTBUF_1_WRITE) << BIT_SHIFT_RXPKTBUF_1_WRITE)
+#define BITS_RXPKTBUF_1_WRITE                                                  \
+	(BIT_MASK_RXPKTBUF_1_WRITE << BIT_SHIFT_RXPKTBUF_1_WRITE)
+#define BIT_CLEAR_RXPKTBUF_1_WRITE(x) ((x) & (~BITS_RXPKTBUF_1_WRITE))
+#define BIT_GET_RXPKTBUF_1_WRITE(x)                                            \
+	(((x) >> BIT_SHIFT_RXPKTBUF_1_WRITE) & BIT_MASK_RXPKTBUF_1_WRITE)
+#define BIT_SET_RXPKTBUF_1_WRITE(x, v)                                         \
+	(BIT_CLEAR_RXPKTBUF_1_WRITE(x) | BIT_RXPKTBUF_1_WRITE(v))
+
+#define BIT_SHIFT_R_RXPKTBF_DBG_SEL 0
+#define BIT_MASK_R_RXPKTBF_DBG_SEL 0x3
+#define BIT_R_RXPKTBF_DBG_SEL(x)                                               \
+	(((x) & BIT_MASK_R_RXPKTBF_DBG_SEL) << BIT_SHIFT_R_RXPKTBF_DBG_SEL)
+#define BITS_R_RXPKTBF_DBG_SEL                                                 \
+	(BIT_MASK_R_RXPKTBF_DBG_SEL << BIT_SHIFT_R_RXPKTBF_DBG_SEL)
+#define BIT_CLEAR_R_RXPKTBF_DBG_SEL(x) ((x) & (~BITS_R_RXPKTBF_DBG_SEL))
+#define BIT_GET_R_RXPKTBF_DBG_SEL(x)                                           \
+	(((x) >> BIT_SHIFT_R_RXPKTBF_DBG_SEL) & BIT_MASK_R_RXPKTBF_DBG_SEL)
+#define BIT_SET_R_RXPKTBF_DBG_SEL(x, v)                                        \
+	(BIT_CLEAR_R_RXPKTBF_DBG_SEL(x) | BIT_R_RXPKTBF_DBG_SEL(v))
+
+/* 2 REG_RFE_CTRL_PAD_E2			(Offset 0x11B0) */
+
+#define BIT_RFE_CTRL_ANTSW_E2 BIT(16)
+#define BIT_RFE_CTRL_PIN15_E2 BIT(15)
+#define BIT_RFE_CTRL_PIN14_E2 BIT(14)
+#define BIT_RFE_CTRL_PIN13_E2 BIT(13)
+#define BIT_RFE_CTRL_PIN12_E2 BIT(12)
+#define BIT_RFE_CTRL_PIN11_E2 BIT(11)
+#define BIT_RFE_CTRL_PIN10_E2 BIT(10)
+#define BIT_RFE_CTRL_PIN9_E2 BIT(9)
+#define BIT_RFE_CTRL_PIN8_E2 BIT(8)
+#define BIT_RFE_CTRL_PIN7_E2 BIT(7)
+#define BIT_RFE_CTRL_PIN6_E2 BIT(6)
+#define BIT_RFE_CTRL_PIN5_E2 BIT(5)
+#define BIT_RFE_CTRL_PIN4_E2 BIT(4)
+#define BIT_RFE_CTRL_PIN3_E2 BIT(3)
+#define BIT_RFE_CTRL_PIN2_E2 BIT(2)
+#define BIT_RFE_CTRL_PIN1_E2 BIT(1)
+#define BIT_RFE_CTRL_PIN0_E2 BIT(0)
+
+/* 2 REG_RFE_CTRL_PAD_SR			(Offset 0x11B4) */
+
+#define BIT_RFE_CTRL_ANTSW_SR BIT(16)
+#define BIT_RFE_CTRL_PIN15_SR BIT(15)
+#define BIT_RFE_CTRL_PIN14_SR BIT(14)
+#define BIT_RFE_CTRL_PIN13_SR BIT(13)
+#define BIT_RFE_CTRL_PIN12_SR BIT(12)
+#define BIT_RFE_CTRL_PIN11_SR BIT(11)
+#define BIT_RFE_CTRL_PIN10_SR BIT(10)
+#define BIT_RFE_CTRL_PIN9_SR BIT(9)
+#define BIT_RFE_CTRL_PIN8_SR BIT(8)
+#define BIT_RFE_CTRL_PIN7_SR BIT(7)
+#define BIT_RFE_CTRL_PIN6_SR BIT(6)
+#define BIT_RFE_CTRL_PIN5_SR BIT(5)
+#define BIT_RFE_CTRL_PIN4_SR BIT(4)
+#define BIT_RFE_CTRL_PIN3_SR BIT(3)
+#define BIT_RFE_CTRL_PIN2_SR BIT(2)
+#define BIT_RFE_CTRL_PIN1_SR BIT(1)
+#define BIT_RFE_CTRL_PIN0_SR BIT(0)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_EXT_QUEUE_REG			(Offset 0x11C0) */
+
+#define BIT_SHIFT_PCIE_PRIORITY_SEL 0
+#define BIT_MASK_PCIE_PRIORITY_SEL 0x3
+#define BIT_PCIE_PRIORITY_SEL(x)                                               \
+	(((x) & BIT_MASK_PCIE_PRIORITY_SEL) << BIT_SHIFT_PCIE_PRIORITY_SEL)
+#define BITS_PCIE_PRIORITY_SEL                                                 \
+	(BIT_MASK_PCIE_PRIORITY_SEL << BIT_SHIFT_PCIE_PRIORITY_SEL)
+#define BIT_CLEAR_PCIE_PRIORITY_SEL(x) ((x) & (~BITS_PCIE_PRIORITY_SEL))
+#define BIT_GET_PCIE_PRIORITY_SEL(x)                                           \
+	(((x) >> BIT_SHIFT_PCIE_PRIORITY_SEL) & BIT_MASK_PCIE_PRIORITY_SEL)
+#define BIT_SET_PCIE_PRIORITY_SEL(x, v)                                        \
+	(BIT_CLEAR_PCIE_PRIORITY_SEL(x) | BIT_PCIE_PRIORITY_SEL(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_H2C_PRIORITY_SEL			(Offset 0x11C0) */
+
+#define BIT_SHIFT_H2C_PRIORITY_SEL 0
+#define BIT_MASK_H2C_PRIORITY_SEL 0x3
+#define BIT_H2C_PRIORITY_SEL(x)                                                \
+	(((x) & BIT_MASK_H2C_PRIORITY_SEL) << BIT_SHIFT_H2C_PRIORITY_SEL)
+#define BITS_H2C_PRIORITY_SEL                                                  \
+	(BIT_MASK_H2C_PRIORITY_SEL << BIT_SHIFT_H2C_PRIORITY_SEL)
+#define BIT_CLEAR_H2C_PRIORITY_SEL(x) ((x) & (~BITS_H2C_PRIORITY_SEL))
+#define BIT_GET_H2C_PRIORITY_SEL(x)                                            \
+	(((x) >> BIT_SHIFT_H2C_PRIORITY_SEL) & BIT_MASK_H2C_PRIORITY_SEL)
+#define BIT_SET_H2C_PRIORITY_SEL(x, v)                                         \
+	(BIT_CLEAR_H2C_PRIORITY_SEL(x) | BIT_H2C_PRIORITY_SEL(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_COUNTER_CONTROL			(Offset 0x11C4) */
+
+#define BIT_EN_USB_CNT BIT(5)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_COUNTER_CTRL			(Offset 0x11C4) */
+
+#define BIT_USB_COUNT_EN BIT(5)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_COUNTER_CONTROL			(Offset 0x11C4) */
+
+#define BIT_EN_PCIE_CNT BIT(4)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_COUNTER_CTRL			(Offset 0x11C4) */
+
+#define BIT_PCIE_COUNT_EN BIT(4)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_COUNTER_CONTROL			(Offset 0x11C4) */
+
+#define BIT_RQPN_CNT BIT(3)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_COUNTER_CTRL			(Offset 0x11C4) */
+
+#define BIT_RQPN_COUNT_EN BIT(3)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_COUNTER_CONTROL			(Offset 0x11C4) */
+
+#define BIT_RDE_CNT BIT(2)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_COUNTER_CTRL			(Offset 0x11C4) */
+
+#define BIT_RDE_COUNT_EN BIT(2)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_COUNTER_CONTROL			(Offset 0x11C4) */
+
+#define BIT_TDE_CNT BIT(1)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_COUNTER_CTRL			(Offset 0x11C4) */
+
+#define BIT_TDE_COUNT_EN BIT(1)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_COUNTER_CONTROL			(Offset 0x11C4) */
+
+#define BIT_DIS_CNT BIT(0)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_COUNTER_CTRL			(Offset 0x11C4) */
+
+#define BIT_DISABLE_COUNTER BIT(0)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_COUNTER_TH				(Offset 0x11C8) */
+
+#define BIT_CNT_ALL_MACID BIT(31)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_COUNTER_THRESHOLD			(Offset 0x11C8) */
+
+#define BIT_SEL_ALL_MACID BIT(31)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_COUNTER_TH				(Offset 0x11C8) */
+
+#define BIT_SHIFT_CNT_MACID 24
+#define BIT_MASK_CNT_MACID 0x7f
+#define BIT_CNT_MACID(x) (((x) & BIT_MASK_CNT_MACID) << BIT_SHIFT_CNT_MACID)
+#define BITS_CNT_MACID (BIT_MASK_CNT_MACID << BIT_SHIFT_CNT_MACID)
+#define BIT_CLEAR_CNT_MACID(x) ((x) & (~BITS_CNT_MACID))
+#define BIT_GET_CNT_MACID(x) (((x) >> BIT_SHIFT_CNT_MACID) & BIT_MASK_CNT_MACID)
+#define BIT_SET_CNT_MACID(x, v) (BIT_CLEAR_CNT_MACID(x) | BIT_CNT_MACID(v))
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_COUNTER_THRESHOLD			(Offset 0x11C8) */
+
+#define BIT_SHIFT_COUNTER_MACID 24
+#define BIT_MASK_COUNTER_MACID 0x7f
+#define BIT_COUNTER_MACID(x)                                                   \
+	(((x) & BIT_MASK_COUNTER_MACID) << BIT_SHIFT_COUNTER_MACID)
+#define BITS_COUNTER_MACID (BIT_MASK_COUNTER_MACID << BIT_SHIFT_COUNTER_MACID)
+#define BIT_CLEAR_COUNTER_MACID(x) ((x) & (~BITS_COUNTER_MACID))
+#define BIT_GET_COUNTER_MACID(x)                                               \
+	(((x) >> BIT_SHIFT_COUNTER_MACID) & BIT_MASK_COUNTER_MACID)
+#define BIT_SET_COUNTER_MACID(x, v)                                            \
+	(BIT_CLEAR_COUNTER_MACID(x) | BIT_COUNTER_MACID(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_COUNTER_SET				(Offset 0x11CC) */
+
+#define BIT_RTS_RST BIT(24)
+#define BIT_PTCL_RST BIT(23)
+#define BIT_SCH_RST BIT(22)
+#define BIT_EDCA_RST BIT(21)
+#define BIT_RQPN_RST BIT(20)
+#define BIT_USB_RST BIT(19)
+#define BIT_PCIE_RST BIT(18)
+#define BIT_RXDMA_RST BIT(17)
+#define BIT_TXDMA_RST BIT(16)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_COUNTER_SET				(Offset 0x11CC) */
+
+#define BIT_SHIFT_REQUEST_RESET 16
+#define BIT_MASK_REQUEST_RESET 0xffff
+#define BIT_REQUEST_RESET(x)                                                   \
+	(((x) & BIT_MASK_REQUEST_RESET) << BIT_SHIFT_REQUEST_RESET)
+#define BITS_REQUEST_RESET (BIT_MASK_REQUEST_RESET << BIT_SHIFT_REQUEST_RESET)
+#define BIT_CLEAR_REQUEST_RESET(x) ((x) & (~BITS_REQUEST_RESET))
+#define BIT_GET_REQUEST_RESET(x)                                               \
+	(((x) >> BIT_SHIFT_REQUEST_RESET) & BIT_MASK_REQUEST_RESET)
+#define BIT_SET_REQUEST_RESET(x, v)                                            \
+	(BIT_CLEAR_REQUEST_RESET(x) | BIT_REQUEST_RESET(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_COUNTER_SET				(Offset 0x11CC) */
+
+#define BIT_EN_RTS_START BIT(8)
+#define BIT_EN_PTCL_START BIT(7)
+#define BIT_EN_SCH_START BIT(6)
+#define BIT_EN_EDCA_START BIT(5)
+#define BIT_EN_RQPN_START BIT(4)
+#define BIT_EN_USB_START BIT(3)
+#define BIT_EN_PCIE_START BIT(2)
+#define BIT_EN_RXDMA_START BIT(1)
+#define BIT_EN_TXDMA_START BIT(0)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_COUNTER_SET				(Offset 0x11CC) */
+
+#define BIT_SHIFT_REQUEST_START 0
+#define BIT_MASK_REQUEST_START 0xffff
+#define BIT_REQUEST_START(x)                                                   \
+	(((x) & BIT_MASK_REQUEST_START) << BIT_SHIFT_REQUEST_START)
+#define BITS_REQUEST_START (BIT_MASK_REQUEST_START << BIT_SHIFT_REQUEST_START)
+#define BIT_CLEAR_REQUEST_START(x) ((x) & (~BITS_REQUEST_START))
+#define BIT_GET_REQUEST_START(x)                                               \
+	(((x) >> BIT_SHIFT_REQUEST_START) & BIT_MASK_REQUEST_START)
+#define BIT_SET_REQUEST_START(x, v)                                            \
+	(BIT_CLEAR_REQUEST_START(x) | BIT_REQUEST_START(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_COUNTER_OVERFLOW			(Offset 0x11D0) */
+
+#define BIT_RTS_OVF BIT(8)
+#define BIT_PTCL_OVF BIT(7)
+#define BIT_SCH_OVF BIT(6)
+#define BIT_EDCA_OVF BIT(5)
+#define BIT_RQPN_OVF BIT(4)
+#define BIT_USB_OVF BIT(3)
+#define BIT_PCIE_OVF BIT(2)
+#define BIT_RXDMA_OVF BIT(1)
+#define BIT_TXDMA_OVF BIT(0)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_COUNTER_OVERFLOW			(Offset 0x11D0) */
+
+#define BIT_SHIFT_CNT_OVF_REG 0
+#define BIT_MASK_CNT_OVF_REG 0xffff
+#define BIT_CNT_OVF_REG(x)                                                     \
+	(((x) & BIT_MASK_CNT_OVF_REG) << BIT_SHIFT_CNT_OVF_REG)
+#define BITS_CNT_OVF_REG (BIT_MASK_CNT_OVF_REG << BIT_SHIFT_CNT_OVF_REG)
+#define BIT_CLEAR_CNT_OVF_REG(x) ((x) & (~BITS_CNT_OVF_REG))
+#define BIT_GET_CNT_OVF_REG(x)                                                 \
+	(((x) >> BIT_SHIFT_CNT_OVF_REG) & BIT_MASK_CNT_OVF_REG)
+#define BIT_SET_CNT_OVF_REG(x, v)                                              \
+	(BIT_CLEAR_CNT_OVF_REG(x) | BIT_CNT_OVF_REG(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_TDE_LEN_TH				(Offset 0x11D4) */
+
+#define BIT_SHIFT_TXDMA_LEN_TH0 16
+#define BIT_MASK_TXDMA_LEN_TH0 0xffff
+#define BIT_TXDMA_LEN_TH0(x)                                                   \
+	(((x) & BIT_MASK_TXDMA_LEN_TH0) << BIT_SHIFT_TXDMA_LEN_TH0)
+#define BITS_TXDMA_LEN_TH0 (BIT_MASK_TXDMA_LEN_TH0 << BIT_SHIFT_TXDMA_LEN_TH0)
+#define BIT_CLEAR_TXDMA_LEN_TH0(x) ((x) & (~BITS_TXDMA_LEN_TH0))
+#define BIT_GET_TXDMA_LEN_TH0(x)                                               \
+	(((x) >> BIT_SHIFT_TXDMA_LEN_TH0) & BIT_MASK_TXDMA_LEN_TH0)
+#define BIT_SET_TXDMA_LEN_TH0(x, v)                                            \
+	(BIT_CLEAR_TXDMA_LEN_TH0(x) | BIT_TXDMA_LEN_TH0(v))
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_TXDMA_LEN_THRESHOLD			(Offset 0x11D4) */
+
+#define BIT_SHIFT_TDE_LEN_TH1 16
+#define BIT_MASK_TDE_LEN_TH1 0xffff
+#define BIT_TDE_LEN_TH1(x)                                                     \
+	(((x) & BIT_MASK_TDE_LEN_TH1) << BIT_SHIFT_TDE_LEN_TH1)
+#define BITS_TDE_LEN_TH1 (BIT_MASK_TDE_LEN_TH1 << BIT_SHIFT_TDE_LEN_TH1)
+#define BIT_CLEAR_TDE_LEN_TH1(x) ((x) & (~BITS_TDE_LEN_TH1))
+#define BIT_GET_TDE_LEN_TH1(x)                                                 \
+	(((x) >> BIT_SHIFT_TDE_LEN_TH1) & BIT_MASK_TDE_LEN_TH1)
+#define BIT_SET_TDE_LEN_TH1(x, v)                                              \
+	(BIT_CLEAR_TDE_LEN_TH1(x) | BIT_TDE_LEN_TH1(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_TDE_LEN_TH				(Offset 0x11D4) */
+
+#define BIT_SHIFT_TXDMA_LEN_TH1 0
+#define BIT_MASK_TXDMA_LEN_TH1 0xffff
+#define BIT_TXDMA_LEN_TH1(x)                                                   \
+	(((x) & BIT_MASK_TXDMA_LEN_TH1) << BIT_SHIFT_TXDMA_LEN_TH1)
+#define BITS_TXDMA_LEN_TH1 (BIT_MASK_TXDMA_LEN_TH1 << BIT_SHIFT_TXDMA_LEN_TH1)
+#define BIT_CLEAR_TXDMA_LEN_TH1(x) ((x) & (~BITS_TXDMA_LEN_TH1))
+#define BIT_GET_TXDMA_LEN_TH1(x)                                               \
+	(((x) >> BIT_SHIFT_TXDMA_LEN_TH1) & BIT_MASK_TXDMA_LEN_TH1)
+#define BIT_SET_TXDMA_LEN_TH1(x, v)                                            \
+	(BIT_CLEAR_TXDMA_LEN_TH1(x) | BIT_TXDMA_LEN_TH1(v))
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_TXDMA_LEN_THRESHOLD			(Offset 0x11D4) */
+
+#define BIT_SHIFT_TDE_LEN_TH0 0
+#define BIT_MASK_TDE_LEN_TH0 0xffff
+#define BIT_TDE_LEN_TH0(x)                                                     \
+	(((x) & BIT_MASK_TDE_LEN_TH0) << BIT_SHIFT_TDE_LEN_TH0)
+#define BITS_TDE_LEN_TH0 (BIT_MASK_TDE_LEN_TH0 << BIT_SHIFT_TDE_LEN_TH0)
+#define BIT_CLEAR_TDE_LEN_TH0(x) ((x) & (~BITS_TDE_LEN_TH0))
+#define BIT_GET_TDE_LEN_TH0(x)                                                 \
+	(((x) >> BIT_SHIFT_TDE_LEN_TH0) & BIT_MASK_TDE_LEN_TH0)
+#define BIT_SET_TDE_LEN_TH0(x, v)                                              \
+	(BIT_CLEAR_TDE_LEN_TH0(x) | BIT_TDE_LEN_TH0(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_RDE_LEN_TH				(Offset 0x11D8) */
+
+#define BIT_SHIFT_RXDMA_LEN_TH0 16
+#define BIT_MASK_RXDMA_LEN_TH0 0xffff
+#define BIT_RXDMA_LEN_TH0(x)                                                   \
+	(((x) & BIT_MASK_RXDMA_LEN_TH0) << BIT_SHIFT_RXDMA_LEN_TH0)
+#define BITS_RXDMA_LEN_TH0 (BIT_MASK_RXDMA_LEN_TH0 << BIT_SHIFT_RXDMA_LEN_TH0)
+#define BIT_CLEAR_RXDMA_LEN_TH0(x) ((x) & (~BITS_RXDMA_LEN_TH0))
+#define BIT_GET_RXDMA_LEN_TH0(x)                                               \
+	(((x) >> BIT_SHIFT_RXDMA_LEN_TH0) & BIT_MASK_RXDMA_LEN_TH0)
+#define BIT_SET_RXDMA_LEN_TH0(x, v)                                            \
+	(BIT_CLEAR_RXDMA_LEN_TH0(x) | BIT_RXDMA_LEN_TH0(v))
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_RXDMA_LEN_THRESHOLD			(Offset 0x11D8) */
+
+#define BIT_SHIFT_RDE_LEN_TH1 16
+#define BIT_MASK_RDE_LEN_TH1 0xffff
+#define BIT_RDE_LEN_TH1(x)                                                     \
+	(((x) & BIT_MASK_RDE_LEN_TH1) << BIT_SHIFT_RDE_LEN_TH1)
+#define BITS_RDE_LEN_TH1 (BIT_MASK_RDE_LEN_TH1 << BIT_SHIFT_RDE_LEN_TH1)
+#define BIT_CLEAR_RDE_LEN_TH1(x) ((x) & (~BITS_RDE_LEN_TH1))
+#define BIT_GET_RDE_LEN_TH1(x)                                                 \
+	(((x) >> BIT_SHIFT_RDE_LEN_TH1) & BIT_MASK_RDE_LEN_TH1)
+#define BIT_SET_RDE_LEN_TH1(x, v)                                              \
+	(BIT_CLEAR_RDE_LEN_TH1(x) | BIT_RDE_LEN_TH1(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_RDE_LEN_TH				(Offset 0x11D8) */
+
+#define BIT_SHIFT_RXDMA_LEN_TH1 0
+#define BIT_MASK_RXDMA_LEN_TH1 0xffff
+#define BIT_RXDMA_LEN_TH1(x)                                                   \
+	(((x) & BIT_MASK_RXDMA_LEN_TH1) << BIT_SHIFT_RXDMA_LEN_TH1)
+#define BITS_RXDMA_LEN_TH1 (BIT_MASK_RXDMA_LEN_TH1 << BIT_SHIFT_RXDMA_LEN_TH1)
+#define BIT_CLEAR_RXDMA_LEN_TH1(x) ((x) & (~BITS_RXDMA_LEN_TH1))
+#define BIT_GET_RXDMA_LEN_TH1(x)                                               \
+	(((x) >> BIT_SHIFT_RXDMA_LEN_TH1) & BIT_MASK_RXDMA_LEN_TH1)
+#define BIT_SET_RXDMA_LEN_TH1(x, v)                                            \
+	(BIT_CLEAR_RXDMA_LEN_TH1(x) | BIT_RXDMA_LEN_TH1(v))
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_RXDMA_LEN_THRESHOLD			(Offset 0x11D8) */
+
+#define BIT_SHIFT_RDE_LEN_TH0 0
+#define BIT_MASK_RDE_LEN_TH0 0xffff
+#define BIT_RDE_LEN_TH0(x)                                                     \
+	(((x) & BIT_MASK_RDE_LEN_TH0) << BIT_SHIFT_RDE_LEN_TH0)
+#define BITS_RDE_LEN_TH0 (BIT_MASK_RDE_LEN_TH0 << BIT_SHIFT_RDE_LEN_TH0)
+#define BIT_CLEAR_RDE_LEN_TH0(x) ((x) & (~BITS_RDE_LEN_TH0))
+#define BIT_GET_RDE_LEN_TH0(x)                                                 \
+	(((x) >> BIT_SHIFT_RDE_LEN_TH0) & BIT_MASK_RDE_LEN_TH0)
+#define BIT_SET_RDE_LEN_TH0(x, v)                                              \
+	(BIT_CLEAR_RDE_LEN_TH0(x) | BIT_RDE_LEN_TH0(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_PCIE_EXEC_TIME			(Offset 0x11DC) */
+
+#define BIT_SHIFT_COUNTER_INTERVAL_SEL 16
+#define BIT_MASK_COUNTER_INTERVAL_SEL 0x3
+#define BIT_COUNTER_INTERVAL_SEL(x)                                            \
+	(((x) & BIT_MASK_COUNTER_INTERVAL_SEL)                                 \
+	 << BIT_SHIFT_COUNTER_INTERVAL_SEL)
+#define BITS_COUNTER_INTERVAL_SEL                                              \
+	(BIT_MASK_COUNTER_INTERVAL_SEL << BIT_SHIFT_COUNTER_INTERVAL_SEL)
+#define BIT_CLEAR_COUNTER_INTERVAL_SEL(x) ((x) & (~BITS_COUNTER_INTERVAL_SEL))
+#define BIT_GET_COUNTER_INTERVAL_SEL(x)                                        \
+	(((x) >> BIT_SHIFT_COUNTER_INTERVAL_SEL) &                             \
+	 BIT_MASK_COUNTER_INTERVAL_SEL)
+#define BIT_SET_COUNTER_INTERVAL_SEL(x, v)                                     \
+	(BIT_CLEAR_COUNTER_INTERVAL_SEL(x) | BIT_COUNTER_INTERVAL_SEL(v))
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_PCIE_EXEC_TIME_THRESHOLD		(Offset 0x11DC) */
+
+#define BIT_SHIFT_COUNT_INT_SEL 16
+#define BIT_MASK_COUNT_INT_SEL 0x3
+#define BIT_COUNT_INT_SEL(x)                                                   \
+	(((x) & BIT_MASK_COUNT_INT_SEL) << BIT_SHIFT_COUNT_INT_SEL)
+#define BITS_COUNT_INT_SEL (BIT_MASK_COUNT_INT_SEL << BIT_SHIFT_COUNT_INT_SEL)
+#define BIT_CLEAR_COUNT_INT_SEL(x) ((x) & (~BITS_COUNT_INT_SEL))
+#define BIT_GET_COUNT_INT_SEL(x)                                               \
+	(((x) >> BIT_SHIFT_COUNT_INT_SEL) & BIT_MASK_COUNT_INT_SEL)
+#define BIT_SET_COUNT_INT_SEL(x, v)                                            \
+	(BIT_CLEAR_COUNT_INT_SEL(x) | BIT_COUNT_INT_SEL(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_PCIE_EXEC_TIME			(Offset 0x11DC) */
+
+#define BIT_SHIFT_PCIE_TRANS_DATA_TH1 0
+#define BIT_MASK_PCIE_TRANS_DATA_TH1 0xffff
+#define BIT_PCIE_TRANS_DATA_TH1(x)                                             \
+	(((x) & BIT_MASK_PCIE_TRANS_DATA_TH1) << BIT_SHIFT_PCIE_TRANS_DATA_TH1)
+#define BITS_PCIE_TRANS_DATA_TH1                                               \
+	(BIT_MASK_PCIE_TRANS_DATA_TH1 << BIT_SHIFT_PCIE_TRANS_DATA_TH1)
+#define BIT_CLEAR_PCIE_TRANS_DATA_TH1(x) ((x) & (~BITS_PCIE_TRANS_DATA_TH1))
+#define BIT_GET_PCIE_TRANS_DATA_TH1(x)                                         \
+	(((x) >> BIT_SHIFT_PCIE_TRANS_DATA_TH1) & BIT_MASK_PCIE_TRANS_DATA_TH1)
+#define BIT_SET_PCIE_TRANS_DATA_TH1(x, v)                                      \
+	(BIT_CLEAR_PCIE_TRANS_DATA_TH1(x) | BIT_PCIE_TRANS_DATA_TH1(v))
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_PCIE_EXEC_TIME_THRESHOLD		(Offset 0x11DC) */
+
+#define BIT_SHIFT_EXEC_TIME_TH 0
+#define BIT_MASK_EXEC_TIME_TH 0xffff
+#define BIT_EXEC_TIME_TH(x)                                                    \
+	(((x) & BIT_MASK_EXEC_TIME_TH) << BIT_SHIFT_EXEC_TIME_TH)
+#define BITS_EXEC_TIME_TH (BIT_MASK_EXEC_TIME_TH << BIT_SHIFT_EXEC_TIME_TH)
+#define BIT_CLEAR_EXEC_TIME_TH(x) ((x) & (~BITS_EXEC_TIME_TH))
+#define BIT_GET_EXEC_TIME_TH(x)                                                \
+	(((x) >> BIT_SHIFT_EXEC_TIME_TH) & BIT_MASK_EXEC_TIME_TH)
+#define BIT_SET_EXEC_TIME_TH(x, v)                                             \
+	(BIT_CLEAR_EXEC_TIME_TH(x) | BIT_EXEC_TIME_TH(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_FT2IMR				(Offset 0x11E0) */
+
+#define BIT_PORT4_RX_UCMD1_UAPSD0_OK_INT_EN BIT(31)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FT2IMR				(Offset 0x11E0) */
+
+#define BIT_FS_CLI3_RX_UAPSDMD1_EN BIT(31)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_FT2IMR				(Offset 0x11E0) */
+
+#define BIT_PORT4_RX_UCMD0_UAPSD0_OK_INT_EN BIT(30)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FT2IMR				(Offset 0x11E0) */
+
+#define BIT_FS_CLI3_RX_UAPSDMD0_EN BIT(30)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_FT2IMR				(Offset 0x11E0) */
+
+#define BIT_PORT4_TRIPKT_OK_INT_EN BIT(29)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FT2IMR				(Offset 0x11E0) */
+
+#define BIT_FS_CLI3_TRIGGER_PKT_EN BIT(29)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_FT2IMR				(Offset 0x11E0) */
+
+#define BIT_PORT4_RX_EOSP_OK_INT_EN BIT(28)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FT2IMR				(Offset 0x11E0) */
+
+#define BIT_FS_CLI3_EOSP_INT_EN BIT(28)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_FT2IMR				(Offset 0x11E0) */
+
+#define BIT_PORT3_RX_UCMD1_UAPSD0_OK_INT_EN BIT(27)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FT2IMR				(Offset 0x11E0) */
+
+#define BIT_FS_CLI2_RX_UAPSDMD1_EN BIT(27)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_FT2IMR				(Offset 0x11E0) */
+
+#define BIT_PORT3_RX_UCMD0_UAPSD0_OK_INT_EN BIT(26)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FT2IMR				(Offset 0x11E0) */
+
+#define BIT_FS_CLI2_RX_UAPSDMD0_EN BIT(26)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_FT2IMR				(Offset 0x11E0) */
+
+#define BIT_PORT3_TRIPKT_OK_INT_EN BIT(25)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FT2IMR				(Offset 0x11E0) */
+
+#define BIT_FS_CLI2_TRIGGER_PKT_EN BIT(25)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_FT2IMR				(Offset 0x11E0) */
+
+#define BIT_PORT3_RX_EOSP_OK_INT_EN BIT(24)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FT2IMR				(Offset 0x11E0) */
+
+#define BIT_FS_CLI2_EOSP_INT_EN BIT(24)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_FT2IMR				(Offset 0x11E0) */
+
+#define BIT_PORT2_RX_UCMD1_UAPSD0_OK_INT_EN BIT(23)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FT2IMR				(Offset 0x11E0) */
+
+#define BIT_FS_CLI1_RX_UAPSDMD1_EN BIT(23)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_FT2IMR				(Offset 0x11E0) */
+
+#define BIT_PORT2_RX_UCMD0_UAPSD0_OK_INT_EN BIT(22)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FT2IMR				(Offset 0x11E0) */
+
+#define BIT_FS_CLI1_RX_UAPSDMD0_EN BIT(22)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_FT2IMR				(Offset 0x11E0) */
+
+#define BIT_PORT2_TRIPKT_OK_INT_EN BIT(21)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FT2IMR				(Offset 0x11E0) */
+
+#define BIT_FS_CLI1_TRIGGER_PKT_EN BIT(21)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_FT2IMR				(Offset 0x11E0) */
+
+#define BIT_PORT2_RX_EOSP_OK_INT_EN BIT(20)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FT2IMR				(Offset 0x11E0) */
+
+#define BIT_FS_CLI1_EOSP_INT_EN BIT(20)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_FT2IMR				(Offset 0x11E0) */
+
+#define BIT_PORT1_RX_UCMD1_UAPSD0_OK_INT_EN BIT(19)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FT2IMR				(Offset 0x11E0) */
+
+#define BIT_FS_CLI0_RX_UAPSDMD1_EN BIT(19)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_FT2IMR				(Offset 0x11E0) */
+
+#define BIT_PORT1_RX_UCMD0_UAPSD0_OK_INT_EN BIT(18)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FT2IMR				(Offset 0x11E0) */
+
+#define BIT_FS_CLI0_RX_UAPSDMD0_EN BIT(18)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_FT2IMR				(Offset 0x11E0) */
+
+#define BIT_PORT1_TRIPKT_OK_INT_EN BIT(17)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FT2IMR				(Offset 0x11E0) */
+
+#define BIT_FS_CLI0_TRIGGER_PKT_EN BIT(17)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_FT2IMR				(Offset 0x11E0) */
+
+#define BIT_PORT1_RX_EOSP_OK_INT_EN BIT(16)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FT2IMR				(Offset 0x11E0) */
+
+#define BIT_FS_CLI0_EOSP_INT_EN BIT(16)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_FT2IMR				(Offset 0x11E0) */
+
+#define BIT_NOA2_TSFT_BIT32_TOGGLE_INT_EN BIT(9)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FT2IMR				(Offset 0x11E0) */
+
+#define BIT_FS_TSF_BIT32_TOGGLE_P2P2_EN BIT(9)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_FT2IMR				(Offset 0x11E0) */
+
+#define BIT_NOA1_TSFT_BIT32_TOGGLE_INT_EN BIT(8)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FT2IMR				(Offset 0x11E0) */
+
+#define BIT_FS_TSF_BIT32_TOGGLE_P2P1_EN BIT(8)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_FT2IMR				(Offset 0x11E0) */
+
+#define BIT_PORT4_TX_NULL1_DONE_INT_EN BIT(7)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FT2IMR				(Offset 0x11E0) */
+
+#define BIT_FS_CLI3_TX_NULL1_INT_EN BIT(7)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_FT2IMR				(Offset 0x11E0) */
+
+#define BIT_PORT4_TX_NULL0_DONE_INT_EN BIT(6)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FT2IMR				(Offset 0x11E0) */
+
+#define BIT_FS_CLI3_TX_NULL0_INT_EN BIT(6)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_FT2IMR				(Offset 0x11E0) */
+
+#define BIT_PORT3_TX_NULL1_DONE_INT_EN BIT(5)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FT2IMR				(Offset 0x11E0) */
+
+#define BIT_FS_CLI2_TX_NULL1_INT_EN BIT(5)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_FT2IMR				(Offset 0x11E0) */
+
+#define BIT_PORT3_TX_NULL0_DONE_INT_EN BIT(4)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FT2IMR				(Offset 0x11E0) */
+
+#define BIT_FS_CLI2_TX_NULL0_INT_EN BIT(4)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_FT2IMR				(Offset 0x11E0) */
+
+#define BIT_PORT2_TX_NULL1_DONE_INT_EN BIT(3)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FT2IMR				(Offset 0x11E0) */
+
+#define BIT_FS_CLI1_TX_NULL1_INT_EN BIT(3)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_FT2IMR				(Offset 0x11E0) */
+
+#define BIT_PORT2_TX_NULL0_DONE_INT_EN BIT(2)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FT2IMR				(Offset 0x11E0) */
+
+#define BIT_FS_CLI1_TX_NULL0_INT_EN BIT(2)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_FT2IMR				(Offset 0x11E0) */
+
+#define BIT_PORT1_TX_NULL1_DONE_INT_EN BIT(1)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FT2IMR				(Offset 0x11E0) */
+
+#define BIT_FS_CLI0_TX_NULL1_INT_EN BIT(1)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_FT2IMR				(Offset 0x11E0) */
+
+#define BIT_PORT1_TX_NULL0_DONE_INT_EN BIT(0)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FT2IMR				(Offset 0x11E0) */
+
+#define BIT_FS_CLI0_TX_NULL0_INT_EN BIT(0)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_FT2ISR				(Offset 0x11E4) */
+
+#define BIT_PORT4_RX_UCMD1_UAPSD0_OK_INT BIT(31)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FT2ISR				(Offset 0x11E4) */
+
+#define BIT_FS_CLI3_RX_UAPSDMD1_INT BIT(31)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_FT2ISR				(Offset 0x11E4) */
+
+#define BIT_PORT4_RX_UCMD0_UAPSD0_OK_INT BIT(30)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FT2ISR				(Offset 0x11E4) */
+
+#define BIT_FS_CLI3_RX_UAPSDMD0_INT BIT(30)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_FT2ISR				(Offset 0x11E4) */
+
+#define BIT_PORT4_TRIPKT_OK_INT BIT(29)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FT2ISR				(Offset 0x11E4) */
+
+#define BIT_FS_CLI3_TRIGGER_PKT_INT BIT(29)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_FT2ISR				(Offset 0x11E4) */
+
+#define BIT_PORT4_RX_EOSP_OK_INT BIT(28)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FT2ISR				(Offset 0x11E4) */
+
+#define BIT_FS_CLI3_EOSP_INT BIT(28)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_FT2ISR				(Offset 0x11E4) */
+
+#define BIT_PORT3_RX_UCMD1_UAPSD0_OK_INT BIT(27)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FT2ISR				(Offset 0x11E4) */
+
+#define BIT_FS_CLI2_RX_UAPSDMD1_INT BIT(27)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_FT2ISR				(Offset 0x11E4) */
+
+#define BIT_PORT3_RX_UCMD0_UAPSD0_OK_INT BIT(26)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FT2ISR				(Offset 0x11E4) */
+
+#define BIT_FS_CLI2_RX_UAPSDMD0_INT BIT(26)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_FT2ISR				(Offset 0x11E4) */
+
+#define BIT_PORT3_TRIPKT_OK_INT BIT(25)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FT2ISR				(Offset 0x11E4) */
+
+#define BIT_FS_CLI2_TRIGGER_PKT_INT BIT(25)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_FT2ISR				(Offset 0x11E4) */
+
+#define BIT_PORT3_RX_EOSP_OK_INT BIT(24)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FT2ISR				(Offset 0x11E4) */
+
+#define BIT_FS_CLI2_EOSP_INT BIT(24)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_FT2ISR				(Offset 0x11E4) */
+
+#define BIT_PORT2_RX_UCMD1_UAPSD0_OK_INT BIT(23)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FT2ISR				(Offset 0x11E4) */
+
+#define BIT_FS_CLI1_RX_UAPSDMD1_INT BIT(23)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_FT2ISR				(Offset 0x11E4) */
+
+#define BIT_PORT2_RX_UCMD0_UAPSD0_OK_INT BIT(22)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FT2ISR				(Offset 0x11E4) */
+
+#define BIT_FS_CLI1_RX_UAPSDMD0_INT BIT(22)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_FT2ISR				(Offset 0x11E4) */
+
+#define BIT_PORT2_TRIPKT_OK_INT BIT(21)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FT2ISR				(Offset 0x11E4) */
+
+#define BIT_FS_CLI1_TRIGGER_PKT_INT BIT(21)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_FT2ISR				(Offset 0x11E4) */
+
+#define BIT_PORT2_RX_EOSP_OK_INT BIT(20)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FT2ISR				(Offset 0x11E4) */
+
+#define BIT_FS_CLI1_EOSP_INT BIT(20)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_FT2ISR				(Offset 0x11E4) */
+
+#define BIT_PORT1_RX_UCMD1_UAPSD0_OK_INT BIT(19)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FT2ISR				(Offset 0x11E4) */
+
+#define BIT_FS_CLI0_RX_UAPSDMD1_INT BIT(19)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_FT2ISR				(Offset 0x11E4) */
+
+#define BIT_PORT1_RX_UCMD0_UAPSD0_OK_INT BIT(18)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FT2ISR				(Offset 0x11E4) */
+
+#define BIT_FS_CLI0_RX_UAPSDMD0_INT BIT(18)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_FT2ISR				(Offset 0x11E4) */
+
+#define BIT_PORT1_TRIPKT_OK_INT BIT(17)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FT2ISR				(Offset 0x11E4) */
+
+#define BIT_FS_CLI0_TRIGGER_PKT_INT BIT(17)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_FT2ISR				(Offset 0x11E4) */
+
+#define BIT_PORT1_RX_EOSP_OK_INT BIT(16)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FT2ISR				(Offset 0x11E4) */
+
+#define BIT_FS_CLI0_EOSP_INT BIT(16)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_FT2ISR				(Offset 0x11E4) */
+
+#define BIT_NOA2_TSFT_BIT32_TOGGLE_INT BIT(9)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FT2ISR				(Offset 0x11E4) */
+
+#define BIT_FS_TSF_BIT32_TOGGLE_P2P2_INT BIT(9)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_FT2ISR				(Offset 0x11E4) */
+
+#define BIT_NOA1_TSFT_BIT32_TOGGLE_INT BIT(8)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FT2ISR				(Offset 0x11E4) */
+
+#define BIT_FS_TSF_BIT32_TOGGLE_P2P1_INT BIT(8)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_FT2ISR				(Offset 0x11E4) */
+
+#define BIT_PORT4_TX_NULL1_DONE_INT BIT(7)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FT2ISR				(Offset 0x11E4) */
+
+#define BIT_FS_CLI3_TX_NULL1_INT BIT(7)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_FT2ISR				(Offset 0x11E4) */
+
+#define BIT_PORT4_TX_NULL0_DONE_INT BIT(6)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FT2ISR				(Offset 0x11E4) */
+
+#define BIT_FS_CLI3_TX_NULL0_INT BIT(6)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_FT2ISR				(Offset 0x11E4) */
+
+#define BIT_PORT3_TX_NULL1_DONE_INT BIT(5)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FT2ISR				(Offset 0x11E4) */
+
+#define BIT_FS_CLI2_TX_NULL1_INT BIT(5)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_FT2ISR				(Offset 0x11E4) */
+
+#define BIT_PORT3_TX_NULL0_DONE_INT BIT(4)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FT2ISR				(Offset 0x11E4) */
+
+#define BIT_FS_CLI2_TX_NULL0_INT BIT(4)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_FT2ISR				(Offset 0x11E4) */
+
+#define BIT_PORT2_TX_NULL1_DONE_INT BIT(3)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FT2ISR				(Offset 0x11E4) */
+
+#define BIT_FS_CLI1_TX_NULL1_INT BIT(3)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_FT2ISR				(Offset 0x11E4) */
+
+#define BIT_PORT2_TX_NULL0_DONE_INT BIT(2)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FT2ISR				(Offset 0x11E4) */
+
+#define BIT_FS_CLI1_TX_NULL0_INT BIT(2)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_FT2ISR				(Offset 0x11E4) */
+
+#define BIT_PORT1_TX_NULL1_DONE_INT BIT(1)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FT2ISR				(Offset 0x11E4) */
+
+#define BIT_FS_CLI0_TX_NULL1_INT BIT(1)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_FT2ISR				(Offset 0x11E4) */
+
+#define BIT_PORT1_TX_NULL0_DONE_INT BIT(0)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FT2ISR				(Offset 0x11E4) */
+
+#define BIT_FS_CLI0_TX_NULL0_INT BIT(0)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_MSG2				(Offset 0x11F0) */
+
+#define BIT_SHIFT_FW_MSG2 0
+#define BIT_MASK_FW_MSG2 0xffffffffL
+#define BIT_FW_MSG2(x) (((x) & BIT_MASK_FW_MSG2) << BIT_SHIFT_FW_MSG2)
+#define BITS_FW_MSG2 (BIT_MASK_FW_MSG2 << BIT_SHIFT_FW_MSG2)
+#define BIT_CLEAR_FW_MSG2(x) ((x) & (~BITS_FW_MSG2))
+#define BIT_GET_FW_MSG2(x) (((x) >> BIT_SHIFT_FW_MSG2) & BIT_MASK_FW_MSG2)
+#define BIT_SET_FW_MSG2(x, v) (BIT_CLEAR_FW_MSG2(x) | BIT_FW_MSG2(v))
+
+/* 2 REG_MSG3				(Offset 0x11F4) */
+
+#define BIT_SHIFT_FW_MSG3 0
+#define BIT_MASK_FW_MSG3 0xffffffffL
+#define BIT_FW_MSG3(x) (((x) & BIT_MASK_FW_MSG3) << BIT_SHIFT_FW_MSG3)
+#define BITS_FW_MSG3 (BIT_MASK_FW_MSG3 << BIT_SHIFT_FW_MSG3)
+#define BIT_CLEAR_FW_MSG3(x) ((x) & (~BITS_FW_MSG3))
+#define BIT_GET_FW_MSG3(x) (((x) >> BIT_SHIFT_FW_MSG3) & BIT_MASK_FW_MSG3)
+#define BIT_SET_FW_MSG3(x, v) (BIT_CLEAR_FW_MSG3(x) | BIT_FW_MSG3(v))
+
+/* 2 REG_MSG4				(Offset 0x11F8) */
+
+#define BIT_SHIFT_FW_MSG4 0
+#define BIT_MASK_FW_MSG4 0xffffffffL
+#define BIT_FW_MSG4(x) (((x) & BIT_MASK_FW_MSG4) << BIT_SHIFT_FW_MSG4)
+#define BITS_FW_MSG4 (BIT_MASK_FW_MSG4 << BIT_SHIFT_FW_MSG4)
+#define BIT_CLEAR_FW_MSG4(x) ((x) & (~BITS_FW_MSG4))
+#define BIT_GET_FW_MSG4(x) (((x) >> BIT_SHIFT_FW_MSG4) & BIT_MASK_FW_MSG4)
+#define BIT_SET_FW_MSG4(x, v) (BIT_CLEAR_FW_MSG4(x) | BIT_FW_MSG4(v))
+
+/* 2 REG_MSG5				(Offset 0x11FC) */
+
+#define BIT_SHIFT_FW_MSG5 0
+#define BIT_MASK_FW_MSG5 0xffffffffL
+#define BIT_FW_MSG5(x) (((x) & BIT_MASK_FW_MSG5) << BIT_SHIFT_FW_MSG5)
+#define BITS_FW_MSG5 (BIT_MASK_FW_MSG5 << BIT_SHIFT_FW_MSG5)
+#define BIT_CLEAR_FW_MSG5(x) ((x) & (~BITS_FW_MSG5))
+#define BIT_GET_FW_MSG5(x) (((x) >> BIT_SHIFT_FW_MSG5) & BIT_MASK_FW_MSG5)
+#define BIT_SET_FW_MSG5(x, v) (BIT_CLEAR_FW_MSG5(x) | BIT_FW_MSG5(v))
+
+/* 2 REG_DDMA_CH0SA				(Offset 0x1200) */
+
+#define BIT_SHIFT_DDMACH0_SA 0
+#define BIT_MASK_DDMACH0_SA 0xffffffffL
+#define BIT_DDMACH0_SA(x) (((x) & BIT_MASK_DDMACH0_SA) << BIT_SHIFT_DDMACH0_SA)
+#define BITS_DDMACH0_SA (BIT_MASK_DDMACH0_SA << BIT_SHIFT_DDMACH0_SA)
+#define BIT_CLEAR_DDMACH0_SA(x) ((x) & (~BITS_DDMACH0_SA))
+#define BIT_GET_DDMACH0_SA(x)                                                  \
+	(((x) >> BIT_SHIFT_DDMACH0_SA) & BIT_MASK_DDMACH0_SA)
+#define BIT_SET_DDMACH0_SA(x, v) (BIT_CLEAR_DDMACH0_SA(x) | BIT_DDMACH0_SA(v))
+
+/* 2 REG_DDMA_CH0DA				(Offset 0x1204) */
+
+#define BIT_SHIFT_DDMACH0_DA 0
+#define BIT_MASK_DDMACH0_DA 0xffffffffL
+#define BIT_DDMACH0_DA(x) (((x) & BIT_MASK_DDMACH0_DA) << BIT_SHIFT_DDMACH0_DA)
+#define BITS_DDMACH0_DA (BIT_MASK_DDMACH0_DA << BIT_SHIFT_DDMACH0_DA)
+#define BIT_CLEAR_DDMACH0_DA(x) ((x) & (~BITS_DDMACH0_DA))
+#define BIT_GET_DDMACH0_DA(x)                                                  \
+	(((x) >> BIT_SHIFT_DDMACH0_DA) & BIT_MASK_DDMACH0_DA)
+#define BIT_SET_DDMACH0_DA(x, v) (BIT_CLEAR_DDMACH0_DA(x) | BIT_DDMACH0_DA(v))
+
+/* 2 REG_DDMA_CH0CTRL			(Offset 0x1208) */
+
+#define BIT_DDMACH0_OWN BIT(31)
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+/* 2 REG_DDMA_CH0CTRL			(Offset 0x1208) */
+
+#define BIT_DDMACH0_ERR_MON BIT(30)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_DDMA_CH0CTRL			(Offset 0x1208) */
+
+#define BIT_DDMACH0_IDMEM_ERR BIT(30)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_DDMA_CH0CTRL			(Offset 0x1208) */
+
+#define BIT_DDMACH0_CHKSUM_EN BIT(29)
+#define BIT_DDMACH0_DA_W_DISABLE BIT(28)
+#define BIT_DDMACH0_CHKSUM_STS BIT(27)
+#define BIT_DDMACH0_DDMA_MODE BIT(26)
+#define BIT_DDMACH0_RESET_CHKSUM_STS BIT(25)
+#define BIT_DDMACH0_CHKSUM_CONT BIT(24)
+
+#define BIT_SHIFT_DDMACH0_DLEN 0
+#define BIT_MASK_DDMACH0_DLEN 0x3ffff
+#define BIT_DDMACH0_DLEN(x)                                                    \
+	(((x) & BIT_MASK_DDMACH0_DLEN) << BIT_SHIFT_DDMACH0_DLEN)
+#define BITS_DDMACH0_DLEN (BIT_MASK_DDMACH0_DLEN << BIT_SHIFT_DDMACH0_DLEN)
+#define BIT_CLEAR_DDMACH0_DLEN(x) ((x) & (~BITS_DDMACH0_DLEN))
+#define BIT_GET_DDMACH0_DLEN(x)                                                \
+	(((x) >> BIT_SHIFT_DDMACH0_DLEN) & BIT_MASK_DDMACH0_DLEN)
+#define BIT_SET_DDMACH0_DLEN(x, v)                                             \
+	(BIT_CLEAR_DDMACH0_DLEN(x) | BIT_DDMACH0_DLEN(v))
+
+/* 2 REG_DDMA_CH1SA				(Offset 0x1210) */
+
+#define BIT_SHIFT_DDMACH1_SA 0
+#define BIT_MASK_DDMACH1_SA 0xffffffffL
+#define BIT_DDMACH1_SA(x) (((x) & BIT_MASK_DDMACH1_SA) << BIT_SHIFT_DDMACH1_SA)
+#define BITS_DDMACH1_SA (BIT_MASK_DDMACH1_SA << BIT_SHIFT_DDMACH1_SA)
+#define BIT_CLEAR_DDMACH1_SA(x) ((x) & (~BITS_DDMACH1_SA))
+#define BIT_GET_DDMACH1_SA(x)                                                  \
+	(((x) >> BIT_SHIFT_DDMACH1_SA) & BIT_MASK_DDMACH1_SA)
+#define BIT_SET_DDMACH1_SA(x, v) (BIT_CLEAR_DDMACH1_SA(x) | BIT_DDMACH1_SA(v))
+
+/* 2 REG_DDMA_CH1DA				(Offset 0x1214) */
+
+#define BIT_SHIFT_DDMACH1_DA 0
+#define BIT_MASK_DDMACH1_DA 0xffffffffL
+#define BIT_DDMACH1_DA(x) (((x) & BIT_MASK_DDMACH1_DA) << BIT_SHIFT_DDMACH1_DA)
+#define BITS_DDMACH1_DA (BIT_MASK_DDMACH1_DA << BIT_SHIFT_DDMACH1_DA)
+#define BIT_CLEAR_DDMACH1_DA(x) ((x) & (~BITS_DDMACH1_DA))
+#define BIT_GET_DDMACH1_DA(x)                                                  \
+	(((x) >> BIT_SHIFT_DDMACH1_DA) & BIT_MASK_DDMACH1_DA)
+#define BIT_SET_DDMACH1_DA(x, v) (BIT_CLEAR_DDMACH1_DA(x) | BIT_DDMACH1_DA(v))
+
+/* 2 REG_DDMA_CH1CTRL			(Offset 0x1218) */
+
+#define BIT_DDMACH1_OWN BIT(31)
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+/* 2 REG_DDMA_CH1CTRL			(Offset 0x1218) */
+
+#define BIT_DDMACH1_ERR_MON BIT(30)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_DDMA_CH1CTRL			(Offset 0x1218) */
+
+#define BIT_DDMACH1_IDMEM_ERR BIT(30)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_DDMA_CH1CTRL			(Offset 0x1218) */
+
+#define BIT_DDMACH1_CHKSUM_EN BIT(29)
+#define BIT_DDMACH1_DA_W_DISABLE BIT(28)
+#define BIT_DDMACH1_CHKSUM_STS BIT(27)
+#define BIT_DDMACH1_DDMA_MODE BIT(26)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT)
+
+/* 2 REG_DDMA_CH1CTRL			(Offset 0x1218) */
+
+#define BIT_DDMACH1_RESET_CHKSUM_STS BIT(25)
+#define BIT_DDMACH1_CHKSUM_CONT BIT(24)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_DDMA_CH1CTRL			(Offset 0x1218) */
+
+#define BIT_SHIFT_DDMACH1_DLEN 0
+#define BIT_MASK_DDMACH1_DLEN 0x3ffff
+#define BIT_DDMACH1_DLEN(x)                                                    \
+	(((x) & BIT_MASK_DDMACH1_DLEN) << BIT_SHIFT_DDMACH1_DLEN)
+#define BITS_DDMACH1_DLEN (BIT_MASK_DDMACH1_DLEN << BIT_SHIFT_DDMACH1_DLEN)
+#define BIT_CLEAR_DDMACH1_DLEN(x) ((x) & (~BITS_DDMACH1_DLEN))
+#define BIT_GET_DDMACH1_DLEN(x)                                                \
+	(((x) >> BIT_SHIFT_DDMACH1_DLEN) & BIT_MASK_DDMACH1_DLEN)
+#define BIT_SET_DDMACH1_DLEN(x, v)                                             \
+	(BIT_CLEAR_DDMACH1_DLEN(x) | BIT_DDMACH1_DLEN(v))
+
+/* 2 REG_DDMA_CH2SA				(Offset 0x1220) */
+
+#define BIT_SHIFT_DDMACH2_SA 0
+#define BIT_MASK_DDMACH2_SA 0xffffffffL
+#define BIT_DDMACH2_SA(x) (((x) & BIT_MASK_DDMACH2_SA) << BIT_SHIFT_DDMACH2_SA)
+#define BITS_DDMACH2_SA (BIT_MASK_DDMACH2_SA << BIT_SHIFT_DDMACH2_SA)
+#define BIT_CLEAR_DDMACH2_SA(x) ((x) & (~BITS_DDMACH2_SA))
+#define BIT_GET_DDMACH2_SA(x)                                                  \
+	(((x) >> BIT_SHIFT_DDMACH2_SA) & BIT_MASK_DDMACH2_SA)
+#define BIT_SET_DDMACH2_SA(x, v) (BIT_CLEAR_DDMACH2_SA(x) | BIT_DDMACH2_SA(v))
+
+/* 2 REG_DDMA_CH2DA				(Offset 0x1224) */
+
+#define BIT_SHIFT_DDMACH2_DA 0
+#define BIT_MASK_DDMACH2_DA 0xffffffffL
+#define BIT_DDMACH2_DA(x) (((x) & BIT_MASK_DDMACH2_DA) << BIT_SHIFT_DDMACH2_DA)
+#define BITS_DDMACH2_DA (BIT_MASK_DDMACH2_DA << BIT_SHIFT_DDMACH2_DA)
+#define BIT_CLEAR_DDMACH2_DA(x) ((x) & (~BITS_DDMACH2_DA))
+#define BIT_GET_DDMACH2_DA(x)                                                  \
+	(((x) >> BIT_SHIFT_DDMACH2_DA) & BIT_MASK_DDMACH2_DA)
+#define BIT_SET_DDMACH2_DA(x, v) (BIT_CLEAR_DDMACH2_DA(x) | BIT_DDMACH2_DA(v))
+
+/* 2 REG_DDMA_CH2CTRL			(Offset 0x1228) */
+
+#define BIT_DDMACH2_OWN BIT(31)
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+/* 2 REG_DDMA_CH2CTRL			(Offset 0x1228) */
+
+#define BIT_DDMACH2_ERR_MON BIT(30)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_DDMA_CH2CTRL			(Offset 0x1228) */
+
+#define BIT_DDMACH2_IDMEM_ERR BIT(30)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_DDMA_CH2CTRL			(Offset 0x1228) */
+
+#define BIT_DDMACH2_CHKSUM_EN BIT(29)
+#define BIT_DDMACH2_DA_W_DISABLE BIT(28)
+#define BIT_DDMACH2_CHKSUM_STS BIT(27)
+#define BIT_DDMACH2_DDMA_MODE BIT(26)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT)
+
+/* 2 REG_DDMA_CH2CTRL			(Offset 0x1228) */
+
+#define BIT_DDMACH2_RESET_CHKSUM_STS BIT(25)
+#define BIT_DDMACH2_CHKSUM_CONT BIT(24)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_DDMA_CH2CTRL			(Offset 0x1228) */
+
+#define BIT_SHIFT_DDMACH2_DLEN 0
+#define BIT_MASK_DDMACH2_DLEN 0x3ffff
+#define BIT_DDMACH2_DLEN(x)                                                    \
+	(((x) & BIT_MASK_DDMACH2_DLEN) << BIT_SHIFT_DDMACH2_DLEN)
+#define BITS_DDMACH2_DLEN (BIT_MASK_DDMACH2_DLEN << BIT_SHIFT_DDMACH2_DLEN)
+#define BIT_CLEAR_DDMACH2_DLEN(x) ((x) & (~BITS_DDMACH2_DLEN))
+#define BIT_GET_DDMACH2_DLEN(x)                                                \
+	(((x) >> BIT_SHIFT_DDMACH2_DLEN) & BIT_MASK_DDMACH2_DLEN)
+#define BIT_SET_DDMACH2_DLEN(x, v)                                             \
+	(BIT_CLEAR_DDMACH2_DLEN(x) | BIT_DDMACH2_DLEN(v))
+
+/* 2 REG_DDMA_CH3SA				(Offset 0x1230) */
+
+#define BIT_SHIFT_DDMACH3_SA 0
+#define BIT_MASK_DDMACH3_SA 0xffffffffL
+#define BIT_DDMACH3_SA(x) (((x) & BIT_MASK_DDMACH3_SA) << BIT_SHIFT_DDMACH3_SA)
+#define BITS_DDMACH3_SA (BIT_MASK_DDMACH3_SA << BIT_SHIFT_DDMACH3_SA)
+#define BIT_CLEAR_DDMACH3_SA(x) ((x) & (~BITS_DDMACH3_SA))
+#define BIT_GET_DDMACH3_SA(x)                                                  \
+	(((x) >> BIT_SHIFT_DDMACH3_SA) & BIT_MASK_DDMACH3_SA)
+#define BIT_SET_DDMACH3_SA(x, v) (BIT_CLEAR_DDMACH3_SA(x) | BIT_DDMACH3_SA(v))
+
+/* 2 REG_DDMA_CH3DA				(Offset 0x1234) */
+
+#define BIT_SHIFT_DDMACH3_DA 0
+#define BIT_MASK_DDMACH3_DA 0xffffffffL
+#define BIT_DDMACH3_DA(x) (((x) & BIT_MASK_DDMACH3_DA) << BIT_SHIFT_DDMACH3_DA)
+#define BITS_DDMACH3_DA (BIT_MASK_DDMACH3_DA << BIT_SHIFT_DDMACH3_DA)
+#define BIT_CLEAR_DDMACH3_DA(x) ((x) & (~BITS_DDMACH3_DA))
+#define BIT_GET_DDMACH3_DA(x)                                                  \
+	(((x) >> BIT_SHIFT_DDMACH3_DA) & BIT_MASK_DDMACH3_DA)
+#define BIT_SET_DDMACH3_DA(x, v) (BIT_CLEAR_DDMACH3_DA(x) | BIT_DDMACH3_DA(v))
+
+/* 2 REG_DDMA_CH3CTRL			(Offset 0x1238) */
+
+#define BIT_DDMACH3_OWN BIT(31)
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+/* 2 REG_DDMA_CH3CTRL			(Offset 0x1238) */
+
+#define BIT_DDMACH3_ERR_MON BIT(30)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_DDMA_CH3CTRL			(Offset 0x1238) */
+
+#define BIT_DDMACH3_IDMEM_ERR BIT(30)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_DDMA_CH3CTRL			(Offset 0x1238) */
+
+#define BIT_DDMACH3_CHKSUM_EN BIT(29)
+#define BIT_DDMACH3_DA_W_DISABLE BIT(28)
+#define BIT_DDMACH3_CHKSUM_STS BIT(27)
+#define BIT_DDMACH3_DDMA_MODE BIT(26)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT)
+
+/* 2 REG_DDMA_CH3CTRL			(Offset 0x1238) */
+
+#define BIT_DDMACH3_RESET_CHKSUM_STS BIT(25)
+#define BIT_DDMACH3_CHKSUM_CONT BIT(24)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_DDMA_CH3CTRL			(Offset 0x1238) */
+
+#define BIT_SHIFT_DDMACH3_DLEN 0
+#define BIT_MASK_DDMACH3_DLEN 0x3ffff
+#define BIT_DDMACH3_DLEN(x)                                                    \
+	(((x) & BIT_MASK_DDMACH3_DLEN) << BIT_SHIFT_DDMACH3_DLEN)
+#define BITS_DDMACH3_DLEN (BIT_MASK_DDMACH3_DLEN << BIT_SHIFT_DDMACH3_DLEN)
+#define BIT_CLEAR_DDMACH3_DLEN(x) ((x) & (~BITS_DDMACH3_DLEN))
+#define BIT_GET_DDMACH3_DLEN(x)                                                \
+	(((x) >> BIT_SHIFT_DDMACH3_DLEN) & BIT_MASK_DDMACH3_DLEN)
+#define BIT_SET_DDMACH3_DLEN(x, v)                                             \
+	(BIT_CLEAR_DDMACH3_DLEN(x) | BIT_DDMACH3_DLEN(v))
+
+/* 2 REG_DDMA_CH4SA				(Offset 0x1240) */
+
+#define BIT_SHIFT_DDMACH4_SA 0
+#define BIT_MASK_DDMACH4_SA 0xffffffffL
+#define BIT_DDMACH4_SA(x) (((x) & BIT_MASK_DDMACH4_SA) << BIT_SHIFT_DDMACH4_SA)
+#define BITS_DDMACH4_SA (BIT_MASK_DDMACH4_SA << BIT_SHIFT_DDMACH4_SA)
+#define BIT_CLEAR_DDMACH4_SA(x) ((x) & (~BITS_DDMACH4_SA))
+#define BIT_GET_DDMACH4_SA(x)                                                  \
+	(((x) >> BIT_SHIFT_DDMACH4_SA) & BIT_MASK_DDMACH4_SA)
+#define BIT_SET_DDMACH4_SA(x, v) (BIT_CLEAR_DDMACH4_SA(x) | BIT_DDMACH4_SA(v))
+
+/* 2 REG_DDMA_CH4DA				(Offset 0x1244) */
+
+#define BIT_SHIFT_DDMACH4_DA 0
+#define BIT_MASK_DDMACH4_DA 0xffffffffL
+#define BIT_DDMACH4_DA(x) (((x) & BIT_MASK_DDMACH4_DA) << BIT_SHIFT_DDMACH4_DA)
+#define BITS_DDMACH4_DA (BIT_MASK_DDMACH4_DA << BIT_SHIFT_DDMACH4_DA)
+#define BIT_CLEAR_DDMACH4_DA(x) ((x) & (~BITS_DDMACH4_DA))
+#define BIT_GET_DDMACH4_DA(x)                                                  \
+	(((x) >> BIT_SHIFT_DDMACH4_DA) & BIT_MASK_DDMACH4_DA)
+#define BIT_SET_DDMACH4_DA(x, v) (BIT_CLEAR_DDMACH4_DA(x) | BIT_DDMACH4_DA(v))
+
+/* 2 REG_DDMA_CH4CTRL			(Offset 0x1248) */
+
+#define BIT_DDMACH4_OWN BIT(31)
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+/* 2 REG_DDMA_CH4CTRL			(Offset 0x1248) */
+
+#define BIT_DDMACH4_ERR_MON BIT(30)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_DDMA_CH4CTRL			(Offset 0x1248) */
+
+#define BIT_DDMACH4_IDMEM_ERR BIT(30)
+#define BIT_DDMACH5_IDMEM_ERR BIT(30)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_DDMA_CH4CTRL			(Offset 0x1248) */
+
+#define BIT_DDMACH4_CHKSUM_EN BIT(29)
+#define BIT_DDMACH4_DA_W_DISABLE BIT(28)
+#define BIT_DDMACH4_CHKSUM_STS BIT(27)
+#define BIT_DDMACH4_DDMA_MODE BIT(26)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT)
+
+/* 2 REG_DDMA_CH4CTRL			(Offset 0x1248) */
+
+#define BIT_DDMACH4_RESET_CHKSUM_STS BIT(25)
+#define BIT_DDMACH5_RESET_CHKSUM_STS BIT(25)
+#define BIT_DDMACH4_CHKSUM_CONT BIT(24)
+#define BIT_DDMACH5_CHKSUM_CONT BIT(24)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_DDMA_CH4CTRL			(Offset 0x1248) */
+
+#define BIT_SHIFT_DDMACH4_DLEN 0
+#define BIT_MASK_DDMACH4_DLEN 0x3ffff
+#define BIT_DDMACH4_DLEN(x)                                                    \
+	(((x) & BIT_MASK_DDMACH4_DLEN) << BIT_SHIFT_DDMACH4_DLEN)
+#define BITS_DDMACH4_DLEN (BIT_MASK_DDMACH4_DLEN << BIT_SHIFT_DDMACH4_DLEN)
+#define BIT_CLEAR_DDMACH4_DLEN(x) ((x) & (~BITS_DDMACH4_DLEN))
+#define BIT_GET_DDMACH4_DLEN(x)                                                \
+	(((x) >> BIT_SHIFT_DDMACH4_DLEN) & BIT_MASK_DDMACH4_DLEN)
+#define BIT_SET_DDMACH4_DLEN(x, v)                                             \
+	(BIT_CLEAR_DDMACH4_DLEN(x) | BIT_DDMACH4_DLEN(v))
+
+/* 2 REG_DDMA_CH5SA				(Offset 0x1250) */
+
+#define BIT_SHIFT_DDMACH5_SA 0
+#define BIT_MASK_DDMACH5_SA 0xffffffffL
+#define BIT_DDMACH5_SA(x) (((x) & BIT_MASK_DDMACH5_SA) << BIT_SHIFT_DDMACH5_SA)
+#define BITS_DDMACH5_SA (BIT_MASK_DDMACH5_SA << BIT_SHIFT_DDMACH5_SA)
+#define BIT_CLEAR_DDMACH5_SA(x) ((x) & (~BITS_DDMACH5_SA))
+#define BIT_GET_DDMACH5_SA(x)                                                  \
+	(((x) >> BIT_SHIFT_DDMACH5_SA) & BIT_MASK_DDMACH5_SA)
+#define BIT_SET_DDMACH5_SA(x, v) (BIT_CLEAR_DDMACH5_SA(x) | BIT_DDMACH5_SA(v))
+
+/* 2 REG_DDMA_CH5DA				(Offset 0x1254) */
+
+#define BIT_DDMACH5_OWN BIT(31)
+#define BIT_DDMACH5_CHKSUM_EN BIT(29)
+#define BIT_DDMACH5_DA_W_DISABLE BIT(28)
+#define BIT_DDMACH5_CHKSUM_STS BIT(27)
+#define BIT_DDMACH5_DDMA_MODE BIT(26)
+
+#define BIT_SHIFT_DDMACH5_DA 0
+#define BIT_MASK_DDMACH5_DA 0xffffffffL
+#define BIT_DDMACH5_DA(x) (((x) & BIT_MASK_DDMACH5_DA) << BIT_SHIFT_DDMACH5_DA)
+#define BITS_DDMACH5_DA (BIT_MASK_DDMACH5_DA << BIT_SHIFT_DDMACH5_DA)
+#define BIT_CLEAR_DDMACH5_DA(x) ((x) & (~BITS_DDMACH5_DA))
+#define BIT_GET_DDMACH5_DA(x)                                                  \
+	(((x) >> BIT_SHIFT_DDMACH5_DA) & BIT_MASK_DDMACH5_DA)
+#define BIT_SET_DDMACH5_DA(x, v) (BIT_CLEAR_DDMACH5_DA(x) | BIT_DDMACH5_DA(v))
+
+#define BIT_SHIFT_DDMACH5_DLEN 0
+#define BIT_MASK_DDMACH5_DLEN 0x3ffff
+#define BIT_DDMACH5_DLEN(x)                                                    \
+	(((x) & BIT_MASK_DDMACH5_DLEN) << BIT_SHIFT_DDMACH5_DLEN)
+#define BITS_DDMACH5_DLEN (BIT_MASK_DDMACH5_DLEN << BIT_SHIFT_DDMACH5_DLEN)
+#define BIT_CLEAR_DDMACH5_DLEN(x) ((x) & (~BITS_DDMACH5_DLEN))
+#define BIT_GET_DDMACH5_DLEN(x)                                                \
+	(((x) >> BIT_SHIFT_DDMACH5_DLEN) & BIT_MASK_DDMACH5_DLEN)
+#define BIT_SET_DDMACH5_DLEN(x, v)                                             \
+	(BIT_CLEAR_DDMACH5_DLEN(x) | BIT_DDMACH5_DLEN(v))
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+/* 2 REG_REG_DDMA_CH5CTRL			(Offset 0x1258) */
+
+#define BIT_DDMACH5_ERR_MON BIT(30)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_DDMA_INT_MSK			(Offset 0x12E0) */
+
+#define BIT_DDMACH5_MSK BIT(5)
+#define BIT_DDMACH4_MSK BIT(4)
+#define BIT_DDMACH3_MSK BIT(3)
+#define BIT_DDMACH2_MSK BIT(2)
+#define BIT_DDMACH1_MSK BIT(1)
+#define BIT_DDMACH0_MSK BIT(0)
+
+/* 2 REG_DDMA_CHSTATUS			(Offset 0x12E8) */
+
+#define BIT_DDMACH5_BUSY BIT(5)
+#define BIT_DDMACH4_BUSY BIT(4)
+#define BIT_DDMACH3_BUSY BIT(3)
+#define BIT_DDMACH2_BUSY BIT(2)
+#define BIT_DDMACH1_BUSY BIT(1)
+#define BIT_DDMACH0_BUSY BIT(0)
+
+/* 2 REG_DDMA_CHKSUM				(Offset 0x12F0) */
+
+#define BIT_SHIFT_IDDMA0_CHKSUM 0
+#define BIT_MASK_IDDMA0_CHKSUM 0xffff
+#define BIT_IDDMA0_CHKSUM(x)                                                   \
+	(((x) & BIT_MASK_IDDMA0_CHKSUM) << BIT_SHIFT_IDDMA0_CHKSUM)
+#define BITS_IDDMA0_CHKSUM (BIT_MASK_IDDMA0_CHKSUM << BIT_SHIFT_IDDMA0_CHKSUM)
+#define BIT_CLEAR_IDDMA0_CHKSUM(x) ((x) & (~BITS_IDDMA0_CHKSUM))
+#define BIT_GET_IDDMA0_CHKSUM(x)                                               \
+	(((x) >> BIT_SHIFT_IDDMA0_CHKSUM) & BIT_MASK_IDDMA0_CHKSUM)
+#define BIT_SET_IDDMA0_CHKSUM(x, v)                                            \
+	(BIT_CLEAR_IDDMA0_CHKSUM(x) | BIT_IDDMA0_CHKSUM(v))
+
+/* 2 REG_DDMA_MONITOR			(Offset 0x12FC) */
+
+#define BIT_IDDMA0_PERMU_UNDERFLOW BIT(14)
+#define BIT_IDDMA0_FIFO_UNDERFLOW BIT(13)
+#define BIT_IDDMA0_FIFO_OVERFLOW BIT(12)
+#define BIT_CH5_ERR BIT(5)
+#define BIT_CH4_ERR BIT(4)
+#define BIT_CH3_ERR BIT(3)
+#define BIT_CH2_ERR BIT(2)
+#define BIT_CH1_ERR BIT(1)
+#define BIT_CH0_ERR BIT(0)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_STC_INT_CS				(Offset 0x1300) */
+
+#define BIT_STC_INT_EN BIT(31)
+#define BIT_STC_INT_GRP_EN BIT(31)
+
+#define BIT_SHIFT_STC_INT_FLAG 16
+#define BIT_MASK_STC_INT_FLAG 0xff
+#define BIT_STC_INT_FLAG(x)                                                    \
+	(((x) & BIT_MASK_STC_INT_FLAG) << BIT_SHIFT_STC_INT_FLAG)
+#define BITS_STC_INT_FLAG (BIT_MASK_STC_INT_FLAG << BIT_SHIFT_STC_INT_FLAG)
+#define BIT_CLEAR_STC_INT_FLAG(x) ((x) & (~BITS_STC_INT_FLAG))
+#define BIT_GET_STC_INT_FLAG(x)                                                \
+	(((x) >> BIT_SHIFT_STC_INT_FLAG) & BIT_MASK_STC_INT_FLAG)
+#define BIT_SET_STC_INT_FLAG(x, v)                                             \
+	(BIT_CLEAR_STC_INT_FLAG(x) | BIT_STC_INT_FLAG(v))
+
+#define BIT_SHIFT_STC_INT_IDX 8
+#define BIT_MASK_STC_INT_IDX 0x7
+#define BIT_STC_INT_IDX(x)                                                     \
+	(((x) & BIT_MASK_STC_INT_IDX) << BIT_SHIFT_STC_INT_IDX)
+#define BITS_STC_INT_IDX (BIT_MASK_STC_INT_IDX << BIT_SHIFT_STC_INT_IDX)
+#define BIT_CLEAR_STC_INT_IDX(x) ((x) & (~BITS_STC_INT_IDX))
+#define BIT_GET_STC_INT_IDX(x)                                                 \
+	(((x) >> BIT_SHIFT_STC_INT_IDX) & BIT_MASK_STC_INT_IDX)
+#define BIT_SET_STC_INT_IDX(x, v)                                              \
+	(BIT_CLEAR_STC_INT_IDX(x) | BIT_STC_INT_IDX(v))
+
+#define BIT_SHIFT_STC_INT_EXPECT_LS 8
+#define BIT_MASK_STC_INT_EXPECT_LS 0x3f
+#define BIT_STC_INT_EXPECT_LS(x)                                               \
+	(((x) & BIT_MASK_STC_INT_EXPECT_LS) << BIT_SHIFT_STC_INT_EXPECT_LS)
+#define BITS_STC_INT_EXPECT_LS                                                 \
+	(BIT_MASK_STC_INT_EXPECT_LS << BIT_SHIFT_STC_INT_EXPECT_LS)
+#define BIT_CLEAR_STC_INT_EXPECT_LS(x) ((x) & (~BITS_STC_INT_EXPECT_LS))
+#define BIT_GET_STC_INT_EXPECT_LS(x)                                           \
+	(((x) >> BIT_SHIFT_STC_INT_EXPECT_LS) & BIT_MASK_STC_INT_EXPECT_LS)
+#define BIT_SET_STC_INT_EXPECT_LS(x, v)                                        \
+	(BIT_CLEAR_STC_INT_EXPECT_LS(x) | BIT_STC_INT_EXPECT_LS(v))
+
+#define BIT_SHIFT_STC_INT_REALTIME_CS 0
+#define BIT_MASK_STC_INT_REALTIME_CS 0x3f
+#define BIT_STC_INT_REALTIME_CS(x)                                             \
+	(((x) & BIT_MASK_STC_INT_REALTIME_CS) << BIT_SHIFT_STC_INT_REALTIME_CS)
+#define BITS_STC_INT_REALTIME_CS                                               \
+	(BIT_MASK_STC_INT_REALTIME_CS << BIT_SHIFT_STC_INT_REALTIME_CS)
+#define BIT_CLEAR_STC_INT_REALTIME_CS(x) ((x) & (~BITS_STC_INT_REALTIME_CS))
+#define BIT_GET_STC_INT_REALTIME_CS(x)                                         \
+	(((x) >> BIT_SHIFT_STC_INT_REALTIME_CS) & BIT_MASK_STC_INT_REALTIME_CS)
+#define BIT_SET_STC_INT_REALTIME_CS(x, v)                                      \
+	(BIT_CLEAR_STC_INT_REALTIME_CS(x) | BIT_STC_INT_REALTIME_CS(v))
+
+#define BIT_SHIFT_STC_INT_EXPECT_CS 0
+#define BIT_MASK_STC_INT_EXPECT_CS 0x3f
+#define BIT_STC_INT_EXPECT_CS(x)                                               \
+	(((x) & BIT_MASK_STC_INT_EXPECT_CS) << BIT_SHIFT_STC_INT_EXPECT_CS)
+#define BITS_STC_INT_EXPECT_CS                                                 \
+	(BIT_MASK_STC_INT_EXPECT_CS << BIT_SHIFT_STC_INT_EXPECT_CS)
+#define BIT_CLEAR_STC_INT_EXPECT_CS(x) ((x) & (~BITS_STC_INT_EXPECT_CS))
+#define BIT_GET_STC_INT_EXPECT_CS(x)                                           \
+	(((x) >> BIT_SHIFT_STC_INT_EXPECT_CS) & BIT_MASK_STC_INT_EXPECT_CS)
+#define BIT_SET_STC_INT_EXPECT_CS(x, v)                                        \
+	(BIT_CLEAR_STC_INT_EXPECT_CS(x) | BIT_STC_INT_EXPECT_CS(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_ACH4_ACH5_TXBD_NUM			(Offset 0x130C) */
+
+#define BIT_PCIE_ACH5_FLAG BIT(30)
+
+#define BIT_SHIFT_ACH5_DESC_MODE 28
+#define BIT_MASK_ACH5_DESC_MODE 0x3
+#define BIT_ACH5_DESC_MODE(x)                                                  \
+	(((x) & BIT_MASK_ACH5_DESC_MODE) << BIT_SHIFT_ACH5_DESC_MODE)
+#define BITS_ACH5_DESC_MODE                                                    \
+	(BIT_MASK_ACH5_DESC_MODE << BIT_SHIFT_ACH5_DESC_MODE)
+#define BIT_CLEAR_ACH5_DESC_MODE(x) ((x) & (~BITS_ACH5_DESC_MODE))
+#define BIT_GET_ACH5_DESC_MODE(x)                                              \
+	(((x) >> BIT_SHIFT_ACH5_DESC_MODE) & BIT_MASK_ACH5_DESC_MODE)
+#define BIT_SET_ACH5_DESC_MODE(x, v)                                           \
+	(BIT_CLEAR_ACH5_DESC_MODE(x) | BIT_ACH5_DESC_MODE(v))
+
+#define BIT_SHIFT_ACH5_DESC_NUM 16
+#define BIT_MASK_ACH5_DESC_NUM 0xfff
+#define BIT_ACH5_DESC_NUM(x)                                                   \
+	(((x) & BIT_MASK_ACH5_DESC_NUM) << BIT_SHIFT_ACH5_DESC_NUM)
+#define BITS_ACH5_DESC_NUM (BIT_MASK_ACH5_DESC_NUM << BIT_SHIFT_ACH5_DESC_NUM)
+#define BIT_CLEAR_ACH5_DESC_NUM(x) ((x) & (~BITS_ACH5_DESC_NUM))
+#define BIT_GET_ACH5_DESC_NUM(x)                                               \
+	(((x) >> BIT_SHIFT_ACH5_DESC_NUM) & BIT_MASK_ACH5_DESC_NUM)
+#define BIT_SET_ACH5_DESC_NUM(x, v)                                            \
+	(BIT_CLEAR_ACH5_DESC_NUM(x) | BIT_ACH5_DESC_NUM(v))
+
+#define BIT_PCIE_ACH4_FLAG BIT(14)
+
+#define BIT_SHIFT_ACH4_DESC_MODE 12
+#define BIT_MASK_ACH4_DESC_MODE 0x3
+#define BIT_ACH4_DESC_MODE(x)                                                  \
+	(((x) & BIT_MASK_ACH4_DESC_MODE) << BIT_SHIFT_ACH4_DESC_MODE)
+#define BITS_ACH4_DESC_MODE                                                    \
+	(BIT_MASK_ACH4_DESC_MODE << BIT_SHIFT_ACH4_DESC_MODE)
+#define BIT_CLEAR_ACH4_DESC_MODE(x) ((x) & (~BITS_ACH4_DESC_MODE))
+#define BIT_GET_ACH4_DESC_MODE(x)                                              \
+	(((x) >> BIT_SHIFT_ACH4_DESC_MODE) & BIT_MASK_ACH4_DESC_MODE)
+#define BIT_SET_ACH4_DESC_MODE(x, v)                                           \
+	(BIT_CLEAR_ACH4_DESC_MODE(x) | BIT_ACH4_DESC_MODE(v))
+
+#define BIT_SHIFT_ACH4_DESC_NUM 0
+#define BIT_MASK_ACH4_DESC_NUM 0xfff
+#define BIT_ACH4_DESC_NUM(x)                                                   \
+	(((x) & BIT_MASK_ACH4_DESC_NUM) << BIT_SHIFT_ACH4_DESC_NUM)
+#define BITS_ACH4_DESC_NUM (BIT_MASK_ACH4_DESC_NUM << BIT_SHIFT_ACH4_DESC_NUM)
+#define BIT_CLEAR_ACH4_DESC_NUM(x) ((x) & (~BITS_ACH4_DESC_NUM))
+#define BIT_GET_ACH4_DESC_NUM(x)                                               \
+	(((x) >> BIT_SHIFT_ACH4_DESC_NUM) & BIT_MASK_ACH4_DESC_NUM)
+#define BIT_SET_ACH4_DESC_NUM(x, v)                                            \
+	(BIT_CLEAR_ACH4_DESC_NUM(x) | BIT_ACH4_DESC_NUM(v))
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+
+/* 2 REG_CMU_DLY_CTRL			(Offset 0x1310) */
+
+#define BIT_CMU_DLY_EN BIT(31)
+#define BIT_CMU_DLY_MODE BIT(30)
+
+#define BIT_SHIFT_CMU_DLY_PRE_DIV 0
+#define BIT_MASK_CMU_DLY_PRE_DIV 0xff
+#define BIT_CMU_DLY_PRE_DIV(x)                                                 \
+	(((x) & BIT_MASK_CMU_DLY_PRE_DIV) << BIT_SHIFT_CMU_DLY_PRE_DIV)
+#define BITS_CMU_DLY_PRE_DIV                                                   \
+	(BIT_MASK_CMU_DLY_PRE_DIV << BIT_SHIFT_CMU_DLY_PRE_DIV)
+#define BIT_CLEAR_CMU_DLY_PRE_DIV(x) ((x) & (~BITS_CMU_DLY_PRE_DIV))
+#define BIT_GET_CMU_DLY_PRE_DIV(x)                                             \
+	(((x) >> BIT_SHIFT_CMU_DLY_PRE_DIV) & BIT_MASK_CMU_DLY_PRE_DIV)
+#define BIT_SET_CMU_DLY_PRE_DIV(x, v)                                          \
+	(BIT_CLEAR_CMU_DLY_PRE_DIV(x) | BIT_CMU_DLY_PRE_DIV(v))
+
+/* 2 REG_CMU_DLY_CFG				(Offset 0x1314) */
+
+#define BIT_SHIFT_CMU_DLY_LTR_A2I 24
+#define BIT_MASK_CMU_DLY_LTR_A2I 0xff
+#define BIT_CMU_DLY_LTR_A2I(x)                                                 \
+	(((x) & BIT_MASK_CMU_DLY_LTR_A2I) << BIT_SHIFT_CMU_DLY_LTR_A2I)
+#define BITS_CMU_DLY_LTR_A2I                                                   \
+	(BIT_MASK_CMU_DLY_LTR_A2I << BIT_SHIFT_CMU_DLY_LTR_A2I)
+#define BIT_CLEAR_CMU_DLY_LTR_A2I(x) ((x) & (~BITS_CMU_DLY_LTR_A2I))
+#define BIT_GET_CMU_DLY_LTR_A2I(x)                                             \
+	(((x) >> BIT_SHIFT_CMU_DLY_LTR_A2I) & BIT_MASK_CMU_DLY_LTR_A2I)
+#define BIT_SET_CMU_DLY_LTR_A2I(x, v)                                          \
+	(BIT_CLEAR_CMU_DLY_LTR_A2I(x) | BIT_CMU_DLY_LTR_A2I(v))
+
+#define BIT_SHIFT_CMU_DLY_LTR_I2A 16
+#define BIT_MASK_CMU_DLY_LTR_I2A 0xff
+#define BIT_CMU_DLY_LTR_I2A(x)                                                 \
+	(((x) & BIT_MASK_CMU_DLY_LTR_I2A) << BIT_SHIFT_CMU_DLY_LTR_I2A)
+#define BITS_CMU_DLY_LTR_I2A                                                   \
+	(BIT_MASK_CMU_DLY_LTR_I2A << BIT_SHIFT_CMU_DLY_LTR_I2A)
+#define BIT_CLEAR_CMU_DLY_LTR_I2A(x) ((x) & (~BITS_CMU_DLY_LTR_I2A))
+#define BIT_GET_CMU_DLY_LTR_I2A(x)                                             \
+	(((x) >> BIT_SHIFT_CMU_DLY_LTR_I2A) & BIT_MASK_CMU_DLY_LTR_I2A)
+#define BIT_SET_CMU_DLY_LTR_I2A(x, v)                                          \
+	(BIT_CLEAR_CMU_DLY_LTR_I2A(x) | BIT_CMU_DLY_LTR_I2A(v))
+
+#define BIT_SHIFT_CMU_DLY_LTR_IDLE 8
+#define BIT_MASK_CMU_DLY_LTR_IDLE 0xff
+#define BIT_CMU_DLY_LTR_IDLE(x)                                                \
+	(((x) & BIT_MASK_CMU_DLY_LTR_IDLE) << BIT_SHIFT_CMU_DLY_LTR_IDLE)
+#define BITS_CMU_DLY_LTR_IDLE                                                  \
+	(BIT_MASK_CMU_DLY_LTR_IDLE << BIT_SHIFT_CMU_DLY_LTR_IDLE)
+#define BIT_CLEAR_CMU_DLY_LTR_IDLE(x) ((x) & (~BITS_CMU_DLY_LTR_IDLE))
+#define BIT_GET_CMU_DLY_LTR_IDLE(x)                                            \
+	(((x) >> BIT_SHIFT_CMU_DLY_LTR_IDLE) & BIT_MASK_CMU_DLY_LTR_IDLE)
+#define BIT_SET_CMU_DLY_LTR_IDLE(x, v)                                         \
+	(BIT_CLEAR_CMU_DLY_LTR_IDLE(x) | BIT_CMU_DLY_LTR_IDLE(v))
+
+#define BIT_SHIFT_CMU_DLY_LTR_ACT 0
+#define BIT_MASK_CMU_DLY_LTR_ACT 0xff
+#define BIT_CMU_DLY_LTR_ACT(x)                                                 \
+	(((x) & BIT_MASK_CMU_DLY_LTR_ACT) << BIT_SHIFT_CMU_DLY_LTR_ACT)
+#define BITS_CMU_DLY_LTR_ACT                                                   \
+	(BIT_MASK_CMU_DLY_LTR_ACT << BIT_SHIFT_CMU_DLY_LTR_ACT)
+#define BIT_CLEAR_CMU_DLY_LTR_ACT(x) ((x) & (~BITS_CMU_DLY_LTR_ACT))
+#define BIT_GET_CMU_DLY_LTR_ACT(x)                                             \
+	(((x) >> BIT_SHIFT_CMU_DLY_LTR_ACT) & BIT_MASK_CMU_DLY_LTR_ACT)
+#define BIT_SET_CMU_DLY_LTR_ACT(x, v)                                          \
+	(BIT_CLEAR_CMU_DLY_LTR_ACT(x) | BIT_CMU_DLY_LTR_ACT(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_FWCMDQ_TXBD_IDX			(Offset 0x1318) */
+
+#define BIT_SHIFT_FWCMDQ_HW_IDX 16
+#define BIT_MASK_FWCMDQ_HW_IDX 0xfff
+#define BIT_FWCMDQ_HW_IDX(x)                                                   \
+	(((x) & BIT_MASK_FWCMDQ_HW_IDX) << BIT_SHIFT_FWCMDQ_HW_IDX)
+#define BITS_FWCMDQ_HW_IDX (BIT_MASK_FWCMDQ_HW_IDX << BIT_SHIFT_FWCMDQ_HW_IDX)
+#define BIT_CLEAR_FWCMDQ_HW_IDX(x) ((x) & (~BITS_FWCMDQ_HW_IDX))
+#define BIT_GET_FWCMDQ_HW_IDX(x)                                               \
+	(((x) >> BIT_SHIFT_FWCMDQ_HW_IDX) & BIT_MASK_FWCMDQ_HW_IDX)
+#define BIT_SET_FWCMDQ_HW_IDX(x, v)                                            \
+	(BIT_CLEAR_FWCMDQ_HW_IDX(x) | BIT_FWCMDQ_HW_IDX(v))
+
+#define BIT_SHIFT_FWCMDQ_HOST_IDX 0
+#define BIT_MASK_FWCMDQ_HOST_IDX 0xfff
+#define BIT_FWCMDQ_HOST_IDX(x)                                                 \
+	(((x) & BIT_MASK_FWCMDQ_HOST_IDX) << BIT_SHIFT_FWCMDQ_HOST_IDX)
+#define BITS_FWCMDQ_HOST_IDX                                                   \
+	(BIT_MASK_FWCMDQ_HOST_IDX << BIT_SHIFT_FWCMDQ_HOST_IDX)
+#define BIT_CLEAR_FWCMDQ_HOST_IDX(x) ((x) & (~BITS_FWCMDQ_HOST_IDX))
+#define BIT_GET_FWCMDQ_HOST_IDX(x)                                             \
+	(((x) >> BIT_SHIFT_FWCMDQ_HOST_IDX) & BIT_MASK_FWCMDQ_HOST_IDX)
+#define BIT_SET_FWCMDQ_HOST_IDX(x, v)                                          \
+	(BIT_CLEAR_FWCMDQ_HOST_IDX(x) | BIT_FWCMDQ_HOST_IDX(v))
+
+/* 2 REG_P0HI8Q_TXBD_IDX			(Offset 0x131C) */
+
+#define BIT_SHIFT_P0HI8Q_HW_IDX 16
+#define BIT_MASK_P0HI8Q_HW_IDX 0xfff
+#define BIT_P0HI8Q_HW_IDX(x)                                                   \
+	(((x) & BIT_MASK_P0HI8Q_HW_IDX) << BIT_SHIFT_P0HI8Q_HW_IDX)
+#define BITS_P0HI8Q_HW_IDX (BIT_MASK_P0HI8Q_HW_IDX << BIT_SHIFT_P0HI8Q_HW_IDX)
+#define BIT_CLEAR_P0HI8Q_HW_IDX(x) ((x) & (~BITS_P0HI8Q_HW_IDX))
+#define BIT_GET_P0HI8Q_HW_IDX(x)                                               \
+	(((x) >> BIT_SHIFT_P0HI8Q_HW_IDX) & BIT_MASK_P0HI8Q_HW_IDX)
+#define BIT_SET_P0HI8Q_HW_IDX(x, v)                                            \
+	(BIT_CLEAR_P0HI8Q_HW_IDX(x) | BIT_P0HI8Q_HW_IDX(v))
+
+#define BIT_SHIFT_P0HI8Q_HOST_IDX 0
+#define BIT_MASK_P0HI8Q_HOST_IDX 0xfff
+#define BIT_P0HI8Q_HOST_IDX(x)                                                 \
+	(((x) & BIT_MASK_P0HI8Q_HOST_IDX) << BIT_SHIFT_P0HI8Q_HOST_IDX)
+#define BITS_P0HI8Q_HOST_IDX                                                   \
+	(BIT_MASK_P0HI8Q_HOST_IDX << BIT_SHIFT_P0HI8Q_HOST_IDX)
+#define BIT_CLEAR_P0HI8Q_HOST_IDX(x) ((x) & (~BITS_P0HI8Q_HOST_IDX))
+#define BIT_GET_P0HI8Q_HOST_IDX(x)                                             \
+	(((x) >> BIT_SHIFT_P0HI8Q_HOST_IDX) & BIT_MASK_P0HI8Q_HOST_IDX)
+#define BIT_SET_P0HI8Q_HOST_IDX(x, v)                                          \
+	(BIT_CLEAR_P0HI8Q_HOST_IDX(x) | BIT_P0HI8Q_HOST_IDX(v))
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_H2CQ_TXBD_DESA			(Offset 0x1320) */
+
+#define BIT_SHIFT_H2CQ_TXBD_DESA 0
+#define BIT_MASK_H2CQ_TXBD_DESA 0xffffffffffffffffL
+#define BIT_H2CQ_TXBD_DESA(x)                                                  \
+	(((x) & BIT_MASK_H2CQ_TXBD_DESA) << BIT_SHIFT_H2CQ_TXBD_DESA)
+#define BITS_H2CQ_TXBD_DESA                                                    \
+	(BIT_MASK_H2CQ_TXBD_DESA << BIT_SHIFT_H2CQ_TXBD_DESA)
+#define BIT_CLEAR_H2CQ_TXBD_DESA(x) ((x) & (~BITS_H2CQ_TXBD_DESA))
+#define BIT_GET_H2CQ_TXBD_DESA(x)                                              \
+	(((x) >> BIT_SHIFT_H2CQ_TXBD_DESA) & BIT_MASK_H2CQ_TXBD_DESA)
+#define BIT_SET_H2CQ_TXBD_DESA(x, v)                                           \
+	(BIT_CLEAR_H2CQ_TXBD_DESA(x) | BIT_H2CQ_TXBD_DESA(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_H2CQ_TXBD_DESA_L			(Offset 0x1320) */
+
+#define BIT_SHIFT_H2CQ_TXBD_DESA_L 0
+#define BIT_MASK_H2CQ_TXBD_DESA_L 0xffffffffL
+#define BIT_H2CQ_TXBD_DESA_L(x)                                                \
+	(((x) & BIT_MASK_H2CQ_TXBD_DESA_L) << BIT_SHIFT_H2CQ_TXBD_DESA_L)
+#define BITS_H2CQ_TXBD_DESA_L                                                  \
+	(BIT_MASK_H2CQ_TXBD_DESA_L << BIT_SHIFT_H2CQ_TXBD_DESA_L)
+#define BIT_CLEAR_H2CQ_TXBD_DESA_L(x) ((x) & (~BITS_H2CQ_TXBD_DESA_L))
+#define BIT_GET_H2CQ_TXBD_DESA_L(x)                                            \
+	(((x) >> BIT_SHIFT_H2CQ_TXBD_DESA_L) & BIT_MASK_H2CQ_TXBD_DESA_L)
+#define BIT_SET_H2CQ_TXBD_DESA_L(x, v)                                         \
+	(BIT_CLEAR_H2CQ_TXBD_DESA_L(x) | BIT_H2CQ_TXBD_DESA_L(v))
+
+/* 2 REG_H2CQ_TXBD_DESA_H			(Offset 0x1324) */
+
+#define BIT_SHIFT_H2CQ_TXBD_DESA_H 0
+#define BIT_MASK_H2CQ_TXBD_DESA_H 0xffffffffL
+#define BIT_H2CQ_TXBD_DESA_H(x)                                                \
+	(((x) & BIT_MASK_H2CQ_TXBD_DESA_H) << BIT_SHIFT_H2CQ_TXBD_DESA_H)
+#define BITS_H2CQ_TXBD_DESA_H                                                  \
+	(BIT_MASK_H2CQ_TXBD_DESA_H << BIT_SHIFT_H2CQ_TXBD_DESA_H)
+#define BIT_CLEAR_H2CQ_TXBD_DESA_H(x) ((x) & (~BITS_H2CQ_TXBD_DESA_H))
+#define BIT_GET_H2CQ_TXBD_DESA_H(x)                                            \
+	(((x) >> BIT_SHIFT_H2CQ_TXBD_DESA_H) & BIT_MASK_H2CQ_TXBD_DESA_H)
+#define BIT_SET_H2CQ_TXBD_DESA_H(x, v)                                         \
+	(BIT_CLEAR_H2CQ_TXBD_DESA_H(x) | BIT_H2CQ_TXBD_DESA_H(v))
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_H2CQ_TXBD_NUM			(Offset 0x1328) */
+
+#define BIT_PCIE_H2CQ_FLAG BIT(14)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_H2CQ_TXBD_NUM			(Offset 0x1328) */
+
+#define BIT_HCI_H2CQ_FLAG BIT(14)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_H2CQ_TXBD_NUM			(Offset 0x1328) */
+
+#define BIT_SHIFT_H2CQ_DESC_MODE 12
+#define BIT_MASK_H2CQ_DESC_MODE 0x3
+#define BIT_H2CQ_DESC_MODE(x)                                                  \
+	(((x) & BIT_MASK_H2CQ_DESC_MODE) << BIT_SHIFT_H2CQ_DESC_MODE)
+#define BITS_H2CQ_DESC_MODE                                                    \
+	(BIT_MASK_H2CQ_DESC_MODE << BIT_SHIFT_H2CQ_DESC_MODE)
+#define BIT_CLEAR_H2CQ_DESC_MODE(x) ((x) & (~BITS_H2CQ_DESC_MODE))
+#define BIT_GET_H2CQ_DESC_MODE(x)                                              \
+	(((x) >> BIT_SHIFT_H2CQ_DESC_MODE) & BIT_MASK_H2CQ_DESC_MODE)
+#define BIT_SET_H2CQ_DESC_MODE(x, v)                                           \
+	(BIT_CLEAR_H2CQ_DESC_MODE(x) | BIT_H2CQ_DESC_MODE(v))
+
+#define BIT_SHIFT_H2CQ_DESC_NUM 0
+#define BIT_MASK_H2CQ_DESC_NUM 0xfff
+#define BIT_H2CQ_DESC_NUM(x)                                                   \
+	(((x) & BIT_MASK_H2CQ_DESC_NUM) << BIT_SHIFT_H2CQ_DESC_NUM)
+#define BITS_H2CQ_DESC_NUM (BIT_MASK_H2CQ_DESC_NUM << BIT_SHIFT_H2CQ_DESC_NUM)
+#define BIT_CLEAR_H2CQ_DESC_NUM(x) ((x) & (~BITS_H2CQ_DESC_NUM))
+#define BIT_GET_H2CQ_DESC_NUM(x)                                               \
+	(((x) >> BIT_SHIFT_H2CQ_DESC_NUM) & BIT_MASK_H2CQ_DESC_NUM)
+#define BIT_SET_H2CQ_DESC_NUM(x, v)                                            \
+	(BIT_CLEAR_H2CQ_DESC_NUM(x) | BIT_H2CQ_DESC_NUM(v))
+
+/* 2 REG_H2CQ_TXBD_IDX			(Offset 0x132C) */
+
+#define BIT_SHIFT_H2CQ_HW_IDX 16
+#define BIT_MASK_H2CQ_HW_IDX 0xfff
+#define BIT_H2CQ_HW_IDX(x)                                                     \
+	(((x) & BIT_MASK_H2CQ_HW_IDX) << BIT_SHIFT_H2CQ_HW_IDX)
+#define BITS_H2CQ_HW_IDX (BIT_MASK_H2CQ_HW_IDX << BIT_SHIFT_H2CQ_HW_IDX)
+#define BIT_CLEAR_H2CQ_HW_IDX(x) ((x) & (~BITS_H2CQ_HW_IDX))
+#define BIT_GET_H2CQ_HW_IDX(x)                                                 \
+	(((x) >> BIT_SHIFT_H2CQ_HW_IDX) & BIT_MASK_H2CQ_HW_IDX)
+#define BIT_SET_H2CQ_HW_IDX(x, v)                                              \
+	(BIT_CLEAR_H2CQ_HW_IDX(x) | BIT_H2CQ_HW_IDX(v))
+
+#define BIT_SHIFT_H2CQ_HOST_IDX 0
+#define BIT_MASK_H2CQ_HOST_IDX 0xfff
+#define BIT_H2CQ_HOST_IDX(x)                                                   \
+	(((x) & BIT_MASK_H2CQ_HOST_IDX) << BIT_SHIFT_H2CQ_HOST_IDX)
+#define BITS_H2CQ_HOST_IDX (BIT_MASK_H2CQ_HOST_IDX << BIT_SHIFT_H2CQ_HOST_IDX)
+#define BIT_CLEAR_H2CQ_HOST_IDX(x) ((x) & (~BITS_H2CQ_HOST_IDX))
+#define BIT_GET_H2CQ_HOST_IDX(x)                                               \
+	(((x) >> BIT_SHIFT_H2CQ_HOST_IDX) & BIT_MASK_H2CQ_HOST_IDX)
+#define BIT_SET_H2CQ_HOST_IDX(x, v)                                            \
+	(BIT_CLEAR_H2CQ_HOST_IDX(x) | BIT_H2CQ_HOST_IDX(v))
+
+/* 2 REG_H2CQ_CSR				(Offset 0x1330) */
+
+#define BIT_H2CQ_FULL BIT(31)
+#define BIT_CLR_H2CQ_HOST_IDX BIT(16)
+#define BIT_CLR_H2CQ_HW_IDX BIT(8)
+#define BIT_STOP_H2CQ BIT(0)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_P0HI9Q_TXBD_IDX			(Offset 0x1334) */
+
+#define BIT_SHIFT_P0HI9Q_HW_IDX 16
+#define BIT_MASK_P0HI9Q_HW_IDX 0xfff
+#define BIT_P0HI9Q_HW_IDX(x)                                                   \
+	(((x) & BIT_MASK_P0HI9Q_HW_IDX) << BIT_SHIFT_P0HI9Q_HW_IDX)
+#define BITS_P0HI9Q_HW_IDX (BIT_MASK_P0HI9Q_HW_IDX << BIT_SHIFT_P0HI9Q_HW_IDX)
+#define BIT_CLEAR_P0HI9Q_HW_IDX(x) ((x) & (~BITS_P0HI9Q_HW_IDX))
+#define BIT_GET_P0HI9Q_HW_IDX(x)                                               \
+	(((x) >> BIT_SHIFT_P0HI9Q_HW_IDX) & BIT_MASK_P0HI9Q_HW_IDX)
+#define BIT_SET_P0HI9Q_HW_IDX(x, v)                                            \
+	(BIT_CLEAR_P0HI9Q_HW_IDX(x) | BIT_P0HI9Q_HW_IDX(v))
+
+#define BIT_SHIFT_P0HI9Q_HOST_IDX 0
+#define BIT_MASK_P0HI9Q_HOST_IDX 0xfff
+#define BIT_P0HI9Q_HOST_IDX(x)                                                 \
+	(((x) & BIT_MASK_P0HI9Q_HOST_IDX) << BIT_SHIFT_P0HI9Q_HOST_IDX)
+#define BITS_P0HI9Q_HOST_IDX                                                   \
+	(BIT_MASK_P0HI9Q_HOST_IDX << BIT_SHIFT_P0HI9Q_HOST_IDX)
+#define BIT_CLEAR_P0HI9Q_HOST_IDX(x) ((x) & (~BITS_P0HI9Q_HOST_IDX))
+#define BIT_GET_P0HI9Q_HOST_IDX(x)                                             \
+	(((x) >> BIT_SHIFT_P0HI9Q_HOST_IDX) & BIT_MASK_P0HI9Q_HOST_IDX)
+#define BIT_SET_P0HI9Q_HOST_IDX(x, v)                                          \
+	(BIT_CLEAR_P0HI9Q_HOST_IDX(x) | BIT_P0HI9Q_HOST_IDX(v))
+
+/* 2 REG_P0HI10Q_TXBD_IDX			(Offset 0x1338) */
+
+#define BIT_SHIFT_P0HI10Q_HW_IDX 16
+#define BIT_MASK_P0HI10Q_HW_IDX 0xfff
+#define BIT_P0HI10Q_HW_IDX(x)                                                  \
+	(((x) & BIT_MASK_P0HI10Q_HW_IDX) << BIT_SHIFT_P0HI10Q_HW_IDX)
+#define BITS_P0HI10Q_HW_IDX                                                    \
+	(BIT_MASK_P0HI10Q_HW_IDX << BIT_SHIFT_P0HI10Q_HW_IDX)
+#define BIT_CLEAR_P0HI10Q_HW_IDX(x) ((x) & (~BITS_P0HI10Q_HW_IDX))
+#define BIT_GET_P0HI10Q_HW_IDX(x)                                              \
+	(((x) >> BIT_SHIFT_P0HI10Q_HW_IDX) & BIT_MASK_P0HI10Q_HW_IDX)
+#define BIT_SET_P0HI10Q_HW_IDX(x, v)                                           \
+	(BIT_CLEAR_P0HI10Q_HW_IDX(x) | BIT_P0HI10Q_HW_IDX(v))
+
+#define BIT_SHIFT_P0HI10Q_HOST_IDX 0
+#define BIT_MASK_P0HI10Q_HOST_IDX 0xfff
+#define BIT_P0HI10Q_HOST_IDX(x)                                                \
+	(((x) & BIT_MASK_P0HI10Q_HOST_IDX) << BIT_SHIFT_P0HI10Q_HOST_IDX)
+#define BITS_P0HI10Q_HOST_IDX                                                  \
+	(BIT_MASK_P0HI10Q_HOST_IDX << BIT_SHIFT_P0HI10Q_HOST_IDX)
+#define BIT_CLEAR_P0HI10Q_HOST_IDX(x) ((x) & (~BITS_P0HI10Q_HOST_IDX))
+#define BIT_GET_P0HI10Q_HOST_IDX(x)                                            \
+	(((x) >> BIT_SHIFT_P0HI10Q_HOST_IDX) & BIT_MASK_P0HI10Q_HOST_IDX)
+#define BIT_SET_P0HI10Q_HOST_IDX(x, v)                                         \
+	(BIT_CLEAR_P0HI10Q_HOST_IDX(x) | BIT_P0HI10Q_HOST_IDX(v))
+
+/* 2 REG_P0HI11Q_TXBD_IDX			(Offset 0x133C) */
+
+#define BIT_SHIFT_P0HI11Q_HW_IDX 16
+#define BIT_MASK_P0HI11Q_HW_IDX 0xfff
+#define BIT_P0HI11Q_HW_IDX(x)                                                  \
+	(((x) & BIT_MASK_P0HI11Q_HW_IDX) << BIT_SHIFT_P0HI11Q_HW_IDX)
+#define BITS_P0HI11Q_HW_IDX                                                    \
+	(BIT_MASK_P0HI11Q_HW_IDX << BIT_SHIFT_P0HI11Q_HW_IDX)
+#define BIT_CLEAR_P0HI11Q_HW_IDX(x) ((x) & (~BITS_P0HI11Q_HW_IDX))
+#define BIT_GET_P0HI11Q_HW_IDX(x)                                              \
+	(((x) >> BIT_SHIFT_P0HI11Q_HW_IDX) & BIT_MASK_P0HI11Q_HW_IDX)
+#define BIT_SET_P0HI11Q_HW_IDX(x, v)                                           \
+	(BIT_CLEAR_P0HI11Q_HW_IDX(x) | BIT_P0HI11Q_HW_IDX(v))
+
+#define BIT_SHIFT_P0HI11Q_HOST_IDX 0
+#define BIT_MASK_P0HI11Q_HOST_IDX 0xfff
+#define BIT_P0HI11Q_HOST_IDX(x)                                                \
+	(((x) & BIT_MASK_P0HI11Q_HOST_IDX) << BIT_SHIFT_P0HI11Q_HOST_IDX)
+#define BITS_P0HI11Q_HOST_IDX                                                  \
+	(BIT_MASK_P0HI11Q_HOST_IDX << BIT_SHIFT_P0HI11Q_HOST_IDX)
+#define BIT_CLEAR_P0HI11Q_HOST_IDX(x) ((x) & (~BITS_P0HI11Q_HOST_IDX))
+#define BIT_GET_P0HI11Q_HOST_IDX(x)                                            \
+	(((x) >> BIT_SHIFT_P0HI11Q_HOST_IDX) & BIT_MASK_P0HI11Q_HOST_IDX)
+#define BIT_SET_P0HI11Q_HOST_IDX(x, v)                                         \
+	(BIT_CLEAR_P0HI11Q_HOST_IDX(x) | BIT_P0HI11Q_HOST_IDX(v))
+
+/* 2 REG_P0HI12Q_TXBD_IDX			(Offset 0x1340) */
+
+#define BIT_SHIFT_P0HI12Q_HW_IDX 16
+#define BIT_MASK_P0HI12Q_HW_IDX 0xfff
+#define BIT_P0HI12Q_HW_IDX(x)                                                  \
+	(((x) & BIT_MASK_P0HI12Q_HW_IDX) << BIT_SHIFT_P0HI12Q_HW_IDX)
+#define BITS_P0HI12Q_HW_IDX                                                    \
+	(BIT_MASK_P0HI12Q_HW_IDX << BIT_SHIFT_P0HI12Q_HW_IDX)
+#define BIT_CLEAR_P0HI12Q_HW_IDX(x) ((x) & (~BITS_P0HI12Q_HW_IDX))
+#define BIT_GET_P0HI12Q_HW_IDX(x)                                              \
+	(((x) >> BIT_SHIFT_P0HI12Q_HW_IDX) & BIT_MASK_P0HI12Q_HW_IDX)
+#define BIT_SET_P0HI12Q_HW_IDX(x, v)                                           \
+	(BIT_CLEAR_P0HI12Q_HW_IDX(x) | BIT_P0HI12Q_HW_IDX(v))
+
+#define BIT_SHIFT_P0HI12Q_HOST_IDX 0
+#define BIT_MASK_P0HI12Q_HOST_IDX 0xfff
+#define BIT_P0HI12Q_HOST_IDX(x)                                                \
+	(((x) & BIT_MASK_P0HI12Q_HOST_IDX) << BIT_SHIFT_P0HI12Q_HOST_IDX)
+#define BITS_P0HI12Q_HOST_IDX                                                  \
+	(BIT_MASK_P0HI12Q_HOST_IDX << BIT_SHIFT_P0HI12Q_HOST_IDX)
+#define BIT_CLEAR_P0HI12Q_HOST_IDX(x) ((x) & (~BITS_P0HI12Q_HOST_IDX))
+#define BIT_GET_P0HI12Q_HOST_IDX(x)                                            \
+	(((x) >> BIT_SHIFT_P0HI12Q_HOST_IDX) & BIT_MASK_P0HI12Q_HOST_IDX)
+#define BIT_SET_P0HI12Q_HOST_IDX(x, v)                                         \
+	(BIT_CLEAR_P0HI12Q_HOST_IDX(x) | BIT_P0HI12Q_HOST_IDX(v))
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_CPL_BUFFER_MONITOR			(Offset 0x1344) */
+
+#define BIT_TXQFULL_FLAG BIT(19)
+
+#define BIT_SHIFT_RELAX_ORDERING_ATTR 17
+#define BIT_MASK_RELAX_ORDERING_ATTR 0x3
+#define BIT_RELAX_ORDERING_ATTR(x)                                             \
+	(((x) & BIT_MASK_RELAX_ORDERING_ATTR) << BIT_SHIFT_RELAX_ORDERING_ATTR)
+#define BITS_RELAX_ORDERING_ATTR                                               \
+	(BIT_MASK_RELAX_ORDERING_ATTR << BIT_SHIFT_RELAX_ORDERING_ATTR)
+#define BIT_CLEAR_RELAX_ORDERING_ATTR(x) ((x) & (~BITS_RELAX_ORDERING_ATTR))
+#define BIT_GET_RELAX_ORDERING_ATTR(x)                                         \
+	(((x) >> BIT_SHIFT_RELAX_ORDERING_ATTR) & BIT_MASK_RELAX_ORDERING_ATTR)
+#define BIT_SET_RELAX_ORDERING_ATTR(x, v)                                      \
+	(BIT_CLEAR_RELAX_ORDERING_ATTR(x) | BIT_RELAX_ORDERING_ATTR(v))
+
+#define BIT_CLR_QD_CPL_MIN_REMAIN BIT(16)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_P0HI13Q_TXBD_IDX			(Offset 0x1344) */
+
+#define BIT_SHIFT_P0HI13Q_HW_IDX 16
+#define BIT_MASK_P0HI13Q_HW_IDX 0xfff
+#define BIT_P0HI13Q_HW_IDX(x)                                                  \
+	(((x) & BIT_MASK_P0HI13Q_HW_IDX) << BIT_SHIFT_P0HI13Q_HW_IDX)
+#define BITS_P0HI13Q_HW_IDX                                                    \
+	(BIT_MASK_P0HI13Q_HW_IDX << BIT_SHIFT_P0HI13Q_HW_IDX)
+#define BIT_CLEAR_P0HI13Q_HW_IDX(x) ((x) & (~BITS_P0HI13Q_HW_IDX))
+#define BIT_GET_P0HI13Q_HW_IDX(x)                                              \
+	(((x) >> BIT_SHIFT_P0HI13Q_HW_IDX) & BIT_MASK_P0HI13Q_HW_IDX)
+#define BIT_SET_P0HI13Q_HW_IDX(x, v)                                           \
+	(BIT_CLEAR_P0HI13Q_HW_IDX(x) | BIT_P0HI13Q_HW_IDX(v))
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_CPL_BUFFER_MONITOR			(Offset 0x1344) */
+
+#define BIT_SHIFT_QD_CPL_MIN_REMAIN_ADDR 8
+#define BIT_MASK_QD_CPL_MIN_REMAIN_ADDR 0xff
+#define BIT_QD_CPL_MIN_REMAIN_ADDR(x)                                          \
+	(((x) & BIT_MASK_QD_CPL_MIN_REMAIN_ADDR)                               \
+	 << BIT_SHIFT_QD_CPL_MIN_REMAIN_ADDR)
+#define BITS_QD_CPL_MIN_REMAIN_ADDR                                            \
+	(BIT_MASK_QD_CPL_MIN_REMAIN_ADDR << BIT_SHIFT_QD_CPL_MIN_REMAIN_ADDR)
+#define BIT_CLEAR_QD_CPL_MIN_REMAIN_ADDR(x)                                    \
+	((x) & (~BITS_QD_CPL_MIN_REMAIN_ADDR))
+#define BIT_GET_QD_CPL_MIN_REMAIN_ADDR(x)                                      \
+	(((x) >> BIT_SHIFT_QD_CPL_MIN_REMAIN_ADDR) &                           \
+	 BIT_MASK_QD_CPL_MIN_REMAIN_ADDR)
+#define BIT_SET_QD_CPL_MIN_REMAIN_ADDR(x, v)                                   \
+	(BIT_CLEAR_QD_CPL_MIN_REMAIN_ADDR(x) | BIT_QD_CPL_MIN_REMAIN_ADDR(v))
+
+#define BIT_SHIFT_QD_CPL_CUR_REMAIN_ADDR 0
+#define BIT_MASK_QD_CPL_CUR_REMAIN_ADDR 0xff
+#define BIT_QD_CPL_CUR_REMAIN_ADDR(x)                                          \
+	(((x) & BIT_MASK_QD_CPL_CUR_REMAIN_ADDR)                               \
+	 << BIT_SHIFT_QD_CPL_CUR_REMAIN_ADDR)
+#define BITS_QD_CPL_CUR_REMAIN_ADDR                                            \
+	(BIT_MASK_QD_CPL_CUR_REMAIN_ADDR << BIT_SHIFT_QD_CPL_CUR_REMAIN_ADDR)
+#define BIT_CLEAR_QD_CPL_CUR_REMAIN_ADDR(x)                                    \
+	((x) & (~BITS_QD_CPL_CUR_REMAIN_ADDR))
+#define BIT_GET_QD_CPL_CUR_REMAIN_ADDR(x)                                      \
+	(((x) >> BIT_SHIFT_QD_CPL_CUR_REMAIN_ADDR) &                           \
+	 BIT_MASK_QD_CPL_CUR_REMAIN_ADDR)
+#define BIT_SET_QD_CPL_CUR_REMAIN_ADDR(x, v)                                   \
+	(BIT_CLEAR_QD_CPL_CUR_REMAIN_ADDR(x) | BIT_QD_CPL_CUR_REMAIN_ADDR(v))
+
+#define BIT_SHIFT_PTM_LOCAL_CLOCK 0
+#define BIT_MASK_PTM_LOCAL_CLOCK 0xffffffffL
+#define BIT_PTM_LOCAL_CLOCK(x)                                                 \
+	(((x) & BIT_MASK_PTM_LOCAL_CLOCK) << BIT_SHIFT_PTM_LOCAL_CLOCK)
+#define BITS_PTM_LOCAL_CLOCK                                                   \
+	(BIT_MASK_PTM_LOCAL_CLOCK << BIT_SHIFT_PTM_LOCAL_CLOCK)
+#define BIT_CLEAR_PTM_LOCAL_CLOCK(x) ((x) & (~BITS_PTM_LOCAL_CLOCK))
+#define BIT_GET_PTM_LOCAL_CLOCK(x)                                             \
+	(((x) >> BIT_SHIFT_PTM_LOCAL_CLOCK) & BIT_MASK_PTM_LOCAL_CLOCK)
+#define BIT_SET_PTM_LOCAL_CLOCK(x, v)                                          \
+	(BIT_CLEAR_PTM_LOCAL_CLOCK(x) | BIT_PTM_LOCAL_CLOCK(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_P0HI13Q_TXBD_IDX			(Offset 0x1344) */
+
+#define BIT_SHIFT_P0HI13Q_HOST_IDX 0
+#define BIT_MASK_P0HI13Q_HOST_IDX 0xfff
+#define BIT_P0HI13Q_HOST_IDX(x)                                                \
+	(((x) & BIT_MASK_P0HI13Q_HOST_IDX) << BIT_SHIFT_P0HI13Q_HOST_IDX)
+#define BITS_P0HI13Q_HOST_IDX                                                  \
+	(BIT_MASK_P0HI13Q_HOST_IDX << BIT_SHIFT_P0HI13Q_HOST_IDX)
+#define BIT_CLEAR_P0HI13Q_HOST_IDX(x) ((x) & (~BITS_P0HI13Q_HOST_IDX))
+#define BIT_GET_P0HI13Q_HOST_IDX(x)                                            \
+	(((x) >> BIT_SHIFT_P0HI13Q_HOST_IDX) & BIT_MASK_P0HI13Q_HOST_IDX)
+#define BIT_SET_P0HI13Q_HOST_IDX(x, v)                                         \
+	(BIT_CLEAR_P0HI13Q_HOST_IDX(x) | BIT_P0HI13Q_HOST_IDX(v))
+
+/* 2 REG_P0HI14Q_TXBD_IDX			(Offset 0x1348) */
+
+#define BIT_SHIFT_P0HI14Q_HW_IDX 16
+#define BIT_MASK_P0HI14Q_HW_IDX 0xfff
+#define BIT_P0HI14Q_HW_IDX(x)                                                  \
+	(((x) & BIT_MASK_P0HI14Q_HW_IDX) << BIT_SHIFT_P0HI14Q_HW_IDX)
+#define BITS_P0HI14Q_HW_IDX                                                    \
+	(BIT_MASK_P0HI14Q_HW_IDX << BIT_SHIFT_P0HI14Q_HW_IDX)
+#define BIT_CLEAR_P0HI14Q_HW_IDX(x) ((x) & (~BITS_P0HI14Q_HW_IDX))
+#define BIT_GET_P0HI14Q_HW_IDX(x)                                              \
+	(((x) >> BIT_SHIFT_P0HI14Q_HW_IDX) & BIT_MASK_P0HI14Q_HW_IDX)
+#define BIT_SET_P0HI14Q_HW_IDX(x, v)                                           \
+	(BIT_CLEAR_P0HI14Q_HW_IDX(x) | BIT_P0HI14Q_HW_IDX(v))
+
+#define BIT_SHIFT_P0HI14Q_HOST_IDX 0
+#define BIT_MASK_P0HI14Q_HOST_IDX 0xfff
+#define BIT_P0HI14Q_HOST_IDX(x)                                                \
+	(((x) & BIT_MASK_P0HI14Q_HOST_IDX) << BIT_SHIFT_P0HI14Q_HOST_IDX)
+#define BITS_P0HI14Q_HOST_IDX                                                  \
+	(BIT_MASK_P0HI14Q_HOST_IDX << BIT_SHIFT_P0HI14Q_HOST_IDX)
+#define BIT_CLEAR_P0HI14Q_HOST_IDX(x) ((x) & (~BITS_P0HI14Q_HOST_IDX))
+#define BIT_GET_P0HI14Q_HOST_IDX(x)                                            \
+	(((x) >> BIT_SHIFT_P0HI14Q_HOST_IDX) & BIT_MASK_P0HI14Q_HOST_IDX)
+#define BIT_SET_P0HI14Q_HOST_IDX(x, v)                                         \
+	(BIT_CLEAR_P0HI14Q_HOST_IDX(x) | BIT_P0HI14Q_HOST_IDX(v))
+
+/* 2 REG_P0HI15Q_TXBD_IDX			(Offset 0x134C) */
+
+#define BIT_SHIFT_P0HI15Q_HW_IDX 16
+#define BIT_MASK_P0HI15Q_HW_IDX 0xfff
+#define BIT_P0HI15Q_HW_IDX(x)                                                  \
+	(((x) & BIT_MASK_P0HI15Q_HW_IDX) << BIT_SHIFT_P0HI15Q_HW_IDX)
+#define BITS_P0HI15Q_HW_IDX                                                    \
+	(BIT_MASK_P0HI15Q_HW_IDX << BIT_SHIFT_P0HI15Q_HW_IDX)
+#define BIT_CLEAR_P0HI15Q_HW_IDX(x) ((x) & (~BITS_P0HI15Q_HW_IDX))
+#define BIT_GET_P0HI15Q_HW_IDX(x)                                              \
+	(((x) >> BIT_SHIFT_P0HI15Q_HW_IDX) & BIT_MASK_P0HI15Q_HW_IDX)
+#define BIT_SET_P0HI15Q_HW_IDX(x, v)                                           \
+	(BIT_CLEAR_P0HI15Q_HW_IDX(x) | BIT_P0HI15Q_HW_IDX(v))
+
+#define BIT_SHIFT_P0HI15Q_HOST_IDX 0
+#define BIT_MASK_P0HI15Q_HOST_IDX 0xfff
+#define BIT_P0HI15Q_HOST_IDX(x)                                                \
+	(((x) & BIT_MASK_P0HI15Q_HOST_IDX) << BIT_SHIFT_P0HI15Q_HOST_IDX)
+#define BITS_P0HI15Q_HOST_IDX                                                  \
+	(BIT_MASK_P0HI15Q_HOST_IDX << BIT_SHIFT_P0HI15Q_HOST_IDX)
+#define BIT_CLEAR_P0HI15Q_HOST_IDX(x) ((x) & (~BITS_P0HI15Q_HOST_IDX))
+#define BIT_GET_P0HI15Q_HOST_IDX(x)                                            \
+	(((x) >> BIT_SHIFT_P0HI15Q_HOST_IDX) & BIT_MASK_P0HI15Q_HOST_IDX)
+#define BIT_SET_P0HI15Q_HOST_IDX(x, v)                                         \
+	(BIT_CLEAR_P0HI15Q_HOST_IDX(x) | BIT_P0HI15Q_HOST_IDX(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_AXI_EXCEPT_CS			(Offset 0x1350) */
+
+#define BIT_AXI_RXDMA_TIMEOUT_RE BIT(21)
+#define BIT_AXI_TXDMA_TIMEOUT_RE BIT(20)
+#define BIT_AXI_DECERR_W_RE BIT(19)
+#define BIT_AXI_DECERR_R_RE BIT(18)
+
+#endif
+
+#if (HALMAC_8822B_SUPPORT)
+
+/* 2 REG_CHANGE_PCIE_SPEED			(Offset 0x1350) */
+
+#define BIT_CHANGE_PCIE_SPEED BIT(18)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_AXI_EXCEPT_CS			(Offset 0x1350) */
+
+#define BIT_AXI_SLVERR_W_RE BIT(17)
+#define BIT_AXI_SLVERR_R_RE BIT(16)
+
+#endif
+
+#if (HALMAC_8822B_SUPPORT)
+
+/* 2 REG_CHANGE_PCIE_SPEED			(Offset 0x1350) */
+
+#define BIT_SHIFT_GEN1_GEN2 16
+#define BIT_MASK_GEN1_GEN2 0x3
+#define BIT_GEN1_GEN2(x) (((x) & BIT_MASK_GEN1_GEN2) << BIT_SHIFT_GEN1_GEN2)
+#define BITS_GEN1_GEN2 (BIT_MASK_GEN1_GEN2 << BIT_SHIFT_GEN1_GEN2)
+#define BIT_CLEAR_GEN1_GEN2(x) ((x) & (~BITS_GEN1_GEN2))
+#define BIT_GET_GEN1_GEN2(x) (((x) >> BIT_SHIFT_GEN1_GEN2) & BIT_MASK_GEN1_GEN2)
+#define BIT_SET_GEN1_GEN2(x, v) (BIT_CLEAR_GEN1_GEN2(x) | BIT_GEN1_GEN2(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_AXI_EXCEPT_CS			(Offset 0x1350) */
+
+#define BIT_AXI_RXDMA_TIMEOUT_IE BIT(13)
+#define BIT_AXI_TXDMA_TIMEOUT_IE BIT(12)
+#define BIT_AXI_DECERR_W_IE BIT(11)
+#define BIT_AXI_DECERR_R_IE BIT(10)
+#define BIT_AXI_SLVERR_W_IE BIT(9)
+#define BIT_AXI_SLVERR_R_IE BIT(8)
+
+#endif
+
+#if (HALMAC_8822B_SUPPORT)
+
+/* 2 REG_CHANGE_PCIE_SPEED			(Offset 0x1350) */
+
+#define BIT_SHIFT_RXDMA_ERROR_COUNTER 8
+#define BIT_MASK_RXDMA_ERROR_COUNTER 0xff
+#define BIT_RXDMA_ERROR_COUNTER(x)                                             \
+	(((x) & BIT_MASK_RXDMA_ERROR_COUNTER) << BIT_SHIFT_RXDMA_ERROR_COUNTER)
+#define BITS_RXDMA_ERROR_COUNTER                                               \
+	(BIT_MASK_RXDMA_ERROR_COUNTER << BIT_SHIFT_RXDMA_ERROR_COUNTER)
+#define BIT_CLEAR_RXDMA_ERROR_COUNTER(x) ((x) & (~BITS_RXDMA_ERROR_COUNTER))
+#define BIT_GET_RXDMA_ERROR_COUNTER(x)                                         \
+	(((x) >> BIT_SHIFT_RXDMA_ERROR_COUNTER) & BIT_MASK_RXDMA_ERROR_COUNTER)
+#define BIT_SET_RXDMA_ERROR_COUNTER(x, v)                                      \
+	(BIT_CLEAR_RXDMA_ERROR_COUNTER(x) | BIT_RXDMA_ERROR_COUNTER(v))
+
+#define BIT_TXDMA_ERROR_HANDLE_STATUS BIT(7)
+#define BIT_TXDMA_ERROR_PULSE BIT(6)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_AXI_EXCEPT_CS			(Offset 0x1350) */
+
+#define BIT_AXI_RXDMA_TIMEOUT_FLAG BIT(5)
+
+#endif
+
+#if (HALMAC_8822B_SUPPORT)
+
+/* 2 REG_CHANGE_PCIE_SPEED			(Offset 0x1350) */
+
+#define BIT_TXDMA_STUCK_ERROR_HANDLE_ENABLE BIT(5)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_AXI_EXCEPT_CS			(Offset 0x1350) */
+
+#define BIT_AXI_TXDMA_TIMEOUT_FLAG BIT(4)
+
+#endif
+
+#if (HALMAC_8822B_SUPPORT)
+
+/* 2 REG_CHANGE_PCIE_SPEED			(Offset 0x1350) */
+
+#define BIT_TXDMA_RETURN_ERROR_ENABLE BIT(4)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_AXI_EXCEPT_CS			(Offset 0x1350) */
+
+#define BIT_AXI_DECERR_W_FLAG BIT(3)
+
+#endif
+
+#if (HALMAC_8822B_SUPPORT)
+
+/* 2 REG_CHANGE_PCIE_SPEED			(Offset 0x1350) */
+
+#define BIT_RXDMA_ERROR_HANDLE_STATUS BIT(3)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_AXI_EXCEPT_CS			(Offset 0x1350) */
+
+#define BIT_AXI_DECERR_R_FLAG BIT(2)
+#define BIT_AXI_SLVERR_W_FLAG BIT(1)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_TSFT_PTM_DIFF			(Offset 0x1350) */
+
+#define BIT_SHIFT_TSFT_PTM_DIFF 0
+#define BIT_MASK_TSFT_PTM_DIFF 0xffffffffL
+#define BIT_TSFT_PTM_DIFF(x)                                                   \
+	(((x) & BIT_MASK_TSFT_PTM_DIFF) << BIT_SHIFT_TSFT_PTM_DIFF)
+#define BITS_TSFT_PTM_DIFF (BIT_MASK_TSFT_PTM_DIFF << BIT_SHIFT_TSFT_PTM_DIFF)
+#define BIT_CLEAR_TSFT_PTM_DIFF(x) ((x) & (~BITS_TSFT_PTM_DIFF))
+#define BIT_GET_TSFT_PTM_DIFF(x)                                               \
+	(((x) >> BIT_SHIFT_TSFT_PTM_DIFF) & BIT_MASK_TSFT_PTM_DIFF)
+#define BIT_SET_TSFT_PTM_DIFF(x, v)                                            \
+	(BIT_CLEAR_TSFT_PTM_DIFF(x) | BIT_TSFT_PTM_DIFF(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_AXI_EXCEPT_CS			(Offset 0x1350) */
+
+#define BIT_AXI_SLVERR_R_FLAG BIT(0)
+
+#endif
+
+#if (HALMAC_8822B_SUPPORT)
+
+/* 2 REG_CHANGE_PCIE_SPEED			(Offset 0x1350) */
+
+#define BIT_SHIFT_AUTO_HANG_RELEASE 0
+#define BIT_MASK_AUTO_HANG_RELEASE 0x7
+#define BIT_AUTO_HANG_RELEASE(x)                                               \
+	(((x) & BIT_MASK_AUTO_HANG_RELEASE) << BIT_SHIFT_AUTO_HANG_RELEASE)
+#define BITS_AUTO_HANG_RELEASE                                                 \
+	(BIT_MASK_AUTO_HANG_RELEASE << BIT_SHIFT_AUTO_HANG_RELEASE)
+#define BIT_CLEAR_AUTO_HANG_RELEASE(x) ((x) & (~BITS_AUTO_HANG_RELEASE))
+#define BIT_GET_AUTO_HANG_RELEASE(x)                                           \
+	(((x) >> BIT_SHIFT_AUTO_HANG_RELEASE) & BIT_MASK_AUTO_HANG_RELEASE)
+#define BIT_SET_AUTO_HANG_RELEASE(x, v)                                        \
+	(BIT_CLEAR_AUTO_HANG_RELEASE(x) | BIT_AUTO_HANG_RELEASE(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_AXI_EXCEPT_TIME			(Offset 0x1354) */
+
+#define BIT_SHIFT_AXI_RECOVERY_TIME 24
+#define BIT_MASK_AXI_RECOVERY_TIME 0xff
+#define BIT_AXI_RECOVERY_TIME(x)                                               \
+	(((x) & BIT_MASK_AXI_RECOVERY_TIME) << BIT_SHIFT_AXI_RECOVERY_TIME)
+#define BITS_AXI_RECOVERY_TIME                                                 \
+	(BIT_MASK_AXI_RECOVERY_TIME << BIT_SHIFT_AXI_RECOVERY_TIME)
+#define BIT_CLEAR_AXI_RECOVERY_TIME(x) ((x) & (~BITS_AXI_RECOVERY_TIME))
+#define BIT_GET_AXI_RECOVERY_TIME(x)                                           \
+	(((x) >> BIT_SHIFT_AXI_RECOVERY_TIME) & BIT_MASK_AXI_RECOVERY_TIME)
+#define BIT_SET_AXI_RECOVERY_TIME(x, v)                                        \
+	(BIT_CLEAR_AXI_RECOVERY_TIME(x) | BIT_AXI_RECOVERY_TIME(v))
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_PTM_CTRL_STATUS			(Offset 0x1354) */
+
+#define BIT_BCNQ2_EMPTY BIT(23)
+#define BIT_BCNQ1_EMPTY BIT(22)
+#define BIT_BCNQ0_EMPTY BIT(21)
+#define BIT_EVTQ_EMPTY BIT(20)
+#define BIT_MGQ_CPU_EMPTY_V2 BIT(19)
+#define BIT_BCNQ_EMPTY_V2 BIT(18)
+#define BIT_HQQ_EMPTY_V2 BIT(17)
+
+#define BIT_SHIFT_TAIL_PKT_V1 16
+#define BIT_MASK_TAIL_PKT_V1 0xff
+#define BIT_TAIL_PKT_V1(x)                                                     \
+	(((x) & BIT_MASK_TAIL_PKT_V1) << BIT_SHIFT_TAIL_PKT_V1)
+#define BITS_TAIL_PKT_V1 (BIT_MASK_TAIL_PKT_V1 << BIT_SHIFT_TAIL_PKT_V1)
+#define BIT_CLEAR_TAIL_PKT_V1(x) ((x) & (~BITS_TAIL_PKT_V1))
+#define BIT_GET_TAIL_PKT_V1(x)                                                 \
+	(((x) >> BIT_SHIFT_TAIL_PKT_V1) & BIT_MASK_TAIL_PKT_V1)
+#define BIT_SET_TAIL_PKT_V1(x, v)                                              \
+	(BIT_CLEAR_TAIL_PKT_V1(x) | BIT_TAIL_PKT_V1(v))
+
+#define BIT_MQQ_EMPTY_V3 BIT(16)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_AXI_EXCEPT_TIME			(Offset 0x1354) */
+
+#define BIT_SHIFT_AXI_RXDMA_TIMEOUT_VAL 12
+#define BIT_MASK_AXI_RXDMA_TIMEOUT_VAL 0xfff
+#define BIT_AXI_RXDMA_TIMEOUT_VAL(x)                                           \
+	(((x) & BIT_MASK_AXI_RXDMA_TIMEOUT_VAL)                                \
+	 << BIT_SHIFT_AXI_RXDMA_TIMEOUT_VAL)
+#define BITS_AXI_RXDMA_TIMEOUT_VAL                                             \
+	(BIT_MASK_AXI_RXDMA_TIMEOUT_VAL << BIT_SHIFT_AXI_RXDMA_TIMEOUT_VAL)
+#define BIT_CLEAR_AXI_RXDMA_TIMEOUT_VAL(x) ((x) & (~BITS_AXI_RXDMA_TIMEOUT_VAL))
+#define BIT_GET_AXI_RXDMA_TIMEOUT_VAL(x)                                       \
+	(((x) >> BIT_SHIFT_AXI_RXDMA_TIMEOUT_VAL) &                            \
+	 BIT_MASK_AXI_RXDMA_TIMEOUT_VAL)
+#define BIT_SET_AXI_RXDMA_TIMEOUT_VAL(x, v)                                    \
+	(BIT_CLEAR_AXI_RXDMA_TIMEOUT_VAL(x) | BIT_AXI_RXDMA_TIMEOUT_VAL(v))
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_PTM_CTRL_STATUS			(Offset 0x1354) */
+
+#define BIT_SHIFT_PKT_NUM_V1 8
+#define BIT_MASK_PKT_NUM_V1 0xff
+#define BIT_PKT_NUM_V1(x) (((x) & BIT_MASK_PKT_NUM_V1) << BIT_SHIFT_PKT_NUM_V1)
+#define BITS_PKT_NUM_V1 (BIT_MASK_PKT_NUM_V1 << BIT_SHIFT_PKT_NUM_V1)
+#define BIT_CLEAR_PKT_NUM_V1(x) ((x) & (~BITS_PKT_NUM_V1))
+#define BIT_GET_PKT_NUM_V1(x)                                                  \
+	(((x) >> BIT_SHIFT_PKT_NUM_V1) & BIT_MASK_PKT_NUM_V1)
+#define BIT_SET_PKT_NUM_V1(x, v) (BIT_CLEAR_PKT_NUM_V1(x) | BIT_PKT_NUM_V1(v))
+
+#define BIT_SHIFT_QUEUEAC_V1 8
+#define BIT_MASK_QUEUEAC_V1 0x3
+#define BIT_QUEUEAC_V1(x) (((x) & BIT_MASK_QUEUEAC_V1) << BIT_SHIFT_QUEUEAC_V1)
+#define BITS_QUEUEAC_V1 (BIT_MASK_QUEUEAC_V1 << BIT_SHIFT_QUEUEAC_V1)
+#define BIT_CLEAR_QUEUEAC_V1(x) ((x) & (~BITS_QUEUEAC_V1))
+#define BIT_GET_QUEUEAC_V1(x)                                                  \
+	(((x) >> BIT_SHIFT_QUEUEAC_V1) & BIT_MASK_QUEUEAC_V1)
+#define BIT_SET_QUEUEAC_V1(x, v) (BIT_CLEAR_QUEUEAC_V1(x) | BIT_QUEUEAC_V1(v))
+
+#define BIT_SHIFT_ACQ_STOP 5
+#define BIT_MASK_ACQ_STOP 0xffff
+#define BIT_ACQ_STOP(x) (((x) & BIT_MASK_ACQ_STOP) << BIT_SHIFT_ACQ_STOP)
+#define BITS_ACQ_STOP (BIT_MASK_ACQ_STOP << BIT_SHIFT_ACQ_STOP)
+#define BIT_CLEAR_ACQ_STOP(x) ((x) & (~BITS_ACQ_STOP))
+#define BIT_GET_ACQ_STOP(x) (((x) >> BIT_SHIFT_ACQ_STOP) & BIT_MASK_ACQ_STOP)
+#define BIT_SET_ACQ_STOP(x, v) (BIT_CLEAR_ACQ_STOP(x) | BIT_ACQ_STOP(v))
+
+#define BIT_SHIFT_TSFT_PORT_SEL 3
+#define BIT_MASK_TSFT_PORT_SEL 0x3
+#define BIT_TSFT_PORT_SEL(x)                                                   \
+	(((x) & BIT_MASK_TSFT_PORT_SEL) << BIT_SHIFT_TSFT_PORT_SEL)
+#define BITS_TSFT_PORT_SEL (BIT_MASK_TSFT_PORT_SEL << BIT_SHIFT_TSFT_PORT_SEL)
+#define BIT_CLEAR_TSFT_PORT_SEL(x) ((x) & (~BITS_TSFT_PORT_SEL))
+#define BIT_GET_TSFT_PORT_SEL(x)                                               \
+	(((x) >> BIT_SHIFT_TSFT_PORT_SEL) & BIT_MASK_TSFT_PORT_SEL)
+#define BIT_SET_TSFT_PORT_SEL(x, v)                                            \
+	(BIT_CLEAR_TSFT_PORT_SEL(x) | BIT_TSFT_PORT_SEL(v))
+
+#define BIT_PTM_CONTEXT_VALID BIT(2)
+#define BIT_PTM_MANUL_UPDATE BIT(1)
+#define BIT_PTM_AUTO_UPDATE BIT(0)
+
+#define BIT_SHIFT_HEAD_PKT_V1 0
+#define BIT_MASK_HEAD_PKT_V1 0xff
+#define BIT_HEAD_PKT_V1(x)                                                     \
+	(((x) & BIT_MASK_HEAD_PKT_V1) << BIT_SHIFT_HEAD_PKT_V1)
+#define BITS_HEAD_PKT_V1 (BIT_MASK_HEAD_PKT_V1 << BIT_SHIFT_HEAD_PKT_V1)
+#define BIT_CLEAR_HEAD_PKT_V1(x) ((x) & (~BITS_HEAD_PKT_V1))
+#define BIT_GET_HEAD_PKT_V1(x)                                                 \
+	(((x) >> BIT_SHIFT_HEAD_PKT_V1) & BIT_MASK_HEAD_PKT_V1)
+#define BIT_SET_HEAD_PKT_V1(x, v)                                              \
+	(BIT_CLEAR_HEAD_PKT_V1(x) | BIT_HEAD_PKT_V1(v))
+
+#define BIT_SHIFT_QUEUEMACID_V1 0
+#define BIT_MASK_QUEUEMACID_V1 0x7f
+#define BIT_QUEUEMACID_V1(x)                                                   \
+	(((x) & BIT_MASK_QUEUEMACID_V1) << BIT_SHIFT_QUEUEMACID_V1)
+#define BITS_QUEUEMACID_V1 (BIT_MASK_QUEUEMACID_V1 << BIT_SHIFT_QUEUEMACID_V1)
+#define BIT_CLEAR_QUEUEMACID_V1(x) ((x) & (~BITS_QUEUEMACID_V1))
+#define BIT_GET_QUEUEMACID_V1(x)                                               \
+	(((x) >> BIT_SHIFT_QUEUEMACID_V1) & BIT_MASK_QUEUEMACID_V1)
+#define BIT_SET_QUEUEMACID_V1(x, v)                                            \
+	(BIT_CLEAR_QUEUEMACID_V1(x) | BIT_QUEUEMACID_V1(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_AXI_EXCEPT_TIME			(Offset 0x1354) */
+
+#define BIT_SHIFT_AXI_TXDMA_TIMEOUT_VAL 0
+#define BIT_MASK_AXI_TXDMA_TIMEOUT_VAL 0xfff
+#define BIT_AXI_TXDMA_TIMEOUT_VAL(x)                                           \
+	(((x) & BIT_MASK_AXI_TXDMA_TIMEOUT_VAL)                                \
+	 << BIT_SHIFT_AXI_TXDMA_TIMEOUT_VAL)
+#define BITS_AXI_TXDMA_TIMEOUT_VAL                                             \
+	(BIT_MASK_AXI_TXDMA_TIMEOUT_VAL << BIT_SHIFT_AXI_TXDMA_TIMEOUT_VAL)
+#define BIT_CLEAR_AXI_TXDMA_TIMEOUT_VAL(x) ((x) & (~BITS_AXI_TXDMA_TIMEOUT_VAL))
+#define BIT_GET_AXI_TXDMA_TIMEOUT_VAL(x)                                       \
+	(((x) >> BIT_SHIFT_AXI_TXDMA_TIMEOUT_VAL) &                            \
+	 BIT_MASK_AXI_TXDMA_TIMEOUT_VAL)
+#define BIT_SET_AXI_TXDMA_TIMEOUT_VAL(x, v)                                    \
+	(BIT_CLEAR_AXI_TXDMA_TIMEOUT_VAL(x) | BIT_AXI_TXDMA_TIMEOUT_VAL(v))
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_DEBUG_STATE1			(Offset 0x1354) */
+
+#define BIT_SHIFT_DEBUG_STATE1 0
+#define BIT_MASK_DEBUG_STATE1 0xffffffffL
+#define BIT_DEBUG_STATE1(x)                                                    \
+	(((x) & BIT_MASK_DEBUG_STATE1) << BIT_SHIFT_DEBUG_STATE1)
+#define BITS_DEBUG_STATE1 (BIT_MASK_DEBUG_STATE1 << BIT_SHIFT_DEBUG_STATE1)
+#define BIT_CLEAR_DEBUG_STATE1(x) ((x) & (~BITS_DEBUG_STATE1))
+#define BIT_GET_DEBUG_STATE1(x)                                                \
+	(((x) >> BIT_SHIFT_DEBUG_STATE1) & BIT_MASK_DEBUG_STATE1)
+#define BIT_SET_DEBUG_STATE1(x, v)                                             \
+	(BIT_CLEAR_DEBUG_STATE1(x) | BIT_DEBUG_STATE1(v))
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+/* 2 REG_HI8Q_TXBD_IDX			(Offset 0x1358) */
+
+#define BIT_SHIFT_HI8Q_HW_IDX 16
+#define BIT_MASK_HI8Q_HW_IDX 0xfff
+#define BIT_HI8Q_HW_IDX(x)                                                     \
+	(((x) & BIT_MASK_HI8Q_HW_IDX) << BIT_SHIFT_HI8Q_HW_IDX)
+#define BITS_HI8Q_HW_IDX (BIT_MASK_HI8Q_HW_IDX << BIT_SHIFT_HI8Q_HW_IDX)
+#define BIT_CLEAR_HI8Q_HW_IDX(x) ((x) & (~BITS_HI8Q_HW_IDX))
+#define BIT_GET_HI8Q_HW_IDX(x)                                                 \
+	(((x) >> BIT_SHIFT_HI8Q_HW_IDX) & BIT_MASK_HI8Q_HW_IDX)
+#define BIT_SET_HI8Q_HW_IDX(x, v)                                              \
+	(BIT_CLEAR_HI8Q_HW_IDX(x) | BIT_HI8Q_HW_IDX(v))
+
+#define BIT_SHIFT_HI8Q_HOST_IDX 0
+#define BIT_MASK_HI8Q_HOST_IDX 0xfff
+#define BIT_HI8Q_HOST_IDX(x)                                                   \
+	(((x) & BIT_MASK_HI8Q_HOST_IDX) << BIT_SHIFT_HI8Q_HOST_IDX)
+#define BITS_HI8Q_HOST_IDX (BIT_MASK_HI8Q_HOST_IDX << BIT_SHIFT_HI8Q_HOST_IDX)
+#define BIT_CLEAR_HI8Q_HOST_IDX(x) ((x) & (~BITS_HI8Q_HOST_IDX))
+#define BIT_GET_HI8Q_HOST_IDX(x)                                               \
+	(((x) >> BIT_SHIFT_HI8Q_HOST_IDX) & BIT_MASK_HI8Q_HOST_IDX)
+#define BIT_SET_HI8Q_HOST_IDX(x, v)                                            \
+	(BIT_CLEAR_HI8Q_HOST_IDX(x) | BIT_HI8Q_HOST_IDX(v))
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_DEBUG_STATE2			(Offset 0x1358) */
+
+#define BIT_SHIFT_DEBUG_STATE2 0
+#define BIT_MASK_DEBUG_STATE2 0xffffffffL
+#define BIT_DEBUG_STATE2(x)                                                    \
+	(((x) & BIT_MASK_DEBUG_STATE2) << BIT_SHIFT_DEBUG_STATE2)
+#define BITS_DEBUG_STATE2 (BIT_MASK_DEBUG_STATE2 << BIT_SHIFT_DEBUG_STATE2)
+#define BIT_CLEAR_DEBUG_STATE2(x) ((x) & (~BITS_DEBUG_STATE2))
+#define BIT_GET_DEBUG_STATE2(x)                                                \
+	(((x) >> BIT_SHIFT_DEBUG_STATE2) & BIT_MASK_DEBUG_STATE2)
+#define BIT_SET_DEBUG_STATE2(x, v)                                             \
+	(BIT_CLEAR_DEBUG_STATE2(x) | BIT_DEBUG_STATE2(v))
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+/* 2 REG_HI9Q_TXBD_IDX			(Offset 0x135C) */
+
+#define BIT_SHIFT_HI9Q_HW_IDX 16
+#define BIT_MASK_HI9Q_HW_IDX 0xfff
+#define BIT_HI9Q_HW_IDX(x)                                                     \
+	(((x) & BIT_MASK_HI9Q_HW_IDX) << BIT_SHIFT_HI9Q_HW_IDX)
+#define BITS_HI9Q_HW_IDX (BIT_MASK_HI9Q_HW_IDX << BIT_SHIFT_HI9Q_HW_IDX)
+#define BIT_CLEAR_HI9Q_HW_IDX(x) ((x) & (~BITS_HI9Q_HW_IDX))
+#define BIT_GET_HI9Q_HW_IDX(x)                                                 \
+	(((x) >> BIT_SHIFT_HI9Q_HW_IDX) & BIT_MASK_HI9Q_HW_IDX)
+#define BIT_SET_HI9Q_HW_IDX(x, v)                                              \
+	(BIT_CLEAR_HI9Q_HW_IDX(x) | BIT_HI9Q_HW_IDX(v))
+
+#define BIT_SHIFT_HI9Q_HOST_IDX 0
+#define BIT_MASK_HI9Q_HOST_IDX 0xfff
+#define BIT_HI9Q_HOST_IDX(x)                                                   \
+	(((x) & BIT_MASK_HI9Q_HOST_IDX) << BIT_SHIFT_HI9Q_HOST_IDX)
+#define BITS_HI9Q_HOST_IDX (BIT_MASK_HI9Q_HOST_IDX << BIT_SHIFT_HI9Q_HOST_IDX)
+#define BIT_CLEAR_HI9Q_HOST_IDX(x) ((x) & (~BITS_HI9Q_HOST_IDX))
+#define BIT_GET_HI9Q_HOST_IDX(x)                                               \
+	(((x) >> BIT_SHIFT_HI9Q_HOST_IDX) & BIT_MASK_HI9Q_HOST_IDX)
+#define BIT_SET_HI9Q_HOST_IDX(x, v)                                            \
+	(BIT_CLEAR_HI9Q_HOST_IDX(x) | BIT_HI9Q_HOST_IDX(v))
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_DEBUG_STATE3			(Offset 0x135C) */
+
+#define BIT_SHIFT_DEBUG_STATE3 0
+#define BIT_MASK_DEBUG_STATE3 0xffffffffL
+#define BIT_DEBUG_STATE3(x)                                                    \
+	(((x) & BIT_MASK_DEBUG_STATE3) << BIT_SHIFT_DEBUG_STATE3)
+#define BITS_DEBUG_STATE3 (BIT_MASK_DEBUG_STATE3 << BIT_SHIFT_DEBUG_STATE3)
+#define BIT_CLEAR_DEBUG_STATE3(x) ((x) & (~BITS_DEBUG_STATE3))
+#define BIT_GET_DEBUG_STATE3(x)                                                \
+	(((x) >> BIT_SHIFT_DEBUG_STATE3) & BIT_MASK_DEBUG_STATE3)
+#define BIT_SET_DEBUG_STATE3(x, v)                                             \
+	(BIT_CLEAR_DEBUG_STATE3(x) | BIT_DEBUG_STATE3(v))
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+/* 2 REG_HI10Q_TXBD_IDX			(Offset 0x1360) */
+
+#define BIT_SHIFT_HI10Q_HW_IDX 16
+#define BIT_MASK_HI10Q_HW_IDX 0xfff
+#define BIT_HI10Q_HW_IDX(x)                                                    \
+	(((x) & BIT_MASK_HI10Q_HW_IDX) << BIT_SHIFT_HI10Q_HW_IDX)
+#define BITS_HI10Q_HW_IDX (BIT_MASK_HI10Q_HW_IDX << BIT_SHIFT_HI10Q_HW_IDX)
+#define BIT_CLEAR_HI10Q_HW_IDX(x) ((x) & (~BITS_HI10Q_HW_IDX))
+#define BIT_GET_HI10Q_HW_IDX(x)                                                \
+	(((x) >> BIT_SHIFT_HI10Q_HW_IDX) & BIT_MASK_HI10Q_HW_IDX)
+#define BIT_SET_HI10Q_HW_IDX(x, v)                                             \
+	(BIT_CLEAR_HI10Q_HW_IDX(x) | BIT_HI10Q_HW_IDX(v))
+
+#define BIT_SHIFT_HI10Q_HOST_IDX 0
+#define BIT_MASK_HI10Q_HOST_IDX 0xfff
+#define BIT_HI10Q_HOST_IDX(x)                                                  \
+	(((x) & BIT_MASK_HI10Q_HOST_IDX) << BIT_SHIFT_HI10Q_HOST_IDX)
+#define BITS_HI10Q_HOST_IDX                                                    \
+	(BIT_MASK_HI10Q_HOST_IDX << BIT_SHIFT_HI10Q_HOST_IDX)
+#define BIT_CLEAR_HI10Q_HOST_IDX(x) ((x) & (~BITS_HI10Q_HOST_IDX))
+#define BIT_GET_HI10Q_HOST_IDX(x)                                              \
+	(((x) >> BIT_SHIFT_HI10Q_HOST_IDX) & BIT_MASK_HI10Q_HOST_IDX)
+#define BIT_SET_HI10Q_HOST_IDX(x, v)                                           \
+	(BIT_CLEAR_HI10Q_HOST_IDX(x) | BIT_HI10Q_HOST_IDX(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_ACH5_TXBD_DESA_L			(Offset 0x1360) */
+
+#define BIT_SHIFT_ACH5_TXBD_DESA_L 0
+#define BIT_MASK_ACH5_TXBD_DESA_L 0xffffffffL
+#define BIT_ACH5_TXBD_DESA_L(x)                                                \
+	(((x) & BIT_MASK_ACH5_TXBD_DESA_L) << BIT_SHIFT_ACH5_TXBD_DESA_L)
+#define BITS_ACH5_TXBD_DESA_L                                                  \
+	(BIT_MASK_ACH5_TXBD_DESA_L << BIT_SHIFT_ACH5_TXBD_DESA_L)
+#define BIT_CLEAR_ACH5_TXBD_DESA_L(x) ((x) & (~BITS_ACH5_TXBD_DESA_L))
+#define BIT_GET_ACH5_TXBD_DESA_L(x)                                            \
+	(((x) >> BIT_SHIFT_ACH5_TXBD_DESA_L) & BIT_MASK_ACH5_TXBD_DESA_L)
+#define BIT_SET_ACH5_TXBD_DESA_L(x, v)                                         \
+	(BIT_CLEAR_ACH5_TXBD_DESA_L(x) | BIT_ACH5_TXBD_DESA_L(v))
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+/* 2 REG_HI11Q_TXBD_IDX			(Offset 0x1364) */
+
+#define BIT_SHIFT_HI11Q_HW_IDX 16
+#define BIT_MASK_HI11Q_HW_IDX 0xfff
+#define BIT_HI11Q_HW_IDX(x)                                                    \
+	(((x) & BIT_MASK_HI11Q_HW_IDX) << BIT_SHIFT_HI11Q_HW_IDX)
+#define BITS_HI11Q_HW_IDX (BIT_MASK_HI11Q_HW_IDX << BIT_SHIFT_HI11Q_HW_IDX)
+#define BIT_CLEAR_HI11Q_HW_IDX(x) ((x) & (~BITS_HI11Q_HW_IDX))
+#define BIT_GET_HI11Q_HW_IDX(x)                                                \
+	(((x) >> BIT_SHIFT_HI11Q_HW_IDX) & BIT_MASK_HI11Q_HW_IDX)
+#define BIT_SET_HI11Q_HW_IDX(x, v)                                             \
+	(BIT_CLEAR_HI11Q_HW_IDX(x) | BIT_HI11Q_HW_IDX(v))
+
+#define BIT_SHIFT_HI11Q_HOST_IDX 0
+#define BIT_MASK_HI11Q_HOST_IDX 0xfff
+#define BIT_HI11Q_HOST_IDX(x)                                                  \
+	(((x) & BIT_MASK_HI11Q_HOST_IDX) << BIT_SHIFT_HI11Q_HOST_IDX)
+#define BITS_HI11Q_HOST_IDX                                                    \
+	(BIT_MASK_HI11Q_HOST_IDX << BIT_SHIFT_HI11Q_HOST_IDX)
+#define BIT_CLEAR_HI11Q_HOST_IDX(x) ((x) & (~BITS_HI11Q_HOST_IDX))
+#define BIT_GET_HI11Q_HOST_IDX(x)                                              \
+	(((x) >> BIT_SHIFT_HI11Q_HOST_IDX) & BIT_MASK_HI11Q_HOST_IDX)
+#define BIT_SET_HI11Q_HOST_IDX(x, v)                                           \
+	(BIT_CLEAR_HI11Q_HOST_IDX(x) | BIT_HI11Q_HOST_IDX(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_ACH5_TXBD_DESA_H			(Offset 0x1364) */
+
+#define BIT_SHIFT_ACH5_TXBD_DESA_H 0
+#define BIT_MASK_ACH5_TXBD_DESA_H 0xffffffffL
+#define BIT_ACH5_TXBD_DESA_H(x)                                                \
+	(((x) & BIT_MASK_ACH5_TXBD_DESA_H) << BIT_SHIFT_ACH5_TXBD_DESA_H)
+#define BITS_ACH5_TXBD_DESA_H                                                  \
+	(BIT_MASK_ACH5_TXBD_DESA_H << BIT_SHIFT_ACH5_TXBD_DESA_H)
+#define BIT_CLEAR_ACH5_TXBD_DESA_H(x) ((x) & (~BITS_ACH5_TXBD_DESA_H))
+#define BIT_GET_ACH5_TXBD_DESA_H(x)                                            \
+	(((x) >> BIT_SHIFT_ACH5_TXBD_DESA_H) & BIT_MASK_ACH5_TXBD_DESA_H)
+#define BIT_SET_ACH5_TXBD_DESA_H(x, v)                                         \
+	(BIT_CLEAR_ACH5_TXBD_DESA_H(x) | BIT_ACH5_TXBD_DESA_H(v))
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+/* 2 REG_HI12Q_TXBD_IDX			(Offset 0x1368) */
+
+#define BIT_SHIFT_HI12Q_HW_IDX 16
+#define BIT_MASK_HI12Q_HW_IDX 0xfff
+#define BIT_HI12Q_HW_IDX(x)                                                    \
+	(((x) & BIT_MASK_HI12Q_HW_IDX) << BIT_SHIFT_HI12Q_HW_IDX)
+#define BITS_HI12Q_HW_IDX (BIT_MASK_HI12Q_HW_IDX << BIT_SHIFT_HI12Q_HW_IDX)
+#define BIT_CLEAR_HI12Q_HW_IDX(x) ((x) & (~BITS_HI12Q_HW_IDX))
+#define BIT_GET_HI12Q_HW_IDX(x)                                                \
+	(((x) >> BIT_SHIFT_HI12Q_HW_IDX) & BIT_MASK_HI12Q_HW_IDX)
+#define BIT_SET_HI12Q_HW_IDX(x, v)                                             \
+	(BIT_CLEAR_HI12Q_HW_IDX(x) | BIT_HI12Q_HW_IDX(v))
+
+#define BIT_SHIFT_HI12Q_HOST_IDX 0
+#define BIT_MASK_HI12Q_HOST_IDX 0xfff
+#define BIT_HI12Q_HOST_IDX(x)                                                  \
+	(((x) & BIT_MASK_HI12Q_HOST_IDX) << BIT_SHIFT_HI12Q_HOST_IDX)
+#define BITS_HI12Q_HOST_IDX                                                    \
+	(BIT_MASK_HI12Q_HOST_IDX << BIT_SHIFT_HI12Q_HOST_IDX)
+#define BIT_CLEAR_HI12Q_HOST_IDX(x) ((x) & (~BITS_HI12Q_HOST_IDX))
+#define BIT_GET_HI12Q_HOST_IDX(x)                                              \
+	(((x) >> BIT_SHIFT_HI12Q_HOST_IDX) & BIT_MASK_HI12Q_HOST_IDX)
+#define BIT_SET_HI12Q_HOST_IDX(x, v)                                           \
+	(BIT_CLEAR_HI12Q_HOST_IDX(x) | BIT_HI12Q_HOST_IDX(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_ACH6_TXBD_DESA_L			(Offset 0x1368) */
+
+#define BIT_SHIFT_ACH6_TXBD_DESA_L 0
+#define BIT_MASK_ACH6_TXBD_DESA_L 0xffffffffL
+#define BIT_ACH6_TXBD_DESA_L(x)                                                \
+	(((x) & BIT_MASK_ACH6_TXBD_DESA_L) << BIT_SHIFT_ACH6_TXBD_DESA_L)
+#define BITS_ACH6_TXBD_DESA_L                                                  \
+	(BIT_MASK_ACH6_TXBD_DESA_L << BIT_SHIFT_ACH6_TXBD_DESA_L)
+#define BIT_CLEAR_ACH6_TXBD_DESA_L(x) ((x) & (~BITS_ACH6_TXBD_DESA_L))
+#define BIT_GET_ACH6_TXBD_DESA_L(x)                                            \
+	(((x) >> BIT_SHIFT_ACH6_TXBD_DESA_L) & BIT_MASK_ACH6_TXBD_DESA_L)
+#define BIT_SET_ACH6_TXBD_DESA_L(x, v)                                         \
+	(BIT_CLEAR_ACH6_TXBD_DESA_L(x) | BIT_ACH6_TXBD_DESA_L(v))
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+/* 2 REG_HI13Q_TXBD_IDX			(Offset 0x136C) */
+
+#define BIT_SHIFT_HI13Q_HW_IDX 16
+#define BIT_MASK_HI13Q_HW_IDX 0xfff
+#define BIT_HI13Q_HW_IDX(x)                                                    \
+	(((x) & BIT_MASK_HI13Q_HW_IDX) << BIT_SHIFT_HI13Q_HW_IDX)
+#define BITS_HI13Q_HW_IDX (BIT_MASK_HI13Q_HW_IDX << BIT_SHIFT_HI13Q_HW_IDX)
+#define BIT_CLEAR_HI13Q_HW_IDX(x) ((x) & (~BITS_HI13Q_HW_IDX))
+#define BIT_GET_HI13Q_HW_IDX(x)                                                \
+	(((x) >> BIT_SHIFT_HI13Q_HW_IDX) & BIT_MASK_HI13Q_HW_IDX)
+#define BIT_SET_HI13Q_HW_IDX(x, v)                                             \
+	(BIT_CLEAR_HI13Q_HW_IDX(x) | BIT_HI13Q_HW_IDX(v))
+
+#define BIT_SHIFT_HI13Q_HOST_IDX 0
+#define BIT_MASK_HI13Q_HOST_IDX 0xfff
+#define BIT_HI13Q_HOST_IDX(x)                                                  \
+	(((x) & BIT_MASK_HI13Q_HOST_IDX) << BIT_SHIFT_HI13Q_HOST_IDX)
+#define BITS_HI13Q_HOST_IDX                                                    \
+	(BIT_MASK_HI13Q_HOST_IDX << BIT_SHIFT_HI13Q_HOST_IDX)
+#define BIT_CLEAR_HI13Q_HOST_IDX(x) ((x) & (~BITS_HI13Q_HOST_IDX))
+#define BIT_GET_HI13Q_HOST_IDX(x)                                              \
+	(((x) >> BIT_SHIFT_HI13Q_HOST_IDX) & BIT_MASK_HI13Q_HOST_IDX)
+#define BIT_SET_HI13Q_HOST_IDX(x, v)                                           \
+	(BIT_CLEAR_HI13Q_HOST_IDX(x) | BIT_HI13Q_HOST_IDX(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_ACH6_TXBD_DESA_H			(Offset 0x136C) */
+
+#define BIT_SHIFT_ACH6_TXBD_DESA_H 0
+#define BIT_MASK_ACH6_TXBD_DESA_H 0xffffffffL
+#define BIT_ACH6_TXBD_DESA_H(x)                                                \
+	(((x) & BIT_MASK_ACH6_TXBD_DESA_H) << BIT_SHIFT_ACH6_TXBD_DESA_H)
+#define BITS_ACH6_TXBD_DESA_H                                                  \
+	(BIT_MASK_ACH6_TXBD_DESA_H << BIT_SHIFT_ACH6_TXBD_DESA_H)
+#define BIT_CLEAR_ACH6_TXBD_DESA_H(x) ((x) & (~BITS_ACH6_TXBD_DESA_H))
+#define BIT_GET_ACH6_TXBD_DESA_H(x)                                            \
+	(((x) >> BIT_SHIFT_ACH6_TXBD_DESA_H) & BIT_MASK_ACH6_TXBD_DESA_H)
+#define BIT_SET_ACH6_TXBD_DESA_H(x, v)                                         \
+	(BIT_CLEAR_ACH6_TXBD_DESA_H(x) | BIT_ACH6_TXBD_DESA_H(v))
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+/* 2 REG_HI14Q_TXBD_IDX			(Offset 0x1370) */
+
+#define BIT_SHIFT_HI14Q_HW_IDX 16
+#define BIT_MASK_HI14Q_HW_IDX 0xfff
+#define BIT_HI14Q_HW_IDX(x)                                                    \
+	(((x) & BIT_MASK_HI14Q_HW_IDX) << BIT_SHIFT_HI14Q_HW_IDX)
+#define BITS_HI14Q_HW_IDX (BIT_MASK_HI14Q_HW_IDX << BIT_SHIFT_HI14Q_HW_IDX)
+#define BIT_CLEAR_HI14Q_HW_IDX(x) ((x) & (~BITS_HI14Q_HW_IDX))
+#define BIT_GET_HI14Q_HW_IDX(x)                                                \
+	(((x) >> BIT_SHIFT_HI14Q_HW_IDX) & BIT_MASK_HI14Q_HW_IDX)
+#define BIT_SET_HI14Q_HW_IDX(x, v)                                             \
+	(BIT_CLEAR_HI14Q_HW_IDX(x) | BIT_HI14Q_HW_IDX(v))
+
+#define BIT_SHIFT_HI14Q_HOST_IDX 0
+#define BIT_MASK_HI14Q_HOST_IDX 0xfff
+#define BIT_HI14Q_HOST_IDX(x)                                                  \
+	(((x) & BIT_MASK_HI14Q_HOST_IDX) << BIT_SHIFT_HI14Q_HOST_IDX)
+#define BITS_HI14Q_HOST_IDX                                                    \
+	(BIT_MASK_HI14Q_HOST_IDX << BIT_SHIFT_HI14Q_HOST_IDX)
+#define BIT_CLEAR_HI14Q_HOST_IDX(x) ((x) & (~BITS_HI14Q_HOST_IDX))
+#define BIT_GET_HI14Q_HOST_IDX(x)                                              \
+	(((x) >> BIT_SHIFT_HI14Q_HOST_IDX) & BIT_MASK_HI14Q_HOST_IDX)
+#define BIT_SET_HI14Q_HOST_IDX(x, v)                                           \
+	(BIT_CLEAR_HI14Q_HOST_IDX(x) | BIT_HI14Q_HOST_IDX(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_ACH7_TXBD_DESA_L			(Offset 0x1370) */
+
+#define BIT_SHIFT_ACH7_TXBD_DESA_L 0
+#define BIT_MASK_ACH7_TXBD_DESA_L 0xffffffffL
+#define BIT_ACH7_TXBD_DESA_L(x)                                                \
+	(((x) & BIT_MASK_ACH7_TXBD_DESA_L) << BIT_SHIFT_ACH7_TXBD_DESA_L)
+#define BITS_ACH7_TXBD_DESA_L                                                  \
+	(BIT_MASK_ACH7_TXBD_DESA_L << BIT_SHIFT_ACH7_TXBD_DESA_L)
+#define BIT_CLEAR_ACH7_TXBD_DESA_L(x) ((x) & (~BITS_ACH7_TXBD_DESA_L))
+#define BIT_GET_ACH7_TXBD_DESA_L(x)                                            \
+	(((x) >> BIT_SHIFT_ACH7_TXBD_DESA_L) & BIT_MASK_ACH7_TXBD_DESA_L)
+#define BIT_SET_ACH7_TXBD_DESA_L(x, v)                                         \
+	(BIT_CLEAR_ACH7_TXBD_DESA_L(x) | BIT_ACH7_TXBD_DESA_L(v))
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+/* 2 REG_HI15Q_TXBD_IDX			(Offset 0x1374) */
+
+#define BIT_SHIFT_HI15Q_HW_IDX 16
+#define BIT_MASK_HI15Q_HW_IDX 0xfff
+#define BIT_HI15Q_HW_IDX(x)                                                    \
+	(((x) & BIT_MASK_HI15Q_HW_IDX) << BIT_SHIFT_HI15Q_HW_IDX)
+#define BITS_HI15Q_HW_IDX (BIT_MASK_HI15Q_HW_IDX << BIT_SHIFT_HI15Q_HW_IDX)
+#define BIT_CLEAR_HI15Q_HW_IDX(x) ((x) & (~BITS_HI15Q_HW_IDX))
+#define BIT_GET_HI15Q_HW_IDX(x)                                                \
+	(((x) >> BIT_SHIFT_HI15Q_HW_IDX) & BIT_MASK_HI15Q_HW_IDX)
+#define BIT_SET_HI15Q_HW_IDX(x, v)                                             \
+	(BIT_CLEAR_HI15Q_HW_IDX(x) | BIT_HI15Q_HW_IDX(v))
+
+#define BIT_SHIFT_HI15Q_HOST_IDX 0
+#define BIT_MASK_HI15Q_HOST_IDX 0xfff
+#define BIT_HI15Q_HOST_IDX(x)                                                  \
+	(((x) & BIT_MASK_HI15Q_HOST_IDX) << BIT_SHIFT_HI15Q_HOST_IDX)
+#define BITS_HI15Q_HOST_IDX                                                    \
+	(BIT_MASK_HI15Q_HOST_IDX << BIT_SHIFT_HI15Q_HOST_IDX)
+#define BIT_CLEAR_HI15Q_HOST_IDX(x) ((x) & (~BITS_HI15Q_HOST_IDX))
+#define BIT_GET_HI15Q_HOST_IDX(x)                                              \
+	(((x) >> BIT_SHIFT_HI15Q_HOST_IDX) & BIT_MASK_HI15Q_HOST_IDX)
+#define BIT_SET_HI15Q_HOST_IDX(x, v)                                           \
+	(BIT_CLEAR_HI15Q_HOST_IDX(x) | BIT_HI15Q_HOST_IDX(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_ACH7_TXBD_DESA_H			(Offset 0x1374) */
+
+#define BIT_SHIFT_ACH7_TXBD_DESA_H 0
+#define BIT_MASK_ACH7_TXBD_DESA_H 0xffffffffL
+#define BIT_ACH7_TXBD_DESA_H(x)                                                \
+	(((x) & BIT_MASK_ACH7_TXBD_DESA_H) << BIT_SHIFT_ACH7_TXBD_DESA_H)
+#define BITS_ACH7_TXBD_DESA_H                                                  \
+	(BIT_MASK_ACH7_TXBD_DESA_H << BIT_SHIFT_ACH7_TXBD_DESA_H)
+#define BIT_CLEAR_ACH7_TXBD_DESA_H(x) ((x) & (~BITS_ACH7_TXBD_DESA_H))
+#define BIT_GET_ACH7_TXBD_DESA_H(x)                                            \
+	(((x) >> BIT_SHIFT_ACH7_TXBD_DESA_H) & BIT_MASK_ACH7_TXBD_DESA_H)
+#define BIT_SET_ACH7_TXBD_DESA_H(x, v)                                         \
+	(BIT_CLEAR_ACH7_TXBD_DESA_H(x) | BIT_ACH7_TXBD_DESA_H(v))
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+/* 2 REG_HI8Q_TXBD_DESA			(Offset 0x1378) */
+
+#define BIT_SHIFT_HI8Q_TXBD_DESA 0
+#define BIT_MASK_HI8Q_TXBD_DESA 0xffffffffffffffffL
+#define BIT_HI8Q_TXBD_DESA(x)                                                  \
+	(((x) & BIT_MASK_HI8Q_TXBD_DESA) << BIT_SHIFT_HI8Q_TXBD_DESA)
+#define BITS_HI8Q_TXBD_DESA                                                    \
+	(BIT_MASK_HI8Q_TXBD_DESA << BIT_SHIFT_HI8Q_TXBD_DESA)
+#define BIT_CLEAR_HI8Q_TXBD_DESA(x) ((x) & (~BITS_HI8Q_TXBD_DESA))
+#define BIT_GET_HI8Q_TXBD_DESA(x)                                              \
+	(((x) >> BIT_SHIFT_HI8Q_TXBD_DESA) & BIT_MASK_HI8Q_TXBD_DESA)
+#define BIT_SET_HI8Q_TXBD_DESA(x, v)                                           \
+	(BIT_CLEAR_HI8Q_TXBD_DESA(x) | BIT_HI8Q_TXBD_DESA(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_ACH8_TXBD_DESA_L			(Offset 0x1378) */
+
+#define BIT_SHIFT_ACH8_TXBD_DESA_L 0
+#define BIT_MASK_ACH8_TXBD_DESA_L 0xffffffffL
+#define BIT_ACH8_TXBD_DESA_L(x)                                                \
+	(((x) & BIT_MASK_ACH8_TXBD_DESA_L) << BIT_SHIFT_ACH8_TXBD_DESA_L)
+#define BITS_ACH8_TXBD_DESA_L                                                  \
+	(BIT_MASK_ACH8_TXBD_DESA_L << BIT_SHIFT_ACH8_TXBD_DESA_L)
+#define BIT_CLEAR_ACH8_TXBD_DESA_L(x) ((x) & (~BITS_ACH8_TXBD_DESA_L))
+#define BIT_GET_ACH8_TXBD_DESA_L(x)                                            \
+	(((x) >> BIT_SHIFT_ACH8_TXBD_DESA_L) & BIT_MASK_ACH8_TXBD_DESA_L)
+#define BIT_SET_ACH8_TXBD_DESA_L(x, v)                                         \
+	(BIT_CLEAR_ACH8_TXBD_DESA_L(x) | BIT_ACH8_TXBD_DESA_L(v))
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_CHNL_DMA_CFG_V1			(Offset 0x137C) */
+
+#define BIT_TXHCI_EN_V1 BIT(26)
+#define BIT_TXHCI_IDLE_V1 BIT(25)
+#define BIT_DMA_PRI_EN_V1 BIT(24)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_ACH8_TXBD_DESA_H			(Offset 0x137C) */
+
+#define BIT_SHIFT_ACH8_TXBD_DESA_H 0
+#define BIT_MASK_ACH8_TXBD_DESA_H 0xffffffffL
+#define BIT_ACH8_TXBD_DESA_H(x)                                                \
+	(((x) & BIT_MASK_ACH8_TXBD_DESA_H) << BIT_SHIFT_ACH8_TXBD_DESA_H)
+#define BITS_ACH8_TXBD_DESA_H                                                  \
+	(BIT_MASK_ACH8_TXBD_DESA_H << BIT_SHIFT_ACH8_TXBD_DESA_H)
+#define BIT_CLEAR_ACH8_TXBD_DESA_H(x) ((x) & (~BITS_ACH8_TXBD_DESA_H))
+#define BIT_GET_ACH8_TXBD_DESA_H(x)                                            \
+	(((x) >> BIT_SHIFT_ACH8_TXBD_DESA_H) & BIT_MASK_ACH8_TXBD_DESA_H)
+#define BIT_SET_ACH8_TXBD_DESA_H(x, v)                                         \
+	(BIT_CLEAR_ACH8_TXBD_DESA_H(x) | BIT_ACH8_TXBD_DESA_H(v))
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+/* 2 REG_HI9Q_TXBD_DESA			(Offset 0x1380) */
+
+#define BIT_SHIFT_HI9Q_TXBD_DESA 0
+#define BIT_MASK_HI9Q_TXBD_DESA 0xffffffffffffffffL
+#define BIT_HI9Q_TXBD_DESA(x)                                                  \
+	(((x) & BIT_MASK_HI9Q_TXBD_DESA) << BIT_SHIFT_HI9Q_TXBD_DESA)
+#define BITS_HI9Q_TXBD_DESA                                                    \
+	(BIT_MASK_HI9Q_TXBD_DESA << BIT_SHIFT_HI9Q_TXBD_DESA)
+#define BIT_CLEAR_HI9Q_TXBD_DESA(x) ((x) & (~BITS_HI9Q_TXBD_DESA))
+#define BIT_GET_HI9Q_TXBD_DESA(x)                                              \
+	(((x) >> BIT_SHIFT_HI9Q_TXBD_DESA) & BIT_MASK_HI9Q_TXBD_DESA)
+#define BIT_SET_HI9Q_TXBD_DESA(x, v)                                           \
+	(BIT_CLEAR_HI9Q_TXBD_DESA(x) | BIT_HI9Q_TXBD_DESA(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_ACH9_TXBD_DESA_L			(Offset 0x1380) */
+
+#define BIT_SHIFT_ACH9_TXBD_DESA_L 0
+#define BIT_MASK_ACH9_TXBD_DESA_L 0xffffffffL
+#define BIT_ACH9_TXBD_DESA_L(x)                                                \
+	(((x) & BIT_MASK_ACH9_TXBD_DESA_L) << BIT_SHIFT_ACH9_TXBD_DESA_L)
+#define BITS_ACH9_TXBD_DESA_L                                                  \
+	(BIT_MASK_ACH9_TXBD_DESA_L << BIT_SHIFT_ACH9_TXBD_DESA_L)
+#define BIT_CLEAR_ACH9_TXBD_DESA_L(x) ((x) & (~BITS_ACH9_TXBD_DESA_L))
+#define BIT_GET_ACH9_TXBD_DESA_L(x)                                            \
+	(((x) >> BIT_SHIFT_ACH9_TXBD_DESA_L) & BIT_MASK_ACH9_TXBD_DESA_L)
+#define BIT_SET_ACH9_TXBD_DESA_L(x, v)                                         \
+	(BIT_CLEAR_ACH9_TXBD_DESA_L(x) | BIT_ACH9_TXBD_DESA_L(v))
+
+/* 2 REG_ACH9_TXBD_DESA_H			(Offset 0x1384) */
+
+#define BIT_SHIFT_ACH9_TXBD_DESA_H 0
+#define BIT_MASK_ACH9_TXBD_DESA_H 0xffffffffL
+#define BIT_ACH9_TXBD_DESA_H(x)                                                \
+	(((x) & BIT_MASK_ACH9_TXBD_DESA_H) << BIT_SHIFT_ACH9_TXBD_DESA_H)
+#define BITS_ACH9_TXBD_DESA_H                                                  \
+	(BIT_MASK_ACH9_TXBD_DESA_H << BIT_SHIFT_ACH9_TXBD_DESA_H)
+#define BIT_CLEAR_ACH9_TXBD_DESA_H(x) ((x) & (~BITS_ACH9_TXBD_DESA_H))
+#define BIT_GET_ACH9_TXBD_DESA_H(x)                                            \
+	(((x) >> BIT_SHIFT_ACH9_TXBD_DESA_H) & BIT_MASK_ACH9_TXBD_DESA_H)
+#define BIT_SET_ACH9_TXBD_DESA_H(x, v)                                         \
+	(BIT_CLEAR_ACH9_TXBD_DESA_H(x) | BIT_ACH9_TXBD_DESA_H(v))
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+/* 2 REG_HI10Q_TXBD_DESA			(Offset 0x1388) */
+
+#define BIT_SHIFT_HI10Q_TXBD_DESA 0
+#define BIT_MASK_HI10Q_TXBD_DESA 0xffffffffffffffffL
+#define BIT_HI10Q_TXBD_DESA(x)                                                 \
+	(((x) & BIT_MASK_HI10Q_TXBD_DESA) << BIT_SHIFT_HI10Q_TXBD_DESA)
+#define BITS_HI10Q_TXBD_DESA                                                   \
+	(BIT_MASK_HI10Q_TXBD_DESA << BIT_SHIFT_HI10Q_TXBD_DESA)
+#define BIT_CLEAR_HI10Q_TXBD_DESA(x) ((x) & (~BITS_HI10Q_TXBD_DESA))
+#define BIT_GET_HI10Q_TXBD_DESA(x)                                             \
+	(((x) >> BIT_SHIFT_HI10Q_TXBD_DESA) & BIT_MASK_HI10Q_TXBD_DESA)
+#define BIT_SET_HI10Q_TXBD_DESA(x, v)                                          \
+	(BIT_CLEAR_HI10Q_TXBD_DESA(x) | BIT_HI10Q_TXBD_DESA(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_ACH10_TXBD_DESA_L			(Offset 0x1388) */
+
+#define BIT_SHIFT_ACH10_TXBD_DESA_L 0
+#define BIT_MASK_ACH10_TXBD_DESA_L 0xffffffffL
+#define BIT_ACH10_TXBD_DESA_L(x)                                               \
+	(((x) & BIT_MASK_ACH10_TXBD_DESA_L) << BIT_SHIFT_ACH10_TXBD_DESA_L)
+#define BITS_ACH10_TXBD_DESA_L                                                 \
+	(BIT_MASK_ACH10_TXBD_DESA_L << BIT_SHIFT_ACH10_TXBD_DESA_L)
+#define BIT_CLEAR_ACH10_TXBD_DESA_L(x) ((x) & (~BITS_ACH10_TXBD_DESA_L))
+#define BIT_GET_ACH10_TXBD_DESA_L(x)                                           \
+	(((x) >> BIT_SHIFT_ACH10_TXBD_DESA_L) & BIT_MASK_ACH10_TXBD_DESA_L)
+#define BIT_SET_ACH10_TXBD_DESA_L(x, v)                                        \
+	(BIT_CLEAR_ACH10_TXBD_DESA_L(x) | BIT_ACH10_TXBD_DESA_L(v))
+
+/* 2 REG_ACH10_TXBD_DESA_H			(Offset 0x138C) */
+
+#define BIT_SHIFT_ACH10_TXBD_DESA_H 0
+#define BIT_MASK_ACH10_TXBD_DESA_H 0xffffffffL
+#define BIT_ACH10_TXBD_DESA_H(x)                                               \
+	(((x) & BIT_MASK_ACH10_TXBD_DESA_H) << BIT_SHIFT_ACH10_TXBD_DESA_H)
+#define BITS_ACH10_TXBD_DESA_H                                                 \
+	(BIT_MASK_ACH10_TXBD_DESA_H << BIT_SHIFT_ACH10_TXBD_DESA_H)
+#define BIT_CLEAR_ACH10_TXBD_DESA_H(x) ((x) & (~BITS_ACH10_TXBD_DESA_H))
+#define BIT_GET_ACH10_TXBD_DESA_H(x)                                           \
+	(((x) >> BIT_SHIFT_ACH10_TXBD_DESA_H) & BIT_MASK_ACH10_TXBD_DESA_H)
+#define BIT_SET_ACH10_TXBD_DESA_H(x, v)                                        \
+	(BIT_CLEAR_ACH10_TXBD_DESA_H(x) | BIT_ACH10_TXBD_DESA_H(v))
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+/* 2 REG_HI11Q_TXBD_DESA			(Offset 0x1390) */
+
+#define BIT_SHIFT_HI11Q_TXBD_DESA 0
+#define BIT_MASK_HI11Q_TXBD_DESA 0xffffffffffffffffL
+#define BIT_HI11Q_TXBD_DESA(x)                                                 \
+	(((x) & BIT_MASK_HI11Q_TXBD_DESA) << BIT_SHIFT_HI11Q_TXBD_DESA)
+#define BITS_HI11Q_TXBD_DESA                                                   \
+	(BIT_MASK_HI11Q_TXBD_DESA << BIT_SHIFT_HI11Q_TXBD_DESA)
+#define BIT_CLEAR_HI11Q_TXBD_DESA(x) ((x) & (~BITS_HI11Q_TXBD_DESA))
+#define BIT_GET_HI11Q_TXBD_DESA(x)                                             \
+	(((x) >> BIT_SHIFT_HI11Q_TXBD_DESA) & BIT_MASK_HI11Q_TXBD_DESA)
+#define BIT_SET_HI11Q_TXBD_DESA(x, v)                                          \
+	(BIT_CLEAR_HI11Q_TXBD_DESA(x) | BIT_HI11Q_TXBD_DESA(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_ACH11_TXBD_DESA_L			(Offset 0x1390) */
+
+#define BIT_SHIFT_ACH11_TXBD_DESA_L 0
+#define BIT_MASK_ACH11_TXBD_DESA_L 0xffffffffL
+#define BIT_ACH11_TXBD_DESA_L(x)                                               \
+	(((x) & BIT_MASK_ACH11_TXBD_DESA_L) << BIT_SHIFT_ACH11_TXBD_DESA_L)
+#define BITS_ACH11_TXBD_DESA_L                                                 \
+	(BIT_MASK_ACH11_TXBD_DESA_L << BIT_SHIFT_ACH11_TXBD_DESA_L)
+#define BIT_CLEAR_ACH11_TXBD_DESA_L(x) ((x) & (~BITS_ACH11_TXBD_DESA_L))
+#define BIT_GET_ACH11_TXBD_DESA_L(x)                                           \
+	(((x) >> BIT_SHIFT_ACH11_TXBD_DESA_L) & BIT_MASK_ACH11_TXBD_DESA_L)
+#define BIT_SET_ACH11_TXBD_DESA_L(x, v)                                        \
+	(BIT_CLEAR_ACH11_TXBD_DESA_L(x) | BIT_ACH11_TXBD_DESA_L(v))
+
+/* 2 REG_ACH11_TXBD_DESA_H			(Offset 0x1394) */
+
+#define BIT_SHIFT_ACH11_TXBD_DESA_H 0
+#define BIT_MASK_ACH11_TXBD_DESA_H 0xffffffffL
+#define BIT_ACH11_TXBD_DESA_H(x)                                               \
+	(((x) & BIT_MASK_ACH11_TXBD_DESA_H) << BIT_SHIFT_ACH11_TXBD_DESA_H)
+#define BITS_ACH11_TXBD_DESA_H                                                 \
+	(BIT_MASK_ACH11_TXBD_DESA_H << BIT_SHIFT_ACH11_TXBD_DESA_H)
+#define BIT_CLEAR_ACH11_TXBD_DESA_H(x) ((x) & (~BITS_ACH11_TXBD_DESA_H))
+#define BIT_GET_ACH11_TXBD_DESA_H(x)                                           \
+	(((x) >> BIT_SHIFT_ACH11_TXBD_DESA_H) & BIT_MASK_ACH11_TXBD_DESA_H)
+#define BIT_SET_ACH11_TXBD_DESA_H(x, v)                                        \
+	(BIT_CLEAR_ACH11_TXBD_DESA_H(x) | BIT_ACH11_TXBD_DESA_H(v))
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+/* 2 REG_HI12Q_TXBD_DESA			(Offset 0x1398) */
+
+#define BIT_SHIFT_HI12Q_TXBD_DESA 0
+#define BIT_MASK_HI12Q_TXBD_DESA 0xffffffffffffffffL
+#define BIT_HI12Q_TXBD_DESA(x)                                                 \
+	(((x) & BIT_MASK_HI12Q_TXBD_DESA) << BIT_SHIFT_HI12Q_TXBD_DESA)
+#define BITS_HI12Q_TXBD_DESA                                                   \
+	(BIT_MASK_HI12Q_TXBD_DESA << BIT_SHIFT_HI12Q_TXBD_DESA)
+#define BIT_CLEAR_HI12Q_TXBD_DESA(x) ((x) & (~BITS_HI12Q_TXBD_DESA))
+#define BIT_GET_HI12Q_TXBD_DESA(x)                                             \
+	(((x) >> BIT_SHIFT_HI12Q_TXBD_DESA) & BIT_MASK_HI12Q_TXBD_DESA)
+#define BIT_SET_HI12Q_TXBD_DESA(x, v)                                          \
+	(BIT_CLEAR_HI12Q_TXBD_DESA(x) | BIT_HI12Q_TXBD_DESA(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_ACH12_TXBD_DESA_L			(Offset 0x1398) */
+
+#define BIT_SHIFT_ACH12_TXBD_DESA_L 0
+#define BIT_MASK_ACH12_TXBD_DESA_L 0xffffffffL
+#define BIT_ACH12_TXBD_DESA_L(x)                                               \
+	(((x) & BIT_MASK_ACH12_TXBD_DESA_L) << BIT_SHIFT_ACH12_TXBD_DESA_L)
+#define BITS_ACH12_TXBD_DESA_L                                                 \
+	(BIT_MASK_ACH12_TXBD_DESA_L << BIT_SHIFT_ACH12_TXBD_DESA_L)
+#define BIT_CLEAR_ACH12_TXBD_DESA_L(x) ((x) & (~BITS_ACH12_TXBD_DESA_L))
+#define BIT_GET_ACH12_TXBD_DESA_L(x)                                           \
+	(((x) >> BIT_SHIFT_ACH12_TXBD_DESA_L) & BIT_MASK_ACH12_TXBD_DESA_L)
+#define BIT_SET_ACH12_TXBD_DESA_L(x, v)                                        \
+	(BIT_CLEAR_ACH12_TXBD_DESA_L(x) | BIT_ACH12_TXBD_DESA_L(v))
+
+/* 2 REG_ACH12_TXBD_DESA_H			(Offset 0x139C) */
+
+#define BIT_SHIFT_ACH12_TXBD_DESA_H 0
+#define BIT_MASK_ACH12_TXBD_DESA_H 0xffffffffL
+#define BIT_ACH12_TXBD_DESA_H(x)                                               \
+	(((x) & BIT_MASK_ACH12_TXBD_DESA_H) << BIT_SHIFT_ACH12_TXBD_DESA_H)
+#define BITS_ACH12_TXBD_DESA_H                                                 \
+	(BIT_MASK_ACH12_TXBD_DESA_H << BIT_SHIFT_ACH12_TXBD_DESA_H)
+#define BIT_CLEAR_ACH12_TXBD_DESA_H(x) ((x) & (~BITS_ACH12_TXBD_DESA_H))
+#define BIT_GET_ACH12_TXBD_DESA_H(x)                                           \
+	(((x) >> BIT_SHIFT_ACH12_TXBD_DESA_H) & BIT_MASK_ACH12_TXBD_DESA_H)
+#define BIT_SET_ACH12_TXBD_DESA_H(x, v)                                        \
+	(BIT_CLEAR_ACH12_TXBD_DESA_H(x) | BIT_ACH12_TXBD_DESA_H(v))
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+/* 2 REG_HI13Q_TXBD_DESA			(Offset 0x13A0) */
+
+#define BIT_SHIFT_HI13Q_TXBD_DESA 0
+#define BIT_MASK_HI13Q_TXBD_DESA 0xffffffffffffffffL
+#define BIT_HI13Q_TXBD_DESA(x)                                                 \
+	(((x) & BIT_MASK_HI13Q_TXBD_DESA) << BIT_SHIFT_HI13Q_TXBD_DESA)
+#define BITS_HI13Q_TXBD_DESA                                                   \
+	(BIT_MASK_HI13Q_TXBD_DESA << BIT_SHIFT_HI13Q_TXBD_DESA)
+#define BIT_CLEAR_HI13Q_TXBD_DESA(x) ((x) & (~BITS_HI13Q_TXBD_DESA))
+#define BIT_GET_HI13Q_TXBD_DESA(x)                                             \
+	(((x) >> BIT_SHIFT_HI13Q_TXBD_DESA) & BIT_MASK_HI13Q_TXBD_DESA)
+#define BIT_SET_HI13Q_TXBD_DESA(x, v)                                          \
+	(BIT_CLEAR_HI13Q_TXBD_DESA(x) | BIT_HI13Q_TXBD_DESA(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_ACH13_TXBD_DESA_L			(Offset 0x13A0) */
+
+#define BIT_SHIFT_ACH13_TXBD_DESA_L 0
+#define BIT_MASK_ACH13_TXBD_DESA_L 0xffffffffL
+#define BIT_ACH13_TXBD_DESA_L(x)                                               \
+	(((x) & BIT_MASK_ACH13_TXBD_DESA_L) << BIT_SHIFT_ACH13_TXBD_DESA_L)
+#define BITS_ACH13_TXBD_DESA_L                                                 \
+	(BIT_MASK_ACH13_TXBD_DESA_L << BIT_SHIFT_ACH13_TXBD_DESA_L)
+#define BIT_CLEAR_ACH13_TXBD_DESA_L(x) ((x) & (~BITS_ACH13_TXBD_DESA_L))
+#define BIT_GET_ACH13_TXBD_DESA_L(x)                                           \
+	(((x) >> BIT_SHIFT_ACH13_TXBD_DESA_L) & BIT_MASK_ACH13_TXBD_DESA_L)
+#define BIT_SET_ACH13_TXBD_DESA_L(x, v)                                        \
+	(BIT_CLEAR_ACH13_TXBD_DESA_L(x) | BIT_ACH13_TXBD_DESA_L(v))
+
+/* 2 REG_ACH13_TXBD_DESA_H			(Offset 0x13A4) */
+
+#define BIT_SHIFT_ACH13_TXBD_DESA_H 0
+#define BIT_MASK_ACH13_TXBD_DESA_H 0xffffffffL
+#define BIT_ACH13_TXBD_DESA_H(x)                                               \
+	(((x) & BIT_MASK_ACH13_TXBD_DESA_H) << BIT_SHIFT_ACH13_TXBD_DESA_H)
+#define BITS_ACH13_TXBD_DESA_H                                                 \
+	(BIT_MASK_ACH13_TXBD_DESA_H << BIT_SHIFT_ACH13_TXBD_DESA_H)
+#define BIT_CLEAR_ACH13_TXBD_DESA_H(x) ((x) & (~BITS_ACH13_TXBD_DESA_H))
+#define BIT_GET_ACH13_TXBD_DESA_H(x)                                           \
+	(((x) >> BIT_SHIFT_ACH13_TXBD_DESA_H) & BIT_MASK_ACH13_TXBD_DESA_H)
+#define BIT_SET_ACH13_TXBD_DESA_H(x, v)                                        \
+	(BIT_CLEAR_ACH13_TXBD_DESA_H(x) | BIT_ACH13_TXBD_DESA_H(v))
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+/* 2 REG_HI14Q_TXBD_DESA			(Offset 0x13A8) */
+
+#define BIT_SHIFT_HI14Q_TXBD_DESA 0
+#define BIT_MASK_HI14Q_TXBD_DESA 0xffffffffffffffffL
+#define BIT_HI14Q_TXBD_DESA(x)                                                 \
+	(((x) & BIT_MASK_HI14Q_TXBD_DESA) << BIT_SHIFT_HI14Q_TXBD_DESA)
+#define BITS_HI14Q_TXBD_DESA                                                   \
+	(BIT_MASK_HI14Q_TXBD_DESA << BIT_SHIFT_HI14Q_TXBD_DESA)
+#define BIT_CLEAR_HI14Q_TXBD_DESA(x) ((x) & (~BITS_HI14Q_TXBD_DESA))
+#define BIT_GET_HI14Q_TXBD_DESA(x)                                             \
+	(((x) >> BIT_SHIFT_HI14Q_TXBD_DESA) & BIT_MASK_HI14Q_TXBD_DESA)
+#define BIT_SET_HI14Q_TXBD_DESA(x, v)                                          \
+	(BIT_CLEAR_HI14Q_TXBD_DESA(x) | BIT_HI14Q_TXBD_DESA(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_HI0Q_TXBD_DESA_L			(Offset 0x13A8) */
+
+#define BIT_SHIFT_HI0Q_TXBD_DESA_L 0
+#define BIT_MASK_HI0Q_TXBD_DESA_L 0xffffffffL
+#define BIT_HI0Q_TXBD_DESA_L(x)                                                \
+	(((x) & BIT_MASK_HI0Q_TXBD_DESA_L) << BIT_SHIFT_HI0Q_TXBD_DESA_L)
+#define BITS_HI0Q_TXBD_DESA_L                                                  \
+	(BIT_MASK_HI0Q_TXBD_DESA_L << BIT_SHIFT_HI0Q_TXBD_DESA_L)
+#define BIT_CLEAR_HI0Q_TXBD_DESA_L(x) ((x) & (~BITS_HI0Q_TXBD_DESA_L))
+#define BIT_GET_HI0Q_TXBD_DESA_L(x)                                            \
+	(((x) >> BIT_SHIFT_HI0Q_TXBD_DESA_L) & BIT_MASK_HI0Q_TXBD_DESA_L)
+#define BIT_SET_HI0Q_TXBD_DESA_L(x, v)                                         \
+	(BIT_CLEAR_HI0Q_TXBD_DESA_L(x) | BIT_HI0Q_TXBD_DESA_L(v))
+
+/* 2 REG_HI0Q_TXBD_DESA_H			(Offset 0x13AC) */
+
+#define BIT_SHIFT_HI0Q_TXBD_DESA_H 0
+#define BIT_MASK_HI0Q_TXBD_DESA_H 0xffffffffL
+#define BIT_HI0Q_TXBD_DESA_H(x)                                                \
+	(((x) & BIT_MASK_HI0Q_TXBD_DESA_H) << BIT_SHIFT_HI0Q_TXBD_DESA_H)
+#define BITS_HI0Q_TXBD_DESA_H                                                  \
+	(BIT_MASK_HI0Q_TXBD_DESA_H << BIT_SHIFT_HI0Q_TXBD_DESA_H)
+#define BIT_CLEAR_HI0Q_TXBD_DESA_H(x) ((x) & (~BITS_HI0Q_TXBD_DESA_H))
+#define BIT_GET_HI0Q_TXBD_DESA_H(x)                                            \
+	(((x) >> BIT_SHIFT_HI0Q_TXBD_DESA_H) & BIT_MASK_HI0Q_TXBD_DESA_H)
+#define BIT_SET_HI0Q_TXBD_DESA_H(x, v)                                         \
+	(BIT_CLEAR_HI0Q_TXBD_DESA_H(x) | BIT_HI0Q_TXBD_DESA_H(v))
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+/* 2 REG_HI15Q_TXBD_DESA			(Offset 0x13B0) */
+
+#define BIT_SHIFT_HI15Q_TXBD_DESA 0
+#define BIT_MASK_HI15Q_TXBD_DESA 0xffffffffffffffffL
+#define BIT_HI15Q_TXBD_DESA(x)                                                 \
+	(((x) & BIT_MASK_HI15Q_TXBD_DESA) << BIT_SHIFT_HI15Q_TXBD_DESA)
+#define BITS_HI15Q_TXBD_DESA                                                   \
+	(BIT_MASK_HI15Q_TXBD_DESA << BIT_SHIFT_HI15Q_TXBD_DESA)
+#define BIT_CLEAR_HI15Q_TXBD_DESA(x) ((x) & (~BITS_HI15Q_TXBD_DESA))
+#define BIT_GET_HI15Q_TXBD_DESA(x)                                             \
+	(((x) >> BIT_SHIFT_HI15Q_TXBD_DESA) & BIT_MASK_HI15Q_TXBD_DESA)
+#define BIT_SET_HI15Q_TXBD_DESA(x, v)                                          \
+	(BIT_CLEAR_HI15Q_TXBD_DESA(x) | BIT_HI15Q_TXBD_DESA(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_HI1Q_TXBD_DESA_L			(Offset 0x13B0) */
+
+#define BIT_SHIFT_HI1Q_TXBD_DESA_L 0
+#define BIT_MASK_HI1Q_TXBD_DESA_L 0xffffffffL
+#define BIT_HI1Q_TXBD_DESA_L(x)                                                \
+	(((x) & BIT_MASK_HI1Q_TXBD_DESA_L) << BIT_SHIFT_HI1Q_TXBD_DESA_L)
+#define BITS_HI1Q_TXBD_DESA_L                                                  \
+	(BIT_MASK_HI1Q_TXBD_DESA_L << BIT_SHIFT_HI1Q_TXBD_DESA_L)
+#define BIT_CLEAR_HI1Q_TXBD_DESA_L(x) ((x) & (~BITS_HI1Q_TXBD_DESA_L))
+#define BIT_GET_HI1Q_TXBD_DESA_L(x)                                            \
+	(((x) >> BIT_SHIFT_HI1Q_TXBD_DESA_L) & BIT_MASK_HI1Q_TXBD_DESA_L)
+#define BIT_SET_HI1Q_TXBD_DESA_L(x, v)                                         \
+	(BIT_CLEAR_HI1Q_TXBD_DESA_L(x) | BIT_HI1Q_TXBD_DESA_L(v))
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_PCIE_HISR0_V1			(Offset 0x13B4) */
+
+#define BIT_PRE_TX_ERR_INT BIT(31)
+#define BIT_HISR1_IND BIT(11)
+#define BIT_TXDMAOK_CHANNEL15 BIT(7)
+#define BIT_TXDMAOK_CHANNEL14 BIT(6)
+#define BIT_TXDMAOK_CHANNEL3 BIT(5)
+#define BIT_TXDMAOK_CHANNEL2 BIT(4)
+#define BIT_TXDMAOK_CHANNEL1 BIT(3)
+#define BIT_TXDMAOK_CHANNEL0 BIT(2)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_HI1Q_TXBD_DESA_H			(Offset 0x13B4) */
+
+#define BIT_SHIFT_HI1Q_TXBD_DESA_H 0
+#define BIT_MASK_HI1Q_TXBD_DESA_H 0xffffffffL
+#define BIT_HI1Q_TXBD_DESA_H(x)                                                \
+	(((x) & BIT_MASK_HI1Q_TXBD_DESA_H) << BIT_SHIFT_HI1Q_TXBD_DESA_H)
+#define BITS_HI1Q_TXBD_DESA_H                                                  \
+	(BIT_MASK_HI1Q_TXBD_DESA_H << BIT_SHIFT_HI1Q_TXBD_DESA_H)
+#define BIT_CLEAR_HI1Q_TXBD_DESA_H(x) ((x) & (~BITS_HI1Q_TXBD_DESA_H))
+#define BIT_GET_HI1Q_TXBD_DESA_H(x)                                            \
+	(((x) >> BIT_SHIFT_HI1Q_TXBD_DESA_H) & BIT_MASK_HI1Q_TXBD_DESA_H)
+#define BIT_SET_HI1Q_TXBD_DESA_H(x, v)                                         \
+	(BIT_CLEAR_HI1Q_TXBD_DESA_H(x) | BIT_HI1Q_TXBD_DESA_H(v))
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+/* 2 REG_HI8Q_TXBD_NUM			(Offset 0x13B8) */
+
+#define BIT_HI8Q_FLAG BIT(14)
+
+#define BIT_SHIFT_HI8Q_DESC_MODE 12
+#define BIT_MASK_HI8Q_DESC_MODE 0x3
+#define BIT_HI8Q_DESC_MODE(x)                                                  \
+	(((x) & BIT_MASK_HI8Q_DESC_MODE) << BIT_SHIFT_HI8Q_DESC_MODE)
+#define BITS_HI8Q_DESC_MODE                                                    \
+	(BIT_MASK_HI8Q_DESC_MODE << BIT_SHIFT_HI8Q_DESC_MODE)
+#define BIT_CLEAR_HI8Q_DESC_MODE(x) ((x) & (~BITS_HI8Q_DESC_MODE))
+#define BIT_GET_HI8Q_DESC_MODE(x)                                              \
+	(((x) >> BIT_SHIFT_HI8Q_DESC_MODE) & BIT_MASK_HI8Q_DESC_MODE)
+#define BIT_SET_HI8Q_DESC_MODE(x, v)                                           \
+	(BIT_CLEAR_HI8Q_DESC_MODE(x) | BIT_HI8Q_DESC_MODE(v))
+
+#define BIT_SHIFT_HI8Q_DESC_NUM 0
+#define BIT_MASK_HI8Q_DESC_NUM 0xfff
+#define BIT_HI8Q_DESC_NUM(x)                                                   \
+	(((x) & BIT_MASK_HI8Q_DESC_NUM) << BIT_SHIFT_HI8Q_DESC_NUM)
+#define BITS_HI8Q_DESC_NUM (BIT_MASK_HI8Q_DESC_NUM << BIT_SHIFT_HI8Q_DESC_NUM)
+#define BIT_CLEAR_HI8Q_DESC_NUM(x) ((x) & (~BITS_HI8Q_DESC_NUM))
+#define BIT_GET_HI8Q_DESC_NUM(x)                                               \
+	(((x) >> BIT_SHIFT_HI8Q_DESC_NUM) & BIT_MASK_HI8Q_DESC_NUM)
+#define BIT_SET_HI8Q_DESC_NUM(x, v)                                            \
+	(BIT_CLEAR_HI8Q_DESC_NUM(x) | BIT_HI8Q_DESC_NUM(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_HI2Q_TXBD_DESA_L			(Offset 0x13B8) */
+
+#define BIT_SHIFT_HI2Q_TXBD_DESA_L 0
+#define BIT_MASK_HI2Q_TXBD_DESA_L 0xffffffffL
+#define BIT_HI2Q_TXBD_DESA_L(x)                                                \
+	(((x) & BIT_MASK_HI2Q_TXBD_DESA_L) << BIT_SHIFT_HI2Q_TXBD_DESA_L)
+#define BITS_HI2Q_TXBD_DESA_L                                                  \
+	(BIT_MASK_HI2Q_TXBD_DESA_L << BIT_SHIFT_HI2Q_TXBD_DESA_L)
+#define BIT_CLEAR_HI2Q_TXBD_DESA_L(x) ((x) & (~BITS_HI2Q_TXBD_DESA_L))
+#define BIT_GET_HI2Q_TXBD_DESA_L(x)                                            \
+	(((x) >> BIT_SHIFT_HI2Q_TXBD_DESA_L) & BIT_MASK_HI2Q_TXBD_DESA_L)
+#define BIT_SET_HI2Q_TXBD_DESA_L(x, v)                                         \
+	(BIT_CLEAR_HI2Q_TXBD_DESA_L(x) | BIT_HI2Q_TXBD_DESA_L(v))
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+/* 2 REG_HI9Q_TXBD_NUM			(Offset 0x13BA) */
+
+#define BIT_HI9Q_FLAG BIT(14)
+
+#define BIT_SHIFT_HI9Q_DESC_MODE 12
+#define BIT_MASK_HI9Q_DESC_MODE 0x3
+#define BIT_HI9Q_DESC_MODE(x)                                                  \
+	(((x) & BIT_MASK_HI9Q_DESC_MODE) << BIT_SHIFT_HI9Q_DESC_MODE)
+#define BITS_HI9Q_DESC_MODE                                                    \
+	(BIT_MASK_HI9Q_DESC_MODE << BIT_SHIFT_HI9Q_DESC_MODE)
+#define BIT_CLEAR_HI9Q_DESC_MODE(x) ((x) & (~BITS_HI9Q_DESC_MODE))
+#define BIT_GET_HI9Q_DESC_MODE(x)                                              \
+	(((x) >> BIT_SHIFT_HI9Q_DESC_MODE) & BIT_MASK_HI9Q_DESC_MODE)
+#define BIT_SET_HI9Q_DESC_MODE(x, v)                                           \
+	(BIT_CLEAR_HI9Q_DESC_MODE(x) | BIT_HI9Q_DESC_MODE(v))
+
+#define BIT_SHIFT_HI9Q_DESC_NUM 0
+#define BIT_MASK_HI9Q_DESC_NUM 0xfff
+#define BIT_HI9Q_DESC_NUM(x)                                                   \
+	(((x) & BIT_MASK_HI9Q_DESC_NUM) << BIT_SHIFT_HI9Q_DESC_NUM)
+#define BITS_HI9Q_DESC_NUM (BIT_MASK_HI9Q_DESC_NUM << BIT_SHIFT_HI9Q_DESC_NUM)
+#define BIT_CLEAR_HI9Q_DESC_NUM(x) ((x) & (~BITS_HI9Q_DESC_NUM))
+#define BIT_GET_HI9Q_DESC_NUM(x)                                               \
+	(((x) >> BIT_SHIFT_HI9Q_DESC_NUM) & BIT_MASK_HI9Q_DESC_NUM)
+#define BIT_SET_HI9Q_DESC_NUM(x, v)                                            \
+	(BIT_CLEAR_HI9Q_DESC_NUM(x) | BIT_HI9Q_DESC_NUM(v))
+
+/* 2 REG_HI10Q_TXBD_NUM			(Offset 0x13BC) */
+
+#define BIT_HI10Q_FLAG BIT(14)
+
+#define BIT_SHIFT_HI10Q_DESC_MODE 12
+#define BIT_MASK_HI10Q_DESC_MODE 0x3
+#define BIT_HI10Q_DESC_MODE(x)                                                 \
+	(((x) & BIT_MASK_HI10Q_DESC_MODE) << BIT_SHIFT_HI10Q_DESC_MODE)
+#define BITS_HI10Q_DESC_MODE                                                   \
+	(BIT_MASK_HI10Q_DESC_MODE << BIT_SHIFT_HI10Q_DESC_MODE)
+#define BIT_CLEAR_HI10Q_DESC_MODE(x) ((x) & (~BITS_HI10Q_DESC_MODE))
+#define BIT_GET_HI10Q_DESC_MODE(x)                                             \
+	(((x) >> BIT_SHIFT_HI10Q_DESC_MODE) & BIT_MASK_HI10Q_DESC_MODE)
+#define BIT_SET_HI10Q_DESC_MODE(x, v)                                          \
+	(BIT_CLEAR_HI10Q_DESC_MODE(x) | BIT_HI10Q_DESC_MODE(v))
+
+#define BIT_SHIFT_HI10Q_DESC_NUM 0
+#define BIT_MASK_HI10Q_DESC_NUM 0xfff
+#define BIT_HI10Q_DESC_NUM(x)                                                  \
+	(((x) & BIT_MASK_HI10Q_DESC_NUM) << BIT_SHIFT_HI10Q_DESC_NUM)
+#define BITS_HI10Q_DESC_NUM                                                    \
+	(BIT_MASK_HI10Q_DESC_NUM << BIT_SHIFT_HI10Q_DESC_NUM)
+#define BIT_CLEAR_HI10Q_DESC_NUM(x) ((x) & (~BITS_HI10Q_DESC_NUM))
+#define BIT_GET_HI10Q_DESC_NUM(x)                                              \
+	(((x) >> BIT_SHIFT_HI10Q_DESC_NUM) & BIT_MASK_HI10Q_DESC_NUM)
+#define BIT_SET_HI10Q_DESC_NUM(x, v)                                           \
+	(BIT_CLEAR_HI10Q_DESC_NUM(x) | BIT_HI10Q_DESC_NUM(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_HI2Q_TXBD_DESA_H			(Offset 0x13BC) */
+
+#define BIT_SHIFT_HI2Q_TXBD_DESA_H 0
+#define BIT_MASK_HI2Q_TXBD_DESA_H 0xffffffffL
+#define BIT_HI2Q_TXBD_DESA_H(x)                                                \
+	(((x) & BIT_MASK_HI2Q_TXBD_DESA_H) << BIT_SHIFT_HI2Q_TXBD_DESA_H)
+#define BITS_HI2Q_TXBD_DESA_H                                                  \
+	(BIT_MASK_HI2Q_TXBD_DESA_H << BIT_SHIFT_HI2Q_TXBD_DESA_H)
+#define BIT_CLEAR_HI2Q_TXBD_DESA_H(x) ((x) & (~BITS_HI2Q_TXBD_DESA_H))
+#define BIT_GET_HI2Q_TXBD_DESA_H(x)                                            \
+	(((x) >> BIT_SHIFT_HI2Q_TXBD_DESA_H) & BIT_MASK_HI2Q_TXBD_DESA_H)
+#define BIT_SET_HI2Q_TXBD_DESA_H(x, v)                                         \
+	(BIT_CLEAR_HI2Q_TXBD_DESA_H(x) | BIT_HI2Q_TXBD_DESA_H(v))
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+/* 2 REG_HI11Q_TXBD_NUM			(Offset 0x13BE) */
+
+#define BIT_HI11Q_FLAG BIT(14)
+
+#define BIT_SHIFT_HI11Q_DESC_MODE 12
+#define BIT_MASK_HI11Q_DESC_MODE 0x3
+#define BIT_HI11Q_DESC_MODE(x)                                                 \
+	(((x) & BIT_MASK_HI11Q_DESC_MODE) << BIT_SHIFT_HI11Q_DESC_MODE)
+#define BITS_HI11Q_DESC_MODE                                                   \
+	(BIT_MASK_HI11Q_DESC_MODE << BIT_SHIFT_HI11Q_DESC_MODE)
+#define BIT_CLEAR_HI11Q_DESC_MODE(x) ((x) & (~BITS_HI11Q_DESC_MODE))
+#define BIT_GET_HI11Q_DESC_MODE(x)                                             \
+	(((x) >> BIT_SHIFT_HI11Q_DESC_MODE) & BIT_MASK_HI11Q_DESC_MODE)
+#define BIT_SET_HI11Q_DESC_MODE(x, v)                                          \
+	(BIT_CLEAR_HI11Q_DESC_MODE(x) | BIT_HI11Q_DESC_MODE(v))
+
+#define BIT_SHIFT_HI11Q_DESC_NUM 0
+#define BIT_MASK_HI11Q_DESC_NUM 0xfff
+#define BIT_HI11Q_DESC_NUM(x)                                                  \
+	(((x) & BIT_MASK_HI11Q_DESC_NUM) << BIT_SHIFT_HI11Q_DESC_NUM)
+#define BITS_HI11Q_DESC_NUM                                                    \
+	(BIT_MASK_HI11Q_DESC_NUM << BIT_SHIFT_HI11Q_DESC_NUM)
+#define BIT_CLEAR_HI11Q_DESC_NUM(x) ((x) & (~BITS_HI11Q_DESC_NUM))
+#define BIT_GET_HI11Q_DESC_NUM(x)                                              \
+	(((x) >> BIT_SHIFT_HI11Q_DESC_NUM) & BIT_MASK_HI11Q_DESC_NUM)
+#define BIT_SET_HI11Q_DESC_NUM(x, v)                                           \
+	(BIT_CLEAR_HI11Q_DESC_NUM(x) | BIT_HI11Q_DESC_NUM(v))
+
+/* 2 REG_HI12Q_TXBD_NUM			(Offset 0x13C0) */
+
+#define BIT_HI12Q_FLAG BIT(14)
+
+#define BIT_SHIFT_HI12Q_DESC_MODE 12
+#define BIT_MASK_HI12Q_DESC_MODE 0x3
+#define BIT_HI12Q_DESC_MODE(x)                                                 \
+	(((x) & BIT_MASK_HI12Q_DESC_MODE) << BIT_SHIFT_HI12Q_DESC_MODE)
+#define BITS_HI12Q_DESC_MODE                                                   \
+	(BIT_MASK_HI12Q_DESC_MODE << BIT_SHIFT_HI12Q_DESC_MODE)
+#define BIT_CLEAR_HI12Q_DESC_MODE(x) ((x) & (~BITS_HI12Q_DESC_MODE))
+#define BIT_GET_HI12Q_DESC_MODE(x)                                             \
+	(((x) >> BIT_SHIFT_HI12Q_DESC_MODE) & BIT_MASK_HI12Q_DESC_MODE)
+#define BIT_SET_HI12Q_DESC_MODE(x, v)                                          \
+	(BIT_CLEAR_HI12Q_DESC_MODE(x) | BIT_HI12Q_DESC_MODE(v))
+
+#define BIT_SHIFT_HI12Q_DESC_NUM 0
+#define BIT_MASK_HI12Q_DESC_NUM 0xfff
+#define BIT_HI12Q_DESC_NUM(x)                                                  \
+	(((x) & BIT_MASK_HI12Q_DESC_NUM) << BIT_SHIFT_HI12Q_DESC_NUM)
+#define BITS_HI12Q_DESC_NUM                                                    \
+	(BIT_MASK_HI12Q_DESC_NUM << BIT_SHIFT_HI12Q_DESC_NUM)
+#define BIT_CLEAR_HI12Q_DESC_NUM(x) ((x) & (~BITS_HI12Q_DESC_NUM))
+#define BIT_GET_HI12Q_DESC_NUM(x)                                              \
+	(((x) >> BIT_SHIFT_HI12Q_DESC_NUM) & BIT_MASK_HI12Q_DESC_NUM)
+#define BIT_SET_HI12Q_DESC_NUM(x, v)                                           \
+	(BIT_CLEAR_HI12Q_DESC_NUM(x) | BIT_HI12Q_DESC_NUM(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_HI3Q_TXBD_DESA_L			(Offset 0x13C0) */
+
+#define BIT_SHIFT_HI3Q_TXBD_DESA_L 0
+#define BIT_MASK_HI3Q_TXBD_DESA_L 0xffffffffL
+#define BIT_HI3Q_TXBD_DESA_L(x)                                                \
+	(((x) & BIT_MASK_HI3Q_TXBD_DESA_L) << BIT_SHIFT_HI3Q_TXBD_DESA_L)
+#define BITS_HI3Q_TXBD_DESA_L                                                  \
+	(BIT_MASK_HI3Q_TXBD_DESA_L << BIT_SHIFT_HI3Q_TXBD_DESA_L)
+#define BIT_CLEAR_HI3Q_TXBD_DESA_L(x) ((x) & (~BITS_HI3Q_TXBD_DESA_L))
+#define BIT_GET_HI3Q_TXBD_DESA_L(x)                                            \
+	(((x) >> BIT_SHIFT_HI3Q_TXBD_DESA_L) & BIT_MASK_HI3Q_TXBD_DESA_L)
+#define BIT_SET_HI3Q_TXBD_DESA_L(x, v)                                         \
+	(BIT_CLEAR_HI3Q_TXBD_DESA_L(x) | BIT_HI3Q_TXBD_DESA_L(v))
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+/* 2 REG_HI13Q_TXBD_NUM			(Offset 0x13C2) */
+
+#define BIT_HI13Q_FLAG BIT(14)
+
+#define BIT_SHIFT_HI13Q_DESC_MODE 12
+#define BIT_MASK_HI13Q_DESC_MODE 0x3
+#define BIT_HI13Q_DESC_MODE(x)                                                 \
+	(((x) & BIT_MASK_HI13Q_DESC_MODE) << BIT_SHIFT_HI13Q_DESC_MODE)
+#define BITS_HI13Q_DESC_MODE                                                   \
+	(BIT_MASK_HI13Q_DESC_MODE << BIT_SHIFT_HI13Q_DESC_MODE)
+#define BIT_CLEAR_HI13Q_DESC_MODE(x) ((x) & (~BITS_HI13Q_DESC_MODE))
+#define BIT_GET_HI13Q_DESC_MODE(x)                                             \
+	(((x) >> BIT_SHIFT_HI13Q_DESC_MODE) & BIT_MASK_HI13Q_DESC_MODE)
+#define BIT_SET_HI13Q_DESC_MODE(x, v)                                          \
+	(BIT_CLEAR_HI13Q_DESC_MODE(x) | BIT_HI13Q_DESC_MODE(v))
+
+#define BIT_SHIFT_HI13Q_DESC_NUM 0
+#define BIT_MASK_HI13Q_DESC_NUM 0xfff
+#define BIT_HI13Q_DESC_NUM(x)                                                  \
+	(((x) & BIT_MASK_HI13Q_DESC_NUM) << BIT_SHIFT_HI13Q_DESC_NUM)
+#define BITS_HI13Q_DESC_NUM                                                    \
+	(BIT_MASK_HI13Q_DESC_NUM << BIT_SHIFT_HI13Q_DESC_NUM)
+#define BIT_CLEAR_HI13Q_DESC_NUM(x) ((x) & (~BITS_HI13Q_DESC_NUM))
+#define BIT_GET_HI13Q_DESC_NUM(x)                                              \
+	(((x) >> BIT_SHIFT_HI13Q_DESC_NUM) & BIT_MASK_HI13Q_DESC_NUM)
+#define BIT_SET_HI13Q_DESC_NUM(x, v)                                           \
+	(BIT_CLEAR_HI13Q_DESC_NUM(x) | BIT_HI13Q_DESC_NUM(v))
+
+/* 2 REG_HI14Q_TXBD_NUM			(Offset 0x13C4) */
+
+#define BIT_HI14Q_FLAG BIT(14)
+
+#define BIT_SHIFT_HI14Q_DESC_MODE 12
+#define BIT_MASK_HI14Q_DESC_MODE 0x3
+#define BIT_HI14Q_DESC_MODE(x)                                                 \
+	(((x) & BIT_MASK_HI14Q_DESC_MODE) << BIT_SHIFT_HI14Q_DESC_MODE)
+#define BITS_HI14Q_DESC_MODE                                                   \
+	(BIT_MASK_HI14Q_DESC_MODE << BIT_SHIFT_HI14Q_DESC_MODE)
+#define BIT_CLEAR_HI14Q_DESC_MODE(x) ((x) & (~BITS_HI14Q_DESC_MODE))
+#define BIT_GET_HI14Q_DESC_MODE(x)                                             \
+	(((x) >> BIT_SHIFT_HI14Q_DESC_MODE) & BIT_MASK_HI14Q_DESC_MODE)
+#define BIT_SET_HI14Q_DESC_MODE(x, v)                                          \
+	(BIT_CLEAR_HI14Q_DESC_MODE(x) | BIT_HI14Q_DESC_MODE(v))
+
+#define BIT_SHIFT_HI14Q_DESC_NUM 0
+#define BIT_MASK_HI14Q_DESC_NUM 0xfff
+#define BIT_HI14Q_DESC_NUM(x)                                                  \
+	(((x) & BIT_MASK_HI14Q_DESC_NUM) << BIT_SHIFT_HI14Q_DESC_NUM)
+#define BITS_HI14Q_DESC_NUM                                                    \
+	(BIT_MASK_HI14Q_DESC_NUM << BIT_SHIFT_HI14Q_DESC_NUM)
+#define BIT_CLEAR_HI14Q_DESC_NUM(x) ((x) & (~BITS_HI14Q_DESC_NUM))
+#define BIT_GET_HI14Q_DESC_NUM(x)                                              \
+	(((x) >> BIT_SHIFT_HI14Q_DESC_NUM) & BIT_MASK_HI14Q_DESC_NUM)
+#define BIT_SET_HI14Q_DESC_NUM(x, v)                                           \
+	(BIT_CLEAR_HI14Q_DESC_NUM(x) | BIT_HI14Q_DESC_NUM(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_HI3Q_TXBD_DESA_H			(Offset 0x13C4) */
+
+#define BIT_SHIFT_HI3Q_TXBD_DESA_H 0
+#define BIT_MASK_HI3Q_TXBD_DESA_H 0xffffffffL
+#define BIT_HI3Q_TXBD_DESA_H(x)                                                \
+	(((x) & BIT_MASK_HI3Q_TXBD_DESA_H) << BIT_SHIFT_HI3Q_TXBD_DESA_H)
+#define BITS_HI3Q_TXBD_DESA_H                                                  \
+	(BIT_MASK_HI3Q_TXBD_DESA_H << BIT_SHIFT_HI3Q_TXBD_DESA_H)
+#define BIT_CLEAR_HI3Q_TXBD_DESA_H(x) ((x) & (~BITS_HI3Q_TXBD_DESA_H))
+#define BIT_GET_HI3Q_TXBD_DESA_H(x)                                            \
+	(((x) >> BIT_SHIFT_HI3Q_TXBD_DESA_H) & BIT_MASK_HI3Q_TXBD_DESA_H)
+#define BIT_SET_HI3Q_TXBD_DESA_H(x, v)                                         \
+	(BIT_CLEAR_HI3Q_TXBD_DESA_H(x) | BIT_HI3Q_TXBD_DESA_H(v))
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+/* 2 REG_HI15Q_TXBD_NUM			(Offset 0x13C6) */
+
+#define BIT_HI15Q_FLAG BIT(14)
+
+#define BIT_SHIFT_HI15Q_DESC_MODE 12
+#define BIT_MASK_HI15Q_DESC_MODE 0x3
+#define BIT_HI15Q_DESC_MODE(x)                                                 \
+	(((x) & BIT_MASK_HI15Q_DESC_MODE) << BIT_SHIFT_HI15Q_DESC_MODE)
+#define BITS_HI15Q_DESC_MODE                                                   \
+	(BIT_MASK_HI15Q_DESC_MODE << BIT_SHIFT_HI15Q_DESC_MODE)
+#define BIT_CLEAR_HI15Q_DESC_MODE(x) ((x) & (~BITS_HI15Q_DESC_MODE))
+#define BIT_GET_HI15Q_DESC_MODE(x)                                             \
+	(((x) >> BIT_SHIFT_HI15Q_DESC_MODE) & BIT_MASK_HI15Q_DESC_MODE)
+#define BIT_SET_HI15Q_DESC_MODE(x, v)                                          \
+	(BIT_CLEAR_HI15Q_DESC_MODE(x) | BIT_HI15Q_DESC_MODE(v))
+
+#define BIT_SHIFT_HI15Q_DESC_NUM 0
+#define BIT_MASK_HI15Q_DESC_NUM 0xfff
+#define BIT_HI15Q_DESC_NUM(x)                                                  \
+	(((x) & BIT_MASK_HI15Q_DESC_NUM) << BIT_SHIFT_HI15Q_DESC_NUM)
+#define BITS_HI15Q_DESC_NUM                                                    \
+	(BIT_MASK_HI15Q_DESC_NUM << BIT_SHIFT_HI15Q_DESC_NUM)
+#define BIT_CLEAR_HI15Q_DESC_NUM(x) ((x) & (~BITS_HI15Q_DESC_NUM))
+#define BIT_GET_HI15Q_DESC_NUM(x)                                              \
+	(((x) >> BIT_SHIFT_HI15Q_DESC_NUM) & BIT_MASK_HI15Q_DESC_NUM)
+#define BIT_SET_HI15Q_DESC_NUM(x, v)                                           \
+	(BIT_CLEAR_HI15Q_DESC_NUM(x) | BIT_HI15Q_DESC_NUM(v))
+
+/* 2 REG_HIQ_DMA_STOP			(Offset 0x13C8) */
+
+#define BIT_STOP_HI15Q BIT(7)
+#define BIT_STOP_HI14Q BIT(6)
+#define BIT_STOP_HI13Q BIT(5)
+#define BIT_STOP_HI12Q BIT(4)
+#define BIT_STOP_HI11Q BIT(3)
+#define BIT_STOP_HI10Q BIT(2)
+#define BIT_STOP_HI9Q BIT(1)
+#define BIT_STOP_HI8Q BIT(0)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_HI4Q_TXBD_DESA_L			(Offset 0x13C8) */
+
+#define BIT_SHIFT_HI4Q_TXBD_DESA_L 0
+#define BIT_MASK_HI4Q_TXBD_DESA_L 0xffffffffL
+#define BIT_HI4Q_TXBD_DESA_L(x)                                                \
+	(((x) & BIT_MASK_HI4Q_TXBD_DESA_L) << BIT_SHIFT_HI4Q_TXBD_DESA_L)
+#define BITS_HI4Q_TXBD_DESA_L                                                  \
+	(BIT_MASK_HI4Q_TXBD_DESA_L << BIT_SHIFT_HI4Q_TXBD_DESA_L)
+#define BIT_CLEAR_HI4Q_TXBD_DESA_L(x) ((x) & (~BITS_HI4Q_TXBD_DESA_L))
+#define BIT_GET_HI4Q_TXBD_DESA_L(x)                                            \
+	(((x) >> BIT_SHIFT_HI4Q_TXBD_DESA_L) & BIT_MASK_HI4Q_TXBD_DESA_L)
+#define BIT_SET_HI4Q_TXBD_DESA_L(x, v)                                         \
+	(BIT_CLEAR_HI4Q_TXBD_DESA_L(x) | BIT_HI4Q_TXBD_DESA_L(v))
+
+/* 2 REG_HI4Q_TXBD_DESA_H			(Offset 0x13CC) */
+
+#define BIT_SHIFT_HI4Q_TXBD_DESA_H 0
+#define BIT_MASK_HI4Q_TXBD_DESA_H 0xffffffffL
+#define BIT_HI4Q_TXBD_DESA_H(x)                                                \
+	(((x) & BIT_MASK_HI4Q_TXBD_DESA_H) << BIT_SHIFT_HI4Q_TXBD_DESA_H)
+#define BITS_HI4Q_TXBD_DESA_H                                                  \
+	(BIT_MASK_HI4Q_TXBD_DESA_H << BIT_SHIFT_HI4Q_TXBD_DESA_H)
+#define BIT_CLEAR_HI4Q_TXBD_DESA_H(x) ((x) & (~BITS_HI4Q_TXBD_DESA_H))
+#define BIT_GET_HI4Q_TXBD_DESA_H(x)                                            \
+	(((x) >> BIT_SHIFT_HI4Q_TXBD_DESA_H) & BIT_MASK_HI4Q_TXBD_DESA_H)
+#define BIT_SET_HI4Q_TXBD_DESA_H(x, v)                                         \
+	(BIT_CLEAR_HI4Q_TXBD_DESA_H(x) | BIT_HI4Q_TXBD_DESA_H(v))
+
+/* 2 REG_HI5Q_TXBD_DESA_L			(Offset 0x13D0) */
+
+#define BIT_SHIFT_HI5Q_TXBD_DESA_L 0
+#define BIT_MASK_HI5Q_TXBD_DESA_L 0xffffffffL
+#define BIT_HI5Q_TXBD_DESA_L(x)                                                \
+	(((x) & BIT_MASK_HI5Q_TXBD_DESA_L) << BIT_SHIFT_HI5Q_TXBD_DESA_L)
+#define BITS_HI5Q_TXBD_DESA_L                                                  \
+	(BIT_MASK_HI5Q_TXBD_DESA_L << BIT_SHIFT_HI5Q_TXBD_DESA_L)
+#define BIT_CLEAR_HI5Q_TXBD_DESA_L(x) ((x) & (~BITS_HI5Q_TXBD_DESA_L))
+#define BIT_GET_HI5Q_TXBD_DESA_L(x)                                            \
+	(((x) >> BIT_SHIFT_HI5Q_TXBD_DESA_L) & BIT_MASK_HI5Q_TXBD_DESA_L)
+#define BIT_SET_HI5Q_TXBD_DESA_L(x, v)                                         \
+	(BIT_CLEAR_HI5Q_TXBD_DESA_L(x) | BIT_HI5Q_TXBD_DESA_L(v))
+
+/* 2 REG_HI5Q_TXBD_DESA_H			(Offset 0x13D4) */
+
+#define BIT_SHIFT_HI5Q_TXBD_DESA_H 0
+#define BIT_MASK_HI5Q_TXBD_DESA_H 0xffffffffL
+#define BIT_HI5Q_TXBD_DESA_H(x)                                                \
+	(((x) & BIT_MASK_HI5Q_TXBD_DESA_H) << BIT_SHIFT_HI5Q_TXBD_DESA_H)
+#define BITS_HI5Q_TXBD_DESA_H                                                  \
+	(BIT_MASK_HI5Q_TXBD_DESA_H << BIT_SHIFT_HI5Q_TXBD_DESA_H)
+#define BIT_CLEAR_HI5Q_TXBD_DESA_H(x) ((x) & (~BITS_HI5Q_TXBD_DESA_H))
+#define BIT_GET_HI5Q_TXBD_DESA_H(x)                                            \
+	(((x) >> BIT_SHIFT_HI5Q_TXBD_DESA_H) & BIT_MASK_HI5Q_TXBD_DESA_H)
+#define BIT_SET_HI5Q_TXBD_DESA_H(x, v)                                         \
+	(BIT_CLEAR_HI5Q_TXBD_DESA_H(x) | BIT_HI5Q_TXBD_DESA_H(v))
+
+/* 2 REG_HI6Q_TXBD_DESA_L			(Offset 0x13D8) */
+
+#define BIT_SHIFT_HI6Q_TXBD_DESA_L 0
+#define BIT_MASK_HI6Q_TXBD_DESA_L 0xffffffffL
+#define BIT_HI6Q_TXBD_DESA_L(x)                                                \
+	(((x) & BIT_MASK_HI6Q_TXBD_DESA_L) << BIT_SHIFT_HI6Q_TXBD_DESA_L)
+#define BITS_HI6Q_TXBD_DESA_L                                                  \
+	(BIT_MASK_HI6Q_TXBD_DESA_L << BIT_SHIFT_HI6Q_TXBD_DESA_L)
+#define BIT_CLEAR_HI6Q_TXBD_DESA_L(x) ((x) & (~BITS_HI6Q_TXBD_DESA_L))
+#define BIT_GET_HI6Q_TXBD_DESA_L(x)                                            \
+	(((x) >> BIT_SHIFT_HI6Q_TXBD_DESA_L) & BIT_MASK_HI6Q_TXBD_DESA_L)
+#define BIT_SET_HI6Q_TXBD_DESA_L(x, v)                                         \
+	(BIT_CLEAR_HI6Q_TXBD_DESA_L(x) | BIT_HI6Q_TXBD_DESA_L(v))
+
+/* 2 REG_HI6Q_TXBD_DESA_H			(Offset 0x13DC) */
+
+#define BIT_SHIFT_HI6Q_TXBD_DESA_H 0
+#define BIT_MASK_HI6Q_TXBD_DESA_H 0xffffffffL
+#define BIT_HI6Q_TXBD_DESA_H(x)                                                \
+	(((x) & BIT_MASK_HI6Q_TXBD_DESA_H) << BIT_SHIFT_HI6Q_TXBD_DESA_H)
+#define BITS_HI6Q_TXBD_DESA_H                                                  \
+	(BIT_MASK_HI6Q_TXBD_DESA_H << BIT_SHIFT_HI6Q_TXBD_DESA_H)
+#define BIT_CLEAR_HI6Q_TXBD_DESA_H(x) ((x) & (~BITS_HI6Q_TXBD_DESA_H))
+#define BIT_GET_HI6Q_TXBD_DESA_H(x)                                            \
+	(((x) >> BIT_SHIFT_HI6Q_TXBD_DESA_H) & BIT_MASK_HI6Q_TXBD_DESA_H)
+#define BIT_SET_HI6Q_TXBD_DESA_H(x, v)                                         \
+	(BIT_CLEAR_HI6Q_TXBD_DESA_H(x) | BIT_HI6Q_TXBD_DESA_H(v))
+
+/* 2 REG_HI7Q_TXBD_DESA_L			(Offset 0x13E0) */
+
+#define BIT_SHIFT_HI7Q_TXBD_DESA_L 0
+#define BIT_MASK_HI7Q_TXBD_DESA_L 0xffffffffL
+#define BIT_HI7Q_TXBD_DESA_L(x)                                                \
+	(((x) & BIT_MASK_HI7Q_TXBD_DESA_L) << BIT_SHIFT_HI7Q_TXBD_DESA_L)
+#define BITS_HI7Q_TXBD_DESA_L                                                  \
+	(BIT_MASK_HI7Q_TXBD_DESA_L << BIT_SHIFT_HI7Q_TXBD_DESA_L)
+#define BIT_CLEAR_HI7Q_TXBD_DESA_L(x) ((x) & (~BITS_HI7Q_TXBD_DESA_L))
+#define BIT_GET_HI7Q_TXBD_DESA_L(x)                                            \
+	(((x) >> BIT_SHIFT_HI7Q_TXBD_DESA_L) & BIT_MASK_HI7Q_TXBD_DESA_L)
+#define BIT_SET_HI7Q_TXBD_DESA_L(x, v)                                         \
+	(BIT_CLEAR_HI7Q_TXBD_DESA_L(x) | BIT_HI7Q_TXBD_DESA_L(v))
+
+/* 2 REG_HI7Q_TXBD_DESA_H			(Offset 0x13E4) */
+
+#define BIT_SHIFT_HI7Q_TXBD_DESA_H 0
+#define BIT_MASK_HI7Q_TXBD_DESA_H 0xffffffffL
+#define BIT_HI7Q_TXBD_DESA_H(x)                                                \
+	(((x) & BIT_MASK_HI7Q_TXBD_DESA_H) << BIT_SHIFT_HI7Q_TXBD_DESA_H)
+#define BITS_HI7Q_TXBD_DESA_H                                                  \
+	(BIT_MASK_HI7Q_TXBD_DESA_H << BIT_SHIFT_HI7Q_TXBD_DESA_H)
+#define BIT_CLEAR_HI7Q_TXBD_DESA_H(x) ((x) & (~BITS_HI7Q_TXBD_DESA_H))
+#define BIT_GET_HI7Q_TXBD_DESA_H(x)                                            \
+	(((x) >> BIT_SHIFT_HI7Q_TXBD_DESA_H) & BIT_MASK_HI7Q_TXBD_DESA_H)
+#define BIT_SET_HI7Q_TXBD_DESA_H(x, v)                                         \
+	(BIT_CLEAR_HI7Q_TXBD_DESA_H(x) | BIT_HI7Q_TXBD_DESA_H(v))
+
+/* 2 REG_ACH8_ACH9_TXBD_NUM			(Offset 0x13E8) */
+
+#define BIT_PCIE_ACH9_FLAG BIT(30)
+
+#define BIT_SHIFT_ACH9_DESC_MODE 28
+#define BIT_MASK_ACH9_DESC_MODE 0x3
+#define BIT_ACH9_DESC_MODE(x)                                                  \
+	(((x) & BIT_MASK_ACH9_DESC_MODE) << BIT_SHIFT_ACH9_DESC_MODE)
+#define BITS_ACH9_DESC_MODE                                                    \
+	(BIT_MASK_ACH9_DESC_MODE << BIT_SHIFT_ACH9_DESC_MODE)
+#define BIT_CLEAR_ACH9_DESC_MODE(x) ((x) & (~BITS_ACH9_DESC_MODE))
+#define BIT_GET_ACH9_DESC_MODE(x)                                              \
+	(((x) >> BIT_SHIFT_ACH9_DESC_MODE) & BIT_MASK_ACH9_DESC_MODE)
+#define BIT_SET_ACH9_DESC_MODE(x, v)                                           \
+	(BIT_CLEAR_ACH9_DESC_MODE(x) | BIT_ACH9_DESC_MODE(v))
+
+#define BIT_SHIFT_ACH9_DESC_NUM 16
+#define BIT_MASK_ACH9_DESC_NUM 0xfff
+#define BIT_ACH9_DESC_NUM(x)                                                   \
+	(((x) & BIT_MASK_ACH9_DESC_NUM) << BIT_SHIFT_ACH9_DESC_NUM)
+#define BITS_ACH9_DESC_NUM (BIT_MASK_ACH9_DESC_NUM << BIT_SHIFT_ACH9_DESC_NUM)
+#define BIT_CLEAR_ACH9_DESC_NUM(x) ((x) & (~BITS_ACH9_DESC_NUM))
+#define BIT_GET_ACH9_DESC_NUM(x)                                               \
+	(((x) >> BIT_SHIFT_ACH9_DESC_NUM) & BIT_MASK_ACH9_DESC_NUM)
+#define BIT_SET_ACH9_DESC_NUM(x, v)                                            \
+	(BIT_CLEAR_ACH9_DESC_NUM(x) | BIT_ACH9_DESC_NUM(v))
+
+#define BIT_PCIE_ACH8_FLAG BIT(14)
+
+#define BIT_SHIFT_ACH8_DESC_MODE 12
+#define BIT_MASK_ACH8_DESC_MODE 0x3
+#define BIT_ACH8_DESC_MODE(x)                                                  \
+	(((x) & BIT_MASK_ACH8_DESC_MODE) << BIT_SHIFT_ACH8_DESC_MODE)
+#define BITS_ACH8_DESC_MODE                                                    \
+	(BIT_MASK_ACH8_DESC_MODE << BIT_SHIFT_ACH8_DESC_MODE)
+#define BIT_CLEAR_ACH8_DESC_MODE(x) ((x) & (~BITS_ACH8_DESC_MODE))
+#define BIT_GET_ACH8_DESC_MODE(x)                                              \
+	(((x) >> BIT_SHIFT_ACH8_DESC_MODE) & BIT_MASK_ACH8_DESC_MODE)
+#define BIT_SET_ACH8_DESC_MODE(x, v)                                           \
+	(BIT_CLEAR_ACH8_DESC_MODE(x) | BIT_ACH8_DESC_MODE(v))
+
+#define BIT_SHIFT_ACH8_DESC_NUM 0
+#define BIT_MASK_ACH8_DESC_NUM 0xfff
+#define BIT_ACH8_DESC_NUM(x)                                                   \
+	(((x) & BIT_MASK_ACH8_DESC_NUM) << BIT_SHIFT_ACH8_DESC_NUM)
+#define BITS_ACH8_DESC_NUM (BIT_MASK_ACH8_DESC_NUM << BIT_SHIFT_ACH8_DESC_NUM)
+#define BIT_CLEAR_ACH8_DESC_NUM(x) ((x) & (~BITS_ACH8_DESC_NUM))
+#define BIT_GET_ACH8_DESC_NUM(x)                                               \
+	(((x) >> BIT_SHIFT_ACH8_DESC_NUM) & BIT_MASK_ACH8_DESC_NUM)
+#define BIT_SET_ACH8_DESC_NUM(x, v)                                            \
+	(BIT_CLEAR_ACH8_DESC_NUM(x) | BIT_ACH8_DESC_NUM(v))
+
+/* 2 REG_ACH10_ACH11_TXBD_NUM		(Offset 0x13EC) */
+
+#define BIT_PCIE_ACH11_FLAG BIT(30)
+
+#define BIT_SHIFT_ACH11_DESC_MODE 28
+#define BIT_MASK_ACH11_DESC_MODE 0x3
+#define BIT_ACH11_DESC_MODE(x)                                                 \
+	(((x) & BIT_MASK_ACH11_DESC_MODE) << BIT_SHIFT_ACH11_DESC_MODE)
+#define BITS_ACH11_DESC_MODE                                                   \
+	(BIT_MASK_ACH11_DESC_MODE << BIT_SHIFT_ACH11_DESC_MODE)
+#define BIT_CLEAR_ACH11_DESC_MODE(x) ((x) & (~BITS_ACH11_DESC_MODE))
+#define BIT_GET_ACH11_DESC_MODE(x)                                             \
+	(((x) >> BIT_SHIFT_ACH11_DESC_MODE) & BIT_MASK_ACH11_DESC_MODE)
+#define BIT_SET_ACH11_DESC_MODE(x, v)                                          \
+	(BIT_CLEAR_ACH11_DESC_MODE(x) | BIT_ACH11_DESC_MODE(v))
+
+#define BIT_SHIFT_ACH11_DESC_NUM 16
+#define BIT_MASK_ACH11_DESC_NUM 0xfff
+#define BIT_ACH11_DESC_NUM(x)                                                  \
+	(((x) & BIT_MASK_ACH11_DESC_NUM) << BIT_SHIFT_ACH11_DESC_NUM)
+#define BITS_ACH11_DESC_NUM                                                    \
+	(BIT_MASK_ACH11_DESC_NUM << BIT_SHIFT_ACH11_DESC_NUM)
+#define BIT_CLEAR_ACH11_DESC_NUM(x) ((x) & (~BITS_ACH11_DESC_NUM))
+#define BIT_GET_ACH11_DESC_NUM(x)                                              \
+	(((x) >> BIT_SHIFT_ACH11_DESC_NUM) & BIT_MASK_ACH11_DESC_NUM)
+#define BIT_SET_ACH11_DESC_NUM(x, v)                                           \
+	(BIT_CLEAR_ACH11_DESC_NUM(x) | BIT_ACH11_DESC_NUM(v))
+
+#define BIT_PCIE_ACH10_FLAG BIT(14)
+
+#define BIT_SHIFT_ACH10_DESC_MODE 12
+#define BIT_MASK_ACH10_DESC_MODE 0x3
+#define BIT_ACH10_DESC_MODE(x)                                                 \
+	(((x) & BIT_MASK_ACH10_DESC_MODE) << BIT_SHIFT_ACH10_DESC_MODE)
+#define BITS_ACH10_DESC_MODE                                                   \
+	(BIT_MASK_ACH10_DESC_MODE << BIT_SHIFT_ACH10_DESC_MODE)
+#define BIT_CLEAR_ACH10_DESC_MODE(x) ((x) & (~BITS_ACH10_DESC_MODE))
+#define BIT_GET_ACH10_DESC_MODE(x)                                             \
+	(((x) >> BIT_SHIFT_ACH10_DESC_MODE) & BIT_MASK_ACH10_DESC_MODE)
+#define BIT_SET_ACH10_DESC_MODE(x, v)                                          \
+	(BIT_CLEAR_ACH10_DESC_MODE(x) | BIT_ACH10_DESC_MODE(v))
+
+#define BIT_SHIFT_ACH10_DESC_NUM 0
+#define BIT_MASK_ACH10_DESC_NUM 0xfff
+#define BIT_ACH10_DESC_NUM(x)                                                  \
+	(((x) & BIT_MASK_ACH10_DESC_NUM) << BIT_SHIFT_ACH10_DESC_NUM)
+#define BITS_ACH10_DESC_NUM                                                    \
+	(BIT_MASK_ACH10_DESC_NUM << BIT_SHIFT_ACH10_DESC_NUM)
+#define BIT_CLEAR_ACH10_DESC_NUM(x) ((x) & (~BITS_ACH10_DESC_NUM))
+#define BIT_GET_ACH10_DESC_NUM(x)                                              \
+	(((x) >> BIT_SHIFT_ACH10_DESC_NUM) & BIT_MASK_ACH10_DESC_NUM)
+#define BIT_SET_ACH10_DESC_NUM(x, v)                                           \
+	(BIT_CLEAR_ACH10_DESC_NUM(x) | BIT_ACH10_DESC_NUM(v))
+
+/* 2 REG_ACH12_ACH13_TXBD_NUM		(Offset 0x13F0) */
+
+#define BIT_PCIE_ACH13_FLAG BIT(30)
+
+#define BIT_SHIFT_ACH13_DESC_MODE 28
+#define BIT_MASK_ACH13_DESC_MODE 0x3
+#define BIT_ACH13_DESC_MODE(x)                                                 \
+	(((x) & BIT_MASK_ACH13_DESC_MODE) << BIT_SHIFT_ACH13_DESC_MODE)
+#define BITS_ACH13_DESC_MODE                                                   \
+	(BIT_MASK_ACH13_DESC_MODE << BIT_SHIFT_ACH13_DESC_MODE)
+#define BIT_CLEAR_ACH13_DESC_MODE(x) ((x) & (~BITS_ACH13_DESC_MODE))
+#define BIT_GET_ACH13_DESC_MODE(x)                                             \
+	(((x) >> BIT_SHIFT_ACH13_DESC_MODE) & BIT_MASK_ACH13_DESC_MODE)
+#define BIT_SET_ACH13_DESC_MODE(x, v)                                          \
+	(BIT_CLEAR_ACH13_DESC_MODE(x) | BIT_ACH13_DESC_MODE(v))
+
+#define BIT_SHIFT_ACH13_DESC_NUM 16
+#define BIT_MASK_ACH13_DESC_NUM 0xfff
+#define BIT_ACH13_DESC_NUM(x)                                                  \
+	(((x) & BIT_MASK_ACH13_DESC_NUM) << BIT_SHIFT_ACH13_DESC_NUM)
+#define BITS_ACH13_DESC_NUM                                                    \
+	(BIT_MASK_ACH13_DESC_NUM << BIT_SHIFT_ACH13_DESC_NUM)
+#define BIT_CLEAR_ACH13_DESC_NUM(x) ((x) & (~BITS_ACH13_DESC_NUM))
+#define BIT_GET_ACH13_DESC_NUM(x)                                              \
+	(((x) >> BIT_SHIFT_ACH13_DESC_NUM) & BIT_MASK_ACH13_DESC_NUM)
+#define BIT_SET_ACH13_DESC_NUM(x, v)                                           \
+	(BIT_CLEAR_ACH13_DESC_NUM(x) | BIT_ACH13_DESC_NUM(v))
+
+#define BIT_PCIE_ACH12_FLAG BIT(14)
+
+#define BIT_SHIFT_ACH12_DESC_MODE 12
+#define BIT_MASK_ACH12_DESC_MODE 0x3
+#define BIT_ACH12_DESC_MODE(x)                                                 \
+	(((x) & BIT_MASK_ACH12_DESC_MODE) << BIT_SHIFT_ACH12_DESC_MODE)
+#define BITS_ACH12_DESC_MODE                                                   \
+	(BIT_MASK_ACH12_DESC_MODE << BIT_SHIFT_ACH12_DESC_MODE)
+#define BIT_CLEAR_ACH12_DESC_MODE(x) ((x) & (~BITS_ACH12_DESC_MODE))
+#define BIT_GET_ACH12_DESC_MODE(x)                                             \
+	(((x) >> BIT_SHIFT_ACH12_DESC_MODE) & BIT_MASK_ACH12_DESC_MODE)
+#define BIT_SET_ACH12_DESC_MODE(x, v)                                          \
+	(BIT_CLEAR_ACH12_DESC_MODE(x) | BIT_ACH12_DESC_MODE(v))
+
+#define BIT_SHIFT_ACH12_DESC_NUM 0
+#define BIT_MASK_ACH12_DESC_NUM 0xfff
+#define BIT_ACH12_DESC_NUM(x)                                                  \
+	(((x) & BIT_MASK_ACH12_DESC_NUM) << BIT_SHIFT_ACH12_DESC_NUM)
+#define BITS_ACH12_DESC_NUM                                                    \
+	(BIT_MASK_ACH12_DESC_NUM << BIT_SHIFT_ACH12_DESC_NUM)
+#define BIT_CLEAR_ACH12_DESC_NUM(x) ((x) & (~BITS_ACH12_DESC_NUM))
+#define BIT_GET_ACH12_DESC_NUM(x)                                              \
+	(((x) >> BIT_SHIFT_ACH12_DESC_NUM) & BIT_MASK_ACH12_DESC_NUM)
+#define BIT_SET_ACH12_DESC_NUM(x, v)                                           \
+	(BIT_CLEAR_ACH12_DESC_NUM(x) | BIT_ACH12_DESC_NUM(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT || HALMAC_8822B_SUPPORT)
+
+/* 2 REG_OLD_DEHANG				(Offset 0x13F4) */
+
+#define BIT_OLD_DEHANG BIT(1)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_ACH4_TXBD_DESA_L			(Offset 0x13F8) */
+
+#define BIT_SHIFT_ACH4_TXBD_DESA_L 0
+#define BIT_MASK_ACH4_TXBD_DESA_L 0xffffffffL
+#define BIT_ACH4_TXBD_DESA_L(x)                                                \
+	(((x) & BIT_MASK_ACH4_TXBD_DESA_L) << BIT_SHIFT_ACH4_TXBD_DESA_L)
+#define BITS_ACH4_TXBD_DESA_L                                                  \
+	(BIT_MASK_ACH4_TXBD_DESA_L << BIT_SHIFT_ACH4_TXBD_DESA_L)
+#define BIT_CLEAR_ACH4_TXBD_DESA_L(x) ((x) & (~BITS_ACH4_TXBD_DESA_L))
+#define BIT_GET_ACH4_TXBD_DESA_L(x)                                            \
+	(((x) >> BIT_SHIFT_ACH4_TXBD_DESA_L) & BIT_MASK_ACH4_TXBD_DESA_L)
+#define BIT_SET_ACH4_TXBD_DESA_L(x, v)                                         \
+	(BIT_CLEAR_ACH4_TXBD_DESA_L(x) | BIT_ACH4_TXBD_DESA_L(v))
+
+/* 2 REG_ACH4_TXBD_DESA_H			(Offset 0x13FC) */
+
+#define BIT_SHIFT_ACH4_TXBD_DESA_H 0
+#define BIT_MASK_ACH4_TXBD_DESA_H 0xffffffffL
+#define BIT_ACH4_TXBD_DESA_H(x)                                                \
+	(((x) & BIT_MASK_ACH4_TXBD_DESA_H) << BIT_SHIFT_ACH4_TXBD_DESA_H)
+#define BITS_ACH4_TXBD_DESA_H                                                  \
+	(BIT_MASK_ACH4_TXBD_DESA_H << BIT_SHIFT_ACH4_TXBD_DESA_H)
+#define BIT_CLEAR_ACH4_TXBD_DESA_H(x) ((x) & (~BITS_ACH4_TXBD_DESA_H))
+#define BIT_GET_ACH4_TXBD_DESA_H(x)                                            \
+	(((x) >> BIT_SHIFT_ACH4_TXBD_DESA_H) & BIT_MASK_ACH4_TXBD_DESA_H)
+#define BIT_SET_ACH4_TXBD_DESA_H(x, v)                                         \
+	(BIT_CLEAR_ACH4_TXBD_DESA_H(x) | BIT_ACH4_TXBD_DESA_H(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_Q0_Q1_INFO				(Offset 0x1400) */
+
+#define BIT_SHIFT_AC1_PKT_INFO 16
+#define BIT_MASK_AC1_PKT_INFO 0xfff
+#define BIT_AC1_PKT_INFO(x)                                                    \
+	(((x) & BIT_MASK_AC1_PKT_INFO) << BIT_SHIFT_AC1_PKT_INFO)
+#define BITS_AC1_PKT_INFO (BIT_MASK_AC1_PKT_INFO << BIT_SHIFT_AC1_PKT_INFO)
+#define BIT_CLEAR_AC1_PKT_INFO(x) ((x) & (~BITS_AC1_PKT_INFO))
+#define BIT_GET_AC1_PKT_INFO(x)                                                \
+	(((x) >> BIT_SHIFT_AC1_PKT_INFO) & BIT_MASK_AC1_PKT_INFO)
+#define BIT_SET_AC1_PKT_INFO(x, v)                                             \
+	(BIT_CLEAR_AC1_PKT_INFO(x) | BIT_AC1_PKT_INFO(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_MU_OFFSET				(Offset 0x1400) */
+
+#define BIT_SHIFT_MU_RATETABLE_OFFSET 16
+#define BIT_MASK_MU_RATETABLE_OFFSET 0x1ff
+#define BIT_MU_RATETABLE_OFFSET(x)                                             \
+	(((x) & BIT_MASK_MU_RATETABLE_OFFSET) << BIT_SHIFT_MU_RATETABLE_OFFSET)
+#define BITS_MU_RATETABLE_OFFSET                                               \
+	(BIT_MASK_MU_RATETABLE_OFFSET << BIT_SHIFT_MU_RATETABLE_OFFSET)
+#define BIT_CLEAR_MU_RATETABLE_OFFSET(x) ((x) & (~BITS_MU_RATETABLE_OFFSET))
+#define BIT_GET_MU_RATETABLE_OFFSET(x)                                         \
+	(((x) >> BIT_SHIFT_MU_RATETABLE_OFFSET) & BIT_MASK_MU_RATETABLE_OFFSET)
+#define BIT_SET_MU_RATETABLE_OFFSET(x, v)                                      \
+	(BIT_CLEAR_MU_RATETABLE_OFFSET(x) | BIT_MU_RATETABLE_OFFSET(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_Q0_Q1_INFO				(Offset 0x1400) */
+
+#define BIT_SHIFT_AC0_PKT_INFO 0
+#define BIT_MASK_AC0_PKT_INFO 0xfff
+#define BIT_AC0_PKT_INFO(x)                                                    \
+	(((x) & BIT_MASK_AC0_PKT_INFO) << BIT_SHIFT_AC0_PKT_INFO)
+#define BITS_AC0_PKT_INFO (BIT_MASK_AC0_PKT_INFO << BIT_SHIFT_AC0_PKT_INFO)
+#define BIT_CLEAR_AC0_PKT_INFO(x) ((x) & (~BITS_AC0_PKT_INFO))
+#define BIT_GET_AC0_PKT_INFO(x)                                                \
+	(((x) >> BIT_SHIFT_AC0_PKT_INFO) & BIT_MASK_AC0_PKT_INFO)
+#define BIT_SET_AC0_PKT_INFO(x, v)                                             \
+	(BIT_CLEAR_AC0_PKT_INFO(x) | BIT_AC0_PKT_INFO(v))
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+/* 2 REG_ARFR6				(Offset 0x1400) */
+
+#define BIT_SHIFT_ARFR6_V1 0
+#define BIT_MASK_ARFR6_V1 0xffffffffffffffffL
+#define BIT_ARFR6_V1(x) (((x) & BIT_MASK_ARFR6_V1) << BIT_SHIFT_ARFR6_V1)
+#define BITS_ARFR6_V1 (BIT_MASK_ARFR6_V1 << BIT_SHIFT_ARFR6_V1)
+#define BIT_CLEAR_ARFR6_V1(x) ((x) & (~BITS_ARFR6_V1))
+#define BIT_GET_ARFR6_V1(x) (((x) >> BIT_SHIFT_ARFR6_V1) & BIT_MASK_ARFR6_V1)
+#define BIT_SET_ARFR6_V1(x, v) (BIT_CLEAR_ARFR6_V1(x) | BIT_ARFR6_V1(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_MU_OFFSET				(Offset 0x1400) */
+
+#define BIT_SHIFT_MU_SCORETABLE_OFFSET 0
+#define BIT_MASK_MU_SCORETABLE_OFFSET 0x1ff
+#define BIT_MU_SCORETABLE_OFFSET(x)                                            \
+	(((x) & BIT_MASK_MU_SCORETABLE_OFFSET)                                 \
+	 << BIT_SHIFT_MU_SCORETABLE_OFFSET)
+#define BITS_MU_SCORETABLE_OFFSET                                              \
+	(BIT_MASK_MU_SCORETABLE_OFFSET << BIT_SHIFT_MU_SCORETABLE_OFFSET)
+#define BIT_CLEAR_MU_SCORETABLE_OFFSET(x) ((x) & (~BITS_MU_SCORETABLE_OFFSET))
+#define BIT_GET_MU_SCORETABLE_OFFSET(x)                                        \
+	(((x) >> BIT_SHIFT_MU_SCORETABLE_OFFSET) &                             \
+	 BIT_MASK_MU_SCORETABLE_OFFSET)
+#define BIT_SET_MU_SCORETABLE_OFFSET(x, v)                                     \
+	(BIT_CLEAR_MU_SCORETABLE_OFFSET(x) | BIT_MU_SCORETABLE_OFFSET(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_Q2_Q3_INFO				(Offset 0x1404) */
+
+#define BIT_SHIFT_AC3_PKT_INFO 16
+#define BIT_MASK_AC3_PKT_INFO 0xfff
+#define BIT_AC3_PKT_INFO(x)                                                    \
+	(((x) & BIT_MASK_AC3_PKT_INFO) << BIT_SHIFT_AC3_PKT_INFO)
+#define BITS_AC3_PKT_INFO (BIT_MASK_AC3_PKT_INFO << BIT_SHIFT_AC3_PKT_INFO)
+#define BIT_CLEAR_AC3_PKT_INFO(x) ((x) & (~BITS_AC3_PKT_INFO))
+#define BIT_GET_AC3_PKT_INFO(x)                                                \
+	(((x) >> BIT_SHIFT_AC3_PKT_INFO) & BIT_MASK_AC3_PKT_INFO)
+#define BIT_SET_AC3_PKT_INFO(x, v)                                             \
+	(BIT_CLEAR_AC3_PKT_INFO(x) | BIT_AC3_PKT_INFO(v))
+
+#define BIT_SHIFT_AC2_PKT_INFO 0
+#define BIT_MASK_AC2_PKT_INFO 0xfff
+#define BIT_AC2_PKT_INFO(x)                                                    \
+	(((x) & BIT_MASK_AC2_PKT_INFO) << BIT_SHIFT_AC2_PKT_INFO)
+#define BITS_AC2_PKT_INFO (BIT_MASK_AC2_PKT_INFO << BIT_SHIFT_AC2_PKT_INFO)
+#define BIT_CLEAR_AC2_PKT_INFO(x) ((x) & (~BITS_AC2_PKT_INFO))
+#define BIT_GET_AC2_PKT_INFO(x)                                                \
+	(((x) >> BIT_SHIFT_AC2_PKT_INFO) & BIT_MASK_AC2_PKT_INFO)
+#define BIT_SET_AC2_PKT_INFO(x, v)                                             \
+	(BIT_CLEAR_AC2_PKT_INFO(x) | BIT_AC2_PKT_INFO(v))
+
+/* 2 REG_Q4_Q5_INFO				(Offset 0x1408) */
+
+#define BIT_SHIFT_AC5_PKT_INFO 16
+#define BIT_MASK_AC5_PKT_INFO 0xfff
+#define BIT_AC5_PKT_INFO(x)                                                    \
+	(((x) & BIT_MASK_AC5_PKT_INFO) << BIT_SHIFT_AC5_PKT_INFO)
+#define BITS_AC5_PKT_INFO (BIT_MASK_AC5_PKT_INFO << BIT_SHIFT_AC5_PKT_INFO)
+#define BIT_CLEAR_AC5_PKT_INFO(x) ((x) & (~BITS_AC5_PKT_INFO))
+#define BIT_GET_AC5_PKT_INFO(x)                                                \
+	(((x) >> BIT_SHIFT_AC5_PKT_INFO) & BIT_MASK_AC5_PKT_INFO)
+#define BIT_SET_AC5_PKT_INFO(x, v)                                             \
+	(BIT_CLEAR_AC5_PKT_INFO(x) | BIT_AC5_PKT_INFO(v))
+
+#define BIT_SHIFT_AC4_PKT_INFO 0
+#define BIT_MASK_AC4_PKT_INFO 0xfff
+#define BIT_AC4_PKT_INFO(x)                                                    \
+	(((x) & BIT_MASK_AC4_PKT_INFO) << BIT_SHIFT_AC4_PKT_INFO)
+#define BITS_AC4_PKT_INFO (BIT_MASK_AC4_PKT_INFO << BIT_SHIFT_AC4_PKT_INFO)
+#define BIT_CLEAR_AC4_PKT_INFO(x) ((x) & (~BITS_AC4_PKT_INFO))
+#define BIT_GET_AC4_PKT_INFO(x)                                                \
+	(((x) >> BIT_SHIFT_AC4_PKT_INFO) & BIT_MASK_AC4_PKT_INFO)
+#define BIT_SET_AC4_PKT_INFO(x, v)                                             \
+	(BIT_CLEAR_AC4_PKT_INFO(x) | BIT_AC4_PKT_INFO(v))
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+/* 2 REG_ARFR7				(Offset 0x1408) */
+
+#define BIT_SHIFT_ARFR7_V1 0
+#define BIT_MASK_ARFR7_V1 0xffffffffffffffffL
+#define BIT_ARFR7_V1(x) (((x) & BIT_MASK_ARFR7_V1) << BIT_SHIFT_ARFR7_V1)
+#define BITS_ARFR7_V1 (BIT_MASK_ARFR7_V1 << BIT_SHIFT_ARFR7_V1)
+#define BIT_CLEAR_ARFR7_V1(x) ((x) & (~BITS_ARFR7_V1))
+#define BIT_GET_ARFR7_V1(x) (((x) >> BIT_SHIFT_ARFR7_V1) & BIT_MASK_ARFR7_V1)
+#define BIT_SET_ARFR7_V1(x, v) (BIT_CLEAR_ARFR7_V1(x) | BIT_ARFR7_V1(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_Q6_Q7_INFO				(Offset 0x140C) */
+
+#define BIT_SHIFT_AC7_PKT_INFO 16
+#define BIT_MASK_AC7_PKT_INFO 0xfff
+#define BIT_AC7_PKT_INFO(x)                                                    \
+	(((x) & BIT_MASK_AC7_PKT_INFO) << BIT_SHIFT_AC7_PKT_INFO)
+#define BITS_AC7_PKT_INFO (BIT_MASK_AC7_PKT_INFO << BIT_SHIFT_AC7_PKT_INFO)
+#define BIT_CLEAR_AC7_PKT_INFO(x) ((x) & (~BITS_AC7_PKT_INFO))
+#define BIT_GET_AC7_PKT_INFO(x)                                                \
+	(((x) >> BIT_SHIFT_AC7_PKT_INFO) & BIT_MASK_AC7_PKT_INFO)
+#define BIT_SET_AC7_PKT_INFO(x, v)                                             \
+	(BIT_CLEAR_AC7_PKT_INFO(x) | BIT_AC7_PKT_INFO(v))
+
+#define BIT_SHIFT_AC6_PKT_INFO 0
+#define BIT_MASK_AC6_PKT_INFO 0xfff
+#define BIT_AC6_PKT_INFO(x)                                                    \
+	(((x) & BIT_MASK_AC6_PKT_INFO) << BIT_SHIFT_AC6_PKT_INFO)
+#define BITS_AC6_PKT_INFO (BIT_MASK_AC6_PKT_INFO << BIT_SHIFT_AC6_PKT_INFO)
+#define BIT_CLEAR_AC6_PKT_INFO(x) ((x) & (~BITS_AC6_PKT_INFO))
+#define BIT_GET_AC6_PKT_INFO(x)                                                \
+	(((x) >> BIT_SHIFT_AC6_PKT_INFO) & BIT_MASK_AC6_PKT_INFO)
+#define BIT_SET_AC6_PKT_INFO(x, v)                                             \
+	(BIT_CLEAR_AC6_PKT_INFO(x) | BIT_AC6_PKT_INFO(v))
+
+/* 2 REG_MGQ_HIQ_INFO			(Offset 0x1410) */
+
+#define BIT_SHIFT_HIQ_PKT_INFO 16
+#define BIT_MASK_HIQ_PKT_INFO 0xfff
+#define BIT_HIQ_PKT_INFO(x)                                                    \
+	(((x) & BIT_MASK_HIQ_PKT_INFO) << BIT_SHIFT_HIQ_PKT_INFO)
+#define BITS_HIQ_PKT_INFO (BIT_MASK_HIQ_PKT_INFO << BIT_SHIFT_HIQ_PKT_INFO)
+#define BIT_CLEAR_HIQ_PKT_INFO(x) ((x) & (~BITS_HIQ_PKT_INFO))
+#define BIT_GET_HIQ_PKT_INFO(x)                                                \
+	(((x) >> BIT_SHIFT_HIQ_PKT_INFO) & BIT_MASK_HIQ_PKT_INFO)
+#define BIT_SET_HIQ_PKT_INFO(x, v)                                             \
+	(BIT_CLEAR_HIQ_PKT_INFO(x) | BIT_HIQ_PKT_INFO(v))
+
+#define BIT_SHIFT_MGQ_PKT_INFO 0
+#define BIT_MASK_MGQ_PKT_INFO 0xfff
+#define BIT_MGQ_PKT_INFO(x)                                                    \
+	(((x) & BIT_MASK_MGQ_PKT_INFO) << BIT_SHIFT_MGQ_PKT_INFO)
+#define BITS_MGQ_PKT_INFO (BIT_MASK_MGQ_PKT_INFO << BIT_SHIFT_MGQ_PKT_INFO)
+#define BIT_CLEAR_MGQ_PKT_INFO(x) ((x) & (~BITS_MGQ_PKT_INFO))
+#define BIT_GET_MGQ_PKT_INFO(x)                                                \
+	(((x) >> BIT_SHIFT_MGQ_PKT_INFO) & BIT_MASK_MGQ_PKT_INFO)
+#define BIT_SET_MGQ_PKT_INFO(x, v)                                             \
+	(BIT_CLEAR_MGQ_PKT_INFO(x) | BIT_MGQ_PKT_INFO(v))
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+/* 2 REG_ARFR8				(Offset 0x1410) */
+
+#define BIT_SHIFT_ARFR8_V1 0
+#define BIT_MASK_ARFR8_V1 0xffffffffffffffffL
+#define BIT_ARFR8_V1(x) (((x) & BIT_MASK_ARFR8_V1) << BIT_SHIFT_ARFR8_V1)
+#define BITS_ARFR8_V1 (BIT_MASK_ARFR8_V1 << BIT_SHIFT_ARFR8_V1)
+#define BIT_CLEAR_ARFR8_V1(x) ((x) & (~BITS_ARFR8_V1))
+#define BIT_GET_ARFR8_V1(x) (((x) >> BIT_SHIFT_ARFR8_V1) & BIT_MASK_ARFR8_V1)
+#define BIT_SET_ARFR8_V1(x, v) (BIT_CLEAR_ARFR8_V1(x) | BIT_ARFR8_V1(v))
+
+#define BIT_SHIFT_MEDIUM_HAS_IDLE_TRIGGER 0
+#define BIT_MASK_MEDIUM_HAS_IDLE_TRIGGER 0xff
+#define BIT_MEDIUM_HAS_IDLE_TRIGGER(x)                                         \
+	(((x) & BIT_MASK_MEDIUM_HAS_IDLE_TRIGGER)                              \
+	 << BIT_SHIFT_MEDIUM_HAS_IDLE_TRIGGER)
+#define BITS_MEDIUM_HAS_IDLE_TRIGGER                                           \
+	(BIT_MASK_MEDIUM_HAS_IDLE_TRIGGER << BIT_SHIFT_MEDIUM_HAS_IDLE_TRIGGER)
+#define BIT_CLEAR_MEDIUM_HAS_IDLE_TRIGGER(x)                                   \
+	((x) & (~BITS_MEDIUM_HAS_IDLE_TRIGGER))
+#define BIT_GET_MEDIUM_HAS_IDLE_TRIGGER(x)                                     \
+	(((x) >> BIT_SHIFT_MEDIUM_HAS_IDLE_TRIGGER) &                          \
+	 BIT_MASK_MEDIUM_HAS_IDLE_TRIGGER)
+#define BIT_SET_MEDIUM_HAS_IDLE_TRIGGER(x, v)                                  \
+	(BIT_CLEAR_MEDIUM_HAS_IDLE_TRIGGER(x) | BIT_MEDIUM_HAS_IDLE_TRIGGER(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT)
+
+/* 2 REG_CMDQ_BCNQ_INFO			(Offset 0x1414) */
+
+#define BIT_SHIFT_BCNQ_PKT_INFO_V1 16
+#define BIT_MASK_BCNQ_PKT_INFO_V1 0xfff
+#define BIT_BCNQ_PKT_INFO_V1(x)                                                \
+	(((x) & BIT_MASK_BCNQ_PKT_INFO_V1) << BIT_SHIFT_BCNQ_PKT_INFO_V1)
+#define BITS_BCNQ_PKT_INFO_V1                                                  \
+	(BIT_MASK_BCNQ_PKT_INFO_V1 << BIT_SHIFT_BCNQ_PKT_INFO_V1)
+#define BIT_CLEAR_BCNQ_PKT_INFO_V1(x) ((x) & (~BITS_BCNQ_PKT_INFO_V1))
+#define BIT_GET_BCNQ_PKT_INFO_V1(x)                                            \
+	(((x) >> BIT_SHIFT_BCNQ_PKT_INFO_V1) & BIT_MASK_BCNQ_PKT_INFO_V1)
+#define BIT_SET_BCNQ_PKT_INFO_V1(x, v)                                         \
+	(BIT_CLEAR_BCNQ_PKT_INFO_V1(x) | BIT_BCNQ_PKT_INFO_V1(v))
+
+#define BIT_SHIFT_BCNERR_PORT_SEL 16
+#define BIT_MASK_BCNERR_PORT_SEL 0x7
+#define BIT_BCNERR_PORT_SEL(x)                                                 \
+	(((x) & BIT_MASK_BCNERR_PORT_SEL) << BIT_SHIFT_BCNERR_PORT_SEL)
+#define BITS_BCNERR_PORT_SEL                                                   \
+	(BIT_MASK_BCNERR_PORT_SEL << BIT_SHIFT_BCNERR_PORT_SEL)
+#define BIT_CLEAR_BCNERR_PORT_SEL(x) ((x) & (~BITS_BCNERR_PORT_SEL))
+#define BIT_GET_BCNERR_PORT_SEL(x)                                             \
+	(((x) >> BIT_SHIFT_BCNERR_PORT_SEL) & BIT_MASK_BCNERR_PORT_SEL)
+#define BIT_SET_BCNERR_PORT_SEL(x, v)                                          \
+	(BIT_CLEAR_BCNERR_PORT_SEL(x) | BIT_BCNERR_PORT_SEL(v))
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_CMDQ_BCNQ_INFO			(Offset 0x1414) */
+
+#define BIT_SHIFT_CMDQ_PKT_INFO 16
+#define BIT_MASK_CMDQ_PKT_INFO 0xfff
+#define BIT_CMDQ_PKT_INFO(x)                                                   \
+	(((x) & BIT_MASK_CMDQ_PKT_INFO) << BIT_SHIFT_CMDQ_PKT_INFO)
+#define BITS_CMDQ_PKT_INFO (BIT_MASK_CMDQ_PKT_INFO << BIT_SHIFT_CMDQ_PKT_INFO)
+#define BIT_CLEAR_CMDQ_PKT_INFO(x) ((x) & (~BITS_CMDQ_PKT_INFO))
+#define BIT_GET_CMDQ_PKT_INFO(x)                                               \
+	(((x) >> BIT_SHIFT_CMDQ_PKT_INFO) & BIT_MASK_CMDQ_PKT_INFO)
+#define BIT_SET_CMDQ_PKT_INFO(x, v)                                            \
+	(BIT_CLEAR_CMDQ_PKT_INFO(x) | BIT_CMDQ_PKT_INFO(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT)
+
+/* 2 REG_CMDQ_BCNQ_INFO			(Offset 0x1414) */
+
+#define BIT_SHIFT_CMDQ_PKT_INFO_V1 0
+#define BIT_MASK_CMDQ_PKT_INFO_V1 0xfff
+#define BIT_CMDQ_PKT_INFO_V1(x)                                                \
+	(((x) & BIT_MASK_CMDQ_PKT_INFO_V1) << BIT_SHIFT_CMDQ_PKT_INFO_V1)
+#define BITS_CMDQ_PKT_INFO_V1                                                  \
+	(BIT_MASK_CMDQ_PKT_INFO_V1 << BIT_SHIFT_CMDQ_PKT_INFO_V1)
+#define BIT_CLEAR_CMDQ_PKT_INFO_V1(x) ((x) & (~BITS_CMDQ_PKT_INFO_V1))
+#define BIT_GET_CMDQ_PKT_INFO_V1(x)                                            \
+	(((x) >> BIT_SHIFT_CMDQ_PKT_INFO_V1) & BIT_MASK_CMDQ_PKT_INFO_V1)
+#define BIT_SET_CMDQ_PKT_INFO_V1(x, v)                                         \
+	(BIT_CLEAR_CMDQ_PKT_INFO_V1(x) | BIT_CMDQ_PKT_INFO_V1(v))
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_CMDQ_BCNQ_INFO			(Offset 0x1414) */
+
+#define BIT_SHIFT_BCNQ_PKT_INFO 0
+#define BIT_MASK_BCNQ_PKT_INFO 0xfff
+#define BIT_BCNQ_PKT_INFO(x)                                                   \
+	(((x) & BIT_MASK_BCNQ_PKT_INFO) << BIT_SHIFT_BCNQ_PKT_INFO)
+#define BITS_BCNQ_PKT_INFO (BIT_MASK_BCNQ_PKT_INFO << BIT_SHIFT_BCNQ_PKT_INFO)
+#define BIT_CLEAR_BCNQ_PKT_INFO(x) ((x) & (~BITS_BCNQ_PKT_INFO))
+#define BIT_GET_BCNQ_PKT_INFO(x)                                               \
+	(((x) >> BIT_SHIFT_BCNQ_PKT_INFO) & BIT_MASK_BCNQ_PKT_INFO)
+#define BIT_SET_BCNQ_PKT_INFO(x, v)                                            \
+	(BIT_CLEAR_BCNQ_PKT_INFO(x) | BIT_BCNQ_PKT_INFO(v))
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_LOOPBACK_OPTION			(Offset 0x1420) */
+
+#define BIT_LOOPACK_FAST_EDCA_EN BIT(24)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+
+/* 2 REG_USEREG_SETTING			(Offset 0x1420) */
+
+#define BIT_NDPA_USEREG BIT(21)
+
+#define BIT_SHIFT_RETRY_USEREG 19
+#define BIT_MASK_RETRY_USEREG 0x3
+#define BIT_RETRY_USEREG(x)                                                    \
+	(((x) & BIT_MASK_RETRY_USEREG) << BIT_SHIFT_RETRY_USEREG)
+#define BITS_RETRY_USEREG (BIT_MASK_RETRY_USEREG << BIT_SHIFT_RETRY_USEREG)
+#define BIT_CLEAR_RETRY_USEREG(x) ((x) & (~BITS_RETRY_USEREG))
+#define BIT_GET_RETRY_USEREG(x)                                                \
+	(((x) >> BIT_SHIFT_RETRY_USEREG) & BIT_MASK_RETRY_USEREG)
+#define BIT_SET_RETRY_USEREG(x, v)                                             \
+	(BIT_CLEAR_RETRY_USEREG(x) | BIT_RETRY_USEREG(v))
+
+#define BIT_SHIFT_TRYPKT_USEREG 17
+#define BIT_MASK_TRYPKT_USEREG 0x3
+#define BIT_TRYPKT_USEREG(x)                                                   \
+	(((x) & BIT_MASK_TRYPKT_USEREG) << BIT_SHIFT_TRYPKT_USEREG)
+#define BITS_TRYPKT_USEREG (BIT_MASK_TRYPKT_USEREG << BIT_SHIFT_TRYPKT_USEREG)
+#define BIT_CLEAR_TRYPKT_USEREG(x) ((x) & (~BITS_TRYPKT_USEREG))
+#define BIT_GET_TRYPKT_USEREG(x)                                               \
+	(((x) >> BIT_SHIFT_TRYPKT_USEREG) & BIT_MASK_TRYPKT_USEREG)
+#define BIT_SET_TRYPKT_USEREG(x, v)                                            \
+	(BIT_CLEAR_TRYPKT_USEREG(x) | BIT_TRYPKT_USEREG(v))
+
+#define BIT_CTLPKT_USEREG BIT(16)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_AESIV_SETTING			(Offset 0x1424) */
+
+#define BIT_SHIFT_AESIV_OFFSET 0
+#define BIT_MASK_AESIV_OFFSET 0xfff
+#define BIT_AESIV_OFFSET(x)                                                    \
+	(((x) & BIT_MASK_AESIV_OFFSET) << BIT_SHIFT_AESIV_OFFSET)
+#define BITS_AESIV_OFFSET (BIT_MASK_AESIV_OFFSET << BIT_SHIFT_AESIV_OFFSET)
+#define BIT_CLEAR_AESIV_OFFSET(x) ((x) & (~BITS_AESIV_OFFSET))
+#define BIT_GET_AESIV_OFFSET(x)                                                \
+	(((x) >> BIT_SHIFT_AESIV_OFFSET) & BIT_MASK_AESIV_OFFSET)
+#define BIT_SET_AESIV_OFFSET(x, v)                                             \
+	(BIT_CLEAR_AESIV_OFFSET(x) | BIT_AESIV_OFFSET(v))
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_BF0_TIME_SETTING			(Offset 0x1428) */
+
+#define BIT_BF0_TIMER_SET BIT(31)
+#define BIT_BF0_TIMER_CLR BIT(30)
+#define BIT_BF0_UPDATE_EN BIT(29)
+#define BIT_BF0_TIMER_EN BIT(28)
+
+#define BIT_SHIFT_BF0_PRETIME_OVER 16
+#define BIT_MASK_BF0_PRETIME_OVER 0xfff
+#define BIT_BF0_PRETIME_OVER(x)                                                \
+	(((x) & BIT_MASK_BF0_PRETIME_OVER) << BIT_SHIFT_BF0_PRETIME_OVER)
+#define BITS_BF0_PRETIME_OVER                                                  \
+	(BIT_MASK_BF0_PRETIME_OVER << BIT_SHIFT_BF0_PRETIME_OVER)
+#define BIT_CLEAR_BF0_PRETIME_OVER(x) ((x) & (~BITS_BF0_PRETIME_OVER))
+#define BIT_GET_BF0_PRETIME_OVER(x)                                            \
+	(((x) >> BIT_SHIFT_BF0_PRETIME_OVER) & BIT_MASK_BF0_PRETIME_OVER)
+#define BIT_SET_BF0_PRETIME_OVER(x, v)                                         \
+	(BIT_CLEAR_BF0_PRETIME_OVER(x) | BIT_BF0_PRETIME_OVER(v))
+
+#define BIT_SHIFT_BF0_LIFETIME 0
+#define BIT_MASK_BF0_LIFETIME 0xffff
+#define BIT_BF0_LIFETIME(x)                                                    \
+	(((x) & BIT_MASK_BF0_LIFETIME) << BIT_SHIFT_BF0_LIFETIME)
+#define BITS_BF0_LIFETIME (BIT_MASK_BF0_LIFETIME << BIT_SHIFT_BF0_LIFETIME)
+#define BIT_CLEAR_BF0_LIFETIME(x) ((x) & (~BITS_BF0_LIFETIME))
+#define BIT_GET_BF0_LIFETIME(x)                                                \
+	(((x) >> BIT_SHIFT_BF0_LIFETIME) & BIT_MASK_BF0_LIFETIME)
+#define BIT_SET_BF0_LIFETIME(x, v)                                             \
+	(BIT_CLEAR_BF0_LIFETIME(x) | BIT_BF0_LIFETIME(v))
+
+/* 2 REG_BF1_TIME_SETTING			(Offset 0x142C) */
+
+#define BIT_BF1_TIMER_SET BIT(31)
+#define BIT_BF1_TIMER_CLR BIT(30)
+#define BIT_BF1_UPDATE_EN BIT(29)
+#define BIT_BF1_TIMER_EN BIT(28)
+
+#define BIT_SHIFT_BF1_PRETIME_OVER 16
+#define BIT_MASK_BF1_PRETIME_OVER 0xfff
+#define BIT_BF1_PRETIME_OVER(x)                                                \
+	(((x) & BIT_MASK_BF1_PRETIME_OVER) << BIT_SHIFT_BF1_PRETIME_OVER)
+#define BITS_BF1_PRETIME_OVER                                                  \
+	(BIT_MASK_BF1_PRETIME_OVER << BIT_SHIFT_BF1_PRETIME_OVER)
+#define BIT_CLEAR_BF1_PRETIME_OVER(x) ((x) & (~BITS_BF1_PRETIME_OVER))
+#define BIT_GET_BF1_PRETIME_OVER(x)                                            \
+	(((x) >> BIT_SHIFT_BF1_PRETIME_OVER) & BIT_MASK_BF1_PRETIME_OVER)
+#define BIT_SET_BF1_PRETIME_OVER(x, v)                                         \
+	(BIT_CLEAR_BF1_PRETIME_OVER(x) | BIT_BF1_PRETIME_OVER(v))
+
+#define BIT_SHIFT_BF1_LIFETIME 0
+#define BIT_MASK_BF1_LIFETIME 0xffff
+#define BIT_BF1_LIFETIME(x)                                                    \
+	(((x) & BIT_MASK_BF1_LIFETIME) << BIT_SHIFT_BF1_LIFETIME)
+#define BITS_BF1_LIFETIME (BIT_MASK_BF1_LIFETIME << BIT_SHIFT_BF1_LIFETIME)
+#define BIT_CLEAR_BF1_LIFETIME(x) ((x) & (~BITS_BF1_LIFETIME))
+#define BIT_GET_BF1_LIFETIME(x)                                                \
+	(((x) >> BIT_SHIFT_BF1_LIFETIME) & BIT_MASK_BF1_LIFETIME)
+#define BIT_SET_BF1_LIFETIME(x, v)                                             \
+	(BIT_CLEAR_BF1_LIFETIME(x) | BIT_BF1_LIFETIME(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_BF_TIMEOUT_EN			(Offset 0x1430) */
+
+#define BIT_EN_VHT_LDPC BIT(9)
+#define BIT_EN_HT_LDPC BIT(8)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_BF_TIMEOUT_EN			(Offset 0x1430) */
+
+#define BIT_BF1_TIMEOUT_EN BIT(1)
+#define BIT_BF0_TIMEOUT_EN BIT(0)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_MACID_RELEASE0			(Offset 0x1434) */
+
+#define BIT_SHIFT_MACID31_0_RELEASE 0
+#define BIT_MASK_MACID31_0_RELEASE 0xffffffffL
+#define BIT_MACID31_0_RELEASE(x)                                               \
+	(((x) & BIT_MASK_MACID31_0_RELEASE) << BIT_SHIFT_MACID31_0_RELEASE)
+#define BITS_MACID31_0_RELEASE                                                 \
+	(BIT_MASK_MACID31_0_RELEASE << BIT_SHIFT_MACID31_0_RELEASE)
+#define BIT_CLEAR_MACID31_0_RELEASE(x) ((x) & (~BITS_MACID31_0_RELEASE))
+#define BIT_GET_MACID31_0_RELEASE(x)                                           \
+	(((x) >> BIT_SHIFT_MACID31_0_RELEASE) & BIT_MASK_MACID31_0_RELEASE)
+#define BIT_SET_MACID31_0_RELEASE(x, v)                                        \
+	(BIT_CLEAR_MACID31_0_RELEASE(x) | BIT_MACID31_0_RELEASE(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_MACID_RELEASE_INFO			(Offset 0x1434) */
+
+#define BIT_SHIFT_MACID_RELEASE_INFO 0
+#define BIT_MASK_MACID_RELEASE_INFO 0xffffffffL
+#define BIT_MACID_RELEASE_INFO(x)                                              \
+	(((x) & BIT_MASK_MACID_RELEASE_INFO) << BIT_SHIFT_MACID_RELEASE_INFO)
+#define BITS_MACID_RELEASE_INFO                                                \
+	(BIT_MASK_MACID_RELEASE_INFO << BIT_SHIFT_MACID_RELEASE_INFO)
+#define BIT_CLEAR_MACID_RELEASE_INFO(x) ((x) & (~BITS_MACID_RELEASE_INFO))
+#define BIT_GET_MACID_RELEASE_INFO(x)                                          \
+	(((x) >> BIT_SHIFT_MACID_RELEASE_INFO) & BIT_MASK_MACID_RELEASE_INFO)
+#define BIT_SET_MACID_RELEASE_INFO(x, v)                                       \
+	(BIT_CLEAR_MACID_RELEASE_INFO(x) | BIT_MACID_RELEASE_INFO(v))
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_MACID_RELEASE1			(Offset 0x1438) */
+
+#define BIT_SHIFT_MACID63_32_RELEASE 0
+#define BIT_MASK_MACID63_32_RELEASE 0xffffffffL
+#define BIT_MACID63_32_RELEASE(x)                                              \
+	(((x) & BIT_MASK_MACID63_32_RELEASE) << BIT_SHIFT_MACID63_32_RELEASE)
+#define BITS_MACID63_32_RELEASE                                                \
+	(BIT_MASK_MACID63_32_RELEASE << BIT_SHIFT_MACID63_32_RELEASE)
+#define BIT_CLEAR_MACID63_32_RELEASE(x) ((x) & (~BITS_MACID63_32_RELEASE))
+#define BIT_GET_MACID63_32_RELEASE(x)                                          \
+	(((x) >> BIT_SHIFT_MACID63_32_RELEASE) & BIT_MASK_MACID63_32_RELEASE)
+#define BIT_SET_MACID63_32_RELEASE(x, v)                                       \
+	(BIT_CLEAR_MACID63_32_RELEASE(x) | BIT_MACID63_32_RELEASE(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_MACID_RELEASE_SUCCESS_INFO		(Offset 0x1438) */
+
+#define BIT_SHIFT_MACID_RELEASE_SUCCESS_INFO 0
+#define BIT_MASK_MACID_RELEASE_SUCCESS_INFO 0xffffffffL
+#define BIT_MACID_RELEASE_SUCCESS_INFO(x)                                      \
+	(((x) & BIT_MASK_MACID_RELEASE_SUCCESS_INFO)                           \
+	 << BIT_SHIFT_MACID_RELEASE_SUCCESS_INFO)
+#define BITS_MACID_RELEASE_SUCCESS_INFO                                        \
+	(BIT_MASK_MACID_RELEASE_SUCCESS_INFO                                   \
+	 << BIT_SHIFT_MACID_RELEASE_SUCCESS_INFO)
+#define BIT_CLEAR_MACID_RELEASE_SUCCESS_INFO(x)                                \
+	((x) & (~BITS_MACID_RELEASE_SUCCESS_INFO))
+#define BIT_GET_MACID_RELEASE_SUCCESS_INFO(x)                                  \
+	(((x) >> BIT_SHIFT_MACID_RELEASE_SUCCESS_INFO) &                       \
+	 BIT_MASK_MACID_RELEASE_SUCCESS_INFO)
+#define BIT_SET_MACID_RELEASE_SUCCESS_INFO(x, v)                               \
+	(BIT_CLEAR_MACID_RELEASE_SUCCESS_INFO(x) |                             \
+	 BIT_MACID_RELEASE_SUCCESS_INFO(v))
+
+/* 2 REG_MACID_RELEASE_CTRL			(Offset 0x143C) */
+
+#define BIT_SHIFT_MACID_RELEASE_SEL 24
+#define BIT_MASK_MACID_RELEASE_SEL 0x7
+#define BIT_MACID_RELEASE_SEL(x)                                               \
+	(((x) & BIT_MASK_MACID_RELEASE_SEL) << BIT_SHIFT_MACID_RELEASE_SEL)
+#define BITS_MACID_RELEASE_SEL                                                 \
+	(BIT_MASK_MACID_RELEASE_SEL << BIT_SHIFT_MACID_RELEASE_SEL)
+#define BIT_CLEAR_MACID_RELEASE_SEL(x) ((x) & (~BITS_MACID_RELEASE_SEL))
+#define BIT_GET_MACID_RELEASE_SEL(x)                                           \
+	(((x) >> BIT_SHIFT_MACID_RELEASE_SEL) & BIT_MASK_MACID_RELEASE_SEL)
+#define BIT_SET_MACID_RELEASE_SEL(x, v)                                        \
+	(BIT_CLEAR_MACID_RELEASE_SEL(x) | BIT_MACID_RELEASE_SEL(v))
+
+#define BIT_SHIFT_MACID_RELEASE_CLEAR_OFFSET 16
+#define BIT_MASK_MACID_RELEASE_CLEAR_OFFSET 0xff
+#define BIT_MACID_RELEASE_CLEAR_OFFSET(x)                                      \
+	(((x) & BIT_MASK_MACID_RELEASE_CLEAR_OFFSET)                           \
+	 << BIT_SHIFT_MACID_RELEASE_CLEAR_OFFSET)
+#define BITS_MACID_RELEASE_CLEAR_OFFSET                                        \
+	(BIT_MASK_MACID_RELEASE_CLEAR_OFFSET                                   \
+	 << BIT_SHIFT_MACID_RELEASE_CLEAR_OFFSET)
+#define BIT_CLEAR_MACID_RELEASE_CLEAR_OFFSET(x)                                \
+	((x) & (~BITS_MACID_RELEASE_CLEAR_OFFSET))
+#define BIT_GET_MACID_RELEASE_CLEAR_OFFSET(x)                                  \
+	(((x) >> BIT_SHIFT_MACID_RELEASE_CLEAR_OFFSET) &                       \
+	 BIT_MASK_MACID_RELEASE_CLEAR_OFFSET)
+#define BIT_SET_MACID_RELEASE_CLEAR_OFFSET(x, v)                               \
+	(BIT_CLEAR_MACID_RELEASE_CLEAR_OFFSET(x) |                             \
+	 BIT_MACID_RELEASE_CLEAR_OFFSET(v))
+
+#define BIT_MACID_RELEASE_VALUE BIT(8)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_MACID_RELEASE2			(Offset 0x143C) */
+
+#define BIT_SHIFT_MACID95_64_RELEASE 0
+#define BIT_MASK_MACID95_64_RELEASE 0xffffffffL
+#define BIT_MACID95_64_RELEASE(x)                                              \
+	(((x) & BIT_MASK_MACID95_64_RELEASE) << BIT_SHIFT_MACID95_64_RELEASE)
+#define BITS_MACID95_64_RELEASE                                                \
+	(BIT_MASK_MACID95_64_RELEASE << BIT_SHIFT_MACID95_64_RELEASE)
+#define BIT_CLEAR_MACID95_64_RELEASE(x) ((x) & (~BITS_MACID95_64_RELEASE))
+#define BIT_GET_MACID95_64_RELEASE(x)                                          \
+	(((x) >> BIT_SHIFT_MACID95_64_RELEASE) & BIT_MASK_MACID95_64_RELEASE)
+#define BIT_SET_MACID95_64_RELEASE(x, v)                                       \
+	(BIT_CLEAR_MACID95_64_RELEASE(x) | BIT_MACID95_64_RELEASE(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_MACID_RELEASE_CTRL			(Offset 0x143C) */
+
+#define BIT_SHIFT_MACID_RELEASE_OFFSET 0
+#define BIT_MASK_MACID_RELEASE_OFFSET 0xff
+#define BIT_MACID_RELEASE_OFFSET(x)                                            \
+	(((x) & BIT_MASK_MACID_RELEASE_OFFSET)                                 \
+	 << BIT_SHIFT_MACID_RELEASE_OFFSET)
+#define BITS_MACID_RELEASE_OFFSET                                              \
+	(BIT_MASK_MACID_RELEASE_OFFSET << BIT_SHIFT_MACID_RELEASE_OFFSET)
+#define BIT_CLEAR_MACID_RELEASE_OFFSET(x) ((x) & (~BITS_MACID_RELEASE_OFFSET))
+#define BIT_GET_MACID_RELEASE_OFFSET(x)                                        \
+	(((x) >> BIT_SHIFT_MACID_RELEASE_OFFSET) &                             \
+	 BIT_MASK_MACID_RELEASE_OFFSET)
+#define BIT_SET_MACID_RELEASE_OFFSET(x, v)                                     \
+	(BIT_CLEAR_MACID_RELEASE_OFFSET(x) | BIT_MACID_RELEASE_OFFSET(v))
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_MACID_RELEASE3			(Offset 0x1440) */
+
+#define BIT_SHIFT_MACID127_96_RELEASE 0
+#define BIT_MASK_MACID127_96_RELEASE 0xffffffffL
+#define BIT_MACID127_96_RELEASE(x)                                             \
+	(((x) & BIT_MASK_MACID127_96_RELEASE) << BIT_SHIFT_MACID127_96_RELEASE)
+#define BITS_MACID127_96_RELEASE                                               \
+	(BIT_MASK_MACID127_96_RELEASE << BIT_SHIFT_MACID127_96_RELEASE)
+#define BIT_CLEAR_MACID127_96_RELEASE(x) ((x) & (~BITS_MACID127_96_RELEASE))
+#define BIT_GET_MACID127_96_RELEASE(x)                                         \
+	(((x) >> BIT_SHIFT_MACID127_96_RELEASE) & BIT_MASK_MACID127_96_RELEASE)
+#define BIT_SET_MACID127_96_RELEASE(x, v)                                      \
+	(BIT_CLEAR_MACID127_96_RELEASE(x) | BIT_MACID127_96_RELEASE(v))
+
+/* 2 REG_MACID_RELEASE_SETTING		(Offset 0x1444) */
+
+#define BIT_MACID_VALUE BIT(7)
+
+#define BIT_SHIFT_MACID_OFFSET 0
+#define BIT_MASK_MACID_OFFSET 0x7f
+#define BIT_MACID_OFFSET(x)                                                    \
+	(((x) & BIT_MASK_MACID_OFFSET) << BIT_SHIFT_MACID_OFFSET)
+#define BITS_MACID_OFFSET (BIT_MASK_MACID_OFFSET << BIT_SHIFT_MACID_OFFSET)
+#define BIT_CLEAR_MACID_OFFSET(x) ((x) & (~BITS_MACID_OFFSET))
+#define BIT_GET_MACID_OFFSET(x)                                                \
+	(((x) >> BIT_SHIFT_MACID_OFFSET) & BIT_MASK_MACID_OFFSET)
+#define BIT_SET_MACID_OFFSET(x, v)                                             \
+	(BIT_CLEAR_MACID_OFFSET(x) | BIT_MACID_OFFSET(v))
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FAST_EDCA_VOVI_SETTING		(Offset 0x1448) */
+
+#define BIT_SHIFT_VI_FAST_EDCA_TO 24
+#define BIT_MASK_VI_FAST_EDCA_TO 0xff
+#define BIT_VI_FAST_EDCA_TO(x)                                                 \
+	(((x) & BIT_MASK_VI_FAST_EDCA_TO) << BIT_SHIFT_VI_FAST_EDCA_TO)
+#define BITS_VI_FAST_EDCA_TO                                                   \
+	(BIT_MASK_VI_FAST_EDCA_TO << BIT_SHIFT_VI_FAST_EDCA_TO)
+#define BIT_CLEAR_VI_FAST_EDCA_TO(x) ((x) & (~BITS_VI_FAST_EDCA_TO))
+#define BIT_GET_VI_FAST_EDCA_TO(x)                                             \
+	(((x) >> BIT_SHIFT_VI_FAST_EDCA_TO) & BIT_MASK_VI_FAST_EDCA_TO)
+#define BIT_SET_VI_FAST_EDCA_TO(x, v)                                          \
+	(BIT_CLEAR_VI_FAST_EDCA_TO(x) | BIT_VI_FAST_EDCA_TO(v))
+
+#define BIT_VI_THRESHOLD_SEL BIT(23)
+
+#define BIT_SHIFT_VI_FAST_EDCA_PKT_TH 16
+#define BIT_MASK_VI_FAST_EDCA_PKT_TH 0x7f
+#define BIT_VI_FAST_EDCA_PKT_TH(x)                                             \
+	(((x) & BIT_MASK_VI_FAST_EDCA_PKT_TH) << BIT_SHIFT_VI_FAST_EDCA_PKT_TH)
+#define BITS_VI_FAST_EDCA_PKT_TH                                               \
+	(BIT_MASK_VI_FAST_EDCA_PKT_TH << BIT_SHIFT_VI_FAST_EDCA_PKT_TH)
+#define BIT_CLEAR_VI_FAST_EDCA_PKT_TH(x) ((x) & (~BITS_VI_FAST_EDCA_PKT_TH))
+#define BIT_GET_VI_FAST_EDCA_PKT_TH(x)                                         \
+	(((x) >> BIT_SHIFT_VI_FAST_EDCA_PKT_TH) & BIT_MASK_VI_FAST_EDCA_PKT_TH)
+#define BIT_SET_VI_FAST_EDCA_PKT_TH(x, v)                                      \
+	(BIT_CLEAR_VI_FAST_EDCA_PKT_TH(x) | BIT_VI_FAST_EDCA_PKT_TH(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FAST_EDCA_VOVI_SETTING		(Offset 0x1448) */
+
+#define BIT_SHIFT_VO_FAST_EDCA_TO 8
+#define BIT_MASK_VO_FAST_EDCA_TO 0xff
+#define BIT_VO_FAST_EDCA_TO(x)                                                 \
+	(((x) & BIT_MASK_VO_FAST_EDCA_TO) << BIT_SHIFT_VO_FAST_EDCA_TO)
+#define BITS_VO_FAST_EDCA_TO                                                   \
+	(BIT_MASK_VO_FAST_EDCA_TO << BIT_SHIFT_VO_FAST_EDCA_TO)
+#define BIT_CLEAR_VO_FAST_EDCA_TO(x) ((x) & (~BITS_VO_FAST_EDCA_TO))
+#define BIT_GET_VO_FAST_EDCA_TO(x)                                             \
+	(((x) >> BIT_SHIFT_VO_FAST_EDCA_TO) & BIT_MASK_VO_FAST_EDCA_TO)
+#define BIT_SET_VO_FAST_EDCA_TO(x, v)                                          \
+	(BIT_CLEAR_VO_FAST_EDCA_TO(x) | BIT_VO_FAST_EDCA_TO(v))
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FAST_EDCA_VOVI_SETTING		(Offset 0x1448) */
+
+#define BIT_VO_THRESHOLD_SEL BIT(7)
+
+#define BIT_SHIFT_VO_FAST_EDCA_PKT_TH 0
+#define BIT_MASK_VO_FAST_EDCA_PKT_TH 0x7f
+#define BIT_VO_FAST_EDCA_PKT_TH(x)                                             \
+	(((x) & BIT_MASK_VO_FAST_EDCA_PKT_TH) << BIT_SHIFT_VO_FAST_EDCA_PKT_TH)
+#define BITS_VO_FAST_EDCA_PKT_TH                                               \
+	(BIT_MASK_VO_FAST_EDCA_PKT_TH << BIT_SHIFT_VO_FAST_EDCA_PKT_TH)
+#define BIT_CLEAR_VO_FAST_EDCA_PKT_TH(x) ((x) & (~BITS_VO_FAST_EDCA_PKT_TH))
+#define BIT_GET_VO_FAST_EDCA_PKT_TH(x)                                         \
+	(((x) >> BIT_SHIFT_VO_FAST_EDCA_PKT_TH) & BIT_MASK_VO_FAST_EDCA_PKT_TH)
+#define BIT_SET_VO_FAST_EDCA_PKT_TH(x, v)                                      \
+	(BIT_CLEAR_VO_FAST_EDCA_PKT_TH(x) | BIT_VO_FAST_EDCA_PKT_TH(v))
+
+/* 2 REG_FAST_EDCA_BEBK_SETTING		(Offset 0x144C) */
+
+#define BIT_SHIFT_BK_FAST_EDCA_TO 24
+#define BIT_MASK_BK_FAST_EDCA_TO 0xff
+#define BIT_BK_FAST_EDCA_TO(x)                                                 \
+	(((x) & BIT_MASK_BK_FAST_EDCA_TO) << BIT_SHIFT_BK_FAST_EDCA_TO)
+#define BITS_BK_FAST_EDCA_TO                                                   \
+	(BIT_MASK_BK_FAST_EDCA_TO << BIT_SHIFT_BK_FAST_EDCA_TO)
+#define BIT_CLEAR_BK_FAST_EDCA_TO(x) ((x) & (~BITS_BK_FAST_EDCA_TO))
+#define BIT_GET_BK_FAST_EDCA_TO(x)                                             \
+	(((x) >> BIT_SHIFT_BK_FAST_EDCA_TO) & BIT_MASK_BK_FAST_EDCA_TO)
+#define BIT_SET_BK_FAST_EDCA_TO(x, v)                                          \
+	(BIT_CLEAR_BK_FAST_EDCA_TO(x) | BIT_BK_FAST_EDCA_TO(v))
+
+#define BIT_BK_THRESHOLD_SEL BIT(23)
+
+#define BIT_SHIFT_BK_FAST_EDCA_PKT_TH 16
+#define BIT_MASK_BK_FAST_EDCA_PKT_TH 0x7f
+#define BIT_BK_FAST_EDCA_PKT_TH(x)                                             \
+	(((x) & BIT_MASK_BK_FAST_EDCA_PKT_TH) << BIT_SHIFT_BK_FAST_EDCA_PKT_TH)
+#define BITS_BK_FAST_EDCA_PKT_TH                                               \
+	(BIT_MASK_BK_FAST_EDCA_PKT_TH << BIT_SHIFT_BK_FAST_EDCA_PKT_TH)
+#define BIT_CLEAR_BK_FAST_EDCA_PKT_TH(x) ((x) & (~BITS_BK_FAST_EDCA_PKT_TH))
+#define BIT_GET_BK_FAST_EDCA_PKT_TH(x)                                         \
+	(((x) >> BIT_SHIFT_BK_FAST_EDCA_PKT_TH) & BIT_MASK_BK_FAST_EDCA_PKT_TH)
+#define BIT_SET_BK_FAST_EDCA_PKT_TH(x, v)                                      \
+	(BIT_CLEAR_BK_FAST_EDCA_PKT_TH(x) | BIT_BK_FAST_EDCA_PKT_TH(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FAST_EDCA_BEBK_SETTING		(Offset 0x144C) */
+
+#define BIT_SHIFT_BE_FAST_EDCA_TO 8
+#define BIT_MASK_BE_FAST_EDCA_TO 0xff
+#define BIT_BE_FAST_EDCA_TO(x)                                                 \
+	(((x) & BIT_MASK_BE_FAST_EDCA_TO) << BIT_SHIFT_BE_FAST_EDCA_TO)
+#define BITS_BE_FAST_EDCA_TO                                                   \
+	(BIT_MASK_BE_FAST_EDCA_TO << BIT_SHIFT_BE_FAST_EDCA_TO)
+#define BIT_CLEAR_BE_FAST_EDCA_TO(x) ((x) & (~BITS_BE_FAST_EDCA_TO))
+#define BIT_GET_BE_FAST_EDCA_TO(x)                                             \
+	(((x) >> BIT_SHIFT_BE_FAST_EDCA_TO) & BIT_MASK_BE_FAST_EDCA_TO)
+#define BIT_SET_BE_FAST_EDCA_TO(x, v)                                          \
+	(BIT_CLEAR_BE_FAST_EDCA_TO(x) | BIT_BE_FAST_EDCA_TO(v))
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FAST_EDCA_BEBK_SETTING		(Offset 0x144C) */
+
+#define BIT_BE_THRESHOLD_SEL BIT(7)
+
+#define BIT_SHIFT_BE_FAST_EDCA_PKT_TH 0
+#define BIT_MASK_BE_FAST_EDCA_PKT_TH 0x7f
+#define BIT_BE_FAST_EDCA_PKT_TH(x)                                             \
+	(((x) & BIT_MASK_BE_FAST_EDCA_PKT_TH) << BIT_SHIFT_BE_FAST_EDCA_PKT_TH)
+#define BITS_BE_FAST_EDCA_PKT_TH                                               \
+	(BIT_MASK_BE_FAST_EDCA_PKT_TH << BIT_SHIFT_BE_FAST_EDCA_PKT_TH)
+#define BIT_CLEAR_BE_FAST_EDCA_PKT_TH(x) ((x) & (~BITS_BE_FAST_EDCA_PKT_TH))
+#define BIT_GET_BE_FAST_EDCA_PKT_TH(x)                                         \
+	(((x) >> BIT_SHIFT_BE_FAST_EDCA_PKT_TH) & BIT_MASK_BE_FAST_EDCA_PKT_TH)
+#define BIT_SET_BE_FAST_EDCA_PKT_TH(x, v)                                      \
+	(BIT_CLEAR_BE_FAST_EDCA_PKT_TH(x) | BIT_BE_FAST_EDCA_PKT_TH(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_MACID_DROP0				(Offset 0x1450) */
+
+#define BIT_SHIFT_MACID31_0_DROP 0
+#define BIT_MASK_MACID31_0_DROP 0xffffffffL
+#define BIT_MACID31_0_DROP(x)                                                  \
+	(((x) & BIT_MASK_MACID31_0_DROP) << BIT_SHIFT_MACID31_0_DROP)
+#define BITS_MACID31_0_DROP                                                    \
+	(BIT_MASK_MACID31_0_DROP << BIT_SHIFT_MACID31_0_DROP)
+#define BIT_CLEAR_MACID31_0_DROP(x) ((x) & (~BITS_MACID31_0_DROP))
+#define BIT_GET_MACID31_0_DROP(x)                                              \
+	(((x) >> BIT_SHIFT_MACID31_0_DROP) & BIT_MASK_MACID31_0_DROP)
+#define BIT_SET_MACID31_0_DROP(x, v)                                           \
+	(BIT_CLEAR_MACID31_0_DROP(x) | BIT_MACID31_0_DROP(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_MACID_DROP_INFO			(Offset 0x1450) */
+
+#define BIT_SHIFT_MACID_DROP_INFO 0
+#define BIT_MASK_MACID_DROP_INFO 0xffffffffL
+#define BIT_MACID_DROP_INFO(x)                                                 \
+	(((x) & BIT_MASK_MACID_DROP_INFO) << BIT_SHIFT_MACID_DROP_INFO)
+#define BITS_MACID_DROP_INFO                                                   \
+	(BIT_MASK_MACID_DROP_INFO << BIT_SHIFT_MACID_DROP_INFO)
+#define BIT_CLEAR_MACID_DROP_INFO(x) ((x) & (~BITS_MACID_DROP_INFO))
+#define BIT_GET_MACID_DROP_INFO(x)                                             \
+	(((x) >> BIT_SHIFT_MACID_DROP_INFO) & BIT_MASK_MACID_DROP_INFO)
+#define BIT_SET_MACID_DROP_INFO(x, v)                                          \
+	(BIT_CLEAR_MACID_DROP_INFO(x) | BIT_MACID_DROP_INFO(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_MACID_DROP1				(Offset 0x1454) */
+
+#define BIT_SHIFT_MACID63_32_DROP 0
+#define BIT_MASK_MACID63_32_DROP 0xffffffffL
+#define BIT_MACID63_32_DROP(x)                                                 \
+	(((x) & BIT_MASK_MACID63_32_DROP) << BIT_SHIFT_MACID63_32_DROP)
+#define BITS_MACID63_32_DROP                                                   \
+	(BIT_MASK_MACID63_32_DROP << BIT_SHIFT_MACID63_32_DROP)
+#define BIT_CLEAR_MACID63_32_DROP(x) ((x) & (~BITS_MACID63_32_DROP))
+#define BIT_GET_MACID63_32_DROP(x)                                             \
+	(((x) >> BIT_SHIFT_MACID63_32_DROP) & BIT_MASK_MACID63_32_DROP)
+#define BIT_SET_MACID63_32_DROP(x, v)                                          \
+	(BIT_CLEAR_MACID63_32_DROP(x) | BIT_MACID63_32_DROP(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_MACID_DROP_CTRL			(Offset 0x1454) */
+
+#define BIT_SHIFT_MACID_DROP_SEL 0
+#define BIT_MASK_MACID_DROP_SEL 0x7
+#define BIT_MACID_DROP_SEL(x)                                                  \
+	(((x) & BIT_MASK_MACID_DROP_SEL) << BIT_SHIFT_MACID_DROP_SEL)
+#define BITS_MACID_DROP_SEL                                                    \
+	(BIT_MASK_MACID_DROP_SEL << BIT_SHIFT_MACID_DROP_SEL)
+#define BIT_CLEAR_MACID_DROP_SEL(x) ((x) & (~BITS_MACID_DROP_SEL))
+#define BIT_GET_MACID_DROP_SEL(x)                                              \
+	(((x) >> BIT_SHIFT_MACID_DROP_SEL) & BIT_MASK_MACID_DROP_SEL)
+#define BIT_SET_MACID_DROP_SEL(x, v)                                           \
+	(BIT_CLEAR_MACID_DROP_SEL(x) | BIT_MACID_DROP_SEL(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_MACID_DROP2				(Offset 0x1458) */
+
+#define BIT_SHIFT_MACID95_64_DROP 0
+#define BIT_MASK_MACID95_64_DROP 0xffffffffL
+#define BIT_MACID95_64_DROP(x)                                                 \
+	(((x) & BIT_MASK_MACID95_64_DROP) << BIT_SHIFT_MACID95_64_DROP)
+#define BITS_MACID95_64_DROP                                                   \
+	(BIT_MASK_MACID95_64_DROP << BIT_SHIFT_MACID95_64_DROP)
+#define BIT_CLEAR_MACID95_64_DROP(x) ((x) & (~BITS_MACID95_64_DROP))
+#define BIT_GET_MACID95_64_DROP(x)                                             \
+	(((x) >> BIT_SHIFT_MACID95_64_DROP) & BIT_MASK_MACID95_64_DROP)
+#define BIT_SET_MACID95_64_DROP(x, v)                                          \
+	(BIT_CLEAR_MACID95_64_DROP(x) | BIT_MACID95_64_DROP(v))
+
+/* 2 REG_MACID_DROP3				(Offset 0x145C) */
+
+#define BIT_SHIFT_MACID127_96_DROP 0
+#define BIT_MASK_MACID127_96_DROP 0xffffffffL
+#define BIT_MACID127_96_DROP(x)                                                \
+	(((x) & BIT_MASK_MACID127_96_DROP) << BIT_SHIFT_MACID127_96_DROP)
+#define BITS_MACID127_96_DROP                                                  \
+	(BIT_MASK_MACID127_96_DROP << BIT_SHIFT_MACID127_96_DROP)
+#define BIT_CLEAR_MACID127_96_DROP(x) ((x) & (~BITS_MACID127_96_DROP))
+#define BIT_GET_MACID127_96_DROP(x)                                            \
+	(((x) >> BIT_SHIFT_MACID127_96_DROP) & BIT_MASK_MACID127_96_DROP)
+#define BIT_SET_MACID127_96_DROP(x, v)                                         \
+	(BIT_CLEAR_MACID127_96_DROP(x) | BIT_MACID127_96_DROP(v))
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_R_MACID_RELEASE_SUCCESS_1		(Offset 0x1464) */
+
+#define BIT_SHIFT_R_MACID_RELEASE_SUCCESS_1 0
+#define BIT_MASK_R_MACID_RELEASE_SUCCESS_1 0xffffffffL
+#define BIT_R_MACID_RELEASE_SUCCESS_1(x)                                       \
+	(((x) & BIT_MASK_R_MACID_RELEASE_SUCCESS_1)                            \
+	 << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_1)
+#define BITS_R_MACID_RELEASE_SUCCESS_1                                         \
+	(BIT_MASK_R_MACID_RELEASE_SUCCESS_1                                    \
+	 << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_1)
+#define BIT_CLEAR_R_MACID_RELEASE_SUCCESS_1(x)                                 \
+	((x) & (~BITS_R_MACID_RELEASE_SUCCESS_1))
+#define BIT_GET_R_MACID_RELEASE_SUCCESS_1(x)                                   \
+	(((x) >> BIT_SHIFT_R_MACID_RELEASE_SUCCESS_1) &                        \
+	 BIT_MASK_R_MACID_RELEASE_SUCCESS_1)
+#define BIT_SET_R_MACID_RELEASE_SUCCESS_1(x, v)                                \
+	(BIT_CLEAR_R_MACID_RELEASE_SUCCESS_1(x) |                              \
+	 BIT_R_MACID_RELEASE_SUCCESS_1(v))
+
+/* 2 REG_R_MACID_RELEASE_SUCCESS_3		(Offset 0x146C) */
+
+#define BIT_SHIFT_R_MACID_RELEASE_SUCCESS_3 0
+#define BIT_MASK_R_MACID_RELEASE_SUCCESS_3 0xffffffffL
+#define BIT_R_MACID_RELEASE_SUCCESS_3(x)                                       \
+	(((x) & BIT_MASK_R_MACID_RELEASE_SUCCESS_3)                            \
+	 << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_3)
+#define BITS_R_MACID_RELEASE_SUCCESS_3                                         \
+	(BIT_MASK_R_MACID_RELEASE_SUCCESS_3                                    \
+	 << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_3)
+#define BIT_CLEAR_R_MACID_RELEASE_SUCCESS_3(x)                                 \
+	((x) & (~BITS_R_MACID_RELEASE_SUCCESS_3))
+#define BIT_GET_R_MACID_RELEASE_SUCCESS_3(x)                                   \
+	(((x) >> BIT_SHIFT_R_MACID_RELEASE_SUCCESS_3) &                        \
+	 BIT_MASK_R_MACID_RELEASE_SUCCESS_3)
+#define BIT_SET_R_MACID_RELEASE_SUCCESS_3(x, v)                                \
+	(BIT_CLEAR_R_MACID_RELEASE_SUCCESS_3(x) |                              \
+	 BIT_R_MACID_RELEASE_SUCCESS_3(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822B_SUPPORT)
+
+/* 2 REG_MGG_FIFO_CRTL			(Offset 0x1470) */
+
+#define BIT_R_MGG_FIFO_EN BIT(31)
+
+#define BIT_SHIFT_R_MGG_FIFO_PG_SIZE 28
+#define BIT_MASK_R_MGG_FIFO_PG_SIZE 0x7
+#define BIT_R_MGG_FIFO_PG_SIZE(x)                                              \
+	(((x) & BIT_MASK_R_MGG_FIFO_PG_SIZE) << BIT_SHIFT_R_MGG_FIFO_PG_SIZE)
+#define BITS_R_MGG_FIFO_PG_SIZE                                                \
+	(BIT_MASK_R_MGG_FIFO_PG_SIZE << BIT_SHIFT_R_MGG_FIFO_PG_SIZE)
+#define BIT_CLEAR_R_MGG_FIFO_PG_SIZE(x) ((x) & (~BITS_R_MGG_FIFO_PG_SIZE))
+#define BIT_GET_R_MGG_FIFO_PG_SIZE(x)                                          \
+	(((x) >> BIT_SHIFT_R_MGG_FIFO_PG_SIZE) & BIT_MASK_R_MGG_FIFO_PG_SIZE)
+#define BIT_SET_R_MGG_FIFO_PG_SIZE(x, v)                                       \
+	(BIT_CLEAR_R_MGG_FIFO_PG_SIZE(x) | BIT_R_MGG_FIFO_PG_SIZE(v))
+
+#define BIT_SHIFT_R_MGG_FIFO_START_PG 16
+#define BIT_MASK_R_MGG_FIFO_START_PG 0xfff
+#define BIT_R_MGG_FIFO_START_PG(x)                                             \
+	(((x) & BIT_MASK_R_MGG_FIFO_START_PG) << BIT_SHIFT_R_MGG_FIFO_START_PG)
+#define BITS_R_MGG_FIFO_START_PG                                               \
+	(BIT_MASK_R_MGG_FIFO_START_PG << BIT_SHIFT_R_MGG_FIFO_START_PG)
+#define BIT_CLEAR_R_MGG_FIFO_START_PG(x) ((x) & (~BITS_R_MGG_FIFO_START_PG))
+#define BIT_GET_R_MGG_FIFO_START_PG(x)                                         \
+	(((x) >> BIT_SHIFT_R_MGG_FIFO_START_PG) & BIT_MASK_R_MGG_FIFO_START_PG)
+#define BIT_SET_R_MGG_FIFO_START_PG(x, v)                                      \
+	(BIT_CLEAR_R_MGG_FIFO_START_PG(x) | BIT_R_MGG_FIFO_START_PG(v))
+
+#define BIT_SHIFT_R_MGG_FIFO_SIZE 14
+#define BIT_MASK_R_MGG_FIFO_SIZE 0x3
+#define BIT_R_MGG_FIFO_SIZE(x)                                                 \
+	(((x) & BIT_MASK_R_MGG_FIFO_SIZE) << BIT_SHIFT_R_MGG_FIFO_SIZE)
+#define BITS_R_MGG_FIFO_SIZE                                                   \
+	(BIT_MASK_R_MGG_FIFO_SIZE << BIT_SHIFT_R_MGG_FIFO_SIZE)
+#define BIT_CLEAR_R_MGG_FIFO_SIZE(x) ((x) & (~BITS_R_MGG_FIFO_SIZE))
+#define BIT_GET_R_MGG_FIFO_SIZE(x)                                             \
+	(((x) >> BIT_SHIFT_R_MGG_FIFO_SIZE) & BIT_MASK_R_MGG_FIFO_SIZE)
+#define BIT_SET_R_MGG_FIFO_SIZE(x, v)                                          \
+	(BIT_CLEAR_R_MGG_FIFO_SIZE(x) | BIT_R_MGG_FIFO_SIZE(v))
+
+#define BIT_R_MGG_FIFO_PAUSE BIT(13)
+
+#define BIT_SHIFT_R_MGG_FIFO_RPTR 8
+#define BIT_MASK_R_MGG_FIFO_RPTR 0x1f
+#define BIT_R_MGG_FIFO_RPTR(x)                                                 \
+	(((x) & BIT_MASK_R_MGG_FIFO_RPTR) << BIT_SHIFT_R_MGG_FIFO_RPTR)
+#define BITS_R_MGG_FIFO_RPTR                                                   \
+	(BIT_MASK_R_MGG_FIFO_RPTR << BIT_SHIFT_R_MGG_FIFO_RPTR)
+#define BIT_CLEAR_R_MGG_FIFO_RPTR(x) ((x) & (~BITS_R_MGG_FIFO_RPTR))
+#define BIT_GET_R_MGG_FIFO_RPTR(x)                                             \
+	(((x) >> BIT_SHIFT_R_MGG_FIFO_RPTR) & BIT_MASK_R_MGG_FIFO_RPTR)
+#define BIT_SET_R_MGG_FIFO_RPTR(x, v)                                          \
+	(BIT_CLEAR_R_MGG_FIFO_RPTR(x) | BIT_R_MGG_FIFO_RPTR(v))
+
+#define BIT_R_MGG_FIFO_OV BIT(7)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_MGQ_FIFO_WRITE_POINTER		(Offset 0x1470) */
+
+#define BIT_MGQ_FIFO_OV BIT(7)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822B_SUPPORT)
+
+/* 2 REG_MGG_FIFO_CRTL			(Offset 0x1470) */
+
+#define BIT_R_MGG_FIFO_WPTR_ERROR BIT(6)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_MGQ_FIFO_WRITE_POINTER		(Offset 0x1470) */
+
+#define BIT_MGQ_FIFO_WPTR_ERROR BIT(6)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822B_SUPPORT)
+
+/* 2 REG_MGG_FIFO_CRTL			(Offset 0x1470) */
+
+#define BIT_R_EN_CPU_LIFETIME BIT(5)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_MGQ_FIFO_WRITE_POINTER		(Offset 0x1470) */
+
+#define BIT_EN_MGQ_FIFO_LIFETIME BIT(5)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822B_SUPPORT)
+
+/* 2 REG_MGG_FIFO_CRTL			(Offset 0x1470) */
+
+#define BIT_SHIFT_R_MGG_FIFO_WPTR 0
+#define BIT_MASK_R_MGG_FIFO_WPTR 0x1f
+#define BIT_R_MGG_FIFO_WPTR(x)                                                 \
+	(((x) & BIT_MASK_R_MGG_FIFO_WPTR) << BIT_SHIFT_R_MGG_FIFO_WPTR)
+#define BITS_R_MGG_FIFO_WPTR                                                   \
+	(BIT_MASK_R_MGG_FIFO_WPTR << BIT_SHIFT_R_MGG_FIFO_WPTR)
+#define BIT_CLEAR_R_MGG_FIFO_WPTR(x) ((x) & (~BITS_R_MGG_FIFO_WPTR))
+#define BIT_GET_R_MGG_FIFO_WPTR(x)                                             \
+	(((x) >> BIT_SHIFT_R_MGG_FIFO_WPTR) & BIT_MASK_R_MGG_FIFO_WPTR)
+#define BIT_SET_R_MGG_FIFO_WPTR(x, v)                                          \
+	(BIT_CLEAR_R_MGG_FIFO_WPTR(x) | BIT_R_MGG_FIFO_WPTR(v))
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_MGQ_FIFO_WRITE_POINTER		(Offset 0x1470) */
+
+#define BIT_SHIFT_MGQ_FIFO_WPTR 0
+#define BIT_MASK_MGQ_FIFO_WPTR 0x1f
+#define BIT_MGQ_FIFO_WPTR(x)                                                   \
+	(((x) & BIT_MASK_MGQ_FIFO_WPTR) << BIT_SHIFT_MGQ_FIFO_WPTR)
+#define BITS_MGQ_FIFO_WPTR (BIT_MASK_MGQ_FIFO_WPTR << BIT_SHIFT_MGQ_FIFO_WPTR)
+#define BIT_CLEAR_MGQ_FIFO_WPTR(x) ((x) & (~BITS_MGQ_FIFO_WPTR))
+#define BIT_GET_MGQ_FIFO_WPTR(x)                                               \
+	(((x) >> BIT_SHIFT_MGQ_FIFO_WPTR) & BIT_MASK_MGQ_FIFO_WPTR)
+#define BIT_SET_MGQ_FIFO_WPTR(x, v)                                            \
+	(BIT_CLEAR_MGQ_FIFO_WPTR(x) | BIT_MGQ_FIFO_WPTR(v))
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_MGQ_FIFO_ENABLE			(Offset 0x1472) */
+
+#define BIT_MGQ_FIFO_EN BIT(15)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_MGQ_FIFO_ENABLE			(Offset 0x1472) */
+
+#define BIT_MGQ_FIFO_EN_V1 BIT(15)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_MGQ_FIFO_READ_POINTER		(Offset 0x1472) */
+
+#define BIT_SHIFT_MGQ_FIFO_SIZE 14
+#define BIT_MASK_MGQ_FIFO_SIZE 0x3
+#define BIT_MGQ_FIFO_SIZE(x)                                                   \
+	(((x) & BIT_MASK_MGQ_FIFO_SIZE) << BIT_SHIFT_MGQ_FIFO_SIZE)
+#define BITS_MGQ_FIFO_SIZE (BIT_MASK_MGQ_FIFO_SIZE << BIT_SHIFT_MGQ_FIFO_SIZE)
+#define BIT_CLEAR_MGQ_FIFO_SIZE(x) ((x) & (~BITS_MGQ_FIFO_SIZE))
+#define BIT_GET_MGQ_FIFO_SIZE(x)                                               \
+	(((x) >> BIT_SHIFT_MGQ_FIFO_SIZE) & BIT_MASK_MGQ_FIFO_SIZE)
+#define BIT_SET_MGQ_FIFO_SIZE(x, v)                                            \
+	(BIT_CLEAR_MGQ_FIFO_SIZE(x) | BIT_MGQ_FIFO_SIZE(v))
+
+#define BIT_MGQ_FIFO_PAUSE BIT(13)
+
+#define BIT_SHIFT_MGQ_FIFO_PG_SIZE 12
+#define BIT_MASK_MGQ_FIFO_PG_SIZE 0x7
+#define BIT_MGQ_FIFO_PG_SIZE(x)                                                \
+	(((x) & BIT_MASK_MGQ_FIFO_PG_SIZE) << BIT_SHIFT_MGQ_FIFO_PG_SIZE)
+#define BITS_MGQ_FIFO_PG_SIZE                                                  \
+	(BIT_MASK_MGQ_FIFO_PG_SIZE << BIT_SHIFT_MGQ_FIFO_PG_SIZE)
+#define BIT_CLEAR_MGQ_FIFO_PG_SIZE(x) ((x) & (~BITS_MGQ_FIFO_PG_SIZE))
+#define BIT_GET_MGQ_FIFO_PG_SIZE(x)                                            \
+	(((x) >> BIT_SHIFT_MGQ_FIFO_PG_SIZE) & BIT_MASK_MGQ_FIFO_PG_SIZE)
+#define BIT_SET_MGQ_FIFO_PG_SIZE(x, v)                                         \
+	(BIT_CLEAR_MGQ_FIFO_PG_SIZE(x) | BIT_MGQ_FIFO_PG_SIZE(v))
+
+#define BIT_SHIFT_MGQ_FIFO_RPTR 8
+#define BIT_MASK_MGQ_FIFO_RPTR 0x1f
+#define BIT_MGQ_FIFO_RPTR(x)                                                   \
+	(((x) & BIT_MASK_MGQ_FIFO_RPTR) << BIT_SHIFT_MGQ_FIFO_RPTR)
+#define BITS_MGQ_FIFO_RPTR (BIT_MASK_MGQ_FIFO_RPTR << BIT_SHIFT_MGQ_FIFO_RPTR)
+#define BIT_CLEAR_MGQ_FIFO_RPTR(x) ((x) & (~BITS_MGQ_FIFO_RPTR))
+#define BIT_GET_MGQ_FIFO_RPTR(x)                                               \
+	(((x) >> BIT_SHIFT_MGQ_FIFO_RPTR) & BIT_MASK_MGQ_FIFO_RPTR)
+#define BIT_SET_MGQ_FIFO_RPTR(x, v)                                            \
+	(BIT_CLEAR_MGQ_FIFO_RPTR(x) | BIT_MGQ_FIFO_RPTR(v))
+
+#define BIT_SHIFT_MGQ_FIFO_START_PG 0
+#define BIT_MASK_MGQ_FIFO_START_PG 0xfff
+#define BIT_MGQ_FIFO_START_PG(x)                                               \
+	(((x) & BIT_MASK_MGQ_FIFO_START_PG) << BIT_SHIFT_MGQ_FIFO_START_PG)
+#define BITS_MGQ_FIFO_START_PG                                                 \
+	(BIT_MASK_MGQ_FIFO_START_PG << BIT_SHIFT_MGQ_FIFO_START_PG)
+#define BIT_CLEAR_MGQ_FIFO_START_PG(x) ((x) & (~BITS_MGQ_FIFO_START_PG))
+#define BIT_GET_MGQ_FIFO_START_PG(x)                                           \
+	(((x) >> BIT_SHIFT_MGQ_FIFO_START_PG) & BIT_MASK_MGQ_FIFO_START_PG)
+#define BIT_SET_MGQ_FIFO_START_PG(x, v)                                        \
+	(BIT_CLEAR_MGQ_FIFO_START_PG(x) | BIT_MGQ_FIFO_START_PG(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822B_SUPPORT)
+
+/* 2 REG_MGG_FIFO_INT			(Offset 0x1474) */
+
+#define BIT_SHIFT_R_MGG_FIFO_INT_FLAG 16
+#define BIT_MASK_R_MGG_FIFO_INT_FLAG 0xffff
+#define BIT_R_MGG_FIFO_INT_FLAG(x)                                             \
+	(((x) & BIT_MASK_R_MGG_FIFO_INT_FLAG) << BIT_SHIFT_R_MGG_FIFO_INT_FLAG)
+#define BITS_R_MGG_FIFO_INT_FLAG                                               \
+	(BIT_MASK_R_MGG_FIFO_INT_FLAG << BIT_SHIFT_R_MGG_FIFO_INT_FLAG)
+#define BIT_CLEAR_R_MGG_FIFO_INT_FLAG(x) ((x) & (~BITS_R_MGG_FIFO_INT_FLAG))
+#define BIT_GET_R_MGG_FIFO_INT_FLAG(x)                                         \
+	(((x) >> BIT_SHIFT_R_MGG_FIFO_INT_FLAG) & BIT_MASK_R_MGG_FIFO_INT_FLAG)
+#define BIT_SET_R_MGG_FIFO_INT_FLAG(x, v)                                      \
+	(BIT_CLEAR_R_MGG_FIFO_INT_FLAG(x) | BIT_R_MGG_FIFO_INT_FLAG(v))
+
+#define BIT_SHIFT_R_MGG_FIFO_INT_MASK 0
+#define BIT_MASK_R_MGG_FIFO_INT_MASK 0xffff
+#define BIT_R_MGG_FIFO_INT_MASK(x)                                             \
+	(((x) & BIT_MASK_R_MGG_FIFO_INT_MASK) << BIT_SHIFT_R_MGG_FIFO_INT_MASK)
+#define BITS_R_MGG_FIFO_INT_MASK                                               \
+	(BIT_MASK_R_MGG_FIFO_INT_MASK << BIT_SHIFT_R_MGG_FIFO_INT_MASK)
+#define BIT_CLEAR_R_MGG_FIFO_INT_MASK(x) ((x) & (~BITS_R_MGG_FIFO_INT_MASK))
+#define BIT_GET_R_MGG_FIFO_INT_MASK(x)                                         \
+	(((x) >> BIT_SHIFT_R_MGG_FIFO_INT_MASK) & BIT_MASK_R_MGG_FIFO_INT_MASK)
+#define BIT_SET_R_MGG_FIFO_INT_MASK(x, v)                                      \
+	(BIT_CLEAR_R_MGG_FIFO_INT_MASK(x) | BIT_R_MGG_FIFO_INT_MASK(v))
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_MGQ_FIFO_RELEASE_INT_MASK		(Offset 0x1474) */
+
+#define BIT_SHIFT_MGQ_FIFO_REL_INT_MASK 0
+#define BIT_MASK_MGQ_FIFO_REL_INT_MASK 0xffff
+#define BIT_MGQ_FIFO_REL_INT_MASK(x)                                           \
+	(((x) & BIT_MASK_MGQ_FIFO_REL_INT_MASK)                                \
+	 << BIT_SHIFT_MGQ_FIFO_REL_INT_MASK)
+#define BITS_MGQ_FIFO_REL_INT_MASK                                             \
+	(BIT_MASK_MGQ_FIFO_REL_INT_MASK << BIT_SHIFT_MGQ_FIFO_REL_INT_MASK)
+#define BIT_CLEAR_MGQ_FIFO_REL_INT_MASK(x) ((x) & (~BITS_MGQ_FIFO_REL_INT_MASK))
+#define BIT_GET_MGQ_FIFO_REL_INT_MASK(x)                                       \
+	(((x) >> BIT_SHIFT_MGQ_FIFO_REL_INT_MASK) &                            \
+	 BIT_MASK_MGQ_FIFO_REL_INT_MASK)
+#define BIT_SET_MGQ_FIFO_REL_INT_MASK(x, v)                                    \
+	(BIT_CLEAR_MGQ_FIFO_REL_INT_MASK(x) | BIT_MGQ_FIFO_REL_INT_MASK(v))
+
+/* 2 REG_MGQ_FIFO_RELEASE_INT_FLAG		(Offset 0x1476) */
+
+#define BIT_SHIFT_MGQ_FIFO_REL_INT_FLAG 0
+#define BIT_MASK_MGQ_FIFO_REL_INT_FLAG 0xffff
+#define BIT_MGQ_FIFO_REL_INT_FLAG(x)                                           \
+	(((x) & BIT_MASK_MGQ_FIFO_REL_INT_FLAG)                                \
+	 << BIT_SHIFT_MGQ_FIFO_REL_INT_FLAG)
+#define BITS_MGQ_FIFO_REL_INT_FLAG                                             \
+	(BIT_MASK_MGQ_FIFO_REL_INT_FLAG << BIT_SHIFT_MGQ_FIFO_REL_INT_FLAG)
+#define BIT_CLEAR_MGQ_FIFO_REL_INT_FLAG(x) ((x) & (~BITS_MGQ_FIFO_REL_INT_FLAG))
+#define BIT_GET_MGQ_FIFO_REL_INT_FLAG(x)                                       \
+	(((x) >> BIT_SHIFT_MGQ_FIFO_REL_INT_FLAG) &                            \
+	 BIT_MASK_MGQ_FIFO_REL_INT_FLAG)
+#define BIT_SET_MGQ_FIFO_REL_INT_FLAG(x, v)                                    \
+	(BIT_CLEAR_MGQ_FIFO_REL_INT_FLAG(x) | BIT_MGQ_FIFO_REL_INT_FLAG(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822B_SUPPORT)
+
+/* 2 REG_MGG_FIFO_LIFETIME			(Offset 0x1478) */
+
+#define BIT_SHIFT_R_MGG_FIFO_LIFETIME 16
+#define BIT_MASK_R_MGG_FIFO_LIFETIME 0xffff
+#define BIT_R_MGG_FIFO_LIFETIME(x)                                             \
+	(((x) & BIT_MASK_R_MGG_FIFO_LIFETIME) << BIT_SHIFT_R_MGG_FIFO_LIFETIME)
+#define BITS_R_MGG_FIFO_LIFETIME                                               \
+	(BIT_MASK_R_MGG_FIFO_LIFETIME << BIT_SHIFT_R_MGG_FIFO_LIFETIME)
+#define BIT_CLEAR_R_MGG_FIFO_LIFETIME(x) ((x) & (~BITS_R_MGG_FIFO_LIFETIME))
+#define BIT_GET_R_MGG_FIFO_LIFETIME(x)                                         \
+	(((x) >> BIT_SHIFT_R_MGG_FIFO_LIFETIME) & BIT_MASK_R_MGG_FIFO_LIFETIME)
+#define BIT_SET_R_MGG_FIFO_LIFETIME(x, v)                                      \
+	(BIT_CLEAR_R_MGG_FIFO_LIFETIME(x) | BIT_R_MGG_FIFO_LIFETIME(v))
+
+#define BIT_SHIFT_R_MGG_FIFO_VALID_MAP 0
+#define BIT_MASK_R_MGG_FIFO_VALID_MAP 0xffff
+#define BIT_R_MGG_FIFO_VALID_MAP(x)                                            \
+	(((x) & BIT_MASK_R_MGG_FIFO_VALID_MAP)                                 \
+	 << BIT_SHIFT_R_MGG_FIFO_VALID_MAP)
+#define BITS_R_MGG_FIFO_VALID_MAP                                              \
+	(BIT_MASK_R_MGG_FIFO_VALID_MAP << BIT_SHIFT_R_MGG_FIFO_VALID_MAP)
+#define BIT_CLEAR_R_MGG_FIFO_VALID_MAP(x) ((x) & (~BITS_R_MGG_FIFO_VALID_MAP))
+#define BIT_GET_R_MGG_FIFO_VALID_MAP(x)                                        \
+	(((x) >> BIT_SHIFT_R_MGG_FIFO_VALID_MAP) &                             \
+	 BIT_MASK_R_MGG_FIFO_VALID_MAP)
+#define BIT_SET_R_MGG_FIFO_VALID_MAP(x, v)                                     \
+	(BIT_CLEAR_R_MGG_FIFO_VALID_MAP(x) | BIT_R_MGG_FIFO_VALID_MAP(v))
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_MGQ_FIFO_VALID_MAP			(Offset 0x1478) */
+
+#define BIT_SHIFT_MGQ_FIFO_PKT_VALID_MAP 0
+#define BIT_MASK_MGQ_FIFO_PKT_VALID_MAP 0xffff
+#define BIT_MGQ_FIFO_PKT_VALID_MAP(x)                                          \
+	(((x) & BIT_MASK_MGQ_FIFO_PKT_VALID_MAP)                               \
+	 << BIT_SHIFT_MGQ_FIFO_PKT_VALID_MAP)
+#define BITS_MGQ_FIFO_PKT_VALID_MAP                                            \
+	(BIT_MASK_MGQ_FIFO_PKT_VALID_MAP << BIT_SHIFT_MGQ_FIFO_PKT_VALID_MAP)
+#define BIT_CLEAR_MGQ_FIFO_PKT_VALID_MAP(x)                                    \
+	((x) & (~BITS_MGQ_FIFO_PKT_VALID_MAP))
+#define BIT_GET_MGQ_FIFO_PKT_VALID_MAP(x)                                      \
+	(((x) >> BIT_SHIFT_MGQ_FIFO_PKT_VALID_MAP) &                           \
+	 BIT_MASK_MGQ_FIFO_PKT_VALID_MAP)
+#define BIT_SET_MGQ_FIFO_PKT_VALID_MAP(x, v)                                   \
+	(BIT_CLEAR_MGQ_FIFO_PKT_VALID_MAP(x) | BIT_MGQ_FIFO_PKT_VALID_MAP(v))
+
+/* 2 REG_MGQ_FIFO_LIFETIME			(Offset 0x147A) */
+
+#define BIT_SHIFT_MGQ_FIFO_LIFETIME 0
+#define BIT_MASK_MGQ_FIFO_LIFETIME 0xffff
+#define BIT_MGQ_FIFO_LIFETIME(x)                                               \
+	(((x) & BIT_MASK_MGQ_FIFO_LIFETIME) << BIT_SHIFT_MGQ_FIFO_LIFETIME)
+#define BITS_MGQ_FIFO_LIFETIME                                                 \
+	(BIT_MASK_MGQ_FIFO_LIFETIME << BIT_SHIFT_MGQ_FIFO_LIFETIME)
+#define BIT_CLEAR_MGQ_FIFO_LIFETIME(x) ((x) & (~BITS_MGQ_FIFO_LIFETIME))
+#define BIT_GET_MGQ_FIFO_LIFETIME(x)                                           \
+	(((x) >> BIT_SHIFT_MGQ_FIFO_LIFETIME) & BIT_MASK_MGQ_FIFO_LIFETIME)
+#define BIT_SET_MGQ_FIFO_LIFETIME(x, v)                                        \
+	(BIT_CLEAR_MGQ_FIFO_LIFETIME(x) | BIT_MGQ_FIFO_LIFETIME(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_PKT_TRANS				(Offset 0x1480) */
+
+#define BIT_SHIFT_IE_DESC_OFFSET 16
+#define BIT_MASK_IE_DESC_OFFSET 0x1ff
+#define BIT_IE_DESC_OFFSET(x)                                                  \
+	(((x) & BIT_MASK_IE_DESC_OFFSET) << BIT_SHIFT_IE_DESC_OFFSET)
+#define BITS_IE_DESC_OFFSET                                                    \
+	(BIT_MASK_IE_DESC_OFFSET << BIT_SHIFT_IE_DESC_OFFSET)
+#define BIT_CLEAR_IE_DESC_OFFSET(x) ((x) & (~BITS_IE_DESC_OFFSET))
+#define BIT_GET_IE_DESC_OFFSET(x)                                              \
+	(((x) >> BIT_SHIFT_IE_DESC_OFFSET) & BIT_MASK_IE_DESC_OFFSET)
+#define BIT_SET_IE_DESC_OFFSET(x, v)                                           \
+	(BIT_CLEAR_IE_DESC_OFFSET(x) | BIT_IE_DESC_OFFSET(v))
+
+#define BIT_DIS_FWCMD_PATH_ERRCHK BIT(13)
+#define BIT_MAC_HDR_CONVERT_EN BIT(12)
+#define BIT_TXDESC_TRANS_EN BIT(8)
+#define BIT_PKT_TRANS_ERRINT_EN BIT(7)
+
+#define BIT_SHIFT_PKT_TRANS_ERR_MACID_SEL 4
+#define BIT_MASK_PKT_TRANS_ERR_MACID_SEL 0x3
+#define BIT_PKT_TRANS_ERR_MACID_SEL(x)                                         \
+	(((x) & BIT_MASK_PKT_TRANS_ERR_MACID_SEL)                              \
+	 << BIT_SHIFT_PKT_TRANS_ERR_MACID_SEL)
+#define BITS_PKT_TRANS_ERR_MACID_SEL                                           \
+	(BIT_MASK_PKT_TRANS_ERR_MACID_SEL << BIT_SHIFT_PKT_TRANS_ERR_MACID_SEL)
+#define BIT_CLEAR_PKT_TRANS_ERR_MACID_SEL(x)                                   \
+	((x) & (~BITS_PKT_TRANS_ERR_MACID_SEL))
+#define BIT_GET_PKT_TRANS_ERR_MACID_SEL(x)                                     \
+	(((x) >> BIT_SHIFT_PKT_TRANS_ERR_MACID_SEL) &                          \
+	 BIT_MASK_PKT_TRANS_ERR_MACID_SEL)
+#define BIT_SET_PKT_TRANS_ERR_MACID_SEL(x, v)                                  \
+	(BIT_CLEAR_PKT_TRANS_ERR_MACID_SEL(x) | BIT_PKT_TRANS_ERR_MACID_SEL(v))
+
+#define BIT_PKT_TRANS_IEINIT_ERR BIT(3)
+#define BIT_PKT_TRANS_IENUM_ERR BIT(2)
+#define BIT_PKT_TRANS_IECNT_ERR1 BIT(1)
+#define BIT_PKT_TRANS_IECNT_ERR0 BIT(0)
+
+/* 2 REG_SHCUT_LLC_ETH_TYPE1			(Offset 0x1488) */
+
+#define BIT_SHIFT_SHCUT_MHDR_OFFSET 16
+#define BIT_MASK_SHCUT_MHDR_OFFSET 0x1ff
+#define BIT_SHCUT_MHDR_OFFSET(x)                                               \
+	(((x) & BIT_MASK_SHCUT_MHDR_OFFSET) << BIT_SHIFT_SHCUT_MHDR_OFFSET)
+#define BITS_SHCUT_MHDR_OFFSET                                                 \
+	(BIT_MASK_SHCUT_MHDR_OFFSET << BIT_SHIFT_SHCUT_MHDR_OFFSET)
+#define BIT_CLEAR_SHCUT_MHDR_OFFSET(x) ((x) & (~BITS_SHCUT_MHDR_OFFSET))
+#define BIT_GET_SHCUT_MHDR_OFFSET(x)                                           \
+	(((x) >> BIT_SHIFT_SHCUT_MHDR_OFFSET) & BIT_MASK_SHCUT_MHDR_OFFSET)
+#define BIT_SET_SHCUT_MHDR_OFFSET(x, v)                                        \
+	(BIT_CLEAR_SHCUT_MHDR_OFFSET(x) | BIT_SHCUT_MHDR_OFFSET(v))
+
+#define BIT_SHIFT_PKT_TRANS_ERR_MACID 0
+#define BIT_MASK_PKT_TRANS_ERR_MACID 0xffffffffL
+#define BIT_PKT_TRANS_ERR_MACID(x)                                             \
+	(((x) & BIT_MASK_PKT_TRANS_ERR_MACID) << BIT_SHIFT_PKT_TRANS_ERR_MACID)
+#define BITS_PKT_TRANS_ERR_MACID                                               \
+	(BIT_MASK_PKT_TRANS_ERR_MACID << BIT_SHIFT_PKT_TRANS_ERR_MACID)
+#define BIT_CLEAR_PKT_TRANS_ERR_MACID(x) ((x) & (~BITS_PKT_TRANS_ERR_MACID))
+#define BIT_GET_PKT_TRANS_ERR_MACID(x)                                         \
+	(((x) >> BIT_SHIFT_PKT_TRANS_ERR_MACID) & BIT_MASK_PKT_TRANS_ERR_MACID)
+#define BIT_SET_PKT_TRANS_ERR_MACID(x, v)                                      \
+	(BIT_CLEAR_PKT_TRANS_ERR_MACID(x) | BIT_PKT_TRANS_ERR_MACID(v))
+
+/* 2 REG_FWCMDQ_CTRL				(Offset 0x14A0) */
+
+#define BIT_FW_RELEASEPKT_POLLING BIT(31)
+
+#define BIT_SHIFT_FWCMDQ_RELEASE_HEAD 16
+#define BIT_MASK_FWCMDQ_RELEASE_HEAD 0xfff
+#define BIT_FWCMDQ_RELEASE_HEAD(x)                                             \
+	(((x) & BIT_MASK_FWCMDQ_RELEASE_HEAD) << BIT_SHIFT_FWCMDQ_RELEASE_HEAD)
+#define BITS_FWCMDQ_RELEASE_HEAD                                               \
+	(BIT_MASK_FWCMDQ_RELEASE_HEAD << BIT_SHIFT_FWCMDQ_RELEASE_HEAD)
+#define BIT_CLEAR_FWCMDQ_RELEASE_HEAD(x) ((x) & (~BITS_FWCMDQ_RELEASE_HEAD))
+#define BIT_GET_FWCMDQ_RELEASE_HEAD(x)                                         \
+	(((x) >> BIT_SHIFT_FWCMDQ_RELEASE_HEAD) & BIT_MASK_FWCMDQ_RELEASE_HEAD)
+#define BIT_SET_FWCMDQ_RELEASE_HEAD(x, v)                                      \
+	(BIT_CLEAR_FWCMDQ_RELEASE_HEAD(x) | BIT_FWCMDQ_RELEASE_HEAD(v))
+
+#define BIT_FW_GETPKTT_POLLING BIT(15)
+
+#define BIT_SHIFT_FWCMDQ_H 0
+#define BIT_MASK_FWCMDQ_H 0xfff
+#define BIT_FWCMDQ_H(x) (((x) & BIT_MASK_FWCMDQ_H) << BIT_SHIFT_FWCMDQ_H)
+#define BITS_FWCMDQ_H (BIT_MASK_FWCMDQ_H << BIT_SHIFT_FWCMDQ_H)
+#define BIT_CLEAR_FWCMDQ_H(x) ((x) & (~BITS_FWCMDQ_H))
+#define BIT_GET_FWCMDQ_H(x) (((x) >> BIT_SHIFT_FWCMDQ_H) & BIT_MASK_FWCMDQ_H)
+#define BIT_SET_FWCMDQ_H(x, v) (BIT_CLEAR_FWCMDQ_H(x) | BIT_FWCMDQ_H(v))
+
+/* 2 REG_FWCMDQ_PAGE				(Offset 0x14A4) */
+
+#define BIT_SHIFT_FWCMDQ_TOTAL_PAGE 16
+#define BIT_MASK_FWCMDQ_TOTAL_PAGE 0xfff
+#define BIT_FWCMDQ_TOTAL_PAGE(x)                                               \
+	(((x) & BIT_MASK_FWCMDQ_TOTAL_PAGE) << BIT_SHIFT_FWCMDQ_TOTAL_PAGE)
+#define BITS_FWCMDQ_TOTAL_PAGE                                                 \
+	(BIT_MASK_FWCMDQ_TOTAL_PAGE << BIT_SHIFT_FWCMDQ_TOTAL_PAGE)
+#define BIT_CLEAR_FWCMDQ_TOTAL_PAGE(x) ((x) & (~BITS_FWCMDQ_TOTAL_PAGE))
+#define BIT_GET_FWCMDQ_TOTAL_PAGE(x)                                           \
+	(((x) >> BIT_SHIFT_FWCMDQ_TOTAL_PAGE) & BIT_MASK_FWCMDQ_TOTAL_PAGE)
+#define BIT_SET_FWCMDQ_TOTAL_PAGE(x, v)                                        \
+	(BIT_CLEAR_FWCMDQ_TOTAL_PAGE(x) | BIT_FWCMDQ_TOTAL_PAGE(v))
+
+#define BIT_SHIFT_FWCMDQ_QUEUE_PAGE 0
+#define BIT_MASK_FWCMDQ_QUEUE_PAGE 0xfff
+#define BIT_FWCMDQ_QUEUE_PAGE(x)                                               \
+	(((x) & BIT_MASK_FWCMDQ_QUEUE_PAGE) << BIT_SHIFT_FWCMDQ_QUEUE_PAGE)
+#define BITS_FWCMDQ_QUEUE_PAGE                                                 \
+	(BIT_MASK_FWCMDQ_QUEUE_PAGE << BIT_SHIFT_FWCMDQ_QUEUE_PAGE)
+#define BIT_CLEAR_FWCMDQ_QUEUE_PAGE(x) ((x) & (~BITS_FWCMDQ_QUEUE_PAGE))
+#define BIT_GET_FWCMDQ_QUEUE_PAGE(x)                                           \
+	(((x) >> BIT_SHIFT_FWCMDQ_QUEUE_PAGE) & BIT_MASK_FWCMDQ_QUEUE_PAGE)
+#define BIT_SET_FWCMDQ_QUEUE_PAGE(x, v)                                        \
+	(BIT_CLEAR_FWCMDQ_QUEUE_PAGE(x) | BIT_FWCMDQ_QUEUE_PAGE(v))
+
+/* 2 REG_FWCMDQ_INFO				(Offset 0x14A8) */
+
+#define BIT_FWCMD_READY BIT(31)
+#define BIT_FWCMDQ_OVERFLOW BIT(30)
+#define BIT_FWCMDQ_UNDERFLOW BIT(29)
+#define BIT_FWCMDQ_RELEASE_MISS BIT(28)
+
+#define BIT_SHIFT_FWCMDQ_TOTAL_PKT 16
+#define BIT_MASK_FWCMDQ_TOTAL_PKT 0xfff
+#define BIT_FWCMDQ_TOTAL_PKT(x)                                                \
+	(((x) & BIT_MASK_FWCMDQ_TOTAL_PKT) << BIT_SHIFT_FWCMDQ_TOTAL_PKT)
+#define BITS_FWCMDQ_TOTAL_PKT                                                  \
+	(BIT_MASK_FWCMDQ_TOTAL_PKT << BIT_SHIFT_FWCMDQ_TOTAL_PKT)
+#define BIT_CLEAR_FWCMDQ_TOTAL_PKT(x) ((x) & (~BITS_FWCMDQ_TOTAL_PKT))
+#define BIT_GET_FWCMDQ_TOTAL_PKT(x)                                            \
+	(((x) >> BIT_SHIFT_FWCMDQ_TOTAL_PKT) & BIT_MASK_FWCMDQ_TOTAL_PKT)
+#define BIT_SET_FWCMDQ_TOTAL_PKT(x, v)                                         \
+	(BIT_CLEAR_FWCMDQ_TOTAL_PKT(x) | BIT_FWCMDQ_TOTAL_PKT(v))
+
+#define BIT_SHIFT_FWCMDQ_QUEUE_PKT 0
+#define BIT_MASK_FWCMDQ_QUEUE_PKT 0xfff
+#define BIT_FWCMDQ_QUEUE_PKT(x)                                                \
+	(((x) & BIT_MASK_FWCMDQ_QUEUE_PKT) << BIT_SHIFT_FWCMDQ_QUEUE_PKT)
+#define BITS_FWCMDQ_QUEUE_PKT                                                  \
+	(BIT_MASK_FWCMDQ_QUEUE_PKT << BIT_SHIFT_FWCMDQ_QUEUE_PKT)
+#define BIT_CLEAR_FWCMDQ_QUEUE_PKT(x) ((x) & (~BITS_FWCMDQ_QUEUE_PKT))
+#define BIT_GET_FWCMDQ_QUEUE_PKT(x)                                            \
+	(((x) >> BIT_SHIFT_FWCMDQ_QUEUE_PKT) & BIT_MASK_FWCMDQ_QUEUE_PKT)
+#define BIT_SET_FWCMDQ_QUEUE_PKT(x, v)                                         \
+	(BIT_CLEAR_FWCMDQ_QUEUE_PKT(x) | BIT_FWCMDQ_QUEUE_PKT(v))
+
+/* 2 REG_FWCMDQ_HOLD_PKTNUM			(Offset 0x14AC) */
+
+#define BIT_SHIFT_FWCMDQ_HOLD__PKTNUM 0
+#define BIT_MASK_FWCMDQ_HOLD__PKTNUM 0xfff
+#define BIT_FWCMDQ_HOLD__PKTNUM(x)                                             \
+	(((x) & BIT_MASK_FWCMDQ_HOLD__PKTNUM) << BIT_SHIFT_FWCMDQ_HOLD__PKTNUM)
+#define BITS_FWCMDQ_HOLD__PKTNUM                                               \
+	(BIT_MASK_FWCMDQ_HOLD__PKTNUM << BIT_SHIFT_FWCMDQ_HOLD__PKTNUM)
+#define BIT_CLEAR_FWCMDQ_HOLD__PKTNUM(x) ((x) & (~BITS_FWCMDQ_HOLD__PKTNUM))
+#define BIT_GET_FWCMDQ_HOLD__PKTNUM(x)                                         \
+	(((x) >> BIT_SHIFT_FWCMDQ_HOLD__PKTNUM) & BIT_MASK_FWCMDQ_HOLD__PKTNUM)
+#define BIT_SET_FWCMDQ_HOLD__PKTNUM(x, v)                                      \
+	(BIT_CLEAR_FWCMDQ_HOLD__PKTNUM(x) | BIT_FWCMDQ_HOLD__PKTNUM(v))
+
+/* 2 REG_MU_TX_CTRL				(Offset 0x14C0) */
+
+#define BIT_SEARCH_DONE_RDY BIT(31)
+#define BIT_MU_EN BIT(30)
+#define BIT_MU_SECONDARY_WAITMODE_EN BIT(29)
+#define BIT_MU_BB_SCORE_EN BIT(28)
+#define BIT_MU_SECONDARY_ANT_COUNT_EN BIT(27)
+#define BIT_MUARB_SEARCH_ERR_EN BIT(26)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_MU_TX_CTL				(Offset 0x14C0) */
+
+#define BIT_R_MU_P1_WAIT_STATE_EN BIT(16)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_MU_TX_CTRL				(Offset 0x14C0) */
+
+#define BIT_SHIFT_DIS_SU_TXBF 16
+#define BIT_MASK_DIS_SU_TXBF 0x3f
+#define BIT_DIS_SU_TXBF(x)                                                     \
+	(((x) & BIT_MASK_DIS_SU_TXBF) << BIT_SHIFT_DIS_SU_TXBF)
+#define BITS_DIS_SU_TXBF (BIT_MASK_DIS_SU_TXBF << BIT_SHIFT_DIS_SU_TXBF)
+#define BIT_CLEAR_DIS_SU_TXBF(x) ((x) & (~BITS_DIS_SU_TXBF))
+#define BIT_GET_DIS_SU_TXBF(x)                                                 \
+	(((x) >> BIT_SHIFT_DIS_SU_TXBF) & BIT_MASK_DIS_SU_TXBF)
+#define BIT_SET_DIS_SU_TXBF(x, v)                                              \
+	(BIT_CLEAR_DIS_SU_TXBF(x) | BIT_DIS_SU_TXBF(v))
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_MU_TX_CTL				(Offset 0x14C0) */
+
+#define BIT_SHIFT_R_MU_RL 12
+#define BIT_MASK_R_MU_RL 0xf
+#define BIT_R_MU_RL(x) (((x) & BIT_MASK_R_MU_RL) << BIT_SHIFT_R_MU_RL)
+#define BITS_R_MU_RL (BIT_MASK_R_MU_RL << BIT_SHIFT_R_MU_RL)
+#define BIT_CLEAR_R_MU_RL(x) ((x) & (~BITS_R_MU_RL))
+#define BIT_GET_R_MU_RL(x) (((x) >> BIT_SHIFT_R_MU_RL) & BIT_MASK_R_MU_RL)
+#define BIT_SET_R_MU_RL(x, v) (BIT_CLEAR_R_MU_RL(x) | BIT_R_MU_RL(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_MU_TX_CTRL				(Offset 0x14C0) */
+
+#define BIT_SHIFT_MU_RL 12
+#define BIT_MASK_MU_RL 0xf
+#define BIT_MU_RL(x) (((x) & BIT_MASK_MU_RL) << BIT_SHIFT_MU_RL)
+#define BITS_MU_RL (BIT_MASK_MU_RL << BIT_SHIFT_MU_RL)
+#define BIT_CLEAR_MU_RL(x) ((x) & (~BITS_MU_RL))
+#define BIT_GET_MU_RL(x) (((x) >> BIT_SHIFT_MU_RL) & BIT_MASK_MU_RL)
+#define BIT_SET_MU_RL(x, v) (BIT_CLEAR_MU_RL(x) | BIT_MU_RL(v))
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_MU_TX_CTL				(Offset 0x14C0) */
+
+#define BIT_R_FORCE_P1_RATEDOWN BIT(11)
+
+#define BIT_SHIFT_R_MU_TAB_SEL 8
+#define BIT_MASK_R_MU_TAB_SEL 0x7
+#define BIT_R_MU_TAB_SEL(x)                                                    \
+	(((x) & BIT_MASK_R_MU_TAB_SEL) << BIT_SHIFT_R_MU_TAB_SEL)
+#define BITS_R_MU_TAB_SEL (BIT_MASK_R_MU_TAB_SEL << BIT_SHIFT_R_MU_TAB_SEL)
+#define BIT_CLEAR_R_MU_TAB_SEL(x) ((x) & (~BITS_R_MU_TAB_SEL))
+#define BIT_GET_R_MU_TAB_SEL(x)                                                \
+	(((x) >> BIT_SHIFT_R_MU_TAB_SEL) & BIT_MASK_R_MU_TAB_SEL)
+#define BIT_SET_R_MU_TAB_SEL(x, v)                                             \
+	(BIT_CLEAR_R_MU_TAB_SEL(x) | BIT_R_MU_TAB_SEL(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_MU_TX_CTRL				(Offset 0x14C0) */
+
+#define BIT_SHIFT_MU_TAB_SEL 8
+#define BIT_MASK_MU_TAB_SEL 0xf
+#define BIT_MU_TAB_SEL(x) (((x) & BIT_MASK_MU_TAB_SEL) << BIT_SHIFT_MU_TAB_SEL)
+#define BITS_MU_TAB_SEL (BIT_MASK_MU_TAB_SEL << BIT_SHIFT_MU_TAB_SEL)
+#define BIT_CLEAR_MU_TAB_SEL(x) ((x) & (~BITS_MU_TAB_SEL))
+#define BIT_GET_MU_TAB_SEL(x)                                                  \
+	(((x) >> BIT_SHIFT_MU_TAB_SEL) & BIT_MASK_MU_TAB_SEL)
+#define BIT_SET_MU_TAB_SEL(x, v) (BIT_CLEAR_MU_TAB_SEL(x) | BIT_MU_TAB_SEL(v))
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_MU_TX_CTL				(Offset 0x14C0) */
+
+#define BIT_R_EN_MU_MIMO BIT(7)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_MU_TX_CTL				(Offset 0x14C0) */
+
+#define BIT_R_EN_REVERS_GTAB BIT(6)
+
+#define BIT_SHIFT_R_MU_TABLE_VALID 0
+#define BIT_MASK_R_MU_TABLE_VALID 0x3f
+#define BIT_R_MU_TABLE_VALID(x)                                                \
+	(((x) & BIT_MASK_R_MU_TABLE_VALID) << BIT_SHIFT_R_MU_TABLE_VALID)
+#define BITS_R_MU_TABLE_VALID                                                  \
+	(BIT_MASK_R_MU_TABLE_VALID << BIT_SHIFT_R_MU_TABLE_VALID)
+#define BIT_CLEAR_R_MU_TABLE_VALID(x) ((x) & (~BITS_R_MU_TABLE_VALID))
+#define BIT_GET_R_MU_TABLE_VALID(x)                                            \
+	(((x) >> BIT_SHIFT_R_MU_TABLE_VALID) & BIT_MASK_R_MU_TABLE_VALID)
+#define BIT_SET_R_MU_TABLE_VALID(x, v)                                         \
+	(BIT_CLEAR_R_MU_TABLE_VALID(x) | BIT_R_MU_TABLE_VALID(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_MU_TX_CTRL				(Offset 0x14C0) */
+
+#define BIT_SHIFT_MU_TAB_VALID 0
+#define BIT_MASK_MU_TAB_VALID 0x3f
+#define BIT_MU_TAB_VALID(x)                                                    \
+	(((x) & BIT_MASK_MU_TAB_VALID) << BIT_SHIFT_MU_TAB_VALID)
+#define BITS_MU_TAB_VALID (BIT_MASK_MU_TAB_VALID << BIT_SHIFT_MU_TAB_VALID)
+#define BIT_CLEAR_MU_TAB_VALID(x) ((x) & (~BITS_MU_TAB_VALID))
+#define BIT_GET_MU_TAB_VALID(x)                                                \
+	(((x) >> BIT_SHIFT_MU_TAB_VALID) & BIT_MASK_MU_TAB_VALID)
+#define BIT_SET_MU_TAB_VALID(x, v)                                             \
+	(BIT_CLEAR_MU_TAB_VALID(x) | BIT_MU_TAB_VALID(v))
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_MU_STA_GID_VLD			(Offset 0x14C4) */
+
+#define BIT_SHIFT_R_MU_STA_GTAB_VALID 0
+#define BIT_MASK_R_MU_STA_GTAB_VALID 0xffffffffL
+#define BIT_R_MU_STA_GTAB_VALID(x)                                             \
+	(((x) & BIT_MASK_R_MU_STA_GTAB_VALID) << BIT_SHIFT_R_MU_STA_GTAB_VALID)
+#define BITS_R_MU_STA_GTAB_VALID                                               \
+	(BIT_MASK_R_MU_STA_GTAB_VALID << BIT_SHIFT_R_MU_STA_GTAB_VALID)
+#define BIT_CLEAR_R_MU_STA_GTAB_VALID(x) ((x) & (~BITS_R_MU_STA_GTAB_VALID))
+#define BIT_GET_R_MU_STA_GTAB_VALID(x)                                         \
+	(((x) >> BIT_SHIFT_R_MU_STA_GTAB_VALID) & BIT_MASK_R_MU_STA_GTAB_VALID)
+#define BIT_SET_R_MU_STA_GTAB_VALID(x, v)                                      \
+	(BIT_CLEAR_R_MU_STA_GTAB_VALID(x) | BIT_R_MU_STA_GTAB_VALID(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_MU_STA_GID_VLD			(Offset 0x14C4) */
+
+#define BIT_SHIFT_MU_STA_GTAB_VALID 0
+#define BIT_MASK_MU_STA_GTAB_VALID 0xffffffffL
+#define BIT_MU_STA_GTAB_VALID(x)                                               \
+	(((x) & BIT_MASK_MU_STA_GTAB_VALID) << BIT_SHIFT_MU_STA_GTAB_VALID)
+#define BITS_MU_STA_GTAB_VALID                                                 \
+	(BIT_MASK_MU_STA_GTAB_VALID << BIT_SHIFT_MU_STA_GTAB_VALID)
+#define BIT_CLEAR_MU_STA_GTAB_VALID(x) ((x) & (~BITS_MU_STA_GTAB_VALID))
+#define BIT_GET_MU_STA_GTAB_VALID(x)                                           \
+	(((x) >> BIT_SHIFT_MU_STA_GTAB_VALID) & BIT_MASK_MU_STA_GTAB_VALID)
+#define BIT_SET_MU_STA_GTAB_VALID(x, v)                                        \
+	(BIT_CLEAR_MU_STA_GTAB_VALID(x) | BIT_MU_STA_GTAB_VALID(v))
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_MU_STA_USER_POS_INFO		(Offset 0x14C8) */
+
+#define BIT_SHIFT_R_MU_STA_GTAB_POSITION_L 0
+#define BIT_MASK_R_MU_STA_GTAB_POSITION_L 0xffffffffL
+#define BIT_R_MU_STA_GTAB_POSITION_L(x)                                        \
+	(((x) & BIT_MASK_R_MU_STA_GTAB_POSITION_L)                             \
+	 << BIT_SHIFT_R_MU_STA_GTAB_POSITION_L)
+#define BITS_R_MU_STA_GTAB_POSITION_L                                          \
+	(BIT_MASK_R_MU_STA_GTAB_POSITION_L                                     \
+	 << BIT_SHIFT_R_MU_STA_GTAB_POSITION_L)
+#define BIT_CLEAR_R_MU_STA_GTAB_POSITION_L(x)                                  \
+	((x) & (~BITS_R_MU_STA_GTAB_POSITION_L))
+#define BIT_GET_R_MU_STA_GTAB_POSITION_L(x)                                    \
+	(((x) >> BIT_SHIFT_R_MU_STA_GTAB_POSITION_L) &                         \
+	 BIT_MASK_R_MU_STA_GTAB_POSITION_L)
+#define BIT_SET_R_MU_STA_GTAB_POSITION_L(x, v)                                 \
+	(BIT_CLEAR_R_MU_STA_GTAB_POSITION_L(x) |                               \
+	 BIT_R_MU_STA_GTAB_POSITION_L(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_MU_STA_USER_POS_INFO		(Offset 0x14C8) */
+
+#define BIT_SHIFT_MU_STA_GTAB_POSITION_L 0
+#define BIT_MASK_MU_STA_GTAB_POSITION_L 0xffffffffL
+#define BIT_MU_STA_GTAB_POSITION_L(x)                                          \
+	(((x) & BIT_MASK_MU_STA_GTAB_POSITION_L)                               \
+	 << BIT_SHIFT_MU_STA_GTAB_POSITION_L)
+#define BITS_MU_STA_GTAB_POSITION_L                                            \
+	(BIT_MASK_MU_STA_GTAB_POSITION_L << BIT_SHIFT_MU_STA_GTAB_POSITION_L)
+#define BIT_CLEAR_MU_STA_GTAB_POSITION_L(x)                                    \
+	((x) & (~BITS_MU_STA_GTAB_POSITION_L))
+#define BIT_GET_MU_STA_GTAB_POSITION_L(x)                                      \
+	(((x) >> BIT_SHIFT_MU_STA_GTAB_POSITION_L) &                           \
+	 BIT_MASK_MU_STA_GTAB_POSITION_L)
+#define BIT_SET_MU_STA_GTAB_POSITION_L(x, v)                                   \
+	(BIT_CLEAR_MU_STA_GTAB_POSITION_L(x) | BIT_MU_STA_GTAB_POSITION_L(v))
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_MU_STA_USER_POS_INFO_H		(Offset 0x14CC) */
+
+#define BIT_SHIFT_R_MU_STA_GTAB_POSITION_H 0
+#define BIT_MASK_R_MU_STA_GTAB_POSITION_H 0xffffffffL
+#define BIT_R_MU_STA_GTAB_POSITION_H(x)                                        \
+	(((x) & BIT_MASK_R_MU_STA_GTAB_POSITION_H)                             \
+	 << BIT_SHIFT_R_MU_STA_GTAB_POSITION_H)
+#define BITS_R_MU_STA_GTAB_POSITION_H                                          \
+	(BIT_MASK_R_MU_STA_GTAB_POSITION_H                                     \
+	 << BIT_SHIFT_R_MU_STA_GTAB_POSITION_H)
+#define BIT_CLEAR_R_MU_STA_GTAB_POSITION_H(x)                                  \
+	((x) & (~BITS_R_MU_STA_GTAB_POSITION_H))
+#define BIT_GET_R_MU_STA_GTAB_POSITION_H(x)                                    \
+	(((x) >> BIT_SHIFT_R_MU_STA_GTAB_POSITION_H) &                         \
+	 BIT_MASK_R_MU_STA_GTAB_POSITION_H)
+#define BIT_SET_R_MU_STA_GTAB_POSITION_H(x, v)                                 \
+	(BIT_CLEAR_R_MU_STA_GTAB_POSITION_H(x) |                               \
+	 BIT_R_MU_STA_GTAB_POSITION_H(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_MU_STA_USER_POS_INFO_H		(Offset 0x14CC) */
+
+#define BIT_SHIFT_MU_STA_GTAB_POSITION_H 0
+#define BIT_MASK_MU_STA_GTAB_POSITION_H 0xffffffffL
+#define BIT_MU_STA_GTAB_POSITION_H(x)                                          \
+	(((x) & BIT_MASK_MU_STA_GTAB_POSITION_H)                               \
+	 << BIT_SHIFT_MU_STA_GTAB_POSITION_H)
+#define BITS_MU_STA_GTAB_POSITION_H                                            \
+	(BIT_MASK_MU_STA_GTAB_POSITION_H << BIT_SHIFT_MU_STA_GTAB_POSITION_H)
+#define BIT_CLEAR_MU_STA_GTAB_POSITION_H(x)                                    \
+	((x) & (~BITS_MU_STA_GTAB_POSITION_H))
+#define BIT_GET_MU_STA_GTAB_POSITION_H(x)                                      \
+	(((x) >> BIT_SHIFT_MU_STA_GTAB_POSITION_H) &                           \
+	 BIT_MASK_MU_STA_GTAB_POSITION_H)
+#define BIT_SET_MU_STA_GTAB_POSITION_H(x, v)                                   \
+	(BIT_CLEAR_MU_STA_GTAB_POSITION_H(x) | BIT_MU_STA_GTAB_POSITION_H(v))
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_MU_TRX_DBG_CNT			(Offset 0x14D0) */
+
+#define BIT_MU_DNGCNT_RST BIT(20)
+
+#endif
+
+#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+
+/* 2 REG_MU_TRX_DBG_CNT			(Offset 0x14D0) */
+
+#define BIT_SHIFT_MU_DBGCNT_SEL 16
+#define BIT_MASK_MU_DBGCNT_SEL 0xf
+#define BIT_MU_DBGCNT_SEL(x)                                                   \
+	(((x) & BIT_MASK_MU_DBGCNT_SEL) << BIT_SHIFT_MU_DBGCNT_SEL)
+#define BITS_MU_DBGCNT_SEL (BIT_MASK_MU_DBGCNT_SEL << BIT_SHIFT_MU_DBGCNT_SEL)
+#define BIT_CLEAR_MU_DBGCNT_SEL(x) ((x) & (~BITS_MU_DBGCNT_SEL))
+#define BIT_GET_MU_DBGCNT_SEL(x)                                               \
+	(((x) >> BIT_SHIFT_MU_DBGCNT_SEL) & BIT_MASK_MU_DBGCNT_SEL)
+#define BIT_SET_MU_DBGCNT_SEL(x, v)                                            \
+	(BIT_CLEAR_MU_DBGCNT_SEL(x) | BIT_MU_DBGCNT_SEL(v))
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_CHNL_INFO_CTRL			(Offset 0x14D0) */
+
+#define BIT_CHNL_REF_RXNAV BIT(7)
+#define BIT_CHNL_REF_VBON BIT(6)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_CHNL_INFO_CTRL			(Offset 0x14D0) */
+
+#define BIT_CHNL_REF_EDCCA BIT(5)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_CHNL_INFO_CTRL			(Offset 0x14D0) */
+
+#define BIT_RST_CHNL_BUSY BIT(3)
+#define BIT_RST_CHNL_IDLE BIT(2)
+#define BIT_CHNL_INFO_RST BIT(1)
+#define BIT_ATM_AIRTIME_EN BIT(0)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_MU_TRX_DBG_CNT			(Offset 0x14D0) */
+
+#define BIT_SHIFT_MU_DNGCNT 0
+#define BIT_MASK_MU_DNGCNT 0xffff
+#define BIT_MU_DNGCNT(x) (((x) & BIT_MASK_MU_DNGCNT) << BIT_SHIFT_MU_DNGCNT)
+#define BITS_MU_DNGCNT (BIT_MASK_MU_DNGCNT << BIT_SHIFT_MU_DNGCNT)
+#define BIT_CLEAR_MU_DNGCNT(x) ((x) & (~BITS_MU_DNGCNT))
+#define BIT_GET_MU_DNGCNT(x) (((x) >> BIT_SHIFT_MU_DNGCNT) & BIT_MASK_MU_DNGCNT)
+#define BIT_SET_MU_DNGCNT(x, v) (BIT_CLEAR_MU_DNGCNT(x) | BIT_MU_DNGCNT(v))
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_CHNL_BUSY_TIME			(Offset 0x14D8) */
+
+#define BIT_SHIFT_CHNL_BUSY_TIME 0
+#define BIT_MASK_CHNL_BUSY_TIME 0xffffffffL
+#define BIT_CHNL_BUSY_TIME(x)                                                  \
+	(((x) & BIT_MASK_CHNL_BUSY_TIME) << BIT_SHIFT_CHNL_BUSY_TIME)
+#define BITS_CHNL_BUSY_TIME                                                    \
+	(BIT_MASK_CHNL_BUSY_TIME << BIT_SHIFT_CHNL_BUSY_TIME)
+#define BIT_CLEAR_CHNL_BUSY_TIME(x) ((x) & (~BITS_CHNL_BUSY_TIME))
+#define BIT_GET_CHNL_BUSY_TIME(x)                                              \
+	(((x) >> BIT_SHIFT_CHNL_BUSY_TIME) & BIT_MASK_CHNL_BUSY_TIME)
+#define BIT_SET_CHNL_BUSY_TIME(x, v)                                           \
+	(BIT_CLEAR_CHNL_BUSY_TIME(x) | BIT_CHNL_BUSY_TIME(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_MU_TRX_DBG_CNT_V1			(Offset 0x14DC) */
+
+#define BIT_FORCE_SND_STS_EN BIT(31)
+
+#define BIT_SHIFT_SND_STS_VALUE 24
+#define BIT_MASK_SND_STS_VALUE 0x3f
+#define BIT_SND_STS_VALUE(x)                                                   \
+	(((x) & BIT_MASK_SND_STS_VALUE) << BIT_SHIFT_SND_STS_VALUE)
+#define BITS_SND_STS_VALUE (BIT_MASK_SND_STS_VALUE << BIT_SHIFT_SND_STS_VALUE)
+#define BIT_CLEAR_SND_STS_VALUE(x) ((x) & (~BITS_SND_STS_VALUE))
+#define BIT_GET_SND_STS_VALUE(x)                                               \
+	(((x) >> BIT_SHIFT_SND_STS_VALUE) & BIT_MASK_SND_STS_VALUE)
+#define BIT_SET_SND_STS_VALUE(x, v)                                            \
+	(BIT_CLEAR_SND_STS_VALUE(x) | BIT_SND_STS_VALUE(v))
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_MU_TRX_DBG_CNT_V1			(Offset 0x14DC) */
+
+#define BIT_SHIFT_MU_DNGCNT_SEL 16
+#define BIT_MASK_MU_DNGCNT_SEL 0xf
+#define BIT_MU_DNGCNT_SEL(x)                                                   \
+	(((x) & BIT_MASK_MU_DNGCNT_SEL) << BIT_SHIFT_MU_DNGCNT_SEL)
+#define BITS_MU_DNGCNT_SEL (BIT_MASK_MU_DNGCNT_SEL << BIT_SHIFT_MU_DNGCNT_SEL)
+#define BIT_CLEAR_MU_DNGCNT_SEL(x) ((x) & (~BITS_MU_DNGCNT_SEL))
+#define BIT_GET_MU_DNGCNT_SEL(x)                                               \
+	(((x) >> BIT_SHIFT_MU_DNGCNT_SEL) & BIT_MASK_MU_DNGCNT_SEL)
+#define BIT_SET_MU_DNGCNT_SEL(x, v)                                            \
+	(BIT_CLEAR_MU_DNGCNT_SEL(x) | BIT_MU_DNGCNT_SEL(v))
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT)
+
+/* 2 REG_SU_DURATION				(Offset 0x14F0) */
+
+#define BIT_SHIFT_SU_DURATION 0
+#define BIT_MASK_SU_DURATION 0xffff
+#define BIT_SU_DURATION(x)                                                     \
+	(((x) & BIT_MASK_SU_DURATION) << BIT_SHIFT_SU_DURATION)
+#define BITS_SU_DURATION (BIT_MASK_SU_DURATION << BIT_SHIFT_SU_DURATION)
+#define BIT_CLEAR_SU_DURATION(x) ((x) & (~BITS_SU_DURATION))
+#define BIT_GET_SU_DURATION(x)                                                 \
+	(((x) >> BIT_SHIFT_SU_DURATION) & BIT_MASK_SU_DURATION)
+#define BIT_SET_SU_DURATION(x, v)                                              \
+	(BIT_CLEAR_SU_DURATION(x) | BIT_SU_DURATION(v))
+
+/* 2 REG_MU_DURATION				(Offset 0x14F2) */
+
+#define BIT_SHIFT_MU_DURATION 0
+#define BIT_MASK_MU_DURATION 0xffff
+#define BIT_MU_DURATION(x)                                                     \
+	(((x) & BIT_MASK_MU_DURATION) << BIT_SHIFT_MU_DURATION)
+#define BITS_MU_DURATION (BIT_MASK_MU_DURATION << BIT_SHIFT_MU_DURATION)
+#define BIT_CLEAR_MU_DURATION(x) ((x) & (~BITS_MU_DURATION))
+#define BIT_GET_MU_DURATION(x)                                                 \
+	(((x) >> BIT_SHIFT_MU_DURATION) & BIT_MASK_MU_DURATION)
+#define BIT_SET_MU_DURATION(x, v)                                              \
+	(BIT_CLEAR_MU_DURATION(x) | BIT_MU_DURATION(v))
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT)
+
+/* 2 REG_SWPS_CTRL				(Offset 0x14F4) */
+
+#define BIT_SHIFT_SWPS_RPT_LENGTH 8
+#define BIT_MASK_SWPS_RPT_LENGTH 0x7f
+#define BIT_SWPS_RPT_LENGTH(x)                                                 \
+	(((x) & BIT_MASK_SWPS_RPT_LENGTH) << BIT_SHIFT_SWPS_RPT_LENGTH)
+#define BITS_SWPS_RPT_LENGTH                                                   \
+	(BIT_MASK_SWPS_RPT_LENGTH << BIT_SHIFT_SWPS_RPT_LENGTH)
+#define BIT_CLEAR_SWPS_RPT_LENGTH(x) ((x) & (~BITS_SWPS_RPT_LENGTH))
+#define BIT_GET_SWPS_RPT_LENGTH(x)                                             \
+	(((x) >> BIT_SHIFT_SWPS_RPT_LENGTH) & BIT_MASK_SWPS_RPT_LENGTH)
+#define BIT_SET_SWPS_RPT_LENGTH(x, v)                                          \
+	(BIT_CLEAR_SWPS_RPT_LENGTH(x) | BIT_SWPS_RPT_LENGTH(v))
+
+#define BIT_SHIFT_MACID_SWPS_EN_SEL 2
+#define BIT_MASK_MACID_SWPS_EN_SEL 0x3
+#define BIT_MACID_SWPS_EN_SEL(x)                                               \
+	(((x) & BIT_MASK_MACID_SWPS_EN_SEL) << BIT_SHIFT_MACID_SWPS_EN_SEL)
+#define BITS_MACID_SWPS_EN_SEL                                                 \
+	(BIT_MASK_MACID_SWPS_EN_SEL << BIT_SHIFT_MACID_SWPS_EN_SEL)
+#define BIT_CLEAR_MACID_SWPS_EN_SEL(x) ((x) & (~BITS_MACID_SWPS_EN_SEL))
+#define BIT_GET_MACID_SWPS_EN_SEL(x)                                           \
+	(((x) >> BIT_SHIFT_MACID_SWPS_EN_SEL) & BIT_MASK_MACID_SWPS_EN_SEL)
+#define BIT_SET_MACID_SWPS_EN_SEL(x, v)                                        \
+	(BIT_CLEAR_MACID_SWPS_EN_SEL(x) | BIT_MACID_SWPS_EN_SEL(v))
+
+#define BIT_SWPS_MANUALL_POLLING BIT(1)
+#define BIT_SWPS_EN BIT(0)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT)
+
+/* 2 REG_HW_NDPA_RTY_LIMIT			(Offset 0x14F4) */
+
+#define BIT_SHIFT_HW_NDPA_RTY_LIMIT 0
+#define BIT_MASK_HW_NDPA_RTY_LIMIT 0xf
+#define BIT_HW_NDPA_RTY_LIMIT(x)                                               \
+	(((x) & BIT_MASK_HW_NDPA_RTY_LIMIT) << BIT_SHIFT_HW_NDPA_RTY_LIMIT)
+#define BITS_HW_NDPA_RTY_LIMIT                                                 \
+	(BIT_MASK_HW_NDPA_RTY_LIMIT << BIT_SHIFT_HW_NDPA_RTY_LIMIT)
+#define BIT_CLEAR_HW_NDPA_RTY_LIMIT(x) ((x) & (~BITS_HW_NDPA_RTY_LIMIT))
+#define BIT_GET_HW_NDPA_RTY_LIMIT(x)                                           \
+	(((x) >> BIT_SHIFT_HW_NDPA_RTY_LIMIT) & BIT_MASK_HW_NDPA_RTY_LIMIT)
+#define BIT_SET_HW_NDPA_RTY_LIMIT(x, v)                                        \
+	(BIT_CLEAR_HW_NDPA_RTY_LIMIT(x) | BIT_HW_NDPA_RTY_LIMIT(v))
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT)
+
+/* 2 REG_MACID_SWPS_EN			(Offset 0x14FC) */
+
+#define BIT_SHIFT_MACID_SWPS_EN 0
+#define BIT_MASK_MACID_SWPS_EN 0xffffffffL
+#define BIT_MACID_SWPS_EN(x)                                                   \
+	(((x) & BIT_MASK_MACID_SWPS_EN) << BIT_SHIFT_MACID_SWPS_EN)
+#define BITS_MACID_SWPS_EN (BIT_MASK_MACID_SWPS_EN << BIT_SHIFT_MACID_SWPS_EN)
+#define BIT_CLEAR_MACID_SWPS_EN(x) ((x) & (~BITS_MACID_SWPS_EN))
+#define BIT_GET_MACID_SWPS_EN(x)                                               \
+	(((x) >> BIT_SHIFT_MACID_SWPS_EN) & BIT_MASK_MACID_SWPS_EN)
+#define BIT_SET_MACID_SWPS_EN(x, v)                                            \
+	(BIT_CLEAR_MACID_SWPS_EN(x) | BIT_MACID_SWPS_EN(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_PORT_CTRL_SEL			(Offset 0x1500) */
+
+#define BIT_SHIFT_BCN_TIMER_SEL_FWRD_V1 4
+#define BIT_MASK_BCN_TIMER_SEL_FWRD_V1 0x7
+#define BIT_BCN_TIMER_SEL_FWRD_V1(x)                                           \
+	(((x) & BIT_MASK_BCN_TIMER_SEL_FWRD_V1)                                \
+	 << BIT_SHIFT_BCN_TIMER_SEL_FWRD_V1)
+#define BITS_BCN_TIMER_SEL_FWRD_V1                                             \
+	(BIT_MASK_BCN_TIMER_SEL_FWRD_V1 << BIT_SHIFT_BCN_TIMER_SEL_FWRD_V1)
+#define BIT_CLEAR_BCN_TIMER_SEL_FWRD_V1(x) ((x) & (~BITS_BCN_TIMER_SEL_FWRD_V1))
+#define BIT_GET_BCN_TIMER_SEL_FWRD_V1(x)                                       \
+	(((x) >> BIT_SHIFT_BCN_TIMER_SEL_FWRD_V1) &                            \
+	 BIT_MASK_BCN_TIMER_SEL_FWRD_V1)
+#define BIT_SET_BCN_TIMER_SEL_FWRD_V1(x, v)                                    \
+	(BIT_CLEAR_BCN_TIMER_SEL_FWRD_V1(x) | BIT_BCN_TIMER_SEL_FWRD_V1(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_CPUMGQ_TX_TIMER			(Offset 0x1500) */
+
+#define BIT_SHIFT_CPUMGQ_TX_TIMER_V1 0
+#define BIT_MASK_CPUMGQ_TX_TIMER_V1 0xffffffffL
+#define BIT_CPUMGQ_TX_TIMER_V1(x)                                              \
+	(((x) & BIT_MASK_CPUMGQ_TX_TIMER_V1) << BIT_SHIFT_CPUMGQ_TX_TIMER_V1)
+#define BITS_CPUMGQ_TX_TIMER_V1                                                \
+	(BIT_MASK_CPUMGQ_TX_TIMER_V1 << BIT_SHIFT_CPUMGQ_TX_TIMER_V1)
+#define BIT_CLEAR_CPUMGQ_TX_TIMER_V1(x) ((x) & (~BITS_CPUMGQ_TX_TIMER_V1))
+#define BIT_GET_CPUMGQ_TX_TIMER_V1(x)                                          \
+	(((x) >> BIT_SHIFT_CPUMGQ_TX_TIMER_V1) & BIT_MASK_CPUMGQ_TX_TIMER_V1)
+#define BIT_SET_CPUMGQ_TX_TIMER_V1(x, v)                                       \
+	(BIT_CLEAR_CPUMGQ_TX_TIMER_V1(x) | BIT_CPUMGQ_TX_TIMER_V1(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_PORT_CTRL_SEL			(Offset 0x1500) */
+
+#define BIT_SHIFT_PORT_CTRL_SEL 0
+#define BIT_MASK_PORT_CTRL_SEL 0x7
+#define BIT_PORT_CTRL_SEL(x)                                                   \
+	(((x) & BIT_MASK_PORT_CTRL_SEL) << BIT_SHIFT_PORT_CTRL_SEL)
+#define BITS_PORT_CTRL_SEL (BIT_MASK_PORT_CTRL_SEL << BIT_SHIFT_PORT_CTRL_SEL)
+#define BIT_CLEAR_PORT_CTRL_SEL(x) ((x) & (~BITS_PORT_CTRL_SEL))
+#define BIT_GET_PORT_CTRL_SEL(x)                                               \
+	(((x) >> BIT_SHIFT_PORT_CTRL_SEL) & BIT_MASK_PORT_CTRL_SEL)
+#define BIT_SET_PORT_CTRL_SEL(x, v)                                            \
+	(BIT_CLEAR_PORT_CTRL_SEL(x) | BIT_PORT_CTRL_SEL(v))
+
+/* 2 REG_PORT_CTRL_CFG			(Offset 0x1501) */
+
+#define BIT_BCNERR_CNT_EN_V1 BIT(11)
+#define BIT_DIS_TRX_CAL_BCN_V1 BIT(10)
+#define BIT_DIS_TX_CAL_TBTT_V1 BIT(9)
+#define BIT_BCN_AGGRESSION_V1 BIT(8)
+#define BIT_TSFTR_RST_V1 BIT(7)
+#define BIT_EN_TXBCN_RPT_V1 BIT(5)
+#define BIT_EN_PORT_FUNCTION BIT(3)
+#define BIT_EN_RXBCN_RPT BIT(2)
+
+/* 2 REG_TBTT_PROHIBIT_CFG			(Offset 0x1504) */
+
+#define BIT_MASK_PROHIBIT BIT(23)
+
+#define BIT_SHIFT_TBTT_HOLD_TIME 8
+#define BIT_MASK_TBTT_HOLD_TIME 0xfff
+#define BIT_TBTT_HOLD_TIME(x)                                                  \
+	(((x) & BIT_MASK_TBTT_HOLD_TIME) << BIT_SHIFT_TBTT_HOLD_TIME)
+#define BITS_TBTT_HOLD_TIME                                                    \
+	(BIT_MASK_TBTT_HOLD_TIME << BIT_SHIFT_TBTT_HOLD_TIME)
+#define BIT_CLEAR_TBTT_HOLD_TIME(x) ((x) & (~BITS_TBTT_HOLD_TIME))
+#define BIT_GET_TBTT_HOLD_TIME(x)                                              \
+	(((x) >> BIT_SHIFT_TBTT_HOLD_TIME) & BIT_MASK_TBTT_HOLD_TIME)
+#define BIT_SET_TBTT_HOLD_TIME(x, v)                                           \
+	(BIT_CLEAR_TBTT_HOLD_TIME(x) | BIT_TBTT_HOLD_TIME(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_PS_TIMER_A				(Offset 0x1504) */
+
+#define BIT_SHIFT_PS_TIMER_A_V1 0
+#define BIT_MASK_PS_TIMER_A_V1 0xffffffffL
+#define BIT_PS_TIMER_A_V1(x)                                                   \
+	(((x) & BIT_MASK_PS_TIMER_A_V1) << BIT_SHIFT_PS_TIMER_A_V1)
+#define BITS_PS_TIMER_A_V1 (BIT_MASK_PS_TIMER_A_V1 << BIT_SHIFT_PS_TIMER_A_V1)
+#define BIT_CLEAR_PS_TIMER_A_V1(x) ((x) & (~BITS_PS_TIMER_A_V1))
+#define BIT_GET_PS_TIMER_A_V1(x)                                               \
+	(((x) >> BIT_SHIFT_PS_TIMER_A_V1) & BIT_MASK_PS_TIMER_A_V1)
+#define BIT_SET_PS_TIMER_A_V1(x, v)                                            \
+	(BIT_CLEAR_PS_TIMER_A_V1(x) | BIT_PS_TIMER_A_V1(v))
+
+/* 2 REG_PS_TIMER_B				(Offset 0x1508) */
+
+#define BIT_SHIFT_PS_TIMER_B_V1 0
+#define BIT_MASK_PS_TIMER_B_V1 0xffffffffL
+#define BIT_PS_TIMER_B_V1(x)                                                   \
+	(((x) & BIT_MASK_PS_TIMER_B_V1) << BIT_SHIFT_PS_TIMER_B_V1)
+#define BITS_PS_TIMER_B_V1 (BIT_MASK_PS_TIMER_B_V1 << BIT_SHIFT_PS_TIMER_B_V1)
+#define BIT_CLEAR_PS_TIMER_B_V1(x) ((x) & (~BITS_PS_TIMER_B_V1))
+#define BIT_GET_PS_TIMER_B_V1(x)                                               \
+	(((x) >> BIT_SHIFT_PS_TIMER_B_V1) & BIT_MASK_PS_TIMER_B_V1)
+#define BIT_SET_PS_TIMER_B_V1(x, v)                                            \
+	(BIT_CLEAR_PS_TIMER_B_V1(x) | BIT_PS_TIMER_B_V1(v))
+
+/* 2 REG_PS_TIMER_C				(Offset 0x150C) */
+
+#define BIT_SHIFT_PS_TIMER_C_V1 0
+#define BIT_MASK_PS_TIMER_C_V1 0xffffffffL
+#define BIT_PS_TIMER_C_V1(x)                                                   \
+	(((x) & BIT_MASK_PS_TIMER_C_V1) << BIT_SHIFT_PS_TIMER_C_V1)
+#define BITS_PS_TIMER_C_V1 (BIT_MASK_PS_TIMER_C_V1 << BIT_SHIFT_PS_TIMER_C_V1)
+#define BIT_CLEAR_PS_TIMER_C_V1(x) ((x) & (~BITS_PS_TIMER_C_V1))
+#define BIT_GET_PS_TIMER_C_V1(x)                                               \
+	(((x) >> BIT_SHIFT_PS_TIMER_C_V1) & BIT_MASK_PS_TIMER_C_V1)
+#define BIT_SET_PS_TIMER_C_V1(x, v)                                            \
+	(BIT_CLEAR_PS_TIMER_C_V1(x) | BIT_PS_TIMER_C_V1(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_TSFTR_SYNC_OFFSET_CFG		(Offset 0x150C) */
+
+#define BIT_SHIFT_TSFTR_SNC_OFFSET_V1 0
+#define BIT_MASK_TSFTR_SNC_OFFSET_V1 0xffffff
+#define BIT_TSFTR_SNC_OFFSET_V1(x)                                             \
+	(((x) & BIT_MASK_TSFTR_SNC_OFFSET_V1) << BIT_SHIFT_TSFTR_SNC_OFFSET_V1)
+#define BITS_TSFTR_SNC_OFFSET_V1                                               \
+	(BIT_MASK_TSFTR_SNC_OFFSET_V1 << BIT_SHIFT_TSFTR_SNC_OFFSET_V1)
+#define BIT_CLEAR_TSFTR_SNC_OFFSET_V1(x) ((x) & (~BITS_TSFTR_SNC_OFFSET_V1))
+#define BIT_GET_TSFTR_SNC_OFFSET_V1(x)                                         \
+	(((x) >> BIT_SHIFT_TSFTR_SNC_OFFSET_V1) & BIT_MASK_TSFTR_SNC_OFFSET_V1)
+#define BIT_SET_TSFTR_SNC_OFFSET_V1(x, v)                                      \
+	(BIT_CLEAR_TSFTR_SNC_OFFSET_V1(x) | BIT_TSFTR_SNC_OFFSET_V1(v))
+
+/* 2 REG_TSFTR_SYNC_CTRL_CFG			(Offset 0x150F) */
+
+#define BIT_SYNC_TSF_NOW_V1 BIT(5)
+#define BIT_SYNC_TSF_ONCE BIT(4)
+#define BIT_SYNC_TSF_AUTO BIT(3)
+
+#define BIT_SHIFT_SYNC_PORT_SEL 0
+#define BIT_MASK_SYNC_PORT_SEL 0x7
+#define BIT_SYNC_PORT_SEL(x)                                                   \
+	(((x) & BIT_MASK_SYNC_PORT_SEL) << BIT_SHIFT_SYNC_PORT_SEL)
+#define BITS_SYNC_PORT_SEL (BIT_MASK_SYNC_PORT_SEL << BIT_SHIFT_SYNC_PORT_SEL)
+#define BIT_CLEAR_SYNC_PORT_SEL(x) ((x) & (~BITS_SYNC_PORT_SEL))
+#define BIT_GET_SYNC_PORT_SEL(x)                                               \
+	(((x) >> BIT_SHIFT_SYNC_PORT_SEL) & BIT_MASK_SYNC_PORT_SEL)
+#define BIT_SET_SYNC_PORT_SEL(x, v)                                            \
+	(BIT_CLEAR_SYNC_PORT_SEL(x) | BIT_SYNC_PORT_SEL(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_PS_TIMER_ABC_CPUMGQ_TIMER_CRTL	(Offset 0x1510) */
+
+#define BIT_CPUMGQ_TIMER_EN BIT(31)
+#define BIT_CPUMGQ_TX_EN BIT(28)
+
+#define BIT_SHIFT_CPUMGQ_TIMER_TSF_SEL 24
+#define BIT_MASK_CPUMGQ_TIMER_TSF_SEL 0x7
+#define BIT_CPUMGQ_TIMER_TSF_SEL(x)                                            \
+	(((x) & BIT_MASK_CPUMGQ_TIMER_TSF_SEL)                                 \
+	 << BIT_SHIFT_CPUMGQ_TIMER_TSF_SEL)
+#define BITS_CPUMGQ_TIMER_TSF_SEL                                              \
+	(BIT_MASK_CPUMGQ_TIMER_TSF_SEL << BIT_SHIFT_CPUMGQ_TIMER_TSF_SEL)
+#define BIT_CLEAR_CPUMGQ_TIMER_TSF_SEL(x) ((x) & (~BITS_CPUMGQ_TIMER_TSF_SEL))
+#define BIT_GET_CPUMGQ_TIMER_TSF_SEL(x)                                        \
+	(((x) >> BIT_SHIFT_CPUMGQ_TIMER_TSF_SEL) &                             \
+	 BIT_MASK_CPUMGQ_TIMER_TSF_SEL)
+#define BIT_SET_CPUMGQ_TIMER_TSF_SEL(x, v)                                     \
+	(BIT_CLEAR_CPUMGQ_TIMER_TSF_SEL(x) | BIT_CPUMGQ_TIMER_TSF_SEL(v))
+
+#define BIT_PS_TIMER_C_EN BIT(23)
+
+#define BIT_SHIFT_PS_TIMER_C_TSF_SEL 16
+#define BIT_MASK_PS_TIMER_C_TSF_SEL 0x7
+#define BIT_PS_TIMER_C_TSF_SEL(x)                                              \
+	(((x) & BIT_MASK_PS_TIMER_C_TSF_SEL) << BIT_SHIFT_PS_TIMER_C_TSF_SEL)
+#define BITS_PS_TIMER_C_TSF_SEL                                                \
+	(BIT_MASK_PS_TIMER_C_TSF_SEL << BIT_SHIFT_PS_TIMER_C_TSF_SEL)
+#define BIT_CLEAR_PS_TIMER_C_TSF_SEL(x) ((x) & (~BITS_PS_TIMER_C_TSF_SEL))
+#define BIT_GET_PS_TIMER_C_TSF_SEL(x)                                          \
+	(((x) >> BIT_SHIFT_PS_TIMER_C_TSF_SEL) & BIT_MASK_PS_TIMER_C_TSF_SEL)
+#define BIT_SET_PS_TIMER_C_TSF_SEL(x, v)                                       \
+	(BIT_CLEAR_PS_TIMER_C_TSF_SEL(x) | BIT_PS_TIMER_C_TSF_SEL(v))
+
+#define BIT_PS_TIMER_B_EN BIT(15)
+
+#define BIT_SHIFT_PS_TIMER_B_TSF_SEL 8
+#define BIT_MASK_PS_TIMER_B_TSF_SEL 0x7
+#define BIT_PS_TIMER_B_TSF_SEL(x)                                              \
+	(((x) & BIT_MASK_PS_TIMER_B_TSF_SEL) << BIT_SHIFT_PS_TIMER_B_TSF_SEL)
+#define BITS_PS_TIMER_B_TSF_SEL                                                \
+	(BIT_MASK_PS_TIMER_B_TSF_SEL << BIT_SHIFT_PS_TIMER_B_TSF_SEL)
+#define BIT_CLEAR_PS_TIMER_B_TSF_SEL(x) ((x) & (~BITS_PS_TIMER_B_TSF_SEL))
+#define BIT_GET_PS_TIMER_B_TSF_SEL(x)                                          \
+	(((x) >> BIT_SHIFT_PS_TIMER_B_TSF_SEL) & BIT_MASK_PS_TIMER_B_TSF_SEL)
+#define BIT_SET_PS_TIMER_B_TSF_SEL(x, v)                                       \
+	(BIT_CLEAR_PS_TIMER_B_TSF_SEL(x) | BIT_PS_TIMER_B_TSF_SEL(v))
+
+#define BIT_PS_TIMER_A_EN BIT(7)
+
+#define BIT_SHIFT_PS_TIMER_A_TSF_SEL 0
+#define BIT_MASK_PS_TIMER_A_TSF_SEL 0x7
+#define BIT_PS_TIMER_A_TSF_SEL(x)                                              \
+	(((x) & BIT_MASK_PS_TIMER_A_TSF_SEL) << BIT_SHIFT_PS_TIMER_A_TSF_SEL)
+#define BITS_PS_TIMER_A_TSF_SEL                                                \
+	(BIT_MASK_PS_TIMER_A_TSF_SEL << BIT_SHIFT_PS_TIMER_A_TSF_SEL)
+#define BIT_CLEAR_PS_TIMER_A_TSF_SEL(x) ((x) & (~BITS_PS_TIMER_A_TSF_SEL))
+#define BIT_GET_PS_TIMER_A_TSF_SEL(x)                                          \
+	(((x) >> BIT_SHIFT_PS_TIMER_A_TSF_SEL) & BIT_MASK_PS_TIMER_A_TSF_SEL)
+#define BIT_SET_PS_TIMER_A_TSF_SEL(x, v)                                       \
+	(BIT_CLEAR_PS_TIMER_A_TSF_SEL(x) | BIT_PS_TIMER_A_TSF_SEL(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_BCN_SPACE_CFG			(Offset 0x1510) */
+
+#define BIT_SHIFT_BCN_SPACE 0
+#define BIT_MASK_BCN_SPACE 0xffff
+#define BIT_BCN_SPACE(x) (((x) & BIT_MASK_BCN_SPACE) << BIT_SHIFT_BCN_SPACE)
+#define BITS_BCN_SPACE (BIT_MASK_BCN_SPACE << BIT_SHIFT_BCN_SPACE)
+#define BIT_CLEAR_BCN_SPACE(x) ((x) & (~BITS_BCN_SPACE))
+#define BIT_GET_BCN_SPACE(x) (((x) >> BIT_SHIFT_BCN_SPACE) & BIT_MASK_BCN_SPACE)
+#define BIT_SET_BCN_SPACE(x, v) (BIT_CLEAR_BCN_SPACE(x) | BIT_BCN_SPACE(v))
+
+/* 2 REG_EARLY_INT_ADJUST_CFG		(Offset 0x1512) */
+
+#define BIT_SHIFT_EARLY_INT_ADJUST 0
+#define BIT_MASK_EARLY_INT_ADJUST 0xffff
+#define BIT_EARLY_INT_ADJUST(x)                                                \
+	(((x) & BIT_MASK_EARLY_INT_ADJUST) << BIT_SHIFT_EARLY_INT_ADJUST)
+#define BITS_EARLY_INT_ADJUST                                                  \
+	(BIT_MASK_EARLY_INT_ADJUST << BIT_SHIFT_EARLY_INT_ADJUST)
+#define BIT_CLEAR_EARLY_INT_ADJUST(x) ((x) & (~BITS_EARLY_INT_ADJUST))
+#define BIT_GET_EARLY_INT_ADJUST(x)                                            \
+	(((x) >> BIT_SHIFT_EARLY_INT_ADJUST) & BIT_MASK_EARLY_INT_ADJUST)
+#define BIT_SET_EARLY_INT_ADJUST(x, v)                                         \
+	(BIT_CLEAR_EARLY_INT_ADJUST(x) | BIT_EARLY_INT_ADJUST(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_CPUMGQ_TX_TIMER_EARLY		(Offset 0x1514) */
+
+#define BIT_SHIFT_CPUMGQ_TX_TIMER_EARLY 0
+#define BIT_MASK_CPUMGQ_TX_TIMER_EARLY 0xff
+#define BIT_CPUMGQ_TX_TIMER_EARLY(x)                                           \
+	(((x) & BIT_MASK_CPUMGQ_TX_TIMER_EARLY)                                \
+	 << BIT_SHIFT_CPUMGQ_TX_TIMER_EARLY)
+#define BITS_CPUMGQ_TX_TIMER_EARLY                                             \
+	(BIT_MASK_CPUMGQ_TX_TIMER_EARLY << BIT_SHIFT_CPUMGQ_TX_TIMER_EARLY)
+#define BIT_CLEAR_CPUMGQ_TX_TIMER_EARLY(x) ((x) & (~BITS_CPUMGQ_TX_TIMER_EARLY))
+#define BIT_GET_CPUMGQ_TX_TIMER_EARLY(x)                                       \
+	(((x) >> BIT_SHIFT_CPUMGQ_TX_TIMER_EARLY) &                            \
+	 BIT_MASK_CPUMGQ_TX_TIMER_EARLY)
+#define BIT_SET_CPUMGQ_TX_TIMER_EARLY(x, v)                                    \
+	(BIT_CLEAR_CPUMGQ_TX_TIMER_EARLY(x) | BIT_CPUMGQ_TX_TIMER_EARLY(v))
+
+/* 2 REG_PS_TIMER_A_EARLY			(Offset 0x1515) */
+
+#define BIT_SHIFT_PS_TIMER_A_EARLY 0
+#define BIT_MASK_PS_TIMER_A_EARLY 0xff
+#define BIT_PS_TIMER_A_EARLY(x)                                                \
+	(((x) & BIT_MASK_PS_TIMER_A_EARLY) << BIT_SHIFT_PS_TIMER_A_EARLY)
+#define BITS_PS_TIMER_A_EARLY                                                  \
+	(BIT_MASK_PS_TIMER_A_EARLY << BIT_SHIFT_PS_TIMER_A_EARLY)
+#define BIT_CLEAR_PS_TIMER_A_EARLY(x) ((x) & (~BITS_PS_TIMER_A_EARLY))
+#define BIT_GET_PS_TIMER_A_EARLY(x)                                            \
+	(((x) >> BIT_SHIFT_PS_TIMER_A_EARLY) & BIT_MASK_PS_TIMER_A_EARLY)
+#define BIT_SET_PS_TIMER_A_EARLY(x, v)                                         \
+	(BIT_CLEAR_PS_TIMER_A_EARLY(x) | BIT_PS_TIMER_A_EARLY(v))
+
+/* 2 REG_PS_TIMER_B_EARLY			(Offset 0x1516) */
+
+#define BIT_SHIFT_PS_TIMER_B_EARLY 0
+#define BIT_MASK_PS_TIMER_B_EARLY 0xff
+#define BIT_PS_TIMER_B_EARLY(x)                                                \
+	(((x) & BIT_MASK_PS_TIMER_B_EARLY) << BIT_SHIFT_PS_TIMER_B_EARLY)
+#define BITS_PS_TIMER_B_EARLY                                                  \
+	(BIT_MASK_PS_TIMER_B_EARLY << BIT_SHIFT_PS_TIMER_B_EARLY)
+#define BIT_CLEAR_PS_TIMER_B_EARLY(x) ((x) & (~BITS_PS_TIMER_B_EARLY))
+#define BIT_GET_PS_TIMER_B_EARLY(x)                                            \
+	(((x) >> BIT_SHIFT_PS_TIMER_B_EARLY) & BIT_MASK_PS_TIMER_B_EARLY)
+#define BIT_SET_PS_TIMER_B_EARLY(x, v)                                         \
+	(BIT_CLEAR_PS_TIMER_B_EARLY(x) | BIT_PS_TIMER_B_EARLY(v))
+
+/* 2 REG_PS_TIMER_C_EARLY			(Offset 0x1517) */
+
+#define BIT_SHIFT_PS_TIMER_C_EARLY 0
+#define BIT_MASK_PS_TIMER_C_EARLY 0xff
+#define BIT_PS_TIMER_C_EARLY(x)                                                \
+	(((x) & BIT_MASK_PS_TIMER_C_EARLY) << BIT_SHIFT_PS_TIMER_C_EARLY)
+#define BITS_PS_TIMER_C_EARLY                                                  \
+	(BIT_MASK_PS_TIMER_C_EARLY << BIT_SHIFT_PS_TIMER_C_EARLY)
+#define BIT_CLEAR_PS_TIMER_C_EARLY(x) ((x) & (~BITS_PS_TIMER_C_EARLY))
+#define BIT_GET_PS_TIMER_C_EARLY(x)                                            \
+	(((x) >> BIT_SHIFT_PS_TIMER_C_EARLY) & BIT_MASK_PS_TIMER_C_EARLY)
+#define BIT_SET_PS_TIMER_C_EARLY(x, v)                                         \
+	(BIT_CLEAR_PS_TIMER_C_EARLY(x) | BIT_PS_TIMER_C_EARLY(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_CPUMGQ_PARAMETER			(Offset 0x1518) */
+
+#define BIT_STOP_CPUMGQ BIT(16)
+
+#define BIT_SHIFT_CPUMGQ_PARAMETER 0
+#define BIT_MASK_CPUMGQ_PARAMETER 0xffff
+#define BIT_CPUMGQ_PARAMETER(x)                                                \
+	(((x) & BIT_MASK_CPUMGQ_PARAMETER) << BIT_SHIFT_CPUMGQ_PARAMETER)
+#define BITS_CPUMGQ_PARAMETER                                                  \
+	(BIT_MASK_CPUMGQ_PARAMETER << BIT_SHIFT_CPUMGQ_PARAMETER)
+#define BIT_CLEAR_CPUMGQ_PARAMETER(x) ((x) & (~BITS_CPUMGQ_PARAMETER))
+#define BIT_GET_CPUMGQ_PARAMETER(x)                                            \
+	(((x) >> BIT_SHIFT_CPUMGQ_PARAMETER) & BIT_MASK_CPUMGQ_PARAMETER)
+#define BIT_SET_CPUMGQ_PARAMETER(x, v)                                         \
+	(BIT_CLEAR_CPUMGQ_PARAMETER(x) | BIT_CPUMGQ_PARAMETER(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_SW_TBTT_TSF_INFO			(Offset 0x151C) */
+
+#define BIT_SHIFT_SW_TBTT_TSF_INFO 0
+#define BIT_MASK_SW_TBTT_TSF_INFO 0xffffffffL
+#define BIT_SW_TBTT_TSF_INFO(x)                                                \
+	(((x) & BIT_MASK_SW_TBTT_TSF_INFO) << BIT_SHIFT_SW_TBTT_TSF_INFO)
+#define BITS_SW_TBTT_TSF_INFO                                                  \
+	(BIT_MASK_SW_TBTT_TSF_INFO << BIT_SHIFT_SW_TBTT_TSF_INFO)
+#define BIT_CLEAR_SW_TBTT_TSF_INFO(x) ((x) & (~BITS_SW_TBTT_TSF_INFO))
+#define BIT_GET_SW_TBTT_TSF_INFO(x)                                            \
+	(((x) >> BIT_SHIFT_SW_TBTT_TSF_INFO) & BIT_MASK_SW_TBTT_TSF_INFO)
+#define BIT_SET_SW_TBTT_TSF_INFO(x, v)                                         \
+	(BIT_CLEAR_SW_TBTT_TSF_INFO(x) | BIT_SW_TBTT_TSF_INFO(v))
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_TSF_SYNC_ADJ			(Offset 0x1520) */
+
+#define BIT_SHIFT_R_P0_TSFT_ADJ_VAL 16
+#define BIT_MASK_R_P0_TSFT_ADJ_VAL 0xffff
+#define BIT_R_P0_TSFT_ADJ_VAL(x)                                               \
+	(((x) & BIT_MASK_R_P0_TSFT_ADJ_VAL) << BIT_SHIFT_R_P0_TSFT_ADJ_VAL)
+#define BITS_R_P0_TSFT_ADJ_VAL                                                 \
+	(BIT_MASK_R_P0_TSFT_ADJ_VAL << BIT_SHIFT_R_P0_TSFT_ADJ_VAL)
+#define BIT_CLEAR_R_P0_TSFT_ADJ_VAL(x) ((x) & (~BITS_R_P0_TSFT_ADJ_VAL))
+#define BIT_GET_R_P0_TSFT_ADJ_VAL(x)                                           \
+	(((x) >> BIT_SHIFT_R_P0_TSFT_ADJ_VAL) & BIT_MASK_R_P0_TSFT_ADJ_VAL)
+#define BIT_SET_R_P0_TSFT_ADJ_VAL(x, v)                                        \
+	(BIT_CLEAR_R_P0_TSFT_ADJ_VAL(x) | BIT_R_P0_TSFT_ADJ_VAL(v))
+
+#define BIT_R_X_COMP_Y_OVER BIT(8)
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+/* 2 REG_TSF_SYN_CTRL0			(Offset 0x1520) */
+
+#define BIT_TSF_SYNC_COMPARE_POLLING BIT(7)
+#define BIT_TSF_SYNC_POLLING BIT(6)
+
+#define BIT_SHIFT_TSF_SYNC_DUT 3
+#define BIT_MASK_TSF_SYNC_DUT 0x7
+#define BIT_TSF_SYNC_DUT(x)                                                    \
+	(((x) & BIT_MASK_TSF_SYNC_DUT) << BIT_SHIFT_TSF_SYNC_DUT)
+#define BITS_TSF_SYNC_DUT (BIT_MASK_TSF_SYNC_DUT << BIT_SHIFT_TSF_SYNC_DUT)
+#define BIT_CLEAR_TSF_SYNC_DUT(x) ((x) & (~BITS_TSF_SYNC_DUT))
+#define BIT_GET_TSF_SYNC_DUT(x)                                                \
+	(((x) >> BIT_SHIFT_TSF_SYNC_DUT) & BIT_MASK_TSF_SYNC_DUT)
+#define BIT_SET_TSF_SYNC_DUT(x, v)                                             \
+	(BIT_CLEAR_TSF_SYNC_DUT(x) | BIT_TSF_SYNC_DUT(v))
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_TSF_SYNC_ADJ			(Offset 0x1520) */
+
+#define BIT_SHIFT_R_X_SYNC_SEL 3
+#define BIT_MASK_R_X_SYNC_SEL 0x7
+#define BIT_R_X_SYNC_SEL(x)                                                    \
+	(((x) & BIT_MASK_R_X_SYNC_SEL) << BIT_SHIFT_R_X_SYNC_SEL)
+#define BITS_R_X_SYNC_SEL (BIT_MASK_R_X_SYNC_SEL << BIT_SHIFT_R_X_SYNC_SEL)
+#define BIT_CLEAR_R_X_SYNC_SEL(x) ((x) & (~BITS_R_X_SYNC_SEL))
+#define BIT_GET_R_X_SYNC_SEL(x)                                                \
+	(((x) >> BIT_SHIFT_R_X_SYNC_SEL) & BIT_MASK_R_X_SYNC_SEL)
+#define BIT_SET_R_X_SYNC_SEL(x, v)                                             \
+	(BIT_CLEAR_R_X_SYNC_SEL(x) | BIT_R_X_SYNC_SEL(v))
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+/* 2 REG_TSF_SYN_CTRL0			(Offset 0x1520) */
+
+#define BIT_SHIFT_TSF_SYNC_SOURCE 0
+#define BIT_MASK_TSF_SYNC_SOURCE 0x7
+#define BIT_TSF_SYNC_SOURCE(x)                                                 \
+	(((x) & BIT_MASK_TSF_SYNC_SOURCE) << BIT_SHIFT_TSF_SYNC_SOURCE)
+#define BITS_TSF_SYNC_SOURCE                                                   \
+	(BIT_MASK_TSF_SYNC_SOURCE << BIT_SHIFT_TSF_SYNC_SOURCE)
+#define BIT_CLEAR_TSF_SYNC_SOURCE(x) ((x) & (~BITS_TSF_SYNC_SOURCE))
+#define BIT_GET_TSF_SYNC_SOURCE(x)                                             \
+	(((x) >> BIT_SHIFT_TSF_SYNC_SOURCE) & BIT_MASK_TSF_SYNC_SOURCE)
+#define BIT_SET_TSF_SYNC_SOURCE(x, v)                                          \
+	(BIT_CLEAR_TSF_SYNC_SOURCE(x) | BIT_TSF_SYNC_SOURCE(v))
+
+#define BIT_TSF_SYNC_SIGNAL BIT(0)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_TSF_SYNC_ADJ			(Offset 0x1520) */
+
+#define BIT_SHIFT_R_SYNC_Y_SEL 0
+#define BIT_MASK_R_SYNC_Y_SEL 0x7
+#define BIT_R_SYNC_Y_SEL(x)                                                    \
+	(((x) & BIT_MASK_R_SYNC_Y_SEL) << BIT_SHIFT_R_SYNC_Y_SEL)
+#define BITS_R_SYNC_Y_SEL (BIT_MASK_R_SYNC_Y_SEL << BIT_SHIFT_R_SYNC_Y_SEL)
+#define BIT_CLEAR_R_SYNC_Y_SEL(x) ((x) & (~BITS_R_SYNC_Y_SEL))
+#define BIT_GET_R_SYNC_Y_SEL(x)                                                \
+	(((x) >> BIT_SHIFT_R_SYNC_Y_SEL) & BIT_MASK_R_SYNC_Y_SEL)
+#define BIT_SET_R_SYNC_Y_SEL(x, v)                                             \
+	(BIT_CLEAR_R_SYNC_Y_SEL(x) | BIT_R_SYNC_Y_SEL(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_TSFTR_LOW				(Offset 0x1520) */
+
+#define BIT_SHIFT_TSF_TIMER_LOW 0
+#define BIT_MASK_TSF_TIMER_LOW 0xffffffffL
+#define BIT_TSF_TIMER_LOW(x)                                                   \
+	(((x) & BIT_MASK_TSF_TIMER_LOW) << BIT_SHIFT_TSF_TIMER_LOW)
+#define BITS_TSF_TIMER_LOW (BIT_MASK_TSF_TIMER_LOW << BIT_SHIFT_TSF_TIMER_LOW)
+#define BIT_CLEAR_TSF_TIMER_LOW(x) ((x) & (~BITS_TSF_TIMER_LOW))
+#define BIT_GET_TSF_TIMER_LOW(x)                                               \
+	(((x) >> BIT_SHIFT_TSF_TIMER_LOW) & BIT_MASK_TSF_TIMER_LOW)
+#define BIT_SET_TSF_TIMER_LOW(x, v)                                            \
+	(BIT_CLEAR_TSF_TIMER_LOW(x) | BIT_TSF_TIMER_LOW(v))
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+/* 2 REG_TSF_SYN_OFFSET0			(Offset 0x1522) */
+
+#define BIT_SHIFT_TSF_SYNC_INTERVAL_PORT0 0
+#define BIT_MASK_TSF_SYNC_INTERVAL_PORT0 0xffff
+#define BIT_TSF_SYNC_INTERVAL_PORT0(x)                                         \
+	(((x) & BIT_MASK_TSF_SYNC_INTERVAL_PORT0)                              \
+	 << BIT_SHIFT_TSF_SYNC_INTERVAL_PORT0)
+#define BITS_TSF_SYNC_INTERVAL_PORT0                                           \
+	(BIT_MASK_TSF_SYNC_INTERVAL_PORT0 << BIT_SHIFT_TSF_SYNC_INTERVAL_PORT0)
+#define BIT_CLEAR_TSF_SYNC_INTERVAL_PORT0(x)                                   \
+	((x) & (~BITS_TSF_SYNC_INTERVAL_PORT0))
+#define BIT_GET_TSF_SYNC_INTERVAL_PORT0(x)                                     \
+	(((x) >> BIT_SHIFT_TSF_SYNC_INTERVAL_PORT0) &                          \
+	 BIT_MASK_TSF_SYNC_INTERVAL_PORT0)
+#define BIT_SET_TSF_SYNC_INTERVAL_PORT0(x, v)                                  \
+	(BIT_CLEAR_TSF_SYNC_INTERVAL_PORT0(x) | BIT_TSF_SYNC_INTERVAL_PORT0(v))
+
+/* 2 REG_TSF_SYN_OFFSET1			(Offset 0x1524) */
+
+#define BIT_SHIFT_TSF_SYNC_INTERVAL_CLI1 16
+#define BIT_MASK_TSF_SYNC_INTERVAL_CLI1 0xffff
+#define BIT_TSF_SYNC_INTERVAL_CLI1(x)                                          \
+	(((x) & BIT_MASK_TSF_SYNC_INTERVAL_CLI1)                               \
+	 << BIT_SHIFT_TSF_SYNC_INTERVAL_CLI1)
+#define BITS_TSF_SYNC_INTERVAL_CLI1                                            \
+	(BIT_MASK_TSF_SYNC_INTERVAL_CLI1 << BIT_SHIFT_TSF_SYNC_INTERVAL_CLI1)
+#define BIT_CLEAR_TSF_SYNC_INTERVAL_CLI1(x)                                    \
+	((x) & (~BITS_TSF_SYNC_INTERVAL_CLI1))
+#define BIT_GET_TSF_SYNC_INTERVAL_CLI1(x)                                      \
+	(((x) >> BIT_SHIFT_TSF_SYNC_INTERVAL_CLI1) &                           \
+	 BIT_MASK_TSF_SYNC_INTERVAL_CLI1)
+#define BIT_SET_TSF_SYNC_INTERVAL_CLI1(x, v)                                   \
+	(BIT_CLEAR_TSF_SYNC_INTERVAL_CLI1(x) | BIT_TSF_SYNC_INTERVAL_CLI1(v))
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_TSF_ADJ_VLAUE			(Offset 0x1524) */
+
+#define BIT_SHIFT_R_CLI1_TSFT_ADJ_VAL 16
+#define BIT_MASK_R_CLI1_TSFT_ADJ_VAL 0xffff
+#define BIT_R_CLI1_TSFT_ADJ_VAL(x)                                             \
+	(((x) & BIT_MASK_R_CLI1_TSFT_ADJ_VAL) << BIT_SHIFT_R_CLI1_TSFT_ADJ_VAL)
+#define BITS_R_CLI1_TSFT_ADJ_VAL                                               \
+	(BIT_MASK_R_CLI1_TSFT_ADJ_VAL << BIT_SHIFT_R_CLI1_TSFT_ADJ_VAL)
+#define BIT_CLEAR_R_CLI1_TSFT_ADJ_VAL(x) ((x) & (~BITS_R_CLI1_TSFT_ADJ_VAL))
+#define BIT_GET_R_CLI1_TSFT_ADJ_VAL(x)                                         \
+	(((x) >> BIT_SHIFT_R_CLI1_TSFT_ADJ_VAL) & BIT_MASK_R_CLI1_TSFT_ADJ_VAL)
+#define BIT_SET_R_CLI1_TSFT_ADJ_VAL(x, v)                                      \
+	(BIT_CLEAR_R_CLI1_TSFT_ADJ_VAL(x) | BIT_R_CLI1_TSFT_ADJ_VAL(v))
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+/* 2 REG_TSF_SYN_OFFSET1			(Offset 0x1524) */
+
+#define BIT_SHIFT_TSF_SYNC_INTERVAL_CLI0 0
+#define BIT_MASK_TSF_SYNC_INTERVAL_CLI0 0xffff
+#define BIT_TSF_SYNC_INTERVAL_CLI0(x)                                          \
+	(((x) & BIT_MASK_TSF_SYNC_INTERVAL_CLI0)                               \
+	 << BIT_SHIFT_TSF_SYNC_INTERVAL_CLI0)
+#define BITS_TSF_SYNC_INTERVAL_CLI0                                            \
+	(BIT_MASK_TSF_SYNC_INTERVAL_CLI0 << BIT_SHIFT_TSF_SYNC_INTERVAL_CLI0)
+#define BIT_CLEAR_TSF_SYNC_INTERVAL_CLI0(x)                                    \
+	((x) & (~BITS_TSF_SYNC_INTERVAL_CLI0))
+#define BIT_GET_TSF_SYNC_INTERVAL_CLI0(x)                                      \
+	(((x) >> BIT_SHIFT_TSF_SYNC_INTERVAL_CLI0) &                           \
+	 BIT_MASK_TSF_SYNC_INTERVAL_CLI0)
+#define BIT_SET_TSF_SYNC_INTERVAL_CLI0(x, v)                                   \
+	(BIT_CLEAR_TSF_SYNC_INTERVAL_CLI0(x) | BIT_TSF_SYNC_INTERVAL_CLI0(v))
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_TSF_ADJ_VLAUE			(Offset 0x1524) */
+
+#define BIT_SHIFT_R_CLI0_TSFT_ADJ_VAL 0
+#define BIT_MASK_R_CLI0_TSFT_ADJ_VAL 0xffff
+#define BIT_R_CLI0_TSFT_ADJ_VAL(x)                                             \
+	(((x) & BIT_MASK_R_CLI0_TSFT_ADJ_VAL) << BIT_SHIFT_R_CLI0_TSFT_ADJ_VAL)
+#define BITS_R_CLI0_TSFT_ADJ_VAL                                               \
+	(BIT_MASK_R_CLI0_TSFT_ADJ_VAL << BIT_SHIFT_R_CLI0_TSFT_ADJ_VAL)
+#define BIT_CLEAR_R_CLI0_TSFT_ADJ_VAL(x) ((x) & (~BITS_R_CLI0_TSFT_ADJ_VAL))
+#define BIT_GET_R_CLI0_TSFT_ADJ_VAL(x)                                         \
+	(((x) >> BIT_SHIFT_R_CLI0_TSFT_ADJ_VAL) & BIT_MASK_R_CLI0_TSFT_ADJ_VAL)
+#define BIT_SET_R_CLI0_TSFT_ADJ_VAL(x, v)                                      \
+	(BIT_CLEAR_R_CLI0_TSFT_ADJ_VAL(x) | BIT_R_CLI0_TSFT_ADJ_VAL(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_TSFTR_HIGH				(Offset 0x1524) */
+
+#define BIT_SHIFT_TSF_TIMER_HIGH 0
+#define BIT_MASK_TSF_TIMER_HIGH 0xffffffffL
+#define BIT_TSF_TIMER_HIGH(x)                                                  \
+	(((x) & BIT_MASK_TSF_TIMER_HIGH) << BIT_SHIFT_TSF_TIMER_HIGH)
+#define BITS_TSF_TIMER_HIGH                                                    \
+	(BIT_MASK_TSF_TIMER_HIGH << BIT_SHIFT_TSF_TIMER_HIGH)
+#define BIT_CLEAR_TSF_TIMER_HIGH(x) ((x) & (~BITS_TSF_TIMER_HIGH))
+#define BIT_GET_TSF_TIMER_HIGH(x)                                              \
+	(((x) >> BIT_SHIFT_TSF_TIMER_HIGH) & BIT_MASK_TSF_TIMER_HIGH)
+#define BIT_SET_TSF_TIMER_HIGH(x, v)                                           \
+	(BIT_CLEAR_TSF_TIMER_HIGH(x) | BIT_TSF_TIMER_HIGH(v))
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+/* 2 REG_TSF_SYN_OFFSET2			(Offset 0x1528) */
+
+#define BIT_SHIFT_TSF_SYNC_INTERVAL_CLI3 16
+#define BIT_MASK_TSF_SYNC_INTERVAL_CLI3 0xffff
+#define BIT_TSF_SYNC_INTERVAL_CLI3(x)                                          \
+	(((x) & BIT_MASK_TSF_SYNC_INTERVAL_CLI3)                               \
+	 << BIT_SHIFT_TSF_SYNC_INTERVAL_CLI3)
+#define BITS_TSF_SYNC_INTERVAL_CLI3                                            \
+	(BIT_MASK_TSF_SYNC_INTERVAL_CLI3 << BIT_SHIFT_TSF_SYNC_INTERVAL_CLI3)
+#define BIT_CLEAR_TSF_SYNC_INTERVAL_CLI3(x)                                    \
+	((x) & (~BITS_TSF_SYNC_INTERVAL_CLI3))
+#define BIT_GET_TSF_SYNC_INTERVAL_CLI3(x)                                      \
+	(((x) >> BIT_SHIFT_TSF_SYNC_INTERVAL_CLI3) &                           \
+	 BIT_MASK_TSF_SYNC_INTERVAL_CLI3)
+#define BIT_SET_TSF_SYNC_INTERVAL_CLI3(x, v)                                   \
+	(BIT_CLEAR_TSF_SYNC_INTERVAL_CLI3(x) | BIT_TSF_SYNC_INTERVAL_CLI3(v))
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_TSF_ADJ_VLAUE_2			(Offset 0x1528) */
+
+#define BIT_SHIFT_R_CLI3_TSFT_ADJ_VAL 16
+#define BIT_MASK_R_CLI3_TSFT_ADJ_VAL 0xffff
+#define BIT_R_CLI3_TSFT_ADJ_VAL(x)                                             \
+	(((x) & BIT_MASK_R_CLI3_TSFT_ADJ_VAL) << BIT_SHIFT_R_CLI3_TSFT_ADJ_VAL)
+#define BITS_R_CLI3_TSFT_ADJ_VAL                                               \
+	(BIT_MASK_R_CLI3_TSFT_ADJ_VAL << BIT_SHIFT_R_CLI3_TSFT_ADJ_VAL)
+#define BIT_CLEAR_R_CLI3_TSFT_ADJ_VAL(x) ((x) & (~BITS_R_CLI3_TSFT_ADJ_VAL))
+#define BIT_GET_R_CLI3_TSFT_ADJ_VAL(x)                                         \
+	(((x) >> BIT_SHIFT_R_CLI3_TSFT_ADJ_VAL) & BIT_MASK_R_CLI3_TSFT_ADJ_VAL)
+#define BIT_SET_R_CLI3_TSFT_ADJ_VAL(x, v)                                      \
+	(BIT_CLEAR_R_CLI3_TSFT_ADJ_VAL(x) | BIT_R_CLI3_TSFT_ADJ_VAL(v))
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+/* 2 REG_TSF_SYN_OFFSET2			(Offset 0x1528) */
+
+#define BIT_SHIFT_TSF_SYNC_INTERVAL_CLI2 0
+#define BIT_MASK_TSF_SYNC_INTERVAL_CLI2 0xffff
+#define BIT_TSF_SYNC_INTERVAL_CLI2(x)                                          \
+	(((x) & BIT_MASK_TSF_SYNC_INTERVAL_CLI2)                               \
+	 << BIT_SHIFT_TSF_SYNC_INTERVAL_CLI2)
+#define BITS_TSF_SYNC_INTERVAL_CLI2                                            \
+	(BIT_MASK_TSF_SYNC_INTERVAL_CLI2 << BIT_SHIFT_TSF_SYNC_INTERVAL_CLI2)
+#define BIT_CLEAR_TSF_SYNC_INTERVAL_CLI2(x)                                    \
+	((x) & (~BITS_TSF_SYNC_INTERVAL_CLI2))
+#define BIT_GET_TSF_SYNC_INTERVAL_CLI2(x)                                      \
+	(((x) >> BIT_SHIFT_TSF_SYNC_INTERVAL_CLI2) &                           \
+	 BIT_MASK_TSF_SYNC_INTERVAL_CLI2)
+#define BIT_SET_TSF_SYNC_INTERVAL_CLI2(x, v)                                   \
+	(BIT_CLEAR_TSF_SYNC_INTERVAL_CLI2(x) | BIT_TSF_SYNC_INTERVAL_CLI2(v))
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_TSF_ADJ_VLAUE_2			(Offset 0x1528) */
+
+#define BIT_SHIFT_R_CLI2_TSFT_ADJ_VAL 0
+#define BIT_MASK_R_CLI2_TSFT_ADJ_VAL 0xffff
+#define BIT_R_CLI2_TSFT_ADJ_VAL(x)                                             \
+	(((x) & BIT_MASK_R_CLI2_TSFT_ADJ_VAL) << BIT_SHIFT_R_CLI2_TSFT_ADJ_VAL)
+#define BITS_R_CLI2_TSFT_ADJ_VAL                                               \
+	(BIT_MASK_R_CLI2_TSFT_ADJ_VAL << BIT_SHIFT_R_CLI2_TSFT_ADJ_VAL)
+#define BIT_CLEAR_R_CLI2_TSFT_ADJ_VAL(x) ((x) & (~BITS_R_CLI2_TSFT_ADJ_VAL))
+#define BIT_GET_R_CLI2_TSFT_ADJ_VAL(x)                                         \
+	(((x) >> BIT_SHIFT_R_CLI2_TSFT_ADJ_VAL) & BIT_MASK_R_CLI2_TSFT_ADJ_VAL)
+#define BIT_SET_R_CLI2_TSFT_ADJ_VAL(x, v)                                      \
+	(BIT_CLEAR_R_CLI2_TSFT_ADJ_VAL(x) | BIT_R_CLI2_TSFT_ADJ_VAL(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_BCN_ERR_CNT_MAC			(Offset 0x1528) */
+
+#define BIT_SHIFT_BCN_ERR_CNT_MAC 0
+#define BIT_MASK_BCN_ERR_CNT_MAC 0xff
+#define BIT_BCN_ERR_CNT_MAC(x)                                                 \
+	(((x) & BIT_MASK_BCN_ERR_CNT_MAC) << BIT_SHIFT_BCN_ERR_CNT_MAC)
+#define BITS_BCN_ERR_CNT_MAC                                                   \
+	(BIT_MASK_BCN_ERR_CNT_MAC << BIT_SHIFT_BCN_ERR_CNT_MAC)
+#define BIT_CLEAR_BCN_ERR_CNT_MAC(x) ((x) & (~BITS_BCN_ERR_CNT_MAC))
+#define BIT_GET_BCN_ERR_CNT_MAC(x)                                             \
+	(((x) >> BIT_SHIFT_BCN_ERR_CNT_MAC) & BIT_MASK_BCN_ERR_CNT_MAC)
+#define BIT_SET_BCN_ERR_CNT_MAC(x, v)                                          \
+	(BIT_CLEAR_BCN_ERR_CNT_MAC(x) | BIT_BCN_ERR_CNT_MAC(v))
+
+/* 2 REG_BCN_ERR_CNT_EDCCA			(Offset 0x1529) */
+
+#define BIT_SHIFT_BCN_ERR_CNT_EDCCA 0
+#define BIT_MASK_BCN_ERR_CNT_EDCCA 0xff
+#define BIT_BCN_ERR_CNT_EDCCA(x)                                               \
+	(((x) & BIT_MASK_BCN_ERR_CNT_EDCCA) << BIT_SHIFT_BCN_ERR_CNT_EDCCA)
+#define BITS_BCN_ERR_CNT_EDCCA                                                 \
+	(BIT_MASK_BCN_ERR_CNT_EDCCA << BIT_SHIFT_BCN_ERR_CNT_EDCCA)
+#define BIT_CLEAR_BCN_ERR_CNT_EDCCA(x) ((x) & (~BITS_BCN_ERR_CNT_EDCCA))
+#define BIT_GET_BCN_ERR_CNT_EDCCA(x)                                           \
+	(((x) >> BIT_SHIFT_BCN_ERR_CNT_EDCCA) & BIT_MASK_BCN_ERR_CNT_EDCCA)
+#define BIT_SET_BCN_ERR_CNT_EDCCA(x, v)                                        \
+	(BIT_CLEAR_BCN_ERR_CNT_EDCCA(x) | BIT_BCN_ERR_CNT_EDCCA(v))
+
+/* 2 REG_BCN_ERR_CNT_CCA			(Offset 0x152A) */
+
+#define BIT_SHIFT_BCN_ERR_CNT_CCA 0
+#define BIT_MASK_BCN_ERR_CNT_CCA 0xff
+#define BIT_BCN_ERR_CNT_CCA(x)                                                 \
+	(((x) & BIT_MASK_BCN_ERR_CNT_CCA) << BIT_SHIFT_BCN_ERR_CNT_CCA)
+#define BITS_BCN_ERR_CNT_CCA                                                   \
+	(BIT_MASK_BCN_ERR_CNT_CCA << BIT_SHIFT_BCN_ERR_CNT_CCA)
+#define BIT_CLEAR_BCN_ERR_CNT_CCA(x) ((x) & (~BITS_BCN_ERR_CNT_CCA))
+#define BIT_GET_BCN_ERR_CNT_CCA(x)                                             \
+	(((x) >> BIT_SHIFT_BCN_ERR_CNT_CCA) & BIT_MASK_BCN_ERR_CNT_CCA)
+#define BIT_SET_BCN_ERR_CNT_CCA(x, v)                                          \
+	(BIT_CLEAR_BCN_ERR_CNT_CCA(x) | BIT_BCN_ERR_CNT_CCA(v))
+
+/* 2 REG_BCN_ERR_CNT_INVALID			(Offset 0x152B) */
+
+#define BIT_SHIFT_BCN_ERR_CNT_INVALID 0
+#define BIT_MASK_BCN_ERR_CNT_INVALID 0xff
+#define BIT_BCN_ERR_CNT_INVALID(x)                                             \
+	(((x) & BIT_MASK_BCN_ERR_CNT_INVALID) << BIT_SHIFT_BCN_ERR_CNT_INVALID)
+#define BITS_BCN_ERR_CNT_INVALID                                               \
+	(BIT_MASK_BCN_ERR_CNT_INVALID << BIT_SHIFT_BCN_ERR_CNT_INVALID)
+#define BIT_CLEAR_BCN_ERR_CNT_INVALID(x) ((x) & (~BITS_BCN_ERR_CNT_INVALID))
+#define BIT_GET_BCN_ERR_CNT_INVALID(x)                                         \
+	(((x) >> BIT_SHIFT_BCN_ERR_CNT_INVALID) & BIT_MASK_BCN_ERR_CNT_INVALID)
+#define BIT_SET_BCN_ERR_CNT_INVALID(x, v)                                      \
+	(BIT_CLEAR_BCN_ERR_CNT_INVALID(x) | BIT_BCN_ERR_CNT_INVALID(v))
+
+/* 2 REG_BCN_ERR_CNT_OTHERS			(Offset 0x152C) */
+
+#define BIT_SHIFT_BCN_ERR_CNT_OTHERS 0
+#define BIT_MASK_BCN_ERR_CNT_OTHERS 0xff
+#define BIT_BCN_ERR_CNT_OTHERS(x)                                              \
+	(((x) & BIT_MASK_BCN_ERR_CNT_OTHERS) << BIT_SHIFT_BCN_ERR_CNT_OTHERS)
+#define BITS_BCN_ERR_CNT_OTHERS                                                \
+	(BIT_MASK_BCN_ERR_CNT_OTHERS << BIT_SHIFT_BCN_ERR_CNT_OTHERS)
+#define BIT_CLEAR_BCN_ERR_CNT_OTHERS(x) ((x) & (~BITS_BCN_ERR_CNT_OTHERS))
+#define BIT_GET_BCN_ERR_CNT_OTHERS(x)                                          \
+	(((x) >> BIT_SHIFT_BCN_ERR_CNT_OTHERS) & BIT_MASK_BCN_ERR_CNT_OTHERS)
+#define BIT_SET_BCN_ERR_CNT_OTHERS(x, v)                                       \
+	(BIT_CLEAR_BCN_ERR_CNT_OTHERS(x) | BIT_BCN_ERR_CNT_OTHERS(v))
+
+/* 2 REG_RX_BCN_TIMER			(Offset 0x152D) */
+
+#define BIT_SHIFT_RX_BCN_TIMER 0
+#define BIT_MASK_RX_BCN_TIMER 0xffff
+#define BIT_RX_BCN_TIMER(x)                                                    \
+	(((x) & BIT_MASK_RX_BCN_TIMER) << BIT_SHIFT_RX_BCN_TIMER)
+#define BITS_RX_BCN_TIMER (BIT_MASK_RX_BCN_TIMER << BIT_SHIFT_RX_BCN_TIMER)
+#define BIT_CLEAR_RX_BCN_TIMER(x) ((x) & (~BITS_RX_BCN_TIMER))
+#define BIT_GET_RX_BCN_TIMER(x)                                                \
+	(((x) >> BIT_SHIFT_RX_BCN_TIMER) & BIT_MASK_RX_BCN_TIMER)
+#define BIT_SET_RX_BCN_TIMER(x, v)                                             \
+	(BIT_CLEAR_RX_BCN_TIMER(x) | BIT_RX_BCN_TIMER(v))
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+/* 2 REG_TSF_SYN_COMPARE_VALUE		(Offset 0x1530) */
+
+#define BIT_SHIFT_TSF_SYN_COMPARE_VALUE 0
+#define BIT_MASK_TSF_SYN_COMPARE_VALUE 0xffffffffffffffffL
+#define BIT_TSF_SYN_COMPARE_VALUE(x)                                           \
+	(((x) & BIT_MASK_TSF_SYN_COMPARE_VALUE)                                \
+	 << BIT_SHIFT_TSF_SYN_COMPARE_VALUE)
+#define BITS_TSF_SYN_COMPARE_VALUE                                             \
+	(BIT_MASK_TSF_SYN_COMPARE_VALUE << BIT_SHIFT_TSF_SYN_COMPARE_VALUE)
+#define BIT_CLEAR_TSF_SYN_COMPARE_VALUE(x) ((x) & (~BITS_TSF_SYN_COMPARE_VALUE))
+#define BIT_GET_TSF_SYN_COMPARE_VALUE(x)                                       \
+	(((x) >> BIT_SHIFT_TSF_SYN_COMPARE_VALUE) &                            \
+	 BIT_MASK_TSF_SYN_COMPARE_VALUE)
+#define BIT_SET_TSF_SYN_COMPARE_VALUE(x, v)                                    \
+	(BIT_CLEAR_TSF_SYN_COMPARE_VALUE(x) | BIT_TSF_SYN_COMPARE_VALUE(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_SUB_BCN_SPACE			(Offset 0x1534) */
+
+#define BIT_SHIFT_SUB_BCN_SPACE_V2 0
+#define BIT_MASK_SUB_BCN_SPACE_V2 0xff
+#define BIT_SUB_BCN_SPACE_V2(x)                                                \
+	(((x) & BIT_MASK_SUB_BCN_SPACE_V2) << BIT_SHIFT_SUB_BCN_SPACE_V2)
+#define BITS_SUB_BCN_SPACE_V2                                                  \
+	(BIT_MASK_SUB_BCN_SPACE_V2 << BIT_SHIFT_SUB_BCN_SPACE_V2)
+#define BIT_CLEAR_SUB_BCN_SPACE_V2(x) ((x) & (~BITS_SUB_BCN_SPACE_V2))
+#define BIT_GET_SUB_BCN_SPACE_V2(x)                                            \
+	(((x) >> BIT_SHIFT_SUB_BCN_SPACE_V2) & BIT_MASK_SUB_BCN_SPACE_V2)
+#define BIT_SET_SUB_BCN_SPACE_V2(x, v)                                         \
+	(BIT_CLEAR_SUB_BCN_SPACE_V2(x) | BIT_SUB_BCN_SPACE_V2(v))
+
+/* 2 REG_MBID_NUM_V1				(Offset 0x1535) */
+
+#define BIT_SHIFT_BCN_ERR_PORT_SEL 4
+#define BIT_MASK_BCN_ERR_PORT_SEL 0xf
+#define BIT_BCN_ERR_PORT_SEL(x)                                                \
+	(((x) & BIT_MASK_BCN_ERR_PORT_SEL) << BIT_SHIFT_BCN_ERR_PORT_SEL)
+#define BITS_BCN_ERR_PORT_SEL                                                  \
+	(BIT_MASK_BCN_ERR_PORT_SEL << BIT_SHIFT_BCN_ERR_PORT_SEL)
+#define BIT_CLEAR_BCN_ERR_PORT_SEL(x) ((x) & (~BITS_BCN_ERR_PORT_SEL))
+#define BIT_GET_BCN_ERR_PORT_SEL(x)                                            \
+	(((x) >> BIT_SHIFT_BCN_ERR_PORT_SEL) & BIT_MASK_BCN_ERR_PORT_SEL)
+#define BIT_SET_BCN_ERR_PORT_SEL(x, v)                                         \
+	(BIT_CLEAR_BCN_ERR_PORT_SEL(x) | BIT_BCN_ERR_PORT_SEL(v))
+
+#define BIT_SHIFT_MBID_BCN_NUM_V1 0
+#define BIT_MASK_MBID_BCN_NUM_V1 0xf
+#define BIT_MBID_BCN_NUM_V1(x)                                                 \
+	(((x) & BIT_MASK_MBID_BCN_NUM_V1) << BIT_SHIFT_MBID_BCN_NUM_V1)
+#define BITS_MBID_BCN_NUM_V1                                                   \
+	(BIT_MASK_MBID_BCN_NUM_V1 << BIT_SHIFT_MBID_BCN_NUM_V1)
+#define BIT_CLEAR_MBID_BCN_NUM_V1(x) ((x) & (~BITS_MBID_BCN_NUM_V1))
+#define BIT_GET_MBID_BCN_NUM_V1(x)                                             \
+	(((x) >> BIT_SHIFT_MBID_BCN_NUM_V1) & BIT_MASK_MBID_BCN_NUM_V1)
+#define BIT_SET_MBID_BCN_NUM_V1(x, v)                                          \
+	(BIT_CLEAR_MBID_BCN_NUM_V1(x) | BIT_MBID_BCN_NUM_V1(v))
+
+/* 2 REG_MBSSID_CTRL_V1			(Offset 0x1536) */
+
+#define BIT_MBID_BCNQ15_EN BIT(15)
+#define BIT_MBID_BCNQ14_EN BIT(14)
+#define BIT_MBID_BCNQ13_EN BIT(13)
+#define BIT_MBID_BCNQ12_EN BIT(12)
+#define BIT_MBID_BCNQ11_EN BIT(11)
+#define BIT_MBID_BCNQ10_EN BIT(10)
+#define BIT_MBID_BCNQ9_EN BIT(9)
+#define BIT_MBID_BCNQ8_EN BIT(8)
+
+/* 2 REG_BW_CFG				(Offset 0x1539) */
+
+#define BIT_SLEEP_32K_EN BIT(3)
+#define BIT_DIS_MARK_TSF_US_V1 BIT(2)
+
+/* 2 REG_ATIMWND_CFG				(Offset 0x153A) */
+
+#define BIT_SHIFT_ATIMWND_V1 0
+#define BIT_MASK_ATIMWND_V1 0xff
+#define BIT_ATIMWND_V1(x) (((x) & BIT_MASK_ATIMWND_V1) << BIT_SHIFT_ATIMWND_V1)
+#define BITS_ATIMWND_V1 (BIT_MASK_ATIMWND_V1 << BIT_SHIFT_ATIMWND_V1)
+#define BIT_CLEAR_ATIMWND_V1(x) ((x) & (~BITS_ATIMWND_V1))
+#define BIT_GET_ATIMWND_V1(x)                                                  \
+	(((x) >> BIT_SHIFT_ATIMWND_V1) & BIT_MASK_ATIMWND_V1)
+#define BIT_SET_ATIMWND_V1(x, v) (BIT_CLEAR_ATIMWND_V1(x) | BIT_ATIMWND_V1(v))
+
+/* 2 REG_DTIM_COUNTER_CFG			(Offset 0x153B) */
+
+#define BIT_SHIFT_DTIM_COUNT 0
+#define BIT_MASK_DTIM_COUNT 0xff
+#define BIT_DTIM_COUNT(x) (((x) & BIT_MASK_DTIM_COUNT) << BIT_SHIFT_DTIM_COUNT)
+#define BITS_DTIM_COUNT (BIT_MASK_DTIM_COUNT << BIT_SHIFT_DTIM_COUNT)
+#define BIT_CLEAR_DTIM_COUNT(x) ((x) & (~BITS_DTIM_COUNT))
+#define BIT_GET_DTIM_COUNT(x)                                                  \
+	(((x) >> BIT_SHIFT_DTIM_COUNT) & BIT_MASK_DTIM_COUNT)
+#define BIT_SET_DTIM_COUNT(x, v) (BIT_CLEAR_DTIM_COUNT(x) | BIT_DTIM_COUNT(v))
+
+/* 2 REG_ATIM_DTIM_CTRL_SEL			(Offset 0x153C) */
+
+#define BIT_DTIM_BYPASS_V1 BIT(7)
+
+#define BIT_SHIFT_ATIM_DTIM_SEL 0
+#define BIT_MASK_ATIM_DTIM_SEL 0x1f
+#define BIT_ATIM_DTIM_SEL(x)                                                   \
+	(((x) & BIT_MASK_ATIM_DTIM_SEL) << BIT_SHIFT_ATIM_DTIM_SEL)
+#define BITS_ATIM_DTIM_SEL (BIT_MASK_ATIM_DTIM_SEL << BIT_SHIFT_ATIM_DTIM_SEL)
+#define BIT_CLEAR_ATIM_DTIM_SEL(x) ((x) & (~BITS_ATIM_DTIM_SEL))
+#define BIT_GET_ATIM_DTIM_SEL(x)                                               \
+	(((x) >> BIT_SHIFT_ATIM_DTIM_SEL) & BIT_MASK_ATIM_DTIM_SEL)
+#define BIT_SET_ATIM_DTIM_SEL(x, v)                                            \
+	(BIT_CLEAR_ATIM_DTIM_SEL(x) | BIT_ATIM_DTIM_SEL(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_ATIMUGT_V1				(Offset 0x153D) */
+
+#define BIT_SHIFT_ATIM_URGENT 0
+#define BIT_MASK_ATIM_URGENT 0xff
+#define BIT_ATIM_URGENT(x)                                                     \
+	(((x) & BIT_MASK_ATIM_URGENT) << BIT_SHIFT_ATIM_URGENT)
+#define BITS_ATIM_URGENT (BIT_MASK_ATIM_URGENT << BIT_SHIFT_ATIM_URGENT)
+#define BIT_CLEAR_ATIM_URGENT(x) ((x) & (~BITS_ATIM_URGENT))
+#define BIT_GET_ATIM_URGENT(x)                                                 \
+	(((x) >> BIT_SHIFT_ATIM_URGENT) & BIT_MASK_ATIM_URGENT)
+#define BIT_SET_ATIM_URGENT(x, v)                                              \
+	(BIT_CLEAR_ATIM_URGENT(x) | BIT_ATIM_URGENT(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_DIS_ATIM_V1				(Offset 0x1540) */
+
+#define BIT_DIS_ATIM_P4 BIT(19)
+#define BIT_DIS_ATIM_P3 BIT(18)
+#define BIT_DIS_ATIM_P2 BIT(17)
+#define BIT_DIS_ATIM_P1 BIT(16)
+#define BIT_DIS_ATIM_VAP15 BIT(15)
+#define BIT_DIS_ATIM_VAP14 BIT(14)
+#define BIT_DIS_ATIM_VAP13 BIT(13)
+#define BIT_DIS_ATIM_VAP12 BIT(12)
+#define BIT_DIS_ATIM_VAP11 BIT(11)
+#define BIT_DIS_ATIM_VAP10 BIT(10)
+#define BIT_DIS_ATIM_VAP9 BIT(9)
+#define BIT_DIS_ATIM_VAP8 BIT(8)
+#define BIT_DIS_ATIM_ROOT_P0 BIT(0)
+
+/* 2 REG_HIQ_NO_LMT_EN_V1			(Offset 0x1544) */
+
+#define BIT_HIQ_NO_LMT_EN_P4 BIT(19)
+#define BIT_HIQ_NO_LMT_EN_P3 BIT(18)
+#define BIT_HIQ_NO_LMT_EN_P2 BIT(17)
+#define BIT_HIQ_NO_LMT_EN_P1 BIT(16)
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT)
+
+/* 2 REG_HIQ_NO_LMT_EN_V1			(Offset 0x1544) */
+
+#define BIT_HIQ_NO_LMT_EN_VAP15 BIT(15)
+#define BIT_HIQ_NO_LMT_EN_VAP14 BIT(14)
+#define BIT_HIQ_NO_LMT_EN_VAP13 BIT(13)
+#define BIT_HIQ_NO_LMT_EN_VAP12 BIT(12)
+#define BIT_HIQ_NO_LMT_EN_VAP11 BIT(11)
+#define BIT_HIQ_NO_LMT_EN_VAP10 BIT(10)
+#define BIT_HIQ_NO_LMT_EN_VAP9 BIT(9)
+#define BIT_HIQ_NO_LMT_EN_VAP8 BIT(8)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_HIQ_NO_LMT_EN_V1			(Offset 0x1544) */
+
+#define BIT_HIQ_NO_LMT_EN_ROOT_P0 BIT(0)
+
+/* 2 REG_P2PPS_CTRL_V1			(Offset 0x1548) */
+
+#define BIT_P2P_PWR_RST1_V2 BIT(15)
+#define BIT_P2P_PWR_RST0_V2 BIT(14)
+#define BIT_EN_TSFBIT32_RST_P2P_V1 BIT(13)
+
+#define BIT_SHIFT_NOA_UNIT0_SEL_V1 8
+#define BIT_MASK_NOA_UNIT0_SEL_V1 0x7
+#define BIT_NOA_UNIT0_SEL_V1(x)                                                \
+	(((x) & BIT_MASK_NOA_UNIT0_SEL_V1) << BIT_SHIFT_NOA_UNIT0_SEL_V1)
+#define BITS_NOA_UNIT0_SEL_V1                                                  \
+	(BIT_MASK_NOA_UNIT0_SEL_V1 << BIT_SHIFT_NOA_UNIT0_SEL_V1)
+#define BIT_CLEAR_NOA_UNIT0_SEL_V1(x) ((x) & (~BITS_NOA_UNIT0_SEL_V1))
+#define BIT_GET_NOA_UNIT0_SEL_V1(x)                                            \
+	(((x) >> BIT_SHIFT_NOA_UNIT0_SEL_V1) & BIT_MASK_NOA_UNIT0_SEL_V1)
+#define BIT_SET_NOA_UNIT0_SEL_V1(x, v)                                         \
+	(BIT_CLEAR_NOA_UNIT0_SEL_V1(x) | BIT_NOA_UNIT0_SEL_V1(v))
+
+#define BIT_P2P_CTW_ALLSTASLEEP_V1 BIT(7)
+#define BIT_P2P_OFF_DISTX_EN_V1 BIT(6)
+#define BIT_PWR_MGT_EN_V1 BIT(5)
+#define BIT_P2P_NOA1_EN_V1 BIT(2)
+#define BIT_P2P_NOA0_EN_V1 BIT(1)
+
+/* 2 REG_P2PPS1_CTRL_V1			(Offset 0x154C) */
+
+#define BIT_P2P1_PWR_RST1_V2 BIT(15)
+#define BIT_P2P1_PWR_RST0_V2 BIT(14)
+#define BIT_EN_TSFBIT32_RST_P2P1_V1 BIT(13)
+
+#define BIT_SHIFT_NOA_UNIT1_SEL_V1 8
+#define BIT_MASK_NOA_UNIT1_SEL_V1 0x7
+#define BIT_NOA_UNIT1_SEL_V1(x)                                                \
+	(((x) & BIT_MASK_NOA_UNIT1_SEL_V1) << BIT_SHIFT_NOA_UNIT1_SEL_V1)
+#define BITS_NOA_UNIT1_SEL_V1                                                  \
+	(BIT_MASK_NOA_UNIT1_SEL_V1 << BIT_SHIFT_NOA_UNIT1_SEL_V1)
+#define BIT_CLEAR_NOA_UNIT1_SEL_V1(x) ((x) & (~BITS_NOA_UNIT1_SEL_V1))
+#define BIT_GET_NOA_UNIT1_SEL_V1(x)                                            \
+	(((x) >> BIT_SHIFT_NOA_UNIT1_SEL_V1) & BIT_MASK_NOA_UNIT1_SEL_V1)
+#define BIT_SET_NOA_UNIT1_SEL_V1(x, v)                                         \
+	(BIT_CLEAR_NOA_UNIT1_SEL_V1(x) | BIT_NOA_UNIT1_SEL_V1(v))
+
+#define BIT_P2P1_CTW_ALLSTASLEEP_V1 BIT(7)
+#define BIT_P2P1_PWR_MGT_EN_V1 BIT(5)
+#define BIT_P2P1_NOA1_EN_V1 BIT(2)
+#define BIT_P2P1_NOA0_EN_V1 BIT(1)
+
+/* 2 REG_P2PPS1_SPEC_STATE_V1		(Offset 0x154E) */
+
+#define BIT_P2P1_SPEC_POWER_STATEP BIT(7)
+#define BIT_P2P1_SPEC_BEACON_AREA_ON BIT(5)
+
+/* 2 REG_P2PPS2_CTRL_V1			(Offset 0x1550) */
+
+#define BIT_P2P2_PWR_RST1_V2 BIT(15)
+#define BIT_P2P2_PWR_RST0_V2 BIT(14)
+#define BIT_EN_TSFBIT32_RST_P2P2_V1 BIT(13)
+
+#define BIT_SHIFT_NOA_UNIT2_SEL_V1 8
+#define BIT_MASK_NOA_UNIT2_SEL_V1 0x7
+#define BIT_NOA_UNIT2_SEL_V1(x)                                                \
+	(((x) & BIT_MASK_NOA_UNIT2_SEL_V1) << BIT_SHIFT_NOA_UNIT2_SEL_V1)
+#define BITS_NOA_UNIT2_SEL_V1                                                  \
+	(BIT_MASK_NOA_UNIT2_SEL_V1 << BIT_SHIFT_NOA_UNIT2_SEL_V1)
+#define BIT_CLEAR_NOA_UNIT2_SEL_V1(x) ((x) & (~BITS_NOA_UNIT2_SEL_V1))
+#define BIT_GET_NOA_UNIT2_SEL_V1(x)                                            \
+	(((x) >> BIT_SHIFT_NOA_UNIT2_SEL_V1) & BIT_MASK_NOA_UNIT2_SEL_V1)
+#define BIT_SET_NOA_UNIT2_SEL_V1(x, v)                                         \
+	(BIT_CLEAR_NOA_UNIT2_SEL_V1(x) | BIT_NOA_UNIT2_SEL_V1(v))
+
+#define BIT_P2P2_CTW_ALLSTASLEEP_V1 BIT(7)
+#define BIT_P2P2_OFF_DISTX_EN_V1 BIT(6)
+#define BIT_P2P2_PWR_MGT_EN_V1 BIT(5)
+#define BIT_P2P2_NOA1_EN_V1 BIT(2)
+#define BIT_P2P2_NOA0_EN_V1 BIT(1)
+
+/* 2 REG_P2PPS2_SPEC_STATE_V1		(Offset 0x1552) */
+
+#define BIT_P2P2_SPEC_POWER_STATEP BIT(7)
+#define BIT_P2P2_SPEC_BEACON_AREA_ON BIT(5)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_P2PON_DIS_TXTIME_V1			(Offset 0x1554) */
+
+#define BIT_SHIFT_P2PON_DIS_TXTIME 0
+#define BIT_MASK_P2PON_DIS_TXTIME 0xff
+#define BIT_P2PON_DIS_TXTIME(x)                                                \
+	(((x) & BIT_MASK_P2PON_DIS_TXTIME) << BIT_SHIFT_P2PON_DIS_TXTIME)
+#define BITS_P2PON_DIS_TXTIME                                                  \
+	(BIT_MASK_P2PON_DIS_TXTIME << BIT_SHIFT_P2PON_DIS_TXTIME)
+#define BIT_CLEAR_P2PON_DIS_TXTIME(x) ((x) & (~BITS_P2PON_DIS_TXTIME))
+#define BIT_GET_P2PON_DIS_TXTIME(x)                                            \
+	(((x) >> BIT_SHIFT_P2PON_DIS_TXTIME) & BIT_MASK_P2PON_DIS_TXTIME)
+#define BIT_SET_P2PON_DIS_TXTIME(x, v)                                         \
+	(BIT_CLEAR_P2PON_DIS_TXTIME(x) | BIT_P2PON_DIS_TXTIME(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_CHG_POWER_BCN_AREA			(Offset 0x1556) */
+
+#define BIT_CHG_POWER_BCN_AREA BIT(0)
+
+/* 2 REG_NOA_SEL				(Offset 0x1557) */
+
+#define BIT_SHIFT_NOA_SEL_V1 0
+#define BIT_MASK_NOA_SEL_V1 0x7
+#define BIT_NOA_SEL_V1(x) (((x) & BIT_MASK_NOA_SEL_V1) << BIT_SHIFT_NOA_SEL_V1)
+#define BITS_NOA_SEL_V1 (BIT_MASK_NOA_SEL_V1 << BIT_SHIFT_NOA_SEL_V1)
+#define BIT_CLEAR_NOA_SEL_V1(x) ((x) & (~BITS_NOA_SEL_V1))
+#define BIT_GET_NOA_SEL_V1(x)                                                  \
+	(((x) >> BIT_SHIFT_NOA_SEL_V1) & BIT_MASK_NOA_SEL_V1)
+#define BIT_SET_NOA_SEL_V1(x, v) (BIT_CLEAR_NOA_SEL_V1(x) | BIT_NOA_SEL_V1(v))
+
+/* 2 REG_NOA_PARAM_3_V1			(Offset 0x1564) */
+
+#define BIT_SHIFT_NOA_COUNT_V2 0
+#define BIT_MASK_NOA_COUNT_V2 0xffffffffL
+#define BIT_NOA_COUNT_V2(x)                                                    \
+	(((x) & BIT_MASK_NOA_COUNT_V2) << BIT_SHIFT_NOA_COUNT_V2)
+#define BITS_NOA_COUNT_V2 (BIT_MASK_NOA_COUNT_V2 << BIT_SHIFT_NOA_COUNT_V2)
+#define BIT_CLEAR_NOA_COUNT_V2(x) ((x) & (~BITS_NOA_COUNT_V2))
+#define BIT_GET_NOA_COUNT_V2(x)                                                \
+	(((x) >> BIT_SHIFT_NOA_COUNT_V2) & BIT_MASK_NOA_COUNT_V2)
+#define BIT_SET_NOA_COUNT_V2(x, v)                                             \
+	(BIT_CLEAR_NOA_COUNT_V2(x) | BIT_NOA_COUNT_V2(v))
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_NOA_ON_ERLY_TIME_V1			(Offset 0x1568) */
+
+#define BIT_SHIFT__NOA_ON_ERLY_TIME 0
+#define BIT_MASK__NOA_ON_ERLY_TIME 0xff
+#define BIT__NOA_ON_ERLY_TIME(x)                                               \
+	(((x) & BIT_MASK__NOA_ON_ERLY_TIME) << BIT_SHIFT__NOA_ON_ERLY_TIME)
+#define BITS__NOA_ON_ERLY_TIME                                                 \
+	(BIT_MASK__NOA_ON_ERLY_TIME << BIT_SHIFT__NOA_ON_ERLY_TIME)
+#define BIT_CLEAR__NOA_ON_ERLY_TIME(x) ((x) & (~BITS__NOA_ON_ERLY_TIME))
+#define BIT_GET__NOA_ON_ERLY_TIME(x)                                           \
+	(((x) >> BIT_SHIFT__NOA_ON_ERLY_TIME) & BIT_MASK__NOA_ON_ERLY_TIME)
+#define BIT_SET__NOA_ON_ERLY_TIME(x, v)                                        \
+	(BIT_CLEAR__NOA_ON_ERLY_TIME(x) | BIT__NOA_ON_ERLY_TIME(v))
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_P2PPS_HW_AUTO_PAUSE_CTRL		(Offset 0x156C) */
+
+#define BIT_P2PPS_NOA_STOP_TX_HANG BIT(31)
+#define BIT_P2PPS_MACID_PAUSE_EN BIT(11)
+#define BIT_P2PPS__MGQ_PAUSE BIT(10)
+#define BIT_P2PPS__HIQ_PAUSE BIT(9)
+#define BIT_P2PPS__BCNQ_PAUSE BIT(8)
+
+#define BIT_SHIFT_P2PPS_MACID_PAUSE 0
+#define BIT_MASK_P2PPS_MACID_PAUSE 0xff
+#define BIT_P2PPS_MACID_PAUSE(x)                                               \
+	(((x) & BIT_MASK_P2PPS_MACID_PAUSE) << BIT_SHIFT_P2PPS_MACID_PAUSE)
+#define BITS_P2PPS_MACID_PAUSE                                                 \
+	(BIT_MASK_P2PPS_MACID_PAUSE << BIT_SHIFT_P2PPS_MACID_PAUSE)
+#define BIT_CLEAR_P2PPS_MACID_PAUSE(x) ((x) & (~BITS_P2PPS_MACID_PAUSE))
+#define BIT_GET_P2PPS_MACID_PAUSE(x)                                           \
+	(((x) >> BIT_SHIFT_P2PPS_MACID_PAUSE) & BIT_MASK_P2PPS_MACID_PAUSE)
+#define BIT_SET_P2PPS_MACID_PAUSE(x, v)                                        \
+	(BIT_CLEAR_P2PPS_MACID_PAUSE(x) | BIT_P2PPS_MACID_PAUSE(v))
+
+/* 2 REG_P2PPS1_HW_AUTO_PAUSE_CTRL		(Offset 0x1570) */
+
+#define BIT_P2PPS1_NOA_STOP_TX_HANG BIT(31)
+#define BIT_P2PPS1_MACID_PAUSE_EN BIT(11)
+#define BIT_P2PPS1__MGQ_PAUSE BIT(10)
+#define BIT_P2PPS1__HIQ_PAUSE BIT(9)
+#define BIT_P2PPS1__BCNQ_PAUSE BIT(8)
+
+#define BIT_SHIFT_P2PPS1_MACID_PAUSE 0
+#define BIT_MASK_P2PPS1_MACID_PAUSE 0xff
+#define BIT_P2PPS1_MACID_PAUSE(x)                                              \
+	(((x) & BIT_MASK_P2PPS1_MACID_PAUSE) << BIT_SHIFT_P2PPS1_MACID_PAUSE)
+#define BITS_P2PPS1_MACID_PAUSE                                                \
+	(BIT_MASK_P2PPS1_MACID_PAUSE << BIT_SHIFT_P2PPS1_MACID_PAUSE)
+#define BIT_CLEAR_P2PPS1_MACID_PAUSE(x) ((x) & (~BITS_P2PPS1_MACID_PAUSE))
+#define BIT_GET_P2PPS1_MACID_PAUSE(x)                                          \
+	(((x) >> BIT_SHIFT_P2PPS1_MACID_PAUSE) & BIT_MASK_P2PPS1_MACID_PAUSE)
+#define BIT_SET_P2PPS1_MACID_PAUSE(x, v)                                       \
+	(BIT_CLEAR_P2PPS1_MACID_PAUSE(x) | BIT_P2PPS1_MACID_PAUSE(v))
+
+/* 2 REG_P2PPS2_HW_AUTO_PAUSE_CTRL		(Offset 0x1574) */
+
+#define BIT_P2PPS2_NOA_STOP_TX_HANG BIT(31)
+#define BIT_P2PPS2_MACID_PAUSE_EN BIT(11)
+#define BIT_P2PPS2__MGQ_PAUSE BIT(10)
+#define BIT_P2PPS2__HIQ_PAUSE BIT(9)
+#define BIT_P2PPS2__BCNQ_PAUSE BIT(8)
+
+#define BIT_SHIFT_P2PPS2_MACID_PAUSE 0
+#define BIT_MASK_P2PPS2_MACID_PAUSE 0xff
+#define BIT_P2PPS2_MACID_PAUSE(x)                                              \
+	(((x) & BIT_MASK_P2PPS2_MACID_PAUSE) << BIT_SHIFT_P2PPS2_MACID_PAUSE)
+#define BITS_P2PPS2_MACID_PAUSE                                                \
+	(BIT_MASK_P2PPS2_MACID_PAUSE << BIT_SHIFT_P2PPS2_MACID_PAUSE)
+#define BIT_CLEAR_P2PPS2_MACID_PAUSE(x) ((x) & (~BITS_P2PPS2_MACID_PAUSE))
+#define BIT_GET_P2PPS2_MACID_PAUSE(x)                                          \
+	(((x) >> BIT_SHIFT_P2PPS2_MACID_PAUSE) & BIT_MASK_P2PPS2_MACID_PAUSE)
+#define BIT_SET_P2PPS2_MACID_PAUSE(x, v)                                       \
+	(BIT_CLEAR_P2PPS2_MACID_PAUSE(x) | BIT_P2PPS2_MACID_PAUSE(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_RX_TBTT_SHIFT			(Offset 0x1578) */
+
+#define BIT_SHIFT_RX_TBTT_SHIFT_SEL 24
+#define BIT_MASK_RX_TBTT_SHIFT_SEL 0x7
+#define BIT_RX_TBTT_SHIFT_SEL(x)                                               \
+	(((x) & BIT_MASK_RX_TBTT_SHIFT_SEL) << BIT_SHIFT_RX_TBTT_SHIFT_SEL)
+#define BITS_RX_TBTT_SHIFT_SEL                                                 \
+	(BIT_MASK_RX_TBTT_SHIFT_SEL << BIT_SHIFT_RX_TBTT_SHIFT_SEL)
+#define BIT_CLEAR_RX_TBTT_SHIFT_SEL(x) ((x) & (~BITS_RX_TBTT_SHIFT_SEL))
+#define BIT_GET_RX_TBTT_SHIFT_SEL(x)                                           \
+	(((x) >> BIT_SHIFT_RX_TBTT_SHIFT_SEL) & BIT_MASK_RX_TBTT_SHIFT_SEL)
+#define BIT_SET_RX_TBTT_SHIFT_SEL(x, v)                                        \
+	(BIT_CLEAR_RX_TBTT_SHIFT_SEL(x) | BIT_RX_TBTT_SHIFT_SEL(v))
+
+#define BIT_RX_TBTT_SHIFT_RW_FLAG BIT(15)
+
+#define BIT_SHIFT_RX_TBTT_SHIFT_OFFSET 0
+#define BIT_MASK_RX_TBTT_SHIFT_OFFSET 0xfff
+#define BIT_RX_TBTT_SHIFT_OFFSET(x)                                            \
+	(((x) & BIT_MASK_RX_TBTT_SHIFT_OFFSET)                                 \
+	 << BIT_SHIFT_RX_TBTT_SHIFT_OFFSET)
+#define BITS_RX_TBTT_SHIFT_OFFSET                                              \
+	(BIT_MASK_RX_TBTT_SHIFT_OFFSET << BIT_SHIFT_RX_TBTT_SHIFT_OFFSET)
+#define BIT_CLEAR_RX_TBTT_SHIFT_OFFSET(x) ((x) & (~BITS_RX_TBTT_SHIFT_OFFSET))
+#define BIT_GET_RX_TBTT_SHIFT_OFFSET(x)                                        \
+	(((x) >> BIT_SHIFT_RX_TBTT_SHIFT_OFFSET) &                             \
+	 BIT_MASK_RX_TBTT_SHIFT_OFFSET)
+#define BIT_SET_RX_TBTT_SHIFT_OFFSET(x, v)                                     \
+	(BIT_CLEAR_RX_TBTT_SHIFT_OFFSET(x) | BIT_RX_TBTT_SHIFT_OFFSET(v))
+
+/* 2 REG_FREERUN_CNT_LOW			(Offset 0x1580) */
+
+#define BIT_SHIFT_FREERUN_CNT_LOW 0
+#define BIT_MASK_FREERUN_CNT_LOW 0xffffffffL
+#define BIT_FREERUN_CNT_LOW(x)                                                 \
+	(((x) & BIT_MASK_FREERUN_CNT_LOW) << BIT_SHIFT_FREERUN_CNT_LOW)
+#define BITS_FREERUN_CNT_LOW                                                   \
+	(BIT_MASK_FREERUN_CNT_LOW << BIT_SHIFT_FREERUN_CNT_LOW)
+#define BIT_CLEAR_FREERUN_CNT_LOW(x) ((x) & (~BITS_FREERUN_CNT_LOW))
+#define BIT_GET_FREERUN_CNT_LOW(x)                                             \
+	(((x) >> BIT_SHIFT_FREERUN_CNT_LOW) & BIT_MASK_FREERUN_CNT_LOW)
+#define BIT_SET_FREERUN_CNT_LOW(x, v)                                          \
+	(BIT_CLEAR_FREERUN_CNT_LOW(x) | BIT_FREERUN_CNT_LOW(v))
+
+/* 2 REG_FREERUN_CNT_HIGH			(Offset 0x1584) */
+
+#define BIT_SHIFT_FREERUN_CNT_HIGH 0
+#define BIT_MASK_FREERUN_CNT_HIGH 0xffffffffL
+#define BIT_FREERUN_CNT_HIGH(x)                                                \
+	(((x) & BIT_MASK_FREERUN_CNT_HIGH) << BIT_SHIFT_FREERUN_CNT_HIGH)
+#define BITS_FREERUN_CNT_HIGH                                                  \
+	(BIT_MASK_FREERUN_CNT_HIGH << BIT_SHIFT_FREERUN_CNT_HIGH)
+#define BIT_CLEAR_FREERUN_CNT_HIGH(x) ((x) & (~BITS_FREERUN_CNT_HIGH))
+#define BIT_GET_FREERUN_CNT_HIGH(x)                                            \
+	(((x) >> BIT_SHIFT_FREERUN_CNT_HIGH) & BIT_MASK_FREERUN_CNT_HIGH)
+#define BIT_SET_FREERUN_CNT_HIGH(x, v)                                         \
+	(BIT_CLEAR_FREERUN_CNT_HIGH(x) | BIT_FREERUN_CNT_HIGH(v))
+
+/* 2 REG_PS_TIMER_0				(Offset 0x158C) */
+
+#define BIT_SHIFT_PS_TIMER_0 0
+#define BIT_MASK_PS_TIMER_0 0xffffffffL
+#define BIT_PS_TIMER_0(x) (((x) & BIT_MASK_PS_TIMER_0) << BIT_SHIFT_PS_TIMER_0)
+#define BITS_PS_TIMER_0 (BIT_MASK_PS_TIMER_0 << BIT_SHIFT_PS_TIMER_0)
+#define BIT_CLEAR_PS_TIMER_0(x) ((x) & (~BITS_PS_TIMER_0))
+#define BIT_GET_PS_TIMER_0(x)                                                  \
+	(((x) >> BIT_SHIFT_PS_TIMER_0) & BIT_MASK_PS_TIMER_0)
+#define BIT_SET_PS_TIMER_0(x, v) (BIT_CLEAR_PS_TIMER_0(x) | BIT_PS_TIMER_0(v))
+
+/* 2 REG_PS_TIMER_1				(Offset 0x1590) */
+
+#define BIT_SHIFT_PS_TIMER_1 0
+#define BIT_MASK_PS_TIMER_1 0xffffffffL
+#define BIT_PS_TIMER_1(x) (((x) & BIT_MASK_PS_TIMER_1) << BIT_SHIFT_PS_TIMER_1)
+#define BITS_PS_TIMER_1 (BIT_MASK_PS_TIMER_1 << BIT_SHIFT_PS_TIMER_1)
+#define BIT_CLEAR_PS_TIMER_1(x) ((x) & (~BITS_PS_TIMER_1))
+#define BIT_GET_PS_TIMER_1(x)                                                  \
+	(((x) >> BIT_SHIFT_PS_TIMER_1) & BIT_MASK_PS_TIMER_1)
+#define BIT_SET_PS_TIMER_1(x, v) (BIT_CLEAR_PS_TIMER_1(x) | BIT_PS_TIMER_1(v))
+
+/* 2 REG_PS_TIMER_2				(Offset 0x1594) */
+
+#define BIT_SHIFT_PS_TIMER_2 0
+#define BIT_MASK_PS_TIMER_2 0xffffffffL
+#define BIT_PS_TIMER_2(x) (((x) & BIT_MASK_PS_TIMER_2) << BIT_SHIFT_PS_TIMER_2)
+#define BITS_PS_TIMER_2 (BIT_MASK_PS_TIMER_2 << BIT_SHIFT_PS_TIMER_2)
+#define BIT_CLEAR_PS_TIMER_2(x) ((x) & (~BITS_PS_TIMER_2))
+#define BIT_GET_PS_TIMER_2(x)                                                  \
+	(((x) >> BIT_SHIFT_PS_TIMER_2) & BIT_MASK_PS_TIMER_2)
+#define BIT_SET_PS_TIMER_2(x, v) (BIT_CLEAR_PS_TIMER_2(x) | BIT_PS_TIMER_2(v))
+
+/* 2 REG_PS_TIMER_3				(Offset 0x1598) */
+
+#define BIT_SHIFT_PS_TIMER_3 0
+#define BIT_MASK_PS_TIMER_3 0xffffffffL
+#define BIT_PS_TIMER_3(x) (((x) & BIT_MASK_PS_TIMER_3) << BIT_SHIFT_PS_TIMER_3)
+#define BITS_PS_TIMER_3 (BIT_MASK_PS_TIMER_3 << BIT_SHIFT_PS_TIMER_3)
+#define BIT_CLEAR_PS_TIMER_3(x) ((x) & (~BITS_PS_TIMER_3))
+#define BIT_GET_PS_TIMER_3(x)                                                  \
+	(((x) >> BIT_SHIFT_PS_TIMER_3) & BIT_MASK_PS_TIMER_3)
+#define BIT_SET_PS_TIMER_3(x, v) (BIT_CLEAR_PS_TIMER_3(x) | BIT_PS_TIMER_3(v))
+
+/* 2 REG_PS_TIMER_4				(Offset 0x159C) */
+
+#define BIT_SHIFT_PS_TIMER_4 0
+#define BIT_MASK_PS_TIMER_4 0xffffffffL
+#define BIT_PS_TIMER_4(x) (((x) & BIT_MASK_PS_TIMER_4) << BIT_SHIFT_PS_TIMER_4)
+#define BITS_PS_TIMER_4 (BIT_MASK_PS_TIMER_4 << BIT_SHIFT_PS_TIMER_4)
+#define BIT_CLEAR_PS_TIMER_4(x) ((x) & (~BITS_PS_TIMER_4))
+#define BIT_GET_PS_TIMER_4(x)                                                  \
+	(((x) >> BIT_SHIFT_PS_TIMER_4) & BIT_MASK_PS_TIMER_4)
+#define BIT_SET_PS_TIMER_4(x, v) (BIT_CLEAR_PS_TIMER_4(x) | BIT_PS_TIMER_4(v))
+
+/* 2 REG_PS_TIMER_5				(Offset 0x15A0) */
+
+#define BIT_SHIFT_PS_TIMER_5 0
+#define BIT_MASK_PS_TIMER_5 0xffffffffL
+#define BIT_PS_TIMER_5(x) (((x) & BIT_MASK_PS_TIMER_5) << BIT_SHIFT_PS_TIMER_5)
+#define BITS_PS_TIMER_5 (BIT_MASK_PS_TIMER_5 << BIT_SHIFT_PS_TIMER_5)
+#define BIT_CLEAR_PS_TIMER_5(x) ((x) & (~BITS_PS_TIMER_5))
+#define BIT_GET_PS_TIMER_5(x)                                                  \
+	(((x) >> BIT_SHIFT_PS_TIMER_5) & BIT_MASK_PS_TIMER_5)
+#define BIT_SET_PS_TIMER_5(x, v) (BIT_CLEAR_PS_TIMER_5(x) | BIT_PS_TIMER_5(v))
+
+/* 2 REG_PS_TIMER_01_CTRL			(Offset 0x15A4) */
+
+#define BIT_SHIFT_PS_TIMER_1_EARLY_TIME 24
+#define BIT_MASK_PS_TIMER_1_EARLY_TIME 0xff
+#define BIT_PS_TIMER_1_EARLY_TIME(x)                                           \
+	(((x) & BIT_MASK_PS_TIMER_1_EARLY_TIME)                                \
+	 << BIT_SHIFT_PS_TIMER_1_EARLY_TIME)
+#define BITS_PS_TIMER_1_EARLY_TIME                                             \
+	(BIT_MASK_PS_TIMER_1_EARLY_TIME << BIT_SHIFT_PS_TIMER_1_EARLY_TIME)
+#define BIT_CLEAR_PS_TIMER_1_EARLY_TIME(x) ((x) & (~BITS_PS_TIMER_1_EARLY_TIME))
+#define BIT_GET_PS_TIMER_1_EARLY_TIME(x)                                       \
+	(((x) >> BIT_SHIFT_PS_TIMER_1_EARLY_TIME) &                            \
+	 BIT_MASK_PS_TIMER_1_EARLY_TIME)
+#define BIT_SET_PS_TIMER_1_EARLY_TIME(x, v)                                    \
+	(BIT_CLEAR_PS_TIMER_1_EARLY_TIME(x) | BIT_PS_TIMER_1_EARLY_TIME(v))
+
+#define BIT_PS_TIMER_1_EN BIT(23)
+
+#define BIT_SHIFT_PS_TIMER_1_TSF_SEL 16
+#define BIT_MASK_PS_TIMER_1_TSF_SEL 0x7
+#define BIT_PS_TIMER_1_TSF_SEL(x)                                              \
+	(((x) & BIT_MASK_PS_TIMER_1_TSF_SEL) << BIT_SHIFT_PS_TIMER_1_TSF_SEL)
+#define BITS_PS_TIMER_1_TSF_SEL                                                \
+	(BIT_MASK_PS_TIMER_1_TSF_SEL << BIT_SHIFT_PS_TIMER_1_TSF_SEL)
+#define BIT_CLEAR_PS_TIMER_1_TSF_SEL(x) ((x) & (~BITS_PS_TIMER_1_TSF_SEL))
+#define BIT_GET_PS_TIMER_1_TSF_SEL(x)                                          \
+	(((x) >> BIT_SHIFT_PS_TIMER_1_TSF_SEL) & BIT_MASK_PS_TIMER_1_TSF_SEL)
+#define BIT_SET_PS_TIMER_1_TSF_SEL(x, v)                                       \
+	(BIT_CLEAR_PS_TIMER_1_TSF_SEL(x) | BIT_PS_TIMER_1_TSF_SEL(v))
+
+#define BIT_SHIFT_PS_TIMER_0_EARLY_TIME 8
+#define BIT_MASK_PS_TIMER_0_EARLY_TIME 0xff
+#define BIT_PS_TIMER_0_EARLY_TIME(x)                                           \
+	(((x) & BIT_MASK_PS_TIMER_0_EARLY_TIME)                                \
+	 << BIT_SHIFT_PS_TIMER_0_EARLY_TIME)
+#define BITS_PS_TIMER_0_EARLY_TIME                                             \
+	(BIT_MASK_PS_TIMER_0_EARLY_TIME << BIT_SHIFT_PS_TIMER_0_EARLY_TIME)
+#define BIT_CLEAR_PS_TIMER_0_EARLY_TIME(x) ((x) & (~BITS_PS_TIMER_0_EARLY_TIME))
+#define BIT_GET_PS_TIMER_0_EARLY_TIME(x)                                       \
+	(((x) >> BIT_SHIFT_PS_TIMER_0_EARLY_TIME) &                            \
+	 BIT_MASK_PS_TIMER_0_EARLY_TIME)
+#define BIT_SET_PS_TIMER_0_EARLY_TIME(x, v)                                    \
+	(BIT_CLEAR_PS_TIMER_0_EARLY_TIME(x) | BIT_PS_TIMER_0_EARLY_TIME(v))
+
+#define BIT_PS_TIMER_0_EN BIT(7)
+
+#define BIT_SHIFT_PS_TIMER_0_TSF_SEL 0
+#define BIT_MASK_PS_TIMER_0_TSF_SEL 0x7
+#define BIT_PS_TIMER_0_TSF_SEL(x)                                              \
+	(((x) & BIT_MASK_PS_TIMER_0_TSF_SEL) << BIT_SHIFT_PS_TIMER_0_TSF_SEL)
+#define BITS_PS_TIMER_0_TSF_SEL                                                \
+	(BIT_MASK_PS_TIMER_0_TSF_SEL << BIT_SHIFT_PS_TIMER_0_TSF_SEL)
+#define BIT_CLEAR_PS_TIMER_0_TSF_SEL(x) ((x) & (~BITS_PS_TIMER_0_TSF_SEL))
+#define BIT_GET_PS_TIMER_0_TSF_SEL(x)                                          \
+	(((x) >> BIT_SHIFT_PS_TIMER_0_TSF_SEL) & BIT_MASK_PS_TIMER_0_TSF_SEL)
+#define BIT_SET_PS_TIMER_0_TSF_SEL(x, v)                                       \
+	(BIT_CLEAR_PS_TIMER_0_TSF_SEL(x) | BIT_PS_TIMER_0_TSF_SEL(v))
+
+/* 2 REG_PS_TIMER_23_CTRL			(Offset 0x15A8) */
+
+#define BIT_SHIFT_PS_TIMER_3_EARLY_TIME 24
+#define BIT_MASK_PS_TIMER_3_EARLY_TIME 0xff
+#define BIT_PS_TIMER_3_EARLY_TIME(x)                                           \
+	(((x) & BIT_MASK_PS_TIMER_3_EARLY_TIME)                                \
+	 << BIT_SHIFT_PS_TIMER_3_EARLY_TIME)
+#define BITS_PS_TIMER_3_EARLY_TIME                                             \
+	(BIT_MASK_PS_TIMER_3_EARLY_TIME << BIT_SHIFT_PS_TIMER_3_EARLY_TIME)
+#define BIT_CLEAR_PS_TIMER_3_EARLY_TIME(x) ((x) & (~BITS_PS_TIMER_3_EARLY_TIME))
+#define BIT_GET_PS_TIMER_3_EARLY_TIME(x)                                       \
+	(((x) >> BIT_SHIFT_PS_TIMER_3_EARLY_TIME) &                            \
+	 BIT_MASK_PS_TIMER_3_EARLY_TIME)
+#define BIT_SET_PS_TIMER_3_EARLY_TIME(x, v)                                    \
+	(BIT_CLEAR_PS_TIMER_3_EARLY_TIME(x) | BIT_PS_TIMER_3_EARLY_TIME(v))
+
+#define BIT_PS_TIMER_3_EN BIT(23)
+
+#define BIT_SHIFT_PS_TIMER_3_TSF_SEL 16
+#define BIT_MASK_PS_TIMER_3_TSF_SEL 0x7
+#define BIT_PS_TIMER_3_TSF_SEL(x)                                              \
+	(((x) & BIT_MASK_PS_TIMER_3_TSF_SEL) << BIT_SHIFT_PS_TIMER_3_TSF_SEL)
+#define BITS_PS_TIMER_3_TSF_SEL                                                \
+	(BIT_MASK_PS_TIMER_3_TSF_SEL << BIT_SHIFT_PS_TIMER_3_TSF_SEL)
+#define BIT_CLEAR_PS_TIMER_3_TSF_SEL(x) ((x) & (~BITS_PS_TIMER_3_TSF_SEL))
+#define BIT_GET_PS_TIMER_3_TSF_SEL(x)                                          \
+	(((x) >> BIT_SHIFT_PS_TIMER_3_TSF_SEL) & BIT_MASK_PS_TIMER_3_TSF_SEL)
+#define BIT_SET_PS_TIMER_3_TSF_SEL(x, v)                                       \
+	(BIT_CLEAR_PS_TIMER_3_TSF_SEL(x) | BIT_PS_TIMER_3_TSF_SEL(v))
+
+#define BIT_SHIFT_PS_TIMER_2_EARLY_TIME 8
+#define BIT_MASK_PS_TIMER_2_EARLY_TIME 0xff
+#define BIT_PS_TIMER_2_EARLY_TIME(x)                                           \
+	(((x) & BIT_MASK_PS_TIMER_2_EARLY_TIME)                                \
+	 << BIT_SHIFT_PS_TIMER_2_EARLY_TIME)
+#define BITS_PS_TIMER_2_EARLY_TIME                                             \
+	(BIT_MASK_PS_TIMER_2_EARLY_TIME << BIT_SHIFT_PS_TIMER_2_EARLY_TIME)
+#define BIT_CLEAR_PS_TIMER_2_EARLY_TIME(x) ((x) & (~BITS_PS_TIMER_2_EARLY_TIME))
+#define BIT_GET_PS_TIMER_2_EARLY_TIME(x)                                       \
+	(((x) >> BIT_SHIFT_PS_TIMER_2_EARLY_TIME) &                            \
+	 BIT_MASK_PS_TIMER_2_EARLY_TIME)
+#define BIT_SET_PS_TIMER_2_EARLY_TIME(x, v)                                    \
+	(BIT_CLEAR_PS_TIMER_2_EARLY_TIME(x) | BIT_PS_TIMER_2_EARLY_TIME(v))
+
+#define BIT_PS_TIMER_2_EN BIT(7)
+
+#define BIT_SHIFT_PS_TIMER_2_TSF_SEL 0
+#define BIT_MASK_PS_TIMER_2_TSF_SEL 0x7
+#define BIT_PS_TIMER_2_TSF_SEL(x)                                              \
+	(((x) & BIT_MASK_PS_TIMER_2_TSF_SEL) << BIT_SHIFT_PS_TIMER_2_TSF_SEL)
+#define BITS_PS_TIMER_2_TSF_SEL                                                \
+	(BIT_MASK_PS_TIMER_2_TSF_SEL << BIT_SHIFT_PS_TIMER_2_TSF_SEL)
+#define BIT_CLEAR_PS_TIMER_2_TSF_SEL(x) ((x) & (~BITS_PS_TIMER_2_TSF_SEL))
+#define BIT_GET_PS_TIMER_2_TSF_SEL(x)                                          \
+	(((x) >> BIT_SHIFT_PS_TIMER_2_TSF_SEL) & BIT_MASK_PS_TIMER_2_TSF_SEL)
+#define BIT_SET_PS_TIMER_2_TSF_SEL(x, v)                                       \
+	(BIT_CLEAR_PS_TIMER_2_TSF_SEL(x) | BIT_PS_TIMER_2_TSF_SEL(v))
+
+/* 2 REG_PS_TIMER_45_CTRL			(Offset 0x15AC) */
+
+#define BIT_SHIFT_PS_TIMER_5_EARLY_TIME 24
+#define BIT_MASK_PS_TIMER_5_EARLY_TIME 0xff
+#define BIT_PS_TIMER_5_EARLY_TIME(x)                                           \
+	(((x) & BIT_MASK_PS_TIMER_5_EARLY_TIME)                                \
+	 << BIT_SHIFT_PS_TIMER_5_EARLY_TIME)
+#define BITS_PS_TIMER_5_EARLY_TIME                                             \
+	(BIT_MASK_PS_TIMER_5_EARLY_TIME << BIT_SHIFT_PS_TIMER_5_EARLY_TIME)
+#define BIT_CLEAR_PS_TIMER_5_EARLY_TIME(x) ((x) & (~BITS_PS_TIMER_5_EARLY_TIME))
+#define BIT_GET_PS_TIMER_5_EARLY_TIME(x)                                       \
+	(((x) >> BIT_SHIFT_PS_TIMER_5_EARLY_TIME) &                            \
+	 BIT_MASK_PS_TIMER_5_EARLY_TIME)
+#define BIT_SET_PS_TIMER_5_EARLY_TIME(x, v)                                    \
+	(BIT_CLEAR_PS_TIMER_5_EARLY_TIME(x) | BIT_PS_TIMER_5_EARLY_TIME(v))
+
+#define BIT_PS_TIMER_5_EN BIT(23)
+
+#define BIT_SHIFT_PS_TIMER_5_TSF_SEL 16
+#define BIT_MASK_PS_TIMER_5_TSF_SEL 0x7
+#define BIT_PS_TIMER_5_TSF_SEL(x)                                              \
+	(((x) & BIT_MASK_PS_TIMER_5_TSF_SEL) << BIT_SHIFT_PS_TIMER_5_TSF_SEL)
+#define BITS_PS_TIMER_5_TSF_SEL                                                \
+	(BIT_MASK_PS_TIMER_5_TSF_SEL << BIT_SHIFT_PS_TIMER_5_TSF_SEL)
+#define BIT_CLEAR_PS_TIMER_5_TSF_SEL(x) ((x) & (~BITS_PS_TIMER_5_TSF_SEL))
+#define BIT_GET_PS_TIMER_5_TSF_SEL(x)                                          \
+	(((x) >> BIT_SHIFT_PS_TIMER_5_TSF_SEL) & BIT_MASK_PS_TIMER_5_TSF_SEL)
+#define BIT_SET_PS_TIMER_5_TSF_SEL(x, v)                                       \
+	(BIT_CLEAR_PS_TIMER_5_TSF_SEL(x) | BIT_PS_TIMER_5_TSF_SEL(v))
+
+#define BIT_SHIFT_PS_TIMER_4_EARLY_TIME 8
+#define BIT_MASK_PS_TIMER_4_EARLY_TIME 0xff
+#define BIT_PS_TIMER_4_EARLY_TIME(x)                                           \
+	(((x) & BIT_MASK_PS_TIMER_4_EARLY_TIME)                                \
+	 << BIT_SHIFT_PS_TIMER_4_EARLY_TIME)
+#define BITS_PS_TIMER_4_EARLY_TIME                                             \
+	(BIT_MASK_PS_TIMER_4_EARLY_TIME << BIT_SHIFT_PS_TIMER_4_EARLY_TIME)
+#define BIT_CLEAR_PS_TIMER_4_EARLY_TIME(x) ((x) & (~BITS_PS_TIMER_4_EARLY_TIME))
+#define BIT_GET_PS_TIMER_4_EARLY_TIME(x)                                       \
+	(((x) >> BIT_SHIFT_PS_TIMER_4_EARLY_TIME) &                            \
+	 BIT_MASK_PS_TIMER_4_EARLY_TIME)
+#define BIT_SET_PS_TIMER_4_EARLY_TIME(x, v)                                    \
+	(BIT_CLEAR_PS_TIMER_4_EARLY_TIME(x) | BIT_PS_TIMER_4_EARLY_TIME(v))
+
+#define BIT_PS_TIMER_4_EN BIT(7)
+
+#define BIT_SHIFT_PS_TIMER_4_TSF_SEL 0
+#define BIT_MASK_PS_TIMER_4_TSF_SEL 0x7
+#define BIT_PS_TIMER_4_TSF_SEL(x)                                              \
+	(((x) & BIT_MASK_PS_TIMER_4_TSF_SEL) << BIT_SHIFT_PS_TIMER_4_TSF_SEL)
+#define BITS_PS_TIMER_4_TSF_SEL                                                \
+	(BIT_MASK_PS_TIMER_4_TSF_SEL << BIT_SHIFT_PS_TIMER_4_TSF_SEL)
+#define BIT_CLEAR_PS_TIMER_4_TSF_SEL(x) ((x) & (~BITS_PS_TIMER_4_TSF_SEL))
+#define BIT_GET_PS_TIMER_4_TSF_SEL(x)                                          \
+	(((x) >> BIT_SHIFT_PS_TIMER_4_TSF_SEL) & BIT_MASK_PS_TIMER_4_TSF_SEL)
+#define BIT_SET_PS_TIMER_4_TSF_SEL(x, v)                                       \
+	(BIT_CLEAR_PS_TIMER_4_TSF_SEL(x) | BIT_PS_TIMER_4_TSF_SEL(v))
+
+/* 2 REG_CPUMGQ_FREERUN_TIMER_CTRL		(Offset 0x15B0) */
+
+#define BIT_FREECNT_RST_V1 BIT(23)
+#define BIT_EN_FREECNT_V1 BIT(16)
+
+#define BIT_SHIFT_CPUMGQ_TX_TIMER_EARLY_V1 8
+#define BIT_MASK_CPUMGQ_TX_TIMER_EARLY_V1 0xff
+#define BIT_CPUMGQ_TX_TIMER_EARLY_V1(x)                                        \
+	(((x) & BIT_MASK_CPUMGQ_TX_TIMER_EARLY_V1)                             \
+	 << BIT_SHIFT_CPUMGQ_TX_TIMER_EARLY_V1)
+#define BITS_CPUMGQ_TX_TIMER_EARLY_V1                                          \
+	(BIT_MASK_CPUMGQ_TX_TIMER_EARLY_V1                                     \
+	 << BIT_SHIFT_CPUMGQ_TX_TIMER_EARLY_V1)
+#define BIT_CLEAR_CPUMGQ_TX_TIMER_EARLY_V1(x)                                  \
+	((x) & (~BITS_CPUMGQ_TX_TIMER_EARLY_V1))
+#define BIT_GET_CPUMGQ_TX_TIMER_EARLY_V1(x)                                    \
+	(((x) >> BIT_SHIFT_CPUMGQ_TX_TIMER_EARLY_V1) &                         \
+	 BIT_MASK_CPUMGQ_TX_TIMER_EARLY_V1)
+#define BIT_SET_CPUMGQ_TX_TIMER_EARLY_V1(x, v)                                 \
+	(BIT_CLEAR_CPUMGQ_TX_TIMER_EARLY_V1(x) |                               \
+	 BIT_CPUMGQ_TX_TIMER_EARLY_V1(v))
+
+#define BIT_CPUMGQ_TIMER_EN_V1 BIT(7)
+#define BIT_CPUMGQ_DROP_BY_HOLDTIME BIT(5)
+#define BIT_CPUMGQ_TX_EN_V1 BIT(4)
+
+#define BIT_SHIFT_CPUMGQ_TIMER_TSF_SEL_V1 0
+#define BIT_MASK_CPUMGQ_TIMER_TSF_SEL_V1 0x7
+#define BIT_CPUMGQ_TIMER_TSF_SEL_V1(x)                                         \
+	(((x) & BIT_MASK_CPUMGQ_TIMER_TSF_SEL_V1)                              \
+	 << BIT_SHIFT_CPUMGQ_TIMER_TSF_SEL_V1)
+#define BITS_CPUMGQ_TIMER_TSF_SEL_V1                                           \
+	(BIT_MASK_CPUMGQ_TIMER_TSF_SEL_V1 << BIT_SHIFT_CPUMGQ_TIMER_TSF_SEL_V1)
+#define BIT_CLEAR_CPUMGQ_TIMER_TSF_SEL_V1(x)                                   \
+	((x) & (~BITS_CPUMGQ_TIMER_TSF_SEL_V1))
+#define BIT_GET_CPUMGQ_TIMER_TSF_SEL_V1(x)                                     \
+	(((x) >> BIT_SHIFT_CPUMGQ_TIMER_TSF_SEL_V1) &                          \
+	 BIT_MASK_CPUMGQ_TIMER_TSF_SEL_V1)
+#define BIT_SET_CPUMGQ_TIMER_TSF_SEL_V1(x, v)                                  \
+	(BIT_CLEAR_CPUMGQ_TIMER_TSF_SEL_V1(x) | BIT_CPUMGQ_TIMER_TSF_SEL_V1(v))
+
+/* 2 REG_CPUMGQ_PROHIBIT			(Offset 0x15B4) */
+
+#define BIT_SHIFT_CPUMGQ_HOLD_TIME 8
+#define BIT_MASK_CPUMGQ_HOLD_TIME 0xfff
+#define BIT_CPUMGQ_HOLD_TIME(x)                                                \
+	(((x) & BIT_MASK_CPUMGQ_HOLD_TIME) << BIT_SHIFT_CPUMGQ_HOLD_TIME)
+#define BITS_CPUMGQ_HOLD_TIME                                                  \
+	(BIT_MASK_CPUMGQ_HOLD_TIME << BIT_SHIFT_CPUMGQ_HOLD_TIME)
+#define BIT_CLEAR_CPUMGQ_HOLD_TIME(x) ((x) & (~BITS_CPUMGQ_HOLD_TIME))
+#define BIT_GET_CPUMGQ_HOLD_TIME(x)                                            \
+	(((x) >> BIT_SHIFT_CPUMGQ_HOLD_TIME) & BIT_MASK_CPUMGQ_HOLD_TIME)
+#define BIT_SET_CPUMGQ_HOLD_TIME(x, v)                                         \
+	(BIT_CLEAR_CPUMGQ_HOLD_TIME(x) | BIT_CPUMGQ_HOLD_TIME(v))
+
+#define BIT_SHIFT_CPUMGQ_PROHIBIT_SETUP 0
+#define BIT_MASK_CPUMGQ_PROHIBIT_SETUP 0xf
+#define BIT_CPUMGQ_PROHIBIT_SETUP(x)                                           \
+	(((x) & BIT_MASK_CPUMGQ_PROHIBIT_SETUP)                                \
+	 << BIT_SHIFT_CPUMGQ_PROHIBIT_SETUP)
+#define BITS_CPUMGQ_PROHIBIT_SETUP                                             \
+	(BIT_MASK_CPUMGQ_PROHIBIT_SETUP << BIT_SHIFT_CPUMGQ_PROHIBIT_SETUP)
+#define BIT_CLEAR_CPUMGQ_PROHIBIT_SETUP(x) ((x) & (~BITS_CPUMGQ_PROHIBIT_SETUP))
+#define BIT_GET_CPUMGQ_PROHIBIT_SETUP(x)                                       \
+	(((x) >> BIT_SHIFT_CPUMGQ_PROHIBIT_SETUP) &                            \
+	 BIT_MASK_CPUMGQ_PROHIBIT_SETUP)
+#define BIT_SET_CPUMGQ_PROHIBIT_SETUP(x, v)                                    \
+	(BIT_CLEAR_CPUMGQ_PROHIBIT_SETUP(x) | BIT_CPUMGQ_PROHIBIT_SETUP(v))
+
+/* 2 REG_TIMER_COMPARE			(Offset 0x15C0) */
+
+#define BIT_COMP_TRIGGER BIT(7)
+
+#define BIT_SHIFT_Y_COMP 4
+#define BIT_MASK_Y_COMP 0x7
+#define BIT_Y_COMP(x) (((x) & BIT_MASK_Y_COMP) << BIT_SHIFT_Y_COMP)
+#define BITS_Y_COMP (BIT_MASK_Y_COMP << BIT_SHIFT_Y_COMP)
+#define BIT_CLEAR_Y_COMP(x) ((x) & (~BITS_Y_COMP))
+#define BIT_GET_Y_COMP(x) (((x) >> BIT_SHIFT_Y_COMP) & BIT_MASK_Y_COMP)
+#define BIT_SET_Y_COMP(x, v) (BIT_CLEAR_Y_COMP(x) | BIT_Y_COMP(v))
+
+#define BIT_X_COMP_Y_OVERFLOW BIT(3)
+
+#define BIT_SHIFT_X_COMP 0
+#define BIT_MASK_X_COMP 0x7
+#define BIT_X_COMP(x) (((x) & BIT_MASK_X_COMP) << BIT_SHIFT_X_COMP)
+#define BITS_X_COMP (BIT_MASK_X_COMP << BIT_SHIFT_X_COMP)
+#define BIT_CLEAR_X_COMP(x) ((x) & (~BITS_X_COMP))
+#define BIT_GET_X_COMP(x) (((x) >> BIT_SHIFT_X_COMP) & BIT_MASK_X_COMP)
+#define BIT_SET_X_COMP(x, v) (BIT_CLEAR_X_COMP(x) | BIT_X_COMP(v))
+
+/* 2 REG_TIMER_COMPARE_VALUE_LOW		(Offset 0x15C4) */
+
+#define BIT_SHIFT_COMP_VALUE_LOW 0
+#define BIT_MASK_COMP_VALUE_LOW 0xffffffffL
+#define BIT_COMP_VALUE_LOW(x)                                                  \
+	(((x) & BIT_MASK_COMP_VALUE_LOW) << BIT_SHIFT_COMP_VALUE_LOW)
+#define BITS_COMP_VALUE_LOW                                                    \
+	(BIT_MASK_COMP_VALUE_LOW << BIT_SHIFT_COMP_VALUE_LOW)
+#define BIT_CLEAR_COMP_VALUE_LOW(x) ((x) & (~BITS_COMP_VALUE_LOW))
+#define BIT_GET_COMP_VALUE_LOW(x)                                              \
+	(((x) >> BIT_SHIFT_COMP_VALUE_LOW) & BIT_MASK_COMP_VALUE_LOW)
+#define BIT_SET_COMP_VALUE_LOW(x, v)                                           \
+	(BIT_CLEAR_COMP_VALUE_LOW(x) | BIT_COMP_VALUE_LOW(v))
+
+/* 2 REG_TIMER_COMPARE_VALUE_HIGH		(Offset 0x15C8) */
+
+#define BIT_SHIFT_COMP_VALUE_HIGH 0
+#define BIT_MASK_COMP_VALUE_HIGH 0xffffffffL
+#define BIT_COMP_VALUE_HIGH(x)                                                 \
+	(((x) & BIT_MASK_COMP_VALUE_HIGH) << BIT_SHIFT_COMP_VALUE_HIGH)
+#define BITS_COMP_VALUE_HIGH                                                   \
+	(BIT_MASK_COMP_VALUE_HIGH << BIT_SHIFT_COMP_VALUE_HIGH)
+#define BIT_CLEAR_COMP_VALUE_HIGH(x) ((x) & (~BITS_COMP_VALUE_HIGH))
+#define BIT_GET_COMP_VALUE_HIGH(x)                                             \
+	(((x) >> BIT_SHIFT_COMP_VALUE_HIGH) & BIT_MASK_COMP_VALUE_HIGH)
+#define BIT_SET_COMP_VALUE_HIGH(x, v)                                          \
+	(BIT_CLEAR_COMP_VALUE_HIGH(x) | BIT_COMP_VALUE_HIGH(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_SCHEDULER_COUNTER			(Offset 0x15D0) */
+
+#define BIT_SHIFT__SCHEDULER_COUNTER 16
+#define BIT_MASK__SCHEDULER_COUNTER 0xffff
+#define BIT__SCHEDULER_COUNTER(x)                                              \
+	(((x) & BIT_MASK__SCHEDULER_COUNTER) << BIT_SHIFT__SCHEDULER_COUNTER)
+#define BITS__SCHEDULER_COUNTER                                                \
+	(BIT_MASK__SCHEDULER_COUNTER << BIT_SHIFT__SCHEDULER_COUNTER)
+#define BIT_CLEAR__SCHEDULER_COUNTER(x) ((x) & (~BITS__SCHEDULER_COUNTER))
+#define BIT_GET__SCHEDULER_COUNTER(x)                                          \
+	(((x) >> BIT_SHIFT__SCHEDULER_COUNTER) & BIT_MASK__SCHEDULER_COUNTER)
+#define BIT_SET__SCHEDULER_COUNTER(x, v)                                       \
+	(BIT_CLEAR__SCHEDULER_COUNTER(x) | BIT__SCHEDULER_COUNTER(v))
+
+#define BIT__SCHEDULER_COUNTER_RST BIT(8)
+
+#define BIT_SHIFT_SCHEDULER_COUNTER_SEL 0
+#define BIT_MASK_SCHEDULER_COUNTER_SEL 0xff
+#define BIT_SCHEDULER_COUNTER_SEL(x)                                           \
+	(((x) & BIT_MASK_SCHEDULER_COUNTER_SEL)                                \
+	 << BIT_SHIFT_SCHEDULER_COUNTER_SEL)
+#define BITS_SCHEDULER_COUNTER_SEL                                             \
+	(BIT_MASK_SCHEDULER_COUNTER_SEL << BIT_SHIFT_SCHEDULER_COUNTER_SEL)
+#define BIT_CLEAR_SCHEDULER_COUNTER_SEL(x) ((x) & (~BITS_SCHEDULER_COUNTER_SEL))
+#define BIT_GET_SCHEDULER_COUNTER_SEL(x)                                       \
+	(((x) >> BIT_SHIFT_SCHEDULER_COUNTER_SEL) &                            \
+	 BIT_MASK_SCHEDULER_COUNTER_SEL)
+#define BIT_SET_SCHEDULER_COUNTER_SEL(x, v)                                    \
+	(BIT_CLEAR_SCHEDULER_COUNTER_SEL(x) | BIT_SCHEDULER_COUNTER_SEL(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_BCN_PSR_RPT2			(Offset 0x1600) */
+
+#define BIT_SHIFT_DTIM_CNT2 24
+#define BIT_MASK_DTIM_CNT2 0xff
+#define BIT_DTIM_CNT2(x) (((x) & BIT_MASK_DTIM_CNT2) << BIT_SHIFT_DTIM_CNT2)
+#define BITS_DTIM_CNT2 (BIT_MASK_DTIM_CNT2 << BIT_SHIFT_DTIM_CNT2)
+#define BIT_CLEAR_DTIM_CNT2(x) ((x) & (~BITS_DTIM_CNT2))
+#define BIT_GET_DTIM_CNT2(x) (((x) >> BIT_SHIFT_DTIM_CNT2) & BIT_MASK_DTIM_CNT2)
+#define BIT_SET_DTIM_CNT2(x, v) (BIT_CLEAR_DTIM_CNT2(x) | BIT_DTIM_CNT2(v))
+
+#define BIT_SHIFT_DTIM_PERIOD2 16
+#define BIT_MASK_DTIM_PERIOD2 0xff
+#define BIT_DTIM_PERIOD2(x)                                                    \
+	(((x) & BIT_MASK_DTIM_PERIOD2) << BIT_SHIFT_DTIM_PERIOD2)
+#define BITS_DTIM_PERIOD2 (BIT_MASK_DTIM_PERIOD2 << BIT_SHIFT_DTIM_PERIOD2)
+#define BIT_CLEAR_DTIM_PERIOD2(x) ((x) & (~BITS_DTIM_PERIOD2))
+#define BIT_GET_DTIM_PERIOD2(x)                                                \
+	(((x) >> BIT_SHIFT_DTIM_PERIOD2) & BIT_MASK_DTIM_PERIOD2)
+#define BIT_SET_DTIM_PERIOD2(x, v)                                             \
+	(BIT_CLEAR_DTIM_PERIOD2(x) | BIT_DTIM_PERIOD2(v))
+
+#define BIT_DTIM2 BIT(15)
+#define BIT_TIM2 BIT(14)
+
+#define BIT_SHIFT_PS_AID_2 0
+#define BIT_MASK_PS_AID_2 0x7ff
+#define BIT_PS_AID_2(x) (((x) & BIT_MASK_PS_AID_2) << BIT_SHIFT_PS_AID_2)
+#define BITS_PS_AID_2 (BIT_MASK_PS_AID_2 << BIT_SHIFT_PS_AID_2)
+#define BIT_CLEAR_PS_AID_2(x) ((x) & (~BITS_PS_AID_2))
+#define BIT_GET_PS_AID_2(x) (((x) >> BIT_SHIFT_PS_AID_2) & BIT_MASK_PS_AID_2)
+#define BIT_SET_PS_AID_2(x, v) (BIT_CLEAR_PS_AID_2(x) | BIT_PS_AID_2(v))
+
+/* 2 REG_BCN_PSR_RPT3			(Offset 0x1604) */
+
+#define BIT_SHIFT_DTIM_CNT3 24
+#define BIT_MASK_DTIM_CNT3 0xff
+#define BIT_DTIM_CNT3(x) (((x) & BIT_MASK_DTIM_CNT3) << BIT_SHIFT_DTIM_CNT3)
+#define BITS_DTIM_CNT3 (BIT_MASK_DTIM_CNT3 << BIT_SHIFT_DTIM_CNT3)
+#define BIT_CLEAR_DTIM_CNT3(x) ((x) & (~BITS_DTIM_CNT3))
+#define BIT_GET_DTIM_CNT3(x) (((x) >> BIT_SHIFT_DTIM_CNT3) & BIT_MASK_DTIM_CNT3)
+#define BIT_SET_DTIM_CNT3(x, v) (BIT_CLEAR_DTIM_CNT3(x) | BIT_DTIM_CNT3(v))
+
+#define BIT_SHIFT_DTIM_PERIOD3 16
+#define BIT_MASK_DTIM_PERIOD3 0xff
+#define BIT_DTIM_PERIOD3(x)                                                    \
+	(((x) & BIT_MASK_DTIM_PERIOD3) << BIT_SHIFT_DTIM_PERIOD3)
+#define BITS_DTIM_PERIOD3 (BIT_MASK_DTIM_PERIOD3 << BIT_SHIFT_DTIM_PERIOD3)
+#define BIT_CLEAR_DTIM_PERIOD3(x) ((x) & (~BITS_DTIM_PERIOD3))
+#define BIT_GET_DTIM_PERIOD3(x)                                                \
+	(((x) >> BIT_SHIFT_DTIM_PERIOD3) & BIT_MASK_DTIM_PERIOD3)
+#define BIT_SET_DTIM_PERIOD3(x, v)                                             \
+	(BIT_CLEAR_DTIM_PERIOD3(x) | BIT_DTIM_PERIOD3(v))
+
+#define BIT_DTIM3 BIT(15)
+#define BIT_TIM3 BIT(14)
+
+#define BIT_SHIFT_PS_AID_3 0
+#define BIT_MASK_PS_AID_3 0x7ff
+#define BIT_PS_AID_3(x) (((x) & BIT_MASK_PS_AID_3) << BIT_SHIFT_PS_AID_3)
+#define BITS_PS_AID_3 (BIT_MASK_PS_AID_3 << BIT_SHIFT_PS_AID_3)
+#define BIT_CLEAR_PS_AID_3(x) ((x) & (~BITS_PS_AID_3))
+#define BIT_GET_PS_AID_3(x) (((x) >> BIT_SHIFT_PS_AID_3) & BIT_MASK_PS_AID_3)
+#define BIT_SET_PS_AID_3(x, v) (BIT_CLEAR_PS_AID_3(x) | BIT_PS_AID_3(v))
+
+/* 2 REG_BCN_PSR_RPT4			(Offset 0x1608) */
+
+#define BIT_SHIFT_DTIM_CNT4 24
+#define BIT_MASK_DTIM_CNT4 0xff
+#define BIT_DTIM_CNT4(x) (((x) & BIT_MASK_DTIM_CNT4) << BIT_SHIFT_DTIM_CNT4)
+#define BITS_DTIM_CNT4 (BIT_MASK_DTIM_CNT4 << BIT_SHIFT_DTIM_CNT4)
+#define BIT_CLEAR_DTIM_CNT4(x) ((x) & (~BITS_DTIM_CNT4))
+#define BIT_GET_DTIM_CNT4(x) (((x) >> BIT_SHIFT_DTIM_CNT4) & BIT_MASK_DTIM_CNT4)
+#define BIT_SET_DTIM_CNT4(x, v) (BIT_CLEAR_DTIM_CNT4(x) | BIT_DTIM_CNT4(v))
+
+#define BIT_SHIFT_DTIM_PERIOD4 16
+#define BIT_MASK_DTIM_PERIOD4 0xff
+#define BIT_DTIM_PERIOD4(x)                                                    \
+	(((x) & BIT_MASK_DTIM_PERIOD4) << BIT_SHIFT_DTIM_PERIOD4)
+#define BITS_DTIM_PERIOD4 (BIT_MASK_DTIM_PERIOD4 << BIT_SHIFT_DTIM_PERIOD4)
+#define BIT_CLEAR_DTIM_PERIOD4(x) ((x) & (~BITS_DTIM_PERIOD4))
+#define BIT_GET_DTIM_PERIOD4(x)                                                \
+	(((x) >> BIT_SHIFT_DTIM_PERIOD4) & BIT_MASK_DTIM_PERIOD4)
+#define BIT_SET_DTIM_PERIOD4(x, v)                                             \
+	(BIT_CLEAR_DTIM_PERIOD4(x) | BIT_DTIM_PERIOD4(v))
+
+#define BIT_DTIM4 BIT(15)
+#define BIT_TIM4 BIT(14)
+
+#define BIT_SHIFT_PS_AID_4 0
+#define BIT_MASK_PS_AID_4 0x7ff
+#define BIT_PS_AID_4(x) (((x) & BIT_MASK_PS_AID_4) << BIT_SHIFT_PS_AID_4)
+#define BITS_PS_AID_4 (BIT_MASK_PS_AID_4 << BIT_SHIFT_PS_AID_4)
+#define BIT_CLEAR_PS_AID_4(x) ((x) & (~BITS_PS_AID_4))
+#define BIT_GET_PS_AID_4(x) (((x) >> BIT_SHIFT_PS_AID_4) & BIT_MASK_PS_AID_4)
+#define BIT_SET_PS_AID_4(x, v) (BIT_CLEAR_PS_AID_4(x) | BIT_PS_AID_4(v))
+
+/* 2 REG_A1_ADDR_MASK			(Offset 0x160C) */
+
+#define BIT_SHIFT_A1_ADDR_MASK 0
+#define BIT_MASK_A1_ADDR_MASK 0xffffffffL
+#define BIT_A1_ADDR_MASK(x)                                                    \
+	(((x) & BIT_MASK_A1_ADDR_MASK) << BIT_SHIFT_A1_ADDR_MASK)
+#define BITS_A1_ADDR_MASK (BIT_MASK_A1_ADDR_MASK << BIT_SHIFT_A1_ADDR_MASK)
+#define BIT_CLEAR_A1_ADDR_MASK(x) ((x) & (~BITS_A1_ADDR_MASK))
+#define BIT_GET_A1_ADDR_MASK(x)                                                \
+	(((x) >> BIT_SHIFT_A1_ADDR_MASK) & BIT_MASK_A1_ADDR_MASK)
+#define BIT_SET_A1_ADDR_MASK(x, v)                                             \
+	(BIT_CLEAR_A1_ADDR_MASK(x) | BIT_A1_ADDR_MASK(v))
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_RXPSF_CTRL				(Offset 0x1610) */
+
+#define BIT_RXGCK_FIFOTHR_EN BIT(28)
+
+#define BIT_SHIFT_RXGCK_VHT_FIFOTHR 26
+#define BIT_MASK_RXGCK_VHT_FIFOTHR 0x3
+#define BIT_RXGCK_VHT_FIFOTHR(x)                                               \
+	(((x) & BIT_MASK_RXGCK_VHT_FIFOTHR) << BIT_SHIFT_RXGCK_VHT_FIFOTHR)
+#define BITS_RXGCK_VHT_FIFOTHR                                                 \
+	(BIT_MASK_RXGCK_VHT_FIFOTHR << BIT_SHIFT_RXGCK_VHT_FIFOTHR)
+#define BIT_CLEAR_RXGCK_VHT_FIFOTHR(x) ((x) & (~BITS_RXGCK_VHT_FIFOTHR))
+#define BIT_GET_RXGCK_VHT_FIFOTHR(x)                                           \
+	(((x) >> BIT_SHIFT_RXGCK_VHT_FIFOTHR) & BIT_MASK_RXGCK_VHT_FIFOTHR)
+#define BIT_SET_RXGCK_VHT_FIFOTHR(x, v)                                        \
+	(BIT_CLEAR_RXGCK_VHT_FIFOTHR(x) | BIT_RXGCK_VHT_FIFOTHR(v))
+
+#define BIT_SHIFT_RXGCK_HT_FIFOTHR 24
+#define BIT_MASK_RXGCK_HT_FIFOTHR 0x3
+#define BIT_RXGCK_HT_FIFOTHR(x)                                                \
+	(((x) & BIT_MASK_RXGCK_HT_FIFOTHR) << BIT_SHIFT_RXGCK_HT_FIFOTHR)
+#define BITS_RXGCK_HT_FIFOTHR                                                  \
+	(BIT_MASK_RXGCK_HT_FIFOTHR << BIT_SHIFT_RXGCK_HT_FIFOTHR)
+#define BIT_CLEAR_RXGCK_HT_FIFOTHR(x) ((x) & (~BITS_RXGCK_HT_FIFOTHR))
+#define BIT_GET_RXGCK_HT_FIFOTHR(x)                                            \
+	(((x) >> BIT_SHIFT_RXGCK_HT_FIFOTHR) & BIT_MASK_RXGCK_HT_FIFOTHR)
+#define BIT_SET_RXGCK_HT_FIFOTHR(x, v)                                         \
+	(BIT_CLEAR_RXGCK_HT_FIFOTHR(x) | BIT_RXGCK_HT_FIFOTHR(v))
+
+#define BIT_SHIFT_RXGCK_OFDM_FIFOTHR 22
+#define BIT_MASK_RXGCK_OFDM_FIFOTHR 0x3
+#define BIT_RXGCK_OFDM_FIFOTHR(x)                                              \
+	(((x) & BIT_MASK_RXGCK_OFDM_FIFOTHR) << BIT_SHIFT_RXGCK_OFDM_FIFOTHR)
+#define BITS_RXGCK_OFDM_FIFOTHR                                                \
+	(BIT_MASK_RXGCK_OFDM_FIFOTHR << BIT_SHIFT_RXGCK_OFDM_FIFOTHR)
+#define BIT_CLEAR_RXGCK_OFDM_FIFOTHR(x) ((x) & (~BITS_RXGCK_OFDM_FIFOTHR))
+#define BIT_GET_RXGCK_OFDM_FIFOTHR(x)                                          \
+	(((x) >> BIT_SHIFT_RXGCK_OFDM_FIFOTHR) & BIT_MASK_RXGCK_OFDM_FIFOTHR)
+#define BIT_SET_RXGCK_OFDM_FIFOTHR(x, v)                                       \
+	(BIT_CLEAR_RXGCK_OFDM_FIFOTHR(x) | BIT_RXGCK_OFDM_FIFOTHR(v))
+
+#define BIT_SHIFT_RXGCK_CCK_FIFOTHR 20
+#define BIT_MASK_RXGCK_CCK_FIFOTHR 0x3
+#define BIT_RXGCK_CCK_FIFOTHR(x)                                               \
+	(((x) & BIT_MASK_RXGCK_CCK_FIFOTHR) << BIT_SHIFT_RXGCK_CCK_FIFOTHR)
+#define BITS_RXGCK_CCK_FIFOTHR                                                 \
+	(BIT_MASK_RXGCK_CCK_FIFOTHR << BIT_SHIFT_RXGCK_CCK_FIFOTHR)
+#define BIT_CLEAR_RXGCK_CCK_FIFOTHR(x) ((x) & (~BITS_RXGCK_CCK_FIFOTHR))
+#define BIT_GET_RXGCK_CCK_FIFOTHR(x)                                           \
+	(((x) >> BIT_SHIFT_RXGCK_CCK_FIFOTHR) & BIT_MASK_RXGCK_CCK_FIFOTHR)
+#define BIT_SET_RXGCK_CCK_FIFOTHR(x, v)                                        \
+	(BIT_CLEAR_RXGCK_CCK_FIFOTHR(x) | BIT_RXGCK_CCK_FIFOTHR(v))
+
+#define BIT_SHIFT_RXGCK_ENTRY_DELAY 17
+#define BIT_MASK_RXGCK_ENTRY_DELAY 0x7
+#define BIT_RXGCK_ENTRY_DELAY(x)                                               \
+	(((x) & BIT_MASK_RXGCK_ENTRY_DELAY) << BIT_SHIFT_RXGCK_ENTRY_DELAY)
+#define BITS_RXGCK_ENTRY_DELAY                                                 \
+	(BIT_MASK_RXGCK_ENTRY_DELAY << BIT_SHIFT_RXGCK_ENTRY_DELAY)
+#define BIT_CLEAR_RXGCK_ENTRY_DELAY(x) ((x) & (~BITS_RXGCK_ENTRY_DELAY))
+#define BIT_GET_RXGCK_ENTRY_DELAY(x)                                           \
+	(((x) >> BIT_SHIFT_RXGCK_ENTRY_DELAY) & BIT_MASK_RXGCK_ENTRY_DELAY)
+#define BIT_SET_RXGCK_ENTRY_DELAY(x, v)                                        \
+	(BIT_CLEAR_RXGCK_ENTRY_DELAY(x) | BIT_RXGCK_ENTRY_DELAY(v))
+
+#define BIT_RXGCK_OFDMCCA_EN BIT(16)
+
+#define BIT_SHIFT_RXPSF_PKTLENTHR 13
+#define BIT_MASK_RXPSF_PKTLENTHR 0x7
+#define BIT_RXPSF_PKTLENTHR(x)                                                 \
+	(((x) & BIT_MASK_RXPSF_PKTLENTHR) << BIT_SHIFT_RXPSF_PKTLENTHR)
+#define BITS_RXPSF_PKTLENTHR                                                   \
+	(BIT_MASK_RXPSF_PKTLENTHR << BIT_SHIFT_RXPSF_PKTLENTHR)
+#define BIT_CLEAR_RXPSF_PKTLENTHR(x) ((x) & (~BITS_RXPSF_PKTLENTHR))
+#define BIT_GET_RXPSF_PKTLENTHR(x)                                             \
+	(((x) >> BIT_SHIFT_RXPSF_PKTLENTHR) & BIT_MASK_RXPSF_PKTLENTHR)
+#define BIT_SET_RXPSF_PKTLENTHR(x, v)                                          \
+	(BIT_CLEAR_RXPSF_PKTLENTHR(x) | BIT_RXPSF_PKTLENTHR(v))
+
+#define BIT_RXPSF_CTRLEN BIT(12)
+#define BIT_RXPSF_VHTCHKEN BIT(11)
+#define BIT_RXPSF_HTCHKEN BIT(10)
+#define BIT_RXPSF_OFDMCHKEN BIT(9)
+#define BIT_RXPSF_CCKCHKEN BIT(8)
+#define BIT_RXPSF_OFDMRST BIT(7)
+#define BIT_RXPSF_CCKRST BIT(6)
+#define BIT_RXPSF_MHCHKEN BIT(5)
+#define BIT_RXPSF_CONT_ERRCHKEN BIT(4)
+#define BIT_RXPSF_ALL_ERRCHKEN BIT(3)
+
+#define BIT_SHIFT_RXPSF_ERRTHR 0
+#define BIT_MASK_RXPSF_ERRTHR 0x7
+#define BIT_RXPSF_ERRTHR(x)                                                    \
+	(((x) & BIT_MASK_RXPSF_ERRTHR) << BIT_SHIFT_RXPSF_ERRTHR)
+#define BITS_RXPSF_ERRTHR (BIT_MASK_RXPSF_ERRTHR << BIT_SHIFT_RXPSF_ERRTHR)
+#define BIT_CLEAR_RXPSF_ERRTHR(x) ((x) & (~BITS_RXPSF_ERRTHR))
+#define BIT_GET_RXPSF_ERRTHR(x)                                                \
+	(((x) >> BIT_SHIFT_RXPSF_ERRTHR) & BIT_MASK_RXPSF_ERRTHR)
+#define BIT_SET_RXPSF_ERRTHR(x, v)                                             \
+	(BIT_CLEAR_RXPSF_ERRTHR(x) | BIT_RXPSF_ERRTHR(v))
+
+/* 2 REG_RXPSF_TYPE_CTRL			(Offset 0x1614) */
+
+#define BIT_RXPSF_DATA15EN BIT(31)
+#define BIT_RXPSF_DATA14EN BIT(30)
+#define BIT_RXPSF_DATA13EN BIT(29)
+#define BIT_RXPSF_DATA12EN BIT(28)
+#define BIT_RXPSF_DATA11EN BIT(27)
+#define BIT_RXPSF_DATA10EN BIT(26)
+#define BIT_RXPSF_DATA9EN BIT(25)
+#define BIT_RXPSF_DATA8EN BIT(24)
+#define BIT_RXPSF_DATA7EN BIT(23)
+#define BIT_RXPSF_DATA6EN BIT(22)
+#define BIT_RXPSF_DATA5EN BIT(21)
+#define BIT_RXPSF_DATA4EN BIT(20)
+#define BIT_RXPSF_DATA3EN BIT(19)
+#define BIT_RXPSF_DATA2EN BIT(18)
+#define BIT_RXPSF_DATA1EN BIT(17)
+#define BIT_RXPSF_DATA0EN BIT(16)
+#define BIT_RXPSF_MGT15EN BIT(15)
+#define BIT_RXPSF_MGT14EN BIT(14)
+#define BIT_RXPSF_MGT13EN BIT(13)
+#define BIT_RXPSF_MGT12EN BIT(12)
+#define BIT_RXPSF_MGT11EN BIT(11)
+#define BIT_RXPSF_MGT10EN BIT(10)
+#define BIT_RXPSF_MGT9EN BIT(9)
+#define BIT_RXPSF_MGT8EN BIT(8)
+#define BIT_RXPSF_MGT7EN BIT(7)
+#define BIT_RXPSF_MGT6EN BIT(6)
+#define BIT_RXPSF_MGT5EN BIT(5)
+#define BIT_RXPSF_MGT4EN BIT(4)
+#define BIT_RXPSF_MGT3EN BIT(3)
+#define BIT_RXPSF_MGT2EN BIT(2)
+#define BIT_RXPSF_MGT1EN BIT(1)
+#define BIT_RXPSF_MGT0EN BIT(0)
+
+/* 2 REG_CAM_ACCESS_CTRL			(Offset 0x1618) */
+
+#define BIT_INDIRECT_ERR BIT(6)
+#define BIT_DIRECT_ERR BIT(5)
+#define BIT_DIR_ACCESS_EN_RX_BA BIT(4)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_CAM_ACCESS_CTRL			(Offset 0x1618) */
+
+#define BIT_DIR_ACCESS_EN_MBSSIDCAM BIT(3)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_CAM_ACCESS_CTRL			(Offset 0x1618) */
+
+#define BIT_DIR_ACCESS_EN_ADDRCAM BIT(3)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_CAM_ACCESS_CTRL			(Offset 0x1618) */
+
+#define BIT_DIR_ACCESS_EN_KEY BIT(2)
+#define BIT_DIR_ACCESS_EN_WOWLAN BIT(1)
+#define BIT_DIR_ACCESS_EN_FW_FILTER BIT(0)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_CUT_AMSDU_CTRL			(Offset 0x161C) */
+
+#define BIT__CUT_AMSDU_CHKLEN_EN BIT(31)
+#define BIT_EN_CUT_AMSDU BIT(30)
+
+#define BIT_SHIFT_CUT_AMSDU_CHKLEN_L_TH 16
+#define BIT_MASK_CUT_AMSDU_CHKLEN_L_TH 0xff
+#define BIT_CUT_AMSDU_CHKLEN_L_TH(x)                                           \
+	(((x) & BIT_MASK_CUT_AMSDU_CHKLEN_L_TH)                                \
+	 << BIT_SHIFT_CUT_AMSDU_CHKLEN_L_TH)
+#define BITS_CUT_AMSDU_CHKLEN_L_TH                                             \
+	(BIT_MASK_CUT_AMSDU_CHKLEN_L_TH << BIT_SHIFT_CUT_AMSDU_CHKLEN_L_TH)
+#define BIT_CLEAR_CUT_AMSDU_CHKLEN_L_TH(x) ((x) & (~BITS_CUT_AMSDU_CHKLEN_L_TH))
+#define BIT_GET_CUT_AMSDU_CHKLEN_L_TH(x)                                       \
+	(((x) >> BIT_SHIFT_CUT_AMSDU_CHKLEN_L_TH) &                            \
+	 BIT_MASK_CUT_AMSDU_CHKLEN_L_TH)
+#define BIT_SET_CUT_AMSDU_CHKLEN_L_TH(x, v)                                    \
+	(BIT_CLEAR_CUT_AMSDU_CHKLEN_L_TH(x) | BIT_CUT_AMSDU_CHKLEN_L_TH(v))
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_HT_SND_REF_RATE			(Offset 0x161C) */
+
+#define BIT_SHIFT_WMAC_HT_CSI_RATE 0
+#define BIT_MASK_WMAC_HT_CSI_RATE 0x3f
+#define BIT_WMAC_HT_CSI_RATE(x)                                                \
+	(((x) & BIT_MASK_WMAC_HT_CSI_RATE) << BIT_SHIFT_WMAC_HT_CSI_RATE)
+#define BITS_WMAC_HT_CSI_RATE                                                  \
+	(BIT_MASK_WMAC_HT_CSI_RATE << BIT_SHIFT_WMAC_HT_CSI_RATE)
+#define BIT_CLEAR_WMAC_HT_CSI_RATE(x) ((x) & (~BITS_WMAC_HT_CSI_RATE))
+#define BIT_GET_WMAC_HT_CSI_RATE(x)                                            \
+	(((x) >> BIT_SHIFT_WMAC_HT_CSI_RATE) & BIT_MASK_WMAC_HT_CSI_RATE)
+#define BIT_SET_WMAC_HT_CSI_RATE(x, v)                                         \
+	(BIT_CLEAR_WMAC_HT_CSI_RATE(x) | BIT_WMAC_HT_CSI_RATE(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_CUT_AMSDU_CTRL			(Offset 0x161C) */
+
+#define BIT_SHIFT_CUT_AMSDU_CHKLEN_H_TH 0
+#define BIT_MASK_CUT_AMSDU_CHKLEN_H_TH 0xffff
+#define BIT_CUT_AMSDU_CHKLEN_H_TH(x)                                           \
+	(((x) & BIT_MASK_CUT_AMSDU_CHKLEN_H_TH)                                \
+	 << BIT_SHIFT_CUT_AMSDU_CHKLEN_H_TH)
+#define BITS_CUT_AMSDU_CHKLEN_H_TH                                             \
+	(BIT_MASK_CUT_AMSDU_CHKLEN_H_TH << BIT_SHIFT_CUT_AMSDU_CHKLEN_H_TH)
+#define BIT_CLEAR_CUT_AMSDU_CHKLEN_H_TH(x) ((x) & (~BITS_CUT_AMSDU_CHKLEN_H_TH))
+#define BIT_GET_CUT_AMSDU_CHKLEN_H_TH(x)                                       \
+	(((x) >> BIT_SHIFT_CUT_AMSDU_CHKLEN_H_TH) &                            \
+	 BIT_MASK_CUT_AMSDU_CHKLEN_H_TH)
+#define BIT_SET_CUT_AMSDU_CHKLEN_H_TH(x, v)                                    \
+	(BIT_CLEAR_CUT_AMSDU_CHKLEN_H_TH(x) | BIT_CUT_AMSDU_CHKLEN_H_TH(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT)
+
+/* 2 REG_MACID2				(Offset 0x1620) */
+
+#define BIT_SHIFT_MACID2 0
+#define BIT_MASK_MACID2 0xffffffffffffL
+#define BIT_MACID2(x) (((x) & BIT_MASK_MACID2) << BIT_SHIFT_MACID2)
+#define BITS_MACID2 (BIT_MASK_MACID2 << BIT_SHIFT_MACID2)
+#define BIT_CLEAR_MACID2(x) ((x) & (~BITS_MACID2))
+#define BIT_GET_MACID2(x) (((x) >> BIT_SHIFT_MACID2) & BIT_MASK_MACID2)
+#define BIT_SET_MACID2(x, v) (BIT_CLEAR_MACID2(x) | BIT_MACID2(v))
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_MACID2				(Offset 0x1620) */
+
+#define BIT_SHIFT_MACID2_V1 0
+#define BIT_MASK_MACID2_V1 0xffffffffL
+#define BIT_MACID2_V1(x) (((x) & BIT_MASK_MACID2_V1) << BIT_SHIFT_MACID2_V1)
+#define BITS_MACID2_V1 (BIT_MASK_MACID2_V1 << BIT_SHIFT_MACID2_V1)
+#define BIT_CLEAR_MACID2_V1(x) ((x) & (~BITS_MACID2_V1))
+#define BIT_GET_MACID2_V1(x) (((x) >> BIT_SHIFT_MACID2_V1) & BIT_MASK_MACID2_V1)
+#define BIT_SET_MACID2_V1(x, v) (BIT_CLEAR_MACID2_V1(x) | BIT_MACID2_V1(v))
+
+/* 2 REG_MACID2_H				(Offset 0x1624) */
+
+#define BIT_SHIFT_MACID2_H_V1 0
+#define BIT_MASK_MACID2_H_V1 0xffff
+#define BIT_MACID2_H_V1(x)                                                     \
+	(((x) & BIT_MASK_MACID2_H_V1) << BIT_SHIFT_MACID2_H_V1)
+#define BITS_MACID2_H_V1 (BIT_MASK_MACID2_H_V1 << BIT_SHIFT_MACID2_H_V1)
+#define BIT_CLEAR_MACID2_H_V1(x) ((x) & (~BITS_MACID2_H_V1))
+#define BIT_GET_MACID2_H_V1(x)                                                 \
+	(((x) >> BIT_SHIFT_MACID2_H_V1) & BIT_MASK_MACID2_H_V1)
+#define BIT_SET_MACID2_H_V1(x, v)                                              \
+	(BIT_CLEAR_MACID2_H_V1(x) | BIT_MACID2_H_V1(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT)
+
+/* 2 REG_BSSID2				(Offset 0x1628) */
+
+#define BIT_SHIFT_BSSID2 0
+#define BIT_MASK_BSSID2 0xffffffffffffL
+#define BIT_BSSID2(x) (((x) & BIT_MASK_BSSID2) << BIT_SHIFT_BSSID2)
+#define BITS_BSSID2 (BIT_MASK_BSSID2 << BIT_SHIFT_BSSID2)
+#define BIT_CLEAR_BSSID2(x) ((x) & (~BITS_BSSID2))
+#define BIT_GET_BSSID2(x) (((x) >> BIT_SHIFT_BSSID2) & BIT_MASK_BSSID2)
+#define BIT_SET_BSSID2(x, v) (BIT_CLEAR_BSSID2(x) | BIT_BSSID2(v))
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_BSSID2				(Offset 0x1628) */
+
+#define BIT_SHIFT_BSSID2_V1 0
+#define BIT_MASK_BSSID2_V1 0xffffffffL
+#define BIT_BSSID2_V1(x) (((x) & BIT_MASK_BSSID2_V1) << BIT_SHIFT_BSSID2_V1)
+#define BITS_BSSID2_V1 (BIT_MASK_BSSID2_V1 << BIT_SHIFT_BSSID2_V1)
+#define BIT_CLEAR_BSSID2_V1(x) ((x) & (~BITS_BSSID2_V1))
+#define BIT_GET_BSSID2_V1(x) (((x) >> BIT_SHIFT_BSSID2_V1) & BIT_MASK_BSSID2_V1)
+#define BIT_SET_BSSID2_V1(x, v) (BIT_CLEAR_BSSID2_V1(x) | BIT_BSSID2_V1(v))
+
+/* 2 REG_BSSID2_H				(Offset 0x162C) */
+
+#define BIT_SHIFT_BSSID2_H_V1 0
+#define BIT_MASK_BSSID2_H_V1 0xffff
+#define BIT_BSSID2_H_V1(x)                                                     \
+	(((x) & BIT_MASK_BSSID2_H_V1) << BIT_SHIFT_BSSID2_H_V1)
+#define BITS_BSSID2_H_V1 (BIT_MASK_BSSID2_H_V1 << BIT_SHIFT_BSSID2_H_V1)
+#define BIT_CLEAR_BSSID2_H_V1(x) ((x) & (~BITS_BSSID2_H_V1))
+#define BIT_GET_BSSID2_H_V1(x)                                                 \
+	(((x) >> BIT_SHIFT_BSSID2_H_V1) & BIT_MASK_BSSID2_H_V1)
+#define BIT_SET_BSSID2_H_V1(x, v)                                              \
+	(BIT_CLEAR_BSSID2_H_V1(x) | BIT_BSSID2_H_V1(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT)
+
+/* 2 REG_MACID3				(Offset 0x1630) */
+
+#define BIT_SHIFT_MACID3 0
+#define BIT_MASK_MACID3 0xffffffffffffL
+#define BIT_MACID3(x) (((x) & BIT_MASK_MACID3) << BIT_SHIFT_MACID3)
+#define BITS_MACID3 (BIT_MASK_MACID3 << BIT_SHIFT_MACID3)
+#define BIT_CLEAR_MACID3(x) ((x) & (~BITS_MACID3))
+#define BIT_GET_MACID3(x) (((x) >> BIT_SHIFT_MACID3) & BIT_MASK_MACID3)
+#define BIT_SET_MACID3(x, v) (BIT_CLEAR_MACID3(x) | BIT_MACID3(v))
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_MACID3				(Offset 0x1630) */
+
+#define BIT_SHIFT_MACID3_V1 0
+#define BIT_MASK_MACID3_V1 0xffffffffL
+#define BIT_MACID3_V1(x) (((x) & BIT_MASK_MACID3_V1) << BIT_SHIFT_MACID3_V1)
+#define BITS_MACID3_V1 (BIT_MASK_MACID3_V1 << BIT_SHIFT_MACID3_V1)
+#define BIT_CLEAR_MACID3_V1(x) ((x) & (~BITS_MACID3_V1))
+#define BIT_GET_MACID3_V1(x) (((x) >> BIT_SHIFT_MACID3_V1) & BIT_MASK_MACID3_V1)
+#define BIT_SET_MACID3_V1(x, v) (BIT_CLEAR_MACID3_V1(x) | BIT_MACID3_V1(v))
+
+/* 2 REG_MACID3_H				(Offset 0x1634) */
+
+#define BIT_SHIFT_MACID3_H_V1 0
+#define BIT_MASK_MACID3_H_V1 0xffff
+#define BIT_MACID3_H_V1(x)                                                     \
+	(((x) & BIT_MASK_MACID3_H_V1) << BIT_SHIFT_MACID3_H_V1)
+#define BITS_MACID3_H_V1 (BIT_MASK_MACID3_H_V1 << BIT_SHIFT_MACID3_H_V1)
+#define BIT_CLEAR_MACID3_H_V1(x) ((x) & (~BITS_MACID3_H_V1))
+#define BIT_GET_MACID3_H_V1(x)                                                 \
+	(((x) >> BIT_SHIFT_MACID3_H_V1) & BIT_MASK_MACID3_H_V1)
+#define BIT_SET_MACID3_H_V1(x, v)                                              \
+	(BIT_CLEAR_MACID3_H_V1(x) | BIT_MACID3_H_V1(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT)
+
+/* 2 REG_BSSID3				(Offset 0x1638) */
+
+#define BIT_SHIFT_BSSID3 0
+#define BIT_MASK_BSSID3 0xffffffffffffL
+#define BIT_BSSID3(x) (((x) & BIT_MASK_BSSID3) << BIT_SHIFT_BSSID3)
+#define BITS_BSSID3 (BIT_MASK_BSSID3 << BIT_SHIFT_BSSID3)
+#define BIT_CLEAR_BSSID3(x) ((x) & (~BITS_BSSID3))
+#define BIT_GET_BSSID3(x) (((x) >> BIT_SHIFT_BSSID3) & BIT_MASK_BSSID3)
+#define BIT_SET_BSSID3(x, v) (BIT_CLEAR_BSSID3(x) | BIT_BSSID3(v))
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_BSSID3				(Offset 0x1638) */
+
+#define BIT_SHIFT_BSSID3_V1 0
+#define BIT_MASK_BSSID3_V1 0xffffffffL
+#define BIT_BSSID3_V1(x) (((x) & BIT_MASK_BSSID3_V1) << BIT_SHIFT_BSSID3_V1)
+#define BITS_BSSID3_V1 (BIT_MASK_BSSID3_V1 << BIT_SHIFT_BSSID3_V1)
+#define BIT_CLEAR_BSSID3_V1(x) ((x) & (~BITS_BSSID3_V1))
+#define BIT_GET_BSSID3_V1(x) (((x) >> BIT_SHIFT_BSSID3_V1) & BIT_MASK_BSSID3_V1)
+#define BIT_SET_BSSID3_V1(x, v) (BIT_CLEAR_BSSID3_V1(x) | BIT_BSSID3_V1(v))
+
+/* 2 REG_BSSID3_H				(Offset 0x163C) */
+
+#define BIT_SHIFT_BSSID3_H_V1 0
+#define BIT_MASK_BSSID3_H_V1 0xffff
+#define BIT_BSSID3_H_V1(x)                                                     \
+	(((x) & BIT_MASK_BSSID3_H_V1) << BIT_SHIFT_BSSID3_H_V1)
+#define BITS_BSSID3_H_V1 (BIT_MASK_BSSID3_H_V1 << BIT_SHIFT_BSSID3_H_V1)
+#define BIT_CLEAR_BSSID3_H_V1(x) ((x) & (~BITS_BSSID3_H_V1))
+#define BIT_GET_BSSID3_H_V1(x)                                                 \
+	(((x) >> BIT_SHIFT_BSSID3_H_V1) & BIT_MASK_BSSID3_H_V1)
+#define BIT_SET_BSSID3_H_V1(x, v)                                              \
+	(BIT_CLEAR_BSSID3_H_V1(x) | BIT_BSSID3_H_V1(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT)
+
+/* 2 REG_MACID4				(Offset 0x1640) */
+
+#define BIT_SHIFT_MACID4 0
+#define BIT_MASK_MACID4 0xffffffffffffL
+#define BIT_MACID4(x) (((x) & BIT_MASK_MACID4) << BIT_SHIFT_MACID4)
+#define BITS_MACID4 (BIT_MASK_MACID4 << BIT_SHIFT_MACID4)
+#define BIT_CLEAR_MACID4(x) ((x) & (~BITS_MACID4))
+#define BIT_GET_MACID4(x) (((x) >> BIT_SHIFT_MACID4) & BIT_MASK_MACID4)
+#define BIT_SET_MACID4(x, v) (BIT_CLEAR_MACID4(x) | BIT_MACID4(v))
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_MACID4				(Offset 0x1640) */
+
+#define BIT_SHIFT_MACID4_V1 0
+#define BIT_MASK_MACID4_V1 0xffffffffL
+#define BIT_MACID4_V1(x) (((x) & BIT_MASK_MACID4_V1) << BIT_SHIFT_MACID4_V1)
+#define BITS_MACID4_V1 (BIT_MASK_MACID4_V1 << BIT_SHIFT_MACID4_V1)
+#define BIT_CLEAR_MACID4_V1(x) ((x) & (~BITS_MACID4_V1))
+#define BIT_GET_MACID4_V1(x) (((x) >> BIT_SHIFT_MACID4_V1) & BIT_MASK_MACID4_V1)
+#define BIT_SET_MACID4_V1(x, v) (BIT_CLEAR_MACID4_V1(x) | BIT_MACID4_V1(v))
+
+/* 2 REG_MACID4_H				(Offset 0x1644) */
+
+#define BIT_SHIFT_MACID4_H_V1 0
+#define BIT_MASK_MACID4_H_V1 0xffff
+#define BIT_MACID4_H_V1(x)                                                     \
+	(((x) & BIT_MASK_MACID4_H_V1) << BIT_SHIFT_MACID4_H_V1)
+#define BITS_MACID4_H_V1 (BIT_MASK_MACID4_H_V1 << BIT_SHIFT_MACID4_H_V1)
+#define BIT_CLEAR_MACID4_H_V1(x) ((x) & (~BITS_MACID4_H_V1))
+#define BIT_GET_MACID4_H_V1(x)                                                 \
+	(((x) >> BIT_SHIFT_MACID4_H_V1) & BIT_MASK_MACID4_H_V1)
+#define BIT_SET_MACID4_H_V1(x, v)                                              \
+	(BIT_CLEAR_MACID4_H_V1(x) | BIT_MACID4_H_V1(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT)
+
+/* 2 REG_BSSID4				(Offset 0x1648) */
+
+#define BIT_SHIFT_BSSID4 0
+#define BIT_MASK_BSSID4 0xffffffffffffL
+#define BIT_BSSID4(x) (((x) & BIT_MASK_BSSID4) << BIT_SHIFT_BSSID4)
+#define BITS_BSSID4 (BIT_MASK_BSSID4 << BIT_SHIFT_BSSID4)
+#define BIT_CLEAR_BSSID4(x) ((x) & (~BITS_BSSID4))
+#define BIT_GET_BSSID4(x) (((x) >> BIT_SHIFT_BSSID4) & BIT_MASK_BSSID4)
+#define BIT_SET_BSSID4(x, v) (BIT_CLEAR_BSSID4(x) | BIT_BSSID4(v))
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_BSSID4				(Offset 0x1648) */
+
+#define BIT_SHIFT_BSSID4_V1 0
+#define BIT_MASK_BSSID4_V1 0xffffffffL
+#define BIT_BSSID4_V1(x) (((x) & BIT_MASK_BSSID4_V1) << BIT_SHIFT_BSSID4_V1)
+#define BITS_BSSID4_V1 (BIT_MASK_BSSID4_V1 << BIT_SHIFT_BSSID4_V1)
+#define BIT_CLEAR_BSSID4_V1(x) ((x) & (~BITS_BSSID4_V1))
+#define BIT_GET_BSSID4_V1(x) (((x) >> BIT_SHIFT_BSSID4_V1) & BIT_MASK_BSSID4_V1)
+#define BIT_SET_BSSID4_V1(x, v) (BIT_CLEAR_BSSID4_V1(x) | BIT_BSSID4_V1(v))
+
+/* 2 REG_BSSID4_H				(Offset 0x164C) */
+
+#define BIT_SHIFT_BSSID4_H_V1 0
+#define BIT_MASK_BSSID4_H_V1 0xffff
+#define BIT_BSSID4_H_V1(x)                                                     \
+	(((x) & BIT_MASK_BSSID4_H_V1) << BIT_SHIFT_BSSID4_H_V1)
+#define BITS_BSSID4_H_V1 (BIT_MASK_BSSID4_H_V1 << BIT_SHIFT_BSSID4_H_V1)
+#define BIT_CLEAR_BSSID4_H_V1(x) ((x) & (~BITS_BSSID4_H_V1))
+#define BIT_GET_BSSID4_H_V1(x)                                                 \
+	(((x) >> BIT_SHIFT_BSSID4_H_V1) & BIT_MASK_BSSID4_H_V1)
+#define BIT_SET_BSSID4_H_V1(x, v)                                              \
+	(BIT_CLEAR_BSSID4_H_V1(x) | BIT_BSSID4_H_V1(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_NOA_REPORT				(Offset 0x1650) */
+
+#define BIT_SHIFT_NOA_RPT 0
+#define BIT_MASK_NOA_RPT 0xffffffffL
+#define BIT_NOA_RPT(x) (((x) & BIT_MASK_NOA_RPT) << BIT_SHIFT_NOA_RPT)
+#define BITS_NOA_RPT (BIT_MASK_NOA_RPT << BIT_SHIFT_NOA_RPT)
+#define BIT_CLEAR_NOA_RPT(x) ((x) & (~BITS_NOA_RPT))
+#define BIT_GET_NOA_RPT(x) (((x) >> BIT_SHIFT_NOA_RPT) & BIT_MASK_NOA_RPT)
+#define BIT_SET_NOA_RPT(x, v) (BIT_CLEAR_NOA_RPT(x) | BIT_NOA_RPT(v))
+
+/* 2 REG_NOA_REPORT_1			(Offset 0x1654) */
+
+#define BIT_SHIFT_NOA_RPT_1 0
+#define BIT_MASK_NOA_RPT_1 0xffffffffL
+#define BIT_NOA_RPT_1(x) (((x) & BIT_MASK_NOA_RPT_1) << BIT_SHIFT_NOA_RPT_1)
+#define BITS_NOA_RPT_1 (BIT_MASK_NOA_RPT_1 << BIT_SHIFT_NOA_RPT_1)
+#define BIT_CLEAR_NOA_RPT_1(x) ((x) & (~BITS_NOA_RPT_1))
+#define BIT_GET_NOA_RPT_1(x) (((x) >> BIT_SHIFT_NOA_RPT_1) & BIT_MASK_NOA_RPT_1)
+#define BIT_SET_NOA_RPT_1(x, v) (BIT_CLEAR_NOA_RPT_1(x) | BIT_NOA_RPT_1(v))
+
+/* 2 REG_NOA_REPORT_2			(Offset 0x1658) */
+
+#define BIT_SHIFT_NOA_RPT_2 0
+#define BIT_MASK_NOA_RPT_2 0xffffffffL
+#define BIT_NOA_RPT_2(x) (((x) & BIT_MASK_NOA_RPT_2) << BIT_SHIFT_NOA_RPT_2)
+#define BITS_NOA_RPT_2 (BIT_MASK_NOA_RPT_2 << BIT_SHIFT_NOA_RPT_2)
+#define BIT_CLEAR_NOA_RPT_2(x) ((x) & (~BITS_NOA_RPT_2))
+#define BIT_GET_NOA_RPT_2(x) (((x) >> BIT_SHIFT_NOA_RPT_2) & BIT_MASK_NOA_RPT_2)
+#define BIT_SET_NOA_RPT_2(x, v) (BIT_CLEAR_NOA_RPT_2(x) | BIT_NOA_RPT_2(v))
+
+/* 2 REG_NOA_REPORT_3			(Offset 0x165C) */
+
+#define BIT_SHIFT_NOA_RPT_3 0
+#define BIT_MASK_NOA_RPT_3 0xff
+#define BIT_NOA_RPT_3(x) (((x) & BIT_MASK_NOA_RPT_3) << BIT_SHIFT_NOA_RPT_3)
+#define BITS_NOA_RPT_3 (BIT_MASK_NOA_RPT_3 << BIT_SHIFT_NOA_RPT_3)
+#define BIT_CLEAR_NOA_RPT_3(x) ((x) & (~BITS_NOA_RPT_3))
+#define BIT_GET_NOA_RPT_3(x) (((x) >> BIT_SHIFT_NOA_RPT_3) & BIT_MASK_NOA_RPT_3)
+#define BIT_SET_NOA_RPT_3(x, v) (BIT_CLEAR_NOA_RPT_3(x) | BIT_NOA_RPT_3(v))
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_PWRBIT_SETTING			(Offset 0x1660) */
+
+#define BIT_CLI3_WMAC_TCRPWRMGT_HWCTL_EN BIT(15)
+#define BIT_CLI3_WMAC_TCRPWRMGT_HWDATA_EN BIT(14)
+#define BIT_CLI3_WMAC_TCRPWRMGT_HWACT_EN BIT(13)
+#define BIT_CLI3_PWR_ST_V1 BIT(12)
+#define BIT_CLI2_WMAC_TCRPWRMGT_HWCTL_EN BIT(11)
+#define BIT_CLI2_WMAC_TCRPWRMGT_HWDATA_EN BIT(10)
+#define BIT_CLI2_WMAC_TCRPWRMGT_HWACT_EN BIT(9)
+#define BIT_CLI2_PWR_ST_V1 BIT(8)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT)
+
+/* 2 REG_PWRBIT_SETTING			(Offset 0x1660) */
+
+#define BIT_CLI3_PWRBIT_OW_EN BIT(7)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_PWRBIT_SETTING			(Offset 0x1660) */
+
+#define BIT_CLI1_WMAC_TCRPWRMGT_HWCTL_EN BIT(7)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT)
+
+/* 2 REG_PWRBIT_SETTING			(Offset 0x1660) */
+
+#define BIT_CLI3_PWR_ST BIT(6)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_PWRBIT_SETTING			(Offset 0x1660) */
+
+#define BIT_CLI1_WMAC_TCRPWRMGT_HWDATA_EN BIT(6)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT)
+
+/* 2 REG_PWRBIT_SETTING			(Offset 0x1660) */
+
+#define BIT_CLI2_PWRBIT_OW_EN BIT(5)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_PWRBIT_SETTING			(Offset 0x1660) */
+
+#define BIT_CLI1_WMAC_TCRPWRMGT_HWACT_EN BIT(5)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT)
+
+/* 2 REG_PWRBIT_SETTING			(Offset 0x1660) */
+
+#define BIT_CLI2_PWR_ST BIT(4)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_PWRBIT_SETTING			(Offset 0x1660) */
+
+#define BIT_CLI1_PWR_ST_V1 BIT(4)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT)
+
+/* 2 REG_PWRBIT_SETTING			(Offset 0x1660) */
+
+#define BIT_CLI1_PWRBIT_OW_EN BIT(3)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_PWRBIT_SETTING			(Offset 0x1660) */
+
+#define BIT_CLI0_WMAC_TCRPWRMGT_HWCTL_EN BIT(3)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT)
+
+/* 2 REG_PWRBIT_SETTING			(Offset 0x1660) */
+
+#define BIT_CLI1_PWR_ST BIT(2)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_PWRBIT_SETTING			(Offset 0x1660) */
+
+#define BIT_CLI0_WMAC_TCRPWRMGT_HWDATA_EN BIT(2)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT)
+
+/* 2 REG_PWRBIT_SETTING			(Offset 0x1660) */
+
+#define BIT_CLI0_PWRBIT_OW_EN BIT(1)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_PWRBIT_SETTING			(Offset 0x1660) */
+
+#define BIT_CLI0_WMAC_TCRPWRMGT_HWACT_EN BIT(1)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT)
+
+/* 2 REG_PWRBIT_SETTING			(Offset 0x1660) */
+
+#define BIT_CLI0_PWR_ST BIT(0)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_PWRBIT_SETTING			(Offset 0x1660) */
+
+#define BIT_CLI0_PWR_ST_V1 BIT(0)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_GENERAL_OPTION			(Offset 0x1664) */
+
+#define BIT_FIX_MSDU_TAIL_WR BIT(12)
+#define BIT_FIX_MSDU_SHIFT BIT(11)
+
+#endif
+
+#if (HALMAC_8822C_SUPPORT)
+
+/* 2 REG_GENERAL_OPTION			(Offset 0x1664) */
+
+#define BIT_WMAC_RXRST_NDP_TIMEOUT BIT(11)
+#define BIT_WMAC_NDP_STANDBY_WAIT_RXEND BIT(10)
+#define BIT_DUMMY_FCS_READY_MASK_EN BIT(9)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_GENERAL_OPTION			(Offset 0x1664) */
+
+#define BIT_RXFIFO_GNT_CUT BIT(8)
+
+#endif
+
+#if (HALMAC_8822C_SUPPORT)
+
+/* 2 REG_GENERAL_OPTION			(Offset 0x1664) */
+
+#define BIT_DUMMY_RXD_FCS_ERROR_MASK_EN_V1 BIT(7)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_GENERAL_OPTION			(Offset 0x1664) */
+
+#define BIT_WMAC_EXT_DBG_SEL_V1 BIT(6)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_GENERAL_OPTION			(Offset 0x1664) */
+
+#define BIT_WMAC_FIX_FIRST_MPDU_WITH_PHYSTS BIT(5)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_GENERAL_OPTION			(Offset 0x1664) */
+
+#define BIT_RX_DMA_BYPASS_CHECK_DATABYPASS_CHECK_DATA BIT(4)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_GENERAL_OPTION			(Offset 0x1664) */
+
+#define BIT_DUMMY_RXD_FCS_ERROR_MASK_EN BIT(4)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_GENERAL_OPTION			(Offset 0x1664) */
+
+#define BIT_RX_DMA_BYPASS_CHECK_MGTBIT_RX_DMA_BYPASS_CHECK_MGT BIT(3)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_GENERAL_OPTION			(Offset 0x1664) */
+
+#define BIT_PATTERN_MATCH_FIX_EN BIT(3)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_GENERAL_OPTION			(Offset 0x1664) */
+
+#define BIT_TXSERV_FIELD_SEL BIT(2)
+#define BIT_RXVHT_LEN_SEL BIT(1)
+#define BIT_RXMIC_PROTECT_EN BIT(0)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_FWPHYFF_RCR				(Offset 0x1668) */
+
+#define BIT_RCR2_AAMSDU BIT(25)
+#define BIT_RCR2_CBSSID_BCN BIT(24)
+#define BIT_RCR2_ACRC32 BIT(23)
+#define BIT_RCR2_TA_BCN BIT(22)
+#define BIT_RCR2_CBSSID_DATA BIT(21)
+#define BIT_RCR2_ADD3 BIT(20)
+#define BIT_RCR2_AB BIT(19)
+#define BIT_RCR2_AM BIT(18)
+#define BIT_RCR2_APM BIT(17)
+#define BIT_RCR2_AAP BIT(16)
+#define BIT_RCR1_AAMSDU BIT(9)
+#define BIT_RCR1_CBSSID_BCN BIT(8)
+#define BIT_RCR1_ACRC32 BIT(7)
+#define BIT_RCR1_TA_BCN BIT(6)
+#define BIT_RCR1_CBSSID_DATA BIT(5)
+#define BIT_RCR1_ADD3 BIT(4)
+#define BIT_RCR1_AB BIT(3)
+#define BIT_RCR1_AM BIT(2)
+#define BIT_RCR1_APM BIT(1)
+#define BIT_RCR1_AAP BIT(0)
+
+/* 2 REG_ADDRCAM_WRITE_CONTENT		(Offset 0x166C) */
+
+#define BIT_SHIFT_ADDRCAM_WDATA 0
+#define BIT_MASK_ADDRCAM_WDATA 0xffffffffL
+#define BIT_ADDRCAM_WDATA(x)                                                   \
+	(((x) & BIT_MASK_ADDRCAM_WDATA) << BIT_SHIFT_ADDRCAM_WDATA)
+#define BITS_ADDRCAM_WDATA (BIT_MASK_ADDRCAM_WDATA << BIT_SHIFT_ADDRCAM_WDATA)
+#define BIT_CLEAR_ADDRCAM_WDATA(x) ((x) & (~BITS_ADDRCAM_WDATA))
+#define BIT_GET_ADDRCAM_WDATA(x)                                               \
+	(((x) >> BIT_SHIFT_ADDRCAM_WDATA) & BIT_MASK_ADDRCAM_WDATA)
+#define BIT_SET_ADDRCAM_WDATA(x, v)                                            \
+	(BIT_CLEAR_ADDRCAM_WDATA(x) | BIT_ADDRCAM_WDATA(v))
+
+/* 2 REG_ADDRCAM_READ_CONTENT		(Offset 0x1670) */
+
+#define BIT_SHIFT_ADDRCAM_RDATA 0
+#define BIT_MASK_ADDRCAM_RDATA 0xffffffffL
+#define BIT_ADDRCAM_RDATA(x)                                                   \
+	(((x) & BIT_MASK_ADDRCAM_RDATA) << BIT_SHIFT_ADDRCAM_RDATA)
+#define BITS_ADDRCAM_RDATA (BIT_MASK_ADDRCAM_RDATA << BIT_SHIFT_ADDRCAM_RDATA)
+#define BIT_CLEAR_ADDRCAM_RDATA(x) ((x) & (~BITS_ADDRCAM_RDATA))
+#define BIT_GET_ADDRCAM_RDATA(x)                                               \
+	(((x) >> BIT_SHIFT_ADDRCAM_RDATA) & BIT_MASK_ADDRCAM_RDATA)
+#define BIT_SET_ADDRCAM_RDATA(x, v)                                            \
+	(BIT_CLEAR_ADDRCAM_RDATA(x) | BIT_ADDRCAM_RDATA(v))
+
+/* 2 REG_ADDRCAM_CFG				(Offset 0x1674) */
+
+#define BIT_ADDRCAM_POLL BIT(31)
+#define BIT__ADDRCAM_WT_EN BIT(30)
+#define BIT_CLRADDRCAM BIT(29)
+
+#define BIT_SHIFT__ADDRCAM_ADDR 8
+#define BIT_MASK__ADDRCAM_ADDR 0x3ff
+#define BIT__ADDRCAM_ADDR(x)                                                   \
+	(((x) & BIT_MASK__ADDRCAM_ADDR) << BIT_SHIFT__ADDRCAM_ADDR)
+#define BITS__ADDRCAM_ADDR (BIT_MASK__ADDRCAM_ADDR << BIT_SHIFT__ADDRCAM_ADDR)
+#define BIT_CLEAR__ADDRCAM_ADDR(x) ((x) & (~BITS__ADDRCAM_ADDR))
+#define BIT_GET__ADDRCAM_ADDR(x)                                               \
+	(((x) >> BIT_SHIFT__ADDRCAM_ADDR) & BIT_MASK__ADDRCAM_ADDR)
+#define BIT_SET__ADDRCAM_ADDR(x, v)                                            \
+	(BIT_CLEAR__ADDRCAM_ADDR(x) | BIT__ADDRCAM_ADDR(v))
+
+#define BIT_SHIFT_ADDRCAM_RANGE 0
+#define BIT_MASK_ADDRCAM_RANGE 0x7f
+#define BIT_ADDRCAM_RANGE(x)                                                   \
+	(((x) & BIT_MASK_ADDRCAM_RANGE) << BIT_SHIFT_ADDRCAM_RANGE)
+#define BITS_ADDRCAM_RANGE (BIT_MASK_ADDRCAM_RANGE << BIT_SHIFT_ADDRCAM_RANGE)
+#define BIT_CLEAR_ADDRCAM_RANGE(x) ((x) & (~BITS_ADDRCAM_RANGE))
+#define BIT_GET_ADDRCAM_RANGE(x)                                               \
+	(((x) >> BIT_SHIFT_ADDRCAM_RANGE) & BIT_MASK_ADDRCAM_RANGE)
+#define BIT_SET_ADDRCAM_RANGE(x, v)                                            \
+	(BIT_CLEAR_ADDRCAM_RANGE(x) | BIT_ADDRCAM_RANGE(v))
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_CSI_RRSR				(Offset 0x1678) */
+
+#define BIT_CSI_LDPC_EN BIT(29)
+#define BIT_CSI_STBC_EN BIT(28)
+
+#define BIT_SHIFT_CSI_RRSC_BITMAP 4
+#define BIT_MASK_CSI_RRSC_BITMAP 0xffffff
+#define BIT_CSI_RRSC_BITMAP(x)                                                 \
+	(((x) & BIT_MASK_CSI_RRSC_BITMAP) << BIT_SHIFT_CSI_RRSC_BITMAP)
+#define BITS_CSI_RRSC_BITMAP                                                   \
+	(BIT_MASK_CSI_RRSC_BITMAP << BIT_SHIFT_CSI_RRSC_BITMAP)
+#define BIT_CLEAR_CSI_RRSC_BITMAP(x) ((x) & (~BITS_CSI_RRSC_BITMAP))
+#define BIT_GET_CSI_RRSC_BITMAP(x)                                             \
+	(((x) >> BIT_SHIFT_CSI_RRSC_BITMAP) & BIT_MASK_CSI_RRSC_BITMAP)
+#define BIT_SET_CSI_RRSC_BITMAP(x, v)                                          \
+	(BIT_CLEAR_CSI_RRSC_BITMAP(x) | BIT_CSI_RRSC_BITMAP(v))
+
+#define BIT_SHIFT_OFDM_LEN_TH 0
+#define BIT_MASK_OFDM_LEN_TH 0xf
+#define BIT_OFDM_LEN_TH(x)                                                     \
+	(((x) & BIT_MASK_OFDM_LEN_TH) << BIT_SHIFT_OFDM_LEN_TH)
+#define BITS_OFDM_LEN_TH (BIT_MASK_OFDM_LEN_TH << BIT_SHIFT_OFDM_LEN_TH)
+#define BIT_CLEAR_OFDM_LEN_TH(x) ((x) & (~BITS_OFDM_LEN_TH))
+#define BIT_GET_OFDM_LEN_TH(x)                                                 \
+	(((x) >> BIT_SHIFT_OFDM_LEN_TH) & BIT_MASK_OFDM_LEN_TH)
+#define BIT_SET_OFDM_LEN_TH(x, v)                                              \
+	(BIT_CLEAR_OFDM_LEN_TH(x) | BIT_OFDM_LEN_TH(v))
+
+#define BIT_SHIFT_WMAC_MULBK_PAGE_SIZE 0
+#define BIT_MASK_WMAC_MULBK_PAGE_SIZE 0xff
+#define BIT_WMAC_MULBK_PAGE_SIZE(x)                                            \
+	(((x) & BIT_MASK_WMAC_MULBK_PAGE_SIZE)                                 \
+	 << BIT_SHIFT_WMAC_MULBK_PAGE_SIZE)
+#define BITS_WMAC_MULBK_PAGE_SIZE                                              \
+	(BIT_MASK_WMAC_MULBK_PAGE_SIZE << BIT_SHIFT_WMAC_MULBK_PAGE_SIZE)
+#define BIT_CLEAR_WMAC_MULBK_PAGE_SIZE(x) ((x) & (~BITS_WMAC_MULBK_PAGE_SIZE))
+#define BIT_GET_WMAC_MULBK_PAGE_SIZE(x)                                        \
+	(((x) >> BIT_SHIFT_WMAC_MULBK_PAGE_SIZE) &                             \
+	 BIT_MASK_WMAC_MULBK_PAGE_SIZE)
+#define BIT_SET_WMAC_MULBK_PAGE_SIZE(x, v)                                     \
+	(BIT_CLEAR_WMAC_MULBK_PAGE_SIZE(x) | BIT_WMAC_MULBK_PAGE_SIZE(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822B_SUPPORT)
+
+/* 2 REG_WMAC_MU_BF_OPTION			(Offset 0x167C) */
+
+#define BIT_BIT_WMAC_TXMU_ACKPOLICY_EN BIT(6)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_MU_BF_OPTION			(Offset 0x167C) */
+
+#define BIT_WMAC_TXMU_ACKPOLICY_EN BIT(6)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_WMAC_PAUSE_BB_CLR_TH		(Offset 0x167D) */
+
+#define BIT_SHIFT_WMAC_PAUSE_BB_CLR_TH 0
+#define BIT_MASK_WMAC_PAUSE_BB_CLR_TH 0xff
+#define BIT_WMAC_PAUSE_BB_CLR_TH(x)                                            \
+	(((x) & BIT_MASK_WMAC_PAUSE_BB_CLR_TH)                                 \
+	 << BIT_SHIFT_WMAC_PAUSE_BB_CLR_TH)
+#define BITS_WMAC_PAUSE_BB_CLR_TH                                              \
+	(BIT_MASK_WMAC_PAUSE_BB_CLR_TH << BIT_SHIFT_WMAC_PAUSE_BB_CLR_TH)
+#define BIT_CLEAR_WMAC_PAUSE_BB_CLR_TH(x) ((x) & (~BITS_WMAC_PAUSE_BB_CLR_TH))
+#define BIT_GET_WMAC_PAUSE_BB_CLR_TH(x)                                        \
+	(((x) >> BIT_SHIFT_WMAC_PAUSE_BB_CLR_TH) &                             \
+	 BIT_MASK_WMAC_PAUSE_BB_CLR_TH)
+#define BIT_SET_WMAC_PAUSE_BB_CLR_TH(x, v)                                     \
+	(BIT_CLEAR_WMAC_PAUSE_BB_CLR_TH(x) | BIT_WMAC_PAUSE_BB_CLR_TH(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+
+/* 2 REG_WMAC_MU_ARB				(Offset 0x167E) */
+
+#define BIT_WMAC_ARB_HW_ADAPT_EN BIT(7)
+#define BIT_WMAC_ARB_SW_EN BIT(6)
+
+#define BIT_SHIFT_WMAC_ARB_SW_STATE 0
+#define BIT_MASK_WMAC_ARB_SW_STATE 0x3f
+#define BIT_WMAC_ARB_SW_STATE(x)                                               \
+	(((x) & BIT_MASK_WMAC_ARB_SW_STATE) << BIT_SHIFT_WMAC_ARB_SW_STATE)
+#define BITS_WMAC_ARB_SW_STATE                                                 \
+	(BIT_MASK_WMAC_ARB_SW_STATE << BIT_SHIFT_WMAC_ARB_SW_STATE)
+#define BIT_CLEAR_WMAC_ARB_SW_STATE(x) ((x) & (~BITS_WMAC_ARB_SW_STATE))
+#define BIT_GET_WMAC_ARB_SW_STATE(x)                                           \
+	(((x) >> BIT_SHIFT_WMAC_ARB_SW_STATE) & BIT_MASK_WMAC_ARB_SW_STATE)
+#define BIT_SET_WMAC_ARB_SW_STATE(x, v)                                        \
+	(BIT_CLEAR_WMAC_ARB_SW_STATE(x) | BIT_WMAC_ARB_SW_STATE(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_WMAC_MU_OPTION			(Offset 0x167F) */
+
+#define BIT_NOCHK_BFPOLL_BMP BIT(7)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT)
+
+/* 2 REG_WMAC_MU_OPTION			(Offset 0x167F) */
+
+#define BIT_SHIFT_WMAC_MU_DBGSEL 5
+#define BIT_MASK_WMAC_MU_DBGSEL 0x3
+#define BIT_WMAC_MU_DBGSEL(x)                                                  \
+	(((x) & BIT_MASK_WMAC_MU_DBGSEL) << BIT_SHIFT_WMAC_MU_DBGSEL)
+#define BITS_WMAC_MU_DBGSEL                                                    \
+	(BIT_MASK_WMAC_MU_DBGSEL << BIT_SHIFT_WMAC_MU_DBGSEL)
+#define BIT_CLEAR_WMAC_MU_DBGSEL(x) ((x) & (~BITS_WMAC_MU_DBGSEL))
+#define BIT_GET_WMAC_MU_DBGSEL(x)                                              \
+	(((x) >> BIT_SHIFT_WMAC_MU_DBGSEL) & BIT_MASK_WMAC_MU_DBGSEL)
+#define BIT_SET_WMAC_MU_DBGSEL(x, v)                                           \
+	(BIT_CLEAR_WMAC_MU_DBGSEL(x) | BIT_WMAC_MU_DBGSEL(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+
+/* 2 REG_WMAC_MU_OPTION			(Offset 0x167F) */
+
+#define BIT_SHIFT_WMAC_MU_CPRD_TIMEOUT 0
+#define BIT_MASK_WMAC_MU_CPRD_TIMEOUT 0x1f
+#define BIT_WMAC_MU_CPRD_TIMEOUT(x)                                            \
+	(((x) & BIT_MASK_WMAC_MU_CPRD_TIMEOUT)                                 \
+	 << BIT_SHIFT_WMAC_MU_CPRD_TIMEOUT)
+#define BITS_WMAC_MU_CPRD_TIMEOUT                                              \
+	(BIT_MASK_WMAC_MU_CPRD_TIMEOUT << BIT_SHIFT_WMAC_MU_CPRD_TIMEOUT)
+#define BIT_CLEAR_WMAC_MU_CPRD_TIMEOUT(x) ((x) & (~BITS_WMAC_MU_CPRD_TIMEOUT))
+#define BIT_GET_WMAC_MU_CPRD_TIMEOUT(x)                                        \
+	(((x) >> BIT_SHIFT_WMAC_MU_CPRD_TIMEOUT) &                             \
+	 BIT_MASK_WMAC_MU_CPRD_TIMEOUT)
+#define BIT_SET_WMAC_MU_CPRD_TIMEOUT(x, v)                                     \
+	(BIT_CLEAR_WMAC_MU_CPRD_TIMEOUT(x) | BIT_WMAC_MU_CPRD_TIMEOUT(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_WMAC_MU_BF_CTL			(Offset 0x1680) */
+
+#define BIT_WMAC_INVLD_BFPRT_CHK BIT(15)
+#define BIT_WMAC_RETXBFRPTSEQ_UPD BIT(14)
+
+#define BIT_SHIFT_WMAC_MU_BFRPTSEG_SEL 12
+#define BIT_MASK_WMAC_MU_BFRPTSEG_SEL 0x3
+#define BIT_WMAC_MU_BFRPTSEG_SEL(x)                                            \
+	(((x) & BIT_MASK_WMAC_MU_BFRPTSEG_SEL)                                 \
+	 << BIT_SHIFT_WMAC_MU_BFRPTSEG_SEL)
+#define BITS_WMAC_MU_BFRPTSEG_SEL                                              \
+	(BIT_MASK_WMAC_MU_BFRPTSEG_SEL << BIT_SHIFT_WMAC_MU_BFRPTSEG_SEL)
+#define BIT_CLEAR_WMAC_MU_BFRPTSEG_SEL(x) ((x) & (~BITS_WMAC_MU_BFRPTSEG_SEL))
+#define BIT_GET_WMAC_MU_BFRPTSEG_SEL(x)                                        \
+	(((x) >> BIT_SHIFT_WMAC_MU_BFRPTSEG_SEL) &                             \
+	 BIT_MASK_WMAC_MU_BFRPTSEG_SEL)
+#define BIT_SET_WMAC_MU_BFRPTSEG_SEL(x, v)                                     \
+	(BIT_CLEAR_WMAC_MU_BFRPTSEG_SEL(x) | BIT_WMAC_MU_BFRPTSEG_SEL(v))
+
+#define BIT_SHIFT_WMAC_MU_BF_MYAID 0
+#define BIT_MASK_WMAC_MU_BF_MYAID 0xfff
+#define BIT_WMAC_MU_BF_MYAID(x)                                                \
+	(((x) & BIT_MASK_WMAC_MU_BF_MYAID) << BIT_SHIFT_WMAC_MU_BF_MYAID)
+#define BITS_WMAC_MU_BF_MYAID                                                  \
+	(BIT_MASK_WMAC_MU_BF_MYAID << BIT_SHIFT_WMAC_MU_BF_MYAID)
+#define BIT_CLEAR_WMAC_MU_BF_MYAID(x) ((x) & (~BITS_WMAC_MU_BF_MYAID))
+#define BIT_GET_WMAC_MU_BF_MYAID(x)                                            \
+	(((x) >> BIT_SHIFT_WMAC_MU_BF_MYAID) & BIT_MASK_WMAC_MU_BF_MYAID)
+#define BIT_SET_WMAC_MU_BF_MYAID(x, v)                                         \
+	(BIT_CLEAR_WMAC_MU_BF_MYAID(x) | BIT_WMAC_MU_BF_MYAID(v))
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_WMAC_MU_BFRPT_PARA			(Offset 0x1682) */
+
+#define BIT_SHIFT_BFRPT_PARA_USERID_SEL_V1 13
+#define BIT_MASK_BFRPT_PARA_USERID_SEL_V1 0x7
+#define BIT_BFRPT_PARA_USERID_SEL_V1(x)                                        \
+	(((x) & BIT_MASK_BFRPT_PARA_USERID_SEL_V1)                             \
+	 << BIT_SHIFT_BFRPT_PARA_USERID_SEL_V1)
+#define BITS_BFRPT_PARA_USERID_SEL_V1                                          \
+	(BIT_MASK_BFRPT_PARA_USERID_SEL_V1                                     \
+	 << BIT_SHIFT_BFRPT_PARA_USERID_SEL_V1)
+#define BIT_CLEAR_BFRPT_PARA_USERID_SEL_V1(x)                                  \
+	((x) & (~BITS_BFRPT_PARA_USERID_SEL_V1))
+#define BIT_GET_BFRPT_PARA_USERID_SEL_V1(x)                                    \
+	(((x) >> BIT_SHIFT_BFRPT_PARA_USERID_SEL_V1) &                         \
+	 BIT_MASK_BFRPT_PARA_USERID_SEL_V1)
+#define BIT_SET_BFRPT_PARA_USERID_SEL_V1(x, v)                                 \
+	(BIT_CLEAR_BFRPT_PARA_USERID_SEL_V1(x) |                               \
+	 BIT_BFRPT_PARA_USERID_SEL_V1(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT)
+
+/* 2 REG_WMAC_MU_BFRPT_PARA			(Offset 0x1682) */
+
+#define BIT_SHIFT_BFRPT_PARA_USERID_SEL 12
+#define BIT_MASK_BFRPT_PARA_USERID_SEL 0x7
+#define BIT_BFRPT_PARA_USERID_SEL(x)                                           \
+	(((x) & BIT_MASK_BFRPT_PARA_USERID_SEL)                                \
+	 << BIT_SHIFT_BFRPT_PARA_USERID_SEL)
+#define BITS_BFRPT_PARA_USERID_SEL                                             \
+	(BIT_MASK_BFRPT_PARA_USERID_SEL << BIT_SHIFT_BFRPT_PARA_USERID_SEL)
+#define BIT_CLEAR_BFRPT_PARA_USERID_SEL(x) ((x) & (~BITS_BFRPT_PARA_USERID_SEL))
+#define BIT_GET_BFRPT_PARA_USERID_SEL(x)                                       \
+	(((x) >> BIT_SHIFT_BFRPT_PARA_USERID_SEL) &                            \
+	 BIT_MASK_BFRPT_PARA_USERID_SEL)
+#define BIT_SET_BFRPT_PARA_USERID_SEL(x, v)                                    \
+	(BIT_CLEAR_BFRPT_PARA_USERID_SEL(x) | BIT_BFRPT_PARA_USERID_SEL(v))
+
+#endif
+
+#if (HALMAC_8822B_SUPPORT)
+
+/* 2 REG_WMAC_MU_BFRPT_PARA			(Offset 0x1682) */
+
+#define BIT_SHIFT_BIT_BFRPT_PARA_USERID_SEL 12
+#define BIT_MASK_BIT_BFRPT_PARA_USERID_SEL 0x7
+#define BIT_BIT_BFRPT_PARA_USERID_SEL(x)                                       \
+	(((x) & BIT_MASK_BIT_BFRPT_PARA_USERID_SEL)                            \
+	 << BIT_SHIFT_BIT_BFRPT_PARA_USERID_SEL)
+#define BITS_BIT_BFRPT_PARA_USERID_SEL                                         \
+	(BIT_MASK_BIT_BFRPT_PARA_USERID_SEL                                    \
+	 << BIT_SHIFT_BIT_BFRPT_PARA_USERID_SEL)
+#define BIT_CLEAR_BIT_BFRPT_PARA_USERID_SEL(x)                                 \
+	((x) & (~BITS_BIT_BFRPT_PARA_USERID_SEL))
+#define BIT_GET_BIT_BFRPT_PARA_USERID_SEL(x)                                   \
+	(((x) >> BIT_SHIFT_BIT_BFRPT_PARA_USERID_SEL) &                        \
+	 BIT_MASK_BIT_BFRPT_PARA_USERID_SEL)
+#define BIT_SET_BIT_BFRPT_PARA_USERID_SEL(x, v)                                \
+	(BIT_CLEAR_BIT_BFRPT_PARA_USERID_SEL(x) |                              \
+	 BIT_BIT_BFRPT_PARA_USERID_SEL(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+
+/* 2 REG_WMAC_MU_BFRPT_PARA			(Offset 0x1682) */
+
+#define BIT_SHIFT_BFRPT_PARA 0
+#define BIT_MASK_BFRPT_PARA 0xfff
+#define BIT_BFRPT_PARA(x) (((x) & BIT_MASK_BFRPT_PARA) << BIT_SHIFT_BFRPT_PARA)
+#define BITS_BFRPT_PARA (BIT_MASK_BFRPT_PARA << BIT_SHIFT_BFRPT_PARA)
+#define BIT_CLEAR_BFRPT_PARA(x) ((x) & (~BITS_BFRPT_PARA))
+#define BIT_GET_BFRPT_PARA(x)                                                  \
+	(((x) >> BIT_SHIFT_BFRPT_PARA) & BIT_MASK_BFRPT_PARA)
+#define BIT_SET_BFRPT_PARA(x, v) (BIT_CLEAR_BFRPT_PARA(x) | BIT_BFRPT_PARA(v))
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_WMAC_MU_BFRPT_PARA			(Offset 0x1682) */
+
+#define BIT_SHIFT_BFRPT_PARA_V1 0
+#define BIT_MASK_BFRPT_PARA_V1 0x1fff
+#define BIT_BFRPT_PARA_V1(x)                                                   \
+	(((x) & BIT_MASK_BFRPT_PARA_V1) << BIT_SHIFT_BFRPT_PARA_V1)
+#define BITS_BFRPT_PARA_V1 (BIT_MASK_BFRPT_PARA_V1 << BIT_SHIFT_BFRPT_PARA_V1)
+#define BIT_CLEAR_BFRPT_PARA_V1(x) ((x) & (~BITS_BFRPT_PARA_V1))
+#define BIT_GET_BFRPT_PARA_V1(x)                                               \
+	(((x) >> BIT_SHIFT_BFRPT_PARA_V1) & BIT_MASK_BFRPT_PARA_V1)
+#define BIT_SET_BFRPT_PARA_V1(x, v)                                            \
+	(BIT_CLEAR_BFRPT_PARA_V1(x) | BIT_BFRPT_PARA_V1(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_WMAC_ASSOCIATED_MU_BFMEE2		(Offset 0x1684) */
+
+#define BIT_STATUS_BFEE2 BIT(10)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_WMAC_ASSOCIATED_MU_BFMEE2		(Offset 0x1684) */
+
+#define BIT_WMAC_MU_BFEE2_EN BIT(9)
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+/* 2 REG_WMAC_ASSOCIATED_MU_BFMEE2		(Offset 0x1684) */
+
+#define BIT_WMAC_MU_BFEE2_USER_EN BIT(9)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_WMAC_ASSOCIATED_MU_BFMEE2		(Offset 0x1684) */
+
+#define BIT_SHIFT_WMAC_MU_BFEE2_AID 0
+#define BIT_MASK_WMAC_MU_BFEE2_AID 0x1ff
+#define BIT_WMAC_MU_BFEE2_AID(x)                                               \
+	(((x) & BIT_MASK_WMAC_MU_BFEE2_AID) << BIT_SHIFT_WMAC_MU_BFEE2_AID)
+#define BITS_WMAC_MU_BFEE2_AID                                                 \
+	(BIT_MASK_WMAC_MU_BFEE2_AID << BIT_SHIFT_WMAC_MU_BFEE2_AID)
+#define BIT_CLEAR_WMAC_MU_BFEE2_AID(x) ((x) & (~BITS_WMAC_MU_BFEE2_AID))
+#define BIT_GET_WMAC_MU_BFEE2_AID(x)                                           \
+	(((x) >> BIT_SHIFT_WMAC_MU_BFEE2_AID) & BIT_MASK_WMAC_MU_BFEE2_AID)
+#define BIT_SET_WMAC_MU_BFEE2_AID(x, v)                                        \
+	(BIT_CLEAR_WMAC_MU_BFEE2_AID(x) | BIT_WMAC_MU_BFEE2_AID(v))
+
+/* 2 REG_WMAC_ASSOCIATED_MU_BFMEE3		(Offset 0x1686) */
+
+#define BIT_STATUS_BFEE3 BIT(10)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_WMAC_ASSOCIATED_MU_BFMEE3		(Offset 0x1686) */
+
+#define BIT_WMAC_MU_BFEE3_EN BIT(9)
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+/* 2 REG_WMAC_ASSOCIATED_MU_BFMEE3		(Offset 0x1686) */
+
+#define BIT_WMAC_MU_BFEE3_USER_EN BIT(9)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_WMAC_ASSOCIATED_MU_BFMEE3		(Offset 0x1686) */
+
+#define BIT_SHIFT_WMAC_MU_BFEE3_AID 0
+#define BIT_MASK_WMAC_MU_BFEE3_AID 0x1ff
+#define BIT_WMAC_MU_BFEE3_AID(x)                                               \
+	(((x) & BIT_MASK_WMAC_MU_BFEE3_AID) << BIT_SHIFT_WMAC_MU_BFEE3_AID)
+#define BITS_WMAC_MU_BFEE3_AID                                                 \
+	(BIT_MASK_WMAC_MU_BFEE3_AID << BIT_SHIFT_WMAC_MU_BFEE3_AID)
+#define BIT_CLEAR_WMAC_MU_BFEE3_AID(x) ((x) & (~BITS_WMAC_MU_BFEE3_AID))
+#define BIT_GET_WMAC_MU_BFEE3_AID(x)                                           \
+	(((x) >> BIT_SHIFT_WMAC_MU_BFEE3_AID) & BIT_MASK_WMAC_MU_BFEE3_AID)
+#define BIT_SET_WMAC_MU_BFEE3_AID(x, v)                                        \
+	(BIT_CLEAR_WMAC_MU_BFEE3_AID(x) | BIT_WMAC_MU_BFEE3_AID(v))
+
+/* 2 REG_WMAC_ASSOCIATED_MU_BFMEE4		(Offset 0x1688) */
+
+#define BIT_STATUS_BFEE4 BIT(10)
+#define BIT_WMAC_MU_BFEE4_EN BIT(9)
+
+#define BIT_SHIFT_WMAC_MU_BFEE4_AID 0
+#define BIT_MASK_WMAC_MU_BFEE4_AID 0x1ff
+#define BIT_WMAC_MU_BFEE4_AID(x)                                               \
+	(((x) & BIT_MASK_WMAC_MU_BFEE4_AID) << BIT_SHIFT_WMAC_MU_BFEE4_AID)
+#define BITS_WMAC_MU_BFEE4_AID                                                 \
+	(BIT_MASK_WMAC_MU_BFEE4_AID << BIT_SHIFT_WMAC_MU_BFEE4_AID)
+#define BIT_CLEAR_WMAC_MU_BFEE4_AID(x) ((x) & (~BITS_WMAC_MU_BFEE4_AID))
+#define BIT_GET_WMAC_MU_BFEE4_AID(x)                                           \
+	(((x) >> BIT_SHIFT_WMAC_MU_BFEE4_AID) & BIT_MASK_WMAC_MU_BFEE4_AID)
+#define BIT_SET_WMAC_MU_BFEE4_AID(x, v)                                        \
+	(BIT_CLEAR_WMAC_MU_BFEE4_AID(x) | BIT_WMAC_MU_BFEE4_AID(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822B_SUPPORT)
+
+/* 2 REG_WMAC_ASSOCIATED_MU_BFMEE5		(Offset 0x168A) */
+
+#define BIT_STATUS_BFEE5 BIT(10)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_WMAC_ASSOCIATED_MU_BFMEE5		(Offset 0x168A) */
+
+#define BIT_BIT_STATUS_BFEE5 BIT(10)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_WMAC_ASSOCIATED_MU_BFMEE5		(Offset 0x168A) */
+
+#define BIT_WMAC_MU_BFEE5_EN BIT(9)
+
+#define BIT_SHIFT_WMAC_MU_BFEE5_AID 0
+#define BIT_MASK_WMAC_MU_BFEE5_AID 0x1ff
+#define BIT_WMAC_MU_BFEE5_AID(x)                                               \
+	(((x) & BIT_MASK_WMAC_MU_BFEE5_AID) << BIT_SHIFT_WMAC_MU_BFEE5_AID)
+#define BITS_WMAC_MU_BFEE5_AID                                                 \
+	(BIT_MASK_WMAC_MU_BFEE5_AID << BIT_SHIFT_WMAC_MU_BFEE5_AID)
+#define BIT_CLEAR_WMAC_MU_BFEE5_AID(x) ((x) & (~BITS_WMAC_MU_BFEE5_AID))
+#define BIT_GET_WMAC_MU_BFEE5_AID(x)                                           \
+	(((x) >> BIT_SHIFT_WMAC_MU_BFEE5_AID) & BIT_MASK_WMAC_MU_BFEE5_AID)
+#define BIT_SET_WMAC_MU_BFEE5_AID(x, v)                                        \
+	(BIT_CLEAR_WMAC_MU_BFEE5_AID(x) | BIT_WMAC_MU_BFEE5_AID(v))
+
+/* 2 REG_WMAC_ASSOCIATED_MU_BFMEE6		(Offset 0x168C) */
+
+#define BIT_STATUS_BFEE6 BIT(10)
+#define BIT_WMAC_MU_BFEE6_EN BIT(9)
+
+#define BIT_SHIFT_WMAC_MU_BFEE6_AID 0
+#define BIT_MASK_WMAC_MU_BFEE6_AID 0x1ff
+#define BIT_WMAC_MU_BFEE6_AID(x)                                               \
+	(((x) & BIT_MASK_WMAC_MU_BFEE6_AID) << BIT_SHIFT_WMAC_MU_BFEE6_AID)
+#define BITS_WMAC_MU_BFEE6_AID                                                 \
+	(BIT_MASK_WMAC_MU_BFEE6_AID << BIT_SHIFT_WMAC_MU_BFEE6_AID)
+#define BIT_CLEAR_WMAC_MU_BFEE6_AID(x) ((x) & (~BITS_WMAC_MU_BFEE6_AID))
+#define BIT_GET_WMAC_MU_BFEE6_AID(x)                                           \
+	(((x) >> BIT_SHIFT_WMAC_MU_BFEE6_AID) & BIT_MASK_WMAC_MU_BFEE6_AID)
+#define BIT_SET_WMAC_MU_BFEE6_AID(x, v)                                        \
+	(BIT_CLEAR_WMAC_MU_BFEE6_AID(x) | BIT_WMAC_MU_BFEE6_AID(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_WMAC_ASSOCIATED_MU_BFMEE7		(Offset 0x168E) */
+
+#define BIT_BIT_STATUS_BFEE4 BIT(10)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_WMAC_ASSOCIATED_MU_BFMEE7		(Offset 0x168E) */
+
+#define BIT_STATUS_BFEE7 BIT(10)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_WMAC_ASSOCIATED_MU_BFMEE7		(Offset 0x168E) */
+
+#define BIT_WMAC_MU_BFEE7_EN BIT(9)
+
+#define BIT_SHIFT_WMAC_MU_BFEE7_AID 0
+#define BIT_MASK_WMAC_MU_BFEE7_AID 0x1ff
+#define BIT_WMAC_MU_BFEE7_AID(x)                                               \
+	(((x) & BIT_MASK_WMAC_MU_BFEE7_AID) << BIT_SHIFT_WMAC_MU_BFEE7_AID)
+#define BITS_WMAC_MU_BFEE7_AID                                                 \
+	(BIT_MASK_WMAC_MU_BFEE7_AID << BIT_SHIFT_WMAC_MU_BFEE7_AID)
+#define BIT_CLEAR_WMAC_MU_BFEE7_AID(x) ((x) & (~BITS_WMAC_MU_BFEE7_AID))
+#define BIT_GET_WMAC_MU_BFEE7_AID(x)                                           \
+	(((x) >> BIT_SHIFT_WMAC_MU_BFEE7_AID) & BIT_MASK_WMAC_MU_BFEE7_AID)
+#define BIT_SET_WMAC_MU_BFEE7_AID(x, v)                                        \
+	(BIT_CLEAR_WMAC_MU_BFEE7_AID(x) | BIT_WMAC_MU_BFEE7_AID(v))
+
+/* 2 REG_WMAC_BB_STOP_RX_COUNTER		(Offset 0x1690) */
+
+#define BIT_RST_ALL_COUNTER BIT(31)
+
+#define BIT_SHIFT_ABORT_RX_VBON_COUNTER 16
+#define BIT_MASK_ABORT_RX_VBON_COUNTER 0xff
+#define BIT_ABORT_RX_VBON_COUNTER(x)                                           \
+	(((x) & BIT_MASK_ABORT_RX_VBON_COUNTER)                                \
+	 << BIT_SHIFT_ABORT_RX_VBON_COUNTER)
+#define BITS_ABORT_RX_VBON_COUNTER                                             \
+	(BIT_MASK_ABORT_RX_VBON_COUNTER << BIT_SHIFT_ABORT_RX_VBON_COUNTER)
+#define BIT_CLEAR_ABORT_RX_VBON_COUNTER(x) ((x) & (~BITS_ABORT_RX_VBON_COUNTER))
+#define BIT_GET_ABORT_RX_VBON_COUNTER(x)                                       \
+	(((x) >> BIT_SHIFT_ABORT_RX_VBON_COUNTER) &                            \
+	 BIT_MASK_ABORT_RX_VBON_COUNTER)
+#define BIT_SET_ABORT_RX_VBON_COUNTER(x, v)                                    \
+	(BIT_CLEAR_ABORT_RX_VBON_COUNTER(x) | BIT_ABORT_RX_VBON_COUNTER(v))
+
+#define BIT_SHIFT_ABORT_RX_RDRDY_COUNTER 8
+#define BIT_MASK_ABORT_RX_RDRDY_COUNTER 0xff
+#define BIT_ABORT_RX_RDRDY_COUNTER(x)                                          \
+	(((x) & BIT_MASK_ABORT_RX_RDRDY_COUNTER)                               \
+	 << BIT_SHIFT_ABORT_RX_RDRDY_COUNTER)
+#define BITS_ABORT_RX_RDRDY_COUNTER                                            \
+	(BIT_MASK_ABORT_RX_RDRDY_COUNTER << BIT_SHIFT_ABORT_RX_RDRDY_COUNTER)
+#define BIT_CLEAR_ABORT_RX_RDRDY_COUNTER(x)                                    \
+	((x) & (~BITS_ABORT_RX_RDRDY_COUNTER))
+#define BIT_GET_ABORT_RX_RDRDY_COUNTER(x)                                      \
+	(((x) >> BIT_SHIFT_ABORT_RX_RDRDY_COUNTER) &                           \
+	 BIT_MASK_ABORT_RX_RDRDY_COUNTER)
+#define BIT_SET_ABORT_RX_RDRDY_COUNTER(x, v)                                   \
+	(BIT_CLEAR_ABORT_RX_RDRDY_COUNTER(x) | BIT_ABORT_RX_RDRDY_COUNTER(v))
+
+#define BIT_SHIFT_VBON_EARLY_FALLING_COUNTER 0
+#define BIT_MASK_VBON_EARLY_FALLING_COUNTER 0xff
+#define BIT_VBON_EARLY_FALLING_COUNTER(x)                                      \
+	(((x) & BIT_MASK_VBON_EARLY_FALLING_COUNTER)                           \
+	 << BIT_SHIFT_VBON_EARLY_FALLING_COUNTER)
+#define BITS_VBON_EARLY_FALLING_COUNTER                                        \
+	(BIT_MASK_VBON_EARLY_FALLING_COUNTER                                   \
+	 << BIT_SHIFT_VBON_EARLY_FALLING_COUNTER)
+#define BIT_CLEAR_VBON_EARLY_FALLING_COUNTER(x)                                \
+	((x) & (~BITS_VBON_EARLY_FALLING_COUNTER))
+#define BIT_GET_VBON_EARLY_FALLING_COUNTER(x)                                  \
+	(((x) >> BIT_SHIFT_VBON_EARLY_FALLING_COUNTER) &                       \
+	 BIT_MASK_VBON_EARLY_FALLING_COUNTER)
+#define BIT_SET_VBON_EARLY_FALLING_COUNTER(x, v)                               \
+	(BIT_CLEAR_VBON_EARLY_FALLING_COUNTER(x) |                             \
+	 BIT_VBON_EARLY_FALLING_COUNTER(v))
+
+/* 2 REG_WMAC_PLCP_MONITOR			(Offset 0x1694) */
+
+#define BIT_WMAC_PLCP_TRX_SEL BIT(31)
+
+#define BIT_SHIFT_WMAC_PLCP_RDSIG_SEL 28
+#define BIT_MASK_WMAC_PLCP_RDSIG_SEL 0x7
+#define BIT_WMAC_PLCP_RDSIG_SEL(x)                                             \
+	(((x) & BIT_MASK_WMAC_PLCP_RDSIG_SEL) << BIT_SHIFT_WMAC_PLCP_RDSIG_SEL)
+#define BITS_WMAC_PLCP_RDSIG_SEL                                               \
+	(BIT_MASK_WMAC_PLCP_RDSIG_SEL << BIT_SHIFT_WMAC_PLCP_RDSIG_SEL)
+#define BIT_CLEAR_WMAC_PLCP_RDSIG_SEL(x) ((x) & (~BITS_WMAC_PLCP_RDSIG_SEL))
+#define BIT_GET_WMAC_PLCP_RDSIG_SEL(x)                                         \
+	(((x) >> BIT_SHIFT_WMAC_PLCP_RDSIG_SEL) & BIT_MASK_WMAC_PLCP_RDSIG_SEL)
+#define BIT_SET_WMAC_PLCP_RDSIG_SEL(x, v)                                      \
+	(BIT_CLEAR_WMAC_PLCP_RDSIG_SEL(x) | BIT_WMAC_PLCP_RDSIG_SEL(v))
+
+#define BIT_SHIFT_WMAC_RATE_IDX 24
+#define BIT_MASK_WMAC_RATE_IDX 0xf
+#define BIT_WMAC_RATE_IDX(x)                                                   \
+	(((x) & BIT_MASK_WMAC_RATE_IDX) << BIT_SHIFT_WMAC_RATE_IDX)
+#define BITS_WMAC_RATE_IDX (BIT_MASK_WMAC_RATE_IDX << BIT_SHIFT_WMAC_RATE_IDX)
+#define BIT_CLEAR_WMAC_RATE_IDX(x) ((x) & (~BITS_WMAC_RATE_IDX))
+#define BIT_GET_WMAC_RATE_IDX(x)                                               \
+	(((x) >> BIT_SHIFT_WMAC_RATE_IDX) & BIT_MASK_WMAC_RATE_IDX)
+#define BIT_SET_WMAC_RATE_IDX(x, v)                                            \
+	(BIT_CLEAR_WMAC_RATE_IDX(x) | BIT_WMAC_RATE_IDX(v))
+
+#define BIT_SHIFT_WMAC_PLCP_RDSIG 0
+#define BIT_MASK_WMAC_PLCP_RDSIG 0xffffff
+#define BIT_WMAC_PLCP_RDSIG(x)                                                 \
+	(((x) & BIT_MASK_WMAC_PLCP_RDSIG) << BIT_SHIFT_WMAC_PLCP_RDSIG)
+#define BITS_WMAC_PLCP_RDSIG                                                   \
+	(BIT_MASK_WMAC_PLCP_RDSIG << BIT_SHIFT_WMAC_PLCP_RDSIG)
+#define BIT_CLEAR_WMAC_PLCP_RDSIG(x) ((x) & (~BITS_WMAC_PLCP_RDSIG))
+#define BIT_GET_WMAC_PLCP_RDSIG(x)                                             \
+	(((x) >> BIT_SHIFT_WMAC_PLCP_RDSIG) & BIT_MASK_WMAC_PLCP_RDSIG)
+#define BIT_SET_WMAC_PLCP_RDSIG(x, v)                                          \
+	(BIT_CLEAR_WMAC_PLCP_RDSIG(x) | BIT_WMAC_PLCP_RDSIG(v))
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_WMAC_PLCP_MONITOR_MUTX		(Offset 0x1698) */
+
+#define BIT_WMAC_MUTX_IDX BIT(24)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_WMAC_DEBUG_PORT			(Offset 0x1698) */
+
+#define BIT_SHIFT_WMAC_DEBUG_PORT 0
+#define BIT_MASK_WMAC_DEBUG_PORT 0xffffffffL
+#define BIT_WMAC_DEBUG_PORT(x)                                                 \
+	(((x) & BIT_MASK_WMAC_DEBUG_PORT) << BIT_SHIFT_WMAC_DEBUG_PORT)
+#define BITS_WMAC_DEBUG_PORT                                                   \
+	(BIT_MASK_WMAC_DEBUG_PORT << BIT_SHIFT_WMAC_DEBUG_PORT)
+#define BIT_CLEAR_WMAC_DEBUG_PORT(x) ((x) & (~BITS_WMAC_DEBUG_PORT))
+#define BIT_GET_WMAC_DEBUG_PORT(x)                                             \
+	(((x) >> BIT_SHIFT_WMAC_DEBUG_PORT) & BIT_MASK_WMAC_DEBUG_PORT)
+#define BIT_SET_WMAC_DEBUG_PORT(x, v)                                          \
+	(BIT_CLEAR_WMAC_DEBUG_PORT(x) | BIT_WMAC_DEBUG_PORT(v))
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_WMAC_CSIDMA_CFG			(Offset 0x169C) */
+
+#define BIT_SHIFT_CSI_SEG_SIZE 16
+#define BIT_MASK_CSI_SEG_SIZE 0xfff
+#define BIT_CSI_SEG_SIZE(x)                                                    \
+	(((x) & BIT_MASK_CSI_SEG_SIZE) << BIT_SHIFT_CSI_SEG_SIZE)
+#define BITS_CSI_SEG_SIZE (BIT_MASK_CSI_SEG_SIZE << BIT_SHIFT_CSI_SEG_SIZE)
+#define BIT_CLEAR_CSI_SEG_SIZE(x) ((x) & (~BITS_CSI_SEG_SIZE))
+#define BIT_GET_CSI_SEG_SIZE(x)                                                \
+	(((x) >> BIT_SHIFT_CSI_SEG_SIZE) & BIT_MASK_CSI_SEG_SIZE)
+#define BIT_SET_CSI_SEG_SIZE(x, v)                                             \
+	(BIT_CLEAR_CSI_SEG_SIZE(x) | BIT_CSI_SEG_SIZE(v))
+
+#define BIT_SHIFT_CSI_START_PAGE 0
+#define BIT_MASK_CSI_START_PAGE 0xfff
+#define BIT_CSI_START_PAGE(x)                                                  \
+	(((x) & BIT_MASK_CSI_START_PAGE) << BIT_SHIFT_CSI_START_PAGE)
+#define BITS_CSI_START_PAGE                                                    \
+	(BIT_MASK_CSI_START_PAGE << BIT_SHIFT_CSI_START_PAGE)
+#define BIT_CLEAR_CSI_START_PAGE(x) ((x) & (~BITS_CSI_START_PAGE))
+#define BIT_GET_CSI_START_PAGE(x)                                              \
+	(((x) >> BIT_SHIFT_CSI_START_PAGE) & BIT_MASK_CSI_START_PAGE)
+#define BIT_SET_CSI_START_PAGE(x, v)                                           \
+	(BIT_CLEAR_CSI_START_PAGE(x) | BIT_CSI_START_PAGE(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822B_SUPPORT)
+
+/* 2 REG_TRANSMIT_ADDRSS_0			(Offset 0x16A0) */
+
+#define BIT_SHIFT_TA0 0
+#define BIT_MASK_TA0 0xffffffffffffL
+#define BIT_TA0(x) (((x) & BIT_MASK_TA0) << BIT_SHIFT_TA0)
+#define BITS_TA0 (BIT_MASK_TA0 << BIT_SHIFT_TA0)
+#define BIT_CLEAR_TA0(x) ((x) & (~BITS_TA0))
+#define BIT_GET_TA0(x) (((x) >> BIT_SHIFT_TA0) & BIT_MASK_TA0)
+#define BIT_SET_TA0(x, v) (BIT_CLEAR_TA0(x) | BIT_TA0(v))
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_TRANSMIT_ADDRSS_0			(Offset 0x16A0) */
+
+#define BIT_SHIFT_TA0_V1 0
+#define BIT_MASK_TA0_V1 0xffffffffL
+#define BIT_TA0_V1(x) (((x) & BIT_MASK_TA0_V1) << BIT_SHIFT_TA0_V1)
+#define BITS_TA0_V1 (BIT_MASK_TA0_V1 << BIT_SHIFT_TA0_V1)
+#define BIT_CLEAR_TA0_V1(x) ((x) & (~BITS_TA0_V1))
+#define BIT_GET_TA0_V1(x) (((x) >> BIT_SHIFT_TA0_V1) & BIT_MASK_TA0_V1)
+#define BIT_SET_TA0_V1(x, v) (BIT_CLEAR_TA0_V1(x) | BIT_TA0_V1(v))
+
+/* 2 REG_TRANSMIT_ADDRSS_0_H			(Offset 0x16A4) */
+
+#define BIT_SHIFT_TA0_H_V1 0
+#define BIT_MASK_TA0_H_V1 0xffff
+#define BIT_TA0_H_V1(x) (((x) & BIT_MASK_TA0_H_V1) << BIT_SHIFT_TA0_H_V1)
+#define BITS_TA0_H_V1 (BIT_MASK_TA0_H_V1 << BIT_SHIFT_TA0_H_V1)
+#define BIT_CLEAR_TA0_H_V1(x) ((x) & (~BITS_TA0_H_V1))
+#define BIT_GET_TA0_H_V1(x) (((x) >> BIT_SHIFT_TA0_H_V1) & BIT_MASK_TA0_H_V1)
+#define BIT_SET_TA0_H_V1(x, v) (BIT_CLEAR_TA0_H_V1(x) | BIT_TA0_H_V1(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822B_SUPPORT)
+
+/* 2 REG_TRANSMIT_ADDRSS_1			(Offset 0x16A8) */
+
+#define BIT_SHIFT_TA1 0
+#define BIT_MASK_TA1 0xffffffffffffL
+#define BIT_TA1(x) (((x) & BIT_MASK_TA1) << BIT_SHIFT_TA1)
+#define BITS_TA1 (BIT_MASK_TA1 << BIT_SHIFT_TA1)
+#define BIT_CLEAR_TA1(x) ((x) & (~BITS_TA1))
+#define BIT_GET_TA1(x) (((x) >> BIT_SHIFT_TA1) & BIT_MASK_TA1)
+#define BIT_SET_TA1(x, v) (BIT_CLEAR_TA1(x) | BIT_TA1(v))
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_TRANSMIT_ADDRSS_1			(Offset 0x16A8) */
+
+#define BIT_SHIFT_TA1_V1 0
+#define BIT_MASK_TA1_V1 0xffffffffL
+#define BIT_TA1_V1(x) (((x) & BIT_MASK_TA1_V1) << BIT_SHIFT_TA1_V1)
+#define BITS_TA1_V1 (BIT_MASK_TA1_V1 << BIT_SHIFT_TA1_V1)
+#define BIT_CLEAR_TA1_V1(x) ((x) & (~BITS_TA1_V1))
+#define BIT_GET_TA1_V1(x) (((x) >> BIT_SHIFT_TA1_V1) & BIT_MASK_TA1_V1)
+#define BIT_SET_TA1_V1(x, v) (BIT_CLEAR_TA1_V1(x) | BIT_TA1_V1(v))
+
+/* 2 REG_TRANSMIT_ADDRSS_1_H			(Offset 0x16AC) */
+
+#define BIT_SHIFT_TA1_H_V1 0
+#define BIT_MASK_TA1_H_V1 0xffff
+#define BIT_TA1_H_V1(x) (((x) & BIT_MASK_TA1_H_V1) << BIT_SHIFT_TA1_H_V1)
+#define BITS_TA1_H_V1 (BIT_MASK_TA1_H_V1 << BIT_SHIFT_TA1_H_V1)
+#define BIT_CLEAR_TA1_H_V1(x) ((x) & (~BITS_TA1_H_V1))
+#define BIT_GET_TA1_H_V1(x) (((x) >> BIT_SHIFT_TA1_H_V1) & BIT_MASK_TA1_H_V1)
+#define BIT_SET_TA1_H_V1(x, v) (BIT_CLEAR_TA1_H_V1(x) | BIT_TA1_H_V1(v))
+
+#define BIT_SHIFT_TA2_V1 0
+#define BIT_MASK_TA2_V1 0xffffffffL
+#define BIT_TA2_V1(x) (((x) & BIT_MASK_TA2_V1) << BIT_SHIFT_TA2_V1)
+#define BITS_TA2_V1 (BIT_MASK_TA2_V1 << BIT_SHIFT_TA2_V1)
+#define BIT_CLEAR_TA2_V1(x) ((x) & (~BITS_TA2_V1))
+#define BIT_GET_TA2_V1(x) (((x) >> BIT_SHIFT_TA2_V1) & BIT_MASK_TA2_V1)
+#define BIT_SET_TA2_V1(x, v) (BIT_CLEAR_TA2_V1(x) | BIT_TA2_V1(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822B_SUPPORT)
+
+/* 2 REG_TRANSMIT_ADDRSS_2			(Offset 0x16B0) */
+
+#define BIT_SHIFT_TA2 0
+#define BIT_MASK_TA2 0xffffffffffffL
+#define BIT_TA2(x) (((x) & BIT_MASK_TA2) << BIT_SHIFT_TA2)
+#define BITS_TA2 (BIT_MASK_TA2 << BIT_SHIFT_TA2)
+#define BIT_CLEAR_TA2(x) ((x) & (~BITS_TA2))
+#define BIT_GET_TA2(x) (((x) >> BIT_SHIFT_TA2) & BIT_MASK_TA2)
+#define BIT_SET_TA2(x, v) (BIT_CLEAR_TA2(x) | BIT_TA2(v))
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_TRANSMIT_ADDRSS_2_H			(Offset 0x16B4) */
+
+#define BIT_SHIFT_TA2_H_V1 0
+#define BIT_MASK_TA2_H_V1 0xffff
+#define BIT_TA2_H_V1(x) (((x) & BIT_MASK_TA2_H_V1) << BIT_SHIFT_TA2_H_V1)
+#define BITS_TA2_H_V1 (BIT_MASK_TA2_H_V1 << BIT_SHIFT_TA2_H_V1)
+#define BIT_CLEAR_TA2_H_V1(x) ((x) & (~BITS_TA2_H_V1))
+#define BIT_GET_TA2_H_V1(x) (((x) >> BIT_SHIFT_TA2_H_V1) & BIT_MASK_TA2_H_V1)
+#define BIT_SET_TA2_H_V1(x, v) (BIT_CLEAR_TA2_H_V1(x) | BIT_TA2_H_V1(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822B_SUPPORT)
+
+/* 2 REG_TRANSMIT_ADDRSS_3			(Offset 0x16B8) */
+
+#define BIT_SHIFT_TA3 0
+#define BIT_MASK_TA3 0xffffffffffffL
+#define BIT_TA3(x) (((x) & BIT_MASK_TA3) << BIT_SHIFT_TA3)
+#define BITS_TA3 (BIT_MASK_TA3 << BIT_SHIFT_TA3)
+#define BIT_CLEAR_TA3(x) ((x) & (~BITS_TA3))
+#define BIT_GET_TA3(x) (((x) >> BIT_SHIFT_TA3) & BIT_MASK_TA3)
+#define BIT_SET_TA3(x, v) (BIT_CLEAR_TA3(x) | BIT_TA3(v))
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_TRANSMIT_ADDRSS_3_H			(Offset 0x16BC) */
+
+#define BIT_SHIFT_TA3_H_V1 0
+#define BIT_MASK_TA3_H_V1 0xffff
+#define BIT_TA3_H_V1(x) (((x) & BIT_MASK_TA3_H_V1) << BIT_SHIFT_TA3_H_V1)
+#define BITS_TA3_H_V1 (BIT_MASK_TA3_H_V1 << BIT_SHIFT_TA3_H_V1)
+#define BIT_CLEAR_TA3_H_V1(x) ((x) & (~BITS_TA3_H_V1))
+#define BIT_GET_TA3_H_V1(x) (((x) >> BIT_SHIFT_TA3_H_V1) & BIT_MASK_TA3_H_V1)
+#define BIT_SET_TA3_H_V1(x, v) (BIT_CLEAR_TA3_H_V1(x) | BIT_TA3_H_V1(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822B_SUPPORT)
+
+/* 2 REG_TRANSMIT_ADDRSS_4			(Offset 0x16C0) */
+
+#define BIT_R_WMAC_RX_SYNCFIFO_SYNC BIT(55)
+#define BIT_R_WMAC_RXRST_DLY BIT(54)
+#define BIT_R_WMAC_SRCH_TXRPT_REF_DROP BIT(53)
+#define BIT_R_WMAC_SRCH_TXRPT_UA1 BIT(52)
+
+#define BIT_SHIFT_TA4 0
+#define BIT_MASK_TA4 0xffffffffffffL
+#define BIT_TA4(x) (((x) & BIT_MASK_TA4) << BIT_SHIFT_TA4)
+#define BITS_TA4 (BIT_MASK_TA4 << BIT_SHIFT_TA4)
+#define BIT_CLEAR_TA4(x) ((x) & (~BITS_TA4))
+#define BIT_GET_TA4(x) (((x) >> BIT_SHIFT_TA4) & BIT_MASK_TA4)
+#define BIT_SET_TA4(x, v) (BIT_CLEAR_TA4(x) | BIT_TA4(v))
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_TRANSMIT_ADDRSS_4			(Offset 0x16C0) */
+
+#define BIT_SHIFT_TA4_V1 0
+#define BIT_MASK_TA4_V1 0xffffffffL
+#define BIT_TA4_V1(x) (((x) & BIT_MASK_TA4_V1) << BIT_SHIFT_TA4_V1)
+#define BITS_TA4_V1 (BIT_MASK_TA4_V1 << BIT_SHIFT_TA4_V1)
+#define BIT_CLEAR_TA4_V1(x) ((x) & (~BITS_TA4_V1))
+#define BIT_GET_TA4_V1(x) (((x) >> BIT_SHIFT_TA4_V1) & BIT_MASK_TA4_V1)
+#define BIT_SET_TA4_V1(x, v) (BIT_CLEAR_TA4_V1(x) | BIT_TA4_V1(v))
+
+/* 2 REG_TRANSMIT_ADDRSS_4_H			(Offset 0x16C4) */
+
+#define BIT_SHIFT_TA4_H_V1 0
+#define BIT_MASK_TA4_H_V1 0xffff
+#define BIT_TA4_H_V1(x) (((x) & BIT_MASK_TA4_H_V1) << BIT_SHIFT_TA4_H_V1)
+#define BITS_TA4_H_V1 (BIT_MASK_TA4_H_V1 << BIT_SHIFT_TA4_H_V1)
+#define BIT_CLEAR_TA4_H_V1(x) ((x) & (~BITS_TA4_H_V1))
+#define BIT_GET_TA4_H_V1(x) (((x) >> BIT_SHIFT_TA4_H_V1) & BIT_MASK_TA4_H_V1)
+#define BIT_SET_TA4_H_V1(x, v) (BIT_CLEAR_TA4_H_V1(x) | BIT_TA4_H_V1(v))
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT)
+
+/* 2 REG_SND_AID12				(Offset 0x16D0) */
+
+#define BIT_SHIFT_USERID_SEL 12
+#define BIT_MASK_USERID_SEL 0x7
+#define BIT_USERID_SEL(x) (((x) & BIT_MASK_USERID_SEL) << BIT_SHIFT_USERID_SEL)
+#define BITS_USERID_SEL (BIT_MASK_USERID_SEL << BIT_SHIFT_USERID_SEL)
+#define BIT_CLEAR_USERID_SEL(x) ((x) & (~BITS_USERID_SEL))
+#define BIT_GET_USERID_SEL(x)                                                  \
+	(((x) >> BIT_SHIFT_USERID_SEL) & BIT_MASK_USERID_SEL)
+#define BIT_SET_USERID_SEL(x, v) (BIT_CLEAR_USERID_SEL(x) | BIT_USERID_SEL(v))
+
+#define BIT_SHIFT_USERID_AID12 0
+#define BIT_MASK_USERID_AID12 0xfff
+#define BIT_USERID_AID12(x)                                                    \
+	(((x) & BIT_MASK_USERID_AID12) << BIT_SHIFT_USERID_AID12)
+#define BITS_USERID_AID12 (BIT_MASK_USERID_AID12 << BIT_SHIFT_USERID_AID12)
+#define BIT_CLEAR_USERID_AID12(x) ((x) & (~BITS_USERID_AID12))
+#define BIT_GET_USERID_AID12(x)                                                \
+	(((x) >> BIT_SHIFT_USERID_AID12) & BIT_MASK_USERID_AID12)
+#define BIT_SET_USERID_AID12(x, v)                                             \
+	(BIT_CLEAR_USERID_AID12(x) | BIT_USERID_AID12(v))
+
+/* 2 REG_SND_PKT_INFO			(Offset 0x16D2) */
+
+#define BIT_SND_FROM_DS BIT(7)
+#define BIT_SND_TO_DS BIT(6)
+
+#define BIT_SHIFT_SND_TOKEN 0
+#define BIT_MASK_SND_TOKEN 0x3f
+#define BIT_SND_TOKEN(x) (((x) & BIT_MASK_SND_TOKEN) << BIT_SHIFT_SND_TOKEN)
+#define BITS_SND_TOKEN (BIT_MASK_SND_TOKEN << BIT_SHIFT_SND_TOKEN)
+#define BIT_CLEAR_SND_TOKEN(x) ((x) & (~BITS_SND_TOKEN))
+#define BIT_GET_SND_TOKEN(x) (((x) >> BIT_SHIFT_SND_TOKEN) & BIT_MASK_SND_TOKEN)
+#define BIT_SET_SND_TOKEN(x, v) (BIT_CLEAR_SND_TOKEN(x) | BIT_SND_TOKEN(v))
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_WL2LTECOEX_INDIRECT_ACCESS_CTRL_V1 (Offset 0x1700) */
+
+#define BIT_LTECOEX_ACCESS_START_V1 BIT(31)
+#define BIT_LTECOEX_WRITE_MODE_V1 BIT(30)
+#define BIT_LTECOEX_READY_BIT_V1 BIT(29)
+
+#define BIT_SHIFT_WRITE_BYTE_EN_V1 16
+#define BIT_MASK_WRITE_BYTE_EN_V1 0xf
+#define BIT_WRITE_BYTE_EN_V1(x)                                                \
+	(((x) & BIT_MASK_WRITE_BYTE_EN_V1) << BIT_SHIFT_WRITE_BYTE_EN_V1)
+#define BITS_WRITE_BYTE_EN_V1                                                  \
+	(BIT_MASK_WRITE_BYTE_EN_V1 << BIT_SHIFT_WRITE_BYTE_EN_V1)
+#define BIT_CLEAR_WRITE_BYTE_EN_V1(x) ((x) & (~BITS_WRITE_BYTE_EN_V1))
+#define BIT_GET_WRITE_BYTE_EN_V1(x)                                            \
+	(((x) >> BIT_SHIFT_WRITE_BYTE_EN_V1) & BIT_MASK_WRITE_BYTE_EN_V1)
+#define BIT_SET_WRITE_BYTE_EN_V1(x, v)                                         \
+	(BIT_CLEAR_WRITE_BYTE_EN_V1(x) | BIT_WRITE_BYTE_EN_V1(v))
+
+#define BIT_SHIFT_LTECOEX_REG_ADDR_V1 0
+#define BIT_MASK_LTECOEX_REG_ADDR_V1 0xffff
+#define BIT_LTECOEX_REG_ADDR_V1(x)                                             \
+	(((x) & BIT_MASK_LTECOEX_REG_ADDR_V1) << BIT_SHIFT_LTECOEX_REG_ADDR_V1)
+#define BITS_LTECOEX_REG_ADDR_V1                                               \
+	(BIT_MASK_LTECOEX_REG_ADDR_V1 << BIT_SHIFT_LTECOEX_REG_ADDR_V1)
+#define BIT_CLEAR_LTECOEX_REG_ADDR_V1(x) ((x) & (~BITS_LTECOEX_REG_ADDR_V1))
+#define BIT_GET_LTECOEX_REG_ADDR_V1(x)                                         \
+	(((x) >> BIT_SHIFT_LTECOEX_REG_ADDR_V1) & BIT_MASK_LTECOEX_REG_ADDR_V1)
+#define BIT_SET_LTECOEX_REG_ADDR_V1(x, v)                                      \
+	(BIT_CLEAR_LTECOEX_REG_ADDR_V1(x) | BIT_LTECOEX_REG_ADDR_V1(v))
+
+/* 2 REG_WL2LTECOEX_INDIRECT_ACCESS_WRITE_DATA_V1 (Offset 0x1704) */
+
+#define BIT_SHIFT_LTECOEX_W_DATA_V1 0
+#define BIT_MASK_LTECOEX_W_DATA_V1 0xffffffffL
+#define BIT_LTECOEX_W_DATA_V1(x)                                               \
+	(((x) & BIT_MASK_LTECOEX_W_DATA_V1) << BIT_SHIFT_LTECOEX_W_DATA_V1)
+#define BITS_LTECOEX_W_DATA_V1                                                 \
+	(BIT_MASK_LTECOEX_W_DATA_V1 << BIT_SHIFT_LTECOEX_W_DATA_V1)
+#define BIT_CLEAR_LTECOEX_W_DATA_V1(x) ((x) & (~BITS_LTECOEX_W_DATA_V1))
+#define BIT_GET_LTECOEX_W_DATA_V1(x)                                           \
+	(((x) >> BIT_SHIFT_LTECOEX_W_DATA_V1) & BIT_MASK_LTECOEX_W_DATA_V1)
+#define BIT_SET_LTECOEX_W_DATA_V1(x, v)                                        \
+	(BIT_CLEAR_LTECOEX_W_DATA_V1(x) | BIT_LTECOEX_W_DATA_V1(v))
+
+/* 2 REG_WL2LTECOEX_INDIRECT_ACCESS_READ_DATA_V1 (Offset 0x1708) */
+
+#define BIT_SHIFT_LTECOEX_R_DATA_V1 0
+#define BIT_MASK_LTECOEX_R_DATA_V1 0xffffffffL
+#define BIT_LTECOEX_R_DATA_V1(x)                                               \
+	(((x) & BIT_MASK_LTECOEX_R_DATA_V1) << BIT_SHIFT_LTECOEX_R_DATA_V1)
+#define BITS_LTECOEX_R_DATA_V1                                                 \
+	(BIT_MASK_LTECOEX_R_DATA_V1 << BIT_SHIFT_LTECOEX_R_DATA_V1)
+#define BIT_CLEAR_LTECOEX_R_DATA_V1(x) ((x) & (~BITS_LTECOEX_R_DATA_V1))
+#define BIT_GET_LTECOEX_R_DATA_V1(x)                                           \
+	(((x) >> BIT_SHIFT_LTECOEX_R_DATA_V1) & BIT_MASK_LTECOEX_R_DATA_V1)
+#define BIT_SET_LTECOEX_R_DATA_V1(x, v)                                        \
+	(BIT_CLEAR_LTECOEX_R_DATA_V1(x) | BIT_LTECOEX_R_DATA_V1(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_DMA_RQPN_INFO_0			(Offset 0x2200) */
+
+#define BIT_SHIFT_CH0_AVAL_PG 16
+#define BIT_MASK_CH0_AVAL_PG 0xfff
+#define BIT_CH0_AVAL_PG(x)                                                     \
+	(((x) & BIT_MASK_CH0_AVAL_PG) << BIT_SHIFT_CH0_AVAL_PG)
+#define BITS_CH0_AVAL_PG (BIT_MASK_CH0_AVAL_PG << BIT_SHIFT_CH0_AVAL_PG)
+#define BIT_CLEAR_CH0_AVAL_PG(x) ((x) & (~BITS_CH0_AVAL_PG))
+#define BIT_GET_CH0_AVAL_PG(x)                                                 \
+	(((x) >> BIT_SHIFT_CH0_AVAL_PG) & BIT_MASK_CH0_AVAL_PG)
+#define BIT_SET_CH0_AVAL_PG(x, v)                                              \
+	(BIT_CLEAR_CH0_AVAL_PG(x) | BIT_CH0_AVAL_PG(v))
+
+#define BIT_SHIFT_CH0_RSVD_PG 0
+#define BIT_MASK_CH0_RSVD_PG 0xfff
+#define BIT_CH0_RSVD_PG(x)                                                     \
+	(((x) & BIT_MASK_CH0_RSVD_PG) << BIT_SHIFT_CH0_RSVD_PG)
+#define BITS_CH0_RSVD_PG (BIT_MASK_CH0_RSVD_PG << BIT_SHIFT_CH0_RSVD_PG)
+#define BIT_CLEAR_CH0_RSVD_PG(x) ((x) & (~BITS_CH0_RSVD_PG))
+#define BIT_GET_CH0_RSVD_PG(x)                                                 \
+	(((x) >> BIT_SHIFT_CH0_RSVD_PG) & BIT_MASK_CH0_RSVD_PG)
+#define BIT_SET_CH0_RSVD_PG(x, v)                                              \
+	(BIT_CLEAR_CH0_RSVD_PG(x) | BIT_CH0_RSVD_PG(v))
+
+/* 2 REG_DMA_RQPN_INFO_1			(Offset 0x2204) */
+
+#define BIT_SHIFT_CH1_AVAL_PG 16
+#define BIT_MASK_CH1_AVAL_PG 0xfff
+#define BIT_CH1_AVAL_PG(x)                                                     \
+	(((x) & BIT_MASK_CH1_AVAL_PG) << BIT_SHIFT_CH1_AVAL_PG)
+#define BITS_CH1_AVAL_PG (BIT_MASK_CH1_AVAL_PG << BIT_SHIFT_CH1_AVAL_PG)
+#define BIT_CLEAR_CH1_AVAL_PG(x) ((x) & (~BITS_CH1_AVAL_PG))
+#define BIT_GET_CH1_AVAL_PG(x)                                                 \
+	(((x) >> BIT_SHIFT_CH1_AVAL_PG) & BIT_MASK_CH1_AVAL_PG)
+#define BIT_SET_CH1_AVAL_PG(x, v)                                              \
+	(BIT_CLEAR_CH1_AVAL_PG(x) | BIT_CH1_AVAL_PG(v))
+
+#define BIT_SHIFT_CH1_RSVD_PG 0
+#define BIT_MASK_CH1_RSVD_PG 0xfff
+#define BIT_CH1_RSVD_PG(x)                                                     \
+	(((x) & BIT_MASK_CH1_RSVD_PG) << BIT_SHIFT_CH1_RSVD_PG)
+#define BITS_CH1_RSVD_PG (BIT_MASK_CH1_RSVD_PG << BIT_SHIFT_CH1_RSVD_PG)
+#define BIT_CLEAR_CH1_RSVD_PG(x) ((x) & (~BITS_CH1_RSVD_PG))
+#define BIT_GET_CH1_RSVD_PG(x)                                                 \
+	(((x) >> BIT_SHIFT_CH1_RSVD_PG) & BIT_MASK_CH1_RSVD_PG)
+#define BIT_SET_CH1_RSVD_PG(x, v)                                              \
+	(BIT_CLEAR_CH1_RSVD_PG(x) | BIT_CH1_RSVD_PG(v))
+
+/* 2 REG_DMA_RQPN_INFO_2			(Offset 0x2208) */
+
+#define BIT_SHIFT_CH2_AVAL_PG 16
+#define BIT_MASK_CH2_AVAL_PG 0xfff
+#define BIT_CH2_AVAL_PG(x)                                                     \
+	(((x) & BIT_MASK_CH2_AVAL_PG) << BIT_SHIFT_CH2_AVAL_PG)
+#define BITS_CH2_AVAL_PG (BIT_MASK_CH2_AVAL_PG << BIT_SHIFT_CH2_AVAL_PG)
+#define BIT_CLEAR_CH2_AVAL_PG(x) ((x) & (~BITS_CH2_AVAL_PG))
+#define BIT_GET_CH2_AVAL_PG(x)                                                 \
+	(((x) >> BIT_SHIFT_CH2_AVAL_PG) & BIT_MASK_CH2_AVAL_PG)
+#define BIT_SET_CH2_AVAL_PG(x, v)                                              \
+	(BIT_CLEAR_CH2_AVAL_PG(x) | BIT_CH2_AVAL_PG(v))
+
+#define BIT_SHIFT_CH2_RSVD_PG 0
+#define BIT_MASK_CH2_RSVD_PG 0xfff
+#define BIT_CH2_RSVD_PG(x)                                                     \
+	(((x) & BIT_MASK_CH2_RSVD_PG) << BIT_SHIFT_CH2_RSVD_PG)
+#define BITS_CH2_RSVD_PG (BIT_MASK_CH2_RSVD_PG << BIT_SHIFT_CH2_RSVD_PG)
+#define BIT_CLEAR_CH2_RSVD_PG(x) ((x) & (~BITS_CH2_RSVD_PG))
+#define BIT_GET_CH2_RSVD_PG(x)                                                 \
+	(((x) >> BIT_SHIFT_CH2_RSVD_PG) & BIT_MASK_CH2_RSVD_PG)
+#define BIT_SET_CH2_RSVD_PG(x, v)                                              \
+	(BIT_CLEAR_CH2_RSVD_PG(x) | BIT_CH2_RSVD_PG(v))
+
+/* 2 REG_DMA_RQPN_INFO_3			(Offset 0x220C) */
+
+#define BIT_SHIFT_CH3_AVAL_PG 16
+#define BIT_MASK_CH3_AVAL_PG 0xfff
+#define BIT_CH3_AVAL_PG(x)                                                     \
+	(((x) & BIT_MASK_CH3_AVAL_PG) << BIT_SHIFT_CH3_AVAL_PG)
+#define BITS_CH3_AVAL_PG (BIT_MASK_CH3_AVAL_PG << BIT_SHIFT_CH3_AVAL_PG)
+#define BIT_CLEAR_CH3_AVAL_PG(x) ((x) & (~BITS_CH3_AVAL_PG))
+#define BIT_GET_CH3_AVAL_PG(x)                                                 \
+	(((x) >> BIT_SHIFT_CH3_AVAL_PG) & BIT_MASK_CH3_AVAL_PG)
+#define BIT_SET_CH3_AVAL_PG(x, v)                                              \
+	(BIT_CLEAR_CH3_AVAL_PG(x) | BIT_CH3_AVAL_PG(v))
+
+#define BIT_SHIFT_CH3_RSVD_PG 0
+#define BIT_MASK_CH3_RSVD_PG 0xfff
+#define BIT_CH3_RSVD_PG(x)                                                     \
+	(((x) & BIT_MASK_CH3_RSVD_PG) << BIT_SHIFT_CH3_RSVD_PG)
+#define BITS_CH3_RSVD_PG (BIT_MASK_CH3_RSVD_PG << BIT_SHIFT_CH3_RSVD_PG)
+#define BIT_CLEAR_CH3_RSVD_PG(x) ((x) & (~BITS_CH3_RSVD_PG))
+#define BIT_GET_CH3_RSVD_PG(x)                                                 \
+	(((x) >> BIT_SHIFT_CH3_RSVD_PG) & BIT_MASK_CH3_RSVD_PG)
+#define BIT_SET_CH3_RSVD_PG(x, v)                                              \
+	(BIT_CLEAR_CH3_RSVD_PG(x) | BIT_CH3_RSVD_PG(v))
+
+/* 2 REG_DMA_RQPN_INFO_4			(Offset 0x2210) */
+
+#define BIT_SHIFT_CH4_AVAL_PG 16
+#define BIT_MASK_CH4_AVAL_PG 0xfff
+#define BIT_CH4_AVAL_PG(x)                                                     \
+	(((x) & BIT_MASK_CH4_AVAL_PG) << BIT_SHIFT_CH4_AVAL_PG)
+#define BITS_CH4_AVAL_PG (BIT_MASK_CH4_AVAL_PG << BIT_SHIFT_CH4_AVAL_PG)
+#define BIT_CLEAR_CH4_AVAL_PG(x) ((x) & (~BITS_CH4_AVAL_PG))
+#define BIT_GET_CH4_AVAL_PG(x)                                                 \
+	(((x) >> BIT_SHIFT_CH4_AVAL_PG) & BIT_MASK_CH4_AVAL_PG)
+#define BIT_SET_CH4_AVAL_PG(x, v)                                              \
+	(BIT_CLEAR_CH4_AVAL_PG(x) | BIT_CH4_AVAL_PG(v))
+
+#define BIT_SHIFT_CH4_RSVD_PG 0
+#define BIT_MASK_CH4_RSVD_PG 0xfff
+#define BIT_CH4_RSVD_PG(x)                                                     \
+	(((x) & BIT_MASK_CH4_RSVD_PG) << BIT_SHIFT_CH4_RSVD_PG)
+#define BITS_CH4_RSVD_PG (BIT_MASK_CH4_RSVD_PG << BIT_SHIFT_CH4_RSVD_PG)
+#define BIT_CLEAR_CH4_RSVD_PG(x) ((x) & (~BITS_CH4_RSVD_PG))
+#define BIT_GET_CH4_RSVD_PG(x)                                                 \
+	(((x) >> BIT_SHIFT_CH4_RSVD_PG) & BIT_MASK_CH4_RSVD_PG)
+#define BIT_SET_CH4_RSVD_PG(x, v)                                              \
+	(BIT_CLEAR_CH4_RSVD_PG(x) | BIT_CH4_RSVD_PG(v))
+
+/* 2 REG_DMA_RQPN_INFO_5			(Offset 0x2214) */
+
+#define BIT_SHIFT_CH5_AVAL_PG 16
+#define BIT_MASK_CH5_AVAL_PG 0xfff
+#define BIT_CH5_AVAL_PG(x)                                                     \
+	(((x) & BIT_MASK_CH5_AVAL_PG) << BIT_SHIFT_CH5_AVAL_PG)
+#define BITS_CH5_AVAL_PG (BIT_MASK_CH5_AVAL_PG << BIT_SHIFT_CH5_AVAL_PG)
+#define BIT_CLEAR_CH5_AVAL_PG(x) ((x) & (~BITS_CH5_AVAL_PG))
+#define BIT_GET_CH5_AVAL_PG(x)                                                 \
+	(((x) >> BIT_SHIFT_CH5_AVAL_PG) & BIT_MASK_CH5_AVAL_PG)
+#define BIT_SET_CH5_AVAL_PG(x, v)                                              \
+	(BIT_CLEAR_CH5_AVAL_PG(x) | BIT_CH5_AVAL_PG(v))
+
+#define BIT_SHIFT_CH5_RSVD_PG 0
+#define BIT_MASK_CH5_RSVD_PG 0xfff
+#define BIT_CH5_RSVD_PG(x)                                                     \
+	(((x) & BIT_MASK_CH5_RSVD_PG) << BIT_SHIFT_CH5_RSVD_PG)
+#define BITS_CH5_RSVD_PG (BIT_MASK_CH5_RSVD_PG << BIT_SHIFT_CH5_RSVD_PG)
+#define BIT_CLEAR_CH5_RSVD_PG(x) ((x) & (~BITS_CH5_RSVD_PG))
+#define BIT_GET_CH5_RSVD_PG(x)                                                 \
+	(((x) >> BIT_SHIFT_CH5_RSVD_PG) & BIT_MASK_CH5_RSVD_PG)
+#define BIT_SET_CH5_RSVD_PG(x, v)                                              \
+	(BIT_CLEAR_CH5_RSVD_PG(x) | BIT_CH5_RSVD_PG(v))
+
+/* 2 REG_DMA_RQPN_INFO_6			(Offset 0x2218) */
+
+#define BIT_SHIFT_CH6_AVAL_PG 16
+#define BIT_MASK_CH6_AVAL_PG 0xfff
+#define BIT_CH6_AVAL_PG(x)                                                     \
+	(((x) & BIT_MASK_CH6_AVAL_PG) << BIT_SHIFT_CH6_AVAL_PG)
+#define BITS_CH6_AVAL_PG (BIT_MASK_CH6_AVAL_PG << BIT_SHIFT_CH6_AVAL_PG)
+#define BIT_CLEAR_CH6_AVAL_PG(x) ((x) & (~BITS_CH6_AVAL_PG))
+#define BIT_GET_CH6_AVAL_PG(x)                                                 \
+	(((x) >> BIT_SHIFT_CH6_AVAL_PG) & BIT_MASK_CH6_AVAL_PG)
+#define BIT_SET_CH6_AVAL_PG(x, v)                                              \
+	(BIT_CLEAR_CH6_AVAL_PG(x) | BIT_CH6_AVAL_PG(v))
+
+#define BIT_SHIFT_CH6_RSVD_PG 0
+#define BIT_MASK_CH6_RSVD_PG 0xfff
+#define BIT_CH6_RSVD_PG(x)                                                     \
+	(((x) & BIT_MASK_CH6_RSVD_PG) << BIT_SHIFT_CH6_RSVD_PG)
+#define BITS_CH6_RSVD_PG (BIT_MASK_CH6_RSVD_PG << BIT_SHIFT_CH6_RSVD_PG)
+#define BIT_CLEAR_CH6_RSVD_PG(x) ((x) & (~BITS_CH6_RSVD_PG))
+#define BIT_GET_CH6_RSVD_PG(x)                                                 \
+	(((x) >> BIT_SHIFT_CH6_RSVD_PG) & BIT_MASK_CH6_RSVD_PG)
+#define BIT_SET_CH6_RSVD_PG(x, v)                                              \
+	(BIT_CLEAR_CH6_RSVD_PG(x) | BIT_CH6_RSVD_PG(v))
+
+/* 2 REG_DMA_RQPN_INFO_7			(Offset 0x221C) */
+
+#define BIT_SHIFT_CH7_AVAL_PG 16
+#define BIT_MASK_CH7_AVAL_PG 0xfff
+#define BIT_CH7_AVAL_PG(x)                                                     \
+	(((x) & BIT_MASK_CH7_AVAL_PG) << BIT_SHIFT_CH7_AVAL_PG)
+#define BITS_CH7_AVAL_PG (BIT_MASK_CH7_AVAL_PG << BIT_SHIFT_CH7_AVAL_PG)
+#define BIT_CLEAR_CH7_AVAL_PG(x) ((x) & (~BITS_CH7_AVAL_PG))
+#define BIT_GET_CH7_AVAL_PG(x)                                                 \
+	(((x) >> BIT_SHIFT_CH7_AVAL_PG) & BIT_MASK_CH7_AVAL_PG)
+#define BIT_SET_CH7_AVAL_PG(x, v)                                              \
+	(BIT_CLEAR_CH7_AVAL_PG(x) | BIT_CH7_AVAL_PG(v))
+
+#define BIT_SHIFT_CH7_RSVD_PG 0
+#define BIT_MASK_CH7_RSVD_PG 0xfff
+#define BIT_CH7_RSVD_PG(x)                                                     \
+	(((x) & BIT_MASK_CH7_RSVD_PG) << BIT_SHIFT_CH7_RSVD_PG)
+#define BITS_CH7_RSVD_PG (BIT_MASK_CH7_RSVD_PG << BIT_SHIFT_CH7_RSVD_PG)
+#define BIT_CLEAR_CH7_RSVD_PG(x) ((x) & (~BITS_CH7_RSVD_PG))
+#define BIT_GET_CH7_RSVD_PG(x)                                                 \
+	(((x) >> BIT_SHIFT_CH7_RSVD_PG) & BIT_MASK_CH7_RSVD_PG)
+#define BIT_SET_CH7_RSVD_PG(x, v)                                              \
+	(BIT_CLEAR_CH7_RSVD_PG(x) | BIT_CH7_RSVD_PG(v))
+
+/* 2 REG_DMA_RQPN_INFO_8			(Offset 0x2220) */
+
+#define BIT_SHIFT_CH8_AVAL_PG 16
+#define BIT_MASK_CH8_AVAL_PG 0xfff
+#define BIT_CH8_AVAL_PG(x)                                                     \
+	(((x) & BIT_MASK_CH8_AVAL_PG) << BIT_SHIFT_CH8_AVAL_PG)
+#define BITS_CH8_AVAL_PG (BIT_MASK_CH8_AVAL_PG << BIT_SHIFT_CH8_AVAL_PG)
+#define BIT_CLEAR_CH8_AVAL_PG(x) ((x) & (~BITS_CH8_AVAL_PG))
+#define BIT_GET_CH8_AVAL_PG(x)                                                 \
+	(((x) >> BIT_SHIFT_CH8_AVAL_PG) & BIT_MASK_CH8_AVAL_PG)
+#define BIT_SET_CH8_AVAL_PG(x, v)                                              \
+	(BIT_CLEAR_CH8_AVAL_PG(x) | BIT_CH8_AVAL_PG(v))
+
+#define BIT_SHIFT_CH8_RSVD_PG 0
+#define BIT_MASK_CH8_RSVD_PG 0xfff
+#define BIT_CH8_RSVD_PG(x)                                                     \
+	(((x) & BIT_MASK_CH8_RSVD_PG) << BIT_SHIFT_CH8_RSVD_PG)
+#define BITS_CH8_RSVD_PG (BIT_MASK_CH8_RSVD_PG << BIT_SHIFT_CH8_RSVD_PG)
+#define BIT_CLEAR_CH8_RSVD_PG(x) ((x) & (~BITS_CH8_RSVD_PG))
+#define BIT_GET_CH8_RSVD_PG(x)                                                 \
+	(((x) >> BIT_SHIFT_CH8_RSVD_PG) & BIT_MASK_CH8_RSVD_PG)
+#define BIT_SET_CH8_RSVD_PG(x, v)                                              \
+	(BIT_CLEAR_CH8_RSVD_PG(x) | BIT_CH8_RSVD_PG(v))
+
+/* 2 REG_DMA_RQPN_INFO_9			(Offset 0x2224) */
+
+#define BIT_SHIFT_CH9_AVAL_PG 16
+#define BIT_MASK_CH9_AVAL_PG 0xfff
+#define BIT_CH9_AVAL_PG(x)                                                     \
+	(((x) & BIT_MASK_CH9_AVAL_PG) << BIT_SHIFT_CH9_AVAL_PG)
+#define BITS_CH9_AVAL_PG (BIT_MASK_CH9_AVAL_PG << BIT_SHIFT_CH9_AVAL_PG)
+#define BIT_CLEAR_CH9_AVAL_PG(x) ((x) & (~BITS_CH9_AVAL_PG))
+#define BIT_GET_CH9_AVAL_PG(x)                                                 \
+	(((x) >> BIT_SHIFT_CH9_AVAL_PG) & BIT_MASK_CH9_AVAL_PG)
+#define BIT_SET_CH9_AVAL_PG(x, v)                                              \
+	(BIT_CLEAR_CH9_AVAL_PG(x) | BIT_CH9_AVAL_PG(v))
+
+#define BIT_SHIFT_CH9_RSVD_PG 0
+#define BIT_MASK_CH9_RSVD_PG 0xfff
+#define BIT_CH9_RSVD_PG(x)                                                     \
+	(((x) & BIT_MASK_CH9_RSVD_PG) << BIT_SHIFT_CH9_RSVD_PG)
+#define BITS_CH9_RSVD_PG (BIT_MASK_CH9_RSVD_PG << BIT_SHIFT_CH9_RSVD_PG)
+#define BIT_CLEAR_CH9_RSVD_PG(x) ((x) & (~BITS_CH9_RSVD_PG))
+#define BIT_GET_CH9_RSVD_PG(x)                                                 \
+	(((x) >> BIT_SHIFT_CH9_RSVD_PG) & BIT_MASK_CH9_RSVD_PG)
+#define BIT_SET_CH9_RSVD_PG(x, v)                                              \
+	(BIT_CLEAR_CH9_RSVD_PG(x) | BIT_CH9_RSVD_PG(v))
+
+/* 2 REG_DMA_RQPN_INFO_10			(Offset 0x2228) */
+
+#define BIT_SHIFT_CH10_AVAL_PG 16
+#define BIT_MASK_CH10_AVAL_PG 0xfff
+#define BIT_CH10_AVAL_PG(x)                                                    \
+	(((x) & BIT_MASK_CH10_AVAL_PG) << BIT_SHIFT_CH10_AVAL_PG)
+#define BITS_CH10_AVAL_PG (BIT_MASK_CH10_AVAL_PG << BIT_SHIFT_CH10_AVAL_PG)
+#define BIT_CLEAR_CH10_AVAL_PG(x) ((x) & (~BITS_CH10_AVAL_PG))
+#define BIT_GET_CH10_AVAL_PG(x)                                                \
+	(((x) >> BIT_SHIFT_CH10_AVAL_PG) & BIT_MASK_CH10_AVAL_PG)
+#define BIT_SET_CH10_AVAL_PG(x, v)                                             \
+	(BIT_CLEAR_CH10_AVAL_PG(x) | BIT_CH10_AVAL_PG(v))
+
+#define BIT_SHIFT_CH10_RSVD_PG 0
+#define BIT_MASK_CH10_RSVD_PG 0xfff
+#define BIT_CH10_RSVD_PG(x)                                                    \
+	(((x) & BIT_MASK_CH10_RSVD_PG) << BIT_SHIFT_CH10_RSVD_PG)
+#define BITS_CH10_RSVD_PG (BIT_MASK_CH10_RSVD_PG << BIT_SHIFT_CH10_RSVD_PG)
+#define BIT_CLEAR_CH10_RSVD_PG(x) ((x) & (~BITS_CH10_RSVD_PG))
+#define BIT_GET_CH10_RSVD_PG(x)                                                \
+	(((x) >> BIT_SHIFT_CH10_RSVD_PG) & BIT_MASK_CH10_RSVD_PG)
+#define BIT_SET_CH10_RSVD_PG(x, v)                                             \
+	(BIT_CLEAR_CH10_RSVD_PG(x) | BIT_CH10_RSVD_PG(v))
+
+/* 2 REG_DMA_RQPN_INFO_11			(Offset 0x222C) */
+
+#define BIT_SHIFT_CH11_AVAL_PG 16
+#define BIT_MASK_CH11_AVAL_PG 0xfff
+#define BIT_CH11_AVAL_PG(x)                                                    \
+	(((x) & BIT_MASK_CH11_AVAL_PG) << BIT_SHIFT_CH11_AVAL_PG)
+#define BITS_CH11_AVAL_PG (BIT_MASK_CH11_AVAL_PG << BIT_SHIFT_CH11_AVAL_PG)
+#define BIT_CLEAR_CH11_AVAL_PG(x) ((x) & (~BITS_CH11_AVAL_PG))
+#define BIT_GET_CH11_AVAL_PG(x)                                                \
+	(((x) >> BIT_SHIFT_CH11_AVAL_PG) & BIT_MASK_CH11_AVAL_PG)
+#define BIT_SET_CH11_AVAL_PG(x, v)                                             \
+	(BIT_CLEAR_CH11_AVAL_PG(x) | BIT_CH11_AVAL_PG(v))
+
+#define BIT_SHIFT_CH11_RSVD_PG 0
+#define BIT_MASK_CH11_RSVD_PG 0xfff
+#define BIT_CH11_RSVD_PG(x)                                                    \
+	(((x) & BIT_MASK_CH11_RSVD_PG) << BIT_SHIFT_CH11_RSVD_PG)
+#define BITS_CH11_RSVD_PG (BIT_MASK_CH11_RSVD_PG << BIT_SHIFT_CH11_RSVD_PG)
+#define BIT_CLEAR_CH11_RSVD_PG(x) ((x) & (~BITS_CH11_RSVD_PG))
+#define BIT_GET_CH11_RSVD_PG(x)                                                \
+	(((x) >> BIT_SHIFT_CH11_RSVD_PG) & BIT_MASK_CH11_RSVD_PG)
+#define BIT_SET_CH11_RSVD_PG(x, v)                                             \
+	(BIT_CLEAR_CH11_RSVD_PG(x) | BIT_CH11_RSVD_PG(v))
+
+/* 2 REG_DMA_RQPN_INFO_12			(Offset 0x2230) */
+
+#define BIT_SHIFT_CH12_AVAL_PG 16
+#define BIT_MASK_CH12_AVAL_PG 0xfff
+#define BIT_CH12_AVAL_PG(x)                                                    \
+	(((x) & BIT_MASK_CH12_AVAL_PG) << BIT_SHIFT_CH12_AVAL_PG)
+#define BITS_CH12_AVAL_PG (BIT_MASK_CH12_AVAL_PG << BIT_SHIFT_CH12_AVAL_PG)
+#define BIT_CLEAR_CH12_AVAL_PG(x) ((x) & (~BITS_CH12_AVAL_PG))
+#define BIT_GET_CH12_AVAL_PG(x)                                                \
+	(((x) >> BIT_SHIFT_CH12_AVAL_PG) & BIT_MASK_CH12_AVAL_PG)
+#define BIT_SET_CH12_AVAL_PG(x, v)                                             \
+	(BIT_CLEAR_CH12_AVAL_PG(x) | BIT_CH12_AVAL_PG(v))
+
+#define BIT_SHIFT_CH12_RSVD_PG 0
+#define BIT_MASK_CH12_RSVD_PG 0xfff
+#define BIT_CH12_RSVD_PG(x)                                                    \
+	(((x) & BIT_MASK_CH12_RSVD_PG) << BIT_SHIFT_CH12_RSVD_PG)
+#define BITS_CH12_RSVD_PG (BIT_MASK_CH12_RSVD_PG << BIT_SHIFT_CH12_RSVD_PG)
+#define BIT_CLEAR_CH12_RSVD_PG(x) ((x) & (~BITS_CH12_RSVD_PG))
+#define BIT_GET_CH12_RSVD_PG(x)                                                \
+	(((x) >> BIT_SHIFT_CH12_RSVD_PG) & BIT_MASK_CH12_RSVD_PG)
+#define BIT_SET_CH12_RSVD_PG(x, v)                                             \
+	(BIT_CLEAR_CH12_RSVD_PG(x) | BIT_CH12_RSVD_PG(v))
+
+/* 2 REG_DMA_RQPN_INFO_13			(Offset 0x2234) */
+
+#define BIT_SHIFT_CH13_AVAL_PG 16
+#define BIT_MASK_CH13_AVAL_PG 0xfff
+#define BIT_CH13_AVAL_PG(x)                                                    \
+	(((x) & BIT_MASK_CH13_AVAL_PG) << BIT_SHIFT_CH13_AVAL_PG)
+#define BITS_CH13_AVAL_PG (BIT_MASK_CH13_AVAL_PG << BIT_SHIFT_CH13_AVAL_PG)
+#define BIT_CLEAR_CH13_AVAL_PG(x) ((x) & (~BITS_CH13_AVAL_PG))
+#define BIT_GET_CH13_AVAL_PG(x)                                                \
+	(((x) >> BIT_SHIFT_CH13_AVAL_PG) & BIT_MASK_CH13_AVAL_PG)
+#define BIT_SET_CH13_AVAL_PG(x, v)                                             \
+	(BIT_CLEAR_CH13_AVAL_PG(x) | BIT_CH13_AVAL_PG(v))
+
+#define BIT_SHIFT_CH13_RSVD_PG 0
+#define BIT_MASK_CH13_RSVD_PG 0xfff
+#define BIT_CH13_RSVD_PG(x)                                                    \
+	(((x) & BIT_MASK_CH13_RSVD_PG) << BIT_SHIFT_CH13_RSVD_PG)
+#define BITS_CH13_RSVD_PG (BIT_MASK_CH13_RSVD_PG << BIT_SHIFT_CH13_RSVD_PG)
+#define BIT_CLEAR_CH13_RSVD_PG(x) ((x) & (~BITS_CH13_RSVD_PG))
+#define BIT_GET_CH13_RSVD_PG(x)                                                \
+	(((x) >> BIT_SHIFT_CH13_RSVD_PG) & BIT_MASK_CH13_RSVD_PG)
+#define BIT_SET_CH13_RSVD_PG(x, v)                                             \
+	(BIT_CLEAR_CH13_RSVD_PG(x) | BIT_CH13_RSVD_PG(v))
+
+/* 2 REG_DMA_RQPN_INFO_14			(Offset 0x2238) */
+
+#define BIT_SHIFT_CH14_AVAL_PG 16
+#define BIT_MASK_CH14_AVAL_PG 0xfff
+#define BIT_CH14_AVAL_PG(x)                                                    \
+	(((x) & BIT_MASK_CH14_AVAL_PG) << BIT_SHIFT_CH14_AVAL_PG)
+#define BITS_CH14_AVAL_PG (BIT_MASK_CH14_AVAL_PG << BIT_SHIFT_CH14_AVAL_PG)
+#define BIT_CLEAR_CH14_AVAL_PG(x) ((x) & (~BITS_CH14_AVAL_PG))
+#define BIT_GET_CH14_AVAL_PG(x)                                                \
+	(((x) >> BIT_SHIFT_CH14_AVAL_PG) & BIT_MASK_CH14_AVAL_PG)
+#define BIT_SET_CH14_AVAL_PG(x, v)                                             \
+	(BIT_CLEAR_CH14_AVAL_PG(x) | BIT_CH14_AVAL_PG(v))
+
+#define BIT_SHIFT_CH14_RSVD_PG 0
+#define BIT_MASK_CH14_RSVD_PG 0xfff
+#define BIT_CH14_RSVD_PG(x)                                                    \
+	(((x) & BIT_MASK_CH14_RSVD_PG) << BIT_SHIFT_CH14_RSVD_PG)
+#define BITS_CH14_RSVD_PG (BIT_MASK_CH14_RSVD_PG << BIT_SHIFT_CH14_RSVD_PG)
+#define BIT_CLEAR_CH14_RSVD_PG(x) ((x) & (~BITS_CH14_RSVD_PG))
+#define BIT_GET_CH14_RSVD_PG(x)                                                \
+	(((x) >> BIT_SHIFT_CH14_RSVD_PG) & BIT_MASK_CH14_RSVD_PG)
+#define BIT_SET_CH14_RSVD_PG(x, v)                                             \
+	(BIT_CLEAR_CH14_RSVD_PG(x) | BIT_CH14_RSVD_PG(v))
+
+/* 2 REG_DMA_RQPN_INFO_15			(Offset 0x223C) */
+
+#define BIT_SHIFT_CH15_AVAL_PG 16
+#define BIT_MASK_CH15_AVAL_PG 0xfff
+#define BIT_CH15_AVAL_PG(x)                                                    \
+	(((x) & BIT_MASK_CH15_AVAL_PG) << BIT_SHIFT_CH15_AVAL_PG)
+#define BITS_CH15_AVAL_PG (BIT_MASK_CH15_AVAL_PG << BIT_SHIFT_CH15_AVAL_PG)
+#define BIT_CLEAR_CH15_AVAL_PG(x) ((x) & (~BITS_CH15_AVAL_PG))
+#define BIT_GET_CH15_AVAL_PG(x)                                                \
+	(((x) >> BIT_SHIFT_CH15_AVAL_PG) & BIT_MASK_CH15_AVAL_PG)
+#define BIT_SET_CH15_AVAL_PG(x, v)                                             \
+	(BIT_CLEAR_CH15_AVAL_PG(x) | BIT_CH15_AVAL_PG(v))
+
+#define BIT_SHIFT_CH15_RSVD_PG 0
+#define BIT_MASK_CH15_RSVD_PG 0xfff
+#define BIT_CH15_RSVD_PG(x)                                                    \
+	(((x) & BIT_MASK_CH15_RSVD_PG) << BIT_SHIFT_CH15_RSVD_PG)
+#define BITS_CH15_RSVD_PG (BIT_MASK_CH15_RSVD_PG << BIT_SHIFT_CH15_RSVD_PG)
+#define BIT_CLEAR_CH15_RSVD_PG(x) ((x) & (~BITS_CH15_RSVD_PG))
+#define BIT_GET_CH15_RSVD_PG(x)                                                \
+	(((x) >> BIT_SHIFT_CH15_RSVD_PG) & BIT_MASK_CH15_RSVD_PG)
+#define BIT_SET_CH15_RSVD_PG(x, v)                                             \
+	(BIT_CLEAR_CH15_RSVD_PG(x) | BIT_CH15_RSVD_PG(v))
+
+/* 2 REG_DMA_RQPN_INFO_16			(Offset 0x2240) */
+
+#define BIT_SHIFT_CH16_AVAL_PG 16
+#define BIT_MASK_CH16_AVAL_PG 0xfff
+#define BIT_CH16_AVAL_PG(x)                                                    \
+	(((x) & BIT_MASK_CH16_AVAL_PG) << BIT_SHIFT_CH16_AVAL_PG)
+#define BITS_CH16_AVAL_PG (BIT_MASK_CH16_AVAL_PG << BIT_SHIFT_CH16_AVAL_PG)
+#define BIT_CLEAR_CH16_AVAL_PG(x) ((x) & (~BITS_CH16_AVAL_PG))
+#define BIT_GET_CH16_AVAL_PG(x)                                                \
+	(((x) >> BIT_SHIFT_CH16_AVAL_PG) & BIT_MASK_CH16_AVAL_PG)
+#define BIT_SET_CH16_AVAL_PG(x, v)                                             \
+	(BIT_CLEAR_CH16_AVAL_PG(x) | BIT_CH16_AVAL_PG(v))
+
+#define BIT_SHIFT_CH16_RSVD_PG 0
+#define BIT_MASK_CH16_RSVD_PG 0xfff
+#define BIT_CH16_RSVD_PG(x)                                                    \
+	(((x) & BIT_MASK_CH16_RSVD_PG) << BIT_SHIFT_CH16_RSVD_PG)
+#define BITS_CH16_RSVD_PG (BIT_MASK_CH16_RSVD_PG << BIT_SHIFT_CH16_RSVD_PG)
+#define BIT_CLEAR_CH16_RSVD_PG(x) ((x) & (~BITS_CH16_RSVD_PG))
+#define BIT_GET_CH16_RSVD_PG(x)                                                \
+	(((x) >> BIT_SHIFT_CH16_RSVD_PG) & BIT_MASK_CH16_RSVD_PG)
+#define BIT_SET_CH16_RSVD_PG(x, v)                                             \
+	(BIT_CLEAR_CH16_RSVD_PG(x) | BIT_CH16_RSVD_PG(v))
+
+/* 2 REG_HWAMSDU_CTL1			(Offset 0x2250) */
+
+#define BIT_SHIFT_HWAMSDU_PKTNUM 8
+#define BIT_MASK_HWAMSDU_PKTNUM 0x3f
+#define BIT_HWAMSDU_PKTNUM(x)                                                  \
+	(((x) & BIT_MASK_HWAMSDU_PKTNUM) << BIT_SHIFT_HWAMSDU_PKTNUM)
+#define BITS_HWAMSDU_PKTNUM                                                    \
+	(BIT_MASK_HWAMSDU_PKTNUM << BIT_SHIFT_HWAMSDU_PKTNUM)
+#define BIT_CLEAR_HWAMSDU_PKTNUM(x) ((x) & (~BITS_HWAMSDU_PKTNUM))
+#define BIT_GET_HWAMSDU_PKTNUM(x)                                              \
+	(((x) >> BIT_SHIFT_HWAMSDU_PKTNUM) & BIT_MASK_HWAMSDU_PKTNUM)
+#define BIT_SET_HWAMSDU_PKTNUM(x, v)                                           \
+	(BIT_CLEAR_HWAMSDU_PKTNUM(x) | BIT_HWAMSDU_PKTNUM(v))
+
+#define BIT_HWAMSDU_BUSY BIT(7)
+#define BIT_SINGLE_AMSDU BIT(2)
+#define BIT_HWAMSDU_PADDING_MODE BIT(1)
+#define BIT_HWAMSDU_EN BIT(0)
+
+/* 2 REG_HWAMSDU_CTL2			(Offset 0x2254) */
+
+#define BIT_SHIFT_HWAMSDU_AMSDU_TIMEOUT 16
+#define BIT_MASK_HWAMSDU_AMSDU_TIMEOUT 0xffff
+#define BIT_HWAMSDU_AMSDU_TIMEOUT(x)                                           \
+	(((x) & BIT_MASK_HWAMSDU_AMSDU_TIMEOUT)                                \
+	 << BIT_SHIFT_HWAMSDU_AMSDU_TIMEOUT)
+#define BITS_HWAMSDU_AMSDU_TIMEOUT                                             \
+	(BIT_MASK_HWAMSDU_AMSDU_TIMEOUT << BIT_SHIFT_HWAMSDU_AMSDU_TIMEOUT)
+#define BIT_CLEAR_HWAMSDU_AMSDU_TIMEOUT(x) ((x) & (~BITS_HWAMSDU_AMSDU_TIMEOUT))
+#define BIT_GET_HWAMSDU_AMSDU_TIMEOUT(x)                                       \
+	(((x) >> BIT_SHIFT_HWAMSDU_AMSDU_TIMEOUT) &                            \
+	 BIT_MASK_HWAMSDU_AMSDU_TIMEOUT)
+#define BIT_SET_HWAMSDU_AMSDU_TIMEOUT(x, v)                                    \
+	(BIT_CLEAR_HWAMSDU_AMSDU_TIMEOUT(x) | BIT_HWAMSDU_AMSDU_TIMEOUT(v))
+
+#define BIT_SHIFT_HWAMSDU_MSDU_TIMEOUT 0
+#define BIT_MASK_HWAMSDU_MSDU_TIMEOUT 0xffff
+#define BIT_HWAMSDU_MSDU_TIMEOUT(x)                                            \
+	(((x) & BIT_MASK_HWAMSDU_MSDU_TIMEOUT)                                 \
+	 << BIT_SHIFT_HWAMSDU_MSDU_TIMEOUT)
+#define BITS_HWAMSDU_MSDU_TIMEOUT                                              \
+	(BIT_MASK_HWAMSDU_MSDU_TIMEOUT << BIT_SHIFT_HWAMSDU_MSDU_TIMEOUT)
+#define BIT_CLEAR_HWAMSDU_MSDU_TIMEOUT(x) ((x) & (~BITS_HWAMSDU_MSDU_TIMEOUT))
+#define BIT_GET_HWAMSDU_MSDU_TIMEOUT(x)                                        \
+	(((x) >> BIT_SHIFT_HWAMSDU_MSDU_TIMEOUT) &                             \
+	 BIT_MASK_HWAMSDU_MSDU_TIMEOUT)
+#define BIT_SET_HWAMSDU_MSDU_TIMEOUT(x, v)                                     \
+	(BIT_CLEAR_HWAMSDU_MSDU_TIMEOUT(x) | BIT_HWAMSDU_MSDU_TIMEOUT(v))
+
+/* 2 REG_HI8Q_TXBD_DESA_L			(Offset 0x2300) */
+
+#define BIT_SHIFT_HI8Q_TXBD_DESA_L 0
+#define BIT_MASK_HI8Q_TXBD_DESA_L 0xffffffffL
+#define BIT_HI8Q_TXBD_DESA_L(x)                                                \
+	(((x) & BIT_MASK_HI8Q_TXBD_DESA_L) << BIT_SHIFT_HI8Q_TXBD_DESA_L)
+#define BITS_HI8Q_TXBD_DESA_L                                                  \
+	(BIT_MASK_HI8Q_TXBD_DESA_L << BIT_SHIFT_HI8Q_TXBD_DESA_L)
+#define BIT_CLEAR_HI8Q_TXBD_DESA_L(x) ((x) & (~BITS_HI8Q_TXBD_DESA_L))
+#define BIT_GET_HI8Q_TXBD_DESA_L(x)                                            \
+	(((x) >> BIT_SHIFT_HI8Q_TXBD_DESA_L) & BIT_MASK_HI8Q_TXBD_DESA_L)
+#define BIT_SET_HI8Q_TXBD_DESA_L(x, v)                                         \
+	(BIT_CLEAR_HI8Q_TXBD_DESA_L(x) | BIT_HI8Q_TXBD_DESA_L(v))
+
+/* 2 REG_HI8Q_TXBD_DESA_H			(Offset 0x2304) */
+
+#define BIT_SHIFT_HI8Q_TXBD_DESA_H 0
+#define BIT_MASK_HI8Q_TXBD_DESA_H 0xffffffffL
+#define BIT_HI8Q_TXBD_DESA_H(x)                                                \
+	(((x) & BIT_MASK_HI8Q_TXBD_DESA_H) << BIT_SHIFT_HI8Q_TXBD_DESA_H)
+#define BITS_HI8Q_TXBD_DESA_H                                                  \
+	(BIT_MASK_HI8Q_TXBD_DESA_H << BIT_SHIFT_HI8Q_TXBD_DESA_H)
+#define BIT_CLEAR_HI8Q_TXBD_DESA_H(x) ((x) & (~BITS_HI8Q_TXBD_DESA_H))
+#define BIT_GET_HI8Q_TXBD_DESA_H(x)                                            \
+	(((x) >> BIT_SHIFT_HI8Q_TXBD_DESA_H) & BIT_MASK_HI8Q_TXBD_DESA_H)
+#define BIT_SET_HI8Q_TXBD_DESA_H(x, v)                                         \
+	(BIT_CLEAR_HI8Q_TXBD_DESA_H(x) | BIT_HI8Q_TXBD_DESA_H(v))
+
+/* 2 REG_HI9Q_TXBD_DESA_L			(Offset 0x2308) */
+
+#define BIT_SHIFT_HI9Q_TXBD_DESA_L 0
+#define BIT_MASK_HI9Q_TXBD_DESA_L 0xffffffffL
+#define BIT_HI9Q_TXBD_DESA_L(x)                                                \
+	(((x) & BIT_MASK_HI9Q_TXBD_DESA_L) << BIT_SHIFT_HI9Q_TXBD_DESA_L)
+#define BITS_HI9Q_TXBD_DESA_L                                                  \
+	(BIT_MASK_HI9Q_TXBD_DESA_L << BIT_SHIFT_HI9Q_TXBD_DESA_L)
+#define BIT_CLEAR_HI9Q_TXBD_DESA_L(x) ((x) & (~BITS_HI9Q_TXBD_DESA_L))
+#define BIT_GET_HI9Q_TXBD_DESA_L(x)                                            \
+	(((x) >> BIT_SHIFT_HI9Q_TXBD_DESA_L) & BIT_MASK_HI9Q_TXBD_DESA_L)
+#define BIT_SET_HI9Q_TXBD_DESA_L(x, v)                                         \
+	(BIT_CLEAR_HI9Q_TXBD_DESA_L(x) | BIT_HI9Q_TXBD_DESA_L(v))
+
+/* 2 REG_HI9Q_TXBD_DESA_H			(Offset 0x230C) */
+
+#define BIT_SHIFT_HI9Q_TXBD_DESA_H 0
+#define BIT_MASK_HI9Q_TXBD_DESA_H 0xffffffffL
+#define BIT_HI9Q_TXBD_DESA_H(x)                                                \
+	(((x) & BIT_MASK_HI9Q_TXBD_DESA_H) << BIT_SHIFT_HI9Q_TXBD_DESA_H)
+#define BITS_HI9Q_TXBD_DESA_H                                                  \
+	(BIT_MASK_HI9Q_TXBD_DESA_H << BIT_SHIFT_HI9Q_TXBD_DESA_H)
+#define BIT_CLEAR_HI9Q_TXBD_DESA_H(x) ((x) & (~BITS_HI9Q_TXBD_DESA_H))
+#define BIT_GET_HI9Q_TXBD_DESA_H(x)                                            \
+	(((x) >> BIT_SHIFT_HI9Q_TXBD_DESA_H) & BIT_MASK_HI9Q_TXBD_DESA_H)
+#define BIT_SET_HI9Q_TXBD_DESA_H(x, v)                                         \
+	(BIT_CLEAR_HI9Q_TXBD_DESA_H(x) | BIT_HI9Q_TXBD_DESA_H(v))
+
+/* 2 REG_HI10Q_TXBD_DESA_L			(Offset 0x2310) */
+
+#define BIT_SHIFT_HI10Q_TXBD_DESA_L 0
+#define BIT_MASK_HI10Q_TXBD_DESA_L 0xffffffffL
+#define BIT_HI10Q_TXBD_DESA_L(x)                                               \
+	(((x) & BIT_MASK_HI10Q_TXBD_DESA_L) << BIT_SHIFT_HI10Q_TXBD_DESA_L)
+#define BITS_HI10Q_TXBD_DESA_L                                                 \
+	(BIT_MASK_HI10Q_TXBD_DESA_L << BIT_SHIFT_HI10Q_TXBD_DESA_L)
+#define BIT_CLEAR_HI10Q_TXBD_DESA_L(x) ((x) & (~BITS_HI10Q_TXBD_DESA_L))
+#define BIT_GET_HI10Q_TXBD_DESA_L(x)                                           \
+	(((x) >> BIT_SHIFT_HI10Q_TXBD_DESA_L) & BIT_MASK_HI10Q_TXBD_DESA_L)
+#define BIT_SET_HI10Q_TXBD_DESA_L(x, v)                                        \
+	(BIT_CLEAR_HI10Q_TXBD_DESA_L(x) | BIT_HI10Q_TXBD_DESA_L(v))
+
+/* 2 REG_HI10Q_TXBD_DESA_H			(Offset 0x2314) */
+
+#define BIT_SHIFT_HI10Q_TXBD_DESA_H 0
+#define BIT_MASK_HI10Q_TXBD_DESA_H 0xffffffffL
+#define BIT_HI10Q_TXBD_DESA_H(x)                                               \
+	(((x) & BIT_MASK_HI10Q_TXBD_DESA_H) << BIT_SHIFT_HI10Q_TXBD_DESA_H)
+#define BITS_HI10Q_TXBD_DESA_H                                                 \
+	(BIT_MASK_HI10Q_TXBD_DESA_H << BIT_SHIFT_HI10Q_TXBD_DESA_H)
+#define BIT_CLEAR_HI10Q_TXBD_DESA_H(x) ((x) & (~BITS_HI10Q_TXBD_DESA_H))
+#define BIT_GET_HI10Q_TXBD_DESA_H(x)                                           \
+	(((x) >> BIT_SHIFT_HI10Q_TXBD_DESA_H) & BIT_MASK_HI10Q_TXBD_DESA_H)
+#define BIT_SET_HI10Q_TXBD_DESA_H(x, v)                                        \
+	(BIT_CLEAR_HI10Q_TXBD_DESA_H(x) | BIT_HI10Q_TXBD_DESA_H(v))
+
+/* 2 REG_HI11Q_TXBD_DESA_L			(Offset 0x2318) */
+
+#define BIT_SHIFT_HI11Q_TXBD_DESA_L 0
+#define BIT_MASK_HI11Q_TXBD_DESA_L 0xffffffffL
+#define BIT_HI11Q_TXBD_DESA_L(x)                                               \
+	(((x) & BIT_MASK_HI11Q_TXBD_DESA_L) << BIT_SHIFT_HI11Q_TXBD_DESA_L)
+#define BITS_HI11Q_TXBD_DESA_L                                                 \
+	(BIT_MASK_HI11Q_TXBD_DESA_L << BIT_SHIFT_HI11Q_TXBD_DESA_L)
+#define BIT_CLEAR_HI11Q_TXBD_DESA_L(x) ((x) & (~BITS_HI11Q_TXBD_DESA_L))
+#define BIT_GET_HI11Q_TXBD_DESA_L(x)                                           \
+	(((x) >> BIT_SHIFT_HI11Q_TXBD_DESA_L) & BIT_MASK_HI11Q_TXBD_DESA_L)
+#define BIT_SET_HI11Q_TXBD_DESA_L(x, v)                                        \
+	(BIT_CLEAR_HI11Q_TXBD_DESA_L(x) | BIT_HI11Q_TXBD_DESA_L(v))
+
+/* 2 REG_HI11Q_TXBD_DESA_H			(Offset 0x231C) */
+
+#define BIT_SHIFT_HI11Q_TXBD_DESA_H 0
+#define BIT_MASK_HI11Q_TXBD_DESA_H 0xffffffffL
+#define BIT_HI11Q_TXBD_DESA_H(x)                                               \
+	(((x) & BIT_MASK_HI11Q_TXBD_DESA_H) << BIT_SHIFT_HI11Q_TXBD_DESA_H)
+#define BITS_HI11Q_TXBD_DESA_H                                                 \
+	(BIT_MASK_HI11Q_TXBD_DESA_H << BIT_SHIFT_HI11Q_TXBD_DESA_H)
+#define BIT_CLEAR_HI11Q_TXBD_DESA_H(x) ((x) & (~BITS_HI11Q_TXBD_DESA_H))
+#define BIT_GET_HI11Q_TXBD_DESA_H(x)                                           \
+	(((x) >> BIT_SHIFT_HI11Q_TXBD_DESA_H) & BIT_MASK_HI11Q_TXBD_DESA_H)
+#define BIT_SET_HI11Q_TXBD_DESA_H(x, v)                                        \
+	(BIT_CLEAR_HI11Q_TXBD_DESA_H(x) | BIT_HI11Q_TXBD_DESA_H(v))
+
+/* 2 REG_HI12Q_TXBD_DESA_L			(Offset 0x2320) */
+
+#define BIT_SHIFT_HI12Q_TXBD_DESA_L 0
+#define BIT_MASK_HI12Q_TXBD_DESA_L 0xffffffffL
+#define BIT_HI12Q_TXBD_DESA_L(x)                                               \
+	(((x) & BIT_MASK_HI12Q_TXBD_DESA_L) << BIT_SHIFT_HI12Q_TXBD_DESA_L)
+#define BITS_HI12Q_TXBD_DESA_L                                                 \
+	(BIT_MASK_HI12Q_TXBD_DESA_L << BIT_SHIFT_HI12Q_TXBD_DESA_L)
+#define BIT_CLEAR_HI12Q_TXBD_DESA_L(x) ((x) & (~BITS_HI12Q_TXBD_DESA_L))
+#define BIT_GET_HI12Q_TXBD_DESA_L(x)                                           \
+	(((x) >> BIT_SHIFT_HI12Q_TXBD_DESA_L) & BIT_MASK_HI12Q_TXBD_DESA_L)
+#define BIT_SET_HI12Q_TXBD_DESA_L(x, v)                                        \
+	(BIT_CLEAR_HI12Q_TXBD_DESA_L(x) | BIT_HI12Q_TXBD_DESA_L(v))
+
+/* 2 REG_HI12Q_TXBD_DESA_H			(Offset 0x2324) */
+
+#define BIT_SHIFT_HI12Q_TXBD_DESA_H 0
+#define BIT_MASK_HI12Q_TXBD_DESA_H 0xffffffffL
+#define BIT_HI12Q_TXBD_DESA_H(x)                                               \
+	(((x) & BIT_MASK_HI12Q_TXBD_DESA_H) << BIT_SHIFT_HI12Q_TXBD_DESA_H)
+#define BITS_HI12Q_TXBD_DESA_H                                                 \
+	(BIT_MASK_HI12Q_TXBD_DESA_H << BIT_SHIFT_HI12Q_TXBD_DESA_H)
+#define BIT_CLEAR_HI12Q_TXBD_DESA_H(x) ((x) & (~BITS_HI12Q_TXBD_DESA_H))
+#define BIT_GET_HI12Q_TXBD_DESA_H(x)                                           \
+	(((x) >> BIT_SHIFT_HI12Q_TXBD_DESA_H) & BIT_MASK_HI12Q_TXBD_DESA_H)
+#define BIT_SET_HI12Q_TXBD_DESA_H(x, v)                                        \
+	(BIT_CLEAR_HI12Q_TXBD_DESA_H(x) | BIT_HI12Q_TXBD_DESA_H(v))
+
+/* 2 REG_HI13Q_TXBD_DESA_L			(Offset 0x2328) */
+
+#define BIT_SHIFT_HI13Q_TXBD_DESA_L 0
+#define BIT_MASK_HI13Q_TXBD_DESA_L 0xffffffffL
+#define BIT_HI13Q_TXBD_DESA_L(x)                                               \
+	(((x) & BIT_MASK_HI13Q_TXBD_DESA_L) << BIT_SHIFT_HI13Q_TXBD_DESA_L)
+#define BITS_HI13Q_TXBD_DESA_L                                                 \
+	(BIT_MASK_HI13Q_TXBD_DESA_L << BIT_SHIFT_HI13Q_TXBD_DESA_L)
+#define BIT_CLEAR_HI13Q_TXBD_DESA_L(x) ((x) & (~BITS_HI13Q_TXBD_DESA_L))
+#define BIT_GET_HI13Q_TXBD_DESA_L(x)                                           \
+	(((x) >> BIT_SHIFT_HI13Q_TXBD_DESA_L) & BIT_MASK_HI13Q_TXBD_DESA_L)
+#define BIT_SET_HI13Q_TXBD_DESA_L(x, v)                                        \
+	(BIT_CLEAR_HI13Q_TXBD_DESA_L(x) | BIT_HI13Q_TXBD_DESA_L(v))
+
+/* 2 REG_HI13Q_TXBD_DESA_H			(Offset 0x232C) */
+
+#define BIT_SHIFT_HI13Q_TXBD_DESA_H 0
+#define BIT_MASK_HI13Q_TXBD_DESA_H 0xffffffffL
+#define BIT_HI13Q_TXBD_DESA_H(x)                                               \
+	(((x) & BIT_MASK_HI13Q_TXBD_DESA_H) << BIT_SHIFT_HI13Q_TXBD_DESA_H)
+#define BITS_HI13Q_TXBD_DESA_H                                                 \
+	(BIT_MASK_HI13Q_TXBD_DESA_H << BIT_SHIFT_HI13Q_TXBD_DESA_H)
+#define BIT_CLEAR_HI13Q_TXBD_DESA_H(x) ((x) & (~BITS_HI13Q_TXBD_DESA_H))
+#define BIT_GET_HI13Q_TXBD_DESA_H(x)                                           \
+	(((x) >> BIT_SHIFT_HI13Q_TXBD_DESA_H) & BIT_MASK_HI13Q_TXBD_DESA_H)
+#define BIT_SET_HI13Q_TXBD_DESA_H(x, v)                                        \
+	(BIT_CLEAR_HI13Q_TXBD_DESA_H(x) | BIT_HI13Q_TXBD_DESA_H(v))
+
+/* 2 REG_HI14Q_TXBD_DESA_L			(Offset 0x2330) */
+
+#define BIT_SHIFT_HI14Q_TXBD_DESA_L 0
+#define BIT_MASK_HI14Q_TXBD_DESA_L 0xffffffffL
+#define BIT_HI14Q_TXBD_DESA_L(x)                                               \
+	(((x) & BIT_MASK_HI14Q_TXBD_DESA_L) << BIT_SHIFT_HI14Q_TXBD_DESA_L)
+#define BITS_HI14Q_TXBD_DESA_L                                                 \
+	(BIT_MASK_HI14Q_TXBD_DESA_L << BIT_SHIFT_HI14Q_TXBD_DESA_L)
+#define BIT_CLEAR_HI14Q_TXBD_DESA_L(x) ((x) & (~BITS_HI14Q_TXBD_DESA_L))
+#define BIT_GET_HI14Q_TXBD_DESA_L(x)                                           \
+	(((x) >> BIT_SHIFT_HI14Q_TXBD_DESA_L) & BIT_MASK_HI14Q_TXBD_DESA_L)
+#define BIT_SET_HI14Q_TXBD_DESA_L(x, v)                                        \
+	(BIT_CLEAR_HI14Q_TXBD_DESA_L(x) | BIT_HI14Q_TXBD_DESA_L(v))
+
+/* 2 REG_HI14Q_TXBD_DESA_H			(Offset 0x2334) */
+
+#define BIT_SHIFT_HI14Q_TXBD_DESA_H 0
+#define BIT_MASK_HI14Q_TXBD_DESA_H 0xffffffffL
+#define BIT_HI14Q_TXBD_DESA_H(x)                                               \
+	(((x) & BIT_MASK_HI14Q_TXBD_DESA_H) << BIT_SHIFT_HI14Q_TXBD_DESA_H)
+#define BITS_HI14Q_TXBD_DESA_H                                                 \
+	(BIT_MASK_HI14Q_TXBD_DESA_H << BIT_SHIFT_HI14Q_TXBD_DESA_H)
+#define BIT_CLEAR_HI14Q_TXBD_DESA_H(x) ((x) & (~BITS_HI14Q_TXBD_DESA_H))
+#define BIT_GET_HI14Q_TXBD_DESA_H(x)                                           \
+	(((x) >> BIT_SHIFT_HI14Q_TXBD_DESA_H) & BIT_MASK_HI14Q_TXBD_DESA_H)
+#define BIT_SET_HI14Q_TXBD_DESA_H(x, v)                                        \
+	(BIT_CLEAR_HI14Q_TXBD_DESA_H(x) | BIT_HI14Q_TXBD_DESA_H(v))
+
+/* 2 REG_HI15Q_TXBD_DESA_L			(Offset 0x2338) */
+
+#define BIT_SHIFT_HI15Q_TXBD_DESA_L 0
+#define BIT_MASK_HI15Q_TXBD_DESA_L 0xffffffffL
+#define BIT_HI15Q_TXBD_DESA_L(x)                                               \
+	(((x) & BIT_MASK_HI15Q_TXBD_DESA_L) << BIT_SHIFT_HI15Q_TXBD_DESA_L)
+#define BITS_HI15Q_TXBD_DESA_L                                                 \
+	(BIT_MASK_HI15Q_TXBD_DESA_L << BIT_SHIFT_HI15Q_TXBD_DESA_L)
+#define BIT_CLEAR_HI15Q_TXBD_DESA_L(x) ((x) & (~BITS_HI15Q_TXBD_DESA_L))
+#define BIT_GET_HI15Q_TXBD_DESA_L(x)                                           \
+	(((x) >> BIT_SHIFT_HI15Q_TXBD_DESA_L) & BIT_MASK_HI15Q_TXBD_DESA_L)
+#define BIT_SET_HI15Q_TXBD_DESA_L(x, v)                                        \
+	(BIT_CLEAR_HI15Q_TXBD_DESA_L(x) | BIT_HI15Q_TXBD_DESA_L(v))
+
+/* 2 REG_HI15Q_TXBD_DESA_H			(Offset 0x233C) */
+
+#define BIT_SHIFT_HI15Q_TXBD_DESA_H 0
+#define BIT_MASK_HI15Q_TXBD_DESA_H 0xffffffffL
+#define BIT_HI15Q_TXBD_DESA_H(x)                                               \
+	(((x) & BIT_MASK_HI15Q_TXBD_DESA_H) << BIT_SHIFT_HI15Q_TXBD_DESA_H)
+#define BITS_HI15Q_TXBD_DESA_H                                                 \
+	(BIT_MASK_HI15Q_TXBD_DESA_H << BIT_SHIFT_HI15Q_TXBD_DESA_H)
+#define BIT_CLEAR_HI15Q_TXBD_DESA_H(x) ((x) & (~BITS_HI15Q_TXBD_DESA_H))
+#define BIT_GET_HI15Q_TXBD_DESA_H(x)                                           \
+	(((x) >> BIT_SHIFT_HI15Q_TXBD_DESA_H) & BIT_MASK_HI15Q_TXBD_DESA_H)
+#define BIT_SET_HI15Q_TXBD_DESA_H(x, v)                                        \
+	(BIT_CLEAR_HI15Q_TXBD_DESA_H(x) | BIT_HI15Q_TXBD_DESA_H(v))
+
+/* 2 REG_HI16Q_TXBD_DESA_L			(Offset 0x2340) */
+
+#define BIT_SHIFT_HI16Q_TXBD_DESA_L 0
+#define BIT_MASK_HI16Q_TXBD_DESA_L 0xffffffffL
+#define BIT_HI16Q_TXBD_DESA_L(x)                                               \
+	(((x) & BIT_MASK_HI16Q_TXBD_DESA_L) << BIT_SHIFT_HI16Q_TXBD_DESA_L)
+#define BITS_HI16Q_TXBD_DESA_L                                                 \
+	(BIT_MASK_HI16Q_TXBD_DESA_L << BIT_SHIFT_HI16Q_TXBD_DESA_L)
+#define BIT_CLEAR_HI16Q_TXBD_DESA_L(x) ((x) & (~BITS_HI16Q_TXBD_DESA_L))
+#define BIT_GET_HI16Q_TXBD_DESA_L(x)                                           \
+	(((x) >> BIT_SHIFT_HI16Q_TXBD_DESA_L) & BIT_MASK_HI16Q_TXBD_DESA_L)
+#define BIT_SET_HI16Q_TXBD_DESA_L(x, v)                                        \
+	(BIT_CLEAR_HI16Q_TXBD_DESA_L(x) | BIT_HI16Q_TXBD_DESA_L(v))
+
+/* 2 REG_HI16Q_TXBD_DESA_H			(Offset 0x2344) */
+
+#define BIT_SHIFT_HI16Q_TXBD_DESA_H 0
+#define BIT_MASK_HI16Q_TXBD_DESA_H 0xffffffffL
+#define BIT_HI16Q_TXBD_DESA_H(x)                                               \
+	(((x) & BIT_MASK_HI16Q_TXBD_DESA_H) << BIT_SHIFT_HI16Q_TXBD_DESA_H)
+#define BITS_HI16Q_TXBD_DESA_H                                                 \
+	(BIT_MASK_HI16Q_TXBD_DESA_H << BIT_SHIFT_HI16Q_TXBD_DESA_H)
+#define BIT_CLEAR_HI16Q_TXBD_DESA_H(x) ((x) & (~BITS_HI16Q_TXBD_DESA_H))
+#define BIT_GET_HI16Q_TXBD_DESA_H(x)                                           \
+	(((x) >> BIT_SHIFT_HI16Q_TXBD_DESA_H) & BIT_MASK_HI16Q_TXBD_DESA_H)
+#define BIT_SET_HI16Q_TXBD_DESA_H(x, v)                                        \
+	(BIT_CLEAR_HI16Q_TXBD_DESA_H(x) | BIT_HI16Q_TXBD_DESA_H(v))
+
+/* 2 REG_HI17Q_TXBD_DESA_L			(Offset 0x2348) */
+
+#define BIT_SHIFT_HI17Q_TXBD_DESA_L 0
+#define BIT_MASK_HI17Q_TXBD_DESA_L 0xffffffffL
+#define BIT_HI17Q_TXBD_DESA_L(x)                                               \
+	(((x) & BIT_MASK_HI17Q_TXBD_DESA_L) << BIT_SHIFT_HI17Q_TXBD_DESA_L)
+#define BITS_HI17Q_TXBD_DESA_L                                                 \
+	(BIT_MASK_HI17Q_TXBD_DESA_L << BIT_SHIFT_HI17Q_TXBD_DESA_L)
+#define BIT_CLEAR_HI17Q_TXBD_DESA_L(x) ((x) & (~BITS_HI17Q_TXBD_DESA_L))
+#define BIT_GET_HI17Q_TXBD_DESA_L(x)                                           \
+	(((x) >> BIT_SHIFT_HI17Q_TXBD_DESA_L) & BIT_MASK_HI17Q_TXBD_DESA_L)
+#define BIT_SET_HI17Q_TXBD_DESA_L(x, v)                                        \
+	(BIT_CLEAR_HI17Q_TXBD_DESA_L(x) | BIT_HI17Q_TXBD_DESA_L(v))
+
+/* 2 REG_HI17Q_TXBD_DESA_H			(Offset 0x234C) */
+
+#define BIT_SHIFT_HI17Q_TXBD_DESA_H 0
+#define BIT_MASK_HI17Q_TXBD_DESA_H 0xffffffffL
+#define BIT_HI17Q_TXBD_DESA_H(x)                                               \
+	(((x) & BIT_MASK_HI17Q_TXBD_DESA_H) << BIT_SHIFT_HI17Q_TXBD_DESA_H)
+#define BITS_HI17Q_TXBD_DESA_H                                                 \
+	(BIT_MASK_HI17Q_TXBD_DESA_H << BIT_SHIFT_HI17Q_TXBD_DESA_H)
+#define BIT_CLEAR_HI17Q_TXBD_DESA_H(x) ((x) & (~BITS_HI17Q_TXBD_DESA_H))
+#define BIT_GET_HI17Q_TXBD_DESA_H(x)                                           \
+	(((x) >> BIT_SHIFT_HI17Q_TXBD_DESA_H) & BIT_MASK_HI17Q_TXBD_DESA_H)
+#define BIT_SET_HI17Q_TXBD_DESA_H(x, v)                                        \
+	(BIT_CLEAR_HI17Q_TXBD_DESA_H(x) | BIT_HI17Q_TXBD_DESA_H(v))
+
+/* 2 REG_HI18Q_TXBD_DESA_L			(Offset 0x2350) */
+
+#define BIT_SHIFT_HI18Q_TXBD_DESA_L 0
+#define BIT_MASK_HI18Q_TXBD_DESA_L 0xffffffffL
+#define BIT_HI18Q_TXBD_DESA_L(x)                                               \
+	(((x) & BIT_MASK_HI18Q_TXBD_DESA_L) << BIT_SHIFT_HI18Q_TXBD_DESA_L)
+#define BITS_HI18Q_TXBD_DESA_L                                                 \
+	(BIT_MASK_HI18Q_TXBD_DESA_L << BIT_SHIFT_HI18Q_TXBD_DESA_L)
+#define BIT_CLEAR_HI18Q_TXBD_DESA_L(x) ((x) & (~BITS_HI18Q_TXBD_DESA_L))
+#define BIT_GET_HI18Q_TXBD_DESA_L(x)                                           \
+	(((x) >> BIT_SHIFT_HI18Q_TXBD_DESA_L) & BIT_MASK_HI18Q_TXBD_DESA_L)
+#define BIT_SET_HI18Q_TXBD_DESA_L(x, v)                                        \
+	(BIT_CLEAR_HI18Q_TXBD_DESA_L(x) | BIT_HI18Q_TXBD_DESA_L(v))
+
+/* 2 REG_HI18Q_TXBD_DESA_H			(Offset 0x2354) */
+
+#define BIT_SHIFT_HI18Q_TXBD_DESA_H 0
+#define BIT_MASK_HI18Q_TXBD_DESA_H 0xffffffffL
+#define BIT_HI18Q_TXBD_DESA_H(x)                                               \
+	(((x) & BIT_MASK_HI18Q_TXBD_DESA_H) << BIT_SHIFT_HI18Q_TXBD_DESA_H)
+#define BITS_HI18Q_TXBD_DESA_H                                                 \
+	(BIT_MASK_HI18Q_TXBD_DESA_H << BIT_SHIFT_HI18Q_TXBD_DESA_H)
+#define BIT_CLEAR_HI18Q_TXBD_DESA_H(x) ((x) & (~BITS_HI18Q_TXBD_DESA_H))
+#define BIT_GET_HI18Q_TXBD_DESA_H(x)                                           \
+	(((x) >> BIT_SHIFT_HI18Q_TXBD_DESA_H) & BIT_MASK_HI18Q_TXBD_DESA_H)
+#define BIT_SET_HI18Q_TXBD_DESA_H(x, v)                                        \
+	(BIT_CLEAR_HI18Q_TXBD_DESA_H(x) | BIT_HI18Q_TXBD_DESA_H(v))
+
+/* 2 REG_HI19Q_TXBD_DESA_L			(Offset 0x2358) */
+
+#define BIT_SHIFT_HI19Q_TXBD_DESA_L 0
+#define BIT_MASK_HI19Q_TXBD_DESA_L 0xffffffffL
+#define BIT_HI19Q_TXBD_DESA_L(x)                                               \
+	(((x) & BIT_MASK_HI19Q_TXBD_DESA_L) << BIT_SHIFT_HI19Q_TXBD_DESA_L)
+#define BITS_HI19Q_TXBD_DESA_L                                                 \
+	(BIT_MASK_HI19Q_TXBD_DESA_L << BIT_SHIFT_HI19Q_TXBD_DESA_L)
+#define BIT_CLEAR_HI19Q_TXBD_DESA_L(x) ((x) & (~BITS_HI19Q_TXBD_DESA_L))
+#define BIT_GET_HI19Q_TXBD_DESA_L(x)                                           \
+	(((x) >> BIT_SHIFT_HI19Q_TXBD_DESA_L) & BIT_MASK_HI19Q_TXBD_DESA_L)
+#define BIT_SET_HI19Q_TXBD_DESA_L(x, v)                                        \
+	(BIT_CLEAR_HI19Q_TXBD_DESA_L(x) | BIT_HI19Q_TXBD_DESA_L(v))
+
+/* 2 REG_HI19Q_TXBD_DESA_H			(Offset 0x235C) */
+
+#define BIT_CLR_P0HI19Q_HW_IDX BIT(25)
+#define BIT_CLR_P0HI18Q_HW_IDX BIT(24)
+#define BIT_CLR_P0HI17Q_HW_IDX BIT(23)
+#define BIT_CLR_P0HI16Q_HW_IDX BIT(22)
+#define BIT_CLR_P0HI19Q_HOST_IDX BIT(9)
+#define BIT_CLR_P0HI18Q_HOST_IDX BIT(8)
+#define BIT_CLR_P0HI17Q_HOST_IDX BIT(7)
+#define BIT_CLR_P0HI16Q_HOST_IDX BIT(6)
+
+#define BIT_SHIFT_HI19Q_TXBD_DESA_H 0
+#define BIT_MASK_HI19Q_TXBD_DESA_H 0xffffffffL
+#define BIT_HI19Q_TXBD_DESA_H(x)                                               \
+	(((x) & BIT_MASK_HI19Q_TXBD_DESA_H) << BIT_SHIFT_HI19Q_TXBD_DESA_H)
+#define BITS_HI19Q_TXBD_DESA_H                                                 \
+	(BIT_MASK_HI19Q_TXBD_DESA_H << BIT_SHIFT_HI19Q_TXBD_DESA_H)
+#define BIT_CLEAR_HI19Q_TXBD_DESA_H(x) ((x) & (~BITS_HI19Q_TXBD_DESA_H))
+#define BIT_GET_HI19Q_TXBD_DESA_H(x)                                           \
+	(((x) >> BIT_SHIFT_HI19Q_TXBD_DESA_H) & BIT_MASK_HI19Q_TXBD_DESA_H)
+#define BIT_SET_HI19Q_TXBD_DESA_H(x, v)                                        \
+	(BIT_CLEAR_HI19Q_TXBD_DESA_H(x) | BIT_HI19Q_TXBD_DESA_H(v))
+
+/* 2 REG_P0HI16Q_TXBD_IDX			(Offset 0x2370) */
+
+#define BIT_SHIFT_P0HI16Q_HW_IDX 16
+#define BIT_MASK_P0HI16Q_HW_IDX 0xfff
+#define BIT_P0HI16Q_HW_IDX(x)                                                  \
+	(((x) & BIT_MASK_P0HI16Q_HW_IDX) << BIT_SHIFT_P0HI16Q_HW_IDX)
+#define BITS_P0HI16Q_HW_IDX                                                    \
+	(BIT_MASK_P0HI16Q_HW_IDX << BIT_SHIFT_P0HI16Q_HW_IDX)
+#define BIT_CLEAR_P0HI16Q_HW_IDX(x) ((x) & (~BITS_P0HI16Q_HW_IDX))
+#define BIT_GET_P0HI16Q_HW_IDX(x)                                              \
+	(((x) >> BIT_SHIFT_P0HI16Q_HW_IDX) & BIT_MASK_P0HI16Q_HW_IDX)
+#define BIT_SET_P0HI16Q_HW_IDX(x, v)                                           \
+	(BIT_CLEAR_P0HI16Q_HW_IDX(x) | BIT_P0HI16Q_HW_IDX(v))
+
+#define BIT_SHIFT_P0HI16Q_HOST_IDX 0
+#define BIT_MASK_P0HI16Q_HOST_IDX 0xfff
+#define BIT_P0HI16Q_HOST_IDX(x)                                                \
+	(((x) & BIT_MASK_P0HI16Q_HOST_IDX) << BIT_SHIFT_P0HI16Q_HOST_IDX)
+#define BITS_P0HI16Q_HOST_IDX                                                  \
+	(BIT_MASK_P0HI16Q_HOST_IDX << BIT_SHIFT_P0HI16Q_HOST_IDX)
+#define BIT_CLEAR_P0HI16Q_HOST_IDX(x) ((x) & (~BITS_P0HI16Q_HOST_IDX))
+#define BIT_GET_P0HI16Q_HOST_IDX(x)                                            \
+	(((x) >> BIT_SHIFT_P0HI16Q_HOST_IDX) & BIT_MASK_P0HI16Q_HOST_IDX)
+#define BIT_SET_P0HI16Q_HOST_IDX(x, v)                                         \
+	(BIT_CLEAR_P0HI16Q_HOST_IDX(x) | BIT_P0HI16Q_HOST_IDX(v))
+
+/* 2 REG_P0HI17Q_TXBD_IDX			(Offset 0x2374) */
+
+#define BIT_SHIFT_P0HI17Q_HW_IDX 16
+#define BIT_MASK_P0HI17Q_HW_IDX 0xfff
+#define BIT_P0HI17Q_HW_IDX(x)                                                  \
+	(((x) & BIT_MASK_P0HI17Q_HW_IDX) << BIT_SHIFT_P0HI17Q_HW_IDX)
+#define BITS_P0HI17Q_HW_IDX                                                    \
+	(BIT_MASK_P0HI17Q_HW_IDX << BIT_SHIFT_P0HI17Q_HW_IDX)
+#define BIT_CLEAR_P0HI17Q_HW_IDX(x) ((x) & (~BITS_P0HI17Q_HW_IDX))
+#define BIT_GET_P0HI17Q_HW_IDX(x)                                              \
+	(((x) >> BIT_SHIFT_P0HI17Q_HW_IDX) & BIT_MASK_P0HI17Q_HW_IDX)
+#define BIT_SET_P0HI17Q_HW_IDX(x, v)                                           \
+	(BIT_CLEAR_P0HI17Q_HW_IDX(x) | BIT_P0HI17Q_HW_IDX(v))
+
+#define BIT_SHIFT_P0HI17Q_HOST_IDX 0
+#define BIT_MASK_P0HI17Q_HOST_IDX 0xfff
+#define BIT_P0HI17Q_HOST_IDX(x)                                                \
+	(((x) & BIT_MASK_P0HI17Q_HOST_IDX) << BIT_SHIFT_P0HI17Q_HOST_IDX)
+#define BITS_P0HI17Q_HOST_IDX                                                  \
+	(BIT_MASK_P0HI17Q_HOST_IDX << BIT_SHIFT_P0HI17Q_HOST_IDX)
+#define BIT_CLEAR_P0HI17Q_HOST_IDX(x) ((x) & (~BITS_P0HI17Q_HOST_IDX))
+#define BIT_GET_P0HI17Q_HOST_IDX(x)                                            \
+	(((x) >> BIT_SHIFT_P0HI17Q_HOST_IDX) & BIT_MASK_P0HI17Q_HOST_IDX)
+#define BIT_SET_P0HI17Q_HOST_IDX(x, v)                                         \
+	(BIT_CLEAR_P0HI17Q_HOST_IDX(x) | BIT_P0HI17Q_HOST_IDX(v))
+
+/* 2 REG_P0HI18Q_TXBD_IDX			(Offset 0x2378) */
+
+#define BIT_SHIFT_P0HI18Q_HW_IDX 16
+#define BIT_MASK_P0HI18Q_HW_IDX 0xfff
+#define BIT_P0HI18Q_HW_IDX(x)                                                  \
+	(((x) & BIT_MASK_P0HI18Q_HW_IDX) << BIT_SHIFT_P0HI18Q_HW_IDX)
+#define BITS_P0HI18Q_HW_IDX                                                    \
+	(BIT_MASK_P0HI18Q_HW_IDX << BIT_SHIFT_P0HI18Q_HW_IDX)
+#define BIT_CLEAR_P0HI18Q_HW_IDX(x) ((x) & (~BITS_P0HI18Q_HW_IDX))
+#define BIT_GET_P0HI18Q_HW_IDX(x)                                              \
+	(((x) >> BIT_SHIFT_P0HI18Q_HW_IDX) & BIT_MASK_P0HI18Q_HW_IDX)
+#define BIT_SET_P0HI18Q_HW_IDX(x, v)                                           \
+	(BIT_CLEAR_P0HI18Q_HW_IDX(x) | BIT_P0HI18Q_HW_IDX(v))
+
+#define BIT_SHIFT_P0HI18Q_HOST_IDX 0
+#define BIT_MASK_P0HI18Q_HOST_IDX 0xfff
+#define BIT_P0HI18Q_HOST_IDX(x)                                                \
+	(((x) & BIT_MASK_P0HI18Q_HOST_IDX) << BIT_SHIFT_P0HI18Q_HOST_IDX)
+#define BITS_P0HI18Q_HOST_IDX                                                  \
+	(BIT_MASK_P0HI18Q_HOST_IDX << BIT_SHIFT_P0HI18Q_HOST_IDX)
+#define BIT_CLEAR_P0HI18Q_HOST_IDX(x) ((x) & (~BITS_P0HI18Q_HOST_IDX))
+#define BIT_GET_P0HI18Q_HOST_IDX(x)                                            \
+	(((x) >> BIT_SHIFT_P0HI18Q_HOST_IDX) & BIT_MASK_P0HI18Q_HOST_IDX)
+#define BIT_SET_P0HI18Q_HOST_IDX(x, v)                                         \
+	(BIT_CLEAR_P0HI18Q_HOST_IDX(x) | BIT_P0HI18Q_HOST_IDX(v))
+
+/* 2 REG_P0HI19Q_TXBD_IDX			(Offset 0x237C) */
+
+#define BIT_SHIFT_P0HI19Q_HW_IDX 16
+#define BIT_MASK_P0HI19Q_HW_IDX 0xfff
+#define BIT_P0HI19Q_HW_IDX(x)                                                  \
+	(((x) & BIT_MASK_P0HI19Q_HW_IDX) << BIT_SHIFT_P0HI19Q_HW_IDX)
+#define BITS_P0HI19Q_HW_IDX                                                    \
+	(BIT_MASK_P0HI19Q_HW_IDX << BIT_SHIFT_P0HI19Q_HW_IDX)
+#define BIT_CLEAR_P0HI19Q_HW_IDX(x) ((x) & (~BITS_P0HI19Q_HW_IDX))
+#define BIT_GET_P0HI19Q_HW_IDX(x)                                              \
+	(((x) >> BIT_SHIFT_P0HI19Q_HW_IDX) & BIT_MASK_P0HI19Q_HW_IDX)
+#define BIT_SET_P0HI19Q_HW_IDX(x, v)                                           \
+	(BIT_CLEAR_P0HI19Q_HW_IDX(x) | BIT_P0HI19Q_HW_IDX(v))
+
+#define BIT_SHIFT_P0HI19Q_HOST_IDX 0
+#define BIT_MASK_P0HI19Q_HOST_IDX 0xfff
+#define BIT_P0HI19Q_HOST_IDX(x)                                                \
+	(((x) & BIT_MASK_P0HI19Q_HOST_IDX) << BIT_SHIFT_P0HI19Q_HOST_IDX)
+#define BITS_P0HI19Q_HOST_IDX                                                  \
+	(BIT_MASK_P0HI19Q_HOST_IDX << BIT_SHIFT_P0HI19Q_HOST_IDX)
+#define BIT_CLEAR_P0HI19Q_HOST_IDX(x) ((x) & (~BITS_P0HI19Q_HOST_IDX))
+#define BIT_GET_P0HI19Q_HOST_IDX(x)                                            \
+	(((x) >> BIT_SHIFT_P0HI19Q_HOST_IDX) & BIT_MASK_P0HI19Q_HOST_IDX)
+#define BIT_SET_P0HI19Q_HOST_IDX(x, v)                                         \
+	(BIT_CLEAR_P0HI19Q_HOST_IDX(x) | BIT_P0HI19Q_HOST_IDX(v))
+
+/* 2 REG_P0HI16Q_HI17Q_TXBD_NUM		(Offset 0x2380) */
+
+#define BIT_P0HI17Q_FLAG BIT(30)
+
+#define BIT_SHIFT_P0HI17Q_DESC_MODE 28
+#define BIT_MASK_P0HI17Q_DESC_MODE 0x3
+#define BIT_P0HI17Q_DESC_MODE(x)                                               \
+	(((x) & BIT_MASK_P0HI17Q_DESC_MODE) << BIT_SHIFT_P0HI17Q_DESC_MODE)
+#define BITS_P0HI17Q_DESC_MODE                                                 \
+	(BIT_MASK_P0HI17Q_DESC_MODE << BIT_SHIFT_P0HI17Q_DESC_MODE)
+#define BIT_CLEAR_P0HI17Q_DESC_MODE(x) ((x) & (~BITS_P0HI17Q_DESC_MODE))
+#define BIT_GET_P0HI17Q_DESC_MODE(x)                                           \
+	(((x) >> BIT_SHIFT_P0HI17Q_DESC_MODE) & BIT_MASK_P0HI17Q_DESC_MODE)
+#define BIT_SET_P0HI17Q_DESC_MODE(x, v)                                        \
+	(BIT_CLEAR_P0HI17Q_DESC_MODE(x) | BIT_P0HI17Q_DESC_MODE(v))
+
+#define BIT_SHIFT_P0HI17Q_DESC_NUM 16
+#define BIT_MASK_P0HI17Q_DESC_NUM 0xfff
+#define BIT_P0HI17Q_DESC_NUM(x)                                                \
+	(((x) & BIT_MASK_P0HI17Q_DESC_NUM) << BIT_SHIFT_P0HI17Q_DESC_NUM)
+#define BITS_P0HI17Q_DESC_NUM                                                  \
+	(BIT_MASK_P0HI17Q_DESC_NUM << BIT_SHIFT_P0HI17Q_DESC_NUM)
+#define BIT_CLEAR_P0HI17Q_DESC_NUM(x) ((x) & (~BITS_P0HI17Q_DESC_NUM))
+#define BIT_GET_P0HI17Q_DESC_NUM(x)                                            \
+	(((x) >> BIT_SHIFT_P0HI17Q_DESC_NUM) & BIT_MASK_P0HI17Q_DESC_NUM)
+#define BIT_SET_P0HI17Q_DESC_NUM(x, v)                                         \
+	(BIT_CLEAR_P0HI17Q_DESC_NUM(x) | BIT_P0HI17Q_DESC_NUM(v))
+
+#define BIT_P0HI16Q_FLAG BIT(14)
+
+#define BIT_SHIFT_P0HI16Q_DESC_MODE 12
+#define BIT_MASK_P0HI16Q_DESC_MODE 0x3
+#define BIT_P0HI16Q_DESC_MODE(x)                                               \
+	(((x) & BIT_MASK_P0HI16Q_DESC_MODE) << BIT_SHIFT_P0HI16Q_DESC_MODE)
+#define BITS_P0HI16Q_DESC_MODE                                                 \
+	(BIT_MASK_P0HI16Q_DESC_MODE << BIT_SHIFT_P0HI16Q_DESC_MODE)
+#define BIT_CLEAR_P0HI16Q_DESC_MODE(x) ((x) & (~BITS_P0HI16Q_DESC_MODE))
+#define BIT_GET_P0HI16Q_DESC_MODE(x)                                           \
+	(((x) >> BIT_SHIFT_P0HI16Q_DESC_MODE) & BIT_MASK_P0HI16Q_DESC_MODE)
+#define BIT_SET_P0HI16Q_DESC_MODE(x, v)                                        \
+	(BIT_CLEAR_P0HI16Q_DESC_MODE(x) | BIT_P0HI16Q_DESC_MODE(v))
+
+#define BIT_SHIFT_P0HI16Q_DESC_NUM 0
+#define BIT_MASK_P0HI16Q_DESC_NUM 0xfff
+#define BIT_P0HI16Q_DESC_NUM(x)                                                \
+	(((x) & BIT_MASK_P0HI16Q_DESC_NUM) << BIT_SHIFT_P0HI16Q_DESC_NUM)
+#define BITS_P0HI16Q_DESC_NUM                                                  \
+	(BIT_MASK_P0HI16Q_DESC_NUM << BIT_SHIFT_P0HI16Q_DESC_NUM)
+#define BIT_CLEAR_P0HI16Q_DESC_NUM(x) ((x) & (~BITS_P0HI16Q_DESC_NUM))
+#define BIT_GET_P0HI16Q_DESC_NUM(x)                                            \
+	(((x) >> BIT_SHIFT_P0HI16Q_DESC_NUM) & BIT_MASK_P0HI16Q_DESC_NUM)
+#define BIT_SET_P0HI16Q_DESC_NUM(x, v)                                         \
+	(BIT_CLEAR_P0HI16Q_DESC_NUM(x) | BIT_P0HI16Q_DESC_NUM(v))
+
+/* 2 REG_P0HI18Q_HI19Q_TXBD_NUM		(Offset 0x2384) */
+
+#define BIT_P0HI19Q_FLAG BIT(30)
+
+#define BIT_SHIFT_P0HI19Q_DESC_MODE 28
+#define BIT_MASK_P0HI19Q_DESC_MODE 0x3
+#define BIT_P0HI19Q_DESC_MODE(x)                                               \
+	(((x) & BIT_MASK_P0HI19Q_DESC_MODE) << BIT_SHIFT_P0HI19Q_DESC_MODE)
+#define BITS_P0HI19Q_DESC_MODE                                                 \
+	(BIT_MASK_P0HI19Q_DESC_MODE << BIT_SHIFT_P0HI19Q_DESC_MODE)
+#define BIT_CLEAR_P0HI19Q_DESC_MODE(x) ((x) & (~BITS_P0HI19Q_DESC_MODE))
+#define BIT_GET_P0HI19Q_DESC_MODE(x)                                           \
+	(((x) >> BIT_SHIFT_P0HI19Q_DESC_MODE) & BIT_MASK_P0HI19Q_DESC_MODE)
+#define BIT_SET_P0HI19Q_DESC_MODE(x, v)                                        \
+	(BIT_CLEAR_P0HI19Q_DESC_MODE(x) | BIT_P0HI19Q_DESC_MODE(v))
+
+#define BIT_SHIFT_P0HI19Q_DESC_NUM 16
+#define BIT_MASK_P0HI19Q_DESC_NUM 0xfff
+#define BIT_P0HI19Q_DESC_NUM(x)                                                \
+	(((x) & BIT_MASK_P0HI19Q_DESC_NUM) << BIT_SHIFT_P0HI19Q_DESC_NUM)
+#define BITS_P0HI19Q_DESC_NUM                                                  \
+	(BIT_MASK_P0HI19Q_DESC_NUM << BIT_SHIFT_P0HI19Q_DESC_NUM)
+#define BIT_CLEAR_P0HI19Q_DESC_NUM(x) ((x) & (~BITS_P0HI19Q_DESC_NUM))
+#define BIT_GET_P0HI19Q_DESC_NUM(x)                                            \
+	(((x) >> BIT_SHIFT_P0HI19Q_DESC_NUM) & BIT_MASK_P0HI19Q_DESC_NUM)
+#define BIT_SET_P0HI19Q_DESC_NUM(x, v)                                         \
+	(BIT_CLEAR_P0HI19Q_DESC_NUM(x) | BIT_P0HI19Q_DESC_NUM(v))
+
+#define BIT_P0HI18Q_FLAG BIT(14)
+
+#define BIT_SHIFT_P0HI18Q_DESC_MODE 12
+#define BIT_MASK_P0HI18Q_DESC_MODE 0x3
+#define BIT_P0HI18Q_DESC_MODE(x)                                               \
+	(((x) & BIT_MASK_P0HI18Q_DESC_MODE) << BIT_SHIFT_P0HI18Q_DESC_MODE)
+#define BITS_P0HI18Q_DESC_MODE                                                 \
+	(BIT_MASK_P0HI18Q_DESC_MODE << BIT_SHIFT_P0HI18Q_DESC_MODE)
+#define BIT_CLEAR_P0HI18Q_DESC_MODE(x) ((x) & (~BITS_P0HI18Q_DESC_MODE))
+#define BIT_GET_P0HI18Q_DESC_MODE(x)                                           \
+	(((x) >> BIT_SHIFT_P0HI18Q_DESC_MODE) & BIT_MASK_P0HI18Q_DESC_MODE)
+#define BIT_SET_P0HI18Q_DESC_MODE(x, v)                                        \
+	(BIT_CLEAR_P0HI18Q_DESC_MODE(x) | BIT_P0HI18Q_DESC_MODE(v))
+
+#define BIT_SHIFT_P0HI18Q_DESC_NUM 0
+#define BIT_MASK_P0HI18Q_DESC_NUM 0xfff
+#define BIT_P0HI18Q_DESC_NUM(x)                                                \
+	(((x) & BIT_MASK_P0HI18Q_DESC_NUM) << BIT_SHIFT_P0HI18Q_DESC_NUM)
+#define BITS_P0HI18Q_DESC_NUM                                                  \
+	(BIT_MASK_P0HI18Q_DESC_NUM << BIT_SHIFT_P0HI18Q_DESC_NUM)
+#define BIT_CLEAR_P0HI18Q_DESC_NUM(x) ((x) & (~BITS_P0HI18Q_DESC_NUM))
+#define BIT_GET_P0HI18Q_DESC_NUM(x)                                            \
+	(((x) >> BIT_SHIFT_P0HI18Q_DESC_NUM) & BIT_MASK_P0HI18Q_DESC_NUM)
+#define BIT_SET_P0HI18Q_DESC_NUM(x, v)                                         \
+	(BIT_CLEAR_P0HI18Q_DESC_NUM(x) | BIT_P0HI18Q_DESC_NUM(v))
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_PCIE_HISR1				(Offset 0x23BC) */
+
+#define BIT_CPU_MGQ_EARLY_INT BIT(6)
+#define BIT_PSTIMER_5 BIT(4)
+#define BIT_PSTIMER_4 BIT(3)
+#define BIT_PSTIMER_3 BIT(2)
+#define BIT_BB_STOPRX_INT BIT(0)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_P0HI8Q_HI9Q_TXBD_NUM		(Offset 0x23C0) */
+
+#define BIT_P0HI9Q_FLAG BIT(30)
+
+#define BIT_SHIFT_P0HI9Q_DESC_MODE 28
+#define BIT_MASK_P0HI9Q_DESC_MODE 0x3
+#define BIT_P0HI9Q_DESC_MODE(x)                                                \
+	(((x) & BIT_MASK_P0HI9Q_DESC_MODE) << BIT_SHIFT_P0HI9Q_DESC_MODE)
+#define BITS_P0HI9Q_DESC_MODE                                                  \
+	(BIT_MASK_P0HI9Q_DESC_MODE << BIT_SHIFT_P0HI9Q_DESC_MODE)
+#define BIT_CLEAR_P0HI9Q_DESC_MODE(x) ((x) & (~BITS_P0HI9Q_DESC_MODE))
+#define BIT_GET_P0HI9Q_DESC_MODE(x)                                            \
+	(((x) >> BIT_SHIFT_P0HI9Q_DESC_MODE) & BIT_MASK_P0HI9Q_DESC_MODE)
+#define BIT_SET_P0HI9Q_DESC_MODE(x, v)                                         \
+	(BIT_CLEAR_P0HI9Q_DESC_MODE(x) | BIT_P0HI9Q_DESC_MODE(v))
+
+#define BIT_SHIFT_P0HI9Q_DESC_NUM 16
+#define BIT_MASK_P0HI9Q_DESC_NUM 0xfff
+#define BIT_P0HI9Q_DESC_NUM(x)                                                 \
+	(((x) & BIT_MASK_P0HI9Q_DESC_NUM) << BIT_SHIFT_P0HI9Q_DESC_NUM)
+#define BITS_P0HI9Q_DESC_NUM                                                   \
+	(BIT_MASK_P0HI9Q_DESC_NUM << BIT_SHIFT_P0HI9Q_DESC_NUM)
+#define BIT_CLEAR_P0HI9Q_DESC_NUM(x) ((x) & (~BITS_P0HI9Q_DESC_NUM))
+#define BIT_GET_P0HI9Q_DESC_NUM(x)                                             \
+	(((x) >> BIT_SHIFT_P0HI9Q_DESC_NUM) & BIT_MASK_P0HI9Q_DESC_NUM)
+#define BIT_SET_P0HI9Q_DESC_NUM(x, v)                                          \
+	(BIT_CLEAR_P0HI9Q_DESC_NUM(x) | BIT_P0HI9Q_DESC_NUM(v))
+
+#define BIT_P0HI8Q_FLAG BIT(14)
+
+#define BIT_SHIFT_P0HI8Q_DESC_MODE 12
+#define BIT_MASK_P0HI8Q_DESC_MODE 0x3
+#define BIT_P0HI8Q_DESC_MODE(x)                                                \
+	(((x) & BIT_MASK_P0HI8Q_DESC_MODE) << BIT_SHIFT_P0HI8Q_DESC_MODE)
+#define BITS_P0HI8Q_DESC_MODE                                                  \
+	(BIT_MASK_P0HI8Q_DESC_MODE << BIT_SHIFT_P0HI8Q_DESC_MODE)
+#define BIT_CLEAR_P0HI8Q_DESC_MODE(x) ((x) & (~BITS_P0HI8Q_DESC_MODE))
+#define BIT_GET_P0HI8Q_DESC_MODE(x)                                            \
+	(((x) >> BIT_SHIFT_P0HI8Q_DESC_MODE) & BIT_MASK_P0HI8Q_DESC_MODE)
+#define BIT_SET_P0HI8Q_DESC_MODE(x, v)                                         \
+	(BIT_CLEAR_P0HI8Q_DESC_MODE(x) | BIT_P0HI8Q_DESC_MODE(v))
+
+#define BIT_SHIFT_P0HI8Q_DESC_NUM 0
+#define BIT_MASK_P0HI8Q_DESC_NUM 0xfff
+#define BIT_P0HI8Q_DESC_NUM(x)                                                 \
+	(((x) & BIT_MASK_P0HI8Q_DESC_NUM) << BIT_SHIFT_P0HI8Q_DESC_NUM)
+#define BITS_P0HI8Q_DESC_NUM                                                   \
+	(BIT_MASK_P0HI8Q_DESC_NUM << BIT_SHIFT_P0HI8Q_DESC_NUM)
+#define BIT_CLEAR_P0HI8Q_DESC_NUM(x) ((x) & (~BITS_P0HI8Q_DESC_NUM))
+#define BIT_GET_P0HI8Q_DESC_NUM(x)                                             \
+	(((x) >> BIT_SHIFT_P0HI8Q_DESC_NUM) & BIT_MASK_P0HI8Q_DESC_NUM)
+#define BIT_SET_P0HI8Q_DESC_NUM(x, v)                                          \
+	(BIT_CLEAR_P0HI8Q_DESC_NUM(x) | BIT_P0HI8Q_DESC_NUM(v))
+
+/* 2 REG_P0HI10Q_HI11Q_TXBD_NUM		(Offset 0x23C4) */
+
+#define BIT_P0HI11Q_FLAG BIT(30)
+
+#define BIT_SHIFT_P0HI11Q_DESC_MODE 28
+#define BIT_MASK_P0HI11Q_DESC_MODE 0x3
+#define BIT_P0HI11Q_DESC_MODE(x)                                               \
+	(((x) & BIT_MASK_P0HI11Q_DESC_MODE) << BIT_SHIFT_P0HI11Q_DESC_MODE)
+#define BITS_P0HI11Q_DESC_MODE                                                 \
+	(BIT_MASK_P0HI11Q_DESC_MODE << BIT_SHIFT_P0HI11Q_DESC_MODE)
+#define BIT_CLEAR_P0HI11Q_DESC_MODE(x) ((x) & (~BITS_P0HI11Q_DESC_MODE))
+#define BIT_GET_P0HI11Q_DESC_MODE(x)                                           \
+	(((x) >> BIT_SHIFT_P0HI11Q_DESC_MODE) & BIT_MASK_P0HI11Q_DESC_MODE)
+#define BIT_SET_P0HI11Q_DESC_MODE(x, v)                                        \
+	(BIT_CLEAR_P0HI11Q_DESC_MODE(x) | BIT_P0HI11Q_DESC_MODE(v))
+
+#define BIT_SHIFT_P0HI11Q_DESC_NUM 16
+#define BIT_MASK_P0HI11Q_DESC_NUM 0xfff
+#define BIT_P0HI11Q_DESC_NUM(x)                                                \
+	(((x) & BIT_MASK_P0HI11Q_DESC_NUM) << BIT_SHIFT_P0HI11Q_DESC_NUM)
+#define BITS_P0HI11Q_DESC_NUM                                                  \
+	(BIT_MASK_P0HI11Q_DESC_NUM << BIT_SHIFT_P0HI11Q_DESC_NUM)
+#define BIT_CLEAR_P0HI11Q_DESC_NUM(x) ((x) & (~BITS_P0HI11Q_DESC_NUM))
+#define BIT_GET_P0HI11Q_DESC_NUM(x)                                            \
+	(((x) >> BIT_SHIFT_P0HI11Q_DESC_NUM) & BIT_MASK_P0HI11Q_DESC_NUM)
+#define BIT_SET_P0HI11Q_DESC_NUM(x, v)                                         \
+	(BIT_CLEAR_P0HI11Q_DESC_NUM(x) | BIT_P0HI11Q_DESC_NUM(v))
+
+#define BIT_P0HI10Q_FLAG BIT(14)
+
+#define BIT_SHIFT_P0HI10Q_DESC_MODE 12
+#define BIT_MASK_P0HI10Q_DESC_MODE 0x3
+#define BIT_P0HI10Q_DESC_MODE(x)                                               \
+	(((x) & BIT_MASK_P0HI10Q_DESC_MODE) << BIT_SHIFT_P0HI10Q_DESC_MODE)
+#define BITS_P0HI10Q_DESC_MODE                                                 \
+	(BIT_MASK_P0HI10Q_DESC_MODE << BIT_SHIFT_P0HI10Q_DESC_MODE)
+#define BIT_CLEAR_P0HI10Q_DESC_MODE(x) ((x) & (~BITS_P0HI10Q_DESC_MODE))
+#define BIT_GET_P0HI10Q_DESC_MODE(x)                                           \
+	(((x) >> BIT_SHIFT_P0HI10Q_DESC_MODE) & BIT_MASK_P0HI10Q_DESC_MODE)
+#define BIT_SET_P0HI10Q_DESC_MODE(x, v)                                        \
+	(BIT_CLEAR_P0HI10Q_DESC_MODE(x) | BIT_P0HI10Q_DESC_MODE(v))
+
+#define BIT_SHIFT_P0HI10Q_DESC_NUM 0
+#define BIT_MASK_P0HI10Q_DESC_NUM 0xfff
+#define BIT_P0HI10Q_DESC_NUM(x)                                                \
+	(((x) & BIT_MASK_P0HI10Q_DESC_NUM) << BIT_SHIFT_P0HI10Q_DESC_NUM)
+#define BITS_P0HI10Q_DESC_NUM                                                  \
+	(BIT_MASK_P0HI10Q_DESC_NUM << BIT_SHIFT_P0HI10Q_DESC_NUM)
+#define BIT_CLEAR_P0HI10Q_DESC_NUM(x) ((x) & (~BITS_P0HI10Q_DESC_NUM))
+#define BIT_GET_P0HI10Q_DESC_NUM(x)                                            \
+	(((x) >> BIT_SHIFT_P0HI10Q_DESC_NUM) & BIT_MASK_P0HI10Q_DESC_NUM)
+#define BIT_SET_P0HI10Q_DESC_NUM(x, v)                                         \
+	(BIT_CLEAR_P0HI10Q_DESC_NUM(x) | BIT_P0HI10Q_DESC_NUM(v))
+
+/* 2 REG_P0HI12Q_HI13Q_TXBD_NUM		(Offset 0x23C8) */
+
+#define BIT_P0HI13Q_FLAG BIT(30)
+
+#define BIT_SHIFT_P0HI13Q_DESC_MODE 28
+#define BIT_MASK_P0HI13Q_DESC_MODE 0x3
+#define BIT_P0HI13Q_DESC_MODE(x)                                               \
+	(((x) & BIT_MASK_P0HI13Q_DESC_MODE) << BIT_SHIFT_P0HI13Q_DESC_MODE)
+#define BITS_P0HI13Q_DESC_MODE                                                 \
+	(BIT_MASK_P0HI13Q_DESC_MODE << BIT_SHIFT_P0HI13Q_DESC_MODE)
+#define BIT_CLEAR_P0HI13Q_DESC_MODE(x) ((x) & (~BITS_P0HI13Q_DESC_MODE))
+#define BIT_GET_P0HI13Q_DESC_MODE(x)                                           \
+	(((x) >> BIT_SHIFT_P0HI13Q_DESC_MODE) & BIT_MASK_P0HI13Q_DESC_MODE)
+#define BIT_SET_P0HI13Q_DESC_MODE(x, v)                                        \
+	(BIT_CLEAR_P0HI13Q_DESC_MODE(x) | BIT_P0HI13Q_DESC_MODE(v))
+
+#define BIT_SHIFT_P0HI13Q_DESC_NUM 16
+#define BIT_MASK_P0HI13Q_DESC_NUM 0xfff
+#define BIT_P0HI13Q_DESC_NUM(x)                                                \
+	(((x) & BIT_MASK_P0HI13Q_DESC_NUM) << BIT_SHIFT_P0HI13Q_DESC_NUM)
+#define BITS_P0HI13Q_DESC_NUM                                                  \
+	(BIT_MASK_P0HI13Q_DESC_NUM << BIT_SHIFT_P0HI13Q_DESC_NUM)
+#define BIT_CLEAR_P0HI13Q_DESC_NUM(x) ((x) & (~BITS_P0HI13Q_DESC_NUM))
+#define BIT_GET_P0HI13Q_DESC_NUM(x)                                            \
+	(((x) >> BIT_SHIFT_P0HI13Q_DESC_NUM) & BIT_MASK_P0HI13Q_DESC_NUM)
+#define BIT_SET_P0HI13Q_DESC_NUM(x, v)                                         \
+	(BIT_CLEAR_P0HI13Q_DESC_NUM(x) | BIT_P0HI13Q_DESC_NUM(v))
+
+#define BIT_P0HI12Q_FLAG BIT(14)
+
+#define BIT_SHIFT_P0HI12Q_DESC_MODE 12
+#define BIT_MASK_P0HI12Q_DESC_MODE 0x3
+#define BIT_P0HI12Q_DESC_MODE(x)                                               \
+	(((x) & BIT_MASK_P0HI12Q_DESC_MODE) << BIT_SHIFT_P0HI12Q_DESC_MODE)
+#define BITS_P0HI12Q_DESC_MODE                                                 \
+	(BIT_MASK_P0HI12Q_DESC_MODE << BIT_SHIFT_P0HI12Q_DESC_MODE)
+#define BIT_CLEAR_P0HI12Q_DESC_MODE(x) ((x) & (~BITS_P0HI12Q_DESC_MODE))
+#define BIT_GET_P0HI12Q_DESC_MODE(x)                                           \
+	(((x) >> BIT_SHIFT_P0HI12Q_DESC_MODE) & BIT_MASK_P0HI12Q_DESC_MODE)
+#define BIT_SET_P0HI12Q_DESC_MODE(x, v)                                        \
+	(BIT_CLEAR_P0HI12Q_DESC_MODE(x) | BIT_P0HI12Q_DESC_MODE(v))
+
+#define BIT_SHIFT_P0HI12Q_DESC_NUM 0
+#define BIT_MASK_P0HI12Q_DESC_NUM 0xfff
+#define BIT_P0HI12Q_DESC_NUM(x)                                                \
+	(((x) & BIT_MASK_P0HI12Q_DESC_NUM) << BIT_SHIFT_P0HI12Q_DESC_NUM)
+#define BITS_P0HI12Q_DESC_NUM                                                  \
+	(BIT_MASK_P0HI12Q_DESC_NUM << BIT_SHIFT_P0HI12Q_DESC_NUM)
+#define BIT_CLEAR_P0HI12Q_DESC_NUM(x) ((x) & (~BITS_P0HI12Q_DESC_NUM))
+#define BIT_GET_P0HI12Q_DESC_NUM(x)                                            \
+	(((x) >> BIT_SHIFT_P0HI12Q_DESC_NUM) & BIT_MASK_P0HI12Q_DESC_NUM)
+#define BIT_SET_P0HI12Q_DESC_NUM(x, v)                                         \
+	(BIT_CLEAR_P0HI12Q_DESC_NUM(x) | BIT_P0HI12Q_DESC_NUM(v))
+
+/* 2 REG_P0HI14Q_HI15Q_TXBD_NUM		(Offset 0x23CC) */
+
+#define BIT_P0HI15Q_FLAG BIT(30)
+
+#define BIT_SHIFT_P0HI15Q_DESC_MODE 28
+#define BIT_MASK_P0HI15Q_DESC_MODE 0x3
+#define BIT_P0HI15Q_DESC_MODE(x)                                               \
+	(((x) & BIT_MASK_P0HI15Q_DESC_MODE) << BIT_SHIFT_P0HI15Q_DESC_MODE)
+#define BITS_P0HI15Q_DESC_MODE                                                 \
+	(BIT_MASK_P0HI15Q_DESC_MODE << BIT_SHIFT_P0HI15Q_DESC_MODE)
+#define BIT_CLEAR_P0HI15Q_DESC_MODE(x) ((x) & (~BITS_P0HI15Q_DESC_MODE))
+#define BIT_GET_P0HI15Q_DESC_MODE(x)                                           \
+	(((x) >> BIT_SHIFT_P0HI15Q_DESC_MODE) & BIT_MASK_P0HI15Q_DESC_MODE)
+#define BIT_SET_P0HI15Q_DESC_MODE(x, v)                                        \
+	(BIT_CLEAR_P0HI15Q_DESC_MODE(x) | BIT_P0HI15Q_DESC_MODE(v))
+
+#define BIT_SHIFT_P0HI15Q_DESC_NUM 16
+#define BIT_MASK_P0HI15Q_DESC_NUM 0xfff
+#define BIT_P0HI15Q_DESC_NUM(x)                                                \
+	(((x) & BIT_MASK_P0HI15Q_DESC_NUM) << BIT_SHIFT_P0HI15Q_DESC_NUM)
+#define BITS_P0HI15Q_DESC_NUM                                                  \
+	(BIT_MASK_P0HI15Q_DESC_NUM << BIT_SHIFT_P0HI15Q_DESC_NUM)
+#define BIT_CLEAR_P0HI15Q_DESC_NUM(x) ((x) & (~BITS_P0HI15Q_DESC_NUM))
+#define BIT_GET_P0HI15Q_DESC_NUM(x)                                            \
+	(((x) >> BIT_SHIFT_P0HI15Q_DESC_NUM) & BIT_MASK_P0HI15Q_DESC_NUM)
+#define BIT_SET_P0HI15Q_DESC_NUM(x, v)                                         \
+	(BIT_CLEAR_P0HI15Q_DESC_NUM(x) | BIT_P0HI15Q_DESC_NUM(v))
+
+#define BIT_P0HI14Q_FLAG BIT(14)
+
+#define BIT_SHIFT_P0HI14Q_DESC_MODE 12
+#define BIT_MASK_P0HI14Q_DESC_MODE 0x3
+#define BIT_P0HI14Q_DESC_MODE(x)                                               \
+	(((x) & BIT_MASK_P0HI14Q_DESC_MODE) << BIT_SHIFT_P0HI14Q_DESC_MODE)
+#define BITS_P0HI14Q_DESC_MODE                                                 \
+	(BIT_MASK_P0HI14Q_DESC_MODE << BIT_SHIFT_P0HI14Q_DESC_MODE)
+#define BIT_CLEAR_P0HI14Q_DESC_MODE(x) ((x) & (~BITS_P0HI14Q_DESC_MODE))
+#define BIT_GET_P0HI14Q_DESC_MODE(x)                                           \
+	(((x) >> BIT_SHIFT_P0HI14Q_DESC_MODE) & BIT_MASK_P0HI14Q_DESC_MODE)
+#define BIT_SET_P0HI14Q_DESC_MODE(x, v)                                        \
+	(BIT_CLEAR_P0HI14Q_DESC_MODE(x) | BIT_P0HI14Q_DESC_MODE(v))
+
+#define BIT_SHIFT_P0HI14Q_DESC_NUM 0
+#define BIT_MASK_P0HI14Q_DESC_NUM 0xfff
+#define BIT_P0HI14Q_DESC_NUM(x)                                                \
+	(((x) & BIT_MASK_P0HI14Q_DESC_NUM) << BIT_SHIFT_P0HI14Q_DESC_NUM)
+#define BITS_P0HI14Q_DESC_NUM                                                  \
+	(BIT_MASK_P0HI14Q_DESC_NUM << BIT_SHIFT_P0HI14Q_DESC_NUM)
+#define BIT_CLEAR_P0HI14Q_DESC_NUM(x) ((x) & (~BITS_P0HI14Q_DESC_NUM))
+#define BIT_GET_P0HI14Q_DESC_NUM(x)                                            \
+	(((x) >> BIT_SHIFT_P0HI14Q_DESC_NUM) & BIT_MASK_P0HI14Q_DESC_NUM)
+#define BIT_SET_P0HI14Q_DESC_NUM(x, v)                                         \
+	(BIT_CLEAR_P0HI14Q_DESC_NUM(x) | BIT_P0HI14Q_DESC_NUM(v))
+
+/* 2 REG_ACH6_ACH7_TXBD_NUM			(Offset 0x23F0) */
+
+#define BIT_PCIE_ACH7_FLAG BIT(30)
+
+#define BIT_SHIFT_ACH7_DESC_MODE 28
+#define BIT_MASK_ACH7_DESC_MODE 0x3
+#define BIT_ACH7_DESC_MODE(x)                                                  \
+	(((x) & BIT_MASK_ACH7_DESC_MODE) << BIT_SHIFT_ACH7_DESC_MODE)
+#define BITS_ACH7_DESC_MODE                                                    \
+	(BIT_MASK_ACH7_DESC_MODE << BIT_SHIFT_ACH7_DESC_MODE)
+#define BIT_CLEAR_ACH7_DESC_MODE(x) ((x) & (~BITS_ACH7_DESC_MODE))
+#define BIT_GET_ACH7_DESC_MODE(x)                                              \
+	(((x) >> BIT_SHIFT_ACH7_DESC_MODE) & BIT_MASK_ACH7_DESC_MODE)
+#define BIT_SET_ACH7_DESC_MODE(x, v)                                           \
+	(BIT_CLEAR_ACH7_DESC_MODE(x) | BIT_ACH7_DESC_MODE(v))
+
+#define BIT_SHIFT_ACH7_DESC_NUM 16
+#define BIT_MASK_ACH7_DESC_NUM 0xfff
+#define BIT_ACH7_DESC_NUM(x)                                                   \
+	(((x) & BIT_MASK_ACH7_DESC_NUM) << BIT_SHIFT_ACH7_DESC_NUM)
+#define BITS_ACH7_DESC_NUM (BIT_MASK_ACH7_DESC_NUM << BIT_SHIFT_ACH7_DESC_NUM)
+#define BIT_CLEAR_ACH7_DESC_NUM(x) ((x) & (~BITS_ACH7_DESC_NUM))
+#define BIT_GET_ACH7_DESC_NUM(x)                                               \
+	(((x) >> BIT_SHIFT_ACH7_DESC_NUM) & BIT_MASK_ACH7_DESC_NUM)
+#define BIT_SET_ACH7_DESC_NUM(x, v)                                            \
+	(BIT_CLEAR_ACH7_DESC_NUM(x) | BIT_ACH7_DESC_NUM(v))
+
+#define BIT_PCIE_ACH6_FLAG BIT(14)
+
+#define BIT_SHIFT_ACH6_DESC_MODE 12
+#define BIT_MASK_ACH6_DESC_MODE 0x3
+#define BIT_ACH6_DESC_MODE(x)                                                  \
+	(((x) & BIT_MASK_ACH6_DESC_MODE) << BIT_SHIFT_ACH6_DESC_MODE)
+#define BITS_ACH6_DESC_MODE                                                    \
+	(BIT_MASK_ACH6_DESC_MODE << BIT_SHIFT_ACH6_DESC_MODE)
+#define BIT_CLEAR_ACH6_DESC_MODE(x) ((x) & (~BITS_ACH6_DESC_MODE))
+#define BIT_GET_ACH6_DESC_MODE(x)                                              \
+	(((x) >> BIT_SHIFT_ACH6_DESC_MODE) & BIT_MASK_ACH6_DESC_MODE)
+#define BIT_SET_ACH6_DESC_MODE(x, v)                                           \
+	(BIT_CLEAR_ACH6_DESC_MODE(x) | BIT_ACH6_DESC_MODE(v))
+
+#define BIT_SHIFT_ACH6_DESC_NUM 0
+#define BIT_MASK_ACH6_DESC_NUM 0xfff
+#define BIT_ACH6_DESC_NUM(x)                                                   \
+	(((x) & BIT_MASK_ACH6_DESC_NUM) << BIT_SHIFT_ACH6_DESC_NUM)
+#define BITS_ACH6_DESC_NUM (BIT_MASK_ACH6_DESC_NUM << BIT_SHIFT_ACH6_DESC_NUM)
+#define BIT_CLEAR_ACH6_DESC_NUM(x) ((x) & (~BITS_ACH6_DESC_NUM))
+#define BIT_GET_ACH6_DESC_NUM(x)                                               \
+	(((x) >> BIT_SHIFT_ACH6_DESC_NUM) & BIT_MASK_ACH6_DESC_NUM)
+#define BIT_SET_ACH6_DESC_NUM(x, v)                                            \
+	(BIT_CLEAR_ACH6_DESC_NUM(x) | BIT_ACH6_DESC_NUM(v))
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_FAST_EDCA_VOVI_SETTING_V1		(Offset 0x2448) */
+
+#define BIT_SHIFT_VO_FAST_EDCA_TO_V1 0
+#define BIT_MASK_VO_FAST_EDCA_TO_V1 0xffff
+#define BIT_VO_FAST_EDCA_TO_V1(x)                                              \
+	(((x) & BIT_MASK_VO_FAST_EDCA_TO_V1) << BIT_SHIFT_VO_FAST_EDCA_TO_V1)
+#define BITS_VO_FAST_EDCA_TO_V1                                                \
+	(BIT_MASK_VO_FAST_EDCA_TO_V1 << BIT_SHIFT_VO_FAST_EDCA_TO_V1)
+#define BIT_CLEAR_VO_FAST_EDCA_TO_V1(x) ((x) & (~BITS_VO_FAST_EDCA_TO_V1))
+#define BIT_GET_VO_FAST_EDCA_TO_V1(x)                                          \
+	(((x) >> BIT_SHIFT_VO_FAST_EDCA_TO_V1) & BIT_MASK_VO_FAST_EDCA_TO_V1)
+#define BIT_SET_VO_FAST_EDCA_TO_V1(x, v)                                       \
+	(BIT_CLEAR_VO_FAST_EDCA_TO_V1(x) | BIT_VO_FAST_EDCA_TO_V1(v))
+
+/* 2 REG_FAST_EDCA_BEBK_SETTING_V1		(Offset 0x244C) */
+
+#define BIT_SHIFT_BE_FAST_EDCA_TO_V1 0
+#define BIT_MASK_BE_FAST_EDCA_TO_V1 0xffff
+#define BIT_BE_FAST_EDCA_TO_V1(x)                                              \
+	(((x) & BIT_MASK_BE_FAST_EDCA_TO_V1) << BIT_SHIFT_BE_FAST_EDCA_TO_V1)
+#define BITS_BE_FAST_EDCA_TO_V1                                                \
+	(BIT_MASK_BE_FAST_EDCA_TO_V1 << BIT_SHIFT_BE_FAST_EDCA_TO_V1)
+#define BIT_CLEAR_BE_FAST_EDCA_TO_V1(x) ((x) & (~BITS_BE_FAST_EDCA_TO_V1))
+#define BIT_GET_BE_FAST_EDCA_TO_V1(x)                                          \
+	(((x) >> BIT_SHIFT_BE_FAST_EDCA_TO_V1) & BIT_MASK_BE_FAST_EDCA_TO_V1)
+#define BIT_SET_BE_FAST_EDCA_TO_V1(x, v)                                       \
+	(BIT_CLEAR_BE_FAST_EDCA_TO_V1(x) | BIT_BE_FAST_EDCA_TO_V1(v))
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_R_MACID_RELEASE_SUCCESS_0_V1	(Offset 0x2460) */
+
+#define BIT_SHIFT_R_MACID_RELEASE_SUCCESS_0 0
+#define BIT_MASK_R_MACID_RELEASE_SUCCESS_0 0xffffffffL
+#define BIT_R_MACID_RELEASE_SUCCESS_0(x)                                       \
+	(((x) & BIT_MASK_R_MACID_RELEASE_SUCCESS_0)                            \
+	 << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_0)
+#define BITS_R_MACID_RELEASE_SUCCESS_0                                         \
+	(BIT_MASK_R_MACID_RELEASE_SUCCESS_0                                    \
+	 << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_0)
+#define BIT_CLEAR_R_MACID_RELEASE_SUCCESS_0(x)                                 \
+	((x) & (~BITS_R_MACID_RELEASE_SUCCESS_0))
+#define BIT_GET_R_MACID_RELEASE_SUCCESS_0(x)                                   \
+	(((x) >> BIT_SHIFT_R_MACID_RELEASE_SUCCESS_0) &                        \
+	 BIT_MASK_R_MACID_RELEASE_SUCCESS_0)
+#define BIT_SET_R_MACID_RELEASE_SUCCESS_0(x, v)                                \
+	(BIT_CLEAR_R_MACID_RELEASE_SUCCESS_0(x) |                              \
+	 BIT_R_MACID_RELEASE_SUCCESS_0(v))
+
+/* 2 REG_R_MACID_RELEASE_SUCCESS_2_V1	(Offset 0x2468) */
+
+#define BIT_SHIFT_R_MACID_RELEASE_SUCCESS_2 0
+#define BIT_MASK_R_MACID_RELEASE_SUCCESS_2 0xffffffffL
+#define BIT_R_MACID_RELEASE_SUCCESS_2(x)                                       \
+	(((x) & BIT_MASK_R_MACID_RELEASE_SUCCESS_2)                            \
+	 << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_2)
+#define BITS_R_MACID_RELEASE_SUCCESS_2                                         \
+	(BIT_MASK_R_MACID_RELEASE_SUCCESS_2                                    \
+	 << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_2)
+#define BIT_CLEAR_R_MACID_RELEASE_SUCCESS_2(x)                                 \
+	((x) & (~BITS_R_MACID_RELEASE_SUCCESS_2))
+#define BIT_GET_R_MACID_RELEASE_SUCCESS_2(x)                                   \
+	(((x) >> BIT_SHIFT_R_MACID_RELEASE_SUCCESS_2) &                        \
+	 BIT_MASK_R_MACID_RELEASE_SUCCESS_2)
+#define BIT_SET_R_MACID_RELEASE_SUCCESS_2(x, v)                                \
+	(BIT_CLEAR_R_MACID_RELEASE_SUCCESS_2(x) |                              \
+	 BIT_R_MACID_RELEASE_SUCCESS_2(v))
+
+/* 2 REG_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_V1 (Offset 0x247C) */
+
+#define BIT_SHIFT_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET 0
+#define BIT_MASK_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET 0x7f
+#define BIT_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET(x)                            \
+	(((x) & BIT_MASK_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET)                 \
+	 << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET)
+#define BITS_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET                              \
+	(BIT_MASK_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET                         \
+	 << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET)
+#define BIT_CLEAR_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET(x)                      \
+	((x) & (~BITS_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET))
+#define BIT_GET_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET(x)                        \
+	(((x) >> BIT_SHIFT_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET) &             \
+	 BIT_MASK_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET)
+#define BIT_SET_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET(x, v)                     \
+	(BIT_CLEAR_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET(x) |                   \
+	 BIT_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET(v))
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+/* 2 REG_NAN_INFO0				(Offset 0x2480) */
+
+#define BIT_SHIFT_NAN_INFO0 0
+#define BIT_MASK_NAN_INFO0 0xffffffffL
+#define BIT_NAN_INFO0(x) (((x) & BIT_MASK_NAN_INFO0) << BIT_SHIFT_NAN_INFO0)
+#define BITS_NAN_INFO0 (BIT_MASK_NAN_INFO0 << BIT_SHIFT_NAN_INFO0)
+#define BIT_CLEAR_NAN_INFO0(x) ((x) & (~BITS_NAN_INFO0))
+#define BIT_GET_NAN_INFO0(x) (((x) >> BIT_SHIFT_NAN_INFO0) & BIT_MASK_NAN_INFO0)
+#define BIT_SET_NAN_INFO0(x, v) (BIT_CLEAR_NAN_INFO0(x) | BIT_NAN_INFO0(v))
+
+/* 2 REG_NAN_INFO1				(Offset 0x2484) */
+
+#define BIT_SHIFT_NAN_INFO1 0
+#define BIT_MASK_NAN_INFO1 0xffffffffL
+#define BIT_NAN_INFO1(x) (((x) & BIT_MASK_NAN_INFO1) << BIT_SHIFT_NAN_INFO1)
+#define BITS_NAN_INFO1 (BIT_MASK_NAN_INFO1 << BIT_SHIFT_NAN_INFO1)
+#define BIT_CLEAR_NAN_INFO1(x) ((x) & (~BITS_NAN_INFO1))
+#define BIT_GET_NAN_INFO1(x) (((x) >> BIT_SHIFT_NAN_INFO1) & BIT_MASK_NAN_INFO1)
+#define BIT_SET_NAN_INFO1(x, v) (BIT_CLEAR_NAN_INFO1(x) | BIT_NAN_INFO1(v))
+
+/* 2 REG_NAN_INFO2				(Offset 0x2488) */
+
+#define BIT_SHIFT_NAN_INFO2 0
+#define BIT_MASK_NAN_INFO2 0xffffffffL
+#define BIT_NAN_INFO2(x) (((x) & BIT_MASK_NAN_INFO2) << BIT_SHIFT_NAN_INFO2)
+#define BITS_NAN_INFO2 (BIT_MASK_NAN_INFO2 << BIT_SHIFT_NAN_INFO2)
+#define BIT_CLEAR_NAN_INFO2(x) ((x) & (~BITS_NAN_INFO2))
+#define BIT_GET_NAN_INFO2(x) (((x) >> BIT_SHIFT_NAN_INFO2) & BIT_MASK_NAN_INFO2)
+#define BIT_SET_NAN_INFO2(x, v) (BIT_CLEAR_NAN_INFO2(x) | BIT_NAN_INFO2(v))
+
+/* 2 REG_NAN_INFO3				(Offset 0x248C) */
+
+#define BIT_SHIFT_NAN_INFO3 0
+#define BIT_MASK_NAN_INFO3 0xffffffffL
+#define BIT_NAN_INFO3(x) (((x) & BIT_MASK_NAN_INFO3) << BIT_SHIFT_NAN_INFO3)
+#define BITS_NAN_INFO3 (BIT_MASK_NAN_INFO3 << BIT_SHIFT_NAN_INFO3)
+#define BIT_CLEAR_NAN_INFO3(x) ((x) & (~BITS_NAN_INFO3))
+#define BIT_GET_NAN_INFO3(x) (((x) >> BIT_SHIFT_NAN_INFO3) & BIT_MASK_NAN_INFO3)
+#define BIT_SET_NAN_INFO3(x, v) (BIT_CLEAR_NAN_INFO3(x) | BIT_NAN_INFO3(v))
+
+/* 2 REG_NAN_INFO4				(Offset 0x2490) */
+
+#define BIT_SHIFT_NAN_INFO4 0
+#define BIT_MASK_NAN_INFO4 0xffffffffL
+#define BIT_NAN_INFO4(x) (((x) & BIT_MASK_NAN_INFO4) << BIT_SHIFT_NAN_INFO4)
+#define BITS_NAN_INFO4 (BIT_MASK_NAN_INFO4 << BIT_SHIFT_NAN_INFO4)
+#define BIT_CLEAR_NAN_INFO4(x) ((x) & (~BITS_NAN_INFO4))
+#define BIT_GET_NAN_INFO4(x) (((x) >> BIT_SHIFT_NAN_INFO4) & BIT_MASK_NAN_INFO4)
+#define BIT_SET_NAN_INFO4(x, v) (BIT_CLEAR_NAN_INFO4(x) | BIT_NAN_INFO4(v))
+
+/* 2 REG_NAN_INFO5				(Offset 0x2494) */
+
+#define BIT_SHIFT_NAN_INFO5 0
+#define BIT_MASK_NAN_INFO5 0xffffffffL
+#define BIT_NAN_INFO5(x) (((x) & BIT_MASK_NAN_INFO5) << BIT_SHIFT_NAN_INFO5)
+#define BITS_NAN_INFO5 (BIT_MASK_NAN_INFO5 << BIT_SHIFT_NAN_INFO5)
+#define BIT_CLEAR_NAN_INFO5(x) ((x) & (~BITS_NAN_INFO5))
+#define BIT_GET_NAN_INFO5(x) (((x) >> BIT_SHIFT_NAN_INFO5) & BIT_MASK_NAN_INFO5)
+#define BIT_SET_NAN_INFO5(x, v) (BIT_CLEAR_NAN_INFO5(x) | BIT_NAN_INFO5(v))
+
+/* 2 REG_NAN_INFO6				(Offset 0x2498) */
+
+#define BIT_SHIFT_NAN_INFO6 0
+#define BIT_MASK_NAN_INFO6 0xffffffffL
+#define BIT_NAN_INFO6(x) (((x) & BIT_MASK_NAN_INFO6) << BIT_SHIFT_NAN_INFO6)
+#define BITS_NAN_INFO6 (BIT_MASK_NAN_INFO6 << BIT_SHIFT_NAN_INFO6)
+#define BIT_CLEAR_NAN_INFO6(x) ((x) & (~BITS_NAN_INFO6))
+#define BIT_GET_NAN_INFO6(x) (((x) >> BIT_SHIFT_NAN_INFO6) & BIT_MASK_NAN_INFO6)
+#define BIT_SET_NAN_INFO6(x, v) (BIT_CLEAR_NAN_INFO6(x) | BIT_NAN_INFO6(v))
+
+/* 2 REG_NAN_INFO7				(Offset 0x249C) */
+
+#define BIT_SHIFT_NAN_INFO7 0
+#define BIT_MASK_NAN_INFO7 0xffffffffL
+#define BIT_NAN_INFO7(x) (((x) & BIT_MASK_NAN_INFO7) << BIT_SHIFT_NAN_INFO7)
+#define BITS_NAN_INFO7 (BIT_MASK_NAN_INFO7 << BIT_SHIFT_NAN_INFO7)
+#define BIT_CLEAR_NAN_INFO7(x) ((x) & (~BITS_NAN_INFO7))
+#define BIT_GET_NAN_INFO7(x) (((x) >> BIT_SHIFT_NAN_INFO7) & BIT_MASK_NAN_INFO7)
+#define BIT_SET_NAN_INFO7(x, v) (BIT_CLEAR_NAN_INFO7(x) | BIT_NAN_INFO7(v))
+
+/* 2 REG_NAN_INFO8				(Offset 0x24A0) */
+
+#define BIT_SHIFT_NAN_INFO8 0
+#define BIT_MASK_NAN_INFO8 0xffffffffL
+#define BIT_NAN_INFO8(x) (((x) & BIT_MASK_NAN_INFO8) << BIT_SHIFT_NAN_INFO8)
+#define BITS_NAN_INFO8 (BIT_MASK_NAN_INFO8 << BIT_SHIFT_NAN_INFO8)
+#define BIT_CLEAR_NAN_INFO8(x) ((x) & (~BITS_NAN_INFO8))
+#define BIT_GET_NAN_INFO8(x) (((x) >> BIT_SHIFT_NAN_INFO8) & BIT_MASK_NAN_INFO8)
+#define BIT_SET_NAN_INFO8(x, v) (BIT_CLEAR_NAN_INFO8(x) | BIT_NAN_INFO8(v))
+
+/* 2 REG_NAN_INFO9				(Offset 0x24A4) */
+
+#define BIT_SHIFT_NAN_INFO9 0
+#define BIT_MASK_NAN_INFO9 0xffffffffL
+#define BIT_NAN_INFO9(x) (((x) & BIT_MASK_NAN_INFO9) << BIT_SHIFT_NAN_INFO9)
+#define BITS_NAN_INFO9 (BIT_MASK_NAN_INFO9 << BIT_SHIFT_NAN_INFO9)
+#define BIT_CLEAR_NAN_INFO9(x) ((x) & (~BITS_NAN_INFO9))
+#define BIT_GET_NAN_INFO9(x) (((x) >> BIT_SHIFT_NAN_INFO9) & BIT_MASK_NAN_INFO9)
+#define BIT_SET_NAN_INFO9(x, v) (BIT_CLEAR_NAN_INFO9(x) | BIT_NAN_INFO9(v))
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+/* 2 REG_CHNL_INFO_CTRL_V1			(Offset 0x24D0) */
+
+#define BIT_CHNL_REF_EDCA BIT(5)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_CHNL_INFO_CTRL_V1			(Offset 0x24D0) */
+
+#define BIT_CHNL_REF_CCA BIT(4)
+#define BIT_MACTX_ERR_4 BIT(4)
+
+#define BIT_SHIFT_VHTHT_MIMO_CTRL_FIELD 1
+#define BIT_MASK_VHTHT_MIMO_CTRL_FIELD 0xffffff
+#define BIT_VHTHT_MIMO_CTRL_FIELD(x)                                           \
+	(((x) & BIT_MASK_VHTHT_MIMO_CTRL_FIELD)                                \
+	 << BIT_SHIFT_VHTHT_MIMO_CTRL_FIELD)
+#define BITS_VHTHT_MIMO_CTRL_FIELD                                             \
+	(BIT_MASK_VHTHT_MIMO_CTRL_FIELD << BIT_SHIFT_VHTHT_MIMO_CTRL_FIELD)
+#define BIT_CLEAR_VHTHT_MIMO_CTRL_FIELD(x) ((x) & (~BITS_VHTHT_MIMO_CTRL_FIELD))
+#define BIT_GET_VHTHT_MIMO_CTRL_FIELD(x)                                       \
+	(((x) >> BIT_SHIFT_VHTHT_MIMO_CTRL_FIELD) &                            \
+	 BIT_MASK_VHTHT_MIMO_CTRL_FIELD)
+#define BIT_SET_VHTHT_MIMO_CTRL_FIELD(x, v)                                    \
+	(BIT_CLEAR_VHTHT_MIMO_CTRL_FIELD(x) | BIT_VHTHT_MIMO_CTRL_FIELD(v))
+
+#define BIT_CSI_INTERRUPT_STATUS BIT(0)
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_CHNL_IDLE_TIME_V1			(Offset 0x24D4) */
+
+#define BIT_SHIFT_CHNL_IDLE_TIME 0
+#define BIT_MASK_CHNL_IDLE_TIME 0xffffffffL
+#define BIT_CHNL_IDLE_TIME(x)                                                  \
+	(((x) & BIT_MASK_CHNL_IDLE_TIME) << BIT_SHIFT_CHNL_IDLE_TIME)
+#define BITS_CHNL_IDLE_TIME                                                    \
+	(BIT_MASK_CHNL_IDLE_TIME << BIT_SHIFT_CHNL_IDLE_TIME)
+#define BIT_CLEAR_CHNL_IDLE_TIME(x) ((x) & (~BITS_CHNL_IDLE_TIME))
+#define BIT_GET_CHNL_IDLE_TIME(x)                                              \
+	(((x) >> BIT_SHIFT_CHNL_IDLE_TIME) & BIT_MASK_CHNL_IDLE_TIME)
+#define BIT_SET_CHNL_IDLE_TIME(x, v)                                           \
+	(BIT_CLEAR_CHNL_IDLE_TIME(x) | BIT_CHNL_IDLE_TIME(v))
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT)
+
+/* 2 REG_SWPS_PKT_TH_V1			(Offset 0x24F6) */
+
+#define BIT_SHIFT_SWPS_PKT_TH 0
+#define BIT_MASK_SWPS_PKT_TH 0xffff
+#define BIT_SWPS_PKT_TH(x)                                                     \
+	(((x) & BIT_MASK_SWPS_PKT_TH) << BIT_SHIFT_SWPS_PKT_TH)
+#define BITS_SWPS_PKT_TH (BIT_MASK_SWPS_PKT_TH << BIT_SHIFT_SWPS_PKT_TH)
+#define BIT_CLEAR_SWPS_PKT_TH(x) ((x) & (~BITS_SWPS_PKT_TH))
+#define BIT_GET_SWPS_PKT_TH(x)                                                 \
+	(((x) >> BIT_SHIFT_SWPS_PKT_TH) & BIT_MASK_SWPS_PKT_TH)
+#define BIT_SET_SWPS_PKT_TH(x, v)                                              \
+	(BIT_CLEAR_SWPS_PKT_TH(x) | BIT_SWPS_PKT_TH(v))
+
+/* 2 REG_SWPS_TIME_TH_V1			(Offset 0x24F8) */
+
+#define BIT_SHIFT_SWPS_PSTIME_TH 16
+#define BIT_MASK_SWPS_PSTIME_TH 0xffff
+#define BIT_SWPS_PSTIME_TH(x)                                                  \
+	(((x) & BIT_MASK_SWPS_PSTIME_TH) << BIT_SHIFT_SWPS_PSTIME_TH)
+#define BITS_SWPS_PSTIME_TH                                                    \
+	(BIT_MASK_SWPS_PSTIME_TH << BIT_SHIFT_SWPS_PSTIME_TH)
+#define BIT_CLEAR_SWPS_PSTIME_TH(x) ((x) & (~BITS_SWPS_PSTIME_TH))
+#define BIT_GET_SWPS_PSTIME_TH(x)                                              \
+	(((x) >> BIT_SHIFT_SWPS_PSTIME_TH) & BIT_MASK_SWPS_PSTIME_TH)
+#define BIT_SET_SWPS_PSTIME_TH(x, v)                                           \
+	(BIT_CLEAR_SWPS_PSTIME_TH(x) | BIT_SWPS_PSTIME_TH(v))
+
+#define BIT_SHIFT_SWPS_TIME_TH 0
+#define BIT_MASK_SWPS_TIME_TH 0xffff
+#define BIT_SWPS_TIME_TH(x)                                                    \
+	(((x) & BIT_MASK_SWPS_TIME_TH) << BIT_SHIFT_SWPS_TIME_TH)
+#define BITS_SWPS_TIME_TH (BIT_MASK_SWPS_TIME_TH << BIT_SHIFT_SWPS_TIME_TH)
+#define BIT_CLEAR_SWPS_TIME_TH(x) ((x) & (~BITS_SWPS_TIME_TH))
+#define BIT_GET_SWPS_TIME_TH(x)                                                \
+	(((x) >> BIT_SHIFT_SWPS_TIME_TH) & BIT_MASK_SWPS_TIME_TH)
+#define BIT_SET_SWPS_TIME_TH(x, v)                                             \
+	(BIT_CLEAR_SWPS_TIME_TH(x) | BIT_SWPS_TIME_TH(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_TXPAGE_INT_CTRL_0			(Offset 0x3200) */
+
+#define BIT_CH0_INT_EN BIT(31)
+
+#define BIT_SHIFT_CH0_HIGH_TH 16
+#define BIT_MASK_CH0_HIGH_TH 0xfff
+#define BIT_CH0_HIGH_TH(x)                                                     \
+	(((x) & BIT_MASK_CH0_HIGH_TH) << BIT_SHIFT_CH0_HIGH_TH)
+#define BITS_CH0_HIGH_TH (BIT_MASK_CH0_HIGH_TH << BIT_SHIFT_CH0_HIGH_TH)
+#define BIT_CLEAR_CH0_HIGH_TH(x) ((x) & (~BITS_CH0_HIGH_TH))
+#define BIT_GET_CH0_HIGH_TH(x)                                                 \
+	(((x) >> BIT_SHIFT_CH0_HIGH_TH) & BIT_MASK_CH0_HIGH_TH)
+#define BIT_SET_CH0_HIGH_TH(x, v)                                              \
+	(BIT_CLEAR_CH0_HIGH_TH(x) | BIT_CH0_HIGH_TH(v))
+
+#define BIT_SHIFT_CH0_LOW_TH 0
+#define BIT_MASK_CH0_LOW_TH 0xfff
+#define BIT_CH0_LOW_TH(x) (((x) & BIT_MASK_CH0_LOW_TH) << BIT_SHIFT_CH0_LOW_TH)
+#define BITS_CH0_LOW_TH (BIT_MASK_CH0_LOW_TH << BIT_SHIFT_CH0_LOW_TH)
+#define BIT_CLEAR_CH0_LOW_TH(x) ((x) & (~BITS_CH0_LOW_TH))
+#define BIT_GET_CH0_LOW_TH(x)                                                  \
+	(((x) >> BIT_SHIFT_CH0_LOW_TH) & BIT_MASK_CH0_LOW_TH)
+#define BIT_SET_CH0_LOW_TH(x, v) (BIT_CLEAR_CH0_LOW_TH(x) | BIT_CH0_LOW_TH(v))
+
+/* 2 REG_TXPAGE_INT_CTRL_1			(Offset 0x3204) */
+
+#define BIT_CH1_INT_EN BIT(31)
+
+#define BIT_SHIFT_CH1_HIGH_TH 16
+#define BIT_MASK_CH1_HIGH_TH 0xfff
+#define BIT_CH1_HIGH_TH(x)                                                     \
+	(((x) & BIT_MASK_CH1_HIGH_TH) << BIT_SHIFT_CH1_HIGH_TH)
+#define BITS_CH1_HIGH_TH (BIT_MASK_CH1_HIGH_TH << BIT_SHIFT_CH1_HIGH_TH)
+#define BIT_CLEAR_CH1_HIGH_TH(x) ((x) & (~BITS_CH1_HIGH_TH))
+#define BIT_GET_CH1_HIGH_TH(x)                                                 \
+	(((x) >> BIT_SHIFT_CH1_HIGH_TH) & BIT_MASK_CH1_HIGH_TH)
+#define BIT_SET_CH1_HIGH_TH(x, v)                                              \
+	(BIT_CLEAR_CH1_HIGH_TH(x) | BIT_CH1_HIGH_TH(v))
+
+#define BIT_SHIFT_CH1_LOW_TH 0
+#define BIT_MASK_CH1_LOW_TH 0xfff
+#define BIT_CH1_LOW_TH(x) (((x) & BIT_MASK_CH1_LOW_TH) << BIT_SHIFT_CH1_LOW_TH)
+#define BITS_CH1_LOW_TH (BIT_MASK_CH1_LOW_TH << BIT_SHIFT_CH1_LOW_TH)
+#define BIT_CLEAR_CH1_LOW_TH(x) ((x) & (~BITS_CH1_LOW_TH))
+#define BIT_GET_CH1_LOW_TH(x)                                                  \
+	(((x) >> BIT_SHIFT_CH1_LOW_TH) & BIT_MASK_CH1_LOW_TH)
+#define BIT_SET_CH1_LOW_TH(x, v) (BIT_CLEAR_CH1_LOW_TH(x) | BIT_CH1_LOW_TH(v))
+
+/* 2 REG_TXPAGE_INT_CTRL_2			(Offset 0x3208) */
+
+#define BIT_CH2_INT_EN BIT(31)
+
+#define BIT_SHIFT_CH2_HIGH_TH 16
+#define BIT_MASK_CH2_HIGH_TH 0xfff
+#define BIT_CH2_HIGH_TH(x)                                                     \
+	(((x) & BIT_MASK_CH2_HIGH_TH) << BIT_SHIFT_CH2_HIGH_TH)
+#define BITS_CH2_HIGH_TH (BIT_MASK_CH2_HIGH_TH << BIT_SHIFT_CH2_HIGH_TH)
+#define BIT_CLEAR_CH2_HIGH_TH(x) ((x) & (~BITS_CH2_HIGH_TH))
+#define BIT_GET_CH2_HIGH_TH(x)                                                 \
+	(((x) >> BIT_SHIFT_CH2_HIGH_TH) & BIT_MASK_CH2_HIGH_TH)
+#define BIT_SET_CH2_HIGH_TH(x, v)                                              \
+	(BIT_CLEAR_CH2_HIGH_TH(x) | BIT_CH2_HIGH_TH(v))
+
+#define BIT_SHIFT_CH2_LOW_TH 0
+#define BIT_MASK_CH2_LOW_TH 0xfff
+#define BIT_CH2_LOW_TH(x) (((x) & BIT_MASK_CH2_LOW_TH) << BIT_SHIFT_CH2_LOW_TH)
+#define BITS_CH2_LOW_TH (BIT_MASK_CH2_LOW_TH << BIT_SHIFT_CH2_LOW_TH)
+#define BIT_CLEAR_CH2_LOW_TH(x) ((x) & (~BITS_CH2_LOW_TH))
+#define BIT_GET_CH2_LOW_TH(x)                                                  \
+	(((x) >> BIT_SHIFT_CH2_LOW_TH) & BIT_MASK_CH2_LOW_TH)
+#define BIT_SET_CH2_LOW_TH(x, v) (BIT_CLEAR_CH2_LOW_TH(x) | BIT_CH2_LOW_TH(v))
+
+/* 2 REG_TXPAGE_INT_CTRL_3			(Offset 0x320C) */
+
+#define BIT_CH3_INT_EN BIT(31)
+
+#define BIT_SHIFT_CH3_HIGH_TH 16
+#define BIT_MASK_CH3_HIGH_TH 0xfff
+#define BIT_CH3_HIGH_TH(x)                                                     \
+	(((x) & BIT_MASK_CH3_HIGH_TH) << BIT_SHIFT_CH3_HIGH_TH)
+#define BITS_CH3_HIGH_TH (BIT_MASK_CH3_HIGH_TH << BIT_SHIFT_CH3_HIGH_TH)
+#define BIT_CLEAR_CH3_HIGH_TH(x) ((x) & (~BITS_CH3_HIGH_TH))
+#define BIT_GET_CH3_HIGH_TH(x)                                                 \
+	(((x) >> BIT_SHIFT_CH3_HIGH_TH) & BIT_MASK_CH3_HIGH_TH)
+#define BIT_SET_CH3_HIGH_TH(x, v)                                              \
+	(BIT_CLEAR_CH3_HIGH_TH(x) | BIT_CH3_HIGH_TH(v))
+
+#define BIT_SHIFT_CH3_LOW_TH 0
+#define BIT_MASK_CH3_LOW_TH 0xfff
+#define BIT_CH3_LOW_TH(x) (((x) & BIT_MASK_CH3_LOW_TH) << BIT_SHIFT_CH3_LOW_TH)
+#define BITS_CH3_LOW_TH (BIT_MASK_CH3_LOW_TH << BIT_SHIFT_CH3_LOW_TH)
+#define BIT_CLEAR_CH3_LOW_TH(x) ((x) & (~BITS_CH3_LOW_TH))
+#define BIT_GET_CH3_LOW_TH(x)                                                  \
+	(((x) >> BIT_SHIFT_CH3_LOW_TH) & BIT_MASK_CH3_LOW_TH)
+#define BIT_SET_CH3_LOW_TH(x, v) (BIT_CLEAR_CH3_LOW_TH(x) | BIT_CH3_LOW_TH(v))
+
+/* 2 REG_TXPAGE_INT_CTRL_4			(Offset 0x3210) */
+
+#define BIT_CH4_INT_EN BIT(31)
+
+#define BIT_SHIFT_CH4_HIGH_TH 16
+#define BIT_MASK_CH4_HIGH_TH 0xfff
+#define BIT_CH4_HIGH_TH(x)                                                     \
+	(((x) & BIT_MASK_CH4_HIGH_TH) << BIT_SHIFT_CH4_HIGH_TH)
+#define BITS_CH4_HIGH_TH (BIT_MASK_CH4_HIGH_TH << BIT_SHIFT_CH4_HIGH_TH)
+#define BIT_CLEAR_CH4_HIGH_TH(x) ((x) & (~BITS_CH4_HIGH_TH))
+#define BIT_GET_CH4_HIGH_TH(x)                                                 \
+	(((x) >> BIT_SHIFT_CH4_HIGH_TH) & BIT_MASK_CH4_HIGH_TH)
+#define BIT_SET_CH4_HIGH_TH(x, v)                                              \
+	(BIT_CLEAR_CH4_HIGH_TH(x) | BIT_CH4_HIGH_TH(v))
+
+#define BIT_SHIFT_CH4_LOW_TH 0
+#define BIT_MASK_CH4_LOW_TH 0xfff
+#define BIT_CH4_LOW_TH(x) (((x) & BIT_MASK_CH4_LOW_TH) << BIT_SHIFT_CH4_LOW_TH)
+#define BITS_CH4_LOW_TH (BIT_MASK_CH4_LOW_TH << BIT_SHIFT_CH4_LOW_TH)
+#define BIT_CLEAR_CH4_LOW_TH(x) ((x) & (~BITS_CH4_LOW_TH))
+#define BIT_GET_CH4_LOW_TH(x)                                                  \
+	(((x) >> BIT_SHIFT_CH4_LOW_TH) & BIT_MASK_CH4_LOW_TH)
+#define BIT_SET_CH4_LOW_TH(x, v) (BIT_CLEAR_CH4_LOW_TH(x) | BIT_CH4_LOW_TH(v))
+
+/* 2 REG_TXPAGE_INT_CTRL_5			(Offset 0x3214) */
+
+#define BIT_CH5_INT_EN BIT(31)
+
+#define BIT_SHIFT_CH5_HIGH_TH 16
+#define BIT_MASK_CH5_HIGH_TH 0xfff
+#define BIT_CH5_HIGH_TH(x)                                                     \
+	(((x) & BIT_MASK_CH5_HIGH_TH) << BIT_SHIFT_CH5_HIGH_TH)
+#define BITS_CH5_HIGH_TH (BIT_MASK_CH5_HIGH_TH << BIT_SHIFT_CH5_HIGH_TH)
+#define BIT_CLEAR_CH5_HIGH_TH(x) ((x) & (~BITS_CH5_HIGH_TH))
+#define BIT_GET_CH5_HIGH_TH(x)                                                 \
+	(((x) >> BIT_SHIFT_CH5_HIGH_TH) & BIT_MASK_CH5_HIGH_TH)
+#define BIT_SET_CH5_HIGH_TH(x, v)                                              \
+	(BIT_CLEAR_CH5_HIGH_TH(x) | BIT_CH5_HIGH_TH(v))
+
+#define BIT_SHIFT_CH5_LOW_TH 0
+#define BIT_MASK_CH5_LOW_TH 0xfff
+#define BIT_CH5_LOW_TH(x) (((x) & BIT_MASK_CH5_LOW_TH) << BIT_SHIFT_CH5_LOW_TH)
+#define BITS_CH5_LOW_TH (BIT_MASK_CH5_LOW_TH << BIT_SHIFT_CH5_LOW_TH)
+#define BIT_CLEAR_CH5_LOW_TH(x) ((x) & (~BITS_CH5_LOW_TH))
+#define BIT_GET_CH5_LOW_TH(x)                                                  \
+	(((x) >> BIT_SHIFT_CH5_LOW_TH) & BIT_MASK_CH5_LOW_TH)
+#define BIT_SET_CH5_LOW_TH(x, v) (BIT_CLEAR_CH5_LOW_TH(x) | BIT_CH5_LOW_TH(v))
+
+/* 2 REG_TXPAGE_INT_CTRL_6			(Offset 0x3218) */
+
+#define BIT_CH6_INT_EN BIT(31)
+
+#define BIT_SHIFT_CH6_HIGH_TH 16
+#define BIT_MASK_CH6_HIGH_TH 0xfff
+#define BIT_CH6_HIGH_TH(x)                                                     \
+	(((x) & BIT_MASK_CH6_HIGH_TH) << BIT_SHIFT_CH6_HIGH_TH)
+#define BITS_CH6_HIGH_TH (BIT_MASK_CH6_HIGH_TH << BIT_SHIFT_CH6_HIGH_TH)
+#define BIT_CLEAR_CH6_HIGH_TH(x) ((x) & (~BITS_CH6_HIGH_TH))
+#define BIT_GET_CH6_HIGH_TH(x)                                                 \
+	(((x) >> BIT_SHIFT_CH6_HIGH_TH) & BIT_MASK_CH6_HIGH_TH)
+#define BIT_SET_CH6_HIGH_TH(x, v)                                              \
+	(BIT_CLEAR_CH6_HIGH_TH(x) | BIT_CH6_HIGH_TH(v))
+
+#define BIT_SHIFT_CH6_LOW_TH 0
+#define BIT_MASK_CH6_LOW_TH 0xfff
+#define BIT_CH6_LOW_TH(x) (((x) & BIT_MASK_CH6_LOW_TH) << BIT_SHIFT_CH6_LOW_TH)
+#define BITS_CH6_LOW_TH (BIT_MASK_CH6_LOW_TH << BIT_SHIFT_CH6_LOW_TH)
+#define BIT_CLEAR_CH6_LOW_TH(x) ((x) & (~BITS_CH6_LOW_TH))
+#define BIT_GET_CH6_LOW_TH(x)                                                  \
+	(((x) >> BIT_SHIFT_CH6_LOW_TH) & BIT_MASK_CH6_LOW_TH)
+#define BIT_SET_CH6_LOW_TH(x, v) (BIT_CLEAR_CH6_LOW_TH(x) | BIT_CH6_LOW_TH(v))
+
+/* 2 REG_TXPAGE_INT_CTRL_7			(Offset 0x321C) */
+
+#define BIT_CH7_INT_EN BIT(31)
+
+#define BIT_SHIFT_CH7_HIGH_TH 16
+#define BIT_MASK_CH7_HIGH_TH 0xfff
+#define BIT_CH7_HIGH_TH(x)                                                     \
+	(((x) & BIT_MASK_CH7_HIGH_TH) << BIT_SHIFT_CH7_HIGH_TH)
+#define BITS_CH7_HIGH_TH (BIT_MASK_CH7_HIGH_TH << BIT_SHIFT_CH7_HIGH_TH)
+#define BIT_CLEAR_CH7_HIGH_TH(x) ((x) & (~BITS_CH7_HIGH_TH))
+#define BIT_GET_CH7_HIGH_TH(x)                                                 \
+	(((x) >> BIT_SHIFT_CH7_HIGH_TH) & BIT_MASK_CH7_HIGH_TH)
+#define BIT_SET_CH7_HIGH_TH(x, v)                                              \
+	(BIT_CLEAR_CH7_HIGH_TH(x) | BIT_CH7_HIGH_TH(v))
+
+#define BIT_SHIFT_CH7_LOW_TH 0
+#define BIT_MASK_CH7_LOW_TH 0xfff
+#define BIT_CH7_LOW_TH(x) (((x) & BIT_MASK_CH7_LOW_TH) << BIT_SHIFT_CH7_LOW_TH)
+#define BITS_CH7_LOW_TH (BIT_MASK_CH7_LOW_TH << BIT_SHIFT_CH7_LOW_TH)
+#define BIT_CLEAR_CH7_LOW_TH(x) ((x) & (~BITS_CH7_LOW_TH))
+#define BIT_GET_CH7_LOW_TH(x)                                                  \
+	(((x) >> BIT_SHIFT_CH7_LOW_TH) & BIT_MASK_CH7_LOW_TH)
+#define BIT_SET_CH7_LOW_TH(x, v) (BIT_CLEAR_CH7_LOW_TH(x) | BIT_CH7_LOW_TH(v))
+
+/* 2 REG_TXPAGE_INT_CTRL_8			(Offset 0x3220) */
+
+#define BIT_CH8_INT_EN BIT(31)
+
+#define BIT_SHIFT_CH8_HIGH_TH 16
+#define BIT_MASK_CH8_HIGH_TH 0xfff
+#define BIT_CH8_HIGH_TH(x)                                                     \
+	(((x) & BIT_MASK_CH8_HIGH_TH) << BIT_SHIFT_CH8_HIGH_TH)
+#define BITS_CH8_HIGH_TH (BIT_MASK_CH8_HIGH_TH << BIT_SHIFT_CH8_HIGH_TH)
+#define BIT_CLEAR_CH8_HIGH_TH(x) ((x) & (~BITS_CH8_HIGH_TH))
+#define BIT_GET_CH8_HIGH_TH(x)                                                 \
+	(((x) >> BIT_SHIFT_CH8_HIGH_TH) & BIT_MASK_CH8_HIGH_TH)
+#define BIT_SET_CH8_HIGH_TH(x, v)                                              \
+	(BIT_CLEAR_CH8_HIGH_TH(x) | BIT_CH8_HIGH_TH(v))
+
+#define BIT_SHIFT_CH8_LOW_TH 0
+#define BIT_MASK_CH8_LOW_TH 0xfff
+#define BIT_CH8_LOW_TH(x) (((x) & BIT_MASK_CH8_LOW_TH) << BIT_SHIFT_CH8_LOW_TH)
+#define BITS_CH8_LOW_TH (BIT_MASK_CH8_LOW_TH << BIT_SHIFT_CH8_LOW_TH)
+#define BIT_CLEAR_CH8_LOW_TH(x) ((x) & (~BITS_CH8_LOW_TH))
+#define BIT_GET_CH8_LOW_TH(x)                                                  \
+	(((x) >> BIT_SHIFT_CH8_LOW_TH) & BIT_MASK_CH8_LOW_TH)
+#define BIT_SET_CH8_LOW_TH(x, v) (BIT_CLEAR_CH8_LOW_TH(x) | BIT_CH8_LOW_TH(v))
+
+/* 2 REG_TXPAGE_INT_CTRL_9			(Offset 0x3224) */
+
+#define BIT_CH9_INT_EN BIT(31)
+
+#define BIT_SHIFT_CH9_HIGH_TH 16
+#define BIT_MASK_CH9_HIGH_TH 0xfff
+#define BIT_CH9_HIGH_TH(x)                                                     \
+	(((x) & BIT_MASK_CH9_HIGH_TH) << BIT_SHIFT_CH9_HIGH_TH)
+#define BITS_CH9_HIGH_TH (BIT_MASK_CH9_HIGH_TH << BIT_SHIFT_CH9_HIGH_TH)
+#define BIT_CLEAR_CH9_HIGH_TH(x) ((x) & (~BITS_CH9_HIGH_TH))
+#define BIT_GET_CH9_HIGH_TH(x)                                                 \
+	(((x) >> BIT_SHIFT_CH9_HIGH_TH) & BIT_MASK_CH9_HIGH_TH)
+#define BIT_SET_CH9_HIGH_TH(x, v)                                              \
+	(BIT_CLEAR_CH9_HIGH_TH(x) | BIT_CH9_HIGH_TH(v))
+
+#define BIT_SHIFT_CH9_LOW_TH 0
+#define BIT_MASK_CH9_LOW_TH 0xfff
+#define BIT_CH9_LOW_TH(x) (((x) & BIT_MASK_CH9_LOW_TH) << BIT_SHIFT_CH9_LOW_TH)
+#define BITS_CH9_LOW_TH (BIT_MASK_CH9_LOW_TH << BIT_SHIFT_CH9_LOW_TH)
+#define BIT_CLEAR_CH9_LOW_TH(x) ((x) & (~BITS_CH9_LOW_TH))
+#define BIT_GET_CH9_LOW_TH(x)                                                  \
+	(((x) >> BIT_SHIFT_CH9_LOW_TH) & BIT_MASK_CH9_LOW_TH)
+#define BIT_SET_CH9_LOW_TH(x, v) (BIT_CLEAR_CH9_LOW_TH(x) | BIT_CH9_LOW_TH(v))
+
+/* 2 REG_TXPAGE_INT_CTRL_10			(Offset 0x3228) */
+
+#define BIT_CH10_INT_EN BIT(31)
+
+#define BIT_SHIFT_CH10_HIGH_TH 16
+#define BIT_MASK_CH10_HIGH_TH 0xfff
+#define BIT_CH10_HIGH_TH(x)                                                    \
+	(((x) & BIT_MASK_CH10_HIGH_TH) << BIT_SHIFT_CH10_HIGH_TH)
+#define BITS_CH10_HIGH_TH (BIT_MASK_CH10_HIGH_TH << BIT_SHIFT_CH10_HIGH_TH)
+#define BIT_CLEAR_CH10_HIGH_TH(x) ((x) & (~BITS_CH10_HIGH_TH))
+#define BIT_GET_CH10_HIGH_TH(x)                                                \
+	(((x) >> BIT_SHIFT_CH10_HIGH_TH) & BIT_MASK_CH10_HIGH_TH)
+#define BIT_SET_CH10_HIGH_TH(x, v)                                             \
+	(BIT_CLEAR_CH10_HIGH_TH(x) | BIT_CH10_HIGH_TH(v))
+
+#define BIT_SHIFT_CH10_LOW_TH 0
+#define BIT_MASK_CH10_LOW_TH 0xfff
+#define BIT_CH10_LOW_TH(x)                                                     \
+	(((x) & BIT_MASK_CH10_LOW_TH) << BIT_SHIFT_CH10_LOW_TH)
+#define BITS_CH10_LOW_TH (BIT_MASK_CH10_LOW_TH << BIT_SHIFT_CH10_LOW_TH)
+#define BIT_CLEAR_CH10_LOW_TH(x) ((x) & (~BITS_CH10_LOW_TH))
+#define BIT_GET_CH10_LOW_TH(x)                                                 \
+	(((x) >> BIT_SHIFT_CH10_LOW_TH) & BIT_MASK_CH10_LOW_TH)
+#define BIT_SET_CH10_LOW_TH(x, v)                                              \
+	(BIT_CLEAR_CH10_LOW_TH(x) | BIT_CH10_LOW_TH(v))
+
+/* 2 REG_TXPAGE_INT_CTRL_11			(Offset 0x322C) */
+
+#define BIT_CH11_INT_EN BIT(31)
+
+#define BIT_SHIFT_CH11_HIGH_TH 16
+#define BIT_MASK_CH11_HIGH_TH 0xfff
+#define BIT_CH11_HIGH_TH(x)                                                    \
+	(((x) & BIT_MASK_CH11_HIGH_TH) << BIT_SHIFT_CH11_HIGH_TH)
+#define BITS_CH11_HIGH_TH (BIT_MASK_CH11_HIGH_TH << BIT_SHIFT_CH11_HIGH_TH)
+#define BIT_CLEAR_CH11_HIGH_TH(x) ((x) & (~BITS_CH11_HIGH_TH))
+#define BIT_GET_CH11_HIGH_TH(x)                                                \
+	(((x) >> BIT_SHIFT_CH11_HIGH_TH) & BIT_MASK_CH11_HIGH_TH)
+#define BIT_SET_CH11_HIGH_TH(x, v)                                             \
+	(BIT_CLEAR_CH11_HIGH_TH(x) | BIT_CH11_HIGH_TH(v))
+
+#define BIT_SHIFT_CH11_LOW_TH 0
+#define BIT_MASK_CH11_LOW_TH 0xfff
+#define BIT_CH11_LOW_TH(x)                                                     \
+	(((x) & BIT_MASK_CH11_LOW_TH) << BIT_SHIFT_CH11_LOW_TH)
+#define BITS_CH11_LOW_TH (BIT_MASK_CH11_LOW_TH << BIT_SHIFT_CH11_LOW_TH)
+#define BIT_CLEAR_CH11_LOW_TH(x) ((x) & (~BITS_CH11_LOW_TH))
+#define BIT_GET_CH11_LOW_TH(x)                                                 \
+	(((x) >> BIT_SHIFT_CH11_LOW_TH) & BIT_MASK_CH11_LOW_TH)
+#define BIT_SET_CH11_LOW_TH(x, v)                                              \
+	(BIT_CLEAR_CH11_LOW_TH(x) | BIT_CH11_LOW_TH(v))
+
+/* 2 REG_TXPAGE_INT_CTRL_12			(Offset 0x3230) */
+
+#define BIT_CH12_INT_EN BIT(31)
+
+#define BIT_SHIFT_CH12_HIGH_TH 16
+#define BIT_MASK_CH12_HIGH_TH 0xfff
+#define BIT_CH12_HIGH_TH(x)                                                    \
+	(((x) & BIT_MASK_CH12_HIGH_TH) << BIT_SHIFT_CH12_HIGH_TH)
+#define BITS_CH12_HIGH_TH (BIT_MASK_CH12_HIGH_TH << BIT_SHIFT_CH12_HIGH_TH)
+#define BIT_CLEAR_CH12_HIGH_TH(x) ((x) & (~BITS_CH12_HIGH_TH))
+#define BIT_GET_CH12_HIGH_TH(x)                                                \
+	(((x) >> BIT_SHIFT_CH12_HIGH_TH) & BIT_MASK_CH12_HIGH_TH)
+#define BIT_SET_CH12_HIGH_TH(x, v)                                             \
+	(BIT_CLEAR_CH12_HIGH_TH(x) | BIT_CH12_HIGH_TH(v))
+
+#define BIT_SHIFT_CH12_LOW_TH 0
+#define BIT_MASK_CH12_LOW_TH 0xfff
+#define BIT_CH12_LOW_TH(x)                                                     \
+	(((x) & BIT_MASK_CH12_LOW_TH) << BIT_SHIFT_CH12_LOW_TH)
+#define BITS_CH12_LOW_TH (BIT_MASK_CH12_LOW_TH << BIT_SHIFT_CH12_LOW_TH)
+#define BIT_CLEAR_CH12_LOW_TH(x) ((x) & (~BITS_CH12_LOW_TH))
+#define BIT_GET_CH12_LOW_TH(x)                                                 \
+	(((x) >> BIT_SHIFT_CH12_LOW_TH) & BIT_MASK_CH12_LOW_TH)
+#define BIT_SET_CH12_LOW_TH(x, v)                                              \
+	(BIT_CLEAR_CH12_LOW_TH(x) | BIT_CH12_LOW_TH(v))
+
+/* 2 REG_TXPAGE_INT_CTRL_13			(Offset 0x3234) */
+
+#define BIT_CH13_INT_EN BIT(31)
+
+#define BIT_SHIFT_CH13_HIGH_TH 16
+#define BIT_MASK_CH13_HIGH_TH 0xfff
+#define BIT_CH13_HIGH_TH(x)                                                    \
+	(((x) & BIT_MASK_CH13_HIGH_TH) << BIT_SHIFT_CH13_HIGH_TH)
+#define BITS_CH13_HIGH_TH (BIT_MASK_CH13_HIGH_TH << BIT_SHIFT_CH13_HIGH_TH)
+#define BIT_CLEAR_CH13_HIGH_TH(x) ((x) & (~BITS_CH13_HIGH_TH))
+#define BIT_GET_CH13_HIGH_TH(x)                                                \
+	(((x) >> BIT_SHIFT_CH13_HIGH_TH) & BIT_MASK_CH13_HIGH_TH)
+#define BIT_SET_CH13_HIGH_TH(x, v)                                             \
+	(BIT_CLEAR_CH13_HIGH_TH(x) | BIT_CH13_HIGH_TH(v))
+
+#define BIT_SHIFT_CH13_LOW_TH 0
+#define BIT_MASK_CH13_LOW_TH 0xfff
+#define BIT_CH13_LOW_TH(x)                                                     \
+	(((x) & BIT_MASK_CH13_LOW_TH) << BIT_SHIFT_CH13_LOW_TH)
+#define BITS_CH13_LOW_TH (BIT_MASK_CH13_LOW_TH << BIT_SHIFT_CH13_LOW_TH)
+#define BIT_CLEAR_CH13_LOW_TH(x) ((x) & (~BITS_CH13_LOW_TH))
+#define BIT_GET_CH13_LOW_TH(x)                                                 \
+	(((x) >> BIT_SHIFT_CH13_LOW_TH) & BIT_MASK_CH13_LOW_TH)
+#define BIT_SET_CH13_LOW_TH(x, v)                                              \
+	(BIT_CLEAR_CH13_LOW_TH(x) | BIT_CH13_LOW_TH(v))
+
+/* 2 REG_TXPAGE_INT_CTRL_14			(Offset 0x3238) */
+
+#define BIT_CH14_INT_EN BIT(31)
+
+#define BIT_SHIFT_CH14_HIGH_TH 16
+#define BIT_MASK_CH14_HIGH_TH 0xfff
+#define BIT_CH14_HIGH_TH(x)                                                    \
+	(((x) & BIT_MASK_CH14_HIGH_TH) << BIT_SHIFT_CH14_HIGH_TH)
+#define BITS_CH14_HIGH_TH (BIT_MASK_CH14_HIGH_TH << BIT_SHIFT_CH14_HIGH_TH)
+#define BIT_CLEAR_CH14_HIGH_TH(x) ((x) & (~BITS_CH14_HIGH_TH))
+#define BIT_GET_CH14_HIGH_TH(x)                                                \
+	(((x) >> BIT_SHIFT_CH14_HIGH_TH) & BIT_MASK_CH14_HIGH_TH)
+#define BIT_SET_CH14_HIGH_TH(x, v)                                             \
+	(BIT_CLEAR_CH14_HIGH_TH(x) | BIT_CH14_HIGH_TH(v))
+
+#define BIT_SHIFT_CH14_LOW_TH 0
+#define BIT_MASK_CH14_LOW_TH 0xfff
+#define BIT_CH14_LOW_TH(x)                                                     \
+	(((x) & BIT_MASK_CH14_LOW_TH) << BIT_SHIFT_CH14_LOW_TH)
+#define BITS_CH14_LOW_TH (BIT_MASK_CH14_LOW_TH << BIT_SHIFT_CH14_LOW_TH)
+#define BIT_CLEAR_CH14_LOW_TH(x) ((x) & (~BITS_CH14_LOW_TH))
+#define BIT_GET_CH14_LOW_TH(x)                                                 \
+	(((x) >> BIT_SHIFT_CH14_LOW_TH) & BIT_MASK_CH14_LOW_TH)
+#define BIT_SET_CH14_LOW_TH(x, v)                                              \
+	(BIT_CLEAR_CH14_LOW_TH(x) | BIT_CH14_LOW_TH(v))
+
+/* 2 REG_TXPAGE_INT_CTRL_15			(Offset 0x323C) */
+
+#define BIT_CH15_INT_EN BIT(31)
+
+#define BIT_SHIFT_CH15_HIGH_TH 16
+#define BIT_MASK_CH15_HIGH_TH 0xfff
+#define BIT_CH15_HIGH_TH(x)                                                    \
+	(((x) & BIT_MASK_CH15_HIGH_TH) << BIT_SHIFT_CH15_HIGH_TH)
+#define BITS_CH15_HIGH_TH (BIT_MASK_CH15_HIGH_TH << BIT_SHIFT_CH15_HIGH_TH)
+#define BIT_CLEAR_CH15_HIGH_TH(x) ((x) & (~BITS_CH15_HIGH_TH))
+#define BIT_GET_CH15_HIGH_TH(x)                                                \
+	(((x) >> BIT_SHIFT_CH15_HIGH_TH) & BIT_MASK_CH15_HIGH_TH)
+#define BIT_SET_CH15_HIGH_TH(x, v)                                             \
+	(BIT_CLEAR_CH15_HIGH_TH(x) | BIT_CH15_HIGH_TH(v))
+
+#define BIT_SHIFT_CH15_LOW_TH 0
+#define BIT_MASK_CH15_LOW_TH 0xfff
+#define BIT_CH15_LOW_TH(x)                                                     \
+	(((x) & BIT_MASK_CH15_LOW_TH) << BIT_SHIFT_CH15_LOW_TH)
+#define BITS_CH15_LOW_TH (BIT_MASK_CH15_LOW_TH << BIT_SHIFT_CH15_LOW_TH)
+#define BIT_CLEAR_CH15_LOW_TH(x) ((x) & (~BITS_CH15_LOW_TH))
+#define BIT_GET_CH15_LOW_TH(x)                                                 \
+	(((x) >> BIT_SHIFT_CH15_LOW_TH) & BIT_MASK_CH15_LOW_TH)
+#define BIT_SET_CH15_LOW_TH(x, v)                                              \
+	(BIT_CLEAR_CH15_LOW_TH(x) | BIT_CH15_LOW_TH(v))
+
+/* 2 REG_TXPAGE_INT_CTRL_16			(Offset 0x3240) */
+
+#define BIT_CH16_INT_EN BIT(31)
+
+#define BIT_SHIFT_CH16_HIGH_TH 16
+#define BIT_MASK_CH16_HIGH_TH 0xfff
+#define BIT_CH16_HIGH_TH(x)                                                    \
+	(((x) & BIT_MASK_CH16_HIGH_TH) << BIT_SHIFT_CH16_HIGH_TH)
+#define BITS_CH16_HIGH_TH (BIT_MASK_CH16_HIGH_TH << BIT_SHIFT_CH16_HIGH_TH)
+#define BIT_CLEAR_CH16_HIGH_TH(x) ((x) & (~BITS_CH16_HIGH_TH))
+#define BIT_GET_CH16_HIGH_TH(x)                                                \
+	(((x) >> BIT_SHIFT_CH16_HIGH_TH) & BIT_MASK_CH16_HIGH_TH)
+#define BIT_SET_CH16_HIGH_TH(x, v)                                             \
+	(BIT_CLEAR_CH16_HIGH_TH(x) | BIT_CH16_HIGH_TH(v))
+
+#define BIT_SHIFT_CH16_LOW_TH 0
+#define BIT_MASK_CH16_LOW_TH 0xfff
+#define BIT_CH16_LOW_TH(x)                                                     \
+	(((x) & BIT_MASK_CH16_LOW_TH) << BIT_SHIFT_CH16_LOW_TH)
+#define BITS_CH16_LOW_TH (BIT_MASK_CH16_LOW_TH << BIT_SHIFT_CH16_LOW_TH)
+#define BIT_CLEAR_CH16_LOW_TH(x) ((x) & (~BITS_CH16_LOW_TH))
+#define BIT_GET_CH16_LOW_TH(x)                                                 \
+	(((x) >> BIT_SHIFT_CH16_LOW_TH) & BIT_MASK_CH16_LOW_TH)
+#define BIT_SET_CH16_LOW_TH(x, v)                                              \
+	(BIT_CLEAR_CH16_LOW_TH(x) | BIT_CH16_LOW_TH(v))
+
+/* 2 REG_ACH4_TXBD_IDX			(Offset 0x3340) */
+
+#define BIT_SHIFT_ACH4_HW_IDX 16
+#define BIT_MASK_ACH4_HW_IDX 0xfff
+#define BIT_ACH4_HW_IDX(x)                                                     \
+	(((x) & BIT_MASK_ACH4_HW_IDX) << BIT_SHIFT_ACH4_HW_IDX)
+#define BITS_ACH4_HW_IDX (BIT_MASK_ACH4_HW_IDX << BIT_SHIFT_ACH4_HW_IDX)
+#define BIT_CLEAR_ACH4_HW_IDX(x) ((x) & (~BITS_ACH4_HW_IDX))
+#define BIT_GET_ACH4_HW_IDX(x)                                                 \
+	(((x) >> BIT_SHIFT_ACH4_HW_IDX) & BIT_MASK_ACH4_HW_IDX)
+#define BIT_SET_ACH4_HW_IDX(x, v)                                              \
+	(BIT_CLEAR_ACH4_HW_IDX(x) | BIT_ACH4_HW_IDX(v))
+
+#define BIT_SHIFT_ACH4_HOST_IDX 0
+#define BIT_MASK_ACH4_HOST_IDX 0xfff
+#define BIT_ACH4_HOST_IDX(x)                                                   \
+	(((x) & BIT_MASK_ACH4_HOST_IDX) << BIT_SHIFT_ACH4_HOST_IDX)
+#define BITS_ACH4_HOST_IDX (BIT_MASK_ACH4_HOST_IDX << BIT_SHIFT_ACH4_HOST_IDX)
+#define BIT_CLEAR_ACH4_HOST_IDX(x) ((x) & (~BITS_ACH4_HOST_IDX))
+#define BIT_GET_ACH4_HOST_IDX(x)                                               \
+	(((x) >> BIT_SHIFT_ACH4_HOST_IDX) & BIT_MASK_ACH4_HOST_IDX)
+#define BIT_SET_ACH4_HOST_IDX(x, v)                                            \
+	(BIT_CLEAR_ACH4_HOST_IDX(x) | BIT_ACH4_HOST_IDX(v))
+
+/* 2 REG_ACH5_TXBD_IDX			(Offset 0x3344) */
+
+#define BIT_SHIFT_ACH5_HW_IDX 16
+#define BIT_MASK_ACH5_HW_IDX 0xfff
+#define BIT_ACH5_HW_IDX(x)                                                     \
+	(((x) & BIT_MASK_ACH5_HW_IDX) << BIT_SHIFT_ACH5_HW_IDX)
+#define BITS_ACH5_HW_IDX (BIT_MASK_ACH5_HW_IDX << BIT_SHIFT_ACH5_HW_IDX)
+#define BIT_CLEAR_ACH5_HW_IDX(x) ((x) & (~BITS_ACH5_HW_IDX))
+#define BIT_GET_ACH5_HW_IDX(x)                                                 \
+	(((x) >> BIT_SHIFT_ACH5_HW_IDX) & BIT_MASK_ACH5_HW_IDX)
+#define BIT_SET_ACH5_HW_IDX(x, v)                                              \
+	(BIT_CLEAR_ACH5_HW_IDX(x) | BIT_ACH5_HW_IDX(v))
+
+#define BIT_SHIFT_ACH5_HOST_IDX 0
+#define BIT_MASK_ACH5_HOST_IDX 0xfff
+#define BIT_ACH5_HOST_IDX(x)                                                   \
+	(((x) & BIT_MASK_ACH5_HOST_IDX) << BIT_SHIFT_ACH5_HOST_IDX)
+#define BITS_ACH5_HOST_IDX (BIT_MASK_ACH5_HOST_IDX << BIT_SHIFT_ACH5_HOST_IDX)
+#define BIT_CLEAR_ACH5_HOST_IDX(x) ((x) & (~BITS_ACH5_HOST_IDX))
+#define BIT_GET_ACH5_HOST_IDX(x)                                               \
+	(((x) >> BIT_SHIFT_ACH5_HOST_IDX) & BIT_MASK_ACH5_HOST_IDX)
+#define BIT_SET_ACH5_HOST_IDX(x, v)                                            \
+	(BIT_CLEAR_ACH5_HOST_IDX(x) | BIT_ACH5_HOST_IDX(v))
+
+/* 2 REG_ACH6_TXBD_IDX			(Offset 0x3348) */
+
+#define BIT_SHIFT_ACH6_HW_IDX 16
+#define BIT_MASK_ACH6_HW_IDX 0xfff
+#define BIT_ACH6_HW_IDX(x)                                                     \
+	(((x) & BIT_MASK_ACH6_HW_IDX) << BIT_SHIFT_ACH6_HW_IDX)
+#define BITS_ACH6_HW_IDX (BIT_MASK_ACH6_HW_IDX << BIT_SHIFT_ACH6_HW_IDX)
+#define BIT_CLEAR_ACH6_HW_IDX(x) ((x) & (~BITS_ACH6_HW_IDX))
+#define BIT_GET_ACH6_HW_IDX(x)                                                 \
+	(((x) >> BIT_SHIFT_ACH6_HW_IDX) & BIT_MASK_ACH6_HW_IDX)
+#define BIT_SET_ACH6_HW_IDX(x, v)                                              \
+	(BIT_CLEAR_ACH6_HW_IDX(x) | BIT_ACH6_HW_IDX(v))
+
+#define BIT_SHIFT_ACH6_HOST_IDX 0
+#define BIT_MASK_ACH6_HOST_IDX 0xfff
+#define BIT_ACH6_HOST_IDX(x)                                                   \
+	(((x) & BIT_MASK_ACH6_HOST_IDX) << BIT_SHIFT_ACH6_HOST_IDX)
+#define BITS_ACH6_HOST_IDX (BIT_MASK_ACH6_HOST_IDX << BIT_SHIFT_ACH6_HOST_IDX)
+#define BIT_CLEAR_ACH6_HOST_IDX(x) ((x) & (~BITS_ACH6_HOST_IDX))
+#define BIT_GET_ACH6_HOST_IDX(x)                                               \
+	(((x) >> BIT_SHIFT_ACH6_HOST_IDX) & BIT_MASK_ACH6_HOST_IDX)
+#define BIT_SET_ACH6_HOST_IDX(x, v)                                            \
+	(BIT_CLEAR_ACH6_HOST_IDX(x) | BIT_ACH6_HOST_IDX(v))
+
+/* 2 REG_ACH7_TXBD_IDX			(Offset 0x334C) */
+
+#define BIT_SHIFT_ACH7_HW_IDX 16
+#define BIT_MASK_ACH7_HW_IDX 0xfff
+#define BIT_ACH7_HW_IDX(x)                                                     \
+	(((x) & BIT_MASK_ACH7_HW_IDX) << BIT_SHIFT_ACH7_HW_IDX)
+#define BITS_ACH7_HW_IDX (BIT_MASK_ACH7_HW_IDX << BIT_SHIFT_ACH7_HW_IDX)
+#define BIT_CLEAR_ACH7_HW_IDX(x) ((x) & (~BITS_ACH7_HW_IDX))
+#define BIT_GET_ACH7_HW_IDX(x)                                                 \
+	(((x) >> BIT_SHIFT_ACH7_HW_IDX) & BIT_MASK_ACH7_HW_IDX)
+#define BIT_SET_ACH7_HW_IDX(x, v)                                              \
+	(BIT_CLEAR_ACH7_HW_IDX(x) | BIT_ACH7_HW_IDX(v))
+
+#define BIT_SHIFT_ACH7_HOST_IDX 0
+#define BIT_MASK_ACH7_HOST_IDX 0xfff
+#define BIT_ACH7_HOST_IDX(x)                                                   \
+	(((x) & BIT_MASK_ACH7_HOST_IDX) << BIT_SHIFT_ACH7_HOST_IDX)
+#define BITS_ACH7_HOST_IDX (BIT_MASK_ACH7_HOST_IDX << BIT_SHIFT_ACH7_HOST_IDX)
+#define BIT_CLEAR_ACH7_HOST_IDX(x) ((x) & (~BITS_ACH7_HOST_IDX))
+#define BIT_GET_ACH7_HOST_IDX(x)                                               \
+	(((x) >> BIT_SHIFT_ACH7_HOST_IDX) & BIT_MASK_ACH7_HOST_IDX)
+#define BIT_SET_ACH7_HOST_IDX(x, v)                                            \
+	(BIT_CLEAR_ACH7_HOST_IDX(x) | BIT_ACH7_HOST_IDX(v))
+
+/* 2 REG_ACH8_TXBD_IDX			(Offset 0x3350) */
+
+#define BIT_SHIFT_ACH8_HW_IDX 16
+#define BIT_MASK_ACH8_HW_IDX 0xfff
+#define BIT_ACH8_HW_IDX(x)                                                     \
+	(((x) & BIT_MASK_ACH8_HW_IDX) << BIT_SHIFT_ACH8_HW_IDX)
+#define BITS_ACH8_HW_IDX (BIT_MASK_ACH8_HW_IDX << BIT_SHIFT_ACH8_HW_IDX)
+#define BIT_CLEAR_ACH8_HW_IDX(x) ((x) & (~BITS_ACH8_HW_IDX))
+#define BIT_GET_ACH8_HW_IDX(x)                                                 \
+	(((x) >> BIT_SHIFT_ACH8_HW_IDX) & BIT_MASK_ACH8_HW_IDX)
+#define BIT_SET_ACH8_HW_IDX(x, v)                                              \
+	(BIT_CLEAR_ACH8_HW_IDX(x) | BIT_ACH8_HW_IDX(v))
+
+#define BIT_SHIFT_ACH8_HOST_IDX 0
+#define BIT_MASK_ACH8_HOST_IDX 0xfff
+#define BIT_ACH8_HOST_IDX(x)                                                   \
+	(((x) & BIT_MASK_ACH8_HOST_IDX) << BIT_SHIFT_ACH8_HOST_IDX)
+#define BITS_ACH8_HOST_IDX (BIT_MASK_ACH8_HOST_IDX << BIT_SHIFT_ACH8_HOST_IDX)
+#define BIT_CLEAR_ACH8_HOST_IDX(x) ((x) & (~BITS_ACH8_HOST_IDX))
+#define BIT_GET_ACH8_HOST_IDX(x)                                               \
+	(((x) >> BIT_SHIFT_ACH8_HOST_IDX) & BIT_MASK_ACH8_HOST_IDX)
+#define BIT_SET_ACH8_HOST_IDX(x, v)                                            \
+	(BIT_CLEAR_ACH8_HOST_IDX(x) | BIT_ACH8_HOST_IDX(v))
+
+/* 2 REG_ACH9_TXBD_IDX			(Offset 0x3354) */
+
+#define BIT_SHIFT_ACH9_HW_IDX 16
+#define BIT_MASK_ACH9_HW_IDX 0xfff
+#define BIT_ACH9_HW_IDX(x)                                                     \
+	(((x) & BIT_MASK_ACH9_HW_IDX) << BIT_SHIFT_ACH9_HW_IDX)
+#define BITS_ACH9_HW_IDX (BIT_MASK_ACH9_HW_IDX << BIT_SHIFT_ACH9_HW_IDX)
+#define BIT_CLEAR_ACH9_HW_IDX(x) ((x) & (~BITS_ACH9_HW_IDX))
+#define BIT_GET_ACH9_HW_IDX(x)                                                 \
+	(((x) >> BIT_SHIFT_ACH9_HW_IDX) & BIT_MASK_ACH9_HW_IDX)
+#define BIT_SET_ACH9_HW_IDX(x, v)                                              \
+	(BIT_CLEAR_ACH9_HW_IDX(x) | BIT_ACH9_HW_IDX(v))
+
+#define BIT_SHIFT_ACH9_HOST_IDX 0
+#define BIT_MASK_ACH9_HOST_IDX 0xfff
+#define BIT_ACH9_HOST_IDX(x)                                                   \
+	(((x) & BIT_MASK_ACH9_HOST_IDX) << BIT_SHIFT_ACH9_HOST_IDX)
+#define BITS_ACH9_HOST_IDX (BIT_MASK_ACH9_HOST_IDX << BIT_SHIFT_ACH9_HOST_IDX)
+#define BIT_CLEAR_ACH9_HOST_IDX(x) ((x) & (~BITS_ACH9_HOST_IDX))
+#define BIT_GET_ACH9_HOST_IDX(x)                                               \
+	(((x) >> BIT_SHIFT_ACH9_HOST_IDX) & BIT_MASK_ACH9_HOST_IDX)
+#define BIT_SET_ACH9_HOST_IDX(x, v)                                            \
+	(BIT_CLEAR_ACH9_HOST_IDX(x) | BIT_ACH9_HOST_IDX(v))
+
+/* 2 REG_ACH10_TXBD_IDX			(Offset 0x3358) */
+
+#define BIT_SHIFT_ACH10_HW_IDX 16
+#define BIT_MASK_ACH10_HW_IDX 0xfff
+#define BIT_ACH10_HW_IDX(x)                                                    \
+	(((x) & BIT_MASK_ACH10_HW_IDX) << BIT_SHIFT_ACH10_HW_IDX)
+#define BITS_ACH10_HW_IDX (BIT_MASK_ACH10_HW_IDX << BIT_SHIFT_ACH10_HW_IDX)
+#define BIT_CLEAR_ACH10_HW_IDX(x) ((x) & (~BITS_ACH10_HW_IDX))
+#define BIT_GET_ACH10_HW_IDX(x)                                                \
+	(((x) >> BIT_SHIFT_ACH10_HW_IDX) & BIT_MASK_ACH10_HW_IDX)
+#define BIT_SET_ACH10_HW_IDX(x, v)                                             \
+	(BIT_CLEAR_ACH10_HW_IDX(x) | BIT_ACH10_HW_IDX(v))
+
+#define BIT_SHIFT_ACH10_HOST_IDX 0
+#define BIT_MASK_ACH10_HOST_IDX 0xfff
+#define BIT_ACH10_HOST_IDX(x)                                                  \
+	(((x) & BIT_MASK_ACH10_HOST_IDX) << BIT_SHIFT_ACH10_HOST_IDX)
+#define BITS_ACH10_HOST_IDX                                                    \
+	(BIT_MASK_ACH10_HOST_IDX << BIT_SHIFT_ACH10_HOST_IDX)
+#define BIT_CLEAR_ACH10_HOST_IDX(x) ((x) & (~BITS_ACH10_HOST_IDX))
+#define BIT_GET_ACH10_HOST_IDX(x)                                              \
+	(((x) >> BIT_SHIFT_ACH10_HOST_IDX) & BIT_MASK_ACH10_HOST_IDX)
+#define BIT_SET_ACH10_HOST_IDX(x, v)                                           \
+	(BIT_CLEAR_ACH10_HOST_IDX(x) | BIT_ACH10_HOST_IDX(v))
+
+/* 2 REG_ACH11_TXBD_IDX			(Offset 0x335C) */
+
+#define BIT_SHIFT_ACH11_HW_IDX 16
+#define BIT_MASK_ACH11_HW_IDX 0xfff
+#define BIT_ACH11_HW_IDX(x)                                                    \
+	(((x) & BIT_MASK_ACH11_HW_IDX) << BIT_SHIFT_ACH11_HW_IDX)
+#define BITS_ACH11_HW_IDX (BIT_MASK_ACH11_HW_IDX << BIT_SHIFT_ACH11_HW_IDX)
+#define BIT_CLEAR_ACH11_HW_IDX(x) ((x) & (~BITS_ACH11_HW_IDX))
+#define BIT_GET_ACH11_HW_IDX(x)                                                \
+	(((x) >> BIT_SHIFT_ACH11_HW_IDX) & BIT_MASK_ACH11_HW_IDX)
+#define BIT_SET_ACH11_HW_IDX(x, v)                                             \
+	(BIT_CLEAR_ACH11_HW_IDX(x) | BIT_ACH11_HW_IDX(v))
+
+#define BIT_SHIFT_ACH11_HOST_IDX 0
+#define BIT_MASK_ACH11_HOST_IDX 0xfff
+#define BIT_ACH11_HOST_IDX(x)                                                  \
+	(((x) & BIT_MASK_ACH11_HOST_IDX) << BIT_SHIFT_ACH11_HOST_IDX)
+#define BITS_ACH11_HOST_IDX                                                    \
+	(BIT_MASK_ACH11_HOST_IDX << BIT_SHIFT_ACH11_HOST_IDX)
+#define BIT_CLEAR_ACH11_HOST_IDX(x) ((x) & (~BITS_ACH11_HOST_IDX))
+#define BIT_GET_ACH11_HOST_IDX(x)                                              \
+	(((x) >> BIT_SHIFT_ACH11_HOST_IDX) & BIT_MASK_ACH11_HOST_IDX)
+#define BIT_SET_ACH11_HOST_IDX(x, v)                                           \
+	(BIT_CLEAR_ACH11_HOST_IDX(x) | BIT_ACH11_HOST_IDX(v))
+
+/* 2 REG_ACH12_TXBD_IDX			(Offset 0x3360) */
+
+#define BIT_SHIFT_ACH12_HW_IDX 16
+#define BIT_MASK_ACH12_HW_IDX 0xfff
+#define BIT_ACH12_HW_IDX(x)                                                    \
+	(((x) & BIT_MASK_ACH12_HW_IDX) << BIT_SHIFT_ACH12_HW_IDX)
+#define BITS_ACH12_HW_IDX (BIT_MASK_ACH12_HW_IDX << BIT_SHIFT_ACH12_HW_IDX)
+#define BIT_CLEAR_ACH12_HW_IDX(x) ((x) & (~BITS_ACH12_HW_IDX))
+#define BIT_GET_ACH12_HW_IDX(x)                                                \
+	(((x) >> BIT_SHIFT_ACH12_HW_IDX) & BIT_MASK_ACH12_HW_IDX)
+#define BIT_SET_ACH12_HW_IDX(x, v)                                             \
+	(BIT_CLEAR_ACH12_HW_IDX(x) | BIT_ACH12_HW_IDX(v))
+
+#define BIT_SHIFT_ACH12_HOST_IDX 0
+#define BIT_MASK_ACH12_HOST_IDX 0xfff
+#define BIT_ACH12_HOST_IDX(x)                                                  \
+	(((x) & BIT_MASK_ACH12_HOST_IDX) << BIT_SHIFT_ACH12_HOST_IDX)
+#define BITS_ACH12_HOST_IDX                                                    \
+	(BIT_MASK_ACH12_HOST_IDX << BIT_SHIFT_ACH12_HOST_IDX)
+#define BIT_CLEAR_ACH12_HOST_IDX(x) ((x) & (~BITS_ACH12_HOST_IDX))
+#define BIT_GET_ACH12_HOST_IDX(x)                                              \
+	(((x) >> BIT_SHIFT_ACH12_HOST_IDX) & BIT_MASK_ACH12_HOST_IDX)
+#define BIT_SET_ACH12_HOST_IDX(x, v)                                           \
+	(BIT_CLEAR_ACH12_HOST_IDX(x) | BIT_ACH12_HOST_IDX(v))
+
+/* 2 REG_ACH13_TXBD_IDX			(Offset 0x3364) */
+
+#define BIT_SHIFT_ACH13_HW_IDX 16
+#define BIT_MASK_ACH13_HW_IDX 0xfff
+#define BIT_ACH13_HW_IDX(x)                                                    \
+	(((x) & BIT_MASK_ACH13_HW_IDX) << BIT_SHIFT_ACH13_HW_IDX)
+#define BITS_ACH13_HW_IDX (BIT_MASK_ACH13_HW_IDX << BIT_SHIFT_ACH13_HW_IDX)
+#define BIT_CLEAR_ACH13_HW_IDX(x) ((x) & (~BITS_ACH13_HW_IDX))
+#define BIT_GET_ACH13_HW_IDX(x)                                                \
+	(((x) >> BIT_SHIFT_ACH13_HW_IDX) & BIT_MASK_ACH13_HW_IDX)
+#define BIT_SET_ACH13_HW_IDX(x, v)                                             \
+	(BIT_CLEAR_ACH13_HW_IDX(x) | BIT_ACH13_HW_IDX(v))
+
+#define BIT_SHIFT_ACH13_HOST_IDX 0
+#define BIT_MASK_ACH13_HOST_IDX 0xfff
+#define BIT_ACH13_HOST_IDX(x)                                                  \
+	(((x) & BIT_MASK_ACH13_HOST_IDX) << BIT_SHIFT_ACH13_HOST_IDX)
+#define BITS_ACH13_HOST_IDX                                                    \
+	(BIT_MASK_ACH13_HOST_IDX << BIT_SHIFT_ACH13_HOST_IDX)
+#define BIT_CLEAR_ACH13_HOST_IDX(x) ((x) & (~BITS_ACH13_HOST_IDX))
+#define BIT_GET_ACH13_HOST_IDX(x)                                              \
+	(((x) >> BIT_SHIFT_ACH13_HOST_IDX) & BIT_MASK_ACH13_HOST_IDX)
+#define BIT_SET_ACH13_HOST_IDX(x, v)                                           \
+	(BIT_CLEAR_ACH13_HOST_IDX(x) | BIT_ACH13_HOST_IDX(v))
+
+/* 2 REG_AC_CHANNEL0_WEIGHT			(Offset 0x3368) */
+
+#define BIT_SHIFT_AC_CHANNEL0_WEIGHT 0
+#define BIT_MASK_AC_CHANNEL0_WEIGHT 0xff
+#define BIT_AC_CHANNEL0_WEIGHT(x)                                              \
+	(((x) & BIT_MASK_AC_CHANNEL0_WEIGHT) << BIT_SHIFT_AC_CHANNEL0_WEIGHT)
+#define BITS_AC_CHANNEL0_WEIGHT                                                \
+	(BIT_MASK_AC_CHANNEL0_WEIGHT << BIT_SHIFT_AC_CHANNEL0_WEIGHT)
+#define BIT_CLEAR_AC_CHANNEL0_WEIGHT(x) ((x) & (~BITS_AC_CHANNEL0_WEIGHT))
+#define BIT_GET_AC_CHANNEL0_WEIGHT(x)                                          \
+	(((x) >> BIT_SHIFT_AC_CHANNEL0_WEIGHT) & BIT_MASK_AC_CHANNEL0_WEIGHT)
+#define BIT_SET_AC_CHANNEL0_WEIGHT(x, v)                                       \
+	(BIT_CLEAR_AC_CHANNEL0_WEIGHT(x) | BIT_AC_CHANNEL0_WEIGHT(v))
+
+/* 2 REG_AC_CHANNEL1_WEIGHT			(Offset 0x3369) */
+
+#define BIT_SHIFT_AC_CHANNEL1_WEIGHT 0
+#define BIT_MASK_AC_CHANNEL1_WEIGHT 0xff
+#define BIT_AC_CHANNEL1_WEIGHT(x)                                              \
+	(((x) & BIT_MASK_AC_CHANNEL1_WEIGHT) << BIT_SHIFT_AC_CHANNEL1_WEIGHT)
+#define BITS_AC_CHANNEL1_WEIGHT                                                \
+	(BIT_MASK_AC_CHANNEL1_WEIGHT << BIT_SHIFT_AC_CHANNEL1_WEIGHT)
+#define BIT_CLEAR_AC_CHANNEL1_WEIGHT(x) ((x) & (~BITS_AC_CHANNEL1_WEIGHT))
+#define BIT_GET_AC_CHANNEL1_WEIGHT(x)                                          \
+	(((x) >> BIT_SHIFT_AC_CHANNEL1_WEIGHT) & BIT_MASK_AC_CHANNEL1_WEIGHT)
+#define BIT_SET_AC_CHANNEL1_WEIGHT(x, v)                                       \
+	(BIT_CLEAR_AC_CHANNEL1_WEIGHT(x) | BIT_AC_CHANNEL1_WEIGHT(v))
+
+/* 2 REG_AC_CHANNEL2_WEIGHT			(Offset 0x336A) */
+
+#define BIT_SHIFT_AC_CHANNEL2_WEIGHT 0
+#define BIT_MASK_AC_CHANNEL2_WEIGHT 0xff
+#define BIT_AC_CHANNEL2_WEIGHT(x)                                              \
+	(((x) & BIT_MASK_AC_CHANNEL2_WEIGHT) << BIT_SHIFT_AC_CHANNEL2_WEIGHT)
+#define BITS_AC_CHANNEL2_WEIGHT                                                \
+	(BIT_MASK_AC_CHANNEL2_WEIGHT << BIT_SHIFT_AC_CHANNEL2_WEIGHT)
+#define BIT_CLEAR_AC_CHANNEL2_WEIGHT(x) ((x) & (~BITS_AC_CHANNEL2_WEIGHT))
+#define BIT_GET_AC_CHANNEL2_WEIGHT(x)                                          \
+	(((x) >> BIT_SHIFT_AC_CHANNEL2_WEIGHT) & BIT_MASK_AC_CHANNEL2_WEIGHT)
+#define BIT_SET_AC_CHANNEL2_WEIGHT(x, v)                                       \
+	(BIT_CLEAR_AC_CHANNEL2_WEIGHT(x) | BIT_AC_CHANNEL2_WEIGHT(v))
+
+/* 2 REG_AC_CHANNEL3_WEIGHT			(Offset 0x336B) */
+
+#define BIT_SHIFT_AC_CHANNEL3_WEIGHT 0
+#define BIT_MASK_AC_CHANNEL3_WEIGHT 0xff
+#define BIT_AC_CHANNEL3_WEIGHT(x)                                              \
+	(((x) & BIT_MASK_AC_CHANNEL3_WEIGHT) << BIT_SHIFT_AC_CHANNEL3_WEIGHT)
+#define BITS_AC_CHANNEL3_WEIGHT                                                \
+	(BIT_MASK_AC_CHANNEL3_WEIGHT << BIT_SHIFT_AC_CHANNEL3_WEIGHT)
+#define BIT_CLEAR_AC_CHANNEL3_WEIGHT(x) ((x) & (~BITS_AC_CHANNEL3_WEIGHT))
+#define BIT_GET_AC_CHANNEL3_WEIGHT(x)                                          \
+	(((x) >> BIT_SHIFT_AC_CHANNEL3_WEIGHT) & BIT_MASK_AC_CHANNEL3_WEIGHT)
+#define BIT_SET_AC_CHANNEL3_WEIGHT(x, v)                                       \
+	(BIT_CLEAR_AC_CHANNEL3_WEIGHT(x) | BIT_AC_CHANNEL3_WEIGHT(v))
+
+/* 2 REG_AC_CHANNEL4_WEIGHT			(Offset 0x336C) */
+
+#define BIT_SHIFT_AC_CHANNEL4_WEIGHT 0
+#define BIT_MASK_AC_CHANNEL4_WEIGHT 0xff
+#define BIT_AC_CHANNEL4_WEIGHT(x)                                              \
+	(((x) & BIT_MASK_AC_CHANNEL4_WEIGHT) << BIT_SHIFT_AC_CHANNEL4_WEIGHT)
+#define BITS_AC_CHANNEL4_WEIGHT                                                \
+	(BIT_MASK_AC_CHANNEL4_WEIGHT << BIT_SHIFT_AC_CHANNEL4_WEIGHT)
+#define BIT_CLEAR_AC_CHANNEL4_WEIGHT(x) ((x) & (~BITS_AC_CHANNEL4_WEIGHT))
+#define BIT_GET_AC_CHANNEL4_WEIGHT(x)                                          \
+	(((x) >> BIT_SHIFT_AC_CHANNEL4_WEIGHT) & BIT_MASK_AC_CHANNEL4_WEIGHT)
+#define BIT_SET_AC_CHANNEL4_WEIGHT(x, v)                                       \
+	(BIT_CLEAR_AC_CHANNEL4_WEIGHT(x) | BIT_AC_CHANNEL4_WEIGHT(v))
+
+/* 2 REG_AC_CHANNEL5_WEIGHT			(Offset 0x336D) */
+
+#define BIT_SHIFT_AC_CHANNEL5_WEIGHT 0
+#define BIT_MASK_AC_CHANNEL5_WEIGHT 0xff
+#define BIT_AC_CHANNEL5_WEIGHT(x)                                              \
+	(((x) & BIT_MASK_AC_CHANNEL5_WEIGHT) << BIT_SHIFT_AC_CHANNEL5_WEIGHT)
+#define BITS_AC_CHANNEL5_WEIGHT                                                \
+	(BIT_MASK_AC_CHANNEL5_WEIGHT << BIT_SHIFT_AC_CHANNEL5_WEIGHT)
+#define BIT_CLEAR_AC_CHANNEL5_WEIGHT(x) ((x) & (~BITS_AC_CHANNEL5_WEIGHT))
+#define BIT_GET_AC_CHANNEL5_WEIGHT(x)                                          \
+	(((x) >> BIT_SHIFT_AC_CHANNEL5_WEIGHT) & BIT_MASK_AC_CHANNEL5_WEIGHT)
+#define BIT_SET_AC_CHANNEL5_WEIGHT(x, v)                                       \
+	(BIT_CLEAR_AC_CHANNEL5_WEIGHT(x) | BIT_AC_CHANNEL5_WEIGHT(v))
+
+/* 2 REG_AC_CHANNEL6_WEIGHT			(Offset 0x336E) */
+
+#define BIT_SHIFT_AC_CHANNEL6_WEIGHT 0
+#define BIT_MASK_AC_CHANNEL6_WEIGHT 0xff
+#define BIT_AC_CHANNEL6_WEIGHT(x)                                              \
+	(((x) & BIT_MASK_AC_CHANNEL6_WEIGHT) << BIT_SHIFT_AC_CHANNEL6_WEIGHT)
+#define BITS_AC_CHANNEL6_WEIGHT                                                \
+	(BIT_MASK_AC_CHANNEL6_WEIGHT << BIT_SHIFT_AC_CHANNEL6_WEIGHT)
+#define BIT_CLEAR_AC_CHANNEL6_WEIGHT(x) ((x) & (~BITS_AC_CHANNEL6_WEIGHT))
+#define BIT_GET_AC_CHANNEL6_WEIGHT(x)                                          \
+	(((x) >> BIT_SHIFT_AC_CHANNEL6_WEIGHT) & BIT_MASK_AC_CHANNEL6_WEIGHT)
+#define BIT_SET_AC_CHANNEL6_WEIGHT(x, v)                                       \
+	(BIT_CLEAR_AC_CHANNEL6_WEIGHT(x) | BIT_AC_CHANNEL6_WEIGHT(v))
+
+/* 2 REG_AC_CHANNEL7_WEIGHT			(Offset 0x336F) */
+
+#define BIT_SHIFT_AC_CHANNEL7_WEIGHT 0
+#define BIT_MASK_AC_CHANNEL7_WEIGHT 0xff
+#define BIT_AC_CHANNEL7_WEIGHT(x)                                              \
+	(((x) & BIT_MASK_AC_CHANNEL7_WEIGHT) << BIT_SHIFT_AC_CHANNEL7_WEIGHT)
+#define BITS_AC_CHANNEL7_WEIGHT                                                \
+	(BIT_MASK_AC_CHANNEL7_WEIGHT << BIT_SHIFT_AC_CHANNEL7_WEIGHT)
+#define BIT_CLEAR_AC_CHANNEL7_WEIGHT(x) ((x) & (~BITS_AC_CHANNEL7_WEIGHT))
+#define BIT_GET_AC_CHANNEL7_WEIGHT(x)                                          \
+	(((x) >> BIT_SHIFT_AC_CHANNEL7_WEIGHT) & BIT_MASK_AC_CHANNEL7_WEIGHT)
+#define BIT_SET_AC_CHANNEL7_WEIGHT(x, v)                                       \
+	(BIT_CLEAR_AC_CHANNEL7_WEIGHT(x) | BIT_AC_CHANNEL7_WEIGHT(v))
+
+/* 2 REG_AC_CHANNEL8_WEIGHT			(Offset 0x3370) */
+
+#define BIT_SHIFT_AC_CHANNEL8_WEIGHT 0
+#define BIT_MASK_AC_CHANNEL8_WEIGHT 0xff
+#define BIT_AC_CHANNEL8_WEIGHT(x)                                              \
+	(((x) & BIT_MASK_AC_CHANNEL8_WEIGHT) << BIT_SHIFT_AC_CHANNEL8_WEIGHT)
+#define BITS_AC_CHANNEL8_WEIGHT                                                \
+	(BIT_MASK_AC_CHANNEL8_WEIGHT << BIT_SHIFT_AC_CHANNEL8_WEIGHT)
+#define BIT_CLEAR_AC_CHANNEL8_WEIGHT(x) ((x) & (~BITS_AC_CHANNEL8_WEIGHT))
+#define BIT_GET_AC_CHANNEL8_WEIGHT(x)                                          \
+	(((x) >> BIT_SHIFT_AC_CHANNEL8_WEIGHT) & BIT_MASK_AC_CHANNEL8_WEIGHT)
+#define BIT_SET_AC_CHANNEL8_WEIGHT(x, v)                                       \
+	(BIT_CLEAR_AC_CHANNEL8_WEIGHT(x) | BIT_AC_CHANNEL8_WEIGHT(v))
+
+/* 2 REG_AC_CHANNEL9_WEIGHT			(Offset 0x3371) */
+
+#define BIT_SHIFT_AC_CHANNEL9_WEIGHT 0
+#define BIT_MASK_AC_CHANNEL9_WEIGHT 0xff
+#define BIT_AC_CHANNEL9_WEIGHT(x)                                              \
+	(((x) & BIT_MASK_AC_CHANNEL9_WEIGHT) << BIT_SHIFT_AC_CHANNEL9_WEIGHT)
+#define BITS_AC_CHANNEL9_WEIGHT                                                \
+	(BIT_MASK_AC_CHANNEL9_WEIGHT << BIT_SHIFT_AC_CHANNEL9_WEIGHT)
+#define BIT_CLEAR_AC_CHANNEL9_WEIGHT(x) ((x) & (~BITS_AC_CHANNEL9_WEIGHT))
+#define BIT_GET_AC_CHANNEL9_WEIGHT(x)                                          \
+	(((x) >> BIT_SHIFT_AC_CHANNEL9_WEIGHT) & BIT_MASK_AC_CHANNEL9_WEIGHT)
+#define BIT_SET_AC_CHANNEL9_WEIGHT(x, v)                                       \
+	(BIT_CLEAR_AC_CHANNEL9_WEIGHT(x) | BIT_AC_CHANNEL9_WEIGHT(v))
+
+/* 2 REG_AC_CHANNEL10_WEIGHT			(Offset 0x3372) */
+
+#define BIT_SHIFT_AC_CHANNEL10_WEIGHT 0
+#define BIT_MASK_AC_CHANNEL10_WEIGHT 0xff
+#define BIT_AC_CHANNEL10_WEIGHT(x)                                             \
+	(((x) & BIT_MASK_AC_CHANNEL10_WEIGHT) << BIT_SHIFT_AC_CHANNEL10_WEIGHT)
+#define BITS_AC_CHANNEL10_WEIGHT                                               \
+	(BIT_MASK_AC_CHANNEL10_WEIGHT << BIT_SHIFT_AC_CHANNEL10_WEIGHT)
+#define BIT_CLEAR_AC_CHANNEL10_WEIGHT(x) ((x) & (~BITS_AC_CHANNEL10_WEIGHT))
+#define BIT_GET_AC_CHANNEL10_WEIGHT(x)                                         \
+	(((x) >> BIT_SHIFT_AC_CHANNEL10_WEIGHT) & BIT_MASK_AC_CHANNEL10_WEIGHT)
+#define BIT_SET_AC_CHANNEL10_WEIGHT(x, v)                                      \
+	(BIT_CLEAR_AC_CHANNEL10_WEIGHT(x) | BIT_AC_CHANNEL10_WEIGHT(v))
+
+/* 2 REG_AC_CHANNEL11_WEIGHT			(Offset 0x3373) */
+
+#define BIT_SHIFT_AC_CHANNEL11_WEIGHT 0
+#define BIT_MASK_AC_CHANNEL11_WEIGHT 0xff
+#define BIT_AC_CHANNEL11_WEIGHT(x)                                             \
+	(((x) & BIT_MASK_AC_CHANNEL11_WEIGHT) << BIT_SHIFT_AC_CHANNEL11_WEIGHT)
+#define BITS_AC_CHANNEL11_WEIGHT                                               \
+	(BIT_MASK_AC_CHANNEL11_WEIGHT << BIT_SHIFT_AC_CHANNEL11_WEIGHT)
+#define BIT_CLEAR_AC_CHANNEL11_WEIGHT(x) ((x) & (~BITS_AC_CHANNEL11_WEIGHT))
+#define BIT_GET_AC_CHANNEL11_WEIGHT(x)                                         \
+	(((x) >> BIT_SHIFT_AC_CHANNEL11_WEIGHT) & BIT_MASK_AC_CHANNEL11_WEIGHT)
+#define BIT_SET_AC_CHANNEL11_WEIGHT(x, v)                                      \
+	(BIT_CLEAR_AC_CHANNEL11_WEIGHT(x) | BIT_AC_CHANNEL11_WEIGHT(v))
+
+/* 2 REG_AC_CHANNEL12_WEIGHT			(Offset 0x3374) */
+
+#define BIT_SHIFT_AC_CHANNEL12_WEIGHT 0
+#define BIT_MASK_AC_CHANNEL12_WEIGHT 0xff
+#define BIT_AC_CHANNEL12_WEIGHT(x)                                             \
+	(((x) & BIT_MASK_AC_CHANNEL12_WEIGHT) << BIT_SHIFT_AC_CHANNEL12_WEIGHT)
+#define BITS_AC_CHANNEL12_WEIGHT                                               \
+	(BIT_MASK_AC_CHANNEL12_WEIGHT << BIT_SHIFT_AC_CHANNEL12_WEIGHT)
+#define BIT_CLEAR_AC_CHANNEL12_WEIGHT(x) ((x) & (~BITS_AC_CHANNEL12_WEIGHT))
+#define BIT_GET_AC_CHANNEL12_WEIGHT(x)                                         \
+	(((x) >> BIT_SHIFT_AC_CHANNEL12_WEIGHT) & BIT_MASK_AC_CHANNEL12_WEIGHT)
+#define BIT_SET_AC_CHANNEL12_WEIGHT(x, v)                                      \
+	(BIT_CLEAR_AC_CHANNEL12_WEIGHT(x) | BIT_AC_CHANNEL12_WEIGHT(v))
+
+/* 2 REG_AC_CHANNEL13_WEIGHT			(Offset 0x3375) */
+
+#define BIT_SHIFT_AC_CHANNEL13_WEIGHT 0
+#define BIT_MASK_AC_CHANNEL13_WEIGHT 0xff
+#define BIT_AC_CHANNEL13_WEIGHT(x)                                             \
+	(((x) & BIT_MASK_AC_CHANNEL13_WEIGHT) << BIT_SHIFT_AC_CHANNEL13_WEIGHT)
+#define BITS_AC_CHANNEL13_WEIGHT                                               \
+	(BIT_MASK_AC_CHANNEL13_WEIGHT << BIT_SHIFT_AC_CHANNEL13_WEIGHT)
+#define BIT_CLEAR_AC_CHANNEL13_WEIGHT(x) ((x) & (~BITS_AC_CHANNEL13_WEIGHT))
+#define BIT_GET_AC_CHANNEL13_WEIGHT(x)                                         \
+	(((x) >> BIT_SHIFT_AC_CHANNEL13_WEIGHT) & BIT_MASK_AC_CHANNEL13_WEIGHT)
+#define BIT_SET_AC_CHANNEL13_WEIGHT(x, v)                                      \
+	(BIT_CLEAR_AC_CHANNEL13_WEIGHT(x) | BIT_AC_CHANNEL13_WEIGHT(v))
+
+#endif
+
+#endif /* __RTL_WLAN_BITDEF_H__ */
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/halmac/halmac_bit_8197f.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/halmac/halmac_bit_8197f.h
--- linux-5.6.3/3rdparty/rtl8821ce/hal/halmac/halmac_bit_8197f.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/halmac/halmac_bit_8197f.h	2020-04-10 16:35:06.800659320 +0300
@@ -0,0 +1,17293 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ ******************************************************************************/
+
+#ifndef __INC_HALMAC_BIT_8197F_H
+#define __INC_HALMAC_BIT_8197F_H
+
+#define CPU_OPT_WIDTH 0x1F
+
+/* 2 REG_NOT_VALID_8197F */
+
+/* 2 REG_SYS_ISO_CTRL_8197F */
+#define BIT_PWC_EV12V_8197F BIT(15)
+#define BIT_PWC_EV25V_8197F BIT(14)
+#define BIT_PA33V_EN_8197F BIT(13)
+#define BIT_PA12V_EN_8197F BIT(12)
+#define BIT_UA33V_EN_8197F BIT(11)
+#define BIT_UA12V_EN_8197F BIT(10)
+#define BIT_ISO_RFDIO_8197F BIT(9)
+#define BIT_ISO_EB2CORE_8197F BIT(8)
+#define BIT_ISO_DIOE_8197F BIT(7)
+#define BIT_ISO_WLPON2PP_8197F BIT(6)
+#define BIT_ISO_IP2MAC_WA2PP_8197F BIT(5)
+#define BIT_ISO_PD2CORE_8197F BIT(4)
+#define BIT_ISO_PA2PCIE_8197F BIT(3)
+#define BIT_ISO_UD2CORE_8197F BIT(2)
+#define BIT_ISO_UA2USB_8197F BIT(1)
+#define BIT_ISO_WD2PP_8197F BIT(0)
+
+/* 2 REG_SYS_FUNC_EN_8197F */
+#define BIT_FEN_MREGEN_8197F BIT(15)
+#define BIT_FEN_HWPDN_8197F BIT(14)
+#define BIT_EN_25_1_8197F BIT(13)
+#define BIT_FEN_ELDR_8197F BIT(12)
+#define BIT_FEN_DCORE_8197F BIT(11)
+#define BIT_FEN_CPUEN_8197F BIT(10)
+#define BIT_FEN_DIOE_8197F BIT(9)
+#define BIT_FEN_PCIED_8197F BIT(8)
+#define BIT_FEN_PPLL_8197F BIT(7)
+#define BIT_FEN_PCIEA_8197F BIT(6)
+#define BIT_FEN_DIO_PCIE_8197F BIT(5)
+#define BIT_FEN_USBD_8197F BIT(4)
+#define BIT_FEN_UPLL_8197F BIT(3)
+#define BIT_FEN_USBA_8197F BIT(2)
+#define BIT_FEN_BB_GLB_RSTN_8197F BIT(1)
+#define BIT_FEN_BBRSTB_8197F BIT(0)
+
+/* 2 REG_SYS_PW_CTRL_8197F */
+#define BIT_SOP_EABM_8197F BIT(31)
+#define BIT_SOP_ACKF_8197F BIT(30)
+#define BIT_SOP_ERCK_8197F BIT(29)
+#define BIT_SOP_ESWR_8197F BIT(28)
+#define BIT_SOP_PWMM_8197F BIT(27)
+#define BIT_SOP_EECK_8197F BIT(26)
+#define BIT_SOP_EXTL_8197F BIT(24)
+#define BIT_SYM_OP_RING_12M_8197F BIT(22)
+#define BIT_ROP_SWPR_8197F BIT(21)
+#define BIT_DIS_HW_LPLDM_8197F BIT(20)
+#define BIT_OPT_SWRST_WLMCU_8197F BIT(19)
+#define BIT_RDY_SYSPWR_8197F BIT(17)
+#define BIT_EN_WLON_8197F BIT(16)
+#define BIT_APDM_HPDN_8197F BIT(15)
+#define BIT_AFSM_PCIE_SUS_EN_8197F BIT(12)
+#define BIT_AFSM_WLSUS_EN_8197F BIT(11)
+#define BIT_APFM_SWLPS_8197F BIT(10)
+#define BIT_APFM_OFFMAC_8197F BIT(9)
+#define BIT_APFN_ONMAC_8197F BIT(8)
+#define BIT_CHIP_PDN_EN_8197F BIT(7)
+#define BIT_RDY_MACDIS_8197F BIT(6)
+#define BIT_RING_CLK_12M_EN_8197F BIT(4)
+#define BIT_PFM_WOWL_8197F BIT(3)
+#define BIT_PFM_LDKP_8197F BIT(2)
+#define BIT_WL_HCI_ALD_8197F BIT(1)
+#define BIT_PFM_LDALL_8197F BIT(0)
+
+/* 2 REG_SYS_CLK_CTRL_8197F */
+#define BIT_LDO_DUMMY_8197F BIT(15)
+#define BIT_CPU_CLK_EN_8197F BIT(14)
+#define BIT_SYMREG_CLK_EN_8197F BIT(13)
+#define BIT_HCI_CLK_EN_8197F BIT(12)
+#define BIT_MAC_CLK_EN_8197F BIT(11)
+#define BIT_SEC_CLK_EN_8197F BIT(10)
+#define BIT_PHY_SSC_RSTB_8197F BIT(9)
+#define BIT_EXT_32K_EN_8197F BIT(8)
+#define BIT_WL_CLK_TEST_8197F BIT(7)
+#define BIT_OP_SPS_PWM_EN_8197F BIT(6)
+#define BIT_LOADER_CLK_EN_8197F BIT(5)
+#define BIT_MACSLP_8197F BIT(4)
+#define BIT_WAKEPAD_EN_8197F BIT(3)
+#define BIT_ROMD16V_EN_8197F BIT(2)
+#define BIT_CKANA12M_EN_8197F BIT(1)
+#define BIT_CNTD16V_EN_8197F BIT(0)
+
+/* 2 REG_SYS_EEPROM_CTRL_8197F */
+
+#define BIT_SHIFT_VPDIDX_8197F 8
+#define BIT_MASK_VPDIDX_8197F 0xff
+#define BIT_VPDIDX_8197F(x)                                                    \
+	(((x) & BIT_MASK_VPDIDX_8197F) << BIT_SHIFT_VPDIDX_8197F)
+#define BITS_VPDIDX_8197F (BIT_MASK_VPDIDX_8197F << BIT_SHIFT_VPDIDX_8197F)
+#define BIT_CLEAR_VPDIDX_8197F(x) ((x) & (~BITS_VPDIDX_8197F))
+#define BIT_GET_VPDIDX_8197F(x)                                                \
+	(((x) >> BIT_SHIFT_VPDIDX_8197F) & BIT_MASK_VPDIDX_8197F)
+#define BIT_SET_VPDIDX_8197F(x, v)                                             \
+	(BIT_CLEAR_VPDIDX_8197F(x) | BIT_VPDIDX_8197F(v))
+
+#define BIT_SHIFT_EEM1_0_8197F 6
+#define BIT_MASK_EEM1_0_8197F 0x3
+#define BIT_EEM1_0_8197F(x)                                                    \
+	(((x) & BIT_MASK_EEM1_0_8197F) << BIT_SHIFT_EEM1_0_8197F)
+#define BITS_EEM1_0_8197F (BIT_MASK_EEM1_0_8197F << BIT_SHIFT_EEM1_0_8197F)
+#define BIT_CLEAR_EEM1_0_8197F(x) ((x) & (~BITS_EEM1_0_8197F))
+#define BIT_GET_EEM1_0_8197F(x)                                                \
+	(((x) >> BIT_SHIFT_EEM1_0_8197F) & BIT_MASK_EEM1_0_8197F)
+#define BIT_SET_EEM1_0_8197F(x, v)                                             \
+	(BIT_CLEAR_EEM1_0_8197F(x) | BIT_EEM1_0_8197F(v))
+
+#define BIT_AUTOLOAD_SUS_8197F BIT(5)
+#define BIT_EERPOMSEL_8197F BIT(4)
+#define BIT_EECS_V1_8197F BIT(3)
+#define BIT_EESK_V1_8197F BIT(2)
+#define BIT_EEDI_V1_8197F BIT(1)
+#define BIT_EEDO_V1_8197F BIT(0)
+
+/* 2 REG_EE_VPD_8197F */
+
+#define BIT_SHIFT_VPD_DATA_8197F 0
+#define BIT_MASK_VPD_DATA_8197F 0xffffffffL
+#define BIT_VPD_DATA_8197F(x)                                                  \
+	(((x) & BIT_MASK_VPD_DATA_8197F) << BIT_SHIFT_VPD_DATA_8197F)
+#define BITS_VPD_DATA_8197F                                                    \
+	(BIT_MASK_VPD_DATA_8197F << BIT_SHIFT_VPD_DATA_8197F)
+#define BIT_CLEAR_VPD_DATA_8197F(x) ((x) & (~BITS_VPD_DATA_8197F))
+#define BIT_GET_VPD_DATA_8197F(x)                                              \
+	(((x) >> BIT_SHIFT_VPD_DATA_8197F) & BIT_MASK_VPD_DATA_8197F)
+#define BIT_SET_VPD_DATA_8197F(x, v)                                           \
+	(BIT_CLEAR_VPD_DATA_8197F(x) | BIT_VPD_DATA_8197F(v))
+
+/* 2 REG_SYS_SWR_CTRL1_8197F */
+#define BIT_SW18_C2_BIT0_8197F BIT(31)
+
+#define BIT_SHIFT_SW18_C1_8197F 29
+#define BIT_MASK_SW18_C1_8197F 0x3
+#define BIT_SW18_C1_8197F(x)                                                   \
+	(((x) & BIT_MASK_SW18_C1_8197F) << BIT_SHIFT_SW18_C1_8197F)
+#define BITS_SW18_C1_8197F (BIT_MASK_SW18_C1_8197F << BIT_SHIFT_SW18_C1_8197F)
+#define BIT_CLEAR_SW18_C1_8197F(x) ((x) & (~BITS_SW18_C1_8197F))
+#define BIT_GET_SW18_C1_8197F(x)                                               \
+	(((x) >> BIT_SHIFT_SW18_C1_8197F) & BIT_MASK_SW18_C1_8197F)
+#define BIT_SET_SW18_C1_8197F(x, v)                                            \
+	(BIT_CLEAR_SW18_C1_8197F(x) | BIT_SW18_C1_8197F(v))
+
+#define BIT_SHIFT_REG_FREQ_L_8197F 25
+#define BIT_MASK_REG_FREQ_L_8197F 0x7
+#define BIT_REG_FREQ_L_8197F(x)                                                \
+	(((x) & BIT_MASK_REG_FREQ_L_8197F) << BIT_SHIFT_REG_FREQ_L_8197F)
+#define BITS_REG_FREQ_L_8197F                                                  \
+	(BIT_MASK_REG_FREQ_L_8197F << BIT_SHIFT_REG_FREQ_L_8197F)
+#define BIT_CLEAR_REG_FREQ_L_8197F(x) ((x) & (~BITS_REG_FREQ_L_8197F))
+#define BIT_GET_REG_FREQ_L_8197F(x)                                            \
+	(((x) >> BIT_SHIFT_REG_FREQ_L_8197F) & BIT_MASK_REG_FREQ_L_8197F)
+#define BIT_SET_REG_FREQ_L_8197F(x, v)                                         \
+	(BIT_CLEAR_REG_FREQ_L_8197F(x) | BIT_REG_FREQ_L_8197F(v))
+
+#define BIT_REG_EN_DUTY_8197F BIT(24)
+
+#define BIT_SHIFT_REG_MODE_8197F 22
+#define BIT_MASK_REG_MODE_8197F 0x3
+#define BIT_REG_MODE_8197F(x)                                                  \
+	(((x) & BIT_MASK_REG_MODE_8197F) << BIT_SHIFT_REG_MODE_8197F)
+#define BITS_REG_MODE_8197F                                                    \
+	(BIT_MASK_REG_MODE_8197F << BIT_SHIFT_REG_MODE_8197F)
+#define BIT_CLEAR_REG_MODE_8197F(x) ((x) & (~BITS_REG_MODE_8197F))
+#define BIT_GET_REG_MODE_8197F(x)                                              \
+	(((x) >> BIT_SHIFT_REG_MODE_8197F) & BIT_MASK_REG_MODE_8197F)
+#define BIT_SET_REG_MODE_8197F(x, v)                                           \
+	(BIT_CLEAR_REG_MODE_8197F(x) | BIT_REG_MODE_8197F(v))
+
+#define BIT_REG_EN_SP_8197F BIT(21)
+#define BIT_REG_AUTO_L_8197F BIT(20)
+#define BIT_SW18_SELD_BIT0_8197F BIT(19)
+#define BIT_SW18_POWOCP_8197F BIT(18)
+
+#define BIT_SHIFT_SW18_OCP_8197F 15
+#define BIT_MASK_SW18_OCP_8197F 0x7
+#define BIT_SW18_OCP_8197F(x)                                                  \
+	(((x) & BIT_MASK_SW18_OCP_8197F) << BIT_SHIFT_SW18_OCP_8197F)
+#define BITS_SW18_OCP_8197F                                                    \
+	(BIT_MASK_SW18_OCP_8197F << BIT_SHIFT_SW18_OCP_8197F)
+#define BIT_CLEAR_SW18_OCP_8197F(x) ((x) & (~BITS_SW18_OCP_8197F))
+#define BIT_GET_SW18_OCP_8197F(x)                                              \
+	(((x) >> BIT_SHIFT_SW18_OCP_8197F) & BIT_MASK_SW18_OCP_8197F)
+#define BIT_SET_SW18_OCP_8197F(x, v)                                           \
+	(BIT_CLEAR_SW18_OCP_8197F(x) | BIT_SW18_OCP_8197F(v))
+
+#define BIT_SHIFT_CF_L_BIT0_TO_1_8197F 13
+#define BIT_MASK_CF_L_BIT0_TO_1_8197F 0x3
+#define BIT_CF_L_BIT0_TO_1_8197F(x)                                            \
+	(((x) & BIT_MASK_CF_L_BIT0_TO_1_8197F)                                 \
+	 << BIT_SHIFT_CF_L_BIT0_TO_1_8197F)
+#define BITS_CF_L_BIT0_TO_1_8197F                                              \
+	(BIT_MASK_CF_L_BIT0_TO_1_8197F << BIT_SHIFT_CF_L_BIT0_TO_1_8197F)
+#define BIT_CLEAR_CF_L_BIT0_TO_1_8197F(x) ((x) & (~BITS_CF_L_BIT0_TO_1_8197F))
+#define BIT_GET_CF_L_BIT0_TO_1_8197F(x)                                        \
+	(((x) >> BIT_SHIFT_CF_L_BIT0_TO_1_8197F) &                             \
+	 BIT_MASK_CF_L_BIT0_TO_1_8197F)
+#define BIT_SET_CF_L_BIT0_TO_1_8197F(x, v)                                     \
+	(BIT_CLEAR_CF_L_BIT0_TO_1_8197F(x) | BIT_CF_L_BIT0_TO_1_8197F(v))
+
+#define BIT_SW18_FPWM_8197F BIT(11)
+#define BIT_SW18_SWEN_8197F BIT(9)
+#define BIT_SW18_LDEN_8197F BIT(8)
+#define BIT_MAC_ID_EN_8197F BIT(7)
+#define BIT_WL_CTRL_XTAL_CADJ_8197F BIT(6)
+#define BIT_AFE_BGEN_8197F BIT(0)
+
+/* 2 REG_SYS_SWR_CTRL2_8197F */
+
+/* 2 REG_NOT_VALID_8197F */
+
+/* 2 REG_NOT_VALID_8197F */
+
+/* 2 REG_NOT_VALID_8197F */
+
+/* 2 REG_NOT_VALID_8197F */
+
+/* 2 REG_NOT_VALID_8197F */
+
+/* 2 REG_NOT_VALID_8197F */
+
+/* 2 REG_NOT_VALID_8197F */
+
+/* 2 REG_NOT_VALID_8197F */
+
+/* 2 REG_NOT_VALID_8197F */
+
+/* 2 REG_NOT_VALID_8197F */
+
+/* 2 REG_NOT_VALID_8197F */
+
+/* 2 REG_NOT_VALID_8197F */
+
+/* 2 REG_NOT_VALID_8197F */
+
+/* 2 REG_NOT_VALID_8197F */
+
+/* 2 REG_NOT_VALID_8197F */
+
+/* 2 REG_NOT_VALID_8197F */
+
+/* 2 REG_NOT_VALID_8197F */
+
+/* 2 REG_NOT_VALID_8197F */
+
+/* 2 REG_SYS_SWR_CTRL3_8197F */
+#define BIT_SPS18_OCP_DIS_8197F BIT(31)
+
+#define BIT_SHIFT_SPS18_OCP_TH_8197F 16
+#define BIT_MASK_SPS18_OCP_TH_8197F 0x7fff
+#define BIT_SPS18_OCP_TH_8197F(x)                                              \
+	(((x) & BIT_MASK_SPS18_OCP_TH_8197F) << BIT_SHIFT_SPS18_OCP_TH_8197F)
+#define BITS_SPS18_OCP_TH_8197F                                                \
+	(BIT_MASK_SPS18_OCP_TH_8197F << BIT_SHIFT_SPS18_OCP_TH_8197F)
+#define BIT_CLEAR_SPS18_OCP_TH_8197F(x) ((x) & (~BITS_SPS18_OCP_TH_8197F))
+#define BIT_GET_SPS18_OCP_TH_8197F(x)                                          \
+	(((x) >> BIT_SHIFT_SPS18_OCP_TH_8197F) & BIT_MASK_SPS18_OCP_TH_8197F)
+#define BIT_SET_SPS18_OCP_TH_8197F(x, v)                                       \
+	(BIT_CLEAR_SPS18_OCP_TH_8197F(x) | BIT_SPS18_OCP_TH_8197F(v))
+
+#define BIT_SHIFT_OCP_WINDOW_8197F 0
+#define BIT_MASK_OCP_WINDOW_8197F 0xffff
+#define BIT_OCP_WINDOW_8197F(x)                                                \
+	(((x) & BIT_MASK_OCP_WINDOW_8197F) << BIT_SHIFT_OCP_WINDOW_8197F)
+#define BITS_OCP_WINDOW_8197F                                                  \
+	(BIT_MASK_OCP_WINDOW_8197F << BIT_SHIFT_OCP_WINDOW_8197F)
+#define BIT_CLEAR_OCP_WINDOW_8197F(x) ((x) & (~BITS_OCP_WINDOW_8197F))
+#define BIT_GET_OCP_WINDOW_8197F(x)                                            \
+	(((x) >> BIT_SHIFT_OCP_WINDOW_8197F) & BIT_MASK_OCP_WINDOW_8197F)
+#define BIT_SET_OCP_WINDOW_8197F(x, v)                                         \
+	(BIT_CLEAR_OCP_WINDOW_8197F(x) | BIT_OCP_WINDOW_8197F(v))
+
+/* 2 REG_RSV_CTRL_8197F */
+#define BIT_HREG_DBG_8197F BIT(23)
+#define BIT_WLMCUIOIF_8197F BIT(8)
+#define BIT_LOCK_ALL_EN_8197F BIT(7)
+#define BIT_R_DIS_PRST_8197F BIT(6)
+#define BIT_WLOCK_1C_B6_8197F BIT(5)
+#define BIT_WLOCK_40_8197F BIT(4)
+#define BIT_WLOCK_08_8197F BIT(3)
+#define BIT_WLOCK_04_8197F BIT(2)
+#define BIT_WLOCK_00_8197F BIT(1)
+#define BIT_WLOCK_ALL_8197F BIT(0)
+
+/* 2 REG_RF0_CTRL_8197F */
+#define BIT_RF0_SDMRSTB_8197F BIT(2)
+#define BIT_RF0_RSTB_8197F BIT(1)
+#define BIT_RF0_EN_8197F BIT(0)
+
+/* 2 REG_AFE_LDO_CTRL_8197F */
+
+#define BIT_SHIFT_LPLDH12_RSV_8197F 29
+#define BIT_MASK_LPLDH12_RSV_8197F 0x7
+#define BIT_LPLDH12_RSV_8197F(x)                                               \
+	(((x) & BIT_MASK_LPLDH12_RSV_8197F) << BIT_SHIFT_LPLDH12_RSV_8197F)
+#define BITS_LPLDH12_RSV_8197F                                                 \
+	(BIT_MASK_LPLDH12_RSV_8197F << BIT_SHIFT_LPLDH12_RSV_8197F)
+#define BIT_CLEAR_LPLDH12_RSV_8197F(x) ((x) & (~BITS_LPLDH12_RSV_8197F))
+#define BIT_GET_LPLDH12_RSV_8197F(x)                                           \
+	(((x) >> BIT_SHIFT_LPLDH12_RSV_8197F) & BIT_MASK_LPLDH12_RSV_8197F)
+#define BIT_SET_LPLDH12_RSV_8197F(x, v)                                        \
+	(BIT_CLEAR_LPLDH12_RSV_8197F(x) | BIT_LPLDH12_RSV_8197F(v))
+
+#define BIT_LPLDH12_SLP_8197F BIT(28)
+
+#define BIT_SHIFT_LPLDH12_VADJ_8197F 24
+#define BIT_MASK_LPLDH12_VADJ_8197F 0xf
+#define BIT_LPLDH12_VADJ_8197F(x)                                              \
+	(((x) & BIT_MASK_LPLDH12_VADJ_8197F) << BIT_SHIFT_LPLDH12_VADJ_8197F)
+#define BITS_LPLDH12_VADJ_8197F                                                \
+	(BIT_MASK_LPLDH12_VADJ_8197F << BIT_SHIFT_LPLDH12_VADJ_8197F)
+#define BIT_CLEAR_LPLDH12_VADJ_8197F(x) ((x) & (~BITS_LPLDH12_VADJ_8197F))
+#define BIT_GET_LPLDH12_VADJ_8197F(x)                                          \
+	(((x) >> BIT_SHIFT_LPLDH12_VADJ_8197F) & BIT_MASK_LPLDH12_VADJ_8197F)
+#define BIT_SET_LPLDH12_VADJ_8197F(x, v)                                       \
+	(BIT_CLEAR_LPLDH12_VADJ_8197F(x) | BIT_LPLDH12_VADJ_8197F(v))
+
+#define BIT_LDH12_EN_8197F BIT(16)
+#define BIT_POW_REGU_P1_8197F BIT(10)
+#define BIT_LDOV12W_EN_8197F BIT(8)
+#define BIT_EX_XTAL_DRV_DIGI_8197F BIT(7)
+#define BIT_EX_XTAL_DRV_USB_8197F BIT(6)
+#define BIT_EX_XTAL_DRV_AFE_8197F BIT(5)
+#define BIT_EX_XTAL_DRV_RF2_8197F BIT(4)
+#define BIT_EX_XTAL_DRV_RF1_8197F BIT(3)
+#define BIT_POW_REGU_P0_8197F BIT(2)
+
+/* 2 REG_NOT_VALID_8197F */
+#define BIT_POW_PLL_LDO_8197F BIT(0)
+
+/* 2 REG_AFE_CTRL1_8197F */
+#define BIT_AGPIO_GPE_8197F BIT(31)
+
+#define BIT_SHIFT_XTAL_CAP_XI_8197F 25
+#define BIT_MASK_XTAL_CAP_XI_8197F 0x3f
+#define BIT_XTAL_CAP_XI_8197F(x)                                               \
+	(((x) & BIT_MASK_XTAL_CAP_XI_8197F) << BIT_SHIFT_XTAL_CAP_XI_8197F)
+#define BITS_XTAL_CAP_XI_8197F                                                 \
+	(BIT_MASK_XTAL_CAP_XI_8197F << BIT_SHIFT_XTAL_CAP_XI_8197F)
+#define BIT_CLEAR_XTAL_CAP_XI_8197F(x) ((x) & (~BITS_XTAL_CAP_XI_8197F))
+#define BIT_GET_XTAL_CAP_XI_8197F(x)                                           \
+	(((x) >> BIT_SHIFT_XTAL_CAP_XI_8197F) & BIT_MASK_XTAL_CAP_XI_8197F)
+#define BIT_SET_XTAL_CAP_XI_8197F(x, v)                                        \
+	(BIT_CLEAR_XTAL_CAP_XI_8197F(x) | BIT_XTAL_CAP_XI_8197F(v))
+
+#define BIT_SHIFT_XTAL_DRV_DIGI_8197F 23
+#define BIT_MASK_XTAL_DRV_DIGI_8197F 0x3
+#define BIT_XTAL_DRV_DIGI_8197F(x)                                             \
+	(((x) & BIT_MASK_XTAL_DRV_DIGI_8197F) << BIT_SHIFT_XTAL_DRV_DIGI_8197F)
+#define BITS_XTAL_DRV_DIGI_8197F                                               \
+	(BIT_MASK_XTAL_DRV_DIGI_8197F << BIT_SHIFT_XTAL_DRV_DIGI_8197F)
+#define BIT_CLEAR_XTAL_DRV_DIGI_8197F(x) ((x) & (~BITS_XTAL_DRV_DIGI_8197F))
+#define BIT_GET_XTAL_DRV_DIGI_8197F(x)                                         \
+	(((x) >> BIT_SHIFT_XTAL_DRV_DIGI_8197F) & BIT_MASK_XTAL_DRV_DIGI_8197F)
+#define BIT_SET_XTAL_DRV_DIGI_8197F(x, v)                                      \
+	(BIT_CLEAR_XTAL_DRV_DIGI_8197F(x) | BIT_XTAL_DRV_DIGI_8197F(v))
+
+#define BIT_XTAL_DRV_USB_BIT1_8197F BIT(22)
+
+#define BIT_SHIFT_MAC_CLK_SEL_8197F 20
+#define BIT_MASK_MAC_CLK_SEL_8197F 0x3
+#define BIT_MAC_CLK_SEL_8197F(x)                                               \
+	(((x) & BIT_MASK_MAC_CLK_SEL_8197F) << BIT_SHIFT_MAC_CLK_SEL_8197F)
+#define BITS_MAC_CLK_SEL_8197F                                                 \
+	(BIT_MASK_MAC_CLK_SEL_8197F << BIT_SHIFT_MAC_CLK_SEL_8197F)
+#define BIT_CLEAR_MAC_CLK_SEL_8197F(x) ((x) & (~BITS_MAC_CLK_SEL_8197F))
+#define BIT_GET_MAC_CLK_SEL_8197F(x)                                           \
+	(((x) >> BIT_SHIFT_MAC_CLK_SEL_8197F) & BIT_MASK_MAC_CLK_SEL_8197F)
+#define BIT_SET_MAC_CLK_SEL_8197F(x, v)                                        \
+	(BIT_CLEAR_MAC_CLK_SEL_8197F(x) | BIT_MAC_CLK_SEL_8197F(v))
+
+#define BIT_XTAL_DRV_USB_BIT0_8197F BIT(19)
+
+#define BIT_SHIFT_XTAL_DRV_AFE_8197F 17
+#define BIT_MASK_XTAL_DRV_AFE_8197F 0x3
+#define BIT_XTAL_DRV_AFE_8197F(x)                                              \
+	(((x) & BIT_MASK_XTAL_DRV_AFE_8197F) << BIT_SHIFT_XTAL_DRV_AFE_8197F)
+#define BITS_XTAL_DRV_AFE_8197F                                                \
+	(BIT_MASK_XTAL_DRV_AFE_8197F << BIT_SHIFT_XTAL_DRV_AFE_8197F)
+#define BIT_CLEAR_XTAL_DRV_AFE_8197F(x) ((x) & (~BITS_XTAL_DRV_AFE_8197F))
+#define BIT_GET_XTAL_DRV_AFE_8197F(x)                                          \
+	(((x) >> BIT_SHIFT_XTAL_DRV_AFE_8197F) & BIT_MASK_XTAL_DRV_AFE_8197F)
+#define BIT_SET_XTAL_DRV_AFE_8197F(x, v)                                       \
+	(BIT_CLEAR_XTAL_DRV_AFE_8197F(x) | BIT_XTAL_DRV_AFE_8197F(v))
+
+#define BIT_SHIFT_XTAL_DRV_RF2_8197F 15
+#define BIT_MASK_XTAL_DRV_RF2_8197F 0x3
+#define BIT_XTAL_DRV_RF2_8197F(x)                                              \
+	(((x) & BIT_MASK_XTAL_DRV_RF2_8197F) << BIT_SHIFT_XTAL_DRV_RF2_8197F)
+#define BITS_XTAL_DRV_RF2_8197F                                                \
+	(BIT_MASK_XTAL_DRV_RF2_8197F << BIT_SHIFT_XTAL_DRV_RF2_8197F)
+#define BIT_CLEAR_XTAL_DRV_RF2_8197F(x) ((x) & (~BITS_XTAL_DRV_RF2_8197F))
+#define BIT_GET_XTAL_DRV_RF2_8197F(x)                                          \
+	(((x) >> BIT_SHIFT_XTAL_DRV_RF2_8197F) & BIT_MASK_XTAL_DRV_RF2_8197F)
+#define BIT_SET_XTAL_DRV_RF2_8197F(x, v)                                       \
+	(BIT_CLEAR_XTAL_DRV_RF2_8197F(x) | BIT_XTAL_DRV_RF2_8197F(v))
+
+#define BIT_SHIFT_XTAL_DRV_RF1_8197F 13
+#define BIT_MASK_XTAL_DRV_RF1_8197F 0x3
+#define BIT_XTAL_DRV_RF1_8197F(x)                                              \
+	(((x) & BIT_MASK_XTAL_DRV_RF1_8197F) << BIT_SHIFT_XTAL_DRV_RF1_8197F)
+#define BITS_XTAL_DRV_RF1_8197F                                                \
+	(BIT_MASK_XTAL_DRV_RF1_8197F << BIT_SHIFT_XTAL_DRV_RF1_8197F)
+#define BIT_CLEAR_XTAL_DRV_RF1_8197F(x) ((x) & (~BITS_XTAL_DRV_RF1_8197F))
+#define BIT_GET_XTAL_DRV_RF1_8197F(x)                                          \
+	(((x) >> BIT_SHIFT_XTAL_DRV_RF1_8197F) & BIT_MASK_XTAL_DRV_RF1_8197F)
+#define BIT_SET_XTAL_DRV_RF1_8197F(x, v)                                       \
+	(BIT_CLEAR_XTAL_DRV_RF1_8197F(x) | BIT_XTAL_DRV_RF1_8197F(v))
+
+#define BIT_XTAL_DELAY_DIGI_8197F BIT(12)
+#define BIT_XTAL_DELAY_USB_8197F BIT(11)
+#define BIT_XTAL_DELAY_AFE_8197F BIT(10)
+#define BIT_XTAL_LP_V1_8197F BIT(9)
+#define BIT_XTAL_GM_SEP_V1_8197F BIT(8)
+#define BIT_XTAL_LDO_VREF_V1_8197F BIT(7)
+#define BIT_XTAL_XQSEL_RF_8197F BIT(6)
+#define BIT_XTAL_XQSEL_8197F BIT(5)
+
+#define BIT_SHIFT_XTAL_GMN_V1_8197F 3
+#define BIT_MASK_XTAL_GMN_V1_8197F 0x3
+#define BIT_XTAL_GMN_V1_8197F(x)                                               \
+	(((x) & BIT_MASK_XTAL_GMN_V1_8197F) << BIT_SHIFT_XTAL_GMN_V1_8197F)
+#define BITS_XTAL_GMN_V1_8197F                                                 \
+	(BIT_MASK_XTAL_GMN_V1_8197F << BIT_SHIFT_XTAL_GMN_V1_8197F)
+#define BIT_CLEAR_XTAL_GMN_V1_8197F(x) ((x) & (~BITS_XTAL_GMN_V1_8197F))
+#define BIT_GET_XTAL_GMN_V1_8197F(x)                                           \
+	(((x) >> BIT_SHIFT_XTAL_GMN_V1_8197F) & BIT_MASK_XTAL_GMN_V1_8197F)
+#define BIT_SET_XTAL_GMN_V1_8197F(x, v)                                        \
+	(BIT_CLEAR_XTAL_GMN_V1_8197F(x) | BIT_XTAL_GMN_V1_8197F(v))
+
+#define BIT_SHIFT_XTAL_GMP_V1_8197F 1
+#define BIT_MASK_XTAL_GMP_V1_8197F 0x3
+#define BIT_XTAL_GMP_V1_8197F(x)                                               \
+	(((x) & BIT_MASK_XTAL_GMP_V1_8197F) << BIT_SHIFT_XTAL_GMP_V1_8197F)
+#define BITS_XTAL_GMP_V1_8197F                                                 \
+	(BIT_MASK_XTAL_GMP_V1_8197F << BIT_SHIFT_XTAL_GMP_V1_8197F)
+#define BIT_CLEAR_XTAL_GMP_V1_8197F(x) ((x) & (~BITS_XTAL_GMP_V1_8197F))
+#define BIT_GET_XTAL_GMP_V1_8197F(x)                                           \
+	(((x) >> BIT_SHIFT_XTAL_GMP_V1_8197F) & BIT_MASK_XTAL_GMP_V1_8197F)
+#define BIT_SET_XTAL_GMP_V1_8197F(x, v)                                        \
+	(BIT_CLEAR_XTAL_GMP_V1_8197F(x) | BIT_XTAL_GMP_V1_8197F(v))
+
+#define BIT_XTAL_EN_8197F BIT(0)
+
+/* 2 REG_AFE_CTRL2_8197F */
+
+#define BIT_SHIFT_RS_SET_V2_8197F 26
+#define BIT_MASK_RS_SET_V2_8197F 0x7
+#define BIT_RS_SET_V2_8197F(x)                                                 \
+	(((x) & BIT_MASK_RS_SET_V2_8197F) << BIT_SHIFT_RS_SET_V2_8197F)
+#define BITS_RS_SET_V2_8197F                                                   \
+	(BIT_MASK_RS_SET_V2_8197F << BIT_SHIFT_RS_SET_V2_8197F)
+#define BIT_CLEAR_RS_SET_V2_8197F(x) ((x) & (~BITS_RS_SET_V2_8197F))
+#define BIT_GET_RS_SET_V2_8197F(x)                                             \
+	(((x) >> BIT_SHIFT_RS_SET_V2_8197F) & BIT_MASK_RS_SET_V2_8197F)
+#define BIT_SET_RS_SET_V2_8197F(x, v)                                          \
+	(BIT_CLEAR_RS_SET_V2_8197F(x) | BIT_RS_SET_V2_8197F(v))
+
+#define BIT_SHIFT_CP_BIAS_V2_8197F 18
+#define BIT_MASK_CP_BIAS_V2_8197F 0x7
+#define BIT_CP_BIAS_V2_8197F(x)                                                \
+	(((x) & BIT_MASK_CP_BIAS_V2_8197F) << BIT_SHIFT_CP_BIAS_V2_8197F)
+#define BITS_CP_BIAS_V2_8197F                                                  \
+	(BIT_MASK_CP_BIAS_V2_8197F << BIT_SHIFT_CP_BIAS_V2_8197F)
+#define BIT_CLEAR_CP_BIAS_V2_8197F(x) ((x) & (~BITS_CP_BIAS_V2_8197F))
+#define BIT_GET_CP_BIAS_V2_8197F(x)                                            \
+	(((x) >> BIT_SHIFT_CP_BIAS_V2_8197F) & BIT_MASK_CP_BIAS_V2_8197F)
+#define BIT_SET_CP_BIAS_V2_8197F(x, v)                                         \
+	(BIT_CLEAR_CP_BIAS_V2_8197F(x) | BIT_CP_BIAS_V2_8197F(v))
+
+#define BIT_FREF_SEL_8197F BIT(16)
+
+#define BIT_SHIFT_MCCO_V2_8197F 14
+#define BIT_MASK_MCCO_V2_8197F 0x3
+#define BIT_MCCO_V2_8197F(x)                                                   \
+	(((x) & BIT_MASK_MCCO_V2_8197F) << BIT_SHIFT_MCCO_V2_8197F)
+#define BITS_MCCO_V2_8197F (BIT_MASK_MCCO_V2_8197F << BIT_SHIFT_MCCO_V2_8197F)
+#define BIT_CLEAR_MCCO_V2_8197F(x) ((x) & (~BITS_MCCO_V2_8197F))
+#define BIT_GET_MCCO_V2_8197F(x)                                               \
+	(((x) >> BIT_SHIFT_MCCO_V2_8197F) & BIT_MASK_MCCO_V2_8197F)
+#define BIT_SET_MCCO_V2_8197F(x, v)                                            \
+	(BIT_CLEAR_MCCO_V2_8197F(x) | BIT_MCCO_V2_8197F(v))
+
+#define BIT_SHIFT_CK320_EN_8197F 12
+#define BIT_MASK_CK320_EN_8197F 0x3
+#define BIT_CK320_EN_8197F(x)                                                  \
+	(((x) & BIT_MASK_CK320_EN_8197F) << BIT_SHIFT_CK320_EN_8197F)
+#define BITS_CK320_EN_8197F                                                    \
+	(BIT_MASK_CK320_EN_8197F << BIT_SHIFT_CK320_EN_8197F)
+#define BIT_CLEAR_CK320_EN_8197F(x) ((x) & (~BITS_CK320_EN_8197F))
+#define BIT_GET_CK320_EN_8197F(x)                                              \
+	(((x) >> BIT_SHIFT_CK320_EN_8197F) & BIT_MASK_CK320_EN_8197F)
+#define BIT_SET_CK320_EN_8197F(x, v)                                           \
+	(BIT_CLEAR_CK320_EN_8197F(x) | BIT_CK320_EN_8197F(v))
+
+#define BIT_AGPIO_GPO_8197F BIT(9)
+
+#define BIT_SHIFT_AGPIO_DRV_8197F 7
+#define BIT_MASK_AGPIO_DRV_8197F 0x3
+#define BIT_AGPIO_DRV_8197F(x)                                                 \
+	(((x) & BIT_MASK_AGPIO_DRV_8197F) << BIT_SHIFT_AGPIO_DRV_8197F)
+#define BITS_AGPIO_DRV_8197F                                                   \
+	(BIT_MASK_AGPIO_DRV_8197F << BIT_SHIFT_AGPIO_DRV_8197F)
+#define BIT_CLEAR_AGPIO_DRV_8197F(x) ((x) & (~BITS_AGPIO_DRV_8197F))
+#define BIT_GET_AGPIO_DRV_8197F(x)                                             \
+	(((x) >> BIT_SHIFT_AGPIO_DRV_8197F) & BIT_MASK_AGPIO_DRV_8197F)
+#define BIT_SET_AGPIO_DRV_8197F(x, v)                                          \
+	(BIT_CLEAR_AGPIO_DRV_8197F(x) | BIT_AGPIO_DRV_8197F(v))
+
+#define BIT_SHIFT_XTAL_CAP_XO_8197F 1
+#define BIT_MASK_XTAL_CAP_XO_8197F 0x3f
+#define BIT_XTAL_CAP_XO_8197F(x)                                               \
+	(((x) & BIT_MASK_XTAL_CAP_XO_8197F) << BIT_SHIFT_XTAL_CAP_XO_8197F)
+#define BITS_XTAL_CAP_XO_8197F                                                 \
+	(BIT_MASK_XTAL_CAP_XO_8197F << BIT_SHIFT_XTAL_CAP_XO_8197F)
+#define BIT_CLEAR_XTAL_CAP_XO_8197F(x) ((x) & (~BITS_XTAL_CAP_XO_8197F))
+#define BIT_GET_XTAL_CAP_XO_8197F(x)                                           \
+	(((x) >> BIT_SHIFT_XTAL_CAP_XO_8197F) & BIT_MASK_XTAL_CAP_XO_8197F)
+#define BIT_SET_XTAL_CAP_XO_8197F(x, v)                                        \
+	(BIT_CLEAR_XTAL_CAP_XO_8197F(x) | BIT_XTAL_CAP_XO_8197F(v))
+
+#define BIT_POW_PLL_8197F BIT(0)
+
+/* 2 REG_AFE_CTRL3_8197F */
+
+#define BIT_SHIFT_PS_V2_8197F 7
+#define BIT_MASK_PS_V2_8197F 0x7
+#define BIT_PS_V2_8197F(x)                                                     \
+	(((x) & BIT_MASK_PS_V2_8197F) << BIT_SHIFT_PS_V2_8197F)
+#define BITS_PS_V2_8197F (BIT_MASK_PS_V2_8197F << BIT_SHIFT_PS_V2_8197F)
+#define BIT_CLEAR_PS_V2_8197F(x) ((x) & (~BITS_PS_V2_8197F))
+#define BIT_GET_PS_V2_8197F(x)                                                 \
+	(((x) >> BIT_SHIFT_PS_V2_8197F) & BIT_MASK_PS_V2_8197F)
+#define BIT_SET_PS_V2_8197F(x, v)                                              \
+	(BIT_CLEAR_PS_V2_8197F(x) | BIT_PS_V2_8197F(v))
+
+#define BIT_PSEN_8197F BIT(6)
+#define BIT_DOGENB_8197F BIT(5)
+
+/* 2 REG_EFUSE_CTRL_8197F */
+#define BIT_EF_FLAG_8197F BIT(31)
+
+#define BIT_SHIFT_EF_PGPD_8197F 28
+#define BIT_MASK_EF_PGPD_8197F 0x7
+#define BIT_EF_PGPD_8197F(x)                                                   \
+	(((x) & BIT_MASK_EF_PGPD_8197F) << BIT_SHIFT_EF_PGPD_8197F)
+#define BITS_EF_PGPD_8197F (BIT_MASK_EF_PGPD_8197F << BIT_SHIFT_EF_PGPD_8197F)
+#define BIT_CLEAR_EF_PGPD_8197F(x) ((x) & (~BITS_EF_PGPD_8197F))
+#define BIT_GET_EF_PGPD_8197F(x)                                               \
+	(((x) >> BIT_SHIFT_EF_PGPD_8197F) & BIT_MASK_EF_PGPD_8197F)
+#define BIT_SET_EF_PGPD_8197F(x, v)                                            \
+	(BIT_CLEAR_EF_PGPD_8197F(x) | BIT_EF_PGPD_8197F(v))
+
+#define BIT_SHIFT_EF_RDT_8197F 24
+#define BIT_MASK_EF_RDT_8197F 0xf
+#define BIT_EF_RDT_8197F(x)                                                    \
+	(((x) & BIT_MASK_EF_RDT_8197F) << BIT_SHIFT_EF_RDT_8197F)
+#define BITS_EF_RDT_8197F (BIT_MASK_EF_RDT_8197F << BIT_SHIFT_EF_RDT_8197F)
+#define BIT_CLEAR_EF_RDT_8197F(x) ((x) & (~BITS_EF_RDT_8197F))
+#define BIT_GET_EF_RDT_8197F(x)                                                \
+	(((x) >> BIT_SHIFT_EF_RDT_8197F) & BIT_MASK_EF_RDT_8197F)
+#define BIT_SET_EF_RDT_8197F(x, v)                                             \
+	(BIT_CLEAR_EF_RDT_8197F(x) | BIT_EF_RDT_8197F(v))
+
+#define BIT_SHIFT_EF_PGTS_8197F 20
+#define BIT_MASK_EF_PGTS_8197F 0xf
+#define BIT_EF_PGTS_8197F(x)                                                   \
+	(((x) & BIT_MASK_EF_PGTS_8197F) << BIT_SHIFT_EF_PGTS_8197F)
+#define BITS_EF_PGTS_8197F (BIT_MASK_EF_PGTS_8197F << BIT_SHIFT_EF_PGTS_8197F)
+#define BIT_CLEAR_EF_PGTS_8197F(x) ((x) & (~BITS_EF_PGTS_8197F))
+#define BIT_GET_EF_PGTS_8197F(x)                                               \
+	(((x) >> BIT_SHIFT_EF_PGTS_8197F) & BIT_MASK_EF_PGTS_8197F)
+#define BIT_SET_EF_PGTS_8197F(x, v)                                            \
+	(BIT_CLEAR_EF_PGTS_8197F(x) | BIT_EF_PGTS_8197F(v))
+
+#define BIT_EF_PDWN_8197F BIT(19)
+#define BIT_EF_ALDEN_8197F BIT(18)
+
+#define BIT_SHIFT_EF_ADDR_8197F 8
+#define BIT_MASK_EF_ADDR_8197F 0x3ff
+#define BIT_EF_ADDR_8197F(x)                                                   \
+	(((x) & BIT_MASK_EF_ADDR_8197F) << BIT_SHIFT_EF_ADDR_8197F)
+#define BITS_EF_ADDR_8197F (BIT_MASK_EF_ADDR_8197F << BIT_SHIFT_EF_ADDR_8197F)
+#define BIT_CLEAR_EF_ADDR_8197F(x) ((x) & (~BITS_EF_ADDR_8197F))
+#define BIT_GET_EF_ADDR_8197F(x)                                               \
+	(((x) >> BIT_SHIFT_EF_ADDR_8197F) & BIT_MASK_EF_ADDR_8197F)
+#define BIT_SET_EF_ADDR_8197F(x, v)                                            \
+	(BIT_CLEAR_EF_ADDR_8197F(x) | BIT_EF_ADDR_8197F(v))
+
+#define BIT_SHIFT_EF_DATA_8197F 0
+#define BIT_MASK_EF_DATA_8197F 0xff
+#define BIT_EF_DATA_8197F(x)                                                   \
+	(((x) & BIT_MASK_EF_DATA_8197F) << BIT_SHIFT_EF_DATA_8197F)
+#define BITS_EF_DATA_8197F (BIT_MASK_EF_DATA_8197F << BIT_SHIFT_EF_DATA_8197F)
+#define BIT_CLEAR_EF_DATA_8197F(x) ((x) & (~BITS_EF_DATA_8197F))
+#define BIT_GET_EF_DATA_8197F(x)                                               \
+	(((x) >> BIT_SHIFT_EF_DATA_8197F) & BIT_MASK_EF_DATA_8197F)
+#define BIT_SET_EF_DATA_8197F(x, v)                                            \
+	(BIT_CLEAR_EF_DATA_8197F(x) | BIT_EF_DATA_8197F(v))
+
+/* 2 REG_LDO_EFUSE_CTRL_8197F */
+#define BIT_LDOE25_EN_8197F BIT(31)
+
+#define BIT_SHIFT_LDOE25_V12ADJ_L_8197F 27
+#define BIT_MASK_LDOE25_V12ADJ_L_8197F 0xf
+#define BIT_LDOE25_V12ADJ_L_8197F(x)                                           \
+	(((x) & BIT_MASK_LDOE25_V12ADJ_L_8197F)                                \
+	 << BIT_SHIFT_LDOE25_V12ADJ_L_8197F)
+#define BITS_LDOE25_V12ADJ_L_8197F                                             \
+	(BIT_MASK_LDOE25_V12ADJ_L_8197F << BIT_SHIFT_LDOE25_V12ADJ_L_8197F)
+#define BIT_CLEAR_LDOE25_V12ADJ_L_8197F(x) ((x) & (~BITS_LDOE25_V12ADJ_L_8197F))
+#define BIT_GET_LDOE25_V12ADJ_L_8197F(x)                                       \
+	(((x) >> BIT_SHIFT_LDOE25_V12ADJ_L_8197F) &                            \
+	 BIT_MASK_LDOE25_V12ADJ_L_8197F)
+#define BIT_SET_LDOE25_V12ADJ_L_8197F(x, v)                                    \
+	(BIT_CLEAR_LDOE25_V12ADJ_L_8197F(x) | BIT_LDOE25_V12ADJ_L_8197F(v))
+
+#define BIT_SHIFT_EF_SCAN_START_V1_8197F 16
+#define BIT_MASK_EF_SCAN_START_V1_8197F 0x3ff
+#define BIT_EF_SCAN_START_V1_8197F(x)                                          \
+	(((x) & BIT_MASK_EF_SCAN_START_V1_8197F)                               \
+	 << BIT_SHIFT_EF_SCAN_START_V1_8197F)
+#define BITS_EF_SCAN_START_V1_8197F                                            \
+	(BIT_MASK_EF_SCAN_START_V1_8197F << BIT_SHIFT_EF_SCAN_START_V1_8197F)
+#define BIT_CLEAR_EF_SCAN_START_V1_8197F(x)                                    \
+	((x) & (~BITS_EF_SCAN_START_V1_8197F))
+#define BIT_GET_EF_SCAN_START_V1_8197F(x)                                      \
+	(((x) >> BIT_SHIFT_EF_SCAN_START_V1_8197F) &                           \
+	 BIT_MASK_EF_SCAN_START_V1_8197F)
+#define BIT_SET_EF_SCAN_START_V1_8197F(x, v)                                   \
+	(BIT_CLEAR_EF_SCAN_START_V1_8197F(x) | BIT_EF_SCAN_START_V1_8197F(v))
+
+#define BIT_SHIFT_EF_SCAN_END_8197F 12
+#define BIT_MASK_EF_SCAN_END_8197F 0xf
+#define BIT_EF_SCAN_END_8197F(x)                                               \
+	(((x) & BIT_MASK_EF_SCAN_END_8197F) << BIT_SHIFT_EF_SCAN_END_8197F)
+#define BITS_EF_SCAN_END_8197F                                                 \
+	(BIT_MASK_EF_SCAN_END_8197F << BIT_SHIFT_EF_SCAN_END_8197F)
+#define BIT_CLEAR_EF_SCAN_END_8197F(x) ((x) & (~BITS_EF_SCAN_END_8197F))
+#define BIT_GET_EF_SCAN_END_8197F(x)                                           \
+	(((x) >> BIT_SHIFT_EF_SCAN_END_8197F) & BIT_MASK_EF_SCAN_END_8197F)
+#define BIT_SET_EF_SCAN_END_8197F(x, v)                                        \
+	(BIT_CLEAR_EF_SCAN_END_8197F(x) | BIT_EF_SCAN_END_8197F(v))
+
+#define BIT_SHIFT_EF_CELL_SEL_8197F 8
+#define BIT_MASK_EF_CELL_SEL_8197F 0x3
+#define BIT_EF_CELL_SEL_8197F(x)                                               \
+	(((x) & BIT_MASK_EF_CELL_SEL_8197F) << BIT_SHIFT_EF_CELL_SEL_8197F)
+#define BITS_EF_CELL_SEL_8197F                                                 \
+	(BIT_MASK_EF_CELL_SEL_8197F << BIT_SHIFT_EF_CELL_SEL_8197F)
+#define BIT_CLEAR_EF_CELL_SEL_8197F(x) ((x) & (~BITS_EF_CELL_SEL_8197F))
+#define BIT_GET_EF_CELL_SEL_8197F(x)                                           \
+	(((x) >> BIT_SHIFT_EF_CELL_SEL_8197F) & BIT_MASK_EF_CELL_SEL_8197F)
+#define BIT_SET_EF_CELL_SEL_8197F(x, v)                                        \
+	(BIT_CLEAR_EF_CELL_SEL_8197F(x) | BIT_EF_CELL_SEL_8197F(v))
+
+#define BIT_EF_TRPT_8197F BIT(7)
+
+#define BIT_SHIFT_EF_TTHD_8197F 0
+#define BIT_MASK_EF_TTHD_8197F 0x7f
+#define BIT_EF_TTHD_8197F(x)                                                   \
+	(((x) & BIT_MASK_EF_TTHD_8197F) << BIT_SHIFT_EF_TTHD_8197F)
+#define BITS_EF_TTHD_8197F (BIT_MASK_EF_TTHD_8197F << BIT_SHIFT_EF_TTHD_8197F)
+#define BIT_CLEAR_EF_TTHD_8197F(x) ((x) & (~BITS_EF_TTHD_8197F))
+#define BIT_GET_EF_TTHD_8197F(x)                                               \
+	(((x) >> BIT_SHIFT_EF_TTHD_8197F) & BIT_MASK_EF_TTHD_8197F)
+#define BIT_SET_EF_TTHD_8197F(x, v)                                            \
+	(BIT_CLEAR_EF_TTHD_8197F(x) | BIT_EF_TTHD_8197F(v))
+
+/* 2 REG_PWR_OPTION_CTRL_8197F */
+
+#define BIT_SHIFT_DBG_SEL_V1_8197F 16
+#define BIT_MASK_DBG_SEL_V1_8197F 0xff
+#define BIT_DBG_SEL_V1_8197F(x)                                                \
+	(((x) & BIT_MASK_DBG_SEL_V1_8197F) << BIT_SHIFT_DBG_SEL_V1_8197F)
+#define BITS_DBG_SEL_V1_8197F                                                  \
+	(BIT_MASK_DBG_SEL_V1_8197F << BIT_SHIFT_DBG_SEL_V1_8197F)
+#define BIT_CLEAR_DBG_SEL_V1_8197F(x) ((x) & (~BITS_DBG_SEL_V1_8197F))
+#define BIT_GET_DBG_SEL_V1_8197F(x)                                            \
+	(((x) >> BIT_SHIFT_DBG_SEL_V1_8197F) & BIT_MASK_DBG_SEL_V1_8197F)
+#define BIT_SET_DBG_SEL_V1_8197F(x, v)                                         \
+	(BIT_CLEAR_DBG_SEL_V1_8197F(x) | BIT_DBG_SEL_V1_8197F(v))
+
+#define BIT_SHIFT_DBG_SEL_BYTE_8197F 14
+#define BIT_MASK_DBG_SEL_BYTE_8197F 0x3
+#define BIT_DBG_SEL_BYTE_8197F(x)                                              \
+	(((x) & BIT_MASK_DBG_SEL_BYTE_8197F) << BIT_SHIFT_DBG_SEL_BYTE_8197F)
+#define BITS_DBG_SEL_BYTE_8197F                                                \
+	(BIT_MASK_DBG_SEL_BYTE_8197F << BIT_SHIFT_DBG_SEL_BYTE_8197F)
+#define BIT_CLEAR_DBG_SEL_BYTE_8197F(x) ((x) & (~BITS_DBG_SEL_BYTE_8197F))
+#define BIT_GET_DBG_SEL_BYTE_8197F(x)                                          \
+	(((x) >> BIT_SHIFT_DBG_SEL_BYTE_8197F) & BIT_MASK_DBG_SEL_BYTE_8197F)
+#define BIT_SET_DBG_SEL_BYTE_8197F(x, v)                                       \
+	(BIT_CLEAR_DBG_SEL_BYTE_8197F(x) | BIT_DBG_SEL_BYTE_8197F(v))
+
+#define BIT_SHIFT_STD_L1_V1_8197F 12
+#define BIT_MASK_STD_L1_V1_8197F 0x3
+#define BIT_STD_L1_V1_8197F(x)                                                 \
+	(((x) & BIT_MASK_STD_L1_V1_8197F) << BIT_SHIFT_STD_L1_V1_8197F)
+#define BITS_STD_L1_V1_8197F                                                   \
+	(BIT_MASK_STD_L1_V1_8197F << BIT_SHIFT_STD_L1_V1_8197F)
+#define BIT_CLEAR_STD_L1_V1_8197F(x) ((x) & (~BITS_STD_L1_V1_8197F))
+#define BIT_GET_STD_L1_V1_8197F(x)                                             \
+	(((x) >> BIT_SHIFT_STD_L1_V1_8197F) & BIT_MASK_STD_L1_V1_8197F)
+#define BIT_SET_STD_L1_V1_8197F(x, v)                                          \
+	(BIT_CLEAR_STD_L1_V1_8197F(x) | BIT_STD_L1_V1_8197F(v))
+
+#define BIT_SYSON_DBG_PAD_E2_8197F BIT(11)
+#define BIT_SYSON_LED_PAD_E2_8197F BIT(10)
+#define BIT_SYSON_GPEE_PAD_E2_8197F BIT(9)
+#define BIT_SYSON_PCI_PAD_E2_8197F BIT(8)
+#define BIT_AUTO_SW_LDO_VOL_EN_8197F BIT(7)
+
+#define BIT_SHIFT_SYSON_SPS0WWV_WT_8197F 4
+#define BIT_MASK_SYSON_SPS0WWV_WT_8197F 0x3
+#define BIT_SYSON_SPS0WWV_WT_8197F(x)                                          \
+	(((x) & BIT_MASK_SYSON_SPS0WWV_WT_8197F)                               \
+	 << BIT_SHIFT_SYSON_SPS0WWV_WT_8197F)
+#define BITS_SYSON_SPS0WWV_WT_8197F                                            \
+	(BIT_MASK_SYSON_SPS0WWV_WT_8197F << BIT_SHIFT_SYSON_SPS0WWV_WT_8197F)
+#define BIT_CLEAR_SYSON_SPS0WWV_WT_8197F(x)                                    \
+	((x) & (~BITS_SYSON_SPS0WWV_WT_8197F))
+#define BIT_GET_SYSON_SPS0WWV_WT_8197F(x)                                      \
+	(((x) >> BIT_SHIFT_SYSON_SPS0WWV_WT_8197F) &                           \
+	 BIT_MASK_SYSON_SPS0WWV_WT_8197F)
+#define BIT_SET_SYSON_SPS0WWV_WT_8197F(x, v)                                   \
+	(BIT_CLEAR_SYSON_SPS0WWV_WT_8197F(x) | BIT_SYSON_SPS0WWV_WT_8197F(v))
+
+#define BIT_SHIFT_SYSON_SPS0LDO_WT_8197F 2
+#define BIT_MASK_SYSON_SPS0LDO_WT_8197F 0x3
+#define BIT_SYSON_SPS0LDO_WT_8197F(x)                                          \
+	(((x) & BIT_MASK_SYSON_SPS0LDO_WT_8197F)                               \
+	 << BIT_SHIFT_SYSON_SPS0LDO_WT_8197F)
+#define BITS_SYSON_SPS0LDO_WT_8197F                                            \
+	(BIT_MASK_SYSON_SPS0LDO_WT_8197F << BIT_SHIFT_SYSON_SPS0LDO_WT_8197F)
+#define BIT_CLEAR_SYSON_SPS0LDO_WT_8197F(x)                                    \
+	((x) & (~BITS_SYSON_SPS0LDO_WT_8197F))
+#define BIT_GET_SYSON_SPS0LDO_WT_8197F(x)                                      \
+	(((x) >> BIT_SHIFT_SYSON_SPS0LDO_WT_8197F) &                           \
+	 BIT_MASK_SYSON_SPS0LDO_WT_8197F)
+#define BIT_SET_SYSON_SPS0LDO_WT_8197F(x, v)                                   \
+	(BIT_CLEAR_SYSON_SPS0LDO_WT_8197F(x) | BIT_SYSON_SPS0LDO_WT_8197F(v))
+
+#define BIT_SHIFT_SYSON_RCLK_SCALE_8197F 0
+#define BIT_MASK_SYSON_RCLK_SCALE_8197F 0x3
+#define BIT_SYSON_RCLK_SCALE_8197F(x)                                          \
+	(((x) & BIT_MASK_SYSON_RCLK_SCALE_8197F)                               \
+	 << BIT_SHIFT_SYSON_RCLK_SCALE_8197F)
+#define BITS_SYSON_RCLK_SCALE_8197F                                            \
+	(BIT_MASK_SYSON_RCLK_SCALE_8197F << BIT_SHIFT_SYSON_RCLK_SCALE_8197F)
+#define BIT_CLEAR_SYSON_RCLK_SCALE_8197F(x)                                    \
+	((x) & (~BITS_SYSON_RCLK_SCALE_8197F))
+#define BIT_GET_SYSON_RCLK_SCALE_8197F(x)                                      \
+	(((x) >> BIT_SHIFT_SYSON_RCLK_SCALE_8197F) &                           \
+	 BIT_MASK_SYSON_RCLK_SCALE_8197F)
+#define BIT_SET_SYSON_RCLK_SCALE_8197F(x, v)                                   \
+	(BIT_CLEAR_SYSON_RCLK_SCALE_8197F(x) | BIT_SYSON_RCLK_SCALE_8197F(v))
+
+/* 2 REG_CAL_TIMER_8197F */
+
+#define BIT_SHIFT_MATCH_CNT_8197F 8
+#define BIT_MASK_MATCH_CNT_8197F 0xff
+#define BIT_MATCH_CNT_8197F(x)                                                 \
+	(((x) & BIT_MASK_MATCH_CNT_8197F) << BIT_SHIFT_MATCH_CNT_8197F)
+#define BITS_MATCH_CNT_8197F                                                   \
+	(BIT_MASK_MATCH_CNT_8197F << BIT_SHIFT_MATCH_CNT_8197F)
+#define BIT_CLEAR_MATCH_CNT_8197F(x) ((x) & (~BITS_MATCH_CNT_8197F))
+#define BIT_GET_MATCH_CNT_8197F(x)                                             \
+	(((x) >> BIT_SHIFT_MATCH_CNT_8197F) & BIT_MASK_MATCH_CNT_8197F)
+#define BIT_SET_MATCH_CNT_8197F(x, v)                                          \
+	(BIT_CLEAR_MATCH_CNT_8197F(x) | BIT_MATCH_CNT_8197F(v))
+
+#define BIT_SHIFT_CAL_SCAL_8197F 0
+#define BIT_MASK_CAL_SCAL_8197F 0xff
+#define BIT_CAL_SCAL_8197F(x)                                                  \
+	(((x) & BIT_MASK_CAL_SCAL_8197F) << BIT_SHIFT_CAL_SCAL_8197F)
+#define BITS_CAL_SCAL_8197F                                                    \
+	(BIT_MASK_CAL_SCAL_8197F << BIT_SHIFT_CAL_SCAL_8197F)
+#define BIT_CLEAR_CAL_SCAL_8197F(x) ((x) & (~BITS_CAL_SCAL_8197F))
+#define BIT_GET_CAL_SCAL_8197F(x)                                              \
+	(((x) >> BIT_SHIFT_CAL_SCAL_8197F) & BIT_MASK_CAL_SCAL_8197F)
+#define BIT_SET_CAL_SCAL_8197F(x, v)                                           \
+	(BIT_CLEAR_CAL_SCAL_8197F(x) | BIT_CAL_SCAL_8197F(v))
+
+/* 2 REG_ACLK_MON_8197F */
+
+#define BIT_SHIFT_RCLK_MON_8197F 5
+#define BIT_MASK_RCLK_MON_8197F 0x7ff
+#define BIT_RCLK_MON_8197F(x)                                                  \
+	(((x) & BIT_MASK_RCLK_MON_8197F) << BIT_SHIFT_RCLK_MON_8197F)
+#define BITS_RCLK_MON_8197F                                                    \
+	(BIT_MASK_RCLK_MON_8197F << BIT_SHIFT_RCLK_MON_8197F)
+#define BIT_CLEAR_RCLK_MON_8197F(x) ((x) & (~BITS_RCLK_MON_8197F))
+#define BIT_GET_RCLK_MON_8197F(x)                                              \
+	(((x) >> BIT_SHIFT_RCLK_MON_8197F) & BIT_MASK_RCLK_MON_8197F)
+#define BIT_SET_RCLK_MON_8197F(x, v)                                           \
+	(BIT_CLEAR_RCLK_MON_8197F(x) | BIT_RCLK_MON_8197F(v))
+
+#define BIT_CAL_EN_8197F BIT(4)
+
+#define BIT_SHIFT_DPSTU_8197F 2
+#define BIT_MASK_DPSTU_8197F 0x3
+#define BIT_DPSTU_8197F(x)                                                     \
+	(((x) & BIT_MASK_DPSTU_8197F) << BIT_SHIFT_DPSTU_8197F)
+#define BITS_DPSTU_8197F (BIT_MASK_DPSTU_8197F << BIT_SHIFT_DPSTU_8197F)
+#define BIT_CLEAR_DPSTU_8197F(x) ((x) & (~BITS_DPSTU_8197F))
+#define BIT_GET_DPSTU_8197F(x)                                                 \
+	(((x) >> BIT_SHIFT_DPSTU_8197F) & BIT_MASK_DPSTU_8197F)
+#define BIT_SET_DPSTU_8197F(x, v)                                              \
+	(BIT_CLEAR_DPSTU_8197F(x) | BIT_DPSTU_8197F(v))
+
+#define BIT_SUS_16X_8197F BIT(1)
+
+/* 2 REG_NOT_VALID_8197F */
+
+/* 2 REG_GPIO_MUXCFG_8197F */
+#define BIT_SIC_LOWEST_PRIORITY_8197F BIT(28)
+
+#define BIT_SHIFT_PIN_USECASE_8197F 24
+#define BIT_MASK_PIN_USECASE_8197F 0xf
+#define BIT_PIN_USECASE_8197F(x)                                               \
+	(((x) & BIT_MASK_PIN_USECASE_8197F) << BIT_SHIFT_PIN_USECASE_8197F)
+#define BITS_PIN_USECASE_8197F                                                 \
+	(BIT_MASK_PIN_USECASE_8197F << BIT_SHIFT_PIN_USECASE_8197F)
+#define BIT_CLEAR_PIN_USECASE_8197F(x) ((x) & (~BITS_PIN_USECASE_8197F))
+#define BIT_GET_PIN_USECASE_8197F(x)                                           \
+	(((x) >> BIT_SHIFT_PIN_USECASE_8197F) & BIT_MASK_PIN_USECASE_8197F)
+#define BIT_SET_PIN_USECASE_8197F(x, v)                                        \
+	(BIT_CLEAR_PIN_USECASE_8197F(x) | BIT_PIN_USECASE_8197F(v))
+
+#define BIT_FSPI_EN_8197F BIT(19)
+#define BIT_WL_RTS_EXT_32K_SEL_8197F BIT(18)
+#define BIT_WLGP_SPI_EN_8197F BIT(16)
+#define BIT_SIC_LBK_8197F BIT(15)
+#define BIT_ENHTP_8197F BIT(14)
+#define BIT_WLPHY_DBG_EN_8197F BIT(13)
+#define BIT_ENSIC_8197F BIT(12)
+#define BIT_SIC_SWRST_8197F BIT(11)
+#define BIT_PO_WIFI_PTA_PINS_8197F BIT(10)
+#define BIT_BTCOEX_MBOX_EN_8197F BIT(9)
+#define BIT_ENUART_8197F BIT(8)
+
+#define BIT_SHIFT_BTMODE_8197F 6
+#define BIT_MASK_BTMODE_8197F 0x3
+#define BIT_BTMODE_8197F(x)                                                    \
+	(((x) & BIT_MASK_BTMODE_8197F) << BIT_SHIFT_BTMODE_8197F)
+#define BITS_BTMODE_8197F (BIT_MASK_BTMODE_8197F << BIT_SHIFT_BTMODE_8197F)
+#define BIT_CLEAR_BTMODE_8197F(x) ((x) & (~BITS_BTMODE_8197F))
+#define BIT_GET_BTMODE_8197F(x)                                                \
+	(((x) >> BIT_SHIFT_BTMODE_8197F) & BIT_MASK_BTMODE_8197F)
+#define BIT_SET_BTMODE_8197F(x, v)                                             \
+	(BIT_CLEAR_BTMODE_8197F(x) | BIT_BTMODE_8197F(v))
+
+#define BIT_ENBT_8197F BIT(5)
+#define BIT_EROM_EN_8197F BIT(4)
+#define BIT_WLRFE_6_7_EN_8197F BIT(3)
+#define BIT_WLRFE_4_5_EN_8197F BIT(2)
+
+#define BIT_SHIFT_GPIOSEL_8197F 0
+#define BIT_MASK_GPIOSEL_8197F 0x3
+#define BIT_GPIOSEL_8197F(x)                                                   \
+	(((x) & BIT_MASK_GPIOSEL_8197F) << BIT_SHIFT_GPIOSEL_8197F)
+#define BITS_GPIOSEL_8197F (BIT_MASK_GPIOSEL_8197F << BIT_SHIFT_GPIOSEL_8197F)
+#define BIT_CLEAR_GPIOSEL_8197F(x) ((x) & (~BITS_GPIOSEL_8197F))
+#define BIT_GET_GPIOSEL_8197F(x)                                               \
+	(((x) >> BIT_SHIFT_GPIOSEL_8197F) & BIT_MASK_GPIOSEL_8197F)
+#define BIT_SET_GPIOSEL_8197F(x, v)                                            \
+	(BIT_CLEAR_GPIOSEL_8197F(x) | BIT_GPIOSEL_8197F(v))
+
+/* 2 REG_GPIO_PIN_CTRL_8197F */
+
+#define BIT_SHIFT_GPIO_MOD_7_TO_0_8197F 24
+#define BIT_MASK_GPIO_MOD_7_TO_0_8197F 0xff
+#define BIT_GPIO_MOD_7_TO_0_8197F(x)                                           \
+	(((x) & BIT_MASK_GPIO_MOD_7_TO_0_8197F)                                \
+	 << BIT_SHIFT_GPIO_MOD_7_TO_0_8197F)
+#define BITS_GPIO_MOD_7_TO_0_8197F                                             \
+	(BIT_MASK_GPIO_MOD_7_TO_0_8197F << BIT_SHIFT_GPIO_MOD_7_TO_0_8197F)
+#define BIT_CLEAR_GPIO_MOD_7_TO_0_8197F(x) ((x) & (~BITS_GPIO_MOD_7_TO_0_8197F))
+#define BIT_GET_GPIO_MOD_7_TO_0_8197F(x)                                       \
+	(((x) >> BIT_SHIFT_GPIO_MOD_7_TO_0_8197F) &                            \
+	 BIT_MASK_GPIO_MOD_7_TO_0_8197F)
+#define BIT_SET_GPIO_MOD_7_TO_0_8197F(x, v)                                    \
+	(BIT_CLEAR_GPIO_MOD_7_TO_0_8197F(x) | BIT_GPIO_MOD_7_TO_0_8197F(v))
+
+#define BIT_SHIFT_GPIO_IO_SEL_7_TO_0_8197F 16
+#define BIT_MASK_GPIO_IO_SEL_7_TO_0_8197F 0xff
+#define BIT_GPIO_IO_SEL_7_TO_0_8197F(x)                                        \
+	(((x) & BIT_MASK_GPIO_IO_SEL_7_TO_0_8197F)                             \
+	 << BIT_SHIFT_GPIO_IO_SEL_7_TO_0_8197F)
+#define BITS_GPIO_IO_SEL_7_TO_0_8197F                                          \
+	(BIT_MASK_GPIO_IO_SEL_7_TO_0_8197F                                     \
+	 << BIT_SHIFT_GPIO_IO_SEL_7_TO_0_8197F)
+#define BIT_CLEAR_GPIO_IO_SEL_7_TO_0_8197F(x)                                  \
+	((x) & (~BITS_GPIO_IO_SEL_7_TO_0_8197F))
+#define BIT_GET_GPIO_IO_SEL_7_TO_0_8197F(x)                                    \
+	(((x) >> BIT_SHIFT_GPIO_IO_SEL_7_TO_0_8197F) &                         \
+	 BIT_MASK_GPIO_IO_SEL_7_TO_0_8197F)
+#define BIT_SET_GPIO_IO_SEL_7_TO_0_8197F(x, v)                                 \
+	(BIT_CLEAR_GPIO_IO_SEL_7_TO_0_8197F(x) |                               \
+	 BIT_GPIO_IO_SEL_7_TO_0_8197F(v))
+
+#define BIT_SHIFT_GPIO_OUT_7_TO_0_8197F 8
+#define BIT_MASK_GPIO_OUT_7_TO_0_8197F 0xff
+#define BIT_GPIO_OUT_7_TO_0_8197F(x)                                           \
+	(((x) & BIT_MASK_GPIO_OUT_7_TO_0_8197F)                                \
+	 << BIT_SHIFT_GPIO_OUT_7_TO_0_8197F)
+#define BITS_GPIO_OUT_7_TO_0_8197F                                             \
+	(BIT_MASK_GPIO_OUT_7_TO_0_8197F << BIT_SHIFT_GPIO_OUT_7_TO_0_8197F)
+#define BIT_CLEAR_GPIO_OUT_7_TO_0_8197F(x) ((x) & (~BITS_GPIO_OUT_7_TO_0_8197F))
+#define BIT_GET_GPIO_OUT_7_TO_0_8197F(x)                                       \
+	(((x) >> BIT_SHIFT_GPIO_OUT_7_TO_0_8197F) &                            \
+	 BIT_MASK_GPIO_OUT_7_TO_0_8197F)
+#define BIT_SET_GPIO_OUT_7_TO_0_8197F(x, v)                                    \
+	(BIT_CLEAR_GPIO_OUT_7_TO_0_8197F(x) | BIT_GPIO_OUT_7_TO_0_8197F(v))
+
+#define BIT_SHIFT_GPIO_IN_7_TO_0_8197F 0
+#define BIT_MASK_GPIO_IN_7_TO_0_8197F 0xff
+#define BIT_GPIO_IN_7_TO_0_8197F(x)                                            \
+	(((x) & BIT_MASK_GPIO_IN_7_TO_0_8197F)                                 \
+	 << BIT_SHIFT_GPIO_IN_7_TO_0_8197F)
+#define BITS_GPIO_IN_7_TO_0_8197F                                              \
+	(BIT_MASK_GPIO_IN_7_TO_0_8197F << BIT_SHIFT_GPIO_IN_7_TO_0_8197F)
+#define BIT_CLEAR_GPIO_IN_7_TO_0_8197F(x) ((x) & (~BITS_GPIO_IN_7_TO_0_8197F))
+#define BIT_GET_GPIO_IN_7_TO_0_8197F(x)                                        \
+	(((x) >> BIT_SHIFT_GPIO_IN_7_TO_0_8197F) &                             \
+	 BIT_MASK_GPIO_IN_7_TO_0_8197F)
+#define BIT_SET_GPIO_IN_7_TO_0_8197F(x, v)                                     \
+	(BIT_CLEAR_GPIO_IN_7_TO_0_8197F(x) | BIT_GPIO_IN_7_TO_0_8197F(v))
+
+/* 2 REG_GPIO_INTM_8197F */
+
+#define BIT_SHIFT_MUXDBG_SEL_8197F 30
+#define BIT_MASK_MUXDBG_SEL_8197F 0x3
+#define BIT_MUXDBG_SEL_8197F(x)                                                \
+	(((x) & BIT_MASK_MUXDBG_SEL_8197F) << BIT_SHIFT_MUXDBG_SEL_8197F)
+#define BITS_MUXDBG_SEL_8197F                                                  \
+	(BIT_MASK_MUXDBG_SEL_8197F << BIT_SHIFT_MUXDBG_SEL_8197F)
+#define BIT_CLEAR_MUXDBG_SEL_8197F(x) ((x) & (~BITS_MUXDBG_SEL_8197F))
+#define BIT_GET_MUXDBG_SEL_8197F(x)                                            \
+	(((x) >> BIT_SHIFT_MUXDBG_SEL_8197F) & BIT_MASK_MUXDBG_SEL_8197F)
+#define BIT_SET_MUXDBG_SEL_8197F(x, v)                                         \
+	(BIT_CLEAR_MUXDBG_SEL_8197F(x) | BIT_MUXDBG_SEL_8197F(v))
+
+#define BIT_EXTWOL_SEL_8197F BIT(17)
+#define BIT_EXTWOL_EN_8197F BIT(16)
+#define BIT_GPIOF_INT_MD_8197F BIT(15)
+#define BIT_GPIOE_INT_MD_8197F BIT(14)
+#define BIT_GPIOD_INT_MD_8197F BIT(13)
+#define BIT_GPIOC_INT_MD_8197F BIT(12)
+#define BIT_GPIOB_INT_MD_8197F BIT(11)
+#define BIT_GPIOA_INT_MD_8197F BIT(10)
+#define BIT_GPIO9_INT_MD_8197F BIT(9)
+#define BIT_GPIO8_INT_MD_8197F BIT(8)
+#define BIT_GPIO7_INT_MD_8197F BIT(7)
+#define BIT_GPIO6_INT_MD_8197F BIT(6)
+#define BIT_GPIO5_INT_MD_8197F BIT(5)
+#define BIT_GPIO4_INT_MD_8197F BIT(4)
+#define BIT_GPIO3_INT_MD_8197F BIT(3)
+#define BIT_GPIO2_INT_MD_8197F BIT(2)
+#define BIT_GPIO1_INT_MD_8197F BIT(1)
+#define BIT_GPIO0_INT_MD_8197F BIT(0)
+
+/* 2 REG_LED_CFG_8197F */
+#define BIT_LNAON_SEL_EN_8197F BIT(26)
+#define BIT_PAPE_SEL_EN_8197F BIT(25)
+#define BIT_DPDT_WLBT_SEL_8197F BIT(24)
+#define BIT_DPDT_SEL_EN_8197F BIT(23)
+#define BIT_LED2DIS_V1_8197F BIT(22)
+#define BIT_LED2EN_8197F BIT(21)
+#define BIT_LED2PL_8197F BIT(20)
+#define BIT_LED2SV_8197F BIT(19)
+
+#define BIT_SHIFT_LED2CM_8197F 16
+#define BIT_MASK_LED2CM_8197F 0x7
+#define BIT_LED2CM_8197F(x)                                                    \
+	(((x) & BIT_MASK_LED2CM_8197F) << BIT_SHIFT_LED2CM_8197F)
+#define BITS_LED2CM_8197F (BIT_MASK_LED2CM_8197F << BIT_SHIFT_LED2CM_8197F)
+#define BIT_CLEAR_LED2CM_8197F(x) ((x) & (~BITS_LED2CM_8197F))
+#define BIT_GET_LED2CM_8197F(x)                                                \
+	(((x) >> BIT_SHIFT_LED2CM_8197F) & BIT_MASK_LED2CM_8197F)
+#define BIT_SET_LED2CM_8197F(x, v)                                             \
+	(BIT_CLEAR_LED2CM_8197F(x) | BIT_LED2CM_8197F(v))
+
+#define BIT_LED1DIS_8197F BIT(15)
+#define BIT_LED1PL_8197F BIT(12)
+#define BIT_LED1SV_8197F BIT(11)
+
+#define BIT_SHIFT_LED1CM_8197F 8
+#define BIT_MASK_LED1CM_8197F 0x7
+#define BIT_LED1CM_8197F(x)                                                    \
+	(((x) & BIT_MASK_LED1CM_8197F) << BIT_SHIFT_LED1CM_8197F)
+#define BITS_LED1CM_8197F (BIT_MASK_LED1CM_8197F << BIT_SHIFT_LED1CM_8197F)
+#define BIT_CLEAR_LED1CM_8197F(x) ((x) & (~BITS_LED1CM_8197F))
+#define BIT_GET_LED1CM_8197F(x)                                                \
+	(((x) >> BIT_SHIFT_LED1CM_8197F) & BIT_MASK_LED1CM_8197F)
+#define BIT_SET_LED1CM_8197F(x, v)                                             \
+	(BIT_CLEAR_LED1CM_8197F(x) | BIT_LED1CM_8197F(v))
+
+#define BIT_LED0DIS_8197F BIT(7)
+
+#define BIT_SHIFT_AFE_LDO_SWR_CHECK_8197F 5
+#define BIT_MASK_AFE_LDO_SWR_CHECK_8197F 0x3
+#define BIT_AFE_LDO_SWR_CHECK_8197F(x)                                         \
+	(((x) & BIT_MASK_AFE_LDO_SWR_CHECK_8197F)                              \
+	 << BIT_SHIFT_AFE_LDO_SWR_CHECK_8197F)
+#define BITS_AFE_LDO_SWR_CHECK_8197F                                           \
+	(BIT_MASK_AFE_LDO_SWR_CHECK_8197F << BIT_SHIFT_AFE_LDO_SWR_CHECK_8197F)
+#define BIT_CLEAR_AFE_LDO_SWR_CHECK_8197F(x)                                   \
+	((x) & (~BITS_AFE_LDO_SWR_CHECK_8197F))
+#define BIT_GET_AFE_LDO_SWR_CHECK_8197F(x)                                     \
+	(((x) >> BIT_SHIFT_AFE_LDO_SWR_CHECK_8197F) &                          \
+	 BIT_MASK_AFE_LDO_SWR_CHECK_8197F)
+#define BIT_SET_AFE_LDO_SWR_CHECK_8197F(x, v)                                  \
+	(BIT_CLEAR_AFE_LDO_SWR_CHECK_8197F(x) | BIT_AFE_LDO_SWR_CHECK_8197F(v))
+
+#define BIT_LED0PL_8197F BIT(4)
+#define BIT_LED0SV_8197F BIT(3)
+
+#define BIT_SHIFT_LED0CM_8197F 0
+#define BIT_MASK_LED0CM_8197F 0x7
+#define BIT_LED0CM_8197F(x)                                                    \
+	(((x) & BIT_MASK_LED0CM_8197F) << BIT_SHIFT_LED0CM_8197F)
+#define BITS_LED0CM_8197F (BIT_MASK_LED0CM_8197F << BIT_SHIFT_LED0CM_8197F)
+#define BIT_CLEAR_LED0CM_8197F(x) ((x) & (~BITS_LED0CM_8197F))
+#define BIT_GET_LED0CM_8197F(x)                                                \
+	(((x) >> BIT_SHIFT_LED0CM_8197F) & BIT_MASK_LED0CM_8197F)
+#define BIT_SET_LED0CM_8197F(x, v)                                             \
+	(BIT_CLEAR_LED0CM_8197F(x) | BIT_LED0CM_8197F(v))
+
+/* 2 REG_FSIMR_8197F */
+#define BIT_FS_PDNINT_EN_8197F BIT(31)
+#define BIT_FS_SPS_OCP_INT_EN_8197F BIT(29)
+#define BIT_FS_PWMERR_INT_EN_8197F BIT(28)
+#define BIT_FS_GPIOF_INT_EN_8197F BIT(27)
+#define BIT_FS_GPIOE_INT_EN_8197F BIT(26)
+#define BIT_FS_GPIOD_INT_EN_8197F BIT(25)
+#define BIT_FS_GPIOC_INT_EN_8197F BIT(24)
+#define BIT_FS_GPIOB_INT_EN_8197F BIT(23)
+#define BIT_FS_GPIOA_INT_EN_8197F BIT(22)
+#define BIT_FS_GPIO9_INT_EN_8197F BIT(21)
+#define BIT_FS_GPIO8_INT_EN_8197F BIT(20)
+#define BIT_FS_GPIO7_INT_EN_8197F BIT(19)
+#define BIT_FS_GPIO6_INT_EN_8197F BIT(18)
+#define BIT_FS_GPIO5_INT_EN_8197F BIT(17)
+#define BIT_FS_GPIO4_INT_EN_8197F BIT(16)
+#define BIT_FS_GPIO3_INT_EN_8197F BIT(15)
+#define BIT_FS_GPIO2_INT_EN_8197F BIT(14)
+#define BIT_FS_GPIO1_INT_EN_8197F BIT(13)
+#define BIT_FS_GPIO0_INT_EN_8197F BIT(12)
+#define BIT_FS_HCI_SUS_EN_8197F BIT(11)
+#define BIT_FS_HCI_RES_EN_8197F BIT(10)
+#define BIT_FS_HCI_RESET_EN_8197F BIT(9)
+#define BIT_AXI_EXCEPT_FINT_EN_8197F BIT(8)
+#define BIT_FS_BTON_STS_UPDATE_MSK_EN_8197F BIT(7)
+#define BIT_ACT2RECOVERY_INT_EN_V1_8197F BIT(6)
+#define BIT_FS_TRPC_TO_INT_EN_8197F BIT(5)
+#define BIT_FS_RPC_O_T_INT_EN_8197F BIT(4)
+#define BIT_FS_32K_LEAVE_SETTING_MAK_8197F BIT(3)
+#define BIT_FS_32K_ENTER_SETTING_MAK_8197F BIT(2)
+#define BIT_FS_USB_LPMRSM_MSK_8197F BIT(1)
+#define BIT_FS_USB_LPMINT_MSK_8197F BIT(0)
+
+/* 2 REG_FSISR_8197F */
+#define BIT_FS_PDNINT_8197F BIT(31)
+#define BIT_FS_SPS_OCP_INT_8197F BIT(29)
+#define BIT_FS_PWMERR_INT_8197F BIT(28)
+#define BIT_FS_GPIOF_INT_8197F BIT(27)
+#define BIT_FS_GPIOE_INT_8197F BIT(26)
+#define BIT_FS_GPIOD_INT_8197F BIT(25)
+#define BIT_FS_GPIOC_INT_8197F BIT(24)
+#define BIT_FS_GPIOB_INT_8197F BIT(23)
+#define BIT_FS_GPIOA_INT_8197F BIT(22)
+#define BIT_FS_GPIO9_INT_8197F BIT(21)
+#define BIT_FS_GPIO8_INT_8197F BIT(20)
+#define BIT_FS_GPIO7_INT_8197F BIT(19)
+#define BIT_FS_GPIO6_INT_8197F BIT(18)
+#define BIT_FS_GPIO5_INT_8197F BIT(17)
+#define BIT_FS_GPIO4_INT_8197F BIT(16)
+#define BIT_FS_GPIO3_INT_8197F BIT(15)
+#define BIT_FS_GPIO2_INT_8197F BIT(14)
+#define BIT_FS_GPIO1_INT_8197F BIT(13)
+#define BIT_FS_GPIO0_INT_8197F BIT(12)
+#define BIT_FS_HCI_SUS_INT_8197F BIT(11)
+#define BIT_FS_HCI_RES_INT_8197F BIT(10)
+#define BIT_FS_HCI_RESET_INT_8197F BIT(9)
+#define BIT_AXI_EXCEPT_FINT_8197F BIT(8)
+#define BIT_FS_BTON_STS_UPDATE_INT_8197F BIT(7)
+#define BIT_ACT2RECOVERY_INT_V1_8197F BIT(6)
+#define BIT_FS_TRPC_TO_INT_INT_8197F BIT(5)
+#define BIT_FS_RPC_O_T_INT_INT_8197F BIT(4)
+#define BIT_FS_32K_LEAVE_SETTING_INT_8197F BIT(3)
+#define BIT_FS_32K_ENTER_SETTING_INT_8197F BIT(2)
+#define BIT_FS_USB_LPMRSM_INT_8197F BIT(1)
+#define BIT_FS_USB_LPMINT_INT_8197F BIT(0)
+
+/* 2 REG_HSIMR_8197F */
+#define BIT_GPIOF_INT_EN_8197F BIT(31)
+#define BIT_GPIOE_INT_EN_8197F BIT(30)
+#define BIT_GPIOD_INT_EN_8197F BIT(29)
+#define BIT_GPIOC_INT_EN_8197F BIT(28)
+#define BIT_GPIOB_INT_EN_8197F BIT(27)
+#define BIT_GPIOA_INT_EN_8197F BIT(26)
+#define BIT_GPIO9_INT_EN_8197F BIT(25)
+#define BIT_GPIO8_INT_EN_8197F BIT(24)
+#define BIT_GPIO7_INT_EN_8197F BIT(23)
+#define BIT_GPIO6_INT_EN_8197F BIT(22)
+#define BIT_GPIO5_INT_EN_8197F BIT(21)
+#define BIT_GPIO4_INT_EN_8197F BIT(20)
+#define BIT_GPIO3_INT_EN_8197F BIT(19)
+#define BIT_GPIO2_INT_EN_8197F BIT(18)
+#define BIT_GPIO1_INT_EN_8197F BIT(17)
+#define BIT_GPIO0_INT_EN_8197F BIT(16)
+#define BIT_AXI_EXCEPT_HINT_EN_8197F BIT(9)
+#define BIT_PDNINT_EN_V2_8197F BIT(8)
+#define BIT_PDNINT_EN_V1_8197F BIT(7)
+#define BIT_RON_INT_EN_V1_8197F BIT(6)
+#define BIT_SPS_OCP_INT_EN_V1_8197F BIT(5)
+#define BIT_GPIO15_0_INT_EN_V1_8197F BIT(0)
+
+/* 2 REG_HSISR_8197F */
+#define BIT_GPIOF_INT_8197F BIT(31)
+#define BIT_GPIOE_INT_8197F BIT(30)
+#define BIT_GPIOD_INT_8197F BIT(29)
+#define BIT_GPIOC_INT_8197F BIT(28)
+#define BIT_GPIOB_INT_8197F BIT(27)
+#define BIT_GPIOA_INT_8197F BIT(26)
+#define BIT_GPIO9_INT_8197F BIT(25)
+#define BIT_GPIO8_INT_8197F BIT(24)
+#define BIT_GPIO7_INT_8197F BIT(23)
+#define BIT_GPIO6_INT_8197F BIT(22)
+#define BIT_GPIO5_INT_8197F BIT(21)
+#define BIT_GPIO4_INT_8197F BIT(20)
+#define BIT_GPIO3_INT_8197F BIT(19)
+#define BIT_GPIO2_INT_8197F BIT(18)
+#define BIT_GPIO1_INT_8197F BIT(17)
+#define BIT_GPIO0_INT_8197F BIT(16)
+#define BIT_AXI_EXCEPT_HINT_8197F BIT(8)
+#define BIT_PDNINT_V1_8197F BIT(7)
+#define BIT_RON_INT_V1_8197F BIT(6)
+#define BIT_SPS_OCP_INT_V1_8197F BIT(5)
+#define BIT_GPIO15_0_INT_V1_8197F BIT(0)
+
+/* 2 REG_GPIO_EXT_CTRL_8197F */
+
+#define BIT_SHIFT_GPIO_MOD_15_TO_8_8197F 24
+#define BIT_MASK_GPIO_MOD_15_TO_8_8197F 0xff
+#define BIT_GPIO_MOD_15_TO_8_8197F(x)                                          \
+	(((x) & BIT_MASK_GPIO_MOD_15_TO_8_8197F)                               \
+	 << BIT_SHIFT_GPIO_MOD_15_TO_8_8197F)
+#define BITS_GPIO_MOD_15_TO_8_8197F                                            \
+	(BIT_MASK_GPIO_MOD_15_TO_8_8197F << BIT_SHIFT_GPIO_MOD_15_TO_8_8197F)
+#define BIT_CLEAR_GPIO_MOD_15_TO_8_8197F(x)                                    \
+	((x) & (~BITS_GPIO_MOD_15_TO_8_8197F))
+#define BIT_GET_GPIO_MOD_15_TO_8_8197F(x)                                      \
+	(((x) >> BIT_SHIFT_GPIO_MOD_15_TO_8_8197F) &                           \
+	 BIT_MASK_GPIO_MOD_15_TO_8_8197F)
+#define BIT_SET_GPIO_MOD_15_TO_8_8197F(x, v)                                   \
+	(BIT_CLEAR_GPIO_MOD_15_TO_8_8197F(x) | BIT_GPIO_MOD_15_TO_8_8197F(v))
+
+#define BIT_SHIFT_GPIO_IO_SEL_15_TO_8_8197F 16
+#define BIT_MASK_GPIO_IO_SEL_15_TO_8_8197F 0xff
+#define BIT_GPIO_IO_SEL_15_TO_8_8197F(x)                                       \
+	(((x) & BIT_MASK_GPIO_IO_SEL_15_TO_8_8197F)                            \
+	 << BIT_SHIFT_GPIO_IO_SEL_15_TO_8_8197F)
+#define BITS_GPIO_IO_SEL_15_TO_8_8197F                                         \
+	(BIT_MASK_GPIO_IO_SEL_15_TO_8_8197F                                    \
+	 << BIT_SHIFT_GPIO_IO_SEL_15_TO_8_8197F)
+#define BIT_CLEAR_GPIO_IO_SEL_15_TO_8_8197F(x)                                 \
+	((x) & (~BITS_GPIO_IO_SEL_15_TO_8_8197F))
+#define BIT_GET_GPIO_IO_SEL_15_TO_8_8197F(x)                                   \
+	(((x) >> BIT_SHIFT_GPIO_IO_SEL_15_TO_8_8197F) &                        \
+	 BIT_MASK_GPIO_IO_SEL_15_TO_8_8197F)
+#define BIT_SET_GPIO_IO_SEL_15_TO_8_8197F(x, v)                                \
+	(BIT_CLEAR_GPIO_IO_SEL_15_TO_8_8197F(x) |                              \
+	 BIT_GPIO_IO_SEL_15_TO_8_8197F(v))
+
+#define BIT_SHIFT_GPIO_OUT_15_TO_8_8197F 8
+#define BIT_MASK_GPIO_OUT_15_TO_8_8197F 0xff
+#define BIT_GPIO_OUT_15_TO_8_8197F(x)                                          \
+	(((x) & BIT_MASK_GPIO_OUT_15_TO_8_8197F)                               \
+	 << BIT_SHIFT_GPIO_OUT_15_TO_8_8197F)
+#define BITS_GPIO_OUT_15_TO_8_8197F                                            \
+	(BIT_MASK_GPIO_OUT_15_TO_8_8197F << BIT_SHIFT_GPIO_OUT_15_TO_8_8197F)
+#define BIT_CLEAR_GPIO_OUT_15_TO_8_8197F(x)                                    \
+	((x) & (~BITS_GPIO_OUT_15_TO_8_8197F))
+#define BIT_GET_GPIO_OUT_15_TO_8_8197F(x)                                      \
+	(((x) >> BIT_SHIFT_GPIO_OUT_15_TO_8_8197F) &                           \
+	 BIT_MASK_GPIO_OUT_15_TO_8_8197F)
+#define BIT_SET_GPIO_OUT_15_TO_8_8197F(x, v)                                   \
+	(BIT_CLEAR_GPIO_OUT_15_TO_8_8197F(x) | BIT_GPIO_OUT_15_TO_8_8197F(v))
+
+#define BIT_SHIFT_GPIO_IN_15_TO_8_8197F 0
+#define BIT_MASK_GPIO_IN_15_TO_8_8197F 0xff
+#define BIT_GPIO_IN_15_TO_8_8197F(x)                                           \
+	(((x) & BIT_MASK_GPIO_IN_15_TO_8_8197F)                                \
+	 << BIT_SHIFT_GPIO_IN_15_TO_8_8197F)
+#define BITS_GPIO_IN_15_TO_8_8197F                                             \
+	(BIT_MASK_GPIO_IN_15_TO_8_8197F << BIT_SHIFT_GPIO_IN_15_TO_8_8197F)
+#define BIT_CLEAR_GPIO_IN_15_TO_8_8197F(x) ((x) & (~BITS_GPIO_IN_15_TO_8_8197F))
+#define BIT_GET_GPIO_IN_15_TO_8_8197F(x)                                       \
+	(((x) >> BIT_SHIFT_GPIO_IN_15_TO_8_8197F) &                            \
+	 BIT_MASK_GPIO_IN_15_TO_8_8197F)
+#define BIT_SET_GPIO_IN_15_TO_8_8197F(x, v)                                    \
+	(BIT_CLEAR_GPIO_IN_15_TO_8_8197F(x) | BIT_GPIO_IN_15_TO_8_8197F(v))
+
+/* 2 REG_PAD_CTRL1_8197F */
+#define BIT_PAPE_WLBT_SEL_8197F BIT(29)
+#define BIT_LNAON_WLBT_SEL_8197F BIT(28)
+#define BIT_BTGP_GPG3_FEN_8197F BIT(26)
+#define BIT_BTGP_GPG2_FEN_8197F BIT(25)
+#define BIT_BTGP_JTAG_EN_8197F BIT(24)
+#define BIT_XTAL_CLK_EXTARNAL_EN_8197F BIT(23)
+#define BIT_BTGP_UART0_EN_8197F BIT(22)
+#define BIT_BTGP_UART1_EN_8197F BIT(21)
+#define BIT_BTGP_SPI_EN_8197F BIT(20)
+#define BIT_BTGP_GPIO_E2_8197F BIT(19)
+#define BIT_BTGP_GPIO_EN_8197F BIT(18)
+
+#define BIT_SHIFT_BTGP_GPIO_SL_8197F 16
+#define BIT_MASK_BTGP_GPIO_SL_8197F 0x3
+#define BIT_BTGP_GPIO_SL_8197F(x)                                              \
+	(((x) & BIT_MASK_BTGP_GPIO_SL_8197F) << BIT_SHIFT_BTGP_GPIO_SL_8197F)
+#define BITS_BTGP_GPIO_SL_8197F                                                \
+	(BIT_MASK_BTGP_GPIO_SL_8197F << BIT_SHIFT_BTGP_GPIO_SL_8197F)
+#define BIT_CLEAR_BTGP_GPIO_SL_8197F(x) ((x) & (~BITS_BTGP_GPIO_SL_8197F))
+#define BIT_GET_BTGP_GPIO_SL_8197F(x)                                          \
+	(((x) >> BIT_SHIFT_BTGP_GPIO_SL_8197F) & BIT_MASK_BTGP_GPIO_SL_8197F)
+#define BIT_SET_BTGP_GPIO_SL_8197F(x, v)                                       \
+	(BIT_CLEAR_BTGP_GPIO_SL_8197F(x) | BIT_BTGP_GPIO_SL_8197F(v))
+
+#define BIT_PAD_SDIO_SR_8197F BIT(14)
+#define BIT_GPIO14_OUTPUT_PL_8197F BIT(13)
+#define BIT_HOST_WAKE_PAD_PULL_EN_8197F BIT(12)
+#define BIT_HOST_WAKE_PAD_SL_8197F BIT(11)
+#define BIT_PAD_LNAON_SR_8197F BIT(10)
+#define BIT_PAD_LNAON_E2_8197F BIT(9)
+#define BIT_SW_LNAON_G_SEL_DATA_8197F BIT(8)
+#define BIT_SW_LNAON_A_SEL_DATA_8197F BIT(7)
+#define BIT_PAD_PAPE_SR_8197F BIT(6)
+#define BIT_PAD_PAPE_E2_8197F BIT(5)
+#define BIT_SW_PAPE_G_SEL_DATA_8197F BIT(4)
+#define BIT_SW_PAPE_A_SEL_DATA_8197F BIT(3)
+#define BIT_PAD_DPDT_SR_8197F BIT(2)
+#define BIT_PAD_DPDT_PAD_E2_8197F BIT(1)
+#define BIT_SW_DPDT_SEL_DATA_8197F BIT(0)
+
+/* 2 REG_WL_BT_PWR_CTRL_8197F */
+#define BIT_ISO_BD2PP_8197F BIT(31)
+#define BIT_LDOV12B_EN_8197F BIT(30)
+#define BIT_CKEN_BTGPS_8197F BIT(29)
+#define BIT_FEN_BTGPS_8197F BIT(28)
+#define BIT_BTCPU_BOOTSEL_8197F BIT(27)
+#define BIT_SPI_SPEEDUP_8197F BIT(26)
+#define BIT_DEVWAKE_PAD_TYPE_SEL_8197F BIT(24)
+#define BIT_CLKREQ_PAD_TYPE_SEL_8197F BIT(23)
+#define BIT_ISO_BTPON2PP_8197F BIT(22)
+#define BIT_BT_HWROF_EN_8197F BIT(19)
+#define BIT_BT_FUNC_EN_8197F BIT(18)
+#define BIT_BT_HWPDN_SL_8197F BIT(17)
+#define BIT_BT_DISN_EN_8197F BIT(16)
+#define BIT_BT_PDN_PULL_EN_8197F BIT(15)
+#define BIT_WL_PDN_PULL_EN_8197F BIT(14)
+#define BIT_EXTERNAL_REQUEST_PL_8197F BIT(13)
+#define BIT_GPIO0_2_3_PULL_LOW_EN_8197F BIT(12)
+#define BIT_ISO_BA2PP_8197F BIT(11)
+#define BIT_BT_AFE_LDO_EN_8197F BIT(10)
+#define BIT_BT_AFE_PLL_EN_8197F BIT(9)
+#define BIT_BT_DIG_CLK_EN_8197F BIT(8)
+#define BIT_WL_DRV_EXIST_IDX_8197F BIT(5)
+#define BIT_DOP_EHPAD_8197F BIT(4)
+#define BIT_WL_HWROF_EN_8197F BIT(3)
+#define BIT_WL_FUNC_EN_8197F BIT(2)
+#define BIT_WL_HWPDN_SL_8197F BIT(1)
+#define BIT_WL_HWPDN_EN_8197F BIT(0)
+
+/* 2 REG_SDM_DEBUG_8197F */
+
+#define BIT_SHIFT_WLCLK_PHASE_8197F 0
+#define BIT_MASK_WLCLK_PHASE_8197F 0x1f
+#define BIT_WLCLK_PHASE_8197F(x)                                               \
+	(((x) & BIT_MASK_WLCLK_PHASE_8197F) << BIT_SHIFT_WLCLK_PHASE_8197F)
+#define BITS_WLCLK_PHASE_8197F                                                 \
+	(BIT_MASK_WLCLK_PHASE_8197F << BIT_SHIFT_WLCLK_PHASE_8197F)
+#define BIT_CLEAR_WLCLK_PHASE_8197F(x) ((x) & (~BITS_WLCLK_PHASE_8197F))
+#define BIT_GET_WLCLK_PHASE_8197F(x)                                           \
+	(((x) >> BIT_SHIFT_WLCLK_PHASE_8197F) & BIT_MASK_WLCLK_PHASE_8197F)
+#define BIT_SET_WLCLK_PHASE_8197F(x, v)                                        \
+	(BIT_CLEAR_WLCLK_PHASE_8197F(x) | BIT_WLCLK_PHASE_8197F(v))
+
+/* 2 REG_SYS_SDIO_CTRL_8197F */
+#define BIT_DBG_GNT_WL_BT_8197F BIT(27)
+#define BIT_LTE_MUX_CTRL_PATH_8197F BIT(26)
+#define BIT_SDIO_INT_POLARITY_8197F BIT(19)
+#define BIT_SDIO_INT_8197F BIT(18)
+#define BIT_SDIO_OFF_EN_8197F BIT(17)
+#define BIT_SDIO_ON_EN_8197F BIT(16)
+
+/* 2 REG_HCI_OPT_CTRL_8197F */
+#define BIT_USB_HOST_PWR_OFF_EN_8197F BIT(12)
+#define BIT_SYM_LPS_BLOCK_EN_8197F BIT(11)
+#define BIT_USB_LPM_ACT_EN_8197F BIT(10)
+#define BIT_USB_LPM_NY_8197F BIT(9)
+#define BIT_USB_SUS_DIS_8197F BIT(8)
+
+#define BIT_SHIFT_SDIO_PAD_E_8197F 5
+#define BIT_MASK_SDIO_PAD_E_8197F 0x7
+#define BIT_SDIO_PAD_E_8197F(x)                                                \
+	(((x) & BIT_MASK_SDIO_PAD_E_8197F) << BIT_SHIFT_SDIO_PAD_E_8197F)
+#define BITS_SDIO_PAD_E_8197F                                                  \
+	(BIT_MASK_SDIO_PAD_E_8197F << BIT_SHIFT_SDIO_PAD_E_8197F)
+#define BIT_CLEAR_SDIO_PAD_E_8197F(x) ((x) & (~BITS_SDIO_PAD_E_8197F))
+#define BIT_GET_SDIO_PAD_E_8197F(x)                                            \
+	(((x) >> BIT_SHIFT_SDIO_PAD_E_8197F) & BIT_MASK_SDIO_PAD_E_8197F)
+#define BIT_SET_SDIO_PAD_E_8197F(x, v)                                         \
+	(BIT_CLEAR_SDIO_PAD_E_8197F(x) | BIT_SDIO_PAD_E_8197F(v))
+
+#define BIT_USB_LPPLL_EN_8197F BIT(4)
+#define BIT_ROP_SW15_8197F BIT(2)
+#define BIT_PCI_CKRDY_OPT_8197F BIT(1)
+#define BIT_PCI_VAUX_EN_8197F BIT(0)
+
+/* 2 REG_AFE_CTRL4_8197F */
+#define BIT_RF1_SDMRSTB_8197F BIT(26)
+#define BIT_RF1_RSTB_8197F BIT(25)
+#define BIT_RF1_EN_8197F BIT(24)
+
+#define BIT_SHIFT_XTAL_LDO_8197F 20
+#define BIT_MASK_XTAL_LDO_8197F 0x7
+#define BIT_XTAL_LDO_8197F(x)                                                  \
+	(((x) & BIT_MASK_XTAL_LDO_8197F) << BIT_SHIFT_XTAL_LDO_8197F)
+#define BITS_XTAL_LDO_8197F                                                    \
+	(BIT_MASK_XTAL_LDO_8197F << BIT_SHIFT_XTAL_LDO_8197F)
+#define BIT_CLEAR_XTAL_LDO_8197F(x) ((x) & (~BITS_XTAL_LDO_8197F))
+#define BIT_GET_XTAL_LDO_8197F(x)                                              \
+	(((x) >> BIT_SHIFT_XTAL_LDO_8197F) & BIT_MASK_XTAL_LDO_8197F)
+#define BIT_SET_XTAL_LDO_8197F(x, v)                                           \
+	(BIT_CLEAR_XTAL_LDO_8197F(x) | BIT_XTAL_LDO_8197F(v))
+
+#define BIT_ADC_CK_SYNC_EN_8197F BIT(16)
+
+/* 2 REG_LDO_SWR_CTRL_8197F */
+
+/* 2 REG_NOT_VALID_8197F */
+
+/* 2 REG_NOT_VALID_8197F */
+
+/* 2 REG_NOT_VALID_8197F */
+
+/* 2 REG_NOT_VALID_8197F */
+
+/* 2 REG_NOT_VALID_8197F */
+
+/* 2 REG_NOT_VALID_8197F */
+
+/* 2 REG_NOT_VALID_8197F */
+
+/* 2 REG_NOT_VALID_8197F */
+
+/* 2 REG_NOT_VALID_8197F */
+
+/* 2 REG_NOT_VALID_8197F */
+
+/* 2 REG_NOT_VALID_8197F */
+
+/* 2 REG_NOT_VALID_8197F */
+
+/* 2 REG_NOT_VALID_8197F */
+
+/* 2 REG_NOT_VALID_8197F */
+
+/* 2 REG_NOT_VALID_8197F */
+
+/* 2 REG_NOT_VALID_8197F */
+
+/* 2 REG_NOT_VALID_8197F */
+
+/* 2 REG_NOT_VALID_8197F */
+
+/* 2 REG_MCUFW_CTRL_8197F */
+
+#define BIT_SHIFT_RPWM_8197F 24
+#define BIT_MASK_RPWM_8197F 0xff
+#define BIT_RPWM_8197F(x) (((x) & BIT_MASK_RPWM_8197F) << BIT_SHIFT_RPWM_8197F)
+#define BITS_RPWM_8197F (BIT_MASK_RPWM_8197F << BIT_SHIFT_RPWM_8197F)
+#define BIT_CLEAR_RPWM_8197F(x) ((x) & (~BITS_RPWM_8197F))
+#define BIT_GET_RPWM_8197F(x)                                                  \
+	(((x) >> BIT_SHIFT_RPWM_8197F) & BIT_MASK_RPWM_8197F)
+#define BIT_SET_RPWM_8197F(x, v) (BIT_CLEAR_RPWM_8197F(x) | BIT_RPWM_8197F(v))
+
+#define BIT_CPRST_8197F BIT(23)
+#define BIT_ANA_PORT_EN_8197F BIT(22)
+#define BIT_MAC_PORT_EN_8197F BIT(21)
+#define BIT_BOOT_FSPI_EN_8197F BIT(20)
+#define BIT_ROM_DLEN_8197F BIT(19)
+
+#define BIT_SHIFT_ROM_PGE_8197F 16
+#define BIT_MASK_ROM_PGE_8197F 0x7
+#define BIT_ROM_PGE_8197F(x)                                                   \
+	(((x) & BIT_MASK_ROM_PGE_8197F) << BIT_SHIFT_ROM_PGE_8197F)
+#define BITS_ROM_PGE_8197F (BIT_MASK_ROM_PGE_8197F << BIT_SHIFT_ROM_PGE_8197F)
+#define BIT_CLEAR_ROM_PGE_8197F(x) ((x) & (~BITS_ROM_PGE_8197F))
+#define BIT_GET_ROM_PGE_8197F(x)                                               \
+	(((x) >> BIT_SHIFT_ROM_PGE_8197F) & BIT_MASK_ROM_PGE_8197F)
+#define BIT_SET_ROM_PGE_8197F(x, v)                                            \
+	(BIT_CLEAR_ROM_PGE_8197F(x) | BIT_ROM_PGE_8197F(v))
+
+#define BIT_FW_INIT_RDY_8197F BIT(15)
+#define BIT_FW_DW_RDY_8197F BIT(14)
+
+#define BIT_SHIFT_CPU_CLK_SEL_8197F 12
+#define BIT_MASK_CPU_CLK_SEL_8197F 0x3
+#define BIT_CPU_CLK_SEL_8197F(x)                                               \
+	(((x) & BIT_MASK_CPU_CLK_SEL_8197F) << BIT_SHIFT_CPU_CLK_SEL_8197F)
+#define BITS_CPU_CLK_SEL_8197F                                                 \
+	(BIT_MASK_CPU_CLK_SEL_8197F << BIT_SHIFT_CPU_CLK_SEL_8197F)
+#define BIT_CLEAR_CPU_CLK_SEL_8197F(x) ((x) & (~BITS_CPU_CLK_SEL_8197F))
+#define BIT_GET_CPU_CLK_SEL_8197F(x)                                           \
+	(((x) >> BIT_SHIFT_CPU_CLK_SEL_8197F) & BIT_MASK_CPU_CLK_SEL_8197F)
+#define BIT_SET_CPU_CLK_SEL_8197F(x, v)                                        \
+	(BIT_CLEAR_CPU_CLK_SEL_8197F(x) | BIT_CPU_CLK_SEL_8197F(v))
+
+#define BIT_CCLK_CHG_MASK_8197F BIT(11)
+#define BIT_FW_INIT_RDY_V1_8197F BIT(10)
+#define BIT_R_8051_SPD_8197F BIT(9)
+#define BIT_MCU_CLK_EN_8197F BIT(8)
+#define BIT_RAM_DL_SEL_8197F BIT(7)
+#define BIT_WINTINI_RDY_8197F BIT(6)
+#define BIT_RF_INIT_RDY_8197F BIT(5)
+#define BIT_BB_INIT_RDY_8197F BIT(4)
+#define BIT_MAC_INIT_RDY_8197F BIT(3)
+#define BIT_MCU_FWDL_RDY_8197F BIT(1)
+#define BIT_MCU_FWDL_EN_8197F BIT(0)
+
+/* 2 REG_MCU_TST_CFG_8197F */
+
+#define BIT_SHIFT_LBKTST_8197F 0
+#define BIT_MASK_LBKTST_8197F 0xffff
+#define BIT_LBKTST_8197F(x)                                                    \
+	(((x) & BIT_MASK_LBKTST_8197F) << BIT_SHIFT_LBKTST_8197F)
+#define BITS_LBKTST_8197F (BIT_MASK_LBKTST_8197F << BIT_SHIFT_LBKTST_8197F)
+#define BIT_CLEAR_LBKTST_8197F(x) ((x) & (~BITS_LBKTST_8197F))
+#define BIT_GET_LBKTST_8197F(x)                                                \
+	(((x) >> BIT_SHIFT_LBKTST_8197F) & BIT_MASK_LBKTST_8197F)
+#define BIT_SET_LBKTST_8197F(x, v)                                             \
+	(BIT_CLEAR_LBKTST_8197F(x) | BIT_LBKTST_8197F(v))
+
+/* 2 REG_HMEBOX_E0_E1_8197F */
+
+#define BIT_SHIFT_HOST_MSG_E1_8197F 16
+#define BIT_MASK_HOST_MSG_E1_8197F 0xffff
+#define BIT_HOST_MSG_E1_8197F(x)                                               \
+	(((x) & BIT_MASK_HOST_MSG_E1_8197F) << BIT_SHIFT_HOST_MSG_E1_8197F)
+#define BITS_HOST_MSG_E1_8197F                                                 \
+	(BIT_MASK_HOST_MSG_E1_8197F << BIT_SHIFT_HOST_MSG_E1_8197F)
+#define BIT_CLEAR_HOST_MSG_E1_8197F(x) ((x) & (~BITS_HOST_MSG_E1_8197F))
+#define BIT_GET_HOST_MSG_E1_8197F(x)                                           \
+	(((x) >> BIT_SHIFT_HOST_MSG_E1_8197F) & BIT_MASK_HOST_MSG_E1_8197F)
+#define BIT_SET_HOST_MSG_E1_8197F(x, v)                                        \
+	(BIT_CLEAR_HOST_MSG_E1_8197F(x) | BIT_HOST_MSG_E1_8197F(v))
+
+#define BIT_SHIFT_HOST_MSG_E0_8197F 0
+#define BIT_MASK_HOST_MSG_E0_8197F 0xffff
+#define BIT_HOST_MSG_E0_8197F(x)                                               \
+	(((x) & BIT_MASK_HOST_MSG_E0_8197F) << BIT_SHIFT_HOST_MSG_E0_8197F)
+#define BITS_HOST_MSG_E0_8197F                                                 \
+	(BIT_MASK_HOST_MSG_E0_8197F << BIT_SHIFT_HOST_MSG_E0_8197F)
+#define BIT_CLEAR_HOST_MSG_E0_8197F(x) ((x) & (~BITS_HOST_MSG_E0_8197F))
+#define BIT_GET_HOST_MSG_E0_8197F(x)                                           \
+	(((x) >> BIT_SHIFT_HOST_MSG_E0_8197F) & BIT_MASK_HOST_MSG_E0_8197F)
+#define BIT_SET_HOST_MSG_E0_8197F(x, v)                                        \
+	(BIT_CLEAR_HOST_MSG_E0_8197F(x) | BIT_HOST_MSG_E0_8197F(v))
+
+/* 2 REG_HMEBOX_E2_E3_8197F */
+
+#define BIT_SHIFT_HOST_MSG_E3_8197F 16
+#define BIT_MASK_HOST_MSG_E3_8197F 0xffff
+#define BIT_HOST_MSG_E3_8197F(x)                                               \
+	(((x) & BIT_MASK_HOST_MSG_E3_8197F) << BIT_SHIFT_HOST_MSG_E3_8197F)
+#define BITS_HOST_MSG_E3_8197F                                                 \
+	(BIT_MASK_HOST_MSG_E3_8197F << BIT_SHIFT_HOST_MSG_E3_8197F)
+#define BIT_CLEAR_HOST_MSG_E3_8197F(x) ((x) & (~BITS_HOST_MSG_E3_8197F))
+#define BIT_GET_HOST_MSG_E3_8197F(x)                                           \
+	(((x) >> BIT_SHIFT_HOST_MSG_E3_8197F) & BIT_MASK_HOST_MSG_E3_8197F)
+#define BIT_SET_HOST_MSG_E3_8197F(x, v)                                        \
+	(BIT_CLEAR_HOST_MSG_E3_8197F(x) | BIT_HOST_MSG_E3_8197F(v))
+
+#define BIT_SHIFT_HOST_MSG_E2_8197F 0
+#define BIT_MASK_HOST_MSG_E2_8197F 0xffff
+#define BIT_HOST_MSG_E2_8197F(x)                                               \
+	(((x) & BIT_MASK_HOST_MSG_E2_8197F) << BIT_SHIFT_HOST_MSG_E2_8197F)
+#define BITS_HOST_MSG_E2_8197F                                                 \
+	(BIT_MASK_HOST_MSG_E2_8197F << BIT_SHIFT_HOST_MSG_E2_8197F)
+#define BIT_CLEAR_HOST_MSG_E2_8197F(x) ((x) & (~BITS_HOST_MSG_E2_8197F))
+#define BIT_GET_HOST_MSG_E2_8197F(x)                                           \
+	(((x) >> BIT_SHIFT_HOST_MSG_E2_8197F) & BIT_MASK_HOST_MSG_E2_8197F)
+#define BIT_SET_HOST_MSG_E2_8197F(x, v)                                        \
+	(BIT_CLEAR_HOST_MSG_E2_8197F(x) | BIT_HOST_MSG_E2_8197F(v))
+
+/* 2 REG_WLLPS_CTRL_8197F */
+
+/* 2 REG_NOT_VALID_8197F */
+
+/* 2 REG_NOT_VALID_8197F */
+
+/* 2 REG_NOT_VALID_8197F */
+
+/* 2 REG_NOT_VALID_8197F */
+
+/* 2 REG_NOT_VALID_8197F */
+
+/* 2 REG_NOT_VALID_8197F */
+
+/* 2 REG_NOT_VALID_8197F */
+
+/* 2 REG_NOT_VALID_8197F */
+
+/* 2 REG_NOT_VALID_8197F */
+
+/* 2 REG_NOT_VALID_8197F */
+
+/* 2 REG_NOT_VALID_8197F */
+
+/* 2 REG_NOT_VALID_8197F */
+
+/* 2 REG_NOT_VALID_8197F */
+
+/* 2 REG_NOT_VALID_8197F */
+
+/* 2 REG_NOT_VALID_8197F */
+
+/* 2 REG_AFE_CTRL5_8197F */
+#define BIT_BB_DBG_SEL_AFE_SDM_V3_8197F BIT(31)
+#define BIT_ORDER_SDM_8197F BIT(30)
+#define BIT_RFE_SEL_SDM_8197F BIT(29)
+
+#define BIT_SHIFT_REF_SEL_8197F 25
+#define BIT_MASK_REF_SEL_8197F 0xf
+#define BIT_REF_SEL_8197F(x)                                                   \
+	(((x) & BIT_MASK_REF_SEL_8197F) << BIT_SHIFT_REF_SEL_8197F)
+#define BITS_REF_SEL_8197F (BIT_MASK_REF_SEL_8197F << BIT_SHIFT_REF_SEL_8197F)
+#define BIT_CLEAR_REF_SEL_8197F(x) ((x) & (~BITS_REF_SEL_8197F))
+#define BIT_GET_REF_SEL_8197F(x)                                               \
+	(((x) >> BIT_SHIFT_REF_SEL_8197F) & BIT_MASK_REF_SEL_8197F)
+#define BIT_SET_REF_SEL_8197F(x, v)                                            \
+	(BIT_CLEAR_REF_SEL_8197F(x) | BIT_REF_SEL_8197F(v))
+
+#define BIT_SHIFT_F0F_SDM_V2_8197F 12
+#define BIT_MASK_F0F_SDM_V2_8197F 0x1fff
+#define BIT_F0F_SDM_V2_8197F(x)                                                \
+	(((x) & BIT_MASK_F0F_SDM_V2_8197F) << BIT_SHIFT_F0F_SDM_V2_8197F)
+#define BITS_F0F_SDM_V2_8197F                                                  \
+	(BIT_MASK_F0F_SDM_V2_8197F << BIT_SHIFT_F0F_SDM_V2_8197F)
+#define BIT_CLEAR_F0F_SDM_V2_8197F(x) ((x) & (~BITS_F0F_SDM_V2_8197F))
+#define BIT_GET_F0F_SDM_V2_8197F(x)                                            \
+	(((x) >> BIT_SHIFT_F0F_SDM_V2_8197F) & BIT_MASK_F0F_SDM_V2_8197F)
+#define BIT_SET_F0F_SDM_V2_8197F(x, v)                                         \
+	(BIT_CLEAR_F0F_SDM_V2_8197F(x) | BIT_F0F_SDM_V2_8197F(v))
+
+#define BIT_SHIFT_F0N_SDM_V2_8197F 9
+#define BIT_MASK_F0N_SDM_V2_8197F 0x7
+#define BIT_F0N_SDM_V2_8197F(x)                                                \
+	(((x) & BIT_MASK_F0N_SDM_V2_8197F) << BIT_SHIFT_F0N_SDM_V2_8197F)
+#define BITS_F0N_SDM_V2_8197F                                                  \
+	(BIT_MASK_F0N_SDM_V2_8197F << BIT_SHIFT_F0N_SDM_V2_8197F)
+#define BIT_CLEAR_F0N_SDM_V2_8197F(x) ((x) & (~BITS_F0N_SDM_V2_8197F))
+#define BIT_GET_F0N_SDM_V2_8197F(x)                                            \
+	(((x) >> BIT_SHIFT_F0N_SDM_V2_8197F) & BIT_MASK_F0N_SDM_V2_8197F)
+#define BIT_SET_F0N_SDM_V2_8197F(x, v)                                         \
+	(BIT_CLEAR_F0N_SDM_V2_8197F(x) | BIT_F0N_SDM_V2_8197F(v))
+
+#define BIT_SHIFT_DIVN_SDM_V2_8197F 3
+#define BIT_MASK_DIVN_SDM_V2_8197F 0x3f
+#define BIT_DIVN_SDM_V2_8197F(x)                                               \
+	(((x) & BIT_MASK_DIVN_SDM_V2_8197F) << BIT_SHIFT_DIVN_SDM_V2_8197F)
+#define BITS_DIVN_SDM_V2_8197F                                                 \
+	(BIT_MASK_DIVN_SDM_V2_8197F << BIT_SHIFT_DIVN_SDM_V2_8197F)
+#define BIT_CLEAR_DIVN_SDM_V2_8197F(x) ((x) & (~BITS_DIVN_SDM_V2_8197F))
+#define BIT_GET_DIVN_SDM_V2_8197F(x)                                           \
+	(((x) >> BIT_SHIFT_DIVN_SDM_V2_8197F) & BIT_MASK_DIVN_SDM_V2_8197F)
+#define BIT_SET_DIVN_SDM_V2_8197F(x, v)                                        \
+	(BIT_CLEAR_DIVN_SDM_V2_8197F(x) | BIT_DIVN_SDM_V2_8197F(v))
+
+#define BIT_SHIFT_DITHER_SDM_V2_8197F 0
+#define BIT_MASK_DITHER_SDM_V2_8197F 0x7
+#define BIT_DITHER_SDM_V2_8197F(x)                                             \
+	(((x) & BIT_MASK_DITHER_SDM_V2_8197F) << BIT_SHIFT_DITHER_SDM_V2_8197F)
+#define BITS_DITHER_SDM_V2_8197F                                               \
+	(BIT_MASK_DITHER_SDM_V2_8197F << BIT_SHIFT_DITHER_SDM_V2_8197F)
+#define BIT_CLEAR_DITHER_SDM_V2_8197F(x) ((x) & (~BITS_DITHER_SDM_V2_8197F))
+#define BIT_GET_DITHER_SDM_V2_8197F(x)                                         \
+	(((x) >> BIT_SHIFT_DITHER_SDM_V2_8197F) & BIT_MASK_DITHER_SDM_V2_8197F)
+#define BIT_SET_DITHER_SDM_V2_8197F(x, v)                                      \
+	(BIT_CLEAR_DITHER_SDM_V2_8197F(x) | BIT_DITHER_SDM_V2_8197F(v))
+
+/* 2 REG_GPIO_DEBOUNCE_CTRL_8197F */
+#define BIT_WLGP_DBC1EN_8197F BIT(15)
+
+#define BIT_SHIFT_WLGP_DBC1_8197F 8
+#define BIT_MASK_WLGP_DBC1_8197F 0xf
+#define BIT_WLGP_DBC1_8197F(x)                                                 \
+	(((x) & BIT_MASK_WLGP_DBC1_8197F) << BIT_SHIFT_WLGP_DBC1_8197F)
+#define BITS_WLGP_DBC1_8197F                                                   \
+	(BIT_MASK_WLGP_DBC1_8197F << BIT_SHIFT_WLGP_DBC1_8197F)
+#define BIT_CLEAR_WLGP_DBC1_8197F(x) ((x) & (~BITS_WLGP_DBC1_8197F))
+#define BIT_GET_WLGP_DBC1_8197F(x)                                             \
+	(((x) >> BIT_SHIFT_WLGP_DBC1_8197F) & BIT_MASK_WLGP_DBC1_8197F)
+#define BIT_SET_WLGP_DBC1_8197F(x, v)                                          \
+	(BIT_CLEAR_WLGP_DBC1_8197F(x) | BIT_WLGP_DBC1_8197F(v))
+
+#define BIT_WLGP_DBC0EN_8197F BIT(7)
+
+#define BIT_SHIFT_WLGP_DBC0_8197F 0
+#define BIT_MASK_WLGP_DBC0_8197F 0xf
+#define BIT_WLGP_DBC0_8197F(x)                                                 \
+	(((x) & BIT_MASK_WLGP_DBC0_8197F) << BIT_SHIFT_WLGP_DBC0_8197F)
+#define BITS_WLGP_DBC0_8197F                                                   \
+	(BIT_MASK_WLGP_DBC0_8197F << BIT_SHIFT_WLGP_DBC0_8197F)
+#define BIT_CLEAR_WLGP_DBC0_8197F(x) ((x) & (~BITS_WLGP_DBC0_8197F))
+#define BIT_GET_WLGP_DBC0_8197F(x)                                             \
+	(((x) >> BIT_SHIFT_WLGP_DBC0_8197F) & BIT_MASK_WLGP_DBC0_8197F)
+#define BIT_SET_WLGP_DBC0_8197F(x, v)                                          \
+	(BIT_CLEAR_WLGP_DBC0_8197F(x) | BIT_WLGP_DBC0_8197F(v))
+
+/* 2 REG_RPWM2_8197F */
+
+#define BIT_SHIFT_RPWM2_8197F 16
+#define BIT_MASK_RPWM2_8197F 0xffff
+#define BIT_RPWM2_8197F(x)                                                     \
+	(((x) & BIT_MASK_RPWM2_8197F) << BIT_SHIFT_RPWM2_8197F)
+#define BITS_RPWM2_8197F (BIT_MASK_RPWM2_8197F << BIT_SHIFT_RPWM2_8197F)
+#define BIT_CLEAR_RPWM2_8197F(x) ((x) & (~BITS_RPWM2_8197F))
+#define BIT_GET_RPWM2_8197F(x)                                                 \
+	(((x) >> BIT_SHIFT_RPWM2_8197F) & BIT_MASK_RPWM2_8197F)
+#define BIT_SET_RPWM2_8197F(x, v)                                              \
+	(BIT_CLEAR_RPWM2_8197F(x) | BIT_RPWM2_8197F(v))
+
+/* 2 REG_SYSON_FSM_MON_8197F */
+
+#define BIT_SHIFT_FSM_MON_SEL_8197F 24
+#define BIT_MASK_FSM_MON_SEL_8197F 0x7
+#define BIT_FSM_MON_SEL_8197F(x)                                               \
+	(((x) & BIT_MASK_FSM_MON_SEL_8197F) << BIT_SHIFT_FSM_MON_SEL_8197F)
+#define BITS_FSM_MON_SEL_8197F                                                 \
+	(BIT_MASK_FSM_MON_SEL_8197F << BIT_SHIFT_FSM_MON_SEL_8197F)
+#define BIT_CLEAR_FSM_MON_SEL_8197F(x) ((x) & (~BITS_FSM_MON_SEL_8197F))
+#define BIT_GET_FSM_MON_SEL_8197F(x)                                           \
+	(((x) >> BIT_SHIFT_FSM_MON_SEL_8197F) & BIT_MASK_FSM_MON_SEL_8197F)
+#define BIT_SET_FSM_MON_SEL_8197F(x, v)                                        \
+	(BIT_CLEAR_FSM_MON_SEL_8197F(x) | BIT_FSM_MON_SEL_8197F(v))
+
+#define BIT_DOP_ELDO_8197F BIT(23)
+#define BIT_FSM_MON_UPD_8197F BIT(15)
+
+#define BIT_SHIFT_FSM_PAR_8197F 0
+#define BIT_MASK_FSM_PAR_8197F 0x7fff
+#define BIT_FSM_PAR_8197F(x)                                                   \
+	(((x) & BIT_MASK_FSM_PAR_8197F) << BIT_SHIFT_FSM_PAR_8197F)
+#define BITS_FSM_PAR_8197F (BIT_MASK_FSM_PAR_8197F << BIT_SHIFT_FSM_PAR_8197F)
+#define BIT_CLEAR_FSM_PAR_8197F(x) ((x) & (~BITS_FSM_PAR_8197F))
+#define BIT_GET_FSM_PAR_8197F(x)                                               \
+	(((x) >> BIT_SHIFT_FSM_PAR_8197F) & BIT_MASK_FSM_PAR_8197F)
+#define BIT_SET_FSM_PAR_8197F(x, v)                                            \
+	(BIT_CLEAR_FSM_PAR_8197F(x) | BIT_FSM_PAR_8197F(v))
+
+/* 2 REG_AFE_CTRL6_8197F */
+
+#define BIT_SHIFT_TSFT_SEL_V1_8197F 0
+#define BIT_MASK_TSFT_SEL_V1_8197F 0x7
+#define BIT_TSFT_SEL_V1_8197F(x)                                               \
+	(((x) & BIT_MASK_TSFT_SEL_V1_8197F) << BIT_SHIFT_TSFT_SEL_V1_8197F)
+#define BITS_TSFT_SEL_V1_8197F                                                 \
+	(BIT_MASK_TSFT_SEL_V1_8197F << BIT_SHIFT_TSFT_SEL_V1_8197F)
+#define BIT_CLEAR_TSFT_SEL_V1_8197F(x) ((x) & (~BITS_TSFT_SEL_V1_8197F))
+#define BIT_GET_TSFT_SEL_V1_8197F(x)                                           \
+	(((x) >> BIT_SHIFT_TSFT_SEL_V1_8197F) & BIT_MASK_TSFT_SEL_V1_8197F)
+#define BIT_SET_TSFT_SEL_V1_8197F(x, v)                                        \
+	(BIT_CLEAR_TSFT_SEL_V1_8197F(x) | BIT_TSFT_SEL_V1_8197F(v))
+
+/* 2 REG_PMC_DBG_CTRL1_8197F */
+#define BIT_BT_INT_EN_8197F BIT(31)
+
+#define BIT_SHIFT_RD_WR_WIFI_BT_INFO_8197F 16
+#define BIT_MASK_RD_WR_WIFI_BT_INFO_8197F 0x7fff
+#define BIT_RD_WR_WIFI_BT_INFO_8197F(x)                                        \
+	(((x) & BIT_MASK_RD_WR_WIFI_BT_INFO_8197F)                             \
+	 << BIT_SHIFT_RD_WR_WIFI_BT_INFO_8197F)
+#define BITS_RD_WR_WIFI_BT_INFO_8197F                                          \
+	(BIT_MASK_RD_WR_WIFI_BT_INFO_8197F                                     \
+	 << BIT_SHIFT_RD_WR_WIFI_BT_INFO_8197F)
+#define BIT_CLEAR_RD_WR_WIFI_BT_INFO_8197F(x)                                  \
+	((x) & (~BITS_RD_WR_WIFI_BT_INFO_8197F))
+#define BIT_GET_RD_WR_WIFI_BT_INFO_8197F(x)                                    \
+	(((x) >> BIT_SHIFT_RD_WR_WIFI_BT_INFO_8197F) &                         \
+	 BIT_MASK_RD_WR_WIFI_BT_INFO_8197F)
+#define BIT_SET_RD_WR_WIFI_BT_INFO_8197F(x, v)                                 \
+	(BIT_CLEAR_RD_WR_WIFI_BT_INFO_8197F(x) |                               \
+	 BIT_RD_WR_WIFI_BT_INFO_8197F(v))
+
+#define BIT_PMC_WR_OVF_8197F BIT(8)
+
+#define BIT_SHIFT_WLPMC_ERRINT_8197F 0
+#define BIT_MASK_WLPMC_ERRINT_8197F 0xff
+#define BIT_WLPMC_ERRINT_8197F(x)                                              \
+	(((x) & BIT_MASK_WLPMC_ERRINT_8197F) << BIT_SHIFT_WLPMC_ERRINT_8197F)
+#define BITS_WLPMC_ERRINT_8197F                                                \
+	(BIT_MASK_WLPMC_ERRINT_8197F << BIT_SHIFT_WLPMC_ERRINT_8197F)
+#define BIT_CLEAR_WLPMC_ERRINT_8197F(x) ((x) & (~BITS_WLPMC_ERRINT_8197F))
+#define BIT_GET_WLPMC_ERRINT_8197F(x)                                          \
+	(((x) >> BIT_SHIFT_WLPMC_ERRINT_8197F) & BIT_MASK_WLPMC_ERRINT_8197F)
+#define BIT_SET_WLPMC_ERRINT_8197F(x, v)                                       \
+	(BIT_CLEAR_WLPMC_ERRINT_8197F(x) | BIT_WLPMC_ERRINT_8197F(v))
+
+/* 2 REG_AFE_CTRL7_8197F */
+
+#define BIT_SHIFT_SEL_V_8197F 30
+#define BIT_MASK_SEL_V_8197F 0x3
+#define BIT_SEL_V_8197F(x)                                                     \
+	(((x) & BIT_MASK_SEL_V_8197F) << BIT_SHIFT_SEL_V_8197F)
+#define BITS_SEL_V_8197F (BIT_MASK_SEL_V_8197F << BIT_SHIFT_SEL_V_8197F)
+#define BIT_CLEAR_SEL_V_8197F(x) ((x) & (~BITS_SEL_V_8197F))
+#define BIT_GET_SEL_V_8197F(x)                                                 \
+	(((x) >> BIT_SHIFT_SEL_V_8197F) & BIT_MASK_SEL_V_8197F)
+#define BIT_SET_SEL_V_8197F(x, v)                                              \
+	(BIT_CLEAR_SEL_V_8197F(x) | BIT_SEL_V_8197F(v))
+
+#define BIT_SEL_LDO_PC_8197F BIT(29)
+
+#define BIT_SHIFT_CK_MON_SEL_V2_8197F 26
+#define BIT_MASK_CK_MON_SEL_V2_8197F 0x7
+#define BIT_CK_MON_SEL_V2_8197F(x)                                             \
+	(((x) & BIT_MASK_CK_MON_SEL_V2_8197F) << BIT_SHIFT_CK_MON_SEL_V2_8197F)
+#define BITS_CK_MON_SEL_V2_8197F                                               \
+	(BIT_MASK_CK_MON_SEL_V2_8197F << BIT_SHIFT_CK_MON_SEL_V2_8197F)
+#define BIT_CLEAR_CK_MON_SEL_V2_8197F(x) ((x) & (~BITS_CK_MON_SEL_V2_8197F))
+#define BIT_GET_CK_MON_SEL_V2_8197F(x)                                         \
+	(((x) >> BIT_SHIFT_CK_MON_SEL_V2_8197F) & BIT_MASK_CK_MON_SEL_V2_8197F)
+#define BIT_SET_CK_MON_SEL_V2_8197F(x, v)                                      \
+	(BIT_CLEAR_CK_MON_SEL_V2_8197F(x) | BIT_CK_MON_SEL_V2_8197F(v))
+
+#define BIT_CK_MON_EN_8197F BIT(25)
+#define BIT_FREF_EDGE_8197F BIT(24)
+#define BIT_CK320M_EN_8197F BIT(23)
+#define BIT_CK_5M_EN_8197F BIT(22)
+#define BIT_TESTEN_8197F BIT(21)
+
+/* 2 REG_HIMR0_8197F */
+#define BIT_TIMEOUT_INTERRUPT2_MASK_8197F BIT(31)
+#define BIT_TIMEOUT_INTERRUTP1_MASK_8197F BIT(30)
+#define BIT_PSTIMEOUT_MSK_8197F BIT(29)
+#define BIT_GTINT4_MSK_8197F BIT(28)
+#define BIT_GTINT3_MSK_8197F BIT(27)
+#define BIT_TXBCN0ERR_MSK_8197F BIT(26)
+#define BIT_TXBCN0OK_MSK_8197F BIT(25)
+#define BIT_TSF_BIT32_TOGGLE_MSK_8197F BIT(24)
+#define BIT_BCNDMAINT0_MSK_8197F BIT(20)
+#define BIT_BCNDERR0_MSK_8197F BIT(16)
+#define BIT_HSISR_IND_ON_INT_MSK_8197F BIT(15)
+#define BIT_HISR3_IND_INT_MSK_8197F BIT(14)
+#define BIT_HISR2_IND_INT_MSK_8197F BIT(13)
+#define BIT_CTWEND_MSK_8197F BIT(12)
+#define BIT_HISR1_IND_MSK_8197F BIT(11)
+#define BIT_C2HCMD_MSK_8197F BIT(10)
+#define BIT_CPWM2_MSK_8197F BIT(9)
+#define BIT_CPWM_MSK_8197F BIT(8)
+#define BIT_HIGHDOK_MSK_8197F BIT(7)
+#define BIT_MGTDOK_MSK_8197F BIT(6)
+#define BIT_BKDOK_MSK_8197F BIT(5)
+#define BIT_BEDOK_MSK_8197F BIT(4)
+#define BIT_VIDOK_MSK_8197F BIT(3)
+#define BIT_VODOK_MSK_8197F BIT(2)
+#define BIT_RDU_MSK_8197F BIT(1)
+#define BIT_RXOK_MSK_8197F BIT(0)
+
+/* 2 REG_HISR0_8197F */
+#define BIT_PSTIMEOUT2_8197F BIT(31)
+#define BIT_PSTIMEOUT1_8197F BIT(30)
+#define BIT_PSTIMEOUT_8197F BIT(29)
+#define BIT_GTINT4_8197F BIT(28)
+#define BIT_GTINT3_8197F BIT(27)
+#define BIT_TXBCN0ERR_8197F BIT(26)
+#define BIT_TXBCN0OK_8197F BIT(25)
+#define BIT_TSF_BIT32_TOGGLE_8197F BIT(24)
+#define BIT_BCNDMAINT0_8197F BIT(20)
+#define BIT_BCNDERR0_8197F BIT(16)
+#define BIT_HSISR_IND_ON_INT_8197F BIT(15)
+#define BIT_HISR3_IND_INT_8197F BIT(14)
+#define BIT_HISR2_IND_INT_8197F BIT(13)
+#define BIT_CTWEND_8197F BIT(12)
+#define BIT_HISR1_IND_INT_8197F BIT(11)
+#define BIT_C2HCMD_8197F BIT(10)
+#define BIT_CPWM2_8197F BIT(9)
+#define BIT_CPWM_8197F BIT(8)
+#define BIT_HIGHDOK_8197F BIT(7)
+#define BIT_MGTDOK_8197F BIT(6)
+#define BIT_BKDOK_8197F BIT(5)
+#define BIT_BEDOK_8197F BIT(4)
+#define BIT_VIDOK_8197F BIT(3)
+#define BIT_VODOK_8197F BIT(2)
+#define BIT_RDU_8197F BIT(1)
+#define BIT_RXOK_8197F BIT(0)
+
+/* 2 REG_HIMR1_8197F */
+#define BIT_BTON_STS_UPDATE_MSK_8197F BIT(29)
+#define BIT_MCU_ERR_MASK_8197F BIT(28)
+#define BIT_BCNDMAINT7__MSK_8197F BIT(27)
+#define BIT_BCNDMAINT6__MSK_8197F BIT(26)
+#define BIT_BCNDMAINT5__MSK_8197F BIT(25)
+#define BIT_BCNDMAINT4__MSK_8197F BIT(24)
+#define BIT_BCNDMAINT3_MSK_8197F BIT(23)
+#define BIT_BCNDMAINT2_MSK_8197F BIT(22)
+#define BIT_BCNDMAINT1_MSK_8197F BIT(21)
+#define BIT_BCNDERR7_MSK_8197F BIT(20)
+#define BIT_BCNDERR6_MSK_8197F BIT(19)
+#define BIT_BCNDERR5_MSK_8197F BIT(18)
+#define BIT_BCNDERR4_MSK_8197F BIT(17)
+#define BIT_BCNDERR3_MSK_8197F BIT(16)
+#define BIT_BCNDERR2_MSK_8197F BIT(15)
+#define BIT_BCNDERR1_MSK_8197F BIT(14)
+#define BIT_ATIMEND_E_MSK_8197F BIT(13)
+#define BIT_ATIMEND__MSK_8197F BIT(12)
+#define BIT_TXERR_MSK_8197F BIT(11)
+#define BIT_RXERR_MSK_8197F BIT(10)
+#define BIT_TXFOVW_MSK_8197F BIT(9)
+#define BIT_FOVW_MSK_8197F BIT(8)
+
+/* 2 REG_HISR1_8197F */
+#define BIT_BTON_STS_UPDATE_INT_8197F BIT(29)
+#define BIT_MCU_ERR_8197F BIT(28)
+#define BIT_BCNDMAINT7_8197F BIT(27)
+#define BIT_BCNDMAINT6_8197F BIT(26)
+#define BIT_BCNDMAINT5_8197F BIT(25)
+#define BIT_BCNDMAINT4_8197F BIT(24)
+#define BIT_BCNDMAINT3_8197F BIT(23)
+#define BIT_BCNDMAINT2_8197F BIT(22)
+#define BIT_BCNDMAINT1_8197F BIT(21)
+#define BIT_BCNDERR7_8197F BIT(20)
+#define BIT_BCNDERR6_8197F BIT(19)
+#define BIT_BCNDERR5_8197F BIT(18)
+#define BIT_BCNDERR4_8197F BIT(17)
+#define BIT_BCNDERR3_8197F BIT(16)
+#define BIT_BCNDERR2_8197F BIT(15)
+#define BIT_BCNDERR1_8197F BIT(14)
+#define BIT_ATIMEND_E_8197F BIT(13)
+#define BIT_ATIMEND_8197F BIT(12)
+#define BIT_TXERR_INT_8197F BIT(11)
+#define BIT_RXERR_INT_8197F BIT(10)
+#define BIT_TXFOVW_8197F BIT(9)
+#define BIT_FOVW_8197F BIT(8)
+
+/* 2 REG_DBG_PORT_SEL_8197F */
+
+#define BIT_SHIFT_DEBUG_ST_8197F 0
+#define BIT_MASK_DEBUG_ST_8197F 0xffffffffL
+#define BIT_DEBUG_ST_8197F(x)                                                  \
+	(((x) & BIT_MASK_DEBUG_ST_8197F) << BIT_SHIFT_DEBUG_ST_8197F)
+#define BITS_DEBUG_ST_8197F                                                    \
+	(BIT_MASK_DEBUG_ST_8197F << BIT_SHIFT_DEBUG_ST_8197F)
+#define BIT_CLEAR_DEBUG_ST_8197F(x) ((x) & (~BITS_DEBUG_ST_8197F))
+#define BIT_GET_DEBUG_ST_8197F(x)                                              \
+	(((x) >> BIT_SHIFT_DEBUG_ST_8197F) & BIT_MASK_DEBUG_ST_8197F)
+#define BIT_SET_DEBUG_ST_8197F(x, v)                                           \
+	(BIT_CLEAR_DEBUG_ST_8197F(x) | BIT_DEBUG_ST_8197F(v))
+
+/* 2 REG_PAD_CTRL2_8197F */
+
+/* 2 REG_NOT_VALID_8197F */
+
+/* 2 REG_NOT_VALID_8197F */
+
+/* 2 REG_NOT_VALID_8197F */
+
+/* 2 REG_NOT_VALID_8197F */
+
+/* 2 REG_NOT_VALID_8197F */
+#define BIT_LD_B12V_EN_V1_8197F BIT(7)
+#define BIT_EECS_IOSEL_V1_8197F BIT(6)
+#define BIT_EECS_DATA_O_V1_8197F BIT(5)
+#define BIT_EECS_DATA_I_V1_8197F BIT(4)
+#define BIT_EESK_IOSEL_V1_8197F BIT(2)
+#define BIT_EESK_DATA_O_V1_8197F BIT(1)
+#define BIT_EESK_DATA_I_V1_8197F BIT(0)
+
+/* 2 REG_NOT_VALID_8197F */
+
+/* 2 REG_PMC_DBG_CTRL2_8197F */
+
+#define BIT_SHIFT_EFUSE_BURN_GNT_8197F 24
+#define BIT_MASK_EFUSE_BURN_GNT_8197F 0xff
+#define BIT_EFUSE_BURN_GNT_8197F(x)                                            \
+	(((x) & BIT_MASK_EFUSE_BURN_GNT_8197F)                                 \
+	 << BIT_SHIFT_EFUSE_BURN_GNT_8197F)
+#define BITS_EFUSE_BURN_GNT_8197F                                              \
+	(BIT_MASK_EFUSE_BURN_GNT_8197F << BIT_SHIFT_EFUSE_BURN_GNT_8197F)
+#define BIT_CLEAR_EFUSE_BURN_GNT_8197F(x) ((x) & (~BITS_EFUSE_BURN_GNT_8197F))
+#define BIT_GET_EFUSE_BURN_GNT_8197F(x)                                        \
+	(((x) >> BIT_SHIFT_EFUSE_BURN_GNT_8197F) &                             \
+	 BIT_MASK_EFUSE_BURN_GNT_8197F)
+#define BIT_SET_EFUSE_BURN_GNT_8197F(x, v)                                     \
+	(BIT_CLEAR_EFUSE_BURN_GNT_8197F(x) | BIT_EFUSE_BURN_GNT_8197F(v))
+
+#define BIT_STOP_WL_PMC_8197F BIT(9)
+#define BIT_STOP_SYM_PMC_8197F BIT(8)
+#define BIT_REG_RST_WLPMC_8197F BIT(5)
+#define BIT_REG_RST_PD12N_8197F BIT(4)
+#define BIT_SYSON_DIS_WLREG_WRMSK_8197F BIT(3)
+#define BIT_SYSON_DIS_PMCREG_WRMSK_8197F BIT(2)
+
+#define BIT_SHIFT_SYSON_REG_ARB_8197F 0
+#define BIT_MASK_SYSON_REG_ARB_8197F 0x3
+#define BIT_SYSON_REG_ARB_8197F(x)                                             \
+	(((x) & BIT_MASK_SYSON_REG_ARB_8197F) << BIT_SHIFT_SYSON_REG_ARB_8197F)
+#define BITS_SYSON_REG_ARB_8197F                                               \
+	(BIT_MASK_SYSON_REG_ARB_8197F << BIT_SHIFT_SYSON_REG_ARB_8197F)
+#define BIT_CLEAR_SYSON_REG_ARB_8197F(x) ((x) & (~BITS_SYSON_REG_ARB_8197F))
+#define BIT_GET_SYSON_REG_ARB_8197F(x)                                         \
+	(((x) >> BIT_SHIFT_SYSON_REG_ARB_8197F) & BIT_MASK_SYSON_REG_ARB_8197F)
+#define BIT_SET_SYSON_REG_ARB_8197F(x, v)                                      \
+	(BIT_CLEAR_SYSON_REG_ARB_8197F(x) | BIT_SYSON_REG_ARB_8197F(v))
+
+/* 2 REG_BIST_CTRL_8197F */
+#define BIT_BIST_USB_DIS_8197F BIT(27)
+#define BIT_BIST_PCI_DIS_8197F BIT(26)
+#define BIT_BIST_BT_DIS_8197F BIT(25)
+#define BIT_BIST_WL_DIS_8197F BIT(24)
+
+#define BIT_SHIFT_BIST_RPT_SEL_8197F 16
+#define BIT_MASK_BIST_RPT_SEL_8197F 0xf
+#define BIT_BIST_RPT_SEL_8197F(x)                                              \
+	(((x) & BIT_MASK_BIST_RPT_SEL_8197F) << BIT_SHIFT_BIST_RPT_SEL_8197F)
+#define BITS_BIST_RPT_SEL_8197F                                                \
+	(BIT_MASK_BIST_RPT_SEL_8197F << BIT_SHIFT_BIST_RPT_SEL_8197F)
+#define BIT_CLEAR_BIST_RPT_SEL_8197F(x) ((x) & (~BITS_BIST_RPT_SEL_8197F))
+#define BIT_GET_BIST_RPT_SEL_8197F(x)                                          \
+	(((x) >> BIT_SHIFT_BIST_RPT_SEL_8197F) & BIT_MASK_BIST_RPT_SEL_8197F)
+#define BIT_SET_BIST_RPT_SEL_8197F(x, v)                                       \
+	(BIT_CLEAR_BIST_RPT_SEL_8197F(x) | BIT_BIST_RPT_SEL_8197F(v))
+
+#define BIT_BIST_RESUME_PS_8197F BIT(4)
+#define BIT_BIST_RESUME_8197F BIT(3)
+#define BIT_BIST_NORMAL_8197F BIT(2)
+#define BIT_BIST_RSTN_8197F BIT(1)
+#define BIT_BIST_CLK_EN_8197F BIT(0)
+
+/* 2 REG_BIST_RPT_8197F */
+
+#define BIT_SHIFT_MBIST_REPORT_8197F 0
+#define BIT_MASK_MBIST_REPORT_8197F 0xffffffffL
+#define BIT_MBIST_REPORT_8197F(x)                                              \
+	(((x) & BIT_MASK_MBIST_REPORT_8197F) << BIT_SHIFT_MBIST_REPORT_8197F)
+#define BITS_MBIST_REPORT_8197F                                                \
+	(BIT_MASK_MBIST_REPORT_8197F << BIT_SHIFT_MBIST_REPORT_8197F)
+#define BIT_CLEAR_MBIST_REPORT_8197F(x) ((x) & (~BITS_MBIST_REPORT_8197F))
+#define BIT_GET_MBIST_REPORT_8197F(x)                                          \
+	(((x) >> BIT_SHIFT_MBIST_REPORT_8197F) & BIT_MASK_MBIST_REPORT_8197F)
+#define BIT_SET_MBIST_REPORT_8197F(x, v)                                       \
+	(BIT_CLEAR_MBIST_REPORT_8197F(x) | BIT_MBIST_REPORT_8197F(v))
+
+/* 2 REG_MEM_CTRL_8197F */
+#define BIT_UMEM_RME_8197F BIT(31)
+
+#define BIT_SHIFT_BT_SPRAM_8197F 28
+#define BIT_MASK_BT_SPRAM_8197F 0x3
+#define BIT_BT_SPRAM_8197F(x)                                                  \
+	(((x) & BIT_MASK_BT_SPRAM_8197F) << BIT_SHIFT_BT_SPRAM_8197F)
+#define BITS_BT_SPRAM_8197F                                                    \
+	(BIT_MASK_BT_SPRAM_8197F << BIT_SHIFT_BT_SPRAM_8197F)
+#define BIT_CLEAR_BT_SPRAM_8197F(x) ((x) & (~BITS_BT_SPRAM_8197F))
+#define BIT_GET_BT_SPRAM_8197F(x)                                              \
+	(((x) >> BIT_SHIFT_BT_SPRAM_8197F) & BIT_MASK_BT_SPRAM_8197F)
+#define BIT_SET_BT_SPRAM_8197F(x, v)                                           \
+	(BIT_CLEAR_BT_SPRAM_8197F(x) | BIT_BT_SPRAM_8197F(v))
+
+#define BIT_SHIFT_BT_ROM_8197F 24
+#define BIT_MASK_BT_ROM_8197F 0xf
+#define BIT_BT_ROM_8197F(x)                                                    \
+	(((x) & BIT_MASK_BT_ROM_8197F) << BIT_SHIFT_BT_ROM_8197F)
+#define BITS_BT_ROM_8197F (BIT_MASK_BT_ROM_8197F << BIT_SHIFT_BT_ROM_8197F)
+#define BIT_CLEAR_BT_ROM_8197F(x) ((x) & (~BITS_BT_ROM_8197F))
+#define BIT_GET_BT_ROM_8197F(x)                                                \
+	(((x) >> BIT_SHIFT_BT_ROM_8197F) & BIT_MASK_BT_ROM_8197F)
+#define BIT_SET_BT_ROM_8197F(x, v)                                             \
+	(BIT_CLEAR_BT_ROM_8197F(x) | BIT_BT_ROM_8197F(v))
+
+#define BIT_SHIFT_PCI_DPRAM_8197F 10
+#define BIT_MASK_PCI_DPRAM_8197F 0x3
+#define BIT_PCI_DPRAM_8197F(x)                                                 \
+	(((x) & BIT_MASK_PCI_DPRAM_8197F) << BIT_SHIFT_PCI_DPRAM_8197F)
+#define BITS_PCI_DPRAM_8197F                                                   \
+	(BIT_MASK_PCI_DPRAM_8197F << BIT_SHIFT_PCI_DPRAM_8197F)
+#define BIT_CLEAR_PCI_DPRAM_8197F(x) ((x) & (~BITS_PCI_DPRAM_8197F))
+#define BIT_GET_PCI_DPRAM_8197F(x)                                             \
+	(((x) >> BIT_SHIFT_PCI_DPRAM_8197F) & BIT_MASK_PCI_DPRAM_8197F)
+#define BIT_SET_PCI_DPRAM_8197F(x, v)                                          \
+	(BIT_CLEAR_PCI_DPRAM_8197F(x) | BIT_PCI_DPRAM_8197F(v))
+
+#define BIT_SHIFT_PCI_SPRAM_8197F 8
+#define BIT_MASK_PCI_SPRAM_8197F 0x3
+#define BIT_PCI_SPRAM_8197F(x)                                                 \
+	(((x) & BIT_MASK_PCI_SPRAM_8197F) << BIT_SHIFT_PCI_SPRAM_8197F)
+#define BITS_PCI_SPRAM_8197F                                                   \
+	(BIT_MASK_PCI_SPRAM_8197F << BIT_SHIFT_PCI_SPRAM_8197F)
+#define BIT_CLEAR_PCI_SPRAM_8197F(x) ((x) & (~BITS_PCI_SPRAM_8197F))
+#define BIT_GET_PCI_SPRAM_8197F(x)                                             \
+	(((x) >> BIT_SHIFT_PCI_SPRAM_8197F) & BIT_MASK_PCI_SPRAM_8197F)
+#define BIT_SET_PCI_SPRAM_8197F(x, v)                                          \
+	(BIT_CLEAR_PCI_SPRAM_8197F(x) | BIT_PCI_SPRAM_8197F(v))
+
+#define BIT_SHIFT_USB_SPRAM_8197F 6
+#define BIT_MASK_USB_SPRAM_8197F 0x3
+#define BIT_USB_SPRAM_8197F(x)                                                 \
+	(((x) & BIT_MASK_USB_SPRAM_8197F) << BIT_SHIFT_USB_SPRAM_8197F)
+#define BITS_USB_SPRAM_8197F                                                   \
+	(BIT_MASK_USB_SPRAM_8197F << BIT_SHIFT_USB_SPRAM_8197F)
+#define BIT_CLEAR_USB_SPRAM_8197F(x) ((x) & (~BITS_USB_SPRAM_8197F))
+#define BIT_GET_USB_SPRAM_8197F(x)                                             \
+	(((x) >> BIT_SHIFT_USB_SPRAM_8197F) & BIT_MASK_USB_SPRAM_8197F)
+#define BIT_SET_USB_SPRAM_8197F(x, v)                                          \
+	(BIT_CLEAR_USB_SPRAM_8197F(x) | BIT_USB_SPRAM_8197F(v))
+
+#define BIT_SHIFT_USB_SPRF_8197F 4
+#define BIT_MASK_USB_SPRF_8197F 0x3
+#define BIT_USB_SPRF_8197F(x)                                                  \
+	(((x) & BIT_MASK_USB_SPRF_8197F) << BIT_SHIFT_USB_SPRF_8197F)
+#define BITS_USB_SPRF_8197F                                                    \
+	(BIT_MASK_USB_SPRF_8197F << BIT_SHIFT_USB_SPRF_8197F)
+#define BIT_CLEAR_USB_SPRF_8197F(x) ((x) & (~BITS_USB_SPRF_8197F))
+#define BIT_GET_USB_SPRF_8197F(x)                                              \
+	(((x) >> BIT_SHIFT_USB_SPRF_8197F) & BIT_MASK_USB_SPRF_8197F)
+#define BIT_SET_USB_SPRF_8197F(x, v)                                           \
+	(BIT_CLEAR_USB_SPRF_8197F(x) | BIT_USB_SPRF_8197F(v))
+
+#define BIT_SHIFT_MCU_ROM_8197F 0
+#define BIT_MASK_MCU_ROM_8197F 0xf
+#define BIT_MCU_ROM_8197F(x)                                                   \
+	(((x) & BIT_MASK_MCU_ROM_8197F) << BIT_SHIFT_MCU_ROM_8197F)
+#define BITS_MCU_ROM_8197F (BIT_MASK_MCU_ROM_8197F << BIT_SHIFT_MCU_ROM_8197F)
+#define BIT_CLEAR_MCU_ROM_8197F(x) ((x) & (~BITS_MCU_ROM_8197F))
+#define BIT_GET_MCU_ROM_8197F(x)                                               \
+	(((x) >> BIT_SHIFT_MCU_ROM_8197F) & BIT_MASK_MCU_ROM_8197F)
+#define BIT_SET_MCU_ROM_8197F(x, v)                                            \
+	(BIT_CLEAR_MCU_ROM_8197F(x) | BIT_MCU_ROM_8197F(v))
+
+/* 2 REG_AFE_CTRL8_8197F */
+
+#define BIT_SHIFT_BB_DBG_SEL_AFE_SDM_V4_8197F 26
+#define BIT_MASK_BB_DBG_SEL_AFE_SDM_V4_8197F 0x7
+#define BIT_BB_DBG_SEL_AFE_SDM_V4_8197F(x)                                     \
+	(((x) & BIT_MASK_BB_DBG_SEL_AFE_SDM_V4_8197F)                          \
+	 << BIT_SHIFT_BB_DBG_SEL_AFE_SDM_V4_8197F)
+#define BITS_BB_DBG_SEL_AFE_SDM_V4_8197F                                       \
+	(BIT_MASK_BB_DBG_SEL_AFE_SDM_V4_8197F                                  \
+	 << BIT_SHIFT_BB_DBG_SEL_AFE_SDM_V4_8197F)
+#define BIT_CLEAR_BB_DBG_SEL_AFE_SDM_V4_8197F(x)                               \
+	((x) & (~BITS_BB_DBG_SEL_AFE_SDM_V4_8197F))
+#define BIT_GET_BB_DBG_SEL_AFE_SDM_V4_8197F(x)                                 \
+	(((x) >> BIT_SHIFT_BB_DBG_SEL_AFE_SDM_V4_8197F) &                      \
+	 BIT_MASK_BB_DBG_SEL_AFE_SDM_V4_8197F)
+#define BIT_SET_BB_DBG_SEL_AFE_SDM_V4_8197F(x, v)                              \
+	(BIT_CLEAR_BB_DBG_SEL_AFE_SDM_V4_8197F(x) |                            \
+	 BIT_BB_DBG_SEL_AFE_SDM_V4_8197F(v))
+
+#define BIT_SYN_AGPIO_8197F BIT(20)
+
+#define BIT_SHIFT_XTAL_SEL_TOK_V2_8197F 0
+#define BIT_MASK_XTAL_SEL_TOK_V2_8197F 0x7
+#define BIT_XTAL_SEL_TOK_V2_8197F(x)                                           \
+	(((x) & BIT_MASK_XTAL_SEL_TOK_V2_8197F)                                \
+	 << BIT_SHIFT_XTAL_SEL_TOK_V2_8197F)
+#define BITS_XTAL_SEL_TOK_V2_8197F                                             \
+	(BIT_MASK_XTAL_SEL_TOK_V2_8197F << BIT_SHIFT_XTAL_SEL_TOK_V2_8197F)
+#define BIT_CLEAR_XTAL_SEL_TOK_V2_8197F(x) ((x) & (~BITS_XTAL_SEL_TOK_V2_8197F))
+#define BIT_GET_XTAL_SEL_TOK_V2_8197F(x)                                       \
+	(((x) >> BIT_SHIFT_XTAL_SEL_TOK_V2_8197F) &                            \
+	 BIT_MASK_XTAL_SEL_TOK_V2_8197F)
+#define BIT_SET_XTAL_SEL_TOK_V2_8197F(x, v)                                    \
+	(BIT_CLEAR_XTAL_SEL_TOK_V2_8197F(x) | BIT_XTAL_SEL_TOK_V2_8197F(v))
+
+/* 2 REG_USB_SIE_INTF_8197F */
+
+/* 2 REG_NOT_VALID_8197F */
+
+/* 2 REG_NOT_VALID_8197F */
+
+/* 2 REG_NOT_VALID_8197F */
+
+/* 2 REG_NOT_VALID_8197F */
+
+/* 2 REG_NOT_VALID_8197F */
+
+/* 2 REG_NOT_VALID_8197F */
+
+/* 2 REG_NOT_VALID_8197F */
+
+/* 2 REG_PCIE_MIO_INTF_8197F */
+#define BIT_PCIE_MIO_BYIOREG_8197F BIT(13)
+#define BIT_PCIE_MIO_RE_8197F BIT(12)
+
+#define BIT_SHIFT_PCIE_MIO_WE_8197F 8
+#define BIT_MASK_PCIE_MIO_WE_8197F 0xf
+#define BIT_PCIE_MIO_WE_8197F(x)                                               \
+	(((x) & BIT_MASK_PCIE_MIO_WE_8197F) << BIT_SHIFT_PCIE_MIO_WE_8197F)
+#define BITS_PCIE_MIO_WE_8197F                                                 \
+	(BIT_MASK_PCIE_MIO_WE_8197F << BIT_SHIFT_PCIE_MIO_WE_8197F)
+#define BIT_CLEAR_PCIE_MIO_WE_8197F(x) ((x) & (~BITS_PCIE_MIO_WE_8197F))
+#define BIT_GET_PCIE_MIO_WE_8197F(x)                                           \
+	(((x) >> BIT_SHIFT_PCIE_MIO_WE_8197F) & BIT_MASK_PCIE_MIO_WE_8197F)
+#define BIT_SET_PCIE_MIO_WE_8197F(x, v)                                        \
+	(BIT_CLEAR_PCIE_MIO_WE_8197F(x) | BIT_PCIE_MIO_WE_8197F(v))
+
+#define BIT_SHIFT_PCIE_MIO_ADDR_8197F 0
+#define BIT_MASK_PCIE_MIO_ADDR_8197F 0xff
+#define BIT_PCIE_MIO_ADDR_8197F(x)                                             \
+	(((x) & BIT_MASK_PCIE_MIO_ADDR_8197F) << BIT_SHIFT_PCIE_MIO_ADDR_8197F)
+#define BITS_PCIE_MIO_ADDR_8197F                                               \
+	(BIT_MASK_PCIE_MIO_ADDR_8197F << BIT_SHIFT_PCIE_MIO_ADDR_8197F)
+#define BIT_CLEAR_PCIE_MIO_ADDR_8197F(x) ((x) & (~BITS_PCIE_MIO_ADDR_8197F))
+#define BIT_GET_PCIE_MIO_ADDR_8197F(x)                                         \
+	(((x) >> BIT_SHIFT_PCIE_MIO_ADDR_8197F) & BIT_MASK_PCIE_MIO_ADDR_8197F)
+#define BIT_SET_PCIE_MIO_ADDR_8197F(x, v)                                      \
+	(BIT_CLEAR_PCIE_MIO_ADDR_8197F(x) | BIT_PCIE_MIO_ADDR_8197F(v))
+
+/* 2 REG_PCIE_MIO_INTD_8197F */
+
+#define BIT_SHIFT_PCIE_MIO_DATA_8197F 0
+#define BIT_MASK_PCIE_MIO_DATA_8197F 0xffffffffL
+#define BIT_PCIE_MIO_DATA_8197F(x)                                             \
+	(((x) & BIT_MASK_PCIE_MIO_DATA_8197F) << BIT_SHIFT_PCIE_MIO_DATA_8197F)
+#define BITS_PCIE_MIO_DATA_8197F                                               \
+	(BIT_MASK_PCIE_MIO_DATA_8197F << BIT_SHIFT_PCIE_MIO_DATA_8197F)
+#define BIT_CLEAR_PCIE_MIO_DATA_8197F(x) ((x) & (~BITS_PCIE_MIO_DATA_8197F))
+#define BIT_GET_PCIE_MIO_DATA_8197F(x)                                         \
+	(((x) >> BIT_SHIFT_PCIE_MIO_DATA_8197F) & BIT_MASK_PCIE_MIO_DATA_8197F)
+#define BIT_SET_PCIE_MIO_DATA_8197F(x, v)                                      \
+	(BIT_CLEAR_PCIE_MIO_DATA_8197F(x) | BIT_PCIE_MIO_DATA_8197F(v))
+
+/* 2 REG_WLRF1_8197F */
+
+/* 2 REG_SYS_CFG1_8197F */
+
+#define BIT_SHIFT_TRP_ICFG_8197F 28
+#define BIT_MASK_TRP_ICFG_8197F 0xf
+#define BIT_TRP_ICFG_8197F(x)                                                  \
+	(((x) & BIT_MASK_TRP_ICFG_8197F) << BIT_SHIFT_TRP_ICFG_8197F)
+#define BITS_TRP_ICFG_8197F                                                    \
+	(BIT_MASK_TRP_ICFG_8197F << BIT_SHIFT_TRP_ICFG_8197F)
+#define BIT_CLEAR_TRP_ICFG_8197F(x) ((x) & (~BITS_TRP_ICFG_8197F))
+#define BIT_GET_TRP_ICFG_8197F(x)                                              \
+	(((x) >> BIT_SHIFT_TRP_ICFG_8197F) & BIT_MASK_TRP_ICFG_8197F)
+#define BIT_SET_TRP_ICFG_8197F(x, v)                                           \
+	(BIT_CLEAR_TRP_ICFG_8197F(x) | BIT_TRP_ICFG_8197F(v))
+
+#define BIT_RF_TYPE_ID_8197F BIT(27)
+#define BIT_BD_HCI_SEL_8197F BIT(26)
+#define BIT_BD_PKG_SEL_8197F BIT(25)
+#define BIT_SPSLDO_SEL_8197F BIT(24)
+#define BIT_RTL_ID_8197F BIT(23)
+#define BIT_PAD_HWPD_IDN_8197F BIT(22)
+#define BIT_TESTMODE_8197F BIT(20)
+
+#define BIT_SHIFT_VENDOR_ID_8197F 16
+#define BIT_MASK_VENDOR_ID_8197F 0xf
+#define BIT_VENDOR_ID_8197F(x)                                                 \
+	(((x) & BIT_MASK_VENDOR_ID_8197F) << BIT_SHIFT_VENDOR_ID_8197F)
+#define BITS_VENDOR_ID_8197F                                                   \
+	(BIT_MASK_VENDOR_ID_8197F << BIT_SHIFT_VENDOR_ID_8197F)
+#define BIT_CLEAR_VENDOR_ID_8197F(x) ((x) & (~BITS_VENDOR_ID_8197F))
+#define BIT_GET_VENDOR_ID_8197F(x)                                             \
+	(((x) >> BIT_SHIFT_VENDOR_ID_8197F) & BIT_MASK_VENDOR_ID_8197F)
+#define BIT_SET_VENDOR_ID_8197F(x, v)                                          \
+	(BIT_CLEAR_VENDOR_ID_8197F(x) | BIT_VENDOR_ID_8197F(v))
+
+#define BIT_SHIFT_CHIP_VER_8197F 12
+#define BIT_MASK_CHIP_VER_8197F 0xf
+#define BIT_CHIP_VER_8197F(x)                                                  \
+	(((x) & BIT_MASK_CHIP_VER_8197F) << BIT_SHIFT_CHIP_VER_8197F)
+#define BITS_CHIP_VER_8197F                                                    \
+	(BIT_MASK_CHIP_VER_8197F << BIT_SHIFT_CHIP_VER_8197F)
+#define BIT_CLEAR_CHIP_VER_8197F(x) ((x) & (~BITS_CHIP_VER_8197F))
+#define BIT_GET_CHIP_VER_8197F(x)                                              \
+	(((x) >> BIT_SHIFT_CHIP_VER_8197F) & BIT_MASK_CHIP_VER_8197F)
+#define BIT_SET_CHIP_VER_8197F(x, v)                                           \
+	(BIT_CLEAR_CHIP_VER_8197F(x) | BIT_CHIP_VER_8197F(v))
+
+#define BIT_BD_MAC1_8197F BIT(10)
+#define BIT_BD_MAC2_8197F BIT(9)
+#define BIT_SIC_IDLE_8197F BIT(8)
+#define BIT_SW_OFFLOAD_EN_8197F BIT(7)
+#define BIT_OCP_SHUTDN_8197F BIT(6)
+#define BIT_V15_VLD_8197F BIT(5)
+#define BIT_PCIRSTB_8197F BIT(4)
+#define BIT_PCLK_VLD_8197F BIT(3)
+#define BIT_UCLK_VLD_8197F BIT(2)
+#define BIT_ACLK_VLD_8197F BIT(1)
+#define BIT_XCLK_VLD_8197F BIT(0)
+
+/* 2 REG_SYS_STATUS1_8197F */
+
+#define BIT_SHIFT_RF_RL_ID_8197F 28
+#define BIT_MASK_RF_RL_ID_8197F 0xf
+#define BIT_RF_RL_ID_8197F(x)                                                  \
+	(((x) & BIT_MASK_RF_RL_ID_8197F) << BIT_SHIFT_RF_RL_ID_8197F)
+#define BITS_RF_RL_ID_8197F                                                    \
+	(BIT_MASK_RF_RL_ID_8197F << BIT_SHIFT_RF_RL_ID_8197F)
+#define BIT_CLEAR_RF_RL_ID_8197F(x) ((x) & (~BITS_RF_RL_ID_8197F))
+#define BIT_GET_RF_RL_ID_8197F(x)                                              \
+	(((x) >> BIT_SHIFT_RF_RL_ID_8197F) & BIT_MASK_RF_RL_ID_8197F)
+#define BIT_SET_RF_RL_ID_8197F(x, v)                                           \
+	(BIT_CLEAR_RF_RL_ID_8197F(x) | BIT_RF_RL_ID_8197F(v))
+
+#define BIT_HPHY_ICFG_8197F BIT(19)
+
+#define BIT_SHIFT_SEL_0XC0_8197F 16
+#define BIT_MASK_SEL_0XC0_8197F 0x3
+#define BIT_SEL_0XC0_8197F(x)                                                  \
+	(((x) & BIT_MASK_SEL_0XC0_8197F) << BIT_SHIFT_SEL_0XC0_8197F)
+#define BITS_SEL_0XC0_8197F                                                    \
+	(BIT_MASK_SEL_0XC0_8197F << BIT_SHIFT_SEL_0XC0_8197F)
+#define BIT_CLEAR_SEL_0XC0_8197F(x) ((x) & (~BITS_SEL_0XC0_8197F))
+#define BIT_GET_SEL_0XC0_8197F(x)                                              \
+	(((x) >> BIT_SHIFT_SEL_0XC0_8197F) & BIT_MASK_SEL_0XC0_8197F)
+#define BIT_SET_SEL_0XC0_8197F(x, v)                                           \
+	(BIT_CLEAR_SEL_0XC0_8197F(x) | BIT_SEL_0XC0_8197F(v))
+
+#define BIT_USB_OPERATION_MODE_8197F BIT(10)
+#define BIT_BT_PDN_8197F BIT(9)
+#define BIT_AUTO_WLPON_8197F BIT(8)
+#define BIT_WL_MODE_8197F BIT(7)
+#define BIT_PKG_SEL_HCI_8197F BIT(6)
+
+#define BIT_SHIFT_HCI_SEL_8197F 4
+#define BIT_MASK_HCI_SEL_8197F 0x3
+#define BIT_HCI_SEL_8197F(x)                                                   \
+	(((x) & BIT_MASK_HCI_SEL_8197F) << BIT_SHIFT_HCI_SEL_8197F)
+#define BITS_HCI_SEL_8197F (BIT_MASK_HCI_SEL_8197F << BIT_SHIFT_HCI_SEL_8197F)
+#define BIT_CLEAR_HCI_SEL_8197F(x) ((x) & (~BITS_HCI_SEL_8197F))
+#define BIT_GET_HCI_SEL_8197F(x)                                               \
+	(((x) >> BIT_SHIFT_HCI_SEL_8197F) & BIT_MASK_HCI_SEL_8197F)
+#define BIT_SET_HCI_SEL_8197F(x, v)                                            \
+	(BIT_CLEAR_HCI_SEL_8197F(x) | BIT_HCI_SEL_8197F(v))
+
+#define BIT_SHIFT_PAD_HCI_SEL_8197F 2
+#define BIT_MASK_PAD_HCI_SEL_8197F 0x3
+#define BIT_PAD_HCI_SEL_8197F(x)                                               \
+	(((x) & BIT_MASK_PAD_HCI_SEL_8197F) << BIT_SHIFT_PAD_HCI_SEL_8197F)
+#define BITS_PAD_HCI_SEL_8197F                                                 \
+	(BIT_MASK_PAD_HCI_SEL_8197F << BIT_SHIFT_PAD_HCI_SEL_8197F)
+#define BIT_CLEAR_PAD_HCI_SEL_8197F(x) ((x) & (~BITS_PAD_HCI_SEL_8197F))
+#define BIT_GET_PAD_HCI_SEL_8197F(x)                                           \
+	(((x) >> BIT_SHIFT_PAD_HCI_SEL_8197F) & BIT_MASK_PAD_HCI_SEL_8197F)
+#define BIT_SET_PAD_HCI_SEL_8197F(x, v)                                        \
+	(BIT_CLEAR_PAD_HCI_SEL_8197F(x) | BIT_PAD_HCI_SEL_8197F(v))
+
+#define BIT_SHIFT_EFS_HCI_SEL_8197F 0
+#define BIT_MASK_EFS_HCI_SEL_8197F 0x3
+#define BIT_EFS_HCI_SEL_8197F(x)                                               \
+	(((x) & BIT_MASK_EFS_HCI_SEL_8197F) << BIT_SHIFT_EFS_HCI_SEL_8197F)
+#define BITS_EFS_HCI_SEL_8197F                                                 \
+	(BIT_MASK_EFS_HCI_SEL_8197F << BIT_SHIFT_EFS_HCI_SEL_8197F)
+#define BIT_CLEAR_EFS_HCI_SEL_8197F(x) ((x) & (~BITS_EFS_HCI_SEL_8197F))
+#define BIT_GET_EFS_HCI_SEL_8197F(x)                                           \
+	(((x) >> BIT_SHIFT_EFS_HCI_SEL_8197F) & BIT_MASK_EFS_HCI_SEL_8197F)
+#define BIT_SET_EFS_HCI_SEL_8197F(x, v)                                        \
+	(BIT_CLEAR_EFS_HCI_SEL_8197F(x) | BIT_EFS_HCI_SEL_8197F(v))
+
+/* 2 REG_SYS_STATUS2_8197F */
+#define BIT_SIO_ALDN_8197F BIT(19)
+#define BIT_USB_ALDN_8197F BIT(18)
+#define BIT_PCI_ALDN_8197F BIT(17)
+#define BIT_SYS_ALDN_8197F BIT(16)
+
+#define BIT_SHIFT_EPVID1_8197F 8
+#define BIT_MASK_EPVID1_8197F 0xff
+#define BIT_EPVID1_8197F(x)                                                    \
+	(((x) & BIT_MASK_EPVID1_8197F) << BIT_SHIFT_EPVID1_8197F)
+#define BITS_EPVID1_8197F (BIT_MASK_EPVID1_8197F << BIT_SHIFT_EPVID1_8197F)
+#define BIT_CLEAR_EPVID1_8197F(x) ((x) & (~BITS_EPVID1_8197F))
+#define BIT_GET_EPVID1_8197F(x)                                                \
+	(((x) >> BIT_SHIFT_EPVID1_8197F) & BIT_MASK_EPVID1_8197F)
+#define BIT_SET_EPVID1_8197F(x, v)                                             \
+	(BIT_CLEAR_EPVID1_8197F(x) | BIT_EPVID1_8197F(v))
+
+#define BIT_SHIFT_EPVID0_8197F 0
+#define BIT_MASK_EPVID0_8197F 0xff
+#define BIT_EPVID0_8197F(x)                                                    \
+	(((x) & BIT_MASK_EPVID0_8197F) << BIT_SHIFT_EPVID0_8197F)
+#define BITS_EPVID0_8197F (BIT_MASK_EPVID0_8197F << BIT_SHIFT_EPVID0_8197F)
+#define BIT_CLEAR_EPVID0_8197F(x) ((x) & (~BITS_EPVID0_8197F))
+#define BIT_GET_EPVID0_8197F(x)                                                \
+	(((x) >> BIT_SHIFT_EPVID0_8197F) & BIT_MASK_EPVID0_8197F)
+#define BIT_SET_EPVID0_8197F(x, v)                                             \
+	(BIT_CLEAR_EPVID0_8197F(x) | BIT_EPVID0_8197F(v))
+
+/* 2 REG_SYS_CFG2_8197F */
+
+#define BIT_SHIFT_HW_ID_8197F 0
+#define BIT_MASK_HW_ID_8197F 0xff
+#define BIT_HW_ID_8197F(x)                                                     \
+	(((x) & BIT_MASK_HW_ID_8197F) << BIT_SHIFT_HW_ID_8197F)
+#define BITS_HW_ID_8197F (BIT_MASK_HW_ID_8197F << BIT_SHIFT_HW_ID_8197F)
+#define BIT_CLEAR_HW_ID_8197F(x) ((x) & (~BITS_HW_ID_8197F))
+#define BIT_GET_HW_ID_8197F(x)                                                 \
+	(((x) >> BIT_SHIFT_HW_ID_8197F) & BIT_MASK_HW_ID_8197F)
+#define BIT_SET_HW_ID_8197F(x, v)                                              \
+	(BIT_CLEAR_HW_ID_8197F(x) | BIT_HW_ID_8197F(v))
+
+/* 2 REG_NOT_VALID_8197F */
+
+/* 2 REG_SYS_CFG3_8197F */
+
+/* 2 REG_SYS_CFG4_8197F */
+
+/* 2 REG_CPU_DMEM_CON_8197F */
+#define BIT_ANA_PORT_IDLE_8197F BIT(18)
+#define BIT_MAC_PORT_IDLE_8197F BIT(17)
+#define BIT_WL_PLATFORM_RST_8197F BIT(16)
+#define BIT_WL_SECURITY_CLK_8197F BIT(15)
+
+#define BIT_SHIFT_CPU_DMEM_CON_8197F 0
+#define BIT_MASK_CPU_DMEM_CON_8197F 0xff
+#define BIT_CPU_DMEM_CON_8197F(x)                                              \
+	(((x) & BIT_MASK_CPU_DMEM_CON_8197F) << BIT_SHIFT_CPU_DMEM_CON_8197F)
+#define BITS_CPU_DMEM_CON_8197F                                                \
+	(BIT_MASK_CPU_DMEM_CON_8197F << BIT_SHIFT_CPU_DMEM_CON_8197F)
+#define BIT_CLEAR_CPU_DMEM_CON_8197F(x) ((x) & (~BITS_CPU_DMEM_CON_8197F))
+#define BIT_GET_CPU_DMEM_CON_8197F(x)                                          \
+	(((x) >> BIT_SHIFT_CPU_DMEM_CON_8197F) & BIT_MASK_CPU_DMEM_CON_8197F)
+#define BIT_SET_CPU_DMEM_CON_8197F(x, v)                                       \
+	(BIT_CLEAR_CPU_DMEM_CON_8197F(x) | BIT_CPU_DMEM_CON_8197F(v))
+
+/* 2 REG_HIMR2_8197F */
+#define BIT_BCNDMAINT_P4_MSK_8197F BIT(31)
+#define BIT_BCNDMAINT_P3_MSK_8197F BIT(30)
+#define BIT_BCNDMAINT_P2_MSK_8197F BIT(29)
+#define BIT_BCNDMAINT_P1_MSK_8197F BIT(28)
+#define BIT_ATIMEND7_MSK_8197F BIT(22)
+#define BIT_ATIMEND6_MSK_8197F BIT(21)
+#define BIT_ATIMEND5_MSK_8197F BIT(20)
+#define BIT_ATIMEND4_MSK_8197F BIT(19)
+#define BIT_ATIMEND3_MSK_8197F BIT(18)
+#define BIT_ATIMEND2_MSK_8197F BIT(17)
+#define BIT_ATIMEND1_MSK_8197F BIT(16)
+#define BIT_TXBCN7OK_MSK_8197F BIT(14)
+#define BIT_TXBCN6OK_MSK_8197F BIT(13)
+#define BIT_TXBCN5OK_MSK_8197F BIT(12)
+#define BIT_TXBCN4OK_MSK_8197F BIT(11)
+#define BIT_TXBCN3OK_MSK_8197F BIT(10)
+#define BIT_TXBCN2OK_MSK_8197F BIT(9)
+#define BIT_TXBCN1OK_MSK_V1_8197F BIT(8)
+#define BIT_TXBCN7ERR_MSK_8197F BIT(6)
+#define BIT_TXBCN6ERR_MSK_8197F BIT(5)
+#define BIT_TXBCN5ERR_MSK_8197F BIT(4)
+#define BIT_TXBCN4ERR_MSK_8197F BIT(3)
+#define BIT_TXBCN3ERR_MSK_8197F BIT(2)
+#define BIT_TXBCN2ERR_MSK_8197F BIT(1)
+#define BIT_TXBCN1ERR_MSK_V1_8197F BIT(0)
+
+/* 2 REG_HISR2_8197F */
+#define BIT_BCNDMAINT_P4_8197F BIT(31)
+#define BIT_BCNDMAINT_P3_8197F BIT(30)
+#define BIT_BCNDMAINT_P2_8197F BIT(29)
+#define BIT_BCNDMAINT_P1_8197F BIT(28)
+#define BIT_ATIMEND7_8197F BIT(22)
+#define BIT_ATIMEND6_8197F BIT(21)
+#define BIT_ATIMEND5_8197F BIT(20)
+#define BIT_ATIMEND4_8197F BIT(19)
+#define BIT_ATIMEND3_8197F BIT(18)
+#define BIT_ATIMEND2_8197F BIT(17)
+#define BIT_ATIMEND1_8197F BIT(16)
+#define BIT_TXBCN7OK_8197F BIT(14)
+#define BIT_TXBCN6OK_8197F BIT(13)
+#define BIT_TXBCN5OK_8197F BIT(12)
+#define BIT_TXBCN4OK_8197F BIT(11)
+#define BIT_TXBCN3OK_8197F BIT(10)
+#define BIT_TXBCN2OK_8197F BIT(9)
+#define BIT_TXBCN1OK_8197F BIT(8)
+#define BIT_TXBCN7ERR_8197F BIT(6)
+#define BIT_TXBCN6ERR_8197F BIT(5)
+#define BIT_TXBCN5ERR_8197F BIT(4)
+#define BIT_TXBCN4ERR_8197F BIT(3)
+#define BIT_TXBCN3ERR_8197F BIT(2)
+#define BIT_TXBCN2ERR_8197F BIT(1)
+#define BIT_TXBCN1ERR_8197F BIT(0)
+
+/* 2 REG_HIMR3_8197F */
+#define BIT_SETH2CDOK_MASK_8197F BIT(16)
+#define BIT_H2C_CMD_FULL_MASK_8197F BIT(15)
+#define BIT_PWR_INT_127_MASK_8197F BIT(14)
+#define BIT_TXSHORTCUT_TXDESUPDATEOK_MASK_8197F BIT(13)
+#define BIT_TXSHORTCUT_BKUPDATEOK_MASK_8197F BIT(12)
+#define BIT_TXSHORTCUT_BEUPDATEOK_MASK_8197F BIT(11)
+#define BIT_TXSHORTCUT_VIUPDATEOK_MAS_8197F BIT(10)
+#define BIT_TXSHORTCUT_VOUPDATEOK_MASK_8197F BIT(9)
+#define BIT_PWR_INT_127_MASK_V1_8197F BIT(8)
+#define BIT_PWR_INT_126TO96_MASK_8197F BIT(7)
+#define BIT_PWR_INT_95TO64_MASK_8197F BIT(6)
+#define BIT_PWR_INT_63TO32_MASK_8197F BIT(5)
+#define BIT_PWR_INT_31TO0_MASK_8197F BIT(4)
+#define BIT_DDMA0_LP_INT_MSK_8197F BIT(1)
+#define BIT_DDMA0_HP_INT_MSK_8197F BIT(0)
+
+/* 2 REG_HISR3_8197F */
+#define BIT_SETH2CDOK_8197F BIT(16)
+#define BIT_H2C_CMD_FULL_8197F BIT(15)
+#define BIT_PWR_INT_127_8197F BIT(14)
+#define BIT_TXSHORTCUT_TXDESUPDATEOK_8197F BIT(13)
+#define BIT_TXSHORTCUT_BKUPDATEOK_8197F BIT(12)
+#define BIT_TXSHORTCUT_BEUPDATEOK_8197F BIT(11)
+#define BIT_TXSHORTCUT_VIUPDATEOK_8197F BIT(10)
+#define BIT_TXSHORTCUT_VOUPDATEOK_8197F BIT(9)
+#define BIT_PWR_INT_127_V1_8197F BIT(8)
+#define BIT_PWR_INT_126TO96_8197F BIT(7)
+#define BIT_PWR_INT_95TO64_8197F BIT(6)
+#define BIT_PWR_INT_63TO32_8197F BIT(5)
+#define BIT_PWR_INT_31TO0_8197F BIT(4)
+#define BIT_DDMA0_LP_INT_8197F BIT(1)
+#define BIT_DDMA0_HP_INT_8197F BIT(0)
+
+/* 2 REG_SW_MDIO_8197F */
+
+/* 2 REG_SW_FLUSH_8197F */
+#define BIT_FLUSH_HOLDN_EN_8197F BIT(25)
+#define BIT_FLUSH_WR_EN_8197F BIT(24)
+#define BIT_SW_FLASH_CONTROL_8197F BIT(23)
+#define BIT_SW_FLASH_WEN_E_8197F BIT(19)
+#define BIT_SW_FLASH_HOLDN_E_8197F BIT(18)
+#define BIT_SW_FLASH_SO_E_8197F BIT(17)
+#define BIT_SW_FLASH_SI_E_8197F BIT(16)
+#define BIT_SW_FLASH_SK_O_8197F BIT(13)
+#define BIT_SW_FLASH_CEN_O_8197F BIT(12)
+#define BIT_SW_FLASH_WEN_O_8197F BIT(11)
+#define BIT_SW_FLASH_HOLDN_O_8197F BIT(10)
+#define BIT_SW_FLASH_SO_O_8197F BIT(9)
+#define BIT_SW_FLASH_SI_O_8197F BIT(8)
+#define BIT_SW_FLASH_WEN_I_8197F BIT(3)
+#define BIT_SW_FLASH_HOLDN_I_8197F BIT(2)
+#define BIT_SW_FLASH_SO_I_8197F BIT(1)
+#define BIT_SW_FLASH_SI_I_8197F BIT(0)
+
+/* 2 REG_DBG_GPIO_BMUX_8197F */
+
+#define BIT_SHIFT_DBG_GPIO_BMUX_7_8197F 21
+#define BIT_MASK_DBG_GPIO_BMUX_7_8197F 0x7
+#define BIT_DBG_GPIO_BMUX_7_8197F(x)                                           \
+	(((x) & BIT_MASK_DBG_GPIO_BMUX_7_8197F)                                \
+	 << BIT_SHIFT_DBG_GPIO_BMUX_7_8197F)
+#define BITS_DBG_GPIO_BMUX_7_8197F                                             \
+	(BIT_MASK_DBG_GPIO_BMUX_7_8197F << BIT_SHIFT_DBG_GPIO_BMUX_7_8197F)
+#define BIT_CLEAR_DBG_GPIO_BMUX_7_8197F(x) ((x) & (~BITS_DBG_GPIO_BMUX_7_8197F))
+#define BIT_GET_DBG_GPIO_BMUX_7_8197F(x)                                       \
+	(((x) >> BIT_SHIFT_DBG_GPIO_BMUX_7_8197F) &                            \
+	 BIT_MASK_DBG_GPIO_BMUX_7_8197F)
+#define BIT_SET_DBG_GPIO_BMUX_7_8197F(x, v)                                    \
+	(BIT_CLEAR_DBG_GPIO_BMUX_7_8197F(x) | BIT_DBG_GPIO_BMUX_7_8197F(v))
+
+#define BIT_SHIFT_DBG_GPIO_BMUX_6_8197F 18
+#define BIT_MASK_DBG_GPIO_BMUX_6_8197F 0x7
+#define BIT_DBG_GPIO_BMUX_6_8197F(x)                                           \
+	(((x) & BIT_MASK_DBG_GPIO_BMUX_6_8197F)                                \
+	 << BIT_SHIFT_DBG_GPIO_BMUX_6_8197F)
+#define BITS_DBG_GPIO_BMUX_6_8197F                                             \
+	(BIT_MASK_DBG_GPIO_BMUX_6_8197F << BIT_SHIFT_DBG_GPIO_BMUX_6_8197F)
+#define BIT_CLEAR_DBG_GPIO_BMUX_6_8197F(x) ((x) & (~BITS_DBG_GPIO_BMUX_6_8197F))
+#define BIT_GET_DBG_GPIO_BMUX_6_8197F(x)                                       \
+	(((x) >> BIT_SHIFT_DBG_GPIO_BMUX_6_8197F) &                            \
+	 BIT_MASK_DBG_GPIO_BMUX_6_8197F)
+#define BIT_SET_DBG_GPIO_BMUX_6_8197F(x, v)                                    \
+	(BIT_CLEAR_DBG_GPIO_BMUX_6_8197F(x) | BIT_DBG_GPIO_BMUX_6_8197F(v))
+
+#define BIT_SHIFT_DBG_GPIO_BMUX_5_8197F 15
+#define BIT_MASK_DBG_GPIO_BMUX_5_8197F 0x7
+#define BIT_DBG_GPIO_BMUX_5_8197F(x)                                           \
+	(((x) & BIT_MASK_DBG_GPIO_BMUX_5_8197F)                                \
+	 << BIT_SHIFT_DBG_GPIO_BMUX_5_8197F)
+#define BITS_DBG_GPIO_BMUX_5_8197F                                             \
+	(BIT_MASK_DBG_GPIO_BMUX_5_8197F << BIT_SHIFT_DBG_GPIO_BMUX_5_8197F)
+#define BIT_CLEAR_DBG_GPIO_BMUX_5_8197F(x) ((x) & (~BITS_DBG_GPIO_BMUX_5_8197F))
+#define BIT_GET_DBG_GPIO_BMUX_5_8197F(x)                                       \
+	(((x) >> BIT_SHIFT_DBG_GPIO_BMUX_5_8197F) &                            \
+	 BIT_MASK_DBG_GPIO_BMUX_5_8197F)
+#define BIT_SET_DBG_GPIO_BMUX_5_8197F(x, v)                                    \
+	(BIT_CLEAR_DBG_GPIO_BMUX_5_8197F(x) | BIT_DBG_GPIO_BMUX_5_8197F(v))
+
+#define BIT_SHIFT_DBG_GPIO_BMUX_4_8197F 12
+#define BIT_MASK_DBG_GPIO_BMUX_4_8197F 0x7
+#define BIT_DBG_GPIO_BMUX_4_8197F(x)                                           \
+	(((x) & BIT_MASK_DBG_GPIO_BMUX_4_8197F)                                \
+	 << BIT_SHIFT_DBG_GPIO_BMUX_4_8197F)
+#define BITS_DBG_GPIO_BMUX_4_8197F                                             \
+	(BIT_MASK_DBG_GPIO_BMUX_4_8197F << BIT_SHIFT_DBG_GPIO_BMUX_4_8197F)
+#define BIT_CLEAR_DBG_GPIO_BMUX_4_8197F(x) ((x) & (~BITS_DBG_GPIO_BMUX_4_8197F))
+#define BIT_GET_DBG_GPIO_BMUX_4_8197F(x)                                       \
+	(((x) >> BIT_SHIFT_DBG_GPIO_BMUX_4_8197F) &                            \
+	 BIT_MASK_DBG_GPIO_BMUX_4_8197F)
+#define BIT_SET_DBG_GPIO_BMUX_4_8197F(x, v)                                    \
+	(BIT_CLEAR_DBG_GPIO_BMUX_4_8197F(x) | BIT_DBG_GPIO_BMUX_4_8197F(v))
+
+#define BIT_SHIFT_DBG_GPIO_BMUX_3_8197F 9
+#define BIT_MASK_DBG_GPIO_BMUX_3_8197F 0x7
+#define BIT_DBG_GPIO_BMUX_3_8197F(x)                                           \
+	(((x) & BIT_MASK_DBG_GPIO_BMUX_3_8197F)                                \
+	 << BIT_SHIFT_DBG_GPIO_BMUX_3_8197F)
+#define BITS_DBG_GPIO_BMUX_3_8197F                                             \
+	(BIT_MASK_DBG_GPIO_BMUX_3_8197F << BIT_SHIFT_DBG_GPIO_BMUX_3_8197F)
+#define BIT_CLEAR_DBG_GPIO_BMUX_3_8197F(x) ((x) & (~BITS_DBG_GPIO_BMUX_3_8197F))
+#define BIT_GET_DBG_GPIO_BMUX_3_8197F(x)                                       \
+	(((x) >> BIT_SHIFT_DBG_GPIO_BMUX_3_8197F) &                            \
+	 BIT_MASK_DBG_GPIO_BMUX_3_8197F)
+#define BIT_SET_DBG_GPIO_BMUX_3_8197F(x, v)                                    \
+	(BIT_CLEAR_DBG_GPIO_BMUX_3_8197F(x) | BIT_DBG_GPIO_BMUX_3_8197F(v))
+
+#define BIT_SHIFT_DBG_GPIO_BMUX_2_8197F 6
+#define BIT_MASK_DBG_GPIO_BMUX_2_8197F 0x7
+#define BIT_DBG_GPIO_BMUX_2_8197F(x)                                           \
+	(((x) & BIT_MASK_DBG_GPIO_BMUX_2_8197F)                                \
+	 << BIT_SHIFT_DBG_GPIO_BMUX_2_8197F)
+#define BITS_DBG_GPIO_BMUX_2_8197F                                             \
+	(BIT_MASK_DBG_GPIO_BMUX_2_8197F << BIT_SHIFT_DBG_GPIO_BMUX_2_8197F)
+#define BIT_CLEAR_DBG_GPIO_BMUX_2_8197F(x) ((x) & (~BITS_DBG_GPIO_BMUX_2_8197F))
+#define BIT_GET_DBG_GPIO_BMUX_2_8197F(x)                                       \
+	(((x) >> BIT_SHIFT_DBG_GPIO_BMUX_2_8197F) &                            \
+	 BIT_MASK_DBG_GPIO_BMUX_2_8197F)
+#define BIT_SET_DBG_GPIO_BMUX_2_8197F(x, v)                                    \
+	(BIT_CLEAR_DBG_GPIO_BMUX_2_8197F(x) | BIT_DBG_GPIO_BMUX_2_8197F(v))
+
+#define BIT_SHIFT_DBG_GPIO_BMUX_1_8197F 3
+#define BIT_MASK_DBG_GPIO_BMUX_1_8197F 0x7
+#define BIT_DBG_GPIO_BMUX_1_8197F(x)                                           \
+	(((x) & BIT_MASK_DBG_GPIO_BMUX_1_8197F)                                \
+	 << BIT_SHIFT_DBG_GPIO_BMUX_1_8197F)
+#define BITS_DBG_GPIO_BMUX_1_8197F                                             \
+	(BIT_MASK_DBG_GPIO_BMUX_1_8197F << BIT_SHIFT_DBG_GPIO_BMUX_1_8197F)
+#define BIT_CLEAR_DBG_GPIO_BMUX_1_8197F(x) ((x) & (~BITS_DBG_GPIO_BMUX_1_8197F))
+#define BIT_GET_DBG_GPIO_BMUX_1_8197F(x)                                       \
+	(((x) >> BIT_SHIFT_DBG_GPIO_BMUX_1_8197F) &                            \
+	 BIT_MASK_DBG_GPIO_BMUX_1_8197F)
+#define BIT_SET_DBG_GPIO_BMUX_1_8197F(x, v)                                    \
+	(BIT_CLEAR_DBG_GPIO_BMUX_1_8197F(x) | BIT_DBG_GPIO_BMUX_1_8197F(v))
+
+#define BIT_SHIFT_DBG_GPIO_BMUX_0_8197F 0
+#define BIT_MASK_DBG_GPIO_BMUX_0_8197F 0x7
+#define BIT_DBG_GPIO_BMUX_0_8197F(x)                                           \
+	(((x) & BIT_MASK_DBG_GPIO_BMUX_0_8197F)                                \
+	 << BIT_SHIFT_DBG_GPIO_BMUX_0_8197F)
+#define BITS_DBG_GPIO_BMUX_0_8197F                                             \
+	(BIT_MASK_DBG_GPIO_BMUX_0_8197F << BIT_SHIFT_DBG_GPIO_BMUX_0_8197F)
+#define BIT_CLEAR_DBG_GPIO_BMUX_0_8197F(x) ((x) & (~BITS_DBG_GPIO_BMUX_0_8197F))
+#define BIT_GET_DBG_GPIO_BMUX_0_8197F(x)                                       \
+	(((x) >> BIT_SHIFT_DBG_GPIO_BMUX_0_8197F) &                            \
+	 BIT_MASK_DBG_GPIO_BMUX_0_8197F)
+#define BIT_SET_DBG_GPIO_BMUX_0_8197F(x, v)                                    \
+	(BIT_CLEAR_DBG_GPIO_BMUX_0_8197F(x) | BIT_DBG_GPIO_BMUX_0_8197F(v))
+
+/* 2 REG_FPGA_TAG_8197F (NO USE IN ASIC) */
+
+#define BIT_SHIFT_FPGA_TAG_8197F 0
+#define BIT_MASK_FPGA_TAG_8197F 0xffffffffL
+#define BIT_FPGA_TAG_8197F(x)                                                  \
+	(((x) & BIT_MASK_FPGA_TAG_8197F) << BIT_SHIFT_FPGA_TAG_8197F)
+#define BITS_FPGA_TAG_8197F                                                    \
+	(BIT_MASK_FPGA_TAG_8197F << BIT_SHIFT_FPGA_TAG_8197F)
+#define BIT_CLEAR_FPGA_TAG_8197F(x) ((x) & (~BITS_FPGA_TAG_8197F))
+#define BIT_GET_FPGA_TAG_8197F(x)                                              \
+	(((x) >> BIT_SHIFT_FPGA_TAG_8197F) & BIT_MASK_FPGA_TAG_8197F)
+#define BIT_SET_FPGA_TAG_8197F(x, v)                                           \
+	(BIT_CLEAR_FPGA_TAG_8197F(x) | BIT_FPGA_TAG_8197F(v))
+
+/* 2 REG_WL_DSS_CTRL0_8197F */
+#define BIT_WL_DSS_RSTN_8197F BIT(27)
+#define BIT_WL_DSS_EN_CLK_8197F BIT(26)
+#define BIT_WL_DSS_SPEED_EN_8197F BIT(25)
+
+#define BIT_SHIFT_WL_DSS_COUNT_OUT_8197F 0
+#define BIT_MASK_WL_DSS_COUNT_OUT_8197F 0xfffff
+#define BIT_WL_DSS_COUNT_OUT_8197F(x)                                          \
+	(((x) & BIT_MASK_WL_DSS_COUNT_OUT_8197F)                               \
+	 << BIT_SHIFT_WL_DSS_COUNT_OUT_8197F)
+#define BITS_WL_DSS_COUNT_OUT_8197F                                            \
+	(BIT_MASK_WL_DSS_COUNT_OUT_8197F << BIT_SHIFT_WL_DSS_COUNT_OUT_8197F)
+#define BIT_CLEAR_WL_DSS_COUNT_OUT_8197F(x)                                    \
+	((x) & (~BITS_WL_DSS_COUNT_OUT_8197F))
+#define BIT_GET_WL_DSS_COUNT_OUT_8197F(x)                                      \
+	(((x) >> BIT_SHIFT_WL_DSS_COUNT_OUT_8197F) &                           \
+	 BIT_MASK_WL_DSS_COUNT_OUT_8197F)
+#define BIT_SET_WL_DSS_COUNT_OUT_8197F(x, v)                                   \
+	(BIT_CLEAR_WL_DSS_COUNT_OUT_8197F(x) | BIT_WL_DSS_COUNT_OUT_8197F(v))
+
+/* 2 REG_WL_DSS_CTRL1_8197F */
+#define BIT_WL_DSS_RSTN_8197F BIT(27)
+#define BIT_WL_DSS_EN_CLK_8197F BIT(26)
+#define BIT_WL_DSS_SPEED_EN_8197F BIT(25)
+#define BIT_WL_DSS_WIRE_SEL_8197F BIT(24)
+
+#define BIT_SHIFT_WL_DSS_RO_SEL_8197F 20
+#define BIT_MASK_WL_DSS_RO_SEL_8197F 0x7
+#define BIT_WL_DSS_RO_SEL_8197F(x)                                             \
+	(((x) & BIT_MASK_WL_DSS_RO_SEL_8197F) << BIT_SHIFT_WL_DSS_RO_SEL_8197F)
+#define BITS_WL_DSS_RO_SEL_8197F                                               \
+	(BIT_MASK_WL_DSS_RO_SEL_8197F << BIT_SHIFT_WL_DSS_RO_SEL_8197F)
+#define BIT_CLEAR_WL_DSS_RO_SEL_8197F(x) ((x) & (~BITS_WL_DSS_RO_SEL_8197F))
+#define BIT_GET_WL_DSS_RO_SEL_8197F(x)                                         \
+	(((x) >> BIT_SHIFT_WL_DSS_RO_SEL_8197F) & BIT_MASK_WL_DSS_RO_SEL_8197F)
+#define BIT_SET_WL_DSS_RO_SEL_8197F(x, v)                                      \
+	(BIT_CLEAR_WL_DSS_RO_SEL_8197F(x) | BIT_WL_DSS_RO_SEL_8197F(v))
+
+#define BIT_SHIFT_WL_DSS_DATA_IN_8197F 0
+#define BIT_MASK_WL_DSS_DATA_IN_8197F 0xfffff
+#define BIT_WL_DSS_DATA_IN_8197F(x)                                            \
+	(((x) & BIT_MASK_WL_DSS_DATA_IN_8197F)                                 \
+	 << BIT_SHIFT_WL_DSS_DATA_IN_8197F)
+#define BITS_WL_DSS_DATA_IN_8197F                                              \
+	(BIT_MASK_WL_DSS_DATA_IN_8197F << BIT_SHIFT_WL_DSS_DATA_IN_8197F)
+#define BIT_CLEAR_WL_DSS_DATA_IN_8197F(x) ((x) & (~BITS_WL_DSS_DATA_IN_8197F))
+#define BIT_GET_WL_DSS_DATA_IN_8197F(x)                                        \
+	(((x) >> BIT_SHIFT_WL_DSS_DATA_IN_8197F) &                             \
+	 BIT_MASK_WL_DSS_DATA_IN_8197F)
+#define BIT_SET_WL_DSS_DATA_IN_8197F(x, v)                                     \
+	(BIT_CLEAR_WL_DSS_DATA_IN_8197F(x) | BIT_WL_DSS_DATA_IN_8197F(v))
+
+/* 2 REG_WL_DSS_STATUS1_8197F */
+#define BIT_WL_DSS_READY_8197F BIT(21)
+#define BIT_WL_DSS_WSORT_GO_8197F BIT(20)
+
+#define BIT_SHIFT_WL_DSS_COUNT_OUT_8197F 0
+#define BIT_MASK_WL_DSS_COUNT_OUT_8197F 0xfffff
+#define BIT_WL_DSS_COUNT_OUT_8197F(x)                                          \
+	(((x) & BIT_MASK_WL_DSS_COUNT_OUT_8197F)                               \
+	 << BIT_SHIFT_WL_DSS_COUNT_OUT_8197F)
+#define BITS_WL_DSS_COUNT_OUT_8197F                                            \
+	(BIT_MASK_WL_DSS_COUNT_OUT_8197F << BIT_SHIFT_WL_DSS_COUNT_OUT_8197F)
+#define BIT_CLEAR_WL_DSS_COUNT_OUT_8197F(x)                                    \
+	((x) & (~BITS_WL_DSS_COUNT_OUT_8197F))
+#define BIT_GET_WL_DSS_COUNT_OUT_8197F(x)                                      \
+	(((x) >> BIT_SHIFT_WL_DSS_COUNT_OUT_8197F) &                           \
+	 BIT_MASK_WL_DSS_COUNT_OUT_8197F)
+#define BIT_SET_WL_DSS_COUNT_OUT_8197F(x, v)                                   \
+	(BIT_CLEAR_WL_DSS_COUNT_OUT_8197F(x) | BIT_WL_DSS_COUNT_OUT_8197F(v))
+
+/* 2 REG_FW_DBG0_8197F */
+
+#define BIT_SHIFT_FW_DBG0_8197F 0
+#define BIT_MASK_FW_DBG0_8197F 0xffffffffL
+#define BIT_FW_DBG0_8197F(x)                                                   \
+	(((x) & BIT_MASK_FW_DBG0_8197F) << BIT_SHIFT_FW_DBG0_8197F)
+#define BITS_FW_DBG0_8197F (BIT_MASK_FW_DBG0_8197F << BIT_SHIFT_FW_DBG0_8197F)
+#define BIT_CLEAR_FW_DBG0_8197F(x) ((x) & (~BITS_FW_DBG0_8197F))
+#define BIT_GET_FW_DBG0_8197F(x)                                               \
+	(((x) >> BIT_SHIFT_FW_DBG0_8197F) & BIT_MASK_FW_DBG0_8197F)
+#define BIT_SET_FW_DBG0_8197F(x, v)                                            \
+	(BIT_CLEAR_FW_DBG0_8197F(x) | BIT_FW_DBG0_8197F(v))
+
+/* 2 REG_FW_DBG1_8197F */
+
+#define BIT_SHIFT_FW_DBG1_8197F 0
+#define BIT_MASK_FW_DBG1_8197F 0xffffffffL
+#define BIT_FW_DBG1_8197F(x)                                                   \
+	(((x) & BIT_MASK_FW_DBG1_8197F) << BIT_SHIFT_FW_DBG1_8197F)
+#define BITS_FW_DBG1_8197F (BIT_MASK_FW_DBG1_8197F << BIT_SHIFT_FW_DBG1_8197F)
+#define BIT_CLEAR_FW_DBG1_8197F(x) ((x) & (~BITS_FW_DBG1_8197F))
+#define BIT_GET_FW_DBG1_8197F(x)                                               \
+	(((x) >> BIT_SHIFT_FW_DBG1_8197F) & BIT_MASK_FW_DBG1_8197F)
+#define BIT_SET_FW_DBG1_8197F(x, v)                                            \
+	(BIT_CLEAR_FW_DBG1_8197F(x) | BIT_FW_DBG1_8197F(v))
+
+/* 2 REG_FW_DBG2_8197F */
+
+#define BIT_SHIFT_FW_DBG2_8197F 0
+#define BIT_MASK_FW_DBG2_8197F 0xffffffffL
+#define BIT_FW_DBG2_8197F(x)                                                   \
+	(((x) & BIT_MASK_FW_DBG2_8197F) << BIT_SHIFT_FW_DBG2_8197F)
+#define BITS_FW_DBG2_8197F (BIT_MASK_FW_DBG2_8197F << BIT_SHIFT_FW_DBG2_8197F)
+#define BIT_CLEAR_FW_DBG2_8197F(x) ((x) & (~BITS_FW_DBG2_8197F))
+#define BIT_GET_FW_DBG2_8197F(x)                                               \
+	(((x) >> BIT_SHIFT_FW_DBG2_8197F) & BIT_MASK_FW_DBG2_8197F)
+#define BIT_SET_FW_DBG2_8197F(x, v)                                            \
+	(BIT_CLEAR_FW_DBG2_8197F(x) | BIT_FW_DBG2_8197F(v))
+
+/* 2 REG_FW_DBG3_8197F */
+
+#define BIT_SHIFT_FW_DBG3_8197F 0
+#define BIT_MASK_FW_DBG3_8197F 0xffffffffL
+#define BIT_FW_DBG3_8197F(x)                                                   \
+	(((x) & BIT_MASK_FW_DBG3_8197F) << BIT_SHIFT_FW_DBG3_8197F)
+#define BITS_FW_DBG3_8197F (BIT_MASK_FW_DBG3_8197F << BIT_SHIFT_FW_DBG3_8197F)
+#define BIT_CLEAR_FW_DBG3_8197F(x) ((x) & (~BITS_FW_DBG3_8197F))
+#define BIT_GET_FW_DBG3_8197F(x)                                               \
+	(((x) >> BIT_SHIFT_FW_DBG3_8197F) & BIT_MASK_FW_DBG3_8197F)
+#define BIT_SET_FW_DBG3_8197F(x, v)                                            \
+	(BIT_CLEAR_FW_DBG3_8197F(x) | BIT_FW_DBG3_8197F(v))
+
+/* 2 REG_FW_DBG4_8197F */
+
+#define BIT_SHIFT_FW_DBG4_8197F 0
+#define BIT_MASK_FW_DBG4_8197F 0xffffffffL
+#define BIT_FW_DBG4_8197F(x)                                                   \
+	(((x) & BIT_MASK_FW_DBG4_8197F) << BIT_SHIFT_FW_DBG4_8197F)
+#define BITS_FW_DBG4_8197F (BIT_MASK_FW_DBG4_8197F << BIT_SHIFT_FW_DBG4_8197F)
+#define BIT_CLEAR_FW_DBG4_8197F(x) ((x) & (~BITS_FW_DBG4_8197F))
+#define BIT_GET_FW_DBG4_8197F(x)                                               \
+	(((x) >> BIT_SHIFT_FW_DBG4_8197F) & BIT_MASK_FW_DBG4_8197F)
+#define BIT_SET_FW_DBG4_8197F(x, v)                                            \
+	(BIT_CLEAR_FW_DBG4_8197F(x) | BIT_FW_DBG4_8197F(v))
+
+/* 2 REG_FW_DBG5_8197F */
+
+#define BIT_SHIFT_FW_DBG5_8197F 0
+#define BIT_MASK_FW_DBG5_8197F 0xffffffffL
+#define BIT_FW_DBG5_8197F(x)                                                   \
+	(((x) & BIT_MASK_FW_DBG5_8197F) << BIT_SHIFT_FW_DBG5_8197F)
+#define BITS_FW_DBG5_8197F (BIT_MASK_FW_DBG5_8197F << BIT_SHIFT_FW_DBG5_8197F)
+#define BIT_CLEAR_FW_DBG5_8197F(x) ((x) & (~BITS_FW_DBG5_8197F))
+#define BIT_GET_FW_DBG5_8197F(x)                                               \
+	(((x) >> BIT_SHIFT_FW_DBG5_8197F) & BIT_MASK_FW_DBG5_8197F)
+#define BIT_SET_FW_DBG5_8197F(x, v)                                            \
+	(BIT_CLEAR_FW_DBG5_8197F(x) | BIT_FW_DBG5_8197F(v))
+
+/* 2 REG_FW_DBG6_8197F */
+
+#define BIT_SHIFT_FW_DBG6_8197F 0
+#define BIT_MASK_FW_DBG6_8197F 0xffffffffL
+#define BIT_FW_DBG6_8197F(x)                                                   \
+	(((x) & BIT_MASK_FW_DBG6_8197F) << BIT_SHIFT_FW_DBG6_8197F)
+#define BITS_FW_DBG6_8197F (BIT_MASK_FW_DBG6_8197F << BIT_SHIFT_FW_DBG6_8197F)
+#define BIT_CLEAR_FW_DBG6_8197F(x) ((x) & (~BITS_FW_DBG6_8197F))
+#define BIT_GET_FW_DBG6_8197F(x)                                               \
+	(((x) >> BIT_SHIFT_FW_DBG6_8197F) & BIT_MASK_FW_DBG6_8197F)
+#define BIT_SET_FW_DBG6_8197F(x, v)                                            \
+	(BIT_CLEAR_FW_DBG6_8197F(x) | BIT_FW_DBG6_8197F(v))
+
+/* 2 REG_FW_DBG7_8197F */
+
+#define BIT_SHIFT_FW_DBG7_8197F 0
+#define BIT_MASK_FW_DBG7_8197F 0xffffffffL
+#define BIT_FW_DBG7_8197F(x)                                                   \
+	(((x) & BIT_MASK_FW_DBG7_8197F) << BIT_SHIFT_FW_DBG7_8197F)
+#define BITS_FW_DBG7_8197F (BIT_MASK_FW_DBG7_8197F << BIT_SHIFT_FW_DBG7_8197F)
+#define BIT_CLEAR_FW_DBG7_8197F(x) ((x) & (~BITS_FW_DBG7_8197F))
+#define BIT_GET_FW_DBG7_8197F(x)                                               \
+	(((x) >> BIT_SHIFT_FW_DBG7_8197F) & BIT_MASK_FW_DBG7_8197F)
+#define BIT_SET_FW_DBG7_8197F(x, v)                                            \
+	(BIT_CLEAR_FW_DBG7_8197F(x) | BIT_FW_DBG7_8197F(v))
+
+/* 2 REG_NOT_VALID_8197F */
+
+/* 2 REG_CR_8197F (ENABLE FUNCTION REGISTER) */
+#define BIT_MACIO_TIMEOUT_EN_8197F BIT(29)
+
+#define BIT_SHIFT_LBMODE_8197F 24
+#define BIT_MASK_LBMODE_8197F 0x1f
+#define BIT_LBMODE_8197F(x)                                                    \
+	(((x) & BIT_MASK_LBMODE_8197F) << BIT_SHIFT_LBMODE_8197F)
+#define BITS_LBMODE_8197F (BIT_MASK_LBMODE_8197F << BIT_SHIFT_LBMODE_8197F)
+#define BIT_CLEAR_LBMODE_8197F(x) ((x) & (~BITS_LBMODE_8197F))
+#define BIT_GET_LBMODE_8197F(x)                                                \
+	(((x) >> BIT_SHIFT_LBMODE_8197F) & BIT_MASK_LBMODE_8197F)
+#define BIT_SET_LBMODE_8197F(x, v)                                             \
+	(BIT_CLEAR_LBMODE_8197F(x) | BIT_LBMODE_8197F(v))
+
+#define BIT_SHIFT_NETYPE1_8197F 18
+#define BIT_MASK_NETYPE1_8197F 0x3
+#define BIT_NETYPE1_8197F(x)                                                   \
+	(((x) & BIT_MASK_NETYPE1_8197F) << BIT_SHIFT_NETYPE1_8197F)
+#define BITS_NETYPE1_8197F (BIT_MASK_NETYPE1_8197F << BIT_SHIFT_NETYPE1_8197F)
+#define BIT_CLEAR_NETYPE1_8197F(x) ((x) & (~BITS_NETYPE1_8197F))
+#define BIT_GET_NETYPE1_8197F(x)                                               \
+	(((x) >> BIT_SHIFT_NETYPE1_8197F) & BIT_MASK_NETYPE1_8197F)
+#define BIT_SET_NETYPE1_8197F(x, v)                                            \
+	(BIT_CLEAR_NETYPE1_8197F(x) | BIT_NETYPE1_8197F(v))
+
+#define BIT_SHIFT_NETYPE0_8197F 16
+#define BIT_MASK_NETYPE0_8197F 0x3
+#define BIT_NETYPE0_8197F(x)                                                   \
+	(((x) & BIT_MASK_NETYPE0_8197F) << BIT_SHIFT_NETYPE0_8197F)
+#define BITS_NETYPE0_8197F (BIT_MASK_NETYPE0_8197F << BIT_SHIFT_NETYPE0_8197F)
+#define BIT_CLEAR_NETYPE0_8197F(x) ((x) & (~BITS_NETYPE0_8197F))
+#define BIT_GET_NETYPE0_8197F(x)                                               \
+	(((x) >> BIT_SHIFT_NETYPE0_8197F) & BIT_MASK_NETYPE0_8197F)
+#define BIT_SET_NETYPE0_8197F(x, v)                                            \
+	(BIT_CLEAR_NETYPE0_8197F(x) | BIT_NETYPE0_8197F(v))
+
+#define BIT_STAT_FUNC_RST_8197F BIT(13)
+#define BIT_I2C_MAILBOX_EN_8197F BIT(12)
+#define BIT_SHCUT_EN_8197F BIT(11)
+#define BIT_32K_CAL_TMR_EN_8197F BIT(10)
+#define BIT_MAC_SEC_EN_8197F BIT(9)
+#define BIT_ENSWBCN_8197F BIT(8)
+#define BIT_MACRXEN_8197F BIT(7)
+#define BIT_MACTXEN_8197F BIT(6)
+#define BIT_SCHEDULE_EN_8197F BIT(5)
+#define BIT_PROTOCOL_EN_8197F BIT(4)
+#define BIT_RXDMA_EN_8197F BIT(3)
+#define BIT_TXDMA_EN_8197F BIT(2)
+#define BIT_HCI_RXDMA_EN_8197F BIT(1)
+#define BIT_HCI_TXDMA_EN_8197F BIT(0)
+
+/* 2 REG_TSF_CLK_STATE_8197F */
+#define BIT_TSF_CLK_STABLE_8197F BIT(15)
+
+/* 2 REG_TXDMA_PQ_MAP_8197F */
+
+#define BIT_SHIFT_TXDMA_HIQ_MAP_8197F 14
+#define BIT_MASK_TXDMA_HIQ_MAP_8197F 0x3
+#define BIT_TXDMA_HIQ_MAP_8197F(x)                                             \
+	(((x) & BIT_MASK_TXDMA_HIQ_MAP_8197F) << BIT_SHIFT_TXDMA_HIQ_MAP_8197F)
+#define BITS_TXDMA_HIQ_MAP_8197F                                               \
+	(BIT_MASK_TXDMA_HIQ_MAP_8197F << BIT_SHIFT_TXDMA_HIQ_MAP_8197F)
+#define BIT_CLEAR_TXDMA_HIQ_MAP_8197F(x) ((x) & (~BITS_TXDMA_HIQ_MAP_8197F))
+#define BIT_GET_TXDMA_HIQ_MAP_8197F(x)                                         \
+	(((x) >> BIT_SHIFT_TXDMA_HIQ_MAP_8197F) & BIT_MASK_TXDMA_HIQ_MAP_8197F)
+#define BIT_SET_TXDMA_HIQ_MAP_8197F(x, v)                                      \
+	(BIT_CLEAR_TXDMA_HIQ_MAP_8197F(x) | BIT_TXDMA_HIQ_MAP_8197F(v))
+
+#define BIT_SHIFT_TXDMA_MGQ_MAP_8197F 12
+#define BIT_MASK_TXDMA_MGQ_MAP_8197F 0x3
+#define BIT_TXDMA_MGQ_MAP_8197F(x)                                             \
+	(((x) & BIT_MASK_TXDMA_MGQ_MAP_8197F) << BIT_SHIFT_TXDMA_MGQ_MAP_8197F)
+#define BITS_TXDMA_MGQ_MAP_8197F                                               \
+	(BIT_MASK_TXDMA_MGQ_MAP_8197F << BIT_SHIFT_TXDMA_MGQ_MAP_8197F)
+#define BIT_CLEAR_TXDMA_MGQ_MAP_8197F(x) ((x) & (~BITS_TXDMA_MGQ_MAP_8197F))
+#define BIT_GET_TXDMA_MGQ_MAP_8197F(x)                                         \
+	(((x) >> BIT_SHIFT_TXDMA_MGQ_MAP_8197F) & BIT_MASK_TXDMA_MGQ_MAP_8197F)
+#define BIT_SET_TXDMA_MGQ_MAP_8197F(x, v)                                      \
+	(BIT_CLEAR_TXDMA_MGQ_MAP_8197F(x) | BIT_TXDMA_MGQ_MAP_8197F(v))
+
+#define BIT_SHIFT_TXDMA_BKQ_MAP_8197F 10
+#define BIT_MASK_TXDMA_BKQ_MAP_8197F 0x3
+#define BIT_TXDMA_BKQ_MAP_8197F(x)                                             \
+	(((x) & BIT_MASK_TXDMA_BKQ_MAP_8197F) << BIT_SHIFT_TXDMA_BKQ_MAP_8197F)
+#define BITS_TXDMA_BKQ_MAP_8197F                                               \
+	(BIT_MASK_TXDMA_BKQ_MAP_8197F << BIT_SHIFT_TXDMA_BKQ_MAP_8197F)
+#define BIT_CLEAR_TXDMA_BKQ_MAP_8197F(x) ((x) & (~BITS_TXDMA_BKQ_MAP_8197F))
+#define BIT_GET_TXDMA_BKQ_MAP_8197F(x)                                         \
+	(((x) >> BIT_SHIFT_TXDMA_BKQ_MAP_8197F) & BIT_MASK_TXDMA_BKQ_MAP_8197F)
+#define BIT_SET_TXDMA_BKQ_MAP_8197F(x, v)                                      \
+	(BIT_CLEAR_TXDMA_BKQ_MAP_8197F(x) | BIT_TXDMA_BKQ_MAP_8197F(v))
+
+#define BIT_SHIFT_TXDMA_BEQ_MAP_8197F 8
+#define BIT_MASK_TXDMA_BEQ_MAP_8197F 0x3
+#define BIT_TXDMA_BEQ_MAP_8197F(x)                                             \
+	(((x) & BIT_MASK_TXDMA_BEQ_MAP_8197F) << BIT_SHIFT_TXDMA_BEQ_MAP_8197F)
+#define BITS_TXDMA_BEQ_MAP_8197F                                               \
+	(BIT_MASK_TXDMA_BEQ_MAP_8197F << BIT_SHIFT_TXDMA_BEQ_MAP_8197F)
+#define BIT_CLEAR_TXDMA_BEQ_MAP_8197F(x) ((x) & (~BITS_TXDMA_BEQ_MAP_8197F))
+#define BIT_GET_TXDMA_BEQ_MAP_8197F(x)                                         \
+	(((x) >> BIT_SHIFT_TXDMA_BEQ_MAP_8197F) & BIT_MASK_TXDMA_BEQ_MAP_8197F)
+#define BIT_SET_TXDMA_BEQ_MAP_8197F(x, v)                                      \
+	(BIT_CLEAR_TXDMA_BEQ_MAP_8197F(x) | BIT_TXDMA_BEQ_MAP_8197F(v))
+
+#define BIT_SHIFT_TXDMA_VIQ_MAP_8197F 6
+#define BIT_MASK_TXDMA_VIQ_MAP_8197F 0x3
+#define BIT_TXDMA_VIQ_MAP_8197F(x)                                             \
+	(((x) & BIT_MASK_TXDMA_VIQ_MAP_8197F) << BIT_SHIFT_TXDMA_VIQ_MAP_8197F)
+#define BITS_TXDMA_VIQ_MAP_8197F                                               \
+	(BIT_MASK_TXDMA_VIQ_MAP_8197F << BIT_SHIFT_TXDMA_VIQ_MAP_8197F)
+#define BIT_CLEAR_TXDMA_VIQ_MAP_8197F(x) ((x) & (~BITS_TXDMA_VIQ_MAP_8197F))
+#define BIT_GET_TXDMA_VIQ_MAP_8197F(x)                                         \
+	(((x) >> BIT_SHIFT_TXDMA_VIQ_MAP_8197F) & BIT_MASK_TXDMA_VIQ_MAP_8197F)
+#define BIT_SET_TXDMA_VIQ_MAP_8197F(x, v)                                      \
+	(BIT_CLEAR_TXDMA_VIQ_MAP_8197F(x) | BIT_TXDMA_VIQ_MAP_8197F(v))
+
+#define BIT_SHIFT_TXDMA_VOQ_MAP_8197F 4
+#define BIT_MASK_TXDMA_VOQ_MAP_8197F 0x3
+#define BIT_TXDMA_VOQ_MAP_8197F(x)                                             \
+	(((x) & BIT_MASK_TXDMA_VOQ_MAP_8197F) << BIT_SHIFT_TXDMA_VOQ_MAP_8197F)
+#define BITS_TXDMA_VOQ_MAP_8197F                                               \
+	(BIT_MASK_TXDMA_VOQ_MAP_8197F << BIT_SHIFT_TXDMA_VOQ_MAP_8197F)
+#define BIT_CLEAR_TXDMA_VOQ_MAP_8197F(x) ((x) & (~BITS_TXDMA_VOQ_MAP_8197F))
+#define BIT_GET_TXDMA_VOQ_MAP_8197F(x)                                         \
+	(((x) >> BIT_SHIFT_TXDMA_VOQ_MAP_8197F) & BIT_MASK_TXDMA_VOQ_MAP_8197F)
+#define BIT_SET_TXDMA_VOQ_MAP_8197F(x, v)                                      \
+	(BIT_CLEAR_TXDMA_VOQ_MAP_8197F(x) | BIT_TXDMA_VOQ_MAP_8197F(v))
+
+/* 2 REG_NOT_VALID_8197F */
+#define BIT_RXDMA_AGG_EN_8197F BIT(2)
+#define BIT_RXSHFT_EN_8197F BIT(1)
+#define BIT_RXDMA_ARBBW_EN_8197F BIT(0)
+
+/* 2 REG_TRXFF_BNDY_8197F */
+
+#define BIT_SHIFT_RXFFOVFL_RSV_V2_8197F 8
+#define BIT_MASK_RXFFOVFL_RSV_V2_8197F 0xf
+#define BIT_RXFFOVFL_RSV_V2_8197F(x)                                           \
+	(((x) & BIT_MASK_RXFFOVFL_RSV_V2_8197F)                                \
+	 << BIT_SHIFT_RXFFOVFL_RSV_V2_8197F)
+#define BITS_RXFFOVFL_RSV_V2_8197F                                             \
+	(BIT_MASK_RXFFOVFL_RSV_V2_8197F << BIT_SHIFT_RXFFOVFL_RSV_V2_8197F)
+#define BIT_CLEAR_RXFFOVFL_RSV_V2_8197F(x) ((x) & (~BITS_RXFFOVFL_RSV_V2_8197F))
+#define BIT_GET_RXFFOVFL_RSV_V2_8197F(x)                                       \
+	(((x) >> BIT_SHIFT_RXFFOVFL_RSV_V2_8197F) &                            \
+	 BIT_MASK_RXFFOVFL_RSV_V2_8197F)
+#define BIT_SET_RXFFOVFL_RSV_V2_8197F(x, v)                                    \
+	(BIT_CLEAR_RXFFOVFL_RSV_V2_8197F(x) | BIT_RXFFOVFL_RSV_V2_8197F(v))
+
+#define BIT_SHIFT_TXPKTBUF_PGBNDY_8197F 0
+#define BIT_MASK_TXPKTBUF_PGBNDY_8197F 0xff
+#define BIT_TXPKTBUF_PGBNDY_8197F(x)                                           \
+	(((x) & BIT_MASK_TXPKTBUF_PGBNDY_8197F)                                \
+	 << BIT_SHIFT_TXPKTBUF_PGBNDY_8197F)
+#define BITS_TXPKTBUF_PGBNDY_8197F                                             \
+	(BIT_MASK_TXPKTBUF_PGBNDY_8197F << BIT_SHIFT_TXPKTBUF_PGBNDY_8197F)
+#define BIT_CLEAR_TXPKTBUF_PGBNDY_8197F(x) ((x) & (~BITS_TXPKTBUF_PGBNDY_8197F))
+#define BIT_GET_TXPKTBUF_PGBNDY_8197F(x)                                       \
+	(((x) >> BIT_SHIFT_TXPKTBUF_PGBNDY_8197F) &                            \
+	 BIT_MASK_TXPKTBUF_PGBNDY_8197F)
+#define BIT_SET_TXPKTBUF_PGBNDY_8197F(x, v)                                    \
+	(BIT_CLEAR_TXPKTBUF_PGBNDY_8197F(x) | BIT_TXPKTBUF_PGBNDY_8197F(v))
+
+/* 2 REG_PTA_I2C_MBOX_8197F */
+
+/* 2 REG_NOT_VALID_8197F */
+
+#define BIT_SHIFT_I2C_M_STATUS_8197F 8
+#define BIT_MASK_I2C_M_STATUS_8197F 0xf
+#define BIT_I2C_M_STATUS_8197F(x)                                              \
+	(((x) & BIT_MASK_I2C_M_STATUS_8197F) << BIT_SHIFT_I2C_M_STATUS_8197F)
+#define BITS_I2C_M_STATUS_8197F                                                \
+	(BIT_MASK_I2C_M_STATUS_8197F << BIT_SHIFT_I2C_M_STATUS_8197F)
+#define BIT_CLEAR_I2C_M_STATUS_8197F(x) ((x) & (~BITS_I2C_M_STATUS_8197F))
+#define BIT_GET_I2C_M_STATUS_8197F(x)                                          \
+	(((x) >> BIT_SHIFT_I2C_M_STATUS_8197F) & BIT_MASK_I2C_M_STATUS_8197F)
+#define BIT_SET_I2C_M_STATUS_8197F(x, v)                                       \
+	(BIT_CLEAR_I2C_M_STATUS_8197F(x) | BIT_I2C_M_STATUS_8197F(v))
+
+#define BIT_SHIFT_I2C_M_BUS_GNT_FW_8197F 4
+#define BIT_MASK_I2C_M_BUS_GNT_FW_8197F 0x7
+#define BIT_I2C_M_BUS_GNT_FW_8197F(x)                                          \
+	(((x) & BIT_MASK_I2C_M_BUS_GNT_FW_8197F)                               \
+	 << BIT_SHIFT_I2C_M_BUS_GNT_FW_8197F)
+#define BITS_I2C_M_BUS_GNT_FW_8197F                                            \
+	(BIT_MASK_I2C_M_BUS_GNT_FW_8197F << BIT_SHIFT_I2C_M_BUS_GNT_FW_8197F)
+#define BIT_CLEAR_I2C_M_BUS_GNT_FW_8197F(x)                                    \
+	((x) & (~BITS_I2C_M_BUS_GNT_FW_8197F))
+#define BIT_GET_I2C_M_BUS_GNT_FW_8197F(x)                                      \
+	(((x) >> BIT_SHIFT_I2C_M_BUS_GNT_FW_8197F) &                           \
+	 BIT_MASK_I2C_M_BUS_GNT_FW_8197F)
+#define BIT_SET_I2C_M_BUS_GNT_FW_8197F(x, v)                                   \
+	(BIT_CLEAR_I2C_M_BUS_GNT_FW_8197F(x) | BIT_I2C_M_BUS_GNT_FW_8197F(v))
+
+#define BIT_I2C_M_GNT_FW_8197F BIT(3)
+
+#define BIT_SHIFT_I2C_M_SPEED_8197F 1
+#define BIT_MASK_I2C_M_SPEED_8197F 0x3
+#define BIT_I2C_M_SPEED_8197F(x)                                               \
+	(((x) & BIT_MASK_I2C_M_SPEED_8197F) << BIT_SHIFT_I2C_M_SPEED_8197F)
+#define BITS_I2C_M_SPEED_8197F                                                 \
+	(BIT_MASK_I2C_M_SPEED_8197F << BIT_SHIFT_I2C_M_SPEED_8197F)
+#define BIT_CLEAR_I2C_M_SPEED_8197F(x) ((x) & (~BITS_I2C_M_SPEED_8197F))
+#define BIT_GET_I2C_M_SPEED_8197F(x)                                           \
+	(((x) >> BIT_SHIFT_I2C_M_SPEED_8197F) & BIT_MASK_I2C_M_SPEED_8197F)
+#define BIT_SET_I2C_M_SPEED_8197F(x, v)                                        \
+	(BIT_CLEAR_I2C_M_SPEED_8197F(x) | BIT_I2C_M_SPEED_8197F(v))
+
+#define BIT_I2C_M_UNLOCK_8197F BIT(0)
+
+/* 2 REG_RXFF_BNDY_8197F */
+
+/* 2 REG_NOT_VALID_8197F */
+
+#define BIT_SHIFT_RXFF0_BNDY_V2_8197F 0
+#define BIT_MASK_RXFF0_BNDY_V2_8197F 0x3ffff
+#define BIT_RXFF0_BNDY_V2_8197F(x)                                             \
+	(((x) & BIT_MASK_RXFF0_BNDY_V2_8197F) << BIT_SHIFT_RXFF0_BNDY_V2_8197F)
+#define BITS_RXFF0_BNDY_V2_8197F                                               \
+	(BIT_MASK_RXFF0_BNDY_V2_8197F << BIT_SHIFT_RXFF0_BNDY_V2_8197F)
+#define BIT_CLEAR_RXFF0_BNDY_V2_8197F(x) ((x) & (~BITS_RXFF0_BNDY_V2_8197F))
+#define BIT_GET_RXFF0_BNDY_V2_8197F(x)                                         \
+	(((x) >> BIT_SHIFT_RXFF0_BNDY_V2_8197F) & BIT_MASK_RXFF0_BNDY_V2_8197F)
+#define BIT_SET_RXFF0_BNDY_V2_8197F(x, v)                                      \
+	(BIT_CLEAR_RXFF0_BNDY_V2_8197F(x) | BIT_RXFF0_BNDY_V2_8197F(v))
+
+/* 2 REG_FE1IMR_8197F */
+#define BIT_BB_STOP_RX_INT_EN_8197F BIT(29)
+#define BIT_FS_RXDMA2_DONE_INT_EN_8197F BIT(28)
+#define BIT_FS_RXDONE3_INT_EN_8197F BIT(27)
+#define BIT_FS_RXDONE2_INT_EN_8197F BIT(26)
+#define BIT_FS_RX_BCN_P4_INT_EN_8197F BIT(25)
+#define BIT_FS_RX_BCN_P3_INT_EN_8197F BIT(24)
+#define BIT_FS_RX_BCN_P2_INT_EN_8197F BIT(23)
+#define BIT_FS_RX_BCN_P1_INT_EN_8197F BIT(22)
+#define BIT_FS_RX_BCN_P0_INT_EN_8197F BIT(21)
+#define BIT_FS_RX_UMD0_INT_EN_8197F BIT(20)
+#define BIT_FS_RX_UMD1_INT_EN_8197F BIT(19)
+#define BIT_FS_RX_BMD0_INT_EN_8197F BIT(18)
+#define BIT_FS_RX_BMD1_INT_EN_8197F BIT(17)
+#define BIT_FS_RXDONE_INT_EN_8197F BIT(16)
+#define BIT_FS_WWLAN_INT_EN_8197F BIT(15)
+#define BIT_FS_SOUND_DONE_INT_EN_8197F BIT(14)
+#define BIT_FS_LP_STBY_INT_EN_8197F BIT(13)
+#define BIT_FS_TRL_MTR_INT_EN_8197F BIT(12)
+#define BIT_FS_BF1_PRETO_INT_EN_8197F BIT(11)
+#define BIT_FS_BF0_PRETO_INT_EN_8197F BIT(10)
+#define BIT_FS_PTCL_RELEASE_MACID_INT_EN_8197F BIT(9)
+#define BIT_FS_LTE_COEX_EN_8197F BIT(6)
+#define BIT_FS_WLACTOFF_INT_EN_8197F BIT(5)
+#define BIT_FS_WLACTON_INT_EN_8197F BIT(4)
+#define BIT_FS_BTCMD_INT_EN_8197F BIT(3)
+#define BIT_FS_REG_MAILBOX_TO_I2C_INT_EN_8197F BIT(2)
+#define BIT_FS_TRPC_TO_INT_EN_V1_8197F BIT(1)
+#define BIT_FS_RPC_O_T_INT_EN_V1_8197F BIT(0)
+
+/* 2 REG_FE1ISR_8197F */
+#define BIT_BB_STOP_RX_INT_8197F BIT(29)
+#define BIT_FS_RXDMA2_DONE_INT_8197F BIT(28)
+#define BIT_FS_RXDONE3_INT_8197F BIT(27)
+#define BIT_FS_RXDONE2_INT_8197F BIT(26)
+#define BIT_FS_RX_BCN_P4_INT_8197F BIT(25)
+#define BIT_FS_RX_BCN_P3_INT_8197F BIT(24)
+#define BIT_FS_RX_BCN_P2_INT_8197F BIT(23)
+#define BIT_FS_RX_BCN_P1_INT_8197F BIT(22)
+#define BIT_FS_RX_BCN_P0_INT_8197F BIT(21)
+#define BIT_FS_RX_UMD0_INT_8197F BIT(20)
+#define BIT_FS_RX_UMD1_INT_8197F BIT(19)
+#define BIT_FS_RX_BMD0_INT_8197F BIT(18)
+#define BIT_FS_RX_BMD1_INT_8197F BIT(17)
+#define BIT_FS_RXDONE_INT_8197F BIT(16)
+#define BIT_FS_WWLAN_INT_8197F BIT(15)
+#define BIT_FS_SOUND_DONE_INT_8197F BIT(14)
+#define BIT_FS_LP_STBY_INT_8197F BIT(13)
+#define BIT_FS_TRL_MTR_INT_8197F BIT(12)
+#define BIT_FS_BF1_PRETO_INT_8197F BIT(11)
+#define BIT_FS_BF0_PRETO_INT_8197F BIT(10)
+#define BIT_FS_PTCL_RELEASE_MACID_INT_8197F BIT(9)
+#define BIT_FS_LTE_COEX_INT_8197F BIT(6)
+#define BIT_FS_WLACTOFF_INT_8197F BIT(5)
+#define BIT_FS_WLACTON_INT_8197F BIT(4)
+#define BIT_FS_BCN_RX_INT_INT_8197F BIT(3)
+#define BIT_FS_MAILBOX_TO_I2C_INT_8197F BIT(2)
+#define BIT_FS_TRPC_TO_INT_8197F BIT(1)
+#define BIT_FS_RPC_O_T_INT_8197F BIT(0)
+
+/* 2 REG_NOT_VALID_8197F */
+
+/* 2 REG_CPWM_8197F */
+#define BIT_CPWM_TOGGLING_8197F BIT(31)
+
+#define BIT_SHIFT_CPWM_MOD_8197F 24
+#define BIT_MASK_CPWM_MOD_8197F 0x7f
+#define BIT_CPWM_MOD_8197F(x)                                                  \
+	(((x) & BIT_MASK_CPWM_MOD_8197F) << BIT_SHIFT_CPWM_MOD_8197F)
+#define BITS_CPWM_MOD_8197F                                                    \
+	(BIT_MASK_CPWM_MOD_8197F << BIT_SHIFT_CPWM_MOD_8197F)
+#define BIT_CLEAR_CPWM_MOD_8197F(x) ((x) & (~BITS_CPWM_MOD_8197F))
+#define BIT_GET_CPWM_MOD_8197F(x)                                              \
+	(((x) >> BIT_SHIFT_CPWM_MOD_8197F) & BIT_MASK_CPWM_MOD_8197F)
+#define BIT_SET_CPWM_MOD_8197F(x, v)                                           \
+	(BIT_CLEAR_CPWM_MOD_8197F(x) | BIT_CPWM_MOD_8197F(v))
+
+/* 2 REG_FWIMR_8197F */
+#define BIT_FS_TXBCNOK_MB7_INT_EN_8197F BIT(31)
+#define BIT_FS_TXBCNOK_MB6_INT_EN_8197F BIT(30)
+#define BIT_FS_TXBCNOK_MB5_INT_EN_8197F BIT(29)
+#define BIT_FS_TXBCNOK_MB4_INT_EN_8197F BIT(28)
+#define BIT_FS_TXBCNOK_MB3_INT_EN_8197F BIT(27)
+#define BIT_FS_TXBCNOK_MB2_INT_EN_8197F BIT(26)
+#define BIT_FS_TXBCNOK_MB1_INT_EN_8197F BIT(25)
+#define BIT_FS_TXBCNOK_MB0_INT_EN_8197F BIT(24)
+#define BIT_FS_TXBCNERR_MB7_INT_EN_8197F BIT(23)
+#define BIT_FS_TXBCNERR_MB6_INT_EN_8197F BIT(22)
+#define BIT_FS_TXBCNERR_MB5_INT_EN_8197F BIT(21)
+#define BIT_FS_TXBCNERR_MB4_INT_EN_8197F BIT(20)
+#define BIT_FS_TXBCNERR_MB3_INT_EN_8197F BIT(19)
+#define BIT_FS_TXBCNERR_MB2_INT_EN_8197F BIT(18)
+#define BIT_FS_TXBCNERR_MB1_INT_EN_8197F BIT(17)
+#define BIT_FS_TXBCNERR_MB0_INT_EN_8197F BIT(16)
+#define BIT_CPUMGN_POLLED_PKT_DONE_INT_EN_8197F BIT(15)
+#define BIT_FS_MGNTQ_RPTR_RELEASE_INT_EN_8197F BIT(13)
+#define BIT_FS_MGNTQFF_TO_INT_EN_8197F BIT(12)
+#define BIT_FS_DDMA1_LP_INT_ENBIT_CPUMGN_POLLED_PKT_BUSY_ERR_INT_EN_8197F      \
+	BIT(11)
+#define BIT_FS_DDMA1_HP_INT_EN_8197F BIT(10)
+#define BIT_FS_DDMA0_LP_INT_EN_8197F BIT(9)
+#define BIT_FS_DDMA0_HP_INT_EN_8197F BIT(8)
+#define BIT_FS_TRXRPT_INT_EN_8197F BIT(7)
+#define BIT_FS_C2H_W_READY_INT_EN_8197F BIT(6)
+#define BIT_FS_HRCV_INT_EN_8197F BIT(5)
+#define BIT_FS_H2CCMD_INT_EN_8197F BIT(4)
+#define BIT_FS_TXPKTIN_INT_EN_8197F BIT(3)
+#define BIT_FS_ERRORHDL_INT_EN_8197F BIT(2)
+#define BIT_FS_TXCCX_INT_EN_8197F BIT(1)
+#define BIT_FS_TXCLOSE_INT_EN_8197F BIT(0)
+
+/* 2 REG_FWISR_8197F */
+#define BIT_FS_TXBCNOK_MB7_INT_8197F BIT(31)
+#define BIT_FS_TXBCNOK_MB6_INT_8197F BIT(30)
+#define BIT_FS_TXBCNOK_MB5_INT_8197F BIT(29)
+#define BIT_FS_TXBCNOK_MB4_INT_8197F BIT(28)
+#define BIT_FS_TXBCNOK_MB3_INT_8197F BIT(27)
+#define BIT_FS_TXBCNOK_MB2_INT_8197F BIT(26)
+#define BIT_FS_TXBCNOK_MB1_INT_8197F BIT(25)
+#define BIT_FS_TXBCNOK_MB0_INT_8197F BIT(24)
+#define BIT_FS_TXBCNERR_MB7_INT_8197F BIT(23)
+#define BIT_FS_TXBCNERR_MB6_INT_8197F BIT(22)
+#define BIT_FS_TXBCNERR_MB5_INT_8197F BIT(21)
+#define BIT_FS_TXBCNERR_MB4_INT_8197F BIT(20)
+#define BIT_FS_TXBCNERR_MB3_INT_8197F BIT(19)
+#define BIT_FS_TXBCNERR_MB2_INT_8197F BIT(18)
+#define BIT_FS_TXBCNERR_MB1_INT_8197F BIT(17)
+#define BIT_FS_TXBCNERR_MB0_INT_8197F BIT(16)
+#define BIT_CPUMGN_POLLED_PKT_DONE_INT_8197F BIT(15)
+#define BIT_FS_MGNTQ_RPTR_RELEASE_INT_8197F BIT(13)
+#define BIT_FS_MGNTQFF_TO_INT_8197F BIT(12)
+#define BIT_FS_DDMA1_LP_INTBIT_CPUMGN_POLLED_PKT_BUSY_ERR_INT_8197F BIT(11)
+#define BIT_FS_DDMA1_HP_INT_8197F BIT(10)
+#define BIT_FS_DDMA0_LP_INT_8197F BIT(9)
+#define BIT_FS_DDMA0_HP_INT_8197F BIT(8)
+#define BIT_FS_TRXRPT_INT_8197F BIT(7)
+#define BIT_FS_C2H_W_READY_INT_8197F BIT(6)
+#define BIT_FS_HRCV_INT_8197F BIT(5)
+#define BIT_FS_H2CCMD_INT_8197F BIT(4)
+#define BIT_FS_TXPKTIN_INT_8197F BIT(3)
+#define BIT_FS_ERRORHDL_INT_8197F BIT(2)
+#define BIT_FS_TXCCX_INT_8197F BIT(1)
+#define BIT_FS_TXCLOSE_INT_8197F BIT(0)
+
+/* 2 REG_FTIMR_8197F */
+#define BIT_PS_TIMER_C_EARLY_INT_EN_8197F BIT(23)
+#define BIT_PS_TIMER_B_EARLY_INT_EN_8197F BIT(22)
+#define BIT_PS_TIMER_A_EARLY_INT_EN_8197F BIT(21)
+#define BIT_CPUMGQ_TX_TIMER_EARLY_INT_EN_8197F BIT(20)
+#define BIT_PS_TIMER_C_INT_EN_8197F BIT(19)
+#define BIT_PS_TIMER_B_INT_EN_8197F BIT(18)
+#define BIT_PS_TIMER_A_INT_EN_8197F BIT(17)
+#define BIT_CPUMGQ_TX_TIMER_INT_EN_8197F BIT(16)
+#define BIT_FS_PS_TIMEOUT2_EN_8197F BIT(15)
+#define BIT_FS_PS_TIMEOUT1_EN_8197F BIT(14)
+#define BIT_FS_PS_TIMEOUT0_EN_8197F BIT(13)
+#define BIT_FS_GTINT8_EN_8197F BIT(8)
+#define BIT_FS_GTINT7_EN_8197F BIT(7)
+#define BIT_FS_GTINT6_EN_8197F BIT(6)
+#define BIT_FS_GTINT5_EN_8197F BIT(5)
+#define BIT_FS_GTINT4_EN_8197F BIT(4)
+#define BIT_FS_GTINT3_EN_8197F BIT(3)
+#define BIT_FS_GTINT2_EN_8197F BIT(2)
+#define BIT_FS_GTINT1_EN_8197F BIT(1)
+#define BIT_FS_GTINT0_EN_8197F BIT(0)
+
+/* 2 REG_FTISR_8197F */
+#define BIT_PS_TIMER_C_EARLY__INT_8197F BIT(23)
+#define BIT_PS_TIMER_B_EARLY__INT_8197F BIT(22)
+#define BIT_PS_TIMER_A_EARLY__INT_8197F BIT(21)
+#define BIT_CPUMGQ_TX_TIMER_EARLY_INT_8197F BIT(20)
+#define BIT_PS_TIMER_C_INT_8197F BIT(19)
+#define BIT_PS_TIMER_B_INT_8197F BIT(18)
+#define BIT_PS_TIMER_A_INT_8197F BIT(17)
+#define BIT_CPUMGQ_TX_TIMER_INT_8197F BIT(16)
+#define BIT_FS_PS_TIMEOUT2_INT_8197F BIT(15)
+#define BIT_FS_PS_TIMEOUT1_INT_8197F BIT(14)
+#define BIT_FS_PS_TIMEOUT0_INT_8197F BIT(13)
+#define BIT_FS_GTINT8_INT_8197F BIT(8)
+#define BIT_FS_GTINT7_INT_8197F BIT(7)
+#define BIT_FS_GTINT6_INT_8197F BIT(6)
+#define BIT_FS_GTINT5_INT_8197F BIT(5)
+#define BIT_FS_GTINT4_INT_8197F BIT(4)
+#define BIT_FS_GTINT3_INT_8197F BIT(3)
+#define BIT_FS_GTINT2_INT_8197F BIT(2)
+#define BIT_FS_GTINT1_INT_8197F BIT(1)
+#define BIT_FS_GTINT0_INT_8197F BIT(0)
+
+/* 2 REG_PKTBUF_DBG_CTRL_8197F */
+
+#define BIT_SHIFT_PKTBUF_WRITE_EN_8197F 24
+#define BIT_MASK_PKTBUF_WRITE_EN_8197F 0xff
+#define BIT_PKTBUF_WRITE_EN_8197F(x)                                           \
+	(((x) & BIT_MASK_PKTBUF_WRITE_EN_8197F)                                \
+	 << BIT_SHIFT_PKTBUF_WRITE_EN_8197F)
+#define BITS_PKTBUF_WRITE_EN_8197F                                             \
+	(BIT_MASK_PKTBUF_WRITE_EN_8197F << BIT_SHIFT_PKTBUF_WRITE_EN_8197F)
+#define BIT_CLEAR_PKTBUF_WRITE_EN_8197F(x) ((x) & (~BITS_PKTBUF_WRITE_EN_8197F))
+#define BIT_GET_PKTBUF_WRITE_EN_8197F(x)                                       \
+	(((x) >> BIT_SHIFT_PKTBUF_WRITE_EN_8197F) &                            \
+	 BIT_MASK_PKTBUF_WRITE_EN_8197F)
+#define BIT_SET_PKTBUF_WRITE_EN_8197F(x, v)                                    \
+	(BIT_CLEAR_PKTBUF_WRITE_EN_8197F(x) | BIT_PKTBUF_WRITE_EN_8197F(v))
+
+#define BIT_TXRPTBUF_DBG_8197F BIT(23)
+
+/* 2 REG_NOT_VALID_8197F */
+#define BIT_TXPKTBUF_DBG_V2_8197F BIT(20)
+#define BIT_RXPKTBUF_DBG_8197F BIT(16)
+
+#define BIT_SHIFT_PKTBUF_DBG_ADDR_8197F 0
+#define BIT_MASK_PKTBUF_DBG_ADDR_8197F 0x1fff
+#define BIT_PKTBUF_DBG_ADDR_8197F(x)                                           \
+	(((x) & BIT_MASK_PKTBUF_DBG_ADDR_8197F)                                \
+	 << BIT_SHIFT_PKTBUF_DBG_ADDR_8197F)
+#define BITS_PKTBUF_DBG_ADDR_8197F                                             \
+	(BIT_MASK_PKTBUF_DBG_ADDR_8197F << BIT_SHIFT_PKTBUF_DBG_ADDR_8197F)
+#define BIT_CLEAR_PKTBUF_DBG_ADDR_8197F(x) ((x) & (~BITS_PKTBUF_DBG_ADDR_8197F))
+#define BIT_GET_PKTBUF_DBG_ADDR_8197F(x)                                       \
+	(((x) >> BIT_SHIFT_PKTBUF_DBG_ADDR_8197F) &                            \
+	 BIT_MASK_PKTBUF_DBG_ADDR_8197F)
+#define BIT_SET_PKTBUF_DBG_ADDR_8197F(x, v)                                    \
+	(BIT_CLEAR_PKTBUF_DBG_ADDR_8197F(x) | BIT_PKTBUF_DBG_ADDR_8197F(v))
+
+/* 2 REG_PKTBUF_DBG_DATA_L_8197F */
+
+#define BIT_SHIFT_PKTBUF_DBG_DATA_L_8197F 0
+#define BIT_MASK_PKTBUF_DBG_DATA_L_8197F 0xffffffffL
+#define BIT_PKTBUF_DBG_DATA_L_8197F(x)                                         \
+	(((x) & BIT_MASK_PKTBUF_DBG_DATA_L_8197F)                              \
+	 << BIT_SHIFT_PKTBUF_DBG_DATA_L_8197F)
+#define BITS_PKTBUF_DBG_DATA_L_8197F                                           \
+	(BIT_MASK_PKTBUF_DBG_DATA_L_8197F << BIT_SHIFT_PKTBUF_DBG_DATA_L_8197F)
+#define BIT_CLEAR_PKTBUF_DBG_DATA_L_8197F(x)                                   \
+	((x) & (~BITS_PKTBUF_DBG_DATA_L_8197F))
+#define BIT_GET_PKTBUF_DBG_DATA_L_8197F(x)                                     \
+	(((x) >> BIT_SHIFT_PKTBUF_DBG_DATA_L_8197F) &                          \
+	 BIT_MASK_PKTBUF_DBG_DATA_L_8197F)
+#define BIT_SET_PKTBUF_DBG_DATA_L_8197F(x, v)                                  \
+	(BIT_CLEAR_PKTBUF_DBG_DATA_L_8197F(x) | BIT_PKTBUF_DBG_DATA_L_8197F(v))
+
+/* 2 REG_PKTBUF_DBG_DATA_H_8197F */
+
+#define BIT_SHIFT_PKTBUF_DBG_DATA_H_8197F 0
+#define BIT_MASK_PKTBUF_DBG_DATA_H_8197F 0xffffffffL
+#define BIT_PKTBUF_DBG_DATA_H_8197F(x)                                         \
+	(((x) & BIT_MASK_PKTBUF_DBG_DATA_H_8197F)                              \
+	 << BIT_SHIFT_PKTBUF_DBG_DATA_H_8197F)
+#define BITS_PKTBUF_DBG_DATA_H_8197F                                           \
+	(BIT_MASK_PKTBUF_DBG_DATA_H_8197F << BIT_SHIFT_PKTBUF_DBG_DATA_H_8197F)
+#define BIT_CLEAR_PKTBUF_DBG_DATA_H_8197F(x)                                   \
+	((x) & (~BITS_PKTBUF_DBG_DATA_H_8197F))
+#define BIT_GET_PKTBUF_DBG_DATA_H_8197F(x)                                     \
+	(((x) >> BIT_SHIFT_PKTBUF_DBG_DATA_H_8197F) &                          \
+	 BIT_MASK_PKTBUF_DBG_DATA_H_8197F)
+#define BIT_SET_PKTBUF_DBG_DATA_H_8197F(x, v)                                  \
+	(BIT_CLEAR_PKTBUF_DBG_DATA_H_8197F(x) | BIT_PKTBUF_DBG_DATA_H_8197F(v))
+
+/* 2 REG_CPWM2_8197F */
+
+#define BIT_SHIFT_L0S_TO_RCVY_NUM_8197F 16
+#define BIT_MASK_L0S_TO_RCVY_NUM_8197F 0xff
+#define BIT_L0S_TO_RCVY_NUM_8197F(x)                                           \
+	(((x) & BIT_MASK_L0S_TO_RCVY_NUM_8197F)                                \
+	 << BIT_SHIFT_L0S_TO_RCVY_NUM_8197F)
+#define BITS_L0S_TO_RCVY_NUM_8197F                                             \
+	(BIT_MASK_L0S_TO_RCVY_NUM_8197F << BIT_SHIFT_L0S_TO_RCVY_NUM_8197F)
+#define BIT_CLEAR_L0S_TO_RCVY_NUM_8197F(x) ((x) & (~BITS_L0S_TO_RCVY_NUM_8197F))
+#define BIT_GET_L0S_TO_RCVY_NUM_8197F(x)                                       \
+	(((x) >> BIT_SHIFT_L0S_TO_RCVY_NUM_8197F) &                            \
+	 BIT_MASK_L0S_TO_RCVY_NUM_8197F)
+#define BIT_SET_L0S_TO_RCVY_NUM_8197F(x, v)                                    \
+	(BIT_CLEAR_L0S_TO_RCVY_NUM_8197F(x) | BIT_L0S_TO_RCVY_NUM_8197F(v))
+
+#define BIT_CPWM2_TOGGLING_8197F BIT(15)
+
+#define BIT_SHIFT_CPWM2_MOD_8197F 0
+#define BIT_MASK_CPWM2_MOD_8197F 0x7fff
+#define BIT_CPWM2_MOD_8197F(x)                                                 \
+	(((x) & BIT_MASK_CPWM2_MOD_8197F) << BIT_SHIFT_CPWM2_MOD_8197F)
+#define BITS_CPWM2_MOD_8197F                                                   \
+	(BIT_MASK_CPWM2_MOD_8197F << BIT_SHIFT_CPWM2_MOD_8197F)
+#define BIT_CLEAR_CPWM2_MOD_8197F(x) ((x) & (~BITS_CPWM2_MOD_8197F))
+#define BIT_GET_CPWM2_MOD_8197F(x)                                             \
+	(((x) >> BIT_SHIFT_CPWM2_MOD_8197F) & BIT_MASK_CPWM2_MOD_8197F)
+#define BIT_SET_CPWM2_MOD_8197F(x, v)                                          \
+	(BIT_CLEAR_CPWM2_MOD_8197F(x) | BIT_CPWM2_MOD_8197F(v))
+
+/* 2 REG_NOT_VALID_8197F */
+
+/* 2 REG_TC0_CTRL_8197F */
+#define BIT_TC0INT_EN_8197F BIT(26)
+#define BIT_TC0MODE_8197F BIT(25)
+#define BIT_TC0EN_8197F BIT(24)
+
+#define BIT_SHIFT_TC0DATA_8197F 0
+#define BIT_MASK_TC0DATA_8197F 0xffffff
+#define BIT_TC0DATA_8197F(x)                                                   \
+	(((x) & BIT_MASK_TC0DATA_8197F) << BIT_SHIFT_TC0DATA_8197F)
+#define BITS_TC0DATA_8197F (BIT_MASK_TC0DATA_8197F << BIT_SHIFT_TC0DATA_8197F)
+#define BIT_CLEAR_TC0DATA_8197F(x) ((x) & (~BITS_TC0DATA_8197F))
+#define BIT_GET_TC0DATA_8197F(x)                                               \
+	(((x) >> BIT_SHIFT_TC0DATA_8197F) & BIT_MASK_TC0DATA_8197F)
+#define BIT_SET_TC0DATA_8197F(x, v)                                            \
+	(BIT_CLEAR_TC0DATA_8197F(x) | BIT_TC0DATA_8197F(v))
+
+/* 2 REG_TC1_CTRL_8197F */
+#define BIT_TC1INT_EN_8197F BIT(26)
+#define BIT_TC1MODE_8197F BIT(25)
+#define BIT_TC1EN_8197F BIT(24)
+
+#define BIT_SHIFT_TC1DATA_8197F 0
+#define BIT_MASK_TC1DATA_8197F 0xffffff
+#define BIT_TC1DATA_8197F(x)                                                   \
+	(((x) & BIT_MASK_TC1DATA_8197F) << BIT_SHIFT_TC1DATA_8197F)
+#define BITS_TC1DATA_8197F (BIT_MASK_TC1DATA_8197F << BIT_SHIFT_TC1DATA_8197F)
+#define BIT_CLEAR_TC1DATA_8197F(x) ((x) & (~BITS_TC1DATA_8197F))
+#define BIT_GET_TC1DATA_8197F(x)                                               \
+	(((x) >> BIT_SHIFT_TC1DATA_8197F) & BIT_MASK_TC1DATA_8197F)
+#define BIT_SET_TC1DATA_8197F(x, v)                                            \
+	(BIT_CLEAR_TC1DATA_8197F(x) | BIT_TC1DATA_8197F(v))
+
+/* 2 REG_TC2_CTRL_8197F */
+#define BIT_TC2INT_EN_8197F BIT(26)
+#define BIT_TC2MODE_8197F BIT(25)
+#define BIT_TC2EN_8197F BIT(24)
+
+#define BIT_SHIFT_TC2DATA_8197F 0
+#define BIT_MASK_TC2DATA_8197F 0xffffff
+#define BIT_TC2DATA_8197F(x)                                                   \
+	(((x) & BIT_MASK_TC2DATA_8197F) << BIT_SHIFT_TC2DATA_8197F)
+#define BITS_TC2DATA_8197F (BIT_MASK_TC2DATA_8197F << BIT_SHIFT_TC2DATA_8197F)
+#define BIT_CLEAR_TC2DATA_8197F(x) ((x) & (~BITS_TC2DATA_8197F))
+#define BIT_GET_TC2DATA_8197F(x)                                               \
+	(((x) >> BIT_SHIFT_TC2DATA_8197F) & BIT_MASK_TC2DATA_8197F)
+#define BIT_SET_TC2DATA_8197F(x, v)                                            \
+	(BIT_CLEAR_TC2DATA_8197F(x) | BIT_TC2DATA_8197F(v))
+
+/* 2 REG_TC3_CTRL_8197F */
+#define BIT_TC3INT_EN_8197F BIT(26)
+#define BIT_TC3MODE_8197F BIT(25)
+#define BIT_TC3EN_8197F BIT(24)
+
+#define BIT_SHIFT_TC3DATA_8197F 0
+#define BIT_MASK_TC3DATA_8197F 0xffffff
+#define BIT_TC3DATA_8197F(x)                                                   \
+	(((x) & BIT_MASK_TC3DATA_8197F) << BIT_SHIFT_TC3DATA_8197F)
+#define BITS_TC3DATA_8197F (BIT_MASK_TC3DATA_8197F << BIT_SHIFT_TC3DATA_8197F)
+#define BIT_CLEAR_TC3DATA_8197F(x) ((x) & (~BITS_TC3DATA_8197F))
+#define BIT_GET_TC3DATA_8197F(x)                                               \
+	(((x) >> BIT_SHIFT_TC3DATA_8197F) & BIT_MASK_TC3DATA_8197F)
+#define BIT_SET_TC3DATA_8197F(x, v)                                            \
+	(BIT_CLEAR_TC3DATA_8197F(x) | BIT_TC3DATA_8197F(v))
+
+/* 2 REG_TC4_CTRL_8197F */
+#define BIT_TC4INT_EN_8197F BIT(26)
+#define BIT_TC4MODE_8197F BIT(25)
+#define BIT_TC4EN_8197F BIT(24)
+
+#define BIT_SHIFT_TC4DATA_8197F 0
+#define BIT_MASK_TC4DATA_8197F 0xffffff
+#define BIT_TC4DATA_8197F(x)                                                   \
+	(((x) & BIT_MASK_TC4DATA_8197F) << BIT_SHIFT_TC4DATA_8197F)
+#define BITS_TC4DATA_8197F (BIT_MASK_TC4DATA_8197F << BIT_SHIFT_TC4DATA_8197F)
+#define BIT_CLEAR_TC4DATA_8197F(x) ((x) & (~BITS_TC4DATA_8197F))
+#define BIT_GET_TC4DATA_8197F(x)                                               \
+	(((x) >> BIT_SHIFT_TC4DATA_8197F) & BIT_MASK_TC4DATA_8197F)
+#define BIT_SET_TC4DATA_8197F(x, v)                                            \
+	(BIT_CLEAR_TC4DATA_8197F(x) | BIT_TC4DATA_8197F(v))
+
+/* 2 REG_TCUNIT_BASE_8197F */
+
+#define BIT_SHIFT_TCUNIT_BASE_8197F 0
+#define BIT_MASK_TCUNIT_BASE_8197F 0x3fff
+#define BIT_TCUNIT_BASE_8197F(x)                                               \
+	(((x) & BIT_MASK_TCUNIT_BASE_8197F) << BIT_SHIFT_TCUNIT_BASE_8197F)
+#define BITS_TCUNIT_BASE_8197F                                                 \
+	(BIT_MASK_TCUNIT_BASE_8197F << BIT_SHIFT_TCUNIT_BASE_8197F)
+#define BIT_CLEAR_TCUNIT_BASE_8197F(x) ((x) & (~BITS_TCUNIT_BASE_8197F))
+#define BIT_GET_TCUNIT_BASE_8197F(x)                                           \
+	(((x) >> BIT_SHIFT_TCUNIT_BASE_8197F) & BIT_MASK_TCUNIT_BASE_8197F)
+#define BIT_SET_TCUNIT_BASE_8197F(x, v)                                        \
+	(BIT_CLEAR_TCUNIT_BASE_8197F(x) | BIT_TCUNIT_BASE_8197F(v))
+
+/* 2 REG_TC5_CTRL_8197F */
+#define BIT_TC5INT_EN_8197F BIT(26)
+#define BIT_TC5MODE_8197F BIT(25)
+#define BIT_TC5EN_8197F BIT(24)
+
+#define BIT_SHIFT_TC5DATA_8197F 0
+#define BIT_MASK_TC5DATA_8197F 0xffffff
+#define BIT_TC5DATA_8197F(x)                                                   \
+	(((x) & BIT_MASK_TC5DATA_8197F) << BIT_SHIFT_TC5DATA_8197F)
+#define BITS_TC5DATA_8197F (BIT_MASK_TC5DATA_8197F << BIT_SHIFT_TC5DATA_8197F)
+#define BIT_CLEAR_TC5DATA_8197F(x) ((x) & (~BITS_TC5DATA_8197F))
+#define BIT_GET_TC5DATA_8197F(x)                                               \
+	(((x) >> BIT_SHIFT_TC5DATA_8197F) & BIT_MASK_TC5DATA_8197F)
+#define BIT_SET_TC5DATA_8197F(x, v)                                            \
+	(BIT_CLEAR_TC5DATA_8197F(x) | BIT_TC5DATA_8197F(v))
+
+/* 2 REG_TC6_CTRL_8197F */
+#define BIT_TC6INT_EN_8197F BIT(26)
+#define BIT_TC6MODE_8197F BIT(25)
+#define BIT_TC6EN_8197F BIT(24)
+
+#define BIT_SHIFT_TC6DATA_8197F 0
+#define BIT_MASK_TC6DATA_8197F 0xffffff
+#define BIT_TC6DATA_8197F(x)                                                   \
+	(((x) & BIT_MASK_TC6DATA_8197F) << BIT_SHIFT_TC6DATA_8197F)
+#define BITS_TC6DATA_8197F (BIT_MASK_TC6DATA_8197F << BIT_SHIFT_TC6DATA_8197F)
+#define BIT_CLEAR_TC6DATA_8197F(x) ((x) & (~BITS_TC6DATA_8197F))
+#define BIT_GET_TC6DATA_8197F(x)                                               \
+	(((x) >> BIT_SHIFT_TC6DATA_8197F) & BIT_MASK_TC6DATA_8197F)
+#define BIT_SET_TC6DATA_8197F(x, v)                                            \
+	(BIT_CLEAR_TC6DATA_8197F(x) | BIT_TC6DATA_8197F(v))
+
+/* 2 REG_MBIST_FAIL_8197F */
+
+#define BIT_SHIFT_8051_MBIST_FAIL_8197F 26
+#define BIT_MASK_8051_MBIST_FAIL_8197F 0x7
+#define BIT_8051_MBIST_FAIL_8197F(x)                                           \
+	(((x) & BIT_MASK_8051_MBIST_FAIL_8197F)                                \
+	 << BIT_SHIFT_8051_MBIST_FAIL_8197F)
+#define BITS_8051_MBIST_FAIL_8197F                                             \
+	(BIT_MASK_8051_MBIST_FAIL_8197F << BIT_SHIFT_8051_MBIST_FAIL_8197F)
+#define BIT_CLEAR_8051_MBIST_FAIL_8197F(x) ((x) & (~BITS_8051_MBIST_FAIL_8197F))
+#define BIT_GET_8051_MBIST_FAIL_8197F(x)                                       \
+	(((x) >> BIT_SHIFT_8051_MBIST_FAIL_8197F) &                            \
+	 BIT_MASK_8051_MBIST_FAIL_8197F)
+#define BIT_SET_8051_MBIST_FAIL_8197F(x, v)                                    \
+	(BIT_CLEAR_8051_MBIST_FAIL_8197F(x) | BIT_8051_MBIST_FAIL_8197F(v))
+
+#define BIT_SHIFT_USB_MBIST_FAIL_8197F 24
+#define BIT_MASK_USB_MBIST_FAIL_8197F 0x3
+#define BIT_USB_MBIST_FAIL_8197F(x)                                            \
+	(((x) & BIT_MASK_USB_MBIST_FAIL_8197F)                                 \
+	 << BIT_SHIFT_USB_MBIST_FAIL_8197F)
+#define BITS_USB_MBIST_FAIL_8197F                                              \
+	(BIT_MASK_USB_MBIST_FAIL_8197F << BIT_SHIFT_USB_MBIST_FAIL_8197F)
+#define BIT_CLEAR_USB_MBIST_FAIL_8197F(x) ((x) & (~BITS_USB_MBIST_FAIL_8197F))
+#define BIT_GET_USB_MBIST_FAIL_8197F(x)                                        \
+	(((x) >> BIT_SHIFT_USB_MBIST_FAIL_8197F) &                             \
+	 BIT_MASK_USB_MBIST_FAIL_8197F)
+#define BIT_SET_USB_MBIST_FAIL_8197F(x, v)                                     \
+	(BIT_CLEAR_USB_MBIST_FAIL_8197F(x) | BIT_USB_MBIST_FAIL_8197F(v))
+
+#define BIT_SHIFT_PCIE_MBIST_FAIL_8197F 16
+#define BIT_MASK_PCIE_MBIST_FAIL_8197F 0x3f
+#define BIT_PCIE_MBIST_FAIL_8197F(x)                                           \
+	(((x) & BIT_MASK_PCIE_MBIST_FAIL_8197F)                                \
+	 << BIT_SHIFT_PCIE_MBIST_FAIL_8197F)
+#define BITS_PCIE_MBIST_FAIL_8197F                                             \
+	(BIT_MASK_PCIE_MBIST_FAIL_8197F << BIT_SHIFT_PCIE_MBIST_FAIL_8197F)
+#define BIT_CLEAR_PCIE_MBIST_FAIL_8197F(x) ((x) & (~BITS_PCIE_MBIST_FAIL_8197F))
+#define BIT_GET_PCIE_MBIST_FAIL_8197F(x)                                       \
+	(((x) >> BIT_SHIFT_PCIE_MBIST_FAIL_8197F) &                            \
+	 BIT_MASK_PCIE_MBIST_FAIL_8197F)
+#define BIT_SET_PCIE_MBIST_FAIL_8197F(x, v)                                    \
+	(BIT_CLEAR_PCIE_MBIST_FAIL_8197F(x) | BIT_PCIE_MBIST_FAIL_8197F(v))
+
+#define BIT_SHIFT_MAC_MBIST_FAIL_DRF_8197F 0
+#define BIT_MASK_MAC_MBIST_FAIL_DRF_8197F 0x3ffff
+#define BIT_MAC_MBIST_FAIL_DRF_8197F(x)                                        \
+	(((x) & BIT_MASK_MAC_MBIST_FAIL_DRF_8197F)                             \
+	 << BIT_SHIFT_MAC_MBIST_FAIL_DRF_8197F)
+#define BITS_MAC_MBIST_FAIL_DRF_8197F                                          \
+	(BIT_MASK_MAC_MBIST_FAIL_DRF_8197F                                     \
+	 << BIT_SHIFT_MAC_MBIST_FAIL_DRF_8197F)
+#define BIT_CLEAR_MAC_MBIST_FAIL_DRF_8197F(x)                                  \
+	((x) & (~BITS_MAC_MBIST_FAIL_DRF_8197F))
+#define BIT_GET_MAC_MBIST_FAIL_DRF_8197F(x)                                    \
+	(((x) >> BIT_SHIFT_MAC_MBIST_FAIL_DRF_8197F) &                         \
+	 BIT_MASK_MAC_MBIST_FAIL_DRF_8197F)
+#define BIT_SET_MAC_MBIST_FAIL_DRF_8197F(x, v)                                 \
+	(BIT_CLEAR_MAC_MBIST_FAIL_DRF_8197F(x) |                               \
+	 BIT_MAC_MBIST_FAIL_DRF_8197F(v))
+
+/* 2 REG_MBIST_START_PAUSE_8197F */
+
+#define BIT_SHIFT_8051_MBIST_START_PAUSE_8197F 26
+#define BIT_MASK_8051_MBIST_START_PAUSE_8197F 0x7
+#define BIT_8051_MBIST_START_PAUSE_8197F(x)                                    \
+	(((x) & BIT_MASK_8051_MBIST_START_PAUSE_8197F)                         \
+	 << BIT_SHIFT_8051_MBIST_START_PAUSE_8197F)
+#define BITS_8051_MBIST_START_PAUSE_8197F                                      \
+	(BIT_MASK_8051_MBIST_START_PAUSE_8197F                                 \
+	 << BIT_SHIFT_8051_MBIST_START_PAUSE_8197F)
+#define BIT_CLEAR_8051_MBIST_START_PAUSE_8197F(x)                              \
+	((x) & (~BITS_8051_MBIST_START_PAUSE_8197F))
+#define BIT_GET_8051_MBIST_START_PAUSE_8197F(x)                                \
+	(((x) >> BIT_SHIFT_8051_MBIST_START_PAUSE_8197F) &                     \
+	 BIT_MASK_8051_MBIST_START_PAUSE_8197F)
+#define BIT_SET_8051_MBIST_START_PAUSE_8197F(x, v)                             \
+	(BIT_CLEAR_8051_MBIST_START_PAUSE_8197F(x) |                           \
+	 BIT_8051_MBIST_START_PAUSE_8197F(v))
+
+#define BIT_SHIFT_USB_MBIST_START_PAUSE_8197F 24
+#define BIT_MASK_USB_MBIST_START_PAUSE_8197F 0x3
+#define BIT_USB_MBIST_START_PAUSE_8197F(x)                                     \
+	(((x) & BIT_MASK_USB_MBIST_START_PAUSE_8197F)                          \
+	 << BIT_SHIFT_USB_MBIST_START_PAUSE_8197F)
+#define BITS_USB_MBIST_START_PAUSE_8197F                                       \
+	(BIT_MASK_USB_MBIST_START_PAUSE_8197F                                  \
+	 << BIT_SHIFT_USB_MBIST_START_PAUSE_8197F)
+#define BIT_CLEAR_USB_MBIST_START_PAUSE_8197F(x)                               \
+	((x) & (~BITS_USB_MBIST_START_PAUSE_8197F))
+#define BIT_GET_USB_MBIST_START_PAUSE_8197F(x)                                 \
+	(((x) >> BIT_SHIFT_USB_MBIST_START_PAUSE_8197F) &                      \
+	 BIT_MASK_USB_MBIST_START_PAUSE_8197F)
+#define BIT_SET_USB_MBIST_START_PAUSE_8197F(x, v)                              \
+	(BIT_CLEAR_USB_MBIST_START_PAUSE_8197F(x) |                            \
+	 BIT_USB_MBIST_START_PAUSE_8197F(v))
+
+#define BIT_SHIFT_PCIE_MBIST_START_PAUSE_8197F 16
+#define BIT_MASK_PCIE_MBIST_START_PAUSE_8197F 0x3f
+#define BIT_PCIE_MBIST_START_PAUSE_8197F(x)                                    \
+	(((x) & BIT_MASK_PCIE_MBIST_START_PAUSE_8197F)                         \
+	 << BIT_SHIFT_PCIE_MBIST_START_PAUSE_8197F)
+#define BITS_PCIE_MBIST_START_PAUSE_8197F                                      \
+	(BIT_MASK_PCIE_MBIST_START_PAUSE_8197F                                 \
+	 << BIT_SHIFT_PCIE_MBIST_START_PAUSE_8197F)
+#define BIT_CLEAR_PCIE_MBIST_START_PAUSE_8197F(x)                              \
+	((x) & (~BITS_PCIE_MBIST_START_PAUSE_8197F))
+#define BIT_GET_PCIE_MBIST_START_PAUSE_8197F(x)                                \
+	(((x) >> BIT_SHIFT_PCIE_MBIST_START_PAUSE_8197F) &                     \
+	 BIT_MASK_PCIE_MBIST_START_PAUSE_8197F)
+#define BIT_SET_PCIE_MBIST_START_PAUSE_8197F(x, v)                             \
+	(BIT_CLEAR_PCIE_MBIST_START_PAUSE_8197F(x) |                           \
+	 BIT_PCIE_MBIST_START_PAUSE_8197F(v))
+
+#define BIT_SHIFT_MAC_MBIST_START_PAUSE_V1_8197F 0
+#define BIT_MASK_MAC_MBIST_START_PAUSE_V1_8197F 0x3ffff
+#define BIT_MAC_MBIST_START_PAUSE_V1_8197F(x)                                  \
+	(((x) & BIT_MASK_MAC_MBIST_START_PAUSE_V1_8197F)                       \
+	 << BIT_SHIFT_MAC_MBIST_START_PAUSE_V1_8197F)
+#define BITS_MAC_MBIST_START_PAUSE_V1_8197F                                    \
+	(BIT_MASK_MAC_MBIST_START_PAUSE_V1_8197F                               \
+	 << BIT_SHIFT_MAC_MBIST_START_PAUSE_V1_8197F)
+#define BIT_CLEAR_MAC_MBIST_START_PAUSE_V1_8197F(x)                            \
+	((x) & (~BITS_MAC_MBIST_START_PAUSE_V1_8197F))
+#define BIT_GET_MAC_MBIST_START_PAUSE_V1_8197F(x)                              \
+	(((x) >> BIT_SHIFT_MAC_MBIST_START_PAUSE_V1_8197F) &                   \
+	 BIT_MASK_MAC_MBIST_START_PAUSE_V1_8197F)
+#define BIT_SET_MAC_MBIST_START_PAUSE_V1_8197F(x, v)                           \
+	(BIT_CLEAR_MAC_MBIST_START_PAUSE_V1_8197F(x) |                         \
+	 BIT_MAC_MBIST_START_PAUSE_V1_8197F(v))
+
+/* 2 REG_MBIST_DONE_8197F */
+
+#define BIT_SHIFT_8051_MBIST_DONE_8197F 26
+#define BIT_MASK_8051_MBIST_DONE_8197F 0x7
+#define BIT_8051_MBIST_DONE_8197F(x)                                           \
+	(((x) & BIT_MASK_8051_MBIST_DONE_8197F)                                \
+	 << BIT_SHIFT_8051_MBIST_DONE_8197F)
+#define BITS_8051_MBIST_DONE_8197F                                             \
+	(BIT_MASK_8051_MBIST_DONE_8197F << BIT_SHIFT_8051_MBIST_DONE_8197F)
+#define BIT_CLEAR_8051_MBIST_DONE_8197F(x) ((x) & (~BITS_8051_MBIST_DONE_8197F))
+#define BIT_GET_8051_MBIST_DONE_8197F(x)                                       \
+	(((x) >> BIT_SHIFT_8051_MBIST_DONE_8197F) &                            \
+	 BIT_MASK_8051_MBIST_DONE_8197F)
+#define BIT_SET_8051_MBIST_DONE_8197F(x, v)                                    \
+	(BIT_CLEAR_8051_MBIST_DONE_8197F(x) | BIT_8051_MBIST_DONE_8197F(v))
+
+#define BIT_SHIFT_USB_MBIST_DONE_8197F 24
+#define BIT_MASK_USB_MBIST_DONE_8197F 0x3
+#define BIT_USB_MBIST_DONE_8197F(x)                                            \
+	(((x) & BIT_MASK_USB_MBIST_DONE_8197F)                                 \
+	 << BIT_SHIFT_USB_MBIST_DONE_8197F)
+#define BITS_USB_MBIST_DONE_8197F                                              \
+	(BIT_MASK_USB_MBIST_DONE_8197F << BIT_SHIFT_USB_MBIST_DONE_8197F)
+#define BIT_CLEAR_USB_MBIST_DONE_8197F(x) ((x) & (~BITS_USB_MBIST_DONE_8197F))
+#define BIT_GET_USB_MBIST_DONE_8197F(x)                                        \
+	(((x) >> BIT_SHIFT_USB_MBIST_DONE_8197F) &                             \
+	 BIT_MASK_USB_MBIST_DONE_8197F)
+#define BIT_SET_USB_MBIST_DONE_8197F(x, v)                                     \
+	(BIT_CLEAR_USB_MBIST_DONE_8197F(x) | BIT_USB_MBIST_DONE_8197F(v))
+
+#define BIT_SHIFT_PCIE_MBIST_DONE_8197F 16
+#define BIT_MASK_PCIE_MBIST_DONE_8197F 0x3f
+#define BIT_PCIE_MBIST_DONE_8197F(x)                                           \
+	(((x) & BIT_MASK_PCIE_MBIST_DONE_8197F)                                \
+	 << BIT_SHIFT_PCIE_MBIST_DONE_8197F)
+#define BITS_PCIE_MBIST_DONE_8197F                                             \
+	(BIT_MASK_PCIE_MBIST_DONE_8197F << BIT_SHIFT_PCIE_MBIST_DONE_8197F)
+#define BIT_CLEAR_PCIE_MBIST_DONE_8197F(x) ((x) & (~BITS_PCIE_MBIST_DONE_8197F))
+#define BIT_GET_PCIE_MBIST_DONE_8197F(x)                                       \
+	(((x) >> BIT_SHIFT_PCIE_MBIST_DONE_8197F) &                            \
+	 BIT_MASK_PCIE_MBIST_DONE_8197F)
+#define BIT_SET_PCIE_MBIST_DONE_8197F(x, v)                                    \
+	(BIT_CLEAR_PCIE_MBIST_DONE_8197F(x) | BIT_PCIE_MBIST_DONE_8197F(v))
+
+#define BIT_SHIFT_MAC_MBIST_DONE_V1_8197F 0
+#define BIT_MASK_MAC_MBIST_DONE_V1_8197F 0x3ffff
+#define BIT_MAC_MBIST_DONE_V1_8197F(x)                                         \
+	(((x) & BIT_MASK_MAC_MBIST_DONE_V1_8197F)                              \
+	 << BIT_SHIFT_MAC_MBIST_DONE_V1_8197F)
+#define BITS_MAC_MBIST_DONE_V1_8197F                                           \
+	(BIT_MASK_MAC_MBIST_DONE_V1_8197F << BIT_SHIFT_MAC_MBIST_DONE_V1_8197F)
+#define BIT_CLEAR_MAC_MBIST_DONE_V1_8197F(x)                                   \
+	((x) & (~BITS_MAC_MBIST_DONE_V1_8197F))
+#define BIT_GET_MAC_MBIST_DONE_V1_8197F(x)                                     \
+	(((x) >> BIT_SHIFT_MAC_MBIST_DONE_V1_8197F) &                          \
+	 BIT_MASK_MAC_MBIST_DONE_V1_8197F)
+#define BIT_SET_MAC_MBIST_DONE_V1_8197F(x, v)                                  \
+	(BIT_CLEAR_MAC_MBIST_DONE_V1_8197F(x) | BIT_MAC_MBIST_DONE_V1_8197F(v))
+
+/* 2 REG_MBIST_FAIL_NRML_8197F */
+
+#define BIT_SHIFT_MBIST_FAIL_NRML_V1_8197F 0
+#define BIT_MASK_MBIST_FAIL_NRML_V1_8197F 0x3ffff
+#define BIT_MBIST_FAIL_NRML_V1_8197F(x)                                        \
+	(((x) & BIT_MASK_MBIST_FAIL_NRML_V1_8197F)                             \
+	 << BIT_SHIFT_MBIST_FAIL_NRML_V1_8197F)
+#define BITS_MBIST_FAIL_NRML_V1_8197F                                          \
+	(BIT_MASK_MBIST_FAIL_NRML_V1_8197F                                     \
+	 << BIT_SHIFT_MBIST_FAIL_NRML_V1_8197F)
+#define BIT_CLEAR_MBIST_FAIL_NRML_V1_8197F(x)                                  \
+	((x) & (~BITS_MBIST_FAIL_NRML_V1_8197F))
+#define BIT_GET_MBIST_FAIL_NRML_V1_8197F(x)                                    \
+	(((x) >> BIT_SHIFT_MBIST_FAIL_NRML_V1_8197F) &                         \
+	 BIT_MASK_MBIST_FAIL_NRML_V1_8197F)
+#define BIT_SET_MBIST_FAIL_NRML_V1_8197F(x, v)                                 \
+	(BIT_CLEAR_MBIST_FAIL_NRML_V1_8197F(x) |                               \
+	 BIT_MBIST_FAIL_NRML_V1_8197F(v))
+
+/* 2 REG_AES_DECRPT_DATA_8197F */
+
+#define BIT_SHIFT_IPS_CFG_ADDR_8197F 0
+#define BIT_MASK_IPS_CFG_ADDR_8197F 0xff
+#define BIT_IPS_CFG_ADDR_8197F(x)                                              \
+	(((x) & BIT_MASK_IPS_CFG_ADDR_8197F) << BIT_SHIFT_IPS_CFG_ADDR_8197F)
+#define BITS_IPS_CFG_ADDR_8197F                                                \
+	(BIT_MASK_IPS_CFG_ADDR_8197F << BIT_SHIFT_IPS_CFG_ADDR_8197F)
+#define BIT_CLEAR_IPS_CFG_ADDR_8197F(x) ((x) & (~BITS_IPS_CFG_ADDR_8197F))
+#define BIT_GET_IPS_CFG_ADDR_8197F(x)                                          \
+	(((x) >> BIT_SHIFT_IPS_CFG_ADDR_8197F) & BIT_MASK_IPS_CFG_ADDR_8197F)
+#define BIT_SET_IPS_CFG_ADDR_8197F(x, v)                                       \
+	(BIT_CLEAR_IPS_CFG_ADDR_8197F(x) | BIT_IPS_CFG_ADDR_8197F(v))
+
+/* 2 REG_AES_DECRPT_CFG_8197F */
+
+#define BIT_SHIFT_IPS_CFG_DATA_8197F 0
+#define BIT_MASK_IPS_CFG_DATA_8197F 0xffffffffL
+#define BIT_IPS_CFG_DATA_8197F(x)                                              \
+	(((x) & BIT_MASK_IPS_CFG_DATA_8197F) << BIT_SHIFT_IPS_CFG_DATA_8197F)
+#define BITS_IPS_CFG_DATA_8197F                                                \
+	(BIT_MASK_IPS_CFG_DATA_8197F << BIT_SHIFT_IPS_CFG_DATA_8197F)
+#define BIT_CLEAR_IPS_CFG_DATA_8197F(x) ((x) & (~BITS_IPS_CFG_DATA_8197F))
+#define BIT_GET_IPS_CFG_DATA_8197F(x)                                          \
+	(((x) >> BIT_SHIFT_IPS_CFG_DATA_8197F) & BIT_MASK_IPS_CFG_DATA_8197F)
+#define BIT_SET_IPS_CFG_DATA_8197F(x, v)                                       \
+	(BIT_CLEAR_IPS_CFG_DATA_8197F(x) | BIT_IPS_CFG_DATA_8197F(v))
+
+/* 2 REG_NOT_VALID_8197F */
+
+/* 2 REG_MACCLKFRQ_8197F */
+
+#define BIT_SHIFT_MACCLK_FREQ_LOW32_8197F 0
+#define BIT_MASK_MACCLK_FREQ_LOW32_8197F 0xffffffffL
+#define BIT_MACCLK_FREQ_LOW32_8197F(x)                                         \
+	(((x) & BIT_MASK_MACCLK_FREQ_LOW32_8197F)                              \
+	 << BIT_SHIFT_MACCLK_FREQ_LOW32_8197F)
+#define BITS_MACCLK_FREQ_LOW32_8197F                                           \
+	(BIT_MASK_MACCLK_FREQ_LOW32_8197F << BIT_SHIFT_MACCLK_FREQ_LOW32_8197F)
+#define BIT_CLEAR_MACCLK_FREQ_LOW32_8197F(x)                                   \
+	((x) & (~BITS_MACCLK_FREQ_LOW32_8197F))
+#define BIT_GET_MACCLK_FREQ_LOW32_8197F(x)                                     \
+	(((x) >> BIT_SHIFT_MACCLK_FREQ_LOW32_8197F) &                          \
+	 BIT_MASK_MACCLK_FREQ_LOW32_8197F)
+#define BIT_SET_MACCLK_FREQ_LOW32_8197F(x, v)                                  \
+	(BIT_CLEAR_MACCLK_FREQ_LOW32_8197F(x) | BIT_MACCLK_FREQ_LOW32_8197F(v))
+
+/* 2 REG_TMETER_8197F */
+
+#define BIT_SHIFT_MACCLK_FREQ_HIGH10_8197F 0
+#define BIT_MASK_MACCLK_FREQ_HIGH10_8197F 0x3ff
+#define BIT_MACCLK_FREQ_HIGH10_8197F(x)                                        \
+	(((x) & BIT_MASK_MACCLK_FREQ_HIGH10_8197F)                             \
+	 << BIT_SHIFT_MACCLK_FREQ_HIGH10_8197F)
+#define BITS_MACCLK_FREQ_HIGH10_8197F                                          \
+	(BIT_MASK_MACCLK_FREQ_HIGH10_8197F                                     \
+	 << BIT_SHIFT_MACCLK_FREQ_HIGH10_8197F)
+#define BIT_CLEAR_MACCLK_FREQ_HIGH10_8197F(x)                                  \
+	((x) & (~BITS_MACCLK_FREQ_HIGH10_8197F))
+#define BIT_GET_MACCLK_FREQ_HIGH10_8197F(x)                                    \
+	(((x) >> BIT_SHIFT_MACCLK_FREQ_HIGH10_8197F) &                         \
+	 BIT_MASK_MACCLK_FREQ_HIGH10_8197F)
+#define BIT_SET_MACCLK_FREQ_HIGH10_8197F(x, v)                                 \
+	(BIT_CLEAR_MACCLK_FREQ_HIGH10_8197F(x) |                               \
+	 BIT_MACCLK_FREQ_HIGH10_8197F(v))
+
+/* 2 REG_OSC_32K_CTRL_8197F */
+#define BIT_32K_CLK_OUT_RDY_8197F BIT(12)
+
+#define BIT_SHIFT_MONITOR_CYCLE_LOG2_8197F 8
+#define BIT_MASK_MONITOR_CYCLE_LOG2_8197F 0xf
+#define BIT_MONITOR_CYCLE_LOG2_8197F(x)                                        \
+	(((x) & BIT_MASK_MONITOR_CYCLE_LOG2_8197F)                             \
+	 << BIT_SHIFT_MONITOR_CYCLE_LOG2_8197F)
+#define BITS_MONITOR_CYCLE_LOG2_8197F                                          \
+	(BIT_MASK_MONITOR_CYCLE_LOG2_8197F                                     \
+	 << BIT_SHIFT_MONITOR_CYCLE_LOG2_8197F)
+#define BIT_CLEAR_MONITOR_CYCLE_LOG2_8197F(x)                                  \
+	((x) & (~BITS_MONITOR_CYCLE_LOG2_8197F))
+#define BIT_GET_MONITOR_CYCLE_LOG2_8197F(x)                                    \
+	(((x) >> BIT_SHIFT_MONITOR_CYCLE_LOG2_8197F) &                         \
+	 BIT_MASK_MONITOR_CYCLE_LOG2_8197F)
+#define BIT_SET_MONITOR_CYCLE_LOG2_8197F(x, v)                                 \
+	(BIT_CLEAR_MONITOR_CYCLE_LOG2_8197F(x) |                               \
+	 BIT_MONITOR_CYCLE_LOG2_8197F(v))
+
+/* 2 REG_32K_CAL_REG1_8197F */
+
+#define BIT_SHIFT_FREQVALUE_UNREGCLK_8197F 8
+#define BIT_MASK_FREQVALUE_UNREGCLK_8197F 0xffffff
+#define BIT_FREQVALUE_UNREGCLK_8197F(x)                                        \
+	(((x) & BIT_MASK_FREQVALUE_UNREGCLK_8197F)                             \
+	 << BIT_SHIFT_FREQVALUE_UNREGCLK_8197F)
+#define BITS_FREQVALUE_UNREGCLK_8197F                                          \
+	(BIT_MASK_FREQVALUE_UNREGCLK_8197F                                     \
+	 << BIT_SHIFT_FREQVALUE_UNREGCLK_8197F)
+#define BIT_CLEAR_FREQVALUE_UNREGCLK_8197F(x)                                  \
+	((x) & (~BITS_FREQVALUE_UNREGCLK_8197F))
+#define BIT_GET_FREQVALUE_UNREGCLK_8197F(x)                                    \
+	(((x) >> BIT_SHIFT_FREQVALUE_UNREGCLK_8197F) &                         \
+	 BIT_MASK_FREQVALUE_UNREGCLK_8197F)
+#define BIT_SET_FREQVALUE_UNREGCLK_8197F(x, v)                                 \
+	(BIT_CLEAR_FREQVALUE_UNREGCLK_8197F(x) |                               \
+	 BIT_FREQVALUE_UNREGCLK_8197F(v))
+
+#define BIT_CAL32K_DBGMOD_8197F BIT(7)
+
+#define BIT_SHIFT_NCO_THRS_8197F 0
+#define BIT_MASK_NCO_THRS_8197F 0x7f
+#define BIT_NCO_THRS_8197F(x)                                                  \
+	(((x) & BIT_MASK_NCO_THRS_8197F) << BIT_SHIFT_NCO_THRS_8197F)
+#define BITS_NCO_THRS_8197F                                                    \
+	(BIT_MASK_NCO_THRS_8197F << BIT_SHIFT_NCO_THRS_8197F)
+#define BIT_CLEAR_NCO_THRS_8197F(x) ((x) & (~BITS_NCO_THRS_8197F))
+#define BIT_GET_NCO_THRS_8197F(x)                                              \
+	(((x) >> BIT_SHIFT_NCO_THRS_8197F) & BIT_MASK_NCO_THRS_8197F)
+#define BIT_SET_NCO_THRS_8197F(x, v)                                           \
+	(BIT_CLEAR_NCO_THRS_8197F(x) | BIT_NCO_THRS_8197F(v))
+
+/* 2 REG_NOT_VALID_8197F */
+
+/* 2 REG_C2HEVT_8197F */
+
+#define BIT_SHIFT_C2HEVT_MSG_8197F 0
+#define BIT_MASK_C2HEVT_MSG_8197F 0xffffffffffffffffffffffffffffffffL
+#define BIT_C2HEVT_MSG_8197F(x)                                                \
+	(((x) & BIT_MASK_C2HEVT_MSG_8197F) << BIT_SHIFT_C2HEVT_MSG_8197F)
+#define BITS_C2HEVT_MSG_8197F                                                  \
+	(BIT_MASK_C2HEVT_MSG_8197F << BIT_SHIFT_C2HEVT_MSG_8197F)
+#define BIT_CLEAR_C2HEVT_MSG_8197F(x) ((x) & (~BITS_C2HEVT_MSG_8197F))
+#define BIT_GET_C2HEVT_MSG_8197F(x)                                            \
+	(((x) >> BIT_SHIFT_C2HEVT_MSG_8197F) & BIT_MASK_C2HEVT_MSG_8197F)
+#define BIT_SET_C2HEVT_MSG_8197F(x, v)                                         \
+	(BIT_CLEAR_C2HEVT_MSG_8197F(x) | BIT_C2HEVT_MSG_8197F(v))
+
+/* 2 REG_SW_DEFINED_PAGE1_8197F */
+
+#define BIT_SHIFT_SW_DEFINED_PAGE1_8197F 0
+#define BIT_MASK_SW_DEFINED_PAGE1_8197F 0xffffffffffffffffL
+#define BIT_SW_DEFINED_PAGE1_8197F(x)                                          \
+	(((x) & BIT_MASK_SW_DEFINED_PAGE1_8197F)                               \
+	 << BIT_SHIFT_SW_DEFINED_PAGE1_8197F)
+#define BITS_SW_DEFINED_PAGE1_8197F                                            \
+	(BIT_MASK_SW_DEFINED_PAGE1_8197F << BIT_SHIFT_SW_DEFINED_PAGE1_8197F)
+#define BIT_CLEAR_SW_DEFINED_PAGE1_8197F(x)                                    \
+	((x) & (~BITS_SW_DEFINED_PAGE1_8197F))
+#define BIT_GET_SW_DEFINED_PAGE1_8197F(x)                                      \
+	(((x) >> BIT_SHIFT_SW_DEFINED_PAGE1_8197F) &                           \
+	 BIT_MASK_SW_DEFINED_PAGE1_8197F)
+#define BIT_SET_SW_DEFINED_PAGE1_8197F(x, v)                                   \
+	(BIT_CLEAR_SW_DEFINED_PAGE1_8197F(x) | BIT_SW_DEFINED_PAGE1_8197F(v))
+
+/* 2 REG_MCUTST_I_8197F */
+
+#define BIT_SHIFT_MCUDMSG_I_8197F 0
+#define BIT_MASK_MCUDMSG_I_8197F 0xffffffffL
+#define BIT_MCUDMSG_I_8197F(x)                                                 \
+	(((x) & BIT_MASK_MCUDMSG_I_8197F) << BIT_SHIFT_MCUDMSG_I_8197F)
+#define BITS_MCUDMSG_I_8197F                                                   \
+	(BIT_MASK_MCUDMSG_I_8197F << BIT_SHIFT_MCUDMSG_I_8197F)
+#define BIT_CLEAR_MCUDMSG_I_8197F(x) ((x) & (~BITS_MCUDMSG_I_8197F))
+#define BIT_GET_MCUDMSG_I_8197F(x)                                             \
+	(((x) >> BIT_SHIFT_MCUDMSG_I_8197F) & BIT_MASK_MCUDMSG_I_8197F)
+#define BIT_SET_MCUDMSG_I_8197F(x, v)                                          \
+	(BIT_CLEAR_MCUDMSG_I_8197F(x) | BIT_MCUDMSG_I_8197F(v))
+
+/* 2 REG_MCUTST_II_8197F */
+
+#define BIT_SHIFT_MCUDMSG_II_8197F 0
+#define BIT_MASK_MCUDMSG_II_8197F 0xffffffffL
+#define BIT_MCUDMSG_II_8197F(x)                                                \
+	(((x) & BIT_MASK_MCUDMSG_II_8197F) << BIT_SHIFT_MCUDMSG_II_8197F)
+#define BITS_MCUDMSG_II_8197F                                                  \
+	(BIT_MASK_MCUDMSG_II_8197F << BIT_SHIFT_MCUDMSG_II_8197F)
+#define BIT_CLEAR_MCUDMSG_II_8197F(x) ((x) & (~BITS_MCUDMSG_II_8197F))
+#define BIT_GET_MCUDMSG_II_8197F(x)                                            \
+	(((x) >> BIT_SHIFT_MCUDMSG_II_8197F) & BIT_MASK_MCUDMSG_II_8197F)
+#define BIT_SET_MCUDMSG_II_8197F(x, v)                                         \
+	(BIT_CLEAR_MCUDMSG_II_8197F(x) | BIT_MCUDMSG_II_8197F(v))
+
+/* 2 REG_FMETHR_8197F */
+#define BIT_FMSG_INT_8197F BIT(31)
+
+#define BIT_SHIFT_FW_MSG_8197F 0
+#define BIT_MASK_FW_MSG_8197F 0xffffffffL
+#define BIT_FW_MSG_8197F(x)                                                    \
+	(((x) & BIT_MASK_FW_MSG_8197F) << BIT_SHIFT_FW_MSG_8197F)
+#define BITS_FW_MSG_8197F (BIT_MASK_FW_MSG_8197F << BIT_SHIFT_FW_MSG_8197F)
+#define BIT_CLEAR_FW_MSG_8197F(x) ((x) & (~BITS_FW_MSG_8197F))
+#define BIT_GET_FW_MSG_8197F(x)                                                \
+	(((x) >> BIT_SHIFT_FW_MSG_8197F) & BIT_MASK_FW_MSG_8197F)
+#define BIT_SET_FW_MSG_8197F(x, v)                                             \
+	(BIT_CLEAR_FW_MSG_8197F(x) | BIT_FW_MSG_8197F(v))
+
+/* 2 REG_HMETFR_8197F */
+
+#define BIT_SHIFT_HRCV_MSG_8197F 24
+#define BIT_MASK_HRCV_MSG_8197F 0xff
+#define BIT_HRCV_MSG_8197F(x)                                                  \
+	(((x) & BIT_MASK_HRCV_MSG_8197F) << BIT_SHIFT_HRCV_MSG_8197F)
+#define BITS_HRCV_MSG_8197F                                                    \
+	(BIT_MASK_HRCV_MSG_8197F << BIT_SHIFT_HRCV_MSG_8197F)
+#define BIT_CLEAR_HRCV_MSG_8197F(x) ((x) & (~BITS_HRCV_MSG_8197F))
+#define BIT_GET_HRCV_MSG_8197F(x)                                              \
+	(((x) >> BIT_SHIFT_HRCV_MSG_8197F) & BIT_MASK_HRCV_MSG_8197F)
+#define BIT_SET_HRCV_MSG_8197F(x, v)                                           \
+	(BIT_CLEAR_HRCV_MSG_8197F(x) | BIT_HRCV_MSG_8197F(v))
+
+#define BIT_INT_BOX3_8197F BIT(3)
+#define BIT_INT_BOX2_8197F BIT(2)
+#define BIT_INT_BOX1_8197F BIT(1)
+#define BIT_INT_BOX0_8197F BIT(0)
+
+/* 2 REG_HMEBOX0_8197F */
+
+#define BIT_SHIFT_HOST_MSG_0_8197F 0
+#define BIT_MASK_HOST_MSG_0_8197F 0xffffffffL
+#define BIT_HOST_MSG_0_8197F(x)                                                \
+	(((x) & BIT_MASK_HOST_MSG_0_8197F) << BIT_SHIFT_HOST_MSG_0_8197F)
+#define BITS_HOST_MSG_0_8197F                                                  \
+	(BIT_MASK_HOST_MSG_0_8197F << BIT_SHIFT_HOST_MSG_0_8197F)
+#define BIT_CLEAR_HOST_MSG_0_8197F(x) ((x) & (~BITS_HOST_MSG_0_8197F))
+#define BIT_GET_HOST_MSG_0_8197F(x)                                            \
+	(((x) >> BIT_SHIFT_HOST_MSG_0_8197F) & BIT_MASK_HOST_MSG_0_8197F)
+#define BIT_SET_HOST_MSG_0_8197F(x, v)                                         \
+	(BIT_CLEAR_HOST_MSG_0_8197F(x) | BIT_HOST_MSG_0_8197F(v))
+
+/* 2 REG_HMEBOX1_8197F */
+
+#define BIT_SHIFT_HOST_MSG_1_8197F 0
+#define BIT_MASK_HOST_MSG_1_8197F 0xffffffffL
+#define BIT_HOST_MSG_1_8197F(x)                                                \
+	(((x) & BIT_MASK_HOST_MSG_1_8197F) << BIT_SHIFT_HOST_MSG_1_8197F)
+#define BITS_HOST_MSG_1_8197F                                                  \
+	(BIT_MASK_HOST_MSG_1_8197F << BIT_SHIFT_HOST_MSG_1_8197F)
+#define BIT_CLEAR_HOST_MSG_1_8197F(x) ((x) & (~BITS_HOST_MSG_1_8197F))
+#define BIT_GET_HOST_MSG_1_8197F(x)                                            \
+	(((x) >> BIT_SHIFT_HOST_MSG_1_8197F) & BIT_MASK_HOST_MSG_1_8197F)
+#define BIT_SET_HOST_MSG_1_8197F(x, v)                                         \
+	(BIT_CLEAR_HOST_MSG_1_8197F(x) | BIT_HOST_MSG_1_8197F(v))
+
+/* 2 REG_HMEBOX2_8197F */
+
+#define BIT_SHIFT_HOST_MSG_2_8197F 0
+#define BIT_MASK_HOST_MSG_2_8197F 0xffffffffL
+#define BIT_HOST_MSG_2_8197F(x)                                                \
+	(((x) & BIT_MASK_HOST_MSG_2_8197F) << BIT_SHIFT_HOST_MSG_2_8197F)
+#define BITS_HOST_MSG_2_8197F                                                  \
+	(BIT_MASK_HOST_MSG_2_8197F << BIT_SHIFT_HOST_MSG_2_8197F)
+#define BIT_CLEAR_HOST_MSG_2_8197F(x) ((x) & (~BITS_HOST_MSG_2_8197F))
+#define BIT_GET_HOST_MSG_2_8197F(x)                                            \
+	(((x) >> BIT_SHIFT_HOST_MSG_2_8197F) & BIT_MASK_HOST_MSG_2_8197F)
+#define BIT_SET_HOST_MSG_2_8197F(x, v)                                         \
+	(BIT_CLEAR_HOST_MSG_2_8197F(x) | BIT_HOST_MSG_2_8197F(v))
+
+/* 2 REG_HMEBOX3_8197F */
+
+#define BIT_SHIFT_HOST_MSG_3_8197F 0
+#define BIT_MASK_HOST_MSG_3_8197F 0xffffffffL
+#define BIT_HOST_MSG_3_8197F(x)                                                \
+	(((x) & BIT_MASK_HOST_MSG_3_8197F) << BIT_SHIFT_HOST_MSG_3_8197F)
+#define BITS_HOST_MSG_3_8197F                                                  \
+	(BIT_MASK_HOST_MSG_3_8197F << BIT_SHIFT_HOST_MSG_3_8197F)
+#define BIT_CLEAR_HOST_MSG_3_8197F(x) ((x) & (~BITS_HOST_MSG_3_8197F))
+#define BIT_GET_HOST_MSG_3_8197F(x)                                            \
+	(((x) >> BIT_SHIFT_HOST_MSG_3_8197F) & BIT_MASK_HOST_MSG_3_8197F)
+#define BIT_SET_HOST_MSG_3_8197F(x, v)                                         \
+	(BIT_CLEAR_HOST_MSG_3_8197F(x) | BIT_HOST_MSG_3_8197F(v))
+
+/* 2 REG_LLT_INIT_8197F */
+
+#define BIT_SHIFT_LLTE_RWM_8197F 30
+#define BIT_MASK_LLTE_RWM_8197F 0x3
+#define BIT_LLTE_RWM_8197F(x)                                                  \
+	(((x) & BIT_MASK_LLTE_RWM_8197F) << BIT_SHIFT_LLTE_RWM_8197F)
+#define BITS_LLTE_RWM_8197F                                                    \
+	(BIT_MASK_LLTE_RWM_8197F << BIT_SHIFT_LLTE_RWM_8197F)
+#define BIT_CLEAR_LLTE_RWM_8197F(x) ((x) & (~BITS_LLTE_RWM_8197F))
+#define BIT_GET_LLTE_RWM_8197F(x)                                              \
+	(((x) >> BIT_SHIFT_LLTE_RWM_8197F) & BIT_MASK_LLTE_RWM_8197F)
+#define BIT_SET_LLTE_RWM_8197F(x, v)                                           \
+	(BIT_CLEAR_LLTE_RWM_8197F(x) | BIT_LLTE_RWM_8197F(v))
+
+#define BIT_SHIFT_LLTINI_PDATA_V1_8197F 16
+#define BIT_MASK_LLTINI_PDATA_V1_8197F 0xfff
+#define BIT_LLTINI_PDATA_V1_8197F(x)                                           \
+	(((x) & BIT_MASK_LLTINI_PDATA_V1_8197F)                                \
+	 << BIT_SHIFT_LLTINI_PDATA_V1_8197F)
+#define BITS_LLTINI_PDATA_V1_8197F                                             \
+	(BIT_MASK_LLTINI_PDATA_V1_8197F << BIT_SHIFT_LLTINI_PDATA_V1_8197F)
+#define BIT_CLEAR_LLTINI_PDATA_V1_8197F(x) ((x) & (~BITS_LLTINI_PDATA_V1_8197F))
+#define BIT_GET_LLTINI_PDATA_V1_8197F(x)                                       \
+	(((x) >> BIT_SHIFT_LLTINI_PDATA_V1_8197F) &                            \
+	 BIT_MASK_LLTINI_PDATA_V1_8197F)
+#define BIT_SET_LLTINI_PDATA_V1_8197F(x, v)                                    \
+	(BIT_CLEAR_LLTINI_PDATA_V1_8197F(x) | BIT_LLTINI_PDATA_V1_8197F(v))
+
+#define BIT_SHIFT_LLTINI_HDATA_V1_8197F 0
+#define BIT_MASK_LLTINI_HDATA_V1_8197F 0xfff
+#define BIT_LLTINI_HDATA_V1_8197F(x)                                           \
+	(((x) & BIT_MASK_LLTINI_HDATA_V1_8197F)                                \
+	 << BIT_SHIFT_LLTINI_HDATA_V1_8197F)
+#define BITS_LLTINI_HDATA_V1_8197F                                             \
+	(BIT_MASK_LLTINI_HDATA_V1_8197F << BIT_SHIFT_LLTINI_HDATA_V1_8197F)
+#define BIT_CLEAR_LLTINI_HDATA_V1_8197F(x) ((x) & (~BITS_LLTINI_HDATA_V1_8197F))
+#define BIT_GET_LLTINI_HDATA_V1_8197F(x)                                       \
+	(((x) >> BIT_SHIFT_LLTINI_HDATA_V1_8197F) &                            \
+	 BIT_MASK_LLTINI_HDATA_V1_8197F)
+#define BIT_SET_LLTINI_HDATA_V1_8197F(x, v)                                    \
+	(BIT_CLEAR_LLTINI_HDATA_V1_8197F(x) | BIT_LLTINI_HDATA_V1_8197F(v))
+
+/* 2 REG_LLT_INIT_ADDR_8197F */
+
+#define BIT_SHIFT_LLTINI_ADDR_V1_8197F 0
+#define BIT_MASK_LLTINI_ADDR_V1_8197F 0xfff
+#define BIT_LLTINI_ADDR_V1_8197F(x)                                            \
+	(((x) & BIT_MASK_LLTINI_ADDR_V1_8197F)                                 \
+	 << BIT_SHIFT_LLTINI_ADDR_V1_8197F)
+#define BITS_LLTINI_ADDR_V1_8197F                                              \
+	(BIT_MASK_LLTINI_ADDR_V1_8197F << BIT_SHIFT_LLTINI_ADDR_V1_8197F)
+#define BIT_CLEAR_LLTINI_ADDR_V1_8197F(x) ((x) & (~BITS_LLTINI_ADDR_V1_8197F))
+#define BIT_GET_LLTINI_ADDR_V1_8197F(x)                                        \
+	(((x) >> BIT_SHIFT_LLTINI_ADDR_V1_8197F) &                             \
+	 BIT_MASK_LLTINI_ADDR_V1_8197F)
+#define BIT_SET_LLTINI_ADDR_V1_8197F(x, v)                                     \
+	(BIT_CLEAR_LLTINI_ADDR_V1_8197F(x) | BIT_LLTINI_ADDR_V1_8197F(v))
+
+/* 2 REG_BB_ACCESS_CTRL_8197F */
+
+#define BIT_SHIFT_BB_WRITE_READ_8197F 30
+#define BIT_MASK_BB_WRITE_READ_8197F 0x3
+#define BIT_BB_WRITE_READ_8197F(x)                                             \
+	(((x) & BIT_MASK_BB_WRITE_READ_8197F) << BIT_SHIFT_BB_WRITE_READ_8197F)
+#define BITS_BB_WRITE_READ_8197F                                               \
+	(BIT_MASK_BB_WRITE_READ_8197F << BIT_SHIFT_BB_WRITE_READ_8197F)
+#define BIT_CLEAR_BB_WRITE_READ_8197F(x) ((x) & (~BITS_BB_WRITE_READ_8197F))
+#define BIT_GET_BB_WRITE_READ_8197F(x)                                         \
+	(((x) >> BIT_SHIFT_BB_WRITE_READ_8197F) & BIT_MASK_BB_WRITE_READ_8197F)
+#define BIT_SET_BB_WRITE_READ_8197F(x, v)                                      \
+	(BIT_CLEAR_BB_WRITE_READ_8197F(x) | BIT_BB_WRITE_READ_8197F(v))
+
+#define BIT_SHIFT_BB_WRITE_EN_V1_8197F 16
+#define BIT_MASK_BB_WRITE_EN_V1_8197F 0xf
+#define BIT_BB_WRITE_EN_V1_8197F(x)                                            \
+	(((x) & BIT_MASK_BB_WRITE_EN_V1_8197F)                                 \
+	 << BIT_SHIFT_BB_WRITE_EN_V1_8197F)
+#define BITS_BB_WRITE_EN_V1_8197F                                              \
+	(BIT_MASK_BB_WRITE_EN_V1_8197F << BIT_SHIFT_BB_WRITE_EN_V1_8197F)
+#define BIT_CLEAR_BB_WRITE_EN_V1_8197F(x) ((x) & (~BITS_BB_WRITE_EN_V1_8197F))
+#define BIT_GET_BB_WRITE_EN_V1_8197F(x)                                        \
+	(((x) >> BIT_SHIFT_BB_WRITE_EN_V1_8197F) &                             \
+	 BIT_MASK_BB_WRITE_EN_V1_8197F)
+#define BIT_SET_BB_WRITE_EN_V1_8197F(x, v)                                     \
+	(BIT_CLEAR_BB_WRITE_EN_V1_8197F(x) | BIT_BB_WRITE_EN_V1_8197F(v))
+
+#define BIT_SHIFT_BB_ADDR_V1_8197F 2
+#define BIT_MASK_BB_ADDR_V1_8197F 0xfff
+#define BIT_BB_ADDR_V1_8197F(x)                                                \
+	(((x) & BIT_MASK_BB_ADDR_V1_8197F) << BIT_SHIFT_BB_ADDR_V1_8197F)
+#define BITS_BB_ADDR_V1_8197F                                                  \
+	(BIT_MASK_BB_ADDR_V1_8197F << BIT_SHIFT_BB_ADDR_V1_8197F)
+#define BIT_CLEAR_BB_ADDR_V1_8197F(x) ((x) & (~BITS_BB_ADDR_V1_8197F))
+#define BIT_GET_BB_ADDR_V1_8197F(x)                                            \
+	(((x) >> BIT_SHIFT_BB_ADDR_V1_8197F) & BIT_MASK_BB_ADDR_V1_8197F)
+#define BIT_SET_BB_ADDR_V1_8197F(x, v)                                         \
+	(BIT_CLEAR_BB_ADDR_V1_8197F(x) | BIT_BB_ADDR_V1_8197F(v))
+
+#define BIT_BB_ERRACC_8197F BIT(0)
+
+/* 2 REG_BB_ACCESS_DATA_8197F */
+
+#define BIT_SHIFT_BB_DATA_8197F 0
+#define BIT_MASK_BB_DATA_8197F 0xffffffffL
+#define BIT_BB_DATA_8197F(x)                                                   \
+	(((x) & BIT_MASK_BB_DATA_8197F) << BIT_SHIFT_BB_DATA_8197F)
+#define BITS_BB_DATA_8197F (BIT_MASK_BB_DATA_8197F << BIT_SHIFT_BB_DATA_8197F)
+#define BIT_CLEAR_BB_DATA_8197F(x) ((x) & (~BITS_BB_DATA_8197F))
+#define BIT_GET_BB_DATA_8197F(x)                                               \
+	(((x) >> BIT_SHIFT_BB_DATA_8197F) & BIT_MASK_BB_DATA_8197F)
+#define BIT_SET_BB_DATA_8197F(x, v)                                            \
+	(BIT_CLEAR_BB_DATA_8197F(x) | BIT_BB_DATA_8197F(v))
+
+/* 2 REG_HMEBOX_E0_8197F */
+
+#define BIT_SHIFT_HMEBOX_E0_8197F 0
+#define BIT_MASK_HMEBOX_E0_8197F 0xffffffffL
+#define BIT_HMEBOX_E0_8197F(x)                                                 \
+	(((x) & BIT_MASK_HMEBOX_E0_8197F) << BIT_SHIFT_HMEBOX_E0_8197F)
+#define BITS_HMEBOX_E0_8197F                                                   \
+	(BIT_MASK_HMEBOX_E0_8197F << BIT_SHIFT_HMEBOX_E0_8197F)
+#define BIT_CLEAR_HMEBOX_E0_8197F(x) ((x) & (~BITS_HMEBOX_E0_8197F))
+#define BIT_GET_HMEBOX_E0_8197F(x)                                             \
+	(((x) >> BIT_SHIFT_HMEBOX_E0_8197F) & BIT_MASK_HMEBOX_E0_8197F)
+#define BIT_SET_HMEBOX_E0_8197F(x, v)                                          \
+	(BIT_CLEAR_HMEBOX_E0_8197F(x) | BIT_HMEBOX_E0_8197F(v))
+
+/* 2 REG_HMEBOX_E1_8197F */
+
+#define BIT_SHIFT_HMEBOX_E1_8197F 0
+#define BIT_MASK_HMEBOX_E1_8197F 0xffffffffL
+#define BIT_HMEBOX_E1_8197F(x)                                                 \
+	(((x) & BIT_MASK_HMEBOX_E1_8197F) << BIT_SHIFT_HMEBOX_E1_8197F)
+#define BITS_HMEBOX_E1_8197F                                                   \
+	(BIT_MASK_HMEBOX_E1_8197F << BIT_SHIFT_HMEBOX_E1_8197F)
+#define BIT_CLEAR_HMEBOX_E1_8197F(x) ((x) & (~BITS_HMEBOX_E1_8197F))
+#define BIT_GET_HMEBOX_E1_8197F(x)                                             \
+	(((x) >> BIT_SHIFT_HMEBOX_E1_8197F) & BIT_MASK_HMEBOX_E1_8197F)
+#define BIT_SET_HMEBOX_E1_8197F(x, v)                                          \
+	(BIT_CLEAR_HMEBOX_E1_8197F(x) | BIT_HMEBOX_E1_8197F(v))
+
+/* 2 REG_HMEBOX_E2_8197F */
+
+#define BIT_SHIFT_HMEBOX_E2_8197F 0
+#define BIT_MASK_HMEBOX_E2_8197F 0xffffffffL
+#define BIT_HMEBOX_E2_8197F(x)                                                 \
+	(((x) & BIT_MASK_HMEBOX_E2_8197F) << BIT_SHIFT_HMEBOX_E2_8197F)
+#define BITS_HMEBOX_E2_8197F                                                   \
+	(BIT_MASK_HMEBOX_E2_8197F << BIT_SHIFT_HMEBOX_E2_8197F)
+#define BIT_CLEAR_HMEBOX_E2_8197F(x) ((x) & (~BITS_HMEBOX_E2_8197F))
+#define BIT_GET_HMEBOX_E2_8197F(x)                                             \
+	(((x) >> BIT_SHIFT_HMEBOX_E2_8197F) & BIT_MASK_HMEBOX_E2_8197F)
+#define BIT_SET_HMEBOX_E2_8197F(x, v)                                          \
+	(BIT_CLEAR_HMEBOX_E2_8197F(x) | BIT_HMEBOX_E2_8197F(v))
+
+/* 2 REG_HMEBOX_E3_8197F */
+
+#define BIT_SHIFT_HMEBOX_E3_8197F 0
+#define BIT_MASK_HMEBOX_E3_8197F 0xffffffffL
+#define BIT_HMEBOX_E3_8197F(x)                                                 \
+	(((x) & BIT_MASK_HMEBOX_E3_8197F) << BIT_SHIFT_HMEBOX_E3_8197F)
+#define BITS_HMEBOX_E3_8197F                                                   \
+	(BIT_MASK_HMEBOX_E3_8197F << BIT_SHIFT_HMEBOX_E3_8197F)
+#define BIT_CLEAR_HMEBOX_E3_8197F(x) ((x) & (~BITS_HMEBOX_E3_8197F))
+#define BIT_GET_HMEBOX_E3_8197F(x)                                             \
+	(((x) >> BIT_SHIFT_HMEBOX_E3_8197F) & BIT_MASK_HMEBOX_E3_8197F)
+#define BIT_SET_HMEBOX_E3_8197F(x, v)                                          \
+	(BIT_CLEAR_HMEBOX_E3_8197F(x) | BIT_HMEBOX_E3_8197F(v))
+
+/* 2 REG_NOT_VALID_8197F */
+
+/* 2 REG_CR_EXT_8197F */
+
+#define BIT_SHIFT_PHY_REQ_DELAY_8197F 24
+#define BIT_MASK_PHY_REQ_DELAY_8197F 0xf
+#define BIT_PHY_REQ_DELAY_8197F(x)                                             \
+	(((x) & BIT_MASK_PHY_REQ_DELAY_8197F) << BIT_SHIFT_PHY_REQ_DELAY_8197F)
+#define BITS_PHY_REQ_DELAY_8197F                                               \
+	(BIT_MASK_PHY_REQ_DELAY_8197F << BIT_SHIFT_PHY_REQ_DELAY_8197F)
+#define BIT_CLEAR_PHY_REQ_DELAY_8197F(x) ((x) & (~BITS_PHY_REQ_DELAY_8197F))
+#define BIT_GET_PHY_REQ_DELAY_8197F(x)                                         \
+	(((x) >> BIT_SHIFT_PHY_REQ_DELAY_8197F) & BIT_MASK_PHY_REQ_DELAY_8197F)
+#define BIT_SET_PHY_REQ_DELAY_8197F(x, v)                                      \
+	(BIT_CLEAR_PHY_REQ_DELAY_8197F(x) | BIT_PHY_REQ_DELAY_8197F(v))
+
+#define BIT_SPD_DOWN_8197F BIT(16)
+
+#define BIT_SHIFT_NETYPE4_8197F 4
+#define BIT_MASK_NETYPE4_8197F 0x3
+#define BIT_NETYPE4_8197F(x)                                                   \
+	(((x) & BIT_MASK_NETYPE4_8197F) << BIT_SHIFT_NETYPE4_8197F)
+#define BITS_NETYPE4_8197F (BIT_MASK_NETYPE4_8197F << BIT_SHIFT_NETYPE4_8197F)
+#define BIT_CLEAR_NETYPE4_8197F(x) ((x) & (~BITS_NETYPE4_8197F))
+#define BIT_GET_NETYPE4_8197F(x)                                               \
+	(((x) >> BIT_SHIFT_NETYPE4_8197F) & BIT_MASK_NETYPE4_8197F)
+#define BIT_SET_NETYPE4_8197F(x, v)                                            \
+	(BIT_CLEAR_NETYPE4_8197F(x) | BIT_NETYPE4_8197F(v))
+
+#define BIT_SHIFT_NETYPE3_8197F 2
+#define BIT_MASK_NETYPE3_8197F 0x3
+#define BIT_NETYPE3_8197F(x)                                                   \
+	(((x) & BIT_MASK_NETYPE3_8197F) << BIT_SHIFT_NETYPE3_8197F)
+#define BITS_NETYPE3_8197F (BIT_MASK_NETYPE3_8197F << BIT_SHIFT_NETYPE3_8197F)
+#define BIT_CLEAR_NETYPE3_8197F(x) ((x) & (~BITS_NETYPE3_8197F))
+#define BIT_GET_NETYPE3_8197F(x)                                               \
+	(((x) >> BIT_SHIFT_NETYPE3_8197F) & BIT_MASK_NETYPE3_8197F)
+#define BIT_SET_NETYPE3_8197F(x, v)                                            \
+	(BIT_CLEAR_NETYPE3_8197F(x) | BIT_NETYPE3_8197F(v))
+
+#define BIT_SHIFT_NETYPE2_8197F 0
+#define BIT_MASK_NETYPE2_8197F 0x3
+#define BIT_NETYPE2_8197F(x)                                                   \
+	(((x) & BIT_MASK_NETYPE2_8197F) << BIT_SHIFT_NETYPE2_8197F)
+#define BITS_NETYPE2_8197F (BIT_MASK_NETYPE2_8197F << BIT_SHIFT_NETYPE2_8197F)
+#define BIT_CLEAR_NETYPE2_8197F(x) ((x) & (~BITS_NETYPE2_8197F))
+#define BIT_GET_NETYPE2_8197F(x)                                               \
+	(((x) >> BIT_SHIFT_NETYPE2_8197F) & BIT_MASK_NETYPE2_8197F)
+#define BIT_SET_NETYPE2_8197F(x, v)                                            \
+	(BIT_CLEAR_NETYPE2_8197F(x) | BIT_NETYPE2_8197F(v))
+
+/* 2 REG_FWFF_8197F */
+
+#define BIT_SHIFT_PKTNUM_TH_8197F 24
+#define BIT_MASK_PKTNUM_TH_8197F 0xff
+#define BIT_PKTNUM_TH_8197F(x)                                                 \
+	(((x) & BIT_MASK_PKTNUM_TH_8197F) << BIT_SHIFT_PKTNUM_TH_8197F)
+#define BITS_PKTNUM_TH_8197F                                                   \
+	(BIT_MASK_PKTNUM_TH_8197F << BIT_SHIFT_PKTNUM_TH_8197F)
+#define BIT_CLEAR_PKTNUM_TH_8197F(x) ((x) & (~BITS_PKTNUM_TH_8197F))
+#define BIT_GET_PKTNUM_TH_8197F(x)                                             \
+	(((x) >> BIT_SHIFT_PKTNUM_TH_8197F) & BIT_MASK_PKTNUM_TH_8197F)
+#define BIT_SET_PKTNUM_TH_8197F(x, v)                                          \
+	(BIT_CLEAR_PKTNUM_TH_8197F(x) | BIT_PKTNUM_TH_8197F(v))
+
+#define BIT_SHIFT_TIMER_TH_8197F 16
+#define BIT_MASK_TIMER_TH_8197F 0xff
+#define BIT_TIMER_TH_8197F(x)                                                  \
+	(((x) & BIT_MASK_TIMER_TH_8197F) << BIT_SHIFT_TIMER_TH_8197F)
+#define BITS_TIMER_TH_8197F                                                    \
+	(BIT_MASK_TIMER_TH_8197F << BIT_SHIFT_TIMER_TH_8197F)
+#define BIT_CLEAR_TIMER_TH_8197F(x) ((x) & (~BITS_TIMER_TH_8197F))
+#define BIT_GET_TIMER_TH_8197F(x)                                              \
+	(((x) >> BIT_SHIFT_TIMER_TH_8197F) & BIT_MASK_TIMER_TH_8197F)
+#define BIT_SET_TIMER_TH_8197F(x, v)                                           \
+	(BIT_CLEAR_TIMER_TH_8197F(x) | BIT_TIMER_TH_8197F(v))
+
+#define BIT_SHIFT_RXPKT1ENADDR_8197F 0
+#define BIT_MASK_RXPKT1ENADDR_8197F 0xffff
+#define BIT_RXPKT1ENADDR_8197F(x)                                              \
+	(((x) & BIT_MASK_RXPKT1ENADDR_8197F) << BIT_SHIFT_RXPKT1ENADDR_8197F)
+#define BITS_RXPKT1ENADDR_8197F                                                \
+	(BIT_MASK_RXPKT1ENADDR_8197F << BIT_SHIFT_RXPKT1ENADDR_8197F)
+#define BIT_CLEAR_RXPKT1ENADDR_8197F(x) ((x) & (~BITS_RXPKT1ENADDR_8197F))
+#define BIT_GET_RXPKT1ENADDR_8197F(x)                                          \
+	(((x) >> BIT_SHIFT_RXPKT1ENADDR_8197F) & BIT_MASK_RXPKT1ENADDR_8197F)
+#define BIT_SET_RXPKT1ENADDR_8197F(x, v)                                       \
+	(BIT_CLEAR_RXPKT1ENADDR_8197F(x) | BIT_RXPKT1ENADDR_8197F(v))
+
+/* 2 REG_RXFF_PTR_V1_8197F */
+
+/* 2 REG_NOT_VALID_8197F */
+
+#define BIT_SHIFT_RXFF0_RDPTR_V2_8197F 0
+#define BIT_MASK_RXFF0_RDPTR_V2_8197F 0x3ffff
+#define BIT_RXFF0_RDPTR_V2_8197F(x)                                            \
+	(((x) & BIT_MASK_RXFF0_RDPTR_V2_8197F)                                 \
+	 << BIT_SHIFT_RXFF0_RDPTR_V2_8197F)
+#define BITS_RXFF0_RDPTR_V2_8197F                                              \
+	(BIT_MASK_RXFF0_RDPTR_V2_8197F << BIT_SHIFT_RXFF0_RDPTR_V2_8197F)
+#define BIT_CLEAR_RXFF0_RDPTR_V2_8197F(x) ((x) & (~BITS_RXFF0_RDPTR_V2_8197F))
+#define BIT_GET_RXFF0_RDPTR_V2_8197F(x)                                        \
+	(((x) >> BIT_SHIFT_RXFF0_RDPTR_V2_8197F) &                             \
+	 BIT_MASK_RXFF0_RDPTR_V2_8197F)
+#define BIT_SET_RXFF0_RDPTR_V2_8197F(x, v)                                     \
+	(BIT_CLEAR_RXFF0_RDPTR_V2_8197F(x) | BIT_RXFF0_RDPTR_V2_8197F(v))
+
+/* 2 REG_RXFF_WTR_V1_8197F */
+
+/* 2 REG_NOT_VALID_8197F */
+
+#define BIT_SHIFT_RXFF0_WTPTR_V2_8197F 0
+#define BIT_MASK_RXFF0_WTPTR_V2_8197F 0x3ffff
+#define BIT_RXFF0_WTPTR_V2_8197F(x)                                            \
+	(((x) & BIT_MASK_RXFF0_WTPTR_V2_8197F)                                 \
+	 << BIT_SHIFT_RXFF0_WTPTR_V2_8197F)
+#define BITS_RXFF0_WTPTR_V2_8197F                                              \
+	(BIT_MASK_RXFF0_WTPTR_V2_8197F << BIT_SHIFT_RXFF0_WTPTR_V2_8197F)
+#define BIT_CLEAR_RXFF0_WTPTR_V2_8197F(x) ((x) & (~BITS_RXFF0_WTPTR_V2_8197F))
+#define BIT_GET_RXFF0_WTPTR_V2_8197F(x)                                        \
+	(((x) >> BIT_SHIFT_RXFF0_WTPTR_V2_8197F) &                             \
+	 BIT_MASK_RXFF0_WTPTR_V2_8197F)
+#define BIT_SET_RXFF0_WTPTR_V2_8197F(x, v)                                     \
+	(BIT_CLEAR_RXFF0_WTPTR_V2_8197F(x) | BIT_RXFF0_WTPTR_V2_8197F(v))
+
+/* 2 REG_FE2IMR_8197F */
+#define BIT_FS_TXSC_DESC_DONE_INT_EN_8197F BIT(28)
+#define BIT_FS_TXSC_BKDONE_INT_EN_8197F BIT(27)
+#define BIT_FS_TXSC_BEDONE_INT_EN_8197F BIT(26)
+#define BIT_FS_TXSC_VIDONE_INT_EN_8197F BIT(25)
+#define BIT_FS_TXSC_VODONE_INT_EN_8197F BIT(24)
+#define BIT_FS_ATIM_MB7_INT_EN_8197F BIT(23)
+#define BIT_FS_ATIM_MB6_INT_EN_8197F BIT(22)
+#define BIT_FS_ATIM_MB5_INT_EN_8197F BIT(21)
+#define BIT_FS_ATIM_MB4_INT_EN_8197F BIT(20)
+#define BIT_FS_ATIM_MB3_INT_EN_8197F BIT(19)
+#define BIT_FS_ATIM_MB2_INT_EN_8197F BIT(18)
+#define BIT_FS_ATIM_MB1_INT_EN_8197F BIT(17)
+#define BIT_FS_ATIM_MB0_INT_EN_8197F BIT(16)
+#define BIT_FS_TBTT4INT_EN_8197F BIT(11)
+#define BIT_FS_TBTT3INT_EN_8197F BIT(10)
+#define BIT_FS_TBTT2INT_EN_8197F BIT(9)
+#define BIT_FS_TBTT1INT_EN_8197F BIT(8)
+#define BIT_FS_TBTT0_MB7INT_EN_8197F BIT(7)
+#define BIT_FS_TBTT0_MB6INT_EN_8197F BIT(6)
+#define BIT_FS_TBTT0_MB5INT_EN_8197F BIT(5)
+#define BIT_FS_TBTT0_MB4INT_EN_8197F BIT(4)
+#define BIT_FS_TBTT0_MB3INT_EN_8197F BIT(3)
+#define BIT_FS_TBTT0_MB2INT_EN_8197F BIT(2)
+#define BIT_FS_TBTT0_MB1INT_EN_8197F BIT(1)
+#define BIT_FS_TBTT0_INT_EN_8197F BIT(0)
+
+/* 2 REG_FE2ISR_8197F */
+#define BIT_FS_TXSC_DESC_DONE_INT_8197F BIT(28)
+#define BIT_FS_TXSC_BKDONE_INT_8197F BIT(27)
+#define BIT_FS_TXSC_BEDONE_INT_8197F BIT(26)
+#define BIT_FS_TXSC_VIDONE_INT_8197F BIT(25)
+#define BIT_FS_TXSC_VODONE_INT_8197F BIT(24)
+#define BIT_FS_ATIM_MB7_INT_8197F BIT(23)
+#define BIT_FS_ATIM_MB6_INT_8197F BIT(22)
+#define BIT_FS_ATIM_MB5_INT_8197F BIT(21)
+#define BIT_FS_ATIM_MB4_INT_8197F BIT(20)
+#define BIT_FS_ATIM_MB3_INT_8197F BIT(19)
+#define BIT_FS_ATIM_MB2_INT_8197F BIT(18)
+#define BIT_FS_ATIM_MB1_INT_8197F BIT(17)
+#define BIT_FS_ATIM_MB0_INT_8197F BIT(16)
+#define BIT_FS_TBTT4INT_8197F BIT(11)
+#define BIT_FS_TBTT3INT_8197F BIT(10)
+#define BIT_FS_TBTT2INT_8197F BIT(9)
+#define BIT_FS_TBTT1INT_8197F BIT(8)
+#define BIT_FS_TBTT0_MB7INT_8197F BIT(7)
+#define BIT_FS_TBTT0_MB6INT_8197F BIT(6)
+#define BIT_FS_TBTT0_MB5INT_8197F BIT(5)
+#define BIT_FS_TBTT0_MB4INT_8197F BIT(4)
+#define BIT_FS_TBTT0_MB3INT_8197F BIT(3)
+#define BIT_FS_TBTT0_MB2INT_8197F BIT(2)
+#define BIT_FS_TBTT0_MB1INT_8197F BIT(1)
+#define BIT_FS_TBTT0_INT_8197F BIT(0)
+
+/* 2 REG_FE3IMR_8197F */
+#define BIT_FS_BCNELY4_AGGR_INT_EN_8197F BIT(31)
+#define BIT_FS_BCNELY3_AGGR_INT_EN_8197F BIT(30)
+#define BIT_FS_BCNELY2_AGGR_INT_EN_8197F BIT(29)
+#define BIT_FS_BCNELY1_AGGR_INT_EN_8197F BIT(28)
+#define BIT_FS_BCNDMA4_INT_EN_8197F BIT(27)
+#define BIT_FS_BCNDMA3_INT_EN_8197F BIT(26)
+#define BIT_FS_BCNDMA2_INT_EN_8197F BIT(25)
+#define BIT_FS_BCNDMA1_INT_EN_8197F BIT(24)
+#define BIT_FS_BCNDMA0_MB7_INT_EN_8197F BIT(23)
+#define BIT_FS_BCNDMA0_MB6_INT_EN_8197F BIT(22)
+#define BIT_FS_BCNDMA0_MB5_INT_EN_8197F BIT(21)
+#define BIT_FS_BCNDMA0_MB4_INT_EN_8197F BIT(20)
+#define BIT_FS_BCNDMA0_MB3_INT_EN_8197F BIT(19)
+#define BIT_FS_BCNDMA0_MB2_INT_EN_8197F BIT(18)
+#define BIT_FS_BCNDMA0_MB1_INT_EN_8197F BIT(17)
+#define BIT_FS_BCNDMA0_INT_EN_8197F BIT(16)
+#define BIT_FS_MTI_BCNIVLEAR_INT__EN_8197F BIT(15)
+#define BIT_FS_BCNERLY4_INT_EN_8197F BIT(11)
+#define BIT_FS_BCNERLY3_INT_EN_8197F BIT(10)
+#define BIT_FS_BCNERLY2_INT_EN_8197F BIT(9)
+#define BIT_FS_BCNERLY1_INT_EN_8197F BIT(8)
+#define BIT_FS_BCNERLY0_MB7INT_EN_8197F BIT(7)
+#define BIT_FS_BCNERLY0_MB6INT_EN_8197F BIT(6)
+#define BIT_FS_BCNERLY0_MB5INT_EN_8197F BIT(5)
+#define BIT_FS_BCNERLY0_MB4INT_EN_8197F BIT(4)
+#define BIT_FS_BCNERLY0_MB3INT_EN_8197F BIT(3)
+#define BIT_FS_BCNERLY0_MB2INT_EN_8197F BIT(2)
+#define BIT_FS_BCNERLY0_MB1INT_EN_8197F BIT(1)
+#define BIT_FS_BCNERLY0_INT_EN_8197F BIT(0)
+
+/* 2 REG_FE3ISR_8197F */
+#define BIT_FS_BCNELY4_AGGR_INT_8197F BIT(31)
+#define BIT_FS_BCNELY3_AGGR_INT_8197F BIT(30)
+#define BIT_FS_BCNELY2_AGGR_INT_8197F BIT(29)
+#define BIT_FS_BCNELY1_AGGR_INT_8197F BIT(28)
+#define BIT_FS_BCNDMA4_INT_8197F BIT(27)
+#define BIT_FS_BCNDMA3_INT_8197F BIT(26)
+#define BIT_FS_BCNDMA2_INT_8197F BIT(25)
+#define BIT_FS_BCNDMA1_INT_8197F BIT(24)
+#define BIT_FS_BCNDMA0_MB7_INT_8197F BIT(23)
+#define BIT_FS_BCNDMA0_MB6_INT_8197F BIT(22)
+#define BIT_FS_BCNDMA0_MB5_INT_8197F BIT(21)
+#define BIT_FS_BCNDMA0_MB4_INT_8197F BIT(20)
+#define BIT_FS_BCNDMA0_MB3_INT_8197F BIT(19)
+#define BIT_FS_BCNDMA0_MB2_INT_8197F BIT(18)
+#define BIT_FS_BCNDMA0_MB1_INT_8197F BIT(17)
+#define BIT_FS_BCNDMA0_INT_8197F BIT(16)
+#define BIT_FS_MTI_BCNIVLEAR_INT_8197F BIT(15)
+#define BIT_FS_BCNERLY4_INT_8197F BIT(11)
+#define BIT_FS_BCNERLY3_INT_8197F BIT(10)
+#define BIT_FS_BCNERLY2_INT_8197F BIT(9)
+#define BIT_FS_BCNERLY1_INT_8197F BIT(8)
+#define BIT_FS_BCNERLY0_MB7INT_8197F BIT(7)
+#define BIT_FS_BCNERLY0_MB6INT_8197F BIT(6)
+#define BIT_FS_BCNERLY0_MB5INT_8197F BIT(5)
+#define BIT_FS_BCNERLY0_MB4INT_8197F BIT(4)
+#define BIT_FS_BCNERLY0_MB3INT_8197F BIT(3)
+#define BIT_FS_BCNERLY0_MB2INT_8197F BIT(2)
+#define BIT_FS_BCNERLY0_MB1INT_8197F BIT(1)
+#define BIT_FS_BCNERLY0_INT_8197F BIT(0)
+
+/* 2 REG_FE4IMR_8197F */
+#define BIT_PORT4_PKTIN_INT_EN_8197F BIT(19)
+#define BIT_PORT3_PKTIN_INT_EN_8197F BIT(18)
+#define BIT_PORT2_PKTIN_INT_EN_8197F BIT(17)
+#define BIT_PORT1_PKTIN_INT_EN_8197F BIT(16)
+#define BIT_PORT4_RXUCMD0_OK_INT_EN_8197F BIT(15)
+#define BIT_PORT4_RXUCMD1_OK_INT_EN_8197F BIT(14)
+#define BIT_PORT4_RXBCMD0_OK_INT_EN_8197F BIT(13)
+#define BIT_PORT4_RXBCMD1_OK_INT_EN_8197F BIT(12)
+#define BIT_PORT3_RXUCMD0_OK_INT_EN_8197F BIT(11)
+#define BIT_PORT3_RXUCMD1_OK_INT_EN_8197F BIT(10)
+#define BIT_PORT3_RXBCMD0_OK_INT_EN_8197F BIT(9)
+#define BIT_PORT3_RXBCMD1_OK_INT_EN_8197F BIT(8)
+#define BIT_PORT2_RXUCMD0_OK_INT_EN_8197F BIT(7)
+#define BIT_PORT2_RXUCMD1_OK_INT_EN_8197F BIT(6)
+#define BIT_PORT2_RXBCMD0_OK_INT_EN_8197F BIT(5)
+#define BIT_PORT2_RXBCMD1_OK_INT_EN_8197F BIT(4)
+#define BIT_PORT1_RXUCMD0_OK_INT_EN_8197F BIT(3)
+#define BIT_PORT1_RXUCMD1_OK_INT_EN_8197F BIT(2)
+#define BIT_PORT1_RXBCMD0_OK_INT_EN_8197F BIT(1)
+#define BIT_PORT1_RXBCMD1_OK_INT_EN_8197F BIT(0)
+
+/* 2 REG_FE4ISR_8197F */
+#define BIT_PORT4_PKTIN_INT_8197F BIT(19)
+#define BIT_PORT3_PKTIN_INT_8197F BIT(18)
+#define BIT_PORT2_PKTIN_INT_8197F BIT(17)
+#define BIT_PORT1_PKTIN_INT_8197F BIT(16)
+#define BIT_PORT4_RXUCMD0_OK_INT_8197F BIT(15)
+#define BIT_PORT4_RXUCMD1_OK_INT_8197F BIT(14)
+#define BIT_PORT4_RXBCMD0_OK_INT_8197F BIT(13)
+#define BIT_PORT4_RXBCMD1_OK_INT_8197F BIT(12)
+#define BIT_PORT3_RXUCMD0_OK_INT_8197F BIT(11)
+#define BIT_PORT3_RXUCMD1_OK_INT_8197F BIT(10)
+#define BIT_PORT3_RXBCMD0_OK_INT_8197F BIT(9)
+#define BIT_PORT3_RXBCMD1_OK_INT_8197F BIT(8)
+#define BIT_PORT2_RXUCMD0_OK_INT_8197F BIT(7)
+#define BIT_PORT2_RXUCMD1_OK_INT_8197F BIT(6)
+#define BIT_PORT2_RXBCMD0_OK_INT_8197F BIT(5)
+#define BIT_PORT2_RXBCMD1_OK_INT_8197F BIT(4)
+#define BIT_PORT1_RXUCMD0_OK_INT_8197F BIT(3)
+#define BIT_PORT1_RXUCMD1_OK_INT_8197F BIT(2)
+#define BIT_PORT1_RXBCMD0_OK_INT_8197F BIT(1)
+#define BIT_PORT1_RXBCMD1_OK_INT_8197F BIT(0)
+
+/* 2 REG_FT1IMR_8197F */
+#define BIT__FT2ISR__IND_MSK_8197F BIT(30)
+#define BIT_FTM_PTT_INT_EN_8197F BIT(29)
+#define BIT_RXFTMREQ_INT_EN_8197F BIT(28)
+#define BIT_RXFTM_INT_EN_8197F BIT(27)
+#define BIT_TXFTM_INT_EN_8197F BIT(26)
+#define BIT_FS_H2C_CMD_OK_INT_EN_8197F BIT(25)
+#define BIT_FS_H2C_CMD_FULL_INT_EN_8197F BIT(24)
+#define BIT_FS_MACID_PWRCHANGE5_INT_EN_8197F BIT(23)
+#define BIT_FS_MACID_PWRCHANGE4_INT_EN_8197F BIT(22)
+#define BIT_FS_MACID_PWRCHANGE3_INT_EN_8197F BIT(21)
+#define BIT_FS_MACID_PWRCHANGE2_INT_EN_8197F BIT(20)
+#define BIT_FS_MACID_PWRCHANGE1_INT_EN_8197F BIT(19)
+#define BIT_FS_MACID_PWRCHANGE0_INT_EN_8197F BIT(18)
+#define BIT_FS_CTWEND2_INT_EN_8197F BIT(17)
+#define BIT_FS_CTWEND1_INT_EN_8197F BIT(16)
+#define BIT_FS_CTWEND0_INT_EN_8197F BIT(15)
+#define BIT_FS_TX_NULL1_INT_EN_8197F BIT(14)
+#define BIT_FS_TX_NULL0_INT_EN_8197F BIT(13)
+#define BIT_FS_TSF_BIT32_TOGGLE_EN_8197F BIT(12)
+#define BIT_FS_P2P_RFON2_INT_EN_8197F BIT(11)
+#define BIT_FS_P2P_RFOFF2_INT_EN_8197F BIT(10)
+#define BIT_FS_P2P_RFON1_INT_EN_8197F BIT(9)
+#define BIT_FS_P2P_RFOFF1_INT_EN_8197F BIT(8)
+#define BIT_FS_P2P_RFON0_INT_EN_8197F BIT(7)
+#define BIT_FS_P2P_RFOFF0_INT_EN_8197F BIT(6)
+#define BIT_FS_RX_UAPSDMD1_EN_8197F BIT(5)
+#define BIT_FS_RX_UAPSDMD0_EN_8197F BIT(4)
+#define BIT_FS_TRIGGER_PKT_EN_8197F BIT(3)
+#define BIT_FS_EOSP_INT_EN_8197F BIT(2)
+#define BIT_FS_RPWM2_INT_EN_8197F BIT(1)
+#define BIT_FS_RPWM_INT_EN_8197F BIT(0)
+
+/* 2 REG_FT1ISR_8197F */
+#define BIT__FT2ISR__IND_INT_8197F BIT(30)
+#define BIT_FTM_PTT_INT_8197F BIT(29)
+#define BIT_RXFTMREQ_INT_8197F BIT(28)
+#define BIT_RXFTM_INT_8197F BIT(27)
+#define BIT_TXFTM_INT_8197F BIT(26)
+#define BIT_FS_H2C_CMD_OK_INT_8197F BIT(25)
+#define BIT_FS_H2C_CMD_FULL_INT_8197F BIT(24)
+#define BIT_FS_MACID_PWRCHANGE5_INT_8197F BIT(23)
+#define BIT_FS_MACID_PWRCHANGE4_INT_8197F BIT(22)
+#define BIT_FS_MACID_PWRCHANGE3_INT_8197F BIT(21)
+#define BIT_FS_MACID_PWRCHANGE2_INT_8197F BIT(20)
+#define BIT_FS_MACID_PWRCHANGE1_INT_8197F BIT(19)
+#define BIT_FS_MACID_PWRCHANGE0_INT_8197F BIT(18)
+#define BIT_FS_CTWEND2_INT_8197F BIT(17)
+#define BIT_FS_CTWEND1_INT_8197F BIT(16)
+#define BIT_FS_CTWEND0_INT_8197F BIT(15)
+#define BIT_FS_TX_NULL1_INT_8197F BIT(14)
+#define BIT_FS_TX_NULL0_INT_8197F BIT(13)
+#define BIT_FS_TSF_BIT32_TOGGLE_INT_8197F BIT(12)
+#define BIT_FS_P2P_RFON2_INT_8197F BIT(11)
+#define BIT_FS_P2P_RFOFF2_INT_8197F BIT(10)
+#define BIT_FS_P2P_RFON1_INT_8197F BIT(9)
+#define BIT_FS_P2P_RFOFF1_INT_8197F BIT(8)
+#define BIT_FS_P2P_RFON0_INT_8197F BIT(7)
+#define BIT_FS_P2P_RFOFF0_INT_8197F BIT(6)
+#define BIT_FS_RX_UAPSDMD1_INT_8197F BIT(5)
+#define BIT_FS_RX_UAPSDMD0_INT_8197F BIT(4)
+#define BIT_FS_TRIGGER_PKT_INT_8197F BIT(3)
+#define BIT_FS_EOSP_INT_8197F BIT(2)
+#define BIT_FS_RPWM2_INT_8197F BIT(1)
+#define BIT_FS_RPWM_INT_8197F BIT(0)
+
+/* 2 REG_SPWR0_8197F */
+
+#define BIT_SHIFT_MID_31TO0_8197F 0
+#define BIT_MASK_MID_31TO0_8197F 0xffffffffL
+#define BIT_MID_31TO0_8197F(x)                                                 \
+	(((x) & BIT_MASK_MID_31TO0_8197F) << BIT_SHIFT_MID_31TO0_8197F)
+#define BITS_MID_31TO0_8197F                                                   \
+	(BIT_MASK_MID_31TO0_8197F << BIT_SHIFT_MID_31TO0_8197F)
+#define BIT_CLEAR_MID_31TO0_8197F(x) ((x) & (~BITS_MID_31TO0_8197F))
+#define BIT_GET_MID_31TO0_8197F(x)                                             \
+	(((x) >> BIT_SHIFT_MID_31TO0_8197F) & BIT_MASK_MID_31TO0_8197F)
+#define BIT_SET_MID_31TO0_8197F(x, v)                                          \
+	(BIT_CLEAR_MID_31TO0_8197F(x) | BIT_MID_31TO0_8197F(v))
+
+/* 2 REG_SPWR1_8197F */
+
+#define BIT_SHIFT_MID_63TO32_8197F 0
+#define BIT_MASK_MID_63TO32_8197F 0xffffffffL
+#define BIT_MID_63TO32_8197F(x)                                                \
+	(((x) & BIT_MASK_MID_63TO32_8197F) << BIT_SHIFT_MID_63TO32_8197F)
+#define BITS_MID_63TO32_8197F                                                  \
+	(BIT_MASK_MID_63TO32_8197F << BIT_SHIFT_MID_63TO32_8197F)
+#define BIT_CLEAR_MID_63TO32_8197F(x) ((x) & (~BITS_MID_63TO32_8197F))
+#define BIT_GET_MID_63TO32_8197F(x)                                            \
+	(((x) >> BIT_SHIFT_MID_63TO32_8197F) & BIT_MASK_MID_63TO32_8197F)
+#define BIT_SET_MID_63TO32_8197F(x, v)                                         \
+	(BIT_CLEAR_MID_63TO32_8197F(x) | BIT_MID_63TO32_8197F(v))
+
+/* 2 REG_SPWR2_8197F */
+
+#define BIT_SHIFT_MID_95O64_8197F 0
+#define BIT_MASK_MID_95O64_8197F 0xffffffffL
+#define BIT_MID_95O64_8197F(x)                                                 \
+	(((x) & BIT_MASK_MID_95O64_8197F) << BIT_SHIFT_MID_95O64_8197F)
+#define BITS_MID_95O64_8197F                                                   \
+	(BIT_MASK_MID_95O64_8197F << BIT_SHIFT_MID_95O64_8197F)
+#define BIT_CLEAR_MID_95O64_8197F(x) ((x) & (~BITS_MID_95O64_8197F))
+#define BIT_GET_MID_95O64_8197F(x)                                             \
+	(((x) >> BIT_SHIFT_MID_95O64_8197F) & BIT_MASK_MID_95O64_8197F)
+#define BIT_SET_MID_95O64_8197F(x, v)                                          \
+	(BIT_CLEAR_MID_95O64_8197F(x) | BIT_MID_95O64_8197F(v))
+
+/* 2 REG_SPWR3_8197F */
+
+#define BIT_SHIFT_MID_127TO96_8197F 0
+#define BIT_MASK_MID_127TO96_8197F 0xffffffffL
+#define BIT_MID_127TO96_8197F(x)                                               \
+	(((x) & BIT_MASK_MID_127TO96_8197F) << BIT_SHIFT_MID_127TO96_8197F)
+#define BITS_MID_127TO96_8197F                                                 \
+	(BIT_MASK_MID_127TO96_8197F << BIT_SHIFT_MID_127TO96_8197F)
+#define BIT_CLEAR_MID_127TO96_8197F(x) ((x) & (~BITS_MID_127TO96_8197F))
+#define BIT_GET_MID_127TO96_8197F(x)                                           \
+	(((x) >> BIT_SHIFT_MID_127TO96_8197F) & BIT_MASK_MID_127TO96_8197F)
+#define BIT_SET_MID_127TO96_8197F(x, v)                                        \
+	(BIT_CLEAR_MID_127TO96_8197F(x) | BIT_MID_127TO96_8197F(v))
+
+/* 2 REG_POWSEQ_8197F */
+
+#define BIT_SHIFT_SEQNUM_MID_8197F 16
+#define BIT_MASK_SEQNUM_MID_8197F 0xffff
+#define BIT_SEQNUM_MID_8197F(x)                                                \
+	(((x) & BIT_MASK_SEQNUM_MID_8197F) << BIT_SHIFT_SEQNUM_MID_8197F)
+#define BITS_SEQNUM_MID_8197F                                                  \
+	(BIT_MASK_SEQNUM_MID_8197F << BIT_SHIFT_SEQNUM_MID_8197F)
+#define BIT_CLEAR_SEQNUM_MID_8197F(x) ((x) & (~BITS_SEQNUM_MID_8197F))
+#define BIT_GET_SEQNUM_MID_8197F(x)                                            \
+	(((x) >> BIT_SHIFT_SEQNUM_MID_8197F) & BIT_MASK_SEQNUM_MID_8197F)
+#define BIT_SET_SEQNUM_MID_8197F(x, v)                                         \
+	(BIT_CLEAR_SEQNUM_MID_8197F(x) | BIT_SEQNUM_MID_8197F(v))
+
+#define BIT_SHIFT_REF_MID_8197F 0
+#define BIT_MASK_REF_MID_8197F 0x7f
+#define BIT_REF_MID_8197F(x)                                                   \
+	(((x) & BIT_MASK_REF_MID_8197F) << BIT_SHIFT_REF_MID_8197F)
+#define BITS_REF_MID_8197F (BIT_MASK_REF_MID_8197F << BIT_SHIFT_REF_MID_8197F)
+#define BIT_CLEAR_REF_MID_8197F(x) ((x) & (~BITS_REF_MID_8197F))
+#define BIT_GET_REF_MID_8197F(x)                                               \
+	(((x) >> BIT_SHIFT_REF_MID_8197F) & BIT_MASK_REF_MID_8197F)
+#define BIT_SET_REF_MID_8197F(x, v)                                            \
+	(BIT_CLEAR_REF_MID_8197F(x) | BIT_REF_MID_8197F(v))
+
+/* 2 REG_TC7_CTRL_V1_8197F */
+#define BIT_TC7INT_EN_8197F BIT(26)
+#define BIT_TC7MODE_8197F BIT(25)
+#define BIT_TC7EN_8197F BIT(24)
+
+#define BIT_SHIFT_TC7DATA_8197F 0
+#define BIT_MASK_TC7DATA_8197F 0xffffff
+#define BIT_TC7DATA_8197F(x)                                                   \
+	(((x) & BIT_MASK_TC7DATA_8197F) << BIT_SHIFT_TC7DATA_8197F)
+#define BITS_TC7DATA_8197F (BIT_MASK_TC7DATA_8197F << BIT_SHIFT_TC7DATA_8197F)
+#define BIT_CLEAR_TC7DATA_8197F(x) ((x) & (~BITS_TC7DATA_8197F))
+#define BIT_GET_TC7DATA_8197F(x)                                               \
+	(((x) >> BIT_SHIFT_TC7DATA_8197F) & BIT_MASK_TC7DATA_8197F)
+#define BIT_SET_TC7DATA_8197F(x, v)                                            \
+	(BIT_CLEAR_TC7DATA_8197F(x) | BIT_TC7DATA_8197F(v))
+
+/* 2 REG_TC8_CTRL_V1_8197F */
+#define BIT_TC8INT_EN_8197F BIT(26)
+#define BIT_TC8MODE_8197F BIT(25)
+#define BIT_TC8EN_8197F BIT(24)
+
+#define BIT_SHIFT_TC8DATA_8197F 0
+#define BIT_MASK_TC8DATA_8197F 0xffffff
+#define BIT_TC8DATA_8197F(x)                                                   \
+	(((x) & BIT_MASK_TC8DATA_8197F) << BIT_SHIFT_TC8DATA_8197F)
+#define BITS_TC8DATA_8197F (BIT_MASK_TC8DATA_8197F << BIT_SHIFT_TC8DATA_8197F)
+#define BIT_CLEAR_TC8DATA_8197F(x) ((x) & (~BITS_TC8DATA_8197F))
+#define BIT_GET_TC8DATA_8197F(x)                                               \
+	(((x) >> BIT_SHIFT_TC8DATA_8197F) & BIT_MASK_TC8DATA_8197F)
+#define BIT_SET_TC8DATA_8197F(x, v)                                            \
+	(BIT_CLEAR_TC8DATA_8197F(x) | BIT_TC8DATA_8197F(v))
+
+/* 2 REG_RXBCN_TBTT_INTERVAL_PORT0TO3_8197F */
+
+/* 2 REG_RXBCN_TBTT_INTERVAL_PORT4_8197F */
+
+/* 2 REG_EXT_QUEUE_REG_8197F */
+
+#define BIT_SHIFT_PCIE_PRIORITY_SEL_8197F 0
+#define BIT_MASK_PCIE_PRIORITY_SEL_8197F 0x3
+#define BIT_PCIE_PRIORITY_SEL_8197F(x)                                         \
+	(((x) & BIT_MASK_PCIE_PRIORITY_SEL_8197F)                              \
+	 << BIT_SHIFT_PCIE_PRIORITY_SEL_8197F)
+#define BITS_PCIE_PRIORITY_SEL_8197F                                           \
+	(BIT_MASK_PCIE_PRIORITY_SEL_8197F << BIT_SHIFT_PCIE_PRIORITY_SEL_8197F)
+#define BIT_CLEAR_PCIE_PRIORITY_SEL_8197F(x)                                   \
+	((x) & (~BITS_PCIE_PRIORITY_SEL_8197F))
+#define BIT_GET_PCIE_PRIORITY_SEL_8197F(x)                                     \
+	(((x) >> BIT_SHIFT_PCIE_PRIORITY_SEL_8197F) &                          \
+	 BIT_MASK_PCIE_PRIORITY_SEL_8197F)
+#define BIT_SET_PCIE_PRIORITY_SEL_8197F(x, v)                                  \
+	(BIT_CLEAR_PCIE_PRIORITY_SEL_8197F(x) | BIT_PCIE_PRIORITY_SEL_8197F(v))
+
+/* 2 REG_COUNTER_CONTROL_8197F */
+
+#define BIT_SHIFT_COUNTER_BASE_8197F 16
+#define BIT_MASK_COUNTER_BASE_8197F 0x1fff
+#define BIT_COUNTER_BASE_8197F(x)                                              \
+	(((x) & BIT_MASK_COUNTER_BASE_8197F) << BIT_SHIFT_COUNTER_BASE_8197F)
+#define BITS_COUNTER_BASE_8197F                                                \
+	(BIT_MASK_COUNTER_BASE_8197F << BIT_SHIFT_COUNTER_BASE_8197F)
+#define BIT_CLEAR_COUNTER_BASE_8197F(x) ((x) & (~BITS_COUNTER_BASE_8197F))
+#define BIT_GET_COUNTER_BASE_8197F(x)                                          \
+	(((x) >> BIT_SHIFT_COUNTER_BASE_8197F) & BIT_MASK_COUNTER_BASE_8197F)
+#define BIT_SET_COUNTER_BASE_8197F(x, v)                                       \
+	(BIT_CLEAR_COUNTER_BASE_8197F(x) | BIT_COUNTER_BASE_8197F(v))
+
+#define BIT_EN_RTS_REQ_8197F BIT(9)
+#define BIT_EN_EDCA_REQ_8197F BIT(8)
+#define BIT_EN_PTCL_REQ_8197F BIT(7)
+#define BIT_EN_SCH_REQ_8197F BIT(6)
+#define BIT_EN_USB_CNT_8197F BIT(5)
+#define BIT_EN_PCIE_CNT_8197F BIT(4)
+#define BIT_RQPN_CNT_8197F BIT(3)
+#define BIT_RDE_CNT_8197F BIT(2)
+#define BIT_TDE_CNT_8197F BIT(1)
+#define BIT_DIS_CNT_8197F BIT(0)
+
+/* 2 REG_COUNTER_TH_8197F */
+#define BIT_CNT_ALL_MACID_8197F BIT(31)
+
+#define BIT_SHIFT_CNT_MACID_8197F 24
+#define BIT_MASK_CNT_MACID_8197F 0x7f
+#define BIT_CNT_MACID_8197F(x)                                                 \
+	(((x) & BIT_MASK_CNT_MACID_8197F) << BIT_SHIFT_CNT_MACID_8197F)
+#define BITS_CNT_MACID_8197F                                                   \
+	(BIT_MASK_CNT_MACID_8197F << BIT_SHIFT_CNT_MACID_8197F)
+#define BIT_CLEAR_CNT_MACID_8197F(x) ((x) & (~BITS_CNT_MACID_8197F))
+#define BIT_GET_CNT_MACID_8197F(x)                                             \
+	(((x) >> BIT_SHIFT_CNT_MACID_8197F) & BIT_MASK_CNT_MACID_8197F)
+#define BIT_SET_CNT_MACID_8197F(x, v)                                          \
+	(BIT_CLEAR_CNT_MACID_8197F(x) | BIT_CNT_MACID_8197F(v))
+
+#define BIT_SHIFT_AGG_VALUE2_8197F 16
+#define BIT_MASK_AGG_VALUE2_8197F 0x7f
+#define BIT_AGG_VALUE2_8197F(x)                                                \
+	(((x) & BIT_MASK_AGG_VALUE2_8197F) << BIT_SHIFT_AGG_VALUE2_8197F)
+#define BITS_AGG_VALUE2_8197F                                                  \
+	(BIT_MASK_AGG_VALUE2_8197F << BIT_SHIFT_AGG_VALUE2_8197F)
+#define BIT_CLEAR_AGG_VALUE2_8197F(x) ((x) & (~BITS_AGG_VALUE2_8197F))
+#define BIT_GET_AGG_VALUE2_8197F(x)                                            \
+	(((x) >> BIT_SHIFT_AGG_VALUE2_8197F) & BIT_MASK_AGG_VALUE2_8197F)
+#define BIT_SET_AGG_VALUE2_8197F(x, v)                                         \
+	(BIT_CLEAR_AGG_VALUE2_8197F(x) | BIT_AGG_VALUE2_8197F(v))
+
+#define BIT_SHIFT_AGG_VALUE1_8197F 8
+#define BIT_MASK_AGG_VALUE1_8197F 0x7f
+#define BIT_AGG_VALUE1_8197F(x)                                                \
+	(((x) & BIT_MASK_AGG_VALUE1_8197F) << BIT_SHIFT_AGG_VALUE1_8197F)
+#define BITS_AGG_VALUE1_8197F                                                  \
+	(BIT_MASK_AGG_VALUE1_8197F << BIT_SHIFT_AGG_VALUE1_8197F)
+#define BIT_CLEAR_AGG_VALUE1_8197F(x) ((x) & (~BITS_AGG_VALUE1_8197F))
+#define BIT_GET_AGG_VALUE1_8197F(x)                                            \
+	(((x) >> BIT_SHIFT_AGG_VALUE1_8197F) & BIT_MASK_AGG_VALUE1_8197F)
+#define BIT_SET_AGG_VALUE1_8197F(x, v)                                         \
+	(BIT_CLEAR_AGG_VALUE1_8197F(x) | BIT_AGG_VALUE1_8197F(v))
+
+#define BIT_SHIFT_AGG_VALUE0_8197F 0
+#define BIT_MASK_AGG_VALUE0_8197F 0x7f
+#define BIT_AGG_VALUE0_8197F(x)                                                \
+	(((x) & BIT_MASK_AGG_VALUE0_8197F) << BIT_SHIFT_AGG_VALUE0_8197F)
+#define BITS_AGG_VALUE0_8197F                                                  \
+	(BIT_MASK_AGG_VALUE0_8197F << BIT_SHIFT_AGG_VALUE0_8197F)
+#define BIT_CLEAR_AGG_VALUE0_8197F(x) ((x) & (~BITS_AGG_VALUE0_8197F))
+#define BIT_GET_AGG_VALUE0_8197F(x)                                            \
+	(((x) >> BIT_SHIFT_AGG_VALUE0_8197F) & BIT_MASK_AGG_VALUE0_8197F)
+#define BIT_SET_AGG_VALUE0_8197F(x, v)                                         \
+	(BIT_CLEAR_AGG_VALUE0_8197F(x) | BIT_AGG_VALUE0_8197F(v))
+
+/* 2 REG_COUNTER_SET_8197F */
+#define BIT_RTS_RST_8197F BIT(24)
+#define BIT_PTCL_RST_8197F BIT(23)
+#define BIT_SCH_RST_8197F BIT(22)
+#define BIT_EDCA_RST_8197F BIT(21)
+#define BIT_RQPN_RST_8197F BIT(20)
+#define BIT_USB_RST_8197F BIT(19)
+#define BIT_PCIE_RST_8197F BIT(18)
+#define BIT_RXDMA_RST_8197F BIT(17)
+#define BIT_TXDMA_RST_8197F BIT(16)
+#define BIT_EN_RTS_START_8197F BIT(8)
+#define BIT_EN_PTCL_START_8197F BIT(7)
+#define BIT_EN_SCH_START_8197F BIT(6)
+#define BIT_EN_EDCA_START_8197F BIT(5)
+#define BIT_EN_RQPN_START_8197F BIT(4)
+#define BIT_EN_USB_START_8197F BIT(3)
+#define BIT_EN_PCIE_START_8197F BIT(2)
+#define BIT_EN_RXDMA_START_8197F BIT(1)
+#define BIT_EN_TXDMA_START_8197F BIT(0)
+
+/* 2 REG_COUNTER_OVERFLOW_8197F */
+#define BIT_RTS_OVF_8197F BIT(8)
+#define BIT_PTCL_OVF_8197F BIT(7)
+#define BIT_SCH_OVF_8197F BIT(6)
+#define BIT_EDCA_OVF_8197F BIT(5)
+#define BIT_RQPN_OVF_8197F BIT(4)
+#define BIT_USB_OVF_8197F BIT(3)
+#define BIT_PCIE_OVF_8197F BIT(2)
+#define BIT_RXDMA_OVF_8197F BIT(1)
+#define BIT_TXDMA_OVF_8197F BIT(0)
+
+/* 2 REG_TDE_LEN_TH_8197F */
+
+#define BIT_SHIFT_TXDMA_LEN_TH0_8197F 16
+#define BIT_MASK_TXDMA_LEN_TH0_8197F 0xffff
+#define BIT_TXDMA_LEN_TH0_8197F(x)                                             \
+	(((x) & BIT_MASK_TXDMA_LEN_TH0_8197F) << BIT_SHIFT_TXDMA_LEN_TH0_8197F)
+#define BITS_TXDMA_LEN_TH0_8197F                                               \
+	(BIT_MASK_TXDMA_LEN_TH0_8197F << BIT_SHIFT_TXDMA_LEN_TH0_8197F)
+#define BIT_CLEAR_TXDMA_LEN_TH0_8197F(x) ((x) & (~BITS_TXDMA_LEN_TH0_8197F))
+#define BIT_GET_TXDMA_LEN_TH0_8197F(x)                                         \
+	(((x) >> BIT_SHIFT_TXDMA_LEN_TH0_8197F) & BIT_MASK_TXDMA_LEN_TH0_8197F)
+#define BIT_SET_TXDMA_LEN_TH0_8197F(x, v)                                      \
+	(BIT_CLEAR_TXDMA_LEN_TH0_8197F(x) | BIT_TXDMA_LEN_TH0_8197F(v))
+
+#define BIT_SHIFT_TXDMA_LEN_TH1_8197F 0
+#define BIT_MASK_TXDMA_LEN_TH1_8197F 0xffff
+#define BIT_TXDMA_LEN_TH1_8197F(x)                                             \
+	(((x) & BIT_MASK_TXDMA_LEN_TH1_8197F) << BIT_SHIFT_TXDMA_LEN_TH1_8197F)
+#define BITS_TXDMA_LEN_TH1_8197F                                               \
+	(BIT_MASK_TXDMA_LEN_TH1_8197F << BIT_SHIFT_TXDMA_LEN_TH1_8197F)
+#define BIT_CLEAR_TXDMA_LEN_TH1_8197F(x) ((x) & (~BITS_TXDMA_LEN_TH1_8197F))
+#define BIT_GET_TXDMA_LEN_TH1_8197F(x)                                         \
+	(((x) >> BIT_SHIFT_TXDMA_LEN_TH1_8197F) & BIT_MASK_TXDMA_LEN_TH1_8197F)
+#define BIT_SET_TXDMA_LEN_TH1_8197F(x, v)                                      \
+	(BIT_CLEAR_TXDMA_LEN_TH1_8197F(x) | BIT_TXDMA_LEN_TH1_8197F(v))
+
+/* 2 REG_RDE_LEN_TH_8197F */
+
+#define BIT_SHIFT_RXDMA_LEN_TH0_8197F 16
+#define BIT_MASK_RXDMA_LEN_TH0_8197F 0xffff
+#define BIT_RXDMA_LEN_TH0_8197F(x)                                             \
+	(((x) & BIT_MASK_RXDMA_LEN_TH0_8197F) << BIT_SHIFT_RXDMA_LEN_TH0_8197F)
+#define BITS_RXDMA_LEN_TH0_8197F                                               \
+	(BIT_MASK_RXDMA_LEN_TH0_8197F << BIT_SHIFT_RXDMA_LEN_TH0_8197F)
+#define BIT_CLEAR_RXDMA_LEN_TH0_8197F(x) ((x) & (~BITS_RXDMA_LEN_TH0_8197F))
+#define BIT_GET_RXDMA_LEN_TH0_8197F(x)                                         \
+	(((x) >> BIT_SHIFT_RXDMA_LEN_TH0_8197F) & BIT_MASK_RXDMA_LEN_TH0_8197F)
+#define BIT_SET_RXDMA_LEN_TH0_8197F(x, v)                                      \
+	(BIT_CLEAR_RXDMA_LEN_TH0_8197F(x) | BIT_RXDMA_LEN_TH0_8197F(v))
+
+#define BIT_SHIFT_RXDMA_LEN_TH1_8197F 0
+#define BIT_MASK_RXDMA_LEN_TH1_8197F 0xffff
+#define BIT_RXDMA_LEN_TH1_8197F(x)                                             \
+	(((x) & BIT_MASK_RXDMA_LEN_TH1_8197F) << BIT_SHIFT_RXDMA_LEN_TH1_8197F)
+#define BITS_RXDMA_LEN_TH1_8197F                                               \
+	(BIT_MASK_RXDMA_LEN_TH1_8197F << BIT_SHIFT_RXDMA_LEN_TH1_8197F)
+#define BIT_CLEAR_RXDMA_LEN_TH1_8197F(x) ((x) & (~BITS_RXDMA_LEN_TH1_8197F))
+#define BIT_GET_RXDMA_LEN_TH1_8197F(x)                                         \
+	(((x) >> BIT_SHIFT_RXDMA_LEN_TH1_8197F) & BIT_MASK_RXDMA_LEN_TH1_8197F)
+#define BIT_SET_RXDMA_LEN_TH1_8197F(x, v)                                      \
+	(BIT_CLEAR_RXDMA_LEN_TH1_8197F(x) | BIT_RXDMA_LEN_TH1_8197F(v))
+
+/* 2 REG_PCIE_EXEC_TIME_8197F */
+
+#define BIT_SHIFT_COUNTER_INTERVAL_SEL_8197F 16
+#define BIT_MASK_COUNTER_INTERVAL_SEL_8197F 0x3
+#define BIT_COUNTER_INTERVAL_SEL_8197F(x)                                      \
+	(((x) & BIT_MASK_COUNTER_INTERVAL_SEL_8197F)                           \
+	 << BIT_SHIFT_COUNTER_INTERVAL_SEL_8197F)
+#define BITS_COUNTER_INTERVAL_SEL_8197F                                        \
+	(BIT_MASK_COUNTER_INTERVAL_SEL_8197F                                   \
+	 << BIT_SHIFT_COUNTER_INTERVAL_SEL_8197F)
+#define BIT_CLEAR_COUNTER_INTERVAL_SEL_8197F(x)                                \
+	((x) & (~BITS_COUNTER_INTERVAL_SEL_8197F))
+#define BIT_GET_COUNTER_INTERVAL_SEL_8197F(x)                                  \
+	(((x) >> BIT_SHIFT_COUNTER_INTERVAL_SEL_8197F) &                       \
+	 BIT_MASK_COUNTER_INTERVAL_SEL_8197F)
+#define BIT_SET_COUNTER_INTERVAL_SEL_8197F(x, v)                               \
+	(BIT_CLEAR_COUNTER_INTERVAL_SEL_8197F(x) |                             \
+	 BIT_COUNTER_INTERVAL_SEL_8197F(v))
+
+#define BIT_SHIFT_PCIE_TRANS_DATA_TH1_8197F 0
+#define BIT_MASK_PCIE_TRANS_DATA_TH1_8197F 0xffff
+#define BIT_PCIE_TRANS_DATA_TH1_8197F(x)                                       \
+	(((x) & BIT_MASK_PCIE_TRANS_DATA_TH1_8197F)                            \
+	 << BIT_SHIFT_PCIE_TRANS_DATA_TH1_8197F)
+#define BITS_PCIE_TRANS_DATA_TH1_8197F                                         \
+	(BIT_MASK_PCIE_TRANS_DATA_TH1_8197F                                    \
+	 << BIT_SHIFT_PCIE_TRANS_DATA_TH1_8197F)
+#define BIT_CLEAR_PCIE_TRANS_DATA_TH1_8197F(x)                                 \
+	((x) & (~BITS_PCIE_TRANS_DATA_TH1_8197F))
+#define BIT_GET_PCIE_TRANS_DATA_TH1_8197F(x)                                   \
+	(((x) >> BIT_SHIFT_PCIE_TRANS_DATA_TH1_8197F) &                        \
+	 BIT_MASK_PCIE_TRANS_DATA_TH1_8197F)
+#define BIT_SET_PCIE_TRANS_DATA_TH1_8197F(x, v)                                \
+	(BIT_CLEAR_PCIE_TRANS_DATA_TH1_8197F(x) |                              \
+	 BIT_PCIE_TRANS_DATA_TH1_8197F(v))
+
+/* 2 REG_FT2IMR_8197F */
+#define BIT_PORT4_RX_UCMD1_UAPSD0_OK_INT_EN_8197F BIT(31)
+#define BIT_PORT4_RX_UCMD0_UAPSD0_OK_INT_EN_8197F BIT(30)
+#define BIT_PORT4_TRIPKT_OK_INT_EN_8197F BIT(29)
+#define BIT_PORT4_RX_EOSP_OK_INT_EN_8197F BIT(28)
+#define BIT_PORT3_RX_UCMD1_UAPSD0_OK_INT_EN_8197F BIT(27)
+#define BIT_PORT3_RX_UCMD0_UAPSD0_OK_INT_EN_8197F BIT(26)
+#define BIT_PORT3_TRIPKT_OK_INT_EN_8197F BIT(25)
+#define BIT_PORT3_RX_EOSP_OK_INT_EN_8197F BIT(24)
+#define BIT_PORT2_RX_UCMD1_UAPSD0_OK_INT_EN_8197F BIT(23)
+#define BIT_PORT2_RX_UCMD0_UAPSD0_OK_INT_EN_8197F BIT(22)
+#define BIT_PORT2_TRIPKT_OK_INT_EN_8197F BIT(21)
+#define BIT_PORT2_RX_EOSP_OK_INT_EN_8197F BIT(20)
+#define BIT_PORT1_RX_UCMD1_UAPSD0_OK_INT_EN_8197F BIT(19)
+#define BIT_PORT1_RX_UCMD0_UAPSD0_OK_INT_EN_8197F BIT(18)
+#define BIT_PORT1_TRIPKT_OK_INT_EN_8197F BIT(17)
+#define BIT_PORT1_RX_EOSP_OK_INT_EN_8197F BIT(16)
+#define BIT_NOA2_TSFT_BIT32_TOGGLE_INT_EN_8197F BIT(9)
+#define BIT_NOA1_TSFT_BIT32_TOGGLE_INT_EN_8197F BIT(8)
+#define BIT_PORT4_TX_NULL1_DONE_INT_EN_8197F BIT(7)
+#define BIT_PORT4_TX_NULL0_DONE_INT_EN_8197F BIT(6)
+#define BIT_PORT3_TX_NULL1_DONE_INT_EN_8197F BIT(5)
+#define BIT_PORT3_TX_NULL0_DONE_INT_EN_8197F BIT(4)
+#define BIT_PORT2_TX_NULL1_DONE_INT_EN_8197F BIT(3)
+#define BIT_PORT2_TX_NULL0_DONE_INT_EN_8197F BIT(2)
+#define BIT_PORT1_TX_NULL1_DONE_INT_EN_8197F BIT(1)
+#define BIT_PORT1_TX_NULL0_DONE_INT_EN_8197F BIT(0)
+
+/* 2 REG_FT2ISR_8197F */
+#define BIT_PORT4_RX_UCMD1_UAPSD0_OK_INT_8197F BIT(31)
+#define BIT_PORT4_RX_UCMD0_UAPSD0_OK_INT_8197F BIT(30)
+#define BIT_PORT4_TRIPKT_OK_INT_8197F BIT(29)
+#define BIT_PORT4_RX_EOSP_OK_INT_8197F BIT(28)
+#define BIT_PORT3_RX_UCMD1_UAPSD0_OK_INT_8197F BIT(27)
+#define BIT_PORT3_RX_UCMD0_UAPSD0_OK_INT_8197F BIT(26)
+#define BIT_PORT3_TRIPKT_OK_INT_8197F BIT(25)
+#define BIT_PORT3_RX_EOSP_OK_INT_8197F BIT(24)
+#define BIT_PORT2_RX_UCMD1_UAPSD0_OK_INT_8197F BIT(23)
+#define BIT_PORT2_RX_UCMD0_UAPSD0_OK_INT_8197F BIT(22)
+#define BIT_PORT2_TRIPKT_OK_INT_8197F BIT(21)
+#define BIT_PORT2_RX_EOSP_OK_INT_8197F BIT(20)
+#define BIT_PORT1_RX_UCMD1_UAPSD0_OK_INT_8197F BIT(19)
+#define BIT_PORT1_RX_UCMD0_UAPSD0_OK_INT_8197F BIT(18)
+#define BIT_PORT1_TRIPKT_OK_INT_8197F BIT(17)
+#define BIT_PORT1_RX_EOSP_OK_INT_8197F BIT(16)
+#define BIT_NOA2_TSFT_BIT32_TOGGLE_INT_8197F BIT(9)
+#define BIT_NOA1_TSFT_BIT32_TOGGLE_INT_8197F BIT(8)
+#define BIT_PORT4_TX_NULL1_DONE_INT_8197F BIT(7)
+#define BIT_PORT4_TX_NULL0_DONE_INT_8197F BIT(6)
+#define BIT_PORT3_TX_NULL1_DONE_INT_8197F BIT(5)
+#define BIT_PORT3_TX_NULL0_DONE_INT_8197F BIT(4)
+#define BIT_PORT2_TX_NULL1_DONE_INT_8197F BIT(3)
+#define BIT_PORT2_TX_NULL0_DONE_INT_8197F BIT(2)
+#define BIT_PORT1_TX_NULL1_DONE_INT_8197F BIT(1)
+#define BIT_PORT1_TX_NULL0_DONE_INT_8197F BIT(0)
+
+/* 2 REG_MSG2_8197F */
+
+#define BIT_SHIFT_FW_MSG2_8197F 0
+#define BIT_MASK_FW_MSG2_8197F 0xffffffffL
+#define BIT_FW_MSG2_8197F(x)                                                   \
+	(((x) & BIT_MASK_FW_MSG2_8197F) << BIT_SHIFT_FW_MSG2_8197F)
+#define BITS_FW_MSG2_8197F (BIT_MASK_FW_MSG2_8197F << BIT_SHIFT_FW_MSG2_8197F)
+#define BIT_CLEAR_FW_MSG2_8197F(x) ((x) & (~BITS_FW_MSG2_8197F))
+#define BIT_GET_FW_MSG2_8197F(x)                                               \
+	(((x) >> BIT_SHIFT_FW_MSG2_8197F) & BIT_MASK_FW_MSG2_8197F)
+#define BIT_SET_FW_MSG2_8197F(x, v)                                            \
+	(BIT_CLEAR_FW_MSG2_8197F(x) | BIT_FW_MSG2_8197F(v))
+
+/* 2 REG_MSG3_8197F */
+
+#define BIT_SHIFT_FW_MSG3_8197F 0
+#define BIT_MASK_FW_MSG3_8197F 0xffffffffL
+#define BIT_FW_MSG3_8197F(x)                                                   \
+	(((x) & BIT_MASK_FW_MSG3_8197F) << BIT_SHIFT_FW_MSG3_8197F)
+#define BITS_FW_MSG3_8197F (BIT_MASK_FW_MSG3_8197F << BIT_SHIFT_FW_MSG3_8197F)
+#define BIT_CLEAR_FW_MSG3_8197F(x) ((x) & (~BITS_FW_MSG3_8197F))
+#define BIT_GET_FW_MSG3_8197F(x)                                               \
+	(((x) >> BIT_SHIFT_FW_MSG3_8197F) & BIT_MASK_FW_MSG3_8197F)
+#define BIT_SET_FW_MSG3_8197F(x, v)                                            \
+	(BIT_CLEAR_FW_MSG3_8197F(x) | BIT_FW_MSG3_8197F(v))
+
+/* 2 REG_MSG4_8197F */
+
+#define BIT_SHIFT_FW_MSG4_8197F 0
+#define BIT_MASK_FW_MSG4_8197F 0xffffffffL
+#define BIT_FW_MSG4_8197F(x)                                                   \
+	(((x) & BIT_MASK_FW_MSG4_8197F) << BIT_SHIFT_FW_MSG4_8197F)
+#define BITS_FW_MSG4_8197F (BIT_MASK_FW_MSG4_8197F << BIT_SHIFT_FW_MSG4_8197F)
+#define BIT_CLEAR_FW_MSG4_8197F(x) ((x) & (~BITS_FW_MSG4_8197F))
+#define BIT_GET_FW_MSG4_8197F(x)                                               \
+	(((x) >> BIT_SHIFT_FW_MSG4_8197F) & BIT_MASK_FW_MSG4_8197F)
+#define BIT_SET_FW_MSG4_8197F(x, v)                                            \
+	(BIT_CLEAR_FW_MSG4_8197F(x) | BIT_FW_MSG4_8197F(v))
+
+/* 2 REG_MSG5_8197F */
+
+#define BIT_SHIFT_FW_MSG5_8197F 0
+#define BIT_MASK_FW_MSG5_8197F 0xffffffffL
+#define BIT_FW_MSG5_8197F(x)                                                   \
+	(((x) & BIT_MASK_FW_MSG5_8197F) << BIT_SHIFT_FW_MSG5_8197F)
+#define BITS_FW_MSG5_8197F (BIT_MASK_FW_MSG5_8197F << BIT_SHIFT_FW_MSG5_8197F)
+#define BIT_CLEAR_FW_MSG5_8197F(x) ((x) & (~BITS_FW_MSG5_8197F))
+#define BIT_GET_FW_MSG5_8197F(x)                                               \
+	(((x) >> BIT_SHIFT_FW_MSG5_8197F) & BIT_MASK_FW_MSG5_8197F)
+#define BIT_SET_FW_MSG5_8197F(x, v)                                            \
+	(BIT_CLEAR_FW_MSG5_8197F(x) | BIT_FW_MSG5_8197F(v))
+
+/* 2 REG_NOT_VALID_8197F */
+
+/* 2 REG_FIFOPAGE_CTRL_1_8197F */
+
+#define BIT_SHIFT_TX_OQT_HE_FREE_SPACE_V1_8197F 16
+#define BIT_MASK_TX_OQT_HE_FREE_SPACE_V1_8197F 0xff
+#define BIT_TX_OQT_HE_FREE_SPACE_V1_8197F(x)                                   \
+	(((x) & BIT_MASK_TX_OQT_HE_FREE_SPACE_V1_8197F)                        \
+	 << BIT_SHIFT_TX_OQT_HE_FREE_SPACE_V1_8197F)
+#define BITS_TX_OQT_HE_FREE_SPACE_V1_8197F                                     \
+	(BIT_MASK_TX_OQT_HE_FREE_SPACE_V1_8197F                                \
+	 << BIT_SHIFT_TX_OQT_HE_FREE_SPACE_V1_8197F)
+#define BIT_CLEAR_TX_OQT_HE_FREE_SPACE_V1_8197F(x)                             \
+	((x) & (~BITS_TX_OQT_HE_FREE_SPACE_V1_8197F))
+#define BIT_GET_TX_OQT_HE_FREE_SPACE_V1_8197F(x)                               \
+	(((x) >> BIT_SHIFT_TX_OQT_HE_FREE_SPACE_V1_8197F) &                    \
+	 BIT_MASK_TX_OQT_HE_FREE_SPACE_V1_8197F)
+#define BIT_SET_TX_OQT_HE_FREE_SPACE_V1_8197F(x, v)                            \
+	(BIT_CLEAR_TX_OQT_HE_FREE_SPACE_V1_8197F(x) |                          \
+	 BIT_TX_OQT_HE_FREE_SPACE_V1_8197F(v))
+
+#define BIT_SHIFT_TX_OQT_NL_FREE_SPACE_V1_8197F 0
+#define BIT_MASK_TX_OQT_NL_FREE_SPACE_V1_8197F 0xff
+#define BIT_TX_OQT_NL_FREE_SPACE_V1_8197F(x)                                   \
+	(((x) & BIT_MASK_TX_OQT_NL_FREE_SPACE_V1_8197F)                        \
+	 << BIT_SHIFT_TX_OQT_NL_FREE_SPACE_V1_8197F)
+#define BITS_TX_OQT_NL_FREE_SPACE_V1_8197F                                     \
+	(BIT_MASK_TX_OQT_NL_FREE_SPACE_V1_8197F                                \
+	 << BIT_SHIFT_TX_OQT_NL_FREE_SPACE_V1_8197F)
+#define BIT_CLEAR_TX_OQT_NL_FREE_SPACE_V1_8197F(x)                             \
+	((x) & (~BITS_TX_OQT_NL_FREE_SPACE_V1_8197F))
+#define BIT_GET_TX_OQT_NL_FREE_SPACE_V1_8197F(x)                               \
+	(((x) >> BIT_SHIFT_TX_OQT_NL_FREE_SPACE_V1_8197F) &                    \
+	 BIT_MASK_TX_OQT_NL_FREE_SPACE_V1_8197F)
+#define BIT_SET_TX_OQT_NL_FREE_SPACE_V1_8197F(x, v)                            \
+	(BIT_CLEAR_TX_OQT_NL_FREE_SPACE_V1_8197F(x) |                          \
+	 BIT_TX_OQT_NL_FREE_SPACE_V1_8197F(v))
+
+/* 2 REG_FIFOPAGE_CTRL_2_8197F */
+#define BIT_BCN_VALID_1_V1_8197F BIT(31)
+
+#define BIT_SHIFT_BCN_HEAD_1_V1_8197F 16
+#define BIT_MASK_BCN_HEAD_1_V1_8197F 0xfff
+#define BIT_BCN_HEAD_1_V1_8197F(x)                                             \
+	(((x) & BIT_MASK_BCN_HEAD_1_V1_8197F) << BIT_SHIFT_BCN_HEAD_1_V1_8197F)
+#define BITS_BCN_HEAD_1_V1_8197F                                               \
+	(BIT_MASK_BCN_HEAD_1_V1_8197F << BIT_SHIFT_BCN_HEAD_1_V1_8197F)
+#define BIT_CLEAR_BCN_HEAD_1_V1_8197F(x) ((x) & (~BITS_BCN_HEAD_1_V1_8197F))
+#define BIT_GET_BCN_HEAD_1_V1_8197F(x)                                         \
+	(((x) >> BIT_SHIFT_BCN_HEAD_1_V1_8197F) & BIT_MASK_BCN_HEAD_1_V1_8197F)
+#define BIT_SET_BCN_HEAD_1_V1_8197F(x, v)                                      \
+	(BIT_CLEAR_BCN_HEAD_1_V1_8197F(x) | BIT_BCN_HEAD_1_V1_8197F(v))
+
+#define BIT_BCN_VALID_V1_8197F BIT(15)
+
+#define BIT_SHIFT_BCN_HEAD_V1_8197F 0
+#define BIT_MASK_BCN_HEAD_V1_8197F 0xfff
+#define BIT_BCN_HEAD_V1_8197F(x)                                               \
+	(((x) & BIT_MASK_BCN_HEAD_V1_8197F) << BIT_SHIFT_BCN_HEAD_V1_8197F)
+#define BITS_BCN_HEAD_V1_8197F                                                 \
+	(BIT_MASK_BCN_HEAD_V1_8197F << BIT_SHIFT_BCN_HEAD_V1_8197F)
+#define BIT_CLEAR_BCN_HEAD_V1_8197F(x) ((x) & (~BITS_BCN_HEAD_V1_8197F))
+#define BIT_GET_BCN_HEAD_V1_8197F(x)                                           \
+	(((x) >> BIT_SHIFT_BCN_HEAD_V1_8197F) & BIT_MASK_BCN_HEAD_V1_8197F)
+#define BIT_SET_BCN_HEAD_V1_8197F(x, v)                                        \
+	(BIT_CLEAR_BCN_HEAD_V1_8197F(x) | BIT_BCN_HEAD_V1_8197F(v))
+
+/* 2 REG_AUTO_LLT_V1_8197F */
+
+#define BIT_SHIFT_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8197F 24
+#define BIT_MASK_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8197F 0xff
+#define BIT_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8197F(x)                            \
+	(((x) & BIT_MASK_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8197F)                 \
+	 << BIT_SHIFT_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8197F)
+#define BITS_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8197F                              \
+	(BIT_MASK_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8197F                         \
+	 << BIT_SHIFT_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8197F)
+#define BIT_CLEAR_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8197F(x)                      \
+	((x) & (~BITS_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8197F))
+#define BIT_GET_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8197F(x)                        \
+	(((x) >> BIT_SHIFT_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8197F) &             \
+	 BIT_MASK_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8197F)
+#define BIT_SET_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8197F(x, v)                     \
+	(BIT_CLEAR_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8197F(x) |                   \
+	 BIT_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8197F(v))
+
+#define BIT_SHIFT_LLT_FREE_PAGE_V1_8197F 8
+#define BIT_MASK_LLT_FREE_PAGE_V1_8197F 0xffff
+#define BIT_LLT_FREE_PAGE_V1_8197F(x)                                          \
+	(((x) & BIT_MASK_LLT_FREE_PAGE_V1_8197F)                               \
+	 << BIT_SHIFT_LLT_FREE_PAGE_V1_8197F)
+#define BITS_LLT_FREE_PAGE_V1_8197F                                            \
+	(BIT_MASK_LLT_FREE_PAGE_V1_8197F << BIT_SHIFT_LLT_FREE_PAGE_V1_8197F)
+#define BIT_CLEAR_LLT_FREE_PAGE_V1_8197F(x)                                    \
+	((x) & (~BITS_LLT_FREE_PAGE_V1_8197F))
+#define BIT_GET_LLT_FREE_PAGE_V1_8197F(x)                                      \
+	(((x) >> BIT_SHIFT_LLT_FREE_PAGE_V1_8197F) &                           \
+	 BIT_MASK_LLT_FREE_PAGE_V1_8197F)
+#define BIT_SET_LLT_FREE_PAGE_V1_8197F(x, v)                                   \
+	(BIT_CLEAR_LLT_FREE_PAGE_V1_8197F(x) | BIT_LLT_FREE_PAGE_V1_8197F(v))
+
+#define BIT_SHIFT_BLK_DESC_NUM_8197F 4
+#define BIT_MASK_BLK_DESC_NUM_8197F 0xf
+#define BIT_BLK_DESC_NUM_8197F(x)                                              \
+	(((x) & BIT_MASK_BLK_DESC_NUM_8197F) << BIT_SHIFT_BLK_DESC_NUM_8197F)
+#define BITS_BLK_DESC_NUM_8197F                                                \
+	(BIT_MASK_BLK_DESC_NUM_8197F << BIT_SHIFT_BLK_DESC_NUM_8197F)
+#define BIT_CLEAR_BLK_DESC_NUM_8197F(x) ((x) & (~BITS_BLK_DESC_NUM_8197F))
+#define BIT_GET_BLK_DESC_NUM_8197F(x)                                          \
+	(((x) >> BIT_SHIFT_BLK_DESC_NUM_8197F) & BIT_MASK_BLK_DESC_NUM_8197F)
+#define BIT_SET_BLK_DESC_NUM_8197F(x, v)                                       \
+	(BIT_CLEAR_BLK_DESC_NUM_8197F(x) | BIT_BLK_DESC_NUM_8197F(v))
+
+#define BIT_R_BCN_HEAD_SEL_8197F BIT(3)
+#define BIT_R_EN_BCN_SW_HEAD_SEL_8197F BIT(2)
+#define BIT_LLT_DBG_SEL_8197F BIT(1)
+#define BIT_AUTO_INIT_LLT_V1_8197F BIT(0)
+
+/* 2 REG_TXDMA_OFFSET_CHK_8197F */
+#define BIT_EM_CHKSUM_FIN_8197F BIT(31)
+#define BIT_EMN_PCIE_DMA_MOD_8197F BIT(30)
+#define BIT_EN_TXQUE_CLR_8197F BIT(29)
+#define BIT_EN_PCIE_FIFO_MODE_8197F BIT(28)
+
+#define BIT_SHIFT_PG_UNDER_TH_V1_8197F 16
+#define BIT_MASK_PG_UNDER_TH_V1_8197F 0xfff
+#define BIT_PG_UNDER_TH_V1_8197F(x)                                            \
+	(((x) & BIT_MASK_PG_UNDER_TH_V1_8197F)                                 \
+	 << BIT_SHIFT_PG_UNDER_TH_V1_8197F)
+#define BITS_PG_UNDER_TH_V1_8197F                                              \
+	(BIT_MASK_PG_UNDER_TH_V1_8197F << BIT_SHIFT_PG_UNDER_TH_V1_8197F)
+#define BIT_CLEAR_PG_UNDER_TH_V1_8197F(x) ((x) & (~BITS_PG_UNDER_TH_V1_8197F))
+#define BIT_GET_PG_UNDER_TH_V1_8197F(x)                                        \
+	(((x) >> BIT_SHIFT_PG_UNDER_TH_V1_8197F) &                             \
+	 BIT_MASK_PG_UNDER_TH_V1_8197F)
+#define BIT_SET_PG_UNDER_TH_V1_8197F(x, v)                                     \
+	(BIT_CLEAR_PG_UNDER_TH_V1_8197F(x) | BIT_PG_UNDER_TH_V1_8197F(v))
+
+#define BIT_EN_RESET_RESTORE_H2C_8197F BIT(15)
+#define BIT_SDIO_TDE_FINISH_8197F BIT(14)
+#define BIT_SDIO_TXDESC_CHKSUM_EN_8197F BIT(13)
+#define BIT_RST_RDPTR_8197F BIT(12)
+#define BIT_RST_WRPTR_8197F BIT(11)
+#define BIT_CHK_PG_TH_EN_8197F BIT(10)
+#define BIT_DROP_DATA_EN_8197F BIT(9)
+#define BIT_CHECK_OFFSET_EN_8197F BIT(8)
+
+#define BIT_SHIFT_CHECK_OFFSET_8197F 0
+#define BIT_MASK_CHECK_OFFSET_8197F 0xff
+#define BIT_CHECK_OFFSET_8197F(x)                                              \
+	(((x) & BIT_MASK_CHECK_OFFSET_8197F) << BIT_SHIFT_CHECK_OFFSET_8197F)
+#define BITS_CHECK_OFFSET_8197F                                                \
+	(BIT_MASK_CHECK_OFFSET_8197F << BIT_SHIFT_CHECK_OFFSET_8197F)
+#define BIT_CLEAR_CHECK_OFFSET_8197F(x) ((x) & (~BITS_CHECK_OFFSET_8197F))
+#define BIT_GET_CHECK_OFFSET_8197F(x)                                          \
+	(((x) >> BIT_SHIFT_CHECK_OFFSET_8197F) & BIT_MASK_CHECK_OFFSET_8197F)
+#define BIT_SET_CHECK_OFFSET_8197F(x, v)                                       \
+	(BIT_CLEAR_CHECK_OFFSET_8197F(x) | BIT_CHECK_OFFSET_8197F(v))
+
+/* 2 REG_TXDMA_STATUS_8197F */
+#define BIT_HI_OQT_UDN_8197F BIT(17)
+#define BIT_HI_OQT_OVF_8197F BIT(16)
+#define BIT_PAYLOAD_CHKSUM_ERR_8197F BIT(15)
+#define BIT_PAYLOAD_UDN_8197F BIT(14)
+#define BIT_PAYLOAD_OVF_8197F BIT(13)
+#define BIT_DSC_CHKSUM_FAIL_8197F BIT(12)
+#define BIT_UNKNOWN_QSEL_8197F BIT(11)
+#define BIT_EP_QSEL_DIFF_8197F BIT(10)
+#define BIT_TX_OFFS_UNMATCH_8197F BIT(9)
+#define BIT_TXOQT_UDN_8197F BIT(8)
+#define BIT_TXOQT_OVF_8197F BIT(7)
+#define BIT_TXDMA_SFF_UDN_8197F BIT(6)
+#define BIT_TXDMA_SFF_OVF_8197F BIT(5)
+#define BIT_LLT_NULL_PG_8197F BIT(4)
+#define BIT_PAGE_UDN_8197F BIT(3)
+#define BIT_PAGE_OVF_8197F BIT(2)
+#define BIT_TXFF_PG_UDN_8197F BIT(1)
+#define BIT_TXFF_PG_OVF_8197F BIT(0)
+
+/* 2 REG_TX_DMA_DBG_8197F */
+
+/* 2 REG_TQPNT1_8197F */
+
+#define BIT_SHIFT_HPQ_HIGH_TH_V1_8197F 16
+#define BIT_MASK_HPQ_HIGH_TH_V1_8197F 0xfff
+#define BIT_HPQ_HIGH_TH_V1_8197F(x)                                            \
+	(((x) & BIT_MASK_HPQ_HIGH_TH_V1_8197F)                                 \
+	 << BIT_SHIFT_HPQ_HIGH_TH_V1_8197F)
+#define BITS_HPQ_HIGH_TH_V1_8197F                                              \
+	(BIT_MASK_HPQ_HIGH_TH_V1_8197F << BIT_SHIFT_HPQ_HIGH_TH_V1_8197F)
+#define BIT_CLEAR_HPQ_HIGH_TH_V1_8197F(x) ((x) & (~BITS_HPQ_HIGH_TH_V1_8197F))
+#define BIT_GET_HPQ_HIGH_TH_V1_8197F(x)                                        \
+	(((x) >> BIT_SHIFT_HPQ_HIGH_TH_V1_8197F) &                             \
+	 BIT_MASK_HPQ_HIGH_TH_V1_8197F)
+#define BIT_SET_HPQ_HIGH_TH_V1_8197F(x, v)                                     \
+	(BIT_CLEAR_HPQ_HIGH_TH_V1_8197F(x) | BIT_HPQ_HIGH_TH_V1_8197F(v))
+
+#define BIT_SHIFT_HPQ_LOW_TH_V1_8197F 0
+#define BIT_MASK_HPQ_LOW_TH_V1_8197F 0xfff
+#define BIT_HPQ_LOW_TH_V1_8197F(x)                                             \
+	(((x) & BIT_MASK_HPQ_LOW_TH_V1_8197F) << BIT_SHIFT_HPQ_LOW_TH_V1_8197F)
+#define BITS_HPQ_LOW_TH_V1_8197F                                               \
+	(BIT_MASK_HPQ_LOW_TH_V1_8197F << BIT_SHIFT_HPQ_LOW_TH_V1_8197F)
+#define BIT_CLEAR_HPQ_LOW_TH_V1_8197F(x) ((x) & (~BITS_HPQ_LOW_TH_V1_8197F))
+#define BIT_GET_HPQ_LOW_TH_V1_8197F(x)                                         \
+	(((x) >> BIT_SHIFT_HPQ_LOW_TH_V1_8197F) & BIT_MASK_HPQ_LOW_TH_V1_8197F)
+#define BIT_SET_HPQ_LOW_TH_V1_8197F(x, v)                                      \
+	(BIT_CLEAR_HPQ_LOW_TH_V1_8197F(x) | BIT_HPQ_LOW_TH_V1_8197F(v))
+
+/* 2 REG_TQPNT2_8197F */
+
+#define BIT_SHIFT_NPQ_HIGH_TH_V1_8197F 16
+#define BIT_MASK_NPQ_HIGH_TH_V1_8197F 0xfff
+#define BIT_NPQ_HIGH_TH_V1_8197F(x)                                            \
+	(((x) & BIT_MASK_NPQ_HIGH_TH_V1_8197F)                                 \
+	 << BIT_SHIFT_NPQ_HIGH_TH_V1_8197F)
+#define BITS_NPQ_HIGH_TH_V1_8197F                                              \
+	(BIT_MASK_NPQ_HIGH_TH_V1_8197F << BIT_SHIFT_NPQ_HIGH_TH_V1_8197F)
+#define BIT_CLEAR_NPQ_HIGH_TH_V1_8197F(x) ((x) & (~BITS_NPQ_HIGH_TH_V1_8197F))
+#define BIT_GET_NPQ_HIGH_TH_V1_8197F(x)                                        \
+	(((x) >> BIT_SHIFT_NPQ_HIGH_TH_V1_8197F) &                             \
+	 BIT_MASK_NPQ_HIGH_TH_V1_8197F)
+#define BIT_SET_NPQ_HIGH_TH_V1_8197F(x, v)                                     \
+	(BIT_CLEAR_NPQ_HIGH_TH_V1_8197F(x) | BIT_NPQ_HIGH_TH_V1_8197F(v))
+
+#define BIT_SHIFT_NPQ_LOW_TH_V1_8197F 0
+#define BIT_MASK_NPQ_LOW_TH_V1_8197F 0xfff
+#define BIT_NPQ_LOW_TH_V1_8197F(x)                                             \
+	(((x) & BIT_MASK_NPQ_LOW_TH_V1_8197F) << BIT_SHIFT_NPQ_LOW_TH_V1_8197F)
+#define BITS_NPQ_LOW_TH_V1_8197F                                               \
+	(BIT_MASK_NPQ_LOW_TH_V1_8197F << BIT_SHIFT_NPQ_LOW_TH_V1_8197F)
+#define BIT_CLEAR_NPQ_LOW_TH_V1_8197F(x) ((x) & (~BITS_NPQ_LOW_TH_V1_8197F))
+#define BIT_GET_NPQ_LOW_TH_V1_8197F(x)                                         \
+	(((x) >> BIT_SHIFT_NPQ_LOW_TH_V1_8197F) & BIT_MASK_NPQ_LOW_TH_V1_8197F)
+#define BIT_SET_NPQ_LOW_TH_V1_8197F(x, v)                                      \
+	(BIT_CLEAR_NPQ_LOW_TH_V1_8197F(x) | BIT_NPQ_LOW_TH_V1_8197F(v))
+
+/* 2 REG_TQPNT3_8197F */
+
+#define BIT_SHIFT_LPQ_HIGH_TH_V1_8197F 16
+#define BIT_MASK_LPQ_HIGH_TH_V1_8197F 0xfff
+#define BIT_LPQ_HIGH_TH_V1_8197F(x)                                            \
+	(((x) & BIT_MASK_LPQ_HIGH_TH_V1_8197F)                                 \
+	 << BIT_SHIFT_LPQ_HIGH_TH_V1_8197F)
+#define BITS_LPQ_HIGH_TH_V1_8197F                                              \
+	(BIT_MASK_LPQ_HIGH_TH_V1_8197F << BIT_SHIFT_LPQ_HIGH_TH_V1_8197F)
+#define BIT_CLEAR_LPQ_HIGH_TH_V1_8197F(x) ((x) & (~BITS_LPQ_HIGH_TH_V1_8197F))
+#define BIT_GET_LPQ_HIGH_TH_V1_8197F(x)                                        \
+	(((x) >> BIT_SHIFT_LPQ_HIGH_TH_V1_8197F) &                             \
+	 BIT_MASK_LPQ_HIGH_TH_V1_8197F)
+#define BIT_SET_LPQ_HIGH_TH_V1_8197F(x, v)                                     \
+	(BIT_CLEAR_LPQ_HIGH_TH_V1_8197F(x) | BIT_LPQ_HIGH_TH_V1_8197F(v))
+
+#define BIT_SHIFT_LPQ_LOW_TH_V1_8197F 0
+#define BIT_MASK_LPQ_LOW_TH_V1_8197F 0xfff
+#define BIT_LPQ_LOW_TH_V1_8197F(x)                                             \
+	(((x) & BIT_MASK_LPQ_LOW_TH_V1_8197F) << BIT_SHIFT_LPQ_LOW_TH_V1_8197F)
+#define BITS_LPQ_LOW_TH_V1_8197F                                               \
+	(BIT_MASK_LPQ_LOW_TH_V1_8197F << BIT_SHIFT_LPQ_LOW_TH_V1_8197F)
+#define BIT_CLEAR_LPQ_LOW_TH_V1_8197F(x) ((x) & (~BITS_LPQ_LOW_TH_V1_8197F))
+#define BIT_GET_LPQ_LOW_TH_V1_8197F(x)                                         \
+	(((x) >> BIT_SHIFT_LPQ_LOW_TH_V1_8197F) & BIT_MASK_LPQ_LOW_TH_V1_8197F)
+#define BIT_SET_LPQ_LOW_TH_V1_8197F(x, v)                                      \
+	(BIT_CLEAR_LPQ_LOW_TH_V1_8197F(x) | BIT_LPQ_LOW_TH_V1_8197F(v))
+
+/* 2 REG_TQPNT4_8197F */
+
+#define BIT_SHIFT_EXQ_HIGH_TH_V1_8197F 16
+#define BIT_MASK_EXQ_HIGH_TH_V1_8197F 0xfff
+#define BIT_EXQ_HIGH_TH_V1_8197F(x)                                            \
+	(((x) & BIT_MASK_EXQ_HIGH_TH_V1_8197F)                                 \
+	 << BIT_SHIFT_EXQ_HIGH_TH_V1_8197F)
+#define BITS_EXQ_HIGH_TH_V1_8197F                                              \
+	(BIT_MASK_EXQ_HIGH_TH_V1_8197F << BIT_SHIFT_EXQ_HIGH_TH_V1_8197F)
+#define BIT_CLEAR_EXQ_HIGH_TH_V1_8197F(x) ((x) & (~BITS_EXQ_HIGH_TH_V1_8197F))
+#define BIT_GET_EXQ_HIGH_TH_V1_8197F(x)                                        \
+	(((x) >> BIT_SHIFT_EXQ_HIGH_TH_V1_8197F) &                             \
+	 BIT_MASK_EXQ_HIGH_TH_V1_8197F)
+#define BIT_SET_EXQ_HIGH_TH_V1_8197F(x, v)                                     \
+	(BIT_CLEAR_EXQ_HIGH_TH_V1_8197F(x) | BIT_EXQ_HIGH_TH_V1_8197F(v))
+
+#define BIT_SHIFT_EXQ_LOW_TH_V1_8197F 0
+#define BIT_MASK_EXQ_LOW_TH_V1_8197F 0xfff
+#define BIT_EXQ_LOW_TH_V1_8197F(x)                                             \
+	(((x) & BIT_MASK_EXQ_LOW_TH_V1_8197F) << BIT_SHIFT_EXQ_LOW_TH_V1_8197F)
+#define BITS_EXQ_LOW_TH_V1_8197F                                               \
+	(BIT_MASK_EXQ_LOW_TH_V1_8197F << BIT_SHIFT_EXQ_LOW_TH_V1_8197F)
+#define BIT_CLEAR_EXQ_LOW_TH_V1_8197F(x) ((x) & (~BITS_EXQ_LOW_TH_V1_8197F))
+#define BIT_GET_EXQ_LOW_TH_V1_8197F(x)                                         \
+	(((x) >> BIT_SHIFT_EXQ_LOW_TH_V1_8197F) & BIT_MASK_EXQ_LOW_TH_V1_8197F)
+#define BIT_SET_EXQ_LOW_TH_V1_8197F(x, v)                                      \
+	(BIT_CLEAR_EXQ_LOW_TH_V1_8197F(x) | BIT_EXQ_LOW_TH_V1_8197F(v))
+
+/* 2 REG_RQPN_CTRL_1_8197F */
+
+#define BIT_SHIFT_TXPKTNUM_H_8197F 16
+#define BIT_MASK_TXPKTNUM_H_8197F 0xffff
+#define BIT_TXPKTNUM_H_8197F(x)                                                \
+	(((x) & BIT_MASK_TXPKTNUM_H_8197F) << BIT_SHIFT_TXPKTNUM_H_8197F)
+#define BITS_TXPKTNUM_H_8197F                                                  \
+	(BIT_MASK_TXPKTNUM_H_8197F << BIT_SHIFT_TXPKTNUM_H_8197F)
+#define BIT_CLEAR_TXPKTNUM_H_8197F(x) ((x) & (~BITS_TXPKTNUM_H_8197F))
+#define BIT_GET_TXPKTNUM_H_8197F(x)                                            \
+	(((x) >> BIT_SHIFT_TXPKTNUM_H_8197F) & BIT_MASK_TXPKTNUM_H_8197F)
+#define BIT_SET_TXPKTNUM_H_8197F(x, v)                                         \
+	(BIT_CLEAR_TXPKTNUM_H_8197F(x) | BIT_TXPKTNUM_H_8197F(v))
+
+#define BIT_SHIFT_TXPKTNUM_H_V1_8197F 0
+#define BIT_MASK_TXPKTNUM_H_V1_8197F 0xffff
+#define BIT_TXPKTNUM_H_V1_8197F(x)                                             \
+	(((x) & BIT_MASK_TXPKTNUM_H_V1_8197F) << BIT_SHIFT_TXPKTNUM_H_V1_8197F)
+#define BITS_TXPKTNUM_H_V1_8197F                                               \
+	(BIT_MASK_TXPKTNUM_H_V1_8197F << BIT_SHIFT_TXPKTNUM_H_V1_8197F)
+#define BIT_CLEAR_TXPKTNUM_H_V1_8197F(x) ((x) & (~BITS_TXPKTNUM_H_V1_8197F))
+#define BIT_GET_TXPKTNUM_H_V1_8197F(x)                                         \
+	(((x) >> BIT_SHIFT_TXPKTNUM_H_V1_8197F) & BIT_MASK_TXPKTNUM_H_V1_8197F)
+#define BIT_SET_TXPKTNUM_H_V1_8197F(x, v)                                      \
+	(BIT_CLEAR_TXPKTNUM_H_V1_8197F(x) | BIT_TXPKTNUM_H_V1_8197F(v))
+
+/* 2 REG_RQPN_CTRL_2_8197F */
+#define BIT_LD_RQPN_8197F BIT(31)
+#define BIT_EXQ_PUBLIC_DIS_V1_8197F BIT(19)
+#define BIT_NPQ_PUBLIC_DIS_V1_8197F BIT(18)
+#define BIT_LPQ_PUBLIC_DIS_V1_8197F BIT(17)
+#define BIT_HPQ_PUBLIC_DIS_V1_8197F BIT(16)
+
+/* 2 REG_FIFOPAGE_INFO_1_8197F */
+
+#define BIT_SHIFT_HPQ_AVAL_PG_V1_8197F 16
+#define BIT_MASK_HPQ_AVAL_PG_V1_8197F 0xfff
+#define BIT_HPQ_AVAL_PG_V1_8197F(x)                                            \
+	(((x) & BIT_MASK_HPQ_AVAL_PG_V1_8197F)                                 \
+	 << BIT_SHIFT_HPQ_AVAL_PG_V1_8197F)
+#define BITS_HPQ_AVAL_PG_V1_8197F                                              \
+	(BIT_MASK_HPQ_AVAL_PG_V1_8197F << BIT_SHIFT_HPQ_AVAL_PG_V1_8197F)
+#define BIT_CLEAR_HPQ_AVAL_PG_V1_8197F(x) ((x) & (~BITS_HPQ_AVAL_PG_V1_8197F))
+#define BIT_GET_HPQ_AVAL_PG_V1_8197F(x)                                        \
+	(((x) >> BIT_SHIFT_HPQ_AVAL_PG_V1_8197F) &                             \
+	 BIT_MASK_HPQ_AVAL_PG_V1_8197F)
+#define BIT_SET_HPQ_AVAL_PG_V1_8197F(x, v)                                     \
+	(BIT_CLEAR_HPQ_AVAL_PG_V1_8197F(x) | BIT_HPQ_AVAL_PG_V1_8197F(v))
+
+#define BIT_SHIFT_HPQ_V1_8197F 0
+#define BIT_MASK_HPQ_V1_8197F 0xfff
+#define BIT_HPQ_V1_8197F(x)                                                    \
+	(((x) & BIT_MASK_HPQ_V1_8197F) << BIT_SHIFT_HPQ_V1_8197F)
+#define BITS_HPQ_V1_8197F (BIT_MASK_HPQ_V1_8197F << BIT_SHIFT_HPQ_V1_8197F)
+#define BIT_CLEAR_HPQ_V1_8197F(x) ((x) & (~BITS_HPQ_V1_8197F))
+#define BIT_GET_HPQ_V1_8197F(x)                                                \
+	(((x) >> BIT_SHIFT_HPQ_V1_8197F) & BIT_MASK_HPQ_V1_8197F)
+#define BIT_SET_HPQ_V1_8197F(x, v)                                             \
+	(BIT_CLEAR_HPQ_V1_8197F(x) | BIT_HPQ_V1_8197F(v))
+
+/* 2 REG_FIFOPAGE_INFO_2_8197F */
+
+#define BIT_SHIFT_LPQ_AVAL_PG_V1_8197F 16
+#define BIT_MASK_LPQ_AVAL_PG_V1_8197F 0xfff
+#define BIT_LPQ_AVAL_PG_V1_8197F(x)                                            \
+	(((x) & BIT_MASK_LPQ_AVAL_PG_V1_8197F)                                 \
+	 << BIT_SHIFT_LPQ_AVAL_PG_V1_8197F)
+#define BITS_LPQ_AVAL_PG_V1_8197F                                              \
+	(BIT_MASK_LPQ_AVAL_PG_V1_8197F << BIT_SHIFT_LPQ_AVAL_PG_V1_8197F)
+#define BIT_CLEAR_LPQ_AVAL_PG_V1_8197F(x) ((x) & (~BITS_LPQ_AVAL_PG_V1_8197F))
+#define BIT_GET_LPQ_AVAL_PG_V1_8197F(x)                                        \
+	(((x) >> BIT_SHIFT_LPQ_AVAL_PG_V1_8197F) &                             \
+	 BIT_MASK_LPQ_AVAL_PG_V1_8197F)
+#define BIT_SET_LPQ_AVAL_PG_V1_8197F(x, v)                                     \
+	(BIT_CLEAR_LPQ_AVAL_PG_V1_8197F(x) | BIT_LPQ_AVAL_PG_V1_8197F(v))
+
+#define BIT_SHIFT_LPQ_V1_8197F 0
+#define BIT_MASK_LPQ_V1_8197F 0xfff
+#define BIT_LPQ_V1_8197F(x)                                                    \
+	(((x) & BIT_MASK_LPQ_V1_8197F) << BIT_SHIFT_LPQ_V1_8197F)
+#define BITS_LPQ_V1_8197F (BIT_MASK_LPQ_V1_8197F << BIT_SHIFT_LPQ_V1_8197F)
+#define BIT_CLEAR_LPQ_V1_8197F(x) ((x) & (~BITS_LPQ_V1_8197F))
+#define BIT_GET_LPQ_V1_8197F(x)                                                \
+	(((x) >> BIT_SHIFT_LPQ_V1_8197F) & BIT_MASK_LPQ_V1_8197F)
+#define BIT_SET_LPQ_V1_8197F(x, v)                                             \
+	(BIT_CLEAR_LPQ_V1_8197F(x) | BIT_LPQ_V1_8197F(v))
+
+/* 2 REG_FIFOPAGE_INFO_3_8197F */
+
+#define BIT_SHIFT_NPQ_AVAL_PG_V1_8197F 16
+#define BIT_MASK_NPQ_AVAL_PG_V1_8197F 0xfff
+#define BIT_NPQ_AVAL_PG_V1_8197F(x)                                            \
+	(((x) & BIT_MASK_NPQ_AVAL_PG_V1_8197F)                                 \
+	 << BIT_SHIFT_NPQ_AVAL_PG_V1_8197F)
+#define BITS_NPQ_AVAL_PG_V1_8197F                                              \
+	(BIT_MASK_NPQ_AVAL_PG_V1_8197F << BIT_SHIFT_NPQ_AVAL_PG_V1_8197F)
+#define BIT_CLEAR_NPQ_AVAL_PG_V1_8197F(x) ((x) & (~BITS_NPQ_AVAL_PG_V1_8197F))
+#define BIT_GET_NPQ_AVAL_PG_V1_8197F(x)                                        \
+	(((x) >> BIT_SHIFT_NPQ_AVAL_PG_V1_8197F) &                             \
+	 BIT_MASK_NPQ_AVAL_PG_V1_8197F)
+#define BIT_SET_NPQ_AVAL_PG_V1_8197F(x, v)                                     \
+	(BIT_CLEAR_NPQ_AVAL_PG_V1_8197F(x) | BIT_NPQ_AVAL_PG_V1_8197F(v))
+
+#define BIT_SHIFT_NPQ_V1_8197F 0
+#define BIT_MASK_NPQ_V1_8197F 0xfff
+#define BIT_NPQ_V1_8197F(x)                                                    \
+	(((x) & BIT_MASK_NPQ_V1_8197F) << BIT_SHIFT_NPQ_V1_8197F)
+#define BITS_NPQ_V1_8197F (BIT_MASK_NPQ_V1_8197F << BIT_SHIFT_NPQ_V1_8197F)
+#define BIT_CLEAR_NPQ_V1_8197F(x) ((x) & (~BITS_NPQ_V1_8197F))
+#define BIT_GET_NPQ_V1_8197F(x)                                                \
+	(((x) >> BIT_SHIFT_NPQ_V1_8197F) & BIT_MASK_NPQ_V1_8197F)
+#define BIT_SET_NPQ_V1_8197F(x, v)                                             \
+	(BIT_CLEAR_NPQ_V1_8197F(x) | BIT_NPQ_V1_8197F(v))
+
+/* 2 REG_FIFOPAGE_INFO_4_8197F */
+
+#define BIT_SHIFT_EXQ_AVAL_PG_V1_8197F 16
+#define BIT_MASK_EXQ_AVAL_PG_V1_8197F 0xfff
+#define BIT_EXQ_AVAL_PG_V1_8197F(x)                                            \
+	(((x) & BIT_MASK_EXQ_AVAL_PG_V1_8197F)                                 \
+	 << BIT_SHIFT_EXQ_AVAL_PG_V1_8197F)
+#define BITS_EXQ_AVAL_PG_V1_8197F                                              \
+	(BIT_MASK_EXQ_AVAL_PG_V1_8197F << BIT_SHIFT_EXQ_AVAL_PG_V1_8197F)
+#define BIT_CLEAR_EXQ_AVAL_PG_V1_8197F(x) ((x) & (~BITS_EXQ_AVAL_PG_V1_8197F))
+#define BIT_GET_EXQ_AVAL_PG_V1_8197F(x)                                        \
+	(((x) >> BIT_SHIFT_EXQ_AVAL_PG_V1_8197F) &                             \
+	 BIT_MASK_EXQ_AVAL_PG_V1_8197F)
+#define BIT_SET_EXQ_AVAL_PG_V1_8197F(x, v)                                     \
+	(BIT_CLEAR_EXQ_AVAL_PG_V1_8197F(x) | BIT_EXQ_AVAL_PG_V1_8197F(v))
+
+#define BIT_SHIFT_EXQ_V1_8197F 0
+#define BIT_MASK_EXQ_V1_8197F 0xfff
+#define BIT_EXQ_V1_8197F(x)                                                    \
+	(((x) & BIT_MASK_EXQ_V1_8197F) << BIT_SHIFT_EXQ_V1_8197F)
+#define BITS_EXQ_V1_8197F (BIT_MASK_EXQ_V1_8197F << BIT_SHIFT_EXQ_V1_8197F)
+#define BIT_CLEAR_EXQ_V1_8197F(x) ((x) & (~BITS_EXQ_V1_8197F))
+#define BIT_GET_EXQ_V1_8197F(x)                                                \
+	(((x) >> BIT_SHIFT_EXQ_V1_8197F) & BIT_MASK_EXQ_V1_8197F)
+#define BIT_SET_EXQ_V1_8197F(x, v)                                             \
+	(BIT_CLEAR_EXQ_V1_8197F(x) | BIT_EXQ_V1_8197F(v))
+
+/* 2 REG_FIFOPAGE_INFO_5_8197F */
+
+#define BIT_SHIFT_PUBQ_AVAL_PG_V1_8197F 16
+#define BIT_MASK_PUBQ_AVAL_PG_V1_8197F 0xfff
+#define BIT_PUBQ_AVAL_PG_V1_8197F(x)                                           \
+	(((x) & BIT_MASK_PUBQ_AVAL_PG_V1_8197F)                                \
+	 << BIT_SHIFT_PUBQ_AVAL_PG_V1_8197F)
+#define BITS_PUBQ_AVAL_PG_V1_8197F                                             \
+	(BIT_MASK_PUBQ_AVAL_PG_V1_8197F << BIT_SHIFT_PUBQ_AVAL_PG_V1_8197F)
+#define BIT_CLEAR_PUBQ_AVAL_PG_V1_8197F(x) ((x) & (~BITS_PUBQ_AVAL_PG_V1_8197F))
+#define BIT_GET_PUBQ_AVAL_PG_V1_8197F(x)                                       \
+	(((x) >> BIT_SHIFT_PUBQ_AVAL_PG_V1_8197F) &                            \
+	 BIT_MASK_PUBQ_AVAL_PG_V1_8197F)
+#define BIT_SET_PUBQ_AVAL_PG_V1_8197F(x, v)                                    \
+	(BIT_CLEAR_PUBQ_AVAL_PG_V1_8197F(x) | BIT_PUBQ_AVAL_PG_V1_8197F(v))
+
+#define BIT_SHIFT_PUBQ_V1_8197F 0
+#define BIT_MASK_PUBQ_V1_8197F 0xfff
+#define BIT_PUBQ_V1_8197F(x)                                                   \
+	(((x) & BIT_MASK_PUBQ_V1_8197F) << BIT_SHIFT_PUBQ_V1_8197F)
+#define BITS_PUBQ_V1_8197F (BIT_MASK_PUBQ_V1_8197F << BIT_SHIFT_PUBQ_V1_8197F)
+#define BIT_CLEAR_PUBQ_V1_8197F(x) ((x) & (~BITS_PUBQ_V1_8197F))
+#define BIT_GET_PUBQ_V1_8197F(x)                                               \
+	(((x) >> BIT_SHIFT_PUBQ_V1_8197F) & BIT_MASK_PUBQ_V1_8197F)
+#define BIT_SET_PUBQ_V1_8197F(x, v)                                            \
+	(BIT_CLEAR_PUBQ_V1_8197F(x) | BIT_PUBQ_V1_8197F(v))
+
+/* 2 REG_H2C_HEAD_8197F */
+
+#define BIT_SHIFT_H2C_HEAD_8197F 0
+#define BIT_MASK_H2C_HEAD_8197F 0x3ffff
+#define BIT_H2C_HEAD_8197F(x)                                                  \
+	(((x) & BIT_MASK_H2C_HEAD_8197F) << BIT_SHIFT_H2C_HEAD_8197F)
+#define BITS_H2C_HEAD_8197F                                                    \
+	(BIT_MASK_H2C_HEAD_8197F << BIT_SHIFT_H2C_HEAD_8197F)
+#define BIT_CLEAR_H2C_HEAD_8197F(x) ((x) & (~BITS_H2C_HEAD_8197F))
+#define BIT_GET_H2C_HEAD_8197F(x)                                              \
+	(((x) >> BIT_SHIFT_H2C_HEAD_8197F) & BIT_MASK_H2C_HEAD_8197F)
+#define BIT_SET_H2C_HEAD_8197F(x, v)                                           \
+	(BIT_CLEAR_H2C_HEAD_8197F(x) | BIT_H2C_HEAD_8197F(v))
+
+/* 2 REG_H2C_TAIL_8197F */
+
+#define BIT_SHIFT_H2C_TAIL_8197F 0
+#define BIT_MASK_H2C_TAIL_8197F 0x3ffff
+#define BIT_H2C_TAIL_8197F(x)                                                  \
+	(((x) & BIT_MASK_H2C_TAIL_8197F) << BIT_SHIFT_H2C_TAIL_8197F)
+#define BITS_H2C_TAIL_8197F                                                    \
+	(BIT_MASK_H2C_TAIL_8197F << BIT_SHIFT_H2C_TAIL_8197F)
+#define BIT_CLEAR_H2C_TAIL_8197F(x) ((x) & (~BITS_H2C_TAIL_8197F))
+#define BIT_GET_H2C_TAIL_8197F(x)                                              \
+	(((x) >> BIT_SHIFT_H2C_TAIL_8197F) & BIT_MASK_H2C_TAIL_8197F)
+#define BIT_SET_H2C_TAIL_8197F(x, v)                                           \
+	(BIT_CLEAR_H2C_TAIL_8197F(x) | BIT_H2C_TAIL_8197F(v))
+
+/* 2 REG_H2C_READ_ADDR_8197F */
+
+#define BIT_SHIFT_H2C_READ_ADDR_8197F 0
+#define BIT_MASK_H2C_READ_ADDR_8197F 0x3ffff
+#define BIT_H2C_READ_ADDR_8197F(x)                                             \
+	(((x) & BIT_MASK_H2C_READ_ADDR_8197F) << BIT_SHIFT_H2C_READ_ADDR_8197F)
+#define BITS_H2C_READ_ADDR_8197F                                               \
+	(BIT_MASK_H2C_READ_ADDR_8197F << BIT_SHIFT_H2C_READ_ADDR_8197F)
+#define BIT_CLEAR_H2C_READ_ADDR_8197F(x) ((x) & (~BITS_H2C_READ_ADDR_8197F))
+#define BIT_GET_H2C_READ_ADDR_8197F(x)                                         \
+	(((x) >> BIT_SHIFT_H2C_READ_ADDR_8197F) & BIT_MASK_H2C_READ_ADDR_8197F)
+#define BIT_SET_H2C_READ_ADDR_8197F(x, v)                                      \
+	(BIT_CLEAR_H2C_READ_ADDR_8197F(x) | BIT_H2C_READ_ADDR_8197F(v))
+
+/* 2 REG_H2C_WR_ADDR_8197F */
+
+#define BIT_SHIFT_H2C_WR_ADDR_8197F 0
+#define BIT_MASK_H2C_WR_ADDR_8197F 0x3ffff
+#define BIT_H2C_WR_ADDR_8197F(x)                                               \
+	(((x) & BIT_MASK_H2C_WR_ADDR_8197F) << BIT_SHIFT_H2C_WR_ADDR_8197F)
+#define BITS_H2C_WR_ADDR_8197F                                                 \
+	(BIT_MASK_H2C_WR_ADDR_8197F << BIT_SHIFT_H2C_WR_ADDR_8197F)
+#define BIT_CLEAR_H2C_WR_ADDR_8197F(x) ((x) & (~BITS_H2C_WR_ADDR_8197F))
+#define BIT_GET_H2C_WR_ADDR_8197F(x)                                           \
+	(((x) >> BIT_SHIFT_H2C_WR_ADDR_8197F) & BIT_MASK_H2C_WR_ADDR_8197F)
+#define BIT_SET_H2C_WR_ADDR_8197F(x, v)                                        \
+	(BIT_CLEAR_H2C_WR_ADDR_8197F(x) | BIT_H2C_WR_ADDR_8197F(v))
+
+/* 2 REG_H2C_INFO_8197F */
+#define BIT_EXQ_EN_PUBLIC_LIMIT_8197F BIT(11)
+#define BIT_NPQ_EN_PUBLIC_LIMIT_8197F BIT(10)
+#define BIT_LPQ_EN_PUBLIC_LIMIT_8197F BIT(9)
+#define BIT_HPQ_EN_PUBLIC_LIMIT_8197F BIT(8)
+#define BIT_H2C_SPACE_VLD_8197F BIT(3)
+#define BIT_H2C_WR_ADDR_RST_8197F BIT(2)
+
+#define BIT_SHIFT_H2C_LEN_SEL_8197F 0
+#define BIT_MASK_H2C_LEN_SEL_8197F 0x3
+#define BIT_H2C_LEN_SEL_8197F(x)                                               \
+	(((x) & BIT_MASK_H2C_LEN_SEL_8197F) << BIT_SHIFT_H2C_LEN_SEL_8197F)
+#define BITS_H2C_LEN_SEL_8197F                                                 \
+	(BIT_MASK_H2C_LEN_SEL_8197F << BIT_SHIFT_H2C_LEN_SEL_8197F)
+#define BIT_CLEAR_H2C_LEN_SEL_8197F(x) ((x) & (~BITS_H2C_LEN_SEL_8197F))
+#define BIT_GET_H2C_LEN_SEL_8197F(x)                                           \
+	(((x) >> BIT_SHIFT_H2C_LEN_SEL_8197F) & BIT_MASK_H2C_LEN_SEL_8197F)
+#define BIT_SET_H2C_LEN_SEL_8197F(x, v)                                        \
+	(BIT_CLEAR_H2C_LEN_SEL_8197F(x) | BIT_H2C_LEN_SEL_8197F(v))
+
+#define BIT_SHIFT_VI_PUB_LIMIT_8197F 16
+#define BIT_MASK_VI_PUB_LIMIT_8197F 0xfff
+#define BIT_VI_PUB_LIMIT_8197F(x)                                              \
+	(((x) & BIT_MASK_VI_PUB_LIMIT_8197F) << BIT_SHIFT_VI_PUB_LIMIT_8197F)
+#define BITS_VI_PUB_LIMIT_8197F                                                \
+	(BIT_MASK_VI_PUB_LIMIT_8197F << BIT_SHIFT_VI_PUB_LIMIT_8197F)
+#define BIT_CLEAR_VI_PUB_LIMIT_8197F(x) ((x) & (~BITS_VI_PUB_LIMIT_8197F))
+#define BIT_GET_VI_PUB_LIMIT_8197F(x)                                          \
+	(((x) >> BIT_SHIFT_VI_PUB_LIMIT_8197F) & BIT_MASK_VI_PUB_LIMIT_8197F)
+#define BIT_SET_VI_PUB_LIMIT_8197F(x, v)                                       \
+	(BIT_CLEAR_VI_PUB_LIMIT_8197F(x) | BIT_VI_PUB_LIMIT_8197F(v))
+
+#define BIT_SHIFT_VO_PUB_LIMIT_8197F 0
+#define BIT_MASK_VO_PUB_LIMIT_8197F 0xfff
+#define BIT_VO_PUB_LIMIT_8197F(x)                                              \
+	(((x) & BIT_MASK_VO_PUB_LIMIT_8197F) << BIT_SHIFT_VO_PUB_LIMIT_8197F)
+#define BITS_VO_PUB_LIMIT_8197F                                                \
+	(BIT_MASK_VO_PUB_LIMIT_8197F << BIT_SHIFT_VO_PUB_LIMIT_8197F)
+#define BIT_CLEAR_VO_PUB_LIMIT_8197F(x) ((x) & (~BITS_VO_PUB_LIMIT_8197F))
+#define BIT_GET_VO_PUB_LIMIT_8197F(x)                                          \
+	(((x) >> BIT_SHIFT_VO_PUB_LIMIT_8197F) & BIT_MASK_VO_PUB_LIMIT_8197F)
+#define BIT_SET_VO_PUB_LIMIT_8197F(x, v)                                       \
+	(BIT_CLEAR_VO_PUB_LIMIT_8197F(x) | BIT_VO_PUB_LIMIT_8197F(v))
+
+#define BIT_SHIFT_BK_PUB_LIMIT_8197F 16
+#define BIT_MASK_BK_PUB_LIMIT_8197F 0xfff
+#define BIT_BK_PUB_LIMIT_8197F(x)                                              \
+	(((x) & BIT_MASK_BK_PUB_LIMIT_8197F) << BIT_SHIFT_BK_PUB_LIMIT_8197F)
+#define BITS_BK_PUB_LIMIT_8197F                                                \
+	(BIT_MASK_BK_PUB_LIMIT_8197F << BIT_SHIFT_BK_PUB_LIMIT_8197F)
+#define BIT_CLEAR_BK_PUB_LIMIT_8197F(x) ((x) & (~BITS_BK_PUB_LIMIT_8197F))
+#define BIT_GET_BK_PUB_LIMIT_8197F(x)                                          \
+	(((x) >> BIT_SHIFT_BK_PUB_LIMIT_8197F) & BIT_MASK_BK_PUB_LIMIT_8197F)
+#define BIT_SET_BK_PUB_LIMIT_8197F(x, v)                                       \
+	(BIT_CLEAR_BK_PUB_LIMIT_8197F(x) | BIT_BK_PUB_LIMIT_8197F(v))
+
+#define BIT_SHIFT_BE_PUB_LIMIT_8197F 0
+#define BIT_MASK_BE_PUB_LIMIT_8197F 0xfff
+#define BIT_BE_PUB_LIMIT_8197F(x)                                              \
+	(((x) & BIT_MASK_BE_PUB_LIMIT_8197F) << BIT_SHIFT_BE_PUB_LIMIT_8197F)
+#define BITS_BE_PUB_LIMIT_8197F                                                \
+	(BIT_MASK_BE_PUB_LIMIT_8197F << BIT_SHIFT_BE_PUB_LIMIT_8197F)
+#define BIT_CLEAR_BE_PUB_LIMIT_8197F(x) ((x) & (~BITS_BE_PUB_LIMIT_8197F))
+#define BIT_GET_BE_PUB_LIMIT_8197F(x)                                          \
+	(((x) >> BIT_SHIFT_BE_PUB_LIMIT_8197F) & BIT_MASK_BE_PUB_LIMIT_8197F)
+#define BIT_SET_BE_PUB_LIMIT_8197F(x, v)                                       \
+	(BIT_CLEAR_BE_PUB_LIMIT_8197F(x) | BIT_BE_PUB_LIMIT_8197F(v))
+
+/* 2 REG_RXDMA_AGG_PG_TH_8197F */
+#define BIT_DMA_STORE_MODE_8197F BIT(31)
+#define BIT_EN_FW_ADD_8197F BIT(30)
+#define BIT_EN_PRE_CALC_8197F BIT(29)
+#define BIT_RXAGG_SW_EN_8197F BIT(28)
+
+#define BIT_SHIFT_PKT_NUM_WOL_8197F 16
+#define BIT_MASK_PKT_NUM_WOL_8197F 0xff
+#define BIT_PKT_NUM_WOL_8197F(x)                                               \
+	(((x) & BIT_MASK_PKT_NUM_WOL_8197F) << BIT_SHIFT_PKT_NUM_WOL_8197F)
+#define BITS_PKT_NUM_WOL_8197F                                                 \
+	(BIT_MASK_PKT_NUM_WOL_8197F << BIT_SHIFT_PKT_NUM_WOL_8197F)
+#define BIT_CLEAR_PKT_NUM_WOL_8197F(x) ((x) & (~BITS_PKT_NUM_WOL_8197F))
+#define BIT_GET_PKT_NUM_WOL_8197F(x)                                           \
+	(((x) >> BIT_SHIFT_PKT_NUM_WOL_8197F) & BIT_MASK_PKT_NUM_WOL_8197F)
+#define BIT_SET_PKT_NUM_WOL_8197F(x, v)                                        \
+	(BIT_CLEAR_PKT_NUM_WOL_8197F(x) | BIT_PKT_NUM_WOL_8197F(v))
+
+#define BIT_SHIFT_DMA_AGG_TO_V1_8197F 8
+#define BIT_MASK_DMA_AGG_TO_V1_8197F 0xff
+#define BIT_DMA_AGG_TO_V1_8197F(x)                                             \
+	(((x) & BIT_MASK_DMA_AGG_TO_V1_8197F) << BIT_SHIFT_DMA_AGG_TO_V1_8197F)
+#define BITS_DMA_AGG_TO_V1_8197F                                               \
+	(BIT_MASK_DMA_AGG_TO_V1_8197F << BIT_SHIFT_DMA_AGG_TO_V1_8197F)
+#define BIT_CLEAR_DMA_AGG_TO_V1_8197F(x) ((x) & (~BITS_DMA_AGG_TO_V1_8197F))
+#define BIT_GET_DMA_AGG_TO_V1_8197F(x)                                         \
+	(((x) >> BIT_SHIFT_DMA_AGG_TO_V1_8197F) & BIT_MASK_DMA_AGG_TO_V1_8197F)
+#define BIT_SET_DMA_AGG_TO_V1_8197F(x, v)                                      \
+	(BIT_CLEAR_DMA_AGG_TO_V1_8197F(x) | BIT_DMA_AGG_TO_V1_8197F(v))
+
+#define BIT_SHIFT_RXDMA_AGG_PG_TH_8197F 0
+#define BIT_MASK_RXDMA_AGG_PG_TH_8197F 0xff
+#define BIT_RXDMA_AGG_PG_TH_8197F(x)                                           \
+	(((x) & BIT_MASK_RXDMA_AGG_PG_TH_8197F)                                \
+	 << BIT_SHIFT_RXDMA_AGG_PG_TH_8197F)
+#define BITS_RXDMA_AGG_PG_TH_8197F                                             \
+	(BIT_MASK_RXDMA_AGG_PG_TH_8197F << BIT_SHIFT_RXDMA_AGG_PG_TH_8197F)
+#define BIT_CLEAR_RXDMA_AGG_PG_TH_8197F(x) ((x) & (~BITS_RXDMA_AGG_PG_TH_8197F))
+#define BIT_GET_RXDMA_AGG_PG_TH_8197F(x)                                       \
+	(((x) >> BIT_SHIFT_RXDMA_AGG_PG_TH_8197F) &                            \
+	 BIT_MASK_RXDMA_AGG_PG_TH_8197F)
+#define BIT_SET_RXDMA_AGG_PG_TH_8197F(x, v)                                    \
+	(BIT_CLEAR_RXDMA_AGG_PG_TH_8197F(x) | BIT_RXDMA_AGG_PG_TH_8197F(v))
+
+/* 2 REG_RXPKT_NUM_8197F */
+
+#define BIT_SHIFT_RXPKT_NUM_8197F 24
+#define BIT_MASK_RXPKT_NUM_8197F 0xff
+#define BIT_RXPKT_NUM_8197F(x)                                                 \
+	(((x) & BIT_MASK_RXPKT_NUM_8197F) << BIT_SHIFT_RXPKT_NUM_8197F)
+#define BITS_RXPKT_NUM_8197F                                                   \
+	(BIT_MASK_RXPKT_NUM_8197F << BIT_SHIFT_RXPKT_NUM_8197F)
+#define BIT_CLEAR_RXPKT_NUM_8197F(x) ((x) & (~BITS_RXPKT_NUM_8197F))
+#define BIT_GET_RXPKT_NUM_8197F(x)                                             \
+	(((x) >> BIT_SHIFT_RXPKT_NUM_8197F) & BIT_MASK_RXPKT_NUM_8197F)
+#define BIT_SET_RXPKT_NUM_8197F(x, v)                                          \
+	(BIT_CLEAR_RXPKT_NUM_8197F(x) | BIT_RXPKT_NUM_8197F(v))
+
+#define BIT_SHIFT_FW_UPD_RDPTR19_TO_16_8197F 20
+#define BIT_MASK_FW_UPD_RDPTR19_TO_16_8197F 0xf
+#define BIT_FW_UPD_RDPTR19_TO_16_8197F(x)                                      \
+	(((x) & BIT_MASK_FW_UPD_RDPTR19_TO_16_8197F)                           \
+	 << BIT_SHIFT_FW_UPD_RDPTR19_TO_16_8197F)
+#define BITS_FW_UPD_RDPTR19_TO_16_8197F                                        \
+	(BIT_MASK_FW_UPD_RDPTR19_TO_16_8197F                                   \
+	 << BIT_SHIFT_FW_UPD_RDPTR19_TO_16_8197F)
+#define BIT_CLEAR_FW_UPD_RDPTR19_TO_16_8197F(x)                                \
+	((x) & (~BITS_FW_UPD_RDPTR19_TO_16_8197F))
+#define BIT_GET_FW_UPD_RDPTR19_TO_16_8197F(x)                                  \
+	(((x) >> BIT_SHIFT_FW_UPD_RDPTR19_TO_16_8197F) &                       \
+	 BIT_MASK_FW_UPD_RDPTR19_TO_16_8197F)
+#define BIT_SET_FW_UPD_RDPTR19_TO_16_8197F(x, v)                               \
+	(BIT_CLEAR_FW_UPD_RDPTR19_TO_16_8197F(x) |                             \
+	 BIT_FW_UPD_RDPTR19_TO_16_8197F(v))
+
+#define BIT_RXDMA_REQ_8197F BIT(19)
+#define BIT_RW_RELEASE_EN_8197F BIT(18)
+#define BIT_RXDMA_IDLE_8197F BIT(17)
+#define BIT_RXPKT_RELEASE_POLL_8197F BIT(16)
+
+#define BIT_SHIFT_FW_UPD_RDPTR_8197F 0
+#define BIT_MASK_FW_UPD_RDPTR_8197F 0xffff
+#define BIT_FW_UPD_RDPTR_8197F(x)                                              \
+	(((x) & BIT_MASK_FW_UPD_RDPTR_8197F) << BIT_SHIFT_FW_UPD_RDPTR_8197F)
+#define BITS_FW_UPD_RDPTR_8197F                                                \
+	(BIT_MASK_FW_UPD_RDPTR_8197F << BIT_SHIFT_FW_UPD_RDPTR_8197F)
+#define BIT_CLEAR_FW_UPD_RDPTR_8197F(x) ((x) & (~BITS_FW_UPD_RDPTR_8197F))
+#define BIT_GET_FW_UPD_RDPTR_8197F(x)                                          \
+	(((x) >> BIT_SHIFT_FW_UPD_RDPTR_8197F) & BIT_MASK_FW_UPD_RDPTR_8197F)
+#define BIT_SET_FW_UPD_RDPTR_8197F(x, v)                                       \
+	(BIT_CLEAR_FW_UPD_RDPTR_8197F(x) | BIT_FW_UPD_RDPTR_8197F(v))
+
+/* 2 REG_RXDMA_STATUS_8197F */
+#define BIT_FC2H_PKT_OVERFLOW_8197F BIT(8)
+#define BIT_C2H_PKT_OVF_8197F BIT(7)
+#define BIT_AGG_CONFGI_ISSUE_8197F BIT(6)
+#define BIT_FW_POLL_ISSUE_8197F BIT(5)
+#define BIT_RX_DATA_UDN_8197F BIT(4)
+#define BIT_RX_SFF_UDN_8197F BIT(3)
+#define BIT_RX_SFF_OVF_8197F BIT(2)
+#define BIT_RXPKT_OVF_8197F BIT(0)
+
+/* 2 REG_RXDMA_DPR_8197F */
+
+#define BIT_SHIFT_RDE_DEBUG_8197F 0
+#define BIT_MASK_RDE_DEBUG_8197F 0xffffffffL
+#define BIT_RDE_DEBUG_8197F(x)                                                 \
+	(((x) & BIT_MASK_RDE_DEBUG_8197F) << BIT_SHIFT_RDE_DEBUG_8197F)
+#define BITS_RDE_DEBUG_8197F                                                   \
+	(BIT_MASK_RDE_DEBUG_8197F << BIT_SHIFT_RDE_DEBUG_8197F)
+#define BIT_CLEAR_RDE_DEBUG_8197F(x) ((x) & (~BITS_RDE_DEBUG_8197F))
+#define BIT_GET_RDE_DEBUG_8197F(x)                                             \
+	(((x) >> BIT_SHIFT_RDE_DEBUG_8197F) & BIT_MASK_RDE_DEBUG_8197F)
+#define BIT_SET_RDE_DEBUG_8197F(x, v)                                          \
+	(BIT_CLEAR_RDE_DEBUG_8197F(x) | BIT_RDE_DEBUG_8197F(v))
+
+/* 2 REG_RXDMA_MODE_8197F */
+
+/* 2 REG_NOT_VALID_8197F */
+
+/* 2 REG_NOT_VALID_8197F */
+
+/* 2 REG_NOT_VALID_8197F */
+#define BIT_EN_SPD_8197F BIT(6)
+
+#define BIT_SHIFT_BURST_SIZE_8197F 4
+#define BIT_MASK_BURST_SIZE_8197F 0x3
+#define BIT_BURST_SIZE_8197F(x)                                                \
+	(((x) & BIT_MASK_BURST_SIZE_8197F) << BIT_SHIFT_BURST_SIZE_8197F)
+#define BITS_BURST_SIZE_8197F                                                  \
+	(BIT_MASK_BURST_SIZE_8197F << BIT_SHIFT_BURST_SIZE_8197F)
+#define BIT_CLEAR_BURST_SIZE_8197F(x) ((x) & (~BITS_BURST_SIZE_8197F))
+#define BIT_GET_BURST_SIZE_8197F(x)                                            \
+	(((x) >> BIT_SHIFT_BURST_SIZE_8197F) & BIT_MASK_BURST_SIZE_8197F)
+#define BIT_SET_BURST_SIZE_8197F(x, v)                                         \
+	(BIT_CLEAR_BURST_SIZE_8197F(x) | BIT_BURST_SIZE_8197F(v))
+
+#define BIT_SHIFT_BURST_CNT_8197F 2
+#define BIT_MASK_BURST_CNT_8197F 0x3
+#define BIT_BURST_CNT_8197F(x)                                                 \
+	(((x) & BIT_MASK_BURST_CNT_8197F) << BIT_SHIFT_BURST_CNT_8197F)
+#define BITS_BURST_CNT_8197F                                                   \
+	(BIT_MASK_BURST_CNT_8197F << BIT_SHIFT_BURST_CNT_8197F)
+#define BIT_CLEAR_BURST_CNT_8197F(x) ((x) & (~BITS_BURST_CNT_8197F))
+#define BIT_GET_BURST_CNT_8197F(x)                                             \
+	(((x) >> BIT_SHIFT_BURST_CNT_8197F) & BIT_MASK_BURST_CNT_8197F)
+#define BIT_SET_BURST_CNT_8197F(x, v)                                          \
+	(BIT_CLEAR_BURST_CNT_8197F(x) | BIT_BURST_CNT_8197F(v))
+
+#define BIT_DMA_MODE_8197F BIT(1)
+
+/* 2 REG_C2H_PKT_8197F */
+
+#define BIT_SHIFT_R_C2H_STR_ADDR_16_TO_19_8197F 24
+#define BIT_MASK_R_C2H_STR_ADDR_16_TO_19_8197F 0xf
+#define BIT_R_C2H_STR_ADDR_16_TO_19_8197F(x)                                   \
+	(((x) & BIT_MASK_R_C2H_STR_ADDR_16_TO_19_8197F)                        \
+	 << BIT_SHIFT_R_C2H_STR_ADDR_16_TO_19_8197F)
+#define BITS_R_C2H_STR_ADDR_16_TO_19_8197F                                     \
+	(BIT_MASK_R_C2H_STR_ADDR_16_TO_19_8197F                                \
+	 << BIT_SHIFT_R_C2H_STR_ADDR_16_TO_19_8197F)
+#define BIT_CLEAR_R_C2H_STR_ADDR_16_TO_19_8197F(x)                             \
+	((x) & (~BITS_R_C2H_STR_ADDR_16_TO_19_8197F))
+#define BIT_GET_R_C2H_STR_ADDR_16_TO_19_8197F(x)                               \
+	(((x) >> BIT_SHIFT_R_C2H_STR_ADDR_16_TO_19_8197F) &                    \
+	 BIT_MASK_R_C2H_STR_ADDR_16_TO_19_8197F)
+#define BIT_SET_R_C2H_STR_ADDR_16_TO_19_8197F(x, v)                            \
+	(BIT_CLEAR_R_C2H_STR_ADDR_16_TO_19_8197F(x) |                          \
+	 BIT_R_C2H_STR_ADDR_16_TO_19_8197F(v))
+
+#define BIT_R_C2H_PKT_REQ_8197F BIT(16)
+
+#define BIT_SHIFT_R_C2H_STR_ADDR_8197F 0
+#define BIT_MASK_R_C2H_STR_ADDR_8197F 0xffff
+#define BIT_R_C2H_STR_ADDR_8197F(x)                                            \
+	(((x) & BIT_MASK_R_C2H_STR_ADDR_8197F)                                 \
+	 << BIT_SHIFT_R_C2H_STR_ADDR_8197F)
+#define BITS_R_C2H_STR_ADDR_8197F                                              \
+	(BIT_MASK_R_C2H_STR_ADDR_8197F << BIT_SHIFT_R_C2H_STR_ADDR_8197F)
+#define BIT_CLEAR_R_C2H_STR_ADDR_8197F(x) ((x) & (~BITS_R_C2H_STR_ADDR_8197F))
+#define BIT_GET_R_C2H_STR_ADDR_8197F(x)                                        \
+	(((x) >> BIT_SHIFT_R_C2H_STR_ADDR_8197F) &                             \
+	 BIT_MASK_R_C2H_STR_ADDR_8197F)
+#define BIT_SET_R_C2H_STR_ADDR_8197F(x, v)                                     \
+	(BIT_CLEAR_R_C2H_STR_ADDR_8197F(x) | BIT_R_C2H_STR_ADDR_8197F(v))
+
+/* 2 REG_FWFF_C2H_8197F */
+
+#define BIT_SHIFT_C2H_DMA_ADDR_8197F 0
+#define BIT_MASK_C2H_DMA_ADDR_8197F 0x3ffff
+#define BIT_C2H_DMA_ADDR_8197F(x)                                              \
+	(((x) & BIT_MASK_C2H_DMA_ADDR_8197F) << BIT_SHIFT_C2H_DMA_ADDR_8197F)
+#define BITS_C2H_DMA_ADDR_8197F                                                \
+	(BIT_MASK_C2H_DMA_ADDR_8197F << BIT_SHIFT_C2H_DMA_ADDR_8197F)
+#define BIT_CLEAR_C2H_DMA_ADDR_8197F(x) ((x) & (~BITS_C2H_DMA_ADDR_8197F))
+#define BIT_GET_C2H_DMA_ADDR_8197F(x)                                          \
+	(((x) >> BIT_SHIFT_C2H_DMA_ADDR_8197F) & BIT_MASK_C2H_DMA_ADDR_8197F)
+#define BIT_SET_C2H_DMA_ADDR_8197F(x, v)                                       \
+	(BIT_CLEAR_C2H_DMA_ADDR_8197F(x) | BIT_C2H_DMA_ADDR_8197F(v))
+
+/* 2 REG_FWFF_CTRL_8197F */
+#define BIT_FWFF_DMAPKT_REQ_8197F BIT(31)
+
+#define BIT_SHIFT_FWFF_DMA_PKT_NUM_8197F 16
+#define BIT_MASK_FWFF_DMA_PKT_NUM_8197F 0xff
+#define BIT_FWFF_DMA_PKT_NUM_8197F(x)                                          \
+	(((x) & BIT_MASK_FWFF_DMA_PKT_NUM_8197F)                               \
+	 << BIT_SHIFT_FWFF_DMA_PKT_NUM_8197F)
+#define BITS_FWFF_DMA_PKT_NUM_8197F                                            \
+	(BIT_MASK_FWFF_DMA_PKT_NUM_8197F << BIT_SHIFT_FWFF_DMA_PKT_NUM_8197F)
+#define BIT_CLEAR_FWFF_DMA_PKT_NUM_8197F(x)                                    \
+	((x) & (~BITS_FWFF_DMA_PKT_NUM_8197F))
+#define BIT_GET_FWFF_DMA_PKT_NUM_8197F(x)                                      \
+	(((x) >> BIT_SHIFT_FWFF_DMA_PKT_NUM_8197F) &                           \
+	 BIT_MASK_FWFF_DMA_PKT_NUM_8197F)
+#define BIT_SET_FWFF_DMA_PKT_NUM_8197F(x, v)                                   \
+	(BIT_CLEAR_FWFF_DMA_PKT_NUM_8197F(x) | BIT_FWFF_DMA_PKT_NUM_8197F(v))
+
+#define BIT_SHIFT_FWFF_STR_ADDR_8197F 0
+#define BIT_MASK_FWFF_STR_ADDR_8197F 0xffff
+#define BIT_FWFF_STR_ADDR_8197F(x)                                             \
+	(((x) & BIT_MASK_FWFF_STR_ADDR_8197F) << BIT_SHIFT_FWFF_STR_ADDR_8197F)
+#define BITS_FWFF_STR_ADDR_8197F                                               \
+	(BIT_MASK_FWFF_STR_ADDR_8197F << BIT_SHIFT_FWFF_STR_ADDR_8197F)
+#define BIT_CLEAR_FWFF_STR_ADDR_8197F(x) ((x) & (~BITS_FWFF_STR_ADDR_8197F))
+#define BIT_GET_FWFF_STR_ADDR_8197F(x)                                         \
+	(((x) >> BIT_SHIFT_FWFF_STR_ADDR_8197F) & BIT_MASK_FWFF_STR_ADDR_8197F)
+#define BIT_SET_FWFF_STR_ADDR_8197F(x, v)                                      \
+	(BIT_CLEAR_FWFF_STR_ADDR_8197F(x) | BIT_FWFF_STR_ADDR_8197F(v))
+
+/* 2 REG_FWFF_PKT_INFO_8197F */
+
+#define BIT_SHIFT_FWFF_PKT_QUEUED_8197F 16
+#define BIT_MASK_FWFF_PKT_QUEUED_8197F 0xff
+#define BIT_FWFF_PKT_QUEUED_8197F(x)                                           \
+	(((x) & BIT_MASK_FWFF_PKT_QUEUED_8197F)                                \
+	 << BIT_SHIFT_FWFF_PKT_QUEUED_8197F)
+#define BITS_FWFF_PKT_QUEUED_8197F                                             \
+	(BIT_MASK_FWFF_PKT_QUEUED_8197F << BIT_SHIFT_FWFF_PKT_QUEUED_8197F)
+#define BIT_CLEAR_FWFF_PKT_QUEUED_8197F(x) ((x) & (~BITS_FWFF_PKT_QUEUED_8197F))
+#define BIT_GET_FWFF_PKT_QUEUED_8197F(x)                                       \
+	(((x) >> BIT_SHIFT_FWFF_PKT_QUEUED_8197F) &                            \
+	 BIT_MASK_FWFF_PKT_QUEUED_8197F)
+#define BIT_SET_FWFF_PKT_QUEUED_8197F(x, v)                                    \
+	(BIT_CLEAR_FWFF_PKT_QUEUED_8197F(x) | BIT_FWFF_PKT_QUEUED_8197F(v))
+
+#define BIT_SHIFT_FWFF_PKT_STR_ADDR_8197F 0
+#define BIT_MASK_FWFF_PKT_STR_ADDR_8197F 0xffff
+#define BIT_FWFF_PKT_STR_ADDR_8197F(x)                                         \
+	(((x) & BIT_MASK_FWFF_PKT_STR_ADDR_8197F)                              \
+	 << BIT_SHIFT_FWFF_PKT_STR_ADDR_8197F)
+#define BITS_FWFF_PKT_STR_ADDR_8197F                                           \
+	(BIT_MASK_FWFF_PKT_STR_ADDR_8197F << BIT_SHIFT_FWFF_PKT_STR_ADDR_8197F)
+#define BIT_CLEAR_FWFF_PKT_STR_ADDR_8197F(x)                                   \
+	((x) & (~BITS_FWFF_PKT_STR_ADDR_8197F))
+#define BIT_GET_FWFF_PKT_STR_ADDR_8197F(x)                                     \
+	(((x) >> BIT_SHIFT_FWFF_PKT_STR_ADDR_8197F) &                          \
+	 BIT_MASK_FWFF_PKT_STR_ADDR_8197F)
+#define BIT_SET_FWFF_PKT_STR_ADDR_8197F(x, v)                                  \
+	(BIT_CLEAR_FWFF_PKT_STR_ADDR_8197F(x) | BIT_FWFF_PKT_STR_ADDR_8197F(v))
+
+/* 2 REG_FC2H_INFO_8197F */
+#define BIT_FC2H_PKT_REQ_8197F BIT(16)
+
+#define BIT_SHIFT_FC2H_STR_ADDR_8197F 0
+#define BIT_MASK_FC2H_STR_ADDR_8197F 0xffff
+#define BIT_FC2H_STR_ADDR_8197F(x)                                             \
+	(((x) & BIT_MASK_FC2H_STR_ADDR_8197F) << BIT_SHIFT_FC2H_STR_ADDR_8197F)
+#define BITS_FC2H_STR_ADDR_8197F                                               \
+	(BIT_MASK_FC2H_STR_ADDR_8197F << BIT_SHIFT_FC2H_STR_ADDR_8197F)
+#define BIT_CLEAR_FC2H_STR_ADDR_8197F(x) ((x) & (~BITS_FC2H_STR_ADDR_8197F))
+#define BIT_GET_FC2H_STR_ADDR_8197F(x)                                         \
+	(((x) >> BIT_SHIFT_FC2H_STR_ADDR_8197F) & BIT_MASK_FC2H_STR_ADDR_8197F)
+#define BIT_SET_FC2H_STR_ADDR_8197F(x, v)                                      \
+	(BIT_CLEAR_FC2H_STR_ADDR_8197F(x) | BIT_FC2H_STR_ADDR_8197F(v))
+
+/* 2 REG_NOT_VALID_8197F */
+
+/* 2 REG_DDMA_CH0SA_8197F */
+
+#define BIT_SHIFT_DDMACH0_SA_8197F 0
+#define BIT_MASK_DDMACH0_SA_8197F 0xffffffffL
+#define BIT_DDMACH0_SA_8197F(x)                                                \
+	(((x) & BIT_MASK_DDMACH0_SA_8197F) << BIT_SHIFT_DDMACH0_SA_8197F)
+#define BITS_DDMACH0_SA_8197F                                                  \
+	(BIT_MASK_DDMACH0_SA_8197F << BIT_SHIFT_DDMACH0_SA_8197F)
+#define BIT_CLEAR_DDMACH0_SA_8197F(x) ((x) & (~BITS_DDMACH0_SA_8197F))
+#define BIT_GET_DDMACH0_SA_8197F(x)                                            \
+	(((x) >> BIT_SHIFT_DDMACH0_SA_8197F) & BIT_MASK_DDMACH0_SA_8197F)
+#define BIT_SET_DDMACH0_SA_8197F(x, v)                                         \
+	(BIT_CLEAR_DDMACH0_SA_8197F(x) | BIT_DDMACH0_SA_8197F(v))
+
+/* 2 REG_DDMA_CH0DA_8197F */
+
+#define BIT_SHIFT_DDMACH0_DA_8197F 0
+#define BIT_MASK_DDMACH0_DA_8197F 0xffffffffL
+#define BIT_DDMACH0_DA_8197F(x)                                                \
+	(((x) & BIT_MASK_DDMACH0_DA_8197F) << BIT_SHIFT_DDMACH0_DA_8197F)
+#define BITS_DDMACH0_DA_8197F                                                  \
+	(BIT_MASK_DDMACH0_DA_8197F << BIT_SHIFT_DDMACH0_DA_8197F)
+#define BIT_CLEAR_DDMACH0_DA_8197F(x) ((x) & (~BITS_DDMACH0_DA_8197F))
+#define BIT_GET_DDMACH0_DA_8197F(x)                                            \
+	(((x) >> BIT_SHIFT_DDMACH0_DA_8197F) & BIT_MASK_DDMACH0_DA_8197F)
+#define BIT_SET_DDMACH0_DA_8197F(x, v)                                         \
+	(BIT_CLEAR_DDMACH0_DA_8197F(x) | BIT_DDMACH0_DA_8197F(v))
+
+/* 2 REG_DDMA_CH0CTRL_8197F */
+#define BIT_DDMACH0_OWN_8197F BIT(31)
+#define BIT_DDMACH0_CHKSUM_EN_8197F BIT(29)
+#define BIT_DDMACH0_DA_W_DISABLE_8197F BIT(28)
+#define BIT_DDMACH0_CHKSUM_STS_8197F BIT(27)
+#define BIT_DDMACH0_DDMA_MODE_8197F BIT(26)
+#define BIT_DDMACH0_RESET_CHKSUM_STS_8197F BIT(25)
+#define BIT_DDMACH0_CHKSUM_CONT_8197F BIT(24)
+
+#define BIT_SHIFT_DDMACH0_DLEN_8197F 0
+#define BIT_MASK_DDMACH0_DLEN_8197F 0x3ffff
+#define BIT_DDMACH0_DLEN_8197F(x)                                              \
+	(((x) & BIT_MASK_DDMACH0_DLEN_8197F) << BIT_SHIFT_DDMACH0_DLEN_8197F)
+#define BITS_DDMACH0_DLEN_8197F                                                \
+	(BIT_MASK_DDMACH0_DLEN_8197F << BIT_SHIFT_DDMACH0_DLEN_8197F)
+#define BIT_CLEAR_DDMACH0_DLEN_8197F(x) ((x) & (~BITS_DDMACH0_DLEN_8197F))
+#define BIT_GET_DDMACH0_DLEN_8197F(x)                                          \
+	(((x) >> BIT_SHIFT_DDMACH0_DLEN_8197F) & BIT_MASK_DDMACH0_DLEN_8197F)
+#define BIT_SET_DDMACH0_DLEN_8197F(x, v)                                       \
+	(BIT_CLEAR_DDMACH0_DLEN_8197F(x) | BIT_DDMACH0_DLEN_8197F(v))
+
+/* 2 REG_DDMA_CH1SA_8197F */
+
+#define BIT_SHIFT_DDMACH1_SA_8197F 0
+#define BIT_MASK_DDMACH1_SA_8197F 0xffffffffL
+#define BIT_DDMACH1_SA_8197F(x)                                                \
+	(((x) & BIT_MASK_DDMACH1_SA_8197F) << BIT_SHIFT_DDMACH1_SA_8197F)
+#define BITS_DDMACH1_SA_8197F                                                  \
+	(BIT_MASK_DDMACH1_SA_8197F << BIT_SHIFT_DDMACH1_SA_8197F)
+#define BIT_CLEAR_DDMACH1_SA_8197F(x) ((x) & (~BITS_DDMACH1_SA_8197F))
+#define BIT_GET_DDMACH1_SA_8197F(x)                                            \
+	(((x) >> BIT_SHIFT_DDMACH1_SA_8197F) & BIT_MASK_DDMACH1_SA_8197F)
+#define BIT_SET_DDMACH1_SA_8197F(x, v)                                         \
+	(BIT_CLEAR_DDMACH1_SA_8197F(x) | BIT_DDMACH1_SA_8197F(v))
+
+/* 2 REG_DDMA_CH1DA_8197F */
+
+#define BIT_SHIFT_DDMACH1_DA_8197F 0
+#define BIT_MASK_DDMACH1_DA_8197F 0xffffffffL
+#define BIT_DDMACH1_DA_8197F(x)                                                \
+	(((x) & BIT_MASK_DDMACH1_DA_8197F) << BIT_SHIFT_DDMACH1_DA_8197F)
+#define BITS_DDMACH1_DA_8197F                                                  \
+	(BIT_MASK_DDMACH1_DA_8197F << BIT_SHIFT_DDMACH1_DA_8197F)
+#define BIT_CLEAR_DDMACH1_DA_8197F(x) ((x) & (~BITS_DDMACH1_DA_8197F))
+#define BIT_GET_DDMACH1_DA_8197F(x)                                            \
+	(((x) >> BIT_SHIFT_DDMACH1_DA_8197F) & BIT_MASK_DDMACH1_DA_8197F)
+#define BIT_SET_DDMACH1_DA_8197F(x, v)                                         \
+	(BIT_CLEAR_DDMACH1_DA_8197F(x) | BIT_DDMACH1_DA_8197F(v))
+
+/* 2 REG_DDMA_CH1CTRL_8197F */
+#define BIT_DDMACH1_OWN_8197F BIT(31)
+#define BIT_DDMACH1_CHKSUM_EN_8197F BIT(29)
+#define BIT_DDMACH1_DA_W_DISABLE_8197F BIT(28)
+#define BIT_DDMACH1_CHKSUM_STS_8197F BIT(27)
+#define BIT_DDMACH1_DDMA_MODE_8197F BIT(26)
+#define BIT_DDMACH1_RESET_CHKSUM_STS_8197F BIT(25)
+#define BIT_DDMACH1_CHKSUM_CONT_8197F BIT(24)
+
+#define BIT_SHIFT_DDMACH1_DLEN_8197F 0
+#define BIT_MASK_DDMACH1_DLEN_8197F 0x3ffff
+#define BIT_DDMACH1_DLEN_8197F(x)                                              \
+	(((x) & BIT_MASK_DDMACH1_DLEN_8197F) << BIT_SHIFT_DDMACH1_DLEN_8197F)
+#define BITS_DDMACH1_DLEN_8197F                                                \
+	(BIT_MASK_DDMACH1_DLEN_8197F << BIT_SHIFT_DDMACH1_DLEN_8197F)
+#define BIT_CLEAR_DDMACH1_DLEN_8197F(x) ((x) & (~BITS_DDMACH1_DLEN_8197F))
+#define BIT_GET_DDMACH1_DLEN_8197F(x)                                          \
+	(((x) >> BIT_SHIFT_DDMACH1_DLEN_8197F) & BIT_MASK_DDMACH1_DLEN_8197F)
+#define BIT_SET_DDMACH1_DLEN_8197F(x, v)                                       \
+	(BIT_CLEAR_DDMACH1_DLEN_8197F(x) | BIT_DDMACH1_DLEN_8197F(v))
+
+/* 2 REG_DDMA_CH2SA_8197F */
+
+#define BIT_SHIFT_DDMACH2_SA_8197F 0
+#define BIT_MASK_DDMACH2_SA_8197F 0xffffffffL
+#define BIT_DDMACH2_SA_8197F(x)                                                \
+	(((x) & BIT_MASK_DDMACH2_SA_8197F) << BIT_SHIFT_DDMACH2_SA_8197F)
+#define BITS_DDMACH2_SA_8197F                                                  \
+	(BIT_MASK_DDMACH2_SA_8197F << BIT_SHIFT_DDMACH2_SA_8197F)
+#define BIT_CLEAR_DDMACH2_SA_8197F(x) ((x) & (~BITS_DDMACH2_SA_8197F))
+#define BIT_GET_DDMACH2_SA_8197F(x)                                            \
+	(((x) >> BIT_SHIFT_DDMACH2_SA_8197F) & BIT_MASK_DDMACH2_SA_8197F)
+#define BIT_SET_DDMACH2_SA_8197F(x, v)                                         \
+	(BIT_CLEAR_DDMACH2_SA_8197F(x) | BIT_DDMACH2_SA_8197F(v))
+
+/* 2 REG_DDMA_CH2DA_8197F */
+
+#define BIT_SHIFT_DDMACH2_DA_8197F 0
+#define BIT_MASK_DDMACH2_DA_8197F 0xffffffffL
+#define BIT_DDMACH2_DA_8197F(x)                                                \
+	(((x) & BIT_MASK_DDMACH2_DA_8197F) << BIT_SHIFT_DDMACH2_DA_8197F)
+#define BITS_DDMACH2_DA_8197F                                                  \
+	(BIT_MASK_DDMACH2_DA_8197F << BIT_SHIFT_DDMACH2_DA_8197F)
+#define BIT_CLEAR_DDMACH2_DA_8197F(x) ((x) & (~BITS_DDMACH2_DA_8197F))
+#define BIT_GET_DDMACH2_DA_8197F(x)                                            \
+	(((x) >> BIT_SHIFT_DDMACH2_DA_8197F) & BIT_MASK_DDMACH2_DA_8197F)
+#define BIT_SET_DDMACH2_DA_8197F(x, v)                                         \
+	(BIT_CLEAR_DDMACH2_DA_8197F(x) | BIT_DDMACH2_DA_8197F(v))
+
+/* 2 REG_DDMA_CH2CTRL_8197F */
+#define BIT_DDMACH2_OWN_8197F BIT(31)
+#define BIT_DDMACH2_CHKSUM_EN_8197F BIT(29)
+#define BIT_DDMACH2_DA_W_DISABLE_8197F BIT(28)
+#define BIT_DDMACH2_CHKSUM_STS_8197F BIT(27)
+#define BIT_DDMACH2_DDMA_MODE_8197F BIT(26)
+#define BIT_DDMACH2_RESET_CHKSUM_STS_8197F BIT(25)
+#define BIT_DDMACH2_CHKSUM_CONT_8197F BIT(24)
+
+#define BIT_SHIFT_DDMACH2_DLEN_8197F 0
+#define BIT_MASK_DDMACH2_DLEN_8197F 0x3ffff
+#define BIT_DDMACH2_DLEN_8197F(x)                                              \
+	(((x) & BIT_MASK_DDMACH2_DLEN_8197F) << BIT_SHIFT_DDMACH2_DLEN_8197F)
+#define BITS_DDMACH2_DLEN_8197F                                                \
+	(BIT_MASK_DDMACH2_DLEN_8197F << BIT_SHIFT_DDMACH2_DLEN_8197F)
+#define BIT_CLEAR_DDMACH2_DLEN_8197F(x) ((x) & (~BITS_DDMACH2_DLEN_8197F))
+#define BIT_GET_DDMACH2_DLEN_8197F(x)                                          \
+	(((x) >> BIT_SHIFT_DDMACH2_DLEN_8197F) & BIT_MASK_DDMACH2_DLEN_8197F)
+#define BIT_SET_DDMACH2_DLEN_8197F(x, v)                                       \
+	(BIT_CLEAR_DDMACH2_DLEN_8197F(x) | BIT_DDMACH2_DLEN_8197F(v))
+
+/* 2 REG_DDMA_CH3SA_8197F */
+
+#define BIT_SHIFT_DDMACH3_SA_8197F 0
+#define BIT_MASK_DDMACH3_SA_8197F 0xffffffffL
+#define BIT_DDMACH3_SA_8197F(x)                                                \
+	(((x) & BIT_MASK_DDMACH3_SA_8197F) << BIT_SHIFT_DDMACH3_SA_8197F)
+#define BITS_DDMACH3_SA_8197F                                                  \
+	(BIT_MASK_DDMACH3_SA_8197F << BIT_SHIFT_DDMACH3_SA_8197F)
+#define BIT_CLEAR_DDMACH3_SA_8197F(x) ((x) & (~BITS_DDMACH3_SA_8197F))
+#define BIT_GET_DDMACH3_SA_8197F(x)                                            \
+	(((x) >> BIT_SHIFT_DDMACH3_SA_8197F) & BIT_MASK_DDMACH3_SA_8197F)
+#define BIT_SET_DDMACH3_SA_8197F(x, v)                                         \
+	(BIT_CLEAR_DDMACH3_SA_8197F(x) | BIT_DDMACH3_SA_8197F(v))
+
+/* 2 REG_DDMA_CH3DA_8197F */
+
+#define BIT_SHIFT_DDMACH3_DA_8197F 0
+#define BIT_MASK_DDMACH3_DA_8197F 0xffffffffL
+#define BIT_DDMACH3_DA_8197F(x)                                                \
+	(((x) & BIT_MASK_DDMACH3_DA_8197F) << BIT_SHIFT_DDMACH3_DA_8197F)
+#define BITS_DDMACH3_DA_8197F                                                  \
+	(BIT_MASK_DDMACH3_DA_8197F << BIT_SHIFT_DDMACH3_DA_8197F)
+#define BIT_CLEAR_DDMACH3_DA_8197F(x) ((x) & (~BITS_DDMACH3_DA_8197F))
+#define BIT_GET_DDMACH3_DA_8197F(x)                                            \
+	(((x) >> BIT_SHIFT_DDMACH3_DA_8197F) & BIT_MASK_DDMACH3_DA_8197F)
+#define BIT_SET_DDMACH3_DA_8197F(x, v)                                         \
+	(BIT_CLEAR_DDMACH3_DA_8197F(x) | BIT_DDMACH3_DA_8197F(v))
+
+/* 2 REG_DDMA_CH3CTRL_8197F */
+#define BIT_DDMACH3_OWN_8197F BIT(31)
+#define BIT_DDMACH3_CHKSUM_EN_8197F BIT(29)
+#define BIT_DDMACH3_DA_W_DISABLE_8197F BIT(28)
+#define BIT_DDMACH3_CHKSUM_STS_8197F BIT(27)
+#define BIT_DDMACH3_DDMA_MODE_8197F BIT(26)
+#define BIT_DDMACH3_RESET_CHKSUM_STS_8197F BIT(25)
+#define BIT_DDMACH3_CHKSUM_CONT_8197F BIT(24)
+
+#define BIT_SHIFT_DDMACH3_DLEN_8197F 0
+#define BIT_MASK_DDMACH3_DLEN_8197F 0x3ffff
+#define BIT_DDMACH3_DLEN_8197F(x)                                              \
+	(((x) & BIT_MASK_DDMACH3_DLEN_8197F) << BIT_SHIFT_DDMACH3_DLEN_8197F)
+#define BITS_DDMACH3_DLEN_8197F                                                \
+	(BIT_MASK_DDMACH3_DLEN_8197F << BIT_SHIFT_DDMACH3_DLEN_8197F)
+#define BIT_CLEAR_DDMACH3_DLEN_8197F(x) ((x) & (~BITS_DDMACH3_DLEN_8197F))
+#define BIT_GET_DDMACH3_DLEN_8197F(x)                                          \
+	(((x) >> BIT_SHIFT_DDMACH3_DLEN_8197F) & BIT_MASK_DDMACH3_DLEN_8197F)
+#define BIT_SET_DDMACH3_DLEN_8197F(x, v)                                       \
+	(BIT_CLEAR_DDMACH3_DLEN_8197F(x) | BIT_DDMACH3_DLEN_8197F(v))
+
+/* 2 REG_DDMA_CH4SA_8197F */
+
+#define BIT_SHIFT_DDMACH4_SA_8197F 0
+#define BIT_MASK_DDMACH4_SA_8197F 0xffffffffL
+#define BIT_DDMACH4_SA_8197F(x)                                                \
+	(((x) & BIT_MASK_DDMACH4_SA_8197F) << BIT_SHIFT_DDMACH4_SA_8197F)
+#define BITS_DDMACH4_SA_8197F                                                  \
+	(BIT_MASK_DDMACH4_SA_8197F << BIT_SHIFT_DDMACH4_SA_8197F)
+#define BIT_CLEAR_DDMACH4_SA_8197F(x) ((x) & (~BITS_DDMACH4_SA_8197F))
+#define BIT_GET_DDMACH4_SA_8197F(x)                                            \
+	(((x) >> BIT_SHIFT_DDMACH4_SA_8197F) & BIT_MASK_DDMACH4_SA_8197F)
+#define BIT_SET_DDMACH4_SA_8197F(x, v)                                         \
+	(BIT_CLEAR_DDMACH4_SA_8197F(x) | BIT_DDMACH4_SA_8197F(v))
+
+/* 2 REG_DDMA_CH4DA_8197F */
+
+#define BIT_SHIFT_DDMACH4_DA_8197F 0
+#define BIT_MASK_DDMACH4_DA_8197F 0xffffffffL
+#define BIT_DDMACH4_DA_8197F(x)                                                \
+	(((x) & BIT_MASK_DDMACH4_DA_8197F) << BIT_SHIFT_DDMACH4_DA_8197F)
+#define BITS_DDMACH4_DA_8197F                                                  \
+	(BIT_MASK_DDMACH4_DA_8197F << BIT_SHIFT_DDMACH4_DA_8197F)
+#define BIT_CLEAR_DDMACH4_DA_8197F(x) ((x) & (~BITS_DDMACH4_DA_8197F))
+#define BIT_GET_DDMACH4_DA_8197F(x)                                            \
+	(((x) >> BIT_SHIFT_DDMACH4_DA_8197F) & BIT_MASK_DDMACH4_DA_8197F)
+#define BIT_SET_DDMACH4_DA_8197F(x, v)                                         \
+	(BIT_CLEAR_DDMACH4_DA_8197F(x) | BIT_DDMACH4_DA_8197F(v))
+
+/* 2 REG_DDMA_CH4CTRL_8197F */
+#define BIT_DDMACH4_OWN_8197F BIT(31)
+#define BIT_DDMACH4_CHKSUM_EN_8197F BIT(29)
+#define BIT_DDMACH4_DA_W_DISABLE_8197F BIT(28)
+#define BIT_DDMACH4_CHKSUM_STS_8197F BIT(27)
+#define BIT_DDMACH4_DDMA_MODE_8197F BIT(26)
+#define BIT_DDMACH4_RESET_CHKSUM_STS_8197F BIT(25)
+#define BIT_DDMACH4_CHKSUM_CONT_8197F BIT(24)
+
+#define BIT_SHIFT_DDMACH4_DLEN_8197F 0
+#define BIT_MASK_DDMACH4_DLEN_8197F 0x3ffff
+#define BIT_DDMACH4_DLEN_8197F(x)                                              \
+	(((x) & BIT_MASK_DDMACH4_DLEN_8197F) << BIT_SHIFT_DDMACH4_DLEN_8197F)
+#define BITS_DDMACH4_DLEN_8197F                                                \
+	(BIT_MASK_DDMACH4_DLEN_8197F << BIT_SHIFT_DDMACH4_DLEN_8197F)
+#define BIT_CLEAR_DDMACH4_DLEN_8197F(x) ((x) & (~BITS_DDMACH4_DLEN_8197F))
+#define BIT_GET_DDMACH4_DLEN_8197F(x)                                          \
+	(((x) >> BIT_SHIFT_DDMACH4_DLEN_8197F) & BIT_MASK_DDMACH4_DLEN_8197F)
+#define BIT_SET_DDMACH4_DLEN_8197F(x, v)                                       \
+	(BIT_CLEAR_DDMACH4_DLEN_8197F(x) | BIT_DDMACH4_DLEN_8197F(v))
+
+/* 2 REG_DDMA_CH5SA_8197F */
+
+#define BIT_SHIFT_DDMACH5_SA_8197F 0
+#define BIT_MASK_DDMACH5_SA_8197F 0xffffffffL
+#define BIT_DDMACH5_SA_8197F(x)                                                \
+	(((x) & BIT_MASK_DDMACH5_SA_8197F) << BIT_SHIFT_DDMACH5_SA_8197F)
+#define BITS_DDMACH5_SA_8197F                                                  \
+	(BIT_MASK_DDMACH5_SA_8197F << BIT_SHIFT_DDMACH5_SA_8197F)
+#define BIT_CLEAR_DDMACH5_SA_8197F(x) ((x) & (~BITS_DDMACH5_SA_8197F))
+#define BIT_GET_DDMACH5_SA_8197F(x)                                            \
+	(((x) >> BIT_SHIFT_DDMACH5_SA_8197F) & BIT_MASK_DDMACH5_SA_8197F)
+#define BIT_SET_DDMACH5_SA_8197F(x, v)                                         \
+	(BIT_CLEAR_DDMACH5_SA_8197F(x) | BIT_DDMACH5_SA_8197F(v))
+
+/* 2 REG_DDMA_CH5DA_8197F */
+
+#define BIT_SHIFT_DDMACH5_DA_8197F 0
+#define BIT_MASK_DDMACH5_DA_8197F 0xffffffffL
+#define BIT_DDMACH5_DA_8197F(x)                                                \
+	(((x) & BIT_MASK_DDMACH5_DA_8197F) << BIT_SHIFT_DDMACH5_DA_8197F)
+#define BITS_DDMACH5_DA_8197F                                                  \
+	(BIT_MASK_DDMACH5_DA_8197F << BIT_SHIFT_DDMACH5_DA_8197F)
+#define BIT_CLEAR_DDMACH5_DA_8197F(x) ((x) & (~BITS_DDMACH5_DA_8197F))
+#define BIT_GET_DDMACH5_DA_8197F(x)                                            \
+	(((x) >> BIT_SHIFT_DDMACH5_DA_8197F) & BIT_MASK_DDMACH5_DA_8197F)
+#define BIT_SET_DDMACH5_DA_8197F(x, v)                                         \
+	(BIT_CLEAR_DDMACH5_DA_8197F(x) | BIT_DDMACH5_DA_8197F(v))
+
+/* 2 REG_REG_DDMA_CH5CTRL_8197F */
+#define BIT_DDMACH5_OWN_8197F BIT(31)
+#define BIT_DDMACH5_CHKSUM_EN_8197F BIT(29)
+#define BIT_DDMACH5_DA_W_DISABLE_8197F BIT(28)
+#define BIT_DDMACH5_CHKSUM_STS_8197F BIT(27)
+#define BIT_DDMACH5_DDMA_MODE_8197F BIT(26)
+#define BIT_DDMACH5_RESET_CHKSUM_STS_8197F BIT(25)
+#define BIT_DDMACH5_CHKSUM_CONT_8197F BIT(24)
+
+#define BIT_SHIFT_DDMACH5_DLEN_8197F 0
+#define BIT_MASK_DDMACH5_DLEN_8197F 0x3ffff
+#define BIT_DDMACH5_DLEN_8197F(x)                                              \
+	(((x) & BIT_MASK_DDMACH5_DLEN_8197F) << BIT_SHIFT_DDMACH5_DLEN_8197F)
+#define BITS_DDMACH5_DLEN_8197F                                                \
+	(BIT_MASK_DDMACH5_DLEN_8197F << BIT_SHIFT_DDMACH5_DLEN_8197F)
+#define BIT_CLEAR_DDMACH5_DLEN_8197F(x) ((x) & (~BITS_DDMACH5_DLEN_8197F))
+#define BIT_GET_DDMACH5_DLEN_8197F(x)                                          \
+	(((x) >> BIT_SHIFT_DDMACH5_DLEN_8197F) & BIT_MASK_DDMACH5_DLEN_8197F)
+#define BIT_SET_DDMACH5_DLEN_8197F(x, v)                                       \
+	(BIT_CLEAR_DDMACH5_DLEN_8197F(x) | BIT_DDMACH5_DLEN_8197F(v))
+
+/* 2 REG_DDMA_INT_MSK_8197F */
+#define BIT_DDMACH5_MSK_8197F BIT(5)
+#define BIT_DDMACH4_MSK_8197F BIT(4)
+#define BIT_DDMACH3_MSK_8197F BIT(3)
+#define BIT_DDMACH2_MSK_8197F BIT(2)
+#define BIT_DDMACH1_MSK_8197F BIT(1)
+#define BIT_DDMACH0_MSK_8197F BIT(0)
+
+/* 2 REG_DDMA_CHSTATUS_8197F */
+#define BIT_DDMACH5_BUSY_8197F BIT(5)
+#define BIT_DDMACH4_BUSY_8197F BIT(4)
+#define BIT_DDMACH3_BUSY_8197F BIT(3)
+#define BIT_DDMACH2_BUSY_8197F BIT(2)
+#define BIT_DDMACH1_BUSY_8197F BIT(1)
+#define BIT_DDMACH0_BUSY_8197F BIT(0)
+
+/* 2 REG_DDMA_CHKSUM_8197F */
+
+#define BIT_SHIFT_IDDMA0_CHKSUM_8197F 0
+#define BIT_MASK_IDDMA0_CHKSUM_8197F 0xffff
+#define BIT_IDDMA0_CHKSUM_8197F(x)                                             \
+	(((x) & BIT_MASK_IDDMA0_CHKSUM_8197F) << BIT_SHIFT_IDDMA0_CHKSUM_8197F)
+#define BITS_IDDMA0_CHKSUM_8197F                                               \
+	(BIT_MASK_IDDMA0_CHKSUM_8197F << BIT_SHIFT_IDDMA0_CHKSUM_8197F)
+#define BIT_CLEAR_IDDMA0_CHKSUM_8197F(x) ((x) & (~BITS_IDDMA0_CHKSUM_8197F))
+#define BIT_GET_IDDMA0_CHKSUM_8197F(x)                                         \
+	(((x) >> BIT_SHIFT_IDDMA0_CHKSUM_8197F) & BIT_MASK_IDDMA0_CHKSUM_8197F)
+#define BIT_SET_IDDMA0_CHKSUM_8197F(x, v)                                      \
+	(BIT_CLEAR_IDDMA0_CHKSUM_8197F(x) | BIT_IDDMA0_CHKSUM_8197F(v))
+
+/* 2 REG_DDMA_MONITOR_8197F */
+#define BIT_IDDMA0_PERMU_UNDERFLOW_8197F BIT(14)
+#define BIT_IDDMA0_FIFO_UNDERFLOW_8197F BIT(13)
+#define BIT_IDDMA0_FIFO_OVERFLOW_8197F BIT(12)
+#define BIT_CH5_ERR_8197F BIT(5)
+#define BIT_CH4_ERR_8197F BIT(4)
+#define BIT_CH3_ERR_8197F BIT(3)
+#define BIT_CH2_ERR_8197F BIT(2)
+#define BIT_CH1_ERR_8197F BIT(1)
+#define BIT_CH0_ERR_8197F BIT(0)
+
+/* 2 REG_NOT_VALID_8197F */
+
+/* 2 REG_HCI_CTRL_8197F */
+#define BIT_HCIIO_PERSTB_SEL_8197F BIT(31)
+
+#define BIT_SHIFT_HCI_MAX_RXDMA_8197F 28
+#define BIT_MASK_HCI_MAX_RXDMA_8197F 0x7
+#define BIT_HCI_MAX_RXDMA_8197F(x)                                             \
+	(((x) & BIT_MASK_HCI_MAX_RXDMA_8197F) << BIT_SHIFT_HCI_MAX_RXDMA_8197F)
+#define BITS_HCI_MAX_RXDMA_8197F                                               \
+	(BIT_MASK_HCI_MAX_RXDMA_8197F << BIT_SHIFT_HCI_MAX_RXDMA_8197F)
+#define BIT_CLEAR_HCI_MAX_RXDMA_8197F(x) ((x) & (~BITS_HCI_MAX_RXDMA_8197F))
+#define BIT_GET_HCI_MAX_RXDMA_8197F(x)                                         \
+	(((x) >> BIT_SHIFT_HCI_MAX_RXDMA_8197F) & BIT_MASK_HCI_MAX_RXDMA_8197F)
+#define BIT_SET_HCI_MAX_RXDMA_8197F(x, v)                                      \
+	(BIT_CLEAR_HCI_MAX_RXDMA_8197F(x) | BIT_HCI_MAX_RXDMA_8197F(v))
+
+#define BIT_MULRW_8197F BIT(27)
+
+#define BIT_SHIFT_HCI_MAX_TXDMA_8197F 24
+#define BIT_MASK_HCI_MAX_TXDMA_8197F 0x7
+#define BIT_HCI_MAX_TXDMA_8197F(x)                                             \
+	(((x) & BIT_MASK_HCI_MAX_TXDMA_8197F) << BIT_SHIFT_HCI_MAX_TXDMA_8197F)
+#define BITS_HCI_MAX_TXDMA_8197F                                               \
+	(BIT_MASK_HCI_MAX_TXDMA_8197F << BIT_SHIFT_HCI_MAX_TXDMA_8197F)
+#define BIT_CLEAR_HCI_MAX_TXDMA_8197F(x) ((x) & (~BITS_HCI_MAX_TXDMA_8197F))
+#define BIT_GET_HCI_MAX_TXDMA_8197F(x)                                         \
+	(((x) >> BIT_SHIFT_HCI_MAX_TXDMA_8197F) & BIT_MASK_HCI_MAX_TXDMA_8197F)
+#define BIT_SET_HCI_MAX_TXDMA_8197F(x, v)                                      \
+	(BIT_CLEAR_HCI_MAX_TXDMA_8197F(x) | BIT_HCI_MAX_TXDMA_8197F(v))
+
+#define BIT_EN_CPL_TIMEOUT_PS_8197F BIT(22)
+#define BIT_REG_TXDMA_FAIL_PS_8197F BIT(21)
+#define BIT_HCI_RST_TRXDMA_INTF_8197F BIT(20)
+#define BIT_EN_HWENTR_L1_8197F BIT(19)
+#define BIT_EN_ADV_CLKGATE_8197F BIT(18)
+#define BIT_HCI_EN_SWENT_L23_8197F BIT(17)
+#define BIT_HCI_EN_HWEXT_L1_8197F BIT(16)
+#define BIT_RX_CLOSE_EN_8197F BIT(15)
+#define BIT_STOP_BCNQ_8197F BIT(14)
+#define BIT_STOP_MGQ_8197F BIT(13)
+#define BIT_STOP_VOQ_8197F BIT(12)
+#define BIT_STOP_VIQ_8197F BIT(11)
+#define BIT_STOP_BEQ_8197F BIT(10)
+#define BIT_STOP_BKQ_8197F BIT(9)
+#define BIT_STOP_RXQ_8197F BIT(8)
+#define BIT_STOP_HI7Q_8197F BIT(7)
+#define BIT_STOP_HI6Q_8197F BIT(6)
+#define BIT_STOP_HI5Q_8197F BIT(5)
+#define BIT_STOP_HI4Q_8197F BIT(4)
+#define BIT_STOP_HI3Q_8197F BIT(3)
+#define BIT_STOP_HI2Q_8197F BIT(2)
+#define BIT_STOP_HI1Q_8197F BIT(1)
+#define BIT_STOP_HI0Q_8197F BIT(0)
+
+/* 2 REG_INT_MIG_8197F */
+
+#define BIT_SHIFT_TXTTIMER_MATCH_NUM_8197F 28
+#define BIT_MASK_TXTTIMER_MATCH_NUM_8197F 0xf
+#define BIT_TXTTIMER_MATCH_NUM_8197F(x)                                        \
+	(((x) & BIT_MASK_TXTTIMER_MATCH_NUM_8197F)                             \
+	 << BIT_SHIFT_TXTTIMER_MATCH_NUM_8197F)
+#define BITS_TXTTIMER_MATCH_NUM_8197F                                          \
+	(BIT_MASK_TXTTIMER_MATCH_NUM_8197F                                     \
+	 << BIT_SHIFT_TXTTIMER_MATCH_NUM_8197F)
+#define BIT_CLEAR_TXTTIMER_MATCH_NUM_8197F(x)                                  \
+	((x) & (~BITS_TXTTIMER_MATCH_NUM_8197F))
+#define BIT_GET_TXTTIMER_MATCH_NUM_8197F(x)                                    \
+	(((x) >> BIT_SHIFT_TXTTIMER_MATCH_NUM_8197F) &                         \
+	 BIT_MASK_TXTTIMER_MATCH_NUM_8197F)
+#define BIT_SET_TXTTIMER_MATCH_NUM_8197F(x, v)                                 \
+	(BIT_CLEAR_TXTTIMER_MATCH_NUM_8197F(x) |                               \
+	 BIT_TXTTIMER_MATCH_NUM_8197F(v))
+
+#define BIT_SHIFT_TXPKT_NUM_MATCH_8197F 24
+#define BIT_MASK_TXPKT_NUM_MATCH_8197F 0xf
+#define BIT_TXPKT_NUM_MATCH_8197F(x)                                           \
+	(((x) & BIT_MASK_TXPKT_NUM_MATCH_8197F)                                \
+	 << BIT_SHIFT_TXPKT_NUM_MATCH_8197F)
+#define BITS_TXPKT_NUM_MATCH_8197F                                             \
+	(BIT_MASK_TXPKT_NUM_MATCH_8197F << BIT_SHIFT_TXPKT_NUM_MATCH_8197F)
+#define BIT_CLEAR_TXPKT_NUM_MATCH_8197F(x) ((x) & (~BITS_TXPKT_NUM_MATCH_8197F))
+#define BIT_GET_TXPKT_NUM_MATCH_8197F(x)                                       \
+	(((x) >> BIT_SHIFT_TXPKT_NUM_MATCH_8197F) &                            \
+	 BIT_MASK_TXPKT_NUM_MATCH_8197F)
+#define BIT_SET_TXPKT_NUM_MATCH_8197F(x, v)                                    \
+	(BIT_CLEAR_TXPKT_NUM_MATCH_8197F(x) | BIT_TXPKT_NUM_MATCH_8197F(v))
+
+#define BIT_SHIFT_RXTTIMER_MATCH_NUM_8197F 20
+#define BIT_MASK_RXTTIMER_MATCH_NUM_8197F 0xf
+#define BIT_RXTTIMER_MATCH_NUM_8197F(x)                                        \
+	(((x) & BIT_MASK_RXTTIMER_MATCH_NUM_8197F)                             \
+	 << BIT_SHIFT_RXTTIMER_MATCH_NUM_8197F)
+#define BITS_RXTTIMER_MATCH_NUM_8197F                                          \
+	(BIT_MASK_RXTTIMER_MATCH_NUM_8197F                                     \
+	 << BIT_SHIFT_RXTTIMER_MATCH_NUM_8197F)
+#define BIT_CLEAR_RXTTIMER_MATCH_NUM_8197F(x)                                  \
+	((x) & (~BITS_RXTTIMER_MATCH_NUM_8197F))
+#define BIT_GET_RXTTIMER_MATCH_NUM_8197F(x)                                    \
+	(((x) >> BIT_SHIFT_RXTTIMER_MATCH_NUM_8197F) &                         \
+	 BIT_MASK_RXTTIMER_MATCH_NUM_8197F)
+#define BIT_SET_RXTTIMER_MATCH_NUM_8197F(x, v)                                 \
+	(BIT_CLEAR_RXTTIMER_MATCH_NUM_8197F(x) |                               \
+	 BIT_RXTTIMER_MATCH_NUM_8197F(v))
+
+#define BIT_SHIFT_RXPKT_NUM_MATCH_8197F 16
+#define BIT_MASK_RXPKT_NUM_MATCH_8197F 0xf
+#define BIT_RXPKT_NUM_MATCH_8197F(x)                                           \
+	(((x) & BIT_MASK_RXPKT_NUM_MATCH_8197F)                                \
+	 << BIT_SHIFT_RXPKT_NUM_MATCH_8197F)
+#define BITS_RXPKT_NUM_MATCH_8197F                                             \
+	(BIT_MASK_RXPKT_NUM_MATCH_8197F << BIT_SHIFT_RXPKT_NUM_MATCH_8197F)
+#define BIT_CLEAR_RXPKT_NUM_MATCH_8197F(x) ((x) & (~BITS_RXPKT_NUM_MATCH_8197F))
+#define BIT_GET_RXPKT_NUM_MATCH_8197F(x)                                       \
+	(((x) >> BIT_SHIFT_RXPKT_NUM_MATCH_8197F) &                            \
+	 BIT_MASK_RXPKT_NUM_MATCH_8197F)
+#define BIT_SET_RXPKT_NUM_MATCH_8197F(x, v)                                    \
+	(BIT_CLEAR_RXPKT_NUM_MATCH_8197F(x) | BIT_RXPKT_NUM_MATCH_8197F(v))
+
+#define BIT_SHIFT_MIGRATE_TIMER_8197F 0
+#define BIT_MASK_MIGRATE_TIMER_8197F 0xffff
+#define BIT_MIGRATE_TIMER_8197F(x)                                             \
+	(((x) & BIT_MASK_MIGRATE_TIMER_8197F) << BIT_SHIFT_MIGRATE_TIMER_8197F)
+#define BITS_MIGRATE_TIMER_8197F                                               \
+	(BIT_MASK_MIGRATE_TIMER_8197F << BIT_SHIFT_MIGRATE_TIMER_8197F)
+#define BIT_CLEAR_MIGRATE_TIMER_8197F(x) ((x) & (~BITS_MIGRATE_TIMER_8197F))
+#define BIT_GET_MIGRATE_TIMER_8197F(x)                                         \
+	(((x) >> BIT_SHIFT_MIGRATE_TIMER_8197F) & BIT_MASK_MIGRATE_TIMER_8197F)
+#define BIT_SET_MIGRATE_TIMER_8197F(x, v)                                      \
+	(BIT_CLEAR_MIGRATE_TIMER_8197F(x) | BIT_MIGRATE_TIMER_8197F(v))
+
+/* 2 REG_BCNQ_TXBD_DESA_8197F */
+
+#define BIT_SHIFT_BCNQ_TXBD_DESA_8197F 0
+#define BIT_MASK_BCNQ_TXBD_DESA_8197F 0xffffffffffffffffL
+#define BIT_BCNQ_TXBD_DESA_8197F(x)                                            \
+	(((x) & BIT_MASK_BCNQ_TXBD_DESA_8197F)                                 \
+	 << BIT_SHIFT_BCNQ_TXBD_DESA_8197F)
+#define BITS_BCNQ_TXBD_DESA_8197F                                              \
+	(BIT_MASK_BCNQ_TXBD_DESA_8197F << BIT_SHIFT_BCNQ_TXBD_DESA_8197F)
+#define BIT_CLEAR_BCNQ_TXBD_DESA_8197F(x) ((x) & (~BITS_BCNQ_TXBD_DESA_8197F))
+#define BIT_GET_BCNQ_TXBD_DESA_8197F(x)                                        \
+	(((x) >> BIT_SHIFT_BCNQ_TXBD_DESA_8197F) &                             \
+	 BIT_MASK_BCNQ_TXBD_DESA_8197F)
+#define BIT_SET_BCNQ_TXBD_DESA_8197F(x, v)                                     \
+	(BIT_CLEAR_BCNQ_TXBD_DESA_8197F(x) | BIT_BCNQ_TXBD_DESA_8197F(v))
+
+/* 2 REG_MGQ_TXBD_DESA_8197F */
+
+#define BIT_SHIFT_MGQ_TXBD_DESA_8197F 0
+#define BIT_MASK_MGQ_TXBD_DESA_8197F 0xffffffffffffffffL
+#define BIT_MGQ_TXBD_DESA_8197F(x)                                             \
+	(((x) & BIT_MASK_MGQ_TXBD_DESA_8197F) << BIT_SHIFT_MGQ_TXBD_DESA_8197F)
+#define BITS_MGQ_TXBD_DESA_8197F                                               \
+	(BIT_MASK_MGQ_TXBD_DESA_8197F << BIT_SHIFT_MGQ_TXBD_DESA_8197F)
+#define BIT_CLEAR_MGQ_TXBD_DESA_8197F(x) ((x) & (~BITS_MGQ_TXBD_DESA_8197F))
+#define BIT_GET_MGQ_TXBD_DESA_8197F(x)                                         \
+	(((x) >> BIT_SHIFT_MGQ_TXBD_DESA_8197F) & BIT_MASK_MGQ_TXBD_DESA_8197F)
+#define BIT_SET_MGQ_TXBD_DESA_8197F(x, v)                                      \
+	(BIT_CLEAR_MGQ_TXBD_DESA_8197F(x) | BIT_MGQ_TXBD_DESA_8197F(v))
+
+/* 2 REG_VOQ_TXBD_DESA_8197F */
+
+#define BIT_SHIFT_VOQ_TXBD_DESA_8197F 0
+#define BIT_MASK_VOQ_TXBD_DESA_8197F 0xffffffffffffffffL
+#define BIT_VOQ_TXBD_DESA_8197F(x)                                             \
+	(((x) & BIT_MASK_VOQ_TXBD_DESA_8197F) << BIT_SHIFT_VOQ_TXBD_DESA_8197F)
+#define BITS_VOQ_TXBD_DESA_8197F                                               \
+	(BIT_MASK_VOQ_TXBD_DESA_8197F << BIT_SHIFT_VOQ_TXBD_DESA_8197F)
+#define BIT_CLEAR_VOQ_TXBD_DESA_8197F(x) ((x) & (~BITS_VOQ_TXBD_DESA_8197F))
+#define BIT_GET_VOQ_TXBD_DESA_8197F(x)                                         \
+	(((x) >> BIT_SHIFT_VOQ_TXBD_DESA_8197F) & BIT_MASK_VOQ_TXBD_DESA_8197F)
+#define BIT_SET_VOQ_TXBD_DESA_8197F(x, v)                                      \
+	(BIT_CLEAR_VOQ_TXBD_DESA_8197F(x) | BIT_VOQ_TXBD_DESA_8197F(v))
+
+/* 2 REG_VIQ_TXBD_DESA_8197F */
+
+#define BIT_SHIFT_VIQ_TXBD_DESA_8197F 0
+#define BIT_MASK_VIQ_TXBD_DESA_8197F 0xffffffffffffffffL
+#define BIT_VIQ_TXBD_DESA_8197F(x)                                             \
+	(((x) & BIT_MASK_VIQ_TXBD_DESA_8197F) << BIT_SHIFT_VIQ_TXBD_DESA_8197F)
+#define BITS_VIQ_TXBD_DESA_8197F                                               \
+	(BIT_MASK_VIQ_TXBD_DESA_8197F << BIT_SHIFT_VIQ_TXBD_DESA_8197F)
+#define BIT_CLEAR_VIQ_TXBD_DESA_8197F(x) ((x) & (~BITS_VIQ_TXBD_DESA_8197F))
+#define BIT_GET_VIQ_TXBD_DESA_8197F(x)                                         \
+	(((x) >> BIT_SHIFT_VIQ_TXBD_DESA_8197F) & BIT_MASK_VIQ_TXBD_DESA_8197F)
+#define BIT_SET_VIQ_TXBD_DESA_8197F(x, v)                                      \
+	(BIT_CLEAR_VIQ_TXBD_DESA_8197F(x) | BIT_VIQ_TXBD_DESA_8197F(v))
+
+/* 2 REG_BEQ_TXBD_DESA_8197F */
+
+#define BIT_SHIFT_BEQ_TXBD_DESA_8197F 0
+#define BIT_MASK_BEQ_TXBD_DESA_8197F 0xffffffffffffffffL
+#define BIT_BEQ_TXBD_DESA_8197F(x)                                             \
+	(((x) & BIT_MASK_BEQ_TXBD_DESA_8197F) << BIT_SHIFT_BEQ_TXBD_DESA_8197F)
+#define BITS_BEQ_TXBD_DESA_8197F                                               \
+	(BIT_MASK_BEQ_TXBD_DESA_8197F << BIT_SHIFT_BEQ_TXBD_DESA_8197F)
+#define BIT_CLEAR_BEQ_TXBD_DESA_8197F(x) ((x) & (~BITS_BEQ_TXBD_DESA_8197F))
+#define BIT_GET_BEQ_TXBD_DESA_8197F(x)                                         \
+	(((x) >> BIT_SHIFT_BEQ_TXBD_DESA_8197F) & BIT_MASK_BEQ_TXBD_DESA_8197F)
+#define BIT_SET_BEQ_TXBD_DESA_8197F(x, v)                                      \
+	(BIT_CLEAR_BEQ_TXBD_DESA_8197F(x) | BIT_BEQ_TXBD_DESA_8197F(v))
+
+/* 2 REG_BKQ_TXBD_DESA_8197F */
+
+#define BIT_SHIFT_BKQ_TXBD_DESA_8197F 0
+#define BIT_MASK_BKQ_TXBD_DESA_8197F 0xffffffffffffffffL
+#define BIT_BKQ_TXBD_DESA_8197F(x)                                             \
+	(((x) & BIT_MASK_BKQ_TXBD_DESA_8197F) << BIT_SHIFT_BKQ_TXBD_DESA_8197F)
+#define BITS_BKQ_TXBD_DESA_8197F                                               \
+	(BIT_MASK_BKQ_TXBD_DESA_8197F << BIT_SHIFT_BKQ_TXBD_DESA_8197F)
+#define BIT_CLEAR_BKQ_TXBD_DESA_8197F(x) ((x) & (~BITS_BKQ_TXBD_DESA_8197F))
+#define BIT_GET_BKQ_TXBD_DESA_8197F(x)                                         \
+	(((x) >> BIT_SHIFT_BKQ_TXBD_DESA_8197F) & BIT_MASK_BKQ_TXBD_DESA_8197F)
+#define BIT_SET_BKQ_TXBD_DESA_8197F(x, v)                                      \
+	(BIT_CLEAR_BKQ_TXBD_DESA_8197F(x) | BIT_BKQ_TXBD_DESA_8197F(v))
+
+/* 2 REG_RXQ_RXBD_DESA_8197F */
+
+#define BIT_SHIFT_RXQ_RXBD_DESA_8197F 0
+#define BIT_MASK_RXQ_RXBD_DESA_8197F 0xffffffffffffffffL
+#define BIT_RXQ_RXBD_DESA_8197F(x)                                             \
+	(((x) & BIT_MASK_RXQ_RXBD_DESA_8197F) << BIT_SHIFT_RXQ_RXBD_DESA_8197F)
+#define BITS_RXQ_RXBD_DESA_8197F                                               \
+	(BIT_MASK_RXQ_RXBD_DESA_8197F << BIT_SHIFT_RXQ_RXBD_DESA_8197F)
+#define BIT_CLEAR_RXQ_RXBD_DESA_8197F(x) ((x) & (~BITS_RXQ_RXBD_DESA_8197F))
+#define BIT_GET_RXQ_RXBD_DESA_8197F(x)                                         \
+	(((x) >> BIT_SHIFT_RXQ_RXBD_DESA_8197F) & BIT_MASK_RXQ_RXBD_DESA_8197F)
+#define BIT_SET_RXQ_RXBD_DESA_8197F(x, v)                                      \
+	(BIT_CLEAR_RXQ_RXBD_DESA_8197F(x) | BIT_RXQ_RXBD_DESA_8197F(v))
+
+/* 2 REG_HI0Q_TXBD_DESA_8197F */
+
+#define BIT_SHIFT_HI0Q_TXBD_DESA_8197F 0
+#define BIT_MASK_HI0Q_TXBD_DESA_8197F 0xffffffffffffffffL
+#define BIT_HI0Q_TXBD_DESA_8197F(x)                                            \
+	(((x) & BIT_MASK_HI0Q_TXBD_DESA_8197F)                                 \
+	 << BIT_SHIFT_HI0Q_TXBD_DESA_8197F)
+#define BITS_HI0Q_TXBD_DESA_8197F                                              \
+	(BIT_MASK_HI0Q_TXBD_DESA_8197F << BIT_SHIFT_HI0Q_TXBD_DESA_8197F)
+#define BIT_CLEAR_HI0Q_TXBD_DESA_8197F(x) ((x) & (~BITS_HI0Q_TXBD_DESA_8197F))
+#define BIT_GET_HI0Q_TXBD_DESA_8197F(x)                                        \
+	(((x) >> BIT_SHIFT_HI0Q_TXBD_DESA_8197F) &                             \
+	 BIT_MASK_HI0Q_TXBD_DESA_8197F)
+#define BIT_SET_HI0Q_TXBD_DESA_8197F(x, v)                                     \
+	(BIT_CLEAR_HI0Q_TXBD_DESA_8197F(x) | BIT_HI0Q_TXBD_DESA_8197F(v))
+
+/* 2 REG_HI1Q_TXBD_DESA_8197F */
+
+#define BIT_SHIFT_HI1Q_TXBD_DESA_8197F 0
+#define BIT_MASK_HI1Q_TXBD_DESA_8197F 0xffffffffffffffffL
+#define BIT_HI1Q_TXBD_DESA_8197F(x)                                            \
+	(((x) & BIT_MASK_HI1Q_TXBD_DESA_8197F)                                 \
+	 << BIT_SHIFT_HI1Q_TXBD_DESA_8197F)
+#define BITS_HI1Q_TXBD_DESA_8197F                                              \
+	(BIT_MASK_HI1Q_TXBD_DESA_8197F << BIT_SHIFT_HI1Q_TXBD_DESA_8197F)
+#define BIT_CLEAR_HI1Q_TXBD_DESA_8197F(x) ((x) & (~BITS_HI1Q_TXBD_DESA_8197F))
+#define BIT_GET_HI1Q_TXBD_DESA_8197F(x)                                        \
+	(((x) >> BIT_SHIFT_HI1Q_TXBD_DESA_8197F) &                             \
+	 BIT_MASK_HI1Q_TXBD_DESA_8197F)
+#define BIT_SET_HI1Q_TXBD_DESA_8197F(x, v)                                     \
+	(BIT_CLEAR_HI1Q_TXBD_DESA_8197F(x) | BIT_HI1Q_TXBD_DESA_8197F(v))
+
+/* 2 REG_HI2Q_TXBD_DESA_8197F */
+
+#define BIT_SHIFT_HI2Q_TXBD_DESA_8197F 0
+#define BIT_MASK_HI2Q_TXBD_DESA_8197F 0xffffffffffffffffL
+#define BIT_HI2Q_TXBD_DESA_8197F(x)                                            \
+	(((x) & BIT_MASK_HI2Q_TXBD_DESA_8197F)                                 \
+	 << BIT_SHIFT_HI2Q_TXBD_DESA_8197F)
+#define BITS_HI2Q_TXBD_DESA_8197F                                              \
+	(BIT_MASK_HI2Q_TXBD_DESA_8197F << BIT_SHIFT_HI2Q_TXBD_DESA_8197F)
+#define BIT_CLEAR_HI2Q_TXBD_DESA_8197F(x) ((x) & (~BITS_HI2Q_TXBD_DESA_8197F))
+#define BIT_GET_HI2Q_TXBD_DESA_8197F(x)                                        \
+	(((x) >> BIT_SHIFT_HI2Q_TXBD_DESA_8197F) &                             \
+	 BIT_MASK_HI2Q_TXBD_DESA_8197F)
+#define BIT_SET_HI2Q_TXBD_DESA_8197F(x, v)                                     \
+	(BIT_CLEAR_HI2Q_TXBD_DESA_8197F(x) | BIT_HI2Q_TXBD_DESA_8197F(v))
+
+/* 2 REG_HI3Q_TXBD_DESA_8197F */
+
+#define BIT_SHIFT_HI3Q_TXBD_DESA_8197F 0
+#define BIT_MASK_HI3Q_TXBD_DESA_8197F 0xffffffffffffffffL
+#define BIT_HI3Q_TXBD_DESA_8197F(x)                                            \
+	(((x) & BIT_MASK_HI3Q_TXBD_DESA_8197F)                                 \
+	 << BIT_SHIFT_HI3Q_TXBD_DESA_8197F)
+#define BITS_HI3Q_TXBD_DESA_8197F                                              \
+	(BIT_MASK_HI3Q_TXBD_DESA_8197F << BIT_SHIFT_HI3Q_TXBD_DESA_8197F)
+#define BIT_CLEAR_HI3Q_TXBD_DESA_8197F(x) ((x) & (~BITS_HI3Q_TXBD_DESA_8197F))
+#define BIT_GET_HI3Q_TXBD_DESA_8197F(x)                                        \
+	(((x) >> BIT_SHIFT_HI3Q_TXBD_DESA_8197F) &                             \
+	 BIT_MASK_HI3Q_TXBD_DESA_8197F)
+#define BIT_SET_HI3Q_TXBD_DESA_8197F(x, v)                                     \
+	(BIT_CLEAR_HI3Q_TXBD_DESA_8197F(x) | BIT_HI3Q_TXBD_DESA_8197F(v))
+
+/* 2 REG_HI4Q_TXBD_DESA_8197F */
+
+#define BIT_SHIFT_HI4Q_TXBD_DESA_8197F 0
+#define BIT_MASK_HI4Q_TXBD_DESA_8197F 0xffffffffffffffffL
+#define BIT_HI4Q_TXBD_DESA_8197F(x)                                            \
+	(((x) & BIT_MASK_HI4Q_TXBD_DESA_8197F)                                 \
+	 << BIT_SHIFT_HI4Q_TXBD_DESA_8197F)
+#define BITS_HI4Q_TXBD_DESA_8197F                                              \
+	(BIT_MASK_HI4Q_TXBD_DESA_8197F << BIT_SHIFT_HI4Q_TXBD_DESA_8197F)
+#define BIT_CLEAR_HI4Q_TXBD_DESA_8197F(x) ((x) & (~BITS_HI4Q_TXBD_DESA_8197F))
+#define BIT_GET_HI4Q_TXBD_DESA_8197F(x)                                        \
+	(((x) >> BIT_SHIFT_HI4Q_TXBD_DESA_8197F) &                             \
+	 BIT_MASK_HI4Q_TXBD_DESA_8197F)
+#define BIT_SET_HI4Q_TXBD_DESA_8197F(x, v)                                     \
+	(BIT_CLEAR_HI4Q_TXBD_DESA_8197F(x) | BIT_HI4Q_TXBD_DESA_8197F(v))
+
+/* 2 REG_HI5Q_TXBD_DESA_8197F */
+
+#define BIT_SHIFT_HI5Q_TXBD_DESA_8197F 0
+#define BIT_MASK_HI5Q_TXBD_DESA_8197F 0xffffffffffffffffL
+#define BIT_HI5Q_TXBD_DESA_8197F(x)                                            \
+	(((x) & BIT_MASK_HI5Q_TXBD_DESA_8197F)                                 \
+	 << BIT_SHIFT_HI5Q_TXBD_DESA_8197F)
+#define BITS_HI5Q_TXBD_DESA_8197F                                              \
+	(BIT_MASK_HI5Q_TXBD_DESA_8197F << BIT_SHIFT_HI5Q_TXBD_DESA_8197F)
+#define BIT_CLEAR_HI5Q_TXBD_DESA_8197F(x) ((x) & (~BITS_HI5Q_TXBD_DESA_8197F))
+#define BIT_GET_HI5Q_TXBD_DESA_8197F(x)                                        \
+	(((x) >> BIT_SHIFT_HI5Q_TXBD_DESA_8197F) &                             \
+	 BIT_MASK_HI5Q_TXBD_DESA_8197F)
+#define BIT_SET_HI5Q_TXBD_DESA_8197F(x, v)                                     \
+	(BIT_CLEAR_HI5Q_TXBD_DESA_8197F(x) | BIT_HI5Q_TXBD_DESA_8197F(v))
+
+/* 2 REG_HI6Q_TXBD_DESA_8197F */
+
+#define BIT_SHIFT_HI6Q_TXBD_DESA_8197F 0
+#define BIT_MASK_HI6Q_TXBD_DESA_8197F 0xffffffffffffffffL
+#define BIT_HI6Q_TXBD_DESA_8197F(x)                                            \
+	(((x) & BIT_MASK_HI6Q_TXBD_DESA_8197F)                                 \
+	 << BIT_SHIFT_HI6Q_TXBD_DESA_8197F)
+#define BITS_HI6Q_TXBD_DESA_8197F                                              \
+	(BIT_MASK_HI6Q_TXBD_DESA_8197F << BIT_SHIFT_HI6Q_TXBD_DESA_8197F)
+#define BIT_CLEAR_HI6Q_TXBD_DESA_8197F(x) ((x) & (~BITS_HI6Q_TXBD_DESA_8197F))
+#define BIT_GET_HI6Q_TXBD_DESA_8197F(x)                                        \
+	(((x) >> BIT_SHIFT_HI6Q_TXBD_DESA_8197F) &                             \
+	 BIT_MASK_HI6Q_TXBD_DESA_8197F)
+#define BIT_SET_HI6Q_TXBD_DESA_8197F(x, v)                                     \
+	(BIT_CLEAR_HI6Q_TXBD_DESA_8197F(x) | BIT_HI6Q_TXBD_DESA_8197F(v))
+
+/* 2 REG_HI7Q_TXBD_DESA_8197F */
+
+#define BIT_SHIFT_HI7Q_TXBD_DESA_8197F 0
+#define BIT_MASK_HI7Q_TXBD_DESA_8197F 0xffffffffffffffffL
+#define BIT_HI7Q_TXBD_DESA_8197F(x)                                            \
+	(((x) & BIT_MASK_HI7Q_TXBD_DESA_8197F)                                 \
+	 << BIT_SHIFT_HI7Q_TXBD_DESA_8197F)
+#define BITS_HI7Q_TXBD_DESA_8197F                                              \
+	(BIT_MASK_HI7Q_TXBD_DESA_8197F << BIT_SHIFT_HI7Q_TXBD_DESA_8197F)
+#define BIT_CLEAR_HI7Q_TXBD_DESA_8197F(x) ((x) & (~BITS_HI7Q_TXBD_DESA_8197F))
+#define BIT_GET_HI7Q_TXBD_DESA_8197F(x)                                        \
+	(((x) >> BIT_SHIFT_HI7Q_TXBD_DESA_8197F) &                             \
+	 BIT_MASK_HI7Q_TXBD_DESA_8197F)
+#define BIT_SET_HI7Q_TXBD_DESA_8197F(x, v)                                     \
+	(BIT_CLEAR_HI7Q_TXBD_DESA_8197F(x) | BIT_HI7Q_TXBD_DESA_8197F(v))
+
+/* 2 REG_MGQ_TXBD_NUM_8197F */
+#define BIT_HCI_MGQ_FLAG_8197F BIT(14)
+
+#define BIT_SHIFT_MGQ_DESC_MODE_8197F 12
+#define BIT_MASK_MGQ_DESC_MODE_8197F 0x3
+#define BIT_MGQ_DESC_MODE_8197F(x)                                             \
+	(((x) & BIT_MASK_MGQ_DESC_MODE_8197F) << BIT_SHIFT_MGQ_DESC_MODE_8197F)
+#define BITS_MGQ_DESC_MODE_8197F                                               \
+	(BIT_MASK_MGQ_DESC_MODE_8197F << BIT_SHIFT_MGQ_DESC_MODE_8197F)
+#define BIT_CLEAR_MGQ_DESC_MODE_8197F(x) ((x) & (~BITS_MGQ_DESC_MODE_8197F))
+#define BIT_GET_MGQ_DESC_MODE_8197F(x)                                         \
+	(((x) >> BIT_SHIFT_MGQ_DESC_MODE_8197F) & BIT_MASK_MGQ_DESC_MODE_8197F)
+#define BIT_SET_MGQ_DESC_MODE_8197F(x, v)                                      \
+	(BIT_CLEAR_MGQ_DESC_MODE_8197F(x) | BIT_MGQ_DESC_MODE_8197F(v))
+
+#define BIT_SHIFT_MGQ_DESC_NUM_8197F 0
+#define BIT_MASK_MGQ_DESC_NUM_8197F 0xfff
+#define BIT_MGQ_DESC_NUM_8197F(x)                                              \
+	(((x) & BIT_MASK_MGQ_DESC_NUM_8197F) << BIT_SHIFT_MGQ_DESC_NUM_8197F)
+#define BITS_MGQ_DESC_NUM_8197F                                                \
+	(BIT_MASK_MGQ_DESC_NUM_8197F << BIT_SHIFT_MGQ_DESC_NUM_8197F)
+#define BIT_CLEAR_MGQ_DESC_NUM_8197F(x) ((x) & (~BITS_MGQ_DESC_NUM_8197F))
+#define BIT_GET_MGQ_DESC_NUM_8197F(x)                                          \
+	(((x) >> BIT_SHIFT_MGQ_DESC_NUM_8197F) & BIT_MASK_MGQ_DESC_NUM_8197F)
+#define BIT_SET_MGQ_DESC_NUM_8197F(x, v)                                       \
+	(BIT_CLEAR_MGQ_DESC_NUM_8197F(x) | BIT_MGQ_DESC_NUM_8197F(v))
+
+/* 2 REG_RX_RXBD_NUM_8197F */
+#define BIT_SYS_32_64_8197F BIT(15)
+
+#define BIT_SHIFT_BCNQ_DESC_MODE_8197F 13
+#define BIT_MASK_BCNQ_DESC_MODE_8197F 0x3
+#define BIT_BCNQ_DESC_MODE_8197F(x)                                            \
+	(((x) & BIT_MASK_BCNQ_DESC_MODE_8197F)                                 \
+	 << BIT_SHIFT_BCNQ_DESC_MODE_8197F)
+#define BITS_BCNQ_DESC_MODE_8197F                                              \
+	(BIT_MASK_BCNQ_DESC_MODE_8197F << BIT_SHIFT_BCNQ_DESC_MODE_8197F)
+#define BIT_CLEAR_BCNQ_DESC_MODE_8197F(x) ((x) & (~BITS_BCNQ_DESC_MODE_8197F))
+#define BIT_GET_BCNQ_DESC_MODE_8197F(x)                                        \
+	(((x) >> BIT_SHIFT_BCNQ_DESC_MODE_8197F) &                             \
+	 BIT_MASK_BCNQ_DESC_MODE_8197F)
+#define BIT_SET_BCNQ_DESC_MODE_8197F(x, v)                                     \
+	(BIT_CLEAR_BCNQ_DESC_MODE_8197F(x) | BIT_BCNQ_DESC_MODE_8197F(v))
+
+#define BIT_HCI_BCNQ_FLAG_8197F BIT(12)
+
+#define BIT_SHIFT_RXQ_DESC_NUM_8197F 0
+#define BIT_MASK_RXQ_DESC_NUM_8197F 0xfff
+#define BIT_RXQ_DESC_NUM_8197F(x)                                              \
+	(((x) & BIT_MASK_RXQ_DESC_NUM_8197F) << BIT_SHIFT_RXQ_DESC_NUM_8197F)
+#define BITS_RXQ_DESC_NUM_8197F                                                \
+	(BIT_MASK_RXQ_DESC_NUM_8197F << BIT_SHIFT_RXQ_DESC_NUM_8197F)
+#define BIT_CLEAR_RXQ_DESC_NUM_8197F(x) ((x) & (~BITS_RXQ_DESC_NUM_8197F))
+#define BIT_GET_RXQ_DESC_NUM_8197F(x)                                          \
+	(((x) >> BIT_SHIFT_RXQ_DESC_NUM_8197F) & BIT_MASK_RXQ_DESC_NUM_8197F)
+#define BIT_SET_RXQ_DESC_NUM_8197F(x, v)                                       \
+	(BIT_CLEAR_RXQ_DESC_NUM_8197F(x) | BIT_RXQ_DESC_NUM_8197F(v))
+
+/* 2 REG_VOQ_TXBD_NUM_8197F */
+#define BIT_HCI_VOQ_FLAG_8197F BIT(14)
+
+#define BIT_SHIFT_VOQ_DESC_MODE_8197F 12
+#define BIT_MASK_VOQ_DESC_MODE_8197F 0x3
+#define BIT_VOQ_DESC_MODE_8197F(x)                                             \
+	(((x) & BIT_MASK_VOQ_DESC_MODE_8197F) << BIT_SHIFT_VOQ_DESC_MODE_8197F)
+#define BITS_VOQ_DESC_MODE_8197F                                               \
+	(BIT_MASK_VOQ_DESC_MODE_8197F << BIT_SHIFT_VOQ_DESC_MODE_8197F)
+#define BIT_CLEAR_VOQ_DESC_MODE_8197F(x) ((x) & (~BITS_VOQ_DESC_MODE_8197F))
+#define BIT_GET_VOQ_DESC_MODE_8197F(x)                                         \
+	(((x) >> BIT_SHIFT_VOQ_DESC_MODE_8197F) & BIT_MASK_VOQ_DESC_MODE_8197F)
+#define BIT_SET_VOQ_DESC_MODE_8197F(x, v)                                      \
+	(BIT_CLEAR_VOQ_DESC_MODE_8197F(x) | BIT_VOQ_DESC_MODE_8197F(v))
+
+#define BIT_SHIFT_VOQ_DESC_NUM_8197F 0
+#define BIT_MASK_VOQ_DESC_NUM_8197F 0xfff
+#define BIT_VOQ_DESC_NUM_8197F(x)                                              \
+	(((x) & BIT_MASK_VOQ_DESC_NUM_8197F) << BIT_SHIFT_VOQ_DESC_NUM_8197F)
+#define BITS_VOQ_DESC_NUM_8197F                                                \
+	(BIT_MASK_VOQ_DESC_NUM_8197F << BIT_SHIFT_VOQ_DESC_NUM_8197F)
+#define BIT_CLEAR_VOQ_DESC_NUM_8197F(x) ((x) & (~BITS_VOQ_DESC_NUM_8197F))
+#define BIT_GET_VOQ_DESC_NUM_8197F(x)                                          \
+	(((x) >> BIT_SHIFT_VOQ_DESC_NUM_8197F) & BIT_MASK_VOQ_DESC_NUM_8197F)
+#define BIT_SET_VOQ_DESC_NUM_8197F(x, v)                                       \
+	(BIT_CLEAR_VOQ_DESC_NUM_8197F(x) | BIT_VOQ_DESC_NUM_8197F(v))
+
+/* 2 REG_VIQ_TXBD_NUM_8197F */
+#define BIT_HCI_VIQ_FLAG_8197F BIT(14)
+
+#define BIT_SHIFT_VIQ_DESC_MODE_8197F 12
+#define BIT_MASK_VIQ_DESC_MODE_8197F 0x3
+#define BIT_VIQ_DESC_MODE_8197F(x)                                             \
+	(((x) & BIT_MASK_VIQ_DESC_MODE_8197F) << BIT_SHIFT_VIQ_DESC_MODE_8197F)
+#define BITS_VIQ_DESC_MODE_8197F                                               \
+	(BIT_MASK_VIQ_DESC_MODE_8197F << BIT_SHIFT_VIQ_DESC_MODE_8197F)
+#define BIT_CLEAR_VIQ_DESC_MODE_8197F(x) ((x) & (~BITS_VIQ_DESC_MODE_8197F))
+#define BIT_GET_VIQ_DESC_MODE_8197F(x)                                         \
+	(((x) >> BIT_SHIFT_VIQ_DESC_MODE_8197F) & BIT_MASK_VIQ_DESC_MODE_8197F)
+#define BIT_SET_VIQ_DESC_MODE_8197F(x, v)                                      \
+	(BIT_CLEAR_VIQ_DESC_MODE_8197F(x) | BIT_VIQ_DESC_MODE_8197F(v))
+
+#define BIT_SHIFT_VIQ_DESC_NUM_8197F 0
+#define BIT_MASK_VIQ_DESC_NUM_8197F 0xfff
+#define BIT_VIQ_DESC_NUM_8197F(x)                                              \
+	(((x) & BIT_MASK_VIQ_DESC_NUM_8197F) << BIT_SHIFT_VIQ_DESC_NUM_8197F)
+#define BITS_VIQ_DESC_NUM_8197F                                                \
+	(BIT_MASK_VIQ_DESC_NUM_8197F << BIT_SHIFT_VIQ_DESC_NUM_8197F)
+#define BIT_CLEAR_VIQ_DESC_NUM_8197F(x) ((x) & (~BITS_VIQ_DESC_NUM_8197F))
+#define BIT_GET_VIQ_DESC_NUM_8197F(x)                                          \
+	(((x) >> BIT_SHIFT_VIQ_DESC_NUM_8197F) & BIT_MASK_VIQ_DESC_NUM_8197F)
+#define BIT_SET_VIQ_DESC_NUM_8197F(x, v)                                       \
+	(BIT_CLEAR_VIQ_DESC_NUM_8197F(x) | BIT_VIQ_DESC_NUM_8197F(v))
+
+/* 2 REG_BEQ_TXBD_NUM_8197F */
+#define BIT_HCI_BEQ_FLAG_8197F BIT(14)
+
+#define BIT_SHIFT_BEQ_DESC_MODE_8197F 12
+#define BIT_MASK_BEQ_DESC_MODE_8197F 0x3
+#define BIT_BEQ_DESC_MODE_8197F(x)                                             \
+	(((x) & BIT_MASK_BEQ_DESC_MODE_8197F) << BIT_SHIFT_BEQ_DESC_MODE_8197F)
+#define BITS_BEQ_DESC_MODE_8197F                                               \
+	(BIT_MASK_BEQ_DESC_MODE_8197F << BIT_SHIFT_BEQ_DESC_MODE_8197F)
+#define BIT_CLEAR_BEQ_DESC_MODE_8197F(x) ((x) & (~BITS_BEQ_DESC_MODE_8197F))
+#define BIT_GET_BEQ_DESC_MODE_8197F(x)                                         \
+	(((x) >> BIT_SHIFT_BEQ_DESC_MODE_8197F) & BIT_MASK_BEQ_DESC_MODE_8197F)
+#define BIT_SET_BEQ_DESC_MODE_8197F(x, v)                                      \
+	(BIT_CLEAR_BEQ_DESC_MODE_8197F(x) | BIT_BEQ_DESC_MODE_8197F(v))
+
+#define BIT_SHIFT_BEQ_DESC_NUM_8197F 0
+#define BIT_MASK_BEQ_DESC_NUM_8197F 0xfff
+#define BIT_BEQ_DESC_NUM_8197F(x)                                              \
+	(((x) & BIT_MASK_BEQ_DESC_NUM_8197F) << BIT_SHIFT_BEQ_DESC_NUM_8197F)
+#define BITS_BEQ_DESC_NUM_8197F                                                \
+	(BIT_MASK_BEQ_DESC_NUM_8197F << BIT_SHIFT_BEQ_DESC_NUM_8197F)
+#define BIT_CLEAR_BEQ_DESC_NUM_8197F(x) ((x) & (~BITS_BEQ_DESC_NUM_8197F))
+#define BIT_GET_BEQ_DESC_NUM_8197F(x)                                          \
+	(((x) >> BIT_SHIFT_BEQ_DESC_NUM_8197F) & BIT_MASK_BEQ_DESC_NUM_8197F)
+#define BIT_SET_BEQ_DESC_NUM_8197F(x, v)                                       \
+	(BIT_CLEAR_BEQ_DESC_NUM_8197F(x) | BIT_BEQ_DESC_NUM_8197F(v))
+
+/* 2 REG_BKQ_TXBD_NUM_8197F */
+#define BIT_HCI_BKQ_FLAG_8197F BIT(14)
+
+#define BIT_SHIFT_BKQ_DESC_MODE_8197F 12
+#define BIT_MASK_BKQ_DESC_MODE_8197F 0x3
+#define BIT_BKQ_DESC_MODE_8197F(x)                                             \
+	(((x) & BIT_MASK_BKQ_DESC_MODE_8197F) << BIT_SHIFT_BKQ_DESC_MODE_8197F)
+#define BITS_BKQ_DESC_MODE_8197F                                               \
+	(BIT_MASK_BKQ_DESC_MODE_8197F << BIT_SHIFT_BKQ_DESC_MODE_8197F)
+#define BIT_CLEAR_BKQ_DESC_MODE_8197F(x) ((x) & (~BITS_BKQ_DESC_MODE_8197F))
+#define BIT_GET_BKQ_DESC_MODE_8197F(x)                                         \
+	(((x) >> BIT_SHIFT_BKQ_DESC_MODE_8197F) & BIT_MASK_BKQ_DESC_MODE_8197F)
+#define BIT_SET_BKQ_DESC_MODE_8197F(x, v)                                      \
+	(BIT_CLEAR_BKQ_DESC_MODE_8197F(x) | BIT_BKQ_DESC_MODE_8197F(v))
+
+#define BIT_SHIFT_BKQ_DESC_NUM_8197F 0
+#define BIT_MASK_BKQ_DESC_NUM_8197F 0xfff
+#define BIT_BKQ_DESC_NUM_8197F(x)                                              \
+	(((x) & BIT_MASK_BKQ_DESC_NUM_8197F) << BIT_SHIFT_BKQ_DESC_NUM_8197F)
+#define BITS_BKQ_DESC_NUM_8197F                                                \
+	(BIT_MASK_BKQ_DESC_NUM_8197F << BIT_SHIFT_BKQ_DESC_NUM_8197F)
+#define BIT_CLEAR_BKQ_DESC_NUM_8197F(x) ((x) & (~BITS_BKQ_DESC_NUM_8197F))
+#define BIT_GET_BKQ_DESC_NUM_8197F(x)                                          \
+	(((x) >> BIT_SHIFT_BKQ_DESC_NUM_8197F) & BIT_MASK_BKQ_DESC_NUM_8197F)
+#define BIT_SET_BKQ_DESC_NUM_8197F(x, v)                                       \
+	(BIT_CLEAR_BKQ_DESC_NUM_8197F(x) | BIT_BKQ_DESC_NUM_8197F(v))
+
+/* 2 REG_HI0Q_TXBD_NUM_8197F */
+#define BIT_HI0Q_FLAG_8197F BIT(14)
+
+#define BIT_SHIFT_HI0Q_DESC_MODE_8197F 12
+#define BIT_MASK_HI0Q_DESC_MODE_8197F 0x3
+#define BIT_HI0Q_DESC_MODE_8197F(x)                                            \
+	(((x) & BIT_MASK_HI0Q_DESC_MODE_8197F)                                 \
+	 << BIT_SHIFT_HI0Q_DESC_MODE_8197F)
+#define BITS_HI0Q_DESC_MODE_8197F                                              \
+	(BIT_MASK_HI0Q_DESC_MODE_8197F << BIT_SHIFT_HI0Q_DESC_MODE_8197F)
+#define BIT_CLEAR_HI0Q_DESC_MODE_8197F(x) ((x) & (~BITS_HI0Q_DESC_MODE_8197F))
+#define BIT_GET_HI0Q_DESC_MODE_8197F(x)                                        \
+	(((x) >> BIT_SHIFT_HI0Q_DESC_MODE_8197F) &                             \
+	 BIT_MASK_HI0Q_DESC_MODE_8197F)
+#define BIT_SET_HI0Q_DESC_MODE_8197F(x, v)                                     \
+	(BIT_CLEAR_HI0Q_DESC_MODE_8197F(x) | BIT_HI0Q_DESC_MODE_8197F(v))
+
+#define BIT_SHIFT_HI0Q_DESC_NUM_8197F 0
+#define BIT_MASK_HI0Q_DESC_NUM_8197F 0xfff
+#define BIT_HI0Q_DESC_NUM_8197F(x)                                             \
+	(((x) & BIT_MASK_HI0Q_DESC_NUM_8197F) << BIT_SHIFT_HI0Q_DESC_NUM_8197F)
+#define BITS_HI0Q_DESC_NUM_8197F                                               \
+	(BIT_MASK_HI0Q_DESC_NUM_8197F << BIT_SHIFT_HI0Q_DESC_NUM_8197F)
+#define BIT_CLEAR_HI0Q_DESC_NUM_8197F(x) ((x) & (~BITS_HI0Q_DESC_NUM_8197F))
+#define BIT_GET_HI0Q_DESC_NUM_8197F(x)                                         \
+	(((x) >> BIT_SHIFT_HI0Q_DESC_NUM_8197F) & BIT_MASK_HI0Q_DESC_NUM_8197F)
+#define BIT_SET_HI0Q_DESC_NUM_8197F(x, v)                                      \
+	(BIT_CLEAR_HI0Q_DESC_NUM_8197F(x) | BIT_HI0Q_DESC_NUM_8197F(v))
+
+/* 2 REG_HI1Q_TXBD_NUM_8197F */
+#define BIT_HI1Q_FLAG_8197F BIT(14)
+
+#define BIT_SHIFT_HI1Q_DESC_MODE_8197F 12
+#define BIT_MASK_HI1Q_DESC_MODE_8197F 0x3
+#define BIT_HI1Q_DESC_MODE_8197F(x)                                            \
+	(((x) & BIT_MASK_HI1Q_DESC_MODE_8197F)                                 \
+	 << BIT_SHIFT_HI1Q_DESC_MODE_8197F)
+#define BITS_HI1Q_DESC_MODE_8197F                                              \
+	(BIT_MASK_HI1Q_DESC_MODE_8197F << BIT_SHIFT_HI1Q_DESC_MODE_8197F)
+#define BIT_CLEAR_HI1Q_DESC_MODE_8197F(x) ((x) & (~BITS_HI1Q_DESC_MODE_8197F))
+#define BIT_GET_HI1Q_DESC_MODE_8197F(x)                                        \
+	(((x) >> BIT_SHIFT_HI1Q_DESC_MODE_8197F) &                             \
+	 BIT_MASK_HI1Q_DESC_MODE_8197F)
+#define BIT_SET_HI1Q_DESC_MODE_8197F(x, v)                                     \
+	(BIT_CLEAR_HI1Q_DESC_MODE_8197F(x) | BIT_HI1Q_DESC_MODE_8197F(v))
+
+#define BIT_SHIFT_HI1Q_DESC_NUM_8197F 0
+#define BIT_MASK_HI1Q_DESC_NUM_8197F 0xfff
+#define BIT_HI1Q_DESC_NUM_8197F(x)                                             \
+	(((x) & BIT_MASK_HI1Q_DESC_NUM_8197F) << BIT_SHIFT_HI1Q_DESC_NUM_8197F)
+#define BITS_HI1Q_DESC_NUM_8197F                                               \
+	(BIT_MASK_HI1Q_DESC_NUM_8197F << BIT_SHIFT_HI1Q_DESC_NUM_8197F)
+#define BIT_CLEAR_HI1Q_DESC_NUM_8197F(x) ((x) & (~BITS_HI1Q_DESC_NUM_8197F))
+#define BIT_GET_HI1Q_DESC_NUM_8197F(x)                                         \
+	(((x) >> BIT_SHIFT_HI1Q_DESC_NUM_8197F) & BIT_MASK_HI1Q_DESC_NUM_8197F)
+#define BIT_SET_HI1Q_DESC_NUM_8197F(x, v)                                      \
+	(BIT_CLEAR_HI1Q_DESC_NUM_8197F(x) | BIT_HI1Q_DESC_NUM_8197F(v))
+
+/* 2 REG_HI2Q_TXBD_NUM_8197F */
+#define BIT_HI2Q_FLAG_8197F BIT(14)
+
+#define BIT_SHIFT_HI2Q_DESC_MODE_8197F 12
+#define BIT_MASK_HI2Q_DESC_MODE_8197F 0x3
+#define BIT_HI2Q_DESC_MODE_8197F(x)                                            \
+	(((x) & BIT_MASK_HI2Q_DESC_MODE_8197F)                                 \
+	 << BIT_SHIFT_HI2Q_DESC_MODE_8197F)
+#define BITS_HI2Q_DESC_MODE_8197F                                              \
+	(BIT_MASK_HI2Q_DESC_MODE_8197F << BIT_SHIFT_HI2Q_DESC_MODE_8197F)
+#define BIT_CLEAR_HI2Q_DESC_MODE_8197F(x) ((x) & (~BITS_HI2Q_DESC_MODE_8197F))
+#define BIT_GET_HI2Q_DESC_MODE_8197F(x)                                        \
+	(((x) >> BIT_SHIFT_HI2Q_DESC_MODE_8197F) &                             \
+	 BIT_MASK_HI2Q_DESC_MODE_8197F)
+#define BIT_SET_HI2Q_DESC_MODE_8197F(x, v)                                     \
+	(BIT_CLEAR_HI2Q_DESC_MODE_8197F(x) | BIT_HI2Q_DESC_MODE_8197F(v))
+
+#define BIT_SHIFT_HI2Q_DESC_NUM_8197F 0
+#define BIT_MASK_HI2Q_DESC_NUM_8197F 0xfff
+#define BIT_HI2Q_DESC_NUM_8197F(x)                                             \
+	(((x) & BIT_MASK_HI2Q_DESC_NUM_8197F) << BIT_SHIFT_HI2Q_DESC_NUM_8197F)
+#define BITS_HI2Q_DESC_NUM_8197F                                               \
+	(BIT_MASK_HI2Q_DESC_NUM_8197F << BIT_SHIFT_HI2Q_DESC_NUM_8197F)
+#define BIT_CLEAR_HI2Q_DESC_NUM_8197F(x) ((x) & (~BITS_HI2Q_DESC_NUM_8197F))
+#define BIT_GET_HI2Q_DESC_NUM_8197F(x)                                         \
+	(((x) >> BIT_SHIFT_HI2Q_DESC_NUM_8197F) & BIT_MASK_HI2Q_DESC_NUM_8197F)
+#define BIT_SET_HI2Q_DESC_NUM_8197F(x, v)                                      \
+	(BIT_CLEAR_HI2Q_DESC_NUM_8197F(x) | BIT_HI2Q_DESC_NUM_8197F(v))
+
+/* 2 REG_HI3Q_TXBD_NUM_8197F */
+#define BIT_HI3Q_FLAG_8197F BIT(14)
+
+#define BIT_SHIFT_HI3Q_DESC_MODE_8197F 12
+#define BIT_MASK_HI3Q_DESC_MODE_8197F 0x3
+#define BIT_HI3Q_DESC_MODE_8197F(x)                                            \
+	(((x) & BIT_MASK_HI3Q_DESC_MODE_8197F)                                 \
+	 << BIT_SHIFT_HI3Q_DESC_MODE_8197F)
+#define BITS_HI3Q_DESC_MODE_8197F                                              \
+	(BIT_MASK_HI3Q_DESC_MODE_8197F << BIT_SHIFT_HI3Q_DESC_MODE_8197F)
+#define BIT_CLEAR_HI3Q_DESC_MODE_8197F(x) ((x) & (~BITS_HI3Q_DESC_MODE_8197F))
+#define BIT_GET_HI3Q_DESC_MODE_8197F(x)                                        \
+	(((x) >> BIT_SHIFT_HI3Q_DESC_MODE_8197F) &                             \
+	 BIT_MASK_HI3Q_DESC_MODE_8197F)
+#define BIT_SET_HI3Q_DESC_MODE_8197F(x, v)                                     \
+	(BIT_CLEAR_HI3Q_DESC_MODE_8197F(x) | BIT_HI3Q_DESC_MODE_8197F(v))
+
+#define BIT_SHIFT_HI3Q_DESC_NUM_8197F 0
+#define BIT_MASK_HI3Q_DESC_NUM_8197F 0xfff
+#define BIT_HI3Q_DESC_NUM_8197F(x)                                             \
+	(((x) & BIT_MASK_HI3Q_DESC_NUM_8197F) << BIT_SHIFT_HI3Q_DESC_NUM_8197F)
+#define BITS_HI3Q_DESC_NUM_8197F                                               \
+	(BIT_MASK_HI3Q_DESC_NUM_8197F << BIT_SHIFT_HI3Q_DESC_NUM_8197F)
+#define BIT_CLEAR_HI3Q_DESC_NUM_8197F(x) ((x) & (~BITS_HI3Q_DESC_NUM_8197F))
+#define BIT_GET_HI3Q_DESC_NUM_8197F(x)                                         \
+	(((x) >> BIT_SHIFT_HI3Q_DESC_NUM_8197F) & BIT_MASK_HI3Q_DESC_NUM_8197F)
+#define BIT_SET_HI3Q_DESC_NUM_8197F(x, v)                                      \
+	(BIT_CLEAR_HI3Q_DESC_NUM_8197F(x) | BIT_HI3Q_DESC_NUM_8197F(v))
+
+/* 2 REG_HI4Q_TXBD_NUM_8197F */
+#define BIT_HI4Q_FLAG_8197F BIT(14)
+
+#define BIT_SHIFT_HI4Q_DESC_MODE_8197F 12
+#define BIT_MASK_HI4Q_DESC_MODE_8197F 0x3
+#define BIT_HI4Q_DESC_MODE_8197F(x)                                            \
+	(((x) & BIT_MASK_HI4Q_DESC_MODE_8197F)                                 \
+	 << BIT_SHIFT_HI4Q_DESC_MODE_8197F)
+#define BITS_HI4Q_DESC_MODE_8197F                                              \
+	(BIT_MASK_HI4Q_DESC_MODE_8197F << BIT_SHIFT_HI4Q_DESC_MODE_8197F)
+#define BIT_CLEAR_HI4Q_DESC_MODE_8197F(x) ((x) & (~BITS_HI4Q_DESC_MODE_8197F))
+#define BIT_GET_HI4Q_DESC_MODE_8197F(x)                                        \
+	(((x) >> BIT_SHIFT_HI4Q_DESC_MODE_8197F) &                             \
+	 BIT_MASK_HI4Q_DESC_MODE_8197F)
+#define BIT_SET_HI4Q_DESC_MODE_8197F(x, v)                                     \
+	(BIT_CLEAR_HI4Q_DESC_MODE_8197F(x) | BIT_HI4Q_DESC_MODE_8197F(v))
+
+#define BIT_SHIFT_HI4Q_DESC_NUM_8197F 0
+#define BIT_MASK_HI4Q_DESC_NUM_8197F 0xfff
+#define BIT_HI4Q_DESC_NUM_8197F(x)                                             \
+	(((x) & BIT_MASK_HI4Q_DESC_NUM_8197F) << BIT_SHIFT_HI4Q_DESC_NUM_8197F)
+#define BITS_HI4Q_DESC_NUM_8197F                                               \
+	(BIT_MASK_HI4Q_DESC_NUM_8197F << BIT_SHIFT_HI4Q_DESC_NUM_8197F)
+#define BIT_CLEAR_HI4Q_DESC_NUM_8197F(x) ((x) & (~BITS_HI4Q_DESC_NUM_8197F))
+#define BIT_GET_HI4Q_DESC_NUM_8197F(x)                                         \
+	(((x) >> BIT_SHIFT_HI4Q_DESC_NUM_8197F) & BIT_MASK_HI4Q_DESC_NUM_8197F)
+#define BIT_SET_HI4Q_DESC_NUM_8197F(x, v)                                      \
+	(BIT_CLEAR_HI4Q_DESC_NUM_8197F(x) | BIT_HI4Q_DESC_NUM_8197F(v))
+
+/* 2 REG_HI5Q_TXBD_NUM_8197F */
+#define BIT_HI5Q_FLAG_8197F BIT(14)
+
+#define BIT_SHIFT_HI5Q_DESC_MODE_8197F 12
+#define BIT_MASK_HI5Q_DESC_MODE_8197F 0x3
+#define BIT_HI5Q_DESC_MODE_8197F(x)                                            \
+	(((x) & BIT_MASK_HI5Q_DESC_MODE_8197F)                                 \
+	 << BIT_SHIFT_HI5Q_DESC_MODE_8197F)
+#define BITS_HI5Q_DESC_MODE_8197F                                              \
+	(BIT_MASK_HI5Q_DESC_MODE_8197F << BIT_SHIFT_HI5Q_DESC_MODE_8197F)
+#define BIT_CLEAR_HI5Q_DESC_MODE_8197F(x) ((x) & (~BITS_HI5Q_DESC_MODE_8197F))
+#define BIT_GET_HI5Q_DESC_MODE_8197F(x)                                        \
+	(((x) >> BIT_SHIFT_HI5Q_DESC_MODE_8197F) &                             \
+	 BIT_MASK_HI5Q_DESC_MODE_8197F)
+#define BIT_SET_HI5Q_DESC_MODE_8197F(x, v)                                     \
+	(BIT_CLEAR_HI5Q_DESC_MODE_8197F(x) | BIT_HI5Q_DESC_MODE_8197F(v))
+
+#define BIT_SHIFT_HI5Q_DESC_NUM_8197F 0
+#define BIT_MASK_HI5Q_DESC_NUM_8197F 0xfff
+#define BIT_HI5Q_DESC_NUM_8197F(x)                                             \
+	(((x) & BIT_MASK_HI5Q_DESC_NUM_8197F) << BIT_SHIFT_HI5Q_DESC_NUM_8197F)
+#define BITS_HI5Q_DESC_NUM_8197F                                               \
+	(BIT_MASK_HI5Q_DESC_NUM_8197F << BIT_SHIFT_HI5Q_DESC_NUM_8197F)
+#define BIT_CLEAR_HI5Q_DESC_NUM_8197F(x) ((x) & (~BITS_HI5Q_DESC_NUM_8197F))
+#define BIT_GET_HI5Q_DESC_NUM_8197F(x)                                         \
+	(((x) >> BIT_SHIFT_HI5Q_DESC_NUM_8197F) & BIT_MASK_HI5Q_DESC_NUM_8197F)
+#define BIT_SET_HI5Q_DESC_NUM_8197F(x, v)                                      \
+	(BIT_CLEAR_HI5Q_DESC_NUM_8197F(x) | BIT_HI5Q_DESC_NUM_8197F(v))
+
+/* 2 REG_HI6Q_TXBD_NUM_8197F */
+#define BIT_HI6Q_FLAG_8197F BIT(14)
+
+#define BIT_SHIFT_HI6Q_DESC_MODE_8197F 12
+#define BIT_MASK_HI6Q_DESC_MODE_8197F 0x3
+#define BIT_HI6Q_DESC_MODE_8197F(x)                                            \
+	(((x) & BIT_MASK_HI6Q_DESC_MODE_8197F)                                 \
+	 << BIT_SHIFT_HI6Q_DESC_MODE_8197F)
+#define BITS_HI6Q_DESC_MODE_8197F                                              \
+	(BIT_MASK_HI6Q_DESC_MODE_8197F << BIT_SHIFT_HI6Q_DESC_MODE_8197F)
+#define BIT_CLEAR_HI6Q_DESC_MODE_8197F(x) ((x) & (~BITS_HI6Q_DESC_MODE_8197F))
+#define BIT_GET_HI6Q_DESC_MODE_8197F(x)                                        \
+	(((x) >> BIT_SHIFT_HI6Q_DESC_MODE_8197F) &                             \
+	 BIT_MASK_HI6Q_DESC_MODE_8197F)
+#define BIT_SET_HI6Q_DESC_MODE_8197F(x, v)                                     \
+	(BIT_CLEAR_HI6Q_DESC_MODE_8197F(x) | BIT_HI6Q_DESC_MODE_8197F(v))
+
+#define BIT_SHIFT_HI6Q_DESC_NUM_8197F 0
+#define BIT_MASK_HI6Q_DESC_NUM_8197F 0xfff
+#define BIT_HI6Q_DESC_NUM_8197F(x)                                             \
+	(((x) & BIT_MASK_HI6Q_DESC_NUM_8197F) << BIT_SHIFT_HI6Q_DESC_NUM_8197F)
+#define BITS_HI6Q_DESC_NUM_8197F                                               \
+	(BIT_MASK_HI6Q_DESC_NUM_8197F << BIT_SHIFT_HI6Q_DESC_NUM_8197F)
+#define BIT_CLEAR_HI6Q_DESC_NUM_8197F(x) ((x) & (~BITS_HI6Q_DESC_NUM_8197F))
+#define BIT_GET_HI6Q_DESC_NUM_8197F(x)                                         \
+	(((x) >> BIT_SHIFT_HI6Q_DESC_NUM_8197F) & BIT_MASK_HI6Q_DESC_NUM_8197F)
+#define BIT_SET_HI6Q_DESC_NUM_8197F(x, v)                                      \
+	(BIT_CLEAR_HI6Q_DESC_NUM_8197F(x) | BIT_HI6Q_DESC_NUM_8197F(v))
+
+/* 2 REG_HI7Q_TXBD_NUM_8197F */
+#define BIT_HI7Q_FLAG_8197F BIT(14)
+
+#define BIT_SHIFT_HI7Q_DESC_MODE_8197F 12
+#define BIT_MASK_HI7Q_DESC_MODE_8197F 0x3
+#define BIT_HI7Q_DESC_MODE_8197F(x)                                            \
+	(((x) & BIT_MASK_HI7Q_DESC_MODE_8197F)                                 \
+	 << BIT_SHIFT_HI7Q_DESC_MODE_8197F)
+#define BITS_HI7Q_DESC_MODE_8197F                                              \
+	(BIT_MASK_HI7Q_DESC_MODE_8197F << BIT_SHIFT_HI7Q_DESC_MODE_8197F)
+#define BIT_CLEAR_HI7Q_DESC_MODE_8197F(x) ((x) & (~BITS_HI7Q_DESC_MODE_8197F))
+#define BIT_GET_HI7Q_DESC_MODE_8197F(x)                                        \
+	(((x) >> BIT_SHIFT_HI7Q_DESC_MODE_8197F) &                             \
+	 BIT_MASK_HI7Q_DESC_MODE_8197F)
+#define BIT_SET_HI7Q_DESC_MODE_8197F(x, v)                                     \
+	(BIT_CLEAR_HI7Q_DESC_MODE_8197F(x) | BIT_HI7Q_DESC_MODE_8197F(v))
+
+#define BIT_SHIFT_HI7Q_DESC_NUM_8197F 0
+#define BIT_MASK_HI7Q_DESC_NUM_8197F 0xfff
+#define BIT_HI7Q_DESC_NUM_8197F(x)                                             \
+	(((x) & BIT_MASK_HI7Q_DESC_NUM_8197F) << BIT_SHIFT_HI7Q_DESC_NUM_8197F)
+#define BITS_HI7Q_DESC_NUM_8197F                                               \
+	(BIT_MASK_HI7Q_DESC_NUM_8197F << BIT_SHIFT_HI7Q_DESC_NUM_8197F)
+#define BIT_CLEAR_HI7Q_DESC_NUM_8197F(x) ((x) & (~BITS_HI7Q_DESC_NUM_8197F))
+#define BIT_GET_HI7Q_DESC_NUM_8197F(x)                                         \
+	(((x) >> BIT_SHIFT_HI7Q_DESC_NUM_8197F) & BIT_MASK_HI7Q_DESC_NUM_8197F)
+#define BIT_SET_HI7Q_DESC_NUM_8197F(x, v)                                      \
+	(BIT_CLEAR_HI7Q_DESC_NUM_8197F(x) | BIT_HI7Q_DESC_NUM_8197F(v))
+
+/* 2 REG_TSFTIMER_HCI_8197F */
+
+#define BIT_SHIFT_TSFT2_HCI_8197F 16
+#define BIT_MASK_TSFT2_HCI_8197F 0xffff
+#define BIT_TSFT2_HCI_8197F(x)                                                 \
+	(((x) & BIT_MASK_TSFT2_HCI_8197F) << BIT_SHIFT_TSFT2_HCI_8197F)
+#define BITS_TSFT2_HCI_8197F                                                   \
+	(BIT_MASK_TSFT2_HCI_8197F << BIT_SHIFT_TSFT2_HCI_8197F)
+#define BIT_CLEAR_TSFT2_HCI_8197F(x) ((x) & (~BITS_TSFT2_HCI_8197F))
+#define BIT_GET_TSFT2_HCI_8197F(x)                                             \
+	(((x) >> BIT_SHIFT_TSFT2_HCI_8197F) & BIT_MASK_TSFT2_HCI_8197F)
+#define BIT_SET_TSFT2_HCI_8197F(x, v)                                          \
+	(BIT_CLEAR_TSFT2_HCI_8197F(x) | BIT_TSFT2_HCI_8197F(v))
+
+#define BIT_SHIFT_TSFT1_HCI_8197F 0
+#define BIT_MASK_TSFT1_HCI_8197F 0xffff
+#define BIT_TSFT1_HCI_8197F(x)                                                 \
+	(((x) & BIT_MASK_TSFT1_HCI_8197F) << BIT_SHIFT_TSFT1_HCI_8197F)
+#define BITS_TSFT1_HCI_8197F                                                   \
+	(BIT_MASK_TSFT1_HCI_8197F << BIT_SHIFT_TSFT1_HCI_8197F)
+#define BIT_CLEAR_TSFT1_HCI_8197F(x) ((x) & (~BITS_TSFT1_HCI_8197F))
+#define BIT_GET_TSFT1_HCI_8197F(x)                                             \
+	(((x) >> BIT_SHIFT_TSFT1_HCI_8197F) & BIT_MASK_TSFT1_HCI_8197F)
+#define BIT_SET_TSFT1_HCI_8197F(x, v)                                          \
+	(BIT_CLEAR_TSFT1_HCI_8197F(x) | BIT_TSFT1_HCI_8197F(v))
+
+/* 2 REG_BD_RWPTR_CLR_8197F */
+#define BIT_CLR_HI7Q_HW_IDX_8197F BIT(29)
+#define BIT_CLR_HI6Q_HW_IDX_8197F BIT(28)
+#define BIT_CLR_HI5Q_HW_IDX_8197F BIT(27)
+#define BIT_CLR_HI4Q_HW_IDX_8197F BIT(26)
+#define BIT_CLR_HI3Q_HW_IDX_8197F BIT(25)
+#define BIT_CLR_HI2Q_HW_IDX_8197F BIT(24)
+#define BIT_CLR_HI1Q_HW_IDX_8197F BIT(23)
+#define BIT_CLR_HI0Q_HW_IDX_8197F BIT(22)
+#define BIT_CLR_BKQ_HW_IDX_8197F BIT(21)
+#define BIT_CLR_BEQ_HW_IDX_8197F BIT(20)
+#define BIT_CLR_VIQ_HW_IDX_8197F BIT(19)
+#define BIT_CLR_VOQ_HW_IDX_8197F BIT(18)
+#define BIT_CLR_MGQ_HW_IDX_8197F BIT(17)
+#define BIT_CLR_RXQ_HW_IDX_8197F BIT(16)
+#define BIT_CLR_HI7Q_HOST_IDX_8197F BIT(13)
+#define BIT_CLR_HI6Q_HOST_IDX_8197F BIT(12)
+#define BIT_CLR_HI5Q_HOST_IDX_8197F BIT(11)
+#define BIT_CLR_HI4Q_HOST_IDX_8197F BIT(10)
+#define BIT_CLR_HI3Q_HOST_IDX_8197F BIT(9)
+#define BIT_CLR_HI2Q_HOST_IDX_8197F BIT(8)
+#define BIT_CLR_HI1Q_HOST_IDX_8197F BIT(7)
+#define BIT_CLR_HI0Q_HOST_IDX_8197F BIT(6)
+#define BIT_CLR_BKQ_HOST_IDX_8197F BIT(5)
+#define BIT_CLR_BEQ_HOST_IDX_8197F BIT(4)
+#define BIT_CLR_VIQ_HOST_IDX_8197F BIT(3)
+#define BIT_CLR_VOQ_HOST_IDX_8197F BIT(2)
+#define BIT_CLR_MGQ_HOST_IDX_8197F BIT(1)
+#define BIT_CLR_RXQ_HOST_IDX_8197F BIT(0)
+
+/* 2 REG_VOQ_TXBD_IDX_8197F */
+
+#define BIT_SHIFT_VOQ_HW_IDX_8197F 16
+#define BIT_MASK_VOQ_HW_IDX_8197F 0xfff
+#define BIT_VOQ_HW_IDX_8197F(x)                                                \
+	(((x) & BIT_MASK_VOQ_HW_IDX_8197F) << BIT_SHIFT_VOQ_HW_IDX_8197F)
+#define BITS_VOQ_HW_IDX_8197F                                                  \
+	(BIT_MASK_VOQ_HW_IDX_8197F << BIT_SHIFT_VOQ_HW_IDX_8197F)
+#define BIT_CLEAR_VOQ_HW_IDX_8197F(x) ((x) & (~BITS_VOQ_HW_IDX_8197F))
+#define BIT_GET_VOQ_HW_IDX_8197F(x)                                            \
+	(((x) >> BIT_SHIFT_VOQ_HW_IDX_8197F) & BIT_MASK_VOQ_HW_IDX_8197F)
+#define BIT_SET_VOQ_HW_IDX_8197F(x, v)                                         \
+	(BIT_CLEAR_VOQ_HW_IDX_8197F(x) | BIT_VOQ_HW_IDX_8197F(v))
+
+#define BIT_SHIFT_VOQ_HOST_IDX_8197F 0
+#define BIT_MASK_VOQ_HOST_IDX_8197F 0xfff
+#define BIT_VOQ_HOST_IDX_8197F(x)                                              \
+	(((x) & BIT_MASK_VOQ_HOST_IDX_8197F) << BIT_SHIFT_VOQ_HOST_IDX_8197F)
+#define BITS_VOQ_HOST_IDX_8197F                                                \
+	(BIT_MASK_VOQ_HOST_IDX_8197F << BIT_SHIFT_VOQ_HOST_IDX_8197F)
+#define BIT_CLEAR_VOQ_HOST_IDX_8197F(x) ((x) & (~BITS_VOQ_HOST_IDX_8197F))
+#define BIT_GET_VOQ_HOST_IDX_8197F(x)                                          \
+	(((x) >> BIT_SHIFT_VOQ_HOST_IDX_8197F) & BIT_MASK_VOQ_HOST_IDX_8197F)
+#define BIT_SET_VOQ_HOST_IDX_8197F(x, v)                                       \
+	(BIT_CLEAR_VOQ_HOST_IDX_8197F(x) | BIT_VOQ_HOST_IDX_8197F(v))
+
+/* 2 REG_VIQ_TXBD_IDX_8197F */
+
+#define BIT_SHIFT_VIQ_HW_IDX_8197F 16
+#define BIT_MASK_VIQ_HW_IDX_8197F 0xfff
+#define BIT_VIQ_HW_IDX_8197F(x)                                                \
+	(((x) & BIT_MASK_VIQ_HW_IDX_8197F) << BIT_SHIFT_VIQ_HW_IDX_8197F)
+#define BITS_VIQ_HW_IDX_8197F                                                  \
+	(BIT_MASK_VIQ_HW_IDX_8197F << BIT_SHIFT_VIQ_HW_IDX_8197F)
+#define BIT_CLEAR_VIQ_HW_IDX_8197F(x) ((x) & (~BITS_VIQ_HW_IDX_8197F))
+#define BIT_GET_VIQ_HW_IDX_8197F(x)                                            \
+	(((x) >> BIT_SHIFT_VIQ_HW_IDX_8197F) & BIT_MASK_VIQ_HW_IDX_8197F)
+#define BIT_SET_VIQ_HW_IDX_8197F(x, v)                                         \
+	(BIT_CLEAR_VIQ_HW_IDX_8197F(x) | BIT_VIQ_HW_IDX_8197F(v))
+
+#define BIT_SHIFT_VIQ_HOST_IDX_8197F 0
+#define BIT_MASK_VIQ_HOST_IDX_8197F 0xfff
+#define BIT_VIQ_HOST_IDX_8197F(x)                                              \
+	(((x) & BIT_MASK_VIQ_HOST_IDX_8197F) << BIT_SHIFT_VIQ_HOST_IDX_8197F)
+#define BITS_VIQ_HOST_IDX_8197F                                                \
+	(BIT_MASK_VIQ_HOST_IDX_8197F << BIT_SHIFT_VIQ_HOST_IDX_8197F)
+#define BIT_CLEAR_VIQ_HOST_IDX_8197F(x) ((x) & (~BITS_VIQ_HOST_IDX_8197F))
+#define BIT_GET_VIQ_HOST_IDX_8197F(x)                                          \
+	(((x) >> BIT_SHIFT_VIQ_HOST_IDX_8197F) & BIT_MASK_VIQ_HOST_IDX_8197F)
+#define BIT_SET_VIQ_HOST_IDX_8197F(x, v)                                       \
+	(BIT_CLEAR_VIQ_HOST_IDX_8197F(x) | BIT_VIQ_HOST_IDX_8197F(v))
+
+/* 2 REG_BEQ_TXBD_IDX_8197F */
+
+#define BIT_SHIFT_BEQ_HW_IDX_8197F 16
+#define BIT_MASK_BEQ_HW_IDX_8197F 0xfff
+#define BIT_BEQ_HW_IDX_8197F(x)                                                \
+	(((x) & BIT_MASK_BEQ_HW_IDX_8197F) << BIT_SHIFT_BEQ_HW_IDX_8197F)
+#define BITS_BEQ_HW_IDX_8197F                                                  \
+	(BIT_MASK_BEQ_HW_IDX_8197F << BIT_SHIFT_BEQ_HW_IDX_8197F)
+#define BIT_CLEAR_BEQ_HW_IDX_8197F(x) ((x) & (~BITS_BEQ_HW_IDX_8197F))
+#define BIT_GET_BEQ_HW_IDX_8197F(x)                                            \
+	(((x) >> BIT_SHIFT_BEQ_HW_IDX_8197F) & BIT_MASK_BEQ_HW_IDX_8197F)
+#define BIT_SET_BEQ_HW_IDX_8197F(x, v)                                         \
+	(BIT_CLEAR_BEQ_HW_IDX_8197F(x) | BIT_BEQ_HW_IDX_8197F(v))
+
+#define BIT_SHIFT_BEQ_HOST_IDX_8197F 0
+#define BIT_MASK_BEQ_HOST_IDX_8197F 0xfff
+#define BIT_BEQ_HOST_IDX_8197F(x)                                              \
+	(((x) & BIT_MASK_BEQ_HOST_IDX_8197F) << BIT_SHIFT_BEQ_HOST_IDX_8197F)
+#define BITS_BEQ_HOST_IDX_8197F                                                \
+	(BIT_MASK_BEQ_HOST_IDX_8197F << BIT_SHIFT_BEQ_HOST_IDX_8197F)
+#define BIT_CLEAR_BEQ_HOST_IDX_8197F(x) ((x) & (~BITS_BEQ_HOST_IDX_8197F))
+#define BIT_GET_BEQ_HOST_IDX_8197F(x)                                          \
+	(((x) >> BIT_SHIFT_BEQ_HOST_IDX_8197F) & BIT_MASK_BEQ_HOST_IDX_8197F)
+#define BIT_SET_BEQ_HOST_IDX_8197F(x, v)                                       \
+	(BIT_CLEAR_BEQ_HOST_IDX_8197F(x) | BIT_BEQ_HOST_IDX_8197F(v))
+
+/* 2 REG_BKQ_TXBD_IDX_8197F */
+
+#define BIT_SHIFT_BKQ_HW_IDX_8197F 16
+#define BIT_MASK_BKQ_HW_IDX_8197F 0xfff
+#define BIT_BKQ_HW_IDX_8197F(x)                                                \
+	(((x) & BIT_MASK_BKQ_HW_IDX_8197F) << BIT_SHIFT_BKQ_HW_IDX_8197F)
+#define BITS_BKQ_HW_IDX_8197F                                                  \
+	(BIT_MASK_BKQ_HW_IDX_8197F << BIT_SHIFT_BKQ_HW_IDX_8197F)
+#define BIT_CLEAR_BKQ_HW_IDX_8197F(x) ((x) & (~BITS_BKQ_HW_IDX_8197F))
+#define BIT_GET_BKQ_HW_IDX_8197F(x)                                            \
+	(((x) >> BIT_SHIFT_BKQ_HW_IDX_8197F) & BIT_MASK_BKQ_HW_IDX_8197F)
+#define BIT_SET_BKQ_HW_IDX_8197F(x, v)                                         \
+	(BIT_CLEAR_BKQ_HW_IDX_8197F(x) | BIT_BKQ_HW_IDX_8197F(v))
+
+#define BIT_SHIFT_BKQ_HOST_IDX_8197F 0
+#define BIT_MASK_BKQ_HOST_IDX_8197F 0xfff
+#define BIT_BKQ_HOST_IDX_8197F(x)                                              \
+	(((x) & BIT_MASK_BKQ_HOST_IDX_8197F) << BIT_SHIFT_BKQ_HOST_IDX_8197F)
+#define BITS_BKQ_HOST_IDX_8197F                                                \
+	(BIT_MASK_BKQ_HOST_IDX_8197F << BIT_SHIFT_BKQ_HOST_IDX_8197F)
+#define BIT_CLEAR_BKQ_HOST_IDX_8197F(x) ((x) & (~BITS_BKQ_HOST_IDX_8197F))
+#define BIT_GET_BKQ_HOST_IDX_8197F(x)                                          \
+	(((x) >> BIT_SHIFT_BKQ_HOST_IDX_8197F) & BIT_MASK_BKQ_HOST_IDX_8197F)
+#define BIT_SET_BKQ_HOST_IDX_8197F(x, v)                                       \
+	(BIT_CLEAR_BKQ_HOST_IDX_8197F(x) | BIT_BKQ_HOST_IDX_8197F(v))
+
+/* 2 REG_MGQ_TXBD_IDX_8197F */
+
+#define BIT_SHIFT_MGQ_HW_IDX_8197F 16
+#define BIT_MASK_MGQ_HW_IDX_8197F 0xfff
+#define BIT_MGQ_HW_IDX_8197F(x)                                                \
+	(((x) & BIT_MASK_MGQ_HW_IDX_8197F) << BIT_SHIFT_MGQ_HW_IDX_8197F)
+#define BITS_MGQ_HW_IDX_8197F                                                  \
+	(BIT_MASK_MGQ_HW_IDX_8197F << BIT_SHIFT_MGQ_HW_IDX_8197F)
+#define BIT_CLEAR_MGQ_HW_IDX_8197F(x) ((x) & (~BITS_MGQ_HW_IDX_8197F))
+#define BIT_GET_MGQ_HW_IDX_8197F(x)                                            \
+	(((x) >> BIT_SHIFT_MGQ_HW_IDX_8197F) & BIT_MASK_MGQ_HW_IDX_8197F)
+#define BIT_SET_MGQ_HW_IDX_8197F(x, v)                                         \
+	(BIT_CLEAR_MGQ_HW_IDX_8197F(x) | BIT_MGQ_HW_IDX_8197F(v))
+
+#define BIT_SHIFT_MGQ_HOST_IDX_8197F 0
+#define BIT_MASK_MGQ_HOST_IDX_8197F 0xfff
+#define BIT_MGQ_HOST_IDX_8197F(x)                                              \
+	(((x) & BIT_MASK_MGQ_HOST_IDX_8197F) << BIT_SHIFT_MGQ_HOST_IDX_8197F)
+#define BITS_MGQ_HOST_IDX_8197F                                                \
+	(BIT_MASK_MGQ_HOST_IDX_8197F << BIT_SHIFT_MGQ_HOST_IDX_8197F)
+#define BIT_CLEAR_MGQ_HOST_IDX_8197F(x) ((x) & (~BITS_MGQ_HOST_IDX_8197F))
+#define BIT_GET_MGQ_HOST_IDX_8197F(x)                                          \
+	(((x) >> BIT_SHIFT_MGQ_HOST_IDX_8197F) & BIT_MASK_MGQ_HOST_IDX_8197F)
+#define BIT_SET_MGQ_HOST_IDX_8197F(x, v)                                       \
+	(BIT_CLEAR_MGQ_HOST_IDX_8197F(x) | BIT_MGQ_HOST_IDX_8197F(v))
+
+/* 2 REG_RXQ_RXBD_IDX_8197F */
+
+#define BIT_SHIFT_RXQ_HW_IDX_8197F 16
+#define BIT_MASK_RXQ_HW_IDX_8197F 0xfff
+#define BIT_RXQ_HW_IDX_8197F(x)                                                \
+	(((x) & BIT_MASK_RXQ_HW_IDX_8197F) << BIT_SHIFT_RXQ_HW_IDX_8197F)
+#define BITS_RXQ_HW_IDX_8197F                                                  \
+	(BIT_MASK_RXQ_HW_IDX_8197F << BIT_SHIFT_RXQ_HW_IDX_8197F)
+#define BIT_CLEAR_RXQ_HW_IDX_8197F(x) ((x) & (~BITS_RXQ_HW_IDX_8197F))
+#define BIT_GET_RXQ_HW_IDX_8197F(x)                                            \
+	(((x) >> BIT_SHIFT_RXQ_HW_IDX_8197F) & BIT_MASK_RXQ_HW_IDX_8197F)
+#define BIT_SET_RXQ_HW_IDX_8197F(x, v)                                         \
+	(BIT_CLEAR_RXQ_HW_IDX_8197F(x) | BIT_RXQ_HW_IDX_8197F(v))
+
+#define BIT_SHIFT_RXQ_HOST_IDX_8197F 0
+#define BIT_MASK_RXQ_HOST_IDX_8197F 0xfff
+#define BIT_RXQ_HOST_IDX_8197F(x)                                              \
+	(((x) & BIT_MASK_RXQ_HOST_IDX_8197F) << BIT_SHIFT_RXQ_HOST_IDX_8197F)
+#define BITS_RXQ_HOST_IDX_8197F                                                \
+	(BIT_MASK_RXQ_HOST_IDX_8197F << BIT_SHIFT_RXQ_HOST_IDX_8197F)
+#define BIT_CLEAR_RXQ_HOST_IDX_8197F(x) ((x) & (~BITS_RXQ_HOST_IDX_8197F))
+#define BIT_GET_RXQ_HOST_IDX_8197F(x)                                          \
+	(((x) >> BIT_SHIFT_RXQ_HOST_IDX_8197F) & BIT_MASK_RXQ_HOST_IDX_8197F)
+#define BIT_SET_RXQ_HOST_IDX_8197F(x, v)                                       \
+	(BIT_CLEAR_RXQ_HOST_IDX_8197F(x) | BIT_RXQ_HOST_IDX_8197F(v))
+
+/* 2 REG_HI0Q_TXBD_IDX_8197F */
+
+#define BIT_SHIFT_HI0Q_HW_IDX_8197F 16
+#define BIT_MASK_HI0Q_HW_IDX_8197F 0xfff
+#define BIT_HI0Q_HW_IDX_8197F(x)                                               \
+	(((x) & BIT_MASK_HI0Q_HW_IDX_8197F) << BIT_SHIFT_HI0Q_HW_IDX_8197F)
+#define BITS_HI0Q_HW_IDX_8197F                                                 \
+	(BIT_MASK_HI0Q_HW_IDX_8197F << BIT_SHIFT_HI0Q_HW_IDX_8197F)
+#define BIT_CLEAR_HI0Q_HW_IDX_8197F(x) ((x) & (~BITS_HI0Q_HW_IDX_8197F))
+#define BIT_GET_HI0Q_HW_IDX_8197F(x)                                           \
+	(((x) >> BIT_SHIFT_HI0Q_HW_IDX_8197F) & BIT_MASK_HI0Q_HW_IDX_8197F)
+#define BIT_SET_HI0Q_HW_IDX_8197F(x, v)                                        \
+	(BIT_CLEAR_HI0Q_HW_IDX_8197F(x) | BIT_HI0Q_HW_IDX_8197F(v))
+
+#define BIT_SHIFT_HI0Q_HOST_IDX_8197F 0
+#define BIT_MASK_HI0Q_HOST_IDX_8197F 0xfff
+#define BIT_HI0Q_HOST_IDX_8197F(x)                                             \
+	(((x) & BIT_MASK_HI0Q_HOST_IDX_8197F) << BIT_SHIFT_HI0Q_HOST_IDX_8197F)
+#define BITS_HI0Q_HOST_IDX_8197F                                               \
+	(BIT_MASK_HI0Q_HOST_IDX_8197F << BIT_SHIFT_HI0Q_HOST_IDX_8197F)
+#define BIT_CLEAR_HI0Q_HOST_IDX_8197F(x) ((x) & (~BITS_HI0Q_HOST_IDX_8197F))
+#define BIT_GET_HI0Q_HOST_IDX_8197F(x)                                         \
+	(((x) >> BIT_SHIFT_HI0Q_HOST_IDX_8197F) & BIT_MASK_HI0Q_HOST_IDX_8197F)
+#define BIT_SET_HI0Q_HOST_IDX_8197F(x, v)                                      \
+	(BIT_CLEAR_HI0Q_HOST_IDX_8197F(x) | BIT_HI0Q_HOST_IDX_8197F(v))
+
+/* 2 REG_HI1Q_TXBD_IDX_8197F */
+
+#define BIT_SHIFT_HI1Q_HW_IDX_8197F 16
+#define BIT_MASK_HI1Q_HW_IDX_8197F 0xfff
+#define BIT_HI1Q_HW_IDX_8197F(x)                                               \
+	(((x) & BIT_MASK_HI1Q_HW_IDX_8197F) << BIT_SHIFT_HI1Q_HW_IDX_8197F)
+#define BITS_HI1Q_HW_IDX_8197F                                                 \
+	(BIT_MASK_HI1Q_HW_IDX_8197F << BIT_SHIFT_HI1Q_HW_IDX_8197F)
+#define BIT_CLEAR_HI1Q_HW_IDX_8197F(x) ((x) & (~BITS_HI1Q_HW_IDX_8197F))
+#define BIT_GET_HI1Q_HW_IDX_8197F(x)                                           \
+	(((x) >> BIT_SHIFT_HI1Q_HW_IDX_8197F) & BIT_MASK_HI1Q_HW_IDX_8197F)
+#define BIT_SET_HI1Q_HW_IDX_8197F(x, v)                                        \
+	(BIT_CLEAR_HI1Q_HW_IDX_8197F(x) | BIT_HI1Q_HW_IDX_8197F(v))
+
+#define BIT_SHIFT_HI1Q_HOST_IDX_8197F 0
+#define BIT_MASK_HI1Q_HOST_IDX_8197F 0xfff
+#define BIT_HI1Q_HOST_IDX_8197F(x)                                             \
+	(((x) & BIT_MASK_HI1Q_HOST_IDX_8197F) << BIT_SHIFT_HI1Q_HOST_IDX_8197F)
+#define BITS_HI1Q_HOST_IDX_8197F                                               \
+	(BIT_MASK_HI1Q_HOST_IDX_8197F << BIT_SHIFT_HI1Q_HOST_IDX_8197F)
+#define BIT_CLEAR_HI1Q_HOST_IDX_8197F(x) ((x) & (~BITS_HI1Q_HOST_IDX_8197F))
+#define BIT_GET_HI1Q_HOST_IDX_8197F(x)                                         \
+	(((x) >> BIT_SHIFT_HI1Q_HOST_IDX_8197F) & BIT_MASK_HI1Q_HOST_IDX_8197F)
+#define BIT_SET_HI1Q_HOST_IDX_8197F(x, v)                                      \
+	(BIT_CLEAR_HI1Q_HOST_IDX_8197F(x) | BIT_HI1Q_HOST_IDX_8197F(v))
+
+/* 2 REG_HI2Q_TXBD_IDX_8197F */
+
+#define BIT_SHIFT_HI2Q_HW_IDX_8197F 16
+#define BIT_MASK_HI2Q_HW_IDX_8197F 0xfff
+#define BIT_HI2Q_HW_IDX_8197F(x)                                               \
+	(((x) & BIT_MASK_HI2Q_HW_IDX_8197F) << BIT_SHIFT_HI2Q_HW_IDX_8197F)
+#define BITS_HI2Q_HW_IDX_8197F                                                 \
+	(BIT_MASK_HI2Q_HW_IDX_8197F << BIT_SHIFT_HI2Q_HW_IDX_8197F)
+#define BIT_CLEAR_HI2Q_HW_IDX_8197F(x) ((x) & (~BITS_HI2Q_HW_IDX_8197F))
+#define BIT_GET_HI2Q_HW_IDX_8197F(x)                                           \
+	(((x) >> BIT_SHIFT_HI2Q_HW_IDX_8197F) & BIT_MASK_HI2Q_HW_IDX_8197F)
+#define BIT_SET_HI2Q_HW_IDX_8197F(x, v)                                        \
+	(BIT_CLEAR_HI2Q_HW_IDX_8197F(x) | BIT_HI2Q_HW_IDX_8197F(v))
+
+#define BIT_SHIFT_HI2Q_HOST_IDX_8197F 0
+#define BIT_MASK_HI2Q_HOST_IDX_8197F 0xfff
+#define BIT_HI2Q_HOST_IDX_8197F(x)                                             \
+	(((x) & BIT_MASK_HI2Q_HOST_IDX_8197F) << BIT_SHIFT_HI2Q_HOST_IDX_8197F)
+#define BITS_HI2Q_HOST_IDX_8197F                                               \
+	(BIT_MASK_HI2Q_HOST_IDX_8197F << BIT_SHIFT_HI2Q_HOST_IDX_8197F)
+#define BIT_CLEAR_HI2Q_HOST_IDX_8197F(x) ((x) & (~BITS_HI2Q_HOST_IDX_8197F))
+#define BIT_GET_HI2Q_HOST_IDX_8197F(x)                                         \
+	(((x) >> BIT_SHIFT_HI2Q_HOST_IDX_8197F) & BIT_MASK_HI2Q_HOST_IDX_8197F)
+#define BIT_SET_HI2Q_HOST_IDX_8197F(x, v)                                      \
+	(BIT_CLEAR_HI2Q_HOST_IDX_8197F(x) | BIT_HI2Q_HOST_IDX_8197F(v))
+
+/* 2 REG_HI3Q_TXBD_IDX_8197F */
+
+#define BIT_SHIFT_HI3Q_HW_IDX_8197F 16
+#define BIT_MASK_HI3Q_HW_IDX_8197F 0xfff
+#define BIT_HI3Q_HW_IDX_8197F(x)                                               \
+	(((x) & BIT_MASK_HI3Q_HW_IDX_8197F) << BIT_SHIFT_HI3Q_HW_IDX_8197F)
+#define BITS_HI3Q_HW_IDX_8197F                                                 \
+	(BIT_MASK_HI3Q_HW_IDX_8197F << BIT_SHIFT_HI3Q_HW_IDX_8197F)
+#define BIT_CLEAR_HI3Q_HW_IDX_8197F(x) ((x) & (~BITS_HI3Q_HW_IDX_8197F))
+#define BIT_GET_HI3Q_HW_IDX_8197F(x)                                           \
+	(((x) >> BIT_SHIFT_HI3Q_HW_IDX_8197F) & BIT_MASK_HI3Q_HW_IDX_8197F)
+#define BIT_SET_HI3Q_HW_IDX_8197F(x, v)                                        \
+	(BIT_CLEAR_HI3Q_HW_IDX_8197F(x) | BIT_HI3Q_HW_IDX_8197F(v))
+
+#define BIT_SHIFT_HI3Q_HOST_IDX_8197F 0
+#define BIT_MASK_HI3Q_HOST_IDX_8197F 0xfff
+#define BIT_HI3Q_HOST_IDX_8197F(x)                                             \
+	(((x) & BIT_MASK_HI3Q_HOST_IDX_8197F) << BIT_SHIFT_HI3Q_HOST_IDX_8197F)
+#define BITS_HI3Q_HOST_IDX_8197F                                               \
+	(BIT_MASK_HI3Q_HOST_IDX_8197F << BIT_SHIFT_HI3Q_HOST_IDX_8197F)
+#define BIT_CLEAR_HI3Q_HOST_IDX_8197F(x) ((x) & (~BITS_HI3Q_HOST_IDX_8197F))
+#define BIT_GET_HI3Q_HOST_IDX_8197F(x)                                         \
+	(((x) >> BIT_SHIFT_HI3Q_HOST_IDX_8197F) & BIT_MASK_HI3Q_HOST_IDX_8197F)
+#define BIT_SET_HI3Q_HOST_IDX_8197F(x, v)                                      \
+	(BIT_CLEAR_HI3Q_HOST_IDX_8197F(x) | BIT_HI3Q_HOST_IDX_8197F(v))
+
+/* 2 REG_HI4Q_TXBD_IDX_8197F */
+
+#define BIT_SHIFT_HI4Q_HW_IDX_8197F 16
+#define BIT_MASK_HI4Q_HW_IDX_8197F 0xfff
+#define BIT_HI4Q_HW_IDX_8197F(x)                                               \
+	(((x) & BIT_MASK_HI4Q_HW_IDX_8197F) << BIT_SHIFT_HI4Q_HW_IDX_8197F)
+#define BITS_HI4Q_HW_IDX_8197F                                                 \
+	(BIT_MASK_HI4Q_HW_IDX_8197F << BIT_SHIFT_HI4Q_HW_IDX_8197F)
+#define BIT_CLEAR_HI4Q_HW_IDX_8197F(x) ((x) & (~BITS_HI4Q_HW_IDX_8197F))
+#define BIT_GET_HI4Q_HW_IDX_8197F(x)                                           \
+	(((x) >> BIT_SHIFT_HI4Q_HW_IDX_8197F) & BIT_MASK_HI4Q_HW_IDX_8197F)
+#define BIT_SET_HI4Q_HW_IDX_8197F(x, v)                                        \
+	(BIT_CLEAR_HI4Q_HW_IDX_8197F(x) | BIT_HI4Q_HW_IDX_8197F(v))
+
+#define BIT_SHIFT_HI4Q_HOST_IDX_8197F 0
+#define BIT_MASK_HI4Q_HOST_IDX_8197F 0xfff
+#define BIT_HI4Q_HOST_IDX_8197F(x)                                             \
+	(((x) & BIT_MASK_HI4Q_HOST_IDX_8197F) << BIT_SHIFT_HI4Q_HOST_IDX_8197F)
+#define BITS_HI4Q_HOST_IDX_8197F                                               \
+	(BIT_MASK_HI4Q_HOST_IDX_8197F << BIT_SHIFT_HI4Q_HOST_IDX_8197F)
+#define BIT_CLEAR_HI4Q_HOST_IDX_8197F(x) ((x) & (~BITS_HI4Q_HOST_IDX_8197F))
+#define BIT_GET_HI4Q_HOST_IDX_8197F(x)                                         \
+	(((x) >> BIT_SHIFT_HI4Q_HOST_IDX_8197F) & BIT_MASK_HI4Q_HOST_IDX_8197F)
+#define BIT_SET_HI4Q_HOST_IDX_8197F(x, v)                                      \
+	(BIT_CLEAR_HI4Q_HOST_IDX_8197F(x) | BIT_HI4Q_HOST_IDX_8197F(v))
+
+/* 2 REG_HI5Q_TXBD_IDX_8197F */
+
+#define BIT_SHIFT_HI5Q_HW_IDX_8197F 16
+#define BIT_MASK_HI5Q_HW_IDX_8197F 0xfff
+#define BIT_HI5Q_HW_IDX_8197F(x)                                               \
+	(((x) & BIT_MASK_HI5Q_HW_IDX_8197F) << BIT_SHIFT_HI5Q_HW_IDX_8197F)
+#define BITS_HI5Q_HW_IDX_8197F                                                 \
+	(BIT_MASK_HI5Q_HW_IDX_8197F << BIT_SHIFT_HI5Q_HW_IDX_8197F)
+#define BIT_CLEAR_HI5Q_HW_IDX_8197F(x) ((x) & (~BITS_HI5Q_HW_IDX_8197F))
+#define BIT_GET_HI5Q_HW_IDX_8197F(x)                                           \
+	(((x) >> BIT_SHIFT_HI5Q_HW_IDX_8197F) & BIT_MASK_HI5Q_HW_IDX_8197F)
+#define BIT_SET_HI5Q_HW_IDX_8197F(x, v)                                        \
+	(BIT_CLEAR_HI5Q_HW_IDX_8197F(x) | BIT_HI5Q_HW_IDX_8197F(v))
+
+#define BIT_SHIFT_HI5Q_HOST_IDX_8197F 0
+#define BIT_MASK_HI5Q_HOST_IDX_8197F 0xfff
+#define BIT_HI5Q_HOST_IDX_8197F(x)                                             \
+	(((x) & BIT_MASK_HI5Q_HOST_IDX_8197F) << BIT_SHIFT_HI5Q_HOST_IDX_8197F)
+#define BITS_HI5Q_HOST_IDX_8197F                                               \
+	(BIT_MASK_HI5Q_HOST_IDX_8197F << BIT_SHIFT_HI5Q_HOST_IDX_8197F)
+#define BIT_CLEAR_HI5Q_HOST_IDX_8197F(x) ((x) & (~BITS_HI5Q_HOST_IDX_8197F))
+#define BIT_GET_HI5Q_HOST_IDX_8197F(x)                                         \
+	(((x) >> BIT_SHIFT_HI5Q_HOST_IDX_8197F) & BIT_MASK_HI5Q_HOST_IDX_8197F)
+#define BIT_SET_HI5Q_HOST_IDX_8197F(x, v)                                      \
+	(BIT_CLEAR_HI5Q_HOST_IDX_8197F(x) | BIT_HI5Q_HOST_IDX_8197F(v))
+
+/* 2 REG_HI6Q_TXBD_IDX_8197F */
+
+#define BIT_SHIFT_HI6Q_HW_IDX_8197F 16
+#define BIT_MASK_HI6Q_HW_IDX_8197F 0xfff
+#define BIT_HI6Q_HW_IDX_8197F(x)                                               \
+	(((x) & BIT_MASK_HI6Q_HW_IDX_8197F) << BIT_SHIFT_HI6Q_HW_IDX_8197F)
+#define BITS_HI6Q_HW_IDX_8197F                                                 \
+	(BIT_MASK_HI6Q_HW_IDX_8197F << BIT_SHIFT_HI6Q_HW_IDX_8197F)
+#define BIT_CLEAR_HI6Q_HW_IDX_8197F(x) ((x) & (~BITS_HI6Q_HW_IDX_8197F))
+#define BIT_GET_HI6Q_HW_IDX_8197F(x)                                           \
+	(((x) >> BIT_SHIFT_HI6Q_HW_IDX_8197F) & BIT_MASK_HI6Q_HW_IDX_8197F)
+#define BIT_SET_HI6Q_HW_IDX_8197F(x, v)                                        \
+	(BIT_CLEAR_HI6Q_HW_IDX_8197F(x) | BIT_HI6Q_HW_IDX_8197F(v))
+
+#define BIT_SHIFT_HI6Q_HOST_IDX_8197F 0
+#define BIT_MASK_HI6Q_HOST_IDX_8197F 0xfff
+#define BIT_HI6Q_HOST_IDX_8197F(x)                                             \
+	(((x) & BIT_MASK_HI6Q_HOST_IDX_8197F) << BIT_SHIFT_HI6Q_HOST_IDX_8197F)
+#define BITS_HI6Q_HOST_IDX_8197F                                               \
+	(BIT_MASK_HI6Q_HOST_IDX_8197F << BIT_SHIFT_HI6Q_HOST_IDX_8197F)
+#define BIT_CLEAR_HI6Q_HOST_IDX_8197F(x) ((x) & (~BITS_HI6Q_HOST_IDX_8197F))
+#define BIT_GET_HI6Q_HOST_IDX_8197F(x)                                         \
+	(((x) >> BIT_SHIFT_HI6Q_HOST_IDX_8197F) & BIT_MASK_HI6Q_HOST_IDX_8197F)
+#define BIT_SET_HI6Q_HOST_IDX_8197F(x, v)                                      \
+	(BIT_CLEAR_HI6Q_HOST_IDX_8197F(x) | BIT_HI6Q_HOST_IDX_8197F(v))
+
+/* 2 REG_HI7Q_TXBD_IDX_8197F */
+
+#define BIT_SHIFT_HI7Q_HW_IDX_8197F 16
+#define BIT_MASK_HI7Q_HW_IDX_8197F 0xfff
+#define BIT_HI7Q_HW_IDX_8197F(x)                                               \
+	(((x) & BIT_MASK_HI7Q_HW_IDX_8197F) << BIT_SHIFT_HI7Q_HW_IDX_8197F)
+#define BITS_HI7Q_HW_IDX_8197F                                                 \
+	(BIT_MASK_HI7Q_HW_IDX_8197F << BIT_SHIFT_HI7Q_HW_IDX_8197F)
+#define BIT_CLEAR_HI7Q_HW_IDX_8197F(x) ((x) & (~BITS_HI7Q_HW_IDX_8197F))
+#define BIT_GET_HI7Q_HW_IDX_8197F(x)                                           \
+	(((x) >> BIT_SHIFT_HI7Q_HW_IDX_8197F) & BIT_MASK_HI7Q_HW_IDX_8197F)
+#define BIT_SET_HI7Q_HW_IDX_8197F(x, v)                                        \
+	(BIT_CLEAR_HI7Q_HW_IDX_8197F(x) | BIT_HI7Q_HW_IDX_8197F(v))
+
+#define BIT_SHIFT_HI7Q_HOST_IDX_8197F 0
+#define BIT_MASK_HI7Q_HOST_IDX_8197F 0xfff
+#define BIT_HI7Q_HOST_IDX_8197F(x)                                             \
+	(((x) & BIT_MASK_HI7Q_HOST_IDX_8197F) << BIT_SHIFT_HI7Q_HOST_IDX_8197F)
+#define BITS_HI7Q_HOST_IDX_8197F                                               \
+	(BIT_MASK_HI7Q_HOST_IDX_8197F << BIT_SHIFT_HI7Q_HOST_IDX_8197F)
+#define BIT_CLEAR_HI7Q_HOST_IDX_8197F(x) ((x) & (~BITS_HI7Q_HOST_IDX_8197F))
+#define BIT_GET_HI7Q_HOST_IDX_8197F(x)                                         \
+	(((x) >> BIT_SHIFT_HI7Q_HOST_IDX_8197F) & BIT_MASK_HI7Q_HOST_IDX_8197F)
+#define BIT_SET_HI7Q_HOST_IDX_8197F(x, v)                                      \
+	(BIT_CLEAR_HI7Q_HOST_IDX_8197F(x) | BIT_HI7Q_HOST_IDX_8197F(v))
+
+/* 2 REG_DBG_SEL_V1_8197F */
+
+#define BIT_SHIFT_DBG_SEL_8197F 0
+#define BIT_MASK_DBG_SEL_8197F 0xff
+#define BIT_DBG_SEL_8197F(x)                                                   \
+	(((x) & BIT_MASK_DBG_SEL_8197F) << BIT_SHIFT_DBG_SEL_8197F)
+#define BITS_DBG_SEL_8197F (BIT_MASK_DBG_SEL_8197F << BIT_SHIFT_DBG_SEL_8197F)
+#define BIT_CLEAR_DBG_SEL_8197F(x) ((x) & (~BITS_DBG_SEL_8197F))
+#define BIT_GET_DBG_SEL_8197F(x)                                               \
+	(((x) >> BIT_SHIFT_DBG_SEL_8197F) & BIT_MASK_DBG_SEL_8197F)
+#define BIT_SET_DBG_SEL_8197F(x, v)                                            \
+	(BIT_CLEAR_DBG_SEL_8197F(x) | BIT_DBG_SEL_8197F(v))
+
+/* 2 REG_HCI_HRPWM1_V1_8197F */
+
+#define BIT_SHIFT_HCI_HRPWM_8197F 0
+#define BIT_MASK_HCI_HRPWM_8197F 0xff
+#define BIT_HCI_HRPWM_8197F(x)                                                 \
+	(((x) & BIT_MASK_HCI_HRPWM_8197F) << BIT_SHIFT_HCI_HRPWM_8197F)
+#define BITS_HCI_HRPWM_8197F                                                   \
+	(BIT_MASK_HCI_HRPWM_8197F << BIT_SHIFT_HCI_HRPWM_8197F)
+#define BIT_CLEAR_HCI_HRPWM_8197F(x) ((x) & (~BITS_HCI_HRPWM_8197F))
+#define BIT_GET_HCI_HRPWM_8197F(x)                                             \
+	(((x) >> BIT_SHIFT_HCI_HRPWM_8197F) & BIT_MASK_HCI_HRPWM_8197F)
+#define BIT_SET_HCI_HRPWM_8197F(x, v)                                          \
+	(BIT_CLEAR_HCI_HRPWM_8197F(x) | BIT_HCI_HRPWM_8197F(v))
+
+/* 2 REG_HCI_HCPWM1_V1_8197F */
+
+#define BIT_SHIFT_HCI_HCPWM_8197F 0
+#define BIT_MASK_HCI_HCPWM_8197F 0xff
+#define BIT_HCI_HCPWM_8197F(x)                                                 \
+	(((x) & BIT_MASK_HCI_HCPWM_8197F) << BIT_SHIFT_HCI_HCPWM_8197F)
+#define BITS_HCI_HCPWM_8197F                                                   \
+	(BIT_MASK_HCI_HCPWM_8197F << BIT_SHIFT_HCI_HCPWM_8197F)
+#define BIT_CLEAR_HCI_HCPWM_8197F(x) ((x) & (~BITS_HCI_HCPWM_8197F))
+#define BIT_GET_HCI_HCPWM_8197F(x)                                             \
+	(((x) >> BIT_SHIFT_HCI_HCPWM_8197F) & BIT_MASK_HCI_HCPWM_8197F)
+#define BIT_SET_HCI_HCPWM_8197F(x, v)                                          \
+	(BIT_CLEAR_HCI_HCPWM_8197F(x) | BIT_HCI_HCPWM_8197F(v))
+
+/* 2 REG_HCI_CTRL2_8197F */
+#define BIT_DIS_TXDMA_PRE_8197F BIT(7)
+#define BIT_DIS_RXDMA_PRE_8197F BIT(6)
+
+#define BIT_SHIFT_HPS_CLKR_HCI_8197F 4
+#define BIT_MASK_HPS_CLKR_HCI_8197F 0x3
+#define BIT_HPS_CLKR_HCI_8197F(x)                                              \
+	(((x) & BIT_MASK_HPS_CLKR_HCI_8197F) << BIT_SHIFT_HPS_CLKR_HCI_8197F)
+#define BITS_HPS_CLKR_HCI_8197F                                                \
+	(BIT_MASK_HPS_CLKR_HCI_8197F << BIT_SHIFT_HPS_CLKR_HCI_8197F)
+#define BIT_CLEAR_HPS_CLKR_HCI_8197F(x) ((x) & (~BITS_HPS_CLKR_HCI_8197F))
+#define BIT_GET_HPS_CLKR_HCI_8197F(x)                                          \
+	(((x) >> BIT_SHIFT_HPS_CLKR_HCI_8197F) & BIT_MASK_HPS_CLKR_HCI_8197F)
+#define BIT_SET_HPS_CLKR_HCI_8197F(x, v)                                       \
+	(BIT_CLEAR_HPS_CLKR_HCI_8197F(x) | BIT_HPS_CLKR_HCI_8197F(v))
+
+#define BIT_HCI_INT_8197F BIT(3)
+#define BIT_TXFLAG_EXIT_L1_EN_8197F BIT(2)
+#define BIT_EN_RXDMA_ALIGN_V1_8197F BIT(1)
+#define BIT_EN_TXDMA_ALIGN_V1_8197F BIT(0)
+
+/* 2 REG_HCI_HRPWM2_V1_8197F */
+
+#define BIT_SHIFT_HCI_HRPWM2_8197F 0
+#define BIT_MASK_HCI_HRPWM2_8197F 0xffff
+#define BIT_HCI_HRPWM2_8197F(x)                                                \
+	(((x) & BIT_MASK_HCI_HRPWM2_8197F) << BIT_SHIFT_HCI_HRPWM2_8197F)
+#define BITS_HCI_HRPWM2_8197F                                                  \
+	(BIT_MASK_HCI_HRPWM2_8197F << BIT_SHIFT_HCI_HRPWM2_8197F)
+#define BIT_CLEAR_HCI_HRPWM2_8197F(x) ((x) & (~BITS_HCI_HRPWM2_8197F))
+#define BIT_GET_HCI_HRPWM2_8197F(x)                                            \
+	(((x) >> BIT_SHIFT_HCI_HRPWM2_8197F) & BIT_MASK_HCI_HRPWM2_8197F)
+#define BIT_SET_HCI_HRPWM2_8197F(x, v)                                         \
+	(BIT_CLEAR_HCI_HRPWM2_8197F(x) | BIT_HCI_HRPWM2_8197F(v))
+
+/* 2 REG_HCI_HCPWM2_V1_8197F */
+
+#define BIT_SHIFT_HCI_HCPWM2_8197F 0
+#define BIT_MASK_HCI_HCPWM2_8197F 0xffff
+#define BIT_HCI_HCPWM2_8197F(x)                                                \
+	(((x) & BIT_MASK_HCI_HCPWM2_8197F) << BIT_SHIFT_HCI_HCPWM2_8197F)
+#define BITS_HCI_HCPWM2_8197F                                                  \
+	(BIT_MASK_HCI_HCPWM2_8197F << BIT_SHIFT_HCI_HCPWM2_8197F)
+#define BIT_CLEAR_HCI_HCPWM2_8197F(x) ((x) & (~BITS_HCI_HCPWM2_8197F))
+#define BIT_GET_HCI_HCPWM2_8197F(x)                                            \
+	(((x) >> BIT_SHIFT_HCI_HCPWM2_8197F) & BIT_MASK_HCI_HCPWM2_8197F)
+#define BIT_SET_HCI_HCPWM2_8197F(x, v)                                         \
+	(BIT_CLEAR_HCI_HCPWM2_8197F(x) | BIT_HCI_HCPWM2_8197F(v))
+
+/* 2 REG_HCI_H2C_MSG_V1_8197F */
+
+#define BIT_SHIFT_DRV2FW_INFO_8197F 0
+#define BIT_MASK_DRV2FW_INFO_8197F 0xffffffffL
+#define BIT_DRV2FW_INFO_8197F(x)                                               \
+	(((x) & BIT_MASK_DRV2FW_INFO_8197F) << BIT_SHIFT_DRV2FW_INFO_8197F)
+#define BITS_DRV2FW_INFO_8197F                                                 \
+	(BIT_MASK_DRV2FW_INFO_8197F << BIT_SHIFT_DRV2FW_INFO_8197F)
+#define BIT_CLEAR_DRV2FW_INFO_8197F(x) ((x) & (~BITS_DRV2FW_INFO_8197F))
+#define BIT_GET_DRV2FW_INFO_8197F(x)                                           \
+	(((x) >> BIT_SHIFT_DRV2FW_INFO_8197F) & BIT_MASK_DRV2FW_INFO_8197F)
+#define BIT_SET_DRV2FW_INFO_8197F(x, v)                                        \
+	(BIT_CLEAR_DRV2FW_INFO_8197F(x) | BIT_DRV2FW_INFO_8197F(v))
+
+/* 2 REG_HCI_C2H_MSG_V1_8197F */
+
+#define BIT_SHIFT_HCI_C2H_MSG_8197F 0
+#define BIT_MASK_HCI_C2H_MSG_8197F 0xffffffffL
+#define BIT_HCI_C2H_MSG_8197F(x)                                               \
+	(((x) & BIT_MASK_HCI_C2H_MSG_8197F) << BIT_SHIFT_HCI_C2H_MSG_8197F)
+#define BITS_HCI_C2H_MSG_8197F                                                 \
+	(BIT_MASK_HCI_C2H_MSG_8197F << BIT_SHIFT_HCI_C2H_MSG_8197F)
+#define BIT_CLEAR_HCI_C2H_MSG_8197F(x) ((x) & (~BITS_HCI_C2H_MSG_8197F))
+#define BIT_GET_HCI_C2H_MSG_8197F(x)                                           \
+	(((x) >> BIT_SHIFT_HCI_C2H_MSG_8197F) & BIT_MASK_HCI_C2H_MSG_8197F)
+#define BIT_SET_HCI_C2H_MSG_8197F(x, v)                                        \
+	(BIT_CLEAR_HCI_C2H_MSG_8197F(x) | BIT_HCI_C2H_MSG_8197F(v))
+
+/* 2 REG_DBI_WDATA_V1_8197F */
+
+#define BIT_SHIFT_DBI_WDATA_8197F 0
+#define BIT_MASK_DBI_WDATA_8197F 0xffffffffL
+#define BIT_DBI_WDATA_8197F(x)                                                 \
+	(((x) & BIT_MASK_DBI_WDATA_8197F) << BIT_SHIFT_DBI_WDATA_8197F)
+#define BITS_DBI_WDATA_8197F                                                   \
+	(BIT_MASK_DBI_WDATA_8197F << BIT_SHIFT_DBI_WDATA_8197F)
+#define BIT_CLEAR_DBI_WDATA_8197F(x) ((x) & (~BITS_DBI_WDATA_8197F))
+#define BIT_GET_DBI_WDATA_8197F(x)                                             \
+	(((x) >> BIT_SHIFT_DBI_WDATA_8197F) & BIT_MASK_DBI_WDATA_8197F)
+#define BIT_SET_DBI_WDATA_8197F(x, v)                                          \
+	(BIT_CLEAR_DBI_WDATA_8197F(x) | BIT_DBI_WDATA_8197F(v))
+
+/* 2 REG_DBI_RDATA_V1_8197F */
+
+#define BIT_SHIFT_DBI_RDATA_8197F 0
+#define BIT_MASK_DBI_RDATA_8197F 0xffffffffL
+#define BIT_DBI_RDATA_8197F(x)                                                 \
+	(((x) & BIT_MASK_DBI_RDATA_8197F) << BIT_SHIFT_DBI_RDATA_8197F)
+#define BITS_DBI_RDATA_8197F                                                   \
+	(BIT_MASK_DBI_RDATA_8197F << BIT_SHIFT_DBI_RDATA_8197F)
+#define BIT_CLEAR_DBI_RDATA_8197F(x) ((x) & (~BITS_DBI_RDATA_8197F))
+#define BIT_GET_DBI_RDATA_8197F(x)                                             \
+	(((x) >> BIT_SHIFT_DBI_RDATA_8197F) & BIT_MASK_DBI_RDATA_8197F)
+#define BIT_SET_DBI_RDATA_8197F(x, v)                                          \
+	(BIT_CLEAR_DBI_RDATA_8197F(x) | BIT_DBI_RDATA_8197F(v))
+
+/* 2 REG_STUCK_FLAG_V1_8197F */
+#define BIT_EN_STUCK_DBG_8197F BIT(26)
+#define BIT_RX_STUCK_8197F BIT(25)
+#define BIT_TX_STUCK_8197F BIT(24)
+#define BIT_DBI_RFLAG_8197F BIT(17)
+#define BIT_DBI_WFLAG_8197F BIT(16)
+
+#define BIT_SHIFT_DBI_WREN_8197F 12
+#define BIT_MASK_DBI_WREN_8197F 0xf
+#define BIT_DBI_WREN_8197F(x)                                                  \
+	(((x) & BIT_MASK_DBI_WREN_8197F) << BIT_SHIFT_DBI_WREN_8197F)
+#define BITS_DBI_WREN_8197F                                                    \
+	(BIT_MASK_DBI_WREN_8197F << BIT_SHIFT_DBI_WREN_8197F)
+#define BIT_CLEAR_DBI_WREN_8197F(x) ((x) & (~BITS_DBI_WREN_8197F))
+#define BIT_GET_DBI_WREN_8197F(x)                                              \
+	(((x) >> BIT_SHIFT_DBI_WREN_8197F) & BIT_MASK_DBI_WREN_8197F)
+#define BIT_SET_DBI_WREN_8197F(x, v)                                           \
+	(BIT_CLEAR_DBI_WREN_8197F(x) | BIT_DBI_WREN_8197F(v))
+
+#define BIT_SHIFT_DBI_ADDR_8197F 0
+#define BIT_MASK_DBI_ADDR_8197F 0xfff
+#define BIT_DBI_ADDR_8197F(x)                                                  \
+	(((x) & BIT_MASK_DBI_ADDR_8197F) << BIT_SHIFT_DBI_ADDR_8197F)
+#define BITS_DBI_ADDR_8197F                                                    \
+	(BIT_MASK_DBI_ADDR_8197F << BIT_SHIFT_DBI_ADDR_8197F)
+#define BIT_CLEAR_DBI_ADDR_8197F(x) ((x) & (~BITS_DBI_ADDR_8197F))
+#define BIT_GET_DBI_ADDR_8197F(x)                                              \
+	(((x) >> BIT_SHIFT_DBI_ADDR_8197F) & BIT_MASK_DBI_ADDR_8197F)
+#define BIT_SET_DBI_ADDR_8197F(x, v)                                           \
+	(BIT_CLEAR_DBI_ADDR_8197F(x) | BIT_DBI_ADDR_8197F(v))
+
+/* 2 REG_MDIO_V1_8197F */
+
+#define BIT_SHIFT_MDIO_RDATA_8197F 16
+#define BIT_MASK_MDIO_RDATA_8197F 0xffff
+#define BIT_MDIO_RDATA_8197F(x)                                                \
+	(((x) & BIT_MASK_MDIO_RDATA_8197F) << BIT_SHIFT_MDIO_RDATA_8197F)
+#define BITS_MDIO_RDATA_8197F                                                  \
+	(BIT_MASK_MDIO_RDATA_8197F << BIT_SHIFT_MDIO_RDATA_8197F)
+#define BIT_CLEAR_MDIO_RDATA_8197F(x) ((x) & (~BITS_MDIO_RDATA_8197F))
+#define BIT_GET_MDIO_RDATA_8197F(x)                                            \
+	(((x) >> BIT_SHIFT_MDIO_RDATA_8197F) & BIT_MASK_MDIO_RDATA_8197F)
+#define BIT_SET_MDIO_RDATA_8197F(x, v)                                         \
+	(BIT_CLEAR_MDIO_RDATA_8197F(x) | BIT_MDIO_RDATA_8197F(v))
+
+#define BIT_SHIFT_MDIO_WDATA_8197F 0
+#define BIT_MASK_MDIO_WDATA_8197F 0xffff
+#define BIT_MDIO_WDATA_8197F(x)                                                \
+	(((x) & BIT_MASK_MDIO_WDATA_8197F) << BIT_SHIFT_MDIO_WDATA_8197F)
+#define BITS_MDIO_WDATA_8197F                                                  \
+	(BIT_MASK_MDIO_WDATA_8197F << BIT_SHIFT_MDIO_WDATA_8197F)
+#define BIT_CLEAR_MDIO_WDATA_8197F(x) ((x) & (~BITS_MDIO_WDATA_8197F))
+#define BIT_GET_MDIO_WDATA_8197F(x)                                            \
+	(((x) >> BIT_SHIFT_MDIO_WDATA_8197F) & BIT_MASK_MDIO_WDATA_8197F)
+#define BIT_SET_MDIO_WDATA_8197F(x, v)                                         \
+	(BIT_CLEAR_MDIO_WDATA_8197F(x) | BIT_MDIO_WDATA_8197F(v))
+
+/* 2 REG_WDT_CFG_8197F */
+
+#define BIT_SHIFT_MDIO_PHY_ADDR_8197F 24
+#define BIT_MASK_MDIO_PHY_ADDR_8197F 0x1f
+#define BIT_MDIO_PHY_ADDR_8197F(x)                                             \
+	(((x) & BIT_MASK_MDIO_PHY_ADDR_8197F) << BIT_SHIFT_MDIO_PHY_ADDR_8197F)
+#define BITS_MDIO_PHY_ADDR_8197F                                               \
+	(BIT_MASK_MDIO_PHY_ADDR_8197F << BIT_SHIFT_MDIO_PHY_ADDR_8197F)
+#define BIT_CLEAR_MDIO_PHY_ADDR_8197F(x) ((x) & (~BITS_MDIO_PHY_ADDR_8197F))
+#define BIT_GET_MDIO_PHY_ADDR_8197F(x)                                         \
+	(((x) >> BIT_SHIFT_MDIO_PHY_ADDR_8197F) & BIT_MASK_MDIO_PHY_ADDR_8197F)
+#define BIT_SET_MDIO_PHY_ADDR_8197F(x, v)                                      \
+	(BIT_CLEAR_MDIO_PHY_ADDR_8197F(x) | BIT_MDIO_PHY_ADDR_8197F(v))
+
+#define BIT_SHIFT_WATCH_DOG_RECORD_V1_8197F 10
+#define BIT_MASK_WATCH_DOG_RECORD_V1_8197F 0x3fff
+#define BIT_WATCH_DOG_RECORD_V1_8197F(x)                                       \
+	(((x) & BIT_MASK_WATCH_DOG_RECORD_V1_8197F)                            \
+	 << BIT_SHIFT_WATCH_DOG_RECORD_V1_8197F)
+#define BITS_WATCH_DOG_RECORD_V1_8197F                                         \
+	(BIT_MASK_WATCH_DOG_RECORD_V1_8197F                                    \
+	 << BIT_SHIFT_WATCH_DOG_RECORD_V1_8197F)
+#define BIT_CLEAR_WATCH_DOG_RECORD_V1_8197F(x)                                 \
+	((x) & (~BITS_WATCH_DOG_RECORD_V1_8197F))
+#define BIT_GET_WATCH_DOG_RECORD_V1_8197F(x)                                   \
+	(((x) >> BIT_SHIFT_WATCH_DOG_RECORD_V1_8197F) &                        \
+	 BIT_MASK_WATCH_DOG_RECORD_V1_8197F)
+#define BIT_SET_WATCH_DOG_RECORD_V1_8197F(x, v)                                \
+	(BIT_CLEAR_WATCH_DOG_RECORD_V1_8197F(x) |                              \
+	 BIT_WATCH_DOG_RECORD_V1_8197F(v))
+
+#define BIT_R_IO_TIMEOUT_FLAG_V1_8197F BIT(9)
+#define BIT_EN_WATCH_DOG_V1_8197F BIT(8)
+#define BIT_ECRC_EN_V1_8197F BIT(7)
+#define BIT_MDIO_RFLAG_V1_8197F BIT(6)
+#define BIT_MDIO_WFLAG_V1_8197F BIT(5)
+
+#define BIT_SHIFT_MDIO_REG_ADDR_8197F 0
+#define BIT_MASK_MDIO_REG_ADDR_8197F 0x1f
+#define BIT_MDIO_REG_ADDR_8197F(x)                                             \
+	(((x) & BIT_MASK_MDIO_REG_ADDR_8197F) << BIT_SHIFT_MDIO_REG_ADDR_8197F)
+#define BITS_MDIO_REG_ADDR_8197F                                               \
+	(BIT_MASK_MDIO_REG_ADDR_8197F << BIT_SHIFT_MDIO_REG_ADDR_8197F)
+#define BIT_CLEAR_MDIO_REG_ADDR_8197F(x) ((x) & (~BITS_MDIO_REG_ADDR_8197F))
+#define BIT_GET_MDIO_REG_ADDR_8197F(x)                                         \
+	(((x) >> BIT_SHIFT_MDIO_REG_ADDR_8197F) & BIT_MASK_MDIO_REG_ADDR_8197F)
+#define BIT_SET_MDIO_REG_ADDR_8197F(x, v)                                      \
+	(BIT_CLEAR_MDIO_REG_ADDR_8197F(x) | BIT_MDIO_REG_ADDR_8197F(v))
+
+/* 2 REG_HCI_MIX_CFG_8197F */
+#define BIT_RXRST_BACKDOOR_8197F BIT(31)
+#define BIT_TXRST_BACKDOOR_8197F BIT(30)
+#define BIT_RXIDX_RSTB_8197F BIT(29)
+#define BIT_TXIDX_RSTB_8197F BIT(28)
+#define BIT_DROP_NEXT_RXPKT_8197F BIT(27)
+#define BIT_SHORT_CORE_RST_SEL_8197F BIT(26)
+#define BIT_EXCEPT_RESUME_EN_8197F BIT(25)
+#define BIT_EXCEPT_RESUME_FLAG_8197F BIT(24)
+#define BIT_ALIGN_MTU_8197F BIT(23)
+#define BIT_HOST_GEN2_SUPPORT_8197F BIT(20)
+
+#define BIT_SHIFT_TXDMA_ERR_FLAG_8197F 16
+#define BIT_MASK_TXDMA_ERR_FLAG_8197F 0xf
+#define BIT_TXDMA_ERR_FLAG_8197F(x)                                            \
+	(((x) & BIT_MASK_TXDMA_ERR_FLAG_8197F)                                 \
+	 << BIT_SHIFT_TXDMA_ERR_FLAG_8197F)
+#define BITS_TXDMA_ERR_FLAG_8197F                                              \
+	(BIT_MASK_TXDMA_ERR_FLAG_8197F << BIT_SHIFT_TXDMA_ERR_FLAG_8197F)
+#define BIT_CLEAR_TXDMA_ERR_FLAG_8197F(x) ((x) & (~BITS_TXDMA_ERR_FLAG_8197F))
+#define BIT_GET_TXDMA_ERR_FLAG_8197F(x)                                        \
+	(((x) >> BIT_SHIFT_TXDMA_ERR_FLAG_8197F) &                             \
+	 BIT_MASK_TXDMA_ERR_FLAG_8197F)
+#define BIT_SET_TXDMA_ERR_FLAG_8197F(x, v)                                     \
+	(BIT_CLEAR_TXDMA_ERR_FLAG_8197F(x) | BIT_TXDMA_ERR_FLAG_8197F(v))
+
+#define BIT_SHIFT_EARLY_MODE_SEL_8197F 12
+#define BIT_MASK_EARLY_MODE_SEL_8197F 0xf
+#define BIT_EARLY_MODE_SEL_8197F(x)                                            \
+	(((x) & BIT_MASK_EARLY_MODE_SEL_8197F)                                 \
+	 << BIT_SHIFT_EARLY_MODE_SEL_8197F)
+#define BITS_EARLY_MODE_SEL_8197F                                              \
+	(BIT_MASK_EARLY_MODE_SEL_8197F << BIT_SHIFT_EARLY_MODE_SEL_8197F)
+#define BIT_CLEAR_EARLY_MODE_SEL_8197F(x) ((x) & (~BITS_EARLY_MODE_SEL_8197F))
+#define BIT_GET_EARLY_MODE_SEL_8197F(x)                                        \
+	(((x) >> BIT_SHIFT_EARLY_MODE_SEL_8197F) &                             \
+	 BIT_MASK_EARLY_MODE_SEL_8197F)
+#define BIT_SET_EARLY_MODE_SEL_8197F(x, v)                                     \
+	(BIT_CLEAR_EARLY_MODE_SEL_8197F(x) | BIT_EARLY_MODE_SEL_8197F(v))
+
+#define BIT_EPHY_RX50_EN_8197F BIT(11)
+
+#define BIT_SHIFT_MSI_TIMEOUT_ID_V1_8197F 8
+#define BIT_MASK_MSI_TIMEOUT_ID_V1_8197F 0x7
+#define BIT_MSI_TIMEOUT_ID_V1_8197F(x)                                         \
+	(((x) & BIT_MASK_MSI_TIMEOUT_ID_V1_8197F)                              \
+	 << BIT_SHIFT_MSI_TIMEOUT_ID_V1_8197F)
+#define BITS_MSI_TIMEOUT_ID_V1_8197F                                           \
+	(BIT_MASK_MSI_TIMEOUT_ID_V1_8197F << BIT_SHIFT_MSI_TIMEOUT_ID_V1_8197F)
+#define BIT_CLEAR_MSI_TIMEOUT_ID_V1_8197F(x)                                   \
+	((x) & (~BITS_MSI_TIMEOUT_ID_V1_8197F))
+#define BIT_GET_MSI_TIMEOUT_ID_V1_8197F(x)                                     \
+	(((x) >> BIT_SHIFT_MSI_TIMEOUT_ID_V1_8197F) &                          \
+	 BIT_MASK_MSI_TIMEOUT_ID_V1_8197F)
+#define BIT_SET_MSI_TIMEOUT_ID_V1_8197F(x, v)                                  \
+	(BIT_CLEAR_MSI_TIMEOUT_ID_V1_8197F(x) | BIT_MSI_TIMEOUT_ID_V1_8197F(v))
+
+#define BIT_RADDR_RD_8197F BIT(7)
+#define BIT_EN_MUL_TAG_8197F BIT(6)
+#define BIT_EN_EARLY_MODE_8197F BIT(5)
+#define BIT_L0S_LINK_OFF_8197F BIT(4)
+#define BIT_ACT_LINK_OFF_8197F BIT(3)
+
+/* 2 REG_STC_INT_CS_8197F(HCI STATE CHANGE INTERRUPT CONTROL AND STATUS) */
+#define BIT_STC_INT_EN_8197F BIT(31)
+
+#define BIT_SHIFT_STC_INT_FLAG_8197F 16
+#define BIT_MASK_STC_INT_FLAG_8197F 0xff
+#define BIT_STC_INT_FLAG_8197F(x)                                              \
+	(((x) & BIT_MASK_STC_INT_FLAG_8197F) << BIT_SHIFT_STC_INT_FLAG_8197F)
+#define BITS_STC_INT_FLAG_8197F                                                \
+	(BIT_MASK_STC_INT_FLAG_8197F << BIT_SHIFT_STC_INT_FLAG_8197F)
+#define BIT_CLEAR_STC_INT_FLAG_8197F(x) ((x) & (~BITS_STC_INT_FLAG_8197F))
+#define BIT_GET_STC_INT_FLAG_8197F(x)                                          \
+	(((x) >> BIT_SHIFT_STC_INT_FLAG_8197F) & BIT_MASK_STC_INT_FLAG_8197F)
+#define BIT_SET_STC_INT_FLAG_8197F(x, v)                                       \
+	(BIT_CLEAR_STC_INT_FLAG_8197F(x) | BIT_STC_INT_FLAG_8197F(v))
+
+#define BIT_SHIFT_STC_INT_IDX_8197F 8
+#define BIT_MASK_STC_INT_IDX_8197F 0x7
+#define BIT_STC_INT_IDX_8197F(x)                                               \
+	(((x) & BIT_MASK_STC_INT_IDX_8197F) << BIT_SHIFT_STC_INT_IDX_8197F)
+#define BITS_STC_INT_IDX_8197F                                                 \
+	(BIT_MASK_STC_INT_IDX_8197F << BIT_SHIFT_STC_INT_IDX_8197F)
+#define BIT_CLEAR_STC_INT_IDX_8197F(x) ((x) & (~BITS_STC_INT_IDX_8197F))
+#define BIT_GET_STC_INT_IDX_8197F(x)                                           \
+	(((x) >> BIT_SHIFT_STC_INT_IDX_8197F) & BIT_MASK_STC_INT_IDX_8197F)
+#define BIT_SET_STC_INT_IDX_8197F(x, v)                                        \
+	(BIT_CLEAR_STC_INT_IDX_8197F(x) | BIT_STC_INT_IDX_8197F(v))
+
+#define BIT_SHIFT_STC_INT_REALTIME_CS_8197F 0
+#define BIT_MASK_STC_INT_REALTIME_CS_8197F 0x3f
+#define BIT_STC_INT_REALTIME_CS_8197F(x)                                       \
+	(((x) & BIT_MASK_STC_INT_REALTIME_CS_8197F)                            \
+	 << BIT_SHIFT_STC_INT_REALTIME_CS_8197F)
+#define BITS_STC_INT_REALTIME_CS_8197F                                         \
+	(BIT_MASK_STC_INT_REALTIME_CS_8197F                                    \
+	 << BIT_SHIFT_STC_INT_REALTIME_CS_8197F)
+#define BIT_CLEAR_STC_INT_REALTIME_CS_8197F(x)                                 \
+	((x) & (~BITS_STC_INT_REALTIME_CS_8197F))
+#define BIT_GET_STC_INT_REALTIME_CS_8197F(x)                                   \
+	(((x) >> BIT_SHIFT_STC_INT_REALTIME_CS_8197F) &                        \
+	 BIT_MASK_STC_INT_REALTIME_CS_8197F)
+#define BIT_SET_STC_INT_REALTIME_CS_8197F(x, v)                                \
+	(BIT_CLEAR_STC_INT_REALTIME_CS_8197F(x) |                              \
+	 BIT_STC_INT_REALTIME_CS_8197F(v))
+
+/* 2 REG_ST_INT_CFG_8197F(HCI STATE CHANGE INTERRUPT CONFIGURATION) */
+#define BIT_STC_INT_GRP_EN_8197F BIT(31)
+
+#define BIT_SHIFT_STC_INT_EXPECT_LS_8197F 8
+#define BIT_MASK_STC_INT_EXPECT_LS_8197F 0x3f
+#define BIT_STC_INT_EXPECT_LS_8197F(x)                                         \
+	(((x) & BIT_MASK_STC_INT_EXPECT_LS_8197F)                              \
+	 << BIT_SHIFT_STC_INT_EXPECT_LS_8197F)
+#define BITS_STC_INT_EXPECT_LS_8197F                                           \
+	(BIT_MASK_STC_INT_EXPECT_LS_8197F << BIT_SHIFT_STC_INT_EXPECT_LS_8197F)
+#define BIT_CLEAR_STC_INT_EXPECT_LS_8197F(x)                                   \
+	((x) & (~BITS_STC_INT_EXPECT_LS_8197F))
+#define BIT_GET_STC_INT_EXPECT_LS_8197F(x)                                     \
+	(((x) >> BIT_SHIFT_STC_INT_EXPECT_LS_8197F) &                          \
+	 BIT_MASK_STC_INT_EXPECT_LS_8197F)
+#define BIT_SET_STC_INT_EXPECT_LS_8197F(x, v)                                  \
+	(BIT_CLEAR_STC_INT_EXPECT_LS_8197F(x) | BIT_STC_INT_EXPECT_LS_8197F(v))
+
+#define BIT_SHIFT_STC_INT_EXPECT_CS_8197F 0
+#define BIT_MASK_STC_INT_EXPECT_CS_8197F 0x3f
+#define BIT_STC_INT_EXPECT_CS_8197F(x)                                         \
+	(((x) & BIT_MASK_STC_INT_EXPECT_CS_8197F)                              \
+	 << BIT_SHIFT_STC_INT_EXPECT_CS_8197F)
+#define BITS_STC_INT_EXPECT_CS_8197F                                           \
+	(BIT_MASK_STC_INT_EXPECT_CS_8197F << BIT_SHIFT_STC_INT_EXPECT_CS_8197F)
+#define BIT_CLEAR_STC_INT_EXPECT_CS_8197F(x)                                   \
+	((x) & (~BITS_STC_INT_EXPECT_CS_8197F))
+#define BIT_GET_STC_INT_EXPECT_CS_8197F(x)                                     \
+	(((x) >> BIT_SHIFT_STC_INT_EXPECT_CS_8197F) &                          \
+	 BIT_MASK_STC_INT_EXPECT_CS_8197F)
+#define BIT_SET_STC_INT_EXPECT_CS_8197F(x, v)                                  \
+	(BIT_CLEAR_STC_INT_EXPECT_CS_8197F(x) | BIT_STC_INT_EXPECT_CS_8197F(v))
+
+/* 2 REG_CMU_DLY_CTRL_8197F(HCI PHY CLOCK MGT UNIT DELAY CONTROL ) */
+#define BIT_CMU_DLY_EN_8197F BIT(31)
+#define BIT_CMU_DLY_MODE_8197F BIT(30)
+
+#define BIT_SHIFT_CMU_DLY_PRE_DIV_8197F 0
+#define BIT_MASK_CMU_DLY_PRE_DIV_8197F 0xff
+#define BIT_CMU_DLY_PRE_DIV_8197F(x)                                           \
+	(((x) & BIT_MASK_CMU_DLY_PRE_DIV_8197F)                                \
+	 << BIT_SHIFT_CMU_DLY_PRE_DIV_8197F)
+#define BITS_CMU_DLY_PRE_DIV_8197F                                             \
+	(BIT_MASK_CMU_DLY_PRE_DIV_8197F << BIT_SHIFT_CMU_DLY_PRE_DIV_8197F)
+#define BIT_CLEAR_CMU_DLY_PRE_DIV_8197F(x) ((x) & (~BITS_CMU_DLY_PRE_DIV_8197F))
+#define BIT_GET_CMU_DLY_PRE_DIV_8197F(x)                                       \
+	(((x) >> BIT_SHIFT_CMU_DLY_PRE_DIV_8197F) &                            \
+	 BIT_MASK_CMU_DLY_PRE_DIV_8197F)
+#define BIT_SET_CMU_DLY_PRE_DIV_8197F(x, v)                                    \
+	(BIT_CLEAR_CMU_DLY_PRE_DIV_8197F(x) | BIT_CMU_DLY_PRE_DIV_8197F(v))
+
+/* 2 REG_CMU_DLY_CFG_8197F(HCI PHY CLOCK MGT UNIT DELAY CONFIGURATION ) */
+
+#define BIT_SHIFT_CMU_DLY_LTR_A2I_8197F 24
+#define BIT_MASK_CMU_DLY_LTR_A2I_8197F 0xff
+#define BIT_CMU_DLY_LTR_A2I_8197F(x)                                           \
+	(((x) & BIT_MASK_CMU_DLY_LTR_A2I_8197F)                                \
+	 << BIT_SHIFT_CMU_DLY_LTR_A2I_8197F)
+#define BITS_CMU_DLY_LTR_A2I_8197F                                             \
+	(BIT_MASK_CMU_DLY_LTR_A2I_8197F << BIT_SHIFT_CMU_DLY_LTR_A2I_8197F)
+#define BIT_CLEAR_CMU_DLY_LTR_A2I_8197F(x) ((x) & (~BITS_CMU_DLY_LTR_A2I_8197F))
+#define BIT_GET_CMU_DLY_LTR_A2I_8197F(x)                                       \
+	(((x) >> BIT_SHIFT_CMU_DLY_LTR_A2I_8197F) &                            \
+	 BIT_MASK_CMU_DLY_LTR_A2I_8197F)
+#define BIT_SET_CMU_DLY_LTR_A2I_8197F(x, v)                                    \
+	(BIT_CLEAR_CMU_DLY_LTR_A2I_8197F(x) | BIT_CMU_DLY_LTR_A2I_8197F(v))
+
+#define BIT_SHIFT_CMU_DLY_LTR_I2A_8197F 16
+#define BIT_MASK_CMU_DLY_LTR_I2A_8197F 0xff
+#define BIT_CMU_DLY_LTR_I2A_8197F(x)                                           \
+	(((x) & BIT_MASK_CMU_DLY_LTR_I2A_8197F)                                \
+	 << BIT_SHIFT_CMU_DLY_LTR_I2A_8197F)
+#define BITS_CMU_DLY_LTR_I2A_8197F                                             \
+	(BIT_MASK_CMU_DLY_LTR_I2A_8197F << BIT_SHIFT_CMU_DLY_LTR_I2A_8197F)
+#define BIT_CLEAR_CMU_DLY_LTR_I2A_8197F(x) ((x) & (~BITS_CMU_DLY_LTR_I2A_8197F))
+#define BIT_GET_CMU_DLY_LTR_I2A_8197F(x)                                       \
+	(((x) >> BIT_SHIFT_CMU_DLY_LTR_I2A_8197F) &                            \
+	 BIT_MASK_CMU_DLY_LTR_I2A_8197F)
+#define BIT_SET_CMU_DLY_LTR_I2A_8197F(x, v)                                    \
+	(BIT_CLEAR_CMU_DLY_LTR_I2A_8197F(x) | BIT_CMU_DLY_LTR_I2A_8197F(v))
+
+#define BIT_SHIFT_CMU_DLY_LTR_IDLE_8197F 8
+#define BIT_MASK_CMU_DLY_LTR_IDLE_8197F 0xff
+#define BIT_CMU_DLY_LTR_IDLE_8197F(x)                                          \
+	(((x) & BIT_MASK_CMU_DLY_LTR_IDLE_8197F)                               \
+	 << BIT_SHIFT_CMU_DLY_LTR_IDLE_8197F)
+#define BITS_CMU_DLY_LTR_IDLE_8197F                                            \
+	(BIT_MASK_CMU_DLY_LTR_IDLE_8197F << BIT_SHIFT_CMU_DLY_LTR_IDLE_8197F)
+#define BIT_CLEAR_CMU_DLY_LTR_IDLE_8197F(x)                                    \
+	((x) & (~BITS_CMU_DLY_LTR_IDLE_8197F))
+#define BIT_GET_CMU_DLY_LTR_IDLE_8197F(x)                                      \
+	(((x) >> BIT_SHIFT_CMU_DLY_LTR_IDLE_8197F) &                           \
+	 BIT_MASK_CMU_DLY_LTR_IDLE_8197F)
+#define BIT_SET_CMU_DLY_LTR_IDLE_8197F(x, v)                                   \
+	(BIT_CLEAR_CMU_DLY_LTR_IDLE_8197F(x) | BIT_CMU_DLY_LTR_IDLE_8197F(v))
+
+#define BIT_SHIFT_CMU_DLY_LTR_ACT_8197F 0
+#define BIT_MASK_CMU_DLY_LTR_ACT_8197F 0xff
+#define BIT_CMU_DLY_LTR_ACT_8197F(x)                                           \
+	(((x) & BIT_MASK_CMU_DLY_LTR_ACT_8197F)                                \
+	 << BIT_SHIFT_CMU_DLY_LTR_ACT_8197F)
+#define BITS_CMU_DLY_LTR_ACT_8197F                                             \
+	(BIT_MASK_CMU_DLY_LTR_ACT_8197F << BIT_SHIFT_CMU_DLY_LTR_ACT_8197F)
+#define BIT_CLEAR_CMU_DLY_LTR_ACT_8197F(x) ((x) & (~BITS_CMU_DLY_LTR_ACT_8197F))
+#define BIT_GET_CMU_DLY_LTR_ACT_8197F(x)                                       \
+	(((x) >> BIT_SHIFT_CMU_DLY_LTR_ACT_8197F) &                            \
+	 BIT_MASK_CMU_DLY_LTR_ACT_8197F)
+#define BIT_SET_CMU_DLY_LTR_ACT_8197F(x, v)                                    \
+	(BIT_CLEAR_CMU_DLY_LTR_ACT_8197F(x) | BIT_CMU_DLY_LTR_ACT_8197F(v))
+
+/* 2 REG_H2CQ_TXBD_DESA_8197F */
+
+#define BIT_SHIFT_H2CQ_TXBD_DESA_8197F 0
+#define BIT_MASK_H2CQ_TXBD_DESA_8197F 0xffffffffffffffffL
+#define BIT_H2CQ_TXBD_DESA_8197F(x)                                            \
+	(((x) & BIT_MASK_H2CQ_TXBD_DESA_8197F)                                 \
+	 << BIT_SHIFT_H2CQ_TXBD_DESA_8197F)
+#define BITS_H2CQ_TXBD_DESA_8197F                                              \
+	(BIT_MASK_H2CQ_TXBD_DESA_8197F << BIT_SHIFT_H2CQ_TXBD_DESA_8197F)
+#define BIT_CLEAR_H2CQ_TXBD_DESA_8197F(x) ((x) & (~BITS_H2CQ_TXBD_DESA_8197F))
+#define BIT_GET_H2CQ_TXBD_DESA_8197F(x)                                        \
+	(((x) >> BIT_SHIFT_H2CQ_TXBD_DESA_8197F) &                             \
+	 BIT_MASK_H2CQ_TXBD_DESA_8197F)
+#define BIT_SET_H2CQ_TXBD_DESA_8197F(x, v)                                     \
+	(BIT_CLEAR_H2CQ_TXBD_DESA_8197F(x) | BIT_H2CQ_TXBD_DESA_8197F(v))
+
+/* 2 REG_H2CQ_TXBD_NUM_8197F */
+#define BIT_HCI_H2CQ_FLAG_8197F BIT(14)
+
+#define BIT_SHIFT_H2CQ_DESC_MODE_8197F 12
+#define BIT_MASK_H2CQ_DESC_MODE_8197F 0x3
+#define BIT_H2CQ_DESC_MODE_8197F(x)                                            \
+	(((x) & BIT_MASK_H2CQ_DESC_MODE_8197F)                                 \
+	 << BIT_SHIFT_H2CQ_DESC_MODE_8197F)
+#define BITS_H2CQ_DESC_MODE_8197F                                              \
+	(BIT_MASK_H2CQ_DESC_MODE_8197F << BIT_SHIFT_H2CQ_DESC_MODE_8197F)
+#define BIT_CLEAR_H2CQ_DESC_MODE_8197F(x) ((x) & (~BITS_H2CQ_DESC_MODE_8197F))
+#define BIT_GET_H2CQ_DESC_MODE_8197F(x)                                        \
+	(((x) >> BIT_SHIFT_H2CQ_DESC_MODE_8197F) &                             \
+	 BIT_MASK_H2CQ_DESC_MODE_8197F)
+#define BIT_SET_H2CQ_DESC_MODE_8197F(x, v)                                     \
+	(BIT_CLEAR_H2CQ_DESC_MODE_8197F(x) | BIT_H2CQ_DESC_MODE_8197F(v))
+
+#define BIT_SHIFT_H2CQ_DESC_NUM_8197F 0
+#define BIT_MASK_H2CQ_DESC_NUM_8197F 0xfff
+#define BIT_H2CQ_DESC_NUM_8197F(x)                                             \
+	(((x) & BIT_MASK_H2CQ_DESC_NUM_8197F) << BIT_SHIFT_H2CQ_DESC_NUM_8197F)
+#define BITS_H2CQ_DESC_NUM_8197F                                               \
+	(BIT_MASK_H2CQ_DESC_NUM_8197F << BIT_SHIFT_H2CQ_DESC_NUM_8197F)
+#define BIT_CLEAR_H2CQ_DESC_NUM_8197F(x) ((x) & (~BITS_H2CQ_DESC_NUM_8197F))
+#define BIT_GET_H2CQ_DESC_NUM_8197F(x)                                         \
+	(((x) >> BIT_SHIFT_H2CQ_DESC_NUM_8197F) & BIT_MASK_H2CQ_DESC_NUM_8197F)
+#define BIT_SET_H2CQ_DESC_NUM_8197F(x, v)                                      \
+	(BIT_CLEAR_H2CQ_DESC_NUM_8197F(x) | BIT_H2CQ_DESC_NUM_8197F(v))
+
+/* 2 REG_H2CQ_TXBD_IDX_8197F */
+
+#define BIT_SHIFT_H2CQ_HW_IDX_8197F 16
+#define BIT_MASK_H2CQ_HW_IDX_8197F 0xfff
+#define BIT_H2CQ_HW_IDX_8197F(x)                                               \
+	(((x) & BIT_MASK_H2CQ_HW_IDX_8197F) << BIT_SHIFT_H2CQ_HW_IDX_8197F)
+#define BITS_H2CQ_HW_IDX_8197F                                                 \
+	(BIT_MASK_H2CQ_HW_IDX_8197F << BIT_SHIFT_H2CQ_HW_IDX_8197F)
+#define BIT_CLEAR_H2CQ_HW_IDX_8197F(x) ((x) & (~BITS_H2CQ_HW_IDX_8197F))
+#define BIT_GET_H2CQ_HW_IDX_8197F(x)                                           \
+	(((x) >> BIT_SHIFT_H2CQ_HW_IDX_8197F) & BIT_MASK_H2CQ_HW_IDX_8197F)
+#define BIT_SET_H2CQ_HW_IDX_8197F(x, v)                                        \
+	(BIT_CLEAR_H2CQ_HW_IDX_8197F(x) | BIT_H2CQ_HW_IDX_8197F(v))
+
+#define BIT_SHIFT_H2CQ_HOST_IDX_8197F 0
+#define BIT_MASK_H2CQ_HOST_IDX_8197F 0xfff
+#define BIT_H2CQ_HOST_IDX_8197F(x)                                             \
+	(((x) & BIT_MASK_H2CQ_HOST_IDX_8197F) << BIT_SHIFT_H2CQ_HOST_IDX_8197F)
+#define BITS_H2CQ_HOST_IDX_8197F                                               \
+	(BIT_MASK_H2CQ_HOST_IDX_8197F << BIT_SHIFT_H2CQ_HOST_IDX_8197F)
+#define BIT_CLEAR_H2CQ_HOST_IDX_8197F(x) ((x) & (~BITS_H2CQ_HOST_IDX_8197F))
+#define BIT_GET_H2CQ_HOST_IDX_8197F(x)                                         \
+	(((x) >> BIT_SHIFT_H2CQ_HOST_IDX_8197F) & BIT_MASK_H2CQ_HOST_IDX_8197F)
+#define BIT_SET_H2CQ_HOST_IDX_8197F(x, v)                                      \
+	(BIT_CLEAR_H2CQ_HOST_IDX_8197F(x) | BIT_H2CQ_HOST_IDX_8197F(v))
+
+/* 2 REG_H2CQ_CSR_8197F[31:0] (H2CQ CONTROL AND STATUS) */
+#define BIT_H2CQ_FULL_8197F BIT(31)
+#define BIT_CLR_H2CQ_HOST_IDX_8197F BIT(16)
+#define BIT_CLR_H2CQ_HW_IDX_8197F BIT(8)
+#define BIT_STOP_H2CQ_8197F BIT(0)
+
+/* 2 REG_AXI_EXCEPT_CS_8197F[31:0]	(AXI EXCEPTION CONTROL AND STATUS) */
+#define BIT_AXI_RXDMA_TIMEOUT_RE_8197F BIT(21)
+#define BIT_AXI_TXDMA_TIMEOUT_RE_8197F BIT(20)
+#define BIT_AXI_DECERR_W_RE_8197F BIT(19)
+#define BIT_AXI_DECERR_R_RE_8197F BIT(18)
+#define BIT_AXI_SLVERR_W_RE_8197F BIT(17)
+#define BIT_AXI_SLVERR_R_RE_8197F BIT(16)
+#define BIT_AXI_RXDMA_TIMEOUT_IE_8197F BIT(13)
+#define BIT_AXI_TXDMA_TIMEOUT_IE_8197F BIT(12)
+#define BIT_AXI_DECERR_W_IE_8197F BIT(11)
+#define BIT_AXI_DECERR_R_IE_8197F BIT(10)
+#define BIT_AXI_SLVERR_W_IE_8197F BIT(9)
+#define BIT_AXI_SLVERR_R_IE_8197F BIT(8)
+#define BIT_AXI_RXDMA_TIMEOUT_FLAG_8197F BIT(5)
+#define BIT_AXI_TXDMA_TIMEOUT_FLAG_8197F BIT(4)
+#define BIT_AXI_DECERR_W_FLAG_8197F BIT(3)
+#define BIT_AXI_DECERR_R_FLAG_8197F BIT(2)
+#define BIT_AXI_SLVERR_W_FLAG_8197F BIT(1)
+#define BIT_AXI_SLVERR_R_FLAG_8197F BIT(0)
+
+/* 2 REG_AXI_EXCEPT_TIME_8197F[31:0]	(AXI EXCEPTION TIME CONTROL) */
+
+#define BIT_SHIFT_AXI_RECOVERY_TIME_8197F 24
+#define BIT_MASK_AXI_RECOVERY_TIME_8197F 0xff
+#define BIT_AXI_RECOVERY_TIME_8197F(x)                                         \
+	(((x) & BIT_MASK_AXI_RECOVERY_TIME_8197F)                              \
+	 << BIT_SHIFT_AXI_RECOVERY_TIME_8197F)
+#define BITS_AXI_RECOVERY_TIME_8197F                                           \
+	(BIT_MASK_AXI_RECOVERY_TIME_8197F << BIT_SHIFT_AXI_RECOVERY_TIME_8197F)
+#define BIT_CLEAR_AXI_RECOVERY_TIME_8197F(x)                                   \
+	((x) & (~BITS_AXI_RECOVERY_TIME_8197F))
+#define BIT_GET_AXI_RECOVERY_TIME_8197F(x)                                     \
+	(((x) >> BIT_SHIFT_AXI_RECOVERY_TIME_8197F) &                          \
+	 BIT_MASK_AXI_RECOVERY_TIME_8197F)
+#define BIT_SET_AXI_RECOVERY_TIME_8197F(x, v)                                  \
+	(BIT_CLEAR_AXI_RECOVERY_TIME_8197F(x) | BIT_AXI_RECOVERY_TIME_8197F(v))
+
+#define BIT_SHIFT_AXI_RXDMA_TIMEOUT_VAL_8197F 12
+#define BIT_MASK_AXI_RXDMA_TIMEOUT_VAL_8197F 0xfff
+#define BIT_AXI_RXDMA_TIMEOUT_VAL_8197F(x)                                     \
+	(((x) & BIT_MASK_AXI_RXDMA_TIMEOUT_VAL_8197F)                          \
+	 << BIT_SHIFT_AXI_RXDMA_TIMEOUT_VAL_8197F)
+#define BITS_AXI_RXDMA_TIMEOUT_VAL_8197F                                       \
+	(BIT_MASK_AXI_RXDMA_TIMEOUT_VAL_8197F                                  \
+	 << BIT_SHIFT_AXI_RXDMA_TIMEOUT_VAL_8197F)
+#define BIT_CLEAR_AXI_RXDMA_TIMEOUT_VAL_8197F(x)                               \
+	((x) & (~BITS_AXI_RXDMA_TIMEOUT_VAL_8197F))
+#define BIT_GET_AXI_RXDMA_TIMEOUT_VAL_8197F(x)                                 \
+	(((x) >> BIT_SHIFT_AXI_RXDMA_TIMEOUT_VAL_8197F) &                      \
+	 BIT_MASK_AXI_RXDMA_TIMEOUT_VAL_8197F)
+#define BIT_SET_AXI_RXDMA_TIMEOUT_VAL_8197F(x, v)                              \
+	(BIT_CLEAR_AXI_RXDMA_TIMEOUT_VAL_8197F(x) |                            \
+	 BIT_AXI_RXDMA_TIMEOUT_VAL_8197F(v))
+
+#define BIT_SHIFT_AXI_TXDMA_TIMEOUT_VAL_8197F 0
+#define BIT_MASK_AXI_TXDMA_TIMEOUT_VAL_8197F 0xfff
+#define BIT_AXI_TXDMA_TIMEOUT_VAL_8197F(x)                                     \
+	(((x) & BIT_MASK_AXI_TXDMA_TIMEOUT_VAL_8197F)                          \
+	 << BIT_SHIFT_AXI_TXDMA_TIMEOUT_VAL_8197F)
+#define BITS_AXI_TXDMA_TIMEOUT_VAL_8197F                                       \
+	(BIT_MASK_AXI_TXDMA_TIMEOUT_VAL_8197F                                  \
+	 << BIT_SHIFT_AXI_TXDMA_TIMEOUT_VAL_8197F)
+#define BIT_CLEAR_AXI_TXDMA_TIMEOUT_VAL_8197F(x)                               \
+	((x) & (~BITS_AXI_TXDMA_TIMEOUT_VAL_8197F))
+#define BIT_GET_AXI_TXDMA_TIMEOUT_VAL_8197F(x)                                 \
+	(((x) >> BIT_SHIFT_AXI_TXDMA_TIMEOUT_VAL_8197F) &                      \
+	 BIT_MASK_AXI_TXDMA_TIMEOUT_VAL_8197F)
+#define BIT_SET_AXI_TXDMA_TIMEOUT_VAL_8197F(x, v)                              \
+	(BIT_CLEAR_AXI_TXDMA_TIMEOUT_VAL_8197F(x) |                            \
+	 BIT_AXI_TXDMA_TIMEOUT_VAL_8197F(v))
+
+/* 2 REG_Q0_INFO_8197F */
+
+#define BIT_SHIFT_QUEUEMACID_Q0_V1_8197F 25
+#define BIT_MASK_QUEUEMACID_Q0_V1_8197F 0x7f
+#define BIT_QUEUEMACID_Q0_V1_8197F(x)                                          \
+	(((x) & BIT_MASK_QUEUEMACID_Q0_V1_8197F)                               \
+	 << BIT_SHIFT_QUEUEMACID_Q0_V1_8197F)
+#define BITS_QUEUEMACID_Q0_V1_8197F                                            \
+	(BIT_MASK_QUEUEMACID_Q0_V1_8197F << BIT_SHIFT_QUEUEMACID_Q0_V1_8197F)
+#define BIT_CLEAR_QUEUEMACID_Q0_V1_8197F(x)                                    \
+	((x) & (~BITS_QUEUEMACID_Q0_V1_8197F))
+#define BIT_GET_QUEUEMACID_Q0_V1_8197F(x)                                      \
+	(((x) >> BIT_SHIFT_QUEUEMACID_Q0_V1_8197F) &                           \
+	 BIT_MASK_QUEUEMACID_Q0_V1_8197F)
+#define BIT_SET_QUEUEMACID_Q0_V1_8197F(x, v)                                   \
+	(BIT_CLEAR_QUEUEMACID_Q0_V1_8197F(x) | BIT_QUEUEMACID_Q0_V1_8197F(v))
+
+#define BIT_SHIFT_QUEUEAC_Q0_V1_8197F 23
+#define BIT_MASK_QUEUEAC_Q0_V1_8197F 0x3
+#define BIT_QUEUEAC_Q0_V1_8197F(x)                                             \
+	(((x) & BIT_MASK_QUEUEAC_Q0_V1_8197F) << BIT_SHIFT_QUEUEAC_Q0_V1_8197F)
+#define BITS_QUEUEAC_Q0_V1_8197F                                               \
+	(BIT_MASK_QUEUEAC_Q0_V1_8197F << BIT_SHIFT_QUEUEAC_Q0_V1_8197F)
+#define BIT_CLEAR_QUEUEAC_Q0_V1_8197F(x) ((x) & (~BITS_QUEUEAC_Q0_V1_8197F))
+#define BIT_GET_QUEUEAC_Q0_V1_8197F(x)                                         \
+	(((x) >> BIT_SHIFT_QUEUEAC_Q0_V1_8197F) & BIT_MASK_QUEUEAC_Q0_V1_8197F)
+#define BIT_SET_QUEUEAC_Q0_V1_8197F(x, v)                                      \
+	(BIT_CLEAR_QUEUEAC_Q0_V1_8197F(x) | BIT_QUEUEAC_Q0_V1_8197F(v))
+
+#define BIT_TIDEMPTY_Q0_V1_8197F BIT(22)
+
+#define BIT_SHIFT_TAIL_PKT_Q0_V2_8197F 11
+#define BIT_MASK_TAIL_PKT_Q0_V2_8197F 0x7ff
+#define BIT_TAIL_PKT_Q0_V2_8197F(x)                                            \
+	(((x) & BIT_MASK_TAIL_PKT_Q0_V2_8197F)                                 \
+	 << BIT_SHIFT_TAIL_PKT_Q0_V2_8197F)
+#define BITS_TAIL_PKT_Q0_V2_8197F                                              \
+	(BIT_MASK_TAIL_PKT_Q0_V2_8197F << BIT_SHIFT_TAIL_PKT_Q0_V2_8197F)
+#define BIT_CLEAR_TAIL_PKT_Q0_V2_8197F(x) ((x) & (~BITS_TAIL_PKT_Q0_V2_8197F))
+#define BIT_GET_TAIL_PKT_Q0_V2_8197F(x)                                        \
+	(((x) >> BIT_SHIFT_TAIL_PKT_Q0_V2_8197F) &                             \
+	 BIT_MASK_TAIL_PKT_Q0_V2_8197F)
+#define BIT_SET_TAIL_PKT_Q0_V2_8197F(x, v)                                     \
+	(BIT_CLEAR_TAIL_PKT_Q0_V2_8197F(x) | BIT_TAIL_PKT_Q0_V2_8197F(v))
+
+#define BIT_SHIFT_HEAD_PKT_Q0_V1_8197F 0
+#define BIT_MASK_HEAD_PKT_Q0_V1_8197F 0x7ff
+#define BIT_HEAD_PKT_Q0_V1_8197F(x)                                            \
+	(((x) & BIT_MASK_HEAD_PKT_Q0_V1_8197F)                                 \
+	 << BIT_SHIFT_HEAD_PKT_Q0_V1_8197F)
+#define BITS_HEAD_PKT_Q0_V1_8197F                                              \
+	(BIT_MASK_HEAD_PKT_Q0_V1_8197F << BIT_SHIFT_HEAD_PKT_Q0_V1_8197F)
+#define BIT_CLEAR_HEAD_PKT_Q0_V1_8197F(x) ((x) & (~BITS_HEAD_PKT_Q0_V1_8197F))
+#define BIT_GET_HEAD_PKT_Q0_V1_8197F(x)                                        \
+	(((x) >> BIT_SHIFT_HEAD_PKT_Q0_V1_8197F) &                             \
+	 BIT_MASK_HEAD_PKT_Q0_V1_8197F)
+#define BIT_SET_HEAD_PKT_Q0_V1_8197F(x, v)                                     \
+	(BIT_CLEAR_HEAD_PKT_Q0_V1_8197F(x) | BIT_HEAD_PKT_Q0_V1_8197F(v))
+
+/* 2 REG_Q1_INFO_8197F */
+
+#define BIT_SHIFT_QUEUEMACID_Q1_V1_8197F 25
+#define BIT_MASK_QUEUEMACID_Q1_V1_8197F 0x7f
+#define BIT_QUEUEMACID_Q1_V1_8197F(x)                                          \
+	(((x) & BIT_MASK_QUEUEMACID_Q1_V1_8197F)                               \
+	 << BIT_SHIFT_QUEUEMACID_Q1_V1_8197F)
+#define BITS_QUEUEMACID_Q1_V1_8197F                                            \
+	(BIT_MASK_QUEUEMACID_Q1_V1_8197F << BIT_SHIFT_QUEUEMACID_Q1_V1_8197F)
+#define BIT_CLEAR_QUEUEMACID_Q1_V1_8197F(x)                                    \
+	((x) & (~BITS_QUEUEMACID_Q1_V1_8197F))
+#define BIT_GET_QUEUEMACID_Q1_V1_8197F(x)                                      \
+	(((x) >> BIT_SHIFT_QUEUEMACID_Q1_V1_8197F) &                           \
+	 BIT_MASK_QUEUEMACID_Q1_V1_8197F)
+#define BIT_SET_QUEUEMACID_Q1_V1_8197F(x, v)                                   \
+	(BIT_CLEAR_QUEUEMACID_Q1_V1_8197F(x) | BIT_QUEUEMACID_Q1_V1_8197F(v))
+
+#define BIT_SHIFT_QUEUEAC_Q1_V1_8197F 23
+#define BIT_MASK_QUEUEAC_Q1_V1_8197F 0x3
+#define BIT_QUEUEAC_Q1_V1_8197F(x)                                             \
+	(((x) & BIT_MASK_QUEUEAC_Q1_V1_8197F) << BIT_SHIFT_QUEUEAC_Q1_V1_8197F)
+#define BITS_QUEUEAC_Q1_V1_8197F                                               \
+	(BIT_MASK_QUEUEAC_Q1_V1_8197F << BIT_SHIFT_QUEUEAC_Q1_V1_8197F)
+#define BIT_CLEAR_QUEUEAC_Q1_V1_8197F(x) ((x) & (~BITS_QUEUEAC_Q1_V1_8197F))
+#define BIT_GET_QUEUEAC_Q1_V1_8197F(x)                                         \
+	(((x) >> BIT_SHIFT_QUEUEAC_Q1_V1_8197F) & BIT_MASK_QUEUEAC_Q1_V1_8197F)
+#define BIT_SET_QUEUEAC_Q1_V1_8197F(x, v)                                      \
+	(BIT_CLEAR_QUEUEAC_Q1_V1_8197F(x) | BIT_QUEUEAC_Q1_V1_8197F(v))
+
+#define BIT_TIDEMPTY_Q1_V1_8197F BIT(22)
+
+#define BIT_SHIFT_TAIL_PKT_Q1_V2_8197F 11
+#define BIT_MASK_TAIL_PKT_Q1_V2_8197F 0x7ff
+#define BIT_TAIL_PKT_Q1_V2_8197F(x)                                            \
+	(((x) & BIT_MASK_TAIL_PKT_Q1_V2_8197F)                                 \
+	 << BIT_SHIFT_TAIL_PKT_Q1_V2_8197F)
+#define BITS_TAIL_PKT_Q1_V2_8197F                                              \
+	(BIT_MASK_TAIL_PKT_Q1_V2_8197F << BIT_SHIFT_TAIL_PKT_Q1_V2_8197F)
+#define BIT_CLEAR_TAIL_PKT_Q1_V2_8197F(x) ((x) & (~BITS_TAIL_PKT_Q1_V2_8197F))
+#define BIT_GET_TAIL_PKT_Q1_V2_8197F(x)                                        \
+	(((x) >> BIT_SHIFT_TAIL_PKT_Q1_V2_8197F) &                             \
+	 BIT_MASK_TAIL_PKT_Q1_V2_8197F)
+#define BIT_SET_TAIL_PKT_Q1_V2_8197F(x, v)                                     \
+	(BIT_CLEAR_TAIL_PKT_Q1_V2_8197F(x) | BIT_TAIL_PKT_Q1_V2_8197F(v))
+
+#define BIT_SHIFT_HEAD_PKT_Q1_V1_8197F 0
+#define BIT_MASK_HEAD_PKT_Q1_V1_8197F 0x7ff
+#define BIT_HEAD_PKT_Q1_V1_8197F(x)                                            \
+	(((x) & BIT_MASK_HEAD_PKT_Q1_V1_8197F)                                 \
+	 << BIT_SHIFT_HEAD_PKT_Q1_V1_8197F)
+#define BITS_HEAD_PKT_Q1_V1_8197F                                              \
+	(BIT_MASK_HEAD_PKT_Q1_V1_8197F << BIT_SHIFT_HEAD_PKT_Q1_V1_8197F)
+#define BIT_CLEAR_HEAD_PKT_Q1_V1_8197F(x) ((x) & (~BITS_HEAD_PKT_Q1_V1_8197F))
+#define BIT_GET_HEAD_PKT_Q1_V1_8197F(x)                                        \
+	(((x) >> BIT_SHIFT_HEAD_PKT_Q1_V1_8197F) &                             \
+	 BIT_MASK_HEAD_PKT_Q1_V1_8197F)
+#define BIT_SET_HEAD_PKT_Q1_V1_8197F(x, v)                                     \
+	(BIT_CLEAR_HEAD_PKT_Q1_V1_8197F(x) | BIT_HEAD_PKT_Q1_V1_8197F(v))
+
+/* 2 REG_Q2_INFO_8197F */
+
+#define BIT_SHIFT_QUEUEMACID_Q2_V1_8197F 25
+#define BIT_MASK_QUEUEMACID_Q2_V1_8197F 0x7f
+#define BIT_QUEUEMACID_Q2_V1_8197F(x)                                          \
+	(((x) & BIT_MASK_QUEUEMACID_Q2_V1_8197F)                               \
+	 << BIT_SHIFT_QUEUEMACID_Q2_V1_8197F)
+#define BITS_QUEUEMACID_Q2_V1_8197F                                            \
+	(BIT_MASK_QUEUEMACID_Q2_V1_8197F << BIT_SHIFT_QUEUEMACID_Q2_V1_8197F)
+#define BIT_CLEAR_QUEUEMACID_Q2_V1_8197F(x)                                    \
+	((x) & (~BITS_QUEUEMACID_Q2_V1_8197F))
+#define BIT_GET_QUEUEMACID_Q2_V1_8197F(x)                                      \
+	(((x) >> BIT_SHIFT_QUEUEMACID_Q2_V1_8197F) &                           \
+	 BIT_MASK_QUEUEMACID_Q2_V1_8197F)
+#define BIT_SET_QUEUEMACID_Q2_V1_8197F(x, v)                                   \
+	(BIT_CLEAR_QUEUEMACID_Q2_V1_8197F(x) | BIT_QUEUEMACID_Q2_V1_8197F(v))
+
+#define BIT_SHIFT_QUEUEAC_Q2_V1_8197F 23
+#define BIT_MASK_QUEUEAC_Q2_V1_8197F 0x3
+#define BIT_QUEUEAC_Q2_V1_8197F(x)                                             \
+	(((x) & BIT_MASK_QUEUEAC_Q2_V1_8197F) << BIT_SHIFT_QUEUEAC_Q2_V1_8197F)
+#define BITS_QUEUEAC_Q2_V1_8197F                                               \
+	(BIT_MASK_QUEUEAC_Q2_V1_8197F << BIT_SHIFT_QUEUEAC_Q2_V1_8197F)
+#define BIT_CLEAR_QUEUEAC_Q2_V1_8197F(x) ((x) & (~BITS_QUEUEAC_Q2_V1_8197F))
+#define BIT_GET_QUEUEAC_Q2_V1_8197F(x)                                         \
+	(((x) >> BIT_SHIFT_QUEUEAC_Q2_V1_8197F) & BIT_MASK_QUEUEAC_Q2_V1_8197F)
+#define BIT_SET_QUEUEAC_Q2_V1_8197F(x, v)                                      \
+	(BIT_CLEAR_QUEUEAC_Q2_V1_8197F(x) | BIT_QUEUEAC_Q2_V1_8197F(v))
+
+#define BIT_TIDEMPTY_Q2_V1_8197F BIT(22)
+
+#define BIT_SHIFT_TAIL_PKT_Q2_V2_8197F 11
+#define BIT_MASK_TAIL_PKT_Q2_V2_8197F 0x7ff
+#define BIT_TAIL_PKT_Q2_V2_8197F(x)                                            \
+	(((x) & BIT_MASK_TAIL_PKT_Q2_V2_8197F)                                 \
+	 << BIT_SHIFT_TAIL_PKT_Q2_V2_8197F)
+#define BITS_TAIL_PKT_Q2_V2_8197F                                              \
+	(BIT_MASK_TAIL_PKT_Q2_V2_8197F << BIT_SHIFT_TAIL_PKT_Q2_V2_8197F)
+#define BIT_CLEAR_TAIL_PKT_Q2_V2_8197F(x) ((x) & (~BITS_TAIL_PKT_Q2_V2_8197F))
+#define BIT_GET_TAIL_PKT_Q2_V2_8197F(x)                                        \
+	(((x) >> BIT_SHIFT_TAIL_PKT_Q2_V2_8197F) &                             \
+	 BIT_MASK_TAIL_PKT_Q2_V2_8197F)
+#define BIT_SET_TAIL_PKT_Q2_V2_8197F(x, v)                                     \
+	(BIT_CLEAR_TAIL_PKT_Q2_V2_8197F(x) | BIT_TAIL_PKT_Q2_V2_8197F(v))
+
+#define BIT_SHIFT_HEAD_PKT_Q2_V1_8197F 0
+#define BIT_MASK_HEAD_PKT_Q2_V1_8197F 0x7ff
+#define BIT_HEAD_PKT_Q2_V1_8197F(x)                                            \
+	(((x) & BIT_MASK_HEAD_PKT_Q2_V1_8197F)                                 \
+	 << BIT_SHIFT_HEAD_PKT_Q2_V1_8197F)
+#define BITS_HEAD_PKT_Q2_V1_8197F                                              \
+	(BIT_MASK_HEAD_PKT_Q2_V1_8197F << BIT_SHIFT_HEAD_PKT_Q2_V1_8197F)
+#define BIT_CLEAR_HEAD_PKT_Q2_V1_8197F(x) ((x) & (~BITS_HEAD_PKT_Q2_V1_8197F))
+#define BIT_GET_HEAD_PKT_Q2_V1_8197F(x)                                        \
+	(((x) >> BIT_SHIFT_HEAD_PKT_Q2_V1_8197F) &                             \
+	 BIT_MASK_HEAD_PKT_Q2_V1_8197F)
+#define BIT_SET_HEAD_PKT_Q2_V1_8197F(x, v)                                     \
+	(BIT_CLEAR_HEAD_PKT_Q2_V1_8197F(x) | BIT_HEAD_PKT_Q2_V1_8197F(v))
+
+/* 2 REG_Q3_INFO_8197F */
+
+#define BIT_SHIFT_QUEUEMACID_Q3_V1_8197F 25
+#define BIT_MASK_QUEUEMACID_Q3_V1_8197F 0x7f
+#define BIT_QUEUEMACID_Q3_V1_8197F(x)                                          \
+	(((x) & BIT_MASK_QUEUEMACID_Q3_V1_8197F)                               \
+	 << BIT_SHIFT_QUEUEMACID_Q3_V1_8197F)
+#define BITS_QUEUEMACID_Q3_V1_8197F                                            \
+	(BIT_MASK_QUEUEMACID_Q3_V1_8197F << BIT_SHIFT_QUEUEMACID_Q3_V1_8197F)
+#define BIT_CLEAR_QUEUEMACID_Q3_V1_8197F(x)                                    \
+	((x) & (~BITS_QUEUEMACID_Q3_V1_8197F))
+#define BIT_GET_QUEUEMACID_Q3_V1_8197F(x)                                      \
+	(((x) >> BIT_SHIFT_QUEUEMACID_Q3_V1_8197F) &                           \
+	 BIT_MASK_QUEUEMACID_Q3_V1_8197F)
+#define BIT_SET_QUEUEMACID_Q3_V1_8197F(x, v)                                   \
+	(BIT_CLEAR_QUEUEMACID_Q3_V1_8197F(x) | BIT_QUEUEMACID_Q3_V1_8197F(v))
+
+#define BIT_SHIFT_QUEUEAC_Q3_V1_8197F 23
+#define BIT_MASK_QUEUEAC_Q3_V1_8197F 0x3
+#define BIT_QUEUEAC_Q3_V1_8197F(x)                                             \
+	(((x) & BIT_MASK_QUEUEAC_Q3_V1_8197F) << BIT_SHIFT_QUEUEAC_Q3_V1_8197F)
+#define BITS_QUEUEAC_Q3_V1_8197F                                               \
+	(BIT_MASK_QUEUEAC_Q3_V1_8197F << BIT_SHIFT_QUEUEAC_Q3_V1_8197F)
+#define BIT_CLEAR_QUEUEAC_Q3_V1_8197F(x) ((x) & (~BITS_QUEUEAC_Q3_V1_8197F))
+#define BIT_GET_QUEUEAC_Q3_V1_8197F(x)                                         \
+	(((x) >> BIT_SHIFT_QUEUEAC_Q3_V1_8197F) & BIT_MASK_QUEUEAC_Q3_V1_8197F)
+#define BIT_SET_QUEUEAC_Q3_V1_8197F(x, v)                                      \
+	(BIT_CLEAR_QUEUEAC_Q3_V1_8197F(x) | BIT_QUEUEAC_Q3_V1_8197F(v))
+
+#define BIT_TIDEMPTY_Q3_V1_8197F BIT(22)
+
+#define BIT_SHIFT_TAIL_PKT_Q3_V2_8197F 11
+#define BIT_MASK_TAIL_PKT_Q3_V2_8197F 0x7ff
+#define BIT_TAIL_PKT_Q3_V2_8197F(x)                                            \
+	(((x) & BIT_MASK_TAIL_PKT_Q3_V2_8197F)                                 \
+	 << BIT_SHIFT_TAIL_PKT_Q3_V2_8197F)
+#define BITS_TAIL_PKT_Q3_V2_8197F                                              \
+	(BIT_MASK_TAIL_PKT_Q3_V2_8197F << BIT_SHIFT_TAIL_PKT_Q3_V2_8197F)
+#define BIT_CLEAR_TAIL_PKT_Q3_V2_8197F(x) ((x) & (~BITS_TAIL_PKT_Q3_V2_8197F))
+#define BIT_GET_TAIL_PKT_Q3_V2_8197F(x)                                        \
+	(((x) >> BIT_SHIFT_TAIL_PKT_Q3_V2_8197F) &                             \
+	 BIT_MASK_TAIL_PKT_Q3_V2_8197F)
+#define BIT_SET_TAIL_PKT_Q3_V2_8197F(x, v)                                     \
+	(BIT_CLEAR_TAIL_PKT_Q3_V2_8197F(x) | BIT_TAIL_PKT_Q3_V2_8197F(v))
+
+#define BIT_SHIFT_HEAD_PKT_Q3_V1_8197F 0
+#define BIT_MASK_HEAD_PKT_Q3_V1_8197F 0x7ff
+#define BIT_HEAD_PKT_Q3_V1_8197F(x)                                            \
+	(((x) & BIT_MASK_HEAD_PKT_Q3_V1_8197F)                                 \
+	 << BIT_SHIFT_HEAD_PKT_Q3_V1_8197F)
+#define BITS_HEAD_PKT_Q3_V1_8197F                                              \
+	(BIT_MASK_HEAD_PKT_Q3_V1_8197F << BIT_SHIFT_HEAD_PKT_Q3_V1_8197F)
+#define BIT_CLEAR_HEAD_PKT_Q3_V1_8197F(x) ((x) & (~BITS_HEAD_PKT_Q3_V1_8197F))
+#define BIT_GET_HEAD_PKT_Q3_V1_8197F(x)                                        \
+	(((x) >> BIT_SHIFT_HEAD_PKT_Q3_V1_8197F) &                             \
+	 BIT_MASK_HEAD_PKT_Q3_V1_8197F)
+#define BIT_SET_HEAD_PKT_Q3_V1_8197F(x, v)                                     \
+	(BIT_CLEAR_HEAD_PKT_Q3_V1_8197F(x) | BIT_HEAD_PKT_Q3_V1_8197F(v))
+
+/* 2 REG_MGQ_INFO_8197F */
+
+#define BIT_SHIFT_QUEUEMACID_MGQ_V1_8197F 25
+#define BIT_MASK_QUEUEMACID_MGQ_V1_8197F 0x7f
+#define BIT_QUEUEMACID_MGQ_V1_8197F(x)                                         \
+	(((x) & BIT_MASK_QUEUEMACID_MGQ_V1_8197F)                              \
+	 << BIT_SHIFT_QUEUEMACID_MGQ_V1_8197F)
+#define BITS_QUEUEMACID_MGQ_V1_8197F                                           \
+	(BIT_MASK_QUEUEMACID_MGQ_V1_8197F << BIT_SHIFT_QUEUEMACID_MGQ_V1_8197F)
+#define BIT_CLEAR_QUEUEMACID_MGQ_V1_8197F(x)                                   \
+	((x) & (~BITS_QUEUEMACID_MGQ_V1_8197F))
+#define BIT_GET_QUEUEMACID_MGQ_V1_8197F(x)                                     \
+	(((x) >> BIT_SHIFT_QUEUEMACID_MGQ_V1_8197F) &                          \
+	 BIT_MASK_QUEUEMACID_MGQ_V1_8197F)
+#define BIT_SET_QUEUEMACID_MGQ_V1_8197F(x, v)                                  \
+	(BIT_CLEAR_QUEUEMACID_MGQ_V1_8197F(x) | BIT_QUEUEMACID_MGQ_V1_8197F(v))
+
+#define BIT_SHIFT_QUEUEAC_MGQ_V1_8197F 23
+#define BIT_MASK_QUEUEAC_MGQ_V1_8197F 0x3
+#define BIT_QUEUEAC_MGQ_V1_8197F(x)                                            \
+	(((x) & BIT_MASK_QUEUEAC_MGQ_V1_8197F)                                 \
+	 << BIT_SHIFT_QUEUEAC_MGQ_V1_8197F)
+#define BITS_QUEUEAC_MGQ_V1_8197F                                              \
+	(BIT_MASK_QUEUEAC_MGQ_V1_8197F << BIT_SHIFT_QUEUEAC_MGQ_V1_8197F)
+#define BIT_CLEAR_QUEUEAC_MGQ_V1_8197F(x) ((x) & (~BITS_QUEUEAC_MGQ_V1_8197F))
+#define BIT_GET_QUEUEAC_MGQ_V1_8197F(x)                                        \
+	(((x) >> BIT_SHIFT_QUEUEAC_MGQ_V1_8197F) &                             \
+	 BIT_MASK_QUEUEAC_MGQ_V1_8197F)
+#define BIT_SET_QUEUEAC_MGQ_V1_8197F(x, v)                                     \
+	(BIT_CLEAR_QUEUEAC_MGQ_V1_8197F(x) | BIT_QUEUEAC_MGQ_V1_8197F(v))
+
+#define BIT_TIDEMPTY_MGQ_V1_8197F BIT(22)
+
+#define BIT_SHIFT_TAIL_PKT_MGQ_V2_8197F 11
+#define BIT_MASK_TAIL_PKT_MGQ_V2_8197F 0x7ff
+#define BIT_TAIL_PKT_MGQ_V2_8197F(x)                                           \
+	(((x) & BIT_MASK_TAIL_PKT_MGQ_V2_8197F)                                \
+	 << BIT_SHIFT_TAIL_PKT_MGQ_V2_8197F)
+#define BITS_TAIL_PKT_MGQ_V2_8197F                                             \
+	(BIT_MASK_TAIL_PKT_MGQ_V2_8197F << BIT_SHIFT_TAIL_PKT_MGQ_V2_8197F)
+#define BIT_CLEAR_TAIL_PKT_MGQ_V2_8197F(x) ((x) & (~BITS_TAIL_PKT_MGQ_V2_8197F))
+#define BIT_GET_TAIL_PKT_MGQ_V2_8197F(x)                                       \
+	(((x) >> BIT_SHIFT_TAIL_PKT_MGQ_V2_8197F) &                            \
+	 BIT_MASK_TAIL_PKT_MGQ_V2_8197F)
+#define BIT_SET_TAIL_PKT_MGQ_V2_8197F(x, v)                                    \
+	(BIT_CLEAR_TAIL_PKT_MGQ_V2_8197F(x) | BIT_TAIL_PKT_MGQ_V2_8197F(v))
+
+#define BIT_SHIFT_HEAD_PKT_MGQ_V1_8197F 0
+#define BIT_MASK_HEAD_PKT_MGQ_V1_8197F 0x7ff
+#define BIT_HEAD_PKT_MGQ_V1_8197F(x)                                           \
+	(((x) & BIT_MASK_HEAD_PKT_MGQ_V1_8197F)                                \
+	 << BIT_SHIFT_HEAD_PKT_MGQ_V1_8197F)
+#define BITS_HEAD_PKT_MGQ_V1_8197F                                             \
+	(BIT_MASK_HEAD_PKT_MGQ_V1_8197F << BIT_SHIFT_HEAD_PKT_MGQ_V1_8197F)
+#define BIT_CLEAR_HEAD_PKT_MGQ_V1_8197F(x) ((x) & (~BITS_HEAD_PKT_MGQ_V1_8197F))
+#define BIT_GET_HEAD_PKT_MGQ_V1_8197F(x)                                       \
+	(((x) >> BIT_SHIFT_HEAD_PKT_MGQ_V1_8197F) &                            \
+	 BIT_MASK_HEAD_PKT_MGQ_V1_8197F)
+#define BIT_SET_HEAD_PKT_MGQ_V1_8197F(x, v)                                    \
+	(BIT_CLEAR_HEAD_PKT_MGQ_V1_8197F(x) | BIT_HEAD_PKT_MGQ_V1_8197F(v))
+
+/* 2 REG_HIQ_INFO_8197F */
+
+#define BIT_SHIFT_QUEUEMACID_HIQ_V1_8197F 25
+#define BIT_MASK_QUEUEMACID_HIQ_V1_8197F 0x7f
+#define BIT_QUEUEMACID_HIQ_V1_8197F(x)                                         \
+	(((x) & BIT_MASK_QUEUEMACID_HIQ_V1_8197F)                              \
+	 << BIT_SHIFT_QUEUEMACID_HIQ_V1_8197F)
+#define BITS_QUEUEMACID_HIQ_V1_8197F                                           \
+	(BIT_MASK_QUEUEMACID_HIQ_V1_8197F << BIT_SHIFT_QUEUEMACID_HIQ_V1_8197F)
+#define BIT_CLEAR_QUEUEMACID_HIQ_V1_8197F(x)                                   \
+	((x) & (~BITS_QUEUEMACID_HIQ_V1_8197F))
+#define BIT_GET_QUEUEMACID_HIQ_V1_8197F(x)                                     \
+	(((x) >> BIT_SHIFT_QUEUEMACID_HIQ_V1_8197F) &                          \
+	 BIT_MASK_QUEUEMACID_HIQ_V1_8197F)
+#define BIT_SET_QUEUEMACID_HIQ_V1_8197F(x, v)                                  \
+	(BIT_CLEAR_QUEUEMACID_HIQ_V1_8197F(x) | BIT_QUEUEMACID_HIQ_V1_8197F(v))
+
+#define BIT_SHIFT_QUEUEAC_HIQ_V1_8197F 23
+#define BIT_MASK_QUEUEAC_HIQ_V1_8197F 0x3
+#define BIT_QUEUEAC_HIQ_V1_8197F(x)                                            \
+	(((x) & BIT_MASK_QUEUEAC_HIQ_V1_8197F)                                 \
+	 << BIT_SHIFT_QUEUEAC_HIQ_V1_8197F)
+#define BITS_QUEUEAC_HIQ_V1_8197F                                              \
+	(BIT_MASK_QUEUEAC_HIQ_V1_8197F << BIT_SHIFT_QUEUEAC_HIQ_V1_8197F)
+#define BIT_CLEAR_QUEUEAC_HIQ_V1_8197F(x) ((x) & (~BITS_QUEUEAC_HIQ_V1_8197F))
+#define BIT_GET_QUEUEAC_HIQ_V1_8197F(x)                                        \
+	(((x) >> BIT_SHIFT_QUEUEAC_HIQ_V1_8197F) &                             \
+	 BIT_MASK_QUEUEAC_HIQ_V1_8197F)
+#define BIT_SET_QUEUEAC_HIQ_V1_8197F(x, v)                                     \
+	(BIT_CLEAR_QUEUEAC_HIQ_V1_8197F(x) | BIT_QUEUEAC_HIQ_V1_8197F(v))
+
+#define BIT_TIDEMPTY_HIQ_V1_8197F BIT(22)
+
+#define BIT_SHIFT_TAIL_PKT_HIQ_V2_8197F 11
+#define BIT_MASK_TAIL_PKT_HIQ_V2_8197F 0x7ff
+#define BIT_TAIL_PKT_HIQ_V2_8197F(x)                                           \
+	(((x) & BIT_MASK_TAIL_PKT_HIQ_V2_8197F)                                \
+	 << BIT_SHIFT_TAIL_PKT_HIQ_V2_8197F)
+#define BITS_TAIL_PKT_HIQ_V2_8197F                                             \
+	(BIT_MASK_TAIL_PKT_HIQ_V2_8197F << BIT_SHIFT_TAIL_PKT_HIQ_V2_8197F)
+#define BIT_CLEAR_TAIL_PKT_HIQ_V2_8197F(x) ((x) & (~BITS_TAIL_PKT_HIQ_V2_8197F))
+#define BIT_GET_TAIL_PKT_HIQ_V2_8197F(x)                                       \
+	(((x) >> BIT_SHIFT_TAIL_PKT_HIQ_V2_8197F) &                            \
+	 BIT_MASK_TAIL_PKT_HIQ_V2_8197F)
+#define BIT_SET_TAIL_PKT_HIQ_V2_8197F(x, v)                                    \
+	(BIT_CLEAR_TAIL_PKT_HIQ_V2_8197F(x) | BIT_TAIL_PKT_HIQ_V2_8197F(v))
+
+#define BIT_SHIFT_HEAD_PKT_HIQ_V1_8197F 0
+#define BIT_MASK_HEAD_PKT_HIQ_V1_8197F 0x7ff
+#define BIT_HEAD_PKT_HIQ_V1_8197F(x)                                           \
+	(((x) & BIT_MASK_HEAD_PKT_HIQ_V1_8197F)                                \
+	 << BIT_SHIFT_HEAD_PKT_HIQ_V1_8197F)
+#define BITS_HEAD_PKT_HIQ_V1_8197F                                             \
+	(BIT_MASK_HEAD_PKT_HIQ_V1_8197F << BIT_SHIFT_HEAD_PKT_HIQ_V1_8197F)
+#define BIT_CLEAR_HEAD_PKT_HIQ_V1_8197F(x) ((x) & (~BITS_HEAD_PKT_HIQ_V1_8197F))
+#define BIT_GET_HEAD_PKT_HIQ_V1_8197F(x)                                       \
+	(((x) >> BIT_SHIFT_HEAD_PKT_HIQ_V1_8197F) &                            \
+	 BIT_MASK_HEAD_PKT_HIQ_V1_8197F)
+#define BIT_SET_HEAD_PKT_HIQ_V1_8197F(x, v)                                    \
+	(BIT_CLEAR_HEAD_PKT_HIQ_V1_8197F(x) | BIT_HEAD_PKT_HIQ_V1_8197F(v))
+
+/* 2 REG_BCNQ_INFO_8197F */
+
+#define BIT_SHIFT_BCNQ_HEAD_PG_V1_8197F 0
+#define BIT_MASK_BCNQ_HEAD_PG_V1_8197F 0xfff
+#define BIT_BCNQ_HEAD_PG_V1_8197F(x)                                           \
+	(((x) & BIT_MASK_BCNQ_HEAD_PG_V1_8197F)                                \
+	 << BIT_SHIFT_BCNQ_HEAD_PG_V1_8197F)
+#define BITS_BCNQ_HEAD_PG_V1_8197F                                             \
+	(BIT_MASK_BCNQ_HEAD_PG_V1_8197F << BIT_SHIFT_BCNQ_HEAD_PG_V1_8197F)
+#define BIT_CLEAR_BCNQ_HEAD_PG_V1_8197F(x) ((x) & (~BITS_BCNQ_HEAD_PG_V1_8197F))
+#define BIT_GET_BCNQ_HEAD_PG_V1_8197F(x)                                       \
+	(((x) >> BIT_SHIFT_BCNQ_HEAD_PG_V1_8197F) &                            \
+	 BIT_MASK_BCNQ_HEAD_PG_V1_8197F)
+#define BIT_SET_BCNQ_HEAD_PG_V1_8197F(x, v)                                    \
+	(BIT_CLEAR_BCNQ_HEAD_PG_V1_8197F(x) | BIT_BCNQ_HEAD_PG_V1_8197F(v))
+
+/* 2 REG_TXPKT_EMPTY_8197F */
+#define BIT_BCNQ_EMPTY_8197F BIT(11)
+#define BIT_HQQ_EMPTY_8197F BIT(10)
+#define BIT_MQQ_EMPTY_8197F BIT(9)
+#define BIT_MGQ_CPU_EMPTY_8197F BIT(8)
+#define BIT_AC7Q_EMPTY_8197F BIT(7)
+#define BIT_AC6Q_EMPTY_8197F BIT(6)
+#define BIT_AC5Q_EMPTY_8197F BIT(5)
+#define BIT_AC4Q_EMPTY_8197F BIT(4)
+#define BIT_AC3Q_EMPTY_8197F BIT(3)
+#define BIT_AC2Q_EMPTY_8197F BIT(2)
+#define BIT_AC1Q_EMPTY_8197F BIT(1)
+#define BIT_AC0Q_EMPTY_8197F BIT(0)
+
+/* 2 REG_CPU_MGQ_INFO_8197F */
+#define BIT_BCN1_POLL_8197F BIT(30)
+#define BIT_CPUMGT_POLL_8197F BIT(29)
+#define BIT_BCN_POLL_8197F BIT(28)
+#define BIT_CPUMGQ_FW_NUM_V1_8197F BIT(12)
+
+#define BIT_SHIFT_FW_FREE_TAIL_V1_8197F 0
+#define BIT_MASK_FW_FREE_TAIL_V1_8197F 0xfff
+#define BIT_FW_FREE_TAIL_V1_8197F(x)                                           \
+	(((x) & BIT_MASK_FW_FREE_TAIL_V1_8197F)                                \
+	 << BIT_SHIFT_FW_FREE_TAIL_V1_8197F)
+#define BITS_FW_FREE_TAIL_V1_8197F                                             \
+	(BIT_MASK_FW_FREE_TAIL_V1_8197F << BIT_SHIFT_FW_FREE_TAIL_V1_8197F)
+#define BIT_CLEAR_FW_FREE_TAIL_V1_8197F(x) ((x) & (~BITS_FW_FREE_TAIL_V1_8197F))
+#define BIT_GET_FW_FREE_TAIL_V1_8197F(x)                                       \
+	(((x) >> BIT_SHIFT_FW_FREE_TAIL_V1_8197F) &                            \
+	 BIT_MASK_FW_FREE_TAIL_V1_8197F)
+#define BIT_SET_FW_FREE_TAIL_V1_8197F(x, v)                                    \
+	(BIT_CLEAR_FW_FREE_TAIL_V1_8197F(x) | BIT_FW_FREE_TAIL_V1_8197F(v))
+
+/* 2 REG_FWHW_TXQ_CTRL_8197F */
+#define BIT_RTS_LIMIT_IN_OFDM_8197F BIT(23)
+#define BIT_EN_BCNQ_DL_8197F BIT(22)
+#define BIT_EN_RD_RESP_NAV_BK_8197F BIT(21)
+#define BIT_EN_WR_FREE_TAIL_8197F BIT(20)
+
+#define BIT_SHIFT_EN_QUEUE_RPT_8197F 8
+#define BIT_MASK_EN_QUEUE_RPT_8197F 0xff
+#define BIT_EN_QUEUE_RPT_8197F(x)                                              \
+	(((x) & BIT_MASK_EN_QUEUE_RPT_8197F) << BIT_SHIFT_EN_QUEUE_RPT_8197F)
+#define BITS_EN_QUEUE_RPT_8197F                                                \
+	(BIT_MASK_EN_QUEUE_RPT_8197F << BIT_SHIFT_EN_QUEUE_RPT_8197F)
+#define BIT_CLEAR_EN_QUEUE_RPT_8197F(x) ((x) & (~BITS_EN_QUEUE_RPT_8197F))
+#define BIT_GET_EN_QUEUE_RPT_8197F(x)                                          \
+	(((x) >> BIT_SHIFT_EN_QUEUE_RPT_8197F) & BIT_MASK_EN_QUEUE_RPT_8197F)
+#define BIT_SET_EN_QUEUE_RPT_8197F(x, v)                                       \
+	(BIT_CLEAR_EN_QUEUE_RPT_8197F(x) | BIT_EN_QUEUE_RPT_8197F(v))
+
+#define BIT_EN_RTY_BK_8197F BIT(7)
+#define BIT_EN_USE_INI_RAT_8197F BIT(6)
+#define BIT_EN_RTS_NAV_BK_8197F BIT(5)
+#define BIT_DIS_SSN_CHECK_8197F BIT(4)
+#define BIT_MACID_MATCH_RTS_8197F BIT(3)
+#define BIT_EN_BCN_TRXRPT_V1_8197F BIT(2)
+#define BIT_R_EN_FTMRPT_8197F BIT(1)
+#define BIT_R_BMC_NAV_PROTECT_8197F BIT(0)
+
+/* 2 REG_NOT_VALID_8197F */
+#define BIT__R_EN_RTY_BK_COD_8197F BIT(2)
+
+#define BIT_SHIFT__R_DATA_FALLBACK_SEL_8197F 0
+#define BIT_MASK__R_DATA_FALLBACK_SEL_8197F 0x3
+#define BIT__R_DATA_FALLBACK_SEL_8197F(x)                                      \
+	(((x) & BIT_MASK__R_DATA_FALLBACK_SEL_8197F)                           \
+	 << BIT_SHIFT__R_DATA_FALLBACK_SEL_8197F)
+#define BITS__R_DATA_FALLBACK_SEL_8197F                                        \
+	(BIT_MASK__R_DATA_FALLBACK_SEL_8197F                                   \
+	 << BIT_SHIFT__R_DATA_FALLBACK_SEL_8197F)
+#define BIT_CLEAR__R_DATA_FALLBACK_SEL_8197F(x)                                \
+	((x) & (~BITS__R_DATA_FALLBACK_SEL_8197F))
+#define BIT_GET__R_DATA_FALLBACK_SEL_8197F(x)                                  \
+	(((x) >> BIT_SHIFT__R_DATA_FALLBACK_SEL_8197F) &                       \
+	 BIT_MASK__R_DATA_FALLBACK_SEL_8197F)
+#define BIT_SET__R_DATA_FALLBACK_SEL_8197F(x, v)                               \
+	(BIT_CLEAR__R_DATA_FALLBACK_SEL_8197F(x) |                             \
+	 BIT__R_DATA_FALLBACK_SEL_8197F(v))
+
+/* 2 REG_BCNQ_BDNY_V1_8197F */
+
+#define BIT_SHIFT_BCNQ_PGBNDY_V1_8197F 0
+#define BIT_MASK_BCNQ_PGBNDY_V1_8197F 0xfff
+#define BIT_BCNQ_PGBNDY_V1_8197F(x)                                            \
+	(((x) & BIT_MASK_BCNQ_PGBNDY_V1_8197F)                                 \
+	 << BIT_SHIFT_BCNQ_PGBNDY_V1_8197F)
+#define BITS_BCNQ_PGBNDY_V1_8197F                                              \
+	(BIT_MASK_BCNQ_PGBNDY_V1_8197F << BIT_SHIFT_BCNQ_PGBNDY_V1_8197F)
+#define BIT_CLEAR_BCNQ_PGBNDY_V1_8197F(x) ((x) & (~BITS_BCNQ_PGBNDY_V1_8197F))
+#define BIT_GET_BCNQ_PGBNDY_V1_8197F(x)                                        \
+	(((x) >> BIT_SHIFT_BCNQ_PGBNDY_V1_8197F) &                             \
+	 BIT_MASK_BCNQ_PGBNDY_V1_8197F)
+#define BIT_SET_BCNQ_PGBNDY_V1_8197F(x, v)                                     \
+	(BIT_CLEAR_BCNQ_PGBNDY_V1_8197F(x) | BIT_BCNQ_PGBNDY_V1_8197F(v))
+
+/* 2 REG_NOT_VALID_8197F */
+
+/* 2 REG_LIFETIME_EN_8197F */
+#define BIT_BT_INT_CPU_8197F BIT(7)
+#define BIT_BT_INT_PTA_8197F BIT(6)
+#define BIT_EN_CTRL_RTYBIT_8197F BIT(4)
+#define BIT_LIFETIME_BK_EN_8197F BIT(3)
+#define BIT_LIFETIME_BE_EN_8197F BIT(2)
+#define BIT_LIFETIME_VI_EN_8197F BIT(1)
+#define BIT_LIFETIME_VO_EN_8197F BIT(0)
+
+/* 2 REG_NOT_VALID_8197F */
+
+/* 2 REG_SPEC_SIFS_8197F */
+
+#define BIT_SHIFT_SPEC_SIFS_OFDM_PTCL_8197F 8
+#define BIT_MASK_SPEC_SIFS_OFDM_PTCL_8197F 0xff
+#define BIT_SPEC_SIFS_OFDM_PTCL_8197F(x)                                       \
+	(((x) & BIT_MASK_SPEC_SIFS_OFDM_PTCL_8197F)                            \
+	 << BIT_SHIFT_SPEC_SIFS_OFDM_PTCL_8197F)
+#define BITS_SPEC_SIFS_OFDM_PTCL_8197F                                         \
+	(BIT_MASK_SPEC_SIFS_OFDM_PTCL_8197F                                    \
+	 << BIT_SHIFT_SPEC_SIFS_OFDM_PTCL_8197F)
+#define BIT_CLEAR_SPEC_SIFS_OFDM_PTCL_8197F(x)                                 \
+	((x) & (~BITS_SPEC_SIFS_OFDM_PTCL_8197F))
+#define BIT_GET_SPEC_SIFS_OFDM_PTCL_8197F(x)                                   \
+	(((x) >> BIT_SHIFT_SPEC_SIFS_OFDM_PTCL_8197F) &                        \
+	 BIT_MASK_SPEC_SIFS_OFDM_PTCL_8197F)
+#define BIT_SET_SPEC_SIFS_OFDM_PTCL_8197F(x, v)                                \
+	(BIT_CLEAR_SPEC_SIFS_OFDM_PTCL_8197F(x) |                              \
+	 BIT_SPEC_SIFS_OFDM_PTCL_8197F(v))
+
+#define BIT_SHIFT_SPEC_SIFS_CCK_PTCL_8197F 0
+#define BIT_MASK_SPEC_SIFS_CCK_PTCL_8197F 0xff
+#define BIT_SPEC_SIFS_CCK_PTCL_8197F(x)                                        \
+	(((x) & BIT_MASK_SPEC_SIFS_CCK_PTCL_8197F)                             \
+	 << BIT_SHIFT_SPEC_SIFS_CCK_PTCL_8197F)
+#define BITS_SPEC_SIFS_CCK_PTCL_8197F                                          \
+	(BIT_MASK_SPEC_SIFS_CCK_PTCL_8197F                                     \
+	 << BIT_SHIFT_SPEC_SIFS_CCK_PTCL_8197F)
+#define BIT_CLEAR_SPEC_SIFS_CCK_PTCL_8197F(x)                                  \
+	((x) & (~BITS_SPEC_SIFS_CCK_PTCL_8197F))
+#define BIT_GET_SPEC_SIFS_CCK_PTCL_8197F(x)                                    \
+	(((x) >> BIT_SHIFT_SPEC_SIFS_CCK_PTCL_8197F) &                         \
+	 BIT_MASK_SPEC_SIFS_CCK_PTCL_8197F)
+#define BIT_SET_SPEC_SIFS_CCK_PTCL_8197F(x, v)                                 \
+	(BIT_CLEAR_SPEC_SIFS_CCK_PTCL_8197F(x) |                               \
+	 BIT_SPEC_SIFS_CCK_PTCL_8197F(v))
+
+/* 2 REG_RETRY_LIMIT_8197F */
+
+#define BIT_SHIFT_SRL_8197F 8
+#define BIT_MASK_SRL_8197F 0x3f
+#define BIT_SRL_8197F(x) (((x) & BIT_MASK_SRL_8197F) << BIT_SHIFT_SRL_8197F)
+#define BITS_SRL_8197F (BIT_MASK_SRL_8197F << BIT_SHIFT_SRL_8197F)
+#define BIT_CLEAR_SRL_8197F(x) ((x) & (~BITS_SRL_8197F))
+#define BIT_GET_SRL_8197F(x) (((x) >> BIT_SHIFT_SRL_8197F) & BIT_MASK_SRL_8197F)
+#define BIT_SET_SRL_8197F(x, v) (BIT_CLEAR_SRL_8197F(x) | BIT_SRL_8197F(v))
+
+#define BIT_SHIFT_LRL_8197F 0
+#define BIT_MASK_LRL_8197F 0x3f
+#define BIT_LRL_8197F(x) (((x) & BIT_MASK_LRL_8197F) << BIT_SHIFT_LRL_8197F)
+#define BITS_LRL_8197F (BIT_MASK_LRL_8197F << BIT_SHIFT_LRL_8197F)
+#define BIT_CLEAR_LRL_8197F(x) ((x) & (~BITS_LRL_8197F))
+#define BIT_GET_LRL_8197F(x) (((x) >> BIT_SHIFT_LRL_8197F) & BIT_MASK_LRL_8197F)
+#define BIT_SET_LRL_8197F(x, v) (BIT_CLEAR_LRL_8197F(x) | BIT_LRL_8197F(v))
+
+/* 2 REG_TXBF_CTRL_8197F */
+#define BIT_R_ENABLE_NDPA_8197F BIT(31)
+#define BIT_USE_NDPA_PARAMETER_8197F BIT(30)
+#define BIT_R_PROP_TXBF_8197F BIT(29)
+#define BIT_R_EN_NDPA_INT_8197F BIT(28)
+#define BIT_R_TXBF1_80M_8197F BIT(27)
+#define BIT_R_TXBF1_40M_8197F BIT(26)
+#define BIT_R_TXBF1_20M_8197F BIT(25)
+
+#define BIT_SHIFT_R_TXBF1_AID_8197F 16
+#define BIT_MASK_R_TXBF1_AID_8197F 0x1ff
+#define BIT_R_TXBF1_AID_8197F(x)                                               \
+	(((x) & BIT_MASK_R_TXBF1_AID_8197F) << BIT_SHIFT_R_TXBF1_AID_8197F)
+#define BITS_R_TXBF1_AID_8197F                                                 \
+	(BIT_MASK_R_TXBF1_AID_8197F << BIT_SHIFT_R_TXBF1_AID_8197F)
+#define BIT_CLEAR_R_TXBF1_AID_8197F(x) ((x) & (~BITS_R_TXBF1_AID_8197F))
+#define BIT_GET_R_TXBF1_AID_8197F(x)                                           \
+	(((x) >> BIT_SHIFT_R_TXBF1_AID_8197F) & BIT_MASK_R_TXBF1_AID_8197F)
+#define BIT_SET_R_TXBF1_AID_8197F(x, v)                                        \
+	(BIT_CLEAR_R_TXBF1_AID_8197F(x) | BIT_R_TXBF1_AID_8197F(v))
+
+#define BIT_DIS_NDP_BFEN_8197F BIT(15)
+#define BIT_R_TXBCN_NOBLOCK_NDP_8197F BIT(14)
+#define BIT_R_TXBF0_80M_8197F BIT(11)
+#define BIT_R_TXBF0_40M_8197F BIT(10)
+#define BIT_R_TXBF0_20M_8197F BIT(9)
+
+#define BIT_SHIFT_R_TXBF0_AID_8197F 0
+#define BIT_MASK_R_TXBF0_AID_8197F 0x1ff
+#define BIT_R_TXBF0_AID_8197F(x)                                               \
+	(((x) & BIT_MASK_R_TXBF0_AID_8197F) << BIT_SHIFT_R_TXBF0_AID_8197F)
+#define BITS_R_TXBF0_AID_8197F                                                 \
+	(BIT_MASK_R_TXBF0_AID_8197F << BIT_SHIFT_R_TXBF0_AID_8197F)
+#define BIT_CLEAR_R_TXBF0_AID_8197F(x) ((x) & (~BITS_R_TXBF0_AID_8197F))
+#define BIT_GET_R_TXBF0_AID_8197F(x)                                           \
+	(((x) >> BIT_SHIFT_R_TXBF0_AID_8197F) & BIT_MASK_R_TXBF0_AID_8197F)
+#define BIT_SET_R_TXBF0_AID_8197F(x, v)                                        \
+	(BIT_CLEAR_R_TXBF0_AID_8197F(x) | BIT_R_TXBF0_AID_8197F(v))
+
+/* 2 REG_DARFRC_8197F */
+
+#define BIT_SHIFT_DARF_RC8_V2_8197F (56 & CPU_OPT_WIDTH)
+#define BIT_MASK_DARF_RC8_V2_8197F 0x3f
+#define BIT_DARF_RC8_V2_8197F(x)                                               \
+	(((x) & BIT_MASK_DARF_RC8_V2_8197F) << BIT_SHIFT_DARF_RC8_V2_8197F)
+#define BITS_DARF_RC8_V2_8197F                                                 \
+	(BIT_MASK_DARF_RC8_V2_8197F << BIT_SHIFT_DARF_RC8_V2_8197F)
+#define BIT_CLEAR_DARF_RC8_V2_8197F(x) ((x) & (~BITS_DARF_RC8_V2_8197F))
+#define BIT_GET_DARF_RC8_V2_8197F(x)                                           \
+	(((x) >> BIT_SHIFT_DARF_RC8_V2_8197F) & BIT_MASK_DARF_RC8_V2_8197F)
+#define BIT_SET_DARF_RC8_V2_8197F(x, v)                                        \
+	(BIT_CLEAR_DARF_RC8_V2_8197F(x) | BIT_DARF_RC8_V2_8197F(v))
+
+#define BIT_SHIFT_DARF_RC7_V2_8197F (48 & CPU_OPT_WIDTH)
+#define BIT_MASK_DARF_RC7_V2_8197F 0x3f
+#define BIT_DARF_RC7_V2_8197F(x)                                               \
+	(((x) & BIT_MASK_DARF_RC7_V2_8197F) << BIT_SHIFT_DARF_RC7_V2_8197F)
+#define BITS_DARF_RC7_V2_8197F                                                 \
+	(BIT_MASK_DARF_RC7_V2_8197F << BIT_SHIFT_DARF_RC7_V2_8197F)
+#define BIT_CLEAR_DARF_RC7_V2_8197F(x) ((x) & (~BITS_DARF_RC7_V2_8197F))
+#define BIT_GET_DARF_RC7_V2_8197F(x)                                           \
+	(((x) >> BIT_SHIFT_DARF_RC7_V2_8197F) & BIT_MASK_DARF_RC7_V2_8197F)
+#define BIT_SET_DARF_RC7_V2_8197F(x, v)                                        \
+	(BIT_CLEAR_DARF_RC7_V2_8197F(x) | BIT_DARF_RC7_V2_8197F(v))
+
+#define BIT_SHIFT_DARF_RC6_V2_8197F (40 & CPU_OPT_WIDTH)
+#define BIT_MASK_DARF_RC6_V2_8197F 0x3f
+#define BIT_DARF_RC6_V2_8197F(x)                                               \
+	(((x) & BIT_MASK_DARF_RC6_V2_8197F) << BIT_SHIFT_DARF_RC6_V2_8197F)
+#define BITS_DARF_RC6_V2_8197F                                                 \
+	(BIT_MASK_DARF_RC6_V2_8197F << BIT_SHIFT_DARF_RC6_V2_8197F)
+#define BIT_CLEAR_DARF_RC6_V2_8197F(x) ((x) & (~BITS_DARF_RC6_V2_8197F))
+#define BIT_GET_DARF_RC6_V2_8197F(x)                                           \
+	(((x) >> BIT_SHIFT_DARF_RC6_V2_8197F) & BIT_MASK_DARF_RC6_V2_8197F)
+#define BIT_SET_DARF_RC6_V2_8197F(x, v)                                        \
+	(BIT_CLEAR_DARF_RC6_V2_8197F(x) | BIT_DARF_RC6_V2_8197F(v))
+
+#define BIT_SHIFT_DARF_RC5_V2_8197F (32 & CPU_OPT_WIDTH)
+#define BIT_MASK_DARF_RC5_V2_8197F 0x3f
+#define BIT_DARF_RC5_V2_8197F(x)                                               \
+	(((x) & BIT_MASK_DARF_RC5_V2_8197F) << BIT_SHIFT_DARF_RC5_V2_8197F)
+#define BITS_DARF_RC5_V2_8197F                                                 \
+	(BIT_MASK_DARF_RC5_V2_8197F << BIT_SHIFT_DARF_RC5_V2_8197F)
+#define BIT_CLEAR_DARF_RC5_V2_8197F(x) ((x) & (~BITS_DARF_RC5_V2_8197F))
+#define BIT_GET_DARF_RC5_V2_8197F(x)                                           \
+	(((x) >> BIT_SHIFT_DARF_RC5_V2_8197F) & BIT_MASK_DARF_RC5_V2_8197F)
+#define BIT_SET_DARF_RC5_V2_8197F(x, v)                                        \
+	(BIT_CLEAR_DARF_RC5_V2_8197F(x) | BIT_DARF_RC5_V2_8197F(v))
+
+#define BIT_SHIFT_DARF_RC4_V1_8197F 24
+#define BIT_MASK_DARF_RC4_V1_8197F 0x3f
+#define BIT_DARF_RC4_V1_8197F(x)                                               \
+	(((x) & BIT_MASK_DARF_RC4_V1_8197F) << BIT_SHIFT_DARF_RC4_V1_8197F)
+#define BITS_DARF_RC4_V1_8197F                                                 \
+	(BIT_MASK_DARF_RC4_V1_8197F << BIT_SHIFT_DARF_RC4_V1_8197F)
+#define BIT_CLEAR_DARF_RC4_V1_8197F(x) ((x) & (~BITS_DARF_RC4_V1_8197F))
+#define BIT_GET_DARF_RC4_V1_8197F(x)                                           \
+	(((x) >> BIT_SHIFT_DARF_RC4_V1_8197F) & BIT_MASK_DARF_RC4_V1_8197F)
+#define BIT_SET_DARF_RC4_V1_8197F(x, v)                                        \
+	(BIT_CLEAR_DARF_RC4_V1_8197F(x) | BIT_DARF_RC4_V1_8197F(v))
+
+#define BIT_SHIFT_DARF_RC3_V1_8197F 16
+#define BIT_MASK_DARF_RC3_V1_8197F 0x3f
+#define BIT_DARF_RC3_V1_8197F(x)                                               \
+	(((x) & BIT_MASK_DARF_RC3_V1_8197F) << BIT_SHIFT_DARF_RC3_V1_8197F)
+#define BITS_DARF_RC3_V1_8197F                                                 \
+	(BIT_MASK_DARF_RC3_V1_8197F << BIT_SHIFT_DARF_RC3_V1_8197F)
+#define BIT_CLEAR_DARF_RC3_V1_8197F(x) ((x) & (~BITS_DARF_RC3_V1_8197F))
+#define BIT_GET_DARF_RC3_V1_8197F(x)                                           \
+	(((x) >> BIT_SHIFT_DARF_RC3_V1_8197F) & BIT_MASK_DARF_RC3_V1_8197F)
+#define BIT_SET_DARF_RC3_V1_8197F(x, v)                                        \
+	(BIT_CLEAR_DARF_RC3_V1_8197F(x) | BIT_DARF_RC3_V1_8197F(v))
+
+#define BIT_SHIFT_DARF_RC2_V1_8197F 8
+#define BIT_MASK_DARF_RC2_V1_8197F 0x3f
+#define BIT_DARF_RC2_V1_8197F(x)                                               \
+	(((x) & BIT_MASK_DARF_RC2_V1_8197F) << BIT_SHIFT_DARF_RC2_V1_8197F)
+#define BITS_DARF_RC2_V1_8197F                                                 \
+	(BIT_MASK_DARF_RC2_V1_8197F << BIT_SHIFT_DARF_RC2_V1_8197F)
+#define BIT_CLEAR_DARF_RC2_V1_8197F(x) ((x) & (~BITS_DARF_RC2_V1_8197F))
+#define BIT_GET_DARF_RC2_V1_8197F(x)                                           \
+	(((x) >> BIT_SHIFT_DARF_RC2_V1_8197F) & BIT_MASK_DARF_RC2_V1_8197F)
+#define BIT_SET_DARF_RC2_V1_8197F(x, v)                                        \
+	(BIT_CLEAR_DARF_RC2_V1_8197F(x) | BIT_DARF_RC2_V1_8197F(v))
+
+#define BIT_SHIFT_DARF_RC1_V1_8197F 0
+#define BIT_MASK_DARF_RC1_V1_8197F 0x3f
+#define BIT_DARF_RC1_V1_8197F(x)                                               \
+	(((x) & BIT_MASK_DARF_RC1_V1_8197F) << BIT_SHIFT_DARF_RC1_V1_8197F)
+#define BITS_DARF_RC1_V1_8197F                                                 \
+	(BIT_MASK_DARF_RC1_V1_8197F << BIT_SHIFT_DARF_RC1_V1_8197F)
+#define BIT_CLEAR_DARF_RC1_V1_8197F(x) ((x) & (~BITS_DARF_RC1_V1_8197F))
+#define BIT_GET_DARF_RC1_V1_8197F(x)                                           \
+	(((x) >> BIT_SHIFT_DARF_RC1_V1_8197F) & BIT_MASK_DARF_RC1_V1_8197F)
+#define BIT_SET_DARF_RC1_V1_8197F(x, v)                                        \
+	(BIT_CLEAR_DARF_RC1_V1_8197F(x) | BIT_DARF_RC1_V1_8197F(v))
+
+/* 2 REG_RARFRC_8197F */
+
+#define BIT_SHIFT_RARF_RC8_8197F (56 & CPU_OPT_WIDTH)
+#define BIT_MASK_RARF_RC8_8197F 0x1f
+#define BIT_RARF_RC8_8197F(x)                                                  \
+	(((x) & BIT_MASK_RARF_RC8_8197F) << BIT_SHIFT_RARF_RC8_8197F)
+#define BITS_RARF_RC8_8197F                                                    \
+	(BIT_MASK_RARF_RC8_8197F << BIT_SHIFT_RARF_RC8_8197F)
+#define BIT_CLEAR_RARF_RC8_8197F(x) ((x) & (~BITS_RARF_RC8_8197F))
+#define BIT_GET_RARF_RC8_8197F(x)                                              \
+	(((x) >> BIT_SHIFT_RARF_RC8_8197F) & BIT_MASK_RARF_RC8_8197F)
+#define BIT_SET_RARF_RC8_8197F(x, v)                                           \
+	(BIT_CLEAR_RARF_RC8_8197F(x) | BIT_RARF_RC8_8197F(v))
+
+#define BIT_SHIFT_RARF_RC7_8197F (48 & CPU_OPT_WIDTH)
+#define BIT_MASK_RARF_RC7_8197F 0x1f
+#define BIT_RARF_RC7_8197F(x)                                                  \
+	(((x) & BIT_MASK_RARF_RC7_8197F) << BIT_SHIFT_RARF_RC7_8197F)
+#define BITS_RARF_RC7_8197F                                                    \
+	(BIT_MASK_RARF_RC7_8197F << BIT_SHIFT_RARF_RC7_8197F)
+#define BIT_CLEAR_RARF_RC7_8197F(x) ((x) & (~BITS_RARF_RC7_8197F))
+#define BIT_GET_RARF_RC7_8197F(x)                                              \
+	(((x) >> BIT_SHIFT_RARF_RC7_8197F) & BIT_MASK_RARF_RC7_8197F)
+#define BIT_SET_RARF_RC7_8197F(x, v)                                           \
+	(BIT_CLEAR_RARF_RC7_8197F(x) | BIT_RARF_RC7_8197F(v))
+
+#define BIT_SHIFT_RARF_RC6_8197F (40 & CPU_OPT_WIDTH)
+#define BIT_MASK_RARF_RC6_8197F 0x1f
+#define BIT_RARF_RC6_8197F(x)                                                  \
+	(((x) & BIT_MASK_RARF_RC6_8197F) << BIT_SHIFT_RARF_RC6_8197F)
+#define BITS_RARF_RC6_8197F                                                    \
+	(BIT_MASK_RARF_RC6_8197F << BIT_SHIFT_RARF_RC6_8197F)
+#define BIT_CLEAR_RARF_RC6_8197F(x) ((x) & (~BITS_RARF_RC6_8197F))
+#define BIT_GET_RARF_RC6_8197F(x)                                              \
+	(((x) >> BIT_SHIFT_RARF_RC6_8197F) & BIT_MASK_RARF_RC6_8197F)
+#define BIT_SET_RARF_RC6_8197F(x, v)                                           \
+	(BIT_CLEAR_RARF_RC6_8197F(x) | BIT_RARF_RC6_8197F(v))
+
+#define BIT_SHIFT_RARF_RC5_8197F (32 & CPU_OPT_WIDTH)
+#define BIT_MASK_RARF_RC5_8197F 0x1f
+#define BIT_RARF_RC5_8197F(x)                                                  \
+	(((x) & BIT_MASK_RARF_RC5_8197F) << BIT_SHIFT_RARF_RC5_8197F)
+#define BITS_RARF_RC5_8197F                                                    \
+	(BIT_MASK_RARF_RC5_8197F << BIT_SHIFT_RARF_RC5_8197F)
+#define BIT_CLEAR_RARF_RC5_8197F(x) ((x) & (~BITS_RARF_RC5_8197F))
+#define BIT_GET_RARF_RC5_8197F(x)                                              \
+	(((x) >> BIT_SHIFT_RARF_RC5_8197F) & BIT_MASK_RARF_RC5_8197F)
+#define BIT_SET_RARF_RC5_8197F(x, v)                                           \
+	(BIT_CLEAR_RARF_RC5_8197F(x) | BIT_RARF_RC5_8197F(v))
+
+#define BIT_SHIFT_RARF_RC4_8197F 24
+#define BIT_MASK_RARF_RC4_8197F 0x1f
+#define BIT_RARF_RC4_8197F(x)                                                  \
+	(((x) & BIT_MASK_RARF_RC4_8197F) << BIT_SHIFT_RARF_RC4_8197F)
+#define BITS_RARF_RC4_8197F                                                    \
+	(BIT_MASK_RARF_RC4_8197F << BIT_SHIFT_RARF_RC4_8197F)
+#define BIT_CLEAR_RARF_RC4_8197F(x) ((x) & (~BITS_RARF_RC4_8197F))
+#define BIT_GET_RARF_RC4_8197F(x)                                              \
+	(((x) >> BIT_SHIFT_RARF_RC4_8197F) & BIT_MASK_RARF_RC4_8197F)
+#define BIT_SET_RARF_RC4_8197F(x, v)                                           \
+	(BIT_CLEAR_RARF_RC4_8197F(x) | BIT_RARF_RC4_8197F(v))
+
+#define BIT_SHIFT_RARF_RC3_8197F 16
+#define BIT_MASK_RARF_RC3_8197F 0x1f
+#define BIT_RARF_RC3_8197F(x)                                                  \
+	(((x) & BIT_MASK_RARF_RC3_8197F) << BIT_SHIFT_RARF_RC3_8197F)
+#define BITS_RARF_RC3_8197F                                                    \
+	(BIT_MASK_RARF_RC3_8197F << BIT_SHIFT_RARF_RC3_8197F)
+#define BIT_CLEAR_RARF_RC3_8197F(x) ((x) & (~BITS_RARF_RC3_8197F))
+#define BIT_GET_RARF_RC3_8197F(x)                                              \
+	(((x) >> BIT_SHIFT_RARF_RC3_8197F) & BIT_MASK_RARF_RC3_8197F)
+#define BIT_SET_RARF_RC3_8197F(x, v)                                           \
+	(BIT_CLEAR_RARF_RC3_8197F(x) | BIT_RARF_RC3_8197F(v))
+
+#define BIT_SHIFT_RARF_RC2_8197F 8
+#define BIT_MASK_RARF_RC2_8197F 0x1f
+#define BIT_RARF_RC2_8197F(x)                                                  \
+	(((x) & BIT_MASK_RARF_RC2_8197F) << BIT_SHIFT_RARF_RC2_8197F)
+#define BITS_RARF_RC2_8197F                                                    \
+	(BIT_MASK_RARF_RC2_8197F << BIT_SHIFT_RARF_RC2_8197F)
+#define BIT_CLEAR_RARF_RC2_8197F(x) ((x) & (~BITS_RARF_RC2_8197F))
+#define BIT_GET_RARF_RC2_8197F(x)                                              \
+	(((x) >> BIT_SHIFT_RARF_RC2_8197F) & BIT_MASK_RARF_RC2_8197F)
+#define BIT_SET_RARF_RC2_8197F(x, v)                                           \
+	(BIT_CLEAR_RARF_RC2_8197F(x) | BIT_RARF_RC2_8197F(v))
+
+#define BIT_SHIFT_RARF_RC1_8197F 0
+#define BIT_MASK_RARF_RC1_8197F 0x1f
+#define BIT_RARF_RC1_8197F(x)                                                  \
+	(((x) & BIT_MASK_RARF_RC1_8197F) << BIT_SHIFT_RARF_RC1_8197F)
+#define BITS_RARF_RC1_8197F                                                    \
+	(BIT_MASK_RARF_RC1_8197F << BIT_SHIFT_RARF_RC1_8197F)
+#define BIT_CLEAR_RARF_RC1_8197F(x) ((x) & (~BITS_RARF_RC1_8197F))
+#define BIT_GET_RARF_RC1_8197F(x)                                              \
+	(((x) >> BIT_SHIFT_RARF_RC1_8197F) & BIT_MASK_RARF_RC1_8197F)
+#define BIT_SET_RARF_RC1_8197F(x, v)                                           \
+	(BIT_CLEAR_RARF_RC1_8197F(x) | BIT_RARF_RC1_8197F(v))
+
+/* 2 REG_RRSR_8197F */
+#define BIT_EN_VHTBW_FALL_8197F BIT(31)
+#define BIT_EN_HTBW_FALL_8197F BIT(30)
+
+#define BIT_SHIFT_RRSR_RSC_8197F 21
+#define BIT_MASK_RRSR_RSC_8197F 0x3
+#define BIT_RRSR_RSC_8197F(x)                                                  \
+	(((x) & BIT_MASK_RRSR_RSC_8197F) << BIT_SHIFT_RRSR_RSC_8197F)
+#define BITS_RRSR_RSC_8197F                                                    \
+	(BIT_MASK_RRSR_RSC_8197F << BIT_SHIFT_RRSR_RSC_8197F)
+#define BIT_CLEAR_RRSR_RSC_8197F(x) ((x) & (~BITS_RRSR_RSC_8197F))
+#define BIT_GET_RRSR_RSC_8197F(x)                                              \
+	(((x) >> BIT_SHIFT_RRSR_RSC_8197F) & BIT_MASK_RRSR_RSC_8197F)
+#define BIT_SET_RRSR_RSC_8197F(x, v)                                           \
+	(BIT_CLEAR_RRSR_RSC_8197F(x) | BIT_RRSR_RSC_8197F(v))
+
+#define BIT_RRSR_BW_8197F BIT(20)
+
+#define BIT_SHIFT_RRSC_BITMAP_8197F 0
+#define BIT_MASK_RRSC_BITMAP_8197F 0xfffff
+#define BIT_RRSC_BITMAP_8197F(x)                                               \
+	(((x) & BIT_MASK_RRSC_BITMAP_8197F) << BIT_SHIFT_RRSC_BITMAP_8197F)
+#define BITS_RRSC_BITMAP_8197F                                                 \
+	(BIT_MASK_RRSC_BITMAP_8197F << BIT_SHIFT_RRSC_BITMAP_8197F)
+#define BIT_CLEAR_RRSC_BITMAP_8197F(x) ((x) & (~BITS_RRSC_BITMAP_8197F))
+#define BIT_GET_RRSC_BITMAP_8197F(x)                                           \
+	(((x) >> BIT_SHIFT_RRSC_BITMAP_8197F) & BIT_MASK_RRSC_BITMAP_8197F)
+#define BIT_SET_RRSC_BITMAP_8197F(x, v)                                        \
+	(BIT_CLEAR_RRSC_BITMAP_8197F(x) | BIT_RRSC_BITMAP_8197F(v))
+
+/* 2 REG_ARFR0_8197F */
+
+#define BIT_SHIFT_ARFR0_V1_8197F 0
+#define BIT_MASK_ARFR0_V1_8197F 0xffffffffffffffffL
+#define BIT_ARFR0_V1_8197F(x)                                                  \
+	(((x) & BIT_MASK_ARFR0_V1_8197F) << BIT_SHIFT_ARFR0_V1_8197F)
+#define BITS_ARFR0_V1_8197F                                                    \
+	(BIT_MASK_ARFR0_V1_8197F << BIT_SHIFT_ARFR0_V1_8197F)
+#define BIT_CLEAR_ARFR0_V1_8197F(x) ((x) & (~BITS_ARFR0_V1_8197F))
+#define BIT_GET_ARFR0_V1_8197F(x)                                              \
+	(((x) >> BIT_SHIFT_ARFR0_V1_8197F) & BIT_MASK_ARFR0_V1_8197F)
+#define BIT_SET_ARFR0_V1_8197F(x, v)                                           \
+	(BIT_CLEAR_ARFR0_V1_8197F(x) | BIT_ARFR0_V1_8197F(v))
+
+/* 2 REG_ARFR1_V1_8197F */
+
+#define BIT_SHIFT_ARFR1_V1_8197F 0
+#define BIT_MASK_ARFR1_V1_8197F 0xffffffffffffffffL
+#define BIT_ARFR1_V1_8197F(x)                                                  \
+	(((x) & BIT_MASK_ARFR1_V1_8197F) << BIT_SHIFT_ARFR1_V1_8197F)
+#define BITS_ARFR1_V1_8197F                                                    \
+	(BIT_MASK_ARFR1_V1_8197F << BIT_SHIFT_ARFR1_V1_8197F)
+#define BIT_CLEAR_ARFR1_V1_8197F(x) ((x) & (~BITS_ARFR1_V1_8197F))
+#define BIT_GET_ARFR1_V1_8197F(x)                                              \
+	(((x) >> BIT_SHIFT_ARFR1_V1_8197F) & BIT_MASK_ARFR1_V1_8197F)
+#define BIT_SET_ARFR1_V1_8197F(x, v)                                           \
+	(BIT_CLEAR_ARFR1_V1_8197F(x) | BIT_ARFR1_V1_8197F(v))
+
+/* 2 REG_CCK_CHECK_8197F */
+#define BIT_CHECK_CCK_EN_8197F BIT(7)
+#define BIT_EN_BCN_PKT_REL_8197F BIT(6)
+#define BIT_BCN_PORT_SEL_8197F BIT(5)
+#define BIT_MOREDATA_BYPASS_8197F BIT(4)
+#define BIT_EN_CLR_CMD_REL_BCN_PKT_8197F BIT(3)
+#define BIT_R_EN_SET_MOREDATA_8197F BIT(2)
+#define BIT__R_DIS_CLEAR_MACID_RELEASE_8197F BIT(1)
+#define BIT__R_MACID_RELEASE_EN_8197F BIT(0)
+
+/* 2 REG_AMPDU_MAX_TIME_V1_8197F */
+
+#define BIT_SHIFT_AMPDU_MAX_TIME_8197F 0
+#define BIT_MASK_AMPDU_MAX_TIME_8197F 0xff
+#define BIT_AMPDU_MAX_TIME_8197F(x)                                            \
+	(((x) & BIT_MASK_AMPDU_MAX_TIME_8197F)                                 \
+	 << BIT_SHIFT_AMPDU_MAX_TIME_8197F)
+#define BITS_AMPDU_MAX_TIME_8197F                                              \
+	(BIT_MASK_AMPDU_MAX_TIME_8197F << BIT_SHIFT_AMPDU_MAX_TIME_8197F)
+#define BIT_CLEAR_AMPDU_MAX_TIME_8197F(x) ((x) & (~BITS_AMPDU_MAX_TIME_8197F))
+#define BIT_GET_AMPDU_MAX_TIME_8197F(x)                                        \
+	(((x) >> BIT_SHIFT_AMPDU_MAX_TIME_8197F) &                             \
+	 BIT_MASK_AMPDU_MAX_TIME_8197F)
+#define BIT_SET_AMPDU_MAX_TIME_8197F(x, v)                                     \
+	(BIT_CLEAR_AMPDU_MAX_TIME_8197F(x) | BIT_AMPDU_MAX_TIME_8197F(v))
+
+/* 2 REG_BCNQ1_BDNY_V1_8197F */
+
+#define BIT_SHIFT_BCNQ1_PGBNDY_V1_8197F 0
+#define BIT_MASK_BCNQ1_PGBNDY_V1_8197F 0xfff
+#define BIT_BCNQ1_PGBNDY_V1_8197F(x)                                           \
+	(((x) & BIT_MASK_BCNQ1_PGBNDY_V1_8197F)                                \
+	 << BIT_SHIFT_BCNQ1_PGBNDY_V1_8197F)
+#define BITS_BCNQ1_PGBNDY_V1_8197F                                             \
+	(BIT_MASK_BCNQ1_PGBNDY_V1_8197F << BIT_SHIFT_BCNQ1_PGBNDY_V1_8197F)
+#define BIT_CLEAR_BCNQ1_PGBNDY_V1_8197F(x) ((x) & (~BITS_BCNQ1_PGBNDY_V1_8197F))
+#define BIT_GET_BCNQ1_PGBNDY_V1_8197F(x)                                       \
+	(((x) >> BIT_SHIFT_BCNQ1_PGBNDY_V1_8197F) &                            \
+	 BIT_MASK_BCNQ1_PGBNDY_V1_8197F)
+#define BIT_SET_BCNQ1_PGBNDY_V1_8197F(x, v)                                    \
+	(BIT_CLEAR_BCNQ1_PGBNDY_V1_8197F(x) | BIT_BCNQ1_PGBNDY_V1_8197F(v))
+
+/* 2 REG_AMPDU_MAX_LENGTH_8197F */
+
+#define BIT_SHIFT_AMPDU_MAX_LENGTH_8197F 0
+#define BIT_MASK_AMPDU_MAX_LENGTH_8197F 0xffffffffL
+#define BIT_AMPDU_MAX_LENGTH_8197F(x)                                          \
+	(((x) & BIT_MASK_AMPDU_MAX_LENGTH_8197F)                               \
+	 << BIT_SHIFT_AMPDU_MAX_LENGTH_8197F)
+#define BITS_AMPDU_MAX_LENGTH_8197F                                            \
+	(BIT_MASK_AMPDU_MAX_LENGTH_8197F << BIT_SHIFT_AMPDU_MAX_LENGTH_8197F)
+#define BIT_CLEAR_AMPDU_MAX_LENGTH_8197F(x)                                    \
+	((x) & (~BITS_AMPDU_MAX_LENGTH_8197F))
+#define BIT_GET_AMPDU_MAX_LENGTH_8197F(x)                                      \
+	(((x) >> BIT_SHIFT_AMPDU_MAX_LENGTH_8197F) &                           \
+	 BIT_MASK_AMPDU_MAX_LENGTH_8197F)
+#define BIT_SET_AMPDU_MAX_LENGTH_8197F(x, v)                                   \
+	(BIT_CLEAR_AMPDU_MAX_LENGTH_8197F(x) | BIT_AMPDU_MAX_LENGTH_8197F(v))
+
+/* 2 REG_ACQ_STOP_8197F */
+#define BIT_AC7Q_STOP_8197F BIT(7)
+#define BIT_AC6Q_STOP_8197F BIT(6)
+#define BIT_AC5Q_STOP_8197F BIT(5)
+#define BIT_AC4Q_STOP_8197F BIT(4)
+#define BIT_AC3Q_STOP_8197F BIT(3)
+#define BIT_AC2Q_STOP_8197F BIT(2)
+#define BIT_AC1Q_STOP_8197F BIT(1)
+#define BIT_AC0Q_STOP_8197F BIT(0)
+
+/* 2 REG_NDPA_RATE_8197F */
+
+#define BIT_SHIFT_R_NDPA_RATE_V1_8197F 0
+#define BIT_MASK_R_NDPA_RATE_V1_8197F 0xff
+#define BIT_R_NDPA_RATE_V1_8197F(x)                                            \
+	(((x) & BIT_MASK_R_NDPA_RATE_V1_8197F)                                 \
+	 << BIT_SHIFT_R_NDPA_RATE_V1_8197F)
+#define BITS_R_NDPA_RATE_V1_8197F                                              \
+	(BIT_MASK_R_NDPA_RATE_V1_8197F << BIT_SHIFT_R_NDPA_RATE_V1_8197F)
+#define BIT_CLEAR_R_NDPA_RATE_V1_8197F(x) ((x) & (~BITS_R_NDPA_RATE_V1_8197F))
+#define BIT_GET_R_NDPA_RATE_V1_8197F(x)                                        \
+	(((x) >> BIT_SHIFT_R_NDPA_RATE_V1_8197F) &                             \
+	 BIT_MASK_R_NDPA_RATE_V1_8197F)
+#define BIT_SET_R_NDPA_RATE_V1_8197F(x, v)                                     \
+	(BIT_CLEAR_R_NDPA_RATE_V1_8197F(x) | BIT_R_NDPA_RATE_V1_8197F(v))
+
+/* 2 REG_TX_HANG_CTRL_8197F */
+#define BIT_R_EN_GNT_BT_AWAKE_8197F BIT(3)
+#define BIT_EN_EOF_V1_8197F BIT(2)
+#define BIT_DIS_OQT_BLOCK_8197F BIT(1)
+#define BIT_SEARCH_QUEUE_EN_8197F BIT(0)
+
+/* 2 REG_NDPA_OPT_CTRL_8197F */
+#define BIT_R_DIS_MACID_RELEASE_RTY_8197F BIT(5)
+
+#define BIT_SHIFT_BW_SIGTA_8197F 3
+#define BIT_MASK_BW_SIGTA_8197F 0x3
+#define BIT_BW_SIGTA_8197F(x)                                                  \
+	(((x) & BIT_MASK_BW_SIGTA_8197F) << BIT_SHIFT_BW_SIGTA_8197F)
+#define BITS_BW_SIGTA_8197F                                                    \
+	(BIT_MASK_BW_SIGTA_8197F << BIT_SHIFT_BW_SIGTA_8197F)
+#define BIT_CLEAR_BW_SIGTA_8197F(x) ((x) & (~BITS_BW_SIGTA_8197F))
+#define BIT_GET_BW_SIGTA_8197F(x)                                              \
+	(((x) >> BIT_SHIFT_BW_SIGTA_8197F) & BIT_MASK_BW_SIGTA_8197F)
+#define BIT_SET_BW_SIGTA_8197F(x, v)                                           \
+	(BIT_CLEAR_BW_SIGTA_8197F(x) | BIT_BW_SIGTA_8197F(v))
+
+#define BIT_EN_BAR_SIGTA_8197F BIT(2)
+
+#define BIT_SHIFT_R_NDPA_BW_8197F 0
+#define BIT_MASK_R_NDPA_BW_8197F 0x3
+#define BIT_R_NDPA_BW_8197F(x)                                                 \
+	(((x) & BIT_MASK_R_NDPA_BW_8197F) << BIT_SHIFT_R_NDPA_BW_8197F)
+#define BITS_R_NDPA_BW_8197F                                                   \
+	(BIT_MASK_R_NDPA_BW_8197F << BIT_SHIFT_R_NDPA_BW_8197F)
+#define BIT_CLEAR_R_NDPA_BW_8197F(x) ((x) & (~BITS_R_NDPA_BW_8197F))
+#define BIT_GET_R_NDPA_BW_8197F(x)                                             \
+	(((x) >> BIT_SHIFT_R_NDPA_BW_8197F) & BIT_MASK_R_NDPA_BW_8197F)
+#define BIT_SET_R_NDPA_BW_8197F(x, v)                                          \
+	(BIT_CLEAR_R_NDPA_BW_8197F(x) | BIT_R_NDPA_BW_8197F(v))
+
+/* 2 REG_NOT_VALID_8197F */
+
+/* 2 REG_NOT_VALID_8197F */
+
+/* 2 REG_RD_RESP_PKT_TH_8197F */
+
+#define BIT_SHIFT_RD_RESP_PKT_TH_V1_8197F 0
+#define BIT_MASK_RD_RESP_PKT_TH_V1_8197F 0x3f
+#define BIT_RD_RESP_PKT_TH_V1_8197F(x)                                         \
+	(((x) & BIT_MASK_RD_RESP_PKT_TH_V1_8197F)                              \
+	 << BIT_SHIFT_RD_RESP_PKT_TH_V1_8197F)
+#define BITS_RD_RESP_PKT_TH_V1_8197F                                           \
+	(BIT_MASK_RD_RESP_PKT_TH_V1_8197F << BIT_SHIFT_RD_RESP_PKT_TH_V1_8197F)
+#define BIT_CLEAR_RD_RESP_PKT_TH_V1_8197F(x)                                   \
+	((x) & (~BITS_RD_RESP_PKT_TH_V1_8197F))
+#define BIT_GET_RD_RESP_PKT_TH_V1_8197F(x)                                     \
+	(((x) >> BIT_SHIFT_RD_RESP_PKT_TH_V1_8197F) &                          \
+	 BIT_MASK_RD_RESP_PKT_TH_V1_8197F)
+#define BIT_SET_RD_RESP_PKT_TH_V1_8197F(x, v)                                  \
+	(BIT_CLEAR_RD_RESP_PKT_TH_V1_8197F(x) | BIT_RD_RESP_PKT_TH_V1_8197F(v))
+
+/* 2 REG_CMDQ_INFO_8197F */
+
+#define BIT_SHIFT_PKT_NUM_8197F 23
+#define BIT_MASK_PKT_NUM_8197F 0x1ff
+#define BIT_PKT_NUM_8197F(x)                                                   \
+	(((x) & BIT_MASK_PKT_NUM_8197F) << BIT_SHIFT_PKT_NUM_8197F)
+#define BITS_PKT_NUM_8197F (BIT_MASK_PKT_NUM_8197F << BIT_SHIFT_PKT_NUM_8197F)
+#define BIT_CLEAR_PKT_NUM_8197F(x) ((x) & (~BITS_PKT_NUM_8197F))
+#define BIT_GET_PKT_NUM_8197F(x)                                               \
+	(((x) >> BIT_SHIFT_PKT_NUM_8197F) & BIT_MASK_PKT_NUM_8197F)
+#define BIT_SET_PKT_NUM_8197F(x, v)                                            \
+	(BIT_CLEAR_PKT_NUM_8197F(x) | BIT_PKT_NUM_8197F(v))
+
+#define BIT_TIDEMPTY_CMDQ_V1_8197F BIT(22)
+
+#define BIT_SHIFT_TAIL_PKT_CMDQ_V2_8197F 11
+#define BIT_MASK_TAIL_PKT_CMDQ_V2_8197F 0x7ff
+#define BIT_TAIL_PKT_CMDQ_V2_8197F(x)                                          \
+	(((x) & BIT_MASK_TAIL_PKT_CMDQ_V2_8197F)                               \
+	 << BIT_SHIFT_TAIL_PKT_CMDQ_V2_8197F)
+#define BITS_TAIL_PKT_CMDQ_V2_8197F                                            \
+	(BIT_MASK_TAIL_PKT_CMDQ_V2_8197F << BIT_SHIFT_TAIL_PKT_CMDQ_V2_8197F)
+#define BIT_CLEAR_TAIL_PKT_CMDQ_V2_8197F(x)                                    \
+	((x) & (~BITS_TAIL_PKT_CMDQ_V2_8197F))
+#define BIT_GET_TAIL_PKT_CMDQ_V2_8197F(x)                                      \
+	(((x) >> BIT_SHIFT_TAIL_PKT_CMDQ_V2_8197F) &                           \
+	 BIT_MASK_TAIL_PKT_CMDQ_V2_8197F)
+#define BIT_SET_TAIL_PKT_CMDQ_V2_8197F(x, v)                                   \
+	(BIT_CLEAR_TAIL_PKT_CMDQ_V2_8197F(x) | BIT_TAIL_PKT_CMDQ_V2_8197F(v))
+
+#define BIT_SHIFT_HEAD_PKT_CMDQ_V1_8197F 0
+#define BIT_MASK_HEAD_PKT_CMDQ_V1_8197F 0x7ff
+#define BIT_HEAD_PKT_CMDQ_V1_8197F(x)                                          \
+	(((x) & BIT_MASK_HEAD_PKT_CMDQ_V1_8197F)                               \
+	 << BIT_SHIFT_HEAD_PKT_CMDQ_V1_8197F)
+#define BITS_HEAD_PKT_CMDQ_V1_8197F                                            \
+	(BIT_MASK_HEAD_PKT_CMDQ_V1_8197F << BIT_SHIFT_HEAD_PKT_CMDQ_V1_8197F)
+#define BIT_CLEAR_HEAD_PKT_CMDQ_V1_8197F(x)                                    \
+	((x) & (~BITS_HEAD_PKT_CMDQ_V1_8197F))
+#define BIT_GET_HEAD_PKT_CMDQ_V1_8197F(x)                                      \
+	(((x) >> BIT_SHIFT_HEAD_PKT_CMDQ_V1_8197F) &                           \
+	 BIT_MASK_HEAD_PKT_CMDQ_V1_8197F)
+#define BIT_SET_HEAD_PKT_CMDQ_V1_8197F(x, v)                                   \
+	(BIT_CLEAR_HEAD_PKT_CMDQ_V1_8197F(x) | BIT_HEAD_PKT_CMDQ_V1_8197F(v))
+
+/* 2 REG_Q4_INFO_8197F */
+
+#define BIT_SHIFT_QUEUEMACID_Q4_V1_8197F 25
+#define BIT_MASK_QUEUEMACID_Q4_V1_8197F 0x7f
+#define BIT_QUEUEMACID_Q4_V1_8197F(x)                                          \
+	(((x) & BIT_MASK_QUEUEMACID_Q4_V1_8197F)                               \
+	 << BIT_SHIFT_QUEUEMACID_Q4_V1_8197F)
+#define BITS_QUEUEMACID_Q4_V1_8197F                                            \
+	(BIT_MASK_QUEUEMACID_Q4_V1_8197F << BIT_SHIFT_QUEUEMACID_Q4_V1_8197F)
+#define BIT_CLEAR_QUEUEMACID_Q4_V1_8197F(x)                                    \
+	((x) & (~BITS_QUEUEMACID_Q4_V1_8197F))
+#define BIT_GET_QUEUEMACID_Q4_V1_8197F(x)                                      \
+	(((x) >> BIT_SHIFT_QUEUEMACID_Q4_V1_8197F) &                           \
+	 BIT_MASK_QUEUEMACID_Q4_V1_8197F)
+#define BIT_SET_QUEUEMACID_Q4_V1_8197F(x, v)                                   \
+	(BIT_CLEAR_QUEUEMACID_Q4_V1_8197F(x) | BIT_QUEUEMACID_Q4_V1_8197F(v))
+
+#define BIT_SHIFT_QUEUEAC_Q4_V1_8197F 23
+#define BIT_MASK_QUEUEAC_Q4_V1_8197F 0x3
+#define BIT_QUEUEAC_Q4_V1_8197F(x)                                             \
+	(((x) & BIT_MASK_QUEUEAC_Q4_V1_8197F) << BIT_SHIFT_QUEUEAC_Q4_V1_8197F)
+#define BITS_QUEUEAC_Q4_V1_8197F                                               \
+	(BIT_MASK_QUEUEAC_Q4_V1_8197F << BIT_SHIFT_QUEUEAC_Q4_V1_8197F)
+#define BIT_CLEAR_QUEUEAC_Q4_V1_8197F(x) ((x) & (~BITS_QUEUEAC_Q4_V1_8197F))
+#define BIT_GET_QUEUEAC_Q4_V1_8197F(x)                                         \
+	(((x) >> BIT_SHIFT_QUEUEAC_Q4_V1_8197F) & BIT_MASK_QUEUEAC_Q4_V1_8197F)
+#define BIT_SET_QUEUEAC_Q4_V1_8197F(x, v)                                      \
+	(BIT_CLEAR_QUEUEAC_Q4_V1_8197F(x) | BIT_QUEUEAC_Q4_V1_8197F(v))
+
+#define BIT_TIDEMPTY_Q4_V1_8197F BIT(22)
+
+#define BIT_SHIFT_TAIL_PKT_Q4_V2_8197F 11
+#define BIT_MASK_TAIL_PKT_Q4_V2_8197F 0x7ff
+#define BIT_TAIL_PKT_Q4_V2_8197F(x)                                            \
+	(((x) & BIT_MASK_TAIL_PKT_Q4_V2_8197F)                                 \
+	 << BIT_SHIFT_TAIL_PKT_Q4_V2_8197F)
+#define BITS_TAIL_PKT_Q4_V2_8197F                                              \
+	(BIT_MASK_TAIL_PKT_Q4_V2_8197F << BIT_SHIFT_TAIL_PKT_Q4_V2_8197F)
+#define BIT_CLEAR_TAIL_PKT_Q4_V2_8197F(x) ((x) & (~BITS_TAIL_PKT_Q4_V2_8197F))
+#define BIT_GET_TAIL_PKT_Q4_V2_8197F(x)                                        \
+	(((x) >> BIT_SHIFT_TAIL_PKT_Q4_V2_8197F) &                             \
+	 BIT_MASK_TAIL_PKT_Q4_V2_8197F)
+#define BIT_SET_TAIL_PKT_Q4_V2_8197F(x, v)                                     \
+	(BIT_CLEAR_TAIL_PKT_Q4_V2_8197F(x) | BIT_TAIL_PKT_Q4_V2_8197F(v))
+
+#define BIT_SHIFT_HEAD_PKT_Q4_V1_8197F 0
+#define BIT_MASK_HEAD_PKT_Q4_V1_8197F 0x7ff
+#define BIT_HEAD_PKT_Q4_V1_8197F(x)                                            \
+	(((x) & BIT_MASK_HEAD_PKT_Q4_V1_8197F)                                 \
+	 << BIT_SHIFT_HEAD_PKT_Q4_V1_8197F)
+#define BITS_HEAD_PKT_Q4_V1_8197F                                              \
+	(BIT_MASK_HEAD_PKT_Q4_V1_8197F << BIT_SHIFT_HEAD_PKT_Q4_V1_8197F)
+#define BIT_CLEAR_HEAD_PKT_Q4_V1_8197F(x) ((x) & (~BITS_HEAD_PKT_Q4_V1_8197F))
+#define BIT_GET_HEAD_PKT_Q4_V1_8197F(x)                                        \
+	(((x) >> BIT_SHIFT_HEAD_PKT_Q4_V1_8197F) &                             \
+	 BIT_MASK_HEAD_PKT_Q4_V1_8197F)
+#define BIT_SET_HEAD_PKT_Q4_V1_8197F(x, v)                                     \
+	(BIT_CLEAR_HEAD_PKT_Q4_V1_8197F(x) | BIT_HEAD_PKT_Q4_V1_8197F(v))
+
+/* 2 REG_Q5_INFO_8197F */
+
+#define BIT_SHIFT_QUEUEMACID_Q5_V1_8197F 25
+#define BIT_MASK_QUEUEMACID_Q5_V1_8197F 0x7f
+#define BIT_QUEUEMACID_Q5_V1_8197F(x)                                          \
+	(((x) & BIT_MASK_QUEUEMACID_Q5_V1_8197F)                               \
+	 << BIT_SHIFT_QUEUEMACID_Q5_V1_8197F)
+#define BITS_QUEUEMACID_Q5_V1_8197F                                            \
+	(BIT_MASK_QUEUEMACID_Q5_V1_8197F << BIT_SHIFT_QUEUEMACID_Q5_V1_8197F)
+#define BIT_CLEAR_QUEUEMACID_Q5_V1_8197F(x)                                    \
+	((x) & (~BITS_QUEUEMACID_Q5_V1_8197F))
+#define BIT_GET_QUEUEMACID_Q5_V1_8197F(x)                                      \
+	(((x) >> BIT_SHIFT_QUEUEMACID_Q5_V1_8197F) &                           \
+	 BIT_MASK_QUEUEMACID_Q5_V1_8197F)
+#define BIT_SET_QUEUEMACID_Q5_V1_8197F(x, v)                                   \
+	(BIT_CLEAR_QUEUEMACID_Q5_V1_8197F(x) | BIT_QUEUEMACID_Q5_V1_8197F(v))
+
+#define BIT_SHIFT_QUEUEAC_Q5_V1_8197F 23
+#define BIT_MASK_QUEUEAC_Q5_V1_8197F 0x3
+#define BIT_QUEUEAC_Q5_V1_8197F(x)                                             \
+	(((x) & BIT_MASK_QUEUEAC_Q5_V1_8197F) << BIT_SHIFT_QUEUEAC_Q5_V1_8197F)
+#define BITS_QUEUEAC_Q5_V1_8197F                                               \
+	(BIT_MASK_QUEUEAC_Q5_V1_8197F << BIT_SHIFT_QUEUEAC_Q5_V1_8197F)
+#define BIT_CLEAR_QUEUEAC_Q5_V1_8197F(x) ((x) & (~BITS_QUEUEAC_Q5_V1_8197F))
+#define BIT_GET_QUEUEAC_Q5_V1_8197F(x)                                         \
+	(((x) >> BIT_SHIFT_QUEUEAC_Q5_V1_8197F) & BIT_MASK_QUEUEAC_Q5_V1_8197F)
+#define BIT_SET_QUEUEAC_Q5_V1_8197F(x, v)                                      \
+	(BIT_CLEAR_QUEUEAC_Q5_V1_8197F(x) | BIT_QUEUEAC_Q5_V1_8197F(v))
+
+#define BIT_TIDEMPTY_Q5_V1_8197F BIT(22)
+
+#define BIT_SHIFT_TAIL_PKT_Q5_V2_8197F 11
+#define BIT_MASK_TAIL_PKT_Q5_V2_8197F 0x7ff
+#define BIT_TAIL_PKT_Q5_V2_8197F(x)                                            \
+	(((x) & BIT_MASK_TAIL_PKT_Q5_V2_8197F)                                 \
+	 << BIT_SHIFT_TAIL_PKT_Q5_V2_8197F)
+#define BITS_TAIL_PKT_Q5_V2_8197F                                              \
+	(BIT_MASK_TAIL_PKT_Q5_V2_8197F << BIT_SHIFT_TAIL_PKT_Q5_V2_8197F)
+#define BIT_CLEAR_TAIL_PKT_Q5_V2_8197F(x) ((x) & (~BITS_TAIL_PKT_Q5_V2_8197F))
+#define BIT_GET_TAIL_PKT_Q5_V2_8197F(x)                                        \
+	(((x) >> BIT_SHIFT_TAIL_PKT_Q5_V2_8197F) &                             \
+	 BIT_MASK_TAIL_PKT_Q5_V2_8197F)
+#define BIT_SET_TAIL_PKT_Q5_V2_8197F(x, v)                                     \
+	(BIT_CLEAR_TAIL_PKT_Q5_V2_8197F(x) | BIT_TAIL_PKT_Q5_V2_8197F(v))
+
+#define BIT_SHIFT_HEAD_PKT_Q5_V1_8197F 0
+#define BIT_MASK_HEAD_PKT_Q5_V1_8197F 0x7ff
+#define BIT_HEAD_PKT_Q5_V1_8197F(x)                                            \
+	(((x) & BIT_MASK_HEAD_PKT_Q5_V1_8197F)                                 \
+	 << BIT_SHIFT_HEAD_PKT_Q5_V1_8197F)
+#define BITS_HEAD_PKT_Q5_V1_8197F                                              \
+	(BIT_MASK_HEAD_PKT_Q5_V1_8197F << BIT_SHIFT_HEAD_PKT_Q5_V1_8197F)
+#define BIT_CLEAR_HEAD_PKT_Q5_V1_8197F(x) ((x) & (~BITS_HEAD_PKT_Q5_V1_8197F))
+#define BIT_GET_HEAD_PKT_Q5_V1_8197F(x)                                        \
+	(((x) >> BIT_SHIFT_HEAD_PKT_Q5_V1_8197F) &                             \
+	 BIT_MASK_HEAD_PKT_Q5_V1_8197F)
+#define BIT_SET_HEAD_PKT_Q5_V1_8197F(x, v)                                     \
+	(BIT_CLEAR_HEAD_PKT_Q5_V1_8197F(x) | BIT_HEAD_PKT_Q5_V1_8197F(v))
+
+/* 2 REG_Q6_INFO_8197F */
+
+#define BIT_SHIFT_QUEUEMACID_Q6_V1_8197F 25
+#define BIT_MASK_QUEUEMACID_Q6_V1_8197F 0x7f
+#define BIT_QUEUEMACID_Q6_V1_8197F(x)                                          \
+	(((x) & BIT_MASK_QUEUEMACID_Q6_V1_8197F)                               \
+	 << BIT_SHIFT_QUEUEMACID_Q6_V1_8197F)
+#define BITS_QUEUEMACID_Q6_V1_8197F                                            \
+	(BIT_MASK_QUEUEMACID_Q6_V1_8197F << BIT_SHIFT_QUEUEMACID_Q6_V1_8197F)
+#define BIT_CLEAR_QUEUEMACID_Q6_V1_8197F(x)                                    \
+	((x) & (~BITS_QUEUEMACID_Q6_V1_8197F))
+#define BIT_GET_QUEUEMACID_Q6_V1_8197F(x)                                      \
+	(((x) >> BIT_SHIFT_QUEUEMACID_Q6_V1_8197F) &                           \
+	 BIT_MASK_QUEUEMACID_Q6_V1_8197F)
+#define BIT_SET_QUEUEMACID_Q6_V1_8197F(x, v)                                   \
+	(BIT_CLEAR_QUEUEMACID_Q6_V1_8197F(x) | BIT_QUEUEMACID_Q6_V1_8197F(v))
+
+#define BIT_SHIFT_QUEUEAC_Q6_V1_8197F 23
+#define BIT_MASK_QUEUEAC_Q6_V1_8197F 0x3
+#define BIT_QUEUEAC_Q6_V1_8197F(x)                                             \
+	(((x) & BIT_MASK_QUEUEAC_Q6_V1_8197F) << BIT_SHIFT_QUEUEAC_Q6_V1_8197F)
+#define BITS_QUEUEAC_Q6_V1_8197F                                               \
+	(BIT_MASK_QUEUEAC_Q6_V1_8197F << BIT_SHIFT_QUEUEAC_Q6_V1_8197F)
+#define BIT_CLEAR_QUEUEAC_Q6_V1_8197F(x) ((x) & (~BITS_QUEUEAC_Q6_V1_8197F))
+#define BIT_GET_QUEUEAC_Q6_V1_8197F(x)                                         \
+	(((x) >> BIT_SHIFT_QUEUEAC_Q6_V1_8197F) & BIT_MASK_QUEUEAC_Q6_V1_8197F)
+#define BIT_SET_QUEUEAC_Q6_V1_8197F(x, v)                                      \
+	(BIT_CLEAR_QUEUEAC_Q6_V1_8197F(x) | BIT_QUEUEAC_Q6_V1_8197F(v))
+
+#define BIT_TIDEMPTY_Q6_V1_8197F BIT(22)
+
+#define BIT_SHIFT_TAIL_PKT_Q6_V2_8197F 11
+#define BIT_MASK_TAIL_PKT_Q6_V2_8197F 0x7ff
+#define BIT_TAIL_PKT_Q6_V2_8197F(x)                                            \
+	(((x) & BIT_MASK_TAIL_PKT_Q6_V2_8197F)                                 \
+	 << BIT_SHIFT_TAIL_PKT_Q6_V2_8197F)
+#define BITS_TAIL_PKT_Q6_V2_8197F                                              \
+	(BIT_MASK_TAIL_PKT_Q6_V2_8197F << BIT_SHIFT_TAIL_PKT_Q6_V2_8197F)
+#define BIT_CLEAR_TAIL_PKT_Q6_V2_8197F(x) ((x) & (~BITS_TAIL_PKT_Q6_V2_8197F))
+#define BIT_GET_TAIL_PKT_Q6_V2_8197F(x)                                        \
+	(((x) >> BIT_SHIFT_TAIL_PKT_Q6_V2_8197F) &                             \
+	 BIT_MASK_TAIL_PKT_Q6_V2_8197F)
+#define BIT_SET_TAIL_PKT_Q6_V2_8197F(x, v)                                     \
+	(BIT_CLEAR_TAIL_PKT_Q6_V2_8197F(x) | BIT_TAIL_PKT_Q6_V2_8197F(v))
+
+#define BIT_SHIFT_HEAD_PKT_Q6_V1_8197F 0
+#define BIT_MASK_HEAD_PKT_Q6_V1_8197F 0x7ff
+#define BIT_HEAD_PKT_Q6_V1_8197F(x)                                            \
+	(((x) & BIT_MASK_HEAD_PKT_Q6_V1_8197F)                                 \
+	 << BIT_SHIFT_HEAD_PKT_Q6_V1_8197F)
+#define BITS_HEAD_PKT_Q6_V1_8197F                                              \
+	(BIT_MASK_HEAD_PKT_Q6_V1_8197F << BIT_SHIFT_HEAD_PKT_Q6_V1_8197F)
+#define BIT_CLEAR_HEAD_PKT_Q6_V1_8197F(x) ((x) & (~BITS_HEAD_PKT_Q6_V1_8197F))
+#define BIT_GET_HEAD_PKT_Q6_V1_8197F(x)                                        \
+	(((x) >> BIT_SHIFT_HEAD_PKT_Q6_V1_8197F) &                             \
+	 BIT_MASK_HEAD_PKT_Q6_V1_8197F)
+#define BIT_SET_HEAD_PKT_Q6_V1_8197F(x, v)                                     \
+	(BIT_CLEAR_HEAD_PKT_Q6_V1_8197F(x) | BIT_HEAD_PKT_Q6_V1_8197F(v))
+
+/* 2 REG_Q7_INFO_8197F */
+
+#define BIT_SHIFT_QUEUEMACID_Q7_V1_8197F 25
+#define BIT_MASK_QUEUEMACID_Q7_V1_8197F 0x7f
+#define BIT_QUEUEMACID_Q7_V1_8197F(x)                                          \
+	(((x) & BIT_MASK_QUEUEMACID_Q7_V1_8197F)                               \
+	 << BIT_SHIFT_QUEUEMACID_Q7_V1_8197F)
+#define BITS_QUEUEMACID_Q7_V1_8197F                                            \
+	(BIT_MASK_QUEUEMACID_Q7_V1_8197F << BIT_SHIFT_QUEUEMACID_Q7_V1_8197F)
+#define BIT_CLEAR_QUEUEMACID_Q7_V1_8197F(x)                                    \
+	((x) & (~BITS_QUEUEMACID_Q7_V1_8197F))
+#define BIT_GET_QUEUEMACID_Q7_V1_8197F(x)                                      \
+	(((x) >> BIT_SHIFT_QUEUEMACID_Q7_V1_8197F) &                           \
+	 BIT_MASK_QUEUEMACID_Q7_V1_8197F)
+#define BIT_SET_QUEUEMACID_Q7_V1_8197F(x, v)                                   \
+	(BIT_CLEAR_QUEUEMACID_Q7_V1_8197F(x) | BIT_QUEUEMACID_Q7_V1_8197F(v))
+
+#define BIT_SHIFT_QUEUEAC_Q7_V1_8197F 23
+#define BIT_MASK_QUEUEAC_Q7_V1_8197F 0x3
+#define BIT_QUEUEAC_Q7_V1_8197F(x)                                             \
+	(((x) & BIT_MASK_QUEUEAC_Q7_V1_8197F) << BIT_SHIFT_QUEUEAC_Q7_V1_8197F)
+#define BITS_QUEUEAC_Q7_V1_8197F                                               \
+	(BIT_MASK_QUEUEAC_Q7_V1_8197F << BIT_SHIFT_QUEUEAC_Q7_V1_8197F)
+#define BIT_CLEAR_QUEUEAC_Q7_V1_8197F(x) ((x) & (~BITS_QUEUEAC_Q7_V1_8197F))
+#define BIT_GET_QUEUEAC_Q7_V1_8197F(x)                                         \
+	(((x) >> BIT_SHIFT_QUEUEAC_Q7_V1_8197F) & BIT_MASK_QUEUEAC_Q7_V1_8197F)
+#define BIT_SET_QUEUEAC_Q7_V1_8197F(x, v)                                      \
+	(BIT_CLEAR_QUEUEAC_Q7_V1_8197F(x) | BIT_QUEUEAC_Q7_V1_8197F(v))
+
+#define BIT_TIDEMPTY_Q7_V1_8197F BIT(22)
+
+#define BIT_SHIFT_TAIL_PKT_Q7_V2_8197F 11
+#define BIT_MASK_TAIL_PKT_Q7_V2_8197F 0x7ff
+#define BIT_TAIL_PKT_Q7_V2_8197F(x)                                            \
+	(((x) & BIT_MASK_TAIL_PKT_Q7_V2_8197F)                                 \
+	 << BIT_SHIFT_TAIL_PKT_Q7_V2_8197F)
+#define BITS_TAIL_PKT_Q7_V2_8197F                                              \
+	(BIT_MASK_TAIL_PKT_Q7_V2_8197F << BIT_SHIFT_TAIL_PKT_Q7_V2_8197F)
+#define BIT_CLEAR_TAIL_PKT_Q7_V2_8197F(x) ((x) & (~BITS_TAIL_PKT_Q7_V2_8197F))
+#define BIT_GET_TAIL_PKT_Q7_V2_8197F(x)                                        \
+	(((x) >> BIT_SHIFT_TAIL_PKT_Q7_V2_8197F) &                             \
+	 BIT_MASK_TAIL_PKT_Q7_V2_8197F)
+#define BIT_SET_TAIL_PKT_Q7_V2_8197F(x, v)                                     \
+	(BIT_CLEAR_TAIL_PKT_Q7_V2_8197F(x) | BIT_TAIL_PKT_Q7_V2_8197F(v))
+
+#define BIT_SHIFT_HEAD_PKT_Q7_V1_8197F 0
+#define BIT_MASK_HEAD_PKT_Q7_V1_8197F 0x7ff
+#define BIT_HEAD_PKT_Q7_V1_8197F(x)                                            \
+	(((x) & BIT_MASK_HEAD_PKT_Q7_V1_8197F)                                 \
+	 << BIT_SHIFT_HEAD_PKT_Q7_V1_8197F)
+#define BITS_HEAD_PKT_Q7_V1_8197F                                              \
+	(BIT_MASK_HEAD_PKT_Q7_V1_8197F << BIT_SHIFT_HEAD_PKT_Q7_V1_8197F)
+#define BIT_CLEAR_HEAD_PKT_Q7_V1_8197F(x) ((x) & (~BITS_HEAD_PKT_Q7_V1_8197F))
+#define BIT_GET_HEAD_PKT_Q7_V1_8197F(x)                                        \
+	(((x) >> BIT_SHIFT_HEAD_PKT_Q7_V1_8197F) &                             \
+	 BIT_MASK_HEAD_PKT_Q7_V1_8197F)
+#define BIT_SET_HEAD_PKT_Q7_V1_8197F(x, v)                                     \
+	(BIT_CLEAR_HEAD_PKT_Q7_V1_8197F(x) | BIT_HEAD_PKT_Q7_V1_8197F(v))
+
+/* 2 REG_WMAC_LBK_BUF_HD_V1_8197F */
+
+#define BIT_SHIFT_WMAC_LBK_BUF_HEAD_V1_8197F 0
+#define BIT_MASK_WMAC_LBK_BUF_HEAD_V1_8197F 0xfff
+#define BIT_WMAC_LBK_BUF_HEAD_V1_8197F(x)                                      \
+	(((x) & BIT_MASK_WMAC_LBK_BUF_HEAD_V1_8197F)                           \
+	 << BIT_SHIFT_WMAC_LBK_BUF_HEAD_V1_8197F)
+#define BITS_WMAC_LBK_BUF_HEAD_V1_8197F                                        \
+	(BIT_MASK_WMAC_LBK_BUF_HEAD_V1_8197F                                   \
+	 << BIT_SHIFT_WMAC_LBK_BUF_HEAD_V1_8197F)
+#define BIT_CLEAR_WMAC_LBK_BUF_HEAD_V1_8197F(x)                                \
+	((x) & (~BITS_WMAC_LBK_BUF_HEAD_V1_8197F))
+#define BIT_GET_WMAC_LBK_BUF_HEAD_V1_8197F(x)                                  \
+	(((x) >> BIT_SHIFT_WMAC_LBK_BUF_HEAD_V1_8197F) &                       \
+	 BIT_MASK_WMAC_LBK_BUF_HEAD_V1_8197F)
+#define BIT_SET_WMAC_LBK_BUF_HEAD_V1_8197F(x, v)                               \
+	(BIT_CLEAR_WMAC_LBK_BUF_HEAD_V1_8197F(x) |                             \
+	 BIT_WMAC_LBK_BUF_HEAD_V1_8197F(v))
+
+/* 2 REG_MGQ_BDNY_V1_8197F */
+
+#define BIT_SHIFT_MGQ_PGBNDY_V1_8197F 0
+#define BIT_MASK_MGQ_PGBNDY_V1_8197F 0xfff
+#define BIT_MGQ_PGBNDY_V1_8197F(x)                                             \
+	(((x) & BIT_MASK_MGQ_PGBNDY_V1_8197F) << BIT_SHIFT_MGQ_PGBNDY_V1_8197F)
+#define BITS_MGQ_PGBNDY_V1_8197F                                               \
+	(BIT_MASK_MGQ_PGBNDY_V1_8197F << BIT_SHIFT_MGQ_PGBNDY_V1_8197F)
+#define BIT_CLEAR_MGQ_PGBNDY_V1_8197F(x) ((x) & (~BITS_MGQ_PGBNDY_V1_8197F))
+#define BIT_GET_MGQ_PGBNDY_V1_8197F(x)                                         \
+	(((x) >> BIT_SHIFT_MGQ_PGBNDY_V1_8197F) & BIT_MASK_MGQ_PGBNDY_V1_8197F)
+#define BIT_SET_MGQ_PGBNDY_V1_8197F(x, v)                                      \
+	(BIT_CLEAR_MGQ_PGBNDY_V1_8197F(x) | BIT_MGQ_PGBNDY_V1_8197F(v))
+
+/* 2 REG_TXRPT_CTRL_8197F */
+
+#define BIT_SHIFT_TRXRPT_TIMER_TH_8197F 24
+#define BIT_MASK_TRXRPT_TIMER_TH_8197F 0xff
+#define BIT_TRXRPT_TIMER_TH_8197F(x)                                           \
+	(((x) & BIT_MASK_TRXRPT_TIMER_TH_8197F)                                \
+	 << BIT_SHIFT_TRXRPT_TIMER_TH_8197F)
+#define BITS_TRXRPT_TIMER_TH_8197F                                             \
+	(BIT_MASK_TRXRPT_TIMER_TH_8197F << BIT_SHIFT_TRXRPT_TIMER_TH_8197F)
+#define BIT_CLEAR_TRXRPT_TIMER_TH_8197F(x) ((x) & (~BITS_TRXRPT_TIMER_TH_8197F))
+#define BIT_GET_TRXRPT_TIMER_TH_8197F(x)                                       \
+	(((x) >> BIT_SHIFT_TRXRPT_TIMER_TH_8197F) &                            \
+	 BIT_MASK_TRXRPT_TIMER_TH_8197F)
+#define BIT_SET_TRXRPT_TIMER_TH_8197F(x, v)                                    \
+	(BIT_CLEAR_TRXRPT_TIMER_TH_8197F(x) | BIT_TRXRPT_TIMER_TH_8197F(v))
+
+#define BIT_SHIFT_TRXRPT_LEN_TH_8197F 16
+#define BIT_MASK_TRXRPT_LEN_TH_8197F 0xff
+#define BIT_TRXRPT_LEN_TH_8197F(x)                                             \
+	(((x) & BIT_MASK_TRXRPT_LEN_TH_8197F) << BIT_SHIFT_TRXRPT_LEN_TH_8197F)
+#define BITS_TRXRPT_LEN_TH_8197F                                               \
+	(BIT_MASK_TRXRPT_LEN_TH_8197F << BIT_SHIFT_TRXRPT_LEN_TH_8197F)
+#define BIT_CLEAR_TRXRPT_LEN_TH_8197F(x) ((x) & (~BITS_TRXRPT_LEN_TH_8197F))
+#define BIT_GET_TRXRPT_LEN_TH_8197F(x)                                         \
+	(((x) >> BIT_SHIFT_TRXRPT_LEN_TH_8197F) & BIT_MASK_TRXRPT_LEN_TH_8197F)
+#define BIT_SET_TRXRPT_LEN_TH_8197F(x, v)                                      \
+	(BIT_CLEAR_TRXRPT_LEN_TH_8197F(x) | BIT_TRXRPT_LEN_TH_8197F(v))
+
+#define BIT_SHIFT_TRXRPT_READ_PTR_8197F 8
+#define BIT_MASK_TRXRPT_READ_PTR_8197F 0xff
+#define BIT_TRXRPT_READ_PTR_8197F(x)                                           \
+	(((x) & BIT_MASK_TRXRPT_READ_PTR_8197F)                                \
+	 << BIT_SHIFT_TRXRPT_READ_PTR_8197F)
+#define BITS_TRXRPT_READ_PTR_8197F                                             \
+	(BIT_MASK_TRXRPT_READ_PTR_8197F << BIT_SHIFT_TRXRPT_READ_PTR_8197F)
+#define BIT_CLEAR_TRXRPT_READ_PTR_8197F(x) ((x) & (~BITS_TRXRPT_READ_PTR_8197F))
+#define BIT_GET_TRXRPT_READ_PTR_8197F(x)                                       \
+	(((x) >> BIT_SHIFT_TRXRPT_READ_PTR_8197F) &                            \
+	 BIT_MASK_TRXRPT_READ_PTR_8197F)
+#define BIT_SET_TRXRPT_READ_PTR_8197F(x, v)                                    \
+	(BIT_CLEAR_TRXRPT_READ_PTR_8197F(x) | BIT_TRXRPT_READ_PTR_8197F(v))
+
+#define BIT_SHIFT_TRXRPT_WRITE_PTR_8197F 0
+#define BIT_MASK_TRXRPT_WRITE_PTR_8197F 0xff
+#define BIT_TRXRPT_WRITE_PTR_8197F(x)                                          \
+	(((x) & BIT_MASK_TRXRPT_WRITE_PTR_8197F)                               \
+	 << BIT_SHIFT_TRXRPT_WRITE_PTR_8197F)
+#define BITS_TRXRPT_WRITE_PTR_8197F                                            \
+	(BIT_MASK_TRXRPT_WRITE_PTR_8197F << BIT_SHIFT_TRXRPT_WRITE_PTR_8197F)
+#define BIT_CLEAR_TRXRPT_WRITE_PTR_8197F(x)                                    \
+	((x) & (~BITS_TRXRPT_WRITE_PTR_8197F))
+#define BIT_GET_TRXRPT_WRITE_PTR_8197F(x)                                      \
+	(((x) >> BIT_SHIFT_TRXRPT_WRITE_PTR_8197F) &                           \
+	 BIT_MASK_TRXRPT_WRITE_PTR_8197F)
+#define BIT_SET_TRXRPT_WRITE_PTR_8197F(x, v)                                   \
+	(BIT_CLEAR_TRXRPT_WRITE_PTR_8197F(x) | BIT_TRXRPT_WRITE_PTR_8197F(v))
+
+/* 2 REG_INIRTS_RATE_SEL_8197F */
+#define BIT_LEAG_RTS_BW_DUP_8197F BIT(5)
+
+/* 2 REG_BASIC_CFEND_RATE_8197F */
+
+#define BIT_SHIFT_BASIC_CFEND_RATE_8197F 0
+#define BIT_MASK_BASIC_CFEND_RATE_8197F 0x1f
+#define BIT_BASIC_CFEND_RATE_8197F(x)                                          \
+	(((x) & BIT_MASK_BASIC_CFEND_RATE_8197F)                               \
+	 << BIT_SHIFT_BASIC_CFEND_RATE_8197F)
+#define BITS_BASIC_CFEND_RATE_8197F                                            \
+	(BIT_MASK_BASIC_CFEND_RATE_8197F << BIT_SHIFT_BASIC_CFEND_RATE_8197F)
+#define BIT_CLEAR_BASIC_CFEND_RATE_8197F(x)                                    \
+	((x) & (~BITS_BASIC_CFEND_RATE_8197F))
+#define BIT_GET_BASIC_CFEND_RATE_8197F(x)                                      \
+	(((x) >> BIT_SHIFT_BASIC_CFEND_RATE_8197F) &                           \
+	 BIT_MASK_BASIC_CFEND_RATE_8197F)
+#define BIT_SET_BASIC_CFEND_RATE_8197F(x, v)                                   \
+	(BIT_CLEAR_BASIC_CFEND_RATE_8197F(x) | BIT_BASIC_CFEND_RATE_8197F(v))
+
+/* 2 REG_STBC_CFEND_RATE_8197F */
+
+#define BIT_SHIFT_STBC_CFEND_RATE_8197F 0
+#define BIT_MASK_STBC_CFEND_RATE_8197F 0x1f
+#define BIT_STBC_CFEND_RATE_8197F(x)                                           \
+	(((x) & BIT_MASK_STBC_CFEND_RATE_8197F)                                \
+	 << BIT_SHIFT_STBC_CFEND_RATE_8197F)
+#define BITS_STBC_CFEND_RATE_8197F                                             \
+	(BIT_MASK_STBC_CFEND_RATE_8197F << BIT_SHIFT_STBC_CFEND_RATE_8197F)
+#define BIT_CLEAR_STBC_CFEND_RATE_8197F(x) ((x) & (~BITS_STBC_CFEND_RATE_8197F))
+#define BIT_GET_STBC_CFEND_RATE_8197F(x)                                       \
+	(((x) >> BIT_SHIFT_STBC_CFEND_RATE_8197F) &                            \
+	 BIT_MASK_STBC_CFEND_RATE_8197F)
+#define BIT_SET_STBC_CFEND_RATE_8197F(x, v)                                    \
+	(BIT_CLEAR_STBC_CFEND_RATE_8197F(x) | BIT_STBC_CFEND_RATE_8197F(v))
+
+/* 2 REG_DATA_SC_8197F */
+
+#define BIT_SHIFT_TXSC_40M_8197F 4
+#define BIT_MASK_TXSC_40M_8197F 0xf
+#define BIT_TXSC_40M_8197F(x)                                                  \
+	(((x) & BIT_MASK_TXSC_40M_8197F) << BIT_SHIFT_TXSC_40M_8197F)
+#define BITS_TXSC_40M_8197F                                                    \
+	(BIT_MASK_TXSC_40M_8197F << BIT_SHIFT_TXSC_40M_8197F)
+#define BIT_CLEAR_TXSC_40M_8197F(x) ((x) & (~BITS_TXSC_40M_8197F))
+#define BIT_GET_TXSC_40M_8197F(x)                                              \
+	(((x) >> BIT_SHIFT_TXSC_40M_8197F) & BIT_MASK_TXSC_40M_8197F)
+#define BIT_SET_TXSC_40M_8197F(x, v)                                           \
+	(BIT_CLEAR_TXSC_40M_8197F(x) | BIT_TXSC_40M_8197F(v))
+
+#define BIT_SHIFT_TXSC_20M_8197F 0
+#define BIT_MASK_TXSC_20M_8197F 0xf
+#define BIT_TXSC_20M_8197F(x)                                                  \
+	(((x) & BIT_MASK_TXSC_20M_8197F) << BIT_SHIFT_TXSC_20M_8197F)
+#define BITS_TXSC_20M_8197F                                                    \
+	(BIT_MASK_TXSC_20M_8197F << BIT_SHIFT_TXSC_20M_8197F)
+#define BIT_CLEAR_TXSC_20M_8197F(x) ((x) & (~BITS_TXSC_20M_8197F))
+#define BIT_GET_TXSC_20M_8197F(x)                                              \
+	(((x) >> BIT_SHIFT_TXSC_20M_8197F) & BIT_MASK_TXSC_20M_8197F)
+#define BIT_SET_TXSC_20M_8197F(x, v)                                           \
+	(BIT_CLEAR_TXSC_20M_8197F(x) | BIT_TXSC_20M_8197F(v))
+
+/* 2 REG_MACID_SLEEP3_8197F */
+
+#define BIT_SHIFT_MACID127_96_PKTSLEEP_8197F 0
+#define BIT_MASK_MACID127_96_PKTSLEEP_8197F 0xffffffffL
+#define BIT_MACID127_96_PKTSLEEP_8197F(x)                                      \
+	(((x) & BIT_MASK_MACID127_96_PKTSLEEP_8197F)                           \
+	 << BIT_SHIFT_MACID127_96_PKTSLEEP_8197F)
+#define BITS_MACID127_96_PKTSLEEP_8197F                                        \
+	(BIT_MASK_MACID127_96_PKTSLEEP_8197F                                   \
+	 << BIT_SHIFT_MACID127_96_PKTSLEEP_8197F)
+#define BIT_CLEAR_MACID127_96_PKTSLEEP_8197F(x)                                \
+	((x) & (~BITS_MACID127_96_PKTSLEEP_8197F))
+#define BIT_GET_MACID127_96_PKTSLEEP_8197F(x)                                  \
+	(((x) >> BIT_SHIFT_MACID127_96_PKTSLEEP_8197F) &                       \
+	 BIT_MASK_MACID127_96_PKTSLEEP_8197F)
+#define BIT_SET_MACID127_96_PKTSLEEP_8197F(x, v)                               \
+	(BIT_CLEAR_MACID127_96_PKTSLEEP_8197F(x) |                             \
+	 BIT_MACID127_96_PKTSLEEP_8197F(v))
+
+/* 2 REG_MACID_SLEEP1_8197F */
+
+#define BIT_SHIFT_MACID63_32_PKTSLEEP_8197F 0
+#define BIT_MASK_MACID63_32_PKTSLEEP_8197F 0xffffffffL
+#define BIT_MACID63_32_PKTSLEEP_8197F(x)                                       \
+	(((x) & BIT_MASK_MACID63_32_PKTSLEEP_8197F)                            \
+	 << BIT_SHIFT_MACID63_32_PKTSLEEP_8197F)
+#define BITS_MACID63_32_PKTSLEEP_8197F                                         \
+	(BIT_MASK_MACID63_32_PKTSLEEP_8197F                                    \
+	 << BIT_SHIFT_MACID63_32_PKTSLEEP_8197F)
+#define BIT_CLEAR_MACID63_32_PKTSLEEP_8197F(x)                                 \
+	((x) & (~BITS_MACID63_32_PKTSLEEP_8197F))
+#define BIT_GET_MACID63_32_PKTSLEEP_8197F(x)                                   \
+	(((x) >> BIT_SHIFT_MACID63_32_PKTSLEEP_8197F) &                        \
+	 BIT_MASK_MACID63_32_PKTSLEEP_8197F)
+#define BIT_SET_MACID63_32_PKTSLEEP_8197F(x, v)                                \
+	(BIT_CLEAR_MACID63_32_PKTSLEEP_8197F(x) |                              \
+	 BIT_MACID63_32_PKTSLEEP_8197F(v))
+
+/* 2 REG_ARFR2_V1_8197F */
+
+#define BIT_SHIFT_ARFR2_V1_8197F 0
+#define BIT_MASK_ARFR2_V1_8197F 0xffffffffffffffffL
+#define BIT_ARFR2_V1_8197F(x)                                                  \
+	(((x) & BIT_MASK_ARFR2_V1_8197F) << BIT_SHIFT_ARFR2_V1_8197F)
+#define BITS_ARFR2_V1_8197F                                                    \
+	(BIT_MASK_ARFR2_V1_8197F << BIT_SHIFT_ARFR2_V1_8197F)
+#define BIT_CLEAR_ARFR2_V1_8197F(x) ((x) & (~BITS_ARFR2_V1_8197F))
+#define BIT_GET_ARFR2_V1_8197F(x)                                              \
+	(((x) >> BIT_SHIFT_ARFR2_V1_8197F) & BIT_MASK_ARFR2_V1_8197F)
+#define BIT_SET_ARFR2_V1_8197F(x, v)                                           \
+	(BIT_CLEAR_ARFR2_V1_8197F(x) | BIT_ARFR2_V1_8197F(v))
+
+/* 2 REG_ARFR3_V1_8197F */
+
+#define BIT_SHIFT_ARFR3_V1_8197F 0
+#define BIT_MASK_ARFR3_V1_8197F 0xffffffffffffffffL
+#define BIT_ARFR3_V1_8197F(x)                                                  \
+	(((x) & BIT_MASK_ARFR3_V1_8197F) << BIT_SHIFT_ARFR3_V1_8197F)
+#define BITS_ARFR3_V1_8197F                                                    \
+	(BIT_MASK_ARFR3_V1_8197F << BIT_SHIFT_ARFR3_V1_8197F)
+#define BIT_CLEAR_ARFR3_V1_8197F(x) ((x) & (~BITS_ARFR3_V1_8197F))
+#define BIT_GET_ARFR3_V1_8197F(x)                                              \
+	(((x) >> BIT_SHIFT_ARFR3_V1_8197F) & BIT_MASK_ARFR3_V1_8197F)
+#define BIT_SET_ARFR3_V1_8197F(x, v)                                           \
+	(BIT_CLEAR_ARFR3_V1_8197F(x) | BIT_ARFR3_V1_8197F(v))
+
+/* 2 REG_ARFR4_8197F */
+
+#define BIT_SHIFT_ARFR4_8197F 0
+#define BIT_MASK_ARFR4_8197F 0xffffffffffffffffL
+#define BIT_ARFR4_8197F(x)                                                     \
+	(((x) & BIT_MASK_ARFR4_8197F) << BIT_SHIFT_ARFR4_8197F)
+#define BITS_ARFR4_8197F (BIT_MASK_ARFR4_8197F << BIT_SHIFT_ARFR4_8197F)
+#define BIT_CLEAR_ARFR4_8197F(x) ((x) & (~BITS_ARFR4_8197F))
+#define BIT_GET_ARFR4_8197F(x)                                                 \
+	(((x) >> BIT_SHIFT_ARFR4_8197F) & BIT_MASK_ARFR4_8197F)
+#define BIT_SET_ARFR4_8197F(x, v)                                              \
+	(BIT_CLEAR_ARFR4_8197F(x) | BIT_ARFR4_8197F(v))
+
+/* 2 REG_ARFR5_8197F */
+
+#define BIT_SHIFT_ARFR5_8197F 0
+#define BIT_MASK_ARFR5_8197F 0xffffffffffffffffL
+#define BIT_ARFR5_8197F(x)                                                     \
+	(((x) & BIT_MASK_ARFR5_8197F) << BIT_SHIFT_ARFR5_8197F)
+#define BITS_ARFR5_8197F (BIT_MASK_ARFR5_8197F << BIT_SHIFT_ARFR5_8197F)
+#define BIT_CLEAR_ARFR5_8197F(x) ((x) & (~BITS_ARFR5_8197F))
+#define BIT_GET_ARFR5_8197F(x)                                                 \
+	(((x) >> BIT_SHIFT_ARFR5_8197F) & BIT_MASK_ARFR5_8197F)
+#define BIT_SET_ARFR5_8197F(x, v)                                              \
+	(BIT_CLEAR_ARFR5_8197F(x) | BIT_ARFR5_8197F(v))
+
+/* 2 REG_TXRPT_START_OFFSET_8197F */
+#define BIT_SHCUT_PARSE_DASA_8197F BIT(25)
+#define BIT_SHCUT_BYPASS_8197F BIT(24)
+#define BIT__R_RPTFIFO_1K_8197F BIT(16)
+
+#define BIT_SHIFT_MACID_CTRL_OFFSET_8197F 8
+#define BIT_MASK_MACID_CTRL_OFFSET_8197F 0xff
+#define BIT_MACID_CTRL_OFFSET_8197F(x)                                         \
+	(((x) & BIT_MASK_MACID_CTRL_OFFSET_8197F)                              \
+	 << BIT_SHIFT_MACID_CTRL_OFFSET_8197F)
+#define BITS_MACID_CTRL_OFFSET_8197F                                           \
+	(BIT_MASK_MACID_CTRL_OFFSET_8197F << BIT_SHIFT_MACID_CTRL_OFFSET_8197F)
+#define BIT_CLEAR_MACID_CTRL_OFFSET_8197F(x)                                   \
+	((x) & (~BITS_MACID_CTRL_OFFSET_8197F))
+#define BIT_GET_MACID_CTRL_OFFSET_8197F(x)                                     \
+	(((x) >> BIT_SHIFT_MACID_CTRL_OFFSET_8197F) &                          \
+	 BIT_MASK_MACID_CTRL_OFFSET_8197F)
+#define BIT_SET_MACID_CTRL_OFFSET_8197F(x, v)                                  \
+	(BIT_CLEAR_MACID_CTRL_OFFSET_8197F(x) | BIT_MACID_CTRL_OFFSET_8197F(v))
+
+#define BIT_SHIFT_AMPDU_TXRPT_OFFSET_8197F 0
+#define BIT_MASK_AMPDU_TXRPT_OFFSET_8197F 0xff
+#define BIT_AMPDU_TXRPT_OFFSET_8197F(x)                                        \
+	(((x) & BIT_MASK_AMPDU_TXRPT_OFFSET_8197F)                             \
+	 << BIT_SHIFT_AMPDU_TXRPT_OFFSET_8197F)
+#define BITS_AMPDU_TXRPT_OFFSET_8197F                                          \
+	(BIT_MASK_AMPDU_TXRPT_OFFSET_8197F                                     \
+	 << BIT_SHIFT_AMPDU_TXRPT_OFFSET_8197F)
+#define BIT_CLEAR_AMPDU_TXRPT_OFFSET_8197F(x)                                  \
+	((x) & (~BITS_AMPDU_TXRPT_OFFSET_8197F))
+#define BIT_GET_AMPDU_TXRPT_OFFSET_8197F(x)                                    \
+	(((x) >> BIT_SHIFT_AMPDU_TXRPT_OFFSET_8197F) &                         \
+	 BIT_MASK_AMPDU_TXRPT_OFFSET_8197F)
+#define BIT_SET_AMPDU_TXRPT_OFFSET_8197F(x, v)                                 \
+	(BIT_CLEAR_AMPDU_TXRPT_OFFSET_8197F(x) |                               \
+	 BIT_AMPDU_TXRPT_OFFSET_8197F(v))
+
+/* 2 REG_NOT_VALID_8197F */
+
+/* 2 REG_POWER_STAGE1_8197F */
+#define BIT_PTA_WL_PRI_MASK_CPU_MGQ_8197F BIT(31)
+#define BIT_PTA_WL_PRI_MASK_BCNQ_8197F BIT(30)
+#define BIT_PTA_WL_PRI_MASK_HIQ_8197F BIT(29)
+#define BIT_PTA_WL_PRI_MASK_MGQ_8197F BIT(28)
+#define BIT_PTA_WL_PRI_MASK_BK_8197F BIT(27)
+#define BIT_PTA_WL_PRI_MASK_BE_8197F BIT(26)
+#define BIT_PTA_WL_PRI_MASK_VI_8197F BIT(25)
+#define BIT_PTA_WL_PRI_MASK_VO_8197F BIT(24)
+
+#define BIT_SHIFT_POWER_STAGE1_8197F 0
+#define BIT_MASK_POWER_STAGE1_8197F 0xffffff
+#define BIT_POWER_STAGE1_8197F(x)                                              \
+	(((x) & BIT_MASK_POWER_STAGE1_8197F) << BIT_SHIFT_POWER_STAGE1_8197F)
+#define BITS_POWER_STAGE1_8197F                                                \
+	(BIT_MASK_POWER_STAGE1_8197F << BIT_SHIFT_POWER_STAGE1_8197F)
+#define BIT_CLEAR_POWER_STAGE1_8197F(x) ((x) & (~BITS_POWER_STAGE1_8197F))
+#define BIT_GET_POWER_STAGE1_8197F(x)                                          \
+	(((x) >> BIT_SHIFT_POWER_STAGE1_8197F) & BIT_MASK_POWER_STAGE1_8197F)
+#define BIT_SET_POWER_STAGE1_8197F(x, v)                                       \
+	(BIT_CLEAR_POWER_STAGE1_8197F(x) | BIT_POWER_STAGE1_8197F(v))
+
+/* 2 REG_POWER_STAGE2_8197F */
+#define BIT__R_CTRL_PKT_POW_ADJ_8197F BIT(24)
+
+#define BIT_SHIFT_POWER_STAGE2_8197F 0
+#define BIT_MASK_POWER_STAGE2_8197F 0xffffff
+#define BIT_POWER_STAGE2_8197F(x)                                              \
+	(((x) & BIT_MASK_POWER_STAGE2_8197F) << BIT_SHIFT_POWER_STAGE2_8197F)
+#define BITS_POWER_STAGE2_8197F                                                \
+	(BIT_MASK_POWER_STAGE2_8197F << BIT_SHIFT_POWER_STAGE2_8197F)
+#define BIT_CLEAR_POWER_STAGE2_8197F(x) ((x) & (~BITS_POWER_STAGE2_8197F))
+#define BIT_GET_POWER_STAGE2_8197F(x)                                          \
+	(((x) >> BIT_SHIFT_POWER_STAGE2_8197F) & BIT_MASK_POWER_STAGE2_8197F)
+#define BIT_SET_POWER_STAGE2_8197F(x, v)                                       \
+	(BIT_CLEAR_POWER_STAGE2_8197F(x) | BIT_POWER_STAGE2_8197F(v))
+
+/* 2 REG_SW_AMPDU_BURST_MODE_CTRL_8197F */
+
+#define BIT_SHIFT_PAD_NUM_THRES_8197F 24
+#define BIT_MASK_PAD_NUM_THRES_8197F 0x3f
+#define BIT_PAD_NUM_THRES_8197F(x)                                             \
+	(((x) & BIT_MASK_PAD_NUM_THRES_8197F) << BIT_SHIFT_PAD_NUM_THRES_8197F)
+#define BITS_PAD_NUM_THRES_8197F                                               \
+	(BIT_MASK_PAD_NUM_THRES_8197F << BIT_SHIFT_PAD_NUM_THRES_8197F)
+#define BIT_CLEAR_PAD_NUM_THRES_8197F(x) ((x) & (~BITS_PAD_NUM_THRES_8197F))
+#define BIT_GET_PAD_NUM_THRES_8197F(x)                                         \
+	(((x) >> BIT_SHIFT_PAD_NUM_THRES_8197F) & BIT_MASK_PAD_NUM_THRES_8197F)
+#define BIT_SET_PAD_NUM_THRES_8197F(x, v)                                      \
+	(BIT_CLEAR_PAD_NUM_THRES_8197F(x) | BIT_PAD_NUM_THRES_8197F(v))
+
+#define BIT_R_DMA_THIS_QUEUE_BK_8197F BIT(23)
+#define BIT_R_DMA_THIS_QUEUE_BE_8197F BIT(22)
+#define BIT_R_DMA_THIS_QUEUE_VI_8197F BIT(21)
+#define BIT_R_DMA_THIS_QUEUE_VO_8197F BIT(20)
+
+#define BIT_SHIFT_R_TOTAL_LEN_TH_8197F 8
+#define BIT_MASK_R_TOTAL_LEN_TH_8197F 0xfff
+#define BIT_R_TOTAL_LEN_TH_8197F(x)                                            \
+	(((x) & BIT_MASK_R_TOTAL_LEN_TH_8197F)                                 \
+	 << BIT_SHIFT_R_TOTAL_LEN_TH_8197F)
+#define BITS_R_TOTAL_LEN_TH_8197F                                              \
+	(BIT_MASK_R_TOTAL_LEN_TH_8197F << BIT_SHIFT_R_TOTAL_LEN_TH_8197F)
+#define BIT_CLEAR_R_TOTAL_LEN_TH_8197F(x) ((x) & (~BITS_R_TOTAL_LEN_TH_8197F))
+#define BIT_GET_R_TOTAL_LEN_TH_8197F(x)                                        \
+	(((x) >> BIT_SHIFT_R_TOTAL_LEN_TH_8197F) &                             \
+	 BIT_MASK_R_TOTAL_LEN_TH_8197F)
+#define BIT_SET_R_TOTAL_LEN_TH_8197F(x, v)                                     \
+	(BIT_CLEAR_R_TOTAL_LEN_TH_8197F(x) | BIT_R_TOTAL_LEN_TH_8197F(v))
+
+#define BIT_EN_NEW_EARLY_8197F BIT(7)
+#define BIT_PRE_TX_CMD_8197F BIT(6)
+
+#define BIT_SHIFT_NUM_SCL_EN_8197F 4
+#define BIT_MASK_NUM_SCL_EN_8197F 0x3
+#define BIT_NUM_SCL_EN_8197F(x)                                                \
+	(((x) & BIT_MASK_NUM_SCL_EN_8197F) << BIT_SHIFT_NUM_SCL_EN_8197F)
+#define BITS_NUM_SCL_EN_8197F                                                  \
+	(BIT_MASK_NUM_SCL_EN_8197F << BIT_SHIFT_NUM_SCL_EN_8197F)
+#define BIT_CLEAR_NUM_SCL_EN_8197F(x) ((x) & (~BITS_NUM_SCL_EN_8197F))
+#define BIT_GET_NUM_SCL_EN_8197F(x)                                            \
+	(((x) >> BIT_SHIFT_NUM_SCL_EN_8197F) & BIT_MASK_NUM_SCL_EN_8197F)
+#define BIT_SET_NUM_SCL_EN_8197F(x, v)                                         \
+	(BIT_CLEAR_NUM_SCL_EN_8197F(x) | BIT_NUM_SCL_EN_8197F(v))
+
+#define BIT_BK_EN_8197F BIT(3)
+#define BIT_BE_EN_8197F BIT(2)
+#define BIT_VI_EN_8197F BIT(1)
+#define BIT_VO_EN_8197F BIT(0)
+
+/* 2 REG_PKT_LIFE_TIME_8197F */
+
+#define BIT_SHIFT_PKT_LIFTIME_BEBK_8197F 16
+#define BIT_MASK_PKT_LIFTIME_BEBK_8197F 0xffff
+#define BIT_PKT_LIFTIME_BEBK_8197F(x)                                          \
+	(((x) & BIT_MASK_PKT_LIFTIME_BEBK_8197F)                               \
+	 << BIT_SHIFT_PKT_LIFTIME_BEBK_8197F)
+#define BITS_PKT_LIFTIME_BEBK_8197F                                            \
+	(BIT_MASK_PKT_LIFTIME_BEBK_8197F << BIT_SHIFT_PKT_LIFTIME_BEBK_8197F)
+#define BIT_CLEAR_PKT_LIFTIME_BEBK_8197F(x)                                    \
+	((x) & (~BITS_PKT_LIFTIME_BEBK_8197F))
+#define BIT_GET_PKT_LIFTIME_BEBK_8197F(x)                                      \
+	(((x) >> BIT_SHIFT_PKT_LIFTIME_BEBK_8197F) &                           \
+	 BIT_MASK_PKT_LIFTIME_BEBK_8197F)
+#define BIT_SET_PKT_LIFTIME_BEBK_8197F(x, v)                                   \
+	(BIT_CLEAR_PKT_LIFTIME_BEBK_8197F(x) | BIT_PKT_LIFTIME_BEBK_8197F(v))
+
+#define BIT_SHIFT_PKT_LIFTIME_VOVI_8197F 0
+#define BIT_MASK_PKT_LIFTIME_VOVI_8197F 0xffff
+#define BIT_PKT_LIFTIME_VOVI_8197F(x)                                          \
+	(((x) & BIT_MASK_PKT_LIFTIME_VOVI_8197F)                               \
+	 << BIT_SHIFT_PKT_LIFTIME_VOVI_8197F)
+#define BITS_PKT_LIFTIME_VOVI_8197F                                            \
+	(BIT_MASK_PKT_LIFTIME_VOVI_8197F << BIT_SHIFT_PKT_LIFTIME_VOVI_8197F)
+#define BIT_CLEAR_PKT_LIFTIME_VOVI_8197F(x)                                    \
+	((x) & (~BITS_PKT_LIFTIME_VOVI_8197F))
+#define BIT_GET_PKT_LIFTIME_VOVI_8197F(x)                                      \
+	(((x) >> BIT_SHIFT_PKT_LIFTIME_VOVI_8197F) &                           \
+	 BIT_MASK_PKT_LIFTIME_VOVI_8197F)
+#define BIT_SET_PKT_LIFTIME_VOVI_8197F(x, v)                                   \
+	(BIT_CLEAR_PKT_LIFTIME_VOVI_8197F(x) | BIT_PKT_LIFTIME_VOVI_8197F(v))
+
+/* 2 REG_STBC_SETTING_8197F */
+
+#define BIT_SHIFT_CDEND_TXTIME_L_8197F 4
+#define BIT_MASK_CDEND_TXTIME_L_8197F 0xf
+#define BIT_CDEND_TXTIME_L_8197F(x)                                            \
+	(((x) & BIT_MASK_CDEND_TXTIME_L_8197F)                                 \
+	 << BIT_SHIFT_CDEND_TXTIME_L_8197F)
+#define BITS_CDEND_TXTIME_L_8197F                                              \
+	(BIT_MASK_CDEND_TXTIME_L_8197F << BIT_SHIFT_CDEND_TXTIME_L_8197F)
+#define BIT_CLEAR_CDEND_TXTIME_L_8197F(x) ((x) & (~BITS_CDEND_TXTIME_L_8197F))
+#define BIT_GET_CDEND_TXTIME_L_8197F(x)                                        \
+	(((x) >> BIT_SHIFT_CDEND_TXTIME_L_8197F) &                             \
+	 BIT_MASK_CDEND_TXTIME_L_8197F)
+#define BIT_SET_CDEND_TXTIME_L_8197F(x, v)                                     \
+	(BIT_CLEAR_CDEND_TXTIME_L_8197F(x) | BIT_CDEND_TXTIME_L_8197F(v))
+
+#define BIT_SHIFT_NESS_8197F 2
+#define BIT_MASK_NESS_8197F 0x3
+#define BIT_NESS_8197F(x) (((x) & BIT_MASK_NESS_8197F) << BIT_SHIFT_NESS_8197F)
+#define BITS_NESS_8197F (BIT_MASK_NESS_8197F << BIT_SHIFT_NESS_8197F)
+#define BIT_CLEAR_NESS_8197F(x) ((x) & (~BITS_NESS_8197F))
+#define BIT_GET_NESS_8197F(x)                                                  \
+	(((x) >> BIT_SHIFT_NESS_8197F) & BIT_MASK_NESS_8197F)
+#define BIT_SET_NESS_8197F(x, v) (BIT_CLEAR_NESS_8197F(x) | BIT_NESS_8197F(v))
+
+#define BIT_SHIFT_STBC_CFEND_8197F 0
+#define BIT_MASK_STBC_CFEND_8197F 0x3
+#define BIT_STBC_CFEND_8197F(x)                                                \
+	(((x) & BIT_MASK_STBC_CFEND_8197F) << BIT_SHIFT_STBC_CFEND_8197F)
+#define BITS_STBC_CFEND_8197F                                                  \
+	(BIT_MASK_STBC_CFEND_8197F << BIT_SHIFT_STBC_CFEND_8197F)
+#define BIT_CLEAR_STBC_CFEND_8197F(x) ((x) & (~BITS_STBC_CFEND_8197F))
+#define BIT_GET_STBC_CFEND_8197F(x)                                            \
+	(((x) >> BIT_SHIFT_STBC_CFEND_8197F) & BIT_MASK_STBC_CFEND_8197F)
+#define BIT_SET_STBC_CFEND_8197F(x, v)                                         \
+	(BIT_CLEAR_STBC_CFEND_8197F(x) | BIT_STBC_CFEND_8197F(v))
+
+/* 2 REG_STBC_SETTING2_8197F */
+
+#define BIT_SHIFT_CDEND_TXTIME_H_8197F 0
+#define BIT_MASK_CDEND_TXTIME_H_8197F 0x1f
+#define BIT_CDEND_TXTIME_H_8197F(x)                                            \
+	(((x) & BIT_MASK_CDEND_TXTIME_H_8197F)                                 \
+	 << BIT_SHIFT_CDEND_TXTIME_H_8197F)
+#define BITS_CDEND_TXTIME_H_8197F                                              \
+	(BIT_MASK_CDEND_TXTIME_H_8197F << BIT_SHIFT_CDEND_TXTIME_H_8197F)
+#define BIT_CLEAR_CDEND_TXTIME_H_8197F(x) ((x) & (~BITS_CDEND_TXTIME_H_8197F))
+#define BIT_GET_CDEND_TXTIME_H_8197F(x)                                        \
+	(((x) >> BIT_SHIFT_CDEND_TXTIME_H_8197F) &                             \
+	 BIT_MASK_CDEND_TXTIME_H_8197F)
+#define BIT_SET_CDEND_TXTIME_H_8197F(x, v)                                     \
+	(BIT_CLEAR_CDEND_TXTIME_H_8197F(x) | BIT_CDEND_TXTIME_H_8197F(v))
+
+/* 2 REG_QUEUE_CTRL_8197F */
+#define BIT_PTA_EDCCA_EN_8197F BIT(5)
+#define BIT_PTA_WL_TX_EN_8197F BIT(4)
+#define BIT_R_USE_DATA_BW_8197F BIT(3)
+#define BIT_TRI_PKT_INT_MODE1_8197F BIT(2)
+#define BIT_TRI_PKT_INT_MODE0_8197F BIT(1)
+#define BIT_ACQ_MODE_SEL_8197F BIT(0)
+
+/* 2 REG_SINGLE_AMPDU_CTRL_8197F */
+#define BIT_EN_SINGLE_APMDU_8197F BIT(7)
+
+/* 2 REG_PROT_MODE_CTRL_8197F */
+
+#define BIT_SHIFT_RTS_MAX_AGG_NUM_8197F 24
+#define BIT_MASK_RTS_MAX_AGG_NUM_8197F 0x3f
+#define BIT_RTS_MAX_AGG_NUM_8197F(x)                                           \
+	(((x) & BIT_MASK_RTS_MAX_AGG_NUM_8197F)                                \
+	 << BIT_SHIFT_RTS_MAX_AGG_NUM_8197F)
+#define BITS_RTS_MAX_AGG_NUM_8197F                                             \
+	(BIT_MASK_RTS_MAX_AGG_NUM_8197F << BIT_SHIFT_RTS_MAX_AGG_NUM_8197F)
+#define BIT_CLEAR_RTS_MAX_AGG_NUM_8197F(x) ((x) & (~BITS_RTS_MAX_AGG_NUM_8197F))
+#define BIT_GET_RTS_MAX_AGG_NUM_8197F(x)                                       \
+	(((x) >> BIT_SHIFT_RTS_MAX_AGG_NUM_8197F) &                            \
+	 BIT_MASK_RTS_MAX_AGG_NUM_8197F)
+#define BIT_SET_RTS_MAX_AGG_NUM_8197F(x, v)                                    \
+	(BIT_CLEAR_RTS_MAX_AGG_NUM_8197F(x) | BIT_RTS_MAX_AGG_NUM_8197F(v))
+
+#define BIT_SHIFT_MAX_AGG_NUM_8197F 16
+#define BIT_MASK_MAX_AGG_NUM_8197F 0x3f
+#define BIT_MAX_AGG_NUM_8197F(x)                                               \
+	(((x) & BIT_MASK_MAX_AGG_NUM_8197F) << BIT_SHIFT_MAX_AGG_NUM_8197F)
+#define BITS_MAX_AGG_NUM_8197F                                                 \
+	(BIT_MASK_MAX_AGG_NUM_8197F << BIT_SHIFT_MAX_AGG_NUM_8197F)
+#define BIT_CLEAR_MAX_AGG_NUM_8197F(x) ((x) & (~BITS_MAX_AGG_NUM_8197F))
+#define BIT_GET_MAX_AGG_NUM_8197F(x)                                           \
+	(((x) >> BIT_SHIFT_MAX_AGG_NUM_8197F) & BIT_MASK_MAX_AGG_NUM_8197F)
+#define BIT_SET_MAX_AGG_NUM_8197F(x, v)                                        \
+	(BIT_CLEAR_MAX_AGG_NUM_8197F(x) | BIT_MAX_AGG_NUM_8197F(v))
+
+#define BIT_SHIFT_RTS_TXTIME_TH_8197F 8
+#define BIT_MASK_RTS_TXTIME_TH_8197F 0xff
+#define BIT_RTS_TXTIME_TH_8197F(x)                                             \
+	(((x) & BIT_MASK_RTS_TXTIME_TH_8197F) << BIT_SHIFT_RTS_TXTIME_TH_8197F)
+#define BITS_RTS_TXTIME_TH_8197F                                               \
+	(BIT_MASK_RTS_TXTIME_TH_8197F << BIT_SHIFT_RTS_TXTIME_TH_8197F)
+#define BIT_CLEAR_RTS_TXTIME_TH_8197F(x) ((x) & (~BITS_RTS_TXTIME_TH_8197F))
+#define BIT_GET_RTS_TXTIME_TH_8197F(x)                                         \
+	(((x) >> BIT_SHIFT_RTS_TXTIME_TH_8197F) & BIT_MASK_RTS_TXTIME_TH_8197F)
+#define BIT_SET_RTS_TXTIME_TH_8197F(x, v)                                      \
+	(BIT_CLEAR_RTS_TXTIME_TH_8197F(x) | BIT_RTS_TXTIME_TH_8197F(v))
+
+#define BIT_SHIFT_RTS_LEN_TH_8197F 0
+#define BIT_MASK_RTS_LEN_TH_8197F 0xff
+#define BIT_RTS_LEN_TH_8197F(x)                                                \
+	(((x) & BIT_MASK_RTS_LEN_TH_8197F) << BIT_SHIFT_RTS_LEN_TH_8197F)
+#define BITS_RTS_LEN_TH_8197F                                                  \
+	(BIT_MASK_RTS_LEN_TH_8197F << BIT_SHIFT_RTS_LEN_TH_8197F)
+#define BIT_CLEAR_RTS_LEN_TH_8197F(x) ((x) & (~BITS_RTS_LEN_TH_8197F))
+#define BIT_GET_RTS_LEN_TH_8197F(x)                                            \
+	(((x) >> BIT_SHIFT_RTS_LEN_TH_8197F) & BIT_MASK_RTS_LEN_TH_8197F)
+#define BIT_SET_RTS_LEN_TH_8197F(x, v)                                         \
+	(BIT_CLEAR_RTS_LEN_TH_8197F(x) | BIT_RTS_LEN_TH_8197F(v))
+
+/* 2 REG_BAR_MODE_CTRL_8197F */
+
+#define BIT_SHIFT_BAR_RTY_LMT_8197F 16
+#define BIT_MASK_BAR_RTY_LMT_8197F 0x3
+#define BIT_BAR_RTY_LMT_8197F(x)                                               \
+	(((x) & BIT_MASK_BAR_RTY_LMT_8197F) << BIT_SHIFT_BAR_RTY_LMT_8197F)
+#define BITS_BAR_RTY_LMT_8197F                                                 \
+	(BIT_MASK_BAR_RTY_LMT_8197F << BIT_SHIFT_BAR_RTY_LMT_8197F)
+#define BIT_CLEAR_BAR_RTY_LMT_8197F(x) ((x) & (~BITS_BAR_RTY_LMT_8197F))
+#define BIT_GET_BAR_RTY_LMT_8197F(x)                                           \
+	(((x) >> BIT_SHIFT_BAR_RTY_LMT_8197F) & BIT_MASK_BAR_RTY_LMT_8197F)
+#define BIT_SET_BAR_RTY_LMT_8197F(x, v)                                        \
+	(BIT_CLEAR_BAR_RTY_LMT_8197F(x) | BIT_BAR_RTY_LMT_8197F(v))
+
+#define BIT_SHIFT_BAR_PKT_TXTIME_TH_8197F 8
+#define BIT_MASK_BAR_PKT_TXTIME_TH_8197F 0xff
+#define BIT_BAR_PKT_TXTIME_TH_8197F(x)                                         \
+	(((x) & BIT_MASK_BAR_PKT_TXTIME_TH_8197F)                              \
+	 << BIT_SHIFT_BAR_PKT_TXTIME_TH_8197F)
+#define BITS_BAR_PKT_TXTIME_TH_8197F                                           \
+	(BIT_MASK_BAR_PKT_TXTIME_TH_8197F << BIT_SHIFT_BAR_PKT_TXTIME_TH_8197F)
+#define BIT_CLEAR_BAR_PKT_TXTIME_TH_8197F(x)                                   \
+	((x) & (~BITS_BAR_PKT_TXTIME_TH_8197F))
+#define BIT_GET_BAR_PKT_TXTIME_TH_8197F(x)                                     \
+	(((x) >> BIT_SHIFT_BAR_PKT_TXTIME_TH_8197F) &                          \
+	 BIT_MASK_BAR_PKT_TXTIME_TH_8197F)
+#define BIT_SET_BAR_PKT_TXTIME_TH_8197F(x, v)                                  \
+	(BIT_CLEAR_BAR_PKT_TXTIME_TH_8197F(x) | BIT_BAR_PKT_TXTIME_TH_8197F(v))
+
+#define BIT_BAR_EN_V1_8197F BIT(6)
+
+#define BIT_SHIFT_BAR_PKTNUM_TH_V1_8197F 0
+#define BIT_MASK_BAR_PKTNUM_TH_V1_8197F 0x3f
+#define BIT_BAR_PKTNUM_TH_V1_8197F(x)                                          \
+	(((x) & BIT_MASK_BAR_PKTNUM_TH_V1_8197F)                               \
+	 << BIT_SHIFT_BAR_PKTNUM_TH_V1_8197F)
+#define BITS_BAR_PKTNUM_TH_V1_8197F                                            \
+	(BIT_MASK_BAR_PKTNUM_TH_V1_8197F << BIT_SHIFT_BAR_PKTNUM_TH_V1_8197F)
+#define BIT_CLEAR_BAR_PKTNUM_TH_V1_8197F(x)                                    \
+	((x) & (~BITS_BAR_PKTNUM_TH_V1_8197F))
+#define BIT_GET_BAR_PKTNUM_TH_V1_8197F(x)                                      \
+	(((x) >> BIT_SHIFT_BAR_PKTNUM_TH_V1_8197F) &                           \
+	 BIT_MASK_BAR_PKTNUM_TH_V1_8197F)
+#define BIT_SET_BAR_PKTNUM_TH_V1_8197F(x, v)                                   \
+	(BIT_CLEAR_BAR_PKTNUM_TH_V1_8197F(x) | BIT_BAR_PKTNUM_TH_V1_8197F(v))
+
+/* 2 REG_RA_TRY_RATE_AGG_LMT_8197F */
+
+#define BIT_SHIFT_RA_TRY_RATE_AGG_LMT_V1_8197F 0
+#define BIT_MASK_RA_TRY_RATE_AGG_LMT_V1_8197F 0x3f
+#define BIT_RA_TRY_RATE_AGG_LMT_V1_8197F(x)                                    \
+	(((x) & BIT_MASK_RA_TRY_RATE_AGG_LMT_V1_8197F)                         \
+	 << BIT_SHIFT_RA_TRY_RATE_AGG_LMT_V1_8197F)
+#define BITS_RA_TRY_RATE_AGG_LMT_V1_8197F                                      \
+	(BIT_MASK_RA_TRY_RATE_AGG_LMT_V1_8197F                                 \
+	 << BIT_SHIFT_RA_TRY_RATE_AGG_LMT_V1_8197F)
+#define BIT_CLEAR_RA_TRY_RATE_AGG_LMT_V1_8197F(x)                              \
+	((x) & (~BITS_RA_TRY_RATE_AGG_LMT_V1_8197F))
+#define BIT_GET_RA_TRY_RATE_AGG_LMT_V1_8197F(x)                                \
+	(((x) >> BIT_SHIFT_RA_TRY_RATE_AGG_LMT_V1_8197F) &                     \
+	 BIT_MASK_RA_TRY_RATE_AGG_LMT_V1_8197F)
+#define BIT_SET_RA_TRY_RATE_AGG_LMT_V1_8197F(x, v)                             \
+	(BIT_CLEAR_RA_TRY_RATE_AGG_LMT_V1_8197F(x) |                           \
+	 BIT_RA_TRY_RATE_AGG_LMT_V1_8197F(v))
+
+/* 2 REG_MACID_SLEEP2_8197F */
+
+#define BIT_SHIFT_MACID95_64PKTSLEEP_8197F 0
+#define BIT_MASK_MACID95_64PKTSLEEP_8197F 0xffffffffL
+#define BIT_MACID95_64PKTSLEEP_8197F(x)                                        \
+	(((x) & BIT_MASK_MACID95_64PKTSLEEP_8197F)                             \
+	 << BIT_SHIFT_MACID95_64PKTSLEEP_8197F)
+#define BITS_MACID95_64PKTSLEEP_8197F                                          \
+	(BIT_MASK_MACID95_64PKTSLEEP_8197F                                     \
+	 << BIT_SHIFT_MACID95_64PKTSLEEP_8197F)
+#define BIT_CLEAR_MACID95_64PKTSLEEP_8197F(x)                                  \
+	((x) & (~BITS_MACID95_64PKTSLEEP_8197F))
+#define BIT_GET_MACID95_64PKTSLEEP_8197F(x)                                    \
+	(((x) >> BIT_SHIFT_MACID95_64PKTSLEEP_8197F) &                         \
+	 BIT_MASK_MACID95_64PKTSLEEP_8197F)
+#define BIT_SET_MACID95_64PKTSLEEP_8197F(x, v)                                 \
+	(BIT_CLEAR_MACID95_64PKTSLEEP_8197F(x) |                               \
+	 BIT_MACID95_64PKTSLEEP_8197F(v))
+
+/* 2 REG_MACID_SLEEP_8197F */
+
+#define BIT_SHIFT_MACID31_0_PKTSLEEP_8197F 0
+#define BIT_MASK_MACID31_0_PKTSLEEP_8197F 0xffffffffL
+#define BIT_MACID31_0_PKTSLEEP_8197F(x)                                        \
+	(((x) & BIT_MASK_MACID31_0_PKTSLEEP_8197F)                             \
+	 << BIT_SHIFT_MACID31_0_PKTSLEEP_8197F)
+#define BITS_MACID31_0_PKTSLEEP_8197F                                          \
+	(BIT_MASK_MACID31_0_PKTSLEEP_8197F                                     \
+	 << BIT_SHIFT_MACID31_0_PKTSLEEP_8197F)
+#define BIT_CLEAR_MACID31_0_PKTSLEEP_8197F(x)                                  \
+	((x) & (~BITS_MACID31_0_PKTSLEEP_8197F))
+#define BIT_GET_MACID31_0_PKTSLEEP_8197F(x)                                    \
+	(((x) >> BIT_SHIFT_MACID31_0_PKTSLEEP_8197F) &                         \
+	 BIT_MASK_MACID31_0_PKTSLEEP_8197F)
+#define BIT_SET_MACID31_0_PKTSLEEP_8197F(x, v)                                 \
+	(BIT_CLEAR_MACID31_0_PKTSLEEP_8197F(x) |                               \
+	 BIT_MACID31_0_PKTSLEEP_8197F(v))
+
+/* 2 REG_HW_SEQ0_8197F */
+
+#define BIT_SHIFT_HW_SSN_SEQ0_8197F 0
+#define BIT_MASK_HW_SSN_SEQ0_8197F 0xfff
+#define BIT_HW_SSN_SEQ0_8197F(x)                                               \
+	(((x) & BIT_MASK_HW_SSN_SEQ0_8197F) << BIT_SHIFT_HW_SSN_SEQ0_8197F)
+#define BITS_HW_SSN_SEQ0_8197F                                                 \
+	(BIT_MASK_HW_SSN_SEQ0_8197F << BIT_SHIFT_HW_SSN_SEQ0_8197F)
+#define BIT_CLEAR_HW_SSN_SEQ0_8197F(x) ((x) & (~BITS_HW_SSN_SEQ0_8197F))
+#define BIT_GET_HW_SSN_SEQ0_8197F(x)                                           \
+	(((x) >> BIT_SHIFT_HW_SSN_SEQ0_8197F) & BIT_MASK_HW_SSN_SEQ0_8197F)
+#define BIT_SET_HW_SSN_SEQ0_8197F(x, v)                                        \
+	(BIT_CLEAR_HW_SSN_SEQ0_8197F(x) | BIT_HW_SSN_SEQ0_8197F(v))
+
+/* 2 REG_HW_SEQ1_8197F */
+
+#define BIT_SHIFT_HW_SSN_SEQ1_8197F 0
+#define BIT_MASK_HW_SSN_SEQ1_8197F 0xfff
+#define BIT_HW_SSN_SEQ1_8197F(x)                                               \
+	(((x) & BIT_MASK_HW_SSN_SEQ1_8197F) << BIT_SHIFT_HW_SSN_SEQ1_8197F)
+#define BITS_HW_SSN_SEQ1_8197F                                                 \
+	(BIT_MASK_HW_SSN_SEQ1_8197F << BIT_SHIFT_HW_SSN_SEQ1_8197F)
+#define BIT_CLEAR_HW_SSN_SEQ1_8197F(x) ((x) & (~BITS_HW_SSN_SEQ1_8197F))
+#define BIT_GET_HW_SSN_SEQ1_8197F(x)                                           \
+	(((x) >> BIT_SHIFT_HW_SSN_SEQ1_8197F) & BIT_MASK_HW_SSN_SEQ1_8197F)
+#define BIT_SET_HW_SSN_SEQ1_8197F(x, v)                                        \
+	(BIT_CLEAR_HW_SSN_SEQ1_8197F(x) | BIT_HW_SSN_SEQ1_8197F(v))
+
+/* 2 REG_HW_SEQ2_8197F */
+
+#define BIT_SHIFT_HW_SSN_SEQ2_8197F 0
+#define BIT_MASK_HW_SSN_SEQ2_8197F 0xfff
+#define BIT_HW_SSN_SEQ2_8197F(x)                                               \
+	(((x) & BIT_MASK_HW_SSN_SEQ2_8197F) << BIT_SHIFT_HW_SSN_SEQ2_8197F)
+#define BITS_HW_SSN_SEQ2_8197F                                                 \
+	(BIT_MASK_HW_SSN_SEQ2_8197F << BIT_SHIFT_HW_SSN_SEQ2_8197F)
+#define BIT_CLEAR_HW_SSN_SEQ2_8197F(x) ((x) & (~BITS_HW_SSN_SEQ2_8197F))
+#define BIT_GET_HW_SSN_SEQ2_8197F(x)                                           \
+	(((x) >> BIT_SHIFT_HW_SSN_SEQ2_8197F) & BIT_MASK_HW_SSN_SEQ2_8197F)
+#define BIT_SET_HW_SSN_SEQ2_8197F(x, v)                                        \
+	(BIT_CLEAR_HW_SSN_SEQ2_8197F(x) | BIT_HW_SSN_SEQ2_8197F(v))
+
+/* 2 REG_HW_SEQ3_8197F */
+
+#define BIT_SHIFT_CSI_HWSSN_SEL_8197F 12
+#define BIT_MASK_CSI_HWSSN_SEL_8197F 0x3
+#define BIT_CSI_HWSSN_SEL_8197F(x)                                             \
+	(((x) & BIT_MASK_CSI_HWSSN_SEL_8197F) << BIT_SHIFT_CSI_HWSSN_SEL_8197F)
+#define BITS_CSI_HWSSN_SEL_8197F                                               \
+	(BIT_MASK_CSI_HWSSN_SEL_8197F << BIT_SHIFT_CSI_HWSSN_SEL_8197F)
+#define BIT_CLEAR_CSI_HWSSN_SEL_8197F(x) ((x) & (~BITS_CSI_HWSSN_SEL_8197F))
+#define BIT_GET_CSI_HWSSN_SEL_8197F(x)                                         \
+	(((x) >> BIT_SHIFT_CSI_HWSSN_SEL_8197F) & BIT_MASK_CSI_HWSSN_SEL_8197F)
+#define BIT_SET_CSI_HWSSN_SEL_8197F(x, v)                                      \
+	(BIT_CLEAR_CSI_HWSSN_SEL_8197F(x) | BIT_CSI_HWSSN_SEL_8197F(v))
+
+#define BIT_SHIFT_HW_SSN_SEQ3_8197F 0
+#define BIT_MASK_HW_SSN_SEQ3_8197F 0xfff
+#define BIT_HW_SSN_SEQ3_8197F(x)                                               \
+	(((x) & BIT_MASK_HW_SSN_SEQ3_8197F) << BIT_SHIFT_HW_SSN_SEQ3_8197F)
+#define BITS_HW_SSN_SEQ3_8197F                                                 \
+	(BIT_MASK_HW_SSN_SEQ3_8197F << BIT_SHIFT_HW_SSN_SEQ3_8197F)
+#define BIT_CLEAR_HW_SSN_SEQ3_8197F(x) ((x) & (~BITS_HW_SSN_SEQ3_8197F))
+#define BIT_GET_HW_SSN_SEQ3_8197F(x)                                           \
+	(((x) >> BIT_SHIFT_HW_SSN_SEQ3_8197F) & BIT_MASK_HW_SSN_SEQ3_8197F)
+#define BIT_SET_HW_SSN_SEQ3_8197F(x, v)                                        \
+	(BIT_CLEAR_HW_SSN_SEQ3_8197F(x) | BIT_HW_SSN_SEQ3_8197F(v))
+
+/* 2 REG_NULL_PKT_STATUS_V1_8197F */
+
+#define BIT_SHIFT_PTCL_TOTAL_PG_V1_8197F 2
+#define BIT_MASK_PTCL_TOTAL_PG_V1_8197F 0x1fff
+#define BIT_PTCL_TOTAL_PG_V1_8197F(x)                                          \
+	(((x) & BIT_MASK_PTCL_TOTAL_PG_V1_8197F)                               \
+	 << BIT_SHIFT_PTCL_TOTAL_PG_V1_8197F)
+#define BITS_PTCL_TOTAL_PG_V1_8197F                                            \
+	(BIT_MASK_PTCL_TOTAL_PG_V1_8197F << BIT_SHIFT_PTCL_TOTAL_PG_V1_8197F)
+#define BIT_CLEAR_PTCL_TOTAL_PG_V1_8197F(x)                                    \
+	((x) & (~BITS_PTCL_TOTAL_PG_V1_8197F))
+#define BIT_GET_PTCL_TOTAL_PG_V1_8197F(x)                                      \
+	(((x) >> BIT_SHIFT_PTCL_TOTAL_PG_V1_8197F) &                           \
+	 BIT_MASK_PTCL_TOTAL_PG_V1_8197F)
+#define BIT_SET_PTCL_TOTAL_PG_V1_8197F(x, v)                                   \
+	(BIT_CLEAR_PTCL_TOTAL_PG_V1_8197F(x) | BIT_PTCL_TOTAL_PG_V1_8197F(v))
+
+#define BIT_TX_NULL_1_8197F BIT(1)
+#define BIT_TX_NULL_0_8197F BIT(0)
+
+/* 2 REG_PTCL_ERR_STATUS_8197F */
+#define BIT_PTCL_RATE_TABLE_INVALID_8197F BIT(7)
+#define BIT_FTM_T2R_ERROR_8197F BIT(6)
+#define BIT_PTCL_ERR0_8197F BIT(5)
+#define BIT_PTCL_ERR1_8197F BIT(4)
+#define BIT_PTCL_ERR2_8197F BIT(3)
+#define BIT_PTCL_ERR3_8197F BIT(2)
+#define BIT_PTCL_ERR4_8197F BIT(1)
+#define BIT_PTCL_ERR5_8197F BIT(0)
+
+/* 2 REG_NULL_PKT_STATUS_EXTEND_8197F */
+#define BIT_CLI3_TX_NULL_1_8197F BIT(7)
+#define BIT_CLI3_TX_NULL_0_8197F BIT(6)
+#define BIT_CLI2_TX_NULL_1_8197F BIT(5)
+#define BIT_CLI2_TX_NULL_0_8197F BIT(4)
+#define BIT_CLI1_TX_NULL_1_8197F BIT(3)
+#define BIT_CLI1_TX_NULL_0_8197F BIT(2)
+#define BIT_CLI0_TX_NULL_1_8197F BIT(1)
+#define BIT_CLI0_TX_NULL_0_8197F BIT(0)
+
+/* 2 REG_VIDEO_ENHANCEMENT_FUN_8197F */
+#define BIT_VIDEO_JUST_DROP_8197F BIT(1)
+#define BIT_VIDEO_ENHANCEMENT_FUN_EN_8197F BIT(0)
+
+/* 2 REG_BT_POLLUTE_PKT_CNT_8197F */
+
+#define BIT_SHIFT_BT_POLLUTE_PKT_CNT_8197F 0
+#define BIT_MASK_BT_POLLUTE_PKT_CNT_8197F 0xffff
+#define BIT_BT_POLLUTE_PKT_CNT_8197F(x)                                        \
+	(((x) & BIT_MASK_BT_POLLUTE_PKT_CNT_8197F)                             \
+	 << BIT_SHIFT_BT_POLLUTE_PKT_CNT_8197F)
+#define BITS_BT_POLLUTE_PKT_CNT_8197F                                          \
+	(BIT_MASK_BT_POLLUTE_PKT_CNT_8197F                                     \
+	 << BIT_SHIFT_BT_POLLUTE_PKT_CNT_8197F)
+#define BIT_CLEAR_BT_POLLUTE_PKT_CNT_8197F(x)                                  \
+	((x) & (~BITS_BT_POLLUTE_PKT_CNT_8197F))
+#define BIT_GET_BT_POLLUTE_PKT_CNT_8197F(x)                                    \
+	(((x) >> BIT_SHIFT_BT_POLLUTE_PKT_CNT_8197F) &                         \
+	 BIT_MASK_BT_POLLUTE_PKT_CNT_8197F)
+#define BIT_SET_BT_POLLUTE_PKT_CNT_8197F(x, v)                                 \
+	(BIT_CLEAR_BT_POLLUTE_PKT_CNT_8197F(x) |                               \
+	 BIT_BT_POLLUTE_PKT_CNT_8197F(v))
+
+/* 2 REG_NOT_VALID_8197F */
+
+/* 2 REG_PTCL_DBG_8197F */
+
+#define BIT_SHIFT_PTCL_DBG_8197F 0
+#define BIT_MASK_PTCL_DBG_8197F 0xffffffffL
+#define BIT_PTCL_DBG_8197F(x)                                                  \
+	(((x) & BIT_MASK_PTCL_DBG_8197F) << BIT_SHIFT_PTCL_DBG_8197F)
+#define BITS_PTCL_DBG_8197F                                                    \
+	(BIT_MASK_PTCL_DBG_8197F << BIT_SHIFT_PTCL_DBG_8197F)
+#define BIT_CLEAR_PTCL_DBG_8197F(x) ((x) & (~BITS_PTCL_DBG_8197F))
+#define BIT_GET_PTCL_DBG_8197F(x)                                              \
+	(((x) >> BIT_SHIFT_PTCL_DBG_8197F) & BIT_MASK_PTCL_DBG_8197F)
+#define BIT_SET_PTCL_DBG_8197F(x, v)                                           \
+	(BIT_CLEAR_PTCL_DBG_8197F(x) | BIT_PTCL_DBG_8197F(v))
+
+/* 2 REG_TXOP_EXTRA_CTRL_8197F */
+#define BIT_TXOP_EFFICIENCY_EN_8197F BIT(0)
+
+/* 2 REG_NOT_VALID_8197F */
+
+/* 2 REG_CPUMGQ_TIMER_CTRL2_8197F */
+
+#define BIT_SHIFT_TRI_HEAD_ADDR_8197F 16
+#define BIT_MASK_TRI_HEAD_ADDR_8197F 0xfff
+#define BIT_TRI_HEAD_ADDR_8197F(x)                                             \
+	(((x) & BIT_MASK_TRI_HEAD_ADDR_8197F) << BIT_SHIFT_TRI_HEAD_ADDR_8197F)
+#define BITS_TRI_HEAD_ADDR_8197F                                               \
+	(BIT_MASK_TRI_HEAD_ADDR_8197F << BIT_SHIFT_TRI_HEAD_ADDR_8197F)
+#define BIT_CLEAR_TRI_HEAD_ADDR_8197F(x) ((x) & (~BITS_TRI_HEAD_ADDR_8197F))
+#define BIT_GET_TRI_HEAD_ADDR_8197F(x)                                         \
+	(((x) >> BIT_SHIFT_TRI_HEAD_ADDR_8197F) & BIT_MASK_TRI_HEAD_ADDR_8197F)
+#define BIT_SET_TRI_HEAD_ADDR_8197F(x, v)                                      \
+	(BIT_CLEAR_TRI_HEAD_ADDR_8197F(x) | BIT_TRI_HEAD_ADDR_8197F(v))
+
+#define BIT_DROP_TH_EN_8197F BIT(8)
+
+#define BIT_SHIFT_DROP_TH_8197F 0
+#define BIT_MASK_DROP_TH_8197F 0xff
+#define BIT_DROP_TH_8197F(x)                                                   \
+	(((x) & BIT_MASK_DROP_TH_8197F) << BIT_SHIFT_DROP_TH_8197F)
+#define BITS_DROP_TH_8197F (BIT_MASK_DROP_TH_8197F << BIT_SHIFT_DROP_TH_8197F)
+#define BIT_CLEAR_DROP_TH_8197F(x) ((x) & (~BITS_DROP_TH_8197F))
+#define BIT_GET_DROP_TH_8197F(x)                                               \
+	(((x) >> BIT_SHIFT_DROP_TH_8197F) & BIT_MASK_DROP_TH_8197F)
+#define BIT_SET_DROP_TH_8197F(x, v)                                            \
+	(BIT_CLEAR_DROP_TH_8197F(x) | BIT_DROP_TH_8197F(v))
+
+/* 2 REG_NOT_VALID_8197F */
+
+/* 2 REG_DUMMY_PAGE4_8197F */
+#define BIT_MOREDATA_CTRL2_EN_V2_8197F BIT(19)
+#define BIT_MOREDATA_CTRL1_EN_V2_8197F BIT(18)
+#define BIT_PKTIN_MOREDATA_REPLACE_ENABLE_8197F BIT(16)
+
+/* 2 REG_NOT_VALID_8197F */
+
+/* 2 REG_Q0_Q1_INFO_8197F */
+#define BIT_QUEUE_MACID_AC_NOT_THE_SAME_8197F BIT(31)
+
+#define BIT_SHIFT_GTAB_ID_8197F 28
+#define BIT_MASK_GTAB_ID_8197F 0x7
+#define BIT_GTAB_ID_8197F(x)                                                   \
+	(((x) & BIT_MASK_GTAB_ID_8197F) << BIT_SHIFT_GTAB_ID_8197F)
+#define BITS_GTAB_ID_8197F (BIT_MASK_GTAB_ID_8197F << BIT_SHIFT_GTAB_ID_8197F)
+#define BIT_CLEAR_GTAB_ID_8197F(x) ((x) & (~BITS_GTAB_ID_8197F))
+#define BIT_GET_GTAB_ID_8197F(x)                                               \
+	(((x) >> BIT_SHIFT_GTAB_ID_8197F) & BIT_MASK_GTAB_ID_8197F)
+#define BIT_SET_GTAB_ID_8197F(x, v)                                            \
+	(BIT_CLEAR_GTAB_ID_8197F(x) | BIT_GTAB_ID_8197F(v))
+
+#define BIT_SHIFT_AC1_PKT_INFO_8197F 16
+#define BIT_MASK_AC1_PKT_INFO_8197F 0xfff
+#define BIT_AC1_PKT_INFO_8197F(x)                                              \
+	(((x) & BIT_MASK_AC1_PKT_INFO_8197F) << BIT_SHIFT_AC1_PKT_INFO_8197F)
+#define BITS_AC1_PKT_INFO_8197F                                                \
+	(BIT_MASK_AC1_PKT_INFO_8197F << BIT_SHIFT_AC1_PKT_INFO_8197F)
+#define BIT_CLEAR_AC1_PKT_INFO_8197F(x) ((x) & (~BITS_AC1_PKT_INFO_8197F))
+#define BIT_GET_AC1_PKT_INFO_8197F(x)                                          \
+	(((x) >> BIT_SHIFT_AC1_PKT_INFO_8197F) & BIT_MASK_AC1_PKT_INFO_8197F)
+#define BIT_SET_AC1_PKT_INFO_8197F(x, v)                                       \
+	(BIT_CLEAR_AC1_PKT_INFO_8197F(x) | BIT_AC1_PKT_INFO_8197F(v))
+
+#define BIT_QUEUE_MACID_AC_NOT_THE_SAME_V1_8197F BIT(15)
+
+#define BIT_SHIFT_GTAB_ID_V1_8197F 12
+#define BIT_MASK_GTAB_ID_V1_8197F 0x7
+#define BIT_GTAB_ID_V1_8197F(x)                                                \
+	(((x) & BIT_MASK_GTAB_ID_V1_8197F) << BIT_SHIFT_GTAB_ID_V1_8197F)
+#define BITS_GTAB_ID_V1_8197F                                                  \
+	(BIT_MASK_GTAB_ID_V1_8197F << BIT_SHIFT_GTAB_ID_V1_8197F)
+#define BIT_CLEAR_GTAB_ID_V1_8197F(x) ((x) & (~BITS_GTAB_ID_V1_8197F))
+#define BIT_GET_GTAB_ID_V1_8197F(x)                                            \
+	(((x) >> BIT_SHIFT_GTAB_ID_V1_8197F) & BIT_MASK_GTAB_ID_V1_8197F)
+#define BIT_SET_GTAB_ID_V1_8197F(x, v)                                         \
+	(BIT_CLEAR_GTAB_ID_V1_8197F(x) | BIT_GTAB_ID_V1_8197F(v))
+
+#define BIT_SHIFT_AC0_PKT_INFO_8197F 0
+#define BIT_MASK_AC0_PKT_INFO_8197F 0xfff
+#define BIT_AC0_PKT_INFO_8197F(x)                                              \
+	(((x) & BIT_MASK_AC0_PKT_INFO_8197F) << BIT_SHIFT_AC0_PKT_INFO_8197F)
+#define BITS_AC0_PKT_INFO_8197F                                                \
+	(BIT_MASK_AC0_PKT_INFO_8197F << BIT_SHIFT_AC0_PKT_INFO_8197F)
+#define BIT_CLEAR_AC0_PKT_INFO_8197F(x) ((x) & (~BITS_AC0_PKT_INFO_8197F))
+#define BIT_GET_AC0_PKT_INFO_8197F(x)                                          \
+	(((x) >> BIT_SHIFT_AC0_PKT_INFO_8197F) & BIT_MASK_AC0_PKT_INFO_8197F)
+#define BIT_SET_AC0_PKT_INFO_8197F(x, v)                                       \
+	(BIT_CLEAR_AC0_PKT_INFO_8197F(x) | BIT_AC0_PKT_INFO_8197F(v))
+
+/* 2 REG_Q2_Q3_INFO_8197F */
+#define BIT_QUEUE_MACID_AC_NOT_THE_SAME_8197F BIT(31)
+
+#define BIT_SHIFT_GTAB_ID_8197F 28
+#define BIT_MASK_GTAB_ID_8197F 0x7
+#define BIT_GTAB_ID_8197F(x)                                                   \
+	(((x) & BIT_MASK_GTAB_ID_8197F) << BIT_SHIFT_GTAB_ID_8197F)
+#define BITS_GTAB_ID_8197F (BIT_MASK_GTAB_ID_8197F << BIT_SHIFT_GTAB_ID_8197F)
+#define BIT_CLEAR_GTAB_ID_8197F(x) ((x) & (~BITS_GTAB_ID_8197F))
+#define BIT_GET_GTAB_ID_8197F(x)                                               \
+	(((x) >> BIT_SHIFT_GTAB_ID_8197F) & BIT_MASK_GTAB_ID_8197F)
+#define BIT_SET_GTAB_ID_8197F(x, v)                                            \
+	(BIT_CLEAR_GTAB_ID_8197F(x) | BIT_GTAB_ID_8197F(v))
+
+#define BIT_SHIFT_AC3_PKT_INFO_8197F 16
+#define BIT_MASK_AC3_PKT_INFO_8197F 0xfff
+#define BIT_AC3_PKT_INFO_8197F(x)                                              \
+	(((x) & BIT_MASK_AC3_PKT_INFO_8197F) << BIT_SHIFT_AC3_PKT_INFO_8197F)
+#define BITS_AC3_PKT_INFO_8197F                                                \
+	(BIT_MASK_AC3_PKT_INFO_8197F << BIT_SHIFT_AC3_PKT_INFO_8197F)
+#define BIT_CLEAR_AC3_PKT_INFO_8197F(x) ((x) & (~BITS_AC3_PKT_INFO_8197F))
+#define BIT_GET_AC3_PKT_INFO_8197F(x)                                          \
+	(((x) >> BIT_SHIFT_AC3_PKT_INFO_8197F) & BIT_MASK_AC3_PKT_INFO_8197F)
+#define BIT_SET_AC3_PKT_INFO_8197F(x, v)                                       \
+	(BIT_CLEAR_AC3_PKT_INFO_8197F(x) | BIT_AC3_PKT_INFO_8197F(v))
+
+#define BIT_QUEUE_MACID_AC_NOT_THE_SAME_V1_8197F BIT(15)
+
+#define BIT_SHIFT_GTAB_ID_V1_8197F 12
+#define BIT_MASK_GTAB_ID_V1_8197F 0x7
+#define BIT_GTAB_ID_V1_8197F(x)                                                \
+	(((x) & BIT_MASK_GTAB_ID_V1_8197F) << BIT_SHIFT_GTAB_ID_V1_8197F)
+#define BITS_GTAB_ID_V1_8197F                                                  \
+	(BIT_MASK_GTAB_ID_V1_8197F << BIT_SHIFT_GTAB_ID_V1_8197F)
+#define BIT_CLEAR_GTAB_ID_V1_8197F(x) ((x) & (~BITS_GTAB_ID_V1_8197F))
+#define BIT_GET_GTAB_ID_V1_8197F(x)                                            \
+	(((x) >> BIT_SHIFT_GTAB_ID_V1_8197F) & BIT_MASK_GTAB_ID_V1_8197F)
+#define BIT_SET_GTAB_ID_V1_8197F(x, v)                                         \
+	(BIT_CLEAR_GTAB_ID_V1_8197F(x) | BIT_GTAB_ID_V1_8197F(v))
+
+#define BIT_SHIFT_AC2_PKT_INFO_8197F 0
+#define BIT_MASK_AC2_PKT_INFO_8197F 0xfff
+#define BIT_AC2_PKT_INFO_8197F(x)                                              \
+	(((x) & BIT_MASK_AC2_PKT_INFO_8197F) << BIT_SHIFT_AC2_PKT_INFO_8197F)
+#define BITS_AC2_PKT_INFO_8197F                                                \
+	(BIT_MASK_AC2_PKT_INFO_8197F << BIT_SHIFT_AC2_PKT_INFO_8197F)
+#define BIT_CLEAR_AC2_PKT_INFO_8197F(x) ((x) & (~BITS_AC2_PKT_INFO_8197F))
+#define BIT_GET_AC2_PKT_INFO_8197F(x)                                          \
+	(((x) >> BIT_SHIFT_AC2_PKT_INFO_8197F) & BIT_MASK_AC2_PKT_INFO_8197F)
+#define BIT_SET_AC2_PKT_INFO_8197F(x, v)                                       \
+	(BIT_CLEAR_AC2_PKT_INFO_8197F(x) | BIT_AC2_PKT_INFO_8197F(v))
+
+/* 2 REG_Q4_Q5_INFO_8197F */
+#define BIT_QUEUE_MACID_AC_NOT_THE_SAME_8197F BIT(31)
+
+#define BIT_SHIFT_GTAB_ID_8197F 28
+#define BIT_MASK_GTAB_ID_8197F 0x7
+#define BIT_GTAB_ID_8197F(x)                                                   \
+	(((x) & BIT_MASK_GTAB_ID_8197F) << BIT_SHIFT_GTAB_ID_8197F)
+#define BITS_GTAB_ID_8197F (BIT_MASK_GTAB_ID_8197F << BIT_SHIFT_GTAB_ID_8197F)
+#define BIT_CLEAR_GTAB_ID_8197F(x) ((x) & (~BITS_GTAB_ID_8197F))
+#define BIT_GET_GTAB_ID_8197F(x)                                               \
+	(((x) >> BIT_SHIFT_GTAB_ID_8197F) & BIT_MASK_GTAB_ID_8197F)
+#define BIT_SET_GTAB_ID_8197F(x, v)                                            \
+	(BIT_CLEAR_GTAB_ID_8197F(x) | BIT_GTAB_ID_8197F(v))
+
+#define BIT_SHIFT_AC5_PKT_INFO_8197F 16
+#define BIT_MASK_AC5_PKT_INFO_8197F 0xfff
+#define BIT_AC5_PKT_INFO_8197F(x)                                              \
+	(((x) & BIT_MASK_AC5_PKT_INFO_8197F) << BIT_SHIFT_AC5_PKT_INFO_8197F)
+#define BITS_AC5_PKT_INFO_8197F                                                \
+	(BIT_MASK_AC5_PKT_INFO_8197F << BIT_SHIFT_AC5_PKT_INFO_8197F)
+#define BIT_CLEAR_AC5_PKT_INFO_8197F(x) ((x) & (~BITS_AC5_PKT_INFO_8197F))
+#define BIT_GET_AC5_PKT_INFO_8197F(x)                                          \
+	(((x) >> BIT_SHIFT_AC5_PKT_INFO_8197F) & BIT_MASK_AC5_PKT_INFO_8197F)
+#define BIT_SET_AC5_PKT_INFO_8197F(x, v)                                       \
+	(BIT_CLEAR_AC5_PKT_INFO_8197F(x) | BIT_AC5_PKT_INFO_8197F(v))
+
+#define BIT_QUEUE_MACID_AC_NOT_THE_SAME_V1_8197F BIT(15)
+
+#define BIT_SHIFT_GTAB_ID_V1_8197F 12
+#define BIT_MASK_GTAB_ID_V1_8197F 0x7
+#define BIT_GTAB_ID_V1_8197F(x)                                                \
+	(((x) & BIT_MASK_GTAB_ID_V1_8197F) << BIT_SHIFT_GTAB_ID_V1_8197F)
+#define BITS_GTAB_ID_V1_8197F                                                  \
+	(BIT_MASK_GTAB_ID_V1_8197F << BIT_SHIFT_GTAB_ID_V1_8197F)
+#define BIT_CLEAR_GTAB_ID_V1_8197F(x) ((x) & (~BITS_GTAB_ID_V1_8197F))
+#define BIT_GET_GTAB_ID_V1_8197F(x)                                            \
+	(((x) >> BIT_SHIFT_GTAB_ID_V1_8197F) & BIT_MASK_GTAB_ID_V1_8197F)
+#define BIT_SET_GTAB_ID_V1_8197F(x, v)                                         \
+	(BIT_CLEAR_GTAB_ID_V1_8197F(x) | BIT_GTAB_ID_V1_8197F(v))
+
+#define BIT_SHIFT_AC4_PKT_INFO_8197F 0
+#define BIT_MASK_AC4_PKT_INFO_8197F 0xfff
+#define BIT_AC4_PKT_INFO_8197F(x)                                              \
+	(((x) & BIT_MASK_AC4_PKT_INFO_8197F) << BIT_SHIFT_AC4_PKT_INFO_8197F)
+#define BITS_AC4_PKT_INFO_8197F                                                \
+	(BIT_MASK_AC4_PKT_INFO_8197F << BIT_SHIFT_AC4_PKT_INFO_8197F)
+#define BIT_CLEAR_AC4_PKT_INFO_8197F(x) ((x) & (~BITS_AC4_PKT_INFO_8197F))
+#define BIT_GET_AC4_PKT_INFO_8197F(x)                                          \
+	(((x) >> BIT_SHIFT_AC4_PKT_INFO_8197F) & BIT_MASK_AC4_PKT_INFO_8197F)
+#define BIT_SET_AC4_PKT_INFO_8197F(x, v)                                       \
+	(BIT_CLEAR_AC4_PKT_INFO_8197F(x) | BIT_AC4_PKT_INFO_8197F(v))
+
+/* 2 REG_Q6_Q7_INFO_8197F */
+#define BIT_QUEUE_MACID_AC_NOT_THE_SAME_8197F BIT(31)
+
+#define BIT_SHIFT_GTAB_ID_8197F 28
+#define BIT_MASK_GTAB_ID_8197F 0x7
+#define BIT_GTAB_ID_8197F(x)                                                   \
+	(((x) & BIT_MASK_GTAB_ID_8197F) << BIT_SHIFT_GTAB_ID_8197F)
+#define BITS_GTAB_ID_8197F (BIT_MASK_GTAB_ID_8197F << BIT_SHIFT_GTAB_ID_8197F)
+#define BIT_CLEAR_GTAB_ID_8197F(x) ((x) & (~BITS_GTAB_ID_8197F))
+#define BIT_GET_GTAB_ID_8197F(x)                                               \
+	(((x) >> BIT_SHIFT_GTAB_ID_8197F) & BIT_MASK_GTAB_ID_8197F)
+#define BIT_SET_GTAB_ID_8197F(x, v)                                            \
+	(BIT_CLEAR_GTAB_ID_8197F(x) | BIT_GTAB_ID_8197F(v))
+
+#define BIT_SHIFT_AC7_PKT_INFO_8197F 16
+#define BIT_MASK_AC7_PKT_INFO_8197F 0xfff
+#define BIT_AC7_PKT_INFO_8197F(x)                                              \
+	(((x) & BIT_MASK_AC7_PKT_INFO_8197F) << BIT_SHIFT_AC7_PKT_INFO_8197F)
+#define BITS_AC7_PKT_INFO_8197F                                                \
+	(BIT_MASK_AC7_PKT_INFO_8197F << BIT_SHIFT_AC7_PKT_INFO_8197F)
+#define BIT_CLEAR_AC7_PKT_INFO_8197F(x) ((x) & (~BITS_AC7_PKT_INFO_8197F))
+#define BIT_GET_AC7_PKT_INFO_8197F(x)                                          \
+	(((x) >> BIT_SHIFT_AC7_PKT_INFO_8197F) & BIT_MASK_AC7_PKT_INFO_8197F)
+#define BIT_SET_AC7_PKT_INFO_8197F(x, v)                                       \
+	(BIT_CLEAR_AC7_PKT_INFO_8197F(x) | BIT_AC7_PKT_INFO_8197F(v))
+
+#define BIT_QUEUE_MACID_AC_NOT_THE_SAME_V1_8197F BIT(15)
+
+#define BIT_SHIFT_GTAB_ID_V1_8197F 12
+#define BIT_MASK_GTAB_ID_V1_8197F 0x7
+#define BIT_GTAB_ID_V1_8197F(x)                                                \
+	(((x) & BIT_MASK_GTAB_ID_V1_8197F) << BIT_SHIFT_GTAB_ID_V1_8197F)
+#define BITS_GTAB_ID_V1_8197F                                                  \
+	(BIT_MASK_GTAB_ID_V1_8197F << BIT_SHIFT_GTAB_ID_V1_8197F)
+#define BIT_CLEAR_GTAB_ID_V1_8197F(x) ((x) & (~BITS_GTAB_ID_V1_8197F))
+#define BIT_GET_GTAB_ID_V1_8197F(x)                                            \
+	(((x) >> BIT_SHIFT_GTAB_ID_V1_8197F) & BIT_MASK_GTAB_ID_V1_8197F)
+#define BIT_SET_GTAB_ID_V1_8197F(x, v)                                         \
+	(BIT_CLEAR_GTAB_ID_V1_8197F(x) | BIT_GTAB_ID_V1_8197F(v))
+
+#define BIT_SHIFT_AC6_PKT_INFO_8197F 0
+#define BIT_MASK_AC6_PKT_INFO_8197F 0xfff
+#define BIT_AC6_PKT_INFO_8197F(x)                                              \
+	(((x) & BIT_MASK_AC6_PKT_INFO_8197F) << BIT_SHIFT_AC6_PKT_INFO_8197F)
+#define BITS_AC6_PKT_INFO_8197F                                                \
+	(BIT_MASK_AC6_PKT_INFO_8197F << BIT_SHIFT_AC6_PKT_INFO_8197F)
+#define BIT_CLEAR_AC6_PKT_INFO_8197F(x) ((x) & (~BITS_AC6_PKT_INFO_8197F))
+#define BIT_GET_AC6_PKT_INFO_8197F(x)                                          \
+	(((x) >> BIT_SHIFT_AC6_PKT_INFO_8197F) & BIT_MASK_AC6_PKT_INFO_8197F)
+#define BIT_SET_AC6_PKT_INFO_8197F(x, v)                                       \
+	(BIT_CLEAR_AC6_PKT_INFO_8197F(x) | BIT_AC6_PKT_INFO_8197F(v))
+
+/* 2 REG_MGQ_HIQ_INFO_8197F */
+
+#define BIT_SHIFT_HIQ_PKT_INFO_8197F 16
+#define BIT_MASK_HIQ_PKT_INFO_8197F 0xfff
+#define BIT_HIQ_PKT_INFO_8197F(x)                                              \
+	(((x) & BIT_MASK_HIQ_PKT_INFO_8197F) << BIT_SHIFT_HIQ_PKT_INFO_8197F)
+#define BITS_HIQ_PKT_INFO_8197F                                                \
+	(BIT_MASK_HIQ_PKT_INFO_8197F << BIT_SHIFT_HIQ_PKT_INFO_8197F)
+#define BIT_CLEAR_HIQ_PKT_INFO_8197F(x) ((x) & (~BITS_HIQ_PKT_INFO_8197F))
+#define BIT_GET_HIQ_PKT_INFO_8197F(x)                                          \
+	(((x) >> BIT_SHIFT_HIQ_PKT_INFO_8197F) & BIT_MASK_HIQ_PKT_INFO_8197F)
+#define BIT_SET_HIQ_PKT_INFO_8197F(x, v)                                       \
+	(BIT_CLEAR_HIQ_PKT_INFO_8197F(x) | BIT_HIQ_PKT_INFO_8197F(v))
+
+#define BIT_SHIFT_MGQ_PKT_INFO_8197F 0
+#define BIT_MASK_MGQ_PKT_INFO_8197F 0xfff
+#define BIT_MGQ_PKT_INFO_8197F(x)                                              \
+	(((x) & BIT_MASK_MGQ_PKT_INFO_8197F) << BIT_SHIFT_MGQ_PKT_INFO_8197F)
+#define BITS_MGQ_PKT_INFO_8197F                                                \
+	(BIT_MASK_MGQ_PKT_INFO_8197F << BIT_SHIFT_MGQ_PKT_INFO_8197F)
+#define BIT_CLEAR_MGQ_PKT_INFO_8197F(x) ((x) & (~BITS_MGQ_PKT_INFO_8197F))
+#define BIT_GET_MGQ_PKT_INFO_8197F(x)                                          \
+	(((x) >> BIT_SHIFT_MGQ_PKT_INFO_8197F) & BIT_MASK_MGQ_PKT_INFO_8197F)
+#define BIT_SET_MGQ_PKT_INFO_8197F(x, v)                                       \
+	(BIT_CLEAR_MGQ_PKT_INFO_8197F(x) | BIT_MGQ_PKT_INFO_8197F(v))
+
+/* 2 REG_CMDQ_BCNQ_INFO_8197F */
+
+#define BIT_SHIFT_BCNQ_PKT_INFO_V1_8197F 16
+#define BIT_MASK_BCNQ_PKT_INFO_V1_8197F 0xfff
+#define BIT_BCNQ_PKT_INFO_V1_8197F(x)                                          \
+	(((x) & BIT_MASK_BCNQ_PKT_INFO_V1_8197F)                               \
+	 << BIT_SHIFT_BCNQ_PKT_INFO_V1_8197F)
+#define BITS_BCNQ_PKT_INFO_V1_8197F                                            \
+	(BIT_MASK_BCNQ_PKT_INFO_V1_8197F << BIT_SHIFT_BCNQ_PKT_INFO_V1_8197F)
+#define BIT_CLEAR_BCNQ_PKT_INFO_V1_8197F(x)                                    \
+	((x) & (~BITS_BCNQ_PKT_INFO_V1_8197F))
+#define BIT_GET_BCNQ_PKT_INFO_V1_8197F(x)                                      \
+	(((x) >> BIT_SHIFT_BCNQ_PKT_INFO_V1_8197F) &                           \
+	 BIT_MASK_BCNQ_PKT_INFO_V1_8197F)
+#define BIT_SET_BCNQ_PKT_INFO_V1_8197F(x, v)                                   \
+	(BIT_CLEAR_BCNQ_PKT_INFO_V1_8197F(x) | BIT_BCNQ_PKT_INFO_V1_8197F(v))
+
+#define BIT_SHIFT_CMDQ_PKT_INFO_V1_8197F 0
+#define BIT_MASK_CMDQ_PKT_INFO_V1_8197F 0xfff
+#define BIT_CMDQ_PKT_INFO_V1_8197F(x)                                          \
+	(((x) & BIT_MASK_CMDQ_PKT_INFO_V1_8197F)                               \
+	 << BIT_SHIFT_CMDQ_PKT_INFO_V1_8197F)
+#define BITS_CMDQ_PKT_INFO_V1_8197F                                            \
+	(BIT_MASK_CMDQ_PKT_INFO_V1_8197F << BIT_SHIFT_CMDQ_PKT_INFO_V1_8197F)
+#define BIT_CLEAR_CMDQ_PKT_INFO_V1_8197F(x)                                    \
+	((x) & (~BITS_CMDQ_PKT_INFO_V1_8197F))
+#define BIT_GET_CMDQ_PKT_INFO_V1_8197F(x)                                      \
+	(((x) >> BIT_SHIFT_CMDQ_PKT_INFO_V1_8197F) &                           \
+	 BIT_MASK_CMDQ_PKT_INFO_V1_8197F)
+#define BIT_SET_CMDQ_PKT_INFO_V1_8197F(x, v)                                   \
+	(BIT_CLEAR_CMDQ_PKT_INFO_V1_8197F(x) | BIT_CMDQ_PKT_INFO_V1_8197F(v))
+
+/* 2 REG_USEREG_SETTING_8197F */
+#define BIT_NDPA_USEREG_8197F BIT(21)
+
+#define BIT_SHIFT_RETRY_USEREG_8197F 19
+#define BIT_MASK_RETRY_USEREG_8197F 0x3
+#define BIT_RETRY_USEREG_8197F(x)                                              \
+	(((x) & BIT_MASK_RETRY_USEREG_8197F) << BIT_SHIFT_RETRY_USEREG_8197F)
+#define BITS_RETRY_USEREG_8197F                                                \
+	(BIT_MASK_RETRY_USEREG_8197F << BIT_SHIFT_RETRY_USEREG_8197F)
+#define BIT_CLEAR_RETRY_USEREG_8197F(x) ((x) & (~BITS_RETRY_USEREG_8197F))
+#define BIT_GET_RETRY_USEREG_8197F(x)                                          \
+	(((x) >> BIT_SHIFT_RETRY_USEREG_8197F) & BIT_MASK_RETRY_USEREG_8197F)
+#define BIT_SET_RETRY_USEREG_8197F(x, v)                                       \
+	(BIT_CLEAR_RETRY_USEREG_8197F(x) | BIT_RETRY_USEREG_8197F(v))
+
+#define BIT_SHIFT_TRYPKT_USEREG_8197F 17
+#define BIT_MASK_TRYPKT_USEREG_8197F 0x3
+#define BIT_TRYPKT_USEREG_8197F(x)                                             \
+	(((x) & BIT_MASK_TRYPKT_USEREG_8197F) << BIT_SHIFT_TRYPKT_USEREG_8197F)
+#define BITS_TRYPKT_USEREG_8197F                                               \
+	(BIT_MASK_TRYPKT_USEREG_8197F << BIT_SHIFT_TRYPKT_USEREG_8197F)
+#define BIT_CLEAR_TRYPKT_USEREG_8197F(x) ((x) & (~BITS_TRYPKT_USEREG_8197F))
+#define BIT_GET_TRYPKT_USEREG_8197F(x)                                         \
+	(((x) >> BIT_SHIFT_TRYPKT_USEREG_8197F) & BIT_MASK_TRYPKT_USEREG_8197F)
+#define BIT_SET_TRYPKT_USEREG_8197F(x, v)                                      \
+	(BIT_CLEAR_TRYPKT_USEREG_8197F(x) | BIT_TRYPKT_USEREG_8197F(v))
+
+#define BIT_CTLPKT_USEREG_8197F BIT(16)
+
+/* 2 REG_AESIV_SETTING_8197F */
+
+#define BIT_SHIFT_AESIV_OFFSET_8197F 0
+#define BIT_MASK_AESIV_OFFSET_8197F 0xfff
+#define BIT_AESIV_OFFSET_8197F(x)                                              \
+	(((x) & BIT_MASK_AESIV_OFFSET_8197F) << BIT_SHIFT_AESIV_OFFSET_8197F)
+#define BITS_AESIV_OFFSET_8197F                                                \
+	(BIT_MASK_AESIV_OFFSET_8197F << BIT_SHIFT_AESIV_OFFSET_8197F)
+#define BIT_CLEAR_AESIV_OFFSET_8197F(x) ((x) & (~BITS_AESIV_OFFSET_8197F))
+#define BIT_GET_AESIV_OFFSET_8197F(x)                                          \
+	(((x) >> BIT_SHIFT_AESIV_OFFSET_8197F) & BIT_MASK_AESIV_OFFSET_8197F)
+#define BIT_SET_AESIV_OFFSET_8197F(x, v)                                       \
+	(BIT_CLEAR_AESIV_OFFSET_8197F(x) | BIT_AESIV_OFFSET_8197F(v))
+
+/* 2 REG_BF0_TIME_SETTING_8197F */
+#define BIT_BF0_TIMER_SET_8197F BIT(31)
+#define BIT_BF0_TIMER_CLR_8197F BIT(30)
+#define BIT_BF0_UPDATE_EN_8197F BIT(29)
+#define BIT_BF0_TIMER_EN_8197F BIT(28)
+
+#define BIT_SHIFT_BF0_PRETIME_OVER_8197F 16
+#define BIT_MASK_BF0_PRETIME_OVER_8197F 0xfff
+#define BIT_BF0_PRETIME_OVER_8197F(x)                                          \
+	(((x) & BIT_MASK_BF0_PRETIME_OVER_8197F)                               \
+	 << BIT_SHIFT_BF0_PRETIME_OVER_8197F)
+#define BITS_BF0_PRETIME_OVER_8197F                                            \
+	(BIT_MASK_BF0_PRETIME_OVER_8197F << BIT_SHIFT_BF0_PRETIME_OVER_8197F)
+#define BIT_CLEAR_BF0_PRETIME_OVER_8197F(x)                                    \
+	((x) & (~BITS_BF0_PRETIME_OVER_8197F))
+#define BIT_GET_BF0_PRETIME_OVER_8197F(x)                                      \
+	(((x) >> BIT_SHIFT_BF0_PRETIME_OVER_8197F) &                           \
+	 BIT_MASK_BF0_PRETIME_OVER_8197F)
+#define BIT_SET_BF0_PRETIME_OVER_8197F(x, v)                                   \
+	(BIT_CLEAR_BF0_PRETIME_OVER_8197F(x) | BIT_BF0_PRETIME_OVER_8197F(v))
+
+#define BIT_SHIFT_BF0_LIFETIME_8197F 0
+#define BIT_MASK_BF0_LIFETIME_8197F 0xffff
+#define BIT_BF0_LIFETIME_8197F(x)                                              \
+	(((x) & BIT_MASK_BF0_LIFETIME_8197F) << BIT_SHIFT_BF0_LIFETIME_8197F)
+#define BITS_BF0_LIFETIME_8197F                                                \
+	(BIT_MASK_BF0_LIFETIME_8197F << BIT_SHIFT_BF0_LIFETIME_8197F)
+#define BIT_CLEAR_BF0_LIFETIME_8197F(x) ((x) & (~BITS_BF0_LIFETIME_8197F))
+#define BIT_GET_BF0_LIFETIME_8197F(x)                                          \
+	(((x) >> BIT_SHIFT_BF0_LIFETIME_8197F) & BIT_MASK_BF0_LIFETIME_8197F)
+#define BIT_SET_BF0_LIFETIME_8197F(x, v)                                       \
+	(BIT_CLEAR_BF0_LIFETIME_8197F(x) | BIT_BF0_LIFETIME_8197F(v))
+
+/* 2 REG_BF1_TIME_SETTING_8197F */
+#define BIT_BF1_TIMER_SET_8197F BIT(31)
+#define BIT_BF1_TIMER_CLR_8197F BIT(30)
+#define BIT_BF1_UPDATE_EN_8197F BIT(29)
+#define BIT_BF1_TIMER_EN_8197F BIT(28)
+
+#define BIT_SHIFT_BF1_PRETIME_OVER_8197F 16
+#define BIT_MASK_BF1_PRETIME_OVER_8197F 0xfff
+#define BIT_BF1_PRETIME_OVER_8197F(x)                                          \
+	(((x) & BIT_MASK_BF1_PRETIME_OVER_8197F)                               \
+	 << BIT_SHIFT_BF1_PRETIME_OVER_8197F)
+#define BITS_BF1_PRETIME_OVER_8197F                                            \
+	(BIT_MASK_BF1_PRETIME_OVER_8197F << BIT_SHIFT_BF1_PRETIME_OVER_8197F)
+#define BIT_CLEAR_BF1_PRETIME_OVER_8197F(x)                                    \
+	((x) & (~BITS_BF1_PRETIME_OVER_8197F))
+#define BIT_GET_BF1_PRETIME_OVER_8197F(x)                                      \
+	(((x) >> BIT_SHIFT_BF1_PRETIME_OVER_8197F) &                           \
+	 BIT_MASK_BF1_PRETIME_OVER_8197F)
+#define BIT_SET_BF1_PRETIME_OVER_8197F(x, v)                                   \
+	(BIT_CLEAR_BF1_PRETIME_OVER_8197F(x) | BIT_BF1_PRETIME_OVER_8197F(v))
+
+#define BIT_SHIFT_BF1_LIFETIME_8197F 0
+#define BIT_MASK_BF1_LIFETIME_8197F 0xffff
+#define BIT_BF1_LIFETIME_8197F(x)                                              \
+	(((x) & BIT_MASK_BF1_LIFETIME_8197F) << BIT_SHIFT_BF1_LIFETIME_8197F)
+#define BITS_BF1_LIFETIME_8197F                                                \
+	(BIT_MASK_BF1_LIFETIME_8197F << BIT_SHIFT_BF1_LIFETIME_8197F)
+#define BIT_CLEAR_BF1_LIFETIME_8197F(x) ((x) & (~BITS_BF1_LIFETIME_8197F))
+#define BIT_GET_BF1_LIFETIME_8197F(x)                                          \
+	(((x) >> BIT_SHIFT_BF1_LIFETIME_8197F) & BIT_MASK_BF1_LIFETIME_8197F)
+#define BIT_SET_BF1_LIFETIME_8197F(x, v)                                       \
+	(BIT_CLEAR_BF1_LIFETIME_8197F(x) | BIT_BF1_LIFETIME_8197F(v))
+
+/* 2 REG_BF_TIMEOUT_EN_8197F */
+#define BIT_EN_VHT_LDPC_8197F BIT(9)
+#define BIT_EN_HT_LDPC_8197F BIT(8)
+#define BIT_BF1_TIMEOUT_EN_8197F BIT(1)
+#define BIT_BF0_TIMEOUT_EN_8197F BIT(0)
+
+/* 2 REG_MACID_RELEASE0_8197F */
+
+#define BIT_SHIFT_MACID31_0_RELEASE_8197F 0
+#define BIT_MASK_MACID31_0_RELEASE_8197F 0xffffffffL
+#define BIT_MACID31_0_RELEASE_8197F(x)                                         \
+	(((x) & BIT_MASK_MACID31_0_RELEASE_8197F)                              \
+	 << BIT_SHIFT_MACID31_0_RELEASE_8197F)
+#define BITS_MACID31_0_RELEASE_8197F                                           \
+	(BIT_MASK_MACID31_0_RELEASE_8197F << BIT_SHIFT_MACID31_0_RELEASE_8197F)
+#define BIT_CLEAR_MACID31_0_RELEASE_8197F(x)                                   \
+	((x) & (~BITS_MACID31_0_RELEASE_8197F))
+#define BIT_GET_MACID31_0_RELEASE_8197F(x)                                     \
+	(((x) >> BIT_SHIFT_MACID31_0_RELEASE_8197F) &                          \
+	 BIT_MASK_MACID31_0_RELEASE_8197F)
+#define BIT_SET_MACID31_0_RELEASE_8197F(x, v)                                  \
+	(BIT_CLEAR_MACID31_0_RELEASE_8197F(x) | BIT_MACID31_0_RELEASE_8197F(v))
+
+/* 2 REG_MACID_RELEASE1_8197F */
+
+#define BIT_SHIFT_MACID63_32_RELEASE_8197F 0
+#define BIT_MASK_MACID63_32_RELEASE_8197F 0xffffffffL
+#define BIT_MACID63_32_RELEASE_8197F(x)                                        \
+	(((x) & BIT_MASK_MACID63_32_RELEASE_8197F)                             \
+	 << BIT_SHIFT_MACID63_32_RELEASE_8197F)
+#define BITS_MACID63_32_RELEASE_8197F                                          \
+	(BIT_MASK_MACID63_32_RELEASE_8197F                                     \
+	 << BIT_SHIFT_MACID63_32_RELEASE_8197F)
+#define BIT_CLEAR_MACID63_32_RELEASE_8197F(x)                                  \
+	((x) & (~BITS_MACID63_32_RELEASE_8197F))
+#define BIT_GET_MACID63_32_RELEASE_8197F(x)                                    \
+	(((x) >> BIT_SHIFT_MACID63_32_RELEASE_8197F) &                         \
+	 BIT_MASK_MACID63_32_RELEASE_8197F)
+#define BIT_SET_MACID63_32_RELEASE_8197F(x, v)                                 \
+	(BIT_CLEAR_MACID63_32_RELEASE_8197F(x) |                               \
+	 BIT_MACID63_32_RELEASE_8197F(v))
+
+/* 2 REG_MACID_RELEASE2_8197F */
+
+#define BIT_SHIFT_MACID95_64_RELEASE_8197F 0
+#define BIT_MASK_MACID95_64_RELEASE_8197F 0xffffffffL
+#define BIT_MACID95_64_RELEASE_8197F(x)                                        \
+	(((x) & BIT_MASK_MACID95_64_RELEASE_8197F)                             \
+	 << BIT_SHIFT_MACID95_64_RELEASE_8197F)
+#define BITS_MACID95_64_RELEASE_8197F                                          \
+	(BIT_MASK_MACID95_64_RELEASE_8197F                                     \
+	 << BIT_SHIFT_MACID95_64_RELEASE_8197F)
+#define BIT_CLEAR_MACID95_64_RELEASE_8197F(x)                                  \
+	((x) & (~BITS_MACID95_64_RELEASE_8197F))
+#define BIT_GET_MACID95_64_RELEASE_8197F(x)                                    \
+	(((x) >> BIT_SHIFT_MACID95_64_RELEASE_8197F) &                         \
+	 BIT_MASK_MACID95_64_RELEASE_8197F)
+#define BIT_SET_MACID95_64_RELEASE_8197F(x, v)                                 \
+	(BIT_CLEAR_MACID95_64_RELEASE_8197F(x) |                               \
+	 BIT_MACID95_64_RELEASE_8197F(v))
+
+/* 2 REG_MACID_RELEASE3_8197F */
+
+#define BIT_SHIFT_MACID127_96_RELEASE_8197F 0
+#define BIT_MASK_MACID127_96_RELEASE_8197F 0xffffffffL
+#define BIT_MACID127_96_RELEASE_8197F(x)                                       \
+	(((x) & BIT_MASK_MACID127_96_RELEASE_8197F)                            \
+	 << BIT_SHIFT_MACID127_96_RELEASE_8197F)
+#define BITS_MACID127_96_RELEASE_8197F                                         \
+	(BIT_MASK_MACID127_96_RELEASE_8197F                                    \
+	 << BIT_SHIFT_MACID127_96_RELEASE_8197F)
+#define BIT_CLEAR_MACID127_96_RELEASE_8197F(x)                                 \
+	((x) & (~BITS_MACID127_96_RELEASE_8197F))
+#define BIT_GET_MACID127_96_RELEASE_8197F(x)                                   \
+	(((x) >> BIT_SHIFT_MACID127_96_RELEASE_8197F) &                        \
+	 BIT_MASK_MACID127_96_RELEASE_8197F)
+#define BIT_SET_MACID127_96_RELEASE_8197F(x, v)                                \
+	(BIT_CLEAR_MACID127_96_RELEASE_8197F(x) |                              \
+	 BIT_MACID127_96_RELEASE_8197F(v))
+
+/* 2 REG_MACID_RELEASE_SETTING_8197F */
+#define BIT_MACID_VALUE_8197F BIT(7)
+
+#define BIT_SHIFT_MACID_OFFSET_8197F 0
+#define BIT_MASK_MACID_OFFSET_8197F 0x7f
+#define BIT_MACID_OFFSET_8197F(x)                                              \
+	(((x) & BIT_MASK_MACID_OFFSET_8197F) << BIT_SHIFT_MACID_OFFSET_8197F)
+#define BITS_MACID_OFFSET_8197F                                                \
+	(BIT_MASK_MACID_OFFSET_8197F << BIT_SHIFT_MACID_OFFSET_8197F)
+#define BIT_CLEAR_MACID_OFFSET_8197F(x) ((x) & (~BITS_MACID_OFFSET_8197F))
+#define BIT_GET_MACID_OFFSET_8197F(x)                                          \
+	(((x) >> BIT_SHIFT_MACID_OFFSET_8197F) & BIT_MASK_MACID_OFFSET_8197F)
+#define BIT_SET_MACID_OFFSET_8197F(x, v)                                       \
+	(BIT_CLEAR_MACID_OFFSET_8197F(x) | BIT_MACID_OFFSET_8197F(v))
+
+/* 2 REG_FAST_EDCA_VOVI_SETTING_8197F */
+
+#define BIT_SHIFT_VI_FAST_EDCA_TO_8197F 24
+#define BIT_MASK_VI_FAST_EDCA_TO_8197F 0xff
+#define BIT_VI_FAST_EDCA_TO_8197F(x)                                           \
+	(((x) & BIT_MASK_VI_FAST_EDCA_TO_8197F)                                \
+	 << BIT_SHIFT_VI_FAST_EDCA_TO_8197F)
+#define BITS_VI_FAST_EDCA_TO_8197F                                             \
+	(BIT_MASK_VI_FAST_EDCA_TO_8197F << BIT_SHIFT_VI_FAST_EDCA_TO_8197F)
+#define BIT_CLEAR_VI_FAST_EDCA_TO_8197F(x) ((x) & (~BITS_VI_FAST_EDCA_TO_8197F))
+#define BIT_GET_VI_FAST_EDCA_TO_8197F(x)                                       \
+	(((x) >> BIT_SHIFT_VI_FAST_EDCA_TO_8197F) &                            \
+	 BIT_MASK_VI_FAST_EDCA_TO_8197F)
+#define BIT_SET_VI_FAST_EDCA_TO_8197F(x, v)                                    \
+	(BIT_CLEAR_VI_FAST_EDCA_TO_8197F(x) | BIT_VI_FAST_EDCA_TO_8197F(v))
+
+#define BIT_VI_THRESHOLD_SEL_8197F BIT(23)
+
+#define BIT_SHIFT_VI_FAST_EDCA_PKT_TH_8197F 16
+#define BIT_MASK_VI_FAST_EDCA_PKT_TH_8197F 0x7f
+#define BIT_VI_FAST_EDCA_PKT_TH_8197F(x)                                       \
+	(((x) & BIT_MASK_VI_FAST_EDCA_PKT_TH_8197F)                            \
+	 << BIT_SHIFT_VI_FAST_EDCA_PKT_TH_8197F)
+#define BITS_VI_FAST_EDCA_PKT_TH_8197F                                         \
+	(BIT_MASK_VI_FAST_EDCA_PKT_TH_8197F                                    \
+	 << BIT_SHIFT_VI_FAST_EDCA_PKT_TH_8197F)
+#define BIT_CLEAR_VI_FAST_EDCA_PKT_TH_8197F(x)                                 \
+	((x) & (~BITS_VI_FAST_EDCA_PKT_TH_8197F))
+#define BIT_GET_VI_FAST_EDCA_PKT_TH_8197F(x)                                   \
+	(((x) >> BIT_SHIFT_VI_FAST_EDCA_PKT_TH_8197F) &                        \
+	 BIT_MASK_VI_FAST_EDCA_PKT_TH_8197F)
+#define BIT_SET_VI_FAST_EDCA_PKT_TH_8197F(x, v)                                \
+	(BIT_CLEAR_VI_FAST_EDCA_PKT_TH_8197F(x) |                              \
+	 BIT_VI_FAST_EDCA_PKT_TH_8197F(v))
+
+#define BIT_SHIFT_VO_FAST_EDCA_TO_8197F 8
+#define BIT_MASK_VO_FAST_EDCA_TO_8197F 0xff
+#define BIT_VO_FAST_EDCA_TO_8197F(x)                                           \
+	(((x) & BIT_MASK_VO_FAST_EDCA_TO_8197F)                                \
+	 << BIT_SHIFT_VO_FAST_EDCA_TO_8197F)
+#define BITS_VO_FAST_EDCA_TO_8197F                                             \
+	(BIT_MASK_VO_FAST_EDCA_TO_8197F << BIT_SHIFT_VO_FAST_EDCA_TO_8197F)
+#define BIT_CLEAR_VO_FAST_EDCA_TO_8197F(x) ((x) & (~BITS_VO_FAST_EDCA_TO_8197F))
+#define BIT_GET_VO_FAST_EDCA_TO_8197F(x)                                       \
+	(((x) >> BIT_SHIFT_VO_FAST_EDCA_TO_8197F) &                            \
+	 BIT_MASK_VO_FAST_EDCA_TO_8197F)
+#define BIT_SET_VO_FAST_EDCA_TO_8197F(x, v)                                    \
+	(BIT_CLEAR_VO_FAST_EDCA_TO_8197F(x) | BIT_VO_FAST_EDCA_TO_8197F(v))
+
+#define BIT_VO_THRESHOLD_SEL_8197F BIT(7)
+
+#define BIT_SHIFT_VO_FAST_EDCA_PKT_TH_8197F 0
+#define BIT_MASK_VO_FAST_EDCA_PKT_TH_8197F 0x7f
+#define BIT_VO_FAST_EDCA_PKT_TH_8197F(x)                                       \
+	(((x) & BIT_MASK_VO_FAST_EDCA_PKT_TH_8197F)                            \
+	 << BIT_SHIFT_VO_FAST_EDCA_PKT_TH_8197F)
+#define BITS_VO_FAST_EDCA_PKT_TH_8197F                                         \
+	(BIT_MASK_VO_FAST_EDCA_PKT_TH_8197F                                    \
+	 << BIT_SHIFT_VO_FAST_EDCA_PKT_TH_8197F)
+#define BIT_CLEAR_VO_FAST_EDCA_PKT_TH_8197F(x)                                 \
+	((x) & (~BITS_VO_FAST_EDCA_PKT_TH_8197F))
+#define BIT_GET_VO_FAST_EDCA_PKT_TH_8197F(x)                                   \
+	(((x) >> BIT_SHIFT_VO_FAST_EDCA_PKT_TH_8197F) &                        \
+	 BIT_MASK_VO_FAST_EDCA_PKT_TH_8197F)
+#define BIT_SET_VO_FAST_EDCA_PKT_TH_8197F(x, v)                                \
+	(BIT_CLEAR_VO_FAST_EDCA_PKT_TH_8197F(x) |                              \
+	 BIT_VO_FAST_EDCA_PKT_TH_8197F(v))
+
+/* 2 REG_FAST_EDCA_BEBK_SETTING_8197F */
+
+#define BIT_SHIFT_BK_FAST_EDCA_TO_8197F 24
+#define BIT_MASK_BK_FAST_EDCA_TO_8197F 0xff
+#define BIT_BK_FAST_EDCA_TO_8197F(x)                                           \
+	(((x) & BIT_MASK_BK_FAST_EDCA_TO_8197F)                                \
+	 << BIT_SHIFT_BK_FAST_EDCA_TO_8197F)
+#define BITS_BK_FAST_EDCA_TO_8197F                                             \
+	(BIT_MASK_BK_FAST_EDCA_TO_8197F << BIT_SHIFT_BK_FAST_EDCA_TO_8197F)
+#define BIT_CLEAR_BK_FAST_EDCA_TO_8197F(x) ((x) & (~BITS_BK_FAST_EDCA_TO_8197F))
+#define BIT_GET_BK_FAST_EDCA_TO_8197F(x)                                       \
+	(((x) >> BIT_SHIFT_BK_FAST_EDCA_TO_8197F) &                            \
+	 BIT_MASK_BK_FAST_EDCA_TO_8197F)
+#define BIT_SET_BK_FAST_EDCA_TO_8197F(x, v)                                    \
+	(BIT_CLEAR_BK_FAST_EDCA_TO_8197F(x) | BIT_BK_FAST_EDCA_TO_8197F(v))
+
+#define BIT_BK_THRESHOLD_SEL_8197F BIT(23)
+
+#define BIT_SHIFT_BK_FAST_EDCA_PKT_TH_8197F 16
+#define BIT_MASK_BK_FAST_EDCA_PKT_TH_8197F 0x7f
+#define BIT_BK_FAST_EDCA_PKT_TH_8197F(x)                                       \
+	(((x) & BIT_MASK_BK_FAST_EDCA_PKT_TH_8197F)                            \
+	 << BIT_SHIFT_BK_FAST_EDCA_PKT_TH_8197F)
+#define BITS_BK_FAST_EDCA_PKT_TH_8197F                                         \
+	(BIT_MASK_BK_FAST_EDCA_PKT_TH_8197F                                    \
+	 << BIT_SHIFT_BK_FAST_EDCA_PKT_TH_8197F)
+#define BIT_CLEAR_BK_FAST_EDCA_PKT_TH_8197F(x)                                 \
+	((x) & (~BITS_BK_FAST_EDCA_PKT_TH_8197F))
+#define BIT_GET_BK_FAST_EDCA_PKT_TH_8197F(x)                                   \
+	(((x) >> BIT_SHIFT_BK_FAST_EDCA_PKT_TH_8197F) &                        \
+	 BIT_MASK_BK_FAST_EDCA_PKT_TH_8197F)
+#define BIT_SET_BK_FAST_EDCA_PKT_TH_8197F(x, v)                                \
+	(BIT_CLEAR_BK_FAST_EDCA_PKT_TH_8197F(x) |                              \
+	 BIT_BK_FAST_EDCA_PKT_TH_8197F(v))
+
+#define BIT_SHIFT_BE_FAST_EDCA_TO_8197F 8
+#define BIT_MASK_BE_FAST_EDCA_TO_8197F 0xff
+#define BIT_BE_FAST_EDCA_TO_8197F(x)                                           \
+	(((x) & BIT_MASK_BE_FAST_EDCA_TO_8197F)                                \
+	 << BIT_SHIFT_BE_FAST_EDCA_TO_8197F)
+#define BITS_BE_FAST_EDCA_TO_8197F                                             \
+	(BIT_MASK_BE_FAST_EDCA_TO_8197F << BIT_SHIFT_BE_FAST_EDCA_TO_8197F)
+#define BIT_CLEAR_BE_FAST_EDCA_TO_8197F(x) ((x) & (~BITS_BE_FAST_EDCA_TO_8197F))
+#define BIT_GET_BE_FAST_EDCA_TO_8197F(x)                                       \
+	(((x) >> BIT_SHIFT_BE_FAST_EDCA_TO_8197F) &                            \
+	 BIT_MASK_BE_FAST_EDCA_TO_8197F)
+#define BIT_SET_BE_FAST_EDCA_TO_8197F(x, v)                                    \
+	(BIT_CLEAR_BE_FAST_EDCA_TO_8197F(x) | BIT_BE_FAST_EDCA_TO_8197F(v))
+
+#define BIT_BE_THRESHOLD_SEL_8197F BIT(7)
+
+#define BIT_SHIFT_BE_FAST_EDCA_PKT_TH_8197F 0
+#define BIT_MASK_BE_FAST_EDCA_PKT_TH_8197F 0x7f
+#define BIT_BE_FAST_EDCA_PKT_TH_8197F(x)                                       \
+	(((x) & BIT_MASK_BE_FAST_EDCA_PKT_TH_8197F)                            \
+	 << BIT_SHIFT_BE_FAST_EDCA_PKT_TH_8197F)
+#define BITS_BE_FAST_EDCA_PKT_TH_8197F                                         \
+	(BIT_MASK_BE_FAST_EDCA_PKT_TH_8197F                                    \
+	 << BIT_SHIFT_BE_FAST_EDCA_PKT_TH_8197F)
+#define BIT_CLEAR_BE_FAST_EDCA_PKT_TH_8197F(x)                                 \
+	((x) & (~BITS_BE_FAST_EDCA_PKT_TH_8197F))
+#define BIT_GET_BE_FAST_EDCA_PKT_TH_8197F(x)                                   \
+	(((x) >> BIT_SHIFT_BE_FAST_EDCA_PKT_TH_8197F) &                        \
+	 BIT_MASK_BE_FAST_EDCA_PKT_TH_8197F)
+#define BIT_SET_BE_FAST_EDCA_PKT_TH_8197F(x, v)                                \
+	(BIT_CLEAR_BE_FAST_EDCA_PKT_TH_8197F(x) |                              \
+	 BIT_BE_FAST_EDCA_PKT_TH_8197F(v))
+
+/* 2 REG_MACID_DROP0_8197F */
+
+#define BIT_SHIFT_MACID31_0_DROP_8197F 0
+#define BIT_MASK_MACID31_0_DROP_8197F 0xffffffffL
+#define BIT_MACID31_0_DROP_8197F(x)                                            \
+	(((x) & BIT_MASK_MACID31_0_DROP_8197F)                                 \
+	 << BIT_SHIFT_MACID31_0_DROP_8197F)
+#define BITS_MACID31_0_DROP_8197F                                              \
+	(BIT_MASK_MACID31_0_DROP_8197F << BIT_SHIFT_MACID31_0_DROP_8197F)
+#define BIT_CLEAR_MACID31_0_DROP_8197F(x) ((x) & (~BITS_MACID31_0_DROP_8197F))
+#define BIT_GET_MACID31_0_DROP_8197F(x)                                        \
+	(((x) >> BIT_SHIFT_MACID31_0_DROP_8197F) &                             \
+	 BIT_MASK_MACID31_0_DROP_8197F)
+#define BIT_SET_MACID31_0_DROP_8197F(x, v)                                     \
+	(BIT_CLEAR_MACID31_0_DROP_8197F(x) | BIT_MACID31_0_DROP_8197F(v))
+
+/* 2 REG_MACID_DROP1_8197F */
+
+#define BIT_SHIFT_MACID63_32_DROP_8197F 0
+#define BIT_MASK_MACID63_32_DROP_8197F 0xffffffffL
+#define BIT_MACID63_32_DROP_8197F(x)                                           \
+	(((x) & BIT_MASK_MACID63_32_DROP_8197F)                                \
+	 << BIT_SHIFT_MACID63_32_DROP_8197F)
+#define BITS_MACID63_32_DROP_8197F                                             \
+	(BIT_MASK_MACID63_32_DROP_8197F << BIT_SHIFT_MACID63_32_DROP_8197F)
+#define BIT_CLEAR_MACID63_32_DROP_8197F(x) ((x) & (~BITS_MACID63_32_DROP_8197F))
+#define BIT_GET_MACID63_32_DROP_8197F(x)                                       \
+	(((x) >> BIT_SHIFT_MACID63_32_DROP_8197F) &                            \
+	 BIT_MASK_MACID63_32_DROP_8197F)
+#define BIT_SET_MACID63_32_DROP_8197F(x, v)                                    \
+	(BIT_CLEAR_MACID63_32_DROP_8197F(x) | BIT_MACID63_32_DROP_8197F(v))
+
+/* 2 REG_MACID_DROP2_8197F */
+
+#define BIT_SHIFT_MACID95_64_DROP_8197F 0
+#define BIT_MASK_MACID95_64_DROP_8197F 0xffffffffL
+#define BIT_MACID95_64_DROP_8197F(x)                                           \
+	(((x) & BIT_MASK_MACID95_64_DROP_8197F)                                \
+	 << BIT_SHIFT_MACID95_64_DROP_8197F)
+#define BITS_MACID95_64_DROP_8197F                                             \
+	(BIT_MASK_MACID95_64_DROP_8197F << BIT_SHIFT_MACID95_64_DROP_8197F)
+#define BIT_CLEAR_MACID95_64_DROP_8197F(x) ((x) & (~BITS_MACID95_64_DROP_8197F))
+#define BIT_GET_MACID95_64_DROP_8197F(x)                                       \
+	(((x) >> BIT_SHIFT_MACID95_64_DROP_8197F) &                            \
+	 BIT_MASK_MACID95_64_DROP_8197F)
+#define BIT_SET_MACID95_64_DROP_8197F(x, v)                                    \
+	(BIT_CLEAR_MACID95_64_DROP_8197F(x) | BIT_MACID95_64_DROP_8197F(v))
+
+/* 2 REG_MACID_DROP3_8197F */
+
+#define BIT_SHIFT_MACID127_96_DROP_8197F 0
+#define BIT_MASK_MACID127_96_DROP_8197F 0xffffffffL
+#define BIT_MACID127_96_DROP_8197F(x)                                          \
+	(((x) & BIT_MASK_MACID127_96_DROP_8197F)                               \
+	 << BIT_SHIFT_MACID127_96_DROP_8197F)
+#define BITS_MACID127_96_DROP_8197F                                            \
+	(BIT_MASK_MACID127_96_DROP_8197F << BIT_SHIFT_MACID127_96_DROP_8197F)
+#define BIT_CLEAR_MACID127_96_DROP_8197F(x)                                    \
+	((x) & (~BITS_MACID127_96_DROP_8197F))
+#define BIT_GET_MACID127_96_DROP_8197F(x)                                      \
+	(((x) >> BIT_SHIFT_MACID127_96_DROP_8197F) &                           \
+	 BIT_MASK_MACID127_96_DROP_8197F)
+#define BIT_SET_MACID127_96_DROP_8197F(x, v)                                   \
+	(BIT_CLEAR_MACID127_96_DROP_8197F(x) | BIT_MACID127_96_DROP_8197F(v))
+
+/* 2 REG_R_MACID_RELEASE_SUCCESS_0_8197F */
+
+#define BIT_SHIFT_R_MACID_RELEASE_SUCCESS_0_8197F 0
+#define BIT_MASK_R_MACID_RELEASE_SUCCESS_0_8197F 0xffffffffL
+#define BIT_R_MACID_RELEASE_SUCCESS_0_8197F(x)                                 \
+	(((x) & BIT_MASK_R_MACID_RELEASE_SUCCESS_0_8197F)                      \
+	 << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_0_8197F)
+#define BITS_R_MACID_RELEASE_SUCCESS_0_8197F                                   \
+	(BIT_MASK_R_MACID_RELEASE_SUCCESS_0_8197F                              \
+	 << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_0_8197F)
+#define BIT_CLEAR_R_MACID_RELEASE_SUCCESS_0_8197F(x)                           \
+	((x) & (~BITS_R_MACID_RELEASE_SUCCESS_0_8197F))
+#define BIT_GET_R_MACID_RELEASE_SUCCESS_0_8197F(x)                             \
+	(((x) >> BIT_SHIFT_R_MACID_RELEASE_SUCCESS_0_8197F) &                  \
+	 BIT_MASK_R_MACID_RELEASE_SUCCESS_0_8197F)
+#define BIT_SET_R_MACID_RELEASE_SUCCESS_0_8197F(x, v)                          \
+	(BIT_CLEAR_R_MACID_RELEASE_SUCCESS_0_8197F(x) |                        \
+	 BIT_R_MACID_RELEASE_SUCCESS_0_8197F(v))
+
+/* 2 REG_R_MACID_RELEASE_SUCCESS_1_8197F */
+
+#define BIT_SHIFT_R_MACID_RELEASE_SUCCESS_1_8197F 0
+#define BIT_MASK_R_MACID_RELEASE_SUCCESS_1_8197F 0xffffffffL
+#define BIT_R_MACID_RELEASE_SUCCESS_1_8197F(x)                                 \
+	(((x) & BIT_MASK_R_MACID_RELEASE_SUCCESS_1_8197F)                      \
+	 << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_1_8197F)
+#define BITS_R_MACID_RELEASE_SUCCESS_1_8197F                                   \
+	(BIT_MASK_R_MACID_RELEASE_SUCCESS_1_8197F                              \
+	 << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_1_8197F)
+#define BIT_CLEAR_R_MACID_RELEASE_SUCCESS_1_8197F(x)                           \
+	((x) & (~BITS_R_MACID_RELEASE_SUCCESS_1_8197F))
+#define BIT_GET_R_MACID_RELEASE_SUCCESS_1_8197F(x)                             \
+	(((x) >> BIT_SHIFT_R_MACID_RELEASE_SUCCESS_1_8197F) &                  \
+	 BIT_MASK_R_MACID_RELEASE_SUCCESS_1_8197F)
+#define BIT_SET_R_MACID_RELEASE_SUCCESS_1_8197F(x, v)                          \
+	(BIT_CLEAR_R_MACID_RELEASE_SUCCESS_1_8197F(x) |                        \
+	 BIT_R_MACID_RELEASE_SUCCESS_1_8197F(v))
+
+/* 2 REG_R_MACID_RELEASE_SUCCESS_2_8197F */
+
+#define BIT_SHIFT_R_MACID_RELEASE_SUCCESS_2_8197F 0
+#define BIT_MASK_R_MACID_RELEASE_SUCCESS_2_8197F 0xffffffffL
+#define BIT_R_MACID_RELEASE_SUCCESS_2_8197F(x)                                 \
+	(((x) & BIT_MASK_R_MACID_RELEASE_SUCCESS_2_8197F)                      \
+	 << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_2_8197F)
+#define BITS_R_MACID_RELEASE_SUCCESS_2_8197F                                   \
+	(BIT_MASK_R_MACID_RELEASE_SUCCESS_2_8197F                              \
+	 << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_2_8197F)
+#define BIT_CLEAR_R_MACID_RELEASE_SUCCESS_2_8197F(x)                           \
+	((x) & (~BITS_R_MACID_RELEASE_SUCCESS_2_8197F))
+#define BIT_GET_R_MACID_RELEASE_SUCCESS_2_8197F(x)                             \
+	(((x) >> BIT_SHIFT_R_MACID_RELEASE_SUCCESS_2_8197F) &                  \
+	 BIT_MASK_R_MACID_RELEASE_SUCCESS_2_8197F)
+#define BIT_SET_R_MACID_RELEASE_SUCCESS_2_8197F(x, v)                          \
+	(BIT_CLEAR_R_MACID_RELEASE_SUCCESS_2_8197F(x) |                        \
+	 BIT_R_MACID_RELEASE_SUCCESS_2_8197F(v))
+
+/* 2 REG_R_MACID_RELEASE_SUCCESS_3_8197F */
+
+#define BIT_SHIFT_R_MACID_RELEASE_SUCCESS_3_8197F 0
+#define BIT_MASK_R_MACID_RELEASE_SUCCESS_3_8197F 0xffffffffL
+#define BIT_R_MACID_RELEASE_SUCCESS_3_8197F(x)                                 \
+	(((x) & BIT_MASK_R_MACID_RELEASE_SUCCESS_3_8197F)                      \
+	 << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_3_8197F)
+#define BITS_R_MACID_RELEASE_SUCCESS_3_8197F                                   \
+	(BIT_MASK_R_MACID_RELEASE_SUCCESS_3_8197F                              \
+	 << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_3_8197F)
+#define BIT_CLEAR_R_MACID_RELEASE_SUCCESS_3_8197F(x)                           \
+	((x) & (~BITS_R_MACID_RELEASE_SUCCESS_3_8197F))
+#define BIT_GET_R_MACID_RELEASE_SUCCESS_3_8197F(x)                             \
+	(((x) >> BIT_SHIFT_R_MACID_RELEASE_SUCCESS_3_8197F) &                  \
+	 BIT_MASK_R_MACID_RELEASE_SUCCESS_3_8197F)
+#define BIT_SET_R_MACID_RELEASE_SUCCESS_3_8197F(x, v)                          \
+	(BIT_CLEAR_R_MACID_RELEASE_SUCCESS_3_8197F(x) |                        \
+	 BIT_R_MACID_RELEASE_SUCCESS_3_8197F(v))
+
+/* 2 REG_MGG_FIFO_CRTL_8197F */
+#define BIT_R_MGG_FIFO_EN_8197F BIT(31)
+
+#define BIT_SHIFT_R_MGG_FIFO_PG_SIZE_8197F 28
+#define BIT_MASK_R_MGG_FIFO_PG_SIZE_8197F 0x7
+#define BIT_R_MGG_FIFO_PG_SIZE_8197F(x)                                        \
+	(((x) & BIT_MASK_R_MGG_FIFO_PG_SIZE_8197F)                             \
+	 << BIT_SHIFT_R_MGG_FIFO_PG_SIZE_8197F)
+#define BITS_R_MGG_FIFO_PG_SIZE_8197F                                          \
+	(BIT_MASK_R_MGG_FIFO_PG_SIZE_8197F                                     \
+	 << BIT_SHIFT_R_MGG_FIFO_PG_SIZE_8197F)
+#define BIT_CLEAR_R_MGG_FIFO_PG_SIZE_8197F(x)                                  \
+	((x) & (~BITS_R_MGG_FIFO_PG_SIZE_8197F))
+#define BIT_GET_R_MGG_FIFO_PG_SIZE_8197F(x)                                    \
+	(((x) >> BIT_SHIFT_R_MGG_FIFO_PG_SIZE_8197F) &                         \
+	 BIT_MASK_R_MGG_FIFO_PG_SIZE_8197F)
+#define BIT_SET_R_MGG_FIFO_PG_SIZE_8197F(x, v)                                 \
+	(BIT_CLEAR_R_MGG_FIFO_PG_SIZE_8197F(x) |                               \
+	 BIT_R_MGG_FIFO_PG_SIZE_8197F(v))
+
+#define BIT_SHIFT_R_MGG_FIFO_START_PG_8197F 16
+#define BIT_MASK_R_MGG_FIFO_START_PG_8197F 0xfff
+#define BIT_R_MGG_FIFO_START_PG_8197F(x)                                       \
+	(((x) & BIT_MASK_R_MGG_FIFO_START_PG_8197F)                            \
+	 << BIT_SHIFT_R_MGG_FIFO_START_PG_8197F)
+#define BITS_R_MGG_FIFO_START_PG_8197F                                         \
+	(BIT_MASK_R_MGG_FIFO_START_PG_8197F                                    \
+	 << BIT_SHIFT_R_MGG_FIFO_START_PG_8197F)
+#define BIT_CLEAR_R_MGG_FIFO_START_PG_8197F(x)                                 \
+	((x) & (~BITS_R_MGG_FIFO_START_PG_8197F))
+#define BIT_GET_R_MGG_FIFO_START_PG_8197F(x)                                   \
+	(((x) >> BIT_SHIFT_R_MGG_FIFO_START_PG_8197F) &                        \
+	 BIT_MASK_R_MGG_FIFO_START_PG_8197F)
+#define BIT_SET_R_MGG_FIFO_START_PG_8197F(x, v)                                \
+	(BIT_CLEAR_R_MGG_FIFO_START_PG_8197F(x) |                              \
+	 BIT_R_MGG_FIFO_START_PG_8197F(v))
+
+#define BIT_SHIFT_R_MGG_FIFO_SIZE_8197F 14
+#define BIT_MASK_R_MGG_FIFO_SIZE_8197F 0x3
+#define BIT_R_MGG_FIFO_SIZE_8197F(x)                                           \
+	(((x) & BIT_MASK_R_MGG_FIFO_SIZE_8197F)                                \
+	 << BIT_SHIFT_R_MGG_FIFO_SIZE_8197F)
+#define BITS_R_MGG_FIFO_SIZE_8197F                                             \
+	(BIT_MASK_R_MGG_FIFO_SIZE_8197F << BIT_SHIFT_R_MGG_FIFO_SIZE_8197F)
+#define BIT_CLEAR_R_MGG_FIFO_SIZE_8197F(x) ((x) & (~BITS_R_MGG_FIFO_SIZE_8197F))
+#define BIT_GET_R_MGG_FIFO_SIZE_8197F(x)                                       \
+	(((x) >> BIT_SHIFT_R_MGG_FIFO_SIZE_8197F) &                            \
+	 BIT_MASK_R_MGG_FIFO_SIZE_8197F)
+#define BIT_SET_R_MGG_FIFO_SIZE_8197F(x, v)                                    \
+	(BIT_CLEAR_R_MGG_FIFO_SIZE_8197F(x) | BIT_R_MGG_FIFO_SIZE_8197F(v))
+
+#define BIT_R_MGG_FIFO_PAUSE_8197F BIT(13)
+
+#define BIT_SHIFT_R_MGG_FIFO_RPTR_8197F 8
+#define BIT_MASK_R_MGG_FIFO_RPTR_8197F 0x1f
+#define BIT_R_MGG_FIFO_RPTR_8197F(x)                                           \
+	(((x) & BIT_MASK_R_MGG_FIFO_RPTR_8197F)                                \
+	 << BIT_SHIFT_R_MGG_FIFO_RPTR_8197F)
+#define BITS_R_MGG_FIFO_RPTR_8197F                                             \
+	(BIT_MASK_R_MGG_FIFO_RPTR_8197F << BIT_SHIFT_R_MGG_FIFO_RPTR_8197F)
+#define BIT_CLEAR_R_MGG_FIFO_RPTR_8197F(x) ((x) & (~BITS_R_MGG_FIFO_RPTR_8197F))
+#define BIT_GET_R_MGG_FIFO_RPTR_8197F(x)                                       \
+	(((x) >> BIT_SHIFT_R_MGG_FIFO_RPTR_8197F) &                            \
+	 BIT_MASK_R_MGG_FIFO_RPTR_8197F)
+#define BIT_SET_R_MGG_FIFO_RPTR_8197F(x, v)                                    \
+	(BIT_CLEAR_R_MGG_FIFO_RPTR_8197F(x) | BIT_R_MGG_FIFO_RPTR_8197F(v))
+
+#define BIT_R_MGG_FIFO_OV_8197F BIT(7)
+#define BIT_R_MGG_FIFO_WPTR_ERROR_8197F BIT(6)
+#define BIT_R_EN_CPU_LIFETIME_8197F BIT(5)
+
+#define BIT_SHIFT_R_MGG_FIFO_WPTR_8197F 0
+#define BIT_MASK_R_MGG_FIFO_WPTR_8197F 0x1f
+#define BIT_R_MGG_FIFO_WPTR_8197F(x)                                           \
+	(((x) & BIT_MASK_R_MGG_FIFO_WPTR_8197F)                                \
+	 << BIT_SHIFT_R_MGG_FIFO_WPTR_8197F)
+#define BITS_R_MGG_FIFO_WPTR_8197F                                             \
+	(BIT_MASK_R_MGG_FIFO_WPTR_8197F << BIT_SHIFT_R_MGG_FIFO_WPTR_8197F)
+#define BIT_CLEAR_R_MGG_FIFO_WPTR_8197F(x) ((x) & (~BITS_R_MGG_FIFO_WPTR_8197F))
+#define BIT_GET_R_MGG_FIFO_WPTR_8197F(x)                                       \
+	(((x) >> BIT_SHIFT_R_MGG_FIFO_WPTR_8197F) &                            \
+	 BIT_MASK_R_MGG_FIFO_WPTR_8197F)
+#define BIT_SET_R_MGG_FIFO_WPTR_8197F(x, v)                                    \
+	(BIT_CLEAR_R_MGG_FIFO_WPTR_8197F(x) | BIT_R_MGG_FIFO_WPTR_8197F(v))
+
+/* 2 REG_MGG_FIFO_INT_8197F */
+
+#define BIT_SHIFT_R_MGG_FIFO_INT_FLAG_8197F 16
+#define BIT_MASK_R_MGG_FIFO_INT_FLAG_8197F 0xffff
+#define BIT_R_MGG_FIFO_INT_FLAG_8197F(x)                                       \
+	(((x) & BIT_MASK_R_MGG_FIFO_INT_FLAG_8197F)                            \
+	 << BIT_SHIFT_R_MGG_FIFO_INT_FLAG_8197F)
+#define BITS_R_MGG_FIFO_INT_FLAG_8197F                                         \
+	(BIT_MASK_R_MGG_FIFO_INT_FLAG_8197F                                    \
+	 << BIT_SHIFT_R_MGG_FIFO_INT_FLAG_8197F)
+#define BIT_CLEAR_R_MGG_FIFO_INT_FLAG_8197F(x)                                 \
+	((x) & (~BITS_R_MGG_FIFO_INT_FLAG_8197F))
+#define BIT_GET_R_MGG_FIFO_INT_FLAG_8197F(x)                                   \
+	(((x) >> BIT_SHIFT_R_MGG_FIFO_INT_FLAG_8197F) &                        \
+	 BIT_MASK_R_MGG_FIFO_INT_FLAG_8197F)
+#define BIT_SET_R_MGG_FIFO_INT_FLAG_8197F(x, v)                                \
+	(BIT_CLEAR_R_MGG_FIFO_INT_FLAG_8197F(x) |                              \
+	 BIT_R_MGG_FIFO_INT_FLAG_8197F(v))
+
+#define BIT_SHIFT_R_MGG_FIFO_INT_MASK_8197F 0
+#define BIT_MASK_R_MGG_FIFO_INT_MASK_8197F 0xffff
+#define BIT_R_MGG_FIFO_INT_MASK_8197F(x)                                       \
+	(((x) & BIT_MASK_R_MGG_FIFO_INT_MASK_8197F)                            \
+	 << BIT_SHIFT_R_MGG_FIFO_INT_MASK_8197F)
+#define BITS_R_MGG_FIFO_INT_MASK_8197F                                         \
+	(BIT_MASK_R_MGG_FIFO_INT_MASK_8197F                                    \
+	 << BIT_SHIFT_R_MGG_FIFO_INT_MASK_8197F)
+#define BIT_CLEAR_R_MGG_FIFO_INT_MASK_8197F(x)                                 \
+	((x) & (~BITS_R_MGG_FIFO_INT_MASK_8197F))
+#define BIT_GET_R_MGG_FIFO_INT_MASK_8197F(x)                                   \
+	(((x) >> BIT_SHIFT_R_MGG_FIFO_INT_MASK_8197F) &                        \
+	 BIT_MASK_R_MGG_FIFO_INT_MASK_8197F)
+#define BIT_SET_R_MGG_FIFO_INT_MASK_8197F(x, v)                                \
+	(BIT_CLEAR_R_MGG_FIFO_INT_MASK_8197F(x) |                              \
+	 BIT_R_MGG_FIFO_INT_MASK_8197F(v))
+
+/* 2 REG_MGG_FIFO_LIFETIME_8197F */
+
+#define BIT_SHIFT_R_MGG_FIFO_LIFETIME_8197F 16
+#define BIT_MASK_R_MGG_FIFO_LIFETIME_8197F 0xffff
+#define BIT_R_MGG_FIFO_LIFETIME_8197F(x)                                       \
+	(((x) & BIT_MASK_R_MGG_FIFO_LIFETIME_8197F)                            \
+	 << BIT_SHIFT_R_MGG_FIFO_LIFETIME_8197F)
+#define BITS_R_MGG_FIFO_LIFETIME_8197F                                         \
+	(BIT_MASK_R_MGG_FIFO_LIFETIME_8197F                                    \
+	 << BIT_SHIFT_R_MGG_FIFO_LIFETIME_8197F)
+#define BIT_CLEAR_R_MGG_FIFO_LIFETIME_8197F(x)                                 \
+	((x) & (~BITS_R_MGG_FIFO_LIFETIME_8197F))
+#define BIT_GET_R_MGG_FIFO_LIFETIME_8197F(x)                                   \
+	(((x) >> BIT_SHIFT_R_MGG_FIFO_LIFETIME_8197F) &                        \
+	 BIT_MASK_R_MGG_FIFO_LIFETIME_8197F)
+#define BIT_SET_R_MGG_FIFO_LIFETIME_8197F(x, v)                                \
+	(BIT_CLEAR_R_MGG_FIFO_LIFETIME_8197F(x) |                              \
+	 BIT_R_MGG_FIFO_LIFETIME_8197F(v))
+
+#define BIT_SHIFT_R_MGG_FIFO_VALID_MAP_8197F 0
+#define BIT_MASK_R_MGG_FIFO_VALID_MAP_8197F 0xffff
+#define BIT_R_MGG_FIFO_VALID_MAP_8197F(x)                                      \
+	(((x) & BIT_MASK_R_MGG_FIFO_VALID_MAP_8197F)                           \
+	 << BIT_SHIFT_R_MGG_FIFO_VALID_MAP_8197F)
+#define BITS_R_MGG_FIFO_VALID_MAP_8197F                                        \
+	(BIT_MASK_R_MGG_FIFO_VALID_MAP_8197F                                   \
+	 << BIT_SHIFT_R_MGG_FIFO_VALID_MAP_8197F)
+#define BIT_CLEAR_R_MGG_FIFO_VALID_MAP_8197F(x)                                \
+	((x) & (~BITS_R_MGG_FIFO_VALID_MAP_8197F))
+#define BIT_GET_R_MGG_FIFO_VALID_MAP_8197F(x)                                  \
+	(((x) >> BIT_SHIFT_R_MGG_FIFO_VALID_MAP_8197F) &                       \
+	 BIT_MASK_R_MGG_FIFO_VALID_MAP_8197F)
+#define BIT_SET_R_MGG_FIFO_VALID_MAP_8197F(x, v)                               \
+	(BIT_CLEAR_R_MGG_FIFO_VALID_MAP_8197F(x) |                             \
+	 BIT_R_MGG_FIFO_VALID_MAP_8197F(v))
+
+/* 2 REG_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8197F */
+
+#define BIT_SHIFT_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8197F 0
+#define BIT_MASK_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8197F 0x7f
+#define BIT_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8197F(x)                      \
+	(((x) & BIT_MASK_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8197F)           \
+	 << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8197F)
+#define BITS_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8197F                        \
+	(BIT_MASK_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8197F                   \
+	 << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8197F)
+#define BIT_CLEAR_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8197F(x)                \
+	((x) & (~BITS_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8197F))
+#define BIT_GET_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8197F(x)                  \
+	(((x) >> BIT_SHIFT_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8197F) &       \
+	 BIT_MASK_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8197F)
+#define BIT_SET_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8197F(x, v)               \
+	(BIT_CLEAR_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8197F(x) |             \
+	 BIT_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8197F(v))
+
+/* 2 REG_SHCUT_SETTING_8197F */
+
+/* 2 REG_NOT_VALID_8197F */
+
+/* 2 REG_NOT_VALID_8197F */
+
+/* 2 REG_NOT_VALID_8197F */
+
+/* 2 REG_NOT_VALID_8197F */
+
+/* 2 REG_NOT_VALID_8197F */
+
+/* 2 REG_NOT_VALID_8197F */
+
+/* 2 REG_SHCUT_LLC_ETH_TYPE0_8197F */
+
+/* 2 REG_NOT_VALID_8197F */
+
+/* 2 REG_NOT_VALID_8197F */
+
+/* 2 REG_SHCUT_LLC_ETH_TYPE1_8197F */
+
+/* 2 REG_NOT_VALID_8197F */
+
+/* 2 REG_NOT_VALID_8197F */
+
+/* 2 REG_SHCUT_LLC_OUI0_8197F */
+
+/* 2 REG_NOT_VALID_8197F */
+
+/* 2 REG_NOT_VALID_8197F */
+
+/* 2 REG_NOT_VALID_8197F */
+
+/* 2 REG_SHCUT_LLC_OUI1_8197F */
+
+/* 2 REG_NOT_VALID_8197F */
+
+/* 2 REG_NOT_VALID_8197F */
+
+/* 2 REG_NOT_VALID_8197F */
+
+/* 2 REG_SHCUT_LLC_OUI2_8197F */
+
+/* 2 REG_NOT_VALID_8197F */
+
+/* 2 REG_NOT_VALID_8197F */
+
+/* 2 REG_NOT_VALID_8197F */
+
+/* 2 REG_SHCUT_LLC_OUI3_8197F */
+
+/* 2 REG_NOT_VALID_8197F */
+
+/* 2 REG_NOT_VALID_8197F */
+
+/* 2 REG_NOT_VALID_8197F */
+
+/* 2 REG_CHNL_INFO_CTRL_8197F */
+#define BIT_CHNL_REF_RXNAV_8197F BIT(7)
+#define BIT_CHNL_REF_VBON_8197F BIT(6)
+#define BIT_CHNL_REF_EDCCA_8197F BIT(5)
+#define BIT_RST_CHNL_BUSY_8197F BIT(3)
+#define BIT_RST_CHNL_IDLE_8197F BIT(2)
+#define BIT_CHNL_INFO_RST_8197F BIT(1)
+#define BIT_ATM_AIRTIME_EN_8197F BIT(0)
+
+/* 2 REG_CHNL_IDLE_TIME_8197F */
+
+#define BIT_SHIFT_CHNL_IDLE_TIME_8197F 0
+#define BIT_MASK_CHNL_IDLE_TIME_8197F 0xffffffffL
+#define BIT_CHNL_IDLE_TIME_8197F(x)                                            \
+	(((x) & BIT_MASK_CHNL_IDLE_TIME_8197F)                                 \
+	 << BIT_SHIFT_CHNL_IDLE_TIME_8197F)
+#define BITS_CHNL_IDLE_TIME_8197F                                              \
+	(BIT_MASK_CHNL_IDLE_TIME_8197F << BIT_SHIFT_CHNL_IDLE_TIME_8197F)
+#define BIT_CLEAR_CHNL_IDLE_TIME_8197F(x) ((x) & (~BITS_CHNL_IDLE_TIME_8197F))
+#define BIT_GET_CHNL_IDLE_TIME_8197F(x)                                        \
+	(((x) >> BIT_SHIFT_CHNL_IDLE_TIME_8197F) &                             \
+	 BIT_MASK_CHNL_IDLE_TIME_8197F)
+#define BIT_SET_CHNL_IDLE_TIME_8197F(x, v)                                     \
+	(BIT_CLEAR_CHNL_IDLE_TIME_8197F(x) | BIT_CHNL_IDLE_TIME_8197F(v))
+
+/* 2 REG_CHNL_BUSY_TIME_8197F */
+
+#define BIT_SHIFT_CHNL_BUSY_TIME_8197F 0
+#define BIT_MASK_CHNL_BUSY_TIME_8197F 0xffffffffL
+#define BIT_CHNL_BUSY_TIME_8197F(x)                                            \
+	(((x) & BIT_MASK_CHNL_BUSY_TIME_8197F)                                 \
+	 << BIT_SHIFT_CHNL_BUSY_TIME_8197F)
+#define BITS_CHNL_BUSY_TIME_8197F                                              \
+	(BIT_MASK_CHNL_BUSY_TIME_8197F << BIT_SHIFT_CHNL_BUSY_TIME_8197F)
+#define BIT_CLEAR_CHNL_BUSY_TIME_8197F(x) ((x) & (~BITS_CHNL_BUSY_TIME_8197F))
+#define BIT_GET_CHNL_BUSY_TIME_8197F(x)                                        \
+	(((x) >> BIT_SHIFT_CHNL_BUSY_TIME_8197F) &                             \
+	 BIT_MASK_CHNL_BUSY_TIME_8197F)
+#define BIT_SET_CHNL_BUSY_TIME_8197F(x, v)                                     \
+	(BIT_CLEAR_CHNL_BUSY_TIME_8197F(x) | BIT_CHNL_BUSY_TIME_8197F(v))
+
+/* 2 REG_NOT_VALID_8197F */
+
+/* 2 REG_EDCA_VO_PARAM_8197F */
+
+#define BIT_SHIFT_TXOPLIMIT_8197F 16
+#define BIT_MASK_TXOPLIMIT_8197F 0x7ff
+#define BIT_TXOPLIMIT_8197F(x)                                                 \
+	(((x) & BIT_MASK_TXOPLIMIT_8197F) << BIT_SHIFT_TXOPLIMIT_8197F)
+#define BITS_TXOPLIMIT_8197F                                                   \
+	(BIT_MASK_TXOPLIMIT_8197F << BIT_SHIFT_TXOPLIMIT_8197F)
+#define BIT_CLEAR_TXOPLIMIT_8197F(x) ((x) & (~BITS_TXOPLIMIT_8197F))
+#define BIT_GET_TXOPLIMIT_8197F(x)                                             \
+	(((x) >> BIT_SHIFT_TXOPLIMIT_8197F) & BIT_MASK_TXOPLIMIT_8197F)
+#define BIT_SET_TXOPLIMIT_8197F(x, v)                                          \
+	(BIT_CLEAR_TXOPLIMIT_8197F(x) | BIT_TXOPLIMIT_8197F(v))
+
+#define BIT_SHIFT_CW_8197F 8
+#define BIT_MASK_CW_8197F 0xff
+#define BIT_CW_8197F(x) (((x) & BIT_MASK_CW_8197F) << BIT_SHIFT_CW_8197F)
+#define BITS_CW_8197F (BIT_MASK_CW_8197F << BIT_SHIFT_CW_8197F)
+#define BIT_CLEAR_CW_8197F(x) ((x) & (~BITS_CW_8197F))
+#define BIT_GET_CW_8197F(x) (((x) >> BIT_SHIFT_CW_8197F) & BIT_MASK_CW_8197F)
+#define BIT_SET_CW_8197F(x, v) (BIT_CLEAR_CW_8197F(x) | BIT_CW_8197F(v))
+
+#define BIT_SHIFT_AIFS_8197F 0
+#define BIT_MASK_AIFS_8197F 0xff
+#define BIT_AIFS_8197F(x) (((x) & BIT_MASK_AIFS_8197F) << BIT_SHIFT_AIFS_8197F)
+#define BITS_AIFS_8197F (BIT_MASK_AIFS_8197F << BIT_SHIFT_AIFS_8197F)
+#define BIT_CLEAR_AIFS_8197F(x) ((x) & (~BITS_AIFS_8197F))
+#define BIT_GET_AIFS_8197F(x)                                                  \
+	(((x) >> BIT_SHIFT_AIFS_8197F) & BIT_MASK_AIFS_8197F)
+#define BIT_SET_AIFS_8197F(x, v) (BIT_CLEAR_AIFS_8197F(x) | BIT_AIFS_8197F(v))
+
+/* 2 REG_EDCA_VI_PARAM_8197F */
+
+/* 2 REG_NOT_VALID_8197F */
+
+#define BIT_SHIFT_TXOPLIMIT_8197F 16
+#define BIT_MASK_TXOPLIMIT_8197F 0x7ff
+#define BIT_TXOPLIMIT_8197F(x)                                                 \
+	(((x) & BIT_MASK_TXOPLIMIT_8197F) << BIT_SHIFT_TXOPLIMIT_8197F)
+#define BITS_TXOPLIMIT_8197F                                                   \
+	(BIT_MASK_TXOPLIMIT_8197F << BIT_SHIFT_TXOPLIMIT_8197F)
+#define BIT_CLEAR_TXOPLIMIT_8197F(x) ((x) & (~BITS_TXOPLIMIT_8197F))
+#define BIT_GET_TXOPLIMIT_8197F(x)                                             \
+	(((x) >> BIT_SHIFT_TXOPLIMIT_8197F) & BIT_MASK_TXOPLIMIT_8197F)
+#define BIT_SET_TXOPLIMIT_8197F(x, v)                                          \
+	(BIT_CLEAR_TXOPLIMIT_8197F(x) | BIT_TXOPLIMIT_8197F(v))
+
+#define BIT_SHIFT_CW_8197F 8
+#define BIT_MASK_CW_8197F 0xff
+#define BIT_CW_8197F(x) (((x) & BIT_MASK_CW_8197F) << BIT_SHIFT_CW_8197F)
+#define BITS_CW_8197F (BIT_MASK_CW_8197F << BIT_SHIFT_CW_8197F)
+#define BIT_CLEAR_CW_8197F(x) ((x) & (~BITS_CW_8197F))
+#define BIT_GET_CW_8197F(x) (((x) >> BIT_SHIFT_CW_8197F) & BIT_MASK_CW_8197F)
+#define BIT_SET_CW_8197F(x, v) (BIT_CLEAR_CW_8197F(x) | BIT_CW_8197F(v))
+
+#define BIT_SHIFT_AIFS_8197F 0
+#define BIT_MASK_AIFS_8197F 0xff
+#define BIT_AIFS_8197F(x) (((x) & BIT_MASK_AIFS_8197F) << BIT_SHIFT_AIFS_8197F)
+#define BITS_AIFS_8197F (BIT_MASK_AIFS_8197F << BIT_SHIFT_AIFS_8197F)
+#define BIT_CLEAR_AIFS_8197F(x) ((x) & (~BITS_AIFS_8197F))
+#define BIT_GET_AIFS_8197F(x)                                                  \
+	(((x) >> BIT_SHIFT_AIFS_8197F) & BIT_MASK_AIFS_8197F)
+#define BIT_SET_AIFS_8197F(x, v) (BIT_CLEAR_AIFS_8197F(x) | BIT_AIFS_8197F(v))
+
+/* 2 REG_EDCA_BE_PARAM_8197F */
+
+/* 2 REG_NOT_VALID_8197F */
+
+#define BIT_SHIFT_TXOPLIMIT_8197F 16
+#define BIT_MASK_TXOPLIMIT_8197F 0x7ff
+#define BIT_TXOPLIMIT_8197F(x)                                                 \
+	(((x) & BIT_MASK_TXOPLIMIT_8197F) << BIT_SHIFT_TXOPLIMIT_8197F)
+#define BITS_TXOPLIMIT_8197F                                                   \
+	(BIT_MASK_TXOPLIMIT_8197F << BIT_SHIFT_TXOPLIMIT_8197F)
+#define BIT_CLEAR_TXOPLIMIT_8197F(x) ((x) & (~BITS_TXOPLIMIT_8197F))
+#define BIT_GET_TXOPLIMIT_8197F(x)                                             \
+	(((x) >> BIT_SHIFT_TXOPLIMIT_8197F) & BIT_MASK_TXOPLIMIT_8197F)
+#define BIT_SET_TXOPLIMIT_8197F(x, v)                                          \
+	(BIT_CLEAR_TXOPLIMIT_8197F(x) | BIT_TXOPLIMIT_8197F(v))
+
+#define BIT_SHIFT_CW_8197F 8
+#define BIT_MASK_CW_8197F 0xff
+#define BIT_CW_8197F(x) (((x) & BIT_MASK_CW_8197F) << BIT_SHIFT_CW_8197F)
+#define BITS_CW_8197F (BIT_MASK_CW_8197F << BIT_SHIFT_CW_8197F)
+#define BIT_CLEAR_CW_8197F(x) ((x) & (~BITS_CW_8197F))
+#define BIT_GET_CW_8197F(x) (((x) >> BIT_SHIFT_CW_8197F) & BIT_MASK_CW_8197F)
+#define BIT_SET_CW_8197F(x, v) (BIT_CLEAR_CW_8197F(x) | BIT_CW_8197F(v))
+
+#define BIT_SHIFT_AIFS_8197F 0
+#define BIT_MASK_AIFS_8197F 0xff
+#define BIT_AIFS_8197F(x) (((x) & BIT_MASK_AIFS_8197F) << BIT_SHIFT_AIFS_8197F)
+#define BITS_AIFS_8197F (BIT_MASK_AIFS_8197F << BIT_SHIFT_AIFS_8197F)
+#define BIT_CLEAR_AIFS_8197F(x) ((x) & (~BITS_AIFS_8197F))
+#define BIT_GET_AIFS_8197F(x)                                                  \
+	(((x) >> BIT_SHIFT_AIFS_8197F) & BIT_MASK_AIFS_8197F)
+#define BIT_SET_AIFS_8197F(x, v) (BIT_CLEAR_AIFS_8197F(x) | BIT_AIFS_8197F(v))
+
+/* 2 REG_EDCA_BK_PARAM_8197F */
+
+/* 2 REG_NOT_VALID_8197F */
+
+#define BIT_SHIFT_TXOPLIMIT_8197F 16
+#define BIT_MASK_TXOPLIMIT_8197F 0x7ff
+#define BIT_TXOPLIMIT_8197F(x)                                                 \
+	(((x) & BIT_MASK_TXOPLIMIT_8197F) << BIT_SHIFT_TXOPLIMIT_8197F)
+#define BITS_TXOPLIMIT_8197F                                                   \
+	(BIT_MASK_TXOPLIMIT_8197F << BIT_SHIFT_TXOPLIMIT_8197F)
+#define BIT_CLEAR_TXOPLIMIT_8197F(x) ((x) & (~BITS_TXOPLIMIT_8197F))
+#define BIT_GET_TXOPLIMIT_8197F(x)                                             \
+	(((x) >> BIT_SHIFT_TXOPLIMIT_8197F) & BIT_MASK_TXOPLIMIT_8197F)
+#define BIT_SET_TXOPLIMIT_8197F(x, v)                                          \
+	(BIT_CLEAR_TXOPLIMIT_8197F(x) | BIT_TXOPLIMIT_8197F(v))
+
+#define BIT_SHIFT_CW_8197F 8
+#define BIT_MASK_CW_8197F 0xff
+#define BIT_CW_8197F(x) (((x) & BIT_MASK_CW_8197F) << BIT_SHIFT_CW_8197F)
+#define BITS_CW_8197F (BIT_MASK_CW_8197F << BIT_SHIFT_CW_8197F)
+#define BIT_CLEAR_CW_8197F(x) ((x) & (~BITS_CW_8197F))
+#define BIT_GET_CW_8197F(x) (((x) >> BIT_SHIFT_CW_8197F) & BIT_MASK_CW_8197F)
+#define BIT_SET_CW_8197F(x, v) (BIT_CLEAR_CW_8197F(x) | BIT_CW_8197F(v))
+
+#define BIT_SHIFT_AIFS_8197F 0
+#define BIT_MASK_AIFS_8197F 0xff
+#define BIT_AIFS_8197F(x) (((x) & BIT_MASK_AIFS_8197F) << BIT_SHIFT_AIFS_8197F)
+#define BITS_AIFS_8197F (BIT_MASK_AIFS_8197F << BIT_SHIFT_AIFS_8197F)
+#define BIT_CLEAR_AIFS_8197F(x) ((x) & (~BITS_AIFS_8197F))
+#define BIT_GET_AIFS_8197F(x)                                                  \
+	(((x) >> BIT_SHIFT_AIFS_8197F) & BIT_MASK_AIFS_8197F)
+#define BIT_SET_AIFS_8197F(x, v) (BIT_CLEAR_AIFS_8197F(x) | BIT_AIFS_8197F(v))
+
+/* 2 REG_BCNTCFG_8197F */
+
+#define BIT_SHIFT_BCNCW_MAX_8197F 12
+#define BIT_MASK_BCNCW_MAX_8197F 0xf
+#define BIT_BCNCW_MAX_8197F(x)                                                 \
+	(((x) & BIT_MASK_BCNCW_MAX_8197F) << BIT_SHIFT_BCNCW_MAX_8197F)
+#define BITS_BCNCW_MAX_8197F                                                   \
+	(BIT_MASK_BCNCW_MAX_8197F << BIT_SHIFT_BCNCW_MAX_8197F)
+#define BIT_CLEAR_BCNCW_MAX_8197F(x) ((x) & (~BITS_BCNCW_MAX_8197F))
+#define BIT_GET_BCNCW_MAX_8197F(x)                                             \
+	(((x) >> BIT_SHIFT_BCNCW_MAX_8197F) & BIT_MASK_BCNCW_MAX_8197F)
+#define BIT_SET_BCNCW_MAX_8197F(x, v)                                          \
+	(BIT_CLEAR_BCNCW_MAX_8197F(x) | BIT_BCNCW_MAX_8197F(v))
+
+#define BIT_SHIFT_BCNCW_MIN_8197F 8
+#define BIT_MASK_BCNCW_MIN_8197F 0xf
+#define BIT_BCNCW_MIN_8197F(x)                                                 \
+	(((x) & BIT_MASK_BCNCW_MIN_8197F) << BIT_SHIFT_BCNCW_MIN_8197F)
+#define BITS_BCNCW_MIN_8197F                                                   \
+	(BIT_MASK_BCNCW_MIN_8197F << BIT_SHIFT_BCNCW_MIN_8197F)
+#define BIT_CLEAR_BCNCW_MIN_8197F(x) ((x) & (~BITS_BCNCW_MIN_8197F))
+#define BIT_GET_BCNCW_MIN_8197F(x)                                             \
+	(((x) >> BIT_SHIFT_BCNCW_MIN_8197F) & BIT_MASK_BCNCW_MIN_8197F)
+#define BIT_SET_BCNCW_MIN_8197F(x, v)                                          \
+	(BIT_CLEAR_BCNCW_MIN_8197F(x) | BIT_BCNCW_MIN_8197F(v))
+
+#define BIT_SHIFT_BCNIFS_8197F 0
+#define BIT_MASK_BCNIFS_8197F 0xff
+#define BIT_BCNIFS_8197F(x)                                                    \
+	(((x) & BIT_MASK_BCNIFS_8197F) << BIT_SHIFT_BCNIFS_8197F)
+#define BITS_BCNIFS_8197F (BIT_MASK_BCNIFS_8197F << BIT_SHIFT_BCNIFS_8197F)
+#define BIT_CLEAR_BCNIFS_8197F(x) ((x) & (~BITS_BCNIFS_8197F))
+#define BIT_GET_BCNIFS_8197F(x)                                                \
+	(((x) >> BIT_SHIFT_BCNIFS_8197F) & BIT_MASK_BCNIFS_8197F)
+#define BIT_SET_BCNIFS_8197F(x, v)                                             \
+	(BIT_CLEAR_BCNIFS_8197F(x) | BIT_BCNIFS_8197F(v))
+
+/* 2 REG_PIFS_8197F */
+
+#define BIT_SHIFT_PIFS_8197F 0
+#define BIT_MASK_PIFS_8197F 0xff
+#define BIT_PIFS_8197F(x) (((x) & BIT_MASK_PIFS_8197F) << BIT_SHIFT_PIFS_8197F)
+#define BITS_PIFS_8197F (BIT_MASK_PIFS_8197F << BIT_SHIFT_PIFS_8197F)
+#define BIT_CLEAR_PIFS_8197F(x) ((x) & (~BITS_PIFS_8197F))
+#define BIT_GET_PIFS_8197F(x)                                                  \
+	(((x) >> BIT_SHIFT_PIFS_8197F) & BIT_MASK_PIFS_8197F)
+#define BIT_SET_PIFS_8197F(x, v) (BIT_CLEAR_PIFS_8197F(x) | BIT_PIFS_8197F(v))
+
+/* 2 REG_RDG_PIFS_8197F */
+
+#define BIT_SHIFT_RDG_PIFS_8197F 0
+#define BIT_MASK_RDG_PIFS_8197F 0xff
+#define BIT_RDG_PIFS_8197F(x)                                                  \
+	(((x) & BIT_MASK_RDG_PIFS_8197F) << BIT_SHIFT_RDG_PIFS_8197F)
+#define BITS_RDG_PIFS_8197F                                                    \
+	(BIT_MASK_RDG_PIFS_8197F << BIT_SHIFT_RDG_PIFS_8197F)
+#define BIT_CLEAR_RDG_PIFS_8197F(x) ((x) & (~BITS_RDG_PIFS_8197F))
+#define BIT_GET_RDG_PIFS_8197F(x)                                              \
+	(((x) >> BIT_SHIFT_RDG_PIFS_8197F) & BIT_MASK_RDG_PIFS_8197F)
+#define BIT_SET_RDG_PIFS_8197F(x, v)                                           \
+	(BIT_CLEAR_RDG_PIFS_8197F(x) | BIT_RDG_PIFS_8197F(v))
+
+/* 2 REG_SIFS_8197F */
+
+#define BIT_SHIFT_SIFS_OFDM_TRX_8197F 24
+#define BIT_MASK_SIFS_OFDM_TRX_8197F 0xff
+#define BIT_SIFS_OFDM_TRX_8197F(x)                                             \
+	(((x) & BIT_MASK_SIFS_OFDM_TRX_8197F) << BIT_SHIFT_SIFS_OFDM_TRX_8197F)
+#define BITS_SIFS_OFDM_TRX_8197F                                               \
+	(BIT_MASK_SIFS_OFDM_TRX_8197F << BIT_SHIFT_SIFS_OFDM_TRX_8197F)
+#define BIT_CLEAR_SIFS_OFDM_TRX_8197F(x) ((x) & (~BITS_SIFS_OFDM_TRX_8197F))
+#define BIT_GET_SIFS_OFDM_TRX_8197F(x)                                         \
+	(((x) >> BIT_SHIFT_SIFS_OFDM_TRX_8197F) & BIT_MASK_SIFS_OFDM_TRX_8197F)
+#define BIT_SET_SIFS_OFDM_TRX_8197F(x, v)                                      \
+	(BIT_CLEAR_SIFS_OFDM_TRX_8197F(x) | BIT_SIFS_OFDM_TRX_8197F(v))
+
+#define BIT_SHIFT_SIFS_CCK_TRX_8197F 16
+#define BIT_MASK_SIFS_CCK_TRX_8197F 0xff
+#define BIT_SIFS_CCK_TRX_8197F(x)                                              \
+	(((x) & BIT_MASK_SIFS_CCK_TRX_8197F) << BIT_SHIFT_SIFS_CCK_TRX_8197F)
+#define BITS_SIFS_CCK_TRX_8197F                                                \
+	(BIT_MASK_SIFS_CCK_TRX_8197F << BIT_SHIFT_SIFS_CCK_TRX_8197F)
+#define BIT_CLEAR_SIFS_CCK_TRX_8197F(x) ((x) & (~BITS_SIFS_CCK_TRX_8197F))
+#define BIT_GET_SIFS_CCK_TRX_8197F(x)                                          \
+	(((x) >> BIT_SHIFT_SIFS_CCK_TRX_8197F) & BIT_MASK_SIFS_CCK_TRX_8197F)
+#define BIT_SET_SIFS_CCK_TRX_8197F(x, v)                                       \
+	(BIT_CLEAR_SIFS_CCK_TRX_8197F(x) | BIT_SIFS_CCK_TRX_8197F(v))
+
+#define BIT_SHIFT_SIFS_OFDM_CTX_8197F 8
+#define BIT_MASK_SIFS_OFDM_CTX_8197F 0xff
+#define BIT_SIFS_OFDM_CTX_8197F(x)                                             \
+	(((x) & BIT_MASK_SIFS_OFDM_CTX_8197F) << BIT_SHIFT_SIFS_OFDM_CTX_8197F)
+#define BITS_SIFS_OFDM_CTX_8197F                                               \
+	(BIT_MASK_SIFS_OFDM_CTX_8197F << BIT_SHIFT_SIFS_OFDM_CTX_8197F)
+#define BIT_CLEAR_SIFS_OFDM_CTX_8197F(x) ((x) & (~BITS_SIFS_OFDM_CTX_8197F))
+#define BIT_GET_SIFS_OFDM_CTX_8197F(x)                                         \
+	(((x) >> BIT_SHIFT_SIFS_OFDM_CTX_8197F) & BIT_MASK_SIFS_OFDM_CTX_8197F)
+#define BIT_SET_SIFS_OFDM_CTX_8197F(x, v)                                      \
+	(BIT_CLEAR_SIFS_OFDM_CTX_8197F(x) | BIT_SIFS_OFDM_CTX_8197F(v))
+
+#define BIT_SHIFT_SIFS_CCK_CTX_8197F 0
+#define BIT_MASK_SIFS_CCK_CTX_8197F 0xff
+#define BIT_SIFS_CCK_CTX_8197F(x)                                              \
+	(((x) & BIT_MASK_SIFS_CCK_CTX_8197F) << BIT_SHIFT_SIFS_CCK_CTX_8197F)
+#define BITS_SIFS_CCK_CTX_8197F                                                \
+	(BIT_MASK_SIFS_CCK_CTX_8197F << BIT_SHIFT_SIFS_CCK_CTX_8197F)
+#define BIT_CLEAR_SIFS_CCK_CTX_8197F(x) ((x) & (~BITS_SIFS_CCK_CTX_8197F))
+#define BIT_GET_SIFS_CCK_CTX_8197F(x)                                          \
+	(((x) >> BIT_SHIFT_SIFS_CCK_CTX_8197F) & BIT_MASK_SIFS_CCK_CTX_8197F)
+#define BIT_SET_SIFS_CCK_CTX_8197F(x, v)                                       \
+	(BIT_CLEAR_SIFS_CCK_CTX_8197F(x) | BIT_SIFS_CCK_CTX_8197F(v))
+
+/* 2 REG_TSFTR_SYN_OFFSET_8197F */
+
+#define BIT_SHIFT_TSFTR_SNC_OFFSET_8197F 0
+#define BIT_MASK_TSFTR_SNC_OFFSET_8197F 0xffff
+#define BIT_TSFTR_SNC_OFFSET_8197F(x)                                          \
+	(((x) & BIT_MASK_TSFTR_SNC_OFFSET_8197F)                               \
+	 << BIT_SHIFT_TSFTR_SNC_OFFSET_8197F)
+#define BITS_TSFTR_SNC_OFFSET_8197F                                            \
+	(BIT_MASK_TSFTR_SNC_OFFSET_8197F << BIT_SHIFT_TSFTR_SNC_OFFSET_8197F)
+#define BIT_CLEAR_TSFTR_SNC_OFFSET_8197F(x)                                    \
+	((x) & (~BITS_TSFTR_SNC_OFFSET_8197F))
+#define BIT_GET_TSFTR_SNC_OFFSET_8197F(x)                                      \
+	(((x) >> BIT_SHIFT_TSFTR_SNC_OFFSET_8197F) &                           \
+	 BIT_MASK_TSFTR_SNC_OFFSET_8197F)
+#define BIT_SET_TSFTR_SNC_OFFSET_8197F(x, v)                                   \
+	(BIT_CLEAR_TSFTR_SNC_OFFSET_8197F(x) | BIT_TSFTR_SNC_OFFSET_8197F(v))
+
+/* 2 REG_AGGR_BREAK_TIME_8197F */
+
+#define BIT_SHIFT_AGGR_BK_TIME_8197F 0
+#define BIT_MASK_AGGR_BK_TIME_8197F 0xff
+#define BIT_AGGR_BK_TIME_8197F(x)                                              \
+	(((x) & BIT_MASK_AGGR_BK_TIME_8197F) << BIT_SHIFT_AGGR_BK_TIME_8197F)
+#define BITS_AGGR_BK_TIME_8197F                                                \
+	(BIT_MASK_AGGR_BK_TIME_8197F << BIT_SHIFT_AGGR_BK_TIME_8197F)
+#define BIT_CLEAR_AGGR_BK_TIME_8197F(x) ((x) & (~BITS_AGGR_BK_TIME_8197F))
+#define BIT_GET_AGGR_BK_TIME_8197F(x)                                          \
+	(((x) >> BIT_SHIFT_AGGR_BK_TIME_8197F) & BIT_MASK_AGGR_BK_TIME_8197F)
+#define BIT_SET_AGGR_BK_TIME_8197F(x, v)                                       \
+	(BIT_CLEAR_AGGR_BK_TIME_8197F(x) | BIT_AGGR_BK_TIME_8197F(v))
+
+/* 2 REG_SLOT_8197F */
+
+#define BIT_SHIFT_SLOT_8197F 0
+#define BIT_MASK_SLOT_8197F 0xff
+#define BIT_SLOT_8197F(x) (((x) & BIT_MASK_SLOT_8197F) << BIT_SHIFT_SLOT_8197F)
+#define BITS_SLOT_8197F (BIT_MASK_SLOT_8197F << BIT_SHIFT_SLOT_8197F)
+#define BIT_CLEAR_SLOT_8197F(x) ((x) & (~BITS_SLOT_8197F))
+#define BIT_GET_SLOT_8197F(x)                                                  \
+	(((x) >> BIT_SHIFT_SLOT_8197F) & BIT_MASK_SLOT_8197F)
+#define BIT_SET_SLOT_8197F(x, v) (BIT_CLEAR_SLOT_8197F(x) | BIT_SLOT_8197F(v))
+
+/* 2 REG_TX_PTCL_CTRL_8197F */
+#define BIT_DIS_EDCCA_8197F BIT(15)
+#define BIT_DIS_CCA_8197F BIT(14)
+#define BIT_LSIG_TXOP_TXCMD_NAV_8197F BIT(13)
+#define BIT_SIFS_BK_EN_8197F BIT(12)
+
+#define BIT_SHIFT_TXQ_NAV_MSK_8197F 8
+#define BIT_MASK_TXQ_NAV_MSK_8197F 0xf
+#define BIT_TXQ_NAV_MSK_8197F(x)                                               \
+	(((x) & BIT_MASK_TXQ_NAV_MSK_8197F) << BIT_SHIFT_TXQ_NAV_MSK_8197F)
+#define BITS_TXQ_NAV_MSK_8197F                                                 \
+	(BIT_MASK_TXQ_NAV_MSK_8197F << BIT_SHIFT_TXQ_NAV_MSK_8197F)
+#define BIT_CLEAR_TXQ_NAV_MSK_8197F(x) ((x) & (~BITS_TXQ_NAV_MSK_8197F))
+#define BIT_GET_TXQ_NAV_MSK_8197F(x)                                           \
+	(((x) >> BIT_SHIFT_TXQ_NAV_MSK_8197F) & BIT_MASK_TXQ_NAV_MSK_8197F)
+#define BIT_SET_TXQ_NAV_MSK_8197F(x, v)                                        \
+	(BIT_CLEAR_TXQ_NAV_MSK_8197F(x) | BIT_TXQ_NAV_MSK_8197F(v))
+
+#define BIT_DIS_CW_8197F BIT(7)
+#define BIT_NAV_END_TXOP_8197F BIT(6)
+#define BIT_RDG_END_TXOP_8197F BIT(5)
+#define BIT_AC_INBCN_HOLD_8197F BIT(4)
+#define BIT_MGTQ_TXOP_EN_8197F BIT(3)
+#define BIT_MGTQ_RTSMF_EN_8197F BIT(2)
+#define BIT_HIQ_RTSMF_EN_8197F BIT(1)
+#define BIT_BCN_RTSMF_EN_8197F BIT(0)
+
+/* 2 REG_TXPAUSE_8197F */
+#define BIT_STOP_BCN_HI_MGT_8197F BIT(7)
+#define BIT_MAC_STOPBCNQ_8197F BIT(6)
+#define BIT_MAC_STOPHIQ_8197F BIT(5)
+#define BIT_MAC_STOPMGQ_8197F BIT(4)
+#define BIT_MAC_STOPBK_8197F BIT(3)
+#define BIT_MAC_STOPBE_8197F BIT(2)
+#define BIT_MAC_STOPVI_8197F BIT(1)
+#define BIT_MAC_STOPVO_8197F BIT(0)
+
+/* 2 REG_DIS_TXREQ_CLR_8197F */
+#define BIT_DIS_BT_CCA_8197F BIT(7)
+#define BIT_DIS_TXREQ_CLR_CPUMGQ_8197F BIT(6)
+#define BIT_DIS_TXREQ_CLR_HI_8197F BIT(5)
+#define BIT_DIS_TXREQ_CLR_MGQ_8197F BIT(4)
+#define BIT_DIS_TXREQ_CLR_VO_8197F BIT(3)
+#define BIT_DIS_TXREQ_CLR_VI_8197F BIT(2)
+#define BIT_DIS_TXREQ_CLR_BE_8197F BIT(1)
+#define BIT_DIS_TXREQ_CLR_BK_8197F BIT(0)
+
+/* 2 REG_RD_CTRL_8197F */
+#define BIT_EN_CLR_TXREQ_INCCA_8197F BIT(15)
+#define BIT_DIS_TX_OVER_BCNQ_8197F BIT(14)
+#define BIT_EN_BCNERR_INCCA_8197F BIT(13)
+#define BIT_EN_BCNERR_INEDCCA_8197F BIT(12)
+#define BIT_EDCCA_MSK_CNTDOWN_EN_8197F BIT(11)
+#define BIT_DIS_TXOP_CFE_8197F BIT(10)
+#define BIT_DIS_LSIG_CFE_8197F BIT(9)
+#define BIT_DIS_STBC_CFE_8197F BIT(8)
+#define BIT_BKQ_RD_INIT_EN_8197F BIT(7)
+#define BIT_BEQ_RD_INIT_EN_8197F BIT(6)
+#define BIT_VIQ_RD_INIT_EN_8197F BIT(5)
+#define BIT_VOQ_RD_INIT_EN_8197F BIT(4)
+#define BIT_BKQ_RD_RESP_EN_8197F BIT(3)
+#define BIT_BEQ_RD_RESP_EN_8197F BIT(2)
+#define BIT_VIQ_RD_RESP_EN_8197F BIT(1)
+#define BIT_VOQ_RD_RESP_EN_8197F BIT(0)
+
+/* 2 REG_MBSSID_CTRL_8197F */
+#define BIT_MBID_BCNQ7_EN_8197F BIT(7)
+#define BIT_MBID_BCNQ6_EN_8197F BIT(6)
+#define BIT_MBID_BCNQ5_EN_8197F BIT(5)
+#define BIT_MBID_BCNQ4_EN_8197F BIT(4)
+#define BIT_MBID_BCNQ3_EN_8197F BIT(3)
+#define BIT_MBID_BCNQ2_EN_8197F BIT(2)
+#define BIT_MBID_BCNQ1_EN_8197F BIT(1)
+#define BIT_MBID_BCNQ0_EN_8197F BIT(0)
+
+/* 2 REG_P2PPS_CTRL_8197F */
+#define BIT_P2P_CTW_ALLSTASLEEP_8197F BIT(7)
+#define BIT_P2P_OFF_DISTX_EN_8197F BIT(6)
+#define BIT_PWR_MGT_EN_8197F BIT(5)
+#define BIT_P2P_NOA1_EN_8197F BIT(2)
+#define BIT_P2P_NOA0_EN_8197F BIT(1)
+
+/* 2 REG_PKT_LIFETIME_CTRL_8197F */
+#define BIT_EN_TBTT_AREA_FOR_BB_8197F BIT(23)
+#define BIT_EN_BKF_CLR_TXREQ_8197F BIT(22)
+#define BIT_EN_TSFBIT32_RST_P2P_8197F BIT(21)
+#define BIT_EN_BCN_TX_BTCCA_8197F BIT(20)
+#define BIT_DIS_PKT_TX_ATIM_8197F BIT(19)
+#define BIT_DIS_BCN_DIS_CTN_8197F BIT(18)
+#define BIT_EN_NAVEND_RST_TXOP_8197F BIT(17)
+#define BIT_EN_FILTER_CCA_8197F BIT(16)
+
+#define BIT_SHIFT_CCA_FILTER_THRS_8197F 8
+#define BIT_MASK_CCA_FILTER_THRS_8197F 0xff
+#define BIT_CCA_FILTER_THRS_8197F(x)                                           \
+	(((x) & BIT_MASK_CCA_FILTER_THRS_8197F)                                \
+	 << BIT_SHIFT_CCA_FILTER_THRS_8197F)
+#define BITS_CCA_FILTER_THRS_8197F                                             \
+	(BIT_MASK_CCA_FILTER_THRS_8197F << BIT_SHIFT_CCA_FILTER_THRS_8197F)
+#define BIT_CLEAR_CCA_FILTER_THRS_8197F(x) ((x) & (~BITS_CCA_FILTER_THRS_8197F))
+#define BIT_GET_CCA_FILTER_THRS_8197F(x)                                       \
+	(((x) >> BIT_SHIFT_CCA_FILTER_THRS_8197F) &                            \
+	 BIT_MASK_CCA_FILTER_THRS_8197F)
+#define BIT_SET_CCA_FILTER_THRS_8197F(x, v)                                    \
+	(BIT_CLEAR_CCA_FILTER_THRS_8197F(x) | BIT_CCA_FILTER_THRS_8197F(v))
+
+#define BIT_SHIFT_EDCCA_THRS_8197F 0
+#define BIT_MASK_EDCCA_THRS_8197F 0xff
+#define BIT_EDCCA_THRS_8197F(x)                                                \
+	(((x) & BIT_MASK_EDCCA_THRS_8197F) << BIT_SHIFT_EDCCA_THRS_8197F)
+#define BITS_EDCCA_THRS_8197F                                                  \
+	(BIT_MASK_EDCCA_THRS_8197F << BIT_SHIFT_EDCCA_THRS_8197F)
+#define BIT_CLEAR_EDCCA_THRS_8197F(x) ((x) & (~BITS_EDCCA_THRS_8197F))
+#define BIT_GET_EDCCA_THRS_8197F(x)                                            \
+	(((x) >> BIT_SHIFT_EDCCA_THRS_8197F) & BIT_MASK_EDCCA_THRS_8197F)
+#define BIT_SET_EDCCA_THRS_8197F(x, v)                                         \
+	(BIT_CLEAR_EDCCA_THRS_8197F(x) | BIT_EDCCA_THRS_8197F(v))
+
+/* 2 REG_P2PPS_SPEC_STATE_8197F */
+#define BIT_SPEC_POWER_STATE_8197F BIT(7)
+#define BIT_SPEC_CTWINDOW_ON_8197F BIT(6)
+#define BIT_SPEC_BEACON_AREA_ON_8197F BIT(5)
+#define BIT_SPEC_CTWIN_EARLY_DISTX_8197F BIT(4)
+#define BIT_SPEC_NOA1_OFF_PERIOD_8197F BIT(3)
+#define BIT_SPEC_FORCE_DOZE1_8197F BIT(2)
+#define BIT_SPEC_NOA0_OFF_PERIOD_8197F BIT(1)
+#define BIT_SPEC_FORCE_DOZE0_8197F BIT(0)
+
+/* 2 REG_NOT_VALID_8197F */
+
+#define BIT_SHIFT_P2PON_DIS_TXTIME_8197F 0
+#define BIT_MASK_P2PON_DIS_TXTIME_8197F 0xff
+#define BIT_P2PON_DIS_TXTIME_8197F(x)                                          \
+	(((x) & BIT_MASK_P2PON_DIS_TXTIME_8197F)                               \
+	 << BIT_SHIFT_P2PON_DIS_TXTIME_8197F)
+#define BITS_P2PON_DIS_TXTIME_8197F                                            \
+	(BIT_MASK_P2PON_DIS_TXTIME_8197F << BIT_SHIFT_P2PON_DIS_TXTIME_8197F)
+#define BIT_CLEAR_P2PON_DIS_TXTIME_8197F(x)                                    \
+	((x) & (~BITS_P2PON_DIS_TXTIME_8197F))
+#define BIT_GET_P2PON_DIS_TXTIME_8197F(x)                                      \
+	(((x) >> BIT_SHIFT_P2PON_DIS_TXTIME_8197F) &                           \
+	 BIT_MASK_P2PON_DIS_TXTIME_8197F)
+#define BIT_SET_P2PON_DIS_TXTIME_8197F(x, v)                                   \
+	(BIT_CLEAR_P2PON_DIS_TXTIME_8197F(x) | BIT_P2PON_DIS_TXTIME_8197F(v))
+
+/* 2 REG_QUEUE_INCOL_THR_8197F */
+
+#define BIT_SHIFT_BK_QUEUE_THR_8197F 24
+#define BIT_MASK_BK_QUEUE_THR_8197F 0xff
+#define BIT_BK_QUEUE_THR_8197F(x)                                              \
+	(((x) & BIT_MASK_BK_QUEUE_THR_8197F) << BIT_SHIFT_BK_QUEUE_THR_8197F)
+#define BITS_BK_QUEUE_THR_8197F                                                \
+	(BIT_MASK_BK_QUEUE_THR_8197F << BIT_SHIFT_BK_QUEUE_THR_8197F)
+#define BIT_CLEAR_BK_QUEUE_THR_8197F(x) ((x) & (~BITS_BK_QUEUE_THR_8197F))
+#define BIT_GET_BK_QUEUE_THR_8197F(x)                                          \
+	(((x) >> BIT_SHIFT_BK_QUEUE_THR_8197F) & BIT_MASK_BK_QUEUE_THR_8197F)
+#define BIT_SET_BK_QUEUE_THR_8197F(x, v)                                       \
+	(BIT_CLEAR_BK_QUEUE_THR_8197F(x) | BIT_BK_QUEUE_THR_8197F(v))
+
+#define BIT_SHIFT_BE_QUEUE_THR_8197F 16
+#define BIT_MASK_BE_QUEUE_THR_8197F 0xff
+#define BIT_BE_QUEUE_THR_8197F(x)                                              \
+	(((x) & BIT_MASK_BE_QUEUE_THR_8197F) << BIT_SHIFT_BE_QUEUE_THR_8197F)
+#define BITS_BE_QUEUE_THR_8197F                                                \
+	(BIT_MASK_BE_QUEUE_THR_8197F << BIT_SHIFT_BE_QUEUE_THR_8197F)
+#define BIT_CLEAR_BE_QUEUE_THR_8197F(x) ((x) & (~BITS_BE_QUEUE_THR_8197F))
+#define BIT_GET_BE_QUEUE_THR_8197F(x)                                          \
+	(((x) >> BIT_SHIFT_BE_QUEUE_THR_8197F) & BIT_MASK_BE_QUEUE_THR_8197F)
+#define BIT_SET_BE_QUEUE_THR_8197F(x, v)                                       \
+	(BIT_CLEAR_BE_QUEUE_THR_8197F(x) | BIT_BE_QUEUE_THR_8197F(v))
+
+#define BIT_SHIFT_VI_QUEUE_THR_8197F 8
+#define BIT_MASK_VI_QUEUE_THR_8197F 0xff
+#define BIT_VI_QUEUE_THR_8197F(x)                                              \
+	(((x) & BIT_MASK_VI_QUEUE_THR_8197F) << BIT_SHIFT_VI_QUEUE_THR_8197F)
+#define BITS_VI_QUEUE_THR_8197F                                                \
+	(BIT_MASK_VI_QUEUE_THR_8197F << BIT_SHIFT_VI_QUEUE_THR_8197F)
+#define BIT_CLEAR_VI_QUEUE_THR_8197F(x) ((x) & (~BITS_VI_QUEUE_THR_8197F))
+#define BIT_GET_VI_QUEUE_THR_8197F(x)                                          \
+	(((x) >> BIT_SHIFT_VI_QUEUE_THR_8197F) & BIT_MASK_VI_QUEUE_THR_8197F)
+#define BIT_SET_VI_QUEUE_THR_8197F(x, v)                                       \
+	(BIT_CLEAR_VI_QUEUE_THR_8197F(x) | BIT_VI_QUEUE_THR_8197F(v))
+
+#define BIT_SHIFT_VO_QUEUE_THR_8197F 0
+#define BIT_MASK_VO_QUEUE_THR_8197F 0xff
+#define BIT_VO_QUEUE_THR_8197F(x)                                              \
+	(((x) & BIT_MASK_VO_QUEUE_THR_8197F) << BIT_SHIFT_VO_QUEUE_THR_8197F)
+#define BITS_VO_QUEUE_THR_8197F                                                \
+	(BIT_MASK_VO_QUEUE_THR_8197F << BIT_SHIFT_VO_QUEUE_THR_8197F)
+#define BIT_CLEAR_VO_QUEUE_THR_8197F(x) ((x) & (~BITS_VO_QUEUE_THR_8197F))
+#define BIT_GET_VO_QUEUE_THR_8197F(x)                                          \
+	(((x) >> BIT_SHIFT_VO_QUEUE_THR_8197F) & BIT_MASK_VO_QUEUE_THR_8197F)
+#define BIT_SET_VO_QUEUE_THR_8197F(x, v)                                       \
+	(BIT_CLEAR_VO_QUEUE_THR_8197F(x) | BIT_VO_QUEUE_THR_8197F(v))
+
+/* 2 REG_QUEUE_INCOL_EN_8197F */
+#define BIT_QUEUE_INCOL_EN_8197F BIT(16)
+
+#define BIT_SHIFT_BK_TRIGGER_NUM_V1_8197F 12
+#define BIT_MASK_BK_TRIGGER_NUM_V1_8197F 0xf
+#define BIT_BK_TRIGGER_NUM_V1_8197F(x)                                         \
+	(((x) & BIT_MASK_BK_TRIGGER_NUM_V1_8197F)                              \
+	 << BIT_SHIFT_BK_TRIGGER_NUM_V1_8197F)
+#define BITS_BK_TRIGGER_NUM_V1_8197F                                           \
+	(BIT_MASK_BK_TRIGGER_NUM_V1_8197F << BIT_SHIFT_BK_TRIGGER_NUM_V1_8197F)
+#define BIT_CLEAR_BK_TRIGGER_NUM_V1_8197F(x)                                   \
+	((x) & (~BITS_BK_TRIGGER_NUM_V1_8197F))
+#define BIT_GET_BK_TRIGGER_NUM_V1_8197F(x)                                     \
+	(((x) >> BIT_SHIFT_BK_TRIGGER_NUM_V1_8197F) &                          \
+	 BIT_MASK_BK_TRIGGER_NUM_V1_8197F)
+#define BIT_SET_BK_TRIGGER_NUM_V1_8197F(x, v)                                  \
+	(BIT_CLEAR_BK_TRIGGER_NUM_V1_8197F(x) | BIT_BK_TRIGGER_NUM_V1_8197F(v))
+
+#define BIT_SHIFT_BE_TRIGGER_NUM_V1_8197F 8
+#define BIT_MASK_BE_TRIGGER_NUM_V1_8197F 0xf
+#define BIT_BE_TRIGGER_NUM_V1_8197F(x)                                         \
+	(((x) & BIT_MASK_BE_TRIGGER_NUM_V1_8197F)                              \
+	 << BIT_SHIFT_BE_TRIGGER_NUM_V1_8197F)
+#define BITS_BE_TRIGGER_NUM_V1_8197F                                           \
+	(BIT_MASK_BE_TRIGGER_NUM_V1_8197F << BIT_SHIFT_BE_TRIGGER_NUM_V1_8197F)
+#define BIT_CLEAR_BE_TRIGGER_NUM_V1_8197F(x)                                   \
+	((x) & (~BITS_BE_TRIGGER_NUM_V1_8197F))
+#define BIT_GET_BE_TRIGGER_NUM_V1_8197F(x)                                     \
+	(((x) >> BIT_SHIFT_BE_TRIGGER_NUM_V1_8197F) &                          \
+	 BIT_MASK_BE_TRIGGER_NUM_V1_8197F)
+#define BIT_SET_BE_TRIGGER_NUM_V1_8197F(x, v)                                  \
+	(BIT_CLEAR_BE_TRIGGER_NUM_V1_8197F(x) | BIT_BE_TRIGGER_NUM_V1_8197F(v))
+
+#define BIT_SHIFT_VI_TRIGGER_NUM_8197F 4
+#define BIT_MASK_VI_TRIGGER_NUM_8197F 0xf
+#define BIT_VI_TRIGGER_NUM_8197F(x)                                            \
+	(((x) & BIT_MASK_VI_TRIGGER_NUM_8197F)                                 \
+	 << BIT_SHIFT_VI_TRIGGER_NUM_8197F)
+#define BITS_VI_TRIGGER_NUM_8197F                                              \
+	(BIT_MASK_VI_TRIGGER_NUM_8197F << BIT_SHIFT_VI_TRIGGER_NUM_8197F)
+#define BIT_CLEAR_VI_TRIGGER_NUM_8197F(x) ((x) & (~BITS_VI_TRIGGER_NUM_8197F))
+#define BIT_GET_VI_TRIGGER_NUM_8197F(x)                                        \
+	(((x) >> BIT_SHIFT_VI_TRIGGER_NUM_8197F) &                             \
+	 BIT_MASK_VI_TRIGGER_NUM_8197F)
+#define BIT_SET_VI_TRIGGER_NUM_8197F(x, v)                                     \
+	(BIT_CLEAR_VI_TRIGGER_NUM_8197F(x) | BIT_VI_TRIGGER_NUM_8197F(v))
+
+#define BIT_SHIFT_VO_TRIGGER_NUM_8197F 0
+#define BIT_MASK_VO_TRIGGER_NUM_8197F 0xf
+#define BIT_VO_TRIGGER_NUM_8197F(x)                                            \
+	(((x) & BIT_MASK_VO_TRIGGER_NUM_8197F)                                 \
+	 << BIT_SHIFT_VO_TRIGGER_NUM_8197F)
+#define BITS_VO_TRIGGER_NUM_8197F                                              \
+	(BIT_MASK_VO_TRIGGER_NUM_8197F << BIT_SHIFT_VO_TRIGGER_NUM_8197F)
+#define BIT_CLEAR_VO_TRIGGER_NUM_8197F(x) ((x) & (~BITS_VO_TRIGGER_NUM_8197F))
+#define BIT_GET_VO_TRIGGER_NUM_8197F(x)                                        \
+	(((x) >> BIT_SHIFT_VO_TRIGGER_NUM_8197F) &                             \
+	 BIT_MASK_VO_TRIGGER_NUM_8197F)
+#define BIT_SET_VO_TRIGGER_NUM_8197F(x, v)                                     \
+	(BIT_CLEAR_VO_TRIGGER_NUM_8197F(x) | BIT_VO_TRIGGER_NUM_8197F(v))
+
+/* 2 REG_TBTT_PROHIBIT_8197F */
+
+#define BIT_SHIFT_TBTT_HOLD_TIME_AP_8197F 8
+#define BIT_MASK_TBTT_HOLD_TIME_AP_8197F 0xfff
+#define BIT_TBTT_HOLD_TIME_AP_8197F(x)                                         \
+	(((x) & BIT_MASK_TBTT_HOLD_TIME_AP_8197F)                              \
+	 << BIT_SHIFT_TBTT_HOLD_TIME_AP_8197F)
+#define BITS_TBTT_HOLD_TIME_AP_8197F                                           \
+	(BIT_MASK_TBTT_HOLD_TIME_AP_8197F << BIT_SHIFT_TBTT_HOLD_TIME_AP_8197F)
+#define BIT_CLEAR_TBTT_HOLD_TIME_AP_8197F(x)                                   \
+	((x) & (~BITS_TBTT_HOLD_TIME_AP_8197F))
+#define BIT_GET_TBTT_HOLD_TIME_AP_8197F(x)                                     \
+	(((x) >> BIT_SHIFT_TBTT_HOLD_TIME_AP_8197F) &                          \
+	 BIT_MASK_TBTT_HOLD_TIME_AP_8197F)
+#define BIT_SET_TBTT_HOLD_TIME_AP_8197F(x, v)                                  \
+	(BIT_CLEAR_TBTT_HOLD_TIME_AP_8197F(x) | BIT_TBTT_HOLD_TIME_AP_8197F(v))
+
+#define BIT_SHIFT_TBTT_PROHIBIT_SETUP_8197F 0
+#define BIT_MASK_TBTT_PROHIBIT_SETUP_8197F 0xf
+#define BIT_TBTT_PROHIBIT_SETUP_8197F(x)                                       \
+	(((x) & BIT_MASK_TBTT_PROHIBIT_SETUP_8197F)                            \
+	 << BIT_SHIFT_TBTT_PROHIBIT_SETUP_8197F)
+#define BITS_TBTT_PROHIBIT_SETUP_8197F                                         \
+	(BIT_MASK_TBTT_PROHIBIT_SETUP_8197F                                    \
+	 << BIT_SHIFT_TBTT_PROHIBIT_SETUP_8197F)
+#define BIT_CLEAR_TBTT_PROHIBIT_SETUP_8197F(x)                                 \
+	((x) & (~BITS_TBTT_PROHIBIT_SETUP_8197F))
+#define BIT_GET_TBTT_PROHIBIT_SETUP_8197F(x)                                   \
+	(((x) >> BIT_SHIFT_TBTT_PROHIBIT_SETUP_8197F) &                        \
+	 BIT_MASK_TBTT_PROHIBIT_SETUP_8197F)
+#define BIT_SET_TBTT_PROHIBIT_SETUP_8197F(x, v)                                \
+	(BIT_CLEAR_TBTT_PROHIBIT_SETUP_8197F(x) |                              \
+	 BIT_TBTT_PROHIBIT_SETUP_8197F(v))
+
+/* 2 REG_P2PPS_STATE_8197F */
+#define BIT_POWER_STATE_8197F BIT(7)
+#define BIT_CTWINDOW_ON_8197F BIT(6)
+#define BIT_BEACON_AREA_ON_8197F BIT(5)
+#define BIT_CTWIN_EARLY_DISTX_8197F BIT(4)
+#define BIT_NOA1_OFF_PERIOD_8197F BIT(3)
+#define BIT_FORCE_DOZE1_8197F BIT(2)
+#define BIT_NOA0_OFF_PERIOD_8197F BIT(1)
+#define BIT_FORCE_DOZE0_8197F BIT(0)
+
+/* 2 REG_RD_NAV_NXT_8197F */
+
+#define BIT_SHIFT_RD_NAV_PROT_NXT_8197F 0
+#define BIT_MASK_RD_NAV_PROT_NXT_8197F 0xffff
+#define BIT_RD_NAV_PROT_NXT_8197F(x)                                           \
+	(((x) & BIT_MASK_RD_NAV_PROT_NXT_8197F)                                \
+	 << BIT_SHIFT_RD_NAV_PROT_NXT_8197F)
+#define BITS_RD_NAV_PROT_NXT_8197F                                             \
+	(BIT_MASK_RD_NAV_PROT_NXT_8197F << BIT_SHIFT_RD_NAV_PROT_NXT_8197F)
+#define BIT_CLEAR_RD_NAV_PROT_NXT_8197F(x) ((x) & (~BITS_RD_NAV_PROT_NXT_8197F))
+#define BIT_GET_RD_NAV_PROT_NXT_8197F(x)                                       \
+	(((x) >> BIT_SHIFT_RD_NAV_PROT_NXT_8197F) &                            \
+	 BIT_MASK_RD_NAV_PROT_NXT_8197F)
+#define BIT_SET_RD_NAV_PROT_NXT_8197F(x, v)                                    \
+	(BIT_CLEAR_RD_NAV_PROT_NXT_8197F(x) | BIT_RD_NAV_PROT_NXT_8197F(v))
+
+/* 2 REG_NAV_PROT_LEN_8197F */
+
+#define BIT_SHIFT_NAV_PROT_LEN_8197F 0
+#define BIT_MASK_NAV_PROT_LEN_8197F 0xffff
+#define BIT_NAV_PROT_LEN_8197F(x)                                              \
+	(((x) & BIT_MASK_NAV_PROT_LEN_8197F) << BIT_SHIFT_NAV_PROT_LEN_8197F)
+#define BITS_NAV_PROT_LEN_8197F                                                \
+	(BIT_MASK_NAV_PROT_LEN_8197F << BIT_SHIFT_NAV_PROT_LEN_8197F)
+#define BIT_CLEAR_NAV_PROT_LEN_8197F(x) ((x) & (~BITS_NAV_PROT_LEN_8197F))
+#define BIT_GET_NAV_PROT_LEN_8197F(x)                                          \
+	(((x) >> BIT_SHIFT_NAV_PROT_LEN_8197F) & BIT_MASK_NAV_PROT_LEN_8197F)
+#define BIT_SET_NAV_PROT_LEN_8197F(x, v)                                       \
+	(BIT_CLEAR_NAV_PROT_LEN_8197F(x) | BIT_NAV_PROT_LEN_8197F(v))
+
+/* 2 REG_FTM_CTRL_8197F */
+
+#define BIT_SHIFT_FTM_TSF_R2T_PORT_8197F 22
+#define BIT_MASK_FTM_TSF_R2T_PORT_8197F 0x7
+#define BIT_FTM_TSF_R2T_PORT_8197F(x)                                          \
+	(((x) & BIT_MASK_FTM_TSF_R2T_PORT_8197F)                               \
+	 << BIT_SHIFT_FTM_TSF_R2T_PORT_8197F)
+#define BITS_FTM_TSF_R2T_PORT_8197F                                            \
+	(BIT_MASK_FTM_TSF_R2T_PORT_8197F << BIT_SHIFT_FTM_TSF_R2T_PORT_8197F)
+#define BIT_CLEAR_FTM_TSF_R2T_PORT_8197F(x)                                    \
+	((x) & (~BITS_FTM_TSF_R2T_PORT_8197F))
+#define BIT_GET_FTM_TSF_R2T_PORT_8197F(x)                                      \
+	(((x) >> BIT_SHIFT_FTM_TSF_R2T_PORT_8197F) &                           \
+	 BIT_MASK_FTM_TSF_R2T_PORT_8197F)
+#define BIT_SET_FTM_TSF_R2T_PORT_8197F(x, v)                                   \
+	(BIT_CLEAR_FTM_TSF_R2T_PORT_8197F(x) | BIT_FTM_TSF_R2T_PORT_8197F(v))
+
+#define BIT_SHIFT_FTM_TSF_T2R_PORT_8197F 19
+#define BIT_MASK_FTM_TSF_T2R_PORT_8197F 0x7
+#define BIT_FTM_TSF_T2R_PORT_8197F(x)                                          \
+	(((x) & BIT_MASK_FTM_TSF_T2R_PORT_8197F)                               \
+	 << BIT_SHIFT_FTM_TSF_T2R_PORT_8197F)
+#define BITS_FTM_TSF_T2R_PORT_8197F                                            \
+	(BIT_MASK_FTM_TSF_T2R_PORT_8197F << BIT_SHIFT_FTM_TSF_T2R_PORT_8197F)
+#define BIT_CLEAR_FTM_TSF_T2R_PORT_8197F(x)                                    \
+	((x) & (~BITS_FTM_TSF_T2R_PORT_8197F))
+#define BIT_GET_FTM_TSF_T2R_PORT_8197F(x)                                      \
+	(((x) >> BIT_SHIFT_FTM_TSF_T2R_PORT_8197F) &                           \
+	 BIT_MASK_FTM_TSF_T2R_PORT_8197F)
+#define BIT_SET_FTM_TSF_T2R_PORT_8197F(x, v)                                   \
+	(BIT_CLEAR_FTM_TSF_T2R_PORT_8197F(x) | BIT_FTM_TSF_T2R_PORT_8197F(v))
+
+#define BIT_SHIFT_FTM_PTT_PORT_8197F 16
+#define BIT_MASK_FTM_PTT_PORT_8197F 0x7
+#define BIT_FTM_PTT_PORT_8197F(x)                                              \
+	(((x) & BIT_MASK_FTM_PTT_PORT_8197F) << BIT_SHIFT_FTM_PTT_PORT_8197F)
+#define BITS_FTM_PTT_PORT_8197F                                                \
+	(BIT_MASK_FTM_PTT_PORT_8197F << BIT_SHIFT_FTM_PTT_PORT_8197F)
+#define BIT_CLEAR_FTM_PTT_PORT_8197F(x) ((x) & (~BITS_FTM_PTT_PORT_8197F))
+#define BIT_GET_FTM_PTT_PORT_8197F(x)                                          \
+	(((x) >> BIT_SHIFT_FTM_PTT_PORT_8197F) & BIT_MASK_FTM_PTT_PORT_8197F)
+#define BIT_SET_FTM_PTT_PORT_8197F(x, v)                                       \
+	(BIT_CLEAR_FTM_PTT_PORT_8197F(x) | BIT_FTM_PTT_PORT_8197F(v))
+
+#define BIT_SHIFT_FTM_PTT_8197F 0
+#define BIT_MASK_FTM_PTT_8197F 0xffff
+#define BIT_FTM_PTT_8197F(x)                                                   \
+	(((x) & BIT_MASK_FTM_PTT_8197F) << BIT_SHIFT_FTM_PTT_8197F)
+#define BITS_FTM_PTT_8197F (BIT_MASK_FTM_PTT_8197F << BIT_SHIFT_FTM_PTT_8197F)
+#define BIT_CLEAR_FTM_PTT_8197F(x) ((x) & (~BITS_FTM_PTT_8197F))
+#define BIT_GET_FTM_PTT_8197F(x)                                               \
+	(((x) >> BIT_SHIFT_FTM_PTT_8197F) & BIT_MASK_FTM_PTT_8197F)
+#define BIT_SET_FTM_PTT_8197F(x, v)                                            \
+	(BIT_CLEAR_FTM_PTT_8197F(x) | BIT_FTM_PTT_8197F(v))
+
+/* 2 REG_FTM_TSF_CNT_8197F */
+
+#define BIT_SHIFT_FTM_TSF_R2T_8197F 16
+#define BIT_MASK_FTM_TSF_R2T_8197F 0xffff
+#define BIT_FTM_TSF_R2T_8197F(x)                                               \
+	(((x) & BIT_MASK_FTM_TSF_R2T_8197F) << BIT_SHIFT_FTM_TSF_R2T_8197F)
+#define BITS_FTM_TSF_R2T_8197F                                                 \
+	(BIT_MASK_FTM_TSF_R2T_8197F << BIT_SHIFT_FTM_TSF_R2T_8197F)
+#define BIT_CLEAR_FTM_TSF_R2T_8197F(x) ((x) & (~BITS_FTM_TSF_R2T_8197F))
+#define BIT_GET_FTM_TSF_R2T_8197F(x)                                           \
+	(((x) >> BIT_SHIFT_FTM_TSF_R2T_8197F) & BIT_MASK_FTM_TSF_R2T_8197F)
+#define BIT_SET_FTM_TSF_R2T_8197F(x, v)                                        \
+	(BIT_CLEAR_FTM_TSF_R2T_8197F(x) | BIT_FTM_TSF_R2T_8197F(v))
+
+#define BIT_SHIFT_FTM_TSF_T2R_8197F 0
+#define BIT_MASK_FTM_TSF_T2R_8197F 0xffff
+#define BIT_FTM_TSF_T2R_8197F(x)                                               \
+	(((x) & BIT_MASK_FTM_TSF_T2R_8197F) << BIT_SHIFT_FTM_TSF_T2R_8197F)
+#define BITS_FTM_TSF_T2R_8197F                                                 \
+	(BIT_MASK_FTM_TSF_T2R_8197F << BIT_SHIFT_FTM_TSF_T2R_8197F)
+#define BIT_CLEAR_FTM_TSF_T2R_8197F(x) ((x) & (~BITS_FTM_TSF_T2R_8197F))
+#define BIT_GET_FTM_TSF_T2R_8197F(x)                                           \
+	(((x) >> BIT_SHIFT_FTM_TSF_T2R_8197F) & BIT_MASK_FTM_TSF_T2R_8197F)
+#define BIT_SET_FTM_TSF_T2R_8197F(x, v)                                        \
+	(BIT_CLEAR_FTM_TSF_T2R_8197F(x) | BIT_FTM_TSF_T2R_8197F(v))
+
+/* 2 REG_BCN_CTRL_8197F */
+#define BIT_DIS_RX_BSSID_FIT_8197F BIT(6)
+#define BIT_P0_EN_TXBCN_RPT_8197F BIT(5)
+#define BIT_DIS_TSF_UDT_8197F BIT(4)
+#define BIT_EN_BCN_FUNCTION_8197F BIT(3)
+#define BIT_P0_EN_RXBCN_RPT_8197F BIT(2)
+#define BIT_EN_P2P_CTWINDOW_8197F BIT(1)
+#define BIT_EN_P2P_BCNQ_AREA_8197F BIT(0)
+
+/* 2 REG_BCN_CTRL_CLINT0_8197F */
+#define BIT_CLI0_DIS_RX_BSSID_FIT_8197F BIT(6)
+#define BIT_CLI0_DIS_TSF_UDT_8197F BIT(4)
+#define BIT_CLI0_EN_BCN_FUNCTION_8197F BIT(3)
+#define BIT_CLI0_EN_RXBCN_RPT_8197F BIT(2)
+#define BIT_CLI0_ENP2P_CTWINDOW_8197F BIT(1)
+#define BIT_CLI0_ENP2P_BCNQ_AREA_8197F BIT(0)
+
+/* 2 REG_MBID_NUM_8197F */
+#define BIT_EN_PRE_DL_BEACON_8197F BIT(3)
+
+#define BIT_SHIFT_MBID_BCN_NUM_8197F 0
+#define BIT_MASK_MBID_BCN_NUM_8197F 0x7
+#define BIT_MBID_BCN_NUM_8197F(x)                                              \
+	(((x) & BIT_MASK_MBID_BCN_NUM_8197F) << BIT_SHIFT_MBID_BCN_NUM_8197F)
+#define BITS_MBID_BCN_NUM_8197F                                                \
+	(BIT_MASK_MBID_BCN_NUM_8197F << BIT_SHIFT_MBID_BCN_NUM_8197F)
+#define BIT_CLEAR_MBID_BCN_NUM_8197F(x) ((x) & (~BITS_MBID_BCN_NUM_8197F))
+#define BIT_GET_MBID_BCN_NUM_8197F(x)                                          \
+	(((x) >> BIT_SHIFT_MBID_BCN_NUM_8197F) & BIT_MASK_MBID_BCN_NUM_8197F)
+#define BIT_SET_MBID_BCN_NUM_8197F(x, v)                                       \
+	(BIT_CLEAR_MBID_BCN_NUM_8197F(x) | BIT_MBID_BCN_NUM_8197F(v))
+
+/* 2 REG_DUAL_TSF_RST_8197F */
+#define BIT_FREECNT_RST_8197F BIT(5)
+#define BIT_TSFTR_CLI3_RST_8197F BIT(4)
+#define BIT_TSFTR_CLI2_RST_8197F BIT(3)
+#define BIT_TSFTR_CLI1_RST_8197F BIT(2)
+#define BIT_TSFTR_CLI0_RST_8197F BIT(1)
+#define BIT_TSFTR_RST_8197F BIT(0)
+
+/* 2 REG_MBSSID_BCN_SPACE_8197F */
+
+#define BIT_SHIFT_BCN_TIMER_SEL_FWRD_8197F 28
+#define BIT_MASK_BCN_TIMER_SEL_FWRD_8197F 0x7
+#define BIT_BCN_TIMER_SEL_FWRD_8197F(x)                                        \
+	(((x) & BIT_MASK_BCN_TIMER_SEL_FWRD_8197F)                             \
+	 << BIT_SHIFT_BCN_TIMER_SEL_FWRD_8197F)
+#define BITS_BCN_TIMER_SEL_FWRD_8197F                                          \
+	(BIT_MASK_BCN_TIMER_SEL_FWRD_8197F                                     \
+	 << BIT_SHIFT_BCN_TIMER_SEL_FWRD_8197F)
+#define BIT_CLEAR_BCN_TIMER_SEL_FWRD_8197F(x)                                  \
+	((x) & (~BITS_BCN_TIMER_SEL_FWRD_8197F))
+#define BIT_GET_BCN_TIMER_SEL_FWRD_8197F(x)                                    \
+	(((x) >> BIT_SHIFT_BCN_TIMER_SEL_FWRD_8197F) &                         \
+	 BIT_MASK_BCN_TIMER_SEL_FWRD_8197F)
+#define BIT_SET_BCN_TIMER_SEL_FWRD_8197F(x, v)                                 \
+	(BIT_CLEAR_BCN_TIMER_SEL_FWRD_8197F(x) |                               \
+	 BIT_BCN_TIMER_SEL_FWRD_8197F(v))
+
+#define BIT_SHIFT_BCN_SPACE_CLINT0_8197F 16
+#define BIT_MASK_BCN_SPACE_CLINT0_8197F 0xfff
+#define BIT_BCN_SPACE_CLINT0_8197F(x)                                          \
+	(((x) & BIT_MASK_BCN_SPACE_CLINT0_8197F)                               \
+	 << BIT_SHIFT_BCN_SPACE_CLINT0_8197F)
+#define BITS_BCN_SPACE_CLINT0_8197F                                            \
+	(BIT_MASK_BCN_SPACE_CLINT0_8197F << BIT_SHIFT_BCN_SPACE_CLINT0_8197F)
+#define BIT_CLEAR_BCN_SPACE_CLINT0_8197F(x)                                    \
+	((x) & (~BITS_BCN_SPACE_CLINT0_8197F))
+#define BIT_GET_BCN_SPACE_CLINT0_8197F(x)                                      \
+	(((x) >> BIT_SHIFT_BCN_SPACE_CLINT0_8197F) &                           \
+	 BIT_MASK_BCN_SPACE_CLINT0_8197F)
+#define BIT_SET_BCN_SPACE_CLINT0_8197F(x, v)                                   \
+	(BIT_CLEAR_BCN_SPACE_CLINT0_8197F(x) | BIT_BCN_SPACE_CLINT0_8197F(v))
+
+#define BIT_SHIFT_BCN_SPACE0_8197F 0
+#define BIT_MASK_BCN_SPACE0_8197F 0xffff
+#define BIT_BCN_SPACE0_8197F(x)                                                \
+	(((x) & BIT_MASK_BCN_SPACE0_8197F) << BIT_SHIFT_BCN_SPACE0_8197F)
+#define BITS_BCN_SPACE0_8197F                                                  \
+	(BIT_MASK_BCN_SPACE0_8197F << BIT_SHIFT_BCN_SPACE0_8197F)
+#define BIT_CLEAR_BCN_SPACE0_8197F(x) ((x) & (~BITS_BCN_SPACE0_8197F))
+#define BIT_GET_BCN_SPACE0_8197F(x)                                            \
+	(((x) >> BIT_SHIFT_BCN_SPACE0_8197F) & BIT_MASK_BCN_SPACE0_8197F)
+#define BIT_SET_BCN_SPACE0_8197F(x, v)                                         \
+	(BIT_CLEAR_BCN_SPACE0_8197F(x) | BIT_BCN_SPACE0_8197F(v))
+
+/* 2 REG_DRVERLYINT_8197F */
+
+#define BIT_SHIFT_DRVERLYITV_8197F 0
+#define BIT_MASK_DRVERLYITV_8197F 0xff
+#define BIT_DRVERLYITV_8197F(x)                                                \
+	(((x) & BIT_MASK_DRVERLYITV_8197F) << BIT_SHIFT_DRVERLYITV_8197F)
+#define BITS_DRVERLYITV_8197F                                                  \
+	(BIT_MASK_DRVERLYITV_8197F << BIT_SHIFT_DRVERLYITV_8197F)
+#define BIT_CLEAR_DRVERLYITV_8197F(x) ((x) & (~BITS_DRVERLYITV_8197F))
+#define BIT_GET_DRVERLYITV_8197F(x)                                            \
+	(((x) >> BIT_SHIFT_DRVERLYITV_8197F) & BIT_MASK_DRVERLYITV_8197F)
+#define BIT_SET_DRVERLYITV_8197F(x, v)                                         \
+	(BIT_CLEAR_DRVERLYITV_8197F(x) | BIT_DRVERLYITV_8197F(v))
+
+/* 2 REG_BCNDMATIM_8197F */
+
+#define BIT_SHIFT_BCNDMATIM_8197F 0
+#define BIT_MASK_BCNDMATIM_8197F 0xff
+#define BIT_BCNDMATIM_8197F(x)                                                 \
+	(((x) & BIT_MASK_BCNDMATIM_8197F) << BIT_SHIFT_BCNDMATIM_8197F)
+#define BITS_BCNDMATIM_8197F                                                   \
+	(BIT_MASK_BCNDMATIM_8197F << BIT_SHIFT_BCNDMATIM_8197F)
+#define BIT_CLEAR_BCNDMATIM_8197F(x) ((x) & (~BITS_BCNDMATIM_8197F))
+#define BIT_GET_BCNDMATIM_8197F(x)                                             \
+	(((x) >> BIT_SHIFT_BCNDMATIM_8197F) & BIT_MASK_BCNDMATIM_8197F)
+#define BIT_SET_BCNDMATIM_8197F(x, v)                                          \
+	(BIT_CLEAR_BCNDMATIM_8197F(x) | BIT_BCNDMATIM_8197F(v))
+
+/* 2 REG_ATIMWND_8197F */
+
+#define BIT_SHIFT_ATIMWND0_8197F 0
+#define BIT_MASK_ATIMWND0_8197F 0xffff
+#define BIT_ATIMWND0_8197F(x)                                                  \
+	(((x) & BIT_MASK_ATIMWND0_8197F) << BIT_SHIFT_ATIMWND0_8197F)
+#define BITS_ATIMWND0_8197F                                                    \
+	(BIT_MASK_ATIMWND0_8197F << BIT_SHIFT_ATIMWND0_8197F)
+#define BIT_CLEAR_ATIMWND0_8197F(x) ((x) & (~BITS_ATIMWND0_8197F))
+#define BIT_GET_ATIMWND0_8197F(x)                                              \
+	(((x) >> BIT_SHIFT_ATIMWND0_8197F) & BIT_MASK_ATIMWND0_8197F)
+#define BIT_SET_ATIMWND0_8197F(x, v)                                           \
+	(BIT_CLEAR_ATIMWND0_8197F(x) | BIT_ATIMWND0_8197F(v))
+
+/* 2 REG_USTIME_TSF_8197F */
+
+#define BIT_SHIFT_USTIME_TSF_V1_8197F 0
+#define BIT_MASK_USTIME_TSF_V1_8197F 0xff
+#define BIT_USTIME_TSF_V1_8197F(x)                                             \
+	(((x) & BIT_MASK_USTIME_TSF_V1_8197F) << BIT_SHIFT_USTIME_TSF_V1_8197F)
+#define BITS_USTIME_TSF_V1_8197F                                               \
+	(BIT_MASK_USTIME_TSF_V1_8197F << BIT_SHIFT_USTIME_TSF_V1_8197F)
+#define BIT_CLEAR_USTIME_TSF_V1_8197F(x) ((x) & (~BITS_USTIME_TSF_V1_8197F))
+#define BIT_GET_USTIME_TSF_V1_8197F(x)                                         \
+	(((x) >> BIT_SHIFT_USTIME_TSF_V1_8197F) & BIT_MASK_USTIME_TSF_V1_8197F)
+#define BIT_SET_USTIME_TSF_V1_8197F(x, v)                                      \
+	(BIT_CLEAR_USTIME_TSF_V1_8197F(x) | BIT_USTIME_TSF_V1_8197F(v))
+
+/* 2 REG_BCN_MAX_ERR_8197F */
+
+#define BIT_SHIFT_BCN_MAX_ERR_8197F 0
+#define BIT_MASK_BCN_MAX_ERR_8197F 0xff
+#define BIT_BCN_MAX_ERR_8197F(x)                                               \
+	(((x) & BIT_MASK_BCN_MAX_ERR_8197F) << BIT_SHIFT_BCN_MAX_ERR_8197F)
+#define BITS_BCN_MAX_ERR_8197F                                                 \
+	(BIT_MASK_BCN_MAX_ERR_8197F << BIT_SHIFT_BCN_MAX_ERR_8197F)
+#define BIT_CLEAR_BCN_MAX_ERR_8197F(x) ((x) & (~BITS_BCN_MAX_ERR_8197F))
+#define BIT_GET_BCN_MAX_ERR_8197F(x)                                           \
+	(((x) >> BIT_SHIFT_BCN_MAX_ERR_8197F) & BIT_MASK_BCN_MAX_ERR_8197F)
+#define BIT_SET_BCN_MAX_ERR_8197F(x, v)                                        \
+	(BIT_CLEAR_BCN_MAX_ERR_8197F(x) | BIT_BCN_MAX_ERR_8197F(v))
+
+/* 2 REG_RXTSF_OFFSET_CCK_8197F */
+
+#define BIT_SHIFT_CCK_RXTSF_OFFSET_8197F 0
+#define BIT_MASK_CCK_RXTSF_OFFSET_8197F 0xff
+#define BIT_CCK_RXTSF_OFFSET_8197F(x)                                          \
+	(((x) & BIT_MASK_CCK_RXTSF_OFFSET_8197F)                               \
+	 << BIT_SHIFT_CCK_RXTSF_OFFSET_8197F)
+#define BITS_CCK_RXTSF_OFFSET_8197F                                            \
+	(BIT_MASK_CCK_RXTSF_OFFSET_8197F << BIT_SHIFT_CCK_RXTSF_OFFSET_8197F)
+#define BIT_CLEAR_CCK_RXTSF_OFFSET_8197F(x)                                    \
+	((x) & (~BITS_CCK_RXTSF_OFFSET_8197F))
+#define BIT_GET_CCK_RXTSF_OFFSET_8197F(x)                                      \
+	(((x) >> BIT_SHIFT_CCK_RXTSF_OFFSET_8197F) &                           \
+	 BIT_MASK_CCK_RXTSF_OFFSET_8197F)
+#define BIT_SET_CCK_RXTSF_OFFSET_8197F(x, v)                                   \
+	(BIT_CLEAR_CCK_RXTSF_OFFSET_8197F(x) | BIT_CCK_RXTSF_OFFSET_8197F(v))
+
+/* 2 REG_RXTSF_OFFSET_OFDM_8197F */
+
+#define BIT_SHIFT_OFDM_RXTSF_OFFSET_8197F 0
+#define BIT_MASK_OFDM_RXTSF_OFFSET_8197F 0xff
+#define BIT_OFDM_RXTSF_OFFSET_8197F(x)                                         \
+	(((x) & BIT_MASK_OFDM_RXTSF_OFFSET_8197F)                              \
+	 << BIT_SHIFT_OFDM_RXTSF_OFFSET_8197F)
+#define BITS_OFDM_RXTSF_OFFSET_8197F                                           \
+	(BIT_MASK_OFDM_RXTSF_OFFSET_8197F << BIT_SHIFT_OFDM_RXTSF_OFFSET_8197F)
+#define BIT_CLEAR_OFDM_RXTSF_OFFSET_8197F(x)                                   \
+	((x) & (~BITS_OFDM_RXTSF_OFFSET_8197F))
+#define BIT_GET_OFDM_RXTSF_OFFSET_8197F(x)                                     \
+	(((x) >> BIT_SHIFT_OFDM_RXTSF_OFFSET_8197F) &                          \
+	 BIT_MASK_OFDM_RXTSF_OFFSET_8197F)
+#define BIT_SET_OFDM_RXTSF_OFFSET_8197F(x, v)                                  \
+	(BIT_CLEAR_OFDM_RXTSF_OFFSET_8197F(x) | BIT_OFDM_RXTSF_OFFSET_8197F(v))
+
+/* 2 REG_TSFTR_8197F */
+
+#define BIT_SHIFT_TSF_TIMER_8197F 0
+#define BIT_MASK_TSF_TIMER_8197F 0xffffffffffffffffL
+#define BIT_TSF_TIMER_8197F(x)                                                 \
+	(((x) & BIT_MASK_TSF_TIMER_8197F) << BIT_SHIFT_TSF_TIMER_8197F)
+#define BITS_TSF_TIMER_8197F                                                   \
+	(BIT_MASK_TSF_TIMER_8197F << BIT_SHIFT_TSF_TIMER_8197F)
+#define BIT_CLEAR_TSF_TIMER_8197F(x) ((x) & (~BITS_TSF_TIMER_8197F))
+#define BIT_GET_TSF_TIMER_8197F(x)                                             \
+	(((x) >> BIT_SHIFT_TSF_TIMER_8197F) & BIT_MASK_TSF_TIMER_8197F)
+#define BIT_SET_TSF_TIMER_8197F(x, v)                                          \
+	(BIT_CLEAR_TSF_TIMER_8197F(x) | BIT_TSF_TIMER_8197F(v))
+
+/* 2 REG_FREERUN_CNT_8197F */
+
+#define BIT_SHIFT_FREERUN_CNT_8197F 0
+#define BIT_MASK_FREERUN_CNT_8197F 0xffffffffffffffffL
+#define BIT_FREERUN_CNT_8197F(x)                                               \
+	(((x) & BIT_MASK_FREERUN_CNT_8197F) << BIT_SHIFT_FREERUN_CNT_8197F)
+#define BITS_FREERUN_CNT_8197F                                                 \
+	(BIT_MASK_FREERUN_CNT_8197F << BIT_SHIFT_FREERUN_CNT_8197F)
+#define BIT_CLEAR_FREERUN_CNT_8197F(x) ((x) & (~BITS_FREERUN_CNT_8197F))
+#define BIT_GET_FREERUN_CNT_8197F(x)                                           \
+	(((x) >> BIT_SHIFT_FREERUN_CNT_8197F) & BIT_MASK_FREERUN_CNT_8197F)
+#define BIT_SET_FREERUN_CNT_8197F(x, v)                                        \
+	(BIT_CLEAR_FREERUN_CNT_8197F(x) | BIT_FREERUN_CNT_8197F(v))
+
+/* 2 REG_ATIMWND1_8197F */
+
+#define BIT_SHIFT_ATIMWND1_V1_8197F 0
+#define BIT_MASK_ATIMWND1_V1_8197F 0xff
+#define BIT_ATIMWND1_V1_8197F(x)                                               \
+	(((x) & BIT_MASK_ATIMWND1_V1_8197F) << BIT_SHIFT_ATIMWND1_V1_8197F)
+#define BITS_ATIMWND1_V1_8197F                                                 \
+	(BIT_MASK_ATIMWND1_V1_8197F << BIT_SHIFT_ATIMWND1_V1_8197F)
+#define BIT_CLEAR_ATIMWND1_V1_8197F(x) ((x) & (~BITS_ATIMWND1_V1_8197F))
+#define BIT_GET_ATIMWND1_V1_8197F(x)                                           \
+	(((x) >> BIT_SHIFT_ATIMWND1_V1_8197F) & BIT_MASK_ATIMWND1_V1_8197F)
+#define BIT_SET_ATIMWND1_V1_8197F(x, v)                                        \
+	(BIT_CLEAR_ATIMWND1_V1_8197F(x) | BIT_ATIMWND1_V1_8197F(v))
+
+/* 2 REG_TBTT_PROHIBIT_INFRA_8197F */
+
+#define BIT_SHIFT_TBTT_PROHIBIT_INFRA_8197F 0
+#define BIT_MASK_TBTT_PROHIBIT_INFRA_8197F 0xff
+#define BIT_TBTT_PROHIBIT_INFRA_8197F(x)                                       \
+	(((x) & BIT_MASK_TBTT_PROHIBIT_INFRA_8197F)                            \
+	 << BIT_SHIFT_TBTT_PROHIBIT_INFRA_8197F)
+#define BITS_TBTT_PROHIBIT_INFRA_8197F                                         \
+	(BIT_MASK_TBTT_PROHIBIT_INFRA_8197F                                    \
+	 << BIT_SHIFT_TBTT_PROHIBIT_INFRA_8197F)
+#define BIT_CLEAR_TBTT_PROHIBIT_INFRA_8197F(x)                                 \
+	((x) & (~BITS_TBTT_PROHIBIT_INFRA_8197F))
+#define BIT_GET_TBTT_PROHIBIT_INFRA_8197F(x)                                   \
+	(((x) >> BIT_SHIFT_TBTT_PROHIBIT_INFRA_8197F) &                        \
+	 BIT_MASK_TBTT_PROHIBIT_INFRA_8197F)
+#define BIT_SET_TBTT_PROHIBIT_INFRA_8197F(x, v)                                \
+	(BIT_CLEAR_TBTT_PROHIBIT_INFRA_8197F(x) |                              \
+	 BIT_TBTT_PROHIBIT_INFRA_8197F(v))
+
+/* 2 REG_CTWND_8197F */
+
+#define BIT_SHIFT_CTWND_8197F 0
+#define BIT_MASK_CTWND_8197F 0xff
+#define BIT_CTWND_8197F(x)                                                     \
+	(((x) & BIT_MASK_CTWND_8197F) << BIT_SHIFT_CTWND_8197F)
+#define BITS_CTWND_8197F (BIT_MASK_CTWND_8197F << BIT_SHIFT_CTWND_8197F)
+#define BIT_CLEAR_CTWND_8197F(x) ((x) & (~BITS_CTWND_8197F))
+#define BIT_GET_CTWND_8197F(x)                                                 \
+	(((x) >> BIT_SHIFT_CTWND_8197F) & BIT_MASK_CTWND_8197F)
+#define BIT_SET_CTWND_8197F(x, v)                                              \
+	(BIT_CLEAR_CTWND_8197F(x) | BIT_CTWND_8197F(v))
+
+/* 2 REG_BCNIVLCUNT_8197F */
+
+#define BIT_SHIFT_BCNIVLCUNT_8197F 0
+#define BIT_MASK_BCNIVLCUNT_8197F 0x7f
+#define BIT_BCNIVLCUNT_8197F(x)                                                \
+	(((x) & BIT_MASK_BCNIVLCUNT_8197F) << BIT_SHIFT_BCNIVLCUNT_8197F)
+#define BITS_BCNIVLCUNT_8197F                                                  \
+	(BIT_MASK_BCNIVLCUNT_8197F << BIT_SHIFT_BCNIVLCUNT_8197F)
+#define BIT_CLEAR_BCNIVLCUNT_8197F(x) ((x) & (~BITS_BCNIVLCUNT_8197F))
+#define BIT_GET_BCNIVLCUNT_8197F(x)                                            \
+	(((x) >> BIT_SHIFT_BCNIVLCUNT_8197F) & BIT_MASK_BCNIVLCUNT_8197F)
+#define BIT_SET_BCNIVLCUNT_8197F(x, v)                                         \
+	(BIT_CLEAR_BCNIVLCUNT_8197F(x) | BIT_BCNIVLCUNT_8197F(v))
+
+/* 2 REG_BCNDROPCTRL_8197F */
+#define BIT_BEACON_DROP_EN_8197F BIT(7)
+
+#define BIT_SHIFT_BEACON_DROP_IVL_8197F 0
+#define BIT_MASK_BEACON_DROP_IVL_8197F 0x7f
+#define BIT_BEACON_DROP_IVL_8197F(x)                                           \
+	(((x) & BIT_MASK_BEACON_DROP_IVL_8197F)                                \
+	 << BIT_SHIFT_BEACON_DROP_IVL_8197F)
+#define BITS_BEACON_DROP_IVL_8197F                                             \
+	(BIT_MASK_BEACON_DROP_IVL_8197F << BIT_SHIFT_BEACON_DROP_IVL_8197F)
+#define BIT_CLEAR_BEACON_DROP_IVL_8197F(x) ((x) & (~BITS_BEACON_DROP_IVL_8197F))
+#define BIT_GET_BEACON_DROP_IVL_8197F(x)                                       \
+	(((x) >> BIT_SHIFT_BEACON_DROP_IVL_8197F) &                            \
+	 BIT_MASK_BEACON_DROP_IVL_8197F)
+#define BIT_SET_BEACON_DROP_IVL_8197F(x, v)                                    \
+	(BIT_CLEAR_BEACON_DROP_IVL_8197F(x) | BIT_BEACON_DROP_IVL_8197F(v))
+
+/* 2 REG_HGQ_TIMEOUT_PERIOD_8197F */
+
+#define BIT_SHIFT_HGQ_TIMEOUT_PERIOD_8197F 0
+#define BIT_MASK_HGQ_TIMEOUT_PERIOD_8197F 0xff
+#define BIT_HGQ_TIMEOUT_PERIOD_8197F(x)                                        \
+	(((x) & BIT_MASK_HGQ_TIMEOUT_PERIOD_8197F)                             \
+	 << BIT_SHIFT_HGQ_TIMEOUT_PERIOD_8197F)
+#define BITS_HGQ_TIMEOUT_PERIOD_8197F                                          \
+	(BIT_MASK_HGQ_TIMEOUT_PERIOD_8197F                                     \
+	 << BIT_SHIFT_HGQ_TIMEOUT_PERIOD_8197F)
+#define BIT_CLEAR_HGQ_TIMEOUT_PERIOD_8197F(x)                                  \
+	((x) & (~BITS_HGQ_TIMEOUT_PERIOD_8197F))
+#define BIT_GET_HGQ_TIMEOUT_PERIOD_8197F(x)                                    \
+	(((x) >> BIT_SHIFT_HGQ_TIMEOUT_PERIOD_8197F) &                         \
+	 BIT_MASK_HGQ_TIMEOUT_PERIOD_8197F)
+#define BIT_SET_HGQ_TIMEOUT_PERIOD_8197F(x, v)                                 \
+	(BIT_CLEAR_HGQ_TIMEOUT_PERIOD_8197F(x) |                               \
+	 BIT_HGQ_TIMEOUT_PERIOD_8197F(v))
+
+/* 2 REG_TXCMD_TIMEOUT_PERIOD_8197F */
+
+#define BIT_SHIFT_TXCMD_TIMEOUT_PERIOD_8197F 0
+#define BIT_MASK_TXCMD_TIMEOUT_PERIOD_8197F 0xff
+#define BIT_TXCMD_TIMEOUT_PERIOD_8197F(x)                                      \
+	(((x) & BIT_MASK_TXCMD_TIMEOUT_PERIOD_8197F)                           \
+	 << BIT_SHIFT_TXCMD_TIMEOUT_PERIOD_8197F)
+#define BITS_TXCMD_TIMEOUT_PERIOD_8197F                                        \
+	(BIT_MASK_TXCMD_TIMEOUT_PERIOD_8197F                                   \
+	 << BIT_SHIFT_TXCMD_TIMEOUT_PERIOD_8197F)
+#define BIT_CLEAR_TXCMD_TIMEOUT_PERIOD_8197F(x)                                \
+	((x) & (~BITS_TXCMD_TIMEOUT_PERIOD_8197F))
+#define BIT_GET_TXCMD_TIMEOUT_PERIOD_8197F(x)                                  \
+	(((x) >> BIT_SHIFT_TXCMD_TIMEOUT_PERIOD_8197F) &                       \
+	 BIT_MASK_TXCMD_TIMEOUT_PERIOD_8197F)
+#define BIT_SET_TXCMD_TIMEOUT_PERIOD_8197F(x, v)                               \
+	(BIT_CLEAR_TXCMD_TIMEOUT_PERIOD_8197F(x) |                             \
+	 BIT_TXCMD_TIMEOUT_PERIOD_8197F(v))
+
+/* 2 REG_MISC_CTRL_8197F */
+#define BIT_DIS_MARK_TSF_US_8197F BIT(7)
+#define BIT_EN_TSFAUTO_SYNC_8197F BIT(6)
+#define BIT_DIS_TRX_CAL_BCN_8197F BIT(5)
+#define BIT_DIS_TX_CAL_TBTT_8197F BIT(4)
+#define BIT_EN_FREECNT_8197F BIT(3)
+#define BIT_BCN_AGGRESSION_8197F BIT(2)
+
+#define BIT_SHIFT_DIS_SECONDARY_CCA_8197F 0
+#define BIT_MASK_DIS_SECONDARY_CCA_8197F 0x3
+#define BIT_DIS_SECONDARY_CCA_8197F(x)                                         \
+	(((x) & BIT_MASK_DIS_SECONDARY_CCA_8197F)                              \
+	 << BIT_SHIFT_DIS_SECONDARY_CCA_8197F)
+#define BITS_DIS_SECONDARY_CCA_8197F                                           \
+	(BIT_MASK_DIS_SECONDARY_CCA_8197F << BIT_SHIFT_DIS_SECONDARY_CCA_8197F)
+#define BIT_CLEAR_DIS_SECONDARY_CCA_8197F(x)                                   \
+	((x) & (~BITS_DIS_SECONDARY_CCA_8197F))
+#define BIT_GET_DIS_SECONDARY_CCA_8197F(x)                                     \
+	(((x) >> BIT_SHIFT_DIS_SECONDARY_CCA_8197F) &                          \
+	 BIT_MASK_DIS_SECONDARY_CCA_8197F)
+#define BIT_SET_DIS_SECONDARY_CCA_8197F(x, v)                                  \
+	(BIT_CLEAR_DIS_SECONDARY_CCA_8197F(x) | BIT_DIS_SECONDARY_CCA_8197F(v))
+
+/* 2 REG_BCN_CTRL_CLINT1_8197F */
+#define BIT_CLI1_DIS_RX_BSSID_FIT_8197F BIT(6)
+#define BIT_CLI1_DIS_TSF_UDT_8197F BIT(4)
+#define BIT_CLI1_EN_BCN_FUNCTION_8197F BIT(3)
+#define BIT_CLI1_EN_RXBCN_RPT_8197F BIT(2)
+#define BIT_CLI1_ENP2P_CTWINDOW_8197F BIT(1)
+#define BIT_CLI1_ENP2P_BCNQ_AREA_8197F BIT(0)
+
+/* 2 REG_BCN_CTRL_CLINT2_8197F */
+#define BIT_CLI2_DIS_RX_BSSID_FIT_8197F BIT(6)
+#define BIT_CLI2_DIS_TSF_UDT_8197F BIT(4)
+#define BIT_CLI2_EN_BCN_FUNCTION_8197F BIT(3)
+#define BIT_CLI2_EN_RXBCN_RPT_8197F BIT(2)
+#define BIT_CLI2_ENP2P_CTWINDOW_8197F BIT(1)
+#define BIT_CLI2_ENP2P_BCNQ_AREA_8197F BIT(0)
+
+/* 2 REG_BCN_CTRL_CLINT3_8197F */
+#define BIT_CLI3_DIS_RX_BSSID_FIT_8197F BIT(6)
+#define BIT_CLI3_DIS_TSF_UDT_8197F BIT(4)
+#define BIT_CLI3_EN_BCN_FUNCTION_8197F BIT(3)
+#define BIT_CLI3_EN_RXBCN_RPT_8197F BIT(2)
+#define BIT_CLI3_ENP2P_CTWINDOW_8197F BIT(1)
+#define BIT_CLI3_ENP2P_BCNQ_AREA_8197F BIT(0)
+
+/* 2 REG_EXTEND_CTRL_8197F */
+#define BIT_EN_TSFBIT32_RST_P2P2_8197F BIT(5)
+#define BIT_EN_TSFBIT32_RST_P2P1_8197F BIT(4)
+
+#define BIT_SHIFT_PORT_SEL_8197F 0
+#define BIT_MASK_PORT_SEL_8197F 0x7
+#define BIT_PORT_SEL_8197F(x)                                                  \
+	(((x) & BIT_MASK_PORT_SEL_8197F) << BIT_SHIFT_PORT_SEL_8197F)
+#define BITS_PORT_SEL_8197F                                                    \
+	(BIT_MASK_PORT_SEL_8197F << BIT_SHIFT_PORT_SEL_8197F)
+#define BIT_CLEAR_PORT_SEL_8197F(x) ((x) & (~BITS_PORT_SEL_8197F))
+#define BIT_GET_PORT_SEL_8197F(x)                                              \
+	(((x) >> BIT_SHIFT_PORT_SEL_8197F) & BIT_MASK_PORT_SEL_8197F)
+#define BIT_SET_PORT_SEL_8197F(x, v)                                           \
+	(BIT_CLEAR_PORT_SEL_8197F(x) | BIT_PORT_SEL_8197F(v))
+
+/* 2 REG_P2PPS1_SPEC_STATE_8197F */
+#define BIT_P2P1_SPEC_POWER_STATE_8197F BIT(7)
+#define BIT_P2P1_SPEC_CTWINDOW_ON_8197F BIT(6)
+#define BIT_P2P1_SPEC_BCN_AREA_ON_8197F BIT(5)
+#define BIT_P2P1_SPEC_CTWIN_EARLY_DISTX_8197F BIT(4)
+#define BIT_P2P1_SPEC_NOA1_OFF_PERIOD_8197F BIT(3)
+#define BIT_P2P1_SPEC_FORCE_DOZE1_8197F BIT(2)
+#define BIT_P2P1_SPEC_NOA0_OFF_PERIOD_8197F BIT(1)
+#define BIT_P2P1_SPEC_FORCE_DOZE0_8197F BIT(0)
+
+/* 2 REG_P2PPS1_STATE_8197F */
+#define BIT_P2P1_POWER_STATE_8197F BIT(7)
+#define BIT_P2P1_CTWINDOW_ON_8197F BIT(6)
+#define BIT_P2P1_BEACON_AREA_ON_8197F BIT(5)
+#define BIT_P2P1_CTWIN_EARLY_DISTX_8197F BIT(4)
+#define BIT_P2P1_NOA1_OFF_PERIOD_8197F BIT(3)
+#define BIT_P2P1_FORCE_DOZE1_8197F BIT(2)
+#define BIT_P2P1_NOA0_OFF_PERIOD_8197F BIT(1)
+#define BIT_P2P1_FORCE_DOZE0_8197F BIT(0)
+
+/* 2 REG_P2PPS2_SPEC_STATE_8197F */
+#define BIT_P2P2_SPEC_POWER_STATE_8197F BIT(7)
+#define BIT_P2P2_SPEC_CTWINDOW_ON_8197F BIT(6)
+#define BIT_P2P2_SPEC_BCN_AREA_ON_8197F BIT(5)
+#define BIT_P2P2_SPEC_CTWIN_EARLY_DISTX_8197F BIT(4)
+#define BIT_P2P2_SPEC_NOA1_OFF_PERIOD_8197F BIT(3)
+#define BIT_P2P2_SPEC_FORCE_DOZE1_8197F BIT(2)
+#define BIT_P2P2_SPEC_NOA0_OFF_PERIOD_8197F BIT(1)
+#define BIT_P2P2_SPEC_FORCE_DOZE0_8197F BIT(0)
+
+/* 2 REG_P2PPS2_STATE_8197F */
+#define BIT_P2P2_POWER_STATE_8197F BIT(7)
+#define BIT_P2P2_CTWINDOW_ON_8197F BIT(6)
+#define BIT_P2P2_BEACON_AREA_ON_8197F BIT(5)
+#define BIT_P2P2_CTWIN_EARLY_DISTX_8197F BIT(4)
+#define BIT_P2P2_NOA1_OFF_PERIOD_8197F BIT(3)
+#define BIT_P2P2_FORCE_DOZE1_8197F BIT(2)
+#define BIT_P2P2_NOA0_OFF_PERIOD_8197F BIT(1)
+#define BIT_P2P2_FORCE_DOZE0_8197F BIT(0)
+
+/* 2 REG_PS_TIMER0_8197F */
+
+#define BIT_SHIFT_PSTIMER0_INT_8197F 5
+#define BIT_MASK_PSTIMER0_INT_8197F 0x7ffffff
+#define BIT_PSTIMER0_INT_8197F(x)                                              \
+	(((x) & BIT_MASK_PSTIMER0_INT_8197F) << BIT_SHIFT_PSTIMER0_INT_8197F)
+#define BITS_PSTIMER0_INT_8197F                                                \
+	(BIT_MASK_PSTIMER0_INT_8197F << BIT_SHIFT_PSTIMER0_INT_8197F)
+#define BIT_CLEAR_PSTIMER0_INT_8197F(x) ((x) & (~BITS_PSTIMER0_INT_8197F))
+#define BIT_GET_PSTIMER0_INT_8197F(x)                                          \
+	(((x) >> BIT_SHIFT_PSTIMER0_INT_8197F) & BIT_MASK_PSTIMER0_INT_8197F)
+#define BIT_SET_PSTIMER0_INT_8197F(x, v)                                       \
+	(BIT_CLEAR_PSTIMER0_INT_8197F(x) | BIT_PSTIMER0_INT_8197F(v))
+
+/* 2 REG_PS_TIMER1_8197F */
+
+#define BIT_SHIFT_PSTIMER1_INT_8197F 5
+#define BIT_MASK_PSTIMER1_INT_8197F 0x7ffffff
+#define BIT_PSTIMER1_INT_8197F(x)                                              \
+	(((x) & BIT_MASK_PSTIMER1_INT_8197F) << BIT_SHIFT_PSTIMER1_INT_8197F)
+#define BITS_PSTIMER1_INT_8197F                                                \
+	(BIT_MASK_PSTIMER1_INT_8197F << BIT_SHIFT_PSTIMER1_INT_8197F)
+#define BIT_CLEAR_PSTIMER1_INT_8197F(x) ((x) & (~BITS_PSTIMER1_INT_8197F))
+#define BIT_GET_PSTIMER1_INT_8197F(x)                                          \
+	(((x) >> BIT_SHIFT_PSTIMER1_INT_8197F) & BIT_MASK_PSTIMER1_INT_8197F)
+#define BIT_SET_PSTIMER1_INT_8197F(x, v)                                       \
+	(BIT_CLEAR_PSTIMER1_INT_8197F(x) | BIT_PSTIMER1_INT_8197F(v))
+
+/* 2 REG_PS_TIMER2_8197F */
+
+#define BIT_SHIFT_PSTIMER2_INT_8197F 5
+#define BIT_MASK_PSTIMER2_INT_8197F 0x7ffffff
+#define BIT_PSTIMER2_INT_8197F(x)                                              \
+	(((x) & BIT_MASK_PSTIMER2_INT_8197F) << BIT_SHIFT_PSTIMER2_INT_8197F)
+#define BITS_PSTIMER2_INT_8197F                                                \
+	(BIT_MASK_PSTIMER2_INT_8197F << BIT_SHIFT_PSTIMER2_INT_8197F)
+#define BIT_CLEAR_PSTIMER2_INT_8197F(x) ((x) & (~BITS_PSTIMER2_INT_8197F))
+#define BIT_GET_PSTIMER2_INT_8197F(x)                                          \
+	(((x) >> BIT_SHIFT_PSTIMER2_INT_8197F) & BIT_MASK_PSTIMER2_INT_8197F)
+#define BIT_SET_PSTIMER2_INT_8197F(x, v)                                       \
+	(BIT_CLEAR_PSTIMER2_INT_8197F(x) | BIT_PSTIMER2_INT_8197F(v))
+
+/* 2 REG_TBTT_CTN_AREA_8197F */
+
+#define BIT_SHIFT_TBTT_CTN_AREA_8197F 0
+#define BIT_MASK_TBTT_CTN_AREA_8197F 0xff
+#define BIT_TBTT_CTN_AREA_8197F(x)                                             \
+	(((x) & BIT_MASK_TBTT_CTN_AREA_8197F) << BIT_SHIFT_TBTT_CTN_AREA_8197F)
+#define BITS_TBTT_CTN_AREA_8197F                                               \
+	(BIT_MASK_TBTT_CTN_AREA_8197F << BIT_SHIFT_TBTT_CTN_AREA_8197F)
+#define BIT_CLEAR_TBTT_CTN_AREA_8197F(x) ((x) & (~BITS_TBTT_CTN_AREA_8197F))
+#define BIT_GET_TBTT_CTN_AREA_8197F(x)                                         \
+	(((x) >> BIT_SHIFT_TBTT_CTN_AREA_8197F) & BIT_MASK_TBTT_CTN_AREA_8197F)
+#define BIT_SET_TBTT_CTN_AREA_8197F(x, v)                                      \
+	(BIT_CLEAR_TBTT_CTN_AREA_8197F(x) | BIT_TBTT_CTN_AREA_8197F(v))
+
+/* 2 REG_FORCE_BCN_IFS_8197F */
+
+#define BIT_SHIFT_FORCE_BCN_IFS_8197F 0
+#define BIT_MASK_FORCE_BCN_IFS_8197F 0xff
+#define BIT_FORCE_BCN_IFS_8197F(x)                                             \
+	(((x) & BIT_MASK_FORCE_BCN_IFS_8197F) << BIT_SHIFT_FORCE_BCN_IFS_8197F)
+#define BITS_FORCE_BCN_IFS_8197F                                               \
+	(BIT_MASK_FORCE_BCN_IFS_8197F << BIT_SHIFT_FORCE_BCN_IFS_8197F)
+#define BIT_CLEAR_FORCE_BCN_IFS_8197F(x) ((x) & (~BITS_FORCE_BCN_IFS_8197F))
+#define BIT_GET_FORCE_BCN_IFS_8197F(x)                                         \
+	(((x) >> BIT_SHIFT_FORCE_BCN_IFS_8197F) & BIT_MASK_FORCE_BCN_IFS_8197F)
+#define BIT_SET_FORCE_BCN_IFS_8197F(x, v)                                      \
+	(BIT_CLEAR_FORCE_BCN_IFS_8197F(x) | BIT_FORCE_BCN_IFS_8197F(v))
+
+/* 2 REG_TXOP_MIN_8197F */
+#define BIT_NAV_BLK_HGQ_8197F BIT(15)
+#define BIT_NAV_BLK_MGQ_8197F BIT(14)
+
+#define BIT_SHIFT_TXOP_MIN_8197F 0
+#define BIT_MASK_TXOP_MIN_8197F 0x3fff
+#define BIT_TXOP_MIN_8197F(x)                                                  \
+	(((x) & BIT_MASK_TXOP_MIN_8197F) << BIT_SHIFT_TXOP_MIN_8197F)
+#define BITS_TXOP_MIN_8197F                                                    \
+	(BIT_MASK_TXOP_MIN_8197F << BIT_SHIFT_TXOP_MIN_8197F)
+#define BIT_CLEAR_TXOP_MIN_8197F(x) ((x) & (~BITS_TXOP_MIN_8197F))
+#define BIT_GET_TXOP_MIN_8197F(x)                                              \
+	(((x) >> BIT_SHIFT_TXOP_MIN_8197F) & BIT_MASK_TXOP_MIN_8197F)
+#define BIT_SET_TXOP_MIN_8197F(x, v)                                           \
+	(BIT_CLEAR_TXOP_MIN_8197F(x) | BIT_TXOP_MIN_8197F(v))
+
+/* 2 REG_PRE_BKF_TIME_8197F */
+
+#define BIT_SHIFT_PRE_BKF_TIME_8197F 0
+#define BIT_MASK_PRE_BKF_TIME_8197F 0xff
+#define BIT_PRE_BKF_TIME_8197F(x)                                              \
+	(((x) & BIT_MASK_PRE_BKF_TIME_8197F) << BIT_SHIFT_PRE_BKF_TIME_8197F)
+#define BITS_PRE_BKF_TIME_8197F                                                \
+	(BIT_MASK_PRE_BKF_TIME_8197F << BIT_SHIFT_PRE_BKF_TIME_8197F)
+#define BIT_CLEAR_PRE_BKF_TIME_8197F(x) ((x) & (~BITS_PRE_BKF_TIME_8197F))
+#define BIT_GET_PRE_BKF_TIME_8197F(x)                                          \
+	(((x) >> BIT_SHIFT_PRE_BKF_TIME_8197F) & BIT_MASK_PRE_BKF_TIME_8197F)
+#define BIT_SET_PRE_BKF_TIME_8197F(x, v)                                       \
+	(BIT_CLEAR_PRE_BKF_TIME_8197F(x) | BIT_PRE_BKF_TIME_8197F(v))
+
+/* 2 REG_CROSS_TXOP_CTRL_8197F */
+#define BIT_DTIM_BYPASS_8197F BIT(2)
+#define BIT_RTS_NAV_TXOP_8197F BIT(1)
+#define BIT_NOT_CROSS_TXOP_8197F BIT(0)
+
+/* 2 REG_TBTT_INT_SHIFT_CLI0_8197F */
+#define BIT_TBTT_INT_SHIFT_DIR_CLI0_8197F BIT(7)
+
+#define BIT_SHIFT_TBTT_INT_SHIFT_CLI0_8197F 0
+#define BIT_MASK_TBTT_INT_SHIFT_CLI0_8197F 0x7f
+#define BIT_TBTT_INT_SHIFT_CLI0_8197F(x)                                       \
+	(((x) & BIT_MASK_TBTT_INT_SHIFT_CLI0_8197F)                            \
+	 << BIT_SHIFT_TBTT_INT_SHIFT_CLI0_8197F)
+#define BITS_TBTT_INT_SHIFT_CLI0_8197F                                         \
+	(BIT_MASK_TBTT_INT_SHIFT_CLI0_8197F                                    \
+	 << BIT_SHIFT_TBTT_INT_SHIFT_CLI0_8197F)
+#define BIT_CLEAR_TBTT_INT_SHIFT_CLI0_8197F(x)                                 \
+	((x) & (~BITS_TBTT_INT_SHIFT_CLI0_8197F))
+#define BIT_GET_TBTT_INT_SHIFT_CLI0_8197F(x)                                   \
+	(((x) >> BIT_SHIFT_TBTT_INT_SHIFT_CLI0_8197F) &                        \
+	 BIT_MASK_TBTT_INT_SHIFT_CLI0_8197F)
+#define BIT_SET_TBTT_INT_SHIFT_CLI0_8197F(x, v)                                \
+	(BIT_CLEAR_TBTT_INT_SHIFT_CLI0_8197F(x) |                              \
+	 BIT_TBTT_INT_SHIFT_CLI0_8197F(v))
+
+/* 2 REG_TBTT_INT_SHIFT_CLI1_8197F */
+#define BIT_TBTT_INT_SHIFT_DIR_CLI1_8197F BIT(7)
+
+#define BIT_SHIFT_TBTT_INT_SHIFT_CLI1_8197F 0
+#define BIT_MASK_TBTT_INT_SHIFT_CLI1_8197F 0x7f
+#define BIT_TBTT_INT_SHIFT_CLI1_8197F(x)                                       \
+	(((x) & BIT_MASK_TBTT_INT_SHIFT_CLI1_8197F)                            \
+	 << BIT_SHIFT_TBTT_INT_SHIFT_CLI1_8197F)
+#define BITS_TBTT_INT_SHIFT_CLI1_8197F                                         \
+	(BIT_MASK_TBTT_INT_SHIFT_CLI1_8197F                                    \
+	 << BIT_SHIFT_TBTT_INT_SHIFT_CLI1_8197F)
+#define BIT_CLEAR_TBTT_INT_SHIFT_CLI1_8197F(x)                                 \
+	((x) & (~BITS_TBTT_INT_SHIFT_CLI1_8197F))
+#define BIT_GET_TBTT_INT_SHIFT_CLI1_8197F(x)                                   \
+	(((x) >> BIT_SHIFT_TBTT_INT_SHIFT_CLI1_8197F) &                        \
+	 BIT_MASK_TBTT_INT_SHIFT_CLI1_8197F)
+#define BIT_SET_TBTT_INT_SHIFT_CLI1_8197F(x, v)                                \
+	(BIT_CLEAR_TBTT_INT_SHIFT_CLI1_8197F(x) |                              \
+	 BIT_TBTT_INT_SHIFT_CLI1_8197F(v))
+
+/* 2 REG_TBTT_INT_SHIFT_CLI2_8197F */
+#define BIT_TBTT_INT_SHIFT_DIR_CLI2_8197F BIT(7)
+
+#define BIT_SHIFT_TBTT_INT_SHIFT_CLI2_8197F 0
+#define BIT_MASK_TBTT_INT_SHIFT_CLI2_8197F 0x7f
+#define BIT_TBTT_INT_SHIFT_CLI2_8197F(x)                                       \
+	(((x) & BIT_MASK_TBTT_INT_SHIFT_CLI2_8197F)                            \
+	 << BIT_SHIFT_TBTT_INT_SHIFT_CLI2_8197F)
+#define BITS_TBTT_INT_SHIFT_CLI2_8197F                                         \
+	(BIT_MASK_TBTT_INT_SHIFT_CLI2_8197F                                    \
+	 << BIT_SHIFT_TBTT_INT_SHIFT_CLI2_8197F)
+#define BIT_CLEAR_TBTT_INT_SHIFT_CLI2_8197F(x)                                 \
+	((x) & (~BITS_TBTT_INT_SHIFT_CLI2_8197F))
+#define BIT_GET_TBTT_INT_SHIFT_CLI2_8197F(x)                                   \
+	(((x) >> BIT_SHIFT_TBTT_INT_SHIFT_CLI2_8197F) &                        \
+	 BIT_MASK_TBTT_INT_SHIFT_CLI2_8197F)
+#define BIT_SET_TBTT_INT_SHIFT_CLI2_8197F(x, v)                                \
+	(BIT_CLEAR_TBTT_INT_SHIFT_CLI2_8197F(x) |                              \
+	 BIT_TBTT_INT_SHIFT_CLI2_8197F(v))
+
+/* 2 REG_TBTT_INT_SHIFT_CLI3_8197F */
+#define BIT_TBTT_INT_SHIFT_DIR_CLI3_8197F BIT(7)
+
+#define BIT_SHIFT_TBTT_INT_SHIFT_CLI3_8197F 0
+#define BIT_MASK_TBTT_INT_SHIFT_CLI3_8197F 0x7f
+#define BIT_TBTT_INT_SHIFT_CLI3_8197F(x)                                       \
+	(((x) & BIT_MASK_TBTT_INT_SHIFT_CLI3_8197F)                            \
+	 << BIT_SHIFT_TBTT_INT_SHIFT_CLI3_8197F)
+#define BITS_TBTT_INT_SHIFT_CLI3_8197F                                         \
+	(BIT_MASK_TBTT_INT_SHIFT_CLI3_8197F                                    \
+	 << BIT_SHIFT_TBTT_INT_SHIFT_CLI3_8197F)
+#define BIT_CLEAR_TBTT_INT_SHIFT_CLI3_8197F(x)                                 \
+	((x) & (~BITS_TBTT_INT_SHIFT_CLI3_8197F))
+#define BIT_GET_TBTT_INT_SHIFT_CLI3_8197F(x)                                   \
+	(((x) >> BIT_SHIFT_TBTT_INT_SHIFT_CLI3_8197F) &                        \
+	 BIT_MASK_TBTT_INT_SHIFT_CLI3_8197F)
+#define BIT_SET_TBTT_INT_SHIFT_CLI3_8197F(x, v)                                \
+	(BIT_CLEAR_TBTT_INT_SHIFT_CLI3_8197F(x) |                              \
+	 BIT_TBTT_INT_SHIFT_CLI3_8197F(v))
+
+/* 2 REG_TBTT_INT_SHIFT_ENABLE_8197F */
+#define BIT_EN_TBTT_RTY_8197F BIT(1)
+#define BIT_TBTT_INT_SHIFT_ENABLE_8197F BIT(0)
+
+/* 2 REG_ATIMWND2_8197F */
+
+#define BIT_SHIFT_ATIMWND2_8197F 0
+#define BIT_MASK_ATIMWND2_8197F 0xff
+#define BIT_ATIMWND2_8197F(x)                                                  \
+	(((x) & BIT_MASK_ATIMWND2_8197F) << BIT_SHIFT_ATIMWND2_8197F)
+#define BITS_ATIMWND2_8197F                                                    \
+	(BIT_MASK_ATIMWND2_8197F << BIT_SHIFT_ATIMWND2_8197F)
+#define BIT_CLEAR_ATIMWND2_8197F(x) ((x) & (~BITS_ATIMWND2_8197F))
+#define BIT_GET_ATIMWND2_8197F(x)                                              \
+	(((x) >> BIT_SHIFT_ATIMWND2_8197F) & BIT_MASK_ATIMWND2_8197F)
+#define BIT_SET_ATIMWND2_8197F(x, v)                                           \
+	(BIT_CLEAR_ATIMWND2_8197F(x) | BIT_ATIMWND2_8197F(v))
+
+/* 2 REG_ATIMWND3_8197F */
+
+#define BIT_SHIFT_ATIMWND3_8197F 0
+#define BIT_MASK_ATIMWND3_8197F 0xff
+#define BIT_ATIMWND3_8197F(x)                                                  \
+	(((x) & BIT_MASK_ATIMWND3_8197F) << BIT_SHIFT_ATIMWND3_8197F)
+#define BITS_ATIMWND3_8197F                                                    \
+	(BIT_MASK_ATIMWND3_8197F << BIT_SHIFT_ATIMWND3_8197F)
+#define BIT_CLEAR_ATIMWND3_8197F(x) ((x) & (~BITS_ATIMWND3_8197F))
+#define BIT_GET_ATIMWND3_8197F(x)                                              \
+	(((x) >> BIT_SHIFT_ATIMWND3_8197F) & BIT_MASK_ATIMWND3_8197F)
+#define BIT_SET_ATIMWND3_8197F(x, v)                                           \
+	(BIT_CLEAR_ATIMWND3_8197F(x) | BIT_ATIMWND3_8197F(v))
+
+/* 2 REG_ATIMWND4_8197F */
+
+#define BIT_SHIFT_ATIMWND4_8197F 0
+#define BIT_MASK_ATIMWND4_8197F 0xff
+#define BIT_ATIMWND4_8197F(x)                                                  \
+	(((x) & BIT_MASK_ATIMWND4_8197F) << BIT_SHIFT_ATIMWND4_8197F)
+#define BITS_ATIMWND4_8197F                                                    \
+	(BIT_MASK_ATIMWND4_8197F << BIT_SHIFT_ATIMWND4_8197F)
+#define BIT_CLEAR_ATIMWND4_8197F(x) ((x) & (~BITS_ATIMWND4_8197F))
+#define BIT_GET_ATIMWND4_8197F(x)                                              \
+	(((x) >> BIT_SHIFT_ATIMWND4_8197F) & BIT_MASK_ATIMWND4_8197F)
+#define BIT_SET_ATIMWND4_8197F(x, v)                                           \
+	(BIT_CLEAR_ATIMWND4_8197F(x) | BIT_ATIMWND4_8197F(v))
+
+/* 2 REG_ATIMWND5_8197F */
+
+#define BIT_SHIFT_ATIMWND5_8197F 0
+#define BIT_MASK_ATIMWND5_8197F 0xff
+#define BIT_ATIMWND5_8197F(x)                                                  \
+	(((x) & BIT_MASK_ATIMWND5_8197F) << BIT_SHIFT_ATIMWND5_8197F)
+#define BITS_ATIMWND5_8197F                                                    \
+	(BIT_MASK_ATIMWND5_8197F << BIT_SHIFT_ATIMWND5_8197F)
+#define BIT_CLEAR_ATIMWND5_8197F(x) ((x) & (~BITS_ATIMWND5_8197F))
+#define BIT_GET_ATIMWND5_8197F(x)                                              \
+	(((x) >> BIT_SHIFT_ATIMWND5_8197F) & BIT_MASK_ATIMWND5_8197F)
+#define BIT_SET_ATIMWND5_8197F(x, v)                                           \
+	(BIT_CLEAR_ATIMWND5_8197F(x) | BIT_ATIMWND5_8197F(v))
+
+/* 2 REG_ATIMWND6_8197F */
+
+#define BIT_SHIFT_ATIMWND6_8197F 0
+#define BIT_MASK_ATIMWND6_8197F 0xff
+#define BIT_ATIMWND6_8197F(x)                                                  \
+	(((x) & BIT_MASK_ATIMWND6_8197F) << BIT_SHIFT_ATIMWND6_8197F)
+#define BITS_ATIMWND6_8197F                                                    \
+	(BIT_MASK_ATIMWND6_8197F << BIT_SHIFT_ATIMWND6_8197F)
+#define BIT_CLEAR_ATIMWND6_8197F(x) ((x) & (~BITS_ATIMWND6_8197F))
+#define BIT_GET_ATIMWND6_8197F(x)                                              \
+	(((x) >> BIT_SHIFT_ATIMWND6_8197F) & BIT_MASK_ATIMWND6_8197F)
+#define BIT_SET_ATIMWND6_8197F(x, v)                                           \
+	(BIT_CLEAR_ATIMWND6_8197F(x) | BIT_ATIMWND6_8197F(v))
+
+/* 2 REG_ATIMWND7_8197F */
+
+#define BIT_SHIFT_ATIMWND7_8197F 0
+#define BIT_MASK_ATIMWND7_8197F 0xff
+#define BIT_ATIMWND7_8197F(x)                                                  \
+	(((x) & BIT_MASK_ATIMWND7_8197F) << BIT_SHIFT_ATIMWND7_8197F)
+#define BITS_ATIMWND7_8197F                                                    \
+	(BIT_MASK_ATIMWND7_8197F << BIT_SHIFT_ATIMWND7_8197F)
+#define BIT_CLEAR_ATIMWND7_8197F(x) ((x) & (~BITS_ATIMWND7_8197F))
+#define BIT_GET_ATIMWND7_8197F(x)                                              \
+	(((x) >> BIT_SHIFT_ATIMWND7_8197F) & BIT_MASK_ATIMWND7_8197F)
+#define BIT_SET_ATIMWND7_8197F(x, v)                                           \
+	(BIT_CLEAR_ATIMWND7_8197F(x) | BIT_ATIMWND7_8197F(v))
+
+/* 2 REG_ATIMUGT_8197F */
+
+#define BIT_SHIFT_ATIM_URGENT_8197F 0
+#define BIT_MASK_ATIM_URGENT_8197F 0xff
+#define BIT_ATIM_URGENT_8197F(x)                                               \
+	(((x) & BIT_MASK_ATIM_URGENT_8197F) << BIT_SHIFT_ATIM_URGENT_8197F)
+#define BITS_ATIM_URGENT_8197F                                                 \
+	(BIT_MASK_ATIM_URGENT_8197F << BIT_SHIFT_ATIM_URGENT_8197F)
+#define BIT_CLEAR_ATIM_URGENT_8197F(x) ((x) & (~BITS_ATIM_URGENT_8197F))
+#define BIT_GET_ATIM_URGENT_8197F(x)                                           \
+	(((x) >> BIT_SHIFT_ATIM_URGENT_8197F) & BIT_MASK_ATIM_URGENT_8197F)
+#define BIT_SET_ATIM_URGENT_8197F(x, v)                                        \
+	(BIT_CLEAR_ATIM_URGENT_8197F(x) | BIT_ATIM_URGENT_8197F(v))
+
+/* 2 REG_HIQ_NO_LMT_EN_8197F */
+#define BIT_HIQ_NO_LMT_EN_VAP7_8197F BIT(7)
+#define BIT_HIQ_NO_LMT_EN_VAP6_8197F BIT(6)
+#define BIT_HIQ_NO_LMT_EN_VAP5_8197F BIT(5)
+#define BIT_HIQ_NO_LMT_EN_VAP4_8197F BIT(4)
+#define BIT_HIQ_NO_LMT_EN_VAP3_8197F BIT(3)
+#define BIT_HIQ_NO_LMT_EN_VAP2_8197F BIT(2)
+#define BIT_HIQ_NO_LMT_EN_VAP1_8197F BIT(1)
+#define BIT_HIQ_NO_LMT_EN_ROOT_8197F BIT(0)
+
+/* 2 REG_DTIM_COUNTER_ROOT_8197F */
+
+#define BIT_SHIFT_DTIM_COUNT_ROOT_8197F 0
+#define BIT_MASK_DTIM_COUNT_ROOT_8197F 0xff
+#define BIT_DTIM_COUNT_ROOT_8197F(x)                                           \
+	(((x) & BIT_MASK_DTIM_COUNT_ROOT_8197F)                                \
+	 << BIT_SHIFT_DTIM_COUNT_ROOT_8197F)
+#define BITS_DTIM_COUNT_ROOT_8197F                                             \
+	(BIT_MASK_DTIM_COUNT_ROOT_8197F << BIT_SHIFT_DTIM_COUNT_ROOT_8197F)
+#define BIT_CLEAR_DTIM_COUNT_ROOT_8197F(x) ((x) & (~BITS_DTIM_COUNT_ROOT_8197F))
+#define BIT_GET_DTIM_COUNT_ROOT_8197F(x)                                       \
+	(((x) >> BIT_SHIFT_DTIM_COUNT_ROOT_8197F) &                            \
+	 BIT_MASK_DTIM_COUNT_ROOT_8197F)
+#define BIT_SET_DTIM_COUNT_ROOT_8197F(x, v)                                    \
+	(BIT_CLEAR_DTIM_COUNT_ROOT_8197F(x) | BIT_DTIM_COUNT_ROOT_8197F(v))
+
+/* 2 REG_DTIM_COUNTER_VAP1_8197F */
+
+#define BIT_SHIFT_DTIM_COUNT_VAP1_8197F 0
+#define BIT_MASK_DTIM_COUNT_VAP1_8197F 0xff
+#define BIT_DTIM_COUNT_VAP1_8197F(x)                                           \
+	(((x) & BIT_MASK_DTIM_COUNT_VAP1_8197F)                                \
+	 << BIT_SHIFT_DTIM_COUNT_VAP1_8197F)
+#define BITS_DTIM_COUNT_VAP1_8197F                                             \
+	(BIT_MASK_DTIM_COUNT_VAP1_8197F << BIT_SHIFT_DTIM_COUNT_VAP1_8197F)
+#define BIT_CLEAR_DTIM_COUNT_VAP1_8197F(x) ((x) & (~BITS_DTIM_COUNT_VAP1_8197F))
+#define BIT_GET_DTIM_COUNT_VAP1_8197F(x)                                       \
+	(((x) >> BIT_SHIFT_DTIM_COUNT_VAP1_8197F) &                            \
+	 BIT_MASK_DTIM_COUNT_VAP1_8197F)
+#define BIT_SET_DTIM_COUNT_VAP1_8197F(x, v)                                    \
+	(BIT_CLEAR_DTIM_COUNT_VAP1_8197F(x) | BIT_DTIM_COUNT_VAP1_8197F(v))
+
+/* 2 REG_DTIM_COUNTER_VAP2_8197F */
+
+#define BIT_SHIFT_DTIM_COUNT_VAP2_8197F 0
+#define BIT_MASK_DTIM_COUNT_VAP2_8197F 0xff
+#define BIT_DTIM_COUNT_VAP2_8197F(x)                                           \
+	(((x) & BIT_MASK_DTIM_COUNT_VAP2_8197F)                                \
+	 << BIT_SHIFT_DTIM_COUNT_VAP2_8197F)
+#define BITS_DTIM_COUNT_VAP2_8197F                                             \
+	(BIT_MASK_DTIM_COUNT_VAP2_8197F << BIT_SHIFT_DTIM_COUNT_VAP2_8197F)
+#define BIT_CLEAR_DTIM_COUNT_VAP2_8197F(x) ((x) & (~BITS_DTIM_COUNT_VAP2_8197F))
+#define BIT_GET_DTIM_COUNT_VAP2_8197F(x)                                       \
+	(((x) >> BIT_SHIFT_DTIM_COUNT_VAP2_8197F) &                            \
+	 BIT_MASK_DTIM_COUNT_VAP2_8197F)
+#define BIT_SET_DTIM_COUNT_VAP2_8197F(x, v)                                    \
+	(BIT_CLEAR_DTIM_COUNT_VAP2_8197F(x) | BIT_DTIM_COUNT_VAP2_8197F(v))
+
+/* 2 REG_DTIM_COUNTER_VAP3_8197F */
+
+#define BIT_SHIFT_DTIM_COUNT_VAP3_8197F 0
+#define BIT_MASK_DTIM_COUNT_VAP3_8197F 0xff
+#define BIT_DTIM_COUNT_VAP3_8197F(x)                                           \
+	(((x) & BIT_MASK_DTIM_COUNT_VAP3_8197F)                                \
+	 << BIT_SHIFT_DTIM_COUNT_VAP3_8197F)
+#define BITS_DTIM_COUNT_VAP3_8197F                                             \
+	(BIT_MASK_DTIM_COUNT_VAP3_8197F << BIT_SHIFT_DTIM_COUNT_VAP3_8197F)
+#define BIT_CLEAR_DTIM_COUNT_VAP3_8197F(x) ((x) & (~BITS_DTIM_COUNT_VAP3_8197F))
+#define BIT_GET_DTIM_COUNT_VAP3_8197F(x)                                       \
+	(((x) >> BIT_SHIFT_DTIM_COUNT_VAP3_8197F) &                            \
+	 BIT_MASK_DTIM_COUNT_VAP3_8197F)
+#define BIT_SET_DTIM_COUNT_VAP3_8197F(x, v)                                    \
+	(BIT_CLEAR_DTIM_COUNT_VAP3_8197F(x) | BIT_DTIM_COUNT_VAP3_8197F(v))
+
+/* 2 REG_DTIM_COUNTER_VAP4_8197F */
+
+#define BIT_SHIFT_DTIM_COUNT_VAP4_8197F 0
+#define BIT_MASK_DTIM_COUNT_VAP4_8197F 0xff
+#define BIT_DTIM_COUNT_VAP4_8197F(x)                                           \
+	(((x) & BIT_MASK_DTIM_COUNT_VAP4_8197F)                                \
+	 << BIT_SHIFT_DTIM_COUNT_VAP4_8197F)
+#define BITS_DTIM_COUNT_VAP4_8197F                                             \
+	(BIT_MASK_DTIM_COUNT_VAP4_8197F << BIT_SHIFT_DTIM_COUNT_VAP4_8197F)
+#define BIT_CLEAR_DTIM_COUNT_VAP4_8197F(x) ((x) & (~BITS_DTIM_COUNT_VAP4_8197F))
+#define BIT_GET_DTIM_COUNT_VAP4_8197F(x)                                       \
+	(((x) >> BIT_SHIFT_DTIM_COUNT_VAP4_8197F) &                            \
+	 BIT_MASK_DTIM_COUNT_VAP4_8197F)
+#define BIT_SET_DTIM_COUNT_VAP4_8197F(x, v)                                    \
+	(BIT_CLEAR_DTIM_COUNT_VAP4_8197F(x) | BIT_DTIM_COUNT_VAP4_8197F(v))
+
+/* 2 REG_DTIM_COUNTER_VAP5_8197F */
+
+#define BIT_SHIFT_DTIM_COUNT_VAP5_8197F 0
+#define BIT_MASK_DTIM_COUNT_VAP5_8197F 0xff
+#define BIT_DTIM_COUNT_VAP5_8197F(x)                                           \
+	(((x) & BIT_MASK_DTIM_COUNT_VAP5_8197F)                                \
+	 << BIT_SHIFT_DTIM_COUNT_VAP5_8197F)
+#define BITS_DTIM_COUNT_VAP5_8197F                                             \
+	(BIT_MASK_DTIM_COUNT_VAP5_8197F << BIT_SHIFT_DTIM_COUNT_VAP5_8197F)
+#define BIT_CLEAR_DTIM_COUNT_VAP5_8197F(x) ((x) & (~BITS_DTIM_COUNT_VAP5_8197F))
+#define BIT_GET_DTIM_COUNT_VAP5_8197F(x)                                       \
+	(((x) >> BIT_SHIFT_DTIM_COUNT_VAP5_8197F) &                            \
+	 BIT_MASK_DTIM_COUNT_VAP5_8197F)
+#define BIT_SET_DTIM_COUNT_VAP5_8197F(x, v)                                    \
+	(BIT_CLEAR_DTIM_COUNT_VAP5_8197F(x) | BIT_DTIM_COUNT_VAP5_8197F(v))
+
+/* 2 REG_DTIM_COUNTER_VAP6_8197F */
+
+#define BIT_SHIFT_DTIM_COUNT_VAP6_8197F 0
+#define BIT_MASK_DTIM_COUNT_VAP6_8197F 0xff
+#define BIT_DTIM_COUNT_VAP6_8197F(x)                                           \
+	(((x) & BIT_MASK_DTIM_COUNT_VAP6_8197F)                                \
+	 << BIT_SHIFT_DTIM_COUNT_VAP6_8197F)
+#define BITS_DTIM_COUNT_VAP6_8197F                                             \
+	(BIT_MASK_DTIM_COUNT_VAP6_8197F << BIT_SHIFT_DTIM_COUNT_VAP6_8197F)
+#define BIT_CLEAR_DTIM_COUNT_VAP6_8197F(x) ((x) & (~BITS_DTIM_COUNT_VAP6_8197F))
+#define BIT_GET_DTIM_COUNT_VAP6_8197F(x)                                       \
+	(((x) >> BIT_SHIFT_DTIM_COUNT_VAP6_8197F) &                            \
+	 BIT_MASK_DTIM_COUNT_VAP6_8197F)
+#define BIT_SET_DTIM_COUNT_VAP6_8197F(x, v)                                    \
+	(BIT_CLEAR_DTIM_COUNT_VAP6_8197F(x) | BIT_DTIM_COUNT_VAP6_8197F(v))
+
+/* 2 REG_DTIM_COUNTER_VAP7_8197F */
+
+#define BIT_SHIFT_DTIM_COUNT_VAP7_8197F 0
+#define BIT_MASK_DTIM_COUNT_VAP7_8197F 0xff
+#define BIT_DTIM_COUNT_VAP7_8197F(x)                                           \
+	(((x) & BIT_MASK_DTIM_COUNT_VAP7_8197F)                                \
+	 << BIT_SHIFT_DTIM_COUNT_VAP7_8197F)
+#define BITS_DTIM_COUNT_VAP7_8197F                                             \
+	(BIT_MASK_DTIM_COUNT_VAP7_8197F << BIT_SHIFT_DTIM_COUNT_VAP7_8197F)
+#define BIT_CLEAR_DTIM_COUNT_VAP7_8197F(x) ((x) & (~BITS_DTIM_COUNT_VAP7_8197F))
+#define BIT_GET_DTIM_COUNT_VAP7_8197F(x)                                       \
+	(((x) >> BIT_SHIFT_DTIM_COUNT_VAP7_8197F) &                            \
+	 BIT_MASK_DTIM_COUNT_VAP7_8197F)
+#define BIT_SET_DTIM_COUNT_VAP7_8197F(x, v)                                    \
+	(BIT_CLEAR_DTIM_COUNT_VAP7_8197F(x) | BIT_DTIM_COUNT_VAP7_8197F(v))
+
+/* 2 REG_DIS_ATIM_8197F */
+#define BIT_DIS_ATIM_VAP7_8197F BIT(7)
+#define BIT_DIS_ATIM_VAP6_8197F BIT(6)
+#define BIT_DIS_ATIM_VAP5_8197F BIT(5)
+#define BIT_DIS_ATIM_VAP4_8197F BIT(4)
+#define BIT_DIS_ATIM_VAP3_8197F BIT(3)
+#define BIT_DIS_ATIM_VAP2_8197F BIT(2)
+#define BIT_DIS_ATIM_VAP1_8197F BIT(1)
+#define BIT_DIS_ATIM_ROOT_8197F BIT(0)
+
+/* 2 REG_EARLY_128US_8197F */
+
+#define BIT_SHIFT_TSFT_SEL_TIMER1_8197F 3
+#define BIT_MASK_TSFT_SEL_TIMER1_8197F 0x7
+#define BIT_TSFT_SEL_TIMER1_8197F(x)                                           \
+	(((x) & BIT_MASK_TSFT_SEL_TIMER1_8197F)                                \
+	 << BIT_SHIFT_TSFT_SEL_TIMER1_8197F)
+#define BITS_TSFT_SEL_TIMER1_8197F                                             \
+	(BIT_MASK_TSFT_SEL_TIMER1_8197F << BIT_SHIFT_TSFT_SEL_TIMER1_8197F)
+#define BIT_CLEAR_TSFT_SEL_TIMER1_8197F(x) ((x) & (~BITS_TSFT_SEL_TIMER1_8197F))
+#define BIT_GET_TSFT_SEL_TIMER1_8197F(x)                                       \
+	(((x) >> BIT_SHIFT_TSFT_SEL_TIMER1_8197F) &                            \
+	 BIT_MASK_TSFT_SEL_TIMER1_8197F)
+#define BIT_SET_TSFT_SEL_TIMER1_8197F(x, v)                                    \
+	(BIT_CLEAR_TSFT_SEL_TIMER1_8197F(x) | BIT_TSFT_SEL_TIMER1_8197F(v))
+
+#define BIT_SHIFT_EARLY_128US_8197F 0
+#define BIT_MASK_EARLY_128US_8197F 0x7
+#define BIT_EARLY_128US_8197F(x)                                               \
+	(((x) & BIT_MASK_EARLY_128US_8197F) << BIT_SHIFT_EARLY_128US_8197F)
+#define BITS_EARLY_128US_8197F                                                 \
+	(BIT_MASK_EARLY_128US_8197F << BIT_SHIFT_EARLY_128US_8197F)
+#define BIT_CLEAR_EARLY_128US_8197F(x) ((x) & (~BITS_EARLY_128US_8197F))
+#define BIT_GET_EARLY_128US_8197F(x)                                           \
+	(((x) >> BIT_SHIFT_EARLY_128US_8197F) & BIT_MASK_EARLY_128US_8197F)
+#define BIT_SET_EARLY_128US_8197F(x, v)                                        \
+	(BIT_CLEAR_EARLY_128US_8197F(x) | BIT_EARLY_128US_8197F(v))
+
+/* 2 REG_P2PPS1_CTRL_8197F */
+#define BIT_P2P1_CTW_ALLSTASLEEP_8197F BIT(7)
+#define BIT_P2P1_OFF_DISTX_EN_8197F BIT(6)
+#define BIT_P2P1_PWR_MGT_EN_8197F BIT(5)
+#define BIT_P2P1_NOA1_EN_8197F BIT(2)
+#define BIT_P2P1_NOA0_EN_8197F BIT(1)
+
+/* 2 REG_P2PPS2_CTRL_8197F */
+#define BIT_P2P2_CTW_ALLSTASLEEP_8197F BIT(7)
+#define BIT_P2P2_OFF_DISTX_EN_8197F BIT(6)
+#define BIT_P2P2_PWR_MGT_EN_8197F BIT(5)
+#define BIT_P2P2_NOA1_EN_8197F BIT(2)
+#define BIT_P2P2_NOA0_EN_8197F BIT(1)
+
+/* 2 REG_TIMER0_SRC_SEL_8197F */
+
+#define BIT_SHIFT_SYNC_CLI_SEL_8197F 4
+#define BIT_MASK_SYNC_CLI_SEL_8197F 0x7
+#define BIT_SYNC_CLI_SEL_8197F(x)                                              \
+	(((x) & BIT_MASK_SYNC_CLI_SEL_8197F) << BIT_SHIFT_SYNC_CLI_SEL_8197F)
+#define BITS_SYNC_CLI_SEL_8197F                                                \
+	(BIT_MASK_SYNC_CLI_SEL_8197F << BIT_SHIFT_SYNC_CLI_SEL_8197F)
+#define BIT_CLEAR_SYNC_CLI_SEL_8197F(x) ((x) & (~BITS_SYNC_CLI_SEL_8197F))
+#define BIT_GET_SYNC_CLI_SEL_8197F(x)                                          \
+	(((x) >> BIT_SHIFT_SYNC_CLI_SEL_8197F) & BIT_MASK_SYNC_CLI_SEL_8197F)
+#define BIT_SET_SYNC_CLI_SEL_8197F(x, v)                                       \
+	(BIT_CLEAR_SYNC_CLI_SEL_8197F(x) | BIT_SYNC_CLI_SEL_8197F(v))
+
+#define BIT_SHIFT_TSFT_SEL_TIMER0_8197F 0
+#define BIT_MASK_TSFT_SEL_TIMER0_8197F 0x7
+#define BIT_TSFT_SEL_TIMER0_8197F(x)                                           \
+	(((x) & BIT_MASK_TSFT_SEL_TIMER0_8197F)                                \
+	 << BIT_SHIFT_TSFT_SEL_TIMER0_8197F)
+#define BITS_TSFT_SEL_TIMER0_8197F                                             \
+	(BIT_MASK_TSFT_SEL_TIMER0_8197F << BIT_SHIFT_TSFT_SEL_TIMER0_8197F)
+#define BIT_CLEAR_TSFT_SEL_TIMER0_8197F(x) ((x) & (~BITS_TSFT_SEL_TIMER0_8197F))
+#define BIT_GET_TSFT_SEL_TIMER0_8197F(x)                                       \
+	(((x) >> BIT_SHIFT_TSFT_SEL_TIMER0_8197F) &                            \
+	 BIT_MASK_TSFT_SEL_TIMER0_8197F)
+#define BIT_SET_TSFT_SEL_TIMER0_8197F(x, v)                                    \
+	(BIT_CLEAR_TSFT_SEL_TIMER0_8197F(x) | BIT_TSFT_SEL_TIMER0_8197F(v))
+
+/* 2 REG_NOA_UNIT_SEL_8197F */
+
+#define BIT_SHIFT_NOA_UNIT2_SEL_8197F 8
+#define BIT_MASK_NOA_UNIT2_SEL_8197F 0x7
+#define BIT_NOA_UNIT2_SEL_8197F(x)                                             \
+	(((x) & BIT_MASK_NOA_UNIT2_SEL_8197F) << BIT_SHIFT_NOA_UNIT2_SEL_8197F)
+#define BITS_NOA_UNIT2_SEL_8197F                                               \
+	(BIT_MASK_NOA_UNIT2_SEL_8197F << BIT_SHIFT_NOA_UNIT2_SEL_8197F)
+#define BIT_CLEAR_NOA_UNIT2_SEL_8197F(x) ((x) & (~BITS_NOA_UNIT2_SEL_8197F))
+#define BIT_GET_NOA_UNIT2_SEL_8197F(x)                                         \
+	(((x) >> BIT_SHIFT_NOA_UNIT2_SEL_8197F) & BIT_MASK_NOA_UNIT2_SEL_8197F)
+#define BIT_SET_NOA_UNIT2_SEL_8197F(x, v)                                      \
+	(BIT_CLEAR_NOA_UNIT2_SEL_8197F(x) | BIT_NOA_UNIT2_SEL_8197F(v))
+
+#define BIT_SHIFT_NOA_UNIT1_SEL_8197F 4
+#define BIT_MASK_NOA_UNIT1_SEL_8197F 0x7
+#define BIT_NOA_UNIT1_SEL_8197F(x)                                             \
+	(((x) & BIT_MASK_NOA_UNIT1_SEL_8197F) << BIT_SHIFT_NOA_UNIT1_SEL_8197F)
+#define BITS_NOA_UNIT1_SEL_8197F                                               \
+	(BIT_MASK_NOA_UNIT1_SEL_8197F << BIT_SHIFT_NOA_UNIT1_SEL_8197F)
+#define BIT_CLEAR_NOA_UNIT1_SEL_8197F(x) ((x) & (~BITS_NOA_UNIT1_SEL_8197F))
+#define BIT_GET_NOA_UNIT1_SEL_8197F(x)                                         \
+	(((x) >> BIT_SHIFT_NOA_UNIT1_SEL_8197F) & BIT_MASK_NOA_UNIT1_SEL_8197F)
+#define BIT_SET_NOA_UNIT1_SEL_8197F(x, v)                                      \
+	(BIT_CLEAR_NOA_UNIT1_SEL_8197F(x) | BIT_NOA_UNIT1_SEL_8197F(v))
+
+#define BIT_SHIFT_NOA_UNIT0_SEL_8197F 0
+#define BIT_MASK_NOA_UNIT0_SEL_8197F 0x7
+#define BIT_NOA_UNIT0_SEL_8197F(x)                                             \
+	(((x) & BIT_MASK_NOA_UNIT0_SEL_8197F) << BIT_SHIFT_NOA_UNIT0_SEL_8197F)
+#define BITS_NOA_UNIT0_SEL_8197F                                               \
+	(BIT_MASK_NOA_UNIT0_SEL_8197F << BIT_SHIFT_NOA_UNIT0_SEL_8197F)
+#define BIT_CLEAR_NOA_UNIT0_SEL_8197F(x) ((x) & (~BITS_NOA_UNIT0_SEL_8197F))
+#define BIT_GET_NOA_UNIT0_SEL_8197F(x)                                         \
+	(((x) >> BIT_SHIFT_NOA_UNIT0_SEL_8197F) & BIT_MASK_NOA_UNIT0_SEL_8197F)
+#define BIT_SET_NOA_UNIT0_SEL_8197F(x, v)                                      \
+	(BIT_CLEAR_NOA_UNIT0_SEL_8197F(x) | BIT_NOA_UNIT0_SEL_8197F(v))
+
+/* 2 REG_P2POFF_DIS_TXTIME_8197F */
+
+#define BIT_SHIFT_P2POFF_DIS_TXTIME_8197F 0
+#define BIT_MASK_P2POFF_DIS_TXTIME_8197F 0xff
+#define BIT_P2POFF_DIS_TXTIME_8197F(x)                                         \
+	(((x) & BIT_MASK_P2POFF_DIS_TXTIME_8197F)                              \
+	 << BIT_SHIFT_P2POFF_DIS_TXTIME_8197F)
+#define BITS_P2POFF_DIS_TXTIME_8197F                                           \
+	(BIT_MASK_P2POFF_DIS_TXTIME_8197F << BIT_SHIFT_P2POFF_DIS_TXTIME_8197F)
+#define BIT_CLEAR_P2POFF_DIS_TXTIME_8197F(x)                                   \
+	((x) & (~BITS_P2POFF_DIS_TXTIME_8197F))
+#define BIT_GET_P2POFF_DIS_TXTIME_8197F(x)                                     \
+	(((x) >> BIT_SHIFT_P2POFF_DIS_TXTIME_8197F) &                          \
+	 BIT_MASK_P2POFF_DIS_TXTIME_8197F)
+#define BIT_SET_P2POFF_DIS_TXTIME_8197F(x, v)                                  \
+	(BIT_CLEAR_P2POFF_DIS_TXTIME_8197F(x) | BIT_P2POFF_DIS_TXTIME_8197F(v))
+
+/* 2 REG_MBSSID_BCN_SPACE2_8197F */
+
+#define BIT_SHIFT_BCN_SPACE_CLINT2_8197F 16
+#define BIT_MASK_BCN_SPACE_CLINT2_8197F 0xfff
+#define BIT_BCN_SPACE_CLINT2_8197F(x)                                          \
+	(((x) & BIT_MASK_BCN_SPACE_CLINT2_8197F)                               \
+	 << BIT_SHIFT_BCN_SPACE_CLINT2_8197F)
+#define BITS_BCN_SPACE_CLINT2_8197F                                            \
+	(BIT_MASK_BCN_SPACE_CLINT2_8197F << BIT_SHIFT_BCN_SPACE_CLINT2_8197F)
+#define BIT_CLEAR_BCN_SPACE_CLINT2_8197F(x)                                    \
+	((x) & (~BITS_BCN_SPACE_CLINT2_8197F))
+#define BIT_GET_BCN_SPACE_CLINT2_8197F(x)                                      \
+	(((x) >> BIT_SHIFT_BCN_SPACE_CLINT2_8197F) &                           \
+	 BIT_MASK_BCN_SPACE_CLINT2_8197F)
+#define BIT_SET_BCN_SPACE_CLINT2_8197F(x, v)                                   \
+	(BIT_CLEAR_BCN_SPACE_CLINT2_8197F(x) | BIT_BCN_SPACE_CLINT2_8197F(v))
+
+#define BIT_SHIFT_BCN_SPACE_CLINT1_8197F 0
+#define BIT_MASK_BCN_SPACE_CLINT1_8197F 0xfff
+#define BIT_BCN_SPACE_CLINT1_8197F(x)                                          \
+	(((x) & BIT_MASK_BCN_SPACE_CLINT1_8197F)                               \
+	 << BIT_SHIFT_BCN_SPACE_CLINT1_8197F)
+#define BITS_BCN_SPACE_CLINT1_8197F                                            \
+	(BIT_MASK_BCN_SPACE_CLINT1_8197F << BIT_SHIFT_BCN_SPACE_CLINT1_8197F)
+#define BIT_CLEAR_BCN_SPACE_CLINT1_8197F(x)                                    \
+	((x) & (~BITS_BCN_SPACE_CLINT1_8197F))
+#define BIT_GET_BCN_SPACE_CLINT1_8197F(x)                                      \
+	(((x) >> BIT_SHIFT_BCN_SPACE_CLINT1_8197F) &                           \
+	 BIT_MASK_BCN_SPACE_CLINT1_8197F)
+#define BIT_SET_BCN_SPACE_CLINT1_8197F(x, v)                                   \
+	(BIT_CLEAR_BCN_SPACE_CLINT1_8197F(x) | BIT_BCN_SPACE_CLINT1_8197F(v))
+
+/* 2 REG_MBSSID_BCN_SPACE3_8197F */
+
+#define BIT_SHIFT_SUB_BCN_SPACE_8197F 16
+#define BIT_MASK_SUB_BCN_SPACE_8197F 0xff
+#define BIT_SUB_BCN_SPACE_8197F(x)                                             \
+	(((x) & BIT_MASK_SUB_BCN_SPACE_8197F) << BIT_SHIFT_SUB_BCN_SPACE_8197F)
+#define BITS_SUB_BCN_SPACE_8197F                                               \
+	(BIT_MASK_SUB_BCN_SPACE_8197F << BIT_SHIFT_SUB_BCN_SPACE_8197F)
+#define BIT_CLEAR_SUB_BCN_SPACE_8197F(x) ((x) & (~BITS_SUB_BCN_SPACE_8197F))
+#define BIT_GET_SUB_BCN_SPACE_8197F(x)                                         \
+	(((x) >> BIT_SHIFT_SUB_BCN_SPACE_8197F) & BIT_MASK_SUB_BCN_SPACE_8197F)
+#define BIT_SET_SUB_BCN_SPACE_8197F(x, v)                                      \
+	(BIT_CLEAR_SUB_BCN_SPACE_8197F(x) | BIT_SUB_BCN_SPACE_8197F(v))
+
+#define BIT_SHIFT_BCN_SPACE_CLINT3_8197F 0
+#define BIT_MASK_BCN_SPACE_CLINT3_8197F 0xfff
+#define BIT_BCN_SPACE_CLINT3_8197F(x)                                          \
+	(((x) & BIT_MASK_BCN_SPACE_CLINT3_8197F)                               \
+	 << BIT_SHIFT_BCN_SPACE_CLINT3_8197F)
+#define BITS_BCN_SPACE_CLINT3_8197F                                            \
+	(BIT_MASK_BCN_SPACE_CLINT3_8197F << BIT_SHIFT_BCN_SPACE_CLINT3_8197F)
+#define BIT_CLEAR_BCN_SPACE_CLINT3_8197F(x)                                    \
+	((x) & (~BITS_BCN_SPACE_CLINT3_8197F))
+#define BIT_GET_BCN_SPACE_CLINT3_8197F(x)                                      \
+	(((x) >> BIT_SHIFT_BCN_SPACE_CLINT3_8197F) &                           \
+	 BIT_MASK_BCN_SPACE_CLINT3_8197F)
+#define BIT_SET_BCN_SPACE_CLINT3_8197F(x, v)                                   \
+	(BIT_CLEAR_BCN_SPACE_CLINT3_8197F(x) | BIT_BCN_SPACE_CLINT3_8197F(v))
+
+/* 2 REG_ACMHWCTRL_8197F */
+#define BIT_BEQ_ACM_STATUS_8197F BIT(7)
+#define BIT_VIQ_ACM_STATUS_8197F BIT(6)
+#define BIT_VOQ_ACM_STATUS_8197F BIT(5)
+#define BIT_BEQ_ACM_EN_8197F BIT(3)
+#define BIT_VIQ_ACM_EN_8197F BIT(2)
+#define BIT_VOQ_ACM_EN_8197F BIT(1)
+#define BIT_ACMHWEN_8197F BIT(0)
+
+/* 2 REG_ACMRSTCTRL_8197F */
+#define BIT_BE_ACM_RESET_USED_TIME_8197F BIT(2)
+#define BIT_VI_ACM_RESET_USED_TIME_8197F BIT(1)
+#define BIT_VO_ACM_RESET_USED_TIME_8197F BIT(0)
+
+/* 2 REG_ACMAVG_8197F */
+
+#define BIT_SHIFT_AVGPERIOD_8197F 0
+#define BIT_MASK_AVGPERIOD_8197F 0xffff
+#define BIT_AVGPERIOD_8197F(x)                                                 \
+	(((x) & BIT_MASK_AVGPERIOD_8197F) << BIT_SHIFT_AVGPERIOD_8197F)
+#define BITS_AVGPERIOD_8197F                                                   \
+	(BIT_MASK_AVGPERIOD_8197F << BIT_SHIFT_AVGPERIOD_8197F)
+#define BIT_CLEAR_AVGPERIOD_8197F(x) ((x) & (~BITS_AVGPERIOD_8197F))
+#define BIT_GET_AVGPERIOD_8197F(x)                                             \
+	(((x) >> BIT_SHIFT_AVGPERIOD_8197F) & BIT_MASK_AVGPERIOD_8197F)
+#define BIT_SET_AVGPERIOD_8197F(x, v)                                          \
+	(BIT_CLEAR_AVGPERIOD_8197F(x) | BIT_AVGPERIOD_8197F(v))
+
+/* 2 REG_VO_ADMTIME_8197F */
+
+#define BIT_SHIFT_VO_ADMITTED_TIME_8197F 0
+#define BIT_MASK_VO_ADMITTED_TIME_8197F 0xffff
+#define BIT_VO_ADMITTED_TIME_8197F(x)                                          \
+	(((x) & BIT_MASK_VO_ADMITTED_TIME_8197F)                               \
+	 << BIT_SHIFT_VO_ADMITTED_TIME_8197F)
+#define BITS_VO_ADMITTED_TIME_8197F                                            \
+	(BIT_MASK_VO_ADMITTED_TIME_8197F << BIT_SHIFT_VO_ADMITTED_TIME_8197F)
+#define BIT_CLEAR_VO_ADMITTED_TIME_8197F(x)                                    \
+	((x) & (~BITS_VO_ADMITTED_TIME_8197F))
+#define BIT_GET_VO_ADMITTED_TIME_8197F(x)                                      \
+	(((x) >> BIT_SHIFT_VO_ADMITTED_TIME_8197F) &                           \
+	 BIT_MASK_VO_ADMITTED_TIME_8197F)
+#define BIT_SET_VO_ADMITTED_TIME_8197F(x, v)                                   \
+	(BIT_CLEAR_VO_ADMITTED_TIME_8197F(x) | BIT_VO_ADMITTED_TIME_8197F(v))
+
+/* 2 REG_VI_ADMTIME_8197F */
+
+#define BIT_SHIFT_VI_ADMITTED_TIME_8197F 0
+#define BIT_MASK_VI_ADMITTED_TIME_8197F 0xffff
+#define BIT_VI_ADMITTED_TIME_8197F(x)                                          \
+	(((x) & BIT_MASK_VI_ADMITTED_TIME_8197F)                               \
+	 << BIT_SHIFT_VI_ADMITTED_TIME_8197F)
+#define BITS_VI_ADMITTED_TIME_8197F                                            \
+	(BIT_MASK_VI_ADMITTED_TIME_8197F << BIT_SHIFT_VI_ADMITTED_TIME_8197F)
+#define BIT_CLEAR_VI_ADMITTED_TIME_8197F(x)                                    \
+	((x) & (~BITS_VI_ADMITTED_TIME_8197F))
+#define BIT_GET_VI_ADMITTED_TIME_8197F(x)                                      \
+	(((x) >> BIT_SHIFT_VI_ADMITTED_TIME_8197F) &                           \
+	 BIT_MASK_VI_ADMITTED_TIME_8197F)
+#define BIT_SET_VI_ADMITTED_TIME_8197F(x, v)                                   \
+	(BIT_CLEAR_VI_ADMITTED_TIME_8197F(x) | BIT_VI_ADMITTED_TIME_8197F(v))
+
+/* 2 REG_BE_ADMTIME_8197F */
+
+#define BIT_SHIFT_BE_ADMITTED_TIME_8197F 0
+#define BIT_MASK_BE_ADMITTED_TIME_8197F 0xffff
+#define BIT_BE_ADMITTED_TIME_8197F(x)                                          \
+	(((x) & BIT_MASK_BE_ADMITTED_TIME_8197F)                               \
+	 << BIT_SHIFT_BE_ADMITTED_TIME_8197F)
+#define BITS_BE_ADMITTED_TIME_8197F                                            \
+	(BIT_MASK_BE_ADMITTED_TIME_8197F << BIT_SHIFT_BE_ADMITTED_TIME_8197F)
+#define BIT_CLEAR_BE_ADMITTED_TIME_8197F(x)                                    \
+	((x) & (~BITS_BE_ADMITTED_TIME_8197F))
+#define BIT_GET_BE_ADMITTED_TIME_8197F(x)                                      \
+	(((x) >> BIT_SHIFT_BE_ADMITTED_TIME_8197F) &                           \
+	 BIT_MASK_BE_ADMITTED_TIME_8197F)
+#define BIT_SET_BE_ADMITTED_TIME_8197F(x, v)                                   \
+	(BIT_CLEAR_BE_ADMITTED_TIME_8197F(x) | BIT_BE_ADMITTED_TIME_8197F(v))
+
+/* 2 REG_NOT_VALID_8197F */
+#define BIT_CHANGE_POW_BCN_AREA_8197F BIT(9)
+
+/* 2 REG_EDCA_RANDOM_GEN_8197F */
+
+#define BIT_SHIFT_RANDOM_GEN_8197F 0
+#define BIT_MASK_RANDOM_GEN_8197F 0xffffff
+#define BIT_RANDOM_GEN_8197F(x)                                                \
+	(((x) & BIT_MASK_RANDOM_GEN_8197F) << BIT_SHIFT_RANDOM_GEN_8197F)
+#define BITS_RANDOM_GEN_8197F                                                  \
+	(BIT_MASK_RANDOM_GEN_8197F << BIT_SHIFT_RANDOM_GEN_8197F)
+#define BIT_CLEAR_RANDOM_GEN_8197F(x) ((x) & (~BITS_RANDOM_GEN_8197F))
+#define BIT_GET_RANDOM_GEN_8197F(x)                                            \
+	(((x) >> BIT_SHIFT_RANDOM_GEN_8197F) & BIT_MASK_RANDOM_GEN_8197F)
+#define BIT_SET_RANDOM_GEN_8197F(x, v)                                         \
+	(BIT_CLEAR_RANDOM_GEN_8197F(x) | BIT_RANDOM_GEN_8197F(v))
+
+/* 2 REG_TXCMD_NOA_SEL_8197F */
+
+#define BIT_SHIFT_NOA_SEL_V2_8197F 4
+#define BIT_MASK_NOA_SEL_V2_8197F 0x7
+#define BIT_NOA_SEL_V2_8197F(x)                                                \
+	(((x) & BIT_MASK_NOA_SEL_V2_8197F) << BIT_SHIFT_NOA_SEL_V2_8197F)
+#define BITS_NOA_SEL_V2_8197F                                                  \
+	(BIT_MASK_NOA_SEL_V2_8197F << BIT_SHIFT_NOA_SEL_V2_8197F)
+#define BIT_CLEAR_NOA_SEL_V2_8197F(x) ((x) & (~BITS_NOA_SEL_V2_8197F))
+#define BIT_GET_NOA_SEL_V2_8197F(x)                                            \
+	(((x) >> BIT_SHIFT_NOA_SEL_V2_8197F) & BIT_MASK_NOA_SEL_V2_8197F)
+#define BIT_SET_NOA_SEL_V2_8197F(x, v)                                         \
+	(BIT_CLEAR_NOA_SEL_V2_8197F(x) | BIT_NOA_SEL_V2_8197F(v))
+
+#define BIT_SHIFT_TXCMD_SEG_SEL_8197F 0
+#define BIT_MASK_TXCMD_SEG_SEL_8197F 0xf
+#define BIT_TXCMD_SEG_SEL_8197F(x)                                             \
+	(((x) & BIT_MASK_TXCMD_SEG_SEL_8197F) << BIT_SHIFT_TXCMD_SEG_SEL_8197F)
+#define BITS_TXCMD_SEG_SEL_8197F                                               \
+	(BIT_MASK_TXCMD_SEG_SEL_8197F << BIT_SHIFT_TXCMD_SEG_SEL_8197F)
+#define BIT_CLEAR_TXCMD_SEG_SEL_8197F(x) ((x) & (~BITS_TXCMD_SEG_SEL_8197F))
+#define BIT_GET_TXCMD_SEG_SEL_8197F(x)                                         \
+	(((x) >> BIT_SHIFT_TXCMD_SEG_SEL_8197F) & BIT_MASK_TXCMD_SEG_SEL_8197F)
+#define BIT_SET_TXCMD_SEG_SEL_8197F(x, v)                                      \
+	(BIT_CLEAR_TXCMD_SEG_SEL_8197F(x) | BIT_TXCMD_SEG_SEL_8197F(v))
+
+/* 2 REG_NOT_VALID_8197F */
+#define BIT_BCNERR_CNT_EN_8197F BIT(20)
+
+#define BIT_SHIFT_BCNERR_PORT_SEL_8197F 16
+#define BIT_MASK_BCNERR_PORT_SEL_8197F 0x7
+#define BIT_BCNERR_PORT_SEL_8197F(x)                                           \
+	(((x) & BIT_MASK_BCNERR_PORT_SEL_8197F)                                \
+	 << BIT_SHIFT_BCNERR_PORT_SEL_8197F)
+#define BITS_BCNERR_PORT_SEL_8197F                                             \
+	(BIT_MASK_BCNERR_PORT_SEL_8197F << BIT_SHIFT_BCNERR_PORT_SEL_8197F)
+#define BIT_CLEAR_BCNERR_PORT_SEL_8197F(x) ((x) & (~BITS_BCNERR_PORT_SEL_8197F))
+#define BIT_GET_BCNERR_PORT_SEL_8197F(x)                                       \
+	(((x) >> BIT_SHIFT_BCNERR_PORT_SEL_8197F) &                            \
+	 BIT_MASK_BCNERR_PORT_SEL_8197F)
+#define BIT_SET_BCNERR_PORT_SEL_8197F(x, v)                                    \
+	(BIT_CLEAR_BCNERR_PORT_SEL_8197F(x) | BIT_BCNERR_PORT_SEL_8197F(v))
+
+#define BIT_SHIFT_TXPAUSE1_8197F 8
+#define BIT_MASK_TXPAUSE1_8197F 0xff
+#define BIT_TXPAUSE1_8197F(x)                                                  \
+	(((x) & BIT_MASK_TXPAUSE1_8197F) << BIT_SHIFT_TXPAUSE1_8197F)
+#define BITS_TXPAUSE1_8197F                                                    \
+	(BIT_MASK_TXPAUSE1_8197F << BIT_SHIFT_TXPAUSE1_8197F)
+#define BIT_CLEAR_TXPAUSE1_8197F(x) ((x) & (~BITS_TXPAUSE1_8197F))
+#define BIT_GET_TXPAUSE1_8197F(x)                                              \
+	(((x) >> BIT_SHIFT_TXPAUSE1_8197F) & BIT_MASK_TXPAUSE1_8197F)
+#define BIT_SET_TXPAUSE1_8197F(x, v)                                           \
+	(BIT_CLEAR_TXPAUSE1_8197F(x) | BIT_TXPAUSE1_8197F(v))
+
+#define BIT_SHIFT_BW_CFG_8197F 0
+#define BIT_MASK_BW_CFG_8197F 0x3
+#define BIT_BW_CFG_8197F(x)                                                    \
+	(((x) & BIT_MASK_BW_CFG_8197F) << BIT_SHIFT_BW_CFG_8197F)
+#define BITS_BW_CFG_8197F (BIT_MASK_BW_CFG_8197F << BIT_SHIFT_BW_CFG_8197F)
+#define BIT_CLEAR_BW_CFG_8197F(x) ((x) & (~BITS_BW_CFG_8197F))
+#define BIT_GET_BW_CFG_8197F(x)                                                \
+	(((x) >> BIT_SHIFT_BW_CFG_8197F) & BIT_MASK_BW_CFG_8197F)
+#define BIT_SET_BW_CFG_8197F(x, v)                                             \
+	(BIT_CLEAR_BW_CFG_8197F(x) | BIT_BW_CFG_8197F(v))
+
+/* 2 REG_NOT_VALID_8197F */
+
+#define BIT_SHIFT_RXBCN_TIMER_8197F 16
+#define BIT_MASK_RXBCN_TIMER_8197F 0xffff
+#define BIT_RXBCN_TIMER_8197F(x)                                               \
+	(((x) & BIT_MASK_RXBCN_TIMER_8197F) << BIT_SHIFT_RXBCN_TIMER_8197F)
+#define BITS_RXBCN_TIMER_8197F                                                 \
+	(BIT_MASK_RXBCN_TIMER_8197F << BIT_SHIFT_RXBCN_TIMER_8197F)
+#define BIT_CLEAR_RXBCN_TIMER_8197F(x) ((x) & (~BITS_RXBCN_TIMER_8197F))
+#define BIT_GET_RXBCN_TIMER_8197F(x)                                           \
+	(((x) >> BIT_SHIFT_RXBCN_TIMER_8197F) & BIT_MASK_RXBCN_TIMER_8197F)
+#define BIT_SET_RXBCN_TIMER_8197F(x, v)                                        \
+	(BIT_CLEAR_RXBCN_TIMER_8197F(x) | BIT_RXBCN_TIMER_8197F(v))
+
+#define BIT_SHIFT_BCN_ELY_ADJ_8197F 0
+#define BIT_MASK_BCN_ELY_ADJ_8197F 0xffff
+#define BIT_BCN_ELY_ADJ_8197F(x)                                               \
+	(((x) & BIT_MASK_BCN_ELY_ADJ_8197F) << BIT_SHIFT_BCN_ELY_ADJ_8197F)
+#define BITS_BCN_ELY_ADJ_8197F                                                 \
+	(BIT_MASK_BCN_ELY_ADJ_8197F << BIT_SHIFT_BCN_ELY_ADJ_8197F)
+#define BIT_CLEAR_BCN_ELY_ADJ_8197F(x) ((x) & (~BITS_BCN_ELY_ADJ_8197F))
+#define BIT_GET_BCN_ELY_ADJ_8197F(x)                                           \
+	(((x) >> BIT_SHIFT_BCN_ELY_ADJ_8197F) & BIT_MASK_BCN_ELY_ADJ_8197F)
+#define BIT_SET_BCN_ELY_ADJ_8197F(x, v)                                        \
+	(BIT_CLEAR_BCN_ELY_ADJ_8197F(x) | BIT_BCN_ELY_ADJ_8197F(v))
+
+/* 2 REG_NOT_VALID_8197F */
+
+#define BIT_SHIFT_BCNERR_CNT_OTHERS_8197F 24
+#define BIT_MASK_BCNERR_CNT_OTHERS_8197F 0xff
+#define BIT_BCNERR_CNT_OTHERS_8197F(x)                                         \
+	(((x) & BIT_MASK_BCNERR_CNT_OTHERS_8197F)                              \
+	 << BIT_SHIFT_BCNERR_CNT_OTHERS_8197F)
+#define BITS_BCNERR_CNT_OTHERS_8197F                                           \
+	(BIT_MASK_BCNERR_CNT_OTHERS_8197F << BIT_SHIFT_BCNERR_CNT_OTHERS_8197F)
+#define BIT_CLEAR_BCNERR_CNT_OTHERS_8197F(x)                                   \
+	((x) & (~BITS_BCNERR_CNT_OTHERS_8197F))
+#define BIT_GET_BCNERR_CNT_OTHERS_8197F(x)                                     \
+	(((x) >> BIT_SHIFT_BCNERR_CNT_OTHERS_8197F) &                          \
+	 BIT_MASK_BCNERR_CNT_OTHERS_8197F)
+#define BIT_SET_BCNERR_CNT_OTHERS_8197F(x, v)                                  \
+	(BIT_CLEAR_BCNERR_CNT_OTHERS_8197F(x) | BIT_BCNERR_CNT_OTHERS_8197F(v))
+
+#define BIT_SHIFT_BCNERR_CNT_INVALID_8197F 16
+#define BIT_MASK_BCNERR_CNT_INVALID_8197F 0xff
+#define BIT_BCNERR_CNT_INVALID_8197F(x)                                        \
+	(((x) & BIT_MASK_BCNERR_CNT_INVALID_8197F)                             \
+	 << BIT_SHIFT_BCNERR_CNT_INVALID_8197F)
+#define BITS_BCNERR_CNT_INVALID_8197F                                          \
+	(BIT_MASK_BCNERR_CNT_INVALID_8197F                                     \
+	 << BIT_SHIFT_BCNERR_CNT_INVALID_8197F)
+#define BIT_CLEAR_BCNERR_CNT_INVALID_8197F(x)                                  \
+	((x) & (~BITS_BCNERR_CNT_INVALID_8197F))
+#define BIT_GET_BCNERR_CNT_INVALID_8197F(x)                                    \
+	(((x) >> BIT_SHIFT_BCNERR_CNT_INVALID_8197F) &                         \
+	 BIT_MASK_BCNERR_CNT_INVALID_8197F)
+#define BIT_SET_BCNERR_CNT_INVALID_8197F(x, v)                                 \
+	(BIT_CLEAR_BCNERR_CNT_INVALID_8197F(x) |                               \
+	 BIT_BCNERR_CNT_INVALID_8197F(v))
+
+#define BIT_SHIFT_BCNERR_CNT_MAC_8197F 8
+#define BIT_MASK_BCNERR_CNT_MAC_8197F 0xff
+#define BIT_BCNERR_CNT_MAC_8197F(x)                                            \
+	(((x) & BIT_MASK_BCNERR_CNT_MAC_8197F)                                 \
+	 << BIT_SHIFT_BCNERR_CNT_MAC_8197F)
+#define BITS_BCNERR_CNT_MAC_8197F                                              \
+	(BIT_MASK_BCNERR_CNT_MAC_8197F << BIT_SHIFT_BCNERR_CNT_MAC_8197F)
+#define BIT_CLEAR_BCNERR_CNT_MAC_8197F(x) ((x) & (~BITS_BCNERR_CNT_MAC_8197F))
+#define BIT_GET_BCNERR_CNT_MAC_8197F(x)                                        \
+	(((x) >> BIT_SHIFT_BCNERR_CNT_MAC_8197F) &                             \
+	 BIT_MASK_BCNERR_CNT_MAC_8197F)
+#define BIT_SET_BCNERR_CNT_MAC_8197F(x, v)                                     \
+	(BIT_CLEAR_BCNERR_CNT_MAC_8197F(x) | BIT_BCNERR_CNT_MAC_8197F(v))
+
+#define BIT_SHIFT_BCNERR_CNT_CCA_8197F 0
+#define BIT_MASK_BCNERR_CNT_CCA_8197F 0xff
+#define BIT_BCNERR_CNT_CCA_8197F(x)                                            \
+	(((x) & BIT_MASK_BCNERR_CNT_CCA_8197F)                                 \
+	 << BIT_SHIFT_BCNERR_CNT_CCA_8197F)
+#define BITS_BCNERR_CNT_CCA_8197F                                              \
+	(BIT_MASK_BCNERR_CNT_CCA_8197F << BIT_SHIFT_BCNERR_CNT_CCA_8197F)
+#define BIT_CLEAR_BCNERR_CNT_CCA_8197F(x) ((x) & (~BITS_BCNERR_CNT_CCA_8197F))
+#define BIT_GET_BCNERR_CNT_CCA_8197F(x)                                        \
+	(((x) >> BIT_SHIFT_BCNERR_CNT_CCA_8197F) &                             \
+	 BIT_MASK_BCNERR_CNT_CCA_8197F)
+#define BIT_SET_BCNERR_CNT_CCA_8197F(x, v)                                     \
+	(BIT_CLEAR_BCNERR_CNT_CCA_8197F(x) | BIT_BCNERR_CNT_CCA_8197F(v))
+
+/* 2 REG_NOA_PARAM_8197F */
+
+#define BIT_SHIFT_NOA_COUNT_8197F (96 & CPU_OPT_WIDTH)
+#define BIT_MASK_NOA_COUNT_8197F 0xff
+#define BIT_NOA_COUNT_8197F(x)                                                 \
+	(((x) & BIT_MASK_NOA_COUNT_8197F) << BIT_SHIFT_NOA_COUNT_8197F)
+#define BITS_NOA_COUNT_8197F                                                   \
+	(BIT_MASK_NOA_COUNT_8197F << BIT_SHIFT_NOA_COUNT_8197F)
+#define BIT_CLEAR_NOA_COUNT_8197F(x) ((x) & (~BITS_NOA_COUNT_8197F))
+#define BIT_GET_NOA_COUNT_8197F(x)                                             \
+	(((x) >> BIT_SHIFT_NOA_COUNT_8197F) & BIT_MASK_NOA_COUNT_8197F)
+#define BIT_SET_NOA_COUNT_8197F(x, v)                                          \
+	(BIT_CLEAR_NOA_COUNT_8197F(x) | BIT_NOA_COUNT_8197F(v))
+
+#define BIT_SHIFT_NOA_START_TIME_8197F (64 & CPU_OPT_WIDTH)
+#define BIT_MASK_NOA_START_TIME_8197F 0xffffffffL
+#define BIT_NOA_START_TIME_8197F(x)                                            \
+	(((x) & BIT_MASK_NOA_START_TIME_8197F)                                 \
+	 << BIT_SHIFT_NOA_START_TIME_8197F)
+#define BITS_NOA_START_TIME_8197F                                              \
+	(BIT_MASK_NOA_START_TIME_8197F << BIT_SHIFT_NOA_START_TIME_8197F)
+#define BIT_CLEAR_NOA_START_TIME_8197F(x) ((x) & (~BITS_NOA_START_TIME_8197F))
+#define BIT_GET_NOA_START_TIME_8197F(x)                                        \
+	(((x) >> BIT_SHIFT_NOA_START_TIME_8197F) &                             \
+	 BIT_MASK_NOA_START_TIME_8197F)
+#define BIT_SET_NOA_START_TIME_8197F(x, v)                                     \
+	(BIT_CLEAR_NOA_START_TIME_8197F(x) | BIT_NOA_START_TIME_8197F(v))
+
+#define BIT_SHIFT_NOA_INTERVAL_8197F (32 & CPU_OPT_WIDTH)
+#define BIT_MASK_NOA_INTERVAL_8197F 0xffffffffL
+#define BIT_NOA_INTERVAL_8197F(x)                                              \
+	(((x) & BIT_MASK_NOA_INTERVAL_8197F) << BIT_SHIFT_NOA_INTERVAL_8197F)
+#define BITS_NOA_INTERVAL_8197F                                                \
+	(BIT_MASK_NOA_INTERVAL_8197F << BIT_SHIFT_NOA_INTERVAL_8197F)
+#define BIT_CLEAR_NOA_INTERVAL_8197F(x) ((x) & (~BITS_NOA_INTERVAL_8197F))
+#define BIT_GET_NOA_INTERVAL_8197F(x)                                          \
+	(((x) >> BIT_SHIFT_NOA_INTERVAL_8197F) & BIT_MASK_NOA_INTERVAL_8197F)
+#define BIT_SET_NOA_INTERVAL_8197F(x, v)                                       \
+	(BIT_CLEAR_NOA_INTERVAL_8197F(x) | BIT_NOA_INTERVAL_8197F(v))
+
+#define BIT_SHIFT_NOA_DURATION_8197F 0
+#define BIT_MASK_NOA_DURATION_8197F 0xffffffffL
+#define BIT_NOA_DURATION_8197F(x)                                              \
+	(((x) & BIT_MASK_NOA_DURATION_8197F) << BIT_SHIFT_NOA_DURATION_8197F)
+#define BITS_NOA_DURATION_8197F                                                \
+	(BIT_MASK_NOA_DURATION_8197F << BIT_SHIFT_NOA_DURATION_8197F)
+#define BIT_CLEAR_NOA_DURATION_8197F(x) ((x) & (~BITS_NOA_DURATION_8197F))
+#define BIT_GET_NOA_DURATION_8197F(x)                                          \
+	(((x) >> BIT_SHIFT_NOA_DURATION_8197F) & BIT_MASK_NOA_DURATION_8197F)
+#define BIT_SET_NOA_DURATION_8197F(x, v)                                       \
+	(BIT_CLEAR_NOA_DURATION_8197F(x) | BIT_NOA_DURATION_8197F(v))
+
+/* 2 REG_NOT_VALID_8197F */
+
+/* 2 REG_P2P_RST_8197F */
+#define BIT_P2P2_PWR_RST1_8197F BIT(5)
+#define BIT_P2P2_PWR_RST0_8197F BIT(4)
+#define BIT_P2P1_PWR_RST1_8197F BIT(3)
+#define BIT_P2P1_PWR_RST0_8197F BIT(2)
+#define BIT_P2P_PWR_RST1_V1_8197F BIT(1)
+#define BIT_P2P_PWR_RST0_V1_8197F BIT(0)
+
+/* 2 REG_SCHEDULER_RST_8197F */
+#define BIT_SYNC_TSF_NOW_8197F BIT(2)
+#define BIT_SYNC_CLI_8197F BIT(1)
+#define BIT_SCHEDULER_RST_V1_8197F BIT(0)
+
+/* 2 REG_SCH_TXCMD_8197F */
+
+#define BIT_SHIFT_SCH_TXCMD_8197F 0
+#define BIT_MASK_SCH_TXCMD_8197F 0xffffffffL
+#define BIT_SCH_TXCMD_8197F(x)                                                 \
+	(((x) & BIT_MASK_SCH_TXCMD_8197F) << BIT_SHIFT_SCH_TXCMD_8197F)
+#define BITS_SCH_TXCMD_8197F                                                   \
+	(BIT_MASK_SCH_TXCMD_8197F << BIT_SHIFT_SCH_TXCMD_8197F)
+#define BIT_CLEAR_SCH_TXCMD_8197F(x) ((x) & (~BITS_SCH_TXCMD_8197F))
+#define BIT_GET_SCH_TXCMD_8197F(x)                                             \
+	(((x) >> BIT_SHIFT_SCH_TXCMD_8197F) & BIT_MASK_SCH_TXCMD_8197F)
+#define BIT_SET_SCH_TXCMD_8197F(x, v)                                          \
+	(BIT_CLEAR_SCH_TXCMD_8197F(x) | BIT_SCH_TXCMD_8197F(v))
+
+/* 2 REG_PAGE5_DUMMY_8197F */
+
+/* 2 REG_CPUMGQ_TX_TIMER_8197F */
+
+#define BIT_SHIFT_CPUMGQ_TX_TIMER_V1_8197F 0
+#define BIT_MASK_CPUMGQ_TX_TIMER_V1_8197F 0xffffffffL
+#define BIT_CPUMGQ_TX_TIMER_V1_8197F(x)                                        \
+	(((x) & BIT_MASK_CPUMGQ_TX_TIMER_V1_8197F)                             \
+	 << BIT_SHIFT_CPUMGQ_TX_TIMER_V1_8197F)
+#define BITS_CPUMGQ_TX_TIMER_V1_8197F                                          \
+	(BIT_MASK_CPUMGQ_TX_TIMER_V1_8197F                                     \
+	 << BIT_SHIFT_CPUMGQ_TX_TIMER_V1_8197F)
+#define BIT_CLEAR_CPUMGQ_TX_TIMER_V1_8197F(x)                                  \
+	((x) & (~BITS_CPUMGQ_TX_TIMER_V1_8197F))
+#define BIT_GET_CPUMGQ_TX_TIMER_V1_8197F(x)                                    \
+	(((x) >> BIT_SHIFT_CPUMGQ_TX_TIMER_V1_8197F) &                         \
+	 BIT_MASK_CPUMGQ_TX_TIMER_V1_8197F)
+#define BIT_SET_CPUMGQ_TX_TIMER_V1_8197F(x, v)                                 \
+	(BIT_CLEAR_CPUMGQ_TX_TIMER_V1_8197F(x) |                               \
+	 BIT_CPUMGQ_TX_TIMER_V1_8197F(v))
+
+/* 2 REG_PS_TIMER_A_8197F */
+
+#define BIT_SHIFT_PS_TIMER_A_V1_8197F 0
+#define BIT_MASK_PS_TIMER_A_V1_8197F 0xffffffffL
+#define BIT_PS_TIMER_A_V1_8197F(x)                                             \
+	(((x) & BIT_MASK_PS_TIMER_A_V1_8197F) << BIT_SHIFT_PS_TIMER_A_V1_8197F)
+#define BITS_PS_TIMER_A_V1_8197F                                               \
+	(BIT_MASK_PS_TIMER_A_V1_8197F << BIT_SHIFT_PS_TIMER_A_V1_8197F)
+#define BIT_CLEAR_PS_TIMER_A_V1_8197F(x) ((x) & (~BITS_PS_TIMER_A_V1_8197F))
+#define BIT_GET_PS_TIMER_A_V1_8197F(x)                                         \
+	(((x) >> BIT_SHIFT_PS_TIMER_A_V1_8197F) & BIT_MASK_PS_TIMER_A_V1_8197F)
+#define BIT_SET_PS_TIMER_A_V1_8197F(x, v)                                      \
+	(BIT_CLEAR_PS_TIMER_A_V1_8197F(x) | BIT_PS_TIMER_A_V1_8197F(v))
+
+/* 2 REG_PS_TIMER_B_8197F */
+
+#define BIT_SHIFT_PS_TIMER_B_V1_8197F 0
+#define BIT_MASK_PS_TIMER_B_V1_8197F 0xffffffffL
+#define BIT_PS_TIMER_B_V1_8197F(x)                                             \
+	(((x) & BIT_MASK_PS_TIMER_B_V1_8197F) << BIT_SHIFT_PS_TIMER_B_V1_8197F)
+#define BITS_PS_TIMER_B_V1_8197F                                               \
+	(BIT_MASK_PS_TIMER_B_V1_8197F << BIT_SHIFT_PS_TIMER_B_V1_8197F)
+#define BIT_CLEAR_PS_TIMER_B_V1_8197F(x) ((x) & (~BITS_PS_TIMER_B_V1_8197F))
+#define BIT_GET_PS_TIMER_B_V1_8197F(x)                                         \
+	(((x) >> BIT_SHIFT_PS_TIMER_B_V1_8197F) & BIT_MASK_PS_TIMER_B_V1_8197F)
+#define BIT_SET_PS_TIMER_B_V1_8197F(x, v)                                      \
+	(BIT_CLEAR_PS_TIMER_B_V1_8197F(x) | BIT_PS_TIMER_B_V1_8197F(v))
+
+/* 2 REG_PS_TIMER_C_8197F */
+
+#define BIT_SHIFT_PS_TIMER_C_V1_8197F 0
+#define BIT_MASK_PS_TIMER_C_V1_8197F 0xffffffffL
+#define BIT_PS_TIMER_C_V1_8197F(x)                                             \
+	(((x) & BIT_MASK_PS_TIMER_C_V1_8197F) << BIT_SHIFT_PS_TIMER_C_V1_8197F)
+#define BITS_PS_TIMER_C_V1_8197F                                               \
+	(BIT_MASK_PS_TIMER_C_V1_8197F << BIT_SHIFT_PS_TIMER_C_V1_8197F)
+#define BIT_CLEAR_PS_TIMER_C_V1_8197F(x) ((x) & (~BITS_PS_TIMER_C_V1_8197F))
+#define BIT_GET_PS_TIMER_C_V1_8197F(x)                                         \
+	(((x) >> BIT_SHIFT_PS_TIMER_C_V1_8197F) & BIT_MASK_PS_TIMER_C_V1_8197F)
+#define BIT_SET_PS_TIMER_C_V1_8197F(x, v)                                      \
+	(BIT_CLEAR_PS_TIMER_C_V1_8197F(x) | BIT_PS_TIMER_C_V1_8197F(v))
+
+/* 2 REG_PS_TIMER_ABC_CPUMGQ_TIMER_CRTL_8197F */
+#define BIT_CPUMGQ_TIMER_EN_8197F BIT(31)
+#define BIT_CPUMGQ_TX_EN_8197F BIT(28)
+
+#define BIT_SHIFT_CPUMGQ_TIMER_TSF_SEL_8197F 24
+#define BIT_MASK_CPUMGQ_TIMER_TSF_SEL_8197F 0x7
+#define BIT_CPUMGQ_TIMER_TSF_SEL_8197F(x)                                      \
+	(((x) & BIT_MASK_CPUMGQ_TIMER_TSF_SEL_8197F)                           \
+	 << BIT_SHIFT_CPUMGQ_TIMER_TSF_SEL_8197F)
+#define BITS_CPUMGQ_TIMER_TSF_SEL_8197F                                        \
+	(BIT_MASK_CPUMGQ_TIMER_TSF_SEL_8197F                                   \
+	 << BIT_SHIFT_CPUMGQ_TIMER_TSF_SEL_8197F)
+#define BIT_CLEAR_CPUMGQ_TIMER_TSF_SEL_8197F(x)                                \
+	((x) & (~BITS_CPUMGQ_TIMER_TSF_SEL_8197F))
+#define BIT_GET_CPUMGQ_TIMER_TSF_SEL_8197F(x)                                  \
+	(((x) >> BIT_SHIFT_CPUMGQ_TIMER_TSF_SEL_8197F) &                       \
+	 BIT_MASK_CPUMGQ_TIMER_TSF_SEL_8197F)
+#define BIT_SET_CPUMGQ_TIMER_TSF_SEL_8197F(x, v)                               \
+	(BIT_CLEAR_CPUMGQ_TIMER_TSF_SEL_8197F(x) |                             \
+	 BIT_CPUMGQ_TIMER_TSF_SEL_8197F(v))
+
+#define BIT_PS_TIMER_C_EN_8197F BIT(23)
+
+#define BIT_SHIFT_PS_TIMER_C_TSF_SEL_8197F 16
+#define BIT_MASK_PS_TIMER_C_TSF_SEL_8197F 0x7
+#define BIT_PS_TIMER_C_TSF_SEL_8197F(x)                                        \
+	(((x) & BIT_MASK_PS_TIMER_C_TSF_SEL_8197F)                             \
+	 << BIT_SHIFT_PS_TIMER_C_TSF_SEL_8197F)
+#define BITS_PS_TIMER_C_TSF_SEL_8197F                                          \
+	(BIT_MASK_PS_TIMER_C_TSF_SEL_8197F                                     \
+	 << BIT_SHIFT_PS_TIMER_C_TSF_SEL_8197F)
+#define BIT_CLEAR_PS_TIMER_C_TSF_SEL_8197F(x)                                  \
+	((x) & (~BITS_PS_TIMER_C_TSF_SEL_8197F))
+#define BIT_GET_PS_TIMER_C_TSF_SEL_8197F(x)                                    \
+	(((x) >> BIT_SHIFT_PS_TIMER_C_TSF_SEL_8197F) &                         \
+	 BIT_MASK_PS_TIMER_C_TSF_SEL_8197F)
+#define BIT_SET_PS_TIMER_C_TSF_SEL_8197F(x, v)                                 \
+	(BIT_CLEAR_PS_TIMER_C_TSF_SEL_8197F(x) |                               \
+	 BIT_PS_TIMER_C_TSF_SEL_8197F(v))
+
+#define BIT_PS_TIMER_B_EN_8197F BIT(15)
+
+#define BIT_SHIFT_PS_TIMER_B_TSF_SEL_8197F 8
+#define BIT_MASK_PS_TIMER_B_TSF_SEL_8197F 0x7
+#define BIT_PS_TIMER_B_TSF_SEL_8197F(x)                                        \
+	(((x) & BIT_MASK_PS_TIMER_B_TSF_SEL_8197F)                             \
+	 << BIT_SHIFT_PS_TIMER_B_TSF_SEL_8197F)
+#define BITS_PS_TIMER_B_TSF_SEL_8197F                                          \
+	(BIT_MASK_PS_TIMER_B_TSF_SEL_8197F                                     \
+	 << BIT_SHIFT_PS_TIMER_B_TSF_SEL_8197F)
+#define BIT_CLEAR_PS_TIMER_B_TSF_SEL_8197F(x)                                  \
+	((x) & (~BITS_PS_TIMER_B_TSF_SEL_8197F))
+#define BIT_GET_PS_TIMER_B_TSF_SEL_8197F(x)                                    \
+	(((x) >> BIT_SHIFT_PS_TIMER_B_TSF_SEL_8197F) &                         \
+	 BIT_MASK_PS_TIMER_B_TSF_SEL_8197F)
+#define BIT_SET_PS_TIMER_B_TSF_SEL_8197F(x, v)                                 \
+	(BIT_CLEAR_PS_TIMER_B_TSF_SEL_8197F(x) |                               \
+	 BIT_PS_TIMER_B_TSF_SEL_8197F(v))
+
+#define BIT_PS_TIMER_A_EN_8197F BIT(7)
+
+#define BIT_SHIFT_PS_TIMER_A_TSF_SEL_8197F 0
+#define BIT_MASK_PS_TIMER_A_TSF_SEL_8197F 0x7
+#define BIT_PS_TIMER_A_TSF_SEL_8197F(x)                                        \
+	(((x) & BIT_MASK_PS_TIMER_A_TSF_SEL_8197F)                             \
+	 << BIT_SHIFT_PS_TIMER_A_TSF_SEL_8197F)
+#define BITS_PS_TIMER_A_TSF_SEL_8197F                                          \
+	(BIT_MASK_PS_TIMER_A_TSF_SEL_8197F                                     \
+	 << BIT_SHIFT_PS_TIMER_A_TSF_SEL_8197F)
+#define BIT_CLEAR_PS_TIMER_A_TSF_SEL_8197F(x)                                  \
+	((x) & (~BITS_PS_TIMER_A_TSF_SEL_8197F))
+#define BIT_GET_PS_TIMER_A_TSF_SEL_8197F(x)                                    \
+	(((x) >> BIT_SHIFT_PS_TIMER_A_TSF_SEL_8197F) &                         \
+	 BIT_MASK_PS_TIMER_A_TSF_SEL_8197F)
+#define BIT_SET_PS_TIMER_A_TSF_SEL_8197F(x, v)                                 \
+	(BIT_CLEAR_PS_TIMER_A_TSF_SEL_8197F(x) |                               \
+	 BIT_PS_TIMER_A_TSF_SEL_8197F(v))
+
+/* 2 REG_CPUMGQ_TX_TIMER_EARLY_8197F */
+
+#define BIT_SHIFT_CPUMGQ_TX_TIMER_EARLY_8197F 0
+#define BIT_MASK_CPUMGQ_TX_TIMER_EARLY_8197F 0xff
+#define BIT_CPUMGQ_TX_TIMER_EARLY_8197F(x)                                     \
+	(((x) & BIT_MASK_CPUMGQ_TX_TIMER_EARLY_8197F)                          \
+	 << BIT_SHIFT_CPUMGQ_TX_TIMER_EARLY_8197F)
+#define BITS_CPUMGQ_TX_TIMER_EARLY_8197F                                       \
+	(BIT_MASK_CPUMGQ_TX_TIMER_EARLY_8197F                                  \
+	 << BIT_SHIFT_CPUMGQ_TX_TIMER_EARLY_8197F)
+#define BIT_CLEAR_CPUMGQ_TX_TIMER_EARLY_8197F(x)                               \
+	((x) & (~BITS_CPUMGQ_TX_TIMER_EARLY_8197F))
+#define BIT_GET_CPUMGQ_TX_TIMER_EARLY_8197F(x)                                 \
+	(((x) >> BIT_SHIFT_CPUMGQ_TX_TIMER_EARLY_8197F) &                      \
+	 BIT_MASK_CPUMGQ_TX_TIMER_EARLY_8197F)
+#define BIT_SET_CPUMGQ_TX_TIMER_EARLY_8197F(x, v)                              \
+	(BIT_CLEAR_CPUMGQ_TX_TIMER_EARLY_8197F(x) |                            \
+	 BIT_CPUMGQ_TX_TIMER_EARLY_8197F(v))
+
+/* 2 REG_PS_TIMER_A_EARLY_8197F */
+
+#define BIT_SHIFT_PS_TIMER_A_EARLY_8197F 0
+#define BIT_MASK_PS_TIMER_A_EARLY_8197F 0xff
+#define BIT_PS_TIMER_A_EARLY_8197F(x)                                          \
+	(((x) & BIT_MASK_PS_TIMER_A_EARLY_8197F)                               \
+	 << BIT_SHIFT_PS_TIMER_A_EARLY_8197F)
+#define BITS_PS_TIMER_A_EARLY_8197F                                            \
+	(BIT_MASK_PS_TIMER_A_EARLY_8197F << BIT_SHIFT_PS_TIMER_A_EARLY_8197F)
+#define BIT_CLEAR_PS_TIMER_A_EARLY_8197F(x)                                    \
+	((x) & (~BITS_PS_TIMER_A_EARLY_8197F))
+#define BIT_GET_PS_TIMER_A_EARLY_8197F(x)                                      \
+	(((x) >> BIT_SHIFT_PS_TIMER_A_EARLY_8197F) &                           \
+	 BIT_MASK_PS_TIMER_A_EARLY_8197F)
+#define BIT_SET_PS_TIMER_A_EARLY_8197F(x, v)                                   \
+	(BIT_CLEAR_PS_TIMER_A_EARLY_8197F(x) | BIT_PS_TIMER_A_EARLY_8197F(v))
+
+/* 2 REG_PS_TIMER_B_EARLY_8197F */
+
+#define BIT_SHIFT_PS_TIMER_B_EARLY_8197F 0
+#define BIT_MASK_PS_TIMER_B_EARLY_8197F 0xff
+#define BIT_PS_TIMER_B_EARLY_8197F(x)                                          \
+	(((x) & BIT_MASK_PS_TIMER_B_EARLY_8197F)                               \
+	 << BIT_SHIFT_PS_TIMER_B_EARLY_8197F)
+#define BITS_PS_TIMER_B_EARLY_8197F                                            \
+	(BIT_MASK_PS_TIMER_B_EARLY_8197F << BIT_SHIFT_PS_TIMER_B_EARLY_8197F)
+#define BIT_CLEAR_PS_TIMER_B_EARLY_8197F(x)                                    \
+	((x) & (~BITS_PS_TIMER_B_EARLY_8197F))
+#define BIT_GET_PS_TIMER_B_EARLY_8197F(x)                                      \
+	(((x) >> BIT_SHIFT_PS_TIMER_B_EARLY_8197F) &                           \
+	 BIT_MASK_PS_TIMER_B_EARLY_8197F)
+#define BIT_SET_PS_TIMER_B_EARLY_8197F(x, v)                                   \
+	(BIT_CLEAR_PS_TIMER_B_EARLY_8197F(x) | BIT_PS_TIMER_B_EARLY_8197F(v))
+
+/* 2 REG_PS_TIMER_C_EARLY_8197F */
+
+#define BIT_SHIFT_PS_TIMER_C_EARLY_8197F 0
+#define BIT_MASK_PS_TIMER_C_EARLY_8197F 0xff
+#define BIT_PS_TIMER_C_EARLY_8197F(x)                                          \
+	(((x) & BIT_MASK_PS_TIMER_C_EARLY_8197F)                               \
+	 << BIT_SHIFT_PS_TIMER_C_EARLY_8197F)
+#define BITS_PS_TIMER_C_EARLY_8197F                                            \
+	(BIT_MASK_PS_TIMER_C_EARLY_8197F << BIT_SHIFT_PS_TIMER_C_EARLY_8197F)
+#define BIT_CLEAR_PS_TIMER_C_EARLY_8197F(x)                                    \
+	((x) & (~BITS_PS_TIMER_C_EARLY_8197F))
+#define BIT_GET_PS_TIMER_C_EARLY_8197F(x)                                      \
+	(((x) >> BIT_SHIFT_PS_TIMER_C_EARLY_8197F) &                           \
+	 BIT_MASK_PS_TIMER_C_EARLY_8197F)
+#define BIT_SET_PS_TIMER_C_EARLY_8197F(x, v)                                   \
+	(BIT_CLEAR_PS_TIMER_C_EARLY_8197F(x) | BIT_PS_TIMER_C_EARLY_8197F(v))
+
+/* 2 REG_NOT_VALID_8197F */
+#define BIT_STOP_CPUMGQ_8197F BIT(16)
+
+#define BIT_SHIFT_CPUMGQ_PARAMETER_8197F 0
+#define BIT_MASK_CPUMGQ_PARAMETER_8197F 0xffff
+#define BIT_CPUMGQ_PARAMETER_8197F(x)                                          \
+	(((x) & BIT_MASK_CPUMGQ_PARAMETER_8197F)                               \
+	 << BIT_SHIFT_CPUMGQ_PARAMETER_8197F)
+#define BITS_CPUMGQ_PARAMETER_8197F                                            \
+	(BIT_MASK_CPUMGQ_PARAMETER_8197F << BIT_SHIFT_CPUMGQ_PARAMETER_8197F)
+#define BIT_CLEAR_CPUMGQ_PARAMETER_8197F(x)                                    \
+	((x) & (~BITS_CPUMGQ_PARAMETER_8197F))
+#define BIT_GET_CPUMGQ_PARAMETER_8197F(x)                                      \
+	(((x) >> BIT_SHIFT_CPUMGQ_PARAMETER_8197F) &                           \
+	 BIT_MASK_CPUMGQ_PARAMETER_8197F)
+#define BIT_SET_CPUMGQ_PARAMETER_8197F(x, v)                                   \
+	(BIT_CLEAR_CPUMGQ_PARAMETER_8197F(x) | BIT_CPUMGQ_PARAMETER_8197F(v))
+
+/* 2 REG_NOT_VALID_8197F */
+
+/* 2 REG_BWOPMODE_8197F (BW OPERATION MODE REGISTER) */
+
+/* 2 REG_WMAC_FWPKT_CR_8197F */
+#define BIT_FWEN_8197F BIT(7)
+#define BIT_PHYSTS_PKT_CTRL_8197F BIT(6)
+#define BIT_APPHDR_MIDSRCH_FAIL_8197F BIT(4)
+#define BIT_FWPARSING_EN_8197F BIT(3)
+
+#define BIT_SHIFT_APPEND_MHDR_LEN_8197F 0
+#define BIT_MASK_APPEND_MHDR_LEN_8197F 0x7
+#define BIT_APPEND_MHDR_LEN_8197F(x)                                           \
+	(((x) & BIT_MASK_APPEND_MHDR_LEN_8197F)                                \
+	 << BIT_SHIFT_APPEND_MHDR_LEN_8197F)
+#define BITS_APPEND_MHDR_LEN_8197F                                             \
+	(BIT_MASK_APPEND_MHDR_LEN_8197F << BIT_SHIFT_APPEND_MHDR_LEN_8197F)
+#define BIT_CLEAR_APPEND_MHDR_LEN_8197F(x) ((x) & (~BITS_APPEND_MHDR_LEN_8197F))
+#define BIT_GET_APPEND_MHDR_LEN_8197F(x)                                       \
+	(((x) >> BIT_SHIFT_APPEND_MHDR_LEN_8197F) &                            \
+	 BIT_MASK_APPEND_MHDR_LEN_8197F)
+#define BIT_SET_APPEND_MHDR_LEN_8197F(x, v)                                    \
+	(BIT_CLEAR_APPEND_MHDR_LEN_8197F(x) | BIT_APPEND_MHDR_LEN_8197F(v))
+
+/* 2 REG_WMAC_CR_8197F (WMAC CR AND APSD CONTROL REGISTER) */
+#define BIT_APSDOFF_8197F BIT(6)
+#define BIT_IC_MACPHY_M_8197F BIT(0)
+
+/* 2 REG_TCR_8197F (TRANSMISSION CONFIGURATION REGISTER) */
+#define BIT_WMAC_EN_RTS_ADDR_8197F BIT(31)
+#define BIT_WMAC_DISABLE_CCK_8197F BIT(30)
+#define BIT_WMAC_RAW_LEN_8197F BIT(29)
+#define BIT_WMAC_NOTX_IN_RXNDP_8197F BIT(28)
+#define BIT_WMAC_EN_EOF_8197F BIT(27)
+#define BIT_WMAC_BF_SEL_8197F BIT(26)
+#define BIT_WMAC_ANTMODE_SEL_8197F BIT(25)
+#define BIT_WMAC_TCRPWRMGT_HWCTL_8197F BIT(24)
+#define BIT_WMAC_SMOOTH_VAL_8197F BIT(23)
+#define BIT_UNDERFLOWEN_CMPLEN_SEL_8197F BIT(21)
+#define BIT_FETCH_MPDU_AFTER_WSEC_RDY_8197F BIT(20)
+#define BIT_WMAC_TCR_EN_20MST_8197F BIT(19)
+#define BIT_WMAC_DIS_SIGTA_8197F BIT(18)
+#define BIT_WMAC_DIS_A2B0_8197F BIT(17)
+#define BIT_WMAC_MSK_SIGBCRC_8197F BIT(16)
+#define BIT_WMAC_TCR_ERRSTEN_3_8197F BIT(15)
+#define BIT_WMAC_TCR_ERRSTEN_2_8197F BIT(14)
+#define BIT_WMAC_TCR_ERRSTEN_1_8197F BIT(13)
+#define BIT_WMAC_TCR_ERRSTEN_0_8197F BIT(12)
+#define BIT_WMAC_TCR_TXSK_PERPKT_8197F BIT(11)
+#define BIT_ICV_8197F BIT(10)
+#define BIT_CFEND_FORMAT_8197F BIT(9)
+#define BIT_CRC_8197F BIT(8)
+#define BIT_PWRBIT_OW_EN_8197F BIT(7)
+#define BIT_PWR_ST_8197F BIT(6)
+#define BIT_WMAC_TCR_UPD_TIMIE_8197F BIT(5)
+#define BIT_WMAC_TCR_UPD_HGQMD_8197F BIT(4)
+#define BIT_VHTSIGA1_TXPS_8197F BIT(3)
+#define BIT_PAD_SEL_8197F BIT(2)
+#define BIT_DIS_GCLK_8197F BIT(1)
+
+/* 2 REG_RCR_8197F (RECEIVE CONFIGURATION REGISTER) */
+#define BIT_APP_FCS_8197F BIT(31)
+#define BIT_APP_MIC_8197F BIT(30)
+#define BIT_APP_ICV_8197F BIT(29)
+#define BIT_APP_PHYSTS_8197F BIT(28)
+#define BIT_APP_BASSN_8197F BIT(27)
+#define BIT_VHT_DACK_8197F BIT(26)
+#define BIT_TCPOFLD_EN_8197F BIT(25)
+#define BIT_ENMBID_8197F BIT(24)
+#define BIT_LSIGEN_8197F BIT(23)
+#define BIT_MFBEN_8197F BIT(22)
+#define BIT_DISCHKPPDLLEN_8197F BIT(21)
+#define BIT_PKTCTL_DLEN_8197F BIT(20)
+#define BIT_TIM_PARSER_EN_8197F BIT(18)
+#define BIT_BC_MD_EN_8197F BIT(17)
+#define BIT_UC_MD_EN_8197F BIT(16)
+#define BIT_RXSK_PERPKT_8197F BIT(15)
+#define BIT_HTC_LOC_CTRL_8197F BIT(14)
+#define BIT_TA_BCN_8197F BIT(11)
+#define BIT_DISDECMYPKT_8197F BIT(10)
+#define BIT_AICV_8197F BIT(9)
+#define BIT_ACRC32_8197F BIT(8)
+#define BIT_CBSSID_BCN_8197F BIT(7)
+#define BIT_CBSSID_DATA_8197F BIT(6)
+#define BIT_APWRMGT_8197F BIT(5)
+#define BIT_ADD3_8197F BIT(4)
+#define BIT_AB_8197F BIT(3)
+#define BIT_AM_8197F BIT(2)
+#define BIT_APM_8197F BIT(1)
+#define BIT_AAP_8197F BIT(0)
+
+/* 2 REG_RX_DRVINFO_SZ_8197F (RX DRIVER INFO SIZE REGISTER) */
+#define BIT_APP_PHYSTS_PER_SUBMPDU_8197F BIT(7)
+#define BIT_APP_MH_SHIFT_VAL_8197F BIT(6)
+#define BIT_WMAC_ENSHIFT_8197F BIT(5)
+
+#define BIT_SHIFT_DRVINFO_SZ_V1_8197F 0
+#define BIT_MASK_DRVINFO_SZ_V1_8197F 0xf
+#define BIT_DRVINFO_SZ_V1_8197F(x)                                             \
+	(((x) & BIT_MASK_DRVINFO_SZ_V1_8197F) << BIT_SHIFT_DRVINFO_SZ_V1_8197F)
+#define BITS_DRVINFO_SZ_V1_8197F                                               \
+	(BIT_MASK_DRVINFO_SZ_V1_8197F << BIT_SHIFT_DRVINFO_SZ_V1_8197F)
+#define BIT_CLEAR_DRVINFO_SZ_V1_8197F(x) ((x) & (~BITS_DRVINFO_SZ_V1_8197F))
+#define BIT_GET_DRVINFO_SZ_V1_8197F(x)                                         \
+	(((x) >> BIT_SHIFT_DRVINFO_SZ_V1_8197F) & BIT_MASK_DRVINFO_SZ_V1_8197F)
+#define BIT_SET_DRVINFO_SZ_V1_8197F(x, v)                                      \
+	(BIT_CLEAR_DRVINFO_SZ_V1_8197F(x) | BIT_DRVINFO_SZ_V1_8197F(v))
+
+/* 2 REG_RX_DLK_TIME_8197F (RX DEADLOCK TIME REGISTER) */
+
+#define BIT_SHIFT_RX_DLK_TIME_8197F 0
+#define BIT_MASK_RX_DLK_TIME_8197F 0xff
+#define BIT_RX_DLK_TIME_8197F(x)                                               \
+	(((x) & BIT_MASK_RX_DLK_TIME_8197F) << BIT_SHIFT_RX_DLK_TIME_8197F)
+#define BITS_RX_DLK_TIME_8197F                                                 \
+	(BIT_MASK_RX_DLK_TIME_8197F << BIT_SHIFT_RX_DLK_TIME_8197F)
+#define BIT_CLEAR_RX_DLK_TIME_8197F(x) ((x) & (~BITS_RX_DLK_TIME_8197F))
+#define BIT_GET_RX_DLK_TIME_8197F(x)                                           \
+	(((x) >> BIT_SHIFT_RX_DLK_TIME_8197F) & BIT_MASK_RX_DLK_TIME_8197F)
+#define BIT_SET_RX_DLK_TIME_8197F(x, v)                                        \
+	(BIT_CLEAR_RX_DLK_TIME_8197F(x) | BIT_RX_DLK_TIME_8197F(v))
+
+/* 2 REG_RX_PKT_LIMIT_8197F (RX PACKET LENGTH LIMIT REGISTER) */
+
+#define BIT_SHIFT_RXPKTLMT_8197F 0
+#define BIT_MASK_RXPKTLMT_8197F 0x3f
+#define BIT_RXPKTLMT_8197F(x)                                                  \
+	(((x) & BIT_MASK_RXPKTLMT_8197F) << BIT_SHIFT_RXPKTLMT_8197F)
+#define BITS_RXPKTLMT_8197F                                                    \
+	(BIT_MASK_RXPKTLMT_8197F << BIT_SHIFT_RXPKTLMT_8197F)
+#define BIT_CLEAR_RXPKTLMT_8197F(x) ((x) & (~BITS_RXPKTLMT_8197F))
+#define BIT_GET_RXPKTLMT_8197F(x)                                              \
+	(((x) >> BIT_SHIFT_RXPKTLMT_8197F) & BIT_MASK_RXPKTLMT_8197F)
+#define BIT_SET_RXPKTLMT_8197F(x, v)                                           \
+	(BIT_CLEAR_RXPKTLMT_8197F(x) | BIT_RXPKTLMT_8197F(v))
+
+/* 2 REG_MACID_8197F (MAC ID REGISTER) */
+
+#define BIT_SHIFT_MACID_8197F 0
+#define BIT_MASK_MACID_8197F 0xffffffffffffL
+#define BIT_MACID_8197F(x)                                                     \
+	(((x) & BIT_MASK_MACID_8197F) << BIT_SHIFT_MACID_8197F)
+#define BITS_MACID_8197F (BIT_MASK_MACID_8197F << BIT_SHIFT_MACID_8197F)
+#define BIT_CLEAR_MACID_8197F(x) ((x) & (~BITS_MACID_8197F))
+#define BIT_GET_MACID_8197F(x)                                                 \
+	(((x) >> BIT_SHIFT_MACID_8197F) & BIT_MASK_MACID_8197F)
+#define BIT_SET_MACID_8197F(x, v)                                              \
+	(BIT_CLEAR_MACID_8197F(x) | BIT_MACID_8197F(v))
+
+/* 2 REG_BSSID_8197F (BSSID REGISTER) */
+
+#define BIT_SHIFT_BSSID_8197F 0
+#define BIT_MASK_BSSID_8197F 0xffffffffffffL
+#define BIT_BSSID_8197F(x)                                                     \
+	(((x) & BIT_MASK_BSSID_8197F) << BIT_SHIFT_BSSID_8197F)
+#define BITS_BSSID_8197F (BIT_MASK_BSSID_8197F << BIT_SHIFT_BSSID_8197F)
+#define BIT_CLEAR_BSSID_8197F(x) ((x) & (~BITS_BSSID_8197F))
+#define BIT_GET_BSSID_8197F(x)                                                 \
+	(((x) >> BIT_SHIFT_BSSID_8197F) & BIT_MASK_BSSID_8197F)
+#define BIT_SET_BSSID_8197F(x, v)                                              \
+	(BIT_CLEAR_BSSID_8197F(x) | BIT_BSSID_8197F(v))
+
+/* 2 REG_MAR_8197F (MULTICAST ADDRESS REGISTER) */
+
+#define BIT_SHIFT_MAR_8197F 0
+#define BIT_MASK_MAR_8197F 0xffffffffffffffffL
+#define BIT_MAR_8197F(x) (((x) & BIT_MASK_MAR_8197F) << BIT_SHIFT_MAR_8197F)
+#define BITS_MAR_8197F (BIT_MASK_MAR_8197F << BIT_SHIFT_MAR_8197F)
+#define BIT_CLEAR_MAR_8197F(x) ((x) & (~BITS_MAR_8197F))
+#define BIT_GET_MAR_8197F(x) (((x) >> BIT_SHIFT_MAR_8197F) & BIT_MASK_MAR_8197F)
+#define BIT_SET_MAR_8197F(x, v) (BIT_CLEAR_MAR_8197F(x) | BIT_MAR_8197F(v))
+
+/* 2 REG_MBIDCAMCFG_1_8197F (MBSSID CAM CONFIGURATION REGISTER) */
+
+#define BIT_SHIFT_MBIDCAM_RWDATA_L_8197F 0
+#define BIT_MASK_MBIDCAM_RWDATA_L_8197F 0xffffffffL
+#define BIT_MBIDCAM_RWDATA_L_8197F(x)                                          \
+	(((x) & BIT_MASK_MBIDCAM_RWDATA_L_8197F)                               \
+	 << BIT_SHIFT_MBIDCAM_RWDATA_L_8197F)
+#define BITS_MBIDCAM_RWDATA_L_8197F                                            \
+	(BIT_MASK_MBIDCAM_RWDATA_L_8197F << BIT_SHIFT_MBIDCAM_RWDATA_L_8197F)
+#define BIT_CLEAR_MBIDCAM_RWDATA_L_8197F(x)                                    \
+	((x) & (~BITS_MBIDCAM_RWDATA_L_8197F))
+#define BIT_GET_MBIDCAM_RWDATA_L_8197F(x)                                      \
+	(((x) >> BIT_SHIFT_MBIDCAM_RWDATA_L_8197F) &                           \
+	 BIT_MASK_MBIDCAM_RWDATA_L_8197F)
+#define BIT_SET_MBIDCAM_RWDATA_L_8197F(x, v)                                   \
+	(BIT_CLEAR_MBIDCAM_RWDATA_L_8197F(x) | BIT_MBIDCAM_RWDATA_L_8197F(v))
+
+/* 2 REG_MBIDCAMCFG_2_8197F (MBSSID CAM CONFIGURATION REGISTER) */
+#define BIT_MBIDCAM_POLL_8197F BIT(31)
+#define BIT_MBIDCAM_WT_EN_8197F BIT(30)
+
+#define BIT_SHIFT_MBIDCAM_ADDR_V1_8197F 24
+#define BIT_MASK_MBIDCAM_ADDR_V1_8197F 0x3f
+#define BIT_MBIDCAM_ADDR_V1_8197F(x)                                           \
+	(((x) & BIT_MASK_MBIDCAM_ADDR_V1_8197F)                                \
+	 << BIT_SHIFT_MBIDCAM_ADDR_V1_8197F)
+#define BITS_MBIDCAM_ADDR_V1_8197F                                             \
+	(BIT_MASK_MBIDCAM_ADDR_V1_8197F << BIT_SHIFT_MBIDCAM_ADDR_V1_8197F)
+#define BIT_CLEAR_MBIDCAM_ADDR_V1_8197F(x) ((x) & (~BITS_MBIDCAM_ADDR_V1_8197F))
+#define BIT_GET_MBIDCAM_ADDR_V1_8197F(x)                                       \
+	(((x) >> BIT_SHIFT_MBIDCAM_ADDR_V1_8197F) &                            \
+	 BIT_MASK_MBIDCAM_ADDR_V1_8197F)
+#define BIT_SET_MBIDCAM_ADDR_V1_8197F(x, v)                                    \
+	(BIT_CLEAR_MBIDCAM_ADDR_V1_8197F(x) | BIT_MBIDCAM_ADDR_V1_8197F(v))
+
+#define BIT_MBIDCAM_VALID_8197F BIT(23)
+#define BIT_LSIC_TXOP_EN_8197F BIT(17)
+#define BIT_REPEAT_MODE_EN_8197F BIT(16)
+
+#define BIT_SHIFT_MBIDCAM_RWDATA_H_8197F 0
+#define BIT_MASK_MBIDCAM_RWDATA_H_8197F 0xffff
+#define BIT_MBIDCAM_RWDATA_H_8197F(x)                                          \
+	(((x) & BIT_MASK_MBIDCAM_RWDATA_H_8197F)                               \
+	 << BIT_SHIFT_MBIDCAM_RWDATA_H_8197F)
+#define BITS_MBIDCAM_RWDATA_H_8197F                                            \
+	(BIT_MASK_MBIDCAM_RWDATA_H_8197F << BIT_SHIFT_MBIDCAM_RWDATA_H_8197F)
+#define BIT_CLEAR_MBIDCAM_RWDATA_H_8197F(x)                                    \
+	((x) & (~BITS_MBIDCAM_RWDATA_H_8197F))
+#define BIT_GET_MBIDCAM_RWDATA_H_8197F(x)                                      \
+	(((x) >> BIT_SHIFT_MBIDCAM_RWDATA_H_8197F) &                           \
+	 BIT_MASK_MBIDCAM_RWDATA_H_8197F)
+#define BIT_SET_MBIDCAM_RWDATA_H_8197F(x, v)                                   \
+	(BIT_CLEAR_MBIDCAM_RWDATA_H_8197F(x) | BIT_MBIDCAM_RWDATA_H_8197F(v))
+
+/* 2 REG_ZLD_NUM_8197F */
+
+#define BIT_SHIFT_ZLD_NUM_8197F 0
+#define BIT_MASK_ZLD_NUM_8197F 0xff
+#define BIT_ZLD_NUM_8197F(x)                                                   \
+	(((x) & BIT_MASK_ZLD_NUM_8197F) << BIT_SHIFT_ZLD_NUM_8197F)
+#define BITS_ZLD_NUM_8197F (BIT_MASK_ZLD_NUM_8197F << BIT_SHIFT_ZLD_NUM_8197F)
+#define BIT_CLEAR_ZLD_NUM_8197F(x) ((x) & (~BITS_ZLD_NUM_8197F))
+#define BIT_GET_ZLD_NUM_8197F(x)                                               \
+	(((x) >> BIT_SHIFT_ZLD_NUM_8197F) & BIT_MASK_ZLD_NUM_8197F)
+#define BIT_SET_ZLD_NUM_8197F(x, v)                                            \
+	(BIT_CLEAR_ZLD_NUM_8197F(x) | BIT_ZLD_NUM_8197F(v))
+
+/* 2 REG_UDF_THSD_8197F */
+
+#define BIT_SHIFT_UDF_THSD_8197F 0
+#define BIT_MASK_UDF_THSD_8197F 0xff
+#define BIT_UDF_THSD_8197F(x)                                                  \
+	(((x) & BIT_MASK_UDF_THSD_8197F) << BIT_SHIFT_UDF_THSD_8197F)
+#define BITS_UDF_THSD_8197F                                                    \
+	(BIT_MASK_UDF_THSD_8197F << BIT_SHIFT_UDF_THSD_8197F)
+#define BIT_CLEAR_UDF_THSD_8197F(x) ((x) & (~BITS_UDF_THSD_8197F))
+#define BIT_GET_UDF_THSD_8197F(x)                                              \
+	(((x) >> BIT_SHIFT_UDF_THSD_8197F) & BIT_MASK_UDF_THSD_8197F)
+#define BIT_SET_UDF_THSD_8197F(x, v)                                           \
+	(BIT_CLEAR_UDF_THSD_8197F(x) | BIT_UDF_THSD_8197F(v))
+
+/* 2 REG_WMAC_TCR_TSFT_OFS_8197F */
+
+#define BIT_SHIFT_WMAC_TCR_TSFT_OFS_8197F 0
+#define BIT_MASK_WMAC_TCR_TSFT_OFS_8197F 0xffff
+#define BIT_WMAC_TCR_TSFT_OFS_8197F(x)                                         \
+	(((x) & BIT_MASK_WMAC_TCR_TSFT_OFS_8197F)                              \
+	 << BIT_SHIFT_WMAC_TCR_TSFT_OFS_8197F)
+#define BITS_WMAC_TCR_TSFT_OFS_8197F                                           \
+	(BIT_MASK_WMAC_TCR_TSFT_OFS_8197F << BIT_SHIFT_WMAC_TCR_TSFT_OFS_8197F)
+#define BIT_CLEAR_WMAC_TCR_TSFT_OFS_8197F(x)                                   \
+	((x) & (~BITS_WMAC_TCR_TSFT_OFS_8197F))
+#define BIT_GET_WMAC_TCR_TSFT_OFS_8197F(x)                                     \
+	(((x) >> BIT_SHIFT_WMAC_TCR_TSFT_OFS_8197F) &                          \
+	 BIT_MASK_WMAC_TCR_TSFT_OFS_8197F)
+#define BIT_SET_WMAC_TCR_TSFT_OFS_8197F(x, v)                                  \
+	(BIT_CLEAR_WMAC_TCR_TSFT_OFS_8197F(x) | BIT_WMAC_TCR_TSFT_OFS_8197F(v))
+
+/* 2 REG_MCU_TEST_2_V1_8197F */
+
+#define BIT_SHIFT_MCU_RSVD_2_V1_8197F 0
+#define BIT_MASK_MCU_RSVD_2_V1_8197F 0xffff
+#define BIT_MCU_RSVD_2_V1_8197F(x)                                             \
+	(((x) & BIT_MASK_MCU_RSVD_2_V1_8197F) << BIT_SHIFT_MCU_RSVD_2_V1_8197F)
+#define BITS_MCU_RSVD_2_V1_8197F                                               \
+	(BIT_MASK_MCU_RSVD_2_V1_8197F << BIT_SHIFT_MCU_RSVD_2_V1_8197F)
+#define BIT_CLEAR_MCU_RSVD_2_V1_8197F(x) ((x) & (~BITS_MCU_RSVD_2_V1_8197F))
+#define BIT_GET_MCU_RSVD_2_V1_8197F(x)                                         \
+	(((x) >> BIT_SHIFT_MCU_RSVD_2_V1_8197F) & BIT_MASK_MCU_RSVD_2_V1_8197F)
+#define BIT_SET_MCU_RSVD_2_V1_8197F(x, v)                                      \
+	(BIT_CLEAR_MCU_RSVD_2_V1_8197F(x) | BIT_MCU_RSVD_2_V1_8197F(v))
+
+/* 2 REG_WMAC_TXTIMEOUT_8197F */
+
+#define BIT_SHIFT_WMAC_TXTIMEOUT_8197F 0
+#define BIT_MASK_WMAC_TXTIMEOUT_8197F 0xff
+#define BIT_WMAC_TXTIMEOUT_8197F(x)                                            \
+	(((x) & BIT_MASK_WMAC_TXTIMEOUT_8197F)                                 \
+	 << BIT_SHIFT_WMAC_TXTIMEOUT_8197F)
+#define BITS_WMAC_TXTIMEOUT_8197F                                              \
+	(BIT_MASK_WMAC_TXTIMEOUT_8197F << BIT_SHIFT_WMAC_TXTIMEOUT_8197F)
+#define BIT_CLEAR_WMAC_TXTIMEOUT_8197F(x) ((x) & (~BITS_WMAC_TXTIMEOUT_8197F))
+#define BIT_GET_WMAC_TXTIMEOUT_8197F(x)                                        \
+	(((x) >> BIT_SHIFT_WMAC_TXTIMEOUT_8197F) &                             \
+	 BIT_MASK_WMAC_TXTIMEOUT_8197F)
+#define BIT_SET_WMAC_TXTIMEOUT_8197F(x, v)                                     \
+	(BIT_CLEAR_WMAC_TXTIMEOUT_8197F(x) | BIT_WMAC_TXTIMEOUT_8197F(v))
+
+/* 2 REG_STMP_THSD_8197F */
+
+#define BIT_SHIFT_STMP_THSD_8197F 0
+#define BIT_MASK_STMP_THSD_8197F 0xff
+#define BIT_STMP_THSD_8197F(x)                                                 \
+	(((x) & BIT_MASK_STMP_THSD_8197F) << BIT_SHIFT_STMP_THSD_8197F)
+#define BITS_STMP_THSD_8197F                                                   \
+	(BIT_MASK_STMP_THSD_8197F << BIT_SHIFT_STMP_THSD_8197F)
+#define BIT_CLEAR_STMP_THSD_8197F(x) ((x) & (~BITS_STMP_THSD_8197F))
+#define BIT_GET_STMP_THSD_8197F(x)                                             \
+	(((x) >> BIT_SHIFT_STMP_THSD_8197F) & BIT_MASK_STMP_THSD_8197F)
+#define BIT_SET_STMP_THSD_8197F(x, v)                                          \
+	(BIT_CLEAR_STMP_THSD_8197F(x) | BIT_STMP_THSD_8197F(v))
+
+/* 2 REG_MAC_SPEC_SIFS_8197F (SPECIFICATION SIFS REGISTER) */
+
+#define BIT_SHIFT_SPEC_SIFS_OFDM_8197F 8
+#define BIT_MASK_SPEC_SIFS_OFDM_8197F 0xff
+#define BIT_SPEC_SIFS_OFDM_8197F(x)                                            \
+	(((x) & BIT_MASK_SPEC_SIFS_OFDM_8197F)                                 \
+	 << BIT_SHIFT_SPEC_SIFS_OFDM_8197F)
+#define BITS_SPEC_SIFS_OFDM_8197F                                              \
+	(BIT_MASK_SPEC_SIFS_OFDM_8197F << BIT_SHIFT_SPEC_SIFS_OFDM_8197F)
+#define BIT_CLEAR_SPEC_SIFS_OFDM_8197F(x) ((x) & (~BITS_SPEC_SIFS_OFDM_8197F))
+#define BIT_GET_SPEC_SIFS_OFDM_8197F(x)                                        \
+	(((x) >> BIT_SHIFT_SPEC_SIFS_OFDM_8197F) &                             \
+	 BIT_MASK_SPEC_SIFS_OFDM_8197F)
+#define BIT_SET_SPEC_SIFS_OFDM_8197F(x, v)                                     \
+	(BIT_CLEAR_SPEC_SIFS_OFDM_8197F(x) | BIT_SPEC_SIFS_OFDM_8197F(v))
+
+#define BIT_SHIFT_SPEC_SIFS_CCK_8197F 0
+#define BIT_MASK_SPEC_SIFS_CCK_8197F 0xff
+#define BIT_SPEC_SIFS_CCK_8197F(x)                                             \
+	(((x) & BIT_MASK_SPEC_SIFS_CCK_8197F) << BIT_SHIFT_SPEC_SIFS_CCK_8197F)
+#define BITS_SPEC_SIFS_CCK_8197F                                               \
+	(BIT_MASK_SPEC_SIFS_CCK_8197F << BIT_SHIFT_SPEC_SIFS_CCK_8197F)
+#define BIT_CLEAR_SPEC_SIFS_CCK_8197F(x) ((x) & (~BITS_SPEC_SIFS_CCK_8197F))
+#define BIT_GET_SPEC_SIFS_CCK_8197F(x)                                         \
+	(((x) >> BIT_SHIFT_SPEC_SIFS_CCK_8197F) & BIT_MASK_SPEC_SIFS_CCK_8197F)
+#define BIT_SET_SPEC_SIFS_CCK_8197F(x, v)                                      \
+	(BIT_CLEAR_SPEC_SIFS_CCK_8197F(x) | BIT_SPEC_SIFS_CCK_8197F(v))
+
+/* 2 REG_USTIME_EDCA_8197F (US TIME TUNING FOR EDCA REGISTER) */
+
+#define BIT_SHIFT_USTIME_EDCA_8197F 0
+#define BIT_MASK_USTIME_EDCA_8197F 0xff
+#define BIT_USTIME_EDCA_8197F(x)                                               \
+	(((x) & BIT_MASK_USTIME_EDCA_8197F) << BIT_SHIFT_USTIME_EDCA_8197F)
+#define BITS_USTIME_EDCA_8197F                                                 \
+	(BIT_MASK_USTIME_EDCA_8197F << BIT_SHIFT_USTIME_EDCA_8197F)
+#define BIT_CLEAR_USTIME_EDCA_8197F(x) ((x) & (~BITS_USTIME_EDCA_8197F))
+#define BIT_GET_USTIME_EDCA_8197F(x)                                           \
+	(((x) >> BIT_SHIFT_USTIME_EDCA_8197F) & BIT_MASK_USTIME_EDCA_8197F)
+#define BIT_SET_USTIME_EDCA_8197F(x, v)                                        \
+	(BIT_CLEAR_USTIME_EDCA_8197F(x) | BIT_USTIME_EDCA_8197F(v))
+
+/* 2 REG_RESP_SIFS_OFDM_8197F (RESPONSE SIFS FOR OFDM REGISTER) */
+
+#define BIT_SHIFT_SIFS_R2T_OFDM_8197F 8
+#define BIT_MASK_SIFS_R2T_OFDM_8197F 0xff
+#define BIT_SIFS_R2T_OFDM_8197F(x)                                             \
+	(((x) & BIT_MASK_SIFS_R2T_OFDM_8197F) << BIT_SHIFT_SIFS_R2T_OFDM_8197F)
+#define BITS_SIFS_R2T_OFDM_8197F                                               \
+	(BIT_MASK_SIFS_R2T_OFDM_8197F << BIT_SHIFT_SIFS_R2T_OFDM_8197F)
+#define BIT_CLEAR_SIFS_R2T_OFDM_8197F(x) ((x) & (~BITS_SIFS_R2T_OFDM_8197F))
+#define BIT_GET_SIFS_R2T_OFDM_8197F(x)                                         \
+	(((x) >> BIT_SHIFT_SIFS_R2T_OFDM_8197F) & BIT_MASK_SIFS_R2T_OFDM_8197F)
+#define BIT_SET_SIFS_R2T_OFDM_8197F(x, v)                                      \
+	(BIT_CLEAR_SIFS_R2T_OFDM_8197F(x) | BIT_SIFS_R2T_OFDM_8197F(v))
+
+#define BIT_SHIFT_SIFS_T2T_OFDM_8197F 0
+#define BIT_MASK_SIFS_T2T_OFDM_8197F 0xff
+#define BIT_SIFS_T2T_OFDM_8197F(x)                                             \
+	(((x) & BIT_MASK_SIFS_T2T_OFDM_8197F) << BIT_SHIFT_SIFS_T2T_OFDM_8197F)
+#define BITS_SIFS_T2T_OFDM_8197F                                               \
+	(BIT_MASK_SIFS_T2T_OFDM_8197F << BIT_SHIFT_SIFS_T2T_OFDM_8197F)
+#define BIT_CLEAR_SIFS_T2T_OFDM_8197F(x) ((x) & (~BITS_SIFS_T2T_OFDM_8197F))
+#define BIT_GET_SIFS_T2T_OFDM_8197F(x)                                         \
+	(((x) >> BIT_SHIFT_SIFS_T2T_OFDM_8197F) & BIT_MASK_SIFS_T2T_OFDM_8197F)
+#define BIT_SET_SIFS_T2T_OFDM_8197F(x, v)                                      \
+	(BIT_CLEAR_SIFS_T2T_OFDM_8197F(x) | BIT_SIFS_T2T_OFDM_8197F(v))
+
+/* 2 REG_RESP_SIFS_CCK_8197F (RESPONSE SIFS FOR CCK REGISTER) */
+
+#define BIT_SHIFT_SIFS_R2T_CCK_8197F 8
+#define BIT_MASK_SIFS_R2T_CCK_8197F 0xff
+#define BIT_SIFS_R2T_CCK_8197F(x)                                              \
+	(((x) & BIT_MASK_SIFS_R2T_CCK_8197F) << BIT_SHIFT_SIFS_R2T_CCK_8197F)
+#define BITS_SIFS_R2T_CCK_8197F                                                \
+	(BIT_MASK_SIFS_R2T_CCK_8197F << BIT_SHIFT_SIFS_R2T_CCK_8197F)
+#define BIT_CLEAR_SIFS_R2T_CCK_8197F(x) ((x) & (~BITS_SIFS_R2T_CCK_8197F))
+#define BIT_GET_SIFS_R2T_CCK_8197F(x)                                          \
+	(((x) >> BIT_SHIFT_SIFS_R2T_CCK_8197F) & BIT_MASK_SIFS_R2T_CCK_8197F)
+#define BIT_SET_SIFS_R2T_CCK_8197F(x, v)                                       \
+	(BIT_CLEAR_SIFS_R2T_CCK_8197F(x) | BIT_SIFS_R2T_CCK_8197F(v))
+
+#define BIT_SHIFT_SIFS_T2T_CCK_8197F 0
+#define BIT_MASK_SIFS_T2T_CCK_8197F 0xff
+#define BIT_SIFS_T2T_CCK_8197F(x)                                              \
+	(((x) & BIT_MASK_SIFS_T2T_CCK_8197F) << BIT_SHIFT_SIFS_T2T_CCK_8197F)
+#define BITS_SIFS_T2T_CCK_8197F                                                \
+	(BIT_MASK_SIFS_T2T_CCK_8197F << BIT_SHIFT_SIFS_T2T_CCK_8197F)
+#define BIT_CLEAR_SIFS_T2T_CCK_8197F(x) ((x) & (~BITS_SIFS_T2T_CCK_8197F))
+#define BIT_GET_SIFS_T2T_CCK_8197F(x)                                          \
+	(((x) >> BIT_SHIFT_SIFS_T2T_CCK_8197F) & BIT_MASK_SIFS_T2T_CCK_8197F)
+#define BIT_SET_SIFS_T2T_CCK_8197F(x, v)                                       \
+	(BIT_CLEAR_SIFS_T2T_CCK_8197F(x) | BIT_SIFS_T2T_CCK_8197F(v))
+
+/* 2 REG_EIFS_8197F (EIFS REGISTER) */
+
+#define BIT_SHIFT_EIFS_8197F 0
+#define BIT_MASK_EIFS_8197F 0xffff
+#define BIT_EIFS_8197F(x) (((x) & BIT_MASK_EIFS_8197F) << BIT_SHIFT_EIFS_8197F)
+#define BITS_EIFS_8197F (BIT_MASK_EIFS_8197F << BIT_SHIFT_EIFS_8197F)
+#define BIT_CLEAR_EIFS_8197F(x) ((x) & (~BITS_EIFS_8197F))
+#define BIT_GET_EIFS_8197F(x)                                                  \
+	(((x) >> BIT_SHIFT_EIFS_8197F) & BIT_MASK_EIFS_8197F)
+#define BIT_SET_EIFS_8197F(x, v) (BIT_CLEAR_EIFS_8197F(x) | BIT_EIFS_8197F(v))
+
+/* 2 REG_CTS2TO_8197F (CTS2 TIMEOUT REGISTER) */
+
+#define BIT_SHIFT_CTS2TO_8197F 0
+#define BIT_MASK_CTS2TO_8197F 0xff
+#define BIT_CTS2TO_8197F(x)                                                    \
+	(((x) & BIT_MASK_CTS2TO_8197F) << BIT_SHIFT_CTS2TO_8197F)
+#define BITS_CTS2TO_8197F (BIT_MASK_CTS2TO_8197F << BIT_SHIFT_CTS2TO_8197F)
+#define BIT_CLEAR_CTS2TO_8197F(x) ((x) & (~BITS_CTS2TO_8197F))
+#define BIT_GET_CTS2TO_8197F(x)                                                \
+	(((x) >> BIT_SHIFT_CTS2TO_8197F) & BIT_MASK_CTS2TO_8197F)
+#define BIT_SET_CTS2TO_8197F(x, v)                                             \
+	(BIT_CLEAR_CTS2TO_8197F(x) | BIT_CTS2TO_8197F(v))
+
+/* 2 REG_ACKTO_8197F (ACK TIMEOUT REGISTER) */
+
+#define BIT_SHIFT_ACKTO_8197F 0
+#define BIT_MASK_ACKTO_8197F 0xff
+#define BIT_ACKTO_8197F(x)                                                     \
+	(((x) & BIT_MASK_ACKTO_8197F) << BIT_SHIFT_ACKTO_8197F)
+#define BITS_ACKTO_8197F (BIT_MASK_ACKTO_8197F << BIT_SHIFT_ACKTO_8197F)
+#define BIT_CLEAR_ACKTO_8197F(x) ((x) & (~BITS_ACKTO_8197F))
+#define BIT_GET_ACKTO_8197F(x)                                                 \
+	(((x) >> BIT_SHIFT_ACKTO_8197F) & BIT_MASK_ACKTO_8197F)
+#define BIT_SET_ACKTO_8197F(x, v)                                              \
+	(BIT_CLEAR_ACKTO_8197F(x) | BIT_ACKTO_8197F(v))
+
+/* 2 REG_NOT_VALID_8197F */
+
+/* 2 REG_NAV_CTRL_8197F (NAV CONTROL REGISTER) */
+
+#define BIT_SHIFT_NAV_UPPER_8197F 16
+#define BIT_MASK_NAV_UPPER_8197F 0xff
+#define BIT_NAV_UPPER_8197F(x)                                                 \
+	(((x) & BIT_MASK_NAV_UPPER_8197F) << BIT_SHIFT_NAV_UPPER_8197F)
+#define BITS_NAV_UPPER_8197F                                                   \
+	(BIT_MASK_NAV_UPPER_8197F << BIT_SHIFT_NAV_UPPER_8197F)
+#define BIT_CLEAR_NAV_UPPER_8197F(x) ((x) & (~BITS_NAV_UPPER_8197F))
+#define BIT_GET_NAV_UPPER_8197F(x)                                             \
+	(((x) >> BIT_SHIFT_NAV_UPPER_8197F) & BIT_MASK_NAV_UPPER_8197F)
+#define BIT_SET_NAV_UPPER_8197F(x, v)                                          \
+	(BIT_CLEAR_NAV_UPPER_8197F(x) | BIT_NAV_UPPER_8197F(v))
+
+#define BIT_SHIFT_RXMYRTS_NAV_8197F 8
+#define BIT_MASK_RXMYRTS_NAV_8197F 0xf
+#define BIT_RXMYRTS_NAV_8197F(x)                                               \
+	(((x) & BIT_MASK_RXMYRTS_NAV_8197F) << BIT_SHIFT_RXMYRTS_NAV_8197F)
+#define BITS_RXMYRTS_NAV_8197F                                                 \
+	(BIT_MASK_RXMYRTS_NAV_8197F << BIT_SHIFT_RXMYRTS_NAV_8197F)
+#define BIT_CLEAR_RXMYRTS_NAV_8197F(x) ((x) & (~BITS_RXMYRTS_NAV_8197F))
+#define BIT_GET_RXMYRTS_NAV_8197F(x)                                           \
+	(((x) >> BIT_SHIFT_RXMYRTS_NAV_8197F) & BIT_MASK_RXMYRTS_NAV_8197F)
+#define BIT_SET_RXMYRTS_NAV_8197F(x, v)                                        \
+	(BIT_CLEAR_RXMYRTS_NAV_8197F(x) | BIT_RXMYRTS_NAV_8197F(v))
+
+#define BIT_SHIFT_RTSRST_8197F 0
+#define BIT_MASK_RTSRST_8197F 0xff
+#define BIT_RTSRST_8197F(x)                                                    \
+	(((x) & BIT_MASK_RTSRST_8197F) << BIT_SHIFT_RTSRST_8197F)
+#define BITS_RTSRST_8197F (BIT_MASK_RTSRST_8197F << BIT_SHIFT_RTSRST_8197F)
+#define BIT_CLEAR_RTSRST_8197F(x) ((x) & (~BITS_RTSRST_8197F))
+#define BIT_GET_RTSRST_8197F(x)                                                \
+	(((x) >> BIT_SHIFT_RTSRST_8197F) & BIT_MASK_RTSRST_8197F)
+#define BIT_SET_RTSRST_8197F(x, v)                                             \
+	(BIT_CLEAR_RTSRST_8197F(x) | BIT_RTSRST_8197F(v))
+
+/* 2 REG_BACAMCMD_8197F (BLOCK ACK CAM COMMAND REGISTER) */
+#define BIT_BACAM_POLL_8197F BIT(31)
+#define BIT_BACAM_RST_8197F BIT(17)
+#define BIT_BACAM_RW_8197F BIT(16)
+
+#define BIT_SHIFT_TXSBM_8197F 14
+#define BIT_MASK_TXSBM_8197F 0x3
+#define BIT_TXSBM_8197F(x)                                                     \
+	(((x) & BIT_MASK_TXSBM_8197F) << BIT_SHIFT_TXSBM_8197F)
+#define BITS_TXSBM_8197F (BIT_MASK_TXSBM_8197F << BIT_SHIFT_TXSBM_8197F)
+#define BIT_CLEAR_TXSBM_8197F(x) ((x) & (~BITS_TXSBM_8197F))
+#define BIT_GET_TXSBM_8197F(x)                                                 \
+	(((x) >> BIT_SHIFT_TXSBM_8197F) & BIT_MASK_TXSBM_8197F)
+#define BIT_SET_TXSBM_8197F(x, v)                                              \
+	(BIT_CLEAR_TXSBM_8197F(x) | BIT_TXSBM_8197F(v))
+
+#define BIT_SHIFT_BACAM_ADDR_8197F 0
+#define BIT_MASK_BACAM_ADDR_8197F 0x3f
+#define BIT_BACAM_ADDR_8197F(x)                                                \
+	(((x) & BIT_MASK_BACAM_ADDR_8197F) << BIT_SHIFT_BACAM_ADDR_8197F)
+#define BITS_BACAM_ADDR_8197F                                                  \
+	(BIT_MASK_BACAM_ADDR_8197F << BIT_SHIFT_BACAM_ADDR_8197F)
+#define BIT_CLEAR_BACAM_ADDR_8197F(x) ((x) & (~BITS_BACAM_ADDR_8197F))
+#define BIT_GET_BACAM_ADDR_8197F(x)                                            \
+	(((x) >> BIT_SHIFT_BACAM_ADDR_8197F) & BIT_MASK_BACAM_ADDR_8197F)
+#define BIT_SET_BACAM_ADDR_8197F(x, v)                                         \
+	(BIT_CLEAR_BACAM_ADDR_8197F(x) | BIT_BACAM_ADDR_8197F(v))
+
+/* 2 REG_BACAMCONTENT_8197F (BLOCK ACK CAM CONTENT REGISTER) */
+
+#define BIT_SHIFT_BA_CONTENT_H_8197F (32 & CPU_OPT_WIDTH)
+#define BIT_MASK_BA_CONTENT_H_8197F 0xffffffffL
+#define BIT_BA_CONTENT_H_8197F(x)                                              \
+	(((x) & BIT_MASK_BA_CONTENT_H_8197F) << BIT_SHIFT_BA_CONTENT_H_8197F)
+#define BITS_BA_CONTENT_H_8197F                                                \
+	(BIT_MASK_BA_CONTENT_H_8197F << BIT_SHIFT_BA_CONTENT_H_8197F)
+#define BIT_CLEAR_BA_CONTENT_H_8197F(x) ((x) & (~BITS_BA_CONTENT_H_8197F))
+#define BIT_GET_BA_CONTENT_H_8197F(x)                                          \
+	(((x) >> BIT_SHIFT_BA_CONTENT_H_8197F) & BIT_MASK_BA_CONTENT_H_8197F)
+#define BIT_SET_BA_CONTENT_H_8197F(x, v)                                       \
+	(BIT_CLEAR_BA_CONTENT_H_8197F(x) | BIT_BA_CONTENT_H_8197F(v))
+
+#define BIT_SHIFT_BA_CONTENT_L_8197F 0
+#define BIT_MASK_BA_CONTENT_L_8197F 0xffffffffL
+#define BIT_BA_CONTENT_L_8197F(x)                                              \
+	(((x) & BIT_MASK_BA_CONTENT_L_8197F) << BIT_SHIFT_BA_CONTENT_L_8197F)
+#define BITS_BA_CONTENT_L_8197F                                                \
+	(BIT_MASK_BA_CONTENT_L_8197F << BIT_SHIFT_BA_CONTENT_L_8197F)
+#define BIT_CLEAR_BA_CONTENT_L_8197F(x) ((x) & (~BITS_BA_CONTENT_L_8197F))
+#define BIT_GET_BA_CONTENT_L_8197F(x)                                          \
+	(((x) >> BIT_SHIFT_BA_CONTENT_L_8197F) & BIT_MASK_BA_CONTENT_L_8197F)
+#define BIT_SET_BA_CONTENT_L_8197F(x, v)                                       \
+	(BIT_CLEAR_BA_CONTENT_L_8197F(x) | BIT_BA_CONTENT_L_8197F(v))
+
+/* 2 REG_WMAC_BITMAP_CTL_8197F */
+#define BIT_BITMAP_VO_8197F BIT(7)
+#define BIT_BITMAP_VI_8197F BIT(6)
+#define BIT_BITMAP_BE_8197F BIT(5)
+#define BIT_BITMAP_BK_8197F BIT(4)
+
+#define BIT_SHIFT_BITMAP_CONDITION_8197F 2
+#define BIT_MASK_BITMAP_CONDITION_8197F 0x3
+#define BIT_BITMAP_CONDITION_8197F(x)                                          \
+	(((x) & BIT_MASK_BITMAP_CONDITION_8197F)                               \
+	 << BIT_SHIFT_BITMAP_CONDITION_8197F)
+#define BITS_BITMAP_CONDITION_8197F                                            \
+	(BIT_MASK_BITMAP_CONDITION_8197F << BIT_SHIFT_BITMAP_CONDITION_8197F)
+#define BIT_CLEAR_BITMAP_CONDITION_8197F(x)                                    \
+	((x) & (~BITS_BITMAP_CONDITION_8197F))
+#define BIT_GET_BITMAP_CONDITION_8197F(x)                                      \
+	(((x) >> BIT_SHIFT_BITMAP_CONDITION_8197F) &                           \
+	 BIT_MASK_BITMAP_CONDITION_8197F)
+#define BIT_SET_BITMAP_CONDITION_8197F(x, v)                                   \
+	(BIT_CLEAR_BITMAP_CONDITION_8197F(x) | BIT_BITMAP_CONDITION_8197F(v))
+
+#define BIT_BITMAP_SSNBK_COUNTER_CLR_8197F BIT(1)
+#define BIT_BITMAP_FORCE_8197F BIT(0)
+
+/* 2 REG_NOT_VALID_8197F */
+
+#define BIT_SHIFT_RXPKT_TYPE_8197F 2
+#define BIT_MASK_RXPKT_TYPE_8197F 0x3f
+#define BIT_RXPKT_TYPE_8197F(x)                                                \
+	(((x) & BIT_MASK_RXPKT_TYPE_8197F) << BIT_SHIFT_RXPKT_TYPE_8197F)
+#define BITS_RXPKT_TYPE_8197F                                                  \
+	(BIT_MASK_RXPKT_TYPE_8197F << BIT_SHIFT_RXPKT_TYPE_8197F)
+#define BIT_CLEAR_RXPKT_TYPE_8197F(x) ((x) & (~BITS_RXPKT_TYPE_8197F))
+#define BIT_GET_RXPKT_TYPE_8197F(x)                                            \
+	(((x) >> BIT_SHIFT_RXPKT_TYPE_8197F) & BIT_MASK_RXPKT_TYPE_8197F)
+#define BIT_SET_RXPKT_TYPE_8197F(x, v)                                         \
+	(BIT_CLEAR_RXPKT_TYPE_8197F(x) | BIT_RXPKT_TYPE_8197F(v))
+
+#define BIT_TXACT_IND_8197F BIT(1)
+#define BIT_RXACT_IND_8197F BIT(0)
+
+/* 2 REG_WMAC_BACAM_RPMEN_8197F */
+
+#define BIT_SHIFT_BITMAP_SSNBK_COUNTER_8197F 2
+#define BIT_MASK_BITMAP_SSNBK_COUNTER_8197F 0x3f
+#define BIT_BITMAP_SSNBK_COUNTER_8197F(x)                                      \
+	(((x) & BIT_MASK_BITMAP_SSNBK_COUNTER_8197F)                           \
+	 << BIT_SHIFT_BITMAP_SSNBK_COUNTER_8197F)
+#define BITS_BITMAP_SSNBK_COUNTER_8197F                                        \
+	(BIT_MASK_BITMAP_SSNBK_COUNTER_8197F                                   \
+	 << BIT_SHIFT_BITMAP_SSNBK_COUNTER_8197F)
+#define BIT_CLEAR_BITMAP_SSNBK_COUNTER_8197F(x)                                \
+	((x) & (~BITS_BITMAP_SSNBK_COUNTER_8197F))
+#define BIT_GET_BITMAP_SSNBK_COUNTER_8197F(x)                                  \
+	(((x) >> BIT_SHIFT_BITMAP_SSNBK_COUNTER_8197F) &                       \
+	 BIT_MASK_BITMAP_SSNBK_COUNTER_8197F)
+#define BIT_SET_BITMAP_SSNBK_COUNTER_8197F(x, v)                               \
+	(BIT_CLEAR_BITMAP_SSNBK_COUNTER_8197F(x) |                             \
+	 BIT_BITMAP_SSNBK_COUNTER_8197F(v))
+
+#define BIT_BITMAP_EN_8197F BIT(1)
+#define BIT_WMAC_BACAM_RPMEN_8197F BIT(0)
+
+/* 2 REG_LBDLY_8197F (LOOPBACK DELAY REGISTER) */
+
+#define BIT_SHIFT_LBDLY_8197F 0
+#define BIT_MASK_LBDLY_8197F 0x1f
+#define BIT_LBDLY_8197F(x)                                                     \
+	(((x) & BIT_MASK_LBDLY_8197F) << BIT_SHIFT_LBDLY_8197F)
+#define BITS_LBDLY_8197F (BIT_MASK_LBDLY_8197F << BIT_SHIFT_LBDLY_8197F)
+#define BIT_CLEAR_LBDLY_8197F(x) ((x) & (~BITS_LBDLY_8197F))
+#define BIT_GET_LBDLY_8197F(x)                                                 \
+	(((x) >> BIT_SHIFT_LBDLY_8197F) & BIT_MASK_LBDLY_8197F)
+#define BIT_SET_LBDLY_8197F(x, v)                                              \
+	(BIT_CLEAR_LBDLY_8197F(x) | BIT_LBDLY_8197F(v))
+
+/* 2 REG_RXERR_RPT_8197F (RX ERROR REPORT REGISTER) */
+
+#define BIT_SHIFT_RXERR_RPT_SEL_V1_3_0_8197F 28
+#define BIT_MASK_RXERR_RPT_SEL_V1_3_0_8197F 0xf
+#define BIT_RXERR_RPT_SEL_V1_3_0_8197F(x)                                      \
+	(((x) & BIT_MASK_RXERR_RPT_SEL_V1_3_0_8197F)                           \
+	 << BIT_SHIFT_RXERR_RPT_SEL_V1_3_0_8197F)
+#define BITS_RXERR_RPT_SEL_V1_3_0_8197F                                        \
+	(BIT_MASK_RXERR_RPT_SEL_V1_3_0_8197F                                   \
+	 << BIT_SHIFT_RXERR_RPT_SEL_V1_3_0_8197F)
+#define BIT_CLEAR_RXERR_RPT_SEL_V1_3_0_8197F(x)                                \
+	((x) & (~BITS_RXERR_RPT_SEL_V1_3_0_8197F))
+#define BIT_GET_RXERR_RPT_SEL_V1_3_0_8197F(x)                                  \
+	(((x) >> BIT_SHIFT_RXERR_RPT_SEL_V1_3_0_8197F) &                       \
+	 BIT_MASK_RXERR_RPT_SEL_V1_3_0_8197F)
+#define BIT_SET_RXERR_RPT_SEL_V1_3_0_8197F(x, v)                               \
+	(BIT_CLEAR_RXERR_RPT_SEL_V1_3_0_8197F(x) |                             \
+	 BIT_RXERR_RPT_SEL_V1_3_0_8197F(v))
+
+#define BIT_RXERR_RPT_RST_8197F BIT(27)
+#define BIT_RXERR_RPT_SEL_V1_4_8197F BIT(26)
+
+#define BIT_SHIFT_UD_SELECT_BSSID_2_1_8197F 24
+#define BIT_MASK_UD_SELECT_BSSID_2_1_8197F 0x3
+#define BIT_UD_SELECT_BSSID_2_1_8197F(x)                                       \
+	(((x) & BIT_MASK_UD_SELECT_BSSID_2_1_8197F)                            \
+	 << BIT_SHIFT_UD_SELECT_BSSID_2_1_8197F)
+#define BITS_UD_SELECT_BSSID_2_1_8197F                                         \
+	(BIT_MASK_UD_SELECT_BSSID_2_1_8197F                                    \
+	 << BIT_SHIFT_UD_SELECT_BSSID_2_1_8197F)
+#define BIT_CLEAR_UD_SELECT_BSSID_2_1_8197F(x)                                 \
+	((x) & (~BITS_UD_SELECT_BSSID_2_1_8197F))
+#define BIT_GET_UD_SELECT_BSSID_2_1_8197F(x)                                   \
+	(((x) >> BIT_SHIFT_UD_SELECT_BSSID_2_1_8197F) &                        \
+	 BIT_MASK_UD_SELECT_BSSID_2_1_8197F)
+#define BIT_SET_UD_SELECT_BSSID_2_1_8197F(x, v)                                \
+	(BIT_CLEAR_UD_SELECT_BSSID_2_1_8197F(x) |                              \
+	 BIT_UD_SELECT_BSSID_2_1_8197F(v))
+
+#define BIT_W1S_8197F BIT(23)
+#define BIT_UD_SELECT_BSSID_0_8197F BIT(22)
+
+#define BIT_SHIFT_UD_SUB_TYPE_8197F 18
+#define BIT_MASK_UD_SUB_TYPE_8197F 0xf
+#define BIT_UD_SUB_TYPE_8197F(x)                                               \
+	(((x) & BIT_MASK_UD_SUB_TYPE_8197F) << BIT_SHIFT_UD_SUB_TYPE_8197F)
+#define BITS_UD_SUB_TYPE_8197F                                                 \
+	(BIT_MASK_UD_SUB_TYPE_8197F << BIT_SHIFT_UD_SUB_TYPE_8197F)
+#define BIT_CLEAR_UD_SUB_TYPE_8197F(x) ((x) & (~BITS_UD_SUB_TYPE_8197F))
+#define BIT_GET_UD_SUB_TYPE_8197F(x)                                           \
+	(((x) >> BIT_SHIFT_UD_SUB_TYPE_8197F) & BIT_MASK_UD_SUB_TYPE_8197F)
+#define BIT_SET_UD_SUB_TYPE_8197F(x, v)                                        \
+	(BIT_CLEAR_UD_SUB_TYPE_8197F(x) | BIT_UD_SUB_TYPE_8197F(v))
+
+#define BIT_SHIFT_UD_TYPE_8197F 16
+#define BIT_MASK_UD_TYPE_8197F 0x3
+#define BIT_UD_TYPE_8197F(x)                                                   \
+	(((x) & BIT_MASK_UD_TYPE_8197F) << BIT_SHIFT_UD_TYPE_8197F)
+#define BITS_UD_TYPE_8197F (BIT_MASK_UD_TYPE_8197F << BIT_SHIFT_UD_TYPE_8197F)
+#define BIT_CLEAR_UD_TYPE_8197F(x) ((x) & (~BITS_UD_TYPE_8197F))
+#define BIT_GET_UD_TYPE_8197F(x)                                               \
+	(((x) >> BIT_SHIFT_UD_TYPE_8197F) & BIT_MASK_UD_TYPE_8197F)
+#define BIT_SET_UD_TYPE_8197F(x, v)                                            \
+	(BIT_CLEAR_UD_TYPE_8197F(x) | BIT_UD_TYPE_8197F(v))
+
+#define BIT_SHIFT_RPT_COUNTER_8197F 0
+#define BIT_MASK_RPT_COUNTER_8197F 0xffff
+#define BIT_RPT_COUNTER_8197F(x)                                               \
+	(((x) & BIT_MASK_RPT_COUNTER_8197F) << BIT_SHIFT_RPT_COUNTER_8197F)
+#define BITS_RPT_COUNTER_8197F                                                 \
+	(BIT_MASK_RPT_COUNTER_8197F << BIT_SHIFT_RPT_COUNTER_8197F)
+#define BIT_CLEAR_RPT_COUNTER_8197F(x) ((x) & (~BITS_RPT_COUNTER_8197F))
+#define BIT_GET_RPT_COUNTER_8197F(x)                                           \
+	(((x) >> BIT_SHIFT_RPT_COUNTER_8197F) & BIT_MASK_RPT_COUNTER_8197F)
+#define BIT_SET_RPT_COUNTER_8197F(x, v)                                        \
+	(BIT_CLEAR_RPT_COUNTER_8197F(x) | BIT_RPT_COUNTER_8197F(v))
+
+/* 2 REG_WMAC_TRXPTCL_CTL_8197F (WMAC TX/RX PROTOCOL CONTROL REGISTER) */
+
+#define BIT_SHIFT_ACKBA_TYPSEL_8197F (60 & CPU_OPT_WIDTH)
+#define BIT_MASK_ACKBA_TYPSEL_8197F 0xf
+#define BIT_ACKBA_TYPSEL_8197F(x)                                              \
+	(((x) & BIT_MASK_ACKBA_TYPSEL_8197F) << BIT_SHIFT_ACKBA_TYPSEL_8197F)
+#define BITS_ACKBA_TYPSEL_8197F                                                \
+	(BIT_MASK_ACKBA_TYPSEL_8197F << BIT_SHIFT_ACKBA_TYPSEL_8197F)
+#define BIT_CLEAR_ACKBA_TYPSEL_8197F(x) ((x) & (~BITS_ACKBA_TYPSEL_8197F))
+#define BIT_GET_ACKBA_TYPSEL_8197F(x)                                          \
+	(((x) >> BIT_SHIFT_ACKBA_TYPSEL_8197F) & BIT_MASK_ACKBA_TYPSEL_8197F)
+#define BIT_SET_ACKBA_TYPSEL_8197F(x, v)                                       \
+	(BIT_CLEAR_ACKBA_TYPSEL_8197F(x) | BIT_ACKBA_TYPSEL_8197F(v))
+
+#define BIT_SHIFT_ACKBA_ACKPCHK_8197F (56 & CPU_OPT_WIDTH)
+#define BIT_MASK_ACKBA_ACKPCHK_8197F 0xf
+#define BIT_ACKBA_ACKPCHK_8197F(x)                                             \
+	(((x) & BIT_MASK_ACKBA_ACKPCHK_8197F) << BIT_SHIFT_ACKBA_ACKPCHK_8197F)
+#define BITS_ACKBA_ACKPCHK_8197F                                               \
+	(BIT_MASK_ACKBA_ACKPCHK_8197F << BIT_SHIFT_ACKBA_ACKPCHK_8197F)
+#define BIT_CLEAR_ACKBA_ACKPCHK_8197F(x) ((x) & (~BITS_ACKBA_ACKPCHK_8197F))
+#define BIT_GET_ACKBA_ACKPCHK_8197F(x)                                         \
+	(((x) >> BIT_SHIFT_ACKBA_ACKPCHK_8197F) & BIT_MASK_ACKBA_ACKPCHK_8197F)
+#define BIT_SET_ACKBA_ACKPCHK_8197F(x, v)                                      \
+	(BIT_CLEAR_ACKBA_ACKPCHK_8197F(x) | BIT_ACKBA_ACKPCHK_8197F(v))
+
+#define BIT_SHIFT_ACKBAR_TYPESEL_8197F (48 & CPU_OPT_WIDTH)
+#define BIT_MASK_ACKBAR_TYPESEL_8197F 0xff
+#define BIT_ACKBAR_TYPESEL_8197F(x)                                            \
+	(((x) & BIT_MASK_ACKBAR_TYPESEL_8197F)                                 \
+	 << BIT_SHIFT_ACKBAR_TYPESEL_8197F)
+#define BITS_ACKBAR_TYPESEL_8197F                                              \
+	(BIT_MASK_ACKBAR_TYPESEL_8197F << BIT_SHIFT_ACKBAR_TYPESEL_8197F)
+#define BIT_CLEAR_ACKBAR_TYPESEL_8197F(x) ((x) & (~BITS_ACKBAR_TYPESEL_8197F))
+#define BIT_GET_ACKBAR_TYPESEL_8197F(x)                                        \
+	(((x) >> BIT_SHIFT_ACKBAR_TYPESEL_8197F) &                             \
+	 BIT_MASK_ACKBAR_TYPESEL_8197F)
+#define BIT_SET_ACKBAR_TYPESEL_8197F(x, v)                                     \
+	(BIT_CLEAR_ACKBAR_TYPESEL_8197F(x) | BIT_ACKBAR_TYPESEL_8197F(v))
+
+#define BIT_SHIFT_ACKBAR_ACKPCHK_8197F (44 & CPU_OPT_WIDTH)
+#define BIT_MASK_ACKBAR_ACKPCHK_8197F 0xf
+#define BIT_ACKBAR_ACKPCHK_8197F(x)                                            \
+	(((x) & BIT_MASK_ACKBAR_ACKPCHK_8197F)                                 \
+	 << BIT_SHIFT_ACKBAR_ACKPCHK_8197F)
+#define BITS_ACKBAR_ACKPCHK_8197F                                              \
+	(BIT_MASK_ACKBAR_ACKPCHK_8197F << BIT_SHIFT_ACKBAR_ACKPCHK_8197F)
+#define BIT_CLEAR_ACKBAR_ACKPCHK_8197F(x) ((x) & (~BITS_ACKBAR_ACKPCHK_8197F))
+#define BIT_GET_ACKBAR_ACKPCHK_8197F(x)                                        \
+	(((x) >> BIT_SHIFT_ACKBAR_ACKPCHK_8197F) &                             \
+	 BIT_MASK_ACKBAR_ACKPCHK_8197F)
+#define BIT_SET_ACKBAR_ACKPCHK_8197F(x, v)                                     \
+	(BIT_CLEAR_ACKBAR_ACKPCHK_8197F(x) | BIT_ACKBAR_ACKPCHK_8197F(v))
+
+#define BIT_RXBA_IGNOREA2_8197F BIT(42)
+#define BIT_EN_SAVE_ALL_TXOPADDR_8197F BIT(41)
+#define BIT_EN_TXCTS_TO_TXOPOWNER_INRXNAV_8197F BIT(40)
+#define BIT_DIS_TXBA_AMPDUFCSERR_8197F BIT(39)
+#define BIT_DIS_TXBA_RXBARINFULL_8197F BIT(38)
+#define BIT_DIS_TXCFE_INFULL_8197F BIT(37)
+#define BIT_DIS_TXCTS_INFULL_8197F BIT(36)
+#define BIT_EN_TXACKBA_IN_TX_RDG_8197F BIT(35)
+#define BIT_EN_TXACKBA_IN_TXOP_8197F BIT(34)
+#define BIT_EN_TXCTS_IN_RXNAV_8197F BIT(33)
+#define BIT_EN_TXCTS_INTXOP_8197F BIT(32)
+#define BIT_BLK_EDCA_BBSLP_8197F BIT(31)
+#define BIT_BLK_EDCA_BBSBY_8197F BIT(30)
+#define BIT_ACKTO_BLOCK_SCH_EN_8197F BIT(27)
+#define BIT_EIFS_BLOCK_SCH_EN_8197F BIT(26)
+#define BIT_PLCPCHK_RST_EIFS_8197F BIT(25)
+#define BIT_CCA_RST_EIFS_8197F BIT(24)
+#define BIT_DIS_UPD_MYRXPKTNAV_8197F BIT(23)
+#define BIT_EARLY_TXBA_8197F BIT(22)
+
+#define BIT_SHIFT_RESP_CHNBUSY_8197F 20
+#define BIT_MASK_RESP_CHNBUSY_8197F 0x3
+#define BIT_RESP_CHNBUSY_8197F(x)                                              \
+	(((x) & BIT_MASK_RESP_CHNBUSY_8197F) << BIT_SHIFT_RESP_CHNBUSY_8197F)
+#define BITS_RESP_CHNBUSY_8197F                                                \
+	(BIT_MASK_RESP_CHNBUSY_8197F << BIT_SHIFT_RESP_CHNBUSY_8197F)
+#define BIT_CLEAR_RESP_CHNBUSY_8197F(x) ((x) & (~BITS_RESP_CHNBUSY_8197F))
+#define BIT_GET_RESP_CHNBUSY_8197F(x)                                          \
+	(((x) >> BIT_SHIFT_RESP_CHNBUSY_8197F) & BIT_MASK_RESP_CHNBUSY_8197F)
+#define BIT_SET_RESP_CHNBUSY_8197F(x, v)                                       \
+	(BIT_CLEAR_RESP_CHNBUSY_8197F(x) | BIT_RESP_CHNBUSY_8197F(v))
+
+#define BIT_RESP_DCTS_EN_8197F BIT(19)
+#define BIT_RESP_DCFE_EN_8197F BIT(18)
+#define BIT_RESP_SPLCPEN_8197F BIT(17)
+#define BIT_RESP_SGIEN_8197F BIT(16)
+#define BIT_RESP_LDPC_EN_8197F BIT(15)
+#define BIT_DIS_RESP_ACKINCCA_8197F BIT(14)
+#define BIT_DIS_RESP_CTSINCCA_8197F BIT(13)
+
+#define BIT_SHIFT_R_WMAC_SECOND_CCA_TIMER_8197F 10
+#define BIT_MASK_R_WMAC_SECOND_CCA_TIMER_8197F 0x7
+#define BIT_R_WMAC_SECOND_CCA_TIMER_8197F(x)                                   \
+	(((x) & BIT_MASK_R_WMAC_SECOND_CCA_TIMER_8197F)                        \
+	 << BIT_SHIFT_R_WMAC_SECOND_CCA_TIMER_8197F)
+#define BITS_R_WMAC_SECOND_CCA_TIMER_8197F                                     \
+	(BIT_MASK_R_WMAC_SECOND_CCA_TIMER_8197F                                \
+	 << BIT_SHIFT_R_WMAC_SECOND_CCA_TIMER_8197F)
+#define BIT_CLEAR_R_WMAC_SECOND_CCA_TIMER_8197F(x)                             \
+	((x) & (~BITS_R_WMAC_SECOND_CCA_TIMER_8197F))
+#define BIT_GET_R_WMAC_SECOND_CCA_TIMER_8197F(x)                               \
+	(((x) >> BIT_SHIFT_R_WMAC_SECOND_CCA_TIMER_8197F) &                    \
+	 BIT_MASK_R_WMAC_SECOND_CCA_TIMER_8197F)
+#define BIT_SET_R_WMAC_SECOND_CCA_TIMER_8197F(x, v)                            \
+	(BIT_CLEAR_R_WMAC_SECOND_CCA_TIMER_8197F(x) |                          \
+	 BIT_R_WMAC_SECOND_CCA_TIMER_8197F(v))
+
+#define BIT_SHIFT_RFMOD_8197F 7
+#define BIT_MASK_RFMOD_8197F 0x3
+#define BIT_RFMOD_8197F(x)                                                     \
+	(((x) & BIT_MASK_RFMOD_8197F) << BIT_SHIFT_RFMOD_8197F)
+#define BITS_RFMOD_8197F (BIT_MASK_RFMOD_8197F << BIT_SHIFT_RFMOD_8197F)
+#define BIT_CLEAR_RFMOD_8197F(x) ((x) & (~BITS_RFMOD_8197F))
+#define BIT_GET_RFMOD_8197F(x)                                                 \
+	(((x) >> BIT_SHIFT_RFMOD_8197F) & BIT_MASK_RFMOD_8197F)
+#define BIT_SET_RFMOD_8197F(x, v)                                              \
+	(BIT_CLEAR_RFMOD_8197F(x) | BIT_RFMOD_8197F(v))
+
+#define BIT_SHIFT_RESP_CTS_DYNBW_SEL_8197F 5
+#define BIT_MASK_RESP_CTS_DYNBW_SEL_8197F 0x3
+#define BIT_RESP_CTS_DYNBW_SEL_8197F(x)                                        \
+	(((x) & BIT_MASK_RESP_CTS_DYNBW_SEL_8197F)                             \
+	 << BIT_SHIFT_RESP_CTS_DYNBW_SEL_8197F)
+#define BITS_RESP_CTS_DYNBW_SEL_8197F                                          \
+	(BIT_MASK_RESP_CTS_DYNBW_SEL_8197F                                     \
+	 << BIT_SHIFT_RESP_CTS_DYNBW_SEL_8197F)
+#define BIT_CLEAR_RESP_CTS_DYNBW_SEL_8197F(x)                                  \
+	((x) & (~BITS_RESP_CTS_DYNBW_SEL_8197F))
+#define BIT_GET_RESP_CTS_DYNBW_SEL_8197F(x)                                    \
+	(((x) >> BIT_SHIFT_RESP_CTS_DYNBW_SEL_8197F) &                         \
+	 BIT_MASK_RESP_CTS_DYNBW_SEL_8197F)
+#define BIT_SET_RESP_CTS_DYNBW_SEL_8197F(x, v)                                 \
+	(BIT_CLEAR_RESP_CTS_DYNBW_SEL_8197F(x) |                               \
+	 BIT_RESP_CTS_DYNBW_SEL_8197F(v))
+
+#define BIT_DLY_TX_WAIT_RXANTSEL_8197F BIT(4)
+#define BIT_TXRESP_BY_RXANTSEL_8197F BIT(3)
+
+#define BIT_SHIFT_ORIG_DCTS_CHK_8197F 0
+#define BIT_MASK_ORIG_DCTS_CHK_8197F 0x3
+#define BIT_ORIG_DCTS_CHK_8197F(x)                                             \
+	(((x) & BIT_MASK_ORIG_DCTS_CHK_8197F) << BIT_SHIFT_ORIG_DCTS_CHK_8197F)
+#define BITS_ORIG_DCTS_CHK_8197F                                               \
+	(BIT_MASK_ORIG_DCTS_CHK_8197F << BIT_SHIFT_ORIG_DCTS_CHK_8197F)
+#define BIT_CLEAR_ORIG_DCTS_CHK_8197F(x) ((x) & (~BITS_ORIG_DCTS_CHK_8197F))
+#define BIT_GET_ORIG_DCTS_CHK_8197F(x)                                         \
+	(((x) >> BIT_SHIFT_ORIG_DCTS_CHK_8197F) & BIT_MASK_ORIG_DCTS_CHK_8197F)
+#define BIT_SET_ORIG_DCTS_CHK_8197F(x, v)                                      \
+	(BIT_CLEAR_ORIG_DCTS_CHK_8197F(x) | BIT_ORIG_DCTS_CHK_8197F(v))
+
+/* 2 REG_CAMCMD_8197F (CAM COMMAND REGISTER) */
+#define BIT_SECCAM_POLLING_8197F BIT(31)
+#define BIT_SECCAM_CLR_8197F BIT(30)
+#define BIT_MFBCAM_CLR_8197F BIT(29)
+#define BIT_SECCAM_WE_8197F BIT(16)
+
+#define BIT_SHIFT_SECCAM_ADDR_V2_8197F 0
+#define BIT_MASK_SECCAM_ADDR_V2_8197F 0x3ff
+#define BIT_SECCAM_ADDR_V2_8197F(x)                                            \
+	(((x) & BIT_MASK_SECCAM_ADDR_V2_8197F)                                 \
+	 << BIT_SHIFT_SECCAM_ADDR_V2_8197F)
+#define BITS_SECCAM_ADDR_V2_8197F                                              \
+	(BIT_MASK_SECCAM_ADDR_V2_8197F << BIT_SHIFT_SECCAM_ADDR_V2_8197F)
+#define BIT_CLEAR_SECCAM_ADDR_V2_8197F(x) ((x) & (~BITS_SECCAM_ADDR_V2_8197F))
+#define BIT_GET_SECCAM_ADDR_V2_8197F(x)                                        \
+	(((x) >> BIT_SHIFT_SECCAM_ADDR_V2_8197F) &                             \
+	 BIT_MASK_SECCAM_ADDR_V2_8197F)
+#define BIT_SET_SECCAM_ADDR_V2_8197F(x, v)                                     \
+	(BIT_CLEAR_SECCAM_ADDR_V2_8197F(x) | BIT_SECCAM_ADDR_V2_8197F(v))
+
+/* 2 REG_CAMWRITE_8197F (CAM WRITE REGISTER) */
+
+#define BIT_SHIFT_CAMW_DATA_8197F 0
+#define BIT_MASK_CAMW_DATA_8197F 0xffffffffL
+#define BIT_CAMW_DATA_8197F(x)                                                 \
+	(((x) & BIT_MASK_CAMW_DATA_8197F) << BIT_SHIFT_CAMW_DATA_8197F)
+#define BITS_CAMW_DATA_8197F                                                   \
+	(BIT_MASK_CAMW_DATA_8197F << BIT_SHIFT_CAMW_DATA_8197F)
+#define BIT_CLEAR_CAMW_DATA_8197F(x) ((x) & (~BITS_CAMW_DATA_8197F))
+#define BIT_GET_CAMW_DATA_8197F(x)                                             \
+	(((x) >> BIT_SHIFT_CAMW_DATA_8197F) & BIT_MASK_CAMW_DATA_8197F)
+#define BIT_SET_CAMW_DATA_8197F(x, v)                                          \
+	(BIT_CLEAR_CAMW_DATA_8197F(x) | BIT_CAMW_DATA_8197F(v))
+
+/* 2 REG_CAMREAD_8197F (CAM READ REGISTER) */
+
+#define BIT_SHIFT_CAMR_DATA_8197F 0
+#define BIT_MASK_CAMR_DATA_8197F 0xffffffffL
+#define BIT_CAMR_DATA_8197F(x)                                                 \
+	(((x) & BIT_MASK_CAMR_DATA_8197F) << BIT_SHIFT_CAMR_DATA_8197F)
+#define BITS_CAMR_DATA_8197F                                                   \
+	(BIT_MASK_CAMR_DATA_8197F << BIT_SHIFT_CAMR_DATA_8197F)
+#define BIT_CLEAR_CAMR_DATA_8197F(x) ((x) & (~BITS_CAMR_DATA_8197F))
+#define BIT_GET_CAMR_DATA_8197F(x)                                             \
+	(((x) >> BIT_SHIFT_CAMR_DATA_8197F) & BIT_MASK_CAMR_DATA_8197F)
+#define BIT_SET_CAMR_DATA_8197F(x, v)                                          \
+	(BIT_CLEAR_CAMR_DATA_8197F(x) | BIT_CAMR_DATA_8197F(v))
+
+/* 2 REG_CAMDBG_8197F (CAM DEBUG REGISTER) */
+#define BIT_SECCAM_INFO_8197F BIT(31)
+#define BIT_SEC_KEYFOUND_8197F BIT(15)
+
+#define BIT_SHIFT_CAMDBG_SEC_TYPE_8197F 12
+#define BIT_MASK_CAMDBG_SEC_TYPE_8197F 0x7
+#define BIT_CAMDBG_SEC_TYPE_8197F(x)                                           \
+	(((x) & BIT_MASK_CAMDBG_SEC_TYPE_8197F)                                \
+	 << BIT_SHIFT_CAMDBG_SEC_TYPE_8197F)
+#define BITS_CAMDBG_SEC_TYPE_8197F                                             \
+	(BIT_MASK_CAMDBG_SEC_TYPE_8197F << BIT_SHIFT_CAMDBG_SEC_TYPE_8197F)
+#define BIT_CLEAR_CAMDBG_SEC_TYPE_8197F(x) ((x) & (~BITS_CAMDBG_SEC_TYPE_8197F))
+#define BIT_GET_CAMDBG_SEC_TYPE_8197F(x)                                       \
+	(((x) >> BIT_SHIFT_CAMDBG_SEC_TYPE_8197F) &                            \
+	 BIT_MASK_CAMDBG_SEC_TYPE_8197F)
+#define BIT_SET_CAMDBG_SEC_TYPE_8197F(x, v)                                    \
+	(BIT_CLEAR_CAMDBG_SEC_TYPE_8197F(x) | BIT_CAMDBG_SEC_TYPE_8197F(v))
+
+#define BIT_CAMDBG_EXT_SEC_TYPE_8197F BIT(11)
+
+#define BIT_SHIFT_CAMDBG_MIC_KEY_IDX_8197F 5
+#define BIT_MASK_CAMDBG_MIC_KEY_IDX_8197F 0x1f
+#define BIT_CAMDBG_MIC_KEY_IDX_8197F(x)                                        \
+	(((x) & BIT_MASK_CAMDBG_MIC_KEY_IDX_8197F)                             \
+	 << BIT_SHIFT_CAMDBG_MIC_KEY_IDX_8197F)
+#define BITS_CAMDBG_MIC_KEY_IDX_8197F                                          \
+	(BIT_MASK_CAMDBG_MIC_KEY_IDX_8197F                                     \
+	 << BIT_SHIFT_CAMDBG_MIC_KEY_IDX_8197F)
+#define BIT_CLEAR_CAMDBG_MIC_KEY_IDX_8197F(x)                                  \
+	((x) & (~BITS_CAMDBG_MIC_KEY_IDX_8197F))
+#define BIT_GET_CAMDBG_MIC_KEY_IDX_8197F(x)                                    \
+	(((x) >> BIT_SHIFT_CAMDBG_MIC_KEY_IDX_8197F) &                         \
+	 BIT_MASK_CAMDBG_MIC_KEY_IDX_8197F)
+#define BIT_SET_CAMDBG_MIC_KEY_IDX_8197F(x, v)                                 \
+	(BIT_CLEAR_CAMDBG_MIC_KEY_IDX_8197F(x) |                               \
+	 BIT_CAMDBG_MIC_KEY_IDX_8197F(v))
+
+#define BIT_SHIFT_CAMDBG_SEC_KEY_IDX_8197F 0
+#define BIT_MASK_CAMDBG_SEC_KEY_IDX_8197F 0x1f
+#define BIT_CAMDBG_SEC_KEY_IDX_8197F(x)                                        \
+	(((x) & BIT_MASK_CAMDBG_SEC_KEY_IDX_8197F)                             \
+	 << BIT_SHIFT_CAMDBG_SEC_KEY_IDX_8197F)
+#define BITS_CAMDBG_SEC_KEY_IDX_8197F                                          \
+	(BIT_MASK_CAMDBG_SEC_KEY_IDX_8197F                                     \
+	 << BIT_SHIFT_CAMDBG_SEC_KEY_IDX_8197F)
+#define BIT_CLEAR_CAMDBG_SEC_KEY_IDX_8197F(x)                                  \
+	((x) & (~BITS_CAMDBG_SEC_KEY_IDX_8197F))
+#define BIT_GET_CAMDBG_SEC_KEY_IDX_8197F(x)                                    \
+	(((x) >> BIT_SHIFT_CAMDBG_SEC_KEY_IDX_8197F) &                         \
+	 BIT_MASK_CAMDBG_SEC_KEY_IDX_8197F)
+#define BIT_SET_CAMDBG_SEC_KEY_IDX_8197F(x, v)                                 \
+	(BIT_CLEAR_CAMDBG_SEC_KEY_IDX_8197F(x) |                               \
+	 BIT_CAMDBG_SEC_KEY_IDX_8197F(v))
+
+/* 2 REG_RXFILTER_ACTION_1_8197F */
+
+#define BIT_SHIFT_RXFILTER_ACTION_1_8197F 0
+#define BIT_MASK_RXFILTER_ACTION_1_8197F 0xff
+#define BIT_RXFILTER_ACTION_1_8197F(x)                                         \
+	(((x) & BIT_MASK_RXFILTER_ACTION_1_8197F)                              \
+	 << BIT_SHIFT_RXFILTER_ACTION_1_8197F)
+#define BITS_RXFILTER_ACTION_1_8197F                                           \
+	(BIT_MASK_RXFILTER_ACTION_1_8197F << BIT_SHIFT_RXFILTER_ACTION_1_8197F)
+#define BIT_CLEAR_RXFILTER_ACTION_1_8197F(x)                                   \
+	((x) & (~BITS_RXFILTER_ACTION_1_8197F))
+#define BIT_GET_RXFILTER_ACTION_1_8197F(x)                                     \
+	(((x) >> BIT_SHIFT_RXFILTER_ACTION_1_8197F) &                          \
+	 BIT_MASK_RXFILTER_ACTION_1_8197F)
+#define BIT_SET_RXFILTER_ACTION_1_8197F(x, v)                                  \
+	(BIT_CLEAR_RXFILTER_ACTION_1_8197F(x) | BIT_RXFILTER_ACTION_1_8197F(v))
+
+/* 2 REG_RXFILTER_CATEGORY_1_8197F */
+
+#define BIT_SHIFT_RXFILTER_CATEGORY_1_8197F 0
+#define BIT_MASK_RXFILTER_CATEGORY_1_8197F 0xff
+#define BIT_RXFILTER_CATEGORY_1_8197F(x)                                       \
+	(((x) & BIT_MASK_RXFILTER_CATEGORY_1_8197F)                            \
+	 << BIT_SHIFT_RXFILTER_CATEGORY_1_8197F)
+#define BITS_RXFILTER_CATEGORY_1_8197F                                         \
+	(BIT_MASK_RXFILTER_CATEGORY_1_8197F                                    \
+	 << BIT_SHIFT_RXFILTER_CATEGORY_1_8197F)
+#define BIT_CLEAR_RXFILTER_CATEGORY_1_8197F(x)                                 \
+	((x) & (~BITS_RXFILTER_CATEGORY_1_8197F))
+#define BIT_GET_RXFILTER_CATEGORY_1_8197F(x)                                   \
+	(((x) >> BIT_SHIFT_RXFILTER_CATEGORY_1_8197F) &                        \
+	 BIT_MASK_RXFILTER_CATEGORY_1_8197F)
+#define BIT_SET_RXFILTER_CATEGORY_1_8197F(x, v)                                \
+	(BIT_CLEAR_RXFILTER_CATEGORY_1_8197F(x) |                              \
+	 BIT_RXFILTER_CATEGORY_1_8197F(v))
+
+/* 2 REG_SECCFG_8197F (SECURITY CONFIGURATION REGISTER) */
+#define BIT_DIS_GCLK_WAPI_8197F BIT(15)
+#define BIT_DIS_GCLK_AES_8197F BIT(14)
+#define BIT_DIS_GCLK_TKIP_8197F BIT(13)
+#define BIT_AES_SEL_QC_1_8197F BIT(12)
+#define BIT_AES_SEL_QC_0_8197F BIT(11)
+#define BIT_WMAC_CKECK_BMC_8197F BIT(9)
+#define BIT_CHK_KEYID_8197F BIT(8)
+#define BIT_RXBCUSEDK_8197F BIT(7)
+#define BIT_TXBCUSEDK_8197F BIT(6)
+#define BIT_NOSKMC_8197F BIT(5)
+#define BIT_SKBYA2_8197F BIT(4)
+#define BIT_RXDEC_8197F BIT(3)
+#define BIT_TXENC_8197F BIT(2)
+#define BIT_RXUHUSEDK_8197F BIT(1)
+#define BIT_TXUHUSEDK_8197F BIT(0)
+
+/* 2 REG_RXFILTER_ACTION_3_8197F */
+
+#define BIT_SHIFT_RXFILTER_ACTION_3_8197F 0
+#define BIT_MASK_RXFILTER_ACTION_3_8197F 0xff
+#define BIT_RXFILTER_ACTION_3_8197F(x)                                         \
+	(((x) & BIT_MASK_RXFILTER_ACTION_3_8197F)                              \
+	 << BIT_SHIFT_RXFILTER_ACTION_3_8197F)
+#define BITS_RXFILTER_ACTION_3_8197F                                           \
+	(BIT_MASK_RXFILTER_ACTION_3_8197F << BIT_SHIFT_RXFILTER_ACTION_3_8197F)
+#define BIT_CLEAR_RXFILTER_ACTION_3_8197F(x)                                   \
+	((x) & (~BITS_RXFILTER_ACTION_3_8197F))
+#define BIT_GET_RXFILTER_ACTION_3_8197F(x)                                     \
+	(((x) >> BIT_SHIFT_RXFILTER_ACTION_3_8197F) &                          \
+	 BIT_MASK_RXFILTER_ACTION_3_8197F)
+#define BIT_SET_RXFILTER_ACTION_3_8197F(x, v)                                  \
+	(BIT_CLEAR_RXFILTER_ACTION_3_8197F(x) | BIT_RXFILTER_ACTION_3_8197F(v))
+
+/* 2 REG_RXFILTER_CATEGORY_3_8197F */
+
+#define BIT_SHIFT_RXFILTER_CATEGORY_3_8197F 0
+#define BIT_MASK_RXFILTER_CATEGORY_3_8197F 0xff
+#define BIT_RXFILTER_CATEGORY_3_8197F(x)                                       \
+	(((x) & BIT_MASK_RXFILTER_CATEGORY_3_8197F)                            \
+	 << BIT_SHIFT_RXFILTER_CATEGORY_3_8197F)
+#define BITS_RXFILTER_CATEGORY_3_8197F                                         \
+	(BIT_MASK_RXFILTER_CATEGORY_3_8197F                                    \
+	 << BIT_SHIFT_RXFILTER_CATEGORY_3_8197F)
+#define BIT_CLEAR_RXFILTER_CATEGORY_3_8197F(x)                                 \
+	((x) & (~BITS_RXFILTER_CATEGORY_3_8197F))
+#define BIT_GET_RXFILTER_CATEGORY_3_8197F(x)                                   \
+	(((x) >> BIT_SHIFT_RXFILTER_CATEGORY_3_8197F) &                        \
+	 BIT_MASK_RXFILTER_CATEGORY_3_8197F)
+#define BIT_SET_RXFILTER_CATEGORY_3_8197F(x, v)                                \
+	(BIT_CLEAR_RXFILTER_CATEGORY_3_8197F(x) |                              \
+	 BIT_RXFILTER_CATEGORY_3_8197F(v))
+
+/* 2 REG_RXFILTER_ACTION_2_8197F */
+
+#define BIT_SHIFT_RXFILTER_ACTION_2_8197F 0
+#define BIT_MASK_RXFILTER_ACTION_2_8197F 0xff
+#define BIT_RXFILTER_ACTION_2_8197F(x)                                         \
+	(((x) & BIT_MASK_RXFILTER_ACTION_2_8197F)                              \
+	 << BIT_SHIFT_RXFILTER_ACTION_2_8197F)
+#define BITS_RXFILTER_ACTION_2_8197F                                           \
+	(BIT_MASK_RXFILTER_ACTION_2_8197F << BIT_SHIFT_RXFILTER_ACTION_2_8197F)
+#define BIT_CLEAR_RXFILTER_ACTION_2_8197F(x)                                   \
+	((x) & (~BITS_RXFILTER_ACTION_2_8197F))
+#define BIT_GET_RXFILTER_ACTION_2_8197F(x)                                     \
+	(((x) >> BIT_SHIFT_RXFILTER_ACTION_2_8197F) &                          \
+	 BIT_MASK_RXFILTER_ACTION_2_8197F)
+#define BIT_SET_RXFILTER_ACTION_2_8197F(x, v)                                  \
+	(BIT_CLEAR_RXFILTER_ACTION_2_8197F(x) | BIT_RXFILTER_ACTION_2_8197F(v))
+
+/* 2 REG_RXFILTER_CATEGORY_2_8197F */
+
+#define BIT_SHIFT_RXFILTER_CATEGORY_2_8197F 0
+#define BIT_MASK_RXFILTER_CATEGORY_2_8197F 0xff
+#define BIT_RXFILTER_CATEGORY_2_8197F(x)                                       \
+	(((x) & BIT_MASK_RXFILTER_CATEGORY_2_8197F)                            \
+	 << BIT_SHIFT_RXFILTER_CATEGORY_2_8197F)
+#define BITS_RXFILTER_CATEGORY_2_8197F                                         \
+	(BIT_MASK_RXFILTER_CATEGORY_2_8197F                                    \
+	 << BIT_SHIFT_RXFILTER_CATEGORY_2_8197F)
+#define BIT_CLEAR_RXFILTER_CATEGORY_2_8197F(x)                                 \
+	((x) & (~BITS_RXFILTER_CATEGORY_2_8197F))
+#define BIT_GET_RXFILTER_CATEGORY_2_8197F(x)                                   \
+	(((x) >> BIT_SHIFT_RXFILTER_CATEGORY_2_8197F) &                        \
+	 BIT_MASK_RXFILTER_CATEGORY_2_8197F)
+#define BIT_SET_RXFILTER_CATEGORY_2_8197F(x, v)                                \
+	(BIT_CLEAR_RXFILTER_CATEGORY_2_8197F(x) |                              \
+	 BIT_RXFILTER_CATEGORY_2_8197F(v))
+
+/* 2 REG_RXFLTMAP4_8197F (RX FILTER MAP GROUP 4) */
+#define BIT_CTRLFLT15EN_FW_8197F BIT(15)
+#define BIT_CTRLFLT14EN_FW_8197F BIT(14)
+#define BIT_CTRLFLT13EN_FW_8197F BIT(13)
+#define BIT_CTRLFLT12EN_FW_8197F BIT(12)
+#define BIT_CTRLFLT11EN_FW_8197F BIT(11)
+#define BIT_CTRLFLT10EN_FW_8197F BIT(10)
+#define BIT_CTRLFLT9EN_FW_8197F BIT(9)
+#define BIT_CTRLFLT8EN_FW_8197F BIT(8)
+#define BIT_CTRLFLT7EN_FW_8197F BIT(7)
+#define BIT_CTRLFLT6EN_FW_8197F BIT(6)
+#define BIT_CTRLFLT5EN_FW_8197F BIT(5)
+#define BIT_CTRLFLT4EN_FW_8197F BIT(4)
+#define BIT_CTRLFLT3EN_FW_8197F BIT(3)
+#define BIT_CTRLFLT2EN_FW_8197F BIT(2)
+#define BIT_CTRLFLT1EN_FW_8197F BIT(1)
+#define BIT_CTRLFLT0EN_FW_8197F BIT(0)
+
+/* 2 REG_RXFLTMAP3_8197F (RX FILTER MAP GROUP 3) */
+#define BIT_MGTFLT15EN_FW_8197F BIT(15)
+#define BIT_MGTFLT14EN_FW_8197F BIT(14)
+#define BIT_MGTFLT13EN_FW_8197F BIT(13)
+#define BIT_MGTFLT12EN_FW_8197F BIT(12)
+#define BIT_MGTFLT11EN_FW_8197F BIT(11)
+#define BIT_MGTFLT10EN_FW_8197F BIT(10)
+#define BIT_MGTFLT9EN_FW_8197F BIT(9)
+#define BIT_MGTFLT8EN_FW_8197F BIT(8)
+#define BIT_MGTFLT7EN_FW_8197F BIT(7)
+#define BIT_MGTFLT6EN_FW_8197F BIT(6)
+#define BIT_MGTFLT5EN_FW_8197F BIT(5)
+#define BIT_MGTFLT4EN_FW_8197F BIT(4)
+#define BIT_MGTFLT3EN_FW_8197F BIT(3)
+#define BIT_MGTFLT2EN_FW_8197F BIT(2)
+#define BIT_MGTFLT1EN_FW_8197F BIT(1)
+#define BIT_MGTFLT0EN_FW_8197F BIT(0)
+
+/* 2 REG_RXFLTMAP6_8197F (RX FILTER MAP GROUP 3) */
+#define BIT_ACTIONFLT15EN_FW_8197F BIT(15)
+#define BIT_ACTIONFLT14EN_FW_8197F BIT(14)
+#define BIT_ACTIONFLT13EN_FW_8197F BIT(13)
+#define BIT_ACTIONFLT12EN_FW_8197F BIT(12)
+#define BIT_ACTIONFLT11EN_FW_8197F BIT(11)
+#define BIT_ACTIONFLT10EN_FW_8197F BIT(10)
+#define BIT_ACTIONFLT9EN_FW_8197F BIT(9)
+#define BIT_ACTIONFLT8EN_FW_8197F BIT(8)
+#define BIT_ACTIONFLT7EN_FW_8197F BIT(7)
+#define BIT_ACTIONFLT6EN_FW_8197F BIT(6)
+#define BIT_ACTIONFLT5EN_FW_8197F BIT(5)
+#define BIT_ACTIONFLT4EN_FW_8197F BIT(4)
+#define BIT_ACTIONFLT3EN_FW_8197F BIT(3)
+#define BIT_ACTIONFLT2EN_FW_8197F BIT(2)
+#define BIT_ACTIONFLT1EN_FW_8197F BIT(1)
+#define BIT_ACTIONFLT0EN_FW_8197F BIT(0)
+
+/* 2 REG_RXFLTMAP5_8197F (RX FILTER MAP GROUP 3) */
+#define BIT_DATAFLT15EN_FW_8197F BIT(15)
+#define BIT_DATAFLT14EN_FW_8197F BIT(14)
+#define BIT_DATAFLT13EN_FW_8197F BIT(13)
+#define BIT_DATAFLT12EN_FW_8197F BIT(12)
+#define BIT_DATAFLT11EN_FW_8197F BIT(11)
+#define BIT_DATAFLT10EN_FW_8197F BIT(10)
+#define BIT_DATAFLT9EN_FW_8197F BIT(9)
+#define BIT_DATAFLT8EN_FW_8197F BIT(8)
+#define BIT_DATAFLT7EN_FW_8197F BIT(7)
+#define BIT_DATAFLT6EN_FW_8197F BIT(6)
+#define BIT_DATAFLT5EN_FW_8197F BIT(5)
+#define BIT_DATAFLT4EN_FW_8197F BIT(4)
+#define BIT_DATAFLT3EN_FW_8197F BIT(3)
+#define BIT_DATAFLT2EN_FW_8197F BIT(2)
+#define BIT_DATAFLT1EN_FW_8197F BIT(1)
+#define BIT_DATAFLT0EN_FW_8197F BIT(0)
+
+/* 2 REG_WMMPS_UAPSD_TID_8197F (WMM POWER SAVE UAPSD TID REGISTER) */
+#define BIT_WMMPS_UAPSD_TID7_8197F BIT(7)
+#define BIT_WMMPS_UAPSD_TID6_8197F BIT(6)
+#define BIT_WMMPS_UAPSD_TID5_8197F BIT(5)
+#define BIT_WMMPS_UAPSD_TID4_8197F BIT(4)
+#define BIT_WMMPS_UAPSD_TID3_8197F BIT(3)
+#define BIT_WMMPS_UAPSD_TID2_8197F BIT(2)
+#define BIT_WMMPS_UAPSD_TID1_8197F BIT(1)
+#define BIT_WMMPS_UAPSD_TID0_8197F BIT(0)
+
+/* 2 REG_PS_RX_INFO_8197F (POWER SAVE RX INFORMATION REGISTER) */
+
+#define BIT_SHIFT_PORTSEL__PS_RX_INFO_8197F 5
+#define BIT_MASK_PORTSEL__PS_RX_INFO_8197F 0x7
+#define BIT_PORTSEL__PS_RX_INFO_8197F(x)                                       \
+	(((x) & BIT_MASK_PORTSEL__PS_RX_INFO_8197F)                            \
+	 << BIT_SHIFT_PORTSEL__PS_RX_INFO_8197F)
+#define BITS_PORTSEL__PS_RX_INFO_8197F                                         \
+	(BIT_MASK_PORTSEL__PS_RX_INFO_8197F                                    \
+	 << BIT_SHIFT_PORTSEL__PS_RX_INFO_8197F)
+#define BIT_CLEAR_PORTSEL__PS_RX_INFO_8197F(x)                                 \
+	((x) & (~BITS_PORTSEL__PS_RX_INFO_8197F))
+#define BIT_GET_PORTSEL__PS_RX_INFO_8197F(x)                                   \
+	(((x) >> BIT_SHIFT_PORTSEL__PS_RX_INFO_8197F) &                        \
+	 BIT_MASK_PORTSEL__PS_RX_INFO_8197F)
+#define BIT_SET_PORTSEL__PS_RX_INFO_8197F(x, v)                                \
+	(BIT_CLEAR_PORTSEL__PS_RX_INFO_8197F(x) |                              \
+	 BIT_PORTSEL__PS_RX_INFO_8197F(v))
+
+#define BIT_RXCTRLIN0_8197F BIT(4)
+#define BIT_RXMGTIN0_8197F BIT(3)
+#define BIT_RXDATAIN2_8197F BIT(2)
+#define BIT_RXDATAIN1_8197F BIT(1)
+#define BIT_RXDATAIN0_8197F BIT(0)
+
+/* 2 REG_NOT_VALID_8197F */
+#define BIT_CHK_TSF_TA_8197F BIT(2)
+#define BIT_CHK_TSF_CBSSID_8197F BIT(1)
+#define BIT_CHK_TSF_EN_8197F BIT(0)
+
+/* 2 REG_WOW_CTRL_8197F (WAKE ON WLAN CONTROL REGISTER) */
+
+#define BIT_SHIFT_PSF_BSSIDSEL_B2B1_8197F 6
+#define BIT_MASK_PSF_BSSIDSEL_B2B1_8197F 0x3
+#define BIT_PSF_BSSIDSEL_B2B1_8197F(x)                                         \
+	(((x) & BIT_MASK_PSF_BSSIDSEL_B2B1_8197F)                              \
+	 << BIT_SHIFT_PSF_BSSIDSEL_B2B1_8197F)
+#define BITS_PSF_BSSIDSEL_B2B1_8197F                                           \
+	(BIT_MASK_PSF_BSSIDSEL_B2B1_8197F << BIT_SHIFT_PSF_BSSIDSEL_B2B1_8197F)
+#define BIT_CLEAR_PSF_BSSIDSEL_B2B1_8197F(x)                                   \
+	((x) & (~BITS_PSF_BSSIDSEL_B2B1_8197F))
+#define BIT_GET_PSF_BSSIDSEL_B2B1_8197F(x)                                     \
+	(((x) >> BIT_SHIFT_PSF_BSSIDSEL_B2B1_8197F) &                          \
+	 BIT_MASK_PSF_BSSIDSEL_B2B1_8197F)
+#define BIT_SET_PSF_BSSIDSEL_B2B1_8197F(x, v)                                  \
+	(BIT_CLEAR_PSF_BSSIDSEL_B2B1_8197F(x) | BIT_PSF_BSSIDSEL_B2B1_8197F(v))
+
+#define BIT_WOWHCI_8197F BIT(5)
+#define BIT_PSF_BSSIDSEL_B0_8197F BIT(4)
+#define BIT_UWF_8197F BIT(3)
+#define BIT_MAGIC_8197F BIT(2)
+#define BIT_WOWEN_8197F BIT(1)
+#define BIT_FORCE_WAKEUP_8197F BIT(0)
+
+/* 2 REG_LPNAV_CTRL_8197F (LOW POWER NAV CONTROL REGISTER) */
+#define BIT_LPNAV_EN_8197F BIT(31)
+
+#define BIT_SHIFT_LPNAV_EARLY_8197F 16
+#define BIT_MASK_LPNAV_EARLY_8197F 0x7fff
+#define BIT_LPNAV_EARLY_8197F(x)                                               \
+	(((x) & BIT_MASK_LPNAV_EARLY_8197F) << BIT_SHIFT_LPNAV_EARLY_8197F)
+#define BITS_LPNAV_EARLY_8197F                                                 \
+	(BIT_MASK_LPNAV_EARLY_8197F << BIT_SHIFT_LPNAV_EARLY_8197F)
+#define BIT_CLEAR_LPNAV_EARLY_8197F(x) ((x) & (~BITS_LPNAV_EARLY_8197F))
+#define BIT_GET_LPNAV_EARLY_8197F(x)                                           \
+	(((x) >> BIT_SHIFT_LPNAV_EARLY_8197F) & BIT_MASK_LPNAV_EARLY_8197F)
+#define BIT_SET_LPNAV_EARLY_8197F(x, v)                                        \
+	(BIT_CLEAR_LPNAV_EARLY_8197F(x) | BIT_LPNAV_EARLY_8197F(v))
+
+#define BIT_SHIFT_LPNAV_TH_8197F 0
+#define BIT_MASK_LPNAV_TH_8197F 0xffff
+#define BIT_LPNAV_TH_8197F(x)                                                  \
+	(((x) & BIT_MASK_LPNAV_TH_8197F) << BIT_SHIFT_LPNAV_TH_8197F)
+#define BITS_LPNAV_TH_8197F                                                    \
+	(BIT_MASK_LPNAV_TH_8197F << BIT_SHIFT_LPNAV_TH_8197F)
+#define BIT_CLEAR_LPNAV_TH_8197F(x) ((x) & (~BITS_LPNAV_TH_8197F))
+#define BIT_GET_LPNAV_TH_8197F(x)                                              \
+	(((x) >> BIT_SHIFT_LPNAV_TH_8197F) & BIT_MASK_LPNAV_TH_8197F)
+#define BIT_SET_LPNAV_TH_8197F(x, v)                                           \
+	(BIT_CLEAR_LPNAV_TH_8197F(x) | BIT_LPNAV_TH_8197F(v))
+
+/* 2 REG_WKFMCAM_CMD_8197F (WAKEUP FRAME CAM COMMAND REGISTER) */
+#define BIT_WKFCAM_POLLING_V1_8197F BIT(31)
+#define BIT_WKFCAM_CLR_V1_8197F BIT(30)
+#define BIT_WKFCAM_WE_8197F BIT(16)
+
+#define BIT_SHIFT_WKFCAM_ADDR_V2_8197F 8
+#define BIT_MASK_WKFCAM_ADDR_V2_8197F 0xff
+#define BIT_WKFCAM_ADDR_V2_8197F(x)                                            \
+	(((x) & BIT_MASK_WKFCAM_ADDR_V2_8197F)                                 \
+	 << BIT_SHIFT_WKFCAM_ADDR_V2_8197F)
+#define BITS_WKFCAM_ADDR_V2_8197F                                              \
+	(BIT_MASK_WKFCAM_ADDR_V2_8197F << BIT_SHIFT_WKFCAM_ADDR_V2_8197F)
+#define BIT_CLEAR_WKFCAM_ADDR_V2_8197F(x) ((x) & (~BITS_WKFCAM_ADDR_V2_8197F))
+#define BIT_GET_WKFCAM_ADDR_V2_8197F(x)                                        \
+	(((x) >> BIT_SHIFT_WKFCAM_ADDR_V2_8197F) &                             \
+	 BIT_MASK_WKFCAM_ADDR_V2_8197F)
+#define BIT_SET_WKFCAM_ADDR_V2_8197F(x, v)                                     \
+	(BIT_CLEAR_WKFCAM_ADDR_V2_8197F(x) | BIT_WKFCAM_ADDR_V2_8197F(v))
+
+#define BIT_SHIFT_WKFCAM_CAM_NUM_V1_8197F 0
+#define BIT_MASK_WKFCAM_CAM_NUM_V1_8197F 0xff
+#define BIT_WKFCAM_CAM_NUM_V1_8197F(x)                                         \
+	(((x) & BIT_MASK_WKFCAM_CAM_NUM_V1_8197F)                              \
+	 << BIT_SHIFT_WKFCAM_CAM_NUM_V1_8197F)
+#define BITS_WKFCAM_CAM_NUM_V1_8197F                                           \
+	(BIT_MASK_WKFCAM_CAM_NUM_V1_8197F << BIT_SHIFT_WKFCAM_CAM_NUM_V1_8197F)
+#define BIT_CLEAR_WKFCAM_CAM_NUM_V1_8197F(x)                                   \
+	((x) & (~BITS_WKFCAM_CAM_NUM_V1_8197F))
+#define BIT_GET_WKFCAM_CAM_NUM_V1_8197F(x)                                     \
+	(((x) >> BIT_SHIFT_WKFCAM_CAM_NUM_V1_8197F) &                          \
+	 BIT_MASK_WKFCAM_CAM_NUM_V1_8197F)
+#define BIT_SET_WKFCAM_CAM_NUM_V1_8197F(x, v)                                  \
+	(BIT_CLEAR_WKFCAM_CAM_NUM_V1_8197F(x) | BIT_WKFCAM_CAM_NUM_V1_8197F(v))
+
+/* 2 REG_WKFMCAM_RWD_8197F (WAKEUP FRAME READ/WRITE DATA) */
+
+#define BIT_SHIFT_WKFMCAM_RWD_8197F 0
+#define BIT_MASK_WKFMCAM_RWD_8197F 0xffffffffL
+#define BIT_WKFMCAM_RWD_8197F(x)                                               \
+	(((x) & BIT_MASK_WKFMCAM_RWD_8197F) << BIT_SHIFT_WKFMCAM_RWD_8197F)
+#define BITS_WKFMCAM_RWD_8197F                                                 \
+	(BIT_MASK_WKFMCAM_RWD_8197F << BIT_SHIFT_WKFMCAM_RWD_8197F)
+#define BIT_CLEAR_WKFMCAM_RWD_8197F(x) ((x) & (~BITS_WKFMCAM_RWD_8197F))
+#define BIT_GET_WKFMCAM_RWD_8197F(x)                                           \
+	(((x) >> BIT_SHIFT_WKFMCAM_RWD_8197F) & BIT_MASK_WKFMCAM_RWD_8197F)
+#define BIT_SET_WKFMCAM_RWD_8197F(x, v)                                        \
+	(BIT_CLEAR_WKFMCAM_RWD_8197F(x) | BIT_WKFMCAM_RWD_8197F(v))
+
+/* 2 REG_RXFLTMAP1_8197F (RX FILTER MAP GROUP 1) */
+#define BIT_CTRLFLT15EN_8197F BIT(15)
+#define BIT_CTRLFLT14EN_8197F BIT(14)
+#define BIT_CTRLFLT13EN_8197F BIT(13)
+#define BIT_CTRLFLT12EN_8197F BIT(12)
+#define BIT_CTRLFLT11EN_8197F BIT(11)
+#define BIT_CTRLFLT10EN_8197F BIT(10)
+#define BIT_CTRLFLT9EN_8197F BIT(9)
+#define BIT_CTRLFLT8EN_8197F BIT(8)
+#define BIT_CTRLFLT7EN_8197F BIT(7)
+#define BIT_CTRLFLT6EN_8197F BIT(6)
+#define BIT_CTRLFLT5EN_8197F BIT(5)
+#define BIT_CTRLFLT4EN_8197F BIT(4)
+#define BIT_CTRLFLT3EN_8197F BIT(3)
+#define BIT_CTRLFLT2EN_8197F BIT(2)
+#define BIT_CTRLFLT1EN_8197F BIT(1)
+#define BIT_CTRLFLT0EN_8197F BIT(0)
+
+/* 2 REG_RXFLTMAP0_8197F (RX FILTER MAP GROUP 0) */
+#define BIT_MGTFLT15EN_8197F BIT(15)
+#define BIT_MGTFLT14EN_8197F BIT(14)
+#define BIT_MGTFLT13EN_8197F BIT(13)
+#define BIT_MGTFLT12EN_8197F BIT(12)
+#define BIT_MGTFLT11EN_8197F BIT(11)
+#define BIT_MGTFLT10EN_8197F BIT(10)
+#define BIT_MGTFLT9EN_8197F BIT(9)
+#define BIT_MGTFLT8EN_8197F BIT(8)
+#define BIT_MGTFLT7EN_8197F BIT(7)
+#define BIT_MGTFLT6EN_8197F BIT(6)
+#define BIT_MGTFLT5EN_8197F BIT(5)
+#define BIT_MGTFLT4EN_8197F BIT(4)
+#define BIT_MGTFLT3EN_8197F BIT(3)
+#define BIT_MGTFLT2EN_8197F BIT(2)
+#define BIT_MGTFLT1EN_8197F BIT(1)
+#define BIT_MGTFLT0EN_8197F BIT(0)
+
+/* 2 REG_NOT_VALID_8197F */
+
+/* 2 REG_RXFLTMAP_8197F (RX FILTER MAP GROUP 2) */
+#define BIT_DATAFLT15EN_8197F BIT(15)
+#define BIT_DATAFLT14EN_8197F BIT(14)
+#define BIT_DATAFLT13EN_8197F BIT(13)
+#define BIT_DATAFLT12EN_8197F BIT(12)
+#define BIT_DATAFLT11EN_8197F BIT(11)
+#define BIT_DATAFLT10EN_8197F BIT(10)
+#define BIT_DATAFLT9EN_8197F BIT(9)
+#define BIT_DATAFLT8EN_8197F BIT(8)
+#define BIT_DATAFLT7EN_8197F BIT(7)
+#define BIT_DATAFLT6EN_8197F BIT(6)
+#define BIT_DATAFLT5EN_8197F BIT(5)
+#define BIT_DATAFLT4EN_8197F BIT(4)
+#define BIT_DATAFLT3EN_8197F BIT(3)
+#define BIT_DATAFLT2EN_8197F BIT(2)
+#define BIT_DATAFLT1EN_8197F BIT(1)
+#define BIT_DATAFLT0EN_8197F BIT(0)
+
+/* 2 REG_BCN_PSR_RPT_8197F (BEACON PARSER REPORT REGISTER) */
+
+#define BIT_SHIFT_DTIM_CNT_8197F 24
+#define BIT_MASK_DTIM_CNT_8197F 0xff
+#define BIT_DTIM_CNT_8197F(x)                                                  \
+	(((x) & BIT_MASK_DTIM_CNT_8197F) << BIT_SHIFT_DTIM_CNT_8197F)
+#define BITS_DTIM_CNT_8197F                                                    \
+	(BIT_MASK_DTIM_CNT_8197F << BIT_SHIFT_DTIM_CNT_8197F)
+#define BIT_CLEAR_DTIM_CNT_8197F(x) ((x) & (~BITS_DTIM_CNT_8197F))
+#define BIT_GET_DTIM_CNT_8197F(x)                                              \
+	(((x) >> BIT_SHIFT_DTIM_CNT_8197F) & BIT_MASK_DTIM_CNT_8197F)
+#define BIT_SET_DTIM_CNT_8197F(x, v)                                           \
+	(BIT_CLEAR_DTIM_CNT_8197F(x) | BIT_DTIM_CNT_8197F(v))
+
+#define BIT_SHIFT_DTIM_PERIOD_8197F 16
+#define BIT_MASK_DTIM_PERIOD_8197F 0xff
+#define BIT_DTIM_PERIOD_8197F(x)                                               \
+	(((x) & BIT_MASK_DTIM_PERIOD_8197F) << BIT_SHIFT_DTIM_PERIOD_8197F)
+#define BITS_DTIM_PERIOD_8197F                                                 \
+	(BIT_MASK_DTIM_PERIOD_8197F << BIT_SHIFT_DTIM_PERIOD_8197F)
+#define BIT_CLEAR_DTIM_PERIOD_8197F(x) ((x) & (~BITS_DTIM_PERIOD_8197F))
+#define BIT_GET_DTIM_PERIOD_8197F(x)                                           \
+	(((x) >> BIT_SHIFT_DTIM_PERIOD_8197F) & BIT_MASK_DTIM_PERIOD_8197F)
+#define BIT_SET_DTIM_PERIOD_8197F(x, v)                                        \
+	(BIT_CLEAR_DTIM_PERIOD_8197F(x) | BIT_DTIM_PERIOD_8197F(v))
+
+#define BIT_DTIM_8197F BIT(15)
+#define BIT_TIM_8197F BIT(14)
+
+#define BIT_SHIFT_PS_AID_0_8197F 0
+#define BIT_MASK_PS_AID_0_8197F 0x7ff
+#define BIT_PS_AID_0_8197F(x)                                                  \
+	(((x) & BIT_MASK_PS_AID_0_8197F) << BIT_SHIFT_PS_AID_0_8197F)
+#define BITS_PS_AID_0_8197F                                                    \
+	(BIT_MASK_PS_AID_0_8197F << BIT_SHIFT_PS_AID_0_8197F)
+#define BIT_CLEAR_PS_AID_0_8197F(x) ((x) & (~BITS_PS_AID_0_8197F))
+#define BIT_GET_PS_AID_0_8197F(x)                                              \
+	(((x) >> BIT_SHIFT_PS_AID_0_8197F) & BIT_MASK_PS_AID_0_8197F)
+#define BIT_SET_PS_AID_0_8197F(x, v)                                           \
+	(BIT_CLEAR_PS_AID_0_8197F(x) | BIT_PS_AID_0_8197F(v))
+
+/* 2 REG_NOT_VALID_8197F */
+#define BIT_FLC_RPCT_V1_8197F BIT(7)
+#define BIT_MODE_8197F BIT(6)
+
+#define BIT_SHIFT_TRPCD_8197F 0
+#define BIT_MASK_TRPCD_8197F 0x3f
+#define BIT_TRPCD_8197F(x)                                                     \
+	(((x) & BIT_MASK_TRPCD_8197F) << BIT_SHIFT_TRPCD_8197F)
+#define BITS_TRPCD_8197F (BIT_MASK_TRPCD_8197F << BIT_SHIFT_TRPCD_8197F)
+#define BIT_CLEAR_TRPCD_8197F(x) ((x) & (~BITS_TRPCD_8197F))
+#define BIT_GET_TRPCD_8197F(x)                                                 \
+	(((x) >> BIT_SHIFT_TRPCD_8197F) & BIT_MASK_TRPCD_8197F)
+#define BIT_SET_TRPCD_8197F(x, v)                                              \
+	(BIT_CLEAR_TRPCD_8197F(x) | BIT_TRPCD_8197F(v))
+
+/* 2 REG_NOT_VALID_8197F */
+#define BIT_CMF_8197F BIT(2)
+#define BIT_CCF_8197F BIT(1)
+#define BIT_CDF_8197F BIT(0)
+
+/* 2 REG_NOT_VALID_8197F */
+
+#define BIT_SHIFT_FLC_RPCT_8197F 0
+#define BIT_MASK_FLC_RPCT_8197F 0xff
+#define BIT_FLC_RPCT_8197F(x)                                                  \
+	(((x) & BIT_MASK_FLC_RPCT_8197F) << BIT_SHIFT_FLC_RPCT_8197F)
+#define BITS_FLC_RPCT_8197F                                                    \
+	(BIT_MASK_FLC_RPCT_8197F << BIT_SHIFT_FLC_RPCT_8197F)
+#define BIT_CLEAR_FLC_RPCT_8197F(x) ((x) & (~BITS_FLC_RPCT_8197F))
+#define BIT_GET_FLC_RPCT_8197F(x)                                              \
+	(((x) >> BIT_SHIFT_FLC_RPCT_8197F) & BIT_MASK_FLC_RPCT_8197F)
+#define BIT_SET_FLC_RPCT_8197F(x, v)                                           \
+	(BIT_CLEAR_FLC_RPCT_8197F(x) | BIT_FLC_RPCT_8197F(v))
+
+/* 2 REG_NOT_VALID_8197F */
+
+#define BIT_SHIFT_FLC_RPC_8197F 0
+#define BIT_MASK_FLC_RPC_8197F 0xff
+#define BIT_FLC_RPC_8197F(x)                                                   \
+	(((x) & BIT_MASK_FLC_RPC_8197F) << BIT_SHIFT_FLC_RPC_8197F)
+#define BITS_FLC_RPC_8197F (BIT_MASK_FLC_RPC_8197F << BIT_SHIFT_FLC_RPC_8197F)
+#define BIT_CLEAR_FLC_RPC_8197F(x) ((x) & (~BITS_FLC_RPC_8197F))
+#define BIT_GET_FLC_RPC_8197F(x)                                               \
+	(((x) >> BIT_SHIFT_FLC_RPC_8197F) & BIT_MASK_FLC_RPC_8197F)
+#define BIT_SET_FLC_RPC_8197F(x, v)                                            \
+	(BIT_CLEAR_FLC_RPC_8197F(x) | BIT_FLC_RPC_8197F(v))
+
+/* 2 REG_RXPKTMON_CTRL_8197F */
+
+#define BIT_SHIFT_RXBKQPKT_SEQ_8197F 20
+#define BIT_MASK_RXBKQPKT_SEQ_8197F 0xf
+#define BIT_RXBKQPKT_SEQ_8197F(x)                                              \
+	(((x) & BIT_MASK_RXBKQPKT_SEQ_8197F) << BIT_SHIFT_RXBKQPKT_SEQ_8197F)
+#define BITS_RXBKQPKT_SEQ_8197F                                                \
+	(BIT_MASK_RXBKQPKT_SEQ_8197F << BIT_SHIFT_RXBKQPKT_SEQ_8197F)
+#define BIT_CLEAR_RXBKQPKT_SEQ_8197F(x) ((x) & (~BITS_RXBKQPKT_SEQ_8197F))
+#define BIT_GET_RXBKQPKT_SEQ_8197F(x)                                          \
+	(((x) >> BIT_SHIFT_RXBKQPKT_SEQ_8197F) & BIT_MASK_RXBKQPKT_SEQ_8197F)
+#define BIT_SET_RXBKQPKT_SEQ_8197F(x, v)                                       \
+	(BIT_CLEAR_RXBKQPKT_SEQ_8197F(x) | BIT_RXBKQPKT_SEQ_8197F(v))
+
+#define BIT_SHIFT_RXBEQPKT_SEQ_8197F 16
+#define BIT_MASK_RXBEQPKT_SEQ_8197F 0xf
+#define BIT_RXBEQPKT_SEQ_8197F(x)                                              \
+	(((x) & BIT_MASK_RXBEQPKT_SEQ_8197F) << BIT_SHIFT_RXBEQPKT_SEQ_8197F)
+#define BITS_RXBEQPKT_SEQ_8197F                                                \
+	(BIT_MASK_RXBEQPKT_SEQ_8197F << BIT_SHIFT_RXBEQPKT_SEQ_8197F)
+#define BIT_CLEAR_RXBEQPKT_SEQ_8197F(x) ((x) & (~BITS_RXBEQPKT_SEQ_8197F))
+#define BIT_GET_RXBEQPKT_SEQ_8197F(x)                                          \
+	(((x) >> BIT_SHIFT_RXBEQPKT_SEQ_8197F) & BIT_MASK_RXBEQPKT_SEQ_8197F)
+#define BIT_SET_RXBEQPKT_SEQ_8197F(x, v)                                       \
+	(BIT_CLEAR_RXBEQPKT_SEQ_8197F(x) | BIT_RXBEQPKT_SEQ_8197F(v))
+
+#define BIT_SHIFT_RXVIQPKT_SEQ_8197F 12
+#define BIT_MASK_RXVIQPKT_SEQ_8197F 0xf
+#define BIT_RXVIQPKT_SEQ_8197F(x)                                              \
+	(((x) & BIT_MASK_RXVIQPKT_SEQ_8197F) << BIT_SHIFT_RXVIQPKT_SEQ_8197F)
+#define BITS_RXVIQPKT_SEQ_8197F                                                \
+	(BIT_MASK_RXVIQPKT_SEQ_8197F << BIT_SHIFT_RXVIQPKT_SEQ_8197F)
+#define BIT_CLEAR_RXVIQPKT_SEQ_8197F(x) ((x) & (~BITS_RXVIQPKT_SEQ_8197F))
+#define BIT_GET_RXVIQPKT_SEQ_8197F(x)                                          \
+	(((x) >> BIT_SHIFT_RXVIQPKT_SEQ_8197F) & BIT_MASK_RXVIQPKT_SEQ_8197F)
+#define BIT_SET_RXVIQPKT_SEQ_8197F(x, v)                                       \
+	(BIT_CLEAR_RXVIQPKT_SEQ_8197F(x) | BIT_RXVIQPKT_SEQ_8197F(v))
+
+#define BIT_SHIFT_RXVOQPKT_SEQ_8197F 8
+#define BIT_MASK_RXVOQPKT_SEQ_8197F 0xf
+#define BIT_RXVOQPKT_SEQ_8197F(x)                                              \
+	(((x) & BIT_MASK_RXVOQPKT_SEQ_8197F) << BIT_SHIFT_RXVOQPKT_SEQ_8197F)
+#define BITS_RXVOQPKT_SEQ_8197F                                                \
+	(BIT_MASK_RXVOQPKT_SEQ_8197F << BIT_SHIFT_RXVOQPKT_SEQ_8197F)
+#define BIT_CLEAR_RXVOQPKT_SEQ_8197F(x) ((x) & (~BITS_RXVOQPKT_SEQ_8197F))
+#define BIT_GET_RXVOQPKT_SEQ_8197F(x)                                          \
+	(((x) >> BIT_SHIFT_RXVOQPKT_SEQ_8197F) & BIT_MASK_RXVOQPKT_SEQ_8197F)
+#define BIT_SET_RXVOQPKT_SEQ_8197F(x, v)                                       \
+	(BIT_CLEAR_RXVOQPKT_SEQ_8197F(x) | BIT_RXVOQPKT_SEQ_8197F(v))
+
+#define BIT_RXBKQPKT_ERR_8197F BIT(7)
+#define BIT_RXBEQPKT_ERR_8197F BIT(6)
+#define BIT_RXVIQPKT_ERR_8197F BIT(5)
+#define BIT_RXVOQPKT_ERR_8197F BIT(4)
+#define BIT_RXDMA_MON_EN_8197F BIT(2)
+#define BIT_RXPKT_MON_RST_8197F BIT(1)
+#define BIT_RXPKT_MON_EN_8197F BIT(0)
+
+/* 2 REG_STATE_MON_8197F */
+
+#define BIT_SHIFT_STATE_SEL_8197F 24
+#define BIT_MASK_STATE_SEL_8197F 0x1f
+#define BIT_STATE_SEL_8197F(x)                                                 \
+	(((x) & BIT_MASK_STATE_SEL_8197F) << BIT_SHIFT_STATE_SEL_8197F)
+#define BITS_STATE_SEL_8197F                                                   \
+	(BIT_MASK_STATE_SEL_8197F << BIT_SHIFT_STATE_SEL_8197F)
+#define BIT_CLEAR_STATE_SEL_8197F(x) ((x) & (~BITS_STATE_SEL_8197F))
+#define BIT_GET_STATE_SEL_8197F(x)                                             \
+	(((x) >> BIT_SHIFT_STATE_SEL_8197F) & BIT_MASK_STATE_SEL_8197F)
+#define BIT_SET_STATE_SEL_8197F(x, v)                                          \
+	(BIT_CLEAR_STATE_SEL_8197F(x) | BIT_STATE_SEL_8197F(v))
+
+#define BIT_SHIFT_STATE_INFO_8197F 8
+#define BIT_MASK_STATE_INFO_8197F 0xff
+#define BIT_STATE_INFO_8197F(x)                                                \
+	(((x) & BIT_MASK_STATE_INFO_8197F) << BIT_SHIFT_STATE_INFO_8197F)
+#define BITS_STATE_INFO_8197F                                                  \
+	(BIT_MASK_STATE_INFO_8197F << BIT_SHIFT_STATE_INFO_8197F)
+#define BIT_CLEAR_STATE_INFO_8197F(x) ((x) & (~BITS_STATE_INFO_8197F))
+#define BIT_GET_STATE_INFO_8197F(x)                                            \
+	(((x) >> BIT_SHIFT_STATE_INFO_8197F) & BIT_MASK_STATE_INFO_8197F)
+#define BIT_SET_STATE_INFO_8197F(x, v)                                         \
+	(BIT_CLEAR_STATE_INFO_8197F(x) | BIT_STATE_INFO_8197F(v))
+
+#define BIT_UPD_NXT_STATE_8197F BIT(7)
+
+#define BIT_SHIFT_CUR_STATE_8197F 0
+#define BIT_MASK_CUR_STATE_8197F 0x7f
+#define BIT_CUR_STATE_8197F(x)                                                 \
+	(((x) & BIT_MASK_CUR_STATE_8197F) << BIT_SHIFT_CUR_STATE_8197F)
+#define BITS_CUR_STATE_8197F                                                   \
+	(BIT_MASK_CUR_STATE_8197F << BIT_SHIFT_CUR_STATE_8197F)
+#define BIT_CLEAR_CUR_STATE_8197F(x) ((x) & (~BITS_CUR_STATE_8197F))
+#define BIT_GET_CUR_STATE_8197F(x)                                             \
+	(((x) >> BIT_SHIFT_CUR_STATE_8197F) & BIT_MASK_CUR_STATE_8197F)
+#define BIT_SET_CUR_STATE_8197F(x, v)                                          \
+	(BIT_CLEAR_CUR_STATE_8197F(x) | BIT_CUR_STATE_8197F(v))
+
+/* 2 REG_ERROR_MON_8197F */
+#define BIT_MACRX_ERR_1_8197F BIT(17)
+#define BIT_MACRX_ERR_0_8197F BIT(16)
+#define BIT_MACTX_ERR_3_8197F BIT(3)
+#define BIT_MACTX_ERR_2_8197F BIT(2)
+#define BIT_MACTX_ERR_1_8197F BIT(1)
+#define BIT_MACTX_ERR_0_8197F BIT(0)
+
+/* 2 REG_SEARCH_MACID_8197F */
+#define BIT_EN_TXRPTBUF_CLK_8197F BIT(31)
+
+#define BIT_SHIFT_INFO_INDEX_OFFSET_8197F 16
+#define BIT_MASK_INFO_INDEX_OFFSET_8197F 0x1fff
+#define BIT_INFO_INDEX_OFFSET_8197F(x)                                         \
+	(((x) & BIT_MASK_INFO_INDEX_OFFSET_8197F)                              \
+	 << BIT_SHIFT_INFO_INDEX_OFFSET_8197F)
+#define BITS_INFO_INDEX_OFFSET_8197F                                           \
+	(BIT_MASK_INFO_INDEX_OFFSET_8197F << BIT_SHIFT_INFO_INDEX_OFFSET_8197F)
+#define BIT_CLEAR_INFO_INDEX_OFFSET_8197F(x)                                   \
+	((x) & (~BITS_INFO_INDEX_OFFSET_8197F))
+#define BIT_GET_INFO_INDEX_OFFSET_8197F(x)                                     \
+	(((x) >> BIT_SHIFT_INFO_INDEX_OFFSET_8197F) &                          \
+	 BIT_MASK_INFO_INDEX_OFFSET_8197F)
+#define BIT_SET_INFO_INDEX_OFFSET_8197F(x, v)                                  \
+	(BIT_CLEAR_INFO_INDEX_OFFSET_8197F(x) | BIT_INFO_INDEX_OFFSET_8197F(v))
+
+#define BIT_DIS_INFOSRCH_8197F BIT(14)
+#define BIT_DISABLE_B0_8197F BIT(13)
+
+#define BIT_SHIFT_INFO_ADDR_OFFSET_8197F 0
+#define BIT_MASK_INFO_ADDR_OFFSET_8197F 0x1fff
+#define BIT_INFO_ADDR_OFFSET_8197F(x)                                          \
+	(((x) & BIT_MASK_INFO_ADDR_OFFSET_8197F)                               \
+	 << BIT_SHIFT_INFO_ADDR_OFFSET_8197F)
+#define BITS_INFO_ADDR_OFFSET_8197F                                            \
+	(BIT_MASK_INFO_ADDR_OFFSET_8197F << BIT_SHIFT_INFO_ADDR_OFFSET_8197F)
+#define BIT_CLEAR_INFO_ADDR_OFFSET_8197F(x)                                    \
+	((x) & (~BITS_INFO_ADDR_OFFSET_8197F))
+#define BIT_GET_INFO_ADDR_OFFSET_8197F(x)                                      \
+	(((x) >> BIT_SHIFT_INFO_ADDR_OFFSET_8197F) &                           \
+	 BIT_MASK_INFO_ADDR_OFFSET_8197F)
+#define BIT_SET_INFO_ADDR_OFFSET_8197F(x, v)                                   \
+	(BIT_CLEAR_INFO_ADDR_OFFSET_8197F(x) | BIT_INFO_ADDR_OFFSET_8197F(v))
+
+/* 2 REG_BT_COEX_TABLE_8197F (BT-COEXISTENCE CONTROL REGISTER) */
+#define BIT_PRI_MASK_RX_RESP_8197F BIT(126)
+#define BIT_PRI_MASK_RXOFDM_8197F BIT(125)
+#define BIT_PRI_MASK_RXCCK_8197F BIT(124)
+
+#define BIT_SHIFT_PRI_MASK_TXAC_8197F (117 & CPU_OPT_WIDTH)
+#define BIT_MASK_PRI_MASK_TXAC_8197F 0x7f
+#define BIT_PRI_MASK_TXAC_8197F(x)                                             \
+	(((x) & BIT_MASK_PRI_MASK_TXAC_8197F) << BIT_SHIFT_PRI_MASK_TXAC_8197F)
+#define BITS_PRI_MASK_TXAC_8197F                                               \
+	(BIT_MASK_PRI_MASK_TXAC_8197F << BIT_SHIFT_PRI_MASK_TXAC_8197F)
+#define BIT_CLEAR_PRI_MASK_TXAC_8197F(x) ((x) & (~BITS_PRI_MASK_TXAC_8197F))
+#define BIT_GET_PRI_MASK_TXAC_8197F(x)                                         \
+	(((x) >> BIT_SHIFT_PRI_MASK_TXAC_8197F) & BIT_MASK_PRI_MASK_TXAC_8197F)
+#define BIT_SET_PRI_MASK_TXAC_8197F(x, v)                                      \
+	(BIT_CLEAR_PRI_MASK_TXAC_8197F(x) | BIT_PRI_MASK_TXAC_8197F(v))
+
+#define BIT_SHIFT_PRI_MASK_NAV_8197F (109 & CPU_OPT_WIDTH)
+#define BIT_MASK_PRI_MASK_NAV_8197F 0xff
+#define BIT_PRI_MASK_NAV_8197F(x)                                              \
+	(((x) & BIT_MASK_PRI_MASK_NAV_8197F) << BIT_SHIFT_PRI_MASK_NAV_8197F)
+#define BITS_PRI_MASK_NAV_8197F                                                \
+	(BIT_MASK_PRI_MASK_NAV_8197F << BIT_SHIFT_PRI_MASK_NAV_8197F)
+#define BIT_CLEAR_PRI_MASK_NAV_8197F(x) ((x) & (~BITS_PRI_MASK_NAV_8197F))
+#define BIT_GET_PRI_MASK_NAV_8197F(x)                                          \
+	(((x) >> BIT_SHIFT_PRI_MASK_NAV_8197F) & BIT_MASK_PRI_MASK_NAV_8197F)
+#define BIT_SET_PRI_MASK_NAV_8197F(x, v)                                       \
+	(BIT_CLEAR_PRI_MASK_NAV_8197F(x) | BIT_PRI_MASK_NAV_8197F(v))
+
+#define BIT_PRI_MASK_CCK_8197F BIT(108)
+#define BIT_PRI_MASK_OFDM_8197F BIT(107)
+#define BIT_PRI_MASK_RTY_8197F BIT(106)
+
+#define BIT_SHIFT_PRI_MASK_NUM_8197F (102 & CPU_OPT_WIDTH)
+#define BIT_MASK_PRI_MASK_NUM_8197F 0xf
+#define BIT_PRI_MASK_NUM_8197F(x)                                              \
+	(((x) & BIT_MASK_PRI_MASK_NUM_8197F) << BIT_SHIFT_PRI_MASK_NUM_8197F)
+#define BITS_PRI_MASK_NUM_8197F                                                \
+	(BIT_MASK_PRI_MASK_NUM_8197F << BIT_SHIFT_PRI_MASK_NUM_8197F)
+#define BIT_CLEAR_PRI_MASK_NUM_8197F(x) ((x) & (~BITS_PRI_MASK_NUM_8197F))
+#define BIT_GET_PRI_MASK_NUM_8197F(x)                                          \
+	(((x) >> BIT_SHIFT_PRI_MASK_NUM_8197F) & BIT_MASK_PRI_MASK_NUM_8197F)
+#define BIT_SET_PRI_MASK_NUM_8197F(x, v)                                       \
+	(BIT_CLEAR_PRI_MASK_NUM_8197F(x) | BIT_PRI_MASK_NUM_8197F(v))
+
+#define BIT_SHIFT_PRI_MASK_TYPE_8197F (98 & CPU_OPT_WIDTH)
+#define BIT_MASK_PRI_MASK_TYPE_8197F 0xf
+#define BIT_PRI_MASK_TYPE_8197F(x)                                             \
+	(((x) & BIT_MASK_PRI_MASK_TYPE_8197F) << BIT_SHIFT_PRI_MASK_TYPE_8197F)
+#define BITS_PRI_MASK_TYPE_8197F                                               \
+	(BIT_MASK_PRI_MASK_TYPE_8197F << BIT_SHIFT_PRI_MASK_TYPE_8197F)
+#define BIT_CLEAR_PRI_MASK_TYPE_8197F(x) ((x) & (~BITS_PRI_MASK_TYPE_8197F))
+#define BIT_GET_PRI_MASK_TYPE_8197F(x)                                         \
+	(((x) >> BIT_SHIFT_PRI_MASK_TYPE_8197F) & BIT_MASK_PRI_MASK_TYPE_8197F)
+#define BIT_SET_PRI_MASK_TYPE_8197F(x, v)                                      \
+	(BIT_CLEAR_PRI_MASK_TYPE_8197F(x) | BIT_PRI_MASK_TYPE_8197F(v))
+
+#define BIT_OOB_8197F BIT(97)
+#define BIT_ANT_SEL_8197F BIT(96)
+
+#define BIT_SHIFT_BREAK_TABLE_2_8197F (80 & CPU_OPT_WIDTH)
+#define BIT_MASK_BREAK_TABLE_2_8197F 0xffff
+#define BIT_BREAK_TABLE_2_8197F(x)                                             \
+	(((x) & BIT_MASK_BREAK_TABLE_2_8197F) << BIT_SHIFT_BREAK_TABLE_2_8197F)
+#define BITS_BREAK_TABLE_2_8197F                                               \
+	(BIT_MASK_BREAK_TABLE_2_8197F << BIT_SHIFT_BREAK_TABLE_2_8197F)
+#define BIT_CLEAR_BREAK_TABLE_2_8197F(x) ((x) & (~BITS_BREAK_TABLE_2_8197F))
+#define BIT_GET_BREAK_TABLE_2_8197F(x)                                         \
+	(((x) >> BIT_SHIFT_BREAK_TABLE_2_8197F) & BIT_MASK_BREAK_TABLE_2_8197F)
+#define BIT_SET_BREAK_TABLE_2_8197F(x, v)                                      \
+	(BIT_CLEAR_BREAK_TABLE_2_8197F(x) | BIT_BREAK_TABLE_2_8197F(v))
+
+#define BIT_SHIFT_BREAK_TABLE_1_8197F (64 & CPU_OPT_WIDTH)
+#define BIT_MASK_BREAK_TABLE_1_8197F 0xffff
+#define BIT_BREAK_TABLE_1_8197F(x)                                             \
+	(((x) & BIT_MASK_BREAK_TABLE_1_8197F) << BIT_SHIFT_BREAK_TABLE_1_8197F)
+#define BITS_BREAK_TABLE_1_8197F                                               \
+	(BIT_MASK_BREAK_TABLE_1_8197F << BIT_SHIFT_BREAK_TABLE_1_8197F)
+#define BIT_CLEAR_BREAK_TABLE_1_8197F(x) ((x) & (~BITS_BREAK_TABLE_1_8197F))
+#define BIT_GET_BREAK_TABLE_1_8197F(x)                                         \
+	(((x) >> BIT_SHIFT_BREAK_TABLE_1_8197F) & BIT_MASK_BREAK_TABLE_1_8197F)
+#define BIT_SET_BREAK_TABLE_1_8197F(x, v)                                      \
+	(BIT_CLEAR_BREAK_TABLE_1_8197F(x) | BIT_BREAK_TABLE_1_8197F(v))
+
+#define BIT_SHIFT_COEX_TABLE_2_8197F (32 & CPU_OPT_WIDTH)
+#define BIT_MASK_COEX_TABLE_2_8197F 0xffffffffL
+#define BIT_COEX_TABLE_2_8197F(x)                                              \
+	(((x) & BIT_MASK_COEX_TABLE_2_8197F) << BIT_SHIFT_COEX_TABLE_2_8197F)
+#define BITS_COEX_TABLE_2_8197F                                                \
+	(BIT_MASK_COEX_TABLE_2_8197F << BIT_SHIFT_COEX_TABLE_2_8197F)
+#define BIT_CLEAR_COEX_TABLE_2_8197F(x) ((x) & (~BITS_COEX_TABLE_2_8197F))
+#define BIT_GET_COEX_TABLE_2_8197F(x)                                          \
+	(((x) >> BIT_SHIFT_COEX_TABLE_2_8197F) & BIT_MASK_COEX_TABLE_2_8197F)
+#define BIT_SET_COEX_TABLE_2_8197F(x, v)                                       \
+	(BIT_CLEAR_COEX_TABLE_2_8197F(x) | BIT_COEX_TABLE_2_8197F(v))
+
+#define BIT_SHIFT_COEX_TABLE_1_8197F 0
+#define BIT_MASK_COEX_TABLE_1_8197F 0xffffffffL
+#define BIT_COEX_TABLE_1_8197F(x)                                              \
+	(((x) & BIT_MASK_COEX_TABLE_1_8197F) << BIT_SHIFT_COEX_TABLE_1_8197F)
+#define BITS_COEX_TABLE_1_8197F                                                \
+	(BIT_MASK_COEX_TABLE_1_8197F << BIT_SHIFT_COEX_TABLE_1_8197F)
+#define BIT_CLEAR_COEX_TABLE_1_8197F(x) ((x) & (~BITS_COEX_TABLE_1_8197F))
+#define BIT_GET_COEX_TABLE_1_8197F(x)                                          \
+	(((x) >> BIT_SHIFT_COEX_TABLE_1_8197F) & BIT_MASK_COEX_TABLE_1_8197F)
+#define BIT_SET_COEX_TABLE_1_8197F(x, v)                                       \
+	(BIT_CLEAR_COEX_TABLE_1_8197F(x) | BIT_COEX_TABLE_1_8197F(v))
+
+/* 2 REG_RXCMD_0_8197F */
+#define BIT_RXCMD_EN_8197F BIT(31)
+
+#define BIT_SHIFT_RXCMD_INFO_8197F 0
+#define BIT_MASK_RXCMD_INFO_8197F 0x7fffffffL
+#define BIT_RXCMD_INFO_8197F(x)                                                \
+	(((x) & BIT_MASK_RXCMD_INFO_8197F) << BIT_SHIFT_RXCMD_INFO_8197F)
+#define BITS_RXCMD_INFO_8197F                                                  \
+	(BIT_MASK_RXCMD_INFO_8197F << BIT_SHIFT_RXCMD_INFO_8197F)
+#define BIT_CLEAR_RXCMD_INFO_8197F(x) ((x) & (~BITS_RXCMD_INFO_8197F))
+#define BIT_GET_RXCMD_INFO_8197F(x)                                            \
+	(((x) >> BIT_SHIFT_RXCMD_INFO_8197F) & BIT_MASK_RXCMD_INFO_8197F)
+#define BIT_SET_RXCMD_INFO_8197F(x, v)                                         \
+	(BIT_CLEAR_RXCMD_INFO_8197F(x) | BIT_RXCMD_INFO_8197F(v))
+
+/* 2 REG_RXCMD_1_8197F */
+
+#define BIT_SHIFT_RXCMD_PRD_8197F 0
+#define BIT_MASK_RXCMD_PRD_8197F 0xffff
+#define BIT_RXCMD_PRD_8197F(x)                                                 \
+	(((x) & BIT_MASK_RXCMD_PRD_8197F) << BIT_SHIFT_RXCMD_PRD_8197F)
+#define BITS_RXCMD_PRD_8197F                                                   \
+	(BIT_MASK_RXCMD_PRD_8197F << BIT_SHIFT_RXCMD_PRD_8197F)
+#define BIT_CLEAR_RXCMD_PRD_8197F(x) ((x) & (~BITS_RXCMD_PRD_8197F))
+#define BIT_GET_RXCMD_PRD_8197F(x)                                             \
+	(((x) >> BIT_SHIFT_RXCMD_PRD_8197F) & BIT_MASK_RXCMD_PRD_8197F)
+#define BIT_SET_RXCMD_PRD_8197F(x, v)                                          \
+	(BIT_CLEAR_RXCMD_PRD_8197F(x) | BIT_RXCMD_PRD_8197F(v))
+
+/* 2 REG_NOT_VALID_8197F */
+
+/* 2 REG_WMAC_RESP_TXINFO_8197F (RESPONSE TXINFO REGISTER) */
+
+#define BIT_SHIFT_WMAC_RESP_MFB_8197F 25
+#define BIT_MASK_WMAC_RESP_MFB_8197F 0x7f
+#define BIT_WMAC_RESP_MFB_8197F(x)                                             \
+	(((x) & BIT_MASK_WMAC_RESP_MFB_8197F) << BIT_SHIFT_WMAC_RESP_MFB_8197F)
+#define BITS_WMAC_RESP_MFB_8197F                                               \
+	(BIT_MASK_WMAC_RESP_MFB_8197F << BIT_SHIFT_WMAC_RESP_MFB_8197F)
+#define BIT_CLEAR_WMAC_RESP_MFB_8197F(x) ((x) & (~BITS_WMAC_RESP_MFB_8197F))
+#define BIT_GET_WMAC_RESP_MFB_8197F(x)                                         \
+	(((x) >> BIT_SHIFT_WMAC_RESP_MFB_8197F) & BIT_MASK_WMAC_RESP_MFB_8197F)
+#define BIT_SET_WMAC_RESP_MFB_8197F(x, v)                                      \
+	(BIT_CLEAR_WMAC_RESP_MFB_8197F(x) | BIT_WMAC_RESP_MFB_8197F(v))
+
+#define BIT_SHIFT_WMAC_ANTINF_SEL_8197F 23
+#define BIT_MASK_WMAC_ANTINF_SEL_8197F 0x3
+#define BIT_WMAC_ANTINF_SEL_8197F(x)                                           \
+	(((x) & BIT_MASK_WMAC_ANTINF_SEL_8197F)                                \
+	 << BIT_SHIFT_WMAC_ANTINF_SEL_8197F)
+#define BITS_WMAC_ANTINF_SEL_8197F                                             \
+	(BIT_MASK_WMAC_ANTINF_SEL_8197F << BIT_SHIFT_WMAC_ANTINF_SEL_8197F)
+#define BIT_CLEAR_WMAC_ANTINF_SEL_8197F(x) ((x) & (~BITS_WMAC_ANTINF_SEL_8197F))
+#define BIT_GET_WMAC_ANTINF_SEL_8197F(x)                                       \
+	(((x) >> BIT_SHIFT_WMAC_ANTINF_SEL_8197F) &                            \
+	 BIT_MASK_WMAC_ANTINF_SEL_8197F)
+#define BIT_SET_WMAC_ANTINF_SEL_8197F(x, v)                                    \
+	(BIT_CLEAR_WMAC_ANTINF_SEL_8197F(x) | BIT_WMAC_ANTINF_SEL_8197F(v))
+
+#define BIT_SHIFT_WMAC_ANTSEL_SEL_8197F 21
+#define BIT_MASK_WMAC_ANTSEL_SEL_8197F 0x3
+#define BIT_WMAC_ANTSEL_SEL_8197F(x)                                           \
+	(((x) & BIT_MASK_WMAC_ANTSEL_SEL_8197F)                                \
+	 << BIT_SHIFT_WMAC_ANTSEL_SEL_8197F)
+#define BITS_WMAC_ANTSEL_SEL_8197F                                             \
+	(BIT_MASK_WMAC_ANTSEL_SEL_8197F << BIT_SHIFT_WMAC_ANTSEL_SEL_8197F)
+#define BIT_CLEAR_WMAC_ANTSEL_SEL_8197F(x) ((x) & (~BITS_WMAC_ANTSEL_SEL_8197F))
+#define BIT_GET_WMAC_ANTSEL_SEL_8197F(x)                                       \
+	(((x) >> BIT_SHIFT_WMAC_ANTSEL_SEL_8197F) &                            \
+	 BIT_MASK_WMAC_ANTSEL_SEL_8197F)
+#define BIT_SET_WMAC_ANTSEL_SEL_8197F(x, v)                                    \
+	(BIT_CLEAR_WMAC_ANTSEL_SEL_8197F(x) | BIT_WMAC_ANTSEL_SEL_8197F(v))
+
+#define BIT_SHIFT_R_WMAC_RESP_TXPOWER_8197F 18
+#define BIT_MASK_R_WMAC_RESP_TXPOWER_8197F 0x7
+#define BIT_R_WMAC_RESP_TXPOWER_8197F(x)                                       \
+	(((x) & BIT_MASK_R_WMAC_RESP_TXPOWER_8197F)                            \
+	 << BIT_SHIFT_R_WMAC_RESP_TXPOWER_8197F)
+#define BITS_R_WMAC_RESP_TXPOWER_8197F                                         \
+	(BIT_MASK_R_WMAC_RESP_TXPOWER_8197F                                    \
+	 << BIT_SHIFT_R_WMAC_RESP_TXPOWER_8197F)
+#define BIT_CLEAR_R_WMAC_RESP_TXPOWER_8197F(x)                                 \
+	((x) & (~BITS_R_WMAC_RESP_TXPOWER_8197F))
+#define BIT_GET_R_WMAC_RESP_TXPOWER_8197F(x)                                   \
+	(((x) >> BIT_SHIFT_R_WMAC_RESP_TXPOWER_8197F) &                        \
+	 BIT_MASK_R_WMAC_RESP_TXPOWER_8197F)
+#define BIT_SET_R_WMAC_RESP_TXPOWER_8197F(x, v)                                \
+	(BIT_CLEAR_R_WMAC_RESP_TXPOWER_8197F(x) |                              \
+	 BIT_R_WMAC_RESP_TXPOWER_8197F(v))
+
+#define BIT_SHIFT_WMAC_RESP_TXANT_8197F 0
+#define BIT_MASK_WMAC_RESP_TXANT_8197F 0x3ffff
+#define BIT_WMAC_RESP_TXANT_8197F(x)                                           \
+	(((x) & BIT_MASK_WMAC_RESP_TXANT_8197F)                                \
+	 << BIT_SHIFT_WMAC_RESP_TXANT_8197F)
+#define BITS_WMAC_RESP_TXANT_8197F                                             \
+	(BIT_MASK_WMAC_RESP_TXANT_8197F << BIT_SHIFT_WMAC_RESP_TXANT_8197F)
+#define BIT_CLEAR_WMAC_RESP_TXANT_8197F(x) ((x) & (~BITS_WMAC_RESP_TXANT_8197F))
+#define BIT_GET_WMAC_RESP_TXANT_8197F(x)                                       \
+	(((x) >> BIT_SHIFT_WMAC_RESP_TXANT_8197F) &                            \
+	 BIT_MASK_WMAC_RESP_TXANT_8197F)
+#define BIT_SET_WMAC_RESP_TXANT_8197F(x, v)                                    \
+	(BIT_CLEAR_WMAC_RESP_TXANT_8197F(x) | BIT_WMAC_RESP_TXANT_8197F(v))
+
+/* 2 REG_BBPSF_CTRL_8197F */
+#define BIT_CTL_IDLE_CLR_CSI_RPT_8197F BIT(31)
+#define BIT_WMAC_USE_NDPARATE_8197F BIT(30)
+
+#define BIT_SHIFT_WMAC_CSI_RATE_8197F 24
+#define BIT_MASK_WMAC_CSI_RATE_8197F 0x3f
+#define BIT_WMAC_CSI_RATE_8197F(x)                                             \
+	(((x) & BIT_MASK_WMAC_CSI_RATE_8197F) << BIT_SHIFT_WMAC_CSI_RATE_8197F)
+#define BITS_WMAC_CSI_RATE_8197F                                               \
+	(BIT_MASK_WMAC_CSI_RATE_8197F << BIT_SHIFT_WMAC_CSI_RATE_8197F)
+#define BIT_CLEAR_WMAC_CSI_RATE_8197F(x) ((x) & (~BITS_WMAC_CSI_RATE_8197F))
+#define BIT_GET_WMAC_CSI_RATE_8197F(x)                                         \
+	(((x) >> BIT_SHIFT_WMAC_CSI_RATE_8197F) & BIT_MASK_WMAC_CSI_RATE_8197F)
+#define BIT_SET_WMAC_CSI_RATE_8197F(x, v)                                      \
+	(BIT_CLEAR_WMAC_CSI_RATE_8197F(x) | BIT_WMAC_CSI_RATE_8197F(v))
+
+#define BIT_SHIFT_WMAC_RESP_TXRATE_8197F 16
+#define BIT_MASK_WMAC_RESP_TXRATE_8197F 0xff
+#define BIT_WMAC_RESP_TXRATE_8197F(x)                                          \
+	(((x) & BIT_MASK_WMAC_RESP_TXRATE_8197F)                               \
+	 << BIT_SHIFT_WMAC_RESP_TXRATE_8197F)
+#define BITS_WMAC_RESP_TXRATE_8197F                                            \
+	(BIT_MASK_WMAC_RESP_TXRATE_8197F << BIT_SHIFT_WMAC_RESP_TXRATE_8197F)
+#define BIT_CLEAR_WMAC_RESP_TXRATE_8197F(x)                                    \
+	((x) & (~BITS_WMAC_RESP_TXRATE_8197F))
+#define BIT_GET_WMAC_RESP_TXRATE_8197F(x)                                      \
+	(((x) >> BIT_SHIFT_WMAC_RESP_TXRATE_8197F) &                           \
+	 BIT_MASK_WMAC_RESP_TXRATE_8197F)
+#define BIT_SET_WMAC_RESP_TXRATE_8197F(x, v)                                   \
+	(BIT_CLEAR_WMAC_RESP_TXRATE_8197F(x) | BIT_WMAC_RESP_TXRATE_8197F(v))
+
+#define BIT_BBPSF_MPDUCHKEN_8197F BIT(5)
+#define BIT_BBPSF_MHCHKEN_8197F BIT(4)
+#define BIT_BBPSF_ERRCHKEN_8197F BIT(3)
+
+#define BIT_SHIFT_BBPSF_ERRTHR_8197F 0
+#define BIT_MASK_BBPSF_ERRTHR_8197F 0x7
+#define BIT_BBPSF_ERRTHR_8197F(x)                                              \
+	(((x) & BIT_MASK_BBPSF_ERRTHR_8197F) << BIT_SHIFT_BBPSF_ERRTHR_8197F)
+#define BITS_BBPSF_ERRTHR_8197F                                                \
+	(BIT_MASK_BBPSF_ERRTHR_8197F << BIT_SHIFT_BBPSF_ERRTHR_8197F)
+#define BIT_CLEAR_BBPSF_ERRTHR_8197F(x) ((x) & (~BITS_BBPSF_ERRTHR_8197F))
+#define BIT_GET_BBPSF_ERRTHR_8197F(x)                                          \
+	(((x) >> BIT_SHIFT_BBPSF_ERRTHR_8197F) & BIT_MASK_BBPSF_ERRTHR_8197F)
+#define BIT_SET_BBPSF_ERRTHR_8197F(x, v)                                       \
+	(BIT_CLEAR_BBPSF_ERRTHR_8197F(x) | BIT_BBPSF_ERRTHR_8197F(v))
+
+/* 2 REG_NOT_VALID_8197F */
+
+/* 2 REG_P2P_RX_BCN_NOA_8197F (P2P RX BEACON NOA REGISTER) */
+#define BIT_NOA_PARSER_EN_8197F BIT(15)
+
+#define BIT_SHIFT_BSSID_SEL_V1_8197F 12
+#define BIT_MASK_BSSID_SEL_V1_8197F 0x7
+#define BIT_BSSID_SEL_V1_8197F(x)                                              \
+	(((x) & BIT_MASK_BSSID_SEL_V1_8197F) << BIT_SHIFT_BSSID_SEL_V1_8197F)
+#define BITS_BSSID_SEL_V1_8197F                                                \
+	(BIT_MASK_BSSID_SEL_V1_8197F << BIT_SHIFT_BSSID_SEL_V1_8197F)
+#define BIT_CLEAR_BSSID_SEL_V1_8197F(x) ((x) & (~BITS_BSSID_SEL_V1_8197F))
+#define BIT_GET_BSSID_SEL_V1_8197F(x)                                          \
+	(((x) >> BIT_SHIFT_BSSID_SEL_V1_8197F) & BIT_MASK_BSSID_SEL_V1_8197F)
+#define BIT_SET_BSSID_SEL_V1_8197F(x, v)                                       \
+	(BIT_CLEAR_BSSID_SEL_V1_8197F(x) | BIT_BSSID_SEL_V1_8197F(v))
+
+#define BIT_SHIFT_P2P_OUI_TYPE_8197F 0
+#define BIT_MASK_P2P_OUI_TYPE_8197F 0xff
+#define BIT_P2P_OUI_TYPE_8197F(x)                                              \
+	(((x) & BIT_MASK_P2P_OUI_TYPE_8197F) << BIT_SHIFT_P2P_OUI_TYPE_8197F)
+#define BITS_P2P_OUI_TYPE_8197F                                                \
+	(BIT_MASK_P2P_OUI_TYPE_8197F << BIT_SHIFT_P2P_OUI_TYPE_8197F)
+#define BIT_CLEAR_P2P_OUI_TYPE_8197F(x) ((x) & (~BITS_P2P_OUI_TYPE_8197F))
+#define BIT_GET_P2P_OUI_TYPE_8197F(x)                                          \
+	(((x) >> BIT_SHIFT_P2P_OUI_TYPE_8197F) & BIT_MASK_P2P_OUI_TYPE_8197F)
+#define BIT_SET_P2P_OUI_TYPE_8197F(x, v)                                       \
+	(BIT_CLEAR_P2P_OUI_TYPE_8197F(x) | BIT_P2P_OUI_TYPE_8197F(v))
+
+/* 2 REG_ASSOCIATED_BFMER0_INFO_8197F (ASSOCIATED BEAMFORMER0 INFO REGISTER) */
+
+#define BIT_SHIFT_R_WMAC_TXCSI_AID0_8197F (48 & CPU_OPT_WIDTH)
+#define BIT_MASK_R_WMAC_TXCSI_AID0_8197F 0x1ff
+#define BIT_R_WMAC_TXCSI_AID0_8197F(x)                                         \
+	(((x) & BIT_MASK_R_WMAC_TXCSI_AID0_8197F)                              \
+	 << BIT_SHIFT_R_WMAC_TXCSI_AID0_8197F)
+#define BITS_R_WMAC_TXCSI_AID0_8197F                                           \
+	(BIT_MASK_R_WMAC_TXCSI_AID0_8197F << BIT_SHIFT_R_WMAC_TXCSI_AID0_8197F)
+#define BIT_CLEAR_R_WMAC_TXCSI_AID0_8197F(x)                                   \
+	((x) & (~BITS_R_WMAC_TXCSI_AID0_8197F))
+#define BIT_GET_R_WMAC_TXCSI_AID0_8197F(x)                                     \
+	(((x) >> BIT_SHIFT_R_WMAC_TXCSI_AID0_8197F) &                          \
+	 BIT_MASK_R_WMAC_TXCSI_AID0_8197F)
+#define BIT_SET_R_WMAC_TXCSI_AID0_8197F(x, v)                                  \
+	(BIT_CLEAR_R_WMAC_TXCSI_AID0_8197F(x) | BIT_R_WMAC_TXCSI_AID0_8197F(v))
+
+#define BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0_8197F 0
+#define BIT_MASK_R_WMAC_SOUNDING_RXADD_R0_8197F 0xffffffffffffL
+#define BIT_R_WMAC_SOUNDING_RXADD_R0_8197F(x)                                  \
+	(((x) & BIT_MASK_R_WMAC_SOUNDING_RXADD_R0_8197F)                       \
+	 << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0_8197F)
+#define BITS_R_WMAC_SOUNDING_RXADD_R0_8197F                                    \
+	(BIT_MASK_R_WMAC_SOUNDING_RXADD_R0_8197F                               \
+	 << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0_8197F)
+#define BIT_CLEAR_R_WMAC_SOUNDING_RXADD_R0_8197F(x)                            \
+	((x) & (~BITS_R_WMAC_SOUNDING_RXADD_R0_8197F))
+#define BIT_GET_R_WMAC_SOUNDING_RXADD_R0_8197F(x)                              \
+	(((x) >> BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0_8197F) &                   \
+	 BIT_MASK_R_WMAC_SOUNDING_RXADD_R0_8197F)
+#define BIT_SET_R_WMAC_SOUNDING_RXADD_R0_8197F(x, v)                           \
+	(BIT_CLEAR_R_WMAC_SOUNDING_RXADD_R0_8197F(x) |                         \
+	 BIT_R_WMAC_SOUNDING_RXADD_R0_8197F(v))
+
+/* 2 REG_ASSOCIATED_BFMER1_INFO_8197F (ASSOCIATED BEAMFORMER1 INFO REGISTER) */
+
+#define BIT_SHIFT_R_WMAC_TXCSI_AID1_8197F (48 & CPU_OPT_WIDTH)
+#define BIT_MASK_R_WMAC_TXCSI_AID1_8197F 0x1ff
+#define BIT_R_WMAC_TXCSI_AID1_8197F(x)                                         \
+	(((x) & BIT_MASK_R_WMAC_TXCSI_AID1_8197F)                              \
+	 << BIT_SHIFT_R_WMAC_TXCSI_AID1_8197F)
+#define BITS_R_WMAC_TXCSI_AID1_8197F                                           \
+	(BIT_MASK_R_WMAC_TXCSI_AID1_8197F << BIT_SHIFT_R_WMAC_TXCSI_AID1_8197F)
+#define BIT_CLEAR_R_WMAC_TXCSI_AID1_8197F(x)                                   \
+	((x) & (~BITS_R_WMAC_TXCSI_AID1_8197F))
+#define BIT_GET_R_WMAC_TXCSI_AID1_8197F(x)                                     \
+	(((x) >> BIT_SHIFT_R_WMAC_TXCSI_AID1_8197F) &                          \
+	 BIT_MASK_R_WMAC_TXCSI_AID1_8197F)
+#define BIT_SET_R_WMAC_TXCSI_AID1_8197F(x, v)                                  \
+	(BIT_CLEAR_R_WMAC_TXCSI_AID1_8197F(x) | BIT_R_WMAC_TXCSI_AID1_8197F(v))
+
+#define BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1_8197F 0
+#define BIT_MASK_R_WMAC_SOUNDING_RXADD_R1_8197F 0xffffffffffffL
+#define BIT_R_WMAC_SOUNDING_RXADD_R1_8197F(x)                                  \
+	(((x) & BIT_MASK_R_WMAC_SOUNDING_RXADD_R1_8197F)                       \
+	 << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1_8197F)
+#define BITS_R_WMAC_SOUNDING_RXADD_R1_8197F                                    \
+	(BIT_MASK_R_WMAC_SOUNDING_RXADD_R1_8197F                               \
+	 << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1_8197F)
+#define BIT_CLEAR_R_WMAC_SOUNDING_RXADD_R1_8197F(x)                            \
+	((x) & (~BITS_R_WMAC_SOUNDING_RXADD_R1_8197F))
+#define BIT_GET_R_WMAC_SOUNDING_RXADD_R1_8197F(x)                              \
+	(((x) >> BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1_8197F) &                   \
+	 BIT_MASK_R_WMAC_SOUNDING_RXADD_R1_8197F)
+#define BIT_SET_R_WMAC_SOUNDING_RXADD_R1_8197F(x, v)                           \
+	(BIT_CLEAR_R_WMAC_SOUNDING_RXADD_R1_8197F(x) |                         \
+	 BIT_R_WMAC_SOUNDING_RXADD_R1_8197F(v))
+
+/* 2 REG_NOT_VALID_8197F */
+
+/* 2 REG_NOT_VALID_8197F */
+
+/* 2 REG_NOT_VALID_8197F */
+
+/* 2 REG_NOT_VALID_8197F */
+
+/* 2 REG_NOT_VALID_8197F */
+
+/* 2 REG_TX_CSI_RPT_PARAM_BW20_8197F (TX CSI REPORT PARAMETER_BW20 REGISTER) */
+
+#define BIT_SHIFT_R_WMAC_BFINFO_20M_1_8197F 16
+#define BIT_MASK_R_WMAC_BFINFO_20M_1_8197F 0xfff
+#define BIT_R_WMAC_BFINFO_20M_1_8197F(x)                                       \
+	(((x) & BIT_MASK_R_WMAC_BFINFO_20M_1_8197F)                            \
+	 << BIT_SHIFT_R_WMAC_BFINFO_20M_1_8197F)
+#define BITS_R_WMAC_BFINFO_20M_1_8197F                                         \
+	(BIT_MASK_R_WMAC_BFINFO_20M_1_8197F                                    \
+	 << BIT_SHIFT_R_WMAC_BFINFO_20M_1_8197F)
+#define BIT_CLEAR_R_WMAC_BFINFO_20M_1_8197F(x)                                 \
+	((x) & (~BITS_R_WMAC_BFINFO_20M_1_8197F))
+#define BIT_GET_R_WMAC_BFINFO_20M_1_8197F(x)                                   \
+	(((x) >> BIT_SHIFT_R_WMAC_BFINFO_20M_1_8197F) &                        \
+	 BIT_MASK_R_WMAC_BFINFO_20M_1_8197F)
+#define BIT_SET_R_WMAC_BFINFO_20M_1_8197F(x, v)                                \
+	(BIT_CLEAR_R_WMAC_BFINFO_20M_1_8197F(x) |                              \
+	 BIT_R_WMAC_BFINFO_20M_1_8197F(v))
+
+#define BIT_SHIFT_R_WMAC_BFINFO_20M_0_8197F 0
+#define BIT_MASK_R_WMAC_BFINFO_20M_0_8197F 0xfff
+#define BIT_R_WMAC_BFINFO_20M_0_8197F(x)                                       \
+	(((x) & BIT_MASK_R_WMAC_BFINFO_20M_0_8197F)                            \
+	 << BIT_SHIFT_R_WMAC_BFINFO_20M_0_8197F)
+#define BITS_R_WMAC_BFINFO_20M_0_8197F                                         \
+	(BIT_MASK_R_WMAC_BFINFO_20M_0_8197F                                    \
+	 << BIT_SHIFT_R_WMAC_BFINFO_20M_0_8197F)
+#define BIT_CLEAR_R_WMAC_BFINFO_20M_0_8197F(x)                                 \
+	((x) & (~BITS_R_WMAC_BFINFO_20M_0_8197F))
+#define BIT_GET_R_WMAC_BFINFO_20M_0_8197F(x)                                   \
+	(((x) >> BIT_SHIFT_R_WMAC_BFINFO_20M_0_8197F) &                        \
+	 BIT_MASK_R_WMAC_BFINFO_20M_0_8197F)
+#define BIT_SET_R_WMAC_BFINFO_20M_0_8197F(x, v)                                \
+	(BIT_CLEAR_R_WMAC_BFINFO_20M_0_8197F(x) |                              \
+	 BIT_R_WMAC_BFINFO_20M_0_8197F(v))
+
+/* 2 REG_TX_CSI_RPT_PARAM_BW40_8197F (TX CSI REPORT PARAMETER_BW40 REGISTER) */
+
+#define BIT_SHIFT_WMAC_RESP_ANTCD_8197F 0
+#define BIT_MASK_WMAC_RESP_ANTCD_8197F 0xf
+#define BIT_WMAC_RESP_ANTCD_8197F(x)                                           \
+	(((x) & BIT_MASK_WMAC_RESP_ANTCD_8197F)                                \
+	 << BIT_SHIFT_WMAC_RESP_ANTCD_8197F)
+#define BITS_WMAC_RESP_ANTCD_8197F                                             \
+	(BIT_MASK_WMAC_RESP_ANTCD_8197F << BIT_SHIFT_WMAC_RESP_ANTCD_8197F)
+#define BIT_CLEAR_WMAC_RESP_ANTCD_8197F(x) ((x) & (~BITS_WMAC_RESP_ANTCD_8197F))
+#define BIT_GET_WMAC_RESP_ANTCD_8197F(x)                                       \
+	(((x) >> BIT_SHIFT_WMAC_RESP_ANTCD_8197F) &                            \
+	 BIT_MASK_WMAC_RESP_ANTCD_8197F)
+#define BIT_SET_WMAC_RESP_ANTCD_8197F(x, v)                                    \
+	(BIT_CLEAR_WMAC_RESP_ANTCD_8197F(x) | BIT_WMAC_RESP_ANTCD_8197F(v))
+
+/* 2 REG_TX_CSI_RPT_PARAM_BW80_8197F (TX CSI REPORT PARAMETER_BW80 REGISTER) */
+
+/* 2 REG_BCN_PSR_RPT2_8197F (BEACON PARSER REPORT REGISTER2) */
+
+#define BIT_SHIFT_DTIM_CNT2_8197F 24
+#define BIT_MASK_DTIM_CNT2_8197F 0xff
+#define BIT_DTIM_CNT2_8197F(x)                                                 \
+	(((x) & BIT_MASK_DTIM_CNT2_8197F) << BIT_SHIFT_DTIM_CNT2_8197F)
+#define BITS_DTIM_CNT2_8197F                                                   \
+	(BIT_MASK_DTIM_CNT2_8197F << BIT_SHIFT_DTIM_CNT2_8197F)
+#define BIT_CLEAR_DTIM_CNT2_8197F(x) ((x) & (~BITS_DTIM_CNT2_8197F))
+#define BIT_GET_DTIM_CNT2_8197F(x)                                             \
+	(((x) >> BIT_SHIFT_DTIM_CNT2_8197F) & BIT_MASK_DTIM_CNT2_8197F)
+#define BIT_SET_DTIM_CNT2_8197F(x, v)                                          \
+	(BIT_CLEAR_DTIM_CNT2_8197F(x) | BIT_DTIM_CNT2_8197F(v))
+
+#define BIT_SHIFT_DTIM_PERIOD2_8197F 16
+#define BIT_MASK_DTIM_PERIOD2_8197F 0xff
+#define BIT_DTIM_PERIOD2_8197F(x)                                              \
+	(((x) & BIT_MASK_DTIM_PERIOD2_8197F) << BIT_SHIFT_DTIM_PERIOD2_8197F)
+#define BITS_DTIM_PERIOD2_8197F                                                \
+	(BIT_MASK_DTIM_PERIOD2_8197F << BIT_SHIFT_DTIM_PERIOD2_8197F)
+#define BIT_CLEAR_DTIM_PERIOD2_8197F(x) ((x) & (~BITS_DTIM_PERIOD2_8197F))
+#define BIT_GET_DTIM_PERIOD2_8197F(x)                                          \
+	(((x) >> BIT_SHIFT_DTIM_PERIOD2_8197F) & BIT_MASK_DTIM_PERIOD2_8197F)
+#define BIT_SET_DTIM_PERIOD2_8197F(x, v)                                       \
+	(BIT_CLEAR_DTIM_PERIOD2_8197F(x) | BIT_DTIM_PERIOD2_8197F(v))
+
+#define BIT_DTIM2_8197F BIT(15)
+#define BIT_TIM2_8197F BIT(14)
+
+#define BIT_SHIFT_PS_AID_2_8197F 0
+#define BIT_MASK_PS_AID_2_8197F 0x7ff
+#define BIT_PS_AID_2_8197F(x)                                                  \
+	(((x) & BIT_MASK_PS_AID_2_8197F) << BIT_SHIFT_PS_AID_2_8197F)
+#define BITS_PS_AID_2_8197F                                                    \
+	(BIT_MASK_PS_AID_2_8197F << BIT_SHIFT_PS_AID_2_8197F)
+#define BIT_CLEAR_PS_AID_2_8197F(x) ((x) & (~BITS_PS_AID_2_8197F))
+#define BIT_GET_PS_AID_2_8197F(x)                                              \
+	(((x) >> BIT_SHIFT_PS_AID_2_8197F) & BIT_MASK_PS_AID_2_8197F)
+#define BIT_SET_PS_AID_2_8197F(x, v)                                           \
+	(BIT_CLEAR_PS_AID_2_8197F(x) | BIT_PS_AID_2_8197F(v))
+
+/* 2 REG_BCN_PSR_RPT3_8197F (BEACON PARSER REPORT REGISTER3) */
+
+#define BIT_SHIFT_DTIM_CNT3_8197F 24
+#define BIT_MASK_DTIM_CNT3_8197F 0xff
+#define BIT_DTIM_CNT3_8197F(x)                                                 \
+	(((x) & BIT_MASK_DTIM_CNT3_8197F) << BIT_SHIFT_DTIM_CNT3_8197F)
+#define BITS_DTIM_CNT3_8197F                                                   \
+	(BIT_MASK_DTIM_CNT3_8197F << BIT_SHIFT_DTIM_CNT3_8197F)
+#define BIT_CLEAR_DTIM_CNT3_8197F(x) ((x) & (~BITS_DTIM_CNT3_8197F))
+#define BIT_GET_DTIM_CNT3_8197F(x)                                             \
+	(((x) >> BIT_SHIFT_DTIM_CNT3_8197F) & BIT_MASK_DTIM_CNT3_8197F)
+#define BIT_SET_DTIM_CNT3_8197F(x, v)                                          \
+	(BIT_CLEAR_DTIM_CNT3_8197F(x) | BIT_DTIM_CNT3_8197F(v))
+
+#define BIT_SHIFT_DTIM_PERIOD3_8197F 16
+#define BIT_MASK_DTIM_PERIOD3_8197F 0xff
+#define BIT_DTIM_PERIOD3_8197F(x)                                              \
+	(((x) & BIT_MASK_DTIM_PERIOD3_8197F) << BIT_SHIFT_DTIM_PERIOD3_8197F)
+#define BITS_DTIM_PERIOD3_8197F                                                \
+	(BIT_MASK_DTIM_PERIOD3_8197F << BIT_SHIFT_DTIM_PERIOD3_8197F)
+#define BIT_CLEAR_DTIM_PERIOD3_8197F(x) ((x) & (~BITS_DTIM_PERIOD3_8197F))
+#define BIT_GET_DTIM_PERIOD3_8197F(x)                                          \
+	(((x) >> BIT_SHIFT_DTIM_PERIOD3_8197F) & BIT_MASK_DTIM_PERIOD3_8197F)
+#define BIT_SET_DTIM_PERIOD3_8197F(x, v)                                       \
+	(BIT_CLEAR_DTIM_PERIOD3_8197F(x) | BIT_DTIM_PERIOD3_8197F(v))
+
+#define BIT_DTIM3_8197F BIT(15)
+#define BIT_TIM3_8197F BIT(14)
+
+#define BIT_SHIFT_PS_AID_3_8197F 0
+#define BIT_MASK_PS_AID_3_8197F 0x7ff
+#define BIT_PS_AID_3_8197F(x)                                                  \
+	(((x) & BIT_MASK_PS_AID_3_8197F) << BIT_SHIFT_PS_AID_3_8197F)
+#define BITS_PS_AID_3_8197F                                                    \
+	(BIT_MASK_PS_AID_3_8197F << BIT_SHIFT_PS_AID_3_8197F)
+#define BIT_CLEAR_PS_AID_3_8197F(x) ((x) & (~BITS_PS_AID_3_8197F))
+#define BIT_GET_PS_AID_3_8197F(x)                                              \
+	(((x) >> BIT_SHIFT_PS_AID_3_8197F) & BIT_MASK_PS_AID_3_8197F)
+#define BIT_SET_PS_AID_3_8197F(x, v)                                           \
+	(BIT_CLEAR_PS_AID_3_8197F(x) | BIT_PS_AID_3_8197F(v))
+
+/* 2 REG_BCN_PSR_RPT4_8197F (BEACON PARSER REPORT REGISTER4) */
+
+#define BIT_SHIFT_DTIM_CNT4_8197F 24
+#define BIT_MASK_DTIM_CNT4_8197F 0xff
+#define BIT_DTIM_CNT4_8197F(x)                                                 \
+	(((x) & BIT_MASK_DTIM_CNT4_8197F) << BIT_SHIFT_DTIM_CNT4_8197F)
+#define BITS_DTIM_CNT4_8197F                                                   \
+	(BIT_MASK_DTIM_CNT4_8197F << BIT_SHIFT_DTIM_CNT4_8197F)
+#define BIT_CLEAR_DTIM_CNT4_8197F(x) ((x) & (~BITS_DTIM_CNT4_8197F))
+#define BIT_GET_DTIM_CNT4_8197F(x)                                             \
+	(((x) >> BIT_SHIFT_DTIM_CNT4_8197F) & BIT_MASK_DTIM_CNT4_8197F)
+#define BIT_SET_DTIM_CNT4_8197F(x, v)                                          \
+	(BIT_CLEAR_DTIM_CNT4_8197F(x) | BIT_DTIM_CNT4_8197F(v))
+
+#define BIT_SHIFT_DTIM_PERIOD4_8197F 16
+#define BIT_MASK_DTIM_PERIOD4_8197F 0xff
+#define BIT_DTIM_PERIOD4_8197F(x)                                              \
+	(((x) & BIT_MASK_DTIM_PERIOD4_8197F) << BIT_SHIFT_DTIM_PERIOD4_8197F)
+#define BITS_DTIM_PERIOD4_8197F                                                \
+	(BIT_MASK_DTIM_PERIOD4_8197F << BIT_SHIFT_DTIM_PERIOD4_8197F)
+#define BIT_CLEAR_DTIM_PERIOD4_8197F(x) ((x) & (~BITS_DTIM_PERIOD4_8197F))
+#define BIT_GET_DTIM_PERIOD4_8197F(x)                                          \
+	(((x) >> BIT_SHIFT_DTIM_PERIOD4_8197F) & BIT_MASK_DTIM_PERIOD4_8197F)
+#define BIT_SET_DTIM_PERIOD4_8197F(x, v)                                       \
+	(BIT_CLEAR_DTIM_PERIOD4_8197F(x) | BIT_DTIM_PERIOD4_8197F(v))
+
+#define BIT_DTIM4_8197F BIT(15)
+#define BIT_TIM4_8197F BIT(14)
+
+#define BIT_SHIFT_PS_AID_4_8197F 0
+#define BIT_MASK_PS_AID_4_8197F 0x7ff
+#define BIT_PS_AID_4_8197F(x)                                                  \
+	(((x) & BIT_MASK_PS_AID_4_8197F) << BIT_SHIFT_PS_AID_4_8197F)
+#define BITS_PS_AID_4_8197F                                                    \
+	(BIT_MASK_PS_AID_4_8197F << BIT_SHIFT_PS_AID_4_8197F)
+#define BIT_CLEAR_PS_AID_4_8197F(x) ((x) & (~BITS_PS_AID_4_8197F))
+#define BIT_GET_PS_AID_4_8197F(x)                                              \
+	(((x) >> BIT_SHIFT_PS_AID_4_8197F) & BIT_MASK_PS_AID_4_8197F)
+#define BIT_SET_PS_AID_4_8197F(x, v)                                           \
+	(BIT_CLEAR_PS_AID_4_8197F(x) | BIT_PS_AID_4_8197F(v))
+
+/* 2 REG_A1_ADDR_MASK_8197F (A1 ADDR MASK REGISTER) */
+
+#define BIT_SHIFT_A1_ADDR_MASK_8197F 0
+#define BIT_MASK_A1_ADDR_MASK_8197F 0xffffffffL
+#define BIT_A1_ADDR_MASK_8197F(x)                                              \
+	(((x) & BIT_MASK_A1_ADDR_MASK_8197F) << BIT_SHIFT_A1_ADDR_MASK_8197F)
+#define BITS_A1_ADDR_MASK_8197F                                                \
+	(BIT_MASK_A1_ADDR_MASK_8197F << BIT_SHIFT_A1_ADDR_MASK_8197F)
+#define BIT_CLEAR_A1_ADDR_MASK_8197F(x) ((x) & (~BITS_A1_ADDR_MASK_8197F))
+#define BIT_GET_A1_ADDR_MASK_8197F(x)                                          \
+	(((x) >> BIT_SHIFT_A1_ADDR_MASK_8197F) & BIT_MASK_A1_ADDR_MASK_8197F)
+#define BIT_SET_A1_ADDR_MASK_8197F(x, v)                                       \
+	(BIT_CLEAR_A1_ADDR_MASK_8197F(x) | BIT_A1_ADDR_MASK_8197F(v))
+
+/* 2 REG_MACID2_8197F (MAC ID2 REGISTER) */
+
+#define BIT_SHIFT_MACID2_8197F 0
+#define BIT_MASK_MACID2_8197F 0xffffffffffffL
+#define BIT_MACID2_8197F(x)                                                    \
+	(((x) & BIT_MASK_MACID2_8197F) << BIT_SHIFT_MACID2_8197F)
+#define BITS_MACID2_8197F (BIT_MASK_MACID2_8197F << BIT_SHIFT_MACID2_8197F)
+#define BIT_CLEAR_MACID2_8197F(x) ((x) & (~BITS_MACID2_8197F))
+#define BIT_GET_MACID2_8197F(x)                                                \
+	(((x) >> BIT_SHIFT_MACID2_8197F) & BIT_MASK_MACID2_8197F)
+#define BIT_SET_MACID2_8197F(x, v)                                             \
+	(BIT_CLEAR_MACID2_8197F(x) | BIT_MACID2_8197F(v))
+
+/* 2 REG_BSSID2_8197F (BSSID2 REGISTER) */
+
+#define BIT_SHIFT_BSSID2_8197F 0
+#define BIT_MASK_BSSID2_8197F 0xffffffffffffL
+#define BIT_BSSID2_8197F(x)                                                    \
+	(((x) & BIT_MASK_BSSID2_8197F) << BIT_SHIFT_BSSID2_8197F)
+#define BITS_BSSID2_8197F (BIT_MASK_BSSID2_8197F << BIT_SHIFT_BSSID2_8197F)
+#define BIT_CLEAR_BSSID2_8197F(x) ((x) & (~BITS_BSSID2_8197F))
+#define BIT_GET_BSSID2_8197F(x)                                                \
+	(((x) >> BIT_SHIFT_BSSID2_8197F) & BIT_MASK_BSSID2_8197F)
+#define BIT_SET_BSSID2_8197F(x, v)                                             \
+	(BIT_CLEAR_BSSID2_8197F(x) | BIT_BSSID2_8197F(v))
+
+/* 2 REG_MACID3_8197F (MAC ID3 REGISTER) */
+
+#define BIT_SHIFT_MACID3_8197F 0
+#define BIT_MASK_MACID3_8197F 0xffffffffffffL
+#define BIT_MACID3_8197F(x)                                                    \
+	(((x) & BIT_MASK_MACID3_8197F) << BIT_SHIFT_MACID3_8197F)
+#define BITS_MACID3_8197F (BIT_MASK_MACID3_8197F << BIT_SHIFT_MACID3_8197F)
+#define BIT_CLEAR_MACID3_8197F(x) ((x) & (~BITS_MACID3_8197F))
+#define BIT_GET_MACID3_8197F(x)                                                \
+	(((x) >> BIT_SHIFT_MACID3_8197F) & BIT_MASK_MACID3_8197F)
+#define BIT_SET_MACID3_8197F(x, v)                                             \
+	(BIT_CLEAR_MACID3_8197F(x) | BIT_MACID3_8197F(v))
+
+/* 2 REG_BSSID3_8197F (BSSID3 REGISTER) */
+
+#define BIT_SHIFT_BSSID3_8197F 0
+#define BIT_MASK_BSSID3_8197F 0xffffffffffffL
+#define BIT_BSSID3_8197F(x)                                                    \
+	(((x) & BIT_MASK_BSSID3_8197F) << BIT_SHIFT_BSSID3_8197F)
+#define BITS_BSSID3_8197F (BIT_MASK_BSSID3_8197F << BIT_SHIFT_BSSID3_8197F)
+#define BIT_CLEAR_BSSID3_8197F(x) ((x) & (~BITS_BSSID3_8197F))
+#define BIT_GET_BSSID3_8197F(x)                                                \
+	(((x) >> BIT_SHIFT_BSSID3_8197F) & BIT_MASK_BSSID3_8197F)
+#define BIT_SET_BSSID3_8197F(x, v)                                             \
+	(BIT_CLEAR_BSSID3_8197F(x) | BIT_BSSID3_8197F(v))
+
+/* 2 REG_MACID4_8197F (MAC ID4 REGISTER) */
+
+#define BIT_SHIFT_MACID4_8197F 0
+#define BIT_MASK_MACID4_8197F 0xffffffffffffL
+#define BIT_MACID4_8197F(x)                                                    \
+	(((x) & BIT_MASK_MACID4_8197F) << BIT_SHIFT_MACID4_8197F)
+#define BITS_MACID4_8197F (BIT_MASK_MACID4_8197F << BIT_SHIFT_MACID4_8197F)
+#define BIT_CLEAR_MACID4_8197F(x) ((x) & (~BITS_MACID4_8197F))
+#define BIT_GET_MACID4_8197F(x)                                                \
+	(((x) >> BIT_SHIFT_MACID4_8197F) & BIT_MASK_MACID4_8197F)
+#define BIT_SET_MACID4_8197F(x, v)                                             \
+	(BIT_CLEAR_MACID4_8197F(x) | BIT_MACID4_8197F(v))
+
+/* 2 REG_BSSID4_8197F (BSSID4 REGISTER) */
+
+#define BIT_SHIFT_BSSID4_8197F 0
+#define BIT_MASK_BSSID4_8197F 0xffffffffffffL
+#define BIT_BSSID4_8197F(x)                                                    \
+	(((x) & BIT_MASK_BSSID4_8197F) << BIT_SHIFT_BSSID4_8197F)
+#define BITS_BSSID4_8197F (BIT_MASK_BSSID4_8197F << BIT_SHIFT_BSSID4_8197F)
+#define BIT_CLEAR_BSSID4_8197F(x) ((x) & (~BITS_BSSID4_8197F))
+#define BIT_GET_BSSID4_8197F(x)                                                \
+	(((x) >> BIT_SHIFT_BSSID4_8197F) & BIT_MASK_BSSID4_8197F)
+#define BIT_SET_BSSID4_8197F(x, v)                                             \
+	(BIT_CLEAR_BSSID4_8197F(x) | BIT_BSSID4_8197F(v))
+
+/* 2 REG_NOA_REPORT_8197F */
+
+/* 2 REG_PWRBIT_SETTING_8197F */
+#define BIT_CLI3_PWRBIT_OW_EN_8197F BIT(7)
+#define BIT_CLI3_PWR_ST_8197F BIT(6)
+#define BIT_CLI2_PWRBIT_OW_EN_8197F BIT(5)
+#define BIT_CLI2_PWR_ST_8197F BIT(4)
+#define BIT_CLI1_PWRBIT_OW_EN_8197F BIT(3)
+#define BIT_CLI1_PWR_ST_8197F BIT(2)
+#define BIT_CLI0_PWRBIT_OW_EN_8197F BIT(1)
+#define BIT_CLI0_PWR_ST_8197F BIT(0)
+
+/* 2 REG_WMAC_MU_BF_OPTION_8197F */
+#define BIT_WMAC_RESP_NONSTA1_DIS_8197F BIT(7)
+#define BIT_BIT_WMAC_TXMU_ACKPOLICY_EN_8197F BIT(6)
+
+#define BIT_SHIFT_WMAC_TXMU_ACKPOLICY_8197F 4
+#define BIT_MASK_WMAC_TXMU_ACKPOLICY_8197F 0x3
+#define BIT_WMAC_TXMU_ACKPOLICY_8197F(x)                                       \
+	(((x) & BIT_MASK_WMAC_TXMU_ACKPOLICY_8197F)                            \
+	 << BIT_SHIFT_WMAC_TXMU_ACKPOLICY_8197F)
+#define BITS_WMAC_TXMU_ACKPOLICY_8197F                                         \
+	(BIT_MASK_WMAC_TXMU_ACKPOLICY_8197F                                    \
+	 << BIT_SHIFT_WMAC_TXMU_ACKPOLICY_8197F)
+#define BIT_CLEAR_WMAC_TXMU_ACKPOLICY_8197F(x)                                 \
+	((x) & (~BITS_WMAC_TXMU_ACKPOLICY_8197F))
+#define BIT_GET_WMAC_TXMU_ACKPOLICY_8197F(x)                                   \
+	(((x) >> BIT_SHIFT_WMAC_TXMU_ACKPOLICY_8197F) &                        \
+	 BIT_MASK_WMAC_TXMU_ACKPOLICY_8197F)
+#define BIT_SET_WMAC_TXMU_ACKPOLICY_8197F(x, v)                                \
+	(BIT_CLEAR_WMAC_TXMU_ACKPOLICY_8197F(x) |                              \
+	 BIT_WMAC_TXMU_ACKPOLICY_8197F(v))
+
+#define BIT_SHIFT_WMAC_MU_BFEE_PORT_SEL_8197F 1
+#define BIT_MASK_WMAC_MU_BFEE_PORT_SEL_8197F 0x7
+#define BIT_WMAC_MU_BFEE_PORT_SEL_8197F(x)                                     \
+	(((x) & BIT_MASK_WMAC_MU_BFEE_PORT_SEL_8197F)                          \
+	 << BIT_SHIFT_WMAC_MU_BFEE_PORT_SEL_8197F)
+#define BITS_WMAC_MU_BFEE_PORT_SEL_8197F                                       \
+	(BIT_MASK_WMAC_MU_BFEE_PORT_SEL_8197F                                  \
+	 << BIT_SHIFT_WMAC_MU_BFEE_PORT_SEL_8197F)
+#define BIT_CLEAR_WMAC_MU_BFEE_PORT_SEL_8197F(x)                               \
+	((x) & (~BITS_WMAC_MU_BFEE_PORT_SEL_8197F))
+#define BIT_GET_WMAC_MU_BFEE_PORT_SEL_8197F(x)                                 \
+	(((x) >> BIT_SHIFT_WMAC_MU_BFEE_PORT_SEL_8197F) &                      \
+	 BIT_MASK_WMAC_MU_BFEE_PORT_SEL_8197F)
+#define BIT_SET_WMAC_MU_BFEE_PORT_SEL_8197F(x, v)                              \
+	(BIT_CLEAR_WMAC_MU_BFEE_PORT_SEL_8197F(x) |                            \
+	 BIT_WMAC_MU_BFEE_PORT_SEL_8197F(v))
+
+#define BIT_WMAC_MU_BFEE_DIS_8197F BIT(0)
+
+/* 2 REG_WMAC_PAUSE_BB_CLR_TH_8197F */
+
+#define BIT_SHIFT_WMAC_PAUSE_BB_CLR_TH_8197F 0
+#define BIT_MASK_WMAC_PAUSE_BB_CLR_TH_8197F 0xff
+#define BIT_WMAC_PAUSE_BB_CLR_TH_8197F(x)                                      \
+	(((x) & BIT_MASK_WMAC_PAUSE_BB_CLR_TH_8197F)                           \
+	 << BIT_SHIFT_WMAC_PAUSE_BB_CLR_TH_8197F)
+#define BITS_WMAC_PAUSE_BB_CLR_TH_8197F                                        \
+	(BIT_MASK_WMAC_PAUSE_BB_CLR_TH_8197F                                   \
+	 << BIT_SHIFT_WMAC_PAUSE_BB_CLR_TH_8197F)
+#define BIT_CLEAR_WMAC_PAUSE_BB_CLR_TH_8197F(x)                                \
+	((x) & (~BITS_WMAC_PAUSE_BB_CLR_TH_8197F))
+#define BIT_GET_WMAC_PAUSE_BB_CLR_TH_8197F(x)                                  \
+	(((x) >> BIT_SHIFT_WMAC_PAUSE_BB_CLR_TH_8197F) &                       \
+	 BIT_MASK_WMAC_PAUSE_BB_CLR_TH_8197F)
+#define BIT_SET_WMAC_PAUSE_BB_CLR_TH_8197F(x, v)                               \
+	(BIT_CLEAR_WMAC_PAUSE_BB_CLR_TH_8197F(x) |                             \
+	 BIT_WMAC_PAUSE_BB_CLR_TH_8197F(v))
+
+/* 2 REG_WMAC_MU_ARB_8197F */
+#define BIT_WMAC_ARB_HW_ADAPT_EN_8197F BIT(7)
+#define BIT_WMAC_ARB_SW_EN_8197F BIT(6)
+
+#define BIT_SHIFT_WMAC_ARB_SW_STATE_8197F 0
+#define BIT_MASK_WMAC_ARB_SW_STATE_8197F 0x3f
+#define BIT_WMAC_ARB_SW_STATE_8197F(x)                                         \
+	(((x) & BIT_MASK_WMAC_ARB_SW_STATE_8197F)                              \
+	 << BIT_SHIFT_WMAC_ARB_SW_STATE_8197F)
+#define BITS_WMAC_ARB_SW_STATE_8197F                                           \
+	(BIT_MASK_WMAC_ARB_SW_STATE_8197F << BIT_SHIFT_WMAC_ARB_SW_STATE_8197F)
+#define BIT_CLEAR_WMAC_ARB_SW_STATE_8197F(x)                                   \
+	((x) & (~BITS_WMAC_ARB_SW_STATE_8197F))
+#define BIT_GET_WMAC_ARB_SW_STATE_8197F(x)                                     \
+	(((x) >> BIT_SHIFT_WMAC_ARB_SW_STATE_8197F) &                          \
+	 BIT_MASK_WMAC_ARB_SW_STATE_8197F)
+#define BIT_SET_WMAC_ARB_SW_STATE_8197F(x, v)                                  \
+	(BIT_CLEAR_WMAC_ARB_SW_STATE_8197F(x) | BIT_WMAC_ARB_SW_STATE_8197F(v))
+
+/* 2 REG_WMAC_MU_OPTION_8197F */
+
+#define BIT_SHIFT_WMAC_MU_DBGSEL_8197F 5
+#define BIT_MASK_WMAC_MU_DBGSEL_8197F 0x3
+#define BIT_WMAC_MU_DBGSEL_8197F(x)                                            \
+	(((x) & BIT_MASK_WMAC_MU_DBGSEL_8197F)                                 \
+	 << BIT_SHIFT_WMAC_MU_DBGSEL_8197F)
+#define BITS_WMAC_MU_DBGSEL_8197F                                              \
+	(BIT_MASK_WMAC_MU_DBGSEL_8197F << BIT_SHIFT_WMAC_MU_DBGSEL_8197F)
+#define BIT_CLEAR_WMAC_MU_DBGSEL_8197F(x) ((x) & (~BITS_WMAC_MU_DBGSEL_8197F))
+#define BIT_GET_WMAC_MU_DBGSEL_8197F(x)                                        \
+	(((x) >> BIT_SHIFT_WMAC_MU_DBGSEL_8197F) &                             \
+	 BIT_MASK_WMAC_MU_DBGSEL_8197F)
+#define BIT_SET_WMAC_MU_DBGSEL_8197F(x, v)                                     \
+	(BIT_CLEAR_WMAC_MU_DBGSEL_8197F(x) | BIT_WMAC_MU_DBGSEL_8197F(v))
+
+#define BIT_SHIFT_WMAC_MU_CPRD_TIMEOUT_8197F 0
+#define BIT_MASK_WMAC_MU_CPRD_TIMEOUT_8197F 0x1f
+#define BIT_WMAC_MU_CPRD_TIMEOUT_8197F(x)                                      \
+	(((x) & BIT_MASK_WMAC_MU_CPRD_TIMEOUT_8197F)                           \
+	 << BIT_SHIFT_WMAC_MU_CPRD_TIMEOUT_8197F)
+#define BITS_WMAC_MU_CPRD_TIMEOUT_8197F                                        \
+	(BIT_MASK_WMAC_MU_CPRD_TIMEOUT_8197F                                   \
+	 << BIT_SHIFT_WMAC_MU_CPRD_TIMEOUT_8197F)
+#define BIT_CLEAR_WMAC_MU_CPRD_TIMEOUT_8197F(x)                                \
+	((x) & (~BITS_WMAC_MU_CPRD_TIMEOUT_8197F))
+#define BIT_GET_WMAC_MU_CPRD_TIMEOUT_8197F(x)                                  \
+	(((x) >> BIT_SHIFT_WMAC_MU_CPRD_TIMEOUT_8197F) &                       \
+	 BIT_MASK_WMAC_MU_CPRD_TIMEOUT_8197F)
+#define BIT_SET_WMAC_MU_CPRD_TIMEOUT_8197F(x, v)                               \
+	(BIT_CLEAR_WMAC_MU_CPRD_TIMEOUT_8197F(x) |                             \
+	 BIT_WMAC_MU_CPRD_TIMEOUT_8197F(v))
+
+/* 2 REG_WMAC_MU_BF_CTL_8197F */
+#define BIT_WMAC_INVLD_BFPRT_CHK_8197F BIT(15)
+#define BIT_WMAC_RETXBFRPTSEQ_UPD_8197F BIT(14)
+
+#define BIT_SHIFT_WMAC_MU_BFRPTSEG_SEL_8197F 12
+#define BIT_MASK_WMAC_MU_BFRPTSEG_SEL_8197F 0x3
+#define BIT_WMAC_MU_BFRPTSEG_SEL_8197F(x)                                      \
+	(((x) & BIT_MASK_WMAC_MU_BFRPTSEG_SEL_8197F)                           \
+	 << BIT_SHIFT_WMAC_MU_BFRPTSEG_SEL_8197F)
+#define BITS_WMAC_MU_BFRPTSEG_SEL_8197F                                        \
+	(BIT_MASK_WMAC_MU_BFRPTSEG_SEL_8197F                                   \
+	 << BIT_SHIFT_WMAC_MU_BFRPTSEG_SEL_8197F)
+#define BIT_CLEAR_WMAC_MU_BFRPTSEG_SEL_8197F(x)                                \
+	((x) & (~BITS_WMAC_MU_BFRPTSEG_SEL_8197F))
+#define BIT_GET_WMAC_MU_BFRPTSEG_SEL_8197F(x)                                  \
+	(((x) >> BIT_SHIFT_WMAC_MU_BFRPTSEG_SEL_8197F) &                       \
+	 BIT_MASK_WMAC_MU_BFRPTSEG_SEL_8197F)
+#define BIT_SET_WMAC_MU_BFRPTSEG_SEL_8197F(x, v)                               \
+	(BIT_CLEAR_WMAC_MU_BFRPTSEG_SEL_8197F(x) |                             \
+	 BIT_WMAC_MU_BFRPTSEG_SEL_8197F(v))
+
+#define BIT_SHIFT_WMAC_MU_BF_MYAID_8197F 0
+#define BIT_MASK_WMAC_MU_BF_MYAID_8197F 0xfff
+#define BIT_WMAC_MU_BF_MYAID_8197F(x)                                          \
+	(((x) & BIT_MASK_WMAC_MU_BF_MYAID_8197F)                               \
+	 << BIT_SHIFT_WMAC_MU_BF_MYAID_8197F)
+#define BITS_WMAC_MU_BF_MYAID_8197F                                            \
+	(BIT_MASK_WMAC_MU_BF_MYAID_8197F << BIT_SHIFT_WMAC_MU_BF_MYAID_8197F)
+#define BIT_CLEAR_WMAC_MU_BF_MYAID_8197F(x)                                    \
+	((x) & (~BITS_WMAC_MU_BF_MYAID_8197F))
+#define BIT_GET_WMAC_MU_BF_MYAID_8197F(x)                                      \
+	(((x) >> BIT_SHIFT_WMAC_MU_BF_MYAID_8197F) &                           \
+	 BIT_MASK_WMAC_MU_BF_MYAID_8197F)
+#define BIT_SET_WMAC_MU_BF_MYAID_8197F(x, v)                                   \
+	(BIT_CLEAR_WMAC_MU_BF_MYAID_8197F(x) | BIT_WMAC_MU_BF_MYAID_8197F(v))
+
+/* 2 REG_WMAC_MU_BFRPT_PARA_8197F */
+
+#define BIT_SHIFT_BFRPT_PARA_USERID_SEL_8197F 12
+#define BIT_MASK_BFRPT_PARA_USERID_SEL_8197F 0x7
+#define BIT_BFRPT_PARA_USERID_SEL_8197F(x)                                     \
+	(((x) & BIT_MASK_BFRPT_PARA_USERID_SEL_8197F)                          \
+	 << BIT_SHIFT_BFRPT_PARA_USERID_SEL_8197F)
+#define BITS_BFRPT_PARA_USERID_SEL_8197F                                       \
+	(BIT_MASK_BFRPT_PARA_USERID_SEL_8197F                                  \
+	 << BIT_SHIFT_BFRPT_PARA_USERID_SEL_8197F)
+#define BIT_CLEAR_BFRPT_PARA_USERID_SEL_8197F(x)                               \
+	((x) & (~BITS_BFRPT_PARA_USERID_SEL_8197F))
+#define BIT_GET_BFRPT_PARA_USERID_SEL_8197F(x)                                 \
+	(((x) >> BIT_SHIFT_BFRPT_PARA_USERID_SEL_8197F) &                      \
+	 BIT_MASK_BFRPT_PARA_USERID_SEL_8197F)
+#define BIT_SET_BFRPT_PARA_USERID_SEL_8197F(x, v)                              \
+	(BIT_CLEAR_BFRPT_PARA_USERID_SEL_8197F(x) |                            \
+	 BIT_BFRPT_PARA_USERID_SEL_8197F(v))
+
+#define BIT_SHIFT_BFRPT_PARA_8197F 0
+#define BIT_MASK_BFRPT_PARA_8197F 0xfff
+#define BIT_BFRPT_PARA_8197F(x)                                                \
+	(((x) & BIT_MASK_BFRPT_PARA_8197F) << BIT_SHIFT_BFRPT_PARA_8197F)
+#define BITS_BFRPT_PARA_8197F                                                  \
+	(BIT_MASK_BFRPT_PARA_8197F << BIT_SHIFT_BFRPT_PARA_8197F)
+#define BIT_CLEAR_BFRPT_PARA_8197F(x) ((x) & (~BITS_BFRPT_PARA_8197F))
+#define BIT_GET_BFRPT_PARA_8197F(x)                                            \
+	(((x) >> BIT_SHIFT_BFRPT_PARA_8197F) & BIT_MASK_BFRPT_PARA_8197F)
+#define BIT_SET_BFRPT_PARA_8197F(x, v)                                         \
+	(BIT_CLEAR_BFRPT_PARA_8197F(x) | BIT_BFRPT_PARA_8197F(v))
+
+/* 2 REG_WMAC_ASSOCIATED_MU_BFMEE2_8197F */
+#define BIT_STATUS_BFEE2_8197F BIT(10)
+#define BIT_WMAC_MU_BFEE2_EN_8197F BIT(9)
+
+#define BIT_SHIFT_WMAC_MU_BFEE2_AID_8197F 0
+#define BIT_MASK_WMAC_MU_BFEE2_AID_8197F 0x1ff
+#define BIT_WMAC_MU_BFEE2_AID_8197F(x)                                         \
+	(((x) & BIT_MASK_WMAC_MU_BFEE2_AID_8197F)                              \
+	 << BIT_SHIFT_WMAC_MU_BFEE2_AID_8197F)
+#define BITS_WMAC_MU_BFEE2_AID_8197F                                           \
+	(BIT_MASK_WMAC_MU_BFEE2_AID_8197F << BIT_SHIFT_WMAC_MU_BFEE2_AID_8197F)
+#define BIT_CLEAR_WMAC_MU_BFEE2_AID_8197F(x)                                   \
+	((x) & (~BITS_WMAC_MU_BFEE2_AID_8197F))
+#define BIT_GET_WMAC_MU_BFEE2_AID_8197F(x)                                     \
+	(((x) >> BIT_SHIFT_WMAC_MU_BFEE2_AID_8197F) &                          \
+	 BIT_MASK_WMAC_MU_BFEE2_AID_8197F)
+#define BIT_SET_WMAC_MU_BFEE2_AID_8197F(x, v)                                  \
+	(BIT_CLEAR_WMAC_MU_BFEE2_AID_8197F(x) | BIT_WMAC_MU_BFEE2_AID_8197F(v))
+
+/* 2 REG_WMAC_ASSOCIATED_MU_BFMEE3_8197F */
+#define BIT_STATUS_BFEE3_8197F BIT(10)
+#define BIT_WMAC_MU_BFEE3_EN_8197F BIT(9)
+
+#define BIT_SHIFT_WMAC_MU_BFEE3_AID_8197F 0
+#define BIT_MASK_WMAC_MU_BFEE3_AID_8197F 0x1ff
+#define BIT_WMAC_MU_BFEE3_AID_8197F(x)                                         \
+	(((x) & BIT_MASK_WMAC_MU_BFEE3_AID_8197F)                              \
+	 << BIT_SHIFT_WMAC_MU_BFEE3_AID_8197F)
+#define BITS_WMAC_MU_BFEE3_AID_8197F                                           \
+	(BIT_MASK_WMAC_MU_BFEE3_AID_8197F << BIT_SHIFT_WMAC_MU_BFEE3_AID_8197F)
+#define BIT_CLEAR_WMAC_MU_BFEE3_AID_8197F(x)                                   \
+	((x) & (~BITS_WMAC_MU_BFEE3_AID_8197F))
+#define BIT_GET_WMAC_MU_BFEE3_AID_8197F(x)                                     \
+	(((x) >> BIT_SHIFT_WMAC_MU_BFEE3_AID_8197F) &                          \
+	 BIT_MASK_WMAC_MU_BFEE3_AID_8197F)
+#define BIT_SET_WMAC_MU_BFEE3_AID_8197F(x, v)                                  \
+	(BIT_CLEAR_WMAC_MU_BFEE3_AID_8197F(x) | BIT_WMAC_MU_BFEE3_AID_8197F(v))
+
+/* 2 REG_WMAC_ASSOCIATED_MU_BFMEE4_8197F */
+#define BIT_STATUS_BFEE4_8197F BIT(10)
+#define BIT_WMAC_MU_BFEE4_EN_8197F BIT(9)
+
+#define BIT_SHIFT_WMAC_MU_BFEE4_AID_8197F 0
+#define BIT_MASK_WMAC_MU_BFEE4_AID_8197F 0x1ff
+#define BIT_WMAC_MU_BFEE4_AID_8197F(x)                                         \
+	(((x) & BIT_MASK_WMAC_MU_BFEE4_AID_8197F)                              \
+	 << BIT_SHIFT_WMAC_MU_BFEE4_AID_8197F)
+#define BITS_WMAC_MU_BFEE4_AID_8197F                                           \
+	(BIT_MASK_WMAC_MU_BFEE4_AID_8197F << BIT_SHIFT_WMAC_MU_BFEE4_AID_8197F)
+#define BIT_CLEAR_WMAC_MU_BFEE4_AID_8197F(x)                                   \
+	((x) & (~BITS_WMAC_MU_BFEE4_AID_8197F))
+#define BIT_GET_WMAC_MU_BFEE4_AID_8197F(x)                                     \
+	(((x) >> BIT_SHIFT_WMAC_MU_BFEE4_AID_8197F) &                          \
+	 BIT_MASK_WMAC_MU_BFEE4_AID_8197F)
+#define BIT_SET_WMAC_MU_BFEE4_AID_8197F(x, v)                                  \
+	(BIT_CLEAR_WMAC_MU_BFEE4_AID_8197F(x) | BIT_WMAC_MU_BFEE4_AID_8197F(v))
+
+/* 2 REG_WMAC_ASSOCIATED_MU_BFMEE5_8197F */
+#define BIT_STATUS_BFEE5_8197F BIT(10)
+#define BIT_WMAC_MU_BFEE5_EN_8197F BIT(9)
+
+#define BIT_SHIFT_WMAC_MU_BFEE5_AID_8197F 0
+#define BIT_MASK_WMAC_MU_BFEE5_AID_8197F 0x1ff
+#define BIT_WMAC_MU_BFEE5_AID_8197F(x)                                         \
+	(((x) & BIT_MASK_WMAC_MU_BFEE5_AID_8197F)                              \
+	 << BIT_SHIFT_WMAC_MU_BFEE5_AID_8197F)
+#define BITS_WMAC_MU_BFEE5_AID_8197F                                           \
+	(BIT_MASK_WMAC_MU_BFEE5_AID_8197F << BIT_SHIFT_WMAC_MU_BFEE5_AID_8197F)
+#define BIT_CLEAR_WMAC_MU_BFEE5_AID_8197F(x)                                   \
+	((x) & (~BITS_WMAC_MU_BFEE5_AID_8197F))
+#define BIT_GET_WMAC_MU_BFEE5_AID_8197F(x)                                     \
+	(((x) >> BIT_SHIFT_WMAC_MU_BFEE5_AID_8197F) &                          \
+	 BIT_MASK_WMAC_MU_BFEE5_AID_8197F)
+#define BIT_SET_WMAC_MU_BFEE5_AID_8197F(x, v)                                  \
+	(BIT_CLEAR_WMAC_MU_BFEE5_AID_8197F(x) | BIT_WMAC_MU_BFEE5_AID_8197F(v))
+
+/* 2 REG_WMAC_ASSOCIATED_MU_BFMEE6_8197F */
+#define BIT_STATUS_BFEE6_8197F BIT(10)
+#define BIT_WMAC_MU_BFEE6_EN_8197F BIT(9)
+
+#define BIT_SHIFT_WMAC_MU_BFEE6_AID_8197F 0
+#define BIT_MASK_WMAC_MU_BFEE6_AID_8197F 0x1ff
+#define BIT_WMAC_MU_BFEE6_AID_8197F(x)                                         \
+	(((x) & BIT_MASK_WMAC_MU_BFEE6_AID_8197F)                              \
+	 << BIT_SHIFT_WMAC_MU_BFEE6_AID_8197F)
+#define BITS_WMAC_MU_BFEE6_AID_8197F                                           \
+	(BIT_MASK_WMAC_MU_BFEE6_AID_8197F << BIT_SHIFT_WMAC_MU_BFEE6_AID_8197F)
+#define BIT_CLEAR_WMAC_MU_BFEE6_AID_8197F(x)                                   \
+	((x) & (~BITS_WMAC_MU_BFEE6_AID_8197F))
+#define BIT_GET_WMAC_MU_BFEE6_AID_8197F(x)                                     \
+	(((x) >> BIT_SHIFT_WMAC_MU_BFEE6_AID_8197F) &                          \
+	 BIT_MASK_WMAC_MU_BFEE6_AID_8197F)
+#define BIT_SET_WMAC_MU_BFEE6_AID_8197F(x, v)                                  \
+	(BIT_CLEAR_WMAC_MU_BFEE6_AID_8197F(x) | BIT_WMAC_MU_BFEE6_AID_8197F(v))
+
+/* 2 REG_WMAC_ASSOCIATED_MU_BFMEE7_8197F */
+#define BIT_BIT_STATUS_BFEE4_8197F BIT(10)
+#define BIT_WMAC_MU_BFEE7_EN_8197F BIT(9)
+
+#define BIT_SHIFT_WMAC_MU_BFEE7_AID_8197F 0
+#define BIT_MASK_WMAC_MU_BFEE7_AID_8197F 0x1ff
+#define BIT_WMAC_MU_BFEE7_AID_8197F(x)                                         \
+	(((x) & BIT_MASK_WMAC_MU_BFEE7_AID_8197F)                              \
+	 << BIT_SHIFT_WMAC_MU_BFEE7_AID_8197F)
+#define BITS_WMAC_MU_BFEE7_AID_8197F                                           \
+	(BIT_MASK_WMAC_MU_BFEE7_AID_8197F << BIT_SHIFT_WMAC_MU_BFEE7_AID_8197F)
+#define BIT_CLEAR_WMAC_MU_BFEE7_AID_8197F(x)                                   \
+	((x) & (~BITS_WMAC_MU_BFEE7_AID_8197F))
+#define BIT_GET_WMAC_MU_BFEE7_AID_8197F(x)                                     \
+	(((x) >> BIT_SHIFT_WMAC_MU_BFEE7_AID_8197F) &                          \
+	 BIT_MASK_WMAC_MU_BFEE7_AID_8197F)
+#define BIT_SET_WMAC_MU_BFEE7_AID_8197F(x, v)                                  \
+	(BIT_CLEAR_WMAC_MU_BFEE7_AID_8197F(x) | BIT_WMAC_MU_BFEE7_AID_8197F(v))
+
+/* 2 REG_NOT_VALID_8197F */
+#define BIT_RST_ALL_COUNTER_8197F BIT(31)
+
+#define BIT_SHIFT_ABORT_RX_VBON_COUNTER_8197F 16
+#define BIT_MASK_ABORT_RX_VBON_COUNTER_8197F 0xff
+#define BIT_ABORT_RX_VBON_COUNTER_8197F(x)                                     \
+	(((x) & BIT_MASK_ABORT_RX_VBON_COUNTER_8197F)                          \
+	 << BIT_SHIFT_ABORT_RX_VBON_COUNTER_8197F)
+#define BITS_ABORT_RX_VBON_COUNTER_8197F                                       \
+	(BIT_MASK_ABORT_RX_VBON_COUNTER_8197F                                  \
+	 << BIT_SHIFT_ABORT_RX_VBON_COUNTER_8197F)
+#define BIT_CLEAR_ABORT_RX_VBON_COUNTER_8197F(x)                               \
+	((x) & (~BITS_ABORT_RX_VBON_COUNTER_8197F))
+#define BIT_GET_ABORT_RX_VBON_COUNTER_8197F(x)                                 \
+	(((x) >> BIT_SHIFT_ABORT_RX_VBON_COUNTER_8197F) &                      \
+	 BIT_MASK_ABORT_RX_VBON_COUNTER_8197F)
+#define BIT_SET_ABORT_RX_VBON_COUNTER_8197F(x, v)                              \
+	(BIT_CLEAR_ABORT_RX_VBON_COUNTER_8197F(x) |                            \
+	 BIT_ABORT_RX_VBON_COUNTER_8197F(v))
+
+#define BIT_SHIFT_ABORT_RX_RDRDY_COUNTER_8197F 8
+#define BIT_MASK_ABORT_RX_RDRDY_COUNTER_8197F 0xff
+#define BIT_ABORT_RX_RDRDY_COUNTER_8197F(x)                                    \
+	(((x) & BIT_MASK_ABORT_RX_RDRDY_COUNTER_8197F)                         \
+	 << BIT_SHIFT_ABORT_RX_RDRDY_COUNTER_8197F)
+#define BITS_ABORT_RX_RDRDY_COUNTER_8197F                                      \
+	(BIT_MASK_ABORT_RX_RDRDY_COUNTER_8197F                                 \
+	 << BIT_SHIFT_ABORT_RX_RDRDY_COUNTER_8197F)
+#define BIT_CLEAR_ABORT_RX_RDRDY_COUNTER_8197F(x)                              \
+	((x) & (~BITS_ABORT_RX_RDRDY_COUNTER_8197F))
+#define BIT_GET_ABORT_RX_RDRDY_COUNTER_8197F(x)                                \
+	(((x) >> BIT_SHIFT_ABORT_RX_RDRDY_COUNTER_8197F) &                     \
+	 BIT_MASK_ABORT_RX_RDRDY_COUNTER_8197F)
+#define BIT_SET_ABORT_RX_RDRDY_COUNTER_8197F(x, v)                             \
+	(BIT_CLEAR_ABORT_RX_RDRDY_COUNTER_8197F(x) |                           \
+	 BIT_ABORT_RX_RDRDY_COUNTER_8197F(v))
+
+#define BIT_SHIFT_VBON_EARLY_FALLING_COUNTER_8197F 0
+#define BIT_MASK_VBON_EARLY_FALLING_COUNTER_8197F 0xff
+#define BIT_VBON_EARLY_FALLING_COUNTER_8197F(x)                                \
+	(((x) & BIT_MASK_VBON_EARLY_FALLING_COUNTER_8197F)                     \
+	 << BIT_SHIFT_VBON_EARLY_FALLING_COUNTER_8197F)
+#define BITS_VBON_EARLY_FALLING_COUNTER_8197F                                  \
+	(BIT_MASK_VBON_EARLY_FALLING_COUNTER_8197F                             \
+	 << BIT_SHIFT_VBON_EARLY_FALLING_COUNTER_8197F)
+#define BIT_CLEAR_VBON_EARLY_FALLING_COUNTER_8197F(x)                          \
+	((x) & (~BITS_VBON_EARLY_FALLING_COUNTER_8197F))
+#define BIT_GET_VBON_EARLY_FALLING_COUNTER_8197F(x)                            \
+	(((x) >> BIT_SHIFT_VBON_EARLY_FALLING_COUNTER_8197F) &                 \
+	 BIT_MASK_VBON_EARLY_FALLING_COUNTER_8197F)
+#define BIT_SET_VBON_EARLY_FALLING_COUNTER_8197F(x, v)                         \
+	(BIT_CLEAR_VBON_EARLY_FALLING_COUNTER_8197F(x) |                       \
+	 BIT_VBON_EARLY_FALLING_COUNTER_8197F(v))
+
+/* 2 REG_NOT_VALID_8197F */
+#define BIT_WMAC_PLCP_TRX_SEL_8197F BIT(31)
+
+#define BIT_SHIFT_WMAC_PLCP_RDSIG_SEL_8197F 28
+#define BIT_MASK_WMAC_PLCP_RDSIG_SEL_8197F 0x7
+#define BIT_WMAC_PLCP_RDSIG_SEL_8197F(x)                                       \
+	(((x) & BIT_MASK_WMAC_PLCP_RDSIG_SEL_8197F)                            \
+	 << BIT_SHIFT_WMAC_PLCP_RDSIG_SEL_8197F)
+#define BITS_WMAC_PLCP_RDSIG_SEL_8197F                                         \
+	(BIT_MASK_WMAC_PLCP_RDSIG_SEL_8197F                                    \
+	 << BIT_SHIFT_WMAC_PLCP_RDSIG_SEL_8197F)
+#define BIT_CLEAR_WMAC_PLCP_RDSIG_SEL_8197F(x)                                 \
+	((x) & (~BITS_WMAC_PLCP_RDSIG_SEL_8197F))
+#define BIT_GET_WMAC_PLCP_RDSIG_SEL_8197F(x)                                   \
+	(((x) >> BIT_SHIFT_WMAC_PLCP_RDSIG_SEL_8197F) &                        \
+	 BIT_MASK_WMAC_PLCP_RDSIG_SEL_8197F)
+#define BIT_SET_WMAC_PLCP_RDSIG_SEL_8197F(x, v)                                \
+	(BIT_CLEAR_WMAC_PLCP_RDSIG_SEL_8197F(x) |                              \
+	 BIT_WMAC_PLCP_RDSIG_SEL_8197F(v))
+
+#define BIT_SHIFT_WMAC_RATE_IDX_8197F 24
+#define BIT_MASK_WMAC_RATE_IDX_8197F 0xf
+#define BIT_WMAC_RATE_IDX_8197F(x)                                             \
+	(((x) & BIT_MASK_WMAC_RATE_IDX_8197F) << BIT_SHIFT_WMAC_RATE_IDX_8197F)
+#define BITS_WMAC_RATE_IDX_8197F                                               \
+	(BIT_MASK_WMAC_RATE_IDX_8197F << BIT_SHIFT_WMAC_RATE_IDX_8197F)
+#define BIT_CLEAR_WMAC_RATE_IDX_8197F(x) ((x) & (~BITS_WMAC_RATE_IDX_8197F))
+#define BIT_GET_WMAC_RATE_IDX_8197F(x)                                         \
+	(((x) >> BIT_SHIFT_WMAC_RATE_IDX_8197F) & BIT_MASK_WMAC_RATE_IDX_8197F)
+#define BIT_SET_WMAC_RATE_IDX_8197F(x, v)                                      \
+	(BIT_CLEAR_WMAC_RATE_IDX_8197F(x) | BIT_WMAC_RATE_IDX_8197F(v))
+
+#define BIT_SHIFT_WMAC_PLCP_RDSIG_8197F 0
+#define BIT_MASK_WMAC_PLCP_RDSIG_8197F 0xffffff
+#define BIT_WMAC_PLCP_RDSIG_8197F(x)                                           \
+	(((x) & BIT_MASK_WMAC_PLCP_RDSIG_8197F)                                \
+	 << BIT_SHIFT_WMAC_PLCP_RDSIG_8197F)
+#define BITS_WMAC_PLCP_RDSIG_8197F                                             \
+	(BIT_MASK_WMAC_PLCP_RDSIG_8197F << BIT_SHIFT_WMAC_PLCP_RDSIG_8197F)
+#define BIT_CLEAR_WMAC_PLCP_RDSIG_8197F(x) ((x) & (~BITS_WMAC_PLCP_RDSIG_8197F))
+#define BIT_GET_WMAC_PLCP_RDSIG_8197F(x)                                       \
+	(((x) >> BIT_SHIFT_WMAC_PLCP_RDSIG_8197F) &                            \
+	 BIT_MASK_WMAC_PLCP_RDSIG_8197F)
+#define BIT_SET_WMAC_PLCP_RDSIG_8197F(x, v)                                    \
+	(BIT_CLEAR_WMAC_PLCP_RDSIG_8197F(x) | BIT_WMAC_PLCP_RDSIG_8197F(v))
+
+/* 2 REG_NOT_VALID_8197F */
+
+/* 2 REG_NOT_VALID_8197F */
+
+/* 2 REG_NOT_VALID_8197F */
+
+/* 2 REG_NOT_VALID_8197F */
+
+/* 2 REG_NOT_VALID_8197F */
+
+/* 2 REG_TRANSMIT_ADDRSS_0_8197F (TA0 REGISTER) */
+
+#define BIT_SHIFT_TA0_8197F 0
+#define BIT_MASK_TA0_8197F 0xffffffffffffL
+#define BIT_TA0_8197F(x) (((x) & BIT_MASK_TA0_8197F) << BIT_SHIFT_TA0_8197F)
+#define BITS_TA0_8197F (BIT_MASK_TA0_8197F << BIT_SHIFT_TA0_8197F)
+#define BIT_CLEAR_TA0_8197F(x) ((x) & (~BITS_TA0_8197F))
+#define BIT_GET_TA0_8197F(x) (((x) >> BIT_SHIFT_TA0_8197F) & BIT_MASK_TA0_8197F)
+#define BIT_SET_TA0_8197F(x, v) (BIT_CLEAR_TA0_8197F(x) | BIT_TA0_8197F(v))
+
+/* 2 REG_TRANSMIT_ADDRSS_1_8197F (TA1 REGISTER) */
+
+#define BIT_SHIFT_TA1_8197F 0
+#define BIT_MASK_TA1_8197F 0xffffffffffffL
+#define BIT_TA1_8197F(x) (((x) & BIT_MASK_TA1_8197F) << BIT_SHIFT_TA1_8197F)
+#define BITS_TA1_8197F (BIT_MASK_TA1_8197F << BIT_SHIFT_TA1_8197F)
+#define BIT_CLEAR_TA1_8197F(x) ((x) & (~BITS_TA1_8197F))
+#define BIT_GET_TA1_8197F(x) (((x) >> BIT_SHIFT_TA1_8197F) & BIT_MASK_TA1_8197F)
+#define BIT_SET_TA1_8197F(x, v) (BIT_CLEAR_TA1_8197F(x) | BIT_TA1_8197F(v))
+
+/* 2 REG_TRANSMIT_ADDRSS_2_8197F (TA2 REGISTER) */
+
+#define BIT_SHIFT_TA2_8197F 0
+#define BIT_MASK_TA2_8197F 0xffffffffffffL
+#define BIT_TA2_8197F(x) (((x) & BIT_MASK_TA2_8197F) << BIT_SHIFT_TA2_8197F)
+#define BITS_TA2_8197F (BIT_MASK_TA2_8197F << BIT_SHIFT_TA2_8197F)
+#define BIT_CLEAR_TA2_8197F(x) ((x) & (~BITS_TA2_8197F))
+#define BIT_GET_TA2_8197F(x) (((x) >> BIT_SHIFT_TA2_8197F) & BIT_MASK_TA2_8197F)
+#define BIT_SET_TA2_8197F(x, v) (BIT_CLEAR_TA2_8197F(x) | BIT_TA2_8197F(v))
+
+/* 2 REG_TRANSMIT_ADDRSS_3_8197F (TA3 REGISTER) */
+
+#define BIT_SHIFT_TA3_8197F 0
+#define BIT_MASK_TA3_8197F 0xffffffffffffL
+#define BIT_TA3_8197F(x) (((x) & BIT_MASK_TA3_8197F) << BIT_SHIFT_TA3_8197F)
+#define BITS_TA3_8197F (BIT_MASK_TA3_8197F << BIT_SHIFT_TA3_8197F)
+#define BIT_CLEAR_TA3_8197F(x) ((x) & (~BITS_TA3_8197F))
+#define BIT_GET_TA3_8197F(x) (((x) >> BIT_SHIFT_TA3_8197F) & BIT_MASK_TA3_8197F)
+#define BIT_SET_TA3_8197F(x, v) (BIT_CLEAR_TA3_8197F(x) | BIT_TA3_8197F(v))
+
+/* 2 REG_TRANSMIT_ADDRSS_4_8197F (TA4 REGISTER) */
+
+#define BIT_SHIFT_TA4_8197F 0
+#define BIT_MASK_TA4_8197F 0xffffffffffffL
+#define BIT_TA4_8197F(x) (((x) & BIT_MASK_TA4_8197F) << BIT_SHIFT_TA4_8197F)
+#define BITS_TA4_8197F (BIT_MASK_TA4_8197F << BIT_SHIFT_TA4_8197F)
+#define BIT_CLEAR_TA4_8197F(x) ((x) & (~BITS_TA4_8197F))
+#define BIT_GET_TA4_8197F(x) (((x) >> BIT_SHIFT_TA4_8197F) & BIT_MASK_TA4_8197F)
+#define BIT_SET_TA4_8197F(x, v) (BIT_CLEAR_TA4_8197F(x) | BIT_TA4_8197F(v))
+
+/* 2 REG_NOT_VALID_8197F */
+
+/* 2 REG_MACID1_8197F */
+
+#define BIT_SHIFT_MACID1_8197F 0
+#define BIT_MASK_MACID1_8197F 0xffffffffffffL
+#define BIT_MACID1_8197F(x)                                                    \
+	(((x) & BIT_MASK_MACID1_8197F) << BIT_SHIFT_MACID1_8197F)
+#define BITS_MACID1_8197F (BIT_MASK_MACID1_8197F << BIT_SHIFT_MACID1_8197F)
+#define BIT_CLEAR_MACID1_8197F(x) ((x) & (~BITS_MACID1_8197F))
+#define BIT_GET_MACID1_8197F(x)                                                \
+	(((x) >> BIT_SHIFT_MACID1_8197F) & BIT_MASK_MACID1_8197F)
+#define BIT_SET_MACID1_8197F(x, v)                                             \
+	(BIT_CLEAR_MACID1_8197F(x) | BIT_MACID1_8197F(v))
+
+/* 2 REG_BSSID1_8197F */
+
+#define BIT_SHIFT_BSSID1_8197F 0
+#define BIT_MASK_BSSID1_8197F 0xffffffffffffL
+#define BIT_BSSID1_8197F(x)                                                    \
+	(((x) & BIT_MASK_BSSID1_8197F) << BIT_SHIFT_BSSID1_8197F)
+#define BITS_BSSID1_8197F (BIT_MASK_BSSID1_8197F << BIT_SHIFT_BSSID1_8197F)
+#define BIT_CLEAR_BSSID1_8197F(x) ((x) & (~BITS_BSSID1_8197F))
+#define BIT_GET_BSSID1_8197F(x)                                                \
+	(((x) >> BIT_SHIFT_BSSID1_8197F) & BIT_MASK_BSSID1_8197F)
+#define BIT_SET_BSSID1_8197F(x, v)                                             \
+	(BIT_CLEAR_BSSID1_8197F(x) | BIT_BSSID1_8197F(v))
+
+/* 2 REG_BCN_PSR_RPT1_8197F */
+
+#define BIT_SHIFT_DTIM_CNT1_8197F 24
+#define BIT_MASK_DTIM_CNT1_8197F 0xff
+#define BIT_DTIM_CNT1_8197F(x)                                                 \
+	(((x) & BIT_MASK_DTIM_CNT1_8197F) << BIT_SHIFT_DTIM_CNT1_8197F)
+#define BITS_DTIM_CNT1_8197F                                                   \
+	(BIT_MASK_DTIM_CNT1_8197F << BIT_SHIFT_DTIM_CNT1_8197F)
+#define BIT_CLEAR_DTIM_CNT1_8197F(x) ((x) & (~BITS_DTIM_CNT1_8197F))
+#define BIT_GET_DTIM_CNT1_8197F(x)                                             \
+	(((x) >> BIT_SHIFT_DTIM_CNT1_8197F) & BIT_MASK_DTIM_CNT1_8197F)
+#define BIT_SET_DTIM_CNT1_8197F(x, v)                                          \
+	(BIT_CLEAR_DTIM_CNT1_8197F(x) | BIT_DTIM_CNT1_8197F(v))
+
+#define BIT_SHIFT_DTIM_PERIOD1_8197F 16
+#define BIT_MASK_DTIM_PERIOD1_8197F 0xff
+#define BIT_DTIM_PERIOD1_8197F(x)                                              \
+	(((x) & BIT_MASK_DTIM_PERIOD1_8197F) << BIT_SHIFT_DTIM_PERIOD1_8197F)
+#define BITS_DTIM_PERIOD1_8197F                                                \
+	(BIT_MASK_DTIM_PERIOD1_8197F << BIT_SHIFT_DTIM_PERIOD1_8197F)
+#define BIT_CLEAR_DTIM_PERIOD1_8197F(x) ((x) & (~BITS_DTIM_PERIOD1_8197F))
+#define BIT_GET_DTIM_PERIOD1_8197F(x)                                          \
+	(((x) >> BIT_SHIFT_DTIM_PERIOD1_8197F) & BIT_MASK_DTIM_PERIOD1_8197F)
+#define BIT_SET_DTIM_PERIOD1_8197F(x, v)                                       \
+	(BIT_CLEAR_DTIM_PERIOD1_8197F(x) | BIT_DTIM_PERIOD1_8197F(v))
+
+#define BIT_DTIM1_8197F BIT(15)
+#define BIT_TIM1_8197F BIT(14)
+
+#define BIT_SHIFT_PS_AID_1_8197F 0
+#define BIT_MASK_PS_AID_1_8197F 0x7ff
+#define BIT_PS_AID_1_8197F(x)                                                  \
+	(((x) & BIT_MASK_PS_AID_1_8197F) << BIT_SHIFT_PS_AID_1_8197F)
+#define BITS_PS_AID_1_8197F                                                    \
+	(BIT_MASK_PS_AID_1_8197F << BIT_SHIFT_PS_AID_1_8197F)
+#define BIT_CLEAR_PS_AID_1_8197F(x) ((x) & (~BITS_PS_AID_1_8197F))
+#define BIT_GET_PS_AID_1_8197F(x)                                              \
+	(((x) >> BIT_SHIFT_PS_AID_1_8197F) & BIT_MASK_PS_AID_1_8197F)
+#define BIT_SET_PS_AID_1_8197F(x, v)                                           \
+	(BIT_CLEAR_PS_AID_1_8197F(x) | BIT_PS_AID_1_8197F(v))
+
+/* 2 REG_ASSOCIATED_BFMEE_SEL_8197F */
+#define BIT_TXUSER_ID1_8197F BIT(25)
+
+#define BIT_SHIFT_AID1_8197F 16
+#define BIT_MASK_AID1_8197F 0x1ff
+#define BIT_AID1_8197F(x) (((x) & BIT_MASK_AID1_8197F) << BIT_SHIFT_AID1_8197F)
+#define BITS_AID1_8197F (BIT_MASK_AID1_8197F << BIT_SHIFT_AID1_8197F)
+#define BIT_CLEAR_AID1_8197F(x) ((x) & (~BITS_AID1_8197F))
+#define BIT_GET_AID1_8197F(x)                                                  \
+	(((x) >> BIT_SHIFT_AID1_8197F) & BIT_MASK_AID1_8197F)
+#define BIT_SET_AID1_8197F(x, v) (BIT_CLEAR_AID1_8197F(x) | BIT_AID1_8197F(v))
+
+#define BIT_TXUSER_ID0_8197F BIT(9)
+
+#define BIT_SHIFT_AID0_8197F 0
+#define BIT_MASK_AID0_8197F 0x1ff
+#define BIT_AID0_8197F(x) (((x) & BIT_MASK_AID0_8197F) << BIT_SHIFT_AID0_8197F)
+#define BITS_AID0_8197F (BIT_MASK_AID0_8197F << BIT_SHIFT_AID0_8197F)
+#define BIT_CLEAR_AID0_8197F(x) ((x) & (~BITS_AID0_8197F))
+#define BIT_GET_AID0_8197F(x)                                                  \
+	(((x) >> BIT_SHIFT_AID0_8197F) & BIT_MASK_AID0_8197F)
+#define BIT_SET_AID0_8197F(x, v) (BIT_CLEAR_AID0_8197F(x) | BIT_AID0_8197F(v))
+
+/* 2 REG_SND_PTCL_CTRL_8197F */
+
+#define BIT_SHIFT_NDP_RX_STANDBY_TIMER_8197F 24
+#define BIT_MASK_NDP_RX_STANDBY_TIMER_8197F 0xff
+#define BIT_NDP_RX_STANDBY_TIMER_8197F(x)                                      \
+	(((x) & BIT_MASK_NDP_RX_STANDBY_TIMER_8197F)                           \
+	 << BIT_SHIFT_NDP_RX_STANDBY_TIMER_8197F)
+#define BITS_NDP_RX_STANDBY_TIMER_8197F                                        \
+	(BIT_MASK_NDP_RX_STANDBY_TIMER_8197F                                   \
+	 << BIT_SHIFT_NDP_RX_STANDBY_TIMER_8197F)
+#define BIT_CLEAR_NDP_RX_STANDBY_TIMER_8197F(x)                                \
+	((x) & (~BITS_NDP_RX_STANDBY_TIMER_8197F))
+#define BIT_GET_NDP_RX_STANDBY_TIMER_8197F(x)                                  \
+	(((x) >> BIT_SHIFT_NDP_RX_STANDBY_TIMER_8197F) &                       \
+	 BIT_MASK_NDP_RX_STANDBY_TIMER_8197F)
+#define BIT_SET_NDP_RX_STANDBY_TIMER_8197F(x, v)                               \
+	(BIT_CLEAR_NDP_RX_STANDBY_TIMER_8197F(x) |                             \
+	 BIT_NDP_RX_STANDBY_TIMER_8197F(v))
+
+#define BIT_SHIFT_CSI_RPT_OFFSET_HT_8197F 16
+#define BIT_MASK_CSI_RPT_OFFSET_HT_8197F 0xff
+#define BIT_CSI_RPT_OFFSET_HT_8197F(x)                                         \
+	(((x) & BIT_MASK_CSI_RPT_OFFSET_HT_8197F)                              \
+	 << BIT_SHIFT_CSI_RPT_OFFSET_HT_8197F)
+#define BITS_CSI_RPT_OFFSET_HT_8197F                                           \
+	(BIT_MASK_CSI_RPT_OFFSET_HT_8197F << BIT_SHIFT_CSI_RPT_OFFSET_HT_8197F)
+#define BIT_CLEAR_CSI_RPT_OFFSET_HT_8197F(x)                                   \
+	((x) & (~BITS_CSI_RPT_OFFSET_HT_8197F))
+#define BIT_GET_CSI_RPT_OFFSET_HT_8197F(x)                                     \
+	(((x) >> BIT_SHIFT_CSI_RPT_OFFSET_HT_8197F) &                          \
+	 BIT_MASK_CSI_RPT_OFFSET_HT_8197F)
+#define BIT_SET_CSI_RPT_OFFSET_HT_8197F(x, v)                                  \
+	(BIT_CLEAR_CSI_RPT_OFFSET_HT_8197F(x) | BIT_CSI_RPT_OFFSET_HT_8197F(v))
+
+#define BIT_SHIFT_CSI_RPT_OFFSET_VHT_8197F 8
+#define BIT_MASK_CSI_RPT_OFFSET_VHT_8197F 0xff
+#define BIT_CSI_RPT_OFFSET_VHT_8197F(x)                                        \
+	(((x) & BIT_MASK_CSI_RPT_OFFSET_VHT_8197F)                             \
+	 << BIT_SHIFT_CSI_RPT_OFFSET_VHT_8197F)
+#define BITS_CSI_RPT_OFFSET_VHT_8197F                                          \
+	(BIT_MASK_CSI_RPT_OFFSET_VHT_8197F                                     \
+	 << BIT_SHIFT_CSI_RPT_OFFSET_VHT_8197F)
+#define BIT_CLEAR_CSI_RPT_OFFSET_VHT_8197F(x)                                  \
+	((x) & (~BITS_CSI_RPT_OFFSET_VHT_8197F))
+#define BIT_GET_CSI_RPT_OFFSET_VHT_8197F(x)                                    \
+	(((x) >> BIT_SHIFT_CSI_RPT_OFFSET_VHT_8197F) &                         \
+	 BIT_MASK_CSI_RPT_OFFSET_VHT_8197F)
+#define BIT_SET_CSI_RPT_OFFSET_VHT_8197F(x, v)                                 \
+	(BIT_CLEAR_CSI_RPT_OFFSET_VHT_8197F(x) |                               \
+	 BIT_CSI_RPT_OFFSET_VHT_8197F(v))
+
+#define BIT_R_WMAC_USE_NSTS_8197F BIT(7)
+#define BIT_R_DISABLE_CHECK_VHTSIGB_CRC_8197F BIT(6)
+#define BIT_R_DISABLE_CHECK_VHTSIGA_CRC_8197F BIT(5)
+#define BIT_R_WMAC_BFPARAM_SEL_8197F BIT(4)
+#define BIT_R_WMAC_CSISEQ_SEL_8197F BIT(3)
+#define BIT_R_WMAC_CSI_WITHHTC_EN_8197F BIT(2)
+#define BIT_R_WMAC_HT_NDPA_EN_8197F BIT(1)
+#define BIT_R_WMAC_VHT_NDPA_EN_8197F BIT(0)
+
+/* 2 REG_RX_CSI_RPT_INFO_8197F */
+
+/* 2 REG_NS_ARP_CTRL_8197F */
+#define BIT_R_WMAC_NSARP_RSPEN_8197F BIT(15)
+#define BIT_R_WMAC_NSARP_RARP_8197F BIT(9)
+#define BIT_R_WMAC_NSARP_RIPV6_8197F BIT(8)
+
+#define BIT_SHIFT_R_WMAC_NSARP_MODEN_8197F 6
+#define BIT_MASK_R_WMAC_NSARP_MODEN_8197F 0x3
+#define BIT_R_WMAC_NSARP_MODEN_8197F(x)                                        \
+	(((x) & BIT_MASK_R_WMAC_NSARP_MODEN_8197F)                             \
+	 << BIT_SHIFT_R_WMAC_NSARP_MODEN_8197F)
+#define BITS_R_WMAC_NSARP_MODEN_8197F                                          \
+	(BIT_MASK_R_WMAC_NSARP_MODEN_8197F                                     \
+	 << BIT_SHIFT_R_WMAC_NSARP_MODEN_8197F)
+#define BIT_CLEAR_R_WMAC_NSARP_MODEN_8197F(x)                                  \
+	((x) & (~BITS_R_WMAC_NSARP_MODEN_8197F))
+#define BIT_GET_R_WMAC_NSARP_MODEN_8197F(x)                                    \
+	(((x) >> BIT_SHIFT_R_WMAC_NSARP_MODEN_8197F) &                         \
+	 BIT_MASK_R_WMAC_NSARP_MODEN_8197F)
+#define BIT_SET_R_WMAC_NSARP_MODEN_8197F(x, v)                                 \
+	(BIT_CLEAR_R_WMAC_NSARP_MODEN_8197F(x) |                               \
+	 BIT_R_WMAC_NSARP_MODEN_8197F(v))
+
+#define BIT_SHIFT_R_WMAC_NSARP_RSPFTP_8197F 4
+#define BIT_MASK_R_WMAC_NSARP_RSPFTP_8197F 0x3
+#define BIT_R_WMAC_NSARP_RSPFTP_8197F(x)                                       \
+	(((x) & BIT_MASK_R_WMAC_NSARP_RSPFTP_8197F)                            \
+	 << BIT_SHIFT_R_WMAC_NSARP_RSPFTP_8197F)
+#define BITS_R_WMAC_NSARP_RSPFTP_8197F                                         \
+	(BIT_MASK_R_WMAC_NSARP_RSPFTP_8197F                                    \
+	 << BIT_SHIFT_R_WMAC_NSARP_RSPFTP_8197F)
+#define BIT_CLEAR_R_WMAC_NSARP_RSPFTP_8197F(x)                                 \
+	((x) & (~BITS_R_WMAC_NSARP_RSPFTP_8197F))
+#define BIT_GET_R_WMAC_NSARP_RSPFTP_8197F(x)                                   \
+	(((x) >> BIT_SHIFT_R_WMAC_NSARP_RSPFTP_8197F) &                        \
+	 BIT_MASK_R_WMAC_NSARP_RSPFTP_8197F)
+#define BIT_SET_R_WMAC_NSARP_RSPFTP_8197F(x, v)                                \
+	(BIT_CLEAR_R_WMAC_NSARP_RSPFTP_8197F(x) |                              \
+	 BIT_R_WMAC_NSARP_RSPFTP_8197F(v))
+
+#define BIT_SHIFT_R_WMAC_NSARP_RSPSEC_8197F 0
+#define BIT_MASK_R_WMAC_NSARP_RSPSEC_8197F 0xf
+#define BIT_R_WMAC_NSARP_RSPSEC_8197F(x)                                       \
+	(((x) & BIT_MASK_R_WMAC_NSARP_RSPSEC_8197F)                            \
+	 << BIT_SHIFT_R_WMAC_NSARP_RSPSEC_8197F)
+#define BITS_R_WMAC_NSARP_RSPSEC_8197F                                         \
+	(BIT_MASK_R_WMAC_NSARP_RSPSEC_8197F                                    \
+	 << BIT_SHIFT_R_WMAC_NSARP_RSPSEC_8197F)
+#define BIT_CLEAR_R_WMAC_NSARP_RSPSEC_8197F(x)                                 \
+	((x) & (~BITS_R_WMAC_NSARP_RSPSEC_8197F))
+#define BIT_GET_R_WMAC_NSARP_RSPSEC_8197F(x)                                   \
+	(((x) >> BIT_SHIFT_R_WMAC_NSARP_RSPSEC_8197F) &                        \
+	 BIT_MASK_R_WMAC_NSARP_RSPSEC_8197F)
+#define BIT_SET_R_WMAC_NSARP_RSPSEC_8197F(x, v)                                \
+	(BIT_CLEAR_R_WMAC_NSARP_RSPSEC_8197F(x) |                              \
+	 BIT_R_WMAC_NSARP_RSPSEC_8197F(v))
+
+/* 2 REG_NS_ARP_INFO_8197F */
+
+/* 2 REG_BEAMFORMING_INFO_NSARP_V1_8197F */
+
+/* 2 REG_BEAMFORMING_INFO_NSARP_8197F */
+
+/* 2 REG_NOT_VALID_8197F */
+
+/* 2 REG_RSVD_0X740_8197F */
+
+/* 2 REG_WMAC_RTX_CTX_SUBTYPE_CFG_8197F */
+
+#define BIT_SHIFT_R_WMAC_CTX_SUBTYPE_8197F 4
+#define BIT_MASK_R_WMAC_CTX_SUBTYPE_8197F 0xf
+#define BIT_R_WMAC_CTX_SUBTYPE_8197F(x)                                        \
+	(((x) & BIT_MASK_R_WMAC_CTX_SUBTYPE_8197F)                             \
+	 << BIT_SHIFT_R_WMAC_CTX_SUBTYPE_8197F)
+#define BITS_R_WMAC_CTX_SUBTYPE_8197F                                          \
+	(BIT_MASK_R_WMAC_CTX_SUBTYPE_8197F                                     \
+	 << BIT_SHIFT_R_WMAC_CTX_SUBTYPE_8197F)
+#define BIT_CLEAR_R_WMAC_CTX_SUBTYPE_8197F(x)                                  \
+	((x) & (~BITS_R_WMAC_CTX_SUBTYPE_8197F))
+#define BIT_GET_R_WMAC_CTX_SUBTYPE_8197F(x)                                    \
+	(((x) >> BIT_SHIFT_R_WMAC_CTX_SUBTYPE_8197F) &                         \
+	 BIT_MASK_R_WMAC_CTX_SUBTYPE_8197F)
+#define BIT_SET_R_WMAC_CTX_SUBTYPE_8197F(x, v)                                 \
+	(BIT_CLEAR_R_WMAC_CTX_SUBTYPE_8197F(x) |                               \
+	 BIT_R_WMAC_CTX_SUBTYPE_8197F(v))
+
+#define BIT_SHIFT_R_WMAC_RTX_SUBTYPE_8197F 0
+#define BIT_MASK_R_WMAC_RTX_SUBTYPE_8197F 0xf
+#define BIT_R_WMAC_RTX_SUBTYPE_8197F(x)                                        \
+	(((x) & BIT_MASK_R_WMAC_RTX_SUBTYPE_8197F)                             \
+	 << BIT_SHIFT_R_WMAC_RTX_SUBTYPE_8197F)
+#define BITS_R_WMAC_RTX_SUBTYPE_8197F                                          \
+	(BIT_MASK_R_WMAC_RTX_SUBTYPE_8197F                                     \
+	 << BIT_SHIFT_R_WMAC_RTX_SUBTYPE_8197F)
+#define BIT_CLEAR_R_WMAC_RTX_SUBTYPE_8197F(x)                                  \
+	((x) & (~BITS_R_WMAC_RTX_SUBTYPE_8197F))
+#define BIT_GET_R_WMAC_RTX_SUBTYPE_8197F(x)                                    \
+	(((x) >> BIT_SHIFT_R_WMAC_RTX_SUBTYPE_8197F) &                         \
+	 BIT_MASK_R_WMAC_RTX_SUBTYPE_8197F)
+#define BIT_SET_R_WMAC_RTX_SUBTYPE_8197F(x, v)                                 \
+	(BIT_CLEAR_R_WMAC_RTX_SUBTYPE_8197F(x) |                               \
+	 BIT_R_WMAC_RTX_SUBTYPE_8197F(v))
+
+/* 2 REG_WMAC_SWAES_CFG_8197F */
+
+/* 2 REG_BT_COEX_V2_8197F */
+#define BIT_GNT_BT_POLARITY_8197F BIT(12)
+#define BIT_GNT_BT_BYPASS_PRIORITY_8197F BIT(8)
+
+#define BIT_SHIFT_TIMER_8197F 0
+#define BIT_MASK_TIMER_8197F 0xff
+#define BIT_TIMER_8197F(x)                                                     \
+	(((x) & BIT_MASK_TIMER_8197F) << BIT_SHIFT_TIMER_8197F)
+#define BITS_TIMER_8197F (BIT_MASK_TIMER_8197F << BIT_SHIFT_TIMER_8197F)
+#define BIT_CLEAR_TIMER_8197F(x) ((x) & (~BITS_TIMER_8197F))
+#define BIT_GET_TIMER_8197F(x)                                                 \
+	(((x) >> BIT_SHIFT_TIMER_8197F) & BIT_MASK_TIMER_8197F)
+#define BIT_SET_TIMER_8197F(x, v)                                              \
+	(BIT_CLEAR_TIMER_8197F(x) | BIT_TIMER_8197F(v))
+
+/* 2 REG_BT_COEX_8197F */
+#define BIT_R_GNT_BT_RFC_SW_8197F BIT(12)
+#define BIT_R_GNT_BT_RFC_SW_EN_8197F BIT(11)
+#define BIT_R_GNT_BT_BB_SW_8197F BIT(10)
+#define BIT_R_GNT_BT_BB_SW_EN_8197F BIT(9)
+#define BIT_R_BT_CNT_THREN_8197F BIT(8)
+
+#define BIT_SHIFT_R_BT_CNT_THR_8197F 0
+#define BIT_MASK_R_BT_CNT_THR_8197F 0xff
+#define BIT_R_BT_CNT_THR_8197F(x)                                              \
+	(((x) & BIT_MASK_R_BT_CNT_THR_8197F) << BIT_SHIFT_R_BT_CNT_THR_8197F)
+#define BITS_R_BT_CNT_THR_8197F                                                \
+	(BIT_MASK_R_BT_CNT_THR_8197F << BIT_SHIFT_R_BT_CNT_THR_8197F)
+#define BIT_CLEAR_R_BT_CNT_THR_8197F(x) ((x) & (~BITS_R_BT_CNT_THR_8197F))
+#define BIT_GET_R_BT_CNT_THR_8197F(x)                                          \
+	(((x) >> BIT_SHIFT_R_BT_CNT_THR_8197F) & BIT_MASK_R_BT_CNT_THR_8197F)
+#define BIT_SET_R_BT_CNT_THR_8197F(x, v)                                       \
+	(BIT_CLEAR_R_BT_CNT_THR_8197F(x) | BIT_R_BT_CNT_THR_8197F(v))
+
+/* 2 REG_WLAN_ACT_MASK_CTRL_8197F */
+#define BIT_WLRX_TER_BY_CTL_8197F BIT(43)
+#define BIT_WLRX_TER_BY_AD_8197F BIT(42)
+#define BIT_ANT_DIVERSITY_SEL_8197F BIT(41)
+#define BIT_ANTSEL_FOR_BT_CTRL_EN_8197F BIT(40)
+#define BIT_WLACT_LOW_GNTWL_EN_8197F BIT(34)
+#define BIT_WLACT_HIGH_GNTBT_EN_8197F BIT(33)
+
+#define BIT_SHIFT_RXMYRTS_NAV_V1_8197F 8
+#define BIT_MASK_RXMYRTS_NAV_V1_8197F 0xff
+#define BIT_RXMYRTS_NAV_V1_8197F(x)                                            \
+	(((x) & BIT_MASK_RXMYRTS_NAV_V1_8197F)                                 \
+	 << BIT_SHIFT_RXMYRTS_NAV_V1_8197F)
+#define BITS_RXMYRTS_NAV_V1_8197F                                              \
+	(BIT_MASK_RXMYRTS_NAV_V1_8197F << BIT_SHIFT_RXMYRTS_NAV_V1_8197F)
+#define BIT_CLEAR_RXMYRTS_NAV_V1_8197F(x) ((x) & (~BITS_RXMYRTS_NAV_V1_8197F))
+#define BIT_GET_RXMYRTS_NAV_V1_8197F(x)                                        \
+	(((x) >> BIT_SHIFT_RXMYRTS_NAV_V1_8197F) &                             \
+	 BIT_MASK_RXMYRTS_NAV_V1_8197F)
+#define BIT_SET_RXMYRTS_NAV_V1_8197F(x, v)                                     \
+	(BIT_CLEAR_RXMYRTS_NAV_V1_8197F(x) | BIT_RXMYRTS_NAV_V1_8197F(v))
+
+#define BIT_SHIFT_RTSRST_V1_8197F 0
+#define BIT_MASK_RTSRST_V1_8197F 0xff
+#define BIT_RTSRST_V1_8197F(x)                                                 \
+	(((x) & BIT_MASK_RTSRST_V1_8197F) << BIT_SHIFT_RTSRST_V1_8197F)
+#define BITS_RTSRST_V1_8197F                                                   \
+	(BIT_MASK_RTSRST_V1_8197F << BIT_SHIFT_RTSRST_V1_8197F)
+#define BIT_CLEAR_RTSRST_V1_8197F(x) ((x) & (~BITS_RTSRST_V1_8197F))
+#define BIT_GET_RTSRST_V1_8197F(x)                                             \
+	(((x) >> BIT_SHIFT_RTSRST_V1_8197F) & BIT_MASK_RTSRST_V1_8197F)
+#define BIT_SET_RTSRST_V1_8197F(x, v)                                          \
+	(BIT_CLEAR_RTSRST_V1_8197F(x) | BIT_RTSRST_V1_8197F(v))
+
+/* 2 REG_BT_COEX_ENHANCED_INTR_CTRL_8197F */
+
+#define BIT_SHIFT_BT_STAT_DELAY_8197F 12
+#define BIT_MASK_BT_STAT_DELAY_8197F 0xf
+#define BIT_BT_STAT_DELAY_8197F(x)                                             \
+	(((x) & BIT_MASK_BT_STAT_DELAY_8197F) << BIT_SHIFT_BT_STAT_DELAY_8197F)
+#define BITS_BT_STAT_DELAY_8197F                                               \
+	(BIT_MASK_BT_STAT_DELAY_8197F << BIT_SHIFT_BT_STAT_DELAY_8197F)
+#define BIT_CLEAR_BT_STAT_DELAY_8197F(x) ((x) & (~BITS_BT_STAT_DELAY_8197F))
+#define BIT_GET_BT_STAT_DELAY_8197F(x)                                         \
+	(((x) >> BIT_SHIFT_BT_STAT_DELAY_8197F) & BIT_MASK_BT_STAT_DELAY_8197F)
+#define BIT_SET_BT_STAT_DELAY_8197F(x, v)                                      \
+	(BIT_CLEAR_BT_STAT_DELAY_8197F(x) | BIT_BT_STAT_DELAY_8197F(v))
+
+#define BIT_SHIFT_BT_TRX_INIT_DETECT_8197F 8
+#define BIT_MASK_BT_TRX_INIT_DETECT_8197F 0xf
+#define BIT_BT_TRX_INIT_DETECT_8197F(x)                                        \
+	(((x) & BIT_MASK_BT_TRX_INIT_DETECT_8197F)                             \
+	 << BIT_SHIFT_BT_TRX_INIT_DETECT_8197F)
+#define BITS_BT_TRX_INIT_DETECT_8197F                                          \
+	(BIT_MASK_BT_TRX_INIT_DETECT_8197F                                     \
+	 << BIT_SHIFT_BT_TRX_INIT_DETECT_8197F)
+#define BIT_CLEAR_BT_TRX_INIT_DETECT_8197F(x)                                  \
+	((x) & (~BITS_BT_TRX_INIT_DETECT_8197F))
+#define BIT_GET_BT_TRX_INIT_DETECT_8197F(x)                                    \
+	(((x) >> BIT_SHIFT_BT_TRX_INIT_DETECT_8197F) &                         \
+	 BIT_MASK_BT_TRX_INIT_DETECT_8197F)
+#define BIT_SET_BT_TRX_INIT_DETECT_8197F(x, v)                                 \
+	(BIT_CLEAR_BT_TRX_INIT_DETECT_8197F(x) |                               \
+	 BIT_BT_TRX_INIT_DETECT_8197F(v))
+
+#define BIT_SHIFT_BT_PRI_DETECT_TO_8197F 4
+#define BIT_MASK_BT_PRI_DETECT_TO_8197F 0xf
+#define BIT_BT_PRI_DETECT_TO_8197F(x)                                          \
+	(((x) & BIT_MASK_BT_PRI_DETECT_TO_8197F)                               \
+	 << BIT_SHIFT_BT_PRI_DETECT_TO_8197F)
+#define BITS_BT_PRI_DETECT_TO_8197F                                            \
+	(BIT_MASK_BT_PRI_DETECT_TO_8197F << BIT_SHIFT_BT_PRI_DETECT_TO_8197F)
+#define BIT_CLEAR_BT_PRI_DETECT_TO_8197F(x)                                    \
+	((x) & (~BITS_BT_PRI_DETECT_TO_8197F))
+#define BIT_GET_BT_PRI_DETECT_TO_8197F(x)                                      \
+	(((x) >> BIT_SHIFT_BT_PRI_DETECT_TO_8197F) &                           \
+	 BIT_MASK_BT_PRI_DETECT_TO_8197F)
+#define BIT_SET_BT_PRI_DETECT_TO_8197F(x, v)                                   \
+	(BIT_CLEAR_BT_PRI_DETECT_TO_8197F(x) | BIT_BT_PRI_DETECT_TO_8197F(v))
+
+#define BIT_R_GRANTALL_WLMASK_8197F BIT(3)
+#define BIT_STATIS_BT_EN_8197F BIT(2)
+#define BIT_WL_ACT_MASK_ENABLE_8197F BIT(1)
+#define BIT_ENHANCED_BT_8197F BIT(0)
+
+/* 2 REG_BT_ACT_STATISTICS_8197F */
+
+#define BIT_SHIFT_STATIS_BT_LO_RX_8197F (48 & CPU_OPT_WIDTH)
+#define BIT_MASK_STATIS_BT_LO_RX_8197F 0xffff
+#define BIT_STATIS_BT_LO_RX_8197F(x)                                           \
+	(((x) & BIT_MASK_STATIS_BT_LO_RX_8197F)                                \
+	 << BIT_SHIFT_STATIS_BT_LO_RX_8197F)
+#define BITS_STATIS_BT_LO_RX_8197F                                             \
+	(BIT_MASK_STATIS_BT_LO_RX_8197F << BIT_SHIFT_STATIS_BT_LO_RX_8197F)
+#define BIT_CLEAR_STATIS_BT_LO_RX_8197F(x) ((x) & (~BITS_STATIS_BT_LO_RX_8197F))
+#define BIT_GET_STATIS_BT_LO_RX_8197F(x)                                       \
+	(((x) >> BIT_SHIFT_STATIS_BT_LO_RX_8197F) &                            \
+	 BIT_MASK_STATIS_BT_LO_RX_8197F)
+#define BIT_SET_STATIS_BT_LO_RX_8197F(x, v)                                    \
+	(BIT_CLEAR_STATIS_BT_LO_RX_8197F(x) | BIT_STATIS_BT_LO_RX_8197F(v))
+
+#define BIT_SHIFT_STATIS_BT_LO_TX_8197F (32 & CPU_OPT_WIDTH)
+#define BIT_MASK_STATIS_BT_LO_TX_8197F 0xffff
+#define BIT_STATIS_BT_LO_TX_8197F(x)                                           \
+	(((x) & BIT_MASK_STATIS_BT_LO_TX_8197F)                                \
+	 << BIT_SHIFT_STATIS_BT_LO_TX_8197F)
+#define BITS_STATIS_BT_LO_TX_8197F                                             \
+	(BIT_MASK_STATIS_BT_LO_TX_8197F << BIT_SHIFT_STATIS_BT_LO_TX_8197F)
+#define BIT_CLEAR_STATIS_BT_LO_TX_8197F(x) ((x) & (~BITS_STATIS_BT_LO_TX_8197F))
+#define BIT_GET_STATIS_BT_LO_TX_8197F(x)                                       \
+	(((x) >> BIT_SHIFT_STATIS_BT_LO_TX_8197F) &                            \
+	 BIT_MASK_STATIS_BT_LO_TX_8197F)
+#define BIT_SET_STATIS_BT_LO_TX_8197F(x, v)                                    \
+	(BIT_CLEAR_STATIS_BT_LO_TX_8197F(x) | BIT_STATIS_BT_LO_TX_8197F(v))
+
+#define BIT_SHIFT_STATIS_BT_HI_RX_8197F 16
+#define BIT_MASK_STATIS_BT_HI_RX_8197F 0xffff
+#define BIT_STATIS_BT_HI_RX_8197F(x)                                           \
+	(((x) & BIT_MASK_STATIS_BT_HI_RX_8197F)                                \
+	 << BIT_SHIFT_STATIS_BT_HI_RX_8197F)
+#define BITS_STATIS_BT_HI_RX_8197F                                             \
+	(BIT_MASK_STATIS_BT_HI_RX_8197F << BIT_SHIFT_STATIS_BT_HI_RX_8197F)
+#define BIT_CLEAR_STATIS_BT_HI_RX_8197F(x) ((x) & (~BITS_STATIS_BT_HI_RX_8197F))
+#define BIT_GET_STATIS_BT_HI_RX_8197F(x)                                       \
+	(((x) >> BIT_SHIFT_STATIS_BT_HI_RX_8197F) &                            \
+	 BIT_MASK_STATIS_BT_HI_RX_8197F)
+#define BIT_SET_STATIS_BT_HI_RX_8197F(x, v)                                    \
+	(BIT_CLEAR_STATIS_BT_HI_RX_8197F(x) | BIT_STATIS_BT_HI_RX_8197F(v))
+
+#define BIT_SHIFT_STATIS_BT_HI_TX_8197F 0
+#define BIT_MASK_STATIS_BT_HI_TX_8197F 0xffff
+#define BIT_STATIS_BT_HI_TX_8197F(x)                                           \
+	(((x) & BIT_MASK_STATIS_BT_HI_TX_8197F)                                \
+	 << BIT_SHIFT_STATIS_BT_HI_TX_8197F)
+#define BITS_STATIS_BT_HI_TX_8197F                                             \
+	(BIT_MASK_STATIS_BT_HI_TX_8197F << BIT_SHIFT_STATIS_BT_HI_TX_8197F)
+#define BIT_CLEAR_STATIS_BT_HI_TX_8197F(x) ((x) & (~BITS_STATIS_BT_HI_TX_8197F))
+#define BIT_GET_STATIS_BT_HI_TX_8197F(x)                                       \
+	(((x) >> BIT_SHIFT_STATIS_BT_HI_TX_8197F) &                            \
+	 BIT_MASK_STATIS_BT_HI_TX_8197F)
+#define BIT_SET_STATIS_BT_HI_TX_8197F(x, v)                                    \
+	(BIT_CLEAR_STATIS_BT_HI_TX_8197F(x) | BIT_STATIS_BT_HI_TX_8197F(v))
+
+/* 2 REG_BT_STATISTICS_CONTROL_REGISTER_8197F */
+
+#define BIT_SHIFT_R_BT_CMD_RPT_8197F 16
+#define BIT_MASK_R_BT_CMD_RPT_8197F 0xffff
+#define BIT_R_BT_CMD_RPT_8197F(x)                                              \
+	(((x) & BIT_MASK_R_BT_CMD_RPT_8197F) << BIT_SHIFT_R_BT_CMD_RPT_8197F)
+#define BITS_R_BT_CMD_RPT_8197F                                                \
+	(BIT_MASK_R_BT_CMD_RPT_8197F << BIT_SHIFT_R_BT_CMD_RPT_8197F)
+#define BIT_CLEAR_R_BT_CMD_RPT_8197F(x) ((x) & (~BITS_R_BT_CMD_RPT_8197F))
+#define BIT_GET_R_BT_CMD_RPT_8197F(x)                                          \
+	(((x) >> BIT_SHIFT_R_BT_CMD_RPT_8197F) & BIT_MASK_R_BT_CMD_RPT_8197F)
+#define BIT_SET_R_BT_CMD_RPT_8197F(x, v)                                       \
+	(BIT_CLEAR_R_BT_CMD_RPT_8197F(x) | BIT_R_BT_CMD_RPT_8197F(v))
+
+#define BIT_SHIFT_R_RPT_FROM_BT_8197F 8
+#define BIT_MASK_R_RPT_FROM_BT_8197F 0xff
+#define BIT_R_RPT_FROM_BT_8197F(x)                                             \
+	(((x) & BIT_MASK_R_RPT_FROM_BT_8197F) << BIT_SHIFT_R_RPT_FROM_BT_8197F)
+#define BITS_R_RPT_FROM_BT_8197F                                               \
+	(BIT_MASK_R_RPT_FROM_BT_8197F << BIT_SHIFT_R_RPT_FROM_BT_8197F)
+#define BIT_CLEAR_R_RPT_FROM_BT_8197F(x) ((x) & (~BITS_R_RPT_FROM_BT_8197F))
+#define BIT_GET_R_RPT_FROM_BT_8197F(x)                                         \
+	(((x) >> BIT_SHIFT_R_RPT_FROM_BT_8197F) & BIT_MASK_R_RPT_FROM_BT_8197F)
+#define BIT_SET_R_RPT_FROM_BT_8197F(x, v)                                      \
+	(BIT_CLEAR_R_RPT_FROM_BT_8197F(x) | BIT_R_RPT_FROM_BT_8197F(v))
+
+#define BIT_SHIFT_BT_HID_ISR_SET_8197F 6
+#define BIT_MASK_BT_HID_ISR_SET_8197F 0x3
+#define BIT_BT_HID_ISR_SET_8197F(x)                                            \
+	(((x) & BIT_MASK_BT_HID_ISR_SET_8197F)                                 \
+	 << BIT_SHIFT_BT_HID_ISR_SET_8197F)
+#define BITS_BT_HID_ISR_SET_8197F                                              \
+	(BIT_MASK_BT_HID_ISR_SET_8197F << BIT_SHIFT_BT_HID_ISR_SET_8197F)
+#define BIT_CLEAR_BT_HID_ISR_SET_8197F(x) ((x) & (~BITS_BT_HID_ISR_SET_8197F))
+#define BIT_GET_BT_HID_ISR_SET_8197F(x)                                        \
+	(((x) >> BIT_SHIFT_BT_HID_ISR_SET_8197F) &                             \
+	 BIT_MASK_BT_HID_ISR_SET_8197F)
+#define BIT_SET_BT_HID_ISR_SET_8197F(x, v)                                     \
+	(BIT_CLEAR_BT_HID_ISR_SET_8197F(x) | BIT_BT_HID_ISR_SET_8197F(v))
+
+#define BIT_TDMA_BT_START_NOTIFY_8197F BIT(5)
+#define BIT_ENABLE_TDMA_FW_MODE_8197F BIT(4)
+#define BIT_ENABLE_PTA_TDMA_MODE_8197F BIT(3)
+#define BIT_ENABLE_COEXIST_TAB_IN_TDMA_8197F BIT(2)
+#define BIT_GPIO2_GPIO3_EXANGE_OR_NO_BT_CCA_8197F BIT(1)
+#define BIT_RTK_BT_ENABLE_8197F BIT(0)
+
+/* 2 REG_BT_STATUS_REPORT_REGISTER_8197F */
+
+#define BIT_SHIFT_BT_PROFILE_8197F 24
+#define BIT_MASK_BT_PROFILE_8197F 0xff
+#define BIT_BT_PROFILE_8197F(x)                                                \
+	(((x) & BIT_MASK_BT_PROFILE_8197F) << BIT_SHIFT_BT_PROFILE_8197F)
+#define BITS_BT_PROFILE_8197F                                                  \
+	(BIT_MASK_BT_PROFILE_8197F << BIT_SHIFT_BT_PROFILE_8197F)
+#define BIT_CLEAR_BT_PROFILE_8197F(x) ((x) & (~BITS_BT_PROFILE_8197F))
+#define BIT_GET_BT_PROFILE_8197F(x)                                            \
+	(((x) >> BIT_SHIFT_BT_PROFILE_8197F) & BIT_MASK_BT_PROFILE_8197F)
+#define BIT_SET_BT_PROFILE_8197F(x, v)                                         \
+	(BIT_CLEAR_BT_PROFILE_8197F(x) | BIT_BT_PROFILE_8197F(v))
+
+#define BIT_SHIFT_BT_POWER_8197F 16
+#define BIT_MASK_BT_POWER_8197F 0xff
+#define BIT_BT_POWER_8197F(x)                                                  \
+	(((x) & BIT_MASK_BT_POWER_8197F) << BIT_SHIFT_BT_POWER_8197F)
+#define BITS_BT_POWER_8197F                                                    \
+	(BIT_MASK_BT_POWER_8197F << BIT_SHIFT_BT_POWER_8197F)
+#define BIT_CLEAR_BT_POWER_8197F(x) ((x) & (~BITS_BT_POWER_8197F))
+#define BIT_GET_BT_POWER_8197F(x)                                              \
+	(((x) >> BIT_SHIFT_BT_POWER_8197F) & BIT_MASK_BT_POWER_8197F)
+#define BIT_SET_BT_POWER_8197F(x, v)                                           \
+	(BIT_CLEAR_BT_POWER_8197F(x) | BIT_BT_POWER_8197F(v))
+
+#define BIT_SHIFT_BT_PREDECT_STATUS_8197F 8
+#define BIT_MASK_BT_PREDECT_STATUS_8197F 0xff
+#define BIT_BT_PREDECT_STATUS_8197F(x)                                         \
+	(((x) & BIT_MASK_BT_PREDECT_STATUS_8197F)                              \
+	 << BIT_SHIFT_BT_PREDECT_STATUS_8197F)
+#define BITS_BT_PREDECT_STATUS_8197F                                           \
+	(BIT_MASK_BT_PREDECT_STATUS_8197F << BIT_SHIFT_BT_PREDECT_STATUS_8197F)
+#define BIT_CLEAR_BT_PREDECT_STATUS_8197F(x)                                   \
+	((x) & (~BITS_BT_PREDECT_STATUS_8197F))
+#define BIT_GET_BT_PREDECT_STATUS_8197F(x)                                     \
+	(((x) >> BIT_SHIFT_BT_PREDECT_STATUS_8197F) &                          \
+	 BIT_MASK_BT_PREDECT_STATUS_8197F)
+#define BIT_SET_BT_PREDECT_STATUS_8197F(x, v)                                  \
+	(BIT_CLEAR_BT_PREDECT_STATUS_8197F(x) | BIT_BT_PREDECT_STATUS_8197F(v))
+
+#define BIT_SHIFT_BT_CMD_INFO_8197F 0
+#define BIT_MASK_BT_CMD_INFO_8197F 0xff
+#define BIT_BT_CMD_INFO_8197F(x)                                               \
+	(((x) & BIT_MASK_BT_CMD_INFO_8197F) << BIT_SHIFT_BT_CMD_INFO_8197F)
+#define BITS_BT_CMD_INFO_8197F                                                 \
+	(BIT_MASK_BT_CMD_INFO_8197F << BIT_SHIFT_BT_CMD_INFO_8197F)
+#define BIT_CLEAR_BT_CMD_INFO_8197F(x) ((x) & (~BITS_BT_CMD_INFO_8197F))
+#define BIT_GET_BT_CMD_INFO_8197F(x)                                           \
+	(((x) >> BIT_SHIFT_BT_CMD_INFO_8197F) & BIT_MASK_BT_CMD_INFO_8197F)
+#define BIT_SET_BT_CMD_INFO_8197F(x, v)                                        \
+	(BIT_CLEAR_BT_CMD_INFO_8197F(x) | BIT_BT_CMD_INFO_8197F(v))
+
+/* 2 REG_BT_INTERRUPT_CONTROL_REGISTER_8197F */
+#define BIT_EN_MAC_NULL_PKT_NOTIFY_8197F BIT(31)
+#define BIT_EN_WLAN_RPT_AND_BT_QUERY_8197F BIT(30)
+#define BIT_EN_BT_STSTUS_RPT_8197F BIT(29)
+#define BIT_EN_BT_POWER_8197F BIT(28)
+#define BIT_EN_BT_CHANNEL_8197F BIT(27)
+#define BIT_EN_BT_SLOT_CHANGE_8197F BIT(26)
+#define BIT_EN_BT_PROFILE_OR_HID_8197F BIT(25)
+#define BIT_WLAN_RPT_NOTIFY_8197F BIT(24)
+
+#define BIT_SHIFT_WLAN_RPT_DATA_8197F 16
+#define BIT_MASK_WLAN_RPT_DATA_8197F 0xff
+#define BIT_WLAN_RPT_DATA_8197F(x)                                             \
+	(((x) & BIT_MASK_WLAN_RPT_DATA_8197F) << BIT_SHIFT_WLAN_RPT_DATA_8197F)
+#define BITS_WLAN_RPT_DATA_8197F                                               \
+	(BIT_MASK_WLAN_RPT_DATA_8197F << BIT_SHIFT_WLAN_RPT_DATA_8197F)
+#define BIT_CLEAR_WLAN_RPT_DATA_8197F(x) ((x) & (~BITS_WLAN_RPT_DATA_8197F))
+#define BIT_GET_WLAN_RPT_DATA_8197F(x)                                         \
+	(((x) >> BIT_SHIFT_WLAN_RPT_DATA_8197F) & BIT_MASK_WLAN_RPT_DATA_8197F)
+#define BIT_SET_WLAN_RPT_DATA_8197F(x, v)                                      \
+	(BIT_CLEAR_WLAN_RPT_DATA_8197F(x) | BIT_WLAN_RPT_DATA_8197F(v))
+
+#define BIT_SHIFT_CMD_ID_8197F 8
+#define BIT_MASK_CMD_ID_8197F 0xff
+#define BIT_CMD_ID_8197F(x)                                                    \
+	(((x) & BIT_MASK_CMD_ID_8197F) << BIT_SHIFT_CMD_ID_8197F)
+#define BITS_CMD_ID_8197F (BIT_MASK_CMD_ID_8197F << BIT_SHIFT_CMD_ID_8197F)
+#define BIT_CLEAR_CMD_ID_8197F(x) ((x) & (~BITS_CMD_ID_8197F))
+#define BIT_GET_CMD_ID_8197F(x)                                                \
+	(((x) >> BIT_SHIFT_CMD_ID_8197F) & BIT_MASK_CMD_ID_8197F)
+#define BIT_SET_CMD_ID_8197F(x, v)                                             \
+	(BIT_CLEAR_CMD_ID_8197F(x) | BIT_CMD_ID_8197F(v))
+
+#define BIT_SHIFT_BT_DATA_8197F 0
+#define BIT_MASK_BT_DATA_8197F 0xff
+#define BIT_BT_DATA_8197F(x)                                                   \
+	(((x) & BIT_MASK_BT_DATA_8197F) << BIT_SHIFT_BT_DATA_8197F)
+#define BITS_BT_DATA_8197F (BIT_MASK_BT_DATA_8197F << BIT_SHIFT_BT_DATA_8197F)
+#define BIT_CLEAR_BT_DATA_8197F(x) ((x) & (~BITS_BT_DATA_8197F))
+#define BIT_GET_BT_DATA_8197F(x)                                               \
+	(((x) >> BIT_SHIFT_BT_DATA_8197F) & BIT_MASK_BT_DATA_8197F)
+#define BIT_SET_BT_DATA_8197F(x, v)                                            \
+	(BIT_CLEAR_BT_DATA_8197F(x) | BIT_BT_DATA_8197F(v))
+
+/* 2 REG_WLAN_REPORT_TIME_OUT_CONTROL_REGISTER_8197F */
+
+#define BIT_SHIFT_WLAN_RPT_TO_8197F 0
+#define BIT_MASK_WLAN_RPT_TO_8197F 0xff
+#define BIT_WLAN_RPT_TO_8197F(x)                                               \
+	(((x) & BIT_MASK_WLAN_RPT_TO_8197F) << BIT_SHIFT_WLAN_RPT_TO_8197F)
+#define BITS_WLAN_RPT_TO_8197F                                                 \
+	(BIT_MASK_WLAN_RPT_TO_8197F << BIT_SHIFT_WLAN_RPT_TO_8197F)
+#define BIT_CLEAR_WLAN_RPT_TO_8197F(x) ((x) & (~BITS_WLAN_RPT_TO_8197F))
+#define BIT_GET_WLAN_RPT_TO_8197F(x)                                           \
+	(((x) >> BIT_SHIFT_WLAN_RPT_TO_8197F) & BIT_MASK_WLAN_RPT_TO_8197F)
+#define BIT_SET_WLAN_RPT_TO_8197F(x, v)                                        \
+	(BIT_CLEAR_WLAN_RPT_TO_8197F(x) | BIT_WLAN_RPT_TO_8197F(v))
+
+/* 2 REG_BT_ISOLATION_TABLE_REGISTER_REGISTER_8197F */
+
+#define BIT_SHIFT_ISOLATION_CHK_8197F 1
+#define BIT_MASK_ISOLATION_CHK_8197F 0x7fffffffffffffffffffL
+#define BIT_ISOLATION_CHK_8197F(x)                                             \
+	(((x) & BIT_MASK_ISOLATION_CHK_8197F) << BIT_SHIFT_ISOLATION_CHK_8197F)
+#define BITS_ISOLATION_CHK_8197F                                               \
+	(BIT_MASK_ISOLATION_CHK_8197F << BIT_SHIFT_ISOLATION_CHK_8197F)
+#define BIT_CLEAR_ISOLATION_CHK_8197F(x) ((x) & (~BITS_ISOLATION_CHK_8197F))
+#define BIT_GET_ISOLATION_CHK_8197F(x)                                         \
+	(((x) >> BIT_SHIFT_ISOLATION_CHK_8197F) & BIT_MASK_ISOLATION_CHK_8197F)
+#define BIT_SET_ISOLATION_CHK_8197F(x, v)                                      \
+	(BIT_CLEAR_ISOLATION_CHK_8197F(x) | BIT_ISOLATION_CHK_8197F(v))
+
+#define BIT_ISOLATION_EN_8197F BIT(0)
+
+/* 2 REG_BT_INTERRUPT_STATUS_REGISTER_8197F */
+#define BIT_BT_HID_ISR_8197F BIT(7)
+#define BIT_BT_QUERY_ISR_8197F BIT(6)
+#define BIT_MAC_NULL_PKT_NOTIFY_ISR_8197F BIT(5)
+#define BIT_WLAN_RPT_ISR_8197F BIT(4)
+#define BIT_BT_POWER_ISR_8197F BIT(3)
+#define BIT_BT_CHANNEL_ISR_8197F BIT(2)
+#define BIT_BT_SLOT_CHANGE_ISR_8197F BIT(1)
+#define BIT_BT_PROFILE_ISR_8197F BIT(0)
+
+/* 2 REG_BT_TDMA_TIME_REGISTER_8197F */
+
+#define BIT_SHIFT_BT_TIME_8197F 6
+#define BIT_MASK_BT_TIME_8197F 0x3ffffff
+#define BIT_BT_TIME_8197F(x)                                                   \
+	(((x) & BIT_MASK_BT_TIME_8197F) << BIT_SHIFT_BT_TIME_8197F)
+#define BITS_BT_TIME_8197F (BIT_MASK_BT_TIME_8197F << BIT_SHIFT_BT_TIME_8197F)
+#define BIT_CLEAR_BT_TIME_8197F(x) ((x) & (~BITS_BT_TIME_8197F))
+#define BIT_GET_BT_TIME_8197F(x)                                               \
+	(((x) >> BIT_SHIFT_BT_TIME_8197F) & BIT_MASK_BT_TIME_8197F)
+#define BIT_SET_BT_TIME_8197F(x, v)                                            \
+	(BIT_CLEAR_BT_TIME_8197F(x) | BIT_BT_TIME_8197F(v))
+
+#define BIT_SHIFT_BT_RPT_SAMPLE_RATE_8197F 0
+#define BIT_MASK_BT_RPT_SAMPLE_RATE_8197F 0x3f
+#define BIT_BT_RPT_SAMPLE_RATE_8197F(x)                                        \
+	(((x) & BIT_MASK_BT_RPT_SAMPLE_RATE_8197F)                             \
+	 << BIT_SHIFT_BT_RPT_SAMPLE_RATE_8197F)
+#define BITS_BT_RPT_SAMPLE_RATE_8197F                                          \
+	(BIT_MASK_BT_RPT_SAMPLE_RATE_8197F                                     \
+	 << BIT_SHIFT_BT_RPT_SAMPLE_RATE_8197F)
+#define BIT_CLEAR_BT_RPT_SAMPLE_RATE_8197F(x)                                  \
+	((x) & (~BITS_BT_RPT_SAMPLE_RATE_8197F))
+#define BIT_GET_BT_RPT_SAMPLE_RATE_8197F(x)                                    \
+	(((x) >> BIT_SHIFT_BT_RPT_SAMPLE_RATE_8197F) &                         \
+	 BIT_MASK_BT_RPT_SAMPLE_RATE_8197F)
+#define BIT_SET_BT_RPT_SAMPLE_RATE_8197F(x, v)                                 \
+	(BIT_CLEAR_BT_RPT_SAMPLE_RATE_8197F(x) |                               \
+	 BIT_BT_RPT_SAMPLE_RATE_8197F(v))
+
+/* 2 REG_BT_ACT_REGISTER_8197F */
+
+#define BIT_SHIFT_BT_EISR_EN_8197F 16
+#define BIT_MASK_BT_EISR_EN_8197F 0xff
+#define BIT_BT_EISR_EN_8197F(x)                                                \
+	(((x) & BIT_MASK_BT_EISR_EN_8197F) << BIT_SHIFT_BT_EISR_EN_8197F)
+#define BITS_BT_EISR_EN_8197F                                                  \
+	(BIT_MASK_BT_EISR_EN_8197F << BIT_SHIFT_BT_EISR_EN_8197F)
+#define BIT_CLEAR_BT_EISR_EN_8197F(x) ((x) & (~BITS_BT_EISR_EN_8197F))
+#define BIT_GET_BT_EISR_EN_8197F(x)                                            \
+	(((x) >> BIT_SHIFT_BT_EISR_EN_8197F) & BIT_MASK_BT_EISR_EN_8197F)
+#define BIT_SET_BT_EISR_EN_8197F(x, v)                                         \
+	(BIT_CLEAR_BT_EISR_EN_8197F(x) | BIT_BT_EISR_EN_8197F(v))
+
+#define BIT_BT_ACT_FALLING_ISR_8197F BIT(10)
+#define BIT_BT_ACT_RISING_ISR_8197F BIT(9)
+#define BIT_TDMA_TO_ISR_8197F BIT(8)
+
+#define BIT_SHIFT_BT_CH_8197F 0
+#define BIT_MASK_BT_CH_8197F 0xff
+#define BIT_BT_CH_8197F(x)                                                     \
+	(((x) & BIT_MASK_BT_CH_8197F) << BIT_SHIFT_BT_CH_8197F)
+#define BITS_BT_CH_8197F (BIT_MASK_BT_CH_8197F << BIT_SHIFT_BT_CH_8197F)
+#define BIT_CLEAR_BT_CH_8197F(x) ((x) & (~BITS_BT_CH_8197F))
+#define BIT_GET_BT_CH_8197F(x)                                                 \
+	(((x) >> BIT_SHIFT_BT_CH_8197F) & BIT_MASK_BT_CH_8197F)
+#define BIT_SET_BT_CH_8197F(x, v)                                              \
+	(BIT_CLEAR_BT_CH_8197F(x) | BIT_BT_CH_8197F(v))
+
+/* 2 REG_OBFF_CTRL_BASIC_8197F */
+#define BIT_OBFF_EN_V1_8197F BIT(31)
+
+#define BIT_SHIFT_OBFF_STATE_V1_8197F 28
+#define BIT_MASK_OBFF_STATE_V1_8197F 0x3
+#define BIT_OBFF_STATE_V1_8197F(x)                                             \
+	(((x) & BIT_MASK_OBFF_STATE_V1_8197F) << BIT_SHIFT_OBFF_STATE_V1_8197F)
+#define BITS_OBFF_STATE_V1_8197F                                               \
+	(BIT_MASK_OBFF_STATE_V1_8197F << BIT_SHIFT_OBFF_STATE_V1_8197F)
+#define BIT_CLEAR_OBFF_STATE_V1_8197F(x) ((x) & (~BITS_OBFF_STATE_V1_8197F))
+#define BIT_GET_OBFF_STATE_V1_8197F(x)                                         \
+	(((x) >> BIT_SHIFT_OBFF_STATE_V1_8197F) & BIT_MASK_OBFF_STATE_V1_8197F)
+#define BIT_SET_OBFF_STATE_V1_8197F(x, v)                                      \
+	(BIT_CLEAR_OBFF_STATE_V1_8197F(x) | BIT_OBFF_STATE_V1_8197F(v))
+
+#define BIT_OBFF_ACT_RXDMA_EN_8197F BIT(27)
+#define BIT_OBFF_BLOCK_INT_EN_8197F BIT(26)
+#define BIT_OBFF_AUTOACT_EN_8197F BIT(25)
+#define BIT_OBFF_AUTOIDLE_EN_8197F BIT(24)
+
+#define BIT_SHIFT_WAKE_MAX_PLS_8197F 20
+#define BIT_MASK_WAKE_MAX_PLS_8197F 0x7
+#define BIT_WAKE_MAX_PLS_8197F(x)                                              \
+	(((x) & BIT_MASK_WAKE_MAX_PLS_8197F) << BIT_SHIFT_WAKE_MAX_PLS_8197F)
+#define BITS_WAKE_MAX_PLS_8197F                                                \
+	(BIT_MASK_WAKE_MAX_PLS_8197F << BIT_SHIFT_WAKE_MAX_PLS_8197F)
+#define BIT_CLEAR_WAKE_MAX_PLS_8197F(x) ((x) & (~BITS_WAKE_MAX_PLS_8197F))
+#define BIT_GET_WAKE_MAX_PLS_8197F(x)                                          \
+	(((x) >> BIT_SHIFT_WAKE_MAX_PLS_8197F) & BIT_MASK_WAKE_MAX_PLS_8197F)
+#define BIT_SET_WAKE_MAX_PLS_8197F(x, v)                                       \
+	(BIT_CLEAR_WAKE_MAX_PLS_8197F(x) | BIT_WAKE_MAX_PLS_8197F(v))
+
+#define BIT_SHIFT_WAKE_MIN_PLS_8197F 16
+#define BIT_MASK_WAKE_MIN_PLS_8197F 0x7
+#define BIT_WAKE_MIN_PLS_8197F(x)                                              \
+	(((x) & BIT_MASK_WAKE_MIN_PLS_8197F) << BIT_SHIFT_WAKE_MIN_PLS_8197F)
+#define BITS_WAKE_MIN_PLS_8197F                                                \
+	(BIT_MASK_WAKE_MIN_PLS_8197F << BIT_SHIFT_WAKE_MIN_PLS_8197F)
+#define BIT_CLEAR_WAKE_MIN_PLS_8197F(x) ((x) & (~BITS_WAKE_MIN_PLS_8197F))
+#define BIT_GET_WAKE_MIN_PLS_8197F(x)                                          \
+	(((x) >> BIT_SHIFT_WAKE_MIN_PLS_8197F) & BIT_MASK_WAKE_MIN_PLS_8197F)
+#define BIT_SET_WAKE_MIN_PLS_8197F(x, v)                                       \
+	(BIT_CLEAR_WAKE_MIN_PLS_8197F(x) | BIT_WAKE_MIN_PLS_8197F(v))
+
+#define BIT_SHIFT_WAKE_MAX_F2F_8197F 12
+#define BIT_MASK_WAKE_MAX_F2F_8197F 0x7
+#define BIT_WAKE_MAX_F2F_8197F(x)                                              \
+	(((x) & BIT_MASK_WAKE_MAX_F2F_8197F) << BIT_SHIFT_WAKE_MAX_F2F_8197F)
+#define BITS_WAKE_MAX_F2F_8197F                                                \
+	(BIT_MASK_WAKE_MAX_F2F_8197F << BIT_SHIFT_WAKE_MAX_F2F_8197F)
+#define BIT_CLEAR_WAKE_MAX_F2F_8197F(x) ((x) & (~BITS_WAKE_MAX_F2F_8197F))
+#define BIT_GET_WAKE_MAX_F2F_8197F(x)                                          \
+	(((x) >> BIT_SHIFT_WAKE_MAX_F2F_8197F) & BIT_MASK_WAKE_MAX_F2F_8197F)
+#define BIT_SET_WAKE_MAX_F2F_8197F(x, v)                                       \
+	(BIT_CLEAR_WAKE_MAX_F2F_8197F(x) | BIT_WAKE_MAX_F2F_8197F(v))
+
+#define BIT_SHIFT_WAKE_MIN_F2F_8197F 8
+#define BIT_MASK_WAKE_MIN_F2F_8197F 0x7
+#define BIT_WAKE_MIN_F2F_8197F(x)                                              \
+	(((x) & BIT_MASK_WAKE_MIN_F2F_8197F) << BIT_SHIFT_WAKE_MIN_F2F_8197F)
+#define BITS_WAKE_MIN_F2F_8197F                                                \
+	(BIT_MASK_WAKE_MIN_F2F_8197F << BIT_SHIFT_WAKE_MIN_F2F_8197F)
+#define BIT_CLEAR_WAKE_MIN_F2F_8197F(x) ((x) & (~BITS_WAKE_MIN_F2F_8197F))
+#define BIT_GET_WAKE_MIN_F2F_8197F(x)                                          \
+	(((x) >> BIT_SHIFT_WAKE_MIN_F2F_8197F) & BIT_MASK_WAKE_MIN_F2F_8197F)
+#define BIT_SET_WAKE_MIN_F2F_8197F(x, v)                                       \
+	(BIT_CLEAR_WAKE_MIN_F2F_8197F(x) | BIT_WAKE_MIN_F2F_8197F(v))
+
+#define BIT_APP_CPU_ACT_V1_8197F BIT(3)
+#define BIT_APP_OBFF_V1_8197F BIT(2)
+#define BIT_APP_IDLE_V1_8197F BIT(1)
+#define BIT_APP_INIT_V1_8197F BIT(0)
+
+/* 2 REG_OBFF_CTRL2_TIMER_8197F */
+
+#define BIT_SHIFT_RX_HIGH_TIMER_IDX_8197F 24
+#define BIT_MASK_RX_HIGH_TIMER_IDX_8197F 0x7
+#define BIT_RX_HIGH_TIMER_IDX_8197F(x)                                         \
+	(((x) & BIT_MASK_RX_HIGH_TIMER_IDX_8197F)                              \
+	 << BIT_SHIFT_RX_HIGH_TIMER_IDX_8197F)
+#define BITS_RX_HIGH_TIMER_IDX_8197F                                           \
+	(BIT_MASK_RX_HIGH_TIMER_IDX_8197F << BIT_SHIFT_RX_HIGH_TIMER_IDX_8197F)
+#define BIT_CLEAR_RX_HIGH_TIMER_IDX_8197F(x)                                   \
+	((x) & (~BITS_RX_HIGH_TIMER_IDX_8197F))
+#define BIT_GET_RX_HIGH_TIMER_IDX_8197F(x)                                     \
+	(((x) >> BIT_SHIFT_RX_HIGH_TIMER_IDX_8197F) &                          \
+	 BIT_MASK_RX_HIGH_TIMER_IDX_8197F)
+#define BIT_SET_RX_HIGH_TIMER_IDX_8197F(x, v)                                  \
+	(BIT_CLEAR_RX_HIGH_TIMER_IDX_8197F(x) | BIT_RX_HIGH_TIMER_IDX_8197F(v))
+
+#define BIT_SHIFT_RX_MED_TIMER_IDX_8197F 16
+#define BIT_MASK_RX_MED_TIMER_IDX_8197F 0x7
+#define BIT_RX_MED_TIMER_IDX_8197F(x)                                          \
+	(((x) & BIT_MASK_RX_MED_TIMER_IDX_8197F)                               \
+	 << BIT_SHIFT_RX_MED_TIMER_IDX_8197F)
+#define BITS_RX_MED_TIMER_IDX_8197F                                            \
+	(BIT_MASK_RX_MED_TIMER_IDX_8197F << BIT_SHIFT_RX_MED_TIMER_IDX_8197F)
+#define BIT_CLEAR_RX_MED_TIMER_IDX_8197F(x)                                    \
+	((x) & (~BITS_RX_MED_TIMER_IDX_8197F))
+#define BIT_GET_RX_MED_TIMER_IDX_8197F(x)                                      \
+	(((x) >> BIT_SHIFT_RX_MED_TIMER_IDX_8197F) &                           \
+	 BIT_MASK_RX_MED_TIMER_IDX_8197F)
+#define BIT_SET_RX_MED_TIMER_IDX_8197F(x, v)                                   \
+	(BIT_CLEAR_RX_MED_TIMER_IDX_8197F(x) | BIT_RX_MED_TIMER_IDX_8197F(v))
+
+#define BIT_SHIFT_RX_LOW_TIMER_IDX_8197F 8
+#define BIT_MASK_RX_LOW_TIMER_IDX_8197F 0x7
+#define BIT_RX_LOW_TIMER_IDX_8197F(x)                                          \
+	(((x) & BIT_MASK_RX_LOW_TIMER_IDX_8197F)                               \
+	 << BIT_SHIFT_RX_LOW_TIMER_IDX_8197F)
+#define BITS_RX_LOW_TIMER_IDX_8197F                                            \
+	(BIT_MASK_RX_LOW_TIMER_IDX_8197F << BIT_SHIFT_RX_LOW_TIMER_IDX_8197F)
+#define BIT_CLEAR_RX_LOW_TIMER_IDX_8197F(x)                                    \
+	((x) & (~BITS_RX_LOW_TIMER_IDX_8197F))
+#define BIT_GET_RX_LOW_TIMER_IDX_8197F(x)                                      \
+	(((x) >> BIT_SHIFT_RX_LOW_TIMER_IDX_8197F) &                           \
+	 BIT_MASK_RX_LOW_TIMER_IDX_8197F)
+#define BIT_SET_RX_LOW_TIMER_IDX_8197F(x, v)                                   \
+	(BIT_CLEAR_RX_LOW_TIMER_IDX_8197F(x) | BIT_RX_LOW_TIMER_IDX_8197F(v))
+
+#define BIT_SHIFT_OBFF_INT_TIMER_IDX_8197F 0
+#define BIT_MASK_OBFF_INT_TIMER_IDX_8197F 0x7
+#define BIT_OBFF_INT_TIMER_IDX_8197F(x)                                        \
+	(((x) & BIT_MASK_OBFF_INT_TIMER_IDX_8197F)                             \
+	 << BIT_SHIFT_OBFF_INT_TIMER_IDX_8197F)
+#define BITS_OBFF_INT_TIMER_IDX_8197F                                          \
+	(BIT_MASK_OBFF_INT_TIMER_IDX_8197F                                     \
+	 << BIT_SHIFT_OBFF_INT_TIMER_IDX_8197F)
+#define BIT_CLEAR_OBFF_INT_TIMER_IDX_8197F(x)                                  \
+	((x) & (~BITS_OBFF_INT_TIMER_IDX_8197F))
+#define BIT_GET_OBFF_INT_TIMER_IDX_8197F(x)                                    \
+	(((x) >> BIT_SHIFT_OBFF_INT_TIMER_IDX_8197F) &                         \
+	 BIT_MASK_OBFF_INT_TIMER_IDX_8197F)
+#define BIT_SET_OBFF_INT_TIMER_IDX_8197F(x, v)                                 \
+	(BIT_CLEAR_OBFF_INT_TIMER_IDX_8197F(x) |                               \
+	 BIT_OBFF_INT_TIMER_IDX_8197F(v))
+
+/* 2 REG_LTR_CTRL_BASIC_8197F */
+#define BIT_LTR_EN_V1_8197F BIT(31)
+#define BIT_LTR_HW_EN_V1_8197F BIT(30)
+#define BIT_LRT_ACT_CTS_EN_8197F BIT(29)
+#define BIT_LTR_ACT_RXPKT_EN_8197F BIT(28)
+#define BIT_LTR_ACT_RXDMA_EN_8197F BIT(27)
+#define BIT_LTR_IDLE_NO_SNOOP_8197F BIT(26)
+#define BIT_SPDUP_MGTPKT_8197F BIT(25)
+#define BIT_RX_AGG_EN_8197F BIT(24)
+#define BIT_APP_LTR_ACT_8197F BIT(23)
+#define BIT_APP_LTR_IDLE_8197F BIT(22)
+
+#define BIT_SHIFT_HIGH_RATE_TRIG_SEL_8197F 20
+#define BIT_MASK_HIGH_RATE_TRIG_SEL_8197F 0x3
+#define BIT_HIGH_RATE_TRIG_SEL_8197F(x)                                        \
+	(((x) & BIT_MASK_HIGH_RATE_TRIG_SEL_8197F)                             \
+	 << BIT_SHIFT_HIGH_RATE_TRIG_SEL_8197F)
+#define BITS_HIGH_RATE_TRIG_SEL_8197F                                          \
+	(BIT_MASK_HIGH_RATE_TRIG_SEL_8197F                                     \
+	 << BIT_SHIFT_HIGH_RATE_TRIG_SEL_8197F)
+#define BIT_CLEAR_HIGH_RATE_TRIG_SEL_8197F(x)                                  \
+	((x) & (~BITS_HIGH_RATE_TRIG_SEL_8197F))
+#define BIT_GET_HIGH_RATE_TRIG_SEL_8197F(x)                                    \
+	(((x) >> BIT_SHIFT_HIGH_RATE_TRIG_SEL_8197F) &                         \
+	 BIT_MASK_HIGH_RATE_TRIG_SEL_8197F)
+#define BIT_SET_HIGH_RATE_TRIG_SEL_8197F(x, v)                                 \
+	(BIT_CLEAR_HIGH_RATE_TRIG_SEL_8197F(x) |                               \
+	 BIT_HIGH_RATE_TRIG_SEL_8197F(v))
+
+#define BIT_SHIFT_MED_RATE_TRIG_SEL_8197F 18
+#define BIT_MASK_MED_RATE_TRIG_SEL_8197F 0x3
+#define BIT_MED_RATE_TRIG_SEL_8197F(x)                                         \
+	(((x) & BIT_MASK_MED_RATE_TRIG_SEL_8197F)                              \
+	 << BIT_SHIFT_MED_RATE_TRIG_SEL_8197F)
+#define BITS_MED_RATE_TRIG_SEL_8197F                                           \
+	(BIT_MASK_MED_RATE_TRIG_SEL_8197F << BIT_SHIFT_MED_RATE_TRIG_SEL_8197F)
+#define BIT_CLEAR_MED_RATE_TRIG_SEL_8197F(x)                                   \
+	((x) & (~BITS_MED_RATE_TRIG_SEL_8197F))
+#define BIT_GET_MED_RATE_TRIG_SEL_8197F(x)                                     \
+	(((x) >> BIT_SHIFT_MED_RATE_TRIG_SEL_8197F) &                          \
+	 BIT_MASK_MED_RATE_TRIG_SEL_8197F)
+#define BIT_SET_MED_RATE_TRIG_SEL_8197F(x, v)                                  \
+	(BIT_CLEAR_MED_RATE_TRIG_SEL_8197F(x) | BIT_MED_RATE_TRIG_SEL_8197F(v))
+
+#define BIT_SHIFT_LOW_RATE_TRIG_SEL_8197F 16
+#define BIT_MASK_LOW_RATE_TRIG_SEL_8197F 0x3
+#define BIT_LOW_RATE_TRIG_SEL_8197F(x)                                         \
+	(((x) & BIT_MASK_LOW_RATE_TRIG_SEL_8197F)                              \
+	 << BIT_SHIFT_LOW_RATE_TRIG_SEL_8197F)
+#define BITS_LOW_RATE_TRIG_SEL_8197F                                           \
+	(BIT_MASK_LOW_RATE_TRIG_SEL_8197F << BIT_SHIFT_LOW_RATE_TRIG_SEL_8197F)
+#define BIT_CLEAR_LOW_RATE_TRIG_SEL_8197F(x)                                   \
+	((x) & (~BITS_LOW_RATE_TRIG_SEL_8197F))
+#define BIT_GET_LOW_RATE_TRIG_SEL_8197F(x)                                     \
+	(((x) >> BIT_SHIFT_LOW_RATE_TRIG_SEL_8197F) &                          \
+	 BIT_MASK_LOW_RATE_TRIG_SEL_8197F)
+#define BIT_SET_LOW_RATE_TRIG_SEL_8197F(x, v)                                  \
+	(BIT_CLEAR_LOW_RATE_TRIG_SEL_8197F(x) | BIT_LOW_RATE_TRIG_SEL_8197F(v))
+
+#define BIT_SHIFT_HIGH_RATE_BD_IDX_8197F 8
+#define BIT_MASK_HIGH_RATE_BD_IDX_8197F 0x7f
+#define BIT_HIGH_RATE_BD_IDX_8197F(x)                                          \
+	(((x) & BIT_MASK_HIGH_RATE_BD_IDX_8197F)                               \
+	 << BIT_SHIFT_HIGH_RATE_BD_IDX_8197F)
+#define BITS_HIGH_RATE_BD_IDX_8197F                                            \
+	(BIT_MASK_HIGH_RATE_BD_IDX_8197F << BIT_SHIFT_HIGH_RATE_BD_IDX_8197F)
+#define BIT_CLEAR_HIGH_RATE_BD_IDX_8197F(x)                                    \
+	((x) & (~BITS_HIGH_RATE_BD_IDX_8197F))
+#define BIT_GET_HIGH_RATE_BD_IDX_8197F(x)                                      \
+	(((x) >> BIT_SHIFT_HIGH_RATE_BD_IDX_8197F) &                           \
+	 BIT_MASK_HIGH_RATE_BD_IDX_8197F)
+#define BIT_SET_HIGH_RATE_BD_IDX_8197F(x, v)                                   \
+	(BIT_CLEAR_HIGH_RATE_BD_IDX_8197F(x) | BIT_HIGH_RATE_BD_IDX_8197F(v))
+
+#define BIT_SHIFT_LOW_RATE_BD_IDX_8197F 0
+#define BIT_MASK_LOW_RATE_BD_IDX_8197F 0x7f
+#define BIT_LOW_RATE_BD_IDX_8197F(x)                                           \
+	(((x) & BIT_MASK_LOW_RATE_BD_IDX_8197F)                                \
+	 << BIT_SHIFT_LOW_RATE_BD_IDX_8197F)
+#define BITS_LOW_RATE_BD_IDX_8197F                                             \
+	(BIT_MASK_LOW_RATE_BD_IDX_8197F << BIT_SHIFT_LOW_RATE_BD_IDX_8197F)
+#define BIT_CLEAR_LOW_RATE_BD_IDX_8197F(x) ((x) & (~BITS_LOW_RATE_BD_IDX_8197F))
+#define BIT_GET_LOW_RATE_BD_IDX_8197F(x)                                       \
+	(((x) >> BIT_SHIFT_LOW_RATE_BD_IDX_8197F) &                            \
+	 BIT_MASK_LOW_RATE_BD_IDX_8197F)
+#define BIT_SET_LOW_RATE_BD_IDX_8197F(x, v)                                    \
+	(BIT_CLEAR_LOW_RATE_BD_IDX_8197F(x) | BIT_LOW_RATE_BD_IDX_8197F(v))
+
+/* 2 REG_LTR_CTRL2_TIMER_THRESHOLD_8197F */
+
+#define BIT_SHIFT_RX_EMPTY_TIMER_IDX_8197F 24
+#define BIT_MASK_RX_EMPTY_TIMER_IDX_8197F 0x7
+#define BIT_RX_EMPTY_TIMER_IDX_8197F(x)                                        \
+	(((x) & BIT_MASK_RX_EMPTY_TIMER_IDX_8197F)                             \
+	 << BIT_SHIFT_RX_EMPTY_TIMER_IDX_8197F)
+#define BITS_RX_EMPTY_TIMER_IDX_8197F                                          \
+	(BIT_MASK_RX_EMPTY_TIMER_IDX_8197F                                     \
+	 << BIT_SHIFT_RX_EMPTY_TIMER_IDX_8197F)
+#define BIT_CLEAR_RX_EMPTY_TIMER_IDX_8197F(x)                                  \
+	((x) & (~BITS_RX_EMPTY_TIMER_IDX_8197F))
+#define BIT_GET_RX_EMPTY_TIMER_IDX_8197F(x)                                    \
+	(((x) >> BIT_SHIFT_RX_EMPTY_TIMER_IDX_8197F) &                         \
+	 BIT_MASK_RX_EMPTY_TIMER_IDX_8197F)
+#define BIT_SET_RX_EMPTY_TIMER_IDX_8197F(x, v)                                 \
+	(BIT_CLEAR_RX_EMPTY_TIMER_IDX_8197F(x) |                               \
+	 BIT_RX_EMPTY_TIMER_IDX_8197F(v))
+
+#define BIT_SHIFT_RX_AFULL_TH_IDX_8197F 20
+#define BIT_MASK_RX_AFULL_TH_IDX_8197F 0x7
+#define BIT_RX_AFULL_TH_IDX_8197F(x)                                           \
+	(((x) & BIT_MASK_RX_AFULL_TH_IDX_8197F)                                \
+	 << BIT_SHIFT_RX_AFULL_TH_IDX_8197F)
+#define BITS_RX_AFULL_TH_IDX_8197F                                             \
+	(BIT_MASK_RX_AFULL_TH_IDX_8197F << BIT_SHIFT_RX_AFULL_TH_IDX_8197F)
+#define BIT_CLEAR_RX_AFULL_TH_IDX_8197F(x) ((x) & (~BITS_RX_AFULL_TH_IDX_8197F))
+#define BIT_GET_RX_AFULL_TH_IDX_8197F(x)                                       \
+	(((x) >> BIT_SHIFT_RX_AFULL_TH_IDX_8197F) &                            \
+	 BIT_MASK_RX_AFULL_TH_IDX_8197F)
+#define BIT_SET_RX_AFULL_TH_IDX_8197F(x, v)                                    \
+	(BIT_CLEAR_RX_AFULL_TH_IDX_8197F(x) | BIT_RX_AFULL_TH_IDX_8197F(v))
+
+#define BIT_SHIFT_RX_HIGH_TH_IDX_8197F 16
+#define BIT_MASK_RX_HIGH_TH_IDX_8197F 0x7
+#define BIT_RX_HIGH_TH_IDX_8197F(x)                                            \
+	(((x) & BIT_MASK_RX_HIGH_TH_IDX_8197F)                                 \
+	 << BIT_SHIFT_RX_HIGH_TH_IDX_8197F)
+#define BITS_RX_HIGH_TH_IDX_8197F                                              \
+	(BIT_MASK_RX_HIGH_TH_IDX_8197F << BIT_SHIFT_RX_HIGH_TH_IDX_8197F)
+#define BIT_CLEAR_RX_HIGH_TH_IDX_8197F(x) ((x) & (~BITS_RX_HIGH_TH_IDX_8197F))
+#define BIT_GET_RX_HIGH_TH_IDX_8197F(x)                                        \
+	(((x) >> BIT_SHIFT_RX_HIGH_TH_IDX_8197F) &                             \
+	 BIT_MASK_RX_HIGH_TH_IDX_8197F)
+#define BIT_SET_RX_HIGH_TH_IDX_8197F(x, v)                                     \
+	(BIT_CLEAR_RX_HIGH_TH_IDX_8197F(x) | BIT_RX_HIGH_TH_IDX_8197F(v))
+
+#define BIT_SHIFT_RX_MED_TH_IDX_8197F 12
+#define BIT_MASK_RX_MED_TH_IDX_8197F 0x7
+#define BIT_RX_MED_TH_IDX_8197F(x)                                             \
+	(((x) & BIT_MASK_RX_MED_TH_IDX_8197F) << BIT_SHIFT_RX_MED_TH_IDX_8197F)
+#define BITS_RX_MED_TH_IDX_8197F                                               \
+	(BIT_MASK_RX_MED_TH_IDX_8197F << BIT_SHIFT_RX_MED_TH_IDX_8197F)
+#define BIT_CLEAR_RX_MED_TH_IDX_8197F(x) ((x) & (~BITS_RX_MED_TH_IDX_8197F))
+#define BIT_GET_RX_MED_TH_IDX_8197F(x)                                         \
+	(((x) >> BIT_SHIFT_RX_MED_TH_IDX_8197F) & BIT_MASK_RX_MED_TH_IDX_8197F)
+#define BIT_SET_RX_MED_TH_IDX_8197F(x, v)                                      \
+	(BIT_CLEAR_RX_MED_TH_IDX_8197F(x) | BIT_RX_MED_TH_IDX_8197F(v))
+
+#define BIT_SHIFT_RX_LOW_TH_IDX_8197F 8
+#define BIT_MASK_RX_LOW_TH_IDX_8197F 0x7
+#define BIT_RX_LOW_TH_IDX_8197F(x)                                             \
+	(((x) & BIT_MASK_RX_LOW_TH_IDX_8197F) << BIT_SHIFT_RX_LOW_TH_IDX_8197F)
+#define BITS_RX_LOW_TH_IDX_8197F                                               \
+	(BIT_MASK_RX_LOW_TH_IDX_8197F << BIT_SHIFT_RX_LOW_TH_IDX_8197F)
+#define BIT_CLEAR_RX_LOW_TH_IDX_8197F(x) ((x) & (~BITS_RX_LOW_TH_IDX_8197F))
+#define BIT_GET_RX_LOW_TH_IDX_8197F(x)                                         \
+	(((x) >> BIT_SHIFT_RX_LOW_TH_IDX_8197F) & BIT_MASK_RX_LOW_TH_IDX_8197F)
+#define BIT_SET_RX_LOW_TH_IDX_8197F(x, v)                                      \
+	(BIT_CLEAR_RX_LOW_TH_IDX_8197F(x) | BIT_RX_LOW_TH_IDX_8197F(v))
+
+#define BIT_SHIFT_LTR_SPACE_IDX_8197F 4
+#define BIT_MASK_LTR_SPACE_IDX_8197F 0x3
+#define BIT_LTR_SPACE_IDX_8197F(x)                                             \
+	(((x) & BIT_MASK_LTR_SPACE_IDX_8197F) << BIT_SHIFT_LTR_SPACE_IDX_8197F)
+#define BITS_LTR_SPACE_IDX_8197F                                               \
+	(BIT_MASK_LTR_SPACE_IDX_8197F << BIT_SHIFT_LTR_SPACE_IDX_8197F)
+#define BIT_CLEAR_LTR_SPACE_IDX_8197F(x) ((x) & (~BITS_LTR_SPACE_IDX_8197F))
+#define BIT_GET_LTR_SPACE_IDX_8197F(x)                                         \
+	(((x) >> BIT_SHIFT_LTR_SPACE_IDX_8197F) & BIT_MASK_LTR_SPACE_IDX_8197F)
+#define BIT_SET_LTR_SPACE_IDX_8197F(x, v)                                      \
+	(BIT_CLEAR_LTR_SPACE_IDX_8197F(x) | BIT_LTR_SPACE_IDX_8197F(v))
+
+#define BIT_SHIFT_LTR_IDLE_TIMER_IDX_8197F 0
+#define BIT_MASK_LTR_IDLE_TIMER_IDX_8197F 0x7
+#define BIT_LTR_IDLE_TIMER_IDX_8197F(x)                                        \
+	(((x) & BIT_MASK_LTR_IDLE_TIMER_IDX_8197F)                             \
+	 << BIT_SHIFT_LTR_IDLE_TIMER_IDX_8197F)
+#define BITS_LTR_IDLE_TIMER_IDX_8197F                                          \
+	(BIT_MASK_LTR_IDLE_TIMER_IDX_8197F                                     \
+	 << BIT_SHIFT_LTR_IDLE_TIMER_IDX_8197F)
+#define BIT_CLEAR_LTR_IDLE_TIMER_IDX_8197F(x)                                  \
+	((x) & (~BITS_LTR_IDLE_TIMER_IDX_8197F))
+#define BIT_GET_LTR_IDLE_TIMER_IDX_8197F(x)                                    \
+	(((x) >> BIT_SHIFT_LTR_IDLE_TIMER_IDX_8197F) &                         \
+	 BIT_MASK_LTR_IDLE_TIMER_IDX_8197F)
+#define BIT_SET_LTR_IDLE_TIMER_IDX_8197F(x, v)                                 \
+	(BIT_CLEAR_LTR_IDLE_TIMER_IDX_8197F(x) |                               \
+	 BIT_LTR_IDLE_TIMER_IDX_8197F(v))
+
+/* 2 REG_LTR_IDLE_LATENCY_V1_8197F */
+
+#define BIT_SHIFT_LTR_IDLE_L_8197F 0
+#define BIT_MASK_LTR_IDLE_L_8197F 0xffffffffL
+#define BIT_LTR_IDLE_L_8197F(x)                                                \
+	(((x) & BIT_MASK_LTR_IDLE_L_8197F) << BIT_SHIFT_LTR_IDLE_L_8197F)
+#define BITS_LTR_IDLE_L_8197F                                                  \
+	(BIT_MASK_LTR_IDLE_L_8197F << BIT_SHIFT_LTR_IDLE_L_8197F)
+#define BIT_CLEAR_LTR_IDLE_L_8197F(x) ((x) & (~BITS_LTR_IDLE_L_8197F))
+#define BIT_GET_LTR_IDLE_L_8197F(x)                                            \
+	(((x) >> BIT_SHIFT_LTR_IDLE_L_8197F) & BIT_MASK_LTR_IDLE_L_8197F)
+#define BIT_SET_LTR_IDLE_L_8197F(x, v)                                         \
+	(BIT_CLEAR_LTR_IDLE_L_8197F(x) | BIT_LTR_IDLE_L_8197F(v))
+
+/* 2 REG_LTR_ACTIVE_LATENCY_V1_8197F */
+
+#define BIT_SHIFT_LTR_ACT_L_8197F 0
+#define BIT_MASK_LTR_ACT_L_8197F 0xffffffffL
+#define BIT_LTR_ACT_L_8197F(x)                                                 \
+	(((x) & BIT_MASK_LTR_ACT_L_8197F) << BIT_SHIFT_LTR_ACT_L_8197F)
+#define BITS_LTR_ACT_L_8197F                                                   \
+	(BIT_MASK_LTR_ACT_L_8197F << BIT_SHIFT_LTR_ACT_L_8197F)
+#define BIT_CLEAR_LTR_ACT_L_8197F(x) ((x) & (~BITS_LTR_ACT_L_8197F))
+#define BIT_GET_LTR_ACT_L_8197F(x)                                             \
+	(((x) >> BIT_SHIFT_LTR_ACT_L_8197F) & BIT_MASK_LTR_ACT_L_8197F)
+#define BIT_SET_LTR_ACT_L_8197F(x, v)                                          \
+	(BIT_CLEAR_LTR_ACT_L_8197F(x) | BIT_LTR_ACT_L_8197F(v))
+
+/* 2 REG_ANTENNA_TRAINING_CONTROL_REGISTER_8197F */
+#define BIT_APPEND_MACID_IN_RESP_EN_8197F BIT(50)
+#define BIT_ADDR2_MATCH_EN_8197F BIT(49)
+#define BIT_ANTTRN_EN_8197F BIT(48)
+
+#define BIT_SHIFT_TRAIN_STA_ADDR_8197F 0
+#define BIT_MASK_TRAIN_STA_ADDR_8197F 0xffffffffffffL
+#define BIT_TRAIN_STA_ADDR_8197F(x)                                            \
+	(((x) & BIT_MASK_TRAIN_STA_ADDR_8197F)                                 \
+	 << BIT_SHIFT_TRAIN_STA_ADDR_8197F)
+#define BITS_TRAIN_STA_ADDR_8197F                                              \
+	(BIT_MASK_TRAIN_STA_ADDR_8197F << BIT_SHIFT_TRAIN_STA_ADDR_8197F)
+#define BIT_CLEAR_TRAIN_STA_ADDR_8197F(x) ((x) & (~BITS_TRAIN_STA_ADDR_8197F))
+#define BIT_GET_TRAIN_STA_ADDR_8197F(x)                                        \
+	(((x) >> BIT_SHIFT_TRAIN_STA_ADDR_8197F) &                             \
+	 BIT_MASK_TRAIN_STA_ADDR_8197F)
+#define BIT_SET_TRAIN_STA_ADDR_8197F(x, v)                                     \
+	(BIT_CLEAR_TRAIN_STA_ADDR_8197F(x) | BIT_TRAIN_STA_ADDR_8197F(v))
+
+/* 2 REG_RSVD_0X7B4_8197F */
+
+/* 2 REG_WMAC_PKTCNT_RWD_8197F */
+
+#define BIT_SHIFT_PKTCNT_BSSIDMAP_8197F 4
+#define BIT_MASK_PKTCNT_BSSIDMAP_8197F 0xf
+#define BIT_PKTCNT_BSSIDMAP_8197F(x)                                           \
+	(((x) & BIT_MASK_PKTCNT_BSSIDMAP_8197F)                                \
+	 << BIT_SHIFT_PKTCNT_BSSIDMAP_8197F)
+#define BITS_PKTCNT_BSSIDMAP_8197F                                             \
+	(BIT_MASK_PKTCNT_BSSIDMAP_8197F << BIT_SHIFT_PKTCNT_BSSIDMAP_8197F)
+#define BIT_CLEAR_PKTCNT_BSSIDMAP_8197F(x) ((x) & (~BITS_PKTCNT_BSSIDMAP_8197F))
+#define BIT_GET_PKTCNT_BSSIDMAP_8197F(x)                                       \
+	(((x) >> BIT_SHIFT_PKTCNT_BSSIDMAP_8197F) &                            \
+	 BIT_MASK_PKTCNT_BSSIDMAP_8197F)
+#define BIT_SET_PKTCNT_BSSIDMAP_8197F(x, v)                                    \
+	(BIT_CLEAR_PKTCNT_BSSIDMAP_8197F(x) | BIT_PKTCNT_BSSIDMAP_8197F(v))
+
+#define BIT_PKTCNT_CNTRST_8197F BIT(1)
+#define BIT_PKTCNT_CNTEN_8197F BIT(0)
+
+/* 2 REG_WMAC_PKTCNT_CTRL_8197F */
+#define BIT_WMAC_PKTCNT_TRST_8197F BIT(9)
+#define BIT_WMAC_PKTCNT_FEN_8197F BIT(8)
+
+#define BIT_SHIFT_WMAC_PKTCNT_CFGAD_8197F 0
+#define BIT_MASK_WMAC_PKTCNT_CFGAD_8197F 0xff
+#define BIT_WMAC_PKTCNT_CFGAD_8197F(x)                                         \
+	(((x) & BIT_MASK_WMAC_PKTCNT_CFGAD_8197F)                              \
+	 << BIT_SHIFT_WMAC_PKTCNT_CFGAD_8197F)
+#define BITS_WMAC_PKTCNT_CFGAD_8197F                                           \
+	(BIT_MASK_WMAC_PKTCNT_CFGAD_8197F << BIT_SHIFT_WMAC_PKTCNT_CFGAD_8197F)
+#define BIT_CLEAR_WMAC_PKTCNT_CFGAD_8197F(x)                                   \
+	((x) & (~BITS_WMAC_PKTCNT_CFGAD_8197F))
+#define BIT_GET_WMAC_PKTCNT_CFGAD_8197F(x)                                     \
+	(((x) >> BIT_SHIFT_WMAC_PKTCNT_CFGAD_8197F) &                          \
+	 BIT_MASK_WMAC_PKTCNT_CFGAD_8197F)
+#define BIT_SET_WMAC_PKTCNT_CFGAD_8197F(x, v)                                  \
+	(BIT_CLEAR_WMAC_PKTCNT_CFGAD_8197F(x) | BIT_WMAC_PKTCNT_CFGAD_8197F(v))
+
+/* 2 REG_IQ_DUMP_8197F */
+
+#define BIT_SHIFT_R_WMAC_MATCH_REF_MAC_8197F (64 & CPU_OPT_WIDTH)
+#define BIT_MASK_R_WMAC_MATCH_REF_MAC_8197F 0xffffffffL
+#define BIT_R_WMAC_MATCH_REF_MAC_8197F(x)                                      \
+	(((x) & BIT_MASK_R_WMAC_MATCH_REF_MAC_8197F)                           \
+	 << BIT_SHIFT_R_WMAC_MATCH_REF_MAC_8197F)
+#define BITS_R_WMAC_MATCH_REF_MAC_8197F                                        \
+	(BIT_MASK_R_WMAC_MATCH_REF_MAC_8197F                                   \
+	 << BIT_SHIFT_R_WMAC_MATCH_REF_MAC_8197F)
+#define BIT_CLEAR_R_WMAC_MATCH_REF_MAC_8197F(x)                                \
+	((x) & (~BITS_R_WMAC_MATCH_REF_MAC_8197F))
+#define BIT_GET_R_WMAC_MATCH_REF_MAC_8197F(x)                                  \
+	(((x) >> BIT_SHIFT_R_WMAC_MATCH_REF_MAC_8197F) &                       \
+	 BIT_MASK_R_WMAC_MATCH_REF_MAC_8197F)
+#define BIT_SET_R_WMAC_MATCH_REF_MAC_8197F(x, v)                               \
+	(BIT_CLEAR_R_WMAC_MATCH_REF_MAC_8197F(x) |                             \
+	 BIT_R_WMAC_MATCH_REF_MAC_8197F(v))
+
+#define BIT_SHIFT_R_WMAC_MASK_LA_MAC_8197F (32 & CPU_OPT_WIDTH)
+#define BIT_MASK_R_WMAC_MASK_LA_MAC_8197F 0xffffffffL
+#define BIT_R_WMAC_MASK_LA_MAC_8197F(x)                                        \
+	(((x) & BIT_MASK_R_WMAC_MASK_LA_MAC_8197F)                             \
+	 << BIT_SHIFT_R_WMAC_MASK_LA_MAC_8197F)
+#define BITS_R_WMAC_MASK_LA_MAC_8197F                                          \
+	(BIT_MASK_R_WMAC_MASK_LA_MAC_8197F                                     \
+	 << BIT_SHIFT_R_WMAC_MASK_LA_MAC_8197F)
+#define BIT_CLEAR_R_WMAC_MASK_LA_MAC_8197F(x)                                  \
+	((x) & (~BITS_R_WMAC_MASK_LA_MAC_8197F))
+#define BIT_GET_R_WMAC_MASK_LA_MAC_8197F(x)                                    \
+	(((x) >> BIT_SHIFT_R_WMAC_MASK_LA_MAC_8197F) &                         \
+	 BIT_MASK_R_WMAC_MASK_LA_MAC_8197F)
+#define BIT_SET_R_WMAC_MASK_LA_MAC_8197F(x, v)                                 \
+	(BIT_CLEAR_R_WMAC_MASK_LA_MAC_8197F(x) |                               \
+	 BIT_R_WMAC_MASK_LA_MAC_8197F(v))
+
+#define BIT_SHIFT_DUMP_OK_ADDR_8197F 16
+#define BIT_MASK_DUMP_OK_ADDR_8197F 0xffff
+#define BIT_DUMP_OK_ADDR_8197F(x)                                              \
+	(((x) & BIT_MASK_DUMP_OK_ADDR_8197F) << BIT_SHIFT_DUMP_OK_ADDR_8197F)
+#define BITS_DUMP_OK_ADDR_8197F                                                \
+	(BIT_MASK_DUMP_OK_ADDR_8197F << BIT_SHIFT_DUMP_OK_ADDR_8197F)
+#define BIT_CLEAR_DUMP_OK_ADDR_8197F(x) ((x) & (~BITS_DUMP_OK_ADDR_8197F))
+#define BIT_GET_DUMP_OK_ADDR_8197F(x)                                          \
+	(((x) >> BIT_SHIFT_DUMP_OK_ADDR_8197F) & BIT_MASK_DUMP_OK_ADDR_8197F)
+#define BIT_SET_DUMP_OK_ADDR_8197F(x, v)                                       \
+	(BIT_CLEAR_DUMP_OK_ADDR_8197F(x) | BIT_DUMP_OK_ADDR_8197F(v))
+
+#define BIT_SHIFT_R_TRIG_TIME_SEL_8197F 8
+#define BIT_MASK_R_TRIG_TIME_SEL_8197F 0x7f
+#define BIT_R_TRIG_TIME_SEL_8197F(x)                                           \
+	(((x) & BIT_MASK_R_TRIG_TIME_SEL_8197F)                                \
+	 << BIT_SHIFT_R_TRIG_TIME_SEL_8197F)
+#define BITS_R_TRIG_TIME_SEL_8197F                                             \
+	(BIT_MASK_R_TRIG_TIME_SEL_8197F << BIT_SHIFT_R_TRIG_TIME_SEL_8197F)
+#define BIT_CLEAR_R_TRIG_TIME_SEL_8197F(x) ((x) & (~BITS_R_TRIG_TIME_SEL_8197F))
+#define BIT_GET_R_TRIG_TIME_SEL_8197F(x)                                       \
+	(((x) >> BIT_SHIFT_R_TRIG_TIME_SEL_8197F) &                            \
+	 BIT_MASK_R_TRIG_TIME_SEL_8197F)
+#define BIT_SET_R_TRIG_TIME_SEL_8197F(x, v)                                    \
+	(BIT_CLEAR_R_TRIG_TIME_SEL_8197F(x) | BIT_R_TRIG_TIME_SEL_8197F(v))
+
+#define BIT_SHIFT_R_MAC_TRIG_SEL_8197F 6
+#define BIT_MASK_R_MAC_TRIG_SEL_8197F 0x3
+#define BIT_R_MAC_TRIG_SEL_8197F(x)                                            \
+	(((x) & BIT_MASK_R_MAC_TRIG_SEL_8197F)                                 \
+	 << BIT_SHIFT_R_MAC_TRIG_SEL_8197F)
+#define BITS_R_MAC_TRIG_SEL_8197F                                              \
+	(BIT_MASK_R_MAC_TRIG_SEL_8197F << BIT_SHIFT_R_MAC_TRIG_SEL_8197F)
+#define BIT_CLEAR_R_MAC_TRIG_SEL_8197F(x) ((x) & (~BITS_R_MAC_TRIG_SEL_8197F))
+#define BIT_GET_R_MAC_TRIG_SEL_8197F(x)                                        \
+	(((x) >> BIT_SHIFT_R_MAC_TRIG_SEL_8197F) &                             \
+	 BIT_MASK_R_MAC_TRIG_SEL_8197F)
+#define BIT_SET_R_MAC_TRIG_SEL_8197F(x, v)                                     \
+	(BIT_CLEAR_R_MAC_TRIG_SEL_8197F(x) | BIT_R_MAC_TRIG_SEL_8197F(v))
+
+#define BIT_MAC_TRIG_REG_8197F BIT(5)
+
+#define BIT_SHIFT_R_LEVEL_PULSE_SEL_8197F 3
+#define BIT_MASK_R_LEVEL_PULSE_SEL_8197F 0x3
+#define BIT_R_LEVEL_PULSE_SEL_8197F(x)                                         \
+	(((x) & BIT_MASK_R_LEVEL_PULSE_SEL_8197F)                              \
+	 << BIT_SHIFT_R_LEVEL_PULSE_SEL_8197F)
+#define BITS_R_LEVEL_PULSE_SEL_8197F                                           \
+	(BIT_MASK_R_LEVEL_PULSE_SEL_8197F << BIT_SHIFT_R_LEVEL_PULSE_SEL_8197F)
+#define BIT_CLEAR_R_LEVEL_PULSE_SEL_8197F(x)                                   \
+	((x) & (~BITS_R_LEVEL_PULSE_SEL_8197F))
+#define BIT_GET_R_LEVEL_PULSE_SEL_8197F(x)                                     \
+	(((x) >> BIT_SHIFT_R_LEVEL_PULSE_SEL_8197F) &                          \
+	 BIT_MASK_R_LEVEL_PULSE_SEL_8197F)
+#define BIT_SET_R_LEVEL_PULSE_SEL_8197F(x, v)                                  \
+	(BIT_CLEAR_R_LEVEL_PULSE_SEL_8197F(x) | BIT_R_LEVEL_PULSE_SEL_8197F(v))
+
+#define BIT_EN_LA_MAC_8197F BIT(2)
+#define BIT_R_EN_IQDUMP_8197F BIT(1)
+#define BIT_R_IQDATA_DUMP_8197F BIT(0)
+
+/* 2 REG_WMAC_FTM_CTL_8197F */
+#define BIT_RXFTM_TXACK_SC_8197F BIT(6)
+#define BIT_RXFTM_TXACK_BW_8197F BIT(5)
+#define BIT_RXFTM_EN_8197F BIT(3)
+#define BIT_RXFTMREQ_BYDRV_8197F BIT(2)
+#define BIT_RXFTMREQ_EN_8197F BIT(1)
+#define BIT_FTM_EN_8197F BIT(0)
+
+/* 2 REG_IQ_DUMP_EXT_8197F */
+
+#define BIT_SHIFT_R_TIME_UNIT_SEL_8197F 0
+#define BIT_MASK_R_TIME_UNIT_SEL_8197F 0x7
+#define BIT_R_TIME_UNIT_SEL_8197F(x)                                           \
+	(((x) & BIT_MASK_R_TIME_UNIT_SEL_8197F)                                \
+	 << BIT_SHIFT_R_TIME_UNIT_SEL_8197F)
+#define BITS_R_TIME_UNIT_SEL_8197F                                             \
+	(BIT_MASK_R_TIME_UNIT_SEL_8197F << BIT_SHIFT_R_TIME_UNIT_SEL_8197F)
+#define BIT_CLEAR_R_TIME_UNIT_SEL_8197F(x) ((x) & (~BITS_R_TIME_UNIT_SEL_8197F))
+#define BIT_GET_R_TIME_UNIT_SEL_8197F(x)                                       \
+	(((x) >> BIT_SHIFT_R_TIME_UNIT_SEL_8197F) &                            \
+	 BIT_MASK_R_TIME_UNIT_SEL_8197F)
+#define BIT_SET_R_TIME_UNIT_SEL_8197F(x, v)                                    \
+	(BIT_CLEAR_R_TIME_UNIT_SEL_8197F(x) | BIT_R_TIME_UNIT_SEL_8197F(v))
+
+/* 2 REG_OFDM_CCK_LEN_MASK_8197F */
+
+#define BIT_SHIFT_R_WMAC_RX_FIL_LEN_8197F (64 & CPU_OPT_WIDTH)
+#define BIT_MASK_R_WMAC_RX_FIL_LEN_8197F 0xffff
+#define BIT_R_WMAC_RX_FIL_LEN_8197F(x)                                         \
+	(((x) & BIT_MASK_R_WMAC_RX_FIL_LEN_8197F)                              \
+	 << BIT_SHIFT_R_WMAC_RX_FIL_LEN_8197F)
+#define BITS_R_WMAC_RX_FIL_LEN_8197F                                           \
+	(BIT_MASK_R_WMAC_RX_FIL_LEN_8197F << BIT_SHIFT_R_WMAC_RX_FIL_LEN_8197F)
+#define BIT_CLEAR_R_WMAC_RX_FIL_LEN_8197F(x)                                   \
+	((x) & (~BITS_R_WMAC_RX_FIL_LEN_8197F))
+#define BIT_GET_R_WMAC_RX_FIL_LEN_8197F(x)                                     \
+	(((x) >> BIT_SHIFT_R_WMAC_RX_FIL_LEN_8197F) &                          \
+	 BIT_MASK_R_WMAC_RX_FIL_LEN_8197F)
+#define BIT_SET_R_WMAC_RX_FIL_LEN_8197F(x, v)                                  \
+	(BIT_CLEAR_R_WMAC_RX_FIL_LEN_8197F(x) | BIT_R_WMAC_RX_FIL_LEN_8197F(v))
+
+#define BIT_SHIFT_R_WMAC_RXFIFO_FULL_TH_8197F (56 & CPU_OPT_WIDTH)
+#define BIT_MASK_R_WMAC_RXFIFO_FULL_TH_8197F 0xff
+#define BIT_R_WMAC_RXFIFO_FULL_TH_8197F(x)                                     \
+	(((x) & BIT_MASK_R_WMAC_RXFIFO_FULL_TH_8197F)                          \
+	 << BIT_SHIFT_R_WMAC_RXFIFO_FULL_TH_8197F)
+#define BITS_R_WMAC_RXFIFO_FULL_TH_8197F                                       \
+	(BIT_MASK_R_WMAC_RXFIFO_FULL_TH_8197F                                  \
+	 << BIT_SHIFT_R_WMAC_RXFIFO_FULL_TH_8197F)
+#define BIT_CLEAR_R_WMAC_RXFIFO_FULL_TH_8197F(x)                               \
+	((x) & (~BITS_R_WMAC_RXFIFO_FULL_TH_8197F))
+#define BIT_GET_R_WMAC_RXFIFO_FULL_TH_8197F(x)                                 \
+	(((x) >> BIT_SHIFT_R_WMAC_RXFIFO_FULL_TH_8197F) &                      \
+	 BIT_MASK_R_WMAC_RXFIFO_FULL_TH_8197F)
+#define BIT_SET_R_WMAC_RXFIFO_FULL_TH_8197F(x, v)                              \
+	(BIT_CLEAR_R_WMAC_RXFIFO_FULL_TH_8197F(x) |                            \
+	 BIT_R_WMAC_RXFIFO_FULL_TH_8197F(v))
+
+#define BIT_R_WMAC_RX_SYNCFIFO_SYNC_8197F BIT(55)
+#define BIT_R_WMAC_RXRST_DLY_8197F BIT(54)
+#define BIT_R_WMAC_SRCH_TXRPT_REF_DROP_8197F BIT(53)
+#define BIT_R_WMAC_SRCH_TXRPT_UA1_8197F BIT(52)
+#define BIT_R_WMAC_SRCH_TXRPT_TYPE_8197F BIT(51)
+#define BIT_R_WMAC_NDP_RST_8197F BIT(50)
+#define BIT_R_WMAC_POWINT_EN_8197F BIT(49)
+#define BIT_R_WMAC_SRCH_TXRPT_PERPKT_8197F BIT(48)
+#define BIT_R_WMAC_SRCH_TXRPT_MID_8197F BIT(47)
+#define BIT_R_WMAC_PFIN_TOEN_8197F BIT(46)
+#define BIT_R_WMAC_FIL_SECERR_8197F BIT(45)
+#define BIT_R_WMAC_FIL_CTLPKTLEN_8197F BIT(44)
+#define BIT_R_WMAC_FIL_FCTYPE_8197F BIT(43)
+#define BIT_R_WMAC_FIL_FCPROVER_8197F BIT(42)
+#define BIT_R_WMAC_PHYSTS_SNIF_8197F BIT(41)
+#define BIT_R_WMAC_PHYSTS_PLCP_8197F BIT(40)
+#define BIT_R_MAC_TCR_VBONF_RD_8197F BIT(39)
+#define BIT_R_WMAC_TCR_MPAR_NDP_8197F BIT(38)
+#define BIT_R_WMAC_NDP_FILTER_8197F BIT(37)
+#define BIT_R_WMAC_RXLEN_SEL_8197F BIT(36)
+#define BIT_R_WMAC_RXLEN_SEL1_8197F BIT(35)
+#define BIT_R_OFDM_FILTER_8197F BIT(34)
+#define BIT_R_WMAC_CHK_OFDM_LEN_8197F BIT(33)
+#define BIT_R_WMAC_CHK_CCK_LEN_8197F BIT(32)
+
+#define BIT_SHIFT_R_OFDM_LEN_8197F 26
+#define BIT_MASK_R_OFDM_LEN_8197F 0x3f
+#define BIT_R_OFDM_LEN_8197F(x)                                                \
+	(((x) & BIT_MASK_R_OFDM_LEN_8197F) << BIT_SHIFT_R_OFDM_LEN_8197F)
+#define BITS_R_OFDM_LEN_8197F                                                  \
+	(BIT_MASK_R_OFDM_LEN_8197F << BIT_SHIFT_R_OFDM_LEN_8197F)
+#define BIT_CLEAR_R_OFDM_LEN_8197F(x) ((x) & (~BITS_R_OFDM_LEN_8197F))
+#define BIT_GET_R_OFDM_LEN_8197F(x)                                            \
+	(((x) >> BIT_SHIFT_R_OFDM_LEN_8197F) & BIT_MASK_R_OFDM_LEN_8197F)
+#define BIT_SET_R_OFDM_LEN_8197F(x, v)                                         \
+	(BIT_CLEAR_R_OFDM_LEN_8197F(x) | BIT_R_OFDM_LEN_8197F(v))
+
+#define BIT_SHIFT_R_CCK_LEN_8197F 0
+#define BIT_MASK_R_CCK_LEN_8197F 0xffff
+#define BIT_R_CCK_LEN_8197F(x)                                                 \
+	(((x) & BIT_MASK_R_CCK_LEN_8197F) << BIT_SHIFT_R_CCK_LEN_8197F)
+#define BITS_R_CCK_LEN_8197F                                                   \
+	(BIT_MASK_R_CCK_LEN_8197F << BIT_SHIFT_R_CCK_LEN_8197F)
+#define BIT_CLEAR_R_CCK_LEN_8197F(x) ((x) & (~BITS_R_CCK_LEN_8197F))
+#define BIT_GET_R_CCK_LEN_8197F(x)                                             \
+	(((x) >> BIT_SHIFT_R_CCK_LEN_8197F) & BIT_MASK_R_CCK_LEN_8197F)
+#define BIT_SET_R_CCK_LEN_8197F(x, v)                                          \
+	(BIT_CLEAR_R_CCK_LEN_8197F(x) | BIT_R_CCK_LEN_8197F(v))
+
+/* 2 REG_RX_FILTER_FUNCTION_8197F */
+#define BIT_R_WMAC_RXHANG_EN_8197F BIT(15)
+#define BIT_R_WMAC_MHRDDY_LATCH_8197F BIT(14)
+#define BIT_R_MHRDDY_CLR_8197F BIT(13)
+#define BIT_R_RXPKTCTL_FSM_BASED_MPDURDY1_8197F BIT(12)
+#define BIT_R_WMAC_DIS_VHT_PLCP_CHK_MU_8197F BIT(11)
+#define BIT_R_CHK_DELIMIT_LEN_8197F BIT(10)
+#define BIT_R_REAPTER_ADDR_MATCH_8197F BIT(9)
+#define BIT_R_RXPKTCTL_FSM_BASED_MPDURDY_8197F BIT(8)
+#define BIT_R_LATCH_MACHRDY_8197F BIT(7)
+#define BIT_R_WMAC_RXFIL_REND_8197F BIT(6)
+#define BIT_R_WMAC_MPDURDY_CLR_8197F BIT(5)
+#define BIT_R_WMAC_CLRRXSEC_8197F BIT(4)
+#define BIT_R_WMAC_RXFIL_RDEL_8197F BIT(3)
+#define BIT_R_WMAC_RXFIL_FCSE_8197F BIT(2)
+#define BIT_R_WMAC_RXFIL_MESH_DEL_8197F BIT(1)
+#define BIT_R_WMAC_RXFIL_MASKM_8197F BIT(0)
+
+/* 2 REG_NDP_SIG_8197F */
+
+#define BIT_SHIFT_R_WMAC_TXNDP_SIGB_8197F 0
+#define BIT_MASK_R_WMAC_TXNDP_SIGB_8197F 0x1fffff
+#define BIT_R_WMAC_TXNDP_SIGB_8197F(x)                                         \
+	(((x) & BIT_MASK_R_WMAC_TXNDP_SIGB_8197F)                              \
+	 << BIT_SHIFT_R_WMAC_TXNDP_SIGB_8197F)
+#define BITS_R_WMAC_TXNDP_SIGB_8197F                                           \
+	(BIT_MASK_R_WMAC_TXNDP_SIGB_8197F << BIT_SHIFT_R_WMAC_TXNDP_SIGB_8197F)
+#define BIT_CLEAR_R_WMAC_TXNDP_SIGB_8197F(x)                                   \
+	((x) & (~BITS_R_WMAC_TXNDP_SIGB_8197F))
+#define BIT_GET_R_WMAC_TXNDP_SIGB_8197F(x)                                     \
+	(((x) >> BIT_SHIFT_R_WMAC_TXNDP_SIGB_8197F) &                          \
+	 BIT_MASK_R_WMAC_TXNDP_SIGB_8197F)
+#define BIT_SET_R_WMAC_TXNDP_SIGB_8197F(x, v)                                  \
+	(BIT_CLEAR_R_WMAC_TXNDP_SIGB_8197F(x) | BIT_R_WMAC_TXNDP_SIGB_8197F(v))
+
+/* 2 REG_TXCMD_INFO_FOR_RSP_PKT_8197F */
+
+#define BIT_SHIFT_R_MAC_DEBUG_8197F (32 & CPU_OPT_WIDTH)
+#define BIT_MASK_R_MAC_DEBUG_8197F 0xffffffffL
+#define BIT_R_MAC_DEBUG_8197F(x)                                               \
+	(((x) & BIT_MASK_R_MAC_DEBUG_8197F) << BIT_SHIFT_R_MAC_DEBUG_8197F)
+#define BITS_R_MAC_DEBUG_8197F                                                 \
+	(BIT_MASK_R_MAC_DEBUG_8197F << BIT_SHIFT_R_MAC_DEBUG_8197F)
+#define BIT_CLEAR_R_MAC_DEBUG_8197F(x) ((x) & (~BITS_R_MAC_DEBUG_8197F))
+#define BIT_GET_R_MAC_DEBUG_8197F(x)                                           \
+	(((x) >> BIT_SHIFT_R_MAC_DEBUG_8197F) & BIT_MASK_R_MAC_DEBUG_8197F)
+#define BIT_SET_R_MAC_DEBUG_8197F(x, v)                                        \
+	(BIT_CLEAR_R_MAC_DEBUG_8197F(x) | BIT_R_MAC_DEBUG_8197F(v))
+
+#define BIT_SHIFT_R_MAC_DBG_SHIFT_8197F 8
+#define BIT_MASK_R_MAC_DBG_SHIFT_8197F 0x7
+#define BIT_R_MAC_DBG_SHIFT_8197F(x)                                           \
+	(((x) & BIT_MASK_R_MAC_DBG_SHIFT_8197F)                                \
+	 << BIT_SHIFT_R_MAC_DBG_SHIFT_8197F)
+#define BITS_R_MAC_DBG_SHIFT_8197F                                             \
+	(BIT_MASK_R_MAC_DBG_SHIFT_8197F << BIT_SHIFT_R_MAC_DBG_SHIFT_8197F)
+#define BIT_CLEAR_R_MAC_DBG_SHIFT_8197F(x) ((x) & (~BITS_R_MAC_DBG_SHIFT_8197F))
+#define BIT_GET_R_MAC_DBG_SHIFT_8197F(x)                                       \
+	(((x) >> BIT_SHIFT_R_MAC_DBG_SHIFT_8197F) &                            \
+	 BIT_MASK_R_MAC_DBG_SHIFT_8197F)
+#define BIT_SET_R_MAC_DBG_SHIFT_8197F(x, v)                                    \
+	(BIT_CLEAR_R_MAC_DBG_SHIFT_8197F(x) | BIT_R_MAC_DBG_SHIFT_8197F(v))
+
+#define BIT_SHIFT_R_MAC_DBG_SEL_8197F 0
+#define BIT_MASK_R_MAC_DBG_SEL_8197F 0x3
+#define BIT_R_MAC_DBG_SEL_8197F(x)                                             \
+	(((x) & BIT_MASK_R_MAC_DBG_SEL_8197F) << BIT_SHIFT_R_MAC_DBG_SEL_8197F)
+#define BITS_R_MAC_DBG_SEL_8197F                                               \
+	(BIT_MASK_R_MAC_DBG_SEL_8197F << BIT_SHIFT_R_MAC_DBG_SEL_8197F)
+#define BIT_CLEAR_R_MAC_DBG_SEL_8197F(x) ((x) & (~BITS_R_MAC_DBG_SEL_8197F))
+#define BIT_GET_R_MAC_DBG_SEL_8197F(x)                                         \
+	(((x) >> BIT_SHIFT_R_MAC_DBG_SEL_8197F) & BIT_MASK_R_MAC_DBG_SEL_8197F)
+#define BIT_SET_R_MAC_DBG_SEL_8197F(x, v)                                      \
+	(BIT_CLEAR_R_MAC_DBG_SEL_8197F(x) | BIT_R_MAC_DBG_SEL_8197F(v))
+
+/* 2 REG_SEC_OPT_V2_8197F */
+#define BIT_MASK_IV_8197F BIT(18)
+#define BIT_EIVL_ENDIAN_8197F BIT(17)
+#define BIT_EIVH_ENDIAN_8197F BIT(16)
+
+#define BIT_SHIFT_BT_TIME_CNT_8197F 0
+#define BIT_MASK_BT_TIME_CNT_8197F 0xff
+#define BIT_BT_TIME_CNT_8197F(x)                                               \
+	(((x) & BIT_MASK_BT_TIME_CNT_8197F) << BIT_SHIFT_BT_TIME_CNT_8197F)
+#define BITS_BT_TIME_CNT_8197F                                                 \
+	(BIT_MASK_BT_TIME_CNT_8197F << BIT_SHIFT_BT_TIME_CNT_8197F)
+#define BIT_CLEAR_BT_TIME_CNT_8197F(x) ((x) & (~BITS_BT_TIME_CNT_8197F))
+#define BIT_GET_BT_TIME_CNT_8197F(x)                                           \
+	(((x) >> BIT_SHIFT_BT_TIME_CNT_8197F) & BIT_MASK_BT_TIME_CNT_8197F)
+#define BIT_SET_BT_TIME_CNT_8197F(x, v)                                        \
+	(BIT_CLEAR_BT_TIME_CNT_8197F(x) | BIT_BT_TIME_CNT_8197F(v))
+
+/* 2 REG_RTS_ADDRESS_0_8197F */
+
+/* 2 REG_RTS_ADDRESS_1_8197F */
+
+#endif
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/halmac/halmac_bit_8814b.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/halmac/halmac_bit_8814b.h
--- linux-5.6.3/3rdparty/rtl8821ce/hal/halmac/halmac_bit_8814b.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/halmac/halmac_bit_8814b.h	2020-04-10 16:35:06.803659461 +0300
@@ -0,0 +1,26515 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ ******************************************************************************/
+
+#ifndef __INC_HALMAC_BIT_8814B_H
+#define __INC_HALMAC_BIT_8814B_H
+
+#define CPU_OPT_WIDTH 0x1F
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_SYS_ISO_CTRL_8814B */
+#define BIT_PWC_EV12V_8814B BIT(15)
+
+/* 2 REG_NOT_VALID_8814B */
+#define BIT_PA33V_EN_8814B BIT(13)
+#define BIT_PA12V_EN_8814B BIT(12)
+#define BIT_UA33V_EN_8814B BIT(11)
+#define BIT_UA12V_EN_8814B BIT(10)
+#define BIT_ISO_RFDIO_8814B BIT(9)
+#define BIT_ISO_EB2CORE_8814B BIT(8)
+#define BIT_ISO_DIOE_8814B BIT(7)
+#define BIT_ISO_WLPON2PP_8814B BIT(6)
+#define BIT_ISO_IP2MAC_WA2PP_8814B BIT(5)
+#define BIT_ISO_PD2CORE_8814B BIT(4)
+#define BIT_ISO_PA2PCIE_8814B BIT(3)
+#define BIT_ISO_UD2CORE_8814B BIT(2)
+#define BIT_ISO_UA2USB_8814B BIT(1)
+#define BIT_ISO_WD2PP_8814B BIT(0)
+
+/* 2 REG_SYS_FUNC_EN_8814B */
+#define BIT_FEN_MREGEN_8814B BIT(15)
+#define BIT_FEN_HWPDN_8814B BIT(14)
+
+/* 2 REG_NOT_VALID_8814B */
+#define BIT_FEN_ELDR_8814B BIT(12)
+#define BIT_FEN_DCORE_8814B BIT(11)
+#define BIT_FEN_CPUEN_8814B BIT(10)
+#define BIT_FEN_DIOE_8814B BIT(9)
+#define BIT_FEN_PCIED_8814B BIT(8)
+#define BIT_FEN_PPLL_8814B BIT(7)
+#define BIT_FEN_PCIEA_8814B BIT(6)
+#define BIT_FEN_DIO_PCIE_8814B BIT(5)
+#define BIT_FEN_USBD_8814B BIT(4)
+#define BIT_FEN_UPLL_8814B BIT(3)
+#define BIT_FEN_USBA_8814B BIT(2)
+#define BIT_FEN_BB_GLB_RSTN_8814B BIT(1)
+#define BIT_FEN_BBRSTB_8814B BIT(0)
+
+/* 2 REG_SYS_PW_CTRL_8814B */
+#define BIT_SOP_EABM_8814B BIT(31)
+#define BIT_SOP_ACKF_8814B BIT(30)
+#define BIT_SOP_ERCK_8814B BIT(29)
+#define BIT_SOP_ESWR_8814B BIT(28)
+#define BIT_SOP_PWMM_8814B BIT(27)
+#define BIT_SOP_EECK_8814B BIT(26)
+#define BIT_SOP_EXTL_8814B BIT(24)
+#define BIT_SYM_OP_RING_12M_8814B BIT(22)
+#define BIT_ROP_SWPR_8814B BIT(21)
+#define BIT_DIS_HW_LPLDM_8814B BIT(20)
+#define BIT_OPT_SWRST_WLMCU_8814B BIT(19)
+#define BIT_RDY_SYSPWR_8814B BIT(17)
+#define BIT_EN_WLON_8814B BIT(16)
+#define BIT_APDM_HPDN_8814B BIT(15)
+#define BIT_AFSM_PCIE_SUS_EN_8814B BIT(12)
+#define BIT_AFSM_WLSUS_EN_8814B BIT(11)
+#define BIT_APFM_SWLPS_8814B BIT(10)
+#define BIT_APFM_OFFMAC_8814B BIT(9)
+#define BIT_APFN_ONMAC_8814B BIT(8)
+#define BIT_CHIP_PDN_EN_8814B BIT(7)
+#define BIT_RDY_MACDIS_8814B BIT(6)
+
+/* 2 REG_NOT_VALID_8814B */
+#define BIT_PFM_WOWL_8814B BIT(3)
+#define BIT_PFM_LDKP_8814B BIT(2)
+#define BIT_WL_HCI_ALD_8814B BIT(1)
+#define BIT_PFM_LDALL_8814B BIT(0)
+
+/* 2 REG_SYS_CLK_CTRL_8814B */
+#define BIT_DATA_CPU_CLK_EN_8814B BIT(15)
+#define BIT_CPU_CLK_EN_8814B BIT(14)
+#define BIT_SYMREG_CLK_EN_8814B BIT(13)
+#define BIT_HCI_CLK_EN_8814B BIT(12)
+#define BIT_MAC_CLK_EN_8814B BIT(11)
+#define BIT_SEC_CLK_EN_8814B BIT(10)
+#define BIT_PHY_SSC_RSTB_8814B BIT(9)
+#define BIT_EXT_32K_EN_8814B BIT(8)
+#define BIT_WL_CLK_TEST_8814B BIT(7)
+#define BIT_OP_SPS_PWM_EN_8814B BIT(6)
+#define BIT_LOADER_CLK_EN_8814B BIT(5)
+#define BIT_MACSLP_8814B BIT(4)
+#define BIT_WAKEPAD_EN_8814B BIT(3)
+#define BIT_ROMD16V_EN_8814B BIT(2)
+
+/* 2 REG_NOT_VALID_8814B */
+#define BIT_CNTD16V_EN_8814B BIT(0)
+
+/* 2 REG_SYS_EEPROM_CTRL_8814B */
+
+#define BIT_SHIFT_VPDIDX_8814B 8
+#define BIT_MASK_VPDIDX_8814B 0xff
+#define BIT_VPDIDX_8814B(x)                                                    \
+	(((x) & BIT_MASK_VPDIDX_8814B) << BIT_SHIFT_VPDIDX_8814B)
+#define BITS_VPDIDX_8814B (BIT_MASK_VPDIDX_8814B << BIT_SHIFT_VPDIDX_8814B)
+#define BIT_CLEAR_VPDIDX_8814B(x) ((x) & (~BITS_VPDIDX_8814B))
+#define BIT_GET_VPDIDX_8814B(x)                                                \
+	(((x) >> BIT_SHIFT_VPDIDX_8814B) & BIT_MASK_VPDIDX_8814B)
+#define BIT_SET_VPDIDX_8814B(x, v)                                             \
+	(BIT_CLEAR_VPDIDX_8814B(x) | BIT_VPDIDX_8814B(v))
+
+#define BIT_SHIFT_EEM1_0_8814B 6
+#define BIT_MASK_EEM1_0_8814B 0x3
+#define BIT_EEM1_0_8814B(x)                                                    \
+	(((x) & BIT_MASK_EEM1_0_8814B) << BIT_SHIFT_EEM1_0_8814B)
+#define BITS_EEM1_0_8814B (BIT_MASK_EEM1_0_8814B << BIT_SHIFT_EEM1_0_8814B)
+#define BIT_CLEAR_EEM1_0_8814B(x) ((x) & (~BITS_EEM1_0_8814B))
+#define BIT_GET_EEM1_0_8814B(x)                                                \
+	(((x) >> BIT_SHIFT_EEM1_0_8814B) & BIT_MASK_EEM1_0_8814B)
+#define BIT_SET_EEM1_0_8814B(x, v)                                             \
+	(BIT_CLEAR_EEM1_0_8814B(x) | BIT_EEM1_0_8814B(v))
+
+#define BIT_AUTOLOAD_SUS_8814B BIT(5)
+#define BIT_EERPOMSEL_8814B BIT(4)
+#define BIT_EECS_V1_8814B BIT(3)
+#define BIT_EESK_V1_8814B BIT(2)
+#define BIT_EEDI_V1_8814B BIT(1)
+#define BIT_EEDO_V1_8814B BIT(0)
+
+/* 2 REG_EE_VPD_8814B */
+
+#define BIT_SHIFT_VPD_DATA_8814B 0
+#define BIT_MASK_VPD_DATA_8814B 0xffffffffL
+#define BIT_VPD_DATA_8814B(x)                                                  \
+	(((x) & BIT_MASK_VPD_DATA_8814B) << BIT_SHIFT_VPD_DATA_8814B)
+#define BITS_VPD_DATA_8814B                                                    \
+	(BIT_MASK_VPD_DATA_8814B << BIT_SHIFT_VPD_DATA_8814B)
+#define BIT_CLEAR_VPD_DATA_8814B(x) ((x) & (~BITS_VPD_DATA_8814B))
+#define BIT_GET_VPD_DATA_8814B(x)                                              \
+	(((x) >> BIT_SHIFT_VPD_DATA_8814B) & BIT_MASK_VPD_DATA_8814B)
+#define BIT_SET_VPD_DATA_8814B(x, v)                                           \
+	(BIT_CLEAR_VPD_DATA_8814B(x) | BIT_VPD_DATA_8814B(v))
+
+/* 2 REG_SYS_SWR_CTRL1_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+#define BIT_CTRL_SPS_PWM_FREQ_8814B BIT(10)
+
+/* 2 REG_NOT_VALID_8814B */
+#define BIT_DISABLE_OPEN_SPS_LDO_8814B BIT(8)
+#define BIT_MAC_ID_EN_8814B BIT(7)
+#define BIT_WL_CTRL_XTAL_CADJ_8814B BIT(6)
+#define BIT_AFE_BGEN_PCIE_OP_8814B BIT(2)
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_SYS_SWR_CTRL2_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_SYS_SWR_CTRL3_8814B */
+#define BIT_SPS18_OCP_DIS_8814B BIT(31)
+
+#define BIT_SHIFT_SPS18_OCP_TH_8814B 16
+#define BIT_MASK_SPS18_OCP_TH_8814B 0x7fff
+#define BIT_SPS18_OCP_TH_8814B(x)                                              \
+	(((x) & BIT_MASK_SPS18_OCP_TH_8814B) << BIT_SHIFT_SPS18_OCP_TH_8814B)
+#define BITS_SPS18_OCP_TH_8814B                                                \
+	(BIT_MASK_SPS18_OCP_TH_8814B << BIT_SHIFT_SPS18_OCP_TH_8814B)
+#define BIT_CLEAR_SPS18_OCP_TH_8814B(x) ((x) & (~BITS_SPS18_OCP_TH_8814B))
+#define BIT_GET_SPS18_OCP_TH_8814B(x)                                          \
+	(((x) >> BIT_SHIFT_SPS18_OCP_TH_8814B) & BIT_MASK_SPS18_OCP_TH_8814B)
+#define BIT_SET_SPS18_OCP_TH_8814B(x, v)                                       \
+	(BIT_CLEAR_SPS18_OCP_TH_8814B(x) | BIT_SPS18_OCP_TH_8814B(v))
+
+#define BIT_SHIFT_OCP_WINDOW_8814B 0
+#define BIT_MASK_OCP_WINDOW_8814B 0xffff
+#define BIT_OCP_WINDOW_8814B(x)                                                \
+	(((x) & BIT_MASK_OCP_WINDOW_8814B) << BIT_SHIFT_OCP_WINDOW_8814B)
+#define BITS_OCP_WINDOW_8814B                                                  \
+	(BIT_MASK_OCP_WINDOW_8814B << BIT_SHIFT_OCP_WINDOW_8814B)
+#define BIT_CLEAR_OCP_WINDOW_8814B(x) ((x) & (~BITS_OCP_WINDOW_8814B))
+#define BIT_GET_OCP_WINDOW_8814B(x)                                            \
+	(((x) >> BIT_SHIFT_OCP_WINDOW_8814B) & BIT_MASK_OCP_WINDOW_8814B)
+#define BIT_SET_OCP_WINDOW_8814B(x, v)                                         \
+	(BIT_CLEAR_OCP_WINDOW_8814B(x) | BIT_OCP_WINDOW_8814B(v))
+
+/* 2 REG_RSV_CTRL_8814B */
+
+#define BIT_SHIFT_HREG_DBG_V1_8814B 12
+#define BIT_MASK_HREG_DBG_V1_8814B 0xfff
+#define BIT_HREG_DBG_V1_8814B(x)                                               \
+	(((x) & BIT_MASK_HREG_DBG_V1_8814B) << BIT_SHIFT_HREG_DBG_V1_8814B)
+#define BITS_HREG_DBG_V1_8814B                                                 \
+	(BIT_MASK_HREG_DBG_V1_8814B << BIT_SHIFT_HREG_DBG_V1_8814B)
+#define BIT_CLEAR_HREG_DBG_V1_8814B(x) ((x) & (~BITS_HREG_DBG_V1_8814B))
+#define BIT_GET_HREG_DBG_V1_8814B(x)                                           \
+	(((x) >> BIT_SHIFT_HREG_DBG_V1_8814B) & BIT_MASK_HREG_DBG_V1_8814B)
+#define BIT_SET_HREG_DBG_V1_8814B(x, v)                                        \
+	(BIT_CLEAR_HREG_DBG_V1_8814B(x) | BIT_HREG_DBG_V1_8814B(v))
+
+#define BIT_WLMCUIOIF_8814B BIT(8)
+#define BIT_LOCK_ALL_EN_8814B BIT(7)
+#define BIT_R_DIS_PRST_8814B BIT(6)
+#define BIT_WLOCK_1C_B6_8814B BIT(5)
+#define BIT_WLOCK_40_8814B BIT(4)
+#define BIT_WLOCK_08_8814B BIT(3)
+#define BIT_WLOCK_04_8814B BIT(2)
+#define BIT_WLOCK_00_8814B BIT(1)
+#define BIT_WLOCK_ALL_8814B BIT(0)
+
+/* 2 REG_RF_CTRL_8814B */
+#define BIT_RF_SDMRSTB_8814B BIT(2)
+#define BIT_RF_RSTB_8814B BIT(1)
+#define BIT_RF_EN_8814B BIT(0)
+
+/* 2 REG_AFE_LDO_CTRL_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+#define BIT_CPHY_LDO_CL_EN_8814B BIT(19)
+#define BIT_CPHY_LDO_OK_8814B BIT(18)
+#define BIT_PCIE_CALIB_EN_8814B BIT(17)
+#define BIT_LDH12_EN_8814B BIT(16)
+#define BIT_DATA_CPU_PWC_8814B BIT(15)
+#define BIT_WLBBOFF_BIG_PWC_EN_8814B BIT(14)
+#define BIT_WLBBOFF_SMALL_PWC_EN_8814B BIT(13)
+#define BIT_WLMACOFF_BIG_PWC_EN_8814B BIT(12)
+#define BIT_WLPON_PWC_EN_8814B BIT(11)
+
+/* 2 REG_NOT_VALID_8814B */
+#define BIT_LDOV12W_EN_8814B BIT(8)
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_AFE_CTRL1_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+#define BIT_SHIFT_MAC_CLK_SEL_8814B 20
+#define BIT_MASK_MAC_CLK_SEL_8814B 0x3
+#define BIT_MAC_CLK_SEL_8814B(x)                                               \
+	(((x) & BIT_MASK_MAC_CLK_SEL_8814B) << BIT_SHIFT_MAC_CLK_SEL_8814B)
+#define BITS_MAC_CLK_SEL_8814B                                                 \
+	(BIT_MASK_MAC_CLK_SEL_8814B << BIT_SHIFT_MAC_CLK_SEL_8814B)
+#define BIT_CLEAR_MAC_CLK_SEL_8814B(x) ((x) & (~BITS_MAC_CLK_SEL_8814B))
+#define BIT_GET_MAC_CLK_SEL_8814B(x)                                           \
+	(((x) >> BIT_SHIFT_MAC_CLK_SEL_8814B) & BIT_MASK_MAC_CLK_SEL_8814B)
+#define BIT_SET_MAC_CLK_SEL_8814B(x, v)                                        \
+	(BIT_CLEAR_MAC_CLK_SEL_8814B(x) | BIT_MAC_CLK_SEL_8814B(v))
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_ANAPARSW_POW_MAC_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+#define BIT_ENB_LDO_DIODE_L_8814B BIT(3)
+#define BIT_POW_LDO15_8814B BIT(2)
+#define BIT_POW_SW_8814B BIT(1)
+#define BIT_POW_LDO14_8814B BIT(0)
+
+/* 2 REG_ANAPARLDO_POW_MAC_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+#define BIT_LDOE25_POW_L_8814B BIT(0)
+
+/* 2 REG_ANAPAR_POW_MAC_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+#define BIT_POW_PC_LDO3_8814B BIT(5)
+#define BIT_POW_PC_LDO2_8814B BIT(4)
+#define BIT_POW_PC_LDO1_8814B BIT(3)
+#define BIT_POW_PC_LDO0_8814B BIT(2)
+#define BIT_POW_PLL_V1_8814B BIT(1)
+#define BIT_POW_POWER_CUT_8814B BIT(0)
+
+/* 2 REG_ANAPAR_POW_XTAL_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+#define BIT_POW_XTAL_8814B BIT(1)
+#define BIT_POW_BG_8814B BIT(0)
+
+/* 2 REG_ANAPARLDO_MAC_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_EFUSE_CTRL_8814B */
+#define BIT_EF_FLAG_8814B BIT(31)
+
+#define BIT_SHIFT_EF_PGPD_8814B 28
+#define BIT_MASK_EF_PGPD_8814B 0x7
+#define BIT_EF_PGPD_8814B(x)                                                   \
+	(((x) & BIT_MASK_EF_PGPD_8814B) << BIT_SHIFT_EF_PGPD_8814B)
+#define BITS_EF_PGPD_8814B (BIT_MASK_EF_PGPD_8814B << BIT_SHIFT_EF_PGPD_8814B)
+#define BIT_CLEAR_EF_PGPD_8814B(x) ((x) & (~BITS_EF_PGPD_8814B))
+#define BIT_GET_EF_PGPD_8814B(x)                                               \
+	(((x) >> BIT_SHIFT_EF_PGPD_8814B) & BIT_MASK_EF_PGPD_8814B)
+#define BIT_SET_EF_PGPD_8814B(x, v)                                            \
+	(BIT_CLEAR_EF_PGPD_8814B(x) | BIT_EF_PGPD_8814B(v))
+
+#define BIT_SHIFT_EF_RDT_8814B 24
+#define BIT_MASK_EF_RDT_8814B 0xf
+#define BIT_EF_RDT_8814B(x)                                                    \
+	(((x) & BIT_MASK_EF_RDT_8814B) << BIT_SHIFT_EF_RDT_8814B)
+#define BITS_EF_RDT_8814B (BIT_MASK_EF_RDT_8814B << BIT_SHIFT_EF_RDT_8814B)
+#define BIT_CLEAR_EF_RDT_8814B(x) ((x) & (~BITS_EF_RDT_8814B))
+#define BIT_GET_EF_RDT_8814B(x)                                                \
+	(((x) >> BIT_SHIFT_EF_RDT_8814B) & BIT_MASK_EF_RDT_8814B)
+#define BIT_SET_EF_RDT_8814B(x, v)                                             \
+	(BIT_CLEAR_EF_RDT_8814B(x) | BIT_EF_RDT_8814B(v))
+
+#define BIT_SHIFT_EF_PGTS_8814B 20
+#define BIT_MASK_EF_PGTS_8814B 0xf
+#define BIT_EF_PGTS_8814B(x)                                                   \
+	(((x) & BIT_MASK_EF_PGTS_8814B) << BIT_SHIFT_EF_PGTS_8814B)
+#define BITS_EF_PGTS_8814B (BIT_MASK_EF_PGTS_8814B << BIT_SHIFT_EF_PGTS_8814B)
+#define BIT_CLEAR_EF_PGTS_8814B(x) ((x) & (~BITS_EF_PGTS_8814B))
+#define BIT_GET_EF_PGTS_8814B(x)                                               \
+	(((x) >> BIT_SHIFT_EF_PGTS_8814B) & BIT_MASK_EF_PGTS_8814B)
+#define BIT_SET_EF_PGTS_8814B(x, v)                                            \
+	(BIT_CLEAR_EF_PGTS_8814B(x) | BIT_EF_PGTS_8814B(v))
+
+#define BIT_EF_PDWN_8814B BIT(19)
+#define BIT_EF_ALDEN_8814B BIT(18)
+
+#define BIT_SHIFT_EF_ADDR_8814B 8
+#define BIT_MASK_EF_ADDR_8814B 0x3ff
+#define BIT_EF_ADDR_8814B(x)                                                   \
+	(((x) & BIT_MASK_EF_ADDR_8814B) << BIT_SHIFT_EF_ADDR_8814B)
+#define BITS_EF_ADDR_8814B (BIT_MASK_EF_ADDR_8814B << BIT_SHIFT_EF_ADDR_8814B)
+#define BIT_CLEAR_EF_ADDR_8814B(x) ((x) & (~BITS_EF_ADDR_8814B))
+#define BIT_GET_EF_ADDR_8814B(x)                                               \
+	(((x) >> BIT_SHIFT_EF_ADDR_8814B) & BIT_MASK_EF_ADDR_8814B)
+#define BIT_SET_EF_ADDR_8814B(x, v)                                            \
+	(BIT_CLEAR_EF_ADDR_8814B(x) | BIT_EF_ADDR_8814B(v))
+
+#define BIT_SHIFT_EF_DATA_8814B 0
+#define BIT_MASK_EF_DATA_8814B 0xff
+#define BIT_EF_DATA_8814B(x)                                                   \
+	(((x) & BIT_MASK_EF_DATA_8814B) << BIT_SHIFT_EF_DATA_8814B)
+#define BITS_EF_DATA_8814B (BIT_MASK_EF_DATA_8814B << BIT_SHIFT_EF_DATA_8814B)
+#define BIT_CLEAR_EF_DATA_8814B(x) ((x) & (~BITS_EF_DATA_8814B))
+#define BIT_GET_EF_DATA_8814B(x)                                               \
+	(((x) >> BIT_SHIFT_EF_DATA_8814B) & BIT_MASK_EF_DATA_8814B)
+#define BIT_SET_EF_DATA_8814B(x, v)                                            \
+	(BIT_CLEAR_EF_DATA_8814B(x) | BIT_EF_DATA_8814B(v))
+
+/* 2 REG_LDO_EFUSE_CTRL_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+#define BIT_EF_CRES_SEL_8814B BIT(26)
+
+#define BIT_SHIFT_EF_SCAN_START_V1_8814B 16
+#define BIT_MASK_EF_SCAN_START_V1_8814B 0x3ff
+#define BIT_EF_SCAN_START_V1_8814B(x)                                          \
+	(((x) & BIT_MASK_EF_SCAN_START_V1_8814B)                               \
+	 << BIT_SHIFT_EF_SCAN_START_V1_8814B)
+#define BITS_EF_SCAN_START_V1_8814B                                            \
+	(BIT_MASK_EF_SCAN_START_V1_8814B << BIT_SHIFT_EF_SCAN_START_V1_8814B)
+#define BIT_CLEAR_EF_SCAN_START_V1_8814B(x)                                    \
+	((x) & (~BITS_EF_SCAN_START_V1_8814B))
+#define BIT_GET_EF_SCAN_START_V1_8814B(x)                                      \
+	(((x) >> BIT_SHIFT_EF_SCAN_START_V1_8814B) &                           \
+	 BIT_MASK_EF_SCAN_START_V1_8814B)
+#define BIT_SET_EF_SCAN_START_V1_8814B(x, v)                                   \
+	(BIT_CLEAR_EF_SCAN_START_V1_8814B(x) | BIT_EF_SCAN_START_V1_8814B(v))
+
+#define BIT_SHIFT_EF_SCAN_END_8814B 12
+#define BIT_MASK_EF_SCAN_END_8814B 0xf
+#define BIT_EF_SCAN_END_8814B(x)                                               \
+	(((x) & BIT_MASK_EF_SCAN_END_8814B) << BIT_SHIFT_EF_SCAN_END_8814B)
+#define BITS_EF_SCAN_END_8814B                                                 \
+	(BIT_MASK_EF_SCAN_END_8814B << BIT_SHIFT_EF_SCAN_END_8814B)
+#define BIT_CLEAR_EF_SCAN_END_8814B(x) ((x) & (~BITS_EF_SCAN_END_8814B))
+#define BIT_GET_EF_SCAN_END_8814B(x)                                           \
+	(((x) >> BIT_SHIFT_EF_SCAN_END_8814B) & BIT_MASK_EF_SCAN_END_8814B)
+#define BIT_SET_EF_SCAN_END_8814B(x, v)                                        \
+	(BIT_CLEAR_EF_SCAN_END_8814B(x) | BIT_EF_SCAN_END_8814B(v))
+
+#define BIT_EF_PD_DIS_8814B BIT(11)
+
+#define BIT_SHIFT_EF_CELL_SEL_8814B 8
+#define BIT_MASK_EF_CELL_SEL_8814B 0x3
+#define BIT_EF_CELL_SEL_8814B(x)                                               \
+	(((x) & BIT_MASK_EF_CELL_SEL_8814B) << BIT_SHIFT_EF_CELL_SEL_8814B)
+#define BITS_EF_CELL_SEL_8814B                                                 \
+	(BIT_MASK_EF_CELL_SEL_8814B << BIT_SHIFT_EF_CELL_SEL_8814B)
+#define BIT_CLEAR_EF_CELL_SEL_8814B(x) ((x) & (~BITS_EF_CELL_SEL_8814B))
+#define BIT_GET_EF_CELL_SEL_8814B(x)                                           \
+	(((x) >> BIT_SHIFT_EF_CELL_SEL_8814B) & BIT_MASK_EF_CELL_SEL_8814B)
+#define BIT_SET_EF_CELL_SEL_8814B(x, v)                                        \
+	(BIT_CLEAR_EF_CELL_SEL_8814B(x) | BIT_EF_CELL_SEL_8814B(v))
+
+#define BIT_EF_TRPT_8814B BIT(7)
+
+#define BIT_SHIFT_EF_TTHD_8814B 0
+#define BIT_MASK_EF_TTHD_8814B 0x7f
+#define BIT_EF_TTHD_8814B(x)                                                   \
+	(((x) & BIT_MASK_EF_TTHD_8814B) << BIT_SHIFT_EF_TTHD_8814B)
+#define BITS_EF_TTHD_8814B (BIT_MASK_EF_TTHD_8814B << BIT_SHIFT_EF_TTHD_8814B)
+#define BIT_CLEAR_EF_TTHD_8814B(x) ((x) & (~BITS_EF_TTHD_8814B))
+#define BIT_GET_EF_TTHD_8814B(x)                                               \
+	(((x) >> BIT_SHIFT_EF_TTHD_8814B) & BIT_MASK_EF_TTHD_8814B)
+#define BIT_SET_EF_TTHD_8814B(x, v)                                            \
+	(BIT_CLEAR_EF_TTHD_8814B(x) | BIT_EF_TTHD_8814B(v))
+
+/* 2 REG_PWR_OPTION_CTRL_8814B */
+
+#define BIT_SHIFT_DBG_SEL_V1_8814B 16
+#define BIT_MASK_DBG_SEL_V1_8814B 0xff
+#define BIT_DBG_SEL_V1_8814B(x)                                                \
+	(((x) & BIT_MASK_DBG_SEL_V1_8814B) << BIT_SHIFT_DBG_SEL_V1_8814B)
+#define BITS_DBG_SEL_V1_8814B                                                  \
+	(BIT_MASK_DBG_SEL_V1_8814B << BIT_SHIFT_DBG_SEL_V1_8814B)
+#define BIT_CLEAR_DBG_SEL_V1_8814B(x) ((x) & (~BITS_DBG_SEL_V1_8814B))
+#define BIT_GET_DBG_SEL_V1_8814B(x)                                            \
+	(((x) >> BIT_SHIFT_DBG_SEL_V1_8814B) & BIT_MASK_DBG_SEL_V1_8814B)
+#define BIT_SET_DBG_SEL_V1_8814B(x, v)                                         \
+	(BIT_CLEAR_DBG_SEL_V1_8814B(x) | BIT_DBG_SEL_V1_8814B(v))
+
+#define BIT_SHIFT_DBG_SEL_BYTE_8814B 14
+#define BIT_MASK_DBG_SEL_BYTE_8814B 0x3
+#define BIT_DBG_SEL_BYTE_8814B(x)                                              \
+	(((x) & BIT_MASK_DBG_SEL_BYTE_8814B) << BIT_SHIFT_DBG_SEL_BYTE_8814B)
+#define BITS_DBG_SEL_BYTE_8814B                                                \
+	(BIT_MASK_DBG_SEL_BYTE_8814B << BIT_SHIFT_DBG_SEL_BYTE_8814B)
+#define BIT_CLEAR_DBG_SEL_BYTE_8814B(x) ((x) & (~BITS_DBG_SEL_BYTE_8814B))
+#define BIT_GET_DBG_SEL_BYTE_8814B(x)                                          \
+	(((x) >> BIT_SHIFT_DBG_SEL_BYTE_8814B) & BIT_MASK_DBG_SEL_BYTE_8814B)
+#define BIT_SET_DBG_SEL_BYTE_8814B(x, v)                                       \
+	(BIT_CLEAR_DBG_SEL_BYTE_8814B(x) | BIT_DBG_SEL_BYTE_8814B(v))
+
+/* 2 REG_NOT_VALID_8814B */
+#define BIT_SYSON_DBG_PAD_E2_8814B BIT(11)
+#define BIT_SYSON_LED_PAD_E2_8814B BIT(10)
+#define BIT_SYSON_GPEE_PAD_E2_8814B BIT(9)
+#define BIT_SYSON_PCI_PAD_E2_8814B BIT(8)
+#define BIT_AUTO_SW_LDO_VOL_EN_8814B BIT(7)
+
+#define BIT_SHIFT_SYSON_SPS0WWV_WT_8814B 4
+#define BIT_MASK_SYSON_SPS0WWV_WT_8814B 0x3
+#define BIT_SYSON_SPS0WWV_WT_8814B(x)                                          \
+	(((x) & BIT_MASK_SYSON_SPS0WWV_WT_8814B)                               \
+	 << BIT_SHIFT_SYSON_SPS0WWV_WT_8814B)
+#define BITS_SYSON_SPS0WWV_WT_8814B                                            \
+	(BIT_MASK_SYSON_SPS0WWV_WT_8814B << BIT_SHIFT_SYSON_SPS0WWV_WT_8814B)
+#define BIT_CLEAR_SYSON_SPS0WWV_WT_8814B(x)                                    \
+	((x) & (~BITS_SYSON_SPS0WWV_WT_8814B))
+#define BIT_GET_SYSON_SPS0WWV_WT_8814B(x)                                      \
+	(((x) >> BIT_SHIFT_SYSON_SPS0WWV_WT_8814B) &                           \
+	 BIT_MASK_SYSON_SPS0WWV_WT_8814B)
+#define BIT_SET_SYSON_SPS0WWV_WT_8814B(x, v)                                   \
+	(BIT_CLEAR_SYSON_SPS0WWV_WT_8814B(x) | BIT_SYSON_SPS0WWV_WT_8814B(v))
+
+#define BIT_SHIFT_SYSON_SPS0LDO_WT_8814B 2
+#define BIT_MASK_SYSON_SPS0LDO_WT_8814B 0x3
+#define BIT_SYSON_SPS0LDO_WT_8814B(x)                                          \
+	(((x) & BIT_MASK_SYSON_SPS0LDO_WT_8814B)                               \
+	 << BIT_SHIFT_SYSON_SPS0LDO_WT_8814B)
+#define BITS_SYSON_SPS0LDO_WT_8814B                                            \
+	(BIT_MASK_SYSON_SPS0LDO_WT_8814B << BIT_SHIFT_SYSON_SPS0LDO_WT_8814B)
+#define BIT_CLEAR_SYSON_SPS0LDO_WT_8814B(x)                                    \
+	((x) & (~BITS_SYSON_SPS0LDO_WT_8814B))
+#define BIT_GET_SYSON_SPS0LDO_WT_8814B(x)                                      \
+	(((x) >> BIT_SHIFT_SYSON_SPS0LDO_WT_8814B) &                           \
+	 BIT_MASK_SYSON_SPS0LDO_WT_8814B)
+#define BIT_SET_SYSON_SPS0LDO_WT_8814B(x, v)                                   \
+	(BIT_CLEAR_SYSON_SPS0LDO_WT_8814B(x) | BIT_SYSON_SPS0LDO_WT_8814B(v))
+
+#define BIT_SHIFT_SYSON_RCLK_SCALE_8814B 0
+#define BIT_MASK_SYSON_RCLK_SCALE_8814B 0x3
+#define BIT_SYSON_RCLK_SCALE_8814B(x)                                          \
+	(((x) & BIT_MASK_SYSON_RCLK_SCALE_8814B)                               \
+	 << BIT_SHIFT_SYSON_RCLK_SCALE_8814B)
+#define BITS_SYSON_RCLK_SCALE_8814B                                            \
+	(BIT_MASK_SYSON_RCLK_SCALE_8814B << BIT_SHIFT_SYSON_RCLK_SCALE_8814B)
+#define BIT_CLEAR_SYSON_RCLK_SCALE_8814B(x)                                    \
+	((x) & (~BITS_SYSON_RCLK_SCALE_8814B))
+#define BIT_GET_SYSON_RCLK_SCALE_8814B(x)                                      \
+	(((x) >> BIT_SHIFT_SYSON_RCLK_SCALE_8814B) &                           \
+	 BIT_MASK_SYSON_RCLK_SCALE_8814B)
+#define BIT_SET_SYSON_RCLK_SCALE_8814B(x, v)                                   \
+	(BIT_CLEAR_SYSON_RCLK_SCALE_8814B(x) | BIT_SYSON_RCLK_SCALE_8814B(v))
+
+/* 2 REG_CAL_TIMER_8814B */
+
+#define BIT_SHIFT_MATCH_CNT_8814B 8
+#define BIT_MASK_MATCH_CNT_8814B 0xff
+#define BIT_MATCH_CNT_8814B(x)                                                 \
+	(((x) & BIT_MASK_MATCH_CNT_8814B) << BIT_SHIFT_MATCH_CNT_8814B)
+#define BITS_MATCH_CNT_8814B                                                   \
+	(BIT_MASK_MATCH_CNT_8814B << BIT_SHIFT_MATCH_CNT_8814B)
+#define BIT_CLEAR_MATCH_CNT_8814B(x) ((x) & (~BITS_MATCH_CNT_8814B))
+#define BIT_GET_MATCH_CNT_8814B(x)                                             \
+	(((x) >> BIT_SHIFT_MATCH_CNT_8814B) & BIT_MASK_MATCH_CNT_8814B)
+#define BIT_SET_MATCH_CNT_8814B(x, v)                                          \
+	(BIT_CLEAR_MATCH_CNT_8814B(x) | BIT_MATCH_CNT_8814B(v))
+
+#define BIT_SHIFT_CAL_SCAL_8814B 0
+#define BIT_MASK_CAL_SCAL_8814B 0xff
+#define BIT_CAL_SCAL_8814B(x)                                                  \
+	(((x) & BIT_MASK_CAL_SCAL_8814B) << BIT_SHIFT_CAL_SCAL_8814B)
+#define BITS_CAL_SCAL_8814B                                                    \
+	(BIT_MASK_CAL_SCAL_8814B << BIT_SHIFT_CAL_SCAL_8814B)
+#define BIT_CLEAR_CAL_SCAL_8814B(x) ((x) & (~BITS_CAL_SCAL_8814B))
+#define BIT_GET_CAL_SCAL_8814B(x)                                              \
+	(((x) >> BIT_SHIFT_CAL_SCAL_8814B) & BIT_MASK_CAL_SCAL_8814B)
+#define BIT_SET_CAL_SCAL_8814B(x, v)                                           \
+	(BIT_CLEAR_CAL_SCAL_8814B(x) | BIT_CAL_SCAL_8814B(v))
+
+/* 2 REG_ACLK_MON_8814B */
+
+#define BIT_SHIFT_RCLK_MON_8814B 5
+#define BIT_MASK_RCLK_MON_8814B 0x7ff
+#define BIT_RCLK_MON_8814B(x)                                                  \
+	(((x) & BIT_MASK_RCLK_MON_8814B) << BIT_SHIFT_RCLK_MON_8814B)
+#define BITS_RCLK_MON_8814B                                                    \
+	(BIT_MASK_RCLK_MON_8814B << BIT_SHIFT_RCLK_MON_8814B)
+#define BIT_CLEAR_RCLK_MON_8814B(x) ((x) & (~BITS_RCLK_MON_8814B))
+#define BIT_GET_RCLK_MON_8814B(x)                                              \
+	(((x) >> BIT_SHIFT_RCLK_MON_8814B) & BIT_MASK_RCLK_MON_8814B)
+#define BIT_SET_RCLK_MON_8814B(x, v)                                           \
+	(BIT_CLEAR_RCLK_MON_8814B(x) | BIT_RCLK_MON_8814B(v))
+
+#define BIT_CAL_EN_8814B BIT(4)
+
+#define BIT_SHIFT_DPSTU_8814B 2
+#define BIT_MASK_DPSTU_8814B 0x3
+#define BIT_DPSTU_8814B(x)                                                     \
+	(((x) & BIT_MASK_DPSTU_8814B) << BIT_SHIFT_DPSTU_8814B)
+#define BITS_DPSTU_8814B (BIT_MASK_DPSTU_8814B << BIT_SHIFT_DPSTU_8814B)
+#define BIT_CLEAR_DPSTU_8814B(x) ((x) & (~BITS_DPSTU_8814B))
+#define BIT_GET_DPSTU_8814B(x)                                                 \
+	(((x) >> BIT_SHIFT_DPSTU_8814B) & BIT_MASK_DPSTU_8814B)
+#define BIT_SET_DPSTU_8814B(x, v)                                              \
+	(BIT_CLEAR_DPSTU_8814B(x) | BIT_DPSTU_8814B(v))
+
+#define BIT_SUS_16X_8814B BIT(1)
+
+/* 2 REG_GPIO_MUXCFG_8814B */
+#define BIT_EN_DATACPU_GPIO2_8814B BIT(24)
+#define BIT_EN_DATACPU_GPIO_8814B BIT(23)
+#define BIT_EN_DATACPU_UART_8814B BIT(22)
+#define BIT_DATACPU_FSPI_EN_8814B BIT(21)
+#define BIT_EN_GPIO8_UART_OUT_8814B BIT(20)
+#define BIT_FSPI_EN_8814B BIT(19)
+#define BIT_WL_RTS_EXT_32K_SEL_8814B BIT(18)
+#define BIT_WLGP_SPI_EN_8814B BIT(16)
+#define BIT_SIC_LBK_8814B BIT(15)
+#define BIT_ENHTP_8814B BIT(14)
+#define BIT_ENSIC_8814B BIT(12)
+#define BIT_SIC_SWRST_8814B BIT(11)
+#define BIT_PO_WIFI_PTA_PINS_8814B BIT(10)
+#define BIT_PO_BT_PTA_PINS_8814B BIT(9)
+#define BIT_ENUART_8814B BIT(8)
+
+#define BIT_SHIFT_BTMODE_8814B 6
+#define BIT_MASK_BTMODE_8814B 0x3
+#define BIT_BTMODE_8814B(x)                                                    \
+	(((x) & BIT_MASK_BTMODE_8814B) << BIT_SHIFT_BTMODE_8814B)
+#define BITS_BTMODE_8814B (BIT_MASK_BTMODE_8814B << BIT_SHIFT_BTMODE_8814B)
+#define BIT_CLEAR_BTMODE_8814B(x) ((x) & (~BITS_BTMODE_8814B))
+#define BIT_GET_BTMODE_8814B(x)                                                \
+	(((x) >> BIT_SHIFT_BTMODE_8814B) & BIT_MASK_BTMODE_8814B)
+#define BIT_SET_BTMODE_8814B(x, v)                                             \
+	(BIT_CLEAR_BTMODE_8814B(x) | BIT_BTMODE_8814B(v))
+
+#define BIT_ENBT_8814B BIT(5)
+#define BIT_EROM_EN_8814B BIT(4)
+#define BIT_WLRFE_6_7_EN_8814B BIT(3)
+#define BIT_WLRFE_4_5_EN_8814B BIT(2)
+
+#define BIT_SHIFT_GPIOSEL_8814B 0
+#define BIT_MASK_GPIOSEL_8814B 0x3
+#define BIT_GPIOSEL_8814B(x)                                                   \
+	(((x) & BIT_MASK_GPIOSEL_8814B) << BIT_SHIFT_GPIOSEL_8814B)
+#define BITS_GPIOSEL_8814B (BIT_MASK_GPIOSEL_8814B << BIT_SHIFT_GPIOSEL_8814B)
+#define BIT_CLEAR_GPIOSEL_8814B(x) ((x) & (~BITS_GPIOSEL_8814B))
+#define BIT_GET_GPIOSEL_8814B(x)                                               \
+	(((x) >> BIT_SHIFT_GPIOSEL_8814B) & BIT_MASK_GPIOSEL_8814B)
+#define BIT_SET_GPIOSEL_8814B(x, v)                                            \
+	(BIT_CLEAR_GPIOSEL_8814B(x) | BIT_GPIOSEL_8814B(v))
+
+/* 2 REG_GPIO_PIN_CTRL_8814B */
+
+#define BIT_SHIFT_GPIO_MOD_7_TO_0_8814B 24
+#define BIT_MASK_GPIO_MOD_7_TO_0_8814B 0xff
+#define BIT_GPIO_MOD_7_TO_0_8814B(x)                                           \
+	(((x) & BIT_MASK_GPIO_MOD_7_TO_0_8814B)                                \
+	 << BIT_SHIFT_GPIO_MOD_7_TO_0_8814B)
+#define BITS_GPIO_MOD_7_TO_0_8814B                                             \
+	(BIT_MASK_GPIO_MOD_7_TO_0_8814B << BIT_SHIFT_GPIO_MOD_7_TO_0_8814B)
+#define BIT_CLEAR_GPIO_MOD_7_TO_0_8814B(x) ((x) & (~BITS_GPIO_MOD_7_TO_0_8814B))
+#define BIT_GET_GPIO_MOD_7_TO_0_8814B(x)                                       \
+	(((x) >> BIT_SHIFT_GPIO_MOD_7_TO_0_8814B) &                            \
+	 BIT_MASK_GPIO_MOD_7_TO_0_8814B)
+#define BIT_SET_GPIO_MOD_7_TO_0_8814B(x, v)                                    \
+	(BIT_CLEAR_GPIO_MOD_7_TO_0_8814B(x) | BIT_GPIO_MOD_7_TO_0_8814B(v))
+
+#define BIT_SHIFT_GPIO_IO_SEL_7_TO_0_8814B 16
+#define BIT_MASK_GPIO_IO_SEL_7_TO_0_8814B 0xff
+#define BIT_GPIO_IO_SEL_7_TO_0_8814B(x)                                        \
+	(((x) & BIT_MASK_GPIO_IO_SEL_7_TO_0_8814B)                             \
+	 << BIT_SHIFT_GPIO_IO_SEL_7_TO_0_8814B)
+#define BITS_GPIO_IO_SEL_7_TO_0_8814B                                          \
+	(BIT_MASK_GPIO_IO_SEL_7_TO_0_8814B                                     \
+	 << BIT_SHIFT_GPIO_IO_SEL_7_TO_0_8814B)
+#define BIT_CLEAR_GPIO_IO_SEL_7_TO_0_8814B(x)                                  \
+	((x) & (~BITS_GPIO_IO_SEL_7_TO_0_8814B))
+#define BIT_GET_GPIO_IO_SEL_7_TO_0_8814B(x)                                    \
+	(((x) >> BIT_SHIFT_GPIO_IO_SEL_7_TO_0_8814B) &                         \
+	 BIT_MASK_GPIO_IO_SEL_7_TO_0_8814B)
+#define BIT_SET_GPIO_IO_SEL_7_TO_0_8814B(x, v)                                 \
+	(BIT_CLEAR_GPIO_IO_SEL_7_TO_0_8814B(x) |                               \
+	 BIT_GPIO_IO_SEL_7_TO_0_8814B(v))
+
+#define BIT_SHIFT_GPIO_OUT_7_TO_0_8814B 8
+#define BIT_MASK_GPIO_OUT_7_TO_0_8814B 0xff
+#define BIT_GPIO_OUT_7_TO_0_8814B(x)                                           \
+	(((x) & BIT_MASK_GPIO_OUT_7_TO_0_8814B)                                \
+	 << BIT_SHIFT_GPIO_OUT_7_TO_0_8814B)
+#define BITS_GPIO_OUT_7_TO_0_8814B                                             \
+	(BIT_MASK_GPIO_OUT_7_TO_0_8814B << BIT_SHIFT_GPIO_OUT_7_TO_0_8814B)
+#define BIT_CLEAR_GPIO_OUT_7_TO_0_8814B(x) ((x) & (~BITS_GPIO_OUT_7_TO_0_8814B))
+#define BIT_GET_GPIO_OUT_7_TO_0_8814B(x)                                       \
+	(((x) >> BIT_SHIFT_GPIO_OUT_7_TO_0_8814B) &                            \
+	 BIT_MASK_GPIO_OUT_7_TO_0_8814B)
+#define BIT_SET_GPIO_OUT_7_TO_0_8814B(x, v)                                    \
+	(BIT_CLEAR_GPIO_OUT_7_TO_0_8814B(x) | BIT_GPIO_OUT_7_TO_0_8814B(v))
+
+#define BIT_SHIFT_GPIO_IN_7_TO_0_8814B 0
+#define BIT_MASK_GPIO_IN_7_TO_0_8814B 0xff
+#define BIT_GPIO_IN_7_TO_0_8814B(x)                                            \
+	(((x) & BIT_MASK_GPIO_IN_7_TO_0_8814B)                                 \
+	 << BIT_SHIFT_GPIO_IN_7_TO_0_8814B)
+#define BITS_GPIO_IN_7_TO_0_8814B                                              \
+	(BIT_MASK_GPIO_IN_7_TO_0_8814B << BIT_SHIFT_GPIO_IN_7_TO_0_8814B)
+#define BIT_CLEAR_GPIO_IN_7_TO_0_8814B(x) ((x) & (~BITS_GPIO_IN_7_TO_0_8814B))
+#define BIT_GET_GPIO_IN_7_TO_0_8814B(x)                                        \
+	(((x) >> BIT_SHIFT_GPIO_IN_7_TO_0_8814B) &                             \
+	 BIT_MASK_GPIO_IN_7_TO_0_8814B)
+#define BIT_SET_GPIO_IN_7_TO_0_8814B(x, v)                                     \
+	(BIT_CLEAR_GPIO_IN_7_TO_0_8814B(x) | BIT_GPIO_IN_7_TO_0_8814B(v))
+
+/* 2 REG_GPIO_INTM_8814B */
+
+#define BIT_SHIFT_MUXDBG_SEL_8814B 30
+#define BIT_MASK_MUXDBG_SEL_8814B 0x3
+#define BIT_MUXDBG_SEL_8814B(x)                                                \
+	(((x) & BIT_MASK_MUXDBG_SEL_8814B) << BIT_SHIFT_MUXDBG_SEL_8814B)
+#define BITS_MUXDBG_SEL_8814B                                                  \
+	(BIT_MASK_MUXDBG_SEL_8814B << BIT_SHIFT_MUXDBG_SEL_8814B)
+#define BIT_CLEAR_MUXDBG_SEL_8814B(x) ((x) & (~BITS_MUXDBG_SEL_8814B))
+#define BIT_GET_MUXDBG_SEL_8814B(x)                                            \
+	(((x) >> BIT_SHIFT_MUXDBG_SEL_8814B) & BIT_MASK_MUXDBG_SEL_8814B)
+#define BIT_SET_MUXDBG_SEL_8814B(x, v)                                         \
+	(BIT_CLEAR_MUXDBG_SEL_8814B(x) | BIT_MUXDBG_SEL_8814B(v))
+
+#define BIT_EXTWOL_SEL_8814B BIT(17)
+#define BIT_EXTWOL_EN_8814B BIT(16)
+#define BIT_GPIOF_INT_MD_8814B BIT(15)
+#define BIT_GPIOE_INT_MD_8814B BIT(14)
+#define BIT_GPIOD_INT_MD_8814B BIT(13)
+#define BIT_GPIOF_INT_MD_8814B BIT(15)
+#define BIT_GPIOE_INT_MD_8814B BIT(14)
+#define BIT_GPIOD_INT_MD_8814B BIT(13)
+#define BIT_GPIOC_INT_MD_8814B BIT(12)
+#define BIT_GPIOB_INT_MD_8814B BIT(11)
+#define BIT_GPIOA_INT_MD_8814B BIT(10)
+#define BIT_GPIO9_INT_MD_8814B BIT(9)
+#define BIT_GPIO8_INT_MD_8814B BIT(8)
+#define BIT_GPIO7_INT_MD_8814B BIT(7)
+#define BIT_GPIO6_INT_MD_8814B BIT(6)
+#define BIT_GPIO5_INT_MD_8814B BIT(5)
+#define BIT_GPIO4_INT_MD_8814B BIT(4)
+#define BIT_GPIO3_INT_MD_8814B BIT(3)
+#define BIT_GPIO2_INT_MD_8814B BIT(2)
+#define BIT_GPIO1_INT_MD_8814B BIT(1)
+#define BIT_GPIO0_INT_MD_8814B BIT(0)
+
+/* 2 REG_LED_CFG_8814B */
+#define BIT_GPIO3_WL_CTRL_EN_8814B BIT(27)
+#define BIT_LNAON_SEL_EN_8814B BIT(26)
+#define BIT_PAPE_SEL_EN_8814B BIT(25)
+#define BIT_DPDT_WLBT_SEL_8814B BIT(24)
+#define BIT_DPDT_SEL_EN_8814B BIT(23)
+#define BIT_GPIO13_14_WL_CTRL_EN_8814B BIT(22)
+#define BIT_LED2DIS_8814B BIT(21)
+#define BIT_LED2PL_8814B BIT(20)
+#define BIT_LED2SV_8814B BIT(19)
+
+#define BIT_SHIFT_LED2CM_8814B 16
+#define BIT_MASK_LED2CM_8814B 0x7
+#define BIT_LED2CM_8814B(x)                                                    \
+	(((x) & BIT_MASK_LED2CM_8814B) << BIT_SHIFT_LED2CM_8814B)
+#define BITS_LED2CM_8814B (BIT_MASK_LED2CM_8814B << BIT_SHIFT_LED2CM_8814B)
+#define BIT_CLEAR_LED2CM_8814B(x) ((x) & (~BITS_LED2CM_8814B))
+#define BIT_GET_LED2CM_8814B(x)                                                \
+	(((x) >> BIT_SHIFT_LED2CM_8814B) & BIT_MASK_LED2CM_8814B)
+#define BIT_SET_LED2CM_8814B(x, v)                                             \
+	(BIT_CLEAR_LED2CM_8814B(x) | BIT_LED2CM_8814B(v))
+
+#define BIT_LED1DIS_8814B BIT(15)
+#define BIT_LED1PL_8814B BIT(12)
+#define BIT_LED1SV_8814B BIT(11)
+
+#define BIT_SHIFT_LED1CM_8814B 8
+#define BIT_MASK_LED1CM_8814B 0x7
+#define BIT_LED1CM_8814B(x)                                                    \
+	(((x) & BIT_MASK_LED1CM_8814B) << BIT_SHIFT_LED1CM_8814B)
+#define BITS_LED1CM_8814B (BIT_MASK_LED1CM_8814B << BIT_SHIFT_LED1CM_8814B)
+#define BIT_CLEAR_LED1CM_8814B(x) ((x) & (~BITS_LED1CM_8814B))
+#define BIT_GET_LED1CM_8814B(x)                                                \
+	(((x) >> BIT_SHIFT_LED1CM_8814B) & BIT_MASK_LED1CM_8814B)
+#define BIT_SET_LED1CM_8814B(x, v)                                             \
+	(BIT_CLEAR_LED1CM_8814B(x) | BIT_LED1CM_8814B(v))
+
+#define BIT_LED0DIS_8814B BIT(7)
+
+#define BIT_SHIFT_AFE_LDO_SWR_CHECK_8814B 5
+#define BIT_MASK_AFE_LDO_SWR_CHECK_8814B 0x3
+#define BIT_AFE_LDO_SWR_CHECK_8814B(x)                                         \
+	(((x) & BIT_MASK_AFE_LDO_SWR_CHECK_8814B)                              \
+	 << BIT_SHIFT_AFE_LDO_SWR_CHECK_8814B)
+#define BITS_AFE_LDO_SWR_CHECK_8814B                                           \
+	(BIT_MASK_AFE_LDO_SWR_CHECK_8814B << BIT_SHIFT_AFE_LDO_SWR_CHECK_8814B)
+#define BIT_CLEAR_AFE_LDO_SWR_CHECK_8814B(x)                                   \
+	((x) & (~BITS_AFE_LDO_SWR_CHECK_8814B))
+#define BIT_GET_AFE_LDO_SWR_CHECK_8814B(x)                                     \
+	(((x) >> BIT_SHIFT_AFE_LDO_SWR_CHECK_8814B) &                          \
+	 BIT_MASK_AFE_LDO_SWR_CHECK_8814B)
+#define BIT_SET_AFE_LDO_SWR_CHECK_8814B(x, v)                                  \
+	(BIT_CLEAR_AFE_LDO_SWR_CHECK_8814B(x) | BIT_AFE_LDO_SWR_CHECK_8814B(v))
+
+#define BIT_LED0PL_8814B BIT(4)
+#define BIT_LED0SV_8814B BIT(3)
+
+#define BIT_SHIFT_LED0CM_8814B 0
+#define BIT_MASK_LED0CM_8814B 0x7
+#define BIT_LED0CM_8814B(x)                                                    \
+	(((x) & BIT_MASK_LED0CM_8814B) << BIT_SHIFT_LED0CM_8814B)
+#define BITS_LED0CM_8814B (BIT_MASK_LED0CM_8814B << BIT_SHIFT_LED0CM_8814B)
+#define BIT_CLEAR_LED0CM_8814B(x) ((x) & (~BITS_LED0CM_8814B))
+#define BIT_GET_LED0CM_8814B(x)                                                \
+	(((x) >> BIT_SHIFT_LED0CM_8814B) & BIT_MASK_LED0CM_8814B)
+#define BIT_SET_LED0CM_8814B(x, v)                                             \
+	(BIT_CLEAR_LED0CM_8814B(x) | BIT_LED0CM_8814B(v))
+
+/* 2 REG_FSIMR_8814B */
+#define BIT_FS_PDNINT_EN_8814B BIT(31)
+#define BIT_NFC_INT_PAD_EN_8814B BIT(30)
+#define BIT_FS_SPS_OCP_INT_EN_8814B BIT(29)
+#define BIT_FS_PWMERR_INT_EN_8814B BIT(28)
+#define BIT_FS_GPIOF_INT_EN_8814B BIT(27)
+#define BIT_FS_GPIOE_INT_EN_8814B BIT(26)
+#define BIT_FS_GPIOD_INT_EN_8814B BIT(25)
+#define BIT_FS_GPIOC_INT_EN_8814B BIT(24)
+#define BIT_FS_GPIOB_INT_EN_8814B BIT(23)
+#define BIT_FS_GPIOA_INT_EN_8814B BIT(22)
+#define BIT_FS_GPIO9_INT_EN_8814B BIT(21)
+#define BIT_FS_GPIO8_INT_EN_8814B BIT(20)
+#define BIT_FS_GPIO7_INT_EN_8814B BIT(19)
+#define BIT_FS_GPIO6_INT_EN_8814B BIT(18)
+#define BIT_FS_GPIO5_INT_EN_8814B BIT(17)
+#define BIT_FS_GPIO4_INT_EN_8814B BIT(16)
+#define BIT_FS_GPIO3_INT_EN_8814B BIT(15)
+#define BIT_FS_GPIO2_INT_EN_8814B BIT(14)
+#define BIT_FS_GPIO1_INT_EN_8814B BIT(13)
+#define BIT_FS_GPIO0_INT_EN_8814B BIT(12)
+#define BIT_FS_HCI_SUS_EN_8814B BIT(11)
+#define BIT_FS_HCI_RES_EN_8814B BIT(10)
+#define BIT_FS_HCI_RESET_EN_8814B BIT(9)
+#define BIT_USB_SCSI_CMD_EN_8814B BIT(8)
+#define BIT_FS_BTON_STS_UPDATE_MSK_EN_8814B BIT(7)
+#define BIT_ACT2RECOVERY_INT_EN_V1_8814B BIT(6)
+#define BIT_GEN1GEN2_SWITCH_8814B BIT(5)
+#define BIT_HCI_TXDMA_REQ_HIMR_8814B BIT(4)
+#define BIT_FS_32K_LEAVE_SETTING_MAK_8814B BIT(3)
+#define BIT_FS_32K_ENTER_SETTING_MAK_8814B BIT(2)
+#define BIT_FS_USB_LPMRSM_MSK_8814B BIT(1)
+#define BIT_FS_USB_LPMINT_MSK_8814B BIT(0)
+
+/* 2 REG_FSISR_8814B */
+#define BIT_FS_PDNINT_8814B BIT(31)
+#define BIT_FS_SPS_OCP_INT_8814B BIT(29)
+#define BIT_FS_PWMERR_INT_8814B BIT(28)
+#define BIT_FS_GPIOF_INT_8814B BIT(27)
+#define BIT_FS_GPIOE_INT_8814B BIT(26)
+#define BIT_FS_GPIOD_INT_8814B BIT(25)
+#define BIT_FS_GPIOC_INT_8814B BIT(24)
+#define BIT_FS_GPIOB_INT_8814B BIT(23)
+#define BIT_FS_GPIOA_INT_8814B BIT(22)
+#define BIT_FS_GPIO9_INT_8814B BIT(21)
+#define BIT_FS_GPIO8_INT_8814B BIT(20)
+#define BIT_FS_GPIO7_INT_8814B BIT(19)
+#define BIT_FS_GPIO6_INT_8814B BIT(18)
+#define BIT_FS_GPIO5_INT_8814B BIT(17)
+#define BIT_FS_GPIO4_INT_8814B BIT(16)
+#define BIT_FS_GPIO3_INT_8814B BIT(15)
+#define BIT_FS_GPIO2_INT_8814B BIT(14)
+#define BIT_FS_GPIO1_INT_8814B BIT(13)
+#define BIT_FS_GPIO0_INT_8814B BIT(12)
+#define BIT_FS_HCI_SUS_INT_8814B BIT(11)
+#define BIT_FS_HCI_RES_INT_8814B BIT(10)
+#define BIT_FS_HCI_RESET_INT_8814B BIT(9)
+#define BIT_USB_SCSI_CMD_INT_8814B BIT(8)
+#define BIT_FS_BTON_STS_UPDATE_INT_8814B BIT(7)
+#define BIT_ACT2RECOVERY_8814B BIT(6)
+#define BIT_GEN1GEN2_SWITCH_8814B BIT(5)
+#define BIT_HCI_TXDMA_REQ_HISR_8814B BIT(4)
+#define BIT_FS_32K_LEAVE_SETTING_INT_8814B BIT(3)
+#define BIT_FS_32K_ENTER_SETTING_INT_8814B BIT(2)
+#define BIT_FS_USB_LPMRSM_INT_8814B BIT(1)
+#define BIT_FS_USB_LPMINT_INT_8814B BIT(0)
+
+/* 2 REG_HSIMR_8814B */
+#define BIT_GPIOF_INT_EN_8814B BIT(31)
+#define BIT_GPIOE_INT_EN_8814B BIT(30)
+#define BIT_GPIOD_INT_EN_8814B BIT(29)
+#define BIT_GPIOC_INT_EN_8814B BIT(28)
+#define BIT_GPIOB_INT_EN_8814B BIT(27)
+#define BIT_GPIOA_INT_EN_8814B BIT(26)
+#define BIT_GPIO9_INT_EN_8814B BIT(25)
+#define BIT_GPIO8_INT_EN_8814B BIT(24)
+#define BIT_GPIO7_INT_EN_8814B BIT(23)
+#define BIT_GPIO6_INT_EN_8814B BIT(22)
+#define BIT_GPIO5_INT_EN_8814B BIT(21)
+#define BIT_GPIO4_INT_EN_8814B BIT(20)
+#define BIT_GPIO3_INT_EN_8814B BIT(19)
+#define BIT_GPIO2_INT_EN_V1_8814B BIT(18)
+#define BIT_GPIO1_INT_EN_8814B BIT(17)
+#define BIT_GPIO0_INT_EN_8814B BIT(16)
+#define BIT_PDNINT_EN_8814B BIT(7)
+#define BIT_RON_INT_EN_8814B BIT(6)
+#define BIT_SPS_OCP_INT_EN_8814B BIT(5)
+#define BIT_GPIO15_0_INT_EN_8814B BIT(0)
+
+/* 2 REG_HSISR_8814B */
+#define BIT_GPIOF_INT_8814B BIT(31)
+#define BIT_GPIOE_INT_8814B BIT(30)
+#define BIT_GPIOD_INT_8814B BIT(29)
+#define BIT_GPIOC_INT_8814B BIT(28)
+#define BIT_GPIOB_INT_8814B BIT(27)
+#define BIT_GPIOA_INT_8814B BIT(26)
+#define BIT_GPIO9_INT_8814B BIT(25)
+#define BIT_GPIO8_INT_8814B BIT(24)
+#define BIT_GPIO7_INT_8814B BIT(23)
+#define BIT_GPIO6_INT_8814B BIT(22)
+#define BIT_GPIO5_INT_8814B BIT(21)
+#define BIT_GPIO4_INT_8814B BIT(20)
+#define BIT_GPIO3_INT_8814B BIT(19)
+#define BIT_GPIO2_INT_V1_8814B BIT(18)
+#define BIT_GPIO1_INT_8814B BIT(17)
+#define BIT_GPIO0_INT_8814B BIT(16)
+#define BIT_PDNINT_8814B BIT(7)
+#define BIT_RON_INT_8814B BIT(6)
+#define BIT_SPS_OCP_INT_8814B BIT(5)
+#define BIT_GPIO15_0_INT_8814B BIT(0)
+
+/* 2 REG_GPIO_EXT_CTRL_8814B */
+
+#define BIT_SHIFT_GPIO_MOD_15_TO_8_8814B 24
+#define BIT_MASK_GPIO_MOD_15_TO_8_8814B 0xff
+#define BIT_GPIO_MOD_15_TO_8_8814B(x)                                          \
+	(((x) & BIT_MASK_GPIO_MOD_15_TO_8_8814B)                               \
+	 << BIT_SHIFT_GPIO_MOD_15_TO_8_8814B)
+#define BITS_GPIO_MOD_15_TO_8_8814B                                            \
+	(BIT_MASK_GPIO_MOD_15_TO_8_8814B << BIT_SHIFT_GPIO_MOD_15_TO_8_8814B)
+#define BIT_CLEAR_GPIO_MOD_15_TO_8_8814B(x)                                    \
+	((x) & (~BITS_GPIO_MOD_15_TO_8_8814B))
+#define BIT_GET_GPIO_MOD_15_TO_8_8814B(x)                                      \
+	(((x) >> BIT_SHIFT_GPIO_MOD_15_TO_8_8814B) &                           \
+	 BIT_MASK_GPIO_MOD_15_TO_8_8814B)
+#define BIT_SET_GPIO_MOD_15_TO_8_8814B(x, v)                                   \
+	(BIT_CLEAR_GPIO_MOD_15_TO_8_8814B(x) | BIT_GPIO_MOD_15_TO_8_8814B(v))
+
+#define BIT_SHIFT_GPIO_IO_SEL_15_TO_8_8814B 16
+#define BIT_MASK_GPIO_IO_SEL_15_TO_8_8814B 0xff
+#define BIT_GPIO_IO_SEL_15_TO_8_8814B(x)                                       \
+	(((x) & BIT_MASK_GPIO_IO_SEL_15_TO_8_8814B)                            \
+	 << BIT_SHIFT_GPIO_IO_SEL_15_TO_8_8814B)
+#define BITS_GPIO_IO_SEL_15_TO_8_8814B                                         \
+	(BIT_MASK_GPIO_IO_SEL_15_TO_8_8814B                                    \
+	 << BIT_SHIFT_GPIO_IO_SEL_15_TO_8_8814B)
+#define BIT_CLEAR_GPIO_IO_SEL_15_TO_8_8814B(x)                                 \
+	((x) & (~BITS_GPIO_IO_SEL_15_TO_8_8814B))
+#define BIT_GET_GPIO_IO_SEL_15_TO_8_8814B(x)                                   \
+	(((x) >> BIT_SHIFT_GPIO_IO_SEL_15_TO_8_8814B) &                        \
+	 BIT_MASK_GPIO_IO_SEL_15_TO_8_8814B)
+#define BIT_SET_GPIO_IO_SEL_15_TO_8_8814B(x, v)                                \
+	(BIT_CLEAR_GPIO_IO_SEL_15_TO_8_8814B(x) |                              \
+	 BIT_GPIO_IO_SEL_15_TO_8_8814B(v))
+
+#define BIT_SHIFT_GPIO_OUT_15_TO_8_8814B 8
+#define BIT_MASK_GPIO_OUT_15_TO_8_8814B 0xff
+#define BIT_GPIO_OUT_15_TO_8_8814B(x)                                          \
+	(((x) & BIT_MASK_GPIO_OUT_15_TO_8_8814B)                               \
+	 << BIT_SHIFT_GPIO_OUT_15_TO_8_8814B)
+#define BITS_GPIO_OUT_15_TO_8_8814B                                            \
+	(BIT_MASK_GPIO_OUT_15_TO_8_8814B << BIT_SHIFT_GPIO_OUT_15_TO_8_8814B)
+#define BIT_CLEAR_GPIO_OUT_15_TO_8_8814B(x)                                    \
+	((x) & (~BITS_GPIO_OUT_15_TO_8_8814B))
+#define BIT_GET_GPIO_OUT_15_TO_8_8814B(x)                                      \
+	(((x) >> BIT_SHIFT_GPIO_OUT_15_TO_8_8814B) &                           \
+	 BIT_MASK_GPIO_OUT_15_TO_8_8814B)
+#define BIT_SET_GPIO_OUT_15_TO_8_8814B(x, v)                                   \
+	(BIT_CLEAR_GPIO_OUT_15_TO_8_8814B(x) | BIT_GPIO_OUT_15_TO_8_8814B(v))
+
+#define BIT_SHIFT_GPIO_IN_15_TO_8_8814B 0
+#define BIT_MASK_GPIO_IN_15_TO_8_8814B 0xff
+#define BIT_GPIO_IN_15_TO_8_8814B(x)                                           \
+	(((x) & BIT_MASK_GPIO_IN_15_TO_8_8814B)                                \
+	 << BIT_SHIFT_GPIO_IN_15_TO_8_8814B)
+#define BITS_GPIO_IN_15_TO_8_8814B                                             \
+	(BIT_MASK_GPIO_IN_15_TO_8_8814B << BIT_SHIFT_GPIO_IN_15_TO_8_8814B)
+#define BIT_CLEAR_GPIO_IN_15_TO_8_8814B(x) ((x) & (~BITS_GPIO_IN_15_TO_8_8814B))
+#define BIT_GET_GPIO_IN_15_TO_8_8814B(x)                                       \
+	(((x) >> BIT_SHIFT_GPIO_IN_15_TO_8_8814B) &                            \
+	 BIT_MASK_GPIO_IN_15_TO_8_8814B)
+#define BIT_SET_GPIO_IN_15_TO_8_8814B(x, v)                                    \
+	(BIT_CLEAR_GPIO_IN_15_TO_8_8814B(x) | BIT_GPIO_IN_15_TO_8_8814B(v))
+
+/* 2 REG_PAD_CTRL1_8814B */
+#define BIT_DATA_CPU_JTAG_8814B BIT(30)
+#define BIT_PAPE_WLBT_SEL_8814B BIT(29)
+#define BIT_LNAON_WLBT_SEL_8814B BIT(28)
+#define BIT_BTGP_GPG3_FEN_8814B BIT(26)
+#define BIT_BTGP_GPG2_FEN_8814B BIT(25)
+#define BIT_BTGP_JTAG_EN_8814B BIT(24)
+#define BIT_XTAL_CLK_EXTARNAL_EN_8814B BIT(23)
+#define BIT_BTGP_UART0_EN_8814B BIT(22)
+#define BIT_BTGP_UART1_EN_8814B BIT(21)
+#define BIT_BTGP_SPI_EN_8814B BIT(20)
+#define BIT_BTGP_GPIO_E2_8814B BIT(19)
+#define BIT_BTGP_GPIO_EN_8814B BIT(18)
+
+#define BIT_SHIFT_BTGP_GPIO_SL_8814B 16
+#define BIT_MASK_BTGP_GPIO_SL_8814B 0x3
+#define BIT_BTGP_GPIO_SL_8814B(x)                                              \
+	(((x) & BIT_MASK_BTGP_GPIO_SL_8814B) << BIT_SHIFT_BTGP_GPIO_SL_8814B)
+#define BITS_BTGP_GPIO_SL_8814B                                                \
+	(BIT_MASK_BTGP_GPIO_SL_8814B << BIT_SHIFT_BTGP_GPIO_SL_8814B)
+#define BIT_CLEAR_BTGP_GPIO_SL_8814B(x) ((x) & (~BITS_BTGP_GPIO_SL_8814B))
+#define BIT_GET_BTGP_GPIO_SL_8814B(x)                                          \
+	(((x) >> BIT_SHIFT_BTGP_GPIO_SL_8814B) & BIT_MASK_BTGP_GPIO_SL_8814B)
+#define BIT_SET_BTGP_GPIO_SL_8814B(x, v)                                       \
+	(BIT_CLEAR_BTGP_GPIO_SL_8814B(x) | BIT_BTGP_GPIO_SL_8814B(v))
+
+#define BIT_WL_JTAG_8814B BIT(15)
+#define BIT_PAD_SDIO_SR_8814B BIT(14)
+#define BIT_GPIO14_OUTPUT_PL_8814B BIT(13)
+#define BIT_HOST_WAKE_PAD_PULL_EN_8814B BIT(12)
+#define BIT_HOST_WAKE_PAD_SL_8814B BIT(11)
+#define BIT_SW_LNAON_G_SEL_DATA_8814B BIT(8)
+#define BIT_SW_LNAON_A_SEL_DATA_8814B BIT(7)
+#define BIT_SW_PAPE_G_SEL_DATA_8814B BIT(4)
+#define BIT_SW_PAPE_A_SEL_DATA_8814B BIT(3)
+#define BIT_SW_DPDT_SEL_DATA_8814B BIT(0)
+
+/* 2 REG_WL_BT_PWR_CTRL_8814B */
+#define BIT_ISO_BD2PP_8814B BIT(31)
+#define BIT_LDOV12B_EN_8814B BIT(30)
+#define BIT_CKEN_BTGPS_8814B BIT(29)
+#define BIT_FEN_BTGPS_8814B BIT(28)
+#define BIT_BTCPU_BOOTSEL_8814B BIT(27)
+#define BIT_SPI_SPEEDUP_8814B BIT(26)
+#define BIT_BT_SUS_8814B BIT(25)
+#define BIT_DEVWAKE_PAD_TYPE_SEL_8814B BIT(24)
+#define BIT_CLKREQ_PAD_TYPE_SEL_8814B BIT(23)
+#define BIT_ISO_BTPON2PP_8814B BIT(22)
+#define BIT_BTCOEX_CMD_8814B BIT(21)
+#define BIT_BT_UART_INTF_8814B BIT(20)
+#define BIT_BT_HWROF_EN_8814B BIT(19)
+#define BIT_BT_FUNC_EN_8814B BIT(18)
+#define BIT_BT_HWPDN_SL_8814B BIT(17)
+#define BIT_BT_DISN_EN_8814B BIT(16)
+#define BIT_BT_PDN_PULL_EN_8814B BIT(15)
+#define BIT_WL_PDN_PULL_EN_8814B BIT(14)
+#define BIT_EXTERNAL_REQUEST_PL_8814B BIT(13)
+#define BIT_GPIO0_2_3_PULL_LOW_EN_8814B BIT(12)
+#define BIT_ISO_BA2PP_8814B BIT(11)
+#define BIT_BT_AFE_LDO_EN_8814B BIT(10)
+#define BIT_BT_AFE_PLL_EN_8814B BIT(9)
+#define BIT_BT_DIG_CLK_EN_8814B BIT(8)
+#define BIT_UART_BRIDGE_8814B BIT(7)
+#define BIT_OSC32K_CTRL_SEL_8814B BIT(6)
+#define BIT_WL_DRV_EXIST_IDX_8814B BIT(5)
+#define BIT_DOP_EHPAD_8814B BIT(4)
+#define BIT_WL_HWROF_EN_8814B BIT(3)
+#define BIT_WL_FUNC_EN_8814B BIT(2)
+#define BIT_WL_HWPDN_SL_8814B BIT(1)
+#define BIT_WL_HWPDN_EN_8814B BIT(0)
+
+/* 2 REG_SDM_DEBUG_8814B */
+#define BIT_BT_WAKE_DEV_EN_V1_8814B BIT(19)
+#define BIT_BT_WAKE_HST_EN_V1_8814B BIT(18)
+#define BIT_BT_WAKE_HST_PL_V1_8814B BIT(17)
+#define BIT_BT_CLKREQ_EN_V1_8814B BIT(16)
+
+#define BIT_SHIFT_WLCLK_PHASE_8814B 0
+#define BIT_MASK_WLCLK_PHASE_8814B 0x1f
+#define BIT_WLCLK_PHASE_8814B(x)                                               \
+	(((x) & BIT_MASK_WLCLK_PHASE_8814B) << BIT_SHIFT_WLCLK_PHASE_8814B)
+#define BITS_WLCLK_PHASE_8814B                                                 \
+	(BIT_MASK_WLCLK_PHASE_8814B << BIT_SHIFT_WLCLK_PHASE_8814B)
+#define BIT_CLEAR_WLCLK_PHASE_8814B(x) ((x) & (~BITS_WLCLK_PHASE_8814B))
+#define BIT_GET_WLCLK_PHASE_8814B(x)                                           \
+	(((x) >> BIT_SHIFT_WLCLK_PHASE_8814B) & BIT_MASK_WLCLK_PHASE_8814B)
+#define BIT_SET_WLCLK_PHASE_8814B(x, v)                                        \
+	(BIT_CLEAR_WLCLK_PHASE_8814B(x) | BIT_WLCLK_PHASE_8814B(v))
+
+/* 2 REG_SYS_SDIO_CTRL_8814B */
+#define BIT_DBG_GNT_WL_BT_8814B BIT(27)
+#define BIT_LTE_MUX_CTRL_PATH_8814B BIT(26)
+#define BIT_LTE_COEX_UART_8814B BIT(25)
+#define BIT_3W_LTE_WL_GPIO_8814B BIT(24)
+#define BIT_SDIO_INT_POLARITY_8814B BIT(19)
+#define BIT_SDIO_INT_8814B BIT(18)
+#define BIT_SDIO_OFF_EN_8814B BIT(17)
+#define BIT_SDIO_ON_EN_8814B BIT(16)
+#define BIT_PCIE_WAIT_TIMEOUT_EVENT_8814B BIT(10)
+#define BIT_PCIE_WAIT_TIME_8814B BIT(9)
+#define BIT_MPCIE_REFCLK_XTAL_SEL_8814B BIT(8)
+#define BIT_BT_CLKREQ_EN_8814B BIT(6)
+
+#define BIT_SHIFT_USB_CKREF_CML_R_8814B 4
+#define BIT_MASK_USB_CKREF_CML_R_8814B 0x3
+#define BIT_USB_CKREF_CML_R_8814B(x)                                           \
+	(((x) & BIT_MASK_USB_CKREF_CML_R_8814B)                                \
+	 << BIT_SHIFT_USB_CKREF_CML_R_8814B)
+#define BITS_USB_CKREF_CML_R_8814B                                             \
+	(BIT_MASK_USB_CKREF_CML_R_8814B << BIT_SHIFT_USB_CKREF_CML_R_8814B)
+#define BIT_CLEAR_USB_CKREF_CML_R_8814B(x) ((x) & (~BITS_USB_CKREF_CML_R_8814B))
+#define BIT_GET_USB_CKREF_CML_R_8814B(x)                                       \
+	(((x) >> BIT_SHIFT_USB_CKREF_CML_R_8814B) &                            \
+	 BIT_MASK_USB_CKREF_CML_R_8814B)
+#define BIT_SET_USB_CKREF_CML_R_8814B(x, v)                                    \
+	(BIT_CLEAR_USB_CKREF_CML_R_8814B(x) | BIT_USB_CKREF_CML_R_8814B(v))
+
+#define BIT_SHIFT_USB_CKREF_D2S_I_8814B 2
+#define BIT_MASK_USB_CKREF_D2S_I_8814B 0x3
+#define BIT_USB_CKREF_D2S_I_8814B(x)                                           \
+	(((x) & BIT_MASK_USB_CKREF_D2S_I_8814B)                                \
+	 << BIT_SHIFT_USB_CKREF_D2S_I_8814B)
+#define BITS_USB_CKREF_D2S_I_8814B                                             \
+	(BIT_MASK_USB_CKREF_D2S_I_8814B << BIT_SHIFT_USB_CKREF_D2S_I_8814B)
+#define BIT_CLEAR_USB_CKREF_D2S_I_8814B(x) ((x) & (~BITS_USB_CKREF_D2S_I_8814B))
+#define BIT_GET_USB_CKREF_D2S_I_8814B(x)                                       \
+	(((x) >> BIT_SHIFT_USB_CKREF_D2S_I_8814B) &                            \
+	 BIT_MASK_USB_CKREF_D2S_I_8814B)
+#define BIT_SET_USB_CKREF_D2S_I_8814B(x, v)                                    \
+	(BIT_CLEAR_USB_CKREF_D2S_I_8814B(x) | BIT_USB_CKREF_D2S_I_8814B(v))
+
+#define BIT_RES_USB_MASS_STORAGE_DESC_8814B BIT(1)
+#define BIT_USB_WAIT_TIME_8814B BIT(0)
+
+/* 2 REG_HCI_OPT_CTRL_8814B */
+
+#define BIT_SHIFT_TSFT_SEL_8814B 29
+#define BIT_MASK_TSFT_SEL_8814B 0x7
+#define BIT_TSFT_SEL_8814B(x)                                                  \
+	(((x) & BIT_MASK_TSFT_SEL_8814B) << BIT_SHIFT_TSFT_SEL_8814B)
+#define BITS_TSFT_SEL_8814B                                                    \
+	(BIT_MASK_TSFT_SEL_8814B << BIT_SHIFT_TSFT_SEL_8814B)
+#define BIT_CLEAR_TSFT_SEL_8814B(x) ((x) & (~BITS_TSFT_SEL_8814B))
+#define BIT_GET_TSFT_SEL_8814B(x)                                              \
+	(((x) >> BIT_SHIFT_TSFT_SEL_8814B) & BIT_MASK_TSFT_SEL_8814B)
+#define BIT_SET_TSFT_SEL_8814B(x, v)                                           \
+	(BIT_CLEAR_TSFT_SEL_8814B(x) | BIT_TSFT_SEL_8814B(v))
+
+#define BIT_TSFT_BAND_SEL_8814B BIT(28)
+#define BIT_USB_HOST_PWR_OFF_EN_8814B BIT(12)
+#define BIT_SYM_LPS_BLOCK_EN_8814B BIT(11)
+#define BIT_USB_LPM_ACT_EN_8814B BIT(10)
+#define BIT_USB_LPM_NY_8814B BIT(9)
+#define BIT_USB_SUS_DIS_8814B BIT(8)
+
+#define BIT_SHIFT_SDIO_PAD_E_8814B 5
+#define BIT_MASK_SDIO_PAD_E_8814B 0x7
+#define BIT_SDIO_PAD_E_8814B(x)                                                \
+	(((x) & BIT_MASK_SDIO_PAD_E_8814B) << BIT_SHIFT_SDIO_PAD_E_8814B)
+#define BITS_SDIO_PAD_E_8814B                                                  \
+	(BIT_MASK_SDIO_PAD_E_8814B << BIT_SHIFT_SDIO_PAD_E_8814B)
+#define BIT_CLEAR_SDIO_PAD_E_8814B(x) ((x) & (~BITS_SDIO_PAD_E_8814B))
+#define BIT_GET_SDIO_PAD_E_8814B(x)                                            \
+	(((x) >> BIT_SHIFT_SDIO_PAD_E_8814B) & BIT_MASK_SDIO_PAD_E_8814B)
+#define BIT_SET_SDIO_PAD_E_8814B(x, v)                                         \
+	(BIT_CLEAR_SDIO_PAD_E_8814B(x) | BIT_SDIO_PAD_E_8814B(v))
+
+#define BIT_USB_LPPLL_EN_8814B BIT(4)
+#define BIT_ROP_SW15_8814B BIT(2)
+#define BIT_PCI_CKRDY_OPT_8814B BIT(1)
+#define BIT_PCI_VAUX_EN_8814B BIT(0)
+
+/* 2 REG_AFE_CTRL4_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_LDO_SWR_CTRL_8814B */
+#define BIT_ZCD_HW_AUTO_EN_8814B BIT(27)
+#define BIT_ZCD_REGSEL_8814B BIT(26)
+
+#define BIT_SHIFT_AUTO_ZCD_IN_CODE_8814B 21
+#define BIT_MASK_AUTO_ZCD_IN_CODE_8814B 0x1f
+#define BIT_AUTO_ZCD_IN_CODE_8814B(x)                                          \
+	(((x) & BIT_MASK_AUTO_ZCD_IN_CODE_8814B)                               \
+	 << BIT_SHIFT_AUTO_ZCD_IN_CODE_8814B)
+#define BITS_AUTO_ZCD_IN_CODE_8814B                                            \
+	(BIT_MASK_AUTO_ZCD_IN_CODE_8814B << BIT_SHIFT_AUTO_ZCD_IN_CODE_8814B)
+#define BIT_CLEAR_AUTO_ZCD_IN_CODE_8814B(x)                                    \
+	((x) & (~BITS_AUTO_ZCD_IN_CODE_8814B))
+#define BIT_GET_AUTO_ZCD_IN_CODE_8814B(x)                                      \
+	(((x) >> BIT_SHIFT_AUTO_ZCD_IN_CODE_8814B) &                           \
+	 BIT_MASK_AUTO_ZCD_IN_CODE_8814B)
+#define BIT_SET_AUTO_ZCD_IN_CODE_8814B(x, v)                                   \
+	(BIT_CLEAR_AUTO_ZCD_IN_CODE_8814B(x) | BIT_AUTO_ZCD_IN_CODE_8814B(v))
+
+#define BIT_SHIFT_ZCD_CODE_IN_L_8814B 16
+#define BIT_MASK_ZCD_CODE_IN_L_8814B 0x1f
+#define BIT_ZCD_CODE_IN_L_8814B(x)                                             \
+	(((x) & BIT_MASK_ZCD_CODE_IN_L_8814B) << BIT_SHIFT_ZCD_CODE_IN_L_8814B)
+#define BITS_ZCD_CODE_IN_L_8814B                                               \
+	(BIT_MASK_ZCD_CODE_IN_L_8814B << BIT_SHIFT_ZCD_CODE_IN_L_8814B)
+#define BIT_CLEAR_ZCD_CODE_IN_L_8814B(x) ((x) & (~BITS_ZCD_CODE_IN_L_8814B))
+#define BIT_GET_ZCD_CODE_IN_L_8814B(x)                                         \
+	(((x) >> BIT_SHIFT_ZCD_CODE_IN_L_8814B) & BIT_MASK_ZCD_CODE_IN_L_8814B)
+#define BIT_SET_ZCD_CODE_IN_L_8814B(x, v)                                      \
+	(BIT_CLEAR_ZCD_CODE_IN_L_8814B(x) | BIT_ZCD_CODE_IN_L_8814B(v))
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_MCUFW_CTRL_8814B */
+
+#define BIT_SHIFT_RPWM_8814B 24
+#define BIT_MASK_RPWM_8814B 0xff
+#define BIT_RPWM_8814B(x) (((x) & BIT_MASK_RPWM_8814B) << BIT_SHIFT_RPWM_8814B)
+#define BITS_RPWM_8814B (BIT_MASK_RPWM_8814B << BIT_SHIFT_RPWM_8814B)
+#define BIT_CLEAR_RPWM_8814B(x) ((x) & (~BITS_RPWM_8814B))
+#define BIT_GET_RPWM_8814B(x)                                                  \
+	(((x) >> BIT_SHIFT_RPWM_8814B) & BIT_MASK_RPWM_8814B)
+#define BIT_SET_RPWM_8814B(x, v) (BIT_CLEAR_RPWM_8814B(x) | BIT_RPWM_8814B(v))
+
+#define BIT_ANA_PORT_EN_8814B BIT(22)
+#define BIT_MAC_PORT_EN_8814B BIT(21)
+#define BIT_BOOT_FSPI_EN_8814B BIT(20)
+#define BIT_ROM_DLEN_8814B BIT(19)
+
+#define BIT_SHIFT_ROM_PGE_8814B 16
+#define BIT_MASK_ROM_PGE_8814B 0x7
+#define BIT_ROM_PGE_8814B(x)                                                   \
+	(((x) & BIT_MASK_ROM_PGE_8814B) << BIT_SHIFT_ROM_PGE_8814B)
+#define BITS_ROM_PGE_8814B (BIT_MASK_ROM_PGE_8814B << BIT_SHIFT_ROM_PGE_8814B)
+#define BIT_CLEAR_ROM_PGE_8814B(x) ((x) & (~BITS_ROM_PGE_8814B))
+#define BIT_GET_ROM_PGE_8814B(x)                                               \
+	(((x) >> BIT_SHIFT_ROM_PGE_8814B) & BIT_MASK_ROM_PGE_8814B)
+#define BIT_SET_ROM_PGE_8814B(x, v)                                            \
+	(BIT_CLEAR_ROM_PGE_8814B(x) | BIT_ROM_PGE_8814B(v))
+
+#define BIT_FW_INIT_RDY_8814B BIT(15)
+#define BIT_FW_DW_RDY_8814B BIT(14)
+
+#define BIT_SHIFT_CPU_CLK_SEL_8814B 12
+#define BIT_MASK_CPU_CLK_SEL_8814B 0x3
+#define BIT_CPU_CLK_SEL_8814B(x)                                               \
+	(((x) & BIT_MASK_CPU_CLK_SEL_8814B) << BIT_SHIFT_CPU_CLK_SEL_8814B)
+#define BITS_CPU_CLK_SEL_8814B                                                 \
+	(BIT_MASK_CPU_CLK_SEL_8814B << BIT_SHIFT_CPU_CLK_SEL_8814B)
+#define BIT_CLEAR_CPU_CLK_SEL_8814B(x) ((x) & (~BITS_CPU_CLK_SEL_8814B))
+#define BIT_GET_CPU_CLK_SEL_8814B(x)                                           \
+	(((x) >> BIT_SHIFT_CPU_CLK_SEL_8814B) & BIT_MASK_CPU_CLK_SEL_8814B)
+#define BIT_SET_CPU_CLK_SEL_8814B(x, v)                                        \
+	(BIT_CLEAR_CPU_CLK_SEL_8814B(x) | BIT_CPU_CLK_SEL_8814B(v))
+
+#define BIT_CCLK_CHG_MASK_8814B BIT(11)
+#define BIT_EMEM__TXBUF_CHKSUM_OK_8814B BIT(10)
+#define BIT_EMEM_TXBUF_DW_RDY_8814B BIT(9)
+#define BIT_EMEM_CHKSUM_OK_8814B BIT(8)
+#define BIT_EMEM_DW_OK_8814B BIT(7)
+#define BIT_DMEM_CHKSUM_OK_8814B BIT(6)
+#define BIT_DMEM_DW_OK_8814B BIT(5)
+#define BIT_IMEM_CHKSUM_OK_8814B BIT(4)
+#define BIT_IMEM_DW_OK_8814B BIT(3)
+#define BIT_IMEM_BOOT_LOAD_CHKSUM_OK_8814B BIT(2)
+#define BIT_IMEM_BOOT_LOAD_DW_OK_8814B BIT(1)
+#define BIT_MCUFWDL_EN_8814B BIT(0)
+
+/* 2 REG_MCU_TST_CFG_8814B */
+
+#define BIT_SHIFT_C2H_MSG_8814B 0
+#define BIT_MASK_C2H_MSG_8814B 0xffff
+#define BIT_C2H_MSG_8814B(x)                                                   \
+	(((x) & BIT_MASK_C2H_MSG_8814B) << BIT_SHIFT_C2H_MSG_8814B)
+#define BITS_C2H_MSG_8814B (BIT_MASK_C2H_MSG_8814B << BIT_SHIFT_C2H_MSG_8814B)
+#define BIT_CLEAR_C2H_MSG_8814B(x) ((x) & (~BITS_C2H_MSG_8814B))
+#define BIT_GET_C2H_MSG_8814B(x)                                               \
+	(((x) >> BIT_SHIFT_C2H_MSG_8814B) & BIT_MASK_C2H_MSG_8814B)
+#define BIT_SET_C2H_MSG_8814B(x, v)                                            \
+	(BIT_CLEAR_C2H_MSG_8814B(x) | BIT_C2H_MSG_8814B(v))
+
+/* 2 REG_HMEBOX_E0_E1_8814B */
+
+#define BIT_SHIFT_HOST_MSG_E1_8814B 16
+#define BIT_MASK_HOST_MSG_E1_8814B 0xffff
+#define BIT_HOST_MSG_E1_8814B(x)                                               \
+	(((x) & BIT_MASK_HOST_MSG_E1_8814B) << BIT_SHIFT_HOST_MSG_E1_8814B)
+#define BITS_HOST_MSG_E1_8814B                                                 \
+	(BIT_MASK_HOST_MSG_E1_8814B << BIT_SHIFT_HOST_MSG_E1_8814B)
+#define BIT_CLEAR_HOST_MSG_E1_8814B(x) ((x) & (~BITS_HOST_MSG_E1_8814B))
+#define BIT_GET_HOST_MSG_E1_8814B(x)                                           \
+	(((x) >> BIT_SHIFT_HOST_MSG_E1_8814B) & BIT_MASK_HOST_MSG_E1_8814B)
+#define BIT_SET_HOST_MSG_E1_8814B(x, v)                                        \
+	(BIT_CLEAR_HOST_MSG_E1_8814B(x) | BIT_HOST_MSG_E1_8814B(v))
+
+#define BIT_SHIFT_HOST_MSG_E0_8814B 0
+#define BIT_MASK_HOST_MSG_E0_8814B 0xffff
+#define BIT_HOST_MSG_E0_8814B(x)                                               \
+	(((x) & BIT_MASK_HOST_MSG_E0_8814B) << BIT_SHIFT_HOST_MSG_E0_8814B)
+#define BITS_HOST_MSG_E0_8814B                                                 \
+	(BIT_MASK_HOST_MSG_E0_8814B << BIT_SHIFT_HOST_MSG_E0_8814B)
+#define BIT_CLEAR_HOST_MSG_E0_8814B(x) ((x) & (~BITS_HOST_MSG_E0_8814B))
+#define BIT_GET_HOST_MSG_E0_8814B(x)                                           \
+	(((x) >> BIT_SHIFT_HOST_MSG_E0_8814B) & BIT_MASK_HOST_MSG_E0_8814B)
+#define BIT_SET_HOST_MSG_E0_8814B(x, v)                                        \
+	(BIT_CLEAR_HOST_MSG_E0_8814B(x) | BIT_HOST_MSG_E0_8814B(v))
+
+/* 2 REG_HMEBOX_E2_E3_8814B */
+
+#define BIT_SHIFT_HOST_MSG_E3_8814B 16
+#define BIT_MASK_HOST_MSG_E3_8814B 0xffff
+#define BIT_HOST_MSG_E3_8814B(x)                                               \
+	(((x) & BIT_MASK_HOST_MSG_E3_8814B) << BIT_SHIFT_HOST_MSG_E3_8814B)
+#define BITS_HOST_MSG_E3_8814B                                                 \
+	(BIT_MASK_HOST_MSG_E3_8814B << BIT_SHIFT_HOST_MSG_E3_8814B)
+#define BIT_CLEAR_HOST_MSG_E3_8814B(x) ((x) & (~BITS_HOST_MSG_E3_8814B))
+#define BIT_GET_HOST_MSG_E3_8814B(x)                                           \
+	(((x) >> BIT_SHIFT_HOST_MSG_E3_8814B) & BIT_MASK_HOST_MSG_E3_8814B)
+#define BIT_SET_HOST_MSG_E3_8814B(x, v)                                        \
+	(BIT_CLEAR_HOST_MSG_E3_8814B(x) | BIT_HOST_MSG_E3_8814B(v))
+
+#define BIT_SHIFT_HOST_MSG_E2_8814B 0
+#define BIT_MASK_HOST_MSG_E2_8814B 0xffff
+#define BIT_HOST_MSG_E2_8814B(x)                                               \
+	(((x) & BIT_MASK_HOST_MSG_E2_8814B) << BIT_SHIFT_HOST_MSG_E2_8814B)
+#define BITS_HOST_MSG_E2_8814B                                                 \
+	(BIT_MASK_HOST_MSG_E2_8814B << BIT_SHIFT_HOST_MSG_E2_8814B)
+#define BIT_CLEAR_HOST_MSG_E2_8814B(x) ((x) & (~BITS_HOST_MSG_E2_8814B))
+#define BIT_GET_HOST_MSG_E2_8814B(x)                                           \
+	(((x) >> BIT_SHIFT_HOST_MSG_E2_8814B) & BIT_MASK_HOST_MSG_E2_8814B)
+#define BIT_SET_HOST_MSG_E2_8814B(x, v)                                        \
+	(BIT_CLEAR_HOST_MSG_E2_8814B(x) | BIT_HOST_MSG_E2_8814B(v))
+
+/* 2 REG_WLLPS_CTRL_8814B */
+#define BIT_WLLPSOP_EABM_8814B BIT(31)
+#define BIT_WLLPSOP_ACKF_8814B BIT(30)
+#define BIT_WLLPSOP_DLDM_8814B BIT(29)
+#define BIT_WLLPSOP_ESWR_8814B BIT(28)
+#define BIT_WLLPSOP_PWMM_8814B BIT(27)
+#define BIT_WLLPSOP_EECK_8814B BIT(26)
+#define BIT_WLLPSOP_WLMACOFF_8814B BIT(25)
+#define BIT_WLLPSOP_EXTAL_8814B BIT(24)
+#define BIT_WL_SYNPON_VOLTSPDN_8814B BIT(23)
+#define BIT_WLLPSOP_WLBBOFF_8814B BIT(22)
+#define BIT_WLLPSOP_WLMEM_DS_8814B BIT(21)
+
+#define BIT_SHIFT_LPLDH12_VADJ_STEP_DN_8814B 12
+#define BIT_MASK_LPLDH12_VADJ_STEP_DN_8814B 0xf
+#define BIT_LPLDH12_VADJ_STEP_DN_8814B(x)                                      \
+	(((x) & BIT_MASK_LPLDH12_VADJ_STEP_DN_8814B)                           \
+	 << BIT_SHIFT_LPLDH12_VADJ_STEP_DN_8814B)
+#define BITS_LPLDH12_VADJ_STEP_DN_8814B                                        \
+	(BIT_MASK_LPLDH12_VADJ_STEP_DN_8814B                                   \
+	 << BIT_SHIFT_LPLDH12_VADJ_STEP_DN_8814B)
+#define BIT_CLEAR_LPLDH12_VADJ_STEP_DN_8814B(x)                                \
+	((x) & (~BITS_LPLDH12_VADJ_STEP_DN_8814B))
+#define BIT_GET_LPLDH12_VADJ_STEP_DN_8814B(x)                                  \
+	(((x) >> BIT_SHIFT_LPLDH12_VADJ_STEP_DN_8814B) &                       \
+	 BIT_MASK_LPLDH12_VADJ_STEP_DN_8814B)
+#define BIT_SET_LPLDH12_VADJ_STEP_DN_8814B(x, v)                               \
+	(BIT_CLEAR_LPLDH12_VADJ_STEP_DN_8814B(x) |                             \
+	 BIT_LPLDH12_VADJ_STEP_DN_8814B(v))
+
+#define BIT_SHIFT_V15ADJ_L1_STEP_DN_8814B 8
+#define BIT_MASK_V15ADJ_L1_STEP_DN_8814B 0x7
+#define BIT_V15ADJ_L1_STEP_DN_8814B(x)                                         \
+	(((x) & BIT_MASK_V15ADJ_L1_STEP_DN_8814B)                              \
+	 << BIT_SHIFT_V15ADJ_L1_STEP_DN_8814B)
+#define BITS_V15ADJ_L1_STEP_DN_8814B                                           \
+	(BIT_MASK_V15ADJ_L1_STEP_DN_8814B << BIT_SHIFT_V15ADJ_L1_STEP_DN_8814B)
+#define BIT_CLEAR_V15ADJ_L1_STEP_DN_8814B(x)                                   \
+	((x) & (~BITS_V15ADJ_L1_STEP_DN_8814B))
+#define BIT_GET_V15ADJ_L1_STEP_DN_8814B(x)                                     \
+	(((x) >> BIT_SHIFT_V15ADJ_L1_STEP_DN_8814B) &                          \
+	 BIT_MASK_V15ADJ_L1_STEP_DN_8814B)
+#define BIT_SET_V15ADJ_L1_STEP_DN_8814B(x, v)                                  \
+	(BIT_CLEAR_V15ADJ_L1_STEP_DN_8814B(x) | BIT_V15ADJ_L1_STEP_DN_8814B(v))
+
+#define BIT_REGU_32K_CLK_EN_8814B BIT(1)
+#define BIT_WL_LPS_EN_8814B BIT(0)
+
+/* 2 REG_AFE_CTRL5_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_GPIO_DEBOUNCE_CTRL_8814B */
+#define BIT_WLGP_DBC1EN_8814B BIT(15)
+
+#define BIT_SHIFT_WLGP_DBC1_8814B 8
+#define BIT_MASK_WLGP_DBC1_8814B 0xf
+#define BIT_WLGP_DBC1_8814B(x)                                                 \
+	(((x) & BIT_MASK_WLGP_DBC1_8814B) << BIT_SHIFT_WLGP_DBC1_8814B)
+#define BITS_WLGP_DBC1_8814B                                                   \
+	(BIT_MASK_WLGP_DBC1_8814B << BIT_SHIFT_WLGP_DBC1_8814B)
+#define BIT_CLEAR_WLGP_DBC1_8814B(x) ((x) & (~BITS_WLGP_DBC1_8814B))
+#define BIT_GET_WLGP_DBC1_8814B(x)                                             \
+	(((x) >> BIT_SHIFT_WLGP_DBC1_8814B) & BIT_MASK_WLGP_DBC1_8814B)
+#define BIT_SET_WLGP_DBC1_8814B(x, v)                                          \
+	(BIT_CLEAR_WLGP_DBC1_8814B(x) | BIT_WLGP_DBC1_8814B(v))
+
+#define BIT_WLGP_DBC0EN_8814B BIT(7)
+
+#define BIT_SHIFT_WLGP_DBC0_8814B 0
+#define BIT_MASK_WLGP_DBC0_8814B 0xf
+#define BIT_WLGP_DBC0_8814B(x)                                                 \
+	(((x) & BIT_MASK_WLGP_DBC0_8814B) << BIT_SHIFT_WLGP_DBC0_8814B)
+#define BITS_WLGP_DBC0_8814B                                                   \
+	(BIT_MASK_WLGP_DBC0_8814B << BIT_SHIFT_WLGP_DBC0_8814B)
+#define BIT_CLEAR_WLGP_DBC0_8814B(x) ((x) & (~BITS_WLGP_DBC0_8814B))
+#define BIT_GET_WLGP_DBC0_8814B(x)                                             \
+	(((x) >> BIT_SHIFT_WLGP_DBC0_8814B) & BIT_MASK_WLGP_DBC0_8814B)
+#define BIT_SET_WLGP_DBC0_8814B(x, v)                                          \
+	(BIT_CLEAR_WLGP_DBC0_8814B(x) | BIT_WLGP_DBC0_8814B(v))
+
+/* 2 REG_RPWM2_8814B */
+
+#define BIT_SHIFT_RPWM2_8814B 16
+#define BIT_MASK_RPWM2_8814B 0xffff
+#define BIT_RPWM2_8814B(x)                                                     \
+	(((x) & BIT_MASK_RPWM2_8814B) << BIT_SHIFT_RPWM2_8814B)
+#define BITS_RPWM2_8814B (BIT_MASK_RPWM2_8814B << BIT_SHIFT_RPWM2_8814B)
+#define BIT_CLEAR_RPWM2_8814B(x) ((x) & (~BITS_RPWM2_8814B))
+#define BIT_GET_RPWM2_8814B(x)                                                 \
+	(((x) >> BIT_SHIFT_RPWM2_8814B) & BIT_MASK_RPWM2_8814B)
+#define BIT_SET_RPWM2_8814B(x, v)                                              \
+	(BIT_CLEAR_RPWM2_8814B(x) | BIT_RPWM2_8814B(v))
+
+/* 2 REG_SYSON_FSM_MON_8814B */
+
+#define BIT_SHIFT_FSM_MON_SEL_8814B 24
+#define BIT_MASK_FSM_MON_SEL_8814B 0x7
+#define BIT_FSM_MON_SEL_8814B(x)                                               \
+	(((x) & BIT_MASK_FSM_MON_SEL_8814B) << BIT_SHIFT_FSM_MON_SEL_8814B)
+#define BITS_FSM_MON_SEL_8814B                                                 \
+	(BIT_MASK_FSM_MON_SEL_8814B << BIT_SHIFT_FSM_MON_SEL_8814B)
+#define BIT_CLEAR_FSM_MON_SEL_8814B(x) ((x) & (~BITS_FSM_MON_SEL_8814B))
+#define BIT_GET_FSM_MON_SEL_8814B(x)                                           \
+	(((x) >> BIT_SHIFT_FSM_MON_SEL_8814B) & BIT_MASK_FSM_MON_SEL_8814B)
+#define BIT_SET_FSM_MON_SEL_8814B(x, v)                                        \
+	(BIT_CLEAR_FSM_MON_SEL_8814B(x) | BIT_FSM_MON_SEL_8814B(v))
+
+#define BIT_DOP_ELDO_8814B BIT(23)
+#define BIT_FSM_MON_UPD_8814B BIT(15)
+
+#define BIT_SHIFT_FSM_PAR_8814B 0
+#define BIT_MASK_FSM_PAR_8814B 0x7fff
+#define BIT_FSM_PAR_8814B(x)                                                   \
+	(((x) & BIT_MASK_FSM_PAR_8814B) << BIT_SHIFT_FSM_PAR_8814B)
+#define BITS_FSM_PAR_8814B (BIT_MASK_FSM_PAR_8814B << BIT_SHIFT_FSM_PAR_8814B)
+#define BIT_CLEAR_FSM_PAR_8814B(x) ((x) & (~BITS_FSM_PAR_8814B))
+#define BIT_GET_FSM_PAR_8814B(x)                                               \
+	(((x) >> BIT_SHIFT_FSM_PAR_8814B) & BIT_MASK_FSM_PAR_8814B)
+#define BIT_SET_FSM_PAR_8814B(x, v)                                            \
+	(BIT_CLEAR_FSM_PAR_8814B(x) | BIT_FSM_PAR_8814B(v))
+
+/* 2 REG_AFE_CTRL6_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_PMC_DBG_CTRL1_8814B */
+#define BIT_BT_INT_EN_8814B BIT(31)
+
+#define BIT_SHIFT_RD_WR_WIFI_BT_INFO_8814B 16
+#define BIT_MASK_RD_WR_WIFI_BT_INFO_8814B 0x7fff
+#define BIT_RD_WR_WIFI_BT_INFO_8814B(x)                                        \
+	(((x) & BIT_MASK_RD_WR_WIFI_BT_INFO_8814B)                             \
+	 << BIT_SHIFT_RD_WR_WIFI_BT_INFO_8814B)
+#define BITS_RD_WR_WIFI_BT_INFO_8814B                                          \
+	(BIT_MASK_RD_WR_WIFI_BT_INFO_8814B                                     \
+	 << BIT_SHIFT_RD_WR_WIFI_BT_INFO_8814B)
+#define BIT_CLEAR_RD_WR_WIFI_BT_INFO_8814B(x)                                  \
+	((x) & (~BITS_RD_WR_WIFI_BT_INFO_8814B))
+#define BIT_GET_RD_WR_WIFI_BT_INFO_8814B(x)                                    \
+	(((x) >> BIT_SHIFT_RD_WR_WIFI_BT_INFO_8814B) &                         \
+	 BIT_MASK_RD_WR_WIFI_BT_INFO_8814B)
+#define BIT_SET_RD_WR_WIFI_BT_INFO_8814B(x, v)                                 \
+	(BIT_CLEAR_RD_WR_WIFI_BT_INFO_8814B(x) |                               \
+	 BIT_RD_WR_WIFI_BT_INFO_8814B(v))
+
+#define BIT_PMC_WR_OVF_8814B BIT(8)
+
+#define BIT_SHIFT_WLPMC_ERRINT_8814B 0
+#define BIT_MASK_WLPMC_ERRINT_8814B 0xff
+#define BIT_WLPMC_ERRINT_8814B(x)                                              \
+	(((x) & BIT_MASK_WLPMC_ERRINT_8814B) << BIT_SHIFT_WLPMC_ERRINT_8814B)
+#define BITS_WLPMC_ERRINT_8814B                                                \
+	(BIT_MASK_WLPMC_ERRINT_8814B << BIT_SHIFT_WLPMC_ERRINT_8814B)
+#define BIT_CLEAR_WLPMC_ERRINT_8814B(x) ((x) & (~BITS_WLPMC_ERRINT_8814B))
+#define BIT_GET_WLPMC_ERRINT_8814B(x)                                          \
+	(((x) >> BIT_SHIFT_WLPMC_ERRINT_8814B) & BIT_MASK_WLPMC_ERRINT_8814B)
+#define BIT_SET_WLPMC_ERRINT_8814B(x, v)                                       \
+	(BIT_CLEAR_WLPMC_ERRINT_8814B(x) | BIT_WLPMC_ERRINT_8814B(v))
+
+/* 2 REG_AFE_CTRL7_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_HIMR0_8814B */
+#define BIT_PSTIMER_2_MSK_8814B BIT(31)
+#define BIT_PSTIMER_1_MSK_8814B BIT(30)
+#define BIT_PSTIMER_0_MSK_8814B BIT(29)
+#define BIT_GTINT4_MSK_8814B BIT(28)
+#define BIT_GTINT3_MSK_8814B BIT(27)
+#define BIT_TXBCN0ERR_MSK_8814B BIT(26)
+#define BIT_TXBCN0OK_MSK_8814B BIT(25)
+#define BIT_TSF_BIT32_TOGGLE_MSK_8814B BIT(24)
+#define BIT_TXDMA_START_INT_MSK_8814B BIT(23)
+#define BIT_TXDMA_STOP_INT_MSK_8814B BIT(22)
+#define BIT_HISR7_IND_MSK_8814B BIT(21)
+#define BIT_BCNDMAINT0_MSK_8814B BIT(20)
+#define BIT_HISR6_IND_MSK_8814B BIT(19)
+#define BIT_HISR5_IND_MSK_8814B BIT(18)
+#define BIT_HISR4_IND_MSK_8814B BIT(17)
+#define BIT_BCNDERR0_MSK_8814B BIT(16)
+#define BIT_HSISR_IND_ON_INT_MSK_8814B BIT(15)
+#define BIT_HISR3_IND_MSK_8814B BIT(14)
+#define BIT_HISR2_IND_MSK_8814B BIT(13)
+
+/* 2 REG_NOT_VALID_8814B */
+#define BIT_HISR1_IND_MSK_8814B BIT(11)
+#define BIT_C2HCMD_MSK_8814B BIT(10)
+#define BIT_CPWM2_MSK_8814B BIT(9)
+#define BIT_CPWM_MSK_8814B BIT(8)
+#define BIT_TXDMAOK_CHANNEL15_MSK_8814B BIT(7)
+#define BIT_TXDMAOK_CHANNEL14_MSK_8814B BIT(6)
+#define BIT_TXDMAOK_CHANNEL3_MSK_8814B BIT(5)
+#define BIT_TXDMAOK_CHANNEL2_MSK_8814B BIT(4)
+#define BIT_TXDMAOK_CHANNEL1_MSK_8814B BIT(3)
+#define BIT_TXDMAOK_CHANNEL0_MSK_8814B BIT(2)
+#define BIT_RDU_MSK_8814B BIT(1)
+#define BIT_RXOK_MSK_8814B BIT(0)
+
+/* 2 REG_HISR0_8814B */
+#define BIT_PSTIMER_2_8814B BIT(31)
+#define BIT_PSTIMER_1_8814B BIT(30)
+#define BIT_PSTIMER_0_8814B BIT(29)
+#define BIT_GTINT4_8814B BIT(28)
+#define BIT_GTINT3_8814B BIT(27)
+#define BIT_TXBCN0ERR_8814B BIT(26)
+#define BIT_TXBCN0OK_8814B BIT(25)
+#define BIT_TSF_BIT32_TOGGLE_8814B BIT(24)
+#define BIT_TXDMA_START_INT_8814B BIT(23)
+#define BIT_TXDMA_STOP_INT_8814B BIT(22)
+#define BIT_HISR7_IND_8814B BIT(21)
+#define BIT_BCNDMAINT0_8814B BIT(20)
+#define BIT_HISR6_IND_8814B BIT(19)
+#define BIT_HISR5_IND_8814B BIT(18)
+#define BIT_HISR4_IND_8814B BIT(17)
+#define BIT_BCNDERR0_8814B BIT(16)
+#define BIT_HSISR_IND_ON_INT_8814B BIT(15)
+#define BIT_HISR3_IND_8814B BIT(14)
+#define BIT_HISR2_IND_8814B BIT(13)
+
+/* 2 REG_NOT_VALID_8814B */
+#define BIT_HISR1_IND_8814B BIT(11)
+#define BIT_C2HCMD_8814B BIT(10)
+#define BIT_CPWM2_8814B BIT(9)
+#define BIT_CPWM_8814B BIT(8)
+#define BIT_TXDMAOK_CHANNEL15_8814B BIT(7)
+#define BIT_TXDMAOK_CHANNEL14_8814B BIT(6)
+#define BIT_TXDMAOK_CHANNEL3_8814B BIT(5)
+#define BIT_TXDMAOK_CHANNEL2_8814B BIT(4)
+#define BIT_TXDMAOK_CHANNEL1_8814B BIT(3)
+#define BIT_TXDMAOK_CHANNEL0_8814B BIT(2)
+#define BIT_RDU_8814B BIT(1)
+#define BIT_RXOK_8814B BIT(0)
+
+/* 2 REG_HIMR1_8814B */
+#define BIT_PRE_TX_ERR_INT_MSK_8814B BIT(31)
+#define BIT_TXFIFO_TH_INT_8814B BIT(30)
+#define BIT_BTON_STS_UPDATE_MASK_8814B BIT(29)
+#define BIT_BCNDMAINT7__MSK_8814B BIT(27)
+#define BIT_BCNDMAINT6__MSK_8814B BIT(26)
+#define BIT_BCNDMAINT5__MSK_8814B BIT(25)
+#define BIT_BCNDMAINT4__MSK_8814B BIT(24)
+#define BIT_BCNDMAINT3_MSK_8814B BIT(23)
+#define BIT_BCNDMAINT2_MSK_8814B BIT(22)
+#define BIT_BCNDMAINT1_MSK_8814B BIT(21)
+#define BIT_BCNDERR7_MSK_8814B BIT(20)
+#define BIT_BCNDERR6_MSK_8814B BIT(19)
+#define BIT_BCNDERR5_MSK_8814B BIT(18)
+#define BIT_BCNDERR4_MSK_8814B BIT(17)
+#define BIT_BCNDERR3_MSK_8814B BIT(16)
+#define BIT_BCNDERR2_MSK_8814B BIT(15)
+#define BIT_BCNDERR1_MSK_8814B BIT(14)
+#define BIT_ATIMEND__MSK_8814B BIT(12)
+#define BIT_TXERR_MSK_8814B BIT(11)
+#define BIT_RXERR_MSK_8814B BIT(10)
+#define BIT_TXFOVW_MSK_8814B BIT(9)
+#define BIT_FOVW_MSK_8814B BIT(8)
+#define BIT_CPU_MGQ_EARLY_INT_MSK_8814B BIT(6)
+#define BIT_CPU_MGQ_TXDONE_MSK_8814B BIT(5)
+#define BIT_PSTIMER_5_MSK_8814B BIT(4)
+#define BIT_PSTIMER_4_MSK_8814B BIT(3)
+#define BIT_PSTIMER_3_MSK_8814B BIT(2)
+#define BIT_CPUMGQ_TX_TIMER_MSK_8814B BIT(1)
+#define BIT_BB_STOPRX_INT_MSK_8814B BIT(0)
+
+/* 2 REG_HISR1_8814B */
+#define BIT_PRE_TX_ERR_INT_8814B BIT(31)
+#define BIT_TXFIFO_TH_INT_8814B BIT(30)
+#define BIT_BTON_STS_UPDATE_INT_8814B BIT(29)
+#define BIT_BCNDMAINT7_8814B BIT(27)
+#define BIT_BCNDMAINT6_8814B BIT(26)
+#define BIT_BCNDMAINT5_8814B BIT(25)
+#define BIT_BCNDMAINT4_8814B BIT(24)
+#define BIT_BCNDMAINT3_8814B BIT(23)
+#define BIT_BCNDMAINT2_8814B BIT(22)
+#define BIT_BCNDMAINT1_8814B BIT(21)
+#define BIT_BCNDERR7_8814B BIT(20)
+#define BIT_BCNDERR6_8814B BIT(19)
+#define BIT_BCNDERR5_8814B BIT(18)
+#define BIT_BCNDERR4_8814B BIT(17)
+#define BIT_BCNDERR3_8814B BIT(16)
+#define BIT_BCNDERR2_8814B BIT(15)
+#define BIT_BCNDERR1_8814B BIT(14)
+#define BIT_ATIMEND_8814B BIT(12)
+#define BIT_TXERR_INT_8814B BIT(11)
+#define BIT_RXERR_INT_8814B BIT(10)
+#define BIT_TXFOVW_8814B BIT(9)
+#define BIT_FOVW_8814B BIT(8)
+
+/* 2 REG_NOT_VALID_8814B */
+#define BIT_CPU_MGQ_EARLY_INT_8814B BIT(6)
+#define BIT_CPU_MGQ_TXDONE_8814B BIT(5)
+#define BIT_PSTIMER_5_8814B BIT(4)
+#define BIT_PSTIMER_4_8814B BIT(3)
+#define BIT_PSTIMER_3_8814B BIT(2)
+#define BIT_CPUMGQ_TX_TIMER_8814B BIT(1)
+#define BIT_BB_STOPRX_INT_8814B BIT(0)
+
+/* 2 REG_DBG_PORT_SEL_8814B */
+
+#define BIT_SHIFT_DEBUG_ST_8814B 0
+#define BIT_MASK_DEBUG_ST_8814B 0xffffffffL
+#define BIT_DEBUG_ST_8814B(x)                                                  \
+	(((x) & BIT_MASK_DEBUG_ST_8814B) << BIT_SHIFT_DEBUG_ST_8814B)
+#define BITS_DEBUG_ST_8814B                                                    \
+	(BIT_MASK_DEBUG_ST_8814B << BIT_SHIFT_DEBUG_ST_8814B)
+#define BIT_CLEAR_DEBUG_ST_8814B(x) ((x) & (~BITS_DEBUG_ST_8814B))
+#define BIT_GET_DEBUG_ST_8814B(x)                                              \
+	(((x) >> BIT_SHIFT_DEBUG_ST_8814B) & BIT_MASK_DEBUG_ST_8814B)
+#define BIT_SET_DEBUG_ST_8814B(x, v)                                           \
+	(BIT_CLEAR_DEBUG_ST_8814B(x) | BIT_DEBUG_ST_8814B(v))
+
+/* 2 REG_PAD_CTRL2_8814B */
+#define BIT_USB3_USB2_TRANSITION_8814B BIT(20)
+
+#define BIT_SHIFT_USB23_SW_MODE_V1_8814B 18
+#define BIT_MASK_USB23_SW_MODE_V1_8814B 0x3
+#define BIT_USB23_SW_MODE_V1_8814B(x)                                          \
+	(((x) & BIT_MASK_USB23_SW_MODE_V1_8814B)                               \
+	 << BIT_SHIFT_USB23_SW_MODE_V1_8814B)
+#define BITS_USB23_SW_MODE_V1_8814B                                            \
+	(BIT_MASK_USB23_SW_MODE_V1_8814B << BIT_SHIFT_USB23_SW_MODE_V1_8814B)
+#define BIT_CLEAR_USB23_SW_MODE_V1_8814B(x)                                    \
+	((x) & (~BITS_USB23_SW_MODE_V1_8814B))
+#define BIT_GET_USB23_SW_MODE_V1_8814B(x)                                      \
+	(((x) >> BIT_SHIFT_USB23_SW_MODE_V1_8814B) &                           \
+	 BIT_MASK_USB23_SW_MODE_V1_8814B)
+#define BIT_SET_USB23_SW_MODE_V1_8814B(x, v)                                   \
+	(BIT_CLEAR_USB23_SW_MODE_V1_8814B(x) | BIT_USB23_SW_MODE_V1_8814B(v))
+
+#define BIT_NO_PDN_CHIPOFF_V1_8814B BIT(17)
+#define BIT_RSM_EN_V1_8814B BIT(16)
+
+#define BIT_SHIFT_MATCH_CNT_8814B 8
+#define BIT_MASK_MATCH_CNT_8814B 0xff
+#define BIT_MATCH_CNT_8814B(x)                                                 \
+	(((x) & BIT_MASK_MATCH_CNT_8814B) << BIT_SHIFT_MATCH_CNT_8814B)
+#define BITS_MATCH_CNT_8814B                                                   \
+	(BIT_MASK_MATCH_CNT_8814B << BIT_SHIFT_MATCH_CNT_8814B)
+#define BIT_CLEAR_MATCH_CNT_8814B(x) ((x) & (~BITS_MATCH_CNT_8814B))
+#define BIT_GET_MATCH_CNT_8814B(x)                                             \
+	(((x) >> BIT_SHIFT_MATCH_CNT_8814B) & BIT_MASK_MATCH_CNT_8814B)
+#define BIT_SET_MATCH_CNT_8814B(x, v)                                          \
+	(BIT_CLEAR_MATCH_CNT_8814B(x) | BIT_MATCH_CNT_8814B(v))
+
+#define BIT_LD_B12V_EN_8814B BIT(7)
+#define BIT_EECS_IOSEL_V1_8814B BIT(6)
+#define BIT_EECS_DATA_O_V1_8814B BIT(5)
+#define BIT_EECS_DATA_I_V1_8814B BIT(4)
+#define BIT_EESK_IOSEL_V1_8814B BIT(2)
+#define BIT_EESK_DATA_O_V1_8814B BIT(1)
+#define BIT_EESK_DATA_I_V1_8814B BIT(0)
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_PMC_DBG_CTRL2_8814B */
+
+#define BIT_SHIFT_EFUSE_BURN_GNT_8814B 24
+#define BIT_MASK_EFUSE_BURN_GNT_8814B 0xff
+#define BIT_EFUSE_BURN_GNT_8814B(x)                                            \
+	(((x) & BIT_MASK_EFUSE_BURN_GNT_8814B)                                 \
+	 << BIT_SHIFT_EFUSE_BURN_GNT_8814B)
+#define BITS_EFUSE_BURN_GNT_8814B                                              \
+	(BIT_MASK_EFUSE_BURN_GNT_8814B << BIT_SHIFT_EFUSE_BURN_GNT_8814B)
+#define BIT_CLEAR_EFUSE_BURN_GNT_8814B(x) ((x) & (~BITS_EFUSE_BURN_GNT_8814B))
+#define BIT_GET_EFUSE_BURN_GNT_8814B(x)                                        \
+	(((x) >> BIT_SHIFT_EFUSE_BURN_GNT_8814B) &                             \
+	 BIT_MASK_EFUSE_BURN_GNT_8814B)
+#define BIT_SET_EFUSE_BURN_GNT_8814B(x, v)                                     \
+	(BIT_CLEAR_EFUSE_BURN_GNT_8814B(x) | BIT_EFUSE_BURN_GNT_8814B(v))
+
+#define BIT_STOP_WL_PMC_8814B BIT(9)
+#define BIT_STOP_SYM_PMC_8814B BIT(8)
+#define BIT_BT_ACCESS_WL_PAGE0_8814B BIT(6)
+#define BIT_REG_RST_WLPMC_8814B BIT(5)
+#define BIT_REG_RST_PD12N_8814B BIT(4)
+#define BIT_SYSON_DIS_WLREG_WRMSK_8814B BIT(3)
+#define BIT_SYSON_DIS_PMCREG_WRMSK_8814B BIT(2)
+
+#define BIT_SHIFT_SYSON_REG_ARB_8814B 0
+#define BIT_MASK_SYSON_REG_ARB_8814B 0x3
+#define BIT_SYSON_REG_ARB_8814B(x)                                             \
+	(((x) & BIT_MASK_SYSON_REG_ARB_8814B) << BIT_SHIFT_SYSON_REG_ARB_8814B)
+#define BITS_SYSON_REG_ARB_8814B                                               \
+	(BIT_MASK_SYSON_REG_ARB_8814B << BIT_SHIFT_SYSON_REG_ARB_8814B)
+#define BIT_CLEAR_SYSON_REG_ARB_8814B(x) ((x) & (~BITS_SYSON_REG_ARB_8814B))
+#define BIT_GET_SYSON_REG_ARB_8814B(x)                                         \
+	(((x) >> BIT_SHIFT_SYSON_REG_ARB_8814B) & BIT_MASK_SYSON_REG_ARB_8814B)
+#define BIT_SET_SYSON_REG_ARB_8814B(x, v)                                      \
+	(BIT_CLEAR_SYSON_REG_ARB_8814B(x) | BIT_SYSON_REG_ARB_8814B(v))
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_MEM_CTRL_8814B */
+#define BIT_UMEM_RME_8814B BIT(31)
+
+#define BIT_SHIFT_BT_SPRAM_8814B 28
+#define BIT_MASK_BT_SPRAM_8814B 0x3
+#define BIT_BT_SPRAM_8814B(x)                                                  \
+	(((x) & BIT_MASK_BT_SPRAM_8814B) << BIT_SHIFT_BT_SPRAM_8814B)
+#define BITS_BT_SPRAM_8814B                                                    \
+	(BIT_MASK_BT_SPRAM_8814B << BIT_SHIFT_BT_SPRAM_8814B)
+#define BIT_CLEAR_BT_SPRAM_8814B(x) ((x) & (~BITS_BT_SPRAM_8814B))
+#define BIT_GET_BT_SPRAM_8814B(x)                                              \
+	(((x) >> BIT_SHIFT_BT_SPRAM_8814B) & BIT_MASK_BT_SPRAM_8814B)
+#define BIT_SET_BT_SPRAM_8814B(x, v)                                           \
+	(BIT_CLEAR_BT_SPRAM_8814B(x) | BIT_BT_SPRAM_8814B(v))
+
+#define BIT_SHIFT_BT_ROM_8814B 24
+#define BIT_MASK_BT_ROM_8814B 0xf
+#define BIT_BT_ROM_8814B(x)                                                    \
+	(((x) & BIT_MASK_BT_ROM_8814B) << BIT_SHIFT_BT_ROM_8814B)
+#define BITS_BT_ROM_8814B (BIT_MASK_BT_ROM_8814B << BIT_SHIFT_BT_ROM_8814B)
+#define BIT_CLEAR_BT_ROM_8814B(x) ((x) & (~BITS_BT_ROM_8814B))
+#define BIT_GET_BT_ROM_8814B(x)                                                \
+	(((x) >> BIT_SHIFT_BT_ROM_8814B) & BIT_MASK_BT_ROM_8814B)
+#define BIT_SET_BT_ROM_8814B(x, v)                                             \
+	(BIT_CLEAR_BT_ROM_8814B(x) | BIT_BT_ROM_8814B(v))
+
+#define BIT_SHIFT_PCI_DPRAM_8814B 10
+#define BIT_MASK_PCI_DPRAM_8814B 0x3
+#define BIT_PCI_DPRAM_8814B(x)                                                 \
+	(((x) & BIT_MASK_PCI_DPRAM_8814B) << BIT_SHIFT_PCI_DPRAM_8814B)
+#define BITS_PCI_DPRAM_8814B                                                   \
+	(BIT_MASK_PCI_DPRAM_8814B << BIT_SHIFT_PCI_DPRAM_8814B)
+#define BIT_CLEAR_PCI_DPRAM_8814B(x) ((x) & (~BITS_PCI_DPRAM_8814B))
+#define BIT_GET_PCI_DPRAM_8814B(x)                                             \
+	(((x) >> BIT_SHIFT_PCI_DPRAM_8814B) & BIT_MASK_PCI_DPRAM_8814B)
+#define BIT_SET_PCI_DPRAM_8814B(x, v)                                          \
+	(BIT_CLEAR_PCI_DPRAM_8814B(x) | BIT_PCI_DPRAM_8814B(v))
+
+#define BIT_SHIFT_PCI_SPRAM_8814B 8
+#define BIT_MASK_PCI_SPRAM_8814B 0x3
+#define BIT_PCI_SPRAM_8814B(x)                                                 \
+	(((x) & BIT_MASK_PCI_SPRAM_8814B) << BIT_SHIFT_PCI_SPRAM_8814B)
+#define BITS_PCI_SPRAM_8814B                                                   \
+	(BIT_MASK_PCI_SPRAM_8814B << BIT_SHIFT_PCI_SPRAM_8814B)
+#define BIT_CLEAR_PCI_SPRAM_8814B(x) ((x) & (~BITS_PCI_SPRAM_8814B))
+#define BIT_GET_PCI_SPRAM_8814B(x)                                             \
+	(((x) >> BIT_SHIFT_PCI_SPRAM_8814B) & BIT_MASK_PCI_SPRAM_8814B)
+#define BIT_SET_PCI_SPRAM_8814B(x, v)                                          \
+	(BIT_CLEAR_PCI_SPRAM_8814B(x) | BIT_PCI_SPRAM_8814B(v))
+
+#define BIT_SHIFT_USB_SPRAM_8814B 6
+#define BIT_MASK_USB_SPRAM_8814B 0x3
+#define BIT_USB_SPRAM_8814B(x)                                                 \
+	(((x) & BIT_MASK_USB_SPRAM_8814B) << BIT_SHIFT_USB_SPRAM_8814B)
+#define BITS_USB_SPRAM_8814B                                                   \
+	(BIT_MASK_USB_SPRAM_8814B << BIT_SHIFT_USB_SPRAM_8814B)
+#define BIT_CLEAR_USB_SPRAM_8814B(x) ((x) & (~BITS_USB_SPRAM_8814B))
+#define BIT_GET_USB_SPRAM_8814B(x)                                             \
+	(((x) >> BIT_SHIFT_USB_SPRAM_8814B) & BIT_MASK_USB_SPRAM_8814B)
+#define BIT_SET_USB_SPRAM_8814B(x, v)                                          \
+	(BIT_CLEAR_USB_SPRAM_8814B(x) | BIT_USB_SPRAM_8814B(v))
+
+#define BIT_SHIFT_USB_SPRF_8814B 4
+#define BIT_MASK_USB_SPRF_8814B 0x3
+#define BIT_USB_SPRF_8814B(x)                                                  \
+	(((x) & BIT_MASK_USB_SPRF_8814B) << BIT_SHIFT_USB_SPRF_8814B)
+#define BITS_USB_SPRF_8814B                                                    \
+	(BIT_MASK_USB_SPRF_8814B << BIT_SHIFT_USB_SPRF_8814B)
+#define BIT_CLEAR_USB_SPRF_8814B(x) ((x) & (~BITS_USB_SPRF_8814B))
+#define BIT_GET_USB_SPRF_8814B(x)                                              \
+	(((x) >> BIT_SHIFT_USB_SPRF_8814B) & BIT_MASK_USB_SPRF_8814B)
+#define BIT_SET_USB_SPRF_8814B(x, v)                                           \
+	(BIT_CLEAR_USB_SPRF_8814B(x) | BIT_USB_SPRF_8814B(v))
+
+#define BIT_SHIFT_MCU_ROM_8814B 0
+#define BIT_MASK_MCU_ROM_8814B 0xf
+#define BIT_MCU_ROM_8814B(x)                                                   \
+	(((x) & BIT_MASK_MCU_ROM_8814B) << BIT_SHIFT_MCU_ROM_8814B)
+#define BITS_MCU_ROM_8814B (BIT_MASK_MCU_ROM_8814B << BIT_SHIFT_MCU_ROM_8814B)
+#define BIT_CLEAR_MCU_ROM_8814B(x) ((x) & (~BITS_MCU_ROM_8814B))
+#define BIT_GET_MCU_ROM_8814B(x)                                               \
+	(((x) >> BIT_SHIFT_MCU_ROM_8814B) & BIT_MASK_MCU_ROM_8814B)
+#define BIT_SET_MCU_ROM_8814B(x, v)                                            \
+	(BIT_CLEAR_MCU_ROM_8814B(x) | BIT_MCU_ROM_8814B(v))
+
+/* 2 REG_SYN_RFC_CTRL_8814B */
+
+#define BIT_SHIFT_SYN_RF1_CTRL_8814B 8
+#define BIT_MASK_SYN_RF1_CTRL_8814B 0xff
+#define BIT_SYN_RF1_CTRL_8814B(x)                                              \
+	(((x) & BIT_MASK_SYN_RF1_CTRL_8814B) << BIT_SHIFT_SYN_RF1_CTRL_8814B)
+#define BITS_SYN_RF1_CTRL_8814B                                                \
+	(BIT_MASK_SYN_RF1_CTRL_8814B << BIT_SHIFT_SYN_RF1_CTRL_8814B)
+#define BIT_CLEAR_SYN_RF1_CTRL_8814B(x) ((x) & (~BITS_SYN_RF1_CTRL_8814B))
+#define BIT_GET_SYN_RF1_CTRL_8814B(x)                                          \
+	(((x) >> BIT_SHIFT_SYN_RF1_CTRL_8814B) & BIT_MASK_SYN_RF1_CTRL_8814B)
+#define BIT_SET_SYN_RF1_CTRL_8814B(x, v)                                       \
+	(BIT_CLEAR_SYN_RF1_CTRL_8814B(x) | BIT_SYN_RF1_CTRL_8814B(v))
+
+#define BIT_SHIFT_SYN_RF0_CTRL_8814B 0
+#define BIT_MASK_SYN_RF0_CTRL_8814B 0xff
+#define BIT_SYN_RF0_CTRL_8814B(x)                                              \
+	(((x) & BIT_MASK_SYN_RF0_CTRL_8814B) << BIT_SHIFT_SYN_RF0_CTRL_8814B)
+#define BITS_SYN_RF0_CTRL_8814B                                                \
+	(BIT_MASK_SYN_RF0_CTRL_8814B << BIT_SHIFT_SYN_RF0_CTRL_8814B)
+#define BIT_CLEAR_SYN_RF0_CTRL_8814B(x) ((x) & (~BITS_SYN_RF0_CTRL_8814B))
+#define BIT_GET_SYN_RF0_CTRL_8814B(x)                                          \
+	(((x) >> BIT_SHIFT_SYN_RF0_CTRL_8814B) & BIT_MASK_SYN_RF0_CTRL_8814B)
+#define BIT_SET_SYN_RF0_CTRL_8814B(x, v)                                       \
+	(BIT_CLEAR_SYN_RF0_CTRL_8814B(x) | BIT_SYN_RF0_CTRL_8814B(v))
+
+/* 2 REG_USB_SIE_INTF_8814B */
+#define BIT_RD_SEL_8814B BIT(31)
+#define BIT_USB_SIE_INTF_WE_V1_8814B BIT(30)
+#define BIT_USB_SIE_INTF_BYIOREG_V1_8814B BIT(29)
+#define BIT_USB_SIE_SELECT_8814B BIT(28)
+
+#define BIT_SHIFT_USB_SIE_INTF_ADDR_V1_8814B 16
+#define BIT_MASK_USB_SIE_INTF_ADDR_V1_8814B 0x1ff
+#define BIT_USB_SIE_INTF_ADDR_V1_8814B(x)                                      \
+	(((x) & BIT_MASK_USB_SIE_INTF_ADDR_V1_8814B)                           \
+	 << BIT_SHIFT_USB_SIE_INTF_ADDR_V1_8814B)
+#define BITS_USB_SIE_INTF_ADDR_V1_8814B                                        \
+	(BIT_MASK_USB_SIE_INTF_ADDR_V1_8814B                                   \
+	 << BIT_SHIFT_USB_SIE_INTF_ADDR_V1_8814B)
+#define BIT_CLEAR_USB_SIE_INTF_ADDR_V1_8814B(x)                                \
+	((x) & (~BITS_USB_SIE_INTF_ADDR_V1_8814B))
+#define BIT_GET_USB_SIE_INTF_ADDR_V1_8814B(x)                                  \
+	(((x) >> BIT_SHIFT_USB_SIE_INTF_ADDR_V1_8814B) &                       \
+	 BIT_MASK_USB_SIE_INTF_ADDR_V1_8814B)
+#define BIT_SET_USB_SIE_INTF_ADDR_V1_8814B(x, v)                               \
+	(BIT_CLEAR_USB_SIE_INTF_ADDR_V1_8814B(x) |                             \
+	 BIT_USB_SIE_INTF_ADDR_V1_8814B(v))
+
+#define BIT_SHIFT_USB_SIE_INTF_RD_8814B 8
+#define BIT_MASK_USB_SIE_INTF_RD_8814B 0xff
+#define BIT_USB_SIE_INTF_RD_8814B(x)                                           \
+	(((x) & BIT_MASK_USB_SIE_INTF_RD_8814B)                                \
+	 << BIT_SHIFT_USB_SIE_INTF_RD_8814B)
+#define BITS_USB_SIE_INTF_RD_8814B                                             \
+	(BIT_MASK_USB_SIE_INTF_RD_8814B << BIT_SHIFT_USB_SIE_INTF_RD_8814B)
+#define BIT_CLEAR_USB_SIE_INTF_RD_8814B(x) ((x) & (~BITS_USB_SIE_INTF_RD_8814B))
+#define BIT_GET_USB_SIE_INTF_RD_8814B(x)                                       \
+	(((x) >> BIT_SHIFT_USB_SIE_INTF_RD_8814B) &                            \
+	 BIT_MASK_USB_SIE_INTF_RD_8814B)
+#define BIT_SET_USB_SIE_INTF_RD_8814B(x, v)                                    \
+	(BIT_CLEAR_USB_SIE_INTF_RD_8814B(x) | BIT_USB_SIE_INTF_RD_8814B(v))
+
+#define BIT_SHIFT_USB_SIE_INTF_WD_8814B 0
+#define BIT_MASK_USB_SIE_INTF_WD_8814B 0xff
+#define BIT_USB_SIE_INTF_WD_8814B(x)                                           \
+	(((x) & BIT_MASK_USB_SIE_INTF_WD_8814B)                                \
+	 << BIT_SHIFT_USB_SIE_INTF_WD_8814B)
+#define BITS_USB_SIE_INTF_WD_8814B                                             \
+	(BIT_MASK_USB_SIE_INTF_WD_8814B << BIT_SHIFT_USB_SIE_INTF_WD_8814B)
+#define BIT_CLEAR_USB_SIE_INTF_WD_8814B(x) ((x) & (~BITS_USB_SIE_INTF_WD_8814B))
+#define BIT_GET_USB_SIE_INTF_WD_8814B(x)                                       \
+	(((x) >> BIT_SHIFT_USB_SIE_INTF_WD_8814B) &                            \
+	 BIT_MASK_USB_SIE_INTF_WD_8814B)
+#define BIT_SET_USB_SIE_INTF_WD_8814B(x, v)                                    \
+	(BIT_CLEAR_USB_SIE_INTF_WD_8814B(x) | BIT_USB_SIE_INTF_WD_8814B(v))
+
+/* 2 REG_PCIE_MIO_INTF_8814B */
+
+#define BIT_SHIFT_PCIE_MIO_ADDR_PAGE_8814B 16
+#define BIT_MASK_PCIE_MIO_ADDR_PAGE_8814B 0x3
+#define BIT_PCIE_MIO_ADDR_PAGE_8814B(x)                                        \
+	(((x) & BIT_MASK_PCIE_MIO_ADDR_PAGE_8814B)                             \
+	 << BIT_SHIFT_PCIE_MIO_ADDR_PAGE_8814B)
+#define BITS_PCIE_MIO_ADDR_PAGE_8814B                                          \
+	(BIT_MASK_PCIE_MIO_ADDR_PAGE_8814B                                     \
+	 << BIT_SHIFT_PCIE_MIO_ADDR_PAGE_8814B)
+#define BIT_CLEAR_PCIE_MIO_ADDR_PAGE_8814B(x)                                  \
+	((x) & (~BITS_PCIE_MIO_ADDR_PAGE_8814B))
+#define BIT_GET_PCIE_MIO_ADDR_PAGE_8814B(x)                                    \
+	(((x) >> BIT_SHIFT_PCIE_MIO_ADDR_PAGE_8814B) &                         \
+	 BIT_MASK_PCIE_MIO_ADDR_PAGE_8814B)
+#define BIT_SET_PCIE_MIO_ADDR_PAGE_8814B(x, v)                                 \
+	(BIT_CLEAR_PCIE_MIO_ADDR_PAGE_8814B(x) |                               \
+	 BIT_PCIE_MIO_ADDR_PAGE_8814B(v))
+
+#define BIT_PCIE_MIO_BYIOREG_8814B BIT(13)
+#define BIT_PCIE_MIO_RE_8814B BIT(12)
+
+#define BIT_SHIFT_PCIE_MIO_WE_8814B 8
+#define BIT_MASK_PCIE_MIO_WE_8814B 0xf
+#define BIT_PCIE_MIO_WE_8814B(x)                                               \
+	(((x) & BIT_MASK_PCIE_MIO_WE_8814B) << BIT_SHIFT_PCIE_MIO_WE_8814B)
+#define BITS_PCIE_MIO_WE_8814B                                                 \
+	(BIT_MASK_PCIE_MIO_WE_8814B << BIT_SHIFT_PCIE_MIO_WE_8814B)
+#define BIT_CLEAR_PCIE_MIO_WE_8814B(x) ((x) & (~BITS_PCIE_MIO_WE_8814B))
+#define BIT_GET_PCIE_MIO_WE_8814B(x)                                           \
+	(((x) >> BIT_SHIFT_PCIE_MIO_WE_8814B) & BIT_MASK_PCIE_MIO_WE_8814B)
+#define BIT_SET_PCIE_MIO_WE_8814B(x, v)                                        \
+	(BIT_CLEAR_PCIE_MIO_WE_8814B(x) | BIT_PCIE_MIO_WE_8814B(v))
+
+#define BIT_SHIFT_PCIE_MIO_ADDR_8814B 0
+#define BIT_MASK_PCIE_MIO_ADDR_8814B 0xff
+#define BIT_PCIE_MIO_ADDR_8814B(x)                                             \
+	(((x) & BIT_MASK_PCIE_MIO_ADDR_8814B) << BIT_SHIFT_PCIE_MIO_ADDR_8814B)
+#define BITS_PCIE_MIO_ADDR_8814B                                               \
+	(BIT_MASK_PCIE_MIO_ADDR_8814B << BIT_SHIFT_PCIE_MIO_ADDR_8814B)
+#define BIT_CLEAR_PCIE_MIO_ADDR_8814B(x) ((x) & (~BITS_PCIE_MIO_ADDR_8814B))
+#define BIT_GET_PCIE_MIO_ADDR_8814B(x)                                         \
+	(((x) >> BIT_SHIFT_PCIE_MIO_ADDR_8814B) & BIT_MASK_PCIE_MIO_ADDR_8814B)
+#define BIT_SET_PCIE_MIO_ADDR_8814B(x, v)                                      \
+	(BIT_CLEAR_PCIE_MIO_ADDR_8814B(x) | BIT_PCIE_MIO_ADDR_8814B(v))
+
+/* 2 REG_PCIE_MIO_INTD_8814B */
+
+#define BIT_SHIFT_PCIE_MIO_DATA_8814B 0
+#define BIT_MASK_PCIE_MIO_DATA_8814B 0xffffffffL
+#define BIT_PCIE_MIO_DATA_8814B(x)                                             \
+	(((x) & BIT_MASK_PCIE_MIO_DATA_8814B) << BIT_SHIFT_PCIE_MIO_DATA_8814B)
+#define BITS_PCIE_MIO_DATA_8814B                                               \
+	(BIT_MASK_PCIE_MIO_DATA_8814B << BIT_SHIFT_PCIE_MIO_DATA_8814B)
+#define BIT_CLEAR_PCIE_MIO_DATA_8814B(x) ((x) & (~BITS_PCIE_MIO_DATA_8814B))
+#define BIT_GET_PCIE_MIO_DATA_8814B(x)                                         \
+	(((x) >> BIT_SHIFT_PCIE_MIO_DATA_8814B) & BIT_MASK_PCIE_MIO_DATA_8814B)
+#define BIT_SET_PCIE_MIO_DATA_8814B(x, v)                                      \
+	(BIT_CLEAR_PCIE_MIO_DATA_8814B(x) | BIT_PCIE_MIO_DATA_8814B(v))
+
+/* 2 REG_WLRF1_8814B */
+
+#define BIT_SHIFT_WLRF1_CTRL_8814B 24
+#define BIT_MASK_WLRF1_CTRL_8814B 0xff
+#define BIT_WLRF1_CTRL_8814B(x)                                                \
+	(((x) & BIT_MASK_WLRF1_CTRL_8814B) << BIT_SHIFT_WLRF1_CTRL_8814B)
+#define BITS_WLRF1_CTRL_8814B                                                  \
+	(BIT_MASK_WLRF1_CTRL_8814B << BIT_SHIFT_WLRF1_CTRL_8814B)
+#define BIT_CLEAR_WLRF1_CTRL_8814B(x) ((x) & (~BITS_WLRF1_CTRL_8814B))
+#define BIT_GET_WLRF1_CTRL_8814B(x)                                            \
+	(((x) >> BIT_SHIFT_WLRF1_CTRL_8814B) & BIT_MASK_WLRF1_CTRL_8814B)
+#define BIT_SET_WLRF1_CTRL_8814B(x, v)                                         \
+	(BIT_CLEAR_WLRF1_CTRL_8814B(x) | BIT_WLRF1_CTRL_8814B(v))
+
+#define BIT_SHIFT_WLRF2_CTRL_8814B 16
+#define BIT_MASK_WLRF2_CTRL_8814B 0xff
+#define BIT_WLRF2_CTRL_8814B(x)                                                \
+	(((x) & BIT_MASK_WLRF2_CTRL_8814B) << BIT_SHIFT_WLRF2_CTRL_8814B)
+#define BITS_WLRF2_CTRL_8814B                                                  \
+	(BIT_MASK_WLRF2_CTRL_8814B << BIT_SHIFT_WLRF2_CTRL_8814B)
+#define BIT_CLEAR_WLRF2_CTRL_8814B(x) ((x) & (~BITS_WLRF2_CTRL_8814B))
+#define BIT_GET_WLRF2_CTRL_8814B(x)                                            \
+	(((x) >> BIT_SHIFT_WLRF2_CTRL_8814B) & BIT_MASK_WLRF2_CTRL_8814B)
+#define BIT_SET_WLRF2_CTRL_8814B(x, v)                                         \
+	(BIT_CLEAR_WLRF2_CTRL_8814B(x) | BIT_WLRF2_CTRL_8814B(v))
+
+#define BIT_SHIFT_WLRF3_CTRL_8814B 8
+#define BIT_MASK_WLRF3_CTRL_8814B 0xff
+#define BIT_WLRF3_CTRL_8814B(x)                                                \
+	(((x) & BIT_MASK_WLRF3_CTRL_8814B) << BIT_SHIFT_WLRF3_CTRL_8814B)
+#define BITS_WLRF3_CTRL_8814B                                                  \
+	(BIT_MASK_WLRF3_CTRL_8814B << BIT_SHIFT_WLRF3_CTRL_8814B)
+#define BIT_CLEAR_WLRF3_CTRL_8814B(x) ((x) & (~BITS_WLRF3_CTRL_8814B))
+#define BIT_GET_WLRF3_CTRL_8814B(x)                                            \
+	(((x) >> BIT_SHIFT_WLRF3_CTRL_8814B) & BIT_MASK_WLRF3_CTRL_8814B)
+#define BIT_SET_WLRF3_CTRL_8814B(x, v)                                         \
+	(BIT_CLEAR_WLRF3_CTRL_8814B(x) | BIT_WLRF3_CTRL_8814B(v))
+
+/* 2 REG_SYS_CFG1_8814B */
+
+#define BIT_SHIFT_TRP_ICFG_8814B 28
+#define BIT_MASK_TRP_ICFG_8814B 0xf
+#define BIT_TRP_ICFG_8814B(x)                                                  \
+	(((x) & BIT_MASK_TRP_ICFG_8814B) << BIT_SHIFT_TRP_ICFG_8814B)
+#define BITS_TRP_ICFG_8814B                                                    \
+	(BIT_MASK_TRP_ICFG_8814B << BIT_SHIFT_TRP_ICFG_8814B)
+#define BIT_CLEAR_TRP_ICFG_8814B(x) ((x) & (~BITS_TRP_ICFG_8814B))
+#define BIT_GET_TRP_ICFG_8814B(x)                                              \
+	(((x) >> BIT_SHIFT_TRP_ICFG_8814B) & BIT_MASK_TRP_ICFG_8814B)
+#define BIT_SET_TRP_ICFG_8814B(x, v)                                           \
+	(BIT_CLEAR_TRP_ICFG_8814B(x) | BIT_TRP_ICFG_8814B(v))
+
+#define BIT_RF_TYPE_ID_8814B BIT(27)
+#define BIT_BD_HCI_SEL_8814B BIT(26)
+#define BIT_BD_PKG_SEL_8814B BIT(25)
+#define BIT_SPSLDO_SEL_8814B BIT(24)
+#define BIT_RTL_ID_8814B BIT(23)
+#define BIT_PAD_HWPD_IDN_8814B BIT(22)
+#define BIT_TESTMODE_8814B BIT(20)
+
+#define BIT_SHIFT_VENDOR_ID_8814B 16
+#define BIT_MASK_VENDOR_ID_8814B 0xf
+#define BIT_VENDOR_ID_8814B(x)                                                 \
+	(((x) & BIT_MASK_VENDOR_ID_8814B) << BIT_SHIFT_VENDOR_ID_8814B)
+#define BITS_VENDOR_ID_8814B                                                   \
+	(BIT_MASK_VENDOR_ID_8814B << BIT_SHIFT_VENDOR_ID_8814B)
+#define BIT_CLEAR_VENDOR_ID_8814B(x) ((x) & (~BITS_VENDOR_ID_8814B))
+#define BIT_GET_VENDOR_ID_8814B(x)                                             \
+	(((x) >> BIT_SHIFT_VENDOR_ID_8814B) & BIT_MASK_VENDOR_ID_8814B)
+#define BIT_SET_VENDOR_ID_8814B(x, v)                                          \
+	(BIT_CLEAR_VENDOR_ID_8814B(x) | BIT_VENDOR_ID_8814B(v))
+
+#define BIT_SHIFT_CHIP_VER_8814B 12
+#define BIT_MASK_CHIP_VER_8814B 0xf
+#define BIT_CHIP_VER_8814B(x)                                                  \
+	(((x) & BIT_MASK_CHIP_VER_8814B) << BIT_SHIFT_CHIP_VER_8814B)
+#define BITS_CHIP_VER_8814B                                                    \
+	(BIT_MASK_CHIP_VER_8814B << BIT_SHIFT_CHIP_VER_8814B)
+#define BIT_CLEAR_CHIP_VER_8814B(x) ((x) & (~BITS_CHIP_VER_8814B))
+#define BIT_GET_CHIP_VER_8814B(x)                                              \
+	(((x) >> BIT_SHIFT_CHIP_VER_8814B) & BIT_MASK_CHIP_VER_8814B)
+#define BIT_SET_CHIP_VER_8814B(x, v)                                           \
+	(BIT_CLEAR_CHIP_VER_8814B(x) | BIT_CHIP_VER_8814B(v))
+
+#define BIT_BD_MAC3_8814B BIT(11)
+#define BIT_BD_MAC1_8814B BIT(10)
+#define BIT_BD_MAC2_8814B BIT(9)
+#define BIT_SIC_IDLE_8814B BIT(8)
+#define BIT_SW_OFFLOAD_EN_8814B BIT(7)
+#define BIT_OCP_SHUTDN_8814B BIT(6)
+#define BIT_V15_VLD_8814B BIT(5)
+#define BIT_PCIRSTB_8814B BIT(4)
+#define BIT_PCLK_VLD_8814B BIT(3)
+#define BIT_UCLK_VLD_8814B BIT(2)
+#define BIT_ACLK_VLD_8814B BIT(1)
+#define BIT_XCLK_VLD_8814B BIT(0)
+
+/* 2 REG_SYS_STATUS1_8814B */
+
+#define BIT_SHIFT_RF_RL_ID_8814B 28
+#define BIT_MASK_RF_RL_ID_8814B 0xf
+#define BIT_RF_RL_ID_8814B(x)                                                  \
+	(((x) & BIT_MASK_RF_RL_ID_8814B) << BIT_SHIFT_RF_RL_ID_8814B)
+#define BITS_RF_RL_ID_8814B                                                    \
+	(BIT_MASK_RF_RL_ID_8814B << BIT_SHIFT_RF_RL_ID_8814B)
+#define BIT_CLEAR_RF_RL_ID_8814B(x) ((x) & (~BITS_RF_RL_ID_8814B))
+#define BIT_GET_RF_RL_ID_8814B(x)                                              \
+	(((x) >> BIT_SHIFT_RF_RL_ID_8814B) & BIT_MASK_RF_RL_ID_8814B)
+#define BIT_SET_RF_RL_ID_8814B(x, v)                                           \
+	(BIT_CLEAR_RF_RL_ID_8814B(x) | BIT_RF_RL_ID_8814B(v))
+
+/* 2 REG_NOT_VALID_8814B */
+
+#define BIT_SHIFT_XTAL_SEL_8814B 25
+#define BIT_MASK_XTAL_SEL_8814B 0x3
+#define BIT_XTAL_SEL_8814B(x)                                                  \
+	(((x) & BIT_MASK_XTAL_SEL_8814B) << BIT_SHIFT_XTAL_SEL_8814B)
+#define BITS_XTAL_SEL_8814B                                                    \
+	(BIT_MASK_XTAL_SEL_8814B << BIT_SHIFT_XTAL_SEL_8814B)
+#define BIT_CLEAR_XTAL_SEL_8814B(x) ((x) & (~BITS_XTAL_SEL_8814B))
+#define BIT_GET_XTAL_SEL_8814B(x)                                              \
+	(((x) >> BIT_SHIFT_XTAL_SEL_8814B) & BIT_MASK_XTAL_SEL_8814B)
+#define BIT_SET_XTAL_SEL_8814B(x, v)                                           \
+	(BIT_CLEAR_XTAL_SEL_8814B(x) | BIT_XTAL_SEL_8814B(v))
+
+#define BIT_HPHY_ICFG_8814B BIT(19)
+
+#define BIT_SHIFT_SEL_0XC0_8814B 16
+#define BIT_MASK_SEL_0XC0_8814B 0x3
+#define BIT_SEL_0XC0_8814B(x)                                                  \
+	(((x) & BIT_MASK_SEL_0XC0_8814B) << BIT_SHIFT_SEL_0XC0_8814B)
+#define BITS_SEL_0XC0_8814B                                                    \
+	(BIT_MASK_SEL_0XC0_8814B << BIT_SHIFT_SEL_0XC0_8814B)
+#define BIT_CLEAR_SEL_0XC0_8814B(x) ((x) & (~BITS_SEL_0XC0_8814B))
+#define BIT_GET_SEL_0XC0_8814B(x)                                              \
+	(((x) >> BIT_SHIFT_SEL_0XC0_8814B) & BIT_MASK_SEL_0XC0_8814B)
+#define BIT_SET_SEL_0XC0_8814B(x, v)                                           \
+	(BIT_CLEAR_SEL_0XC0_8814B(x) | BIT_SEL_0XC0_8814B(v))
+
+#define BIT_SHIFT_HCI_SEL_V4_8814B 12
+#define BIT_MASK_HCI_SEL_V4_8814B 0x3
+#define BIT_HCI_SEL_V4_8814B(x)                                                \
+	(((x) & BIT_MASK_HCI_SEL_V4_8814B) << BIT_SHIFT_HCI_SEL_V4_8814B)
+#define BITS_HCI_SEL_V4_8814B                                                  \
+	(BIT_MASK_HCI_SEL_V4_8814B << BIT_SHIFT_HCI_SEL_V4_8814B)
+#define BIT_CLEAR_HCI_SEL_V4_8814B(x) ((x) & (~BITS_HCI_SEL_V4_8814B))
+#define BIT_GET_HCI_SEL_V4_8814B(x)                                            \
+	(((x) >> BIT_SHIFT_HCI_SEL_V4_8814B) & BIT_MASK_HCI_SEL_V4_8814B)
+#define BIT_SET_HCI_SEL_V4_8814B(x, v)                                         \
+	(BIT_CLEAR_HCI_SEL_V4_8814B(x) | BIT_HCI_SEL_V4_8814B(v))
+
+#define BIT_USB_OPERATION_MODE_8814B BIT(10)
+#define BIT_BT_PDN_8814B BIT(9)
+#define BIT_AUTO_WLPON_8814B BIT(8)
+#define BIT_WL_MODE_8814B BIT(7)
+#define BIT_PKG_SEL_HCI_8814B BIT(6)
+
+#define BIT_SHIFT_PAD_HCI_SEL_V2_8814B 3
+#define BIT_MASK_PAD_HCI_SEL_V2_8814B 0x3
+#define BIT_PAD_HCI_SEL_V2_8814B(x)                                            \
+	(((x) & BIT_MASK_PAD_HCI_SEL_V2_8814B)                                 \
+	 << BIT_SHIFT_PAD_HCI_SEL_V2_8814B)
+#define BITS_PAD_HCI_SEL_V2_8814B                                              \
+	(BIT_MASK_PAD_HCI_SEL_V2_8814B << BIT_SHIFT_PAD_HCI_SEL_V2_8814B)
+#define BIT_CLEAR_PAD_HCI_SEL_V2_8814B(x) ((x) & (~BITS_PAD_HCI_SEL_V2_8814B))
+#define BIT_GET_PAD_HCI_SEL_V2_8814B(x)                                        \
+	(((x) >> BIT_SHIFT_PAD_HCI_SEL_V2_8814B) &                             \
+	 BIT_MASK_PAD_HCI_SEL_V2_8814B)
+#define BIT_SET_PAD_HCI_SEL_V2_8814B(x, v)                                     \
+	(BIT_CLEAR_PAD_HCI_SEL_V2_8814B(x) | BIT_PAD_HCI_SEL_V2_8814B(v))
+
+#define BIT_SHIFT_EFS_HCI_SEL_8814B 0
+#define BIT_MASK_EFS_HCI_SEL_8814B 0x3
+#define BIT_EFS_HCI_SEL_8814B(x)                                               \
+	(((x) & BIT_MASK_EFS_HCI_SEL_8814B) << BIT_SHIFT_EFS_HCI_SEL_8814B)
+#define BITS_EFS_HCI_SEL_8814B                                                 \
+	(BIT_MASK_EFS_HCI_SEL_8814B << BIT_SHIFT_EFS_HCI_SEL_8814B)
+#define BIT_CLEAR_EFS_HCI_SEL_8814B(x) ((x) & (~BITS_EFS_HCI_SEL_8814B))
+#define BIT_GET_EFS_HCI_SEL_8814B(x)                                           \
+	(((x) >> BIT_SHIFT_EFS_HCI_SEL_8814B) & BIT_MASK_EFS_HCI_SEL_8814B)
+#define BIT_SET_EFS_HCI_SEL_8814B(x, v)                                        \
+	(BIT_CLEAR_EFS_HCI_SEL_8814B(x) | BIT_EFS_HCI_SEL_8814B(v))
+
+/* 2 REG_SYS_STATUS2_8814B */
+#define BIT_SIO_ALDN_8814B BIT(19)
+#define BIT_USB_ALDN_8814B BIT(18)
+#define BIT_PCI_ALDN_8814B BIT(17)
+#define BIT_SYS_ALDN_8814B BIT(16)
+
+#define BIT_SHIFT_EPVID1_8814B 8
+#define BIT_MASK_EPVID1_8814B 0xff
+#define BIT_EPVID1_8814B(x)                                                    \
+	(((x) & BIT_MASK_EPVID1_8814B) << BIT_SHIFT_EPVID1_8814B)
+#define BITS_EPVID1_8814B (BIT_MASK_EPVID1_8814B << BIT_SHIFT_EPVID1_8814B)
+#define BIT_CLEAR_EPVID1_8814B(x) ((x) & (~BITS_EPVID1_8814B))
+#define BIT_GET_EPVID1_8814B(x)                                                \
+	(((x) >> BIT_SHIFT_EPVID1_8814B) & BIT_MASK_EPVID1_8814B)
+#define BIT_SET_EPVID1_8814B(x, v)                                             \
+	(BIT_CLEAR_EPVID1_8814B(x) | BIT_EPVID1_8814B(v))
+
+#define BIT_SHIFT_EPVID0_8814B 0
+#define BIT_MASK_EPVID0_8814B 0xff
+#define BIT_EPVID0_8814B(x)                                                    \
+	(((x) & BIT_MASK_EPVID0_8814B) << BIT_SHIFT_EPVID0_8814B)
+#define BITS_EPVID0_8814B (BIT_MASK_EPVID0_8814B << BIT_SHIFT_EPVID0_8814B)
+#define BIT_CLEAR_EPVID0_8814B(x) ((x) & (~BITS_EPVID0_8814B))
+#define BIT_GET_EPVID0_8814B(x)                                                \
+	(((x) >> BIT_SHIFT_EPVID0_8814B) & BIT_MASK_EPVID0_8814B)
+#define BIT_SET_EPVID0_8814B(x, v)                                             \
+	(BIT_CLEAR_EPVID0_8814B(x) | BIT_EPVID0_8814B(v))
+
+/* 2 REG_SYS_CFG2_8814B */
+#define BIT_USB2_SEL_8814B BIT(31)
+#define BIT_U3PHY_RST_V1_8814B BIT(30)
+#define BIT_U3_TERM_DETECT_8814B BIT(29)
+
+#define BIT_SHIFT_HW_ID_8814B 0
+#define BIT_MASK_HW_ID_8814B 0xff
+#define BIT_HW_ID_8814B(x)                                                     \
+	(((x) & BIT_MASK_HW_ID_8814B) << BIT_SHIFT_HW_ID_8814B)
+#define BITS_HW_ID_8814B (BIT_MASK_HW_ID_8814B << BIT_SHIFT_HW_ID_8814B)
+#define BIT_CLEAR_HW_ID_8814B(x) ((x) & (~BITS_HW_ID_8814B))
+#define BIT_GET_HW_ID_8814B(x)                                                 \
+	(((x) >> BIT_SHIFT_HW_ID_8814B) & BIT_MASK_HW_ID_8814B)
+#define BIT_SET_HW_ID_8814B(x, v)                                              \
+	(BIT_CLEAR_HW_ID_8814B(x) | BIT_HW_ID_8814B(v))
+
+/* 2 REG_NOT_VALID_8814B */
+#define BIT_FEN_WLMAC_OFF_8814B BIT(31)
+#define BIT_PWC_MA33V_8814B BIT(15)
+#define BIT_PWC_MA12V_8814B BIT(14)
+#define BIT_PWC_MD12V_8814B BIT(13)
+#define BIT_PWC_PD12V_8814B BIT(12)
+#define BIT_PWC_UD12V_8814B BIT(11)
+#define BIT_ISO_BB2PP_8814B BIT(7)
+#define BIT_ISO_DENG2PP_8814B BIT(6)
+#define BIT_ISO_MA2MD_8814B BIT(1)
+#define BIT_ISO_MD2PP_8814B BIT(0)
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_ANAPARSW_MAC_0_8814B */
+#define BIT_OCP_L_0_8814B BIT(31)
+#define BIT_POWOCP_L_8814B BIT(30)
+
+#define BIT_SHIFT_CF_L_1_0_8814B 28
+#define BIT_MASK_CF_L_1_0_8814B 0x3
+#define BIT_CF_L_1_0_8814B(x)                                                  \
+	(((x) & BIT_MASK_CF_L_1_0_8814B) << BIT_SHIFT_CF_L_1_0_8814B)
+#define BITS_CF_L_1_0_8814B                                                    \
+	(BIT_MASK_CF_L_1_0_8814B << BIT_SHIFT_CF_L_1_0_8814B)
+#define BIT_CLEAR_CF_L_1_0_8814B(x) ((x) & (~BITS_CF_L_1_0_8814B))
+#define BIT_GET_CF_L_1_0_8814B(x)                                              \
+	(((x) >> BIT_SHIFT_CF_L_1_0_8814B) & BIT_MASK_CF_L_1_0_8814B)
+#define BIT_SET_CF_L_1_0_8814B(x, v)                                           \
+	(BIT_CLEAR_CF_L_1_0_8814B(x) | BIT_CF_L_1_0_8814B(v))
+
+#define BIT_SHIFT_CFC_L_1_0_8814B 26
+#define BIT_MASK_CFC_L_1_0_8814B 0x3
+#define BIT_CFC_L_1_0_8814B(x)                                                 \
+	(((x) & BIT_MASK_CFC_L_1_0_8814B) << BIT_SHIFT_CFC_L_1_0_8814B)
+#define BITS_CFC_L_1_0_8814B                                                   \
+	(BIT_MASK_CFC_L_1_0_8814B << BIT_SHIFT_CFC_L_1_0_8814B)
+#define BIT_CLEAR_CFC_L_1_0_8814B(x) ((x) & (~BITS_CFC_L_1_0_8814B))
+#define BIT_GET_CFC_L_1_0_8814B(x)                                             \
+	(((x) >> BIT_SHIFT_CFC_L_1_0_8814B) & BIT_MASK_CFC_L_1_0_8814B)
+#define BIT_SET_CFC_L_1_0_8814B(x, v)                                          \
+	(BIT_CLEAR_CFC_L_1_0_8814B(x) | BIT_CFC_L_1_0_8814B(v))
+
+#define BIT_SHIFT_R3_L_1_0_8814B 24
+#define BIT_MASK_R3_L_1_0_8814B 0x3
+#define BIT_R3_L_1_0_8814B(x)                                                  \
+	(((x) & BIT_MASK_R3_L_1_0_8814B) << BIT_SHIFT_R3_L_1_0_8814B)
+#define BITS_R3_L_1_0_8814B                                                    \
+	(BIT_MASK_R3_L_1_0_8814B << BIT_SHIFT_R3_L_1_0_8814B)
+#define BIT_CLEAR_R3_L_1_0_8814B(x) ((x) & (~BITS_R3_L_1_0_8814B))
+#define BIT_GET_R3_L_1_0_8814B(x)                                              \
+	(((x) >> BIT_SHIFT_R3_L_1_0_8814B) & BIT_MASK_R3_L_1_0_8814B)
+#define BIT_SET_R3_L_1_0_8814B(x, v)                                           \
+	(BIT_CLEAR_R3_L_1_0_8814B(x) | BIT_R3_L_1_0_8814B(v))
+
+#define BIT_SHIFT_R2_L_1_0_8814B 22
+#define BIT_MASK_R2_L_1_0_8814B 0x3
+#define BIT_R2_L_1_0_8814B(x)                                                  \
+	(((x) & BIT_MASK_R2_L_1_0_8814B) << BIT_SHIFT_R2_L_1_0_8814B)
+#define BITS_R2_L_1_0_8814B                                                    \
+	(BIT_MASK_R2_L_1_0_8814B << BIT_SHIFT_R2_L_1_0_8814B)
+#define BIT_CLEAR_R2_L_1_0_8814B(x) ((x) & (~BITS_R2_L_1_0_8814B))
+#define BIT_GET_R2_L_1_0_8814B(x)                                              \
+	(((x) >> BIT_SHIFT_R2_L_1_0_8814B) & BIT_MASK_R2_L_1_0_8814B)
+#define BIT_SET_R2_L_1_0_8814B(x, v)                                           \
+	(BIT_CLEAR_R2_L_1_0_8814B(x) | BIT_R2_L_1_0_8814B(v))
+
+#define BIT_SHIFT_R1_L_1_0_8814B 20
+#define BIT_MASK_R1_L_1_0_8814B 0x3
+#define BIT_R1_L_1_0_8814B(x)                                                  \
+	(((x) & BIT_MASK_R1_L_1_0_8814B) << BIT_SHIFT_R1_L_1_0_8814B)
+#define BITS_R1_L_1_0_8814B                                                    \
+	(BIT_MASK_R1_L_1_0_8814B << BIT_SHIFT_R1_L_1_0_8814B)
+#define BIT_CLEAR_R1_L_1_0_8814B(x) ((x) & (~BITS_R1_L_1_0_8814B))
+#define BIT_GET_R1_L_1_0_8814B(x)                                              \
+	(((x) >> BIT_SHIFT_R1_L_1_0_8814B) & BIT_MASK_R1_L_1_0_8814B)
+#define BIT_SET_R1_L_1_0_8814B(x, v)                                           \
+	(BIT_CLEAR_R1_L_1_0_8814B(x) | BIT_R1_L_1_0_8814B(v))
+
+#define BIT_SHIFT_C3_L_1_0_8814B 18
+#define BIT_MASK_C3_L_1_0_8814B 0x3
+#define BIT_C3_L_1_0_8814B(x)                                                  \
+	(((x) & BIT_MASK_C3_L_1_0_8814B) << BIT_SHIFT_C3_L_1_0_8814B)
+#define BITS_C3_L_1_0_8814B                                                    \
+	(BIT_MASK_C3_L_1_0_8814B << BIT_SHIFT_C3_L_1_0_8814B)
+#define BIT_CLEAR_C3_L_1_0_8814B(x) ((x) & (~BITS_C3_L_1_0_8814B))
+#define BIT_GET_C3_L_1_0_8814B(x)                                              \
+	(((x) >> BIT_SHIFT_C3_L_1_0_8814B) & BIT_MASK_C3_L_1_0_8814B)
+#define BIT_SET_C3_L_1_0_8814B(x, v)                                           \
+	(BIT_CLEAR_C3_L_1_0_8814B(x) | BIT_C3_L_1_0_8814B(v))
+
+#define BIT_SHIFT_C2_L_1_0_8814B 16
+#define BIT_MASK_C2_L_1_0_8814B 0x3
+#define BIT_C2_L_1_0_8814B(x)                                                  \
+	(((x) & BIT_MASK_C2_L_1_0_8814B) << BIT_SHIFT_C2_L_1_0_8814B)
+#define BITS_C2_L_1_0_8814B                                                    \
+	(BIT_MASK_C2_L_1_0_8814B << BIT_SHIFT_C2_L_1_0_8814B)
+#define BIT_CLEAR_C2_L_1_0_8814B(x) ((x) & (~BITS_C2_L_1_0_8814B))
+#define BIT_GET_C2_L_1_0_8814B(x)                                              \
+	(((x) >> BIT_SHIFT_C2_L_1_0_8814B) & BIT_MASK_C2_L_1_0_8814B)
+#define BIT_SET_C2_L_1_0_8814B(x, v)                                           \
+	(BIT_CLEAR_C2_L_1_0_8814B(x) | BIT_C2_L_1_0_8814B(v))
+
+#define BIT_SHIFT_C1_L_1_0_8814B 14
+#define BIT_MASK_C1_L_1_0_8814B 0x3
+#define BIT_C1_L_1_0_8814B(x)                                                  \
+	(((x) & BIT_MASK_C1_L_1_0_8814B) << BIT_SHIFT_C1_L_1_0_8814B)
+#define BITS_C1_L_1_0_8814B                                                    \
+	(BIT_MASK_C1_L_1_0_8814B << BIT_SHIFT_C1_L_1_0_8814B)
+#define BIT_CLEAR_C1_L_1_0_8814B(x) ((x) & (~BITS_C1_L_1_0_8814B))
+#define BIT_GET_C1_L_1_0_8814B(x)                                              \
+	(((x) >> BIT_SHIFT_C1_L_1_0_8814B) & BIT_MASK_C1_L_1_0_8814B)
+#define BIT_SET_C1_L_1_0_8814B(x, v)                                           \
+	(BIT_CLEAR_C1_L_1_0_8814B(x) | BIT_C1_L_1_0_8814B(v))
+
+#define BIT_REG_TYPE_L_V2_8814B BIT(13)
+#define BIT_REG_PWM_L_8814B BIT(12)
+
+#define BIT_SHIFT_V15ADJ_L_2_0_8814B 9
+#define BIT_MASK_V15ADJ_L_2_0_8814B 0x7
+#define BIT_V15ADJ_L_2_0_8814B(x)                                              \
+	(((x) & BIT_MASK_V15ADJ_L_2_0_8814B) << BIT_SHIFT_V15ADJ_L_2_0_8814B)
+#define BITS_V15ADJ_L_2_0_8814B                                                \
+	(BIT_MASK_V15ADJ_L_2_0_8814B << BIT_SHIFT_V15ADJ_L_2_0_8814B)
+#define BIT_CLEAR_V15ADJ_L_2_0_8814B(x) ((x) & (~BITS_V15ADJ_L_2_0_8814B))
+#define BIT_GET_V15ADJ_L_2_0_8814B(x)                                          \
+	(((x) >> BIT_SHIFT_V15ADJ_L_2_0_8814B) & BIT_MASK_V15ADJ_L_2_0_8814B)
+#define BIT_SET_V15ADJ_L_2_0_8814B(x, v)                                       \
+	(BIT_CLEAR_V15ADJ_L_2_0_8814B(x) | BIT_V15ADJ_L_2_0_8814B(v))
+
+#define BIT_SHIFT_IN_L_2_0_8814B 6
+#define BIT_MASK_IN_L_2_0_8814B 0x7
+#define BIT_IN_L_2_0_8814B(x)                                                  \
+	(((x) & BIT_MASK_IN_L_2_0_8814B) << BIT_SHIFT_IN_L_2_0_8814B)
+#define BITS_IN_L_2_0_8814B                                                    \
+	(BIT_MASK_IN_L_2_0_8814B << BIT_SHIFT_IN_L_2_0_8814B)
+#define BIT_CLEAR_IN_L_2_0_8814B(x) ((x) & (~BITS_IN_L_2_0_8814B))
+#define BIT_GET_IN_L_2_0_8814B(x)                                              \
+	(((x) >> BIT_SHIFT_IN_L_2_0_8814B) & BIT_MASK_IN_L_2_0_8814B)
+#define BIT_SET_IN_L_2_0_8814B(x, v)                                           \
+	(BIT_CLEAR_IN_L_2_0_8814B(x) | BIT_IN_L_2_0_8814B(v))
+
+#define BIT_SHIFT_STD_L_1_0_8814B 4
+#define BIT_MASK_STD_L_1_0_8814B 0x3
+#define BIT_STD_L_1_0_8814B(x)                                                 \
+	(((x) & BIT_MASK_STD_L_1_0_8814B) << BIT_SHIFT_STD_L_1_0_8814B)
+#define BITS_STD_L_1_0_8814B                                                   \
+	(BIT_MASK_STD_L_1_0_8814B << BIT_SHIFT_STD_L_1_0_8814B)
+#define BIT_CLEAR_STD_L_1_0_8814B(x) ((x) & (~BITS_STD_L_1_0_8814B))
+#define BIT_GET_STD_L_1_0_8814B(x)                                             \
+	(((x) >> BIT_SHIFT_STD_L_1_0_8814B) & BIT_MASK_STD_L_1_0_8814B)
+#define BIT_SET_STD_L_1_0_8814B(x, v)                                          \
+	(BIT_CLEAR_STD_L_1_0_8814B(x) | BIT_STD_L_1_0_8814B(v))
+
+#define BIT_SHIFT_VOL_L_3_0_8814B 0
+#define BIT_MASK_VOL_L_3_0_8814B 0xf
+#define BIT_VOL_L_3_0_8814B(x)                                                 \
+	(((x) & BIT_MASK_VOL_L_3_0_8814B) << BIT_SHIFT_VOL_L_3_0_8814B)
+#define BITS_VOL_L_3_0_8814B                                                   \
+	(BIT_MASK_VOL_L_3_0_8814B << BIT_SHIFT_VOL_L_3_0_8814B)
+#define BIT_CLEAR_VOL_L_3_0_8814B(x) ((x) & (~BITS_VOL_L_3_0_8814B))
+#define BIT_GET_VOL_L_3_0_8814B(x)                                             \
+	(((x) >> BIT_SHIFT_VOL_L_3_0_8814B) & BIT_MASK_VOL_L_3_0_8814B)
+#define BIT_SET_VOL_L_3_0_8814B(x, v)                                          \
+	(BIT_CLEAR_VOL_L_3_0_8814B(x) | BIT_VOL_L_3_0_8814B(v))
+
+/* 2 REG_ANAPARSW_MAC_1_8814B */
+
+#define BIT_SHIFT_REG_FREQ_L_V1_8814B 20
+#define BIT_MASK_REG_FREQ_L_V1_8814B 0x7
+#define BIT_REG_FREQ_L_V1_8814B(x)                                             \
+	(((x) & BIT_MASK_REG_FREQ_L_V1_8814B) << BIT_SHIFT_REG_FREQ_L_V1_8814B)
+#define BITS_REG_FREQ_L_V1_8814B                                               \
+	(BIT_MASK_REG_FREQ_L_V1_8814B << BIT_SHIFT_REG_FREQ_L_V1_8814B)
+#define BIT_CLEAR_REG_FREQ_L_V1_8814B(x) ((x) & (~BITS_REG_FREQ_L_V1_8814B))
+#define BIT_GET_REG_FREQ_L_V1_8814B(x)                                         \
+	(((x) >> BIT_SHIFT_REG_FREQ_L_V1_8814B) & BIT_MASK_REG_FREQ_L_V1_8814B)
+#define BIT_SET_REG_FREQ_L_V1_8814B(x, v)                                      \
+	(BIT_CLEAR_REG_FREQ_L_V1_8814B(x) | BIT_REG_FREQ_L_V1_8814B(v))
+
+#define BIT_EN_DUTY_8814B BIT(19)
+
+#define BIT_SHIFT_REG_MOS_HALF_8814B 17
+#define BIT_MASK_REG_MOS_HALF_8814B 0x3
+#define BIT_REG_MOS_HALF_8814B(x)                                              \
+	(((x) & BIT_MASK_REG_MOS_HALF_8814B) << BIT_SHIFT_REG_MOS_HALF_8814B)
+#define BITS_REG_MOS_HALF_8814B                                                \
+	(BIT_MASK_REG_MOS_HALF_8814B << BIT_SHIFT_REG_MOS_HALF_8814B)
+#define BIT_CLEAR_REG_MOS_HALF_8814B(x) ((x) & (~BITS_REG_MOS_HALF_8814B))
+#define BIT_GET_REG_MOS_HALF_8814B(x)                                          \
+	(((x) >> BIT_SHIFT_REG_MOS_HALF_8814B) & BIT_MASK_REG_MOS_HALF_8814B)
+#define BIT_SET_REG_MOS_HALF_8814B(x, v)                                       \
+	(BIT_CLEAR_REG_MOS_HALF_8814B(x) | BIT_REG_MOS_HALF_8814B(v))
+
+#define BIT_EN_SP_8814B BIT(16)
+#define BIT_REG_AUTO_L_V1_8814B BIT(15)
+#define BIT_REG_LDOF_L_V2_8814B BIT(14)
+#define BIT_REG_OCPS_L_V2_8814B BIT(13)
+
+/* 2 REG_NOT_VALID_8814B */
+#define BIT_ARENB_L_V1_8814B BIT(11)
+
+#define BIT_SHIFT_TBOX_L1_1_0_8814B 9
+#define BIT_MASK_TBOX_L1_1_0_8814B 0x3
+#define BIT_TBOX_L1_1_0_8814B(x)                                               \
+	(((x) & BIT_MASK_TBOX_L1_1_0_8814B) << BIT_SHIFT_TBOX_L1_1_0_8814B)
+#define BITS_TBOX_L1_1_0_8814B                                                 \
+	(BIT_MASK_TBOX_L1_1_0_8814B << BIT_SHIFT_TBOX_L1_1_0_8814B)
+#define BIT_CLEAR_TBOX_L1_1_0_8814B(x) ((x) & (~BITS_TBOX_L1_1_0_8814B))
+#define BIT_GET_TBOX_L1_1_0_8814B(x)                                           \
+	(((x) >> BIT_SHIFT_TBOX_L1_1_0_8814B) & BIT_MASK_TBOX_L1_1_0_8814B)
+#define BIT_SET_TBOX_L1_1_0_8814B(x, v)                                        \
+	(BIT_CLEAR_TBOX_L1_1_0_8814B(x) | BIT_TBOX_L1_1_0_8814B(v))
+
+#define BIT_SHIFT_REG_DELAY_L_1_0_8814B 7
+#define BIT_MASK_REG_DELAY_L_1_0_8814B 0x3
+#define BIT_REG_DELAY_L_1_0_8814B(x)                                           \
+	(((x) & BIT_MASK_REG_DELAY_L_1_0_8814B)                                \
+	 << BIT_SHIFT_REG_DELAY_L_1_0_8814B)
+#define BITS_REG_DELAY_L_1_0_8814B                                             \
+	(BIT_MASK_REG_DELAY_L_1_0_8814B << BIT_SHIFT_REG_DELAY_L_1_0_8814B)
+#define BIT_CLEAR_REG_DELAY_L_1_0_8814B(x) ((x) & (~BITS_REG_DELAY_L_1_0_8814B))
+#define BIT_GET_REG_DELAY_L_1_0_8814B(x)                                       \
+	(((x) >> BIT_SHIFT_REG_DELAY_L_1_0_8814B) &                            \
+	 BIT_MASK_REG_DELAY_L_1_0_8814B)
+#define BIT_SET_REG_DELAY_L_1_0_8814B(x, v)                                    \
+	(BIT_CLEAR_REG_DELAY_L_1_0_8814B(x) | BIT_REG_DELAY_L_1_0_8814B(v))
+
+#define BIT_REG_CLAMP_D_L_8814B BIT(6)
+#define BIT_REG_BYPASS_L_V1_8814B BIT(5)
+#define BIT_REG_AUTOZCD_L_8814B BIT(4)
+#define BIT_POW_ZCD_L_V1_8814B BIT(3)
+
+/* 2 REG_NOT_VALID_8814B */
+
+#define BIT_SHIFT_OCP_L_2_1_8814B 0
+#define BIT_MASK_OCP_L_2_1_8814B 0x3
+#define BIT_OCP_L_2_1_8814B(x)                                                 \
+	(((x) & BIT_MASK_OCP_L_2_1_8814B) << BIT_SHIFT_OCP_L_2_1_8814B)
+#define BITS_OCP_L_2_1_8814B                                                   \
+	(BIT_MASK_OCP_L_2_1_8814B << BIT_SHIFT_OCP_L_2_1_8814B)
+#define BIT_CLEAR_OCP_L_2_1_8814B(x) ((x) & (~BITS_OCP_L_2_1_8814B))
+#define BIT_GET_OCP_L_2_1_8814B(x)                                             \
+	(((x) >> BIT_SHIFT_OCP_L_2_1_8814B) & BIT_MASK_OCP_L_2_1_8814B)
+#define BIT_SET_OCP_L_2_1_8814B(x, v)                                          \
+	(BIT_CLEAR_OCP_L_2_1_8814B(x) | BIT_OCP_L_2_1_8814B(v))
+
+/* 2 REG_ANAPAR_MAC_0_8814B */
+
+#define BIT_SHIFT_LPF_C2_1_0_8814B 30
+#define BIT_MASK_LPF_C2_1_0_8814B 0x3
+#define BIT_LPF_C2_1_0_8814B(x)                                                \
+	(((x) & BIT_MASK_LPF_C2_1_0_8814B) << BIT_SHIFT_LPF_C2_1_0_8814B)
+#define BITS_LPF_C2_1_0_8814B                                                  \
+	(BIT_MASK_LPF_C2_1_0_8814B << BIT_SHIFT_LPF_C2_1_0_8814B)
+#define BIT_CLEAR_LPF_C2_1_0_8814B(x) ((x) & (~BITS_LPF_C2_1_0_8814B))
+#define BIT_GET_LPF_C2_1_0_8814B(x)                                            \
+	(((x) >> BIT_SHIFT_LPF_C2_1_0_8814B) & BIT_MASK_LPF_C2_1_0_8814B)
+#define BIT_SET_LPF_C2_1_0_8814B(x, v)                                         \
+	(BIT_CLEAR_LPF_C2_1_0_8814B(x) | BIT_LPF_C2_1_0_8814B(v))
+
+#define BIT_SHIFT_LPF_C1_5_0_8814B 24
+#define BIT_MASK_LPF_C1_5_0_8814B 0x3f
+#define BIT_LPF_C1_5_0_8814B(x)                                                \
+	(((x) & BIT_MASK_LPF_C1_5_0_8814B) << BIT_SHIFT_LPF_C1_5_0_8814B)
+#define BITS_LPF_C1_5_0_8814B                                                  \
+	(BIT_MASK_LPF_C1_5_0_8814B << BIT_SHIFT_LPF_C1_5_0_8814B)
+#define BIT_CLEAR_LPF_C1_5_0_8814B(x) ((x) & (~BITS_LPF_C1_5_0_8814B))
+#define BIT_GET_LPF_C1_5_0_8814B(x)                                            \
+	(((x) >> BIT_SHIFT_LPF_C1_5_0_8814B) & BIT_MASK_LPF_C1_5_0_8814B)
+#define BIT_SET_LPF_C1_5_0_8814B(x, v)                                         \
+	(BIT_CLEAR_LPF_C1_5_0_8814B(x) | BIT_LPF_C1_5_0_8814B(v))
+
+#define BIT_LPF_TIEL_8814B BIT(23)
+#define BIT_LPF_TIEH_8814B BIT(22)
+
+#define BIT_SHIFT_LOCKDET_VREF_L_1_0_8814B 20
+#define BIT_MASK_LOCKDET_VREF_L_1_0_8814B 0x3
+#define BIT_LOCKDET_VREF_L_1_0_8814B(x)                                        \
+	(((x) & BIT_MASK_LOCKDET_VREF_L_1_0_8814B)                             \
+	 << BIT_SHIFT_LOCKDET_VREF_L_1_0_8814B)
+#define BITS_LOCKDET_VREF_L_1_0_8814B                                          \
+	(BIT_MASK_LOCKDET_VREF_L_1_0_8814B                                     \
+	 << BIT_SHIFT_LOCKDET_VREF_L_1_0_8814B)
+#define BIT_CLEAR_LOCKDET_VREF_L_1_0_8814B(x)                                  \
+	((x) & (~BITS_LOCKDET_VREF_L_1_0_8814B))
+#define BIT_GET_LOCKDET_VREF_L_1_0_8814B(x)                                    \
+	(((x) >> BIT_SHIFT_LOCKDET_VREF_L_1_0_8814B) &                         \
+	 BIT_MASK_LOCKDET_VREF_L_1_0_8814B)
+#define BIT_SET_LOCKDET_VREF_L_1_0_8814B(x, v)                                 \
+	(BIT_CLEAR_LOCKDET_VREF_L_1_0_8814B(x) |                               \
+	 BIT_LOCKDET_VREF_L_1_0_8814B(v))
+
+#define BIT_SHIFT_LOCKDET_VREF_H_1_0_8814B 18
+#define BIT_MASK_LOCKDET_VREF_H_1_0_8814B 0x3
+#define BIT_LOCKDET_VREF_H_1_0_8814B(x)                                        \
+	(((x) & BIT_MASK_LOCKDET_VREF_H_1_0_8814B)                             \
+	 << BIT_SHIFT_LOCKDET_VREF_H_1_0_8814B)
+#define BITS_LOCKDET_VREF_H_1_0_8814B                                          \
+	(BIT_MASK_LOCKDET_VREF_H_1_0_8814B                                     \
+	 << BIT_SHIFT_LOCKDET_VREF_H_1_0_8814B)
+#define BIT_CLEAR_LOCKDET_VREF_H_1_0_8814B(x)                                  \
+	((x) & (~BITS_LOCKDET_VREF_H_1_0_8814B))
+#define BIT_GET_LOCKDET_VREF_H_1_0_8814B(x)                                    \
+	(((x) >> BIT_SHIFT_LOCKDET_VREF_H_1_0_8814B) &                         \
+	 BIT_MASK_LOCKDET_VREF_H_1_0_8814B)
+#define BIT_SET_LOCKDET_VREF_H_1_0_8814B(x, v)                                 \
+	(BIT_CLEAR_LOCKDET_VREF_H_1_0_8814B(x) |                               \
+	 BIT_LOCKDET_VREF_H_1_0_8814B(v))
+
+#define BIT_SHIFT_LDO_SEL_1_0_8814B 16
+#define BIT_MASK_LDO_SEL_1_0_8814B 0x3
+#define BIT_LDO_SEL_1_0_8814B(x)                                               \
+	(((x) & BIT_MASK_LDO_SEL_1_0_8814B) << BIT_SHIFT_LDO_SEL_1_0_8814B)
+#define BITS_LDO_SEL_1_0_8814B                                                 \
+	(BIT_MASK_LDO_SEL_1_0_8814B << BIT_SHIFT_LDO_SEL_1_0_8814B)
+#define BIT_CLEAR_LDO_SEL_1_0_8814B(x) ((x) & (~BITS_LDO_SEL_1_0_8814B))
+#define BIT_GET_LDO_SEL_1_0_8814B(x)                                           \
+	(((x) >> BIT_SHIFT_LDO_SEL_1_0_8814B) & BIT_MASK_LDO_SEL_1_0_8814B)
+#define BIT_SET_LDO_SEL_1_0_8814B(x, v)                                        \
+	(BIT_CLEAR_LDO_SEL_1_0_8814B(x) | BIT_LDO_SEL_1_0_8814B(v))
+
+#define BIT_SHIFT_IOFFSET_5_0_8814B 10
+#define BIT_MASK_IOFFSET_5_0_8814B 0x3f
+#define BIT_IOFFSET_5_0_8814B(x)                                               \
+	(((x) & BIT_MASK_IOFFSET_5_0_8814B) << BIT_SHIFT_IOFFSET_5_0_8814B)
+#define BITS_IOFFSET_5_0_8814B                                                 \
+	(BIT_MASK_IOFFSET_5_0_8814B << BIT_SHIFT_IOFFSET_5_0_8814B)
+#define BIT_CLEAR_IOFFSET_5_0_8814B(x) ((x) & (~BITS_IOFFSET_5_0_8814B))
+#define BIT_GET_IOFFSET_5_0_8814B(x)                                           \
+	(((x) >> BIT_SHIFT_IOFFSET_5_0_8814B) & BIT_MASK_IOFFSET_5_0_8814B)
+#define BIT_SET_IOFFSET_5_0_8814B(x, v)                                        \
+	(BIT_CLEAR_IOFFSET_5_0_8814B(x) | BIT_IOFFSET_5_0_8814B(v))
+
+#define BIT_CP_ICPX2_8814B BIT(9)
+
+#define BIT_SHIFT_CP_ICP_SEL_4_0_8814B 4
+#define BIT_MASK_CP_ICP_SEL_4_0_8814B 0x1f
+#define BIT_CP_ICP_SEL_4_0_8814B(x)                                            \
+	(((x) & BIT_MASK_CP_ICP_SEL_4_0_8814B)                                 \
+	 << BIT_SHIFT_CP_ICP_SEL_4_0_8814B)
+#define BITS_CP_ICP_SEL_4_0_8814B                                              \
+	(BIT_MASK_CP_ICP_SEL_4_0_8814B << BIT_SHIFT_CP_ICP_SEL_4_0_8814B)
+#define BIT_CLEAR_CP_ICP_SEL_4_0_8814B(x) ((x) & (~BITS_CP_ICP_SEL_4_0_8814B))
+#define BIT_GET_CP_ICP_SEL_4_0_8814B(x)                                        \
+	(((x) >> BIT_SHIFT_CP_ICP_SEL_4_0_8814B) &                             \
+	 BIT_MASK_CP_ICP_SEL_4_0_8814B)
+#define BIT_SET_CP_ICP_SEL_4_0_8814B(x, v)                                     \
+	(BIT_CLEAR_CP_ICP_SEL_4_0_8814B(x) | BIT_CP_ICP_SEL_4_0_8814B(v))
+
+#define BIT_SHIFT_IB_PI_1_0_8814B 2
+#define BIT_MASK_IB_PI_1_0_8814B 0x3
+#define BIT_IB_PI_1_0_8814B(x)                                                 \
+	(((x) & BIT_MASK_IB_PI_1_0_8814B) << BIT_SHIFT_IB_PI_1_0_8814B)
+#define BITS_IB_PI_1_0_8814B                                                   \
+	(BIT_MASK_IB_PI_1_0_8814B << BIT_SHIFT_IB_PI_1_0_8814B)
+#define BIT_CLEAR_IB_PI_1_0_8814B(x) ((x) & (~BITS_IB_PI_1_0_8814B))
+#define BIT_GET_IB_PI_1_0_8814B(x)                                             \
+	(((x) >> BIT_SHIFT_IB_PI_1_0_8814B) & BIT_MASK_IB_PI_1_0_8814B)
+#define BIT_SET_IB_PI_1_0_8814B(x, v)                                          \
+	(BIT_CLEAR_IB_PI_1_0_8814B(x) | BIT_IB_PI_1_0_8814B(v))
+
+#define BIT_SHIFT_LDO_VSEL_8814B 0
+#define BIT_MASK_LDO_VSEL_8814B 0x3
+#define BIT_LDO_VSEL_8814B(x)                                                  \
+	(((x) & BIT_MASK_LDO_VSEL_8814B) << BIT_SHIFT_LDO_VSEL_8814B)
+#define BITS_LDO_VSEL_8814B                                                    \
+	(BIT_MASK_LDO_VSEL_8814B << BIT_SHIFT_LDO_VSEL_8814B)
+#define BIT_CLEAR_LDO_VSEL_8814B(x) ((x) & (~BITS_LDO_VSEL_8814B))
+#define BIT_GET_LDO_VSEL_8814B(x)                                              \
+	(((x) >> BIT_SHIFT_LDO_VSEL_8814B) & BIT_MASK_LDO_VSEL_8814B)
+#define BIT_SET_LDO_VSEL_8814B(x, v)                                           \
+	(BIT_CLEAR_LDO_VSEL_8814B(x) | BIT_LDO_VSEL_8814B(v))
+
+/* 2 REG_ANAPAR_MAC_1_8814B */
+
+#define BIT_SHIFT_CKX_USB_IB_SEL_8814B 29
+#define BIT_MASK_CKX_USB_IB_SEL_8814B 0x7
+#define BIT_CKX_USB_IB_SEL_8814B(x)                                            \
+	(((x) & BIT_MASK_CKX_USB_IB_SEL_8814B)                                 \
+	 << BIT_SHIFT_CKX_USB_IB_SEL_8814B)
+#define BITS_CKX_USB_IB_SEL_8814B                                              \
+	(BIT_MASK_CKX_USB_IB_SEL_8814B << BIT_SHIFT_CKX_USB_IB_SEL_8814B)
+#define BIT_CLEAR_CKX_USB_IB_SEL_8814B(x) ((x) & (~BITS_CKX_USB_IB_SEL_8814B))
+#define BIT_GET_CKX_USB_IB_SEL_8814B(x)                                        \
+	(((x) >> BIT_SHIFT_CKX_USB_IB_SEL_8814B) &                             \
+	 BIT_MASK_CKX_USB_IB_SEL_8814B)
+#define BIT_SET_CKX_USB_IB_SEL_8814B(x, v)                                     \
+	(BIT_CLEAR_CKX_USB_IB_SEL_8814B(x) | BIT_CKX_USB_IB_SEL_8814B(v))
+
+#define BIT_PFD_DN_GATED_8814B BIT(28)
+#define BIT_PFD_UP_GATED_8814B BIT(27)
+#define BIT_PFD_RESET_GATED_8814B BIT(26)
+
+#define BIT_SHIFT_PFD_OUT_DRV_1_0_8814B 24
+#define BIT_MASK_PFD_OUT_DRV_1_0_8814B 0x3
+#define BIT_PFD_OUT_DRV_1_0_8814B(x)                                           \
+	(((x) & BIT_MASK_PFD_OUT_DRV_1_0_8814B)                                \
+	 << BIT_SHIFT_PFD_OUT_DRV_1_0_8814B)
+#define BITS_PFD_OUT_DRV_1_0_8814B                                             \
+	(BIT_MASK_PFD_OUT_DRV_1_0_8814B << BIT_SHIFT_PFD_OUT_DRV_1_0_8814B)
+#define BIT_CLEAR_PFD_OUT_DRV_1_0_8814B(x) ((x) & (~BITS_PFD_OUT_DRV_1_0_8814B))
+#define BIT_GET_PFD_OUT_DRV_1_0_8814B(x)                                       \
+	(((x) >> BIT_SHIFT_PFD_OUT_DRV_1_0_8814B) &                            \
+	 BIT_MASK_PFD_OUT_DRV_1_0_8814B)
+#define BIT_SET_PFD_OUT_DRV_1_0_8814B(x, v)                                    \
+	(BIT_CLEAR_PFD_OUT_DRV_1_0_8814B(x) | BIT_PFD_OUT_DRV_1_0_8814B(v))
+
+#define BIT_SHIFT_LPF_TIEMID_2_0_8814B 20
+#define BIT_MASK_LPF_TIEMID_2_0_8814B 0x7
+#define BIT_LPF_TIEMID_2_0_8814B(x)                                            \
+	(((x) & BIT_MASK_LPF_TIEMID_2_0_8814B)                                 \
+	 << BIT_SHIFT_LPF_TIEMID_2_0_8814B)
+#define BITS_LPF_TIEMID_2_0_8814B                                              \
+	(BIT_MASK_LPF_TIEMID_2_0_8814B << BIT_SHIFT_LPF_TIEMID_2_0_8814B)
+#define BIT_CLEAR_LPF_TIEMID_2_0_8814B(x) ((x) & (~BITS_LPF_TIEMID_2_0_8814B))
+#define BIT_GET_LPF_TIEMID_2_0_8814B(x)                                        \
+	(((x) >> BIT_SHIFT_LPF_TIEMID_2_0_8814B) &                             \
+	 BIT_MASK_LPF_TIEMID_2_0_8814B)
+#define BIT_SET_LPF_TIEMID_2_0_8814B(x, v)                                     \
+	(BIT_CLEAR_LPF_TIEMID_2_0_8814B(x) | BIT_LPF_TIEMID_2_0_8814B(v))
+
+#define BIT_SHIFT_LPF_R3_4_0_8814B 15
+#define BIT_MASK_LPF_R3_4_0_8814B 0x1f
+#define BIT_LPF_R3_4_0_8814B(x)                                                \
+	(((x) & BIT_MASK_LPF_R3_4_0_8814B) << BIT_SHIFT_LPF_R3_4_0_8814B)
+#define BITS_LPF_R3_4_0_8814B                                                  \
+	(BIT_MASK_LPF_R3_4_0_8814B << BIT_SHIFT_LPF_R3_4_0_8814B)
+#define BIT_CLEAR_LPF_R3_4_0_8814B(x) ((x) & (~BITS_LPF_R3_4_0_8814B))
+#define BIT_GET_LPF_R3_4_0_8814B(x)                                            \
+	(((x) >> BIT_SHIFT_LPF_R3_4_0_8814B) & BIT_MASK_LPF_R3_4_0_8814B)
+#define BIT_SET_LPF_R3_4_0_8814B(x, v)                                         \
+	(BIT_CLEAR_LPF_R3_4_0_8814B(x) | BIT_LPF_R3_4_0_8814B(v))
+
+#define BIT_SHIFT_LPF_R2_4_0_8814B 10
+#define BIT_MASK_LPF_R2_4_0_8814B 0x1f
+#define BIT_LPF_R2_4_0_8814B(x)                                                \
+	(((x) & BIT_MASK_LPF_R2_4_0_8814B) << BIT_SHIFT_LPF_R2_4_0_8814B)
+#define BITS_LPF_R2_4_0_8814B                                                  \
+	(BIT_MASK_LPF_R2_4_0_8814B << BIT_SHIFT_LPF_R2_4_0_8814B)
+#define BIT_CLEAR_LPF_R2_4_0_8814B(x) ((x) & (~BITS_LPF_R2_4_0_8814B))
+#define BIT_GET_LPF_R2_4_0_8814B(x)                                            \
+	(((x) >> BIT_SHIFT_LPF_R2_4_0_8814B) & BIT_MASK_LPF_R2_4_0_8814B)
+#define BIT_SET_LPF_R2_4_0_8814B(x, v)                                         \
+	(BIT_CLEAR_LPF_R2_4_0_8814B(x) | BIT_LPF_R2_4_0_8814B(v))
+
+#define BIT_SHIFT_LPF_C3_5_0_8814B 4
+#define BIT_MASK_LPF_C3_5_0_8814B 0x3f
+#define BIT_LPF_C3_5_0_8814B(x)                                                \
+	(((x) & BIT_MASK_LPF_C3_5_0_8814B) << BIT_SHIFT_LPF_C3_5_0_8814B)
+#define BITS_LPF_C3_5_0_8814B                                                  \
+	(BIT_MASK_LPF_C3_5_0_8814B << BIT_SHIFT_LPF_C3_5_0_8814B)
+#define BIT_CLEAR_LPF_C3_5_0_8814B(x) ((x) & (~BITS_LPF_C3_5_0_8814B))
+#define BIT_GET_LPF_C3_5_0_8814B(x)                                            \
+	(((x) >> BIT_SHIFT_LPF_C3_5_0_8814B) & BIT_MASK_LPF_C3_5_0_8814B)
+#define BIT_SET_LPF_C3_5_0_8814B(x, v)                                         \
+	(BIT_CLEAR_LPF_C3_5_0_8814B(x) | BIT_LPF_C3_5_0_8814B(v))
+
+#define BIT_SHIFT_LPF_C2_5_2_8814B 0
+#define BIT_MASK_LPF_C2_5_2_8814B 0xf
+#define BIT_LPF_C2_5_2_8814B(x)                                                \
+	(((x) & BIT_MASK_LPF_C2_5_2_8814B) << BIT_SHIFT_LPF_C2_5_2_8814B)
+#define BITS_LPF_C2_5_2_8814B                                                  \
+	(BIT_MASK_LPF_C2_5_2_8814B << BIT_SHIFT_LPF_C2_5_2_8814B)
+#define BIT_CLEAR_LPF_C2_5_2_8814B(x) ((x) & (~BITS_LPF_C2_5_2_8814B))
+#define BIT_GET_LPF_C2_5_2_8814B(x)                                            \
+	(((x) >> BIT_SHIFT_LPF_C2_5_2_8814B) & BIT_MASK_LPF_C2_5_2_8814B)
+#define BIT_SET_LPF_C2_5_2_8814B(x, v)                                         \
+	(BIT_CLEAR_LPF_C2_5_2_8814B(x) | BIT_LPF_C2_5_2_8814B(v))
+
+/* 2 REG_ANAPAR_MAC_2_8814B */
+#define BIT_CK_PHASE_SEL_8814B BIT(31)
+#define BIT_CK960M_EN_8814B BIT(30)
+#define BIT_CK640M_EN_8814B BIT(29)
+#define BIT_CK240M_EN_8814B BIT(28)
+
+#define BIT_SHIFT_CK_MON_SEL_2_0_8814B 25
+#define BIT_MASK_CK_MON_SEL_2_0_8814B 0x7
+#define BIT_CK_MON_SEL_2_0_8814B(x)                                            \
+	(((x) & BIT_MASK_CK_MON_SEL_2_0_8814B)                                 \
+	 << BIT_SHIFT_CK_MON_SEL_2_0_8814B)
+#define BITS_CK_MON_SEL_2_0_8814B                                              \
+	(BIT_MASK_CK_MON_SEL_2_0_8814B << BIT_SHIFT_CK_MON_SEL_2_0_8814B)
+#define BIT_CLEAR_CK_MON_SEL_2_0_8814B(x) ((x) & (~BITS_CK_MON_SEL_2_0_8814B))
+#define BIT_GET_CK_MON_SEL_2_0_8814B(x)                                        \
+	(((x) >> BIT_SHIFT_CK_MON_SEL_2_0_8814B) &                             \
+	 BIT_MASK_CK_MON_SEL_2_0_8814B)
+#define BIT_SET_CK_MON_SEL_2_0_8814B(x, v)                                     \
+	(BIT_CLEAR_CK_MON_SEL_2_0_8814B(x) | BIT_CK_MON_SEL_2_0_8814B(v))
+
+#define BIT_CK_MON_EN_V1_8814B BIT(24)
+#define BIT_XTAL_SOURCE_SEL_8814B BIT(23)
+#define BIT_XTAL_FREQ_SEL_8814B BIT(22)
+#define BIT_XTAL_EDGE_SEL_8814B BIT(21)
+#define BIT_XTAL_BUF_SEL_8814B BIT(20)
+
+#define BIT_SHIFT_VCO_CV_7_0_8814B 4
+#define BIT_MASK_VCO_CV_7_0_8814B 0xff
+#define BIT_VCO_CV_7_0_8814B(x)                                                \
+	(((x) & BIT_MASK_VCO_CV_7_0_8814B) << BIT_SHIFT_VCO_CV_7_0_8814B)
+#define BITS_VCO_CV_7_0_8814B                                                  \
+	(BIT_MASK_VCO_CV_7_0_8814B << BIT_SHIFT_VCO_CV_7_0_8814B)
+#define BIT_CLEAR_VCO_CV_7_0_8814B(x) ((x) & (~BITS_VCO_CV_7_0_8814B))
+#define BIT_GET_VCO_CV_7_0_8814B(x)                                            \
+	(((x) >> BIT_SHIFT_VCO_CV_7_0_8814B) & BIT_MASK_VCO_CV_7_0_8814B)
+#define BIT_SET_VCO_CV_7_0_8814B(x, v)                                         \
+	(BIT_CLEAR_VCO_CV_7_0_8814B(x) | BIT_VCO_CV_7_0_8814B(v))
+
+#define BIT_VCO_KVCO_8814B BIT(3)
+#define BIT_SDM_EDGE_SEL_8814B BIT(2)
+#define BIT_SDM_CK_SEL_8814B BIT(1)
+#define BIT_SDM_CK_GATED_8814B BIT(0)
+
+/* 2 REG_ANAPAR_MAC_3_8814B */
+
+#define BIT_SHIFT_LCK_WAIT_CYCLE_2_0_8814B 28
+#define BIT_MASK_LCK_WAIT_CYCLE_2_0_8814B 0x7
+#define BIT_LCK_WAIT_CYCLE_2_0_8814B(x)                                        \
+	(((x) & BIT_MASK_LCK_WAIT_CYCLE_2_0_8814B)                             \
+	 << BIT_SHIFT_LCK_WAIT_CYCLE_2_0_8814B)
+#define BITS_LCK_WAIT_CYCLE_2_0_8814B                                          \
+	(BIT_MASK_LCK_WAIT_CYCLE_2_0_8814B                                     \
+	 << BIT_SHIFT_LCK_WAIT_CYCLE_2_0_8814B)
+#define BIT_CLEAR_LCK_WAIT_CYCLE_2_0_8814B(x)                                  \
+	((x) & (~BITS_LCK_WAIT_CYCLE_2_0_8814B))
+#define BIT_GET_LCK_WAIT_CYCLE_2_0_8814B(x)                                    \
+	(((x) >> BIT_SHIFT_LCK_WAIT_CYCLE_2_0_8814B) &                         \
+	 BIT_MASK_LCK_WAIT_CYCLE_2_0_8814B)
+#define BIT_SET_LCK_WAIT_CYCLE_2_0_8814B(x, v)                                 \
+	(BIT_CLEAR_LCK_WAIT_CYCLE_2_0_8814B(x) |                               \
+	 BIT_LCK_WAIT_CYCLE_2_0_8814B(v))
+
+#define BIT_SHIFT_LCK_VCO_DIVISOR_1_0_8814B 26
+#define BIT_MASK_LCK_VCO_DIVISOR_1_0_8814B 0x3
+#define BIT_LCK_VCO_DIVISOR_1_0_8814B(x)                                       \
+	(((x) & BIT_MASK_LCK_VCO_DIVISOR_1_0_8814B)                            \
+	 << BIT_SHIFT_LCK_VCO_DIVISOR_1_0_8814B)
+#define BITS_LCK_VCO_DIVISOR_1_0_8814B                                         \
+	(BIT_MASK_LCK_VCO_DIVISOR_1_0_8814B                                    \
+	 << BIT_SHIFT_LCK_VCO_DIVISOR_1_0_8814B)
+#define BIT_CLEAR_LCK_VCO_DIVISOR_1_0_8814B(x)                                 \
+	((x) & (~BITS_LCK_VCO_DIVISOR_1_0_8814B))
+#define BIT_GET_LCK_VCO_DIVISOR_1_0_8814B(x)                                   \
+	(((x) >> BIT_SHIFT_LCK_VCO_DIVISOR_1_0_8814B) &                        \
+	 BIT_MASK_LCK_VCO_DIVISOR_1_0_8814B)
+#define BIT_SET_LCK_VCO_DIVISOR_1_0_8814B(x, v)                                \
+	(BIT_CLEAR_LCK_VCO_DIVISOR_1_0_8814B(x) |                              \
+	 BIT_LCK_VCO_DIVISOR_1_0_8814B(v))
+
+#define BIT_SHIFT_LCK_SEARCH_MODE_1_0_8814B 24
+#define BIT_MASK_LCK_SEARCH_MODE_1_0_8814B 0x3
+#define BIT_LCK_SEARCH_MODE_1_0_8814B(x)                                       \
+	(((x) & BIT_MASK_LCK_SEARCH_MODE_1_0_8814B)                            \
+	 << BIT_SHIFT_LCK_SEARCH_MODE_1_0_8814B)
+#define BITS_LCK_SEARCH_MODE_1_0_8814B                                         \
+	(BIT_MASK_LCK_SEARCH_MODE_1_0_8814B                                    \
+	 << BIT_SHIFT_LCK_SEARCH_MODE_1_0_8814B)
+#define BIT_CLEAR_LCK_SEARCH_MODE_1_0_8814B(x)                                 \
+	((x) & (~BITS_LCK_SEARCH_MODE_1_0_8814B))
+#define BIT_GET_LCK_SEARCH_MODE_1_0_8814B(x)                                   \
+	(((x) >> BIT_SHIFT_LCK_SEARCH_MODE_1_0_8814B) &                        \
+	 BIT_MASK_LCK_SEARCH_MODE_1_0_8814B)
+#define BIT_SET_LCK_SEARCH_MODE_1_0_8814B(x, v)                                \
+	(BIT_CLEAR_LCK_SEARCH_MODE_1_0_8814B(x) |                              \
+	 BIT_LCK_SEARCH_MODE_1_0_8814B(v))
+
+#define BIT_SHIFT_LS_CV_OFFSET_3_0_8814B 12
+#define BIT_MASK_LS_CV_OFFSET_3_0_8814B 0xf
+#define BIT_LS_CV_OFFSET_3_0_8814B(x)                                          \
+	(((x) & BIT_MASK_LS_CV_OFFSET_3_0_8814B)                               \
+	 << BIT_SHIFT_LS_CV_OFFSET_3_0_8814B)
+#define BITS_LS_CV_OFFSET_3_0_8814B                                            \
+	(BIT_MASK_LS_CV_OFFSET_3_0_8814B << BIT_SHIFT_LS_CV_OFFSET_3_0_8814B)
+#define BIT_CLEAR_LS_CV_OFFSET_3_0_8814B(x)                                    \
+	((x) & (~BITS_LS_CV_OFFSET_3_0_8814B))
+#define BIT_GET_LS_CV_OFFSET_3_0_8814B(x)                                      \
+	(((x) >> BIT_SHIFT_LS_CV_OFFSET_3_0_8814B) &                           \
+	 BIT_MASK_LS_CV_OFFSET_3_0_8814B)
+#define BIT_SET_LS_CV_OFFSET_3_0_8814B(x, v)                                   \
+	(BIT_CLEAR_LS_CV_OFFSET_3_0_8814B(x) | BIT_LS_CV_OFFSET_3_0_8814B(v))
+
+#define BIT_LS_EN_LC_CK40M_8814B BIT(11)
+#define BIT_LS__CV_MANUAL_8814B BIT(10)
+#define BIT_LS_PYPASS_PI_8814B BIT(9)
+#define BIT_MBIASE_8814B BIT(4)
+
+/* 2 REG_ANAPAR_MAC_4_8814B */
+#define BIT_LS_TIE_MID_MODE_8814B BIT(28)
+
+#define BIT_SHIFT_LS_SYNC_CYCLE_1_0_8814B 26
+#define BIT_MASK_LS_SYNC_CYCLE_1_0_8814B 0x3
+#define BIT_LS_SYNC_CYCLE_1_0_8814B(x)                                         \
+	(((x) & BIT_MASK_LS_SYNC_CYCLE_1_0_8814B)                              \
+	 << BIT_SHIFT_LS_SYNC_CYCLE_1_0_8814B)
+#define BITS_LS_SYNC_CYCLE_1_0_8814B                                           \
+	(BIT_MASK_LS_SYNC_CYCLE_1_0_8814B << BIT_SHIFT_LS_SYNC_CYCLE_1_0_8814B)
+#define BIT_CLEAR_LS_SYNC_CYCLE_1_0_8814B(x)                                   \
+	((x) & (~BITS_LS_SYNC_CYCLE_1_0_8814B))
+#define BIT_GET_LS_SYNC_CYCLE_1_0_8814B(x)                                     \
+	(((x) >> BIT_SHIFT_LS_SYNC_CYCLE_1_0_8814B) &                          \
+	 BIT_MASK_LS_SYNC_CYCLE_1_0_8814B)
+#define BIT_SET_LS_SYNC_CYCLE_1_0_8814B(x, v)                                  \
+	(BIT_CLEAR_LS_SYNC_CYCLE_1_0_8814B(x) | BIT_LS_SYNC_CYCLE_1_0_8814B(v))
+
+#define BIT_LS_SDM_ORDER_8814B BIT(25)
+#define BIT_LS_RST_LC_CAL_8814B BIT(14)
+#define BIT_LS_RSTB_8814B BIT(13)
+#define BIT_LS_POW_LC_CAL_PREP_8814B BIT(11)
+
+#define BIT_SHIFT_LCK_XTAL_DIVISOR_1_0_8814B 0
+#define BIT_MASK_LCK_XTAL_DIVISOR_1_0_8814B 0x3
+#define BIT_LCK_XTAL_DIVISOR_1_0_8814B(x)                                      \
+	(((x) & BIT_MASK_LCK_XTAL_DIVISOR_1_0_8814B)                           \
+	 << BIT_SHIFT_LCK_XTAL_DIVISOR_1_0_8814B)
+#define BITS_LCK_XTAL_DIVISOR_1_0_8814B                                        \
+	(BIT_MASK_LCK_XTAL_DIVISOR_1_0_8814B                                   \
+	 << BIT_SHIFT_LCK_XTAL_DIVISOR_1_0_8814B)
+#define BIT_CLEAR_LCK_XTAL_DIVISOR_1_0_8814B(x)                                \
+	((x) & (~BITS_LCK_XTAL_DIVISOR_1_0_8814B))
+#define BIT_GET_LCK_XTAL_DIVISOR_1_0_8814B(x)                                  \
+	(((x) >> BIT_SHIFT_LCK_XTAL_DIVISOR_1_0_8814B) &                       \
+	 BIT_MASK_LCK_XTAL_DIVISOR_1_0_8814B)
+#define BIT_SET_LCK_XTAL_DIVISOR_1_0_8814B(x, v)                               \
+	(BIT_CLEAR_LCK_XTAL_DIVISOR_1_0_8814B(x) |                             \
+	 BIT_LCK_XTAL_DIVISOR_1_0_8814B(v))
+
+/* 2 REG_ANAPAR_MAC_5_8814B */
+
+#define BIT_SHIFT_LS_XTAL_SEL_3_0_8814B 0
+#define BIT_MASK_LS_XTAL_SEL_3_0_8814B 0xf
+#define BIT_LS_XTAL_SEL_3_0_8814B(x)                                           \
+	(((x) & BIT_MASK_LS_XTAL_SEL_3_0_8814B)                                \
+	 << BIT_SHIFT_LS_XTAL_SEL_3_0_8814B)
+#define BITS_LS_XTAL_SEL_3_0_8814B                                             \
+	(BIT_MASK_LS_XTAL_SEL_3_0_8814B << BIT_SHIFT_LS_XTAL_SEL_3_0_8814B)
+#define BIT_CLEAR_LS_XTAL_SEL_3_0_8814B(x) ((x) & (~BITS_LS_XTAL_SEL_3_0_8814B))
+#define BIT_GET_LS_XTAL_SEL_3_0_8814B(x)                                       \
+	(((x) >> BIT_SHIFT_LS_XTAL_SEL_3_0_8814B) &                            \
+	 BIT_MASK_LS_XTAL_SEL_3_0_8814B)
+#define BIT_SET_LS_XTAL_SEL_3_0_8814B(x, v)                                    \
+	(BIT_CLEAR_LS_XTAL_SEL_3_0_8814B(x) | BIT_LS_XTAL_SEL_3_0_8814B(v))
+
+/* 2 REG_ANAPAR_MAC_6_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_ANAPAR_MAC_7_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_ANAPAR_MAC_8_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_ANAPAR_XTAL_0_8814B */
+#define BIT_XTAL_DRV_RF1_0_8814B BIT(31)
+#define BIT_XTAL_GATED_RF1N_8814B BIT(30)
+#define BIT_XTAL_GATED_RF1P_8814B BIT(29)
+#define BIT_XTAL_GM_SEP_V2_8814B BIT(28)
+
+#define BIT_SHIFT_XTAL_LDO_1_0_8814B 26
+#define BIT_MASK_XTAL_LDO_1_0_8814B 0x3
+#define BIT_XTAL_LDO_1_0_8814B(x)                                              \
+	(((x) & BIT_MASK_XTAL_LDO_1_0_8814B) << BIT_SHIFT_XTAL_LDO_1_0_8814B)
+#define BITS_XTAL_LDO_1_0_8814B                                                \
+	(BIT_MASK_XTAL_LDO_1_0_8814B << BIT_SHIFT_XTAL_LDO_1_0_8814B)
+#define BIT_CLEAR_XTAL_LDO_1_0_8814B(x) ((x) & (~BITS_XTAL_LDO_1_0_8814B))
+#define BIT_GET_XTAL_LDO_1_0_8814B(x)                                          \
+	(((x) >> BIT_SHIFT_XTAL_LDO_1_0_8814B) & BIT_MASK_XTAL_LDO_1_0_8814B)
+#define BIT_SET_XTAL_LDO_1_0_8814B(x, v)                                       \
+	(BIT_CLEAR_XTAL_LDO_1_0_8814B(x) | BIT_XTAL_LDO_1_0_8814B(v))
+
+#define BIT_XQSEL_V1_8814B BIT(25)
+#define BIT_GATED_XTAL_OK0_8814B BIT(24)
+
+#define BIT_SHIFT_XTAL_SC_XO_6_0_8814B 17
+#define BIT_MASK_XTAL_SC_XO_6_0_8814B 0x7f
+#define BIT_XTAL_SC_XO_6_0_8814B(x)                                            \
+	(((x) & BIT_MASK_XTAL_SC_XO_6_0_8814B)                                 \
+	 << BIT_SHIFT_XTAL_SC_XO_6_0_8814B)
+#define BITS_XTAL_SC_XO_6_0_8814B                                              \
+	(BIT_MASK_XTAL_SC_XO_6_0_8814B << BIT_SHIFT_XTAL_SC_XO_6_0_8814B)
+#define BIT_CLEAR_XTAL_SC_XO_6_0_8814B(x) ((x) & (~BITS_XTAL_SC_XO_6_0_8814B))
+#define BIT_GET_XTAL_SC_XO_6_0_8814B(x)                                        \
+	(((x) >> BIT_SHIFT_XTAL_SC_XO_6_0_8814B) &                             \
+	 BIT_MASK_XTAL_SC_XO_6_0_8814B)
+#define BIT_SET_XTAL_SC_XO_6_0_8814B(x, v)                                     \
+	(BIT_CLEAR_XTAL_SC_XO_6_0_8814B(x) | BIT_XTAL_SC_XO_6_0_8814B(v))
+
+#define BIT_SHIFT_XTAL_SC_XI_6_0_8814B 10
+#define BIT_MASK_XTAL_SC_XI_6_0_8814B 0x7f
+#define BIT_XTAL_SC_XI_6_0_8814B(x)                                            \
+	(((x) & BIT_MASK_XTAL_SC_XI_6_0_8814B)                                 \
+	 << BIT_SHIFT_XTAL_SC_XI_6_0_8814B)
+#define BITS_XTAL_SC_XI_6_0_8814B                                              \
+	(BIT_MASK_XTAL_SC_XI_6_0_8814B << BIT_SHIFT_XTAL_SC_XI_6_0_8814B)
+#define BIT_CLEAR_XTAL_SC_XI_6_0_8814B(x) ((x) & (~BITS_XTAL_SC_XI_6_0_8814B))
+#define BIT_GET_XTAL_SC_XI_6_0_8814B(x)                                        \
+	(((x) >> BIT_SHIFT_XTAL_SC_XI_6_0_8814B) &                             \
+	 BIT_MASK_XTAL_SC_XI_6_0_8814B)
+#define BIT_SET_XTAL_SC_XI_6_0_8814B(x, v)                                     \
+	(BIT_CLEAR_XTAL_SC_XI_6_0_8814B(x) | BIT_XTAL_SC_XI_6_0_8814B(v))
+
+#define BIT_SHIFT_XTAL_GMN_4_0_8814B 5
+#define BIT_MASK_XTAL_GMN_4_0_8814B 0x1f
+#define BIT_XTAL_GMN_4_0_8814B(x)                                              \
+	(((x) & BIT_MASK_XTAL_GMN_4_0_8814B) << BIT_SHIFT_XTAL_GMN_4_0_8814B)
+#define BITS_XTAL_GMN_4_0_8814B                                                \
+	(BIT_MASK_XTAL_GMN_4_0_8814B << BIT_SHIFT_XTAL_GMN_4_0_8814B)
+#define BIT_CLEAR_XTAL_GMN_4_0_8814B(x) ((x) & (~BITS_XTAL_GMN_4_0_8814B))
+#define BIT_GET_XTAL_GMN_4_0_8814B(x)                                          \
+	(((x) >> BIT_SHIFT_XTAL_GMN_4_0_8814B) & BIT_MASK_XTAL_GMN_4_0_8814B)
+#define BIT_SET_XTAL_GMN_4_0_8814B(x, v)                                       \
+	(BIT_CLEAR_XTAL_GMN_4_0_8814B(x) | BIT_XTAL_GMN_4_0_8814B(v))
+
+#define BIT_SHIFT_XTAL_GMP_4_0_8814B 0
+#define BIT_MASK_XTAL_GMP_4_0_8814B 0x1f
+#define BIT_XTAL_GMP_4_0_8814B(x)                                              \
+	(((x) & BIT_MASK_XTAL_GMP_4_0_8814B) << BIT_SHIFT_XTAL_GMP_4_0_8814B)
+#define BITS_XTAL_GMP_4_0_8814B                                                \
+	(BIT_MASK_XTAL_GMP_4_0_8814B << BIT_SHIFT_XTAL_GMP_4_0_8814B)
+#define BIT_CLEAR_XTAL_GMP_4_0_8814B(x) ((x) & (~BITS_XTAL_GMP_4_0_8814B))
+#define BIT_GET_XTAL_GMP_4_0_8814B(x)                                          \
+	(((x) >> BIT_SHIFT_XTAL_GMP_4_0_8814B) & BIT_MASK_XTAL_GMP_4_0_8814B)
+#define BIT_SET_XTAL_GMP_4_0_8814B(x, v)                                       \
+	(BIT_CLEAR_XTAL_GMP_4_0_8814B(x) | BIT_XTAL_GMP_4_0_8814B(v))
+
+/* 2 REG_ANAPAR_XTAL_1_8814B */
+
+#define BIT_SHIFT_XTAL_LDO_OK_1_0_8814B 30
+#define BIT_MASK_XTAL_LDO_OK_1_0_8814B 0x3
+#define BIT_XTAL_LDO_OK_1_0_8814B(x)                                           \
+	(((x) & BIT_MASK_XTAL_LDO_OK_1_0_8814B)                                \
+	 << BIT_SHIFT_XTAL_LDO_OK_1_0_8814B)
+#define BITS_XTAL_LDO_OK_1_0_8814B                                             \
+	(BIT_MASK_XTAL_LDO_OK_1_0_8814B << BIT_SHIFT_XTAL_LDO_OK_1_0_8814B)
+#define BIT_CLEAR_XTAL_LDO_OK_1_0_8814B(x) ((x) & (~BITS_XTAL_LDO_OK_1_0_8814B))
+#define BIT_GET_XTAL_LDO_OK_1_0_8814B(x)                                       \
+	(((x) >> BIT_SHIFT_XTAL_LDO_OK_1_0_8814B) &                            \
+	 BIT_MASK_XTAL_LDO_OK_1_0_8814B)
+#define BIT_SET_XTAL_LDO_OK_1_0_8814B(x, v)                                    \
+	(BIT_CLEAR_XTAL_LDO_OK_1_0_8814B(x) | BIT_XTAL_LDO_OK_1_0_8814B(v))
+
+#define BIT_SHIFT_XTAL_XORES_SEL_2_0_8814B 27
+#define BIT_MASK_XTAL_XORES_SEL_2_0_8814B 0x7
+#define BIT_XTAL_XORES_SEL_2_0_8814B(x)                                        \
+	(((x) & BIT_MASK_XTAL_XORES_SEL_2_0_8814B)                             \
+	 << BIT_SHIFT_XTAL_XORES_SEL_2_0_8814B)
+#define BITS_XTAL_XORES_SEL_2_0_8814B                                          \
+	(BIT_MASK_XTAL_XORES_SEL_2_0_8814B                                     \
+	 << BIT_SHIFT_XTAL_XORES_SEL_2_0_8814B)
+#define BIT_CLEAR_XTAL_XORES_SEL_2_0_8814B(x)                                  \
+	((x) & (~BITS_XTAL_XORES_SEL_2_0_8814B))
+#define BIT_GET_XTAL_XORES_SEL_2_0_8814B(x)                                    \
+	(((x) >> BIT_SHIFT_XTAL_XORES_SEL_2_0_8814B) &                         \
+	 BIT_MASK_XTAL_XORES_SEL_2_0_8814B)
+#define BIT_SET_XTAL_XORES_SEL_2_0_8814B(x, v)                                 \
+	(BIT_CLEAR_XTAL_XORES_SEL_2_0_8814B(x) |                               \
+	 BIT_XTAL_XORES_SEL_2_0_8814B(v))
+
+#define BIT_SHIFT_XTAL_AAC_PK_SEL_1_0_8814B 25
+#define BIT_MASK_XTAL_AAC_PK_SEL_1_0_8814B 0x3
+#define BIT_XTAL_AAC_PK_SEL_1_0_8814B(x)                                       \
+	(((x) & BIT_MASK_XTAL_AAC_PK_SEL_1_0_8814B)                            \
+	 << BIT_SHIFT_XTAL_AAC_PK_SEL_1_0_8814B)
+#define BITS_XTAL_AAC_PK_SEL_1_0_8814B                                         \
+	(BIT_MASK_XTAL_AAC_PK_SEL_1_0_8814B                                    \
+	 << BIT_SHIFT_XTAL_AAC_PK_SEL_1_0_8814B)
+#define BIT_CLEAR_XTAL_AAC_PK_SEL_1_0_8814B(x)                                 \
+	((x) & (~BITS_XTAL_AAC_PK_SEL_1_0_8814B))
+#define BIT_GET_XTAL_AAC_PK_SEL_1_0_8814B(x)                                   \
+	(((x) >> BIT_SHIFT_XTAL_AAC_PK_SEL_1_0_8814B) &                        \
+	 BIT_MASK_XTAL_AAC_PK_SEL_1_0_8814B)
+#define BIT_SET_XTAL_AAC_PK_SEL_1_0_8814B(x, v)                                \
+	(BIT_CLEAR_XTAL_AAC_PK_SEL_1_0_8814B(x) |                              \
+	 BIT_XTAL_AAC_PK_SEL_1_0_8814B(v))
+
+#define BIT_EN_XTAL_AAC_PKDET_8814B BIT(24)
+#define BIT_EN_XTAL_AAC_GM_8814B BIT(23)
+#define BIT_XTAL_LPMODE_8814B BIT(22)
+
+#define BIT_SHIFT_XTAL_SEL_TOK_2_0_8814B 19
+#define BIT_MASK_XTAL_SEL_TOK_2_0_8814B 0x7
+#define BIT_XTAL_SEL_TOK_2_0_8814B(x)                                          \
+	(((x) & BIT_MASK_XTAL_SEL_TOK_2_0_8814B)                               \
+	 << BIT_SHIFT_XTAL_SEL_TOK_2_0_8814B)
+#define BITS_XTAL_SEL_TOK_2_0_8814B                                            \
+	(BIT_MASK_XTAL_SEL_TOK_2_0_8814B << BIT_SHIFT_XTAL_SEL_TOK_2_0_8814B)
+#define BIT_CLEAR_XTAL_SEL_TOK_2_0_8814B(x)                                    \
+	((x) & (~BITS_XTAL_SEL_TOK_2_0_8814B))
+#define BIT_GET_XTAL_SEL_TOK_2_0_8814B(x)                                      \
+	(((x) >> BIT_SHIFT_XTAL_SEL_TOK_2_0_8814B) &                           \
+	 BIT_MASK_XTAL_SEL_TOK_2_0_8814B)
+#define BIT_SET_XTAL_SEL_TOK_2_0_8814B(x, v)                                   \
+	(BIT_CLEAR_XTAL_SEL_TOK_2_0_8814B(x) | BIT_XTAL_SEL_TOK_2_0_8814B(v))
+
+#define BIT_XQSEL_RF_AWAKE_V2_8814B BIT(18)
+#define BIT_XQSEL_RF_INITIAL_V2_8814B BIT(17)
+#define BIT_XTAL_DELAY_USB_V1_8814B BIT(16)
+#define BIT_XTAL_DELAY_DIGI_V1_8814B BIT(15)
+#define BIT_XTAL_DELAY_AFE_V1_8814B BIT(14)
+#define BIT_XTAL_DRV_RF_LATCH_V3_8814B BIT(13)
+
+#define BIT_SHIFT_XTAL_DRV_DIGI_1_0_8814B 11
+#define BIT_MASK_XTAL_DRV_DIGI_1_0_8814B 0x3
+#define BIT_XTAL_DRV_DIGI_1_0_8814B(x)                                         \
+	(((x) & BIT_MASK_XTAL_DRV_DIGI_1_0_8814B)                              \
+	 << BIT_SHIFT_XTAL_DRV_DIGI_1_0_8814B)
+#define BITS_XTAL_DRV_DIGI_1_0_8814B                                           \
+	(BIT_MASK_XTAL_DRV_DIGI_1_0_8814B << BIT_SHIFT_XTAL_DRV_DIGI_1_0_8814B)
+#define BIT_CLEAR_XTAL_DRV_DIGI_1_0_8814B(x)                                   \
+	((x) & (~BITS_XTAL_DRV_DIGI_1_0_8814B))
+#define BIT_GET_XTAL_DRV_DIGI_1_0_8814B(x)                                     \
+	(((x) >> BIT_SHIFT_XTAL_DRV_DIGI_1_0_8814B) &                          \
+	 BIT_MASK_XTAL_DRV_DIGI_1_0_8814B)
+#define BIT_SET_XTAL_DRV_DIGI_1_0_8814B(x, v)                                  \
+	(BIT_CLEAR_XTAL_DRV_DIGI_1_0_8814B(x) | BIT_XTAL_DRV_DIGI_1_0_8814B(v))
+
+#define BIT_XTAL_GATED_DIGIN_8814B BIT(10)
+#define BIT_XTAL_GATED_DIGIP_8814B BIT(9)
+
+#define BIT_SHIFT_XTAL_DRV_USB_1_0_8814B 7
+#define BIT_MASK_XTAL_DRV_USB_1_0_8814B 0x3
+#define BIT_XTAL_DRV_USB_1_0_8814B(x)                                          \
+	(((x) & BIT_MASK_XTAL_DRV_USB_1_0_8814B)                               \
+	 << BIT_SHIFT_XTAL_DRV_USB_1_0_8814B)
+#define BITS_XTAL_DRV_USB_1_0_8814B                                            \
+	(BIT_MASK_XTAL_DRV_USB_1_0_8814B << BIT_SHIFT_XTAL_DRV_USB_1_0_8814B)
+#define BIT_CLEAR_XTAL_DRV_USB_1_0_8814B(x)                                    \
+	((x) & (~BITS_XTAL_DRV_USB_1_0_8814B))
+#define BIT_GET_XTAL_DRV_USB_1_0_8814B(x)                                      \
+	(((x) >> BIT_SHIFT_XTAL_DRV_USB_1_0_8814B) &                           \
+	 BIT_MASK_XTAL_DRV_USB_1_0_8814B)
+#define BIT_SET_XTAL_DRV_USB_1_0_8814B(x, v)                                   \
+	(BIT_CLEAR_XTAL_DRV_USB_1_0_8814B(x) | BIT_XTAL_DRV_USB_1_0_8814B(v))
+
+#define BIT_XTAL_GATED_USBN_8814B BIT(6)
+#define BIT_XTAL_GATED_USBP_8814B BIT(5)
+
+#define BIT_SHIFT_XTAL_DRV_AFE_1_0_8814B 3
+#define BIT_MASK_XTAL_DRV_AFE_1_0_8814B 0x3
+#define BIT_XTAL_DRV_AFE_1_0_8814B(x)                                          \
+	(((x) & BIT_MASK_XTAL_DRV_AFE_1_0_8814B)                               \
+	 << BIT_SHIFT_XTAL_DRV_AFE_1_0_8814B)
+#define BITS_XTAL_DRV_AFE_1_0_8814B                                            \
+	(BIT_MASK_XTAL_DRV_AFE_1_0_8814B << BIT_SHIFT_XTAL_DRV_AFE_1_0_8814B)
+#define BIT_CLEAR_XTAL_DRV_AFE_1_0_8814B(x)                                    \
+	((x) & (~BITS_XTAL_DRV_AFE_1_0_8814B))
+#define BIT_GET_XTAL_DRV_AFE_1_0_8814B(x)                                      \
+	(((x) >> BIT_SHIFT_XTAL_DRV_AFE_1_0_8814B) &                           \
+	 BIT_MASK_XTAL_DRV_AFE_1_0_8814B)
+#define BIT_SET_XTAL_DRV_AFE_1_0_8814B(x, v)                                   \
+	(BIT_CLEAR_XTAL_DRV_AFE_1_0_8814B(x) | BIT_XTAL_DRV_AFE_1_0_8814B(v))
+
+#define BIT_XTAL_GATED_AFEN_8814B BIT(2)
+#define BIT_XTAL_GATED_AFEP_8814B BIT(1)
+#define BIT_XTAL_DRV_RF1_1_8814B BIT(0)
+
+/* 2 REG_ANAPAR_XTAL_2_8814B */
+#define BIT_XTAL_DRV_RF2_LATCH_8814B BIT(6)
+
+#define BIT_SHIFT_XTAL_DRV_RF2_1_0_8814B 4
+#define BIT_MASK_XTAL_DRV_RF2_1_0_8814B 0x3
+#define BIT_XTAL_DRV_RF2_1_0_8814B(x)                                          \
+	(((x) & BIT_MASK_XTAL_DRV_RF2_1_0_8814B)                               \
+	 << BIT_SHIFT_XTAL_DRV_RF2_1_0_8814B)
+#define BITS_XTAL_DRV_RF2_1_0_8814B                                            \
+	(BIT_MASK_XTAL_DRV_RF2_1_0_8814B << BIT_SHIFT_XTAL_DRV_RF2_1_0_8814B)
+#define BIT_CLEAR_XTAL_DRV_RF2_1_0_8814B(x)                                    \
+	((x) & (~BITS_XTAL_DRV_RF2_1_0_8814B))
+#define BIT_GET_XTAL_DRV_RF2_1_0_8814B(x)                                      \
+	(((x) >> BIT_SHIFT_XTAL_DRV_RF2_1_0_8814B) &                           \
+	 BIT_MASK_XTAL_DRV_RF2_1_0_8814B)
+#define BIT_SET_XTAL_DRV_RF2_1_0_8814B(x, v)                                   \
+	(BIT_CLEAR_XTAL_DRV_RF2_1_0_8814B(x) | BIT_XTAL_DRV_RF2_1_0_8814B(v))
+
+#define BIT_XTAL_GATED_RF2N_8814B BIT(3)
+#define BIT_XTAL_GATED_RF2P_8814B BIT(2)
+#define BIT_XTAL_LDO_DI_8814B BIT(1)
+#define BIT_XTAL_SEL_PWR_8814B BIT(0)
+
+/* 2 REG_ANAPAR_XTAL_AAC_8814B */
+#define BIT_EN_XTAL_AAC_TRIG_8814B BIT(28)
+#define BIT_EN_XTAL_AAC_8814B BIT(27)
+#define BIT_EN_XTAL_AAC_DIGI_8814B BIT(26)
+
+#define BIT_SHIFT_GM_MANUAL_4_0_8814B 21
+#define BIT_MASK_GM_MANUAL_4_0_8814B 0x1f
+#define BIT_GM_MANUAL_4_0_8814B(x)                                             \
+	(((x) & BIT_MASK_GM_MANUAL_4_0_8814B) << BIT_SHIFT_GM_MANUAL_4_0_8814B)
+#define BITS_GM_MANUAL_4_0_8814B                                               \
+	(BIT_MASK_GM_MANUAL_4_0_8814B << BIT_SHIFT_GM_MANUAL_4_0_8814B)
+#define BIT_CLEAR_GM_MANUAL_4_0_8814B(x) ((x) & (~BITS_GM_MANUAL_4_0_8814B))
+#define BIT_GET_GM_MANUAL_4_0_8814B(x)                                         \
+	(((x) >> BIT_SHIFT_GM_MANUAL_4_0_8814B) & BIT_MASK_GM_MANUAL_4_0_8814B)
+#define BIT_SET_GM_MANUAL_4_0_8814B(x, v)                                      \
+	(BIT_CLEAR_GM_MANUAL_4_0_8814B(x) | BIT_GM_MANUAL_4_0_8814B(v))
+
+#define BIT_SHIFT_GM_STUP_4_0_8814B 16
+#define BIT_MASK_GM_STUP_4_0_8814B 0x1f
+#define BIT_GM_STUP_4_0_8814B(x)                                               \
+	(((x) & BIT_MASK_GM_STUP_4_0_8814B) << BIT_SHIFT_GM_STUP_4_0_8814B)
+#define BITS_GM_STUP_4_0_8814B                                                 \
+	(BIT_MASK_GM_STUP_4_0_8814B << BIT_SHIFT_GM_STUP_4_0_8814B)
+#define BIT_CLEAR_GM_STUP_4_0_8814B(x) ((x) & (~BITS_GM_STUP_4_0_8814B))
+#define BIT_GET_GM_STUP_4_0_8814B(x)                                           \
+	(((x) >> BIT_SHIFT_GM_STUP_4_0_8814B) & BIT_MASK_GM_STUP_4_0_8814B)
+#define BIT_SET_GM_STUP_4_0_8814B(x, v)                                        \
+	(BIT_CLEAR_GM_STUP_4_0_8814B(x) | BIT_GM_STUP_4_0_8814B(v))
+
+#define BIT_SHIFT_XTAL_CK_SET_2_0_8814B 13
+#define BIT_MASK_XTAL_CK_SET_2_0_8814B 0x7
+#define BIT_XTAL_CK_SET_2_0_8814B(x)                                           \
+	(((x) & BIT_MASK_XTAL_CK_SET_2_0_8814B)                                \
+	 << BIT_SHIFT_XTAL_CK_SET_2_0_8814B)
+#define BITS_XTAL_CK_SET_2_0_8814B                                             \
+	(BIT_MASK_XTAL_CK_SET_2_0_8814B << BIT_SHIFT_XTAL_CK_SET_2_0_8814B)
+#define BIT_CLEAR_XTAL_CK_SET_2_0_8814B(x) ((x) & (~BITS_XTAL_CK_SET_2_0_8814B))
+#define BIT_GET_XTAL_CK_SET_2_0_8814B(x)                                       \
+	(((x) >> BIT_SHIFT_XTAL_CK_SET_2_0_8814B) &                            \
+	 BIT_MASK_XTAL_CK_SET_2_0_8814B)
+#define BIT_SET_XTAL_CK_SET_2_0_8814B(x, v)                                    \
+	(BIT_CLEAR_XTAL_CK_SET_2_0_8814B(x) | BIT_XTAL_CK_SET_2_0_8814B(v))
+
+#define BIT_SHIFT_GM_INIT_4_0_8814B 8
+#define BIT_MASK_GM_INIT_4_0_8814B 0x1f
+#define BIT_GM_INIT_4_0_8814B(x)                                               \
+	(((x) & BIT_MASK_GM_INIT_4_0_8814B) << BIT_SHIFT_GM_INIT_4_0_8814B)
+#define BITS_GM_INIT_4_0_8814B                                                 \
+	(BIT_MASK_GM_INIT_4_0_8814B << BIT_SHIFT_GM_INIT_4_0_8814B)
+#define BIT_CLEAR_GM_INIT_4_0_8814B(x) ((x) & (~BITS_GM_INIT_4_0_8814B))
+#define BIT_GET_GM_INIT_4_0_8814B(x)                                           \
+	(((x) >> BIT_SHIFT_GM_INIT_4_0_8814B) & BIT_MASK_GM_INIT_4_0_8814B)
+#define BIT_SET_GM_INIT_4_0_8814B(x, v)                                        \
+	(BIT_CLEAR_GM_INIT_4_0_8814B(x) | BIT_GM_INIT_4_0_8814B(v))
+
+#define BIT_GM_STEP_8814B BIT(7)
+
+#define BIT_SHIFT_XAAC_GM_OFFSET_4_0_8814B 2
+#define BIT_MASK_XAAC_GM_OFFSET_4_0_8814B 0x1f
+#define BIT_XAAC_GM_OFFSET_4_0_8814B(x)                                        \
+	(((x) & BIT_MASK_XAAC_GM_OFFSET_4_0_8814B)                             \
+	 << BIT_SHIFT_XAAC_GM_OFFSET_4_0_8814B)
+#define BITS_XAAC_GM_OFFSET_4_0_8814B                                          \
+	(BIT_MASK_XAAC_GM_OFFSET_4_0_8814B                                     \
+	 << BIT_SHIFT_XAAC_GM_OFFSET_4_0_8814B)
+#define BIT_CLEAR_XAAC_GM_OFFSET_4_0_8814B(x)                                  \
+	((x) & (~BITS_XAAC_GM_OFFSET_4_0_8814B))
+#define BIT_GET_XAAC_GM_OFFSET_4_0_8814B(x)                                    \
+	(((x) >> BIT_SHIFT_XAAC_GM_OFFSET_4_0_8814B) &                         \
+	 BIT_MASK_XAAC_GM_OFFSET_4_0_8814B)
+#define BIT_SET_XAAC_GM_OFFSET_4_0_8814B(x, v)                                 \
+	(BIT_CLEAR_XAAC_GM_OFFSET_4_0_8814B(x) |                               \
+	 BIT_XAAC_GM_OFFSET_4_0_8814B(v))
+
+#define BIT_OFFSET_PLUS_8814B BIT(1)
+#define BIT_RESET_N_8814B BIT(0)
+
+/* 2 REG_ANAPAR_XTAL_R_ONLY_8814B */
+#define BIT_XTAL_PKDET_OUT_8814B BIT(6)
+
+#define BIT_SHIFT_XTAL_GM_AAC_4_0_8814B 1
+#define BIT_MASK_XTAL_GM_AAC_4_0_8814B 0x1f
+#define BIT_XTAL_GM_AAC_4_0_8814B(x)                                           \
+	(((x) & BIT_MASK_XTAL_GM_AAC_4_0_8814B)                                \
+	 << BIT_SHIFT_XTAL_GM_AAC_4_0_8814B)
+#define BITS_XTAL_GM_AAC_4_0_8814B                                             \
+	(BIT_MASK_XTAL_GM_AAC_4_0_8814B << BIT_SHIFT_XTAL_GM_AAC_4_0_8814B)
+#define BIT_CLEAR_XTAL_GM_AAC_4_0_8814B(x) ((x) & (~BITS_XTAL_GM_AAC_4_0_8814B))
+#define BIT_GET_XTAL_GM_AAC_4_0_8814B(x)                                       \
+	(((x) >> BIT_SHIFT_XTAL_GM_AAC_4_0_8814B) &                            \
+	 BIT_MASK_XTAL_GM_AAC_4_0_8814B)
+#define BIT_SET_XTAL_GM_AAC_4_0_8814B(x, v)                                    \
+	(BIT_CLEAR_XTAL_GM_AAC_4_0_8814B(x) | BIT_XTAL_GM_AAC_4_0_8814B(v))
+
+#define BIT_XAAC_READY_8814B BIT(0)
+
+/* 2 REG_CPHY_LDO_8814B */
+
+#define BIT_SHIFT_CPHY_LDO_PD_8814B 12
+#define BIT_MASK_CPHY_LDO_PD_8814B 0x3
+#define BIT_CPHY_LDO_PD_8814B(x)                                               \
+	(((x) & BIT_MASK_CPHY_LDO_PD_8814B) << BIT_SHIFT_CPHY_LDO_PD_8814B)
+#define BITS_CPHY_LDO_PD_8814B                                                 \
+	(BIT_MASK_CPHY_LDO_PD_8814B << BIT_SHIFT_CPHY_LDO_PD_8814B)
+#define BIT_CLEAR_CPHY_LDO_PD_8814B(x) ((x) & (~BITS_CPHY_LDO_PD_8814B))
+#define BIT_GET_CPHY_LDO_PD_8814B(x)                                           \
+	(((x) >> BIT_SHIFT_CPHY_LDO_PD_8814B) & BIT_MASK_CPHY_LDO_PD_8814B)
+#define BIT_SET_CPHY_LDO_PD_8814B(x, v)                                        \
+	(BIT_CLEAR_CPHY_LDO_PD_8814B(x) | BIT_CPHY_LDO_PD_8814B(v))
+
+#define BIT_SHIFT_CPHY_LDO_SR_8814B 10
+#define BIT_MASK_CPHY_LDO_SR_8814B 0x3
+#define BIT_CPHY_LDO_SR_8814B(x)                                               \
+	(((x) & BIT_MASK_CPHY_LDO_SR_8814B) << BIT_SHIFT_CPHY_LDO_SR_8814B)
+#define BITS_CPHY_LDO_SR_8814B                                                 \
+	(BIT_MASK_CPHY_LDO_SR_8814B << BIT_SHIFT_CPHY_LDO_SR_8814B)
+#define BIT_CLEAR_CPHY_LDO_SR_8814B(x) ((x) & (~BITS_CPHY_LDO_SR_8814B))
+#define BIT_GET_CPHY_LDO_SR_8814B(x)                                           \
+	(((x) >> BIT_SHIFT_CPHY_LDO_SR_8814B) & BIT_MASK_CPHY_LDO_SR_8814B)
+#define BIT_SET_CPHY_LDO_SR_8814B(x, v)                                        \
+	(BIT_CLEAR_CPHY_LDO_SR_8814B(x) | BIT_CPHY_LDO_SR_8814B(v))
+
+#define BIT_SHIFT_CPHY_LDO_TUNEREF_8814B 8
+#define BIT_MASK_CPHY_LDO_TUNEREF_8814B 0x3
+#define BIT_CPHY_LDO_TUNEREF_8814B(x)                                          \
+	(((x) & BIT_MASK_CPHY_LDO_TUNEREF_8814B)                               \
+	 << BIT_SHIFT_CPHY_LDO_TUNEREF_8814B)
+#define BITS_CPHY_LDO_TUNEREF_8814B                                            \
+	(BIT_MASK_CPHY_LDO_TUNEREF_8814B << BIT_SHIFT_CPHY_LDO_TUNEREF_8814B)
+#define BIT_CLEAR_CPHY_LDO_TUNEREF_8814B(x)                                    \
+	((x) & (~BITS_CPHY_LDO_TUNEREF_8814B))
+#define BIT_GET_CPHY_LDO_TUNEREF_8814B(x)                                      \
+	(((x) >> BIT_SHIFT_CPHY_LDO_TUNEREF_8814B) &                           \
+	 BIT_MASK_CPHY_LDO_TUNEREF_8814B)
+#define BIT_SET_CPHY_LDO_TUNEREF_8814B(x, v)                                   \
+	(BIT_CLEAR_CPHY_LDO_TUNEREF_8814B(x) | BIT_CPHY_LDO_TUNEREF_8814B(v))
+
+#define BIT_SHIFT_CPHY_LDO_TUNE_VO_8814B 5
+#define BIT_MASK_CPHY_LDO_TUNE_VO_8814B 0x7
+#define BIT_CPHY_LDO_TUNE_VO_8814B(x)                                          \
+	(((x) & BIT_MASK_CPHY_LDO_TUNE_VO_8814B)                               \
+	 << BIT_SHIFT_CPHY_LDO_TUNE_VO_8814B)
+#define BITS_CPHY_LDO_TUNE_VO_8814B                                            \
+	(BIT_MASK_CPHY_LDO_TUNE_VO_8814B << BIT_SHIFT_CPHY_LDO_TUNE_VO_8814B)
+#define BIT_CLEAR_CPHY_LDO_TUNE_VO_8814B(x)                                    \
+	((x) & (~BITS_CPHY_LDO_TUNE_VO_8814B))
+#define BIT_GET_CPHY_LDO_TUNE_VO_8814B(x)                                      \
+	(((x) >> BIT_SHIFT_CPHY_LDO_TUNE_VO_8814B) &                           \
+	 BIT_MASK_CPHY_LDO_TUNE_VO_8814B)
+#define BIT_SET_CPHY_LDO_TUNE_VO_8814B(x, v)                                   \
+	(BIT_CLEAR_CPHY_LDO_TUNE_VO_8814B(x) | BIT_CPHY_LDO_TUNE_VO_8814B(v))
+
+#define BIT_SHIFT_CPHY_LDO_OCP_VTH_8814B 2
+#define BIT_MASK_CPHY_LDO_OCP_VTH_8814B 0x7
+#define BIT_CPHY_LDO_OCP_VTH_8814B(x)                                          \
+	(((x) & BIT_MASK_CPHY_LDO_OCP_VTH_8814B)                               \
+	 << BIT_SHIFT_CPHY_LDO_OCP_VTH_8814B)
+#define BITS_CPHY_LDO_OCP_VTH_8814B                                            \
+	(BIT_MASK_CPHY_LDO_OCP_VTH_8814B << BIT_SHIFT_CPHY_LDO_OCP_VTH_8814B)
+#define BIT_CLEAR_CPHY_LDO_OCP_VTH_8814B(x)                                    \
+	((x) & (~BITS_CPHY_LDO_OCP_VTH_8814B))
+#define BIT_GET_CPHY_LDO_OCP_VTH_8814B(x)                                      \
+	(((x) >> BIT_SHIFT_CPHY_LDO_OCP_VTH_8814B) &                           \
+	 BIT_MASK_CPHY_LDO_OCP_VTH_8814B)
+#define BIT_SET_CPHY_LDO_OCP_VTH_8814B(x, v)                                   \
+	(BIT_CLEAR_CPHY_LDO_OCP_VTH_8814B(x) | BIT_CPHY_LDO_OCP_VTH_8814B(v))
+
+#define BIT_SHIFT_VREF_LDO_OK_8814B 0
+#define BIT_MASK_VREF_LDO_OK_8814B 0x3
+#define BIT_VREF_LDO_OK_8814B(x)                                               \
+	(((x) & BIT_MASK_VREF_LDO_OK_8814B) << BIT_SHIFT_VREF_LDO_OK_8814B)
+#define BITS_VREF_LDO_OK_8814B                                                 \
+	(BIT_MASK_VREF_LDO_OK_8814B << BIT_SHIFT_VREF_LDO_OK_8814B)
+#define BIT_CLEAR_VREF_LDO_OK_8814B(x) ((x) & (~BITS_VREF_LDO_OK_8814B))
+#define BIT_GET_VREF_LDO_OK_8814B(x)                                           \
+	(((x) >> BIT_SHIFT_VREF_LDO_OK_8814B) & BIT_MASK_VREF_LDO_OK_8814B)
+#define BIT_SET_VREF_LDO_OK_8814B(x, v)                                        \
+	(BIT_CLEAR_VREF_LDO_OK_8814B(x) | BIT_VREF_LDO_OK_8814B(v))
+
+/* 2 REG_CPHY_BG_8814B */
+
+#define BIT_SHIFT_BG_8814B 0
+#define BIT_MASK_BG_8814B 0x7
+#define BIT_BG_8814B(x) (((x) & BIT_MASK_BG_8814B) << BIT_SHIFT_BG_8814B)
+#define BITS_BG_8814B (BIT_MASK_BG_8814B << BIT_SHIFT_BG_8814B)
+#define BIT_CLEAR_BG_8814B(x) ((x) & (~BITS_BG_8814B))
+#define BIT_GET_BG_8814B(x) (((x) >> BIT_SHIFT_BG_8814B) & BIT_MASK_BG_8814B)
+#define BIT_SET_BG_8814B(x, v) (BIT_CLEAR_BG_8814B(x) | BIT_BG_8814B(v))
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_HIMR_4_8814B */
+#define BIT_TXBCN_OK_PORT4_8814B BIT(31)
+#define BIT_TXBCN_OK_PORT3_8814B BIT(30)
+#define BIT_TXBCN_OK_PORT2_8814B BIT(29)
+#define BIT_TXBCN_OK_PORT1_8814B BIT(28)
+#define BIT_TXBCN15OK_8814B BIT(23)
+#define BIT_TXBCN14OK_8814B BIT(22)
+#define BIT_TXBCN13OK_8814B BIT(21)
+#define BIT_TXBCN12OK_8814B BIT(20)
+#define BIT_TXBCN11OK_8814B BIT(19)
+#define BIT_TXBCN10OK_8814B BIT(18)
+#define BIT_TXBCN9OK_8814B BIT(17)
+#define BIT_TXBCN8OK_8814B BIT(16)
+#define BIT_BCNDERR_PORT4_8814B BIT(15)
+#define BIT_BCNDERR_PORT3_8814B BIT(14)
+#define BIT_BCNDERR_PORT2_8814B BIT(13)
+#define BIT_BCNDERR_PORT1_8814B BIT(12)
+#define BIT_TXBCN15ERR_8814B BIT(7)
+#define BIT_TXBCN14ERR_8814B BIT(6)
+#define BIT_TXBCN13ERR_8814B BIT(5)
+#define BIT_TXBCN12ERR_8814B BIT(4)
+#define BIT_TXBCN11ERR_8814B BIT(3)
+#define BIT_TXBCN10ERR_8814B BIT(2)
+#define BIT_TXBCN9ERR_8814B BIT(1)
+#define BIT_TXBCN8ERR_8814B BIT(0)
+
+/* 2 REG_HISR_4_8814B */
+#define BIT_TXBCN_OK_PORT4_8814B BIT(31)
+#define BIT_TXBCN_OK_PORT3_8814B BIT(30)
+#define BIT_TXBCN_OK_PORT2_8814B BIT(29)
+#define BIT_TXBCN_OK_PORT1_8814B BIT(28)
+#define BIT_TXBCN15OK_8814B BIT(23)
+#define BIT_TXBCN14OK_8814B BIT(22)
+#define BIT_TXBCN13OK_8814B BIT(21)
+#define BIT_TXBCN12OK_8814B BIT(20)
+#define BIT_TXBCN11OK_8814B BIT(19)
+#define BIT_TXBCN10OK_8814B BIT(18)
+#define BIT_TXBCN9OK_8814B BIT(17)
+#define BIT_TXBCN8OK_8814B BIT(16)
+#define BIT_BCNDERR_PORT4_8814B BIT(15)
+#define BIT_BCNDERR_PORT3_8814B BIT(14)
+#define BIT_BCNDERR_PORT2_8814B BIT(13)
+#define BIT_BCNDERR_PORT1_8814B BIT(12)
+#define BIT_TXBCN15ERR_8814B BIT(7)
+#define BIT_TXBCN14ERR_8814B BIT(6)
+#define BIT_TXBCN13ERR_8814B BIT(5)
+#define BIT_TXBCN12ERR_8814B BIT(4)
+#define BIT_TXBCN11ERR_8814B BIT(3)
+#define BIT_TXBCN10ERR_8814B BIT(2)
+#define BIT_TXBCN9ERR_8814B BIT(1)
+#define BIT_TXBCN8ERR_8814B BIT(0)
+
+/* 2 REG_HIMR_5_8814B */
+#define BIT_BCNDMAINT15_8814B BIT(23)
+#define BIT_BCNDMAINT14_8814B BIT(22)
+#define BIT_BCNDMAINT13_8814B BIT(21)
+#define BIT_BCNDMAINT12_8814B BIT(20)
+#define BIT_BCNDMAINT11_8814B BIT(19)
+#define BIT_BCNDMAINT10_8814B BIT(18)
+#define BIT_BCNDMAINT9_8814B BIT(17)
+#define BIT_BCNDMAINT8_8814B BIT(16)
+#define BIT_BCNDERR_PORT4_8814B BIT(15)
+#define BIT_BCNDERR_PORT3_8814B BIT(14)
+#define BIT_BCNDERR_PORT2_8814B BIT(13)
+#define BIT_BCNDERR_PORT1_8814B BIT(12)
+#define BIT_BCNDERR15_8814B BIT(7)
+#define BIT_BCNDERR14_8814B BIT(6)
+#define BIT_BCNDERR13_8814B BIT(5)
+#define BIT_BCNDERR12_8814B BIT(4)
+#define BIT_BCNDERR11_8814B BIT(3)
+#define BIT_BCNDERR10_8814B BIT(2)
+#define BIT_BCNDERR9_8814B BIT(1)
+#define BIT_BCNDERR8_8814B BIT(0)
+
+/* 2 REG_HISR_5_8814B */
+#define BIT_BCNDMAINT15_8814B BIT(23)
+#define BIT_BCNDMAINT14_8814B BIT(22)
+#define BIT_BCNDMAINT13_8814B BIT(21)
+#define BIT_BCNDMAINT12_8814B BIT(20)
+#define BIT_BCNDMAINT11_8814B BIT(19)
+#define BIT_BCNDMAINT10_8814B BIT(18)
+#define BIT_BCNDMAINT9_8814B BIT(17)
+#define BIT_BCNDMAINT8_8814B BIT(16)
+#define BIT_BCNDERR_PORT4_8814B BIT(15)
+#define BIT_BCNDERR_PORT3_8814B BIT(14)
+#define BIT_BCNDERR_PORT2_8814B BIT(13)
+#define BIT_BCNDERR_PORT1_8814B BIT(12)
+#define BIT_BCNDERR15_8814B BIT(7)
+#define BIT_BCNDERR14_8814B BIT(6)
+#define BIT_BCNDERR13_8814B BIT(5)
+#define BIT_BCNDERR12_8814B BIT(4)
+#define BIT_BCNDERR11_8814B BIT(3)
+#define BIT_BCNDERR10_8814B BIT(2)
+#define BIT_BCNDERR9_8814B BIT(1)
+#define BIT_BCNDERR8_8814B BIT(0)
+
+/* 2 REG_SYS_CFG5_8814B */
+#define BIT_LPS_STATUS_8814B BIT(3)
+#define BIT_HCI_TXDMA_BUSY_8814B BIT(2)
+#define BIT_HCI_TXDMA_ALLOW_8814B BIT(1)
+#define BIT_FW_CTRL_HCI_TXDMA_EN_8814B BIT(0)
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_HIMR_6_8814B */
+#define BIT_ATIMEND_PORT4_8814B BIT(31)
+#define BIT_ATIMEND_PORT3_8814B BIT(30)
+#define BIT_ATIMEND_PORT2_8814B BIT(29)
+#define BIT_ATIMEND_PORT1_8814B BIT(28)
+#define BIT_ATIMEND15_8814B BIT(23)
+#define BIT_ATIMEND14_8814B BIT(22)
+#define BIT_ATIMEND13_8814B BIT(21)
+#define BIT_ATIMEND12_8814B BIT(20)
+#define BIT_ATIMEND11_8814B BIT(19)
+#define BIT_ATIMEND10_8814B BIT(18)
+#define BIT_ATIMEND9_8814B BIT(17)
+#define BIT_ATIMEND8_8814B BIT(16)
+#define BIT_PS_TIMER_EARLY_INT_5_8814B BIT(5)
+#define BIT_PS_TIMER_EARLY_INT_4_8814B BIT(4)
+#define BIT_PS_TIMER_EARLY_INT_3_8814B BIT(3)
+#define BIT_PS_TIMER_EARLY_INT_2_8814B BIT(2)
+#define BIT_PS_TIMER_EARLY_INT_1_8814B BIT(1)
+#define BIT_PS_TIMER_EARLY_INT_0_8814B BIT(0)
+
+/* 2 REG_HISR_6_8814B */
+#define BIT_ATIMEND_PORT4_8814B BIT(31)
+#define BIT_ATIMEND_PORT3_8814B BIT(30)
+#define BIT_ATIMEND_PORT2_8814B BIT(29)
+#define BIT_ATIMEND_PORT1_8814B BIT(28)
+#define BIT_ATIMEND15_8814B BIT(23)
+#define BIT_ATIMEND14_8814B BIT(22)
+#define BIT_ATIMEND13_8814B BIT(21)
+#define BIT_ATIMEND12_8814B BIT(20)
+#define BIT_ATIMEND11_8814B BIT(19)
+#define BIT_ATIMEND10_8814B BIT(18)
+#define BIT_ATIMEND9_8814B BIT(17)
+#define BIT_ATIMEND8_8814B BIT(16)
+#define BIT_PS_TIMER_EARLY_INT_5_8814B BIT(5)
+#define BIT_PS_TIMER_EARLY_INT_4_8814B BIT(4)
+#define BIT_PS_TIMER_EARLY_INT_3_8814B BIT(3)
+#define BIT_PS_TIMER_EARLY_INT_2_8814B BIT(2)
+#define BIT_PS_TIMER_EARLY_INT_1_8814B BIT(1)
+#define BIT_PS_TIMER_EARLY_INT_0_8814B BIT(0)
+
+/* 2 REG_CPU_DMEM_CON_8814B */
+#define BIT_WDT_AUTO_MODE_8814B BIT(22)
+#define BIT_WDT_PLATFORM_EN_8814B BIT(21)
+#define BIT_WDT_CPU_EN_8814B BIT(20)
+#define BIT_WDT_OPT_IOWRAPPER_8814B BIT(19)
+#define BIT_ANA_PORT_IDLE_8814B BIT(18)
+#define BIT_MAC_PORT_IDLE_8814B BIT(17)
+#define BIT_WL_PLATFORM_RST_8814B BIT(16)
+#define BIT_WL_SECURITY_CLK_8814B BIT(15)
+#define BIT_DDMA_EN_8814B BIT(8)
+
+#define BIT_SHIFT_CPU_DMEM_CON_8814B 0
+#define BIT_MASK_CPU_DMEM_CON_8814B 0xff
+#define BIT_CPU_DMEM_CON_8814B(x)                                              \
+	(((x) & BIT_MASK_CPU_DMEM_CON_8814B) << BIT_SHIFT_CPU_DMEM_CON_8814B)
+#define BITS_CPU_DMEM_CON_8814B                                                \
+	(BIT_MASK_CPU_DMEM_CON_8814B << BIT_SHIFT_CPU_DMEM_CON_8814B)
+#define BIT_CLEAR_CPU_DMEM_CON_8814B(x) ((x) & (~BITS_CPU_DMEM_CON_8814B))
+#define BIT_GET_CPU_DMEM_CON_8814B(x)                                          \
+	(((x) >> BIT_SHIFT_CPU_DMEM_CON_8814B) & BIT_MASK_CPU_DMEM_CON_8814B)
+#define BIT_SET_CPU_DMEM_CON_8814B(x, v)                                       \
+	(BIT_CLEAR_CPU_DMEM_CON_8814B(x) | BIT_CPU_DMEM_CON_8814B(v))
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_BOOT_REASON_8814B */
+
+#define BIT_SHIFT_BOOT_REASON_V1_8814B 0
+#define BIT_MASK_BOOT_REASON_V1_8814B 0x7
+#define BIT_BOOT_REASON_V1_8814B(x)                                            \
+	(((x) & BIT_MASK_BOOT_REASON_V1_8814B)                                 \
+	 << BIT_SHIFT_BOOT_REASON_V1_8814B)
+#define BITS_BOOT_REASON_V1_8814B                                              \
+	(BIT_MASK_BOOT_REASON_V1_8814B << BIT_SHIFT_BOOT_REASON_V1_8814B)
+#define BIT_CLEAR_BOOT_REASON_V1_8814B(x) ((x) & (~BITS_BOOT_REASON_V1_8814B))
+#define BIT_GET_BOOT_REASON_V1_8814B(x)                                        \
+	(((x) >> BIT_SHIFT_BOOT_REASON_V1_8814B) &                             \
+	 BIT_MASK_BOOT_REASON_V1_8814B)
+#define BIT_SET_BOOT_REASON_V1_8814B(x, v)                                     \
+	(BIT_CLEAR_BOOT_REASON_V1_8814B(x) | BIT_BOOT_REASON_V1_8814B(v))
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_DATA_CPU_CTL0_8814B */
+#define BIT_DATA_FW_READY_8814B BIT(31)
+#define BIT_WDT_SYS_RST_8814B BIT(13)
+#define BIT_WDT_ENABLE_8814B BIT(12)
+
+#define BIT_SHIFT_BOOT_SEL_8814B 6
+#define BIT_MASK_BOOT_SEL_8814B 0x3
+#define BIT_BOOT_SEL_8814B(x)                                                  \
+	(((x) & BIT_MASK_BOOT_SEL_8814B) << BIT_SHIFT_BOOT_SEL_8814B)
+#define BITS_BOOT_SEL_8814B                                                    \
+	(BIT_MASK_BOOT_SEL_8814B << BIT_SHIFT_BOOT_SEL_8814B)
+#define BIT_CLEAR_BOOT_SEL_8814B(x) ((x) & (~BITS_BOOT_SEL_8814B))
+#define BIT_GET_BOOT_SEL_8814B(x)                                              \
+	(((x) >> BIT_SHIFT_BOOT_SEL_8814B) & BIT_MASK_BOOT_SEL_8814B)
+#define BIT_SET_BOOT_SEL_8814B(x, v)                                           \
+	(BIT_CLEAR_BOOT_SEL_8814B(x) | BIT_BOOT_SEL_8814B(v))
+
+#define BIT_CLK_SEL_8814B BIT(4)
+#define BIT_DATA_PLATFORM_RST_8814B BIT(1)
+#define BIT_DATA_CPU_RST_8814B BIT(0)
+
+/* 2 REG_DATA_CPU_CTL1_8814B */
+#define BIT_HOST_INTERFACE_IO_PATH_8814B BIT(7)
+#define BIT_EN_TXDMA_OFLD_8814B BIT(6)
+#define BIT_EN_RXDMA_OFLD_8814B BIT(5)
+#define BIT_EN_HCI_DMA_TX_8814B BIT(4)
+#define BIT_EN_HCI_DMA_RX_8814B BIT(3)
+#define BIT_EN_AXI_DMA_TX_8814B BIT(2)
+#define BIT_EN_AXI_DMA_RX_8814B BIT(1)
+#define BIT_EN_PKT_ENG_8814B BIT(0)
+
+/* 2 REG_TXDMA_STOP_HIMR_8814B */
+
+#define BIT_SHIFT_NTH_TXDMA_STOP_INT_MSK_8814B 0
+#define BIT_MASK_NTH_TXDMA_STOP_INT_MSK_8814B 0x1ffff
+#define BIT_NTH_TXDMA_STOP_INT_MSK_8814B(x)                                    \
+	(((x) & BIT_MASK_NTH_TXDMA_STOP_INT_MSK_8814B)                         \
+	 << BIT_SHIFT_NTH_TXDMA_STOP_INT_MSK_8814B)
+#define BITS_NTH_TXDMA_STOP_INT_MSK_8814B                                      \
+	(BIT_MASK_NTH_TXDMA_STOP_INT_MSK_8814B                                 \
+	 << BIT_SHIFT_NTH_TXDMA_STOP_INT_MSK_8814B)
+#define BIT_CLEAR_NTH_TXDMA_STOP_INT_MSK_8814B(x)                              \
+	((x) & (~BITS_NTH_TXDMA_STOP_INT_MSK_8814B))
+#define BIT_GET_NTH_TXDMA_STOP_INT_MSK_8814B(x)                                \
+	(((x) >> BIT_SHIFT_NTH_TXDMA_STOP_INT_MSK_8814B) &                     \
+	 BIT_MASK_NTH_TXDMA_STOP_INT_MSK_8814B)
+#define BIT_SET_NTH_TXDMA_STOP_INT_MSK_8814B(x, v)                             \
+	(BIT_CLEAR_NTH_TXDMA_STOP_INT_MSK_8814B(x) |                           \
+	 BIT_NTH_TXDMA_STOP_INT_MSK_8814B(v))
+
+/* 2 REG_TXDMA_STOP_HISR_8814B */
+
+#define BIT_SHIFT_NTH_TXDMA_STOP_INT_8814B 0
+#define BIT_MASK_NTH_TXDMA_STOP_INT_8814B 0x1ffff
+#define BIT_NTH_TXDMA_STOP_INT_8814B(x)                                        \
+	(((x) & BIT_MASK_NTH_TXDMA_STOP_INT_8814B)                             \
+	 << BIT_SHIFT_NTH_TXDMA_STOP_INT_8814B)
+#define BITS_NTH_TXDMA_STOP_INT_8814B                                          \
+	(BIT_MASK_NTH_TXDMA_STOP_INT_8814B                                     \
+	 << BIT_SHIFT_NTH_TXDMA_STOP_INT_8814B)
+#define BIT_CLEAR_NTH_TXDMA_STOP_INT_8814B(x)                                  \
+	((x) & (~BITS_NTH_TXDMA_STOP_INT_8814B))
+#define BIT_GET_NTH_TXDMA_STOP_INT_8814B(x)                                    \
+	(((x) >> BIT_SHIFT_NTH_TXDMA_STOP_INT_8814B) &                         \
+	 BIT_MASK_NTH_TXDMA_STOP_INT_8814B)
+#define BIT_SET_NTH_TXDMA_STOP_INT_8814B(x, v)                                 \
+	(BIT_CLEAR_NTH_TXDMA_STOP_INT_8814B(x) |                               \
+	 BIT_NTH_TXDMA_STOP_INT_8814B(v))
+
+/* 2 REG_TXDMA_START_HIMR_8814B */
+
+#define BIT_SHIFT_NTH_TXDMA_START_INT_MSK_8814B 0
+#define BIT_MASK_NTH_TXDMA_START_INT_MSK_8814B 0x1ffff
+#define BIT_NTH_TXDMA_START_INT_MSK_8814B(x)                                   \
+	(((x) & BIT_MASK_NTH_TXDMA_START_INT_MSK_8814B)                        \
+	 << BIT_SHIFT_NTH_TXDMA_START_INT_MSK_8814B)
+#define BITS_NTH_TXDMA_START_INT_MSK_8814B                                     \
+	(BIT_MASK_NTH_TXDMA_START_INT_MSK_8814B                                \
+	 << BIT_SHIFT_NTH_TXDMA_START_INT_MSK_8814B)
+#define BIT_CLEAR_NTH_TXDMA_START_INT_MSK_8814B(x)                             \
+	((x) & (~BITS_NTH_TXDMA_START_INT_MSK_8814B))
+#define BIT_GET_NTH_TXDMA_START_INT_MSK_8814B(x)                               \
+	(((x) >> BIT_SHIFT_NTH_TXDMA_START_INT_MSK_8814B) &                    \
+	 BIT_MASK_NTH_TXDMA_START_INT_MSK_8814B)
+#define BIT_SET_NTH_TXDMA_START_INT_MSK_8814B(x, v)                            \
+	(BIT_CLEAR_NTH_TXDMA_START_INT_MSK_8814B(x) |                          \
+	 BIT_NTH_TXDMA_START_INT_MSK_8814B(v))
+
+/* 2 REG_TXDMA_START_HISR_8814B */
+
+#define BIT_SHIFT_NTH_TXDMA_START_INT_8814B 0
+#define BIT_MASK_NTH_TXDMA_START_INT_8814B 0x1ffff
+#define BIT_NTH_TXDMA_START_INT_8814B(x)                                       \
+	(((x) & BIT_MASK_NTH_TXDMA_START_INT_8814B)                            \
+	 << BIT_SHIFT_NTH_TXDMA_START_INT_8814B)
+#define BITS_NTH_TXDMA_START_INT_8814B                                         \
+	(BIT_MASK_NTH_TXDMA_START_INT_8814B                                    \
+	 << BIT_SHIFT_NTH_TXDMA_START_INT_8814B)
+#define BIT_CLEAR_NTH_TXDMA_START_INT_8814B(x)                                 \
+	((x) & (~BITS_NTH_TXDMA_START_INT_8814B))
+#define BIT_GET_NTH_TXDMA_START_INT_8814B(x)                                   \
+	(((x) >> BIT_SHIFT_NTH_TXDMA_START_INT_8814B) &                        \
+	 BIT_MASK_NTH_TXDMA_START_INT_8814B)
+#define BIT_SET_NTH_TXDMA_START_INT_8814B(x, v)                                \
+	(BIT_CLEAR_NTH_TXDMA_START_INT_8814B(x) |                              \
+	 BIT_NTH_TXDMA_START_INT_8814B(v))
+
+/* 2 REG_NFCPAD_CTRL_8814B */
+#define BIT_PAD_SHUTDW_8814B BIT(18)
+#define BIT_SYSON_NFC_PAD_8814B BIT(17)
+#define BIT_NFC_INT_PAD_CTRL_8814B BIT(16)
+#define BIT_NFC_RFDIS_PAD_CTRL_8814B BIT(15)
+#define BIT_NFC_CLK_PAD_CTRL_8814B BIT(14)
+#define BIT_NFC_DATA_PAD_CTRL_8814B BIT(13)
+#define BIT_NFC_PAD_PULL_CTRL_8814B BIT(12)
+
+#define BIT_SHIFT_NFCPAD_IO_SEL_8814B 8
+#define BIT_MASK_NFCPAD_IO_SEL_8814B 0xf
+#define BIT_NFCPAD_IO_SEL_8814B(x)                                             \
+	(((x) & BIT_MASK_NFCPAD_IO_SEL_8814B) << BIT_SHIFT_NFCPAD_IO_SEL_8814B)
+#define BITS_NFCPAD_IO_SEL_8814B                                               \
+	(BIT_MASK_NFCPAD_IO_SEL_8814B << BIT_SHIFT_NFCPAD_IO_SEL_8814B)
+#define BIT_CLEAR_NFCPAD_IO_SEL_8814B(x) ((x) & (~BITS_NFCPAD_IO_SEL_8814B))
+#define BIT_GET_NFCPAD_IO_SEL_8814B(x)                                         \
+	(((x) >> BIT_SHIFT_NFCPAD_IO_SEL_8814B) & BIT_MASK_NFCPAD_IO_SEL_8814B)
+#define BIT_SET_NFCPAD_IO_SEL_8814B(x, v)                                      \
+	(BIT_CLEAR_NFCPAD_IO_SEL_8814B(x) | BIT_NFCPAD_IO_SEL_8814B(v))
+
+#define BIT_SHIFT_NFCPAD_OUT_8814B 4
+#define BIT_MASK_NFCPAD_OUT_8814B 0xf
+#define BIT_NFCPAD_OUT_8814B(x)                                                \
+	(((x) & BIT_MASK_NFCPAD_OUT_8814B) << BIT_SHIFT_NFCPAD_OUT_8814B)
+#define BITS_NFCPAD_OUT_8814B                                                  \
+	(BIT_MASK_NFCPAD_OUT_8814B << BIT_SHIFT_NFCPAD_OUT_8814B)
+#define BIT_CLEAR_NFCPAD_OUT_8814B(x) ((x) & (~BITS_NFCPAD_OUT_8814B))
+#define BIT_GET_NFCPAD_OUT_8814B(x)                                            \
+	(((x) >> BIT_SHIFT_NFCPAD_OUT_8814B) & BIT_MASK_NFCPAD_OUT_8814B)
+#define BIT_SET_NFCPAD_OUT_8814B(x, v)                                         \
+	(BIT_CLEAR_NFCPAD_OUT_8814B(x) | BIT_NFCPAD_OUT_8814B(v))
+
+#define BIT_SHIFT_NFCPAD_IN_8814B 0
+#define BIT_MASK_NFCPAD_IN_8814B 0xf
+#define BIT_NFCPAD_IN_8814B(x)                                                 \
+	(((x) & BIT_MASK_NFCPAD_IN_8814B) << BIT_SHIFT_NFCPAD_IN_8814B)
+#define BITS_NFCPAD_IN_8814B                                                   \
+	(BIT_MASK_NFCPAD_IN_8814B << BIT_SHIFT_NFCPAD_IN_8814B)
+#define BIT_CLEAR_NFCPAD_IN_8814B(x) ((x) & (~BITS_NFCPAD_IN_8814B))
+#define BIT_GET_NFCPAD_IN_8814B(x)                                             \
+	(((x) >> BIT_SHIFT_NFCPAD_IN_8814B) & BIT_MASK_NFCPAD_IN_8814B)
+#define BIT_SET_NFCPAD_IN_8814B(x, v)                                          \
+	(BIT_CLEAR_NFCPAD_IN_8814B(x) | BIT_NFCPAD_IN_8814B(v))
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_HIMR2_8814B */
+#define BIT_BCNDMAINT_P4_MSK_8814B BIT(31)
+#define BIT_BCNDMAINT_P3_MSK_8814B BIT(30)
+#define BIT_BCNDMAINT_P2_MSK_8814B BIT(29)
+#define BIT_BCNDMAINT_P1_MSK_8814B BIT(28)
+#define BIT_SCH_PHY_TXOP_SIFS_INT_MSK_8814B BIT(23)
+#define BIT_ATIMEND7_MSK_8814B BIT(22)
+#define BIT_ATIMEND6_MSK_8814B BIT(21)
+#define BIT_ATIMEND5_MSK_8814B BIT(20)
+#define BIT_ATIMEND4_MSK_8814B BIT(19)
+#define BIT_ATIMEND3_MSK_8814B BIT(18)
+#define BIT_ATIMEND2_MSK_8814B BIT(17)
+#define BIT_ATIMEND1_MSK_8814B BIT(16)
+#define BIT_TXBCN7OK_MSK_8814B BIT(14)
+#define BIT_TXBCN6OK_MSK_8814B BIT(13)
+#define BIT_TXBCN5OK_MSK_8814B BIT(12)
+#define BIT_TXBCN4OK_MSK_8814B BIT(11)
+#define BIT_TXBCN3OK_MSK_8814B BIT(10)
+#define BIT_TXBCN2OK_MSK_8814B BIT(9)
+#define BIT_TXBCN1OK_MSK_V1_8814B BIT(8)
+#define BIT_TXBCN7ERR_MSK_8814B BIT(6)
+#define BIT_TXBCN6ERR_MSK_8814B BIT(5)
+#define BIT_TXBCN5ERR_MSK_8814B BIT(4)
+#define BIT_TXBCN4ERR_MSK_8814B BIT(3)
+#define BIT_TXBCN3ERR_MSK_8814B BIT(2)
+#define BIT_TXBCN2ERR_MSK_8814B BIT(1)
+#define BIT_TXBCN1ERR_MSK_V1_8814B BIT(0)
+
+/* 2 REG_HISR2_8814B */
+#define BIT_BCNDMAINT_P4_8814B BIT(31)
+#define BIT_BCNDMAINT_P3_8814B BIT(30)
+#define BIT_BCNDMAINT_P2_8814B BIT(29)
+#define BIT_BCNDMAINT_P1_8814B BIT(28)
+#define BIT_SCH_PHY_TXOP_SIFS_INT_8814B BIT(23)
+#define BIT_ATIMEND7_8814B BIT(22)
+#define BIT_ATIMEND6_8814B BIT(21)
+#define BIT_ATIMEND5_8814B BIT(20)
+#define BIT_ATIMEND4_8814B BIT(19)
+#define BIT_ATIMEND3_8814B BIT(18)
+#define BIT_ATIMEND2_8814B BIT(17)
+#define BIT_ATIMEND1_8814B BIT(16)
+#define BIT_TXBCN7OK_8814B BIT(14)
+#define BIT_TXBCN6OK_8814B BIT(13)
+#define BIT_TXBCN5OK_8814B BIT(12)
+#define BIT_TXBCN4OK_8814B BIT(11)
+#define BIT_TXBCN3OK_8814B BIT(10)
+#define BIT_TXBCN2OK_8814B BIT(9)
+#define BIT_TXBCN1OK_8814B BIT(8)
+#define BIT_TXBCN7ERR_8814B BIT(6)
+#define BIT_TXBCN6ERR_8814B BIT(5)
+#define BIT_TXBCN5ERR_8814B BIT(4)
+#define BIT_TXBCN4ERR_8814B BIT(3)
+#define BIT_TXBCN3ERR_8814B BIT(2)
+#define BIT_TXBCN2ERR_8814B BIT(1)
+#define BIT_TXBCN1ERR_8814B BIT(0)
+
+/* 2 REG_HIMR3_8814B */
+#define BIT_GTINT12_MSK_8814B BIT(24)
+#define BIT_GTINT11_MSK_8814B BIT(23)
+#define BIT_GTINT10_MSK_8814B BIT(22)
+#define BIT_GTINT9_MSK_8814B BIT(21)
+#define BIT_RX_DESC_BUF_FULL_MSK_8814B BIT(20)
+#define BIT_CPHY_LDO_OCP_DET_INT_MSK_8814B BIT(19)
+#define BIT_WDT_PLATFORM_INT_MSK_8814B BIT(18)
+#define BIT_WDT_CPU_INT_MSK_8814B BIT(17)
+#define BIT_SETH2CDOK_MASK_8814B BIT(16)
+#define BIT_H2C_CMD_FULL_MASK_8814B BIT(15)
+#define BIT_PKT_TRANS_ERR_MASK_8814B BIT(14)
+#define BIT_TXSHORTCUT_TXDESUPDATEOK_MASK_8814B BIT(13)
+#define BIT_TXSHORTCUT_BKUPDATEOK_MASK_8814B BIT(12)
+#define BIT_TXSHORTCUT_BEUPDATEOK_MASK_8814B BIT(11)
+#define BIT_TXSHORTCUT_VIUPDATEOK_MAS_8814B BIT(10)
+#define BIT_TXSHORTCUT_VOUPDATEOK_MASK_8814B BIT(9)
+#define BIT_SEARCH_FAIL_MSK_8814B BIT(8)
+#define BIT_PWR_INT_127TO96_MASK_8814B BIT(7)
+#define BIT_PWR_INT_95TO64_MASK_8814B BIT(6)
+#define BIT_PWR_INT_63TO32_MASK_8814B BIT(5)
+#define BIT_PWR_INT_31TO0_MASK_8814B BIT(4)
+#define BIT_RX_DMA_STUCK_MSK_8814B BIT(3)
+#define BIT_TX_DMA_STUCK_MSK_8814B BIT(2)
+#define BIT_DDMA0_LP_INT_MSK_8814B BIT(1)
+#define BIT_DDMA0_HP_INT_MSK_8814B BIT(0)
+
+/* 2 REG_HISR3_8814B */
+#define BIT_GTINT12_8814B BIT(24)
+#define BIT_GTINT11_8814B BIT(23)
+#define BIT_GTINT10_8814B BIT(22)
+#define BIT_GTINT9_8814B BIT(21)
+#define BIT_RX_DESC_BUF_FULL_8814B BIT(20)
+#define BIT_CPHY_LDO_OCP_DET_INT_8814B BIT(19)
+#define BIT_WDT_PLATFORM_INT_8814B BIT(18)
+#define BIT_WDT_CPU_INT_8814B BIT(17)
+#define BIT_SETH2CDOK_8814B BIT(16)
+#define BIT_H2C_CMD_FULL_8814B BIT(15)
+#define BIT_PKT_TRANS_ERR_8814B BIT(14)
+#define BIT_TXSHORTCUT_TXDESUPDATEOK_8814B BIT(13)
+#define BIT_TXSHORTCUT_BKUPDATEOK_8814B BIT(12)
+#define BIT_TXSHORTCUT_BEUPDATEOK_8814B BIT(11)
+#define BIT_TXSHORTCUT_VIUPDATEOK_8814B BIT(10)
+#define BIT_TXSHORTCUT_VOUPDATEOK_8814B BIT(9)
+#define BIT_SEARCH_FAIL_8814B BIT(8)
+#define BIT_PWR_INT_127TO96_8814B BIT(7)
+#define BIT_PWR_INT_95TO64_8814B BIT(6)
+#define BIT_PWR_INT_63TO32_8814B BIT(5)
+#define BIT_PWR_INT_31TO0_8814B BIT(4)
+#define BIT_RX_DMA_STUCK_8814B BIT(3)
+#define BIT_TX_DMA_STUCK_8814B BIT(2)
+#define BIT_DDMA0_LP_INT_8814B BIT(1)
+#define BIT_DDMA0_HP_INT_8814B BIT(0)
+
+/* 2 REG_SW_MDIO_8814B */
+#define BIT_DIS_TIMEOUT_IO_8814B BIT(24)
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_HIMR_7_8814B */
+#define BIT_DATA_CPU_WDT_INT_MSK_8814B BIT(31)
+#define BIT_OFLD_TXDMA_ERR_MSK_8814B BIT(30)
+#define BIT_OFLD_TXDMA_FULL_MSK_8814B BIT(29)
+#define BIT_OFLD_RXDMA_OVR_MSK_8814B BIT(28)
+#define BIT_OFLD_RXDMA_ERR_MSK_8814B BIT(27)
+#define BIT_OFLD_RXDMA_DES_UA_MSK_8814B BIT(26)
+#define BIT_TXDMAOK_CHANNEL_16_MSK_8814B BIT(16)
+#define BIT_TXDMAOK_CHANNEL_13_MSK_8814B BIT(13)
+#define BIT_TXDMAOK_CHANNEL_12_MSK_8814B BIT(12)
+#define BIT_TXDMAOK_CHANNEL_11_MSK_8814B BIT(11)
+#define BIT_TXDMAOK_CHANNEL_10_MSK_8814B BIT(10)
+#define BIT_TXDMAOK_CHANNEL_9_MSK_8814B BIT(9)
+#define BIT_TXDMAOK_CHANNEL_8_MSK_8814B BIT(8)
+#define BIT_TXDMAOK_CHANNEL_7_MSK_8814B BIT(7)
+#define BIT_TXDMAOK_CHANNEL_6_MSK_8814B BIT(6)
+#define BIT_TXDMAOK_CHANNEL_5_MSK_8814B BIT(5)
+#define BIT_TXDMAOK_CHANNEL_4_MSK_8814B BIT(4)
+
+/* 2 REG_HISR_7_8814B */
+#define BIT_DATA_CPU_WDT_INT_8814B BIT(31)
+#define BIT_OFLD_TXDMA_ERR_8814B BIT(30)
+#define BIT_OFLD_TXDMA_FULL_8814B BIT(29)
+#define BIT_OFLD_RXDMA_OVR_8814B BIT(28)
+#define BIT_OFLD_RXDMA_ERR_8814B BIT(27)
+#define BIT_OFLD_RXDMA_DES_UA_8814B BIT(26)
+#define BIT_TXDMAOK_CHANNEL_16_8814B BIT(16)
+#define BIT_TXDMAOK_CHANNEL_13_8814B BIT(13)
+#define BIT_TXDMAOK_CHANNEL_12_8814B BIT(12)
+#define BIT_TXDMAOK_CHANNEL_11_8814B BIT(11)
+#define BIT_TXDMAOK_CHANNEL_10_8814B BIT(10)
+#define BIT_TXDMAOK_CHANNEL_9_8814B BIT(9)
+#define BIT_TXDMAOK_CHANNEL_8_8814B BIT(8)
+#define BIT_TXDMAOK_CHANNEL_7_8814B BIT(7)
+#define BIT_TXDMAOK_CHANNEL_6_8814B BIT(6)
+#define BIT_TXDMAOK_CHANNEL_5_8814B BIT(5)
+#define BIT_TXDMAOK_CHANNEL_4_8814B BIT(4)
+
+/* 2 REG_H2C_PKT_READADDR_8814B */
+
+#define BIT_SHIFT_H2C_PKT_READADDR_8814B 0
+#define BIT_MASK_H2C_PKT_READADDR_8814B 0x3ffff
+#define BIT_H2C_PKT_READADDR_8814B(x)                                          \
+	(((x) & BIT_MASK_H2C_PKT_READADDR_8814B)                               \
+	 << BIT_SHIFT_H2C_PKT_READADDR_8814B)
+#define BITS_H2C_PKT_READADDR_8814B                                            \
+	(BIT_MASK_H2C_PKT_READADDR_8814B << BIT_SHIFT_H2C_PKT_READADDR_8814B)
+#define BIT_CLEAR_H2C_PKT_READADDR_8814B(x)                                    \
+	((x) & (~BITS_H2C_PKT_READADDR_8814B))
+#define BIT_GET_H2C_PKT_READADDR_8814B(x)                                      \
+	(((x) >> BIT_SHIFT_H2C_PKT_READADDR_8814B) &                           \
+	 BIT_MASK_H2C_PKT_READADDR_8814B)
+#define BIT_SET_H2C_PKT_READADDR_8814B(x, v)                                   \
+	(BIT_CLEAR_H2C_PKT_READADDR_8814B(x) | BIT_H2C_PKT_READADDR_8814B(v))
+
+/* 2 REG_H2C_PKT_WRITEADDR_8814B */
+
+#define BIT_SHIFT_H2C_PKT_WRITEADDR_8814B 0
+#define BIT_MASK_H2C_PKT_WRITEADDR_8814B 0x3ffff
+#define BIT_H2C_PKT_WRITEADDR_8814B(x)                                         \
+	(((x) & BIT_MASK_H2C_PKT_WRITEADDR_8814B)                              \
+	 << BIT_SHIFT_H2C_PKT_WRITEADDR_8814B)
+#define BITS_H2C_PKT_WRITEADDR_8814B                                           \
+	(BIT_MASK_H2C_PKT_WRITEADDR_8814B << BIT_SHIFT_H2C_PKT_WRITEADDR_8814B)
+#define BIT_CLEAR_H2C_PKT_WRITEADDR_8814B(x)                                   \
+	((x) & (~BITS_H2C_PKT_WRITEADDR_8814B))
+#define BIT_GET_H2C_PKT_WRITEADDR_8814B(x)                                     \
+	(((x) >> BIT_SHIFT_H2C_PKT_WRITEADDR_8814B) &                          \
+	 BIT_MASK_H2C_PKT_WRITEADDR_8814B)
+#define BIT_SET_H2C_PKT_WRITEADDR_8814B(x, v)                                  \
+	(BIT_CLEAR_H2C_PKT_WRITEADDR_8814B(x) | BIT_H2C_PKT_WRITEADDR_8814B(v))
+
+/* 2 REG_MEM_PWR_CRTL_8814B */
+#define BIT_MEM_BB_SD_8814B BIT(17)
+#define BIT_MEM_BB_DS_8814B BIT(16)
+#define BIT_MEM_DENG_LS_8814B BIT(13)
+#define BIT_MEM_DENG_DS_8814B BIT(12)
+#define BIT_MEM_BT_DS_8814B BIT(10)
+#define BIT_MEM_SDIO_LS_8814B BIT(9)
+#define BIT_MEM_SDIO_DS_8814B BIT(8)
+#define BIT_MEM_USB_LS_8814B BIT(7)
+#define BIT_MEM_USB_DS_8814B BIT(6)
+#define BIT_MEM_PCI_LS_8814B BIT(5)
+#define BIT_MEM_PCI_DS_8814B BIT(4)
+#define BIT_MEM_WLMAC_LS_8814B BIT(3)
+#define BIT_MEM_WLMAC_DS_8814B BIT(2)
+#define BIT_MEM_WLMCU_LS_8814B BIT(1)
+#define BIT_MEM_WLMCU_DS_8814B BIT(0)
+
+/* 2 REG_FW_DRV_HANDSHAKE_8814B */
+
+#define BIT_SHIFT_FW_DRV_HANDSHAKE_8814B 0
+#define BIT_MASK_FW_DRV_HANDSHAKE_8814B 0xffffffffL
+#define BIT_FW_DRV_HANDSHAKE_8814B(x)                                          \
+	(((x) & BIT_MASK_FW_DRV_HANDSHAKE_8814B)                               \
+	 << BIT_SHIFT_FW_DRV_HANDSHAKE_8814B)
+#define BITS_FW_DRV_HANDSHAKE_8814B                                            \
+	(BIT_MASK_FW_DRV_HANDSHAKE_8814B << BIT_SHIFT_FW_DRV_HANDSHAKE_8814B)
+#define BIT_CLEAR_FW_DRV_HANDSHAKE_8814B(x)                                    \
+	((x) & (~BITS_FW_DRV_HANDSHAKE_8814B))
+#define BIT_GET_FW_DRV_HANDSHAKE_8814B(x)                                      \
+	(((x) >> BIT_SHIFT_FW_DRV_HANDSHAKE_8814B) &                           \
+	 BIT_MASK_FW_DRV_HANDSHAKE_8814B)
+#define BIT_SET_FW_DRV_HANDSHAKE_8814B(x, v)                                   \
+	(BIT_CLEAR_FW_DRV_HANDSHAKE_8814B(x) | BIT_FW_DRV_HANDSHAKE_8814B(v))
+
+/* 2 REG_FW_DBG0_8814B */
+
+#define BIT_SHIFT_FW_DBG0_8814B 0
+#define BIT_MASK_FW_DBG0_8814B 0xffffffffL
+#define BIT_FW_DBG0_8814B(x)                                                   \
+	(((x) & BIT_MASK_FW_DBG0_8814B) << BIT_SHIFT_FW_DBG0_8814B)
+#define BITS_FW_DBG0_8814B (BIT_MASK_FW_DBG0_8814B << BIT_SHIFT_FW_DBG0_8814B)
+#define BIT_CLEAR_FW_DBG0_8814B(x) ((x) & (~BITS_FW_DBG0_8814B))
+#define BIT_GET_FW_DBG0_8814B(x)                                               \
+	(((x) >> BIT_SHIFT_FW_DBG0_8814B) & BIT_MASK_FW_DBG0_8814B)
+#define BIT_SET_FW_DBG0_8814B(x, v)                                            \
+	(BIT_CLEAR_FW_DBG0_8814B(x) | BIT_FW_DBG0_8814B(v))
+
+/* 2 REG_FW_DBG1_8814B */
+
+#define BIT_SHIFT_FW_DBG1_8814B 0
+#define BIT_MASK_FW_DBG1_8814B 0xffffffffL
+#define BIT_FW_DBG1_8814B(x)                                                   \
+	(((x) & BIT_MASK_FW_DBG1_8814B) << BIT_SHIFT_FW_DBG1_8814B)
+#define BITS_FW_DBG1_8814B (BIT_MASK_FW_DBG1_8814B << BIT_SHIFT_FW_DBG1_8814B)
+#define BIT_CLEAR_FW_DBG1_8814B(x) ((x) & (~BITS_FW_DBG1_8814B))
+#define BIT_GET_FW_DBG1_8814B(x)                                               \
+	(((x) >> BIT_SHIFT_FW_DBG1_8814B) & BIT_MASK_FW_DBG1_8814B)
+#define BIT_SET_FW_DBG1_8814B(x, v)                                            \
+	(BIT_CLEAR_FW_DBG1_8814B(x) | BIT_FW_DBG1_8814B(v))
+
+/* 2 REG_FW_DBG2_8814B */
+
+#define BIT_SHIFT_FW_DBG2_8814B 0
+#define BIT_MASK_FW_DBG2_8814B 0xffffffffL
+#define BIT_FW_DBG2_8814B(x)                                                   \
+	(((x) & BIT_MASK_FW_DBG2_8814B) << BIT_SHIFT_FW_DBG2_8814B)
+#define BITS_FW_DBG2_8814B (BIT_MASK_FW_DBG2_8814B << BIT_SHIFT_FW_DBG2_8814B)
+#define BIT_CLEAR_FW_DBG2_8814B(x) ((x) & (~BITS_FW_DBG2_8814B))
+#define BIT_GET_FW_DBG2_8814B(x)                                               \
+	(((x) >> BIT_SHIFT_FW_DBG2_8814B) & BIT_MASK_FW_DBG2_8814B)
+#define BIT_SET_FW_DBG2_8814B(x, v)                                            \
+	(BIT_CLEAR_FW_DBG2_8814B(x) | BIT_FW_DBG2_8814B(v))
+
+/* 2 REG_FW_DBG3_8814B */
+
+#define BIT_SHIFT_FW_DBG3_8814B 0
+#define BIT_MASK_FW_DBG3_8814B 0xffffffffL
+#define BIT_FW_DBG3_8814B(x)                                                   \
+	(((x) & BIT_MASK_FW_DBG3_8814B) << BIT_SHIFT_FW_DBG3_8814B)
+#define BITS_FW_DBG3_8814B (BIT_MASK_FW_DBG3_8814B << BIT_SHIFT_FW_DBG3_8814B)
+#define BIT_CLEAR_FW_DBG3_8814B(x) ((x) & (~BITS_FW_DBG3_8814B))
+#define BIT_GET_FW_DBG3_8814B(x)                                               \
+	(((x) >> BIT_SHIFT_FW_DBG3_8814B) & BIT_MASK_FW_DBG3_8814B)
+#define BIT_SET_FW_DBG3_8814B(x, v)                                            \
+	(BIT_CLEAR_FW_DBG3_8814B(x) | BIT_FW_DBG3_8814B(v))
+
+/* 2 REG_FW_DBG4_8814B */
+
+#define BIT_SHIFT_FW_DBG4_8814B 0
+#define BIT_MASK_FW_DBG4_8814B 0xffffffffL
+#define BIT_FW_DBG4_8814B(x)                                                   \
+	(((x) & BIT_MASK_FW_DBG4_8814B) << BIT_SHIFT_FW_DBG4_8814B)
+#define BITS_FW_DBG4_8814B (BIT_MASK_FW_DBG4_8814B << BIT_SHIFT_FW_DBG4_8814B)
+#define BIT_CLEAR_FW_DBG4_8814B(x) ((x) & (~BITS_FW_DBG4_8814B))
+#define BIT_GET_FW_DBG4_8814B(x)                                               \
+	(((x) >> BIT_SHIFT_FW_DBG4_8814B) & BIT_MASK_FW_DBG4_8814B)
+#define BIT_SET_FW_DBG4_8814B(x, v)                                            \
+	(BIT_CLEAR_FW_DBG4_8814B(x) | BIT_FW_DBG4_8814B(v))
+
+/* 2 REG_FW_DBG5_8814B */
+
+#define BIT_SHIFT_FW_DBG5_8814B 0
+#define BIT_MASK_FW_DBG5_8814B 0xffffffffL
+#define BIT_FW_DBG5_8814B(x)                                                   \
+	(((x) & BIT_MASK_FW_DBG5_8814B) << BIT_SHIFT_FW_DBG5_8814B)
+#define BITS_FW_DBG5_8814B (BIT_MASK_FW_DBG5_8814B << BIT_SHIFT_FW_DBG5_8814B)
+#define BIT_CLEAR_FW_DBG5_8814B(x) ((x) & (~BITS_FW_DBG5_8814B))
+#define BIT_GET_FW_DBG5_8814B(x)                                               \
+	(((x) >> BIT_SHIFT_FW_DBG5_8814B) & BIT_MASK_FW_DBG5_8814B)
+#define BIT_SET_FW_DBG5_8814B(x, v)                                            \
+	(BIT_CLEAR_FW_DBG5_8814B(x) | BIT_FW_DBG5_8814B(v))
+
+/* 2 REG_FW_DBG6_8814B */
+
+#define BIT_SHIFT_FW_DBG6_8814B 0
+#define BIT_MASK_FW_DBG6_8814B 0xffffffffL
+#define BIT_FW_DBG6_8814B(x)                                                   \
+	(((x) & BIT_MASK_FW_DBG6_8814B) << BIT_SHIFT_FW_DBG6_8814B)
+#define BITS_FW_DBG6_8814B (BIT_MASK_FW_DBG6_8814B << BIT_SHIFT_FW_DBG6_8814B)
+#define BIT_CLEAR_FW_DBG6_8814B(x) ((x) & (~BITS_FW_DBG6_8814B))
+#define BIT_GET_FW_DBG6_8814B(x)                                               \
+	(((x) >> BIT_SHIFT_FW_DBG6_8814B) & BIT_MASK_FW_DBG6_8814B)
+#define BIT_SET_FW_DBG6_8814B(x, v)                                            \
+	(BIT_CLEAR_FW_DBG6_8814B(x) | BIT_FW_DBG6_8814B(v))
+
+/* 2 REG_FW_DBG7_8814B */
+
+#define BIT_SHIFT_FW_DBG7_8814B 0
+#define BIT_MASK_FW_DBG7_8814B 0xffffffffL
+#define BIT_FW_DBG7_8814B(x)                                                   \
+	(((x) & BIT_MASK_FW_DBG7_8814B) << BIT_SHIFT_FW_DBG7_8814B)
+#define BITS_FW_DBG7_8814B (BIT_MASK_FW_DBG7_8814B << BIT_SHIFT_FW_DBG7_8814B)
+#define BIT_CLEAR_FW_DBG7_8814B(x) ((x) & (~BITS_FW_DBG7_8814B))
+#define BIT_GET_FW_DBG7_8814B(x)                                               \
+	(((x) >> BIT_SHIFT_FW_DBG7_8814B) & BIT_MASK_FW_DBG7_8814B)
+#define BIT_SET_FW_DBG7_8814B(x, v)                                            \
+	(BIT_CLEAR_FW_DBG7_8814B(x) | BIT_FW_DBG7_8814B(v))
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_CR_8814B */
+
+#define BIT_SHIFT_LBMODE_8814B 24
+#define BIT_MASK_LBMODE_8814B 0x1f
+#define BIT_LBMODE_8814B(x)                                                    \
+	(((x) & BIT_MASK_LBMODE_8814B) << BIT_SHIFT_LBMODE_8814B)
+#define BITS_LBMODE_8814B (BIT_MASK_LBMODE_8814B << BIT_SHIFT_LBMODE_8814B)
+#define BIT_CLEAR_LBMODE_8814B(x) ((x) & (~BITS_LBMODE_8814B))
+#define BIT_GET_LBMODE_8814B(x)                                                \
+	(((x) >> BIT_SHIFT_LBMODE_8814B) & BIT_MASK_LBMODE_8814B)
+#define BIT_SET_LBMODE_8814B(x, v)                                             \
+	(BIT_CLEAR_LBMODE_8814B(x) | BIT_LBMODE_8814B(v))
+
+#define BIT_SHIFT_NETYPE1_8814B 18
+#define BIT_MASK_NETYPE1_8814B 0x3
+#define BIT_NETYPE1_8814B(x)                                                   \
+	(((x) & BIT_MASK_NETYPE1_8814B) << BIT_SHIFT_NETYPE1_8814B)
+#define BITS_NETYPE1_8814B (BIT_MASK_NETYPE1_8814B << BIT_SHIFT_NETYPE1_8814B)
+#define BIT_CLEAR_NETYPE1_8814B(x) ((x) & (~BITS_NETYPE1_8814B))
+#define BIT_GET_NETYPE1_8814B(x)                                               \
+	(((x) >> BIT_SHIFT_NETYPE1_8814B) & BIT_MASK_NETYPE1_8814B)
+#define BIT_SET_NETYPE1_8814B(x, v)                                            \
+	(BIT_CLEAR_NETYPE1_8814B(x) | BIT_NETYPE1_8814B(v))
+
+#define BIT_SHIFT_NETYPE0_8814B 16
+#define BIT_MASK_NETYPE0_8814B 0x3
+#define BIT_NETYPE0_8814B(x)                                                   \
+	(((x) & BIT_MASK_NETYPE0_8814B) << BIT_SHIFT_NETYPE0_8814B)
+#define BITS_NETYPE0_8814B (BIT_MASK_NETYPE0_8814B << BIT_SHIFT_NETYPE0_8814B)
+#define BIT_CLEAR_NETYPE0_8814B(x) ((x) & (~BITS_NETYPE0_8814B))
+#define BIT_GET_NETYPE0_8814B(x)                                               \
+	(((x) >> BIT_SHIFT_NETYPE0_8814B) & BIT_MASK_NETYPE0_8814B)
+#define BIT_SET_NETYPE0_8814B(x, v)                                            \
+	(BIT_CLEAR_NETYPE0_8814B(x) | BIT_NETYPE0_8814B(v))
+
+#define BIT_COUNTER_STS_EN_8814B BIT(13)
+#define BIT_I2C_MAILBOX_EN_8814B BIT(12)
+#define BIT_SHCUT_EN_8814B BIT(11)
+#define BIT_32K_CAL_TMR_EN_8814B BIT(10)
+#define BIT_MAC_SEC_EN_8814B BIT(9)
+#define BIT_ENSWBCN_8814B BIT(8)
+#define BIT_MACRXEN_8814B BIT(7)
+#define BIT_MACTXEN_8814B BIT(6)
+#define BIT_SCHEDULE_EN_8814B BIT(5)
+#define BIT_PROTOCOL_EN_8814B BIT(4)
+#define BIT_RXDMA_EN_8814B BIT(3)
+#define BIT_TXDMA_EN_8814B BIT(2)
+#define BIT_HCI_RXDMA_EN_8814B BIT(1)
+#define BIT_HCI_TXDMA_EN_8814B BIT(0)
+
+/* 2 REG_PG_SIZE_8814B */
+
+#define BIT_SHIFT_DBG_FIFO_SEL_8814B 16
+#define BIT_MASK_DBG_FIFO_SEL_8814B 0xff
+#define BIT_DBG_FIFO_SEL_8814B(x)                                              \
+	(((x) & BIT_MASK_DBG_FIFO_SEL_8814B) << BIT_SHIFT_DBG_FIFO_SEL_8814B)
+#define BITS_DBG_FIFO_SEL_8814B                                                \
+	(BIT_MASK_DBG_FIFO_SEL_8814B << BIT_SHIFT_DBG_FIFO_SEL_8814B)
+#define BIT_CLEAR_DBG_FIFO_SEL_8814B(x) ((x) & (~BITS_DBG_FIFO_SEL_8814B))
+#define BIT_GET_DBG_FIFO_SEL_8814B(x)                                          \
+	(((x) >> BIT_SHIFT_DBG_FIFO_SEL_8814B) & BIT_MASK_DBG_FIFO_SEL_8814B)
+#define BIT_SET_DBG_FIFO_SEL_8814B(x, v)                                       \
+	(BIT_CLEAR_DBG_FIFO_SEL_8814B(x) | BIT_DBG_FIFO_SEL_8814B(v))
+
+/* 2 REG_PKT_BUFF_ACCESS_CTRL_8814B */
+
+#define BIT_SHIFT_PKT_BUFF_ACCESS_CTRL_8814B 0
+#define BIT_MASK_PKT_BUFF_ACCESS_CTRL_8814B 0xff
+#define BIT_PKT_BUFF_ACCESS_CTRL_8814B(x)                                      \
+	(((x) & BIT_MASK_PKT_BUFF_ACCESS_CTRL_8814B)                           \
+	 << BIT_SHIFT_PKT_BUFF_ACCESS_CTRL_8814B)
+#define BITS_PKT_BUFF_ACCESS_CTRL_8814B                                        \
+	(BIT_MASK_PKT_BUFF_ACCESS_CTRL_8814B                                   \
+	 << BIT_SHIFT_PKT_BUFF_ACCESS_CTRL_8814B)
+#define BIT_CLEAR_PKT_BUFF_ACCESS_CTRL_8814B(x)                                \
+	((x) & (~BITS_PKT_BUFF_ACCESS_CTRL_8814B))
+#define BIT_GET_PKT_BUFF_ACCESS_CTRL_8814B(x)                                  \
+	(((x) >> BIT_SHIFT_PKT_BUFF_ACCESS_CTRL_8814B) &                       \
+	 BIT_MASK_PKT_BUFF_ACCESS_CTRL_8814B)
+#define BIT_SET_PKT_BUFF_ACCESS_CTRL_8814B(x, v)                               \
+	(BIT_CLEAR_PKT_BUFF_ACCESS_CTRL_8814B(x) |                             \
+	 BIT_PKT_BUFF_ACCESS_CTRL_8814B(v))
+
+/* 2 REG_TSF_CLK_STATE_8814B */
+#define BIT_TSF_CLK_STABLE_8814B BIT(15)
+
+/* 2 REG_TXDMA_PQ_MAP_8814B */
+
+#define BIT_SHIFT_TXDMA_H2C_MAP_8814B 16
+#define BIT_MASK_TXDMA_H2C_MAP_8814B 0x3
+#define BIT_TXDMA_H2C_MAP_8814B(x)                                             \
+	(((x) & BIT_MASK_TXDMA_H2C_MAP_8814B) << BIT_SHIFT_TXDMA_H2C_MAP_8814B)
+#define BITS_TXDMA_H2C_MAP_8814B                                               \
+	(BIT_MASK_TXDMA_H2C_MAP_8814B << BIT_SHIFT_TXDMA_H2C_MAP_8814B)
+#define BIT_CLEAR_TXDMA_H2C_MAP_8814B(x) ((x) & (~BITS_TXDMA_H2C_MAP_8814B))
+#define BIT_GET_TXDMA_H2C_MAP_8814B(x)                                         \
+	(((x) >> BIT_SHIFT_TXDMA_H2C_MAP_8814B) & BIT_MASK_TXDMA_H2C_MAP_8814B)
+#define BIT_SET_TXDMA_H2C_MAP_8814B(x, v)                                      \
+	(BIT_CLEAR_TXDMA_H2C_MAP_8814B(x) | BIT_TXDMA_H2C_MAP_8814B(v))
+
+#define BIT_SHIFT_TXDMA_HIQ_MAP_8814B 14
+#define BIT_MASK_TXDMA_HIQ_MAP_8814B 0x3
+#define BIT_TXDMA_HIQ_MAP_8814B(x)                                             \
+	(((x) & BIT_MASK_TXDMA_HIQ_MAP_8814B) << BIT_SHIFT_TXDMA_HIQ_MAP_8814B)
+#define BITS_TXDMA_HIQ_MAP_8814B                                               \
+	(BIT_MASK_TXDMA_HIQ_MAP_8814B << BIT_SHIFT_TXDMA_HIQ_MAP_8814B)
+#define BIT_CLEAR_TXDMA_HIQ_MAP_8814B(x) ((x) & (~BITS_TXDMA_HIQ_MAP_8814B))
+#define BIT_GET_TXDMA_HIQ_MAP_8814B(x)                                         \
+	(((x) >> BIT_SHIFT_TXDMA_HIQ_MAP_8814B) & BIT_MASK_TXDMA_HIQ_MAP_8814B)
+#define BIT_SET_TXDMA_HIQ_MAP_8814B(x, v)                                      \
+	(BIT_CLEAR_TXDMA_HIQ_MAP_8814B(x) | BIT_TXDMA_HIQ_MAP_8814B(v))
+
+#define BIT_SHIFT_TXDMA_MGQ_MAP_8814B 12
+#define BIT_MASK_TXDMA_MGQ_MAP_8814B 0x3
+#define BIT_TXDMA_MGQ_MAP_8814B(x)                                             \
+	(((x) & BIT_MASK_TXDMA_MGQ_MAP_8814B) << BIT_SHIFT_TXDMA_MGQ_MAP_8814B)
+#define BITS_TXDMA_MGQ_MAP_8814B                                               \
+	(BIT_MASK_TXDMA_MGQ_MAP_8814B << BIT_SHIFT_TXDMA_MGQ_MAP_8814B)
+#define BIT_CLEAR_TXDMA_MGQ_MAP_8814B(x) ((x) & (~BITS_TXDMA_MGQ_MAP_8814B))
+#define BIT_GET_TXDMA_MGQ_MAP_8814B(x)                                         \
+	(((x) >> BIT_SHIFT_TXDMA_MGQ_MAP_8814B) & BIT_MASK_TXDMA_MGQ_MAP_8814B)
+#define BIT_SET_TXDMA_MGQ_MAP_8814B(x, v)                                      \
+	(BIT_CLEAR_TXDMA_MGQ_MAP_8814B(x) | BIT_TXDMA_MGQ_MAP_8814B(v))
+
+#define BIT_SHIFT_TXDMA_BKQ_MAP_8814B 10
+#define BIT_MASK_TXDMA_BKQ_MAP_8814B 0x3
+#define BIT_TXDMA_BKQ_MAP_8814B(x)                                             \
+	(((x) & BIT_MASK_TXDMA_BKQ_MAP_8814B) << BIT_SHIFT_TXDMA_BKQ_MAP_8814B)
+#define BITS_TXDMA_BKQ_MAP_8814B                                               \
+	(BIT_MASK_TXDMA_BKQ_MAP_8814B << BIT_SHIFT_TXDMA_BKQ_MAP_8814B)
+#define BIT_CLEAR_TXDMA_BKQ_MAP_8814B(x) ((x) & (~BITS_TXDMA_BKQ_MAP_8814B))
+#define BIT_GET_TXDMA_BKQ_MAP_8814B(x)                                         \
+	(((x) >> BIT_SHIFT_TXDMA_BKQ_MAP_8814B) & BIT_MASK_TXDMA_BKQ_MAP_8814B)
+#define BIT_SET_TXDMA_BKQ_MAP_8814B(x, v)                                      \
+	(BIT_CLEAR_TXDMA_BKQ_MAP_8814B(x) | BIT_TXDMA_BKQ_MAP_8814B(v))
+
+#define BIT_SHIFT_TXDMA_BEQ_MAP_8814B 8
+#define BIT_MASK_TXDMA_BEQ_MAP_8814B 0x3
+#define BIT_TXDMA_BEQ_MAP_8814B(x)                                             \
+	(((x) & BIT_MASK_TXDMA_BEQ_MAP_8814B) << BIT_SHIFT_TXDMA_BEQ_MAP_8814B)
+#define BITS_TXDMA_BEQ_MAP_8814B                                               \
+	(BIT_MASK_TXDMA_BEQ_MAP_8814B << BIT_SHIFT_TXDMA_BEQ_MAP_8814B)
+#define BIT_CLEAR_TXDMA_BEQ_MAP_8814B(x) ((x) & (~BITS_TXDMA_BEQ_MAP_8814B))
+#define BIT_GET_TXDMA_BEQ_MAP_8814B(x)                                         \
+	(((x) >> BIT_SHIFT_TXDMA_BEQ_MAP_8814B) & BIT_MASK_TXDMA_BEQ_MAP_8814B)
+#define BIT_SET_TXDMA_BEQ_MAP_8814B(x, v)                                      \
+	(BIT_CLEAR_TXDMA_BEQ_MAP_8814B(x) | BIT_TXDMA_BEQ_MAP_8814B(v))
+
+#define BIT_SHIFT_TXDMA_VIQ_MAP_8814B 6
+#define BIT_MASK_TXDMA_VIQ_MAP_8814B 0x3
+#define BIT_TXDMA_VIQ_MAP_8814B(x)                                             \
+	(((x) & BIT_MASK_TXDMA_VIQ_MAP_8814B) << BIT_SHIFT_TXDMA_VIQ_MAP_8814B)
+#define BITS_TXDMA_VIQ_MAP_8814B                                               \
+	(BIT_MASK_TXDMA_VIQ_MAP_8814B << BIT_SHIFT_TXDMA_VIQ_MAP_8814B)
+#define BIT_CLEAR_TXDMA_VIQ_MAP_8814B(x) ((x) & (~BITS_TXDMA_VIQ_MAP_8814B))
+#define BIT_GET_TXDMA_VIQ_MAP_8814B(x)                                         \
+	(((x) >> BIT_SHIFT_TXDMA_VIQ_MAP_8814B) & BIT_MASK_TXDMA_VIQ_MAP_8814B)
+#define BIT_SET_TXDMA_VIQ_MAP_8814B(x, v)                                      \
+	(BIT_CLEAR_TXDMA_VIQ_MAP_8814B(x) | BIT_TXDMA_VIQ_MAP_8814B(v))
+
+#define BIT_SHIFT_TXDMA_VOQ_MAP_8814B 4
+#define BIT_MASK_TXDMA_VOQ_MAP_8814B 0x3
+#define BIT_TXDMA_VOQ_MAP_8814B(x)                                             \
+	(((x) & BIT_MASK_TXDMA_VOQ_MAP_8814B) << BIT_SHIFT_TXDMA_VOQ_MAP_8814B)
+#define BITS_TXDMA_VOQ_MAP_8814B                                               \
+	(BIT_MASK_TXDMA_VOQ_MAP_8814B << BIT_SHIFT_TXDMA_VOQ_MAP_8814B)
+#define BIT_CLEAR_TXDMA_VOQ_MAP_8814B(x) ((x) & (~BITS_TXDMA_VOQ_MAP_8814B))
+#define BIT_GET_TXDMA_VOQ_MAP_8814B(x)                                         \
+	(((x) >> BIT_SHIFT_TXDMA_VOQ_MAP_8814B) & BIT_MASK_TXDMA_VOQ_MAP_8814B)
+#define BIT_SET_TXDMA_VOQ_MAP_8814B(x, v)                                      \
+	(BIT_CLEAR_TXDMA_VOQ_MAP_8814B(x) | BIT_TXDMA_VOQ_MAP_8814B(v))
+
+#define BIT_RXDMA_AGG_EN_8814B BIT(2)
+#define BIT_RXSHFT_EN_8814B BIT(1)
+#define BIT_RXDMA_ARBBW_EN_8814B BIT(0)
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_TRXFF_BNDY_8814B */
+
+#define BIT_SHIFT_FWFFOVFL_RSV_8814B 16
+#define BIT_MASK_FWFFOVFL_RSV_8814B 0xf
+#define BIT_FWFFOVFL_RSV_8814B(x)                                              \
+	(((x) & BIT_MASK_FWFFOVFL_RSV_8814B) << BIT_SHIFT_FWFFOVFL_RSV_8814B)
+#define BITS_FWFFOVFL_RSV_8814B                                                \
+	(BIT_MASK_FWFFOVFL_RSV_8814B << BIT_SHIFT_FWFFOVFL_RSV_8814B)
+#define BIT_CLEAR_FWFFOVFL_RSV_8814B(x) ((x) & (~BITS_FWFFOVFL_RSV_8814B))
+#define BIT_GET_FWFFOVFL_RSV_8814B(x)                                          \
+	(((x) >> BIT_SHIFT_FWFFOVFL_RSV_8814B) & BIT_MASK_FWFFOVFL_RSV_8814B)
+#define BIT_SET_FWFFOVFL_RSV_8814B(x, v)                                       \
+	(BIT_CLEAR_FWFFOVFL_RSV_8814B(x) | BIT_FWFFOVFL_RSV_8814B(v))
+
+#define BIT_SHIFT_RXFFOVFL_RSV_V2_8814B 8
+#define BIT_MASK_RXFFOVFL_RSV_V2_8814B 0xf
+#define BIT_RXFFOVFL_RSV_V2_8814B(x)                                           \
+	(((x) & BIT_MASK_RXFFOVFL_RSV_V2_8814B)                                \
+	 << BIT_SHIFT_RXFFOVFL_RSV_V2_8814B)
+#define BITS_RXFFOVFL_RSV_V2_8814B                                             \
+	(BIT_MASK_RXFFOVFL_RSV_V2_8814B << BIT_SHIFT_RXFFOVFL_RSV_V2_8814B)
+#define BIT_CLEAR_RXFFOVFL_RSV_V2_8814B(x) ((x) & (~BITS_RXFFOVFL_RSV_V2_8814B))
+#define BIT_GET_RXFFOVFL_RSV_V2_8814B(x)                                       \
+	(((x) >> BIT_SHIFT_RXFFOVFL_RSV_V2_8814B) &                            \
+	 BIT_MASK_RXFFOVFL_RSV_V2_8814B)
+#define BIT_SET_RXFFOVFL_RSV_V2_8814B(x, v)                                    \
+	(BIT_CLEAR_RXFFOVFL_RSV_V2_8814B(x) | BIT_RXFFOVFL_RSV_V2_8814B(v))
+
+/* 2 REG_PTA_I2C_MBOX_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+#define BIT_SHIFT_I2C_M_STATUS_8814B 8
+#define BIT_MASK_I2C_M_STATUS_8814B 0xf
+#define BIT_I2C_M_STATUS_8814B(x)                                              \
+	(((x) & BIT_MASK_I2C_M_STATUS_8814B) << BIT_SHIFT_I2C_M_STATUS_8814B)
+#define BITS_I2C_M_STATUS_8814B                                                \
+	(BIT_MASK_I2C_M_STATUS_8814B << BIT_SHIFT_I2C_M_STATUS_8814B)
+#define BIT_CLEAR_I2C_M_STATUS_8814B(x) ((x) & (~BITS_I2C_M_STATUS_8814B))
+#define BIT_GET_I2C_M_STATUS_8814B(x)                                          \
+	(((x) >> BIT_SHIFT_I2C_M_STATUS_8814B) & BIT_MASK_I2C_M_STATUS_8814B)
+#define BIT_SET_I2C_M_STATUS_8814B(x, v)                                       \
+	(BIT_CLEAR_I2C_M_STATUS_8814B(x) | BIT_I2C_M_STATUS_8814B(v))
+
+#define BIT_SHIFT_I2C_M_BUS_GNT_FW_8814B 4
+#define BIT_MASK_I2C_M_BUS_GNT_FW_8814B 0x7
+#define BIT_I2C_M_BUS_GNT_FW_8814B(x)                                          \
+	(((x) & BIT_MASK_I2C_M_BUS_GNT_FW_8814B)                               \
+	 << BIT_SHIFT_I2C_M_BUS_GNT_FW_8814B)
+#define BITS_I2C_M_BUS_GNT_FW_8814B                                            \
+	(BIT_MASK_I2C_M_BUS_GNT_FW_8814B << BIT_SHIFT_I2C_M_BUS_GNT_FW_8814B)
+#define BIT_CLEAR_I2C_M_BUS_GNT_FW_8814B(x)                                    \
+	((x) & (~BITS_I2C_M_BUS_GNT_FW_8814B))
+#define BIT_GET_I2C_M_BUS_GNT_FW_8814B(x)                                      \
+	(((x) >> BIT_SHIFT_I2C_M_BUS_GNT_FW_8814B) &                           \
+	 BIT_MASK_I2C_M_BUS_GNT_FW_8814B)
+#define BIT_SET_I2C_M_BUS_GNT_FW_8814B(x, v)                                   \
+	(BIT_CLEAR_I2C_M_BUS_GNT_FW_8814B(x) | BIT_I2C_M_BUS_GNT_FW_8814B(v))
+
+#define BIT_I2C_M_GNT_FW_8814B BIT(3)
+
+#define BIT_SHIFT_I2C_M_SPEED_8814B 1
+#define BIT_MASK_I2C_M_SPEED_8814B 0x3
+#define BIT_I2C_M_SPEED_8814B(x)                                               \
+	(((x) & BIT_MASK_I2C_M_SPEED_8814B) << BIT_SHIFT_I2C_M_SPEED_8814B)
+#define BITS_I2C_M_SPEED_8814B                                                 \
+	(BIT_MASK_I2C_M_SPEED_8814B << BIT_SHIFT_I2C_M_SPEED_8814B)
+#define BIT_CLEAR_I2C_M_SPEED_8814B(x) ((x) & (~BITS_I2C_M_SPEED_8814B))
+#define BIT_GET_I2C_M_SPEED_8814B(x)                                           \
+	(((x) >> BIT_SHIFT_I2C_M_SPEED_8814B) & BIT_MASK_I2C_M_SPEED_8814B)
+#define BIT_SET_I2C_M_SPEED_8814B(x, v)                                        \
+	(BIT_CLEAR_I2C_M_SPEED_8814B(x) | BIT_I2C_M_SPEED_8814B(v))
+
+#define BIT_I2C_M_UNLOCK_8814B BIT(0)
+
+/* 2 REG_RXFF_BNDY_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+#define BIT_SHIFT_RXFF0_BNDY_V2_8814B 0
+#define BIT_MASK_RXFF0_BNDY_V2_8814B 0x3ffff
+#define BIT_RXFF0_BNDY_V2_8814B(x)                                             \
+	(((x) & BIT_MASK_RXFF0_BNDY_V2_8814B) << BIT_SHIFT_RXFF0_BNDY_V2_8814B)
+#define BITS_RXFF0_BNDY_V2_8814B                                               \
+	(BIT_MASK_RXFF0_BNDY_V2_8814B << BIT_SHIFT_RXFF0_BNDY_V2_8814B)
+#define BIT_CLEAR_RXFF0_BNDY_V2_8814B(x) ((x) & (~BITS_RXFF0_BNDY_V2_8814B))
+#define BIT_GET_RXFF0_BNDY_V2_8814B(x)                                         \
+	(((x) >> BIT_SHIFT_RXFF0_BNDY_V2_8814B) & BIT_MASK_RXFF0_BNDY_V2_8814B)
+#define BIT_SET_RXFF0_BNDY_V2_8814B(x, v)                                      \
+	(BIT_CLEAR_RXFF0_BNDY_V2_8814B(x) | BIT_RXFF0_BNDY_V2_8814B(v))
+
+/* 2 REG_FE1IMR_8814B */
+#define BIT_CPUMGQ_DROP_BY_HOLD_TIME_INT_EN_8814B BIT(31)
+#define BIT_FWFF_FULL_INT_EN_8814B BIT(30)
+#define BIT_BB_STOP_RX_INT_EN_8814B BIT(29)
+#define BIT_FS_RXDMA2_DONE_INT_EN_8814B BIT(28)
+#define BIT_FS_RXDONE3_INT_EN_8814B BIT(27)
+#define BIT_FS_RXDONE2_INT_EN_8814B BIT(26)
+#define BIT_FS_RX_BCN_P4_INT_EN_8814B BIT(25)
+#define BIT_FS_RX_BCN_P3_INT_EN_8814B BIT(24)
+#define BIT_FS_RX_BCN_P2_INT_EN_8814B BIT(23)
+#define BIT_FS_RX_BCN_P1_INT_EN_8814B BIT(22)
+#define BIT_FS_RX_BCN_P0_INT_EN_8814B BIT(21)
+#define BIT_FS_RX_UMD0_INT_EN_8814B BIT(20)
+#define BIT_FS_RX_UMD1_INT_EN_8814B BIT(19)
+#define BIT_FS_RX_BMD0_INT_EN_8814B BIT(18)
+#define BIT_FS_RX_BMD1_INT_EN_8814B BIT(17)
+#define BIT_FS_RXDONE_INT_EN_8814B BIT(16)
+#define BIT_FS_WWLAN_INT_EN_8814B BIT(15)
+#define BIT_FS_SOUND_DONE_INT_EN_8814B BIT(14)
+#define BIT_FS_TRL_MTR_INT_EN_8814B BIT(12)
+#define BIT_FS_BF1_PRETO_INT_EN_8814B BIT(11)
+#define BIT_FS_BF0_PRETO_INT_EN_8814B BIT(10)
+#define BIT_FS_PTCL_RELEASE_MACID_INT_EN_8814B BIT(9)
+#define BIT_PRETX_ERRHLD_INT_EN_8814B BIT(8)
+#define BIT_FS_GTRD_INT_EN_8814B BIT(7)
+#define BIT_FS_LTE_COEX_EN_8814B BIT(6)
+#define BIT_FS_WLACTOFF_INT_EN_8814B BIT(5)
+#define BIT_FS_WLACTON_INT_EN_8814B BIT(4)
+#define BIT_FS_BTCMD_INT_EN_8814B BIT(3)
+#define BIT_FS_REG_MAILBOX_TO_I2C_INT_EN_8814B BIT(2)
+#define BIT_FS_TRPC_TO_INT_EN_V1_8814B BIT(1)
+#define BIT_FS_RPC_O_T_INT_EN_V1_8814B BIT(0)
+
+/* 2 REG_FE1ISR_8814B */
+#define BIT_CPUMGQ_DROP_BY_HOLD_TIME_INT_8814B BIT(31)
+#define BIT_FWFF_FULL_INT_8814B BIT(30)
+#define BIT_BB_STOP_RX_INT_8814B BIT(29)
+#define BIT_FS_RXDMA2_DONE_INT_8814B BIT(28)
+#define BIT_FS_RXDONE3_INT_INT_8814B BIT(27)
+#define BIT_FS_RXDONE2_INT_8814B BIT(26)
+#define BIT_FS_RX_BCN_P4_INT_8814B BIT(25)
+#define BIT_FS_RX_BCN_P3_INT_8814B BIT(24)
+#define BIT_FS_RX_BCN_P2_INT_8814B BIT(23)
+#define BIT_FS_RX_BCN_P1_INT_8814B BIT(22)
+#define BIT_FS_RX_BCN_P0_INT_8814B BIT(21)
+#define BIT_FS_RX_UMD0_INT_8814B BIT(20)
+#define BIT_FS_RX_UMD1_INT_8814B BIT(19)
+#define BIT_FS_RX_BMD0_INT_8814B BIT(18)
+#define BIT_FS_RX_BMD1_INT_8814B BIT(17)
+#define BIT_FS_RXDONE_INT_8814B BIT(16)
+#define BIT_FS_WWLAN_INT_8814B BIT(15)
+#define BIT_FS_SOUND_DONE_INT_8814B BIT(14)
+#define BIT_FS_TRL_MTR_INT_8814B BIT(12)
+#define BIT_FS_BF1_PRETO_INT_8814B BIT(11)
+#define BIT_FS_BF0_PRETO_INT_8814B BIT(10)
+#define BIT_FS_PTCL_RELEASE_MACID_INT_8814B BIT(9)
+#define BIT_PRETX_ERRHLD_INT_8814B BIT(8)
+#define BIT_SND_RDY_INT_8814B BIT(7)
+#define BIT_FS_LTE_COEX_INT_8814B BIT(6)
+#define BIT_FS_WLACTOFF_INT_8814B BIT(5)
+#define BIT_FS_WLACTON_INT_8814B BIT(4)
+#define BIT_BT_CMD_INT_8814B BIT(3)
+#define BIT_FS_MAILBOX_TO_I2C_INT_8814B BIT(2)
+#define BIT_FS_TRPC_TO_INT_8814B BIT(1)
+#define BIT_FS_RPC_O_T_INT_8814B BIT(0)
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_CPWM_8814B */
+#define BIT_CPWM_TOGGLING_8814B BIT(31)
+
+#define BIT_SHIFT_CPWM_MOD_8814B 24
+#define BIT_MASK_CPWM_MOD_8814B 0x7f
+#define BIT_CPWM_MOD_8814B(x)                                                  \
+	(((x) & BIT_MASK_CPWM_MOD_8814B) << BIT_SHIFT_CPWM_MOD_8814B)
+#define BITS_CPWM_MOD_8814B                                                    \
+	(BIT_MASK_CPWM_MOD_8814B << BIT_SHIFT_CPWM_MOD_8814B)
+#define BIT_CLEAR_CPWM_MOD_8814B(x) ((x) & (~BITS_CPWM_MOD_8814B))
+#define BIT_GET_CPWM_MOD_8814B(x)                                              \
+	(((x) >> BIT_SHIFT_CPWM_MOD_8814B) & BIT_MASK_CPWM_MOD_8814B)
+#define BIT_SET_CPWM_MOD_8814B(x, v)                                           \
+	(BIT_CLEAR_CPWM_MOD_8814B(x) | BIT_CPWM_MOD_8814B(v))
+
+/* 2 REG_FWIMR_8814B */
+#define BIT_FS_TXBCNOK_MB7_INT_EN_8814B BIT(31)
+#define BIT_FS_TXBCNOK_MB6_INT_EN_8814B BIT(30)
+#define BIT_FS_TXBCNOK_MB5_INT_EN_8814B BIT(29)
+#define BIT_FS_TXBCNOK_MB4_INT_EN_8814B BIT(28)
+#define BIT_FS_TXBCNOK_MB3_INT_EN_8814B BIT(27)
+#define BIT_FS_TXBCNOK_MB2_INT_EN_8814B BIT(26)
+#define BIT_FS_TXBCNOK_MB1_INT_EN_8814B BIT(25)
+#define BIT_FS_TXBCNOK_MB0_INT_EN_8814B BIT(24)
+#define BIT_FS_TXBCNERR_MB7_INT_EN_8814B BIT(23)
+#define BIT_FS_TXBCNERR_MB6_INT_EN_8814B BIT(22)
+#define BIT_FS_TXBCNERR_MB5_INT_EN_8814B BIT(21)
+#define BIT_FS_TXBCNERR_MB4_INT_EN_8814B BIT(20)
+#define BIT_FS_TXBCNERR_MB3_INT_EN_8814B BIT(19)
+#define BIT_FS_TXBCNERR_MB2_INT_EN_8814B BIT(18)
+#define BIT_FS_TXBCNERR_MB1_INT_EN_8814B BIT(17)
+#define BIT_FS_TXBCNERR_MB0_INT_EN_8814B BIT(16)
+#define BIT_CPU_MGQ_TXDONE_INT_EN_8814B BIT(15)
+#define BIT_SIFS_OVERSPEC_INT_EN_8814B BIT(14)
+#define BIT_FS_MGNTQ_RPTR_RELEASE_INT_EN_8814B BIT(13)
+#define BIT_FS_MGNTQFF_TO_INT_EN_8814B BIT(12)
+#define BIT_FS_CPUMGQ_ERR_INT_EN_8814B BIT(11)
+#define BIT_FS_DDMA0_LP_INT_EN_8814B BIT(9)
+#define BIT_FS_DDMA0_HP_INT_EN_8814B BIT(8)
+#define BIT_FS_TRXRPT_INT_EN_8814B BIT(7)
+#define BIT_FS_C2H_W_READY_INT_EN_8814B BIT(6)
+#define BIT_FS_HRCV_INT_EN_8814B BIT(5)
+#define BIT_FS_H2CCMD_INT_EN_8814B BIT(4)
+#define BIT_FS_TXPKTIN_INT_EN_8814B BIT(3)
+#define BIT_FS_ERRORHDL_INT_EN_8814B BIT(2)
+#define BIT_FS_TXCCX_INT_EN_8814B BIT(1)
+#define BIT_FS_TXCLOSE_INT_EN_8814B BIT(0)
+
+/* 2 REG_FWISR_8814B */
+#define BIT_FS_TXBCNOK_MB7_INT_8814B BIT(31)
+#define BIT_FS_TXBCNOK_MB6_INT_8814B BIT(30)
+#define BIT_FS_TXBCNOK_MB5_INT_8814B BIT(29)
+#define BIT_FS_TXBCNOK_MB4_INT_8814B BIT(28)
+#define BIT_FS_TXBCNOK_MB3_INT_8814B BIT(27)
+#define BIT_FS_TXBCNOK_MB2_INT_8814B BIT(26)
+#define BIT_FS_TXBCNOK_MB1_INT_8814B BIT(25)
+#define BIT_FS_TXBCNOK_MB0_INT_8814B BIT(24)
+#define BIT_FS_TXBCNERR_MB7_INT_8814B BIT(23)
+#define BIT_FS_TXBCNERR_MB6_INT_8814B BIT(22)
+#define BIT_FS_TXBCNERR_MB5_INT_8814B BIT(21)
+#define BIT_FS_TXBCNERR_MB4_INT_8814B BIT(20)
+#define BIT_FS_TXBCNERR_MB3_INT_8814B BIT(19)
+#define BIT_FS_TXBCNERR_MB2_INT_8814B BIT(18)
+#define BIT_FS_TXBCNERR_MB1_INT_8814B BIT(17)
+#define BIT_FS_TXBCNERR_MB0_INT_8814B BIT(16)
+#define BIT_CPU_MGQ_TXDONE_INT_8814B BIT(15)
+#define BIT_SIFS_OVERSPEC_INT_8814B BIT(14)
+#define BIT_FS_MGNTQ_RPTR_RELEASE_INT_8814B BIT(13)
+#define BIT_FS_MGNTQFF_TO_INT_8814B BIT(12)
+#define BIT_FS_CPUMGQ_ERR_INT_8814B BIT(11)
+#define BIT_FWCMD_PKTIN_INT_8814B BIT(10)
+#define BIT_FS_DDMA0_LP_INT_8814B BIT(9)
+#define BIT_FS_DDMA0_HP_INT_8814B BIT(8)
+#define BIT_FS_TRXRPT_INT_8814B BIT(7)
+#define BIT_FS_C2H_W_READY_INT_8814B BIT(6)
+#define BIT_FS_HRCV_INT_8814B BIT(5)
+#define BIT_FS_H2CCMD_INT_8814B BIT(4)
+#define BIT_FS_TXPKTIN_INT_8814B BIT(3)
+#define BIT_FS_ERRORHDL_INT_8814B BIT(2)
+#define BIT_FS_TXCCX_INT_8814B BIT(1)
+#define BIT_FS_TXCLOSE_INT_8814B BIT(0)
+
+/* 2 REG_FTIMR_8814B */
+#define BIT_PS_TIMER_C_EARLY_INT_EN_8814B BIT(23)
+#define BIT_PS_TIMER_B_EARLY_INT_EN_8814B BIT(22)
+#define BIT_PS_TIMER_A_EARLY_INT_EN_8814B BIT(21)
+#define BIT_CPUMGQ_TX_TIMER_EARLY_INT_EN_8814B BIT(20)
+#define BIT_PS_TIMER_C_INT_EN_8814B BIT(19)
+#define BIT_PS_TIMER_B_INT_EN_8814B BIT(18)
+#define BIT_PS_TIMER_A_INT_EN_8814B BIT(17)
+#define BIT_CPUMGQ_TX_TIMER_INT_EN_8814B BIT(16)
+#define BIT_FS_PS_TIMEOUT2_EN_8814B BIT(15)
+#define BIT_FS_PS_TIMEOUT1_EN_8814B BIT(14)
+#define BIT_FS_PS_TIMEOUT0_EN_8814B BIT(13)
+#define BIT_FS_GTINT12_EN_8814B BIT(12)
+#define BIT_FS_GTINT11_EN_8814B BIT(11)
+#define BIT_FS_GTINT10_EN_8814B BIT(10)
+#define BIT_FS_GTINT9_EN_8814B BIT(9)
+#define BIT_FS_GTINT8_EN_8814B BIT(8)
+#define BIT_FS_GTINT7_EN_8814B BIT(7)
+#define BIT_FS_GTINT6_EN_8814B BIT(6)
+#define BIT_FS_GTINT5_EN_8814B BIT(5)
+#define BIT_FS_GTINT4_EN_8814B BIT(4)
+#define BIT_FS_GTINT3_EN_8814B BIT(3)
+#define BIT_FS_GTINT2_EN_8814B BIT(2)
+#define BIT_FS_GTINT1_EN_8814B BIT(1)
+#define BIT_FS_GTINT0_EN_8814B BIT(0)
+
+/* 2 REG_FTISR_8814B */
+#define BIT_PS_TIMER_5_EARLY__INT_8814B BIT(26)
+#define BIT_PS_TIMER_4_EARLY__INT_8814B BIT(25)
+#define BIT_PS_TIMER_3_EARLY__INT_8814B BIT(24)
+#define BIT_PS_TIMER_2_EARLY__INT_8814B BIT(23)
+#define BIT_PS_TIMER_1_EARLY__INT_8814B BIT(22)
+#define BIT_PS_TIMER_0_EARLY__INT_8814B BIT(21)
+#define BIT_CPUMGQ_TX_TIMER_EARLY_INT_8814B BIT(20)
+#define BIT_PS_TIMER_5_INT_8814B BIT(19)
+#define BIT_PS_TIMER_4_INT_8814B BIT(18)
+#define BIT_PS_TIMER_3_INT_8814B BIT(17)
+#define BIT_CPUMGQ_TX_TIMER_INT_8814B BIT(16)
+#define BIT_PS_TIMER_2_INT_8814B BIT(15)
+#define BIT_PS_TIMER_1_INT_8814B BIT(14)
+#define BIT_PS_TIMER_0_INT_8814B BIT(13)
+#define BIT_FS_GTINT12_INT_8814B BIT(12)
+#define BIT_FS_GTINT11_INT_8814B BIT(11)
+#define BIT_FS_GTINT10_INT_8814B BIT(10)
+#define BIT_FS_GTINT9_INT_8814B BIT(9)
+#define BIT_FS_GTINT8_INT_8814B BIT(8)
+#define BIT_FS_GTINT7_INT_8814B BIT(7)
+#define BIT_FS_GTINT6_INT_8814B BIT(6)
+#define BIT_FS_GTINT5_INT_8814B BIT(5)
+#define BIT_FS_GTINT4_INT_8814B BIT(4)
+#define BIT_FS_GTINT3_INT_8814B BIT(3)
+#define BIT_FS_GTINT2_INT_8814B BIT(2)
+#define BIT_FS_GTINT1_INT_8814B BIT(1)
+#define BIT_FS_GTINT0_INT_8814B BIT(0)
+
+/* 2 REG_PKTBUF_DBG_CTRL_8814B */
+
+#define BIT_SHIFT_PKTBUF_WRITE_EN_8814B 24
+#define BIT_MASK_PKTBUF_WRITE_EN_8814B 0xff
+#define BIT_PKTBUF_WRITE_EN_8814B(x)                                           \
+	(((x) & BIT_MASK_PKTBUF_WRITE_EN_8814B)                                \
+	 << BIT_SHIFT_PKTBUF_WRITE_EN_8814B)
+#define BITS_PKTBUF_WRITE_EN_8814B                                             \
+	(BIT_MASK_PKTBUF_WRITE_EN_8814B << BIT_SHIFT_PKTBUF_WRITE_EN_8814B)
+#define BIT_CLEAR_PKTBUF_WRITE_EN_8814B(x) ((x) & (~BITS_PKTBUF_WRITE_EN_8814B))
+#define BIT_GET_PKTBUF_WRITE_EN_8814B(x)                                       \
+	(((x) >> BIT_SHIFT_PKTBUF_WRITE_EN_8814B) &                            \
+	 BIT_MASK_PKTBUF_WRITE_EN_8814B)
+#define BIT_SET_PKTBUF_WRITE_EN_8814B(x, v)                                    \
+	(BIT_CLEAR_PKTBUF_WRITE_EN_8814B(x) | BIT_PKTBUF_WRITE_EN_8814B(v))
+
+#define BIT_TXRPTBUF_DBG_8814B BIT(23)
+
+/* 2 REG_NOT_VALID_8814B */
+#define BIT_TXPKTBUF_DBG_V2_8814B BIT(20)
+#define BIT_RXPKTBUF_DBG_8814B BIT(16)
+
+#define BIT_SHIFT_PKTBUF_DBG_ADDR_8814B 0
+#define BIT_MASK_PKTBUF_DBG_ADDR_8814B 0x1fff
+#define BIT_PKTBUF_DBG_ADDR_8814B(x)                                           \
+	(((x) & BIT_MASK_PKTBUF_DBG_ADDR_8814B)                                \
+	 << BIT_SHIFT_PKTBUF_DBG_ADDR_8814B)
+#define BITS_PKTBUF_DBG_ADDR_8814B                                             \
+	(BIT_MASK_PKTBUF_DBG_ADDR_8814B << BIT_SHIFT_PKTBUF_DBG_ADDR_8814B)
+#define BIT_CLEAR_PKTBUF_DBG_ADDR_8814B(x) ((x) & (~BITS_PKTBUF_DBG_ADDR_8814B))
+#define BIT_GET_PKTBUF_DBG_ADDR_8814B(x)                                       \
+	(((x) >> BIT_SHIFT_PKTBUF_DBG_ADDR_8814B) &                            \
+	 BIT_MASK_PKTBUF_DBG_ADDR_8814B)
+#define BIT_SET_PKTBUF_DBG_ADDR_8814B(x, v)                                    \
+	(BIT_CLEAR_PKTBUF_DBG_ADDR_8814B(x) | BIT_PKTBUF_DBG_ADDR_8814B(v))
+
+/* 2 REG_PKTBUF_DBG_DATA_L_8814B */
+
+#define BIT_SHIFT_PKTBUF_DBG_DATA_L_8814B 0
+#define BIT_MASK_PKTBUF_DBG_DATA_L_8814B 0xffffffffL
+#define BIT_PKTBUF_DBG_DATA_L_8814B(x)                                         \
+	(((x) & BIT_MASK_PKTBUF_DBG_DATA_L_8814B)                              \
+	 << BIT_SHIFT_PKTBUF_DBG_DATA_L_8814B)
+#define BITS_PKTBUF_DBG_DATA_L_8814B                                           \
+	(BIT_MASK_PKTBUF_DBG_DATA_L_8814B << BIT_SHIFT_PKTBUF_DBG_DATA_L_8814B)
+#define BIT_CLEAR_PKTBUF_DBG_DATA_L_8814B(x)                                   \
+	((x) & (~BITS_PKTBUF_DBG_DATA_L_8814B))
+#define BIT_GET_PKTBUF_DBG_DATA_L_8814B(x)                                     \
+	(((x) >> BIT_SHIFT_PKTBUF_DBG_DATA_L_8814B) &                          \
+	 BIT_MASK_PKTBUF_DBG_DATA_L_8814B)
+#define BIT_SET_PKTBUF_DBG_DATA_L_8814B(x, v)                                  \
+	(BIT_CLEAR_PKTBUF_DBG_DATA_L_8814B(x) | BIT_PKTBUF_DBG_DATA_L_8814B(v))
+
+/* 2 REG_PKTBUF_DBG_DATA_H_8814B */
+
+#define BIT_SHIFT_PKTBUF_DBG_DATA_H_8814B 0
+#define BIT_MASK_PKTBUF_DBG_DATA_H_8814B 0xffffffffL
+#define BIT_PKTBUF_DBG_DATA_H_8814B(x)                                         \
+	(((x) & BIT_MASK_PKTBUF_DBG_DATA_H_8814B)                              \
+	 << BIT_SHIFT_PKTBUF_DBG_DATA_H_8814B)
+#define BITS_PKTBUF_DBG_DATA_H_8814B                                           \
+	(BIT_MASK_PKTBUF_DBG_DATA_H_8814B << BIT_SHIFT_PKTBUF_DBG_DATA_H_8814B)
+#define BIT_CLEAR_PKTBUF_DBG_DATA_H_8814B(x)                                   \
+	((x) & (~BITS_PKTBUF_DBG_DATA_H_8814B))
+#define BIT_GET_PKTBUF_DBG_DATA_H_8814B(x)                                     \
+	(((x) >> BIT_SHIFT_PKTBUF_DBG_DATA_H_8814B) &                          \
+	 BIT_MASK_PKTBUF_DBG_DATA_H_8814B)
+#define BIT_SET_PKTBUF_DBG_DATA_H_8814B(x, v)                                  \
+	(BIT_CLEAR_PKTBUF_DBG_DATA_H_8814B(x) | BIT_PKTBUF_DBG_DATA_H_8814B(v))
+
+/* 2 REG_CPWM2_8814B */
+
+#define BIT_SHIFT_L0S_TO_RCVY_NUM_8814B 16
+#define BIT_MASK_L0S_TO_RCVY_NUM_8814B 0xff
+#define BIT_L0S_TO_RCVY_NUM_8814B(x)                                           \
+	(((x) & BIT_MASK_L0S_TO_RCVY_NUM_8814B)                                \
+	 << BIT_SHIFT_L0S_TO_RCVY_NUM_8814B)
+#define BITS_L0S_TO_RCVY_NUM_8814B                                             \
+	(BIT_MASK_L0S_TO_RCVY_NUM_8814B << BIT_SHIFT_L0S_TO_RCVY_NUM_8814B)
+#define BIT_CLEAR_L0S_TO_RCVY_NUM_8814B(x) ((x) & (~BITS_L0S_TO_RCVY_NUM_8814B))
+#define BIT_GET_L0S_TO_RCVY_NUM_8814B(x)                                       \
+	(((x) >> BIT_SHIFT_L0S_TO_RCVY_NUM_8814B) &                            \
+	 BIT_MASK_L0S_TO_RCVY_NUM_8814B)
+#define BIT_SET_L0S_TO_RCVY_NUM_8814B(x, v)                                    \
+	(BIT_CLEAR_L0S_TO_RCVY_NUM_8814B(x) | BIT_L0S_TO_RCVY_NUM_8814B(v))
+
+#define BIT_CPWM2_TOGGLING_8814B BIT(15)
+
+#define BIT_SHIFT_CPWM2_MOD_8814B 0
+#define BIT_MASK_CPWM2_MOD_8814B 0x7fff
+#define BIT_CPWM2_MOD_8814B(x)                                                 \
+	(((x) & BIT_MASK_CPWM2_MOD_8814B) << BIT_SHIFT_CPWM2_MOD_8814B)
+#define BITS_CPWM2_MOD_8814B                                                   \
+	(BIT_MASK_CPWM2_MOD_8814B << BIT_SHIFT_CPWM2_MOD_8814B)
+#define BIT_CLEAR_CPWM2_MOD_8814B(x) ((x) & (~BITS_CPWM2_MOD_8814B))
+#define BIT_GET_CPWM2_MOD_8814B(x)                                             \
+	(((x) >> BIT_SHIFT_CPWM2_MOD_8814B) & BIT_MASK_CPWM2_MOD_8814B)
+#define BIT_SET_CPWM2_MOD_8814B(x, v)                                          \
+	(BIT_CLEAR_CPWM2_MOD_8814B(x) | BIT_CPWM2_MOD_8814B(v))
+
+/* 2 REG_TC0_CTRL_8814B */
+#define BIT_TC0INT_EN_8814B BIT(26)
+#define BIT_TC0MODE_8814B BIT(25)
+#define BIT_TC0EN_8814B BIT(24)
+
+#define BIT_SHIFT_TC0DATA_8814B 0
+#define BIT_MASK_TC0DATA_8814B 0xffffff
+#define BIT_TC0DATA_8814B(x)                                                   \
+	(((x) & BIT_MASK_TC0DATA_8814B) << BIT_SHIFT_TC0DATA_8814B)
+#define BITS_TC0DATA_8814B (BIT_MASK_TC0DATA_8814B << BIT_SHIFT_TC0DATA_8814B)
+#define BIT_CLEAR_TC0DATA_8814B(x) ((x) & (~BITS_TC0DATA_8814B))
+#define BIT_GET_TC0DATA_8814B(x)                                               \
+	(((x) >> BIT_SHIFT_TC0DATA_8814B) & BIT_MASK_TC0DATA_8814B)
+#define BIT_SET_TC0DATA_8814B(x, v)                                            \
+	(BIT_CLEAR_TC0DATA_8814B(x) | BIT_TC0DATA_8814B(v))
+
+/* 2 REG_TC1_CTRL_8814B */
+#define BIT_TC1INT_EN_8814B BIT(26)
+#define BIT_TC1MODE_8814B BIT(25)
+#define BIT_TC1EN_8814B BIT(24)
+
+#define BIT_SHIFT_TC1DATA_8814B 0
+#define BIT_MASK_TC1DATA_8814B 0xffffff
+#define BIT_TC1DATA_8814B(x)                                                   \
+	(((x) & BIT_MASK_TC1DATA_8814B) << BIT_SHIFT_TC1DATA_8814B)
+#define BITS_TC1DATA_8814B (BIT_MASK_TC1DATA_8814B << BIT_SHIFT_TC1DATA_8814B)
+#define BIT_CLEAR_TC1DATA_8814B(x) ((x) & (~BITS_TC1DATA_8814B))
+#define BIT_GET_TC1DATA_8814B(x)                                               \
+	(((x) >> BIT_SHIFT_TC1DATA_8814B) & BIT_MASK_TC1DATA_8814B)
+#define BIT_SET_TC1DATA_8814B(x, v)                                            \
+	(BIT_CLEAR_TC1DATA_8814B(x) | BIT_TC1DATA_8814B(v))
+
+/* 2 REG_TC2_CTRL_8814B */
+#define BIT_TC2INT_EN_8814B BIT(26)
+#define BIT_TC2MODE_8814B BIT(25)
+#define BIT_TC2EN_8814B BIT(24)
+
+#define BIT_SHIFT_TC2DATA_8814B 0
+#define BIT_MASK_TC2DATA_8814B 0xffffff
+#define BIT_TC2DATA_8814B(x)                                                   \
+	(((x) & BIT_MASK_TC2DATA_8814B) << BIT_SHIFT_TC2DATA_8814B)
+#define BITS_TC2DATA_8814B (BIT_MASK_TC2DATA_8814B << BIT_SHIFT_TC2DATA_8814B)
+#define BIT_CLEAR_TC2DATA_8814B(x) ((x) & (~BITS_TC2DATA_8814B))
+#define BIT_GET_TC2DATA_8814B(x)                                               \
+	(((x) >> BIT_SHIFT_TC2DATA_8814B) & BIT_MASK_TC2DATA_8814B)
+#define BIT_SET_TC2DATA_8814B(x, v)                                            \
+	(BIT_CLEAR_TC2DATA_8814B(x) | BIT_TC2DATA_8814B(v))
+
+/* 2 REG_TC3_CTRL_8814B */
+#define BIT_TC3INT_EN_8814B BIT(26)
+#define BIT_TC3MODE_8814B BIT(25)
+#define BIT_TC3EN_8814B BIT(24)
+
+#define BIT_SHIFT_TC3DATA_8814B 0
+#define BIT_MASK_TC3DATA_8814B 0xffffff
+#define BIT_TC3DATA_8814B(x)                                                   \
+	(((x) & BIT_MASK_TC3DATA_8814B) << BIT_SHIFT_TC3DATA_8814B)
+#define BITS_TC3DATA_8814B (BIT_MASK_TC3DATA_8814B << BIT_SHIFT_TC3DATA_8814B)
+#define BIT_CLEAR_TC3DATA_8814B(x) ((x) & (~BITS_TC3DATA_8814B))
+#define BIT_GET_TC3DATA_8814B(x)                                               \
+	(((x) >> BIT_SHIFT_TC3DATA_8814B) & BIT_MASK_TC3DATA_8814B)
+#define BIT_SET_TC3DATA_8814B(x, v)                                            \
+	(BIT_CLEAR_TC3DATA_8814B(x) | BIT_TC3DATA_8814B(v))
+
+/* 2 REG_TC4_CTRL_8814B */
+#define BIT_TC4INT_EN_8814B BIT(26)
+#define BIT_TC4MODE_8814B BIT(25)
+#define BIT_TC4EN_8814B BIT(24)
+
+#define BIT_SHIFT_TC4DATA_8814B 0
+#define BIT_MASK_TC4DATA_8814B 0xffffff
+#define BIT_TC4DATA_8814B(x)                                                   \
+	(((x) & BIT_MASK_TC4DATA_8814B) << BIT_SHIFT_TC4DATA_8814B)
+#define BITS_TC4DATA_8814B (BIT_MASK_TC4DATA_8814B << BIT_SHIFT_TC4DATA_8814B)
+#define BIT_CLEAR_TC4DATA_8814B(x) ((x) & (~BITS_TC4DATA_8814B))
+#define BIT_GET_TC4DATA_8814B(x)                                               \
+	(((x) >> BIT_SHIFT_TC4DATA_8814B) & BIT_MASK_TC4DATA_8814B)
+#define BIT_SET_TC4DATA_8814B(x, v)                                            \
+	(BIT_CLEAR_TC4DATA_8814B(x) | BIT_TC4DATA_8814B(v))
+
+/* 2 REG_TCUNIT_BASE_8814B */
+
+#define BIT_SHIFT_TCUNIT_BASE_8814B 0
+#define BIT_MASK_TCUNIT_BASE_8814B 0x3fff
+#define BIT_TCUNIT_BASE_8814B(x)                                               \
+	(((x) & BIT_MASK_TCUNIT_BASE_8814B) << BIT_SHIFT_TCUNIT_BASE_8814B)
+#define BITS_TCUNIT_BASE_8814B                                                 \
+	(BIT_MASK_TCUNIT_BASE_8814B << BIT_SHIFT_TCUNIT_BASE_8814B)
+#define BIT_CLEAR_TCUNIT_BASE_8814B(x) ((x) & (~BITS_TCUNIT_BASE_8814B))
+#define BIT_GET_TCUNIT_BASE_8814B(x)                                           \
+	(((x) >> BIT_SHIFT_TCUNIT_BASE_8814B) & BIT_MASK_TCUNIT_BASE_8814B)
+#define BIT_SET_TCUNIT_BASE_8814B(x, v)                                        \
+	(BIT_CLEAR_TCUNIT_BASE_8814B(x) | BIT_TCUNIT_BASE_8814B(v))
+
+/* 2 REG_TC5_CTRL_8814B */
+#define BIT_TC5INT_EN_8814B BIT(26)
+#define BIT_TC5MODE_8814B BIT(25)
+#define BIT_TC5EN_8814B BIT(24)
+
+#define BIT_SHIFT_TC5DATA_8814B 0
+#define BIT_MASK_TC5DATA_8814B 0xffffff
+#define BIT_TC5DATA_8814B(x)                                                   \
+	(((x) & BIT_MASK_TC5DATA_8814B) << BIT_SHIFT_TC5DATA_8814B)
+#define BITS_TC5DATA_8814B (BIT_MASK_TC5DATA_8814B << BIT_SHIFT_TC5DATA_8814B)
+#define BIT_CLEAR_TC5DATA_8814B(x) ((x) & (~BITS_TC5DATA_8814B))
+#define BIT_GET_TC5DATA_8814B(x)                                               \
+	(((x) >> BIT_SHIFT_TC5DATA_8814B) & BIT_MASK_TC5DATA_8814B)
+#define BIT_SET_TC5DATA_8814B(x, v)                                            \
+	(BIT_CLEAR_TC5DATA_8814B(x) | BIT_TC5DATA_8814B(v))
+
+/* 2 REG_TC6_CTRL_8814B */
+#define BIT_TC6INT_EN_8814B BIT(26)
+#define BIT_TC6MODE_8814B BIT(25)
+#define BIT_TC6EN_8814B BIT(24)
+
+#define BIT_SHIFT_TC6DATA_8814B 0
+#define BIT_MASK_TC6DATA_8814B 0xffffff
+#define BIT_TC6DATA_8814B(x)                                                   \
+	(((x) & BIT_MASK_TC6DATA_8814B) << BIT_SHIFT_TC6DATA_8814B)
+#define BITS_TC6DATA_8814B (BIT_MASK_TC6DATA_8814B << BIT_SHIFT_TC6DATA_8814B)
+#define BIT_CLEAR_TC6DATA_8814B(x) ((x) & (~BITS_TC6DATA_8814B))
+#define BIT_GET_TC6DATA_8814B(x)                                               \
+	(((x) >> BIT_SHIFT_TC6DATA_8814B) & BIT_MASK_TC6DATA_8814B)
+#define BIT_SET_TC6DATA_8814B(x, v)                                            \
+	(BIT_CLEAR_TC6DATA_8814B(x) | BIT_TC6DATA_8814B(v))
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_AES_DECRPT_DATA_8814B */
+
+#define BIT_SHIFT_IPS_CFG_ADDR_8814B 0
+#define BIT_MASK_IPS_CFG_ADDR_8814B 0xff
+#define BIT_IPS_CFG_ADDR_8814B(x)                                              \
+	(((x) & BIT_MASK_IPS_CFG_ADDR_8814B) << BIT_SHIFT_IPS_CFG_ADDR_8814B)
+#define BITS_IPS_CFG_ADDR_8814B                                                \
+	(BIT_MASK_IPS_CFG_ADDR_8814B << BIT_SHIFT_IPS_CFG_ADDR_8814B)
+#define BIT_CLEAR_IPS_CFG_ADDR_8814B(x) ((x) & (~BITS_IPS_CFG_ADDR_8814B))
+#define BIT_GET_IPS_CFG_ADDR_8814B(x)                                          \
+	(((x) >> BIT_SHIFT_IPS_CFG_ADDR_8814B) & BIT_MASK_IPS_CFG_ADDR_8814B)
+#define BIT_SET_IPS_CFG_ADDR_8814B(x, v)                                       \
+	(BIT_CLEAR_IPS_CFG_ADDR_8814B(x) | BIT_IPS_CFG_ADDR_8814B(v))
+
+/* 2 REG_AES_DECRPT_CFG_8814B */
+
+#define BIT_SHIFT_IPS_CFG_DATA_8814B 0
+#define BIT_MASK_IPS_CFG_DATA_8814B 0xffffffffL
+#define BIT_IPS_CFG_DATA_8814B(x)                                              \
+	(((x) & BIT_MASK_IPS_CFG_DATA_8814B) << BIT_SHIFT_IPS_CFG_DATA_8814B)
+#define BITS_IPS_CFG_DATA_8814B                                                \
+	(BIT_MASK_IPS_CFG_DATA_8814B << BIT_SHIFT_IPS_CFG_DATA_8814B)
+#define BIT_CLEAR_IPS_CFG_DATA_8814B(x) ((x) & (~BITS_IPS_CFG_DATA_8814B))
+#define BIT_GET_IPS_CFG_DATA_8814B(x)                                          \
+	(((x) >> BIT_SHIFT_IPS_CFG_DATA_8814B) & BIT_MASK_IPS_CFG_DATA_8814B)
+#define BIT_SET_IPS_CFG_DATA_8814B(x, v)                                       \
+	(BIT_CLEAR_IPS_CFG_DATA_8814B(x) | BIT_IPS_CFG_DATA_8814B(v))
+
+/* 2 REG_HIOE_CTRL_8814B */
+#define BIT_HIOE_WRITE_REQ_8814B BIT(30)
+#define BIT_HIOE_READ_REQ_8814B BIT(29)
+#define BIT_INST_FORMAT_ERR_8814B BIT(25)
+#define BIT_OP_TIMEOUT_ERR_8814B BIT(24)
+
+#define BIT_SHIFT_HIOE_OP_TIMEOUT_8814B 16
+#define BIT_MASK_HIOE_OP_TIMEOUT_8814B 0xff
+#define BIT_HIOE_OP_TIMEOUT_8814B(x)                                           \
+	(((x) & BIT_MASK_HIOE_OP_TIMEOUT_8814B)                                \
+	 << BIT_SHIFT_HIOE_OP_TIMEOUT_8814B)
+#define BITS_HIOE_OP_TIMEOUT_8814B                                             \
+	(BIT_MASK_HIOE_OP_TIMEOUT_8814B << BIT_SHIFT_HIOE_OP_TIMEOUT_8814B)
+#define BIT_CLEAR_HIOE_OP_TIMEOUT_8814B(x) ((x) & (~BITS_HIOE_OP_TIMEOUT_8814B))
+#define BIT_GET_HIOE_OP_TIMEOUT_8814B(x)                                       \
+	(((x) >> BIT_SHIFT_HIOE_OP_TIMEOUT_8814B) &                            \
+	 BIT_MASK_HIOE_OP_TIMEOUT_8814B)
+#define BIT_SET_HIOE_OP_TIMEOUT_8814B(x, v)                                    \
+	(BIT_CLEAR_HIOE_OP_TIMEOUT_8814B(x) | BIT_HIOE_OP_TIMEOUT_8814B(v))
+
+#define BIT_SHIFT_BITDATA_CHECKSUM_8814B 0
+#define BIT_MASK_BITDATA_CHECKSUM_8814B 0xffff
+#define BIT_BITDATA_CHECKSUM_8814B(x)                                          \
+	(((x) & BIT_MASK_BITDATA_CHECKSUM_8814B)                               \
+	 << BIT_SHIFT_BITDATA_CHECKSUM_8814B)
+#define BITS_BITDATA_CHECKSUM_8814B                                            \
+	(BIT_MASK_BITDATA_CHECKSUM_8814B << BIT_SHIFT_BITDATA_CHECKSUM_8814B)
+#define BIT_CLEAR_BITDATA_CHECKSUM_8814B(x)                                    \
+	((x) & (~BITS_BITDATA_CHECKSUM_8814B))
+#define BIT_GET_BITDATA_CHECKSUM_8814B(x)                                      \
+	(((x) >> BIT_SHIFT_BITDATA_CHECKSUM_8814B) &                           \
+	 BIT_MASK_BITDATA_CHECKSUM_8814B)
+#define BIT_SET_BITDATA_CHECKSUM_8814B(x, v)                                   \
+	(BIT_CLEAR_BITDATA_CHECKSUM_8814B(x) | BIT_BITDATA_CHECKSUM_8814B(v))
+
+/* 2 REG_HIOE_CFG_FILE_8814B */
+
+#define BIT_SHIFT_TXBF_END_ADDR_8814B 16
+#define BIT_MASK_TXBF_END_ADDR_8814B 0xffff
+#define BIT_TXBF_END_ADDR_8814B(x)                                             \
+	(((x) & BIT_MASK_TXBF_END_ADDR_8814B) << BIT_SHIFT_TXBF_END_ADDR_8814B)
+#define BITS_TXBF_END_ADDR_8814B                                               \
+	(BIT_MASK_TXBF_END_ADDR_8814B << BIT_SHIFT_TXBF_END_ADDR_8814B)
+#define BIT_CLEAR_TXBF_END_ADDR_8814B(x) ((x) & (~BITS_TXBF_END_ADDR_8814B))
+#define BIT_GET_TXBF_END_ADDR_8814B(x)                                         \
+	(((x) >> BIT_SHIFT_TXBF_END_ADDR_8814B) & BIT_MASK_TXBF_END_ADDR_8814B)
+#define BIT_SET_TXBF_END_ADDR_8814B(x, v)                                      \
+	(BIT_CLEAR_TXBF_END_ADDR_8814B(x) | BIT_TXBF_END_ADDR_8814B(v))
+
+#define BIT_SHIFT_TXBF_STR_ADDR_8814B 0
+#define BIT_MASK_TXBF_STR_ADDR_8814B 0xffff
+#define BIT_TXBF_STR_ADDR_8814B(x)                                             \
+	(((x) & BIT_MASK_TXBF_STR_ADDR_8814B) << BIT_SHIFT_TXBF_STR_ADDR_8814B)
+#define BITS_TXBF_STR_ADDR_8814B                                               \
+	(BIT_MASK_TXBF_STR_ADDR_8814B << BIT_SHIFT_TXBF_STR_ADDR_8814B)
+#define BIT_CLEAR_TXBF_STR_ADDR_8814B(x) ((x) & (~BITS_TXBF_STR_ADDR_8814B))
+#define BIT_GET_TXBF_STR_ADDR_8814B(x)                                         \
+	(((x) >> BIT_SHIFT_TXBF_STR_ADDR_8814B) & BIT_MASK_TXBF_STR_ADDR_8814B)
+#define BIT_SET_TXBF_STR_ADDR_8814B(x, v)                                      \
+	(BIT_CLEAR_TXBF_STR_ADDR_8814B(x) | BIT_TXBF_STR_ADDR_8814B(v))
+
+/* 2 REG_TMETER_8814B */
+#define BIT_TEMP_VALID_8814B BIT(31)
+
+#define BIT_SHIFT_TEMP_VALUE_8814B 24
+#define BIT_MASK_TEMP_VALUE_8814B 0x3f
+#define BIT_TEMP_VALUE_8814B(x)                                                \
+	(((x) & BIT_MASK_TEMP_VALUE_8814B) << BIT_SHIFT_TEMP_VALUE_8814B)
+#define BITS_TEMP_VALUE_8814B                                                  \
+	(BIT_MASK_TEMP_VALUE_8814B << BIT_SHIFT_TEMP_VALUE_8814B)
+#define BIT_CLEAR_TEMP_VALUE_8814B(x) ((x) & (~BITS_TEMP_VALUE_8814B))
+#define BIT_GET_TEMP_VALUE_8814B(x)                                            \
+	(((x) >> BIT_SHIFT_TEMP_VALUE_8814B) & BIT_MASK_TEMP_VALUE_8814B)
+#define BIT_SET_TEMP_VALUE_8814B(x, v)                                         \
+	(BIT_CLEAR_TEMP_VALUE_8814B(x) | BIT_TEMP_VALUE_8814B(v))
+
+#define BIT_SHIFT_REG_TMETER_TIMER_8814B 8
+#define BIT_MASK_REG_TMETER_TIMER_8814B 0xfff
+#define BIT_REG_TMETER_TIMER_8814B(x)                                          \
+	(((x) & BIT_MASK_REG_TMETER_TIMER_8814B)                               \
+	 << BIT_SHIFT_REG_TMETER_TIMER_8814B)
+#define BITS_REG_TMETER_TIMER_8814B                                            \
+	(BIT_MASK_REG_TMETER_TIMER_8814B << BIT_SHIFT_REG_TMETER_TIMER_8814B)
+#define BIT_CLEAR_REG_TMETER_TIMER_8814B(x)                                    \
+	((x) & (~BITS_REG_TMETER_TIMER_8814B))
+#define BIT_GET_REG_TMETER_TIMER_8814B(x)                                      \
+	(((x) >> BIT_SHIFT_REG_TMETER_TIMER_8814B) &                           \
+	 BIT_MASK_REG_TMETER_TIMER_8814B)
+#define BIT_SET_REG_TMETER_TIMER_8814B(x, v)                                   \
+	(BIT_CLEAR_REG_TMETER_TIMER_8814B(x) | BIT_REG_TMETER_TIMER_8814B(v))
+
+#define BIT_SHIFT_REG_TEMP_DELTA_8814B 2
+#define BIT_MASK_REG_TEMP_DELTA_8814B 0x3f
+#define BIT_REG_TEMP_DELTA_8814B(x)                                            \
+	(((x) & BIT_MASK_REG_TEMP_DELTA_8814B)                                 \
+	 << BIT_SHIFT_REG_TEMP_DELTA_8814B)
+#define BITS_REG_TEMP_DELTA_8814B                                              \
+	(BIT_MASK_REG_TEMP_DELTA_8814B << BIT_SHIFT_REG_TEMP_DELTA_8814B)
+#define BIT_CLEAR_REG_TEMP_DELTA_8814B(x) ((x) & (~BITS_REG_TEMP_DELTA_8814B))
+#define BIT_GET_REG_TEMP_DELTA_8814B(x)                                        \
+	(((x) >> BIT_SHIFT_REG_TEMP_DELTA_8814B) &                             \
+	 BIT_MASK_REG_TEMP_DELTA_8814B)
+#define BIT_SET_REG_TEMP_DELTA_8814B(x, v)                                     \
+	(BIT_CLEAR_REG_TEMP_DELTA_8814B(x) | BIT_REG_TEMP_DELTA_8814B(v))
+
+#define BIT_REG_TMETER_EN_8814B BIT(0)
+
+/* 2 REG_OSC_32K_CTRL_8814B */
+
+#define BIT_SHIFT_OSC_32K_CLKGEN_0_8814B 16
+#define BIT_MASK_OSC_32K_CLKGEN_0_8814B 0xffff
+#define BIT_OSC_32K_CLKGEN_0_8814B(x)                                          \
+	(((x) & BIT_MASK_OSC_32K_CLKGEN_0_8814B)                               \
+	 << BIT_SHIFT_OSC_32K_CLKGEN_0_8814B)
+#define BITS_OSC_32K_CLKGEN_0_8814B                                            \
+	(BIT_MASK_OSC_32K_CLKGEN_0_8814B << BIT_SHIFT_OSC_32K_CLKGEN_0_8814B)
+#define BIT_CLEAR_OSC_32K_CLKGEN_0_8814B(x)                                    \
+	((x) & (~BITS_OSC_32K_CLKGEN_0_8814B))
+#define BIT_GET_OSC_32K_CLKGEN_0_8814B(x)                                      \
+	(((x) >> BIT_SHIFT_OSC_32K_CLKGEN_0_8814B) &                           \
+	 BIT_MASK_OSC_32K_CLKGEN_0_8814B)
+#define BIT_SET_OSC_32K_CLKGEN_0_8814B(x, v)                                   \
+	(BIT_CLEAR_OSC_32K_CLKGEN_0_8814B(x) | BIT_OSC_32K_CLKGEN_0_8814B(v))
+
+#define BIT_SHIFT_OSC_32K_RES_COMP_8814B 4
+#define BIT_MASK_OSC_32K_RES_COMP_8814B 0x3
+#define BIT_OSC_32K_RES_COMP_8814B(x)                                          \
+	(((x) & BIT_MASK_OSC_32K_RES_COMP_8814B)                               \
+	 << BIT_SHIFT_OSC_32K_RES_COMP_8814B)
+#define BITS_OSC_32K_RES_COMP_8814B                                            \
+	(BIT_MASK_OSC_32K_RES_COMP_8814B << BIT_SHIFT_OSC_32K_RES_COMP_8814B)
+#define BIT_CLEAR_OSC_32K_RES_COMP_8814B(x)                                    \
+	((x) & (~BITS_OSC_32K_RES_COMP_8814B))
+#define BIT_GET_OSC_32K_RES_COMP_8814B(x)                                      \
+	(((x) >> BIT_SHIFT_OSC_32K_RES_COMP_8814B) &                           \
+	 BIT_MASK_OSC_32K_RES_COMP_8814B)
+#define BIT_SET_OSC_32K_RES_COMP_8814B(x, v)                                   \
+	(BIT_CLEAR_OSC_32K_RES_COMP_8814B(x) | BIT_OSC_32K_RES_COMP_8814B(v))
+
+#define BIT_OSC_32K_OUT_SEL_8814B BIT(3)
+#define BIT_ISO_WL_2_OSC_32K_8814B BIT(1)
+#define BIT_POW_CKGEN_8814B BIT(0)
+
+/* 2 REG_32K_CAL_REG1_8814B */
+#define BIT_CAL_32K_REG_WR_8814B BIT(31)
+#define BIT_CAL_32K_DBG_SEL_8814B BIT(22)
+
+#define BIT_SHIFT_CAL_32K_REG_ADDR_8814B 16
+#define BIT_MASK_CAL_32K_REG_ADDR_8814B 0x3f
+#define BIT_CAL_32K_REG_ADDR_8814B(x)                                          \
+	(((x) & BIT_MASK_CAL_32K_REG_ADDR_8814B)                               \
+	 << BIT_SHIFT_CAL_32K_REG_ADDR_8814B)
+#define BITS_CAL_32K_REG_ADDR_8814B                                            \
+	(BIT_MASK_CAL_32K_REG_ADDR_8814B << BIT_SHIFT_CAL_32K_REG_ADDR_8814B)
+#define BIT_CLEAR_CAL_32K_REG_ADDR_8814B(x)                                    \
+	((x) & (~BITS_CAL_32K_REG_ADDR_8814B))
+#define BIT_GET_CAL_32K_REG_ADDR_8814B(x)                                      \
+	(((x) >> BIT_SHIFT_CAL_32K_REG_ADDR_8814B) &                           \
+	 BIT_MASK_CAL_32K_REG_ADDR_8814B)
+#define BIT_SET_CAL_32K_REG_ADDR_8814B(x, v)                                   \
+	(BIT_CLEAR_CAL_32K_REG_ADDR_8814B(x) | BIT_CAL_32K_REG_ADDR_8814B(v))
+
+#define BIT_SHIFT_CAL_32K_REG_DATA_8814B 0
+#define BIT_MASK_CAL_32K_REG_DATA_8814B 0xffff
+#define BIT_CAL_32K_REG_DATA_8814B(x)                                          \
+	(((x) & BIT_MASK_CAL_32K_REG_DATA_8814B)                               \
+	 << BIT_SHIFT_CAL_32K_REG_DATA_8814B)
+#define BITS_CAL_32K_REG_DATA_8814B                                            \
+	(BIT_MASK_CAL_32K_REG_DATA_8814B << BIT_SHIFT_CAL_32K_REG_DATA_8814B)
+#define BIT_CLEAR_CAL_32K_REG_DATA_8814B(x)                                    \
+	((x) & (~BITS_CAL_32K_REG_DATA_8814B))
+#define BIT_GET_CAL_32K_REG_DATA_8814B(x)                                      \
+	(((x) >> BIT_SHIFT_CAL_32K_REG_DATA_8814B) &                           \
+	 BIT_MASK_CAL_32K_REG_DATA_8814B)
+#define BIT_SET_CAL_32K_REG_DATA_8814B(x, v)                                   \
+	(BIT_CLEAR_CAL_32K_REG_DATA_8814B(x) | BIT_CAL_32K_REG_DATA_8814B(v))
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_C2HEVT_8814B */
+
+#define BIT_SHIFT_C2HEVT_MSG_V1_8814B 0
+#define BIT_MASK_C2HEVT_MSG_V1_8814B 0xffffffffL
+#define BIT_C2HEVT_MSG_V1_8814B(x)                                             \
+	(((x) & BIT_MASK_C2HEVT_MSG_V1_8814B) << BIT_SHIFT_C2HEVT_MSG_V1_8814B)
+#define BITS_C2HEVT_MSG_V1_8814B                                               \
+	(BIT_MASK_C2HEVT_MSG_V1_8814B << BIT_SHIFT_C2HEVT_MSG_V1_8814B)
+#define BIT_CLEAR_C2HEVT_MSG_V1_8814B(x) ((x) & (~BITS_C2HEVT_MSG_V1_8814B))
+#define BIT_GET_C2HEVT_MSG_V1_8814B(x)                                         \
+	(((x) >> BIT_SHIFT_C2HEVT_MSG_V1_8814B) & BIT_MASK_C2HEVT_MSG_V1_8814B)
+#define BIT_SET_C2HEVT_MSG_V1_8814B(x, v)                                      \
+	(BIT_CLEAR_C2HEVT_MSG_V1_8814B(x) | BIT_C2HEVT_MSG_V1_8814B(v))
+
+/* 2 REG_C2HEVT_1_8814B */
+
+#define BIT_SHIFT_C2HEVT_MSG_1_8814B 0
+#define BIT_MASK_C2HEVT_MSG_1_8814B 0xffffffffL
+#define BIT_C2HEVT_MSG_1_8814B(x)                                              \
+	(((x) & BIT_MASK_C2HEVT_MSG_1_8814B) << BIT_SHIFT_C2HEVT_MSG_1_8814B)
+#define BITS_C2HEVT_MSG_1_8814B                                                \
+	(BIT_MASK_C2HEVT_MSG_1_8814B << BIT_SHIFT_C2HEVT_MSG_1_8814B)
+#define BIT_CLEAR_C2HEVT_MSG_1_8814B(x) ((x) & (~BITS_C2HEVT_MSG_1_8814B))
+#define BIT_GET_C2HEVT_MSG_1_8814B(x)                                          \
+	(((x) >> BIT_SHIFT_C2HEVT_MSG_1_8814B) & BIT_MASK_C2HEVT_MSG_1_8814B)
+#define BIT_SET_C2HEVT_MSG_1_8814B(x, v)                                       \
+	(BIT_CLEAR_C2HEVT_MSG_1_8814B(x) | BIT_C2HEVT_MSG_1_8814B(v))
+
+/* 2 REG_C2HEVT_2_8814B */
+
+#define BIT_SHIFT_C2HEVT_MSG_2_8814B 0
+#define BIT_MASK_C2HEVT_MSG_2_8814B 0xffffffffL
+#define BIT_C2HEVT_MSG_2_8814B(x)                                              \
+	(((x) & BIT_MASK_C2HEVT_MSG_2_8814B) << BIT_SHIFT_C2HEVT_MSG_2_8814B)
+#define BITS_C2HEVT_MSG_2_8814B                                                \
+	(BIT_MASK_C2HEVT_MSG_2_8814B << BIT_SHIFT_C2HEVT_MSG_2_8814B)
+#define BIT_CLEAR_C2HEVT_MSG_2_8814B(x) ((x) & (~BITS_C2HEVT_MSG_2_8814B))
+#define BIT_GET_C2HEVT_MSG_2_8814B(x)                                          \
+	(((x) >> BIT_SHIFT_C2HEVT_MSG_2_8814B) & BIT_MASK_C2HEVT_MSG_2_8814B)
+#define BIT_SET_C2HEVT_MSG_2_8814B(x, v)                                       \
+	(BIT_CLEAR_C2HEVT_MSG_2_8814B(x) | BIT_C2HEVT_MSG_2_8814B(v))
+
+/* 2 REG_C2HEVT_3_8814B */
+
+#define BIT_SHIFT_C2HEVT_MSG_3_8814B 0
+#define BIT_MASK_C2HEVT_MSG_3_8814B 0xffffffffL
+#define BIT_C2HEVT_MSG_3_8814B(x)                                              \
+	(((x) & BIT_MASK_C2HEVT_MSG_3_8814B) << BIT_SHIFT_C2HEVT_MSG_3_8814B)
+#define BITS_C2HEVT_MSG_3_8814B                                                \
+	(BIT_MASK_C2HEVT_MSG_3_8814B << BIT_SHIFT_C2HEVT_MSG_3_8814B)
+#define BIT_CLEAR_C2HEVT_MSG_3_8814B(x) ((x) & (~BITS_C2HEVT_MSG_3_8814B))
+#define BIT_GET_C2HEVT_MSG_3_8814B(x)                                          \
+	(((x) >> BIT_SHIFT_C2HEVT_MSG_3_8814B) & BIT_MASK_C2HEVT_MSG_3_8814B)
+#define BIT_SET_C2HEVT_MSG_3_8814B(x, v)                                       \
+	(BIT_CLEAR_C2HEVT_MSG_3_8814B(x) | BIT_C2HEVT_MSG_3_8814B(v))
+
+/* 2 REG_RXDESC_BUFF_RPTR_8814B */
+
+#define BIT_SHIFT_RXDESC_BUFF_RPTR_8814B 0
+#define BIT_MASK_RXDESC_BUFF_RPTR_8814B 0xffffffffL
+#define BIT_RXDESC_BUFF_RPTR_8814B(x)                                          \
+	(((x) & BIT_MASK_RXDESC_BUFF_RPTR_8814B)                               \
+	 << BIT_SHIFT_RXDESC_BUFF_RPTR_8814B)
+#define BITS_RXDESC_BUFF_RPTR_8814B                                            \
+	(BIT_MASK_RXDESC_BUFF_RPTR_8814B << BIT_SHIFT_RXDESC_BUFF_RPTR_8814B)
+#define BIT_CLEAR_RXDESC_BUFF_RPTR_8814B(x)                                    \
+	((x) & (~BITS_RXDESC_BUFF_RPTR_8814B))
+#define BIT_GET_RXDESC_BUFF_RPTR_8814B(x)                                      \
+	(((x) >> BIT_SHIFT_RXDESC_BUFF_RPTR_8814B) &                           \
+	 BIT_MASK_RXDESC_BUFF_RPTR_8814B)
+#define BIT_SET_RXDESC_BUFF_RPTR_8814B(x, v)                                   \
+	(BIT_CLEAR_RXDESC_BUFF_RPTR_8814B(x) | BIT_RXDESC_BUFF_RPTR_8814B(v))
+
+/* 2 REG_RXDESC_BUFF_WPTR_8814B */
+
+#define BIT_SHIFT_RXDESC_BUFF_WPTR_8814B 0
+#define BIT_MASK_RXDESC_BUFF_WPTR_8814B 0xffffffffL
+#define BIT_RXDESC_BUFF_WPTR_8814B(x)                                          \
+	(((x) & BIT_MASK_RXDESC_BUFF_WPTR_8814B)                               \
+	 << BIT_SHIFT_RXDESC_BUFF_WPTR_8814B)
+#define BITS_RXDESC_BUFF_WPTR_8814B                                            \
+	(BIT_MASK_RXDESC_BUFF_WPTR_8814B << BIT_SHIFT_RXDESC_BUFF_WPTR_8814B)
+#define BIT_CLEAR_RXDESC_BUFF_WPTR_8814B(x)                                    \
+	((x) & (~BITS_RXDESC_BUFF_WPTR_8814B))
+#define BIT_GET_RXDESC_BUFF_WPTR_8814B(x)                                      \
+	(((x) >> BIT_SHIFT_RXDESC_BUFF_WPTR_8814B) &                           \
+	 BIT_MASK_RXDESC_BUFF_WPTR_8814B)
+#define BIT_SET_RXDESC_BUFF_WPTR_8814B(x, v)                                   \
+	(BIT_CLEAR_RXDESC_BUFF_WPTR_8814B(x) | BIT_RXDESC_BUFF_WPTR_8814B(v))
+
+/* 2 REG_SW_DEFINED_PAGE1_8814B */
+
+#define BIT_SHIFT_SW_DEFINED_PAGE1_V1_8814B 0
+#define BIT_MASK_SW_DEFINED_PAGE1_V1_8814B 0xffffffffL
+#define BIT_SW_DEFINED_PAGE1_V1_8814B(x)                                       \
+	(((x) & BIT_MASK_SW_DEFINED_PAGE1_V1_8814B)                            \
+	 << BIT_SHIFT_SW_DEFINED_PAGE1_V1_8814B)
+#define BITS_SW_DEFINED_PAGE1_V1_8814B                                         \
+	(BIT_MASK_SW_DEFINED_PAGE1_V1_8814B                                    \
+	 << BIT_SHIFT_SW_DEFINED_PAGE1_V1_8814B)
+#define BIT_CLEAR_SW_DEFINED_PAGE1_V1_8814B(x)                                 \
+	((x) & (~BITS_SW_DEFINED_PAGE1_V1_8814B))
+#define BIT_GET_SW_DEFINED_PAGE1_V1_8814B(x)                                   \
+	(((x) >> BIT_SHIFT_SW_DEFINED_PAGE1_V1_8814B) &                        \
+	 BIT_MASK_SW_DEFINED_PAGE1_V1_8814B)
+#define BIT_SET_SW_DEFINED_PAGE1_V1_8814B(x, v)                                \
+	(BIT_CLEAR_SW_DEFINED_PAGE1_V1_8814B(x) |                              \
+	 BIT_SW_DEFINED_PAGE1_V1_8814B(v))
+
+/* 2 REG_SW_DEFINED_PAGE2_8814B */
+
+#define BIT_SHIFT_SW_DEFINED_PAGE2_8814B 0
+#define BIT_MASK_SW_DEFINED_PAGE2_8814B 0xffffffffL
+#define BIT_SW_DEFINED_PAGE2_8814B(x)                                          \
+	(((x) & BIT_MASK_SW_DEFINED_PAGE2_8814B)                               \
+	 << BIT_SHIFT_SW_DEFINED_PAGE2_8814B)
+#define BITS_SW_DEFINED_PAGE2_8814B                                            \
+	(BIT_MASK_SW_DEFINED_PAGE2_8814B << BIT_SHIFT_SW_DEFINED_PAGE2_8814B)
+#define BIT_CLEAR_SW_DEFINED_PAGE2_8814B(x)                                    \
+	((x) & (~BITS_SW_DEFINED_PAGE2_8814B))
+#define BIT_GET_SW_DEFINED_PAGE2_8814B(x)                                      \
+	(((x) >> BIT_SHIFT_SW_DEFINED_PAGE2_8814B) &                           \
+	 BIT_MASK_SW_DEFINED_PAGE2_8814B)
+#define BIT_SET_SW_DEFINED_PAGE2_8814B(x, v)                                   \
+	(BIT_CLEAR_SW_DEFINED_PAGE2_8814B(x) | BIT_SW_DEFINED_PAGE2_8814B(v))
+
+/* 2 REG_MCUTST_I_8814B */
+
+#define BIT_SHIFT_MCUDMSG_I_8814B 0
+#define BIT_MASK_MCUDMSG_I_8814B 0xffffffffL
+#define BIT_MCUDMSG_I_8814B(x)                                                 \
+	(((x) & BIT_MASK_MCUDMSG_I_8814B) << BIT_SHIFT_MCUDMSG_I_8814B)
+#define BITS_MCUDMSG_I_8814B                                                   \
+	(BIT_MASK_MCUDMSG_I_8814B << BIT_SHIFT_MCUDMSG_I_8814B)
+#define BIT_CLEAR_MCUDMSG_I_8814B(x) ((x) & (~BITS_MCUDMSG_I_8814B))
+#define BIT_GET_MCUDMSG_I_8814B(x)                                             \
+	(((x) >> BIT_SHIFT_MCUDMSG_I_8814B) & BIT_MASK_MCUDMSG_I_8814B)
+#define BIT_SET_MCUDMSG_I_8814B(x, v)                                          \
+	(BIT_CLEAR_MCUDMSG_I_8814B(x) | BIT_MCUDMSG_I_8814B(v))
+
+/* 2 REG_MCUTST_II_8814B */
+
+#define BIT_SHIFT_MCUDMSG_II_8814B 0
+#define BIT_MASK_MCUDMSG_II_8814B 0xffffffffL
+#define BIT_MCUDMSG_II_8814B(x)                                                \
+	(((x) & BIT_MASK_MCUDMSG_II_8814B) << BIT_SHIFT_MCUDMSG_II_8814B)
+#define BITS_MCUDMSG_II_8814B                                                  \
+	(BIT_MASK_MCUDMSG_II_8814B << BIT_SHIFT_MCUDMSG_II_8814B)
+#define BIT_CLEAR_MCUDMSG_II_8814B(x) ((x) & (~BITS_MCUDMSG_II_8814B))
+#define BIT_GET_MCUDMSG_II_8814B(x)                                            \
+	(((x) >> BIT_SHIFT_MCUDMSG_II_8814B) & BIT_MASK_MCUDMSG_II_8814B)
+#define BIT_SET_MCUDMSG_II_8814B(x, v)                                         \
+	(BIT_CLEAR_MCUDMSG_II_8814B(x) | BIT_MCUDMSG_II_8814B(v))
+
+/* 2 REG_FMETHR_8814B */
+#define BIT_FMSG_INT_8814B BIT(31)
+
+#define BIT_SHIFT_FW_MSG_8814B 0
+#define BIT_MASK_FW_MSG_8814B 0xffffffffL
+#define BIT_FW_MSG_8814B(x)                                                    \
+	(((x) & BIT_MASK_FW_MSG_8814B) << BIT_SHIFT_FW_MSG_8814B)
+#define BITS_FW_MSG_8814B (BIT_MASK_FW_MSG_8814B << BIT_SHIFT_FW_MSG_8814B)
+#define BIT_CLEAR_FW_MSG_8814B(x) ((x) & (~BITS_FW_MSG_8814B))
+#define BIT_GET_FW_MSG_8814B(x)                                                \
+	(((x) >> BIT_SHIFT_FW_MSG_8814B) & BIT_MASK_FW_MSG_8814B)
+#define BIT_SET_FW_MSG_8814B(x, v)                                             \
+	(BIT_CLEAR_FW_MSG_8814B(x) | BIT_FW_MSG_8814B(v))
+
+/* 2 REG_HMETFR_8814B */
+
+#define BIT_SHIFT_HRCV_MSG_8814B 24
+#define BIT_MASK_HRCV_MSG_8814B 0xff
+#define BIT_HRCV_MSG_8814B(x)                                                  \
+	(((x) & BIT_MASK_HRCV_MSG_8814B) << BIT_SHIFT_HRCV_MSG_8814B)
+#define BITS_HRCV_MSG_8814B                                                    \
+	(BIT_MASK_HRCV_MSG_8814B << BIT_SHIFT_HRCV_MSG_8814B)
+#define BIT_CLEAR_HRCV_MSG_8814B(x) ((x) & (~BITS_HRCV_MSG_8814B))
+#define BIT_GET_HRCV_MSG_8814B(x)                                              \
+	(((x) >> BIT_SHIFT_HRCV_MSG_8814B) & BIT_MASK_HRCV_MSG_8814B)
+#define BIT_SET_HRCV_MSG_8814B(x, v)                                           \
+	(BIT_CLEAR_HRCV_MSG_8814B(x) | BIT_HRCV_MSG_8814B(v))
+
+#define BIT_INT_BOX3_8814B BIT(3)
+#define BIT_INT_BOX2_8814B BIT(2)
+#define BIT_INT_BOX1_8814B BIT(1)
+#define BIT_INT_BOX0_8814B BIT(0)
+
+/* 2 REG_HMEBOX0_8814B */
+
+#define BIT_SHIFT_HOST_MSG_0_8814B 0
+#define BIT_MASK_HOST_MSG_0_8814B 0xffffffffL
+#define BIT_HOST_MSG_0_8814B(x)                                                \
+	(((x) & BIT_MASK_HOST_MSG_0_8814B) << BIT_SHIFT_HOST_MSG_0_8814B)
+#define BITS_HOST_MSG_0_8814B                                                  \
+	(BIT_MASK_HOST_MSG_0_8814B << BIT_SHIFT_HOST_MSG_0_8814B)
+#define BIT_CLEAR_HOST_MSG_0_8814B(x) ((x) & (~BITS_HOST_MSG_0_8814B))
+#define BIT_GET_HOST_MSG_0_8814B(x)                                            \
+	(((x) >> BIT_SHIFT_HOST_MSG_0_8814B) & BIT_MASK_HOST_MSG_0_8814B)
+#define BIT_SET_HOST_MSG_0_8814B(x, v)                                         \
+	(BIT_CLEAR_HOST_MSG_0_8814B(x) | BIT_HOST_MSG_0_8814B(v))
+
+/* 2 REG_HMEBOX1_8814B */
+
+#define BIT_SHIFT_HOST_MSG_1_8814B 0
+#define BIT_MASK_HOST_MSG_1_8814B 0xffffffffL
+#define BIT_HOST_MSG_1_8814B(x)                                                \
+	(((x) & BIT_MASK_HOST_MSG_1_8814B) << BIT_SHIFT_HOST_MSG_1_8814B)
+#define BITS_HOST_MSG_1_8814B                                                  \
+	(BIT_MASK_HOST_MSG_1_8814B << BIT_SHIFT_HOST_MSG_1_8814B)
+#define BIT_CLEAR_HOST_MSG_1_8814B(x) ((x) & (~BITS_HOST_MSG_1_8814B))
+#define BIT_GET_HOST_MSG_1_8814B(x)                                            \
+	(((x) >> BIT_SHIFT_HOST_MSG_1_8814B) & BIT_MASK_HOST_MSG_1_8814B)
+#define BIT_SET_HOST_MSG_1_8814B(x, v)                                         \
+	(BIT_CLEAR_HOST_MSG_1_8814B(x) | BIT_HOST_MSG_1_8814B(v))
+
+/* 2 REG_HMEBOX2_8814B */
+
+#define BIT_SHIFT_HOST_MSG_2_8814B 0
+#define BIT_MASK_HOST_MSG_2_8814B 0xffffffffL
+#define BIT_HOST_MSG_2_8814B(x)                                                \
+	(((x) & BIT_MASK_HOST_MSG_2_8814B) << BIT_SHIFT_HOST_MSG_2_8814B)
+#define BITS_HOST_MSG_2_8814B                                                  \
+	(BIT_MASK_HOST_MSG_2_8814B << BIT_SHIFT_HOST_MSG_2_8814B)
+#define BIT_CLEAR_HOST_MSG_2_8814B(x) ((x) & (~BITS_HOST_MSG_2_8814B))
+#define BIT_GET_HOST_MSG_2_8814B(x)                                            \
+	(((x) >> BIT_SHIFT_HOST_MSG_2_8814B) & BIT_MASK_HOST_MSG_2_8814B)
+#define BIT_SET_HOST_MSG_2_8814B(x, v)                                         \
+	(BIT_CLEAR_HOST_MSG_2_8814B(x) | BIT_HOST_MSG_2_8814B(v))
+
+/* 2 REG_HMEBOX3_8814B */
+
+#define BIT_SHIFT_HOST_MSG_3_8814B 0
+#define BIT_MASK_HOST_MSG_3_8814B 0xffffffffL
+#define BIT_HOST_MSG_3_8814B(x)                                                \
+	(((x) & BIT_MASK_HOST_MSG_3_8814B) << BIT_SHIFT_HOST_MSG_3_8814B)
+#define BITS_HOST_MSG_3_8814B                                                  \
+	(BIT_MASK_HOST_MSG_3_8814B << BIT_SHIFT_HOST_MSG_3_8814B)
+#define BIT_CLEAR_HOST_MSG_3_8814B(x) ((x) & (~BITS_HOST_MSG_3_8814B))
+#define BIT_GET_HOST_MSG_3_8814B(x)                                            \
+	(((x) >> BIT_SHIFT_HOST_MSG_3_8814B) & BIT_MASK_HOST_MSG_3_8814B)
+#define BIT_SET_HOST_MSG_3_8814B(x, v)                                         \
+	(BIT_CLEAR_HOST_MSG_3_8814B(x) | BIT_HOST_MSG_3_8814B(v))
+
+/* 2 REG_RXDESC_BUFF_BNDY_8814B */
+
+#define BIT_SHIFT_RXDESC_BUFF_BNDY_8814B 0
+#define BIT_MASK_RXDESC_BUFF_BNDY_8814B 0xffffffffL
+#define BIT_RXDESC_BUFF_BNDY_8814B(x)                                          \
+	(((x) & BIT_MASK_RXDESC_BUFF_BNDY_8814B)                               \
+	 << BIT_SHIFT_RXDESC_BUFF_BNDY_8814B)
+#define BITS_RXDESC_BUFF_BNDY_8814B                                            \
+	(BIT_MASK_RXDESC_BUFF_BNDY_8814B << BIT_SHIFT_RXDESC_BUFF_BNDY_8814B)
+#define BIT_CLEAR_RXDESC_BUFF_BNDY_8814B(x)                                    \
+	((x) & (~BITS_RXDESC_BUFF_BNDY_8814B))
+#define BIT_GET_RXDESC_BUFF_BNDY_8814B(x)                                      \
+	(((x) >> BIT_SHIFT_RXDESC_BUFF_BNDY_8814B) &                           \
+	 BIT_MASK_RXDESC_BUFF_BNDY_8814B)
+#define BIT_SET_RXDESC_BUFF_BNDY_8814B(x, v)                                   \
+	(BIT_CLEAR_RXDESC_BUFF_BNDY_8814B(x) | BIT_RXDESC_BUFF_BNDY_8814B(v))
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_BB_ACCESS_CTRL_8814B */
+
+#define BIT_SHIFT_BB_WRITE_READ_8814B 30
+#define BIT_MASK_BB_WRITE_READ_8814B 0x3
+#define BIT_BB_WRITE_READ_8814B(x)                                             \
+	(((x) & BIT_MASK_BB_WRITE_READ_8814B) << BIT_SHIFT_BB_WRITE_READ_8814B)
+#define BITS_BB_WRITE_READ_8814B                                               \
+	(BIT_MASK_BB_WRITE_READ_8814B << BIT_SHIFT_BB_WRITE_READ_8814B)
+#define BIT_CLEAR_BB_WRITE_READ_8814B(x) ((x) & (~BITS_BB_WRITE_READ_8814B))
+#define BIT_GET_BB_WRITE_READ_8814B(x)                                         \
+	(((x) >> BIT_SHIFT_BB_WRITE_READ_8814B) & BIT_MASK_BB_WRITE_READ_8814B)
+#define BIT_SET_BB_WRITE_READ_8814B(x, v)                                      \
+	(BIT_CLEAR_BB_WRITE_READ_8814B(x) | BIT_BB_WRITE_READ_8814B(v))
+
+#define BIT_SHIFT_BB_WRITE_EN_8814B 12
+#define BIT_MASK_BB_WRITE_EN_8814B 0xf
+#define BIT_BB_WRITE_EN_8814B(x)                                               \
+	(((x) & BIT_MASK_BB_WRITE_EN_8814B) << BIT_SHIFT_BB_WRITE_EN_8814B)
+#define BITS_BB_WRITE_EN_8814B                                                 \
+	(BIT_MASK_BB_WRITE_EN_8814B << BIT_SHIFT_BB_WRITE_EN_8814B)
+#define BIT_CLEAR_BB_WRITE_EN_8814B(x) ((x) & (~BITS_BB_WRITE_EN_8814B))
+#define BIT_GET_BB_WRITE_EN_8814B(x)                                           \
+	(((x) >> BIT_SHIFT_BB_WRITE_EN_8814B) & BIT_MASK_BB_WRITE_EN_8814B)
+#define BIT_SET_BB_WRITE_EN_8814B(x, v)                                        \
+	(BIT_CLEAR_BB_WRITE_EN_8814B(x) | BIT_BB_WRITE_EN_8814B(v))
+
+#define BIT_SHIFT_BB_ADDR_8814B 2
+#define BIT_MASK_BB_ADDR_8814B 0x1ff
+#define BIT_BB_ADDR_8814B(x)                                                   \
+	(((x) & BIT_MASK_BB_ADDR_8814B) << BIT_SHIFT_BB_ADDR_8814B)
+#define BITS_BB_ADDR_8814B (BIT_MASK_BB_ADDR_8814B << BIT_SHIFT_BB_ADDR_8814B)
+#define BIT_CLEAR_BB_ADDR_8814B(x) ((x) & (~BITS_BB_ADDR_8814B))
+#define BIT_GET_BB_ADDR_8814B(x)                                               \
+	(((x) >> BIT_SHIFT_BB_ADDR_8814B) & BIT_MASK_BB_ADDR_8814B)
+#define BIT_SET_BB_ADDR_8814B(x, v)                                            \
+	(BIT_CLEAR_BB_ADDR_8814B(x) | BIT_BB_ADDR_8814B(v))
+
+#define BIT_BB_ERRACC_8814B BIT(0)
+
+/* 2 REG_BB_ACCESS_DATA_8814B */
+
+#define BIT_SHIFT_BB_DATA_8814B 0
+#define BIT_MASK_BB_DATA_8814B 0xffffffffL
+#define BIT_BB_DATA_8814B(x)                                                   \
+	(((x) & BIT_MASK_BB_DATA_8814B) << BIT_SHIFT_BB_DATA_8814B)
+#define BITS_BB_DATA_8814B (BIT_MASK_BB_DATA_8814B << BIT_SHIFT_BB_DATA_8814B)
+#define BIT_CLEAR_BB_DATA_8814B(x) ((x) & (~BITS_BB_DATA_8814B))
+#define BIT_GET_BB_DATA_8814B(x)                                               \
+	(((x) >> BIT_SHIFT_BB_DATA_8814B) & BIT_MASK_BB_DATA_8814B)
+#define BIT_SET_BB_DATA_8814B(x, v)                                            \
+	(BIT_CLEAR_BB_DATA_8814B(x) | BIT_BB_DATA_8814B(v))
+
+/* 2 REG_HMEBOX_E0_8814B */
+
+#define BIT_SHIFT_HMEBOX_E0_8814B 0
+#define BIT_MASK_HMEBOX_E0_8814B 0xffffffffL
+#define BIT_HMEBOX_E0_8814B(x)                                                 \
+	(((x) & BIT_MASK_HMEBOX_E0_8814B) << BIT_SHIFT_HMEBOX_E0_8814B)
+#define BITS_HMEBOX_E0_8814B                                                   \
+	(BIT_MASK_HMEBOX_E0_8814B << BIT_SHIFT_HMEBOX_E0_8814B)
+#define BIT_CLEAR_HMEBOX_E0_8814B(x) ((x) & (~BITS_HMEBOX_E0_8814B))
+#define BIT_GET_HMEBOX_E0_8814B(x)                                             \
+	(((x) >> BIT_SHIFT_HMEBOX_E0_8814B) & BIT_MASK_HMEBOX_E0_8814B)
+#define BIT_SET_HMEBOX_E0_8814B(x, v)                                          \
+	(BIT_CLEAR_HMEBOX_E0_8814B(x) | BIT_HMEBOX_E0_8814B(v))
+
+/* 2 REG_HMEBOX_E1_8814B */
+
+#define BIT_SHIFT_HMEBOX_E1_8814B 0
+#define BIT_MASK_HMEBOX_E1_8814B 0xffffffffL
+#define BIT_HMEBOX_E1_8814B(x)                                                 \
+	(((x) & BIT_MASK_HMEBOX_E1_8814B) << BIT_SHIFT_HMEBOX_E1_8814B)
+#define BITS_HMEBOX_E1_8814B                                                   \
+	(BIT_MASK_HMEBOX_E1_8814B << BIT_SHIFT_HMEBOX_E1_8814B)
+#define BIT_CLEAR_HMEBOX_E1_8814B(x) ((x) & (~BITS_HMEBOX_E1_8814B))
+#define BIT_GET_HMEBOX_E1_8814B(x)                                             \
+	(((x) >> BIT_SHIFT_HMEBOX_E1_8814B) & BIT_MASK_HMEBOX_E1_8814B)
+#define BIT_SET_HMEBOX_E1_8814B(x, v)                                          \
+	(BIT_CLEAR_HMEBOX_E1_8814B(x) | BIT_HMEBOX_E1_8814B(v))
+
+/* 2 REG_HMEBOX_E2_8814B */
+
+#define BIT_SHIFT_HMEBOX_E2_8814B 0
+#define BIT_MASK_HMEBOX_E2_8814B 0xffffffffL
+#define BIT_HMEBOX_E2_8814B(x)                                                 \
+	(((x) & BIT_MASK_HMEBOX_E2_8814B) << BIT_SHIFT_HMEBOX_E2_8814B)
+#define BITS_HMEBOX_E2_8814B                                                   \
+	(BIT_MASK_HMEBOX_E2_8814B << BIT_SHIFT_HMEBOX_E2_8814B)
+#define BIT_CLEAR_HMEBOX_E2_8814B(x) ((x) & (~BITS_HMEBOX_E2_8814B))
+#define BIT_GET_HMEBOX_E2_8814B(x)                                             \
+	(((x) >> BIT_SHIFT_HMEBOX_E2_8814B) & BIT_MASK_HMEBOX_E2_8814B)
+#define BIT_SET_HMEBOX_E2_8814B(x, v)                                          \
+	(BIT_CLEAR_HMEBOX_E2_8814B(x) | BIT_HMEBOX_E2_8814B(v))
+
+/* 2 REG_HMEBOX_E3_8814B */
+
+#define BIT_SHIFT_HMEBOX_E3_8814B 0
+#define BIT_MASK_HMEBOX_E3_8814B 0xffffffffL
+#define BIT_HMEBOX_E3_8814B(x)                                                 \
+	(((x) & BIT_MASK_HMEBOX_E3_8814B) << BIT_SHIFT_HMEBOX_E3_8814B)
+#define BITS_HMEBOX_E3_8814B                                                   \
+	(BIT_MASK_HMEBOX_E3_8814B << BIT_SHIFT_HMEBOX_E3_8814B)
+#define BIT_CLEAR_HMEBOX_E3_8814B(x) ((x) & (~BITS_HMEBOX_E3_8814B))
+#define BIT_GET_HMEBOX_E3_8814B(x)                                             \
+	(((x) >> BIT_SHIFT_HMEBOX_E3_8814B) & BIT_MASK_HMEBOX_E3_8814B)
+#define BIT_SET_HMEBOX_E3_8814B(x, v)                                          \
+	(BIT_CLEAR_HMEBOX_E3_8814B(x) | BIT_HMEBOX_E3_8814B(v))
+
+/* 2 REG_CR_EXT_8814B */
+
+#define BIT_SHIFT_PHY_REQ_DELAY_8814B 24
+#define BIT_MASK_PHY_REQ_DELAY_8814B 0xf
+#define BIT_PHY_REQ_DELAY_8814B(x)                                             \
+	(((x) & BIT_MASK_PHY_REQ_DELAY_8814B) << BIT_SHIFT_PHY_REQ_DELAY_8814B)
+#define BITS_PHY_REQ_DELAY_8814B                                               \
+	(BIT_MASK_PHY_REQ_DELAY_8814B << BIT_SHIFT_PHY_REQ_DELAY_8814B)
+#define BIT_CLEAR_PHY_REQ_DELAY_8814B(x) ((x) & (~BITS_PHY_REQ_DELAY_8814B))
+#define BIT_GET_PHY_REQ_DELAY_8814B(x)                                         \
+	(((x) >> BIT_SHIFT_PHY_REQ_DELAY_8814B) & BIT_MASK_PHY_REQ_DELAY_8814B)
+#define BIT_SET_PHY_REQ_DELAY_8814B(x, v)                                      \
+	(BIT_CLEAR_PHY_REQ_DELAY_8814B(x) | BIT_PHY_REQ_DELAY_8814B(v))
+
+/* 2 REG_NOT_VALID_8814B */
+#define BIT_FW_FIFO_PTR_RST_8814B BIT(18)
+#define BIT_PHY_FIFO_PTR_RST_8814B BIT(17)
+#define BIT_SPD_DOWN_8814B BIT(16)
+
+/* 2 REG_NOT_VALID_8814B */
+
+#define BIT_SHIFT_NETYPE4_8814B 4
+#define BIT_MASK_NETYPE4_8814B 0x3
+#define BIT_NETYPE4_8814B(x)                                                   \
+	(((x) & BIT_MASK_NETYPE4_8814B) << BIT_SHIFT_NETYPE4_8814B)
+#define BITS_NETYPE4_8814B (BIT_MASK_NETYPE4_8814B << BIT_SHIFT_NETYPE4_8814B)
+#define BIT_CLEAR_NETYPE4_8814B(x) ((x) & (~BITS_NETYPE4_8814B))
+#define BIT_GET_NETYPE4_8814B(x)                                               \
+	(((x) >> BIT_SHIFT_NETYPE4_8814B) & BIT_MASK_NETYPE4_8814B)
+#define BIT_SET_NETYPE4_8814B(x, v)                                            \
+	(BIT_CLEAR_NETYPE4_8814B(x) | BIT_NETYPE4_8814B(v))
+
+#define BIT_SHIFT_NETYPE3_8814B 2
+#define BIT_MASK_NETYPE3_8814B 0x3
+#define BIT_NETYPE3_8814B(x)                                                   \
+	(((x) & BIT_MASK_NETYPE3_8814B) << BIT_SHIFT_NETYPE3_8814B)
+#define BITS_NETYPE3_8814B (BIT_MASK_NETYPE3_8814B << BIT_SHIFT_NETYPE3_8814B)
+#define BIT_CLEAR_NETYPE3_8814B(x) ((x) & (~BITS_NETYPE3_8814B))
+#define BIT_GET_NETYPE3_8814B(x)                                               \
+	(((x) >> BIT_SHIFT_NETYPE3_8814B) & BIT_MASK_NETYPE3_8814B)
+#define BIT_SET_NETYPE3_8814B(x, v)                                            \
+	(BIT_CLEAR_NETYPE3_8814B(x) | BIT_NETYPE3_8814B(v))
+
+#define BIT_SHIFT_NETYPE2_8814B 0
+#define BIT_MASK_NETYPE2_8814B 0x3
+#define BIT_NETYPE2_8814B(x)                                                   \
+	(((x) & BIT_MASK_NETYPE2_8814B) << BIT_SHIFT_NETYPE2_8814B)
+#define BITS_NETYPE2_8814B (BIT_MASK_NETYPE2_8814B << BIT_SHIFT_NETYPE2_8814B)
+#define BIT_CLEAR_NETYPE2_8814B(x) ((x) & (~BITS_NETYPE2_8814B))
+#define BIT_GET_NETYPE2_8814B(x)                                               \
+	(((x) >> BIT_SHIFT_NETYPE2_8814B) & BIT_MASK_NETYPE2_8814B)
+#define BIT_SET_NETYPE2_8814B(x, v)                                            \
+	(BIT_CLEAR_NETYPE2_8814B(x) | BIT_NETYPE2_8814B(v))
+
+/* 2 REG_TC9_CTRL_8814B */
+#define BIT_TC9INT_EN_8814B BIT(26)
+#define BIT_TC9MODE_8814B BIT(25)
+#define BIT_TC9EN_8814B BIT(24)
+
+#define BIT_SHIFT_TC9DATA_8814B 0
+#define BIT_MASK_TC9DATA_8814B 0xffffff
+#define BIT_TC9DATA_8814B(x)                                                   \
+	(((x) & BIT_MASK_TC9DATA_8814B) << BIT_SHIFT_TC9DATA_8814B)
+#define BITS_TC9DATA_8814B (BIT_MASK_TC9DATA_8814B << BIT_SHIFT_TC9DATA_8814B)
+#define BIT_CLEAR_TC9DATA_8814B(x) ((x) & (~BITS_TC9DATA_8814B))
+#define BIT_GET_TC9DATA_8814B(x)                                               \
+	(((x) >> BIT_SHIFT_TC9DATA_8814B) & BIT_MASK_TC9DATA_8814B)
+#define BIT_SET_TC9DATA_8814B(x, v)                                            \
+	(BIT_CLEAR_TC9DATA_8814B(x) | BIT_TC9DATA_8814B(v))
+
+/* 2 REG_TC10_CTRL_8814B */
+#define BIT_TC10INT_EN_8814B BIT(26)
+#define BIT_TC10MODE_8814B BIT(25)
+#define BIT_TC10EN_8814B BIT(24)
+
+#define BIT_SHIFT_TC10DATA_8814B 0
+#define BIT_MASK_TC10DATA_8814B 0xffffff
+#define BIT_TC10DATA_8814B(x)                                                  \
+	(((x) & BIT_MASK_TC10DATA_8814B) << BIT_SHIFT_TC10DATA_8814B)
+#define BITS_TC10DATA_8814B                                                    \
+	(BIT_MASK_TC10DATA_8814B << BIT_SHIFT_TC10DATA_8814B)
+#define BIT_CLEAR_TC10DATA_8814B(x) ((x) & (~BITS_TC10DATA_8814B))
+#define BIT_GET_TC10DATA_8814B(x)                                              \
+	(((x) >> BIT_SHIFT_TC10DATA_8814B) & BIT_MASK_TC10DATA_8814B)
+#define BIT_SET_TC10DATA_8814B(x, v)                                           \
+	(BIT_CLEAR_TC10DATA_8814B(x) | BIT_TC10DATA_8814B(v))
+
+/* 2 REG_TC11_CTRL_8814B */
+#define BIT_TC11INT_EN_8814B BIT(26)
+#define BIT_TC11MODE_8814B BIT(25)
+#define BIT_TC11EN_8814B BIT(24)
+
+#define BIT_SHIFT_TC11DATA_8814B 0
+#define BIT_MASK_TC11DATA_8814B 0xffffff
+#define BIT_TC11DATA_8814B(x)                                                  \
+	(((x) & BIT_MASK_TC11DATA_8814B) << BIT_SHIFT_TC11DATA_8814B)
+#define BITS_TC11DATA_8814B                                                    \
+	(BIT_MASK_TC11DATA_8814B << BIT_SHIFT_TC11DATA_8814B)
+#define BIT_CLEAR_TC11DATA_8814B(x) ((x) & (~BITS_TC11DATA_8814B))
+#define BIT_GET_TC11DATA_8814B(x)                                              \
+	(((x) >> BIT_SHIFT_TC11DATA_8814B) & BIT_MASK_TC11DATA_8814B)
+#define BIT_SET_TC11DATA_8814B(x, v)                                           \
+	(BIT_CLEAR_TC11DATA_8814B(x) | BIT_TC11DATA_8814B(v))
+
+/* 2 REG_TC12_CTRL_8814B */
+#define BIT_TC12INT_EN_8814B BIT(26)
+#define BIT_TC12MODE_8814B BIT(25)
+#define BIT_TC12EN_8814B BIT(24)
+
+#define BIT_SHIFT_TC12DATA_8814B 0
+#define BIT_MASK_TC12DATA_8814B 0xffffff
+#define BIT_TC12DATA_8814B(x)                                                  \
+	(((x) & BIT_MASK_TC12DATA_8814B) << BIT_SHIFT_TC12DATA_8814B)
+#define BITS_TC12DATA_8814B                                                    \
+	(BIT_MASK_TC12DATA_8814B << BIT_SHIFT_TC12DATA_8814B)
+#define BIT_CLEAR_TC12DATA_8814B(x) ((x) & (~BITS_TC12DATA_8814B))
+#define BIT_GET_TC12DATA_8814B(x)                                              \
+	(((x) >> BIT_SHIFT_TC12DATA_8814B) & BIT_MASK_TC12DATA_8814B)
+#define BIT_SET_TC12DATA_8814B(x, v)                                           \
+	(BIT_CLEAR_TC12DATA_8814B(x) | BIT_TC12DATA_8814B(v))
+
+/* 2 REG_FWFF_8814B */
+
+#define BIT_SHIFT_PKTNUM_TH_V1_8814B 24
+#define BIT_MASK_PKTNUM_TH_V1_8814B 0xff
+#define BIT_PKTNUM_TH_V1_8814B(x)                                              \
+	(((x) & BIT_MASK_PKTNUM_TH_V1_8814B) << BIT_SHIFT_PKTNUM_TH_V1_8814B)
+#define BITS_PKTNUM_TH_V1_8814B                                                \
+	(BIT_MASK_PKTNUM_TH_V1_8814B << BIT_SHIFT_PKTNUM_TH_V1_8814B)
+#define BIT_CLEAR_PKTNUM_TH_V1_8814B(x) ((x) & (~BITS_PKTNUM_TH_V1_8814B))
+#define BIT_GET_PKTNUM_TH_V1_8814B(x)                                          \
+	(((x) >> BIT_SHIFT_PKTNUM_TH_V1_8814B) & BIT_MASK_PKTNUM_TH_V1_8814B)
+#define BIT_SET_PKTNUM_TH_V1_8814B(x, v)                                       \
+	(BIT_CLEAR_PKTNUM_TH_V1_8814B(x) | BIT_PKTNUM_TH_V1_8814B(v))
+
+#define BIT_SHIFT_TIMER_TH_8814B 16
+#define BIT_MASK_TIMER_TH_8814B 0xff
+#define BIT_TIMER_TH_8814B(x)                                                  \
+	(((x) & BIT_MASK_TIMER_TH_8814B) << BIT_SHIFT_TIMER_TH_8814B)
+#define BITS_TIMER_TH_8814B                                                    \
+	(BIT_MASK_TIMER_TH_8814B << BIT_SHIFT_TIMER_TH_8814B)
+#define BIT_CLEAR_TIMER_TH_8814B(x) ((x) & (~BITS_TIMER_TH_8814B))
+#define BIT_GET_TIMER_TH_8814B(x)                                              \
+	(((x) >> BIT_SHIFT_TIMER_TH_8814B) & BIT_MASK_TIMER_TH_8814B)
+#define BIT_SET_TIMER_TH_8814B(x, v)                                           \
+	(BIT_CLEAR_TIMER_TH_8814B(x) | BIT_TIMER_TH_8814B(v))
+
+#define BIT_SHIFT_RXPKT1ENADDR_8814B 0
+#define BIT_MASK_RXPKT1ENADDR_8814B 0xffff
+#define BIT_RXPKT1ENADDR_8814B(x)                                              \
+	(((x) & BIT_MASK_RXPKT1ENADDR_8814B) << BIT_SHIFT_RXPKT1ENADDR_8814B)
+#define BITS_RXPKT1ENADDR_8814B                                                \
+	(BIT_MASK_RXPKT1ENADDR_8814B << BIT_SHIFT_RXPKT1ENADDR_8814B)
+#define BIT_CLEAR_RXPKT1ENADDR_8814B(x) ((x) & (~BITS_RXPKT1ENADDR_8814B))
+#define BIT_GET_RXPKT1ENADDR_8814B(x)                                          \
+	(((x) >> BIT_SHIFT_RXPKT1ENADDR_8814B) & BIT_MASK_RXPKT1ENADDR_8814B)
+#define BIT_SET_RXPKT1ENADDR_8814B(x, v)                                       \
+	(BIT_CLEAR_RXPKT1ENADDR_8814B(x) | BIT_RXPKT1ENADDR_8814B(v))
+
+/* 2 REG_RXFF_PTR_V1_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+#define BIT_SHIFT_RXFF0_RDPTR_V2_8814B 0
+#define BIT_MASK_RXFF0_RDPTR_V2_8814B 0x3ffff
+#define BIT_RXFF0_RDPTR_V2_8814B(x)                                            \
+	(((x) & BIT_MASK_RXFF0_RDPTR_V2_8814B)                                 \
+	 << BIT_SHIFT_RXFF0_RDPTR_V2_8814B)
+#define BITS_RXFF0_RDPTR_V2_8814B                                              \
+	(BIT_MASK_RXFF0_RDPTR_V2_8814B << BIT_SHIFT_RXFF0_RDPTR_V2_8814B)
+#define BIT_CLEAR_RXFF0_RDPTR_V2_8814B(x) ((x) & (~BITS_RXFF0_RDPTR_V2_8814B))
+#define BIT_GET_RXFF0_RDPTR_V2_8814B(x)                                        \
+	(((x) >> BIT_SHIFT_RXFF0_RDPTR_V2_8814B) &                             \
+	 BIT_MASK_RXFF0_RDPTR_V2_8814B)
+#define BIT_SET_RXFF0_RDPTR_V2_8814B(x, v)                                     \
+	(BIT_CLEAR_RXFF0_RDPTR_V2_8814B(x) | BIT_RXFF0_RDPTR_V2_8814B(v))
+
+/* 2 REG_RXFF_WTR_V1_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+#define BIT_SHIFT_RXFF0_WTPTR_V2_8814B 0
+#define BIT_MASK_RXFF0_WTPTR_V2_8814B 0x3ffff
+#define BIT_RXFF0_WTPTR_V2_8814B(x)                                            \
+	(((x) & BIT_MASK_RXFF0_WTPTR_V2_8814B)                                 \
+	 << BIT_SHIFT_RXFF0_WTPTR_V2_8814B)
+#define BITS_RXFF0_WTPTR_V2_8814B                                              \
+	(BIT_MASK_RXFF0_WTPTR_V2_8814B << BIT_SHIFT_RXFF0_WTPTR_V2_8814B)
+#define BIT_CLEAR_RXFF0_WTPTR_V2_8814B(x) ((x) & (~BITS_RXFF0_WTPTR_V2_8814B))
+#define BIT_GET_RXFF0_WTPTR_V2_8814B(x)                                        \
+	(((x) >> BIT_SHIFT_RXFF0_WTPTR_V2_8814B) &                             \
+	 BIT_MASK_RXFF0_WTPTR_V2_8814B)
+#define BIT_SET_RXFF0_WTPTR_V2_8814B(x, v)                                     \
+	(BIT_CLEAR_RXFF0_WTPTR_V2_8814B(x) | BIT_RXFF0_WTPTR_V2_8814B(v))
+
+/* 2 REG_FE2IMR_8814B */
+#define BIT__FE4ISR__IND_MSK_8814B BIT(29)
+#define BIT_FS_TXSC_DESC_DONE_INT_EN_8814B BIT(28)
+#define BIT_FS_TXSC_BKDONE_INT_EN_8814B BIT(27)
+#define BIT_FS_TXSC_BEDONE_INT_EN_8814B BIT(26)
+#define BIT_FS_TXSC_VIDONE_INT_EN_8814B BIT(25)
+#define BIT_FS_TXSC_VODONE_INT_EN_8814B BIT(24)
+#define BIT_FS_ATIM_MB7_INT_EN_8814B BIT(23)
+#define BIT_FS_ATIM_MB6_INT_EN_8814B BIT(22)
+#define BIT_FS_ATIM_MB5_INT_EN_8814B BIT(21)
+#define BIT_FS_ATIM_MB4_INT_EN_8814B BIT(20)
+#define BIT_FS_ATIM_MB3_INT_EN_8814B BIT(19)
+#define BIT_FS_ATIM_MB2_INT_EN_8814B BIT(18)
+#define BIT_FS_ATIM_MB1_INT_EN_8814B BIT(17)
+#define BIT_FS_ATIM_MB0_INT_EN_8814B BIT(16)
+#define BIT_FS_TBTT4INT_EN_8814B BIT(11)
+#define BIT_FS_TBTT3INT_EN_8814B BIT(10)
+#define BIT_FS_TBTT2INT_EN_8814B BIT(9)
+#define BIT_FS_TBTT1INT_EN_8814B BIT(8)
+#define BIT_FS_TBTT0_MB7INT_EN_8814B BIT(7)
+#define BIT_FS_TBTT0_MB6INT_EN_8814B BIT(6)
+#define BIT_FS_TBTT0_MB5INT_EN_8814B BIT(5)
+#define BIT_FS_TBTT0_MB4INT_EN_8814B BIT(4)
+#define BIT_FS_TBTT0_MB3INT_EN_8814B BIT(3)
+#define BIT_FS_TBTT0_MB2INT_EN_8814B BIT(2)
+#define BIT_FS_TBTT0_MB1INT_EN_8814B BIT(1)
+#define BIT_FS_TBTT0_INT_EN_8814B BIT(0)
+
+/* 2 REG_FE2ISR_8814B */
+#define BIT__FE4ISR__IND_INT_8814B BIT(29)
+#define BIT_FS_TXSC_DESC_DONE_INT_8814B BIT(28)
+#define BIT_FS_TXSC_BKDONE_INT_8814B BIT(27)
+#define BIT_FS_TXSC_BEDONE_INT_8814B BIT(26)
+#define BIT_FS_TXSC_VIDONE_INT_8814B BIT(25)
+#define BIT_FS_TXSC_VODONE_INT_8814B BIT(24)
+#define BIT_FS_ATIM_MB7_INT_8814B BIT(23)
+#define BIT_FS_ATIM_MB6_INT_8814B BIT(22)
+#define BIT_FS_ATIM_MB5_INT_8814B BIT(21)
+#define BIT_FS_ATIM_MB4_INT_8814B BIT(20)
+#define BIT_FS_ATIM_MB3_INT_8814B BIT(19)
+#define BIT_FS_ATIM_MB2_INT_8814B BIT(18)
+#define BIT_FS_ATIM_MB1_INT_8814B BIT(17)
+#define BIT_FS_ATIM_MB0_INT_8814B BIT(16)
+#define BIT_FS_TBTT4INT_8814B BIT(11)
+#define BIT_FS_TBTT3INT_8814B BIT(10)
+#define BIT_FS_TBTT2INT_8814B BIT(9)
+#define BIT_FS_TBTT1INT_8814B BIT(8)
+#define BIT_FS_TBTT0_MB7INT_8814B BIT(7)
+#define BIT_FS_TBTT0_MB6INT_8814B BIT(6)
+#define BIT_FS_TBTT0_MB5INT_8814B BIT(5)
+#define BIT_FS_TBTT0_MB4INT_8814B BIT(4)
+#define BIT_FS_TBTT0_MB3INT_8814B BIT(3)
+#define BIT_FS_TBTT0_MB2INT_8814B BIT(2)
+#define BIT_FS_TBTT0_MB1INT_8814B BIT(1)
+#define BIT_FS_TBTT0_INT_8814B BIT(0)
+
+/* 2 REG_FE3IMR_8814B */
+#define BIT_FS_CLI3_MTI_BCNIVLEAR_INT__EN_8814B BIT(31)
+#define BIT_FS_CLI2_MTI_BCNIVLEAR_INT__EN_8814B BIT(30)
+#define BIT_FS_CLI1_MTI_BCNIVLEAR_INT__EN_8814B BIT(29)
+#define BIT_FS_CLI0_MTI_BCNIVLEAR_INT__EN_8814B BIT(28)
+#define BIT_FS_BCNDMA4_INT_EN_8814B BIT(27)
+#define BIT_FS_BCNDMA3_INT_EN_8814B BIT(26)
+#define BIT_FS_BCNDMA2_INT_EN_8814B BIT(25)
+#define BIT_FS_BCNDMA1_INT_EN_8814B BIT(24)
+#define BIT_FS_BCNDMA0_MB7_INT_EN_8814B BIT(23)
+#define BIT_FS_BCNDMA0_MB6_INT_EN_8814B BIT(22)
+#define BIT_FS_BCNDMA0_MB5_INT_EN_8814B BIT(21)
+#define BIT_FS_BCNDMA0_MB4_INT_EN_8814B BIT(20)
+#define BIT_FS_BCNDMA0_MB3_INT_EN_8814B BIT(19)
+#define BIT_FS_BCNDMA0_MB2_INT_EN_8814B BIT(18)
+#define BIT_FS_BCNDMA0_MB1_INT_EN_8814B BIT(17)
+#define BIT_FS_BCNDMA0_INT_EN_8814B BIT(16)
+#define BIT_FS_MTI_BCNIVLEAR_INT__EN_8814B BIT(15)
+#define BIT_FS_BCNERLY4_INT_EN_8814B BIT(11)
+#define BIT_FS_BCNERLY3_INT_EN_8814B BIT(10)
+#define BIT_FS_BCNERLY2_INT_EN_8814B BIT(9)
+#define BIT_FS_BCNERLY1_INT_EN_8814B BIT(8)
+#define BIT_FS_BCNERLY0_MB7INT_EN_8814B BIT(7)
+#define BIT_FS_BCNERLY0_MB6INT_EN_8814B BIT(6)
+#define BIT_FS_BCNERLY0_MB5INT_EN_8814B BIT(5)
+#define BIT_FS_BCNERLY0_MB4INT_EN_8814B BIT(4)
+#define BIT_FS_BCNERLY0_MB3INT_EN_8814B BIT(3)
+#define BIT_FS_BCNERLY0_MB2INT_EN_8814B BIT(2)
+#define BIT_FS_BCNERLY0_MB1INT_EN_8814B BIT(1)
+#define BIT_FS_BCNERLY0_INT_EN_8814B BIT(0)
+
+/* 2 REG_FE3ISR_8814B */
+#define BIT_FS_CLI3_MTI_BCNIVLEAR_INT_8814B BIT(31)
+#define BIT_FS_CLI2_MTI_BCNIVLEAR_INT_8814B BIT(30)
+#define BIT_FS_CLI1_MTI_BCNIVLEAR_INT_8814B BIT(29)
+#define BIT_FS_CLI0_MTI_BCNIVLEAR_INT_8814B BIT(28)
+#define BIT_FS_BCNDMA4_INT_8814B BIT(27)
+#define BIT_FS_BCNDMA3_INT_8814B BIT(26)
+#define BIT_FS_BCNDMA2_INT_8814B BIT(25)
+#define BIT_FS_BCNDMA1_INT_8814B BIT(24)
+#define BIT_FS_BCNDMA0_MB7_INT_8814B BIT(23)
+#define BIT_FS_BCNDMA0_MB6_INT_8814B BIT(22)
+#define BIT_FS_BCNDMA0_MB5_INT_8814B BIT(21)
+#define BIT_FS_BCNDMA0_MB4_INT_8814B BIT(20)
+#define BIT_FS_BCNDMA0_MB3_INT_8814B BIT(19)
+#define BIT_FS_BCNDMA0_MB2_INT_8814B BIT(18)
+#define BIT_FS_BCNDMA0_MB1_INT_8814B BIT(17)
+#define BIT_FS_BCNDMA0_INT_8814B BIT(16)
+#define BIT_FS_MTI_BCNIVLEAR_INT_8814B BIT(15)
+#define BIT_FS_BCNERLY4_INT_8814B BIT(11)
+#define BIT_FS_BCNERLY3_INT_8814B BIT(10)
+#define BIT_FS_BCNERLY2_INT_8814B BIT(9)
+#define BIT_FS_BCNERLY1_INT_8814B BIT(8)
+#define BIT_FS_BCNERLY0_MB7INT_8814B BIT(7)
+#define BIT_FS_BCNERLY0_MB6INT_8814B BIT(6)
+#define BIT_FS_BCNERLY0_MB5INT_8814B BIT(5)
+#define BIT_FS_BCNERLY0_MB4INT_8814B BIT(4)
+#define BIT_FS_BCNERLY0_MB3INT_8814B BIT(3)
+#define BIT_FS_BCNERLY0_MB2INT_8814B BIT(2)
+#define BIT_FS_BCNERLY0_MB1INT_8814B BIT(1)
+#define BIT_FS_BCNERLY0_INT_8814B BIT(0)
+
+/* 2 REG_FE4IMR_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+#define BIT_FS_CLI3_TXPKTIN_INT_EN_8814B BIT(19)
+#define BIT_FS_CLI2_TXPKTIN_INT_EN_8814B BIT(18)
+#define BIT_FS_CLI1_TXPKTIN_INT_EN_8814B BIT(17)
+#define BIT_FS_CLI0_TXPKTIN_INT_EN_8814B BIT(16)
+#define BIT_FS_CLI3_RX_UMD0_INT_EN_8814B BIT(15)
+#define BIT_FS_CLI3_RX_UMD1_INT_EN_8814B BIT(14)
+#define BIT_FS_CLI3_RX_BMD0_INT_EN_8814B BIT(13)
+#define BIT_FS_CLI3_RX_BMD1_INT_EN_8814B BIT(12)
+#define BIT_FS_CLI2_RX_UMD0_INT_EN_8814B BIT(11)
+#define BIT_FS_CLI2_RX_UMD1_INT_EN_8814B BIT(10)
+#define BIT_FS_CLI2_RX_BMD0_INT_EN_8814B BIT(9)
+#define BIT_FS_CLI2_RX_BMD1_INT_EN_8814B BIT(8)
+#define BIT_FS_CLI1_RX_UMD0_INT_EN_8814B BIT(7)
+#define BIT_FS_CLI1_RX_UMD1_INT_EN_8814B BIT(6)
+#define BIT_FS_CLI1_RX_BMD0_INT_EN_8814B BIT(5)
+#define BIT_FS_CLI1_RX_BMD1_INT_EN_8814B BIT(4)
+#define BIT_FS_CLI0_RX_UMD0_INT_EN_8814B BIT(3)
+#define BIT_FS_CLI0_RX_UMD1_INT_EN_8814B BIT(2)
+#define BIT_FS_CLI0_RX_BMD0_INT_EN_8814B BIT(1)
+#define BIT_FS_CLI0_RX_BMD1_INT_EN_8814B BIT(0)
+
+/* 2 REG_FE4ISR_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+#define BIT_P2P_PWROFF_NOA2_ERLY_INT_8814B BIT(22)
+#define BIT_P2P_PWROFF_NOA1_ERLY_INT_8814B BIT(21)
+#define BIT_P2P_PWROFF_NOA0_ERLY_INT_8814B BIT(20)
+#define BIT_FS_CLI3_TXPKTIN_INT_8814B BIT(19)
+#define BIT_FS_CLI2_TXPKTIN_INT_8814B BIT(18)
+#define BIT_FS_CLI1_TXPKTIN_INT_8814B BIT(17)
+#define BIT_FS_CLI0_TXPKTIN_INT_8814B BIT(16)
+#define BIT_FS_CLI3_RX_UMD0_INT_8814B BIT(15)
+#define BIT_FS_CLI3_RX_UMD1_INT_8814B BIT(14)
+#define BIT_FS_CLI3_RX_BMD0_INT_8814B BIT(13)
+#define BIT_FS_CLI3_RX_BMD1_INT_8814B BIT(12)
+#define BIT_FS_CLI2_RX_UMD0_INT_8814B BIT(11)
+#define BIT_FS_CLI2_RX_UMD1_INT_8814B BIT(10)
+#define BIT_FS_CLI2_RX_BMD0_INT_8814B BIT(9)
+#define BIT_FS_CLI2_RX_BMD1_INT_8814B BIT(8)
+#define BIT_FS_CLI1_RX_UMD0_INT_8814B BIT(7)
+#define BIT_FS_CLI1_RX_UMD1_INT_8814B BIT(6)
+#define BIT_FS_CLI1_RX_BMD0_INT_8814B BIT(5)
+#define BIT_FS_CLI1_RX_BMD1_INT_8814B BIT(4)
+#define BIT_FS_CLI0_RX_UMD0_INT_8814B BIT(3)
+#define BIT_FS_CLI0_RX_UMD1_INT_8814B BIT(2)
+#define BIT_FS_CLI0_RX_BMD0_INT_8814B BIT(1)
+#define BIT_FS_CLI0_RX_BMD1_INT_8814B BIT(0)
+
+/* 2 REG_FT1IMR_8814B */
+#define BIT__FT2ISR__IND_MSK_8814B BIT(30)
+#define BIT_FTM_PTT_INT_EN_8814B BIT(29)
+#define BIT_RXFTMREQ_INT_EN_8814B BIT(28)
+#define BIT_RXFTM_INT_EN_8814B BIT(27)
+#define BIT_TXFTM_INT_EN_8814B BIT(26)
+#define BIT_FS_H2C_CMD_OK_INT_EN_8814B BIT(25)
+#define BIT_FS_H2C_CMD_FULL_INT_EN_8814B BIT(24)
+#define BIT_FS_MACID_SEARCH_FAIL_INT_EN_8814B BIT(22)
+#define BIT_FS_MACID_PWRCHANGE3_INT_EN_8814B BIT(21)
+#define BIT_FS_MACID_PWRCHANGE2_INT_EN_8814B BIT(20)
+#define BIT_FS_MACID_PWRCHANGE1_INT_EN_8814B BIT(19)
+#define BIT_FS_MACID_PWRCHANGE0_INT_EN_8814B BIT(18)
+#define BIT_FS_CTWEND2_INT_EN_8814B BIT(17)
+#define BIT_FS_CTWEND1_INT_EN_8814B BIT(16)
+#define BIT_FS_CTWEND0_INT_EN_8814B BIT(15)
+#define BIT_FS_TX_NULL1_INT_EN_8814B BIT(14)
+#define BIT_FS_TX_NULL0_INT_EN_8814B BIT(13)
+#define BIT_FS_TSF_BIT32_TOGGLE_EN_8814B BIT(12)
+#define BIT_FS_P2P_RFON2_INT_EN_8814B BIT(11)
+#define BIT_FS_P2P_RFOFF2_INT_EN_8814B BIT(10)
+#define BIT_FS_P2P_RFON1_INT_EN_8814B BIT(9)
+#define BIT_FS_P2P_RFOFF1_INT_EN_8814B BIT(8)
+#define BIT_FS_P2P_RFON0_INT_EN_8814B BIT(7)
+#define BIT_FS_P2P_RFOFF0_INT_EN_8814B BIT(6)
+#define BIT_FS_RX_UAPSDMD1_EN_8814B BIT(5)
+#define BIT_FS_RX_UAPSDMD0_EN_8814B BIT(4)
+#define BIT_FS_TRIGGER_PKT_EN_8814B BIT(3)
+#define BIT_FS_EOSP_INT_EN_8814B BIT(2)
+#define BIT_FS_RPWM2_INT_EN_8814B BIT(1)
+#define BIT_FS_RPWM_INT_EN_8814B BIT(0)
+
+/* 2 REG_FT1ISR_8814B */
+#define BIT__FT2ISR__IND_INT_8814B BIT(30)
+#define BIT_FTM_PTT_INT_8814B BIT(29)
+#define BIT_RXFTMREQ_INT_8814B BIT(28)
+#define BIT_RXFTM_INT_8814B BIT(27)
+#define BIT_TXFTM_INT_8814B BIT(26)
+#define BIT_FS_H2C_CMD_OK_INT_8814B BIT(25)
+#define BIT_FS_H2C_CMD_FULL_INT_8814B BIT(24)
+#define BIT_FS_MACID_SEARCH_FAIL_INT_8814B BIT(22)
+#define BIT_FS_MACID_PWRCHANGE3_INT_8814B BIT(21)
+#define BIT_FS_MACID_PWRCHANGE2_INT_8814B BIT(20)
+#define BIT_FS_MACID_PWRCHANGE1_INT_8814B BIT(19)
+#define BIT_FS_MACID_PWRCHANGE0_INT_8814B BIT(18)
+#define BIT_FS_CTWEND2_INT_8814B BIT(17)
+#define BIT_FS_CTWEND1_INT_8814B BIT(16)
+#define BIT_FS_CTWEND0_INT_8814B BIT(15)
+#define BIT_FS_TX_NULL1_INT_8814B BIT(14)
+#define BIT_FS_TX_NULL0_INT_8814B BIT(13)
+#define BIT_FS_TSF_BIT32_TOGGLE_INT_8814B BIT(12)
+#define BIT_FS_P2P_RFON2_INT_8814B BIT(11)
+#define BIT_FS_P2P_RFOFF2_INT_8814B BIT(10)
+#define BIT_FS_P2P_RFON1_INT_8814B BIT(9)
+#define BIT_FS_P2P_RFOFF1_INT_8814B BIT(8)
+#define BIT_FS_P2P_RFON0_INT_8814B BIT(7)
+#define BIT_FS_P2P_RFOFF0_INT_8814B BIT(6)
+#define BIT_FS_RX_UAPSDMD1_INT_8814B BIT(5)
+#define BIT_FS_RX_UAPSDMD0_INT_8814B BIT(4)
+#define BIT_FS_TRIGGER_PKT_INT_8814B BIT(3)
+#define BIT_FS_EOSP_INT_8814B BIT(2)
+#define BIT_FS_RPWM2_INT_8814B BIT(1)
+#define BIT_FS_RPWM_INT_8814B BIT(0)
+
+/* 2 REG_SPWR0_8814B */
+
+#define BIT_SHIFT_MID_31TO0_8814B 0
+#define BIT_MASK_MID_31TO0_8814B 0xffffffffL
+#define BIT_MID_31TO0_8814B(x)                                                 \
+	(((x) & BIT_MASK_MID_31TO0_8814B) << BIT_SHIFT_MID_31TO0_8814B)
+#define BITS_MID_31TO0_8814B                                                   \
+	(BIT_MASK_MID_31TO0_8814B << BIT_SHIFT_MID_31TO0_8814B)
+#define BIT_CLEAR_MID_31TO0_8814B(x) ((x) & (~BITS_MID_31TO0_8814B))
+#define BIT_GET_MID_31TO0_8814B(x)                                             \
+	(((x) >> BIT_SHIFT_MID_31TO0_8814B) & BIT_MASK_MID_31TO0_8814B)
+#define BIT_SET_MID_31TO0_8814B(x, v)                                          \
+	(BIT_CLEAR_MID_31TO0_8814B(x) | BIT_MID_31TO0_8814B(v))
+
+/* 2 REG_SPWR1_8814B */
+
+#define BIT_SHIFT_MID_63TO32_8814B 0
+#define BIT_MASK_MID_63TO32_8814B 0xffffffffL
+#define BIT_MID_63TO32_8814B(x)                                                \
+	(((x) & BIT_MASK_MID_63TO32_8814B) << BIT_SHIFT_MID_63TO32_8814B)
+#define BITS_MID_63TO32_8814B                                                  \
+	(BIT_MASK_MID_63TO32_8814B << BIT_SHIFT_MID_63TO32_8814B)
+#define BIT_CLEAR_MID_63TO32_8814B(x) ((x) & (~BITS_MID_63TO32_8814B))
+#define BIT_GET_MID_63TO32_8814B(x)                                            \
+	(((x) >> BIT_SHIFT_MID_63TO32_8814B) & BIT_MASK_MID_63TO32_8814B)
+#define BIT_SET_MID_63TO32_8814B(x, v)                                         \
+	(BIT_CLEAR_MID_63TO32_8814B(x) | BIT_MID_63TO32_8814B(v))
+
+/* 2 REG_SPWR2_8814B */
+
+#define BIT_SHIFT_MID_95O64_8814B 0
+#define BIT_MASK_MID_95O64_8814B 0xffffffffL
+#define BIT_MID_95O64_8814B(x)                                                 \
+	(((x) & BIT_MASK_MID_95O64_8814B) << BIT_SHIFT_MID_95O64_8814B)
+#define BITS_MID_95O64_8814B                                                   \
+	(BIT_MASK_MID_95O64_8814B << BIT_SHIFT_MID_95O64_8814B)
+#define BIT_CLEAR_MID_95O64_8814B(x) ((x) & (~BITS_MID_95O64_8814B))
+#define BIT_GET_MID_95O64_8814B(x)                                             \
+	(((x) >> BIT_SHIFT_MID_95O64_8814B) & BIT_MASK_MID_95O64_8814B)
+#define BIT_SET_MID_95O64_8814B(x, v)                                          \
+	(BIT_CLEAR_MID_95O64_8814B(x) | BIT_MID_95O64_8814B(v))
+
+/* 2 REG_SPWR3_8814B */
+
+#define BIT_SHIFT_MID_127TO96_8814B 0
+#define BIT_MASK_MID_127TO96_8814B 0xffffffffL
+#define BIT_MID_127TO96_8814B(x)                                               \
+	(((x) & BIT_MASK_MID_127TO96_8814B) << BIT_SHIFT_MID_127TO96_8814B)
+#define BITS_MID_127TO96_8814B                                                 \
+	(BIT_MASK_MID_127TO96_8814B << BIT_SHIFT_MID_127TO96_8814B)
+#define BIT_CLEAR_MID_127TO96_8814B(x) ((x) & (~BITS_MID_127TO96_8814B))
+#define BIT_GET_MID_127TO96_8814B(x)                                           \
+	(((x) >> BIT_SHIFT_MID_127TO96_8814B) & BIT_MASK_MID_127TO96_8814B)
+#define BIT_SET_MID_127TO96_8814B(x, v)                                        \
+	(BIT_CLEAR_MID_127TO96_8814B(x) | BIT_MID_127TO96_8814B(v))
+
+/* 2 REG_POWSEQ_8814B */
+
+#define BIT_SHIFT_SEQNUM_MID_8814B 16
+#define BIT_MASK_SEQNUM_MID_8814B 0xffff
+#define BIT_SEQNUM_MID_8814B(x)                                                \
+	(((x) & BIT_MASK_SEQNUM_MID_8814B) << BIT_SHIFT_SEQNUM_MID_8814B)
+#define BITS_SEQNUM_MID_8814B                                                  \
+	(BIT_MASK_SEQNUM_MID_8814B << BIT_SHIFT_SEQNUM_MID_8814B)
+#define BIT_CLEAR_SEQNUM_MID_8814B(x) ((x) & (~BITS_SEQNUM_MID_8814B))
+#define BIT_GET_SEQNUM_MID_8814B(x)                                            \
+	(((x) >> BIT_SHIFT_SEQNUM_MID_8814B) & BIT_MASK_SEQNUM_MID_8814B)
+#define BIT_SET_SEQNUM_MID_8814B(x, v)                                         \
+	(BIT_CLEAR_SEQNUM_MID_8814B(x) | BIT_SEQNUM_MID_8814B(v))
+
+#define BIT_SHIFT_REF_MID_8814B 0
+#define BIT_MASK_REF_MID_8814B 0x7f
+#define BIT_REF_MID_8814B(x)                                                   \
+	(((x) & BIT_MASK_REF_MID_8814B) << BIT_SHIFT_REF_MID_8814B)
+#define BITS_REF_MID_8814B (BIT_MASK_REF_MID_8814B << BIT_SHIFT_REF_MID_8814B)
+#define BIT_CLEAR_REF_MID_8814B(x) ((x) & (~BITS_REF_MID_8814B))
+#define BIT_GET_REF_MID_8814B(x)                                               \
+	(((x) >> BIT_SHIFT_REF_MID_8814B) & BIT_MASK_REF_MID_8814B)
+#define BIT_SET_REF_MID_8814B(x, v)                                            \
+	(BIT_CLEAR_REF_MID_8814B(x) | BIT_REF_MID_8814B(v))
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_TC7_CTRL_V1_8814B */
+#define BIT_TC7INT_EN_8814B BIT(26)
+#define BIT_TC7MODE_8814B BIT(25)
+#define BIT_TC7EN_8814B BIT(24)
+
+#define BIT_SHIFT_TC7DATA_8814B 0
+#define BIT_MASK_TC7DATA_8814B 0xffffff
+#define BIT_TC7DATA_8814B(x)                                                   \
+	(((x) & BIT_MASK_TC7DATA_8814B) << BIT_SHIFT_TC7DATA_8814B)
+#define BITS_TC7DATA_8814B (BIT_MASK_TC7DATA_8814B << BIT_SHIFT_TC7DATA_8814B)
+#define BIT_CLEAR_TC7DATA_8814B(x) ((x) & (~BITS_TC7DATA_8814B))
+#define BIT_GET_TC7DATA_8814B(x)                                               \
+	(((x) >> BIT_SHIFT_TC7DATA_8814B) & BIT_MASK_TC7DATA_8814B)
+#define BIT_SET_TC7DATA_8814B(x, v)                                            \
+	(BIT_CLEAR_TC7DATA_8814B(x) | BIT_TC7DATA_8814B(v))
+
+/* 2 REG_TC8_CTRL_V1_8814B */
+#define BIT_TC8INT_EN_8814B BIT(26)
+#define BIT_TC8MODE_8814B BIT(25)
+#define BIT_TC8EN_8814B BIT(24)
+
+#define BIT_SHIFT_TC8DATA_8814B 0
+#define BIT_MASK_TC8DATA_8814B 0xffffff
+#define BIT_TC8DATA_8814B(x)                                                   \
+	(((x) & BIT_MASK_TC8DATA_8814B) << BIT_SHIFT_TC8DATA_8814B)
+#define BITS_TC8DATA_8814B (BIT_MASK_TC8DATA_8814B << BIT_SHIFT_TC8DATA_8814B)
+#define BIT_CLEAR_TC8DATA_8814B(x) ((x) & (~BITS_TC8DATA_8814B))
+#define BIT_GET_TC8DATA_8814B(x)                                               \
+	(((x) >> BIT_SHIFT_TC8DATA_8814B) & BIT_MASK_TC8DATA_8814B)
+#define BIT_SET_TC8DATA_8814B(x, v)                                            \
+	(BIT_CLEAR_TC8DATA_8814B(x) | BIT_TC8DATA_8814B(v))
+
+/* 2 REG_RX_BCN_TBTT_ITVL0_8814B */
+
+#define BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT2_8814B 24
+#define BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT2_8814B 0xff
+#define BIT_RX_BCN_TBTT_ITVL_CLIENT2_8814B(x)                                  \
+	(((x) & BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT2_8814B)                       \
+	 << BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT2_8814B)
+#define BITS_RX_BCN_TBTT_ITVL_CLIENT2_8814B                                    \
+	(BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT2_8814B                               \
+	 << BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT2_8814B)
+#define BIT_CLEAR_RX_BCN_TBTT_ITVL_CLIENT2_8814B(x)                            \
+	((x) & (~BITS_RX_BCN_TBTT_ITVL_CLIENT2_8814B))
+#define BIT_GET_RX_BCN_TBTT_ITVL_CLIENT2_8814B(x)                              \
+	(((x) >> BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT2_8814B) &                   \
+	 BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT2_8814B)
+#define BIT_SET_RX_BCN_TBTT_ITVL_CLIENT2_8814B(x, v)                           \
+	(BIT_CLEAR_RX_BCN_TBTT_ITVL_CLIENT2_8814B(x) |                         \
+	 BIT_RX_BCN_TBTT_ITVL_CLIENT2_8814B(v))
+
+#define BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT1_8814B 16
+#define BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT1_8814B 0xff
+#define BIT_RX_BCN_TBTT_ITVL_CLIENT1_8814B(x)                                  \
+	(((x) & BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT1_8814B)                       \
+	 << BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT1_8814B)
+#define BITS_RX_BCN_TBTT_ITVL_CLIENT1_8814B                                    \
+	(BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT1_8814B                               \
+	 << BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT1_8814B)
+#define BIT_CLEAR_RX_BCN_TBTT_ITVL_CLIENT1_8814B(x)                            \
+	((x) & (~BITS_RX_BCN_TBTT_ITVL_CLIENT1_8814B))
+#define BIT_GET_RX_BCN_TBTT_ITVL_CLIENT1_8814B(x)                              \
+	(((x) >> BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT1_8814B) &                   \
+	 BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT1_8814B)
+#define BIT_SET_RX_BCN_TBTT_ITVL_CLIENT1_8814B(x, v)                           \
+	(BIT_CLEAR_RX_BCN_TBTT_ITVL_CLIENT1_8814B(x) |                         \
+	 BIT_RX_BCN_TBTT_ITVL_CLIENT1_8814B(v))
+
+#define BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT0_8814B 8
+#define BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT0_8814B 0xff
+#define BIT_RX_BCN_TBTT_ITVL_CLIENT0_8814B(x)                                  \
+	(((x) & BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT0_8814B)                       \
+	 << BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT0_8814B)
+#define BITS_RX_BCN_TBTT_ITVL_CLIENT0_8814B                                    \
+	(BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT0_8814B                               \
+	 << BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT0_8814B)
+#define BIT_CLEAR_RX_BCN_TBTT_ITVL_CLIENT0_8814B(x)                            \
+	((x) & (~BITS_RX_BCN_TBTT_ITVL_CLIENT0_8814B))
+#define BIT_GET_RX_BCN_TBTT_ITVL_CLIENT0_8814B(x)                              \
+	(((x) >> BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT0_8814B) &                   \
+	 BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT0_8814B)
+#define BIT_SET_RX_BCN_TBTT_ITVL_CLIENT0_8814B(x, v)                           \
+	(BIT_CLEAR_RX_BCN_TBTT_ITVL_CLIENT0_8814B(x) |                         \
+	 BIT_RX_BCN_TBTT_ITVL_CLIENT0_8814B(v))
+
+#define BIT_SHIFT_RX_BCN_TBTT_ITVL_PORT0_8814B 0
+#define BIT_MASK_RX_BCN_TBTT_ITVL_PORT0_8814B 0xff
+#define BIT_RX_BCN_TBTT_ITVL_PORT0_8814B(x)                                    \
+	(((x) & BIT_MASK_RX_BCN_TBTT_ITVL_PORT0_8814B)                         \
+	 << BIT_SHIFT_RX_BCN_TBTT_ITVL_PORT0_8814B)
+#define BITS_RX_BCN_TBTT_ITVL_PORT0_8814B                                      \
+	(BIT_MASK_RX_BCN_TBTT_ITVL_PORT0_8814B                                 \
+	 << BIT_SHIFT_RX_BCN_TBTT_ITVL_PORT0_8814B)
+#define BIT_CLEAR_RX_BCN_TBTT_ITVL_PORT0_8814B(x)                              \
+	((x) & (~BITS_RX_BCN_TBTT_ITVL_PORT0_8814B))
+#define BIT_GET_RX_BCN_TBTT_ITVL_PORT0_8814B(x)                                \
+	(((x) >> BIT_SHIFT_RX_BCN_TBTT_ITVL_PORT0_8814B) &                     \
+	 BIT_MASK_RX_BCN_TBTT_ITVL_PORT0_8814B)
+#define BIT_SET_RX_BCN_TBTT_ITVL_PORT0_8814B(x, v)                             \
+	(BIT_CLEAR_RX_BCN_TBTT_ITVL_PORT0_8814B(x) |                           \
+	 BIT_RX_BCN_TBTT_ITVL_PORT0_8814B(v))
+
+/* 2 REG_RX_BCN_TBTT_ITVL1_8814B */
+
+#define BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT3_8814B 0
+#define BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT3_8814B 0xff
+#define BIT_RX_BCN_TBTT_ITVL_CLIENT3_8814B(x)                                  \
+	(((x) & BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT3_8814B)                       \
+	 << BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT3_8814B)
+#define BITS_RX_BCN_TBTT_ITVL_CLIENT3_8814B                                    \
+	(BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT3_8814B                               \
+	 << BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT3_8814B)
+#define BIT_CLEAR_RX_BCN_TBTT_ITVL_CLIENT3_8814B(x)                            \
+	((x) & (~BITS_RX_BCN_TBTT_ITVL_CLIENT3_8814B))
+#define BIT_GET_RX_BCN_TBTT_ITVL_CLIENT3_8814B(x)                              \
+	(((x) >> BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT3_8814B) &                   \
+	 BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT3_8814B)
+#define BIT_SET_RX_BCN_TBTT_ITVL_CLIENT3_8814B(x, v)                           \
+	(BIT_CLEAR_RX_BCN_TBTT_ITVL_CLIENT3_8814B(x) |                         \
+	 BIT_RX_BCN_TBTT_ITVL_CLIENT3_8814B(v))
+
+/* 2 REG_FWIMR1_8814B */
+#define BIT_FS_ATIM_MB15_INT_EN_8814B BIT(31)
+#define BIT_FS_ATIM_MB14_INT_EN_8814B BIT(30)
+#define BIT_FS_ATIM_MB13_INT_EN_8814B BIT(29)
+#define BIT_FS_ATIM_MB12_INT_EN_8814B BIT(28)
+#define BIT_FS_ATIM_MB11_INT_EN_8814B BIT(27)
+#define BIT_FS_ATIM_MB10_INT_EN_8814B BIT(26)
+#define BIT_FS_ATIM_MB9_INT_EN_8814B BIT(25)
+#define BIT_FS_ATIM_MB8_INT_EN_8814B BIT(24)
+#define BIT_FS_TXBCNERR_MB15_INT_EN_8814B BIT(23)
+#define BIT_FS_TXBCNERR_MB14_INT_EN_8814B BIT(22)
+#define BIT_FS_TXBCNERR_MB13_INT_EN_8814B BIT(21)
+#define BIT_FS_TXBCNERR_MB12_INT_EN_8814B BIT(20)
+#define BIT_FS_TXBCNERR_MB11_INT_EN_8814B BIT(19)
+#define BIT_FS_TXBCNERR_MB10_INT_EN_8814B BIT(18)
+#define BIT_FS_TXBCNERR_MB9_INT_EN_8814B BIT(17)
+#define BIT_FS_TXBCNERR_MB8_INT_EN_8814B BIT(16)
+#define BIT_FS_TXBCNOK_MB15_INT_EN_8814B BIT(15)
+#define BIT_FS_TXBCNOK_MB14_INT_EN_8814B BIT(14)
+#define BIT_FS_TXBCNOK_MB13_INT_EN_8814B BIT(13)
+#define BIT_FS_TXBCNOK_MB12_INT_EN_8814B BIT(12)
+#define BIT_FS_TXBCNOK_MB11_INT_EN_8814B BIT(11)
+#define BIT_FS_TXBCNOK_MB10_INT_EN_8814B BIT(10)
+#define BIT_FS_TXBCNOK_MB9_INT_EN_8814B BIT(9)
+#define BIT_FS_TXBCNOK_MB8_INT_EN_8814B BIT(8)
+#define BIT_FS_BCNERLY0_MB15INT_EN_8814B BIT(7)
+#define BIT_FS_BCNERLY0_MB14INT_EN_8814B BIT(6)
+#define BIT_FS_BCNERLY0_MB13INT_EN_8814B BIT(5)
+#define BIT_FS_BCNERLY0_MB12INT_EN_8814B BIT(4)
+#define BIT_FS_BCNERLY0_MB11INT_EN_8814B BIT(3)
+#define BIT_FS_BCNERLY0_MB10INT_EN_8814B BIT(2)
+#define BIT_FS_BCNERLY0_MB9INT_EN_8814B BIT(1)
+#define BIT_FS_BCNERLY0_MB8INT_EN_8814B BIT(0)
+
+/* 2 REG_FWISR1_8814B */
+#define BIT_FS_ATIM_MB15_INT_8814B BIT(31)
+#define BIT_FS_ATIM_MB14_INT_8814B BIT(30)
+#define BIT_FS_ATIM_MB13_INT_8814B BIT(29)
+#define BIT_FS_ATIM_MB12_INT_8814B BIT(28)
+#define BIT_FS_ATIM_MB11_INT_8814B BIT(27)
+#define BIT_FS_ATIM_MB10_INT_8814B BIT(26)
+#define BIT_FS_ATIM_MB9_INT_8814B BIT(25)
+#define BIT_FS_ATIM_MB8_INT_8814B BIT(24)
+#define BIT_FS_TXBCNERR_MB15_INT_8814B BIT(23)
+#define BIT_FS_TXBCNERR_MB14_INT_8814B BIT(22)
+#define BIT_FS_TXBCNERR_MB13_INT_8814B BIT(21)
+#define BIT_FS_TXBCNERR_MB12_INT_8814B BIT(20)
+#define BIT_FS_TXBCNERR_MB11_INT_8814B BIT(19)
+#define BIT_FS_TXBCNERR_MB10_INT_8814B BIT(18)
+#define BIT_FS_TXBCNERR_MB9_INT_8814B BIT(17)
+#define BIT_FS_TXBCNERR_MB8_INT_8814B BIT(16)
+#define BIT_FS_TXBCNOK_MB15_INT_8814B BIT(15)
+#define BIT_FS_TXBCNOK_MB14_INT_8814B BIT(14)
+#define BIT_FS_TXBCNOK_MB13_INT_8814B BIT(13)
+#define BIT_FS_TXBCNOK_MB12_INT_8814B BIT(12)
+#define BIT_FS_TXBCNOK_MB11_INT_8814B BIT(11)
+#define BIT_FS_TXBCNOK_MB10_INT_8814B BIT(10)
+#define BIT_FS_TXBCNOK_MB9_INT_8814B BIT(9)
+#define BIT_FS_TXBCNOK_MB8_INT_8814B BIT(8)
+#define BIT_FS_BCNERLY0_MB15INT_8814B BIT(7)
+#define BIT_FS_BCNERLY0_MB14INT_8814B BIT(6)
+#define BIT_FS_BCNERLY0_MB13INT_8814B BIT(5)
+#define BIT_FS_BCNERLY0_MB12INT_8814B BIT(4)
+#define BIT_FS_BCNERLY0_MB11INT_8814B BIT(3)
+#define BIT_FS_BCNERLY0_MB10INT_8814B BIT(2)
+#define BIT_FS_BCNERLY0_MB9INT_8814B BIT(1)
+#define BIT_FS_BCNERLY0_MB8INT_8814B BIT(0)
+
+/* 2 REG_FWIMR2_8814B */
+#define BIT_FS_BCNDMA0_MB15_INT_EN_8814B BIT(15)
+#define BIT_FS_BCNDMA0_MB14_INT_EN_8814B BIT(14)
+#define BIT_FS_BCNDMA0_MB13_INT_EN_8814B BIT(13)
+#define BIT_FS_BCNDMA0_MB12_INT_EN_8814B BIT(12)
+#define BIT_FS_BCNDMA0_MB11_INT_EN_8814B BIT(11)
+#define BIT_FS_BCNDMA0_MB10_INT_EN_8814B BIT(10)
+#define BIT_FS_BCNDMA0_MB9_INT_EN_8814B BIT(9)
+#define BIT_FS_BCNDMA0_MB8_INT_EN_8814B BIT(8)
+#define BIT_FS_TBTT0_MB15INT_EN_8814B BIT(7)
+#define BIT_FS_TBTT0_MB14INT_EN_8814B BIT(6)
+#define BIT_FS_TBTT0_MB13INT_EN_8814B BIT(5)
+#define BIT_FS_TBTT0_MB12INT_EN_8814B BIT(4)
+#define BIT_FS_TBTT0_MB11INT_EN_8814B BIT(3)
+#define BIT_FS_TBTT0_MB10INT_EN_8814B BIT(2)
+#define BIT_FS_TBTT0_MB9INT_EN_8814B BIT(1)
+#define BIT_FS_TBTT0_MB8INT_EN_8814B BIT(0)
+
+/* 2 REG_FWISR2_8814B */
+#define BIT_FS_BCNDMA0_MB15_INT_8814B BIT(15)
+#define BIT_FS_BCNDMA0_MB14_INT_8814B BIT(14)
+#define BIT_FS_BCNDMA0_MB13_INT_8814B BIT(13)
+#define BIT_FS_BCNDMA0_MB12_INT_8814B BIT(12)
+#define BIT_FS_BCNDMA0_MB11_INT_8814B BIT(11)
+#define BIT_FS_BCNDMA0_MB10_INT_8814B BIT(10)
+#define BIT_FS_BCNDMA0_MB9_INT_8814B BIT(9)
+#define BIT_FS_BCNDMA0_MB8_INT_8814B BIT(8)
+#define BIT_FS_TBTT0_MB15INT_8814B BIT(7)
+#define BIT_FS_TBTT0_MB14INT_8814B BIT(6)
+#define BIT_FS_TBTT0_MB13INT_8814B BIT(5)
+#define BIT_FS_TBTT0_MB12INT_8814B BIT(4)
+#define BIT_FS_TBTT0_MB11INT_8814B BIT(3)
+#define BIT_FS_TBTT0_MB10INT_8814B BIT(2)
+#define BIT_FS_TBTT0_MB9INT_8814B BIT(1)
+#define BIT_FS_TBTT0_MB8INT_8814B BIT(0)
+
+/* 2 REG_FWIMR3_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+#define BIT_FS_TXBCNOK_PORT4_INT_EN_8814B BIT(11)
+#define BIT_FS_TXBCNOK_PORT3_INT_EN_8814B BIT(10)
+#define BIT_FS_TXBCNOK_PORT2_INT_EN_8814B BIT(9)
+#define BIT_FS_TXBCNOK_PORT1_INT_EN_8814B BIT(8)
+#define BIT_FS_TXBCNERR_PORT4_INT_EN_8814B BIT(7)
+#define BIT_FS_TXBCNERR_PORT3_INT_EN_8814B BIT(6)
+#define BIT_FS_TXBCNERR_PORT2_INT_EN_8814B BIT(5)
+#define BIT_FS_TXBCNERR_PORT1_INT_EN_8814B BIT(4)
+#define BIT_FS_ATIM_PORT4_INT_EN_8814B BIT(3)
+#define BIT_FS_ATIM_PORT3_INT_EN_8814B BIT(2)
+#define BIT_FS_ATIM_PORT2_INT_EN_8814B BIT(1)
+#define BIT_FS_ATIM_PORT1_INT_EN_8814B BIT(0)
+
+/* 2 REG_FWISR3_8814B */
+#define BIT_FS_TXBCNOK_PORT4_INT_8814B BIT(11)
+#define BIT_FS_TXBCNOK_PORT3_INT_8814B BIT(10)
+#define BIT_FS_TXBCNOK_PORT2_INT_8814B BIT(9)
+#define BIT_FS_TXBCNOK_PORT1_INT_8814B BIT(8)
+#define BIT_FS_TXBCNERR_PORT4_INT_8814B BIT(7)
+#define BIT_FS_TXBCNERR_PORT3_INT_8814B BIT(6)
+#define BIT_FS_TXBCNERR_PORT2_INT_8814B BIT(5)
+#define BIT_FS_TXBCNERR_PORT1_INT_8814B BIT(4)
+#define BIT_FS_ATIM_PORT4_INT_8814B BIT(3)
+#define BIT_FS_ATIM_PORT3_INT_8814B BIT(2)
+#define BIT_FS_ATIM_PORT2_INT_8814B BIT(1)
+#define BIT_FS_ATIM_PORT1_INT_8814B BIT(0)
+
+/* 2 REG_SPEED_SENSOR_8814B */
+#define BIT_DSS_1_RST_N_8814B BIT(31)
+#define BIT_DSS_1_SPEED_EN_8814B BIT(30)
+#define BIT_DSS_1_WIRE_SEL_8814B BIT(29)
+#define BIT_DSS_ENCLK_8814B BIT(28)
+
+#define BIT_SHIFT_DSS_1_RO_SEL_8814B 24
+#define BIT_MASK_DSS_1_RO_SEL_8814B 0x7
+#define BIT_DSS_1_RO_SEL_8814B(x)                                              \
+	(((x) & BIT_MASK_DSS_1_RO_SEL_8814B) << BIT_SHIFT_DSS_1_RO_SEL_8814B)
+#define BITS_DSS_1_RO_SEL_8814B                                                \
+	(BIT_MASK_DSS_1_RO_SEL_8814B << BIT_SHIFT_DSS_1_RO_SEL_8814B)
+#define BIT_CLEAR_DSS_1_RO_SEL_8814B(x) ((x) & (~BITS_DSS_1_RO_SEL_8814B))
+#define BIT_GET_DSS_1_RO_SEL_8814B(x)                                          \
+	(((x) >> BIT_SHIFT_DSS_1_RO_SEL_8814B) & BIT_MASK_DSS_1_RO_SEL_8814B)
+#define BIT_SET_DSS_1_RO_SEL_8814B(x, v)                                       \
+	(BIT_CLEAR_DSS_1_RO_SEL_8814B(x) | BIT_DSS_1_RO_SEL_8814B(v))
+
+#define BIT_SHIFT_DSS_1_DATA_IN_8814B 0
+#define BIT_MASK_DSS_1_DATA_IN_8814B 0xfffff
+#define BIT_DSS_1_DATA_IN_8814B(x)                                             \
+	(((x) & BIT_MASK_DSS_1_DATA_IN_8814B) << BIT_SHIFT_DSS_1_DATA_IN_8814B)
+#define BITS_DSS_1_DATA_IN_8814B                                               \
+	(BIT_MASK_DSS_1_DATA_IN_8814B << BIT_SHIFT_DSS_1_DATA_IN_8814B)
+#define BIT_CLEAR_DSS_1_DATA_IN_8814B(x) ((x) & (~BITS_DSS_1_DATA_IN_8814B))
+#define BIT_GET_DSS_1_DATA_IN_8814B(x)                                         \
+	(((x) >> BIT_SHIFT_DSS_1_DATA_IN_8814B) & BIT_MASK_DSS_1_DATA_IN_8814B)
+#define BIT_SET_DSS_1_DATA_IN_8814B(x, v)                                      \
+	(BIT_CLEAR_DSS_1_DATA_IN_8814B(x) | BIT_DSS_1_DATA_IN_8814B(v))
+
+/* 2 REG_SPEED_SENSOR1_8814B */
+#define BIT_DSS_1_READY_8814B BIT(31)
+#define BIT_DSS_1_WSORT_GO_8814B BIT(30)
+
+#define BIT_SHIFT_DSS_1_COUNT_OUT_8814B 0
+#define BIT_MASK_DSS_1_COUNT_OUT_8814B 0xfffff
+#define BIT_DSS_1_COUNT_OUT_8814B(x)                                           \
+	(((x) & BIT_MASK_DSS_1_COUNT_OUT_8814B)                                \
+	 << BIT_SHIFT_DSS_1_COUNT_OUT_8814B)
+#define BITS_DSS_1_COUNT_OUT_8814B                                             \
+	(BIT_MASK_DSS_1_COUNT_OUT_8814B << BIT_SHIFT_DSS_1_COUNT_OUT_8814B)
+#define BIT_CLEAR_DSS_1_COUNT_OUT_8814B(x) ((x) & (~BITS_DSS_1_COUNT_OUT_8814B))
+#define BIT_GET_DSS_1_COUNT_OUT_8814B(x)                                       \
+	(((x) >> BIT_SHIFT_DSS_1_COUNT_OUT_8814B) &                            \
+	 BIT_MASK_DSS_1_COUNT_OUT_8814B)
+#define BIT_SET_DSS_1_COUNT_OUT_8814B(x, v)                                    \
+	(BIT_CLEAR_DSS_1_COUNT_OUT_8814B(x) | BIT_DSS_1_COUNT_OUT_8814B(v))
+
+/* 2 REG_SPEED_SENSOR2_8814B */
+#define BIT_DSS_2_RST_N_8814B BIT(31)
+#define BIT_DSS_2_SPEED_EN_8814B BIT(30)
+#define BIT_DSS_2_WIRE_SEL_8814B BIT(29)
+#define BIT_DSS_ENCLK_8814B BIT(28)
+
+#define BIT_SHIFT_DSS_2_RO_SEL_8814B 24
+#define BIT_MASK_DSS_2_RO_SEL_8814B 0x7
+#define BIT_DSS_2_RO_SEL_8814B(x)                                              \
+	(((x) & BIT_MASK_DSS_2_RO_SEL_8814B) << BIT_SHIFT_DSS_2_RO_SEL_8814B)
+#define BITS_DSS_2_RO_SEL_8814B                                                \
+	(BIT_MASK_DSS_2_RO_SEL_8814B << BIT_SHIFT_DSS_2_RO_SEL_8814B)
+#define BIT_CLEAR_DSS_2_RO_SEL_8814B(x) ((x) & (~BITS_DSS_2_RO_SEL_8814B))
+#define BIT_GET_DSS_2_RO_SEL_8814B(x)                                          \
+	(((x) >> BIT_SHIFT_DSS_2_RO_SEL_8814B) & BIT_MASK_DSS_2_RO_SEL_8814B)
+#define BIT_SET_DSS_2_RO_SEL_8814B(x, v)                                       \
+	(BIT_CLEAR_DSS_2_RO_SEL_8814B(x) | BIT_DSS_2_RO_SEL_8814B(v))
+
+#define BIT_SHIFT_DSS_2_DATA_IN_8814B 0
+#define BIT_MASK_DSS_2_DATA_IN_8814B 0xfffff
+#define BIT_DSS_2_DATA_IN_8814B(x)                                             \
+	(((x) & BIT_MASK_DSS_2_DATA_IN_8814B) << BIT_SHIFT_DSS_2_DATA_IN_8814B)
+#define BITS_DSS_2_DATA_IN_8814B                                               \
+	(BIT_MASK_DSS_2_DATA_IN_8814B << BIT_SHIFT_DSS_2_DATA_IN_8814B)
+#define BIT_CLEAR_DSS_2_DATA_IN_8814B(x) ((x) & (~BITS_DSS_2_DATA_IN_8814B))
+#define BIT_GET_DSS_2_DATA_IN_8814B(x)                                         \
+	(((x) >> BIT_SHIFT_DSS_2_DATA_IN_8814B) & BIT_MASK_DSS_2_DATA_IN_8814B)
+#define BIT_SET_DSS_2_DATA_IN_8814B(x, v)                                      \
+	(BIT_CLEAR_DSS_2_DATA_IN_8814B(x) | BIT_DSS_2_DATA_IN_8814B(v))
+
+/* 2 REG_SPEED_SENSOR3_8814B */
+#define BIT_DSS_2_READY_8814B BIT(31)
+#define BIT_DSS_2_WSORT_GO_8814B BIT(30)
+
+#define BIT_SHIFT_DSS_2_COUNT_OUT_8814B 0
+#define BIT_MASK_DSS_2_COUNT_OUT_8814B 0xfffff
+#define BIT_DSS_2_COUNT_OUT_8814B(x)                                           \
+	(((x) & BIT_MASK_DSS_2_COUNT_OUT_8814B)                                \
+	 << BIT_SHIFT_DSS_2_COUNT_OUT_8814B)
+#define BITS_DSS_2_COUNT_OUT_8814B                                             \
+	(BIT_MASK_DSS_2_COUNT_OUT_8814B << BIT_SHIFT_DSS_2_COUNT_OUT_8814B)
+#define BIT_CLEAR_DSS_2_COUNT_OUT_8814B(x) ((x) & (~BITS_DSS_2_COUNT_OUT_8814B))
+#define BIT_GET_DSS_2_COUNT_OUT_8814B(x)                                       \
+	(((x) >> BIT_SHIFT_DSS_2_COUNT_OUT_8814B) &                            \
+	 BIT_MASK_DSS_2_COUNT_OUT_8814B)
+#define BIT_SET_DSS_2_COUNT_OUT_8814B(x, v)                                    \
+	(BIT_CLEAR_DSS_2_COUNT_OUT_8814B(x) | BIT_DSS_2_COUNT_OUT_8814B(v))
+
+/* 2 REG_SPEED_SENSOR4_8814B */
+#define BIT_DSS_3_RST_N_8814B BIT(31)
+#define BIT_DSS_3_SPEED_EN_8814B BIT(30)
+#define BIT_DSS_3_WIRE_SEL_8814B BIT(29)
+#define BIT_DSS_ENCLK_8814B BIT(28)
+
+#define BIT_SHIFT_DSS_3_RO_SEL_8814B 24
+#define BIT_MASK_DSS_3_RO_SEL_8814B 0x7
+#define BIT_DSS_3_RO_SEL_8814B(x)                                              \
+	(((x) & BIT_MASK_DSS_3_RO_SEL_8814B) << BIT_SHIFT_DSS_3_RO_SEL_8814B)
+#define BITS_DSS_3_RO_SEL_8814B                                                \
+	(BIT_MASK_DSS_3_RO_SEL_8814B << BIT_SHIFT_DSS_3_RO_SEL_8814B)
+#define BIT_CLEAR_DSS_3_RO_SEL_8814B(x) ((x) & (~BITS_DSS_3_RO_SEL_8814B))
+#define BIT_GET_DSS_3_RO_SEL_8814B(x)                                          \
+	(((x) >> BIT_SHIFT_DSS_3_RO_SEL_8814B) & BIT_MASK_DSS_3_RO_SEL_8814B)
+#define BIT_SET_DSS_3_RO_SEL_8814B(x, v)                                       \
+	(BIT_CLEAR_DSS_3_RO_SEL_8814B(x) | BIT_DSS_3_RO_SEL_8814B(v))
+
+#define BIT_SHIFT_DSS_3_DATA_IN_8814B 0
+#define BIT_MASK_DSS_3_DATA_IN_8814B 0xfffff
+#define BIT_DSS_3_DATA_IN_8814B(x)                                             \
+	(((x) & BIT_MASK_DSS_3_DATA_IN_8814B) << BIT_SHIFT_DSS_3_DATA_IN_8814B)
+#define BITS_DSS_3_DATA_IN_8814B                                               \
+	(BIT_MASK_DSS_3_DATA_IN_8814B << BIT_SHIFT_DSS_3_DATA_IN_8814B)
+#define BIT_CLEAR_DSS_3_DATA_IN_8814B(x) ((x) & (~BITS_DSS_3_DATA_IN_8814B))
+#define BIT_GET_DSS_3_DATA_IN_8814B(x)                                         \
+	(((x) >> BIT_SHIFT_DSS_3_DATA_IN_8814B) & BIT_MASK_DSS_3_DATA_IN_8814B)
+#define BIT_SET_DSS_3_DATA_IN_8814B(x, v)                                      \
+	(BIT_CLEAR_DSS_3_DATA_IN_8814B(x) | BIT_DSS_3_DATA_IN_8814B(v))
+
+/* 2 REG_SPEED_SENSOR5_8814B */
+#define BIT_DSS_3_READY_8814B BIT(31)
+#define BIT_DSS_3_WSORT_GO_8814B BIT(30)
+
+#define BIT_SHIFT_DSS_3_COUNT_OUT_8814B 0
+#define BIT_MASK_DSS_3_COUNT_OUT_8814B 0xfffff
+#define BIT_DSS_3_COUNT_OUT_8814B(x)                                           \
+	(((x) & BIT_MASK_DSS_3_COUNT_OUT_8814B)                                \
+	 << BIT_SHIFT_DSS_3_COUNT_OUT_8814B)
+#define BITS_DSS_3_COUNT_OUT_8814B                                             \
+	(BIT_MASK_DSS_3_COUNT_OUT_8814B << BIT_SHIFT_DSS_3_COUNT_OUT_8814B)
+#define BIT_CLEAR_DSS_3_COUNT_OUT_8814B(x) ((x) & (~BITS_DSS_3_COUNT_OUT_8814B))
+#define BIT_GET_DSS_3_COUNT_OUT_8814B(x)                                       \
+	(((x) >> BIT_SHIFT_DSS_3_COUNT_OUT_8814B) &                            \
+	 BIT_MASK_DSS_3_COUNT_OUT_8814B)
+#define BIT_SET_DSS_3_COUNT_OUT_8814B(x, v)                                    \
+	(BIT_CLEAR_DSS_3_COUNT_OUT_8814B(x) | BIT_DSS_3_COUNT_OUT_8814B(v))
+
+/* 2 REG_RXPKTBUF_1_MAX_ADDR_8814B */
+
+#define BIT_SHIFT_RXPKTBUF_SIZE_8814B 30
+#define BIT_MASK_RXPKTBUF_SIZE_8814B 0x3
+#define BIT_RXPKTBUF_SIZE_8814B(x)                                             \
+	(((x) & BIT_MASK_RXPKTBUF_SIZE_8814B) << BIT_SHIFT_RXPKTBUF_SIZE_8814B)
+#define BITS_RXPKTBUF_SIZE_8814B                                               \
+	(BIT_MASK_RXPKTBUF_SIZE_8814B << BIT_SHIFT_RXPKTBUF_SIZE_8814B)
+#define BIT_CLEAR_RXPKTBUF_SIZE_8814B(x) ((x) & (~BITS_RXPKTBUF_SIZE_8814B))
+#define BIT_GET_RXPKTBUF_SIZE_8814B(x)                                         \
+	(((x) >> BIT_SHIFT_RXPKTBUF_SIZE_8814B) & BIT_MASK_RXPKTBUF_SIZE_8814B)
+#define BIT_SET_RXPKTBUF_SIZE_8814B(x, v)                                      \
+	(BIT_CLEAR_RXPKTBUF_SIZE_8814B(x) | BIT_RXPKTBUF_SIZE_8814B(v))
+
+#define BIT_RXPKTBUF_DBG_SEL_8814B BIT(29)
+
+#define BIT_SHIFT_RXPKTBUF_1_MAX_ADDR_8814B 0
+#define BIT_MASK_RXPKTBUF_1_MAX_ADDR_8814B 0x3ffff
+#define BIT_RXPKTBUF_1_MAX_ADDR_8814B(x)                                       \
+	(((x) & BIT_MASK_RXPKTBUF_1_MAX_ADDR_8814B)                            \
+	 << BIT_SHIFT_RXPKTBUF_1_MAX_ADDR_8814B)
+#define BITS_RXPKTBUF_1_MAX_ADDR_8814B                                         \
+	(BIT_MASK_RXPKTBUF_1_MAX_ADDR_8814B                                    \
+	 << BIT_SHIFT_RXPKTBUF_1_MAX_ADDR_8814B)
+#define BIT_CLEAR_RXPKTBUF_1_MAX_ADDR_8814B(x)                                 \
+	((x) & (~BITS_RXPKTBUF_1_MAX_ADDR_8814B))
+#define BIT_GET_RXPKTBUF_1_MAX_ADDR_8814B(x)                                   \
+	(((x) >> BIT_SHIFT_RXPKTBUF_1_MAX_ADDR_8814B) &                        \
+	 BIT_MASK_RXPKTBUF_1_MAX_ADDR_8814B)
+#define BIT_SET_RXPKTBUF_1_MAX_ADDR_8814B(x, v)                                \
+	(BIT_CLEAR_RXPKTBUF_1_MAX_ADDR_8814B(x) |                              \
+	 BIT_RXPKTBUF_1_MAX_ADDR_8814B(v))
+
+/* 2 REG_RXFWBUF_1_MAX_ADDR_8814B */
+
+#define BIT_SHIFT_RXFWBUF_1_MAX_ADDR_8814B 0
+#define BIT_MASK_RXFWBUF_1_MAX_ADDR_8814B 0xffff
+#define BIT_RXFWBUF_1_MAX_ADDR_8814B(x)                                        \
+	(((x) & BIT_MASK_RXFWBUF_1_MAX_ADDR_8814B)                             \
+	 << BIT_SHIFT_RXFWBUF_1_MAX_ADDR_8814B)
+#define BITS_RXFWBUF_1_MAX_ADDR_8814B                                          \
+	(BIT_MASK_RXFWBUF_1_MAX_ADDR_8814B                                     \
+	 << BIT_SHIFT_RXFWBUF_1_MAX_ADDR_8814B)
+#define BIT_CLEAR_RXFWBUF_1_MAX_ADDR_8814B(x)                                  \
+	((x) & (~BITS_RXFWBUF_1_MAX_ADDR_8814B))
+#define BIT_GET_RXFWBUF_1_MAX_ADDR_8814B(x)                                    \
+	(((x) >> BIT_SHIFT_RXFWBUF_1_MAX_ADDR_8814B) &                         \
+	 BIT_MASK_RXFWBUF_1_MAX_ADDR_8814B)
+#define BIT_SET_RXFWBUF_1_MAX_ADDR_8814B(x, v)                                 \
+	(BIT_CLEAR_RXFWBUF_1_MAX_ADDR_8814B(x) |                               \
+	 BIT_RXFWBUF_1_MAX_ADDR_8814B(v))
+
+/* 2 REG_IO_WRAP_ERR_FLAG_V1_8814B */
+#define BIT_IO_WRAP_ERR_8814B BIT(0)
+
+/* 2 REG_RXPKTBUF_1_READ_8814B */
+
+#define BIT_SHIFT_RXPKTBUF_1_READ_8814B 0
+#define BIT_MASK_RXPKTBUF_1_READ_8814B 0x3ffff
+#define BIT_RXPKTBUF_1_READ_8814B(x)                                           \
+	(((x) & BIT_MASK_RXPKTBUF_1_READ_8814B)                                \
+	 << BIT_SHIFT_RXPKTBUF_1_READ_8814B)
+#define BITS_RXPKTBUF_1_READ_8814B                                             \
+	(BIT_MASK_RXPKTBUF_1_READ_8814B << BIT_SHIFT_RXPKTBUF_1_READ_8814B)
+#define BIT_CLEAR_RXPKTBUF_1_READ_8814B(x) ((x) & (~BITS_RXPKTBUF_1_READ_8814B))
+#define BIT_GET_RXPKTBUF_1_READ_8814B(x)                                       \
+	(((x) >> BIT_SHIFT_RXPKTBUF_1_READ_8814B) &                            \
+	 BIT_MASK_RXPKTBUF_1_READ_8814B)
+#define BIT_SET_RXPKTBUF_1_READ_8814B(x, v)                                    \
+	(BIT_CLEAR_RXPKTBUF_1_READ_8814B(x) | BIT_RXPKTBUF_1_READ_8814B(v))
+
+/* 2 REG_RXPKTBUF_1_WRITE_8814B */
+
+#define BIT_SHIFT_RXPKTBUF_1_WRITE_8814B 0
+#define BIT_MASK_RXPKTBUF_1_WRITE_8814B 0x3ffff
+#define BIT_RXPKTBUF_1_WRITE_8814B(x)                                          \
+	(((x) & BIT_MASK_RXPKTBUF_1_WRITE_8814B)                               \
+	 << BIT_SHIFT_RXPKTBUF_1_WRITE_8814B)
+#define BITS_RXPKTBUF_1_WRITE_8814B                                            \
+	(BIT_MASK_RXPKTBUF_1_WRITE_8814B << BIT_SHIFT_RXPKTBUF_1_WRITE_8814B)
+#define BIT_CLEAR_RXPKTBUF_1_WRITE_8814B(x)                                    \
+	((x) & (~BITS_RXPKTBUF_1_WRITE_8814B))
+#define BIT_GET_RXPKTBUF_1_WRITE_8814B(x)                                      \
+	(((x) >> BIT_SHIFT_RXPKTBUF_1_WRITE_8814B) &                           \
+	 BIT_MASK_RXPKTBUF_1_WRITE_8814B)
+#define BIT_SET_RXPKTBUF_1_WRITE_8814B(x, v)                                   \
+	(BIT_CLEAR_RXPKTBUF_1_WRITE_8814B(x) | BIT_RXPKTBUF_1_WRITE_8814B(v))
+
+/* 2 REG_BUFF_DBGUG_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+#define BIT_SHIFT_R_OQT_DBG_SEL_8814B 16
+#define BIT_MASK_R_OQT_DBG_SEL_8814B 0xff
+#define BIT_R_OQT_DBG_SEL_8814B(x)                                             \
+	(((x) & BIT_MASK_R_OQT_DBG_SEL_8814B) << BIT_SHIFT_R_OQT_DBG_SEL_8814B)
+#define BITS_R_OQT_DBG_SEL_8814B                                               \
+	(BIT_MASK_R_OQT_DBG_SEL_8814B << BIT_SHIFT_R_OQT_DBG_SEL_8814B)
+#define BIT_CLEAR_R_OQT_DBG_SEL_8814B(x) ((x) & (~BITS_R_OQT_DBG_SEL_8814B))
+#define BIT_GET_R_OQT_DBG_SEL_8814B(x)                                         \
+	(((x) >> BIT_SHIFT_R_OQT_DBG_SEL_8814B) & BIT_MASK_R_OQT_DBG_SEL_8814B)
+#define BIT_SET_R_OQT_DBG_SEL_8814B(x, v)                                      \
+	(BIT_CLEAR_R_OQT_DBG_SEL_8814B(x) | BIT_R_OQT_DBG_SEL_8814B(v))
+
+#define BIT_SHIFT_R_TXPKTBF_DBG_SEL_8814B 8
+#define BIT_MASK_R_TXPKTBF_DBG_SEL_8814B 0x7
+#define BIT_R_TXPKTBF_DBG_SEL_8814B(x)                                         \
+	(((x) & BIT_MASK_R_TXPKTBF_DBG_SEL_8814B)                              \
+	 << BIT_SHIFT_R_TXPKTBF_DBG_SEL_8814B)
+#define BITS_R_TXPKTBF_DBG_SEL_8814B                                           \
+	(BIT_MASK_R_TXPKTBF_DBG_SEL_8814B << BIT_SHIFT_R_TXPKTBF_DBG_SEL_8814B)
+#define BIT_CLEAR_R_TXPKTBF_DBG_SEL_8814B(x)                                   \
+	((x) & (~BITS_R_TXPKTBF_DBG_SEL_8814B))
+#define BIT_GET_R_TXPKTBF_DBG_SEL_8814B(x)                                     \
+	(((x) >> BIT_SHIFT_R_TXPKTBF_DBG_SEL_8814B) &                          \
+	 BIT_MASK_R_TXPKTBF_DBG_SEL_8814B)
+#define BIT_SET_R_TXPKTBF_DBG_SEL_8814B(x, v)                                  \
+	(BIT_CLEAR_R_TXPKTBF_DBG_SEL_8814B(x) | BIT_R_TXPKTBF_DBG_SEL_8814B(v))
+
+#define BIT_SHIFT_R_RXPKT_DBG_SEL_8814B 6
+#define BIT_MASK_R_RXPKT_DBG_SEL_8814B 0x3
+#define BIT_R_RXPKT_DBG_SEL_8814B(x)                                           \
+	(((x) & BIT_MASK_R_RXPKT_DBG_SEL_8814B)                                \
+	 << BIT_SHIFT_R_RXPKT_DBG_SEL_8814B)
+#define BITS_R_RXPKT_DBG_SEL_8814B                                             \
+	(BIT_MASK_R_RXPKT_DBG_SEL_8814B << BIT_SHIFT_R_RXPKT_DBG_SEL_8814B)
+#define BIT_CLEAR_R_RXPKT_DBG_SEL_8814B(x) ((x) & (~BITS_R_RXPKT_DBG_SEL_8814B))
+#define BIT_GET_R_RXPKT_DBG_SEL_8814B(x)                                       \
+	(((x) >> BIT_SHIFT_R_RXPKT_DBG_SEL_8814B) &                            \
+	 BIT_MASK_R_RXPKT_DBG_SEL_8814B)
+#define BIT_SET_R_RXPKT_DBG_SEL_8814B(x, v)                                    \
+	(BIT_CLEAR_R_RXPKT_DBG_SEL_8814B(x) | BIT_R_RXPKT_DBG_SEL_8814B(v))
+
+#define BIT_SHIFT_R_RXPKTBF_DBG_SEL_8814B 0
+#define BIT_MASK_R_RXPKTBF_DBG_SEL_8814B 0x3
+#define BIT_R_RXPKTBF_DBG_SEL_8814B(x)                                         \
+	(((x) & BIT_MASK_R_RXPKTBF_DBG_SEL_8814B)                              \
+	 << BIT_SHIFT_R_RXPKTBF_DBG_SEL_8814B)
+#define BITS_R_RXPKTBF_DBG_SEL_8814B                                           \
+	(BIT_MASK_R_RXPKTBF_DBG_SEL_8814B << BIT_SHIFT_R_RXPKTBF_DBG_SEL_8814B)
+#define BIT_CLEAR_R_RXPKTBF_DBG_SEL_8814B(x)                                   \
+	((x) & (~BITS_R_RXPKTBF_DBG_SEL_8814B))
+#define BIT_GET_R_RXPKTBF_DBG_SEL_8814B(x)                                     \
+	(((x) >> BIT_SHIFT_R_RXPKTBF_DBG_SEL_8814B) &                          \
+	 BIT_MASK_R_RXPKTBF_DBG_SEL_8814B)
+#define BIT_SET_R_RXPKTBF_DBG_SEL_8814B(x, v)                                  \
+	(BIT_CLEAR_R_RXPKTBF_DBG_SEL_8814B(x) | BIT_R_RXPKTBF_DBG_SEL_8814B(v))
+
+/* 2 REG_RFE_CTRL_PAD_E2_8814B */
+#define BIT_RFE_CTRL_ANTSW_E2_8814B BIT(16)
+#define BIT_RFE_CTRL_PIN15_E2_8814B BIT(15)
+#define BIT_RFE_CTRL_PIN14_E2_8814B BIT(14)
+#define BIT_RFE_CTRL_PIN13_E2_8814B BIT(13)
+#define BIT_RFE_CTRL_PIN12_E2_8814B BIT(12)
+#define BIT_RFE_CTRL_PIN11_E2_8814B BIT(11)
+#define BIT_RFE_CTRL_PIN10_E2_8814B BIT(10)
+#define BIT_RFE_CTRL_PIN9_E2_8814B BIT(9)
+#define BIT_RFE_CTRL_PIN8_E2_8814B BIT(8)
+#define BIT_RFE_CTRL_PIN7_E2_8814B BIT(7)
+#define BIT_RFE_CTRL_PIN6_E2_8814B BIT(6)
+#define BIT_RFE_CTRL_PIN5_E2_8814B BIT(5)
+#define BIT_RFE_CTRL_PIN4_E2_8814B BIT(4)
+#define BIT_RFE_CTRL_PIN3_E2_8814B BIT(3)
+#define BIT_RFE_CTRL_PIN2_E2_8814B BIT(2)
+#define BIT_RFE_CTRL_PIN1_E2_8814B BIT(1)
+#define BIT_RFE_CTRL_PIN0_E2_8814B BIT(0)
+
+/* 2 REG_RFE_CTRL_PAD_SR_8814B */
+#define BIT_RFE_CTRL_ANTSW_SR_8814B BIT(16)
+#define BIT_RFE_CTRL_PIN15_SR_8814B BIT(15)
+#define BIT_RFE_CTRL_PIN14_SR_8814B BIT(14)
+#define BIT_RFE_CTRL_PIN13_SR_8814B BIT(13)
+#define BIT_RFE_CTRL_PIN12_SR_8814B BIT(12)
+#define BIT_RFE_CTRL_PIN11_SR_8814B BIT(11)
+#define BIT_RFE_CTRL_PIN10_SR_8814B BIT(10)
+#define BIT_RFE_CTRL_PIN9_SR_8814B BIT(9)
+#define BIT_RFE_CTRL_PIN8_SR_8814B BIT(8)
+#define BIT_RFE_CTRL_PIN7_SR_8814B BIT(7)
+#define BIT_RFE_CTRL_PIN6_SR_8814B BIT(6)
+#define BIT_RFE_CTRL_PIN5_SR_8814B BIT(5)
+#define BIT_RFE_CTRL_PIN4_SR_8814B BIT(4)
+#define BIT_RFE_CTRL_PIN3_SR_8814B BIT(3)
+#define BIT_RFE_CTRL_PIN2_SR_8814B BIT(2)
+#define BIT_RFE_CTRL_PIN1_SR_8814B BIT(1)
+#define BIT_RFE_CTRL_PIN0_SR_8814B BIT(0)
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_H2C_PRIORITY_SEL_8814B */
+
+#define BIT_SHIFT_H2C_PRIORITY_SEL_8814B 0
+#define BIT_MASK_H2C_PRIORITY_SEL_8814B 0x3
+#define BIT_H2C_PRIORITY_SEL_8814B(x)                                          \
+	(((x) & BIT_MASK_H2C_PRIORITY_SEL_8814B)                               \
+	 << BIT_SHIFT_H2C_PRIORITY_SEL_8814B)
+#define BITS_H2C_PRIORITY_SEL_8814B                                            \
+	(BIT_MASK_H2C_PRIORITY_SEL_8814B << BIT_SHIFT_H2C_PRIORITY_SEL_8814B)
+#define BIT_CLEAR_H2C_PRIORITY_SEL_8814B(x)                                    \
+	((x) & (~BITS_H2C_PRIORITY_SEL_8814B))
+#define BIT_GET_H2C_PRIORITY_SEL_8814B(x)                                      \
+	(((x) >> BIT_SHIFT_H2C_PRIORITY_SEL_8814B) &                           \
+	 BIT_MASK_H2C_PRIORITY_SEL_8814B)
+#define BIT_SET_H2C_PRIORITY_SEL_8814B(x, v)                                   \
+	(BIT_CLEAR_H2C_PRIORITY_SEL_8814B(x) | BIT_H2C_PRIORITY_SEL_8814B(v))
+
+/* 2 REG_COUNTER_CTRL_8814B */
+
+#define BIT_SHIFT_COUNTER_BASE_8814B 16
+#define BIT_MASK_COUNTER_BASE_8814B 0x1fff
+#define BIT_COUNTER_BASE_8814B(x)                                              \
+	(((x) & BIT_MASK_COUNTER_BASE_8814B) << BIT_SHIFT_COUNTER_BASE_8814B)
+#define BITS_COUNTER_BASE_8814B                                                \
+	(BIT_MASK_COUNTER_BASE_8814B << BIT_SHIFT_COUNTER_BASE_8814B)
+#define BIT_CLEAR_COUNTER_BASE_8814B(x) ((x) & (~BITS_COUNTER_BASE_8814B))
+#define BIT_GET_COUNTER_BASE_8814B(x)                                          \
+	(((x) >> BIT_SHIFT_COUNTER_BASE_8814B) & BIT_MASK_COUNTER_BASE_8814B)
+#define BIT_SET_COUNTER_BASE_8814B(x, v)                                       \
+	(BIT_CLEAR_COUNTER_BASE_8814B(x) | BIT_COUNTER_BASE_8814B(v))
+
+#define BIT_EN_RTS_REQ_8814B BIT(9)
+#define BIT_EN_EDCA_REQ_8814B BIT(8)
+#define BIT_EN_PTCL_REQ_8814B BIT(7)
+#define BIT_EN_SCH_REQ_8814B BIT(6)
+#define BIT_USB_COUNT_EN_8814B BIT(5)
+#define BIT_PCIE_COUNT_EN_8814B BIT(4)
+#define BIT_RQPN_COUNT_EN_8814B BIT(3)
+#define BIT_RDE_COUNT_EN_8814B BIT(2)
+#define BIT_TDE_COUNT_EN_8814B BIT(1)
+#define BIT_DISABLE_COUNTER_8814B BIT(0)
+
+/* 2 REG_COUNTER_THRESHOLD_8814B */
+#define BIT_SEL_ALL_MACID_8814B BIT(31)
+
+#define BIT_SHIFT_COUNTER_MACID_8814B 24
+#define BIT_MASK_COUNTER_MACID_8814B 0x7f
+#define BIT_COUNTER_MACID_8814B(x)                                             \
+	(((x) & BIT_MASK_COUNTER_MACID_8814B) << BIT_SHIFT_COUNTER_MACID_8814B)
+#define BITS_COUNTER_MACID_8814B                                               \
+	(BIT_MASK_COUNTER_MACID_8814B << BIT_SHIFT_COUNTER_MACID_8814B)
+#define BIT_CLEAR_COUNTER_MACID_8814B(x) ((x) & (~BITS_COUNTER_MACID_8814B))
+#define BIT_GET_COUNTER_MACID_8814B(x)                                         \
+	(((x) >> BIT_SHIFT_COUNTER_MACID_8814B) & BIT_MASK_COUNTER_MACID_8814B)
+#define BIT_SET_COUNTER_MACID_8814B(x, v)                                      \
+	(BIT_CLEAR_COUNTER_MACID_8814B(x) | BIT_COUNTER_MACID_8814B(v))
+
+#define BIT_SHIFT_AGG_VALUE2_8814B 16
+#define BIT_MASK_AGG_VALUE2_8814B 0x7f
+#define BIT_AGG_VALUE2_8814B(x)                                                \
+	(((x) & BIT_MASK_AGG_VALUE2_8814B) << BIT_SHIFT_AGG_VALUE2_8814B)
+#define BITS_AGG_VALUE2_8814B                                                  \
+	(BIT_MASK_AGG_VALUE2_8814B << BIT_SHIFT_AGG_VALUE2_8814B)
+#define BIT_CLEAR_AGG_VALUE2_8814B(x) ((x) & (~BITS_AGG_VALUE2_8814B))
+#define BIT_GET_AGG_VALUE2_8814B(x)                                            \
+	(((x) >> BIT_SHIFT_AGG_VALUE2_8814B) & BIT_MASK_AGG_VALUE2_8814B)
+#define BIT_SET_AGG_VALUE2_8814B(x, v)                                         \
+	(BIT_CLEAR_AGG_VALUE2_8814B(x) | BIT_AGG_VALUE2_8814B(v))
+
+#define BIT_SHIFT_AGG_VALUE1_8814B 8
+#define BIT_MASK_AGG_VALUE1_8814B 0x7f
+#define BIT_AGG_VALUE1_8814B(x)                                                \
+	(((x) & BIT_MASK_AGG_VALUE1_8814B) << BIT_SHIFT_AGG_VALUE1_8814B)
+#define BITS_AGG_VALUE1_8814B                                                  \
+	(BIT_MASK_AGG_VALUE1_8814B << BIT_SHIFT_AGG_VALUE1_8814B)
+#define BIT_CLEAR_AGG_VALUE1_8814B(x) ((x) & (~BITS_AGG_VALUE1_8814B))
+#define BIT_GET_AGG_VALUE1_8814B(x)                                            \
+	(((x) >> BIT_SHIFT_AGG_VALUE1_8814B) & BIT_MASK_AGG_VALUE1_8814B)
+#define BIT_SET_AGG_VALUE1_8814B(x, v)                                         \
+	(BIT_CLEAR_AGG_VALUE1_8814B(x) | BIT_AGG_VALUE1_8814B(v))
+
+#define BIT_SHIFT_AGG_VALUE0_8814B 0
+#define BIT_MASK_AGG_VALUE0_8814B 0x7f
+#define BIT_AGG_VALUE0_8814B(x)                                                \
+	(((x) & BIT_MASK_AGG_VALUE0_8814B) << BIT_SHIFT_AGG_VALUE0_8814B)
+#define BITS_AGG_VALUE0_8814B                                                  \
+	(BIT_MASK_AGG_VALUE0_8814B << BIT_SHIFT_AGG_VALUE0_8814B)
+#define BIT_CLEAR_AGG_VALUE0_8814B(x) ((x) & (~BITS_AGG_VALUE0_8814B))
+#define BIT_GET_AGG_VALUE0_8814B(x)                                            \
+	(((x) >> BIT_SHIFT_AGG_VALUE0_8814B) & BIT_MASK_AGG_VALUE0_8814B)
+#define BIT_SET_AGG_VALUE0_8814B(x, v)                                         \
+	(BIT_CLEAR_AGG_VALUE0_8814B(x) | BIT_AGG_VALUE0_8814B(v))
+
+/* 2 REG_COUNTER_SET_8814B */
+
+#define BIT_SHIFT_REQUEST_RESET_8814B 16
+#define BIT_MASK_REQUEST_RESET_8814B 0xffff
+#define BIT_REQUEST_RESET_8814B(x)                                             \
+	(((x) & BIT_MASK_REQUEST_RESET_8814B) << BIT_SHIFT_REQUEST_RESET_8814B)
+#define BITS_REQUEST_RESET_8814B                                               \
+	(BIT_MASK_REQUEST_RESET_8814B << BIT_SHIFT_REQUEST_RESET_8814B)
+#define BIT_CLEAR_REQUEST_RESET_8814B(x) ((x) & (~BITS_REQUEST_RESET_8814B))
+#define BIT_GET_REQUEST_RESET_8814B(x)                                         \
+	(((x) >> BIT_SHIFT_REQUEST_RESET_8814B) & BIT_MASK_REQUEST_RESET_8814B)
+#define BIT_SET_REQUEST_RESET_8814B(x, v)                                      \
+	(BIT_CLEAR_REQUEST_RESET_8814B(x) | BIT_REQUEST_RESET_8814B(v))
+
+#define BIT_SHIFT_REQUEST_START_8814B 0
+#define BIT_MASK_REQUEST_START_8814B 0xffff
+#define BIT_REQUEST_START_8814B(x)                                             \
+	(((x) & BIT_MASK_REQUEST_START_8814B) << BIT_SHIFT_REQUEST_START_8814B)
+#define BITS_REQUEST_START_8814B                                               \
+	(BIT_MASK_REQUEST_START_8814B << BIT_SHIFT_REQUEST_START_8814B)
+#define BIT_CLEAR_REQUEST_START_8814B(x) ((x) & (~BITS_REQUEST_START_8814B))
+#define BIT_GET_REQUEST_START_8814B(x)                                         \
+	(((x) >> BIT_SHIFT_REQUEST_START_8814B) & BIT_MASK_REQUEST_START_8814B)
+#define BIT_SET_REQUEST_START_8814B(x, v)                                      \
+	(BIT_CLEAR_REQUEST_START_8814B(x) | BIT_REQUEST_START_8814B(v))
+
+/* 2 REG_COUNTER_OVERFLOW_8814B */
+
+#define BIT_SHIFT_CNT_OVF_REG_8814B 0
+#define BIT_MASK_CNT_OVF_REG_8814B 0xffff
+#define BIT_CNT_OVF_REG_8814B(x)                                               \
+	(((x) & BIT_MASK_CNT_OVF_REG_8814B) << BIT_SHIFT_CNT_OVF_REG_8814B)
+#define BITS_CNT_OVF_REG_8814B                                                 \
+	(BIT_MASK_CNT_OVF_REG_8814B << BIT_SHIFT_CNT_OVF_REG_8814B)
+#define BIT_CLEAR_CNT_OVF_REG_8814B(x) ((x) & (~BITS_CNT_OVF_REG_8814B))
+#define BIT_GET_CNT_OVF_REG_8814B(x)                                           \
+	(((x) >> BIT_SHIFT_CNT_OVF_REG_8814B) & BIT_MASK_CNT_OVF_REG_8814B)
+#define BIT_SET_CNT_OVF_REG_8814B(x, v)                                        \
+	(BIT_CLEAR_CNT_OVF_REG_8814B(x) | BIT_CNT_OVF_REG_8814B(v))
+
+/* 2 REG_TXDMA_LEN_THRESHOLD_8814B */
+
+#define BIT_SHIFT_TDE_LEN_TH1_8814B 16
+#define BIT_MASK_TDE_LEN_TH1_8814B 0xffff
+#define BIT_TDE_LEN_TH1_8814B(x)                                               \
+	(((x) & BIT_MASK_TDE_LEN_TH1_8814B) << BIT_SHIFT_TDE_LEN_TH1_8814B)
+#define BITS_TDE_LEN_TH1_8814B                                                 \
+	(BIT_MASK_TDE_LEN_TH1_8814B << BIT_SHIFT_TDE_LEN_TH1_8814B)
+#define BIT_CLEAR_TDE_LEN_TH1_8814B(x) ((x) & (~BITS_TDE_LEN_TH1_8814B))
+#define BIT_GET_TDE_LEN_TH1_8814B(x)                                           \
+	(((x) >> BIT_SHIFT_TDE_LEN_TH1_8814B) & BIT_MASK_TDE_LEN_TH1_8814B)
+#define BIT_SET_TDE_LEN_TH1_8814B(x, v)                                        \
+	(BIT_CLEAR_TDE_LEN_TH1_8814B(x) | BIT_TDE_LEN_TH1_8814B(v))
+
+#define BIT_SHIFT_TDE_LEN_TH0_8814B 0
+#define BIT_MASK_TDE_LEN_TH0_8814B 0xffff
+#define BIT_TDE_LEN_TH0_8814B(x)                                               \
+	(((x) & BIT_MASK_TDE_LEN_TH0_8814B) << BIT_SHIFT_TDE_LEN_TH0_8814B)
+#define BITS_TDE_LEN_TH0_8814B                                                 \
+	(BIT_MASK_TDE_LEN_TH0_8814B << BIT_SHIFT_TDE_LEN_TH0_8814B)
+#define BIT_CLEAR_TDE_LEN_TH0_8814B(x) ((x) & (~BITS_TDE_LEN_TH0_8814B))
+#define BIT_GET_TDE_LEN_TH0_8814B(x)                                           \
+	(((x) >> BIT_SHIFT_TDE_LEN_TH0_8814B) & BIT_MASK_TDE_LEN_TH0_8814B)
+#define BIT_SET_TDE_LEN_TH0_8814B(x, v)                                        \
+	(BIT_CLEAR_TDE_LEN_TH0_8814B(x) | BIT_TDE_LEN_TH0_8814B(v))
+
+/* 2 REG_RXDMA_LEN_THRESHOLD_8814B */
+
+#define BIT_SHIFT_RDE_LEN_TH1_8814B 16
+#define BIT_MASK_RDE_LEN_TH1_8814B 0xffff
+#define BIT_RDE_LEN_TH1_8814B(x)                                               \
+	(((x) & BIT_MASK_RDE_LEN_TH1_8814B) << BIT_SHIFT_RDE_LEN_TH1_8814B)
+#define BITS_RDE_LEN_TH1_8814B                                                 \
+	(BIT_MASK_RDE_LEN_TH1_8814B << BIT_SHIFT_RDE_LEN_TH1_8814B)
+#define BIT_CLEAR_RDE_LEN_TH1_8814B(x) ((x) & (~BITS_RDE_LEN_TH1_8814B))
+#define BIT_GET_RDE_LEN_TH1_8814B(x)                                           \
+	(((x) >> BIT_SHIFT_RDE_LEN_TH1_8814B) & BIT_MASK_RDE_LEN_TH1_8814B)
+#define BIT_SET_RDE_LEN_TH1_8814B(x, v)                                        \
+	(BIT_CLEAR_RDE_LEN_TH1_8814B(x) | BIT_RDE_LEN_TH1_8814B(v))
+
+#define BIT_SHIFT_RDE_LEN_TH0_8814B 0
+#define BIT_MASK_RDE_LEN_TH0_8814B 0xffff
+#define BIT_RDE_LEN_TH0_8814B(x)                                               \
+	(((x) & BIT_MASK_RDE_LEN_TH0_8814B) << BIT_SHIFT_RDE_LEN_TH0_8814B)
+#define BITS_RDE_LEN_TH0_8814B                                                 \
+	(BIT_MASK_RDE_LEN_TH0_8814B << BIT_SHIFT_RDE_LEN_TH0_8814B)
+#define BIT_CLEAR_RDE_LEN_TH0_8814B(x) ((x) & (~BITS_RDE_LEN_TH0_8814B))
+#define BIT_GET_RDE_LEN_TH0_8814B(x)                                           \
+	(((x) >> BIT_SHIFT_RDE_LEN_TH0_8814B) & BIT_MASK_RDE_LEN_TH0_8814B)
+#define BIT_SET_RDE_LEN_TH0_8814B(x, v)                                        \
+	(BIT_CLEAR_RDE_LEN_TH0_8814B(x) | BIT_RDE_LEN_TH0_8814B(v))
+
+/* 2 REG_PCIE_EXEC_TIME_THRESHOLD_8814B */
+
+#define BIT_SHIFT_COUNT_INT_SEL_8814B 16
+#define BIT_MASK_COUNT_INT_SEL_8814B 0x3
+#define BIT_COUNT_INT_SEL_8814B(x)                                             \
+	(((x) & BIT_MASK_COUNT_INT_SEL_8814B) << BIT_SHIFT_COUNT_INT_SEL_8814B)
+#define BITS_COUNT_INT_SEL_8814B                                               \
+	(BIT_MASK_COUNT_INT_SEL_8814B << BIT_SHIFT_COUNT_INT_SEL_8814B)
+#define BIT_CLEAR_COUNT_INT_SEL_8814B(x) ((x) & (~BITS_COUNT_INT_SEL_8814B))
+#define BIT_GET_COUNT_INT_SEL_8814B(x)                                         \
+	(((x) >> BIT_SHIFT_COUNT_INT_SEL_8814B) & BIT_MASK_COUNT_INT_SEL_8814B)
+#define BIT_SET_COUNT_INT_SEL_8814B(x, v)                                      \
+	(BIT_CLEAR_COUNT_INT_SEL_8814B(x) | BIT_COUNT_INT_SEL_8814B(v))
+
+#define BIT_SHIFT_EXEC_TIME_TH_8814B 0
+#define BIT_MASK_EXEC_TIME_TH_8814B 0xffff
+#define BIT_EXEC_TIME_TH_8814B(x)                                              \
+	(((x) & BIT_MASK_EXEC_TIME_TH_8814B) << BIT_SHIFT_EXEC_TIME_TH_8814B)
+#define BITS_EXEC_TIME_TH_8814B                                                \
+	(BIT_MASK_EXEC_TIME_TH_8814B << BIT_SHIFT_EXEC_TIME_TH_8814B)
+#define BIT_CLEAR_EXEC_TIME_TH_8814B(x) ((x) & (~BITS_EXEC_TIME_TH_8814B))
+#define BIT_GET_EXEC_TIME_TH_8814B(x)                                          \
+	(((x) >> BIT_SHIFT_EXEC_TIME_TH_8814B) & BIT_MASK_EXEC_TIME_TH_8814B)
+#define BIT_SET_EXEC_TIME_TH_8814B(x, v)                                       \
+	(BIT_CLEAR_EXEC_TIME_TH_8814B(x) | BIT_EXEC_TIME_TH_8814B(v))
+
+/* 2 REG_FT2IMR_8814B */
+#define BIT_FS_CLI3_RX_UAPSDMD1_EN_8814B BIT(31)
+#define BIT_FS_CLI3_RX_UAPSDMD0_EN_8814B BIT(30)
+#define BIT_FS_CLI3_TRIGGER_PKT_EN_8814B BIT(29)
+#define BIT_FS_CLI3_EOSP_INT_EN_8814B BIT(28)
+#define BIT_FS_CLI2_RX_UAPSDMD1_EN_8814B BIT(27)
+#define BIT_FS_CLI2_RX_UAPSDMD0_EN_8814B BIT(26)
+#define BIT_FS_CLI2_TRIGGER_PKT_EN_8814B BIT(25)
+#define BIT_FS_CLI2_EOSP_INT_EN_8814B BIT(24)
+#define BIT_FS_CLI1_RX_UAPSDMD1_EN_8814B BIT(23)
+#define BIT_FS_CLI1_RX_UAPSDMD0_EN_8814B BIT(22)
+#define BIT_FS_CLI1_TRIGGER_PKT_EN_8814B BIT(21)
+#define BIT_FS_CLI1_EOSP_INT_EN_8814B BIT(20)
+#define BIT_FS_CLI0_RX_UAPSDMD1_EN_8814B BIT(19)
+#define BIT_FS_CLI0_RX_UAPSDMD0_EN_8814B BIT(18)
+#define BIT_FS_CLI0_TRIGGER_PKT_EN_8814B BIT(17)
+#define BIT_FS_CLI0_EOSP_INT_EN_8814B BIT(16)
+#define BIT_FS_TSF_BIT32_TOGGLE_P2P2_EN_8814B BIT(9)
+#define BIT_FS_TSF_BIT32_TOGGLE_P2P1_EN_8814B BIT(8)
+#define BIT_FS_CLI3_TX_NULL1_INT_EN_8814B BIT(7)
+#define BIT_FS_CLI3_TX_NULL0_INT_EN_8814B BIT(6)
+#define BIT_FS_CLI2_TX_NULL1_INT_EN_8814B BIT(5)
+#define BIT_FS_CLI2_TX_NULL0_INT_EN_8814B BIT(4)
+#define BIT_FS_CLI1_TX_NULL1_INT_EN_8814B BIT(3)
+#define BIT_FS_CLI1_TX_NULL0_INT_EN_8814B BIT(2)
+#define BIT_FS_CLI0_TX_NULL1_INT_EN_8814B BIT(1)
+#define BIT_FS_CLI0_TX_NULL0_INT_EN_8814B BIT(0)
+
+/* 2 REG_FT2ISR_8814B */
+#define BIT_FS_CLI3_RX_UAPSDMD1_INT_8814B BIT(31)
+#define BIT_FS_CLI3_RX_UAPSDMD0_INT_8814B BIT(30)
+#define BIT_FS_CLI3_TRIGGER_PKT_INT_8814B BIT(29)
+#define BIT_FS_CLI3_EOSP_INT_8814B BIT(28)
+#define BIT_FS_CLI2_RX_UAPSDMD1_INT_8814B BIT(27)
+#define BIT_FS_CLI2_RX_UAPSDMD0_INT_8814B BIT(26)
+#define BIT_FS_CLI2_TRIGGER_PKT_INT_8814B BIT(25)
+#define BIT_FS_CLI2_EOSP_INT_8814B BIT(24)
+#define BIT_FS_CLI1_RX_UAPSDMD1_INT_8814B BIT(23)
+#define BIT_FS_CLI1_RX_UAPSDMD0_INT_8814B BIT(22)
+#define BIT_FS_CLI1_TRIGGER_PKT_INT_8814B BIT(21)
+#define BIT_FS_CLI1_EOSP_INT_8814B BIT(20)
+#define BIT_FS_CLI0_RX_UAPSDMD1_INT_8814B BIT(19)
+#define BIT_FS_CLI0_RX_UAPSDMD0_INT_8814B BIT(18)
+#define BIT_FS_CLI0_TRIGGER_PKT_INT_8814B BIT(17)
+#define BIT_FS_CLI0_EOSP_INT_8814B BIT(16)
+#define BIT_FS_TSF_BIT32_TOGGLE_P2P2_INT_8814B BIT(9)
+#define BIT_FS_TSF_BIT32_TOGGLE_P2P1_INT_8814B BIT(8)
+#define BIT_FS_CLI3_TX_NULL1_INT_8814B BIT(7)
+#define BIT_FS_CLI3_TX_NULL0_INT_8814B BIT(6)
+#define BIT_FS_CLI2_TX_NULL1_INT_8814B BIT(5)
+#define BIT_FS_CLI2_TX_NULL0_INT_8814B BIT(4)
+#define BIT_FS_CLI1_TX_NULL1_INT_8814B BIT(3)
+#define BIT_FS_CLI1_TX_NULL0_INT_8814B BIT(2)
+#define BIT_FS_CLI0_TX_NULL1_INT_8814B BIT(1)
+#define BIT_FS_CLI0_TX_NULL0_INT_8814B BIT(0)
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_MSG2_8814B */
+
+#define BIT_SHIFT_FW_MSG2_8814B 0
+#define BIT_MASK_FW_MSG2_8814B 0xffffffffL
+#define BIT_FW_MSG2_8814B(x)                                                   \
+	(((x) & BIT_MASK_FW_MSG2_8814B) << BIT_SHIFT_FW_MSG2_8814B)
+#define BITS_FW_MSG2_8814B (BIT_MASK_FW_MSG2_8814B << BIT_SHIFT_FW_MSG2_8814B)
+#define BIT_CLEAR_FW_MSG2_8814B(x) ((x) & (~BITS_FW_MSG2_8814B))
+#define BIT_GET_FW_MSG2_8814B(x)                                               \
+	(((x) >> BIT_SHIFT_FW_MSG2_8814B) & BIT_MASK_FW_MSG2_8814B)
+#define BIT_SET_FW_MSG2_8814B(x, v)                                            \
+	(BIT_CLEAR_FW_MSG2_8814B(x) | BIT_FW_MSG2_8814B(v))
+
+/* 2 REG_MSG3_8814B */
+
+#define BIT_SHIFT_FW_MSG3_8814B 0
+#define BIT_MASK_FW_MSG3_8814B 0xffffffffL
+#define BIT_FW_MSG3_8814B(x)                                                   \
+	(((x) & BIT_MASK_FW_MSG3_8814B) << BIT_SHIFT_FW_MSG3_8814B)
+#define BITS_FW_MSG3_8814B (BIT_MASK_FW_MSG3_8814B << BIT_SHIFT_FW_MSG3_8814B)
+#define BIT_CLEAR_FW_MSG3_8814B(x) ((x) & (~BITS_FW_MSG3_8814B))
+#define BIT_GET_FW_MSG3_8814B(x)                                               \
+	(((x) >> BIT_SHIFT_FW_MSG3_8814B) & BIT_MASK_FW_MSG3_8814B)
+#define BIT_SET_FW_MSG3_8814B(x, v)                                            \
+	(BIT_CLEAR_FW_MSG3_8814B(x) | BIT_FW_MSG3_8814B(v))
+
+/* 2 REG_MSG4_8814B */
+
+#define BIT_SHIFT_FW_MSG4_8814B 0
+#define BIT_MASK_FW_MSG4_8814B 0xffffffffL
+#define BIT_FW_MSG4_8814B(x)                                                   \
+	(((x) & BIT_MASK_FW_MSG4_8814B) << BIT_SHIFT_FW_MSG4_8814B)
+#define BITS_FW_MSG4_8814B (BIT_MASK_FW_MSG4_8814B << BIT_SHIFT_FW_MSG4_8814B)
+#define BIT_CLEAR_FW_MSG4_8814B(x) ((x) & (~BITS_FW_MSG4_8814B))
+#define BIT_GET_FW_MSG4_8814B(x)                                               \
+	(((x) >> BIT_SHIFT_FW_MSG4_8814B) & BIT_MASK_FW_MSG4_8814B)
+#define BIT_SET_FW_MSG4_8814B(x, v)                                            \
+	(BIT_CLEAR_FW_MSG4_8814B(x) | BIT_FW_MSG4_8814B(v))
+
+/* 2 REG_MSG5_8814B */
+
+#define BIT_SHIFT_FW_MSG5_8814B 0
+#define BIT_MASK_FW_MSG5_8814B 0xffffffffL
+#define BIT_FW_MSG5_8814B(x)                                                   \
+	(((x) & BIT_MASK_FW_MSG5_8814B) << BIT_SHIFT_FW_MSG5_8814B)
+#define BITS_FW_MSG5_8814B (BIT_MASK_FW_MSG5_8814B << BIT_SHIFT_FW_MSG5_8814B)
+#define BIT_CLEAR_FW_MSG5_8814B(x) ((x) & (~BITS_FW_MSG5_8814B))
+#define BIT_GET_FW_MSG5_8814B(x)                                               \
+	(((x) >> BIT_SHIFT_FW_MSG5_8814B) & BIT_MASK_FW_MSG5_8814B)
+#define BIT_SET_FW_MSG5_8814B(x, v)                                            \
+	(BIT_CLEAR_FW_MSG5_8814B(x) | BIT_FW_MSG5_8814B(v))
+
+/* 2 REG_BIST_RSTN0_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_BIST_RSTN2_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_BIST_MODE_NRML0_8814B */
+
+/* 2 REG_BIST_MODE_NRML1_8814B */
+
+/* 2 REG_BIST_MODE_NRML2_8814B */
+
+/* 2 REG_BIST_MODE_NRML3_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_BIST_DONE_NRML_MAC_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_BIST_DONE_NRML1_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_BIST_DONE_DRF_MAC_8814B */
+
+/* 2 REG_BIST_DONE_DRF_8814B */
+
+/* 2 REG_BIST_DONE_DRF1_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_BIST_FAIL_NRML_MAC_8814B */
+
+/* 2 REG_BIST_FAIL_NRML_8814B */
+
+/* 2 REG_BIST_FAIL_NRML1_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_BIST_FAIL_NRML_MAC_V1_8814B */
+
+/* 2 REG_BIST_FAIL_NRML_V1_8814B */
+
+/* 2 REG_BIST_FAIL_NRML1_V1_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_BIST_MISR_DATAOUT_8814B */
+
+/* 2 REG_BIST_MISR_DATAOUT1_8814B */
+
+/* 2 REG_BIST_MISR_DATAOUT_CPU_8814B */
+
+/* 2 REG_BIST_MISR_DATAOUT_CPU1_8814B */
+
+/* 2 REG_BIST_MISR_DATAOUT_CPU2_8814B */
+
+/* 2 REG_BIST_MISR_DATOUT_CPU3_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_BCN_CTRL_0_8814B */
+#define BIT_BCN1_VALID_8814B BIT(31)
+
+/* 2 REG_NOT_VALID_8814B */
+
+#define BIT_SHIFT_BCN1_HEAD_8814B 16
+#define BIT_MASK_BCN1_HEAD_8814B 0xfff
+#define BIT_BCN1_HEAD_8814B(x)                                                 \
+	(((x) & BIT_MASK_BCN1_HEAD_8814B) << BIT_SHIFT_BCN1_HEAD_8814B)
+#define BITS_BCN1_HEAD_8814B                                                   \
+	(BIT_MASK_BCN1_HEAD_8814B << BIT_SHIFT_BCN1_HEAD_8814B)
+#define BIT_CLEAR_BCN1_HEAD_8814B(x) ((x) & (~BITS_BCN1_HEAD_8814B))
+#define BIT_GET_BCN1_HEAD_8814B(x)                                             \
+	(((x) >> BIT_SHIFT_BCN1_HEAD_8814B) & BIT_MASK_BCN1_HEAD_8814B)
+#define BIT_SET_BCN1_HEAD_8814B(x, v)                                          \
+	(BIT_CLEAR_BCN1_HEAD_8814B(x) | BIT_BCN1_HEAD_8814B(v))
+
+#define BIT_BCN0_VALID_8814B BIT(15)
+
+/* 2 REG_NOT_VALID_8814B */
+
+#define BIT_SHIFT_BCN0_HEAD_8814B 0
+#define BIT_MASK_BCN0_HEAD_8814B 0xfff
+#define BIT_BCN0_HEAD_8814B(x)                                                 \
+	(((x) & BIT_MASK_BCN0_HEAD_8814B) << BIT_SHIFT_BCN0_HEAD_8814B)
+#define BITS_BCN0_HEAD_8814B                                                   \
+	(BIT_MASK_BCN0_HEAD_8814B << BIT_SHIFT_BCN0_HEAD_8814B)
+#define BIT_CLEAR_BCN0_HEAD_8814B(x) ((x) & (~BITS_BCN0_HEAD_8814B))
+#define BIT_GET_BCN0_HEAD_8814B(x)                                             \
+	(((x) >> BIT_SHIFT_BCN0_HEAD_8814B) & BIT_MASK_BCN0_HEAD_8814B)
+#define BIT_SET_BCN0_HEAD_8814B(x, v)                                          \
+	(BIT_CLEAR_BCN0_HEAD_8814B(x) | BIT_BCN0_HEAD_8814B(v))
+
+/* 2 REG_BCN_CTRL_1_8814B */
+#define BIT_BCN3_VALID_8814B BIT(31)
+
+/* 2 REG_NOT_VALID_8814B */
+
+#define BIT_SHIFT_BCN3_HEAD_8814B 16
+#define BIT_MASK_BCN3_HEAD_8814B 0xfff
+#define BIT_BCN3_HEAD_8814B(x)                                                 \
+	(((x) & BIT_MASK_BCN3_HEAD_8814B) << BIT_SHIFT_BCN3_HEAD_8814B)
+#define BITS_BCN3_HEAD_8814B                                                   \
+	(BIT_MASK_BCN3_HEAD_8814B << BIT_SHIFT_BCN3_HEAD_8814B)
+#define BIT_CLEAR_BCN3_HEAD_8814B(x) ((x) & (~BITS_BCN3_HEAD_8814B))
+#define BIT_GET_BCN3_HEAD_8814B(x)                                             \
+	(((x) >> BIT_SHIFT_BCN3_HEAD_8814B) & BIT_MASK_BCN3_HEAD_8814B)
+#define BIT_SET_BCN3_HEAD_8814B(x, v)                                          \
+	(BIT_CLEAR_BCN3_HEAD_8814B(x) | BIT_BCN3_HEAD_8814B(v))
+
+#define BIT_BCN2_VALID_8814B BIT(15)
+
+/* 2 REG_NOT_VALID_8814B */
+
+#define BIT_SHIFT_BCN2_HEAD_8814B 0
+#define BIT_MASK_BCN2_HEAD_8814B 0xfff
+#define BIT_BCN2_HEAD_8814B(x)                                                 \
+	(((x) & BIT_MASK_BCN2_HEAD_8814B) << BIT_SHIFT_BCN2_HEAD_8814B)
+#define BITS_BCN2_HEAD_8814B                                                   \
+	(BIT_MASK_BCN2_HEAD_8814B << BIT_SHIFT_BCN2_HEAD_8814B)
+#define BIT_CLEAR_BCN2_HEAD_8814B(x) ((x) & (~BITS_BCN2_HEAD_8814B))
+#define BIT_GET_BCN2_HEAD_8814B(x)                                             \
+	(((x) >> BIT_SHIFT_BCN2_HEAD_8814B) & BIT_MASK_BCN2_HEAD_8814B)
+#define BIT_SET_BCN2_HEAD_8814B(x, v)                                          \
+	(BIT_CLEAR_BCN2_HEAD_8814B(x) | BIT_BCN2_HEAD_8814B(v))
+
+/* 2 REG_AUTO_LLT_V1_8814B */
+
+#define BIT_SHIFT_MAX_TX_PKT_V1_8814B 24
+#define BIT_MASK_MAX_TX_PKT_V1_8814B 0xff
+#define BIT_MAX_TX_PKT_V1_8814B(x)                                             \
+	(((x) & BIT_MASK_MAX_TX_PKT_V1_8814B) << BIT_SHIFT_MAX_TX_PKT_V1_8814B)
+#define BITS_MAX_TX_PKT_V1_8814B                                               \
+	(BIT_MASK_MAX_TX_PKT_V1_8814B << BIT_SHIFT_MAX_TX_PKT_V1_8814B)
+#define BIT_CLEAR_MAX_TX_PKT_V1_8814B(x) ((x) & (~BITS_MAX_TX_PKT_V1_8814B))
+#define BIT_GET_MAX_TX_PKT_V1_8814B(x)                                         \
+	(((x) >> BIT_SHIFT_MAX_TX_PKT_V1_8814B) & BIT_MASK_MAX_TX_PKT_V1_8814B)
+#define BIT_SET_MAX_TX_PKT_V1_8814B(x, v)                                      \
+	(BIT_CLEAR_MAX_TX_PKT_V1_8814B(x) | BIT_MAX_TX_PKT_V1_8814B(v))
+
+/* 2 REG_NOT_VALID_8814B */
+
+#define BIT_SHIFT_R_BCN_HEAD_SEL_V1_8814B 20
+#define BIT_MASK_R_BCN_HEAD_SEL_V1_8814B 0x7
+#define BIT_R_BCN_HEAD_SEL_V1_8814B(x)                                         \
+	(((x) & BIT_MASK_R_BCN_HEAD_SEL_V1_8814B)                              \
+	 << BIT_SHIFT_R_BCN_HEAD_SEL_V1_8814B)
+#define BITS_R_BCN_HEAD_SEL_V1_8814B                                           \
+	(BIT_MASK_R_BCN_HEAD_SEL_V1_8814B << BIT_SHIFT_R_BCN_HEAD_SEL_V1_8814B)
+#define BIT_CLEAR_R_BCN_HEAD_SEL_V1_8814B(x)                                   \
+	((x) & (~BITS_R_BCN_HEAD_SEL_V1_8814B))
+#define BIT_GET_R_BCN_HEAD_SEL_V1_8814B(x)                                     \
+	(((x) >> BIT_SHIFT_R_BCN_HEAD_SEL_V1_8814B) &                          \
+	 BIT_MASK_R_BCN_HEAD_SEL_V1_8814B)
+#define BIT_SET_R_BCN_HEAD_SEL_V1_8814B(x, v)                                  \
+	(BIT_CLEAR_R_BCN_HEAD_SEL_V1_8814B(x) | BIT_R_BCN_HEAD_SEL_V1_8814B(v))
+
+#define BIT_SHIFT_LLT_FREE_PAGE_V2_8814B 8
+#define BIT_MASK_LLT_FREE_PAGE_V2_8814B 0xfff
+#define BIT_LLT_FREE_PAGE_V2_8814B(x)                                          \
+	(((x) & BIT_MASK_LLT_FREE_PAGE_V2_8814B)                               \
+	 << BIT_SHIFT_LLT_FREE_PAGE_V2_8814B)
+#define BITS_LLT_FREE_PAGE_V2_8814B                                            \
+	(BIT_MASK_LLT_FREE_PAGE_V2_8814B << BIT_SHIFT_LLT_FREE_PAGE_V2_8814B)
+#define BIT_CLEAR_LLT_FREE_PAGE_V2_8814B(x)                                    \
+	((x) & (~BITS_LLT_FREE_PAGE_V2_8814B))
+#define BIT_GET_LLT_FREE_PAGE_V2_8814B(x)                                      \
+	(((x) >> BIT_SHIFT_LLT_FREE_PAGE_V2_8814B) &                           \
+	 BIT_MASK_LLT_FREE_PAGE_V2_8814B)
+#define BIT_SET_LLT_FREE_PAGE_V2_8814B(x, v)                                   \
+	(BIT_CLEAR_LLT_FREE_PAGE_V2_8814B(x) | BIT_LLT_FREE_PAGE_V2_8814B(v))
+
+#define BIT_SHIFT_BLK_DESC_NUM_8814B 4
+#define BIT_MASK_BLK_DESC_NUM_8814B 0xf
+#define BIT_BLK_DESC_NUM_8814B(x)                                              \
+	(((x) & BIT_MASK_BLK_DESC_NUM_8814B) << BIT_SHIFT_BLK_DESC_NUM_8814B)
+#define BITS_BLK_DESC_NUM_8814B                                                \
+	(BIT_MASK_BLK_DESC_NUM_8814B << BIT_SHIFT_BLK_DESC_NUM_8814B)
+#define BIT_CLEAR_BLK_DESC_NUM_8814B(x) ((x) & (~BITS_BLK_DESC_NUM_8814B))
+#define BIT_GET_BLK_DESC_NUM_8814B(x)                                          \
+	(((x) >> BIT_SHIFT_BLK_DESC_NUM_8814B) & BIT_MASK_BLK_DESC_NUM_8814B)
+#define BIT_SET_BLK_DESC_NUM_8814B(x, v)                                       \
+	(BIT_CLEAR_BLK_DESC_NUM_8814B(x) | BIT_BLK_DESC_NUM_8814B(v))
+
+#define BIT_TDE_ERROR_STOP_8814B BIT(3)
+#define BIT_R_EN_BCN_SW_HEAD_SEL_8814B BIT(2)
+#define BIT_LLT_DBG_SEL_8814B BIT(1)
+#define BIT_AUTO_INIT_LLT_V1_8814B BIT(0)
+
+/* 2 REG_TXDMA_OFFSET_CHK_8814B */
+#define BIT_EM_CHKSUM_FIN_8814B BIT(31)
+#define BIT_EMN_PCIE_DMA_MOD_8814B BIT(30)
+#define BIT_EN_TXQUE_CLR_8814B BIT(29)
+#define BIT_EN_PCIE_FIFO_MODE_8814B BIT(28)
+
+#define BIT_SHIFT_PG_UNDER_TH_V1_8814B 16
+#define BIT_MASK_PG_UNDER_TH_V1_8814B 0xfff
+#define BIT_PG_UNDER_TH_V1_8814B(x)                                            \
+	(((x) & BIT_MASK_PG_UNDER_TH_V1_8814B)                                 \
+	 << BIT_SHIFT_PG_UNDER_TH_V1_8814B)
+#define BITS_PG_UNDER_TH_V1_8814B                                              \
+	(BIT_MASK_PG_UNDER_TH_V1_8814B << BIT_SHIFT_PG_UNDER_TH_V1_8814B)
+#define BIT_CLEAR_PG_UNDER_TH_V1_8814B(x) ((x) & (~BITS_PG_UNDER_TH_V1_8814B))
+#define BIT_GET_PG_UNDER_TH_V1_8814B(x)                                        \
+	(((x) >> BIT_SHIFT_PG_UNDER_TH_V1_8814B) &                             \
+	 BIT_MASK_PG_UNDER_TH_V1_8814B)
+#define BIT_SET_PG_UNDER_TH_V1_8814B(x, v)                                     \
+	(BIT_CLEAR_PG_UNDER_TH_V1_8814B(x) | BIT_PG_UNDER_TH_V1_8814B(v))
+
+#define BIT_R_EN_RESET_RESTORE_H2C_8814B BIT(15)
+#define BIT_SDIO_TDE_FINISH_8814B BIT(14)
+#define BIT_SDIO_TXDESC_CHKSUM_EN_8814B BIT(13)
+#define BIT_RST_RDPTR_8814B BIT(12)
+#define BIT_RST_WRPTR_8814B BIT(11)
+#define BIT_CHK_PG_TH_EN_8814B BIT(10)
+#define BIT_DROP_DATA_EN_8814B BIT(9)
+#define BIT_CHECK_OFFSET_EN_8814B BIT(8)
+
+#define BIT_SHIFT_CHECK_OFFSET_8814B 0
+#define BIT_MASK_CHECK_OFFSET_8814B 0xff
+#define BIT_CHECK_OFFSET_8814B(x)                                              \
+	(((x) & BIT_MASK_CHECK_OFFSET_8814B) << BIT_SHIFT_CHECK_OFFSET_8814B)
+#define BITS_CHECK_OFFSET_8814B                                                \
+	(BIT_MASK_CHECK_OFFSET_8814B << BIT_SHIFT_CHECK_OFFSET_8814B)
+#define BIT_CLEAR_CHECK_OFFSET_8814B(x) ((x) & (~BITS_CHECK_OFFSET_8814B))
+#define BIT_GET_CHECK_OFFSET_8814B(x)                                          \
+	(((x) >> BIT_SHIFT_CHECK_OFFSET_8814B) & BIT_MASK_CHECK_OFFSET_8814B)
+#define BIT_SET_CHECK_OFFSET_8814B(x, v)                                       \
+	(BIT_CLEAR_CHECK_OFFSET_8814B(x) | BIT_CHECK_OFFSET_8814B(v))
+
+/* 2 REG_TXDMA_STATUS_8814B */
+#define BIT_AMSDU_PKT_SIZE_ERR_8814B BIT(31)
+#define BIT_AMSDU_EN_ERR_8814B BIT(30)
+#define BIT_CHKSUM_AMSDU_EN_ERR_8814B BIT(29)
+#define BIT_TXPKTBF_REQ_ERR_8814B BIT(28)
+#define BIT_OQT_UDN_16_8814B BIT(27)
+#define BIT_OQT_OVF_16_8814B BIT(26)
+#define BIT_OQT_UDN_14_15_8814B BIT(25)
+#define BIT_OQT_OVF_14_15_8814B BIT(24)
+#define BIT_OQT_UDN_13_8814B BIT(23)
+#define BIT_OQT_OVF_13_8814B BIT(22)
+#define BIT_OQT_UDN_12_8814B BIT(21)
+#define BIT_OQT_OVF_12_8814B BIT(20)
+#define BIT_OQT_UDN_8_11_8814B BIT(19)
+#define BIT_OQT_OVF_8_11_8814B BIT(18)
+#define BIT_OQT_UDN_4_7_8814B BIT(17)
+#define BIT_OQT_OVF_4_7_8814B BIT(16)
+#define BIT_PAYLOAD_CHKSUM_ERR_8814B BIT(15)
+#define BIT_PAYLOAD_UDN_8814B BIT(14)
+#define BIT_PAYLOAD_OVF_8814B BIT(13)
+#define BIT_DSC_CHKSUM_FAIL_8814B BIT(12)
+#define BIT_EP_QSEL_DIFF_8814B BIT(10)
+#define BIT_TX_OFFS_UNMATCH_8814B BIT(9)
+#define BIT_TXOQT_UDN_0_3_8814B BIT(8)
+#define BIT_TXOQT_OVF_0_3_8814B BIT(7)
+#define BIT_TXDMA_SFF_UDN_8814B BIT(6)
+#define BIT_TXDMA_SFF_OVF_8814B BIT(5)
+#define BIT_LLT_NULL_PG_8814B BIT(4)
+#define BIT_PAGE_UDN_8814B BIT(3)
+#define BIT_PAGE_OVF_8814B BIT(2)
+#define BIT_TXFF_PG_UDN_8814B BIT(1)
+#define BIT_TXFF_PG_OVF_8814B BIT(0)
+
+/* 2 REG_TX_DMA_DBG_8814B */
+
+/* 2 REG_DMA_RQPN_INFO_PUB_8814B */
+
+#define BIT_SHIFT_PUB_AVAL_PG_8814B 16
+#define BIT_MASK_PUB_AVAL_PG_8814B 0xfff
+#define BIT_PUB_AVAL_PG_8814B(x)                                               \
+	(((x) & BIT_MASK_PUB_AVAL_PG_8814B) << BIT_SHIFT_PUB_AVAL_PG_8814B)
+#define BITS_PUB_AVAL_PG_8814B                                                 \
+	(BIT_MASK_PUB_AVAL_PG_8814B << BIT_SHIFT_PUB_AVAL_PG_8814B)
+#define BIT_CLEAR_PUB_AVAL_PG_8814B(x) ((x) & (~BITS_PUB_AVAL_PG_8814B))
+#define BIT_GET_PUB_AVAL_PG_8814B(x)                                           \
+	(((x) >> BIT_SHIFT_PUB_AVAL_PG_8814B) & BIT_MASK_PUB_AVAL_PG_8814B)
+#define BIT_SET_PUB_AVAL_PG_8814B(x, v)                                        \
+	(BIT_CLEAR_PUB_AVAL_PG_8814B(x) | BIT_PUB_AVAL_PG_8814B(v))
+
+#define BIT_SHIFT_PUB_RSVD_PG_8814B 0
+#define BIT_MASK_PUB_RSVD_PG_8814B 0xfff
+#define BIT_PUB_RSVD_PG_8814B(x)                                               \
+	(((x) & BIT_MASK_PUB_RSVD_PG_8814B) << BIT_SHIFT_PUB_RSVD_PG_8814B)
+#define BITS_PUB_RSVD_PG_8814B                                                 \
+	(BIT_MASK_PUB_RSVD_PG_8814B << BIT_SHIFT_PUB_RSVD_PG_8814B)
+#define BIT_CLEAR_PUB_RSVD_PG_8814B(x) ((x) & (~BITS_PUB_RSVD_PG_8814B))
+#define BIT_GET_PUB_RSVD_PG_8814B(x)                                           \
+	(((x) >> BIT_SHIFT_PUB_RSVD_PG_8814B) & BIT_MASK_PUB_RSVD_PG_8814B)
+#define BIT_SET_PUB_RSVD_PG_8814B(x, v)                                        \
+	(BIT_CLEAR_PUB_RSVD_PG_8814B(x) | BIT_PUB_RSVD_PG_8814B(v))
+
+/* 2 REG_RQPN_CTRL_2_V1_8814B */
+#define BIT_LD_RQPN_V1_8814B BIT(31)
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+#define BIT_CH16_PUBLIC_DIS_8814B BIT(16)
+#define BIT_CH15_PUBLIC_DIS_8814B BIT(15)
+#define BIT_CH14_PUBLIC_DIS_8814B BIT(14)
+#define BIT_CH13_PUBLIC_DIS_8814B BIT(13)
+#define BIT_CH12_PUBLIC_DIS_8814B BIT(12)
+#define BIT_CH11_PUBLIC_DIS_8814B BIT(11)
+#define BIT_CH10_PUBLIC_DIS_8814B BIT(10)
+#define BIT_CH9_PUBLIC_DIS_8814B BIT(9)
+#define BIT_CH8_PUBLIC_DIS_8814B BIT(8)
+#define BIT_CH7_PUBLIC_DIS_8814B BIT(7)
+#define BIT_CH6_PUBLIC_DIS_8814B BIT(6)
+#define BIT_CH5_PUBLIC_DIS_8814B BIT(5)
+#define BIT_CH4_PUBLIC_DIS_8814B BIT(4)
+#define BIT_CH3_PUBLIC_DIS_8814B BIT(3)
+#define BIT_CH2_PUBLIC_DIS_8814B BIT(2)
+#define BIT_CH1_PUBLIC_DIS_8814B BIT(1)
+#define BIT_CH0_PUBLIC_DIS_8814B BIT(0)
+
+/* 2 REG_BCN_CTRL_2_8814B */
+#define BIT_BCN0_EXT_VALID_8814B BIT(31)
+
+/* 2 REG_NOT_VALID_8814B */
+
+#define BIT_SHIFT_BCN0_EXT_HEAD_8814B 16
+#define BIT_MASK_BCN0_EXT_HEAD_8814B 0xfff
+#define BIT_BCN0_EXT_HEAD_8814B(x)                                             \
+	(((x) & BIT_MASK_BCN0_EXT_HEAD_8814B) << BIT_SHIFT_BCN0_EXT_HEAD_8814B)
+#define BITS_BCN0_EXT_HEAD_8814B                                               \
+	(BIT_MASK_BCN0_EXT_HEAD_8814B << BIT_SHIFT_BCN0_EXT_HEAD_8814B)
+#define BIT_CLEAR_BCN0_EXT_HEAD_8814B(x) ((x) & (~BITS_BCN0_EXT_HEAD_8814B))
+#define BIT_GET_BCN0_EXT_HEAD_8814B(x)                                         \
+	(((x) >> BIT_SHIFT_BCN0_EXT_HEAD_8814B) & BIT_MASK_BCN0_EXT_HEAD_8814B)
+#define BIT_SET_BCN0_EXT_HEAD_8814B(x, v)                                      \
+	(BIT_CLEAR_BCN0_EXT_HEAD_8814B(x) | BIT_BCN0_EXT_HEAD_8814B(v))
+
+#define BIT_BCN4_VALID_8814B BIT(15)
+
+/* 2 REG_NOT_VALID_8814B */
+
+#define BIT_SHIFT_BCN4_HEAD_8814B 0
+#define BIT_MASK_BCN4_HEAD_8814B 0xfff
+#define BIT_BCN4_HEAD_8814B(x)                                                 \
+	(((x) & BIT_MASK_BCN4_HEAD_8814B) << BIT_SHIFT_BCN4_HEAD_8814B)
+#define BITS_BCN4_HEAD_8814B                                                   \
+	(BIT_MASK_BCN4_HEAD_8814B << BIT_SHIFT_BCN4_HEAD_8814B)
+#define BIT_CLEAR_BCN4_HEAD_8814B(x) ((x) & (~BITS_BCN4_HEAD_8814B))
+#define BIT_GET_BCN4_HEAD_8814B(x)                                             \
+	(((x) >> BIT_SHIFT_BCN4_HEAD_8814B) & BIT_MASK_BCN4_HEAD_8814B)
+#define BIT_SET_BCN4_HEAD_8814B(x, v)                                          \
+	(BIT_CLEAR_BCN4_HEAD_8814B(x) | BIT_BCN4_HEAD_8814B(v))
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_TXPKTNUM_0_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+#define BIT_SHIFT_TXPKTNUM_CH4_7_8814B 16
+#define BIT_MASK_TXPKTNUM_CH4_7_8814B 0xfff
+#define BIT_TXPKTNUM_CH4_7_8814B(x)                                            \
+	(((x) & BIT_MASK_TXPKTNUM_CH4_7_8814B)                                 \
+	 << BIT_SHIFT_TXPKTNUM_CH4_7_8814B)
+#define BITS_TXPKTNUM_CH4_7_8814B                                              \
+	(BIT_MASK_TXPKTNUM_CH4_7_8814B << BIT_SHIFT_TXPKTNUM_CH4_7_8814B)
+#define BIT_CLEAR_TXPKTNUM_CH4_7_8814B(x) ((x) & (~BITS_TXPKTNUM_CH4_7_8814B))
+#define BIT_GET_TXPKTNUM_CH4_7_8814B(x)                                        \
+	(((x) >> BIT_SHIFT_TXPKTNUM_CH4_7_8814B) &                             \
+	 BIT_MASK_TXPKTNUM_CH4_7_8814B)
+#define BIT_SET_TXPKTNUM_CH4_7_8814B(x, v)                                     \
+	(BIT_CLEAR_TXPKTNUM_CH4_7_8814B(x) | BIT_TXPKTNUM_CH4_7_8814B(v))
+
+/* 2 REG_NOT_VALID_8814B */
+
+#define BIT_SHIFT_TXPKTNUM_CH0_3_8814B 0
+#define BIT_MASK_TXPKTNUM_CH0_3_8814B 0xfff
+#define BIT_TXPKTNUM_CH0_3_8814B(x)                                            \
+	(((x) & BIT_MASK_TXPKTNUM_CH0_3_8814B)                                 \
+	 << BIT_SHIFT_TXPKTNUM_CH0_3_8814B)
+#define BITS_TXPKTNUM_CH0_3_8814B                                              \
+	(BIT_MASK_TXPKTNUM_CH0_3_8814B << BIT_SHIFT_TXPKTNUM_CH0_3_8814B)
+#define BIT_CLEAR_TXPKTNUM_CH0_3_8814B(x) ((x) & (~BITS_TXPKTNUM_CH0_3_8814B))
+#define BIT_GET_TXPKTNUM_CH0_3_8814B(x)                                        \
+	(((x) >> BIT_SHIFT_TXPKTNUM_CH0_3_8814B) &                             \
+	 BIT_MASK_TXPKTNUM_CH0_3_8814B)
+#define BIT_SET_TXPKTNUM_CH0_3_8814B(x, v)                                     \
+	(BIT_CLEAR_TXPKTNUM_CH0_3_8814B(x) | BIT_TXPKTNUM_CH0_3_8814B(v))
+
+/* 2 REG_TXPKTNUM_1_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+#define BIT_SHIFT_TXPKTNUM_CH12_8814B 16
+#define BIT_MASK_TXPKTNUM_CH12_8814B 0xfff
+#define BIT_TXPKTNUM_CH12_8814B(x)                                             \
+	(((x) & BIT_MASK_TXPKTNUM_CH12_8814B) << BIT_SHIFT_TXPKTNUM_CH12_8814B)
+#define BITS_TXPKTNUM_CH12_8814B                                               \
+	(BIT_MASK_TXPKTNUM_CH12_8814B << BIT_SHIFT_TXPKTNUM_CH12_8814B)
+#define BIT_CLEAR_TXPKTNUM_CH12_8814B(x) ((x) & (~BITS_TXPKTNUM_CH12_8814B))
+#define BIT_GET_TXPKTNUM_CH12_8814B(x)                                         \
+	(((x) >> BIT_SHIFT_TXPKTNUM_CH12_8814B) & BIT_MASK_TXPKTNUM_CH12_8814B)
+#define BIT_SET_TXPKTNUM_CH12_8814B(x, v)                                      \
+	(BIT_CLEAR_TXPKTNUM_CH12_8814B(x) | BIT_TXPKTNUM_CH12_8814B(v))
+
+/* 2 REG_NOT_VALID_8814B */
+
+#define BIT_SHIFT_TXPKTNUM_CH8_11_8814B 0
+#define BIT_MASK_TXPKTNUM_CH8_11_8814B 0xfff
+#define BIT_TXPKTNUM_CH8_11_8814B(x)                                           \
+	(((x) & BIT_MASK_TXPKTNUM_CH8_11_8814B)                                \
+	 << BIT_SHIFT_TXPKTNUM_CH8_11_8814B)
+#define BITS_TXPKTNUM_CH8_11_8814B                                             \
+	(BIT_MASK_TXPKTNUM_CH8_11_8814B << BIT_SHIFT_TXPKTNUM_CH8_11_8814B)
+#define BIT_CLEAR_TXPKTNUM_CH8_11_8814B(x) ((x) & (~BITS_TXPKTNUM_CH8_11_8814B))
+#define BIT_GET_TXPKTNUM_CH8_11_8814B(x)                                       \
+	(((x) >> BIT_SHIFT_TXPKTNUM_CH8_11_8814B) &                            \
+	 BIT_MASK_TXPKTNUM_CH8_11_8814B)
+#define BIT_SET_TXPKTNUM_CH8_11_8814B(x, v)                                    \
+	(BIT_CLEAR_TXPKTNUM_CH8_11_8814B(x) | BIT_TXPKTNUM_CH8_11_8814B(v))
+
+/* 2 REG_TXPKTNUM_2_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+#define BIT_SHIFT_TXPKTNUM_CH14_15_8814B 16
+#define BIT_MASK_TXPKTNUM_CH14_15_8814B 0xfff
+#define BIT_TXPKTNUM_CH14_15_8814B(x)                                          \
+	(((x) & BIT_MASK_TXPKTNUM_CH14_15_8814B)                               \
+	 << BIT_SHIFT_TXPKTNUM_CH14_15_8814B)
+#define BITS_TXPKTNUM_CH14_15_8814B                                            \
+	(BIT_MASK_TXPKTNUM_CH14_15_8814B << BIT_SHIFT_TXPKTNUM_CH14_15_8814B)
+#define BIT_CLEAR_TXPKTNUM_CH14_15_8814B(x)                                    \
+	((x) & (~BITS_TXPKTNUM_CH14_15_8814B))
+#define BIT_GET_TXPKTNUM_CH14_15_8814B(x)                                      \
+	(((x) >> BIT_SHIFT_TXPKTNUM_CH14_15_8814B) &                           \
+	 BIT_MASK_TXPKTNUM_CH14_15_8814B)
+#define BIT_SET_TXPKTNUM_CH14_15_8814B(x, v)                                   \
+	(BIT_CLEAR_TXPKTNUM_CH14_15_8814B(x) | BIT_TXPKTNUM_CH14_15_8814B(v))
+
+/* 2 REG_NOT_VALID_8814B */
+
+#define BIT_SHIFT_TXPKTNUM_CH13_8814B 0
+#define BIT_MASK_TXPKTNUM_CH13_8814B 0xfff
+#define BIT_TXPKTNUM_CH13_8814B(x)                                             \
+	(((x) & BIT_MASK_TXPKTNUM_CH13_8814B) << BIT_SHIFT_TXPKTNUM_CH13_8814B)
+#define BITS_TXPKTNUM_CH13_8814B                                               \
+	(BIT_MASK_TXPKTNUM_CH13_8814B << BIT_SHIFT_TXPKTNUM_CH13_8814B)
+#define BIT_CLEAR_TXPKTNUM_CH13_8814B(x) ((x) & (~BITS_TXPKTNUM_CH13_8814B))
+#define BIT_GET_TXPKTNUM_CH13_8814B(x)                                         \
+	(((x) >> BIT_SHIFT_TXPKTNUM_CH13_8814B) & BIT_MASK_TXPKTNUM_CH13_8814B)
+#define BIT_SET_TXPKTNUM_CH13_8814B(x, v)                                      \
+	(BIT_CLEAR_TXPKTNUM_CH13_8814B(x) | BIT_TXPKTNUM_CH13_8814B(v))
+
+/* 2 REG_TXPKTNUM_3_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+#define BIT_SHIFT_TXPKTNUM_CH16_8814B 0
+#define BIT_MASK_TXPKTNUM_CH16_8814B 0xfff
+#define BIT_TXPKTNUM_CH16_8814B(x)                                             \
+	(((x) & BIT_MASK_TXPKTNUM_CH16_8814B) << BIT_SHIFT_TXPKTNUM_CH16_8814B)
+#define BITS_TXPKTNUM_CH16_8814B                                               \
+	(BIT_MASK_TXPKTNUM_CH16_8814B << BIT_SHIFT_TXPKTNUM_CH16_8814B)
+#define BIT_CLEAR_TXPKTNUM_CH16_8814B(x) ((x) & (~BITS_TXPKTNUM_CH16_8814B))
+#define BIT_GET_TXPKTNUM_CH16_8814B(x)                                         \
+	(((x) >> BIT_SHIFT_TXPKTNUM_CH16_8814B) & BIT_MASK_TXPKTNUM_CH16_8814B)
+#define BIT_SET_TXPKTNUM_CH16_8814B(x, v)                                      \
+	(BIT_CLEAR_TXPKTNUM_CH16_8814B(x) | BIT_TXPKTNUM_CH16_8814B(v))
+
+/* 2 REG_TX_AGG_ALIGN_8814B */
+
+#define BIT_SHIFT_HW_FLOW_CTL_EN_8814B 16
+#define BIT_MASK_HW_FLOW_CTL_EN_8814B 0xffff
+#define BIT_HW_FLOW_CTL_EN_8814B(x)                                            \
+	(((x) & BIT_MASK_HW_FLOW_CTL_EN_8814B)                                 \
+	 << BIT_SHIFT_HW_FLOW_CTL_EN_8814B)
+#define BITS_HW_FLOW_CTL_EN_8814B                                              \
+	(BIT_MASK_HW_FLOW_CTL_EN_8814B << BIT_SHIFT_HW_FLOW_CTL_EN_8814B)
+#define BIT_CLEAR_HW_FLOW_CTL_EN_8814B(x) ((x) & (~BITS_HW_FLOW_CTL_EN_8814B))
+#define BIT_GET_HW_FLOW_CTL_EN_8814B(x)                                        \
+	(((x) >> BIT_SHIFT_HW_FLOW_CTL_EN_8814B) &                             \
+	 BIT_MASK_HW_FLOW_CTL_EN_8814B)
+#define BIT_SET_HW_FLOW_CTL_EN_8814B(x, v)                                     \
+	(BIT_CLEAR_HW_FLOW_CTL_EN_8814B(x) | BIT_HW_FLOW_CTL_EN_8814B(v))
+
+/* 2 REG_NOT_VALID_8814B */
+#define BIT_SDIO_TXAGG_ALIGN_ADJUST_EN_V1_8814B BIT(15)
+
+#define BIT_SHIFT_SDIO_TXAGG_ALIGN_SIZE_V1_8814B 0
+#define BIT_MASK_SDIO_TXAGG_ALIGN_SIZE_V1_8814B 0xfff
+#define BIT_SDIO_TXAGG_ALIGN_SIZE_V1_8814B(x)                                  \
+	(((x) & BIT_MASK_SDIO_TXAGG_ALIGN_SIZE_V1_8814B)                       \
+	 << BIT_SHIFT_SDIO_TXAGG_ALIGN_SIZE_V1_8814B)
+#define BITS_SDIO_TXAGG_ALIGN_SIZE_V1_8814B                                    \
+	(BIT_MASK_SDIO_TXAGG_ALIGN_SIZE_V1_8814B                               \
+	 << BIT_SHIFT_SDIO_TXAGG_ALIGN_SIZE_V1_8814B)
+#define BIT_CLEAR_SDIO_TXAGG_ALIGN_SIZE_V1_8814B(x)                            \
+	((x) & (~BITS_SDIO_TXAGG_ALIGN_SIZE_V1_8814B))
+#define BIT_GET_SDIO_TXAGG_ALIGN_SIZE_V1_8814B(x)                              \
+	(((x) >> BIT_SHIFT_SDIO_TXAGG_ALIGN_SIZE_V1_8814B) &                   \
+	 BIT_MASK_SDIO_TXAGG_ALIGN_SIZE_V1_8814B)
+#define BIT_SET_SDIO_TXAGG_ALIGN_SIZE_V1_8814B(x, v)                           \
+	(BIT_CLEAR_SDIO_TXAGG_ALIGN_SIZE_V1_8814B(x) |                         \
+	 BIT_SDIO_TXAGG_ALIGN_SIZE_V1_8814B(v))
+
+/* 2 REG_H2C_HEAD_8814B */
+
+#define BIT_SHIFT_H2C_HEAD_V1_8814B 0
+#define BIT_MASK_H2C_HEAD_V1_8814B 0x7ffff
+#define BIT_H2C_HEAD_V1_8814B(x)                                               \
+	(((x) & BIT_MASK_H2C_HEAD_V1_8814B) << BIT_SHIFT_H2C_HEAD_V1_8814B)
+#define BITS_H2C_HEAD_V1_8814B                                                 \
+	(BIT_MASK_H2C_HEAD_V1_8814B << BIT_SHIFT_H2C_HEAD_V1_8814B)
+#define BIT_CLEAR_H2C_HEAD_V1_8814B(x) ((x) & (~BITS_H2C_HEAD_V1_8814B))
+#define BIT_GET_H2C_HEAD_V1_8814B(x)                                           \
+	(((x) >> BIT_SHIFT_H2C_HEAD_V1_8814B) & BIT_MASK_H2C_HEAD_V1_8814B)
+#define BIT_SET_H2C_HEAD_V1_8814B(x, v)                                        \
+	(BIT_CLEAR_H2C_HEAD_V1_8814B(x) | BIT_H2C_HEAD_V1_8814B(v))
+
+/* 2 REG_H2C_TAIL_8814B */
+
+#define BIT_SHIFT_H2C_TAIL_V1_8814B 0
+#define BIT_MASK_H2C_TAIL_V1_8814B 0x7ffff
+#define BIT_H2C_TAIL_V1_8814B(x)                                               \
+	(((x) & BIT_MASK_H2C_TAIL_V1_8814B) << BIT_SHIFT_H2C_TAIL_V1_8814B)
+#define BITS_H2C_TAIL_V1_8814B                                                 \
+	(BIT_MASK_H2C_TAIL_V1_8814B << BIT_SHIFT_H2C_TAIL_V1_8814B)
+#define BIT_CLEAR_H2C_TAIL_V1_8814B(x) ((x) & (~BITS_H2C_TAIL_V1_8814B))
+#define BIT_GET_H2C_TAIL_V1_8814B(x)                                           \
+	(((x) >> BIT_SHIFT_H2C_TAIL_V1_8814B) & BIT_MASK_H2C_TAIL_V1_8814B)
+#define BIT_SET_H2C_TAIL_V1_8814B(x, v)                                        \
+	(BIT_CLEAR_H2C_TAIL_V1_8814B(x) | BIT_H2C_TAIL_V1_8814B(v))
+
+/* 2 REG_H2C_READ_ADDR_8814B */
+
+#define BIT_SHIFT_H2C_READ_ADDR_V1_8814B 0
+#define BIT_MASK_H2C_READ_ADDR_V1_8814B 0x7ffff
+#define BIT_H2C_READ_ADDR_V1_8814B(x)                                          \
+	(((x) & BIT_MASK_H2C_READ_ADDR_V1_8814B)                               \
+	 << BIT_SHIFT_H2C_READ_ADDR_V1_8814B)
+#define BITS_H2C_READ_ADDR_V1_8814B                                            \
+	(BIT_MASK_H2C_READ_ADDR_V1_8814B << BIT_SHIFT_H2C_READ_ADDR_V1_8814B)
+#define BIT_CLEAR_H2C_READ_ADDR_V1_8814B(x)                                    \
+	((x) & (~BITS_H2C_READ_ADDR_V1_8814B))
+#define BIT_GET_H2C_READ_ADDR_V1_8814B(x)                                      \
+	(((x) >> BIT_SHIFT_H2C_READ_ADDR_V1_8814B) &                           \
+	 BIT_MASK_H2C_READ_ADDR_V1_8814B)
+#define BIT_SET_H2C_READ_ADDR_V1_8814B(x, v)                                   \
+	(BIT_CLEAR_H2C_READ_ADDR_V1_8814B(x) | BIT_H2C_READ_ADDR_V1_8814B(v))
+
+/* 2 REG_H2C_WR_ADDR_8814B */
+
+#define BIT_SHIFT_H2C_WR_ADDR_V1_8814B 0
+#define BIT_MASK_H2C_WR_ADDR_V1_8814B 0x7ffff
+#define BIT_H2C_WR_ADDR_V1_8814B(x)                                            \
+	(((x) & BIT_MASK_H2C_WR_ADDR_V1_8814B)                                 \
+	 << BIT_SHIFT_H2C_WR_ADDR_V1_8814B)
+#define BITS_H2C_WR_ADDR_V1_8814B                                              \
+	(BIT_MASK_H2C_WR_ADDR_V1_8814B << BIT_SHIFT_H2C_WR_ADDR_V1_8814B)
+#define BIT_CLEAR_H2C_WR_ADDR_V1_8814B(x) ((x) & (~BITS_H2C_WR_ADDR_V1_8814B))
+#define BIT_GET_H2C_WR_ADDR_V1_8814B(x)                                        \
+	(((x) >> BIT_SHIFT_H2C_WR_ADDR_V1_8814B) &                             \
+	 BIT_MASK_H2C_WR_ADDR_V1_8814B)
+#define BIT_SET_H2C_WR_ADDR_V1_8814B(x, v)                                     \
+	(BIT_CLEAR_H2C_WR_ADDR_V1_8814B(x) | BIT_H2C_WR_ADDR_V1_8814B(v))
+
+/* 2 REG_H2C_INFO_8814B */
+#define BIT_H2C_SPACE_VLD_8814B BIT(3)
+#define BIT_H2C_WR_ADDR_RST_8814B BIT(2)
+
+#define BIT_SHIFT_H2C_LEN_SEL_8814B 0
+#define BIT_MASK_H2C_LEN_SEL_8814B 0x3
+#define BIT_H2C_LEN_SEL_8814B(x)                                               \
+	(((x) & BIT_MASK_H2C_LEN_SEL_8814B) << BIT_SHIFT_H2C_LEN_SEL_8814B)
+#define BITS_H2C_LEN_SEL_8814B                                                 \
+	(BIT_MASK_H2C_LEN_SEL_8814B << BIT_SHIFT_H2C_LEN_SEL_8814B)
+#define BIT_CLEAR_H2C_LEN_SEL_8814B(x) ((x) & (~BITS_H2C_LEN_SEL_8814B))
+#define BIT_GET_H2C_LEN_SEL_8814B(x)                                           \
+	(((x) >> BIT_SHIFT_H2C_LEN_SEL_8814B) & BIT_MASK_H2C_LEN_SEL_8814B)
+#define BIT_SET_H2C_LEN_SEL_8814B(x, v)                                        \
+	(BIT_CLEAR_H2C_LEN_SEL_8814B(x) | BIT_H2C_LEN_SEL_8814B(v))
+
+/* 2 REG_DMA_OQT_0_8814B */
+
+#define BIT_SHIFT_TX_OQT_12_FREE_SPACE_8814B 24
+#define BIT_MASK_TX_OQT_12_FREE_SPACE_8814B 0xff
+#define BIT_TX_OQT_12_FREE_SPACE_8814B(x)                                      \
+	(((x) & BIT_MASK_TX_OQT_12_FREE_SPACE_8814B)                           \
+	 << BIT_SHIFT_TX_OQT_12_FREE_SPACE_8814B)
+#define BITS_TX_OQT_12_FREE_SPACE_8814B                                        \
+	(BIT_MASK_TX_OQT_12_FREE_SPACE_8814B                                   \
+	 << BIT_SHIFT_TX_OQT_12_FREE_SPACE_8814B)
+#define BIT_CLEAR_TX_OQT_12_FREE_SPACE_8814B(x)                                \
+	((x) & (~BITS_TX_OQT_12_FREE_SPACE_8814B))
+#define BIT_GET_TX_OQT_12_FREE_SPACE_8814B(x)                                  \
+	(((x) >> BIT_SHIFT_TX_OQT_12_FREE_SPACE_8814B) &                       \
+	 BIT_MASK_TX_OQT_12_FREE_SPACE_8814B)
+#define BIT_SET_TX_OQT_12_FREE_SPACE_8814B(x, v)                               \
+	(BIT_CLEAR_TX_OQT_12_FREE_SPACE_8814B(x) |                             \
+	 BIT_TX_OQT_12_FREE_SPACE_8814B(v))
+
+#define BIT_SHIFT_TX_OQT_8_11_FREE_SPACE_8814B 16
+#define BIT_MASK_TX_OQT_8_11_FREE_SPACE_8814B 0xff
+#define BIT_TX_OQT_8_11_FREE_SPACE_8814B(x)                                    \
+	(((x) & BIT_MASK_TX_OQT_8_11_FREE_SPACE_8814B)                         \
+	 << BIT_SHIFT_TX_OQT_8_11_FREE_SPACE_8814B)
+#define BITS_TX_OQT_8_11_FREE_SPACE_8814B                                      \
+	(BIT_MASK_TX_OQT_8_11_FREE_SPACE_8814B                                 \
+	 << BIT_SHIFT_TX_OQT_8_11_FREE_SPACE_8814B)
+#define BIT_CLEAR_TX_OQT_8_11_FREE_SPACE_8814B(x)                              \
+	((x) & (~BITS_TX_OQT_8_11_FREE_SPACE_8814B))
+#define BIT_GET_TX_OQT_8_11_FREE_SPACE_8814B(x)                                \
+	(((x) >> BIT_SHIFT_TX_OQT_8_11_FREE_SPACE_8814B) &                     \
+	 BIT_MASK_TX_OQT_8_11_FREE_SPACE_8814B)
+#define BIT_SET_TX_OQT_8_11_FREE_SPACE_8814B(x, v)                             \
+	(BIT_CLEAR_TX_OQT_8_11_FREE_SPACE_8814B(x) |                           \
+	 BIT_TX_OQT_8_11_FREE_SPACE_8814B(v))
+
+#define BIT_SHIFT_TX_OQT_4_7_FREE_SPACE_8814B 8
+#define BIT_MASK_TX_OQT_4_7_FREE_SPACE_8814B 0xff
+#define BIT_TX_OQT_4_7_FREE_SPACE_8814B(x)                                     \
+	(((x) & BIT_MASK_TX_OQT_4_7_FREE_SPACE_8814B)                          \
+	 << BIT_SHIFT_TX_OQT_4_7_FREE_SPACE_8814B)
+#define BITS_TX_OQT_4_7_FREE_SPACE_8814B                                       \
+	(BIT_MASK_TX_OQT_4_7_FREE_SPACE_8814B                                  \
+	 << BIT_SHIFT_TX_OQT_4_7_FREE_SPACE_8814B)
+#define BIT_CLEAR_TX_OQT_4_7_FREE_SPACE_8814B(x)                               \
+	((x) & (~BITS_TX_OQT_4_7_FREE_SPACE_8814B))
+#define BIT_GET_TX_OQT_4_7_FREE_SPACE_8814B(x)                                 \
+	(((x) >> BIT_SHIFT_TX_OQT_4_7_FREE_SPACE_8814B) &                      \
+	 BIT_MASK_TX_OQT_4_7_FREE_SPACE_8814B)
+#define BIT_SET_TX_OQT_4_7_FREE_SPACE_8814B(x, v)                              \
+	(BIT_CLEAR_TX_OQT_4_7_FREE_SPACE_8814B(x) |                            \
+	 BIT_TX_OQT_4_7_FREE_SPACE_8814B(v))
+
+#define BIT_SHIFT_TX_OQT_0_3_FREE_SPACE_8814B 0
+#define BIT_MASK_TX_OQT_0_3_FREE_SPACE_8814B 0xff
+#define BIT_TX_OQT_0_3_FREE_SPACE_8814B(x)                                     \
+	(((x) & BIT_MASK_TX_OQT_0_3_FREE_SPACE_8814B)                          \
+	 << BIT_SHIFT_TX_OQT_0_3_FREE_SPACE_8814B)
+#define BITS_TX_OQT_0_3_FREE_SPACE_8814B                                       \
+	(BIT_MASK_TX_OQT_0_3_FREE_SPACE_8814B                                  \
+	 << BIT_SHIFT_TX_OQT_0_3_FREE_SPACE_8814B)
+#define BIT_CLEAR_TX_OQT_0_3_FREE_SPACE_8814B(x)                               \
+	((x) & (~BITS_TX_OQT_0_3_FREE_SPACE_8814B))
+#define BIT_GET_TX_OQT_0_3_FREE_SPACE_8814B(x)                                 \
+	(((x) >> BIT_SHIFT_TX_OQT_0_3_FREE_SPACE_8814B) &                      \
+	 BIT_MASK_TX_OQT_0_3_FREE_SPACE_8814B)
+#define BIT_SET_TX_OQT_0_3_FREE_SPACE_8814B(x, v)                              \
+	(BIT_CLEAR_TX_OQT_0_3_FREE_SPACE_8814B(x) |                            \
+	 BIT_TX_OQT_0_3_FREE_SPACE_8814B(v))
+
+/* 2 REG_DMA_OQT_1_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+#define BIT_SHIFT_TX_OQT_16_FREE_SPACE_8814B 16
+#define BIT_MASK_TX_OQT_16_FREE_SPACE_8814B 0xff
+#define BIT_TX_OQT_16_FREE_SPACE_8814B(x)                                      \
+	(((x) & BIT_MASK_TX_OQT_16_FREE_SPACE_8814B)                           \
+	 << BIT_SHIFT_TX_OQT_16_FREE_SPACE_8814B)
+#define BITS_TX_OQT_16_FREE_SPACE_8814B                                        \
+	(BIT_MASK_TX_OQT_16_FREE_SPACE_8814B                                   \
+	 << BIT_SHIFT_TX_OQT_16_FREE_SPACE_8814B)
+#define BIT_CLEAR_TX_OQT_16_FREE_SPACE_8814B(x)                                \
+	((x) & (~BITS_TX_OQT_16_FREE_SPACE_8814B))
+#define BIT_GET_TX_OQT_16_FREE_SPACE_8814B(x)                                  \
+	(((x) >> BIT_SHIFT_TX_OQT_16_FREE_SPACE_8814B) &                       \
+	 BIT_MASK_TX_OQT_16_FREE_SPACE_8814B)
+#define BIT_SET_TX_OQT_16_FREE_SPACE_8814B(x, v)                               \
+	(BIT_CLEAR_TX_OQT_16_FREE_SPACE_8814B(x) |                             \
+	 BIT_TX_OQT_16_FREE_SPACE_8814B(v))
+
+#define BIT_SHIFT_TX_OQT_14_15_FREE_SPACE_8814B 8
+#define BIT_MASK_TX_OQT_14_15_FREE_SPACE_8814B 0xff
+#define BIT_TX_OQT_14_15_FREE_SPACE_8814B(x)                                   \
+	(((x) & BIT_MASK_TX_OQT_14_15_FREE_SPACE_8814B)                        \
+	 << BIT_SHIFT_TX_OQT_14_15_FREE_SPACE_8814B)
+#define BITS_TX_OQT_14_15_FREE_SPACE_8814B                                     \
+	(BIT_MASK_TX_OQT_14_15_FREE_SPACE_8814B                                \
+	 << BIT_SHIFT_TX_OQT_14_15_FREE_SPACE_8814B)
+#define BIT_CLEAR_TX_OQT_14_15_FREE_SPACE_8814B(x)                             \
+	((x) & (~BITS_TX_OQT_14_15_FREE_SPACE_8814B))
+#define BIT_GET_TX_OQT_14_15_FREE_SPACE_8814B(x)                               \
+	(((x) >> BIT_SHIFT_TX_OQT_14_15_FREE_SPACE_8814B) &                    \
+	 BIT_MASK_TX_OQT_14_15_FREE_SPACE_8814B)
+#define BIT_SET_TX_OQT_14_15_FREE_SPACE_8814B(x, v)                            \
+	(BIT_CLEAR_TX_OQT_14_15_FREE_SPACE_8814B(x) |                          \
+	 BIT_TX_OQT_14_15_FREE_SPACE_8814B(v))
+
+#define BIT_SHIFT_TX_OQT_13_FREE_SPACE_8814B 0
+#define BIT_MASK_TX_OQT_13_FREE_SPACE_8814B 0xff
+#define BIT_TX_OQT_13_FREE_SPACE_8814B(x)                                      \
+	(((x) & BIT_MASK_TX_OQT_13_FREE_SPACE_8814B)                           \
+	 << BIT_SHIFT_TX_OQT_13_FREE_SPACE_8814B)
+#define BITS_TX_OQT_13_FREE_SPACE_8814B                                        \
+	(BIT_MASK_TX_OQT_13_FREE_SPACE_8814B                                   \
+	 << BIT_SHIFT_TX_OQT_13_FREE_SPACE_8814B)
+#define BIT_CLEAR_TX_OQT_13_FREE_SPACE_8814B(x)                                \
+	((x) & (~BITS_TX_OQT_13_FREE_SPACE_8814B))
+#define BIT_GET_TX_OQT_13_FREE_SPACE_8814B(x)                                  \
+	(((x) >> BIT_SHIFT_TX_OQT_13_FREE_SPACE_8814B) &                       \
+	 BIT_MASK_TX_OQT_13_FREE_SPACE_8814B)
+#define BIT_SET_TX_OQT_13_FREE_SPACE_8814B(x, v)                               \
+	(BIT_CLEAR_TX_OQT_13_FREE_SPACE_8814B(x) |                             \
+	 BIT_TX_OQT_13_FREE_SPACE_8814B(v))
+
+/* 2 REG_RXDMA_AGG_PG_TH_8814B */
+#define BIT_DMA_STORE_8814B BIT(31)
+
+/* 2 REG_NOT_VALID_8814B */
+#define BIT_EN_PRE_CALC_8814B BIT(29)
+#define BIT_RXAGG_SW_EN_8814B BIT(28)
+#define BIT_RXAGG_SW_TRIG_8814B BIT(27)
+
+/* 2 REG_NOT_VALID_8814B */
+
+#define BIT_SHIFT_DMA_AGG_TO_V1_8814B 8
+#define BIT_MASK_DMA_AGG_TO_V1_8814B 0xff
+#define BIT_DMA_AGG_TO_V1_8814B(x)                                             \
+	(((x) & BIT_MASK_DMA_AGG_TO_V1_8814B) << BIT_SHIFT_DMA_AGG_TO_V1_8814B)
+#define BITS_DMA_AGG_TO_V1_8814B                                               \
+	(BIT_MASK_DMA_AGG_TO_V1_8814B << BIT_SHIFT_DMA_AGG_TO_V1_8814B)
+#define BIT_CLEAR_DMA_AGG_TO_V1_8814B(x) ((x) & (~BITS_DMA_AGG_TO_V1_8814B))
+#define BIT_GET_DMA_AGG_TO_V1_8814B(x)                                         \
+	(((x) >> BIT_SHIFT_DMA_AGG_TO_V1_8814B) & BIT_MASK_DMA_AGG_TO_V1_8814B)
+#define BIT_SET_DMA_AGG_TO_V1_8814B(x, v)                                      \
+	(BIT_CLEAR_DMA_AGG_TO_V1_8814B(x) | BIT_DMA_AGG_TO_V1_8814B(v))
+
+#define BIT_SHIFT_RXDMA_AGG_PG_TH_8814B 0
+#define BIT_MASK_RXDMA_AGG_PG_TH_8814B 0xff
+#define BIT_RXDMA_AGG_PG_TH_8814B(x)                                           \
+	(((x) & BIT_MASK_RXDMA_AGG_PG_TH_8814B)                                \
+	 << BIT_SHIFT_RXDMA_AGG_PG_TH_8814B)
+#define BITS_RXDMA_AGG_PG_TH_8814B                                             \
+	(BIT_MASK_RXDMA_AGG_PG_TH_8814B << BIT_SHIFT_RXDMA_AGG_PG_TH_8814B)
+#define BIT_CLEAR_RXDMA_AGG_PG_TH_8814B(x) ((x) & (~BITS_RXDMA_AGG_PG_TH_8814B))
+#define BIT_GET_RXDMA_AGG_PG_TH_8814B(x)                                       \
+	(((x) >> BIT_SHIFT_RXDMA_AGG_PG_TH_8814B) &                            \
+	 BIT_MASK_RXDMA_AGG_PG_TH_8814B)
+#define BIT_SET_RXDMA_AGG_PG_TH_8814B(x, v)                                    \
+	(BIT_CLEAR_RXDMA_AGG_PG_TH_8814B(x) | BIT_RXDMA_AGG_PG_TH_8814B(v))
+
+/* 2 REG_RXDMA_CTRL_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+#define BIT_SHIFT_FW_UPD_RDPTR19_TO_16_8814B 20
+#define BIT_MASK_FW_UPD_RDPTR19_TO_16_8814B 0xf
+#define BIT_FW_UPD_RDPTR19_TO_16_8814B(x)                                      \
+	(((x) & BIT_MASK_FW_UPD_RDPTR19_TO_16_8814B)                           \
+	 << BIT_SHIFT_FW_UPD_RDPTR19_TO_16_8814B)
+#define BITS_FW_UPD_RDPTR19_TO_16_8814B                                        \
+	(BIT_MASK_FW_UPD_RDPTR19_TO_16_8814B                                   \
+	 << BIT_SHIFT_FW_UPD_RDPTR19_TO_16_8814B)
+#define BIT_CLEAR_FW_UPD_RDPTR19_TO_16_8814B(x)                                \
+	((x) & (~BITS_FW_UPD_RDPTR19_TO_16_8814B))
+#define BIT_GET_FW_UPD_RDPTR19_TO_16_8814B(x)                                  \
+	(((x) >> BIT_SHIFT_FW_UPD_RDPTR19_TO_16_8814B) &                       \
+	 BIT_MASK_FW_UPD_RDPTR19_TO_16_8814B)
+#define BIT_SET_FW_UPD_RDPTR19_TO_16_8814B(x, v)                               \
+	(BIT_CLEAR_FW_UPD_RDPTR19_TO_16_8814B(x) |                             \
+	 BIT_FW_UPD_RDPTR19_TO_16_8814B(v))
+
+#define BIT_RXDMA_REQ_8814B BIT(19)
+#define BIT_RW_RELEASE_EN_8814B BIT(18)
+#define BIT_RXDMA_IDLE_8814B BIT(17)
+#define BIT_RXPKT_RELEASE_POLL_8814B BIT(16)
+
+#define BIT_SHIFT_FW_UPD_RDPTR_8814B 0
+#define BIT_MASK_FW_UPD_RDPTR_8814B 0xffff
+#define BIT_FW_UPD_RDPTR_8814B(x)                                              \
+	(((x) & BIT_MASK_FW_UPD_RDPTR_8814B) << BIT_SHIFT_FW_UPD_RDPTR_8814B)
+#define BITS_FW_UPD_RDPTR_8814B                                                \
+	(BIT_MASK_FW_UPD_RDPTR_8814B << BIT_SHIFT_FW_UPD_RDPTR_8814B)
+#define BIT_CLEAR_FW_UPD_RDPTR_8814B(x) ((x) & (~BITS_FW_UPD_RDPTR_8814B))
+#define BIT_GET_FW_UPD_RDPTR_8814B(x)                                          \
+	(((x) >> BIT_SHIFT_FW_UPD_RDPTR_8814B) & BIT_MASK_FW_UPD_RDPTR_8814B)
+#define BIT_SET_FW_UPD_RDPTR_8814B(x, v)                                       \
+	(BIT_CLEAR_FW_UPD_RDPTR_8814B(x) | BIT_FW_UPD_RDPTR_8814B(v))
+
+/* 2 REG_RXDMA_STATUS_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+#define BIT_C2H_PKT_OVF_8814B BIT(7)
+#define BIT_AGG_CONFGI_ISSUE_8814B BIT(6)
+#define BIT_FW_POLL_ISSUE_8814B BIT(5)
+#define BIT_RX_DATA_UDN_8814B BIT(4)
+#define BIT_RX_SFF_UDN_8814B BIT(3)
+#define BIT_RX_SFF_OVF_8814B BIT(2)
+#define BIT_RXPKT_OVF_8814B BIT(0)
+
+/* 2 REG_RXDMA_DPR_8814B */
+
+#define BIT_SHIFT_RDE_DEBUG_8814B 0
+#define BIT_MASK_RDE_DEBUG_8814B 0xffffffffL
+#define BIT_RDE_DEBUG_8814B(x)                                                 \
+	(((x) & BIT_MASK_RDE_DEBUG_8814B) << BIT_SHIFT_RDE_DEBUG_8814B)
+#define BITS_RDE_DEBUG_8814B                                                   \
+	(BIT_MASK_RDE_DEBUG_8814B << BIT_SHIFT_RDE_DEBUG_8814B)
+#define BIT_CLEAR_RDE_DEBUG_8814B(x) ((x) & (~BITS_RDE_DEBUG_8814B))
+#define BIT_GET_RDE_DEBUG_8814B(x)                                             \
+	(((x) >> BIT_SHIFT_RDE_DEBUG_8814B) & BIT_MASK_RDE_DEBUG_8814B)
+#define BIT_SET_RDE_DEBUG_8814B(x, v)                                          \
+	(BIT_CLEAR_RDE_DEBUG_8814B(x) | BIT_RDE_DEBUG_8814B(v))
+
+/* 2 REG_RXDMA_MODE_8814B */
+
+#define BIT_SHIFT_PKTNUM_TH_V2_8814B 24
+#define BIT_MASK_PKTNUM_TH_V2_8814B 0x1f
+#define BIT_PKTNUM_TH_V2_8814B(x)                                              \
+	(((x) & BIT_MASK_PKTNUM_TH_V2_8814B) << BIT_SHIFT_PKTNUM_TH_V2_8814B)
+#define BITS_PKTNUM_TH_V2_8814B                                                \
+	(BIT_MASK_PKTNUM_TH_V2_8814B << BIT_SHIFT_PKTNUM_TH_V2_8814B)
+#define BIT_CLEAR_PKTNUM_TH_V2_8814B(x) ((x) & (~BITS_PKTNUM_TH_V2_8814B))
+#define BIT_GET_PKTNUM_TH_V2_8814B(x)                                          \
+	(((x) >> BIT_SHIFT_PKTNUM_TH_V2_8814B) & BIT_MASK_PKTNUM_TH_V2_8814B)
+#define BIT_SET_PKTNUM_TH_V2_8814B(x, v)                                       \
+	(BIT_CLEAR_PKTNUM_TH_V2_8814B(x) | BIT_PKTNUM_TH_V2_8814B(v))
+
+#define BIT_TXBA_BREAK_USBAGG_8814B BIT(23)
+
+#define BIT_SHIFT_PKTLEN_PARA_8814B 16
+#define BIT_MASK_PKTLEN_PARA_8814B 0x7
+#define BIT_PKTLEN_PARA_8814B(x)                                               \
+	(((x) & BIT_MASK_PKTLEN_PARA_8814B) << BIT_SHIFT_PKTLEN_PARA_8814B)
+#define BITS_PKTLEN_PARA_8814B                                                 \
+	(BIT_MASK_PKTLEN_PARA_8814B << BIT_SHIFT_PKTLEN_PARA_8814B)
+#define BIT_CLEAR_PKTLEN_PARA_8814B(x) ((x) & (~BITS_PKTLEN_PARA_8814B))
+#define BIT_GET_PKTLEN_PARA_8814B(x)                                           \
+	(((x) >> BIT_SHIFT_PKTLEN_PARA_8814B) & BIT_MASK_PKTLEN_PARA_8814B)
+#define BIT_SET_PKTLEN_PARA_8814B(x, v)                                        \
+	(BIT_CLEAR_PKTLEN_PARA_8814B(x) | BIT_PKTLEN_PARA_8814B(v))
+
+#define BIT_RX_DBG_SEL_8814B BIT(7)
+#define BIT_EN_SPD_8814B BIT(6)
+
+#define BIT_SHIFT_BURST_SIZE_8814B 4
+#define BIT_MASK_BURST_SIZE_8814B 0x3
+#define BIT_BURST_SIZE_8814B(x)                                                \
+	(((x) & BIT_MASK_BURST_SIZE_8814B) << BIT_SHIFT_BURST_SIZE_8814B)
+#define BITS_BURST_SIZE_8814B                                                  \
+	(BIT_MASK_BURST_SIZE_8814B << BIT_SHIFT_BURST_SIZE_8814B)
+#define BIT_CLEAR_BURST_SIZE_8814B(x) ((x) & (~BITS_BURST_SIZE_8814B))
+#define BIT_GET_BURST_SIZE_8814B(x)                                            \
+	(((x) >> BIT_SHIFT_BURST_SIZE_8814B) & BIT_MASK_BURST_SIZE_8814B)
+#define BIT_SET_BURST_SIZE_8814B(x, v)                                         \
+	(BIT_CLEAR_BURST_SIZE_8814B(x) | BIT_BURST_SIZE_8814B(v))
+
+#define BIT_SHIFT_BURST_CNT_8814B 2
+#define BIT_MASK_BURST_CNT_8814B 0x3
+#define BIT_BURST_CNT_8814B(x)                                                 \
+	(((x) & BIT_MASK_BURST_CNT_8814B) << BIT_SHIFT_BURST_CNT_8814B)
+#define BITS_BURST_CNT_8814B                                                   \
+	(BIT_MASK_BURST_CNT_8814B << BIT_SHIFT_BURST_CNT_8814B)
+#define BIT_CLEAR_BURST_CNT_8814B(x) ((x) & (~BITS_BURST_CNT_8814B))
+#define BIT_GET_BURST_CNT_8814B(x)                                             \
+	(((x) >> BIT_SHIFT_BURST_CNT_8814B) & BIT_MASK_BURST_CNT_8814B)
+#define BIT_SET_BURST_CNT_8814B(x, v)                                          \
+	(BIT_CLEAR_BURST_CNT_8814B(x) | BIT_BURST_CNT_8814B(v))
+
+#define BIT_DMA_MODE_8814B BIT(1)
+
+/* 2 REG_C2H_PKT_8814B */
+
+#define BIT_SHIFT_R_C2H_STR_ADDR_16_TO_19_8814B 24
+#define BIT_MASK_R_C2H_STR_ADDR_16_TO_19_8814B 0xf
+#define BIT_R_C2H_STR_ADDR_16_TO_19_8814B(x)                                   \
+	(((x) & BIT_MASK_R_C2H_STR_ADDR_16_TO_19_8814B)                        \
+	 << BIT_SHIFT_R_C2H_STR_ADDR_16_TO_19_8814B)
+#define BITS_R_C2H_STR_ADDR_16_TO_19_8814B                                     \
+	(BIT_MASK_R_C2H_STR_ADDR_16_TO_19_8814B                                \
+	 << BIT_SHIFT_R_C2H_STR_ADDR_16_TO_19_8814B)
+#define BIT_CLEAR_R_C2H_STR_ADDR_16_TO_19_8814B(x)                             \
+	((x) & (~BITS_R_C2H_STR_ADDR_16_TO_19_8814B))
+#define BIT_GET_R_C2H_STR_ADDR_16_TO_19_8814B(x)                               \
+	(((x) >> BIT_SHIFT_R_C2H_STR_ADDR_16_TO_19_8814B) &                    \
+	 BIT_MASK_R_C2H_STR_ADDR_16_TO_19_8814B)
+#define BIT_SET_R_C2H_STR_ADDR_16_TO_19_8814B(x, v)                            \
+	(BIT_CLEAR_R_C2H_STR_ADDR_16_TO_19_8814B(x) |                          \
+	 BIT_R_C2H_STR_ADDR_16_TO_19_8814B(v))
+
+#define BIT_R_C2H_PKT_REQ_8814B BIT(16)
+
+#define BIT_SHIFT_R_C2H_STR_ADDR_8814B 0
+#define BIT_MASK_R_C2H_STR_ADDR_8814B 0xffff
+#define BIT_R_C2H_STR_ADDR_8814B(x)                                            \
+	(((x) & BIT_MASK_R_C2H_STR_ADDR_8814B)                                 \
+	 << BIT_SHIFT_R_C2H_STR_ADDR_8814B)
+#define BITS_R_C2H_STR_ADDR_8814B                                              \
+	(BIT_MASK_R_C2H_STR_ADDR_8814B << BIT_SHIFT_R_C2H_STR_ADDR_8814B)
+#define BIT_CLEAR_R_C2H_STR_ADDR_8814B(x) ((x) & (~BITS_R_C2H_STR_ADDR_8814B))
+#define BIT_GET_R_C2H_STR_ADDR_8814B(x)                                        \
+	(((x) >> BIT_SHIFT_R_C2H_STR_ADDR_8814B) &                             \
+	 BIT_MASK_R_C2H_STR_ADDR_8814B)
+#define BIT_SET_R_C2H_STR_ADDR_8814B(x, v)                                     \
+	(BIT_CLEAR_R_C2H_STR_ADDR_8814B(x) | BIT_R_C2H_STR_ADDR_8814B(v))
+
+/* 2 REG_FWFF_C2H_8814B */
+
+#define BIT_SHIFT_C2H_DMA_ADDR_8814B 0
+#define BIT_MASK_C2H_DMA_ADDR_8814B 0x3ffff
+#define BIT_C2H_DMA_ADDR_8814B(x)                                              \
+	(((x) & BIT_MASK_C2H_DMA_ADDR_8814B) << BIT_SHIFT_C2H_DMA_ADDR_8814B)
+#define BITS_C2H_DMA_ADDR_8814B                                                \
+	(BIT_MASK_C2H_DMA_ADDR_8814B << BIT_SHIFT_C2H_DMA_ADDR_8814B)
+#define BIT_CLEAR_C2H_DMA_ADDR_8814B(x) ((x) & (~BITS_C2H_DMA_ADDR_8814B))
+#define BIT_GET_C2H_DMA_ADDR_8814B(x)                                          \
+	(((x) >> BIT_SHIFT_C2H_DMA_ADDR_8814B) & BIT_MASK_C2H_DMA_ADDR_8814B)
+#define BIT_SET_C2H_DMA_ADDR_8814B(x, v)                                       \
+	(BIT_CLEAR_C2H_DMA_ADDR_8814B(x) | BIT_C2H_DMA_ADDR_8814B(v))
+
+/* 2 REG_FWFF_CTRL_8814B */
+#define BIT_FWFF_DMAPKT_REQ_8814B BIT(31)
+
+#define BIT_SHIFT_FWFF_DMA_PKT_NUM_V1_8814B 16
+#define BIT_MASK_FWFF_DMA_PKT_NUM_V1_8814B 0x7fff
+#define BIT_FWFF_DMA_PKT_NUM_V1_8814B(x)                                       \
+	(((x) & BIT_MASK_FWFF_DMA_PKT_NUM_V1_8814B)                            \
+	 << BIT_SHIFT_FWFF_DMA_PKT_NUM_V1_8814B)
+#define BITS_FWFF_DMA_PKT_NUM_V1_8814B                                         \
+	(BIT_MASK_FWFF_DMA_PKT_NUM_V1_8814B                                    \
+	 << BIT_SHIFT_FWFF_DMA_PKT_NUM_V1_8814B)
+#define BIT_CLEAR_FWFF_DMA_PKT_NUM_V1_8814B(x)                                 \
+	((x) & (~BITS_FWFF_DMA_PKT_NUM_V1_8814B))
+#define BIT_GET_FWFF_DMA_PKT_NUM_V1_8814B(x)                                   \
+	(((x) >> BIT_SHIFT_FWFF_DMA_PKT_NUM_V1_8814B) &                        \
+	 BIT_MASK_FWFF_DMA_PKT_NUM_V1_8814B)
+#define BIT_SET_FWFF_DMA_PKT_NUM_V1_8814B(x, v)                                \
+	(BIT_CLEAR_FWFF_DMA_PKT_NUM_V1_8814B(x) |                              \
+	 BIT_FWFF_DMA_PKT_NUM_V1_8814B(v))
+
+#define BIT_SHIFT_FWFF_STR_ADDR_8814B 0
+#define BIT_MASK_FWFF_STR_ADDR_8814B 0xffff
+#define BIT_FWFF_STR_ADDR_8814B(x)                                             \
+	(((x) & BIT_MASK_FWFF_STR_ADDR_8814B) << BIT_SHIFT_FWFF_STR_ADDR_8814B)
+#define BITS_FWFF_STR_ADDR_8814B                                               \
+	(BIT_MASK_FWFF_STR_ADDR_8814B << BIT_SHIFT_FWFF_STR_ADDR_8814B)
+#define BIT_CLEAR_FWFF_STR_ADDR_8814B(x) ((x) & (~BITS_FWFF_STR_ADDR_8814B))
+#define BIT_GET_FWFF_STR_ADDR_8814B(x)                                         \
+	(((x) >> BIT_SHIFT_FWFF_STR_ADDR_8814B) & BIT_MASK_FWFF_STR_ADDR_8814B)
+#define BIT_SET_FWFF_STR_ADDR_8814B(x, v)                                      \
+	(BIT_CLEAR_FWFF_STR_ADDR_8814B(x) | BIT_FWFF_STR_ADDR_8814B(v))
+
+/* 2 REG_FWFF_PKT_INFO_8814B */
+
+#define BIT_SHIFT_FWFF_PKT_READ_ADDR_8814B 16
+#define BIT_MASK_FWFF_PKT_READ_ADDR_8814B 0xffff
+#define BIT_FWFF_PKT_READ_ADDR_8814B(x)                                        \
+	(((x) & BIT_MASK_FWFF_PKT_READ_ADDR_8814B)                             \
+	 << BIT_SHIFT_FWFF_PKT_READ_ADDR_8814B)
+#define BITS_FWFF_PKT_READ_ADDR_8814B                                          \
+	(BIT_MASK_FWFF_PKT_READ_ADDR_8814B                                     \
+	 << BIT_SHIFT_FWFF_PKT_READ_ADDR_8814B)
+#define BIT_CLEAR_FWFF_PKT_READ_ADDR_8814B(x)                                  \
+	((x) & (~BITS_FWFF_PKT_READ_ADDR_8814B))
+#define BIT_GET_FWFF_PKT_READ_ADDR_8814B(x)                                    \
+	(((x) >> BIT_SHIFT_FWFF_PKT_READ_ADDR_8814B) &                         \
+	 BIT_MASK_FWFF_PKT_READ_ADDR_8814B)
+#define BIT_SET_FWFF_PKT_READ_ADDR_8814B(x, v)                                 \
+	(BIT_CLEAR_FWFF_PKT_READ_ADDR_8814B(x) |                               \
+	 BIT_FWFF_PKT_READ_ADDR_8814B(v))
+
+#define BIT_SHIFT_FWFF_PKT_WRITE_ADDR_8814B 0
+#define BIT_MASK_FWFF_PKT_WRITE_ADDR_8814B 0xffff
+#define BIT_FWFF_PKT_WRITE_ADDR_8814B(x)                                       \
+	(((x) & BIT_MASK_FWFF_PKT_WRITE_ADDR_8814B)                            \
+	 << BIT_SHIFT_FWFF_PKT_WRITE_ADDR_8814B)
+#define BITS_FWFF_PKT_WRITE_ADDR_8814B                                         \
+	(BIT_MASK_FWFF_PKT_WRITE_ADDR_8814B                                    \
+	 << BIT_SHIFT_FWFF_PKT_WRITE_ADDR_8814B)
+#define BIT_CLEAR_FWFF_PKT_WRITE_ADDR_8814B(x)                                 \
+	((x) & (~BITS_FWFF_PKT_WRITE_ADDR_8814B))
+#define BIT_GET_FWFF_PKT_WRITE_ADDR_8814B(x)                                   \
+	(((x) >> BIT_SHIFT_FWFF_PKT_WRITE_ADDR_8814B) &                        \
+	 BIT_MASK_FWFF_PKT_WRITE_ADDR_8814B)
+#define BIT_SET_FWFF_PKT_WRITE_ADDR_8814B(x, v)                                \
+	(BIT_CLEAR_FWFF_PKT_WRITE_ADDR_8814B(x) |                              \
+	 BIT_FWFF_PKT_WRITE_ADDR_8814B(v))
+
+/* 2 REG_FWFF_PKT_INFO2_8814B */
+
+#define BIT_SHIFT_FWFF_PKT_QUEUED_V1_8814B 0
+#define BIT_MASK_FWFF_PKT_QUEUED_V1_8814B 0xffff
+#define BIT_FWFF_PKT_QUEUED_V1_8814B(x)                                        \
+	(((x) & BIT_MASK_FWFF_PKT_QUEUED_V1_8814B)                             \
+	 << BIT_SHIFT_FWFF_PKT_QUEUED_V1_8814B)
+#define BITS_FWFF_PKT_QUEUED_V1_8814B                                          \
+	(BIT_MASK_FWFF_PKT_QUEUED_V1_8814B                                     \
+	 << BIT_SHIFT_FWFF_PKT_QUEUED_V1_8814B)
+#define BIT_CLEAR_FWFF_PKT_QUEUED_V1_8814B(x)                                  \
+	((x) & (~BITS_FWFF_PKT_QUEUED_V1_8814B))
+#define BIT_GET_FWFF_PKT_QUEUED_V1_8814B(x)                                    \
+	(((x) >> BIT_SHIFT_FWFF_PKT_QUEUED_V1_8814B) &                         \
+	 BIT_MASK_FWFF_PKT_QUEUED_V1_8814B)
+#define BIT_SET_FWFF_PKT_QUEUED_V1_8814B(x, v)                                 \
+	(BIT_CLEAR_FWFF_PKT_QUEUED_V1_8814B(x) |                               \
+	 BIT_FWFF_PKT_QUEUED_V1_8814B(v))
+
+/* 2 REG_RXPKTNUM_8814B */
+
+#define BIT_SHIFT_PKT_NUM_WOL_V1_8814B 16
+#define BIT_MASK_PKT_NUM_WOL_V1_8814B 0xffff
+#define BIT_PKT_NUM_WOL_V1_8814B(x)                                            \
+	(((x) & BIT_MASK_PKT_NUM_WOL_V1_8814B)                                 \
+	 << BIT_SHIFT_PKT_NUM_WOL_V1_8814B)
+#define BITS_PKT_NUM_WOL_V1_8814B                                              \
+	(BIT_MASK_PKT_NUM_WOL_V1_8814B << BIT_SHIFT_PKT_NUM_WOL_V1_8814B)
+#define BIT_CLEAR_PKT_NUM_WOL_V1_8814B(x) ((x) & (~BITS_PKT_NUM_WOL_V1_8814B))
+#define BIT_GET_PKT_NUM_WOL_V1_8814B(x)                                        \
+	(((x) >> BIT_SHIFT_PKT_NUM_WOL_V1_8814B) &                             \
+	 BIT_MASK_PKT_NUM_WOL_V1_8814B)
+#define BIT_SET_PKT_NUM_WOL_V1_8814B(x, v)                                     \
+	(BIT_CLEAR_PKT_NUM_WOL_V1_8814B(x) | BIT_PKT_NUM_WOL_V1_8814B(v))
+
+#define BIT_SHIFT_RXPKT_NUM_V1_8814B 0
+#define BIT_MASK_RXPKT_NUM_V1_8814B 0xffff
+#define BIT_RXPKT_NUM_V1_8814B(x)                                              \
+	(((x) & BIT_MASK_RXPKT_NUM_V1_8814B) << BIT_SHIFT_RXPKT_NUM_V1_8814B)
+#define BITS_RXPKT_NUM_V1_8814B                                                \
+	(BIT_MASK_RXPKT_NUM_V1_8814B << BIT_SHIFT_RXPKT_NUM_V1_8814B)
+#define BIT_CLEAR_RXPKT_NUM_V1_8814B(x) ((x) & (~BITS_RXPKT_NUM_V1_8814B))
+#define BIT_GET_RXPKT_NUM_V1_8814B(x)                                          \
+	(((x) >> BIT_SHIFT_RXPKT_NUM_V1_8814B) & BIT_MASK_RXPKT_NUM_V1_8814B)
+#define BIT_SET_RXPKT_NUM_V1_8814B(x, v)                                       \
+	(BIT_CLEAR_RXPKT_NUM_V1_8814B(x) | BIT_RXPKT_NUM_V1_8814B(v))
+
+/* 2 REG_RXPKTNUM_TH_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+#define BIT_SHIFT_RXPKT_NUM_TH_8814B 0
+#define BIT_MASK_RXPKT_NUM_TH_8814B 0xff
+#define BIT_RXPKT_NUM_TH_8814B(x)                                              \
+	(((x) & BIT_MASK_RXPKT_NUM_TH_8814B) << BIT_SHIFT_RXPKT_NUM_TH_8814B)
+#define BITS_RXPKT_NUM_TH_8814B                                                \
+	(BIT_MASK_RXPKT_NUM_TH_8814B << BIT_SHIFT_RXPKT_NUM_TH_8814B)
+#define BIT_CLEAR_RXPKT_NUM_TH_8814B(x) ((x) & (~BITS_RXPKT_NUM_TH_8814B))
+#define BIT_GET_RXPKT_NUM_TH_8814B(x)                                          \
+	(((x) >> BIT_SHIFT_RXPKT_NUM_TH_8814B) & BIT_MASK_RXPKT_NUM_TH_8814B)
+#define BIT_SET_RXPKT_NUM_TH_8814B(x, v)                                       \
+	(BIT_CLEAR_RXPKT_NUM_TH_8814B(x) | BIT_RXPKT_NUM_TH_8814B(v))
+
+/* 2 REG_FW_UPD_RXDES_RDPTR_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+#define BIT_SHIFT_FW_UPD_RXDES_RD_PTR_8814B 0
+#define BIT_MASK_FW_UPD_RXDES_RD_PTR_8814B 0x3ffff
+#define BIT_FW_UPD_RXDES_RD_PTR_8814B(x)                                       \
+	(((x) & BIT_MASK_FW_UPD_RXDES_RD_PTR_8814B)                            \
+	 << BIT_SHIFT_FW_UPD_RXDES_RD_PTR_8814B)
+#define BITS_FW_UPD_RXDES_RD_PTR_8814B                                         \
+	(BIT_MASK_FW_UPD_RXDES_RD_PTR_8814B                                    \
+	 << BIT_SHIFT_FW_UPD_RXDES_RD_PTR_8814B)
+#define BIT_CLEAR_FW_UPD_RXDES_RD_PTR_8814B(x)                                 \
+	((x) & (~BITS_FW_UPD_RXDES_RD_PTR_8814B))
+#define BIT_GET_FW_UPD_RXDES_RD_PTR_8814B(x)                                   \
+	(((x) >> BIT_SHIFT_FW_UPD_RXDES_RD_PTR_8814B) &                        \
+	 BIT_MASK_FW_UPD_RXDES_RD_PTR_8814B)
+#define BIT_SET_FW_UPD_RXDES_RD_PTR_8814B(x, v)                                \
+	(BIT_CLEAR_FW_UPD_RXDES_RD_PTR_8814B(x) |                              \
+	 BIT_FW_UPD_RXDES_RD_PTR_8814B(v))
+
+/* 2 REG_DDMA_CH0SA_8814B */
+
+#define BIT_SHIFT_DDMACH0_SA_8814B 0
+#define BIT_MASK_DDMACH0_SA_8814B 0xffffffffL
+#define BIT_DDMACH0_SA_8814B(x)                                                \
+	(((x) & BIT_MASK_DDMACH0_SA_8814B) << BIT_SHIFT_DDMACH0_SA_8814B)
+#define BITS_DDMACH0_SA_8814B                                                  \
+	(BIT_MASK_DDMACH0_SA_8814B << BIT_SHIFT_DDMACH0_SA_8814B)
+#define BIT_CLEAR_DDMACH0_SA_8814B(x) ((x) & (~BITS_DDMACH0_SA_8814B))
+#define BIT_GET_DDMACH0_SA_8814B(x)                                            \
+	(((x) >> BIT_SHIFT_DDMACH0_SA_8814B) & BIT_MASK_DDMACH0_SA_8814B)
+#define BIT_SET_DDMACH0_SA_8814B(x, v)                                         \
+	(BIT_CLEAR_DDMACH0_SA_8814B(x) | BIT_DDMACH0_SA_8814B(v))
+
+/* 2 REG_DDMA_CH0DA_8814B */
+
+#define BIT_SHIFT_DDMACH0_DA_8814B 0
+#define BIT_MASK_DDMACH0_DA_8814B 0xffffffffL
+#define BIT_DDMACH0_DA_8814B(x)                                                \
+	(((x) & BIT_MASK_DDMACH0_DA_8814B) << BIT_SHIFT_DDMACH0_DA_8814B)
+#define BITS_DDMACH0_DA_8814B                                                  \
+	(BIT_MASK_DDMACH0_DA_8814B << BIT_SHIFT_DDMACH0_DA_8814B)
+#define BIT_CLEAR_DDMACH0_DA_8814B(x) ((x) & (~BITS_DDMACH0_DA_8814B))
+#define BIT_GET_DDMACH0_DA_8814B(x)                                            \
+	(((x) >> BIT_SHIFT_DDMACH0_DA_8814B) & BIT_MASK_DDMACH0_DA_8814B)
+#define BIT_SET_DDMACH0_DA_8814B(x, v)                                         \
+	(BIT_CLEAR_DDMACH0_DA_8814B(x) | BIT_DDMACH0_DA_8814B(v))
+
+/* 2 REG_DDMA_CH0CTRL_8814B */
+#define BIT_DDMACH0_OWN_8814B BIT(31)
+#define BIT_DDMACH0_IDMEM_ERR_8814B BIT(30)
+#define BIT_DDMACH0_CHKSUM_EN_8814B BIT(29)
+#define BIT_DDMACH0_DA_W_DISABLE_8814B BIT(28)
+#define BIT_DDMACH0_CHKSUM_STS_8814B BIT(27)
+#define BIT_DDMACH0_DDMA_MODE_8814B BIT(26)
+#define BIT_DDMACH0_RESET_CHKSUM_STS_8814B BIT(25)
+#define BIT_DDMACH0_CHKSUM_CONT_8814B BIT(24)
+
+#define BIT_SHIFT_DDMACH0_DLEN_8814B 0
+#define BIT_MASK_DDMACH0_DLEN_8814B 0x3ffff
+#define BIT_DDMACH0_DLEN_8814B(x)                                              \
+	(((x) & BIT_MASK_DDMACH0_DLEN_8814B) << BIT_SHIFT_DDMACH0_DLEN_8814B)
+#define BITS_DDMACH0_DLEN_8814B                                                \
+	(BIT_MASK_DDMACH0_DLEN_8814B << BIT_SHIFT_DDMACH0_DLEN_8814B)
+#define BIT_CLEAR_DDMACH0_DLEN_8814B(x) ((x) & (~BITS_DDMACH0_DLEN_8814B))
+#define BIT_GET_DDMACH0_DLEN_8814B(x)                                          \
+	(((x) >> BIT_SHIFT_DDMACH0_DLEN_8814B) & BIT_MASK_DDMACH0_DLEN_8814B)
+#define BIT_SET_DDMACH0_DLEN_8814B(x, v)                                       \
+	(BIT_CLEAR_DDMACH0_DLEN_8814B(x) | BIT_DDMACH0_DLEN_8814B(v))
+
+/* 2 REG_DDMA_CH1SA_8814B */
+
+#define BIT_SHIFT_DDMACH1_SA_8814B 0
+#define BIT_MASK_DDMACH1_SA_8814B 0xffffffffL
+#define BIT_DDMACH1_SA_8814B(x)                                                \
+	(((x) & BIT_MASK_DDMACH1_SA_8814B) << BIT_SHIFT_DDMACH1_SA_8814B)
+#define BITS_DDMACH1_SA_8814B                                                  \
+	(BIT_MASK_DDMACH1_SA_8814B << BIT_SHIFT_DDMACH1_SA_8814B)
+#define BIT_CLEAR_DDMACH1_SA_8814B(x) ((x) & (~BITS_DDMACH1_SA_8814B))
+#define BIT_GET_DDMACH1_SA_8814B(x)                                            \
+	(((x) >> BIT_SHIFT_DDMACH1_SA_8814B) & BIT_MASK_DDMACH1_SA_8814B)
+#define BIT_SET_DDMACH1_SA_8814B(x, v)                                         \
+	(BIT_CLEAR_DDMACH1_SA_8814B(x) | BIT_DDMACH1_SA_8814B(v))
+
+/* 2 REG_DDMA_CH1DA_8814B */
+
+#define BIT_SHIFT_DDMACH1_DA_8814B 0
+#define BIT_MASK_DDMACH1_DA_8814B 0xffffffffL
+#define BIT_DDMACH1_DA_8814B(x)                                                \
+	(((x) & BIT_MASK_DDMACH1_DA_8814B) << BIT_SHIFT_DDMACH1_DA_8814B)
+#define BITS_DDMACH1_DA_8814B                                                  \
+	(BIT_MASK_DDMACH1_DA_8814B << BIT_SHIFT_DDMACH1_DA_8814B)
+#define BIT_CLEAR_DDMACH1_DA_8814B(x) ((x) & (~BITS_DDMACH1_DA_8814B))
+#define BIT_GET_DDMACH1_DA_8814B(x)                                            \
+	(((x) >> BIT_SHIFT_DDMACH1_DA_8814B) & BIT_MASK_DDMACH1_DA_8814B)
+#define BIT_SET_DDMACH1_DA_8814B(x, v)                                         \
+	(BIT_CLEAR_DDMACH1_DA_8814B(x) | BIT_DDMACH1_DA_8814B(v))
+
+/* 2 REG_DDMA_CH1CTRL_8814B */
+#define BIT_DDMACH1_OWN_8814B BIT(31)
+#define BIT_DDMACH1_IDMEM_ERR_8814B BIT(30)
+#define BIT_DDMACH1_CHKSUM_EN_8814B BIT(29)
+#define BIT_DDMACH1_DA_W_DISABLE_8814B BIT(28)
+#define BIT_DDMACH1_CHKSUM_STS_8814B BIT(27)
+#define BIT_DDMACH1_DDMA_MODE_8814B BIT(26)
+#define BIT_DDMACH1_RESET_CHKSUM_STS_8814B BIT(25)
+#define BIT_DDMACH1_CHKSUM_CONT_8814B BIT(24)
+
+#define BIT_SHIFT_DDMACH1_DLEN_8814B 0
+#define BIT_MASK_DDMACH1_DLEN_8814B 0x3ffff
+#define BIT_DDMACH1_DLEN_8814B(x)                                              \
+	(((x) & BIT_MASK_DDMACH1_DLEN_8814B) << BIT_SHIFT_DDMACH1_DLEN_8814B)
+#define BITS_DDMACH1_DLEN_8814B                                                \
+	(BIT_MASK_DDMACH1_DLEN_8814B << BIT_SHIFT_DDMACH1_DLEN_8814B)
+#define BIT_CLEAR_DDMACH1_DLEN_8814B(x) ((x) & (~BITS_DDMACH1_DLEN_8814B))
+#define BIT_GET_DDMACH1_DLEN_8814B(x)                                          \
+	(((x) >> BIT_SHIFT_DDMACH1_DLEN_8814B) & BIT_MASK_DDMACH1_DLEN_8814B)
+#define BIT_SET_DDMACH1_DLEN_8814B(x, v)                                       \
+	(BIT_CLEAR_DDMACH1_DLEN_8814B(x) | BIT_DDMACH1_DLEN_8814B(v))
+
+/* 2 REG_DDMA_CH2SA_8814B */
+
+#define BIT_SHIFT_DDMACH2_SA_8814B 0
+#define BIT_MASK_DDMACH2_SA_8814B 0xffffffffL
+#define BIT_DDMACH2_SA_8814B(x)                                                \
+	(((x) & BIT_MASK_DDMACH2_SA_8814B) << BIT_SHIFT_DDMACH2_SA_8814B)
+#define BITS_DDMACH2_SA_8814B                                                  \
+	(BIT_MASK_DDMACH2_SA_8814B << BIT_SHIFT_DDMACH2_SA_8814B)
+#define BIT_CLEAR_DDMACH2_SA_8814B(x) ((x) & (~BITS_DDMACH2_SA_8814B))
+#define BIT_GET_DDMACH2_SA_8814B(x)                                            \
+	(((x) >> BIT_SHIFT_DDMACH2_SA_8814B) & BIT_MASK_DDMACH2_SA_8814B)
+#define BIT_SET_DDMACH2_SA_8814B(x, v)                                         \
+	(BIT_CLEAR_DDMACH2_SA_8814B(x) | BIT_DDMACH2_SA_8814B(v))
+
+/* 2 REG_DDMA_CH2DA_8814B */
+
+#define BIT_SHIFT_DDMACH2_DA_8814B 0
+#define BIT_MASK_DDMACH2_DA_8814B 0xffffffffL
+#define BIT_DDMACH2_DA_8814B(x)                                                \
+	(((x) & BIT_MASK_DDMACH2_DA_8814B) << BIT_SHIFT_DDMACH2_DA_8814B)
+#define BITS_DDMACH2_DA_8814B                                                  \
+	(BIT_MASK_DDMACH2_DA_8814B << BIT_SHIFT_DDMACH2_DA_8814B)
+#define BIT_CLEAR_DDMACH2_DA_8814B(x) ((x) & (~BITS_DDMACH2_DA_8814B))
+#define BIT_GET_DDMACH2_DA_8814B(x)                                            \
+	(((x) >> BIT_SHIFT_DDMACH2_DA_8814B) & BIT_MASK_DDMACH2_DA_8814B)
+#define BIT_SET_DDMACH2_DA_8814B(x, v)                                         \
+	(BIT_CLEAR_DDMACH2_DA_8814B(x) | BIT_DDMACH2_DA_8814B(v))
+
+/* 2 REG_DDMA_CH2CTRL_8814B */
+#define BIT_DDMACH2_OWN_8814B BIT(31)
+#define BIT_DDMACH2_IDMEM_ERR_8814B BIT(30)
+#define BIT_DDMACH2_CHKSUM_EN_8814B BIT(29)
+#define BIT_DDMACH2_DA_W_DISABLE_8814B BIT(28)
+#define BIT_DDMACH2_CHKSUM_STS_8814B BIT(27)
+#define BIT_DDMACH2_DDMA_MODE_8814B BIT(26)
+#define BIT_DDMACH2_RESET_CHKSUM_STS_8814B BIT(25)
+#define BIT_DDMACH2_CHKSUM_CONT_8814B BIT(24)
+
+#define BIT_SHIFT_DDMACH2_DLEN_8814B 0
+#define BIT_MASK_DDMACH2_DLEN_8814B 0x3ffff
+#define BIT_DDMACH2_DLEN_8814B(x)                                              \
+	(((x) & BIT_MASK_DDMACH2_DLEN_8814B) << BIT_SHIFT_DDMACH2_DLEN_8814B)
+#define BITS_DDMACH2_DLEN_8814B                                                \
+	(BIT_MASK_DDMACH2_DLEN_8814B << BIT_SHIFT_DDMACH2_DLEN_8814B)
+#define BIT_CLEAR_DDMACH2_DLEN_8814B(x) ((x) & (~BITS_DDMACH2_DLEN_8814B))
+#define BIT_GET_DDMACH2_DLEN_8814B(x)                                          \
+	(((x) >> BIT_SHIFT_DDMACH2_DLEN_8814B) & BIT_MASK_DDMACH2_DLEN_8814B)
+#define BIT_SET_DDMACH2_DLEN_8814B(x, v)                                       \
+	(BIT_CLEAR_DDMACH2_DLEN_8814B(x) | BIT_DDMACH2_DLEN_8814B(v))
+
+/* 2 REG_DDMA_CH3SA_8814B */
+
+#define BIT_SHIFT_DDMACH3_SA_8814B 0
+#define BIT_MASK_DDMACH3_SA_8814B 0xffffffffL
+#define BIT_DDMACH3_SA_8814B(x)                                                \
+	(((x) & BIT_MASK_DDMACH3_SA_8814B) << BIT_SHIFT_DDMACH3_SA_8814B)
+#define BITS_DDMACH3_SA_8814B                                                  \
+	(BIT_MASK_DDMACH3_SA_8814B << BIT_SHIFT_DDMACH3_SA_8814B)
+#define BIT_CLEAR_DDMACH3_SA_8814B(x) ((x) & (~BITS_DDMACH3_SA_8814B))
+#define BIT_GET_DDMACH3_SA_8814B(x)                                            \
+	(((x) >> BIT_SHIFT_DDMACH3_SA_8814B) & BIT_MASK_DDMACH3_SA_8814B)
+#define BIT_SET_DDMACH3_SA_8814B(x, v)                                         \
+	(BIT_CLEAR_DDMACH3_SA_8814B(x) | BIT_DDMACH3_SA_8814B(v))
+
+/* 2 REG_DDMA_CH3DA_8814B */
+
+#define BIT_SHIFT_DDMACH3_DA_8814B 0
+#define BIT_MASK_DDMACH3_DA_8814B 0xffffffffL
+#define BIT_DDMACH3_DA_8814B(x)                                                \
+	(((x) & BIT_MASK_DDMACH3_DA_8814B) << BIT_SHIFT_DDMACH3_DA_8814B)
+#define BITS_DDMACH3_DA_8814B                                                  \
+	(BIT_MASK_DDMACH3_DA_8814B << BIT_SHIFT_DDMACH3_DA_8814B)
+#define BIT_CLEAR_DDMACH3_DA_8814B(x) ((x) & (~BITS_DDMACH3_DA_8814B))
+#define BIT_GET_DDMACH3_DA_8814B(x)                                            \
+	(((x) >> BIT_SHIFT_DDMACH3_DA_8814B) & BIT_MASK_DDMACH3_DA_8814B)
+#define BIT_SET_DDMACH3_DA_8814B(x, v)                                         \
+	(BIT_CLEAR_DDMACH3_DA_8814B(x) | BIT_DDMACH3_DA_8814B(v))
+
+/* 2 REG_DDMA_CH3CTRL_8814B */
+#define BIT_DDMACH3_OWN_8814B BIT(31)
+#define BIT_DDMACH3_IDMEM_ERR_8814B BIT(30)
+#define BIT_DDMACH3_CHKSUM_EN_8814B BIT(29)
+#define BIT_DDMACH3_DA_W_DISABLE_8814B BIT(28)
+#define BIT_DDMACH3_CHKSUM_STS_8814B BIT(27)
+#define BIT_DDMACH3_DDMA_MODE_8814B BIT(26)
+#define BIT_DDMACH3_RESET_CHKSUM_STS_8814B BIT(25)
+#define BIT_DDMACH3_CHKSUM_CONT_8814B BIT(24)
+
+#define BIT_SHIFT_DDMACH3_DLEN_8814B 0
+#define BIT_MASK_DDMACH3_DLEN_8814B 0x3ffff
+#define BIT_DDMACH3_DLEN_8814B(x)                                              \
+	(((x) & BIT_MASK_DDMACH3_DLEN_8814B) << BIT_SHIFT_DDMACH3_DLEN_8814B)
+#define BITS_DDMACH3_DLEN_8814B                                                \
+	(BIT_MASK_DDMACH3_DLEN_8814B << BIT_SHIFT_DDMACH3_DLEN_8814B)
+#define BIT_CLEAR_DDMACH3_DLEN_8814B(x) ((x) & (~BITS_DDMACH3_DLEN_8814B))
+#define BIT_GET_DDMACH3_DLEN_8814B(x)                                          \
+	(((x) >> BIT_SHIFT_DDMACH3_DLEN_8814B) & BIT_MASK_DDMACH3_DLEN_8814B)
+#define BIT_SET_DDMACH3_DLEN_8814B(x, v)                                       \
+	(BIT_CLEAR_DDMACH3_DLEN_8814B(x) | BIT_DDMACH3_DLEN_8814B(v))
+
+/* 2 REG_DDMA_CH4SA_8814B */
+
+#define BIT_SHIFT_DDMACH4_SA_8814B 0
+#define BIT_MASK_DDMACH4_SA_8814B 0xffffffffL
+#define BIT_DDMACH4_SA_8814B(x)                                                \
+	(((x) & BIT_MASK_DDMACH4_SA_8814B) << BIT_SHIFT_DDMACH4_SA_8814B)
+#define BITS_DDMACH4_SA_8814B                                                  \
+	(BIT_MASK_DDMACH4_SA_8814B << BIT_SHIFT_DDMACH4_SA_8814B)
+#define BIT_CLEAR_DDMACH4_SA_8814B(x) ((x) & (~BITS_DDMACH4_SA_8814B))
+#define BIT_GET_DDMACH4_SA_8814B(x)                                            \
+	(((x) >> BIT_SHIFT_DDMACH4_SA_8814B) & BIT_MASK_DDMACH4_SA_8814B)
+#define BIT_SET_DDMACH4_SA_8814B(x, v)                                         \
+	(BIT_CLEAR_DDMACH4_SA_8814B(x) | BIT_DDMACH4_SA_8814B(v))
+
+/* 2 REG_DDMA_CH4DA_8814B */
+
+#define BIT_SHIFT_DDMACH4_DA_8814B 0
+#define BIT_MASK_DDMACH4_DA_8814B 0xffffffffL
+#define BIT_DDMACH4_DA_8814B(x)                                                \
+	(((x) & BIT_MASK_DDMACH4_DA_8814B) << BIT_SHIFT_DDMACH4_DA_8814B)
+#define BITS_DDMACH4_DA_8814B                                                  \
+	(BIT_MASK_DDMACH4_DA_8814B << BIT_SHIFT_DDMACH4_DA_8814B)
+#define BIT_CLEAR_DDMACH4_DA_8814B(x) ((x) & (~BITS_DDMACH4_DA_8814B))
+#define BIT_GET_DDMACH4_DA_8814B(x)                                            \
+	(((x) >> BIT_SHIFT_DDMACH4_DA_8814B) & BIT_MASK_DDMACH4_DA_8814B)
+#define BIT_SET_DDMACH4_DA_8814B(x, v)                                         \
+	(BIT_CLEAR_DDMACH4_DA_8814B(x) | BIT_DDMACH4_DA_8814B(v))
+
+/* 2 REG_DDMA_CH4CTRL_8814B */
+#define BIT_DDMACH4_OWN_8814B BIT(31)
+#define BIT_DDMACH4_IDMEM_ERR_8814B BIT(30)
+#define BIT_DDMACH4_CHKSUM_EN_8814B BIT(29)
+#define BIT_DDMACH4_DA_W_DISABLE_8814B BIT(28)
+#define BIT_DDMACH4_CHKSUM_STS_8814B BIT(27)
+#define BIT_DDMACH4_DDMA_MODE_8814B BIT(26)
+#define BIT_DDMACH4_RESET_CHKSUM_STS_8814B BIT(25)
+#define BIT_DDMACH4_CHKSUM_CONT_8814B BIT(24)
+
+#define BIT_SHIFT_DDMACH4_DLEN_8814B 0
+#define BIT_MASK_DDMACH4_DLEN_8814B 0x3ffff
+#define BIT_DDMACH4_DLEN_8814B(x)                                              \
+	(((x) & BIT_MASK_DDMACH4_DLEN_8814B) << BIT_SHIFT_DDMACH4_DLEN_8814B)
+#define BITS_DDMACH4_DLEN_8814B                                                \
+	(BIT_MASK_DDMACH4_DLEN_8814B << BIT_SHIFT_DDMACH4_DLEN_8814B)
+#define BIT_CLEAR_DDMACH4_DLEN_8814B(x) ((x) & (~BITS_DDMACH4_DLEN_8814B))
+#define BIT_GET_DDMACH4_DLEN_8814B(x)                                          \
+	(((x) >> BIT_SHIFT_DDMACH4_DLEN_8814B) & BIT_MASK_DDMACH4_DLEN_8814B)
+#define BIT_SET_DDMACH4_DLEN_8814B(x, v)                                       \
+	(BIT_CLEAR_DDMACH4_DLEN_8814B(x) | BIT_DDMACH4_DLEN_8814B(v))
+
+/* 2 REG_DDMA_CH5SA_8814B */
+
+#define BIT_SHIFT_DDMACH5_SA_8814B 0
+#define BIT_MASK_DDMACH5_SA_8814B 0xffffffffL
+#define BIT_DDMACH5_SA_8814B(x)                                                \
+	(((x) & BIT_MASK_DDMACH5_SA_8814B) << BIT_SHIFT_DDMACH5_SA_8814B)
+#define BITS_DDMACH5_SA_8814B                                                  \
+	(BIT_MASK_DDMACH5_SA_8814B << BIT_SHIFT_DDMACH5_SA_8814B)
+#define BIT_CLEAR_DDMACH5_SA_8814B(x) ((x) & (~BITS_DDMACH5_SA_8814B))
+#define BIT_GET_DDMACH5_SA_8814B(x)                                            \
+	(((x) >> BIT_SHIFT_DDMACH5_SA_8814B) & BIT_MASK_DDMACH5_SA_8814B)
+#define BIT_SET_DDMACH5_SA_8814B(x, v)                                         \
+	(BIT_CLEAR_DDMACH5_SA_8814B(x) | BIT_DDMACH5_SA_8814B(v))
+
+/* 2 REG_DDMA_CH5DA_8814B */
+
+#define BIT_SHIFT_DDMACH5_DA_8814B 0
+#define BIT_MASK_DDMACH5_DA_8814B 0xffffffffL
+#define BIT_DDMACH5_DA_8814B(x)                                                \
+	(((x) & BIT_MASK_DDMACH5_DA_8814B) << BIT_SHIFT_DDMACH5_DA_8814B)
+#define BITS_DDMACH5_DA_8814B                                                  \
+	(BIT_MASK_DDMACH5_DA_8814B << BIT_SHIFT_DDMACH5_DA_8814B)
+#define BIT_CLEAR_DDMACH5_DA_8814B(x) ((x) & (~BITS_DDMACH5_DA_8814B))
+#define BIT_GET_DDMACH5_DA_8814B(x)                                            \
+	(((x) >> BIT_SHIFT_DDMACH5_DA_8814B) & BIT_MASK_DDMACH5_DA_8814B)
+#define BIT_SET_DDMACH5_DA_8814B(x, v)                                         \
+	(BIT_CLEAR_DDMACH5_DA_8814B(x) | BIT_DDMACH5_DA_8814B(v))
+
+/* 2 REG_DDMA_CH5CTRL_8814B */
+#define BIT_DDMACH5_OWN_8814B BIT(31)
+#define BIT_DDMACH5_IDMEM_ERR_8814B BIT(30)
+#define BIT_DDMACH5_CHKSUM_EN_8814B BIT(29)
+#define BIT_DDMACH5_DA_W_DISABLE_8814B BIT(28)
+#define BIT_DDMACH5_CHKSUM_STS_8814B BIT(27)
+#define BIT_DDMACH5_DDMA_MODE_8814B BIT(26)
+#define BIT_DDMACH5_RESET_CHKSUM_STS_8814B BIT(25)
+#define BIT_DDMACH5_CHKSUM_CONT_8814B BIT(24)
+
+#define BIT_SHIFT_DDMACH5_DLEN_8814B 0
+#define BIT_MASK_DDMACH5_DLEN_8814B 0x3ffff
+#define BIT_DDMACH5_DLEN_8814B(x)                                              \
+	(((x) & BIT_MASK_DDMACH5_DLEN_8814B) << BIT_SHIFT_DDMACH5_DLEN_8814B)
+#define BITS_DDMACH5_DLEN_8814B                                                \
+	(BIT_MASK_DDMACH5_DLEN_8814B << BIT_SHIFT_DDMACH5_DLEN_8814B)
+#define BIT_CLEAR_DDMACH5_DLEN_8814B(x) ((x) & (~BITS_DDMACH5_DLEN_8814B))
+#define BIT_GET_DDMACH5_DLEN_8814B(x)                                          \
+	(((x) >> BIT_SHIFT_DDMACH5_DLEN_8814B) & BIT_MASK_DDMACH5_DLEN_8814B)
+#define BIT_SET_DDMACH5_DLEN_8814B(x, v)                                       \
+	(BIT_CLEAR_DDMACH5_DLEN_8814B(x) | BIT_DDMACH5_DLEN_8814B(v))
+
+/* 2 REG_DDMA_INT_MSK_8814B */
+#define BIT_DDMACH5_MSK_8814B BIT(5)
+#define BIT_DDMACH4_MSK_8814B BIT(4)
+#define BIT_DDMACH3_MSK_8814B BIT(3)
+#define BIT_DDMACH2_MSK_8814B BIT(2)
+#define BIT_DDMACH1_MSK_8814B BIT(1)
+#define BIT_DDMACH0_MSK_8814B BIT(0)
+
+/* 2 REG_DDMA_CHSTATUS_8814B */
+#define BIT_DDMACH5_BUSY_8814B BIT(5)
+#define BIT_DDMACH4_BUSY_8814B BIT(4)
+#define BIT_DDMACH3_BUSY_8814B BIT(3)
+#define BIT_DDMACH2_BUSY_8814B BIT(2)
+#define BIT_DDMACH1_BUSY_8814B BIT(1)
+#define BIT_DDMACH0_BUSY_8814B BIT(0)
+
+/* 2 REG_DDMA_CHKSUM_8814B */
+
+#define BIT_SHIFT_IDDMA0_CHKSUM_8814B 0
+#define BIT_MASK_IDDMA0_CHKSUM_8814B 0xffff
+#define BIT_IDDMA0_CHKSUM_8814B(x)                                             \
+	(((x) & BIT_MASK_IDDMA0_CHKSUM_8814B) << BIT_SHIFT_IDDMA0_CHKSUM_8814B)
+#define BITS_IDDMA0_CHKSUM_8814B                                               \
+	(BIT_MASK_IDDMA0_CHKSUM_8814B << BIT_SHIFT_IDDMA0_CHKSUM_8814B)
+#define BIT_CLEAR_IDDMA0_CHKSUM_8814B(x) ((x) & (~BITS_IDDMA0_CHKSUM_8814B))
+#define BIT_GET_IDDMA0_CHKSUM_8814B(x)                                         \
+	(((x) >> BIT_SHIFT_IDDMA0_CHKSUM_8814B) & BIT_MASK_IDDMA0_CHKSUM_8814B)
+#define BIT_SET_IDDMA0_CHKSUM_8814B(x, v)                                      \
+	(BIT_CLEAR_IDDMA0_CHKSUM_8814B(x) | BIT_IDDMA0_CHKSUM_8814B(v))
+
+/* 2 REG_DDMA_MONITOR_8814B */
+#define BIT_IDDMA0_PERMU_UNDERFLOW_8814B BIT(14)
+#define BIT_IDDMA0_FIFO_UNDERFLOW_8814B BIT(13)
+#define BIT_IDDMA0_FIFO_OVERFLOW_8814B BIT(12)
+#define BIT_CH5_ERR_8814B BIT(5)
+#define BIT_CH4_ERR_8814B BIT(4)
+#define BIT_CH3_ERR_8814B BIT(3)
+#define BIT_CH2_ERR_8814B BIT(2)
+#define BIT_CH1_ERR_8814B BIT(1)
+#define BIT_CH0_ERR_8814B BIT(0)
+
+/* 2 REG_DMA_RQPN_INFO_0_8814B */
+
+#define BIT_SHIFT_CH0_AVAL_PG_8814B 16
+#define BIT_MASK_CH0_AVAL_PG_8814B 0xfff
+#define BIT_CH0_AVAL_PG_8814B(x)                                               \
+	(((x) & BIT_MASK_CH0_AVAL_PG_8814B) << BIT_SHIFT_CH0_AVAL_PG_8814B)
+#define BITS_CH0_AVAL_PG_8814B                                                 \
+	(BIT_MASK_CH0_AVAL_PG_8814B << BIT_SHIFT_CH0_AVAL_PG_8814B)
+#define BIT_CLEAR_CH0_AVAL_PG_8814B(x) ((x) & (~BITS_CH0_AVAL_PG_8814B))
+#define BIT_GET_CH0_AVAL_PG_8814B(x)                                           \
+	(((x) >> BIT_SHIFT_CH0_AVAL_PG_8814B) & BIT_MASK_CH0_AVAL_PG_8814B)
+#define BIT_SET_CH0_AVAL_PG_8814B(x, v)                                        \
+	(BIT_CLEAR_CH0_AVAL_PG_8814B(x) | BIT_CH0_AVAL_PG_8814B(v))
+
+#define BIT_SHIFT_CH0_RSVD_PG_8814B 0
+#define BIT_MASK_CH0_RSVD_PG_8814B 0xfff
+#define BIT_CH0_RSVD_PG_8814B(x)                                               \
+	(((x) & BIT_MASK_CH0_RSVD_PG_8814B) << BIT_SHIFT_CH0_RSVD_PG_8814B)
+#define BITS_CH0_RSVD_PG_8814B                                                 \
+	(BIT_MASK_CH0_RSVD_PG_8814B << BIT_SHIFT_CH0_RSVD_PG_8814B)
+#define BIT_CLEAR_CH0_RSVD_PG_8814B(x) ((x) & (~BITS_CH0_RSVD_PG_8814B))
+#define BIT_GET_CH0_RSVD_PG_8814B(x)                                           \
+	(((x) >> BIT_SHIFT_CH0_RSVD_PG_8814B) & BIT_MASK_CH0_RSVD_PG_8814B)
+#define BIT_SET_CH0_RSVD_PG_8814B(x, v)                                        \
+	(BIT_CLEAR_CH0_RSVD_PG_8814B(x) | BIT_CH0_RSVD_PG_8814B(v))
+
+/* 2 REG_DMA_RQPN_INFO_1_8814B */
+
+#define BIT_SHIFT_CH1_AVAL_PG_8814B 16
+#define BIT_MASK_CH1_AVAL_PG_8814B 0xfff
+#define BIT_CH1_AVAL_PG_8814B(x)                                               \
+	(((x) & BIT_MASK_CH1_AVAL_PG_8814B) << BIT_SHIFT_CH1_AVAL_PG_8814B)
+#define BITS_CH1_AVAL_PG_8814B                                                 \
+	(BIT_MASK_CH1_AVAL_PG_8814B << BIT_SHIFT_CH1_AVAL_PG_8814B)
+#define BIT_CLEAR_CH1_AVAL_PG_8814B(x) ((x) & (~BITS_CH1_AVAL_PG_8814B))
+#define BIT_GET_CH1_AVAL_PG_8814B(x)                                           \
+	(((x) >> BIT_SHIFT_CH1_AVAL_PG_8814B) & BIT_MASK_CH1_AVAL_PG_8814B)
+#define BIT_SET_CH1_AVAL_PG_8814B(x, v)                                        \
+	(BIT_CLEAR_CH1_AVAL_PG_8814B(x) | BIT_CH1_AVAL_PG_8814B(v))
+
+#define BIT_SHIFT_CH1_RSVD_PG_8814B 0
+#define BIT_MASK_CH1_RSVD_PG_8814B 0xfff
+#define BIT_CH1_RSVD_PG_8814B(x)                                               \
+	(((x) & BIT_MASK_CH1_RSVD_PG_8814B) << BIT_SHIFT_CH1_RSVD_PG_8814B)
+#define BITS_CH1_RSVD_PG_8814B                                                 \
+	(BIT_MASK_CH1_RSVD_PG_8814B << BIT_SHIFT_CH1_RSVD_PG_8814B)
+#define BIT_CLEAR_CH1_RSVD_PG_8814B(x) ((x) & (~BITS_CH1_RSVD_PG_8814B))
+#define BIT_GET_CH1_RSVD_PG_8814B(x)                                           \
+	(((x) >> BIT_SHIFT_CH1_RSVD_PG_8814B) & BIT_MASK_CH1_RSVD_PG_8814B)
+#define BIT_SET_CH1_RSVD_PG_8814B(x, v)                                        \
+	(BIT_CLEAR_CH1_RSVD_PG_8814B(x) | BIT_CH1_RSVD_PG_8814B(v))
+
+/* 2 REG_DMA_RQPN_INFO_2_8814B */
+
+#define BIT_SHIFT_CH2_AVAL_PG_8814B 16
+#define BIT_MASK_CH2_AVAL_PG_8814B 0xfff
+#define BIT_CH2_AVAL_PG_8814B(x)                                               \
+	(((x) & BIT_MASK_CH2_AVAL_PG_8814B) << BIT_SHIFT_CH2_AVAL_PG_8814B)
+#define BITS_CH2_AVAL_PG_8814B                                                 \
+	(BIT_MASK_CH2_AVAL_PG_8814B << BIT_SHIFT_CH2_AVAL_PG_8814B)
+#define BIT_CLEAR_CH2_AVAL_PG_8814B(x) ((x) & (~BITS_CH2_AVAL_PG_8814B))
+#define BIT_GET_CH2_AVAL_PG_8814B(x)                                           \
+	(((x) >> BIT_SHIFT_CH2_AVAL_PG_8814B) & BIT_MASK_CH2_AVAL_PG_8814B)
+#define BIT_SET_CH2_AVAL_PG_8814B(x, v)                                        \
+	(BIT_CLEAR_CH2_AVAL_PG_8814B(x) | BIT_CH2_AVAL_PG_8814B(v))
+
+#define BIT_SHIFT_CH2_RSVD_PG_8814B 0
+#define BIT_MASK_CH2_RSVD_PG_8814B 0xfff
+#define BIT_CH2_RSVD_PG_8814B(x)                                               \
+	(((x) & BIT_MASK_CH2_RSVD_PG_8814B) << BIT_SHIFT_CH2_RSVD_PG_8814B)
+#define BITS_CH2_RSVD_PG_8814B                                                 \
+	(BIT_MASK_CH2_RSVD_PG_8814B << BIT_SHIFT_CH2_RSVD_PG_8814B)
+#define BIT_CLEAR_CH2_RSVD_PG_8814B(x) ((x) & (~BITS_CH2_RSVD_PG_8814B))
+#define BIT_GET_CH2_RSVD_PG_8814B(x)                                           \
+	(((x) >> BIT_SHIFT_CH2_RSVD_PG_8814B) & BIT_MASK_CH2_RSVD_PG_8814B)
+#define BIT_SET_CH2_RSVD_PG_8814B(x, v)                                        \
+	(BIT_CLEAR_CH2_RSVD_PG_8814B(x) | BIT_CH2_RSVD_PG_8814B(v))
+
+/* 2 REG_DMA_RQPN_INFO_3_8814B */
+
+#define BIT_SHIFT_CH3_AVAL_PG_8814B 16
+#define BIT_MASK_CH3_AVAL_PG_8814B 0xfff
+#define BIT_CH3_AVAL_PG_8814B(x)                                               \
+	(((x) & BIT_MASK_CH3_AVAL_PG_8814B) << BIT_SHIFT_CH3_AVAL_PG_8814B)
+#define BITS_CH3_AVAL_PG_8814B                                                 \
+	(BIT_MASK_CH3_AVAL_PG_8814B << BIT_SHIFT_CH3_AVAL_PG_8814B)
+#define BIT_CLEAR_CH3_AVAL_PG_8814B(x) ((x) & (~BITS_CH3_AVAL_PG_8814B))
+#define BIT_GET_CH3_AVAL_PG_8814B(x)                                           \
+	(((x) >> BIT_SHIFT_CH3_AVAL_PG_8814B) & BIT_MASK_CH3_AVAL_PG_8814B)
+#define BIT_SET_CH3_AVAL_PG_8814B(x, v)                                        \
+	(BIT_CLEAR_CH3_AVAL_PG_8814B(x) | BIT_CH3_AVAL_PG_8814B(v))
+
+#define BIT_SHIFT_CH3_RSVD_PG_8814B 0
+#define BIT_MASK_CH3_RSVD_PG_8814B 0xfff
+#define BIT_CH3_RSVD_PG_8814B(x)                                               \
+	(((x) & BIT_MASK_CH3_RSVD_PG_8814B) << BIT_SHIFT_CH3_RSVD_PG_8814B)
+#define BITS_CH3_RSVD_PG_8814B                                                 \
+	(BIT_MASK_CH3_RSVD_PG_8814B << BIT_SHIFT_CH3_RSVD_PG_8814B)
+#define BIT_CLEAR_CH3_RSVD_PG_8814B(x) ((x) & (~BITS_CH3_RSVD_PG_8814B))
+#define BIT_GET_CH3_RSVD_PG_8814B(x)                                           \
+	(((x) >> BIT_SHIFT_CH3_RSVD_PG_8814B) & BIT_MASK_CH3_RSVD_PG_8814B)
+#define BIT_SET_CH3_RSVD_PG_8814B(x, v)                                        \
+	(BIT_CLEAR_CH3_RSVD_PG_8814B(x) | BIT_CH3_RSVD_PG_8814B(v))
+
+/* 2 REG_DMA_RQPN_INFO_4_8814B */
+
+#define BIT_SHIFT_CH4_AVAL_PG_8814B 16
+#define BIT_MASK_CH4_AVAL_PG_8814B 0xfff
+#define BIT_CH4_AVAL_PG_8814B(x)                                               \
+	(((x) & BIT_MASK_CH4_AVAL_PG_8814B) << BIT_SHIFT_CH4_AVAL_PG_8814B)
+#define BITS_CH4_AVAL_PG_8814B                                                 \
+	(BIT_MASK_CH4_AVAL_PG_8814B << BIT_SHIFT_CH4_AVAL_PG_8814B)
+#define BIT_CLEAR_CH4_AVAL_PG_8814B(x) ((x) & (~BITS_CH4_AVAL_PG_8814B))
+#define BIT_GET_CH4_AVAL_PG_8814B(x)                                           \
+	(((x) >> BIT_SHIFT_CH4_AVAL_PG_8814B) & BIT_MASK_CH4_AVAL_PG_8814B)
+#define BIT_SET_CH4_AVAL_PG_8814B(x, v)                                        \
+	(BIT_CLEAR_CH4_AVAL_PG_8814B(x) | BIT_CH4_AVAL_PG_8814B(v))
+
+#define BIT_SHIFT_CH4_RSVD_PG_8814B 0
+#define BIT_MASK_CH4_RSVD_PG_8814B 0xfff
+#define BIT_CH4_RSVD_PG_8814B(x)                                               \
+	(((x) & BIT_MASK_CH4_RSVD_PG_8814B) << BIT_SHIFT_CH4_RSVD_PG_8814B)
+#define BITS_CH4_RSVD_PG_8814B                                                 \
+	(BIT_MASK_CH4_RSVD_PG_8814B << BIT_SHIFT_CH4_RSVD_PG_8814B)
+#define BIT_CLEAR_CH4_RSVD_PG_8814B(x) ((x) & (~BITS_CH4_RSVD_PG_8814B))
+#define BIT_GET_CH4_RSVD_PG_8814B(x)                                           \
+	(((x) >> BIT_SHIFT_CH4_RSVD_PG_8814B) & BIT_MASK_CH4_RSVD_PG_8814B)
+#define BIT_SET_CH4_RSVD_PG_8814B(x, v)                                        \
+	(BIT_CLEAR_CH4_RSVD_PG_8814B(x) | BIT_CH4_RSVD_PG_8814B(v))
+
+/* 2 REG_DMA_RQPN_INFO_5_8814B */
+
+#define BIT_SHIFT_CH5_AVAL_PG_8814B 16
+#define BIT_MASK_CH5_AVAL_PG_8814B 0xfff
+#define BIT_CH5_AVAL_PG_8814B(x)                                               \
+	(((x) & BIT_MASK_CH5_AVAL_PG_8814B) << BIT_SHIFT_CH5_AVAL_PG_8814B)
+#define BITS_CH5_AVAL_PG_8814B                                                 \
+	(BIT_MASK_CH5_AVAL_PG_8814B << BIT_SHIFT_CH5_AVAL_PG_8814B)
+#define BIT_CLEAR_CH5_AVAL_PG_8814B(x) ((x) & (~BITS_CH5_AVAL_PG_8814B))
+#define BIT_GET_CH5_AVAL_PG_8814B(x)                                           \
+	(((x) >> BIT_SHIFT_CH5_AVAL_PG_8814B) & BIT_MASK_CH5_AVAL_PG_8814B)
+#define BIT_SET_CH5_AVAL_PG_8814B(x, v)                                        \
+	(BIT_CLEAR_CH5_AVAL_PG_8814B(x) | BIT_CH5_AVAL_PG_8814B(v))
+
+#define BIT_SHIFT_CH5_RSVD_PG_8814B 0
+#define BIT_MASK_CH5_RSVD_PG_8814B 0xfff
+#define BIT_CH5_RSVD_PG_8814B(x)                                               \
+	(((x) & BIT_MASK_CH5_RSVD_PG_8814B) << BIT_SHIFT_CH5_RSVD_PG_8814B)
+#define BITS_CH5_RSVD_PG_8814B                                                 \
+	(BIT_MASK_CH5_RSVD_PG_8814B << BIT_SHIFT_CH5_RSVD_PG_8814B)
+#define BIT_CLEAR_CH5_RSVD_PG_8814B(x) ((x) & (~BITS_CH5_RSVD_PG_8814B))
+#define BIT_GET_CH5_RSVD_PG_8814B(x)                                           \
+	(((x) >> BIT_SHIFT_CH5_RSVD_PG_8814B) & BIT_MASK_CH5_RSVD_PG_8814B)
+#define BIT_SET_CH5_RSVD_PG_8814B(x, v)                                        \
+	(BIT_CLEAR_CH5_RSVD_PG_8814B(x) | BIT_CH5_RSVD_PG_8814B(v))
+
+/* 2 REG_DMA_RQPN_INFO_6_8814B */
+
+#define BIT_SHIFT_CH6_AVAL_PG_8814B 16
+#define BIT_MASK_CH6_AVAL_PG_8814B 0xfff
+#define BIT_CH6_AVAL_PG_8814B(x)                                               \
+	(((x) & BIT_MASK_CH6_AVAL_PG_8814B) << BIT_SHIFT_CH6_AVAL_PG_8814B)
+#define BITS_CH6_AVAL_PG_8814B                                                 \
+	(BIT_MASK_CH6_AVAL_PG_8814B << BIT_SHIFT_CH6_AVAL_PG_8814B)
+#define BIT_CLEAR_CH6_AVAL_PG_8814B(x) ((x) & (~BITS_CH6_AVAL_PG_8814B))
+#define BIT_GET_CH6_AVAL_PG_8814B(x)                                           \
+	(((x) >> BIT_SHIFT_CH6_AVAL_PG_8814B) & BIT_MASK_CH6_AVAL_PG_8814B)
+#define BIT_SET_CH6_AVAL_PG_8814B(x, v)                                        \
+	(BIT_CLEAR_CH6_AVAL_PG_8814B(x) | BIT_CH6_AVAL_PG_8814B(v))
+
+#define BIT_SHIFT_CH6_RSVD_PG_8814B 0
+#define BIT_MASK_CH6_RSVD_PG_8814B 0xfff
+#define BIT_CH6_RSVD_PG_8814B(x)                                               \
+	(((x) & BIT_MASK_CH6_RSVD_PG_8814B) << BIT_SHIFT_CH6_RSVD_PG_8814B)
+#define BITS_CH6_RSVD_PG_8814B                                                 \
+	(BIT_MASK_CH6_RSVD_PG_8814B << BIT_SHIFT_CH6_RSVD_PG_8814B)
+#define BIT_CLEAR_CH6_RSVD_PG_8814B(x) ((x) & (~BITS_CH6_RSVD_PG_8814B))
+#define BIT_GET_CH6_RSVD_PG_8814B(x)                                           \
+	(((x) >> BIT_SHIFT_CH6_RSVD_PG_8814B) & BIT_MASK_CH6_RSVD_PG_8814B)
+#define BIT_SET_CH6_RSVD_PG_8814B(x, v)                                        \
+	(BIT_CLEAR_CH6_RSVD_PG_8814B(x) | BIT_CH6_RSVD_PG_8814B(v))
+
+/* 2 REG_DMA_RQPN_INFO_7_8814B */
+
+#define BIT_SHIFT_CH7_AVAL_PG_8814B 16
+#define BIT_MASK_CH7_AVAL_PG_8814B 0xfff
+#define BIT_CH7_AVAL_PG_8814B(x)                                               \
+	(((x) & BIT_MASK_CH7_AVAL_PG_8814B) << BIT_SHIFT_CH7_AVAL_PG_8814B)
+#define BITS_CH7_AVAL_PG_8814B                                                 \
+	(BIT_MASK_CH7_AVAL_PG_8814B << BIT_SHIFT_CH7_AVAL_PG_8814B)
+#define BIT_CLEAR_CH7_AVAL_PG_8814B(x) ((x) & (~BITS_CH7_AVAL_PG_8814B))
+#define BIT_GET_CH7_AVAL_PG_8814B(x)                                           \
+	(((x) >> BIT_SHIFT_CH7_AVAL_PG_8814B) & BIT_MASK_CH7_AVAL_PG_8814B)
+#define BIT_SET_CH7_AVAL_PG_8814B(x, v)                                        \
+	(BIT_CLEAR_CH7_AVAL_PG_8814B(x) | BIT_CH7_AVAL_PG_8814B(v))
+
+#define BIT_SHIFT_CH7_RSVD_PG_8814B 0
+#define BIT_MASK_CH7_RSVD_PG_8814B 0xfff
+#define BIT_CH7_RSVD_PG_8814B(x)                                               \
+	(((x) & BIT_MASK_CH7_RSVD_PG_8814B) << BIT_SHIFT_CH7_RSVD_PG_8814B)
+#define BITS_CH7_RSVD_PG_8814B                                                 \
+	(BIT_MASK_CH7_RSVD_PG_8814B << BIT_SHIFT_CH7_RSVD_PG_8814B)
+#define BIT_CLEAR_CH7_RSVD_PG_8814B(x) ((x) & (~BITS_CH7_RSVD_PG_8814B))
+#define BIT_GET_CH7_RSVD_PG_8814B(x)                                           \
+	(((x) >> BIT_SHIFT_CH7_RSVD_PG_8814B) & BIT_MASK_CH7_RSVD_PG_8814B)
+#define BIT_SET_CH7_RSVD_PG_8814B(x, v)                                        \
+	(BIT_CLEAR_CH7_RSVD_PG_8814B(x) | BIT_CH7_RSVD_PG_8814B(v))
+
+/* 2 REG_DMA_RQPN_INFO_8_8814B */
+
+#define BIT_SHIFT_CH8_AVAL_PG_8814B 16
+#define BIT_MASK_CH8_AVAL_PG_8814B 0xfff
+#define BIT_CH8_AVAL_PG_8814B(x)                                               \
+	(((x) & BIT_MASK_CH8_AVAL_PG_8814B) << BIT_SHIFT_CH8_AVAL_PG_8814B)
+#define BITS_CH8_AVAL_PG_8814B                                                 \
+	(BIT_MASK_CH8_AVAL_PG_8814B << BIT_SHIFT_CH8_AVAL_PG_8814B)
+#define BIT_CLEAR_CH8_AVAL_PG_8814B(x) ((x) & (~BITS_CH8_AVAL_PG_8814B))
+#define BIT_GET_CH8_AVAL_PG_8814B(x)                                           \
+	(((x) >> BIT_SHIFT_CH8_AVAL_PG_8814B) & BIT_MASK_CH8_AVAL_PG_8814B)
+#define BIT_SET_CH8_AVAL_PG_8814B(x, v)                                        \
+	(BIT_CLEAR_CH8_AVAL_PG_8814B(x) | BIT_CH8_AVAL_PG_8814B(v))
+
+#define BIT_SHIFT_CH8_RSVD_PG_8814B 0
+#define BIT_MASK_CH8_RSVD_PG_8814B 0xfff
+#define BIT_CH8_RSVD_PG_8814B(x)                                               \
+	(((x) & BIT_MASK_CH8_RSVD_PG_8814B) << BIT_SHIFT_CH8_RSVD_PG_8814B)
+#define BITS_CH8_RSVD_PG_8814B                                                 \
+	(BIT_MASK_CH8_RSVD_PG_8814B << BIT_SHIFT_CH8_RSVD_PG_8814B)
+#define BIT_CLEAR_CH8_RSVD_PG_8814B(x) ((x) & (~BITS_CH8_RSVD_PG_8814B))
+#define BIT_GET_CH8_RSVD_PG_8814B(x)                                           \
+	(((x) >> BIT_SHIFT_CH8_RSVD_PG_8814B) & BIT_MASK_CH8_RSVD_PG_8814B)
+#define BIT_SET_CH8_RSVD_PG_8814B(x, v)                                        \
+	(BIT_CLEAR_CH8_RSVD_PG_8814B(x) | BIT_CH8_RSVD_PG_8814B(v))
+
+/* 2 REG_DMA_RQPN_INFO_9_8814B */
+
+#define BIT_SHIFT_CH9_AVAL_PG_8814B 16
+#define BIT_MASK_CH9_AVAL_PG_8814B 0xfff
+#define BIT_CH9_AVAL_PG_8814B(x)                                               \
+	(((x) & BIT_MASK_CH9_AVAL_PG_8814B) << BIT_SHIFT_CH9_AVAL_PG_8814B)
+#define BITS_CH9_AVAL_PG_8814B                                                 \
+	(BIT_MASK_CH9_AVAL_PG_8814B << BIT_SHIFT_CH9_AVAL_PG_8814B)
+#define BIT_CLEAR_CH9_AVAL_PG_8814B(x) ((x) & (~BITS_CH9_AVAL_PG_8814B))
+#define BIT_GET_CH9_AVAL_PG_8814B(x)                                           \
+	(((x) >> BIT_SHIFT_CH9_AVAL_PG_8814B) & BIT_MASK_CH9_AVAL_PG_8814B)
+#define BIT_SET_CH9_AVAL_PG_8814B(x, v)                                        \
+	(BIT_CLEAR_CH9_AVAL_PG_8814B(x) | BIT_CH9_AVAL_PG_8814B(v))
+
+#define BIT_SHIFT_CH9_RSVD_PG_8814B 0
+#define BIT_MASK_CH9_RSVD_PG_8814B 0xfff
+#define BIT_CH9_RSVD_PG_8814B(x)                                               \
+	(((x) & BIT_MASK_CH9_RSVD_PG_8814B) << BIT_SHIFT_CH9_RSVD_PG_8814B)
+#define BITS_CH9_RSVD_PG_8814B                                                 \
+	(BIT_MASK_CH9_RSVD_PG_8814B << BIT_SHIFT_CH9_RSVD_PG_8814B)
+#define BIT_CLEAR_CH9_RSVD_PG_8814B(x) ((x) & (~BITS_CH9_RSVD_PG_8814B))
+#define BIT_GET_CH9_RSVD_PG_8814B(x)                                           \
+	(((x) >> BIT_SHIFT_CH9_RSVD_PG_8814B) & BIT_MASK_CH9_RSVD_PG_8814B)
+#define BIT_SET_CH9_RSVD_PG_8814B(x, v)                                        \
+	(BIT_CLEAR_CH9_RSVD_PG_8814B(x) | BIT_CH9_RSVD_PG_8814B(v))
+
+/* 2 REG_DMA_RQPN_INFO_10_8814B */
+
+#define BIT_SHIFT_CH10_AVAL_PG_8814B 16
+#define BIT_MASK_CH10_AVAL_PG_8814B 0xfff
+#define BIT_CH10_AVAL_PG_8814B(x)                                              \
+	(((x) & BIT_MASK_CH10_AVAL_PG_8814B) << BIT_SHIFT_CH10_AVAL_PG_8814B)
+#define BITS_CH10_AVAL_PG_8814B                                                \
+	(BIT_MASK_CH10_AVAL_PG_8814B << BIT_SHIFT_CH10_AVAL_PG_8814B)
+#define BIT_CLEAR_CH10_AVAL_PG_8814B(x) ((x) & (~BITS_CH10_AVAL_PG_8814B))
+#define BIT_GET_CH10_AVAL_PG_8814B(x)                                          \
+	(((x) >> BIT_SHIFT_CH10_AVAL_PG_8814B) & BIT_MASK_CH10_AVAL_PG_8814B)
+#define BIT_SET_CH10_AVAL_PG_8814B(x, v)                                       \
+	(BIT_CLEAR_CH10_AVAL_PG_8814B(x) | BIT_CH10_AVAL_PG_8814B(v))
+
+#define BIT_SHIFT_CH10_RSVD_PG_8814B 0
+#define BIT_MASK_CH10_RSVD_PG_8814B 0xfff
+#define BIT_CH10_RSVD_PG_8814B(x)                                              \
+	(((x) & BIT_MASK_CH10_RSVD_PG_8814B) << BIT_SHIFT_CH10_RSVD_PG_8814B)
+#define BITS_CH10_RSVD_PG_8814B                                                \
+	(BIT_MASK_CH10_RSVD_PG_8814B << BIT_SHIFT_CH10_RSVD_PG_8814B)
+#define BIT_CLEAR_CH10_RSVD_PG_8814B(x) ((x) & (~BITS_CH10_RSVD_PG_8814B))
+#define BIT_GET_CH10_RSVD_PG_8814B(x)                                          \
+	(((x) >> BIT_SHIFT_CH10_RSVD_PG_8814B) & BIT_MASK_CH10_RSVD_PG_8814B)
+#define BIT_SET_CH10_RSVD_PG_8814B(x, v)                                       \
+	(BIT_CLEAR_CH10_RSVD_PG_8814B(x) | BIT_CH10_RSVD_PG_8814B(v))
+
+/* 2 REG_DMA_RQPN_INFO_11_8814B */
+
+#define BIT_SHIFT_CH11_AVAL_PG_8814B 16
+#define BIT_MASK_CH11_AVAL_PG_8814B 0xfff
+#define BIT_CH11_AVAL_PG_8814B(x)                                              \
+	(((x) & BIT_MASK_CH11_AVAL_PG_8814B) << BIT_SHIFT_CH11_AVAL_PG_8814B)
+#define BITS_CH11_AVAL_PG_8814B                                                \
+	(BIT_MASK_CH11_AVAL_PG_8814B << BIT_SHIFT_CH11_AVAL_PG_8814B)
+#define BIT_CLEAR_CH11_AVAL_PG_8814B(x) ((x) & (~BITS_CH11_AVAL_PG_8814B))
+#define BIT_GET_CH11_AVAL_PG_8814B(x)                                          \
+	(((x) >> BIT_SHIFT_CH11_AVAL_PG_8814B) & BIT_MASK_CH11_AVAL_PG_8814B)
+#define BIT_SET_CH11_AVAL_PG_8814B(x, v)                                       \
+	(BIT_CLEAR_CH11_AVAL_PG_8814B(x) | BIT_CH11_AVAL_PG_8814B(v))
+
+#define BIT_SHIFT_CH11_RSVD_PG_8814B 0
+#define BIT_MASK_CH11_RSVD_PG_8814B 0xfff
+#define BIT_CH11_RSVD_PG_8814B(x)                                              \
+	(((x) & BIT_MASK_CH11_RSVD_PG_8814B) << BIT_SHIFT_CH11_RSVD_PG_8814B)
+#define BITS_CH11_RSVD_PG_8814B                                                \
+	(BIT_MASK_CH11_RSVD_PG_8814B << BIT_SHIFT_CH11_RSVD_PG_8814B)
+#define BIT_CLEAR_CH11_RSVD_PG_8814B(x) ((x) & (~BITS_CH11_RSVD_PG_8814B))
+#define BIT_GET_CH11_RSVD_PG_8814B(x)                                          \
+	(((x) >> BIT_SHIFT_CH11_RSVD_PG_8814B) & BIT_MASK_CH11_RSVD_PG_8814B)
+#define BIT_SET_CH11_RSVD_PG_8814B(x, v)                                       \
+	(BIT_CLEAR_CH11_RSVD_PG_8814B(x) | BIT_CH11_RSVD_PG_8814B(v))
+
+/* 2 REG_DMA_RQPN_INFO_12_8814B */
+
+#define BIT_SHIFT_CH12_AVAL_PG_8814B 16
+#define BIT_MASK_CH12_AVAL_PG_8814B 0xfff
+#define BIT_CH12_AVAL_PG_8814B(x)                                              \
+	(((x) & BIT_MASK_CH12_AVAL_PG_8814B) << BIT_SHIFT_CH12_AVAL_PG_8814B)
+#define BITS_CH12_AVAL_PG_8814B                                                \
+	(BIT_MASK_CH12_AVAL_PG_8814B << BIT_SHIFT_CH12_AVAL_PG_8814B)
+#define BIT_CLEAR_CH12_AVAL_PG_8814B(x) ((x) & (~BITS_CH12_AVAL_PG_8814B))
+#define BIT_GET_CH12_AVAL_PG_8814B(x)                                          \
+	(((x) >> BIT_SHIFT_CH12_AVAL_PG_8814B) & BIT_MASK_CH12_AVAL_PG_8814B)
+#define BIT_SET_CH12_AVAL_PG_8814B(x, v)                                       \
+	(BIT_CLEAR_CH12_AVAL_PG_8814B(x) | BIT_CH12_AVAL_PG_8814B(v))
+
+#define BIT_SHIFT_CH12_RSVD_PG_8814B 0
+#define BIT_MASK_CH12_RSVD_PG_8814B 0xfff
+#define BIT_CH12_RSVD_PG_8814B(x)                                              \
+	(((x) & BIT_MASK_CH12_RSVD_PG_8814B) << BIT_SHIFT_CH12_RSVD_PG_8814B)
+#define BITS_CH12_RSVD_PG_8814B                                                \
+	(BIT_MASK_CH12_RSVD_PG_8814B << BIT_SHIFT_CH12_RSVD_PG_8814B)
+#define BIT_CLEAR_CH12_RSVD_PG_8814B(x) ((x) & (~BITS_CH12_RSVD_PG_8814B))
+#define BIT_GET_CH12_RSVD_PG_8814B(x)                                          \
+	(((x) >> BIT_SHIFT_CH12_RSVD_PG_8814B) & BIT_MASK_CH12_RSVD_PG_8814B)
+#define BIT_SET_CH12_RSVD_PG_8814B(x, v)                                       \
+	(BIT_CLEAR_CH12_RSVD_PG_8814B(x) | BIT_CH12_RSVD_PG_8814B(v))
+
+/* 2 REG_DMA_RQPN_INFO_13_8814B */
+
+#define BIT_SHIFT_CH13_AVAL_PG_8814B 16
+#define BIT_MASK_CH13_AVAL_PG_8814B 0xfff
+#define BIT_CH13_AVAL_PG_8814B(x)                                              \
+	(((x) & BIT_MASK_CH13_AVAL_PG_8814B) << BIT_SHIFT_CH13_AVAL_PG_8814B)
+#define BITS_CH13_AVAL_PG_8814B                                                \
+	(BIT_MASK_CH13_AVAL_PG_8814B << BIT_SHIFT_CH13_AVAL_PG_8814B)
+#define BIT_CLEAR_CH13_AVAL_PG_8814B(x) ((x) & (~BITS_CH13_AVAL_PG_8814B))
+#define BIT_GET_CH13_AVAL_PG_8814B(x)                                          \
+	(((x) >> BIT_SHIFT_CH13_AVAL_PG_8814B) & BIT_MASK_CH13_AVAL_PG_8814B)
+#define BIT_SET_CH13_AVAL_PG_8814B(x, v)                                       \
+	(BIT_CLEAR_CH13_AVAL_PG_8814B(x) | BIT_CH13_AVAL_PG_8814B(v))
+
+#define BIT_SHIFT_CH13_RSVD_PG_8814B 0
+#define BIT_MASK_CH13_RSVD_PG_8814B 0xfff
+#define BIT_CH13_RSVD_PG_8814B(x)                                              \
+	(((x) & BIT_MASK_CH13_RSVD_PG_8814B) << BIT_SHIFT_CH13_RSVD_PG_8814B)
+#define BITS_CH13_RSVD_PG_8814B                                                \
+	(BIT_MASK_CH13_RSVD_PG_8814B << BIT_SHIFT_CH13_RSVD_PG_8814B)
+#define BIT_CLEAR_CH13_RSVD_PG_8814B(x) ((x) & (~BITS_CH13_RSVD_PG_8814B))
+#define BIT_GET_CH13_RSVD_PG_8814B(x)                                          \
+	(((x) >> BIT_SHIFT_CH13_RSVD_PG_8814B) & BIT_MASK_CH13_RSVD_PG_8814B)
+#define BIT_SET_CH13_RSVD_PG_8814B(x, v)                                       \
+	(BIT_CLEAR_CH13_RSVD_PG_8814B(x) | BIT_CH13_RSVD_PG_8814B(v))
+
+/* 2 REG_DMA_RQPN_INFO_14_8814B */
+
+#define BIT_SHIFT_CH14_AVAL_PG_8814B 16
+#define BIT_MASK_CH14_AVAL_PG_8814B 0xfff
+#define BIT_CH14_AVAL_PG_8814B(x)                                              \
+	(((x) & BIT_MASK_CH14_AVAL_PG_8814B) << BIT_SHIFT_CH14_AVAL_PG_8814B)
+#define BITS_CH14_AVAL_PG_8814B                                                \
+	(BIT_MASK_CH14_AVAL_PG_8814B << BIT_SHIFT_CH14_AVAL_PG_8814B)
+#define BIT_CLEAR_CH14_AVAL_PG_8814B(x) ((x) & (~BITS_CH14_AVAL_PG_8814B))
+#define BIT_GET_CH14_AVAL_PG_8814B(x)                                          \
+	(((x) >> BIT_SHIFT_CH14_AVAL_PG_8814B) & BIT_MASK_CH14_AVAL_PG_8814B)
+#define BIT_SET_CH14_AVAL_PG_8814B(x, v)                                       \
+	(BIT_CLEAR_CH14_AVAL_PG_8814B(x) | BIT_CH14_AVAL_PG_8814B(v))
+
+#define BIT_SHIFT_CH14_RSVD_PG_8814B 0
+#define BIT_MASK_CH14_RSVD_PG_8814B 0xfff
+#define BIT_CH14_RSVD_PG_8814B(x)                                              \
+	(((x) & BIT_MASK_CH14_RSVD_PG_8814B) << BIT_SHIFT_CH14_RSVD_PG_8814B)
+#define BITS_CH14_RSVD_PG_8814B                                                \
+	(BIT_MASK_CH14_RSVD_PG_8814B << BIT_SHIFT_CH14_RSVD_PG_8814B)
+#define BIT_CLEAR_CH14_RSVD_PG_8814B(x) ((x) & (~BITS_CH14_RSVD_PG_8814B))
+#define BIT_GET_CH14_RSVD_PG_8814B(x)                                          \
+	(((x) >> BIT_SHIFT_CH14_RSVD_PG_8814B) & BIT_MASK_CH14_RSVD_PG_8814B)
+#define BIT_SET_CH14_RSVD_PG_8814B(x, v)                                       \
+	(BIT_CLEAR_CH14_RSVD_PG_8814B(x) | BIT_CH14_RSVD_PG_8814B(v))
+
+/* 2 REG_DMA_RQPN_INFO_15_8814B */
+
+#define BIT_SHIFT_CH15_AVAL_PG_8814B 16
+#define BIT_MASK_CH15_AVAL_PG_8814B 0xfff
+#define BIT_CH15_AVAL_PG_8814B(x)                                              \
+	(((x) & BIT_MASK_CH15_AVAL_PG_8814B) << BIT_SHIFT_CH15_AVAL_PG_8814B)
+#define BITS_CH15_AVAL_PG_8814B                                                \
+	(BIT_MASK_CH15_AVAL_PG_8814B << BIT_SHIFT_CH15_AVAL_PG_8814B)
+#define BIT_CLEAR_CH15_AVAL_PG_8814B(x) ((x) & (~BITS_CH15_AVAL_PG_8814B))
+#define BIT_GET_CH15_AVAL_PG_8814B(x)                                          \
+	(((x) >> BIT_SHIFT_CH15_AVAL_PG_8814B) & BIT_MASK_CH15_AVAL_PG_8814B)
+#define BIT_SET_CH15_AVAL_PG_8814B(x, v)                                       \
+	(BIT_CLEAR_CH15_AVAL_PG_8814B(x) | BIT_CH15_AVAL_PG_8814B(v))
+
+#define BIT_SHIFT_CH15_RSVD_PG_8814B 0
+#define BIT_MASK_CH15_RSVD_PG_8814B 0xfff
+#define BIT_CH15_RSVD_PG_8814B(x)                                              \
+	(((x) & BIT_MASK_CH15_RSVD_PG_8814B) << BIT_SHIFT_CH15_RSVD_PG_8814B)
+#define BITS_CH15_RSVD_PG_8814B                                                \
+	(BIT_MASK_CH15_RSVD_PG_8814B << BIT_SHIFT_CH15_RSVD_PG_8814B)
+#define BIT_CLEAR_CH15_RSVD_PG_8814B(x) ((x) & (~BITS_CH15_RSVD_PG_8814B))
+#define BIT_GET_CH15_RSVD_PG_8814B(x)                                          \
+	(((x) >> BIT_SHIFT_CH15_RSVD_PG_8814B) & BIT_MASK_CH15_RSVD_PG_8814B)
+#define BIT_SET_CH15_RSVD_PG_8814B(x, v)                                       \
+	(BIT_CLEAR_CH15_RSVD_PG_8814B(x) | BIT_CH15_RSVD_PG_8814B(v))
+
+/* 2 REG_DMA_RQPN_INFO_16_8814B */
+
+#define BIT_SHIFT_CH16_AVAL_PG_8814B 16
+#define BIT_MASK_CH16_AVAL_PG_8814B 0xfff
+#define BIT_CH16_AVAL_PG_8814B(x)                                              \
+	(((x) & BIT_MASK_CH16_AVAL_PG_8814B) << BIT_SHIFT_CH16_AVAL_PG_8814B)
+#define BITS_CH16_AVAL_PG_8814B                                                \
+	(BIT_MASK_CH16_AVAL_PG_8814B << BIT_SHIFT_CH16_AVAL_PG_8814B)
+#define BIT_CLEAR_CH16_AVAL_PG_8814B(x) ((x) & (~BITS_CH16_AVAL_PG_8814B))
+#define BIT_GET_CH16_AVAL_PG_8814B(x)                                          \
+	(((x) >> BIT_SHIFT_CH16_AVAL_PG_8814B) & BIT_MASK_CH16_AVAL_PG_8814B)
+#define BIT_SET_CH16_AVAL_PG_8814B(x, v)                                       \
+	(BIT_CLEAR_CH16_AVAL_PG_8814B(x) | BIT_CH16_AVAL_PG_8814B(v))
+
+#define BIT_SHIFT_CH16_RSVD_PG_8814B 0
+#define BIT_MASK_CH16_RSVD_PG_8814B 0xfff
+#define BIT_CH16_RSVD_PG_8814B(x)                                              \
+	(((x) & BIT_MASK_CH16_RSVD_PG_8814B) << BIT_SHIFT_CH16_RSVD_PG_8814B)
+#define BITS_CH16_RSVD_PG_8814B                                                \
+	(BIT_MASK_CH16_RSVD_PG_8814B << BIT_SHIFT_CH16_RSVD_PG_8814B)
+#define BIT_CLEAR_CH16_RSVD_PG_8814B(x) ((x) & (~BITS_CH16_RSVD_PG_8814B))
+#define BIT_GET_CH16_RSVD_PG_8814B(x)                                          \
+	(((x) >> BIT_SHIFT_CH16_RSVD_PG_8814B) & BIT_MASK_CH16_RSVD_PG_8814B)
+#define BIT_SET_CH16_RSVD_PG_8814B(x, v)                                       \
+	(BIT_CLEAR_CH16_RSVD_PG_8814B(x) | BIT_CH16_RSVD_PG_8814B(v))
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_HWAMSDU_CTL1_8814B */
+
+#define BIT_SHIFT_HWAMSDU_PKTNUM_8814B 8
+#define BIT_MASK_HWAMSDU_PKTNUM_8814B 0x3f
+#define BIT_HWAMSDU_PKTNUM_8814B(x)                                            \
+	(((x) & BIT_MASK_HWAMSDU_PKTNUM_8814B)                                 \
+	 << BIT_SHIFT_HWAMSDU_PKTNUM_8814B)
+#define BITS_HWAMSDU_PKTNUM_8814B                                              \
+	(BIT_MASK_HWAMSDU_PKTNUM_8814B << BIT_SHIFT_HWAMSDU_PKTNUM_8814B)
+#define BIT_CLEAR_HWAMSDU_PKTNUM_8814B(x) ((x) & (~BITS_HWAMSDU_PKTNUM_8814B))
+#define BIT_GET_HWAMSDU_PKTNUM_8814B(x)                                        \
+	(((x) >> BIT_SHIFT_HWAMSDU_PKTNUM_8814B) &                             \
+	 BIT_MASK_HWAMSDU_PKTNUM_8814B)
+#define BIT_SET_HWAMSDU_PKTNUM_8814B(x, v)                                     \
+	(BIT_CLEAR_HWAMSDU_PKTNUM_8814B(x) | BIT_HWAMSDU_PKTNUM_8814B(v))
+
+#define BIT_HWAMSDU_BUSY_8814B BIT(7)
+#define BIT_SINGLE_AMSDU_8814B BIT(2)
+#define BIT_HWAMSDU_PADDING_MODE_8814B BIT(1)
+#define BIT_HWAMSDU_EN_8814B BIT(0)
+
+/* 2 REG_HWAMSDU_CTL2_8814B */
+
+#define BIT_SHIFT_HWAMSDU_AMSDU_TIMEOUT_8814B 16
+#define BIT_MASK_HWAMSDU_AMSDU_TIMEOUT_8814B 0xffff
+#define BIT_HWAMSDU_AMSDU_TIMEOUT_8814B(x)                                     \
+	(((x) & BIT_MASK_HWAMSDU_AMSDU_TIMEOUT_8814B)                          \
+	 << BIT_SHIFT_HWAMSDU_AMSDU_TIMEOUT_8814B)
+#define BITS_HWAMSDU_AMSDU_TIMEOUT_8814B                                       \
+	(BIT_MASK_HWAMSDU_AMSDU_TIMEOUT_8814B                                  \
+	 << BIT_SHIFT_HWAMSDU_AMSDU_TIMEOUT_8814B)
+#define BIT_CLEAR_HWAMSDU_AMSDU_TIMEOUT_8814B(x)                               \
+	((x) & (~BITS_HWAMSDU_AMSDU_TIMEOUT_8814B))
+#define BIT_GET_HWAMSDU_AMSDU_TIMEOUT_8814B(x)                                 \
+	(((x) >> BIT_SHIFT_HWAMSDU_AMSDU_TIMEOUT_8814B) &                      \
+	 BIT_MASK_HWAMSDU_AMSDU_TIMEOUT_8814B)
+#define BIT_SET_HWAMSDU_AMSDU_TIMEOUT_8814B(x, v)                              \
+	(BIT_CLEAR_HWAMSDU_AMSDU_TIMEOUT_8814B(x) |                            \
+	 BIT_HWAMSDU_AMSDU_TIMEOUT_8814B(v))
+
+#define BIT_SHIFT_HWAMSDU_MSDU_TIMEOUT_8814B 0
+#define BIT_MASK_HWAMSDU_MSDU_TIMEOUT_8814B 0xffff
+#define BIT_HWAMSDU_MSDU_TIMEOUT_8814B(x)                                      \
+	(((x) & BIT_MASK_HWAMSDU_MSDU_TIMEOUT_8814B)                           \
+	 << BIT_SHIFT_HWAMSDU_MSDU_TIMEOUT_8814B)
+#define BITS_HWAMSDU_MSDU_TIMEOUT_8814B                                        \
+	(BIT_MASK_HWAMSDU_MSDU_TIMEOUT_8814B                                   \
+	 << BIT_SHIFT_HWAMSDU_MSDU_TIMEOUT_8814B)
+#define BIT_CLEAR_HWAMSDU_MSDU_TIMEOUT_8814B(x)                                \
+	((x) & (~BITS_HWAMSDU_MSDU_TIMEOUT_8814B))
+#define BIT_GET_HWAMSDU_MSDU_TIMEOUT_8814B(x)                                  \
+	(((x) >> BIT_SHIFT_HWAMSDU_MSDU_TIMEOUT_8814B) &                       \
+	 BIT_MASK_HWAMSDU_MSDU_TIMEOUT_8814B)
+#define BIT_SET_HWAMSDU_MSDU_TIMEOUT_8814B(x, v)                               \
+	(BIT_CLEAR_HWAMSDU_MSDU_TIMEOUT_8814B(x) |                             \
+	 BIT_HWAMSDU_MSDU_TIMEOUT_8814B(v))
+
+/* 2 REG_TXPAGE_INT_CTRL_0_8814B */
+#define BIT_CH0_INT_EN_8814B BIT(31)
+
+#define BIT_SHIFT_CH0_HIGH_TH_8814B 16
+#define BIT_MASK_CH0_HIGH_TH_8814B 0xfff
+#define BIT_CH0_HIGH_TH_8814B(x)                                               \
+	(((x) & BIT_MASK_CH0_HIGH_TH_8814B) << BIT_SHIFT_CH0_HIGH_TH_8814B)
+#define BITS_CH0_HIGH_TH_8814B                                                 \
+	(BIT_MASK_CH0_HIGH_TH_8814B << BIT_SHIFT_CH0_HIGH_TH_8814B)
+#define BIT_CLEAR_CH0_HIGH_TH_8814B(x) ((x) & (~BITS_CH0_HIGH_TH_8814B))
+#define BIT_GET_CH0_HIGH_TH_8814B(x)                                           \
+	(((x) >> BIT_SHIFT_CH0_HIGH_TH_8814B) & BIT_MASK_CH0_HIGH_TH_8814B)
+#define BIT_SET_CH0_HIGH_TH_8814B(x, v)                                        \
+	(BIT_CLEAR_CH0_HIGH_TH_8814B(x) | BIT_CH0_HIGH_TH_8814B(v))
+
+#define BIT_SHIFT_CH0_LOW_TH_8814B 0
+#define BIT_MASK_CH0_LOW_TH_8814B 0xfff
+#define BIT_CH0_LOW_TH_8814B(x)                                                \
+	(((x) & BIT_MASK_CH0_LOW_TH_8814B) << BIT_SHIFT_CH0_LOW_TH_8814B)
+#define BITS_CH0_LOW_TH_8814B                                                  \
+	(BIT_MASK_CH0_LOW_TH_8814B << BIT_SHIFT_CH0_LOW_TH_8814B)
+#define BIT_CLEAR_CH0_LOW_TH_8814B(x) ((x) & (~BITS_CH0_LOW_TH_8814B))
+#define BIT_GET_CH0_LOW_TH_8814B(x)                                            \
+	(((x) >> BIT_SHIFT_CH0_LOW_TH_8814B) & BIT_MASK_CH0_LOW_TH_8814B)
+#define BIT_SET_CH0_LOW_TH_8814B(x, v)                                         \
+	(BIT_CLEAR_CH0_LOW_TH_8814B(x) | BIT_CH0_LOW_TH_8814B(v))
+
+/* 2 REG_TXPAGE_INT_CTRL_1_8814B */
+#define BIT_CH1_INT_EN_8814B BIT(31)
+
+#define BIT_SHIFT_CH1_HIGH_TH_8814B 16
+#define BIT_MASK_CH1_HIGH_TH_8814B 0xfff
+#define BIT_CH1_HIGH_TH_8814B(x)                                               \
+	(((x) & BIT_MASK_CH1_HIGH_TH_8814B) << BIT_SHIFT_CH1_HIGH_TH_8814B)
+#define BITS_CH1_HIGH_TH_8814B                                                 \
+	(BIT_MASK_CH1_HIGH_TH_8814B << BIT_SHIFT_CH1_HIGH_TH_8814B)
+#define BIT_CLEAR_CH1_HIGH_TH_8814B(x) ((x) & (~BITS_CH1_HIGH_TH_8814B))
+#define BIT_GET_CH1_HIGH_TH_8814B(x)                                           \
+	(((x) >> BIT_SHIFT_CH1_HIGH_TH_8814B) & BIT_MASK_CH1_HIGH_TH_8814B)
+#define BIT_SET_CH1_HIGH_TH_8814B(x, v)                                        \
+	(BIT_CLEAR_CH1_HIGH_TH_8814B(x) | BIT_CH1_HIGH_TH_8814B(v))
+
+#define BIT_SHIFT_CH1_LOW_TH_8814B 0
+#define BIT_MASK_CH1_LOW_TH_8814B 0xfff
+#define BIT_CH1_LOW_TH_8814B(x)                                                \
+	(((x) & BIT_MASK_CH1_LOW_TH_8814B) << BIT_SHIFT_CH1_LOW_TH_8814B)
+#define BITS_CH1_LOW_TH_8814B                                                  \
+	(BIT_MASK_CH1_LOW_TH_8814B << BIT_SHIFT_CH1_LOW_TH_8814B)
+#define BIT_CLEAR_CH1_LOW_TH_8814B(x) ((x) & (~BITS_CH1_LOW_TH_8814B))
+#define BIT_GET_CH1_LOW_TH_8814B(x)                                            \
+	(((x) >> BIT_SHIFT_CH1_LOW_TH_8814B) & BIT_MASK_CH1_LOW_TH_8814B)
+#define BIT_SET_CH1_LOW_TH_8814B(x, v)                                         \
+	(BIT_CLEAR_CH1_LOW_TH_8814B(x) | BIT_CH1_LOW_TH_8814B(v))
+
+/* 2 REG_TXPAGE_INT_CTRL_2_8814B */
+#define BIT_CH2_INT_EN_8814B BIT(31)
+
+#define BIT_SHIFT_CH2_HIGH_TH_8814B 16
+#define BIT_MASK_CH2_HIGH_TH_8814B 0xfff
+#define BIT_CH2_HIGH_TH_8814B(x)                                               \
+	(((x) & BIT_MASK_CH2_HIGH_TH_8814B) << BIT_SHIFT_CH2_HIGH_TH_8814B)
+#define BITS_CH2_HIGH_TH_8814B                                                 \
+	(BIT_MASK_CH2_HIGH_TH_8814B << BIT_SHIFT_CH2_HIGH_TH_8814B)
+#define BIT_CLEAR_CH2_HIGH_TH_8814B(x) ((x) & (~BITS_CH2_HIGH_TH_8814B))
+#define BIT_GET_CH2_HIGH_TH_8814B(x)                                           \
+	(((x) >> BIT_SHIFT_CH2_HIGH_TH_8814B) & BIT_MASK_CH2_HIGH_TH_8814B)
+#define BIT_SET_CH2_HIGH_TH_8814B(x, v)                                        \
+	(BIT_CLEAR_CH2_HIGH_TH_8814B(x) | BIT_CH2_HIGH_TH_8814B(v))
+
+#define BIT_SHIFT_CH2_LOW_TH_8814B 0
+#define BIT_MASK_CH2_LOW_TH_8814B 0xfff
+#define BIT_CH2_LOW_TH_8814B(x)                                                \
+	(((x) & BIT_MASK_CH2_LOW_TH_8814B) << BIT_SHIFT_CH2_LOW_TH_8814B)
+#define BITS_CH2_LOW_TH_8814B                                                  \
+	(BIT_MASK_CH2_LOW_TH_8814B << BIT_SHIFT_CH2_LOW_TH_8814B)
+#define BIT_CLEAR_CH2_LOW_TH_8814B(x) ((x) & (~BITS_CH2_LOW_TH_8814B))
+#define BIT_GET_CH2_LOW_TH_8814B(x)                                            \
+	(((x) >> BIT_SHIFT_CH2_LOW_TH_8814B) & BIT_MASK_CH2_LOW_TH_8814B)
+#define BIT_SET_CH2_LOW_TH_8814B(x, v)                                         \
+	(BIT_CLEAR_CH2_LOW_TH_8814B(x) | BIT_CH2_LOW_TH_8814B(v))
+
+/* 2 REG_TXPAGE_INT_CTRL_3_8814B */
+#define BIT_CH3_INT_EN_8814B BIT(31)
+
+#define BIT_SHIFT_CH3_HIGH_TH_8814B 16
+#define BIT_MASK_CH3_HIGH_TH_8814B 0xfff
+#define BIT_CH3_HIGH_TH_8814B(x)                                               \
+	(((x) & BIT_MASK_CH3_HIGH_TH_8814B) << BIT_SHIFT_CH3_HIGH_TH_8814B)
+#define BITS_CH3_HIGH_TH_8814B                                                 \
+	(BIT_MASK_CH3_HIGH_TH_8814B << BIT_SHIFT_CH3_HIGH_TH_8814B)
+#define BIT_CLEAR_CH3_HIGH_TH_8814B(x) ((x) & (~BITS_CH3_HIGH_TH_8814B))
+#define BIT_GET_CH3_HIGH_TH_8814B(x)                                           \
+	(((x) >> BIT_SHIFT_CH3_HIGH_TH_8814B) & BIT_MASK_CH3_HIGH_TH_8814B)
+#define BIT_SET_CH3_HIGH_TH_8814B(x, v)                                        \
+	(BIT_CLEAR_CH3_HIGH_TH_8814B(x) | BIT_CH3_HIGH_TH_8814B(v))
+
+#define BIT_SHIFT_CH3_LOW_TH_8814B 0
+#define BIT_MASK_CH3_LOW_TH_8814B 0xfff
+#define BIT_CH3_LOW_TH_8814B(x)                                                \
+	(((x) & BIT_MASK_CH3_LOW_TH_8814B) << BIT_SHIFT_CH3_LOW_TH_8814B)
+#define BITS_CH3_LOW_TH_8814B                                                  \
+	(BIT_MASK_CH3_LOW_TH_8814B << BIT_SHIFT_CH3_LOW_TH_8814B)
+#define BIT_CLEAR_CH3_LOW_TH_8814B(x) ((x) & (~BITS_CH3_LOW_TH_8814B))
+#define BIT_GET_CH3_LOW_TH_8814B(x)                                            \
+	(((x) >> BIT_SHIFT_CH3_LOW_TH_8814B) & BIT_MASK_CH3_LOW_TH_8814B)
+#define BIT_SET_CH3_LOW_TH_8814B(x, v)                                         \
+	(BIT_CLEAR_CH3_LOW_TH_8814B(x) | BIT_CH3_LOW_TH_8814B(v))
+
+/* 2 REG_TXPAGE_INT_CTRL_4_8814B */
+#define BIT_CH4_INT_EN_8814B BIT(31)
+
+#define BIT_SHIFT_CH4_HIGH_TH_8814B 16
+#define BIT_MASK_CH4_HIGH_TH_8814B 0xfff
+#define BIT_CH4_HIGH_TH_8814B(x)                                               \
+	(((x) & BIT_MASK_CH4_HIGH_TH_8814B) << BIT_SHIFT_CH4_HIGH_TH_8814B)
+#define BITS_CH4_HIGH_TH_8814B                                                 \
+	(BIT_MASK_CH4_HIGH_TH_8814B << BIT_SHIFT_CH4_HIGH_TH_8814B)
+#define BIT_CLEAR_CH4_HIGH_TH_8814B(x) ((x) & (~BITS_CH4_HIGH_TH_8814B))
+#define BIT_GET_CH4_HIGH_TH_8814B(x)                                           \
+	(((x) >> BIT_SHIFT_CH4_HIGH_TH_8814B) & BIT_MASK_CH4_HIGH_TH_8814B)
+#define BIT_SET_CH4_HIGH_TH_8814B(x, v)                                        \
+	(BIT_CLEAR_CH4_HIGH_TH_8814B(x) | BIT_CH4_HIGH_TH_8814B(v))
+
+#define BIT_SHIFT_CH4_LOW_TH_8814B 0
+#define BIT_MASK_CH4_LOW_TH_8814B 0xfff
+#define BIT_CH4_LOW_TH_8814B(x)                                                \
+	(((x) & BIT_MASK_CH4_LOW_TH_8814B) << BIT_SHIFT_CH4_LOW_TH_8814B)
+#define BITS_CH4_LOW_TH_8814B                                                  \
+	(BIT_MASK_CH4_LOW_TH_8814B << BIT_SHIFT_CH4_LOW_TH_8814B)
+#define BIT_CLEAR_CH4_LOW_TH_8814B(x) ((x) & (~BITS_CH4_LOW_TH_8814B))
+#define BIT_GET_CH4_LOW_TH_8814B(x)                                            \
+	(((x) >> BIT_SHIFT_CH4_LOW_TH_8814B) & BIT_MASK_CH4_LOW_TH_8814B)
+#define BIT_SET_CH4_LOW_TH_8814B(x, v)                                         \
+	(BIT_CLEAR_CH4_LOW_TH_8814B(x) | BIT_CH4_LOW_TH_8814B(v))
+
+/* 2 REG_TXPAGE_INT_CTRL_5_8814B */
+#define BIT_CH5_INT_EN_8814B BIT(31)
+
+#define BIT_SHIFT_CH5_HIGH_TH_8814B 16
+#define BIT_MASK_CH5_HIGH_TH_8814B 0xfff
+#define BIT_CH5_HIGH_TH_8814B(x)                                               \
+	(((x) & BIT_MASK_CH5_HIGH_TH_8814B) << BIT_SHIFT_CH5_HIGH_TH_8814B)
+#define BITS_CH5_HIGH_TH_8814B                                                 \
+	(BIT_MASK_CH5_HIGH_TH_8814B << BIT_SHIFT_CH5_HIGH_TH_8814B)
+#define BIT_CLEAR_CH5_HIGH_TH_8814B(x) ((x) & (~BITS_CH5_HIGH_TH_8814B))
+#define BIT_GET_CH5_HIGH_TH_8814B(x)                                           \
+	(((x) >> BIT_SHIFT_CH5_HIGH_TH_8814B) & BIT_MASK_CH5_HIGH_TH_8814B)
+#define BIT_SET_CH5_HIGH_TH_8814B(x, v)                                        \
+	(BIT_CLEAR_CH5_HIGH_TH_8814B(x) | BIT_CH5_HIGH_TH_8814B(v))
+
+#define BIT_SHIFT_CH5_LOW_TH_8814B 0
+#define BIT_MASK_CH5_LOW_TH_8814B 0xfff
+#define BIT_CH5_LOW_TH_8814B(x)                                                \
+	(((x) & BIT_MASK_CH5_LOW_TH_8814B) << BIT_SHIFT_CH5_LOW_TH_8814B)
+#define BITS_CH5_LOW_TH_8814B                                                  \
+	(BIT_MASK_CH5_LOW_TH_8814B << BIT_SHIFT_CH5_LOW_TH_8814B)
+#define BIT_CLEAR_CH5_LOW_TH_8814B(x) ((x) & (~BITS_CH5_LOW_TH_8814B))
+#define BIT_GET_CH5_LOW_TH_8814B(x)                                            \
+	(((x) >> BIT_SHIFT_CH5_LOW_TH_8814B) & BIT_MASK_CH5_LOW_TH_8814B)
+#define BIT_SET_CH5_LOW_TH_8814B(x, v)                                         \
+	(BIT_CLEAR_CH5_LOW_TH_8814B(x) | BIT_CH5_LOW_TH_8814B(v))
+
+/* 2 REG_TXPAGE_INT_CTRL_6_8814B */
+#define BIT_CH6_INT_EN_8814B BIT(31)
+
+#define BIT_SHIFT_CH6_HIGH_TH_8814B 16
+#define BIT_MASK_CH6_HIGH_TH_8814B 0xfff
+#define BIT_CH6_HIGH_TH_8814B(x)                                               \
+	(((x) & BIT_MASK_CH6_HIGH_TH_8814B) << BIT_SHIFT_CH6_HIGH_TH_8814B)
+#define BITS_CH6_HIGH_TH_8814B                                                 \
+	(BIT_MASK_CH6_HIGH_TH_8814B << BIT_SHIFT_CH6_HIGH_TH_8814B)
+#define BIT_CLEAR_CH6_HIGH_TH_8814B(x) ((x) & (~BITS_CH6_HIGH_TH_8814B))
+#define BIT_GET_CH6_HIGH_TH_8814B(x)                                           \
+	(((x) >> BIT_SHIFT_CH6_HIGH_TH_8814B) & BIT_MASK_CH6_HIGH_TH_8814B)
+#define BIT_SET_CH6_HIGH_TH_8814B(x, v)                                        \
+	(BIT_CLEAR_CH6_HIGH_TH_8814B(x) | BIT_CH6_HIGH_TH_8814B(v))
+
+#define BIT_SHIFT_CH6_LOW_TH_8814B 0
+#define BIT_MASK_CH6_LOW_TH_8814B 0xfff
+#define BIT_CH6_LOW_TH_8814B(x)                                                \
+	(((x) & BIT_MASK_CH6_LOW_TH_8814B) << BIT_SHIFT_CH6_LOW_TH_8814B)
+#define BITS_CH6_LOW_TH_8814B                                                  \
+	(BIT_MASK_CH6_LOW_TH_8814B << BIT_SHIFT_CH6_LOW_TH_8814B)
+#define BIT_CLEAR_CH6_LOW_TH_8814B(x) ((x) & (~BITS_CH6_LOW_TH_8814B))
+#define BIT_GET_CH6_LOW_TH_8814B(x)                                            \
+	(((x) >> BIT_SHIFT_CH6_LOW_TH_8814B) & BIT_MASK_CH6_LOW_TH_8814B)
+#define BIT_SET_CH6_LOW_TH_8814B(x, v)                                         \
+	(BIT_CLEAR_CH6_LOW_TH_8814B(x) | BIT_CH6_LOW_TH_8814B(v))
+
+/* 2 REG_TXPAGE_INT_CTRL_7_8814B */
+#define BIT_CH7_INT_EN_8814B BIT(31)
+
+#define BIT_SHIFT_CH7_HIGH_TH_8814B 16
+#define BIT_MASK_CH7_HIGH_TH_8814B 0xfff
+#define BIT_CH7_HIGH_TH_8814B(x)                                               \
+	(((x) & BIT_MASK_CH7_HIGH_TH_8814B) << BIT_SHIFT_CH7_HIGH_TH_8814B)
+#define BITS_CH7_HIGH_TH_8814B                                                 \
+	(BIT_MASK_CH7_HIGH_TH_8814B << BIT_SHIFT_CH7_HIGH_TH_8814B)
+#define BIT_CLEAR_CH7_HIGH_TH_8814B(x) ((x) & (~BITS_CH7_HIGH_TH_8814B))
+#define BIT_GET_CH7_HIGH_TH_8814B(x)                                           \
+	(((x) >> BIT_SHIFT_CH7_HIGH_TH_8814B) & BIT_MASK_CH7_HIGH_TH_8814B)
+#define BIT_SET_CH7_HIGH_TH_8814B(x, v)                                        \
+	(BIT_CLEAR_CH7_HIGH_TH_8814B(x) | BIT_CH7_HIGH_TH_8814B(v))
+
+#define BIT_SHIFT_CH7_LOW_TH_8814B 0
+#define BIT_MASK_CH7_LOW_TH_8814B 0xfff
+#define BIT_CH7_LOW_TH_8814B(x)                                                \
+	(((x) & BIT_MASK_CH7_LOW_TH_8814B) << BIT_SHIFT_CH7_LOW_TH_8814B)
+#define BITS_CH7_LOW_TH_8814B                                                  \
+	(BIT_MASK_CH7_LOW_TH_8814B << BIT_SHIFT_CH7_LOW_TH_8814B)
+#define BIT_CLEAR_CH7_LOW_TH_8814B(x) ((x) & (~BITS_CH7_LOW_TH_8814B))
+#define BIT_GET_CH7_LOW_TH_8814B(x)                                            \
+	(((x) >> BIT_SHIFT_CH7_LOW_TH_8814B) & BIT_MASK_CH7_LOW_TH_8814B)
+#define BIT_SET_CH7_LOW_TH_8814B(x, v)                                         \
+	(BIT_CLEAR_CH7_LOW_TH_8814B(x) | BIT_CH7_LOW_TH_8814B(v))
+
+/* 2 REG_TXPAGE_INT_CTRL_8_8814B */
+#define BIT_CH8_INT_EN_8814B BIT(31)
+
+#define BIT_SHIFT_CH8_HIGH_TH_8814B 16
+#define BIT_MASK_CH8_HIGH_TH_8814B 0xfff
+#define BIT_CH8_HIGH_TH_8814B(x)                                               \
+	(((x) & BIT_MASK_CH8_HIGH_TH_8814B) << BIT_SHIFT_CH8_HIGH_TH_8814B)
+#define BITS_CH8_HIGH_TH_8814B                                                 \
+	(BIT_MASK_CH8_HIGH_TH_8814B << BIT_SHIFT_CH8_HIGH_TH_8814B)
+#define BIT_CLEAR_CH8_HIGH_TH_8814B(x) ((x) & (~BITS_CH8_HIGH_TH_8814B))
+#define BIT_GET_CH8_HIGH_TH_8814B(x)                                           \
+	(((x) >> BIT_SHIFT_CH8_HIGH_TH_8814B) & BIT_MASK_CH8_HIGH_TH_8814B)
+#define BIT_SET_CH8_HIGH_TH_8814B(x, v)                                        \
+	(BIT_CLEAR_CH8_HIGH_TH_8814B(x) | BIT_CH8_HIGH_TH_8814B(v))
+
+#define BIT_SHIFT_CH8_LOW_TH_8814B 0
+#define BIT_MASK_CH8_LOW_TH_8814B 0xfff
+#define BIT_CH8_LOW_TH_8814B(x)                                                \
+	(((x) & BIT_MASK_CH8_LOW_TH_8814B) << BIT_SHIFT_CH8_LOW_TH_8814B)
+#define BITS_CH8_LOW_TH_8814B                                                  \
+	(BIT_MASK_CH8_LOW_TH_8814B << BIT_SHIFT_CH8_LOW_TH_8814B)
+#define BIT_CLEAR_CH8_LOW_TH_8814B(x) ((x) & (~BITS_CH8_LOW_TH_8814B))
+#define BIT_GET_CH8_LOW_TH_8814B(x)                                            \
+	(((x) >> BIT_SHIFT_CH8_LOW_TH_8814B) & BIT_MASK_CH8_LOW_TH_8814B)
+#define BIT_SET_CH8_LOW_TH_8814B(x, v)                                         \
+	(BIT_CLEAR_CH8_LOW_TH_8814B(x) | BIT_CH8_LOW_TH_8814B(v))
+
+/* 2 REG_TXPAGE_INT_CTRL_9_8814B */
+#define BIT_CH9_INT_EN_8814B BIT(31)
+
+#define BIT_SHIFT_CH9_HIGH_TH_8814B 16
+#define BIT_MASK_CH9_HIGH_TH_8814B 0xfff
+#define BIT_CH9_HIGH_TH_8814B(x)                                               \
+	(((x) & BIT_MASK_CH9_HIGH_TH_8814B) << BIT_SHIFT_CH9_HIGH_TH_8814B)
+#define BITS_CH9_HIGH_TH_8814B                                                 \
+	(BIT_MASK_CH9_HIGH_TH_8814B << BIT_SHIFT_CH9_HIGH_TH_8814B)
+#define BIT_CLEAR_CH9_HIGH_TH_8814B(x) ((x) & (~BITS_CH9_HIGH_TH_8814B))
+#define BIT_GET_CH9_HIGH_TH_8814B(x)                                           \
+	(((x) >> BIT_SHIFT_CH9_HIGH_TH_8814B) & BIT_MASK_CH9_HIGH_TH_8814B)
+#define BIT_SET_CH9_HIGH_TH_8814B(x, v)                                        \
+	(BIT_CLEAR_CH9_HIGH_TH_8814B(x) | BIT_CH9_HIGH_TH_8814B(v))
+
+#define BIT_SHIFT_CH9_LOW_TH_8814B 0
+#define BIT_MASK_CH9_LOW_TH_8814B 0xfff
+#define BIT_CH9_LOW_TH_8814B(x)                                                \
+	(((x) & BIT_MASK_CH9_LOW_TH_8814B) << BIT_SHIFT_CH9_LOW_TH_8814B)
+#define BITS_CH9_LOW_TH_8814B                                                  \
+	(BIT_MASK_CH9_LOW_TH_8814B << BIT_SHIFT_CH9_LOW_TH_8814B)
+#define BIT_CLEAR_CH9_LOW_TH_8814B(x) ((x) & (~BITS_CH9_LOW_TH_8814B))
+#define BIT_GET_CH9_LOW_TH_8814B(x)                                            \
+	(((x) >> BIT_SHIFT_CH9_LOW_TH_8814B) & BIT_MASK_CH9_LOW_TH_8814B)
+#define BIT_SET_CH9_LOW_TH_8814B(x, v)                                         \
+	(BIT_CLEAR_CH9_LOW_TH_8814B(x) | BIT_CH9_LOW_TH_8814B(v))
+
+/* 2 REG_TXPAGE_INT_CTRL_10_8814B */
+#define BIT_CH10_INT_EN_8814B BIT(31)
+
+#define BIT_SHIFT_CH10_HIGH_TH_8814B 16
+#define BIT_MASK_CH10_HIGH_TH_8814B 0xfff
+#define BIT_CH10_HIGH_TH_8814B(x)                                              \
+	(((x) & BIT_MASK_CH10_HIGH_TH_8814B) << BIT_SHIFT_CH10_HIGH_TH_8814B)
+#define BITS_CH10_HIGH_TH_8814B                                                \
+	(BIT_MASK_CH10_HIGH_TH_8814B << BIT_SHIFT_CH10_HIGH_TH_8814B)
+#define BIT_CLEAR_CH10_HIGH_TH_8814B(x) ((x) & (~BITS_CH10_HIGH_TH_8814B))
+#define BIT_GET_CH10_HIGH_TH_8814B(x)                                          \
+	(((x) >> BIT_SHIFT_CH10_HIGH_TH_8814B) & BIT_MASK_CH10_HIGH_TH_8814B)
+#define BIT_SET_CH10_HIGH_TH_8814B(x, v)                                       \
+	(BIT_CLEAR_CH10_HIGH_TH_8814B(x) | BIT_CH10_HIGH_TH_8814B(v))
+
+#define BIT_SHIFT_CH10_LOW_TH_8814B 0
+#define BIT_MASK_CH10_LOW_TH_8814B 0xfff
+#define BIT_CH10_LOW_TH_8814B(x)                                               \
+	(((x) & BIT_MASK_CH10_LOW_TH_8814B) << BIT_SHIFT_CH10_LOW_TH_8814B)
+#define BITS_CH10_LOW_TH_8814B                                                 \
+	(BIT_MASK_CH10_LOW_TH_8814B << BIT_SHIFT_CH10_LOW_TH_8814B)
+#define BIT_CLEAR_CH10_LOW_TH_8814B(x) ((x) & (~BITS_CH10_LOW_TH_8814B))
+#define BIT_GET_CH10_LOW_TH_8814B(x)                                           \
+	(((x) >> BIT_SHIFT_CH10_LOW_TH_8814B) & BIT_MASK_CH10_LOW_TH_8814B)
+#define BIT_SET_CH10_LOW_TH_8814B(x, v)                                        \
+	(BIT_CLEAR_CH10_LOW_TH_8814B(x) | BIT_CH10_LOW_TH_8814B(v))
+
+/* 2 REG_TXPAGE_INT_CTRL_11_8814B */
+#define BIT_CH11_INT_EN_8814B BIT(31)
+
+#define BIT_SHIFT_CH11_HIGH_TH_8814B 16
+#define BIT_MASK_CH11_HIGH_TH_8814B 0xfff
+#define BIT_CH11_HIGH_TH_8814B(x)                                              \
+	(((x) & BIT_MASK_CH11_HIGH_TH_8814B) << BIT_SHIFT_CH11_HIGH_TH_8814B)
+#define BITS_CH11_HIGH_TH_8814B                                                \
+	(BIT_MASK_CH11_HIGH_TH_8814B << BIT_SHIFT_CH11_HIGH_TH_8814B)
+#define BIT_CLEAR_CH11_HIGH_TH_8814B(x) ((x) & (~BITS_CH11_HIGH_TH_8814B))
+#define BIT_GET_CH11_HIGH_TH_8814B(x)                                          \
+	(((x) >> BIT_SHIFT_CH11_HIGH_TH_8814B) & BIT_MASK_CH11_HIGH_TH_8814B)
+#define BIT_SET_CH11_HIGH_TH_8814B(x, v)                                       \
+	(BIT_CLEAR_CH11_HIGH_TH_8814B(x) | BIT_CH11_HIGH_TH_8814B(v))
+
+#define BIT_SHIFT_CH11_LOW_TH_8814B 0
+#define BIT_MASK_CH11_LOW_TH_8814B 0xfff
+#define BIT_CH11_LOW_TH_8814B(x)                                               \
+	(((x) & BIT_MASK_CH11_LOW_TH_8814B) << BIT_SHIFT_CH11_LOW_TH_8814B)
+#define BITS_CH11_LOW_TH_8814B                                                 \
+	(BIT_MASK_CH11_LOW_TH_8814B << BIT_SHIFT_CH11_LOW_TH_8814B)
+#define BIT_CLEAR_CH11_LOW_TH_8814B(x) ((x) & (~BITS_CH11_LOW_TH_8814B))
+#define BIT_GET_CH11_LOW_TH_8814B(x)                                           \
+	(((x) >> BIT_SHIFT_CH11_LOW_TH_8814B) & BIT_MASK_CH11_LOW_TH_8814B)
+#define BIT_SET_CH11_LOW_TH_8814B(x, v)                                        \
+	(BIT_CLEAR_CH11_LOW_TH_8814B(x) | BIT_CH11_LOW_TH_8814B(v))
+
+/* 2 REG_TXPAGE_INT_CTRL_12_8814B */
+#define BIT_CH12_INT_EN_8814B BIT(31)
+
+#define BIT_SHIFT_CH12_HIGH_TH_8814B 16
+#define BIT_MASK_CH12_HIGH_TH_8814B 0xfff
+#define BIT_CH12_HIGH_TH_8814B(x)                                              \
+	(((x) & BIT_MASK_CH12_HIGH_TH_8814B) << BIT_SHIFT_CH12_HIGH_TH_8814B)
+#define BITS_CH12_HIGH_TH_8814B                                                \
+	(BIT_MASK_CH12_HIGH_TH_8814B << BIT_SHIFT_CH12_HIGH_TH_8814B)
+#define BIT_CLEAR_CH12_HIGH_TH_8814B(x) ((x) & (~BITS_CH12_HIGH_TH_8814B))
+#define BIT_GET_CH12_HIGH_TH_8814B(x)                                          \
+	(((x) >> BIT_SHIFT_CH12_HIGH_TH_8814B) & BIT_MASK_CH12_HIGH_TH_8814B)
+#define BIT_SET_CH12_HIGH_TH_8814B(x, v)                                       \
+	(BIT_CLEAR_CH12_HIGH_TH_8814B(x) | BIT_CH12_HIGH_TH_8814B(v))
+
+#define BIT_SHIFT_CH12_LOW_TH_8814B 0
+#define BIT_MASK_CH12_LOW_TH_8814B 0xfff
+#define BIT_CH12_LOW_TH_8814B(x)                                               \
+	(((x) & BIT_MASK_CH12_LOW_TH_8814B) << BIT_SHIFT_CH12_LOW_TH_8814B)
+#define BITS_CH12_LOW_TH_8814B                                                 \
+	(BIT_MASK_CH12_LOW_TH_8814B << BIT_SHIFT_CH12_LOW_TH_8814B)
+#define BIT_CLEAR_CH12_LOW_TH_8814B(x) ((x) & (~BITS_CH12_LOW_TH_8814B))
+#define BIT_GET_CH12_LOW_TH_8814B(x)                                           \
+	(((x) >> BIT_SHIFT_CH12_LOW_TH_8814B) & BIT_MASK_CH12_LOW_TH_8814B)
+#define BIT_SET_CH12_LOW_TH_8814B(x, v)                                        \
+	(BIT_CLEAR_CH12_LOW_TH_8814B(x) | BIT_CH12_LOW_TH_8814B(v))
+
+/* 2 REG_TXPAGE_INT_CTRL_13_8814B */
+#define BIT_CH13_INT_EN_8814B BIT(31)
+
+#define BIT_SHIFT_CH13_HIGH_TH_8814B 16
+#define BIT_MASK_CH13_HIGH_TH_8814B 0xfff
+#define BIT_CH13_HIGH_TH_8814B(x)                                              \
+	(((x) & BIT_MASK_CH13_HIGH_TH_8814B) << BIT_SHIFT_CH13_HIGH_TH_8814B)
+#define BITS_CH13_HIGH_TH_8814B                                                \
+	(BIT_MASK_CH13_HIGH_TH_8814B << BIT_SHIFT_CH13_HIGH_TH_8814B)
+#define BIT_CLEAR_CH13_HIGH_TH_8814B(x) ((x) & (~BITS_CH13_HIGH_TH_8814B))
+#define BIT_GET_CH13_HIGH_TH_8814B(x)                                          \
+	(((x) >> BIT_SHIFT_CH13_HIGH_TH_8814B) & BIT_MASK_CH13_HIGH_TH_8814B)
+#define BIT_SET_CH13_HIGH_TH_8814B(x, v)                                       \
+	(BIT_CLEAR_CH13_HIGH_TH_8814B(x) | BIT_CH13_HIGH_TH_8814B(v))
+
+#define BIT_SHIFT_CH13_LOW_TH_8814B 0
+#define BIT_MASK_CH13_LOW_TH_8814B 0xfff
+#define BIT_CH13_LOW_TH_8814B(x)                                               \
+	(((x) & BIT_MASK_CH13_LOW_TH_8814B) << BIT_SHIFT_CH13_LOW_TH_8814B)
+#define BITS_CH13_LOW_TH_8814B                                                 \
+	(BIT_MASK_CH13_LOW_TH_8814B << BIT_SHIFT_CH13_LOW_TH_8814B)
+#define BIT_CLEAR_CH13_LOW_TH_8814B(x) ((x) & (~BITS_CH13_LOW_TH_8814B))
+#define BIT_GET_CH13_LOW_TH_8814B(x)                                           \
+	(((x) >> BIT_SHIFT_CH13_LOW_TH_8814B) & BIT_MASK_CH13_LOW_TH_8814B)
+#define BIT_SET_CH13_LOW_TH_8814B(x, v)                                        \
+	(BIT_CLEAR_CH13_LOW_TH_8814B(x) | BIT_CH13_LOW_TH_8814B(v))
+
+/* 2 REG_TXPAGE_INT_CTRL_14_8814B */
+#define BIT_CH14_INT_EN_8814B BIT(31)
+
+#define BIT_SHIFT_CH14_HIGH_TH_8814B 16
+#define BIT_MASK_CH14_HIGH_TH_8814B 0xfff
+#define BIT_CH14_HIGH_TH_8814B(x)                                              \
+	(((x) & BIT_MASK_CH14_HIGH_TH_8814B) << BIT_SHIFT_CH14_HIGH_TH_8814B)
+#define BITS_CH14_HIGH_TH_8814B                                                \
+	(BIT_MASK_CH14_HIGH_TH_8814B << BIT_SHIFT_CH14_HIGH_TH_8814B)
+#define BIT_CLEAR_CH14_HIGH_TH_8814B(x) ((x) & (~BITS_CH14_HIGH_TH_8814B))
+#define BIT_GET_CH14_HIGH_TH_8814B(x)                                          \
+	(((x) >> BIT_SHIFT_CH14_HIGH_TH_8814B) & BIT_MASK_CH14_HIGH_TH_8814B)
+#define BIT_SET_CH14_HIGH_TH_8814B(x, v)                                       \
+	(BIT_CLEAR_CH14_HIGH_TH_8814B(x) | BIT_CH14_HIGH_TH_8814B(v))
+
+#define BIT_SHIFT_CH14_LOW_TH_8814B 0
+#define BIT_MASK_CH14_LOW_TH_8814B 0xfff
+#define BIT_CH14_LOW_TH_8814B(x)                                               \
+	(((x) & BIT_MASK_CH14_LOW_TH_8814B) << BIT_SHIFT_CH14_LOW_TH_8814B)
+#define BITS_CH14_LOW_TH_8814B                                                 \
+	(BIT_MASK_CH14_LOW_TH_8814B << BIT_SHIFT_CH14_LOW_TH_8814B)
+#define BIT_CLEAR_CH14_LOW_TH_8814B(x) ((x) & (~BITS_CH14_LOW_TH_8814B))
+#define BIT_GET_CH14_LOW_TH_8814B(x)                                           \
+	(((x) >> BIT_SHIFT_CH14_LOW_TH_8814B) & BIT_MASK_CH14_LOW_TH_8814B)
+#define BIT_SET_CH14_LOW_TH_8814B(x, v)                                        \
+	(BIT_CLEAR_CH14_LOW_TH_8814B(x) | BIT_CH14_LOW_TH_8814B(v))
+
+/* 2 REG_TXPAGE_INT_CTRL_15_8814B */
+#define BIT_CH15_INT_EN_8814B BIT(31)
+
+#define BIT_SHIFT_CH15_HIGH_TH_8814B 16
+#define BIT_MASK_CH15_HIGH_TH_8814B 0xfff
+#define BIT_CH15_HIGH_TH_8814B(x)                                              \
+	(((x) & BIT_MASK_CH15_HIGH_TH_8814B) << BIT_SHIFT_CH15_HIGH_TH_8814B)
+#define BITS_CH15_HIGH_TH_8814B                                                \
+	(BIT_MASK_CH15_HIGH_TH_8814B << BIT_SHIFT_CH15_HIGH_TH_8814B)
+#define BIT_CLEAR_CH15_HIGH_TH_8814B(x) ((x) & (~BITS_CH15_HIGH_TH_8814B))
+#define BIT_GET_CH15_HIGH_TH_8814B(x)                                          \
+	(((x) >> BIT_SHIFT_CH15_HIGH_TH_8814B) & BIT_MASK_CH15_HIGH_TH_8814B)
+#define BIT_SET_CH15_HIGH_TH_8814B(x, v)                                       \
+	(BIT_CLEAR_CH15_HIGH_TH_8814B(x) | BIT_CH15_HIGH_TH_8814B(v))
+
+#define BIT_SHIFT_CH15_LOW_TH_8814B 0
+#define BIT_MASK_CH15_LOW_TH_8814B 0xfff
+#define BIT_CH15_LOW_TH_8814B(x)                                               \
+	(((x) & BIT_MASK_CH15_LOW_TH_8814B) << BIT_SHIFT_CH15_LOW_TH_8814B)
+#define BITS_CH15_LOW_TH_8814B                                                 \
+	(BIT_MASK_CH15_LOW_TH_8814B << BIT_SHIFT_CH15_LOW_TH_8814B)
+#define BIT_CLEAR_CH15_LOW_TH_8814B(x) ((x) & (~BITS_CH15_LOW_TH_8814B))
+#define BIT_GET_CH15_LOW_TH_8814B(x)                                           \
+	(((x) >> BIT_SHIFT_CH15_LOW_TH_8814B) & BIT_MASK_CH15_LOW_TH_8814B)
+#define BIT_SET_CH15_LOW_TH_8814B(x, v)                                        \
+	(BIT_CLEAR_CH15_LOW_TH_8814B(x) | BIT_CH15_LOW_TH_8814B(v))
+
+/* 2 REG_TXPAGE_INT_CTRL_16_8814B */
+#define BIT_CH16_INT_EN_8814B BIT(31)
+
+#define BIT_SHIFT_CH16_HIGH_TH_8814B 16
+#define BIT_MASK_CH16_HIGH_TH_8814B 0xfff
+#define BIT_CH16_HIGH_TH_8814B(x)                                              \
+	(((x) & BIT_MASK_CH16_HIGH_TH_8814B) << BIT_SHIFT_CH16_HIGH_TH_8814B)
+#define BITS_CH16_HIGH_TH_8814B                                                \
+	(BIT_MASK_CH16_HIGH_TH_8814B << BIT_SHIFT_CH16_HIGH_TH_8814B)
+#define BIT_CLEAR_CH16_HIGH_TH_8814B(x) ((x) & (~BITS_CH16_HIGH_TH_8814B))
+#define BIT_GET_CH16_HIGH_TH_8814B(x)                                          \
+	(((x) >> BIT_SHIFT_CH16_HIGH_TH_8814B) & BIT_MASK_CH16_HIGH_TH_8814B)
+#define BIT_SET_CH16_HIGH_TH_8814B(x, v)                                       \
+	(BIT_CLEAR_CH16_HIGH_TH_8814B(x) | BIT_CH16_HIGH_TH_8814B(v))
+
+#define BIT_SHIFT_CH16_LOW_TH_8814B 0
+#define BIT_MASK_CH16_LOW_TH_8814B 0xfff
+#define BIT_CH16_LOW_TH_8814B(x)                                               \
+	(((x) & BIT_MASK_CH16_LOW_TH_8814B) << BIT_SHIFT_CH16_LOW_TH_8814B)
+#define BITS_CH16_LOW_TH_8814B                                                 \
+	(BIT_MASK_CH16_LOW_TH_8814B << BIT_SHIFT_CH16_LOW_TH_8814B)
+#define BIT_CLEAR_CH16_LOW_TH_8814B(x) ((x) & (~BITS_CH16_LOW_TH_8814B))
+#define BIT_GET_CH16_LOW_TH_8814B(x)                                           \
+	(((x) >> BIT_SHIFT_CH16_LOW_TH_8814B) & BIT_MASK_CH16_LOW_TH_8814B)
+#define BIT_SET_CH16_LOW_TH_8814B(x, v)                                        \
+	(BIT_CLEAR_CH16_LOW_TH_8814B(x) | BIT_CH16_LOW_TH_8814B(v))
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_PCIE_CTRL_8814B */
+#define BIT_PCIEIO_PERSTB_SEL_8814B BIT(31)
+
+#define BIT_SHIFT_PCIE_MAX_RXDMA_8814B 28
+#define BIT_MASK_PCIE_MAX_RXDMA_8814B 0x7
+#define BIT_PCIE_MAX_RXDMA_8814B(x)                                            \
+	(((x) & BIT_MASK_PCIE_MAX_RXDMA_8814B)                                 \
+	 << BIT_SHIFT_PCIE_MAX_RXDMA_8814B)
+#define BITS_PCIE_MAX_RXDMA_8814B                                              \
+	(BIT_MASK_PCIE_MAX_RXDMA_8814B << BIT_SHIFT_PCIE_MAX_RXDMA_8814B)
+#define BIT_CLEAR_PCIE_MAX_RXDMA_8814B(x) ((x) & (~BITS_PCIE_MAX_RXDMA_8814B))
+#define BIT_GET_PCIE_MAX_RXDMA_8814B(x)                                        \
+	(((x) >> BIT_SHIFT_PCIE_MAX_RXDMA_8814B) &                             \
+	 BIT_MASK_PCIE_MAX_RXDMA_8814B)
+#define BIT_SET_PCIE_MAX_RXDMA_8814B(x, v)                                     \
+	(BIT_CLEAR_PCIE_MAX_RXDMA_8814B(x) | BIT_PCIE_MAX_RXDMA_8814B(v))
+
+#define BIT_MULRW_8814B BIT(27)
+
+#define BIT_SHIFT_PCIE_MAX_TXDMA_8814B 24
+#define BIT_MASK_PCIE_MAX_TXDMA_8814B 0x7
+#define BIT_PCIE_MAX_TXDMA_8814B(x)                                            \
+	(((x) & BIT_MASK_PCIE_MAX_TXDMA_8814B)                                 \
+	 << BIT_SHIFT_PCIE_MAX_TXDMA_8814B)
+#define BITS_PCIE_MAX_TXDMA_8814B                                              \
+	(BIT_MASK_PCIE_MAX_TXDMA_8814B << BIT_SHIFT_PCIE_MAX_TXDMA_8814B)
+#define BIT_CLEAR_PCIE_MAX_TXDMA_8814B(x) ((x) & (~BITS_PCIE_MAX_TXDMA_8814B))
+#define BIT_GET_PCIE_MAX_TXDMA_8814B(x)                                        \
+	(((x) >> BIT_SHIFT_PCIE_MAX_TXDMA_8814B) &                             \
+	 BIT_MASK_PCIE_MAX_TXDMA_8814B)
+#define BIT_SET_PCIE_MAX_TXDMA_8814B(x, v)                                     \
+	(BIT_CLEAR_PCIE_MAX_TXDMA_8814B(x) | BIT_PCIE_MAX_TXDMA_8814B(v))
+
+#define BIT_PWR_SCALE_START_PS_8814B BIT(23)
+#define BIT_EN_CPL_TIMEOUT_PS_8814B BIT(22)
+#define BIT_REG_TXDMA_FAIL_PS_8814B BIT(21)
+#define BIT_PCIE_RST_TRXDMA_INTF_8814B BIT(20)
+#define BIT_EN_HWENTR_L1_8814B BIT(19)
+#define BIT_EN_ADV_CLKGATE_8814B BIT(18)
+#define BIT_PCIE_EN_SWENT_L23_8814B BIT(17)
+#define BIT_PCIE_EN_HWEXT_L1_8814B BIT(16)
+#define BIT_STOP_P0_MPRT_BCNQ4_8814B BIT(6)
+#define BIT_STOP_P0_MPRT_BCNQ3_8814B BIT(4)
+#define BIT_STOP_P0_MPRT_BCNQ2_8814B BIT(2)
+#define BIT_STOP_P0_MPRT_BCNQ1_8814B BIT(0)
+
+/* 2 REG_ACH_CTRL_8814B */
+#define BIT_STOP_P0HIQ19_8814B BIT(27)
+#define BIT_STOP_P0HIQ18_8814B BIT(26)
+#define BIT_STOP_P0HIQ17_8814B BIT(25)
+#define BIT_STOP_P0HIQ16_8814B BIT(24)
+#define BIT_RX_CLOSE_EN_V1_8814B BIT(21)
+#define BIT_STOP_FWCMDQ_8814B BIT(20)
+#define BIT_STOP_P0BCNQ_8814B BIT(18)
+#define BIT_STOP_P0MGQ_8814B BIT(16)
+#define BIT_STOP_ACH13_8814B BIT(15)
+#define BIT_STOP_ACH12_8814B BIT(14)
+#define BIT_STOP_ACH11_8814B BIT(13)
+#define BIT_STOP_ACH10_8814B BIT(12)
+#define BIT_STOP_ACH9_8814B BIT(11)
+#define BIT_STOP_ACH8_8814B BIT(10)
+#define BIT_STOP_ACH7_8814B BIT(9)
+#define BIT_STOP_ACH6_8814B BIT(8)
+#define BIT_STOP_ACH5_8814B BIT(7)
+#define BIT_STOP_ACH4_8814B BIT(6)
+#define BIT_STOP_ACH3_8814B BIT(5)
+#define BIT_STOP_ACH2_8814B BIT(4)
+#define BIT_STOP_ACH1_8814B BIT(3)
+#define BIT_STOP_ACH0_8814B BIT(2)
+#define BIT_STOP_P0RX_8814B BIT(0)
+
+/* 2 REG_HIQ_CTRL_8814B */
+#define BIT_STOP_P0HIQ15_8814B BIT(15)
+#define BIT_STOP_P0HIQ14_8814B BIT(14)
+#define BIT_STOP_P0HIQ13_8814B BIT(13)
+#define BIT_STOP_P0HIQ12_8814B BIT(12)
+#define BIT_STOP_P0HIQ11_8814B BIT(11)
+#define BIT_STOP_P0HIQ10_8814B BIT(10)
+#define BIT_STOP_P0HIQ9_8814B BIT(9)
+#define BIT_STOP_P0HIQ8_8814B BIT(8)
+#define BIT_STOP_P0HIQ7_8814B BIT(7)
+#define BIT_STOP_P0HIQ6_8814B BIT(6)
+#define BIT_STOP_P0HIQ5_8814B BIT(5)
+#define BIT_STOP_P0HIQ4_8814B BIT(4)
+#define BIT_STOP_P0HIQ3_8814B BIT(3)
+#define BIT_STOP_P0HIQ2_8814B BIT(2)
+#define BIT_STOP_P0HIQ1_8814B BIT(1)
+#define BIT_STOP_P0HIQ0_8814B BIT(0)
+
+/* 2 REG_INT_MIG_V1_8814B */
+
+#define BIT_SHIFT_TXTTIMER_MATCH_NUM_8814B 28
+#define BIT_MASK_TXTTIMER_MATCH_NUM_8814B 0xf
+#define BIT_TXTTIMER_MATCH_NUM_8814B(x)                                        \
+	(((x) & BIT_MASK_TXTTIMER_MATCH_NUM_8814B)                             \
+	 << BIT_SHIFT_TXTTIMER_MATCH_NUM_8814B)
+#define BITS_TXTTIMER_MATCH_NUM_8814B                                          \
+	(BIT_MASK_TXTTIMER_MATCH_NUM_8814B                                     \
+	 << BIT_SHIFT_TXTTIMER_MATCH_NUM_8814B)
+#define BIT_CLEAR_TXTTIMER_MATCH_NUM_8814B(x)                                  \
+	((x) & (~BITS_TXTTIMER_MATCH_NUM_8814B))
+#define BIT_GET_TXTTIMER_MATCH_NUM_8814B(x)                                    \
+	(((x) >> BIT_SHIFT_TXTTIMER_MATCH_NUM_8814B) &                         \
+	 BIT_MASK_TXTTIMER_MATCH_NUM_8814B)
+#define BIT_SET_TXTTIMER_MATCH_NUM_8814B(x, v)                                 \
+	(BIT_CLEAR_TXTTIMER_MATCH_NUM_8814B(x) |                               \
+	 BIT_TXTTIMER_MATCH_NUM_8814B(v))
+
+#define BIT_SHIFT_TXPKT_NUM_MATCH_8814B 24
+#define BIT_MASK_TXPKT_NUM_MATCH_8814B 0xf
+#define BIT_TXPKT_NUM_MATCH_8814B(x)                                           \
+	(((x) & BIT_MASK_TXPKT_NUM_MATCH_8814B)                                \
+	 << BIT_SHIFT_TXPKT_NUM_MATCH_8814B)
+#define BITS_TXPKT_NUM_MATCH_8814B                                             \
+	(BIT_MASK_TXPKT_NUM_MATCH_8814B << BIT_SHIFT_TXPKT_NUM_MATCH_8814B)
+#define BIT_CLEAR_TXPKT_NUM_MATCH_8814B(x) ((x) & (~BITS_TXPKT_NUM_MATCH_8814B))
+#define BIT_GET_TXPKT_NUM_MATCH_8814B(x)                                       \
+	(((x) >> BIT_SHIFT_TXPKT_NUM_MATCH_8814B) &                            \
+	 BIT_MASK_TXPKT_NUM_MATCH_8814B)
+#define BIT_SET_TXPKT_NUM_MATCH_8814B(x, v)                                    \
+	(BIT_CLEAR_TXPKT_NUM_MATCH_8814B(x) | BIT_TXPKT_NUM_MATCH_8814B(v))
+
+#define BIT_SHIFT_RXTTIMER_MATCH_NUM_8814B 20
+#define BIT_MASK_RXTTIMER_MATCH_NUM_8814B 0xf
+#define BIT_RXTTIMER_MATCH_NUM_8814B(x)                                        \
+	(((x) & BIT_MASK_RXTTIMER_MATCH_NUM_8814B)                             \
+	 << BIT_SHIFT_RXTTIMER_MATCH_NUM_8814B)
+#define BITS_RXTTIMER_MATCH_NUM_8814B                                          \
+	(BIT_MASK_RXTTIMER_MATCH_NUM_8814B                                     \
+	 << BIT_SHIFT_RXTTIMER_MATCH_NUM_8814B)
+#define BIT_CLEAR_RXTTIMER_MATCH_NUM_8814B(x)                                  \
+	((x) & (~BITS_RXTTIMER_MATCH_NUM_8814B))
+#define BIT_GET_RXTTIMER_MATCH_NUM_8814B(x)                                    \
+	(((x) >> BIT_SHIFT_RXTTIMER_MATCH_NUM_8814B) &                         \
+	 BIT_MASK_RXTTIMER_MATCH_NUM_8814B)
+#define BIT_SET_RXTTIMER_MATCH_NUM_8814B(x, v)                                 \
+	(BIT_CLEAR_RXTTIMER_MATCH_NUM_8814B(x) |                               \
+	 BIT_RXTTIMER_MATCH_NUM_8814B(v))
+
+#define BIT_SHIFT_RXPKT_NUM_MATCH_8814B 16
+#define BIT_MASK_RXPKT_NUM_MATCH_8814B 0xf
+#define BIT_RXPKT_NUM_MATCH_8814B(x)                                           \
+	(((x) & BIT_MASK_RXPKT_NUM_MATCH_8814B)                                \
+	 << BIT_SHIFT_RXPKT_NUM_MATCH_8814B)
+#define BITS_RXPKT_NUM_MATCH_8814B                                             \
+	(BIT_MASK_RXPKT_NUM_MATCH_8814B << BIT_SHIFT_RXPKT_NUM_MATCH_8814B)
+#define BIT_CLEAR_RXPKT_NUM_MATCH_8814B(x) ((x) & (~BITS_RXPKT_NUM_MATCH_8814B))
+#define BIT_GET_RXPKT_NUM_MATCH_8814B(x)                                       \
+	(((x) >> BIT_SHIFT_RXPKT_NUM_MATCH_8814B) &                            \
+	 BIT_MASK_RXPKT_NUM_MATCH_8814B)
+#define BIT_SET_RXPKT_NUM_MATCH_8814B(x, v)                                    \
+	(BIT_CLEAR_RXPKT_NUM_MATCH_8814B(x) | BIT_RXPKT_NUM_MATCH_8814B(v))
+
+#define BIT_SHIFT_MIGRATE_TIMER_8814B 0
+#define BIT_MASK_MIGRATE_TIMER_8814B 0xffff
+#define BIT_MIGRATE_TIMER_8814B(x)                                             \
+	(((x) & BIT_MASK_MIGRATE_TIMER_8814B) << BIT_SHIFT_MIGRATE_TIMER_8814B)
+#define BITS_MIGRATE_TIMER_8814B                                               \
+	(BIT_MASK_MIGRATE_TIMER_8814B << BIT_SHIFT_MIGRATE_TIMER_8814B)
+#define BIT_CLEAR_MIGRATE_TIMER_8814B(x) ((x) & (~BITS_MIGRATE_TIMER_8814B))
+#define BIT_GET_MIGRATE_TIMER_8814B(x)                                         \
+	(((x) >> BIT_SHIFT_MIGRATE_TIMER_8814B) & BIT_MASK_MIGRATE_TIMER_8814B)
+#define BIT_SET_MIGRATE_TIMER_8814B(x, v)                                      \
+	(BIT_CLEAR_MIGRATE_TIMER_8814B(x) | BIT_MIGRATE_TIMER_8814B(v))
+
+/* 2 REG_P0MGQ_TXBD_DESA_L_8814B */
+
+/* 2 REG_P0MGQ_TXBD_DESA_H_8814B */
+
+/* 2 REG_ACH0_TXBD_DESA_L_8814B */
+
+#define BIT_SHIFT_ACH0_TXBD_DESA_L_8814B 0
+#define BIT_MASK_ACH0_TXBD_DESA_L_8814B 0xffffffffL
+#define BIT_ACH0_TXBD_DESA_L_8814B(x)                                          \
+	(((x) & BIT_MASK_ACH0_TXBD_DESA_L_8814B)                               \
+	 << BIT_SHIFT_ACH0_TXBD_DESA_L_8814B)
+#define BITS_ACH0_TXBD_DESA_L_8814B                                            \
+	(BIT_MASK_ACH0_TXBD_DESA_L_8814B << BIT_SHIFT_ACH0_TXBD_DESA_L_8814B)
+#define BIT_CLEAR_ACH0_TXBD_DESA_L_8814B(x)                                    \
+	((x) & (~BITS_ACH0_TXBD_DESA_L_8814B))
+#define BIT_GET_ACH0_TXBD_DESA_L_8814B(x)                                      \
+	(((x) >> BIT_SHIFT_ACH0_TXBD_DESA_L_8814B) &                           \
+	 BIT_MASK_ACH0_TXBD_DESA_L_8814B)
+#define BIT_SET_ACH0_TXBD_DESA_L_8814B(x, v)                                   \
+	(BIT_CLEAR_ACH0_TXBD_DESA_L_8814B(x) | BIT_ACH0_TXBD_DESA_L_8814B(v))
+
+/* 2 REG_ACH0_TXBD_DESA_H_8814B */
+
+#define BIT_SHIFT_ACH0_TXBD_DESA_H_8814B 0
+#define BIT_MASK_ACH0_TXBD_DESA_H_8814B 0xffffffffL
+#define BIT_ACH0_TXBD_DESA_H_8814B(x)                                          \
+	(((x) & BIT_MASK_ACH0_TXBD_DESA_H_8814B)                               \
+	 << BIT_SHIFT_ACH0_TXBD_DESA_H_8814B)
+#define BITS_ACH0_TXBD_DESA_H_8814B                                            \
+	(BIT_MASK_ACH0_TXBD_DESA_H_8814B << BIT_SHIFT_ACH0_TXBD_DESA_H_8814B)
+#define BIT_CLEAR_ACH0_TXBD_DESA_H_8814B(x)                                    \
+	((x) & (~BITS_ACH0_TXBD_DESA_H_8814B))
+#define BIT_GET_ACH0_TXBD_DESA_H_8814B(x)                                      \
+	(((x) >> BIT_SHIFT_ACH0_TXBD_DESA_H_8814B) &                           \
+	 BIT_MASK_ACH0_TXBD_DESA_H_8814B)
+#define BIT_SET_ACH0_TXBD_DESA_H_8814B(x, v)                                   \
+	(BIT_CLEAR_ACH0_TXBD_DESA_H_8814B(x) | BIT_ACH0_TXBD_DESA_H_8814B(v))
+
+/* 2 REG_ACH1_TXBD_DESA_L_8814B */
+
+#define BIT_SHIFT_ACH1_TXBD_DESA_L_8814B 0
+#define BIT_MASK_ACH1_TXBD_DESA_L_8814B 0xffffffffL
+#define BIT_ACH1_TXBD_DESA_L_8814B(x)                                          \
+	(((x) & BIT_MASK_ACH1_TXBD_DESA_L_8814B)                               \
+	 << BIT_SHIFT_ACH1_TXBD_DESA_L_8814B)
+#define BITS_ACH1_TXBD_DESA_L_8814B                                            \
+	(BIT_MASK_ACH1_TXBD_DESA_L_8814B << BIT_SHIFT_ACH1_TXBD_DESA_L_8814B)
+#define BIT_CLEAR_ACH1_TXBD_DESA_L_8814B(x)                                    \
+	((x) & (~BITS_ACH1_TXBD_DESA_L_8814B))
+#define BIT_GET_ACH1_TXBD_DESA_L_8814B(x)                                      \
+	(((x) >> BIT_SHIFT_ACH1_TXBD_DESA_L_8814B) &                           \
+	 BIT_MASK_ACH1_TXBD_DESA_L_8814B)
+#define BIT_SET_ACH1_TXBD_DESA_L_8814B(x, v)                                   \
+	(BIT_CLEAR_ACH1_TXBD_DESA_L_8814B(x) | BIT_ACH1_TXBD_DESA_L_8814B(v))
+
+/* 2 REG_ACH1_TXBD_DESA_H_8814B */
+
+#define BIT_SHIFT_ACH1_TXBD_DESA_H_8814B 0
+#define BIT_MASK_ACH1_TXBD_DESA_H_8814B 0xffffffffL
+#define BIT_ACH1_TXBD_DESA_H_8814B(x)                                          \
+	(((x) & BIT_MASK_ACH1_TXBD_DESA_H_8814B)                               \
+	 << BIT_SHIFT_ACH1_TXBD_DESA_H_8814B)
+#define BITS_ACH1_TXBD_DESA_H_8814B                                            \
+	(BIT_MASK_ACH1_TXBD_DESA_H_8814B << BIT_SHIFT_ACH1_TXBD_DESA_H_8814B)
+#define BIT_CLEAR_ACH1_TXBD_DESA_H_8814B(x)                                    \
+	((x) & (~BITS_ACH1_TXBD_DESA_H_8814B))
+#define BIT_GET_ACH1_TXBD_DESA_H_8814B(x)                                      \
+	(((x) >> BIT_SHIFT_ACH1_TXBD_DESA_H_8814B) &                           \
+	 BIT_MASK_ACH1_TXBD_DESA_H_8814B)
+#define BIT_SET_ACH1_TXBD_DESA_H_8814B(x, v)                                   \
+	(BIT_CLEAR_ACH1_TXBD_DESA_H_8814B(x) | BIT_ACH1_TXBD_DESA_H_8814B(v))
+
+/* 2 REG_ACH2_TXBD_DESA_L_8814B */
+
+#define BIT_SHIFT_ACH2_TXBD_DESA_L_8814B 0
+#define BIT_MASK_ACH2_TXBD_DESA_L_8814B 0xffffffffL
+#define BIT_ACH2_TXBD_DESA_L_8814B(x)                                          \
+	(((x) & BIT_MASK_ACH2_TXBD_DESA_L_8814B)                               \
+	 << BIT_SHIFT_ACH2_TXBD_DESA_L_8814B)
+#define BITS_ACH2_TXBD_DESA_L_8814B                                            \
+	(BIT_MASK_ACH2_TXBD_DESA_L_8814B << BIT_SHIFT_ACH2_TXBD_DESA_L_8814B)
+#define BIT_CLEAR_ACH2_TXBD_DESA_L_8814B(x)                                    \
+	((x) & (~BITS_ACH2_TXBD_DESA_L_8814B))
+#define BIT_GET_ACH2_TXBD_DESA_L_8814B(x)                                      \
+	(((x) >> BIT_SHIFT_ACH2_TXBD_DESA_L_8814B) &                           \
+	 BIT_MASK_ACH2_TXBD_DESA_L_8814B)
+#define BIT_SET_ACH2_TXBD_DESA_L_8814B(x, v)                                   \
+	(BIT_CLEAR_ACH2_TXBD_DESA_L_8814B(x) | BIT_ACH2_TXBD_DESA_L_8814B(v))
+
+/* 2 REG_ACH2_TXBD_DESA_H_8814B */
+
+#define BIT_SHIFT_ACH2_TXBD_DESA_H_8814B 0
+#define BIT_MASK_ACH2_TXBD_DESA_H_8814B 0xffffffffL
+#define BIT_ACH2_TXBD_DESA_H_8814B(x)                                          \
+	(((x) & BIT_MASK_ACH2_TXBD_DESA_H_8814B)                               \
+	 << BIT_SHIFT_ACH2_TXBD_DESA_H_8814B)
+#define BITS_ACH2_TXBD_DESA_H_8814B                                            \
+	(BIT_MASK_ACH2_TXBD_DESA_H_8814B << BIT_SHIFT_ACH2_TXBD_DESA_H_8814B)
+#define BIT_CLEAR_ACH2_TXBD_DESA_H_8814B(x)                                    \
+	((x) & (~BITS_ACH2_TXBD_DESA_H_8814B))
+#define BIT_GET_ACH2_TXBD_DESA_H_8814B(x)                                      \
+	(((x) >> BIT_SHIFT_ACH2_TXBD_DESA_H_8814B) &                           \
+	 BIT_MASK_ACH2_TXBD_DESA_H_8814B)
+#define BIT_SET_ACH2_TXBD_DESA_H_8814B(x, v)                                   \
+	(BIT_CLEAR_ACH2_TXBD_DESA_H_8814B(x) | BIT_ACH2_TXBD_DESA_H_8814B(v))
+
+/* 2 REG_ACH3_TXBD_DESA_L_8814B */
+
+#define BIT_SHIFT_ACH3_TXBD_DESA_L_8814B 0
+#define BIT_MASK_ACH3_TXBD_DESA_L_8814B 0xffffffffL
+#define BIT_ACH3_TXBD_DESA_L_8814B(x)                                          \
+	(((x) & BIT_MASK_ACH3_TXBD_DESA_L_8814B)                               \
+	 << BIT_SHIFT_ACH3_TXBD_DESA_L_8814B)
+#define BITS_ACH3_TXBD_DESA_L_8814B                                            \
+	(BIT_MASK_ACH3_TXBD_DESA_L_8814B << BIT_SHIFT_ACH3_TXBD_DESA_L_8814B)
+#define BIT_CLEAR_ACH3_TXBD_DESA_L_8814B(x)                                    \
+	((x) & (~BITS_ACH3_TXBD_DESA_L_8814B))
+#define BIT_GET_ACH3_TXBD_DESA_L_8814B(x)                                      \
+	(((x) >> BIT_SHIFT_ACH3_TXBD_DESA_L_8814B) &                           \
+	 BIT_MASK_ACH3_TXBD_DESA_L_8814B)
+#define BIT_SET_ACH3_TXBD_DESA_L_8814B(x, v)                                   \
+	(BIT_CLEAR_ACH3_TXBD_DESA_L_8814B(x) | BIT_ACH3_TXBD_DESA_L_8814B(v))
+
+/* 2 REG_ACH3_TXBD_DESA_H_8814B */
+
+#define BIT_SHIFT_ACH3_TXBD_DESA_H_8814B 0
+#define BIT_MASK_ACH3_TXBD_DESA_H_8814B 0xffffffffL
+#define BIT_ACH3_TXBD_DESA_H_8814B(x)                                          \
+	(((x) & BIT_MASK_ACH3_TXBD_DESA_H_8814B)                               \
+	 << BIT_SHIFT_ACH3_TXBD_DESA_H_8814B)
+#define BITS_ACH3_TXBD_DESA_H_8814B                                            \
+	(BIT_MASK_ACH3_TXBD_DESA_H_8814B << BIT_SHIFT_ACH3_TXBD_DESA_H_8814B)
+#define BIT_CLEAR_ACH3_TXBD_DESA_H_8814B(x)                                    \
+	((x) & (~BITS_ACH3_TXBD_DESA_H_8814B))
+#define BIT_GET_ACH3_TXBD_DESA_H_8814B(x)                                      \
+	(((x) >> BIT_SHIFT_ACH3_TXBD_DESA_H_8814B) &                           \
+	 BIT_MASK_ACH3_TXBD_DESA_H_8814B)
+#define BIT_SET_ACH3_TXBD_DESA_H_8814B(x, v)                                   \
+	(BIT_CLEAR_ACH3_TXBD_DESA_H_8814B(x) | BIT_ACH3_TXBD_DESA_H_8814B(v))
+
+/* 2 REG_P0RXQ_RXBD_DESA_L_8814B */
+
+#define BIT_SHIFT_P0RXQ_RXBD_DESA_L_8814B 0
+#define BIT_MASK_P0RXQ_RXBD_DESA_L_8814B 0xffffffffL
+#define BIT_P0RXQ_RXBD_DESA_L_8814B(x)                                         \
+	(((x) & BIT_MASK_P0RXQ_RXBD_DESA_L_8814B)                              \
+	 << BIT_SHIFT_P0RXQ_RXBD_DESA_L_8814B)
+#define BITS_P0RXQ_RXBD_DESA_L_8814B                                           \
+	(BIT_MASK_P0RXQ_RXBD_DESA_L_8814B << BIT_SHIFT_P0RXQ_RXBD_DESA_L_8814B)
+#define BIT_CLEAR_P0RXQ_RXBD_DESA_L_8814B(x)                                   \
+	((x) & (~BITS_P0RXQ_RXBD_DESA_L_8814B))
+#define BIT_GET_P0RXQ_RXBD_DESA_L_8814B(x)                                     \
+	(((x) >> BIT_SHIFT_P0RXQ_RXBD_DESA_L_8814B) &                          \
+	 BIT_MASK_P0RXQ_RXBD_DESA_L_8814B)
+#define BIT_SET_P0RXQ_RXBD_DESA_L_8814B(x, v)                                  \
+	(BIT_CLEAR_P0RXQ_RXBD_DESA_L_8814B(x) | BIT_P0RXQ_RXBD_DESA_L_8814B(v))
+
+/* 2 REG_P0RXQ_RXBD_DESA_H_8814B */
+
+#define BIT_SHIFT_P0RXQ_RXBD_DESA_H_8814B 0
+#define BIT_MASK_P0RXQ_RXBD_DESA_H_8814B 0xffffffffL
+#define BIT_P0RXQ_RXBD_DESA_H_8814B(x)                                         \
+	(((x) & BIT_MASK_P0RXQ_RXBD_DESA_H_8814B)                              \
+	 << BIT_SHIFT_P0RXQ_RXBD_DESA_H_8814B)
+#define BITS_P0RXQ_RXBD_DESA_H_8814B                                           \
+	(BIT_MASK_P0RXQ_RXBD_DESA_H_8814B << BIT_SHIFT_P0RXQ_RXBD_DESA_H_8814B)
+#define BIT_CLEAR_P0RXQ_RXBD_DESA_H_8814B(x)                                   \
+	((x) & (~BITS_P0RXQ_RXBD_DESA_H_8814B))
+#define BIT_GET_P0RXQ_RXBD_DESA_H_8814B(x)                                     \
+	(((x) >> BIT_SHIFT_P0RXQ_RXBD_DESA_H_8814B) &                          \
+	 BIT_MASK_P0RXQ_RXBD_DESA_H_8814B)
+#define BIT_SET_P0RXQ_RXBD_DESA_H_8814B(x, v)                                  \
+	(BIT_CLEAR_P0RXQ_RXBD_DESA_H_8814B(x) | BIT_P0RXQ_RXBD_DESA_H_8814B(v))
+
+/* 2 REG_P0BCNQ_TXBD_DESA_L_8814B */
+
+#define BIT_SHIFT_P0BCNQ_TXBD_DESA_L_8814B 0
+#define BIT_MASK_P0BCNQ_TXBD_DESA_L_8814B 0xffffffffL
+#define BIT_P0BCNQ_TXBD_DESA_L_8814B(x)                                        \
+	(((x) & BIT_MASK_P0BCNQ_TXBD_DESA_L_8814B)                             \
+	 << BIT_SHIFT_P0BCNQ_TXBD_DESA_L_8814B)
+#define BITS_P0BCNQ_TXBD_DESA_L_8814B                                          \
+	(BIT_MASK_P0BCNQ_TXBD_DESA_L_8814B                                     \
+	 << BIT_SHIFT_P0BCNQ_TXBD_DESA_L_8814B)
+#define BIT_CLEAR_P0BCNQ_TXBD_DESA_L_8814B(x)                                  \
+	((x) & (~BITS_P0BCNQ_TXBD_DESA_L_8814B))
+#define BIT_GET_P0BCNQ_TXBD_DESA_L_8814B(x)                                    \
+	(((x) >> BIT_SHIFT_P0BCNQ_TXBD_DESA_L_8814B) &                         \
+	 BIT_MASK_P0BCNQ_TXBD_DESA_L_8814B)
+#define BIT_SET_P0BCNQ_TXBD_DESA_L_8814B(x, v)                                 \
+	(BIT_CLEAR_P0BCNQ_TXBD_DESA_L_8814B(x) |                               \
+	 BIT_P0BCNQ_TXBD_DESA_L_8814B(v))
+
+/* 2 REG_P0BCNQ_TXBD_DESA_H_8814B */
+
+#define BIT_SHIFT_P0BCNQ_TXBD_DESA_H_8814B 0
+#define BIT_MASK_P0BCNQ_TXBD_DESA_H_8814B 0xffffffffL
+#define BIT_P0BCNQ_TXBD_DESA_H_8814B(x)                                        \
+	(((x) & BIT_MASK_P0BCNQ_TXBD_DESA_H_8814B)                             \
+	 << BIT_SHIFT_P0BCNQ_TXBD_DESA_H_8814B)
+#define BITS_P0BCNQ_TXBD_DESA_H_8814B                                          \
+	(BIT_MASK_P0BCNQ_TXBD_DESA_H_8814B                                     \
+	 << BIT_SHIFT_P0BCNQ_TXBD_DESA_H_8814B)
+#define BIT_CLEAR_P0BCNQ_TXBD_DESA_H_8814B(x)                                  \
+	((x) & (~BITS_P0BCNQ_TXBD_DESA_H_8814B))
+#define BIT_GET_P0BCNQ_TXBD_DESA_H_8814B(x)                                    \
+	(((x) >> BIT_SHIFT_P0BCNQ_TXBD_DESA_H_8814B) &                         \
+	 BIT_MASK_P0BCNQ_TXBD_DESA_H_8814B)
+#define BIT_SET_P0BCNQ_TXBD_DESA_H_8814B(x, v)                                 \
+	(BIT_CLEAR_P0BCNQ_TXBD_DESA_H_8814B(x) |                               \
+	 BIT_P0BCNQ_TXBD_DESA_H_8814B(v))
+
+/* 2 REG_FWCMDQ_TXBD_DESA_L_8814B */
+
+#define BIT_SHIFT_FWCMDQ_TXBD_DESA_L_8814B 0
+#define BIT_MASK_FWCMDQ_TXBD_DESA_L_8814B 0xffffffffL
+#define BIT_FWCMDQ_TXBD_DESA_L_8814B(x)                                        \
+	(((x) & BIT_MASK_FWCMDQ_TXBD_DESA_L_8814B)                             \
+	 << BIT_SHIFT_FWCMDQ_TXBD_DESA_L_8814B)
+#define BITS_FWCMDQ_TXBD_DESA_L_8814B                                          \
+	(BIT_MASK_FWCMDQ_TXBD_DESA_L_8814B                                     \
+	 << BIT_SHIFT_FWCMDQ_TXBD_DESA_L_8814B)
+#define BIT_CLEAR_FWCMDQ_TXBD_DESA_L_8814B(x)                                  \
+	((x) & (~BITS_FWCMDQ_TXBD_DESA_L_8814B))
+#define BIT_GET_FWCMDQ_TXBD_DESA_L_8814B(x)                                    \
+	(((x) >> BIT_SHIFT_FWCMDQ_TXBD_DESA_L_8814B) &                         \
+	 BIT_MASK_FWCMDQ_TXBD_DESA_L_8814B)
+#define BIT_SET_FWCMDQ_TXBD_DESA_L_8814B(x, v)                                 \
+	(BIT_CLEAR_FWCMDQ_TXBD_DESA_L_8814B(x) |                               \
+	 BIT_FWCMDQ_TXBD_DESA_L_8814B(v))
+
+/* 2 REG_FWCMDQ_TXBD_DESA_H_8814B */
+
+#define BIT_SHIFT_FWCMDQ_TXBD_DESA_H_8814B 0
+#define BIT_MASK_FWCMDQ_TXBD_DESA_H_8814B 0xffffffffL
+#define BIT_FWCMDQ_TXBD_DESA_H_8814B(x)                                        \
+	(((x) & BIT_MASK_FWCMDQ_TXBD_DESA_H_8814B)                             \
+	 << BIT_SHIFT_FWCMDQ_TXBD_DESA_H_8814B)
+#define BITS_FWCMDQ_TXBD_DESA_H_8814B                                          \
+	(BIT_MASK_FWCMDQ_TXBD_DESA_H_8814B                                     \
+	 << BIT_SHIFT_FWCMDQ_TXBD_DESA_H_8814B)
+#define BIT_CLEAR_FWCMDQ_TXBD_DESA_H_8814B(x)                                  \
+	((x) & (~BITS_FWCMDQ_TXBD_DESA_H_8814B))
+#define BIT_GET_FWCMDQ_TXBD_DESA_H_8814B(x)                                    \
+	(((x) >> BIT_SHIFT_FWCMDQ_TXBD_DESA_H_8814B) &                         \
+	 BIT_MASK_FWCMDQ_TXBD_DESA_H_8814B)
+#define BIT_SET_FWCMDQ_TXBD_DESA_H_8814B(x, v)                                 \
+	(BIT_CLEAR_FWCMDQ_TXBD_DESA_H_8814B(x) |                               \
+	 BIT_FWCMDQ_TXBD_DESA_H_8814B(v))
+
+/* 2 REG_PCIE_HRPWM1_HCPWM1_DCPU_8814B */
+
+#define BIT_SHIFT_PCIE_HCPWM1_DCPU_8814B 16
+#define BIT_MASK_PCIE_HCPWM1_DCPU_8814B 0xff
+#define BIT_PCIE_HCPWM1_DCPU_8814B(x)                                          \
+	(((x) & BIT_MASK_PCIE_HCPWM1_DCPU_8814B)                               \
+	 << BIT_SHIFT_PCIE_HCPWM1_DCPU_8814B)
+#define BITS_PCIE_HCPWM1_DCPU_8814B                                            \
+	(BIT_MASK_PCIE_HCPWM1_DCPU_8814B << BIT_SHIFT_PCIE_HCPWM1_DCPU_8814B)
+#define BIT_CLEAR_PCIE_HCPWM1_DCPU_8814B(x)                                    \
+	((x) & (~BITS_PCIE_HCPWM1_DCPU_8814B))
+#define BIT_GET_PCIE_HCPWM1_DCPU_8814B(x)                                      \
+	(((x) >> BIT_SHIFT_PCIE_HCPWM1_DCPU_8814B) &                           \
+	 BIT_MASK_PCIE_HCPWM1_DCPU_8814B)
+#define BIT_SET_PCIE_HCPWM1_DCPU_8814B(x, v)                                   \
+	(BIT_CLEAR_PCIE_HCPWM1_DCPU_8814B(x) | BIT_PCIE_HCPWM1_DCPU_8814B(v))
+
+#define BIT_SHIFT_PCIE_HRPWM1_DCPU_8814B 8
+#define BIT_MASK_PCIE_HRPWM1_DCPU_8814B 0xff
+#define BIT_PCIE_HRPWM1_DCPU_8814B(x)                                          \
+	(((x) & BIT_MASK_PCIE_HRPWM1_DCPU_8814B)                               \
+	 << BIT_SHIFT_PCIE_HRPWM1_DCPU_8814B)
+#define BITS_PCIE_HRPWM1_DCPU_8814B                                            \
+	(BIT_MASK_PCIE_HRPWM1_DCPU_8814B << BIT_SHIFT_PCIE_HRPWM1_DCPU_8814B)
+#define BIT_CLEAR_PCIE_HRPWM1_DCPU_8814B(x)                                    \
+	((x) & (~BITS_PCIE_HRPWM1_DCPU_8814B))
+#define BIT_GET_PCIE_HRPWM1_DCPU_8814B(x)                                      \
+	(((x) >> BIT_SHIFT_PCIE_HRPWM1_DCPU_8814B) &                           \
+	 BIT_MASK_PCIE_HRPWM1_DCPU_8814B)
+#define BIT_SET_PCIE_HRPWM1_DCPU_8814B(x, v)                                   \
+	(BIT_CLEAR_PCIE_HRPWM1_DCPU_8814B(x) | BIT_PCIE_HRPWM1_DCPU_8814B(v))
+
+/* 2 REG_P0_MPRT_BCNQ_TXBD_DESA_L_8814B */
+
+#define BIT_SHIFT_P0_MPRT_BCNQ_TXBD_DESA_L_8814B 0
+#define BIT_MASK_P0_MPRT_BCNQ_TXBD_DESA_L_8814B 0xffffffffL
+#define BIT_P0_MPRT_BCNQ_TXBD_DESA_L_8814B(x)                                  \
+	(((x) & BIT_MASK_P0_MPRT_BCNQ_TXBD_DESA_L_8814B)                       \
+	 << BIT_SHIFT_P0_MPRT_BCNQ_TXBD_DESA_L_8814B)
+#define BITS_P0_MPRT_BCNQ_TXBD_DESA_L_8814B                                    \
+	(BIT_MASK_P0_MPRT_BCNQ_TXBD_DESA_L_8814B                               \
+	 << BIT_SHIFT_P0_MPRT_BCNQ_TXBD_DESA_L_8814B)
+#define BIT_CLEAR_P0_MPRT_BCNQ_TXBD_DESA_L_8814B(x)                            \
+	((x) & (~BITS_P0_MPRT_BCNQ_TXBD_DESA_L_8814B))
+#define BIT_GET_P0_MPRT_BCNQ_TXBD_DESA_L_8814B(x)                              \
+	(((x) >> BIT_SHIFT_P0_MPRT_BCNQ_TXBD_DESA_L_8814B) &                   \
+	 BIT_MASK_P0_MPRT_BCNQ_TXBD_DESA_L_8814B)
+#define BIT_SET_P0_MPRT_BCNQ_TXBD_DESA_L_8814B(x, v)                           \
+	(BIT_CLEAR_P0_MPRT_BCNQ_TXBD_DESA_L_8814B(x) |                         \
+	 BIT_P0_MPRT_BCNQ_TXBD_DESA_L_8814B(v))
+
+/* 2 REG_P0_MPRT_BCNQ_TXBD_DESA_H_8814B */
+
+#define BIT_SHIFT_P0_MPRT_BCNQ_TXBD_DESA_H_8814B 0
+#define BIT_MASK_P0_MPRT_BCNQ_TXBD_DESA_H_8814B 0xffffffffL
+#define BIT_P0_MPRT_BCNQ_TXBD_DESA_H_8814B(x)                                  \
+	(((x) & BIT_MASK_P0_MPRT_BCNQ_TXBD_DESA_H_8814B)                       \
+	 << BIT_SHIFT_P0_MPRT_BCNQ_TXBD_DESA_H_8814B)
+#define BITS_P0_MPRT_BCNQ_TXBD_DESA_H_8814B                                    \
+	(BIT_MASK_P0_MPRT_BCNQ_TXBD_DESA_H_8814B                               \
+	 << BIT_SHIFT_P0_MPRT_BCNQ_TXBD_DESA_H_8814B)
+#define BIT_CLEAR_P0_MPRT_BCNQ_TXBD_DESA_H_8814B(x)                            \
+	((x) & (~BITS_P0_MPRT_BCNQ_TXBD_DESA_H_8814B))
+#define BIT_GET_P0_MPRT_BCNQ_TXBD_DESA_H_8814B(x)                              \
+	(((x) >> BIT_SHIFT_P0_MPRT_BCNQ_TXBD_DESA_H_8814B) &                   \
+	 BIT_MASK_P0_MPRT_BCNQ_TXBD_DESA_H_8814B)
+#define BIT_SET_P0_MPRT_BCNQ_TXBD_DESA_H_8814B(x, v)                           \
+	(BIT_CLEAR_P0_MPRT_BCNQ_TXBD_DESA_H_8814B(x) |                         \
+	 BIT_P0_MPRT_BCNQ_TXBD_DESA_H_8814B(v))
+
+/* 2 REG_P0_MPRT_BCNQ_TXRXBD_NUM_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+#define BIT_SHIFT_P0_MPRT_BCNQ_DESC_MODE_8814B 13
+#define BIT_MASK_P0_MPRT_BCNQ_DESC_MODE_8814B 0x3
+#define BIT_P0_MPRT_BCNQ_DESC_MODE_8814B(x)                                    \
+	(((x) & BIT_MASK_P0_MPRT_BCNQ_DESC_MODE_8814B)                         \
+	 << BIT_SHIFT_P0_MPRT_BCNQ_DESC_MODE_8814B)
+#define BITS_P0_MPRT_BCNQ_DESC_MODE_8814B                                      \
+	(BIT_MASK_P0_MPRT_BCNQ_DESC_MODE_8814B                                 \
+	 << BIT_SHIFT_P0_MPRT_BCNQ_DESC_MODE_8814B)
+#define BIT_CLEAR_P0_MPRT_BCNQ_DESC_MODE_8814B(x)                              \
+	((x) & (~BITS_P0_MPRT_BCNQ_DESC_MODE_8814B))
+#define BIT_GET_P0_MPRT_BCNQ_DESC_MODE_8814B(x)                                \
+	(((x) >> BIT_SHIFT_P0_MPRT_BCNQ_DESC_MODE_8814B) &                     \
+	 BIT_MASK_P0_MPRT_BCNQ_DESC_MODE_8814B)
+#define BIT_SET_P0_MPRT_BCNQ_DESC_MODE_8814B(x, v)                             \
+	(BIT_CLEAR_P0_MPRT_BCNQ_DESC_MODE_8814B(x) |                           \
+	 BIT_P0_MPRT_BCNQ_DESC_MODE_8814B(v))
+
+#define BIT_PCIE_P0MPRT_BCNQ4_FLAG_8814B BIT(11)
+#define BIT_PCIE_P0MPRT_BCNQ3_FLAG_8814B BIT(10)
+#define BIT_PCIE_P0MPRT_BCNQ2_FLAG_8814B BIT(9)
+#define BIT_PCIE_P0MPRT_BCNQ1_FLAG_8814B BIT(8)
+#define BIT_EPHY_CAL_DONE_8814B BIT(1)
+#define BIT_RESET_APHY_8814B BIT(0)
+
+/* 2 REG_BD_RWPTR_CLR2_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+#define BIT_CLR_ACH7_HW_IDX_8814B BIT(21)
+#define BIT_CLR_ACH6_HW_IDX_8814B BIT(20)
+#define BIT_CLR_ACH5_HW_IDX_8814B BIT(19)
+#define BIT_CLR_ACH4_HW_IDX_8814B BIT(18)
+
+/* 2 REG_NOT_VALID_8814B */
+#define BIT_CLR_ACH7_HOST_IDX_8814B BIT(5)
+#define BIT_CLR_ACH6_HOST_IDX_8814B BIT(4)
+#define BIT_CLR_ACH5_HOST_IDX_8814B BIT(3)
+#define BIT_CLR_ACH4_HOST_IDX_8814B BIT(2)
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_BD_RWPTR_CLR3_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+#define BIT_CLR_P0HI15Q_HW_IDX_8814B BIT(29)
+#define BIT_CLR_P0HI14Q_HW_IDX_8814B BIT(28)
+#define BIT_CLR_P0HI13Q_HW_IDX_8814B BIT(27)
+#define BIT_CLR_P0HI12Q_HW_IDX_8814B BIT(26)
+#define BIT_CLR_P0HI11Q_HW_IDX_8814B BIT(25)
+#define BIT_CLR_P0HI10Q_HW_IDX_8814B BIT(24)
+#define BIT_CLR_P0HI9Q_HW_IDX_8814B BIT(23)
+#define BIT_CLR_P0HI8Q_HW_IDX_8814B BIT(22)
+#define BIT_CLR_ACH13_HW_IDX_8814B BIT(21)
+#define BIT_CLR_ACH12_HW_IDX_8814B BIT(20)
+#define BIT_CLR_ACH11_HW_IDX_8814B BIT(19)
+#define BIT_CLR_ACH10_HW_IDX_8814B BIT(18)
+#define BIT_CLR_ACH9_HW_IDX_8814B BIT(17)
+#define BIT_CLR_ACH8_HW_IDX_8814B BIT(16)
+
+/* 2 REG_NOT_VALID_8814B */
+#define BIT_CLR_P0HI15Q_HOST_IDX_8814B BIT(13)
+#define BIT_CLR_P0HI14Q_HOST_IDX_8814B BIT(12)
+#define BIT_CLR_P0HI13Q_HOST_IDX_8814B BIT(11)
+#define BIT_CLR_P0HI12Q_HOST_IDX_8814B BIT(10)
+#define BIT_CLR_P0HI11Q_HOST_IDX_8814B BIT(9)
+#define BIT_CLR_P0HI10Q_HOST_IDX_8814B BIT(8)
+#define BIT_CLR_P0HI9Q_HOST_IDX_8814B BIT(7)
+#define BIT_CLR_P0HI8Q_HOST_IDX_8814B BIT(6)
+#define BIT_CLR_ACH13_HOST_IDX_8814B BIT(5)
+#define BIT_CLR_ACH12_HOST_IDX_8814B BIT(4)
+#define BIT_CLR_ACH11_HOST_IDX_8814B BIT(3)
+#define BIT_CLR_ACH10_HOST_IDX_8814B BIT(2)
+#define BIT_CLR_ACH9_HOST_IDX_8814B BIT(1)
+#define BIT_CLR_ACH8_HOST_IDX_8814B BIT(0)
+
+/* 2 REG_P0MGQ_RXQ_TXRXBD_NUM_8814B */
+#define BIT_SYS_32_64_V1_8814B BIT(31)
+
+#define BIT_SHIFT_P0BCNQ_DESC_MODE_8814B 29
+#define BIT_MASK_P0BCNQ_DESC_MODE_8814B 0x3
+#define BIT_P0BCNQ_DESC_MODE_8814B(x)                                          \
+	(((x) & BIT_MASK_P0BCNQ_DESC_MODE_8814B)                               \
+	 << BIT_SHIFT_P0BCNQ_DESC_MODE_8814B)
+#define BITS_P0BCNQ_DESC_MODE_8814B                                            \
+	(BIT_MASK_P0BCNQ_DESC_MODE_8814B << BIT_SHIFT_P0BCNQ_DESC_MODE_8814B)
+#define BIT_CLEAR_P0BCNQ_DESC_MODE_8814B(x)                                    \
+	((x) & (~BITS_P0BCNQ_DESC_MODE_8814B))
+#define BIT_GET_P0BCNQ_DESC_MODE_8814B(x)                                      \
+	(((x) >> BIT_SHIFT_P0BCNQ_DESC_MODE_8814B) &                           \
+	 BIT_MASK_P0BCNQ_DESC_MODE_8814B)
+#define BIT_SET_P0BCNQ_DESC_MODE_8814B(x, v)                                   \
+	(BIT_CLEAR_P0BCNQ_DESC_MODE_8814B(x) | BIT_P0BCNQ_DESC_MODE_8814B(v))
+
+#define BIT_PCIE_P0BCNQ_FLAG_8814B BIT(28)
+
+#define BIT_SHIFT_P0RXQ_DESC_NUM_8814B 16
+#define BIT_MASK_P0RXQ_DESC_NUM_8814B 0xfff
+#define BIT_P0RXQ_DESC_NUM_8814B(x)                                            \
+	(((x) & BIT_MASK_P0RXQ_DESC_NUM_8814B)                                 \
+	 << BIT_SHIFT_P0RXQ_DESC_NUM_8814B)
+#define BITS_P0RXQ_DESC_NUM_8814B                                              \
+	(BIT_MASK_P0RXQ_DESC_NUM_8814B << BIT_SHIFT_P0RXQ_DESC_NUM_8814B)
+#define BIT_CLEAR_P0RXQ_DESC_NUM_8814B(x) ((x) & (~BITS_P0RXQ_DESC_NUM_8814B))
+#define BIT_GET_P0RXQ_DESC_NUM_8814B(x)                                        \
+	(((x) >> BIT_SHIFT_P0RXQ_DESC_NUM_8814B) &                             \
+	 BIT_MASK_P0RXQ_DESC_NUM_8814B)
+#define BIT_SET_P0RXQ_DESC_NUM_8814B(x, v)                                     \
+	(BIT_CLEAR_P0RXQ_DESC_NUM_8814B(x) | BIT_P0RXQ_DESC_NUM_8814B(v))
+
+#define BIT_PCIE_P0MGQ_FLAG_8814B BIT(14)
+
+#define BIT_SHIFT_P0MGQ_DESC_MODE_8814B 12
+#define BIT_MASK_P0MGQ_DESC_MODE_8814B 0x3
+#define BIT_P0MGQ_DESC_MODE_8814B(x)                                           \
+	(((x) & BIT_MASK_P0MGQ_DESC_MODE_8814B)                                \
+	 << BIT_SHIFT_P0MGQ_DESC_MODE_8814B)
+#define BITS_P0MGQ_DESC_MODE_8814B                                             \
+	(BIT_MASK_P0MGQ_DESC_MODE_8814B << BIT_SHIFT_P0MGQ_DESC_MODE_8814B)
+#define BIT_CLEAR_P0MGQ_DESC_MODE_8814B(x) ((x) & (~BITS_P0MGQ_DESC_MODE_8814B))
+#define BIT_GET_P0MGQ_DESC_MODE_8814B(x)                                       \
+	(((x) >> BIT_SHIFT_P0MGQ_DESC_MODE_8814B) &                            \
+	 BIT_MASK_P0MGQ_DESC_MODE_8814B)
+#define BIT_SET_P0MGQ_DESC_MODE_8814B(x, v)                                    \
+	(BIT_CLEAR_P0MGQ_DESC_MODE_8814B(x) | BIT_P0MGQ_DESC_MODE_8814B(v))
+
+#define BIT_SHIFT_P0MGQ_DESC_NUM_8814B 0
+#define BIT_MASK_P0MGQ_DESC_NUM_8814B 0xfff
+#define BIT_P0MGQ_DESC_NUM_8814B(x)                                            \
+	(((x) & BIT_MASK_P0MGQ_DESC_NUM_8814B)                                 \
+	 << BIT_SHIFT_P0MGQ_DESC_NUM_8814B)
+#define BITS_P0MGQ_DESC_NUM_8814B                                              \
+	(BIT_MASK_P0MGQ_DESC_NUM_8814B << BIT_SHIFT_P0MGQ_DESC_NUM_8814B)
+#define BIT_CLEAR_P0MGQ_DESC_NUM_8814B(x) ((x) & (~BITS_P0MGQ_DESC_NUM_8814B))
+#define BIT_GET_P0MGQ_DESC_NUM_8814B(x)                                        \
+	(((x) >> BIT_SHIFT_P0MGQ_DESC_NUM_8814B) &                             \
+	 BIT_MASK_P0MGQ_DESC_NUM_8814B)
+#define BIT_SET_P0MGQ_DESC_NUM_8814B(x, v)                                     \
+	(BIT_CLEAR_P0MGQ_DESC_NUM_8814B(x) | BIT_P0MGQ_DESC_NUM_8814B(v))
+
+/* 2 REG_CHNL_DMA_CFG_8814B */
+#define BIT_TXHCI_EN_8814B BIT(26)
+#define BIT_TXHCI_IDLE_8814B BIT(25)
+#define BIT_DMA_PRI_EN_8814B BIT(24)
+
+/* 2 REG_FWCMDQ_TXBD_NUM_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+#define BIT_PCIE_FWCMDQ_FLAG_8814B BIT(14)
+
+#define BIT_SHIFT_FWCMDQ_DESC_MODE_8814B 12
+#define BIT_MASK_FWCMDQ_DESC_MODE_8814B 0x3
+#define BIT_FWCMDQ_DESC_MODE_8814B(x)                                          \
+	(((x) & BIT_MASK_FWCMDQ_DESC_MODE_8814B)                               \
+	 << BIT_SHIFT_FWCMDQ_DESC_MODE_8814B)
+#define BITS_FWCMDQ_DESC_MODE_8814B                                            \
+	(BIT_MASK_FWCMDQ_DESC_MODE_8814B << BIT_SHIFT_FWCMDQ_DESC_MODE_8814B)
+#define BIT_CLEAR_FWCMDQ_DESC_MODE_8814B(x)                                    \
+	((x) & (~BITS_FWCMDQ_DESC_MODE_8814B))
+#define BIT_GET_FWCMDQ_DESC_MODE_8814B(x)                                      \
+	(((x) >> BIT_SHIFT_FWCMDQ_DESC_MODE_8814B) &                           \
+	 BIT_MASK_FWCMDQ_DESC_MODE_8814B)
+#define BIT_SET_FWCMDQ_DESC_MODE_8814B(x, v)                                   \
+	(BIT_CLEAR_FWCMDQ_DESC_MODE_8814B(x) | BIT_FWCMDQ_DESC_MODE_8814B(v))
+
+#define BIT_SHIFT_FWCMDQ_DESC_NUM_8814B 0
+#define BIT_MASK_FWCMDQ_DESC_NUM_8814B 0xfff
+#define BIT_FWCMDQ_DESC_NUM_8814B(x)                                           \
+	(((x) & BIT_MASK_FWCMDQ_DESC_NUM_8814B)                                \
+	 << BIT_SHIFT_FWCMDQ_DESC_NUM_8814B)
+#define BITS_FWCMDQ_DESC_NUM_8814B                                             \
+	(BIT_MASK_FWCMDQ_DESC_NUM_8814B << BIT_SHIFT_FWCMDQ_DESC_NUM_8814B)
+#define BIT_CLEAR_FWCMDQ_DESC_NUM_8814B(x) ((x) & (~BITS_FWCMDQ_DESC_NUM_8814B))
+#define BIT_GET_FWCMDQ_DESC_NUM_8814B(x)                                       \
+	(((x) >> BIT_SHIFT_FWCMDQ_DESC_NUM_8814B) &                            \
+	 BIT_MASK_FWCMDQ_DESC_NUM_8814B)
+#define BIT_SET_FWCMDQ_DESC_NUM_8814B(x, v)                                    \
+	(BIT_CLEAR_FWCMDQ_DESC_NUM_8814B(x) | BIT_FWCMDQ_DESC_NUM_8814B(v))
+
+/* 2 REG_ACH0_ACH1_TXBD_NUM_8814B */
+#define BIT_PCIE_ACH1_FLAG_V1_8814B BIT(30)
+
+#define BIT_SHIFT_ACH1_DESC_MODE_V1_8814B 28
+#define BIT_MASK_ACH1_DESC_MODE_V1_8814B 0x3
+#define BIT_ACH1_DESC_MODE_V1_8814B(x)                                         \
+	(((x) & BIT_MASK_ACH1_DESC_MODE_V1_8814B)                              \
+	 << BIT_SHIFT_ACH1_DESC_MODE_V1_8814B)
+#define BITS_ACH1_DESC_MODE_V1_8814B                                           \
+	(BIT_MASK_ACH1_DESC_MODE_V1_8814B << BIT_SHIFT_ACH1_DESC_MODE_V1_8814B)
+#define BIT_CLEAR_ACH1_DESC_MODE_V1_8814B(x)                                   \
+	((x) & (~BITS_ACH1_DESC_MODE_V1_8814B))
+#define BIT_GET_ACH1_DESC_MODE_V1_8814B(x)                                     \
+	(((x) >> BIT_SHIFT_ACH1_DESC_MODE_V1_8814B) &                          \
+	 BIT_MASK_ACH1_DESC_MODE_V1_8814B)
+#define BIT_SET_ACH1_DESC_MODE_V1_8814B(x, v)                                  \
+	(BIT_CLEAR_ACH1_DESC_MODE_V1_8814B(x) | BIT_ACH1_DESC_MODE_V1_8814B(v))
+
+#define BIT_SHIFT_ACH1_DESC_NUM_V1_8814B 16
+#define BIT_MASK_ACH1_DESC_NUM_V1_8814B 0xfff
+#define BIT_ACH1_DESC_NUM_V1_8814B(x)                                          \
+	(((x) & BIT_MASK_ACH1_DESC_NUM_V1_8814B)                               \
+	 << BIT_SHIFT_ACH1_DESC_NUM_V1_8814B)
+#define BITS_ACH1_DESC_NUM_V1_8814B                                            \
+	(BIT_MASK_ACH1_DESC_NUM_V1_8814B << BIT_SHIFT_ACH1_DESC_NUM_V1_8814B)
+#define BIT_CLEAR_ACH1_DESC_NUM_V1_8814B(x)                                    \
+	((x) & (~BITS_ACH1_DESC_NUM_V1_8814B))
+#define BIT_GET_ACH1_DESC_NUM_V1_8814B(x)                                      \
+	(((x) >> BIT_SHIFT_ACH1_DESC_NUM_V1_8814B) &                           \
+	 BIT_MASK_ACH1_DESC_NUM_V1_8814B)
+#define BIT_SET_ACH1_DESC_NUM_V1_8814B(x, v)                                   \
+	(BIT_CLEAR_ACH1_DESC_NUM_V1_8814B(x) | BIT_ACH1_DESC_NUM_V1_8814B(v))
+
+#define BIT_PCIE_ACH0_FLAG_8814B BIT(14)
+
+#define BIT_SHIFT_ACH0_DESC_MODE_8814B 12
+#define BIT_MASK_ACH0_DESC_MODE_8814B 0x3
+#define BIT_ACH0_DESC_MODE_8814B(x)                                            \
+	(((x) & BIT_MASK_ACH0_DESC_MODE_8814B)                                 \
+	 << BIT_SHIFT_ACH0_DESC_MODE_8814B)
+#define BITS_ACH0_DESC_MODE_8814B                                              \
+	(BIT_MASK_ACH0_DESC_MODE_8814B << BIT_SHIFT_ACH0_DESC_MODE_8814B)
+#define BIT_CLEAR_ACH0_DESC_MODE_8814B(x) ((x) & (~BITS_ACH0_DESC_MODE_8814B))
+#define BIT_GET_ACH0_DESC_MODE_8814B(x)                                        \
+	(((x) >> BIT_SHIFT_ACH0_DESC_MODE_8814B) &                             \
+	 BIT_MASK_ACH0_DESC_MODE_8814B)
+#define BIT_SET_ACH0_DESC_MODE_8814B(x, v)                                     \
+	(BIT_CLEAR_ACH0_DESC_MODE_8814B(x) | BIT_ACH0_DESC_MODE_8814B(v))
+
+#define BIT_SHIFT_ACH0_DESC_NUM_8814B 0
+#define BIT_MASK_ACH0_DESC_NUM_8814B 0xfff
+#define BIT_ACH0_DESC_NUM_8814B(x)                                             \
+	(((x) & BIT_MASK_ACH0_DESC_NUM_8814B) << BIT_SHIFT_ACH0_DESC_NUM_8814B)
+#define BITS_ACH0_DESC_NUM_8814B                                               \
+	(BIT_MASK_ACH0_DESC_NUM_8814B << BIT_SHIFT_ACH0_DESC_NUM_8814B)
+#define BIT_CLEAR_ACH0_DESC_NUM_8814B(x) ((x) & (~BITS_ACH0_DESC_NUM_8814B))
+#define BIT_GET_ACH0_DESC_NUM_8814B(x)                                         \
+	(((x) >> BIT_SHIFT_ACH0_DESC_NUM_8814B) & BIT_MASK_ACH0_DESC_NUM_8814B)
+#define BIT_SET_ACH0_DESC_NUM_8814B(x, v)                                      \
+	(BIT_CLEAR_ACH0_DESC_NUM_8814B(x) | BIT_ACH0_DESC_NUM_8814B(v))
+
+/* 2 REG_ACH2_ACH3_TXBD_NUM_8814B */
+#define BIT_PCIE_ACH3_FLAG_V1_8814B BIT(30)
+
+#define BIT_SHIFT_ACH3_DESC_MODE_V1_8814B 28
+#define BIT_MASK_ACH3_DESC_MODE_V1_8814B 0x3
+#define BIT_ACH3_DESC_MODE_V1_8814B(x)                                         \
+	(((x) & BIT_MASK_ACH3_DESC_MODE_V1_8814B)                              \
+	 << BIT_SHIFT_ACH3_DESC_MODE_V1_8814B)
+#define BITS_ACH3_DESC_MODE_V1_8814B                                           \
+	(BIT_MASK_ACH3_DESC_MODE_V1_8814B << BIT_SHIFT_ACH3_DESC_MODE_V1_8814B)
+#define BIT_CLEAR_ACH3_DESC_MODE_V1_8814B(x)                                   \
+	((x) & (~BITS_ACH3_DESC_MODE_V1_8814B))
+#define BIT_GET_ACH3_DESC_MODE_V1_8814B(x)                                     \
+	(((x) >> BIT_SHIFT_ACH3_DESC_MODE_V1_8814B) &                          \
+	 BIT_MASK_ACH3_DESC_MODE_V1_8814B)
+#define BIT_SET_ACH3_DESC_MODE_V1_8814B(x, v)                                  \
+	(BIT_CLEAR_ACH3_DESC_MODE_V1_8814B(x) | BIT_ACH3_DESC_MODE_V1_8814B(v))
+
+#define BIT_SHIFT_ACH3_DESC_NUM_V1_8814B 16
+#define BIT_MASK_ACH3_DESC_NUM_V1_8814B 0xfff
+#define BIT_ACH3_DESC_NUM_V1_8814B(x)                                          \
+	(((x) & BIT_MASK_ACH3_DESC_NUM_V1_8814B)                               \
+	 << BIT_SHIFT_ACH3_DESC_NUM_V1_8814B)
+#define BITS_ACH3_DESC_NUM_V1_8814B                                            \
+	(BIT_MASK_ACH3_DESC_NUM_V1_8814B << BIT_SHIFT_ACH3_DESC_NUM_V1_8814B)
+#define BIT_CLEAR_ACH3_DESC_NUM_V1_8814B(x)                                    \
+	((x) & (~BITS_ACH3_DESC_NUM_V1_8814B))
+#define BIT_GET_ACH3_DESC_NUM_V1_8814B(x)                                      \
+	(((x) >> BIT_SHIFT_ACH3_DESC_NUM_V1_8814B) &                           \
+	 BIT_MASK_ACH3_DESC_NUM_V1_8814B)
+#define BIT_SET_ACH3_DESC_NUM_V1_8814B(x, v)                                   \
+	(BIT_CLEAR_ACH3_DESC_NUM_V1_8814B(x) | BIT_ACH3_DESC_NUM_V1_8814B(v))
+
+#define BIT_PCIE_ACH2_FLAG_8814B BIT(14)
+
+#define BIT_SHIFT_ACH2_DESC_MODE_8814B 12
+#define BIT_MASK_ACH2_DESC_MODE_8814B 0x3
+#define BIT_ACH2_DESC_MODE_8814B(x)                                            \
+	(((x) & BIT_MASK_ACH2_DESC_MODE_8814B)                                 \
+	 << BIT_SHIFT_ACH2_DESC_MODE_8814B)
+#define BITS_ACH2_DESC_MODE_8814B                                              \
+	(BIT_MASK_ACH2_DESC_MODE_8814B << BIT_SHIFT_ACH2_DESC_MODE_8814B)
+#define BIT_CLEAR_ACH2_DESC_MODE_8814B(x) ((x) & (~BITS_ACH2_DESC_MODE_8814B))
+#define BIT_GET_ACH2_DESC_MODE_8814B(x)                                        \
+	(((x) >> BIT_SHIFT_ACH2_DESC_MODE_8814B) &                             \
+	 BIT_MASK_ACH2_DESC_MODE_8814B)
+#define BIT_SET_ACH2_DESC_MODE_8814B(x, v)                                     \
+	(BIT_CLEAR_ACH2_DESC_MODE_8814B(x) | BIT_ACH2_DESC_MODE_8814B(v))
+
+#define BIT_SHIFT_ACH2_DESC_NUM_8814B 0
+#define BIT_MASK_ACH2_DESC_NUM_8814B 0xfff
+#define BIT_ACH2_DESC_NUM_8814B(x)                                             \
+	(((x) & BIT_MASK_ACH2_DESC_NUM_8814B) << BIT_SHIFT_ACH2_DESC_NUM_8814B)
+#define BITS_ACH2_DESC_NUM_8814B                                               \
+	(BIT_MASK_ACH2_DESC_NUM_8814B << BIT_SHIFT_ACH2_DESC_NUM_8814B)
+#define BIT_CLEAR_ACH2_DESC_NUM_8814B(x) ((x) & (~BITS_ACH2_DESC_NUM_8814B))
+#define BIT_GET_ACH2_DESC_NUM_8814B(x)                                         \
+	(((x) >> BIT_SHIFT_ACH2_DESC_NUM_8814B) & BIT_MASK_ACH2_DESC_NUM_8814B)
+#define BIT_SET_ACH2_DESC_NUM_8814B(x, v)                                      \
+	(BIT_CLEAR_ACH2_DESC_NUM_8814B(x) | BIT_ACH2_DESC_NUM_8814B(v))
+
+/* 2 REG_P0HI0Q_HI1Q_TXBD_NUM_8814B */
+#define BIT_P0HI1Q_FLAG_8814B BIT(30)
+
+#define BIT_SHIFT_P0HI1Q_DESC_MODE_8814B 28
+#define BIT_MASK_P0HI1Q_DESC_MODE_8814B 0x3
+#define BIT_P0HI1Q_DESC_MODE_8814B(x)                                          \
+	(((x) & BIT_MASK_P0HI1Q_DESC_MODE_8814B)                               \
+	 << BIT_SHIFT_P0HI1Q_DESC_MODE_8814B)
+#define BITS_P0HI1Q_DESC_MODE_8814B                                            \
+	(BIT_MASK_P0HI1Q_DESC_MODE_8814B << BIT_SHIFT_P0HI1Q_DESC_MODE_8814B)
+#define BIT_CLEAR_P0HI1Q_DESC_MODE_8814B(x)                                    \
+	((x) & (~BITS_P0HI1Q_DESC_MODE_8814B))
+#define BIT_GET_P0HI1Q_DESC_MODE_8814B(x)                                      \
+	(((x) >> BIT_SHIFT_P0HI1Q_DESC_MODE_8814B) &                           \
+	 BIT_MASK_P0HI1Q_DESC_MODE_8814B)
+#define BIT_SET_P0HI1Q_DESC_MODE_8814B(x, v)                                   \
+	(BIT_CLEAR_P0HI1Q_DESC_MODE_8814B(x) | BIT_P0HI1Q_DESC_MODE_8814B(v))
+
+#define BIT_SHIFT_P0HI1Q_DESC_NUM_8814B 16
+#define BIT_MASK_P0HI1Q_DESC_NUM_8814B 0xfff
+#define BIT_P0HI1Q_DESC_NUM_8814B(x)                                           \
+	(((x) & BIT_MASK_P0HI1Q_DESC_NUM_8814B)                                \
+	 << BIT_SHIFT_P0HI1Q_DESC_NUM_8814B)
+#define BITS_P0HI1Q_DESC_NUM_8814B                                             \
+	(BIT_MASK_P0HI1Q_DESC_NUM_8814B << BIT_SHIFT_P0HI1Q_DESC_NUM_8814B)
+#define BIT_CLEAR_P0HI1Q_DESC_NUM_8814B(x) ((x) & (~BITS_P0HI1Q_DESC_NUM_8814B))
+#define BIT_GET_P0HI1Q_DESC_NUM_8814B(x)                                       \
+	(((x) >> BIT_SHIFT_P0HI1Q_DESC_NUM_8814B) &                            \
+	 BIT_MASK_P0HI1Q_DESC_NUM_8814B)
+#define BIT_SET_P0HI1Q_DESC_NUM_8814B(x, v)                                    \
+	(BIT_CLEAR_P0HI1Q_DESC_NUM_8814B(x) | BIT_P0HI1Q_DESC_NUM_8814B(v))
+
+#define BIT_P0HI0Q_FLAG_8814B BIT(14)
+
+#define BIT_SHIFT_P0HI0Q_DESC_MODE_8814B 12
+#define BIT_MASK_P0HI0Q_DESC_MODE_8814B 0x3
+#define BIT_P0HI0Q_DESC_MODE_8814B(x)                                          \
+	(((x) & BIT_MASK_P0HI0Q_DESC_MODE_8814B)                               \
+	 << BIT_SHIFT_P0HI0Q_DESC_MODE_8814B)
+#define BITS_P0HI0Q_DESC_MODE_8814B                                            \
+	(BIT_MASK_P0HI0Q_DESC_MODE_8814B << BIT_SHIFT_P0HI0Q_DESC_MODE_8814B)
+#define BIT_CLEAR_P0HI0Q_DESC_MODE_8814B(x)                                    \
+	((x) & (~BITS_P0HI0Q_DESC_MODE_8814B))
+#define BIT_GET_P0HI0Q_DESC_MODE_8814B(x)                                      \
+	(((x) >> BIT_SHIFT_P0HI0Q_DESC_MODE_8814B) &                           \
+	 BIT_MASK_P0HI0Q_DESC_MODE_8814B)
+#define BIT_SET_P0HI0Q_DESC_MODE_8814B(x, v)                                   \
+	(BIT_CLEAR_P0HI0Q_DESC_MODE_8814B(x) | BIT_P0HI0Q_DESC_MODE_8814B(v))
+
+#define BIT_SHIFT_P0HI0Q_DESC_NUM_8814B 0
+#define BIT_MASK_P0HI0Q_DESC_NUM_8814B 0xfff
+#define BIT_P0HI0Q_DESC_NUM_8814B(x)                                           \
+	(((x) & BIT_MASK_P0HI0Q_DESC_NUM_8814B)                                \
+	 << BIT_SHIFT_P0HI0Q_DESC_NUM_8814B)
+#define BITS_P0HI0Q_DESC_NUM_8814B                                             \
+	(BIT_MASK_P0HI0Q_DESC_NUM_8814B << BIT_SHIFT_P0HI0Q_DESC_NUM_8814B)
+#define BIT_CLEAR_P0HI0Q_DESC_NUM_8814B(x) ((x) & (~BITS_P0HI0Q_DESC_NUM_8814B))
+#define BIT_GET_P0HI0Q_DESC_NUM_8814B(x)                                       \
+	(((x) >> BIT_SHIFT_P0HI0Q_DESC_NUM_8814B) &                            \
+	 BIT_MASK_P0HI0Q_DESC_NUM_8814B)
+#define BIT_SET_P0HI0Q_DESC_NUM_8814B(x, v)                                    \
+	(BIT_CLEAR_P0HI0Q_DESC_NUM_8814B(x) | BIT_P0HI0Q_DESC_NUM_8814B(v))
+
+/* 2 REG_P0HI2Q_HI3Q_TXBD_NUM_8814B */
+#define BIT_P0HI3Q_FLAG_8814B BIT(30)
+
+#define BIT_SHIFT_P0HI3Q_DESC_MODE_8814B 28
+#define BIT_MASK_P0HI3Q_DESC_MODE_8814B 0x3
+#define BIT_P0HI3Q_DESC_MODE_8814B(x)                                          \
+	(((x) & BIT_MASK_P0HI3Q_DESC_MODE_8814B)                               \
+	 << BIT_SHIFT_P0HI3Q_DESC_MODE_8814B)
+#define BITS_P0HI3Q_DESC_MODE_8814B                                            \
+	(BIT_MASK_P0HI3Q_DESC_MODE_8814B << BIT_SHIFT_P0HI3Q_DESC_MODE_8814B)
+#define BIT_CLEAR_P0HI3Q_DESC_MODE_8814B(x)                                    \
+	((x) & (~BITS_P0HI3Q_DESC_MODE_8814B))
+#define BIT_GET_P0HI3Q_DESC_MODE_8814B(x)                                      \
+	(((x) >> BIT_SHIFT_P0HI3Q_DESC_MODE_8814B) &                           \
+	 BIT_MASK_P0HI3Q_DESC_MODE_8814B)
+#define BIT_SET_P0HI3Q_DESC_MODE_8814B(x, v)                                   \
+	(BIT_CLEAR_P0HI3Q_DESC_MODE_8814B(x) | BIT_P0HI3Q_DESC_MODE_8814B(v))
+
+#define BIT_SHIFT_P0HI3Q_DESC_NUM_8814B 16
+#define BIT_MASK_P0HI3Q_DESC_NUM_8814B 0xfff
+#define BIT_P0HI3Q_DESC_NUM_8814B(x)                                           \
+	(((x) & BIT_MASK_P0HI3Q_DESC_NUM_8814B)                                \
+	 << BIT_SHIFT_P0HI3Q_DESC_NUM_8814B)
+#define BITS_P0HI3Q_DESC_NUM_8814B                                             \
+	(BIT_MASK_P0HI3Q_DESC_NUM_8814B << BIT_SHIFT_P0HI3Q_DESC_NUM_8814B)
+#define BIT_CLEAR_P0HI3Q_DESC_NUM_8814B(x) ((x) & (~BITS_P0HI3Q_DESC_NUM_8814B))
+#define BIT_GET_P0HI3Q_DESC_NUM_8814B(x)                                       \
+	(((x) >> BIT_SHIFT_P0HI3Q_DESC_NUM_8814B) &                            \
+	 BIT_MASK_P0HI3Q_DESC_NUM_8814B)
+#define BIT_SET_P0HI3Q_DESC_NUM_8814B(x, v)                                    \
+	(BIT_CLEAR_P0HI3Q_DESC_NUM_8814B(x) | BIT_P0HI3Q_DESC_NUM_8814B(v))
+
+#define BIT_P0HI2Q_FLAG_8814B BIT(14)
+
+#define BIT_SHIFT_P0HI2Q_DESC_MODE_8814B 12
+#define BIT_MASK_P0HI2Q_DESC_MODE_8814B 0x3
+#define BIT_P0HI2Q_DESC_MODE_8814B(x)                                          \
+	(((x) & BIT_MASK_P0HI2Q_DESC_MODE_8814B)                               \
+	 << BIT_SHIFT_P0HI2Q_DESC_MODE_8814B)
+#define BITS_P0HI2Q_DESC_MODE_8814B                                            \
+	(BIT_MASK_P0HI2Q_DESC_MODE_8814B << BIT_SHIFT_P0HI2Q_DESC_MODE_8814B)
+#define BIT_CLEAR_P0HI2Q_DESC_MODE_8814B(x)                                    \
+	((x) & (~BITS_P0HI2Q_DESC_MODE_8814B))
+#define BIT_GET_P0HI2Q_DESC_MODE_8814B(x)                                      \
+	(((x) >> BIT_SHIFT_P0HI2Q_DESC_MODE_8814B) &                           \
+	 BIT_MASK_P0HI2Q_DESC_MODE_8814B)
+#define BIT_SET_P0HI2Q_DESC_MODE_8814B(x, v)                                   \
+	(BIT_CLEAR_P0HI2Q_DESC_MODE_8814B(x) | BIT_P0HI2Q_DESC_MODE_8814B(v))
+
+#define BIT_SHIFT_P0HI2Q_DESC_NUM_8814B 0
+#define BIT_MASK_P0HI2Q_DESC_NUM_8814B 0xfff
+#define BIT_P0HI2Q_DESC_NUM_8814B(x)                                           \
+	(((x) & BIT_MASK_P0HI2Q_DESC_NUM_8814B)                                \
+	 << BIT_SHIFT_P0HI2Q_DESC_NUM_8814B)
+#define BITS_P0HI2Q_DESC_NUM_8814B                                             \
+	(BIT_MASK_P0HI2Q_DESC_NUM_8814B << BIT_SHIFT_P0HI2Q_DESC_NUM_8814B)
+#define BIT_CLEAR_P0HI2Q_DESC_NUM_8814B(x) ((x) & (~BITS_P0HI2Q_DESC_NUM_8814B))
+#define BIT_GET_P0HI2Q_DESC_NUM_8814B(x)                                       \
+	(((x) >> BIT_SHIFT_P0HI2Q_DESC_NUM_8814B) &                            \
+	 BIT_MASK_P0HI2Q_DESC_NUM_8814B)
+#define BIT_SET_P0HI2Q_DESC_NUM_8814B(x, v)                                    \
+	(BIT_CLEAR_P0HI2Q_DESC_NUM_8814B(x) | BIT_P0HI2Q_DESC_NUM_8814B(v))
+
+/* 2 REG_P0HI4Q_HI5Q_TXBD_NUM_8814B */
+#define BIT_P0HI5Q_FLAG_8814B BIT(30)
+
+#define BIT_SHIFT_P0HI5Q_DESC_MODE_8814B 28
+#define BIT_MASK_P0HI5Q_DESC_MODE_8814B 0x3
+#define BIT_P0HI5Q_DESC_MODE_8814B(x)                                          \
+	(((x) & BIT_MASK_P0HI5Q_DESC_MODE_8814B)                               \
+	 << BIT_SHIFT_P0HI5Q_DESC_MODE_8814B)
+#define BITS_P0HI5Q_DESC_MODE_8814B                                            \
+	(BIT_MASK_P0HI5Q_DESC_MODE_8814B << BIT_SHIFT_P0HI5Q_DESC_MODE_8814B)
+#define BIT_CLEAR_P0HI5Q_DESC_MODE_8814B(x)                                    \
+	((x) & (~BITS_P0HI5Q_DESC_MODE_8814B))
+#define BIT_GET_P0HI5Q_DESC_MODE_8814B(x)                                      \
+	(((x) >> BIT_SHIFT_P0HI5Q_DESC_MODE_8814B) &                           \
+	 BIT_MASK_P0HI5Q_DESC_MODE_8814B)
+#define BIT_SET_P0HI5Q_DESC_MODE_8814B(x, v)                                   \
+	(BIT_CLEAR_P0HI5Q_DESC_MODE_8814B(x) | BIT_P0HI5Q_DESC_MODE_8814B(v))
+
+#define BIT_SHIFT_P0HI5Q_DESC_NUM_8814B 16
+#define BIT_MASK_P0HI5Q_DESC_NUM_8814B 0xfff
+#define BIT_P0HI5Q_DESC_NUM_8814B(x)                                           \
+	(((x) & BIT_MASK_P0HI5Q_DESC_NUM_8814B)                                \
+	 << BIT_SHIFT_P0HI5Q_DESC_NUM_8814B)
+#define BITS_P0HI5Q_DESC_NUM_8814B                                             \
+	(BIT_MASK_P0HI5Q_DESC_NUM_8814B << BIT_SHIFT_P0HI5Q_DESC_NUM_8814B)
+#define BIT_CLEAR_P0HI5Q_DESC_NUM_8814B(x) ((x) & (~BITS_P0HI5Q_DESC_NUM_8814B))
+#define BIT_GET_P0HI5Q_DESC_NUM_8814B(x)                                       \
+	(((x) >> BIT_SHIFT_P0HI5Q_DESC_NUM_8814B) &                            \
+	 BIT_MASK_P0HI5Q_DESC_NUM_8814B)
+#define BIT_SET_P0HI5Q_DESC_NUM_8814B(x, v)                                    \
+	(BIT_CLEAR_P0HI5Q_DESC_NUM_8814B(x) | BIT_P0HI5Q_DESC_NUM_8814B(v))
+
+#define BIT_P0HI4Q_FLAG_8814B BIT(14)
+
+#define BIT_SHIFT_P0HI4Q_DESC_MODE_8814B 12
+#define BIT_MASK_P0HI4Q_DESC_MODE_8814B 0x3
+#define BIT_P0HI4Q_DESC_MODE_8814B(x)                                          \
+	(((x) & BIT_MASK_P0HI4Q_DESC_MODE_8814B)                               \
+	 << BIT_SHIFT_P0HI4Q_DESC_MODE_8814B)
+#define BITS_P0HI4Q_DESC_MODE_8814B                                            \
+	(BIT_MASK_P0HI4Q_DESC_MODE_8814B << BIT_SHIFT_P0HI4Q_DESC_MODE_8814B)
+#define BIT_CLEAR_P0HI4Q_DESC_MODE_8814B(x)                                    \
+	((x) & (~BITS_P0HI4Q_DESC_MODE_8814B))
+#define BIT_GET_P0HI4Q_DESC_MODE_8814B(x)                                      \
+	(((x) >> BIT_SHIFT_P0HI4Q_DESC_MODE_8814B) &                           \
+	 BIT_MASK_P0HI4Q_DESC_MODE_8814B)
+#define BIT_SET_P0HI4Q_DESC_MODE_8814B(x, v)                                   \
+	(BIT_CLEAR_P0HI4Q_DESC_MODE_8814B(x) | BIT_P0HI4Q_DESC_MODE_8814B(v))
+
+#define BIT_SHIFT_P0HI4Q_DESC_NUM_8814B 0
+#define BIT_MASK_P0HI4Q_DESC_NUM_8814B 0xfff
+#define BIT_P0HI4Q_DESC_NUM_8814B(x)                                           \
+	(((x) & BIT_MASK_P0HI4Q_DESC_NUM_8814B)                                \
+	 << BIT_SHIFT_P0HI4Q_DESC_NUM_8814B)
+#define BITS_P0HI4Q_DESC_NUM_8814B                                             \
+	(BIT_MASK_P0HI4Q_DESC_NUM_8814B << BIT_SHIFT_P0HI4Q_DESC_NUM_8814B)
+#define BIT_CLEAR_P0HI4Q_DESC_NUM_8814B(x) ((x) & (~BITS_P0HI4Q_DESC_NUM_8814B))
+#define BIT_GET_P0HI4Q_DESC_NUM_8814B(x)                                       \
+	(((x) >> BIT_SHIFT_P0HI4Q_DESC_NUM_8814B) &                            \
+	 BIT_MASK_P0HI4Q_DESC_NUM_8814B)
+#define BIT_SET_P0HI4Q_DESC_NUM_8814B(x, v)                                    \
+	(BIT_CLEAR_P0HI4Q_DESC_NUM_8814B(x) | BIT_P0HI4Q_DESC_NUM_8814B(v))
+
+/* 2 REG_P0HI6Q_HI7Q_TXBD_NUM_8814B */
+#define BIT_P0HI7Q_FLAG_8814B BIT(30)
+
+#define BIT_SHIFT_P0HI7Q_DESC_MODE_8814B 28
+#define BIT_MASK_P0HI7Q_DESC_MODE_8814B 0x3
+#define BIT_P0HI7Q_DESC_MODE_8814B(x)                                          \
+	(((x) & BIT_MASK_P0HI7Q_DESC_MODE_8814B)                               \
+	 << BIT_SHIFT_P0HI7Q_DESC_MODE_8814B)
+#define BITS_P0HI7Q_DESC_MODE_8814B                                            \
+	(BIT_MASK_P0HI7Q_DESC_MODE_8814B << BIT_SHIFT_P0HI7Q_DESC_MODE_8814B)
+#define BIT_CLEAR_P0HI7Q_DESC_MODE_8814B(x)                                    \
+	((x) & (~BITS_P0HI7Q_DESC_MODE_8814B))
+#define BIT_GET_P0HI7Q_DESC_MODE_8814B(x)                                      \
+	(((x) >> BIT_SHIFT_P0HI7Q_DESC_MODE_8814B) &                           \
+	 BIT_MASK_P0HI7Q_DESC_MODE_8814B)
+#define BIT_SET_P0HI7Q_DESC_MODE_8814B(x, v)                                   \
+	(BIT_CLEAR_P0HI7Q_DESC_MODE_8814B(x) | BIT_P0HI7Q_DESC_MODE_8814B(v))
+
+#define BIT_SHIFT_P0HI7Q_DESC_NUM_8814B 16
+#define BIT_MASK_P0HI7Q_DESC_NUM_8814B 0xfff
+#define BIT_P0HI7Q_DESC_NUM_8814B(x)                                           \
+	(((x) & BIT_MASK_P0HI7Q_DESC_NUM_8814B)                                \
+	 << BIT_SHIFT_P0HI7Q_DESC_NUM_8814B)
+#define BITS_P0HI7Q_DESC_NUM_8814B                                             \
+	(BIT_MASK_P0HI7Q_DESC_NUM_8814B << BIT_SHIFT_P0HI7Q_DESC_NUM_8814B)
+#define BIT_CLEAR_P0HI7Q_DESC_NUM_8814B(x) ((x) & (~BITS_P0HI7Q_DESC_NUM_8814B))
+#define BIT_GET_P0HI7Q_DESC_NUM_8814B(x)                                       \
+	(((x) >> BIT_SHIFT_P0HI7Q_DESC_NUM_8814B) &                            \
+	 BIT_MASK_P0HI7Q_DESC_NUM_8814B)
+#define BIT_SET_P0HI7Q_DESC_NUM_8814B(x, v)                                    \
+	(BIT_CLEAR_P0HI7Q_DESC_NUM_8814B(x) | BIT_P0HI7Q_DESC_NUM_8814B(v))
+
+#define BIT_P0HI6Q_FLAG_8814B BIT(14)
+
+#define BIT_SHIFT_P0HI6Q_DESC_MODE_8814B 12
+#define BIT_MASK_P0HI6Q_DESC_MODE_8814B 0x3
+#define BIT_P0HI6Q_DESC_MODE_8814B(x)                                          \
+	(((x) & BIT_MASK_P0HI6Q_DESC_MODE_8814B)                               \
+	 << BIT_SHIFT_P0HI6Q_DESC_MODE_8814B)
+#define BITS_P0HI6Q_DESC_MODE_8814B                                            \
+	(BIT_MASK_P0HI6Q_DESC_MODE_8814B << BIT_SHIFT_P0HI6Q_DESC_MODE_8814B)
+#define BIT_CLEAR_P0HI6Q_DESC_MODE_8814B(x)                                    \
+	((x) & (~BITS_P0HI6Q_DESC_MODE_8814B))
+#define BIT_GET_P0HI6Q_DESC_MODE_8814B(x)                                      \
+	(((x) >> BIT_SHIFT_P0HI6Q_DESC_MODE_8814B) &                           \
+	 BIT_MASK_P0HI6Q_DESC_MODE_8814B)
+#define BIT_SET_P0HI6Q_DESC_MODE_8814B(x, v)                                   \
+	(BIT_CLEAR_P0HI6Q_DESC_MODE_8814B(x) | BIT_P0HI6Q_DESC_MODE_8814B(v))
+
+#define BIT_SHIFT_P0HI6Q_DESC_NUM_8814B 0
+#define BIT_MASK_P0HI6Q_DESC_NUM_8814B 0xfff
+#define BIT_P0HI6Q_DESC_NUM_8814B(x)                                           \
+	(((x) & BIT_MASK_P0HI6Q_DESC_NUM_8814B)                                \
+	 << BIT_SHIFT_P0HI6Q_DESC_NUM_8814B)
+#define BITS_P0HI6Q_DESC_NUM_8814B                                             \
+	(BIT_MASK_P0HI6Q_DESC_NUM_8814B << BIT_SHIFT_P0HI6Q_DESC_NUM_8814B)
+#define BIT_CLEAR_P0HI6Q_DESC_NUM_8814B(x) ((x) & (~BITS_P0HI6Q_DESC_NUM_8814B))
+#define BIT_GET_P0HI6Q_DESC_NUM_8814B(x)                                       \
+	(((x) >> BIT_SHIFT_P0HI6Q_DESC_NUM_8814B) &                            \
+	 BIT_MASK_P0HI6Q_DESC_NUM_8814B)
+#define BIT_SET_P0HI6Q_DESC_NUM_8814B(x, v)                                    \
+	(BIT_CLEAR_P0HI6Q_DESC_NUM_8814B(x) | BIT_P0HI6Q_DESC_NUM_8814B(v))
+
+/* 2 REG_BD_RWPTR_CLR1_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+#define BIT_CLR_FWCMDQ_HW_IDX_8814B BIT(30)
+#define BIT_CLR_P0HI7Q_HW_IDX_8814B BIT(29)
+#define BIT_CLR_P0HI6Q_HW_IDX_8814B BIT(28)
+#define BIT_CLR_P0HI5Q_HW_IDX_8814B BIT(27)
+#define BIT_CLR_P0HI4Q_HW_IDX_8814B BIT(26)
+#define BIT_CLR_P0HI3Q_HW_IDX_8814B BIT(25)
+#define BIT_CLR_P0HI2Q_HW_IDX_8814B BIT(24)
+#define BIT_CLR_P0HI1Q_HW_IDX_8814B BIT(23)
+#define BIT_CLR_P0HI0Q_HW_IDX_8814B BIT(22)
+#define BIT_CLR_ACH3_HW_IDX_8814B BIT(21)
+#define BIT_CLR_ACH2_HW_IDX_8814B BIT(20)
+#define BIT_CLR_ACH1_HW_IDX_8814B BIT(19)
+#define BIT_CLR_ACH0_HW_IDX_8814B BIT(18)
+#define BIT_CLR_P0MGQ_HW_IDX_8814B BIT(17)
+#define BIT_CLR_P0RXQ_HW_IDX_8814B BIT(16)
+
+/* 2 REG_NOT_VALID_8814B */
+#define BIT_CLR_PFWCMDQ_HOST_IDX_8814B BIT(14)
+#define BIT_CLR_P0HI7Q_HOST_IDX_8814B BIT(13)
+#define BIT_CLR_P0HI6Q_HOST_IDX_8814B BIT(12)
+#define BIT_CLR_P0HI5Q_HOST_IDX_8814B BIT(11)
+#define BIT_CLR_P0HI4Q_HOST_IDX_8814B BIT(10)
+#define BIT_CLR_P0HI3Q_HOST_IDX_8814B BIT(9)
+#define BIT_CLR_P0HI2Q_HOST_IDX_8814B BIT(8)
+#define BIT_CLR_P0HI1Q_HOST_IDX_8814B BIT(7)
+#define BIT_CLR_P0HI0Q_HOST_IDX_8814B BIT(6)
+#define BIT_CLR_ACH3_HOST_IDX_8814B BIT(5)
+#define BIT_CLR_ACH2_HOST_IDX_8814B BIT(4)
+#define BIT_CLR_ACH1_HOST_IDX_8814B BIT(3)
+#define BIT_CLR_ACH0_HOST_IDX_8814B BIT(2)
+#define BIT_CLR_P0MGQ_HOST_IDX_8814B BIT(1)
+#define BIT_CLR_P0RXQ_HOST_IDX_8814B BIT(0)
+
+/* 2 REG_TSFTIMER_HCI_8814B */
+
+#define BIT_SHIFT_TSFT2_HCI_8814B 16
+#define BIT_MASK_TSFT2_HCI_8814B 0xffff
+#define BIT_TSFT2_HCI_8814B(x)                                                 \
+	(((x) & BIT_MASK_TSFT2_HCI_8814B) << BIT_SHIFT_TSFT2_HCI_8814B)
+#define BITS_TSFT2_HCI_8814B                                                   \
+	(BIT_MASK_TSFT2_HCI_8814B << BIT_SHIFT_TSFT2_HCI_8814B)
+#define BIT_CLEAR_TSFT2_HCI_8814B(x) ((x) & (~BITS_TSFT2_HCI_8814B))
+#define BIT_GET_TSFT2_HCI_8814B(x)                                             \
+	(((x) >> BIT_SHIFT_TSFT2_HCI_8814B) & BIT_MASK_TSFT2_HCI_8814B)
+#define BIT_SET_TSFT2_HCI_8814B(x, v)                                          \
+	(BIT_CLEAR_TSFT2_HCI_8814B(x) | BIT_TSFT2_HCI_8814B(v))
+
+#define BIT_SHIFT_TSFT1_HCI_8814B 0
+#define BIT_MASK_TSFT1_HCI_8814B 0xffff
+#define BIT_TSFT1_HCI_8814B(x)                                                 \
+	(((x) & BIT_MASK_TSFT1_HCI_8814B) << BIT_SHIFT_TSFT1_HCI_8814B)
+#define BITS_TSFT1_HCI_8814B                                                   \
+	(BIT_MASK_TSFT1_HCI_8814B << BIT_SHIFT_TSFT1_HCI_8814B)
+#define BIT_CLEAR_TSFT1_HCI_8814B(x) ((x) & (~BITS_TSFT1_HCI_8814B))
+#define BIT_GET_TSFT1_HCI_8814B(x)                                             \
+	(((x) >> BIT_SHIFT_TSFT1_HCI_8814B) & BIT_MASK_TSFT1_HCI_8814B)
+#define BIT_SET_TSFT1_HCI_8814B(x, v)                                          \
+	(BIT_CLEAR_TSFT1_HCI_8814B(x) | BIT_TSFT1_HCI_8814B(v))
+
+/* 2 REG_ACH0_TXBD_IDX_8814B */
+
+#define BIT_SHIFT_ACH0_HW_IDX_8814B 16
+#define BIT_MASK_ACH0_HW_IDX_8814B 0xfff
+#define BIT_ACH0_HW_IDX_8814B(x)                                               \
+	(((x) & BIT_MASK_ACH0_HW_IDX_8814B) << BIT_SHIFT_ACH0_HW_IDX_8814B)
+#define BITS_ACH0_HW_IDX_8814B                                                 \
+	(BIT_MASK_ACH0_HW_IDX_8814B << BIT_SHIFT_ACH0_HW_IDX_8814B)
+#define BIT_CLEAR_ACH0_HW_IDX_8814B(x) ((x) & (~BITS_ACH0_HW_IDX_8814B))
+#define BIT_GET_ACH0_HW_IDX_8814B(x)                                           \
+	(((x) >> BIT_SHIFT_ACH0_HW_IDX_8814B) & BIT_MASK_ACH0_HW_IDX_8814B)
+#define BIT_SET_ACH0_HW_IDX_8814B(x, v)                                        \
+	(BIT_CLEAR_ACH0_HW_IDX_8814B(x) | BIT_ACH0_HW_IDX_8814B(v))
+
+#define BIT_SHIFT_ACH0_HOST_IDX_8814B 0
+#define BIT_MASK_ACH0_HOST_IDX_8814B 0xfff
+#define BIT_ACH0_HOST_IDX_8814B(x)                                             \
+	(((x) & BIT_MASK_ACH0_HOST_IDX_8814B) << BIT_SHIFT_ACH0_HOST_IDX_8814B)
+#define BITS_ACH0_HOST_IDX_8814B                                               \
+	(BIT_MASK_ACH0_HOST_IDX_8814B << BIT_SHIFT_ACH0_HOST_IDX_8814B)
+#define BIT_CLEAR_ACH0_HOST_IDX_8814B(x) ((x) & (~BITS_ACH0_HOST_IDX_8814B))
+#define BIT_GET_ACH0_HOST_IDX_8814B(x)                                         \
+	(((x) >> BIT_SHIFT_ACH0_HOST_IDX_8814B) & BIT_MASK_ACH0_HOST_IDX_8814B)
+#define BIT_SET_ACH0_HOST_IDX_8814B(x, v)                                      \
+	(BIT_CLEAR_ACH0_HOST_IDX_8814B(x) | BIT_ACH0_HOST_IDX_8814B(v))
+
+/* 2 REG_ACH1_TXBD_IDX_8814B */
+
+#define BIT_SHIFT_ACH1_HW_IDX_8814B 16
+#define BIT_MASK_ACH1_HW_IDX_8814B 0xfff
+#define BIT_ACH1_HW_IDX_8814B(x)                                               \
+	(((x) & BIT_MASK_ACH1_HW_IDX_8814B) << BIT_SHIFT_ACH1_HW_IDX_8814B)
+#define BITS_ACH1_HW_IDX_8814B                                                 \
+	(BIT_MASK_ACH1_HW_IDX_8814B << BIT_SHIFT_ACH1_HW_IDX_8814B)
+#define BIT_CLEAR_ACH1_HW_IDX_8814B(x) ((x) & (~BITS_ACH1_HW_IDX_8814B))
+#define BIT_GET_ACH1_HW_IDX_8814B(x)                                           \
+	(((x) >> BIT_SHIFT_ACH1_HW_IDX_8814B) & BIT_MASK_ACH1_HW_IDX_8814B)
+#define BIT_SET_ACH1_HW_IDX_8814B(x, v)                                        \
+	(BIT_CLEAR_ACH1_HW_IDX_8814B(x) | BIT_ACH1_HW_IDX_8814B(v))
+
+#define BIT_SHIFT_ACH1_HOST_IDX_8814B 0
+#define BIT_MASK_ACH1_HOST_IDX_8814B 0xfff
+#define BIT_ACH1_HOST_IDX_8814B(x)                                             \
+	(((x) & BIT_MASK_ACH1_HOST_IDX_8814B) << BIT_SHIFT_ACH1_HOST_IDX_8814B)
+#define BITS_ACH1_HOST_IDX_8814B                                               \
+	(BIT_MASK_ACH1_HOST_IDX_8814B << BIT_SHIFT_ACH1_HOST_IDX_8814B)
+#define BIT_CLEAR_ACH1_HOST_IDX_8814B(x) ((x) & (~BITS_ACH1_HOST_IDX_8814B))
+#define BIT_GET_ACH1_HOST_IDX_8814B(x)                                         \
+	(((x) >> BIT_SHIFT_ACH1_HOST_IDX_8814B) & BIT_MASK_ACH1_HOST_IDX_8814B)
+#define BIT_SET_ACH1_HOST_IDX_8814B(x, v)                                      \
+	(BIT_CLEAR_ACH1_HOST_IDX_8814B(x) | BIT_ACH1_HOST_IDX_8814B(v))
+
+/* 2 REG_ACH2_TXBD_IDX_8814B */
+
+#define BIT_SHIFT_ACH2_HW_IDX_8814B 16
+#define BIT_MASK_ACH2_HW_IDX_8814B 0xfff
+#define BIT_ACH2_HW_IDX_8814B(x)                                               \
+	(((x) & BIT_MASK_ACH2_HW_IDX_8814B) << BIT_SHIFT_ACH2_HW_IDX_8814B)
+#define BITS_ACH2_HW_IDX_8814B                                                 \
+	(BIT_MASK_ACH2_HW_IDX_8814B << BIT_SHIFT_ACH2_HW_IDX_8814B)
+#define BIT_CLEAR_ACH2_HW_IDX_8814B(x) ((x) & (~BITS_ACH2_HW_IDX_8814B))
+#define BIT_GET_ACH2_HW_IDX_8814B(x)                                           \
+	(((x) >> BIT_SHIFT_ACH2_HW_IDX_8814B) & BIT_MASK_ACH2_HW_IDX_8814B)
+#define BIT_SET_ACH2_HW_IDX_8814B(x, v)                                        \
+	(BIT_CLEAR_ACH2_HW_IDX_8814B(x) | BIT_ACH2_HW_IDX_8814B(v))
+
+#define BIT_SHIFT_ACH2_HOST_IDX_8814B 0
+#define BIT_MASK_ACH2_HOST_IDX_8814B 0xfff
+#define BIT_ACH2_HOST_IDX_8814B(x)                                             \
+	(((x) & BIT_MASK_ACH2_HOST_IDX_8814B) << BIT_SHIFT_ACH2_HOST_IDX_8814B)
+#define BITS_ACH2_HOST_IDX_8814B                                               \
+	(BIT_MASK_ACH2_HOST_IDX_8814B << BIT_SHIFT_ACH2_HOST_IDX_8814B)
+#define BIT_CLEAR_ACH2_HOST_IDX_8814B(x) ((x) & (~BITS_ACH2_HOST_IDX_8814B))
+#define BIT_GET_ACH2_HOST_IDX_8814B(x)                                         \
+	(((x) >> BIT_SHIFT_ACH2_HOST_IDX_8814B) & BIT_MASK_ACH2_HOST_IDX_8814B)
+#define BIT_SET_ACH2_HOST_IDX_8814B(x, v)                                      \
+	(BIT_CLEAR_ACH2_HOST_IDX_8814B(x) | BIT_ACH2_HOST_IDX_8814B(v))
+
+/* 2 REG_ACH3_TXBD_IDX_8814B */
+
+#define BIT_SHIFT_ACH3_HW_IDX_8814B 16
+#define BIT_MASK_ACH3_HW_IDX_8814B 0xfff
+#define BIT_ACH3_HW_IDX_8814B(x)                                               \
+	(((x) & BIT_MASK_ACH3_HW_IDX_8814B) << BIT_SHIFT_ACH3_HW_IDX_8814B)
+#define BITS_ACH3_HW_IDX_8814B                                                 \
+	(BIT_MASK_ACH3_HW_IDX_8814B << BIT_SHIFT_ACH3_HW_IDX_8814B)
+#define BIT_CLEAR_ACH3_HW_IDX_8814B(x) ((x) & (~BITS_ACH3_HW_IDX_8814B))
+#define BIT_GET_ACH3_HW_IDX_8814B(x)                                           \
+	(((x) >> BIT_SHIFT_ACH3_HW_IDX_8814B) & BIT_MASK_ACH3_HW_IDX_8814B)
+#define BIT_SET_ACH3_HW_IDX_8814B(x, v)                                        \
+	(BIT_CLEAR_ACH3_HW_IDX_8814B(x) | BIT_ACH3_HW_IDX_8814B(v))
+
+#define BIT_SHIFT_ACH3_HOST_IDX_8814B 0
+#define BIT_MASK_ACH3_HOST_IDX_8814B 0xfff
+#define BIT_ACH3_HOST_IDX_8814B(x)                                             \
+	(((x) & BIT_MASK_ACH3_HOST_IDX_8814B) << BIT_SHIFT_ACH3_HOST_IDX_8814B)
+#define BITS_ACH3_HOST_IDX_8814B                                               \
+	(BIT_MASK_ACH3_HOST_IDX_8814B << BIT_SHIFT_ACH3_HOST_IDX_8814B)
+#define BIT_CLEAR_ACH3_HOST_IDX_8814B(x) ((x) & (~BITS_ACH3_HOST_IDX_8814B))
+#define BIT_GET_ACH3_HOST_IDX_8814B(x)                                         \
+	(((x) >> BIT_SHIFT_ACH3_HOST_IDX_8814B) & BIT_MASK_ACH3_HOST_IDX_8814B)
+#define BIT_SET_ACH3_HOST_IDX_8814B(x, v)                                      \
+	(BIT_CLEAR_ACH3_HOST_IDX_8814B(x) | BIT_ACH3_HOST_IDX_8814B(v))
+
+/* 2 REG_P0MGQ_TXBD_IDX_8814B */
+
+#define BIT_SHIFT_P0MGQ_HW_IDX_8814B 16
+#define BIT_MASK_P0MGQ_HW_IDX_8814B 0xfff
+#define BIT_P0MGQ_HW_IDX_8814B(x)                                              \
+	(((x) & BIT_MASK_P0MGQ_HW_IDX_8814B) << BIT_SHIFT_P0MGQ_HW_IDX_8814B)
+#define BITS_P0MGQ_HW_IDX_8814B                                                \
+	(BIT_MASK_P0MGQ_HW_IDX_8814B << BIT_SHIFT_P0MGQ_HW_IDX_8814B)
+#define BIT_CLEAR_P0MGQ_HW_IDX_8814B(x) ((x) & (~BITS_P0MGQ_HW_IDX_8814B))
+#define BIT_GET_P0MGQ_HW_IDX_8814B(x)                                          \
+	(((x) >> BIT_SHIFT_P0MGQ_HW_IDX_8814B) & BIT_MASK_P0MGQ_HW_IDX_8814B)
+#define BIT_SET_P0MGQ_HW_IDX_8814B(x, v)                                       \
+	(BIT_CLEAR_P0MGQ_HW_IDX_8814B(x) | BIT_P0MGQ_HW_IDX_8814B(v))
+
+#define BIT_SHIFT_P0MGQ_HOST_IDX_8814B 0
+#define BIT_MASK_P0MGQ_HOST_IDX_8814B 0xfff
+#define BIT_P0MGQ_HOST_IDX_8814B(x)                                            \
+	(((x) & BIT_MASK_P0MGQ_HOST_IDX_8814B)                                 \
+	 << BIT_SHIFT_P0MGQ_HOST_IDX_8814B)
+#define BITS_P0MGQ_HOST_IDX_8814B                                              \
+	(BIT_MASK_P0MGQ_HOST_IDX_8814B << BIT_SHIFT_P0MGQ_HOST_IDX_8814B)
+#define BIT_CLEAR_P0MGQ_HOST_IDX_8814B(x) ((x) & (~BITS_P0MGQ_HOST_IDX_8814B))
+#define BIT_GET_P0MGQ_HOST_IDX_8814B(x)                                        \
+	(((x) >> BIT_SHIFT_P0MGQ_HOST_IDX_8814B) &                             \
+	 BIT_MASK_P0MGQ_HOST_IDX_8814B)
+#define BIT_SET_P0MGQ_HOST_IDX_8814B(x, v)                                     \
+	(BIT_CLEAR_P0MGQ_HOST_IDX_8814B(x) | BIT_P0MGQ_HOST_IDX_8814B(v))
+
+/* 2 REG_P0RXQ_RXBD_IDX_8814B */
+
+#define BIT_SHIFT_P0RXQ_HW_IDX_8814B 16
+#define BIT_MASK_P0RXQ_HW_IDX_8814B 0xfff
+#define BIT_P0RXQ_HW_IDX_8814B(x)                                              \
+	(((x) & BIT_MASK_P0RXQ_HW_IDX_8814B) << BIT_SHIFT_P0RXQ_HW_IDX_8814B)
+#define BITS_P0RXQ_HW_IDX_8814B                                                \
+	(BIT_MASK_P0RXQ_HW_IDX_8814B << BIT_SHIFT_P0RXQ_HW_IDX_8814B)
+#define BIT_CLEAR_P0RXQ_HW_IDX_8814B(x) ((x) & (~BITS_P0RXQ_HW_IDX_8814B))
+#define BIT_GET_P0RXQ_HW_IDX_8814B(x)                                          \
+	(((x) >> BIT_SHIFT_P0RXQ_HW_IDX_8814B) & BIT_MASK_P0RXQ_HW_IDX_8814B)
+#define BIT_SET_P0RXQ_HW_IDX_8814B(x, v)                                       \
+	(BIT_CLEAR_P0RXQ_HW_IDX_8814B(x) | BIT_P0RXQ_HW_IDX_8814B(v))
+
+#define BIT_SHIFT_P0RXQ_HOST_IDX_8814B 0
+#define BIT_MASK_P0RXQ_HOST_IDX_8814B 0xfff
+#define BIT_P0RXQ_HOST_IDX_8814B(x)                                            \
+	(((x) & BIT_MASK_P0RXQ_HOST_IDX_8814B)                                 \
+	 << BIT_SHIFT_P0RXQ_HOST_IDX_8814B)
+#define BITS_P0RXQ_HOST_IDX_8814B                                              \
+	(BIT_MASK_P0RXQ_HOST_IDX_8814B << BIT_SHIFT_P0RXQ_HOST_IDX_8814B)
+#define BIT_CLEAR_P0RXQ_HOST_IDX_8814B(x) ((x) & (~BITS_P0RXQ_HOST_IDX_8814B))
+#define BIT_GET_P0RXQ_HOST_IDX_8814B(x)                                        \
+	(((x) >> BIT_SHIFT_P0RXQ_HOST_IDX_8814B) &                             \
+	 BIT_MASK_P0RXQ_HOST_IDX_8814B)
+#define BIT_SET_P0RXQ_HOST_IDX_8814B(x, v)                                     \
+	(BIT_CLEAR_P0RXQ_HOST_IDX_8814B(x) | BIT_P0RXQ_HOST_IDX_8814B(v))
+
+/* 2 REG_P0HI0Q_TXBD_IDX_8814B */
+
+#define BIT_SHIFT_P0HI0Q_HW_IDX_8814B 16
+#define BIT_MASK_P0HI0Q_HW_IDX_8814B 0xfff
+#define BIT_P0HI0Q_HW_IDX_8814B(x)                                             \
+	(((x) & BIT_MASK_P0HI0Q_HW_IDX_8814B) << BIT_SHIFT_P0HI0Q_HW_IDX_8814B)
+#define BITS_P0HI0Q_HW_IDX_8814B                                               \
+	(BIT_MASK_P0HI0Q_HW_IDX_8814B << BIT_SHIFT_P0HI0Q_HW_IDX_8814B)
+#define BIT_CLEAR_P0HI0Q_HW_IDX_8814B(x) ((x) & (~BITS_P0HI0Q_HW_IDX_8814B))
+#define BIT_GET_P0HI0Q_HW_IDX_8814B(x)                                         \
+	(((x) >> BIT_SHIFT_P0HI0Q_HW_IDX_8814B) & BIT_MASK_P0HI0Q_HW_IDX_8814B)
+#define BIT_SET_P0HI0Q_HW_IDX_8814B(x, v)                                      \
+	(BIT_CLEAR_P0HI0Q_HW_IDX_8814B(x) | BIT_P0HI0Q_HW_IDX_8814B(v))
+
+#define BIT_SHIFT_P0HI0Q_HOST_IDX_8814B 0
+#define BIT_MASK_P0HI0Q_HOST_IDX_8814B 0xfff
+#define BIT_P0HI0Q_HOST_IDX_8814B(x)                                           \
+	(((x) & BIT_MASK_P0HI0Q_HOST_IDX_8814B)                                \
+	 << BIT_SHIFT_P0HI0Q_HOST_IDX_8814B)
+#define BITS_P0HI0Q_HOST_IDX_8814B                                             \
+	(BIT_MASK_P0HI0Q_HOST_IDX_8814B << BIT_SHIFT_P0HI0Q_HOST_IDX_8814B)
+#define BIT_CLEAR_P0HI0Q_HOST_IDX_8814B(x) ((x) & (~BITS_P0HI0Q_HOST_IDX_8814B))
+#define BIT_GET_P0HI0Q_HOST_IDX_8814B(x)                                       \
+	(((x) >> BIT_SHIFT_P0HI0Q_HOST_IDX_8814B) &                            \
+	 BIT_MASK_P0HI0Q_HOST_IDX_8814B)
+#define BIT_SET_P0HI0Q_HOST_IDX_8814B(x, v)                                    \
+	(BIT_CLEAR_P0HI0Q_HOST_IDX_8814B(x) | BIT_P0HI0Q_HOST_IDX_8814B(v))
+
+/* 2 REG_P0HI1Q_TXBD_IDX_8814B */
+
+#define BIT_SHIFT_P0HI1Q_HW_IDX_8814B 16
+#define BIT_MASK_P0HI1Q_HW_IDX_8814B 0xfff
+#define BIT_P0HI1Q_HW_IDX_8814B(x)                                             \
+	(((x) & BIT_MASK_P0HI1Q_HW_IDX_8814B) << BIT_SHIFT_P0HI1Q_HW_IDX_8814B)
+#define BITS_P0HI1Q_HW_IDX_8814B                                               \
+	(BIT_MASK_P0HI1Q_HW_IDX_8814B << BIT_SHIFT_P0HI1Q_HW_IDX_8814B)
+#define BIT_CLEAR_P0HI1Q_HW_IDX_8814B(x) ((x) & (~BITS_P0HI1Q_HW_IDX_8814B))
+#define BIT_GET_P0HI1Q_HW_IDX_8814B(x)                                         \
+	(((x) >> BIT_SHIFT_P0HI1Q_HW_IDX_8814B) & BIT_MASK_P0HI1Q_HW_IDX_8814B)
+#define BIT_SET_P0HI1Q_HW_IDX_8814B(x, v)                                      \
+	(BIT_CLEAR_P0HI1Q_HW_IDX_8814B(x) | BIT_P0HI1Q_HW_IDX_8814B(v))
+
+#define BIT_SHIFT_P0HI1Q_HOST_IDX_8814B 0
+#define BIT_MASK_P0HI1Q_HOST_IDX_8814B 0xfff
+#define BIT_P0HI1Q_HOST_IDX_8814B(x)                                           \
+	(((x) & BIT_MASK_P0HI1Q_HOST_IDX_8814B)                                \
+	 << BIT_SHIFT_P0HI1Q_HOST_IDX_8814B)
+#define BITS_P0HI1Q_HOST_IDX_8814B                                             \
+	(BIT_MASK_P0HI1Q_HOST_IDX_8814B << BIT_SHIFT_P0HI1Q_HOST_IDX_8814B)
+#define BIT_CLEAR_P0HI1Q_HOST_IDX_8814B(x) ((x) & (~BITS_P0HI1Q_HOST_IDX_8814B))
+#define BIT_GET_P0HI1Q_HOST_IDX_8814B(x)                                       \
+	(((x) >> BIT_SHIFT_P0HI1Q_HOST_IDX_8814B) &                            \
+	 BIT_MASK_P0HI1Q_HOST_IDX_8814B)
+#define BIT_SET_P0HI1Q_HOST_IDX_8814B(x, v)                                    \
+	(BIT_CLEAR_P0HI1Q_HOST_IDX_8814B(x) | BIT_P0HI1Q_HOST_IDX_8814B(v))
+
+/* 2 REG_P0HI2Q_TXBD_IDX_8814B */
+
+#define BIT_SHIFT_P0HI2Q_HW_IDX_8814B 16
+#define BIT_MASK_P0HI2Q_HW_IDX_8814B 0xfff
+#define BIT_P0HI2Q_HW_IDX_8814B(x)                                             \
+	(((x) & BIT_MASK_P0HI2Q_HW_IDX_8814B) << BIT_SHIFT_P0HI2Q_HW_IDX_8814B)
+#define BITS_P0HI2Q_HW_IDX_8814B                                               \
+	(BIT_MASK_P0HI2Q_HW_IDX_8814B << BIT_SHIFT_P0HI2Q_HW_IDX_8814B)
+#define BIT_CLEAR_P0HI2Q_HW_IDX_8814B(x) ((x) & (~BITS_P0HI2Q_HW_IDX_8814B))
+#define BIT_GET_P0HI2Q_HW_IDX_8814B(x)                                         \
+	(((x) >> BIT_SHIFT_P0HI2Q_HW_IDX_8814B) & BIT_MASK_P0HI2Q_HW_IDX_8814B)
+#define BIT_SET_P0HI2Q_HW_IDX_8814B(x, v)                                      \
+	(BIT_CLEAR_P0HI2Q_HW_IDX_8814B(x) | BIT_P0HI2Q_HW_IDX_8814B(v))
+
+#define BIT_SHIFT_P0HI2Q_HOST_IDX_8814B 0
+#define BIT_MASK_P0HI2Q_HOST_IDX_8814B 0xfff
+#define BIT_P0HI2Q_HOST_IDX_8814B(x)                                           \
+	(((x) & BIT_MASK_P0HI2Q_HOST_IDX_8814B)                                \
+	 << BIT_SHIFT_P0HI2Q_HOST_IDX_8814B)
+#define BITS_P0HI2Q_HOST_IDX_8814B                                             \
+	(BIT_MASK_P0HI2Q_HOST_IDX_8814B << BIT_SHIFT_P0HI2Q_HOST_IDX_8814B)
+#define BIT_CLEAR_P0HI2Q_HOST_IDX_8814B(x) ((x) & (~BITS_P0HI2Q_HOST_IDX_8814B))
+#define BIT_GET_P0HI2Q_HOST_IDX_8814B(x)                                       \
+	(((x) >> BIT_SHIFT_P0HI2Q_HOST_IDX_8814B) &                            \
+	 BIT_MASK_P0HI2Q_HOST_IDX_8814B)
+#define BIT_SET_P0HI2Q_HOST_IDX_8814B(x, v)                                    \
+	(BIT_CLEAR_P0HI2Q_HOST_IDX_8814B(x) | BIT_P0HI2Q_HOST_IDX_8814B(v))
+
+/* 2 REG_P0HI3Q_TXBD_IDX_8814B */
+
+#define BIT_SHIFT_P0HI3Q_HW_IDX_8814B 16
+#define BIT_MASK_P0HI3Q_HW_IDX_8814B 0xfff
+#define BIT_P0HI3Q_HW_IDX_8814B(x)                                             \
+	(((x) & BIT_MASK_P0HI3Q_HW_IDX_8814B) << BIT_SHIFT_P0HI3Q_HW_IDX_8814B)
+#define BITS_P0HI3Q_HW_IDX_8814B                                               \
+	(BIT_MASK_P0HI3Q_HW_IDX_8814B << BIT_SHIFT_P0HI3Q_HW_IDX_8814B)
+#define BIT_CLEAR_P0HI3Q_HW_IDX_8814B(x) ((x) & (~BITS_P0HI3Q_HW_IDX_8814B))
+#define BIT_GET_P0HI3Q_HW_IDX_8814B(x)                                         \
+	(((x) >> BIT_SHIFT_P0HI3Q_HW_IDX_8814B) & BIT_MASK_P0HI3Q_HW_IDX_8814B)
+#define BIT_SET_P0HI3Q_HW_IDX_8814B(x, v)                                      \
+	(BIT_CLEAR_P0HI3Q_HW_IDX_8814B(x) | BIT_P0HI3Q_HW_IDX_8814B(v))
+
+#define BIT_SHIFT_P0HI3Q_HOST_IDX_8814B 0
+#define BIT_MASK_P0HI3Q_HOST_IDX_8814B 0xfff
+#define BIT_P0HI3Q_HOST_IDX_8814B(x)                                           \
+	(((x) & BIT_MASK_P0HI3Q_HOST_IDX_8814B)                                \
+	 << BIT_SHIFT_P0HI3Q_HOST_IDX_8814B)
+#define BITS_P0HI3Q_HOST_IDX_8814B                                             \
+	(BIT_MASK_P0HI3Q_HOST_IDX_8814B << BIT_SHIFT_P0HI3Q_HOST_IDX_8814B)
+#define BIT_CLEAR_P0HI3Q_HOST_IDX_8814B(x) ((x) & (~BITS_P0HI3Q_HOST_IDX_8814B))
+#define BIT_GET_P0HI3Q_HOST_IDX_8814B(x)                                       \
+	(((x) >> BIT_SHIFT_P0HI3Q_HOST_IDX_8814B) &                            \
+	 BIT_MASK_P0HI3Q_HOST_IDX_8814B)
+#define BIT_SET_P0HI3Q_HOST_IDX_8814B(x, v)                                    \
+	(BIT_CLEAR_P0HI3Q_HOST_IDX_8814B(x) | BIT_P0HI3Q_HOST_IDX_8814B(v))
+
+/* 2 REG_P0HI4Q_TXBD_IDX_8814B */
+
+#define BIT_SHIFT_P0HI4Q_HW_IDX_8814B 16
+#define BIT_MASK_P0HI4Q_HW_IDX_8814B 0xfff
+#define BIT_P0HI4Q_HW_IDX_8814B(x)                                             \
+	(((x) & BIT_MASK_P0HI4Q_HW_IDX_8814B) << BIT_SHIFT_P0HI4Q_HW_IDX_8814B)
+#define BITS_P0HI4Q_HW_IDX_8814B                                               \
+	(BIT_MASK_P0HI4Q_HW_IDX_8814B << BIT_SHIFT_P0HI4Q_HW_IDX_8814B)
+#define BIT_CLEAR_P0HI4Q_HW_IDX_8814B(x) ((x) & (~BITS_P0HI4Q_HW_IDX_8814B))
+#define BIT_GET_P0HI4Q_HW_IDX_8814B(x)                                         \
+	(((x) >> BIT_SHIFT_P0HI4Q_HW_IDX_8814B) & BIT_MASK_P0HI4Q_HW_IDX_8814B)
+#define BIT_SET_P0HI4Q_HW_IDX_8814B(x, v)                                      \
+	(BIT_CLEAR_P0HI4Q_HW_IDX_8814B(x) | BIT_P0HI4Q_HW_IDX_8814B(v))
+
+#define BIT_SHIFT_P0HI4Q_HOST_IDX_8814B 0
+#define BIT_MASK_P0HI4Q_HOST_IDX_8814B 0xfff
+#define BIT_P0HI4Q_HOST_IDX_8814B(x)                                           \
+	(((x) & BIT_MASK_P0HI4Q_HOST_IDX_8814B)                                \
+	 << BIT_SHIFT_P0HI4Q_HOST_IDX_8814B)
+#define BITS_P0HI4Q_HOST_IDX_8814B                                             \
+	(BIT_MASK_P0HI4Q_HOST_IDX_8814B << BIT_SHIFT_P0HI4Q_HOST_IDX_8814B)
+#define BIT_CLEAR_P0HI4Q_HOST_IDX_8814B(x) ((x) & (~BITS_P0HI4Q_HOST_IDX_8814B))
+#define BIT_GET_P0HI4Q_HOST_IDX_8814B(x)                                       \
+	(((x) >> BIT_SHIFT_P0HI4Q_HOST_IDX_8814B) &                            \
+	 BIT_MASK_P0HI4Q_HOST_IDX_8814B)
+#define BIT_SET_P0HI4Q_HOST_IDX_8814B(x, v)                                    \
+	(BIT_CLEAR_P0HI4Q_HOST_IDX_8814B(x) | BIT_P0HI4Q_HOST_IDX_8814B(v))
+
+/* 2 REG_P0HI5Q_TXBD_IDX_8814B */
+
+#define BIT_SHIFT_P0HI5Q_HW_IDX_8814B 16
+#define BIT_MASK_P0HI5Q_HW_IDX_8814B 0xfff
+#define BIT_P0HI5Q_HW_IDX_8814B(x)                                             \
+	(((x) & BIT_MASK_P0HI5Q_HW_IDX_8814B) << BIT_SHIFT_P0HI5Q_HW_IDX_8814B)
+#define BITS_P0HI5Q_HW_IDX_8814B                                               \
+	(BIT_MASK_P0HI5Q_HW_IDX_8814B << BIT_SHIFT_P0HI5Q_HW_IDX_8814B)
+#define BIT_CLEAR_P0HI5Q_HW_IDX_8814B(x) ((x) & (~BITS_P0HI5Q_HW_IDX_8814B))
+#define BIT_GET_P0HI5Q_HW_IDX_8814B(x)                                         \
+	(((x) >> BIT_SHIFT_P0HI5Q_HW_IDX_8814B) & BIT_MASK_P0HI5Q_HW_IDX_8814B)
+#define BIT_SET_P0HI5Q_HW_IDX_8814B(x, v)                                      \
+	(BIT_CLEAR_P0HI5Q_HW_IDX_8814B(x) | BIT_P0HI5Q_HW_IDX_8814B(v))
+
+#define BIT_SHIFT_P0HI5Q_HOST_IDX_8814B 0
+#define BIT_MASK_P0HI5Q_HOST_IDX_8814B 0xfff
+#define BIT_P0HI5Q_HOST_IDX_8814B(x)                                           \
+	(((x) & BIT_MASK_P0HI5Q_HOST_IDX_8814B)                                \
+	 << BIT_SHIFT_P0HI5Q_HOST_IDX_8814B)
+#define BITS_P0HI5Q_HOST_IDX_8814B                                             \
+	(BIT_MASK_P0HI5Q_HOST_IDX_8814B << BIT_SHIFT_P0HI5Q_HOST_IDX_8814B)
+#define BIT_CLEAR_P0HI5Q_HOST_IDX_8814B(x) ((x) & (~BITS_P0HI5Q_HOST_IDX_8814B))
+#define BIT_GET_P0HI5Q_HOST_IDX_8814B(x)                                       \
+	(((x) >> BIT_SHIFT_P0HI5Q_HOST_IDX_8814B) &                            \
+	 BIT_MASK_P0HI5Q_HOST_IDX_8814B)
+#define BIT_SET_P0HI5Q_HOST_IDX_8814B(x, v)                                    \
+	(BIT_CLEAR_P0HI5Q_HOST_IDX_8814B(x) | BIT_P0HI5Q_HOST_IDX_8814B(v))
+
+/* 2 REG_P0HI6Q_TXBD_IDX_8814B */
+
+#define BIT_SHIFT_P0HI6Q_HW_IDX_8814B 16
+#define BIT_MASK_P0HI6Q_HW_IDX_8814B 0xfff
+#define BIT_P0HI6Q_HW_IDX_8814B(x)                                             \
+	(((x) & BIT_MASK_P0HI6Q_HW_IDX_8814B) << BIT_SHIFT_P0HI6Q_HW_IDX_8814B)
+#define BITS_P0HI6Q_HW_IDX_8814B                                               \
+	(BIT_MASK_P0HI6Q_HW_IDX_8814B << BIT_SHIFT_P0HI6Q_HW_IDX_8814B)
+#define BIT_CLEAR_P0HI6Q_HW_IDX_8814B(x) ((x) & (~BITS_P0HI6Q_HW_IDX_8814B))
+#define BIT_GET_P0HI6Q_HW_IDX_8814B(x)                                         \
+	(((x) >> BIT_SHIFT_P0HI6Q_HW_IDX_8814B) & BIT_MASK_P0HI6Q_HW_IDX_8814B)
+#define BIT_SET_P0HI6Q_HW_IDX_8814B(x, v)                                      \
+	(BIT_CLEAR_P0HI6Q_HW_IDX_8814B(x) | BIT_P0HI6Q_HW_IDX_8814B(v))
+
+#define BIT_SHIFT_P0HI6Q_HOST_IDX_8814B 0
+#define BIT_MASK_P0HI6Q_HOST_IDX_8814B 0xfff
+#define BIT_P0HI6Q_HOST_IDX_8814B(x)                                           \
+	(((x) & BIT_MASK_P0HI6Q_HOST_IDX_8814B)                                \
+	 << BIT_SHIFT_P0HI6Q_HOST_IDX_8814B)
+#define BITS_P0HI6Q_HOST_IDX_8814B                                             \
+	(BIT_MASK_P0HI6Q_HOST_IDX_8814B << BIT_SHIFT_P0HI6Q_HOST_IDX_8814B)
+#define BIT_CLEAR_P0HI6Q_HOST_IDX_8814B(x) ((x) & (~BITS_P0HI6Q_HOST_IDX_8814B))
+#define BIT_GET_P0HI6Q_HOST_IDX_8814B(x)                                       \
+	(((x) >> BIT_SHIFT_P0HI6Q_HOST_IDX_8814B) &                            \
+	 BIT_MASK_P0HI6Q_HOST_IDX_8814B)
+#define BIT_SET_P0HI6Q_HOST_IDX_8814B(x, v)                                    \
+	(BIT_CLEAR_P0HI6Q_HOST_IDX_8814B(x) | BIT_P0HI6Q_HOST_IDX_8814B(v))
+
+/* 2 REG_P0HI7Q_TXBD_IDX_8814B */
+
+#define BIT_SHIFT_P0HI7Q_HW_IDX_8814B 16
+#define BIT_MASK_P0HI7Q_HW_IDX_8814B 0xfff
+#define BIT_P0HI7Q_HW_IDX_8814B(x)                                             \
+	(((x) & BIT_MASK_P0HI7Q_HW_IDX_8814B) << BIT_SHIFT_P0HI7Q_HW_IDX_8814B)
+#define BITS_P0HI7Q_HW_IDX_8814B                                               \
+	(BIT_MASK_P0HI7Q_HW_IDX_8814B << BIT_SHIFT_P0HI7Q_HW_IDX_8814B)
+#define BIT_CLEAR_P0HI7Q_HW_IDX_8814B(x) ((x) & (~BITS_P0HI7Q_HW_IDX_8814B))
+#define BIT_GET_P0HI7Q_HW_IDX_8814B(x)                                         \
+	(((x) >> BIT_SHIFT_P0HI7Q_HW_IDX_8814B) & BIT_MASK_P0HI7Q_HW_IDX_8814B)
+#define BIT_SET_P0HI7Q_HW_IDX_8814B(x, v)                                      \
+	(BIT_CLEAR_P0HI7Q_HW_IDX_8814B(x) | BIT_P0HI7Q_HW_IDX_8814B(v))
+
+#define BIT_SHIFT_P0HI7Q_HOST_IDX_8814B 0
+#define BIT_MASK_P0HI7Q_HOST_IDX_8814B 0xfff
+#define BIT_P0HI7Q_HOST_IDX_8814B(x)                                           \
+	(((x) & BIT_MASK_P0HI7Q_HOST_IDX_8814B)                                \
+	 << BIT_SHIFT_P0HI7Q_HOST_IDX_8814B)
+#define BITS_P0HI7Q_HOST_IDX_8814B                                             \
+	(BIT_MASK_P0HI7Q_HOST_IDX_8814B << BIT_SHIFT_P0HI7Q_HOST_IDX_8814B)
+#define BIT_CLEAR_P0HI7Q_HOST_IDX_8814B(x) ((x) & (~BITS_P0HI7Q_HOST_IDX_8814B))
+#define BIT_GET_P0HI7Q_HOST_IDX_8814B(x)                                       \
+	(((x) >> BIT_SHIFT_P0HI7Q_HOST_IDX_8814B) &                            \
+	 BIT_MASK_P0HI7Q_HOST_IDX_8814B)
+#define BIT_SET_P0HI7Q_HOST_IDX_8814B(x, v)                                    \
+	(BIT_CLEAR_P0HI7Q_HOST_IDX_8814B(x) | BIT_P0HI7Q_HOST_IDX_8814B(v))
+
+/* 2 REG_DBGSEL_PCIE_HRPWM1_HCPWM1_V1_8814B */
+#define BIT_DIS_TXDMA_PRE_V1_8814B BIT(31)
+#define BIT_DIS_RXDMA_PRE_V1_8814B BIT(30)
+
+#define BIT_SHIFT_HPS_CLKR_PCIE_V1_8814B 28
+#define BIT_MASK_HPS_CLKR_PCIE_V1_8814B 0x3
+#define BIT_HPS_CLKR_PCIE_V1_8814B(x)                                          \
+	(((x) & BIT_MASK_HPS_CLKR_PCIE_V1_8814B)                               \
+	 << BIT_SHIFT_HPS_CLKR_PCIE_V1_8814B)
+#define BITS_HPS_CLKR_PCIE_V1_8814B                                            \
+	(BIT_MASK_HPS_CLKR_PCIE_V1_8814B << BIT_SHIFT_HPS_CLKR_PCIE_V1_8814B)
+#define BIT_CLEAR_HPS_CLKR_PCIE_V1_8814B(x)                                    \
+	((x) & (~BITS_HPS_CLKR_PCIE_V1_8814B))
+#define BIT_GET_HPS_CLKR_PCIE_V1_8814B(x)                                      \
+	(((x) >> BIT_SHIFT_HPS_CLKR_PCIE_V1_8814B) &                           \
+	 BIT_MASK_HPS_CLKR_PCIE_V1_8814B)
+#define BIT_SET_HPS_CLKR_PCIE_V1_8814B(x, v)                                   \
+	(BIT_CLEAR_HPS_CLKR_PCIE_V1_8814B(x) | BIT_HPS_CLKR_PCIE_V1_8814B(v))
+
+#define BIT_PCIE_INT_V1_8814B BIT(27)
+#define BIT_TXFLAG_EXIT_L1_EN_V1_8814B BIT(26)
+#define BIT_EN_RXDMA_ALIGN_V2_8814B BIT(25)
+#define BIT_EN_TXDMA_ALIGN_V2_8814B BIT(24)
+
+#define BIT_SHIFT_PCIE_HCPWM_V1_8814B 16
+#define BIT_MASK_PCIE_HCPWM_V1_8814B 0xff
+#define BIT_PCIE_HCPWM_V1_8814B(x)                                             \
+	(((x) & BIT_MASK_PCIE_HCPWM_V1_8814B) << BIT_SHIFT_PCIE_HCPWM_V1_8814B)
+#define BITS_PCIE_HCPWM_V1_8814B                                               \
+	(BIT_MASK_PCIE_HCPWM_V1_8814B << BIT_SHIFT_PCIE_HCPWM_V1_8814B)
+#define BIT_CLEAR_PCIE_HCPWM_V1_8814B(x) ((x) & (~BITS_PCIE_HCPWM_V1_8814B))
+#define BIT_GET_PCIE_HCPWM_V1_8814B(x)                                         \
+	(((x) >> BIT_SHIFT_PCIE_HCPWM_V1_8814B) & BIT_MASK_PCIE_HCPWM_V1_8814B)
+#define BIT_SET_PCIE_HCPWM_V1_8814B(x, v)                                      \
+	(BIT_CLEAR_PCIE_HCPWM_V1_8814B(x) | BIT_PCIE_HCPWM_V1_8814B(v))
+
+#define BIT_SHIFT_PCIE_HRPWM_V1_8814B 8
+#define BIT_MASK_PCIE_HRPWM_V1_8814B 0xff
+#define BIT_PCIE_HRPWM_V1_8814B(x)                                             \
+	(((x) & BIT_MASK_PCIE_HRPWM_V1_8814B) << BIT_SHIFT_PCIE_HRPWM_V1_8814B)
+#define BITS_PCIE_HRPWM_V1_8814B                                               \
+	(BIT_MASK_PCIE_HRPWM_V1_8814B << BIT_SHIFT_PCIE_HRPWM_V1_8814B)
+#define BIT_CLEAR_PCIE_HRPWM_V1_8814B(x) ((x) & (~BITS_PCIE_HRPWM_V1_8814B))
+#define BIT_GET_PCIE_HRPWM_V1_8814B(x)                                         \
+	(((x) >> BIT_SHIFT_PCIE_HRPWM_V1_8814B) & BIT_MASK_PCIE_HRPWM_V1_8814B)
+#define BIT_SET_PCIE_HRPWM_V1_8814B(x, v)                                      \
+	(BIT_CLEAR_PCIE_HRPWM_V1_8814B(x) | BIT_PCIE_HRPWM_V1_8814B(v))
+
+#define BIT_SHIFT_DBG_SEL_8814B 0
+#define BIT_MASK_DBG_SEL_8814B 0xff
+#define BIT_DBG_SEL_8814B(x)                                                   \
+	(((x) & BIT_MASK_DBG_SEL_8814B) << BIT_SHIFT_DBG_SEL_8814B)
+#define BITS_DBG_SEL_8814B (BIT_MASK_DBG_SEL_8814B << BIT_SHIFT_DBG_SEL_8814B)
+#define BIT_CLEAR_DBG_SEL_8814B(x) ((x) & (~BITS_DBG_SEL_8814B))
+#define BIT_GET_DBG_SEL_8814B(x)                                               \
+	(((x) >> BIT_SHIFT_DBG_SEL_8814B) & BIT_MASK_DBG_SEL_8814B)
+#define BIT_SET_DBG_SEL_8814B(x, v)                                            \
+	(BIT_CLEAR_DBG_SEL_8814B(x) | BIT_DBG_SEL_8814B(v))
+
+/* 2 REG_PCIE_HRPWM2_HCPWM2_V1_8814B */
+
+#define BIT_SHIFT_PCIE_HCPWM2_V1_8814B 16
+#define BIT_MASK_PCIE_HCPWM2_V1_8814B 0xffff
+#define BIT_PCIE_HCPWM2_V1_8814B(x)                                            \
+	(((x) & BIT_MASK_PCIE_HCPWM2_V1_8814B)                                 \
+	 << BIT_SHIFT_PCIE_HCPWM2_V1_8814B)
+#define BITS_PCIE_HCPWM2_V1_8814B                                              \
+	(BIT_MASK_PCIE_HCPWM2_V1_8814B << BIT_SHIFT_PCIE_HCPWM2_V1_8814B)
+#define BIT_CLEAR_PCIE_HCPWM2_V1_8814B(x) ((x) & (~BITS_PCIE_HCPWM2_V1_8814B))
+#define BIT_GET_PCIE_HCPWM2_V1_8814B(x)                                        \
+	(((x) >> BIT_SHIFT_PCIE_HCPWM2_V1_8814B) &                             \
+	 BIT_MASK_PCIE_HCPWM2_V1_8814B)
+#define BIT_SET_PCIE_HCPWM2_V1_8814B(x, v)                                     \
+	(BIT_CLEAR_PCIE_HCPWM2_V1_8814B(x) | BIT_PCIE_HCPWM2_V1_8814B(v))
+
+#define BIT_SHIFT_PCIE_HRPWM2_8814B 0
+#define BIT_MASK_PCIE_HRPWM2_8814B 0xffff
+#define BIT_PCIE_HRPWM2_8814B(x)                                               \
+	(((x) & BIT_MASK_PCIE_HRPWM2_8814B) << BIT_SHIFT_PCIE_HRPWM2_8814B)
+#define BITS_PCIE_HRPWM2_8814B                                                 \
+	(BIT_MASK_PCIE_HRPWM2_8814B << BIT_SHIFT_PCIE_HRPWM2_8814B)
+#define BIT_CLEAR_PCIE_HRPWM2_8814B(x) ((x) & (~BITS_PCIE_HRPWM2_8814B))
+#define BIT_GET_PCIE_HRPWM2_8814B(x)                                           \
+	(((x) >> BIT_SHIFT_PCIE_HRPWM2_8814B) & BIT_MASK_PCIE_HRPWM2_8814B)
+#define BIT_SET_PCIE_HRPWM2_8814B(x, v)                                        \
+	(BIT_CLEAR_PCIE_HRPWM2_8814B(x) | BIT_PCIE_HRPWM2_8814B(v))
+
+/* 2 REG_PCIE_H2C_MSG_V1_8814B */
+
+#define BIT_SHIFT_DRV2FW_INFO_8814B 0
+#define BIT_MASK_DRV2FW_INFO_8814B 0xffffffffL
+#define BIT_DRV2FW_INFO_8814B(x)                                               \
+	(((x) & BIT_MASK_DRV2FW_INFO_8814B) << BIT_SHIFT_DRV2FW_INFO_8814B)
+#define BITS_DRV2FW_INFO_8814B                                                 \
+	(BIT_MASK_DRV2FW_INFO_8814B << BIT_SHIFT_DRV2FW_INFO_8814B)
+#define BIT_CLEAR_DRV2FW_INFO_8814B(x) ((x) & (~BITS_DRV2FW_INFO_8814B))
+#define BIT_GET_DRV2FW_INFO_8814B(x)                                           \
+	(((x) >> BIT_SHIFT_DRV2FW_INFO_8814B) & BIT_MASK_DRV2FW_INFO_8814B)
+#define BIT_SET_DRV2FW_INFO_8814B(x, v)                                        \
+	(BIT_CLEAR_DRV2FW_INFO_8814B(x) | BIT_DRV2FW_INFO_8814B(v))
+
+/* 2 REG_PCIE_C2H_MSG_V1_8814B */
+
+#define BIT_SHIFT_HCI_PCIE_C2H_MSG_8814B 0
+#define BIT_MASK_HCI_PCIE_C2H_MSG_8814B 0xffffffffL
+#define BIT_HCI_PCIE_C2H_MSG_8814B(x)                                          \
+	(((x) & BIT_MASK_HCI_PCIE_C2H_MSG_8814B)                               \
+	 << BIT_SHIFT_HCI_PCIE_C2H_MSG_8814B)
+#define BITS_HCI_PCIE_C2H_MSG_8814B                                            \
+	(BIT_MASK_HCI_PCIE_C2H_MSG_8814B << BIT_SHIFT_HCI_PCIE_C2H_MSG_8814B)
+#define BIT_CLEAR_HCI_PCIE_C2H_MSG_8814B(x)                                    \
+	((x) & (~BITS_HCI_PCIE_C2H_MSG_8814B))
+#define BIT_GET_HCI_PCIE_C2H_MSG_8814B(x)                                      \
+	(((x) >> BIT_SHIFT_HCI_PCIE_C2H_MSG_8814B) &                           \
+	 BIT_MASK_HCI_PCIE_C2H_MSG_8814B)
+#define BIT_SET_HCI_PCIE_C2H_MSG_8814B(x, v)                                   \
+	(BIT_CLEAR_HCI_PCIE_C2H_MSG_8814B(x) | BIT_HCI_PCIE_C2H_MSG_8814B(v))
+
+/* 2 REG_DBI_WDATA_V1_8814B */
+
+#define BIT_SHIFT_DBI_WDATA_8814B 0
+#define BIT_MASK_DBI_WDATA_8814B 0xffffffffL
+#define BIT_DBI_WDATA_8814B(x)                                                 \
+	(((x) & BIT_MASK_DBI_WDATA_8814B) << BIT_SHIFT_DBI_WDATA_8814B)
+#define BITS_DBI_WDATA_8814B                                                   \
+	(BIT_MASK_DBI_WDATA_8814B << BIT_SHIFT_DBI_WDATA_8814B)
+#define BIT_CLEAR_DBI_WDATA_8814B(x) ((x) & (~BITS_DBI_WDATA_8814B))
+#define BIT_GET_DBI_WDATA_8814B(x)                                             \
+	(((x) >> BIT_SHIFT_DBI_WDATA_8814B) & BIT_MASK_DBI_WDATA_8814B)
+#define BIT_SET_DBI_WDATA_8814B(x, v)                                          \
+	(BIT_CLEAR_DBI_WDATA_8814B(x) | BIT_DBI_WDATA_8814B(v))
+
+/* 2 REG_DBI_RDATA_V1_8814B */
+
+#define BIT_SHIFT_DBI_RDATA_8814B 0
+#define BIT_MASK_DBI_RDATA_8814B 0xffffffffL
+#define BIT_DBI_RDATA_8814B(x)                                                 \
+	(((x) & BIT_MASK_DBI_RDATA_8814B) << BIT_SHIFT_DBI_RDATA_8814B)
+#define BITS_DBI_RDATA_8814B                                                   \
+	(BIT_MASK_DBI_RDATA_8814B << BIT_SHIFT_DBI_RDATA_8814B)
+#define BIT_CLEAR_DBI_RDATA_8814B(x) ((x) & (~BITS_DBI_RDATA_8814B))
+#define BIT_GET_DBI_RDATA_8814B(x)                                             \
+	(((x) >> BIT_SHIFT_DBI_RDATA_8814B) & BIT_MASK_DBI_RDATA_8814B)
+#define BIT_SET_DBI_RDATA_8814B(x, v)                                          \
+	(BIT_CLEAR_DBI_RDATA_8814B(x) | BIT_DBI_RDATA_8814B(v))
+
+/* 2 REG_DBI_FLAG_V1_8814B */
+
+#define BIT_SHIFT_LOOPBACK_DBG_SEL_8814B 28
+#define BIT_MASK_LOOPBACK_DBG_SEL_8814B 0xf
+#define BIT_LOOPBACK_DBG_SEL_8814B(x)                                          \
+	(((x) & BIT_MASK_LOOPBACK_DBG_SEL_8814B)                               \
+	 << BIT_SHIFT_LOOPBACK_DBG_SEL_8814B)
+#define BITS_LOOPBACK_DBG_SEL_8814B                                            \
+	(BIT_MASK_LOOPBACK_DBG_SEL_8814B << BIT_SHIFT_LOOPBACK_DBG_SEL_8814B)
+#define BIT_CLEAR_LOOPBACK_DBG_SEL_8814B(x)                                    \
+	((x) & (~BITS_LOOPBACK_DBG_SEL_8814B))
+#define BIT_GET_LOOPBACK_DBG_SEL_8814B(x)                                      \
+	(((x) >> BIT_SHIFT_LOOPBACK_DBG_SEL_8814B) &                           \
+	 BIT_MASK_LOOPBACK_DBG_SEL_8814B)
+#define BIT_SET_LOOPBACK_DBG_SEL_8814B(x, v)                                   \
+	(BIT_CLEAR_LOOPBACK_DBG_SEL_8814B(x) | BIT_LOOPBACK_DBG_SEL_8814B(v))
+
+#define BIT_EN_STUCK_DBG_8814B BIT(26)
+#define BIT_RX_STUCK_8814B BIT(25)
+#define BIT_TX_STUCK_8814B BIT(24)
+#define BIT_DBI_RFLAG_8814B BIT(17)
+#define BIT_DBI_WFLAG_8814B BIT(16)
+
+#define BIT_SHIFT_DBI_WREN_8814B 12
+#define BIT_MASK_DBI_WREN_8814B 0xf
+#define BIT_DBI_WREN_8814B(x)                                                  \
+	(((x) & BIT_MASK_DBI_WREN_8814B) << BIT_SHIFT_DBI_WREN_8814B)
+#define BITS_DBI_WREN_8814B                                                    \
+	(BIT_MASK_DBI_WREN_8814B << BIT_SHIFT_DBI_WREN_8814B)
+#define BIT_CLEAR_DBI_WREN_8814B(x) ((x) & (~BITS_DBI_WREN_8814B))
+#define BIT_GET_DBI_WREN_8814B(x)                                              \
+	(((x) >> BIT_SHIFT_DBI_WREN_8814B) & BIT_MASK_DBI_WREN_8814B)
+#define BIT_SET_DBI_WREN_8814B(x, v)                                           \
+	(BIT_CLEAR_DBI_WREN_8814B(x) | BIT_DBI_WREN_8814B(v))
+
+#define BIT_SHIFT_DBI_ADDR_8814B 0
+#define BIT_MASK_DBI_ADDR_8814B 0xfff
+#define BIT_DBI_ADDR_8814B(x)                                                  \
+	(((x) & BIT_MASK_DBI_ADDR_8814B) << BIT_SHIFT_DBI_ADDR_8814B)
+#define BITS_DBI_ADDR_8814B                                                    \
+	(BIT_MASK_DBI_ADDR_8814B << BIT_SHIFT_DBI_ADDR_8814B)
+#define BIT_CLEAR_DBI_ADDR_8814B(x) ((x) & (~BITS_DBI_ADDR_8814B))
+#define BIT_GET_DBI_ADDR_8814B(x)                                              \
+	(((x) >> BIT_SHIFT_DBI_ADDR_8814B) & BIT_MASK_DBI_ADDR_8814B)
+#define BIT_SET_DBI_ADDR_8814B(x, v)                                           \
+	(BIT_CLEAR_DBI_ADDR_8814B(x) | BIT_DBI_ADDR_8814B(v))
+
+/* 2 REG_MDIO_V1_8814B */
+
+#define BIT_SHIFT_MDIO_RDATA_8814B 16
+#define BIT_MASK_MDIO_RDATA_8814B 0xffff
+#define BIT_MDIO_RDATA_8814B(x)                                                \
+	(((x) & BIT_MASK_MDIO_RDATA_8814B) << BIT_SHIFT_MDIO_RDATA_8814B)
+#define BITS_MDIO_RDATA_8814B                                                  \
+	(BIT_MASK_MDIO_RDATA_8814B << BIT_SHIFT_MDIO_RDATA_8814B)
+#define BIT_CLEAR_MDIO_RDATA_8814B(x) ((x) & (~BITS_MDIO_RDATA_8814B))
+#define BIT_GET_MDIO_RDATA_8814B(x)                                            \
+	(((x) >> BIT_SHIFT_MDIO_RDATA_8814B) & BIT_MASK_MDIO_RDATA_8814B)
+#define BIT_SET_MDIO_RDATA_8814B(x, v)                                         \
+	(BIT_CLEAR_MDIO_RDATA_8814B(x) | BIT_MDIO_RDATA_8814B(v))
+
+#define BIT_SHIFT_MDIO_WDATA_8814B 0
+#define BIT_MASK_MDIO_WDATA_8814B 0xffff
+#define BIT_MDIO_WDATA_8814B(x)                                                \
+	(((x) & BIT_MASK_MDIO_WDATA_8814B) << BIT_SHIFT_MDIO_WDATA_8814B)
+#define BITS_MDIO_WDATA_8814B                                                  \
+	(BIT_MASK_MDIO_WDATA_8814B << BIT_SHIFT_MDIO_WDATA_8814B)
+#define BIT_CLEAR_MDIO_WDATA_8814B(x) ((x) & (~BITS_MDIO_WDATA_8814B))
+#define BIT_GET_MDIO_WDATA_8814B(x)                                            \
+	(((x) >> BIT_SHIFT_MDIO_WDATA_8814B) & BIT_MASK_MDIO_WDATA_8814B)
+#define BIT_SET_MDIO_WDATA_8814B(x, v)                                         \
+	(BIT_CLEAR_MDIO_WDATA_8814B(x) | BIT_MDIO_WDATA_8814B(v))
+
+/* 2 REG_PCIE_MIX_CFG_8814B */
+
+#define BIT_SHIFT_MDIO_PHY_ADDR_8814B 24
+#define BIT_MASK_MDIO_PHY_ADDR_8814B 0x1f
+#define BIT_MDIO_PHY_ADDR_8814B(x)                                             \
+	(((x) & BIT_MASK_MDIO_PHY_ADDR_8814B) << BIT_SHIFT_MDIO_PHY_ADDR_8814B)
+#define BITS_MDIO_PHY_ADDR_8814B                                               \
+	(BIT_MASK_MDIO_PHY_ADDR_8814B << BIT_SHIFT_MDIO_PHY_ADDR_8814B)
+#define BIT_CLEAR_MDIO_PHY_ADDR_8814B(x) ((x) & (~BITS_MDIO_PHY_ADDR_8814B))
+#define BIT_GET_MDIO_PHY_ADDR_8814B(x)                                         \
+	(((x) >> BIT_SHIFT_MDIO_PHY_ADDR_8814B) & BIT_MASK_MDIO_PHY_ADDR_8814B)
+#define BIT_SET_MDIO_PHY_ADDR_8814B(x, v)                                      \
+	(BIT_CLEAR_MDIO_PHY_ADDR_8814B(x) | BIT_MDIO_PHY_ADDR_8814B(v))
+
+#define BIT_SHIFT_WATCH_DOG_RECORD_V1_8814B 10
+#define BIT_MASK_WATCH_DOG_RECORD_V1_8814B 0x3fff
+#define BIT_WATCH_DOG_RECORD_V1_8814B(x)                                       \
+	(((x) & BIT_MASK_WATCH_DOG_RECORD_V1_8814B)                            \
+	 << BIT_SHIFT_WATCH_DOG_RECORD_V1_8814B)
+#define BITS_WATCH_DOG_RECORD_V1_8814B                                         \
+	(BIT_MASK_WATCH_DOG_RECORD_V1_8814B                                    \
+	 << BIT_SHIFT_WATCH_DOG_RECORD_V1_8814B)
+#define BIT_CLEAR_WATCH_DOG_RECORD_V1_8814B(x)                                 \
+	((x) & (~BITS_WATCH_DOG_RECORD_V1_8814B))
+#define BIT_GET_WATCH_DOG_RECORD_V1_8814B(x)                                   \
+	(((x) >> BIT_SHIFT_WATCH_DOG_RECORD_V1_8814B) &                        \
+	 BIT_MASK_WATCH_DOG_RECORD_V1_8814B)
+#define BIT_SET_WATCH_DOG_RECORD_V1_8814B(x, v)                                \
+	(BIT_CLEAR_WATCH_DOG_RECORD_V1_8814B(x) |                              \
+	 BIT_WATCH_DOG_RECORD_V1_8814B(v))
+
+#define BIT_R_IO_TIMEOUT_FLAG_V1_8814B BIT(9)
+#define BIT_EN_WATCH_DOG_8814B BIT(8)
+#define BIT_ECRC_EN_8814B BIT(7)
+#define BIT_MDIO_RFLAG_8814B BIT(6)
+#define BIT_MDIO_WFLAG_8814B BIT(5)
+
+#define BIT_SHIFT_MDIO_REG_ADDR_8814B 0
+#define BIT_MASK_MDIO_REG_ADDR_8814B 0x1f
+#define BIT_MDIO_REG_ADDR_8814B(x)                                             \
+	(((x) & BIT_MASK_MDIO_REG_ADDR_8814B) << BIT_SHIFT_MDIO_REG_ADDR_8814B)
+#define BITS_MDIO_REG_ADDR_8814B                                               \
+	(BIT_MASK_MDIO_REG_ADDR_8814B << BIT_SHIFT_MDIO_REG_ADDR_8814B)
+#define BIT_CLEAR_MDIO_REG_ADDR_8814B(x) ((x) & (~BITS_MDIO_REG_ADDR_8814B))
+#define BIT_GET_MDIO_REG_ADDR_8814B(x)                                         \
+	(((x) >> BIT_SHIFT_MDIO_REG_ADDR_8814B) & BIT_MASK_MDIO_REG_ADDR_8814B)
+#define BIT_SET_MDIO_REG_ADDR_8814B(x, v)                                      \
+	(BIT_CLEAR_MDIO_REG_ADDR_8814B(x) | BIT_MDIO_REG_ADDR_8814B(v))
+
+/* 2 REG_HCI_MIX_CFG_8814B */
+#define BIT_EN_ALIGN_MTU_8814B BIT(23)
+
+#define BIT_SHIFT_LATENCY_CONTROL_8814B 21
+#define BIT_MASK_LATENCY_CONTROL_8814B 0x3
+#define BIT_LATENCY_CONTROL_8814B(x)                                           \
+	(((x) & BIT_MASK_LATENCY_CONTROL_8814B)                                \
+	 << BIT_SHIFT_LATENCY_CONTROL_8814B)
+#define BITS_LATENCY_CONTROL_8814B                                             \
+	(BIT_MASK_LATENCY_CONTROL_8814B << BIT_SHIFT_LATENCY_CONTROL_8814B)
+#define BIT_CLEAR_LATENCY_CONTROL_8814B(x) ((x) & (~BITS_LATENCY_CONTROL_8814B))
+#define BIT_GET_LATENCY_CONTROL_8814B(x)                                       \
+	(((x) >> BIT_SHIFT_LATENCY_CONTROL_8814B) &                            \
+	 BIT_MASK_LATENCY_CONTROL_8814B)
+#define BIT_SET_LATENCY_CONTROL_8814B(x, v)                                    \
+	(BIT_CLEAR_LATENCY_CONTROL_8814B(x) | BIT_LATENCY_CONTROL_8814B(v))
+
+#define BIT_HOST_GEN2_SUPPORT_8814B BIT(20)
+
+#define BIT_SHIFT_TXDMA_ERR_FLAG_V1_8814B 15
+#define BIT_MASK_TXDMA_ERR_FLAG_V1_8814B 0x1f
+#define BIT_TXDMA_ERR_FLAG_V1_8814B(x)                                         \
+	(((x) & BIT_MASK_TXDMA_ERR_FLAG_V1_8814B)                              \
+	 << BIT_SHIFT_TXDMA_ERR_FLAG_V1_8814B)
+#define BITS_TXDMA_ERR_FLAG_V1_8814B                                           \
+	(BIT_MASK_TXDMA_ERR_FLAG_V1_8814B << BIT_SHIFT_TXDMA_ERR_FLAG_V1_8814B)
+#define BIT_CLEAR_TXDMA_ERR_FLAG_V1_8814B(x)                                   \
+	((x) & (~BITS_TXDMA_ERR_FLAG_V1_8814B))
+#define BIT_GET_TXDMA_ERR_FLAG_V1_8814B(x)                                     \
+	(((x) >> BIT_SHIFT_TXDMA_ERR_FLAG_V1_8814B) &                          \
+	 BIT_MASK_TXDMA_ERR_FLAG_V1_8814B)
+#define BIT_SET_TXDMA_ERR_FLAG_V1_8814B(x, v)                                  \
+	(BIT_CLEAR_TXDMA_ERR_FLAG_V1_8814B(x) | BIT_TXDMA_ERR_FLAG_V1_8814B(v))
+
+#define BIT_EPHY_RX50_EN_8814B BIT(11)
+
+#define BIT_SHIFT_MSI_TIMEOUT_ID_V1_8814B 8
+#define BIT_MASK_MSI_TIMEOUT_ID_V1_8814B 0x7
+#define BIT_MSI_TIMEOUT_ID_V1_8814B(x)                                         \
+	(((x) & BIT_MASK_MSI_TIMEOUT_ID_V1_8814B)                              \
+	 << BIT_SHIFT_MSI_TIMEOUT_ID_V1_8814B)
+#define BITS_MSI_TIMEOUT_ID_V1_8814B                                           \
+	(BIT_MASK_MSI_TIMEOUT_ID_V1_8814B << BIT_SHIFT_MSI_TIMEOUT_ID_V1_8814B)
+#define BIT_CLEAR_MSI_TIMEOUT_ID_V1_8814B(x)                                   \
+	((x) & (~BITS_MSI_TIMEOUT_ID_V1_8814B))
+#define BIT_GET_MSI_TIMEOUT_ID_V1_8814B(x)                                     \
+	(((x) >> BIT_SHIFT_MSI_TIMEOUT_ID_V1_8814B) &                          \
+	 BIT_MASK_MSI_TIMEOUT_ID_V1_8814B)
+#define BIT_SET_MSI_TIMEOUT_ID_V1_8814B(x, v)                                  \
+	(BIT_CLEAR_MSI_TIMEOUT_ID_V1_8814B(x) | BIT_MSI_TIMEOUT_ID_V1_8814B(v))
+
+#define BIT_RADDR_RD_8814B BIT(7)
+#define BIT_L0S_LINK_OFF_8814B BIT(4)
+#define BIT_ACT_LINK_OFF_8814B BIT(3)
+#define BIT_EN_SLOW_MAC_TX_8814B BIT(2)
+#define BIT_EN_SLOW_MAC_RX_8814B BIT(1)
+#define BIT_EN_SLOW_MAC_HW_8814B BIT(0)
+
+/* 2 REG_STC_INT_CS_8814B(PCIE STATE CHANGE INTERRUPT CONTROL AND STATUS) */
+#define BIT_STC_INT_EN_8814B BIT(31)
+
+#define BIT_SHIFT_STC_INT_FLAG_8814B 16
+#define BIT_MASK_STC_INT_FLAG_8814B 0xff
+#define BIT_STC_INT_FLAG_8814B(x)                                              \
+	(((x) & BIT_MASK_STC_INT_FLAG_8814B) << BIT_SHIFT_STC_INT_FLAG_8814B)
+#define BITS_STC_INT_FLAG_8814B                                                \
+	(BIT_MASK_STC_INT_FLAG_8814B << BIT_SHIFT_STC_INT_FLAG_8814B)
+#define BIT_CLEAR_STC_INT_FLAG_8814B(x) ((x) & (~BITS_STC_INT_FLAG_8814B))
+#define BIT_GET_STC_INT_FLAG_8814B(x)                                          \
+	(((x) >> BIT_SHIFT_STC_INT_FLAG_8814B) & BIT_MASK_STC_INT_FLAG_8814B)
+#define BIT_SET_STC_INT_FLAG_8814B(x, v)                                       \
+	(BIT_CLEAR_STC_INT_FLAG_8814B(x) | BIT_STC_INT_FLAG_8814B(v))
+
+#define BIT_SHIFT_STC_INT_IDX_8814B 8
+#define BIT_MASK_STC_INT_IDX_8814B 0x7
+#define BIT_STC_INT_IDX_8814B(x)                                               \
+	(((x) & BIT_MASK_STC_INT_IDX_8814B) << BIT_SHIFT_STC_INT_IDX_8814B)
+#define BITS_STC_INT_IDX_8814B                                                 \
+	(BIT_MASK_STC_INT_IDX_8814B << BIT_SHIFT_STC_INT_IDX_8814B)
+#define BIT_CLEAR_STC_INT_IDX_8814B(x) ((x) & (~BITS_STC_INT_IDX_8814B))
+#define BIT_GET_STC_INT_IDX_8814B(x)                                           \
+	(((x) >> BIT_SHIFT_STC_INT_IDX_8814B) & BIT_MASK_STC_INT_IDX_8814B)
+#define BIT_SET_STC_INT_IDX_8814B(x, v)                                        \
+	(BIT_CLEAR_STC_INT_IDX_8814B(x) | BIT_STC_INT_IDX_8814B(v))
+
+#define BIT_SHIFT_STC_INT_REALTIME_CS_8814B 0
+#define BIT_MASK_STC_INT_REALTIME_CS_8814B 0x3f
+#define BIT_STC_INT_REALTIME_CS_8814B(x)                                       \
+	(((x) & BIT_MASK_STC_INT_REALTIME_CS_8814B)                            \
+	 << BIT_SHIFT_STC_INT_REALTIME_CS_8814B)
+#define BITS_STC_INT_REALTIME_CS_8814B                                         \
+	(BIT_MASK_STC_INT_REALTIME_CS_8814B                                    \
+	 << BIT_SHIFT_STC_INT_REALTIME_CS_8814B)
+#define BIT_CLEAR_STC_INT_REALTIME_CS_8814B(x)                                 \
+	((x) & (~BITS_STC_INT_REALTIME_CS_8814B))
+#define BIT_GET_STC_INT_REALTIME_CS_8814B(x)                                   \
+	(((x) >> BIT_SHIFT_STC_INT_REALTIME_CS_8814B) &                        \
+	 BIT_MASK_STC_INT_REALTIME_CS_8814B)
+#define BIT_SET_STC_INT_REALTIME_CS_8814B(x, v)                                \
+	(BIT_CLEAR_STC_INT_REALTIME_CS_8814B(x) |                              \
+	 BIT_STC_INT_REALTIME_CS_8814B(v))
+
+/* 2 REG_ST_INT_CFG_8814B(PCIE STATE CHANGE INTERRUPT CONFIGURATION) */
+#define BIT_STC_INT_GRP_EN_8814B BIT(31)
+
+#define BIT_SHIFT_STC_INT_EXPECT_LS_8814B 8
+#define BIT_MASK_STC_INT_EXPECT_LS_8814B 0x3f
+#define BIT_STC_INT_EXPECT_LS_8814B(x)                                         \
+	(((x) & BIT_MASK_STC_INT_EXPECT_LS_8814B)                              \
+	 << BIT_SHIFT_STC_INT_EXPECT_LS_8814B)
+#define BITS_STC_INT_EXPECT_LS_8814B                                           \
+	(BIT_MASK_STC_INT_EXPECT_LS_8814B << BIT_SHIFT_STC_INT_EXPECT_LS_8814B)
+#define BIT_CLEAR_STC_INT_EXPECT_LS_8814B(x)                                   \
+	((x) & (~BITS_STC_INT_EXPECT_LS_8814B))
+#define BIT_GET_STC_INT_EXPECT_LS_8814B(x)                                     \
+	(((x) >> BIT_SHIFT_STC_INT_EXPECT_LS_8814B) &                          \
+	 BIT_MASK_STC_INT_EXPECT_LS_8814B)
+#define BIT_SET_STC_INT_EXPECT_LS_8814B(x, v)                                  \
+	(BIT_CLEAR_STC_INT_EXPECT_LS_8814B(x) | BIT_STC_INT_EXPECT_LS_8814B(v))
+
+/* 2 REG_NOT_VALID_8814B */
+
+#define BIT_SHIFT_STC_INT_EXPECT_CS_8814B 0
+#define BIT_MASK_STC_INT_EXPECT_CS_8814B 0x3f
+#define BIT_STC_INT_EXPECT_CS_8814B(x)                                         \
+	(((x) & BIT_MASK_STC_INT_EXPECT_CS_8814B)                              \
+	 << BIT_SHIFT_STC_INT_EXPECT_CS_8814B)
+#define BITS_STC_INT_EXPECT_CS_8814B                                           \
+	(BIT_MASK_STC_INT_EXPECT_CS_8814B << BIT_SHIFT_STC_INT_EXPECT_CS_8814B)
+#define BIT_CLEAR_STC_INT_EXPECT_CS_8814B(x)                                   \
+	((x) & (~BITS_STC_INT_EXPECT_CS_8814B))
+#define BIT_GET_STC_INT_EXPECT_CS_8814B(x)                                     \
+	(((x) >> BIT_SHIFT_STC_INT_EXPECT_CS_8814B) &                          \
+	 BIT_MASK_STC_INT_EXPECT_CS_8814B)
+#define BIT_SET_STC_INT_EXPECT_CS_8814B(x, v)                                  \
+	(BIT_CLEAR_STC_INT_EXPECT_CS_8814B(x) | BIT_STC_INT_EXPECT_CS_8814B(v))
+
+/* 2 REG_ACH4_ACH5_TXBD_NUM_8814B */
+#define BIT_PCIE_ACH5_FLAG_8814B BIT(30)
+
+#define BIT_SHIFT_ACH5_DESC_MODE_8814B 28
+#define BIT_MASK_ACH5_DESC_MODE_8814B 0x3
+#define BIT_ACH5_DESC_MODE_8814B(x)                                            \
+	(((x) & BIT_MASK_ACH5_DESC_MODE_8814B)                                 \
+	 << BIT_SHIFT_ACH5_DESC_MODE_8814B)
+#define BITS_ACH5_DESC_MODE_8814B                                              \
+	(BIT_MASK_ACH5_DESC_MODE_8814B << BIT_SHIFT_ACH5_DESC_MODE_8814B)
+#define BIT_CLEAR_ACH5_DESC_MODE_8814B(x) ((x) & (~BITS_ACH5_DESC_MODE_8814B))
+#define BIT_GET_ACH5_DESC_MODE_8814B(x)                                        \
+	(((x) >> BIT_SHIFT_ACH5_DESC_MODE_8814B) &                             \
+	 BIT_MASK_ACH5_DESC_MODE_8814B)
+#define BIT_SET_ACH5_DESC_MODE_8814B(x, v)                                     \
+	(BIT_CLEAR_ACH5_DESC_MODE_8814B(x) | BIT_ACH5_DESC_MODE_8814B(v))
+
+#define BIT_SHIFT_ACH5_DESC_NUM_8814B 16
+#define BIT_MASK_ACH5_DESC_NUM_8814B 0xfff
+#define BIT_ACH5_DESC_NUM_8814B(x)                                             \
+	(((x) & BIT_MASK_ACH5_DESC_NUM_8814B) << BIT_SHIFT_ACH5_DESC_NUM_8814B)
+#define BITS_ACH5_DESC_NUM_8814B                                               \
+	(BIT_MASK_ACH5_DESC_NUM_8814B << BIT_SHIFT_ACH5_DESC_NUM_8814B)
+#define BIT_CLEAR_ACH5_DESC_NUM_8814B(x) ((x) & (~BITS_ACH5_DESC_NUM_8814B))
+#define BIT_GET_ACH5_DESC_NUM_8814B(x)                                         \
+	(((x) >> BIT_SHIFT_ACH5_DESC_NUM_8814B) & BIT_MASK_ACH5_DESC_NUM_8814B)
+#define BIT_SET_ACH5_DESC_NUM_8814B(x, v)                                      \
+	(BIT_CLEAR_ACH5_DESC_NUM_8814B(x) | BIT_ACH5_DESC_NUM_8814B(v))
+
+#define BIT_PCIE_ACH4_FLAG_8814B BIT(14)
+
+#define BIT_SHIFT_ACH4_DESC_MODE_8814B 12
+#define BIT_MASK_ACH4_DESC_MODE_8814B 0x3
+#define BIT_ACH4_DESC_MODE_8814B(x)                                            \
+	(((x) & BIT_MASK_ACH4_DESC_MODE_8814B)                                 \
+	 << BIT_SHIFT_ACH4_DESC_MODE_8814B)
+#define BITS_ACH4_DESC_MODE_8814B                                              \
+	(BIT_MASK_ACH4_DESC_MODE_8814B << BIT_SHIFT_ACH4_DESC_MODE_8814B)
+#define BIT_CLEAR_ACH4_DESC_MODE_8814B(x) ((x) & (~BITS_ACH4_DESC_MODE_8814B))
+#define BIT_GET_ACH4_DESC_MODE_8814B(x)                                        \
+	(((x) >> BIT_SHIFT_ACH4_DESC_MODE_8814B) &                             \
+	 BIT_MASK_ACH4_DESC_MODE_8814B)
+#define BIT_SET_ACH4_DESC_MODE_8814B(x, v)                                     \
+	(BIT_CLEAR_ACH4_DESC_MODE_8814B(x) | BIT_ACH4_DESC_MODE_8814B(v))
+
+#define BIT_SHIFT_ACH4_DESC_NUM_8814B 0
+#define BIT_MASK_ACH4_DESC_NUM_8814B 0xfff
+#define BIT_ACH4_DESC_NUM_8814B(x)                                             \
+	(((x) & BIT_MASK_ACH4_DESC_NUM_8814B) << BIT_SHIFT_ACH4_DESC_NUM_8814B)
+#define BITS_ACH4_DESC_NUM_8814B                                               \
+	(BIT_MASK_ACH4_DESC_NUM_8814B << BIT_SHIFT_ACH4_DESC_NUM_8814B)
+#define BIT_CLEAR_ACH4_DESC_NUM_8814B(x) ((x) & (~BITS_ACH4_DESC_NUM_8814B))
+#define BIT_GET_ACH4_DESC_NUM_8814B(x)                                         \
+	(((x) >> BIT_SHIFT_ACH4_DESC_NUM_8814B) & BIT_MASK_ACH4_DESC_NUM_8814B)
+#define BIT_SET_ACH4_DESC_NUM_8814B(x, v)                                      \
+	(BIT_CLEAR_ACH4_DESC_NUM_8814B(x) | BIT_ACH4_DESC_NUM_8814B(v))
+
+/* 2 REG_FWCMDQ_TXBD_IDX_8814B */
+
+#define BIT_SHIFT_FWCMDQ_HW_IDX_8814B 16
+#define BIT_MASK_FWCMDQ_HW_IDX_8814B 0xfff
+#define BIT_FWCMDQ_HW_IDX_8814B(x)                                             \
+	(((x) & BIT_MASK_FWCMDQ_HW_IDX_8814B) << BIT_SHIFT_FWCMDQ_HW_IDX_8814B)
+#define BITS_FWCMDQ_HW_IDX_8814B                                               \
+	(BIT_MASK_FWCMDQ_HW_IDX_8814B << BIT_SHIFT_FWCMDQ_HW_IDX_8814B)
+#define BIT_CLEAR_FWCMDQ_HW_IDX_8814B(x) ((x) & (~BITS_FWCMDQ_HW_IDX_8814B))
+#define BIT_GET_FWCMDQ_HW_IDX_8814B(x)                                         \
+	(((x) >> BIT_SHIFT_FWCMDQ_HW_IDX_8814B) & BIT_MASK_FWCMDQ_HW_IDX_8814B)
+#define BIT_SET_FWCMDQ_HW_IDX_8814B(x, v)                                      \
+	(BIT_CLEAR_FWCMDQ_HW_IDX_8814B(x) | BIT_FWCMDQ_HW_IDX_8814B(v))
+
+#define BIT_SHIFT_FWCMDQ_HOST_IDX_8814B 0
+#define BIT_MASK_FWCMDQ_HOST_IDX_8814B 0xfff
+#define BIT_FWCMDQ_HOST_IDX_8814B(x)                                           \
+	(((x) & BIT_MASK_FWCMDQ_HOST_IDX_8814B)                                \
+	 << BIT_SHIFT_FWCMDQ_HOST_IDX_8814B)
+#define BITS_FWCMDQ_HOST_IDX_8814B                                             \
+	(BIT_MASK_FWCMDQ_HOST_IDX_8814B << BIT_SHIFT_FWCMDQ_HOST_IDX_8814B)
+#define BIT_CLEAR_FWCMDQ_HOST_IDX_8814B(x) ((x) & (~BITS_FWCMDQ_HOST_IDX_8814B))
+#define BIT_GET_FWCMDQ_HOST_IDX_8814B(x)                                       \
+	(((x) >> BIT_SHIFT_FWCMDQ_HOST_IDX_8814B) &                            \
+	 BIT_MASK_FWCMDQ_HOST_IDX_8814B)
+#define BIT_SET_FWCMDQ_HOST_IDX_8814B(x, v)                                    \
+	(BIT_CLEAR_FWCMDQ_HOST_IDX_8814B(x) | BIT_FWCMDQ_HOST_IDX_8814B(v))
+
+/* 2 REG_P0HI8Q_TXBD_IDX_8814B */
+
+#define BIT_SHIFT_P0HI8Q_HW_IDX_8814B 16
+#define BIT_MASK_P0HI8Q_HW_IDX_8814B 0xfff
+#define BIT_P0HI8Q_HW_IDX_8814B(x)                                             \
+	(((x) & BIT_MASK_P0HI8Q_HW_IDX_8814B) << BIT_SHIFT_P0HI8Q_HW_IDX_8814B)
+#define BITS_P0HI8Q_HW_IDX_8814B                                               \
+	(BIT_MASK_P0HI8Q_HW_IDX_8814B << BIT_SHIFT_P0HI8Q_HW_IDX_8814B)
+#define BIT_CLEAR_P0HI8Q_HW_IDX_8814B(x) ((x) & (~BITS_P0HI8Q_HW_IDX_8814B))
+#define BIT_GET_P0HI8Q_HW_IDX_8814B(x)                                         \
+	(((x) >> BIT_SHIFT_P0HI8Q_HW_IDX_8814B) & BIT_MASK_P0HI8Q_HW_IDX_8814B)
+#define BIT_SET_P0HI8Q_HW_IDX_8814B(x, v)                                      \
+	(BIT_CLEAR_P0HI8Q_HW_IDX_8814B(x) | BIT_P0HI8Q_HW_IDX_8814B(v))
+
+#define BIT_SHIFT_P0HI8Q_HOST_IDX_8814B 0
+#define BIT_MASK_P0HI8Q_HOST_IDX_8814B 0xfff
+#define BIT_P0HI8Q_HOST_IDX_8814B(x)                                           \
+	(((x) & BIT_MASK_P0HI8Q_HOST_IDX_8814B)                                \
+	 << BIT_SHIFT_P0HI8Q_HOST_IDX_8814B)
+#define BITS_P0HI8Q_HOST_IDX_8814B                                             \
+	(BIT_MASK_P0HI8Q_HOST_IDX_8814B << BIT_SHIFT_P0HI8Q_HOST_IDX_8814B)
+#define BIT_CLEAR_P0HI8Q_HOST_IDX_8814B(x) ((x) & (~BITS_P0HI8Q_HOST_IDX_8814B))
+#define BIT_GET_P0HI8Q_HOST_IDX_8814B(x)                                       \
+	(((x) >> BIT_SHIFT_P0HI8Q_HOST_IDX_8814B) &                            \
+	 BIT_MASK_P0HI8Q_HOST_IDX_8814B)
+#define BIT_SET_P0HI8Q_HOST_IDX_8814B(x, v)                                    \
+	(BIT_CLEAR_P0HI8Q_HOST_IDX_8814B(x) | BIT_P0HI8Q_HOST_IDX_8814B(v))
+
+/* 2 REG_H2CQ_TXBD_DESA_L_8814B */
+
+#define BIT_SHIFT_H2CQ_TXBD_DESA_L_8814B 0
+#define BIT_MASK_H2CQ_TXBD_DESA_L_8814B 0xffffffffL
+#define BIT_H2CQ_TXBD_DESA_L_8814B(x)                                          \
+	(((x) & BIT_MASK_H2CQ_TXBD_DESA_L_8814B)                               \
+	 << BIT_SHIFT_H2CQ_TXBD_DESA_L_8814B)
+#define BITS_H2CQ_TXBD_DESA_L_8814B                                            \
+	(BIT_MASK_H2CQ_TXBD_DESA_L_8814B << BIT_SHIFT_H2CQ_TXBD_DESA_L_8814B)
+#define BIT_CLEAR_H2CQ_TXBD_DESA_L_8814B(x)                                    \
+	((x) & (~BITS_H2CQ_TXBD_DESA_L_8814B))
+#define BIT_GET_H2CQ_TXBD_DESA_L_8814B(x)                                      \
+	(((x) >> BIT_SHIFT_H2CQ_TXBD_DESA_L_8814B) &                           \
+	 BIT_MASK_H2CQ_TXBD_DESA_L_8814B)
+#define BIT_SET_H2CQ_TXBD_DESA_L_8814B(x, v)                                   \
+	(BIT_CLEAR_H2CQ_TXBD_DESA_L_8814B(x) | BIT_H2CQ_TXBD_DESA_L_8814B(v))
+
+/* 2 REG_H2CQ_TXBD_DESA_H_8814B */
+
+#define BIT_SHIFT_H2CQ_TXBD_DESA_H_8814B 0
+#define BIT_MASK_H2CQ_TXBD_DESA_H_8814B 0xffffffffL
+#define BIT_H2CQ_TXBD_DESA_H_8814B(x)                                          \
+	(((x) & BIT_MASK_H2CQ_TXBD_DESA_H_8814B)                               \
+	 << BIT_SHIFT_H2CQ_TXBD_DESA_H_8814B)
+#define BITS_H2CQ_TXBD_DESA_H_8814B                                            \
+	(BIT_MASK_H2CQ_TXBD_DESA_H_8814B << BIT_SHIFT_H2CQ_TXBD_DESA_H_8814B)
+#define BIT_CLEAR_H2CQ_TXBD_DESA_H_8814B(x)                                    \
+	((x) & (~BITS_H2CQ_TXBD_DESA_H_8814B))
+#define BIT_GET_H2CQ_TXBD_DESA_H_8814B(x)                                      \
+	(((x) >> BIT_SHIFT_H2CQ_TXBD_DESA_H_8814B) &                           \
+	 BIT_MASK_H2CQ_TXBD_DESA_H_8814B)
+#define BIT_SET_H2CQ_TXBD_DESA_H_8814B(x, v)                                   \
+	(BIT_CLEAR_H2CQ_TXBD_DESA_H_8814B(x) | BIT_H2CQ_TXBD_DESA_H_8814B(v))
+
+/* 2 REG_H2CQ_TXBD_NUM_8814B */
+#define BIT_PCIE_H2CQ_FLAG_8814B BIT(14)
+
+#define BIT_SHIFT_H2CQ_DESC_MODE_8814B 12
+#define BIT_MASK_H2CQ_DESC_MODE_8814B 0x3
+#define BIT_H2CQ_DESC_MODE_8814B(x)                                            \
+	(((x) & BIT_MASK_H2CQ_DESC_MODE_8814B)                                 \
+	 << BIT_SHIFT_H2CQ_DESC_MODE_8814B)
+#define BITS_H2CQ_DESC_MODE_8814B                                              \
+	(BIT_MASK_H2CQ_DESC_MODE_8814B << BIT_SHIFT_H2CQ_DESC_MODE_8814B)
+#define BIT_CLEAR_H2CQ_DESC_MODE_8814B(x) ((x) & (~BITS_H2CQ_DESC_MODE_8814B))
+#define BIT_GET_H2CQ_DESC_MODE_8814B(x)                                        \
+	(((x) >> BIT_SHIFT_H2CQ_DESC_MODE_8814B) &                             \
+	 BIT_MASK_H2CQ_DESC_MODE_8814B)
+#define BIT_SET_H2CQ_DESC_MODE_8814B(x, v)                                     \
+	(BIT_CLEAR_H2CQ_DESC_MODE_8814B(x) | BIT_H2CQ_DESC_MODE_8814B(v))
+
+#define BIT_SHIFT_H2CQ_DESC_NUM_8814B 0
+#define BIT_MASK_H2CQ_DESC_NUM_8814B 0xfff
+#define BIT_H2CQ_DESC_NUM_8814B(x)                                             \
+	(((x) & BIT_MASK_H2CQ_DESC_NUM_8814B) << BIT_SHIFT_H2CQ_DESC_NUM_8814B)
+#define BITS_H2CQ_DESC_NUM_8814B                                               \
+	(BIT_MASK_H2CQ_DESC_NUM_8814B << BIT_SHIFT_H2CQ_DESC_NUM_8814B)
+#define BIT_CLEAR_H2CQ_DESC_NUM_8814B(x) ((x) & (~BITS_H2CQ_DESC_NUM_8814B))
+#define BIT_GET_H2CQ_DESC_NUM_8814B(x)                                         \
+	(((x) >> BIT_SHIFT_H2CQ_DESC_NUM_8814B) & BIT_MASK_H2CQ_DESC_NUM_8814B)
+#define BIT_SET_H2CQ_DESC_NUM_8814B(x, v)                                      \
+	(BIT_CLEAR_H2CQ_DESC_NUM_8814B(x) | BIT_H2CQ_DESC_NUM_8814B(v))
+
+/* 2 REG_H2CQ_TXBD_IDX_8814B */
+
+#define BIT_SHIFT_H2CQ_HW_IDX_8814B 16
+#define BIT_MASK_H2CQ_HW_IDX_8814B 0xfff
+#define BIT_H2CQ_HW_IDX_8814B(x)                                               \
+	(((x) & BIT_MASK_H2CQ_HW_IDX_8814B) << BIT_SHIFT_H2CQ_HW_IDX_8814B)
+#define BITS_H2CQ_HW_IDX_8814B                                                 \
+	(BIT_MASK_H2CQ_HW_IDX_8814B << BIT_SHIFT_H2CQ_HW_IDX_8814B)
+#define BIT_CLEAR_H2CQ_HW_IDX_8814B(x) ((x) & (~BITS_H2CQ_HW_IDX_8814B))
+#define BIT_GET_H2CQ_HW_IDX_8814B(x)                                           \
+	(((x) >> BIT_SHIFT_H2CQ_HW_IDX_8814B) & BIT_MASK_H2CQ_HW_IDX_8814B)
+#define BIT_SET_H2CQ_HW_IDX_8814B(x, v)                                        \
+	(BIT_CLEAR_H2CQ_HW_IDX_8814B(x) | BIT_H2CQ_HW_IDX_8814B(v))
+
+#define BIT_SHIFT_H2CQ_HOST_IDX_8814B 0
+#define BIT_MASK_H2CQ_HOST_IDX_8814B 0xfff
+#define BIT_H2CQ_HOST_IDX_8814B(x)                                             \
+	(((x) & BIT_MASK_H2CQ_HOST_IDX_8814B) << BIT_SHIFT_H2CQ_HOST_IDX_8814B)
+#define BITS_H2CQ_HOST_IDX_8814B                                               \
+	(BIT_MASK_H2CQ_HOST_IDX_8814B << BIT_SHIFT_H2CQ_HOST_IDX_8814B)
+#define BIT_CLEAR_H2CQ_HOST_IDX_8814B(x) ((x) & (~BITS_H2CQ_HOST_IDX_8814B))
+#define BIT_GET_H2CQ_HOST_IDX_8814B(x)                                         \
+	(((x) >> BIT_SHIFT_H2CQ_HOST_IDX_8814B) & BIT_MASK_H2CQ_HOST_IDX_8814B)
+#define BIT_SET_H2CQ_HOST_IDX_8814B(x, v)                                      \
+	(BIT_CLEAR_H2CQ_HOST_IDX_8814B(x) | BIT_H2CQ_HOST_IDX_8814B(v))
+
+/* 2 REG_H2CQ_CSR_8814B[31:0] (H2CQ CONTROL AND STATUS) */
+#define BIT_H2CQ_FULL_8814B BIT(31)
+#define BIT_CLR_H2CQ_HOST_IDX_8814B BIT(16)
+#define BIT_CLR_H2CQ_HW_IDX_8814B BIT(8)
+#define BIT_STOP_H2CQ_8814B BIT(0)
+
+/* 2 REG_P0HI9Q_TXBD_IDX_8814B */
+
+#define BIT_SHIFT_P0HI9Q_HW_IDX_8814B 16
+#define BIT_MASK_P0HI9Q_HW_IDX_8814B 0xfff
+#define BIT_P0HI9Q_HW_IDX_8814B(x)                                             \
+	(((x) & BIT_MASK_P0HI9Q_HW_IDX_8814B) << BIT_SHIFT_P0HI9Q_HW_IDX_8814B)
+#define BITS_P0HI9Q_HW_IDX_8814B                                               \
+	(BIT_MASK_P0HI9Q_HW_IDX_8814B << BIT_SHIFT_P0HI9Q_HW_IDX_8814B)
+#define BIT_CLEAR_P0HI9Q_HW_IDX_8814B(x) ((x) & (~BITS_P0HI9Q_HW_IDX_8814B))
+#define BIT_GET_P0HI9Q_HW_IDX_8814B(x)                                         \
+	(((x) >> BIT_SHIFT_P0HI9Q_HW_IDX_8814B) & BIT_MASK_P0HI9Q_HW_IDX_8814B)
+#define BIT_SET_P0HI9Q_HW_IDX_8814B(x, v)                                      \
+	(BIT_CLEAR_P0HI9Q_HW_IDX_8814B(x) | BIT_P0HI9Q_HW_IDX_8814B(v))
+
+#define BIT_SHIFT_P0HI9Q_HOST_IDX_8814B 0
+#define BIT_MASK_P0HI9Q_HOST_IDX_8814B 0xfff
+#define BIT_P0HI9Q_HOST_IDX_8814B(x)                                           \
+	(((x) & BIT_MASK_P0HI9Q_HOST_IDX_8814B)                                \
+	 << BIT_SHIFT_P0HI9Q_HOST_IDX_8814B)
+#define BITS_P0HI9Q_HOST_IDX_8814B                                             \
+	(BIT_MASK_P0HI9Q_HOST_IDX_8814B << BIT_SHIFT_P0HI9Q_HOST_IDX_8814B)
+#define BIT_CLEAR_P0HI9Q_HOST_IDX_8814B(x) ((x) & (~BITS_P0HI9Q_HOST_IDX_8814B))
+#define BIT_GET_P0HI9Q_HOST_IDX_8814B(x)                                       \
+	(((x) >> BIT_SHIFT_P0HI9Q_HOST_IDX_8814B) &                            \
+	 BIT_MASK_P0HI9Q_HOST_IDX_8814B)
+#define BIT_SET_P0HI9Q_HOST_IDX_8814B(x, v)                                    \
+	(BIT_CLEAR_P0HI9Q_HOST_IDX_8814B(x) | BIT_P0HI9Q_HOST_IDX_8814B(v))
+
+/* 2 REG_P0HI10Q_TXBD_IDX_8814B */
+
+#define BIT_SHIFT_P0HI10Q_HW_IDX_8814B 16
+#define BIT_MASK_P0HI10Q_HW_IDX_8814B 0xfff
+#define BIT_P0HI10Q_HW_IDX_8814B(x)                                            \
+	(((x) & BIT_MASK_P0HI10Q_HW_IDX_8814B)                                 \
+	 << BIT_SHIFT_P0HI10Q_HW_IDX_8814B)
+#define BITS_P0HI10Q_HW_IDX_8814B                                              \
+	(BIT_MASK_P0HI10Q_HW_IDX_8814B << BIT_SHIFT_P0HI10Q_HW_IDX_8814B)
+#define BIT_CLEAR_P0HI10Q_HW_IDX_8814B(x) ((x) & (~BITS_P0HI10Q_HW_IDX_8814B))
+#define BIT_GET_P0HI10Q_HW_IDX_8814B(x)                                        \
+	(((x) >> BIT_SHIFT_P0HI10Q_HW_IDX_8814B) &                             \
+	 BIT_MASK_P0HI10Q_HW_IDX_8814B)
+#define BIT_SET_P0HI10Q_HW_IDX_8814B(x, v)                                     \
+	(BIT_CLEAR_P0HI10Q_HW_IDX_8814B(x) | BIT_P0HI10Q_HW_IDX_8814B(v))
+
+#define BIT_SHIFT_P0HI10Q_HOST_IDX_8814B 0
+#define BIT_MASK_P0HI10Q_HOST_IDX_8814B 0xfff
+#define BIT_P0HI10Q_HOST_IDX_8814B(x)                                          \
+	(((x) & BIT_MASK_P0HI10Q_HOST_IDX_8814B)                               \
+	 << BIT_SHIFT_P0HI10Q_HOST_IDX_8814B)
+#define BITS_P0HI10Q_HOST_IDX_8814B                                            \
+	(BIT_MASK_P0HI10Q_HOST_IDX_8814B << BIT_SHIFT_P0HI10Q_HOST_IDX_8814B)
+#define BIT_CLEAR_P0HI10Q_HOST_IDX_8814B(x)                                    \
+	((x) & (~BITS_P0HI10Q_HOST_IDX_8814B))
+#define BIT_GET_P0HI10Q_HOST_IDX_8814B(x)                                      \
+	(((x) >> BIT_SHIFT_P0HI10Q_HOST_IDX_8814B) &                           \
+	 BIT_MASK_P0HI10Q_HOST_IDX_8814B)
+#define BIT_SET_P0HI10Q_HOST_IDX_8814B(x, v)                                   \
+	(BIT_CLEAR_P0HI10Q_HOST_IDX_8814B(x) | BIT_P0HI10Q_HOST_IDX_8814B(v))
+
+/* 2 REG_P0HI11Q_TXBD_IDX_8814B */
+
+#define BIT_SHIFT_P0HI11Q_HW_IDX_8814B 16
+#define BIT_MASK_P0HI11Q_HW_IDX_8814B 0xfff
+#define BIT_P0HI11Q_HW_IDX_8814B(x)                                            \
+	(((x) & BIT_MASK_P0HI11Q_HW_IDX_8814B)                                 \
+	 << BIT_SHIFT_P0HI11Q_HW_IDX_8814B)
+#define BITS_P0HI11Q_HW_IDX_8814B                                              \
+	(BIT_MASK_P0HI11Q_HW_IDX_8814B << BIT_SHIFT_P0HI11Q_HW_IDX_8814B)
+#define BIT_CLEAR_P0HI11Q_HW_IDX_8814B(x) ((x) & (~BITS_P0HI11Q_HW_IDX_8814B))
+#define BIT_GET_P0HI11Q_HW_IDX_8814B(x)                                        \
+	(((x) >> BIT_SHIFT_P0HI11Q_HW_IDX_8814B) &                             \
+	 BIT_MASK_P0HI11Q_HW_IDX_8814B)
+#define BIT_SET_P0HI11Q_HW_IDX_8814B(x, v)                                     \
+	(BIT_CLEAR_P0HI11Q_HW_IDX_8814B(x) | BIT_P0HI11Q_HW_IDX_8814B(v))
+
+#define BIT_SHIFT_P0HI11Q_HOST_IDX_8814B 0
+#define BIT_MASK_P0HI11Q_HOST_IDX_8814B 0xfff
+#define BIT_P0HI11Q_HOST_IDX_8814B(x)                                          \
+	(((x) & BIT_MASK_P0HI11Q_HOST_IDX_8814B)                               \
+	 << BIT_SHIFT_P0HI11Q_HOST_IDX_8814B)
+#define BITS_P0HI11Q_HOST_IDX_8814B                                            \
+	(BIT_MASK_P0HI11Q_HOST_IDX_8814B << BIT_SHIFT_P0HI11Q_HOST_IDX_8814B)
+#define BIT_CLEAR_P0HI11Q_HOST_IDX_8814B(x)                                    \
+	((x) & (~BITS_P0HI11Q_HOST_IDX_8814B))
+#define BIT_GET_P0HI11Q_HOST_IDX_8814B(x)                                      \
+	(((x) >> BIT_SHIFT_P0HI11Q_HOST_IDX_8814B) &                           \
+	 BIT_MASK_P0HI11Q_HOST_IDX_8814B)
+#define BIT_SET_P0HI11Q_HOST_IDX_8814B(x, v)                                   \
+	(BIT_CLEAR_P0HI11Q_HOST_IDX_8814B(x) | BIT_P0HI11Q_HOST_IDX_8814B(v))
+
+/* 2 REG_P0HI12Q_TXBD_IDX_8814B */
+
+#define BIT_SHIFT_P0HI12Q_HW_IDX_8814B 16
+#define BIT_MASK_P0HI12Q_HW_IDX_8814B 0xfff
+#define BIT_P0HI12Q_HW_IDX_8814B(x)                                            \
+	(((x) & BIT_MASK_P0HI12Q_HW_IDX_8814B)                                 \
+	 << BIT_SHIFT_P0HI12Q_HW_IDX_8814B)
+#define BITS_P0HI12Q_HW_IDX_8814B                                              \
+	(BIT_MASK_P0HI12Q_HW_IDX_8814B << BIT_SHIFT_P0HI12Q_HW_IDX_8814B)
+#define BIT_CLEAR_P0HI12Q_HW_IDX_8814B(x) ((x) & (~BITS_P0HI12Q_HW_IDX_8814B))
+#define BIT_GET_P0HI12Q_HW_IDX_8814B(x)                                        \
+	(((x) >> BIT_SHIFT_P0HI12Q_HW_IDX_8814B) &                             \
+	 BIT_MASK_P0HI12Q_HW_IDX_8814B)
+#define BIT_SET_P0HI12Q_HW_IDX_8814B(x, v)                                     \
+	(BIT_CLEAR_P0HI12Q_HW_IDX_8814B(x) | BIT_P0HI12Q_HW_IDX_8814B(v))
+
+#define BIT_SHIFT_P0HI12Q_HOST_IDX_8814B 0
+#define BIT_MASK_P0HI12Q_HOST_IDX_8814B 0xfff
+#define BIT_P0HI12Q_HOST_IDX_8814B(x)                                          \
+	(((x) & BIT_MASK_P0HI12Q_HOST_IDX_8814B)                               \
+	 << BIT_SHIFT_P0HI12Q_HOST_IDX_8814B)
+#define BITS_P0HI12Q_HOST_IDX_8814B                                            \
+	(BIT_MASK_P0HI12Q_HOST_IDX_8814B << BIT_SHIFT_P0HI12Q_HOST_IDX_8814B)
+#define BIT_CLEAR_P0HI12Q_HOST_IDX_8814B(x)                                    \
+	((x) & (~BITS_P0HI12Q_HOST_IDX_8814B))
+#define BIT_GET_P0HI12Q_HOST_IDX_8814B(x)                                      \
+	(((x) >> BIT_SHIFT_P0HI12Q_HOST_IDX_8814B) &                           \
+	 BIT_MASK_P0HI12Q_HOST_IDX_8814B)
+#define BIT_SET_P0HI12Q_HOST_IDX_8814B(x, v)                                   \
+	(BIT_CLEAR_P0HI12Q_HOST_IDX_8814B(x) | BIT_P0HI12Q_HOST_IDX_8814B(v))
+
+/* 2 REG_P0HI13Q_TXBD_IDX_8814B */
+
+#define BIT_SHIFT_P0HI13Q_HW_IDX_8814B 16
+#define BIT_MASK_P0HI13Q_HW_IDX_8814B 0xfff
+#define BIT_P0HI13Q_HW_IDX_8814B(x)                                            \
+	(((x) & BIT_MASK_P0HI13Q_HW_IDX_8814B)                                 \
+	 << BIT_SHIFT_P0HI13Q_HW_IDX_8814B)
+#define BITS_P0HI13Q_HW_IDX_8814B                                              \
+	(BIT_MASK_P0HI13Q_HW_IDX_8814B << BIT_SHIFT_P0HI13Q_HW_IDX_8814B)
+#define BIT_CLEAR_P0HI13Q_HW_IDX_8814B(x) ((x) & (~BITS_P0HI13Q_HW_IDX_8814B))
+#define BIT_GET_P0HI13Q_HW_IDX_8814B(x)                                        \
+	(((x) >> BIT_SHIFT_P0HI13Q_HW_IDX_8814B) &                             \
+	 BIT_MASK_P0HI13Q_HW_IDX_8814B)
+#define BIT_SET_P0HI13Q_HW_IDX_8814B(x, v)                                     \
+	(BIT_CLEAR_P0HI13Q_HW_IDX_8814B(x) | BIT_P0HI13Q_HW_IDX_8814B(v))
+
+#define BIT_SHIFT_P0HI13Q_HOST_IDX_8814B 0
+#define BIT_MASK_P0HI13Q_HOST_IDX_8814B 0xfff
+#define BIT_P0HI13Q_HOST_IDX_8814B(x)                                          \
+	(((x) & BIT_MASK_P0HI13Q_HOST_IDX_8814B)                               \
+	 << BIT_SHIFT_P0HI13Q_HOST_IDX_8814B)
+#define BITS_P0HI13Q_HOST_IDX_8814B                                            \
+	(BIT_MASK_P0HI13Q_HOST_IDX_8814B << BIT_SHIFT_P0HI13Q_HOST_IDX_8814B)
+#define BIT_CLEAR_P0HI13Q_HOST_IDX_8814B(x)                                    \
+	((x) & (~BITS_P0HI13Q_HOST_IDX_8814B))
+#define BIT_GET_P0HI13Q_HOST_IDX_8814B(x)                                      \
+	(((x) >> BIT_SHIFT_P0HI13Q_HOST_IDX_8814B) &                           \
+	 BIT_MASK_P0HI13Q_HOST_IDX_8814B)
+#define BIT_SET_P0HI13Q_HOST_IDX_8814B(x, v)                                   \
+	(BIT_CLEAR_P0HI13Q_HOST_IDX_8814B(x) | BIT_P0HI13Q_HOST_IDX_8814B(v))
+
+/* 2 REG_P0HI14Q_TXBD_IDX_8814B */
+
+#define BIT_SHIFT_P0HI14Q_HW_IDX_8814B 16
+#define BIT_MASK_P0HI14Q_HW_IDX_8814B 0xfff
+#define BIT_P0HI14Q_HW_IDX_8814B(x)                                            \
+	(((x) & BIT_MASK_P0HI14Q_HW_IDX_8814B)                                 \
+	 << BIT_SHIFT_P0HI14Q_HW_IDX_8814B)
+#define BITS_P0HI14Q_HW_IDX_8814B                                              \
+	(BIT_MASK_P0HI14Q_HW_IDX_8814B << BIT_SHIFT_P0HI14Q_HW_IDX_8814B)
+#define BIT_CLEAR_P0HI14Q_HW_IDX_8814B(x) ((x) & (~BITS_P0HI14Q_HW_IDX_8814B))
+#define BIT_GET_P0HI14Q_HW_IDX_8814B(x)                                        \
+	(((x) >> BIT_SHIFT_P0HI14Q_HW_IDX_8814B) &                             \
+	 BIT_MASK_P0HI14Q_HW_IDX_8814B)
+#define BIT_SET_P0HI14Q_HW_IDX_8814B(x, v)                                     \
+	(BIT_CLEAR_P0HI14Q_HW_IDX_8814B(x) | BIT_P0HI14Q_HW_IDX_8814B(v))
+
+#define BIT_SHIFT_P0HI14Q_HOST_IDX_8814B 0
+#define BIT_MASK_P0HI14Q_HOST_IDX_8814B 0xfff
+#define BIT_P0HI14Q_HOST_IDX_8814B(x)                                          \
+	(((x) & BIT_MASK_P0HI14Q_HOST_IDX_8814B)                               \
+	 << BIT_SHIFT_P0HI14Q_HOST_IDX_8814B)
+#define BITS_P0HI14Q_HOST_IDX_8814B                                            \
+	(BIT_MASK_P0HI14Q_HOST_IDX_8814B << BIT_SHIFT_P0HI14Q_HOST_IDX_8814B)
+#define BIT_CLEAR_P0HI14Q_HOST_IDX_8814B(x)                                    \
+	((x) & (~BITS_P0HI14Q_HOST_IDX_8814B))
+#define BIT_GET_P0HI14Q_HOST_IDX_8814B(x)                                      \
+	(((x) >> BIT_SHIFT_P0HI14Q_HOST_IDX_8814B) &                           \
+	 BIT_MASK_P0HI14Q_HOST_IDX_8814B)
+#define BIT_SET_P0HI14Q_HOST_IDX_8814B(x, v)                                   \
+	(BIT_CLEAR_P0HI14Q_HOST_IDX_8814B(x) | BIT_P0HI14Q_HOST_IDX_8814B(v))
+
+/* 2 REG_P0HI15Q_TXBD_IDX_8814B */
+
+#define BIT_SHIFT_P0HI15Q_HW_IDX_8814B 16
+#define BIT_MASK_P0HI15Q_HW_IDX_8814B 0xfff
+#define BIT_P0HI15Q_HW_IDX_8814B(x)                                            \
+	(((x) & BIT_MASK_P0HI15Q_HW_IDX_8814B)                                 \
+	 << BIT_SHIFT_P0HI15Q_HW_IDX_8814B)
+#define BITS_P0HI15Q_HW_IDX_8814B                                              \
+	(BIT_MASK_P0HI15Q_HW_IDX_8814B << BIT_SHIFT_P0HI15Q_HW_IDX_8814B)
+#define BIT_CLEAR_P0HI15Q_HW_IDX_8814B(x) ((x) & (~BITS_P0HI15Q_HW_IDX_8814B))
+#define BIT_GET_P0HI15Q_HW_IDX_8814B(x)                                        \
+	(((x) >> BIT_SHIFT_P0HI15Q_HW_IDX_8814B) &                             \
+	 BIT_MASK_P0HI15Q_HW_IDX_8814B)
+#define BIT_SET_P0HI15Q_HW_IDX_8814B(x, v)                                     \
+	(BIT_CLEAR_P0HI15Q_HW_IDX_8814B(x) | BIT_P0HI15Q_HW_IDX_8814B(v))
+
+#define BIT_SHIFT_P0HI15Q_HOST_IDX_8814B 0
+#define BIT_MASK_P0HI15Q_HOST_IDX_8814B 0xfff
+#define BIT_P0HI15Q_HOST_IDX_8814B(x)                                          \
+	(((x) & BIT_MASK_P0HI15Q_HOST_IDX_8814B)                               \
+	 << BIT_SHIFT_P0HI15Q_HOST_IDX_8814B)
+#define BITS_P0HI15Q_HOST_IDX_8814B                                            \
+	(BIT_MASK_P0HI15Q_HOST_IDX_8814B << BIT_SHIFT_P0HI15Q_HOST_IDX_8814B)
+#define BIT_CLEAR_P0HI15Q_HOST_IDX_8814B(x)                                    \
+	((x) & (~BITS_P0HI15Q_HOST_IDX_8814B))
+#define BIT_GET_P0HI15Q_HOST_IDX_8814B(x)                                      \
+	(((x) >> BIT_SHIFT_P0HI15Q_HOST_IDX_8814B) &                           \
+	 BIT_MASK_P0HI15Q_HOST_IDX_8814B)
+#define BIT_SET_P0HI15Q_HOST_IDX_8814B(x, v)                                   \
+	(BIT_CLEAR_P0HI15Q_HOST_IDX_8814B(x) | BIT_P0HI15Q_HOST_IDX_8814B(v))
+
+/* 2 REG_CHANGE_PCIE_SPEED_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+#define BIT_SHIFT_RXDMA_ERR_CNT_8814B 8
+#define BIT_MASK_RXDMA_ERR_CNT_8814B 0xff
+#define BIT_RXDMA_ERR_CNT_8814B(x)                                             \
+	(((x) & BIT_MASK_RXDMA_ERR_CNT_8814B) << BIT_SHIFT_RXDMA_ERR_CNT_8814B)
+#define BITS_RXDMA_ERR_CNT_8814B                                               \
+	(BIT_MASK_RXDMA_ERR_CNT_8814B << BIT_SHIFT_RXDMA_ERR_CNT_8814B)
+#define BIT_CLEAR_RXDMA_ERR_CNT_8814B(x) ((x) & (~BITS_RXDMA_ERR_CNT_8814B))
+#define BIT_GET_RXDMA_ERR_CNT_8814B(x)                                         \
+	(((x) >> BIT_SHIFT_RXDMA_ERR_CNT_8814B) & BIT_MASK_RXDMA_ERR_CNT_8814B)
+#define BIT_SET_RXDMA_ERR_CNT_8814B(x, v)                                      \
+	(BIT_CLEAR_RXDMA_ERR_CNT_8814B(x) | BIT_RXDMA_ERR_CNT_8814B(v))
+
+#define BIT_TXDMA_ERR_HANDLE_REQ_8814B BIT(7)
+#define BIT_TXDMA_ERROR_PS_8814B BIT(6)
+#define BIT_EN_TXDMA_STUCK_ERR_HANDLE_8814B BIT(5)
+#define BIT_EN_TXDMA_RTN_ERR_HANDLE_8814B BIT(4)
+#define BIT_RXDMA_ERR_HANDLE_REQ_8814B BIT(3)
+#define BIT_RXDMA_ERROR_PS_8814B BIT(2)
+#define BIT_EN_RXDMA_STUCK_ERR_HANDLE_8814B BIT(1)
+#define BIT_EN_RXDMA_RTN_ERR_HANDLE_8814B BIT(0)
+
+/* 2 REG_DEBUG_STATE1_8814B */
+
+#define BIT_SHIFT_DEBUG_STATE1_8814B 0
+#define BIT_MASK_DEBUG_STATE1_8814B 0xffffffffL
+#define BIT_DEBUG_STATE1_8814B(x)                                              \
+	(((x) & BIT_MASK_DEBUG_STATE1_8814B) << BIT_SHIFT_DEBUG_STATE1_8814B)
+#define BITS_DEBUG_STATE1_8814B                                                \
+	(BIT_MASK_DEBUG_STATE1_8814B << BIT_SHIFT_DEBUG_STATE1_8814B)
+#define BIT_CLEAR_DEBUG_STATE1_8814B(x) ((x) & (~BITS_DEBUG_STATE1_8814B))
+#define BIT_GET_DEBUG_STATE1_8814B(x)                                          \
+	(((x) >> BIT_SHIFT_DEBUG_STATE1_8814B) & BIT_MASK_DEBUG_STATE1_8814B)
+#define BIT_SET_DEBUG_STATE1_8814B(x, v)                                       \
+	(BIT_CLEAR_DEBUG_STATE1_8814B(x) | BIT_DEBUG_STATE1_8814B(v))
+
+/* 2 REG_DEBUG_STATE2_8814B */
+
+#define BIT_SHIFT_DEBUG_STATE2_8814B 0
+#define BIT_MASK_DEBUG_STATE2_8814B 0xffffffffL
+#define BIT_DEBUG_STATE2_8814B(x)                                              \
+	(((x) & BIT_MASK_DEBUG_STATE2_8814B) << BIT_SHIFT_DEBUG_STATE2_8814B)
+#define BITS_DEBUG_STATE2_8814B                                                \
+	(BIT_MASK_DEBUG_STATE2_8814B << BIT_SHIFT_DEBUG_STATE2_8814B)
+#define BIT_CLEAR_DEBUG_STATE2_8814B(x) ((x) & (~BITS_DEBUG_STATE2_8814B))
+#define BIT_GET_DEBUG_STATE2_8814B(x)                                          \
+	(((x) >> BIT_SHIFT_DEBUG_STATE2_8814B) & BIT_MASK_DEBUG_STATE2_8814B)
+#define BIT_SET_DEBUG_STATE2_8814B(x, v)                                       \
+	(BIT_CLEAR_DEBUG_STATE2_8814B(x) | BIT_DEBUG_STATE2_8814B(v))
+
+/* 2 REG_DEBUG_STATE3_8814B */
+
+#define BIT_SHIFT_DEBUG_STATE3_8814B 0
+#define BIT_MASK_DEBUG_STATE3_8814B 0xffffffffL
+#define BIT_DEBUG_STATE3_8814B(x)                                              \
+	(((x) & BIT_MASK_DEBUG_STATE3_8814B) << BIT_SHIFT_DEBUG_STATE3_8814B)
+#define BITS_DEBUG_STATE3_8814B                                                \
+	(BIT_MASK_DEBUG_STATE3_8814B << BIT_SHIFT_DEBUG_STATE3_8814B)
+#define BIT_CLEAR_DEBUG_STATE3_8814B(x) ((x) & (~BITS_DEBUG_STATE3_8814B))
+#define BIT_GET_DEBUG_STATE3_8814B(x)                                          \
+	(((x) >> BIT_SHIFT_DEBUG_STATE3_8814B) & BIT_MASK_DEBUG_STATE3_8814B)
+#define BIT_SET_DEBUG_STATE3_8814B(x, v)                                       \
+	(BIT_CLEAR_DEBUG_STATE3_8814B(x) | BIT_DEBUG_STATE3_8814B(v))
+
+/* 2 REG_ACH5_TXBD_DESA_L_8814B */
+
+#define BIT_SHIFT_ACH5_TXBD_DESA_L_8814B 0
+#define BIT_MASK_ACH5_TXBD_DESA_L_8814B 0xffffffffL
+#define BIT_ACH5_TXBD_DESA_L_8814B(x)                                          \
+	(((x) & BIT_MASK_ACH5_TXBD_DESA_L_8814B)                               \
+	 << BIT_SHIFT_ACH5_TXBD_DESA_L_8814B)
+#define BITS_ACH5_TXBD_DESA_L_8814B                                            \
+	(BIT_MASK_ACH5_TXBD_DESA_L_8814B << BIT_SHIFT_ACH5_TXBD_DESA_L_8814B)
+#define BIT_CLEAR_ACH5_TXBD_DESA_L_8814B(x)                                    \
+	((x) & (~BITS_ACH5_TXBD_DESA_L_8814B))
+#define BIT_GET_ACH5_TXBD_DESA_L_8814B(x)                                      \
+	(((x) >> BIT_SHIFT_ACH5_TXBD_DESA_L_8814B) &                           \
+	 BIT_MASK_ACH5_TXBD_DESA_L_8814B)
+#define BIT_SET_ACH5_TXBD_DESA_L_8814B(x, v)                                   \
+	(BIT_CLEAR_ACH5_TXBD_DESA_L_8814B(x) | BIT_ACH5_TXBD_DESA_L_8814B(v))
+
+/* 2 REG_ACH5_TXBD_DESA_H_8814B */
+
+#define BIT_SHIFT_ACH5_TXBD_DESA_H_8814B 0
+#define BIT_MASK_ACH5_TXBD_DESA_H_8814B 0xffffffffL
+#define BIT_ACH5_TXBD_DESA_H_8814B(x)                                          \
+	(((x) & BIT_MASK_ACH5_TXBD_DESA_H_8814B)                               \
+	 << BIT_SHIFT_ACH5_TXBD_DESA_H_8814B)
+#define BITS_ACH5_TXBD_DESA_H_8814B                                            \
+	(BIT_MASK_ACH5_TXBD_DESA_H_8814B << BIT_SHIFT_ACH5_TXBD_DESA_H_8814B)
+#define BIT_CLEAR_ACH5_TXBD_DESA_H_8814B(x)                                    \
+	((x) & (~BITS_ACH5_TXBD_DESA_H_8814B))
+#define BIT_GET_ACH5_TXBD_DESA_H_8814B(x)                                      \
+	(((x) >> BIT_SHIFT_ACH5_TXBD_DESA_H_8814B) &                           \
+	 BIT_MASK_ACH5_TXBD_DESA_H_8814B)
+#define BIT_SET_ACH5_TXBD_DESA_H_8814B(x, v)                                   \
+	(BIT_CLEAR_ACH5_TXBD_DESA_H_8814B(x) | BIT_ACH5_TXBD_DESA_H_8814B(v))
+
+/* 2 REG_ACH6_TXBD_DESA_L_8814B */
+
+#define BIT_SHIFT_ACH6_TXBD_DESA_L_8814B 0
+#define BIT_MASK_ACH6_TXBD_DESA_L_8814B 0xffffffffL
+#define BIT_ACH6_TXBD_DESA_L_8814B(x)                                          \
+	(((x) & BIT_MASK_ACH6_TXBD_DESA_L_8814B)                               \
+	 << BIT_SHIFT_ACH6_TXBD_DESA_L_8814B)
+#define BITS_ACH6_TXBD_DESA_L_8814B                                            \
+	(BIT_MASK_ACH6_TXBD_DESA_L_8814B << BIT_SHIFT_ACH6_TXBD_DESA_L_8814B)
+#define BIT_CLEAR_ACH6_TXBD_DESA_L_8814B(x)                                    \
+	((x) & (~BITS_ACH6_TXBD_DESA_L_8814B))
+#define BIT_GET_ACH6_TXBD_DESA_L_8814B(x)                                      \
+	(((x) >> BIT_SHIFT_ACH6_TXBD_DESA_L_8814B) &                           \
+	 BIT_MASK_ACH6_TXBD_DESA_L_8814B)
+#define BIT_SET_ACH6_TXBD_DESA_L_8814B(x, v)                                   \
+	(BIT_CLEAR_ACH6_TXBD_DESA_L_8814B(x) | BIT_ACH6_TXBD_DESA_L_8814B(v))
+
+/* 2 REG_ACH6_TXBD_DESA_H_8814B */
+
+#define BIT_SHIFT_ACH6_TXBD_DESA_H_8814B 0
+#define BIT_MASK_ACH6_TXBD_DESA_H_8814B 0xffffffffL
+#define BIT_ACH6_TXBD_DESA_H_8814B(x)                                          \
+	(((x) & BIT_MASK_ACH6_TXBD_DESA_H_8814B)                               \
+	 << BIT_SHIFT_ACH6_TXBD_DESA_H_8814B)
+#define BITS_ACH6_TXBD_DESA_H_8814B                                            \
+	(BIT_MASK_ACH6_TXBD_DESA_H_8814B << BIT_SHIFT_ACH6_TXBD_DESA_H_8814B)
+#define BIT_CLEAR_ACH6_TXBD_DESA_H_8814B(x)                                    \
+	((x) & (~BITS_ACH6_TXBD_DESA_H_8814B))
+#define BIT_GET_ACH6_TXBD_DESA_H_8814B(x)                                      \
+	(((x) >> BIT_SHIFT_ACH6_TXBD_DESA_H_8814B) &                           \
+	 BIT_MASK_ACH6_TXBD_DESA_H_8814B)
+#define BIT_SET_ACH6_TXBD_DESA_H_8814B(x, v)                                   \
+	(BIT_CLEAR_ACH6_TXBD_DESA_H_8814B(x) | BIT_ACH6_TXBD_DESA_H_8814B(v))
+
+/* 2 REG_ACH7_TXBD_DESA_L_8814B */
+
+#define BIT_SHIFT_ACH7_TXBD_DESA_L_8814B 0
+#define BIT_MASK_ACH7_TXBD_DESA_L_8814B 0xffffffffL
+#define BIT_ACH7_TXBD_DESA_L_8814B(x)                                          \
+	(((x) & BIT_MASK_ACH7_TXBD_DESA_L_8814B)                               \
+	 << BIT_SHIFT_ACH7_TXBD_DESA_L_8814B)
+#define BITS_ACH7_TXBD_DESA_L_8814B                                            \
+	(BIT_MASK_ACH7_TXBD_DESA_L_8814B << BIT_SHIFT_ACH7_TXBD_DESA_L_8814B)
+#define BIT_CLEAR_ACH7_TXBD_DESA_L_8814B(x)                                    \
+	((x) & (~BITS_ACH7_TXBD_DESA_L_8814B))
+#define BIT_GET_ACH7_TXBD_DESA_L_8814B(x)                                      \
+	(((x) >> BIT_SHIFT_ACH7_TXBD_DESA_L_8814B) &                           \
+	 BIT_MASK_ACH7_TXBD_DESA_L_8814B)
+#define BIT_SET_ACH7_TXBD_DESA_L_8814B(x, v)                                   \
+	(BIT_CLEAR_ACH7_TXBD_DESA_L_8814B(x) | BIT_ACH7_TXBD_DESA_L_8814B(v))
+
+/* 2 REG_ACH7_TXBD_DESA_H_8814B */
+
+#define BIT_SHIFT_ACH7_TXBD_DESA_H_8814B 0
+#define BIT_MASK_ACH7_TXBD_DESA_H_8814B 0xffffffffL
+#define BIT_ACH7_TXBD_DESA_H_8814B(x)                                          \
+	(((x) & BIT_MASK_ACH7_TXBD_DESA_H_8814B)                               \
+	 << BIT_SHIFT_ACH7_TXBD_DESA_H_8814B)
+#define BITS_ACH7_TXBD_DESA_H_8814B                                            \
+	(BIT_MASK_ACH7_TXBD_DESA_H_8814B << BIT_SHIFT_ACH7_TXBD_DESA_H_8814B)
+#define BIT_CLEAR_ACH7_TXBD_DESA_H_8814B(x)                                    \
+	((x) & (~BITS_ACH7_TXBD_DESA_H_8814B))
+#define BIT_GET_ACH7_TXBD_DESA_H_8814B(x)                                      \
+	(((x) >> BIT_SHIFT_ACH7_TXBD_DESA_H_8814B) &                           \
+	 BIT_MASK_ACH7_TXBD_DESA_H_8814B)
+#define BIT_SET_ACH7_TXBD_DESA_H_8814B(x, v)                                   \
+	(BIT_CLEAR_ACH7_TXBD_DESA_H_8814B(x) | BIT_ACH7_TXBD_DESA_H_8814B(v))
+
+/* 2 REG_ACH8_TXBD_DESA_L_8814B */
+
+#define BIT_SHIFT_ACH8_TXBD_DESA_L_8814B 0
+#define BIT_MASK_ACH8_TXBD_DESA_L_8814B 0xffffffffL
+#define BIT_ACH8_TXBD_DESA_L_8814B(x)                                          \
+	(((x) & BIT_MASK_ACH8_TXBD_DESA_L_8814B)                               \
+	 << BIT_SHIFT_ACH8_TXBD_DESA_L_8814B)
+#define BITS_ACH8_TXBD_DESA_L_8814B                                            \
+	(BIT_MASK_ACH8_TXBD_DESA_L_8814B << BIT_SHIFT_ACH8_TXBD_DESA_L_8814B)
+#define BIT_CLEAR_ACH8_TXBD_DESA_L_8814B(x)                                    \
+	((x) & (~BITS_ACH8_TXBD_DESA_L_8814B))
+#define BIT_GET_ACH8_TXBD_DESA_L_8814B(x)                                      \
+	(((x) >> BIT_SHIFT_ACH8_TXBD_DESA_L_8814B) &                           \
+	 BIT_MASK_ACH8_TXBD_DESA_L_8814B)
+#define BIT_SET_ACH8_TXBD_DESA_L_8814B(x, v)                                   \
+	(BIT_CLEAR_ACH8_TXBD_DESA_L_8814B(x) | BIT_ACH8_TXBD_DESA_L_8814B(v))
+
+/* 2 REG_ACH8_TXBD_DESA_H_8814B */
+
+#define BIT_SHIFT_ACH8_TXBD_DESA_H_8814B 0
+#define BIT_MASK_ACH8_TXBD_DESA_H_8814B 0xffffffffL
+#define BIT_ACH8_TXBD_DESA_H_8814B(x)                                          \
+	(((x) & BIT_MASK_ACH8_TXBD_DESA_H_8814B)                               \
+	 << BIT_SHIFT_ACH8_TXBD_DESA_H_8814B)
+#define BITS_ACH8_TXBD_DESA_H_8814B                                            \
+	(BIT_MASK_ACH8_TXBD_DESA_H_8814B << BIT_SHIFT_ACH8_TXBD_DESA_H_8814B)
+#define BIT_CLEAR_ACH8_TXBD_DESA_H_8814B(x)                                    \
+	((x) & (~BITS_ACH8_TXBD_DESA_H_8814B))
+#define BIT_GET_ACH8_TXBD_DESA_H_8814B(x)                                      \
+	(((x) >> BIT_SHIFT_ACH8_TXBD_DESA_H_8814B) &                           \
+	 BIT_MASK_ACH8_TXBD_DESA_H_8814B)
+#define BIT_SET_ACH8_TXBD_DESA_H_8814B(x, v)                                   \
+	(BIT_CLEAR_ACH8_TXBD_DESA_H_8814B(x) | BIT_ACH8_TXBD_DESA_H_8814B(v))
+
+/* 2 REG_ACH9_TXBD_DESA_L_8814B */
+
+#define BIT_SHIFT_ACH9_TXBD_DESA_L_8814B 0
+#define BIT_MASK_ACH9_TXBD_DESA_L_8814B 0xffffffffL
+#define BIT_ACH9_TXBD_DESA_L_8814B(x)                                          \
+	(((x) & BIT_MASK_ACH9_TXBD_DESA_L_8814B)                               \
+	 << BIT_SHIFT_ACH9_TXBD_DESA_L_8814B)
+#define BITS_ACH9_TXBD_DESA_L_8814B                                            \
+	(BIT_MASK_ACH9_TXBD_DESA_L_8814B << BIT_SHIFT_ACH9_TXBD_DESA_L_8814B)
+#define BIT_CLEAR_ACH9_TXBD_DESA_L_8814B(x)                                    \
+	((x) & (~BITS_ACH9_TXBD_DESA_L_8814B))
+#define BIT_GET_ACH9_TXBD_DESA_L_8814B(x)                                      \
+	(((x) >> BIT_SHIFT_ACH9_TXBD_DESA_L_8814B) &                           \
+	 BIT_MASK_ACH9_TXBD_DESA_L_8814B)
+#define BIT_SET_ACH9_TXBD_DESA_L_8814B(x, v)                                   \
+	(BIT_CLEAR_ACH9_TXBD_DESA_L_8814B(x) | BIT_ACH9_TXBD_DESA_L_8814B(v))
+
+/* 2 REG_ACH9_TXBD_DESA_H_8814B */
+
+#define BIT_SHIFT_ACH9_TXBD_DESA_H_8814B 0
+#define BIT_MASK_ACH9_TXBD_DESA_H_8814B 0xffffffffL
+#define BIT_ACH9_TXBD_DESA_H_8814B(x)                                          \
+	(((x) & BIT_MASK_ACH9_TXBD_DESA_H_8814B)                               \
+	 << BIT_SHIFT_ACH9_TXBD_DESA_H_8814B)
+#define BITS_ACH9_TXBD_DESA_H_8814B                                            \
+	(BIT_MASK_ACH9_TXBD_DESA_H_8814B << BIT_SHIFT_ACH9_TXBD_DESA_H_8814B)
+#define BIT_CLEAR_ACH9_TXBD_DESA_H_8814B(x)                                    \
+	((x) & (~BITS_ACH9_TXBD_DESA_H_8814B))
+#define BIT_GET_ACH9_TXBD_DESA_H_8814B(x)                                      \
+	(((x) >> BIT_SHIFT_ACH9_TXBD_DESA_H_8814B) &                           \
+	 BIT_MASK_ACH9_TXBD_DESA_H_8814B)
+#define BIT_SET_ACH9_TXBD_DESA_H_8814B(x, v)                                   \
+	(BIT_CLEAR_ACH9_TXBD_DESA_H_8814B(x) | BIT_ACH9_TXBD_DESA_H_8814B(v))
+
+/* 2 REG_ACH10_TXBD_DESA_L_8814B */
+
+#define BIT_SHIFT_ACH10_TXBD_DESA_L_8814B 0
+#define BIT_MASK_ACH10_TXBD_DESA_L_8814B 0xffffffffL
+#define BIT_ACH10_TXBD_DESA_L_8814B(x)                                         \
+	(((x) & BIT_MASK_ACH10_TXBD_DESA_L_8814B)                              \
+	 << BIT_SHIFT_ACH10_TXBD_DESA_L_8814B)
+#define BITS_ACH10_TXBD_DESA_L_8814B                                           \
+	(BIT_MASK_ACH10_TXBD_DESA_L_8814B << BIT_SHIFT_ACH10_TXBD_DESA_L_8814B)
+#define BIT_CLEAR_ACH10_TXBD_DESA_L_8814B(x)                                   \
+	((x) & (~BITS_ACH10_TXBD_DESA_L_8814B))
+#define BIT_GET_ACH10_TXBD_DESA_L_8814B(x)                                     \
+	(((x) >> BIT_SHIFT_ACH10_TXBD_DESA_L_8814B) &                          \
+	 BIT_MASK_ACH10_TXBD_DESA_L_8814B)
+#define BIT_SET_ACH10_TXBD_DESA_L_8814B(x, v)                                  \
+	(BIT_CLEAR_ACH10_TXBD_DESA_L_8814B(x) | BIT_ACH10_TXBD_DESA_L_8814B(v))
+
+/* 2 REG_ACH10_TXBD_DESA_H_8814B */
+
+#define BIT_SHIFT_ACH10_TXBD_DESA_H_8814B 0
+#define BIT_MASK_ACH10_TXBD_DESA_H_8814B 0xffffffffL
+#define BIT_ACH10_TXBD_DESA_H_8814B(x)                                         \
+	(((x) & BIT_MASK_ACH10_TXBD_DESA_H_8814B)                              \
+	 << BIT_SHIFT_ACH10_TXBD_DESA_H_8814B)
+#define BITS_ACH10_TXBD_DESA_H_8814B                                           \
+	(BIT_MASK_ACH10_TXBD_DESA_H_8814B << BIT_SHIFT_ACH10_TXBD_DESA_H_8814B)
+#define BIT_CLEAR_ACH10_TXBD_DESA_H_8814B(x)                                   \
+	((x) & (~BITS_ACH10_TXBD_DESA_H_8814B))
+#define BIT_GET_ACH10_TXBD_DESA_H_8814B(x)                                     \
+	(((x) >> BIT_SHIFT_ACH10_TXBD_DESA_H_8814B) &                          \
+	 BIT_MASK_ACH10_TXBD_DESA_H_8814B)
+#define BIT_SET_ACH10_TXBD_DESA_H_8814B(x, v)                                  \
+	(BIT_CLEAR_ACH10_TXBD_DESA_H_8814B(x) | BIT_ACH10_TXBD_DESA_H_8814B(v))
+
+/* 2 REG_ACH11_TXBD_DESA_L_8814B */
+
+#define BIT_SHIFT_ACH11_TXBD_DESA_L_8814B 0
+#define BIT_MASK_ACH11_TXBD_DESA_L_8814B 0xffffffffL
+#define BIT_ACH11_TXBD_DESA_L_8814B(x)                                         \
+	(((x) & BIT_MASK_ACH11_TXBD_DESA_L_8814B)                              \
+	 << BIT_SHIFT_ACH11_TXBD_DESA_L_8814B)
+#define BITS_ACH11_TXBD_DESA_L_8814B                                           \
+	(BIT_MASK_ACH11_TXBD_DESA_L_8814B << BIT_SHIFT_ACH11_TXBD_DESA_L_8814B)
+#define BIT_CLEAR_ACH11_TXBD_DESA_L_8814B(x)                                   \
+	((x) & (~BITS_ACH11_TXBD_DESA_L_8814B))
+#define BIT_GET_ACH11_TXBD_DESA_L_8814B(x)                                     \
+	(((x) >> BIT_SHIFT_ACH11_TXBD_DESA_L_8814B) &                          \
+	 BIT_MASK_ACH11_TXBD_DESA_L_8814B)
+#define BIT_SET_ACH11_TXBD_DESA_L_8814B(x, v)                                  \
+	(BIT_CLEAR_ACH11_TXBD_DESA_L_8814B(x) | BIT_ACH11_TXBD_DESA_L_8814B(v))
+
+/* 2 REG_ACH11_TXBD_DESA_H_8814B */
+
+#define BIT_SHIFT_ACH11_TXBD_DESA_H_8814B 0
+#define BIT_MASK_ACH11_TXBD_DESA_H_8814B 0xffffffffL
+#define BIT_ACH11_TXBD_DESA_H_8814B(x)                                         \
+	(((x) & BIT_MASK_ACH11_TXBD_DESA_H_8814B)                              \
+	 << BIT_SHIFT_ACH11_TXBD_DESA_H_8814B)
+#define BITS_ACH11_TXBD_DESA_H_8814B                                           \
+	(BIT_MASK_ACH11_TXBD_DESA_H_8814B << BIT_SHIFT_ACH11_TXBD_DESA_H_8814B)
+#define BIT_CLEAR_ACH11_TXBD_DESA_H_8814B(x)                                   \
+	((x) & (~BITS_ACH11_TXBD_DESA_H_8814B))
+#define BIT_GET_ACH11_TXBD_DESA_H_8814B(x)                                     \
+	(((x) >> BIT_SHIFT_ACH11_TXBD_DESA_H_8814B) &                          \
+	 BIT_MASK_ACH11_TXBD_DESA_H_8814B)
+#define BIT_SET_ACH11_TXBD_DESA_H_8814B(x, v)                                  \
+	(BIT_CLEAR_ACH11_TXBD_DESA_H_8814B(x) | BIT_ACH11_TXBD_DESA_H_8814B(v))
+
+/* 2 REG_ACH12_TXBD_DESA_L_8814B */
+
+#define BIT_SHIFT_ACH12_TXBD_DESA_L_8814B 0
+#define BIT_MASK_ACH12_TXBD_DESA_L_8814B 0xffffffffL
+#define BIT_ACH12_TXBD_DESA_L_8814B(x)                                         \
+	(((x) & BIT_MASK_ACH12_TXBD_DESA_L_8814B)                              \
+	 << BIT_SHIFT_ACH12_TXBD_DESA_L_8814B)
+#define BITS_ACH12_TXBD_DESA_L_8814B                                           \
+	(BIT_MASK_ACH12_TXBD_DESA_L_8814B << BIT_SHIFT_ACH12_TXBD_DESA_L_8814B)
+#define BIT_CLEAR_ACH12_TXBD_DESA_L_8814B(x)                                   \
+	((x) & (~BITS_ACH12_TXBD_DESA_L_8814B))
+#define BIT_GET_ACH12_TXBD_DESA_L_8814B(x)                                     \
+	(((x) >> BIT_SHIFT_ACH12_TXBD_DESA_L_8814B) &                          \
+	 BIT_MASK_ACH12_TXBD_DESA_L_8814B)
+#define BIT_SET_ACH12_TXBD_DESA_L_8814B(x, v)                                  \
+	(BIT_CLEAR_ACH12_TXBD_DESA_L_8814B(x) | BIT_ACH12_TXBD_DESA_L_8814B(v))
+
+/* 2 REG_ACH12_TXBD_DESA_H_8814B */
+
+#define BIT_SHIFT_ACH12_TXBD_DESA_H_8814B 0
+#define BIT_MASK_ACH12_TXBD_DESA_H_8814B 0xffffffffL
+#define BIT_ACH12_TXBD_DESA_H_8814B(x)                                         \
+	(((x) & BIT_MASK_ACH12_TXBD_DESA_H_8814B)                              \
+	 << BIT_SHIFT_ACH12_TXBD_DESA_H_8814B)
+#define BITS_ACH12_TXBD_DESA_H_8814B                                           \
+	(BIT_MASK_ACH12_TXBD_DESA_H_8814B << BIT_SHIFT_ACH12_TXBD_DESA_H_8814B)
+#define BIT_CLEAR_ACH12_TXBD_DESA_H_8814B(x)                                   \
+	((x) & (~BITS_ACH12_TXBD_DESA_H_8814B))
+#define BIT_GET_ACH12_TXBD_DESA_H_8814B(x)                                     \
+	(((x) >> BIT_SHIFT_ACH12_TXBD_DESA_H_8814B) &                          \
+	 BIT_MASK_ACH12_TXBD_DESA_H_8814B)
+#define BIT_SET_ACH12_TXBD_DESA_H_8814B(x, v)                                  \
+	(BIT_CLEAR_ACH12_TXBD_DESA_H_8814B(x) | BIT_ACH12_TXBD_DESA_H_8814B(v))
+
+/* 2 REG_ACH13_TXBD_DESA_L_8814B */
+
+#define BIT_SHIFT_ACH13_TXBD_DESA_L_8814B 0
+#define BIT_MASK_ACH13_TXBD_DESA_L_8814B 0xffffffffL
+#define BIT_ACH13_TXBD_DESA_L_8814B(x)                                         \
+	(((x) & BIT_MASK_ACH13_TXBD_DESA_L_8814B)                              \
+	 << BIT_SHIFT_ACH13_TXBD_DESA_L_8814B)
+#define BITS_ACH13_TXBD_DESA_L_8814B                                           \
+	(BIT_MASK_ACH13_TXBD_DESA_L_8814B << BIT_SHIFT_ACH13_TXBD_DESA_L_8814B)
+#define BIT_CLEAR_ACH13_TXBD_DESA_L_8814B(x)                                   \
+	((x) & (~BITS_ACH13_TXBD_DESA_L_8814B))
+#define BIT_GET_ACH13_TXBD_DESA_L_8814B(x)                                     \
+	(((x) >> BIT_SHIFT_ACH13_TXBD_DESA_L_8814B) &                          \
+	 BIT_MASK_ACH13_TXBD_DESA_L_8814B)
+#define BIT_SET_ACH13_TXBD_DESA_L_8814B(x, v)                                  \
+	(BIT_CLEAR_ACH13_TXBD_DESA_L_8814B(x) | BIT_ACH13_TXBD_DESA_L_8814B(v))
+
+/* 2 REG_ACH13_TXBD_DESA_H_8814B */
+
+#define BIT_SHIFT_ACH13_TXBD_DESA_H_8814B 0
+#define BIT_MASK_ACH13_TXBD_DESA_H_8814B 0xffffffffL
+#define BIT_ACH13_TXBD_DESA_H_8814B(x)                                         \
+	(((x) & BIT_MASK_ACH13_TXBD_DESA_H_8814B)                              \
+	 << BIT_SHIFT_ACH13_TXBD_DESA_H_8814B)
+#define BITS_ACH13_TXBD_DESA_H_8814B                                           \
+	(BIT_MASK_ACH13_TXBD_DESA_H_8814B << BIT_SHIFT_ACH13_TXBD_DESA_H_8814B)
+#define BIT_CLEAR_ACH13_TXBD_DESA_H_8814B(x)                                   \
+	((x) & (~BITS_ACH13_TXBD_DESA_H_8814B))
+#define BIT_GET_ACH13_TXBD_DESA_H_8814B(x)                                     \
+	(((x) >> BIT_SHIFT_ACH13_TXBD_DESA_H_8814B) &                          \
+	 BIT_MASK_ACH13_TXBD_DESA_H_8814B)
+#define BIT_SET_ACH13_TXBD_DESA_H_8814B(x, v)                                  \
+	(BIT_CLEAR_ACH13_TXBD_DESA_H_8814B(x) | BIT_ACH13_TXBD_DESA_H_8814B(v))
+
+/* 2 REG_HI0Q_TXBD_DESA_L_8814B */
+
+#define BIT_SHIFT_HI0Q_TXBD_DESA_L_8814B 0
+#define BIT_MASK_HI0Q_TXBD_DESA_L_8814B 0xffffffffL
+#define BIT_HI0Q_TXBD_DESA_L_8814B(x)                                          \
+	(((x) & BIT_MASK_HI0Q_TXBD_DESA_L_8814B)                               \
+	 << BIT_SHIFT_HI0Q_TXBD_DESA_L_8814B)
+#define BITS_HI0Q_TXBD_DESA_L_8814B                                            \
+	(BIT_MASK_HI0Q_TXBD_DESA_L_8814B << BIT_SHIFT_HI0Q_TXBD_DESA_L_8814B)
+#define BIT_CLEAR_HI0Q_TXBD_DESA_L_8814B(x)                                    \
+	((x) & (~BITS_HI0Q_TXBD_DESA_L_8814B))
+#define BIT_GET_HI0Q_TXBD_DESA_L_8814B(x)                                      \
+	(((x) >> BIT_SHIFT_HI0Q_TXBD_DESA_L_8814B) &                           \
+	 BIT_MASK_HI0Q_TXBD_DESA_L_8814B)
+#define BIT_SET_HI0Q_TXBD_DESA_L_8814B(x, v)                                   \
+	(BIT_CLEAR_HI0Q_TXBD_DESA_L_8814B(x) | BIT_HI0Q_TXBD_DESA_L_8814B(v))
+
+/* 2 REG_HI0Q_TXBD_DESA_H_8814B */
+
+#define BIT_SHIFT_HI0Q_TXBD_DESA_H_8814B 0
+#define BIT_MASK_HI0Q_TXBD_DESA_H_8814B 0xffffffffL
+#define BIT_HI0Q_TXBD_DESA_H_8814B(x)                                          \
+	(((x) & BIT_MASK_HI0Q_TXBD_DESA_H_8814B)                               \
+	 << BIT_SHIFT_HI0Q_TXBD_DESA_H_8814B)
+#define BITS_HI0Q_TXBD_DESA_H_8814B                                            \
+	(BIT_MASK_HI0Q_TXBD_DESA_H_8814B << BIT_SHIFT_HI0Q_TXBD_DESA_H_8814B)
+#define BIT_CLEAR_HI0Q_TXBD_DESA_H_8814B(x)                                    \
+	((x) & (~BITS_HI0Q_TXBD_DESA_H_8814B))
+#define BIT_GET_HI0Q_TXBD_DESA_H_8814B(x)                                      \
+	(((x) >> BIT_SHIFT_HI0Q_TXBD_DESA_H_8814B) &                           \
+	 BIT_MASK_HI0Q_TXBD_DESA_H_8814B)
+#define BIT_SET_HI0Q_TXBD_DESA_H_8814B(x, v)                                   \
+	(BIT_CLEAR_HI0Q_TXBD_DESA_H_8814B(x) | BIT_HI0Q_TXBD_DESA_H_8814B(v))
+
+/* 2 REG_HI1Q_TXBD_DESA_L_8814B */
+
+#define BIT_SHIFT_HI1Q_TXBD_DESA_L_8814B 0
+#define BIT_MASK_HI1Q_TXBD_DESA_L_8814B 0xffffffffL
+#define BIT_HI1Q_TXBD_DESA_L_8814B(x)                                          \
+	(((x) & BIT_MASK_HI1Q_TXBD_DESA_L_8814B)                               \
+	 << BIT_SHIFT_HI1Q_TXBD_DESA_L_8814B)
+#define BITS_HI1Q_TXBD_DESA_L_8814B                                            \
+	(BIT_MASK_HI1Q_TXBD_DESA_L_8814B << BIT_SHIFT_HI1Q_TXBD_DESA_L_8814B)
+#define BIT_CLEAR_HI1Q_TXBD_DESA_L_8814B(x)                                    \
+	((x) & (~BITS_HI1Q_TXBD_DESA_L_8814B))
+#define BIT_GET_HI1Q_TXBD_DESA_L_8814B(x)                                      \
+	(((x) >> BIT_SHIFT_HI1Q_TXBD_DESA_L_8814B) &                           \
+	 BIT_MASK_HI1Q_TXBD_DESA_L_8814B)
+#define BIT_SET_HI1Q_TXBD_DESA_L_8814B(x, v)                                   \
+	(BIT_CLEAR_HI1Q_TXBD_DESA_L_8814B(x) | BIT_HI1Q_TXBD_DESA_L_8814B(v))
+
+/* 2 REG_HI1Q_TXBD_DESA_H_8814B */
+
+#define BIT_SHIFT_HI1Q_TXBD_DESA_H_8814B 0
+#define BIT_MASK_HI1Q_TXBD_DESA_H_8814B 0xffffffffL
+#define BIT_HI1Q_TXBD_DESA_H_8814B(x)                                          \
+	(((x) & BIT_MASK_HI1Q_TXBD_DESA_H_8814B)                               \
+	 << BIT_SHIFT_HI1Q_TXBD_DESA_H_8814B)
+#define BITS_HI1Q_TXBD_DESA_H_8814B                                            \
+	(BIT_MASK_HI1Q_TXBD_DESA_H_8814B << BIT_SHIFT_HI1Q_TXBD_DESA_H_8814B)
+#define BIT_CLEAR_HI1Q_TXBD_DESA_H_8814B(x)                                    \
+	((x) & (~BITS_HI1Q_TXBD_DESA_H_8814B))
+#define BIT_GET_HI1Q_TXBD_DESA_H_8814B(x)                                      \
+	(((x) >> BIT_SHIFT_HI1Q_TXBD_DESA_H_8814B) &                           \
+	 BIT_MASK_HI1Q_TXBD_DESA_H_8814B)
+#define BIT_SET_HI1Q_TXBD_DESA_H_8814B(x, v)                                   \
+	(BIT_CLEAR_HI1Q_TXBD_DESA_H_8814B(x) | BIT_HI1Q_TXBD_DESA_H_8814B(v))
+
+/* 2 REG_HI2Q_TXBD_DESA_L_8814B */
+
+#define BIT_SHIFT_HI2Q_TXBD_DESA_L_8814B 0
+#define BIT_MASK_HI2Q_TXBD_DESA_L_8814B 0xffffffffL
+#define BIT_HI2Q_TXBD_DESA_L_8814B(x)                                          \
+	(((x) & BIT_MASK_HI2Q_TXBD_DESA_L_8814B)                               \
+	 << BIT_SHIFT_HI2Q_TXBD_DESA_L_8814B)
+#define BITS_HI2Q_TXBD_DESA_L_8814B                                            \
+	(BIT_MASK_HI2Q_TXBD_DESA_L_8814B << BIT_SHIFT_HI2Q_TXBD_DESA_L_8814B)
+#define BIT_CLEAR_HI2Q_TXBD_DESA_L_8814B(x)                                    \
+	((x) & (~BITS_HI2Q_TXBD_DESA_L_8814B))
+#define BIT_GET_HI2Q_TXBD_DESA_L_8814B(x)                                      \
+	(((x) >> BIT_SHIFT_HI2Q_TXBD_DESA_L_8814B) &                           \
+	 BIT_MASK_HI2Q_TXBD_DESA_L_8814B)
+#define BIT_SET_HI2Q_TXBD_DESA_L_8814B(x, v)                                   \
+	(BIT_CLEAR_HI2Q_TXBD_DESA_L_8814B(x) | BIT_HI2Q_TXBD_DESA_L_8814B(v))
+
+/* 2 REG_HI2Q_TXBD_DESA_H_8814B */
+
+#define BIT_SHIFT_HI2Q_TXBD_DESA_H_8814B 0
+#define BIT_MASK_HI2Q_TXBD_DESA_H_8814B 0xffffffffL
+#define BIT_HI2Q_TXBD_DESA_H_8814B(x)                                          \
+	(((x) & BIT_MASK_HI2Q_TXBD_DESA_H_8814B)                               \
+	 << BIT_SHIFT_HI2Q_TXBD_DESA_H_8814B)
+#define BITS_HI2Q_TXBD_DESA_H_8814B                                            \
+	(BIT_MASK_HI2Q_TXBD_DESA_H_8814B << BIT_SHIFT_HI2Q_TXBD_DESA_H_8814B)
+#define BIT_CLEAR_HI2Q_TXBD_DESA_H_8814B(x)                                    \
+	((x) & (~BITS_HI2Q_TXBD_DESA_H_8814B))
+#define BIT_GET_HI2Q_TXBD_DESA_H_8814B(x)                                      \
+	(((x) >> BIT_SHIFT_HI2Q_TXBD_DESA_H_8814B) &                           \
+	 BIT_MASK_HI2Q_TXBD_DESA_H_8814B)
+#define BIT_SET_HI2Q_TXBD_DESA_H_8814B(x, v)                                   \
+	(BIT_CLEAR_HI2Q_TXBD_DESA_H_8814B(x) | BIT_HI2Q_TXBD_DESA_H_8814B(v))
+
+/* 2 REG_HI3Q_TXBD_DESA_L_8814B */
+
+#define BIT_SHIFT_HI3Q_TXBD_DESA_L_8814B 0
+#define BIT_MASK_HI3Q_TXBD_DESA_L_8814B 0xffffffffL
+#define BIT_HI3Q_TXBD_DESA_L_8814B(x)                                          \
+	(((x) & BIT_MASK_HI3Q_TXBD_DESA_L_8814B)                               \
+	 << BIT_SHIFT_HI3Q_TXBD_DESA_L_8814B)
+#define BITS_HI3Q_TXBD_DESA_L_8814B                                            \
+	(BIT_MASK_HI3Q_TXBD_DESA_L_8814B << BIT_SHIFT_HI3Q_TXBD_DESA_L_8814B)
+#define BIT_CLEAR_HI3Q_TXBD_DESA_L_8814B(x)                                    \
+	((x) & (~BITS_HI3Q_TXBD_DESA_L_8814B))
+#define BIT_GET_HI3Q_TXBD_DESA_L_8814B(x)                                      \
+	(((x) >> BIT_SHIFT_HI3Q_TXBD_DESA_L_8814B) &                           \
+	 BIT_MASK_HI3Q_TXBD_DESA_L_8814B)
+#define BIT_SET_HI3Q_TXBD_DESA_L_8814B(x, v)                                   \
+	(BIT_CLEAR_HI3Q_TXBD_DESA_L_8814B(x) | BIT_HI3Q_TXBD_DESA_L_8814B(v))
+
+/* 2 REG_HI3Q_TXBD_DESA_H_8814B */
+
+#define BIT_SHIFT_HI3Q_TXBD_DESA_H_8814B 0
+#define BIT_MASK_HI3Q_TXBD_DESA_H_8814B 0xffffffffL
+#define BIT_HI3Q_TXBD_DESA_H_8814B(x)                                          \
+	(((x) & BIT_MASK_HI3Q_TXBD_DESA_H_8814B)                               \
+	 << BIT_SHIFT_HI3Q_TXBD_DESA_H_8814B)
+#define BITS_HI3Q_TXBD_DESA_H_8814B                                            \
+	(BIT_MASK_HI3Q_TXBD_DESA_H_8814B << BIT_SHIFT_HI3Q_TXBD_DESA_H_8814B)
+#define BIT_CLEAR_HI3Q_TXBD_DESA_H_8814B(x)                                    \
+	((x) & (~BITS_HI3Q_TXBD_DESA_H_8814B))
+#define BIT_GET_HI3Q_TXBD_DESA_H_8814B(x)                                      \
+	(((x) >> BIT_SHIFT_HI3Q_TXBD_DESA_H_8814B) &                           \
+	 BIT_MASK_HI3Q_TXBD_DESA_H_8814B)
+#define BIT_SET_HI3Q_TXBD_DESA_H_8814B(x, v)                                   \
+	(BIT_CLEAR_HI3Q_TXBD_DESA_H_8814B(x) | BIT_HI3Q_TXBD_DESA_H_8814B(v))
+
+/* 2 REG_HI4Q_TXBD_DESA_L_8814B */
+
+#define BIT_SHIFT_HI4Q_TXBD_DESA_L_8814B 0
+#define BIT_MASK_HI4Q_TXBD_DESA_L_8814B 0xffffffffL
+#define BIT_HI4Q_TXBD_DESA_L_8814B(x)                                          \
+	(((x) & BIT_MASK_HI4Q_TXBD_DESA_L_8814B)                               \
+	 << BIT_SHIFT_HI4Q_TXBD_DESA_L_8814B)
+#define BITS_HI4Q_TXBD_DESA_L_8814B                                            \
+	(BIT_MASK_HI4Q_TXBD_DESA_L_8814B << BIT_SHIFT_HI4Q_TXBD_DESA_L_8814B)
+#define BIT_CLEAR_HI4Q_TXBD_DESA_L_8814B(x)                                    \
+	((x) & (~BITS_HI4Q_TXBD_DESA_L_8814B))
+#define BIT_GET_HI4Q_TXBD_DESA_L_8814B(x)                                      \
+	(((x) >> BIT_SHIFT_HI4Q_TXBD_DESA_L_8814B) &                           \
+	 BIT_MASK_HI4Q_TXBD_DESA_L_8814B)
+#define BIT_SET_HI4Q_TXBD_DESA_L_8814B(x, v)                                   \
+	(BIT_CLEAR_HI4Q_TXBD_DESA_L_8814B(x) | BIT_HI4Q_TXBD_DESA_L_8814B(v))
+
+/* 2 REG_HI4Q_TXBD_DESA_H_8814B */
+
+#define BIT_SHIFT_HI4Q_TXBD_DESA_H_8814B 0
+#define BIT_MASK_HI4Q_TXBD_DESA_H_8814B 0xffffffffL
+#define BIT_HI4Q_TXBD_DESA_H_8814B(x)                                          \
+	(((x) & BIT_MASK_HI4Q_TXBD_DESA_H_8814B)                               \
+	 << BIT_SHIFT_HI4Q_TXBD_DESA_H_8814B)
+#define BITS_HI4Q_TXBD_DESA_H_8814B                                            \
+	(BIT_MASK_HI4Q_TXBD_DESA_H_8814B << BIT_SHIFT_HI4Q_TXBD_DESA_H_8814B)
+#define BIT_CLEAR_HI4Q_TXBD_DESA_H_8814B(x)                                    \
+	((x) & (~BITS_HI4Q_TXBD_DESA_H_8814B))
+#define BIT_GET_HI4Q_TXBD_DESA_H_8814B(x)                                      \
+	(((x) >> BIT_SHIFT_HI4Q_TXBD_DESA_H_8814B) &                           \
+	 BIT_MASK_HI4Q_TXBD_DESA_H_8814B)
+#define BIT_SET_HI4Q_TXBD_DESA_H_8814B(x, v)                                   \
+	(BIT_CLEAR_HI4Q_TXBD_DESA_H_8814B(x) | BIT_HI4Q_TXBD_DESA_H_8814B(v))
+
+/* 2 REG_HI5Q_TXBD_DESA_L_8814B */
+
+#define BIT_SHIFT_HI5Q_TXBD_DESA_L_8814B 0
+#define BIT_MASK_HI5Q_TXBD_DESA_L_8814B 0xffffffffL
+#define BIT_HI5Q_TXBD_DESA_L_8814B(x)                                          \
+	(((x) & BIT_MASK_HI5Q_TXBD_DESA_L_8814B)                               \
+	 << BIT_SHIFT_HI5Q_TXBD_DESA_L_8814B)
+#define BITS_HI5Q_TXBD_DESA_L_8814B                                            \
+	(BIT_MASK_HI5Q_TXBD_DESA_L_8814B << BIT_SHIFT_HI5Q_TXBD_DESA_L_8814B)
+#define BIT_CLEAR_HI5Q_TXBD_DESA_L_8814B(x)                                    \
+	((x) & (~BITS_HI5Q_TXBD_DESA_L_8814B))
+#define BIT_GET_HI5Q_TXBD_DESA_L_8814B(x)                                      \
+	(((x) >> BIT_SHIFT_HI5Q_TXBD_DESA_L_8814B) &                           \
+	 BIT_MASK_HI5Q_TXBD_DESA_L_8814B)
+#define BIT_SET_HI5Q_TXBD_DESA_L_8814B(x, v)                                   \
+	(BIT_CLEAR_HI5Q_TXBD_DESA_L_8814B(x) | BIT_HI5Q_TXBD_DESA_L_8814B(v))
+
+/* 2 REG_HI5Q_TXBD_DESA_H_8814B */
+
+#define BIT_SHIFT_HI5Q_TXBD_DESA_H_8814B 0
+#define BIT_MASK_HI5Q_TXBD_DESA_H_8814B 0xffffffffL
+#define BIT_HI5Q_TXBD_DESA_H_8814B(x)                                          \
+	(((x) & BIT_MASK_HI5Q_TXBD_DESA_H_8814B)                               \
+	 << BIT_SHIFT_HI5Q_TXBD_DESA_H_8814B)
+#define BITS_HI5Q_TXBD_DESA_H_8814B                                            \
+	(BIT_MASK_HI5Q_TXBD_DESA_H_8814B << BIT_SHIFT_HI5Q_TXBD_DESA_H_8814B)
+#define BIT_CLEAR_HI5Q_TXBD_DESA_H_8814B(x)                                    \
+	((x) & (~BITS_HI5Q_TXBD_DESA_H_8814B))
+#define BIT_GET_HI5Q_TXBD_DESA_H_8814B(x)                                      \
+	(((x) >> BIT_SHIFT_HI5Q_TXBD_DESA_H_8814B) &                           \
+	 BIT_MASK_HI5Q_TXBD_DESA_H_8814B)
+#define BIT_SET_HI5Q_TXBD_DESA_H_8814B(x, v)                                   \
+	(BIT_CLEAR_HI5Q_TXBD_DESA_H_8814B(x) | BIT_HI5Q_TXBD_DESA_H_8814B(v))
+
+/* 2 REG_HI6Q_TXBD_DESA_L_8814B */
+
+#define BIT_SHIFT_HI6Q_TXBD_DESA_L_8814B 0
+#define BIT_MASK_HI6Q_TXBD_DESA_L_8814B 0xffffffffL
+#define BIT_HI6Q_TXBD_DESA_L_8814B(x)                                          \
+	(((x) & BIT_MASK_HI6Q_TXBD_DESA_L_8814B)                               \
+	 << BIT_SHIFT_HI6Q_TXBD_DESA_L_8814B)
+#define BITS_HI6Q_TXBD_DESA_L_8814B                                            \
+	(BIT_MASK_HI6Q_TXBD_DESA_L_8814B << BIT_SHIFT_HI6Q_TXBD_DESA_L_8814B)
+#define BIT_CLEAR_HI6Q_TXBD_DESA_L_8814B(x)                                    \
+	((x) & (~BITS_HI6Q_TXBD_DESA_L_8814B))
+#define BIT_GET_HI6Q_TXBD_DESA_L_8814B(x)                                      \
+	(((x) >> BIT_SHIFT_HI6Q_TXBD_DESA_L_8814B) &                           \
+	 BIT_MASK_HI6Q_TXBD_DESA_L_8814B)
+#define BIT_SET_HI6Q_TXBD_DESA_L_8814B(x, v)                                   \
+	(BIT_CLEAR_HI6Q_TXBD_DESA_L_8814B(x) | BIT_HI6Q_TXBD_DESA_L_8814B(v))
+
+/* 2 REG_HI6Q_TXBD_DESA_H_8814B */
+
+#define BIT_SHIFT_HI6Q_TXBD_DESA_H_8814B 0
+#define BIT_MASK_HI6Q_TXBD_DESA_H_8814B 0xffffffffL
+#define BIT_HI6Q_TXBD_DESA_H_8814B(x)                                          \
+	(((x) & BIT_MASK_HI6Q_TXBD_DESA_H_8814B)                               \
+	 << BIT_SHIFT_HI6Q_TXBD_DESA_H_8814B)
+#define BITS_HI6Q_TXBD_DESA_H_8814B                                            \
+	(BIT_MASK_HI6Q_TXBD_DESA_H_8814B << BIT_SHIFT_HI6Q_TXBD_DESA_H_8814B)
+#define BIT_CLEAR_HI6Q_TXBD_DESA_H_8814B(x)                                    \
+	((x) & (~BITS_HI6Q_TXBD_DESA_H_8814B))
+#define BIT_GET_HI6Q_TXBD_DESA_H_8814B(x)                                      \
+	(((x) >> BIT_SHIFT_HI6Q_TXBD_DESA_H_8814B) &                           \
+	 BIT_MASK_HI6Q_TXBD_DESA_H_8814B)
+#define BIT_SET_HI6Q_TXBD_DESA_H_8814B(x, v)                                   \
+	(BIT_CLEAR_HI6Q_TXBD_DESA_H_8814B(x) | BIT_HI6Q_TXBD_DESA_H_8814B(v))
+
+/* 2 REG_HI7Q_TXBD_DESA_L_8814B */
+
+#define BIT_SHIFT_HI7Q_TXBD_DESA_L_8814B 0
+#define BIT_MASK_HI7Q_TXBD_DESA_L_8814B 0xffffffffL
+#define BIT_HI7Q_TXBD_DESA_L_8814B(x)                                          \
+	(((x) & BIT_MASK_HI7Q_TXBD_DESA_L_8814B)                               \
+	 << BIT_SHIFT_HI7Q_TXBD_DESA_L_8814B)
+#define BITS_HI7Q_TXBD_DESA_L_8814B                                            \
+	(BIT_MASK_HI7Q_TXBD_DESA_L_8814B << BIT_SHIFT_HI7Q_TXBD_DESA_L_8814B)
+#define BIT_CLEAR_HI7Q_TXBD_DESA_L_8814B(x)                                    \
+	((x) & (~BITS_HI7Q_TXBD_DESA_L_8814B))
+#define BIT_GET_HI7Q_TXBD_DESA_L_8814B(x)                                      \
+	(((x) >> BIT_SHIFT_HI7Q_TXBD_DESA_L_8814B) &                           \
+	 BIT_MASK_HI7Q_TXBD_DESA_L_8814B)
+#define BIT_SET_HI7Q_TXBD_DESA_L_8814B(x, v)                                   \
+	(BIT_CLEAR_HI7Q_TXBD_DESA_L_8814B(x) | BIT_HI7Q_TXBD_DESA_L_8814B(v))
+
+/* 2 REG_HI7Q_TXBD_DESA_H_8814B */
+
+#define BIT_SHIFT_HI7Q_TXBD_DESA_H_8814B 0
+#define BIT_MASK_HI7Q_TXBD_DESA_H_8814B 0xffffffffL
+#define BIT_HI7Q_TXBD_DESA_H_8814B(x)                                          \
+	(((x) & BIT_MASK_HI7Q_TXBD_DESA_H_8814B)                               \
+	 << BIT_SHIFT_HI7Q_TXBD_DESA_H_8814B)
+#define BITS_HI7Q_TXBD_DESA_H_8814B                                            \
+	(BIT_MASK_HI7Q_TXBD_DESA_H_8814B << BIT_SHIFT_HI7Q_TXBD_DESA_H_8814B)
+#define BIT_CLEAR_HI7Q_TXBD_DESA_H_8814B(x)                                    \
+	((x) & (~BITS_HI7Q_TXBD_DESA_H_8814B))
+#define BIT_GET_HI7Q_TXBD_DESA_H_8814B(x)                                      \
+	(((x) >> BIT_SHIFT_HI7Q_TXBD_DESA_H_8814B) &                           \
+	 BIT_MASK_HI7Q_TXBD_DESA_H_8814B)
+#define BIT_SET_HI7Q_TXBD_DESA_H_8814B(x, v)                                   \
+	(BIT_CLEAR_HI7Q_TXBD_DESA_H_8814B(x) | BIT_HI7Q_TXBD_DESA_H_8814B(v))
+
+/* 2 REG_ACH8_ACH9_TXBD_NUM_8814B */
+#define BIT_PCIE_ACH9_FLAG_8814B BIT(30)
+
+#define BIT_SHIFT_ACH9_DESC_MODE_8814B 28
+#define BIT_MASK_ACH9_DESC_MODE_8814B 0x3
+#define BIT_ACH9_DESC_MODE_8814B(x)                                            \
+	(((x) & BIT_MASK_ACH9_DESC_MODE_8814B)                                 \
+	 << BIT_SHIFT_ACH9_DESC_MODE_8814B)
+#define BITS_ACH9_DESC_MODE_8814B                                              \
+	(BIT_MASK_ACH9_DESC_MODE_8814B << BIT_SHIFT_ACH9_DESC_MODE_8814B)
+#define BIT_CLEAR_ACH9_DESC_MODE_8814B(x) ((x) & (~BITS_ACH9_DESC_MODE_8814B))
+#define BIT_GET_ACH9_DESC_MODE_8814B(x)                                        \
+	(((x) >> BIT_SHIFT_ACH9_DESC_MODE_8814B) &                             \
+	 BIT_MASK_ACH9_DESC_MODE_8814B)
+#define BIT_SET_ACH9_DESC_MODE_8814B(x, v)                                     \
+	(BIT_CLEAR_ACH9_DESC_MODE_8814B(x) | BIT_ACH9_DESC_MODE_8814B(v))
+
+#define BIT_SHIFT_ACH9_DESC_NUM_8814B 16
+#define BIT_MASK_ACH9_DESC_NUM_8814B 0xfff
+#define BIT_ACH9_DESC_NUM_8814B(x)                                             \
+	(((x) & BIT_MASK_ACH9_DESC_NUM_8814B) << BIT_SHIFT_ACH9_DESC_NUM_8814B)
+#define BITS_ACH9_DESC_NUM_8814B                                               \
+	(BIT_MASK_ACH9_DESC_NUM_8814B << BIT_SHIFT_ACH9_DESC_NUM_8814B)
+#define BIT_CLEAR_ACH9_DESC_NUM_8814B(x) ((x) & (~BITS_ACH9_DESC_NUM_8814B))
+#define BIT_GET_ACH9_DESC_NUM_8814B(x)                                         \
+	(((x) >> BIT_SHIFT_ACH9_DESC_NUM_8814B) & BIT_MASK_ACH9_DESC_NUM_8814B)
+#define BIT_SET_ACH9_DESC_NUM_8814B(x, v)                                      \
+	(BIT_CLEAR_ACH9_DESC_NUM_8814B(x) | BIT_ACH9_DESC_NUM_8814B(v))
+
+#define BIT_PCIE_ACH8_FLAG_8814B BIT(14)
+
+#define BIT_SHIFT_ACH8_DESC_MODE_8814B 12
+#define BIT_MASK_ACH8_DESC_MODE_8814B 0x3
+#define BIT_ACH8_DESC_MODE_8814B(x)                                            \
+	(((x) & BIT_MASK_ACH8_DESC_MODE_8814B)                                 \
+	 << BIT_SHIFT_ACH8_DESC_MODE_8814B)
+#define BITS_ACH8_DESC_MODE_8814B                                              \
+	(BIT_MASK_ACH8_DESC_MODE_8814B << BIT_SHIFT_ACH8_DESC_MODE_8814B)
+#define BIT_CLEAR_ACH8_DESC_MODE_8814B(x) ((x) & (~BITS_ACH8_DESC_MODE_8814B))
+#define BIT_GET_ACH8_DESC_MODE_8814B(x)                                        \
+	(((x) >> BIT_SHIFT_ACH8_DESC_MODE_8814B) &                             \
+	 BIT_MASK_ACH8_DESC_MODE_8814B)
+#define BIT_SET_ACH8_DESC_MODE_8814B(x, v)                                     \
+	(BIT_CLEAR_ACH8_DESC_MODE_8814B(x) | BIT_ACH8_DESC_MODE_8814B(v))
+
+#define BIT_SHIFT_ACH8_DESC_NUM_8814B 0
+#define BIT_MASK_ACH8_DESC_NUM_8814B 0xfff
+#define BIT_ACH8_DESC_NUM_8814B(x)                                             \
+	(((x) & BIT_MASK_ACH8_DESC_NUM_8814B) << BIT_SHIFT_ACH8_DESC_NUM_8814B)
+#define BITS_ACH8_DESC_NUM_8814B                                               \
+	(BIT_MASK_ACH8_DESC_NUM_8814B << BIT_SHIFT_ACH8_DESC_NUM_8814B)
+#define BIT_CLEAR_ACH8_DESC_NUM_8814B(x) ((x) & (~BITS_ACH8_DESC_NUM_8814B))
+#define BIT_GET_ACH8_DESC_NUM_8814B(x)                                         \
+	(((x) >> BIT_SHIFT_ACH8_DESC_NUM_8814B) & BIT_MASK_ACH8_DESC_NUM_8814B)
+#define BIT_SET_ACH8_DESC_NUM_8814B(x, v)                                      \
+	(BIT_CLEAR_ACH8_DESC_NUM_8814B(x) | BIT_ACH8_DESC_NUM_8814B(v))
+
+/* 2 REG_ACH10_ACH11_TXBD_NUM_8814B */
+#define BIT_PCIE_ACH11_FLAG_8814B BIT(30)
+
+#define BIT_SHIFT_ACH11_DESC_MODE_8814B 28
+#define BIT_MASK_ACH11_DESC_MODE_8814B 0x3
+#define BIT_ACH11_DESC_MODE_8814B(x)                                           \
+	(((x) & BIT_MASK_ACH11_DESC_MODE_8814B)                                \
+	 << BIT_SHIFT_ACH11_DESC_MODE_8814B)
+#define BITS_ACH11_DESC_MODE_8814B                                             \
+	(BIT_MASK_ACH11_DESC_MODE_8814B << BIT_SHIFT_ACH11_DESC_MODE_8814B)
+#define BIT_CLEAR_ACH11_DESC_MODE_8814B(x) ((x) & (~BITS_ACH11_DESC_MODE_8814B))
+#define BIT_GET_ACH11_DESC_MODE_8814B(x)                                       \
+	(((x) >> BIT_SHIFT_ACH11_DESC_MODE_8814B) &                            \
+	 BIT_MASK_ACH11_DESC_MODE_8814B)
+#define BIT_SET_ACH11_DESC_MODE_8814B(x, v)                                    \
+	(BIT_CLEAR_ACH11_DESC_MODE_8814B(x) | BIT_ACH11_DESC_MODE_8814B(v))
+
+#define BIT_SHIFT_ACH11_DESC_NUM_8814B 16
+#define BIT_MASK_ACH11_DESC_NUM_8814B 0xfff
+#define BIT_ACH11_DESC_NUM_8814B(x)                                            \
+	(((x) & BIT_MASK_ACH11_DESC_NUM_8814B)                                 \
+	 << BIT_SHIFT_ACH11_DESC_NUM_8814B)
+#define BITS_ACH11_DESC_NUM_8814B                                              \
+	(BIT_MASK_ACH11_DESC_NUM_8814B << BIT_SHIFT_ACH11_DESC_NUM_8814B)
+#define BIT_CLEAR_ACH11_DESC_NUM_8814B(x) ((x) & (~BITS_ACH11_DESC_NUM_8814B))
+#define BIT_GET_ACH11_DESC_NUM_8814B(x)                                        \
+	(((x) >> BIT_SHIFT_ACH11_DESC_NUM_8814B) &                             \
+	 BIT_MASK_ACH11_DESC_NUM_8814B)
+#define BIT_SET_ACH11_DESC_NUM_8814B(x, v)                                     \
+	(BIT_CLEAR_ACH11_DESC_NUM_8814B(x) | BIT_ACH11_DESC_NUM_8814B(v))
+
+#define BIT_PCIE_ACH10_FLAG_8814B BIT(14)
+
+#define BIT_SHIFT_ACH10_DESC_MODE_8814B 12
+#define BIT_MASK_ACH10_DESC_MODE_8814B 0x3
+#define BIT_ACH10_DESC_MODE_8814B(x)                                           \
+	(((x) & BIT_MASK_ACH10_DESC_MODE_8814B)                                \
+	 << BIT_SHIFT_ACH10_DESC_MODE_8814B)
+#define BITS_ACH10_DESC_MODE_8814B                                             \
+	(BIT_MASK_ACH10_DESC_MODE_8814B << BIT_SHIFT_ACH10_DESC_MODE_8814B)
+#define BIT_CLEAR_ACH10_DESC_MODE_8814B(x) ((x) & (~BITS_ACH10_DESC_MODE_8814B))
+#define BIT_GET_ACH10_DESC_MODE_8814B(x)                                       \
+	(((x) >> BIT_SHIFT_ACH10_DESC_MODE_8814B) &                            \
+	 BIT_MASK_ACH10_DESC_MODE_8814B)
+#define BIT_SET_ACH10_DESC_MODE_8814B(x, v)                                    \
+	(BIT_CLEAR_ACH10_DESC_MODE_8814B(x) | BIT_ACH10_DESC_MODE_8814B(v))
+
+#define BIT_SHIFT_ACH10_DESC_NUM_8814B 0
+#define BIT_MASK_ACH10_DESC_NUM_8814B 0xfff
+#define BIT_ACH10_DESC_NUM_8814B(x)                                            \
+	(((x) & BIT_MASK_ACH10_DESC_NUM_8814B)                                 \
+	 << BIT_SHIFT_ACH10_DESC_NUM_8814B)
+#define BITS_ACH10_DESC_NUM_8814B                                              \
+	(BIT_MASK_ACH10_DESC_NUM_8814B << BIT_SHIFT_ACH10_DESC_NUM_8814B)
+#define BIT_CLEAR_ACH10_DESC_NUM_8814B(x) ((x) & (~BITS_ACH10_DESC_NUM_8814B))
+#define BIT_GET_ACH10_DESC_NUM_8814B(x)                                        \
+	(((x) >> BIT_SHIFT_ACH10_DESC_NUM_8814B) &                             \
+	 BIT_MASK_ACH10_DESC_NUM_8814B)
+#define BIT_SET_ACH10_DESC_NUM_8814B(x, v)                                     \
+	(BIT_CLEAR_ACH10_DESC_NUM_8814B(x) | BIT_ACH10_DESC_NUM_8814B(v))
+
+/* 2 REG_ACH12_ACH13_TXBD_NUM_8814B */
+#define BIT_PCIE_ACH13_FLAG_8814B BIT(30)
+
+#define BIT_SHIFT_ACH13_DESC_MODE_8814B 28
+#define BIT_MASK_ACH13_DESC_MODE_8814B 0x3
+#define BIT_ACH13_DESC_MODE_8814B(x)                                           \
+	(((x) & BIT_MASK_ACH13_DESC_MODE_8814B)                                \
+	 << BIT_SHIFT_ACH13_DESC_MODE_8814B)
+#define BITS_ACH13_DESC_MODE_8814B                                             \
+	(BIT_MASK_ACH13_DESC_MODE_8814B << BIT_SHIFT_ACH13_DESC_MODE_8814B)
+#define BIT_CLEAR_ACH13_DESC_MODE_8814B(x) ((x) & (~BITS_ACH13_DESC_MODE_8814B))
+#define BIT_GET_ACH13_DESC_MODE_8814B(x)                                       \
+	(((x) >> BIT_SHIFT_ACH13_DESC_MODE_8814B) &                            \
+	 BIT_MASK_ACH13_DESC_MODE_8814B)
+#define BIT_SET_ACH13_DESC_MODE_8814B(x, v)                                    \
+	(BIT_CLEAR_ACH13_DESC_MODE_8814B(x) | BIT_ACH13_DESC_MODE_8814B(v))
+
+#define BIT_SHIFT_ACH13_DESC_NUM_8814B 16
+#define BIT_MASK_ACH13_DESC_NUM_8814B 0xfff
+#define BIT_ACH13_DESC_NUM_8814B(x)                                            \
+	(((x) & BIT_MASK_ACH13_DESC_NUM_8814B)                                 \
+	 << BIT_SHIFT_ACH13_DESC_NUM_8814B)
+#define BITS_ACH13_DESC_NUM_8814B                                              \
+	(BIT_MASK_ACH13_DESC_NUM_8814B << BIT_SHIFT_ACH13_DESC_NUM_8814B)
+#define BIT_CLEAR_ACH13_DESC_NUM_8814B(x) ((x) & (~BITS_ACH13_DESC_NUM_8814B))
+#define BIT_GET_ACH13_DESC_NUM_8814B(x)                                        \
+	(((x) >> BIT_SHIFT_ACH13_DESC_NUM_8814B) &                             \
+	 BIT_MASK_ACH13_DESC_NUM_8814B)
+#define BIT_SET_ACH13_DESC_NUM_8814B(x, v)                                     \
+	(BIT_CLEAR_ACH13_DESC_NUM_8814B(x) | BIT_ACH13_DESC_NUM_8814B(v))
+
+#define BIT_PCIE_ACH12_FLAG_8814B BIT(14)
+
+#define BIT_SHIFT_ACH12_DESC_MODE_8814B 12
+#define BIT_MASK_ACH12_DESC_MODE_8814B 0x3
+#define BIT_ACH12_DESC_MODE_8814B(x)                                           \
+	(((x) & BIT_MASK_ACH12_DESC_MODE_8814B)                                \
+	 << BIT_SHIFT_ACH12_DESC_MODE_8814B)
+#define BITS_ACH12_DESC_MODE_8814B                                             \
+	(BIT_MASK_ACH12_DESC_MODE_8814B << BIT_SHIFT_ACH12_DESC_MODE_8814B)
+#define BIT_CLEAR_ACH12_DESC_MODE_8814B(x) ((x) & (~BITS_ACH12_DESC_MODE_8814B))
+#define BIT_GET_ACH12_DESC_MODE_8814B(x)                                       \
+	(((x) >> BIT_SHIFT_ACH12_DESC_MODE_8814B) &                            \
+	 BIT_MASK_ACH12_DESC_MODE_8814B)
+#define BIT_SET_ACH12_DESC_MODE_8814B(x, v)                                    \
+	(BIT_CLEAR_ACH12_DESC_MODE_8814B(x) | BIT_ACH12_DESC_MODE_8814B(v))
+
+#define BIT_SHIFT_ACH12_DESC_NUM_8814B 0
+#define BIT_MASK_ACH12_DESC_NUM_8814B 0xfff
+#define BIT_ACH12_DESC_NUM_8814B(x)                                            \
+	(((x) & BIT_MASK_ACH12_DESC_NUM_8814B)                                 \
+	 << BIT_SHIFT_ACH12_DESC_NUM_8814B)
+#define BITS_ACH12_DESC_NUM_8814B                                              \
+	(BIT_MASK_ACH12_DESC_NUM_8814B << BIT_SHIFT_ACH12_DESC_NUM_8814B)
+#define BIT_CLEAR_ACH12_DESC_NUM_8814B(x) ((x) & (~BITS_ACH12_DESC_NUM_8814B))
+#define BIT_GET_ACH12_DESC_NUM_8814B(x)                                        \
+	(((x) >> BIT_SHIFT_ACH12_DESC_NUM_8814B) &                             \
+	 BIT_MASK_ACH12_DESC_NUM_8814B)
+#define BIT_SET_ACH12_DESC_NUM_8814B(x, v)                                     \
+	(BIT_CLEAR_ACH12_DESC_NUM_8814B(x) | BIT_ACH12_DESC_NUM_8814B(v))
+
+/* 2 REG_OLD_DEHANG_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+#define BIT_OLD_DEHANG_8814B BIT(1)
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_ACH4_TXBD_DESA_L_8814B */
+
+#define BIT_SHIFT_ACH4_TXBD_DESA_L_8814B 0
+#define BIT_MASK_ACH4_TXBD_DESA_L_8814B 0xffffffffL
+#define BIT_ACH4_TXBD_DESA_L_8814B(x)                                          \
+	(((x) & BIT_MASK_ACH4_TXBD_DESA_L_8814B)                               \
+	 << BIT_SHIFT_ACH4_TXBD_DESA_L_8814B)
+#define BITS_ACH4_TXBD_DESA_L_8814B                                            \
+	(BIT_MASK_ACH4_TXBD_DESA_L_8814B << BIT_SHIFT_ACH4_TXBD_DESA_L_8814B)
+#define BIT_CLEAR_ACH4_TXBD_DESA_L_8814B(x)                                    \
+	((x) & (~BITS_ACH4_TXBD_DESA_L_8814B))
+#define BIT_GET_ACH4_TXBD_DESA_L_8814B(x)                                      \
+	(((x) >> BIT_SHIFT_ACH4_TXBD_DESA_L_8814B) &                           \
+	 BIT_MASK_ACH4_TXBD_DESA_L_8814B)
+#define BIT_SET_ACH4_TXBD_DESA_L_8814B(x, v)                                   \
+	(BIT_CLEAR_ACH4_TXBD_DESA_L_8814B(x) | BIT_ACH4_TXBD_DESA_L_8814B(v))
+
+/* 2 REG_ACH4_TXBD_DESA_H_8814B */
+
+#define BIT_SHIFT_ACH4_TXBD_DESA_H_8814B 0
+#define BIT_MASK_ACH4_TXBD_DESA_H_8814B 0xffffffffL
+#define BIT_ACH4_TXBD_DESA_H_8814B(x)                                          \
+	(((x) & BIT_MASK_ACH4_TXBD_DESA_H_8814B)                               \
+	 << BIT_SHIFT_ACH4_TXBD_DESA_H_8814B)
+#define BITS_ACH4_TXBD_DESA_H_8814B                                            \
+	(BIT_MASK_ACH4_TXBD_DESA_H_8814B << BIT_SHIFT_ACH4_TXBD_DESA_H_8814B)
+#define BIT_CLEAR_ACH4_TXBD_DESA_H_8814B(x)                                    \
+	((x) & (~BITS_ACH4_TXBD_DESA_H_8814B))
+#define BIT_GET_ACH4_TXBD_DESA_H_8814B(x)                                      \
+	(((x) >> BIT_SHIFT_ACH4_TXBD_DESA_H_8814B) &                           \
+	 BIT_MASK_ACH4_TXBD_DESA_H_8814B)
+#define BIT_SET_ACH4_TXBD_DESA_H_8814B(x, v)                                   \
+	(BIT_CLEAR_ACH4_TXBD_DESA_H_8814B(x) | BIT_ACH4_TXBD_DESA_H_8814B(v))
+
+/* 2 REG_HI8Q_TXBD_DESA_L_8814B */
+
+#define BIT_SHIFT_HI8Q_TXBD_DESA_L_8814B 0
+#define BIT_MASK_HI8Q_TXBD_DESA_L_8814B 0xffffffffL
+#define BIT_HI8Q_TXBD_DESA_L_8814B(x)                                          \
+	(((x) & BIT_MASK_HI8Q_TXBD_DESA_L_8814B)                               \
+	 << BIT_SHIFT_HI8Q_TXBD_DESA_L_8814B)
+#define BITS_HI8Q_TXBD_DESA_L_8814B                                            \
+	(BIT_MASK_HI8Q_TXBD_DESA_L_8814B << BIT_SHIFT_HI8Q_TXBD_DESA_L_8814B)
+#define BIT_CLEAR_HI8Q_TXBD_DESA_L_8814B(x)                                    \
+	((x) & (~BITS_HI8Q_TXBD_DESA_L_8814B))
+#define BIT_GET_HI8Q_TXBD_DESA_L_8814B(x)                                      \
+	(((x) >> BIT_SHIFT_HI8Q_TXBD_DESA_L_8814B) &                           \
+	 BIT_MASK_HI8Q_TXBD_DESA_L_8814B)
+#define BIT_SET_HI8Q_TXBD_DESA_L_8814B(x, v)                                   \
+	(BIT_CLEAR_HI8Q_TXBD_DESA_L_8814B(x) | BIT_HI8Q_TXBD_DESA_L_8814B(v))
+
+/* 2 REG_HI8Q_TXBD_DESA_H_8814B */
+
+#define BIT_SHIFT_HI8Q_TXBD_DESA_H_8814B 0
+#define BIT_MASK_HI8Q_TXBD_DESA_H_8814B 0xffffffffL
+#define BIT_HI8Q_TXBD_DESA_H_8814B(x)                                          \
+	(((x) & BIT_MASK_HI8Q_TXBD_DESA_H_8814B)                               \
+	 << BIT_SHIFT_HI8Q_TXBD_DESA_H_8814B)
+#define BITS_HI8Q_TXBD_DESA_H_8814B                                            \
+	(BIT_MASK_HI8Q_TXBD_DESA_H_8814B << BIT_SHIFT_HI8Q_TXBD_DESA_H_8814B)
+#define BIT_CLEAR_HI8Q_TXBD_DESA_H_8814B(x)                                    \
+	((x) & (~BITS_HI8Q_TXBD_DESA_H_8814B))
+#define BIT_GET_HI8Q_TXBD_DESA_H_8814B(x)                                      \
+	(((x) >> BIT_SHIFT_HI8Q_TXBD_DESA_H_8814B) &                           \
+	 BIT_MASK_HI8Q_TXBD_DESA_H_8814B)
+#define BIT_SET_HI8Q_TXBD_DESA_H_8814B(x, v)                                   \
+	(BIT_CLEAR_HI8Q_TXBD_DESA_H_8814B(x) | BIT_HI8Q_TXBD_DESA_H_8814B(v))
+
+/* 2 REG_HI9Q_TXBD_DESA_L_8814B */
+
+#define BIT_SHIFT_HI9Q_TXBD_DESA_L_8814B 0
+#define BIT_MASK_HI9Q_TXBD_DESA_L_8814B 0xffffffffL
+#define BIT_HI9Q_TXBD_DESA_L_8814B(x)                                          \
+	(((x) & BIT_MASK_HI9Q_TXBD_DESA_L_8814B)                               \
+	 << BIT_SHIFT_HI9Q_TXBD_DESA_L_8814B)
+#define BITS_HI9Q_TXBD_DESA_L_8814B                                            \
+	(BIT_MASK_HI9Q_TXBD_DESA_L_8814B << BIT_SHIFT_HI9Q_TXBD_DESA_L_8814B)
+#define BIT_CLEAR_HI9Q_TXBD_DESA_L_8814B(x)                                    \
+	((x) & (~BITS_HI9Q_TXBD_DESA_L_8814B))
+#define BIT_GET_HI9Q_TXBD_DESA_L_8814B(x)                                      \
+	(((x) >> BIT_SHIFT_HI9Q_TXBD_DESA_L_8814B) &                           \
+	 BIT_MASK_HI9Q_TXBD_DESA_L_8814B)
+#define BIT_SET_HI9Q_TXBD_DESA_L_8814B(x, v)                                   \
+	(BIT_CLEAR_HI9Q_TXBD_DESA_L_8814B(x) | BIT_HI9Q_TXBD_DESA_L_8814B(v))
+
+/* 2 REG_HI9Q_TXBD_DESA_H_8814B */
+
+#define BIT_SHIFT_HI9Q_TXBD_DESA_H_8814B 0
+#define BIT_MASK_HI9Q_TXBD_DESA_H_8814B 0xffffffffL
+#define BIT_HI9Q_TXBD_DESA_H_8814B(x)                                          \
+	(((x) & BIT_MASK_HI9Q_TXBD_DESA_H_8814B)                               \
+	 << BIT_SHIFT_HI9Q_TXBD_DESA_H_8814B)
+#define BITS_HI9Q_TXBD_DESA_H_8814B                                            \
+	(BIT_MASK_HI9Q_TXBD_DESA_H_8814B << BIT_SHIFT_HI9Q_TXBD_DESA_H_8814B)
+#define BIT_CLEAR_HI9Q_TXBD_DESA_H_8814B(x)                                    \
+	((x) & (~BITS_HI9Q_TXBD_DESA_H_8814B))
+#define BIT_GET_HI9Q_TXBD_DESA_H_8814B(x)                                      \
+	(((x) >> BIT_SHIFT_HI9Q_TXBD_DESA_H_8814B) &                           \
+	 BIT_MASK_HI9Q_TXBD_DESA_H_8814B)
+#define BIT_SET_HI9Q_TXBD_DESA_H_8814B(x, v)                                   \
+	(BIT_CLEAR_HI9Q_TXBD_DESA_H_8814B(x) | BIT_HI9Q_TXBD_DESA_H_8814B(v))
+
+/* 2 REG_HI10Q_TXBD_DESA_L_8814B */
+
+#define BIT_SHIFT_HI10Q_TXBD_DESA_L_8814B 0
+#define BIT_MASK_HI10Q_TXBD_DESA_L_8814B 0xffffffffL
+#define BIT_HI10Q_TXBD_DESA_L_8814B(x)                                         \
+	(((x) & BIT_MASK_HI10Q_TXBD_DESA_L_8814B)                              \
+	 << BIT_SHIFT_HI10Q_TXBD_DESA_L_8814B)
+#define BITS_HI10Q_TXBD_DESA_L_8814B                                           \
+	(BIT_MASK_HI10Q_TXBD_DESA_L_8814B << BIT_SHIFT_HI10Q_TXBD_DESA_L_8814B)
+#define BIT_CLEAR_HI10Q_TXBD_DESA_L_8814B(x)                                   \
+	((x) & (~BITS_HI10Q_TXBD_DESA_L_8814B))
+#define BIT_GET_HI10Q_TXBD_DESA_L_8814B(x)                                     \
+	(((x) >> BIT_SHIFT_HI10Q_TXBD_DESA_L_8814B) &                          \
+	 BIT_MASK_HI10Q_TXBD_DESA_L_8814B)
+#define BIT_SET_HI10Q_TXBD_DESA_L_8814B(x, v)                                  \
+	(BIT_CLEAR_HI10Q_TXBD_DESA_L_8814B(x) | BIT_HI10Q_TXBD_DESA_L_8814B(v))
+
+/* 2 REG_HI10Q_TXBD_DESA_H_8814B */
+
+#define BIT_SHIFT_HI10Q_TXBD_DESA_H_8814B 0
+#define BIT_MASK_HI10Q_TXBD_DESA_H_8814B 0xffffffffL
+#define BIT_HI10Q_TXBD_DESA_H_8814B(x)                                         \
+	(((x) & BIT_MASK_HI10Q_TXBD_DESA_H_8814B)                              \
+	 << BIT_SHIFT_HI10Q_TXBD_DESA_H_8814B)
+#define BITS_HI10Q_TXBD_DESA_H_8814B                                           \
+	(BIT_MASK_HI10Q_TXBD_DESA_H_8814B << BIT_SHIFT_HI10Q_TXBD_DESA_H_8814B)
+#define BIT_CLEAR_HI10Q_TXBD_DESA_H_8814B(x)                                   \
+	((x) & (~BITS_HI10Q_TXBD_DESA_H_8814B))
+#define BIT_GET_HI10Q_TXBD_DESA_H_8814B(x)                                     \
+	(((x) >> BIT_SHIFT_HI10Q_TXBD_DESA_H_8814B) &                          \
+	 BIT_MASK_HI10Q_TXBD_DESA_H_8814B)
+#define BIT_SET_HI10Q_TXBD_DESA_H_8814B(x, v)                                  \
+	(BIT_CLEAR_HI10Q_TXBD_DESA_H_8814B(x) | BIT_HI10Q_TXBD_DESA_H_8814B(v))
+
+/* 2 REG_HI11Q_TXBD_DESA_L_8814B */
+
+#define BIT_SHIFT_HI11Q_TXBD_DESA_L_8814B 0
+#define BIT_MASK_HI11Q_TXBD_DESA_L_8814B 0xffffffffL
+#define BIT_HI11Q_TXBD_DESA_L_8814B(x)                                         \
+	(((x) & BIT_MASK_HI11Q_TXBD_DESA_L_8814B)                              \
+	 << BIT_SHIFT_HI11Q_TXBD_DESA_L_8814B)
+#define BITS_HI11Q_TXBD_DESA_L_8814B                                           \
+	(BIT_MASK_HI11Q_TXBD_DESA_L_8814B << BIT_SHIFT_HI11Q_TXBD_DESA_L_8814B)
+#define BIT_CLEAR_HI11Q_TXBD_DESA_L_8814B(x)                                   \
+	((x) & (~BITS_HI11Q_TXBD_DESA_L_8814B))
+#define BIT_GET_HI11Q_TXBD_DESA_L_8814B(x)                                     \
+	(((x) >> BIT_SHIFT_HI11Q_TXBD_DESA_L_8814B) &                          \
+	 BIT_MASK_HI11Q_TXBD_DESA_L_8814B)
+#define BIT_SET_HI11Q_TXBD_DESA_L_8814B(x, v)                                  \
+	(BIT_CLEAR_HI11Q_TXBD_DESA_L_8814B(x) | BIT_HI11Q_TXBD_DESA_L_8814B(v))
+
+/* 2 REG_HI11Q_TXBD_DESA_H_8814B */
+
+#define BIT_SHIFT_HI11Q_TXBD_DESA_H_8814B 0
+#define BIT_MASK_HI11Q_TXBD_DESA_H_8814B 0xffffffffL
+#define BIT_HI11Q_TXBD_DESA_H_8814B(x)                                         \
+	(((x) & BIT_MASK_HI11Q_TXBD_DESA_H_8814B)                              \
+	 << BIT_SHIFT_HI11Q_TXBD_DESA_H_8814B)
+#define BITS_HI11Q_TXBD_DESA_H_8814B                                           \
+	(BIT_MASK_HI11Q_TXBD_DESA_H_8814B << BIT_SHIFT_HI11Q_TXBD_DESA_H_8814B)
+#define BIT_CLEAR_HI11Q_TXBD_DESA_H_8814B(x)                                   \
+	((x) & (~BITS_HI11Q_TXBD_DESA_H_8814B))
+#define BIT_GET_HI11Q_TXBD_DESA_H_8814B(x)                                     \
+	(((x) >> BIT_SHIFT_HI11Q_TXBD_DESA_H_8814B) &                          \
+	 BIT_MASK_HI11Q_TXBD_DESA_H_8814B)
+#define BIT_SET_HI11Q_TXBD_DESA_H_8814B(x, v)                                  \
+	(BIT_CLEAR_HI11Q_TXBD_DESA_H_8814B(x) | BIT_HI11Q_TXBD_DESA_H_8814B(v))
+
+/* 2 REG_HI12Q_TXBD_DESA_L_8814B */
+
+#define BIT_SHIFT_HI12Q_TXBD_DESA_L_8814B 0
+#define BIT_MASK_HI12Q_TXBD_DESA_L_8814B 0xffffffffL
+#define BIT_HI12Q_TXBD_DESA_L_8814B(x)                                         \
+	(((x) & BIT_MASK_HI12Q_TXBD_DESA_L_8814B)                              \
+	 << BIT_SHIFT_HI12Q_TXBD_DESA_L_8814B)
+#define BITS_HI12Q_TXBD_DESA_L_8814B                                           \
+	(BIT_MASK_HI12Q_TXBD_DESA_L_8814B << BIT_SHIFT_HI12Q_TXBD_DESA_L_8814B)
+#define BIT_CLEAR_HI12Q_TXBD_DESA_L_8814B(x)                                   \
+	((x) & (~BITS_HI12Q_TXBD_DESA_L_8814B))
+#define BIT_GET_HI12Q_TXBD_DESA_L_8814B(x)                                     \
+	(((x) >> BIT_SHIFT_HI12Q_TXBD_DESA_L_8814B) &                          \
+	 BIT_MASK_HI12Q_TXBD_DESA_L_8814B)
+#define BIT_SET_HI12Q_TXBD_DESA_L_8814B(x, v)                                  \
+	(BIT_CLEAR_HI12Q_TXBD_DESA_L_8814B(x) | BIT_HI12Q_TXBD_DESA_L_8814B(v))
+
+/* 2 REG_HI12Q_TXBD_DESA_H_8814B */
+
+#define BIT_SHIFT_HI12Q_TXBD_DESA_H_8814B 0
+#define BIT_MASK_HI12Q_TXBD_DESA_H_8814B 0xffffffffL
+#define BIT_HI12Q_TXBD_DESA_H_8814B(x)                                         \
+	(((x) & BIT_MASK_HI12Q_TXBD_DESA_H_8814B)                              \
+	 << BIT_SHIFT_HI12Q_TXBD_DESA_H_8814B)
+#define BITS_HI12Q_TXBD_DESA_H_8814B                                           \
+	(BIT_MASK_HI12Q_TXBD_DESA_H_8814B << BIT_SHIFT_HI12Q_TXBD_DESA_H_8814B)
+#define BIT_CLEAR_HI12Q_TXBD_DESA_H_8814B(x)                                   \
+	((x) & (~BITS_HI12Q_TXBD_DESA_H_8814B))
+#define BIT_GET_HI12Q_TXBD_DESA_H_8814B(x)                                     \
+	(((x) >> BIT_SHIFT_HI12Q_TXBD_DESA_H_8814B) &                          \
+	 BIT_MASK_HI12Q_TXBD_DESA_H_8814B)
+#define BIT_SET_HI12Q_TXBD_DESA_H_8814B(x, v)                                  \
+	(BIT_CLEAR_HI12Q_TXBD_DESA_H_8814B(x) | BIT_HI12Q_TXBD_DESA_H_8814B(v))
+
+/* 2 REG_HI13Q_TXBD_DESA_L_8814B */
+
+#define BIT_SHIFT_HI13Q_TXBD_DESA_L_8814B 0
+#define BIT_MASK_HI13Q_TXBD_DESA_L_8814B 0xffffffffL
+#define BIT_HI13Q_TXBD_DESA_L_8814B(x)                                         \
+	(((x) & BIT_MASK_HI13Q_TXBD_DESA_L_8814B)                              \
+	 << BIT_SHIFT_HI13Q_TXBD_DESA_L_8814B)
+#define BITS_HI13Q_TXBD_DESA_L_8814B                                           \
+	(BIT_MASK_HI13Q_TXBD_DESA_L_8814B << BIT_SHIFT_HI13Q_TXBD_DESA_L_8814B)
+#define BIT_CLEAR_HI13Q_TXBD_DESA_L_8814B(x)                                   \
+	((x) & (~BITS_HI13Q_TXBD_DESA_L_8814B))
+#define BIT_GET_HI13Q_TXBD_DESA_L_8814B(x)                                     \
+	(((x) >> BIT_SHIFT_HI13Q_TXBD_DESA_L_8814B) &                          \
+	 BIT_MASK_HI13Q_TXBD_DESA_L_8814B)
+#define BIT_SET_HI13Q_TXBD_DESA_L_8814B(x, v)                                  \
+	(BIT_CLEAR_HI13Q_TXBD_DESA_L_8814B(x) | BIT_HI13Q_TXBD_DESA_L_8814B(v))
+
+/* 2 REG_HI13Q_TXBD_DESA_H_8814B */
+
+#define BIT_SHIFT_HI13Q_TXBD_DESA_H_8814B 0
+#define BIT_MASK_HI13Q_TXBD_DESA_H_8814B 0xffffffffL
+#define BIT_HI13Q_TXBD_DESA_H_8814B(x)                                         \
+	(((x) & BIT_MASK_HI13Q_TXBD_DESA_H_8814B)                              \
+	 << BIT_SHIFT_HI13Q_TXBD_DESA_H_8814B)
+#define BITS_HI13Q_TXBD_DESA_H_8814B                                           \
+	(BIT_MASK_HI13Q_TXBD_DESA_H_8814B << BIT_SHIFT_HI13Q_TXBD_DESA_H_8814B)
+#define BIT_CLEAR_HI13Q_TXBD_DESA_H_8814B(x)                                   \
+	((x) & (~BITS_HI13Q_TXBD_DESA_H_8814B))
+#define BIT_GET_HI13Q_TXBD_DESA_H_8814B(x)                                     \
+	(((x) >> BIT_SHIFT_HI13Q_TXBD_DESA_H_8814B) &                          \
+	 BIT_MASK_HI13Q_TXBD_DESA_H_8814B)
+#define BIT_SET_HI13Q_TXBD_DESA_H_8814B(x, v)                                  \
+	(BIT_CLEAR_HI13Q_TXBD_DESA_H_8814B(x) | BIT_HI13Q_TXBD_DESA_H_8814B(v))
+
+/* 2 REG_HI14Q_TXBD_DESA_L_8814B */
+
+#define BIT_SHIFT_HI14Q_TXBD_DESA_L_8814B 0
+#define BIT_MASK_HI14Q_TXBD_DESA_L_8814B 0xffffffffL
+#define BIT_HI14Q_TXBD_DESA_L_8814B(x)                                         \
+	(((x) & BIT_MASK_HI14Q_TXBD_DESA_L_8814B)                              \
+	 << BIT_SHIFT_HI14Q_TXBD_DESA_L_8814B)
+#define BITS_HI14Q_TXBD_DESA_L_8814B                                           \
+	(BIT_MASK_HI14Q_TXBD_DESA_L_8814B << BIT_SHIFT_HI14Q_TXBD_DESA_L_8814B)
+#define BIT_CLEAR_HI14Q_TXBD_DESA_L_8814B(x)                                   \
+	((x) & (~BITS_HI14Q_TXBD_DESA_L_8814B))
+#define BIT_GET_HI14Q_TXBD_DESA_L_8814B(x)                                     \
+	(((x) >> BIT_SHIFT_HI14Q_TXBD_DESA_L_8814B) &                          \
+	 BIT_MASK_HI14Q_TXBD_DESA_L_8814B)
+#define BIT_SET_HI14Q_TXBD_DESA_L_8814B(x, v)                                  \
+	(BIT_CLEAR_HI14Q_TXBD_DESA_L_8814B(x) | BIT_HI14Q_TXBD_DESA_L_8814B(v))
+
+/* 2 REG_HI14Q_TXBD_DESA_H_8814B */
+
+#define BIT_SHIFT_HI14Q_TXBD_DESA_H_8814B 0
+#define BIT_MASK_HI14Q_TXBD_DESA_H_8814B 0xffffffffL
+#define BIT_HI14Q_TXBD_DESA_H_8814B(x)                                         \
+	(((x) & BIT_MASK_HI14Q_TXBD_DESA_H_8814B)                              \
+	 << BIT_SHIFT_HI14Q_TXBD_DESA_H_8814B)
+#define BITS_HI14Q_TXBD_DESA_H_8814B                                           \
+	(BIT_MASK_HI14Q_TXBD_DESA_H_8814B << BIT_SHIFT_HI14Q_TXBD_DESA_H_8814B)
+#define BIT_CLEAR_HI14Q_TXBD_DESA_H_8814B(x)                                   \
+	((x) & (~BITS_HI14Q_TXBD_DESA_H_8814B))
+#define BIT_GET_HI14Q_TXBD_DESA_H_8814B(x)                                     \
+	(((x) >> BIT_SHIFT_HI14Q_TXBD_DESA_H_8814B) &                          \
+	 BIT_MASK_HI14Q_TXBD_DESA_H_8814B)
+#define BIT_SET_HI14Q_TXBD_DESA_H_8814B(x, v)                                  \
+	(BIT_CLEAR_HI14Q_TXBD_DESA_H_8814B(x) | BIT_HI14Q_TXBD_DESA_H_8814B(v))
+
+/* 2 REG_HI15Q_TXBD_DESA_L_8814B */
+
+#define BIT_SHIFT_HI15Q_TXBD_DESA_L_8814B 0
+#define BIT_MASK_HI15Q_TXBD_DESA_L_8814B 0xffffffffL
+#define BIT_HI15Q_TXBD_DESA_L_8814B(x)                                         \
+	(((x) & BIT_MASK_HI15Q_TXBD_DESA_L_8814B)                              \
+	 << BIT_SHIFT_HI15Q_TXBD_DESA_L_8814B)
+#define BITS_HI15Q_TXBD_DESA_L_8814B                                           \
+	(BIT_MASK_HI15Q_TXBD_DESA_L_8814B << BIT_SHIFT_HI15Q_TXBD_DESA_L_8814B)
+#define BIT_CLEAR_HI15Q_TXBD_DESA_L_8814B(x)                                   \
+	((x) & (~BITS_HI15Q_TXBD_DESA_L_8814B))
+#define BIT_GET_HI15Q_TXBD_DESA_L_8814B(x)                                     \
+	(((x) >> BIT_SHIFT_HI15Q_TXBD_DESA_L_8814B) &                          \
+	 BIT_MASK_HI15Q_TXBD_DESA_L_8814B)
+#define BIT_SET_HI15Q_TXBD_DESA_L_8814B(x, v)                                  \
+	(BIT_CLEAR_HI15Q_TXBD_DESA_L_8814B(x) | BIT_HI15Q_TXBD_DESA_L_8814B(v))
+
+/* 2 REG_HI15Q_TXBD_DESA_H_8814B */
+
+#define BIT_SHIFT_HI15Q_TXBD_DESA_H_8814B 0
+#define BIT_MASK_HI15Q_TXBD_DESA_H_8814B 0xffffffffL
+#define BIT_HI15Q_TXBD_DESA_H_8814B(x)                                         \
+	(((x) & BIT_MASK_HI15Q_TXBD_DESA_H_8814B)                              \
+	 << BIT_SHIFT_HI15Q_TXBD_DESA_H_8814B)
+#define BITS_HI15Q_TXBD_DESA_H_8814B                                           \
+	(BIT_MASK_HI15Q_TXBD_DESA_H_8814B << BIT_SHIFT_HI15Q_TXBD_DESA_H_8814B)
+#define BIT_CLEAR_HI15Q_TXBD_DESA_H_8814B(x)                                   \
+	((x) & (~BITS_HI15Q_TXBD_DESA_H_8814B))
+#define BIT_GET_HI15Q_TXBD_DESA_H_8814B(x)                                     \
+	(((x) >> BIT_SHIFT_HI15Q_TXBD_DESA_H_8814B) &                          \
+	 BIT_MASK_HI15Q_TXBD_DESA_H_8814B)
+#define BIT_SET_HI15Q_TXBD_DESA_H_8814B(x, v)                                  \
+	(BIT_CLEAR_HI15Q_TXBD_DESA_H_8814B(x) | BIT_HI15Q_TXBD_DESA_H_8814B(v))
+
+/* 2 REG_HI16Q_TXBD_DESA_L_8814B */
+
+#define BIT_SHIFT_HI16Q_TXBD_DESA_L_8814B 0
+#define BIT_MASK_HI16Q_TXBD_DESA_L_8814B 0xffffffffL
+#define BIT_HI16Q_TXBD_DESA_L_8814B(x)                                         \
+	(((x) & BIT_MASK_HI16Q_TXBD_DESA_L_8814B)                              \
+	 << BIT_SHIFT_HI16Q_TXBD_DESA_L_8814B)
+#define BITS_HI16Q_TXBD_DESA_L_8814B                                           \
+	(BIT_MASK_HI16Q_TXBD_DESA_L_8814B << BIT_SHIFT_HI16Q_TXBD_DESA_L_8814B)
+#define BIT_CLEAR_HI16Q_TXBD_DESA_L_8814B(x)                                   \
+	((x) & (~BITS_HI16Q_TXBD_DESA_L_8814B))
+#define BIT_GET_HI16Q_TXBD_DESA_L_8814B(x)                                     \
+	(((x) >> BIT_SHIFT_HI16Q_TXBD_DESA_L_8814B) &                          \
+	 BIT_MASK_HI16Q_TXBD_DESA_L_8814B)
+#define BIT_SET_HI16Q_TXBD_DESA_L_8814B(x, v)                                  \
+	(BIT_CLEAR_HI16Q_TXBD_DESA_L_8814B(x) | BIT_HI16Q_TXBD_DESA_L_8814B(v))
+
+/* 2 REG_HI16Q_TXBD_DESA_H_8814B */
+
+#define BIT_SHIFT_HI16Q_TXBD_DESA_H_8814B 0
+#define BIT_MASK_HI16Q_TXBD_DESA_H_8814B 0xffffffffL
+#define BIT_HI16Q_TXBD_DESA_H_8814B(x)                                         \
+	(((x) & BIT_MASK_HI16Q_TXBD_DESA_H_8814B)                              \
+	 << BIT_SHIFT_HI16Q_TXBD_DESA_H_8814B)
+#define BITS_HI16Q_TXBD_DESA_H_8814B                                           \
+	(BIT_MASK_HI16Q_TXBD_DESA_H_8814B << BIT_SHIFT_HI16Q_TXBD_DESA_H_8814B)
+#define BIT_CLEAR_HI16Q_TXBD_DESA_H_8814B(x)                                   \
+	((x) & (~BITS_HI16Q_TXBD_DESA_H_8814B))
+#define BIT_GET_HI16Q_TXBD_DESA_H_8814B(x)                                     \
+	(((x) >> BIT_SHIFT_HI16Q_TXBD_DESA_H_8814B) &                          \
+	 BIT_MASK_HI16Q_TXBD_DESA_H_8814B)
+#define BIT_SET_HI16Q_TXBD_DESA_H_8814B(x, v)                                  \
+	(BIT_CLEAR_HI16Q_TXBD_DESA_H_8814B(x) | BIT_HI16Q_TXBD_DESA_H_8814B(v))
+
+/* 2 REG_HI17Q_TXBD_DESA_L_8814B */
+
+#define BIT_SHIFT_HI17Q_TXBD_DESA_L_8814B 0
+#define BIT_MASK_HI17Q_TXBD_DESA_L_8814B 0xffffffffL
+#define BIT_HI17Q_TXBD_DESA_L_8814B(x)                                         \
+	(((x) & BIT_MASK_HI17Q_TXBD_DESA_L_8814B)                              \
+	 << BIT_SHIFT_HI17Q_TXBD_DESA_L_8814B)
+#define BITS_HI17Q_TXBD_DESA_L_8814B                                           \
+	(BIT_MASK_HI17Q_TXBD_DESA_L_8814B << BIT_SHIFT_HI17Q_TXBD_DESA_L_8814B)
+#define BIT_CLEAR_HI17Q_TXBD_DESA_L_8814B(x)                                   \
+	((x) & (~BITS_HI17Q_TXBD_DESA_L_8814B))
+#define BIT_GET_HI17Q_TXBD_DESA_L_8814B(x)                                     \
+	(((x) >> BIT_SHIFT_HI17Q_TXBD_DESA_L_8814B) &                          \
+	 BIT_MASK_HI17Q_TXBD_DESA_L_8814B)
+#define BIT_SET_HI17Q_TXBD_DESA_L_8814B(x, v)                                  \
+	(BIT_CLEAR_HI17Q_TXBD_DESA_L_8814B(x) | BIT_HI17Q_TXBD_DESA_L_8814B(v))
+
+/* 2 REG_HI17Q_TXBD_DESA_H_8814B */
+
+#define BIT_SHIFT_HI17Q_TXBD_DESA_H_8814B 0
+#define BIT_MASK_HI17Q_TXBD_DESA_H_8814B 0xffffffffL
+#define BIT_HI17Q_TXBD_DESA_H_8814B(x)                                         \
+	(((x) & BIT_MASK_HI17Q_TXBD_DESA_H_8814B)                              \
+	 << BIT_SHIFT_HI17Q_TXBD_DESA_H_8814B)
+#define BITS_HI17Q_TXBD_DESA_H_8814B                                           \
+	(BIT_MASK_HI17Q_TXBD_DESA_H_8814B << BIT_SHIFT_HI17Q_TXBD_DESA_H_8814B)
+#define BIT_CLEAR_HI17Q_TXBD_DESA_H_8814B(x)                                   \
+	((x) & (~BITS_HI17Q_TXBD_DESA_H_8814B))
+#define BIT_GET_HI17Q_TXBD_DESA_H_8814B(x)                                     \
+	(((x) >> BIT_SHIFT_HI17Q_TXBD_DESA_H_8814B) &                          \
+	 BIT_MASK_HI17Q_TXBD_DESA_H_8814B)
+#define BIT_SET_HI17Q_TXBD_DESA_H_8814B(x, v)                                  \
+	(BIT_CLEAR_HI17Q_TXBD_DESA_H_8814B(x) | BIT_HI17Q_TXBD_DESA_H_8814B(v))
+
+/* 2 REG_HI18Q_TXBD_DESA_L_8814B */
+
+#define BIT_SHIFT_HI18Q_TXBD_DESA_L_8814B 0
+#define BIT_MASK_HI18Q_TXBD_DESA_L_8814B 0xffffffffL
+#define BIT_HI18Q_TXBD_DESA_L_8814B(x)                                         \
+	(((x) & BIT_MASK_HI18Q_TXBD_DESA_L_8814B)                              \
+	 << BIT_SHIFT_HI18Q_TXBD_DESA_L_8814B)
+#define BITS_HI18Q_TXBD_DESA_L_8814B                                           \
+	(BIT_MASK_HI18Q_TXBD_DESA_L_8814B << BIT_SHIFT_HI18Q_TXBD_DESA_L_8814B)
+#define BIT_CLEAR_HI18Q_TXBD_DESA_L_8814B(x)                                   \
+	((x) & (~BITS_HI18Q_TXBD_DESA_L_8814B))
+#define BIT_GET_HI18Q_TXBD_DESA_L_8814B(x)                                     \
+	(((x) >> BIT_SHIFT_HI18Q_TXBD_DESA_L_8814B) &                          \
+	 BIT_MASK_HI18Q_TXBD_DESA_L_8814B)
+#define BIT_SET_HI18Q_TXBD_DESA_L_8814B(x, v)                                  \
+	(BIT_CLEAR_HI18Q_TXBD_DESA_L_8814B(x) | BIT_HI18Q_TXBD_DESA_L_8814B(v))
+
+/* 2 REG_HI18Q_TXBD_DESA_H_8814B */
+
+#define BIT_SHIFT_HI18Q_TXBD_DESA_H_8814B 0
+#define BIT_MASK_HI18Q_TXBD_DESA_H_8814B 0xffffffffL
+#define BIT_HI18Q_TXBD_DESA_H_8814B(x)                                         \
+	(((x) & BIT_MASK_HI18Q_TXBD_DESA_H_8814B)                              \
+	 << BIT_SHIFT_HI18Q_TXBD_DESA_H_8814B)
+#define BITS_HI18Q_TXBD_DESA_H_8814B                                           \
+	(BIT_MASK_HI18Q_TXBD_DESA_H_8814B << BIT_SHIFT_HI18Q_TXBD_DESA_H_8814B)
+#define BIT_CLEAR_HI18Q_TXBD_DESA_H_8814B(x)                                   \
+	((x) & (~BITS_HI18Q_TXBD_DESA_H_8814B))
+#define BIT_GET_HI18Q_TXBD_DESA_H_8814B(x)                                     \
+	(((x) >> BIT_SHIFT_HI18Q_TXBD_DESA_H_8814B) &                          \
+	 BIT_MASK_HI18Q_TXBD_DESA_H_8814B)
+#define BIT_SET_HI18Q_TXBD_DESA_H_8814B(x, v)                                  \
+	(BIT_CLEAR_HI18Q_TXBD_DESA_H_8814B(x) | BIT_HI18Q_TXBD_DESA_H_8814B(v))
+
+/* 2 REG_HI19Q_TXBD_DESA_L_8814B */
+
+#define BIT_SHIFT_HI19Q_TXBD_DESA_L_8814B 0
+#define BIT_MASK_HI19Q_TXBD_DESA_L_8814B 0xffffffffL
+#define BIT_HI19Q_TXBD_DESA_L_8814B(x)                                         \
+	(((x) & BIT_MASK_HI19Q_TXBD_DESA_L_8814B)                              \
+	 << BIT_SHIFT_HI19Q_TXBD_DESA_L_8814B)
+#define BITS_HI19Q_TXBD_DESA_L_8814B                                           \
+	(BIT_MASK_HI19Q_TXBD_DESA_L_8814B << BIT_SHIFT_HI19Q_TXBD_DESA_L_8814B)
+#define BIT_CLEAR_HI19Q_TXBD_DESA_L_8814B(x)                                   \
+	((x) & (~BITS_HI19Q_TXBD_DESA_L_8814B))
+#define BIT_GET_HI19Q_TXBD_DESA_L_8814B(x)                                     \
+	(((x) >> BIT_SHIFT_HI19Q_TXBD_DESA_L_8814B) &                          \
+	 BIT_MASK_HI19Q_TXBD_DESA_L_8814B)
+#define BIT_SET_HI19Q_TXBD_DESA_L_8814B(x, v)                                  \
+	(BIT_CLEAR_HI19Q_TXBD_DESA_L_8814B(x) | BIT_HI19Q_TXBD_DESA_L_8814B(v))
+
+/* 2 REG_HI19Q_TXBD_DESA_H_8814B */
+
+#define BIT_SHIFT_HI19Q_TXBD_DESA_H_8814B 0
+#define BIT_MASK_HI19Q_TXBD_DESA_H_8814B 0xffffffffL
+#define BIT_HI19Q_TXBD_DESA_H_8814B(x)                                         \
+	(((x) & BIT_MASK_HI19Q_TXBD_DESA_H_8814B)                              \
+	 << BIT_SHIFT_HI19Q_TXBD_DESA_H_8814B)
+#define BITS_HI19Q_TXBD_DESA_H_8814B                                           \
+	(BIT_MASK_HI19Q_TXBD_DESA_H_8814B << BIT_SHIFT_HI19Q_TXBD_DESA_H_8814B)
+#define BIT_CLEAR_HI19Q_TXBD_DESA_H_8814B(x)                                   \
+	((x) & (~BITS_HI19Q_TXBD_DESA_H_8814B))
+#define BIT_GET_HI19Q_TXBD_DESA_H_8814B(x)                                     \
+	(((x) >> BIT_SHIFT_HI19Q_TXBD_DESA_H_8814B) &                          \
+	 BIT_MASK_HI19Q_TXBD_DESA_H_8814B)
+#define BIT_SET_HI19Q_TXBD_DESA_H_8814B(x, v)                                  \
+	(BIT_CLEAR_HI19Q_TXBD_DESA_H_8814B(x) | BIT_HI19Q_TXBD_DESA_H_8814B(v))
+
+/* 2 REG_BD_RWPTR_CLR6_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+#define BIT_CLR_P0HI19Q_HW_IDX_8814B BIT(25)
+#define BIT_CLR_P0HI18Q_HW_IDX_8814B BIT(24)
+#define BIT_CLR_P0HI17Q_HW_IDX_8814B BIT(23)
+#define BIT_CLR_P0HI16Q_HW_IDX_8814B BIT(22)
+
+/* 2 REG_NOT_VALID_8814B */
+#define BIT_CLR_P0HI19Q_HOST_IDX_8814B BIT(9)
+#define BIT_CLR_P0HI18Q_HOST_IDX_8814B BIT(8)
+#define BIT_CLR_P0HI17Q_HOST_IDX_8814B BIT(7)
+#define BIT_CLR_P0HI16Q_HOST_IDX_8814B BIT(6)
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_P0HI16Q_TXBD_IDX_8814B */
+
+#define BIT_SHIFT_P0HI16Q_HW_IDX_8814B 16
+#define BIT_MASK_P0HI16Q_HW_IDX_8814B 0xfff
+#define BIT_P0HI16Q_HW_IDX_8814B(x)                                            \
+	(((x) & BIT_MASK_P0HI16Q_HW_IDX_8814B)                                 \
+	 << BIT_SHIFT_P0HI16Q_HW_IDX_8814B)
+#define BITS_P0HI16Q_HW_IDX_8814B                                              \
+	(BIT_MASK_P0HI16Q_HW_IDX_8814B << BIT_SHIFT_P0HI16Q_HW_IDX_8814B)
+#define BIT_CLEAR_P0HI16Q_HW_IDX_8814B(x) ((x) & (~BITS_P0HI16Q_HW_IDX_8814B))
+#define BIT_GET_P0HI16Q_HW_IDX_8814B(x)                                        \
+	(((x) >> BIT_SHIFT_P0HI16Q_HW_IDX_8814B) &                             \
+	 BIT_MASK_P0HI16Q_HW_IDX_8814B)
+#define BIT_SET_P0HI16Q_HW_IDX_8814B(x, v)                                     \
+	(BIT_CLEAR_P0HI16Q_HW_IDX_8814B(x) | BIT_P0HI16Q_HW_IDX_8814B(v))
+
+#define BIT_SHIFT_P0HI16Q_HOST_IDX_8814B 0
+#define BIT_MASK_P0HI16Q_HOST_IDX_8814B 0xfff
+#define BIT_P0HI16Q_HOST_IDX_8814B(x)                                          \
+	(((x) & BIT_MASK_P0HI16Q_HOST_IDX_8814B)                               \
+	 << BIT_SHIFT_P0HI16Q_HOST_IDX_8814B)
+#define BITS_P0HI16Q_HOST_IDX_8814B                                            \
+	(BIT_MASK_P0HI16Q_HOST_IDX_8814B << BIT_SHIFT_P0HI16Q_HOST_IDX_8814B)
+#define BIT_CLEAR_P0HI16Q_HOST_IDX_8814B(x)                                    \
+	((x) & (~BITS_P0HI16Q_HOST_IDX_8814B))
+#define BIT_GET_P0HI16Q_HOST_IDX_8814B(x)                                      \
+	(((x) >> BIT_SHIFT_P0HI16Q_HOST_IDX_8814B) &                           \
+	 BIT_MASK_P0HI16Q_HOST_IDX_8814B)
+#define BIT_SET_P0HI16Q_HOST_IDX_8814B(x, v)                                   \
+	(BIT_CLEAR_P0HI16Q_HOST_IDX_8814B(x) | BIT_P0HI16Q_HOST_IDX_8814B(v))
+
+/* 2 REG_P0HI17Q_TXBD_IDX_8814B */
+
+#define BIT_SHIFT_P0HI17Q_HW_IDX_8814B 16
+#define BIT_MASK_P0HI17Q_HW_IDX_8814B 0xfff
+#define BIT_P0HI17Q_HW_IDX_8814B(x)                                            \
+	(((x) & BIT_MASK_P0HI17Q_HW_IDX_8814B)                                 \
+	 << BIT_SHIFT_P0HI17Q_HW_IDX_8814B)
+#define BITS_P0HI17Q_HW_IDX_8814B                                              \
+	(BIT_MASK_P0HI17Q_HW_IDX_8814B << BIT_SHIFT_P0HI17Q_HW_IDX_8814B)
+#define BIT_CLEAR_P0HI17Q_HW_IDX_8814B(x) ((x) & (~BITS_P0HI17Q_HW_IDX_8814B))
+#define BIT_GET_P0HI17Q_HW_IDX_8814B(x)                                        \
+	(((x) >> BIT_SHIFT_P0HI17Q_HW_IDX_8814B) &                             \
+	 BIT_MASK_P0HI17Q_HW_IDX_8814B)
+#define BIT_SET_P0HI17Q_HW_IDX_8814B(x, v)                                     \
+	(BIT_CLEAR_P0HI17Q_HW_IDX_8814B(x) | BIT_P0HI17Q_HW_IDX_8814B(v))
+
+#define BIT_SHIFT_P0HI17Q_HOST_IDX_8814B 0
+#define BIT_MASK_P0HI17Q_HOST_IDX_8814B 0xfff
+#define BIT_P0HI17Q_HOST_IDX_8814B(x)                                          \
+	(((x) & BIT_MASK_P0HI17Q_HOST_IDX_8814B)                               \
+	 << BIT_SHIFT_P0HI17Q_HOST_IDX_8814B)
+#define BITS_P0HI17Q_HOST_IDX_8814B                                            \
+	(BIT_MASK_P0HI17Q_HOST_IDX_8814B << BIT_SHIFT_P0HI17Q_HOST_IDX_8814B)
+#define BIT_CLEAR_P0HI17Q_HOST_IDX_8814B(x)                                    \
+	((x) & (~BITS_P0HI17Q_HOST_IDX_8814B))
+#define BIT_GET_P0HI17Q_HOST_IDX_8814B(x)                                      \
+	(((x) >> BIT_SHIFT_P0HI17Q_HOST_IDX_8814B) &                           \
+	 BIT_MASK_P0HI17Q_HOST_IDX_8814B)
+#define BIT_SET_P0HI17Q_HOST_IDX_8814B(x, v)                                   \
+	(BIT_CLEAR_P0HI17Q_HOST_IDX_8814B(x) | BIT_P0HI17Q_HOST_IDX_8814B(v))
+
+/* 2 REG_P0HI18Q_TXBD_IDX_8814B */
+
+#define BIT_SHIFT_P0HI18Q_HW_IDX_8814B 16
+#define BIT_MASK_P0HI18Q_HW_IDX_8814B 0xfff
+#define BIT_P0HI18Q_HW_IDX_8814B(x)                                            \
+	(((x) & BIT_MASK_P0HI18Q_HW_IDX_8814B)                                 \
+	 << BIT_SHIFT_P0HI18Q_HW_IDX_8814B)
+#define BITS_P0HI18Q_HW_IDX_8814B                                              \
+	(BIT_MASK_P0HI18Q_HW_IDX_8814B << BIT_SHIFT_P0HI18Q_HW_IDX_8814B)
+#define BIT_CLEAR_P0HI18Q_HW_IDX_8814B(x) ((x) & (~BITS_P0HI18Q_HW_IDX_8814B))
+#define BIT_GET_P0HI18Q_HW_IDX_8814B(x)                                        \
+	(((x) >> BIT_SHIFT_P0HI18Q_HW_IDX_8814B) &                             \
+	 BIT_MASK_P0HI18Q_HW_IDX_8814B)
+#define BIT_SET_P0HI18Q_HW_IDX_8814B(x, v)                                     \
+	(BIT_CLEAR_P0HI18Q_HW_IDX_8814B(x) | BIT_P0HI18Q_HW_IDX_8814B(v))
+
+#define BIT_SHIFT_P0HI18Q_HOST_IDX_8814B 0
+#define BIT_MASK_P0HI18Q_HOST_IDX_8814B 0xfff
+#define BIT_P0HI18Q_HOST_IDX_8814B(x)                                          \
+	(((x) & BIT_MASK_P0HI18Q_HOST_IDX_8814B)                               \
+	 << BIT_SHIFT_P0HI18Q_HOST_IDX_8814B)
+#define BITS_P0HI18Q_HOST_IDX_8814B                                            \
+	(BIT_MASK_P0HI18Q_HOST_IDX_8814B << BIT_SHIFT_P0HI18Q_HOST_IDX_8814B)
+#define BIT_CLEAR_P0HI18Q_HOST_IDX_8814B(x)                                    \
+	((x) & (~BITS_P0HI18Q_HOST_IDX_8814B))
+#define BIT_GET_P0HI18Q_HOST_IDX_8814B(x)                                      \
+	(((x) >> BIT_SHIFT_P0HI18Q_HOST_IDX_8814B) &                           \
+	 BIT_MASK_P0HI18Q_HOST_IDX_8814B)
+#define BIT_SET_P0HI18Q_HOST_IDX_8814B(x, v)                                   \
+	(BIT_CLEAR_P0HI18Q_HOST_IDX_8814B(x) | BIT_P0HI18Q_HOST_IDX_8814B(v))
+
+/* 2 REG_P0HI19Q_TXBD_IDX_8814B */
+
+#define BIT_SHIFT_P0HI19Q_HW_IDX_8814B 16
+#define BIT_MASK_P0HI19Q_HW_IDX_8814B 0xfff
+#define BIT_P0HI19Q_HW_IDX_8814B(x)                                            \
+	(((x) & BIT_MASK_P0HI19Q_HW_IDX_8814B)                                 \
+	 << BIT_SHIFT_P0HI19Q_HW_IDX_8814B)
+#define BITS_P0HI19Q_HW_IDX_8814B                                              \
+	(BIT_MASK_P0HI19Q_HW_IDX_8814B << BIT_SHIFT_P0HI19Q_HW_IDX_8814B)
+#define BIT_CLEAR_P0HI19Q_HW_IDX_8814B(x) ((x) & (~BITS_P0HI19Q_HW_IDX_8814B))
+#define BIT_GET_P0HI19Q_HW_IDX_8814B(x)                                        \
+	(((x) >> BIT_SHIFT_P0HI19Q_HW_IDX_8814B) &                             \
+	 BIT_MASK_P0HI19Q_HW_IDX_8814B)
+#define BIT_SET_P0HI19Q_HW_IDX_8814B(x, v)                                     \
+	(BIT_CLEAR_P0HI19Q_HW_IDX_8814B(x) | BIT_P0HI19Q_HW_IDX_8814B(v))
+
+#define BIT_SHIFT_P0HI19Q_HOST_IDX_8814B 0
+#define BIT_MASK_P0HI19Q_HOST_IDX_8814B 0xfff
+#define BIT_P0HI19Q_HOST_IDX_8814B(x)                                          \
+	(((x) & BIT_MASK_P0HI19Q_HOST_IDX_8814B)                               \
+	 << BIT_SHIFT_P0HI19Q_HOST_IDX_8814B)
+#define BITS_P0HI19Q_HOST_IDX_8814B                                            \
+	(BIT_MASK_P0HI19Q_HOST_IDX_8814B << BIT_SHIFT_P0HI19Q_HOST_IDX_8814B)
+#define BIT_CLEAR_P0HI19Q_HOST_IDX_8814B(x)                                    \
+	((x) & (~BITS_P0HI19Q_HOST_IDX_8814B))
+#define BIT_GET_P0HI19Q_HOST_IDX_8814B(x)                                      \
+	(((x) >> BIT_SHIFT_P0HI19Q_HOST_IDX_8814B) &                           \
+	 BIT_MASK_P0HI19Q_HOST_IDX_8814B)
+#define BIT_SET_P0HI19Q_HOST_IDX_8814B(x, v)                                   \
+	(BIT_CLEAR_P0HI19Q_HOST_IDX_8814B(x) | BIT_P0HI19Q_HOST_IDX_8814B(v))
+
+/* 2 REG_P0HI16Q_HI17Q_TXBD_NUM_8814B */
+#define BIT_P0HI17Q_FLAG_8814B BIT(30)
+
+#define BIT_SHIFT_P0HI17Q_DESC_MODE_8814B 28
+#define BIT_MASK_P0HI17Q_DESC_MODE_8814B 0x3
+#define BIT_P0HI17Q_DESC_MODE_8814B(x)                                         \
+	(((x) & BIT_MASK_P0HI17Q_DESC_MODE_8814B)                              \
+	 << BIT_SHIFT_P0HI17Q_DESC_MODE_8814B)
+#define BITS_P0HI17Q_DESC_MODE_8814B                                           \
+	(BIT_MASK_P0HI17Q_DESC_MODE_8814B << BIT_SHIFT_P0HI17Q_DESC_MODE_8814B)
+#define BIT_CLEAR_P0HI17Q_DESC_MODE_8814B(x)                                   \
+	((x) & (~BITS_P0HI17Q_DESC_MODE_8814B))
+#define BIT_GET_P0HI17Q_DESC_MODE_8814B(x)                                     \
+	(((x) >> BIT_SHIFT_P0HI17Q_DESC_MODE_8814B) &                          \
+	 BIT_MASK_P0HI17Q_DESC_MODE_8814B)
+#define BIT_SET_P0HI17Q_DESC_MODE_8814B(x, v)                                  \
+	(BIT_CLEAR_P0HI17Q_DESC_MODE_8814B(x) | BIT_P0HI17Q_DESC_MODE_8814B(v))
+
+#define BIT_SHIFT_P0HI17Q_DESC_NUM_8814B 16
+#define BIT_MASK_P0HI17Q_DESC_NUM_8814B 0xfff
+#define BIT_P0HI17Q_DESC_NUM_8814B(x)                                          \
+	(((x) & BIT_MASK_P0HI17Q_DESC_NUM_8814B)                               \
+	 << BIT_SHIFT_P0HI17Q_DESC_NUM_8814B)
+#define BITS_P0HI17Q_DESC_NUM_8814B                                            \
+	(BIT_MASK_P0HI17Q_DESC_NUM_8814B << BIT_SHIFT_P0HI17Q_DESC_NUM_8814B)
+#define BIT_CLEAR_P0HI17Q_DESC_NUM_8814B(x)                                    \
+	((x) & (~BITS_P0HI17Q_DESC_NUM_8814B))
+#define BIT_GET_P0HI17Q_DESC_NUM_8814B(x)                                      \
+	(((x) >> BIT_SHIFT_P0HI17Q_DESC_NUM_8814B) &                           \
+	 BIT_MASK_P0HI17Q_DESC_NUM_8814B)
+#define BIT_SET_P0HI17Q_DESC_NUM_8814B(x, v)                                   \
+	(BIT_CLEAR_P0HI17Q_DESC_NUM_8814B(x) | BIT_P0HI17Q_DESC_NUM_8814B(v))
+
+#define BIT_P0HI16Q_FLAG_8814B BIT(14)
+
+#define BIT_SHIFT_P0HI16Q_DESC_MODE_8814B 12
+#define BIT_MASK_P0HI16Q_DESC_MODE_8814B 0x3
+#define BIT_P0HI16Q_DESC_MODE_8814B(x)                                         \
+	(((x) & BIT_MASK_P0HI16Q_DESC_MODE_8814B)                              \
+	 << BIT_SHIFT_P0HI16Q_DESC_MODE_8814B)
+#define BITS_P0HI16Q_DESC_MODE_8814B                                           \
+	(BIT_MASK_P0HI16Q_DESC_MODE_8814B << BIT_SHIFT_P0HI16Q_DESC_MODE_8814B)
+#define BIT_CLEAR_P0HI16Q_DESC_MODE_8814B(x)                                   \
+	((x) & (~BITS_P0HI16Q_DESC_MODE_8814B))
+#define BIT_GET_P0HI16Q_DESC_MODE_8814B(x)                                     \
+	(((x) >> BIT_SHIFT_P0HI16Q_DESC_MODE_8814B) &                          \
+	 BIT_MASK_P0HI16Q_DESC_MODE_8814B)
+#define BIT_SET_P0HI16Q_DESC_MODE_8814B(x, v)                                  \
+	(BIT_CLEAR_P0HI16Q_DESC_MODE_8814B(x) | BIT_P0HI16Q_DESC_MODE_8814B(v))
+
+#define BIT_SHIFT_P0HI16Q_DESC_NUM_8814B 0
+#define BIT_MASK_P0HI16Q_DESC_NUM_8814B 0xfff
+#define BIT_P0HI16Q_DESC_NUM_8814B(x)                                          \
+	(((x) & BIT_MASK_P0HI16Q_DESC_NUM_8814B)                               \
+	 << BIT_SHIFT_P0HI16Q_DESC_NUM_8814B)
+#define BITS_P0HI16Q_DESC_NUM_8814B                                            \
+	(BIT_MASK_P0HI16Q_DESC_NUM_8814B << BIT_SHIFT_P0HI16Q_DESC_NUM_8814B)
+#define BIT_CLEAR_P0HI16Q_DESC_NUM_8814B(x)                                    \
+	((x) & (~BITS_P0HI16Q_DESC_NUM_8814B))
+#define BIT_GET_P0HI16Q_DESC_NUM_8814B(x)                                      \
+	(((x) >> BIT_SHIFT_P0HI16Q_DESC_NUM_8814B) &                           \
+	 BIT_MASK_P0HI16Q_DESC_NUM_8814B)
+#define BIT_SET_P0HI16Q_DESC_NUM_8814B(x, v)                                   \
+	(BIT_CLEAR_P0HI16Q_DESC_NUM_8814B(x) | BIT_P0HI16Q_DESC_NUM_8814B(v))
+
+/* 2 REG_P0HI18Q_HI19Q_TXBD_NUM_8814B */
+#define BIT_P0HI19Q_FLAG_8814B BIT(30)
+
+#define BIT_SHIFT_P0HI19Q_DESC_MODE_8814B 28
+#define BIT_MASK_P0HI19Q_DESC_MODE_8814B 0x3
+#define BIT_P0HI19Q_DESC_MODE_8814B(x)                                         \
+	(((x) & BIT_MASK_P0HI19Q_DESC_MODE_8814B)                              \
+	 << BIT_SHIFT_P0HI19Q_DESC_MODE_8814B)
+#define BITS_P0HI19Q_DESC_MODE_8814B                                           \
+	(BIT_MASK_P0HI19Q_DESC_MODE_8814B << BIT_SHIFT_P0HI19Q_DESC_MODE_8814B)
+#define BIT_CLEAR_P0HI19Q_DESC_MODE_8814B(x)                                   \
+	((x) & (~BITS_P0HI19Q_DESC_MODE_8814B))
+#define BIT_GET_P0HI19Q_DESC_MODE_8814B(x)                                     \
+	(((x) >> BIT_SHIFT_P0HI19Q_DESC_MODE_8814B) &                          \
+	 BIT_MASK_P0HI19Q_DESC_MODE_8814B)
+#define BIT_SET_P0HI19Q_DESC_MODE_8814B(x, v)                                  \
+	(BIT_CLEAR_P0HI19Q_DESC_MODE_8814B(x) | BIT_P0HI19Q_DESC_MODE_8814B(v))
+
+#define BIT_SHIFT_P0HI19Q_DESC_NUM_8814B 16
+#define BIT_MASK_P0HI19Q_DESC_NUM_8814B 0xfff
+#define BIT_P0HI19Q_DESC_NUM_8814B(x)                                          \
+	(((x) & BIT_MASK_P0HI19Q_DESC_NUM_8814B)                               \
+	 << BIT_SHIFT_P0HI19Q_DESC_NUM_8814B)
+#define BITS_P0HI19Q_DESC_NUM_8814B                                            \
+	(BIT_MASK_P0HI19Q_DESC_NUM_8814B << BIT_SHIFT_P0HI19Q_DESC_NUM_8814B)
+#define BIT_CLEAR_P0HI19Q_DESC_NUM_8814B(x)                                    \
+	((x) & (~BITS_P0HI19Q_DESC_NUM_8814B))
+#define BIT_GET_P0HI19Q_DESC_NUM_8814B(x)                                      \
+	(((x) >> BIT_SHIFT_P0HI19Q_DESC_NUM_8814B) &                           \
+	 BIT_MASK_P0HI19Q_DESC_NUM_8814B)
+#define BIT_SET_P0HI19Q_DESC_NUM_8814B(x, v)                                   \
+	(BIT_CLEAR_P0HI19Q_DESC_NUM_8814B(x) | BIT_P0HI19Q_DESC_NUM_8814B(v))
+
+#define BIT_P0HI18Q_FLAG_8814B BIT(14)
+
+#define BIT_SHIFT_P0HI18Q_DESC_MODE_8814B 12
+#define BIT_MASK_P0HI18Q_DESC_MODE_8814B 0x3
+#define BIT_P0HI18Q_DESC_MODE_8814B(x)                                         \
+	(((x) & BIT_MASK_P0HI18Q_DESC_MODE_8814B)                              \
+	 << BIT_SHIFT_P0HI18Q_DESC_MODE_8814B)
+#define BITS_P0HI18Q_DESC_MODE_8814B                                           \
+	(BIT_MASK_P0HI18Q_DESC_MODE_8814B << BIT_SHIFT_P0HI18Q_DESC_MODE_8814B)
+#define BIT_CLEAR_P0HI18Q_DESC_MODE_8814B(x)                                   \
+	((x) & (~BITS_P0HI18Q_DESC_MODE_8814B))
+#define BIT_GET_P0HI18Q_DESC_MODE_8814B(x)                                     \
+	(((x) >> BIT_SHIFT_P0HI18Q_DESC_MODE_8814B) &                          \
+	 BIT_MASK_P0HI18Q_DESC_MODE_8814B)
+#define BIT_SET_P0HI18Q_DESC_MODE_8814B(x, v)                                  \
+	(BIT_CLEAR_P0HI18Q_DESC_MODE_8814B(x) | BIT_P0HI18Q_DESC_MODE_8814B(v))
+
+#define BIT_SHIFT_P0HI18Q_DESC_NUM_8814B 0
+#define BIT_MASK_P0HI18Q_DESC_NUM_8814B 0xfff
+#define BIT_P0HI18Q_DESC_NUM_8814B(x)                                          \
+	(((x) & BIT_MASK_P0HI18Q_DESC_NUM_8814B)                               \
+	 << BIT_SHIFT_P0HI18Q_DESC_NUM_8814B)
+#define BITS_P0HI18Q_DESC_NUM_8814B                                            \
+	(BIT_MASK_P0HI18Q_DESC_NUM_8814B << BIT_SHIFT_P0HI18Q_DESC_NUM_8814B)
+#define BIT_CLEAR_P0HI18Q_DESC_NUM_8814B(x)                                    \
+	((x) & (~BITS_P0HI18Q_DESC_NUM_8814B))
+#define BIT_GET_P0HI18Q_DESC_NUM_8814B(x)                                      \
+	(((x) >> BIT_SHIFT_P0HI18Q_DESC_NUM_8814B) &                           \
+	 BIT_MASK_P0HI18Q_DESC_NUM_8814B)
+#define BIT_SET_P0HI18Q_DESC_NUM_8814B(x, v)                                   \
+	(BIT_CLEAR_P0HI18Q_DESC_NUM_8814B(x) | BIT_P0HI18Q_DESC_NUM_8814B(v))
+
+/* 2 REG_PCIE_HISR0_8814B */
+#define BIT_PSTIMER_2_8814B BIT(31)
+#define BIT_PSTIMER_1_8814B BIT(30)
+#define BIT_PSTIMER_0_8814B BIT(29)
+#define BIT_GTINT4_8814B BIT(28)
+#define BIT_GTINT3_8814B BIT(27)
+#define BIT_TXBCN0ERR_8814B BIT(26)
+#define BIT_TXBCN0OK_8814B BIT(25)
+#define BIT_TSF_BIT32_TOGGLE_8814B BIT(24)
+#define BIT_TXDMA_START_INT_8814B BIT(23)
+#define BIT_TXDMA_STOP_INT_8814B BIT(22)
+#define BIT_HISR7_IND_8814B BIT(21)
+#define BIT_BCNDMAINT0_8814B BIT(20)
+#define BIT_HISR6_IND_8814B BIT(19)
+#define BIT_HISR5_IND_8814B BIT(18)
+#define BIT_HISR4_IND_8814B BIT(17)
+#define BIT_BCNDERR0_8814B BIT(16)
+#define BIT_HSISR_IND_ON_INT_8814B BIT(15)
+#define BIT_HISR3_IND_8814B BIT(14)
+#define BIT_HISR2_IND_8814B BIT(13)
+#define BIT_HISR1_IND_8814B BIT(11)
+#define BIT_C2HCMD_8814B BIT(10)
+#define BIT_CPWM2_8814B BIT(9)
+#define BIT_CPWM_8814B BIT(8)
+#define BIT_TXDMAOK_CHANNEL15_8814B BIT(7)
+#define BIT_TXDMAOK_CHANNEL14_8814B BIT(6)
+#define BIT_TXDMAOK_CHANNEL3_8814B BIT(5)
+#define BIT_TXDMAOK_CHANNEL2_8814B BIT(4)
+#define BIT_TXDMAOK_CHANNEL1_8814B BIT(3)
+#define BIT_TXDMAOK_CHANNEL0_8814B BIT(2)
+#define BIT_RDU_8814B BIT(1)
+#define BIT_RXOK_8814B BIT(0)
+
+/* 2 REG_PCIE_HISR1_8814B */
+#define BIT_PRE_TX_ERR_INT_8814B BIT(31)
+#define BIT_TXFIFO_TH_INT_8814B BIT(30)
+#define BIT_BTON_STS_UPDATE_INT_8814B BIT(29)
+#define BIT_BCNDMAINT7_8814B BIT(27)
+#define BIT_BCNDMAINT6_8814B BIT(26)
+#define BIT_BCNDMAINT5_8814B BIT(25)
+#define BIT_BCNDMAINT4_8814B BIT(24)
+#define BIT_BCNDMAINT3_8814B BIT(23)
+#define BIT_BCNDMAINT2_8814B BIT(22)
+#define BIT_BCNDMAINT1_8814B BIT(21)
+#define BIT_BCNDERR7_8814B BIT(20)
+#define BIT_BCNDERR6_8814B BIT(19)
+#define BIT_BCNDERR5_8814B BIT(18)
+#define BIT_BCNDERR4_8814B BIT(17)
+#define BIT_BCNDERR3_8814B BIT(16)
+#define BIT_BCNDERR2_8814B BIT(15)
+#define BIT_BCNDERR1_8814B BIT(14)
+#define BIT_ATIMEND_8814B BIT(12)
+#define BIT_TXERR_INT_8814B BIT(11)
+#define BIT_RXERR_INT_8814B BIT(10)
+#define BIT_TXFOVW_8814B BIT(9)
+#define BIT_FOVW_8814B BIT(8)
+#define BIT_CPU_MGQ_EARLY_INT_8814B BIT(6)
+#define BIT_CPU_MGQ_TXDONE_8814B BIT(5)
+#define BIT_PSTIMER_5_8814B BIT(4)
+#define BIT_PSTIMER_4_8814B BIT(3)
+#define BIT_PSTIMER_3_8814B BIT(2)
+#define BIT_CPUMGQ_TX_TIMER_8814B BIT(1)
+#define BIT_BB_STOPRX_INT_8814B BIT(0)
+
+/* 2 REG_P0HI8Q_HI9Q_TXBD_NUM_8814B */
+#define BIT_P0HI9Q_FLAG_8814B BIT(30)
+
+#define BIT_SHIFT_P0HI9Q_DESC_MODE_8814B 28
+#define BIT_MASK_P0HI9Q_DESC_MODE_8814B 0x3
+#define BIT_P0HI9Q_DESC_MODE_8814B(x)                                          \
+	(((x) & BIT_MASK_P0HI9Q_DESC_MODE_8814B)                               \
+	 << BIT_SHIFT_P0HI9Q_DESC_MODE_8814B)
+#define BITS_P0HI9Q_DESC_MODE_8814B                                            \
+	(BIT_MASK_P0HI9Q_DESC_MODE_8814B << BIT_SHIFT_P0HI9Q_DESC_MODE_8814B)
+#define BIT_CLEAR_P0HI9Q_DESC_MODE_8814B(x)                                    \
+	((x) & (~BITS_P0HI9Q_DESC_MODE_8814B))
+#define BIT_GET_P0HI9Q_DESC_MODE_8814B(x)                                      \
+	(((x) >> BIT_SHIFT_P0HI9Q_DESC_MODE_8814B) &                           \
+	 BIT_MASK_P0HI9Q_DESC_MODE_8814B)
+#define BIT_SET_P0HI9Q_DESC_MODE_8814B(x, v)                                   \
+	(BIT_CLEAR_P0HI9Q_DESC_MODE_8814B(x) | BIT_P0HI9Q_DESC_MODE_8814B(v))
+
+#define BIT_SHIFT_P0HI9Q_DESC_NUM_8814B 16
+#define BIT_MASK_P0HI9Q_DESC_NUM_8814B 0xfff
+#define BIT_P0HI9Q_DESC_NUM_8814B(x)                                           \
+	(((x) & BIT_MASK_P0HI9Q_DESC_NUM_8814B)                                \
+	 << BIT_SHIFT_P0HI9Q_DESC_NUM_8814B)
+#define BITS_P0HI9Q_DESC_NUM_8814B                                             \
+	(BIT_MASK_P0HI9Q_DESC_NUM_8814B << BIT_SHIFT_P0HI9Q_DESC_NUM_8814B)
+#define BIT_CLEAR_P0HI9Q_DESC_NUM_8814B(x) ((x) & (~BITS_P0HI9Q_DESC_NUM_8814B))
+#define BIT_GET_P0HI9Q_DESC_NUM_8814B(x)                                       \
+	(((x) >> BIT_SHIFT_P0HI9Q_DESC_NUM_8814B) &                            \
+	 BIT_MASK_P0HI9Q_DESC_NUM_8814B)
+#define BIT_SET_P0HI9Q_DESC_NUM_8814B(x, v)                                    \
+	(BIT_CLEAR_P0HI9Q_DESC_NUM_8814B(x) | BIT_P0HI9Q_DESC_NUM_8814B(v))
+
+#define BIT_P0HI8Q_FLAG_8814B BIT(14)
+
+#define BIT_SHIFT_P0HI8Q_DESC_MODE_8814B 12
+#define BIT_MASK_P0HI8Q_DESC_MODE_8814B 0x3
+#define BIT_P0HI8Q_DESC_MODE_8814B(x)                                          \
+	(((x) & BIT_MASK_P0HI8Q_DESC_MODE_8814B)                               \
+	 << BIT_SHIFT_P0HI8Q_DESC_MODE_8814B)
+#define BITS_P0HI8Q_DESC_MODE_8814B                                            \
+	(BIT_MASK_P0HI8Q_DESC_MODE_8814B << BIT_SHIFT_P0HI8Q_DESC_MODE_8814B)
+#define BIT_CLEAR_P0HI8Q_DESC_MODE_8814B(x)                                    \
+	((x) & (~BITS_P0HI8Q_DESC_MODE_8814B))
+#define BIT_GET_P0HI8Q_DESC_MODE_8814B(x)                                      \
+	(((x) >> BIT_SHIFT_P0HI8Q_DESC_MODE_8814B) &                           \
+	 BIT_MASK_P0HI8Q_DESC_MODE_8814B)
+#define BIT_SET_P0HI8Q_DESC_MODE_8814B(x, v)                                   \
+	(BIT_CLEAR_P0HI8Q_DESC_MODE_8814B(x) | BIT_P0HI8Q_DESC_MODE_8814B(v))
+
+#define BIT_SHIFT_P0HI8Q_DESC_NUM_8814B 0
+#define BIT_MASK_P0HI8Q_DESC_NUM_8814B 0xfff
+#define BIT_P0HI8Q_DESC_NUM_8814B(x)                                           \
+	(((x) & BIT_MASK_P0HI8Q_DESC_NUM_8814B)                                \
+	 << BIT_SHIFT_P0HI8Q_DESC_NUM_8814B)
+#define BITS_P0HI8Q_DESC_NUM_8814B                                             \
+	(BIT_MASK_P0HI8Q_DESC_NUM_8814B << BIT_SHIFT_P0HI8Q_DESC_NUM_8814B)
+#define BIT_CLEAR_P0HI8Q_DESC_NUM_8814B(x) ((x) & (~BITS_P0HI8Q_DESC_NUM_8814B))
+#define BIT_GET_P0HI8Q_DESC_NUM_8814B(x)                                       \
+	(((x) >> BIT_SHIFT_P0HI8Q_DESC_NUM_8814B) &                            \
+	 BIT_MASK_P0HI8Q_DESC_NUM_8814B)
+#define BIT_SET_P0HI8Q_DESC_NUM_8814B(x, v)                                    \
+	(BIT_CLEAR_P0HI8Q_DESC_NUM_8814B(x) | BIT_P0HI8Q_DESC_NUM_8814B(v))
+
+/* 2 REG_P0HI10Q_HI11Q_TXBD_NUM_8814B */
+#define BIT_P0HI11Q_FLAG_8814B BIT(30)
+
+#define BIT_SHIFT_P0HI11Q_DESC_MODE_8814B 28
+#define BIT_MASK_P0HI11Q_DESC_MODE_8814B 0x3
+#define BIT_P0HI11Q_DESC_MODE_8814B(x)                                         \
+	(((x) & BIT_MASK_P0HI11Q_DESC_MODE_8814B)                              \
+	 << BIT_SHIFT_P0HI11Q_DESC_MODE_8814B)
+#define BITS_P0HI11Q_DESC_MODE_8814B                                           \
+	(BIT_MASK_P0HI11Q_DESC_MODE_8814B << BIT_SHIFT_P0HI11Q_DESC_MODE_8814B)
+#define BIT_CLEAR_P0HI11Q_DESC_MODE_8814B(x)                                   \
+	((x) & (~BITS_P0HI11Q_DESC_MODE_8814B))
+#define BIT_GET_P0HI11Q_DESC_MODE_8814B(x)                                     \
+	(((x) >> BIT_SHIFT_P0HI11Q_DESC_MODE_8814B) &                          \
+	 BIT_MASK_P0HI11Q_DESC_MODE_8814B)
+#define BIT_SET_P0HI11Q_DESC_MODE_8814B(x, v)                                  \
+	(BIT_CLEAR_P0HI11Q_DESC_MODE_8814B(x) | BIT_P0HI11Q_DESC_MODE_8814B(v))
+
+#define BIT_SHIFT_P0HI11Q_DESC_NUM_8814B 16
+#define BIT_MASK_P0HI11Q_DESC_NUM_8814B 0xfff
+#define BIT_P0HI11Q_DESC_NUM_8814B(x)                                          \
+	(((x) & BIT_MASK_P0HI11Q_DESC_NUM_8814B)                               \
+	 << BIT_SHIFT_P0HI11Q_DESC_NUM_8814B)
+#define BITS_P0HI11Q_DESC_NUM_8814B                                            \
+	(BIT_MASK_P0HI11Q_DESC_NUM_8814B << BIT_SHIFT_P0HI11Q_DESC_NUM_8814B)
+#define BIT_CLEAR_P0HI11Q_DESC_NUM_8814B(x)                                    \
+	((x) & (~BITS_P0HI11Q_DESC_NUM_8814B))
+#define BIT_GET_P0HI11Q_DESC_NUM_8814B(x)                                      \
+	(((x) >> BIT_SHIFT_P0HI11Q_DESC_NUM_8814B) &                           \
+	 BIT_MASK_P0HI11Q_DESC_NUM_8814B)
+#define BIT_SET_P0HI11Q_DESC_NUM_8814B(x, v)                                   \
+	(BIT_CLEAR_P0HI11Q_DESC_NUM_8814B(x) | BIT_P0HI11Q_DESC_NUM_8814B(v))
+
+#define BIT_P0HI10Q_FLAG_8814B BIT(14)
+
+#define BIT_SHIFT_P0HI10Q_DESC_MODE_8814B 12
+#define BIT_MASK_P0HI10Q_DESC_MODE_8814B 0x3
+#define BIT_P0HI10Q_DESC_MODE_8814B(x)                                         \
+	(((x) & BIT_MASK_P0HI10Q_DESC_MODE_8814B)                              \
+	 << BIT_SHIFT_P0HI10Q_DESC_MODE_8814B)
+#define BITS_P0HI10Q_DESC_MODE_8814B                                           \
+	(BIT_MASK_P0HI10Q_DESC_MODE_8814B << BIT_SHIFT_P0HI10Q_DESC_MODE_8814B)
+#define BIT_CLEAR_P0HI10Q_DESC_MODE_8814B(x)                                   \
+	((x) & (~BITS_P0HI10Q_DESC_MODE_8814B))
+#define BIT_GET_P0HI10Q_DESC_MODE_8814B(x)                                     \
+	(((x) >> BIT_SHIFT_P0HI10Q_DESC_MODE_8814B) &                          \
+	 BIT_MASK_P0HI10Q_DESC_MODE_8814B)
+#define BIT_SET_P0HI10Q_DESC_MODE_8814B(x, v)                                  \
+	(BIT_CLEAR_P0HI10Q_DESC_MODE_8814B(x) | BIT_P0HI10Q_DESC_MODE_8814B(v))
+
+#define BIT_SHIFT_P0HI10Q_DESC_NUM_8814B 0
+#define BIT_MASK_P0HI10Q_DESC_NUM_8814B 0xfff
+#define BIT_P0HI10Q_DESC_NUM_8814B(x)                                          \
+	(((x) & BIT_MASK_P0HI10Q_DESC_NUM_8814B)                               \
+	 << BIT_SHIFT_P0HI10Q_DESC_NUM_8814B)
+#define BITS_P0HI10Q_DESC_NUM_8814B                                            \
+	(BIT_MASK_P0HI10Q_DESC_NUM_8814B << BIT_SHIFT_P0HI10Q_DESC_NUM_8814B)
+#define BIT_CLEAR_P0HI10Q_DESC_NUM_8814B(x)                                    \
+	((x) & (~BITS_P0HI10Q_DESC_NUM_8814B))
+#define BIT_GET_P0HI10Q_DESC_NUM_8814B(x)                                      \
+	(((x) >> BIT_SHIFT_P0HI10Q_DESC_NUM_8814B) &                           \
+	 BIT_MASK_P0HI10Q_DESC_NUM_8814B)
+#define BIT_SET_P0HI10Q_DESC_NUM_8814B(x, v)                                   \
+	(BIT_CLEAR_P0HI10Q_DESC_NUM_8814B(x) | BIT_P0HI10Q_DESC_NUM_8814B(v))
+
+/* 2 REG_P0HI12Q_HI13Q_TXBD_NUM_8814B */
+#define BIT_P0HI13Q_FLAG_8814B BIT(30)
+
+#define BIT_SHIFT_P0HI13Q_DESC_MODE_8814B 28
+#define BIT_MASK_P0HI13Q_DESC_MODE_8814B 0x3
+#define BIT_P0HI13Q_DESC_MODE_8814B(x)                                         \
+	(((x) & BIT_MASK_P0HI13Q_DESC_MODE_8814B)                              \
+	 << BIT_SHIFT_P0HI13Q_DESC_MODE_8814B)
+#define BITS_P0HI13Q_DESC_MODE_8814B                                           \
+	(BIT_MASK_P0HI13Q_DESC_MODE_8814B << BIT_SHIFT_P0HI13Q_DESC_MODE_8814B)
+#define BIT_CLEAR_P0HI13Q_DESC_MODE_8814B(x)                                   \
+	((x) & (~BITS_P0HI13Q_DESC_MODE_8814B))
+#define BIT_GET_P0HI13Q_DESC_MODE_8814B(x)                                     \
+	(((x) >> BIT_SHIFT_P0HI13Q_DESC_MODE_8814B) &                          \
+	 BIT_MASK_P0HI13Q_DESC_MODE_8814B)
+#define BIT_SET_P0HI13Q_DESC_MODE_8814B(x, v)                                  \
+	(BIT_CLEAR_P0HI13Q_DESC_MODE_8814B(x) | BIT_P0HI13Q_DESC_MODE_8814B(v))
+
+#define BIT_SHIFT_P0HI13Q_DESC_NUM_8814B 16
+#define BIT_MASK_P0HI13Q_DESC_NUM_8814B 0xfff
+#define BIT_P0HI13Q_DESC_NUM_8814B(x)                                          \
+	(((x) & BIT_MASK_P0HI13Q_DESC_NUM_8814B)                               \
+	 << BIT_SHIFT_P0HI13Q_DESC_NUM_8814B)
+#define BITS_P0HI13Q_DESC_NUM_8814B                                            \
+	(BIT_MASK_P0HI13Q_DESC_NUM_8814B << BIT_SHIFT_P0HI13Q_DESC_NUM_8814B)
+#define BIT_CLEAR_P0HI13Q_DESC_NUM_8814B(x)                                    \
+	((x) & (~BITS_P0HI13Q_DESC_NUM_8814B))
+#define BIT_GET_P0HI13Q_DESC_NUM_8814B(x)                                      \
+	(((x) >> BIT_SHIFT_P0HI13Q_DESC_NUM_8814B) &                           \
+	 BIT_MASK_P0HI13Q_DESC_NUM_8814B)
+#define BIT_SET_P0HI13Q_DESC_NUM_8814B(x, v)                                   \
+	(BIT_CLEAR_P0HI13Q_DESC_NUM_8814B(x) | BIT_P0HI13Q_DESC_NUM_8814B(v))
+
+#define BIT_P0HI12Q_FLAG_8814B BIT(14)
+
+#define BIT_SHIFT_P0HI12Q_DESC_MODE_8814B 12
+#define BIT_MASK_P0HI12Q_DESC_MODE_8814B 0x3
+#define BIT_P0HI12Q_DESC_MODE_8814B(x)                                         \
+	(((x) & BIT_MASK_P0HI12Q_DESC_MODE_8814B)                              \
+	 << BIT_SHIFT_P0HI12Q_DESC_MODE_8814B)
+#define BITS_P0HI12Q_DESC_MODE_8814B                                           \
+	(BIT_MASK_P0HI12Q_DESC_MODE_8814B << BIT_SHIFT_P0HI12Q_DESC_MODE_8814B)
+#define BIT_CLEAR_P0HI12Q_DESC_MODE_8814B(x)                                   \
+	((x) & (~BITS_P0HI12Q_DESC_MODE_8814B))
+#define BIT_GET_P0HI12Q_DESC_MODE_8814B(x)                                     \
+	(((x) >> BIT_SHIFT_P0HI12Q_DESC_MODE_8814B) &                          \
+	 BIT_MASK_P0HI12Q_DESC_MODE_8814B)
+#define BIT_SET_P0HI12Q_DESC_MODE_8814B(x, v)                                  \
+	(BIT_CLEAR_P0HI12Q_DESC_MODE_8814B(x) | BIT_P0HI12Q_DESC_MODE_8814B(v))
+
+#define BIT_SHIFT_P0HI12Q_DESC_NUM_8814B 0
+#define BIT_MASK_P0HI12Q_DESC_NUM_8814B 0xfff
+#define BIT_P0HI12Q_DESC_NUM_8814B(x)                                          \
+	(((x) & BIT_MASK_P0HI12Q_DESC_NUM_8814B)                               \
+	 << BIT_SHIFT_P0HI12Q_DESC_NUM_8814B)
+#define BITS_P0HI12Q_DESC_NUM_8814B                                            \
+	(BIT_MASK_P0HI12Q_DESC_NUM_8814B << BIT_SHIFT_P0HI12Q_DESC_NUM_8814B)
+#define BIT_CLEAR_P0HI12Q_DESC_NUM_8814B(x)                                    \
+	((x) & (~BITS_P0HI12Q_DESC_NUM_8814B))
+#define BIT_GET_P0HI12Q_DESC_NUM_8814B(x)                                      \
+	(((x) >> BIT_SHIFT_P0HI12Q_DESC_NUM_8814B) &                           \
+	 BIT_MASK_P0HI12Q_DESC_NUM_8814B)
+#define BIT_SET_P0HI12Q_DESC_NUM_8814B(x, v)                                   \
+	(BIT_CLEAR_P0HI12Q_DESC_NUM_8814B(x) | BIT_P0HI12Q_DESC_NUM_8814B(v))
+
+/* 2 REG_P0HI14Q_HI15Q_TXBD_NUM_8814B */
+#define BIT_P0HI15Q_FLAG_8814B BIT(30)
+
+#define BIT_SHIFT_P0HI15Q_DESC_MODE_8814B 28
+#define BIT_MASK_P0HI15Q_DESC_MODE_8814B 0x3
+#define BIT_P0HI15Q_DESC_MODE_8814B(x)                                         \
+	(((x) & BIT_MASK_P0HI15Q_DESC_MODE_8814B)                              \
+	 << BIT_SHIFT_P0HI15Q_DESC_MODE_8814B)
+#define BITS_P0HI15Q_DESC_MODE_8814B                                           \
+	(BIT_MASK_P0HI15Q_DESC_MODE_8814B << BIT_SHIFT_P0HI15Q_DESC_MODE_8814B)
+#define BIT_CLEAR_P0HI15Q_DESC_MODE_8814B(x)                                   \
+	((x) & (~BITS_P0HI15Q_DESC_MODE_8814B))
+#define BIT_GET_P0HI15Q_DESC_MODE_8814B(x)                                     \
+	(((x) >> BIT_SHIFT_P0HI15Q_DESC_MODE_8814B) &                          \
+	 BIT_MASK_P0HI15Q_DESC_MODE_8814B)
+#define BIT_SET_P0HI15Q_DESC_MODE_8814B(x, v)                                  \
+	(BIT_CLEAR_P0HI15Q_DESC_MODE_8814B(x) | BIT_P0HI15Q_DESC_MODE_8814B(v))
+
+#define BIT_SHIFT_P0HI15Q_DESC_NUM_8814B 16
+#define BIT_MASK_P0HI15Q_DESC_NUM_8814B 0xfff
+#define BIT_P0HI15Q_DESC_NUM_8814B(x)                                          \
+	(((x) & BIT_MASK_P0HI15Q_DESC_NUM_8814B)                               \
+	 << BIT_SHIFT_P0HI15Q_DESC_NUM_8814B)
+#define BITS_P0HI15Q_DESC_NUM_8814B                                            \
+	(BIT_MASK_P0HI15Q_DESC_NUM_8814B << BIT_SHIFT_P0HI15Q_DESC_NUM_8814B)
+#define BIT_CLEAR_P0HI15Q_DESC_NUM_8814B(x)                                    \
+	((x) & (~BITS_P0HI15Q_DESC_NUM_8814B))
+#define BIT_GET_P0HI15Q_DESC_NUM_8814B(x)                                      \
+	(((x) >> BIT_SHIFT_P0HI15Q_DESC_NUM_8814B) &                           \
+	 BIT_MASK_P0HI15Q_DESC_NUM_8814B)
+#define BIT_SET_P0HI15Q_DESC_NUM_8814B(x, v)                                   \
+	(BIT_CLEAR_P0HI15Q_DESC_NUM_8814B(x) | BIT_P0HI15Q_DESC_NUM_8814B(v))
+
+#define BIT_P0HI14Q_FLAG_8814B BIT(14)
+
+#define BIT_SHIFT_P0HI14Q_DESC_MODE_8814B 12
+#define BIT_MASK_P0HI14Q_DESC_MODE_8814B 0x3
+#define BIT_P0HI14Q_DESC_MODE_8814B(x)                                         \
+	(((x) & BIT_MASK_P0HI14Q_DESC_MODE_8814B)                              \
+	 << BIT_SHIFT_P0HI14Q_DESC_MODE_8814B)
+#define BITS_P0HI14Q_DESC_MODE_8814B                                           \
+	(BIT_MASK_P0HI14Q_DESC_MODE_8814B << BIT_SHIFT_P0HI14Q_DESC_MODE_8814B)
+#define BIT_CLEAR_P0HI14Q_DESC_MODE_8814B(x)                                   \
+	((x) & (~BITS_P0HI14Q_DESC_MODE_8814B))
+#define BIT_GET_P0HI14Q_DESC_MODE_8814B(x)                                     \
+	(((x) >> BIT_SHIFT_P0HI14Q_DESC_MODE_8814B) &                          \
+	 BIT_MASK_P0HI14Q_DESC_MODE_8814B)
+#define BIT_SET_P0HI14Q_DESC_MODE_8814B(x, v)                                  \
+	(BIT_CLEAR_P0HI14Q_DESC_MODE_8814B(x) | BIT_P0HI14Q_DESC_MODE_8814B(v))
+
+#define BIT_SHIFT_P0HI14Q_DESC_NUM_8814B 0
+#define BIT_MASK_P0HI14Q_DESC_NUM_8814B 0xfff
+#define BIT_P0HI14Q_DESC_NUM_8814B(x)                                          \
+	(((x) & BIT_MASK_P0HI14Q_DESC_NUM_8814B)                               \
+	 << BIT_SHIFT_P0HI14Q_DESC_NUM_8814B)
+#define BITS_P0HI14Q_DESC_NUM_8814B                                            \
+	(BIT_MASK_P0HI14Q_DESC_NUM_8814B << BIT_SHIFT_P0HI14Q_DESC_NUM_8814B)
+#define BIT_CLEAR_P0HI14Q_DESC_NUM_8814B(x)                                    \
+	((x) & (~BITS_P0HI14Q_DESC_NUM_8814B))
+#define BIT_GET_P0HI14Q_DESC_NUM_8814B(x)                                      \
+	(((x) >> BIT_SHIFT_P0HI14Q_DESC_NUM_8814B) &                           \
+	 BIT_MASK_P0HI14Q_DESC_NUM_8814B)
+#define BIT_SET_P0HI14Q_DESC_NUM_8814B(x, v)                                   \
+	(BIT_CLEAR_P0HI14Q_DESC_NUM_8814B(x) | BIT_P0HI14Q_DESC_NUM_8814B(v))
+
+/* 2 REG_ACH6_ACH7_TXBD_NUM_8814B */
+#define BIT_PCIE_ACH7_FLAG_8814B BIT(30)
+
+#define BIT_SHIFT_ACH7_DESC_MODE_8814B 28
+#define BIT_MASK_ACH7_DESC_MODE_8814B 0x3
+#define BIT_ACH7_DESC_MODE_8814B(x)                                            \
+	(((x) & BIT_MASK_ACH7_DESC_MODE_8814B)                                 \
+	 << BIT_SHIFT_ACH7_DESC_MODE_8814B)
+#define BITS_ACH7_DESC_MODE_8814B                                              \
+	(BIT_MASK_ACH7_DESC_MODE_8814B << BIT_SHIFT_ACH7_DESC_MODE_8814B)
+#define BIT_CLEAR_ACH7_DESC_MODE_8814B(x) ((x) & (~BITS_ACH7_DESC_MODE_8814B))
+#define BIT_GET_ACH7_DESC_MODE_8814B(x)                                        \
+	(((x) >> BIT_SHIFT_ACH7_DESC_MODE_8814B) &                             \
+	 BIT_MASK_ACH7_DESC_MODE_8814B)
+#define BIT_SET_ACH7_DESC_MODE_8814B(x, v)                                     \
+	(BIT_CLEAR_ACH7_DESC_MODE_8814B(x) | BIT_ACH7_DESC_MODE_8814B(v))
+
+#define BIT_SHIFT_ACH7_DESC_NUM_8814B 16
+#define BIT_MASK_ACH7_DESC_NUM_8814B 0xfff
+#define BIT_ACH7_DESC_NUM_8814B(x)                                             \
+	(((x) & BIT_MASK_ACH7_DESC_NUM_8814B) << BIT_SHIFT_ACH7_DESC_NUM_8814B)
+#define BITS_ACH7_DESC_NUM_8814B                                               \
+	(BIT_MASK_ACH7_DESC_NUM_8814B << BIT_SHIFT_ACH7_DESC_NUM_8814B)
+#define BIT_CLEAR_ACH7_DESC_NUM_8814B(x) ((x) & (~BITS_ACH7_DESC_NUM_8814B))
+#define BIT_GET_ACH7_DESC_NUM_8814B(x)                                         \
+	(((x) >> BIT_SHIFT_ACH7_DESC_NUM_8814B) & BIT_MASK_ACH7_DESC_NUM_8814B)
+#define BIT_SET_ACH7_DESC_NUM_8814B(x, v)                                      \
+	(BIT_CLEAR_ACH7_DESC_NUM_8814B(x) | BIT_ACH7_DESC_NUM_8814B(v))
+
+#define BIT_PCIE_ACH6_FLAG_8814B BIT(14)
+
+#define BIT_SHIFT_ACH6_DESC_MODE_8814B 12
+#define BIT_MASK_ACH6_DESC_MODE_8814B 0x3
+#define BIT_ACH6_DESC_MODE_8814B(x)                                            \
+	(((x) & BIT_MASK_ACH6_DESC_MODE_8814B)                                 \
+	 << BIT_SHIFT_ACH6_DESC_MODE_8814B)
+#define BITS_ACH6_DESC_MODE_8814B                                              \
+	(BIT_MASK_ACH6_DESC_MODE_8814B << BIT_SHIFT_ACH6_DESC_MODE_8814B)
+#define BIT_CLEAR_ACH6_DESC_MODE_8814B(x) ((x) & (~BITS_ACH6_DESC_MODE_8814B))
+#define BIT_GET_ACH6_DESC_MODE_8814B(x)                                        \
+	(((x) >> BIT_SHIFT_ACH6_DESC_MODE_8814B) &                             \
+	 BIT_MASK_ACH6_DESC_MODE_8814B)
+#define BIT_SET_ACH6_DESC_MODE_8814B(x, v)                                     \
+	(BIT_CLEAR_ACH6_DESC_MODE_8814B(x) | BIT_ACH6_DESC_MODE_8814B(v))
+
+#define BIT_SHIFT_ACH6_DESC_NUM_8814B 0
+#define BIT_MASK_ACH6_DESC_NUM_8814B 0xfff
+#define BIT_ACH6_DESC_NUM_8814B(x)                                             \
+	(((x) & BIT_MASK_ACH6_DESC_NUM_8814B) << BIT_SHIFT_ACH6_DESC_NUM_8814B)
+#define BITS_ACH6_DESC_NUM_8814B                                               \
+	(BIT_MASK_ACH6_DESC_NUM_8814B << BIT_SHIFT_ACH6_DESC_NUM_8814B)
+#define BIT_CLEAR_ACH6_DESC_NUM_8814B(x) ((x) & (~BITS_ACH6_DESC_NUM_8814B))
+#define BIT_GET_ACH6_DESC_NUM_8814B(x)                                         \
+	(((x) >> BIT_SHIFT_ACH6_DESC_NUM_8814B) & BIT_MASK_ACH6_DESC_NUM_8814B)
+#define BIT_SET_ACH6_DESC_NUM_8814B(x, v)                                      \
+	(BIT_CLEAR_ACH6_DESC_NUM_8814B(x) | BIT_ACH6_DESC_NUM_8814B(v))
+
+/* 2 REG_ACH4_TXBD_IDX_8814B */
+
+#define BIT_SHIFT_ACH4_HW_IDX_8814B 16
+#define BIT_MASK_ACH4_HW_IDX_8814B 0xfff
+#define BIT_ACH4_HW_IDX_8814B(x)                                               \
+	(((x) & BIT_MASK_ACH4_HW_IDX_8814B) << BIT_SHIFT_ACH4_HW_IDX_8814B)
+#define BITS_ACH4_HW_IDX_8814B                                                 \
+	(BIT_MASK_ACH4_HW_IDX_8814B << BIT_SHIFT_ACH4_HW_IDX_8814B)
+#define BIT_CLEAR_ACH4_HW_IDX_8814B(x) ((x) & (~BITS_ACH4_HW_IDX_8814B))
+#define BIT_GET_ACH4_HW_IDX_8814B(x)                                           \
+	(((x) >> BIT_SHIFT_ACH4_HW_IDX_8814B) & BIT_MASK_ACH4_HW_IDX_8814B)
+#define BIT_SET_ACH4_HW_IDX_8814B(x, v)                                        \
+	(BIT_CLEAR_ACH4_HW_IDX_8814B(x) | BIT_ACH4_HW_IDX_8814B(v))
+
+#define BIT_SHIFT_ACH4_HOST_IDX_8814B 0
+#define BIT_MASK_ACH4_HOST_IDX_8814B 0xfff
+#define BIT_ACH4_HOST_IDX_8814B(x)                                             \
+	(((x) & BIT_MASK_ACH4_HOST_IDX_8814B) << BIT_SHIFT_ACH4_HOST_IDX_8814B)
+#define BITS_ACH4_HOST_IDX_8814B                                               \
+	(BIT_MASK_ACH4_HOST_IDX_8814B << BIT_SHIFT_ACH4_HOST_IDX_8814B)
+#define BIT_CLEAR_ACH4_HOST_IDX_8814B(x) ((x) & (~BITS_ACH4_HOST_IDX_8814B))
+#define BIT_GET_ACH4_HOST_IDX_8814B(x)                                         \
+	(((x) >> BIT_SHIFT_ACH4_HOST_IDX_8814B) & BIT_MASK_ACH4_HOST_IDX_8814B)
+#define BIT_SET_ACH4_HOST_IDX_8814B(x, v)                                      \
+	(BIT_CLEAR_ACH4_HOST_IDX_8814B(x) | BIT_ACH4_HOST_IDX_8814B(v))
+
+/* 2 REG_ACH5_TXBD_IDX_8814B */
+
+#define BIT_SHIFT_ACH5_HW_IDX_8814B 16
+#define BIT_MASK_ACH5_HW_IDX_8814B 0xfff
+#define BIT_ACH5_HW_IDX_8814B(x)                                               \
+	(((x) & BIT_MASK_ACH5_HW_IDX_8814B) << BIT_SHIFT_ACH5_HW_IDX_8814B)
+#define BITS_ACH5_HW_IDX_8814B                                                 \
+	(BIT_MASK_ACH5_HW_IDX_8814B << BIT_SHIFT_ACH5_HW_IDX_8814B)
+#define BIT_CLEAR_ACH5_HW_IDX_8814B(x) ((x) & (~BITS_ACH5_HW_IDX_8814B))
+#define BIT_GET_ACH5_HW_IDX_8814B(x)                                           \
+	(((x) >> BIT_SHIFT_ACH5_HW_IDX_8814B) & BIT_MASK_ACH5_HW_IDX_8814B)
+#define BIT_SET_ACH5_HW_IDX_8814B(x, v)                                        \
+	(BIT_CLEAR_ACH5_HW_IDX_8814B(x) | BIT_ACH5_HW_IDX_8814B(v))
+
+#define BIT_SHIFT_ACH5_HOST_IDX_8814B 0
+#define BIT_MASK_ACH5_HOST_IDX_8814B 0xfff
+#define BIT_ACH5_HOST_IDX_8814B(x)                                             \
+	(((x) & BIT_MASK_ACH5_HOST_IDX_8814B) << BIT_SHIFT_ACH5_HOST_IDX_8814B)
+#define BITS_ACH5_HOST_IDX_8814B                                               \
+	(BIT_MASK_ACH5_HOST_IDX_8814B << BIT_SHIFT_ACH5_HOST_IDX_8814B)
+#define BIT_CLEAR_ACH5_HOST_IDX_8814B(x) ((x) & (~BITS_ACH5_HOST_IDX_8814B))
+#define BIT_GET_ACH5_HOST_IDX_8814B(x)                                         \
+	(((x) >> BIT_SHIFT_ACH5_HOST_IDX_8814B) & BIT_MASK_ACH5_HOST_IDX_8814B)
+#define BIT_SET_ACH5_HOST_IDX_8814B(x, v)                                      \
+	(BIT_CLEAR_ACH5_HOST_IDX_8814B(x) | BIT_ACH5_HOST_IDX_8814B(v))
+
+/* 2 REG_ACH6_TXBD_IDX_8814B */
+
+#define BIT_SHIFT_ACH6_HW_IDX_8814B 16
+#define BIT_MASK_ACH6_HW_IDX_8814B 0xfff
+#define BIT_ACH6_HW_IDX_8814B(x)                                               \
+	(((x) & BIT_MASK_ACH6_HW_IDX_8814B) << BIT_SHIFT_ACH6_HW_IDX_8814B)
+#define BITS_ACH6_HW_IDX_8814B                                                 \
+	(BIT_MASK_ACH6_HW_IDX_8814B << BIT_SHIFT_ACH6_HW_IDX_8814B)
+#define BIT_CLEAR_ACH6_HW_IDX_8814B(x) ((x) & (~BITS_ACH6_HW_IDX_8814B))
+#define BIT_GET_ACH6_HW_IDX_8814B(x)                                           \
+	(((x) >> BIT_SHIFT_ACH6_HW_IDX_8814B) & BIT_MASK_ACH6_HW_IDX_8814B)
+#define BIT_SET_ACH6_HW_IDX_8814B(x, v)                                        \
+	(BIT_CLEAR_ACH6_HW_IDX_8814B(x) | BIT_ACH6_HW_IDX_8814B(v))
+
+#define BIT_SHIFT_ACH6_HOST_IDX_8814B 0
+#define BIT_MASK_ACH6_HOST_IDX_8814B 0xfff
+#define BIT_ACH6_HOST_IDX_8814B(x)                                             \
+	(((x) & BIT_MASK_ACH6_HOST_IDX_8814B) << BIT_SHIFT_ACH6_HOST_IDX_8814B)
+#define BITS_ACH6_HOST_IDX_8814B                                               \
+	(BIT_MASK_ACH6_HOST_IDX_8814B << BIT_SHIFT_ACH6_HOST_IDX_8814B)
+#define BIT_CLEAR_ACH6_HOST_IDX_8814B(x) ((x) & (~BITS_ACH6_HOST_IDX_8814B))
+#define BIT_GET_ACH6_HOST_IDX_8814B(x)                                         \
+	(((x) >> BIT_SHIFT_ACH6_HOST_IDX_8814B) & BIT_MASK_ACH6_HOST_IDX_8814B)
+#define BIT_SET_ACH6_HOST_IDX_8814B(x, v)                                      \
+	(BIT_CLEAR_ACH6_HOST_IDX_8814B(x) | BIT_ACH6_HOST_IDX_8814B(v))
+
+/* 2 REG_ACH7_TXBD_IDX_8814B */
+
+#define BIT_SHIFT_ACH7_HW_IDX_8814B 16
+#define BIT_MASK_ACH7_HW_IDX_8814B 0xfff
+#define BIT_ACH7_HW_IDX_8814B(x)                                               \
+	(((x) & BIT_MASK_ACH7_HW_IDX_8814B) << BIT_SHIFT_ACH7_HW_IDX_8814B)
+#define BITS_ACH7_HW_IDX_8814B                                                 \
+	(BIT_MASK_ACH7_HW_IDX_8814B << BIT_SHIFT_ACH7_HW_IDX_8814B)
+#define BIT_CLEAR_ACH7_HW_IDX_8814B(x) ((x) & (~BITS_ACH7_HW_IDX_8814B))
+#define BIT_GET_ACH7_HW_IDX_8814B(x)                                           \
+	(((x) >> BIT_SHIFT_ACH7_HW_IDX_8814B) & BIT_MASK_ACH7_HW_IDX_8814B)
+#define BIT_SET_ACH7_HW_IDX_8814B(x, v)                                        \
+	(BIT_CLEAR_ACH7_HW_IDX_8814B(x) | BIT_ACH7_HW_IDX_8814B(v))
+
+#define BIT_SHIFT_ACH7_HOST_IDX_8814B 0
+#define BIT_MASK_ACH7_HOST_IDX_8814B 0xfff
+#define BIT_ACH7_HOST_IDX_8814B(x)                                             \
+	(((x) & BIT_MASK_ACH7_HOST_IDX_8814B) << BIT_SHIFT_ACH7_HOST_IDX_8814B)
+#define BITS_ACH7_HOST_IDX_8814B                                               \
+	(BIT_MASK_ACH7_HOST_IDX_8814B << BIT_SHIFT_ACH7_HOST_IDX_8814B)
+#define BIT_CLEAR_ACH7_HOST_IDX_8814B(x) ((x) & (~BITS_ACH7_HOST_IDX_8814B))
+#define BIT_GET_ACH7_HOST_IDX_8814B(x)                                         \
+	(((x) >> BIT_SHIFT_ACH7_HOST_IDX_8814B) & BIT_MASK_ACH7_HOST_IDX_8814B)
+#define BIT_SET_ACH7_HOST_IDX_8814B(x, v)                                      \
+	(BIT_CLEAR_ACH7_HOST_IDX_8814B(x) | BIT_ACH7_HOST_IDX_8814B(v))
+
+/* 2 REG_ACH8_TXBD_IDX_8814B */
+
+#define BIT_SHIFT_ACH8_HW_IDX_8814B 16
+#define BIT_MASK_ACH8_HW_IDX_8814B 0xfff
+#define BIT_ACH8_HW_IDX_8814B(x)                                               \
+	(((x) & BIT_MASK_ACH8_HW_IDX_8814B) << BIT_SHIFT_ACH8_HW_IDX_8814B)
+#define BITS_ACH8_HW_IDX_8814B                                                 \
+	(BIT_MASK_ACH8_HW_IDX_8814B << BIT_SHIFT_ACH8_HW_IDX_8814B)
+#define BIT_CLEAR_ACH8_HW_IDX_8814B(x) ((x) & (~BITS_ACH8_HW_IDX_8814B))
+#define BIT_GET_ACH8_HW_IDX_8814B(x)                                           \
+	(((x) >> BIT_SHIFT_ACH8_HW_IDX_8814B) & BIT_MASK_ACH8_HW_IDX_8814B)
+#define BIT_SET_ACH8_HW_IDX_8814B(x, v)                                        \
+	(BIT_CLEAR_ACH8_HW_IDX_8814B(x) | BIT_ACH8_HW_IDX_8814B(v))
+
+#define BIT_SHIFT_ACH8_HOST_IDX_8814B 0
+#define BIT_MASK_ACH8_HOST_IDX_8814B 0xfff
+#define BIT_ACH8_HOST_IDX_8814B(x)                                             \
+	(((x) & BIT_MASK_ACH8_HOST_IDX_8814B) << BIT_SHIFT_ACH8_HOST_IDX_8814B)
+#define BITS_ACH8_HOST_IDX_8814B                                               \
+	(BIT_MASK_ACH8_HOST_IDX_8814B << BIT_SHIFT_ACH8_HOST_IDX_8814B)
+#define BIT_CLEAR_ACH8_HOST_IDX_8814B(x) ((x) & (~BITS_ACH8_HOST_IDX_8814B))
+#define BIT_GET_ACH8_HOST_IDX_8814B(x)                                         \
+	(((x) >> BIT_SHIFT_ACH8_HOST_IDX_8814B) & BIT_MASK_ACH8_HOST_IDX_8814B)
+#define BIT_SET_ACH8_HOST_IDX_8814B(x, v)                                      \
+	(BIT_CLEAR_ACH8_HOST_IDX_8814B(x) | BIT_ACH8_HOST_IDX_8814B(v))
+
+/* 2 REG_ACH9_TXBD_IDX_8814B */
+
+#define BIT_SHIFT_ACH9_HW_IDX_8814B 16
+#define BIT_MASK_ACH9_HW_IDX_8814B 0xfff
+#define BIT_ACH9_HW_IDX_8814B(x)                                               \
+	(((x) & BIT_MASK_ACH9_HW_IDX_8814B) << BIT_SHIFT_ACH9_HW_IDX_8814B)
+#define BITS_ACH9_HW_IDX_8814B                                                 \
+	(BIT_MASK_ACH9_HW_IDX_8814B << BIT_SHIFT_ACH9_HW_IDX_8814B)
+#define BIT_CLEAR_ACH9_HW_IDX_8814B(x) ((x) & (~BITS_ACH9_HW_IDX_8814B))
+#define BIT_GET_ACH9_HW_IDX_8814B(x)                                           \
+	(((x) >> BIT_SHIFT_ACH9_HW_IDX_8814B) & BIT_MASK_ACH9_HW_IDX_8814B)
+#define BIT_SET_ACH9_HW_IDX_8814B(x, v)                                        \
+	(BIT_CLEAR_ACH9_HW_IDX_8814B(x) | BIT_ACH9_HW_IDX_8814B(v))
+
+#define BIT_SHIFT_ACH9_HOST_IDX_8814B 0
+#define BIT_MASK_ACH9_HOST_IDX_8814B 0xfff
+#define BIT_ACH9_HOST_IDX_8814B(x)                                             \
+	(((x) & BIT_MASK_ACH9_HOST_IDX_8814B) << BIT_SHIFT_ACH9_HOST_IDX_8814B)
+#define BITS_ACH9_HOST_IDX_8814B                                               \
+	(BIT_MASK_ACH9_HOST_IDX_8814B << BIT_SHIFT_ACH9_HOST_IDX_8814B)
+#define BIT_CLEAR_ACH9_HOST_IDX_8814B(x) ((x) & (~BITS_ACH9_HOST_IDX_8814B))
+#define BIT_GET_ACH9_HOST_IDX_8814B(x)                                         \
+	(((x) >> BIT_SHIFT_ACH9_HOST_IDX_8814B) & BIT_MASK_ACH9_HOST_IDX_8814B)
+#define BIT_SET_ACH9_HOST_IDX_8814B(x, v)                                      \
+	(BIT_CLEAR_ACH9_HOST_IDX_8814B(x) | BIT_ACH9_HOST_IDX_8814B(v))
+
+/* 2 REG_ACH10_TXBD_IDX_8814B */
+
+#define BIT_SHIFT_ACH10_HW_IDX_8814B 16
+#define BIT_MASK_ACH10_HW_IDX_8814B 0xfff
+#define BIT_ACH10_HW_IDX_8814B(x)                                              \
+	(((x) & BIT_MASK_ACH10_HW_IDX_8814B) << BIT_SHIFT_ACH10_HW_IDX_8814B)
+#define BITS_ACH10_HW_IDX_8814B                                                \
+	(BIT_MASK_ACH10_HW_IDX_8814B << BIT_SHIFT_ACH10_HW_IDX_8814B)
+#define BIT_CLEAR_ACH10_HW_IDX_8814B(x) ((x) & (~BITS_ACH10_HW_IDX_8814B))
+#define BIT_GET_ACH10_HW_IDX_8814B(x)                                          \
+	(((x) >> BIT_SHIFT_ACH10_HW_IDX_8814B) & BIT_MASK_ACH10_HW_IDX_8814B)
+#define BIT_SET_ACH10_HW_IDX_8814B(x, v)                                       \
+	(BIT_CLEAR_ACH10_HW_IDX_8814B(x) | BIT_ACH10_HW_IDX_8814B(v))
+
+#define BIT_SHIFT_ACH10_HOST_IDX_8814B 0
+#define BIT_MASK_ACH10_HOST_IDX_8814B 0xfff
+#define BIT_ACH10_HOST_IDX_8814B(x)                                            \
+	(((x) & BIT_MASK_ACH10_HOST_IDX_8814B)                                 \
+	 << BIT_SHIFT_ACH10_HOST_IDX_8814B)
+#define BITS_ACH10_HOST_IDX_8814B                                              \
+	(BIT_MASK_ACH10_HOST_IDX_8814B << BIT_SHIFT_ACH10_HOST_IDX_8814B)
+#define BIT_CLEAR_ACH10_HOST_IDX_8814B(x) ((x) & (~BITS_ACH10_HOST_IDX_8814B))
+#define BIT_GET_ACH10_HOST_IDX_8814B(x)                                        \
+	(((x) >> BIT_SHIFT_ACH10_HOST_IDX_8814B) &                             \
+	 BIT_MASK_ACH10_HOST_IDX_8814B)
+#define BIT_SET_ACH10_HOST_IDX_8814B(x, v)                                     \
+	(BIT_CLEAR_ACH10_HOST_IDX_8814B(x) | BIT_ACH10_HOST_IDX_8814B(v))
+
+/* 2 REG_ACH11_TXBD_IDX_8814B */
+
+#define BIT_SHIFT_ACH11_HW_IDX_8814B 16
+#define BIT_MASK_ACH11_HW_IDX_8814B 0xfff
+#define BIT_ACH11_HW_IDX_8814B(x)                                              \
+	(((x) & BIT_MASK_ACH11_HW_IDX_8814B) << BIT_SHIFT_ACH11_HW_IDX_8814B)
+#define BITS_ACH11_HW_IDX_8814B                                                \
+	(BIT_MASK_ACH11_HW_IDX_8814B << BIT_SHIFT_ACH11_HW_IDX_8814B)
+#define BIT_CLEAR_ACH11_HW_IDX_8814B(x) ((x) & (~BITS_ACH11_HW_IDX_8814B))
+#define BIT_GET_ACH11_HW_IDX_8814B(x)                                          \
+	(((x) >> BIT_SHIFT_ACH11_HW_IDX_8814B) & BIT_MASK_ACH11_HW_IDX_8814B)
+#define BIT_SET_ACH11_HW_IDX_8814B(x, v)                                       \
+	(BIT_CLEAR_ACH11_HW_IDX_8814B(x) | BIT_ACH11_HW_IDX_8814B(v))
+
+#define BIT_SHIFT_ACH11_HOST_IDX_8814B 0
+#define BIT_MASK_ACH11_HOST_IDX_8814B 0xfff
+#define BIT_ACH11_HOST_IDX_8814B(x)                                            \
+	(((x) & BIT_MASK_ACH11_HOST_IDX_8814B)                                 \
+	 << BIT_SHIFT_ACH11_HOST_IDX_8814B)
+#define BITS_ACH11_HOST_IDX_8814B                                              \
+	(BIT_MASK_ACH11_HOST_IDX_8814B << BIT_SHIFT_ACH11_HOST_IDX_8814B)
+#define BIT_CLEAR_ACH11_HOST_IDX_8814B(x) ((x) & (~BITS_ACH11_HOST_IDX_8814B))
+#define BIT_GET_ACH11_HOST_IDX_8814B(x)                                        \
+	(((x) >> BIT_SHIFT_ACH11_HOST_IDX_8814B) &                             \
+	 BIT_MASK_ACH11_HOST_IDX_8814B)
+#define BIT_SET_ACH11_HOST_IDX_8814B(x, v)                                     \
+	(BIT_CLEAR_ACH11_HOST_IDX_8814B(x) | BIT_ACH11_HOST_IDX_8814B(v))
+
+/* 2 REG_ACH12_TXBD_IDX_8814B */
+
+#define BIT_SHIFT_ACH12_HW_IDX_8814B 16
+#define BIT_MASK_ACH12_HW_IDX_8814B 0xfff
+#define BIT_ACH12_HW_IDX_8814B(x)                                              \
+	(((x) & BIT_MASK_ACH12_HW_IDX_8814B) << BIT_SHIFT_ACH12_HW_IDX_8814B)
+#define BITS_ACH12_HW_IDX_8814B                                                \
+	(BIT_MASK_ACH12_HW_IDX_8814B << BIT_SHIFT_ACH12_HW_IDX_8814B)
+#define BIT_CLEAR_ACH12_HW_IDX_8814B(x) ((x) & (~BITS_ACH12_HW_IDX_8814B))
+#define BIT_GET_ACH12_HW_IDX_8814B(x)                                          \
+	(((x) >> BIT_SHIFT_ACH12_HW_IDX_8814B) & BIT_MASK_ACH12_HW_IDX_8814B)
+#define BIT_SET_ACH12_HW_IDX_8814B(x, v)                                       \
+	(BIT_CLEAR_ACH12_HW_IDX_8814B(x) | BIT_ACH12_HW_IDX_8814B(v))
+
+#define BIT_SHIFT_ACH12_HOST_IDX_8814B 0
+#define BIT_MASK_ACH12_HOST_IDX_8814B 0xfff
+#define BIT_ACH12_HOST_IDX_8814B(x)                                            \
+	(((x) & BIT_MASK_ACH12_HOST_IDX_8814B)                                 \
+	 << BIT_SHIFT_ACH12_HOST_IDX_8814B)
+#define BITS_ACH12_HOST_IDX_8814B                                              \
+	(BIT_MASK_ACH12_HOST_IDX_8814B << BIT_SHIFT_ACH12_HOST_IDX_8814B)
+#define BIT_CLEAR_ACH12_HOST_IDX_8814B(x) ((x) & (~BITS_ACH12_HOST_IDX_8814B))
+#define BIT_GET_ACH12_HOST_IDX_8814B(x)                                        \
+	(((x) >> BIT_SHIFT_ACH12_HOST_IDX_8814B) &                             \
+	 BIT_MASK_ACH12_HOST_IDX_8814B)
+#define BIT_SET_ACH12_HOST_IDX_8814B(x, v)                                     \
+	(BIT_CLEAR_ACH12_HOST_IDX_8814B(x) | BIT_ACH12_HOST_IDX_8814B(v))
+
+/* 2 REG_ACH13_TXBD_IDX_8814B */
+
+#define BIT_SHIFT_ACH13_HW_IDX_8814B 16
+#define BIT_MASK_ACH13_HW_IDX_8814B 0xfff
+#define BIT_ACH13_HW_IDX_8814B(x)                                              \
+	(((x) & BIT_MASK_ACH13_HW_IDX_8814B) << BIT_SHIFT_ACH13_HW_IDX_8814B)
+#define BITS_ACH13_HW_IDX_8814B                                                \
+	(BIT_MASK_ACH13_HW_IDX_8814B << BIT_SHIFT_ACH13_HW_IDX_8814B)
+#define BIT_CLEAR_ACH13_HW_IDX_8814B(x) ((x) & (~BITS_ACH13_HW_IDX_8814B))
+#define BIT_GET_ACH13_HW_IDX_8814B(x)                                          \
+	(((x) >> BIT_SHIFT_ACH13_HW_IDX_8814B) & BIT_MASK_ACH13_HW_IDX_8814B)
+#define BIT_SET_ACH13_HW_IDX_8814B(x, v)                                       \
+	(BIT_CLEAR_ACH13_HW_IDX_8814B(x) | BIT_ACH13_HW_IDX_8814B(v))
+
+#define BIT_SHIFT_ACH13_HOST_IDX_8814B 0
+#define BIT_MASK_ACH13_HOST_IDX_8814B 0xfff
+#define BIT_ACH13_HOST_IDX_8814B(x)                                            \
+	(((x) & BIT_MASK_ACH13_HOST_IDX_8814B)                                 \
+	 << BIT_SHIFT_ACH13_HOST_IDX_8814B)
+#define BITS_ACH13_HOST_IDX_8814B                                              \
+	(BIT_MASK_ACH13_HOST_IDX_8814B << BIT_SHIFT_ACH13_HOST_IDX_8814B)
+#define BIT_CLEAR_ACH13_HOST_IDX_8814B(x) ((x) & (~BITS_ACH13_HOST_IDX_8814B))
+#define BIT_GET_ACH13_HOST_IDX_8814B(x)                                        \
+	(((x) >> BIT_SHIFT_ACH13_HOST_IDX_8814B) &                             \
+	 BIT_MASK_ACH13_HOST_IDX_8814B)
+#define BIT_SET_ACH13_HOST_IDX_8814B(x, v)                                     \
+	(BIT_CLEAR_ACH13_HOST_IDX_8814B(x) | BIT_ACH13_HOST_IDX_8814B(v))
+
+/* 2 REG_AC_CHANNEL0_WEIGHT_8814B */
+
+#define BIT_SHIFT_AC_CHANNEL0_WEIGHT_8814B 0
+#define BIT_MASK_AC_CHANNEL0_WEIGHT_8814B 0xff
+#define BIT_AC_CHANNEL0_WEIGHT_8814B(x)                                        \
+	(((x) & BIT_MASK_AC_CHANNEL0_WEIGHT_8814B)                             \
+	 << BIT_SHIFT_AC_CHANNEL0_WEIGHT_8814B)
+#define BITS_AC_CHANNEL0_WEIGHT_8814B                                          \
+	(BIT_MASK_AC_CHANNEL0_WEIGHT_8814B                                     \
+	 << BIT_SHIFT_AC_CHANNEL0_WEIGHT_8814B)
+#define BIT_CLEAR_AC_CHANNEL0_WEIGHT_8814B(x)                                  \
+	((x) & (~BITS_AC_CHANNEL0_WEIGHT_8814B))
+#define BIT_GET_AC_CHANNEL0_WEIGHT_8814B(x)                                    \
+	(((x) >> BIT_SHIFT_AC_CHANNEL0_WEIGHT_8814B) &                         \
+	 BIT_MASK_AC_CHANNEL0_WEIGHT_8814B)
+#define BIT_SET_AC_CHANNEL0_WEIGHT_8814B(x, v)                                 \
+	(BIT_CLEAR_AC_CHANNEL0_WEIGHT_8814B(x) |                               \
+	 BIT_AC_CHANNEL0_WEIGHT_8814B(v))
+
+/* 2 REG_AC_CHANNEL1_WEIGHT_8814B */
+
+#define BIT_SHIFT_AC_CHANNEL1_WEIGHT_8814B 0
+#define BIT_MASK_AC_CHANNEL1_WEIGHT_8814B 0xff
+#define BIT_AC_CHANNEL1_WEIGHT_8814B(x)                                        \
+	(((x) & BIT_MASK_AC_CHANNEL1_WEIGHT_8814B)                             \
+	 << BIT_SHIFT_AC_CHANNEL1_WEIGHT_8814B)
+#define BITS_AC_CHANNEL1_WEIGHT_8814B                                          \
+	(BIT_MASK_AC_CHANNEL1_WEIGHT_8814B                                     \
+	 << BIT_SHIFT_AC_CHANNEL1_WEIGHT_8814B)
+#define BIT_CLEAR_AC_CHANNEL1_WEIGHT_8814B(x)                                  \
+	((x) & (~BITS_AC_CHANNEL1_WEIGHT_8814B))
+#define BIT_GET_AC_CHANNEL1_WEIGHT_8814B(x)                                    \
+	(((x) >> BIT_SHIFT_AC_CHANNEL1_WEIGHT_8814B) &                         \
+	 BIT_MASK_AC_CHANNEL1_WEIGHT_8814B)
+#define BIT_SET_AC_CHANNEL1_WEIGHT_8814B(x, v)                                 \
+	(BIT_CLEAR_AC_CHANNEL1_WEIGHT_8814B(x) |                               \
+	 BIT_AC_CHANNEL1_WEIGHT_8814B(v))
+
+/* 2 REG_AC_CHANNEL2_WEIGHT_8814B */
+
+#define BIT_SHIFT_AC_CHANNEL2_WEIGHT_8814B 0
+#define BIT_MASK_AC_CHANNEL2_WEIGHT_8814B 0xff
+#define BIT_AC_CHANNEL2_WEIGHT_8814B(x)                                        \
+	(((x) & BIT_MASK_AC_CHANNEL2_WEIGHT_8814B)                             \
+	 << BIT_SHIFT_AC_CHANNEL2_WEIGHT_8814B)
+#define BITS_AC_CHANNEL2_WEIGHT_8814B                                          \
+	(BIT_MASK_AC_CHANNEL2_WEIGHT_8814B                                     \
+	 << BIT_SHIFT_AC_CHANNEL2_WEIGHT_8814B)
+#define BIT_CLEAR_AC_CHANNEL2_WEIGHT_8814B(x)                                  \
+	((x) & (~BITS_AC_CHANNEL2_WEIGHT_8814B))
+#define BIT_GET_AC_CHANNEL2_WEIGHT_8814B(x)                                    \
+	(((x) >> BIT_SHIFT_AC_CHANNEL2_WEIGHT_8814B) &                         \
+	 BIT_MASK_AC_CHANNEL2_WEIGHT_8814B)
+#define BIT_SET_AC_CHANNEL2_WEIGHT_8814B(x, v)                                 \
+	(BIT_CLEAR_AC_CHANNEL2_WEIGHT_8814B(x) |                               \
+	 BIT_AC_CHANNEL2_WEIGHT_8814B(v))
+
+/* 2 REG_AC_CHANNEL3_WEIGHT_8814B */
+
+#define BIT_SHIFT_AC_CHANNEL3_WEIGHT_8814B 0
+#define BIT_MASK_AC_CHANNEL3_WEIGHT_8814B 0xff
+#define BIT_AC_CHANNEL3_WEIGHT_8814B(x)                                        \
+	(((x) & BIT_MASK_AC_CHANNEL3_WEIGHT_8814B)                             \
+	 << BIT_SHIFT_AC_CHANNEL3_WEIGHT_8814B)
+#define BITS_AC_CHANNEL3_WEIGHT_8814B                                          \
+	(BIT_MASK_AC_CHANNEL3_WEIGHT_8814B                                     \
+	 << BIT_SHIFT_AC_CHANNEL3_WEIGHT_8814B)
+#define BIT_CLEAR_AC_CHANNEL3_WEIGHT_8814B(x)                                  \
+	((x) & (~BITS_AC_CHANNEL3_WEIGHT_8814B))
+#define BIT_GET_AC_CHANNEL3_WEIGHT_8814B(x)                                    \
+	(((x) >> BIT_SHIFT_AC_CHANNEL3_WEIGHT_8814B) &                         \
+	 BIT_MASK_AC_CHANNEL3_WEIGHT_8814B)
+#define BIT_SET_AC_CHANNEL3_WEIGHT_8814B(x, v)                                 \
+	(BIT_CLEAR_AC_CHANNEL3_WEIGHT_8814B(x) |                               \
+	 BIT_AC_CHANNEL3_WEIGHT_8814B(v))
+
+/* 2 REG_AC_CHANNEL4_WEIGHT_8814B */
+
+#define BIT_SHIFT_AC_CHANNEL4_WEIGHT_8814B 0
+#define BIT_MASK_AC_CHANNEL4_WEIGHT_8814B 0xff
+#define BIT_AC_CHANNEL4_WEIGHT_8814B(x)                                        \
+	(((x) & BIT_MASK_AC_CHANNEL4_WEIGHT_8814B)                             \
+	 << BIT_SHIFT_AC_CHANNEL4_WEIGHT_8814B)
+#define BITS_AC_CHANNEL4_WEIGHT_8814B                                          \
+	(BIT_MASK_AC_CHANNEL4_WEIGHT_8814B                                     \
+	 << BIT_SHIFT_AC_CHANNEL4_WEIGHT_8814B)
+#define BIT_CLEAR_AC_CHANNEL4_WEIGHT_8814B(x)                                  \
+	((x) & (~BITS_AC_CHANNEL4_WEIGHT_8814B))
+#define BIT_GET_AC_CHANNEL4_WEIGHT_8814B(x)                                    \
+	(((x) >> BIT_SHIFT_AC_CHANNEL4_WEIGHT_8814B) &                         \
+	 BIT_MASK_AC_CHANNEL4_WEIGHT_8814B)
+#define BIT_SET_AC_CHANNEL4_WEIGHT_8814B(x, v)                                 \
+	(BIT_CLEAR_AC_CHANNEL4_WEIGHT_8814B(x) |                               \
+	 BIT_AC_CHANNEL4_WEIGHT_8814B(v))
+
+/* 2 REG_AC_CHANNEL5_WEIGHT_8814B */
+
+#define BIT_SHIFT_AC_CHANNEL5_WEIGHT_8814B 0
+#define BIT_MASK_AC_CHANNEL5_WEIGHT_8814B 0xff
+#define BIT_AC_CHANNEL5_WEIGHT_8814B(x)                                        \
+	(((x) & BIT_MASK_AC_CHANNEL5_WEIGHT_8814B)                             \
+	 << BIT_SHIFT_AC_CHANNEL5_WEIGHT_8814B)
+#define BITS_AC_CHANNEL5_WEIGHT_8814B                                          \
+	(BIT_MASK_AC_CHANNEL5_WEIGHT_8814B                                     \
+	 << BIT_SHIFT_AC_CHANNEL5_WEIGHT_8814B)
+#define BIT_CLEAR_AC_CHANNEL5_WEIGHT_8814B(x)                                  \
+	((x) & (~BITS_AC_CHANNEL5_WEIGHT_8814B))
+#define BIT_GET_AC_CHANNEL5_WEIGHT_8814B(x)                                    \
+	(((x) >> BIT_SHIFT_AC_CHANNEL5_WEIGHT_8814B) &                         \
+	 BIT_MASK_AC_CHANNEL5_WEIGHT_8814B)
+#define BIT_SET_AC_CHANNEL5_WEIGHT_8814B(x, v)                                 \
+	(BIT_CLEAR_AC_CHANNEL5_WEIGHT_8814B(x) |                               \
+	 BIT_AC_CHANNEL5_WEIGHT_8814B(v))
+
+/* 2 REG_AC_CHANNEL6_WEIGHT_8814B */
+
+#define BIT_SHIFT_AC_CHANNEL6_WEIGHT_8814B 0
+#define BIT_MASK_AC_CHANNEL6_WEIGHT_8814B 0xff
+#define BIT_AC_CHANNEL6_WEIGHT_8814B(x)                                        \
+	(((x) & BIT_MASK_AC_CHANNEL6_WEIGHT_8814B)                             \
+	 << BIT_SHIFT_AC_CHANNEL6_WEIGHT_8814B)
+#define BITS_AC_CHANNEL6_WEIGHT_8814B                                          \
+	(BIT_MASK_AC_CHANNEL6_WEIGHT_8814B                                     \
+	 << BIT_SHIFT_AC_CHANNEL6_WEIGHT_8814B)
+#define BIT_CLEAR_AC_CHANNEL6_WEIGHT_8814B(x)                                  \
+	((x) & (~BITS_AC_CHANNEL6_WEIGHT_8814B))
+#define BIT_GET_AC_CHANNEL6_WEIGHT_8814B(x)                                    \
+	(((x) >> BIT_SHIFT_AC_CHANNEL6_WEIGHT_8814B) &                         \
+	 BIT_MASK_AC_CHANNEL6_WEIGHT_8814B)
+#define BIT_SET_AC_CHANNEL6_WEIGHT_8814B(x, v)                                 \
+	(BIT_CLEAR_AC_CHANNEL6_WEIGHT_8814B(x) |                               \
+	 BIT_AC_CHANNEL6_WEIGHT_8814B(v))
+
+/* 2 REG_AC_CHANNEL7_WEIGHT_8814B */
+
+#define BIT_SHIFT_AC_CHANNEL7_WEIGHT_8814B 0
+#define BIT_MASK_AC_CHANNEL7_WEIGHT_8814B 0xff
+#define BIT_AC_CHANNEL7_WEIGHT_8814B(x)                                        \
+	(((x) & BIT_MASK_AC_CHANNEL7_WEIGHT_8814B)                             \
+	 << BIT_SHIFT_AC_CHANNEL7_WEIGHT_8814B)
+#define BITS_AC_CHANNEL7_WEIGHT_8814B                                          \
+	(BIT_MASK_AC_CHANNEL7_WEIGHT_8814B                                     \
+	 << BIT_SHIFT_AC_CHANNEL7_WEIGHT_8814B)
+#define BIT_CLEAR_AC_CHANNEL7_WEIGHT_8814B(x)                                  \
+	((x) & (~BITS_AC_CHANNEL7_WEIGHT_8814B))
+#define BIT_GET_AC_CHANNEL7_WEIGHT_8814B(x)                                    \
+	(((x) >> BIT_SHIFT_AC_CHANNEL7_WEIGHT_8814B) &                         \
+	 BIT_MASK_AC_CHANNEL7_WEIGHT_8814B)
+#define BIT_SET_AC_CHANNEL7_WEIGHT_8814B(x, v)                                 \
+	(BIT_CLEAR_AC_CHANNEL7_WEIGHT_8814B(x) |                               \
+	 BIT_AC_CHANNEL7_WEIGHT_8814B(v))
+
+/* 2 REG_AC_CHANNEL8_WEIGHT_8814B */
+
+#define BIT_SHIFT_AC_CHANNEL8_WEIGHT_8814B 0
+#define BIT_MASK_AC_CHANNEL8_WEIGHT_8814B 0xff
+#define BIT_AC_CHANNEL8_WEIGHT_8814B(x)                                        \
+	(((x) & BIT_MASK_AC_CHANNEL8_WEIGHT_8814B)                             \
+	 << BIT_SHIFT_AC_CHANNEL8_WEIGHT_8814B)
+#define BITS_AC_CHANNEL8_WEIGHT_8814B                                          \
+	(BIT_MASK_AC_CHANNEL8_WEIGHT_8814B                                     \
+	 << BIT_SHIFT_AC_CHANNEL8_WEIGHT_8814B)
+#define BIT_CLEAR_AC_CHANNEL8_WEIGHT_8814B(x)                                  \
+	((x) & (~BITS_AC_CHANNEL8_WEIGHT_8814B))
+#define BIT_GET_AC_CHANNEL8_WEIGHT_8814B(x)                                    \
+	(((x) >> BIT_SHIFT_AC_CHANNEL8_WEIGHT_8814B) &                         \
+	 BIT_MASK_AC_CHANNEL8_WEIGHT_8814B)
+#define BIT_SET_AC_CHANNEL8_WEIGHT_8814B(x, v)                                 \
+	(BIT_CLEAR_AC_CHANNEL8_WEIGHT_8814B(x) |                               \
+	 BIT_AC_CHANNEL8_WEIGHT_8814B(v))
+
+/* 2 REG_AC_CHANNEL9_WEIGHT_8814B */
+
+#define BIT_SHIFT_AC_CHANNEL9_WEIGHT_8814B 0
+#define BIT_MASK_AC_CHANNEL9_WEIGHT_8814B 0xff
+#define BIT_AC_CHANNEL9_WEIGHT_8814B(x)                                        \
+	(((x) & BIT_MASK_AC_CHANNEL9_WEIGHT_8814B)                             \
+	 << BIT_SHIFT_AC_CHANNEL9_WEIGHT_8814B)
+#define BITS_AC_CHANNEL9_WEIGHT_8814B                                          \
+	(BIT_MASK_AC_CHANNEL9_WEIGHT_8814B                                     \
+	 << BIT_SHIFT_AC_CHANNEL9_WEIGHT_8814B)
+#define BIT_CLEAR_AC_CHANNEL9_WEIGHT_8814B(x)                                  \
+	((x) & (~BITS_AC_CHANNEL9_WEIGHT_8814B))
+#define BIT_GET_AC_CHANNEL9_WEIGHT_8814B(x)                                    \
+	(((x) >> BIT_SHIFT_AC_CHANNEL9_WEIGHT_8814B) &                         \
+	 BIT_MASK_AC_CHANNEL9_WEIGHT_8814B)
+#define BIT_SET_AC_CHANNEL9_WEIGHT_8814B(x, v)                                 \
+	(BIT_CLEAR_AC_CHANNEL9_WEIGHT_8814B(x) |                               \
+	 BIT_AC_CHANNEL9_WEIGHT_8814B(v))
+
+/* 2 REG_AC_CHANNEL10_WEIGHT_8814B */
+
+#define BIT_SHIFT_AC_CHANNEL10_WEIGHT_8814B 0
+#define BIT_MASK_AC_CHANNEL10_WEIGHT_8814B 0xff
+#define BIT_AC_CHANNEL10_WEIGHT_8814B(x)                                       \
+	(((x) & BIT_MASK_AC_CHANNEL10_WEIGHT_8814B)                            \
+	 << BIT_SHIFT_AC_CHANNEL10_WEIGHT_8814B)
+#define BITS_AC_CHANNEL10_WEIGHT_8814B                                         \
+	(BIT_MASK_AC_CHANNEL10_WEIGHT_8814B                                    \
+	 << BIT_SHIFT_AC_CHANNEL10_WEIGHT_8814B)
+#define BIT_CLEAR_AC_CHANNEL10_WEIGHT_8814B(x)                                 \
+	((x) & (~BITS_AC_CHANNEL10_WEIGHT_8814B))
+#define BIT_GET_AC_CHANNEL10_WEIGHT_8814B(x)                                   \
+	(((x) >> BIT_SHIFT_AC_CHANNEL10_WEIGHT_8814B) &                        \
+	 BIT_MASK_AC_CHANNEL10_WEIGHT_8814B)
+#define BIT_SET_AC_CHANNEL10_WEIGHT_8814B(x, v)                                \
+	(BIT_CLEAR_AC_CHANNEL10_WEIGHT_8814B(x) |                              \
+	 BIT_AC_CHANNEL10_WEIGHT_8814B(v))
+
+/* 2 REG_AC_CHANNEL11_WEIGHT_8814B */
+
+#define BIT_SHIFT_AC_CHANNEL11_WEIGHT_8814B 0
+#define BIT_MASK_AC_CHANNEL11_WEIGHT_8814B 0xff
+#define BIT_AC_CHANNEL11_WEIGHT_8814B(x)                                       \
+	(((x) & BIT_MASK_AC_CHANNEL11_WEIGHT_8814B)                            \
+	 << BIT_SHIFT_AC_CHANNEL11_WEIGHT_8814B)
+#define BITS_AC_CHANNEL11_WEIGHT_8814B                                         \
+	(BIT_MASK_AC_CHANNEL11_WEIGHT_8814B                                    \
+	 << BIT_SHIFT_AC_CHANNEL11_WEIGHT_8814B)
+#define BIT_CLEAR_AC_CHANNEL11_WEIGHT_8814B(x)                                 \
+	((x) & (~BITS_AC_CHANNEL11_WEIGHT_8814B))
+#define BIT_GET_AC_CHANNEL11_WEIGHT_8814B(x)                                   \
+	(((x) >> BIT_SHIFT_AC_CHANNEL11_WEIGHT_8814B) &                        \
+	 BIT_MASK_AC_CHANNEL11_WEIGHT_8814B)
+#define BIT_SET_AC_CHANNEL11_WEIGHT_8814B(x, v)                                \
+	(BIT_CLEAR_AC_CHANNEL11_WEIGHT_8814B(x) |                              \
+	 BIT_AC_CHANNEL11_WEIGHT_8814B(v))
+
+/* 2 REG_AC_CHANNEL12_WEIGHT_8814B */
+
+#define BIT_SHIFT_AC_CHANNEL12_WEIGHT_8814B 0
+#define BIT_MASK_AC_CHANNEL12_WEIGHT_8814B 0xff
+#define BIT_AC_CHANNEL12_WEIGHT_8814B(x)                                       \
+	(((x) & BIT_MASK_AC_CHANNEL12_WEIGHT_8814B)                            \
+	 << BIT_SHIFT_AC_CHANNEL12_WEIGHT_8814B)
+#define BITS_AC_CHANNEL12_WEIGHT_8814B                                         \
+	(BIT_MASK_AC_CHANNEL12_WEIGHT_8814B                                    \
+	 << BIT_SHIFT_AC_CHANNEL12_WEIGHT_8814B)
+#define BIT_CLEAR_AC_CHANNEL12_WEIGHT_8814B(x)                                 \
+	((x) & (~BITS_AC_CHANNEL12_WEIGHT_8814B))
+#define BIT_GET_AC_CHANNEL12_WEIGHT_8814B(x)                                   \
+	(((x) >> BIT_SHIFT_AC_CHANNEL12_WEIGHT_8814B) &                        \
+	 BIT_MASK_AC_CHANNEL12_WEIGHT_8814B)
+#define BIT_SET_AC_CHANNEL12_WEIGHT_8814B(x, v)                                \
+	(BIT_CLEAR_AC_CHANNEL12_WEIGHT_8814B(x) |                              \
+	 BIT_AC_CHANNEL12_WEIGHT_8814B(v))
+
+/* 2 REG_AC_CHANNEL13_WEIGHT_8814B */
+
+#define BIT_SHIFT_AC_CHANNEL13_WEIGHT_8814B 0
+#define BIT_MASK_AC_CHANNEL13_WEIGHT_8814B 0xff
+#define BIT_AC_CHANNEL13_WEIGHT_8814B(x)                                       \
+	(((x) & BIT_MASK_AC_CHANNEL13_WEIGHT_8814B)                            \
+	 << BIT_SHIFT_AC_CHANNEL13_WEIGHT_8814B)
+#define BITS_AC_CHANNEL13_WEIGHT_8814B                                         \
+	(BIT_MASK_AC_CHANNEL13_WEIGHT_8814B                                    \
+	 << BIT_SHIFT_AC_CHANNEL13_WEIGHT_8814B)
+#define BIT_CLEAR_AC_CHANNEL13_WEIGHT_8814B(x)                                 \
+	((x) & (~BITS_AC_CHANNEL13_WEIGHT_8814B))
+#define BIT_GET_AC_CHANNEL13_WEIGHT_8814B(x)                                   \
+	(((x) >> BIT_SHIFT_AC_CHANNEL13_WEIGHT_8814B) &                        \
+	 BIT_MASK_AC_CHANNEL13_WEIGHT_8814B)
+#define BIT_SET_AC_CHANNEL13_WEIGHT_8814B(x, v)                                \
+	(BIT_CLEAR_AC_CHANNEL13_WEIGHT_8814B(x) |                              \
+	 BIT_AC_CHANNEL13_WEIGHT_8814B(v))
+
+/* 2 REG_PCIE_HISR2_8814B */
+#define BIT_BCNDMAINT_P4_8814B BIT(31)
+#define BIT_BCNDMAINT_P3_8814B BIT(30)
+#define BIT_BCNDMAINT_P2_8814B BIT(29)
+#define BIT_BCNDMAINT_P1_8814B BIT(28)
+#define BIT_SCH_PHY_TXOP_SIFS_INT_8814B BIT(23)
+#define BIT_ATIMEND7_8814B BIT(22)
+#define BIT_ATIMEND6_8814B BIT(21)
+#define BIT_ATIMEND5_8814B BIT(20)
+#define BIT_ATIMEND4_8814B BIT(19)
+#define BIT_ATIMEND3_8814B BIT(18)
+#define BIT_ATIMEND2_8814B BIT(17)
+#define BIT_ATIMEND1_8814B BIT(16)
+#define BIT_TXBCN7OK_8814B BIT(14)
+#define BIT_TXBCN6OK_8814B BIT(13)
+#define BIT_TXBCN5OK_8814B BIT(12)
+#define BIT_TXBCN4OK_8814B BIT(11)
+#define BIT_TXBCN3OK_8814B BIT(10)
+#define BIT_TXBCN2OK_8814B BIT(9)
+#define BIT_TXBCN1OK_8814B BIT(8)
+#define BIT_TXBCN7ERR_8814B BIT(6)
+#define BIT_TXBCN6ERR_8814B BIT(5)
+#define BIT_TXBCN5ERR_8814B BIT(4)
+#define BIT_TXBCN4ERR_8814B BIT(3)
+#define BIT_TXBCN3ERR_8814B BIT(2)
+#define BIT_TXBCN2ERR_8814B BIT(1)
+#define BIT_TXBCN1ERR_8814B BIT(0)
+
+/* 2 REG_PCIE_HISR3_8814B */
+#define BIT_GTINT12_8814B BIT(24)
+#define BIT_GTINT11_8814B BIT(23)
+#define BIT_GTINT10_8814B BIT(22)
+#define BIT_GTINT9_8814B BIT(21)
+#define BIT_RX_DESC_BUF_FULL_8814B BIT(20)
+#define BIT_CPHY_LDO_OCP_DET_INT_8814B BIT(19)
+#define BIT_WDT_PLATFORM_INT_8814B BIT(18)
+#define BIT_WDT_CPU_INT_8814B BIT(17)
+#define BIT_SETH2CDOK_8814B BIT(16)
+#define BIT_H2C_CMD_FULL_8814B BIT(15)
+#define BIT_PKT_TRANS_ERR_8814B BIT(14)
+#define BIT_TXSHORTCUT_TXDESUPDATEOK_8814B BIT(13)
+#define BIT_TXSHORTCUT_BKUPDATEOK_8814B BIT(12)
+#define BIT_TXSHORTCUT_BEUPDATEOK_8814B BIT(11)
+#define BIT_TXSHORTCUT_VIUPDATEOK_8814B BIT(10)
+#define BIT_TXSHORTCUT_VOUPDATEOK_8814B BIT(9)
+#define BIT_SEARCH_FAIL_8814B BIT(8)
+#define BIT_PWR_INT_127TO96_8814B BIT(7)
+#define BIT_PWR_INT_95TO64_8814B BIT(6)
+#define BIT_PWR_INT_63TO32_8814B BIT(5)
+#define BIT_PWR_INT_31TO0_8814B BIT(4)
+#define BIT_RX_DMA_STUCK_8814B BIT(3)
+#define BIT_TX_DMA_STUCK_8814B BIT(2)
+#define BIT_DDMA0_LP_INT_8814B BIT(1)
+#define BIT_DDMA0_HP_INT_8814B BIT(0)
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_QUEUELIST_INFO0_8814B */
+
+#define BIT_SHIFT_QINFO0_8814B 0
+#define BIT_MASK_QINFO0_8814B 0xffffffffL
+#define BIT_QINFO0_8814B(x)                                                    \
+	(((x) & BIT_MASK_QINFO0_8814B) << BIT_SHIFT_QINFO0_8814B)
+#define BITS_QINFO0_8814B (BIT_MASK_QINFO0_8814B << BIT_SHIFT_QINFO0_8814B)
+#define BIT_CLEAR_QINFO0_8814B(x) ((x) & (~BITS_QINFO0_8814B))
+#define BIT_GET_QINFO0_8814B(x)                                                \
+	(((x) >> BIT_SHIFT_QINFO0_8814B) & BIT_MASK_QINFO0_8814B)
+#define BIT_SET_QINFO0_8814B(x, v)                                             \
+	(BIT_CLEAR_QINFO0_8814B(x) | BIT_QINFO0_8814B(v))
+
+/* 2 REG_QUEUELIST_INFO1_8814B */
+
+#define BIT_SHIFT_QINFO1_8814B 0
+#define BIT_MASK_QINFO1_8814B 0xffffffffL
+#define BIT_QINFO1_8814B(x)                                                    \
+	(((x) & BIT_MASK_QINFO1_8814B) << BIT_SHIFT_QINFO1_8814B)
+#define BITS_QINFO1_8814B (BIT_MASK_QINFO1_8814B << BIT_SHIFT_QINFO1_8814B)
+#define BIT_CLEAR_QINFO1_8814B(x) ((x) & (~BITS_QINFO1_8814B))
+#define BIT_GET_QINFO1_8814B(x)                                                \
+	(((x) >> BIT_SHIFT_QINFO1_8814B) & BIT_MASK_QINFO1_8814B)
+#define BIT_SET_QINFO1_8814B(x, v)                                             \
+	(BIT_CLEAR_QINFO1_8814B(x) | BIT_QINFO1_8814B(v))
+
+/* 2 REG_QUEUELIST_INFO2_8814B */
+
+#define BIT_SHIFT_QINFO2_8814B 0
+#define BIT_MASK_QINFO2_8814B 0xffffffffL
+#define BIT_QINFO2_8814B(x)                                                    \
+	(((x) & BIT_MASK_QINFO2_8814B) << BIT_SHIFT_QINFO2_8814B)
+#define BITS_QINFO2_8814B (BIT_MASK_QINFO2_8814B << BIT_SHIFT_QINFO2_8814B)
+#define BIT_CLEAR_QINFO2_8814B(x) ((x) & (~BITS_QINFO2_8814B))
+#define BIT_GET_QINFO2_8814B(x)                                                \
+	(((x) >> BIT_SHIFT_QINFO2_8814B) & BIT_MASK_QINFO2_8814B)
+#define BIT_SET_QINFO2_8814B(x, v)                                             \
+	(BIT_CLEAR_QINFO2_8814B(x) | BIT_QINFO2_8814B(v))
+
+/* 2 REG_QUEUELIST_INFO3_8814B */
+
+#define BIT_SHIFT_QINFO3_8814B 0
+#define BIT_MASK_QINFO3_8814B 0xffffffffL
+#define BIT_QINFO3_8814B(x)                                                    \
+	(((x) & BIT_MASK_QINFO3_8814B) << BIT_SHIFT_QINFO3_8814B)
+#define BITS_QINFO3_8814B (BIT_MASK_QINFO3_8814B << BIT_SHIFT_QINFO3_8814B)
+#define BIT_CLEAR_QINFO3_8814B(x) ((x) & (~BITS_QINFO3_8814B))
+#define BIT_GET_QINFO3_8814B(x)                                                \
+	(((x) >> BIT_SHIFT_QINFO3_8814B) & BIT_MASK_QINFO3_8814B)
+#define BIT_SET_QINFO3_8814B(x, v)                                             \
+	(BIT_CLEAR_QINFO3_8814B(x) | BIT_QINFO3_8814B(v))
+
+/* 2 REG_QUEUELIST_INFO_EMPTY_8814B */
+#define BIT_FWCMDQ_EMPTY_8814B BIT(31)
+#define BIT_MGQ_CPU_EMPTY_V1_8814B BIT(30)
+#define BIT_BCNQ_EMPTY_EXTP0_8814B BIT(29)
+#define BIT_BCNQ_EMPTY_PORT4_8814B BIT(28)
+#define BIT_BCNQ_EMPTY_PORT3_8814B BIT(27)
+#define BIT_BCNQ_EMPTY_PORT2_8814B BIT(26)
+#define BIT_BCNQ_EMPTY_PORT1_8814B BIT(25)
+#define BIT_BCNQ_EMPTY_PORT0_8814B BIT(24)
+#define BIT_HQQ_EMPTY_V1_8814B BIT(23)
+#define BIT_MQQ_EMPTY_V2_8814B BIT(22)
+#define BIT_S1_EMPTY_8814B BIT(21)
+#define BIT_S0_EMPTY_8814B BIT(20)
+#define BIT_AC19Q_EMPTY_8814B BIT(19)
+#define BIT_AC18Q_EMPTY_8814B BIT(18)
+#define BIT_AC17Q_EMPTY_8814B BIT(17)
+#define BIT_AC16Q_EMPTY_8814B BIT(16)
+#define BIT_AC15Q_EMPTY_8814B BIT(15)
+#define BIT_AC14Q_EMPTY_8814B BIT(14)
+#define BIT_AC13Q_EMPTY_8814B BIT(13)
+#define BIT_AC12Q_EMPTY_8814B BIT(12)
+#define BIT_AC11Q_EMPTY_8814B BIT(11)
+#define BIT_AC10Q_EMPTY_8814B BIT(10)
+#define BIT_AC9Q_EMPTY_8814B BIT(9)
+#define BIT_AC8Q_EMPTY_8814B BIT(8)
+#define BIT_AC7Q_EMPTY_8814B BIT(7)
+#define BIT_AC6Q_EMPTY_8814B BIT(6)
+#define BIT_AC5Q_EMPTY_8814B BIT(5)
+#define BIT_AC4Q_EMPTY_8814B BIT(4)
+#define BIT_AC3Q_EMPTY_8814B BIT(3)
+#define BIT_AC2Q_EMPTY_8814B BIT(2)
+#define BIT_AC1Q_EMPTY_8814B BIT(1)
+#define BIT_AC0Q_EMPTY_8814B BIT(0)
+
+/* 2 REG_QUEUELIST_ACQ_EN_8814B */
+
+#define BIT_SHIFT_QINFO_CTRL_8814B 24
+#define BIT_MASK_QINFO_CTRL_8814B 0x3f
+#define BIT_QINFO_CTRL_8814B(x)                                                \
+	(((x) & BIT_MASK_QINFO_CTRL_8814B) << BIT_SHIFT_QINFO_CTRL_8814B)
+#define BITS_QINFO_CTRL_8814B                                                  \
+	(BIT_MASK_QINFO_CTRL_8814B << BIT_SHIFT_QINFO_CTRL_8814B)
+#define BIT_CLEAR_QINFO_CTRL_8814B(x) ((x) & (~BITS_QINFO_CTRL_8814B))
+#define BIT_GET_QINFO_CTRL_8814B(x)                                            \
+	(((x) >> BIT_SHIFT_QINFO_CTRL_8814B) & BIT_MASK_QINFO_CTRL_8814B)
+#define BIT_SET_QINFO_CTRL_8814B(x, v)                                         \
+	(BIT_CLEAR_QINFO_CTRL_8814B(x) | BIT_QINFO_CTRL_8814B(v))
+
+#define BIT_SHIFT_QINFO_MODE_BAND_8814B 20
+#define BIT_MASK_QINFO_MODE_BAND_8814B 0x7
+#define BIT_QINFO_MODE_BAND_8814B(x)                                           \
+	(((x) & BIT_MASK_QINFO_MODE_BAND_8814B)                                \
+	 << BIT_SHIFT_QINFO_MODE_BAND_8814B)
+#define BITS_QINFO_MODE_BAND_8814B                                             \
+	(BIT_MASK_QINFO_MODE_BAND_8814B << BIT_SHIFT_QINFO_MODE_BAND_8814B)
+#define BIT_CLEAR_QINFO_MODE_BAND_8814B(x) ((x) & (~BITS_QINFO_MODE_BAND_8814B))
+#define BIT_GET_QINFO_MODE_BAND_8814B(x)                                       \
+	(((x) >> BIT_SHIFT_QINFO_MODE_BAND_8814B) &                            \
+	 BIT_MASK_QINFO_MODE_BAND_8814B)
+#define BIT_SET_QINFO_MODE_BAND_8814B(x, v)                                    \
+	(BIT_CLEAR_QINFO_MODE_BAND_8814B(x) | BIT_QINFO_MODE_BAND_8814B(v))
+
+#define BIT_ACQ19_ENABLE_8814B BIT(19)
+#define BIT_ACQ18_ENABLE_8814B BIT(18)
+#define BIT_ACQ17_ENABLE_8814B BIT(17)
+#define BIT_ACQ16_ENABLE_8814B BIT(16)
+#define BIT_ACQ15_ENABLE_8814B BIT(15)
+#define BIT_ACQ14_ENABLE_8814B BIT(14)
+#define BIT_ACQ13_ENABLE_8814B BIT(13)
+#define BIT_ACQ12_ENABLE_8814B BIT(12)
+#define BIT_ACQ11_ENABLE_8814B BIT(11)
+#define BIT_ACQ10_ENABLE_8814B BIT(10)
+#define BIT_ACQ9_ENABLE_8814B BIT(9)
+#define BIT_ACQ8_ENABLE_8814B BIT(8)
+#define BIT_ACQ7_ENABLE_8814B BIT(7)
+#define BIT_ACQ6_ENABLE_8814B BIT(6)
+#define BIT_ACQ5_ENABLE_8814B BIT(5)
+#define BIT_ACQ4_ENABLE_8814B BIT(4)
+#define BIT_ACQ3_ENABLE_8814B BIT(3)
+#define BIT_ACQ2_ENABLE_8814B BIT(2)
+#define BIT_ACQ1_ENABLE_8814B BIT(1)
+#define BIT_ACQ0_ENABLE_8814B BIT(0)
+
+/* 2 REG_BCNQ_BDNY_V2_8814B */
+
+#define BIT_SHIFT_BCNQ_PGBNDY_WSEL_8814B 28
+#define BIT_MASK_BCNQ_PGBNDY_WSEL_8814B 0x7
+#define BIT_BCNQ_PGBNDY_WSEL_8814B(x)                                          \
+	(((x) & BIT_MASK_BCNQ_PGBNDY_WSEL_8814B)                               \
+	 << BIT_SHIFT_BCNQ_PGBNDY_WSEL_8814B)
+#define BITS_BCNQ_PGBNDY_WSEL_8814B                                            \
+	(BIT_MASK_BCNQ_PGBNDY_WSEL_8814B << BIT_SHIFT_BCNQ_PGBNDY_WSEL_8814B)
+#define BIT_CLEAR_BCNQ_PGBNDY_WSEL_8814B(x)                                    \
+	((x) & (~BITS_BCNQ_PGBNDY_WSEL_8814B))
+#define BIT_GET_BCNQ_PGBNDY_WSEL_8814B(x)                                      \
+	(((x) >> BIT_SHIFT_BCNQ_PGBNDY_WSEL_8814B) &                           \
+	 BIT_MASK_BCNQ_PGBNDY_WSEL_8814B)
+#define BIT_SET_BCNQ_PGBNDY_WSEL_8814B(x, v)                                   \
+	(BIT_CLEAR_BCNQ_PGBNDY_WSEL_8814B(x) | BIT_BCNQ_PGBNDY_WSEL_8814B(v))
+
+#define BIT_SHIFT_BCNQ_PGBNDY_RCONTENT_8814B 12
+#define BIT_MASK_BCNQ_PGBNDY_RCONTENT_8814B 0xfff
+#define BIT_BCNQ_PGBNDY_RCONTENT_8814B(x)                                      \
+	(((x) & BIT_MASK_BCNQ_PGBNDY_RCONTENT_8814B)                           \
+	 << BIT_SHIFT_BCNQ_PGBNDY_RCONTENT_8814B)
+#define BITS_BCNQ_PGBNDY_RCONTENT_8814B                                        \
+	(BIT_MASK_BCNQ_PGBNDY_RCONTENT_8814B                                   \
+	 << BIT_SHIFT_BCNQ_PGBNDY_RCONTENT_8814B)
+#define BIT_CLEAR_BCNQ_PGBNDY_RCONTENT_8814B(x)                                \
+	((x) & (~BITS_BCNQ_PGBNDY_RCONTENT_8814B))
+#define BIT_GET_BCNQ_PGBNDY_RCONTENT_8814B(x)                                  \
+	(((x) >> BIT_SHIFT_BCNQ_PGBNDY_RCONTENT_8814B) &                       \
+	 BIT_MASK_BCNQ_PGBNDY_RCONTENT_8814B)
+#define BIT_SET_BCNQ_PGBNDY_RCONTENT_8814B(x, v)                               \
+	(BIT_CLEAR_BCNQ_PGBNDY_RCONTENT_8814B(x) |                             \
+	 BIT_BCNQ_PGBNDY_RCONTENT_8814B(v))
+
+#define BIT_SHIFT_BCNQ_PGBNDY_WCONTENT_8814B 0
+#define BIT_MASK_BCNQ_PGBNDY_WCONTENT_8814B 0xfff
+#define BIT_BCNQ_PGBNDY_WCONTENT_8814B(x)                                      \
+	(((x) & BIT_MASK_BCNQ_PGBNDY_WCONTENT_8814B)                           \
+	 << BIT_SHIFT_BCNQ_PGBNDY_WCONTENT_8814B)
+#define BITS_BCNQ_PGBNDY_WCONTENT_8814B                                        \
+	(BIT_MASK_BCNQ_PGBNDY_WCONTENT_8814B                                   \
+	 << BIT_SHIFT_BCNQ_PGBNDY_WCONTENT_8814B)
+#define BIT_CLEAR_BCNQ_PGBNDY_WCONTENT_8814B(x)                                \
+	((x) & (~BITS_BCNQ_PGBNDY_WCONTENT_8814B))
+#define BIT_GET_BCNQ_PGBNDY_WCONTENT_8814B(x)                                  \
+	(((x) >> BIT_SHIFT_BCNQ_PGBNDY_WCONTENT_8814B) &                       \
+	 BIT_MASK_BCNQ_PGBNDY_WCONTENT_8814B)
+#define BIT_SET_BCNQ_PGBNDY_WCONTENT_8814B(x, v)                               \
+	(BIT_CLEAR_BCNQ_PGBNDY_WCONTENT_8814B(x) |                             \
+	 BIT_BCNQ_PGBNDY_WCONTENT_8814B(v))
+
+/* 2 REG_CPU_MGQ_INFO_8814B */
+#define BIT_CPUMGT_CLR_V1_8814B BIT(30)
+#define BIT_CPUMGT_POLL_8814B BIT(29)
+#define BIT_BCN_EXT_POLL_8814B BIT(21)
+#define BIT_BCN4_POLL_8814B BIT(20)
+#define BIT_BCN3_POLL_8814B BIT(19)
+#define BIT_BCN2_POLL_8814B BIT(18)
+#define BIT_BCN1_POLL_V1_8814B BIT(17)
+#define BIT_BCN_POLL_V1_8814B BIT(16)
+
+#define BIT_SHIFT_FREE_TAIL_PAGE_8814B 0
+#define BIT_MASK_FREE_TAIL_PAGE_8814B 0xfff
+#define BIT_FREE_TAIL_PAGE_8814B(x)                                            \
+	(((x) & BIT_MASK_FREE_TAIL_PAGE_8814B)                                 \
+	 << BIT_SHIFT_FREE_TAIL_PAGE_8814B)
+#define BITS_FREE_TAIL_PAGE_8814B                                              \
+	(BIT_MASK_FREE_TAIL_PAGE_8814B << BIT_SHIFT_FREE_TAIL_PAGE_8814B)
+#define BIT_CLEAR_FREE_TAIL_PAGE_8814B(x) ((x) & (~BITS_FREE_TAIL_PAGE_8814B))
+#define BIT_GET_FREE_TAIL_PAGE_8814B(x)                                        \
+	(((x) >> BIT_SHIFT_FREE_TAIL_PAGE_8814B) &                             \
+	 BIT_MASK_FREE_TAIL_PAGE_8814B)
+#define BIT_SET_FREE_TAIL_PAGE_8814B(x, v)                                     \
+	(BIT_CLEAR_FREE_TAIL_PAGE_8814B(x) | BIT_FREE_TAIL_PAGE_8814B(v))
+
+/* 2 REG_FWHW_TXQ_CTRL_8814B */
+#define BIT_RTS_LIMIT_IN_OFDM_8814B BIT(23)
+#define BIT_EN_RD_RESP_NAV_BK_8814B BIT(21)
+#define BIT_EN_WR_FREE_TAIL_8814B BIT(20)
+#define BIT_NOTXRPT_USERATE_EN_8814B BIT(19)
+#define BIT_DIS_TXFAIL_RPT_8814B BIT(18)
+#define BIT_FTM_TIMEOUT_BYPASS_8814B BIT(16)
+#define BIT_EN_BCNQ_DL5_8814B BIT(13)
+#define BIT_EN_BCNQ_DL4_8814B BIT(12)
+#define BIT_EN_BCNQ_DL3_8814B BIT(11)
+#define BIT_EN_BCNQ_DL2_8814B BIT(10)
+#define BIT_EN_BCNQ_DL1_8814B BIT(9)
+#define BIT_EN_BCNQ_DL0_8814B BIT(8)
+#define BIT_EN_RTY_BK_8814B BIT(7)
+#define BIT_EN_USE_INI_RAT_8814B BIT(6)
+#define BIT_EN_RTS_NAV_BK_8814B BIT(5)
+#define BIT_DIS_SSN_CHECK_8814B BIT(4)
+#define BIT_MACID_MATCH_RTS_8814B BIT(3)
+#define BIT_EN_BCN_TRXRPT_V1_8814B BIT(2)
+#define BIT_EN_FTMRPT_V1_8814B BIT(1)
+#define BIT_BMC_NAV_PROTECT_8814B BIT(0)
+
+/* 2 REG_DATAFB_SEL_8814B */
+#define BIT_BROADCAST_RTY_EN_8814B BIT(3)
+#define BIT_EN_RTY_BK_COD_8814B BIT(2)
+
+#define BIT_SHIFT__DATA_FALLBACK_SEL_8814B 0
+#define BIT_MASK__DATA_FALLBACK_SEL_8814B 0x3
+#define BIT__DATA_FALLBACK_SEL_8814B(x)                                        \
+	(((x) & BIT_MASK__DATA_FALLBACK_SEL_8814B)                             \
+	 << BIT_SHIFT__DATA_FALLBACK_SEL_8814B)
+#define BITS__DATA_FALLBACK_SEL_8814B                                          \
+	(BIT_MASK__DATA_FALLBACK_SEL_8814B                                     \
+	 << BIT_SHIFT__DATA_FALLBACK_SEL_8814B)
+#define BIT_CLEAR__DATA_FALLBACK_SEL_8814B(x)                                  \
+	((x) & (~BITS__DATA_FALLBACK_SEL_8814B))
+#define BIT_GET__DATA_FALLBACK_SEL_8814B(x)                                    \
+	(((x) >> BIT_SHIFT__DATA_FALLBACK_SEL_8814B) &                         \
+	 BIT_MASK__DATA_FALLBACK_SEL_8814B)
+#define BIT_SET__DATA_FALLBACK_SEL_8814B(x, v)                                 \
+	(BIT_CLEAR__DATA_FALLBACK_SEL_8814B(x) |                               \
+	 BIT__DATA_FALLBACK_SEL_8814B(v))
+
+/* 2 REG_TXBDNY_8814B */
+
+#define BIT_SHIFT_TXBNDY_8814B 0
+#define BIT_MASK_TXBNDY_8814B 0xfff
+#define BIT_TXBNDY_8814B(x)                                                    \
+	(((x) & BIT_MASK_TXBNDY_8814B) << BIT_SHIFT_TXBNDY_8814B)
+#define BITS_TXBNDY_8814B (BIT_MASK_TXBNDY_8814B << BIT_SHIFT_TXBNDY_8814B)
+#define BIT_CLEAR_TXBNDY_8814B(x) ((x) & (~BITS_TXBNDY_8814B))
+#define BIT_GET_TXBNDY_8814B(x)                                                \
+	(((x) >> BIT_SHIFT_TXBNDY_8814B) & BIT_MASK_TXBNDY_8814B)
+#define BIT_SET_TXBNDY_8814B(x, v)                                             \
+	(BIT_CLEAR_TXBNDY_8814B(x) | BIT_TXBNDY_8814B(v))
+
+/* 2 REG_LIFETIME_EN_8814B */
+#define BIT_BT_INT_CPU_8814B BIT(7)
+#define BIT_BT_INT_PTA_8814B BIT(6)
+#define BIT_EN_CTRL_RTYBIT_8814B BIT(4)
+#define BIT_LIFETIME_BK_EN_8814B BIT(3)
+#define BIT_LIFETIME_BE_EN_8814B BIT(2)
+#define BIT_LIFETIME_VI_EN_8814B BIT(1)
+#define BIT_LIFETIME_VO_EN_8814B BIT(0)
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_SPEC_SIFS_8814B */
+
+#define BIT_SHIFT_SPEC_SIFS_OFDM_PTCL_8814B 8
+#define BIT_MASK_SPEC_SIFS_OFDM_PTCL_8814B 0xff
+#define BIT_SPEC_SIFS_OFDM_PTCL_8814B(x)                                       \
+	(((x) & BIT_MASK_SPEC_SIFS_OFDM_PTCL_8814B)                            \
+	 << BIT_SHIFT_SPEC_SIFS_OFDM_PTCL_8814B)
+#define BITS_SPEC_SIFS_OFDM_PTCL_8814B                                         \
+	(BIT_MASK_SPEC_SIFS_OFDM_PTCL_8814B                                    \
+	 << BIT_SHIFT_SPEC_SIFS_OFDM_PTCL_8814B)
+#define BIT_CLEAR_SPEC_SIFS_OFDM_PTCL_8814B(x)                                 \
+	((x) & (~BITS_SPEC_SIFS_OFDM_PTCL_8814B))
+#define BIT_GET_SPEC_SIFS_OFDM_PTCL_8814B(x)                                   \
+	(((x) >> BIT_SHIFT_SPEC_SIFS_OFDM_PTCL_8814B) &                        \
+	 BIT_MASK_SPEC_SIFS_OFDM_PTCL_8814B)
+#define BIT_SET_SPEC_SIFS_OFDM_PTCL_8814B(x, v)                                \
+	(BIT_CLEAR_SPEC_SIFS_OFDM_PTCL_8814B(x) |                              \
+	 BIT_SPEC_SIFS_OFDM_PTCL_8814B(v))
+
+#define BIT_SHIFT_SPEC_SIFS_CCK_PTCL_8814B 0
+#define BIT_MASK_SPEC_SIFS_CCK_PTCL_8814B 0xff
+#define BIT_SPEC_SIFS_CCK_PTCL_8814B(x)                                        \
+	(((x) & BIT_MASK_SPEC_SIFS_CCK_PTCL_8814B)                             \
+	 << BIT_SHIFT_SPEC_SIFS_CCK_PTCL_8814B)
+#define BITS_SPEC_SIFS_CCK_PTCL_8814B                                          \
+	(BIT_MASK_SPEC_SIFS_CCK_PTCL_8814B                                     \
+	 << BIT_SHIFT_SPEC_SIFS_CCK_PTCL_8814B)
+#define BIT_CLEAR_SPEC_SIFS_CCK_PTCL_8814B(x)                                  \
+	((x) & (~BITS_SPEC_SIFS_CCK_PTCL_8814B))
+#define BIT_GET_SPEC_SIFS_CCK_PTCL_8814B(x)                                    \
+	(((x) >> BIT_SHIFT_SPEC_SIFS_CCK_PTCL_8814B) &                         \
+	 BIT_MASK_SPEC_SIFS_CCK_PTCL_8814B)
+#define BIT_SET_SPEC_SIFS_CCK_PTCL_8814B(x, v)                                 \
+	(BIT_CLEAR_SPEC_SIFS_CCK_PTCL_8814B(x) |                               \
+	 BIT_SPEC_SIFS_CCK_PTCL_8814B(v))
+
+/* 2 REG_RETRY_LIMIT_8814B */
+
+#define BIT_SHIFT_SRL_8814B 8
+#define BIT_MASK_SRL_8814B 0x3f
+#define BIT_SRL_8814B(x) (((x) & BIT_MASK_SRL_8814B) << BIT_SHIFT_SRL_8814B)
+#define BITS_SRL_8814B (BIT_MASK_SRL_8814B << BIT_SHIFT_SRL_8814B)
+#define BIT_CLEAR_SRL_8814B(x) ((x) & (~BITS_SRL_8814B))
+#define BIT_GET_SRL_8814B(x) (((x) >> BIT_SHIFT_SRL_8814B) & BIT_MASK_SRL_8814B)
+#define BIT_SET_SRL_8814B(x, v) (BIT_CLEAR_SRL_8814B(x) | BIT_SRL_8814B(v))
+
+#define BIT_SHIFT_LRL_8814B 0
+#define BIT_MASK_LRL_8814B 0x3f
+#define BIT_LRL_8814B(x) (((x) & BIT_MASK_LRL_8814B) << BIT_SHIFT_LRL_8814B)
+#define BITS_LRL_8814B (BIT_MASK_LRL_8814B << BIT_SHIFT_LRL_8814B)
+#define BIT_CLEAR_LRL_8814B(x) ((x) & (~BITS_LRL_8814B))
+#define BIT_GET_LRL_8814B(x) (((x) >> BIT_SHIFT_LRL_8814B) & BIT_MASK_LRL_8814B)
+#define BIT_SET_LRL_8814B(x, v) (BIT_CLEAR_LRL_8814B(x) | BIT_LRL_8814B(v))
+
+/* 2 REG_TXBF_CTRL_8814B */
+#define BIT_ENABLE_NDPA_8814B BIT(31)
+#define BIT_NDPA_PARA_8814B BIT(30)
+#define BIT_PROP_TXBF_8814B BIT(29)
+#define BIT_EN_NDPA_INT_8814B BIT(28)
+#define BIT_TXBF1_80M_160M_8814B BIT(27)
+#define BIT_TXBF1_40M_8814B BIT(26)
+#define BIT_TXBF1_20M_8814B BIT(25)
+
+#define BIT_SHIFT_TXBF1_AID_8814B 16
+#define BIT_MASK_TXBF1_AID_8814B 0x1ff
+#define BIT_TXBF1_AID_8814B(x)                                                 \
+	(((x) & BIT_MASK_TXBF1_AID_8814B) << BIT_SHIFT_TXBF1_AID_8814B)
+#define BITS_TXBF1_AID_8814B                                                   \
+	(BIT_MASK_TXBF1_AID_8814B << BIT_SHIFT_TXBF1_AID_8814B)
+#define BIT_CLEAR_TXBF1_AID_8814B(x) ((x) & (~BITS_TXBF1_AID_8814B))
+#define BIT_GET_TXBF1_AID_8814B(x)                                             \
+	(((x) >> BIT_SHIFT_TXBF1_AID_8814B) & BIT_MASK_TXBF1_AID_8814B)
+#define BIT_SET_TXBF1_AID_8814B(x, v)                                          \
+	(BIT_CLEAR_TXBF1_AID_8814B(x) | BIT_TXBF1_AID_8814B(v))
+
+#define BIT_DIS_NDP_BFEN_8814B BIT(15)
+#define BIT_TXBCN_NOBLOCK_NDP_8814B BIT(14)
+#define BIT_TXBF0_80M_160M_8814B BIT(11)
+#define BIT_TXBF0_40M_8814B BIT(10)
+#define BIT_TXBF0_20M_8814B BIT(9)
+
+#define BIT_SHIFT_TXBF0_AID_8814B 0
+#define BIT_MASK_TXBF0_AID_8814B 0x1ff
+#define BIT_TXBF0_AID_8814B(x)                                                 \
+	(((x) & BIT_MASK_TXBF0_AID_8814B) << BIT_SHIFT_TXBF0_AID_8814B)
+#define BITS_TXBF0_AID_8814B                                                   \
+	(BIT_MASK_TXBF0_AID_8814B << BIT_SHIFT_TXBF0_AID_8814B)
+#define BIT_CLEAR_TXBF0_AID_8814B(x) ((x) & (~BITS_TXBF0_AID_8814B))
+#define BIT_GET_TXBF0_AID_8814B(x)                                             \
+	(((x) >> BIT_SHIFT_TXBF0_AID_8814B) & BIT_MASK_TXBF0_AID_8814B)
+#define BIT_SET_TXBF0_AID_8814B(x, v)                                          \
+	(BIT_CLEAR_TXBF0_AID_8814B(x) | BIT_TXBF0_AID_8814B(v))
+
+/* 2 REG_DARFRC_8814B */
+
+#define BIT_SHIFT_DARF_RC4_V1_8814B 24
+#define BIT_MASK_DARF_RC4_V1_8814B 0x3f
+#define BIT_DARF_RC4_V1_8814B(x)                                               \
+	(((x) & BIT_MASK_DARF_RC4_V1_8814B) << BIT_SHIFT_DARF_RC4_V1_8814B)
+#define BITS_DARF_RC4_V1_8814B                                                 \
+	(BIT_MASK_DARF_RC4_V1_8814B << BIT_SHIFT_DARF_RC4_V1_8814B)
+#define BIT_CLEAR_DARF_RC4_V1_8814B(x) ((x) & (~BITS_DARF_RC4_V1_8814B))
+#define BIT_GET_DARF_RC4_V1_8814B(x)                                           \
+	(((x) >> BIT_SHIFT_DARF_RC4_V1_8814B) & BIT_MASK_DARF_RC4_V1_8814B)
+#define BIT_SET_DARF_RC4_V1_8814B(x, v)                                        \
+	(BIT_CLEAR_DARF_RC4_V1_8814B(x) | BIT_DARF_RC4_V1_8814B(v))
+
+#define BIT_SHIFT_DARF_RC3_V1_8814B 16
+#define BIT_MASK_DARF_RC3_V1_8814B 0x3f
+#define BIT_DARF_RC3_V1_8814B(x)                                               \
+	(((x) & BIT_MASK_DARF_RC3_V1_8814B) << BIT_SHIFT_DARF_RC3_V1_8814B)
+#define BITS_DARF_RC3_V1_8814B                                                 \
+	(BIT_MASK_DARF_RC3_V1_8814B << BIT_SHIFT_DARF_RC3_V1_8814B)
+#define BIT_CLEAR_DARF_RC3_V1_8814B(x) ((x) & (~BITS_DARF_RC3_V1_8814B))
+#define BIT_GET_DARF_RC3_V1_8814B(x)                                           \
+	(((x) >> BIT_SHIFT_DARF_RC3_V1_8814B) & BIT_MASK_DARF_RC3_V1_8814B)
+#define BIT_SET_DARF_RC3_V1_8814B(x, v)                                        \
+	(BIT_CLEAR_DARF_RC3_V1_8814B(x) | BIT_DARF_RC3_V1_8814B(v))
+
+#define BIT_SHIFT_DARF_RC2_V1_8814B 8
+#define BIT_MASK_DARF_RC2_V1_8814B 0x3f
+#define BIT_DARF_RC2_V1_8814B(x)                                               \
+	(((x) & BIT_MASK_DARF_RC2_V1_8814B) << BIT_SHIFT_DARF_RC2_V1_8814B)
+#define BITS_DARF_RC2_V1_8814B                                                 \
+	(BIT_MASK_DARF_RC2_V1_8814B << BIT_SHIFT_DARF_RC2_V1_8814B)
+#define BIT_CLEAR_DARF_RC2_V1_8814B(x) ((x) & (~BITS_DARF_RC2_V1_8814B))
+#define BIT_GET_DARF_RC2_V1_8814B(x)                                           \
+	(((x) >> BIT_SHIFT_DARF_RC2_V1_8814B) & BIT_MASK_DARF_RC2_V1_8814B)
+#define BIT_SET_DARF_RC2_V1_8814B(x, v)                                        \
+	(BIT_CLEAR_DARF_RC2_V1_8814B(x) | BIT_DARF_RC2_V1_8814B(v))
+
+#define BIT_SHIFT_DARF_RC1_V1_8814B 0
+#define BIT_MASK_DARF_RC1_V1_8814B 0x3f
+#define BIT_DARF_RC1_V1_8814B(x)                                               \
+	(((x) & BIT_MASK_DARF_RC1_V1_8814B) << BIT_SHIFT_DARF_RC1_V1_8814B)
+#define BITS_DARF_RC1_V1_8814B                                                 \
+	(BIT_MASK_DARF_RC1_V1_8814B << BIT_SHIFT_DARF_RC1_V1_8814B)
+#define BIT_CLEAR_DARF_RC1_V1_8814B(x) ((x) & (~BITS_DARF_RC1_V1_8814B))
+#define BIT_GET_DARF_RC1_V1_8814B(x)                                           \
+	(((x) >> BIT_SHIFT_DARF_RC1_V1_8814B) & BIT_MASK_DARF_RC1_V1_8814B)
+#define BIT_SET_DARF_RC1_V1_8814B(x, v)                                        \
+	(BIT_CLEAR_DARF_RC1_V1_8814B(x) | BIT_DARF_RC1_V1_8814B(v))
+
+/* 2 REG_DARFRCH_8814B */
+
+#define BIT_SHIFT_DARF_RC8_V2_8814B 24
+#define BIT_MASK_DARF_RC8_V2_8814B 0x3f
+#define BIT_DARF_RC8_V2_8814B(x)                                               \
+	(((x) & BIT_MASK_DARF_RC8_V2_8814B) << BIT_SHIFT_DARF_RC8_V2_8814B)
+#define BITS_DARF_RC8_V2_8814B                                                 \
+	(BIT_MASK_DARF_RC8_V2_8814B << BIT_SHIFT_DARF_RC8_V2_8814B)
+#define BIT_CLEAR_DARF_RC8_V2_8814B(x) ((x) & (~BITS_DARF_RC8_V2_8814B))
+#define BIT_GET_DARF_RC8_V2_8814B(x)                                           \
+	(((x) >> BIT_SHIFT_DARF_RC8_V2_8814B) & BIT_MASK_DARF_RC8_V2_8814B)
+#define BIT_SET_DARF_RC8_V2_8814B(x, v)                                        \
+	(BIT_CLEAR_DARF_RC8_V2_8814B(x) | BIT_DARF_RC8_V2_8814B(v))
+
+#define BIT_SHIFT_DARF_RC7_V2_8814B 16
+#define BIT_MASK_DARF_RC7_V2_8814B 0x3f
+#define BIT_DARF_RC7_V2_8814B(x)                                               \
+	(((x) & BIT_MASK_DARF_RC7_V2_8814B) << BIT_SHIFT_DARF_RC7_V2_8814B)
+#define BITS_DARF_RC7_V2_8814B                                                 \
+	(BIT_MASK_DARF_RC7_V2_8814B << BIT_SHIFT_DARF_RC7_V2_8814B)
+#define BIT_CLEAR_DARF_RC7_V2_8814B(x) ((x) & (~BITS_DARF_RC7_V2_8814B))
+#define BIT_GET_DARF_RC7_V2_8814B(x)                                           \
+	(((x) >> BIT_SHIFT_DARF_RC7_V2_8814B) & BIT_MASK_DARF_RC7_V2_8814B)
+#define BIT_SET_DARF_RC7_V2_8814B(x, v)                                        \
+	(BIT_CLEAR_DARF_RC7_V2_8814B(x) | BIT_DARF_RC7_V2_8814B(v))
+
+#define BIT_SHIFT_DARF_RC6_V2_8814B 8
+#define BIT_MASK_DARF_RC6_V2_8814B 0x3f
+#define BIT_DARF_RC6_V2_8814B(x)                                               \
+	(((x) & BIT_MASK_DARF_RC6_V2_8814B) << BIT_SHIFT_DARF_RC6_V2_8814B)
+#define BITS_DARF_RC6_V2_8814B                                                 \
+	(BIT_MASK_DARF_RC6_V2_8814B << BIT_SHIFT_DARF_RC6_V2_8814B)
+#define BIT_CLEAR_DARF_RC6_V2_8814B(x) ((x) & (~BITS_DARF_RC6_V2_8814B))
+#define BIT_GET_DARF_RC6_V2_8814B(x)                                           \
+	(((x) >> BIT_SHIFT_DARF_RC6_V2_8814B) & BIT_MASK_DARF_RC6_V2_8814B)
+#define BIT_SET_DARF_RC6_V2_8814B(x, v)                                        \
+	(BIT_CLEAR_DARF_RC6_V2_8814B(x) | BIT_DARF_RC6_V2_8814B(v))
+
+#define BIT_SHIFT_DARF_RC5_V2_8814B 0
+#define BIT_MASK_DARF_RC5_V2_8814B 0x3f
+#define BIT_DARF_RC5_V2_8814B(x)                                               \
+	(((x) & BIT_MASK_DARF_RC5_V2_8814B) << BIT_SHIFT_DARF_RC5_V2_8814B)
+#define BITS_DARF_RC5_V2_8814B                                                 \
+	(BIT_MASK_DARF_RC5_V2_8814B << BIT_SHIFT_DARF_RC5_V2_8814B)
+#define BIT_CLEAR_DARF_RC5_V2_8814B(x) ((x) & (~BITS_DARF_RC5_V2_8814B))
+#define BIT_GET_DARF_RC5_V2_8814B(x)                                           \
+	(((x) >> BIT_SHIFT_DARF_RC5_V2_8814B) & BIT_MASK_DARF_RC5_V2_8814B)
+#define BIT_SET_DARF_RC5_V2_8814B(x, v)                                        \
+	(BIT_CLEAR_DARF_RC5_V2_8814B(x) | BIT_DARF_RC5_V2_8814B(v))
+
+/* 2 REG_RARFRC_8814B */
+
+#define BIT_SHIFT_RARF_RC4_8814B 24
+#define BIT_MASK_RARF_RC4_8814B 0x1f
+#define BIT_RARF_RC4_8814B(x)                                                  \
+	(((x) & BIT_MASK_RARF_RC4_8814B) << BIT_SHIFT_RARF_RC4_8814B)
+#define BITS_RARF_RC4_8814B                                                    \
+	(BIT_MASK_RARF_RC4_8814B << BIT_SHIFT_RARF_RC4_8814B)
+#define BIT_CLEAR_RARF_RC4_8814B(x) ((x) & (~BITS_RARF_RC4_8814B))
+#define BIT_GET_RARF_RC4_8814B(x)                                              \
+	(((x) >> BIT_SHIFT_RARF_RC4_8814B) & BIT_MASK_RARF_RC4_8814B)
+#define BIT_SET_RARF_RC4_8814B(x, v)                                           \
+	(BIT_CLEAR_RARF_RC4_8814B(x) | BIT_RARF_RC4_8814B(v))
+
+#define BIT_SHIFT_RARF_RC3_8814B 16
+#define BIT_MASK_RARF_RC3_8814B 0x1f
+#define BIT_RARF_RC3_8814B(x)                                                  \
+	(((x) & BIT_MASK_RARF_RC3_8814B) << BIT_SHIFT_RARF_RC3_8814B)
+#define BITS_RARF_RC3_8814B                                                    \
+	(BIT_MASK_RARF_RC3_8814B << BIT_SHIFT_RARF_RC3_8814B)
+#define BIT_CLEAR_RARF_RC3_8814B(x) ((x) & (~BITS_RARF_RC3_8814B))
+#define BIT_GET_RARF_RC3_8814B(x)                                              \
+	(((x) >> BIT_SHIFT_RARF_RC3_8814B) & BIT_MASK_RARF_RC3_8814B)
+#define BIT_SET_RARF_RC3_8814B(x, v)                                           \
+	(BIT_CLEAR_RARF_RC3_8814B(x) | BIT_RARF_RC3_8814B(v))
+
+#define BIT_SHIFT_RARF_RC2_8814B 8
+#define BIT_MASK_RARF_RC2_8814B 0x1f
+#define BIT_RARF_RC2_8814B(x)                                                  \
+	(((x) & BIT_MASK_RARF_RC2_8814B) << BIT_SHIFT_RARF_RC2_8814B)
+#define BITS_RARF_RC2_8814B                                                    \
+	(BIT_MASK_RARF_RC2_8814B << BIT_SHIFT_RARF_RC2_8814B)
+#define BIT_CLEAR_RARF_RC2_8814B(x) ((x) & (~BITS_RARF_RC2_8814B))
+#define BIT_GET_RARF_RC2_8814B(x)                                              \
+	(((x) >> BIT_SHIFT_RARF_RC2_8814B) & BIT_MASK_RARF_RC2_8814B)
+#define BIT_SET_RARF_RC2_8814B(x, v)                                           \
+	(BIT_CLEAR_RARF_RC2_8814B(x) | BIT_RARF_RC2_8814B(v))
+
+#define BIT_SHIFT_RARF_RC1_8814B 0
+#define BIT_MASK_RARF_RC1_8814B 0x1f
+#define BIT_RARF_RC1_8814B(x)                                                  \
+	(((x) & BIT_MASK_RARF_RC1_8814B) << BIT_SHIFT_RARF_RC1_8814B)
+#define BITS_RARF_RC1_8814B                                                    \
+	(BIT_MASK_RARF_RC1_8814B << BIT_SHIFT_RARF_RC1_8814B)
+#define BIT_CLEAR_RARF_RC1_8814B(x) ((x) & (~BITS_RARF_RC1_8814B))
+#define BIT_GET_RARF_RC1_8814B(x)                                              \
+	(((x) >> BIT_SHIFT_RARF_RC1_8814B) & BIT_MASK_RARF_RC1_8814B)
+#define BIT_SET_RARF_RC1_8814B(x, v)                                           \
+	(BIT_CLEAR_RARF_RC1_8814B(x) | BIT_RARF_RC1_8814B(v))
+
+/* 2 REG_RARFRCH_8814B */
+
+#define BIT_SHIFT_RARF_RC8_V1_8814B 24
+#define BIT_MASK_RARF_RC8_V1_8814B 0x1f
+#define BIT_RARF_RC8_V1_8814B(x)                                               \
+	(((x) & BIT_MASK_RARF_RC8_V1_8814B) << BIT_SHIFT_RARF_RC8_V1_8814B)
+#define BITS_RARF_RC8_V1_8814B                                                 \
+	(BIT_MASK_RARF_RC8_V1_8814B << BIT_SHIFT_RARF_RC8_V1_8814B)
+#define BIT_CLEAR_RARF_RC8_V1_8814B(x) ((x) & (~BITS_RARF_RC8_V1_8814B))
+#define BIT_GET_RARF_RC8_V1_8814B(x)                                           \
+	(((x) >> BIT_SHIFT_RARF_RC8_V1_8814B) & BIT_MASK_RARF_RC8_V1_8814B)
+#define BIT_SET_RARF_RC8_V1_8814B(x, v)                                        \
+	(BIT_CLEAR_RARF_RC8_V1_8814B(x) | BIT_RARF_RC8_V1_8814B(v))
+
+#define BIT_SHIFT_RARF_RC7_V1_8814B 16
+#define BIT_MASK_RARF_RC7_V1_8814B 0x1f
+#define BIT_RARF_RC7_V1_8814B(x)                                               \
+	(((x) & BIT_MASK_RARF_RC7_V1_8814B) << BIT_SHIFT_RARF_RC7_V1_8814B)
+#define BITS_RARF_RC7_V1_8814B                                                 \
+	(BIT_MASK_RARF_RC7_V1_8814B << BIT_SHIFT_RARF_RC7_V1_8814B)
+#define BIT_CLEAR_RARF_RC7_V1_8814B(x) ((x) & (~BITS_RARF_RC7_V1_8814B))
+#define BIT_GET_RARF_RC7_V1_8814B(x)                                           \
+	(((x) >> BIT_SHIFT_RARF_RC7_V1_8814B) & BIT_MASK_RARF_RC7_V1_8814B)
+#define BIT_SET_RARF_RC7_V1_8814B(x, v)                                        \
+	(BIT_CLEAR_RARF_RC7_V1_8814B(x) | BIT_RARF_RC7_V1_8814B(v))
+
+#define BIT_SHIFT_RARF_RC6_V1_8814B 8
+#define BIT_MASK_RARF_RC6_V1_8814B 0x1f
+#define BIT_RARF_RC6_V1_8814B(x)                                               \
+	(((x) & BIT_MASK_RARF_RC6_V1_8814B) << BIT_SHIFT_RARF_RC6_V1_8814B)
+#define BITS_RARF_RC6_V1_8814B                                                 \
+	(BIT_MASK_RARF_RC6_V1_8814B << BIT_SHIFT_RARF_RC6_V1_8814B)
+#define BIT_CLEAR_RARF_RC6_V1_8814B(x) ((x) & (~BITS_RARF_RC6_V1_8814B))
+#define BIT_GET_RARF_RC6_V1_8814B(x)                                           \
+	(((x) >> BIT_SHIFT_RARF_RC6_V1_8814B) & BIT_MASK_RARF_RC6_V1_8814B)
+#define BIT_SET_RARF_RC6_V1_8814B(x, v)                                        \
+	(BIT_CLEAR_RARF_RC6_V1_8814B(x) | BIT_RARF_RC6_V1_8814B(v))
+
+#define BIT_SHIFT_RARF_RC5_V1_8814B 0
+#define BIT_MASK_RARF_RC5_V1_8814B 0x1f
+#define BIT_RARF_RC5_V1_8814B(x)                                               \
+	(((x) & BIT_MASK_RARF_RC5_V1_8814B) << BIT_SHIFT_RARF_RC5_V1_8814B)
+#define BITS_RARF_RC5_V1_8814B                                                 \
+	(BIT_MASK_RARF_RC5_V1_8814B << BIT_SHIFT_RARF_RC5_V1_8814B)
+#define BIT_CLEAR_RARF_RC5_V1_8814B(x) ((x) & (~BITS_RARF_RC5_V1_8814B))
+#define BIT_GET_RARF_RC5_V1_8814B(x)                                           \
+	(((x) >> BIT_SHIFT_RARF_RC5_V1_8814B) & BIT_MASK_RARF_RC5_V1_8814B)
+#define BIT_SET_RARF_RC5_V1_8814B(x, v)                                        \
+	(BIT_CLEAR_RARF_RC5_V1_8814B(x) | BIT_RARF_RC5_V1_8814B(v))
+
+/* 2 REG_RRSR_8814B */
+
+#define BIT_SHIFT_RRSR_RSC_8814B 21
+#define BIT_MASK_RRSR_RSC_8814B 0x3
+#define BIT_RRSR_RSC_8814B(x)                                                  \
+	(((x) & BIT_MASK_RRSR_RSC_8814B) << BIT_SHIFT_RRSR_RSC_8814B)
+#define BITS_RRSR_RSC_8814B                                                    \
+	(BIT_MASK_RRSR_RSC_8814B << BIT_SHIFT_RRSR_RSC_8814B)
+#define BIT_CLEAR_RRSR_RSC_8814B(x) ((x) & (~BITS_RRSR_RSC_8814B))
+#define BIT_GET_RRSR_RSC_8814B(x)                                              \
+	(((x) >> BIT_SHIFT_RRSR_RSC_8814B) & BIT_MASK_RRSR_RSC_8814B)
+#define BIT_SET_RRSR_RSC_8814B(x, v)                                           \
+	(BIT_CLEAR_RRSR_RSC_8814B(x) | BIT_RRSR_RSC_8814B(v))
+
+#define BIT_SHIFT_RRSC_BITMAP_8814B 0
+#define BIT_MASK_RRSC_BITMAP_8814B 0xfffff
+#define BIT_RRSC_BITMAP_8814B(x)                                               \
+	(((x) & BIT_MASK_RRSC_BITMAP_8814B) << BIT_SHIFT_RRSC_BITMAP_8814B)
+#define BITS_RRSC_BITMAP_8814B                                                 \
+	(BIT_MASK_RRSC_BITMAP_8814B << BIT_SHIFT_RRSC_BITMAP_8814B)
+#define BIT_CLEAR_RRSC_BITMAP_8814B(x) ((x) & (~BITS_RRSC_BITMAP_8814B))
+#define BIT_GET_RRSC_BITMAP_8814B(x)                                           \
+	(((x) >> BIT_SHIFT_RRSC_BITMAP_8814B) & BIT_MASK_RRSC_BITMAP_8814B)
+#define BIT_SET_RRSC_BITMAP_8814B(x, v)                                        \
+	(BIT_CLEAR_RRSC_BITMAP_8814B(x) | BIT_RRSC_BITMAP_8814B(v))
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_ARFR0_8814B */
+
+#define BIT_SHIFT_ARFRL0_8814B 0
+#define BIT_MASK_ARFRL0_8814B 0xffffffffL
+#define BIT_ARFRL0_8814B(x)                                                    \
+	(((x) & BIT_MASK_ARFRL0_8814B) << BIT_SHIFT_ARFRL0_8814B)
+#define BITS_ARFRL0_8814B (BIT_MASK_ARFRL0_8814B << BIT_SHIFT_ARFRL0_8814B)
+#define BIT_CLEAR_ARFRL0_8814B(x) ((x) & (~BITS_ARFRL0_8814B))
+#define BIT_GET_ARFRL0_8814B(x)                                                \
+	(((x) >> BIT_SHIFT_ARFRL0_8814B) & BIT_MASK_ARFRL0_8814B)
+#define BIT_SET_ARFRL0_8814B(x, v)                                             \
+	(BIT_CLEAR_ARFRL0_8814B(x) | BIT_ARFRL0_8814B(v))
+
+/* 2 REG_ARFRH0_8814B */
+
+#define BIT_SHIFT_ARFRH0_8814B 0
+#define BIT_MASK_ARFRH0_8814B 0xffffffffL
+#define BIT_ARFRH0_8814B(x)                                                    \
+	(((x) & BIT_MASK_ARFRH0_8814B) << BIT_SHIFT_ARFRH0_8814B)
+#define BITS_ARFRH0_8814B (BIT_MASK_ARFRH0_8814B << BIT_SHIFT_ARFRH0_8814B)
+#define BIT_CLEAR_ARFRH0_8814B(x) ((x) & (~BITS_ARFRH0_8814B))
+#define BIT_GET_ARFRH0_8814B(x)                                                \
+	(((x) >> BIT_SHIFT_ARFRH0_8814B) & BIT_MASK_ARFRH0_8814B)
+#define BIT_SET_ARFRH0_8814B(x, v)                                             \
+	(BIT_CLEAR_ARFRH0_8814B(x) | BIT_ARFRH0_8814B(v))
+
+/* 2 REG_REG_ARFR_WT0_8814B */
+
+#define BIT_SHIFT_RATE7_WEIGHTING_8814B 28
+#define BIT_MASK_RATE7_WEIGHTING_8814B 0xf
+#define BIT_RATE7_WEIGHTING_8814B(x)                                           \
+	(((x) & BIT_MASK_RATE7_WEIGHTING_8814B)                                \
+	 << BIT_SHIFT_RATE7_WEIGHTING_8814B)
+#define BITS_RATE7_WEIGHTING_8814B                                             \
+	(BIT_MASK_RATE7_WEIGHTING_8814B << BIT_SHIFT_RATE7_WEIGHTING_8814B)
+#define BIT_CLEAR_RATE7_WEIGHTING_8814B(x) ((x) & (~BITS_RATE7_WEIGHTING_8814B))
+#define BIT_GET_RATE7_WEIGHTING_8814B(x)                                       \
+	(((x) >> BIT_SHIFT_RATE7_WEIGHTING_8814B) &                            \
+	 BIT_MASK_RATE7_WEIGHTING_8814B)
+#define BIT_SET_RATE7_WEIGHTING_8814B(x, v)                                    \
+	(BIT_CLEAR_RATE7_WEIGHTING_8814B(x) | BIT_RATE7_WEIGHTING_8814B(v))
+
+#define BIT_SHIFT_RATE6_WEIGHTING_8814B 24
+#define BIT_MASK_RATE6_WEIGHTING_8814B 0xf
+#define BIT_RATE6_WEIGHTING_8814B(x)                                           \
+	(((x) & BIT_MASK_RATE6_WEIGHTING_8814B)                                \
+	 << BIT_SHIFT_RATE6_WEIGHTING_8814B)
+#define BITS_RATE6_WEIGHTING_8814B                                             \
+	(BIT_MASK_RATE6_WEIGHTING_8814B << BIT_SHIFT_RATE6_WEIGHTING_8814B)
+#define BIT_CLEAR_RATE6_WEIGHTING_8814B(x) ((x) & (~BITS_RATE6_WEIGHTING_8814B))
+#define BIT_GET_RATE6_WEIGHTING_8814B(x)                                       \
+	(((x) >> BIT_SHIFT_RATE6_WEIGHTING_8814B) &                            \
+	 BIT_MASK_RATE6_WEIGHTING_8814B)
+#define BIT_SET_RATE6_WEIGHTING_8814B(x, v)                                    \
+	(BIT_CLEAR_RATE6_WEIGHTING_8814B(x) | BIT_RATE6_WEIGHTING_8814B(v))
+
+#define BIT_SHIFT_RATE5_WEIGHTING_8814B 20
+#define BIT_MASK_RATE5_WEIGHTING_8814B 0xf
+#define BIT_RATE5_WEIGHTING_8814B(x)                                           \
+	(((x) & BIT_MASK_RATE5_WEIGHTING_8814B)                                \
+	 << BIT_SHIFT_RATE5_WEIGHTING_8814B)
+#define BITS_RATE5_WEIGHTING_8814B                                             \
+	(BIT_MASK_RATE5_WEIGHTING_8814B << BIT_SHIFT_RATE5_WEIGHTING_8814B)
+#define BIT_CLEAR_RATE5_WEIGHTING_8814B(x) ((x) & (~BITS_RATE5_WEIGHTING_8814B))
+#define BIT_GET_RATE5_WEIGHTING_8814B(x)                                       \
+	(((x) >> BIT_SHIFT_RATE5_WEIGHTING_8814B) &                            \
+	 BIT_MASK_RATE5_WEIGHTING_8814B)
+#define BIT_SET_RATE5_WEIGHTING_8814B(x, v)                                    \
+	(BIT_CLEAR_RATE5_WEIGHTING_8814B(x) | BIT_RATE5_WEIGHTING_8814B(v))
+
+#define BIT_SHIFT_RATE4_WEIGHTING_8814B 16
+#define BIT_MASK_RATE4_WEIGHTING_8814B 0xf
+#define BIT_RATE4_WEIGHTING_8814B(x)                                           \
+	(((x) & BIT_MASK_RATE4_WEIGHTING_8814B)                                \
+	 << BIT_SHIFT_RATE4_WEIGHTING_8814B)
+#define BITS_RATE4_WEIGHTING_8814B                                             \
+	(BIT_MASK_RATE4_WEIGHTING_8814B << BIT_SHIFT_RATE4_WEIGHTING_8814B)
+#define BIT_CLEAR_RATE4_WEIGHTING_8814B(x) ((x) & (~BITS_RATE4_WEIGHTING_8814B))
+#define BIT_GET_RATE4_WEIGHTING_8814B(x)                                       \
+	(((x) >> BIT_SHIFT_RATE4_WEIGHTING_8814B) &                            \
+	 BIT_MASK_RATE4_WEIGHTING_8814B)
+#define BIT_SET_RATE4_WEIGHTING_8814B(x, v)                                    \
+	(BIT_CLEAR_RATE4_WEIGHTING_8814B(x) | BIT_RATE4_WEIGHTING_8814B(v))
+
+#define BIT_SHIFT_RATE3_WEIGHTING_8814B 12
+#define BIT_MASK_RATE3_WEIGHTING_8814B 0xf
+#define BIT_RATE3_WEIGHTING_8814B(x)                                           \
+	(((x) & BIT_MASK_RATE3_WEIGHTING_8814B)                                \
+	 << BIT_SHIFT_RATE3_WEIGHTING_8814B)
+#define BITS_RATE3_WEIGHTING_8814B                                             \
+	(BIT_MASK_RATE3_WEIGHTING_8814B << BIT_SHIFT_RATE3_WEIGHTING_8814B)
+#define BIT_CLEAR_RATE3_WEIGHTING_8814B(x) ((x) & (~BITS_RATE3_WEIGHTING_8814B))
+#define BIT_GET_RATE3_WEIGHTING_8814B(x)                                       \
+	(((x) >> BIT_SHIFT_RATE3_WEIGHTING_8814B) &                            \
+	 BIT_MASK_RATE3_WEIGHTING_8814B)
+#define BIT_SET_RATE3_WEIGHTING_8814B(x, v)                                    \
+	(BIT_CLEAR_RATE3_WEIGHTING_8814B(x) | BIT_RATE3_WEIGHTING_8814B(v))
+
+#define BIT_SHIFT_RATE2_WEIGHTING_8814B 8
+#define BIT_MASK_RATE2_WEIGHTING_8814B 0xf
+#define BIT_RATE2_WEIGHTING_8814B(x)                                           \
+	(((x) & BIT_MASK_RATE2_WEIGHTING_8814B)                                \
+	 << BIT_SHIFT_RATE2_WEIGHTING_8814B)
+#define BITS_RATE2_WEIGHTING_8814B                                             \
+	(BIT_MASK_RATE2_WEIGHTING_8814B << BIT_SHIFT_RATE2_WEIGHTING_8814B)
+#define BIT_CLEAR_RATE2_WEIGHTING_8814B(x) ((x) & (~BITS_RATE2_WEIGHTING_8814B))
+#define BIT_GET_RATE2_WEIGHTING_8814B(x)                                       \
+	(((x) >> BIT_SHIFT_RATE2_WEIGHTING_8814B) &                            \
+	 BIT_MASK_RATE2_WEIGHTING_8814B)
+#define BIT_SET_RATE2_WEIGHTING_8814B(x, v)                                    \
+	(BIT_CLEAR_RATE2_WEIGHTING_8814B(x) | BIT_RATE2_WEIGHTING_8814B(v))
+
+#define BIT_SHIFT_RATE1_WEIGHTING_8814B 4
+#define BIT_MASK_RATE1_WEIGHTING_8814B 0xf
+#define BIT_RATE1_WEIGHTING_8814B(x)                                           \
+	(((x) & BIT_MASK_RATE1_WEIGHTING_8814B)                                \
+	 << BIT_SHIFT_RATE1_WEIGHTING_8814B)
+#define BITS_RATE1_WEIGHTING_8814B                                             \
+	(BIT_MASK_RATE1_WEIGHTING_8814B << BIT_SHIFT_RATE1_WEIGHTING_8814B)
+#define BIT_CLEAR_RATE1_WEIGHTING_8814B(x) ((x) & (~BITS_RATE1_WEIGHTING_8814B))
+#define BIT_GET_RATE1_WEIGHTING_8814B(x)                                       \
+	(((x) >> BIT_SHIFT_RATE1_WEIGHTING_8814B) &                            \
+	 BIT_MASK_RATE1_WEIGHTING_8814B)
+#define BIT_SET_RATE1_WEIGHTING_8814B(x, v)                                    \
+	(BIT_CLEAR_RATE1_WEIGHTING_8814B(x) | BIT_RATE1_WEIGHTING_8814B(v))
+
+#define BIT_SHIFT_RATE0_WEIGHTING_8814B 0
+#define BIT_MASK_RATE0_WEIGHTING_8814B 0xf
+#define BIT_RATE0_WEIGHTING_8814B(x)                                           \
+	(((x) & BIT_MASK_RATE0_WEIGHTING_8814B)                                \
+	 << BIT_SHIFT_RATE0_WEIGHTING_8814B)
+#define BITS_RATE0_WEIGHTING_8814B                                             \
+	(BIT_MASK_RATE0_WEIGHTING_8814B << BIT_SHIFT_RATE0_WEIGHTING_8814B)
+#define BIT_CLEAR_RATE0_WEIGHTING_8814B(x) ((x) & (~BITS_RATE0_WEIGHTING_8814B))
+#define BIT_GET_RATE0_WEIGHTING_8814B(x)                                       \
+	(((x) >> BIT_SHIFT_RATE0_WEIGHTING_8814B) &                            \
+	 BIT_MASK_RATE0_WEIGHTING_8814B)
+#define BIT_SET_RATE0_WEIGHTING_8814B(x, v)                                    \
+	(BIT_CLEAR_RATE0_WEIGHTING_8814B(x) | BIT_RATE0_WEIGHTING_8814B(v))
+
+/* 2 REG_REG_ARFR_WT1_8814B */
+
+#define BIT_SHIFT_RATE15_WEIGHTING_8814B 28
+#define BIT_MASK_RATE15_WEIGHTING_8814B 0xf
+#define BIT_RATE15_WEIGHTING_8814B(x)                                          \
+	(((x) & BIT_MASK_RATE15_WEIGHTING_8814B)                               \
+	 << BIT_SHIFT_RATE15_WEIGHTING_8814B)
+#define BITS_RATE15_WEIGHTING_8814B                                            \
+	(BIT_MASK_RATE15_WEIGHTING_8814B << BIT_SHIFT_RATE15_WEIGHTING_8814B)
+#define BIT_CLEAR_RATE15_WEIGHTING_8814B(x)                                    \
+	((x) & (~BITS_RATE15_WEIGHTING_8814B))
+#define BIT_GET_RATE15_WEIGHTING_8814B(x)                                      \
+	(((x) >> BIT_SHIFT_RATE15_WEIGHTING_8814B) &                           \
+	 BIT_MASK_RATE15_WEIGHTING_8814B)
+#define BIT_SET_RATE15_WEIGHTING_8814B(x, v)                                   \
+	(BIT_CLEAR_RATE15_WEIGHTING_8814B(x) | BIT_RATE15_WEIGHTING_8814B(v))
+
+#define BIT_SHIFT_RATE14_WEIGHTING_8814B 24
+#define BIT_MASK_RATE14_WEIGHTING_8814B 0xf
+#define BIT_RATE14_WEIGHTING_8814B(x)                                          \
+	(((x) & BIT_MASK_RATE14_WEIGHTING_8814B)                               \
+	 << BIT_SHIFT_RATE14_WEIGHTING_8814B)
+#define BITS_RATE14_WEIGHTING_8814B                                            \
+	(BIT_MASK_RATE14_WEIGHTING_8814B << BIT_SHIFT_RATE14_WEIGHTING_8814B)
+#define BIT_CLEAR_RATE14_WEIGHTING_8814B(x)                                    \
+	((x) & (~BITS_RATE14_WEIGHTING_8814B))
+#define BIT_GET_RATE14_WEIGHTING_8814B(x)                                      \
+	(((x) >> BIT_SHIFT_RATE14_WEIGHTING_8814B) &                           \
+	 BIT_MASK_RATE14_WEIGHTING_8814B)
+#define BIT_SET_RATE14_WEIGHTING_8814B(x, v)                                   \
+	(BIT_CLEAR_RATE14_WEIGHTING_8814B(x) | BIT_RATE14_WEIGHTING_8814B(v))
+
+#define BIT_SHIFT_RATE13_WEIGHTING_8814B 20
+#define BIT_MASK_RATE13_WEIGHTING_8814B 0xf
+#define BIT_RATE13_WEIGHTING_8814B(x)                                          \
+	(((x) & BIT_MASK_RATE13_WEIGHTING_8814B)                               \
+	 << BIT_SHIFT_RATE13_WEIGHTING_8814B)
+#define BITS_RATE13_WEIGHTING_8814B                                            \
+	(BIT_MASK_RATE13_WEIGHTING_8814B << BIT_SHIFT_RATE13_WEIGHTING_8814B)
+#define BIT_CLEAR_RATE13_WEIGHTING_8814B(x)                                    \
+	((x) & (~BITS_RATE13_WEIGHTING_8814B))
+#define BIT_GET_RATE13_WEIGHTING_8814B(x)                                      \
+	(((x) >> BIT_SHIFT_RATE13_WEIGHTING_8814B) &                           \
+	 BIT_MASK_RATE13_WEIGHTING_8814B)
+#define BIT_SET_RATE13_WEIGHTING_8814B(x, v)                                   \
+	(BIT_CLEAR_RATE13_WEIGHTING_8814B(x) | BIT_RATE13_WEIGHTING_8814B(v))
+
+#define BIT_SHIFT_RATE12_WEIGHTING_8814B 16
+#define BIT_MASK_RATE12_WEIGHTING_8814B 0xf
+#define BIT_RATE12_WEIGHTING_8814B(x)                                          \
+	(((x) & BIT_MASK_RATE12_WEIGHTING_8814B)                               \
+	 << BIT_SHIFT_RATE12_WEIGHTING_8814B)
+#define BITS_RATE12_WEIGHTING_8814B                                            \
+	(BIT_MASK_RATE12_WEIGHTING_8814B << BIT_SHIFT_RATE12_WEIGHTING_8814B)
+#define BIT_CLEAR_RATE12_WEIGHTING_8814B(x)                                    \
+	((x) & (~BITS_RATE12_WEIGHTING_8814B))
+#define BIT_GET_RATE12_WEIGHTING_8814B(x)                                      \
+	(((x) >> BIT_SHIFT_RATE12_WEIGHTING_8814B) &                           \
+	 BIT_MASK_RATE12_WEIGHTING_8814B)
+#define BIT_SET_RATE12_WEIGHTING_8814B(x, v)                                   \
+	(BIT_CLEAR_RATE12_WEIGHTING_8814B(x) | BIT_RATE12_WEIGHTING_8814B(v))
+
+#define BIT_SHIFT_RATE11_WEIGHTING_8814B 12
+#define BIT_MASK_RATE11_WEIGHTING_8814B 0xf
+#define BIT_RATE11_WEIGHTING_8814B(x)                                          \
+	(((x) & BIT_MASK_RATE11_WEIGHTING_8814B)                               \
+	 << BIT_SHIFT_RATE11_WEIGHTING_8814B)
+#define BITS_RATE11_WEIGHTING_8814B                                            \
+	(BIT_MASK_RATE11_WEIGHTING_8814B << BIT_SHIFT_RATE11_WEIGHTING_8814B)
+#define BIT_CLEAR_RATE11_WEIGHTING_8814B(x)                                    \
+	((x) & (~BITS_RATE11_WEIGHTING_8814B))
+#define BIT_GET_RATE11_WEIGHTING_8814B(x)                                      \
+	(((x) >> BIT_SHIFT_RATE11_WEIGHTING_8814B) &                           \
+	 BIT_MASK_RATE11_WEIGHTING_8814B)
+#define BIT_SET_RATE11_WEIGHTING_8814B(x, v)                                   \
+	(BIT_CLEAR_RATE11_WEIGHTING_8814B(x) | BIT_RATE11_WEIGHTING_8814B(v))
+
+#define BIT_SHIFT_RATE10_WEIGHTING_8814B 8
+#define BIT_MASK_RATE10_WEIGHTING_8814B 0xf
+#define BIT_RATE10_WEIGHTING_8814B(x)                                          \
+	(((x) & BIT_MASK_RATE10_WEIGHTING_8814B)                               \
+	 << BIT_SHIFT_RATE10_WEIGHTING_8814B)
+#define BITS_RATE10_WEIGHTING_8814B                                            \
+	(BIT_MASK_RATE10_WEIGHTING_8814B << BIT_SHIFT_RATE10_WEIGHTING_8814B)
+#define BIT_CLEAR_RATE10_WEIGHTING_8814B(x)                                    \
+	((x) & (~BITS_RATE10_WEIGHTING_8814B))
+#define BIT_GET_RATE10_WEIGHTING_8814B(x)                                      \
+	(((x) >> BIT_SHIFT_RATE10_WEIGHTING_8814B) &                           \
+	 BIT_MASK_RATE10_WEIGHTING_8814B)
+#define BIT_SET_RATE10_WEIGHTING_8814B(x, v)                                   \
+	(BIT_CLEAR_RATE10_WEIGHTING_8814B(x) | BIT_RATE10_WEIGHTING_8814B(v))
+
+#define BIT_SHIFT_RATE9_WEIGHTING_8814B 4
+#define BIT_MASK_RATE9_WEIGHTING_8814B 0xf
+#define BIT_RATE9_WEIGHTING_8814B(x)                                           \
+	(((x) & BIT_MASK_RATE9_WEIGHTING_8814B)                                \
+	 << BIT_SHIFT_RATE9_WEIGHTING_8814B)
+#define BITS_RATE9_WEIGHTING_8814B                                             \
+	(BIT_MASK_RATE9_WEIGHTING_8814B << BIT_SHIFT_RATE9_WEIGHTING_8814B)
+#define BIT_CLEAR_RATE9_WEIGHTING_8814B(x) ((x) & (~BITS_RATE9_WEIGHTING_8814B))
+#define BIT_GET_RATE9_WEIGHTING_8814B(x)                                       \
+	(((x) >> BIT_SHIFT_RATE9_WEIGHTING_8814B) &                            \
+	 BIT_MASK_RATE9_WEIGHTING_8814B)
+#define BIT_SET_RATE9_WEIGHTING_8814B(x, v)                                    \
+	(BIT_CLEAR_RATE9_WEIGHTING_8814B(x) | BIT_RATE9_WEIGHTING_8814B(v))
+
+#define BIT_SHIFT_RATE8_WEIGHTING_8814B 0
+#define BIT_MASK_RATE8_WEIGHTING_8814B 0xf
+#define BIT_RATE8_WEIGHTING_8814B(x)                                           \
+	(((x) & BIT_MASK_RATE8_WEIGHTING_8814B)                                \
+	 << BIT_SHIFT_RATE8_WEIGHTING_8814B)
+#define BITS_RATE8_WEIGHTING_8814B                                             \
+	(BIT_MASK_RATE8_WEIGHTING_8814B << BIT_SHIFT_RATE8_WEIGHTING_8814B)
+#define BIT_CLEAR_RATE8_WEIGHTING_8814B(x) ((x) & (~BITS_RATE8_WEIGHTING_8814B))
+#define BIT_GET_RATE8_WEIGHTING_8814B(x)                                       \
+	(((x) >> BIT_SHIFT_RATE8_WEIGHTING_8814B) &                            \
+	 BIT_MASK_RATE8_WEIGHTING_8814B)
+#define BIT_SET_RATE8_WEIGHTING_8814B(x, v)                                    \
+	(BIT_CLEAR_RATE8_WEIGHTING_8814B(x) | BIT_RATE8_WEIGHTING_8814B(v))
+
+/* 2 REG_CCK_CHECK_8814B */
+#define BIT_CHECK_CCK_EN_8814B BIT(7)
+#define BIT_EN_BCN_PKT_REL_P0_8814B BIT(6)
+#define BIT_BCN_PORT_SEL_8814B BIT(5)
+#define BIT_MOREDATA_BYPASS_8814B BIT(4)
+#define BIT_EN_CLR_CMD_REL_BCN_PKT_P0_8814B BIT(3)
+#define BIT_EN_SET_MOREDATA_8814B BIT(2)
+#define BIT__R_DIS_CLEAR_MACID_RELEASE_8814B BIT(1)
+#define BIT__R_MACID_RELEASE_EN_8814B BIT(0)
+
+/* 2 REG_AMPDU_MAX_TIME_V1_8814B */
+
+#define BIT_SHIFT_AMPDU_MAX_TIME_8814B 0
+#define BIT_MASK_AMPDU_MAX_TIME_8814B 0xff
+#define BIT_AMPDU_MAX_TIME_8814B(x)                                            \
+	(((x) & BIT_MASK_AMPDU_MAX_TIME_8814B)                                 \
+	 << BIT_SHIFT_AMPDU_MAX_TIME_8814B)
+#define BITS_AMPDU_MAX_TIME_8814B                                              \
+	(BIT_MASK_AMPDU_MAX_TIME_8814B << BIT_SHIFT_AMPDU_MAX_TIME_8814B)
+#define BIT_CLEAR_AMPDU_MAX_TIME_8814B(x) ((x) & (~BITS_AMPDU_MAX_TIME_8814B))
+#define BIT_GET_AMPDU_MAX_TIME_8814B(x)                                        \
+	(((x) >> BIT_SHIFT_AMPDU_MAX_TIME_8814B) &                             \
+	 BIT_MASK_AMPDU_MAX_TIME_8814B)
+#define BIT_SET_AMPDU_MAX_TIME_8814B(x, v)                                     \
+	(BIT_CLEAR_AMPDU_MAX_TIME_8814B(x) | BIT_AMPDU_MAX_TIME_8814B(v))
+
+/* 2 REG_TAB_SEL_8814B */
+
+#define BIT_SHIFT_RATE_SEL_8814B 0
+#define BIT_MASK_RATE_SEL_8814B 0xf
+#define BIT_RATE_SEL_8814B(x)                                                  \
+	(((x) & BIT_MASK_RATE_SEL_8814B) << BIT_SHIFT_RATE_SEL_8814B)
+#define BITS_RATE_SEL_8814B                                                    \
+	(BIT_MASK_RATE_SEL_8814B << BIT_SHIFT_RATE_SEL_8814B)
+#define BIT_CLEAR_RATE_SEL_8814B(x) ((x) & (~BITS_RATE_SEL_8814B))
+#define BIT_GET_RATE_SEL_8814B(x)                                              \
+	(((x) >> BIT_SHIFT_RATE_SEL_8814B) & BIT_MASK_RATE_SEL_8814B)
+#define BIT_SET_RATE_SEL_8814B(x, v)                                           \
+	(BIT_CLEAR_RATE_SEL_8814B(x) | BIT_RATE_SEL_8814B(v))
+
+/* 2 REG_BCN_INVALID_CTRL_8814B */
+#define BIT_EN_CLR_CMD_REL_BCN_PKT_P4_8814B BIT(7)
+#define BIT_EN_BCN_PKT_REL_P4_8814B BIT(6)
+#define BIT_EN_CLR_CMD_REL_BCN_PKT_P3_8814B BIT(5)
+#define BIT_EN_BCN_PKT_REL_P3_8814B BIT(4)
+#define BIT_EN_CLR_CMD_REL_BCN_PKT_P2_8814B BIT(3)
+#define BIT_EN_BCN_PKT_REL_P2_8814B BIT(2)
+#define BIT_EN_CLR_CMD_REL_BCN_PKT_P1_8814B BIT(1)
+#define BIT_EN_BCN_PKT_REL_P1_8814B BIT(0)
+
+/* 2 REG_AMPDU_MAX_LENGTH_HT_8814B */
+
+#define BIT_SHIFT_AMPDU_MAX_LENGTH_HT_8814B 0
+#define BIT_MASK_AMPDU_MAX_LENGTH_HT_8814B 0xffff
+#define BIT_AMPDU_MAX_LENGTH_HT_8814B(x)                                       \
+	(((x) & BIT_MASK_AMPDU_MAX_LENGTH_HT_8814B)                            \
+	 << BIT_SHIFT_AMPDU_MAX_LENGTH_HT_8814B)
+#define BITS_AMPDU_MAX_LENGTH_HT_8814B                                         \
+	(BIT_MASK_AMPDU_MAX_LENGTH_HT_8814B                                    \
+	 << BIT_SHIFT_AMPDU_MAX_LENGTH_HT_8814B)
+#define BIT_CLEAR_AMPDU_MAX_LENGTH_HT_8814B(x)                                 \
+	((x) & (~BITS_AMPDU_MAX_LENGTH_HT_8814B))
+#define BIT_GET_AMPDU_MAX_LENGTH_HT_8814B(x)                                   \
+	(((x) >> BIT_SHIFT_AMPDU_MAX_LENGTH_HT_8814B) &                        \
+	 BIT_MASK_AMPDU_MAX_LENGTH_HT_8814B)
+#define BIT_SET_AMPDU_MAX_LENGTH_HT_8814B(x, v)                                \
+	(BIT_CLEAR_AMPDU_MAX_LENGTH_HT_8814B(x) |                              \
+	 BIT_AMPDU_MAX_LENGTH_HT_8814B(v))
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NDPA_RATE_8814B */
+
+#define BIT_SHIFT_R_NDPA_RATE_V1_8814B 0
+#define BIT_MASK_R_NDPA_RATE_V1_8814B 0xff
+#define BIT_R_NDPA_RATE_V1_8814B(x)                                            \
+	(((x) & BIT_MASK_R_NDPA_RATE_V1_8814B)                                 \
+	 << BIT_SHIFT_R_NDPA_RATE_V1_8814B)
+#define BITS_R_NDPA_RATE_V1_8814B                                              \
+	(BIT_MASK_R_NDPA_RATE_V1_8814B << BIT_SHIFT_R_NDPA_RATE_V1_8814B)
+#define BIT_CLEAR_R_NDPA_RATE_V1_8814B(x) ((x) & (~BITS_R_NDPA_RATE_V1_8814B))
+#define BIT_GET_R_NDPA_RATE_V1_8814B(x)                                        \
+	(((x) >> BIT_SHIFT_R_NDPA_RATE_V1_8814B) &                             \
+	 BIT_MASK_R_NDPA_RATE_V1_8814B)
+#define BIT_SET_R_NDPA_RATE_V1_8814B(x, v)                                     \
+	(BIT_CLEAR_R_NDPA_RATE_V1_8814B(x) | BIT_R_NDPA_RATE_V1_8814B(v))
+
+/* 2 REG_TX_HANG_CTRL_8814B */
+#define BIT_EN_GNT_BT_AWAKE_8814B BIT(3)
+#define BIT_EN_EOF_V1_8814B BIT(2)
+#define BIT_DIS_OQT_BLOCK_8814B BIT(1)
+#define BIT_SEARCH_QUEUE_EN_8814B BIT(0)
+
+/* 2 REG_NDPA_OPT_CTRL_8814B */
+#define BIT_DIS_MACID_RELEASE_RTY_8814B BIT(5)
+
+#define BIT_SHIFT_BW_SIGTA_8814B 3
+#define BIT_MASK_BW_SIGTA_8814B 0x3
+#define BIT_BW_SIGTA_8814B(x)                                                  \
+	(((x) & BIT_MASK_BW_SIGTA_8814B) << BIT_SHIFT_BW_SIGTA_8814B)
+#define BITS_BW_SIGTA_8814B                                                    \
+	(BIT_MASK_BW_SIGTA_8814B << BIT_SHIFT_BW_SIGTA_8814B)
+#define BIT_CLEAR_BW_SIGTA_8814B(x) ((x) & (~BITS_BW_SIGTA_8814B))
+#define BIT_GET_BW_SIGTA_8814B(x)                                              \
+	(((x) >> BIT_SHIFT_BW_SIGTA_8814B) & BIT_MASK_BW_SIGTA_8814B)
+#define BIT_SET_BW_SIGTA_8814B(x, v)                                           \
+	(BIT_CLEAR_BW_SIGTA_8814B(x) | BIT_BW_SIGTA_8814B(v))
+
+#define BIT_EN_BAR_SIGTA_8814B BIT(2)
+
+#define BIT_SHIFT_NDPA_BW_8814B 0
+#define BIT_MASK_NDPA_BW_8814B 0x3
+#define BIT_NDPA_BW_8814B(x)                                                   \
+	(((x) & BIT_MASK_NDPA_BW_8814B) << BIT_SHIFT_NDPA_BW_8814B)
+#define BITS_NDPA_BW_8814B (BIT_MASK_NDPA_BW_8814B << BIT_SHIFT_NDPA_BW_8814B)
+#define BIT_CLEAR_NDPA_BW_8814B(x) ((x) & (~BITS_NDPA_BW_8814B))
+#define BIT_GET_NDPA_BW_8814B(x)                                               \
+	(((x) >> BIT_SHIFT_NDPA_BW_8814B) & BIT_MASK_NDPA_BW_8814B)
+#define BIT_SET_NDPA_BW_8814B(x, v)                                            \
+	(BIT_CLEAR_NDPA_BW_8814B(x) | BIT_NDPA_BW_8814B(v))
+
+/* 2 REG_AMPDU_MAX_LENGTH_VHT_8814B */
+
+#define BIT_SHIFT_AMPDU_MAX_LENGTH_VHT_8814B 0
+#define BIT_MASK_AMPDU_MAX_LENGTH_VHT_8814B 0x3ffff
+#define BIT_AMPDU_MAX_LENGTH_VHT_8814B(x)                                      \
+	(((x) & BIT_MASK_AMPDU_MAX_LENGTH_VHT_8814B)                           \
+	 << BIT_SHIFT_AMPDU_MAX_LENGTH_VHT_8814B)
+#define BITS_AMPDU_MAX_LENGTH_VHT_8814B                                        \
+	(BIT_MASK_AMPDU_MAX_LENGTH_VHT_8814B                                   \
+	 << BIT_SHIFT_AMPDU_MAX_LENGTH_VHT_8814B)
+#define BIT_CLEAR_AMPDU_MAX_LENGTH_VHT_8814B(x)                                \
+	((x) & (~BITS_AMPDU_MAX_LENGTH_VHT_8814B))
+#define BIT_GET_AMPDU_MAX_LENGTH_VHT_8814B(x)                                  \
+	(((x) >> BIT_SHIFT_AMPDU_MAX_LENGTH_VHT_8814B) &                       \
+	 BIT_MASK_AMPDU_MAX_LENGTH_VHT_8814B)
+#define BIT_SET_AMPDU_MAX_LENGTH_VHT_8814B(x, v)                               \
+	(BIT_CLEAR_AMPDU_MAX_LENGTH_VHT_8814B(x) |                             \
+	 BIT_AMPDU_MAX_LENGTH_VHT_8814B(v))
+
+/* 2 REG_RD_RESP_PKT_TH_8814B */
+
+#define BIT_SHIFT_RD_RESP_PKT_TH_V1_8814B 0
+#define BIT_MASK_RD_RESP_PKT_TH_V1_8814B 0x3f
+#define BIT_RD_RESP_PKT_TH_V1_8814B(x)                                         \
+	(((x) & BIT_MASK_RD_RESP_PKT_TH_V1_8814B)                              \
+	 << BIT_SHIFT_RD_RESP_PKT_TH_V1_8814B)
+#define BITS_RD_RESP_PKT_TH_V1_8814B                                           \
+	(BIT_MASK_RD_RESP_PKT_TH_V1_8814B << BIT_SHIFT_RD_RESP_PKT_TH_V1_8814B)
+#define BIT_CLEAR_RD_RESP_PKT_TH_V1_8814B(x)                                   \
+	((x) & (~BITS_RD_RESP_PKT_TH_V1_8814B))
+#define BIT_GET_RD_RESP_PKT_TH_V1_8814B(x)                                     \
+	(((x) >> BIT_SHIFT_RD_RESP_PKT_TH_V1_8814B) &                          \
+	 BIT_MASK_RD_RESP_PKT_TH_V1_8814B)
+#define BIT_SET_RD_RESP_PKT_TH_V1_8814B(x, v)                                  \
+	(BIT_CLEAR_RD_RESP_PKT_TH_V1_8814B(x) | BIT_RD_RESP_PKT_TH_V1_8814B(v))
+
+/* 2 REG_NEW_EDCA_CTRL_V1_8814B */
+
+#define BIT_SHIFT_RANDOM_VALUE_SHIFT_8814B 9
+#define BIT_MASK_RANDOM_VALUE_SHIFT_8814B 0x7
+#define BIT_RANDOM_VALUE_SHIFT_8814B(x)                                        \
+	(((x) & BIT_MASK_RANDOM_VALUE_SHIFT_8814B)                             \
+	 << BIT_SHIFT_RANDOM_VALUE_SHIFT_8814B)
+#define BITS_RANDOM_VALUE_SHIFT_8814B                                          \
+	(BIT_MASK_RANDOM_VALUE_SHIFT_8814B                                     \
+	 << BIT_SHIFT_RANDOM_VALUE_SHIFT_8814B)
+#define BIT_CLEAR_RANDOM_VALUE_SHIFT_8814B(x)                                  \
+	((x) & (~BITS_RANDOM_VALUE_SHIFT_8814B))
+#define BIT_GET_RANDOM_VALUE_SHIFT_8814B(x)                                    \
+	(((x) >> BIT_SHIFT_RANDOM_VALUE_SHIFT_8814B) &                         \
+	 BIT_MASK_RANDOM_VALUE_SHIFT_8814B)
+#define BIT_SET_RANDOM_VALUE_SHIFT_8814B(x, v)                                 \
+	(BIT_CLEAR_RANDOM_VALUE_SHIFT_8814B(x) |                               \
+	 BIT_RANDOM_VALUE_SHIFT_8814B(v))
+
+#define BIT_ENABLE_NEW_EDCA_8814B BIT(8)
+
+#define BIT_SHIFT_MEDIUM_HAS_IDKE_TRIGGER_8814B 0
+#define BIT_MASK_MEDIUM_HAS_IDKE_TRIGGER_8814B 0xff
+#define BIT_MEDIUM_HAS_IDKE_TRIGGER_8814B(x)                                   \
+	(((x) & BIT_MASK_MEDIUM_HAS_IDKE_TRIGGER_8814B)                        \
+	 << BIT_SHIFT_MEDIUM_HAS_IDKE_TRIGGER_8814B)
+#define BITS_MEDIUM_HAS_IDKE_TRIGGER_8814B                                     \
+	(BIT_MASK_MEDIUM_HAS_IDKE_TRIGGER_8814B                                \
+	 << BIT_SHIFT_MEDIUM_HAS_IDKE_TRIGGER_8814B)
+#define BIT_CLEAR_MEDIUM_HAS_IDKE_TRIGGER_8814B(x)                             \
+	((x) & (~BITS_MEDIUM_HAS_IDKE_TRIGGER_8814B))
+#define BIT_GET_MEDIUM_HAS_IDKE_TRIGGER_8814B(x)                               \
+	(((x) >> BIT_SHIFT_MEDIUM_HAS_IDKE_TRIGGER_8814B) &                    \
+	 BIT_MASK_MEDIUM_HAS_IDKE_TRIGGER_8814B)
+#define BIT_SET_MEDIUM_HAS_IDKE_TRIGGER_8814B(x, v)                            \
+	(BIT_CLEAR_MEDIUM_HAS_IDKE_TRIGGER_8814B(x) |                          \
+	 BIT_MEDIUM_HAS_IDKE_TRIGGER_8814B(v))
+
+/* 2 REG_ACQ_STOP_V2_8814B */
+#define BIT_AC19Q_STOP_8814B BIT(19)
+#define BIT_AC18Q_STOP_8814B BIT(18)
+#define BIT_AC17Q_STOP_8814B BIT(17)
+#define BIT_AC16Q_STOP_8814B BIT(16)
+#define BIT_AC15Q_STOP_8814B BIT(15)
+#define BIT_AC14Q_STOP_8814B BIT(14)
+#define BIT_AC13Q_STOP_8814B BIT(13)
+#define BIT_AC12Q_STOP_8814B BIT(12)
+#define BIT_AC11Q_STOP_8814B BIT(11)
+#define BIT_AC10Q_STOP_8814B BIT(10)
+#define BIT_AC9Q_STOP_8814B BIT(9)
+#define BIT_AC8Q_STOP_8814B BIT(8)
+#define BIT_AC7Q_STOP_8814B BIT(7)
+#define BIT_AC6Q_STOP_8814B BIT(6)
+#define BIT_AC5Q_STOP_8814B BIT(5)
+#define BIT_AC4Q_STOP_8814B BIT(4)
+#define BIT_AC3Q_STOP_8814B BIT(3)
+#define BIT_AC2Q_STOP_8814B BIT(2)
+#define BIT_AC1Q_STOP_8814B BIT(1)
+#define BIT_AC0Q_STOP_8814B BIT(0)
+
+/* 2 REG_WMAC_LBK_BUF_HD_V1_8814B */
+
+#define BIT_SHIFT_WMAC_LBK_BUF_HEAD_V1_8814B 0
+#define BIT_MASK_WMAC_LBK_BUF_HEAD_V1_8814B 0xfff
+#define BIT_WMAC_LBK_BUF_HEAD_V1_8814B(x)                                      \
+	(((x) & BIT_MASK_WMAC_LBK_BUF_HEAD_V1_8814B)                           \
+	 << BIT_SHIFT_WMAC_LBK_BUF_HEAD_V1_8814B)
+#define BITS_WMAC_LBK_BUF_HEAD_V1_8814B                                        \
+	(BIT_MASK_WMAC_LBK_BUF_HEAD_V1_8814B                                   \
+	 << BIT_SHIFT_WMAC_LBK_BUF_HEAD_V1_8814B)
+#define BIT_CLEAR_WMAC_LBK_BUF_HEAD_V1_8814B(x)                                \
+	((x) & (~BITS_WMAC_LBK_BUF_HEAD_V1_8814B))
+#define BIT_GET_WMAC_LBK_BUF_HEAD_V1_8814B(x)                                  \
+	(((x) >> BIT_SHIFT_WMAC_LBK_BUF_HEAD_V1_8814B) &                       \
+	 BIT_MASK_WMAC_LBK_BUF_HEAD_V1_8814B)
+#define BIT_SET_WMAC_LBK_BUF_HEAD_V1_8814B(x, v)                               \
+	(BIT_CLEAR_WMAC_LBK_BUF_HEAD_V1_8814B(x) |                             \
+	 BIT_WMAC_LBK_BUF_HEAD_V1_8814B(v))
+
+/* 2 REG_MGQ_BDNY_V1_8814B */
+
+#define BIT_SHIFT_MGQ_PGBNDY_V1_8814B 0
+#define BIT_MASK_MGQ_PGBNDY_V1_8814B 0xfff
+#define BIT_MGQ_PGBNDY_V1_8814B(x)                                             \
+	(((x) & BIT_MASK_MGQ_PGBNDY_V1_8814B) << BIT_SHIFT_MGQ_PGBNDY_V1_8814B)
+#define BITS_MGQ_PGBNDY_V1_8814B                                               \
+	(BIT_MASK_MGQ_PGBNDY_V1_8814B << BIT_SHIFT_MGQ_PGBNDY_V1_8814B)
+#define BIT_CLEAR_MGQ_PGBNDY_V1_8814B(x) ((x) & (~BITS_MGQ_PGBNDY_V1_8814B))
+#define BIT_GET_MGQ_PGBNDY_V1_8814B(x)                                         \
+	(((x) >> BIT_SHIFT_MGQ_PGBNDY_V1_8814B) & BIT_MASK_MGQ_PGBNDY_V1_8814B)
+#define BIT_SET_MGQ_PGBNDY_V1_8814B(x, v)                                      \
+	(BIT_CLEAR_MGQ_PGBNDY_V1_8814B(x) | BIT_MGQ_PGBNDY_V1_8814B(v))
+
+/* 2 REG_TXRPT_CTRL_8814B */
+
+#define BIT_SHIFT_TRXRPT_TIMER_TH_8814B 24
+#define BIT_MASK_TRXRPT_TIMER_TH_8814B 0xff
+#define BIT_TRXRPT_TIMER_TH_8814B(x)                                           \
+	(((x) & BIT_MASK_TRXRPT_TIMER_TH_8814B)                                \
+	 << BIT_SHIFT_TRXRPT_TIMER_TH_8814B)
+#define BITS_TRXRPT_TIMER_TH_8814B                                             \
+	(BIT_MASK_TRXRPT_TIMER_TH_8814B << BIT_SHIFT_TRXRPT_TIMER_TH_8814B)
+#define BIT_CLEAR_TRXRPT_TIMER_TH_8814B(x) ((x) & (~BITS_TRXRPT_TIMER_TH_8814B))
+#define BIT_GET_TRXRPT_TIMER_TH_8814B(x)                                       \
+	(((x) >> BIT_SHIFT_TRXRPT_TIMER_TH_8814B) &                            \
+	 BIT_MASK_TRXRPT_TIMER_TH_8814B)
+#define BIT_SET_TRXRPT_TIMER_TH_8814B(x, v)                                    \
+	(BIT_CLEAR_TRXRPT_TIMER_TH_8814B(x) | BIT_TRXRPT_TIMER_TH_8814B(v))
+
+#define BIT_SHIFT_TRXRPT_LEN_TH_8814B 16
+#define BIT_MASK_TRXRPT_LEN_TH_8814B 0xff
+#define BIT_TRXRPT_LEN_TH_8814B(x)                                             \
+	(((x) & BIT_MASK_TRXRPT_LEN_TH_8814B) << BIT_SHIFT_TRXRPT_LEN_TH_8814B)
+#define BITS_TRXRPT_LEN_TH_8814B                                               \
+	(BIT_MASK_TRXRPT_LEN_TH_8814B << BIT_SHIFT_TRXRPT_LEN_TH_8814B)
+#define BIT_CLEAR_TRXRPT_LEN_TH_8814B(x) ((x) & (~BITS_TRXRPT_LEN_TH_8814B))
+#define BIT_GET_TRXRPT_LEN_TH_8814B(x)                                         \
+	(((x) >> BIT_SHIFT_TRXRPT_LEN_TH_8814B) & BIT_MASK_TRXRPT_LEN_TH_8814B)
+#define BIT_SET_TRXRPT_LEN_TH_8814B(x, v)                                      \
+	(BIT_CLEAR_TRXRPT_LEN_TH_8814B(x) | BIT_TRXRPT_LEN_TH_8814B(v))
+
+#define BIT_SHIFT_TRXRPT_READ_PTR_8814B 8
+#define BIT_MASK_TRXRPT_READ_PTR_8814B 0xff
+#define BIT_TRXRPT_READ_PTR_8814B(x)                                           \
+	(((x) & BIT_MASK_TRXRPT_READ_PTR_8814B)                                \
+	 << BIT_SHIFT_TRXRPT_READ_PTR_8814B)
+#define BITS_TRXRPT_READ_PTR_8814B                                             \
+	(BIT_MASK_TRXRPT_READ_PTR_8814B << BIT_SHIFT_TRXRPT_READ_PTR_8814B)
+#define BIT_CLEAR_TRXRPT_READ_PTR_8814B(x) ((x) & (~BITS_TRXRPT_READ_PTR_8814B))
+#define BIT_GET_TRXRPT_READ_PTR_8814B(x)                                       \
+	(((x) >> BIT_SHIFT_TRXRPT_READ_PTR_8814B) &                            \
+	 BIT_MASK_TRXRPT_READ_PTR_8814B)
+#define BIT_SET_TRXRPT_READ_PTR_8814B(x, v)                                    \
+	(BIT_CLEAR_TRXRPT_READ_PTR_8814B(x) | BIT_TRXRPT_READ_PTR_8814B(v))
+
+#define BIT_SHIFT_TRXRPT_WRITE_PTR_8814B 0
+#define BIT_MASK_TRXRPT_WRITE_PTR_8814B 0xff
+#define BIT_TRXRPT_WRITE_PTR_8814B(x)                                          \
+	(((x) & BIT_MASK_TRXRPT_WRITE_PTR_8814B)                               \
+	 << BIT_SHIFT_TRXRPT_WRITE_PTR_8814B)
+#define BITS_TRXRPT_WRITE_PTR_8814B                                            \
+	(BIT_MASK_TRXRPT_WRITE_PTR_8814B << BIT_SHIFT_TRXRPT_WRITE_PTR_8814B)
+#define BIT_CLEAR_TRXRPT_WRITE_PTR_8814B(x)                                    \
+	((x) & (~BITS_TRXRPT_WRITE_PTR_8814B))
+#define BIT_GET_TRXRPT_WRITE_PTR_8814B(x)                                      \
+	(((x) >> BIT_SHIFT_TRXRPT_WRITE_PTR_8814B) &                           \
+	 BIT_MASK_TRXRPT_WRITE_PTR_8814B)
+#define BIT_SET_TRXRPT_WRITE_PTR_8814B(x, v)                                   \
+	(BIT_CLEAR_TRXRPT_WRITE_PTR_8814B(x) | BIT_TRXRPT_WRITE_PTR_8814B(v))
+
+/* 2 REG_INIRTS_RATE_SEL_8814B */
+#define BIT_LEAG_RTS_BW_DUP_8814B BIT(5)
+
+/* 2 REG_BASIC_CFEND_RATE_8814B */
+
+#define BIT_SHIFT_BASIC_CFEND_RATE_8814B 0
+#define BIT_MASK_BASIC_CFEND_RATE_8814B 0x1f
+#define BIT_BASIC_CFEND_RATE_8814B(x)                                          \
+	(((x) & BIT_MASK_BASIC_CFEND_RATE_8814B)                               \
+	 << BIT_SHIFT_BASIC_CFEND_RATE_8814B)
+#define BITS_BASIC_CFEND_RATE_8814B                                            \
+	(BIT_MASK_BASIC_CFEND_RATE_8814B << BIT_SHIFT_BASIC_CFEND_RATE_8814B)
+#define BIT_CLEAR_BASIC_CFEND_RATE_8814B(x)                                    \
+	((x) & (~BITS_BASIC_CFEND_RATE_8814B))
+#define BIT_GET_BASIC_CFEND_RATE_8814B(x)                                      \
+	(((x) >> BIT_SHIFT_BASIC_CFEND_RATE_8814B) &                           \
+	 BIT_MASK_BASIC_CFEND_RATE_8814B)
+#define BIT_SET_BASIC_CFEND_RATE_8814B(x, v)                                   \
+	(BIT_CLEAR_BASIC_CFEND_RATE_8814B(x) | BIT_BASIC_CFEND_RATE_8814B(v))
+
+/* 2 REG_STBC_CFEND_RATE_8814B */
+
+#define BIT_SHIFT_STBC_CFEND_RATE_8814B 0
+#define BIT_MASK_STBC_CFEND_RATE_8814B 0x1f
+#define BIT_STBC_CFEND_RATE_8814B(x)                                           \
+	(((x) & BIT_MASK_STBC_CFEND_RATE_8814B)                                \
+	 << BIT_SHIFT_STBC_CFEND_RATE_8814B)
+#define BITS_STBC_CFEND_RATE_8814B                                             \
+	(BIT_MASK_STBC_CFEND_RATE_8814B << BIT_SHIFT_STBC_CFEND_RATE_8814B)
+#define BIT_CLEAR_STBC_CFEND_RATE_8814B(x) ((x) & (~BITS_STBC_CFEND_RATE_8814B))
+#define BIT_GET_STBC_CFEND_RATE_8814B(x)                                       \
+	(((x) >> BIT_SHIFT_STBC_CFEND_RATE_8814B) &                            \
+	 BIT_MASK_STBC_CFEND_RATE_8814B)
+#define BIT_SET_STBC_CFEND_RATE_8814B(x, v)                                    \
+	(BIT_CLEAR_STBC_CFEND_RATE_8814B(x) | BIT_STBC_CFEND_RATE_8814B(v))
+
+/* 2 REG_DATA_SC_8814B */
+
+#define BIT_SHIFT_TXSC_40M_8814B 4
+#define BIT_MASK_TXSC_40M_8814B 0xf
+#define BIT_TXSC_40M_8814B(x)                                                  \
+	(((x) & BIT_MASK_TXSC_40M_8814B) << BIT_SHIFT_TXSC_40M_8814B)
+#define BITS_TXSC_40M_8814B                                                    \
+	(BIT_MASK_TXSC_40M_8814B << BIT_SHIFT_TXSC_40M_8814B)
+#define BIT_CLEAR_TXSC_40M_8814B(x) ((x) & (~BITS_TXSC_40M_8814B))
+#define BIT_GET_TXSC_40M_8814B(x)                                              \
+	(((x) >> BIT_SHIFT_TXSC_40M_8814B) & BIT_MASK_TXSC_40M_8814B)
+#define BIT_SET_TXSC_40M_8814B(x, v)                                           \
+	(BIT_CLEAR_TXSC_40M_8814B(x) | BIT_TXSC_40M_8814B(v))
+
+#define BIT_SHIFT_TXSC_20M_8814B 0
+#define BIT_MASK_TXSC_20M_8814B 0xf
+#define BIT_TXSC_20M_8814B(x)                                                  \
+	(((x) & BIT_MASK_TXSC_20M_8814B) << BIT_SHIFT_TXSC_20M_8814B)
+#define BITS_TXSC_20M_8814B                                                    \
+	(BIT_MASK_TXSC_20M_8814B << BIT_SHIFT_TXSC_20M_8814B)
+#define BIT_CLEAR_TXSC_20M_8814B(x) ((x) & (~BITS_TXSC_20M_8814B))
+#define BIT_GET_TXSC_20M_8814B(x)                                              \
+	(((x) >> BIT_SHIFT_TXSC_20M_8814B) & BIT_MASK_TXSC_20M_8814B)
+#define BIT_SET_TXSC_20M_8814B(x, v)                                           \
+	(BIT_CLEAR_TXSC_20M_8814B(x) | BIT_TXSC_20M_8814B(v))
+
+/* 2 REG_MOREDATA_V1_8814B */
+#define BIT_MOREDATA_CTRL2_EN_V1_8814B BIT(3)
+#define BIT_MOREDATA_CTRL1_EN_V1_8814B BIT(2)
+#define BIT_PKTIN_MOREDATA_REPLACE_ENABLE_V1_8814B BIT(0)
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_DATA_SC1_8814B */
+
+#define BIT_SHIFT_TXSC_160M_8814B 4
+#define BIT_MASK_TXSC_160M_8814B 0xf
+#define BIT_TXSC_160M_8814B(x)                                                 \
+	(((x) & BIT_MASK_TXSC_160M_8814B) << BIT_SHIFT_TXSC_160M_8814B)
+#define BITS_TXSC_160M_8814B                                                   \
+	(BIT_MASK_TXSC_160M_8814B << BIT_SHIFT_TXSC_160M_8814B)
+#define BIT_CLEAR_TXSC_160M_8814B(x) ((x) & (~BITS_TXSC_160M_8814B))
+#define BIT_GET_TXSC_160M_8814B(x)                                             \
+	(((x) >> BIT_SHIFT_TXSC_160M_8814B) & BIT_MASK_TXSC_160M_8814B)
+#define BIT_SET_TXSC_160M_8814B(x, v)                                          \
+	(BIT_CLEAR_TXSC_160M_8814B(x) | BIT_TXSC_160M_8814B(v))
+
+#define BIT_SHIFT_TXSC_80M_8814B 0
+#define BIT_MASK_TXSC_80M_8814B 0xf
+#define BIT_TXSC_80M_8814B(x)                                                  \
+	(((x) & BIT_MASK_TXSC_80M_8814B) << BIT_SHIFT_TXSC_80M_8814B)
+#define BITS_TXSC_80M_8814B                                                    \
+	(BIT_MASK_TXSC_80M_8814B << BIT_SHIFT_TXSC_80M_8814B)
+#define BIT_CLEAR_TXSC_80M_8814B(x) ((x) & (~BITS_TXSC_80M_8814B))
+#define BIT_GET_TXSC_80M_8814B(x)                                              \
+	(((x) >> BIT_SHIFT_TXSC_80M_8814B) & BIT_MASK_TXSC_80M_8814B)
+#define BIT_SET_TXSC_80M_8814B(x, v)                                           \
+	(BIT_CLEAR_TXSC_80M_8814B(x) | BIT_TXSC_80M_8814B(v))
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_TXRPT_START_OFFSET_8814B */
+#define BIT_RPTFIFO_RPTNUM_OPT_8814B BIT(31)
+
+#define BIT_SHIFT_MISSED_RPT_NUM_8814B 28
+#define BIT_MASK_MISSED_RPT_NUM_8814B 0x7
+#define BIT_MISSED_RPT_NUM_8814B(x)                                            \
+	(((x) & BIT_MASK_MISSED_RPT_NUM_8814B)                                 \
+	 << BIT_SHIFT_MISSED_RPT_NUM_8814B)
+#define BITS_MISSED_RPT_NUM_8814B                                              \
+	(BIT_MASK_MISSED_RPT_NUM_8814B << BIT_SHIFT_MISSED_RPT_NUM_8814B)
+#define BIT_CLEAR_MISSED_RPT_NUM_8814B(x) ((x) & (~BITS_MISSED_RPT_NUM_8814B))
+#define BIT_GET_MISSED_RPT_NUM_8814B(x)                                        \
+	(((x) >> BIT_SHIFT_MISSED_RPT_NUM_8814B) &                             \
+	 BIT_MASK_MISSED_RPT_NUM_8814B)
+#define BIT_SET_MISSED_RPT_NUM_8814B(x, v)                                     \
+	(BIT_CLEAR_MISSED_RPT_NUM_8814B(x) | BIT_MISSED_RPT_NUM_8814B(v))
+
+#define BIT_SHIFT_MACID_CTRL_OFFSET_V1_8814B 16
+#define BIT_MASK_MACID_CTRL_OFFSET_V1_8814B 0x1ff
+#define BIT_MACID_CTRL_OFFSET_V1_8814B(x)                                      \
+	(((x) & BIT_MASK_MACID_CTRL_OFFSET_V1_8814B)                           \
+	 << BIT_SHIFT_MACID_CTRL_OFFSET_V1_8814B)
+#define BITS_MACID_CTRL_OFFSET_V1_8814B                                        \
+	(BIT_MASK_MACID_CTRL_OFFSET_V1_8814B                                   \
+	 << BIT_SHIFT_MACID_CTRL_OFFSET_V1_8814B)
+#define BIT_CLEAR_MACID_CTRL_OFFSET_V1_8814B(x)                                \
+	((x) & (~BITS_MACID_CTRL_OFFSET_V1_8814B))
+#define BIT_GET_MACID_CTRL_OFFSET_V1_8814B(x)                                  \
+	(((x) >> BIT_SHIFT_MACID_CTRL_OFFSET_V1_8814B) &                       \
+	 BIT_MASK_MACID_CTRL_OFFSET_V1_8814B)
+#define BIT_SET_MACID_CTRL_OFFSET_V1_8814B(x, v)                               \
+	(BIT_CLEAR_MACID_CTRL_OFFSET_V1_8814B(x) |                             \
+	 BIT_MACID_CTRL_OFFSET_V1_8814B(v))
+
+#define BIT_SHIFT_AMPDU_TXRPT_OFFSET_V1_8814B 0
+#define BIT_MASK_AMPDU_TXRPT_OFFSET_V1_8814B 0x1ff
+#define BIT_AMPDU_TXRPT_OFFSET_V1_8814B(x)                                     \
+	(((x) & BIT_MASK_AMPDU_TXRPT_OFFSET_V1_8814B)                          \
+	 << BIT_SHIFT_AMPDU_TXRPT_OFFSET_V1_8814B)
+#define BITS_AMPDU_TXRPT_OFFSET_V1_8814B                                       \
+	(BIT_MASK_AMPDU_TXRPT_OFFSET_V1_8814B                                  \
+	 << BIT_SHIFT_AMPDU_TXRPT_OFFSET_V1_8814B)
+#define BIT_CLEAR_AMPDU_TXRPT_OFFSET_V1_8814B(x)                               \
+	((x) & (~BITS_AMPDU_TXRPT_OFFSET_V1_8814B))
+#define BIT_GET_AMPDU_TXRPT_OFFSET_V1_8814B(x)                                 \
+	(((x) >> BIT_SHIFT_AMPDU_TXRPT_OFFSET_V1_8814B) &                      \
+	 BIT_MASK_AMPDU_TXRPT_OFFSET_V1_8814B)
+#define BIT_SET_AMPDU_TXRPT_OFFSET_V1_8814B(x, v)                              \
+	(BIT_CLEAR_AMPDU_TXRPT_OFFSET_V1_8814B(x) |                            \
+	 BIT_AMPDU_TXRPT_OFFSET_V1_8814B(v))
+
+/* 2 REG_POWER_STAGE1_8814B */
+#define BIT_PTA_WL_PRI_MASK_CPU_MGQ_8814B BIT(31)
+#define BIT_PTA_WL_PRI_MASK_BCNQ_8814B BIT(30)
+#define BIT_PTA_WL_PRI_MASK_HIQ_8814B BIT(29)
+#define BIT_PTA_WL_PRI_MASK_MGQ_8814B BIT(28)
+#define BIT_PTA_WL_PRI_MASK_BK_8814B BIT(27)
+#define BIT_PTA_WL_PRI_MASK_BE_8814B BIT(26)
+#define BIT_PTA_WL_PRI_MASK_VI_8814B BIT(25)
+#define BIT_PTA_WL_PRI_MASK_VO_8814B BIT(24)
+
+#define BIT_SHIFT_POWER_STAGE1_8814B 0
+#define BIT_MASK_POWER_STAGE1_8814B 0xffffff
+#define BIT_POWER_STAGE1_8814B(x)                                              \
+	(((x) & BIT_MASK_POWER_STAGE1_8814B) << BIT_SHIFT_POWER_STAGE1_8814B)
+#define BITS_POWER_STAGE1_8814B                                                \
+	(BIT_MASK_POWER_STAGE1_8814B << BIT_SHIFT_POWER_STAGE1_8814B)
+#define BIT_CLEAR_POWER_STAGE1_8814B(x) ((x) & (~BITS_POWER_STAGE1_8814B))
+#define BIT_GET_POWER_STAGE1_8814B(x)                                          \
+	(((x) >> BIT_SHIFT_POWER_STAGE1_8814B) & BIT_MASK_POWER_STAGE1_8814B)
+#define BIT_SET_POWER_STAGE1_8814B(x, v)                                       \
+	(BIT_CLEAR_POWER_STAGE1_8814B(x) | BIT_POWER_STAGE1_8814B(v))
+
+/* 2 REG_POWER_STAGE2_8814B */
+#define BIT__CTRL_PKT_POW_ADJ_8814B BIT(24)
+
+#define BIT_SHIFT_POWER_STAGE2_8814B 0
+#define BIT_MASK_POWER_STAGE2_8814B 0xffffff
+#define BIT_POWER_STAGE2_8814B(x)                                              \
+	(((x) & BIT_MASK_POWER_STAGE2_8814B) << BIT_SHIFT_POWER_STAGE2_8814B)
+#define BITS_POWER_STAGE2_8814B                                                \
+	(BIT_MASK_POWER_STAGE2_8814B << BIT_SHIFT_POWER_STAGE2_8814B)
+#define BIT_CLEAR_POWER_STAGE2_8814B(x) ((x) & (~BITS_POWER_STAGE2_8814B))
+#define BIT_GET_POWER_STAGE2_8814B(x)                                          \
+	(((x) >> BIT_SHIFT_POWER_STAGE2_8814B) & BIT_MASK_POWER_STAGE2_8814B)
+#define BIT_SET_POWER_STAGE2_8814B(x, v)                                       \
+	(BIT_CLEAR_POWER_STAGE2_8814B(x) | BIT_POWER_STAGE2_8814B(v))
+
+/* 2 REG_SW_AMPDU_BURST_MODE_CTRL_8814B */
+#define BIT_DMA_THIS_QUEUE_BK_8814B BIT(23)
+#define BIT_DMA_THIS_QUEUE_BE_8814B BIT(22)
+#define BIT_DMA_THIS_QUEUE_VI_8814B BIT(21)
+#define BIT_DMA_THIS_QUEUE_VO_8814B BIT(20)
+
+#define BIT_SHIFT_TOTAL_LEN_TH_8814B 8
+#define BIT_MASK_TOTAL_LEN_TH_8814B 0xfff
+#define BIT_TOTAL_LEN_TH_8814B(x)                                              \
+	(((x) & BIT_MASK_TOTAL_LEN_TH_8814B) << BIT_SHIFT_TOTAL_LEN_TH_8814B)
+#define BITS_TOTAL_LEN_TH_8814B                                                \
+	(BIT_MASK_TOTAL_LEN_TH_8814B << BIT_SHIFT_TOTAL_LEN_TH_8814B)
+#define BIT_CLEAR_TOTAL_LEN_TH_8814B(x) ((x) & (~BITS_TOTAL_LEN_TH_8814B))
+#define BIT_GET_TOTAL_LEN_TH_8814B(x)                                          \
+	(((x) >> BIT_SHIFT_TOTAL_LEN_TH_8814B) & BIT_MASK_TOTAL_LEN_TH_8814B)
+#define BIT_SET_TOTAL_LEN_TH_8814B(x, v)                                       \
+	(BIT_CLEAR_TOTAL_LEN_TH_8814B(x) | BIT_TOTAL_LEN_TH_8814B(v))
+
+#define BIT_PRE_TX_CMD_8814B BIT(6)
+
+#define BIT_SHIFT_NUM_SCL_EN_8814B 4
+#define BIT_MASK_NUM_SCL_EN_8814B 0x3
+#define BIT_NUM_SCL_EN_8814B(x)                                                \
+	(((x) & BIT_MASK_NUM_SCL_EN_8814B) << BIT_SHIFT_NUM_SCL_EN_8814B)
+#define BITS_NUM_SCL_EN_8814B                                                  \
+	(BIT_MASK_NUM_SCL_EN_8814B << BIT_SHIFT_NUM_SCL_EN_8814B)
+#define BIT_CLEAR_NUM_SCL_EN_8814B(x) ((x) & (~BITS_NUM_SCL_EN_8814B))
+#define BIT_GET_NUM_SCL_EN_8814B(x)                                            \
+	(((x) >> BIT_SHIFT_NUM_SCL_EN_8814B) & BIT_MASK_NUM_SCL_EN_8814B)
+#define BIT_SET_NUM_SCL_EN_8814B(x, v)                                         \
+	(BIT_CLEAR_NUM_SCL_EN_8814B(x) | BIT_NUM_SCL_EN_8814B(v))
+
+#define BIT_BK_EN_8814B BIT(3)
+#define BIT_BE_EN_8814B BIT(2)
+#define BIT_VI_EN_8814B BIT(1)
+#define BIT_VO_EN_8814B BIT(0)
+
+/* 2 REG_PKT_LIFE_TIME_8814B */
+
+#define BIT_SHIFT_PKT_LIFTIME_BEBK_8814B 16
+#define BIT_MASK_PKT_LIFTIME_BEBK_8814B 0xffff
+#define BIT_PKT_LIFTIME_BEBK_8814B(x)                                          \
+	(((x) & BIT_MASK_PKT_LIFTIME_BEBK_8814B)                               \
+	 << BIT_SHIFT_PKT_LIFTIME_BEBK_8814B)
+#define BITS_PKT_LIFTIME_BEBK_8814B                                            \
+	(BIT_MASK_PKT_LIFTIME_BEBK_8814B << BIT_SHIFT_PKT_LIFTIME_BEBK_8814B)
+#define BIT_CLEAR_PKT_LIFTIME_BEBK_8814B(x)                                    \
+	((x) & (~BITS_PKT_LIFTIME_BEBK_8814B))
+#define BIT_GET_PKT_LIFTIME_BEBK_8814B(x)                                      \
+	(((x) >> BIT_SHIFT_PKT_LIFTIME_BEBK_8814B) &                           \
+	 BIT_MASK_PKT_LIFTIME_BEBK_8814B)
+#define BIT_SET_PKT_LIFTIME_BEBK_8814B(x, v)                                   \
+	(BIT_CLEAR_PKT_LIFTIME_BEBK_8814B(x) | BIT_PKT_LIFTIME_BEBK_8814B(v))
+
+#define BIT_SHIFT_PKT_LIFTIME_VOVI_8814B 0
+#define BIT_MASK_PKT_LIFTIME_VOVI_8814B 0xffff
+#define BIT_PKT_LIFTIME_VOVI_8814B(x)                                          \
+	(((x) & BIT_MASK_PKT_LIFTIME_VOVI_8814B)                               \
+	 << BIT_SHIFT_PKT_LIFTIME_VOVI_8814B)
+#define BITS_PKT_LIFTIME_VOVI_8814B                                            \
+	(BIT_MASK_PKT_LIFTIME_VOVI_8814B << BIT_SHIFT_PKT_LIFTIME_VOVI_8814B)
+#define BIT_CLEAR_PKT_LIFTIME_VOVI_8814B(x)                                    \
+	((x) & (~BITS_PKT_LIFTIME_VOVI_8814B))
+#define BIT_GET_PKT_LIFTIME_VOVI_8814B(x)                                      \
+	(((x) >> BIT_SHIFT_PKT_LIFTIME_VOVI_8814B) &                           \
+	 BIT_MASK_PKT_LIFTIME_VOVI_8814B)
+#define BIT_SET_PKT_LIFTIME_VOVI_8814B(x, v)                                   \
+	(BIT_CLEAR_PKT_LIFTIME_VOVI_8814B(x) | BIT_PKT_LIFTIME_VOVI_8814B(v))
+
+/* 2 REG_STBC_SETTING_8814B */
+
+#define BIT_SHIFT_CDEND_TXTIME_L_8814B 4
+#define BIT_MASK_CDEND_TXTIME_L_8814B 0xf
+#define BIT_CDEND_TXTIME_L_8814B(x)                                            \
+	(((x) & BIT_MASK_CDEND_TXTIME_L_8814B)                                 \
+	 << BIT_SHIFT_CDEND_TXTIME_L_8814B)
+#define BITS_CDEND_TXTIME_L_8814B                                              \
+	(BIT_MASK_CDEND_TXTIME_L_8814B << BIT_SHIFT_CDEND_TXTIME_L_8814B)
+#define BIT_CLEAR_CDEND_TXTIME_L_8814B(x) ((x) & (~BITS_CDEND_TXTIME_L_8814B))
+#define BIT_GET_CDEND_TXTIME_L_8814B(x)                                        \
+	(((x) >> BIT_SHIFT_CDEND_TXTIME_L_8814B) &                             \
+	 BIT_MASK_CDEND_TXTIME_L_8814B)
+#define BIT_SET_CDEND_TXTIME_L_8814B(x, v)                                     \
+	(BIT_CLEAR_CDEND_TXTIME_L_8814B(x) | BIT_CDEND_TXTIME_L_8814B(v))
+
+#define BIT_SHIFT_NESS_8814B 2
+#define BIT_MASK_NESS_8814B 0x3
+#define BIT_NESS_8814B(x) (((x) & BIT_MASK_NESS_8814B) << BIT_SHIFT_NESS_8814B)
+#define BITS_NESS_8814B (BIT_MASK_NESS_8814B << BIT_SHIFT_NESS_8814B)
+#define BIT_CLEAR_NESS_8814B(x) ((x) & (~BITS_NESS_8814B))
+#define BIT_GET_NESS_8814B(x)                                                  \
+	(((x) >> BIT_SHIFT_NESS_8814B) & BIT_MASK_NESS_8814B)
+#define BIT_SET_NESS_8814B(x, v) (BIT_CLEAR_NESS_8814B(x) | BIT_NESS_8814B(v))
+
+#define BIT_SHIFT_STBC_CFEND_8814B 0
+#define BIT_MASK_STBC_CFEND_8814B 0x3
+#define BIT_STBC_CFEND_8814B(x)                                                \
+	(((x) & BIT_MASK_STBC_CFEND_8814B) << BIT_SHIFT_STBC_CFEND_8814B)
+#define BITS_STBC_CFEND_8814B                                                  \
+	(BIT_MASK_STBC_CFEND_8814B << BIT_SHIFT_STBC_CFEND_8814B)
+#define BIT_CLEAR_STBC_CFEND_8814B(x) ((x) & (~BITS_STBC_CFEND_8814B))
+#define BIT_GET_STBC_CFEND_8814B(x)                                            \
+	(((x) >> BIT_SHIFT_STBC_CFEND_8814B) & BIT_MASK_STBC_CFEND_8814B)
+#define BIT_SET_STBC_CFEND_8814B(x, v)                                         \
+	(BIT_CLEAR_STBC_CFEND_8814B(x) | BIT_STBC_CFEND_8814B(v))
+
+/* 2 REG_STBC_SETTING2_8814B */
+
+#define BIT_SHIFT_CDEND_TXTIME_H_8814B 0
+#define BIT_MASK_CDEND_TXTIME_H_8814B 0x1f
+#define BIT_CDEND_TXTIME_H_8814B(x)                                            \
+	(((x) & BIT_MASK_CDEND_TXTIME_H_8814B)                                 \
+	 << BIT_SHIFT_CDEND_TXTIME_H_8814B)
+#define BITS_CDEND_TXTIME_H_8814B                                              \
+	(BIT_MASK_CDEND_TXTIME_H_8814B << BIT_SHIFT_CDEND_TXTIME_H_8814B)
+#define BIT_CLEAR_CDEND_TXTIME_H_8814B(x) ((x) & (~BITS_CDEND_TXTIME_H_8814B))
+#define BIT_GET_CDEND_TXTIME_H_8814B(x)                                        \
+	(((x) >> BIT_SHIFT_CDEND_TXTIME_H_8814B) &                             \
+	 BIT_MASK_CDEND_TXTIME_H_8814B)
+#define BIT_SET_CDEND_TXTIME_H_8814B(x, v)                                     \
+	(BIT_CLEAR_CDEND_TXTIME_H_8814B(x) | BIT_CDEND_TXTIME_H_8814B(v))
+
+/* 2 REG_QUEUE_CTRL_8814B */
+#define BIT_FORCE_RND_PRI_8814B BIT(6)
+#define BIT_PTA_EDCCA_EN_8814B BIT(5)
+#define BIT_PTA_WL_TX_EN_8814B BIT(4)
+#define BIT_USE_DATA_BW_8814B BIT(3)
+#define BIT_TRI_PKT_INT_MODE1_8814B BIT(2)
+#define BIT_TRI_PKT_INT_MODE0_8814B BIT(1)
+#define BIT_ACQ_MODE_SEL_8814B BIT(0)
+
+/* 2 REG_SINGLE_AMPDU_CTRL_8814B */
+#define BIT_EN_SINGLE_APMDU_8814B BIT(7)
+
+/* 2 REG_PROT_MODE_CTRL_8814B */
+
+#define BIT_SHIFT_RTS_MAX_AGG_NUM_8814B 24
+#define BIT_MASK_RTS_MAX_AGG_NUM_8814B 0x3f
+#define BIT_RTS_MAX_AGG_NUM_8814B(x)                                           \
+	(((x) & BIT_MASK_RTS_MAX_AGG_NUM_8814B)                                \
+	 << BIT_SHIFT_RTS_MAX_AGG_NUM_8814B)
+#define BITS_RTS_MAX_AGG_NUM_8814B                                             \
+	(BIT_MASK_RTS_MAX_AGG_NUM_8814B << BIT_SHIFT_RTS_MAX_AGG_NUM_8814B)
+#define BIT_CLEAR_RTS_MAX_AGG_NUM_8814B(x) ((x) & (~BITS_RTS_MAX_AGG_NUM_8814B))
+#define BIT_GET_RTS_MAX_AGG_NUM_8814B(x)                                       \
+	(((x) >> BIT_SHIFT_RTS_MAX_AGG_NUM_8814B) &                            \
+	 BIT_MASK_RTS_MAX_AGG_NUM_8814B)
+#define BIT_SET_RTS_MAX_AGG_NUM_8814B(x, v)                                    \
+	(BIT_CLEAR_RTS_MAX_AGG_NUM_8814B(x) | BIT_RTS_MAX_AGG_NUM_8814B(v))
+
+#define BIT_SHIFT_MAX_AGG_NUM_8814B 16
+#define BIT_MASK_MAX_AGG_NUM_8814B 0x3f
+#define BIT_MAX_AGG_NUM_8814B(x)                                               \
+	(((x) & BIT_MASK_MAX_AGG_NUM_8814B) << BIT_SHIFT_MAX_AGG_NUM_8814B)
+#define BITS_MAX_AGG_NUM_8814B                                                 \
+	(BIT_MASK_MAX_AGG_NUM_8814B << BIT_SHIFT_MAX_AGG_NUM_8814B)
+#define BIT_CLEAR_MAX_AGG_NUM_8814B(x) ((x) & (~BITS_MAX_AGG_NUM_8814B))
+#define BIT_GET_MAX_AGG_NUM_8814B(x)                                           \
+	(((x) >> BIT_SHIFT_MAX_AGG_NUM_8814B) & BIT_MASK_MAX_AGG_NUM_8814B)
+#define BIT_SET_MAX_AGG_NUM_8814B(x, v)                                        \
+	(BIT_CLEAR_MAX_AGG_NUM_8814B(x) | BIT_MAX_AGG_NUM_8814B(v))
+
+#define BIT_SHIFT_RTS_TXTIME_TH_8814B 8
+#define BIT_MASK_RTS_TXTIME_TH_8814B 0xff
+#define BIT_RTS_TXTIME_TH_8814B(x)                                             \
+	(((x) & BIT_MASK_RTS_TXTIME_TH_8814B) << BIT_SHIFT_RTS_TXTIME_TH_8814B)
+#define BITS_RTS_TXTIME_TH_8814B                                               \
+	(BIT_MASK_RTS_TXTIME_TH_8814B << BIT_SHIFT_RTS_TXTIME_TH_8814B)
+#define BIT_CLEAR_RTS_TXTIME_TH_8814B(x) ((x) & (~BITS_RTS_TXTIME_TH_8814B))
+#define BIT_GET_RTS_TXTIME_TH_8814B(x)                                         \
+	(((x) >> BIT_SHIFT_RTS_TXTIME_TH_8814B) & BIT_MASK_RTS_TXTIME_TH_8814B)
+#define BIT_SET_RTS_TXTIME_TH_8814B(x, v)                                      \
+	(BIT_CLEAR_RTS_TXTIME_TH_8814B(x) | BIT_RTS_TXTIME_TH_8814B(v))
+
+#define BIT_SHIFT_RTS_LEN_TH_8814B 0
+#define BIT_MASK_RTS_LEN_TH_8814B 0xff
+#define BIT_RTS_LEN_TH_8814B(x)                                                \
+	(((x) & BIT_MASK_RTS_LEN_TH_8814B) << BIT_SHIFT_RTS_LEN_TH_8814B)
+#define BITS_RTS_LEN_TH_8814B                                                  \
+	(BIT_MASK_RTS_LEN_TH_8814B << BIT_SHIFT_RTS_LEN_TH_8814B)
+#define BIT_CLEAR_RTS_LEN_TH_8814B(x) ((x) & (~BITS_RTS_LEN_TH_8814B))
+#define BIT_GET_RTS_LEN_TH_8814B(x)                                            \
+	(((x) >> BIT_SHIFT_RTS_LEN_TH_8814B) & BIT_MASK_RTS_LEN_TH_8814B)
+#define BIT_SET_RTS_LEN_TH_8814B(x, v)                                         \
+	(BIT_CLEAR_RTS_LEN_TH_8814B(x) | BIT_RTS_LEN_TH_8814B(v))
+
+/* 2 REG_BAR_MODE_CTRL_8814B */
+
+#define BIT_SHIFT_BAR_RTY_LMT_8814B 16
+#define BIT_MASK_BAR_RTY_LMT_8814B 0x3
+#define BIT_BAR_RTY_LMT_8814B(x)                                               \
+	(((x) & BIT_MASK_BAR_RTY_LMT_8814B) << BIT_SHIFT_BAR_RTY_LMT_8814B)
+#define BITS_BAR_RTY_LMT_8814B                                                 \
+	(BIT_MASK_BAR_RTY_LMT_8814B << BIT_SHIFT_BAR_RTY_LMT_8814B)
+#define BIT_CLEAR_BAR_RTY_LMT_8814B(x) ((x) & (~BITS_BAR_RTY_LMT_8814B))
+#define BIT_GET_BAR_RTY_LMT_8814B(x)                                           \
+	(((x) >> BIT_SHIFT_BAR_RTY_LMT_8814B) & BIT_MASK_BAR_RTY_LMT_8814B)
+#define BIT_SET_BAR_RTY_LMT_8814B(x, v)                                        \
+	(BIT_CLEAR_BAR_RTY_LMT_8814B(x) | BIT_BAR_RTY_LMT_8814B(v))
+
+#define BIT_SHIFT_BAR_PKT_TXTIME_TH_8814B 8
+#define BIT_MASK_BAR_PKT_TXTIME_TH_8814B 0xff
+#define BIT_BAR_PKT_TXTIME_TH_8814B(x)                                         \
+	(((x) & BIT_MASK_BAR_PKT_TXTIME_TH_8814B)                              \
+	 << BIT_SHIFT_BAR_PKT_TXTIME_TH_8814B)
+#define BITS_BAR_PKT_TXTIME_TH_8814B                                           \
+	(BIT_MASK_BAR_PKT_TXTIME_TH_8814B << BIT_SHIFT_BAR_PKT_TXTIME_TH_8814B)
+#define BIT_CLEAR_BAR_PKT_TXTIME_TH_8814B(x)                                   \
+	((x) & (~BITS_BAR_PKT_TXTIME_TH_8814B))
+#define BIT_GET_BAR_PKT_TXTIME_TH_8814B(x)                                     \
+	(((x) >> BIT_SHIFT_BAR_PKT_TXTIME_TH_8814B) &                          \
+	 BIT_MASK_BAR_PKT_TXTIME_TH_8814B)
+#define BIT_SET_BAR_PKT_TXTIME_TH_8814B(x, v)                                  \
+	(BIT_CLEAR_BAR_PKT_TXTIME_TH_8814B(x) | BIT_BAR_PKT_TXTIME_TH_8814B(v))
+
+#define BIT_BAR_EN_V1_8814B BIT(6)
+
+#define BIT_SHIFT_BAR_PKTNUM_TH_V1_8814B 0
+#define BIT_MASK_BAR_PKTNUM_TH_V1_8814B 0x3f
+#define BIT_BAR_PKTNUM_TH_V1_8814B(x)                                          \
+	(((x) & BIT_MASK_BAR_PKTNUM_TH_V1_8814B)                               \
+	 << BIT_SHIFT_BAR_PKTNUM_TH_V1_8814B)
+#define BITS_BAR_PKTNUM_TH_V1_8814B                                            \
+	(BIT_MASK_BAR_PKTNUM_TH_V1_8814B << BIT_SHIFT_BAR_PKTNUM_TH_V1_8814B)
+#define BIT_CLEAR_BAR_PKTNUM_TH_V1_8814B(x)                                    \
+	((x) & (~BITS_BAR_PKTNUM_TH_V1_8814B))
+#define BIT_GET_BAR_PKTNUM_TH_V1_8814B(x)                                      \
+	(((x) >> BIT_SHIFT_BAR_PKTNUM_TH_V1_8814B) &                           \
+	 BIT_MASK_BAR_PKTNUM_TH_V1_8814B)
+#define BIT_SET_BAR_PKTNUM_TH_V1_8814B(x, v)                                   \
+	(BIT_CLEAR_BAR_PKTNUM_TH_V1_8814B(x) | BIT_BAR_PKTNUM_TH_V1_8814B(v))
+
+/* 2 REG_RA_TRY_RATE_AGG_LMT_8814B */
+
+#define BIT_SHIFT_RA_TRY_RATE_AGG_LMT_V1_8814B 0
+#define BIT_MASK_RA_TRY_RATE_AGG_LMT_V1_8814B 0x3f
+#define BIT_RA_TRY_RATE_AGG_LMT_V1_8814B(x)                                    \
+	(((x) & BIT_MASK_RA_TRY_RATE_AGG_LMT_V1_8814B)                         \
+	 << BIT_SHIFT_RA_TRY_RATE_AGG_LMT_V1_8814B)
+#define BITS_RA_TRY_RATE_AGG_LMT_V1_8814B                                      \
+	(BIT_MASK_RA_TRY_RATE_AGG_LMT_V1_8814B                                 \
+	 << BIT_SHIFT_RA_TRY_RATE_AGG_LMT_V1_8814B)
+#define BIT_CLEAR_RA_TRY_RATE_AGG_LMT_V1_8814B(x)                              \
+	((x) & (~BITS_RA_TRY_RATE_AGG_LMT_V1_8814B))
+#define BIT_GET_RA_TRY_RATE_AGG_LMT_V1_8814B(x)                                \
+	(((x) >> BIT_SHIFT_RA_TRY_RATE_AGG_LMT_V1_8814B) &                     \
+	 BIT_MASK_RA_TRY_RATE_AGG_LMT_V1_8814B)
+#define BIT_SET_RA_TRY_RATE_AGG_LMT_V1_8814B(x, v)                             \
+	(BIT_CLEAR_RA_TRY_RATE_AGG_LMT_V1_8814B(x) |                           \
+	 BIT_RA_TRY_RATE_AGG_LMT_V1_8814B(v))
+
+/* 2 REG_MACID_SLEEP_CTRL_8814B */
+
+#define BIT_SHIFT_DEBUG_PROTOCOL_8814B 24
+#define BIT_MASK_DEBUG_PROTOCOL_8814B 0xff
+#define BIT_DEBUG_PROTOCOL_8814B(x)                                            \
+	(((x) & BIT_MASK_DEBUG_PROTOCOL_8814B)                                 \
+	 << BIT_SHIFT_DEBUG_PROTOCOL_8814B)
+#define BITS_DEBUG_PROTOCOL_8814B                                              \
+	(BIT_MASK_DEBUG_PROTOCOL_8814B << BIT_SHIFT_DEBUG_PROTOCOL_8814B)
+#define BIT_CLEAR_DEBUG_PROTOCOL_8814B(x) ((x) & (~BITS_DEBUG_PROTOCOL_8814B))
+#define BIT_GET_DEBUG_PROTOCOL_8814B(x)                                        \
+	(((x) >> BIT_SHIFT_DEBUG_PROTOCOL_8814B) &                             \
+	 BIT_MASK_DEBUG_PROTOCOL_8814B)
+#define BIT_SET_DEBUG_PROTOCOL_8814B(x, v)                                     \
+	(BIT_CLEAR_DEBUG_PROTOCOL_8814B(x) | BIT_DEBUG_PROTOCOL_8814B(v))
+
+#define BIT_SHIFT_BCNQ_PGBNDY_RSEL_8814B 16
+#define BIT_MASK_BCNQ_PGBNDY_RSEL_8814B 0x7
+#define BIT_BCNQ_PGBNDY_RSEL_8814B(x)                                          \
+	(((x) & BIT_MASK_BCNQ_PGBNDY_RSEL_8814B)                               \
+	 << BIT_SHIFT_BCNQ_PGBNDY_RSEL_8814B)
+#define BITS_BCNQ_PGBNDY_RSEL_8814B                                            \
+	(BIT_MASK_BCNQ_PGBNDY_RSEL_8814B << BIT_SHIFT_BCNQ_PGBNDY_RSEL_8814B)
+#define BIT_CLEAR_BCNQ_PGBNDY_RSEL_8814B(x)                                    \
+	((x) & (~BITS_BCNQ_PGBNDY_RSEL_8814B))
+#define BIT_GET_BCNQ_PGBNDY_RSEL_8814B(x)                                      \
+	(((x) >> BIT_SHIFT_BCNQ_PGBNDY_RSEL_8814B) &                           \
+	 BIT_MASK_BCNQ_PGBNDY_RSEL_8814B)
+#define BIT_SET_BCNQ_PGBNDY_RSEL_8814B(x, v)                                   \
+	(BIT_CLEAR_BCNQ_PGBNDY_RSEL_8814B(x) | BIT_BCNQ_PGBNDY_RSEL_8814B(v))
+
+#define BIT_SHIFT_MACID_SLEEP_SEL_8814B 0
+#define BIT_MASK_MACID_SLEEP_SEL_8814B 0x7
+#define BIT_MACID_SLEEP_SEL_8814B(x)                                           \
+	(((x) & BIT_MASK_MACID_SLEEP_SEL_8814B)                                \
+	 << BIT_SHIFT_MACID_SLEEP_SEL_8814B)
+#define BITS_MACID_SLEEP_SEL_8814B                                             \
+	(BIT_MASK_MACID_SLEEP_SEL_8814B << BIT_SHIFT_MACID_SLEEP_SEL_8814B)
+#define BIT_CLEAR_MACID_SLEEP_SEL_8814B(x) ((x) & (~BITS_MACID_SLEEP_SEL_8814B))
+#define BIT_GET_MACID_SLEEP_SEL_8814B(x)                                       \
+	(((x) >> BIT_SHIFT_MACID_SLEEP_SEL_8814B) &                            \
+	 BIT_MASK_MACID_SLEEP_SEL_8814B)
+#define BIT_SET_MACID_SLEEP_SEL_8814B(x, v)                                    \
+	(BIT_CLEAR_MACID_SLEEP_SEL_8814B(x) | BIT_MACID_SLEEP_SEL_8814B(v))
+
+/* 2 REG_MACID_SLEEP_INFO_8814B */
+
+#define BIT_SHIFT_MACID_SLEEP_INFO_8814B 0
+#define BIT_MASK_MACID_SLEEP_INFO_8814B 0xffffffffL
+#define BIT_MACID_SLEEP_INFO_8814B(x)                                          \
+	(((x) & BIT_MASK_MACID_SLEEP_INFO_8814B)                               \
+	 << BIT_SHIFT_MACID_SLEEP_INFO_8814B)
+#define BITS_MACID_SLEEP_INFO_8814B                                            \
+	(BIT_MASK_MACID_SLEEP_INFO_8814B << BIT_SHIFT_MACID_SLEEP_INFO_8814B)
+#define BIT_CLEAR_MACID_SLEEP_INFO_8814B(x)                                    \
+	((x) & (~BITS_MACID_SLEEP_INFO_8814B))
+#define BIT_GET_MACID_SLEEP_INFO_8814B(x)                                      \
+	(((x) >> BIT_SHIFT_MACID_SLEEP_INFO_8814B) &                           \
+	 BIT_MASK_MACID_SLEEP_INFO_8814B)
+#define BIT_SET_MACID_SLEEP_INFO_8814B(x, v)                                   \
+	(BIT_CLEAR_MACID_SLEEP_INFO_8814B(x) | BIT_MACID_SLEEP_INFO_8814B(v))
+
+/* 2 REG_HW_SEQ0_8814B */
+
+#define BIT_SHIFT_HW_SSN_SEQ0_8814B 0
+#define BIT_MASK_HW_SSN_SEQ0_8814B 0xfff
+#define BIT_HW_SSN_SEQ0_8814B(x)                                               \
+	(((x) & BIT_MASK_HW_SSN_SEQ0_8814B) << BIT_SHIFT_HW_SSN_SEQ0_8814B)
+#define BITS_HW_SSN_SEQ0_8814B                                                 \
+	(BIT_MASK_HW_SSN_SEQ0_8814B << BIT_SHIFT_HW_SSN_SEQ0_8814B)
+#define BIT_CLEAR_HW_SSN_SEQ0_8814B(x) ((x) & (~BITS_HW_SSN_SEQ0_8814B))
+#define BIT_GET_HW_SSN_SEQ0_8814B(x)                                           \
+	(((x) >> BIT_SHIFT_HW_SSN_SEQ0_8814B) & BIT_MASK_HW_SSN_SEQ0_8814B)
+#define BIT_SET_HW_SSN_SEQ0_8814B(x, v)                                        \
+	(BIT_CLEAR_HW_SSN_SEQ0_8814B(x) | BIT_HW_SSN_SEQ0_8814B(v))
+
+/* 2 REG_HW_SEQ1_8814B */
+
+#define BIT_SHIFT_HW_SSN_SEQ1_8814B 0
+#define BIT_MASK_HW_SSN_SEQ1_8814B 0xfff
+#define BIT_HW_SSN_SEQ1_8814B(x)                                               \
+	(((x) & BIT_MASK_HW_SSN_SEQ1_8814B) << BIT_SHIFT_HW_SSN_SEQ1_8814B)
+#define BITS_HW_SSN_SEQ1_8814B                                                 \
+	(BIT_MASK_HW_SSN_SEQ1_8814B << BIT_SHIFT_HW_SSN_SEQ1_8814B)
+#define BIT_CLEAR_HW_SSN_SEQ1_8814B(x) ((x) & (~BITS_HW_SSN_SEQ1_8814B))
+#define BIT_GET_HW_SSN_SEQ1_8814B(x)                                           \
+	(((x) >> BIT_SHIFT_HW_SSN_SEQ1_8814B) & BIT_MASK_HW_SSN_SEQ1_8814B)
+#define BIT_SET_HW_SSN_SEQ1_8814B(x, v)                                        \
+	(BIT_CLEAR_HW_SSN_SEQ1_8814B(x) | BIT_HW_SSN_SEQ1_8814B(v))
+
+/* 2 REG_HW_SEQ2_8814B */
+
+#define BIT_SHIFT_HW_SSN_SEQ2_8814B 0
+#define BIT_MASK_HW_SSN_SEQ2_8814B 0xfff
+#define BIT_HW_SSN_SEQ2_8814B(x)                                               \
+	(((x) & BIT_MASK_HW_SSN_SEQ2_8814B) << BIT_SHIFT_HW_SSN_SEQ2_8814B)
+#define BITS_HW_SSN_SEQ2_8814B                                                 \
+	(BIT_MASK_HW_SSN_SEQ2_8814B << BIT_SHIFT_HW_SSN_SEQ2_8814B)
+#define BIT_CLEAR_HW_SSN_SEQ2_8814B(x) ((x) & (~BITS_HW_SSN_SEQ2_8814B))
+#define BIT_GET_HW_SSN_SEQ2_8814B(x)                                           \
+	(((x) >> BIT_SHIFT_HW_SSN_SEQ2_8814B) & BIT_MASK_HW_SSN_SEQ2_8814B)
+#define BIT_SET_HW_SSN_SEQ2_8814B(x, v)                                        \
+	(BIT_CLEAR_HW_SSN_SEQ2_8814B(x) | BIT_HW_SSN_SEQ2_8814B(v))
+
+/* 2 REG_HW_SEQ3_8814B */
+
+#define BIT_SHIFT_CSI_HWSEQ_SEL_8814B 12
+#define BIT_MASK_CSI_HWSEQ_SEL_8814B 0x3
+#define BIT_CSI_HWSEQ_SEL_8814B(x)                                             \
+	(((x) & BIT_MASK_CSI_HWSEQ_SEL_8814B) << BIT_SHIFT_CSI_HWSEQ_SEL_8814B)
+#define BITS_CSI_HWSEQ_SEL_8814B                                               \
+	(BIT_MASK_CSI_HWSEQ_SEL_8814B << BIT_SHIFT_CSI_HWSEQ_SEL_8814B)
+#define BIT_CLEAR_CSI_HWSEQ_SEL_8814B(x) ((x) & (~BITS_CSI_HWSEQ_SEL_8814B))
+#define BIT_GET_CSI_HWSEQ_SEL_8814B(x)                                         \
+	(((x) >> BIT_SHIFT_CSI_HWSEQ_SEL_8814B) & BIT_MASK_CSI_HWSEQ_SEL_8814B)
+#define BIT_SET_CSI_HWSEQ_SEL_8814B(x, v)                                      \
+	(BIT_CLEAR_CSI_HWSEQ_SEL_8814B(x) | BIT_CSI_HWSEQ_SEL_8814B(v))
+
+#define BIT_SHIFT_HW_SSN_SEQ3_8814B 0
+#define BIT_MASK_HW_SSN_SEQ3_8814B 0xfff
+#define BIT_HW_SSN_SEQ3_8814B(x)                                               \
+	(((x) & BIT_MASK_HW_SSN_SEQ3_8814B) << BIT_SHIFT_HW_SSN_SEQ3_8814B)
+#define BITS_HW_SSN_SEQ3_8814B                                                 \
+	(BIT_MASK_HW_SSN_SEQ3_8814B << BIT_SHIFT_HW_SSN_SEQ3_8814B)
+#define BIT_CLEAR_HW_SSN_SEQ3_8814B(x) ((x) & (~BITS_HW_SSN_SEQ3_8814B))
+#define BIT_GET_HW_SSN_SEQ3_8814B(x)                                           \
+	(((x) >> BIT_SHIFT_HW_SSN_SEQ3_8814B) & BIT_MASK_HW_SSN_SEQ3_8814B)
+#define BIT_SET_HW_SSN_SEQ3_8814B(x, v)                                        \
+	(BIT_CLEAR_HW_SSN_SEQ3_8814B(x) | BIT_HW_SSN_SEQ3_8814B(v))
+
+/* 2 REG_NOT_VALID_8814B */
+
+#define BIT_SHIFT_PTCL_TOTAL_PG_V3_8814B 0
+#define BIT_MASK_PTCL_TOTAL_PG_V3_8814B 0x1fff
+#define BIT_PTCL_TOTAL_PG_V3_8814B(x)                                          \
+	(((x) & BIT_MASK_PTCL_TOTAL_PG_V3_8814B)                               \
+	 << BIT_SHIFT_PTCL_TOTAL_PG_V3_8814B)
+#define BITS_PTCL_TOTAL_PG_V3_8814B                                            \
+	(BIT_MASK_PTCL_TOTAL_PG_V3_8814B << BIT_SHIFT_PTCL_TOTAL_PG_V3_8814B)
+#define BIT_CLEAR_PTCL_TOTAL_PG_V3_8814B(x)                                    \
+	((x) & (~BITS_PTCL_TOTAL_PG_V3_8814B))
+#define BIT_GET_PTCL_TOTAL_PG_V3_8814B(x)                                      \
+	(((x) >> BIT_SHIFT_PTCL_TOTAL_PG_V3_8814B) &                           \
+	 BIT_MASK_PTCL_TOTAL_PG_V3_8814B)
+#define BIT_SET_PTCL_TOTAL_PG_V3_8814B(x, v)                                   \
+	(BIT_CLEAR_PTCL_TOTAL_PG_V3_8814B(x) | BIT_PTCL_TOTAL_PG_V3_8814B(v))
+
+/* 2 REG_PTCL_ERR_STATUS_V1_8814B */
+#define BIT_MUARB_SEARCH_ERR_8814B BIT(14)
+#define BIT_MU_BFEN_ERR_8814B BIT(12)
+#define BIT_NDPA_DROPNULL_ERR_8814B BIT(11)
+#define BIT_NDPA_DROPPKT_ERR_8814B BIT(10)
+#define BIT_PTCL_PKYIN_ERR_8814B BIT(9)
+#define BIT_PTCL_QSELCNL_ERR_8814B BIT(8)
+#define BIT_PTCL_RATE_TABLE_INVALID_8814B BIT(7)
+#define BIT_FTM_T2R_ERROR_8814B BIT(6)
+#define BIT_TXTIMEOUT_ERR_8814B BIT(5)
+#define BIT_NULLPAGE_ERR_8814B BIT(4)
+#define BIT_CONTENTION_ERR_8814B BIT(3)
+#define BIT_HEADNULL_ERR_8814B BIT(2)
+#define BIT_OVERFLOW_ERR_8814B BIT(1)
+#define BIT_QUEUE_INDEX_ERR_8814B BIT(0)
+
+/* 2 REG_NULL_PKT_STATUS_V2_8814B */
+#define BIT_HIQ_DROP_8814B BIT(7)
+#define BIT_MGQ_DROP_8814B BIT(6)
+#define BIT_TX_NULL_1_V1_8814B BIT(1)
+#define BIT_TX_NULL_0_V1_8814B BIT(0)
+
+/* 2 REG_PRECNT_CTRL_8814B */
+#define BIT_EN_PRECNT_8814B BIT(11)
+
+#define BIT_SHIFT_PRECNT_TH_8814B 0
+#define BIT_MASK_PRECNT_TH_8814B 0x7ff
+#define BIT_PRECNT_TH_8814B(x)                                                 \
+	(((x) & BIT_MASK_PRECNT_TH_8814B) << BIT_SHIFT_PRECNT_TH_8814B)
+#define BITS_PRECNT_TH_8814B                                                   \
+	(BIT_MASK_PRECNT_TH_8814B << BIT_SHIFT_PRECNT_TH_8814B)
+#define BIT_CLEAR_PRECNT_TH_8814B(x) ((x) & (~BITS_PRECNT_TH_8814B))
+#define BIT_GET_PRECNT_TH_8814B(x)                                             \
+	(((x) >> BIT_SHIFT_PRECNT_TH_8814B) & BIT_MASK_PRECNT_TH_8814B)
+#define BIT_SET_PRECNT_TH_8814B(x, v)                                          \
+	(BIT_CLEAR_PRECNT_TH_8814B(x) | BIT_PRECNT_TH_8814B(v))
+
+/* 2 REG_NULL_PKT_STATUS_EXTEND_V1_8814B */
+#define BIT_CLI3_TX_NULL_1_V1_8814B BIT(7)
+#define BIT_CLI3_TX_NULL_0_V1_8814B BIT(6)
+#define BIT_CLI2_TX_NULL_1_V1_8814B BIT(5)
+#define BIT_CLI2_TX_NULL_0_V1_8814B BIT(4)
+#define BIT_CLI1_TX_NULL_1_V1_8814B BIT(3)
+#define BIT_CLI1_TX_NULL_0_V1_8814B BIT(2)
+#define BIT_CLI0_TX_NULL_1_V1_8814B BIT(1)
+#define BIT_CLI0_TX_NULL_0_V1_8814B BIT(0)
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_PTCL_DBG_V1_8814B */
+
+#define BIT_SHIFT_PTCL_DBG_8814B 0
+#define BIT_MASK_PTCL_DBG_8814B 0xffffffffL
+#define BIT_PTCL_DBG_8814B(x)                                                  \
+	(((x) & BIT_MASK_PTCL_DBG_8814B) << BIT_SHIFT_PTCL_DBG_8814B)
+#define BITS_PTCL_DBG_8814B                                                    \
+	(BIT_MASK_PTCL_DBG_8814B << BIT_SHIFT_PTCL_DBG_8814B)
+#define BIT_CLEAR_PTCL_DBG_8814B(x) ((x) & (~BITS_PTCL_DBG_8814B))
+#define BIT_GET_PTCL_DBG_8814B(x)                                              \
+	(((x) >> BIT_SHIFT_PTCL_DBG_8814B) & BIT_MASK_PTCL_DBG_8814B)
+#define BIT_SET_PTCL_DBG_8814B(x, v)                                           \
+	(BIT_CLEAR_PTCL_DBG_8814B(x) | BIT_PTCL_DBG_8814B(v))
+
+/* 2 REG_BT_POLLUTE_PKTCNT_8814B */
+
+#define BIT_SHIFT_BT_POLLUTE_PKTCNT_8814B 0
+#define BIT_MASK_BT_POLLUTE_PKTCNT_8814B 0xffff
+#define BIT_BT_POLLUTE_PKTCNT_8814B(x)                                         \
+	(((x) & BIT_MASK_BT_POLLUTE_PKTCNT_8814B)                              \
+	 << BIT_SHIFT_BT_POLLUTE_PKTCNT_8814B)
+#define BITS_BT_POLLUTE_PKTCNT_8814B                                           \
+	(BIT_MASK_BT_POLLUTE_PKTCNT_8814B << BIT_SHIFT_BT_POLLUTE_PKTCNT_8814B)
+#define BIT_CLEAR_BT_POLLUTE_PKTCNT_8814B(x)                                   \
+	((x) & (~BITS_BT_POLLUTE_PKTCNT_8814B))
+#define BIT_GET_BT_POLLUTE_PKTCNT_8814B(x)                                     \
+	(((x) >> BIT_SHIFT_BT_POLLUTE_PKTCNT_8814B) &                          \
+	 BIT_MASK_BT_POLLUTE_PKTCNT_8814B)
+#define BIT_SET_BT_POLLUTE_PKTCNT_8814B(x, v)                                  \
+	(BIT_CLEAR_BT_POLLUTE_PKTCNT_8814B(x) | BIT_BT_POLLUTE_PKTCNT_8814B(v))
+
+/* 2 REG_CPUMGQ_TIMER_CTRL2_8814B */
+
+#define BIT_SHIFT_TRI_HEAD_ADDR_8814B 16
+#define BIT_MASK_TRI_HEAD_ADDR_8814B 0xfff
+#define BIT_TRI_HEAD_ADDR_8814B(x)                                             \
+	(((x) & BIT_MASK_TRI_HEAD_ADDR_8814B) << BIT_SHIFT_TRI_HEAD_ADDR_8814B)
+#define BITS_TRI_HEAD_ADDR_8814B                                               \
+	(BIT_MASK_TRI_HEAD_ADDR_8814B << BIT_SHIFT_TRI_HEAD_ADDR_8814B)
+#define BIT_CLEAR_TRI_HEAD_ADDR_8814B(x) ((x) & (~BITS_TRI_HEAD_ADDR_8814B))
+#define BIT_GET_TRI_HEAD_ADDR_8814B(x)                                         \
+	(((x) >> BIT_SHIFT_TRI_HEAD_ADDR_8814B) & BIT_MASK_TRI_HEAD_ADDR_8814B)
+#define BIT_SET_TRI_HEAD_ADDR_8814B(x, v)                                      \
+	(BIT_CLEAR_TRI_HEAD_ADDR_8814B(x) | BIT_TRI_HEAD_ADDR_8814B(v))
+
+#define BIT_DROP_TH_EN_8814B BIT(8)
+
+#define BIT_SHIFT_DROP_TH_8814B 0
+#define BIT_MASK_DROP_TH_8814B 0xff
+#define BIT_DROP_TH_8814B(x)                                                   \
+	(((x) & BIT_MASK_DROP_TH_8814B) << BIT_SHIFT_DROP_TH_8814B)
+#define BITS_DROP_TH_8814B (BIT_MASK_DROP_TH_8814B << BIT_SHIFT_DROP_TH_8814B)
+#define BIT_CLEAR_DROP_TH_8814B(x) ((x) & (~BITS_DROP_TH_8814B))
+#define BIT_GET_DROP_TH_8814B(x)                                               \
+	(((x) >> BIT_SHIFT_DROP_TH_8814B) & BIT_MASK_DROP_TH_8814B)
+#define BIT_SET_DROP_TH_8814B(x, v)                                            \
+	(BIT_CLEAR_DROP_TH_8814B(x) | BIT_DROP_TH_8814B(v))
+
+/* 2 REG_PTCL_DBG_OUT_8814B */
+
+#define BIT_SHIFT_PTCL_DBG_OUT_8814B 0
+#define BIT_MASK_PTCL_DBG_OUT_8814B 0xffffffffL
+#define BIT_PTCL_DBG_OUT_8814B(x)                                              \
+	(((x) & BIT_MASK_PTCL_DBG_OUT_8814B) << BIT_SHIFT_PTCL_DBG_OUT_8814B)
+#define BITS_PTCL_DBG_OUT_8814B                                                \
+	(BIT_MASK_PTCL_DBG_OUT_8814B << BIT_SHIFT_PTCL_DBG_OUT_8814B)
+#define BIT_CLEAR_PTCL_DBG_OUT_8814B(x) ((x) & (~BITS_PTCL_DBG_OUT_8814B))
+#define BIT_GET_PTCL_DBG_OUT_8814B(x)                                          \
+	(((x) >> BIT_SHIFT_PTCL_DBG_OUT_8814B) & BIT_MASK_PTCL_DBG_OUT_8814B)
+#define BIT_SET_PTCL_DBG_OUT_8814B(x, v)                                       \
+	(BIT_CLEAR_PTCL_DBG_OUT_8814B(x) | BIT_PTCL_DBG_OUT_8814B(v))
+
+/* 2 REG_DUMMY_PAGE4_V1_8814B */
+
+/* 2 REG_DUMMY_PAGE4_1_8814B */
+
+/* 2 REG_MU_OFFSET_8814B */
+
+#define BIT_SHIFT_MU_RATETABLE_OFFSET_8814B 16
+#define BIT_MASK_MU_RATETABLE_OFFSET_8814B 0x1ff
+#define BIT_MU_RATETABLE_OFFSET_8814B(x)                                       \
+	(((x) & BIT_MASK_MU_RATETABLE_OFFSET_8814B)                            \
+	 << BIT_SHIFT_MU_RATETABLE_OFFSET_8814B)
+#define BITS_MU_RATETABLE_OFFSET_8814B                                         \
+	(BIT_MASK_MU_RATETABLE_OFFSET_8814B                                    \
+	 << BIT_SHIFT_MU_RATETABLE_OFFSET_8814B)
+#define BIT_CLEAR_MU_RATETABLE_OFFSET_8814B(x)                                 \
+	((x) & (~BITS_MU_RATETABLE_OFFSET_8814B))
+#define BIT_GET_MU_RATETABLE_OFFSET_8814B(x)                                   \
+	(((x) >> BIT_SHIFT_MU_RATETABLE_OFFSET_8814B) &                        \
+	 BIT_MASK_MU_RATETABLE_OFFSET_8814B)
+#define BIT_SET_MU_RATETABLE_OFFSET_8814B(x, v)                                \
+	(BIT_CLEAR_MU_RATETABLE_OFFSET_8814B(x) |                              \
+	 BIT_MU_RATETABLE_OFFSET_8814B(v))
+
+#define BIT_SHIFT_MU_SCORETABLE_OFFSET_8814B 0
+#define BIT_MASK_MU_SCORETABLE_OFFSET_8814B 0x1ff
+#define BIT_MU_SCORETABLE_OFFSET_8814B(x)                                      \
+	(((x) & BIT_MASK_MU_SCORETABLE_OFFSET_8814B)                           \
+	 << BIT_SHIFT_MU_SCORETABLE_OFFSET_8814B)
+#define BITS_MU_SCORETABLE_OFFSET_8814B                                        \
+	(BIT_MASK_MU_SCORETABLE_OFFSET_8814B                                   \
+	 << BIT_SHIFT_MU_SCORETABLE_OFFSET_8814B)
+#define BIT_CLEAR_MU_SCORETABLE_OFFSET_8814B(x)                                \
+	((x) & (~BITS_MU_SCORETABLE_OFFSET_8814B))
+#define BIT_GET_MU_SCORETABLE_OFFSET_8814B(x)                                  \
+	(((x) >> BIT_SHIFT_MU_SCORETABLE_OFFSET_8814B) &                       \
+	 BIT_MASK_MU_SCORETABLE_OFFSET_8814B)
+#define BIT_SET_MU_SCORETABLE_OFFSET_8814B(x, v)                               \
+	(BIT_CLEAR_MU_SCORETABLE_OFFSET_8814B(x) |                             \
+	 BIT_MU_SCORETABLE_OFFSET_8814B(v))
+
+/* 2 REG_BF0_TIME_SETTING_8814B */
+#define BIT_BF0_TIMER_SET_8814B BIT(31)
+#define BIT_BF0_TIMER_CLR_8814B BIT(30)
+#define BIT_BF0_UPDATE_EN_8814B BIT(29)
+#define BIT_BF0_TIMER_EN_8814B BIT(28)
+
+#define BIT_SHIFT_BF0_PRETIME_OVER_8814B 16
+#define BIT_MASK_BF0_PRETIME_OVER_8814B 0xfff
+#define BIT_BF0_PRETIME_OVER_8814B(x)                                          \
+	(((x) & BIT_MASK_BF0_PRETIME_OVER_8814B)                               \
+	 << BIT_SHIFT_BF0_PRETIME_OVER_8814B)
+#define BITS_BF0_PRETIME_OVER_8814B                                            \
+	(BIT_MASK_BF0_PRETIME_OVER_8814B << BIT_SHIFT_BF0_PRETIME_OVER_8814B)
+#define BIT_CLEAR_BF0_PRETIME_OVER_8814B(x)                                    \
+	((x) & (~BITS_BF0_PRETIME_OVER_8814B))
+#define BIT_GET_BF0_PRETIME_OVER_8814B(x)                                      \
+	(((x) >> BIT_SHIFT_BF0_PRETIME_OVER_8814B) &                           \
+	 BIT_MASK_BF0_PRETIME_OVER_8814B)
+#define BIT_SET_BF0_PRETIME_OVER_8814B(x, v)                                   \
+	(BIT_CLEAR_BF0_PRETIME_OVER_8814B(x) | BIT_BF0_PRETIME_OVER_8814B(v))
+
+#define BIT_SHIFT_BF0_LIFETIME_8814B 0
+#define BIT_MASK_BF0_LIFETIME_8814B 0xffff
+#define BIT_BF0_LIFETIME_8814B(x)                                              \
+	(((x) & BIT_MASK_BF0_LIFETIME_8814B) << BIT_SHIFT_BF0_LIFETIME_8814B)
+#define BITS_BF0_LIFETIME_8814B                                                \
+	(BIT_MASK_BF0_LIFETIME_8814B << BIT_SHIFT_BF0_LIFETIME_8814B)
+#define BIT_CLEAR_BF0_LIFETIME_8814B(x) ((x) & (~BITS_BF0_LIFETIME_8814B))
+#define BIT_GET_BF0_LIFETIME_8814B(x)                                          \
+	(((x) >> BIT_SHIFT_BF0_LIFETIME_8814B) & BIT_MASK_BF0_LIFETIME_8814B)
+#define BIT_SET_BF0_LIFETIME_8814B(x, v)                                       \
+	(BIT_CLEAR_BF0_LIFETIME_8814B(x) | BIT_BF0_LIFETIME_8814B(v))
+
+/* 2 REG_BF1_TIME_SETTING_8814B */
+#define BIT_BF1_TIMER_SET_8814B BIT(31)
+#define BIT_BF1_TIMER_CLR_8814B BIT(30)
+#define BIT_BF1_UPDATE_EN_8814B BIT(29)
+#define BIT_BF1_TIMER_EN_8814B BIT(28)
+
+#define BIT_SHIFT_BF1_PRETIME_OVER_8814B 16
+#define BIT_MASK_BF1_PRETIME_OVER_8814B 0xfff
+#define BIT_BF1_PRETIME_OVER_8814B(x)                                          \
+	(((x) & BIT_MASK_BF1_PRETIME_OVER_8814B)                               \
+	 << BIT_SHIFT_BF1_PRETIME_OVER_8814B)
+#define BITS_BF1_PRETIME_OVER_8814B                                            \
+	(BIT_MASK_BF1_PRETIME_OVER_8814B << BIT_SHIFT_BF1_PRETIME_OVER_8814B)
+#define BIT_CLEAR_BF1_PRETIME_OVER_8814B(x)                                    \
+	((x) & (~BITS_BF1_PRETIME_OVER_8814B))
+#define BIT_GET_BF1_PRETIME_OVER_8814B(x)                                      \
+	(((x) >> BIT_SHIFT_BF1_PRETIME_OVER_8814B) &                           \
+	 BIT_MASK_BF1_PRETIME_OVER_8814B)
+#define BIT_SET_BF1_PRETIME_OVER_8814B(x, v)                                   \
+	(BIT_CLEAR_BF1_PRETIME_OVER_8814B(x) | BIT_BF1_PRETIME_OVER_8814B(v))
+
+#define BIT_SHIFT_BF1_LIFETIME_8814B 0
+#define BIT_MASK_BF1_LIFETIME_8814B 0xffff
+#define BIT_BF1_LIFETIME_8814B(x)                                              \
+	(((x) & BIT_MASK_BF1_LIFETIME_8814B) << BIT_SHIFT_BF1_LIFETIME_8814B)
+#define BITS_BF1_LIFETIME_8814B                                                \
+	(BIT_MASK_BF1_LIFETIME_8814B << BIT_SHIFT_BF1_LIFETIME_8814B)
+#define BIT_CLEAR_BF1_LIFETIME_8814B(x) ((x) & (~BITS_BF1_LIFETIME_8814B))
+#define BIT_GET_BF1_LIFETIME_8814B(x)                                          \
+	(((x) >> BIT_SHIFT_BF1_LIFETIME_8814B) & BIT_MASK_BF1_LIFETIME_8814B)
+#define BIT_SET_BF1_LIFETIME_8814B(x, v)                                       \
+	(BIT_CLEAR_BF1_LIFETIME_8814B(x) | BIT_BF1_LIFETIME_8814B(v))
+
+/* 2 REG_BF_TIMEOUT_EN_8814B */
+#define BIT_EN_VHT_LDPC_8814B BIT(9)
+#define BIT_EN_HT_LDPC_8814B BIT(8)
+#define BIT_BF1_TIMEOUT_EN_8814B BIT(1)
+#define BIT_BF0_TIMEOUT_EN_8814B BIT(0)
+
+/* 2 REG_MACID_RELEASE_INFO_8814B */
+
+#define BIT_SHIFT_MACID_RELEASE_INFO_8814B 0
+#define BIT_MASK_MACID_RELEASE_INFO_8814B 0xffffffffL
+#define BIT_MACID_RELEASE_INFO_8814B(x)                                        \
+	(((x) & BIT_MASK_MACID_RELEASE_INFO_8814B)                             \
+	 << BIT_SHIFT_MACID_RELEASE_INFO_8814B)
+#define BITS_MACID_RELEASE_INFO_8814B                                          \
+	(BIT_MASK_MACID_RELEASE_INFO_8814B                                     \
+	 << BIT_SHIFT_MACID_RELEASE_INFO_8814B)
+#define BIT_CLEAR_MACID_RELEASE_INFO_8814B(x)                                  \
+	((x) & (~BITS_MACID_RELEASE_INFO_8814B))
+#define BIT_GET_MACID_RELEASE_INFO_8814B(x)                                    \
+	(((x) >> BIT_SHIFT_MACID_RELEASE_INFO_8814B) &                         \
+	 BIT_MASK_MACID_RELEASE_INFO_8814B)
+#define BIT_SET_MACID_RELEASE_INFO_8814B(x, v)                                 \
+	(BIT_CLEAR_MACID_RELEASE_INFO_8814B(x) |                               \
+	 BIT_MACID_RELEASE_INFO_8814B(v))
+
+/* 2 REG_MACID_RELEASE_SUCCESS_INFO_8814B */
+
+#define BIT_SHIFT_MACID_RELEASE_SUCCESS_INFO_8814B 0
+#define BIT_MASK_MACID_RELEASE_SUCCESS_INFO_8814B 0xffffffffL
+#define BIT_MACID_RELEASE_SUCCESS_INFO_8814B(x)                                \
+	(((x) & BIT_MASK_MACID_RELEASE_SUCCESS_INFO_8814B)                     \
+	 << BIT_SHIFT_MACID_RELEASE_SUCCESS_INFO_8814B)
+#define BITS_MACID_RELEASE_SUCCESS_INFO_8814B                                  \
+	(BIT_MASK_MACID_RELEASE_SUCCESS_INFO_8814B                             \
+	 << BIT_SHIFT_MACID_RELEASE_SUCCESS_INFO_8814B)
+#define BIT_CLEAR_MACID_RELEASE_SUCCESS_INFO_8814B(x)                          \
+	((x) & (~BITS_MACID_RELEASE_SUCCESS_INFO_8814B))
+#define BIT_GET_MACID_RELEASE_SUCCESS_INFO_8814B(x)                            \
+	(((x) >> BIT_SHIFT_MACID_RELEASE_SUCCESS_INFO_8814B) &                 \
+	 BIT_MASK_MACID_RELEASE_SUCCESS_INFO_8814B)
+#define BIT_SET_MACID_RELEASE_SUCCESS_INFO_8814B(x, v)                         \
+	(BIT_CLEAR_MACID_RELEASE_SUCCESS_INFO_8814B(x) |                       \
+	 BIT_MACID_RELEASE_SUCCESS_INFO_8814B(v))
+
+/* 2 REG_MACID_RELEASE_CTRL_8814B */
+
+#define BIT_SHIFT_MACID_RELEASE_SEL_8814B 24
+#define BIT_MASK_MACID_RELEASE_SEL_8814B 0x7
+#define BIT_MACID_RELEASE_SEL_8814B(x)                                         \
+	(((x) & BIT_MASK_MACID_RELEASE_SEL_8814B)                              \
+	 << BIT_SHIFT_MACID_RELEASE_SEL_8814B)
+#define BITS_MACID_RELEASE_SEL_8814B                                           \
+	(BIT_MASK_MACID_RELEASE_SEL_8814B << BIT_SHIFT_MACID_RELEASE_SEL_8814B)
+#define BIT_CLEAR_MACID_RELEASE_SEL_8814B(x)                                   \
+	((x) & (~BITS_MACID_RELEASE_SEL_8814B))
+#define BIT_GET_MACID_RELEASE_SEL_8814B(x)                                     \
+	(((x) >> BIT_SHIFT_MACID_RELEASE_SEL_8814B) &                          \
+	 BIT_MASK_MACID_RELEASE_SEL_8814B)
+#define BIT_SET_MACID_RELEASE_SEL_8814B(x, v)                                  \
+	(BIT_CLEAR_MACID_RELEASE_SEL_8814B(x) | BIT_MACID_RELEASE_SEL_8814B(v))
+
+#define BIT_SHIFT_MACID_RELEASE_CLEAR_OFFSET_8814B 16
+#define BIT_MASK_MACID_RELEASE_CLEAR_OFFSET_8814B 0xff
+#define BIT_MACID_RELEASE_CLEAR_OFFSET_8814B(x)                                \
+	(((x) & BIT_MASK_MACID_RELEASE_CLEAR_OFFSET_8814B)                     \
+	 << BIT_SHIFT_MACID_RELEASE_CLEAR_OFFSET_8814B)
+#define BITS_MACID_RELEASE_CLEAR_OFFSET_8814B                                  \
+	(BIT_MASK_MACID_RELEASE_CLEAR_OFFSET_8814B                             \
+	 << BIT_SHIFT_MACID_RELEASE_CLEAR_OFFSET_8814B)
+#define BIT_CLEAR_MACID_RELEASE_CLEAR_OFFSET_8814B(x)                          \
+	((x) & (~BITS_MACID_RELEASE_CLEAR_OFFSET_8814B))
+#define BIT_GET_MACID_RELEASE_CLEAR_OFFSET_8814B(x)                            \
+	(((x) >> BIT_SHIFT_MACID_RELEASE_CLEAR_OFFSET_8814B) &                 \
+	 BIT_MASK_MACID_RELEASE_CLEAR_OFFSET_8814B)
+#define BIT_SET_MACID_RELEASE_CLEAR_OFFSET_8814B(x, v)                         \
+	(BIT_CLEAR_MACID_RELEASE_CLEAR_OFFSET_8814B(x) |                       \
+	 BIT_MACID_RELEASE_CLEAR_OFFSET_8814B(v))
+
+#define BIT_MACID_RELEASE_VALUE_8814B BIT(8)
+
+#define BIT_SHIFT_MACID_RELEASE_OFFSET_8814B 0
+#define BIT_MASK_MACID_RELEASE_OFFSET_8814B 0xff
+#define BIT_MACID_RELEASE_OFFSET_8814B(x)                                      \
+	(((x) & BIT_MASK_MACID_RELEASE_OFFSET_8814B)                           \
+	 << BIT_SHIFT_MACID_RELEASE_OFFSET_8814B)
+#define BITS_MACID_RELEASE_OFFSET_8814B                                        \
+	(BIT_MASK_MACID_RELEASE_OFFSET_8814B                                   \
+	 << BIT_SHIFT_MACID_RELEASE_OFFSET_8814B)
+#define BIT_CLEAR_MACID_RELEASE_OFFSET_8814B(x)                                \
+	((x) & (~BITS_MACID_RELEASE_OFFSET_8814B))
+#define BIT_GET_MACID_RELEASE_OFFSET_8814B(x)                                  \
+	(((x) >> BIT_SHIFT_MACID_RELEASE_OFFSET_8814B) &                       \
+	 BIT_MASK_MACID_RELEASE_OFFSET_8814B)
+#define BIT_SET_MACID_RELEASE_OFFSET_8814B(x, v)                               \
+	(BIT_CLEAR_MACID_RELEASE_OFFSET_8814B(x) |                             \
+	 BIT_MACID_RELEASE_OFFSET_8814B(v))
+
+/* 2 REG_FAST_EDCA_VOVI_SETTING_8814B */
+
+#define BIT_SHIFT_VI_FAST_EDCA_TO_8814B 24
+#define BIT_MASK_VI_FAST_EDCA_TO_8814B 0xff
+#define BIT_VI_FAST_EDCA_TO_8814B(x)                                           \
+	(((x) & BIT_MASK_VI_FAST_EDCA_TO_8814B)                                \
+	 << BIT_SHIFT_VI_FAST_EDCA_TO_8814B)
+#define BITS_VI_FAST_EDCA_TO_8814B                                             \
+	(BIT_MASK_VI_FAST_EDCA_TO_8814B << BIT_SHIFT_VI_FAST_EDCA_TO_8814B)
+#define BIT_CLEAR_VI_FAST_EDCA_TO_8814B(x) ((x) & (~BITS_VI_FAST_EDCA_TO_8814B))
+#define BIT_GET_VI_FAST_EDCA_TO_8814B(x)                                       \
+	(((x) >> BIT_SHIFT_VI_FAST_EDCA_TO_8814B) &                            \
+	 BIT_MASK_VI_FAST_EDCA_TO_8814B)
+#define BIT_SET_VI_FAST_EDCA_TO_8814B(x, v)                                    \
+	(BIT_CLEAR_VI_FAST_EDCA_TO_8814B(x) | BIT_VI_FAST_EDCA_TO_8814B(v))
+
+#define BIT_VI_THRESHOLD_SEL_8814B BIT(23)
+
+#define BIT_SHIFT_VI_FAST_EDCA_PKT_TH_8814B 16
+#define BIT_MASK_VI_FAST_EDCA_PKT_TH_8814B 0x7f
+#define BIT_VI_FAST_EDCA_PKT_TH_8814B(x)                                       \
+	(((x) & BIT_MASK_VI_FAST_EDCA_PKT_TH_8814B)                            \
+	 << BIT_SHIFT_VI_FAST_EDCA_PKT_TH_8814B)
+#define BITS_VI_FAST_EDCA_PKT_TH_8814B                                         \
+	(BIT_MASK_VI_FAST_EDCA_PKT_TH_8814B                                    \
+	 << BIT_SHIFT_VI_FAST_EDCA_PKT_TH_8814B)
+#define BIT_CLEAR_VI_FAST_EDCA_PKT_TH_8814B(x)                                 \
+	((x) & (~BITS_VI_FAST_EDCA_PKT_TH_8814B))
+#define BIT_GET_VI_FAST_EDCA_PKT_TH_8814B(x)                                   \
+	(((x) >> BIT_SHIFT_VI_FAST_EDCA_PKT_TH_8814B) &                        \
+	 BIT_MASK_VI_FAST_EDCA_PKT_TH_8814B)
+#define BIT_SET_VI_FAST_EDCA_PKT_TH_8814B(x, v)                                \
+	(BIT_CLEAR_VI_FAST_EDCA_PKT_TH_8814B(x) |                              \
+	 BIT_VI_FAST_EDCA_PKT_TH_8814B(v))
+
+#define BIT_SHIFT_VO_FAST_EDCA_TO_8814B 8
+#define BIT_MASK_VO_FAST_EDCA_TO_8814B 0xff
+#define BIT_VO_FAST_EDCA_TO_8814B(x)                                           \
+	(((x) & BIT_MASK_VO_FAST_EDCA_TO_8814B)                                \
+	 << BIT_SHIFT_VO_FAST_EDCA_TO_8814B)
+#define BITS_VO_FAST_EDCA_TO_8814B                                             \
+	(BIT_MASK_VO_FAST_EDCA_TO_8814B << BIT_SHIFT_VO_FAST_EDCA_TO_8814B)
+#define BIT_CLEAR_VO_FAST_EDCA_TO_8814B(x) ((x) & (~BITS_VO_FAST_EDCA_TO_8814B))
+#define BIT_GET_VO_FAST_EDCA_TO_8814B(x)                                       \
+	(((x) >> BIT_SHIFT_VO_FAST_EDCA_TO_8814B) &                            \
+	 BIT_MASK_VO_FAST_EDCA_TO_8814B)
+#define BIT_SET_VO_FAST_EDCA_TO_8814B(x, v)                                    \
+	(BIT_CLEAR_VO_FAST_EDCA_TO_8814B(x) | BIT_VO_FAST_EDCA_TO_8814B(v))
+
+#define BIT_VO_THRESHOLD_SEL_8814B BIT(7)
+
+#define BIT_SHIFT_VO_FAST_EDCA_PKT_TH_8814B 0
+#define BIT_MASK_VO_FAST_EDCA_PKT_TH_8814B 0x7f
+#define BIT_VO_FAST_EDCA_PKT_TH_8814B(x)                                       \
+	(((x) & BIT_MASK_VO_FAST_EDCA_PKT_TH_8814B)                            \
+	 << BIT_SHIFT_VO_FAST_EDCA_PKT_TH_8814B)
+#define BITS_VO_FAST_EDCA_PKT_TH_8814B                                         \
+	(BIT_MASK_VO_FAST_EDCA_PKT_TH_8814B                                    \
+	 << BIT_SHIFT_VO_FAST_EDCA_PKT_TH_8814B)
+#define BIT_CLEAR_VO_FAST_EDCA_PKT_TH_8814B(x)                                 \
+	((x) & (~BITS_VO_FAST_EDCA_PKT_TH_8814B))
+#define BIT_GET_VO_FAST_EDCA_PKT_TH_8814B(x)                                   \
+	(((x) >> BIT_SHIFT_VO_FAST_EDCA_PKT_TH_8814B) &                        \
+	 BIT_MASK_VO_FAST_EDCA_PKT_TH_8814B)
+#define BIT_SET_VO_FAST_EDCA_PKT_TH_8814B(x, v)                                \
+	(BIT_CLEAR_VO_FAST_EDCA_PKT_TH_8814B(x) |                              \
+	 BIT_VO_FAST_EDCA_PKT_TH_8814B(v))
+
+/* 2 REG_FAST_EDCA_BEBK_SETTING_8814B */
+
+#define BIT_SHIFT_BK_FAST_EDCA_TO_8814B 24
+#define BIT_MASK_BK_FAST_EDCA_TO_8814B 0xff
+#define BIT_BK_FAST_EDCA_TO_8814B(x)                                           \
+	(((x) & BIT_MASK_BK_FAST_EDCA_TO_8814B)                                \
+	 << BIT_SHIFT_BK_FAST_EDCA_TO_8814B)
+#define BITS_BK_FAST_EDCA_TO_8814B                                             \
+	(BIT_MASK_BK_FAST_EDCA_TO_8814B << BIT_SHIFT_BK_FAST_EDCA_TO_8814B)
+#define BIT_CLEAR_BK_FAST_EDCA_TO_8814B(x) ((x) & (~BITS_BK_FAST_EDCA_TO_8814B))
+#define BIT_GET_BK_FAST_EDCA_TO_8814B(x)                                       \
+	(((x) >> BIT_SHIFT_BK_FAST_EDCA_TO_8814B) &                            \
+	 BIT_MASK_BK_FAST_EDCA_TO_8814B)
+#define BIT_SET_BK_FAST_EDCA_TO_8814B(x, v)                                    \
+	(BIT_CLEAR_BK_FAST_EDCA_TO_8814B(x) | BIT_BK_FAST_EDCA_TO_8814B(v))
+
+#define BIT_BK_THRESHOLD_SEL_8814B BIT(23)
+
+#define BIT_SHIFT_BK_FAST_EDCA_PKT_TH_8814B 16
+#define BIT_MASK_BK_FAST_EDCA_PKT_TH_8814B 0x7f
+#define BIT_BK_FAST_EDCA_PKT_TH_8814B(x)                                       \
+	(((x) & BIT_MASK_BK_FAST_EDCA_PKT_TH_8814B)                            \
+	 << BIT_SHIFT_BK_FAST_EDCA_PKT_TH_8814B)
+#define BITS_BK_FAST_EDCA_PKT_TH_8814B                                         \
+	(BIT_MASK_BK_FAST_EDCA_PKT_TH_8814B                                    \
+	 << BIT_SHIFT_BK_FAST_EDCA_PKT_TH_8814B)
+#define BIT_CLEAR_BK_FAST_EDCA_PKT_TH_8814B(x)                                 \
+	((x) & (~BITS_BK_FAST_EDCA_PKT_TH_8814B))
+#define BIT_GET_BK_FAST_EDCA_PKT_TH_8814B(x)                                   \
+	(((x) >> BIT_SHIFT_BK_FAST_EDCA_PKT_TH_8814B) &                        \
+	 BIT_MASK_BK_FAST_EDCA_PKT_TH_8814B)
+#define BIT_SET_BK_FAST_EDCA_PKT_TH_8814B(x, v)                                \
+	(BIT_CLEAR_BK_FAST_EDCA_PKT_TH_8814B(x) |                              \
+	 BIT_BK_FAST_EDCA_PKT_TH_8814B(v))
+
+#define BIT_SHIFT_BE_FAST_EDCA_TO_8814B 8
+#define BIT_MASK_BE_FAST_EDCA_TO_8814B 0xff
+#define BIT_BE_FAST_EDCA_TO_8814B(x)                                           \
+	(((x) & BIT_MASK_BE_FAST_EDCA_TO_8814B)                                \
+	 << BIT_SHIFT_BE_FAST_EDCA_TO_8814B)
+#define BITS_BE_FAST_EDCA_TO_8814B                                             \
+	(BIT_MASK_BE_FAST_EDCA_TO_8814B << BIT_SHIFT_BE_FAST_EDCA_TO_8814B)
+#define BIT_CLEAR_BE_FAST_EDCA_TO_8814B(x) ((x) & (~BITS_BE_FAST_EDCA_TO_8814B))
+#define BIT_GET_BE_FAST_EDCA_TO_8814B(x)                                       \
+	(((x) >> BIT_SHIFT_BE_FAST_EDCA_TO_8814B) &                            \
+	 BIT_MASK_BE_FAST_EDCA_TO_8814B)
+#define BIT_SET_BE_FAST_EDCA_TO_8814B(x, v)                                    \
+	(BIT_CLEAR_BE_FAST_EDCA_TO_8814B(x) | BIT_BE_FAST_EDCA_TO_8814B(v))
+
+#define BIT_BE_THRESHOLD_SEL_8814B BIT(7)
+
+#define BIT_SHIFT_BE_FAST_EDCA_PKT_TH_8814B 0
+#define BIT_MASK_BE_FAST_EDCA_PKT_TH_8814B 0x7f
+#define BIT_BE_FAST_EDCA_PKT_TH_8814B(x)                                       \
+	(((x) & BIT_MASK_BE_FAST_EDCA_PKT_TH_8814B)                            \
+	 << BIT_SHIFT_BE_FAST_EDCA_PKT_TH_8814B)
+#define BITS_BE_FAST_EDCA_PKT_TH_8814B                                         \
+	(BIT_MASK_BE_FAST_EDCA_PKT_TH_8814B                                    \
+	 << BIT_SHIFT_BE_FAST_EDCA_PKT_TH_8814B)
+#define BIT_CLEAR_BE_FAST_EDCA_PKT_TH_8814B(x)                                 \
+	((x) & (~BITS_BE_FAST_EDCA_PKT_TH_8814B))
+#define BIT_GET_BE_FAST_EDCA_PKT_TH_8814B(x)                                   \
+	(((x) >> BIT_SHIFT_BE_FAST_EDCA_PKT_TH_8814B) &                        \
+	 BIT_MASK_BE_FAST_EDCA_PKT_TH_8814B)
+#define BIT_SET_BE_FAST_EDCA_PKT_TH_8814B(x, v)                                \
+	(BIT_CLEAR_BE_FAST_EDCA_PKT_TH_8814B(x) |                              \
+	 BIT_BE_FAST_EDCA_PKT_TH_8814B(v))
+
+/* 2 REG_MACID_DROP_INFO_8814B */
+
+#define BIT_SHIFT_MACID_DROP_INFO_8814B 0
+#define BIT_MASK_MACID_DROP_INFO_8814B 0xffffffffL
+#define BIT_MACID_DROP_INFO_8814B(x)                                           \
+	(((x) & BIT_MASK_MACID_DROP_INFO_8814B)                                \
+	 << BIT_SHIFT_MACID_DROP_INFO_8814B)
+#define BITS_MACID_DROP_INFO_8814B                                             \
+	(BIT_MASK_MACID_DROP_INFO_8814B << BIT_SHIFT_MACID_DROP_INFO_8814B)
+#define BIT_CLEAR_MACID_DROP_INFO_8814B(x) ((x) & (~BITS_MACID_DROP_INFO_8814B))
+#define BIT_GET_MACID_DROP_INFO_8814B(x)                                       \
+	(((x) >> BIT_SHIFT_MACID_DROP_INFO_8814B) &                            \
+	 BIT_MASK_MACID_DROP_INFO_8814B)
+#define BIT_SET_MACID_DROP_INFO_8814B(x, v)                                    \
+	(BIT_CLEAR_MACID_DROP_INFO_8814B(x) | BIT_MACID_DROP_INFO_8814B(v))
+
+/* 2 REG_MACID_DROP_CTRL_8814B */
+
+#define BIT_SHIFT_MACID_DROP_SEL_8814B 0
+#define BIT_MASK_MACID_DROP_SEL_8814B 0x7
+#define BIT_MACID_DROP_SEL_8814B(x)                                            \
+	(((x) & BIT_MASK_MACID_DROP_SEL_8814B)                                 \
+	 << BIT_SHIFT_MACID_DROP_SEL_8814B)
+#define BITS_MACID_DROP_SEL_8814B                                              \
+	(BIT_MASK_MACID_DROP_SEL_8814B << BIT_SHIFT_MACID_DROP_SEL_8814B)
+#define BIT_CLEAR_MACID_DROP_SEL_8814B(x) ((x) & (~BITS_MACID_DROP_SEL_8814B))
+#define BIT_GET_MACID_DROP_SEL_8814B(x)                                        \
+	(((x) >> BIT_SHIFT_MACID_DROP_SEL_8814B) &                             \
+	 BIT_MASK_MACID_DROP_SEL_8814B)
+#define BIT_SET_MACID_DROP_SEL_8814B(x, v)                                     \
+	(BIT_CLEAR_MACID_DROP_SEL_8814B(x) | BIT_MACID_DROP_SEL_8814B(v))
+
+/* 2 REG_MGQ_FIFO_WRITE_POINTER_8814B */
+#define BIT_MGQ_FIFO_OV_8814B BIT(7)
+#define BIT_MGQ_FIFO_WPTR_ERROR_8814B BIT(6)
+#define BIT_EN_MGQ_FIFO_LIFETIME_8814B BIT(5)
+
+#define BIT_SHIFT_MGQ_FIFO_WPTR_8814B 0
+#define BIT_MASK_MGQ_FIFO_WPTR_8814B 0x1f
+#define BIT_MGQ_FIFO_WPTR_8814B(x)                                             \
+	(((x) & BIT_MASK_MGQ_FIFO_WPTR_8814B) << BIT_SHIFT_MGQ_FIFO_WPTR_8814B)
+#define BITS_MGQ_FIFO_WPTR_8814B                                               \
+	(BIT_MASK_MGQ_FIFO_WPTR_8814B << BIT_SHIFT_MGQ_FIFO_WPTR_8814B)
+#define BIT_CLEAR_MGQ_FIFO_WPTR_8814B(x) ((x) & (~BITS_MGQ_FIFO_WPTR_8814B))
+#define BIT_GET_MGQ_FIFO_WPTR_8814B(x)                                         \
+	(((x) >> BIT_SHIFT_MGQ_FIFO_WPTR_8814B) & BIT_MASK_MGQ_FIFO_WPTR_8814B)
+#define BIT_SET_MGQ_FIFO_WPTR_8814B(x, v)                                      \
+	(BIT_CLEAR_MGQ_FIFO_WPTR_8814B(x) | BIT_MGQ_FIFO_WPTR_8814B(v))
+
+/* 2 REG_MGQ_FIFO_READ_POINTER_8814B */
+
+#define BIT_SHIFT_MGQ_FIFO_SIZE_8814B 14
+#define BIT_MASK_MGQ_FIFO_SIZE_8814B 0x3
+#define BIT_MGQ_FIFO_SIZE_8814B(x)                                             \
+	(((x) & BIT_MASK_MGQ_FIFO_SIZE_8814B) << BIT_SHIFT_MGQ_FIFO_SIZE_8814B)
+#define BITS_MGQ_FIFO_SIZE_8814B                                               \
+	(BIT_MASK_MGQ_FIFO_SIZE_8814B << BIT_SHIFT_MGQ_FIFO_SIZE_8814B)
+#define BIT_CLEAR_MGQ_FIFO_SIZE_8814B(x) ((x) & (~BITS_MGQ_FIFO_SIZE_8814B))
+#define BIT_GET_MGQ_FIFO_SIZE_8814B(x)                                         \
+	(((x) >> BIT_SHIFT_MGQ_FIFO_SIZE_8814B) & BIT_MASK_MGQ_FIFO_SIZE_8814B)
+#define BIT_SET_MGQ_FIFO_SIZE_8814B(x, v)                                      \
+	(BIT_CLEAR_MGQ_FIFO_SIZE_8814B(x) | BIT_MGQ_FIFO_SIZE_8814B(v))
+
+#define BIT_MGQ_FIFO_PAUSE_8814B BIT(13)
+
+#define BIT_SHIFT_MGQ_FIFO_RPTR_8814B 8
+#define BIT_MASK_MGQ_FIFO_RPTR_8814B 0x1f
+#define BIT_MGQ_FIFO_RPTR_8814B(x)                                             \
+	(((x) & BIT_MASK_MGQ_FIFO_RPTR_8814B) << BIT_SHIFT_MGQ_FIFO_RPTR_8814B)
+#define BITS_MGQ_FIFO_RPTR_8814B                                               \
+	(BIT_MASK_MGQ_FIFO_RPTR_8814B << BIT_SHIFT_MGQ_FIFO_RPTR_8814B)
+#define BIT_CLEAR_MGQ_FIFO_RPTR_8814B(x) ((x) & (~BITS_MGQ_FIFO_RPTR_8814B))
+#define BIT_GET_MGQ_FIFO_RPTR_8814B(x)                                         \
+	(((x) >> BIT_SHIFT_MGQ_FIFO_RPTR_8814B) & BIT_MASK_MGQ_FIFO_RPTR_8814B)
+#define BIT_SET_MGQ_FIFO_RPTR_8814B(x, v)                                      \
+	(BIT_CLEAR_MGQ_FIFO_RPTR_8814B(x) | BIT_MGQ_FIFO_RPTR_8814B(v))
+
+/* 2 REG_MGQ_FIFO_ENABLE_8814B */
+#define BIT_MGQ_FIFO_EN_V1_8814B BIT(15)
+
+#define BIT_SHIFT_MGQ_FIFO_PG_SIZE_8814B 12
+#define BIT_MASK_MGQ_FIFO_PG_SIZE_8814B 0x7
+#define BIT_MGQ_FIFO_PG_SIZE_8814B(x)                                          \
+	(((x) & BIT_MASK_MGQ_FIFO_PG_SIZE_8814B)                               \
+	 << BIT_SHIFT_MGQ_FIFO_PG_SIZE_8814B)
+#define BITS_MGQ_FIFO_PG_SIZE_8814B                                            \
+	(BIT_MASK_MGQ_FIFO_PG_SIZE_8814B << BIT_SHIFT_MGQ_FIFO_PG_SIZE_8814B)
+#define BIT_CLEAR_MGQ_FIFO_PG_SIZE_8814B(x)                                    \
+	((x) & (~BITS_MGQ_FIFO_PG_SIZE_8814B))
+#define BIT_GET_MGQ_FIFO_PG_SIZE_8814B(x)                                      \
+	(((x) >> BIT_SHIFT_MGQ_FIFO_PG_SIZE_8814B) &                           \
+	 BIT_MASK_MGQ_FIFO_PG_SIZE_8814B)
+#define BIT_SET_MGQ_FIFO_PG_SIZE_8814B(x, v)                                   \
+	(BIT_CLEAR_MGQ_FIFO_PG_SIZE_8814B(x) | BIT_MGQ_FIFO_PG_SIZE_8814B(v))
+
+#define BIT_SHIFT_MGQ_FIFO_START_PG_8814B 0
+#define BIT_MASK_MGQ_FIFO_START_PG_8814B 0xfff
+#define BIT_MGQ_FIFO_START_PG_8814B(x)                                         \
+	(((x) & BIT_MASK_MGQ_FIFO_START_PG_8814B)                              \
+	 << BIT_SHIFT_MGQ_FIFO_START_PG_8814B)
+#define BITS_MGQ_FIFO_START_PG_8814B                                           \
+	(BIT_MASK_MGQ_FIFO_START_PG_8814B << BIT_SHIFT_MGQ_FIFO_START_PG_8814B)
+#define BIT_CLEAR_MGQ_FIFO_START_PG_8814B(x)                                   \
+	((x) & (~BITS_MGQ_FIFO_START_PG_8814B))
+#define BIT_GET_MGQ_FIFO_START_PG_8814B(x)                                     \
+	(((x) >> BIT_SHIFT_MGQ_FIFO_START_PG_8814B) &                          \
+	 BIT_MASK_MGQ_FIFO_START_PG_8814B)
+#define BIT_SET_MGQ_FIFO_START_PG_8814B(x, v)                                  \
+	(BIT_CLEAR_MGQ_FIFO_START_PG_8814B(x) | BIT_MGQ_FIFO_START_PG_8814B(v))
+
+/* 2 REG_MGQ_FIFO_RELEASE_INT_MASK_8814B */
+
+#define BIT_SHIFT_MGQ_FIFO_REL_INT_MASK_8814B 0
+#define BIT_MASK_MGQ_FIFO_REL_INT_MASK_8814B 0xffff
+#define BIT_MGQ_FIFO_REL_INT_MASK_8814B(x)                                     \
+	(((x) & BIT_MASK_MGQ_FIFO_REL_INT_MASK_8814B)                          \
+	 << BIT_SHIFT_MGQ_FIFO_REL_INT_MASK_8814B)
+#define BITS_MGQ_FIFO_REL_INT_MASK_8814B                                       \
+	(BIT_MASK_MGQ_FIFO_REL_INT_MASK_8814B                                  \
+	 << BIT_SHIFT_MGQ_FIFO_REL_INT_MASK_8814B)
+#define BIT_CLEAR_MGQ_FIFO_REL_INT_MASK_8814B(x)                               \
+	((x) & (~BITS_MGQ_FIFO_REL_INT_MASK_8814B))
+#define BIT_GET_MGQ_FIFO_REL_INT_MASK_8814B(x)                                 \
+	(((x) >> BIT_SHIFT_MGQ_FIFO_REL_INT_MASK_8814B) &                      \
+	 BIT_MASK_MGQ_FIFO_REL_INT_MASK_8814B)
+#define BIT_SET_MGQ_FIFO_REL_INT_MASK_8814B(x, v)                              \
+	(BIT_CLEAR_MGQ_FIFO_REL_INT_MASK_8814B(x) |                            \
+	 BIT_MGQ_FIFO_REL_INT_MASK_8814B(v))
+
+/* 2 REG_MGQ_FIFO_RELEASE_INT_FLAG_8814B */
+
+#define BIT_SHIFT_MGQ_FIFO_REL_INT_FLAG_8814B 0
+#define BIT_MASK_MGQ_FIFO_REL_INT_FLAG_8814B 0xffff
+#define BIT_MGQ_FIFO_REL_INT_FLAG_8814B(x)                                     \
+	(((x) & BIT_MASK_MGQ_FIFO_REL_INT_FLAG_8814B)                          \
+	 << BIT_SHIFT_MGQ_FIFO_REL_INT_FLAG_8814B)
+#define BITS_MGQ_FIFO_REL_INT_FLAG_8814B                                       \
+	(BIT_MASK_MGQ_FIFO_REL_INT_FLAG_8814B                                  \
+	 << BIT_SHIFT_MGQ_FIFO_REL_INT_FLAG_8814B)
+#define BIT_CLEAR_MGQ_FIFO_REL_INT_FLAG_8814B(x)                               \
+	((x) & (~BITS_MGQ_FIFO_REL_INT_FLAG_8814B))
+#define BIT_GET_MGQ_FIFO_REL_INT_FLAG_8814B(x)                                 \
+	(((x) >> BIT_SHIFT_MGQ_FIFO_REL_INT_FLAG_8814B) &                      \
+	 BIT_MASK_MGQ_FIFO_REL_INT_FLAG_8814B)
+#define BIT_SET_MGQ_FIFO_REL_INT_FLAG_8814B(x, v)                              \
+	(BIT_CLEAR_MGQ_FIFO_REL_INT_FLAG_8814B(x) |                            \
+	 BIT_MGQ_FIFO_REL_INT_FLAG_8814B(v))
+
+/* 2 REG_MGQ_FIFO_VALID_MAP_8814B */
+
+#define BIT_SHIFT_MGQ_FIFO_PKT_VALID_MAP_8814B 0
+#define BIT_MASK_MGQ_FIFO_PKT_VALID_MAP_8814B 0xffff
+#define BIT_MGQ_FIFO_PKT_VALID_MAP_8814B(x)                                    \
+	(((x) & BIT_MASK_MGQ_FIFO_PKT_VALID_MAP_8814B)                         \
+	 << BIT_SHIFT_MGQ_FIFO_PKT_VALID_MAP_8814B)
+#define BITS_MGQ_FIFO_PKT_VALID_MAP_8814B                                      \
+	(BIT_MASK_MGQ_FIFO_PKT_VALID_MAP_8814B                                 \
+	 << BIT_SHIFT_MGQ_FIFO_PKT_VALID_MAP_8814B)
+#define BIT_CLEAR_MGQ_FIFO_PKT_VALID_MAP_8814B(x)                              \
+	((x) & (~BITS_MGQ_FIFO_PKT_VALID_MAP_8814B))
+#define BIT_GET_MGQ_FIFO_PKT_VALID_MAP_8814B(x)                                \
+	(((x) >> BIT_SHIFT_MGQ_FIFO_PKT_VALID_MAP_8814B) &                     \
+	 BIT_MASK_MGQ_FIFO_PKT_VALID_MAP_8814B)
+#define BIT_SET_MGQ_FIFO_PKT_VALID_MAP_8814B(x, v)                             \
+	(BIT_CLEAR_MGQ_FIFO_PKT_VALID_MAP_8814B(x) |                           \
+	 BIT_MGQ_FIFO_PKT_VALID_MAP_8814B(v))
+
+/* 2 REG_MGQ_FIFO_LIFETIME_8814B */
+
+#define BIT_SHIFT_MGQ_FIFO_LIFETIME_8814B 0
+#define BIT_MASK_MGQ_FIFO_LIFETIME_8814B 0xffff
+#define BIT_MGQ_FIFO_LIFETIME_8814B(x)                                         \
+	(((x) & BIT_MASK_MGQ_FIFO_LIFETIME_8814B)                              \
+	 << BIT_SHIFT_MGQ_FIFO_LIFETIME_8814B)
+#define BITS_MGQ_FIFO_LIFETIME_8814B                                           \
+	(BIT_MASK_MGQ_FIFO_LIFETIME_8814B << BIT_SHIFT_MGQ_FIFO_LIFETIME_8814B)
+#define BIT_CLEAR_MGQ_FIFO_LIFETIME_8814B(x)                                   \
+	((x) & (~BITS_MGQ_FIFO_LIFETIME_8814B))
+#define BIT_GET_MGQ_FIFO_LIFETIME_8814B(x)                                     \
+	(((x) >> BIT_SHIFT_MGQ_FIFO_LIFETIME_8814B) &                          \
+	 BIT_MASK_MGQ_FIFO_LIFETIME_8814B)
+#define BIT_SET_MGQ_FIFO_LIFETIME_8814B(x, v)                                  \
+	(BIT_CLEAR_MGQ_FIFO_LIFETIME_8814B(x) | BIT_MGQ_FIFO_LIFETIME_8814B(v))
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_PKT_TRANS_8814B */
+
+#define BIT_SHIFT_IE_DESC_OFFSET_8814B 16
+#define BIT_MASK_IE_DESC_OFFSET_8814B 0x1ff
+#define BIT_IE_DESC_OFFSET_8814B(x)                                            \
+	(((x) & BIT_MASK_IE_DESC_OFFSET_8814B)                                 \
+	 << BIT_SHIFT_IE_DESC_OFFSET_8814B)
+#define BITS_IE_DESC_OFFSET_8814B                                              \
+	(BIT_MASK_IE_DESC_OFFSET_8814B << BIT_SHIFT_IE_DESC_OFFSET_8814B)
+#define BIT_CLEAR_IE_DESC_OFFSET_8814B(x) ((x) & (~BITS_IE_DESC_OFFSET_8814B))
+#define BIT_GET_IE_DESC_OFFSET_8814B(x)                                        \
+	(((x) >> BIT_SHIFT_IE_DESC_OFFSET_8814B) &                             \
+	 BIT_MASK_IE_DESC_OFFSET_8814B)
+#define BIT_SET_IE_DESC_OFFSET_8814B(x, v)                                     \
+	(BIT_CLEAR_IE_DESC_OFFSET_8814B(x) | BIT_IE_DESC_OFFSET_8814B(v))
+
+#define BIT_DIS_FWCMD_PATH_ERRCHK_8814B BIT(13)
+#define BIT_MAC_HDR_CONVERT_EN_8814B BIT(12)
+#define BIT_TXDESC_TRANS_EN_8814B BIT(8)
+#define BIT_PKT_TRANS_ERRINT_EN_8814B BIT(7)
+
+#define BIT_SHIFT_PKT_TRANS_ERR_MACID_SEL_8814B 4
+#define BIT_MASK_PKT_TRANS_ERR_MACID_SEL_8814B 0x3
+#define BIT_PKT_TRANS_ERR_MACID_SEL_8814B(x)                                   \
+	(((x) & BIT_MASK_PKT_TRANS_ERR_MACID_SEL_8814B)                        \
+	 << BIT_SHIFT_PKT_TRANS_ERR_MACID_SEL_8814B)
+#define BITS_PKT_TRANS_ERR_MACID_SEL_8814B                                     \
+	(BIT_MASK_PKT_TRANS_ERR_MACID_SEL_8814B                                \
+	 << BIT_SHIFT_PKT_TRANS_ERR_MACID_SEL_8814B)
+#define BIT_CLEAR_PKT_TRANS_ERR_MACID_SEL_8814B(x)                             \
+	((x) & (~BITS_PKT_TRANS_ERR_MACID_SEL_8814B))
+#define BIT_GET_PKT_TRANS_ERR_MACID_SEL_8814B(x)                               \
+	(((x) >> BIT_SHIFT_PKT_TRANS_ERR_MACID_SEL_8814B) &                    \
+	 BIT_MASK_PKT_TRANS_ERR_MACID_SEL_8814B)
+#define BIT_SET_PKT_TRANS_ERR_MACID_SEL_8814B(x, v)                            \
+	(BIT_CLEAR_PKT_TRANS_ERR_MACID_SEL_8814B(x) |                          \
+	 BIT_PKT_TRANS_ERR_MACID_SEL_8814B(v))
+
+#define BIT_PKT_TRANS_IEINIT_ERR_8814B BIT(3)
+#define BIT_PKT_TRANS_IENUM_ERR_8814B BIT(2)
+#define BIT_PKT_TRANS_IECNT_ERR1_8814B BIT(1)
+#define BIT_PKT_TRANS_IECNT_ERR0_8814B BIT(0)
+
+/* 2 REG_SHCUT_LLC_ETH_TYPE0_8814B */
+
+/* 2 REG_SHCUT_LLC_ETH_TYPE1_8814B */
+
+#define BIT_SHIFT_SHCUT_MHDR_OFFSET_8814B 16
+#define BIT_MASK_SHCUT_MHDR_OFFSET_8814B 0x1ff
+#define BIT_SHCUT_MHDR_OFFSET_8814B(x)                                         \
+	(((x) & BIT_MASK_SHCUT_MHDR_OFFSET_8814B)                              \
+	 << BIT_SHIFT_SHCUT_MHDR_OFFSET_8814B)
+#define BITS_SHCUT_MHDR_OFFSET_8814B                                           \
+	(BIT_MASK_SHCUT_MHDR_OFFSET_8814B << BIT_SHIFT_SHCUT_MHDR_OFFSET_8814B)
+#define BIT_CLEAR_SHCUT_MHDR_OFFSET_8814B(x)                                   \
+	((x) & (~BITS_SHCUT_MHDR_OFFSET_8814B))
+#define BIT_GET_SHCUT_MHDR_OFFSET_8814B(x)                                     \
+	(((x) >> BIT_SHIFT_SHCUT_MHDR_OFFSET_8814B) &                          \
+	 BIT_MASK_SHCUT_MHDR_OFFSET_8814B)
+#define BIT_SET_SHCUT_MHDR_OFFSET_8814B(x, v)                                  \
+	(BIT_CLEAR_SHCUT_MHDR_OFFSET_8814B(x) | BIT_SHCUT_MHDR_OFFSET_8814B(v))
+
+/* 2 REG_SHCUT_LLC_OUI0_8814B */
+
+/* 2 REG_SHCUT_LLC_OUI1_8814B */
+
+/* 2 REG_SHCUT_LLC_OUI2_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+#define BIT_SHIFT_PKT_TRANS_ERR_MACID_8814B 0
+#define BIT_MASK_PKT_TRANS_ERR_MACID_8814B 0xffffffffL
+#define BIT_PKT_TRANS_ERR_MACID_8814B(x)                                       \
+	(((x) & BIT_MASK_PKT_TRANS_ERR_MACID_8814B)                            \
+	 << BIT_SHIFT_PKT_TRANS_ERR_MACID_8814B)
+#define BITS_PKT_TRANS_ERR_MACID_8814B                                         \
+	(BIT_MASK_PKT_TRANS_ERR_MACID_8814B                                    \
+	 << BIT_SHIFT_PKT_TRANS_ERR_MACID_8814B)
+#define BIT_CLEAR_PKT_TRANS_ERR_MACID_8814B(x)                                 \
+	((x) & (~BITS_PKT_TRANS_ERR_MACID_8814B))
+#define BIT_GET_PKT_TRANS_ERR_MACID_8814B(x)                                   \
+	(((x) >> BIT_SHIFT_PKT_TRANS_ERR_MACID_8814B) &                        \
+	 BIT_MASK_PKT_TRANS_ERR_MACID_8814B)
+#define BIT_SET_PKT_TRANS_ERR_MACID_8814B(x, v)                                \
+	(BIT_CLEAR_PKT_TRANS_ERR_MACID_8814B(x) |                              \
+	 BIT_PKT_TRANS_ERR_MACID_8814B(v))
+
+/* 2 REG_FWCMDQ_CTRL_8814B */
+#define BIT_FW_RELEASEPKT_POLLING_8814B BIT(31)
+
+#define BIT_SHIFT_FWCMDQ_RELEASE_HEAD_8814B 16
+#define BIT_MASK_FWCMDQ_RELEASE_HEAD_8814B 0xfff
+#define BIT_FWCMDQ_RELEASE_HEAD_8814B(x)                                       \
+	(((x) & BIT_MASK_FWCMDQ_RELEASE_HEAD_8814B)                            \
+	 << BIT_SHIFT_FWCMDQ_RELEASE_HEAD_8814B)
+#define BITS_FWCMDQ_RELEASE_HEAD_8814B                                         \
+	(BIT_MASK_FWCMDQ_RELEASE_HEAD_8814B                                    \
+	 << BIT_SHIFT_FWCMDQ_RELEASE_HEAD_8814B)
+#define BIT_CLEAR_FWCMDQ_RELEASE_HEAD_8814B(x)                                 \
+	((x) & (~BITS_FWCMDQ_RELEASE_HEAD_8814B))
+#define BIT_GET_FWCMDQ_RELEASE_HEAD_8814B(x)                                   \
+	(((x) >> BIT_SHIFT_FWCMDQ_RELEASE_HEAD_8814B) &                        \
+	 BIT_MASK_FWCMDQ_RELEASE_HEAD_8814B)
+#define BIT_SET_FWCMDQ_RELEASE_HEAD_8814B(x, v)                                \
+	(BIT_CLEAR_FWCMDQ_RELEASE_HEAD_8814B(x) |                              \
+	 BIT_FWCMDQ_RELEASE_HEAD_8814B(v))
+
+#define BIT_FW_GETPKTT_POLLING_8814B BIT(15)
+
+#define BIT_SHIFT_FWCMDQ_H_8814B 0
+#define BIT_MASK_FWCMDQ_H_8814B 0xfff
+#define BIT_FWCMDQ_H_8814B(x)                                                  \
+	(((x) & BIT_MASK_FWCMDQ_H_8814B) << BIT_SHIFT_FWCMDQ_H_8814B)
+#define BITS_FWCMDQ_H_8814B                                                    \
+	(BIT_MASK_FWCMDQ_H_8814B << BIT_SHIFT_FWCMDQ_H_8814B)
+#define BIT_CLEAR_FWCMDQ_H_8814B(x) ((x) & (~BITS_FWCMDQ_H_8814B))
+#define BIT_GET_FWCMDQ_H_8814B(x)                                              \
+	(((x) >> BIT_SHIFT_FWCMDQ_H_8814B) & BIT_MASK_FWCMDQ_H_8814B)
+#define BIT_SET_FWCMDQ_H_8814B(x, v)                                           \
+	(BIT_CLEAR_FWCMDQ_H_8814B(x) | BIT_FWCMDQ_H_8814B(v))
+
+/* 2 REG_FWCMDQ_PAGE_8814B */
+
+#define BIT_SHIFT_FWCMDQ_TOTAL_PAGE_8814B 16
+#define BIT_MASK_FWCMDQ_TOTAL_PAGE_8814B 0xfff
+#define BIT_FWCMDQ_TOTAL_PAGE_8814B(x)                                         \
+	(((x) & BIT_MASK_FWCMDQ_TOTAL_PAGE_8814B)                              \
+	 << BIT_SHIFT_FWCMDQ_TOTAL_PAGE_8814B)
+#define BITS_FWCMDQ_TOTAL_PAGE_8814B                                           \
+	(BIT_MASK_FWCMDQ_TOTAL_PAGE_8814B << BIT_SHIFT_FWCMDQ_TOTAL_PAGE_8814B)
+#define BIT_CLEAR_FWCMDQ_TOTAL_PAGE_8814B(x)                                   \
+	((x) & (~BITS_FWCMDQ_TOTAL_PAGE_8814B))
+#define BIT_GET_FWCMDQ_TOTAL_PAGE_8814B(x)                                     \
+	(((x) >> BIT_SHIFT_FWCMDQ_TOTAL_PAGE_8814B) &                          \
+	 BIT_MASK_FWCMDQ_TOTAL_PAGE_8814B)
+#define BIT_SET_FWCMDQ_TOTAL_PAGE_8814B(x, v)                                  \
+	(BIT_CLEAR_FWCMDQ_TOTAL_PAGE_8814B(x) | BIT_FWCMDQ_TOTAL_PAGE_8814B(v))
+
+#define BIT_SHIFT_FWCMDQ_QUEUE_PAGE_8814B 0
+#define BIT_MASK_FWCMDQ_QUEUE_PAGE_8814B 0xfff
+#define BIT_FWCMDQ_QUEUE_PAGE_8814B(x)                                         \
+	(((x) & BIT_MASK_FWCMDQ_QUEUE_PAGE_8814B)                              \
+	 << BIT_SHIFT_FWCMDQ_QUEUE_PAGE_8814B)
+#define BITS_FWCMDQ_QUEUE_PAGE_8814B                                           \
+	(BIT_MASK_FWCMDQ_QUEUE_PAGE_8814B << BIT_SHIFT_FWCMDQ_QUEUE_PAGE_8814B)
+#define BIT_CLEAR_FWCMDQ_QUEUE_PAGE_8814B(x)                                   \
+	((x) & (~BITS_FWCMDQ_QUEUE_PAGE_8814B))
+#define BIT_GET_FWCMDQ_QUEUE_PAGE_8814B(x)                                     \
+	(((x) >> BIT_SHIFT_FWCMDQ_QUEUE_PAGE_8814B) &                          \
+	 BIT_MASK_FWCMDQ_QUEUE_PAGE_8814B)
+#define BIT_SET_FWCMDQ_QUEUE_PAGE_8814B(x, v)                                  \
+	(BIT_CLEAR_FWCMDQ_QUEUE_PAGE_8814B(x) | BIT_FWCMDQ_QUEUE_PAGE_8814B(v))
+
+/* 2 REG_FWCMDQ_INFO_8814B */
+#define BIT_FWCMD_READY_8814B BIT(31)
+#define BIT_FWCMDQ_OVERFLOW_8814B BIT(30)
+#define BIT_FWCMDQ_UNDERFLOW_8814B BIT(29)
+#define BIT_FWCMDQ_RELEASE_MISS_8814B BIT(28)
+
+#define BIT_SHIFT_FWCMDQ_TOTAL_PKT_8814B 16
+#define BIT_MASK_FWCMDQ_TOTAL_PKT_8814B 0xfff
+#define BIT_FWCMDQ_TOTAL_PKT_8814B(x)                                          \
+	(((x) & BIT_MASK_FWCMDQ_TOTAL_PKT_8814B)                               \
+	 << BIT_SHIFT_FWCMDQ_TOTAL_PKT_8814B)
+#define BITS_FWCMDQ_TOTAL_PKT_8814B                                            \
+	(BIT_MASK_FWCMDQ_TOTAL_PKT_8814B << BIT_SHIFT_FWCMDQ_TOTAL_PKT_8814B)
+#define BIT_CLEAR_FWCMDQ_TOTAL_PKT_8814B(x)                                    \
+	((x) & (~BITS_FWCMDQ_TOTAL_PKT_8814B))
+#define BIT_GET_FWCMDQ_TOTAL_PKT_8814B(x)                                      \
+	(((x) >> BIT_SHIFT_FWCMDQ_TOTAL_PKT_8814B) &                           \
+	 BIT_MASK_FWCMDQ_TOTAL_PKT_8814B)
+#define BIT_SET_FWCMDQ_TOTAL_PKT_8814B(x, v)                                   \
+	(BIT_CLEAR_FWCMDQ_TOTAL_PKT_8814B(x) | BIT_FWCMDQ_TOTAL_PKT_8814B(v))
+
+#define BIT_SHIFT_FWCMDQ_QUEUE_PKT_8814B 0
+#define BIT_MASK_FWCMDQ_QUEUE_PKT_8814B 0xfff
+#define BIT_FWCMDQ_QUEUE_PKT_8814B(x)                                          \
+	(((x) & BIT_MASK_FWCMDQ_QUEUE_PKT_8814B)                               \
+	 << BIT_SHIFT_FWCMDQ_QUEUE_PKT_8814B)
+#define BITS_FWCMDQ_QUEUE_PKT_8814B                                            \
+	(BIT_MASK_FWCMDQ_QUEUE_PKT_8814B << BIT_SHIFT_FWCMDQ_QUEUE_PKT_8814B)
+#define BIT_CLEAR_FWCMDQ_QUEUE_PKT_8814B(x)                                    \
+	((x) & (~BITS_FWCMDQ_QUEUE_PKT_8814B))
+#define BIT_GET_FWCMDQ_QUEUE_PKT_8814B(x)                                      \
+	(((x) >> BIT_SHIFT_FWCMDQ_QUEUE_PKT_8814B) &                           \
+	 BIT_MASK_FWCMDQ_QUEUE_PKT_8814B)
+#define BIT_SET_FWCMDQ_QUEUE_PKT_8814B(x, v)                                   \
+	(BIT_CLEAR_FWCMDQ_QUEUE_PKT_8814B(x) | BIT_FWCMDQ_QUEUE_PKT_8814B(v))
+
+/* 2 REG_FWCMDQ_HOLD_PKTNUM_8814B */
+
+#define BIT_SHIFT_FWCMDQ_HOLD__PKTNUM_8814B 0
+#define BIT_MASK_FWCMDQ_HOLD__PKTNUM_8814B 0xfff
+#define BIT_FWCMDQ_HOLD__PKTNUM_8814B(x)                                       \
+	(((x) & BIT_MASK_FWCMDQ_HOLD__PKTNUM_8814B)                            \
+	 << BIT_SHIFT_FWCMDQ_HOLD__PKTNUM_8814B)
+#define BITS_FWCMDQ_HOLD__PKTNUM_8814B                                         \
+	(BIT_MASK_FWCMDQ_HOLD__PKTNUM_8814B                                    \
+	 << BIT_SHIFT_FWCMDQ_HOLD__PKTNUM_8814B)
+#define BIT_CLEAR_FWCMDQ_HOLD__PKTNUM_8814B(x)                                 \
+	((x) & (~BITS_FWCMDQ_HOLD__PKTNUM_8814B))
+#define BIT_GET_FWCMDQ_HOLD__PKTNUM_8814B(x)                                   \
+	(((x) >> BIT_SHIFT_FWCMDQ_HOLD__PKTNUM_8814B) &                        \
+	 BIT_MASK_FWCMDQ_HOLD__PKTNUM_8814B)
+#define BIT_SET_FWCMDQ_HOLD__PKTNUM_8814B(x, v)                                \
+	(BIT_CLEAR_FWCMDQ_HOLD__PKTNUM_8814B(x) |                              \
+	 BIT_FWCMDQ_HOLD__PKTNUM_8814B(v))
+
+/* 2 REG_MU_TX_CTRL_8814B */
+#define BIT_SEARCH_DONE_RDY_8814B BIT(31)
+#define BIT_MU_EN_8814B BIT(30)
+#define BIT_MU_SECONDARY_WAITMODE_EN_8814B BIT(29)
+#define BIT_MU_BB_SCORE_EN_8814B BIT(28)
+#define BIT_MU_SECONDARY_ANT_COUNT_EN_8814B BIT(27)
+#define BIT_MUARB_SEARCH_ERR_EN_8814B BIT(26)
+
+#define BIT_SHIFT_DIS_SU_TXBF_8814B 16
+#define BIT_MASK_DIS_SU_TXBF_8814B 0x3f
+#define BIT_DIS_SU_TXBF_8814B(x)                                               \
+	(((x) & BIT_MASK_DIS_SU_TXBF_8814B) << BIT_SHIFT_DIS_SU_TXBF_8814B)
+#define BITS_DIS_SU_TXBF_8814B                                                 \
+	(BIT_MASK_DIS_SU_TXBF_8814B << BIT_SHIFT_DIS_SU_TXBF_8814B)
+#define BIT_CLEAR_DIS_SU_TXBF_8814B(x) ((x) & (~BITS_DIS_SU_TXBF_8814B))
+#define BIT_GET_DIS_SU_TXBF_8814B(x)                                           \
+	(((x) >> BIT_SHIFT_DIS_SU_TXBF_8814B) & BIT_MASK_DIS_SU_TXBF_8814B)
+#define BIT_SET_DIS_SU_TXBF_8814B(x, v)                                        \
+	(BIT_CLEAR_DIS_SU_TXBF_8814B(x) | BIT_DIS_SU_TXBF_8814B(v))
+
+#define BIT_SHIFT_MU_RL_8814B 12
+#define BIT_MASK_MU_RL_8814B 0xf
+#define BIT_MU_RL_8814B(x)                                                     \
+	(((x) & BIT_MASK_MU_RL_8814B) << BIT_SHIFT_MU_RL_8814B)
+#define BITS_MU_RL_8814B (BIT_MASK_MU_RL_8814B << BIT_SHIFT_MU_RL_8814B)
+#define BIT_CLEAR_MU_RL_8814B(x) ((x) & (~BITS_MU_RL_8814B))
+#define BIT_GET_MU_RL_8814B(x)                                                 \
+	(((x) >> BIT_SHIFT_MU_RL_8814B) & BIT_MASK_MU_RL_8814B)
+#define BIT_SET_MU_RL_8814B(x, v)                                              \
+	(BIT_CLEAR_MU_RL_8814B(x) | BIT_MU_RL_8814B(v))
+
+#define BIT_SHIFT_MU_TAB_SEL_8814B 8
+#define BIT_MASK_MU_TAB_SEL_8814B 0xf
+#define BIT_MU_TAB_SEL_8814B(x)                                                \
+	(((x) & BIT_MASK_MU_TAB_SEL_8814B) << BIT_SHIFT_MU_TAB_SEL_8814B)
+#define BITS_MU_TAB_SEL_8814B                                                  \
+	(BIT_MASK_MU_TAB_SEL_8814B << BIT_SHIFT_MU_TAB_SEL_8814B)
+#define BIT_CLEAR_MU_TAB_SEL_8814B(x) ((x) & (~BITS_MU_TAB_SEL_8814B))
+#define BIT_GET_MU_TAB_SEL_8814B(x)                                            \
+	(((x) >> BIT_SHIFT_MU_TAB_SEL_8814B) & BIT_MASK_MU_TAB_SEL_8814B)
+#define BIT_SET_MU_TAB_SEL_8814B(x, v)                                         \
+	(BIT_CLEAR_MU_TAB_SEL_8814B(x) | BIT_MU_TAB_SEL_8814B(v))
+
+#define BIT_SHIFT_MU_TAB_VALID_8814B 0
+#define BIT_MASK_MU_TAB_VALID_8814B 0x3f
+#define BIT_MU_TAB_VALID_8814B(x)                                              \
+	(((x) & BIT_MASK_MU_TAB_VALID_8814B) << BIT_SHIFT_MU_TAB_VALID_8814B)
+#define BITS_MU_TAB_VALID_8814B                                                \
+	(BIT_MASK_MU_TAB_VALID_8814B << BIT_SHIFT_MU_TAB_VALID_8814B)
+#define BIT_CLEAR_MU_TAB_VALID_8814B(x) ((x) & (~BITS_MU_TAB_VALID_8814B))
+#define BIT_GET_MU_TAB_VALID_8814B(x)                                          \
+	(((x) >> BIT_SHIFT_MU_TAB_VALID_8814B) & BIT_MASK_MU_TAB_VALID_8814B)
+#define BIT_SET_MU_TAB_VALID_8814B(x, v)                                       \
+	(BIT_CLEAR_MU_TAB_VALID_8814B(x) | BIT_MU_TAB_VALID_8814B(v))
+
+/* 2 REG_MU_STA_GID_VLD_8814B */
+
+#define BIT_SHIFT_MU_STA_GTAB_VALID_8814B 0
+#define BIT_MASK_MU_STA_GTAB_VALID_8814B 0xffffffffL
+#define BIT_MU_STA_GTAB_VALID_8814B(x)                                         \
+	(((x) & BIT_MASK_MU_STA_GTAB_VALID_8814B)                              \
+	 << BIT_SHIFT_MU_STA_GTAB_VALID_8814B)
+#define BITS_MU_STA_GTAB_VALID_8814B                                           \
+	(BIT_MASK_MU_STA_GTAB_VALID_8814B << BIT_SHIFT_MU_STA_GTAB_VALID_8814B)
+#define BIT_CLEAR_MU_STA_GTAB_VALID_8814B(x)                                   \
+	((x) & (~BITS_MU_STA_GTAB_VALID_8814B))
+#define BIT_GET_MU_STA_GTAB_VALID_8814B(x)                                     \
+	(((x) >> BIT_SHIFT_MU_STA_GTAB_VALID_8814B) &                          \
+	 BIT_MASK_MU_STA_GTAB_VALID_8814B)
+#define BIT_SET_MU_STA_GTAB_VALID_8814B(x, v)                                  \
+	(BIT_CLEAR_MU_STA_GTAB_VALID_8814B(x) | BIT_MU_STA_GTAB_VALID_8814B(v))
+
+/* 2 REG_MU_STA_USER_POS_INFO_8814B */
+
+#define BIT_SHIFT_MU_STA_GTAB_POSITION_L_8814B 0
+#define BIT_MASK_MU_STA_GTAB_POSITION_L_8814B 0xffffffffL
+#define BIT_MU_STA_GTAB_POSITION_L_8814B(x)                                    \
+	(((x) & BIT_MASK_MU_STA_GTAB_POSITION_L_8814B)                         \
+	 << BIT_SHIFT_MU_STA_GTAB_POSITION_L_8814B)
+#define BITS_MU_STA_GTAB_POSITION_L_8814B                                      \
+	(BIT_MASK_MU_STA_GTAB_POSITION_L_8814B                                 \
+	 << BIT_SHIFT_MU_STA_GTAB_POSITION_L_8814B)
+#define BIT_CLEAR_MU_STA_GTAB_POSITION_L_8814B(x)                              \
+	((x) & (~BITS_MU_STA_GTAB_POSITION_L_8814B))
+#define BIT_GET_MU_STA_GTAB_POSITION_L_8814B(x)                                \
+	(((x) >> BIT_SHIFT_MU_STA_GTAB_POSITION_L_8814B) &                     \
+	 BIT_MASK_MU_STA_GTAB_POSITION_L_8814B)
+#define BIT_SET_MU_STA_GTAB_POSITION_L_8814B(x, v)                             \
+	(BIT_CLEAR_MU_STA_GTAB_POSITION_L_8814B(x) |                           \
+	 BIT_MU_STA_GTAB_POSITION_L_8814B(v))
+
+/* 2 REG_MU_STA_USER_POS_INFO_H_8814B */
+
+#define BIT_SHIFT_MU_STA_GTAB_POSITION_H_8814B 0
+#define BIT_MASK_MU_STA_GTAB_POSITION_H_8814B 0xffffffffL
+#define BIT_MU_STA_GTAB_POSITION_H_8814B(x)                                    \
+	(((x) & BIT_MASK_MU_STA_GTAB_POSITION_H_8814B)                         \
+	 << BIT_SHIFT_MU_STA_GTAB_POSITION_H_8814B)
+#define BITS_MU_STA_GTAB_POSITION_H_8814B                                      \
+	(BIT_MASK_MU_STA_GTAB_POSITION_H_8814B                                 \
+	 << BIT_SHIFT_MU_STA_GTAB_POSITION_H_8814B)
+#define BIT_CLEAR_MU_STA_GTAB_POSITION_H_8814B(x)                              \
+	((x) & (~BITS_MU_STA_GTAB_POSITION_H_8814B))
+#define BIT_GET_MU_STA_GTAB_POSITION_H_8814B(x)                                \
+	(((x) >> BIT_SHIFT_MU_STA_GTAB_POSITION_H_8814B) &                     \
+	 BIT_MASK_MU_STA_GTAB_POSITION_H_8814B)
+#define BIT_SET_MU_STA_GTAB_POSITION_H_8814B(x, v)                             \
+	(BIT_CLEAR_MU_STA_GTAB_POSITION_H_8814B(x) |                           \
+	 BIT_MU_STA_GTAB_POSITION_H_8814B(v))
+
+/* 2 REG_CHNL_INFO_CTRL_8814B */
+#define BIT_CHNL_REF_RXNAV_8814B BIT(7)
+#define BIT_CHNL_REF_VBON_8814B BIT(6)
+#define BIT_CHNL_REF_EDCA_8814B BIT(5)
+#define BIT_CHNL_REF_CCA_8814B BIT(4)
+#define BIT_RST_CHNL_BUSY_8814B BIT(3)
+#define BIT_RST_CHNL_IDLE_8814B BIT(2)
+#define BIT_CHNL_INFO_RST_8814B BIT(1)
+#define BIT_ATM_AIRTIME_EN_8814B BIT(0)
+
+/* 2 REG_CHNL_IDLE_TIME_8814B */
+
+#define BIT_SHIFT_CHNL_IDLE_TIME_8814B 0
+#define BIT_MASK_CHNL_IDLE_TIME_8814B 0xffffffffL
+#define BIT_CHNL_IDLE_TIME_8814B(x)                                            \
+	(((x) & BIT_MASK_CHNL_IDLE_TIME_8814B)                                 \
+	 << BIT_SHIFT_CHNL_IDLE_TIME_8814B)
+#define BITS_CHNL_IDLE_TIME_8814B                                              \
+	(BIT_MASK_CHNL_IDLE_TIME_8814B << BIT_SHIFT_CHNL_IDLE_TIME_8814B)
+#define BIT_CLEAR_CHNL_IDLE_TIME_8814B(x) ((x) & (~BITS_CHNL_IDLE_TIME_8814B))
+#define BIT_GET_CHNL_IDLE_TIME_8814B(x)                                        \
+	(((x) >> BIT_SHIFT_CHNL_IDLE_TIME_8814B) &                             \
+	 BIT_MASK_CHNL_IDLE_TIME_8814B)
+#define BIT_SET_CHNL_IDLE_TIME_8814B(x, v)                                     \
+	(BIT_CLEAR_CHNL_IDLE_TIME_8814B(x) | BIT_CHNL_IDLE_TIME_8814B(v))
+
+/* 2 REG_CHNL_BUSY_TIME_8814B */
+
+#define BIT_SHIFT_CHNL_BUSY_TIME_8814B 0
+#define BIT_MASK_CHNL_BUSY_TIME_8814B 0xffffffffL
+#define BIT_CHNL_BUSY_TIME_8814B(x)                                            \
+	(((x) & BIT_MASK_CHNL_BUSY_TIME_8814B)                                 \
+	 << BIT_SHIFT_CHNL_BUSY_TIME_8814B)
+#define BITS_CHNL_BUSY_TIME_8814B                                              \
+	(BIT_MASK_CHNL_BUSY_TIME_8814B << BIT_SHIFT_CHNL_BUSY_TIME_8814B)
+#define BIT_CLEAR_CHNL_BUSY_TIME_8814B(x) ((x) & (~BITS_CHNL_BUSY_TIME_8814B))
+#define BIT_GET_CHNL_BUSY_TIME_8814B(x)                                        \
+	(((x) >> BIT_SHIFT_CHNL_BUSY_TIME_8814B) &                             \
+	 BIT_MASK_CHNL_BUSY_TIME_8814B)
+#define BIT_SET_CHNL_BUSY_TIME_8814B(x, v)                                     \
+	(BIT_CLEAR_CHNL_BUSY_TIME_8814B(x) | BIT_CHNL_BUSY_TIME_8814B(v))
+
+/* 2 REG_MU_TRX_DBG_CNT_V1_8814B */
+#define BIT_FORCE_SND_STS_EN_8814B BIT(31)
+
+#define BIT_SHIFT_SND_STS_VALUE_8814B 24
+#define BIT_MASK_SND_STS_VALUE_8814B 0x3f
+#define BIT_SND_STS_VALUE_8814B(x)                                             \
+	(((x) & BIT_MASK_SND_STS_VALUE_8814B) << BIT_SHIFT_SND_STS_VALUE_8814B)
+#define BITS_SND_STS_VALUE_8814B                                               \
+	(BIT_MASK_SND_STS_VALUE_8814B << BIT_SHIFT_SND_STS_VALUE_8814B)
+#define BIT_CLEAR_SND_STS_VALUE_8814B(x) ((x) & (~BITS_SND_STS_VALUE_8814B))
+#define BIT_GET_SND_STS_VALUE_8814B(x)                                         \
+	(((x) >> BIT_SHIFT_SND_STS_VALUE_8814B) & BIT_MASK_SND_STS_VALUE_8814B)
+#define BIT_SET_SND_STS_VALUE_8814B(x, v)                                      \
+	(BIT_CLEAR_SND_STS_VALUE_8814B(x) | BIT_SND_STS_VALUE_8814B(v))
+
+#define BIT_MU_DNGCNT_RST_8814B BIT(20)
+
+#define BIT_SHIFT_MU_DNGCNT_SEL_8814B 16
+#define BIT_MASK_MU_DNGCNT_SEL_8814B 0xf
+#define BIT_MU_DNGCNT_SEL_8814B(x)                                             \
+	(((x) & BIT_MASK_MU_DNGCNT_SEL_8814B) << BIT_SHIFT_MU_DNGCNT_SEL_8814B)
+#define BITS_MU_DNGCNT_SEL_8814B                                               \
+	(BIT_MASK_MU_DNGCNT_SEL_8814B << BIT_SHIFT_MU_DNGCNT_SEL_8814B)
+#define BIT_CLEAR_MU_DNGCNT_SEL_8814B(x) ((x) & (~BITS_MU_DNGCNT_SEL_8814B))
+#define BIT_GET_MU_DNGCNT_SEL_8814B(x)                                         \
+	(((x) >> BIT_SHIFT_MU_DNGCNT_SEL_8814B) & BIT_MASK_MU_DNGCNT_SEL_8814B)
+#define BIT_SET_MU_DNGCNT_SEL_8814B(x, v)                                      \
+	(BIT_CLEAR_MU_DNGCNT_SEL_8814B(x) | BIT_MU_DNGCNT_SEL_8814B(v))
+
+#define BIT_SHIFT_MU_DNGCNT_8814B 0
+#define BIT_MASK_MU_DNGCNT_8814B 0xffff
+#define BIT_MU_DNGCNT_8814B(x)                                                 \
+	(((x) & BIT_MASK_MU_DNGCNT_8814B) << BIT_SHIFT_MU_DNGCNT_8814B)
+#define BITS_MU_DNGCNT_8814B                                                   \
+	(BIT_MASK_MU_DNGCNT_8814B << BIT_SHIFT_MU_DNGCNT_8814B)
+#define BIT_CLEAR_MU_DNGCNT_8814B(x) ((x) & (~BITS_MU_DNGCNT_8814B))
+#define BIT_GET_MU_DNGCNT_8814B(x)                                             \
+	(((x) >> BIT_SHIFT_MU_DNGCNT_8814B) & BIT_MASK_MU_DNGCNT_8814B)
+#define BIT_SET_MU_DNGCNT_8814B(x, v)                                          \
+	(BIT_CLEAR_MU_DNGCNT_8814B(x) | BIT_MU_DNGCNT_8814B(v))
+
+/* 2 REG_SWPS_CTRL_8814B */
+
+#define BIT_SHIFT_SWPS_RPT_LENGTH_8814B 8
+#define BIT_MASK_SWPS_RPT_LENGTH_8814B 0x7f
+#define BIT_SWPS_RPT_LENGTH_8814B(x)                                           \
+	(((x) & BIT_MASK_SWPS_RPT_LENGTH_8814B)                                \
+	 << BIT_SHIFT_SWPS_RPT_LENGTH_8814B)
+#define BITS_SWPS_RPT_LENGTH_8814B                                             \
+	(BIT_MASK_SWPS_RPT_LENGTH_8814B << BIT_SHIFT_SWPS_RPT_LENGTH_8814B)
+#define BIT_CLEAR_SWPS_RPT_LENGTH_8814B(x) ((x) & (~BITS_SWPS_RPT_LENGTH_8814B))
+#define BIT_GET_SWPS_RPT_LENGTH_8814B(x)                                       \
+	(((x) >> BIT_SHIFT_SWPS_RPT_LENGTH_8814B) &                            \
+	 BIT_MASK_SWPS_RPT_LENGTH_8814B)
+#define BIT_SET_SWPS_RPT_LENGTH_8814B(x, v)                                    \
+	(BIT_CLEAR_SWPS_RPT_LENGTH_8814B(x) | BIT_SWPS_RPT_LENGTH_8814B(v))
+
+#define BIT_SHIFT_MACID_SWPS_EN_SEL_8814B 2
+#define BIT_MASK_MACID_SWPS_EN_SEL_8814B 0x3
+#define BIT_MACID_SWPS_EN_SEL_8814B(x)                                         \
+	(((x) & BIT_MASK_MACID_SWPS_EN_SEL_8814B)                              \
+	 << BIT_SHIFT_MACID_SWPS_EN_SEL_8814B)
+#define BITS_MACID_SWPS_EN_SEL_8814B                                           \
+	(BIT_MASK_MACID_SWPS_EN_SEL_8814B << BIT_SHIFT_MACID_SWPS_EN_SEL_8814B)
+#define BIT_CLEAR_MACID_SWPS_EN_SEL_8814B(x)                                   \
+	((x) & (~BITS_MACID_SWPS_EN_SEL_8814B))
+#define BIT_GET_MACID_SWPS_EN_SEL_8814B(x)                                     \
+	(((x) >> BIT_SHIFT_MACID_SWPS_EN_SEL_8814B) &                          \
+	 BIT_MASK_MACID_SWPS_EN_SEL_8814B)
+#define BIT_SET_MACID_SWPS_EN_SEL_8814B(x, v)                                  \
+	(BIT_CLEAR_MACID_SWPS_EN_SEL_8814B(x) | BIT_MACID_SWPS_EN_SEL_8814B(v))
+
+#define BIT_SWPS_MANUALL_POLLING_8814B BIT(1)
+#define BIT_SWPS_EN_8814B BIT(0)
+
+/* 2 REG_SWPS_PKT_TH_8814B */
+
+#define BIT_SHIFT_SWPS_PKT_TH_8814B 0
+#define BIT_MASK_SWPS_PKT_TH_8814B 0xffff
+#define BIT_SWPS_PKT_TH_8814B(x)                                               \
+	(((x) & BIT_MASK_SWPS_PKT_TH_8814B) << BIT_SHIFT_SWPS_PKT_TH_8814B)
+#define BITS_SWPS_PKT_TH_8814B                                                 \
+	(BIT_MASK_SWPS_PKT_TH_8814B << BIT_SHIFT_SWPS_PKT_TH_8814B)
+#define BIT_CLEAR_SWPS_PKT_TH_8814B(x) ((x) & (~BITS_SWPS_PKT_TH_8814B))
+#define BIT_GET_SWPS_PKT_TH_8814B(x)                                           \
+	(((x) >> BIT_SHIFT_SWPS_PKT_TH_8814B) & BIT_MASK_SWPS_PKT_TH_8814B)
+#define BIT_SET_SWPS_PKT_TH_8814B(x, v)                                        \
+	(BIT_CLEAR_SWPS_PKT_TH_8814B(x) | BIT_SWPS_PKT_TH_8814B(v))
+
+/* 2 REG_SWPS_TIME_TH_8814B */
+
+#define BIT_SHIFT_SWPS_PSTIME_TH_8814B 16
+#define BIT_MASK_SWPS_PSTIME_TH_8814B 0xffff
+#define BIT_SWPS_PSTIME_TH_8814B(x)                                            \
+	(((x) & BIT_MASK_SWPS_PSTIME_TH_8814B)                                 \
+	 << BIT_SHIFT_SWPS_PSTIME_TH_8814B)
+#define BITS_SWPS_PSTIME_TH_8814B                                              \
+	(BIT_MASK_SWPS_PSTIME_TH_8814B << BIT_SHIFT_SWPS_PSTIME_TH_8814B)
+#define BIT_CLEAR_SWPS_PSTIME_TH_8814B(x) ((x) & (~BITS_SWPS_PSTIME_TH_8814B))
+#define BIT_GET_SWPS_PSTIME_TH_8814B(x)                                        \
+	(((x) >> BIT_SHIFT_SWPS_PSTIME_TH_8814B) &                             \
+	 BIT_MASK_SWPS_PSTIME_TH_8814B)
+#define BIT_SET_SWPS_PSTIME_TH_8814B(x, v)                                     \
+	(BIT_CLEAR_SWPS_PSTIME_TH_8814B(x) | BIT_SWPS_PSTIME_TH_8814B(v))
+
+#define BIT_SHIFT_SWPS_TIME_TH_8814B 0
+#define BIT_MASK_SWPS_TIME_TH_8814B 0xffff
+#define BIT_SWPS_TIME_TH_8814B(x)                                              \
+	(((x) & BIT_MASK_SWPS_TIME_TH_8814B) << BIT_SHIFT_SWPS_TIME_TH_8814B)
+#define BITS_SWPS_TIME_TH_8814B                                                \
+	(BIT_MASK_SWPS_TIME_TH_8814B << BIT_SHIFT_SWPS_TIME_TH_8814B)
+#define BIT_CLEAR_SWPS_TIME_TH_8814B(x) ((x) & (~BITS_SWPS_TIME_TH_8814B))
+#define BIT_GET_SWPS_TIME_TH_8814B(x)                                          \
+	(((x) >> BIT_SHIFT_SWPS_TIME_TH_8814B) & BIT_MASK_SWPS_TIME_TH_8814B)
+#define BIT_SET_SWPS_TIME_TH_8814B(x, v)                                       \
+	(BIT_CLEAR_SWPS_TIME_TH_8814B(x) | BIT_SWPS_TIME_TH_8814B(v))
+
+/* 2 REG_MACID_SWPS_EN_8814B */
+
+#define BIT_SHIFT_MACID_SWPS_EN_8814B 0
+#define BIT_MASK_MACID_SWPS_EN_8814B 0xffffffffL
+#define BIT_MACID_SWPS_EN_8814B(x)                                             \
+	(((x) & BIT_MASK_MACID_SWPS_EN_8814B) << BIT_SHIFT_MACID_SWPS_EN_8814B)
+#define BITS_MACID_SWPS_EN_8814B                                               \
+	(BIT_MASK_MACID_SWPS_EN_8814B << BIT_SHIFT_MACID_SWPS_EN_8814B)
+#define BIT_CLEAR_MACID_SWPS_EN_8814B(x) ((x) & (~BITS_MACID_SWPS_EN_8814B))
+#define BIT_GET_MACID_SWPS_EN_8814B(x)                                         \
+	(((x) >> BIT_SHIFT_MACID_SWPS_EN_8814B) & BIT_MASK_MACID_SWPS_EN_8814B)
+#define BIT_SET_MACID_SWPS_EN_8814B(x, v)                                      \
+	(BIT_CLEAR_MACID_SWPS_EN_8814B(x) | BIT_MACID_SWPS_EN_8814B(v))
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_EDCA_VO_PARAM_8814B */
+
+#define BIT_SHIFT_TXOPLIMIT_8814B 16
+#define BIT_MASK_TXOPLIMIT_8814B 0x7ff
+#define BIT_TXOPLIMIT_8814B(x)                                                 \
+	(((x) & BIT_MASK_TXOPLIMIT_8814B) << BIT_SHIFT_TXOPLIMIT_8814B)
+#define BITS_TXOPLIMIT_8814B                                                   \
+	(BIT_MASK_TXOPLIMIT_8814B << BIT_SHIFT_TXOPLIMIT_8814B)
+#define BIT_CLEAR_TXOPLIMIT_8814B(x) ((x) & (~BITS_TXOPLIMIT_8814B))
+#define BIT_GET_TXOPLIMIT_8814B(x)                                             \
+	(((x) >> BIT_SHIFT_TXOPLIMIT_8814B) & BIT_MASK_TXOPLIMIT_8814B)
+#define BIT_SET_TXOPLIMIT_8814B(x, v)                                          \
+	(BIT_CLEAR_TXOPLIMIT_8814B(x) | BIT_TXOPLIMIT_8814B(v))
+
+#define BIT_SHIFT_CW_8814B 8
+#define BIT_MASK_CW_8814B 0xff
+#define BIT_CW_8814B(x) (((x) & BIT_MASK_CW_8814B) << BIT_SHIFT_CW_8814B)
+#define BITS_CW_8814B (BIT_MASK_CW_8814B << BIT_SHIFT_CW_8814B)
+#define BIT_CLEAR_CW_8814B(x) ((x) & (~BITS_CW_8814B))
+#define BIT_GET_CW_8814B(x) (((x) >> BIT_SHIFT_CW_8814B) & BIT_MASK_CW_8814B)
+#define BIT_SET_CW_8814B(x, v) (BIT_CLEAR_CW_8814B(x) | BIT_CW_8814B(v))
+
+#define BIT_SHIFT_AIFS_8814B 0
+#define BIT_MASK_AIFS_8814B 0xff
+#define BIT_AIFS_8814B(x) (((x) & BIT_MASK_AIFS_8814B) << BIT_SHIFT_AIFS_8814B)
+#define BITS_AIFS_8814B (BIT_MASK_AIFS_8814B << BIT_SHIFT_AIFS_8814B)
+#define BIT_CLEAR_AIFS_8814B(x) ((x) & (~BITS_AIFS_8814B))
+#define BIT_GET_AIFS_8814B(x)                                                  \
+	(((x) >> BIT_SHIFT_AIFS_8814B) & BIT_MASK_AIFS_8814B)
+#define BIT_SET_AIFS_8814B(x, v) (BIT_CLEAR_AIFS_8814B(x) | BIT_AIFS_8814B(v))
+
+/* 2 REG_EDCA_VI_PARAM_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+#define BIT_SHIFT_TXOPLIMIT_8814B 16
+#define BIT_MASK_TXOPLIMIT_8814B 0x7ff
+#define BIT_TXOPLIMIT_8814B(x)                                                 \
+	(((x) & BIT_MASK_TXOPLIMIT_8814B) << BIT_SHIFT_TXOPLIMIT_8814B)
+#define BITS_TXOPLIMIT_8814B                                                   \
+	(BIT_MASK_TXOPLIMIT_8814B << BIT_SHIFT_TXOPLIMIT_8814B)
+#define BIT_CLEAR_TXOPLIMIT_8814B(x) ((x) & (~BITS_TXOPLIMIT_8814B))
+#define BIT_GET_TXOPLIMIT_8814B(x)                                             \
+	(((x) >> BIT_SHIFT_TXOPLIMIT_8814B) & BIT_MASK_TXOPLIMIT_8814B)
+#define BIT_SET_TXOPLIMIT_8814B(x, v)                                          \
+	(BIT_CLEAR_TXOPLIMIT_8814B(x) | BIT_TXOPLIMIT_8814B(v))
+
+#define BIT_SHIFT_CW_8814B 8
+#define BIT_MASK_CW_8814B 0xff
+#define BIT_CW_8814B(x) (((x) & BIT_MASK_CW_8814B) << BIT_SHIFT_CW_8814B)
+#define BITS_CW_8814B (BIT_MASK_CW_8814B << BIT_SHIFT_CW_8814B)
+#define BIT_CLEAR_CW_8814B(x) ((x) & (~BITS_CW_8814B))
+#define BIT_GET_CW_8814B(x) (((x) >> BIT_SHIFT_CW_8814B) & BIT_MASK_CW_8814B)
+#define BIT_SET_CW_8814B(x, v) (BIT_CLEAR_CW_8814B(x) | BIT_CW_8814B(v))
+
+#define BIT_SHIFT_AIFS_8814B 0
+#define BIT_MASK_AIFS_8814B 0xff
+#define BIT_AIFS_8814B(x) (((x) & BIT_MASK_AIFS_8814B) << BIT_SHIFT_AIFS_8814B)
+#define BITS_AIFS_8814B (BIT_MASK_AIFS_8814B << BIT_SHIFT_AIFS_8814B)
+#define BIT_CLEAR_AIFS_8814B(x) ((x) & (~BITS_AIFS_8814B))
+#define BIT_GET_AIFS_8814B(x)                                                  \
+	(((x) >> BIT_SHIFT_AIFS_8814B) & BIT_MASK_AIFS_8814B)
+#define BIT_SET_AIFS_8814B(x, v) (BIT_CLEAR_AIFS_8814B(x) | BIT_AIFS_8814B(v))
+
+/* 2 REG_EDCA_BE_PARAM_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+#define BIT_SHIFT_TXOPLIMIT_8814B 16
+#define BIT_MASK_TXOPLIMIT_8814B 0x7ff
+#define BIT_TXOPLIMIT_8814B(x)                                                 \
+	(((x) & BIT_MASK_TXOPLIMIT_8814B) << BIT_SHIFT_TXOPLIMIT_8814B)
+#define BITS_TXOPLIMIT_8814B                                                   \
+	(BIT_MASK_TXOPLIMIT_8814B << BIT_SHIFT_TXOPLIMIT_8814B)
+#define BIT_CLEAR_TXOPLIMIT_8814B(x) ((x) & (~BITS_TXOPLIMIT_8814B))
+#define BIT_GET_TXOPLIMIT_8814B(x)                                             \
+	(((x) >> BIT_SHIFT_TXOPLIMIT_8814B) & BIT_MASK_TXOPLIMIT_8814B)
+#define BIT_SET_TXOPLIMIT_8814B(x, v)                                          \
+	(BIT_CLEAR_TXOPLIMIT_8814B(x) | BIT_TXOPLIMIT_8814B(v))
+
+#define BIT_SHIFT_CW_8814B 8
+#define BIT_MASK_CW_8814B 0xff
+#define BIT_CW_8814B(x) (((x) & BIT_MASK_CW_8814B) << BIT_SHIFT_CW_8814B)
+#define BITS_CW_8814B (BIT_MASK_CW_8814B << BIT_SHIFT_CW_8814B)
+#define BIT_CLEAR_CW_8814B(x) ((x) & (~BITS_CW_8814B))
+#define BIT_GET_CW_8814B(x) (((x) >> BIT_SHIFT_CW_8814B) & BIT_MASK_CW_8814B)
+#define BIT_SET_CW_8814B(x, v) (BIT_CLEAR_CW_8814B(x) | BIT_CW_8814B(v))
+
+#define BIT_SHIFT_AIFS_8814B 0
+#define BIT_MASK_AIFS_8814B 0xff
+#define BIT_AIFS_8814B(x) (((x) & BIT_MASK_AIFS_8814B) << BIT_SHIFT_AIFS_8814B)
+#define BITS_AIFS_8814B (BIT_MASK_AIFS_8814B << BIT_SHIFT_AIFS_8814B)
+#define BIT_CLEAR_AIFS_8814B(x) ((x) & (~BITS_AIFS_8814B))
+#define BIT_GET_AIFS_8814B(x)                                                  \
+	(((x) >> BIT_SHIFT_AIFS_8814B) & BIT_MASK_AIFS_8814B)
+#define BIT_SET_AIFS_8814B(x, v) (BIT_CLEAR_AIFS_8814B(x) | BIT_AIFS_8814B(v))
+
+/* 2 REG_EDCA_BK_PARAM_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+#define BIT_SHIFT_TXOPLIMIT_8814B 16
+#define BIT_MASK_TXOPLIMIT_8814B 0x7ff
+#define BIT_TXOPLIMIT_8814B(x)                                                 \
+	(((x) & BIT_MASK_TXOPLIMIT_8814B) << BIT_SHIFT_TXOPLIMIT_8814B)
+#define BITS_TXOPLIMIT_8814B                                                   \
+	(BIT_MASK_TXOPLIMIT_8814B << BIT_SHIFT_TXOPLIMIT_8814B)
+#define BIT_CLEAR_TXOPLIMIT_8814B(x) ((x) & (~BITS_TXOPLIMIT_8814B))
+#define BIT_GET_TXOPLIMIT_8814B(x)                                             \
+	(((x) >> BIT_SHIFT_TXOPLIMIT_8814B) & BIT_MASK_TXOPLIMIT_8814B)
+#define BIT_SET_TXOPLIMIT_8814B(x, v)                                          \
+	(BIT_CLEAR_TXOPLIMIT_8814B(x) | BIT_TXOPLIMIT_8814B(v))
+
+#define BIT_SHIFT_CW_8814B 8
+#define BIT_MASK_CW_8814B 0xff
+#define BIT_CW_8814B(x) (((x) & BIT_MASK_CW_8814B) << BIT_SHIFT_CW_8814B)
+#define BITS_CW_8814B (BIT_MASK_CW_8814B << BIT_SHIFT_CW_8814B)
+#define BIT_CLEAR_CW_8814B(x) ((x) & (~BITS_CW_8814B))
+#define BIT_GET_CW_8814B(x) (((x) >> BIT_SHIFT_CW_8814B) & BIT_MASK_CW_8814B)
+#define BIT_SET_CW_8814B(x, v) (BIT_CLEAR_CW_8814B(x) | BIT_CW_8814B(v))
+
+#define BIT_SHIFT_AIFS_8814B 0
+#define BIT_MASK_AIFS_8814B 0xff
+#define BIT_AIFS_8814B(x) (((x) & BIT_MASK_AIFS_8814B) << BIT_SHIFT_AIFS_8814B)
+#define BITS_AIFS_8814B (BIT_MASK_AIFS_8814B << BIT_SHIFT_AIFS_8814B)
+#define BIT_CLEAR_AIFS_8814B(x) ((x) & (~BITS_AIFS_8814B))
+#define BIT_GET_AIFS_8814B(x)                                                  \
+	(((x) >> BIT_SHIFT_AIFS_8814B) & BIT_MASK_AIFS_8814B)
+#define BIT_SET_AIFS_8814B(x, v) (BIT_CLEAR_AIFS_8814B(x) | BIT_AIFS_8814B(v))
+
+/* 2 REG_BCNTCFG_8814B */
+
+#define BIT_SHIFT_BCNCW_MAX_8814B 12
+#define BIT_MASK_BCNCW_MAX_8814B 0xf
+#define BIT_BCNCW_MAX_8814B(x)                                                 \
+	(((x) & BIT_MASK_BCNCW_MAX_8814B) << BIT_SHIFT_BCNCW_MAX_8814B)
+#define BITS_BCNCW_MAX_8814B                                                   \
+	(BIT_MASK_BCNCW_MAX_8814B << BIT_SHIFT_BCNCW_MAX_8814B)
+#define BIT_CLEAR_BCNCW_MAX_8814B(x) ((x) & (~BITS_BCNCW_MAX_8814B))
+#define BIT_GET_BCNCW_MAX_8814B(x)                                             \
+	(((x) >> BIT_SHIFT_BCNCW_MAX_8814B) & BIT_MASK_BCNCW_MAX_8814B)
+#define BIT_SET_BCNCW_MAX_8814B(x, v)                                          \
+	(BIT_CLEAR_BCNCW_MAX_8814B(x) | BIT_BCNCW_MAX_8814B(v))
+
+#define BIT_SHIFT_BCNCW_MIN_8814B 8
+#define BIT_MASK_BCNCW_MIN_8814B 0xf
+#define BIT_BCNCW_MIN_8814B(x)                                                 \
+	(((x) & BIT_MASK_BCNCW_MIN_8814B) << BIT_SHIFT_BCNCW_MIN_8814B)
+#define BITS_BCNCW_MIN_8814B                                                   \
+	(BIT_MASK_BCNCW_MIN_8814B << BIT_SHIFT_BCNCW_MIN_8814B)
+#define BIT_CLEAR_BCNCW_MIN_8814B(x) ((x) & (~BITS_BCNCW_MIN_8814B))
+#define BIT_GET_BCNCW_MIN_8814B(x)                                             \
+	(((x) >> BIT_SHIFT_BCNCW_MIN_8814B) & BIT_MASK_BCNCW_MIN_8814B)
+#define BIT_SET_BCNCW_MIN_8814B(x, v)                                          \
+	(BIT_CLEAR_BCNCW_MIN_8814B(x) | BIT_BCNCW_MIN_8814B(v))
+
+#define BIT_SHIFT_BCNIFS_8814B 0
+#define BIT_MASK_BCNIFS_8814B 0xff
+#define BIT_BCNIFS_8814B(x)                                                    \
+	(((x) & BIT_MASK_BCNIFS_8814B) << BIT_SHIFT_BCNIFS_8814B)
+#define BITS_BCNIFS_8814B (BIT_MASK_BCNIFS_8814B << BIT_SHIFT_BCNIFS_8814B)
+#define BIT_CLEAR_BCNIFS_8814B(x) ((x) & (~BITS_BCNIFS_8814B))
+#define BIT_GET_BCNIFS_8814B(x)                                                \
+	(((x) >> BIT_SHIFT_BCNIFS_8814B) & BIT_MASK_BCNIFS_8814B)
+#define BIT_SET_BCNIFS_8814B(x, v)                                             \
+	(BIT_CLEAR_BCNIFS_8814B(x) | BIT_BCNIFS_8814B(v))
+
+/* 2 REG_PIFS_8814B */
+
+#define BIT_SHIFT_PIFS_8814B 0
+#define BIT_MASK_PIFS_8814B 0xff
+#define BIT_PIFS_8814B(x) (((x) & BIT_MASK_PIFS_8814B) << BIT_SHIFT_PIFS_8814B)
+#define BITS_PIFS_8814B (BIT_MASK_PIFS_8814B << BIT_SHIFT_PIFS_8814B)
+#define BIT_CLEAR_PIFS_8814B(x) ((x) & (~BITS_PIFS_8814B))
+#define BIT_GET_PIFS_8814B(x)                                                  \
+	(((x) >> BIT_SHIFT_PIFS_8814B) & BIT_MASK_PIFS_8814B)
+#define BIT_SET_PIFS_8814B(x, v) (BIT_CLEAR_PIFS_8814B(x) | BIT_PIFS_8814B(v))
+
+/* 2 REG_RDG_PIFS_8814B */
+
+#define BIT_SHIFT_RDG_PIFS_8814B 0
+#define BIT_MASK_RDG_PIFS_8814B 0xff
+#define BIT_RDG_PIFS_8814B(x)                                                  \
+	(((x) & BIT_MASK_RDG_PIFS_8814B) << BIT_SHIFT_RDG_PIFS_8814B)
+#define BITS_RDG_PIFS_8814B                                                    \
+	(BIT_MASK_RDG_PIFS_8814B << BIT_SHIFT_RDG_PIFS_8814B)
+#define BIT_CLEAR_RDG_PIFS_8814B(x) ((x) & (~BITS_RDG_PIFS_8814B))
+#define BIT_GET_RDG_PIFS_8814B(x)                                              \
+	(((x) >> BIT_SHIFT_RDG_PIFS_8814B) & BIT_MASK_RDG_PIFS_8814B)
+#define BIT_SET_RDG_PIFS_8814B(x, v)                                           \
+	(BIT_CLEAR_RDG_PIFS_8814B(x) | BIT_RDG_PIFS_8814B(v))
+
+/* 2 REG_SIFS_8814B */
+
+#define BIT_SHIFT_SIFS_OFDM_TRX_8814B 24
+#define BIT_MASK_SIFS_OFDM_TRX_8814B 0xff
+#define BIT_SIFS_OFDM_TRX_8814B(x)                                             \
+	(((x) & BIT_MASK_SIFS_OFDM_TRX_8814B) << BIT_SHIFT_SIFS_OFDM_TRX_8814B)
+#define BITS_SIFS_OFDM_TRX_8814B                                               \
+	(BIT_MASK_SIFS_OFDM_TRX_8814B << BIT_SHIFT_SIFS_OFDM_TRX_8814B)
+#define BIT_CLEAR_SIFS_OFDM_TRX_8814B(x) ((x) & (~BITS_SIFS_OFDM_TRX_8814B))
+#define BIT_GET_SIFS_OFDM_TRX_8814B(x)                                         \
+	(((x) >> BIT_SHIFT_SIFS_OFDM_TRX_8814B) & BIT_MASK_SIFS_OFDM_TRX_8814B)
+#define BIT_SET_SIFS_OFDM_TRX_8814B(x, v)                                      \
+	(BIT_CLEAR_SIFS_OFDM_TRX_8814B(x) | BIT_SIFS_OFDM_TRX_8814B(v))
+
+#define BIT_SHIFT_SIFS_CCK_TRX_8814B 16
+#define BIT_MASK_SIFS_CCK_TRX_8814B 0xff
+#define BIT_SIFS_CCK_TRX_8814B(x)                                              \
+	(((x) & BIT_MASK_SIFS_CCK_TRX_8814B) << BIT_SHIFT_SIFS_CCK_TRX_8814B)
+#define BITS_SIFS_CCK_TRX_8814B                                                \
+	(BIT_MASK_SIFS_CCK_TRX_8814B << BIT_SHIFT_SIFS_CCK_TRX_8814B)
+#define BIT_CLEAR_SIFS_CCK_TRX_8814B(x) ((x) & (~BITS_SIFS_CCK_TRX_8814B))
+#define BIT_GET_SIFS_CCK_TRX_8814B(x)                                          \
+	(((x) >> BIT_SHIFT_SIFS_CCK_TRX_8814B) & BIT_MASK_SIFS_CCK_TRX_8814B)
+#define BIT_SET_SIFS_CCK_TRX_8814B(x, v)                                       \
+	(BIT_CLEAR_SIFS_CCK_TRX_8814B(x) | BIT_SIFS_CCK_TRX_8814B(v))
+
+#define BIT_SHIFT_SIFS_OFDM_CTX_8814B 8
+#define BIT_MASK_SIFS_OFDM_CTX_8814B 0xff
+#define BIT_SIFS_OFDM_CTX_8814B(x)                                             \
+	(((x) & BIT_MASK_SIFS_OFDM_CTX_8814B) << BIT_SHIFT_SIFS_OFDM_CTX_8814B)
+#define BITS_SIFS_OFDM_CTX_8814B                                               \
+	(BIT_MASK_SIFS_OFDM_CTX_8814B << BIT_SHIFT_SIFS_OFDM_CTX_8814B)
+#define BIT_CLEAR_SIFS_OFDM_CTX_8814B(x) ((x) & (~BITS_SIFS_OFDM_CTX_8814B))
+#define BIT_GET_SIFS_OFDM_CTX_8814B(x)                                         \
+	(((x) >> BIT_SHIFT_SIFS_OFDM_CTX_8814B) & BIT_MASK_SIFS_OFDM_CTX_8814B)
+#define BIT_SET_SIFS_OFDM_CTX_8814B(x, v)                                      \
+	(BIT_CLEAR_SIFS_OFDM_CTX_8814B(x) | BIT_SIFS_OFDM_CTX_8814B(v))
+
+#define BIT_SHIFT_SIFS_CCK_CTX_8814B 0
+#define BIT_MASK_SIFS_CCK_CTX_8814B 0xff
+#define BIT_SIFS_CCK_CTX_8814B(x)                                              \
+	(((x) & BIT_MASK_SIFS_CCK_CTX_8814B) << BIT_SHIFT_SIFS_CCK_CTX_8814B)
+#define BITS_SIFS_CCK_CTX_8814B                                                \
+	(BIT_MASK_SIFS_CCK_CTX_8814B << BIT_SHIFT_SIFS_CCK_CTX_8814B)
+#define BIT_CLEAR_SIFS_CCK_CTX_8814B(x) ((x) & (~BITS_SIFS_CCK_CTX_8814B))
+#define BIT_GET_SIFS_CCK_CTX_8814B(x)                                          \
+	(((x) >> BIT_SHIFT_SIFS_CCK_CTX_8814B) & BIT_MASK_SIFS_CCK_CTX_8814B)
+#define BIT_SET_SIFS_CCK_CTX_8814B(x, v)                                       \
+	(BIT_CLEAR_SIFS_CCK_CTX_8814B(x) | BIT_SIFS_CCK_CTX_8814B(v))
+
+/* 2 REG_FORCE_BCN_IFS_V1_8814B */
+
+#define BIT_SHIFT_FORCE_BCN_IFS_8814B 0
+#define BIT_MASK_FORCE_BCN_IFS_8814B 0xff
+#define BIT_FORCE_BCN_IFS_8814B(x)                                             \
+	(((x) & BIT_MASK_FORCE_BCN_IFS_8814B) << BIT_SHIFT_FORCE_BCN_IFS_8814B)
+#define BITS_FORCE_BCN_IFS_8814B                                               \
+	(BIT_MASK_FORCE_BCN_IFS_8814B << BIT_SHIFT_FORCE_BCN_IFS_8814B)
+#define BIT_CLEAR_FORCE_BCN_IFS_8814B(x) ((x) & (~BITS_FORCE_BCN_IFS_8814B))
+#define BIT_GET_FORCE_BCN_IFS_8814B(x)                                         \
+	(((x) >> BIT_SHIFT_FORCE_BCN_IFS_8814B) & BIT_MASK_FORCE_BCN_IFS_8814B)
+#define BIT_SET_FORCE_BCN_IFS_8814B(x, v)                                      \
+	(BIT_CLEAR_FORCE_BCN_IFS_8814B(x) | BIT_FORCE_BCN_IFS_8814B(v))
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_AGGR_BREAK_TIME_8814B */
+
+#define BIT_SHIFT_AGGR_BK_TIME_8814B 0
+#define BIT_MASK_AGGR_BK_TIME_8814B 0xff
+#define BIT_AGGR_BK_TIME_8814B(x)                                              \
+	(((x) & BIT_MASK_AGGR_BK_TIME_8814B) << BIT_SHIFT_AGGR_BK_TIME_8814B)
+#define BITS_AGGR_BK_TIME_8814B                                                \
+	(BIT_MASK_AGGR_BK_TIME_8814B << BIT_SHIFT_AGGR_BK_TIME_8814B)
+#define BIT_CLEAR_AGGR_BK_TIME_8814B(x) ((x) & (~BITS_AGGR_BK_TIME_8814B))
+#define BIT_GET_AGGR_BK_TIME_8814B(x)                                          \
+	(((x) >> BIT_SHIFT_AGGR_BK_TIME_8814B) & BIT_MASK_AGGR_BK_TIME_8814B)
+#define BIT_SET_AGGR_BK_TIME_8814B(x, v)                                       \
+	(BIT_CLEAR_AGGR_BK_TIME_8814B(x) | BIT_AGGR_BK_TIME_8814B(v))
+
+/* 2 REG_SLOT_8814B */
+
+#define BIT_SHIFT_SLOT_8814B 0
+#define BIT_MASK_SLOT_8814B 0xff
+#define BIT_SLOT_8814B(x) (((x) & BIT_MASK_SLOT_8814B) << BIT_SHIFT_SLOT_8814B)
+#define BITS_SLOT_8814B (BIT_MASK_SLOT_8814B << BIT_SHIFT_SLOT_8814B)
+#define BIT_CLEAR_SLOT_8814B(x) ((x) & (~BITS_SLOT_8814B))
+#define BIT_GET_SLOT_8814B(x)                                                  \
+	(((x) >> BIT_SHIFT_SLOT_8814B) & BIT_MASK_SLOT_8814B)
+#define BIT_SET_SLOT_8814B(x, v) (BIT_CLEAR_SLOT_8814B(x) | BIT_SLOT_8814B(v))
+
+/* 2 REG_EDCA_CPUMGQ_PARAM_8814B */
+
+#define BIT_SHIFT_CW_V1_8814B 8
+#define BIT_MASK_CW_V1_8814B 0xff
+#define BIT_CW_V1_8814B(x)                                                     \
+	(((x) & BIT_MASK_CW_V1_8814B) << BIT_SHIFT_CW_V1_8814B)
+#define BITS_CW_V1_8814B (BIT_MASK_CW_V1_8814B << BIT_SHIFT_CW_V1_8814B)
+#define BIT_CLEAR_CW_V1_8814B(x) ((x) & (~BITS_CW_V1_8814B))
+#define BIT_GET_CW_V1_8814B(x)                                                 \
+	(((x) >> BIT_SHIFT_CW_V1_8814B) & BIT_MASK_CW_V1_8814B)
+#define BIT_SET_CW_V1_8814B(x, v)                                              \
+	(BIT_CLEAR_CW_V1_8814B(x) | BIT_CW_V1_8814B(v))
+
+#define BIT_SHIFT_AIFS_V1_8814B 0
+#define BIT_MASK_AIFS_V1_8814B 0xff
+#define BIT_AIFS_V1_8814B(x)                                                   \
+	(((x) & BIT_MASK_AIFS_V1_8814B) << BIT_SHIFT_AIFS_V1_8814B)
+#define BITS_AIFS_V1_8814B (BIT_MASK_AIFS_V1_8814B << BIT_SHIFT_AIFS_V1_8814B)
+#define BIT_CLEAR_AIFS_V1_8814B(x) ((x) & (~BITS_AIFS_V1_8814B))
+#define BIT_GET_AIFS_V1_8814B(x)                                               \
+	(((x) >> BIT_SHIFT_AIFS_V1_8814B) & BIT_MASK_AIFS_V1_8814B)
+#define BIT_SET_AIFS_V1_8814B(x, v)                                            \
+	(BIT_CLEAR_AIFS_V1_8814B(x) | BIT_AIFS_V1_8814B(v))
+
+/* 2 REG_CPUMGQ_PAUSE_8814B */
+#define BIT_MAC_STOP_CPUMGQ_V1_8814B BIT(0)
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_TX_PTCL_CTRL_8814B */
+#define BIT_DIS_EDCCA_8814B BIT(15)
+#define BIT_DIS_CCA_8814B BIT(14)
+#define BIT_LSIG_TXOP_TXCMD_NAV_8814B BIT(13)
+#define BIT_SIFS_BK_EN_8814B BIT(12)
+
+#define BIT_SHIFT_TXQ_NAV_MSK_8814B 8
+#define BIT_MASK_TXQ_NAV_MSK_8814B 0xf
+#define BIT_TXQ_NAV_MSK_8814B(x)                                               \
+	(((x) & BIT_MASK_TXQ_NAV_MSK_8814B) << BIT_SHIFT_TXQ_NAV_MSK_8814B)
+#define BITS_TXQ_NAV_MSK_8814B                                                 \
+	(BIT_MASK_TXQ_NAV_MSK_8814B << BIT_SHIFT_TXQ_NAV_MSK_8814B)
+#define BIT_CLEAR_TXQ_NAV_MSK_8814B(x) ((x) & (~BITS_TXQ_NAV_MSK_8814B))
+#define BIT_GET_TXQ_NAV_MSK_8814B(x)                                           \
+	(((x) >> BIT_SHIFT_TXQ_NAV_MSK_8814B) & BIT_MASK_TXQ_NAV_MSK_8814B)
+#define BIT_SET_TXQ_NAV_MSK_8814B(x, v)                                        \
+	(BIT_CLEAR_TXQ_NAV_MSK_8814B(x) | BIT_TXQ_NAV_MSK_8814B(v))
+
+#define BIT_DIS_CW_8814B BIT(7)
+#define BIT_NAV_END_TXOP_8814B BIT(6)
+#define BIT_RDG_END_TXOP_8814B BIT(5)
+#define BIT_AC_INBCN_HOLD_8814B BIT(4)
+#define BIT_MGTQ_TXOP_EN_8814B BIT(3)
+#define BIT_MGTQ_RTSMF_EN_8814B BIT(2)
+#define BIT_HIQ_RTSMF_EN_8814B BIT(1)
+#define BIT_BCN_RTSMF_EN_8814B BIT(0)
+
+/* 2 REG_TXPAUSE_8814B */
+#define BIT_STOP_BCN_HI_MGT_8814B BIT(7)
+#define BIT_MAC_STOPBCNQ_8814B BIT(6)
+#define BIT_MAC_STOPHIQ_8814B BIT(5)
+#define BIT_MAC_STOPMGQ_8814B BIT(4)
+#define BIT_MAC_STOPBK_8814B BIT(3)
+#define BIT_MAC_STOPBE_8814B BIT(2)
+#define BIT_MAC_STOPVI_8814B BIT(1)
+#define BIT_MAC_STOPVO_8814B BIT(0)
+
+/* 2 REG_DIS_TXREQ_CLR_8814B */
+#define BIT_DIS_BT_CCA_8814B BIT(7)
+#define BIT_DIS_TXREQ_CLR_HI_8814B BIT(5)
+#define BIT_DIS_TXREQ_CLR_MGQ_8814B BIT(4)
+#define BIT_DIS_TXREQ_CLR_VO_8814B BIT(3)
+#define BIT_DIS_TXREQ_CLR_VI_8814B BIT(2)
+#define BIT_DIS_TXREQ_CLR_BE_8814B BIT(1)
+#define BIT_DIS_TXREQ_CLR_BK_8814B BIT(0)
+
+/* 2 REG_RD_CTRL_8814B */
+#define BIT_EN_CLR_TXREQ_INCCA_8814B BIT(15)
+#define BIT_DIS_TX_OVER_BCNQ_8814B BIT(14)
+#define BIT_EN_BCNERR_INCCCA_8814B BIT(13)
+#define BIT_EDCCA_MSK_CNTDOWN_EN_8814B BIT(11)
+#define BIT_DIS_TXOP_CFE_8814B BIT(10)
+#define BIT_DIS_LSIG_CFE_8814B BIT(9)
+#define BIT_BKQ_RD_INIT_EN_8814B BIT(7)
+#define BIT_BEQ_RD_INIT_EN_8814B BIT(6)
+#define BIT_VIQ_RD_INIT_EN_8814B BIT(5)
+#define BIT_VOQ_RD_INIT_EN_8814B BIT(4)
+#define BIT_BKQ_RD_RESP_EN_8814B BIT(3)
+#define BIT_BEQ_RD_RESP_EN_8814B BIT(2)
+#define BIT_VIQ_RD_RESP_EN_8814B BIT(1)
+#define BIT_VOQ_RD_RESP_EN_8814B BIT(0)
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_PKT_LIFETIME_CTRL_8814B */
+#define BIT_EN_P2P_CTWND1_8814B BIT(23)
+#define BIT_EN_BKF_CLR_TXREQ_8814B BIT(22)
+#define BIT_EN_BCN_TX_BTCCA_8814B BIT(20)
+#define BIT_DIS_PKT_TX_ATIM_8814B BIT(19)
+#define BIT_DIS_BCN_DIS_CTN_8814B BIT(18)
+#define BIT_EN_NAVEND_RST_TXOP_8814B BIT(17)
+#define BIT_EN_FILTER_CCA_8814B BIT(16)
+
+#define BIT_SHIFT_CCA_FILTER_THRS_8814B 8
+#define BIT_MASK_CCA_FILTER_THRS_8814B 0xff
+#define BIT_CCA_FILTER_THRS_8814B(x)                                           \
+	(((x) & BIT_MASK_CCA_FILTER_THRS_8814B)                                \
+	 << BIT_SHIFT_CCA_FILTER_THRS_8814B)
+#define BITS_CCA_FILTER_THRS_8814B                                             \
+	(BIT_MASK_CCA_FILTER_THRS_8814B << BIT_SHIFT_CCA_FILTER_THRS_8814B)
+#define BIT_CLEAR_CCA_FILTER_THRS_8814B(x) ((x) & (~BITS_CCA_FILTER_THRS_8814B))
+#define BIT_GET_CCA_FILTER_THRS_8814B(x)                                       \
+	(((x) >> BIT_SHIFT_CCA_FILTER_THRS_8814B) &                            \
+	 BIT_MASK_CCA_FILTER_THRS_8814B)
+#define BIT_SET_CCA_FILTER_THRS_8814B(x, v)                                    \
+	(BIT_CLEAR_CCA_FILTER_THRS_8814B(x) | BIT_CCA_FILTER_THRS_8814B(v))
+
+#define BIT_SHIFT_EDCCA_THRS_8814B 0
+#define BIT_MASK_EDCCA_THRS_8814B 0xff
+#define BIT_EDCCA_THRS_8814B(x)                                                \
+	(((x) & BIT_MASK_EDCCA_THRS_8814B) << BIT_SHIFT_EDCCA_THRS_8814B)
+#define BITS_EDCCA_THRS_8814B                                                  \
+	(BIT_MASK_EDCCA_THRS_8814B << BIT_SHIFT_EDCCA_THRS_8814B)
+#define BIT_CLEAR_EDCCA_THRS_8814B(x) ((x) & (~BITS_EDCCA_THRS_8814B))
+#define BIT_GET_EDCCA_THRS_8814B(x)                                            \
+	(((x) >> BIT_SHIFT_EDCCA_THRS_8814B) & BIT_MASK_EDCCA_THRS_8814B)
+#define BIT_SET_EDCCA_THRS_8814B(x, v)                                         \
+	(BIT_CLEAR_EDCCA_THRS_8814B(x) | BIT_EDCCA_THRS_8814B(v))
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_TXOP_LIMIT_CTRL_8814B */
+
+#define BIT_SHIFT_TXOP_TBTT_CNT_8814B 24
+#define BIT_MASK_TXOP_TBTT_CNT_8814B 0xff
+#define BIT_TXOP_TBTT_CNT_8814B(x)                                             \
+	(((x) & BIT_MASK_TXOP_TBTT_CNT_8814B) << BIT_SHIFT_TXOP_TBTT_CNT_8814B)
+#define BITS_TXOP_TBTT_CNT_8814B                                               \
+	(BIT_MASK_TXOP_TBTT_CNT_8814B << BIT_SHIFT_TXOP_TBTT_CNT_8814B)
+#define BIT_CLEAR_TXOP_TBTT_CNT_8814B(x) ((x) & (~BITS_TXOP_TBTT_CNT_8814B))
+#define BIT_GET_TXOP_TBTT_CNT_8814B(x)                                         \
+	(((x) >> BIT_SHIFT_TXOP_TBTT_CNT_8814B) & BIT_MASK_TXOP_TBTT_CNT_8814B)
+#define BIT_SET_TXOP_TBTT_CNT_8814B(x, v)                                      \
+	(BIT_CLEAR_TXOP_TBTT_CNT_8814B(x) | BIT_TXOP_TBTT_CNT_8814B(v))
+
+#define BIT_SHIFT_TXOP_TBTT_CNT_SEL_8814B 20
+#define BIT_MASK_TXOP_TBTT_CNT_SEL_8814B 0xf
+#define BIT_TXOP_TBTT_CNT_SEL_8814B(x)                                         \
+	(((x) & BIT_MASK_TXOP_TBTT_CNT_SEL_8814B)                              \
+	 << BIT_SHIFT_TXOP_TBTT_CNT_SEL_8814B)
+#define BITS_TXOP_TBTT_CNT_SEL_8814B                                           \
+	(BIT_MASK_TXOP_TBTT_CNT_SEL_8814B << BIT_SHIFT_TXOP_TBTT_CNT_SEL_8814B)
+#define BIT_CLEAR_TXOP_TBTT_CNT_SEL_8814B(x)                                   \
+	((x) & (~BITS_TXOP_TBTT_CNT_SEL_8814B))
+#define BIT_GET_TXOP_TBTT_CNT_SEL_8814B(x)                                     \
+	(((x) >> BIT_SHIFT_TXOP_TBTT_CNT_SEL_8814B) &                          \
+	 BIT_MASK_TXOP_TBTT_CNT_SEL_8814B)
+#define BIT_SET_TXOP_TBTT_CNT_SEL_8814B(x, v)                                  \
+	(BIT_CLEAR_TXOP_TBTT_CNT_SEL_8814B(x) | BIT_TXOP_TBTT_CNT_SEL_8814B(v))
+
+#define BIT_SHIFT_TXOP_LMT_EN_8814B 16
+#define BIT_MASK_TXOP_LMT_EN_8814B 0xf
+#define BIT_TXOP_LMT_EN_8814B(x)                                               \
+	(((x) & BIT_MASK_TXOP_LMT_EN_8814B) << BIT_SHIFT_TXOP_LMT_EN_8814B)
+#define BITS_TXOP_LMT_EN_8814B                                                 \
+	(BIT_MASK_TXOP_LMT_EN_8814B << BIT_SHIFT_TXOP_LMT_EN_8814B)
+#define BIT_CLEAR_TXOP_LMT_EN_8814B(x) ((x) & (~BITS_TXOP_LMT_EN_8814B))
+#define BIT_GET_TXOP_LMT_EN_8814B(x)                                           \
+	(((x) >> BIT_SHIFT_TXOP_LMT_EN_8814B) & BIT_MASK_TXOP_LMT_EN_8814B)
+#define BIT_SET_TXOP_LMT_EN_8814B(x, v)                                        \
+	(BIT_CLEAR_TXOP_LMT_EN_8814B(x) | BIT_TXOP_LMT_EN_8814B(v))
+
+#define BIT_SHIFT_TXOP_LMT_TX_TIME_8814B 8
+#define BIT_MASK_TXOP_LMT_TX_TIME_8814B 0xff
+#define BIT_TXOP_LMT_TX_TIME_8814B(x)                                          \
+	(((x) & BIT_MASK_TXOP_LMT_TX_TIME_8814B)                               \
+	 << BIT_SHIFT_TXOP_LMT_TX_TIME_8814B)
+#define BITS_TXOP_LMT_TX_TIME_8814B                                            \
+	(BIT_MASK_TXOP_LMT_TX_TIME_8814B << BIT_SHIFT_TXOP_LMT_TX_TIME_8814B)
+#define BIT_CLEAR_TXOP_LMT_TX_TIME_8814B(x)                                    \
+	((x) & (~BITS_TXOP_LMT_TX_TIME_8814B))
+#define BIT_GET_TXOP_LMT_TX_TIME_8814B(x)                                      \
+	(((x) >> BIT_SHIFT_TXOP_LMT_TX_TIME_8814B) &                           \
+	 BIT_MASK_TXOP_LMT_TX_TIME_8814B)
+#define BIT_SET_TXOP_LMT_TX_TIME_8814B(x, v)                                   \
+	(BIT_CLEAR_TXOP_LMT_TX_TIME_8814B(x) | BIT_TXOP_LMT_TX_TIME_8814B(v))
+
+#define BIT_TXOP_CNT_TRIGGER_RESET_8814B BIT(7)
+
+#define BIT_SHIFT_TXOP_LMT_PKT_NUM_8814B 0
+#define BIT_MASK_TXOP_LMT_PKT_NUM_8814B 0x3f
+#define BIT_TXOP_LMT_PKT_NUM_8814B(x)                                          \
+	(((x) & BIT_MASK_TXOP_LMT_PKT_NUM_8814B)                               \
+	 << BIT_SHIFT_TXOP_LMT_PKT_NUM_8814B)
+#define BITS_TXOP_LMT_PKT_NUM_8814B                                            \
+	(BIT_MASK_TXOP_LMT_PKT_NUM_8814B << BIT_SHIFT_TXOP_LMT_PKT_NUM_8814B)
+#define BIT_CLEAR_TXOP_LMT_PKT_NUM_8814B(x)                                    \
+	((x) & (~BITS_TXOP_LMT_PKT_NUM_8814B))
+#define BIT_GET_TXOP_LMT_PKT_NUM_8814B(x)                                      \
+	(((x) >> BIT_SHIFT_TXOP_LMT_PKT_NUM_8814B) &                           \
+	 BIT_MASK_TXOP_LMT_PKT_NUM_8814B)
+#define BIT_SET_TXOP_LMT_PKT_NUM_8814B(x, v)                                   \
+	(BIT_CLEAR_TXOP_LMT_PKT_NUM_8814B(x) | BIT_TXOP_LMT_PKT_NUM_8814B(v))
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_CCA_TXEN_CNT_8814B */
+#define BIT_ENABLE_STOP_UPDATE_NAV_8814B BIT(21)
+#define BIT_ENABLE_GEN_RANDON_SLOT_TX_8814B BIT(20)
+#define BIT_ENABLE_RANDOM_SHIFT_TX_8814B BIT(19)
+#define BIT_ENABLE_EDCA_REF_FUNCTION_8814B BIT(18)
+#define BIT_CCA_TXEN_CNT_SWITCH_8814B BIT(17)
+#define BIT_CCA_TXEN_CNT_EN_8814B BIT(16)
+
+#define BIT_SHIFT_CCA_TXEN_BIG_CNT_8814B 8
+#define BIT_MASK_CCA_TXEN_BIG_CNT_8814B 0xff
+#define BIT_CCA_TXEN_BIG_CNT_8814B(x)                                          \
+	(((x) & BIT_MASK_CCA_TXEN_BIG_CNT_8814B)                               \
+	 << BIT_SHIFT_CCA_TXEN_BIG_CNT_8814B)
+#define BITS_CCA_TXEN_BIG_CNT_8814B                                            \
+	(BIT_MASK_CCA_TXEN_BIG_CNT_8814B << BIT_SHIFT_CCA_TXEN_BIG_CNT_8814B)
+#define BIT_CLEAR_CCA_TXEN_BIG_CNT_8814B(x)                                    \
+	((x) & (~BITS_CCA_TXEN_BIG_CNT_8814B))
+#define BIT_GET_CCA_TXEN_BIG_CNT_8814B(x)                                      \
+	(((x) >> BIT_SHIFT_CCA_TXEN_BIG_CNT_8814B) &                           \
+	 BIT_MASK_CCA_TXEN_BIG_CNT_8814B)
+#define BIT_SET_CCA_TXEN_BIG_CNT_8814B(x, v)                                   \
+	(BIT_CLEAR_CCA_TXEN_BIG_CNT_8814B(x) | BIT_CCA_TXEN_BIG_CNT_8814B(v))
+
+#define BIT_SHIFT_CCA_TXEN_SMALL_CNT_8814B 0
+#define BIT_MASK_CCA_TXEN_SMALL_CNT_8814B 0xff
+#define BIT_CCA_TXEN_SMALL_CNT_8814B(x)                                        \
+	(((x) & BIT_MASK_CCA_TXEN_SMALL_CNT_8814B)                             \
+	 << BIT_SHIFT_CCA_TXEN_SMALL_CNT_8814B)
+#define BITS_CCA_TXEN_SMALL_CNT_8814B                                          \
+	(BIT_MASK_CCA_TXEN_SMALL_CNT_8814B                                     \
+	 << BIT_SHIFT_CCA_TXEN_SMALL_CNT_8814B)
+#define BIT_CLEAR_CCA_TXEN_SMALL_CNT_8814B(x)                                  \
+	((x) & (~BITS_CCA_TXEN_SMALL_CNT_8814B))
+#define BIT_GET_CCA_TXEN_SMALL_CNT_8814B(x)                                    \
+	(((x) >> BIT_SHIFT_CCA_TXEN_SMALL_CNT_8814B) &                         \
+	 BIT_MASK_CCA_TXEN_SMALL_CNT_8814B)
+#define BIT_SET_CCA_TXEN_SMALL_CNT_8814B(x, v)                                 \
+	(BIT_CLEAR_CCA_TXEN_SMALL_CNT_8814B(x) |                               \
+	 BIT_CCA_TXEN_SMALL_CNT_8814B(v))
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_MAX_INTER_COLLISION_8814B */
+
+#define BIT_SHIFT_MAX_INTER_COLLISION_BK_8814B 24
+#define BIT_MASK_MAX_INTER_COLLISION_BK_8814B 0xff
+#define BIT_MAX_INTER_COLLISION_BK_8814B(x)                                    \
+	(((x) & BIT_MASK_MAX_INTER_COLLISION_BK_8814B)                         \
+	 << BIT_SHIFT_MAX_INTER_COLLISION_BK_8814B)
+#define BITS_MAX_INTER_COLLISION_BK_8814B                                      \
+	(BIT_MASK_MAX_INTER_COLLISION_BK_8814B                                 \
+	 << BIT_SHIFT_MAX_INTER_COLLISION_BK_8814B)
+#define BIT_CLEAR_MAX_INTER_COLLISION_BK_8814B(x)                              \
+	((x) & (~BITS_MAX_INTER_COLLISION_BK_8814B))
+#define BIT_GET_MAX_INTER_COLLISION_BK_8814B(x)                                \
+	(((x) >> BIT_SHIFT_MAX_INTER_COLLISION_BK_8814B) &                     \
+	 BIT_MASK_MAX_INTER_COLLISION_BK_8814B)
+#define BIT_SET_MAX_INTER_COLLISION_BK_8814B(x, v)                             \
+	(BIT_CLEAR_MAX_INTER_COLLISION_BK_8814B(x) |                           \
+	 BIT_MAX_INTER_COLLISION_BK_8814B(v))
+
+#define BIT_SHIFT_MAX_INTER_COLLISION_BE_8814B 16
+#define BIT_MASK_MAX_INTER_COLLISION_BE_8814B 0xff
+#define BIT_MAX_INTER_COLLISION_BE_8814B(x)                                    \
+	(((x) & BIT_MASK_MAX_INTER_COLLISION_BE_8814B)                         \
+	 << BIT_SHIFT_MAX_INTER_COLLISION_BE_8814B)
+#define BITS_MAX_INTER_COLLISION_BE_8814B                                      \
+	(BIT_MASK_MAX_INTER_COLLISION_BE_8814B                                 \
+	 << BIT_SHIFT_MAX_INTER_COLLISION_BE_8814B)
+#define BIT_CLEAR_MAX_INTER_COLLISION_BE_8814B(x)                              \
+	((x) & (~BITS_MAX_INTER_COLLISION_BE_8814B))
+#define BIT_GET_MAX_INTER_COLLISION_BE_8814B(x)                                \
+	(((x) >> BIT_SHIFT_MAX_INTER_COLLISION_BE_8814B) &                     \
+	 BIT_MASK_MAX_INTER_COLLISION_BE_8814B)
+#define BIT_SET_MAX_INTER_COLLISION_BE_8814B(x, v)                             \
+	(BIT_CLEAR_MAX_INTER_COLLISION_BE_8814B(x) |                           \
+	 BIT_MAX_INTER_COLLISION_BE_8814B(v))
+
+#define BIT_SHIFT_MAX_INTER_COLLISION_VI_8814B 8
+#define BIT_MASK_MAX_INTER_COLLISION_VI_8814B 0xff
+#define BIT_MAX_INTER_COLLISION_VI_8814B(x)                                    \
+	(((x) & BIT_MASK_MAX_INTER_COLLISION_VI_8814B)                         \
+	 << BIT_SHIFT_MAX_INTER_COLLISION_VI_8814B)
+#define BITS_MAX_INTER_COLLISION_VI_8814B                                      \
+	(BIT_MASK_MAX_INTER_COLLISION_VI_8814B                                 \
+	 << BIT_SHIFT_MAX_INTER_COLLISION_VI_8814B)
+#define BIT_CLEAR_MAX_INTER_COLLISION_VI_8814B(x)                              \
+	((x) & (~BITS_MAX_INTER_COLLISION_VI_8814B))
+#define BIT_GET_MAX_INTER_COLLISION_VI_8814B(x)                                \
+	(((x) >> BIT_SHIFT_MAX_INTER_COLLISION_VI_8814B) &                     \
+	 BIT_MASK_MAX_INTER_COLLISION_VI_8814B)
+#define BIT_SET_MAX_INTER_COLLISION_VI_8814B(x, v)                             \
+	(BIT_CLEAR_MAX_INTER_COLLISION_VI_8814B(x) |                           \
+	 BIT_MAX_INTER_COLLISION_VI_8814B(v))
+
+#define BIT_SHIFT_MAX_INTER_COLLISION_VO_8814B 0
+#define BIT_MASK_MAX_INTER_COLLISION_VO_8814B 0xff
+#define BIT_MAX_INTER_COLLISION_VO_8814B(x)                                    \
+	(((x) & BIT_MASK_MAX_INTER_COLLISION_VO_8814B)                         \
+	 << BIT_SHIFT_MAX_INTER_COLLISION_VO_8814B)
+#define BITS_MAX_INTER_COLLISION_VO_8814B                                      \
+	(BIT_MASK_MAX_INTER_COLLISION_VO_8814B                                 \
+	 << BIT_SHIFT_MAX_INTER_COLLISION_VO_8814B)
+#define BIT_CLEAR_MAX_INTER_COLLISION_VO_8814B(x)                              \
+	((x) & (~BITS_MAX_INTER_COLLISION_VO_8814B))
+#define BIT_GET_MAX_INTER_COLLISION_VO_8814B(x)                                \
+	(((x) >> BIT_SHIFT_MAX_INTER_COLLISION_VO_8814B) &                     \
+	 BIT_MASK_MAX_INTER_COLLISION_VO_8814B)
+#define BIT_SET_MAX_INTER_COLLISION_VO_8814B(x, v)                             \
+	(BIT_CLEAR_MAX_INTER_COLLISION_VO_8814B(x) |                           \
+	 BIT_MAX_INTER_COLLISION_VO_8814B(v))
+
+/* 2 REG_MAX_INTER_COLLISION_CNT_8814B */
+#define BIT_MAX_INTER_COLLISION_EN_8814B BIT(16)
+
+#define BIT_SHIFT_MAX_INTER_COLLISION_CNT_BK_8814B 12
+#define BIT_MASK_MAX_INTER_COLLISION_CNT_BK_8814B 0xf
+#define BIT_MAX_INTER_COLLISION_CNT_BK_8814B(x)                                \
+	(((x) & BIT_MASK_MAX_INTER_COLLISION_CNT_BK_8814B)                     \
+	 << BIT_SHIFT_MAX_INTER_COLLISION_CNT_BK_8814B)
+#define BITS_MAX_INTER_COLLISION_CNT_BK_8814B                                  \
+	(BIT_MASK_MAX_INTER_COLLISION_CNT_BK_8814B                             \
+	 << BIT_SHIFT_MAX_INTER_COLLISION_CNT_BK_8814B)
+#define BIT_CLEAR_MAX_INTER_COLLISION_CNT_BK_8814B(x)                          \
+	((x) & (~BITS_MAX_INTER_COLLISION_CNT_BK_8814B))
+#define BIT_GET_MAX_INTER_COLLISION_CNT_BK_8814B(x)                            \
+	(((x) >> BIT_SHIFT_MAX_INTER_COLLISION_CNT_BK_8814B) &                 \
+	 BIT_MASK_MAX_INTER_COLLISION_CNT_BK_8814B)
+#define BIT_SET_MAX_INTER_COLLISION_CNT_BK_8814B(x, v)                         \
+	(BIT_CLEAR_MAX_INTER_COLLISION_CNT_BK_8814B(x) |                       \
+	 BIT_MAX_INTER_COLLISION_CNT_BK_8814B(v))
+
+#define BIT_SHIFT_MAX_INTER_COLLISION_CNT_BE_8814B 8
+#define BIT_MASK_MAX_INTER_COLLISION_CNT_BE_8814B 0xf
+#define BIT_MAX_INTER_COLLISION_CNT_BE_8814B(x)                                \
+	(((x) & BIT_MASK_MAX_INTER_COLLISION_CNT_BE_8814B)                     \
+	 << BIT_SHIFT_MAX_INTER_COLLISION_CNT_BE_8814B)
+#define BITS_MAX_INTER_COLLISION_CNT_BE_8814B                                  \
+	(BIT_MASK_MAX_INTER_COLLISION_CNT_BE_8814B                             \
+	 << BIT_SHIFT_MAX_INTER_COLLISION_CNT_BE_8814B)
+#define BIT_CLEAR_MAX_INTER_COLLISION_CNT_BE_8814B(x)                          \
+	((x) & (~BITS_MAX_INTER_COLLISION_CNT_BE_8814B))
+#define BIT_GET_MAX_INTER_COLLISION_CNT_BE_8814B(x)                            \
+	(((x) >> BIT_SHIFT_MAX_INTER_COLLISION_CNT_BE_8814B) &                 \
+	 BIT_MASK_MAX_INTER_COLLISION_CNT_BE_8814B)
+#define BIT_SET_MAX_INTER_COLLISION_CNT_BE_8814B(x, v)                         \
+	(BIT_CLEAR_MAX_INTER_COLLISION_CNT_BE_8814B(x) |                       \
+	 BIT_MAX_INTER_COLLISION_CNT_BE_8814B(v))
+
+#define BIT_SHIFT_MAX_INTER_COLLISION_CNT_VI_8814B 4
+#define BIT_MASK_MAX_INTER_COLLISION_CNT_VI_8814B 0xf
+#define BIT_MAX_INTER_COLLISION_CNT_VI_8814B(x)                                \
+	(((x) & BIT_MASK_MAX_INTER_COLLISION_CNT_VI_8814B)                     \
+	 << BIT_SHIFT_MAX_INTER_COLLISION_CNT_VI_8814B)
+#define BITS_MAX_INTER_COLLISION_CNT_VI_8814B                                  \
+	(BIT_MASK_MAX_INTER_COLLISION_CNT_VI_8814B                             \
+	 << BIT_SHIFT_MAX_INTER_COLLISION_CNT_VI_8814B)
+#define BIT_CLEAR_MAX_INTER_COLLISION_CNT_VI_8814B(x)                          \
+	((x) & (~BITS_MAX_INTER_COLLISION_CNT_VI_8814B))
+#define BIT_GET_MAX_INTER_COLLISION_CNT_VI_8814B(x)                            \
+	(((x) >> BIT_SHIFT_MAX_INTER_COLLISION_CNT_VI_8814B) &                 \
+	 BIT_MASK_MAX_INTER_COLLISION_CNT_VI_8814B)
+#define BIT_SET_MAX_INTER_COLLISION_CNT_VI_8814B(x, v)                         \
+	(BIT_CLEAR_MAX_INTER_COLLISION_CNT_VI_8814B(x) |                       \
+	 BIT_MAX_INTER_COLLISION_CNT_VI_8814B(v))
+
+#define BIT_SHIFT_MAX_INTER_COLLISION_CNT_VO_8814B 0
+#define BIT_MASK_MAX_INTER_COLLISION_CNT_VO_8814B 0xf
+#define BIT_MAX_INTER_COLLISION_CNT_VO_8814B(x)                                \
+	(((x) & BIT_MASK_MAX_INTER_COLLISION_CNT_VO_8814B)                     \
+	 << BIT_SHIFT_MAX_INTER_COLLISION_CNT_VO_8814B)
+#define BITS_MAX_INTER_COLLISION_CNT_VO_8814B                                  \
+	(BIT_MASK_MAX_INTER_COLLISION_CNT_VO_8814B                             \
+	 << BIT_SHIFT_MAX_INTER_COLLISION_CNT_VO_8814B)
+#define BIT_CLEAR_MAX_INTER_COLLISION_CNT_VO_8814B(x)                          \
+	((x) & (~BITS_MAX_INTER_COLLISION_CNT_VO_8814B))
+#define BIT_GET_MAX_INTER_COLLISION_CNT_VO_8814B(x)                            \
+	(((x) >> BIT_SHIFT_MAX_INTER_COLLISION_CNT_VO_8814B) &                 \
+	 BIT_MASK_MAX_INTER_COLLISION_CNT_VO_8814B)
+#define BIT_SET_MAX_INTER_COLLISION_CNT_VO_8814B(x, v)                         \
+	(BIT_CLEAR_MAX_INTER_COLLISION_CNT_VO_8814B(x) |                       \
+	 BIT_MAX_INTER_COLLISION_CNT_VO_8814B(v))
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_RD_NAV_NXT_8814B */
+
+#define BIT_SHIFT_RD_NAV_PROT_NXT_8814B 0
+#define BIT_MASK_RD_NAV_PROT_NXT_8814B 0xffff
+#define BIT_RD_NAV_PROT_NXT_8814B(x)                                           \
+	(((x) & BIT_MASK_RD_NAV_PROT_NXT_8814B)                                \
+	 << BIT_SHIFT_RD_NAV_PROT_NXT_8814B)
+#define BITS_RD_NAV_PROT_NXT_8814B                                             \
+	(BIT_MASK_RD_NAV_PROT_NXT_8814B << BIT_SHIFT_RD_NAV_PROT_NXT_8814B)
+#define BIT_CLEAR_RD_NAV_PROT_NXT_8814B(x) ((x) & (~BITS_RD_NAV_PROT_NXT_8814B))
+#define BIT_GET_RD_NAV_PROT_NXT_8814B(x)                                       \
+	(((x) >> BIT_SHIFT_RD_NAV_PROT_NXT_8814B) &                            \
+	 BIT_MASK_RD_NAV_PROT_NXT_8814B)
+#define BIT_SET_RD_NAV_PROT_NXT_8814B(x, v)                                    \
+	(BIT_CLEAR_RD_NAV_PROT_NXT_8814B(x) | BIT_RD_NAV_PROT_NXT_8814B(v))
+
+/* 2 REG_NAV_PROT_LEN_8814B */
+
+#define BIT_SHIFT_NAV_PROT_LEN_8814B 0
+#define BIT_MASK_NAV_PROT_LEN_8814B 0xffff
+#define BIT_NAV_PROT_LEN_8814B(x)                                              \
+	(((x) & BIT_MASK_NAV_PROT_LEN_8814B) << BIT_SHIFT_NAV_PROT_LEN_8814B)
+#define BITS_NAV_PROT_LEN_8814B                                                \
+	(BIT_MASK_NAV_PROT_LEN_8814B << BIT_SHIFT_NAV_PROT_LEN_8814B)
+#define BIT_CLEAR_NAV_PROT_LEN_8814B(x) ((x) & (~BITS_NAV_PROT_LEN_8814B))
+#define BIT_GET_NAV_PROT_LEN_8814B(x)                                          \
+	(((x) >> BIT_SHIFT_NAV_PROT_LEN_8814B) & BIT_MASK_NAV_PROT_LEN_8814B)
+#define BIT_SET_NAV_PROT_LEN_8814B(x, v)                                       \
+	(BIT_CLEAR_NAV_PROT_LEN_8814B(x) | BIT_NAV_PROT_LEN_8814B(v))
+
+/* 2 REG_FTM_PTT_8814B */
+
+#define BIT_SHIFT_FTM_PTT_TSF_R2T_SEL_8814B 22
+#define BIT_MASK_FTM_PTT_TSF_R2T_SEL_8814B 0x7
+#define BIT_FTM_PTT_TSF_R2T_SEL_8814B(x)                                       \
+	(((x) & BIT_MASK_FTM_PTT_TSF_R2T_SEL_8814B)                            \
+	 << BIT_SHIFT_FTM_PTT_TSF_R2T_SEL_8814B)
+#define BITS_FTM_PTT_TSF_R2T_SEL_8814B                                         \
+	(BIT_MASK_FTM_PTT_TSF_R2T_SEL_8814B                                    \
+	 << BIT_SHIFT_FTM_PTT_TSF_R2T_SEL_8814B)
+#define BIT_CLEAR_FTM_PTT_TSF_R2T_SEL_8814B(x)                                 \
+	((x) & (~BITS_FTM_PTT_TSF_R2T_SEL_8814B))
+#define BIT_GET_FTM_PTT_TSF_R2T_SEL_8814B(x)                                   \
+	(((x) >> BIT_SHIFT_FTM_PTT_TSF_R2T_SEL_8814B) &                        \
+	 BIT_MASK_FTM_PTT_TSF_R2T_SEL_8814B)
+#define BIT_SET_FTM_PTT_TSF_R2T_SEL_8814B(x, v)                                \
+	(BIT_CLEAR_FTM_PTT_TSF_R2T_SEL_8814B(x) |                              \
+	 BIT_FTM_PTT_TSF_R2T_SEL_8814B(v))
+
+#define BIT_SHIFT_FTM_PTT_TSF_T2R_SEL_8814B 19
+#define BIT_MASK_FTM_PTT_TSF_T2R_SEL_8814B 0x7
+#define BIT_FTM_PTT_TSF_T2R_SEL_8814B(x)                                       \
+	(((x) & BIT_MASK_FTM_PTT_TSF_T2R_SEL_8814B)                            \
+	 << BIT_SHIFT_FTM_PTT_TSF_T2R_SEL_8814B)
+#define BITS_FTM_PTT_TSF_T2R_SEL_8814B                                         \
+	(BIT_MASK_FTM_PTT_TSF_T2R_SEL_8814B                                    \
+	 << BIT_SHIFT_FTM_PTT_TSF_T2R_SEL_8814B)
+#define BIT_CLEAR_FTM_PTT_TSF_T2R_SEL_8814B(x)                                 \
+	((x) & (~BITS_FTM_PTT_TSF_T2R_SEL_8814B))
+#define BIT_GET_FTM_PTT_TSF_T2R_SEL_8814B(x)                                   \
+	(((x) >> BIT_SHIFT_FTM_PTT_TSF_T2R_SEL_8814B) &                        \
+	 BIT_MASK_FTM_PTT_TSF_T2R_SEL_8814B)
+#define BIT_SET_FTM_PTT_TSF_T2R_SEL_8814B(x, v)                                \
+	(BIT_CLEAR_FTM_PTT_TSF_T2R_SEL_8814B(x) |                              \
+	 BIT_FTM_PTT_TSF_T2R_SEL_8814B(v))
+
+#define BIT_SHIFT_FTM_PTT_TSF_SEL_8814B 16
+#define BIT_MASK_FTM_PTT_TSF_SEL_8814B 0x7
+#define BIT_FTM_PTT_TSF_SEL_8814B(x)                                           \
+	(((x) & BIT_MASK_FTM_PTT_TSF_SEL_8814B)                                \
+	 << BIT_SHIFT_FTM_PTT_TSF_SEL_8814B)
+#define BITS_FTM_PTT_TSF_SEL_8814B                                             \
+	(BIT_MASK_FTM_PTT_TSF_SEL_8814B << BIT_SHIFT_FTM_PTT_TSF_SEL_8814B)
+#define BIT_CLEAR_FTM_PTT_TSF_SEL_8814B(x) ((x) & (~BITS_FTM_PTT_TSF_SEL_8814B))
+#define BIT_GET_FTM_PTT_TSF_SEL_8814B(x)                                       \
+	(((x) >> BIT_SHIFT_FTM_PTT_TSF_SEL_8814B) &                            \
+	 BIT_MASK_FTM_PTT_TSF_SEL_8814B)
+#define BIT_SET_FTM_PTT_TSF_SEL_8814B(x, v)                                    \
+	(BIT_CLEAR_FTM_PTT_TSF_SEL_8814B(x) | BIT_FTM_PTT_TSF_SEL_8814B(v))
+
+#define BIT_SHIFT_FTM_PTT_VALUE_8814B 0
+#define BIT_MASK_FTM_PTT_VALUE_8814B 0xffff
+#define BIT_FTM_PTT_VALUE_8814B(x)                                             \
+	(((x) & BIT_MASK_FTM_PTT_VALUE_8814B) << BIT_SHIFT_FTM_PTT_VALUE_8814B)
+#define BITS_FTM_PTT_VALUE_8814B                                               \
+	(BIT_MASK_FTM_PTT_VALUE_8814B << BIT_SHIFT_FTM_PTT_VALUE_8814B)
+#define BIT_CLEAR_FTM_PTT_VALUE_8814B(x) ((x) & (~BITS_FTM_PTT_VALUE_8814B))
+#define BIT_GET_FTM_PTT_VALUE_8814B(x)                                         \
+	(((x) >> BIT_SHIFT_FTM_PTT_VALUE_8814B) & BIT_MASK_FTM_PTT_VALUE_8814B)
+#define BIT_SET_FTM_PTT_VALUE_8814B(x, v)                                      \
+	(BIT_CLEAR_FTM_PTT_VALUE_8814B(x) | BIT_FTM_PTT_VALUE_8814B(v))
+
+/* 2 REG_FTM_TSF_8814B */
+
+#define BIT_SHIFT_FTM_T2_TSF_8814B 16
+#define BIT_MASK_FTM_T2_TSF_8814B 0xffff
+#define BIT_FTM_T2_TSF_8814B(x)                                                \
+	(((x) & BIT_MASK_FTM_T2_TSF_8814B) << BIT_SHIFT_FTM_T2_TSF_8814B)
+#define BITS_FTM_T2_TSF_8814B                                                  \
+	(BIT_MASK_FTM_T2_TSF_8814B << BIT_SHIFT_FTM_T2_TSF_8814B)
+#define BIT_CLEAR_FTM_T2_TSF_8814B(x) ((x) & (~BITS_FTM_T2_TSF_8814B))
+#define BIT_GET_FTM_T2_TSF_8814B(x)                                            \
+	(((x) >> BIT_SHIFT_FTM_T2_TSF_8814B) & BIT_MASK_FTM_T2_TSF_8814B)
+#define BIT_SET_FTM_T2_TSF_8814B(x, v)                                         \
+	(BIT_CLEAR_FTM_T2_TSF_8814B(x) | BIT_FTM_T2_TSF_8814B(v))
+
+#define BIT_SHIFT_FTM_T1_TSF_8814B 0
+#define BIT_MASK_FTM_T1_TSF_8814B 0xffff
+#define BIT_FTM_T1_TSF_8814B(x)                                                \
+	(((x) & BIT_MASK_FTM_T1_TSF_8814B) << BIT_SHIFT_FTM_T1_TSF_8814B)
+#define BITS_FTM_T1_TSF_8814B                                                  \
+	(BIT_MASK_FTM_T1_TSF_8814B << BIT_SHIFT_FTM_T1_TSF_8814B)
+#define BIT_CLEAR_FTM_T1_TSF_8814B(x) ((x) & (~BITS_FTM_T1_TSF_8814B))
+#define BIT_GET_FTM_T1_TSF_8814B(x)                                            \
+	(((x) >> BIT_SHIFT_FTM_T1_TSF_8814B) & BIT_MASK_FTM_T1_TSF_8814B)
+#define BIT_SET_FTM_T1_TSF_8814B(x, v)                                         \
+	(BIT_CLEAR_FTM_T1_TSF_8814B(x) | BIT_FTM_T1_TSF_8814B(v))
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_HGQ_TIMEOUT_PERIOD_8814B */
+
+#define BIT_SHIFT_HGQ_TIMEOUT_PERIOD_8814B 0
+#define BIT_MASK_HGQ_TIMEOUT_PERIOD_8814B 0xff
+#define BIT_HGQ_TIMEOUT_PERIOD_8814B(x)                                        \
+	(((x) & BIT_MASK_HGQ_TIMEOUT_PERIOD_8814B)                             \
+	 << BIT_SHIFT_HGQ_TIMEOUT_PERIOD_8814B)
+#define BITS_HGQ_TIMEOUT_PERIOD_8814B                                          \
+	(BIT_MASK_HGQ_TIMEOUT_PERIOD_8814B                                     \
+	 << BIT_SHIFT_HGQ_TIMEOUT_PERIOD_8814B)
+#define BIT_CLEAR_HGQ_TIMEOUT_PERIOD_8814B(x)                                  \
+	((x) & (~BITS_HGQ_TIMEOUT_PERIOD_8814B))
+#define BIT_GET_HGQ_TIMEOUT_PERIOD_8814B(x)                                    \
+	(((x) >> BIT_SHIFT_HGQ_TIMEOUT_PERIOD_8814B) &                         \
+	 BIT_MASK_HGQ_TIMEOUT_PERIOD_8814B)
+#define BIT_SET_HGQ_TIMEOUT_PERIOD_8814B(x, v)                                 \
+	(BIT_CLEAR_HGQ_TIMEOUT_PERIOD_8814B(x) |                               \
+	 BIT_HGQ_TIMEOUT_PERIOD_8814B(v))
+
+/* 2 REG_TXCMD_TIMEOUT_PERIOD_8814B */
+
+#define BIT_SHIFT_TXCMD_TIMEOUT_PERIOD_8814B 0
+#define BIT_MASK_TXCMD_TIMEOUT_PERIOD_8814B 0xff
+#define BIT_TXCMD_TIMEOUT_PERIOD_8814B(x)                                      \
+	(((x) & BIT_MASK_TXCMD_TIMEOUT_PERIOD_8814B)                           \
+	 << BIT_SHIFT_TXCMD_TIMEOUT_PERIOD_8814B)
+#define BITS_TXCMD_TIMEOUT_PERIOD_8814B                                        \
+	(BIT_MASK_TXCMD_TIMEOUT_PERIOD_8814B                                   \
+	 << BIT_SHIFT_TXCMD_TIMEOUT_PERIOD_8814B)
+#define BIT_CLEAR_TXCMD_TIMEOUT_PERIOD_8814B(x)                                \
+	((x) & (~BITS_TXCMD_TIMEOUT_PERIOD_8814B))
+#define BIT_GET_TXCMD_TIMEOUT_PERIOD_8814B(x)                                  \
+	(((x) >> BIT_SHIFT_TXCMD_TIMEOUT_PERIOD_8814B) &                       \
+	 BIT_MASK_TXCMD_TIMEOUT_PERIOD_8814B)
+#define BIT_SET_TXCMD_TIMEOUT_PERIOD_8814B(x, v)                               \
+	(BIT_CLEAR_TXCMD_TIMEOUT_PERIOD_8814B(x) |                             \
+	 BIT_TXCMD_TIMEOUT_PERIOD_8814B(v))
+
+/* 2 REG_MISC_CTRL_8814B */
+#define BIT_DIS_SECONDARY_CCA_80M_8814B BIT(2)
+#define BIT_DIS_SECONDARY_CCA_40M_8814B BIT(1)
+#define BIT_DIS_SECONDARY_CCA_20M_8814B BIT(0)
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_TXOP_MIN_8814B */
+#define BIT_HIQ_NAV_BREAK_EN_8814B BIT(15)
+#define BIT_MGQ_NAV_BREAK_EN_8814B BIT(14)
+
+#define BIT_SHIFT_TXOP_MIN_8814B 0
+#define BIT_MASK_TXOP_MIN_8814B 0x3fff
+#define BIT_TXOP_MIN_8814B(x)                                                  \
+	(((x) & BIT_MASK_TXOP_MIN_8814B) << BIT_SHIFT_TXOP_MIN_8814B)
+#define BITS_TXOP_MIN_8814B                                                    \
+	(BIT_MASK_TXOP_MIN_8814B << BIT_SHIFT_TXOP_MIN_8814B)
+#define BIT_CLEAR_TXOP_MIN_8814B(x) ((x) & (~BITS_TXOP_MIN_8814B))
+#define BIT_GET_TXOP_MIN_8814B(x)                                              \
+	(((x) >> BIT_SHIFT_TXOP_MIN_8814B) & BIT_MASK_TXOP_MIN_8814B)
+#define BIT_SET_TXOP_MIN_8814B(x, v)                                           \
+	(BIT_CLEAR_TXOP_MIN_8814B(x) | BIT_TXOP_MIN_8814B(v))
+
+/* 2 REG_PRE_BKF_TIME_8814B */
+
+#define BIT_SHIFT_PRE_BKF_TIME_8814B 0
+#define BIT_MASK_PRE_BKF_TIME_8814B 0xff
+#define BIT_PRE_BKF_TIME_8814B(x)                                              \
+	(((x) & BIT_MASK_PRE_BKF_TIME_8814B) << BIT_SHIFT_PRE_BKF_TIME_8814B)
+#define BITS_PRE_BKF_TIME_8814B                                                \
+	(BIT_MASK_PRE_BKF_TIME_8814B << BIT_SHIFT_PRE_BKF_TIME_8814B)
+#define BIT_CLEAR_PRE_BKF_TIME_8814B(x) ((x) & (~BITS_PRE_BKF_TIME_8814B))
+#define BIT_GET_PRE_BKF_TIME_8814B(x)                                          \
+	(((x) >> BIT_SHIFT_PRE_BKF_TIME_8814B) & BIT_MASK_PRE_BKF_TIME_8814B)
+#define BIT_SET_PRE_BKF_TIME_8814B(x, v)                                       \
+	(BIT_CLEAR_PRE_BKF_TIME_8814B(x) | BIT_PRE_BKF_TIME_8814B(v))
+
+/* 2 REG_CROSS_TXOP_CTRL_8814B */
+#define BIT_TBTT_RETRY_8814B BIT(4)
+#define BIT_TXFAIL_BREACK_TXOP_EN_8814B BIT(3)
+#define BIT_RTS_NAV_TXOP_8814B BIT(1)
+#define BIT_NOT_CROSS_TXOP_8814B BIT(0)
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_ACMHWCTRL_8814B */
+#define BIT_BEQ_ACM_STATUS_8814B BIT(7)
+#define BIT_VIQ_ACM_STATUS_8814B BIT(6)
+#define BIT_VOQ_ACM_STATUS_8814B BIT(5)
+#define BIT_BEQ_ACM_EN_8814B BIT(3)
+#define BIT_VIQ_ACM_EN_8814B BIT(2)
+#define BIT_VOQ_ACM_EN_8814B BIT(1)
+#define BIT_ACMHWEN_8814B BIT(0)
+
+/* 2 REG_ACMRSTCTRL_8814B */
+#define BIT_BE_ACM_RESET_USED_TIME_8814B BIT(2)
+#define BIT_VI_ACM_RESET_USED_TIME_8814B BIT(1)
+#define BIT_VO_ACM_RESET_USED_TIME_8814B BIT(0)
+
+/* 2 REG_ACMAVG_8814B */
+
+#define BIT_SHIFT_AVGPERIOD_8814B 0
+#define BIT_MASK_AVGPERIOD_8814B 0xffff
+#define BIT_AVGPERIOD_8814B(x)                                                 \
+	(((x) & BIT_MASK_AVGPERIOD_8814B) << BIT_SHIFT_AVGPERIOD_8814B)
+#define BITS_AVGPERIOD_8814B                                                   \
+	(BIT_MASK_AVGPERIOD_8814B << BIT_SHIFT_AVGPERIOD_8814B)
+#define BIT_CLEAR_AVGPERIOD_8814B(x) ((x) & (~BITS_AVGPERIOD_8814B))
+#define BIT_GET_AVGPERIOD_8814B(x)                                             \
+	(((x) >> BIT_SHIFT_AVGPERIOD_8814B) & BIT_MASK_AVGPERIOD_8814B)
+#define BIT_SET_AVGPERIOD_8814B(x, v)                                          \
+	(BIT_CLEAR_AVGPERIOD_8814B(x) | BIT_AVGPERIOD_8814B(v))
+
+/* 2 REG_VO_ADMTIME_8814B */
+
+#define BIT_SHIFT_VO_ADMITTED_TIME_8814B 0
+#define BIT_MASK_VO_ADMITTED_TIME_8814B 0xffff
+#define BIT_VO_ADMITTED_TIME_8814B(x)                                          \
+	(((x) & BIT_MASK_VO_ADMITTED_TIME_8814B)                               \
+	 << BIT_SHIFT_VO_ADMITTED_TIME_8814B)
+#define BITS_VO_ADMITTED_TIME_8814B                                            \
+	(BIT_MASK_VO_ADMITTED_TIME_8814B << BIT_SHIFT_VO_ADMITTED_TIME_8814B)
+#define BIT_CLEAR_VO_ADMITTED_TIME_8814B(x)                                    \
+	((x) & (~BITS_VO_ADMITTED_TIME_8814B))
+#define BIT_GET_VO_ADMITTED_TIME_8814B(x)                                      \
+	(((x) >> BIT_SHIFT_VO_ADMITTED_TIME_8814B) &                           \
+	 BIT_MASK_VO_ADMITTED_TIME_8814B)
+#define BIT_SET_VO_ADMITTED_TIME_8814B(x, v)                                   \
+	(BIT_CLEAR_VO_ADMITTED_TIME_8814B(x) | BIT_VO_ADMITTED_TIME_8814B(v))
+
+/* 2 REG_VI_ADMTIME_8814B */
+
+#define BIT_SHIFT_VI_ADMITTED_TIME_8814B 0
+#define BIT_MASK_VI_ADMITTED_TIME_8814B 0xffff
+#define BIT_VI_ADMITTED_TIME_8814B(x)                                          \
+	(((x) & BIT_MASK_VI_ADMITTED_TIME_8814B)                               \
+	 << BIT_SHIFT_VI_ADMITTED_TIME_8814B)
+#define BITS_VI_ADMITTED_TIME_8814B                                            \
+	(BIT_MASK_VI_ADMITTED_TIME_8814B << BIT_SHIFT_VI_ADMITTED_TIME_8814B)
+#define BIT_CLEAR_VI_ADMITTED_TIME_8814B(x)                                    \
+	((x) & (~BITS_VI_ADMITTED_TIME_8814B))
+#define BIT_GET_VI_ADMITTED_TIME_8814B(x)                                      \
+	(((x) >> BIT_SHIFT_VI_ADMITTED_TIME_8814B) &                           \
+	 BIT_MASK_VI_ADMITTED_TIME_8814B)
+#define BIT_SET_VI_ADMITTED_TIME_8814B(x, v)                                   \
+	(BIT_CLEAR_VI_ADMITTED_TIME_8814B(x) | BIT_VI_ADMITTED_TIME_8814B(v))
+
+/* 2 REG_BE_ADMTIME_8814B */
+
+#define BIT_SHIFT_BE_ADMITTED_TIME_8814B 0
+#define BIT_MASK_BE_ADMITTED_TIME_8814B 0xffff
+#define BIT_BE_ADMITTED_TIME_8814B(x)                                          \
+	(((x) & BIT_MASK_BE_ADMITTED_TIME_8814B)                               \
+	 << BIT_SHIFT_BE_ADMITTED_TIME_8814B)
+#define BITS_BE_ADMITTED_TIME_8814B                                            \
+	(BIT_MASK_BE_ADMITTED_TIME_8814B << BIT_SHIFT_BE_ADMITTED_TIME_8814B)
+#define BIT_CLEAR_BE_ADMITTED_TIME_8814B(x)                                    \
+	((x) & (~BITS_BE_ADMITTED_TIME_8814B))
+#define BIT_GET_BE_ADMITTED_TIME_8814B(x)                                      \
+	(((x) >> BIT_SHIFT_BE_ADMITTED_TIME_8814B) &                           \
+	 BIT_MASK_BE_ADMITTED_TIME_8814B)
+#define BIT_SET_BE_ADMITTED_TIME_8814B(x, v)                                   \
+	(BIT_CLEAR_BE_ADMITTED_TIME_8814B(x) | BIT_BE_ADMITTED_TIME_8814B(v))
+
+/* 2 REG_MAC_HEADER_NAV_OFFSET_8814B */
+
+#define BIT_SHIFT_MAC_HEADER_NAV_OFFSET_8814B 0
+#define BIT_MASK_MAC_HEADER_NAV_OFFSET_8814B 0xff
+#define BIT_MAC_HEADER_NAV_OFFSET_8814B(x)                                     \
+	(((x) & BIT_MASK_MAC_HEADER_NAV_OFFSET_8814B)                          \
+	 << BIT_SHIFT_MAC_HEADER_NAV_OFFSET_8814B)
+#define BITS_MAC_HEADER_NAV_OFFSET_8814B                                       \
+	(BIT_MASK_MAC_HEADER_NAV_OFFSET_8814B                                  \
+	 << BIT_SHIFT_MAC_HEADER_NAV_OFFSET_8814B)
+#define BIT_CLEAR_MAC_HEADER_NAV_OFFSET_8814B(x)                               \
+	((x) & (~BITS_MAC_HEADER_NAV_OFFSET_8814B))
+#define BIT_GET_MAC_HEADER_NAV_OFFSET_8814B(x)                                 \
+	(((x) >> BIT_SHIFT_MAC_HEADER_NAV_OFFSET_8814B) &                      \
+	 BIT_MASK_MAC_HEADER_NAV_OFFSET_8814B)
+#define BIT_SET_MAC_HEADER_NAV_OFFSET_8814B(x, v)                              \
+	(BIT_CLEAR_MAC_HEADER_NAV_OFFSET_8814B(x) |                            \
+	 BIT_MAC_HEADER_NAV_OFFSET_8814B(v))
+
+/* 2 REG_DIS_NDPA_NAV_CHECK_8814B */
+#define BIT_DIS_NDPA_NAV_CHECK_8814B BIT(0)
+
+/* 2 REG_EDCA_RANDOM_GEN_8814B */
+
+#define BIT_SHIFT_RANDOM_GEN_8814B 0
+#define BIT_MASK_RANDOM_GEN_8814B 0xffffff
+#define BIT_RANDOM_GEN_8814B(x)                                                \
+	(((x) & BIT_MASK_RANDOM_GEN_8814B) << BIT_SHIFT_RANDOM_GEN_8814B)
+#define BITS_RANDOM_GEN_8814B                                                  \
+	(BIT_MASK_RANDOM_GEN_8814B << BIT_SHIFT_RANDOM_GEN_8814B)
+#define BIT_CLEAR_RANDOM_GEN_8814B(x) ((x) & (~BITS_RANDOM_GEN_8814B))
+#define BIT_GET_RANDOM_GEN_8814B(x)                                            \
+	(((x) >> BIT_SHIFT_RANDOM_GEN_8814B) & BIT_MASK_RANDOM_GEN_8814B)
+#define BIT_SET_RANDOM_GEN_8814B(x, v)                                         \
+	(BIT_CLEAR_RANDOM_GEN_8814B(x) | BIT_RANDOM_GEN_8814B(v))
+
+/* 2 REG_TXCMD_SEL_8814B */
+
+#define BIT_SHIFT_TXCMD_SEG_SEL_8814B 0
+#define BIT_MASK_TXCMD_SEG_SEL_8814B 0xf
+#define BIT_TXCMD_SEG_SEL_8814B(x)                                             \
+	(((x) & BIT_MASK_TXCMD_SEG_SEL_8814B) << BIT_SHIFT_TXCMD_SEG_SEL_8814B)
+#define BITS_TXCMD_SEG_SEL_8814B                                               \
+	(BIT_MASK_TXCMD_SEG_SEL_8814B << BIT_SHIFT_TXCMD_SEG_SEL_8814B)
+#define BIT_CLEAR_TXCMD_SEG_SEL_8814B(x) ((x) & (~BITS_TXCMD_SEG_SEL_8814B))
+#define BIT_GET_TXCMD_SEG_SEL_8814B(x)                                         \
+	(((x) >> BIT_SHIFT_TXCMD_SEG_SEL_8814B) & BIT_MASK_TXCMD_SEG_SEL_8814B)
+#define BIT_SET_TXCMD_SEG_SEL_8814B(x, v)                                      \
+	(BIT_CLEAR_TXCMD_SEG_SEL_8814B(x) | BIT_TXCMD_SEG_SEL_8814B(v))
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_MU_DBG_INFO_8814B */
+
+#define BIT_SHIFT_MU_DBG_INFO_8814B 0
+#define BIT_MASK_MU_DBG_INFO_8814B 0xffffffffL
+#define BIT_MU_DBG_INFO_8814B(x)                                               \
+	(((x) & BIT_MASK_MU_DBG_INFO_8814B) << BIT_SHIFT_MU_DBG_INFO_8814B)
+#define BITS_MU_DBG_INFO_8814B                                                 \
+	(BIT_MASK_MU_DBG_INFO_8814B << BIT_SHIFT_MU_DBG_INFO_8814B)
+#define BIT_CLEAR_MU_DBG_INFO_8814B(x) ((x) & (~BITS_MU_DBG_INFO_8814B))
+#define BIT_GET_MU_DBG_INFO_8814B(x)                                           \
+	(((x) >> BIT_SHIFT_MU_DBG_INFO_8814B) & BIT_MASK_MU_DBG_INFO_8814B)
+#define BIT_SET_MU_DBG_INFO_8814B(x, v)                                        \
+	(BIT_CLEAR_MU_DBG_INFO_8814B(x) | BIT_MU_DBG_INFO_8814B(v))
+
+/* 2 REG_MU_DBG_INFO_1_8814B */
+
+#define BIT_SHIFT_MU_DBG_INFO_1_8814B 0
+#define BIT_MASK_MU_DBG_INFO_1_8814B 0xffffffffL
+#define BIT_MU_DBG_INFO_1_8814B(x)                                             \
+	(((x) & BIT_MASK_MU_DBG_INFO_1_8814B) << BIT_SHIFT_MU_DBG_INFO_1_8814B)
+#define BITS_MU_DBG_INFO_1_8814B                                               \
+	(BIT_MASK_MU_DBG_INFO_1_8814B << BIT_SHIFT_MU_DBG_INFO_1_8814B)
+#define BIT_CLEAR_MU_DBG_INFO_1_8814B(x) ((x) & (~BITS_MU_DBG_INFO_1_8814B))
+#define BIT_GET_MU_DBG_INFO_1_8814B(x)                                         \
+	(((x) >> BIT_SHIFT_MU_DBG_INFO_1_8814B) & BIT_MASK_MU_DBG_INFO_1_8814B)
+#define BIT_SET_MU_DBG_INFO_1_8814B(x, v)                                      \
+	(BIT_CLEAR_MU_DBG_INFO_1_8814B(x) | BIT_MU_DBG_INFO_1_8814B(v))
+
+/* 2 REG_SCH_DBG_SEL_8814B */
+
+#define BIT_SHIFT_SCH_DBG_SEL_8814B 0
+#define BIT_MASK_SCH_DBG_SEL_8814B 0xff
+#define BIT_SCH_DBG_SEL_8814B(x)                                               \
+	(((x) & BIT_MASK_SCH_DBG_SEL_8814B) << BIT_SHIFT_SCH_DBG_SEL_8814B)
+#define BITS_SCH_DBG_SEL_8814B                                                 \
+	(BIT_MASK_SCH_DBG_SEL_8814B << BIT_SHIFT_SCH_DBG_SEL_8814B)
+#define BIT_CLEAR_SCH_DBG_SEL_8814B(x) ((x) & (~BITS_SCH_DBG_SEL_8814B))
+#define BIT_GET_SCH_DBG_SEL_8814B(x)                                           \
+	(((x) >> BIT_SHIFT_SCH_DBG_SEL_8814B) & BIT_MASK_SCH_DBG_SEL_8814B)
+#define BIT_SET_SCH_DBG_SEL_8814B(x, v)                                        \
+	(BIT_CLEAR_SCH_DBG_SEL_8814B(x) | BIT_SCH_DBG_SEL_8814B(v))
+
+/* 2 REG_SCHEDULER_RST_8814B */
+#define BIT_SCHEDULER_RST_V1_8814B BIT(0)
+
+/* 2 REG_MU_DBG_ERR_FLAG_8814B */
+#define BIT_BCN_PORTID_ERR_8814B BIT(2)
+
+#define BIT_SHIFT_MU_DBG_ERR_FLAG_8814B 0
+#define BIT_MASK_MU_DBG_ERR_FLAG_8814B 0x3
+#define BIT_MU_DBG_ERR_FLAG_8814B(x)                                           \
+	(((x) & BIT_MASK_MU_DBG_ERR_FLAG_8814B)                                \
+	 << BIT_SHIFT_MU_DBG_ERR_FLAG_8814B)
+#define BITS_MU_DBG_ERR_FLAG_8814B                                             \
+	(BIT_MASK_MU_DBG_ERR_FLAG_8814B << BIT_SHIFT_MU_DBG_ERR_FLAG_8814B)
+#define BIT_CLEAR_MU_DBG_ERR_FLAG_8814B(x) ((x) & (~BITS_MU_DBG_ERR_FLAG_8814B))
+#define BIT_GET_MU_DBG_ERR_FLAG_8814B(x)                                       \
+	(((x) >> BIT_SHIFT_MU_DBG_ERR_FLAG_8814B) &                            \
+	 BIT_MASK_MU_DBG_ERR_FLAG_8814B)
+#define BIT_SET_MU_DBG_ERR_FLAG_8814B(x, v)                                    \
+	(BIT_CLEAR_MU_DBG_ERR_FLAG_8814B(x) | BIT_MU_DBG_ERR_FLAG_8814B(v))
+
+/* 2 REG_TX_ERR_RECOVERY_RST_8814B */
+
+#define BIT_SHIFT_ERR_RECOVER_CNT_8814B 4
+#define BIT_MASK_ERR_RECOVER_CNT_8814B 0xf
+#define BIT_ERR_RECOVER_CNT_8814B(x)                                           \
+	(((x) & BIT_MASK_ERR_RECOVER_CNT_8814B)                                \
+	 << BIT_SHIFT_ERR_RECOVER_CNT_8814B)
+#define BITS_ERR_RECOVER_CNT_8814B                                             \
+	(BIT_MASK_ERR_RECOVER_CNT_8814B << BIT_SHIFT_ERR_RECOVER_CNT_8814B)
+#define BIT_CLEAR_ERR_RECOVER_CNT_8814B(x) ((x) & (~BITS_ERR_RECOVER_CNT_8814B))
+#define BIT_GET_ERR_RECOVER_CNT_8814B(x)                                       \
+	(((x) >> BIT_SHIFT_ERR_RECOVER_CNT_8814B) &                            \
+	 BIT_MASK_ERR_RECOVER_CNT_8814B)
+#define BIT_SET_ERR_RECOVER_CNT_8814B(x, v)                                    \
+	(BIT_CLEAR_ERR_RECOVER_CNT_8814B(x) | BIT_ERR_RECOVER_CNT_8814B(v))
+
+#define BIT_RX_HANG_ERR_8814B BIT(2)
+#define BIT_TX_HANG_ERR_8814B BIT(1)
+#define BIT_TX_ERR_RECOVERY_RST_8814B BIT(0)
+
+/* 2 REG_SCH_DBG_VALUE_8814B */
+
+#define BIT_SHIFT_SCH_DBG_VALUE_8814B 0
+#define BIT_MASK_SCH_DBG_VALUE_8814B 0xffffffffL
+#define BIT_SCH_DBG_VALUE_8814B(x)                                             \
+	(((x) & BIT_MASK_SCH_DBG_VALUE_8814B) << BIT_SHIFT_SCH_DBG_VALUE_8814B)
+#define BITS_SCH_DBG_VALUE_8814B                                               \
+	(BIT_MASK_SCH_DBG_VALUE_8814B << BIT_SHIFT_SCH_DBG_VALUE_8814B)
+#define BIT_CLEAR_SCH_DBG_VALUE_8814B(x) ((x) & (~BITS_SCH_DBG_VALUE_8814B))
+#define BIT_GET_SCH_DBG_VALUE_8814B(x)                                         \
+	(((x) >> BIT_SHIFT_SCH_DBG_VALUE_8814B) & BIT_MASK_SCH_DBG_VALUE_8814B)
+#define BIT_SET_SCH_DBG_VALUE_8814B(x, v)                                      \
+	(BIT_CLEAR_SCH_DBG_VALUE_8814B(x) | BIT_SCH_DBG_VALUE_8814B(v))
+
+/* 2 REG_SCH_TXCMD_8814B */
+
+#define BIT_SHIFT_SCH_TXCMD_8814B 0
+#define BIT_MASK_SCH_TXCMD_8814B 0xffffffffL
+#define BIT_SCH_TXCMD_8814B(x)                                                 \
+	(((x) & BIT_MASK_SCH_TXCMD_8814B) << BIT_SHIFT_SCH_TXCMD_8814B)
+#define BITS_SCH_TXCMD_8814B                                                   \
+	(BIT_MASK_SCH_TXCMD_8814B << BIT_SHIFT_SCH_TXCMD_8814B)
+#define BIT_CLEAR_SCH_TXCMD_8814B(x) ((x) & (~BITS_SCH_TXCMD_8814B))
+#define BIT_GET_SCH_TXCMD_8814B(x)                                             \
+	(((x) >> BIT_SHIFT_SCH_TXCMD_8814B) & BIT_MASK_SCH_TXCMD_8814B)
+#define BIT_SET_SCH_TXCMD_8814B(x, v)                                          \
+	(BIT_CLEAR_SCH_TXCMD_8814B(x) | BIT_SCH_TXCMD_8814B(v))
+
+/* 2 REG_PAGE5_DUMMY_8814B */
+
+/* 2 REG_PORT_CTRL_SEL_8814B */
+
+#define BIT_SHIFT_BCN_TIMER_SEL_FWRD_V1_8814B 4
+#define BIT_MASK_BCN_TIMER_SEL_FWRD_V1_8814B 0x7
+#define BIT_BCN_TIMER_SEL_FWRD_V1_8814B(x)                                     \
+	(((x) & BIT_MASK_BCN_TIMER_SEL_FWRD_V1_8814B)                          \
+	 << BIT_SHIFT_BCN_TIMER_SEL_FWRD_V1_8814B)
+#define BITS_BCN_TIMER_SEL_FWRD_V1_8814B                                       \
+	(BIT_MASK_BCN_TIMER_SEL_FWRD_V1_8814B                                  \
+	 << BIT_SHIFT_BCN_TIMER_SEL_FWRD_V1_8814B)
+#define BIT_CLEAR_BCN_TIMER_SEL_FWRD_V1_8814B(x)                               \
+	((x) & (~BITS_BCN_TIMER_SEL_FWRD_V1_8814B))
+#define BIT_GET_BCN_TIMER_SEL_FWRD_V1_8814B(x)                                 \
+	(((x) >> BIT_SHIFT_BCN_TIMER_SEL_FWRD_V1_8814B) &                      \
+	 BIT_MASK_BCN_TIMER_SEL_FWRD_V1_8814B)
+#define BIT_SET_BCN_TIMER_SEL_FWRD_V1_8814B(x, v)                              \
+	(BIT_CLEAR_BCN_TIMER_SEL_FWRD_V1_8814B(x) |                            \
+	 BIT_BCN_TIMER_SEL_FWRD_V1_8814B(v))
+
+#define BIT_SHIFT_PORT_CTRL_SEL_8814B 0
+#define BIT_MASK_PORT_CTRL_SEL_8814B 0x7
+#define BIT_PORT_CTRL_SEL_8814B(x)                                             \
+	(((x) & BIT_MASK_PORT_CTRL_SEL_8814B) << BIT_SHIFT_PORT_CTRL_SEL_8814B)
+#define BITS_PORT_CTRL_SEL_8814B                                               \
+	(BIT_MASK_PORT_CTRL_SEL_8814B << BIT_SHIFT_PORT_CTRL_SEL_8814B)
+#define BIT_CLEAR_PORT_CTRL_SEL_8814B(x) ((x) & (~BITS_PORT_CTRL_SEL_8814B))
+#define BIT_GET_PORT_CTRL_SEL_8814B(x)                                         \
+	(((x) >> BIT_SHIFT_PORT_CTRL_SEL_8814B) & BIT_MASK_PORT_CTRL_SEL_8814B)
+#define BIT_SET_PORT_CTRL_SEL_8814B(x, v)                                      \
+	(BIT_CLEAR_PORT_CTRL_SEL_8814B(x) | BIT_PORT_CTRL_SEL_8814B(v))
+
+/* 2 REG_PORT_CTRL_CFG_8814B */
+#define BIT_BCNERR_CNT_EN_V1_8814B BIT(11)
+#define BIT_DIS_TRX_CAL_BCN_V1_8814B BIT(10)
+#define BIT_DIS_TX_CAL_TBTT_V1_8814B BIT(9)
+#define BIT_BCN_AGGRESSION_V1_8814B BIT(8)
+#define BIT_TSFTR_RST_V1_8814B BIT(7)
+#define BIT_DIS_RX_BSSID_FIT_8814B BIT(6)
+#define BIT_EN_TXBCN_RPT_V1_8814B BIT(5)
+#define BIT_DIS_TSF_UDT_8814B BIT(4)
+#define BIT_EN_PORT_FUNCTION_8814B BIT(3)
+#define BIT_EN_RXBCN_RPT_8814B BIT(2)
+#define BIT_EN_P2P_CTWINDOW_8814B BIT(1)
+#define BIT_EN_P2P_BCNQ_AREA_8814B BIT(0)
+
+/* 2 REG_TBTT_PROHIBIT_CFG_8814B */
+#define BIT_MASK_PROHIBIT_8814B BIT(23)
+
+#define BIT_SHIFT_TBTT_HOLD_TIME_8814B 8
+#define BIT_MASK_TBTT_HOLD_TIME_8814B 0xfff
+#define BIT_TBTT_HOLD_TIME_8814B(x)                                            \
+	(((x) & BIT_MASK_TBTT_HOLD_TIME_8814B)                                 \
+	 << BIT_SHIFT_TBTT_HOLD_TIME_8814B)
+#define BITS_TBTT_HOLD_TIME_8814B                                              \
+	(BIT_MASK_TBTT_HOLD_TIME_8814B << BIT_SHIFT_TBTT_HOLD_TIME_8814B)
+#define BIT_CLEAR_TBTT_HOLD_TIME_8814B(x) ((x) & (~BITS_TBTT_HOLD_TIME_8814B))
+#define BIT_GET_TBTT_HOLD_TIME_8814B(x)                                        \
+	(((x) >> BIT_SHIFT_TBTT_HOLD_TIME_8814B) &                             \
+	 BIT_MASK_TBTT_HOLD_TIME_8814B)
+#define BIT_SET_TBTT_HOLD_TIME_8814B(x, v)                                     \
+	(BIT_CLEAR_TBTT_HOLD_TIME_8814B(x) | BIT_TBTT_HOLD_TIME_8814B(v))
+
+#define BIT_SHIFT_TBTT_PROHIBIT_SETUP_8814B 0
+#define BIT_MASK_TBTT_PROHIBIT_SETUP_8814B 0xf
+#define BIT_TBTT_PROHIBIT_SETUP_8814B(x)                                       \
+	(((x) & BIT_MASK_TBTT_PROHIBIT_SETUP_8814B)                            \
+	 << BIT_SHIFT_TBTT_PROHIBIT_SETUP_8814B)
+#define BITS_TBTT_PROHIBIT_SETUP_8814B                                         \
+	(BIT_MASK_TBTT_PROHIBIT_SETUP_8814B                                    \
+	 << BIT_SHIFT_TBTT_PROHIBIT_SETUP_8814B)
+#define BIT_CLEAR_TBTT_PROHIBIT_SETUP_8814B(x)                                 \
+	((x) & (~BITS_TBTT_PROHIBIT_SETUP_8814B))
+#define BIT_GET_TBTT_PROHIBIT_SETUP_8814B(x)                                   \
+	(((x) >> BIT_SHIFT_TBTT_PROHIBIT_SETUP_8814B) &                        \
+	 BIT_MASK_TBTT_PROHIBIT_SETUP_8814B)
+#define BIT_SET_TBTT_PROHIBIT_SETUP_8814B(x, v)                                \
+	(BIT_CLEAR_TBTT_PROHIBIT_SETUP_8814B(x) |                              \
+	 BIT_TBTT_PROHIBIT_SETUP_8814B(v))
+
+/* 2 REG_DRVERLYINT_CFG_8814B */
+
+#define BIT_SHIFT_DRVERLYITV_8814B 0
+#define BIT_MASK_DRVERLYITV_8814B 0xff
+#define BIT_DRVERLYITV_8814B(x)                                                \
+	(((x) & BIT_MASK_DRVERLYITV_8814B) << BIT_SHIFT_DRVERLYITV_8814B)
+#define BITS_DRVERLYITV_8814B                                                  \
+	(BIT_MASK_DRVERLYITV_8814B << BIT_SHIFT_DRVERLYITV_8814B)
+#define BIT_CLEAR_DRVERLYITV_8814B(x) ((x) & (~BITS_DRVERLYITV_8814B))
+#define BIT_GET_DRVERLYITV_8814B(x)                                            \
+	(((x) >> BIT_SHIFT_DRVERLYITV_8814B) & BIT_MASK_DRVERLYITV_8814B)
+#define BIT_SET_DRVERLYITV_8814B(x, v)                                         \
+	(BIT_CLEAR_DRVERLYITV_8814B(x) | BIT_DRVERLYITV_8814B(v))
+
+/* 2 REG_BCNDMATIM_CFG_8814B */
+
+#define BIT_SHIFT_BCNDMATIM_8814B 0
+#define BIT_MASK_BCNDMATIM_8814B 0xff
+#define BIT_BCNDMATIM_8814B(x)                                                 \
+	(((x) & BIT_MASK_BCNDMATIM_8814B) << BIT_SHIFT_BCNDMATIM_8814B)
+#define BITS_BCNDMATIM_8814B                                                   \
+	(BIT_MASK_BCNDMATIM_8814B << BIT_SHIFT_BCNDMATIM_8814B)
+#define BIT_CLEAR_BCNDMATIM_8814B(x) ((x) & (~BITS_BCNDMATIM_8814B))
+#define BIT_GET_BCNDMATIM_8814B(x)                                             \
+	(((x) >> BIT_SHIFT_BCNDMATIM_8814B) & BIT_MASK_BCNDMATIM_8814B)
+#define BIT_SET_BCNDMATIM_8814B(x, v)                                          \
+	(BIT_CLEAR_BCNDMATIM_8814B(x) | BIT_BCNDMATIM_8814B(v))
+
+/* 2 REG_CTWND_CFG_8814B */
+
+#define BIT_SHIFT_CTWND_8814B 0
+#define BIT_MASK_CTWND_8814B 0xff
+#define BIT_CTWND_8814B(x)                                                     \
+	(((x) & BIT_MASK_CTWND_8814B) << BIT_SHIFT_CTWND_8814B)
+#define BITS_CTWND_8814B (BIT_MASK_CTWND_8814B << BIT_SHIFT_CTWND_8814B)
+#define BIT_CLEAR_CTWND_8814B(x) ((x) & (~BITS_CTWND_8814B))
+#define BIT_GET_CTWND_8814B(x)                                                 \
+	(((x) >> BIT_SHIFT_CTWND_8814B) & BIT_MASK_CTWND_8814B)
+#define BIT_SET_CTWND_8814B(x, v)                                              \
+	(BIT_CLEAR_CTWND_8814B(x) | BIT_CTWND_8814B(v))
+
+/* 2 REG_BCNIVLCUNT_CFG_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+#define BIT_SHIFT_BCNIVLCUNT_8814B 0
+#define BIT_MASK_BCNIVLCUNT_8814B 0x7f
+#define BIT_BCNIVLCUNT_8814B(x)                                                \
+	(((x) & BIT_MASK_BCNIVLCUNT_8814B) << BIT_SHIFT_BCNIVLCUNT_8814B)
+#define BITS_BCNIVLCUNT_8814B                                                  \
+	(BIT_MASK_BCNIVLCUNT_8814B << BIT_SHIFT_BCNIVLCUNT_8814B)
+#define BIT_CLEAR_BCNIVLCUNT_8814B(x) ((x) & (~BITS_BCNIVLCUNT_8814B))
+#define BIT_GET_BCNIVLCUNT_8814B(x)                                            \
+	(((x) >> BIT_SHIFT_BCNIVLCUNT_8814B) & BIT_MASK_BCNIVLCUNT_8814B)
+#define BIT_SET_BCNIVLCUNT_8814B(x, v)                                         \
+	(BIT_CLEAR_BCNIVLCUNT_8814B(x) | BIT_BCNIVLCUNT_8814B(v))
+
+/* 2 REG_EARLY_128US_CFG_8814B */
+
+#define BIT_SHIFT_EARLY_128US_8814B 0
+#define BIT_MASK_EARLY_128US_8814B 0x7
+#define BIT_EARLY_128US_8814B(x)                                               \
+	(((x) & BIT_MASK_EARLY_128US_8814B) << BIT_SHIFT_EARLY_128US_8814B)
+#define BITS_EARLY_128US_8814B                                                 \
+	(BIT_MASK_EARLY_128US_8814B << BIT_SHIFT_EARLY_128US_8814B)
+#define BIT_CLEAR_EARLY_128US_8814B(x) ((x) & (~BITS_EARLY_128US_8814B))
+#define BIT_GET_EARLY_128US_8814B(x)                                           \
+	(((x) >> BIT_SHIFT_EARLY_128US_8814B) & BIT_MASK_EARLY_128US_8814B)
+#define BIT_SET_EARLY_128US_8814B(x, v)                                        \
+	(BIT_CLEAR_EARLY_128US_8814B(x) | BIT_EARLY_128US_8814B(v))
+
+/* 2 REG_TSFTR_SYNC_OFFSET_CFG_8814B */
+
+#define BIT_SHIFT_TSFTR_SNC_OFFSET_V1_8814B 0
+#define BIT_MASK_TSFTR_SNC_OFFSET_V1_8814B 0xffffff
+#define BIT_TSFTR_SNC_OFFSET_V1_8814B(x)                                       \
+	(((x) & BIT_MASK_TSFTR_SNC_OFFSET_V1_8814B)                            \
+	 << BIT_SHIFT_TSFTR_SNC_OFFSET_V1_8814B)
+#define BITS_TSFTR_SNC_OFFSET_V1_8814B                                         \
+	(BIT_MASK_TSFTR_SNC_OFFSET_V1_8814B                                    \
+	 << BIT_SHIFT_TSFTR_SNC_OFFSET_V1_8814B)
+#define BIT_CLEAR_TSFTR_SNC_OFFSET_V1_8814B(x)                                 \
+	((x) & (~BITS_TSFTR_SNC_OFFSET_V1_8814B))
+#define BIT_GET_TSFTR_SNC_OFFSET_V1_8814B(x)                                   \
+	(((x) >> BIT_SHIFT_TSFTR_SNC_OFFSET_V1_8814B) &                        \
+	 BIT_MASK_TSFTR_SNC_OFFSET_V1_8814B)
+#define BIT_SET_TSFTR_SNC_OFFSET_V1_8814B(x, v)                                \
+	(BIT_CLEAR_TSFTR_SNC_OFFSET_V1_8814B(x) |                              \
+	 BIT_TSFTR_SNC_OFFSET_V1_8814B(v))
+
+/* 2 REG_TSFTR_SYNC_CTRL_CFG_8814B */
+#define BIT_SYNC_TSF_NOW_V1_8814B BIT(5)
+#define BIT_SYNC_TSF_ONCE_8814B BIT(4)
+#define BIT_SYNC_TSF_AUTO_8814B BIT(3)
+
+#define BIT_SHIFT_SYNC_PORT_SEL_8814B 0
+#define BIT_MASK_SYNC_PORT_SEL_8814B 0x7
+#define BIT_SYNC_PORT_SEL_8814B(x)                                             \
+	(((x) & BIT_MASK_SYNC_PORT_SEL_8814B) << BIT_SHIFT_SYNC_PORT_SEL_8814B)
+#define BITS_SYNC_PORT_SEL_8814B                                               \
+	(BIT_MASK_SYNC_PORT_SEL_8814B << BIT_SHIFT_SYNC_PORT_SEL_8814B)
+#define BIT_CLEAR_SYNC_PORT_SEL_8814B(x) ((x) & (~BITS_SYNC_PORT_SEL_8814B))
+#define BIT_GET_SYNC_PORT_SEL_8814B(x)                                         \
+	(((x) >> BIT_SHIFT_SYNC_PORT_SEL_8814B) & BIT_MASK_SYNC_PORT_SEL_8814B)
+#define BIT_SET_SYNC_PORT_SEL_8814B(x, v)                                      \
+	(BIT_CLEAR_SYNC_PORT_SEL_8814B(x) | BIT_SYNC_PORT_SEL_8814B(v))
+
+/* 2 REG_BCN_SPACE_CFG_8814B */
+
+#define BIT_SHIFT_BCN_SPACE_8814B 0
+#define BIT_MASK_BCN_SPACE_8814B 0xffff
+#define BIT_BCN_SPACE_8814B(x)                                                 \
+	(((x) & BIT_MASK_BCN_SPACE_8814B) << BIT_SHIFT_BCN_SPACE_8814B)
+#define BITS_BCN_SPACE_8814B                                                   \
+	(BIT_MASK_BCN_SPACE_8814B << BIT_SHIFT_BCN_SPACE_8814B)
+#define BIT_CLEAR_BCN_SPACE_8814B(x) ((x) & (~BITS_BCN_SPACE_8814B))
+#define BIT_GET_BCN_SPACE_8814B(x)                                             \
+	(((x) >> BIT_SHIFT_BCN_SPACE_8814B) & BIT_MASK_BCN_SPACE_8814B)
+#define BIT_SET_BCN_SPACE_8814B(x, v)                                          \
+	(BIT_CLEAR_BCN_SPACE_8814B(x) | BIT_BCN_SPACE_8814B(v))
+
+/* 2 REG_EARLY_INT_ADJUST_CFG_8814B */
+
+#define BIT_SHIFT_EARLY_INT_ADJUST_8814B 0
+#define BIT_MASK_EARLY_INT_ADJUST_8814B 0xffff
+#define BIT_EARLY_INT_ADJUST_8814B(x)                                          \
+	(((x) & BIT_MASK_EARLY_INT_ADJUST_8814B)                               \
+	 << BIT_SHIFT_EARLY_INT_ADJUST_8814B)
+#define BITS_EARLY_INT_ADJUST_8814B                                            \
+	(BIT_MASK_EARLY_INT_ADJUST_8814B << BIT_SHIFT_EARLY_INT_ADJUST_8814B)
+#define BIT_CLEAR_EARLY_INT_ADJUST_8814B(x)                                    \
+	((x) & (~BITS_EARLY_INT_ADJUST_8814B))
+#define BIT_GET_EARLY_INT_ADJUST_8814B(x)                                      \
+	(((x) >> BIT_SHIFT_EARLY_INT_ADJUST_8814B) &                           \
+	 BIT_MASK_EARLY_INT_ADJUST_8814B)
+#define BIT_SET_EARLY_INT_ADJUST_8814B(x, v)                                   \
+	(BIT_CLEAR_EARLY_INT_ADJUST_8814B(x) | BIT_EARLY_INT_ADJUST_8814B(v))
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_SW_TBTT_TSF_INFO_8814B */
+
+#define BIT_SHIFT_SW_TBTT_TSF_INFO_8814B 0
+#define BIT_MASK_SW_TBTT_TSF_INFO_8814B 0xffffffffL
+#define BIT_SW_TBTT_TSF_INFO_8814B(x)                                          \
+	(((x) & BIT_MASK_SW_TBTT_TSF_INFO_8814B)                               \
+	 << BIT_SHIFT_SW_TBTT_TSF_INFO_8814B)
+#define BITS_SW_TBTT_TSF_INFO_8814B                                            \
+	(BIT_MASK_SW_TBTT_TSF_INFO_8814B << BIT_SHIFT_SW_TBTT_TSF_INFO_8814B)
+#define BIT_CLEAR_SW_TBTT_TSF_INFO_8814B(x)                                    \
+	((x) & (~BITS_SW_TBTT_TSF_INFO_8814B))
+#define BIT_GET_SW_TBTT_TSF_INFO_8814B(x)                                      \
+	(((x) >> BIT_SHIFT_SW_TBTT_TSF_INFO_8814B) &                           \
+	 BIT_MASK_SW_TBTT_TSF_INFO_8814B)
+#define BIT_SET_SW_TBTT_TSF_INFO_8814B(x, v)                                   \
+	(BIT_CLEAR_SW_TBTT_TSF_INFO_8814B(x) | BIT_SW_TBTT_TSF_INFO_8814B(v))
+
+/* 2 REG_TSFTR_LOW_8814B */
+
+#define BIT_SHIFT_TSF_TIMER_LOW_8814B 0
+#define BIT_MASK_TSF_TIMER_LOW_8814B 0xffffffffL
+#define BIT_TSF_TIMER_LOW_8814B(x)                                             \
+	(((x) & BIT_MASK_TSF_TIMER_LOW_8814B) << BIT_SHIFT_TSF_TIMER_LOW_8814B)
+#define BITS_TSF_TIMER_LOW_8814B                                               \
+	(BIT_MASK_TSF_TIMER_LOW_8814B << BIT_SHIFT_TSF_TIMER_LOW_8814B)
+#define BIT_CLEAR_TSF_TIMER_LOW_8814B(x) ((x) & (~BITS_TSF_TIMER_LOW_8814B))
+#define BIT_GET_TSF_TIMER_LOW_8814B(x)                                         \
+	(((x) >> BIT_SHIFT_TSF_TIMER_LOW_8814B) & BIT_MASK_TSF_TIMER_LOW_8814B)
+#define BIT_SET_TSF_TIMER_LOW_8814B(x, v)                                      \
+	(BIT_CLEAR_TSF_TIMER_LOW_8814B(x) | BIT_TSF_TIMER_LOW_8814B(v))
+
+/* 2 REG_TSFTR_HIGH_8814B */
+
+#define BIT_SHIFT_TSF_TIMER_HIGH_8814B 0
+#define BIT_MASK_TSF_TIMER_HIGH_8814B 0xffffffffL
+#define BIT_TSF_TIMER_HIGH_8814B(x)                                            \
+	(((x) & BIT_MASK_TSF_TIMER_HIGH_8814B)                                 \
+	 << BIT_SHIFT_TSF_TIMER_HIGH_8814B)
+#define BITS_TSF_TIMER_HIGH_8814B                                              \
+	(BIT_MASK_TSF_TIMER_HIGH_8814B << BIT_SHIFT_TSF_TIMER_HIGH_8814B)
+#define BIT_CLEAR_TSF_TIMER_HIGH_8814B(x) ((x) & (~BITS_TSF_TIMER_HIGH_8814B))
+#define BIT_GET_TSF_TIMER_HIGH_8814B(x)                                        \
+	(((x) >> BIT_SHIFT_TSF_TIMER_HIGH_8814B) &                             \
+	 BIT_MASK_TSF_TIMER_HIGH_8814B)
+#define BIT_SET_TSF_TIMER_HIGH_8814B(x, v)                                     \
+	(BIT_CLEAR_TSF_TIMER_HIGH_8814B(x) | BIT_TSF_TIMER_HIGH_8814B(v))
+
+/* 2 REG_BCN_ERR_CNT_MAC_8814B */
+
+#define BIT_SHIFT_BCN_ERR_CNT_MAC_8814B 0
+#define BIT_MASK_BCN_ERR_CNT_MAC_8814B 0xff
+#define BIT_BCN_ERR_CNT_MAC_8814B(x)                                           \
+	(((x) & BIT_MASK_BCN_ERR_CNT_MAC_8814B)                                \
+	 << BIT_SHIFT_BCN_ERR_CNT_MAC_8814B)
+#define BITS_BCN_ERR_CNT_MAC_8814B                                             \
+	(BIT_MASK_BCN_ERR_CNT_MAC_8814B << BIT_SHIFT_BCN_ERR_CNT_MAC_8814B)
+#define BIT_CLEAR_BCN_ERR_CNT_MAC_8814B(x) ((x) & (~BITS_BCN_ERR_CNT_MAC_8814B))
+#define BIT_GET_BCN_ERR_CNT_MAC_8814B(x)                                       \
+	(((x) >> BIT_SHIFT_BCN_ERR_CNT_MAC_8814B) &                            \
+	 BIT_MASK_BCN_ERR_CNT_MAC_8814B)
+#define BIT_SET_BCN_ERR_CNT_MAC_8814B(x, v)                                    \
+	(BIT_CLEAR_BCN_ERR_CNT_MAC_8814B(x) | BIT_BCN_ERR_CNT_MAC_8814B(v))
+
+/* 2 REG_BCN_ERR_CNT_EDCCA_8814B */
+
+#define BIT_SHIFT_BCN_ERR_CNT_EDCCA_8814B 0
+#define BIT_MASK_BCN_ERR_CNT_EDCCA_8814B 0xff
+#define BIT_BCN_ERR_CNT_EDCCA_8814B(x)                                         \
+	(((x) & BIT_MASK_BCN_ERR_CNT_EDCCA_8814B)                              \
+	 << BIT_SHIFT_BCN_ERR_CNT_EDCCA_8814B)
+#define BITS_BCN_ERR_CNT_EDCCA_8814B                                           \
+	(BIT_MASK_BCN_ERR_CNT_EDCCA_8814B << BIT_SHIFT_BCN_ERR_CNT_EDCCA_8814B)
+#define BIT_CLEAR_BCN_ERR_CNT_EDCCA_8814B(x)                                   \
+	((x) & (~BITS_BCN_ERR_CNT_EDCCA_8814B))
+#define BIT_GET_BCN_ERR_CNT_EDCCA_8814B(x)                                     \
+	(((x) >> BIT_SHIFT_BCN_ERR_CNT_EDCCA_8814B) &                          \
+	 BIT_MASK_BCN_ERR_CNT_EDCCA_8814B)
+#define BIT_SET_BCN_ERR_CNT_EDCCA_8814B(x, v)                                  \
+	(BIT_CLEAR_BCN_ERR_CNT_EDCCA_8814B(x) | BIT_BCN_ERR_CNT_EDCCA_8814B(v))
+
+/* 2 REG_BCN_ERR_CNT_CCA_8814B */
+
+#define BIT_SHIFT_BCN_ERR_CNT_CCA_8814B 0
+#define BIT_MASK_BCN_ERR_CNT_CCA_8814B 0xff
+#define BIT_BCN_ERR_CNT_CCA_8814B(x)                                           \
+	(((x) & BIT_MASK_BCN_ERR_CNT_CCA_8814B)                                \
+	 << BIT_SHIFT_BCN_ERR_CNT_CCA_8814B)
+#define BITS_BCN_ERR_CNT_CCA_8814B                                             \
+	(BIT_MASK_BCN_ERR_CNT_CCA_8814B << BIT_SHIFT_BCN_ERR_CNT_CCA_8814B)
+#define BIT_CLEAR_BCN_ERR_CNT_CCA_8814B(x) ((x) & (~BITS_BCN_ERR_CNT_CCA_8814B))
+#define BIT_GET_BCN_ERR_CNT_CCA_8814B(x)                                       \
+	(((x) >> BIT_SHIFT_BCN_ERR_CNT_CCA_8814B) &                            \
+	 BIT_MASK_BCN_ERR_CNT_CCA_8814B)
+#define BIT_SET_BCN_ERR_CNT_CCA_8814B(x, v)                                    \
+	(BIT_CLEAR_BCN_ERR_CNT_CCA_8814B(x) | BIT_BCN_ERR_CNT_CCA_8814B(v))
+
+/* 2 REG_BCN_ERR_CNT_INVALID_8814B */
+
+#define BIT_SHIFT_BCN_ERR_CNT_INVALID_8814B 0
+#define BIT_MASK_BCN_ERR_CNT_INVALID_8814B 0xff
+#define BIT_BCN_ERR_CNT_INVALID_8814B(x)                                       \
+	(((x) & BIT_MASK_BCN_ERR_CNT_INVALID_8814B)                            \
+	 << BIT_SHIFT_BCN_ERR_CNT_INVALID_8814B)
+#define BITS_BCN_ERR_CNT_INVALID_8814B                                         \
+	(BIT_MASK_BCN_ERR_CNT_INVALID_8814B                                    \
+	 << BIT_SHIFT_BCN_ERR_CNT_INVALID_8814B)
+#define BIT_CLEAR_BCN_ERR_CNT_INVALID_8814B(x)                                 \
+	((x) & (~BITS_BCN_ERR_CNT_INVALID_8814B))
+#define BIT_GET_BCN_ERR_CNT_INVALID_8814B(x)                                   \
+	(((x) >> BIT_SHIFT_BCN_ERR_CNT_INVALID_8814B) &                        \
+	 BIT_MASK_BCN_ERR_CNT_INVALID_8814B)
+#define BIT_SET_BCN_ERR_CNT_INVALID_8814B(x, v)                                \
+	(BIT_CLEAR_BCN_ERR_CNT_INVALID_8814B(x) |                              \
+	 BIT_BCN_ERR_CNT_INVALID_8814B(v))
+
+/* 2 REG_BCN_ERR_CNT_OTHERS_8814B */
+
+#define BIT_SHIFT_BCN_ERR_CNT_OTHERS_8814B 0
+#define BIT_MASK_BCN_ERR_CNT_OTHERS_8814B 0xff
+#define BIT_BCN_ERR_CNT_OTHERS_8814B(x)                                        \
+	(((x) & BIT_MASK_BCN_ERR_CNT_OTHERS_8814B)                             \
+	 << BIT_SHIFT_BCN_ERR_CNT_OTHERS_8814B)
+#define BITS_BCN_ERR_CNT_OTHERS_8814B                                          \
+	(BIT_MASK_BCN_ERR_CNT_OTHERS_8814B                                     \
+	 << BIT_SHIFT_BCN_ERR_CNT_OTHERS_8814B)
+#define BIT_CLEAR_BCN_ERR_CNT_OTHERS_8814B(x)                                  \
+	((x) & (~BITS_BCN_ERR_CNT_OTHERS_8814B))
+#define BIT_GET_BCN_ERR_CNT_OTHERS_8814B(x)                                    \
+	(((x) >> BIT_SHIFT_BCN_ERR_CNT_OTHERS_8814B) &                         \
+	 BIT_MASK_BCN_ERR_CNT_OTHERS_8814B)
+#define BIT_SET_BCN_ERR_CNT_OTHERS_8814B(x, v)                                 \
+	(BIT_CLEAR_BCN_ERR_CNT_OTHERS_8814B(x) |                               \
+	 BIT_BCN_ERR_CNT_OTHERS_8814B(v))
+
+/* 2 REG_RX_BCN_TIMER_8814B */
+
+#define BIT_SHIFT_RX_BCN_TIMER_8814B 0
+#define BIT_MASK_RX_BCN_TIMER_8814B 0xffff
+#define BIT_RX_BCN_TIMER_8814B(x)                                              \
+	(((x) & BIT_MASK_RX_BCN_TIMER_8814B) << BIT_SHIFT_RX_BCN_TIMER_8814B)
+#define BITS_RX_BCN_TIMER_8814B                                                \
+	(BIT_MASK_RX_BCN_TIMER_8814B << BIT_SHIFT_RX_BCN_TIMER_8814B)
+#define BIT_CLEAR_RX_BCN_TIMER_8814B(x) ((x) & (~BITS_RX_BCN_TIMER_8814B))
+#define BIT_GET_RX_BCN_TIMER_8814B(x)                                          \
+	(((x) >> BIT_SHIFT_RX_BCN_TIMER_8814B) & BIT_MASK_RX_BCN_TIMER_8814B)
+#define BIT_SET_RX_BCN_TIMER_8814B(x, v)                                       \
+	(BIT_CLEAR_RX_BCN_TIMER_8814B(x) | BIT_RX_BCN_TIMER_8814B(v))
+
+/* 2 REG_TBTT_CTN_AREA_V1_8814B */
+
+#define BIT_SHIFT_TBTT_CTN_AREA_8814B 0
+#define BIT_MASK_TBTT_CTN_AREA_8814B 0xff
+#define BIT_TBTT_CTN_AREA_8814B(x)                                             \
+	(((x) & BIT_MASK_TBTT_CTN_AREA_8814B) << BIT_SHIFT_TBTT_CTN_AREA_8814B)
+#define BITS_TBTT_CTN_AREA_8814B                                               \
+	(BIT_MASK_TBTT_CTN_AREA_8814B << BIT_SHIFT_TBTT_CTN_AREA_8814B)
+#define BIT_CLEAR_TBTT_CTN_AREA_8814B(x) ((x) & (~BITS_TBTT_CTN_AREA_8814B))
+#define BIT_GET_TBTT_CTN_AREA_8814B(x)                                         \
+	(((x) >> BIT_SHIFT_TBTT_CTN_AREA_8814B) & BIT_MASK_TBTT_CTN_AREA_8814B)
+#define BIT_SET_TBTT_CTN_AREA_8814B(x, v)                                      \
+	(BIT_CLEAR_TBTT_CTN_AREA_8814B(x) | BIT_TBTT_CTN_AREA_8814B(v))
+
+/* 2 REG_BCN_MAX_ERR_V1_8814B */
+
+#define BIT_SHIFT_BCN_MAX_ERR_8814B 0
+#define BIT_MASK_BCN_MAX_ERR_8814B 0xff
+#define BIT_BCN_MAX_ERR_8814B(x)                                               \
+	(((x) & BIT_MASK_BCN_MAX_ERR_8814B) << BIT_SHIFT_BCN_MAX_ERR_8814B)
+#define BITS_BCN_MAX_ERR_8814B                                                 \
+	(BIT_MASK_BCN_MAX_ERR_8814B << BIT_SHIFT_BCN_MAX_ERR_8814B)
+#define BIT_CLEAR_BCN_MAX_ERR_8814B(x) ((x) & (~BITS_BCN_MAX_ERR_8814B))
+#define BIT_GET_BCN_MAX_ERR_8814B(x)                                           \
+	(((x) >> BIT_SHIFT_BCN_MAX_ERR_8814B) & BIT_MASK_BCN_MAX_ERR_8814B)
+#define BIT_SET_BCN_MAX_ERR_8814B(x, v)                                        \
+	(BIT_CLEAR_BCN_MAX_ERR_8814B(x) | BIT_BCN_MAX_ERR_8814B(v))
+
+/* 2 REG_RXTSF_OFFSET_CCK_V1_8814B */
+
+#define BIT_SHIFT_CCK_RXTSF_OFFSET_8814B 0
+#define BIT_MASK_CCK_RXTSF_OFFSET_8814B 0xff
+#define BIT_CCK_RXTSF_OFFSET_8814B(x)                                          \
+	(((x) & BIT_MASK_CCK_RXTSF_OFFSET_8814B)                               \
+	 << BIT_SHIFT_CCK_RXTSF_OFFSET_8814B)
+#define BITS_CCK_RXTSF_OFFSET_8814B                                            \
+	(BIT_MASK_CCK_RXTSF_OFFSET_8814B << BIT_SHIFT_CCK_RXTSF_OFFSET_8814B)
+#define BIT_CLEAR_CCK_RXTSF_OFFSET_8814B(x)                                    \
+	((x) & (~BITS_CCK_RXTSF_OFFSET_8814B))
+#define BIT_GET_CCK_RXTSF_OFFSET_8814B(x)                                      \
+	(((x) >> BIT_SHIFT_CCK_RXTSF_OFFSET_8814B) &                           \
+	 BIT_MASK_CCK_RXTSF_OFFSET_8814B)
+#define BIT_SET_CCK_RXTSF_OFFSET_8814B(x, v)                                   \
+	(BIT_CLEAR_CCK_RXTSF_OFFSET_8814B(x) | BIT_CCK_RXTSF_OFFSET_8814B(v))
+
+/* 2 REG_RXTSF_OFFSET_OFDM_V1_8814B */
+
+#define BIT_SHIFT_OFDM_RXTSF_OFFSET_8814B 0
+#define BIT_MASK_OFDM_RXTSF_OFFSET_8814B 0xff
+#define BIT_OFDM_RXTSF_OFFSET_8814B(x)                                         \
+	(((x) & BIT_MASK_OFDM_RXTSF_OFFSET_8814B)                              \
+	 << BIT_SHIFT_OFDM_RXTSF_OFFSET_8814B)
+#define BITS_OFDM_RXTSF_OFFSET_8814B                                           \
+	(BIT_MASK_OFDM_RXTSF_OFFSET_8814B << BIT_SHIFT_OFDM_RXTSF_OFFSET_8814B)
+#define BIT_CLEAR_OFDM_RXTSF_OFFSET_8814B(x)                                   \
+	((x) & (~BITS_OFDM_RXTSF_OFFSET_8814B))
+#define BIT_GET_OFDM_RXTSF_OFFSET_8814B(x)                                     \
+	(((x) >> BIT_SHIFT_OFDM_RXTSF_OFFSET_8814B) &                          \
+	 BIT_MASK_OFDM_RXTSF_OFFSET_8814B)
+#define BIT_SET_OFDM_RXTSF_OFFSET_8814B(x, v)                                  \
+	(BIT_CLEAR_OFDM_RXTSF_OFFSET_8814B(x) | BIT_OFDM_RXTSF_OFFSET_8814B(v))
+
+/* 2 REG_SUB_BCN_SPACE_8814B */
+
+#define BIT_SHIFT_SUB_BCN_SPACE_V2_8814B 0
+#define BIT_MASK_SUB_BCN_SPACE_V2_8814B 0xff
+#define BIT_SUB_BCN_SPACE_V2_8814B(x)                                          \
+	(((x) & BIT_MASK_SUB_BCN_SPACE_V2_8814B)                               \
+	 << BIT_SHIFT_SUB_BCN_SPACE_V2_8814B)
+#define BITS_SUB_BCN_SPACE_V2_8814B                                            \
+	(BIT_MASK_SUB_BCN_SPACE_V2_8814B << BIT_SHIFT_SUB_BCN_SPACE_V2_8814B)
+#define BIT_CLEAR_SUB_BCN_SPACE_V2_8814B(x)                                    \
+	((x) & (~BITS_SUB_BCN_SPACE_V2_8814B))
+#define BIT_GET_SUB_BCN_SPACE_V2_8814B(x)                                      \
+	(((x) >> BIT_SHIFT_SUB_BCN_SPACE_V2_8814B) &                           \
+	 BIT_MASK_SUB_BCN_SPACE_V2_8814B)
+#define BIT_SET_SUB_BCN_SPACE_V2_8814B(x, v)                                   \
+	(BIT_CLEAR_SUB_BCN_SPACE_V2_8814B(x) | BIT_SUB_BCN_SPACE_V2_8814B(v))
+
+/* 2 REG_MBID_NUM_V1_8814B */
+
+#define BIT_SHIFT_BCN_ERR_PORT_SEL_8814B 4
+#define BIT_MASK_BCN_ERR_PORT_SEL_8814B 0xf
+#define BIT_BCN_ERR_PORT_SEL_8814B(x)                                          \
+	(((x) & BIT_MASK_BCN_ERR_PORT_SEL_8814B)                               \
+	 << BIT_SHIFT_BCN_ERR_PORT_SEL_8814B)
+#define BITS_BCN_ERR_PORT_SEL_8814B                                            \
+	(BIT_MASK_BCN_ERR_PORT_SEL_8814B << BIT_SHIFT_BCN_ERR_PORT_SEL_8814B)
+#define BIT_CLEAR_BCN_ERR_PORT_SEL_8814B(x)                                    \
+	((x) & (~BITS_BCN_ERR_PORT_SEL_8814B))
+#define BIT_GET_BCN_ERR_PORT_SEL_8814B(x)                                      \
+	(((x) >> BIT_SHIFT_BCN_ERR_PORT_SEL_8814B) &                           \
+	 BIT_MASK_BCN_ERR_PORT_SEL_8814B)
+#define BIT_SET_BCN_ERR_PORT_SEL_8814B(x, v)                                   \
+	(BIT_CLEAR_BCN_ERR_PORT_SEL_8814B(x) | BIT_BCN_ERR_PORT_SEL_8814B(v))
+
+#define BIT_SHIFT_MBID_BCN_NUM_V1_8814B 0
+#define BIT_MASK_MBID_BCN_NUM_V1_8814B 0xf
+#define BIT_MBID_BCN_NUM_V1_8814B(x)                                           \
+	(((x) & BIT_MASK_MBID_BCN_NUM_V1_8814B)                                \
+	 << BIT_SHIFT_MBID_BCN_NUM_V1_8814B)
+#define BITS_MBID_BCN_NUM_V1_8814B                                             \
+	(BIT_MASK_MBID_BCN_NUM_V1_8814B << BIT_SHIFT_MBID_BCN_NUM_V1_8814B)
+#define BIT_CLEAR_MBID_BCN_NUM_V1_8814B(x) ((x) & (~BITS_MBID_BCN_NUM_V1_8814B))
+#define BIT_GET_MBID_BCN_NUM_V1_8814B(x)                                       \
+	(((x) >> BIT_SHIFT_MBID_BCN_NUM_V1_8814B) &                            \
+	 BIT_MASK_MBID_BCN_NUM_V1_8814B)
+#define BIT_SET_MBID_BCN_NUM_V1_8814B(x, v)                                    \
+	(BIT_CLEAR_MBID_BCN_NUM_V1_8814B(x) | BIT_MBID_BCN_NUM_V1_8814B(v))
+
+/* 2 REG_MBSSID_CTRL_V1_8814B */
+#define BIT_MBID_BCNQ15_EN_8814B BIT(15)
+#define BIT_MBID_BCNQ14_EN_8814B BIT(14)
+#define BIT_MBID_BCNQ13_EN_8814B BIT(13)
+#define BIT_MBID_BCNQ12_EN_8814B BIT(12)
+#define BIT_MBID_BCNQ11_EN_8814B BIT(11)
+#define BIT_MBID_BCNQ10_EN_8814B BIT(10)
+#define BIT_MBID_BCNQ9_EN_8814B BIT(9)
+#define BIT_MBID_BCNQ8_EN_8814B BIT(8)
+#define BIT_MBID_BCNQ7_EN_8814B BIT(7)
+#define BIT_MBID_BCNQ6_EN_8814B BIT(6)
+#define BIT_MBID_BCNQ5_EN_8814B BIT(5)
+#define BIT_MBID_BCNQ4_EN_8814B BIT(4)
+#define BIT_MBID_BCNQ3_EN_8814B BIT(3)
+#define BIT_MBID_BCNQ2_EN_8814B BIT(2)
+#define BIT_MBID_BCNQ1_EN_8814B BIT(1)
+#define BIT_MBID_BCNQ0_EN_8814B BIT(0)
+
+/* 2 REG_USTIME_TSF_V1_8814B */
+
+#define BIT_SHIFT_USTIME_TSF_V1_8814B 0
+#define BIT_MASK_USTIME_TSF_V1_8814B 0xff
+#define BIT_USTIME_TSF_V1_8814B(x)                                             \
+	(((x) & BIT_MASK_USTIME_TSF_V1_8814B) << BIT_SHIFT_USTIME_TSF_V1_8814B)
+#define BITS_USTIME_TSF_V1_8814B                                               \
+	(BIT_MASK_USTIME_TSF_V1_8814B << BIT_SHIFT_USTIME_TSF_V1_8814B)
+#define BIT_CLEAR_USTIME_TSF_V1_8814B(x) ((x) & (~BITS_USTIME_TSF_V1_8814B))
+#define BIT_GET_USTIME_TSF_V1_8814B(x)                                         \
+	(((x) >> BIT_SHIFT_USTIME_TSF_V1_8814B) & BIT_MASK_USTIME_TSF_V1_8814B)
+#define BIT_SET_USTIME_TSF_V1_8814B(x, v)                                      \
+	(BIT_CLEAR_USTIME_TSF_V1_8814B(x) | BIT_USTIME_TSF_V1_8814B(v))
+
+/* 2 REG_BW_CFG_8814B */
+#define BIT_SLEEP_32K_EN_8814B BIT(3)
+#define BIT_DIS_MARK_TSF_US_V1_8814B BIT(2)
+
+#define BIT_SHIFT_BW_CFG_8814B 0
+#define BIT_MASK_BW_CFG_8814B 0x3
+#define BIT_BW_CFG_8814B(x)                                                    \
+	(((x) & BIT_MASK_BW_CFG_8814B) << BIT_SHIFT_BW_CFG_8814B)
+#define BITS_BW_CFG_8814B (BIT_MASK_BW_CFG_8814B << BIT_SHIFT_BW_CFG_8814B)
+#define BIT_CLEAR_BW_CFG_8814B(x) ((x) & (~BITS_BW_CFG_8814B))
+#define BIT_GET_BW_CFG_8814B(x)                                                \
+	(((x) >> BIT_SHIFT_BW_CFG_8814B) & BIT_MASK_BW_CFG_8814B)
+#define BIT_SET_BW_CFG_8814B(x, v)                                             \
+	(BIT_CLEAR_BW_CFG_8814B(x) | BIT_BW_CFG_8814B(v))
+
+/* 2 REG_ATIMWND_CFG_8814B */
+
+#define BIT_SHIFT_ATIMWND_V1_8814B 0
+#define BIT_MASK_ATIMWND_V1_8814B 0xff
+#define BIT_ATIMWND_V1_8814B(x)                                                \
+	(((x) & BIT_MASK_ATIMWND_V1_8814B) << BIT_SHIFT_ATIMWND_V1_8814B)
+#define BITS_ATIMWND_V1_8814B                                                  \
+	(BIT_MASK_ATIMWND_V1_8814B << BIT_SHIFT_ATIMWND_V1_8814B)
+#define BIT_CLEAR_ATIMWND_V1_8814B(x) ((x) & (~BITS_ATIMWND_V1_8814B))
+#define BIT_GET_ATIMWND_V1_8814B(x)                                            \
+	(((x) >> BIT_SHIFT_ATIMWND_V1_8814B) & BIT_MASK_ATIMWND_V1_8814B)
+#define BIT_SET_ATIMWND_V1_8814B(x, v)                                         \
+	(BIT_CLEAR_ATIMWND_V1_8814B(x) | BIT_ATIMWND_V1_8814B(v))
+
+/* 2 REG_DTIM_COUNTER_CFG_8814B */
+
+#define BIT_SHIFT_DTIM_COUNT_8814B 0
+#define BIT_MASK_DTIM_COUNT_8814B 0xff
+#define BIT_DTIM_COUNT_8814B(x)                                                \
+	(((x) & BIT_MASK_DTIM_COUNT_8814B) << BIT_SHIFT_DTIM_COUNT_8814B)
+#define BITS_DTIM_COUNT_8814B                                                  \
+	(BIT_MASK_DTIM_COUNT_8814B << BIT_SHIFT_DTIM_COUNT_8814B)
+#define BIT_CLEAR_DTIM_COUNT_8814B(x) ((x) & (~BITS_DTIM_COUNT_8814B))
+#define BIT_GET_DTIM_COUNT_8814B(x)                                            \
+	(((x) >> BIT_SHIFT_DTIM_COUNT_8814B) & BIT_MASK_DTIM_COUNT_8814B)
+#define BIT_SET_DTIM_COUNT_8814B(x, v)                                         \
+	(BIT_CLEAR_DTIM_COUNT_8814B(x) | BIT_DTIM_COUNT_8814B(v))
+
+/* 2 REG_ATIM_DTIM_CTRL_SEL_8814B */
+#define BIT_DTIM_BYPASS_V1_8814B BIT(7)
+
+#define BIT_SHIFT_ATIM_DTIM_SEL_8814B 0
+#define BIT_MASK_ATIM_DTIM_SEL_8814B 0x1f
+#define BIT_ATIM_DTIM_SEL_8814B(x)                                             \
+	(((x) & BIT_MASK_ATIM_DTIM_SEL_8814B) << BIT_SHIFT_ATIM_DTIM_SEL_8814B)
+#define BITS_ATIM_DTIM_SEL_8814B                                               \
+	(BIT_MASK_ATIM_DTIM_SEL_8814B << BIT_SHIFT_ATIM_DTIM_SEL_8814B)
+#define BIT_CLEAR_ATIM_DTIM_SEL_8814B(x) ((x) & (~BITS_ATIM_DTIM_SEL_8814B))
+#define BIT_GET_ATIM_DTIM_SEL_8814B(x)                                         \
+	(((x) >> BIT_SHIFT_ATIM_DTIM_SEL_8814B) & BIT_MASK_ATIM_DTIM_SEL_8814B)
+#define BIT_SET_ATIM_DTIM_SEL_8814B(x, v)                                      \
+	(BIT_CLEAR_ATIM_DTIM_SEL_8814B(x) | BIT_ATIM_DTIM_SEL_8814B(v))
+
+/* 2 REG_ATIMUGT_V1_8814B */
+
+#define BIT_SHIFT_ATIM_URGENT_8814B 0
+#define BIT_MASK_ATIM_URGENT_8814B 0xff
+#define BIT_ATIM_URGENT_8814B(x)                                               \
+	(((x) & BIT_MASK_ATIM_URGENT_8814B) << BIT_SHIFT_ATIM_URGENT_8814B)
+#define BITS_ATIM_URGENT_8814B                                                 \
+	(BIT_MASK_ATIM_URGENT_8814B << BIT_SHIFT_ATIM_URGENT_8814B)
+#define BIT_CLEAR_ATIM_URGENT_8814B(x) ((x) & (~BITS_ATIM_URGENT_8814B))
+#define BIT_GET_ATIM_URGENT_8814B(x)                                           \
+	(((x) >> BIT_SHIFT_ATIM_URGENT_8814B) & BIT_MASK_ATIM_URGENT_8814B)
+#define BIT_SET_ATIM_URGENT_8814B(x, v)                                        \
+	(BIT_CLEAR_ATIM_URGENT_8814B(x) | BIT_ATIM_URGENT_8814B(v))
+
+/* 2 REG_BCNDROPCTRL_V1_8814B */
+#define BIT_BEACON_DROP_EN_8814B BIT(7)
+
+#define BIT_SHIFT_BEACON_DROP_IVL_8814B 0
+#define BIT_MASK_BEACON_DROP_IVL_8814B 0x7f
+#define BIT_BEACON_DROP_IVL_8814B(x)                                           \
+	(((x) & BIT_MASK_BEACON_DROP_IVL_8814B)                                \
+	 << BIT_SHIFT_BEACON_DROP_IVL_8814B)
+#define BITS_BEACON_DROP_IVL_8814B                                             \
+	(BIT_MASK_BEACON_DROP_IVL_8814B << BIT_SHIFT_BEACON_DROP_IVL_8814B)
+#define BIT_CLEAR_BEACON_DROP_IVL_8814B(x) ((x) & (~BITS_BEACON_DROP_IVL_8814B))
+#define BIT_GET_BEACON_DROP_IVL_8814B(x)                                       \
+	(((x) >> BIT_SHIFT_BEACON_DROP_IVL_8814B) &                            \
+	 BIT_MASK_BEACON_DROP_IVL_8814B)
+#define BIT_SET_BEACON_DROP_IVL_8814B(x, v)                                    \
+	(BIT_CLEAR_BEACON_DROP_IVL_8814B(x) | BIT_BEACON_DROP_IVL_8814B(v))
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_DIS_ATIM_V1_8814B */
+#define BIT_DIS_ATIM_P4_8814B BIT(19)
+#define BIT_DIS_ATIM_P3_8814B BIT(18)
+#define BIT_DIS_ATIM_P2_8814B BIT(17)
+#define BIT_DIS_ATIM_P1_8814B BIT(16)
+#define BIT_DIS_ATIM_VAP15_8814B BIT(15)
+#define BIT_DIS_ATIM_VAP14_8814B BIT(14)
+#define BIT_DIS_ATIM_VAP13_8814B BIT(13)
+#define BIT_DIS_ATIM_VAP12_8814B BIT(12)
+#define BIT_DIS_ATIM_VAP11_8814B BIT(11)
+#define BIT_DIS_ATIM_VAP10_8814B BIT(10)
+#define BIT_DIS_ATIM_VAP9_8814B BIT(9)
+#define BIT_DIS_ATIM_VAP8_8814B BIT(8)
+#define BIT_DIS_ATIM_VAP7_8814B BIT(7)
+#define BIT_DIS_ATIM_VAP6_8814B BIT(6)
+#define BIT_DIS_ATIM_VAP5_8814B BIT(5)
+#define BIT_DIS_ATIM_VAP4_8814B BIT(4)
+#define BIT_DIS_ATIM_VAP3_8814B BIT(3)
+#define BIT_DIS_ATIM_VAP2_8814B BIT(2)
+#define BIT_DIS_ATIM_VAP1_8814B BIT(1)
+#define BIT_DIS_ATIM_ROOT_P0_8814B BIT(0)
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_HIQ_NO_LMT_EN_V1_8814B */
+#define BIT_HIQ_NO_LMT_EN_P4_8814B BIT(19)
+#define BIT_HIQ_NO_LMT_EN_P3_8814B BIT(18)
+#define BIT_HIQ_NO_LMT_EN_P2_8814B BIT(17)
+#define BIT_HIQ_NO_LMT_EN_P1_8814B BIT(16)
+#define BIT_HIQ_NO_LMT_EN_VAP15_8814B BIT(15)
+#define BIT_HIQ_NO_LMT_EN_VAP14_8814B BIT(14)
+#define BIT_HIQ_NO_LMT_EN_VAP13_8814B BIT(13)
+#define BIT_HIQ_NO_LMT_EN_VAP12_8814B BIT(12)
+#define BIT_HIQ_NO_LMT_EN_VAP11_8814B BIT(11)
+#define BIT_HIQ_NO_LMT_EN_VAP10_8814B BIT(10)
+#define BIT_HIQ_NO_LMT_EN_VAP9_8814B BIT(9)
+#define BIT_HIQ_NO_LMT_EN_VAP8_8814B BIT(8)
+#define BIT_HIQ_NO_LMT_EN_VAP7_8814B BIT(7)
+#define BIT_HIQ_NO_LMT_EN_VAP6_8814B BIT(6)
+#define BIT_HIQ_NO_LMT_EN_VAP5_8814B BIT(5)
+#define BIT_HIQ_NO_LMT_EN_VAP4_8814B BIT(4)
+#define BIT_HIQ_NO_LMT_EN_VAP3_8814B BIT(3)
+#define BIT_HIQ_NO_LMT_EN_VAP2_8814B BIT(2)
+#define BIT_HIQ_NO_LMT_EN_VAP1_8814B BIT(1)
+#define BIT_HIQ_NO_LMT_EN_ROOT_P0_8814B BIT(0)
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_P2PPS_CTRL_V1_8814B */
+#define BIT_P2P_PWR_RST1_V2_8814B BIT(15)
+#define BIT_P2P_PWR_RST0_V2_8814B BIT(14)
+#define BIT_EN_TSFBIT32_RST_P2P_V1_8814B BIT(13)
+
+#define BIT_SHIFT_NOA_UNIT0_SEL_V1_8814B 8
+#define BIT_MASK_NOA_UNIT0_SEL_V1_8814B 0x7
+#define BIT_NOA_UNIT0_SEL_V1_8814B(x)                                          \
+	(((x) & BIT_MASK_NOA_UNIT0_SEL_V1_8814B)                               \
+	 << BIT_SHIFT_NOA_UNIT0_SEL_V1_8814B)
+#define BITS_NOA_UNIT0_SEL_V1_8814B                                            \
+	(BIT_MASK_NOA_UNIT0_SEL_V1_8814B << BIT_SHIFT_NOA_UNIT0_SEL_V1_8814B)
+#define BIT_CLEAR_NOA_UNIT0_SEL_V1_8814B(x)                                    \
+	((x) & (~BITS_NOA_UNIT0_SEL_V1_8814B))
+#define BIT_GET_NOA_UNIT0_SEL_V1_8814B(x)                                      \
+	(((x) >> BIT_SHIFT_NOA_UNIT0_SEL_V1_8814B) &                           \
+	 BIT_MASK_NOA_UNIT0_SEL_V1_8814B)
+#define BIT_SET_NOA_UNIT0_SEL_V1_8814B(x, v)                                   \
+	(BIT_CLEAR_NOA_UNIT0_SEL_V1_8814B(x) | BIT_NOA_UNIT0_SEL_V1_8814B(v))
+
+#define BIT_P2P_CTW_ALLSTASLEEP_V1_8814B BIT(7)
+#define BIT_P2P_OFF_DISTX_EN_V1_8814B BIT(6)
+#define BIT_PWR_MGT_EN_V1_8814B BIT(5)
+#define BIT_P2P_NOA1_EN_V1_8814B BIT(2)
+#define BIT_P2P_NOA0_EN_V1_8814B BIT(1)
+
+/* 2 REG_P2PPS_SPEC_STATE_V1_8814B */
+#define BIT_SPEC_POWER_STATE_8814B BIT(7)
+#define BIT_SPEC_CTWINDOW_ON_8814B BIT(6)
+#define BIT_SPEC_BEACON_AREA_ON_8814B BIT(5)
+#define BIT_SPEC_CTWIN_EARLY_DISTX_8814B BIT(4)
+#define BIT_SPEC_NOA1_OFF_PERIOD_8814B BIT(3)
+#define BIT_SPEC_FORCE_DOZE1_8814B BIT(2)
+#define BIT_SPEC_NOA0_OFF_PERIOD_8814B BIT(1)
+#define BIT_SPEC_FORCE_DOZE0_8814B BIT(0)
+
+/* 2 REG_P2PPS_STATE_V1_8814B */
+#define BIT_POWER_STATE_8814B BIT(7)
+#define BIT_CTWINDOW_ON_8814B BIT(6)
+#define BIT_BEACON_AREA_ON_8814B BIT(5)
+#define BIT_CTWIN_EARLY_DISTX_8814B BIT(4)
+#define BIT_NOA1_OFF_PERIOD_8814B BIT(3)
+#define BIT_FORCE_DOZE1_8814B BIT(2)
+#define BIT_NOA0_OFF_PERIOD_8814B BIT(1)
+#define BIT_FORCE_DOZE0_8814B BIT(0)
+
+/* 2 REG_P2PPS1_CTRL_V1_8814B */
+#define BIT_P2P1_PWR_RST1_V2_8814B BIT(15)
+#define BIT_P2P1_PWR_RST0_V2_8814B BIT(14)
+#define BIT_EN_TSFBIT32_RST_P2P1_V1_8814B BIT(13)
+
+#define BIT_SHIFT_NOA_UNIT1_SEL_V1_8814B 8
+#define BIT_MASK_NOA_UNIT1_SEL_V1_8814B 0x7
+#define BIT_NOA_UNIT1_SEL_V1_8814B(x)                                          \
+	(((x) & BIT_MASK_NOA_UNIT1_SEL_V1_8814B)                               \
+	 << BIT_SHIFT_NOA_UNIT1_SEL_V1_8814B)
+#define BITS_NOA_UNIT1_SEL_V1_8814B                                            \
+	(BIT_MASK_NOA_UNIT1_SEL_V1_8814B << BIT_SHIFT_NOA_UNIT1_SEL_V1_8814B)
+#define BIT_CLEAR_NOA_UNIT1_SEL_V1_8814B(x)                                    \
+	((x) & (~BITS_NOA_UNIT1_SEL_V1_8814B))
+#define BIT_GET_NOA_UNIT1_SEL_V1_8814B(x)                                      \
+	(((x) >> BIT_SHIFT_NOA_UNIT1_SEL_V1_8814B) &                           \
+	 BIT_MASK_NOA_UNIT1_SEL_V1_8814B)
+#define BIT_SET_NOA_UNIT1_SEL_V1_8814B(x, v)                                   \
+	(BIT_CLEAR_NOA_UNIT1_SEL_V1_8814B(x) | BIT_NOA_UNIT1_SEL_V1_8814B(v))
+
+#define BIT_P2P1_CTW_ALLSTASLEEP_V1_8814B BIT(7)
+#define BIT_P2P1_OFF_DISTX_EN_8814B BIT(6)
+#define BIT_P2P1_PWR_MGT_EN_V1_8814B BIT(5)
+#define BIT_P2P1_NOA1_EN_V1_8814B BIT(2)
+#define BIT_P2P1_NOA0_EN_V1_8814B BIT(1)
+
+/* 2 REG_P2PPS1_SPEC_STATE_V1_8814B */
+#define BIT_P2P1_SPEC_POWER_STATEP_8814B BIT(7)
+#define BIT_P2P1_SPEC_CTWINDOW_ON_8814B BIT(6)
+#define BIT_P2P1_SPEC_BEACON_AREA_ON_8814B BIT(5)
+#define BIT_P2P1_SPEC_CTWIN_EARLY_DISTX_8814B BIT(4)
+#define BIT_P2P1_SPEC_NOA1_OFF_PERIOD_8814B BIT(3)
+#define BIT_P2P1_SPEC_FORCE_DOZE1_8814B BIT(2)
+#define BIT_P2P1_SPEC_NOA0_OFF_PERIOD_8814B BIT(1)
+#define BIT_P2P1_SPEC_FORCE_DOZE0_8814B BIT(0)
+
+/* 2 REG_P2PPS1_STATE_V1_8814B */
+#define BIT_P2P1_POWER_STATE_8814B BIT(7)
+#define BIT_P2P1_CTWINDOW_ON_8814B BIT(6)
+#define BIT_P2P1_BEACON_AREA_ON_8814B BIT(5)
+#define BIT_P2P1_CTWIN_EARLY_DISTX_8814B BIT(4)
+#define BIT_P2P1_NOA1_OFF_PERIOD_8814B BIT(3)
+#define BIT_P2P1_FORCE_DOZE1_8814B BIT(2)
+#define BIT_P2P1_NOA0_OFF_PERIOD_8814B BIT(1)
+#define BIT_P2P1_FORCE_DOZE0_8814B BIT(0)
+
+/* 2 REG_P2PPS2_CTRL_V1_8814B */
+#define BIT_P2P2_PWR_RST1_V2_8814B BIT(15)
+#define BIT_P2P2_PWR_RST0_V2_8814B BIT(14)
+#define BIT_EN_TSFBIT32_RST_P2P2_V1_8814B BIT(13)
+
+#define BIT_SHIFT_NOA_UNIT2_SEL_V1_8814B 8
+#define BIT_MASK_NOA_UNIT2_SEL_V1_8814B 0x7
+#define BIT_NOA_UNIT2_SEL_V1_8814B(x)                                          \
+	(((x) & BIT_MASK_NOA_UNIT2_SEL_V1_8814B)                               \
+	 << BIT_SHIFT_NOA_UNIT2_SEL_V1_8814B)
+#define BITS_NOA_UNIT2_SEL_V1_8814B                                            \
+	(BIT_MASK_NOA_UNIT2_SEL_V1_8814B << BIT_SHIFT_NOA_UNIT2_SEL_V1_8814B)
+#define BIT_CLEAR_NOA_UNIT2_SEL_V1_8814B(x)                                    \
+	((x) & (~BITS_NOA_UNIT2_SEL_V1_8814B))
+#define BIT_GET_NOA_UNIT2_SEL_V1_8814B(x)                                      \
+	(((x) >> BIT_SHIFT_NOA_UNIT2_SEL_V1_8814B) &                           \
+	 BIT_MASK_NOA_UNIT2_SEL_V1_8814B)
+#define BIT_SET_NOA_UNIT2_SEL_V1_8814B(x, v)                                   \
+	(BIT_CLEAR_NOA_UNIT2_SEL_V1_8814B(x) | BIT_NOA_UNIT2_SEL_V1_8814B(v))
+
+#define BIT_P2P2_CTW_ALLSTASLEEP_V1_8814B BIT(7)
+#define BIT_P2P2_OFF_DISTX_EN_V1_8814B BIT(6)
+#define BIT_P2P2_PWR_MGT_EN_V1_8814B BIT(5)
+#define BIT_P2P2_NOA1_EN_V1_8814B BIT(2)
+#define BIT_P2P2_NOA0_EN_V1_8814B BIT(1)
+
+/* 2 REG_P2PPS2_SPEC_STATE_V1_8814B */
+#define BIT_P2P2_SPEC_POWER_STATEP_8814B BIT(7)
+#define BIT_P2P2_SPEC_CTWINDOW_ON_8814B BIT(6)
+#define BIT_P2P2_SPEC_BEACON_AREA_ON_8814B BIT(5)
+#define BIT_P2P2_SPEC_CTWIN_EARLY_DISTX_8814B BIT(4)
+#define BIT_P2P2_SPEC_NOA1_OFF_PERIOD_8814B BIT(3)
+#define BIT_P2P2_SPEC_FORCE_DOZE1_8814B BIT(2)
+#define BIT_P2P2_SPEC_NOA0_OFF_PERIOD_8814B BIT(1)
+#define BIT_P2P2_SPEC_FORCE_DOZE0_8814B BIT(0)
+
+/* 2 REG_P2PPS2_STATE_V1_8814B */
+#define BIT_P2P2_POWER_STATE_8814B BIT(7)
+#define BIT_P2P2_CTWINDOW_ON_8814B BIT(6)
+#define BIT_P2P2_BEACON_AREA_ON_8814B BIT(5)
+#define BIT_P2P2_CTWIN_EARLY_DISTX_8814B BIT(4)
+#define BIT_P2P2_NOA1_OFF_PERIOD_8814B BIT(3)
+#define BIT_P2P2_FORCE_DOZE1_8814B BIT(2)
+#define BIT_P2P2_NOA0_OFF_PERIOD_8814B BIT(1)
+#define BIT_P2P2_FORCE_DOZE0_8814B BIT(0)
+
+/* 2 REG_P2PON_DIS_TXTIME_V1_8814B */
+
+#define BIT_SHIFT_P2PON_DIS_TXTIME_8814B 0
+#define BIT_MASK_P2PON_DIS_TXTIME_8814B 0xff
+#define BIT_P2PON_DIS_TXTIME_8814B(x)                                          \
+	(((x) & BIT_MASK_P2PON_DIS_TXTIME_8814B)                               \
+	 << BIT_SHIFT_P2PON_DIS_TXTIME_8814B)
+#define BITS_P2PON_DIS_TXTIME_8814B                                            \
+	(BIT_MASK_P2PON_DIS_TXTIME_8814B << BIT_SHIFT_P2PON_DIS_TXTIME_8814B)
+#define BIT_CLEAR_P2PON_DIS_TXTIME_8814B(x)                                    \
+	((x) & (~BITS_P2PON_DIS_TXTIME_8814B))
+#define BIT_GET_P2PON_DIS_TXTIME_8814B(x)                                      \
+	(((x) >> BIT_SHIFT_P2PON_DIS_TXTIME_8814B) &                           \
+	 BIT_MASK_P2PON_DIS_TXTIME_8814B)
+#define BIT_SET_P2PON_DIS_TXTIME_8814B(x, v)                                   \
+	(BIT_CLEAR_P2PON_DIS_TXTIME_8814B(x) | BIT_P2PON_DIS_TXTIME_8814B(v))
+
+/* 2 REG_P2POFF_DIS_TXTIME_V1_8814B */
+
+#define BIT_SHIFT_P2POFF_DIS_TXTIME_8814B 0
+#define BIT_MASK_P2POFF_DIS_TXTIME_8814B 0xff
+#define BIT_P2POFF_DIS_TXTIME_8814B(x)                                         \
+	(((x) & BIT_MASK_P2POFF_DIS_TXTIME_8814B)                              \
+	 << BIT_SHIFT_P2POFF_DIS_TXTIME_8814B)
+#define BITS_P2POFF_DIS_TXTIME_8814B                                           \
+	(BIT_MASK_P2POFF_DIS_TXTIME_8814B << BIT_SHIFT_P2POFF_DIS_TXTIME_8814B)
+#define BIT_CLEAR_P2POFF_DIS_TXTIME_8814B(x)                                   \
+	((x) & (~BITS_P2POFF_DIS_TXTIME_8814B))
+#define BIT_GET_P2POFF_DIS_TXTIME_8814B(x)                                     \
+	(((x) >> BIT_SHIFT_P2POFF_DIS_TXTIME_8814B) &                          \
+	 BIT_MASK_P2POFF_DIS_TXTIME_8814B)
+#define BIT_SET_P2POFF_DIS_TXTIME_8814B(x, v)                                  \
+	(BIT_CLEAR_P2POFF_DIS_TXTIME_8814B(x) | BIT_P2POFF_DIS_TXTIME_8814B(v))
+
+/* 2 REG_CHG_POWER_BCN_AREA_8814B */
+#define BIT_CHG_POWER_BCN_AREA_8814B BIT(0)
+
+/* 2 REG_NOA_SEL_8814B */
+
+#define BIT_SHIFT_NOA_SEL_V1_8814B 0
+#define BIT_MASK_NOA_SEL_V1_8814B 0x7
+#define BIT_NOA_SEL_V1_8814B(x)                                                \
+	(((x) & BIT_MASK_NOA_SEL_V1_8814B) << BIT_SHIFT_NOA_SEL_V1_8814B)
+#define BITS_NOA_SEL_V1_8814B                                                  \
+	(BIT_MASK_NOA_SEL_V1_8814B << BIT_SHIFT_NOA_SEL_V1_8814B)
+#define BIT_CLEAR_NOA_SEL_V1_8814B(x) ((x) & (~BITS_NOA_SEL_V1_8814B))
+#define BIT_GET_NOA_SEL_V1_8814B(x)                                            \
+	(((x) >> BIT_SHIFT_NOA_SEL_V1_8814B) & BIT_MASK_NOA_SEL_V1_8814B)
+#define BIT_SET_NOA_SEL_V1_8814B(x, v)                                         \
+	(BIT_CLEAR_NOA_SEL_V1_8814B(x) | BIT_NOA_SEL_V1_8814B(v))
+
+/* 2 REG_NOA_PARAM_V1_8814B */
+
+#define BIT_SHIFT_NOA_DURATION_8814B 0
+#define BIT_MASK_NOA_DURATION_8814B 0xffffffffL
+#define BIT_NOA_DURATION_8814B(x)                                              \
+	(((x) & BIT_MASK_NOA_DURATION_8814B) << BIT_SHIFT_NOA_DURATION_8814B)
+#define BITS_NOA_DURATION_8814B                                                \
+	(BIT_MASK_NOA_DURATION_8814B << BIT_SHIFT_NOA_DURATION_8814B)
+#define BIT_CLEAR_NOA_DURATION_8814B(x) ((x) & (~BITS_NOA_DURATION_8814B))
+#define BIT_GET_NOA_DURATION_8814B(x)                                          \
+	(((x) >> BIT_SHIFT_NOA_DURATION_8814B) & BIT_MASK_NOA_DURATION_8814B)
+#define BIT_SET_NOA_DURATION_8814B(x, v)                                       \
+	(BIT_CLEAR_NOA_DURATION_8814B(x) | BIT_NOA_DURATION_8814B(v))
+
+/* 2 REG_NOA_PARAM_1_V1_8814B */
+
+#define BIT_SHIFT_NOA_INTERVAL_8814B 0
+#define BIT_MASK_NOA_INTERVAL_8814B 0xffffffffL
+#define BIT_NOA_INTERVAL_8814B(x)                                              \
+	(((x) & BIT_MASK_NOA_INTERVAL_8814B) << BIT_SHIFT_NOA_INTERVAL_8814B)
+#define BITS_NOA_INTERVAL_8814B                                                \
+	(BIT_MASK_NOA_INTERVAL_8814B << BIT_SHIFT_NOA_INTERVAL_8814B)
+#define BIT_CLEAR_NOA_INTERVAL_8814B(x) ((x) & (~BITS_NOA_INTERVAL_8814B))
+#define BIT_GET_NOA_INTERVAL_8814B(x)                                          \
+	(((x) >> BIT_SHIFT_NOA_INTERVAL_8814B) & BIT_MASK_NOA_INTERVAL_8814B)
+#define BIT_SET_NOA_INTERVAL_8814B(x, v)                                       \
+	(BIT_CLEAR_NOA_INTERVAL_8814B(x) | BIT_NOA_INTERVAL_8814B(v))
+
+/* 2 REG_NOA_PARAM_2_V1_8814B */
+
+#define BIT_SHIFT_NOA_START_TIME_8814B 0
+#define BIT_MASK_NOA_START_TIME_8814B 0xffffffffL
+#define BIT_NOA_START_TIME_8814B(x)                                            \
+	(((x) & BIT_MASK_NOA_START_TIME_8814B)                                 \
+	 << BIT_SHIFT_NOA_START_TIME_8814B)
+#define BITS_NOA_START_TIME_8814B                                              \
+	(BIT_MASK_NOA_START_TIME_8814B << BIT_SHIFT_NOA_START_TIME_8814B)
+#define BIT_CLEAR_NOA_START_TIME_8814B(x) ((x) & (~BITS_NOA_START_TIME_8814B))
+#define BIT_GET_NOA_START_TIME_8814B(x)                                        \
+	(((x) >> BIT_SHIFT_NOA_START_TIME_8814B) &                             \
+	 BIT_MASK_NOA_START_TIME_8814B)
+#define BIT_SET_NOA_START_TIME_8814B(x, v)                                     \
+	(BIT_CLEAR_NOA_START_TIME_8814B(x) | BIT_NOA_START_TIME_8814B(v))
+
+/* 2 REG_NOA_PARAM_3_V1_8814B */
+
+#define BIT_SHIFT_NOA_COUNT_V2_8814B 0
+#define BIT_MASK_NOA_COUNT_V2_8814B 0xffffffffL
+#define BIT_NOA_COUNT_V2_8814B(x)                                              \
+	(((x) & BIT_MASK_NOA_COUNT_V2_8814B) << BIT_SHIFT_NOA_COUNT_V2_8814B)
+#define BITS_NOA_COUNT_V2_8814B                                                \
+	(BIT_MASK_NOA_COUNT_V2_8814B << BIT_SHIFT_NOA_COUNT_V2_8814B)
+#define BIT_CLEAR_NOA_COUNT_V2_8814B(x) ((x) & (~BITS_NOA_COUNT_V2_8814B))
+#define BIT_GET_NOA_COUNT_V2_8814B(x)                                          \
+	(((x) >> BIT_SHIFT_NOA_COUNT_V2_8814B) & BIT_MASK_NOA_COUNT_V2_8814B)
+#define BIT_SET_NOA_COUNT_V2_8814B(x, v)                                       \
+	(BIT_CLEAR_NOA_COUNT_V2_8814B(x) | BIT_NOA_COUNT_V2_8814B(v))
+
+/* 2 REG_NOA_ON_ERLY_TIME_V1_8814B */
+
+#define BIT_SHIFT__NOA_ON_ERLY_TIME_8814B 0
+#define BIT_MASK__NOA_ON_ERLY_TIME_8814B 0xff
+#define BIT__NOA_ON_ERLY_TIME_8814B(x)                                         \
+	(((x) & BIT_MASK__NOA_ON_ERLY_TIME_8814B)                              \
+	 << BIT_SHIFT__NOA_ON_ERLY_TIME_8814B)
+#define BITS__NOA_ON_ERLY_TIME_8814B                                           \
+	(BIT_MASK__NOA_ON_ERLY_TIME_8814B << BIT_SHIFT__NOA_ON_ERLY_TIME_8814B)
+#define BIT_CLEAR__NOA_ON_ERLY_TIME_8814B(x)                                   \
+	((x) & (~BITS__NOA_ON_ERLY_TIME_8814B))
+#define BIT_GET__NOA_ON_ERLY_TIME_8814B(x)                                     \
+	(((x) >> BIT_SHIFT__NOA_ON_ERLY_TIME_8814B) &                          \
+	 BIT_MASK__NOA_ON_ERLY_TIME_8814B)
+#define BIT_SET__NOA_ON_ERLY_TIME_8814B(x, v)                                  \
+	(BIT_CLEAR__NOA_ON_ERLY_TIME_8814B(x) | BIT__NOA_ON_ERLY_TIME_8814B(v))
+
+/* 2 REG_NOA_OFF_ERLY_TIME_V1_8814B */
+
+#define BIT_SHIFT__NOA_OFF_ERLY_TIME_8814B 0
+#define BIT_MASK__NOA_OFF_ERLY_TIME_8814B 0xff
+#define BIT__NOA_OFF_ERLY_TIME_8814B(x)                                        \
+	(((x) & BIT_MASK__NOA_OFF_ERLY_TIME_8814B)                             \
+	 << BIT_SHIFT__NOA_OFF_ERLY_TIME_8814B)
+#define BITS__NOA_OFF_ERLY_TIME_8814B                                          \
+	(BIT_MASK__NOA_OFF_ERLY_TIME_8814B                                     \
+	 << BIT_SHIFT__NOA_OFF_ERLY_TIME_8814B)
+#define BIT_CLEAR__NOA_OFF_ERLY_TIME_8814B(x)                                  \
+	((x) & (~BITS__NOA_OFF_ERLY_TIME_8814B))
+#define BIT_GET__NOA_OFF_ERLY_TIME_8814B(x)                                    \
+	(((x) >> BIT_SHIFT__NOA_OFF_ERLY_TIME_8814B) &                         \
+	 BIT_MASK__NOA_OFF_ERLY_TIME_8814B)
+#define BIT_SET__NOA_OFF_ERLY_TIME_8814B(x, v)                                 \
+	(BIT_CLEAR__NOA_OFF_ERLY_TIME_8814B(x) |                               \
+	 BIT__NOA_OFF_ERLY_TIME_8814B(v))
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_P2PPS_HW_AUTO_PAUSE_CTRL_8814B */
+#define BIT_P2PPS_NOA_STOP_TX_HANG_8814B BIT(31)
+#define BIT_P2PPS_MACID_PAUSE_EN_8814B BIT(11)
+#define BIT_P2PPS__MGQ_PAUSE_8814B BIT(10)
+#define BIT_P2PPS__HIQ_PAUSE_8814B BIT(9)
+#define BIT_P2PPS__BCNQ_PAUSE_8814B BIT(8)
+
+#define BIT_SHIFT_P2PPS_MACID_PAUSE_8814B 0
+#define BIT_MASK_P2PPS_MACID_PAUSE_8814B 0xff
+#define BIT_P2PPS_MACID_PAUSE_8814B(x)                                         \
+	(((x) & BIT_MASK_P2PPS_MACID_PAUSE_8814B)                              \
+	 << BIT_SHIFT_P2PPS_MACID_PAUSE_8814B)
+#define BITS_P2PPS_MACID_PAUSE_8814B                                           \
+	(BIT_MASK_P2PPS_MACID_PAUSE_8814B << BIT_SHIFT_P2PPS_MACID_PAUSE_8814B)
+#define BIT_CLEAR_P2PPS_MACID_PAUSE_8814B(x)                                   \
+	((x) & (~BITS_P2PPS_MACID_PAUSE_8814B))
+#define BIT_GET_P2PPS_MACID_PAUSE_8814B(x)                                     \
+	(((x) >> BIT_SHIFT_P2PPS_MACID_PAUSE_8814B) &                          \
+	 BIT_MASK_P2PPS_MACID_PAUSE_8814B)
+#define BIT_SET_P2PPS_MACID_PAUSE_8814B(x, v)                                  \
+	(BIT_CLEAR_P2PPS_MACID_PAUSE_8814B(x) | BIT_P2PPS_MACID_PAUSE_8814B(v))
+
+/* 2 REG_P2PPS1_HW_AUTO_PAUSE_CTRL_8814B */
+#define BIT_P2PPS1_NOA_STOP_TX_HANG_8814B BIT(31)
+#define BIT_P2PPS1_MACID_PAUSE_EN_8814B BIT(11)
+#define BIT_P2PPS1__MGQ_PAUSE_8814B BIT(10)
+#define BIT_P2PPS1__HIQ_PAUSE_8814B BIT(9)
+#define BIT_P2PPS1__BCNQ_PAUSE_8814B BIT(8)
+
+#define BIT_SHIFT_P2PPS1_MACID_PAUSE_8814B 0
+#define BIT_MASK_P2PPS1_MACID_PAUSE_8814B 0xff
+#define BIT_P2PPS1_MACID_PAUSE_8814B(x)                                        \
+	(((x) & BIT_MASK_P2PPS1_MACID_PAUSE_8814B)                             \
+	 << BIT_SHIFT_P2PPS1_MACID_PAUSE_8814B)
+#define BITS_P2PPS1_MACID_PAUSE_8814B                                          \
+	(BIT_MASK_P2PPS1_MACID_PAUSE_8814B                                     \
+	 << BIT_SHIFT_P2PPS1_MACID_PAUSE_8814B)
+#define BIT_CLEAR_P2PPS1_MACID_PAUSE_8814B(x)                                  \
+	((x) & (~BITS_P2PPS1_MACID_PAUSE_8814B))
+#define BIT_GET_P2PPS1_MACID_PAUSE_8814B(x)                                    \
+	(((x) >> BIT_SHIFT_P2PPS1_MACID_PAUSE_8814B) &                         \
+	 BIT_MASK_P2PPS1_MACID_PAUSE_8814B)
+#define BIT_SET_P2PPS1_MACID_PAUSE_8814B(x, v)                                 \
+	(BIT_CLEAR_P2PPS1_MACID_PAUSE_8814B(x) |                               \
+	 BIT_P2PPS1_MACID_PAUSE_8814B(v))
+
+/* 2 REG_P2PPS2_HW_AUTO_PAUSE_CTRL_8814B */
+#define BIT_P2PPS2_NOA_STOP_TX_HANG_8814B BIT(31)
+#define BIT_P2PPS2_MACID_PAUSE_EN_8814B BIT(11)
+#define BIT_P2PPS2__MGQ_PAUSE_8814B BIT(10)
+#define BIT_P2PPS2__HIQ_PAUSE_8814B BIT(9)
+#define BIT_P2PPS2__BCNQ_PAUSE_8814B BIT(8)
+
+#define BIT_SHIFT_P2PPS2_MACID_PAUSE_8814B 0
+#define BIT_MASK_P2PPS2_MACID_PAUSE_8814B 0xff
+#define BIT_P2PPS2_MACID_PAUSE_8814B(x)                                        \
+	(((x) & BIT_MASK_P2PPS2_MACID_PAUSE_8814B)                             \
+	 << BIT_SHIFT_P2PPS2_MACID_PAUSE_8814B)
+#define BITS_P2PPS2_MACID_PAUSE_8814B                                          \
+	(BIT_MASK_P2PPS2_MACID_PAUSE_8814B                                     \
+	 << BIT_SHIFT_P2PPS2_MACID_PAUSE_8814B)
+#define BIT_CLEAR_P2PPS2_MACID_PAUSE_8814B(x)                                  \
+	((x) & (~BITS_P2PPS2_MACID_PAUSE_8814B))
+#define BIT_GET_P2PPS2_MACID_PAUSE_8814B(x)                                    \
+	(((x) >> BIT_SHIFT_P2PPS2_MACID_PAUSE_8814B) &                         \
+	 BIT_MASK_P2PPS2_MACID_PAUSE_8814B)
+#define BIT_SET_P2PPS2_MACID_PAUSE_8814B(x, v)                                 \
+	(BIT_CLEAR_P2PPS2_MACID_PAUSE_8814B(x) |                               \
+	 BIT_P2PPS2_MACID_PAUSE_8814B(v))
+
+/* 2 REG_RX_TBTT_SHIFT_8814B */
+
+#define BIT_SHIFT_RX_TBTT_SHIFT_SEL_8814B 24
+#define BIT_MASK_RX_TBTT_SHIFT_SEL_8814B 0x7
+#define BIT_RX_TBTT_SHIFT_SEL_8814B(x)                                         \
+	(((x) & BIT_MASK_RX_TBTT_SHIFT_SEL_8814B)                              \
+	 << BIT_SHIFT_RX_TBTT_SHIFT_SEL_8814B)
+#define BITS_RX_TBTT_SHIFT_SEL_8814B                                           \
+	(BIT_MASK_RX_TBTT_SHIFT_SEL_8814B << BIT_SHIFT_RX_TBTT_SHIFT_SEL_8814B)
+#define BIT_CLEAR_RX_TBTT_SHIFT_SEL_8814B(x)                                   \
+	((x) & (~BITS_RX_TBTT_SHIFT_SEL_8814B))
+#define BIT_GET_RX_TBTT_SHIFT_SEL_8814B(x)                                     \
+	(((x) >> BIT_SHIFT_RX_TBTT_SHIFT_SEL_8814B) &                          \
+	 BIT_MASK_RX_TBTT_SHIFT_SEL_8814B)
+#define BIT_SET_RX_TBTT_SHIFT_SEL_8814B(x, v)                                  \
+	(BIT_CLEAR_RX_TBTT_SHIFT_SEL_8814B(x) | BIT_RX_TBTT_SHIFT_SEL_8814B(v))
+
+#define BIT_RX_TBTT_SHIFT_RW_FLAG_8814B BIT(15)
+
+#define BIT_SHIFT_RX_TBTT_SHIFT_OFFSET_8814B 0
+#define BIT_MASK_RX_TBTT_SHIFT_OFFSET_8814B 0xfff
+#define BIT_RX_TBTT_SHIFT_OFFSET_8814B(x)                                      \
+	(((x) & BIT_MASK_RX_TBTT_SHIFT_OFFSET_8814B)                           \
+	 << BIT_SHIFT_RX_TBTT_SHIFT_OFFSET_8814B)
+#define BITS_RX_TBTT_SHIFT_OFFSET_8814B                                        \
+	(BIT_MASK_RX_TBTT_SHIFT_OFFSET_8814B                                   \
+	 << BIT_SHIFT_RX_TBTT_SHIFT_OFFSET_8814B)
+#define BIT_CLEAR_RX_TBTT_SHIFT_OFFSET_8814B(x)                                \
+	((x) & (~BITS_RX_TBTT_SHIFT_OFFSET_8814B))
+#define BIT_GET_RX_TBTT_SHIFT_OFFSET_8814B(x)                                  \
+	(((x) >> BIT_SHIFT_RX_TBTT_SHIFT_OFFSET_8814B) &                       \
+	 BIT_MASK_RX_TBTT_SHIFT_OFFSET_8814B)
+#define BIT_SET_RX_TBTT_SHIFT_OFFSET_8814B(x, v)                               \
+	(BIT_CLEAR_RX_TBTT_SHIFT_OFFSET_8814B(x) |                             \
+	 BIT_RX_TBTT_SHIFT_OFFSET_8814B(v))
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_FREERUN_CNT_LOW_8814B */
+
+#define BIT_SHIFT_FREERUN_CNT_LOW_8814B 0
+#define BIT_MASK_FREERUN_CNT_LOW_8814B 0xffffffffL
+#define BIT_FREERUN_CNT_LOW_8814B(x)                                           \
+	(((x) & BIT_MASK_FREERUN_CNT_LOW_8814B)                                \
+	 << BIT_SHIFT_FREERUN_CNT_LOW_8814B)
+#define BITS_FREERUN_CNT_LOW_8814B                                             \
+	(BIT_MASK_FREERUN_CNT_LOW_8814B << BIT_SHIFT_FREERUN_CNT_LOW_8814B)
+#define BIT_CLEAR_FREERUN_CNT_LOW_8814B(x) ((x) & (~BITS_FREERUN_CNT_LOW_8814B))
+#define BIT_GET_FREERUN_CNT_LOW_8814B(x)                                       \
+	(((x) >> BIT_SHIFT_FREERUN_CNT_LOW_8814B) &                            \
+	 BIT_MASK_FREERUN_CNT_LOW_8814B)
+#define BIT_SET_FREERUN_CNT_LOW_8814B(x, v)                                    \
+	(BIT_CLEAR_FREERUN_CNT_LOW_8814B(x) | BIT_FREERUN_CNT_LOW_8814B(v))
+
+/* 2 REG_FREERUN_CNT_HIGH_8814B */
+
+#define BIT_SHIFT_FREERUN_CNT_HIGH_8814B 0
+#define BIT_MASK_FREERUN_CNT_HIGH_8814B 0xffffffffL
+#define BIT_FREERUN_CNT_HIGH_8814B(x)                                          \
+	(((x) & BIT_MASK_FREERUN_CNT_HIGH_8814B)                               \
+	 << BIT_SHIFT_FREERUN_CNT_HIGH_8814B)
+#define BITS_FREERUN_CNT_HIGH_8814B                                            \
+	(BIT_MASK_FREERUN_CNT_HIGH_8814B << BIT_SHIFT_FREERUN_CNT_HIGH_8814B)
+#define BIT_CLEAR_FREERUN_CNT_HIGH_8814B(x)                                    \
+	((x) & (~BITS_FREERUN_CNT_HIGH_8814B))
+#define BIT_GET_FREERUN_CNT_HIGH_8814B(x)                                      \
+	(((x) >> BIT_SHIFT_FREERUN_CNT_HIGH_8814B) &                           \
+	 BIT_MASK_FREERUN_CNT_HIGH_8814B)
+#define BIT_SET_FREERUN_CNT_HIGH_8814B(x, v)                                   \
+	(BIT_CLEAR_FREERUN_CNT_HIGH_8814B(x) | BIT_FREERUN_CNT_HIGH_8814B(v))
+
+/* 2 REG_CPUMGQ_TX_TIMER_V1_8814B */
+
+#define BIT_SHIFT_CPUMGQ_TX_TIMER_V1_8814B 0
+#define BIT_MASK_CPUMGQ_TX_TIMER_V1_8814B 0xffffffffL
+#define BIT_CPUMGQ_TX_TIMER_V1_8814B(x)                                        \
+	(((x) & BIT_MASK_CPUMGQ_TX_TIMER_V1_8814B)                             \
+	 << BIT_SHIFT_CPUMGQ_TX_TIMER_V1_8814B)
+#define BITS_CPUMGQ_TX_TIMER_V1_8814B                                          \
+	(BIT_MASK_CPUMGQ_TX_TIMER_V1_8814B                                     \
+	 << BIT_SHIFT_CPUMGQ_TX_TIMER_V1_8814B)
+#define BIT_CLEAR_CPUMGQ_TX_TIMER_V1_8814B(x)                                  \
+	((x) & (~BITS_CPUMGQ_TX_TIMER_V1_8814B))
+#define BIT_GET_CPUMGQ_TX_TIMER_V1_8814B(x)                                    \
+	(((x) >> BIT_SHIFT_CPUMGQ_TX_TIMER_V1_8814B) &                         \
+	 BIT_MASK_CPUMGQ_TX_TIMER_V1_8814B)
+#define BIT_SET_CPUMGQ_TX_TIMER_V1_8814B(x, v)                                 \
+	(BIT_CLEAR_CPUMGQ_TX_TIMER_V1_8814B(x) |                               \
+	 BIT_CPUMGQ_TX_TIMER_V1_8814B(v))
+
+/* 2 REG_PS_TIMER_0_8814B */
+
+#define BIT_SHIFT_PS_TIMER_0_8814B 0
+#define BIT_MASK_PS_TIMER_0_8814B 0xffffffffL
+#define BIT_PS_TIMER_0_8814B(x)                                                \
+	(((x) & BIT_MASK_PS_TIMER_0_8814B) << BIT_SHIFT_PS_TIMER_0_8814B)
+#define BITS_PS_TIMER_0_8814B                                                  \
+	(BIT_MASK_PS_TIMER_0_8814B << BIT_SHIFT_PS_TIMER_0_8814B)
+#define BIT_CLEAR_PS_TIMER_0_8814B(x) ((x) & (~BITS_PS_TIMER_0_8814B))
+#define BIT_GET_PS_TIMER_0_8814B(x)                                            \
+	(((x) >> BIT_SHIFT_PS_TIMER_0_8814B) & BIT_MASK_PS_TIMER_0_8814B)
+#define BIT_SET_PS_TIMER_0_8814B(x, v)                                         \
+	(BIT_CLEAR_PS_TIMER_0_8814B(x) | BIT_PS_TIMER_0_8814B(v))
+
+/* 2 REG_PS_TIMER_1_8814B */
+
+#define BIT_SHIFT_PS_TIMER_1_8814B 0
+#define BIT_MASK_PS_TIMER_1_8814B 0xffffffffL
+#define BIT_PS_TIMER_1_8814B(x)                                                \
+	(((x) & BIT_MASK_PS_TIMER_1_8814B) << BIT_SHIFT_PS_TIMER_1_8814B)
+#define BITS_PS_TIMER_1_8814B                                                  \
+	(BIT_MASK_PS_TIMER_1_8814B << BIT_SHIFT_PS_TIMER_1_8814B)
+#define BIT_CLEAR_PS_TIMER_1_8814B(x) ((x) & (~BITS_PS_TIMER_1_8814B))
+#define BIT_GET_PS_TIMER_1_8814B(x)                                            \
+	(((x) >> BIT_SHIFT_PS_TIMER_1_8814B) & BIT_MASK_PS_TIMER_1_8814B)
+#define BIT_SET_PS_TIMER_1_8814B(x, v)                                         \
+	(BIT_CLEAR_PS_TIMER_1_8814B(x) | BIT_PS_TIMER_1_8814B(v))
+
+/* 2 REG_PS_TIMER_2_8814B */
+
+#define BIT_SHIFT_PS_TIMER_2_8814B 0
+#define BIT_MASK_PS_TIMER_2_8814B 0xffffffffL
+#define BIT_PS_TIMER_2_8814B(x)                                                \
+	(((x) & BIT_MASK_PS_TIMER_2_8814B) << BIT_SHIFT_PS_TIMER_2_8814B)
+#define BITS_PS_TIMER_2_8814B                                                  \
+	(BIT_MASK_PS_TIMER_2_8814B << BIT_SHIFT_PS_TIMER_2_8814B)
+#define BIT_CLEAR_PS_TIMER_2_8814B(x) ((x) & (~BITS_PS_TIMER_2_8814B))
+#define BIT_GET_PS_TIMER_2_8814B(x)                                            \
+	(((x) >> BIT_SHIFT_PS_TIMER_2_8814B) & BIT_MASK_PS_TIMER_2_8814B)
+#define BIT_SET_PS_TIMER_2_8814B(x, v)                                         \
+	(BIT_CLEAR_PS_TIMER_2_8814B(x) | BIT_PS_TIMER_2_8814B(v))
+
+/* 2 REG_PS_TIMER_3_8814B */
+
+#define BIT_SHIFT_PS_TIMER_3_8814B 0
+#define BIT_MASK_PS_TIMER_3_8814B 0xffffffffL
+#define BIT_PS_TIMER_3_8814B(x)                                                \
+	(((x) & BIT_MASK_PS_TIMER_3_8814B) << BIT_SHIFT_PS_TIMER_3_8814B)
+#define BITS_PS_TIMER_3_8814B                                                  \
+	(BIT_MASK_PS_TIMER_3_8814B << BIT_SHIFT_PS_TIMER_3_8814B)
+#define BIT_CLEAR_PS_TIMER_3_8814B(x) ((x) & (~BITS_PS_TIMER_3_8814B))
+#define BIT_GET_PS_TIMER_3_8814B(x)                                            \
+	(((x) >> BIT_SHIFT_PS_TIMER_3_8814B) & BIT_MASK_PS_TIMER_3_8814B)
+#define BIT_SET_PS_TIMER_3_8814B(x, v)                                         \
+	(BIT_CLEAR_PS_TIMER_3_8814B(x) | BIT_PS_TIMER_3_8814B(v))
+
+/* 2 REG_PS_TIMER_4_8814B */
+
+#define BIT_SHIFT_PS_TIMER_4_8814B 0
+#define BIT_MASK_PS_TIMER_4_8814B 0xffffffffL
+#define BIT_PS_TIMER_4_8814B(x)                                                \
+	(((x) & BIT_MASK_PS_TIMER_4_8814B) << BIT_SHIFT_PS_TIMER_4_8814B)
+#define BITS_PS_TIMER_4_8814B                                                  \
+	(BIT_MASK_PS_TIMER_4_8814B << BIT_SHIFT_PS_TIMER_4_8814B)
+#define BIT_CLEAR_PS_TIMER_4_8814B(x) ((x) & (~BITS_PS_TIMER_4_8814B))
+#define BIT_GET_PS_TIMER_4_8814B(x)                                            \
+	(((x) >> BIT_SHIFT_PS_TIMER_4_8814B) & BIT_MASK_PS_TIMER_4_8814B)
+#define BIT_SET_PS_TIMER_4_8814B(x, v)                                         \
+	(BIT_CLEAR_PS_TIMER_4_8814B(x) | BIT_PS_TIMER_4_8814B(v))
+
+/* 2 REG_PS_TIMER_5_8814B */
+
+#define BIT_SHIFT_PS_TIMER_5_8814B 0
+#define BIT_MASK_PS_TIMER_5_8814B 0xffffffffL
+#define BIT_PS_TIMER_5_8814B(x)                                                \
+	(((x) & BIT_MASK_PS_TIMER_5_8814B) << BIT_SHIFT_PS_TIMER_5_8814B)
+#define BITS_PS_TIMER_5_8814B                                                  \
+	(BIT_MASK_PS_TIMER_5_8814B << BIT_SHIFT_PS_TIMER_5_8814B)
+#define BIT_CLEAR_PS_TIMER_5_8814B(x) ((x) & (~BITS_PS_TIMER_5_8814B))
+#define BIT_GET_PS_TIMER_5_8814B(x)                                            \
+	(((x) >> BIT_SHIFT_PS_TIMER_5_8814B) & BIT_MASK_PS_TIMER_5_8814B)
+#define BIT_SET_PS_TIMER_5_8814B(x, v)                                         \
+	(BIT_CLEAR_PS_TIMER_5_8814B(x) | BIT_PS_TIMER_5_8814B(v))
+
+/* 2 REG_PS_TIMER_01_CTRL_8814B */
+
+#define BIT_SHIFT_PS_TIMER_1_EARLY_TIME_8814B 24
+#define BIT_MASK_PS_TIMER_1_EARLY_TIME_8814B 0xff
+#define BIT_PS_TIMER_1_EARLY_TIME_8814B(x)                                     \
+	(((x) & BIT_MASK_PS_TIMER_1_EARLY_TIME_8814B)                          \
+	 << BIT_SHIFT_PS_TIMER_1_EARLY_TIME_8814B)
+#define BITS_PS_TIMER_1_EARLY_TIME_8814B                                       \
+	(BIT_MASK_PS_TIMER_1_EARLY_TIME_8814B                                  \
+	 << BIT_SHIFT_PS_TIMER_1_EARLY_TIME_8814B)
+#define BIT_CLEAR_PS_TIMER_1_EARLY_TIME_8814B(x)                               \
+	((x) & (~BITS_PS_TIMER_1_EARLY_TIME_8814B))
+#define BIT_GET_PS_TIMER_1_EARLY_TIME_8814B(x)                                 \
+	(((x) >> BIT_SHIFT_PS_TIMER_1_EARLY_TIME_8814B) &                      \
+	 BIT_MASK_PS_TIMER_1_EARLY_TIME_8814B)
+#define BIT_SET_PS_TIMER_1_EARLY_TIME_8814B(x, v)                              \
+	(BIT_CLEAR_PS_TIMER_1_EARLY_TIME_8814B(x) |                            \
+	 BIT_PS_TIMER_1_EARLY_TIME_8814B(v))
+
+#define BIT_PS_TIMER_1_EN_8814B BIT(23)
+
+#define BIT_SHIFT_PS_TIMER_1_TSF_SEL_8814B 16
+#define BIT_MASK_PS_TIMER_1_TSF_SEL_8814B 0x7
+#define BIT_PS_TIMER_1_TSF_SEL_8814B(x)                                        \
+	(((x) & BIT_MASK_PS_TIMER_1_TSF_SEL_8814B)                             \
+	 << BIT_SHIFT_PS_TIMER_1_TSF_SEL_8814B)
+#define BITS_PS_TIMER_1_TSF_SEL_8814B                                          \
+	(BIT_MASK_PS_TIMER_1_TSF_SEL_8814B                                     \
+	 << BIT_SHIFT_PS_TIMER_1_TSF_SEL_8814B)
+#define BIT_CLEAR_PS_TIMER_1_TSF_SEL_8814B(x)                                  \
+	((x) & (~BITS_PS_TIMER_1_TSF_SEL_8814B))
+#define BIT_GET_PS_TIMER_1_TSF_SEL_8814B(x)                                    \
+	(((x) >> BIT_SHIFT_PS_TIMER_1_TSF_SEL_8814B) &                         \
+	 BIT_MASK_PS_TIMER_1_TSF_SEL_8814B)
+#define BIT_SET_PS_TIMER_1_TSF_SEL_8814B(x, v)                                 \
+	(BIT_CLEAR_PS_TIMER_1_TSF_SEL_8814B(x) |                               \
+	 BIT_PS_TIMER_1_TSF_SEL_8814B(v))
+
+#define BIT_SHIFT_PS_TIMER_0_EARLY_TIME_8814B 8
+#define BIT_MASK_PS_TIMER_0_EARLY_TIME_8814B 0xff
+#define BIT_PS_TIMER_0_EARLY_TIME_8814B(x)                                     \
+	(((x) & BIT_MASK_PS_TIMER_0_EARLY_TIME_8814B)                          \
+	 << BIT_SHIFT_PS_TIMER_0_EARLY_TIME_8814B)
+#define BITS_PS_TIMER_0_EARLY_TIME_8814B                                       \
+	(BIT_MASK_PS_TIMER_0_EARLY_TIME_8814B                                  \
+	 << BIT_SHIFT_PS_TIMER_0_EARLY_TIME_8814B)
+#define BIT_CLEAR_PS_TIMER_0_EARLY_TIME_8814B(x)                               \
+	((x) & (~BITS_PS_TIMER_0_EARLY_TIME_8814B))
+#define BIT_GET_PS_TIMER_0_EARLY_TIME_8814B(x)                                 \
+	(((x) >> BIT_SHIFT_PS_TIMER_0_EARLY_TIME_8814B) &                      \
+	 BIT_MASK_PS_TIMER_0_EARLY_TIME_8814B)
+#define BIT_SET_PS_TIMER_0_EARLY_TIME_8814B(x, v)                              \
+	(BIT_CLEAR_PS_TIMER_0_EARLY_TIME_8814B(x) |                            \
+	 BIT_PS_TIMER_0_EARLY_TIME_8814B(v))
+
+#define BIT_PS_TIMER_0_EN_8814B BIT(7)
+
+#define BIT_SHIFT_PS_TIMER_0_TSF_SEL_8814B 0
+#define BIT_MASK_PS_TIMER_0_TSF_SEL_8814B 0x7
+#define BIT_PS_TIMER_0_TSF_SEL_8814B(x)                                        \
+	(((x) & BIT_MASK_PS_TIMER_0_TSF_SEL_8814B)                             \
+	 << BIT_SHIFT_PS_TIMER_0_TSF_SEL_8814B)
+#define BITS_PS_TIMER_0_TSF_SEL_8814B                                          \
+	(BIT_MASK_PS_TIMER_0_TSF_SEL_8814B                                     \
+	 << BIT_SHIFT_PS_TIMER_0_TSF_SEL_8814B)
+#define BIT_CLEAR_PS_TIMER_0_TSF_SEL_8814B(x)                                  \
+	((x) & (~BITS_PS_TIMER_0_TSF_SEL_8814B))
+#define BIT_GET_PS_TIMER_0_TSF_SEL_8814B(x)                                    \
+	(((x) >> BIT_SHIFT_PS_TIMER_0_TSF_SEL_8814B) &                         \
+	 BIT_MASK_PS_TIMER_0_TSF_SEL_8814B)
+#define BIT_SET_PS_TIMER_0_TSF_SEL_8814B(x, v)                                 \
+	(BIT_CLEAR_PS_TIMER_0_TSF_SEL_8814B(x) |                               \
+	 BIT_PS_TIMER_0_TSF_SEL_8814B(v))
+
+/* 2 REG_PS_TIMER_23_CTRL_8814B */
+
+#define BIT_SHIFT_PS_TIMER_3_EARLY_TIME_8814B 24
+#define BIT_MASK_PS_TIMER_3_EARLY_TIME_8814B 0xff
+#define BIT_PS_TIMER_3_EARLY_TIME_8814B(x)                                     \
+	(((x) & BIT_MASK_PS_TIMER_3_EARLY_TIME_8814B)                          \
+	 << BIT_SHIFT_PS_TIMER_3_EARLY_TIME_8814B)
+#define BITS_PS_TIMER_3_EARLY_TIME_8814B                                       \
+	(BIT_MASK_PS_TIMER_3_EARLY_TIME_8814B                                  \
+	 << BIT_SHIFT_PS_TIMER_3_EARLY_TIME_8814B)
+#define BIT_CLEAR_PS_TIMER_3_EARLY_TIME_8814B(x)                               \
+	((x) & (~BITS_PS_TIMER_3_EARLY_TIME_8814B))
+#define BIT_GET_PS_TIMER_3_EARLY_TIME_8814B(x)                                 \
+	(((x) >> BIT_SHIFT_PS_TIMER_3_EARLY_TIME_8814B) &                      \
+	 BIT_MASK_PS_TIMER_3_EARLY_TIME_8814B)
+#define BIT_SET_PS_TIMER_3_EARLY_TIME_8814B(x, v)                              \
+	(BIT_CLEAR_PS_TIMER_3_EARLY_TIME_8814B(x) |                            \
+	 BIT_PS_TIMER_3_EARLY_TIME_8814B(v))
+
+#define BIT_PS_TIMER_3_EN_8814B BIT(23)
+
+#define BIT_SHIFT_PS_TIMER_3_TSF_SEL_8814B 16
+#define BIT_MASK_PS_TIMER_3_TSF_SEL_8814B 0x7
+#define BIT_PS_TIMER_3_TSF_SEL_8814B(x)                                        \
+	(((x) & BIT_MASK_PS_TIMER_3_TSF_SEL_8814B)                             \
+	 << BIT_SHIFT_PS_TIMER_3_TSF_SEL_8814B)
+#define BITS_PS_TIMER_3_TSF_SEL_8814B                                          \
+	(BIT_MASK_PS_TIMER_3_TSF_SEL_8814B                                     \
+	 << BIT_SHIFT_PS_TIMER_3_TSF_SEL_8814B)
+#define BIT_CLEAR_PS_TIMER_3_TSF_SEL_8814B(x)                                  \
+	((x) & (~BITS_PS_TIMER_3_TSF_SEL_8814B))
+#define BIT_GET_PS_TIMER_3_TSF_SEL_8814B(x)                                    \
+	(((x) >> BIT_SHIFT_PS_TIMER_3_TSF_SEL_8814B) &                         \
+	 BIT_MASK_PS_TIMER_3_TSF_SEL_8814B)
+#define BIT_SET_PS_TIMER_3_TSF_SEL_8814B(x, v)                                 \
+	(BIT_CLEAR_PS_TIMER_3_TSF_SEL_8814B(x) |                               \
+	 BIT_PS_TIMER_3_TSF_SEL_8814B(v))
+
+#define BIT_SHIFT_PS_TIMER_2_EARLY_TIME_8814B 8
+#define BIT_MASK_PS_TIMER_2_EARLY_TIME_8814B 0xff
+#define BIT_PS_TIMER_2_EARLY_TIME_8814B(x)                                     \
+	(((x) & BIT_MASK_PS_TIMER_2_EARLY_TIME_8814B)                          \
+	 << BIT_SHIFT_PS_TIMER_2_EARLY_TIME_8814B)
+#define BITS_PS_TIMER_2_EARLY_TIME_8814B                                       \
+	(BIT_MASK_PS_TIMER_2_EARLY_TIME_8814B                                  \
+	 << BIT_SHIFT_PS_TIMER_2_EARLY_TIME_8814B)
+#define BIT_CLEAR_PS_TIMER_2_EARLY_TIME_8814B(x)                               \
+	((x) & (~BITS_PS_TIMER_2_EARLY_TIME_8814B))
+#define BIT_GET_PS_TIMER_2_EARLY_TIME_8814B(x)                                 \
+	(((x) >> BIT_SHIFT_PS_TIMER_2_EARLY_TIME_8814B) &                      \
+	 BIT_MASK_PS_TIMER_2_EARLY_TIME_8814B)
+#define BIT_SET_PS_TIMER_2_EARLY_TIME_8814B(x, v)                              \
+	(BIT_CLEAR_PS_TIMER_2_EARLY_TIME_8814B(x) |                            \
+	 BIT_PS_TIMER_2_EARLY_TIME_8814B(v))
+
+#define BIT_PS_TIMER_2_EN_8814B BIT(7)
+
+#define BIT_SHIFT_PS_TIMER_2_TSF_SEL_8814B 0
+#define BIT_MASK_PS_TIMER_2_TSF_SEL_8814B 0x7
+#define BIT_PS_TIMER_2_TSF_SEL_8814B(x)                                        \
+	(((x) & BIT_MASK_PS_TIMER_2_TSF_SEL_8814B)                             \
+	 << BIT_SHIFT_PS_TIMER_2_TSF_SEL_8814B)
+#define BITS_PS_TIMER_2_TSF_SEL_8814B                                          \
+	(BIT_MASK_PS_TIMER_2_TSF_SEL_8814B                                     \
+	 << BIT_SHIFT_PS_TIMER_2_TSF_SEL_8814B)
+#define BIT_CLEAR_PS_TIMER_2_TSF_SEL_8814B(x)                                  \
+	((x) & (~BITS_PS_TIMER_2_TSF_SEL_8814B))
+#define BIT_GET_PS_TIMER_2_TSF_SEL_8814B(x)                                    \
+	(((x) >> BIT_SHIFT_PS_TIMER_2_TSF_SEL_8814B) &                         \
+	 BIT_MASK_PS_TIMER_2_TSF_SEL_8814B)
+#define BIT_SET_PS_TIMER_2_TSF_SEL_8814B(x, v)                                 \
+	(BIT_CLEAR_PS_TIMER_2_TSF_SEL_8814B(x) |                               \
+	 BIT_PS_TIMER_2_TSF_SEL_8814B(v))
+
+/* 2 REG_PS_TIMER_45_CTRL_8814B */
+
+#define BIT_SHIFT_PS_TIMER_5_EARLY_TIME_8814B 24
+#define BIT_MASK_PS_TIMER_5_EARLY_TIME_8814B 0xff
+#define BIT_PS_TIMER_5_EARLY_TIME_8814B(x)                                     \
+	(((x) & BIT_MASK_PS_TIMER_5_EARLY_TIME_8814B)                          \
+	 << BIT_SHIFT_PS_TIMER_5_EARLY_TIME_8814B)
+#define BITS_PS_TIMER_5_EARLY_TIME_8814B                                       \
+	(BIT_MASK_PS_TIMER_5_EARLY_TIME_8814B                                  \
+	 << BIT_SHIFT_PS_TIMER_5_EARLY_TIME_8814B)
+#define BIT_CLEAR_PS_TIMER_5_EARLY_TIME_8814B(x)                               \
+	((x) & (~BITS_PS_TIMER_5_EARLY_TIME_8814B))
+#define BIT_GET_PS_TIMER_5_EARLY_TIME_8814B(x)                                 \
+	(((x) >> BIT_SHIFT_PS_TIMER_5_EARLY_TIME_8814B) &                      \
+	 BIT_MASK_PS_TIMER_5_EARLY_TIME_8814B)
+#define BIT_SET_PS_TIMER_5_EARLY_TIME_8814B(x, v)                              \
+	(BIT_CLEAR_PS_TIMER_5_EARLY_TIME_8814B(x) |                            \
+	 BIT_PS_TIMER_5_EARLY_TIME_8814B(v))
+
+#define BIT_PS_TIMER_5_EN_8814B BIT(23)
+
+#define BIT_SHIFT_PS_TIMER_5_TSF_SEL_8814B 16
+#define BIT_MASK_PS_TIMER_5_TSF_SEL_8814B 0x7
+#define BIT_PS_TIMER_5_TSF_SEL_8814B(x)                                        \
+	(((x) & BIT_MASK_PS_TIMER_5_TSF_SEL_8814B)                             \
+	 << BIT_SHIFT_PS_TIMER_5_TSF_SEL_8814B)
+#define BITS_PS_TIMER_5_TSF_SEL_8814B                                          \
+	(BIT_MASK_PS_TIMER_5_TSF_SEL_8814B                                     \
+	 << BIT_SHIFT_PS_TIMER_5_TSF_SEL_8814B)
+#define BIT_CLEAR_PS_TIMER_5_TSF_SEL_8814B(x)                                  \
+	((x) & (~BITS_PS_TIMER_5_TSF_SEL_8814B))
+#define BIT_GET_PS_TIMER_5_TSF_SEL_8814B(x)                                    \
+	(((x) >> BIT_SHIFT_PS_TIMER_5_TSF_SEL_8814B) &                         \
+	 BIT_MASK_PS_TIMER_5_TSF_SEL_8814B)
+#define BIT_SET_PS_TIMER_5_TSF_SEL_8814B(x, v)                                 \
+	(BIT_CLEAR_PS_TIMER_5_TSF_SEL_8814B(x) |                               \
+	 BIT_PS_TIMER_5_TSF_SEL_8814B(v))
+
+#define BIT_SHIFT_PS_TIMER_4_EARLY_TIME_8814B 8
+#define BIT_MASK_PS_TIMER_4_EARLY_TIME_8814B 0xff
+#define BIT_PS_TIMER_4_EARLY_TIME_8814B(x)                                     \
+	(((x) & BIT_MASK_PS_TIMER_4_EARLY_TIME_8814B)                          \
+	 << BIT_SHIFT_PS_TIMER_4_EARLY_TIME_8814B)
+#define BITS_PS_TIMER_4_EARLY_TIME_8814B                                       \
+	(BIT_MASK_PS_TIMER_4_EARLY_TIME_8814B                                  \
+	 << BIT_SHIFT_PS_TIMER_4_EARLY_TIME_8814B)
+#define BIT_CLEAR_PS_TIMER_4_EARLY_TIME_8814B(x)                               \
+	((x) & (~BITS_PS_TIMER_4_EARLY_TIME_8814B))
+#define BIT_GET_PS_TIMER_4_EARLY_TIME_8814B(x)                                 \
+	(((x) >> BIT_SHIFT_PS_TIMER_4_EARLY_TIME_8814B) &                      \
+	 BIT_MASK_PS_TIMER_4_EARLY_TIME_8814B)
+#define BIT_SET_PS_TIMER_4_EARLY_TIME_8814B(x, v)                              \
+	(BIT_CLEAR_PS_TIMER_4_EARLY_TIME_8814B(x) |                            \
+	 BIT_PS_TIMER_4_EARLY_TIME_8814B(v))
+
+#define BIT_PS_TIMER_4_EN_8814B BIT(7)
+
+#define BIT_SHIFT_PS_TIMER_4_TSF_SEL_8814B 0
+#define BIT_MASK_PS_TIMER_4_TSF_SEL_8814B 0x7
+#define BIT_PS_TIMER_4_TSF_SEL_8814B(x)                                        \
+	(((x) & BIT_MASK_PS_TIMER_4_TSF_SEL_8814B)                             \
+	 << BIT_SHIFT_PS_TIMER_4_TSF_SEL_8814B)
+#define BITS_PS_TIMER_4_TSF_SEL_8814B                                          \
+	(BIT_MASK_PS_TIMER_4_TSF_SEL_8814B                                     \
+	 << BIT_SHIFT_PS_TIMER_4_TSF_SEL_8814B)
+#define BIT_CLEAR_PS_TIMER_4_TSF_SEL_8814B(x)                                  \
+	((x) & (~BITS_PS_TIMER_4_TSF_SEL_8814B))
+#define BIT_GET_PS_TIMER_4_TSF_SEL_8814B(x)                                    \
+	(((x) >> BIT_SHIFT_PS_TIMER_4_TSF_SEL_8814B) &                         \
+	 BIT_MASK_PS_TIMER_4_TSF_SEL_8814B)
+#define BIT_SET_PS_TIMER_4_TSF_SEL_8814B(x, v)                                 \
+	(BIT_CLEAR_PS_TIMER_4_TSF_SEL_8814B(x) |                               \
+	 BIT_PS_TIMER_4_TSF_SEL_8814B(v))
+
+/* 2 REG_CPUMGQ_FREERUN_TIMER_CTRL_8814B */
+#define BIT_FREECNT_RST_V1_8814B BIT(23)
+#define BIT_EN_FREECNT_V1_8814B BIT(16)
+
+#define BIT_SHIFT_CPUMGQ_TX_TIMER_EARLY_V1_8814B 8
+#define BIT_MASK_CPUMGQ_TX_TIMER_EARLY_V1_8814B 0xff
+#define BIT_CPUMGQ_TX_TIMER_EARLY_V1_8814B(x)                                  \
+	(((x) & BIT_MASK_CPUMGQ_TX_TIMER_EARLY_V1_8814B)                       \
+	 << BIT_SHIFT_CPUMGQ_TX_TIMER_EARLY_V1_8814B)
+#define BITS_CPUMGQ_TX_TIMER_EARLY_V1_8814B                                    \
+	(BIT_MASK_CPUMGQ_TX_TIMER_EARLY_V1_8814B                               \
+	 << BIT_SHIFT_CPUMGQ_TX_TIMER_EARLY_V1_8814B)
+#define BIT_CLEAR_CPUMGQ_TX_TIMER_EARLY_V1_8814B(x)                            \
+	((x) & (~BITS_CPUMGQ_TX_TIMER_EARLY_V1_8814B))
+#define BIT_GET_CPUMGQ_TX_TIMER_EARLY_V1_8814B(x)                              \
+	(((x) >> BIT_SHIFT_CPUMGQ_TX_TIMER_EARLY_V1_8814B) &                   \
+	 BIT_MASK_CPUMGQ_TX_TIMER_EARLY_V1_8814B)
+#define BIT_SET_CPUMGQ_TX_TIMER_EARLY_V1_8814B(x, v)                           \
+	(BIT_CLEAR_CPUMGQ_TX_TIMER_EARLY_V1_8814B(x) |                         \
+	 BIT_CPUMGQ_TX_TIMER_EARLY_V1_8814B(v))
+
+#define BIT_CPUMGQ_TIMER_EN_V1_8814B BIT(7)
+#define BIT_CPUMGQ_DROP_BY_HOLDTIME_8814B BIT(5)
+#define BIT_CPUMGQ_TX_EN_V1_8814B BIT(4)
+
+#define BIT_SHIFT_CPUMGQ_TIMER_TSF_SEL_V1_8814B 0
+#define BIT_MASK_CPUMGQ_TIMER_TSF_SEL_V1_8814B 0x7
+#define BIT_CPUMGQ_TIMER_TSF_SEL_V1_8814B(x)                                   \
+	(((x) & BIT_MASK_CPUMGQ_TIMER_TSF_SEL_V1_8814B)                        \
+	 << BIT_SHIFT_CPUMGQ_TIMER_TSF_SEL_V1_8814B)
+#define BITS_CPUMGQ_TIMER_TSF_SEL_V1_8814B                                     \
+	(BIT_MASK_CPUMGQ_TIMER_TSF_SEL_V1_8814B                                \
+	 << BIT_SHIFT_CPUMGQ_TIMER_TSF_SEL_V1_8814B)
+#define BIT_CLEAR_CPUMGQ_TIMER_TSF_SEL_V1_8814B(x)                             \
+	((x) & (~BITS_CPUMGQ_TIMER_TSF_SEL_V1_8814B))
+#define BIT_GET_CPUMGQ_TIMER_TSF_SEL_V1_8814B(x)                               \
+	(((x) >> BIT_SHIFT_CPUMGQ_TIMER_TSF_SEL_V1_8814B) &                    \
+	 BIT_MASK_CPUMGQ_TIMER_TSF_SEL_V1_8814B)
+#define BIT_SET_CPUMGQ_TIMER_TSF_SEL_V1_8814B(x, v)                            \
+	(BIT_CLEAR_CPUMGQ_TIMER_TSF_SEL_V1_8814B(x) |                          \
+	 BIT_CPUMGQ_TIMER_TSF_SEL_V1_8814B(v))
+
+/* 2 REG_CPUMGQ_PROHIBIT_8814B */
+
+#define BIT_SHIFT_CPUMGQ_HOLD_TIME_8814B 8
+#define BIT_MASK_CPUMGQ_HOLD_TIME_8814B 0xfff
+#define BIT_CPUMGQ_HOLD_TIME_8814B(x)                                          \
+	(((x) & BIT_MASK_CPUMGQ_HOLD_TIME_8814B)                               \
+	 << BIT_SHIFT_CPUMGQ_HOLD_TIME_8814B)
+#define BITS_CPUMGQ_HOLD_TIME_8814B                                            \
+	(BIT_MASK_CPUMGQ_HOLD_TIME_8814B << BIT_SHIFT_CPUMGQ_HOLD_TIME_8814B)
+#define BIT_CLEAR_CPUMGQ_HOLD_TIME_8814B(x)                                    \
+	((x) & (~BITS_CPUMGQ_HOLD_TIME_8814B))
+#define BIT_GET_CPUMGQ_HOLD_TIME_8814B(x)                                      \
+	(((x) >> BIT_SHIFT_CPUMGQ_HOLD_TIME_8814B) &                           \
+	 BIT_MASK_CPUMGQ_HOLD_TIME_8814B)
+#define BIT_SET_CPUMGQ_HOLD_TIME_8814B(x, v)                                   \
+	(BIT_CLEAR_CPUMGQ_HOLD_TIME_8814B(x) | BIT_CPUMGQ_HOLD_TIME_8814B(v))
+
+#define BIT_SHIFT_CPUMGQ_PROHIBIT_SETUP_8814B 0
+#define BIT_MASK_CPUMGQ_PROHIBIT_SETUP_8814B 0xf
+#define BIT_CPUMGQ_PROHIBIT_SETUP_8814B(x)                                     \
+	(((x) & BIT_MASK_CPUMGQ_PROHIBIT_SETUP_8814B)                          \
+	 << BIT_SHIFT_CPUMGQ_PROHIBIT_SETUP_8814B)
+#define BITS_CPUMGQ_PROHIBIT_SETUP_8814B                                       \
+	(BIT_MASK_CPUMGQ_PROHIBIT_SETUP_8814B                                  \
+	 << BIT_SHIFT_CPUMGQ_PROHIBIT_SETUP_8814B)
+#define BIT_CLEAR_CPUMGQ_PROHIBIT_SETUP_8814B(x)                               \
+	((x) & (~BITS_CPUMGQ_PROHIBIT_SETUP_8814B))
+#define BIT_GET_CPUMGQ_PROHIBIT_SETUP_8814B(x)                                 \
+	(((x) >> BIT_SHIFT_CPUMGQ_PROHIBIT_SETUP_8814B) &                      \
+	 BIT_MASK_CPUMGQ_PROHIBIT_SETUP_8814B)
+#define BIT_SET_CPUMGQ_PROHIBIT_SETUP_8814B(x, v)                              \
+	(BIT_CLEAR_CPUMGQ_PROHIBIT_SETUP_8814B(x) |                            \
+	 BIT_CPUMGQ_PROHIBIT_SETUP_8814B(v))
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_RSVD_8814B */
+
+/* 2 REG_RSVD_8814B */
+
+/* 2 REG_TIMER_COMPARE_8814B */
+#define BIT_COMP_TRIGGER_8814B BIT(7)
+
+#define BIT_SHIFT_Y_COMP_8814B 4
+#define BIT_MASK_Y_COMP_8814B 0x7
+#define BIT_Y_COMP_8814B(x)                                                    \
+	(((x) & BIT_MASK_Y_COMP_8814B) << BIT_SHIFT_Y_COMP_8814B)
+#define BITS_Y_COMP_8814B (BIT_MASK_Y_COMP_8814B << BIT_SHIFT_Y_COMP_8814B)
+#define BIT_CLEAR_Y_COMP_8814B(x) ((x) & (~BITS_Y_COMP_8814B))
+#define BIT_GET_Y_COMP_8814B(x)                                                \
+	(((x) >> BIT_SHIFT_Y_COMP_8814B) & BIT_MASK_Y_COMP_8814B)
+#define BIT_SET_Y_COMP_8814B(x, v)                                             \
+	(BIT_CLEAR_Y_COMP_8814B(x) | BIT_Y_COMP_8814B(v))
+
+#define BIT_X_COMP_Y_OVERFLOW_8814B BIT(3)
+
+#define BIT_SHIFT_X_COMP_8814B 0
+#define BIT_MASK_X_COMP_8814B 0x7
+#define BIT_X_COMP_8814B(x)                                                    \
+	(((x) & BIT_MASK_X_COMP_8814B) << BIT_SHIFT_X_COMP_8814B)
+#define BITS_X_COMP_8814B (BIT_MASK_X_COMP_8814B << BIT_SHIFT_X_COMP_8814B)
+#define BIT_CLEAR_X_COMP_8814B(x) ((x) & (~BITS_X_COMP_8814B))
+#define BIT_GET_X_COMP_8814B(x)                                                \
+	(((x) >> BIT_SHIFT_X_COMP_8814B) & BIT_MASK_X_COMP_8814B)
+#define BIT_SET_X_COMP_8814B(x, v)                                             \
+	(BIT_CLEAR_X_COMP_8814B(x) | BIT_X_COMP_8814B(v))
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_TIMER_COMPARE_VALUE_LOW_8814B */
+
+#define BIT_SHIFT_COMP_VALUE_LOW_8814B 0
+#define BIT_MASK_COMP_VALUE_LOW_8814B 0xffffffffL
+#define BIT_COMP_VALUE_LOW_8814B(x)                                            \
+	(((x) & BIT_MASK_COMP_VALUE_LOW_8814B)                                 \
+	 << BIT_SHIFT_COMP_VALUE_LOW_8814B)
+#define BITS_COMP_VALUE_LOW_8814B                                              \
+	(BIT_MASK_COMP_VALUE_LOW_8814B << BIT_SHIFT_COMP_VALUE_LOW_8814B)
+#define BIT_CLEAR_COMP_VALUE_LOW_8814B(x) ((x) & (~BITS_COMP_VALUE_LOW_8814B))
+#define BIT_GET_COMP_VALUE_LOW_8814B(x)                                        \
+	(((x) >> BIT_SHIFT_COMP_VALUE_LOW_8814B) &                             \
+	 BIT_MASK_COMP_VALUE_LOW_8814B)
+#define BIT_SET_COMP_VALUE_LOW_8814B(x, v)                                     \
+	(BIT_CLEAR_COMP_VALUE_LOW_8814B(x) | BIT_COMP_VALUE_LOW_8814B(v))
+
+/* 2 REG_TIMER_COMPARE_VALUE_HIGH_8814B */
+
+#define BIT_SHIFT_COMP_VALUE_HIGH_8814B 0
+#define BIT_MASK_COMP_VALUE_HIGH_8814B 0xffffffffL
+#define BIT_COMP_VALUE_HIGH_8814B(x)                                           \
+	(((x) & BIT_MASK_COMP_VALUE_HIGH_8814B)                                \
+	 << BIT_SHIFT_COMP_VALUE_HIGH_8814B)
+#define BITS_COMP_VALUE_HIGH_8814B                                             \
+	(BIT_MASK_COMP_VALUE_HIGH_8814B << BIT_SHIFT_COMP_VALUE_HIGH_8814B)
+#define BIT_CLEAR_COMP_VALUE_HIGH_8814B(x) ((x) & (~BITS_COMP_VALUE_HIGH_8814B))
+#define BIT_GET_COMP_VALUE_HIGH_8814B(x)                                       \
+	(((x) >> BIT_SHIFT_COMP_VALUE_HIGH_8814B) &                            \
+	 BIT_MASK_COMP_VALUE_HIGH_8814B)
+#define BIT_SET_COMP_VALUE_HIGH_8814B(x, v)                                    \
+	(BIT_CLEAR_COMP_VALUE_HIGH_8814B(x) | BIT_COMP_VALUE_HIGH_8814B(v))
+
+/* 2 REG_RSVD_8814B */
+
+/* 2 REG_SCHEDULER_COUNTER_8814B */
+
+#define BIT_SHIFT__SCHEDULER_COUNTER_8814B 16
+#define BIT_MASK__SCHEDULER_COUNTER_8814B 0xffff
+#define BIT__SCHEDULER_COUNTER_8814B(x)                                        \
+	(((x) & BIT_MASK__SCHEDULER_COUNTER_8814B)                             \
+	 << BIT_SHIFT__SCHEDULER_COUNTER_8814B)
+#define BITS__SCHEDULER_COUNTER_8814B                                          \
+	(BIT_MASK__SCHEDULER_COUNTER_8814B                                     \
+	 << BIT_SHIFT__SCHEDULER_COUNTER_8814B)
+#define BIT_CLEAR__SCHEDULER_COUNTER_8814B(x)                                  \
+	((x) & (~BITS__SCHEDULER_COUNTER_8814B))
+#define BIT_GET__SCHEDULER_COUNTER_8814B(x)                                    \
+	(((x) >> BIT_SHIFT__SCHEDULER_COUNTER_8814B) &                         \
+	 BIT_MASK__SCHEDULER_COUNTER_8814B)
+#define BIT_SET__SCHEDULER_COUNTER_8814B(x, v)                                 \
+	(BIT_CLEAR__SCHEDULER_COUNTER_8814B(x) |                               \
+	 BIT__SCHEDULER_COUNTER_8814B(v))
+
+#define BIT__SCHEDULER_COUNTER_RST_8814B BIT(8)
+
+#define BIT_SHIFT_SCHEDULER_COUNTER_SEL_8814B 0
+#define BIT_MASK_SCHEDULER_COUNTER_SEL_8814B 0xff
+#define BIT_SCHEDULER_COUNTER_SEL_8814B(x)                                     \
+	(((x) & BIT_MASK_SCHEDULER_COUNTER_SEL_8814B)                          \
+	 << BIT_SHIFT_SCHEDULER_COUNTER_SEL_8814B)
+#define BITS_SCHEDULER_COUNTER_SEL_8814B                                       \
+	(BIT_MASK_SCHEDULER_COUNTER_SEL_8814B                                  \
+	 << BIT_SHIFT_SCHEDULER_COUNTER_SEL_8814B)
+#define BIT_CLEAR_SCHEDULER_COUNTER_SEL_8814B(x)                               \
+	((x) & (~BITS_SCHEDULER_COUNTER_SEL_8814B))
+#define BIT_GET_SCHEDULER_COUNTER_SEL_8814B(x)                                 \
+	(((x) >> BIT_SHIFT_SCHEDULER_COUNTER_SEL_8814B) &                      \
+	 BIT_MASK_SCHEDULER_COUNTER_SEL_8814B)
+#define BIT_SET_SCHEDULER_COUNTER_SEL_8814B(x, v)                              \
+	(BIT_CLEAR_SCHEDULER_COUNTER_SEL_8814B(x) |                            \
+	 BIT_SCHEDULER_COUNTER_SEL_8814B(v))
+
+/* 2 REG_RSVD_8814B */
+
+/* 2 REG_RSVD_8814B */
+
+/* 2 REG_RSVD_8814B */
+
+/* 2 REG_RSVD_8814B */
+
+/* 2 REG_RSVD_8814B */
+
+/* 2 REG_RSVD_8814B */
+
+/* 2 REG_RSVD_8814B */
+
+/* 2 REG_RSVD_8814B */
+
+/* 2 REG_RSVD_8814B */
+
+/* 2 REG_RSVD_8814B */
+
+/* 2 REG_RSVD_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_WMAC_CR_8814B (WMAC CR AND APSD CONTROL REGISTER) */
+#define BIT_IC_MACPHY_M_8814B BIT(0)
+
+/* 2 REG_WMAC_FWPKT_CR_8814B */
+#define BIT_FWEN_8814B BIT(7)
+#define BIT_PHYSTS_PKT_CTRL_8814B BIT(6)
+#define BIT_FWFULL_TO_RXFF_EN_8814B BIT(5)
+#define BIT_APPHDR_MIDSRCH_FAIL_8814B BIT(4)
+#define BIT_FWPARSING_EN_8814B BIT(3)
+
+#define BIT_SHIFT_APPEND_MHDR_LEN_8814B 0
+#define BIT_MASK_APPEND_MHDR_LEN_8814B 0x7
+#define BIT_APPEND_MHDR_LEN_8814B(x)                                           \
+	(((x) & BIT_MASK_APPEND_MHDR_LEN_8814B)                                \
+	 << BIT_SHIFT_APPEND_MHDR_LEN_8814B)
+#define BITS_APPEND_MHDR_LEN_8814B                                             \
+	(BIT_MASK_APPEND_MHDR_LEN_8814B << BIT_SHIFT_APPEND_MHDR_LEN_8814B)
+#define BIT_CLEAR_APPEND_MHDR_LEN_8814B(x) ((x) & (~BITS_APPEND_MHDR_LEN_8814B))
+#define BIT_GET_APPEND_MHDR_LEN_8814B(x)                                       \
+	(((x) >> BIT_SHIFT_APPEND_MHDR_LEN_8814B) &                            \
+	 BIT_MASK_APPEND_MHDR_LEN_8814B)
+#define BIT_SET_APPEND_MHDR_LEN_8814B(x, v)                                    \
+	(BIT_CLEAR_APPEND_MHDR_LEN_8814B(x) | BIT_APPEND_MHDR_LEN_8814B(v))
+
+/* 2 REG_FW_STS_FILTER_8814B */
+#define BIT_DATA_FW_STS_FILTER_8814B BIT(2)
+#define BIT_CTRL_FW_STS_FILTER_8814B BIT(1)
+#define BIT_MGNT_FW_STS_FILTER_8814B BIT(0)
+
+/* 2 REG_RSVD_8814B */
+
+/* 2 REG_TCR_8814B (TRANSMISSION CONFIGURATION REGISTER) */
+#define BIT_WMAC_EN_RTS_ADDR_8814B BIT(31)
+#define BIT_WMAC_DISABLE_CCK_8814B BIT(30)
+#define BIT_WMAC_RAW_LEN_8814B BIT(29)
+#define BIT_WMAC_NOTX_IN_RXNDP_8814B BIT(28)
+#define BIT_WMAC_EN_EOF_8814B BIT(27)
+#define BIT_WMAC_BF_SEL_8814B BIT(26)
+#define BIT_WMAC_TCRPWRMGT_HWCTL_EN_8814B BIT(24)
+#define BIT_WMAC_SMOOTH_VAL_8814B BIT(23)
+#define BIT_WMAC_EN_SCRAM_INC_8814B BIT(22)
+#define BIT_UNDERFLOWEN_CMPLEN_SEL_8814B BIT(21)
+#define BIT_FETCH_MPDU_AFTER_WSEC_RDY_8814B BIT(20)
+#define BIT_WMAC_TCR_EN_20MST_8814B BIT(19)
+#define BIT_WMAC_DIS_SIGTA_8814B BIT(18)
+#define BIT_WMAC_DIS_A2B0_8814B BIT(17)
+#define BIT_WMAC_MSK_SIGBCRC_8814B BIT(16)
+#define BIT_WMAC_TCR_ERRSTEN_3_8814B BIT(15)
+#define BIT_WMAC_TCR_ERRSTEN_2_8814B BIT(14)
+#define BIT_WMAC_TCR_ERRSTEN_1_8814B BIT(13)
+#define BIT_WMAC_TCR_ERRSTEN_0_8814B BIT(12)
+#define BIT_WMAC_TCR_TXSK_PERPKT_8814B BIT(11)
+#define BIT_ICV_8814B BIT(10)
+#define BIT_CRC_8814B BIT(8)
+#define BIT_WMAC_TCRPWRMGT_HWDATA_EN_8814B BIT(7)
+#define BIT_PWR_ST_8814B BIT(6)
+#define BIT_WMAC_TCR_UPD_TIMIE_8814B BIT(5)
+#define BIT_WMAC_TCR_UPD_HGQMD_8814B BIT(4)
+#define BIT_VHTSIGA1_TXPS_8814B BIT(3)
+#define BIT_PAD_SEL_8814B BIT(2)
+#define BIT_DIS_GCLK_8814B BIT(1)
+#define BIT_WMAC_TCRPWRMGT_HWACT_EN_8814B BIT(0)
+
+/* 2 REG_RCR_8814B (RECEIVE CONFIGURATION REGISTER) */
+#define BIT_APP_FCS_8814B BIT(31)
+#define BIT_APP_MIC_8814B BIT(30)
+#define BIT_APP_ICV_8814B BIT(29)
+#define BIT_APP_PHYSTS_8814B BIT(28)
+#define BIT_APP_BASSN_8814B BIT(27)
+#define BIT_VHT_DACK_8814B BIT(26)
+#define BIT_TCPOFLD_EN_8814B BIT(25)
+#define BIT_ENADDRCAM_8814B BIT(24)
+#define BIT_LSIGEN_8814B BIT(23)
+#define BIT_MFBEN_8814B BIT(22)
+#define BIT_DISCHKPPDLLEN_8814B BIT(21)
+#define BIT_PKTCTL_DLEN_8814B BIT(20)
+#define BIT_DISGCLK_8814B BIT(19)
+#define BIT_TIM_PARSER_EN_8814B BIT(18)
+#define BIT_BC_MD_EN_8814B BIT(17)
+#define BIT_UC_MD_EN_8814B BIT(16)
+#define BIT_RXSK_PERPKT_8814B BIT(15)
+#define BIT_HTC_LOC_CTRL_8814B BIT(14)
+#define BIT_ACK_WITH_CBSSID_DATA_OPTION_8814B BIT(13)
+#define BIT_RPFM_CAM_ENABLE_8814B BIT(12)
+#define BIT_TA_BCN_8814B BIT(11)
+#define BIT_DISDECMYPKT_8814B BIT(10)
+#define BIT_AICV_8814B BIT(9)
+#define BIT_ACRC32_8814B BIT(8)
+#define BIT_CBSSID_BCN_8814B BIT(7)
+#define BIT_CBSSID_DATA_8814B BIT(6)
+#define BIT_APWRMGT_8814B BIT(5)
+#define BIT_ADD3_8814B BIT(4)
+#define BIT_AB_8814B BIT(3)
+#define BIT_AM_8814B BIT(2)
+#define BIT_APM_8814B BIT(1)
+#define BIT_AAP_8814B BIT(0)
+
+/* 2 REG_RX_PKT_LIMIT_8814B (RX PACKET LENGTH LIMIT REGISTER) */
+
+#define BIT_SHIFT_RXPKTLMT_8814B 0
+#define BIT_MASK_RXPKTLMT_8814B 0x3f
+#define BIT_RXPKTLMT_8814B(x)                                                  \
+	(((x) & BIT_MASK_RXPKTLMT_8814B) << BIT_SHIFT_RXPKTLMT_8814B)
+#define BITS_RXPKTLMT_8814B                                                    \
+	(BIT_MASK_RXPKTLMT_8814B << BIT_SHIFT_RXPKTLMT_8814B)
+#define BIT_CLEAR_RXPKTLMT_8814B(x) ((x) & (~BITS_RXPKTLMT_8814B))
+#define BIT_GET_RXPKTLMT_8814B(x)                                              \
+	(((x) >> BIT_SHIFT_RXPKTLMT_8814B) & BIT_MASK_RXPKTLMT_8814B)
+#define BIT_SET_RXPKTLMT_8814B(x, v)                                           \
+	(BIT_CLEAR_RXPKTLMT_8814B(x) | BIT_RXPKTLMT_8814B(v))
+
+/* 2 REG_RX_DLK_TIME_8814B (RX DEADLOCK TIME REGISTER) */
+
+#define BIT_SHIFT_RX_DLK_TIME_8814B 0
+#define BIT_MASK_RX_DLK_TIME_8814B 0xff
+#define BIT_RX_DLK_TIME_8814B(x)                                               \
+	(((x) & BIT_MASK_RX_DLK_TIME_8814B) << BIT_SHIFT_RX_DLK_TIME_8814B)
+#define BITS_RX_DLK_TIME_8814B                                                 \
+	(BIT_MASK_RX_DLK_TIME_8814B << BIT_SHIFT_RX_DLK_TIME_8814B)
+#define BIT_CLEAR_RX_DLK_TIME_8814B(x) ((x) & (~BITS_RX_DLK_TIME_8814B))
+#define BIT_GET_RX_DLK_TIME_8814B(x)                                           \
+	(((x) >> BIT_SHIFT_RX_DLK_TIME_8814B) & BIT_MASK_RX_DLK_TIME_8814B)
+#define BIT_SET_RX_DLK_TIME_8814B(x, v)                                        \
+	(BIT_CLEAR_RX_DLK_TIME_8814B(x) | BIT_RX_DLK_TIME_8814B(v))
+
+/* 2 REG_RSVD_8814B */
+
+/* 2 REG_RX_DRVINFO_SZ_8814B (RX DRIVER INFO SIZE REGISTER) */
+#define BIT_PHYSTS_PER_PKT_MODE_8814B BIT(7)
+
+#define BIT_SHIFT_DRVINFO_SZ_V1_8814B 0
+#define BIT_MASK_DRVINFO_SZ_V1_8814B 0xf
+#define BIT_DRVINFO_SZ_V1_8814B(x)                                             \
+	(((x) & BIT_MASK_DRVINFO_SZ_V1_8814B) << BIT_SHIFT_DRVINFO_SZ_V1_8814B)
+#define BITS_DRVINFO_SZ_V1_8814B                                               \
+	(BIT_MASK_DRVINFO_SZ_V1_8814B << BIT_SHIFT_DRVINFO_SZ_V1_8814B)
+#define BIT_CLEAR_DRVINFO_SZ_V1_8814B(x) ((x) & (~BITS_DRVINFO_SZ_V1_8814B))
+#define BIT_GET_DRVINFO_SZ_V1_8814B(x)                                         \
+	(((x) >> BIT_SHIFT_DRVINFO_SZ_V1_8814B) & BIT_MASK_DRVINFO_SZ_V1_8814B)
+#define BIT_SET_DRVINFO_SZ_V1_8814B(x, v)                                      \
+	(BIT_CLEAR_DRVINFO_SZ_V1_8814B(x) | BIT_DRVINFO_SZ_V1_8814B(v))
+
+/* 2 REG_MACID_8814B	(MAC ID REGISTER) */
+
+#define BIT_SHIFT_MACID_V1_8814B 0
+#define BIT_MASK_MACID_V1_8814B 0xffffffffL
+#define BIT_MACID_V1_8814B(x)                                                  \
+	(((x) & BIT_MASK_MACID_V1_8814B) << BIT_SHIFT_MACID_V1_8814B)
+#define BITS_MACID_V1_8814B                                                    \
+	(BIT_MASK_MACID_V1_8814B << BIT_SHIFT_MACID_V1_8814B)
+#define BIT_CLEAR_MACID_V1_8814B(x) ((x) & (~BITS_MACID_V1_8814B))
+#define BIT_GET_MACID_V1_8814B(x)                                              \
+	(((x) >> BIT_SHIFT_MACID_V1_8814B) & BIT_MASK_MACID_V1_8814B)
+#define BIT_SET_MACID_V1_8814B(x, v)                                           \
+	(BIT_CLEAR_MACID_V1_8814B(x) | BIT_MACID_V1_8814B(v))
+
+/* 2 REG_MACID_H_8814B	(MAC ID REGISTER) */
+
+#define BIT_SHIFT_MACID_H_V1_8814B 0
+#define BIT_MASK_MACID_H_V1_8814B 0xffff
+#define BIT_MACID_H_V1_8814B(x)                                                \
+	(((x) & BIT_MASK_MACID_H_V1_8814B) << BIT_SHIFT_MACID_H_V1_8814B)
+#define BITS_MACID_H_V1_8814B                                                  \
+	(BIT_MASK_MACID_H_V1_8814B << BIT_SHIFT_MACID_H_V1_8814B)
+#define BIT_CLEAR_MACID_H_V1_8814B(x) ((x) & (~BITS_MACID_H_V1_8814B))
+#define BIT_GET_MACID_H_V1_8814B(x)                                            \
+	(((x) >> BIT_SHIFT_MACID_H_V1_8814B) & BIT_MASK_MACID_H_V1_8814B)
+#define BIT_SET_MACID_H_V1_8814B(x, v)                                         \
+	(BIT_CLEAR_MACID_H_V1_8814B(x) | BIT_MACID_H_V1_8814B(v))
+
+/* 2 REG_BSSID_8814B (BSSID REGISTER) */
+
+#define BIT_SHIFT_BSSID_V1_8814B 0
+#define BIT_MASK_BSSID_V1_8814B 0xffffffffL
+#define BIT_BSSID_V1_8814B(x)                                                  \
+	(((x) & BIT_MASK_BSSID_V1_8814B) << BIT_SHIFT_BSSID_V1_8814B)
+#define BITS_BSSID_V1_8814B                                                    \
+	(BIT_MASK_BSSID_V1_8814B << BIT_SHIFT_BSSID_V1_8814B)
+#define BIT_CLEAR_BSSID_V1_8814B(x) ((x) & (~BITS_BSSID_V1_8814B))
+#define BIT_GET_BSSID_V1_8814B(x)                                              \
+	(((x) >> BIT_SHIFT_BSSID_V1_8814B) & BIT_MASK_BSSID_V1_8814B)
+#define BIT_SET_BSSID_V1_8814B(x, v)                                           \
+	(BIT_CLEAR_BSSID_V1_8814B(x) | BIT_BSSID_V1_8814B(v))
+
+/* 2 REG_BSSID_H_8814B	(BSSID REGISTER) */
+
+/* 2 REG_NOT_VALID_8814B */
+
+#define BIT_SHIFT_BSSID_H_V1_8814B 0
+#define BIT_MASK_BSSID_H_V1_8814B 0xffff
+#define BIT_BSSID_H_V1_8814B(x)                                                \
+	(((x) & BIT_MASK_BSSID_H_V1_8814B) << BIT_SHIFT_BSSID_H_V1_8814B)
+#define BITS_BSSID_H_V1_8814B                                                  \
+	(BIT_MASK_BSSID_H_V1_8814B << BIT_SHIFT_BSSID_H_V1_8814B)
+#define BIT_CLEAR_BSSID_H_V1_8814B(x) ((x) & (~BITS_BSSID_H_V1_8814B))
+#define BIT_GET_BSSID_H_V1_8814B(x)                                            \
+	(((x) >> BIT_SHIFT_BSSID_H_V1_8814B) & BIT_MASK_BSSID_H_V1_8814B)
+#define BIT_SET_BSSID_H_V1_8814B(x, v)                                         \
+	(BIT_CLEAR_BSSID_H_V1_8814B(x) | BIT_BSSID_H_V1_8814B(v))
+
+/* 2 REG_MAR_8814B (MULTICAST ADDRESS REGISTER) */
+
+#define BIT_SHIFT_MAR_V1_8814B 0
+#define BIT_MASK_MAR_V1_8814B 0xffffffffL
+#define BIT_MAR_V1_8814B(x)                                                    \
+	(((x) & BIT_MASK_MAR_V1_8814B) << BIT_SHIFT_MAR_V1_8814B)
+#define BITS_MAR_V1_8814B (BIT_MASK_MAR_V1_8814B << BIT_SHIFT_MAR_V1_8814B)
+#define BIT_CLEAR_MAR_V1_8814B(x) ((x) & (~BITS_MAR_V1_8814B))
+#define BIT_GET_MAR_V1_8814B(x)                                                \
+	(((x) >> BIT_SHIFT_MAR_V1_8814B) & BIT_MASK_MAR_V1_8814B)
+#define BIT_SET_MAR_V1_8814B(x, v)                                             \
+	(BIT_CLEAR_MAR_V1_8814B(x) | BIT_MAR_V1_8814B(v))
+
+/* 2 REG_MAR_H_8814B (MULTICAST ADDRESS REGISTER) */
+
+#define BIT_SHIFT_MAR_H_V1_8814B 0
+#define BIT_MASK_MAR_H_V1_8814B 0xffffffffL
+#define BIT_MAR_H_V1_8814B(x)                                                  \
+	(((x) & BIT_MASK_MAR_H_V1_8814B) << BIT_SHIFT_MAR_H_V1_8814B)
+#define BITS_MAR_H_V1_8814B                                                    \
+	(BIT_MASK_MAR_H_V1_8814B << BIT_SHIFT_MAR_H_V1_8814B)
+#define BIT_CLEAR_MAR_H_V1_8814B(x) ((x) & (~BITS_MAR_H_V1_8814B))
+#define BIT_GET_MAR_H_V1_8814B(x)                                              \
+	(((x) >> BIT_SHIFT_MAR_H_V1_8814B) & BIT_MASK_MAR_H_V1_8814B)
+#define BIT_SET_MAR_H_V1_8814B(x, v)                                           \
+	(BIT_CLEAR_MAR_H_V1_8814B(x) | BIT_MAR_H_V1_8814B(v))
+
+/* 2 REG_RSVD_8814B */
+
+/* 2 REG_WMAC_DEBUG_SEL_8814B */
+
+#define BIT_SHIFT_WMAC_ARB_DBG_SEL_8814B 3
+#define BIT_MASK_WMAC_ARB_DBG_SEL_8814B 0x3
+#define BIT_WMAC_ARB_DBG_SEL_8814B(x)                                          \
+	(((x) & BIT_MASK_WMAC_ARB_DBG_SEL_8814B)                               \
+	 << BIT_SHIFT_WMAC_ARB_DBG_SEL_8814B)
+#define BITS_WMAC_ARB_DBG_SEL_8814B                                            \
+	(BIT_MASK_WMAC_ARB_DBG_SEL_8814B << BIT_SHIFT_WMAC_ARB_DBG_SEL_8814B)
+#define BIT_CLEAR_WMAC_ARB_DBG_SEL_8814B(x)                                    \
+	((x) & (~BITS_WMAC_ARB_DBG_SEL_8814B))
+#define BIT_GET_WMAC_ARB_DBG_SEL_8814B(x)                                      \
+	(((x) >> BIT_SHIFT_WMAC_ARB_DBG_SEL_8814B) &                           \
+	 BIT_MASK_WMAC_ARB_DBG_SEL_8814B)
+#define BIT_SET_WMAC_ARB_DBG_SEL_8814B(x, v)                                   \
+	(BIT_CLEAR_WMAC_ARB_DBG_SEL_8814B(x) | BIT_WMAC_ARB_DBG_SEL_8814B(v))
+
+#define BIT_WMAC_EXT_DBG_SEL_8814B BIT(2)
+
+#define BIT_SHIFT_WMAC_MU_DBGSEL_V1_8814B 0
+#define BIT_MASK_WMAC_MU_DBGSEL_V1_8814B 0x3
+#define BIT_WMAC_MU_DBGSEL_V1_8814B(x)                                         \
+	(((x) & BIT_MASK_WMAC_MU_DBGSEL_V1_8814B)                              \
+	 << BIT_SHIFT_WMAC_MU_DBGSEL_V1_8814B)
+#define BITS_WMAC_MU_DBGSEL_V1_8814B                                           \
+	(BIT_MASK_WMAC_MU_DBGSEL_V1_8814B << BIT_SHIFT_WMAC_MU_DBGSEL_V1_8814B)
+#define BIT_CLEAR_WMAC_MU_DBGSEL_V1_8814B(x)                                   \
+	((x) & (~BITS_WMAC_MU_DBGSEL_V1_8814B))
+#define BIT_GET_WMAC_MU_DBGSEL_V1_8814B(x)                                     \
+	(((x) >> BIT_SHIFT_WMAC_MU_DBGSEL_V1_8814B) &                          \
+	 BIT_MASK_WMAC_MU_DBGSEL_V1_8814B)
+#define BIT_SET_WMAC_MU_DBGSEL_V1_8814B(x, v)                                  \
+	(BIT_CLEAR_WMAC_MU_DBGSEL_V1_8814B(x) | BIT_WMAC_MU_DBGSEL_V1_8814B(v))
+
+/* 2 REG_WMAC_TCR_TSFT_OFS_8814B */
+
+#define BIT_SHIFT_WMAC_TCR_TSFT_OFS_8814B 0
+#define BIT_MASK_WMAC_TCR_TSFT_OFS_8814B 0xffff
+#define BIT_WMAC_TCR_TSFT_OFS_8814B(x)                                         \
+	(((x) & BIT_MASK_WMAC_TCR_TSFT_OFS_8814B)                              \
+	 << BIT_SHIFT_WMAC_TCR_TSFT_OFS_8814B)
+#define BITS_WMAC_TCR_TSFT_OFS_8814B                                           \
+	(BIT_MASK_WMAC_TCR_TSFT_OFS_8814B << BIT_SHIFT_WMAC_TCR_TSFT_OFS_8814B)
+#define BIT_CLEAR_WMAC_TCR_TSFT_OFS_8814B(x)                                   \
+	((x) & (~BITS_WMAC_TCR_TSFT_OFS_8814B))
+#define BIT_GET_WMAC_TCR_TSFT_OFS_8814B(x)                                     \
+	(((x) >> BIT_SHIFT_WMAC_TCR_TSFT_OFS_8814B) &                          \
+	 BIT_MASK_WMAC_TCR_TSFT_OFS_8814B)
+#define BIT_SET_WMAC_TCR_TSFT_OFS_8814B(x, v)                                  \
+	(BIT_CLEAR_WMAC_TCR_TSFT_OFS_8814B(x) | BIT_WMAC_TCR_TSFT_OFS_8814B(v))
+
+/* 2 REG_UDF_THSD_8814B */
+#define BIT_UDF_THSD_V1_8814B BIT(7)
+
+#define BIT_SHIFT_UDF_THSD_VALUE_8814B 0
+#define BIT_MASK_UDF_THSD_VALUE_8814B 0x7f
+#define BIT_UDF_THSD_VALUE_8814B(x)                                            \
+	(((x) & BIT_MASK_UDF_THSD_VALUE_8814B)                                 \
+	 << BIT_SHIFT_UDF_THSD_VALUE_8814B)
+#define BITS_UDF_THSD_VALUE_8814B                                              \
+	(BIT_MASK_UDF_THSD_VALUE_8814B << BIT_SHIFT_UDF_THSD_VALUE_8814B)
+#define BIT_CLEAR_UDF_THSD_VALUE_8814B(x) ((x) & (~BITS_UDF_THSD_VALUE_8814B))
+#define BIT_GET_UDF_THSD_VALUE_8814B(x)                                        \
+	(((x) >> BIT_SHIFT_UDF_THSD_VALUE_8814B) &                             \
+	 BIT_MASK_UDF_THSD_VALUE_8814B)
+#define BIT_SET_UDF_THSD_VALUE_8814B(x, v)                                     \
+	(BIT_CLEAR_UDF_THSD_VALUE_8814B(x) | BIT_UDF_THSD_VALUE_8814B(v))
+
+/* 2 REG_ZLD_NUM_8814B */
+
+#define BIT_SHIFT_ZLD_NUM_8814B 0
+#define BIT_MASK_ZLD_NUM_8814B 0xff
+#define BIT_ZLD_NUM_8814B(x)                                                   \
+	(((x) & BIT_MASK_ZLD_NUM_8814B) << BIT_SHIFT_ZLD_NUM_8814B)
+#define BITS_ZLD_NUM_8814B (BIT_MASK_ZLD_NUM_8814B << BIT_SHIFT_ZLD_NUM_8814B)
+#define BIT_CLEAR_ZLD_NUM_8814B(x) ((x) & (~BITS_ZLD_NUM_8814B))
+#define BIT_GET_ZLD_NUM_8814B(x)                                               \
+	(((x) >> BIT_SHIFT_ZLD_NUM_8814B) & BIT_MASK_ZLD_NUM_8814B)
+#define BIT_SET_ZLD_NUM_8814B(x, v)                                            \
+	(BIT_CLEAR_ZLD_NUM_8814B(x) | BIT_ZLD_NUM_8814B(v))
+
+/* 2 REG_STMP_THSD_8814B */
+
+#define BIT_SHIFT_STMP_THSD_8814B 0
+#define BIT_MASK_STMP_THSD_8814B 0xff
+#define BIT_STMP_THSD_8814B(x)                                                 \
+	(((x) & BIT_MASK_STMP_THSD_8814B) << BIT_SHIFT_STMP_THSD_8814B)
+#define BITS_STMP_THSD_8814B                                                   \
+	(BIT_MASK_STMP_THSD_8814B << BIT_SHIFT_STMP_THSD_8814B)
+#define BIT_CLEAR_STMP_THSD_8814B(x) ((x) & (~BITS_STMP_THSD_8814B))
+#define BIT_GET_STMP_THSD_8814B(x)                                             \
+	(((x) >> BIT_SHIFT_STMP_THSD_8814B) & BIT_MASK_STMP_THSD_8814B)
+#define BIT_SET_STMP_THSD_8814B(x, v)                                          \
+	(BIT_CLEAR_STMP_THSD_8814B(x) | BIT_STMP_THSD_8814B(v))
+
+/* 2 REG_WMAC_TXTIMEOUT_8814B */
+
+#define BIT_SHIFT_WMAC_TXTIMEOUT_8814B 0
+#define BIT_MASK_WMAC_TXTIMEOUT_8814B 0xff
+#define BIT_WMAC_TXTIMEOUT_8814B(x)                                            \
+	(((x) & BIT_MASK_WMAC_TXTIMEOUT_8814B)                                 \
+	 << BIT_SHIFT_WMAC_TXTIMEOUT_8814B)
+#define BITS_WMAC_TXTIMEOUT_8814B                                              \
+	(BIT_MASK_WMAC_TXTIMEOUT_8814B << BIT_SHIFT_WMAC_TXTIMEOUT_8814B)
+#define BIT_CLEAR_WMAC_TXTIMEOUT_8814B(x) ((x) & (~BITS_WMAC_TXTIMEOUT_8814B))
+#define BIT_GET_WMAC_TXTIMEOUT_8814B(x)                                        \
+	(((x) >> BIT_SHIFT_WMAC_TXTIMEOUT_8814B) &                             \
+	 BIT_MASK_WMAC_TXTIMEOUT_8814B)
+#define BIT_SET_WMAC_TXTIMEOUT_8814B(x, v)                                     \
+	(BIT_CLEAR_WMAC_TXTIMEOUT_8814B(x) | BIT_WMAC_TXTIMEOUT_8814B(v))
+
+/* 2 REG_MCU_TEST_2_V1_8814B */
+
+#define BIT_SHIFT_MCU_RSVD_2_V1_8814B 0
+#define BIT_MASK_MCU_RSVD_2_V1_8814B 0xffff
+#define BIT_MCU_RSVD_2_V1_8814B(x)                                             \
+	(((x) & BIT_MASK_MCU_RSVD_2_V1_8814B) << BIT_SHIFT_MCU_RSVD_2_V1_8814B)
+#define BITS_MCU_RSVD_2_V1_8814B                                               \
+	(BIT_MASK_MCU_RSVD_2_V1_8814B << BIT_SHIFT_MCU_RSVD_2_V1_8814B)
+#define BIT_CLEAR_MCU_RSVD_2_V1_8814B(x) ((x) & (~BITS_MCU_RSVD_2_V1_8814B))
+#define BIT_GET_MCU_RSVD_2_V1_8814B(x)                                         \
+	(((x) >> BIT_SHIFT_MCU_RSVD_2_V1_8814B) & BIT_MASK_MCU_RSVD_2_V1_8814B)
+#define BIT_SET_MCU_RSVD_2_V1_8814B(x, v)                                      \
+	(BIT_CLEAR_MCU_RSVD_2_V1_8814B(x) | BIT_MCU_RSVD_2_V1_8814B(v))
+
+/* 2 REG_USTIME_EDCA_8814B (US TIME TUNING FOR EDCA REGISTER) */
+
+#define BIT_SHIFT_USTIME_EDCA_8814B 0
+#define BIT_MASK_USTIME_EDCA_8814B 0xff
+#define BIT_USTIME_EDCA_8814B(x)                                               \
+	(((x) & BIT_MASK_USTIME_EDCA_8814B) << BIT_SHIFT_USTIME_EDCA_8814B)
+#define BITS_USTIME_EDCA_8814B                                                 \
+	(BIT_MASK_USTIME_EDCA_8814B << BIT_SHIFT_USTIME_EDCA_8814B)
+#define BIT_CLEAR_USTIME_EDCA_8814B(x) ((x) & (~BITS_USTIME_EDCA_8814B))
+#define BIT_GET_USTIME_EDCA_8814B(x)                                           \
+	(((x) >> BIT_SHIFT_USTIME_EDCA_8814B) & BIT_MASK_USTIME_EDCA_8814B)
+#define BIT_SET_USTIME_EDCA_8814B(x, v)                                        \
+	(BIT_CLEAR_USTIME_EDCA_8814B(x) | BIT_USTIME_EDCA_8814B(v))
+
+/* 2 REG_ACKTO_CCK_8814B (ACK TIMEOUT REGISTER FOR CCK RATE) */
+
+#define BIT_SHIFT_ACKTO_CCK_8814B 0
+#define BIT_MASK_ACKTO_CCK_8814B 0xff
+#define BIT_ACKTO_CCK_8814B(x)                                                 \
+	(((x) & BIT_MASK_ACKTO_CCK_8814B) << BIT_SHIFT_ACKTO_CCK_8814B)
+#define BITS_ACKTO_CCK_8814B                                                   \
+	(BIT_MASK_ACKTO_CCK_8814B << BIT_SHIFT_ACKTO_CCK_8814B)
+#define BIT_CLEAR_ACKTO_CCK_8814B(x) ((x) & (~BITS_ACKTO_CCK_8814B))
+#define BIT_GET_ACKTO_CCK_8814B(x)                                             \
+	(((x) >> BIT_SHIFT_ACKTO_CCK_8814B) & BIT_MASK_ACKTO_CCK_8814B)
+#define BIT_SET_ACKTO_CCK_8814B(x, v)                                          \
+	(BIT_CLEAR_ACKTO_CCK_8814B(x) | BIT_ACKTO_CCK_8814B(v))
+
+/* 2 REG_MAC_SPEC_SIFS_8814B (SPECIFICATION SIFS REGISTER) */
+
+#define BIT_SHIFT_SPEC_SIFS_OFDM_8814B 8
+#define BIT_MASK_SPEC_SIFS_OFDM_8814B 0xff
+#define BIT_SPEC_SIFS_OFDM_8814B(x)                                            \
+	(((x) & BIT_MASK_SPEC_SIFS_OFDM_8814B)                                 \
+	 << BIT_SHIFT_SPEC_SIFS_OFDM_8814B)
+#define BITS_SPEC_SIFS_OFDM_8814B                                              \
+	(BIT_MASK_SPEC_SIFS_OFDM_8814B << BIT_SHIFT_SPEC_SIFS_OFDM_8814B)
+#define BIT_CLEAR_SPEC_SIFS_OFDM_8814B(x) ((x) & (~BITS_SPEC_SIFS_OFDM_8814B))
+#define BIT_GET_SPEC_SIFS_OFDM_8814B(x)                                        \
+	(((x) >> BIT_SHIFT_SPEC_SIFS_OFDM_8814B) &                             \
+	 BIT_MASK_SPEC_SIFS_OFDM_8814B)
+#define BIT_SET_SPEC_SIFS_OFDM_8814B(x, v)                                     \
+	(BIT_CLEAR_SPEC_SIFS_OFDM_8814B(x) | BIT_SPEC_SIFS_OFDM_8814B(v))
+
+#define BIT_SHIFT_SPEC_SIFS_CCK_8814B 0
+#define BIT_MASK_SPEC_SIFS_CCK_8814B 0xff
+#define BIT_SPEC_SIFS_CCK_8814B(x)                                             \
+	(((x) & BIT_MASK_SPEC_SIFS_CCK_8814B) << BIT_SHIFT_SPEC_SIFS_CCK_8814B)
+#define BITS_SPEC_SIFS_CCK_8814B                                               \
+	(BIT_MASK_SPEC_SIFS_CCK_8814B << BIT_SHIFT_SPEC_SIFS_CCK_8814B)
+#define BIT_CLEAR_SPEC_SIFS_CCK_8814B(x) ((x) & (~BITS_SPEC_SIFS_CCK_8814B))
+#define BIT_GET_SPEC_SIFS_CCK_8814B(x)                                         \
+	(((x) >> BIT_SHIFT_SPEC_SIFS_CCK_8814B) & BIT_MASK_SPEC_SIFS_CCK_8814B)
+#define BIT_SET_SPEC_SIFS_CCK_8814B(x, v)                                      \
+	(BIT_CLEAR_SPEC_SIFS_CCK_8814B(x) | BIT_SPEC_SIFS_CCK_8814B(v))
+
+/* 2 REG_RESP_SIFS_CCK_8814B (RESPONSE SIFS FOR CCK REGISTER) */
+
+#define BIT_SHIFT_SIFS_R2T_CCK_8814B 8
+#define BIT_MASK_SIFS_R2T_CCK_8814B 0xff
+#define BIT_SIFS_R2T_CCK_8814B(x)                                              \
+	(((x) & BIT_MASK_SIFS_R2T_CCK_8814B) << BIT_SHIFT_SIFS_R2T_CCK_8814B)
+#define BITS_SIFS_R2T_CCK_8814B                                                \
+	(BIT_MASK_SIFS_R2T_CCK_8814B << BIT_SHIFT_SIFS_R2T_CCK_8814B)
+#define BIT_CLEAR_SIFS_R2T_CCK_8814B(x) ((x) & (~BITS_SIFS_R2T_CCK_8814B))
+#define BIT_GET_SIFS_R2T_CCK_8814B(x)                                          \
+	(((x) >> BIT_SHIFT_SIFS_R2T_CCK_8814B) & BIT_MASK_SIFS_R2T_CCK_8814B)
+#define BIT_SET_SIFS_R2T_CCK_8814B(x, v)                                       \
+	(BIT_CLEAR_SIFS_R2T_CCK_8814B(x) | BIT_SIFS_R2T_CCK_8814B(v))
+
+#define BIT_SHIFT_SIFS_T2T_CCK_8814B 0
+#define BIT_MASK_SIFS_T2T_CCK_8814B 0xff
+#define BIT_SIFS_T2T_CCK_8814B(x)                                              \
+	(((x) & BIT_MASK_SIFS_T2T_CCK_8814B) << BIT_SHIFT_SIFS_T2T_CCK_8814B)
+#define BITS_SIFS_T2T_CCK_8814B                                                \
+	(BIT_MASK_SIFS_T2T_CCK_8814B << BIT_SHIFT_SIFS_T2T_CCK_8814B)
+#define BIT_CLEAR_SIFS_T2T_CCK_8814B(x) ((x) & (~BITS_SIFS_T2T_CCK_8814B))
+#define BIT_GET_SIFS_T2T_CCK_8814B(x)                                          \
+	(((x) >> BIT_SHIFT_SIFS_T2T_CCK_8814B) & BIT_MASK_SIFS_T2T_CCK_8814B)
+#define BIT_SET_SIFS_T2T_CCK_8814B(x, v)                                       \
+	(BIT_CLEAR_SIFS_T2T_CCK_8814B(x) | BIT_SIFS_T2T_CCK_8814B(v))
+
+/* 2 REG_RESP_SIFS_OFDM_8814B (RESPONSE SIFS FOR OFDM REGISTER) */
+
+#define BIT_SHIFT_SIFS_R2T_OFDM_8814B 8
+#define BIT_MASK_SIFS_R2T_OFDM_8814B 0xff
+#define BIT_SIFS_R2T_OFDM_8814B(x)                                             \
+	(((x) & BIT_MASK_SIFS_R2T_OFDM_8814B) << BIT_SHIFT_SIFS_R2T_OFDM_8814B)
+#define BITS_SIFS_R2T_OFDM_8814B                                               \
+	(BIT_MASK_SIFS_R2T_OFDM_8814B << BIT_SHIFT_SIFS_R2T_OFDM_8814B)
+#define BIT_CLEAR_SIFS_R2T_OFDM_8814B(x) ((x) & (~BITS_SIFS_R2T_OFDM_8814B))
+#define BIT_GET_SIFS_R2T_OFDM_8814B(x)                                         \
+	(((x) >> BIT_SHIFT_SIFS_R2T_OFDM_8814B) & BIT_MASK_SIFS_R2T_OFDM_8814B)
+#define BIT_SET_SIFS_R2T_OFDM_8814B(x, v)                                      \
+	(BIT_CLEAR_SIFS_R2T_OFDM_8814B(x) | BIT_SIFS_R2T_OFDM_8814B(v))
+
+#define BIT_SHIFT_SIFS_T2T_OFDM_8814B 0
+#define BIT_MASK_SIFS_T2T_OFDM_8814B 0xff
+#define BIT_SIFS_T2T_OFDM_8814B(x)                                             \
+	(((x) & BIT_MASK_SIFS_T2T_OFDM_8814B) << BIT_SHIFT_SIFS_T2T_OFDM_8814B)
+#define BITS_SIFS_T2T_OFDM_8814B                                               \
+	(BIT_MASK_SIFS_T2T_OFDM_8814B << BIT_SHIFT_SIFS_T2T_OFDM_8814B)
+#define BIT_CLEAR_SIFS_T2T_OFDM_8814B(x) ((x) & (~BITS_SIFS_T2T_OFDM_8814B))
+#define BIT_GET_SIFS_T2T_OFDM_8814B(x)                                         \
+	(((x) >> BIT_SHIFT_SIFS_T2T_OFDM_8814B) & BIT_MASK_SIFS_T2T_OFDM_8814B)
+#define BIT_SET_SIFS_T2T_OFDM_8814B(x, v)                                      \
+	(BIT_CLEAR_SIFS_T2T_OFDM_8814B(x) | BIT_SIFS_T2T_OFDM_8814B(v))
+
+/* 2 REG_ACKTO_8814B (ACK TIMEOUT REGISTER) */
+
+#define BIT_SHIFT_ACKTO_8814B 0
+#define BIT_MASK_ACKTO_8814B 0xff
+#define BIT_ACKTO_8814B(x)                                                     \
+	(((x) & BIT_MASK_ACKTO_8814B) << BIT_SHIFT_ACKTO_8814B)
+#define BITS_ACKTO_8814B (BIT_MASK_ACKTO_8814B << BIT_SHIFT_ACKTO_8814B)
+#define BIT_CLEAR_ACKTO_8814B(x) ((x) & (~BITS_ACKTO_8814B))
+#define BIT_GET_ACKTO_8814B(x)                                                 \
+	(((x) >> BIT_SHIFT_ACKTO_8814B) & BIT_MASK_ACKTO_8814B)
+#define BIT_SET_ACKTO_8814B(x, v)                                              \
+	(BIT_CLEAR_ACKTO_8814B(x) | BIT_ACKTO_8814B(v))
+
+/* 2 REG_CTS2TO_8814B (CTS2 TIMEOUT REGISTER) */
+
+#define BIT_SHIFT_CTS2TO_8814B 0
+#define BIT_MASK_CTS2TO_8814B 0xff
+#define BIT_CTS2TO_8814B(x)                                                    \
+	(((x) & BIT_MASK_CTS2TO_8814B) << BIT_SHIFT_CTS2TO_8814B)
+#define BITS_CTS2TO_8814B (BIT_MASK_CTS2TO_8814B << BIT_SHIFT_CTS2TO_8814B)
+#define BIT_CLEAR_CTS2TO_8814B(x) ((x) & (~BITS_CTS2TO_8814B))
+#define BIT_GET_CTS2TO_8814B(x)                                                \
+	(((x) >> BIT_SHIFT_CTS2TO_8814B) & BIT_MASK_CTS2TO_8814B)
+#define BIT_SET_CTS2TO_8814B(x, v)                                             \
+	(BIT_CLEAR_CTS2TO_8814B(x) | BIT_CTS2TO_8814B(v))
+
+/* 2 REG_EIFS_8814B (EIFS REGISTER) */
+
+#define BIT_SHIFT_EIFS_8814B 0
+#define BIT_MASK_EIFS_8814B 0xffff
+#define BIT_EIFS_8814B(x) (((x) & BIT_MASK_EIFS_8814B) << BIT_SHIFT_EIFS_8814B)
+#define BITS_EIFS_8814B (BIT_MASK_EIFS_8814B << BIT_SHIFT_EIFS_8814B)
+#define BIT_CLEAR_EIFS_8814B(x) ((x) & (~BITS_EIFS_8814B))
+#define BIT_GET_EIFS_8814B(x)                                                  \
+	(((x) >> BIT_SHIFT_EIFS_8814B) & BIT_MASK_EIFS_8814B)
+#define BIT_SET_EIFS_8814B(x, v) (BIT_CLEAR_EIFS_8814B(x) | BIT_EIFS_8814B(v))
+
+/* 2 REG_RPFM_MAP0_8814B */
+#define BIT_MGT_RPFM15EN_8814B BIT(15)
+#define BIT_MGT_RPFM14EN_8814B BIT(14)
+#define BIT_MGT_RPFM13EN_8814B BIT(13)
+#define BIT_MGT_RPFM12EN_8814B BIT(12)
+#define BIT_MGT_RPFM11EN_8814B BIT(11)
+#define BIT_MGT_RPFM10EN_8814B BIT(10)
+#define BIT_MGT_RPFM9EN_8814B BIT(9)
+#define BIT_MGT_RPFM8EN_8814B BIT(8)
+#define BIT_MGT_RPFM7EN_8814B BIT(7)
+#define BIT_MGT_RPFM6EN_8814B BIT(6)
+#define BIT_MGT_RPFM5EN_8814B BIT(5)
+#define BIT_MGT_RPFM4EN_8814B BIT(4)
+#define BIT_MGT_RPFM3EN_8814B BIT(3)
+#define BIT_MGT_RPFM2EN_8814B BIT(2)
+#define BIT_MGT_RPFM1EN_8814B BIT(1)
+#define BIT_MGT_RPFM0EN_8814B BIT(0)
+
+/* 2 REG_RPFM_MAP1_V1_8814B */
+#define BIT_DATA_RPFM15EN_8814B BIT(15)
+#define BIT_DATA_RPFM14EN_8814B BIT(14)
+#define BIT_DATA_RPFM13EN_8814B BIT(13)
+#define BIT_DATA_RPFM12EN_8814B BIT(12)
+#define BIT_DATA_RPFM11EN_8814B BIT(11)
+#define BIT_DATA_RPFM10EN_8814B BIT(10)
+#define BIT_DATA_RPFM9EN_8814B BIT(9)
+#define BIT_DATA_RPFM8EN_8814B BIT(8)
+#define BIT_DATA_RPFM7EN_8814B BIT(7)
+#define BIT_DATA_RPFM6EN_8814B BIT(6)
+#define BIT_DATA_RPFM5EN_8814B BIT(5)
+#define BIT_DATA_RPFM4EN_8814B BIT(4)
+#define BIT_DATA_RPFM3EN_8814B BIT(3)
+#define BIT_DATA_RPFM2EN_8814B BIT(2)
+#define BIT_DATA_RPFM1EN_8814B BIT(1)
+#define BIT_DATA_RPFM0EN_8814B BIT(0)
+
+/* 2 REG_RPFM_CAM_CMD_8814B (RX PAYLOAD FRAME MASK CAM COMMAND REGISTER) */
+#define BIT_RPFM_CAM_POLLING_8814B BIT(31)
+#define BIT_RPFM_CAM_CLR_8814B BIT(30)
+#define BIT_RPFM_CAM_WE_8814B BIT(16)
+
+#define BIT_SHIFT_RPFM_CAM_ADDR_8814B 0
+#define BIT_MASK_RPFM_CAM_ADDR_8814B 0x7f
+#define BIT_RPFM_CAM_ADDR_8814B(x)                                             \
+	(((x) & BIT_MASK_RPFM_CAM_ADDR_8814B) << BIT_SHIFT_RPFM_CAM_ADDR_8814B)
+#define BITS_RPFM_CAM_ADDR_8814B                                               \
+	(BIT_MASK_RPFM_CAM_ADDR_8814B << BIT_SHIFT_RPFM_CAM_ADDR_8814B)
+#define BIT_CLEAR_RPFM_CAM_ADDR_8814B(x) ((x) & (~BITS_RPFM_CAM_ADDR_8814B))
+#define BIT_GET_RPFM_CAM_ADDR_8814B(x)                                         \
+	(((x) >> BIT_SHIFT_RPFM_CAM_ADDR_8814B) & BIT_MASK_RPFM_CAM_ADDR_8814B)
+#define BIT_SET_RPFM_CAM_ADDR_8814B(x, v)                                      \
+	(BIT_CLEAR_RPFM_CAM_ADDR_8814B(x) | BIT_RPFM_CAM_ADDR_8814B(v))
+
+/* 2 REG_RPFM_CAM_RWD_8814B (ACK TIMEOUT REGISTER) */
+
+#define BIT_SHIFT_RPFM_CAM_RWD_8814B 0
+#define BIT_MASK_RPFM_CAM_RWD_8814B 0xffffffffL
+#define BIT_RPFM_CAM_RWD_8814B(x)                                              \
+	(((x) & BIT_MASK_RPFM_CAM_RWD_8814B) << BIT_SHIFT_RPFM_CAM_RWD_8814B)
+#define BITS_RPFM_CAM_RWD_8814B                                                \
+	(BIT_MASK_RPFM_CAM_RWD_8814B << BIT_SHIFT_RPFM_CAM_RWD_8814B)
+#define BIT_CLEAR_RPFM_CAM_RWD_8814B(x) ((x) & (~BITS_RPFM_CAM_RWD_8814B))
+#define BIT_GET_RPFM_CAM_RWD_8814B(x)                                          \
+	(((x) >> BIT_SHIFT_RPFM_CAM_RWD_8814B) & BIT_MASK_RPFM_CAM_RWD_8814B)
+#define BIT_SET_RPFM_CAM_RWD_8814B(x, v)                                       \
+	(BIT_CLEAR_RPFM_CAM_RWD_8814B(x) | BIT_RPFM_CAM_RWD_8814B(v))
+
+/* 2 REG_NAV_CTRL_8814B (NAV CONTROL REGISTER) */
+
+#define BIT_SHIFT_NAV_UPPER_8814B 16
+#define BIT_MASK_NAV_UPPER_8814B 0xff
+#define BIT_NAV_UPPER_8814B(x)                                                 \
+	(((x) & BIT_MASK_NAV_UPPER_8814B) << BIT_SHIFT_NAV_UPPER_8814B)
+#define BITS_NAV_UPPER_8814B                                                   \
+	(BIT_MASK_NAV_UPPER_8814B << BIT_SHIFT_NAV_UPPER_8814B)
+#define BIT_CLEAR_NAV_UPPER_8814B(x) ((x) & (~BITS_NAV_UPPER_8814B))
+#define BIT_GET_NAV_UPPER_8814B(x)                                             \
+	(((x) >> BIT_SHIFT_NAV_UPPER_8814B) & BIT_MASK_NAV_UPPER_8814B)
+#define BIT_SET_NAV_UPPER_8814B(x, v)                                          \
+	(BIT_CLEAR_NAV_UPPER_8814B(x) | BIT_NAV_UPPER_8814B(v))
+
+#define BIT_SHIFT_RXMYRTS_NAV_8814B 8
+#define BIT_MASK_RXMYRTS_NAV_8814B 0xf
+#define BIT_RXMYRTS_NAV_8814B(x)                                               \
+	(((x) & BIT_MASK_RXMYRTS_NAV_8814B) << BIT_SHIFT_RXMYRTS_NAV_8814B)
+#define BITS_RXMYRTS_NAV_8814B                                                 \
+	(BIT_MASK_RXMYRTS_NAV_8814B << BIT_SHIFT_RXMYRTS_NAV_8814B)
+#define BIT_CLEAR_RXMYRTS_NAV_8814B(x) ((x) & (~BITS_RXMYRTS_NAV_8814B))
+#define BIT_GET_RXMYRTS_NAV_8814B(x)                                           \
+	(((x) >> BIT_SHIFT_RXMYRTS_NAV_8814B) & BIT_MASK_RXMYRTS_NAV_8814B)
+#define BIT_SET_RXMYRTS_NAV_8814B(x, v)                                        \
+	(BIT_CLEAR_RXMYRTS_NAV_8814B(x) | BIT_RXMYRTS_NAV_8814B(v))
+
+#define BIT_SHIFT_RTSRST_8814B 0
+#define BIT_MASK_RTSRST_8814B 0xff
+#define BIT_RTSRST_8814B(x)                                                    \
+	(((x) & BIT_MASK_RTSRST_8814B) << BIT_SHIFT_RTSRST_8814B)
+#define BITS_RTSRST_8814B (BIT_MASK_RTSRST_8814B << BIT_SHIFT_RTSRST_8814B)
+#define BIT_CLEAR_RTSRST_8814B(x) ((x) & (~BITS_RTSRST_8814B))
+#define BIT_GET_RTSRST_8814B(x)                                                \
+	(((x) >> BIT_SHIFT_RTSRST_8814B) & BIT_MASK_RTSRST_8814B)
+#define BIT_SET_RTSRST_8814B(x, v)                                             \
+	(BIT_CLEAR_RTSRST_8814B(x) | BIT_RTSRST_8814B(v))
+
+/* 2 REG_BACAMCMD_8814B (BLOCK ACK CAM COMMAND REGISTER) */
+#define BIT_BACAM_POLL_8814B BIT(31)
+#define BIT_BACAM_RST_8814B BIT(17)
+#define BIT_BACAM_RW_8814B BIT(16)
+
+#define BIT_SHIFT_TXSBM_8814B 14
+#define BIT_MASK_TXSBM_8814B 0x3
+#define BIT_TXSBM_8814B(x)                                                     \
+	(((x) & BIT_MASK_TXSBM_8814B) << BIT_SHIFT_TXSBM_8814B)
+#define BITS_TXSBM_8814B (BIT_MASK_TXSBM_8814B << BIT_SHIFT_TXSBM_8814B)
+#define BIT_CLEAR_TXSBM_8814B(x) ((x) & (~BITS_TXSBM_8814B))
+#define BIT_GET_TXSBM_8814B(x)                                                 \
+	(((x) >> BIT_SHIFT_TXSBM_8814B) & BIT_MASK_TXSBM_8814B)
+#define BIT_SET_TXSBM_8814B(x, v)                                              \
+	(BIT_CLEAR_TXSBM_8814B(x) | BIT_TXSBM_8814B(v))
+
+#define BIT_SHIFT_BACAM_ADDR_8814B 0
+#define BIT_MASK_BACAM_ADDR_8814B 0x3f
+#define BIT_BACAM_ADDR_8814B(x)                                                \
+	(((x) & BIT_MASK_BACAM_ADDR_8814B) << BIT_SHIFT_BACAM_ADDR_8814B)
+#define BITS_BACAM_ADDR_8814B                                                  \
+	(BIT_MASK_BACAM_ADDR_8814B << BIT_SHIFT_BACAM_ADDR_8814B)
+#define BIT_CLEAR_BACAM_ADDR_8814B(x) ((x) & (~BITS_BACAM_ADDR_8814B))
+#define BIT_GET_BACAM_ADDR_8814B(x)                                            \
+	(((x) >> BIT_SHIFT_BACAM_ADDR_8814B) & BIT_MASK_BACAM_ADDR_8814B)
+#define BIT_SET_BACAM_ADDR_8814B(x, v)                                         \
+	(BIT_CLEAR_BACAM_ADDR_8814B(x) | BIT_BACAM_ADDR_8814B(v))
+
+/* 2 REG_BACAMCONTENT_8814B (BLOCK ACK CAM CONTENT REGISTER) */
+
+#define BIT_SHIFT_BA_CONTENT_L_8814B 0
+#define BIT_MASK_BA_CONTENT_L_8814B 0xffffffffL
+#define BIT_BA_CONTENT_L_8814B(x)                                              \
+	(((x) & BIT_MASK_BA_CONTENT_L_8814B) << BIT_SHIFT_BA_CONTENT_L_8814B)
+#define BITS_BA_CONTENT_L_8814B                                                \
+	(BIT_MASK_BA_CONTENT_L_8814B << BIT_SHIFT_BA_CONTENT_L_8814B)
+#define BIT_CLEAR_BA_CONTENT_L_8814B(x) ((x) & (~BITS_BA_CONTENT_L_8814B))
+#define BIT_GET_BA_CONTENT_L_8814B(x)                                          \
+	(((x) >> BIT_SHIFT_BA_CONTENT_L_8814B) & BIT_MASK_BA_CONTENT_L_8814B)
+#define BIT_SET_BA_CONTENT_L_8814B(x, v)                                       \
+	(BIT_CLEAR_BA_CONTENT_L_8814B(x) | BIT_BA_CONTENT_L_8814B(v))
+
+/* 2 REG_BACAMCONTENT_H_8814B (BLOCK ACK CAM CONTENT REGISTER) */
+
+#define BIT_SHIFT_BA_CONTENT_H_8814B 0
+#define BIT_MASK_BA_CONTENT_H_8814B 0xffffffffL
+#define BIT_BA_CONTENT_H_8814B(x)                                              \
+	(((x) & BIT_MASK_BA_CONTENT_H_8814B) << BIT_SHIFT_BA_CONTENT_H_8814B)
+#define BITS_BA_CONTENT_H_8814B                                                \
+	(BIT_MASK_BA_CONTENT_H_8814B << BIT_SHIFT_BA_CONTENT_H_8814B)
+#define BIT_CLEAR_BA_CONTENT_H_8814B(x) ((x) & (~BITS_BA_CONTENT_H_8814B))
+#define BIT_GET_BA_CONTENT_H_8814B(x)                                          \
+	(((x) >> BIT_SHIFT_BA_CONTENT_H_8814B) & BIT_MASK_BA_CONTENT_H_8814B)
+#define BIT_SET_BA_CONTENT_H_8814B(x, v)                                       \
+	(BIT_CLEAR_BA_CONTENT_H_8814B(x) | BIT_BA_CONTENT_H_8814B(v))
+
+/* 2 REG_LBDLY_8814B (LOOPBACK DELAY REGISTER) */
+
+#define BIT_SHIFT_LBDLY_8814B 0
+#define BIT_MASK_LBDLY_8814B 0x1f
+#define BIT_LBDLY_8814B(x)                                                     \
+	(((x) & BIT_MASK_LBDLY_8814B) << BIT_SHIFT_LBDLY_8814B)
+#define BITS_LBDLY_8814B (BIT_MASK_LBDLY_8814B << BIT_SHIFT_LBDLY_8814B)
+#define BIT_CLEAR_LBDLY_8814B(x) ((x) & (~BITS_LBDLY_8814B))
+#define BIT_GET_LBDLY_8814B(x)                                                 \
+	(((x) >> BIT_SHIFT_LBDLY_8814B) & BIT_MASK_LBDLY_8814B)
+#define BIT_SET_LBDLY_8814B(x, v)                                              \
+	(BIT_CLEAR_LBDLY_8814B(x) | BIT_LBDLY_8814B(v))
+
+/* 2 REG_WMAC_BACAM_RPMEN_8814B */
+
+#define BIT_SHIFT_BITMAP_SSNBK_COUNTER_8814B 2
+#define BIT_MASK_BITMAP_SSNBK_COUNTER_8814B 0x3f
+#define BIT_BITMAP_SSNBK_COUNTER_8814B(x)                                      \
+	(((x) & BIT_MASK_BITMAP_SSNBK_COUNTER_8814B)                           \
+	 << BIT_SHIFT_BITMAP_SSNBK_COUNTER_8814B)
+#define BITS_BITMAP_SSNBK_COUNTER_8814B                                        \
+	(BIT_MASK_BITMAP_SSNBK_COUNTER_8814B                                   \
+	 << BIT_SHIFT_BITMAP_SSNBK_COUNTER_8814B)
+#define BIT_CLEAR_BITMAP_SSNBK_COUNTER_8814B(x)                                \
+	((x) & (~BITS_BITMAP_SSNBK_COUNTER_8814B))
+#define BIT_GET_BITMAP_SSNBK_COUNTER_8814B(x)                                  \
+	(((x) >> BIT_SHIFT_BITMAP_SSNBK_COUNTER_8814B) &                       \
+	 BIT_MASK_BITMAP_SSNBK_COUNTER_8814B)
+#define BIT_SET_BITMAP_SSNBK_COUNTER_8814B(x, v)                               \
+	(BIT_CLEAR_BITMAP_SSNBK_COUNTER_8814B(x) |                             \
+	 BIT_BITMAP_SSNBK_COUNTER_8814B(v))
+
+#define BIT_BITMAP_EN_8814B BIT(1)
+#define BIT_WMAC_BACAM_RPMEN_8814B BIT(0)
+
+/* 2 REG_TX_RX_8814B STATUS */
+
+#define BIT_SHIFT_RXPKT_TYPE_8814B 2
+#define BIT_MASK_RXPKT_TYPE_8814B 0x3f
+#define BIT_RXPKT_TYPE_8814B(x)                                                \
+	(((x) & BIT_MASK_RXPKT_TYPE_8814B) << BIT_SHIFT_RXPKT_TYPE_8814B)
+#define BITS_RXPKT_TYPE_8814B                                                  \
+	(BIT_MASK_RXPKT_TYPE_8814B << BIT_SHIFT_RXPKT_TYPE_8814B)
+#define BIT_CLEAR_RXPKT_TYPE_8814B(x) ((x) & (~BITS_RXPKT_TYPE_8814B))
+#define BIT_GET_RXPKT_TYPE_8814B(x)                                            \
+	(((x) >> BIT_SHIFT_RXPKT_TYPE_8814B) & BIT_MASK_RXPKT_TYPE_8814B)
+#define BIT_SET_RXPKT_TYPE_8814B(x, v)                                         \
+	(BIT_CLEAR_RXPKT_TYPE_8814B(x) | BIT_RXPKT_TYPE_8814B(v))
+
+#define BIT_TXACT_IND_8814B BIT(1)
+#define BIT_RXACT_IND_8814B BIT(0)
+
+/* 2 REG_WMAC_BITMAP_CTL_8814B */
+#define BIT_BITMAP_VO_8814B BIT(7)
+#define BIT_BITMAP_VI_8814B BIT(6)
+#define BIT_BITMAP_BE_8814B BIT(5)
+#define BIT_BITMAP_BK_8814B BIT(4)
+
+#define BIT_SHIFT_BITMAP_CONDITION_8814B 2
+#define BIT_MASK_BITMAP_CONDITION_8814B 0x3
+#define BIT_BITMAP_CONDITION_8814B(x)                                          \
+	(((x) & BIT_MASK_BITMAP_CONDITION_8814B)                               \
+	 << BIT_SHIFT_BITMAP_CONDITION_8814B)
+#define BITS_BITMAP_CONDITION_8814B                                            \
+	(BIT_MASK_BITMAP_CONDITION_8814B << BIT_SHIFT_BITMAP_CONDITION_8814B)
+#define BIT_CLEAR_BITMAP_CONDITION_8814B(x)                                    \
+	((x) & (~BITS_BITMAP_CONDITION_8814B))
+#define BIT_GET_BITMAP_CONDITION_8814B(x)                                      \
+	(((x) >> BIT_SHIFT_BITMAP_CONDITION_8814B) &                           \
+	 BIT_MASK_BITMAP_CONDITION_8814B)
+#define BIT_SET_BITMAP_CONDITION_8814B(x, v)                                   \
+	(BIT_CLEAR_BITMAP_CONDITION_8814B(x) | BIT_BITMAP_CONDITION_8814B(v))
+
+#define BIT_BITMAP_SSNBK_COUNTER_CLR_8814B BIT(1)
+#define BIT_BITMAP_FORCE_8814B BIT(0)
+
+/* 2 REG_RXERR_RPT_8814B (RX ERROR REPORT REGISTER) */
+
+#define BIT_SHIFT_RXERR_RPT_SEL_V1_3_0_8814B 28
+#define BIT_MASK_RXERR_RPT_SEL_V1_3_0_8814B 0xf
+#define BIT_RXERR_RPT_SEL_V1_3_0_8814B(x)                                      \
+	(((x) & BIT_MASK_RXERR_RPT_SEL_V1_3_0_8814B)                           \
+	 << BIT_SHIFT_RXERR_RPT_SEL_V1_3_0_8814B)
+#define BITS_RXERR_RPT_SEL_V1_3_0_8814B                                        \
+	(BIT_MASK_RXERR_RPT_SEL_V1_3_0_8814B                                   \
+	 << BIT_SHIFT_RXERR_RPT_SEL_V1_3_0_8814B)
+#define BIT_CLEAR_RXERR_RPT_SEL_V1_3_0_8814B(x)                                \
+	((x) & (~BITS_RXERR_RPT_SEL_V1_3_0_8814B))
+#define BIT_GET_RXERR_RPT_SEL_V1_3_0_8814B(x)                                  \
+	(((x) >> BIT_SHIFT_RXERR_RPT_SEL_V1_3_0_8814B) &                       \
+	 BIT_MASK_RXERR_RPT_SEL_V1_3_0_8814B)
+#define BIT_SET_RXERR_RPT_SEL_V1_3_0_8814B(x, v)                               \
+	(BIT_CLEAR_RXERR_RPT_SEL_V1_3_0_8814B(x) |                             \
+	 BIT_RXERR_RPT_SEL_V1_3_0_8814B(v))
+
+#define BIT_RXERR_RPT_RST_8814B BIT(27)
+#define BIT_RXERR_RPT_SEL_V1_4_8814B BIT(26)
+#define BIT_W1S_8814B BIT(23)
+#define BIT_UD_SELECT_BSSID_8814B BIT(22)
+
+#define BIT_SHIFT_UD_SUB_TYPE_8814B 18
+#define BIT_MASK_UD_SUB_TYPE_8814B 0xf
+#define BIT_UD_SUB_TYPE_8814B(x)                                               \
+	(((x) & BIT_MASK_UD_SUB_TYPE_8814B) << BIT_SHIFT_UD_SUB_TYPE_8814B)
+#define BITS_UD_SUB_TYPE_8814B                                                 \
+	(BIT_MASK_UD_SUB_TYPE_8814B << BIT_SHIFT_UD_SUB_TYPE_8814B)
+#define BIT_CLEAR_UD_SUB_TYPE_8814B(x) ((x) & (~BITS_UD_SUB_TYPE_8814B))
+#define BIT_GET_UD_SUB_TYPE_8814B(x)                                           \
+	(((x) >> BIT_SHIFT_UD_SUB_TYPE_8814B) & BIT_MASK_UD_SUB_TYPE_8814B)
+#define BIT_SET_UD_SUB_TYPE_8814B(x, v)                                        \
+	(BIT_CLEAR_UD_SUB_TYPE_8814B(x) | BIT_UD_SUB_TYPE_8814B(v))
+
+#define BIT_SHIFT_UD_TYPE_8814B 16
+#define BIT_MASK_UD_TYPE_8814B 0x3
+#define BIT_UD_TYPE_8814B(x)                                                   \
+	(((x) & BIT_MASK_UD_TYPE_8814B) << BIT_SHIFT_UD_TYPE_8814B)
+#define BITS_UD_TYPE_8814B (BIT_MASK_UD_TYPE_8814B << BIT_SHIFT_UD_TYPE_8814B)
+#define BIT_CLEAR_UD_TYPE_8814B(x) ((x) & (~BITS_UD_TYPE_8814B))
+#define BIT_GET_UD_TYPE_8814B(x)                                               \
+	(((x) >> BIT_SHIFT_UD_TYPE_8814B) & BIT_MASK_UD_TYPE_8814B)
+#define BIT_SET_UD_TYPE_8814B(x, v)                                            \
+	(BIT_CLEAR_UD_TYPE_8814B(x) | BIT_UD_TYPE_8814B(v))
+
+#define BIT_SHIFT_RPT_COUNTER_8814B 0
+#define BIT_MASK_RPT_COUNTER_8814B 0xffff
+#define BIT_RPT_COUNTER_8814B(x)                                               \
+	(((x) & BIT_MASK_RPT_COUNTER_8814B) << BIT_SHIFT_RPT_COUNTER_8814B)
+#define BITS_RPT_COUNTER_8814B                                                 \
+	(BIT_MASK_RPT_COUNTER_8814B << BIT_SHIFT_RPT_COUNTER_8814B)
+#define BIT_CLEAR_RPT_COUNTER_8814B(x) ((x) & (~BITS_RPT_COUNTER_8814B))
+#define BIT_GET_RPT_COUNTER_8814B(x)                                           \
+	(((x) >> BIT_SHIFT_RPT_COUNTER_8814B) & BIT_MASK_RPT_COUNTER_8814B)
+#define BIT_SET_RPT_COUNTER_8814B(x, v)                                        \
+	(BIT_CLEAR_RPT_COUNTER_8814B(x) | BIT_RPT_COUNTER_8814B(v))
+
+/* 2 REG_WMAC_TRXPTCL_CTL_8814B	(WMAC TX/RX PROTOCOL CONTROL REGISTER) */
+#define BIT_EN_TXCTS_INTXOP_8814B BIT(32)
+#define BIT_BLK_EDCA_BBSLP_8814B BIT(31)
+#define BIT_BLK_EDCA_BBSBY_8814B BIT(30)
+#define BIT_ACKTO_BLOCK_SCH_EN_8814B BIT(27)
+#define BIT_EIFS_BLOCK_SCH_EN_8814B BIT(26)
+#define BIT_PLCPCHK_RST_EIFS_8814B BIT(25)
+#define BIT_CCA_RST_EIFS_8814B BIT(24)
+#define BIT_DIS_UPD_MYRXPKTNAV_8814B BIT(23)
+#define BIT_EARLY_TXBA_8814B BIT(22)
+
+#define BIT_SHIFT_RESP_CHNBUSY_8814B 20
+#define BIT_MASK_RESP_CHNBUSY_8814B 0x3
+#define BIT_RESP_CHNBUSY_8814B(x)                                              \
+	(((x) & BIT_MASK_RESP_CHNBUSY_8814B) << BIT_SHIFT_RESP_CHNBUSY_8814B)
+#define BITS_RESP_CHNBUSY_8814B                                                \
+	(BIT_MASK_RESP_CHNBUSY_8814B << BIT_SHIFT_RESP_CHNBUSY_8814B)
+#define BIT_CLEAR_RESP_CHNBUSY_8814B(x) ((x) & (~BITS_RESP_CHNBUSY_8814B))
+#define BIT_GET_RESP_CHNBUSY_8814B(x)                                          \
+	(((x) >> BIT_SHIFT_RESP_CHNBUSY_8814B) & BIT_MASK_RESP_CHNBUSY_8814B)
+#define BIT_SET_RESP_CHNBUSY_8814B(x, v)                                       \
+	(BIT_CLEAR_RESP_CHNBUSY_8814B(x) | BIT_RESP_CHNBUSY_8814B(v))
+
+#define BIT_RESP_DCTS_EN_8814B BIT(19)
+#define BIT_RESP_DCFE_EN_8814B BIT(18)
+#define BIT_RESP_SPLCPEN_8814B BIT(17)
+#define BIT_RESP_SGIEN_8814B BIT(16)
+#define BIT_RESP_LDPC_EN_8814B BIT(15)
+#define BIT_DIS_RESP_ACKINCCA_8814B BIT(14)
+#define BIT_DIS_RESP_CTSINCCA_8814B BIT(13)
+
+#define BIT_SHIFT_R_WMAC_SECOND_CCA_TIMER_8814B 10
+#define BIT_MASK_R_WMAC_SECOND_CCA_TIMER_8814B 0x7
+#define BIT_R_WMAC_SECOND_CCA_TIMER_8814B(x)                                   \
+	(((x) & BIT_MASK_R_WMAC_SECOND_CCA_TIMER_8814B)                        \
+	 << BIT_SHIFT_R_WMAC_SECOND_CCA_TIMER_8814B)
+#define BITS_R_WMAC_SECOND_CCA_TIMER_8814B                                     \
+	(BIT_MASK_R_WMAC_SECOND_CCA_TIMER_8814B                                \
+	 << BIT_SHIFT_R_WMAC_SECOND_CCA_TIMER_8814B)
+#define BIT_CLEAR_R_WMAC_SECOND_CCA_TIMER_8814B(x)                             \
+	((x) & (~BITS_R_WMAC_SECOND_CCA_TIMER_8814B))
+#define BIT_GET_R_WMAC_SECOND_CCA_TIMER_8814B(x)                               \
+	(((x) >> BIT_SHIFT_R_WMAC_SECOND_CCA_TIMER_8814B) &                    \
+	 BIT_MASK_R_WMAC_SECOND_CCA_TIMER_8814B)
+#define BIT_SET_R_WMAC_SECOND_CCA_TIMER_8814B(x, v)                            \
+	(BIT_CLEAR_R_WMAC_SECOND_CCA_TIMER_8814B(x) |                          \
+	 BIT_R_WMAC_SECOND_CCA_TIMER_8814B(v))
+
+#define BIT_SHIFT_RFMOD_8814B 7
+#define BIT_MASK_RFMOD_8814B 0x3
+#define BIT_RFMOD_8814B(x)                                                     \
+	(((x) & BIT_MASK_RFMOD_8814B) << BIT_SHIFT_RFMOD_8814B)
+#define BITS_RFMOD_8814B (BIT_MASK_RFMOD_8814B << BIT_SHIFT_RFMOD_8814B)
+#define BIT_CLEAR_RFMOD_8814B(x) ((x) & (~BITS_RFMOD_8814B))
+#define BIT_GET_RFMOD_8814B(x)                                                 \
+	(((x) >> BIT_SHIFT_RFMOD_8814B) & BIT_MASK_RFMOD_8814B)
+#define BIT_SET_RFMOD_8814B(x, v)                                              \
+	(BIT_CLEAR_RFMOD_8814B(x) | BIT_RFMOD_8814B(v))
+
+#define BIT_SHIFT_RESP_CTS_DYNBW_SEL_8814B 5
+#define BIT_MASK_RESP_CTS_DYNBW_SEL_8814B 0x3
+#define BIT_RESP_CTS_DYNBW_SEL_8814B(x)                                        \
+	(((x) & BIT_MASK_RESP_CTS_DYNBW_SEL_8814B)                             \
+	 << BIT_SHIFT_RESP_CTS_DYNBW_SEL_8814B)
+#define BITS_RESP_CTS_DYNBW_SEL_8814B                                          \
+	(BIT_MASK_RESP_CTS_DYNBW_SEL_8814B                                     \
+	 << BIT_SHIFT_RESP_CTS_DYNBW_SEL_8814B)
+#define BIT_CLEAR_RESP_CTS_DYNBW_SEL_8814B(x)                                  \
+	((x) & (~BITS_RESP_CTS_DYNBW_SEL_8814B))
+#define BIT_GET_RESP_CTS_DYNBW_SEL_8814B(x)                                    \
+	(((x) >> BIT_SHIFT_RESP_CTS_DYNBW_SEL_8814B) &                         \
+	 BIT_MASK_RESP_CTS_DYNBW_SEL_8814B)
+#define BIT_SET_RESP_CTS_DYNBW_SEL_8814B(x, v)                                 \
+	(BIT_CLEAR_RESP_CTS_DYNBW_SEL_8814B(x) |                               \
+	 BIT_RESP_CTS_DYNBW_SEL_8814B(v))
+
+#define BIT_DLY_TX_WAIT_RXANTSEL_8814B BIT(4)
+#define BIT_TXRESP_BY_RXANTSEL_8814B BIT(3)
+
+#define BIT_SHIFT_ORIG_DCTS_CHK_8814B 0
+#define BIT_MASK_ORIG_DCTS_CHK_8814B 0x3
+#define BIT_ORIG_DCTS_CHK_8814B(x)                                             \
+	(((x) & BIT_MASK_ORIG_DCTS_CHK_8814B) << BIT_SHIFT_ORIG_DCTS_CHK_8814B)
+#define BITS_ORIG_DCTS_CHK_8814B                                               \
+	(BIT_MASK_ORIG_DCTS_CHK_8814B << BIT_SHIFT_ORIG_DCTS_CHK_8814B)
+#define BIT_CLEAR_ORIG_DCTS_CHK_8814B(x) ((x) & (~BITS_ORIG_DCTS_CHK_8814B))
+#define BIT_GET_ORIG_DCTS_CHK_8814B(x)                                         \
+	(((x) >> BIT_SHIFT_ORIG_DCTS_CHK_8814B) & BIT_MASK_ORIG_DCTS_CHK_8814B)
+#define BIT_SET_ORIG_DCTS_CHK_8814B(x, v)                                      \
+	(BIT_CLEAR_ORIG_DCTS_CHK_8814B(x) | BIT_ORIG_DCTS_CHK_8814B(v))
+
+/* 2 REG_WMAC_TRXPTCL_CTL_H_8814B */
+
+#define BIT_SHIFT_ACKBA_TYPSEL_8814B 28
+#define BIT_MASK_ACKBA_TYPSEL_8814B 0xf
+#define BIT_ACKBA_TYPSEL_8814B(x)                                              \
+	(((x) & BIT_MASK_ACKBA_TYPSEL_8814B) << BIT_SHIFT_ACKBA_TYPSEL_8814B)
+#define BITS_ACKBA_TYPSEL_8814B                                                \
+	(BIT_MASK_ACKBA_TYPSEL_8814B << BIT_SHIFT_ACKBA_TYPSEL_8814B)
+#define BIT_CLEAR_ACKBA_TYPSEL_8814B(x) ((x) & (~BITS_ACKBA_TYPSEL_8814B))
+#define BIT_GET_ACKBA_TYPSEL_8814B(x)                                          \
+	(((x) >> BIT_SHIFT_ACKBA_TYPSEL_8814B) & BIT_MASK_ACKBA_TYPSEL_8814B)
+#define BIT_SET_ACKBA_TYPSEL_8814B(x, v)                                       \
+	(BIT_CLEAR_ACKBA_TYPSEL_8814B(x) | BIT_ACKBA_TYPSEL_8814B(v))
+
+#define BIT_SHIFT_ACKBA_ACKPCHK_8814B 24
+#define BIT_MASK_ACKBA_ACKPCHK_8814B 0xf
+#define BIT_ACKBA_ACKPCHK_8814B(x)                                             \
+	(((x) & BIT_MASK_ACKBA_ACKPCHK_8814B) << BIT_SHIFT_ACKBA_ACKPCHK_8814B)
+#define BITS_ACKBA_ACKPCHK_8814B                                               \
+	(BIT_MASK_ACKBA_ACKPCHK_8814B << BIT_SHIFT_ACKBA_ACKPCHK_8814B)
+#define BIT_CLEAR_ACKBA_ACKPCHK_8814B(x) ((x) & (~BITS_ACKBA_ACKPCHK_8814B))
+#define BIT_GET_ACKBA_ACKPCHK_8814B(x)                                         \
+	(((x) >> BIT_SHIFT_ACKBA_ACKPCHK_8814B) & BIT_MASK_ACKBA_ACKPCHK_8814B)
+#define BIT_SET_ACKBA_ACKPCHK_8814B(x, v)                                      \
+	(BIT_CLEAR_ACKBA_ACKPCHK_8814B(x) | BIT_ACKBA_ACKPCHK_8814B(v))
+
+#define BIT_SHIFT_ACKBAR_TYPESEL_8814B 16
+#define BIT_MASK_ACKBAR_TYPESEL_8814B 0xff
+#define BIT_ACKBAR_TYPESEL_8814B(x)                                            \
+	(((x) & BIT_MASK_ACKBAR_TYPESEL_8814B)                                 \
+	 << BIT_SHIFT_ACKBAR_TYPESEL_8814B)
+#define BITS_ACKBAR_TYPESEL_8814B                                              \
+	(BIT_MASK_ACKBAR_TYPESEL_8814B << BIT_SHIFT_ACKBAR_TYPESEL_8814B)
+#define BIT_CLEAR_ACKBAR_TYPESEL_8814B(x) ((x) & (~BITS_ACKBAR_TYPESEL_8814B))
+#define BIT_GET_ACKBAR_TYPESEL_8814B(x)                                        \
+	(((x) >> BIT_SHIFT_ACKBAR_TYPESEL_8814B) &                             \
+	 BIT_MASK_ACKBAR_TYPESEL_8814B)
+#define BIT_SET_ACKBAR_TYPESEL_8814B(x, v)                                     \
+	(BIT_CLEAR_ACKBAR_TYPESEL_8814B(x) | BIT_ACKBAR_TYPESEL_8814B(v))
+
+#define BIT_SHIFT_ACKBAR_ACKPCHK_8814B 12
+#define BIT_MASK_ACKBAR_ACKPCHK_8814B 0xf
+#define BIT_ACKBAR_ACKPCHK_8814B(x)                                            \
+	(((x) & BIT_MASK_ACKBAR_ACKPCHK_8814B)                                 \
+	 << BIT_SHIFT_ACKBAR_ACKPCHK_8814B)
+#define BITS_ACKBAR_ACKPCHK_8814B                                              \
+	(BIT_MASK_ACKBAR_ACKPCHK_8814B << BIT_SHIFT_ACKBAR_ACKPCHK_8814B)
+#define BIT_CLEAR_ACKBAR_ACKPCHK_8814B(x) ((x) & (~BITS_ACKBAR_ACKPCHK_8814B))
+#define BIT_GET_ACKBAR_ACKPCHK_8814B(x)                                        \
+	(((x) >> BIT_SHIFT_ACKBAR_ACKPCHK_8814B) &                             \
+	 BIT_MASK_ACKBAR_ACKPCHK_8814B)
+#define BIT_SET_ACKBAR_ACKPCHK_8814B(x, v)                                     \
+	(BIT_CLEAR_ACKBAR_ACKPCHK_8814B(x) | BIT_ACKBAR_ACKPCHK_8814B(v))
+
+#define BIT_RXBA_IGNOREA2_V1_8814B BIT(10)
+#define BIT_EN_SAVE_ALL_TXOPADDR_V1_8814B BIT(9)
+#define BIT_EN_TXCTS_TO_TXOPOWNER_INRXNAV_V1_8814B BIT(8)
+#define BIT_DIS_TXBA_AMPDUFCSERR_V1_8814B BIT(7)
+#define BIT_DIS_TXBA_RXBARINFULL_V1_8814B BIT(6)
+#define BIT_DIS_TXCFE_INFULL_V1_8814B BIT(5)
+#define BIT_DIS_TXCTS_INFULL_V1_8814B BIT(4)
+#define BIT_EN_TXACKBA_IN_TX_RDG_V1_8814B BIT(3)
+#define BIT_EN_TXACKBA_IN_TXOP_V1_8814B BIT(2)
+#define BIT_EN_TXCTS_IN_RXNAV_V1_8814B BIT(1)
+#define BIT_EN_TXCTS_INTXOP_V1_8814B BIT(0)
+
+/* 2 REG_CAMCMD_8814B (CAM COMMAND REGISTER) */
+#define BIT_SECCAM_POLLING_8814B BIT(31)
+#define BIT_SECCAM_CLR_8814B BIT(30)
+#define BIT_SECCAM_WE_8814B BIT(16)
+
+#define BIT_SHIFT_SECCAM_ADDR_V2_8814B 0
+#define BIT_MASK_SECCAM_ADDR_V2_8814B 0x3ff
+#define BIT_SECCAM_ADDR_V2_8814B(x)                                            \
+	(((x) & BIT_MASK_SECCAM_ADDR_V2_8814B)                                 \
+	 << BIT_SHIFT_SECCAM_ADDR_V2_8814B)
+#define BITS_SECCAM_ADDR_V2_8814B                                              \
+	(BIT_MASK_SECCAM_ADDR_V2_8814B << BIT_SHIFT_SECCAM_ADDR_V2_8814B)
+#define BIT_CLEAR_SECCAM_ADDR_V2_8814B(x) ((x) & (~BITS_SECCAM_ADDR_V2_8814B))
+#define BIT_GET_SECCAM_ADDR_V2_8814B(x)                                        \
+	(((x) >> BIT_SHIFT_SECCAM_ADDR_V2_8814B) &                             \
+	 BIT_MASK_SECCAM_ADDR_V2_8814B)
+#define BIT_SET_SECCAM_ADDR_V2_8814B(x, v)                                     \
+	(BIT_CLEAR_SECCAM_ADDR_V2_8814B(x) | BIT_SECCAM_ADDR_V2_8814B(v))
+
+/* 2 REG_CAMWRITE_8814B (CAM WRITE REGISTER) */
+
+#define BIT_SHIFT_CAMW_DATA_8814B 0
+#define BIT_MASK_CAMW_DATA_8814B 0xffffffffL
+#define BIT_CAMW_DATA_8814B(x)                                                 \
+	(((x) & BIT_MASK_CAMW_DATA_8814B) << BIT_SHIFT_CAMW_DATA_8814B)
+#define BITS_CAMW_DATA_8814B                                                   \
+	(BIT_MASK_CAMW_DATA_8814B << BIT_SHIFT_CAMW_DATA_8814B)
+#define BIT_CLEAR_CAMW_DATA_8814B(x) ((x) & (~BITS_CAMW_DATA_8814B))
+#define BIT_GET_CAMW_DATA_8814B(x)                                             \
+	(((x) >> BIT_SHIFT_CAMW_DATA_8814B) & BIT_MASK_CAMW_DATA_8814B)
+#define BIT_SET_CAMW_DATA_8814B(x, v)                                          \
+	(BIT_CLEAR_CAMW_DATA_8814B(x) | BIT_CAMW_DATA_8814B(v))
+
+/* 2 REG_CAMREAD_8814B (CAM READ REGISTER) */
+
+#define BIT_SHIFT_CAMR_DATA_8814B 0
+#define BIT_MASK_CAMR_DATA_8814B 0xffffffffL
+#define BIT_CAMR_DATA_8814B(x)                                                 \
+	(((x) & BIT_MASK_CAMR_DATA_8814B) << BIT_SHIFT_CAMR_DATA_8814B)
+#define BITS_CAMR_DATA_8814B                                                   \
+	(BIT_MASK_CAMR_DATA_8814B << BIT_SHIFT_CAMR_DATA_8814B)
+#define BIT_CLEAR_CAMR_DATA_8814B(x) ((x) & (~BITS_CAMR_DATA_8814B))
+#define BIT_GET_CAMR_DATA_8814B(x)                                             \
+	(((x) >> BIT_SHIFT_CAMR_DATA_8814B) & BIT_MASK_CAMR_DATA_8814B)
+#define BIT_SET_CAMR_DATA_8814B(x, v)                                          \
+	(BIT_CLEAR_CAMR_DATA_8814B(x) | BIT_CAMR_DATA_8814B(v))
+
+/* 2 REG_CAMDBG_8814B (CAM DEBUG REGISTER) */
+#define BIT_SECCAM_INFO_8814B BIT(31)
+#define BIT_SEC_KEYFOUND_8814B BIT(15)
+
+#define BIT_SHIFT_CAMDBG_SEC_TYPE_8814B 12
+#define BIT_MASK_CAMDBG_SEC_TYPE_8814B 0x7
+#define BIT_CAMDBG_SEC_TYPE_8814B(x)                                           \
+	(((x) & BIT_MASK_CAMDBG_SEC_TYPE_8814B)                                \
+	 << BIT_SHIFT_CAMDBG_SEC_TYPE_8814B)
+#define BITS_CAMDBG_SEC_TYPE_8814B                                             \
+	(BIT_MASK_CAMDBG_SEC_TYPE_8814B << BIT_SHIFT_CAMDBG_SEC_TYPE_8814B)
+#define BIT_CLEAR_CAMDBG_SEC_TYPE_8814B(x) ((x) & (~BITS_CAMDBG_SEC_TYPE_8814B))
+#define BIT_GET_CAMDBG_SEC_TYPE_8814B(x)                                       \
+	(((x) >> BIT_SHIFT_CAMDBG_SEC_TYPE_8814B) &                            \
+	 BIT_MASK_CAMDBG_SEC_TYPE_8814B)
+#define BIT_SET_CAMDBG_SEC_TYPE_8814B(x, v)                                    \
+	(BIT_CLEAR_CAMDBG_SEC_TYPE_8814B(x) | BIT_CAMDBG_SEC_TYPE_8814B(v))
+
+#define BIT_CAMDBG_EXT_SECTYPE_8814B BIT(11)
+
+#define BIT_SHIFT_CAMDBG_MIC_KEY_IDX_8814B 5
+#define BIT_MASK_CAMDBG_MIC_KEY_IDX_8814B 0x1f
+#define BIT_CAMDBG_MIC_KEY_IDX_8814B(x)                                        \
+	(((x) & BIT_MASK_CAMDBG_MIC_KEY_IDX_8814B)                             \
+	 << BIT_SHIFT_CAMDBG_MIC_KEY_IDX_8814B)
+#define BITS_CAMDBG_MIC_KEY_IDX_8814B                                          \
+	(BIT_MASK_CAMDBG_MIC_KEY_IDX_8814B                                     \
+	 << BIT_SHIFT_CAMDBG_MIC_KEY_IDX_8814B)
+#define BIT_CLEAR_CAMDBG_MIC_KEY_IDX_8814B(x)                                  \
+	((x) & (~BITS_CAMDBG_MIC_KEY_IDX_8814B))
+#define BIT_GET_CAMDBG_MIC_KEY_IDX_8814B(x)                                    \
+	(((x) >> BIT_SHIFT_CAMDBG_MIC_KEY_IDX_8814B) &                         \
+	 BIT_MASK_CAMDBG_MIC_KEY_IDX_8814B)
+#define BIT_SET_CAMDBG_MIC_KEY_IDX_8814B(x, v)                                 \
+	(BIT_CLEAR_CAMDBG_MIC_KEY_IDX_8814B(x) |                               \
+	 BIT_CAMDBG_MIC_KEY_IDX_8814B(v))
+
+#define BIT_SHIFT_CAMDBG_SEC_KEY_IDX_8814B 0
+#define BIT_MASK_CAMDBG_SEC_KEY_IDX_8814B 0x1f
+#define BIT_CAMDBG_SEC_KEY_IDX_8814B(x)                                        \
+	(((x) & BIT_MASK_CAMDBG_SEC_KEY_IDX_8814B)                             \
+	 << BIT_SHIFT_CAMDBG_SEC_KEY_IDX_8814B)
+#define BITS_CAMDBG_SEC_KEY_IDX_8814B                                          \
+	(BIT_MASK_CAMDBG_SEC_KEY_IDX_8814B                                     \
+	 << BIT_SHIFT_CAMDBG_SEC_KEY_IDX_8814B)
+#define BIT_CLEAR_CAMDBG_SEC_KEY_IDX_8814B(x)                                  \
+	((x) & (~BITS_CAMDBG_SEC_KEY_IDX_8814B))
+#define BIT_GET_CAMDBG_SEC_KEY_IDX_8814B(x)                                    \
+	(((x) >> BIT_SHIFT_CAMDBG_SEC_KEY_IDX_8814B) &                         \
+	 BIT_MASK_CAMDBG_SEC_KEY_IDX_8814B)
+#define BIT_SET_CAMDBG_SEC_KEY_IDX_8814B(x, v)                                 \
+	(BIT_CLEAR_CAMDBG_SEC_KEY_IDX_8814B(x) |                               \
+	 BIT_CAMDBG_SEC_KEY_IDX_8814B(v))
+
+/* 2 REG_SECCFG_8814B (SECURITY CONFIGURATION REGISTER) */
+#define BIT_DIS_GCLK_WAPI_8814B BIT(15)
+#define BIT_DIS_GCLK_AES_8814B BIT(14)
+#define BIT_DIS_GCLK_TKIP_8814B BIT(13)
+#define BIT_AES_SEL_QC_1_8814B BIT(12)
+#define BIT_AES_SEL_QC_0_8814B BIT(11)
+#define BIT_CHK_BMC_8814B BIT(9)
+#define BIT_CHK_KEYID_8814B BIT(8)
+#define BIT_RXBCUSEDK_8814B BIT(7)
+#define BIT_TXBCUSEDK_8814B BIT(6)
+#define BIT_NOSKMC_8814B BIT(5)
+#define BIT_SKBYA2_8814B BIT(4)
+#define BIT_RXDEC_8814B BIT(3)
+#define BIT_TXENC_8814B BIT(2)
+#define BIT_RXUHUSEDK_8814B BIT(1)
+#define BIT_TXUHUSEDK_8814B BIT(0)
+
+/* 2 REG_RXFILTER_CATEGORY_1_8814B */
+
+#define BIT_SHIFT_RXFILTER_CATEGORY_1_8814B 0
+#define BIT_MASK_RXFILTER_CATEGORY_1_8814B 0xff
+#define BIT_RXFILTER_CATEGORY_1_8814B(x)                                       \
+	(((x) & BIT_MASK_RXFILTER_CATEGORY_1_8814B)                            \
+	 << BIT_SHIFT_RXFILTER_CATEGORY_1_8814B)
+#define BITS_RXFILTER_CATEGORY_1_8814B                                         \
+	(BIT_MASK_RXFILTER_CATEGORY_1_8814B                                    \
+	 << BIT_SHIFT_RXFILTER_CATEGORY_1_8814B)
+#define BIT_CLEAR_RXFILTER_CATEGORY_1_8814B(x)                                 \
+	((x) & (~BITS_RXFILTER_CATEGORY_1_8814B))
+#define BIT_GET_RXFILTER_CATEGORY_1_8814B(x)                                   \
+	(((x) >> BIT_SHIFT_RXFILTER_CATEGORY_1_8814B) &                        \
+	 BIT_MASK_RXFILTER_CATEGORY_1_8814B)
+#define BIT_SET_RXFILTER_CATEGORY_1_8814B(x, v)                                \
+	(BIT_CLEAR_RXFILTER_CATEGORY_1_8814B(x) |                              \
+	 BIT_RXFILTER_CATEGORY_1_8814B(v))
+
+/* 2 REG_RXFILTER_ACTION_1_8814B */
+
+#define BIT_SHIFT_RXFILTER_ACTION_1_8814B 0
+#define BIT_MASK_RXFILTER_ACTION_1_8814B 0xff
+#define BIT_RXFILTER_ACTION_1_8814B(x)                                         \
+	(((x) & BIT_MASK_RXFILTER_ACTION_1_8814B)                              \
+	 << BIT_SHIFT_RXFILTER_ACTION_1_8814B)
+#define BITS_RXFILTER_ACTION_1_8814B                                           \
+	(BIT_MASK_RXFILTER_ACTION_1_8814B << BIT_SHIFT_RXFILTER_ACTION_1_8814B)
+#define BIT_CLEAR_RXFILTER_ACTION_1_8814B(x)                                   \
+	((x) & (~BITS_RXFILTER_ACTION_1_8814B))
+#define BIT_GET_RXFILTER_ACTION_1_8814B(x)                                     \
+	(((x) >> BIT_SHIFT_RXFILTER_ACTION_1_8814B) &                          \
+	 BIT_MASK_RXFILTER_ACTION_1_8814B)
+#define BIT_SET_RXFILTER_ACTION_1_8814B(x, v)                                  \
+	(BIT_CLEAR_RXFILTER_ACTION_1_8814B(x) | BIT_RXFILTER_ACTION_1_8814B(v))
+
+/* 2 REG_RXFILTER_CATEGORY_2_8814B */
+
+#define BIT_SHIFT_RXFILTER_CATEGORY_2_8814B 0
+#define BIT_MASK_RXFILTER_CATEGORY_2_8814B 0xff
+#define BIT_RXFILTER_CATEGORY_2_8814B(x)                                       \
+	(((x) & BIT_MASK_RXFILTER_CATEGORY_2_8814B)                            \
+	 << BIT_SHIFT_RXFILTER_CATEGORY_2_8814B)
+#define BITS_RXFILTER_CATEGORY_2_8814B                                         \
+	(BIT_MASK_RXFILTER_CATEGORY_2_8814B                                    \
+	 << BIT_SHIFT_RXFILTER_CATEGORY_2_8814B)
+#define BIT_CLEAR_RXFILTER_CATEGORY_2_8814B(x)                                 \
+	((x) & (~BITS_RXFILTER_CATEGORY_2_8814B))
+#define BIT_GET_RXFILTER_CATEGORY_2_8814B(x)                                   \
+	(((x) >> BIT_SHIFT_RXFILTER_CATEGORY_2_8814B) &                        \
+	 BIT_MASK_RXFILTER_CATEGORY_2_8814B)
+#define BIT_SET_RXFILTER_CATEGORY_2_8814B(x, v)                                \
+	(BIT_CLEAR_RXFILTER_CATEGORY_2_8814B(x) |                              \
+	 BIT_RXFILTER_CATEGORY_2_8814B(v))
+
+/* 2 REG_RXFILTER_ACTION_2_8814B */
+
+#define BIT_SHIFT_RXFILTER_ACTION_2_8814B 0
+#define BIT_MASK_RXFILTER_ACTION_2_8814B 0xff
+#define BIT_RXFILTER_ACTION_2_8814B(x)                                         \
+	(((x) & BIT_MASK_RXFILTER_ACTION_2_8814B)                              \
+	 << BIT_SHIFT_RXFILTER_ACTION_2_8814B)
+#define BITS_RXFILTER_ACTION_2_8814B                                           \
+	(BIT_MASK_RXFILTER_ACTION_2_8814B << BIT_SHIFT_RXFILTER_ACTION_2_8814B)
+#define BIT_CLEAR_RXFILTER_ACTION_2_8814B(x)                                   \
+	((x) & (~BITS_RXFILTER_ACTION_2_8814B))
+#define BIT_GET_RXFILTER_ACTION_2_8814B(x)                                     \
+	(((x) >> BIT_SHIFT_RXFILTER_ACTION_2_8814B) &                          \
+	 BIT_MASK_RXFILTER_ACTION_2_8814B)
+#define BIT_SET_RXFILTER_ACTION_2_8814B(x, v)                                  \
+	(BIT_CLEAR_RXFILTER_ACTION_2_8814B(x) | BIT_RXFILTER_ACTION_2_8814B(v))
+
+/* 2 REG_RXFILTER_CATEGORY_3_8814B */
+
+#define BIT_SHIFT_RXFILTER_CATEGORY_3_8814B 0
+#define BIT_MASK_RXFILTER_CATEGORY_3_8814B 0xff
+#define BIT_RXFILTER_CATEGORY_3_8814B(x)                                       \
+	(((x) & BIT_MASK_RXFILTER_CATEGORY_3_8814B)                            \
+	 << BIT_SHIFT_RXFILTER_CATEGORY_3_8814B)
+#define BITS_RXFILTER_CATEGORY_3_8814B                                         \
+	(BIT_MASK_RXFILTER_CATEGORY_3_8814B                                    \
+	 << BIT_SHIFT_RXFILTER_CATEGORY_3_8814B)
+#define BIT_CLEAR_RXFILTER_CATEGORY_3_8814B(x)                                 \
+	((x) & (~BITS_RXFILTER_CATEGORY_3_8814B))
+#define BIT_GET_RXFILTER_CATEGORY_3_8814B(x)                                   \
+	(((x) >> BIT_SHIFT_RXFILTER_CATEGORY_3_8814B) &                        \
+	 BIT_MASK_RXFILTER_CATEGORY_3_8814B)
+#define BIT_SET_RXFILTER_CATEGORY_3_8814B(x, v)                                \
+	(BIT_CLEAR_RXFILTER_CATEGORY_3_8814B(x) |                              \
+	 BIT_RXFILTER_CATEGORY_3_8814B(v))
+
+/* 2 REG_RXFILTER_ACTION_3_8814B */
+
+#define BIT_SHIFT_RXFILTER_ACTION_3_8814B 0
+#define BIT_MASK_RXFILTER_ACTION_3_8814B 0xff
+#define BIT_RXFILTER_ACTION_3_8814B(x)                                         \
+	(((x) & BIT_MASK_RXFILTER_ACTION_3_8814B)                              \
+	 << BIT_SHIFT_RXFILTER_ACTION_3_8814B)
+#define BITS_RXFILTER_ACTION_3_8814B                                           \
+	(BIT_MASK_RXFILTER_ACTION_3_8814B << BIT_SHIFT_RXFILTER_ACTION_3_8814B)
+#define BIT_CLEAR_RXFILTER_ACTION_3_8814B(x)                                   \
+	((x) & (~BITS_RXFILTER_ACTION_3_8814B))
+#define BIT_GET_RXFILTER_ACTION_3_8814B(x)                                     \
+	(((x) >> BIT_SHIFT_RXFILTER_ACTION_3_8814B) &                          \
+	 BIT_MASK_RXFILTER_ACTION_3_8814B)
+#define BIT_SET_RXFILTER_ACTION_3_8814B(x, v)                                  \
+	(BIT_CLEAR_RXFILTER_ACTION_3_8814B(x) | BIT_RXFILTER_ACTION_3_8814B(v))
+
+/* 2 REG_RXFLTMAP3_8814B (RX FILTER MAP GROUP 3) */
+#define BIT_MGTFLT15EN_FW_8814B BIT(15)
+#define BIT_MGTFLT14EN_FW_8814B BIT(14)
+#define BIT_MGTFLT13EN_FW_8814B BIT(13)
+#define BIT_MGTFLT12EN_FW_8814B BIT(12)
+#define BIT_MGTFLT11EN_FW_8814B BIT(11)
+#define BIT_MGTFLT10EN_FW_8814B BIT(10)
+#define BIT_MGTFLT9EN_FW_8814B BIT(9)
+#define BIT_MGTFLT8EN_FW_8814B BIT(8)
+#define BIT_MGTFLT7EN_FW_8814B BIT(7)
+#define BIT_MGTFLT6EN_FW_8814B BIT(6)
+#define BIT_MGTFLT5EN_FW_8814B BIT(5)
+#define BIT_MGTFLT4EN_FW_8814B BIT(4)
+#define BIT_MGTFLT3EN_FW_8814B BIT(3)
+#define BIT_MGTFLT2EN_FW_8814B BIT(2)
+#define BIT_MGTFLT1EN_FW_8814B BIT(1)
+#define BIT_MGTFLT0EN_FW_8814B BIT(0)
+
+/* 2 REG_RXFLTMAP4_8814B (RX FILTER MAP GROUP 4) */
+#define BIT_CTRLFLT15EN_FW_8814B BIT(15)
+#define BIT_CTRLFLT14EN_FW_8814B BIT(14)
+#define BIT_CTRLFLT13EN_FW_8814B BIT(13)
+#define BIT_CTRLFLT12EN_FW_8814B BIT(12)
+#define BIT_CTRLFLT11EN_FW_8814B BIT(11)
+#define BIT_CTRLFLT10EN_FW_8814B BIT(10)
+#define BIT_CTRLFLT9EN_FW_8814B BIT(9)
+#define BIT_CTRLFLT8EN_FW_8814B BIT(8)
+#define BIT_CTRLFLT7EN_FW_8814B BIT(7)
+#define BIT_CTRLFLT6EN_FW_8814B BIT(6)
+#define BIT_CTRLFLT5EN_FW_8814B BIT(5)
+#define BIT_CTRLFLT4EN_FW_8814B BIT(4)
+#define BIT_CTRLFLT3EN_FW_8814B BIT(3)
+#define BIT_CTRLFLT2EN_FW_8814B BIT(2)
+#define BIT_CTRLFLT1EN_FW_8814B BIT(1)
+#define BIT_CTRLFLT0EN_FW_8814B BIT(0)
+
+/* 2 REG_RXFLTMAP5_8814B (RX FILTER MAP GROUP 5) */
+#define BIT_DATAFLT15EN_FW_8814B BIT(15)
+#define BIT_DATAFLT14EN_FW_8814B BIT(14)
+#define BIT_DATAFLT13EN_FW_8814B BIT(13)
+#define BIT_DATAFLT12EN_FW_8814B BIT(12)
+#define BIT_DATAFLT11EN_FW_8814B BIT(11)
+#define BIT_DATAFLT10EN_FW_8814B BIT(10)
+#define BIT_DATAFLT9EN_FW_8814B BIT(9)
+#define BIT_DATAFLT8EN_FW_8814B BIT(8)
+#define BIT_DATAFLT7EN_FW_8814B BIT(7)
+#define BIT_DATAFLT6EN_FW_8814B BIT(6)
+#define BIT_DATAFLT5EN_FW_8814B BIT(5)
+#define BIT_DATAFLT4EN_FW_8814B BIT(4)
+#define BIT_DATAFLT3EN_FW_8814B BIT(3)
+#define BIT_DATAFLT2EN_FW_8814B BIT(2)
+#define BIT_DATAFLT1EN_FW_8814B BIT(1)
+#define BIT_DATAFLT0EN_FW_8814B BIT(0)
+
+/* 2 REG_RXFLTMAP6_8814B (RX FILTER MAP GROUP 6) */
+#define BIT_ACTIONFLT15EN_FW_8814B BIT(15)
+#define BIT_ACTIONFLT14EN_FW_8814B BIT(14)
+#define BIT_ACTIONFLT13EN_FW_8814B BIT(13)
+#define BIT_ACTIONFLT12EN_FW_8814B BIT(12)
+#define BIT_ACTIONFLT11EN_FW_8814B BIT(11)
+#define BIT_ACTIONFLT10EN_FW_8814B BIT(10)
+#define BIT_ACTIONFLT9EN_FW_8814B BIT(9)
+#define BIT_ACTIONFLT8EN_FW_8814B BIT(8)
+#define BIT_ACTIONFLT7EN_FW_8814B BIT(7)
+#define BIT_ACTIONFLT6EN_FW_8814B BIT(6)
+#define BIT_ACTIONFLT5EN_FW_8814B BIT(5)
+#define BIT_ACTIONFLT4EN_FW_8814B BIT(4)
+#define BIT_ACTIONFLT3EN_FW_8814B BIT(3)
+#define BIT_ACTIONFLT2EN_FW_8814B BIT(2)
+#define BIT_ACTIONFLT1EN_FW_8814B BIT(1)
+#define BIT_ACTIONFLT0EN_FW_8814B BIT(0)
+
+/* 2 REG_WOW_CTRL_8814B (WAKE ON WLAN CONTROL REGISTER) */
+
+#define BIT_SHIFT_PSF_BSSIDSEL_B2B1_8814B 6
+#define BIT_MASK_PSF_BSSIDSEL_B2B1_8814B 0x3
+#define BIT_PSF_BSSIDSEL_B2B1_8814B(x)                                         \
+	(((x) & BIT_MASK_PSF_BSSIDSEL_B2B1_8814B)                              \
+	 << BIT_SHIFT_PSF_BSSIDSEL_B2B1_8814B)
+#define BITS_PSF_BSSIDSEL_B2B1_8814B                                           \
+	(BIT_MASK_PSF_BSSIDSEL_B2B1_8814B << BIT_SHIFT_PSF_BSSIDSEL_B2B1_8814B)
+#define BIT_CLEAR_PSF_BSSIDSEL_B2B1_8814B(x)                                   \
+	((x) & (~BITS_PSF_BSSIDSEL_B2B1_8814B))
+#define BIT_GET_PSF_BSSIDSEL_B2B1_8814B(x)                                     \
+	(((x) >> BIT_SHIFT_PSF_BSSIDSEL_B2B1_8814B) &                          \
+	 BIT_MASK_PSF_BSSIDSEL_B2B1_8814B)
+#define BIT_SET_PSF_BSSIDSEL_B2B1_8814B(x, v)                                  \
+	(BIT_CLEAR_PSF_BSSIDSEL_B2B1_8814B(x) | BIT_PSF_BSSIDSEL_B2B1_8814B(v))
+
+#define BIT_WOWHCI_8814B BIT(5)
+#define BIT_PSF_BSSIDSEL_B0_8814B BIT(4)
+#define BIT_UWF_8814B BIT(3)
+#define BIT_MAGIC_8814B BIT(2)
+#define BIT_WOWEN_8814B BIT(1)
+#define BIT_FORCE_WAKEUP_8814B BIT(0)
+
+/* 2 REG_NAN_RX_TSF_FILTER_8814B(NAN_RX_TSF_ADDRESS_FILTER) */
+#define BIT_CHK_TSF_TA_8814B BIT(2)
+#define BIT_CHK_TSF_CBSSID_8814B BIT(1)
+#define BIT_CHK_TSF_EN_8814B BIT(0)
+
+/* 2 REG_PS_RX_INFO_8814B (POWER SAVE RX INFORMATION REGISTER) */
+
+#define BIT_SHIFT_PORTSEL__PS_RX_INFO_8814B 5
+#define BIT_MASK_PORTSEL__PS_RX_INFO_8814B 0x7
+#define BIT_PORTSEL__PS_RX_INFO_8814B(x)                                       \
+	(((x) & BIT_MASK_PORTSEL__PS_RX_INFO_8814B)                            \
+	 << BIT_SHIFT_PORTSEL__PS_RX_INFO_8814B)
+#define BITS_PORTSEL__PS_RX_INFO_8814B                                         \
+	(BIT_MASK_PORTSEL__PS_RX_INFO_8814B                                    \
+	 << BIT_SHIFT_PORTSEL__PS_RX_INFO_8814B)
+#define BIT_CLEAR_PORTSEL__PS_RX_INFO_8814B(x)                                 \
+	((x) & (~BITS_PORTSEL__PS_RX_INFO_8814B))
+#define BIT_GET_PORTSEL__PS_RX_INFO_8814B(x)                                   \
+	(((x) >> BIT_SHIFT_PORTSEL__PS_RX_INFO_8814B) &                        \
+	 BIT_MASK_PORTSEL__PS_RX_INFO_8814B)
+#define BIT_SET_PORTSEL__PS_RX_INFO_8814B(x, v)                                \
+	(BIT_CLEAR_PORTSEL__PS_RX_INFO_8814B(x) |                              \
+	 BIT_PORTSEL__PS_RX_INFO_8814B(v))
+
+#define BIT_RXCTRLIN0_8814B BIT(4)
+#define BIT_RXMGTIN0_8814B BIT(3)
+#define BIT_RXDATAIN2_8814B BIT(2)
+#define BIT_RXDATAIN1_8814B BIT(1)
+#define BIT_RXDATAIN0_8814B BIT(0)
+
+/* 2 REG_WMMPS_UAPSD_TID_8814B (WMM POWER SAVE UAPSD TID REGISTER) */
+#define BIT_WMMPS_UAPSD_TID7_8814B BIT(7)
+#define BIT_WMMPS_UAPSD_TID6_8814B BIT(6)
+#define BIT_WMMPS_UAPSD_TID5_8814B BIT(5)
+#define BIT_WMMPS_UAPSD_TID4_8814B BIT(4)
+#define BIT_WMMPS_UAPSD_TID3_8814B BIT(3)
+#define BIT_WMMPS_UAPSD_TID2_8814B BIT(2)
+#define BIT_WMMPS_UAPSD_TID1_8814B BIT(1)
+#define BIT_WMMPS_UAPSD_TID0_8814B BIT(0)
+
+/* 2 REG_LPNAV_CTRL_8814B (LOW POWER NAV CONTROL REGISTER) */
+
+/* 2 REG_WKFMCAM_CMD_8814B (WAKEUP FRAME CAM COMMAND REGISTER) */
+#define BIT_WKFCAM_POLLING_V1_8814B BIT(31)
+#define BIT_WKFCAM_CLR_V1_8814B BIT(30)
+#define BIT_WKFCAM_WE_8814B BIT(16)
+
+#define BIT_SHIFT_WKFCAM_ADDR_V2_8814B 8
+#define BIT_MASK_WKFCAM_ADDR_V2_8814B 0xff
+#define BIT_WKFCAM_ADDR_V2_8814B(x)                                            \
+	(((x) & BIT_MASK_WKFCAM_ADDR_V2_8814B)                                 \
+	 << BIT_SHIFT_WKFCAM_ADDR_V2_8814B)
+#define BITS_WKFCAM_ADDR_V2_8814B                                              \
+	(BIT_MASK_WKFCAM_ADDR_V2_8814B << BIT_SHIFT_WKFCAM_ADDR_V2_8814B)
+#define BIT_CLEAR_WKFCAM_ADDR_V2_8814B(x) ((x) & (~BITS_WKFCAM_ADDR_V2_8814B))
+#define BIT_GET_WKFCAM_ADDR_V2_8814B(x)                                        \
+	(((x) >> BIT_SHIFT_WKFCAM_ADDR_V2_8814B) &                             \
+	 BIT_MASK_WKFCAM_ADDR_V2_8814B)
+#define BIT_SET_WKFCAM_ADDR_V2_8814B(x, v)                                     \
+	(BIT_CLEAR_WKFCAM_ADDR_V2_8814B(x) | BIT_WKFCAM_ADDR_V2_8814B(v))
+
+#define BIT_SHIFT_WKFCAM_CAM_NUM_V1_8814B 0
+#define BIT_MASK_WKFCAM_CAM_NUM_V1_8814B 0xff
+#define BIT_WKFCAM_CAM_NUM_V1_8814B(x)                                         \
+	(((x) & BIT_MASK_WKFCAM_CAM_NUM_V1_8814B)                              \
+	 << BIT_SHIFT_WKFCAM_CAM_NUM_V1_8814B)
+#define BITS_WKFCAM_CAM_NUM_V1_8814B                                           \
+	(BIT_MASK_WKFCAM_CAM_NUM_V1_8814B << BIT_SHIFT_WKFCAM_CAM_NUM_V1_8814B)
+#define BIT_CLEAR_WKFCAM_CAM_NUM_V1_8814B(x)                                   \
+	((x) & (~BITS_WKFCAM_CAM_NUM_V1_8814B))
+#define BIT_GET_WKFCAM_CAM_NUM_V1_8814B(x)                                     \
+	(((x) >> BIT_SHIFT_WKFCAM_CAM_NUM_V1_8814B) &                          \
+	 BIT_MASK_WKFCAM_CAM_NUM_V1_8814B)
+#define BIT_SET_WKFCAM_CAM_NUM_V1_8814B(x, v)                                  \
+	(BIT_CLEAR_WKFCAM_CAM_NUM_V1_8814B(x) | BIT_WKFCAM_CAM_NUM_V1_8814B(v))
+
+/* 2 REG_WKFMCAM_RWD_8814B (WAKEUP FRAME READ/WRITE DATA) */
+
+#define BIT_SHIFT_WKFMCAM_RWD_8814B 0
+#define BIT_MASK_WKFMCAM_RWD_8814B 0xffffffffL
+#define BIT_WKFMCAM_RWD_8814B(x)                                               \
+	(((x) & BIT_MASK_WKFMCAM_RWD_8814B) << BIT_SHIFT_WKFMCAM_RWD_8814B)
+#define BITS_WKFMCAM_RWD_8814B                                                 \
+	(BIT_MASK_WKFMCAM_RWD_8814B << BIT_SHIFT_WKFMCAM_RWD_8814B)
+#define BIT_CLEAR_WKFMCAM_RWD_8814B(x) ((x) & (~BITS_WKFMCAM_RWD_8814B))
+#define BIT_GET_WKFMCAM_RWD_8814B(x)                                           \
+	(((x) >> BIT_SHIFT_WKFMCAM_RWD_8814B) & BIT_MASK_WKFMCAM_RWD_8814B)
+#define BIT_SET_WKFMCAM_RWD_8814B(x, v)                                        \
+	(BIT_CLEAR_WKFMCAM_RWD_8814B(x) | BIT_WKFMCAM_RWD_8814B(v))
+
+/* 2 REG_RXFLTMAP0_8814B (RX FILTER MAP GROUP 0) */
+#define BIT_MGTFLT15EN_8814B BIT(15)
+#define BIT_MGTFLT14EN_8814B BIT(14)
+#define BIT_MGTFLT13EN_8814B BIT(13)
+#define BIT_MGTFLT12EN_8814B BIT(12)
+#define BIT_MGTFLT11EN_8814B BIT(11)
+#define BIT_MGTFLT10EN_8814B BIT(10)
+#define BIT_MGTFLT9EN_8814B BIT(9)
+#define BIT_MGTFLT8EN_8814B BIT(8)
+#define BIT_MGTFLT7EN_8814B BIT(7)
+#define BIT_MGTFLT6EN_8814B BIT(6)
+#define BIT_MGTFLT5EN_8814B BIT(5)
+#define BIT_MGTFLT4EN_8814B BIT(4)
+#define BIT_MGTFLT3EN_8814B BIT(3)
+#define BIT_MGTFLT2EN_8814B BIT(2)
+#define BIT_MGTFLT1EN_8814B BIT(1)
+#define BIT_MGTFLT0EN_8814B BIT(0)
+
+/* 2 REG_RXFLTMAP1_8814B (RX FILTER MAP GROUP 1) */
+#define BIT_CTRLFLT15EN_8814B BIT(15)
+#define BIT_CTRLFLT14EN_8814B BIT(14)
+#define BIT_CTRLFLT13EN_8814B BIT(13)
+#define BIT_CTRLFLT12EN_8814B BIT(12)
+#define BIT_CTRLFLT11EN_8814B BIT(11)
+#define BIT_CTRLFLT10EN_8814B BIT(10)
+#define BIT_CTRLFLT9EN_8814B BIT(9)
+#define BIT_CTRLFLT8EN_8814B BIT(8)
+#define BIT_CTRLFLT7EN_8814B BIT(7)
+#define BIT_CTRLFLT6EN_8814B BIT(6)
+#define BIT_CTRLFLT5EN_8814B BIT(5)
+#define BIT_CTRLFLT4EN_8814B BIT(4)
+#define BIT_CTRLFLT3EN_8814B BIT(3)
+#define BIT_CTRLFLT2EN_8814B BIT(2)
+#define BIT_CTRLFLT1EN_8814B BIT(1)
+#define BIT_CTRLFLT0EN_8814B BIT(0)
+
+/* 2 REG_RXFLTMAP2_8814B (RX FILTER MAP GROUP 2) */
+#define BIT_DATAFLT15EN_8814B BIT(15)
+#define BIT_DATAFLT14EN_8814B BIT(14)
+#define BIT_DATAFLT13EN_8814B BIT(13)
+#define BIT_DATAFLT12EN_8814B BIT(12)
+#define BIT_DATAFLT11EN_8814B BIT(11)
+#define BIT_DATAFLT10EN_8814B BIT(10)
+#define BIT_DATAFLT9EN_8814B BIT(9)
+#define BIT_DATAFLT8EN_8814B BIT(8)
+#define BIT_DATAFLT7EN_8814B BIT(7)
+#define BIT_DATAFLT6EN_8814B BIT(6)
+#define BIT_DATAFLT5EN_8814B BIT(5)
+#define BIT_DATAFLT4EN_8814B BIT(4)
+#define BIT_DATAFLT3EN_8814B BIT(3)
+#define BIT_DATAFLT2EN_8814B BIT(2)
+#define BIT_DATAFLT1EN_8814B BIT(1)
+#define BIT_DATAFLT0EN_8814B BIT(0)
+
+/* 2 REG_RSVD_8814B */
+
+/* 2 REG_BCN_PSR_RPT_8814B (BEACON PARSER REPORT REGISTER) */
+
+#define BIT_SHIFT_DTIM_CNT_8814B 24
+#define BIT_MASK_DTIM_CNT_8814B 0xff
+#define BIT_DTIM_CNT_8814B(x)                                                  \
+	(((x) & BIT_MASK_DTIM_CNT_8814B) << BIT_SHIFT_DTIM_CNT_8814B)
+#define BITS_DTIM_CNT_8814B                                                    \
+	(BIT_MASK_DTIM_CNT_8814B << BIT_SHIFT_DTIM_CNT_8814B)
+#define BIT_CLEAR_DTIM_CNT_8814B(x) ((x) & (~BITS_DTIM_CNT_8814B))
+#define BIT_GET_DTIM_CNT_8814B(x)                                              \
+	(((x) >> BIT_SHIFT_DTIM_CNT_8814B) & BIT_MASK_DTIM_CNT_8814B)
+#define BIT_SET_DTIM_CNT_8814B(x, v)                                           \
+	(BIT_CLEAR_DTIM_CNT_8814B(x) | BIT_DTIM_CNT_8814B(v))
+
+#define BIT_SHIFT_DTIM_PERIOD_8814B 16
+#define BIT_MASK_DTIM_PERIOD_8814B 0xff
+#define BIT_DTIM_PERIOD_8814B(x)                                               \
+	(((x) & BIT_MASK_DTIM_PERIOD_8814B) << BIT_SHIFT_DTIM_PERIOD_8814B)
+#define BITS_DTIM_PERIOD_8814B                                                 \
+	(BIT_MASK_DTIM_PERIOD_8814B << BIT_SHIFT_DTIM_PERIOD_8814B)
+#define BIT_CLEAR_DTIM_PERIOD_8814B(x) ((x) & (~BITS_DTIM_PERIOD_8814B))
+#define BIT_GET_DTIM_PERIOD_8814B(x)                                           \
+	(((x) >> BIT_SHIFT_DTIM_PERIOD_8814B) & BIT_MASK_DTIM_PERIOD_8814B)
+#define BIT_SET_DTIM_PERIOD_8814B(x, v)                                        \
+	(BIT_CLEAR_DTIM_PERIOD_8814B(x) | BIT_DTIM_PERIOD_8814B(v))
+
+#define BIT_DTIM_8814B BIT(15)
+#define BIT_TIM_8814B BIT(14)
+#define BIT_RPT_VALID_8814B BIT(13)
+
+#define BIT_SHIFT_PS_AID_0_8814B 0
+#define BIT_MASK_PS_AID_0_8814B 0x7ff
+#define BIT_PS_AID_0_8814B(x)                                                  \
+	(((x) & BIT_MASK_PS_AID_0_8814B) << BIT_SHIFT_PS_AID_0_8814B)
+#define BITS_PS_AID_0_8814B                                                    \
+	(BIT_MASK_PS_AID_0_8814B << BIT_SHIFT_PS_AID_0_8814B)
+#define BIT_CLEAR_PS_AID_0_8814B(x) ((x) & (~BITS_PS_AID_0_8814B))
+#define BIT_GET_PS_AID_0_8814B(x)                                              \
+	(((x) >> BIT_SHIFT_PS_AID_0_8814B) & BIT_MASK_PS_AID_0_8814B)
+#define BIT_SET_PS_AID_0_8814B(x, v)                                           \
+	(BIT_CLEAR_PS_AID_0_8814B(x) | BIT_PS_AID_0_8814B(v))
+
+/* 2 REG_FLC_RPC_8814B (FW LPS CONDITION -- RX PKT COUNTER) */
+
+#define BIT_SHIFT_FLC_RPC_8814B 0
+#define BIT_MASK_FLC_RPC_8814B 0xff
+#define BIT_FLC_RPC_8814B(x)                                                   \
+	(((x) & BIT_MASK_FLC_RPC_8814B) << BIT_SHIFT_FLC_RPC_8814B)
+#define BITS_FLC_RPC_8814B (BIT_MASK_FLC_RPC_8814B << BIT_SHIFT_FLC_RPC_8814B)
+#define BIT_CLEAR_FLC_RPC_8814B(x) ((x) & (~BITS_FLC_RPC_8814B))
+#define BIT_GET_FLC_RPC_8814B(x)                                               \
+	(((x) >> BIT_SHIFT_FLC_RPC_8814B) & BIT_MASK_FLC_RPC_8814B)
+#define BIT_SET_FLC_RPC_8814B(x, v)                                            \
+	(BIT_CLEAR_FLC_RPC_8814B(x) | BIT_FLC_RPC_8814B(v))
+
+/* 2 REG_FLC_RPCT_8814B (FLC_RPC THRESHOLD) */
+
+#define BIT_SHIFT_FLC_RPCT_8814B 0
+#define BIT_MASK_FLC_RPCT_8814B 0xff
+#define BIT_FLC_RPCT_8814B(x)                                                  \
+	(((x) & BIT_MASK_FLC_RPCT_8814B) << BIT_SHIFT_FLC_RPCT_8814B)
+#define BITS_FLC_RPCT_8814B                                                    \
+	(BIT_MASK_FLC_RPCT_8814B << BIT_SHIFT_FLC_RPCT_8814B)
+#define BIT_CLEAR_FLC_RPCT_8814B(x) ((x) & (~BITS_FLC_RPCT_8814B))
+#define BIT_GET_FLC_RPCT_8814B(x)                                              \
+	(((x) >> BIT_SHIFT_FLC_RPCT_8814B) & BIT_MASK_FLC_RPCT_8814B)
+#define BIT_SET_FLC_RPCT_8814B(x, v)                                           \
+	(BIT_CLEAR_FLC_RPCT_8814B(x) | BIT_FLC_RPCT_8814B(v))
+
+/* 2 REG_FLC_PTS_8814B (PKT TYPE SELECTION OF FLC_RPC T) */
+#define BIT_CMF_8814B BIT(2)
+#define BIT_CCF_8814B BIT(1)
+#define BIT_CDF_8814B BIT(0)
+
+/* 2 REG_FLC_TRPC_8814B (TIMER OF FLC_RPC) */
+#define BIT_FLC_RPCT_V1_8814B BIT(7)
+#define BIT_MODE_8814B BIT(6)
+
+#define BIT_SHIFT_TRPCD_8814B 0
+#define BIT_MASK_TRPCD_8814B 0x3f
+#define BIT_TRPCD_8814B(x)                                                     \
+	(((x) & BIT_MASK_TRPCD_8814B) << BIT_SHIFT_TRPCD_8814B)
+#define BITS_TRPCD_8814B (BIT_MASK_TRPCD_8814B << BIT_SHIFT_TRPCD_8814B)
+#define BIT_CLEAR_TRPCD_8814B(x) ((x) & (~BITS_TRPCD_8814B))
+#define BIT_GET_TRPCD_8814B(x)                                                 \
+	(((x) >> BIT_SHIFT_TRPCD_8814B) & BIT_MASK_TRPCD_8814B)
+#define BIT_SET_TRPCD_8814B(x, v)                                              \
+	(BIT_CLEAR_TRPCD_8814B(x) | BIT_TRPCD_8814B(v))
+
+/* 2 REG_RXPKTMON_CTRL_8814B */
+
+#define BIT_SHIFT_RXBKQPKT_SEQ_8814B 20
+#define BIT_MASK_RXBKQPKT_SEQ_8814B 0xf
+#define BIT_RXBKQPKT_SEQ_8814B(x)                                              \
+	(((x) & BIT_MASK_RXBKQPKT_SEQ_8814B) << BIT_SHIFT_RXBKQPKT_SEQ_8814B)
+#define BITS_RXBKQPKT_SEQ_8814B                                                \
+	(BIT_MASK_RXBKQPKT_SEQ_8814B << BIT_SHIFT_RXBKQPKT_SEQ_8814B)
+#define BIT_CLEAR_RXBKQPKT_SEQ_8814B(x) ((x) & (~BITS_RXBKQPKT_SEQ_8814B))
+#define BIT_GET_RXBKQPKT_SEQ_8814B(x)                                          \
+	(((x) >> BIT_SHIFT_RXBKQPKT_SEQ_8814B) & BIT_MASK_RXBKQPKT_SEQ_8814B)
+#define BIT_SET_RXBKQPKT_SEQ_8814B(x, v)                                       \
+	(BIT_CLEAR_RXBKQPKT_SEQ_8814B(x) | BIT_RXBKQPKT_SEQ_8814B(v))
+
+#define BIT_SHIFT_RXBEQPKT_SEQ_8814B 16
+#define BIT_MASK_RXBEQPKT_SEQ_8814B 0xf
+#define BIT_RXBEQPKT_SEQ_8814B(x)                                              \
+	(((x) & BIT_MASK_RXBEQPKT_SEQ_8814B) << BIT_SHIFT_RXBEQPKT_SEQ_8814B)
+#define BITS_RXBEQPKT_SEQ_8814B                                                \
+	(BIT_MASK_RXBEQPKT_SEQ_8814B << BIT_SHIFT_RXBEQPKT_SEQ_8814B)
+#define BIT_CLEAR_RXBEQPKT_SEQ_8814B(x) ((x) & (~BITS_RXBEQPKT_SEQ_8814B))
+#define BIT_GET_RXBEQPKT_SEQ_8814B(x)                                          \
+	(((x) >> BIT_SHIFT_RXBEQPKT_SEQ_8814B) & BIT_MASK_RXBEQPKT_SEQ_8814B)
+#define BIT_SET_RXBEQPKT_SEQ_8814B(x, v)                                       \
+	(BIT_CLEAR_RXBEQPKT_SEQ_8814B(x) | BIT_RXBEQPKT_SEQ_8814B(v))
+
+#define BIT_SHIFT_RXVIQPKT_SEQ_8814B 12
+#define BIT_MASK_RXVIQPKT_SEQ_8814B 0xf
+#define BIT_RXVIQPKT_SEQ_8814B(x)                                              \
+	(((x) & BIT_MASK_RXVIQPKT_SEQ_8814B) << BIT_SHIFT_RXVIQPKT_SEQ_8814B)
+#define BITS_RXVIQPKT_SEQ_8814B                                                \
+	(BIT_MASK_RXVIQPKT_SEQ_8814B << BIT_SHIFT_RXVIQPKT_SEQ_8814B)
+#define BIT_CLEAR_RXVIQPKT_SEQ_8814B(x) ((x) & (~BITS_RXVIQPKT_SEQ_8814B))
+#define BIT_GET_RXVIQPKT_SEQ_8814B(x)                                          \
+	(((x) >> BIT_SHIFT_RXVIQPKT_SEQ_8814B) & BIT_MASK_RXVIQPKT_SEQ_8814B)
+#define BIT_SET_RXVIQPKT_SEQ_8814B(x, v)                                       \
+	(BIT_CLEAR_RXVIQPKT_SEQ_8814B(x) | BIT_RXVIQPKT_SEQ_8814B(v))
+
+#define BIT_SHIFT_RXVOQPKT_SEQ_8814B 8
+#define BIT_MASK_RXVOQPKT_SEQ_8814B 0xf
+#define BIT_RXVOQPKT_SEQ_8814B(x)                                              \
+	(((x) & BIT_MASK_RXVOQPKT_SEQ_8814B) << BIT_SHIFT_RXVOQPKT_SEQ_8814B)
+#define BITS_RXVOQPKT_SEQ_8814B                                                \
+	(BIT_MASK_RXVOQPKT_SEQ_8814B << BIT_SHIFT_RXVOQPKT_SEQ_8814B)
+#define BIT_CLEAR_RXVOQPKT_SEQ_8814B(x) ((x) & (~BITS_RXVOQPKT_SEQ_8814B))
+#define BIT_GET_RXVOQPKT_SEQ_8814B(x)                                          \
+	(((x) >> BIT_SHIFT_RXVOQPKT_SEQ_8814B) & BIT_MASK_RXVOQPKT_SEQ_8814B)
+#define BIT_SET_RXVOQPKT_SEQ_8814B(x, v)                                       \
+	(BIT_CLEAR_RXVOQPKT_SEQ_8814B(x) | BIT_RXVOQPKT_SEQ_8814B(v))
+
+#define BIT_RXBKQPKT_ERR_8814B BIT(7)
+#define BIT_RXBEQPKT_ERR_8814B BIT(6)
+#define BIT_RXVIQPKT_ERR_8814B BIT(5)
+#define BIT_RXVOQPKT_ERR_8814B BIT(4)
+#define BIT_RXDMA_MON_EN_8814B BIT(2)
+#define BIT_RXPKT_MON_RST_8814B BIT(1)
+#define BIT_RXPKT_MON_EN_8814B BIT(0)
+
+/* 2 REG_STATE_MON_8814B */
+
+#define BIT_SHIFT_STATE_SEL_8814B 24
+#define BIT_MASK_STATE_SEL_8814B 0x1f
+#define BIT_STATE_SEL_8814B(x)                                                 \
+	(((x) & BIT_MASK_STATE_SEL_8814B) << BIT_SHIFT_STATE_SEL_8814B)
+#define BITS_STATE_SEL_8814B                                                   \
+	(BIT_MASK_STATE_SEL_8814B << BIT_SHIFT_STATE_SEL_8814B)
+#define BIT_CLEAR_STATE_SEL_8814B(x) ((x) & (~BITS_STATE_SEL_8814B))
+#define BIT_GET_STATE_SEL_8814B(x)                                             \
+	(((x) >> BIT_SHIFT_STATE_SEL_8814B) & BIT_MASK_STATE_SEL_8814B)
+#define BIT_SET_STATE_SEL_8814B(x, v)                                          \
+	(BIT_CLEAR_STATE_SEL_8814B(x) | BIT_STATE_SEL_8814B(v))
+
+#define BIT_SHIFT_STATE_INFO_8814B 8
+#define BIT_MASK_STATE_INFO_8814B 0xff
+#define BIT_STATE_INFO_8814B(x)                                                \
+	(((x) & BIT_MASK_STATE_INFO_8814B) << BIT_SHIFT_STATE_INFO_8814B)
+#define BITS_STATE_INFO_8814B                                                  \
+	(BIT_MASK_STATE_INFO_8814B << BIT_SHIFT_STATE_INFO_8814B)
+#define BIT_CLEAR_STATE_INFO_8814B(x) ((x) & (~BITS_STATE_INFO_8814B))
+#define BIT_GET_STATE_INFO_8814B(x)                                            \
+	(((x) >> BIT_SHIFT_STATE_INFO_8814B) & BIT_MASK_STATE_INFO_8814B)
+#define BIT_SET_STATE_INFO_8814B(x, v)                                         \
+	(BIT_CLEAR_STATE_INFO_8814B(x) | BIT_STATE_INFO_8814B(v))
+
+#define BIT_UPD_NXT_STATE_8814B BIT(7)
+
+#define BIT_SHIFT_CUR_STATE_8814B 0
+#define BIT_MASK_CUR_STATE_8814B 0x7f
+#define BIT_CUR_STATE_8814B(x)                                                 \
+	(((x) & BIT_MASK_CUR_STATE_8814B) << BIT_SHIFT_CUR_STATE_8814B)
+#define BITS_CUR_STATE_8814B                                                   \
+	(BIT_MASK_CUR_STATE_8814B << BIT_SHIFT_CUR_STATE_8814B)
+#define BIT_CLEAR_CUR_STATE_8814B(x) ((x) & (~BITS_CUR_STATE_8814B))
+#define BIT_GET_CUR_STATE_8814B(x)                                             \
+	(((x) >> BIT_SHIFT_CUR_STATE_8814B) & BIT_MASK_CUR_STATE_8814B)
+#define BIT_SET_CUR_STATE_8814B(x, v)                                          \
+	(BIT_CLEAR_CUR_STATE_8814B(x) | BIT_CUR_STATE_8814B(v))
+
+/* 2 REG_ERROR_MON_8814B */
+#define BIT_CSIRPT_LEN_BB_MORE_THAN_MAC_8814B BIT(23)
+#define BIT_CSI_CHKSUM_ERROR_8814B BIT(22)
+#define BIT_MACRX_ERR_5_8814B BIT(21)
+#define BIT_MACRX_ERR_4_8814B BIT(20)
+#define BIT_MACRX_ERR_3_8814B BIT(19)
+#define BIT_MACRX_ERR_2_8814B BIT(18)
+#define BIT_MACRX_ERR_1_8814B BIT(17)
+#define BIT_MACRX_ERR_0_8814B BIT(16)
+#define BIT_WMAC_PRETX_ERRHDL_EN_8814B BIT(15)
+#define BIT_MACTX_ERR_5_8814B BIT(5)
+#define BIT_MACTX_ERR_4_8814B BIT(4)
+#define BIT_MACTX_ERR_3_8814B BIT(3)
+#define BIT_MACTX_ERR_2_8814B BIT(2)
+#define BIT_MACTX_ERR_1_8814B BIT(1)
+#define BIT_MACTX_ERR_0_8814B BIT(0)
+
+/* 2 REG_SEARCH_MACID_8814B */
+#define BIT_EN_TXRPTBUF_CLK_8814B BIT(31)
+#define BIT_WMAC_SRCH_FIFOFULL_8814B BIT(15)
+#define BIT_DIS_INFOSRCH_8814B BIT(14)
+#define BIT_DISABLE_B0_8814B BIT(13)
+
+#define BIT_SHIFT_INFO_ADDR_OFFSET_8814B 0
+#define BIT_MASK_INFO_ADDR_OFFSET_8814B 0x1fff
+#define BIT_INFO_ADDR_OFFSET_8814B(x)                                          \
+	(((x) & BIT_MASK_INFO_ADDR_OFFSET_8814B)                               \
+	 << BIT_SHIFT_INFO_ADDR_OFFSET_8814B)
+#define BITS_INFO_ADDR_OFFSET_8814B                                            \
+	(BIT_MASK_INFO_ADDR_OFFSET_8814B << BIT_SHIFT_INFO_ADDR_OFFSET_8814B)
+#define BIT_CLEAR_INFO_ADDR_OFFSET_8814B(x)                                    \
+	((x) & (~BITS_INFO_ADDR_OFFSET_8814B))
+#define BIT_GET_INFO_ADDR_OFFSET_8814B(x)                                      \
+	(((x) >> BIT_SHIFT_INFO_ADDR_OFFSET_8814B) &                           \
+	 BIT_MASK_INFO_ADDR_OFFSET_8814B)
+#define BIT_SET_INFO_ADDR_OFFSET_8814B(x, v)                                   \
+	(BIT_CLEAR_INFO_ADDR_OFFSET_8814B(x) | BIT_INFO_ADDR_OFFSET_8814B(v))
+
+/* 2 REG_BT_COEX_TABLE_8814B (BT-COEXISTENCE CONTROL REGISTER) */
+
+#define BIT_SHIFT_COEX_TABLE_1_8814B 0
+#define BIT_MASK_COEX_TABLE_1_8814B 0xffffffffL
+#define BIT_COEX_TABLE_1_8814B(x)                                              \
+	(((x) & BIT_MASK_COEX_TABLE_1_8814B) << BIT_SHIFT_COEX_TABLE_1_8814B)
+#define BITS_COEX_TABLE_1_8814B                                                \
+	(BIT_MASK_COEX_TABLE_1_8814B << BIT_SHIFT_COEX_TABLE_1_8814B)
+#define BIT_CLEAR_COEX_TABLE_1_8814B(x) ((x) & (~BITS_COEX_TABLE_1_8814B))
+#define BIT_GET_COEX_TABLE_1_8814B(x)                                          \
+	(((x) >> BIT_SHIFT_COEX_TABLE_1_8814B) & BIT_MASK_COEX_TABLE_1_8814B)
+#define BIT_SET_COEX_TABLE_1_8814B(x, v)                                       \
+	(BIT_CLEAR_COEX_TABLE_1_8814B(x) | BIT_COEX_TABLE_1_8814B(v))
+
+/* 2 REG_BT_COEX_TABLE2_8814B (BT-COEXISTENCE CONTROL REGISTER) */
+
+#define BIT_SHIFT_COEX_TABLE_2_8814B 0
+#define BIT_MASK_COEX_TABLE_2_8814B 0xffffffffL
+#define BIT_COEX_TABLE_2_8814B(x)                                              \
+	(((x) & BIT_MASK_COEX_TABLE_2_8814B) << BIT_SHIFT_COEX_TABLE_2_8814B)
+#define BITS_COEX_TABLE_2_8814B                                                \
+	(BIT_MASK_COEX_TABLE_2_8814B << BIT_SHIFT_COEX_TABLE_2_8814B)
+#define BIT_CLEAR_COEX_TABLE_2_8814B(x) ((x) & (~BITS_COEX_TABLE_2_8814B))
+#define BIT_GET_COEX_TABLE_2_8814B(x)                                          \
+	(((x) >> BIT_SHIFT_COEX_TABLE_2_8814B) & BIT_MASK_COEX_TABLE_2_8814B)
+#define BIT_SET_COEX_TABLE_2_8814B(x, v)                                       \
+	(BIT_CLEAR_COEX_TABLE_2_8814B(x) | BIT_COEX_TABLE_2_8814B(v))
+
+/* 2 REG_BT_COEX_BREAK_TABLE_8814B (BT-COEXISTENCE CONTROL REGISTER) */
+
+#define BIT_SHIFT_BREAK_TABLE_2_8814B 16
+#define BIT_MASK_BREAK_TABLE_2_8814B 0xffff
+#define BIT_BREAK_TABLE_2_8814B(x)                                             \
+	(((x) & BIT_MASK_BREAK_TABLE_2_8814B) << BIT_SHIFT_BREAK_TABLE_2_8814B)
+#define BITS_BREAK_TABLE_2_8814B                                               \
+	(BIT_MASK_BREAK_TABLE_2_8814B << BIT_SHIFT_BREAK_TABLE_2_8814B)
+#define BIT_CLEAR_BREAK_TABLE_2_8814B(x) ((x) & (~BITS_BREAK_TABLE_2_8814B))
+#define BIT_GET_BREAK_TABLE_2_8814B(x)                                         \
+	(((x) >> BIT_SHIFT_BREAK_TABLE_2_8814B) & BIT_MASK_BREAK_TABLE_2_8814B)
+#define BIT_SET_BREAK_TABLE_2_8814B(x, v)                                      \
+	(BIT_CLEAR_BREAK_TABLE_2_8814B(x) | BIT_BREAK_TABLE_2_8814B(v))
+
+#define BIT_SHIFT_BREAK_TABLE_1_8814B 0
+#define BIT_MASK_BREAK_TABLE_1_8814B 0xffff
+#define BIT_BREAK_TABLE_1_8814B(x)                                             \
+	(((x) & BIT_MASK_BREAK_TABLE_1_8814B) << BIT_SHIFT_BREAK_TABLE_1_8814B)
+#define BITS_BREAK_TABLE_1_8814B                                               \
+	(BIT_MASK_BREAK_TABLE_1_8814B << BIT_SHIFT_BREAK_TABLE_1_8814B)
+#define BIT_CLEAR_BREAK_TABLE_1_8814B(x) ((x) & (~BITS_BREAK_TABLE_1_8814B))
+#define BIT_GET_BREAK_TABLE_1_8814B(x)                                         \
+	(((x) >> BIT_SHIFT_BREAK_TABLE_1_8814B) & BIT_MASK_BREAK_TABLE_1_8814B)
+#define BIT_SET_BREAK_TABLE_1_8814B(x, v)                                      \
+	(BIT_CLEAR_BREAK_TABLE_1_8814B(x) | BIT_BREAK_TABLE_1_8814B(v))
+
+/* 2 REG_BT_COEX_TABLE_H_8814B (BT-COEXISTENCE CONTROL REGISTER) */
+#define BIT_PRI_MASK_RX_RESP_V1_8814B BIT(30)
+#define BIT_PRI_MASK_RXOFDM_V1_8814B BIT(29)
+#define BIT_PRI_MASK_RXCCK_V1_8814B BIT(28)
+
+#define BIT_SHIFT_PRI_MASK_TXAC_8814B 21
+#define BIT_MASK_PRI_MASK_TXAC_8814B 0x7f
+#define BIT_PRI_MASK_TXAC_8814B(x)                                             \
+	(((x) & BIT_MASK_PRI_MASK_TXAC_8814B) << BIT_SHIFT_PRI_MASK_TXAC_8814B)
+#define BITS_PRI_MASK_TXAC_8814B                                               \
+	(BIT_MASK_PRI_MASK_TXAC_8814B << BIT_SHIFT_PRI_MASK_TXAC_8814B)
+#define BIT_CLEAR_PRI_MASK_TXAC_8814B(x) ((x) & (~BITS_PRI_MASK_TXAC_8814B))
+#define BIT_GET_PRI_MASK_TXAC_8814B(x)                                         \
+	(((x) >> BIT_SHIFT_PRI_MASK_TXAC_8814B) & BIT_MASK_PRI_MASK_TXAC_8814B)
+#define BIT_SET_PRI_MASK_TXAC_8814B(x, v)                                      \
+	(BIT_CLEAR_PRI_MASK_TXAC_8814B(x) | BIT_PRI_MASK_TXAC_8814B(v))
+
+#define BIT_SHIFT_PRI_MASK_NAV_8814B 13
+#define BIT_MASK_PRI_MASK_NAV_8814B 0xff
+#define BIT_PRI_MASK_NAV_8814B(x)                                              \
+	(((x) & BIT_MASK_PRI_MASK_NAV_8814B) << BIT_SHIFT_PRI_MASK_NAV_8814B)
+#define BITS_PRI_MASK_NAV_8814B                                                \
+	(BIT_MASK_PRI_MASK_NAV_8814B << BIT_SHIFT_PRI_MASK_NAV_8814B)
+#define BIT_CLEAR_PRI_MASK_NAV_8814B(x) ((x) & (~BITS_PRI_MASK_NAV_8814B))
+#define BIT_GET_PRI_MASK_NAV_8814B(x)                                          \
+	(((x) >> BIT_SHIFT_PRI_MASK_NAV_8814B) & BIT_MASK_PRI_MASK_NAV_8814B)
+#define BIT_SET_PRI_MASK_NAV_8814B(x, v)                                       \
+	(BIT_CLEAR_PRI_MASK_NAV_8814B(x) | BIT_PRI_MASK_NAV_8814B(v))
+
+#define BIT_PRI_MASK_CCK_V1_8814B BIT(12)
+#define BIT_PRI_MASK_OFDM_V1_8814B BIT(11)
+#define BIT_PRI_MASK_RTY_V1_8814B BIT(10)
+
+#define BIT_SHIFT_PRI_MASK_NUM_8814B 6
+#define BIT_MASK_PRI_MASK_NUM_8814B 0xf
+#define BIT_PRI_MASK_NUM_8814B(x)                                              \
+	(((x) & BIT_MASK_PRI_MASK_NUM_8814B) << BIT_SHIFT_PRI_MASK_NUM_8814B)
+#define BITS_PRI_MASK_NUM_8814B                                                \
+	(BIT_MASK_PRI_MASK_NUM_8814B << BIT_SHIFT_PRI_MASK_NUM_8814B)
+#define BIT_CLEAR_PRI_MASK_NUM_8814B(x) ((x) & (~BITS_PRI_MASK_NUM_8814B))
+#define BIT_GET_PRI_MASK_NUM_8814B(x)                                          \
+	(((x) >> BIT_SHIFT_PRI_MASK_NUM_8814B) & BIT_MASK_PRI_MASK_NUM_8814B)
+#define BIT_SET_PRI_MASK_NUM_8814B(x, v)                                       \
+	(BIT_CLEAR_PRI_MASK_NUM_8814B(x) | BIT_PRI_MASK_NUM_8814B(v))
+
+#define BIT_SHIFT_PRI_MASK_TYPE_8814B 2
+#define BIT_MASK_PRI_MASK_TYPE_8814B 0xf
+#define BIT_PRI_MASK_TYPE_8814B(x)                                             \
+	(((x) & BIT_MASK_PRI_MASK_TYPE_8814B) << BIT_SHIFT_PRI_MASK_TYPE_8814B)
+#define BITS_PRI_MASK_TYPE_8814B                                               \
+	(BIT_MASK_PRI_MASK_TYPE_8814B << BIT_SHIFT_PRI_MASK_TYPE_8814B)
+#define BIT_CLEAR_PRI_MASK_TYPE_8814B(x) ((x) & (~BITS_PRI_MASK_TYPE_8814B))
+#define BIT_GET_PRI_MASK_TYPE_8814B(x)                                         \
+	(((x) >> BIT_SHIFT_PRI_MASK_TYPE_8814B) & BIT_MASK_PRI_MASK_TYPE_8814B)
+#define BIT_SET_PRI_MASK_TYPE_8814B(x, v)                                      \
+	(BIT_CLEAR_PRI_MASK_TYPE_8814B(x) | BIT_PRI_MASK_TYPE_8814B(v))
+
+#define BIT_OOB_V1_8814B BIT(1)
+#define BIT_ANT_SEL_V1_8814B BIT(0)
+
+/* 2 REG_RXCMD_0_8814B */
+#define BIT_RXCMD_EN_8814B BIT(31)
+
+#define BIT_SHIFT_RXCMD_INFO_8814B 0
+#define BIT_MASK_RXCMD_INFO_8814B 0x7fffffffL
+#define BIT_RXCMD_INFO_8814B(x)                                                \
+	(((x) & BIT_MASK_RXCMD_INFO_8814B) << BIT_SHIFT_RXCMD_INFO_8814B)
+#define BITS_RXCMD_INFO_8814B                                                  \
+	(BIT_MASK_RXCMD_INFO_8814B << BIT_SHIFT_RXCMD_INFO_8814B)
+#define BIT_CLEAR_RXCMD_INFO_8814B(x) ((x) & (~BITS_RXCMD_INFO_8814B))
+#define BIT_GET_RXCMD_INFO_8814B(x)                                            \
+	(((x) >> BIT_SHIFT_RXCMD_INFO_8814B) & BIT_MASK_RXCMD_INFO_8814B)
+#define BIT_SET_RXCMD_INFO_8814B(x, v)                                         \
+	(BIT_CLEAR_RXCMD_INFO_8814B(x) | BIT_RXCMD_INFO_8814B(v))
+
+/* 2 REG_RXCMD_1_8814B */
+
+#define BIT_SHIFT_CSI_RADDR_LATCH_8814B 24
+#define BIT_MASK_CSI_RADDR_LATCH_8814B 0xff
+#define BIT_CSI_RADDR_LATCH_8814B(x)                                           \
+	(((x) & BIT_MASK_CSI_RADDR_LATCH_8814B)                                \
+	 << BIT_SHIFT_CSI_RADDR_LATCH_8814B)
+#define BITS_CSI_RADDR_LATCH_8814B                                             \
+	(BIT_MASK_CSI_RADDR_LATCH_8814B << BIT_SHIFT_CSI_RADDR_LATCH_8814B)
+#define BIT_CLEAR_CSI_RADDR_LATCH_8814B(x) ((x) & (~BITS_CSI_RADDR_LATCH_8814B))
+#define BIT_GET_CSI_RADDR_LATCH_8814B(x)                                       \
+	(((x) >> BIT_SHIFT_CSI_RADDR_LATCH_8814B) &                            \
+	 BIT_MASK_CSI_RADDR_LATCH_8814B)
+#define BIT_SET_CSI_RADDR_LATCH_8814B(x, v)                                    \
+	(BIT_CLEAR_CSI_RADDR_LATCH_8814B(x) | BIT_CSI_RADDR_LATCH_8814B(v))
+
+#define BIT_SHIFT_CSI_WADDR_LATCH_8814B 16
+#define BIT_MASK_CSI_WADDR_LATCH_8814B 0xff
+#define BIT_CSI_WADDR_LATCH_8814B(x)                                           \
+	(((x) & BIT_MASK_CSI_WADDR_LATCH_8814B)                                \
+	 << BIT_SHIFT_CSI_WADDR_LATCH_8814B)
+#define BITS_CSI_WADDR_LATCH_8814B                                             \
+	(BIT_MASK_CSI_WADDR_LATCH_8814B << BIT_SHIFT_CSI_WADDR_LATCH_8814B)
+#define BIT_CLEAR_CSI_WADDR_LATCH_8814B(x) ((x) & (~BITS_CSI_WADDR_LATCH_8814B))
+#define BIT_GET_CSI_WADDR_LATCH_8814B(x)                                       \
+	(((x) >> BIT_SHIFT_CSI_WADDR_LATCH_8814B) &                            \
+	 BIT_MASK_CSI_WADDR_LATCH_8814B)
+#define BIT_SET_CSI_WADDR_LATCH_8814B(x, v)                                    \
+	(BIT_CLEAR_CSI_WADDR_LATCH_8814B(x) | BIT_CSI_WADDR_LATCH_8814B(v))
+
+#define BIT_SHIFT_RXCMD_PRD_8814B 0
+#define BIT_MASK_RXCMD_PRD_8814B 0xffff
+#define BIT_RXCMD_PRD_8814B(x)                                                 \
+	(((x) & BIT_MASK_RXCMD_PRD_8814B) << BIT_SHIFT_RXCMD_PRD_8814B)
+#define BITS_RXCMD_PRD_8814B                                                   \
+	(BIT_MASK_RXCMD_PRD_8814B << BIT_SHIFT_RXCMD_PRD_8814B)
+#define BIT_CLEAR_RXCMD_PRD_8814B(x) ((x) & (~BITS_RXCMD_PRD_8814B))
+#define BIT_GET_RXCMD_PRD_8814B(x)                                             \
+	(((x) >> BIT_SHIFT_RXCMD_PRD_8814B) & BIT_MASK_RXCMD_PRD_8814B)
+#define BIT_SET_RXCMD_PRD_8814B(x, v)                                          \
+	(BIT_CLEAR_RXCMD_PRD_8814B(x) | BIT_RXCMD_PRD_8814B(v))
+
+/* 2 REG_WMAC_RESP_TXINFO_8814B (RESPONSE TXINFO REGISTER) */
+
+#define BIT_SHIFT_WMAC_RESP_MFB_8814B 25
+#define BIT_MASK_WMAC_RESP_MFB_8814B 0x7f
+#define BIT_WMAC_RESP_MFB_8814B(x)                                             \
+	(((x) & BIT_MASK_WMAC_RESP_MFB_8814B) << BIT_SHIFT_WMAC_RESP_MFB_8814B)
+#define BITS_WMAC_RESP_MFB_8814B                                               \
+	(BIT_MASK_WMAC_RESP_MFB_8814B << BIT_SHIFT_WMAC_RESP_MFB_8814B)
+#define BIT_CLEAR_WMAC_RESP_MFB_8814B(x) ((x) & (~BITS_WMAC_RESP_MFB_8814B))
+#define BIT_GET_WMAC_RESP_MFB_8814B(x)                                         \
+	(((x) >> BIT_SHIFT_WMAC_RESP_MFB_8814B) & BIT_MASK_WMAC_RESP_MFB_8814B)
+#define BIT_SET_WMAC_RESP_MFB_8814B(x, v)                                      \
+	(BIT_CLEAR_WMAC_RESP_MFB_8814B(x) | BIT_WMAC_RESP_MFB_8814B(v))
+
+#define BIT_SHIFT_WMAC_ANTINF_SEL_8814B 23
+#define BIT_MASK_WMAC_ANTINF_SEL_8814B 0x3
+#define BIT_WMAC_ANTINF_SEL_8814B(x)                                           \
+	(((x) & BIT_MASK_WMAC_ANTINF_SEL_8814B)                                \
+	 << BIT_SHIFT_WMAC_ANTINF_SEL_8814B)
+#define BITS_WMAC_ANTINF_SEL_8814B                                             \
+	(BIT_MASK_WMAC_ANTINF_SEL_8814B << BIT_SHIFT_WMAC_ANTINF_SEL_8814B)
+#define BIT_CLEAR_WMAC_ANTINF_SEL_8814B(x) ((x) & (~BITS_WMAC_ANTINF_SEL_8814B))
+#define BIT_GET_WMAC_ANTINF_SEL_8814B(x)                                       \
+	(((x) >> BIT_SHIFT_WMAC_ANTINF_SEL_8814B) &                            \
+	 BIT_MASK_WMAC_ANTINF_SEL_8814B)
+#define BIT_SET_WMAC_ANTINF_SEL_8814B(x, v)                                    \
+	(BIT_CLEAR_WMAC_ANTINF_SEL_8814B(x) | BIT_WMAC_ANTINF_SEL_8814B(v))
+
+#define BIT_SHIFT_WMAC_ANTSEL_SEL_8814B 21
+#define BIT_MASK_WMAC_ANTSEL_SEL_8814B 0x3
+#define BIT_WMAC_ANTSEL_SEL_8814B(x)                                           \
+	(((x) & BIT_MASK_WMAC_ANTSEL_SEL_8814B)                                \
+	 << BIT_SHIFT_WMAC_ANTSEL_SEL_8814B)
+#define BITS_WMAC_ANTSEL_SEL_8814B                                             \
+	(BIT_MASK_WMAC_ANTSEL_SEL_8814B << BIT_SHIFT_WMAC_ANTSEL_SEL_8814B)
+#define BIT_CLEAR_WMAC_ANTSEL_SEL_8814B(x) ((x) & (~BITS_WMAC_ANTSEL_SEL_8814B))
+#define BIT_GET_WMAC_ANTSEL_SEL_8814B(x)                                       \
+	(((x) >> BIT_SHIFT_WMAC_ANTSEL_SEL_8814B) &                            \
+	 BIT_MASK_WMAC_ANTSEL_SEL_8814B)
+#define BIT_SET_WMAC_ANTSEL_SEL_8814B(x, v)                                    \
+	(BIT_CLEAR_WMAC_ANTSEL_SEL_8814B(x) | BIT_WMAC_ANTSEL_SEL_8814B(v))
+
+#define BIT_SHIFT_WMAC_RESP_TXPOWER_OFFSET_TYPE_8814B 18
+#define BIT_MASK_WMAC_RESP_TXPOWER_OFFSET_TYPE_8814B 0x3
+#define BIT_WMAC_RESP_TXPOWER_OFFSET_TYPE_8814B(x)                             \
+	(((x) & BIT_MASK_WMAC_RESP_TXPOWER_OFFSET_TYPE_8814B)                  \
+	 << BIT_SHIFT_WMAC_RESP_TXPOWER_OFFSET_TYPE_8814B)
+#define BITS_WMAC_RESP_TXPOWER_OFFSET_TYPE_8814B                               \
+	(BIT_MASK_WMAC_RESP_TXPOWER_OFFSET_TYPE_8814B                          \
+	 << BIT_SHIFT_WMAC_RESP_TXPOWER_OFFSET_TYPE_8814B)
+#define BIT_CLEAR_WMAC_RESP_TXPOWER_OFFSET_TYPE_8814B(x)                       \
+	((x) & (~BITS_WMAC_RESP_TXPOWER_OFFSET_TYPE_8814B))
+#define BIT_GET_WMAC_RESP_TXPOWER_OFFSET_TYPE_8814B(x)                         \
+	(((x) >> BIT_SHIFT_WMAC_RESP_TXPOWER_OFFSET_TYPE_8814B) &              \
+	 BIT_MASK_WMAC_RESP_TXPOWER_OFFSET_TYPE_8814B)
+#define BIT_SET_WMAC_RESP_TXPOWER_OFFSET_TYPE_8814B(x, v)                      \
+	(BIT_CLEAR_WMAC_RESP_TXPOWER_OFFSET_TYPE_8814B(x) |                    \
+	 BIT_WMAC_RESP_TXPOWER_OFFSET_TYPE_8814B(v))
+
+#define BIT_SHIFT_WMAC_RESP_TXANT_V1_8814B 6
+#define BIT_MASK_WMAC_RESP_TXANT_V1_8814B 0xfff
+#define BIT_WMAC_RESP_TXANT_V1_8814B(x)                                        \
+	(((x) & BIT_MASK_WMAC_RESP_TXANT_V1_8814B)                             \
+	 << BIT_SHIFT_WMAC_RESP_TXANT_V1_8814B)
+#define BITS_WMAC_RESP_TXANT_V1_8814B                                          \
+	(BIT_MASK_WMAC_RESP_TXANT_V1_8814B                                     \
+	 << BIT_SHIFT_WMAC_RESP_TXANT_V1_8814B)
+#define BIT_CLEAR_WMAC_RESP_TXANT_V1_8814B(x)                                  \
+	((x) & (~BITS_WMAC_RESP_TXANT_V1_8814B))
+#define BIT_GET_WMAC_RESP_TXANT_V1_8814B(x)                                    \
+	(((x) >> BIT_SHIFT_WMAC_RESP_TXANT_V1_8814B) &                         \
+	 BIT_MASK_WMAC_RESP_TXANT_V1_8814B)
+#define BIT_SET_WMAC_RESP_TXANT_V1_8814B(x, v)                                 \
+	(BIT_CLEAR_WMAC_RESP_TXANT_V1_8814B(x) |                               \
+	 BIT_WMAC_RESP_TXANT_V1_8814B(v))
+
+/* 2 REG_BBPSF_CTRL_8814B */
+#define BIT_CTL_IDLE_CLR_CSI_RPT_8814B BIT(31)
+#define BIT_WMAC_USE_NDPARATE_8814B BIT(30)
+
+#define BIT_SHIFT_WMAC_CSI_RATE_8814B 24
+#define BIT_MASK_WMAC_CSI_RATE_8814B 0x3f
+#define BIT_WMAC_CSI_RATE_8814B(x)                                             \
+	(((x) & BIT_MASK_WMAC_CSI_RATE_8814B) << BIT_SHIFT_WMAC_CSI_RATE_8814B)
+#define BITS_WMAC_CSI_RATE_8814B                                               \
+	(BIT_MASK_WMAC_CSI_RATE_8814B << BIT_SHIFT_WMAC_CSI_RATE_8814B)
+#define BIT_CLEAR_WMAC_CSI_RATE_8814B(x) ((x) & (~BITS_WMAC_CSI_RATE_8814B))
+#define BIT_GET_WMAC_CSI_RATE_8814B(x)                                         \
+	(((x) >> BIT_SHIFT_WMAC_CSI_RATE_8814B) & BIT_MASK_WMAC_CSI_RATE_8814B)
+#define BIT_SET_WMAC_CSI_RATE_8814B(x, v)                                      \
+	(BIT_CLEAR_WMAC_CSI_RATE_8814B(x) | BIT_WMAC_CSI_RATE_8814B(v))
+
+#define BIT_SHIFT_WMAC_RESP_TXRATE_8814B 16
+#define BIT_MASK_WMAC_RESP_TXRATE_8814B 0xff
+#define BIT_WMAC_RESP_TXRATE_8814B(x)                                          \
+	(((x) & BIT_MASK_WMAC_RESP_TXRATE_8814B)                               \
+	 << BIT_SHIFT_WMAC_RESP_TXRATE_8814B)
+#define BITS_WMAC_RESP_TXRATE_8814B                                            \
+	(BIT_MASK_WMAC_RESP_TXRATE_8814B << BIT_SHIFT_WMAC_RESP_TXRATE_8814B)
+#define BIT_CLEAR_WMAC_RESP_TXRATE_8814B(x)                                    \
+	((x) & (~BITS_WMAC_RESP_TXRATE_8814B))
+#define BIT_GET_WMAC_RESP_TXRATE_8814B(x)                                      \
+	(((x) >> BIT_SHIFT_WMAC_RESP_TXRATE_8814B) &                           \
+	 BIT_MASK_WMAC_RESP_TXRATE_8814B)
+#define BIT_SET_WMAC_RESP_TXRATE_8814B(x, v)                                   \
+	(BIT_CLEAR_WMAC_RESP_TXRATE_8814B(x) | BIT_WMAC_RESP_TXRATE_8814B(v))
+
+#define BIT_CSI_FORCE_RATE_EN_8814B BIT(15)
+
+#define BIT_SHIFT_CSI_RSC_8814B 13
+#define BIT_MASK_CSI_RSC_8814B 0x3
+#define BIT_CSI_RSC_8814B(x)                                                   \
+	(((x) & BIT_MASK_CSI_RSC_8814B) << BIT_SHIFT_CSI_RSC_8814B)
+#define BITS_CSI_RSC_8814B (BIT_MASK_CSI_RSC_8814B << BIT_SHIFT_CSI_RSC_8814B)
+#define BIT_CLEAR_CSI_RSC_8814B(x) ((x) & (~BITS_CSI_RSC_8814B))
+#define BIT_GET_CSI_RSC_8814B(x)                                               \
+	(((x) >> BIT_SHIFT_CSI_RSC_8814B) & BIT_MASK_CSI_RSC_8814B)
+#define BIT_SET_CSI_RSC_8814B(x, v)                                            \
+	(BIT_CLEAR_CSI_RSC_8814B(x) | BIT_CSI_RSC_8814B(v))
+
+#define BIT_CSI_GID_SEL_8814B BIT(12)
+#define BIT_RDCSIMD_FLAG_TRIG_SEL_8814B BIT(11)
+#define BIT_NDPVLD_POS_RST_FFPTR_DIS_V1_8814B BIT(10)
+#define BIT_NDPVLD_PROTECT_RDRDY_DIS_8814B BIT(9)
+#define BIT_RDCSI_EMPTY_APPZERO_8814B BIT(8)
+#define BIT_CSI_RATE_FB_EN_8814B BIT(7)
+#define BIT_RXFIFO_WRPTR_WO_CHKSUM_8814B BIT(6)
+
+/* 2 REG_P2P_RX_BCN_NOA_8814B (P2P RX BEACON NOA REGISTER) */
+#define BIT_NOA_PARSER_EN_8814B BIT(15)
+
+#define BIT_SHIFT_BSSID_SEL_V1_8814B 12
+#define BIT_MASK_BSSID_SEL_V1_8814B 0x7
+#define BIT_BSSID_SEL_V1_8814B(x)                                              \
+	(((x) & BIT_MASK_BSSID_SEL_V1_8814B) << BIT_SHIFT_BSSID_SEL_V1_8814B)
+#define BITS_BSSID_SEL_V1_8814B                                                \
+	(BIT_MASK_BSSID_SEL_V1_8814B << BIT_SHIFT_BSSID_SEL_V1_8814B)
+#define BIT_CLEAR_BSSID_SEL_V1_8814B(x) ((x) & (~BITS_BSSID_SEL_V1_8814B))
+#define BIT_GET_BSSID_SEL_V1_8814B(x)                                          \
+	(((x) >> BIT_SHIFT_BSSID_SEL_V1_8814B) & BIT_MASK_BSSID_SEL_V1_8814B)
+#define BIT_SET_BSSID_SEL_V1_8814B(x, v)                                       \
+	(BIT_CLEAR_BSSID_SEL_V1_8814B(x) | BIT_BSSID_SEL_V1_8814B(v))
+
+#define BIT_SHIFT_P2P_OUI_TYPE_8814B 0
+#define BIT_MASK_P2P_OUI_TYPE_8814B 0xff
+#define BIT_P2P_OUI_TYPE_8814B(x)                                              \
+	(((x) & BIT_MASK_P2P_OUI_TYPE_8814B) << BIT_SHIFT_P2P_OUI_TYPE_8814B)
+#define BITS_P2P_OUI_TYPE_8814B                                                \
+	(BIT_MASK_P2P_OUI_TYPE_8814B << BIT_SHIFT_P2P_OUI_TYPE_8814B)
+#define BIT_CLEAR_P2P_OUI_TYPE_8814B(x) ((x) & (~BITS_P2P_OUI_TYPE_8814B))
+#define BIT_GET_P2P_OUI_TYPE_8814B(x)                                          \
+	(((x) >> BIT_SHIFT_P2P_OUI_TYPE_8814B) & BIT_MASK_P2P_OUI_TYPE_8814B)
+#define BIT_SET_P2P_OUI_TYPE_8814B(x, v)                                       \
+	(BIT_CLEAR_P2P_OUI_TYPE_8814B(x) | BIT_P2P_OUI_TYPE_8814B(v))
+
+/* 2 REG_RSVD_8814B */
+
+/* 2 REG_ASSOCIATED_BFMER0_INFO_8814B (ASSOCIATED BEAMFORMER0 INFO REGISTER) */
+
+#define BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0_V1_8814B 0
+#define BIT_MASK_R_WMAC_SOUNDING_RXADD_R0_V1_8814B 0xffffffffL
+#define BIT_R_WMAC_SOUNDING_RXADD_R0_V1_8814B(x)                               \
+	(((x) & BIT_MASK_R_WMAC_SOUNDING_RXADD_R0_V1_8814B)                    \
+	 << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0_V1_8814B)
+#define BITS_R_WMAC_SOUNDING_RXADD_R0_V1_8814B                                 \
+	(BIT_MASK_R_WMAC_SOUNDING_RXADD_R0_V1_8814B                            \
+	 << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0_V1_8814B)
+#define BIT_CLEAR_R_WMAC_SOUNDING_RXADD_R0_V1_8814B(x)                         \
+	((x) & (~BITS_R_WMAC_SOUNDING_RXADD_R0_V1_8814B))
+#define BIT_GET_R_WMAC_SOUNDING_RXADD_R0_V1_8814B(x)                           \
+	(((x) >> BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0_V1_8814B) &                \
+	 BIT_MASK_R_WMAC_SOUNDING_RXADD_R0_V1_8814B)
+#define BIT_SET_R_WMAC_SOUNDING_RXADD_R0_V1_8814B(x, v)                        \
+	(BIT_CLEAR_R_WMAC_SOUNDING_RXADD_R0_V1_8814B(x) |                      \
+	 BIT_R_WMAC_SOUNDING_RXADD_R0_V1_8814B(v))
+
+/* 2 REG_ASSOCIATED_BFMER0_INFO_H_8814B */
+
+#define BIT_SHIFT_R_WMAC_TXCSI_AID0_8814B 16
+#define BIT_MASK_R_WMAC_TXCSI_AID0_8814B 0x1ff
+#define BIT_R_WMAC_TXCSI_AID0_8814B(x)                                         \
+	(((x) & BIT_MASK_R_WMAC_TXCSI_AID0_8814B)                              \
+	 << BIT_SHIFT_R_WMAC_TXCSI_AID0_8814B)
+#define BITS_R_WMAC_TXCSI_AID0_8814B                                           \
+	(BIT_MASK_R_WMAC_TXCSI_AID0_8814B << BIT_SHIFT_R_WMAC_TXCSI_AID0_8814B)
+#define BIT_CLEAR_R_WMAC_TXCSI_AID0_8814B(x)                                   \
+	((x) & (~BITS_R_WMAC_TXCSI_AID0_8814B))
+#define BIT_GET_R_WMAC_TXCSI_AID0_8814B(x)                                     \
+	(((x) >> BIT_SHIFT_R_WMAC_TXCSI_AID0_8814B) &                          \
+	 BIT_MASK_R_WMAC_TXCSI_AID0_8814B)
+#define BIT_SET_R_WMAC_TXCSI_AID0_8814B(x, v)                                  \
+	(BIT_CLEAR_R_WMAC_TXCSI_AID0_8814B(x) | BIT_R_WMAC_TXCSI_AID0_8814B(v))
+
+#define BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0_H_V1_8814B 0
+#define BIT_MASK_R_WMAC_SOUNDING_RXADD_R0_H_V1_8814B 0xffff
+#define BIT_R_WMAC_SOUNDING_RXADD_R0_H_V1_8814B(x)                             \
+	(((x) & BIT_MASK_R_WMAC_SOUNDING_RXADD_R0_H_V1_8814B)                  \
+	 << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0_H_V1_8814B)
+#define BITS_R_WMAC_SOUNDING_RXADD_R0_H_V1_8814B                               \
+	(BIT_MASK_R_WMAC_SOUNDING_RXADD_R0_H_V1_8814B                          \
+	 << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0_H_V1_8814B)
+#define BIT_CLEAR_R_WMAC_SOUNDING_RXADD_R0_H_V1_8814B(x)                       \
+	((x) & (~BITS_R_WMAC_SOUNDING_RXADD_R0_H_V1_8814B))
+#define BIT_GET_R_WMAC_SOUNDING_RXADD_R0_H_V1_8814B(x)                         \
+	(((x) >> BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0_H_V1_8814B) &              \
+	 BIT_MASK_R_WMAC_SOUNDING_RXADD_R0_H_V1_8814B)
+#define BIT_SET_R_WMAC_SOUNDING_RXADD_R0_H_V1_8814B(x, v)                      \
+	(BIT_CLEAR_R_WMAC_SOUNDING_RXADD_R0_H_V1_8814B(x) |                    \
+	 BIT_R_WMAC_SOUNDING_RXADD_R0_H_V1_8814B(v))
+
+/* 2 REG_ASSOCIATED_BFMER1_INFO_8814B (ASSOCIATED BEAMFORMER1 INFO REGISTER) */
+
+#define BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1_V1_8814B 0
+#define BIT_MASK_R_WMAC_SOUNDING_RXADD_R1_V1_8814B 0xffffffffL
+#define BIT_R_WMAC_SOUNDING_RXADD_R1_V1_8814B(x)                               \
+	(((x) & BIT_MASK_R_WMAC_SOUNDING_RXADD_R1_V1_8814B)                    \
+	 << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1_V1_8814B)
+#define BITS_R_WMAC_SOUNDING_RXADD_R1_V1_8814B                                 \
+	(BIT_MASK_R_WMAC_SOUNDING_RXADD_R1_V1_8814B                            \
+	 << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1_V1_8814B)
+#define BIT_CLEAR_R_WMAC_SOUNDING_RXADD_R1_V1_8814B(x)                         \
+	((x) & (~BITS_R_WMAC_SOUNDING_RXADD_R1_V1_8814B))
+#define BIT_GET_R_WMAC_SOUNDING_RXADD_R1_V1_8814B(x)                           \
+	(((x) >> BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1_V1_8814B) &                \
+	 BIT_MASK_R_WMAC_SOUNDING_RXADD_R1_V1_8814B)
+#define BIT_SET_R_WMAC_SOUNDING_RXADD_R1_V1_8814B(x, v)                        \
+	(BIT_CLEAR_R_WMAC_SOUNDING_RXADD_R1_V1_8814B(x) |                      \
+	 BIT_R_WMAC_SOUNDING_RXADD_R1_V1_8814B(v))
+
+/* 2 REG_ASSOCIATED_BFMER1_INFO_H_8814B */
+
+#define BIT_SHIFT_R_WMAC_TXCSI_AID1_8814B 16
+#define BIT_MASK_R_WMAC_TXCSI_AID1_8814B 0x1ff
+#define BIT_R_WMAC_TXCSI_AID1_8814B(x)                                         \
+	(((x) & BIT_MASK_R_WMAC_TXCSI_AID1_8814B)                              \
+	 << BIT_SHIFT_R_WMAC_TXCSI_AID1_8814B)
+#define BITS_R_WMAC_TXCSI_AID1_8814B                                           \
+	(BIT_MASK_R_WMAC_TXCSI_AID1_8814B << BIT_SHIFT_R_WMAC_TXCSI_AID1_8814B)
+#define BIT_CLEAR_R_WMAC_TXCSI_AID1_8814B(x)                                   \
+	((x) & (~BITS_R_WMAC_TXCSI_AID1_8814B))
+#define BIT_GET_R_WMAC_TXCSI_AID1_8814B(x)                                     \
+	(((x) >> BIT_SHIFT_R_WMAC_TXCSI_AID1_8814B) &                          \
+	 BIT_MASK_R_WMAC_TXCSI_AID1_8814B)
+#define BIT_SET_R_WMAC_TXCSI_AID1_8814B(x, v)                                  \
+	(BIT_CLEAR_R_WMAC_TXCSI_AID1_8814B(x) | BIT_R_WMAC_TXCSI_AID1_8814B(v))
+
+#define BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1_H_V1_8814B 0
+#define BIT_MASK_R_WMAC_SOUNDING_RXADD_R1_H_V1_8814B 0xffff
+#define BIT_R_WMAC_SOUNDING_RXADD_R1_H_V1_8814B(x)                             \
+	(((x) & BIT_MASK_R_WMAC_SOUNDING_RXADD_R1_H_V1_8814B)                  \
+	 << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1_H_V1_8814B)
+#define BITS_R_WMAC_SOUNDING_RXADD_R1_H_V1_8814B                               \
+	(BIT_MASK_R_WMAC_SOUNDING_RXADD_R1_H_V1_8814B                          \
+	 << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1_H_V1_8814B)
+#define BIT_CLEAR_R_WMAC_SOUNDING_RXADD_R1_H_V1_8814B(x)                       \
+	((x) & (~BITS_R_WMAC_SOUNDING_RXADD_R1_H_V1_8814B))
+#define BIT_GET_R_WMAC_SOUNDING_RXADD_R1_H_V1_8814B(x)                         \
+	(((x) >> BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1_H_V1_8814B) &              \
+	 BIT_MASK_R_WMAC_SOUNDING_RXADD_R1_H_V1_8814B)
+#define BIT_SET_R_WMAC_SOUNDING_RXADD_R1_H_V1_8814B(x, v)                      \
+	(BIT_CLEAR_R_WMAC_SOUNDING_RXADD_R1_H_V1_8814B(x) |                    \
+	 BIT_R_WMAC_SOUNDING_RXADD_R1_H_V1_8814B(v))
+
+/* 2 REG_TX_CSI_RPT_PARAM_BW20_8814B (TX CSI REPORT PARAMETER REGISTER) */
+
+#define BIT_SHIFT_R_WMAC_BFINFO_20M_1_8814B 16
+#define BIT_MASK_R_WMAC_BFINFO_20M_1_8814B 0xfff
+#define BIT_R_WMAC_BFINFO_20M_1_8814B(x)                                       \
+	(((x) & BIT_MASK_R_WMAC_BFINFO_20M_1_8814B)                            \
+	 << BIT_SHIFT_R_WMAC_BFINFO_20M_1_8814B)
+#define BITS_R_WMAC_BFINFO_20M_1_8814B                                         \
+	(BIT_MASK_R_WMAC_BFINFO_20M_1_8814B                                    \
+	 << BIT_SHIFT_R_WMAC_BFINFO_20M_1_8814B)
+#define BIT_CLEAR_R_WMAC_BFINFO_20M_1_8814B(x)                                 \
+	((x) & (~BITS_R_WMAC_BFINFO_20M_1_8814B))
+#define BIT_GET_R_WMAC_BFINFO_20M_1_8814B(x)                                   \
+	(((x) >> BIT_SHIFT_R_WMAC_BFINFO_20M_1_8814B) &                        \
+	 BIT_MASK_R_WMAC_BFINFO_20M_1_8814B)
+#define BIT_SET_R_WMAC_BFINFO_20M_1_8814B(x, v)                                \
+	(BIT_CLEAR_R_WMAC_BFINFO_20M_1_8814B(x) |                              \
+	 BIT_R_WMAC_BFINFO_20M_1_8814B(v))
+
+#define BIT_SHIFT_R_WMAC_BFINFO_20M_0_8814B 0
+#define BIT_MASK_R_WMAC_BFINFO_20M_0_8814B 0xfff
+#define BIT_R_WMAC_BFINFO_20M_0_8814B(x)                                       \
+	(((x) & BIT_MASK_R_WMAC_BFINFO_20M_0_8814B)                            \
+	 << BIT_SHIFT_R_WMAC_BFINFO_20M_0_8814B)
+#define BITS_R_WMAC_BFINFO_20M_0_8814B                                         \
+	(BIT_MASK_R_WMAC_BFINFO_20M_0_8814B                                    \
+	 << BIT_SHIFT_R_WMAC_BFINFO_20M_0_8814B)
+#define BIT_CLEAR_R_WMAC_BFINFO_20M_0_8814B(x)                                 \
+	((x) & (~BITS_R_WMAC_BFINFO_20M_0_8814B))
+#define BIT_GET_R_WMAC_BFINFO_20M_0_8814B(x)                                   \
+	(((x) >> BIT_SHIFT_R_WMAC_BFINFO_20M_0_8814B) &                        \
+	 BIT_MASK_R_WMAC_BFINFO_20M_0_8814B)
+#define BIT_SET_R_WMAC_BFINFO_20M_0_8814B(x, v)                                \
+	(BIT_CLEAR_R_WMAC_BFINFO_20M_0_8814B(x) |                              \
+	 BIT_R_WMAC_BFINFO_20M_0_8814B(v))
+
+/* 2 REG_TX_CSI_RPT_PARAM_BW40_8814B (TX CSI REPORT PARAMETER_BW40 REGISTER) */
+
+#define BIT_SHIFT_WMAC_RESP_ANTD_8814B 12
+#define BIT_MASK_WMAC_RESP_ANTD_8814B 0xf
+#define BIT_WMAC_RESP_ANTD_8814B(x)                                            \
+	(((x) & BIT_MASK_WMAC_RESP_ANTD_8814B)                                 \
+	 << BIT_SHIFT_WMAC_RESP_ANTD_8814B)
+#define BITS_WMAC_RESP_ANTD_8814B                                              \
+	(BIT_MASK_WMAC_RESP_ANTD_8814B << BIT_SHIFT_WMAC_RESP_ANTD_8814B)
+#define BIT_CLEAR_WMAC_RESP_ANTD_8814B(x) ((x) & (~BITS_WMAC_RESP_ANTD_8814B))
+#define BIT_GET_WMAC_RESP_ANTD_8814B(x)                                        \
+	(((x) >> BIT_SHIFT_WMAC_RESP_ANTD_8814B) &                             \
+	 BIT_MASK_WMAC_RESP_ANTD_8814B)
+#define BIT_SET_WMAC_RESP_ANTD_8814B(x, v)                                     \
+	(BIT_CLEAR_WMAC_RESP_ANTD_8814B(x) | BIT_WMAC_RESP_ANTD_8814B(v))
+
+#define BIT_SHIFT_WMAC_RESP_ANTC_8814B 8
+#define BIT_MASK_WMAC_RESP_ANTC_8814B 0xf
+#define BIT_WMAC_RESP_ANTC_8814B(x)                                            \
+	(((x) & BIT_MASK_WMAC_RESP_ANTC_8814B)                                 \
+	 << BIT_SHIFT_WMAC_RESP_ANTC_8814B)
+#define BITS_WMAC_RESP_ANTC_8814B                                              \
+	(BIT_MASK_WMAC_RESP_ANTC_8814B << BIT_SHIFT_WMAC_RESP_ANTC_8814B)
+#define BIT_CLEAR_WMAC_RESP_ANTC_8814B(x) ((x) & (~BITS_WMAC_RESP_ANTC_8814B))
+#define BIT_GET_WMAC_RESP_ANTC_8814B(x)                                        \
+	(((x) >> BIT_SHIFT_WMAC_RESP_ANTC_8814B) &                             \
+	 BIT_MASK_WMAC_RESP_ANTC_8814B)
+#define BIT_SET_WMAC_RESP_ANTC_8814B(x, v)                                     \
+	(BIT_CLEAR_WMAC_RESP_ANTC_8814B(x) | BIT_WMAC_RESP_ANTC_8814B(v))
+
+#define BIT_SHIFT_WMAC_RESP_ANTB_8814B 4
+#define BIT_MASK_WMAC_RESP_ANTB_8814B 0xf
+#define BIT_WMAC_RESP_ANTB_8814B(x)                                            \
+	(((x) & BIT_MASK_WMAC_RESP_ANTB_8814B)                                 \
+	 << BIT_SHIFT_WMAC_RESP_ANTB_8814B)
+#define BITS_WMAC_RESP_ANTB_8814B                                              \
+	(BIT_MASK_WMAC_RESP_ANTB_8814B << BIT_SHIFT_WMAC_RESP_ANTB_8814B)
+#define BIT_CLEAR_WMAC_RESP_ANTB_8814B(x) ((x) & (~BITS_WMAC_RESP_ANTB_8814B))
+#define BIT_GET_WMAC_RESP_ANTB_8814B(x)                                        \
+	(((x) >> BIT_SHIFT_WMAC_RESP_ANTB_8814B) &                             \
+	 BIT_MASK_WMAC_RESP_ANTB_8814B)
+#define BIT_SET_WMAC_RESP_ANTB_8814B(x, v)                                     \
+	(BIT_CLEAR_WMAC_RESP_ANTB_8814B(x) | BIT_WMAC_RESP_ANTB_8814B(v))
+
+#define BIT_SHIFT_WMAC_RESP_ANTA_8814B 0
+#define BIT_MASK_WMAC_RESP_ANTA_8814B 0xf
+#define BIT_WMAC_RESP_ANTA_8814B(x)                                            \
+	(((x) & BIT_MASK_WMAC_RESP_ANTA_8814B)                                 \
+	 << BIT_SHIFT_WMAC_RESP_ANTA_8814B)
+#define BITS_WMAC_RESP_ANTA_8814B                                              \
+	(BIT_MASK_WMAC_RESP_ANTA_8814B << BIT_SHIFT_WMAC_RESP_ANTA_8814B)
+#define BIT_CLEAR_WMAC_RESP_ANTA_8814B(x) ((x) & (~BITS_WMAC_RESP_ANTA_8814B))
+#define BIT_GET_WMAC_RESP_ANTA_8814B(x)                                        \
+	(((x) >> BIT_SHIFT_WMAC_RESP_ANTA_8814B) &                             \
+	 BIT_MASK_WMAC_RESP_ANTA_8814B)
+#define BIT_SET_WMAC_RESP_ANTA_8814B(x, v)                                     \
+	(BIT_CLEAR_WMAC_RESP_ANTA_8814B(x) | BIT_WMAC_RESP_ANTA_8814B(v))
+
+/* 2 REG_RSVD_8814B */
+
+/* 2 REG_BCN_PSR_RPT2_8814B (BEACON PARSER REPORT REGISTER2) */
+
+#define BIT_SHIFT_DTIM_CNT2_8814B 24
+#define BIT_MASK_DTIM_CNT2_8814B 0xff
+#define BIT_DTIM_CNT2_8814B(x)                                                 \
+	(((x) & BIT_MASK_DTIM_CNT2_8814B) << BIT_SHIFT_DTIM_CNT2_8814B)
+#define BITS_DTIM_CNT2_8814B                                                   \
+	(BIT_MASK_DTIM_CNT2_8814B << BIT_SHIFT_DTIM_CNT2_8814B)
+#define BIT_CLEAR_DTIM_CNT2_8814B(x) ((x) & (~BITS_DTIM_CNT2_8814B))
+#define BIT_GET_DTIM_CNT2_8814B(x)                                             \
+	(((x) >> BIT_SHIFT_DTIM_CNT2_8814B) & BIT_MASK_DTIM_CNT2_8814B)
+#define BIT_SET_DTIM_CNT2_8814B(x, v)                                          \
+	(BIT_CLEAR_DTIM_CNT2_8814B(x) | BIT_DTIM_CNT2_8814B(v))
+
+#define BIT_SHIFT_DTIM_PERIOD2_8814B 16
+#define BIT_MASK_DTIM_PERIOD2_8814B 0xff
+#define BIT_DTIM_PERIOD2_8814B(x)                                              \
+	(((x) & BIT_MASK_DTIM_PERIOD2_8814B) << BIT_SHIFT_DTIM_PERIOD2_8814B)
+#define BITS_DTIM_PERIOD2_8814B                                                \
+	(BIT_MASK_DTIM_PERIOD2_8814B << BIT_SHIFT_DTIM_PERIOD2_8814B)
+#define BIT_CLEAR_DTIM_PERIOD2_8814B(x) ((x) & (~BITS_DTIM_PERIOD2_8814B))
+#define BIT_GET_DTIM_PERIOD2_8814B(x)                                          \
+	(((x) >> BIT_SHIFT_DTIM_PERIOD2_8814B) & BIT_MASK_DTIM_PERIOD2_8814B)
+#define BIT_SET_DTIM_PERIOD2_8814B(x, v)                                       \
+	(BIT_CLEAR_DTIM_PERIOD2_8814B(x) | BIT_DTIM_PERIOD2_8814B(v))
+
+#define BIT_DTIM2_8814B BIT(15)
+#define BIT_TIM2_8814B BIT(14)
+#define BIT_RPT_VALID_8814B BIT(13)
+
+#define BIT_SHIFT_PS_AID_2_8814B 0
+#define BIT_MASK_PS_AID_2_8814B 0x7ff
+#define BIT_PS_AID_2_8814B(x)                                                  \
+	(((x) & BIT_MASK_PS_AID_2_8814B) << BIT_SHIFT_PS_AID_2_8814B)
+#define BITS_PS_AID_2_8814B                                                    \
+	(BIT_MASK_PS_AID_2_8814B << BIT_SHIFT_PS_AID_2_8814B)
+#define BIT_CLEAR_PS_AID_2_8814B(x) ((x) & (~BITS_PS_AID_2_8814B))
+#define BIT_GET_PS_AID_2_8814B(x)                                              \
+	(((x) >> BIT_SHIFT_PS_AID_2_8814B) & BIT_MASK_PS_AID_2_8814B)
+#define BIT_SET_PS_AID_2_8814B(x, v)                                           \
+	(BIT_CLEAR_PS_AID_2_8814B(x) | BIT_PS_AID_2_8814B(v))
+
+/* 2 REG_BCN_PSR_RPT3_8814B (BEACON PARSER REPORT REGISTER3) */
+
+#define BIT_SHIFT_DTIM_CNT3_8814B 24
+#define BIT_MASK_DTIM_CNT3_8814B 0xff
+#define BIT_DTIM_CNT3_8814B(x)                                                 \
+	(((x) & BIT_MASK_DTIM_CNT3_8814B) << BIT_SHIFT_DTIM_CNT3_8814B)
+#define BITS_DTIM_CNT3_8814B                                                   \
+	(BIT_MASK_DTIM_CNT3_8814B << BIT_SHIFT_DTIM_CNT3_8814B)
+#define BIT_CLEAR_DTIM_CNT3_8814B(x) ((x) & (~BITS_DTIM_CNT3_8814B))
+#define BIT_GET_DTIM_CNT3_8814B(x)                                             \
+	(((x) >> BIT_SHIFT_DTIM_CNT3_8814B) & BIT_MASK_DTIM_CNT3_8814B)
+#define BIT_SET_DTIM_CNT3_8814B(x, v)                                          \
+	(BIT_CLEAR_DTIM_CNT3_8814B(x) | BIT_DTIM_CNT3_8814B(v))
+
+#define BIT_SHIFT_DTIM_PERIOD3_8814B 16
+#define BIT_MASK_DTIM_PERIOD3_8814B 0xff
+#define BIT_DTIM_PERIOD3_8814B(x)                                              \
+	(((x) & BIT_MASK_DTIM_PERIOD3_8814B) << BIT_SHIFT_DTIM_PERIOD3_8814B)
+#define BITS_DTIM_PERIOD3_8814B                                                \
+	(BIT_MASK_DTIM_PERIOD3_8814B << BIT_SHIFT_DTIM_PERIOD3_8814B)
+#define BIT_CLEAR_DTIM_PERIOD3_8814B(x) ((x) & (~BITS_DTIM_PERIOD3_8814B))
+#define BIT_GET_DTIM_PERIOD3_8814B(x)                                          \
+	(((x) >> BIT_SHIFT_DTIM_PERIOD3_8814B) & BIT_MASK_DTIM_PERIOD3_8814B)
+#define BIT_SET_DTIM_PERIOD3_8814B(x, v)                                       \
+	(BIT_CLEAR_DTIM_PERIOD3_8814B(x) | BIT_DTIM_PERIOD3_8814B(v))
+
+#define BIT_DTIM3_8814B BIT(15)
+#define BIT_TIM3_8814B BIT(14)
+#define BIT_RPT_VALID_8814B BIT(13)
+
+#define BIT_SHIFT_PS_AID_3_8814B 0
+#define BIT_MASK_PS_AID_3_8814B 0x7ff
+#define BIT_PS_AID_3_8814B(x)                                                  \
+	(((x) & BIT_MASK_PS_AID_3_8814B) << BIT_SHIFT_PS_AID_3_8814B)
+#define BITS_PS_AID_3_8814B                                                    \
+	(BIT_MASK_PS_AID_3_8814B << BIT_SHIFT_PS_AID_3_8814B)
+#define BIT_CLEAR_PS_AID_3_8814B(x) ((x) & (~BITS_PS_AID_3_8814B))
+#define BIT_GET_PS_AID_3_8814B(x)                                              \
+	(((x) >> BIT_SHIFT_PS_AID_3_8814B) & BIT_MASK_PS_AID_3_8814B)
+#define BIT_SET_PS_AID_3_8814B(x, v)                                           \
+	(BIT_CLEAR_PS_AID_3_8814B(x) | BIT_PS_AID_3_8814B(v))
+
+/* 2 REG_BCN_PSR_RPT4_8814B (BEACON PARSER REPORT REGISTER4) */
+
+#define BIT_SHIFT_DTIM_CNT4_8814B 24
+#define BIT_MASK_DTIM_CNT4_8814B 0xff
+#define BIT_DTIM_CNT4_8814B(x)                                                 \
+	(((x) & BIT_MASK_DTIM_CNT4_8814B) << BIT_SHIFT_DTIM_CNT4_8814B)
+#define BITS_DTIM_CNT4_8814B                                                   \
+	(BIT_MASK_DTIM_CNT4_8814B << BIT_SHIFT_DTIM_CNT4_8814B)
+#define BIT_CLEAR_DTIM_CNT4_8814B(x) ((x) & (~BITS_DTIM_CNT4_8814B))
+#define BIT_GET_DTIM_CNT4_8814B(x)                                             \
+	(((x) >> BIT_SHIFT_DTIM_CNT4_8814B) & BIT_MASK_DTIM_CNT4_8814B)
+#define BIT_SET_DTIM_CNT4_8814B(x, v)                                          \
+	(BIT_CLEAR_DTIM_CNT4_8814B(x) | BIT_DTIM_CNT4_8814B(v))
+
+#define BIT_SHIFT_DTIM_PERIOD4_8814B 16
+#define BIT_MASK_DTIM_PERIOD4_8814B 0xff
+#define BIT_DTIM_PERIOD4_8814B(x)                                              \
+	(((x) & BIT_MASK_DTIM_PERIOD4_8814B) << BIT_SHIFT_DTIM_PERIOD4_8814B)
+#define BITS_DTIM_PERIOD4_8814B                                                \
+	(BIT_MASK_DTIM_PERIOD4_8814B << BIT_SHIFT_DTIM_PERIOD4_8814B)
+#define BIT_CLEAR_DTIM_PERIOD4_8814B(x) ((x) & (~BITS_DTIM_PERIOD4_8814B))
+#define BIT_GET_DTIM_PERIOD4_8814B(x)                                          \
+	(((x) >> BIT_SHIFT_DTIM_PERIOD4_8814B) & BIT_MASK_DTIM_PERIOD4_8814B)
+#define BIT_SET_DTIM_PERIOD4_8814B(x, v)                                       \
+	(BIT_CLEAR_DTIM_PERIOD4_8814B(x) | BIT_DTIM_PERIOD4_8814B(v))
+
+#define BIT_DTIM4_8814B BIT(15)
+#define BIT_TIM4_8814B BIT(14)
+#define BIT_RPT_VALID_8814B BIT(13)
+
+#define BIT_SHIFT_PS_AID_4_8814B 0
+#define BIT_MASK_PS_AID_4_8814B 0x7ff
+#define BIT_PS_AID_4_8814B(x)                                                  \
+	(((x) & BIT_MASK_PS_AID_4_8814B) << BIT_SHIFT_PS_AID_4_8814B)
+#define BITS_PS_AID_4_8814B                                                    \
+	(BIT_MASK_PS_AID_4_8814B << BIT_SHIFT_PS_AID_4_8814B)
+#define BIT_CLEAR_PS_AID_4_8814B(x) ((x) & (~BITS_PS_AID_4_8814B))
+#define BIT_GET_PS_AID_4_8814B(x)                                              \
+	(((x) >> BIT_SHIFT_PS_AID_4_8814B) & BIT_MASK_PS_AID_4_8814B)
+#define BIT_SET_PS_AID_4_8814B(x, v)                                           \
+	(BIT_CLEAR_PS_AID_4_8814B(x) | BIT_PS_AID_4_8814B(v))
+
+/* 2 REG_A1_ADDR_MASK_8814B (A1 ADDR MASK REGISTER) */
+
+#define BIT_SHIFT_A1_ADDR_MASK_8814B 0
+#define BIT_MASK_A1_ADDR_MASK_8814B 0xffffffffL
+#define BIT_A1_ADDR_MASK_8814B(x)                                              \
+	(((x) & BIT_MASK_A1_ADDR_MASK_8814B) << BIT_SHIFT_A1_ADDR_MASK_8814B)
+#define BITS_A1_ADDR_MASK_8814B                                                \
+	(BIT_MASK_A1_ADDR_MASK_8814B << BIT_SHIFT_A1_ADDR_MASK_8814B)
+#define BIT_CLEAR_A1_ADDR_MASK_8814B(x) ((x) & (~BITS_A1_ADDR_MASK_8814B))
+#define BIT_GET_A1_ADDR_MASK_8814B(x)                                          \
+	(((x) >> BIT_SHIFT_A1_ADDR_MASK_8814B) & BIT_MASK_A1_ADDR_MASK_8814B)
+#define BIT_SET_A1_ADDR_MASK_8814B(x, v)                                       \
+	(BIT_CLEAR_A1_ADDR_MASK_8814B(x) | BIT_A1_ADDR_MASK_8814B(v))
+
+/* 2 REG_RXPSF_CTRL_8814B */
+#define BIT_RXGCK_FIFOTHR_EN_8814B BIT(28)
+
+#define BIT_SHIFT_RXGCK_VHT_FIFOTHR_8814B 26
+#define BIT_MASK_RXGCK_VHT_FIFOTHR_8814B 0x3
+#define BIT_RXGCK_VHT_FIFOTHR_8814B(x)                                         \
+	(((x) & BIT_MASK_RXGCK_VHT_FIFOTHR_8814B)                              \
+	 << BIT_SHIFT_RXGCK_VHT_FIFOTHR_8814B)
+#define BITS_RXGCK_VHT_FIFOTHR_8814B                                           \
+	(BIT_MASK_RXGCK_VHT_FIFOTHR_8814B << BIT_SHIFT_RXGCK_VHT_FIFOTHR_8814B)
+#define BIT_CLEAR_RXGCK_VHT_FIFOTHR_8814B(x)                                   \
+	((x) & (~BITS_RXGCK_VHT_FIFOTHR_8814B))
+#define BIT_GET_RXGCK_VHT_FIFOTHR_8814B(x)                                     \
+	(((x) >> BIT_SHIFT_RXGCK_VHT_FIFOTHR_8814B) &                          \
+	 BIT_MASK_RXGCK_VHT_FIFOTHR_8814B)
+#define BIT_SET_RXGCK_VHT_FIFOTHR_8814B(x, v)                                  \
+	(BIT_CLEAR_RXGCK_VHT_FIFOTHR_8814B(x) | BIT_RXGCK_VHT_FIFOTHR_8814B(v))
+
+#define BIT_SHIFT_RXGCK_HT_FIFOTHR_8814B 24
+#define BIT_MASK_RXGCK_HT_FIFOTHR_8814B 0x3
+#define BIT_RXGCK_HT_FIFOTHR_8814B(x)                                          \
+	(((x) & BIT_MASK_RXGCK_HT_FIFOTHR_8814B)                               \
+	 << BIT_SHIFT_RXGCK_HT_FIFOTHR_8814B)
+#define BITS_RXGCK_HT_FIFOTHR_8814B                                            \
+	(BIT_MASK_RXGCK_HT_FIFOTHR_8814B << BIT_SHIFT_RXGCK_HT_FIFOTHR_8814B)
+#define BIT_CLEAR_RXGCK_HT_FIFOTHR_8814B(x)                                    \
+	((x) & (~BITS_RXGCK_HT_FIFOTHR_8814B))
+#define BIT_GET_RXGCK_HT_FIFOTHR_8814B(x)                                      \
+	(((x) >> BIT_SHIFT_RXGCK_HT_FIFOTHR_8814B) &                           \
+	 BIT_MASK_RXGCK_HT_FIFOTHR_8814B)
+#define BIT_SET_RXGCK_HT_FIFOTHR_8814B(x, v)                                   \
+	(BIT_CLEAR_RXGCK_HT_FIFOTHR_8814B(x) | BIT_RXGCK_HT_FIFOTHR_8814B(v))
+
+#define BIT_SHIFT_RXGCK_OFDM_FIFOTHR_8814B 22
+#define BIT_MASK_RXGCK_OFDM_FIFOTHR_8814B 0x3
+#define BIT_RXGCK_OFDM_FIFOTHR_8814B(x)                                        \
+	(((x) & BIT_MASK_RXGCK_OFDM_FIFOTHR_8814B)                             \
+	 << BIT_SHIFT_RXGCK_OFDM_FIFOTHR_8814B)
+#define BITS_RXGCK_OFDM_FIFOTHR_8814B                                          \
+	(BIT_MASK_RXGCK_OFDM_FIFOTHR_8814B                                     \
+	 << BIT_SHIFT_RXGCK_OFDM_FIFOTHR_8814B)
+#define BIT_CLEAR_RXGCK_OFDM_FIFOTHR_8814B(x)                                  \
+	((x) & (~BITS_RXGCK_OFDM_FIFOTHR_8814B))
+#define BIT_GET_RXGCK_OFDM_FIFOTHR_8814B(x)                                    \
+	(((x) >> BIT_SHIFT_RXGCK_OFDM_FIFOTHR_8814B) &                         \
+	 BIT_MASK_RXGCK_OFDM_FIFOTHR_8814B)
+#define BIT_SET_RXGCK_OFDM_FIFOTHR_8814B(x, v)                                 \
+	(BIT_CLEAR_RXGCK_OFDM_FIFOTHR_8814B(x) |                               \
+	 BIT_RXGCK_OFDM_FIFOTHR_8814B(v))
+
+#define BIT_SHIFT_RXGCK_CCK_FIFOTHR_8814B 20
+#define BIT_MASK_RXGCK_CCK_FIFOTHR_8814B 0x3
+#define BIT_RXGCK_CCK_FIFOTHR_8814B(x)                                         \
+	(((x) & BIT_MASK_RXGCK_CCK_FIFOTHR_8814B)                              \
+	 << BIT_SHIFT_RXGCK_CCK_FIFOTHR_8814B)
+#define BITS_RXGCK_CCK_FIFOTHR_8814B                                           \
+	(BIT_MASK_RXGCK_CCK_FIFOTHR_8814B << BIT_SHIFT_RXGCK_CCK_FIFOTHR_8814B)
+#define BIT_CLEAR_RXGCK_CCK_FIFOTHR_8814B(x)                                   \
+	((x) & (~BITS_RXGCK_CCK_FIFOTHR_8814B))
+#define BIT_GET_RXGCK_CCK_FIFOTHR_8814B(x)                                     \
+	(((x) >> BIT_SHIFT_RXGCK_CCK_FIFOTHR_8814B) &                          \
+	 BIT_MASK_RXGCK_CCK_FIFOTHR_8814B)
+#define BIT_SET_RXGCK_CCK_FIFOTHR_8814B(x, v)                                  \
+	(BIT_CLEAR_RXGCK_CCK_FIFOTHR_8814B(x) | BIT_RXGCK_CCK_FIFOTHR_8814B(v))
+
+#define BIT_SHIFT_RXGCK_ENTRY_DELAY_8814B 17
+#define BIT_MASK_RXGCK_ENTRY_DELAY_8814B 0x7
+#define BIT_RXGCK_ENTRY_DELAY_8814B(x)                                         \
+	(((x) & BIT_MASK_RXGCK_ENTRY_DELAY_8814B)                              \
+	 << BIT_SHIFT_RXGCK_ENTRY_DELAY_8814B)
+#define BITS_RXGCK_ENTRY_DELAY_8814B                                           \
+	(BIT_MASK_RXGCK_ENTRY_DELAY_8814B << BIT_SHIFT_RXGCK_ENTRY_DELAY_8814B)
+#define BIT_CLEAR_RXGCK_ENTRY_DELAY_8814B(x)                                   \
+	((x) & (~BITS_RXGCK_ENTRY_DELAY_8814B))
+#define BIT_GET_RXGCK_ENTRY_DELAY_8814B(x)                                     \
+	(((x) >> BIT_SHIFT_RXGCK_ENTRY_DELAY_8814B) &                          \
+	 BIT_MASK_RXGCK_ENTRY_DELAY_8814B)
+#define BIT_SET_RXGCK_ENTRY_DELAY_8814B(x, v)                                  \
+	(BIT_CLEAR_RXGCK_ENTRY_DELAY_8814B(x) | BIT_RXGCK_ENTRY_DELAY_8814B(v))
+
+#define BIT_RXGCK_OFDMCCA_EN_8814B BIT(16)
+
+#define BIT_SHIFT_RXPSF_PKTLENTHR_8814B 13
+#define BIT_MASK_RXPSF_PKTLENTHR_8814B 0x7
+#define BIT_RXPSF_PKTLENTHR_8814B(x)                                           \
+	(((x) & BIT_MASK_RXPSF_PKTLENTHR_8814B)                                \
+	 << BIT_SHIFT_RXPSF_PKTLENTHR_8814B)
+#define BITS_RXPSF_PKTLENTHR_8814B                                             \
+	(BIT_MASK_RXPSF_PKTLENTHR_8814B << BIT_SHIFT_RXPSF_PKTLENTHR_8814B)
+#define BIT_CLEAR_RXPSF_PKTLENTHR_8814B(x) ((x) & (~BITS_RXPSF_PKTLENTHR_8814B))
+#define BIT_GET_RXPSF_PKTLENTHR_8814B(x)                                       \
+	(((x) >> BIT_SHIFT_RXPSF_PKTLENTHR_8814B) &                            \
+	 BIT_MASK_RXPSF_PKTLENTHR_8814B)
+#define BIT_SET_RXPSF_PKTLENTHR_8814B(x, v)                                    \
+	(BIT_CLEAR_RXPSF_PKTLENTHR_8814B(x) | BIT_RXPSF_PKTLENTHR_8814B(v))
+
+#define BIT_RXPSF_CTRLEN_8814B BIT(12)
+#define BIT_RXPSF_VHTCHKEN_8814B BIT(11)
+#define BIT_RXPSF_HTCHKEN_8814B BIT(10)
+#define BIT_RXPSF_OFDMCHKEN_8814B BIT(9)
+#define BIT_RXPSF_CCKCHKEN_8814B BIT(8)
+#define BIT_RXPSF_OFDMRST_8814B BIT(7)
+#define BIT_RXPSF_CCKRST_8814B BIT(6)
+#define BIT_RXPSF_MHCHKEN_8814B BIT(5)
+#define BIT_RXPSF_CONT_ERRCHKEN_8814B BIT(4)
+#define BIT_RXPSF_ALL_ERRCHKEN_8814B BIT(3)
+
+#define BIT_SHIFT_RXPSF_ERRTHR_8814B 0
+#define BIT_MASK_RXPSF_ERRTHR_8814B 0x7
+#define BIT_RXPSF_ERRTHR_8814B(x)                                              \
+	(((x) & BIT_MASK_RXPSF_ERRTHR_8814B) << BIT_SHIFT_RXPSF_ERRTHR_8814B)
+#define BITS_RXPSF_ERRTHR_8814B                                                \
+	(BIT_MASK_RXPSF_ERRTHR_8814B << BIT_SHIFT_RXPSF_ERRTHR_8814B)
+#define BIT_CLEAR_RXPSF_ERRTHR_8814B(x) ((x) & (~BITS_RXPSF_ERRTHR_8814B))
+#define BIT_GET_RXPSF_ERRTHR_8814B(x)                                          \
+	(((x) >> BIT_SHIFT_RXPSF_ERRTHR_8814B) & BIT_MASK_RXPSF_ERRTHR_8814B)
+#define BIT_SET_RXPSF_ERRTHR_8814B(x, v)                                       \
+	(BIT_CLEAR_RXPSF_ERRTHR_8814B(x) | BIT_RXPSF_ERRTHR_8814B(v))
+
+/* 2 REG_RXPSF_TYPE_CTRL_8814B */
+#define BIT_RXPSF_DATA15EN_8814B BIT(31)
+#define BIT_RXPSF_DATA14EN_8814B BIT(30)
+#define BIT_RXPSF_DATA13EN_8814B BIT(29)
+#define BIT_RXPSF_DATA12EN_8814B BIT(28)
+#define BIT_RXPSF_DATA11EN_8814B BIT(27)
+#define BIT_RXPSF_DATA10EN_8814B BIT(26)
+#define BIT_RXPSF_DATA9EN_8814B BIT(25)
+#define BIT_RXPSF_DATA8EN_8814B BIT(24)
+#define BIT_RXPSF_DATA7EN_8814B BIT(23)
+#define BIT_RXPSF_DATA6EN_8814B BIT(22)
+#define BIT_RXPSF_DATA5EN_8814B BIT(21)
+#define BIT_RXPSF_DATA4EN_8814B BIT(20)
+#define BIT_RXPSF_DATA3EN_8814B BIT(19)
+#define BIT_RXPSF_DATA2EN_8814B BIT(18)
+#define BIT_RXPSF_DATA1EN_8814B BIT(17)
+#define BIT_RXPSF_DATA0EN_8814B BIT(16)
+#define BIT_RXPSF_MGT15EN_8814B BIT(15)
+#define BIT_RXPSF_MGT14EN_8814B BIT(14)
+#define BIT_RXPSF_MGT13EN_8814B BIT(13)
+#define BIT_RXPSF_MGT12EN_8814B BIT(12)
+#define BIT_RXPSF_MGT11EN_8814B BIT(11)
+#define BIT_RXPSF_MGT10EN_8814B BIT(10)
+#define BIT_RXPSF_MGT9EN_8814B BIT(9)
+#define BIT_RXPSF_MGT8EN_8814B BIT(8)
+#define BIT_RXPSF_MGT7EN_8814B BIT(7)
+#define BIT_RXPSF_MGT6EN_8814B BIT(6)
+#define BIT_RXPSF_MGT5EN_8814B BIT(5)
+#define BIT_RXPSF_MGT4EN_8814B BIT(4)
+#define BIT_RXPSF_MGT3EN_8814B BIT(3)
+#define BIT_RXPSF_MGT2EN_8814B BIT(2)
+#define BIT_RXPSF_MGT1EN_8814B BIT(1)
+#define BIT_RXPSF_MGT0EN_8814B BIT(0)
+
+/* 2 REG_CAM_ACCESS_CTRL_8814B */
+#define BIT_INDIRECT_ERR_8814B BIT(6)
+#define BIT_DIRECT_ERR_8814B BIT(5)
+#define BIT_DIR_ACCESS_EN_RX_BA_8814B BIT(4)
+#define BIT_DIR_ACCESS_EN_ADDRCAM_8814B BIT(3)
+#define BIT_DIR_ACCESS_EN_KEY_8814B BIT(2)
+#define BIT_DIR_ACCESS_EN_WOWLAN_8814B BIT(1)
+#define BIT_DIR_ACCESS_EN_FW_FILTER_8814B BIT(0)
+
+/* 2 REG_CUT_AMSDU_CTRL_8814B */
+#define BIT__CUT_AMSDU_CHKLEN_EN_8814B BIT(31)
+#define BIT_EN_CUT_AMSDU_8814B BIT(30)
+
+#define BIT_SHIFT_CUT_AMSDU_CHKLEN_L_TH_8814B 16
+#define BIT_MASK_CUT_AMSDU_CHKLEN_L_TH_8814B 0xff
+#define BIT_CUT_AMSDU_CHKLEN_L_TH_8814B(x)                                     \
+	(((x) & BIT_MASK_CUT_AMSDU_CHKLEN_L_TH_8814B)                          \
+	 << BIT_SHIFT_CUT_AMSDU_CHKLEN_L_TH_8814B)
+#define BITS_CUT_AMSDU_CHKLEN_L_TH_8814B                                       \
+	(BIT_MASK_CUT_AMSDU_CHKLEN_L_TH_8814B                                  \
+	 << BIT_SHIFT_CUT_AMSDU_CHKLEN_L_TH_8814B)
+#define BIT_CLEAR_CUT_AMSDU_CHKLEN_L_TH_8814B(x)                               \
+	((x) & (~BITS_CUT_AMSDU_CHKLEN_L_TH_8814B))
+#define BIT_GET_CUT_AMSDU_CHKLEN_L_TH_8814B(x)                                 \
+	(((x) >> BIT_SHIFT_CUT_AMSDU_CHKLEN_L_TH_8814B) &                      \
+	 BIT_MASK_CUT_AMSDU_CHKLEN_L_TH_8814B)
+#define BIT_SET_CUT_AMSDU_CHKLEN_L_TH_8814B(x, v)                              \
+	(BIT_CLEAR_CUT_AMSDU_CHKLEN_L_TH_8814B(x) |                            \
+	 BIT_CUT_AMSDU_CHKLEN_L_TH_8814B(v))
+
+#define BIT_SHIFT_CUT_AMSDU_CHKLEN_H_TH_8814B 0
+#define BIT_MASK_CUT_AMSDU_CHKLEN_H_TH_8814B 0xffff
+#define BIT_CUT_AMSDU_CHKLEN_H_TH_8814B(x)                                     \
+	(((x) & BIT_MASK_CUT_AMSDU_CHKLEN_H_TH_8814B)                          \
+	 << BIT_SHIFT_CUT_AMSDU_CHKLEN_H_TH_8814B)
+#define BITS_CUT_AMSDU_CHKLEN_H_TH_8814B                                       \
+	(BIT_MASK_CUT_AMSDU_CHKLEN_H_TH_8814B                                  \
+	 << BIT_SHIFT_CUT_AMSDU_CHKLEN_H_TH_8814B)
+#define BIT_CLEAR_CUT_AMSDU_CHKLEN_H_TH_8814B(x)                               \
+	((x) & (~BITS_CUT_AMSDU_CHKLEN_H_TH_8814B))
+#define BIT_GET_CUT_AMSDU_CHKLEN_H_TH_8814B(x)                                 \
+	(((x) >> BIT_SHIFT_CUT_AMSDU_CHKLEN_H_TH_8814B) &                      \
+	 BIT_MASK_CUT_AMSDU_CHKLEN_H_TH_8814B)
+#define BIT_SET_CUT_AMSDU_CHKLEN_H_TH_8814B(x, v)                              \
+	(BIT_CLEAR_CUT_AMSDU_CHKLEN_H_TH_8814B(x) |                            \
+	 BIT_CUT_AMSDU_CHKLEN_H_TH_8814B(v))
+
+/* 2 REG_MACID2_8814B (MAC ID2 REGISTER) */
+
+#define BIT_SHIFT_MACID2_V1_8814B 0
+#define BIT_MASK_MACID2_V1_8814B 0xffffffffL
+#define BIT_MACID2_V1_8814B(x)                                                 \
+	(((x) & BIT_MASK_MACID2_V1_8814B) << BIT_SHIFT_MACID2_V1_8814B)
+#define BITS_MACID2_V1_8814B                                                   \
+	(BIT_MASK_MACID2_V1_8814B << BIT_SHIFT_MACID2_V1_8814B)
+#define BIT_CLEAR_MACID2_V1_8814B(x) ((x) & (~BITS_MACID2_V1_8814B))
+#define BIT_GET_MACID2_V1_8814B(x)                                             \
+	(((x) >> BIT_SHIFT_MACID2_V1_8814B) & BIT_MASK_MACID2_V1_8814B)
+#define BIT_SET_MACID2_V1_8814B(x, v)                                          \
+	(BIT_CLEAR_MACID2_V1_8814B(x) | BIT_MACID2_V1_8814B(v))
+
+/* 2 REG_MACID2_H_8814B (MAC ID2 REGISTER) */
+
+#define BIT_SHIFT_MACID2_H_V1_8814B 0
+#define BIT_MASK_MACID2_H_V1_8814B 0xffff
+#define BIT_MACID2_H_V1_8814B(x)                                               \
+	(((x) & BIT_MASK_MACID2_H_V1_8814B) << BIT_SHIFT_MACID2_H_V1_8814B)
+#define BITS_MACID2_H_V1_8814B                                                 \
+	(BIT_MASK_MACID2_H_V1_8814B << BIT_SHIFT_MACID2_H_V1_8814B)
+#define BIT_CLEAR_MACID2_H_V1_8814B(x) ((x) & (~BITS_MACID2_H_V1_8814B))
+#define BIT_GET_MACID2_H_V1_8814B(x)                                           \
+	(((x) >> BIT_SHIFT_MACID2_H_V1_8814B) & BIT_MASK_MACID2_H_V1_8814B)
+#define BIT_SET_MACID2_H_V1_8814B(x, v)                                        \
+	(BIT_CLEAR_MACID2_H_V1_8814B(x) | BIT_MACID2_H_V1_8814B(v))
+
+/* 2 REG_BSSID2_8814B (BSSID2 REGISTER) */
+
+#define BIT_SHIFT_BSSID2_V1_8814B 0
+#define BIT_MASK_BSSID2_V1_8814B 0xffffffffL
+#define BIT_BSSID2_V1_8814B(x)                                                 \
+	(((x) & BIT_MASK_BSSID2_V1_8814B) << BIT_SHIFT_BSSID2_V1_8814B)
+#define BITS_BSSID2_V1_8814B                                                   \
+	(BIT_MASK_BSSID2_V1_8814B << BIT_SHIFT_BSSID2_V1_8814B)
+#define BIT_CLEAR_BSSID2_V1_8814B(x) ((x) & (~BITS_BSSID2_V1_8814B))
+#define BIT_GET_BSSID2_V1_8814B(x)                                             \
+	(((x) >> BIT_SHIFT_BSSID2_V1_8814B) & BIT_MASK_BSSID2_V1_8814B)
+#define BIT_SET_BSSID2_V1_8814B(x, v)                                          \
+	(BIT_CLEAR_BSSID2_V1_8814B(x) | BIT_BSSID2_V1_8814B(v))
+
+/* 2 REG_BSSID2_H_8814B (BSSID2 REGISTER) */
+
+#define BIT_SHIFT_BSSID2_H_V1_8814B 0
+#define BIT_MASK_BSSID2_H_V1_8814B 0xffff
+#define BIT_BSSID2_H_V1_8814B(x)                                               \
+	(((x) & BIT_MASK_BSSID2_H_V1_8814B) << BIT_SHIFT_BSSID2_H_V1_8814B)
+#define BITS_BSSID2_H_V1_8814B                                                 \
+	(BIT_MASK_BSSID2_H_V1_8814B << BIT_SHIFT_BSSID2_H_V1_8814B)
+#define BIT_CLEAR_BSSID2_H_V1_8814B(x) ((x) & (~BITS_BSSID2_H_V1_8814B))
+#define BIT_GET_BSSID2_H_V1_8814B(x)                                           \
+	(((x) >> BIT_SHIFT_BSSID2_H_V1_8814B) & BIT_MASK_BSSID2_H_V1_8814B)
+#define BIT_SET_BSSID2_H_V1_8814B(x, v)                                        \
+	(BIT_CLEAR_BSSID2_H_V1_8814B(x) | BIT_BSSID2_H_V1_8814B(v))
+
+/* 2 REG_MACID3_8814B (MAC ID3 REGISTER) */
+
+#define BIT_SHIFT_MACID3_V1_8814B 0
+#define BIT_MASK_MACID3_V1_8814B 0xffffffffL
+#define BIT_MACID3_V1_8814B(x)                                                 \
+	(((x) & BIT_MASK_MACID3_V1_8814B) << BIT_SHIFT_MACID3_V1_8814B)
+#define BITS_MACID3_V1_8814B                                                   \
+	(BIT_MASK_MACID3_V1_8814B << BIT_SHIFT_MACID3_V1_8814B)
+#define BIT_CLEAR_MACID3_V1_8814B(x) ((x) & (~BITS_MACID3_V1_8814B))
+#define BIT_GET_MACID3_V1_8814B(x)                                             \
+	(((x) >> BIT_SHIFT_MACID3_V1_8814B) & BIT_MASK_MACID3_V1_8814B)
+#define BIT_SET_MACID3_V1_8814B(x, v)                                          \
+	(BIT_CLEAR_MACID3_V1_8814B(x) | BIT_MACID3_V1_8814B(v))
+
+/* 2 REG_MACID3_H_8814B (MAC ID3 REGISTER) */
+
+#define BIT_SHIFT_MACID3_H_V1_8814B 0
+#define BIT_MASK_MACID3_H_V1_8814B 0xffff
+#define BIT_MACID3_H_V1_8814B(x)                                               \
+	(((x) & BIT_MASK_MACID3_H_V1_8814B) << BIT_SHIFT_MACID3_H_V1_8814B)
+#define BITS_MACID3_H_V1_8814B                                                 \
+	(BIT_MASK_MACID3_H_V1_8814B << BIT_SHIFT_MACID3_H_V1_8814B)
+#define BIT_CLEAR_MACID3_H_V1_8814B(x) ((x) & (~BITS_MACID3_H_V1_8814B))
+#define BIT_GET_MACID3_H_V1_8814B(x)                                           \
+	(((x) >> BIT_SHIFT_MACID3_H_V1_8814B) & BIT_MASK_MACID3_H_V1_8814B)
+#define BIT_SET_MACID3_H_V1_8814B(x, v)                                        \
+	(BIT_CLEAR_MACID3_H_V1_8814B(x) | BIT_MACID3_H_V1_8814B(v))
+
+/* 2 REG_BSSID3_8814B (BSSID3 REGISTER) */
+
+#define BIT_SHIFT_BSSID3_V1_8814B 0
+#define BIT_MASK_BSSID3_V1_8814B 0xffffffffL
+#define BIT_BSSID3_V1_8814B(x)                                                 \
+	(((x) & BIT_MASK_BSSID3_V1_8814B) << BIT_SHIFT_BSSID3_V1_8814B)
+#define BITS_BSSID3_V1_8814B                                                   \
+	(BIT_MASK_BSSID3_V1_8814B << BIT_SHIFT_BSSID3_V1_8814B)
+#define BIT_CLEAR_BSSID3_V1_8814B(x) ((x) & (~BITS_BSSID3_V1_8814B))
+#define BIT_GET_BSSID3_V1_8814B(x)                                             \
+	(((x) >> BIT_SHIFT_BSSID3_V1_8814B) & BIT_MASK_BSSID3_V1_8814B)
+#define BIT_SET_BSSID3_V1_8814B(x, v)                                          \
+	(BIT_CLEAR_BSSID3_V1_8814B(x) | BIT_BSSID3_V1_8814B(v))
+
+/* 2 REG_BSSID3_H_8814B (BSSID3 REGISTER) */
+
+#define BIT_SHIFT_BSSID3_H_V1_8814B 0
+#define BIT_MASK_BSSID3_H_V1_8814B 0xffff
+#define BIT_BSSID3_H_V1_8814B(x)                                               \
+	(((x) & BIT_MASK_BSSID3_H_V1_8814B) << BIT_SHIFT_BSSID3_H_V1_8814B)
+#define BITS_BSSID3_H_V1_8814B                                                 \
+	(BIT_MASK_BSSID3_H_V1_8814B << BIT_SHIFT_BSSID3_H_V1_8814B)
+#define BIT_CLEAR_BSSID3_H_V1_8814B(x) ((x) & (~BITS_BSSID3_H_V1_8814B))
+#define BIT_GET_BSSID3_H_V1_8814B(x)                                           \
+	(((x) >> BIT_SHIFT_BSSID3_H_V1_8814B) & BIT_MASK_BSSID3_H_V1_8814B)
+#define BIT_SET_BSSID3_H_V1_8814B(x, v)                                        \
+	(BIT_CLEAR_BSSID3_H_V1_8814B(x) | BIT_BSSID3_H_V1_8814B(v))
+
+/* 2 REG_MACID4_8814B (MAC ID4 REGISTER) */
+
+#define BIT_SHIFT_MACID4_V1_8814B 0
+#define BIT_MASK_MACID4_V1_8814B 0xffffffffL
+#define BIT_MACID4_V1_8814B(x)                                                 \
+	(((x) & BIT_MASK_MACID4_V1_8814B) << BIT_SHIFT_MACID4_V1_8814B)
+#define BITS_MACID4_V1_8814B                                                   \
+	(BIT_MASK_MACID4_V1_8814B << BIT_SHIFT_MACID4_V1_8814B)
+#define BIT_CLEAR_MACID4_V1_8814B(x) ((x) & (~BITS_MACID4_V1_8814B))
+#define BIT_GET_MACID4_V1_8814B(x)                                             \
+	(((x) >> BIT_SHIFT_MACID4_V1_8814B) & BIT_MASK_MACID4_V1_8814B)
+#define BIT_SET_MACID4_V1_8814B(x, v)                                          \
+	(BIT_CLEAR_MACID4_V1_8814B(x) | BIT_MACID4_V1_8814B(v))
+
+/* 2 REG_MACID4_H_8814B (MAC ID4 REGISTER) */
+
+#define BIT_SHIFT_MACID4_H_V1_8814B 0
+#define BIT_MASK_MACID4_H_V1_8814B 0xffff
+#define BIT_MACID4_H_V1_8814B(x)                                               \
+	(((x) & BIT_MASK_MACID4_H_V1_8814B) << BIT_SHIFT_MACID4_H_V1_8814B)
+#define BITS_MACID4_H_V1_8814B                                                 \
+	(BIT_MASK_MACID4_H_V1_8814B << BIT_SHIFT_MACID4_H_V1_8814B)
+#define BIT_CLEAR_MACID4_H_V1_8814B(x) ((x) & (~BITS_MACID4_H_V1_8814B))
+#define BIT_GET_MACID4_H_V1_8814B(x)                                           \
+	(((x) >> BIT_SHIFT_MACID4_H_V1_8814B) & BIT_MASK_MACID4_H_V1_8814B)
+#define BIT_SET_MACID4_H_V1_8814B(x, v)                                        \
+	(BIT_CLEAR_MACID4_H_V1_8814B(x) | BIT_MACID4_H_V1_8814B(v))
+
+/* 2 REG_BSSID4_8814B (BSSID4 REGISTER) */
+
+#define BIT_SHIFT_BSSID4_V1_8814B 0
+#define BIT_MASK_BSSID4_V1_8814B 0xffffffffL
+#define BIT_BSSID4_V1_8814B(x)                                                 \
+	(((x) & BIT_MASK_BSSID4_V1_8814B) << BIT_SHIFT_BSSID4_V1_8814B)
+#define BITS_BSSID4_V1_8814B                                                   \
+	(BIT_MASK_BSSID4_V1_8814B << BIT_SHIFT_BSSID4_V1_8814B)
+#define BIT_CLEAR_BSSID4_V1_8814B(x) ((x) & (~BITS_BSSID4_V1_8814B))
+#define BIT_GET_BSSID4_V1_8814B(x)                                             \
+	(((x) >> BIT_SHIFT_BSSID4_V1_8814B) & BIT_MASK_BSSID4_V1_8814B)
+#define BIT_SET_BSSID4_V1_8814B(x, v)                                          \
+	(BIT_CLEAR_BSSID4_V1_8814B(x) | BIT_BSSID4_V1_8814B(v))
+
+/* 2 REG_BSSID4_H_8814B (BSSID4 REGISTER) */
+
+#define BIT_SHIFT_BSSID4_H_V1_8814B 0
+#define BIT_MASK_BSSID4_H_V1_8814B 0xffff
+#define BIT_BSSID4_H_V1_8814B(x)                                               \
+	(((x) & BIT_MASK_BSSID4_H_V1_8814B) << BIT_SHIFT_BSSID4_H_V1_8814B)
+#define BITS_BSSID4_H_V1_8814B                                                 \
+	(BIT_MASK_BSSID4_H_V1_8814B << BIT_SHIFT_BSSID4_H_V1_8814B)
+#define BIT_CLEAR_BSSID4_H_V1_8814B(x) ((x) & (~BITS_BSSID4_H_V1_8814B))
+#define BIT_GET_BSSID4_H_V1_8814B(x)                                           \
+	(((x) >> BIT_SHIFT_BSSID4_H_V1_8814B) & BIT_MASK_BSSID4_H_V1_8814B)
+#define BIT_SET_BSSID4_H_V1_8814B(x, v)                                        \
+	(BIT_CLEAR_BSSID4_H_V1_8814B(x) | BIT_BSSID4_H_V1_8814B(v))
+
+/* 2 REG_NOA_REPORT_8814B */
+
+#define BIT_SHIFT_NOA_RPT_8814B 0
+#define BIT_MASK_NOA_RPT_8814B 0xffffffffL
+#define BIT_NOA_RPT_8814B(x)                                                   \
+	(((x) & BIT_MASK_NOA_RPT_8814B) << BIT_SHIFT_NOA_RPT_8814B)
+#define BITS_NOA_RPT_8814B (BIT_MASK_NOA_RPT_8814B << BIT_SHIFT_NOA_RPT_8814B)
+#define BIT_CLEAR_NOA_RPT_8814B(x) ((x) & (~BITS_NOA_RPT_8814B))
+#define BIT_GET_NOA_RPT_8814B(x)                                               \
+	(((x) >> BIT_SHIFT_NOA_RPT_8814B) & BIT_MASK_NOA_RPT_8814B)
+#define BIT_SET_NOA_RPT_8814B(x, v)                                            \
+	(BIT_CLEAR_NOA_RPT_8814B(x) | BIT_NOA_RPT_8814B(v))
+
+/* 2 REG_NOA_REPORT_1_8814B */
+
+#define BIT_SHIFT_NOA_RPT_1_8814B 0
+#define BIT_MASK_NOA_RPT_1_8814B 0xffffffffL
+#define BIT_NOA_RPT_1_8814B(x)                                                 \
+	(((x) & BIT_MASK_NOA_RPT_1_8814B) << BIT_SHIFT_NOA_RPT_1_8814B)
+#define BITS_NOA_RPT_1_8814B                                                   \
+	(BIT_MASK_NOA_RPT_1_8814B << BIT_SHIFT_NOA_RPT_1_8814B)
+#define BIT_CLEAR_NOA_RPT_1_8814B(x) ((x) & (~BITS_NOA_RPT_1_8814B))
+#define BIT_GET_NOA_RPT_1_8814B(x)                                             \
+	(((x) >> BIT_SHIFT_NOA_RPT_1_8814B) & BIT_MASK_NOA_RPT_1_8814B)
+#define BIT_SET_NOA_RPT_1_8814B(x, v)                                          \
+	(BIT_CLEAR_NOA_RPT_1_8814B(x) | BIT_NOA_RPT_1_8814B(v))
+
+/* 2 REG_NOA_REPORT_2_8814B */
+
+#define BIT_SHIFT_NOA_RPT_2_8814B 0
+#define BIT_MASK_NOA_RPT_2_8814B 0xffffffffL
+#define BIT_NOA_RPT_2_8814B(x)                                                 \
+	(((x) & BIT_MASK_NOA_RPT_2_8814B) << BIT_SHIFT_NOA_RPT_2_8814B)
+#define BITS_NOA_RPT_2_8814B                                                   \
+	(BIT_MASK_NOA_RPT_2_8814B << BIT_SHIFT_NOA_RPT_2_8814B)
+#define BIT_CLEAR_NOA_RPT_2_8814B(x) ((x) & (~BITS_NOA_RPT_2_8814B))
+#define BIT_GET_NOA_RPT_2_8814B(x)                                             \
+	(((x) >> BIT_SHIFT_NOA_RPT_2_8814B) & BIT_MASK_NOA_RPT_2_8814B)
+#define BIT_SET_NOA_RPT_2_8814B(x, v)                                          \
+	(BIT_CLEAR_NOA_RPT_2_8814B(x) | BIT_NOA_RPT_2_8814B(v))
+
+/* 2 REG_NOA_REPORT_3_8814B */
+
+#define BIT_SHIFT_NOA_RPT_3_8814B 0
+#define BIT_MASK_NOA_RPT_3_8814B 0xff
+#define BIT_NOA_RPT_3_8814B(x)                                                 \
+	(((x) & BIT_MASK_NOA_RPT_3_8814B) << BIT_SHIFT_NOA_RPT_3_8814B)
+#define BITS_NOA_RPT_3_8814B                                                   \
+	(BIT_MASK_NOA_RPT_3_8814B << BIT_SHIFT_NOA_RPT_3_8814B)
+#define BIT_CLEAR_NOA_RPT_3_8814B(x) ((x) & (~BITS_NOA_RPT_3_8814B))
+#define BIT_GET_NOA_RPT_3_8814B(x)                                             \
+	(((x) >> BIT_SHIFT_NOA_RPT_3_8814B) & BIT_MASK_NOA_RPT_3_8814B)
+#define BIT_SET_NOA_RPT_3_8814B(x, v)                                          \
+	(BIT_CLEAR_NOA_RPT_3_8814B(x) | BIT_NOA_RPT_3_8814B(v))
+
+/* 2 REG_PWRBIT_SETTING_8814B */
+#define BIT_CLI3_WMAC_TCRPWRMGT_HWCTL_EN_8814B BIT(15)
+#define BIT_CLI3_WMAC_TCRPWRMGT_HWDATA_EN_8814B BIT(14)
+#define BIT_CLI3_WMAC_TCRPWRMGT_HWACT_EN_8814B BIT(13)
+#define BIT_CLI3_PWR_ST_V1_8814B BIT(12)
+#define BIT_CLI2_WMAC_TCRPWRMGT_HWCTL_EN_8814B BIT(11)
+#define BIT_CLI2_WMAC_TCRPWRMGT_HWDATA_EN_8814B BIT(10)
+#define BIT_CLI2_WMAC_TCRPWRMGT_HWACT_EN_8814B BIT(9)
+#define BIT_CLI2_PWR_ST_V1_8814B BIT(8)
+#define BIT_CLI1_WMAC_TCRPWRMGT_HWCTL_EN_8814B BIT(7)
+#define BIT_CLI1_WMAC_TCRPWRMGT_HWDATA_EN_8814B BIT(6)
+#define BIT_CLI1_WMAC_TCRPWRMGT_HWACT_EN_8814B BIT(5)
+#define BIT_CLI1_PWR_ST_V1_8814B BIT(4)
+#define BIT_CLI0_WMAC_TCRPWRMGT_HWCTL_EN_8814B BIT(3)
+#define BIT_CLI0_WMAC_TCRPWRMGT_HWDATA_EN_8814B BIT(2)
+#define BIT_CLI0_WMAC_TCRPWRMGT_HWACT_EN_8814B BIT(1)
+#define BIT_CLI0_PWR_ST_V1_8814B BIT(0)
+
+/* 2 REG_GENERAL_OPTION_8814B */
+#define BIT_FIX_MSDU_TAIL_WR_8814B BIT(12)
+#define BIT_FIX_MSDU_SHIFT_8814B BIT(11)
+#define BIT_RXFIFO_GNT_CUT_8814B BIT(8)
+#define BIT_WMAC_FIX_FIRST_MPDU_WITH_PHYSTS_8814B BIT(5)
+#define BIT_DUMMY_RXD_FCS_ERROR_MASK_EN_8814B BIT(4)
+#define BIT_PATTERN_MATCH_FIX_EN_8814B BIT(3)
+#define BIT_TXSERV_FIELD_SEL_8814B BIT(2)
+#define BIT_RXVHT_LEN_SEL_8814B BIT(1)
+#define BIT_RXMIC_PROTECT_EN_8814B BIT(0)
+
+/* 2 REG_FWPHYFF_RCR_8814B */
+#define BIT_RCR2_AAMSDU_8814B BIT(25)
+#define BIT_RCR2_CBSSID_BCN_8814B BIT(24)
+#define BIT_RCR2_ACRC32_8814B BIT(23)
+#define BIT_RCR2_TA_BCN_8814B BIT(22)
+#define BIT_RCR2_CBSSID_DATA_8814B BIT(21)
+#define BIT_RCR2_ADD3_8814B BIT(20)
+#define BIT_RCR2_AB_8814B BIT(19)
+#define BIT_RCR2_AM_8814B BIT(18)
+#define BIT_RCR2_APM_8814B BIT(17)
+#define BIT_RCR2_AAP_8814B BIT(16)
+#define BIT_RCR1_AAMSDU_8814B BIT(9)
+#define BIT_RCR1_CBSSID_BCN_8814B BIT(8)
+#define BIT_RCR1_ACRC32_8814B BIT(7)
+#define BIT_RCR1_TA_BCN_8814B BIT(6)
+#define BIT_RCR1_CBSSID_DATA_8814B BIT(5)
+#define BIT_RCR1_ADD3_8814B BIT(4)
+#define BIT_RCR1_AB_8814B BIT(3)
+#define BIT_RCR1_AM_8814B BIT(2)
+#define BIT_RCR1_APM_8814B BIT(1)
+#define BIT_RCR1_AAP_8814B BIT(0)
+
+/* 2 REG_ADDRCAM_WRITE_CONTENT_8814B */
+
+#define BIT_SHIFT_ADDRCAM_WDATA_8814B 0
+#define BIT_MASK_ADDRCAM_WDATA_8814B 0xffffffffL
+#define BIT_ADDRCAM_WDATA_8814B(x)                                             \
+	(((x) & BIT_MASK_ADDRCAM_WDATA_8814B) << BIT_SHIFT_ADDRCAM_WDATA_8814B)
+#define BITS_ADDRCAM_WDATA_8814B                                               \
+	(BIT_MASK_ADDRCAM_WDATA_8814B << BIT_SHIFT_ADDRCAM_WDATA_8814B)
+#define BIT_CLEAR_ADDRCAM_WDATA_8814B(x) ((x) & (~BITS_ADDRCAM_WDATA_8814B))
+#define BIT_GET_ADDRCAM_WDATA_8814B(x)                                         \
+	(((x) >> BIT_SHIFT_ADDRCAM_WDATA_8814B) & BIT_MASK_ADDRCAM_WDATA_8814B)
+#define BIT_SET_ADDRCAM_WDATA_8814B(x, v)                                      \
+	(BIT_CLEAR_ADDRCAM_WDATA_8814B(x) | BIT_ADDRCAM_WDATA_8814B(v))
+
+/* 2 REG_ADDRCAM_READ_CONTENT_8814B */
+
+#define BIT_SHIFT_ADDRCAM_RDATA_8814B 0
+#define BIT_MASK_ADDRCAM_RDATA_8814B 0xffffffffL
+#define BIT_ADDRCAM_RDATA_8814B(x)                                             \
+	(((x) & BIT_MASK_ADDRCAM_RDATA_8814B) << BIT_SHIFT_ADDRCAM_RDATA_8814B)
+#define BITS_ADDRCAM_RDATA_8814B                                               \
+	(BIT_MASK_ADDRCAM_RDATA_8814B << BIT_SHIFT_ADDRCAM_RDATA_8814B)
+#define BIT_CLEAR_ADDRCAM_RDATA_8814B(x) ((x) & (~BITS_ADDRCAM_RDATA_8814B))
+#define BIT_GET_ADDRCAM_RDATA_8814B(x)                                         \
+	(((x) >> BIT_SHIFT_ADDRCAM_RDATA_8814B) & BIT_MASK_ADDRCAM_RDATA_8814B)
+#define BIT_SET_ADDRCAM_RDATA_8814B(x, v)                                      \
+	(BIT_CLEAR_ADDRCAM_RDATA_8814B(x) | BIT_ADDRCAM_RDATA_8814B(v))
+
+/* 2 REG_ADDRCAM_CFG_8814B */
+#define BIT_ADDRCAM_POLL_8814B BIT(31)
+#define BIT__ADDRCAM_WT_EN_8814B BIT(30)
+#define BIT_CLRADDRCAM_8814B BIT(29)
+
+#define BIT_SHIFT__ADDRCAM_ADDR_8814B 8
+#define BIT_MASK__ADDRCAM_ADDR_8814B 0x3ff
+#define BIT__ADDRCAM_ADDR_8814B(x)                                             \
+	(((x) & BIT_MASK__ADDRCAM_ADDR_8814B) << BIT_SHIFT__ADDRCAM_ADDR_8814B)
+#define BITS__ADDRCAM_ADDR_8814B                                               \
+	(BIT_MASK__ADDRCAM_ADDR_8814B << BIT_SHIFT__ADDRCAM_ADDR_8814B)
+#define BIT_CLEAR__ADDRCAM_ADDR_8814B(x) ((x) & (~BITS__ADDRCAM_ADDR_8814B))
+#define BIT_GET__ADDRCAM_ADDR_8814B(x)                                         \
+	(((x) >> BIT_SHIFT__ADDRCAM_ADDR_8814B) & BIT_MASK__ADDRCAM_ADDR_8814B)
+#define BIT_SET__ADDRCAM_ADDR_8814B(x, v)                                      \
+	(BIT_CLEAR__ADDRCAM_ADDR_8814B(x) | BIT__ADDRCAM_ADDR_8814B(v))
+
+#define BIT_SHIFT_ADDRCAM_RANGE_8814B 0
+#define BIT_MASK_ADDRCAM_RANGE_8814B 0x7f
+#define BIT_ADDRCAM_RANGE_8814B(x)                                             \
+	(((x) & BIT_MASK_ADDRCAM_RANGE_8814B) << BIT_SHIFT_ADDRCAM_RANGE_8814B)
+#define BITS_ADDRCAM_RANGE_8814B                                               \
+	(BIT_MASK_ADDRCAM_RANGE_8814B << BIT_SHIFT_ADDRCAM_RANGE_8814B)
+#define BIT_CLEAR_ADDRCAM_RANGE_8814B(x) ((x) & (~BITS_ADDRCAM_RANGE_8814B))
+#define BIT_GET_ADDRCAM_RANGE_8814B(x)                                         \
+	(((x) >> BIT_SHIFT_ADDRCAM_RANGE_8814B) & BIT_MASK_ADDRCAM_RANGE_8814B)
+#define BIT_SET_ADDRCAM_RANGE_8814B(x, v)                                      \
+	(BIT_CLEAR_ADDRCAM_RANGE_8814B(x) | BIT_ADDRCAM_RANGE_8814B(v))
+
+/* 2 REG_CSI_RRSR_8814B */
+#define BIT_CSI_LDPC_EN_8814B BIT(29)
+#define BIT_CSI_STBC_EN_8814B BIT(28)
+
+#define BIT_SHIFT_CSI_RRSC_BITMAP_8814B 4
+#define BIT_MASK_CSI_RRSC_BITMAP_8814B 0xffffff
+#define BIT_CSI_RRSC_BITMAP_8814B(x)                                           \
+	(((x) & BIT_MASK_CSI_RRSC_BITMAP_8814B)                                \
+	 << BIT_SHIFT_CSI_RRSC_BITMAP_8814B)
+#define BITS_CSI_RRSC_BITMAP_8814B                                             \
+	(BIT_MASK_CSI_RRSC_BITMAP_8814B << BIT_SHIFT_CSI_RRSC_BITMAP_8814B)
+#define BIT_CLEAR_CSI_RRSC_BITMAP_8814B(x) ((x) & (~BITS_CSI_RRSC_BITMAP_8814B))
+#define BIT_GET_CSI_RRSC_BITMAP_8814B(x)                                       \
+	(((x) >> BIT_SHIFT_CSI_RRSC_BITMAP_8814B) &                            \
+	 BIT_MASK_CSI_RRSC_BITMAP_8814B)
+#define BIT_SET_CSI_RRSC_BITMAP_8814B(x, v)                                    \
+	(BIT_CLEAR_CSI_RRSC_BITMAP_8814B(x) | BIT_CSI_RRSC_BITMAP_8814B(v))
+
+#define BIT_SHIFT_OFDM_LEN_TH_8814B 0
+#define BIT_MASK_OFDM_LEN_TH_8814B 0xf
+#define BIT_OFDM_LEN_TH_8814B(x)                                               \
+	(((x) & BIT_MASK_OFDM_LEN_TH_8814B) << BIT_SHIFT_OFDM_LEN_TH_8814B)
+#define BITS_OFDM_LEN_TH_8814B                                                 \
+	(BIT_MASK_OFDM_LEN_TH_8814B << BIT_SHIFT_OFDM_LEN_TH_8814B)
+#define BIT_CLEAR_OFDM_LEN_TH_8814B(x) ((x) & (~BITS_OFDM_LEN_TH_8814B))
+#define BIT_GET_OFDM_LEN_TH_8814B(x)                                           \
+	(((x) >> BIT_SHIFT_OFDM_LEN_TH_8814B) & BIT_MASK_OFDM_LEN_TH_8814B)
+#define BIT_SET_OFDM_LEN_TH_8814B(x, v)                                        \
+	(BIT_CLEAR_OFDM_LEN_TH_8814B(x) | BIT_OFDM_LEN_TH_8814B(v))
+
+/* 2 REG_MU_BF_OPTION_8814B */
+#define BIT_WMAC_RESP_NONSTA1_DIS_8814B BIT(7)
+#define BIT_WMAC_TXMU_ACKPOLICY_EN_8814B BIT(6)
+
+#define BIT_SHIFT_WMAC_TXMU_ACKPOLICY_8814B 4
+#define BIT_MASK_WMAC_TXMU_ACKPOLICY_8814B 0x3
+#define BIT_WMAC_TXMU_ACKPOLICY_8814B(x)                                       \
+	(((x) & BIT_MASK_WMAC_TXMU_ACKPOLICY_8814B)                            \
+	 << BIT_SHIFT_WMAC_TXMU_ACKPOLICY_8814B)
+#define BITS_WMAC_TXMU_ACKPOLICY_8814B                                         \
+	(BIT_MASK_WMAC_TXMU_ACKPOLICY_8814B                                    \
+	 << BIT_SHIFT_WMAC_TXMU_ACKPOLICY_8814B)
+#define BIT_CLEAR_WMAC_TXMU_ACKPOLICY_8814B(x)                                 \
+	((x) & (~BITS_WMAC_TXMU_ACKPOLICY_8814B))
+#define BIT_GET_WMAC_TXMU_ACKPOLICY_8814B(x)                                   \
+	(((x) >> BIT_SHIFT_WMAC_TXMU_ACKPOLICY_8814B) &                        \
+	 BIT_MASK_WMAC_TXMU_ACKPOLICY_8814B)
+#define BIT_SET_WMAC_TXMU_ACKPOLICY_8814B(x, v)                                \
+	(BIT_CLEAR_WMAC_TXMU_ACKPOLICY_8814B(x) |                              \
+	 BIT_WMAC_TXMU_ACKPOLICY_8814B(v))
+
+#define BIT_SHIFT_WMAC_MU_BFEE_PORT_SEL_8814B 1
+#define BIT_MASK_WMAC_MU_BFEE_PORT_SEL_8814B 0x7
+#define BIT_WMAC_MU_BFEE_PORT_SEL_8814B(x)                                     \
+	(((x) & BIT_MASK_WMAC_MU_BFEE_PORT_SEL_8814B)                          \
+	 << BIT_SHIFT_WMAC_MU_BFEE_PORT_SEL_8814B)
+#define BITS_WMAC_MU_BFEE_PORT_SEL_8814B                                       \
+	(BIT_MASK_WMAC_MU_BFEE_PORT_SEL_8814B                                  \
+	 << BIT_SHIFT_WMAC_MU_BFEE_PORT_SEL_8814B)
+#define BIT_CLEAR_WMAC_MU_BFEE_PORT_SEL_8814B(x)                               \
+	((x) & (~BITS_WMAC_MU_BFEE_PORT_SEL_8814B))
+#define BIT_GET_WMAC_MU_BFEE_PORT_SEL_8814B(x)                                 \
+	(((x) >> BIT_SHIFT_WMAC_MU_BFEE_PORT_SEL_8814B) &                      \
+	 BIT_MASK_WMAC_MU_BFEE_PORT_SEL_8814B)
+#define BIT_SET_WMAC_MU_BFEE_PORT_SEL_8814B(x, v)                              \
+	(BIT_CLEAR_WMAC_MU_BFEE_PORT_SEL_8814B(x) |                            \
+	 BIT_WMAC_MU_BFEE_PORT_SEL_8814B(v))
+
+#define BIT_WMAC_MU_BFEE_DIS_8814B BIT(0)
+
+/* 2 REG_WMAC_PAUSE_BB_CLR_TH_8814B */
+
+#define BIT_SHIFT_WMAC_PAUSE_BB_CLR_TH_8814B 0
+#define BIT_MASK_WMAC_PAUSE_BB_CLR_TH_8814B 0xff
+#define BIT_WMAC_PAUSE_BB_CLR_TH_8814B(x)                                      \
+	(((x) & BIT_MASK_WMAC_PAUSE_BB_CLR_TH_8814B)                           \
+	 << BIT_SHIFT_WMAC_PAUSE_BB_CLR_TH_8814B)
+#define BITS_WMAC_PAUSE_BB_CLR_TH_8814B                                        \
+	(BIT_MASK_WMAC_PAUSE_BB_CLR_TH_8814B                                   \
+	 << BIT_SHIFT_WMAC_PAUSE_BB_CLR_TH_8814B)
+#define BIT_CLEAR_WMAC_PAUSE_BB_CLR_TH_8814B(x)                                \
+	((x) & (~BITS_WMAC_PAUSE_BB_CLR_TH_8814B))
+#define BIT_GET_WMAC_PAUSE_BB_CLR_TH_8814B(x)                                  \
+	(((x) >> BIT_SHIFT_WMAC_PAUSE_BB_CLR_TH_8814B) &                       \
+	 BIT_MASK_WMAC_PAUSE_BB_CLR_TH_8814B)
+#define BIT_SET_WMAC_PAUSE_BB_CLR_TH_8814B(x, v)                               \
+	(BIT_CLEAR_WMAC_PAUSE_BB_CLR_TH_8814B(x) |                             \
+	 BIT_WMAC_PAUSE_BB_CLR_TH_8814B(v))
+
+/* 2 REG_WMAC_MULBK_BUF_8814B */
+
+#define BIT_SHIFT_WMAC_MULBK_PAGE_SIZE_8814B 0
+#define BIT_MASK_WMAC_MULBK_PAGE_SIZE_8814B 0xff
+#define BIT_WMAC_MULBK_PAGE_SIZE_8814B(x)                                      \
+	(((x) & BIT_MASK_WMAC_MULBK_PAGE_SIZE_8814B)                           \
+	 << BIT_SHIFT_WMAC_MULBK_PAGE_SIZE_8814B)
+#define BITS_WMAC_MULBK_PAGE_SIZE_8814B                                        \
+	(BIT_MASK_WMAC_MULBK_PAGE_SIZE_8814B                                   \
+	 << BIT_SHIFT_WMAC_MULBK_PAGE_SIZE_8814B)
+#define BIT_CLEAR_WMAC_MULBK_PAGE_SIZE_8814B(x)                                \
+	((x) & (~BITS_WMAC_MULBK_PAGE_SIZE_8814B))
+#define BIT_GET_WMAC_MULBK_PAGE_SIZE_8814B(x)                                  \
+	(((x) >> BIT_SHIFT_WMAC_MULBK_PAGE_SIZE_8814B) &                       \
+	 BIT_MASK_WMAC_MULBK_PAGE_SIZE_8814B)
+#define BIT_SET_WMAC_MULBK_PAGE_SIZE_8814B(x, v)                               \
+	(BIT_CLEAR_WMAC_MULBK_PAGE_SIZE_8814B(x) |                             \
+	 BIT_WMAC_MULBK_PAGE_SIZE_8814B(v))
+
+/* 2 REG_WMAC_MU_OPTION_8814B */
+#define BIT_NOCHK_BFPOLL_BMP_8814B BIT(7)
+
+/* 2 REG_WMAC_MU_BF_CTL_8814B */
+#define BIT_WMAC_INVLD_BFPRT_CHK_8814B BIT(15)
+#define BIT_WMAC_RETXBFRPTSEQ_UPD_8814B BIT(14)
+
+#define BIT_SHIFT_WMAC_MU_BFRPTSEG_SEL_8814B 12
+#define BIT_MASK_WMAC_MU_BFRPTSEG_SEL_8814B 0x3
+#define BIT_WMAC_MU_BFRPTSEG_SEL_8814B(x)                                      \
+	(((x) & BIT_MASK_WMAC_MU_BFRPTSEG_SEL_8814B)                           \
+	 << BIT_SHIFT_WMAC_MU_BFRPTSEG_SEL_8814B)
+#define BITS_WMAC_MU_BFRPTSEG_SEL_8814B                                        \
+	(BIT_MASK_WMAC_MU_BFRPTSEG_SEL_8814B                                   \
+	 << BIT_SHIFT_WMAC_MU_BFRPTSEG_SEL_8814B)
+#define BIT_CLEAR_WMAC_MU_BFRPTSEG_SEL_8814B(x)                                \
+	((x) & (~BITS_WMAC_MU_BFRPTSEG_SEL_8814B))
+#define BIT_GET_WMAC_MU_BFRPTSEG_SEL_8814B(x)                                  \
+	(((x) >> BIT_SHIFT_WMAC_MU_BFRPTSEG_SEL_8814B) &                       \
+	 BIT_MASK_WMAC_MU_BFRPTSEG_SEL_8814B)
+#define BIT_SET_WMAC_MU_BFRPTSEG_SEL_8814B(x, v)                               \
+	(BIT_CLEAR_WMAC_MU_BFRPTSEG_SEL_8814B(x) |                             \
+	 BIT_WMAC_MU_BFRPTSEG_SEL_8814B(v))
+
+#define BIT_SHIFT_WMAC_MU_BF_MYAID_8814B 0
+#define BIT_MASK_WMAC_MU_BF_MYAID_8814B 0xfff
+#define BIT_WMAC_MU_BF_MYAID_8814B(x)                                          \
+	(((x) & BIT_MASK_WMAC_MU_BF_MYAID_8814B)                               \
+	 << BIT_SHIFT_WMAC_MU_BF_MYAID_8814B)
+#define BITS_WMAC_MU_BF_MYAID_8814B                                            \
+	(BIT_MASK_WMAC_MU_BF_MYAID_8814B << BIT_SHIFT_WMAC_MU_BF_MYAID_8814B)
+#define BIT_CLEAR_WMAC_MU_BF_MYAID_8814B(x)                                    \
+	((x) & (~BITS_WMAC_MU_BF_MYAID_8814B))
+#define BIT_GET_WMAC_MU_BF_MYAID_8814B(x)                                      \
+	(((x) >> BIT_SHIFT_WMAC_MU_BF_MYAID_8814B) &                           \
+	 BIT_MASK_WMAC_MU_BF_MYAID_8814B)
+#define BIT_SET_WMAC_MU_BF_MYAID_8814B(x, v)                                   \
+	(BIT_CLEAR_WMAC_MU_BF_MYAID_8814B(x) | BIT_WMAC_MU_BF_MYAID_8814B(v))
+
+/* 2 REG_WMAC_MU_BFRPT_PARA_8814B */
+
+#define BIT_SHIFT_BFRPT_PARA_USERID_SEL_V1_8814B 13
+#define BIT_MASK_BFRPT_PARA_USERID_SEL_V1_8814B 0x7
+#define BIT_BFRPT_PARA_USERID_SEL_V1_8814B(x)                                  \
+	(((x) & BIT_MASK_BFRPT_PARA_USERID_SEL_V1_8814B)                       \
+	 << BIT_SHIFT_BFRPT_PARA_USERID_SEL_V1_8814B)
+#define BITS_BFRPT_PARA_USERID_SEL_V1_8814B                                    \
+	(BIT_MASK_BFRPT_PARA_USERID_SEL_V1_8814B                               \
+	 << BIT_SHIFT_BFRPT_PARA_USERID_SEL_V1_8814B)
+#define BIT_CLEAR_BFRPT_PARA_USERID_SEL_V1_8814B(x)                            \
+	((x) & (~BITS_BFRPT_PARA_USERID_SEL_V1_8814B))
+#define BIT_GET_BFRPT_PARA_USERID_SEL_V1_8814B(x)                              \
+	(((x) >> BIT_SHIFT_BFRPT_PARA_USERID_SEL_V1_8814B) &                   \
+	 BIT_MASK_BFRPT_PARA_USERID_SEL_V1_8814B)
+#define BIT_SET_BFRPT_PARA_USERID_SEL_V1_8814B(x, v)                           \
+	(BIT_CLEAR_BFRPT_PARA_USERID_SEL_V1_8814B(x) |                         \
+	 BIT_BFRPT_PARA_USERID_SEL_V1_8814B(v))
+
+#define BIT_SHIFT_BFRPT_PARA_V1_8814B 0
+#define BIT_MASK_BFRPT_PARA_V1_8814B 0x1fff
+#define BIT_BFRPT_PARA_V1_8814B(x)                                             \
+	(((x) & BIT_MASK_BFRPT_PARA_V1_8814B) << BIT_SHIFT_BFRPT_PARA_V1_8814B)
+#define BITS_BFRPT_PARA_V1_8814B                                               \
+	(BIT_MASK_BFRPT_PARA_V1_8814B << BIT_SHIFT_BFRPT_PARA_V1_8814B)
+#define BIT_CLEAR_BFRPT_PARA_V1_8814B(x) ((x) & (~BITS_BFRPT_PARA_V1_8814B))
+#define BIT_GET_BFRPT_PARA_V1_8814B(x)                                         \
+	(((x) >> BIT_SHIFT_BFRPT_PARA_V1_8814B) & BIT_MASK_BFRPT_PARA_V1_8814B)
+#define BIT_SET_BFRPT_PARA_V1_8814B(x, v)                                      \
+	(BIT_CLEAR_BFRPT_PARA_V1_8814B(x) | BIT_BFRPT_PARA_V1_8814B(v))
+
+/* 2 REG_WMAC_ASSOCIATED_MU_BFMEE2_8814B */
+#define BIT_STATUS_BFEE2_8814B BIT(10)
+#define BIT_WMAC_MU_BFEE2_EN_8814B BIT(9)
+
+#define BIT_SHIFT_WMAC_MU_BFEE2_AID_8814B 0
+#define BIT_MASK_WMAC_MU_BFEE2_AID_8814B 0x1ff
+#define BIT_WMAC_MU_BFEE2_AID_8814B(x)                                         \
+	(((x) & BIT_MASK_WMAC_MU_BFEE2_AID_8814B)                              \
+	 << BIT_SHIFT_WMAC_MU_BFEE2_AID_8814B)
+#define BITS_WMAC_MU_BFEE2_AID_8814B                                           \
+	(BIT_MASK_WMAC_MU_BFEE2_AID_8814B << BIT_SHIFT_WMAC_MU_BFEE2_AID_8814B)
+#define BIT_CLEAR_WMAC_MU_BFEE2_AID_8814B(x)                                   \
+	((x) & (~BITS_WMAC_MU_BFEE2_AID_8814B))
+#define BIT_GET_WMAC_MU_BFEE2_AID_8814B(x)                                     \
+	(((x) >> BIT_SHIFT_WMAC_MU_BFEE2_AID_8814B) &                          \
+	 BIT_MASK_WMAC_MU_BFEE2_AID_8814B)
+#define BIT_SET_WMAC_MU_BFEE2_AID_8814B(x, v)                                  \
+	(BIT_CLEAR_WMAC_MU_BFEE2_AID_8814B(x) | BIT_WMAC_MU_BFEE2_AID_8814B(v))
+
+/* 2 REG_WMAC_ASSOCIATED_MU_BFMEE3_8814B */
+#define BIT_STATUS_BFEE3_8814B BIT(10)
+#define BIT_WMAC_MU_BFEE3_EN_8814B BIT(9)
+
+#define BIT_SHIFT_WMAC_MU_BFEE3_AID_8814B 0
+#define BIT_MASK_WMAC_MU_BFEE3_AID_8814B 0x1ff
+#define BIT_WMAC_MU_BFEE3_AID_8814B(x)                                         \
+	(((x) & BIT_MASK_WMAC_MU_BFEE3_AID_8814B)                              \
+	 << BIT_SHIFT_WMAC_MU_BFEE3_AID_8814B)
+#define BITS_WMAC_MU_BFEE3_AID_8814B                                           \
+	(BIT_MASK_WMAC_MU_BFEE3_AID_8814B << BIT_SHIFT_WMAC_MU_BFEE3_AID_8814B)
+#define BIT_CLEAR_WMAC_MU_BFEE3_AID_8814B(x)                                   \
+	((x) & (~BITS_WMAC_MU_BFEE3_AID_8814B))
+#define BIT_GET_WMAC_MU_BFEE3_AID_8814B(x)                                     \
+	(((x) >> BIT_SHIFT_WMAC_MU_BFEE3_AID_8814B) &                          \
+	 BIT_MASK_WMAC_MU_BFEE3_AID_8814B)
+#define BIT_SET_WMAC_MU_BFEE3_AID_8814B(x, v)                                  \
+	(BIT_CLEAR_WMAC_MU_BFEE3_AID_8814B(x) | BIT_WMAC_MU_BFEE3_AID_8814B(v))
+
+/* 2 REG_WMAC_ASSOCIATED_MU_BFMEE4_8814B */
+#define BIT_STATUS_BFEE4_8814B BIT(10)
+#define BIT_WMAC_MU_BFEE4_EN_8814B BIT(9)
+
+#define BIT_SHIFT_WMAC_MU_BFEE4_AID_8814B 0
+#define BIT_MASK_WMAC_MU_BFEE4_AID_8814B 0x1ff
+#define BIT_WMAC_MU_BFEE4_AID_8814B(x)                                         \
+	(((x) & BIT_MASK_WMAC_MU_BFEE4_AID_8814B)                              \
+	 << BIT_SHIFT_WMAC_MU_BFEE4_AID_8814B)
+#define BITS_WMAC_MU_BFEE4_AID_8814B                                           \
+	(BIT_MASK_WMAC_MU_BFEE4_AID_8814B << BIT_SHIFT_WMAC_MU_BFEE4_AID_8814B)
+#define BIT_CLEAR_WMAC_MU_BFEE4_AID_8814B(x)                                   \
+	((x) & (~BITS_WMAC_MU_BFEE4_AID_8814B))
+#define BIT_GET_WMAC_MU_BFEE4_AID_8814B(x)                                     \
+	(((x) >> BIT_SHIFT_WMAC_MU_BFEE4_AID_8814B) &                          \
+	 BIT_MASK_WMAC_MU_BFEE4_AID_8814B)
+#define BIT_SET_WMAC_MU_BFEE4_AID_8814B(x, v)                                  \
+	(BIT_CLEAR_WMAC_MU_BFEE4_AID_8814B(x) | BIT_WMAC_MU_BFEE4_AID_8814B(v))
+
+/* 2 REG_WMAC_ASSOCIATED_MU_BFMEE5_8814B */
+#define BIT_BIT_STATUS_BFEE5_8814B BIT(10)
+#define BIT_WMAC_MU_BFEE5_EN_8814B BIT(9)
+
+#define BIT_SHIFT_WMAC_MU_BFEE5_AID_8814B 0
+#define BIT_MASK_WMAC_MU_BFEE5_AID_8814B 0x1ff
+#define BIT_WMAC_MU_BFEE5_AID_8814B(x)                                         \
+	(((x) & BIT_MASK_WMAC_MU_BFEE5_AID_8814B)                              \
+	 << BIT_SHIFT_WMAC_MU_BFEE5_AID_8814B)
+#define BITS_WMAC_MU_BFEE5_AID_8814B                                           \
+	(BIT_MASK_WMAC_MU_BFEE5_AID_8814B << BIT_SHIFT_WMAC_MU_BFEE5_AID_8814B)
+#define BIT_CLEAR_WMAC_MU_BFEE5_AID_8814B(x)                                   \
+	((x) & (~BITS_WMAC_MU_BFEE5_AID_8814B))
+#define BIT_GET_WMAC_MU_BFEE5_AID_8814B(x)                                     \
+	(((x) >> BIT_SHIFT_WMAC_MU_BFEE5_AID_8814B) &                          \
+	 BIT_MASK_WMAC_MU_BFEE5_AID_8814B)
+#define BIT_SET_WMAC_MU_BFEE5_AID_8814B(x, v)                                  \
+	(BIT_CLEAR_WMAC_MU_BFEE5_AID_8814B(x) | BIT_WMAC_MU_BFEE5_AID_8814B(v))
+
+/* 2 REG_WMAC_ASSOCIATED_MU_BFMEE6_8814B */
+#define BIT_STATUS_BFEE6_8814B BIT(10)
+#define BIT_WMAC_MU_BFEE6_EN_8814B BIT(9)
+
+#define BIT_SHIFT_WMAC_MU_BFEE6_AID_8814B 0
+#define BIT_MASK_WMAC_MU_BFEE6_AID_8814B 0x1ff
+#define BIT_WMAC_MU_BFEE6_AID_8814B(x)                                         \
+	(((x) & BIT_MASK_WMAC_MU_BFEE6_AID_8814B)                              \
+	 << BIT_SHIFT_WMAC_MU_BFEE6_AID_8814B)
+#define BITS_WMAC_MU_BFEE6_AID_8814B                                           \
+	(BIT_MASK_WMAC_MU_BFEE6_AID_8814B << BIT_SHIFT_WMAC_MU_BFEE6_AID_8814B)
+#define BIT_CLEAR_WMAC_MU_BFEE6_AID_8814B(x)                                   \
+	((x) & (~BITS_WMAC_MU_BFEE6_AID_8814B))
+#define BIT_GET_WMAC_MU_BFEE6_AID_8814B(x)                                     \
+	(((x) >> BIT_SHIFT_WMAC_MU_BFEE6_AID_8814B) &                          \
+	 BIT_MASK_WMAC_MU_BFEE6_AID_8814B)
+#define BIT_SET_WMAC_MU_BFEE6_AID_8814B(x, v)                                  \
+	(BIT_CLEAR_WMAC_MU_BFEE6_AID_8814B(x) | BIT_WMAC_MU_BFEE6_AID_8814B(v))
+
+/* 2 REG_WMAC_ASSOCIATED_MU_BFMEE7_8814B */
+#define BIT_STATUS_BFEE7_8814B BIT(10)
+#define BIT_WMAC_MU_BFEE7_EN_8814B BIT(9)
+
+#define BIT_SHIFT_WMAC_MU_BFEE7_AID_8814B 0
+#define BIT_MASK_WMAC_MU_BFEE7_AID_8814B 0x1ff
+#define BIT_WMAC_MU_BFEE7_AID_8814B(x)                                         \
+	(((x) & BIT_MASK_WMAC_MU_BFEE7_AID_8814B)                              \
+	 << BIT_SHIFT_WMAC_MU_BFEE7_AID_8814B)
+#define BITS_WMAC_MU_BFEE7_AID_8814B                                           \
+	(BIT_MASK_WMAC_MU_BFEE7_AID_8814B << BIT_SHIFT_WMAC_MU_BFEE7_AID_8814B)
+#define BIT_CLEAR_WMAC_MU_BFEE7_AID_8814B(x)                                   \
+	((x) & (~BITS_WMAC_MU_BFEE7_AID_8814B))
+#define BIT_GET_WMAC_MU_BFEE7_AID_8814B(x)                                     \
+	(((x) >> BIT_SHIFT_WMAC_MU_BFEE7_AID_8814B) &                          \
+	 BIT_MASK_WMAC_MU_BFEE7_AID_8814B)
+#define BIT_SET_WMAC_MU_BFEE7_AID_8814B(x, v)                                  \
+	(BIT_CLEAR_WMAC_MU_BFEE7_AID_8814B(x) | BIT_WMAC_MU_BFEE7_AID_8814B(v))
+
+/* 2 REG_WMAC_BB_STOP_RX_COUNTER_8814B */
+#define BIT_RST_ALL_COUNTER_8814B BIT(31)
+
+#define BIT_SHIFT_ABORT_RX_VBON_COUNTER_8814B 16
+#define BIT_MASK_ABORT_RX_VBON_COUNTER_8814B 0xff
+#define BIT_ABORT_RX_VBON_COUNTER_8814B(x)                                     \
+	(((x) & BIT_MASK_ABORT_RX_VBON_COUNTER_8814B)                          \
+	 << BIT_SHIFT_ABORT_RX_VBON_COUNTER_8814B)
+#define BITS_ABORT_RX_VBON_COUNTER_8814B                                       \
+	(BIT_MASK_ABORT_RX_VBON_COUNTER_8814B                                  \
+	 << BIT_SHIFT_ABORT_RX_VBON_COUNTER_8814B)
+#define BIT_CLEAR_ABORT_RX_VBON_COUNTER_8814B(x)                               \
+	((x) & (~BITS_ABORT_RX_VBON_COUNTER_8814B))
+#define BIT_GET_ABORT_RX_VBON_COUNTER_8814B(x)                                 \
+	(((x) >> BIT_SHIFT_ABORT_RX_VBON_COUNTER_8814B) &                      \
+	 BIT_MASK_ABORT_RX_VBON_COUNTER_8814B)
+#define BIT_SET_ABORT_RX_VBON_COUNTER_8814B(x, v)                              \
+	(BIT_CLEAR_ABORT_RX_VBON_COUNTER_8814B(x) |                            \
+	 BIT_ABORT_RX_VBON_COUNTER_8814B(v))
+
+#define BIT_SHIFT_ABORT_RX_RDRDY_COUNTER_8814B 8
+#define BIT_MASK_ABORT_RX_RDRDY_COUNTER_8814B 0xff
+#define BIT_ABORT_RX_RDRDY_COUNTER_8814B(x)                                    \
+	(((x) & BIT_MASK_ABORT_RX_RDRDY_COUNTER_8814B)                         \
+	 << BIT_SHIFT_ABORT_RX_RDRDY_COUNTER_8814B)
+#define BITS_ABORT_RX_RDRDY_COUNTER_8814B                                      \
+	(BIT_MASK_ABORT_RX_RDRDY_COUNTER_8814B                                 \
+	 << BIT_SHIFT_ABORT_RX_RDRDY_COUNTER_8814B)
+#define BIT_CLEAR_ABORT_RX_RDRDY_COUNTER_8814B(x)                              \
+	((x) & (~BITS_ABORT_RX_RDRDY_COUNTER_8814B))
+#define BIT_GET_ABORT_RX_RDRDY_COUNTER_8814B(x)                                \
+	(((x) >> BIT_SHIFT_ABORT_RX_RDRDY_COUNTER_8814B) &                     \
+	 BIT_MASK_ABORT_RX_RDRDY_COUNTER_8814B)
+#define BIT_SET_ABORT_RX_RDRDY_COUNTER_8814B(x, v)                             \
+	(BIT_CLEAR_ABORT_RX_RDRDY_COUNTER_8814B(x) |                           \
+	 BIT_ABORT_RX_RDRDY_COUNTER_8814B(v))
+
+#define BIT_SHIFT_VBON_EARLY_FALLING_COUNTER_8814B 0
+#define BIT_MASK_VBON_EARLY_FALLING_COUNTER_8814B 0xff
+#define BIT_VBON_EARLY_FALLING_COUNTER_8814B(x)                                \
+	(((x) & BIT_MASK_VBON_EARLY_FALLING_COUNTER_8814B)                     \
+	 << BIT_SHIFT_VBON_EARLY_FALLING_COUNTER_8814B)
+#define BITS_VBON_EARLY_FALLING_COUNTER_8814B                                  \
+	(BIT_MASK_VBON_EARLY_FALLING_COUNTER_8814B                             \
+	 << BIT_SHIFT_VBON_EARLY_FALLING_COUNTER_8814B)
+#define BIT_CLEAR_VBON_EARLY_FALLING_COUNTER_8814B(x)                          \
+	((x) & (~BITS_VBON_EARLY_FALLING_COUNTER_8814B))
+#define BIT_GET_VBON_EARLY_FALLING_COUNTER_8814B(x)                            \
+	(((x) >> BIT_SHIFT_VBON_EARLY_FALLING_COUNTER_8814B) &                 \
+	 BIT_MASK_VBON_EARLY_FALLING_COUNTER_8814B)
+#define BIT_SET_VBON_EARLY_FALLING_COUNTER_8814B(x, v)                         \
+	(BIT_CLEAR_VBON_EARLY_FALLING_COUNTER_8814B(x) |                       \
+	 BIT_VBON_EARLY_FALLING_COUNTER_8814B(v))
+
+/* 2 REG_WMAC_PLCP_MONITOR_8814B */
+#define BIT_WMAC_PLCP_TRX_SEL_8814B BIT(31)
+
+#define BIT_SHIFT_WMAC_PLCP_RDSIG_SEL_8814B 28
+#define BIT_MASK_WMAC_PLCP_RDSIG_SEL_8814B 0x7
+#define BIT_WMAC_PLCP_RDSIG_SEL_8814B(x)                                       \
+	(((x) & BIT_MASK_WMAC_PLCP_RDSIG_SEL_8814B)                            \
+	 << BIT_SHIFT_WMAC_PLCP_RDSIG_SEL_8814B)
+#define BITS_WMAC_PLCP_RDSIG_SEL_8814B                                         \
+	(BIT_MASK_WMAC_PLCP_RDSIG_SEL_8814B                                    \
+	 << BIT_SHIFT_WMAC_PLCP_RDSIG_SEL_8814B)
+#define BIT_CLEAR_WMAC_PLCP_RDSIG_SEL_8814B(x)                                 \
+	((x) & (~BITS_WMAC_PLCP_RDSIG_SEL_8814B))
+#define BIT_GET_WMAC_PLCP_RDSIG_SEL_8814B(x)                                   \
+	(((x) >> BIT_SHIFT_WMAC_PLCP_RDSIG_SEL_8814B) &                        \
+	 BIT_MASK_WMAC_PLCP_RDSIG_SEL_8814B)
+#define BIT_SET_WMAC_PLCP_RDSIG_SEL_8814B(x, v)                                \
+	(BIT_CLEAR_WMAC_PLCP_RDSIG_SEL_8814B(x) |                              \
+	 BIT_WMAC_PLCP_RDSIG_SEL_8814B(v))
+
+#define BIT_SHIFT_WMAC_RATE_IDX_8814B 24
+#define BIT_MASK_WMAC_RATE_IDX_8814B 0xf
+#define BIT_WMAC_RATE_IDX_8814B(x)                                             \
+	(((x) & BIT_MASK_WMAC_RATE_IDX_8814B) << BIT_SHIFT_WMAC_RATE_IDX_8814B)
+#define BITS_WMAC_RATE_IDX_8814B                                               \
+	(BIT_MASK_WMAC_RATE_IDX_8814B << BIT_SHIFT_WMAC_RATE_IDX_8814B)
+#define BIT_CLEAR_WMAC_RATE_IDX_8814B(x) ((x) & (~BITS_WMAC_RATE_IDX_8814B))
+#define BIT_GET_WMAC_RATE_IDX_8814B(x)                                         \
+	(((x) >> BIT_SHIFT_WMAC_RATE_IDX_8814B) & BIT_MASK_WMAC_RATE_IDX_8814B)
+#define BIT_SET_WMAC_RATE_IDX_8814B(x, v)                                      \
+	(BIT_CLEAR_WMAC_RATE_IDX_8814B(x) | BIT_WMAC_RATE_IDX_8814B(v))
+
+#define BIT_SHIFT_WMAC_PLCP_RDSIG_8814B 0
+#define BIT_MASK_WMAC_PLCP_RDSIG_8814B 0xffffff
+#define BIT_WMAC_PLCP_RDSIG_8814B(x)                                           \
+	(((x) & BIT_MASK_WMAC_PLCP_RDSIG_8814B)                                \
+	 << BIT_SHIFT_WMAC_PLCP_RDSIG_8814B)
+#define BITS_WMAC_PLCP_RDSIG_8814B                                             \
+	(BIT_MASK_WMAC_PLCP_RDSIG_8814B << BIT_SHIFT_WMAC_PLCP_RDSIG_8814B)
+#define BIT_CLEAR_WMAC_PLCP_RDSIG_8814B(x) ((x) & (~BITS_WMAC_PLCP_RDSIG_8814B))
+#define BIT_GET_WMAC_PLCP_RDSIG_8814B(x)                                       \
+	(((x) >> BIT_SHIFT_WMAC_PLCP_RDSIG_8814B) &                            \
+	 BIT_MASK_WMAC_PLCP_RDSIG_8814B)
+#define BIT_SET_WMAC_PLCP_RDSIG_8814B(x, v)                                    \
+	(BIT_CLEAR_WMAC_PLCP_RDSIG_8814B(x) | BIT_WMAC_PLCP_RDSIG_8814B(v))
+
+/* 2 REG_WMAC_DEBUG_PORT_8814B */
+
+#define BIT_SHIFT_WMAC_DEBUG_PORT_8814B 0
+#define BIT_MASK_WMAC_DEBUG_PORT_8814B 0xffffffffL
+#define BIT_WMAC_DEBUG_PORT_8814B(x)                                           \
+	(((x) & BIT_MASK_WMAC_DEBUG_PORT_8814B)                                \
+	 << BIT_SHIFT_WMAC_DEBUG_PORT_8814B)
+#define BITS_WMAC_DEBUG_PORT_8814B                                             \
+	(BIT_MASK_WMAC_DEBUG_PORT_8814B << BIT_SHIFT_WMAC_DEBUG_PORT_8814B)
+#define BIT_CLEAR_WMAC_DEBUG_PORT_8814B(x) ((x) & (~BITS_WMAC_DEBUG_PORT_8814B))
+#define BIT_GET_WMAC_DEBUG_PORT_8814B(x)                                       \
+	(((x) >> BIT_SHIFT_WMAC_DEBUG_PORT_8814B) &                            \
+	 BIT_MASK_WMAC_DEBUG_PORT_8814B)
+#define BIT_SET_WMAC_DEBUG_PORT_8814B(x, v)                                    \
+	(BIT_CLEAR_WMAC_DEBUG_PORT_8814B(x) | BIT_WMAC_DEBUG_PORT_8814B(v))
+
+/* 2 REG_RSVD_8814B */
+
+/* 2 REG_TRANSMIT_ADDRSS_0_8814B (TA0 REGISTER) */
+
+#define BIT_SHIFT_TA0_V1_8814B 0
+#define BIT_MASK_TA0_V1_8814B 0xffffffffL
+#define BIT_TA0_V1_8814B(x)                                                    \
+	(((x) & BIT_MASK_TA0_V1_8814B) << BIT_SHIFT_TA0_V1_8814B)
+#define BITS_TA0_V1_8814B (BIT_MASK_TA0_V1_8814B << BIT_SHIFT_TA0_V1_8814B)
+#define BIT_CLEAR_TA0_V1_8814B(x) ((x) & (~BITS_TA0_V1_8814B))
+#define BIT_GET_TA0_V1_8814B(x)                                                \
+	(((x) >> BIT_SHIFT_TA0_V1_8814B) & BIT_MASK_TA0_V1_8814B)
+#define BIT_SET_TA0_V1_8814B(x, v)                                             \
+	(BIT_CLEAR_TA0_V1_8814B(x) | BIT_TA0_V1_8814B(v))
+
+/* 2 REG_TRANSMIT_ADDRSS_0_H_8814B (TA0 REGISTER) */
+
+#define BIT_SHIFT_TA0_H_V1_8814B 0
+#define BIT_MASK_TA0_H_V1_8814B 0xffff
+#define BIT_TA0_H_V1_8814B(x)                                                  \
+	(((x) & BIT_MASK_TA0_H_V1_8814B) << BIT_SHIFT_TA0_H_V1_8814B)
+#define BITS_TA0_H_V1_8814B                                                    \
+	(BIT_MASK_TA0_H_V1_8814B << BIT_SHIFT_TA0_H_V1_8814B)
+#define BIT_CLEAR_TA0_H_V1_8814B(x) ((x) & (~BITS_TA0_H_V1_8814B))
+#define BIT_GET_TA0_H_V1_8814B(x)                                              \
+	(((x) >> BIT_SHIFT_TA0_H_V1_8814B) & BIT_MASK_TA0_H_V1_8814B)
+#define BIT_SET_TA0_H_V1_8814B(x, v)                                           \
+	(BIT_CLEAR_TA0_H_V1_8814B(x) | BIT_TA0_H_V1_8814B(v))
+
+/* 2 REG_TRANSMIT_ADDRSS_1_8814B (TA1 REGISTER) */
+
+#define BIT_SHIFT_TA1_V1_8814B 0
+#define BIT_MASK_TA1_V1_8814B 0xffffffffL
+#define BIT_TA1_V1_8814B(x)                                                    \
+	(((x) & BIT_MASK_TA1_V1_8814B) << BIT_SHIFT_TA1_V1_8814B)
+#define BITS_TA1_V1_8814B (BIT_MASK_TA1_V1_8814B << BIT_SHIFT_TA1_V1_8814B)
+#define BIT_CLEAR_TA1_V1_8814B(x) ((x) & (~BITS_TA1_V1_8814B))
+#define BIT_GET_TA1_V1_8814B(x)                                                \
+	(((x) >> BIT_SHIFT_TA1_V1_8814B) & BIT_MASK_TA1_V1_8814B)
+#define BIT_SET_TA1_V1_8814B(x, v)                                             \
+	(BIT_CLEAR_TA1_V1_8814B(x) | BIT_TA1_V1_8814B(v))
+
+/* 2 REG_TRANSMIT_ADDRSS_1_H_8814B (TA1 REGISTER) */
+
+#define BIT_SHIFT_TA1_H_V1_8814B 0
+#define BIT_MASK_TA1_H_V1_8814B 0xffff
+#define BIT_TA1_H_V1_8814B(x)                                                  \
+	(((x) & BIT_MASK_TA1_H_V1_8814B) << BIT_SHIFT_TA1_H_V1_8814B)
+#define BITS_TA1_H_V1_8814B                                                    \
+	(BIT_MASK_TA1_H_V1_8814B << BIT_SHIFT_TA1_H_V1_8814B)
+#define BIT_CLEAR_TA1_H_V1_8814B(x) ((x) & (~BITS_TA1_H_V1_8814B))
+#define BIT_GET_TA1_H_V1_8814B(x)                                              \
+	(((x) >> BIT_SHIFT_TA1_H_V1_8814B) & BIT_MASK_TA1_H_V1_8814B)
+#define BIT_SET_TA1_H_V1_8814B(x, v)                                           \
+	(BIT_CLEAR_TA1_H_V1_8814B(x) | BIT_TA1_H_V1_8814B(v))
+
+/* 2 REG_TRANSMIT_ADDRSS_2_8814B (TA2 REGISTER) */
+
+#define BIT_SHIFT_TA2_V1_8814B 0
+#define BIT_MASK_TA2_V1_8814B 0xffffffffL
+#define BIT_TA2_V1_8814B(x)                                                    \
+	(((x) & BIT_MASK_TA2_V1_8814B) << BIT_SHIFT_TA2_V1_8814B)
+#define BITS_TA2_V1_8814B (BIT_MASK_TA2_V1_8814B << BIT_SHIFT_TA2_V1_8814B)
+#define BIT_CLEAR_TA2_V1_8814B(x) ((x) & (~BITS_TA2_V1_8814B))
+#define BIT_GET_TA2_V1_8814B(x)                                                \
+	(((x) >> BIT_SHIFT_TA2_V1_8814B) & BIT_MASK_TA2_V1_8814B)
+#define BIT_SET_TA2_V1_8814B(x, v)                                             \
+	(BIT_CLEAR_TA2_V1_8814B(x) | BIT_TA2_V1_8814B(v))
+
+/* 2 REG_TRANSMIT_ADDRSS_2_H_8814B (TA2 REGISTER) */
+
+#define BIT_SHIFT_TA2_H_V1_8814B 0
+#define BIT_MASK_TA2_H_V1_8814B 0xffff
+#define BIT_TA2_H_V1_8814B(x)                                                  \
+	(((x) & BIT_MASK_TA2_H_V1_8814B) << BIT_SHIFT_TA2_H_V1_8814B)
+#define BITS_TA2_H_V1_8814B                                                    \
+	(BIT_MASK_TA2_H_V1_8814B << BIT_SHIFT_TA2_H_V1_8814B)
+#define BIT_CLEAR_TA2_H_V1_8814B(x) ((x) & (~BITS_TA2_H_V1_8814B))
+#define BIT_GET_TA2_H_V1_8814B(x)                                              \
+	(((x) >> BIT_SHIFT_TA2_H_V1_8814B) & BIT_MASK_TA2_H_V1_8814B)
+#define BIT_SET_TA2_H_V1_8814B(x, v)                                           \
+	(BIT_CLEAR_TA2_H_V1_8814B(x) | BIT_TA2_H_V1_8814B(v))
+
+/* 2 REG_TRANSMIT_ADDRSS_3_8814B (TA3 REGISTER) */
+
+#define BIT_SHIFT_TA2_V1_8814B 0
+#define BIT_MASK_TA2_V1_8814B 0xffffffffL
+#define BIT_TA2_V1_8814B(x)                                                    \
+	(((x) & BIT_MASK_TA2_V1_8814B) << BIT_SHIFT_TA2_V1_8814B)
+#define BITS_TA2_V1_8814B (BIT_MASK_TA2_V1_8814B << BIT_SHIFT_TA2_V1_8814B)
+#define BIT_CLEAR_TA2_V1_8814B(x) ((x) & (~BITS_TA2_V1_8814B))
+#define BIT_GET_TA2_V1_8814B(x)                                                \
+	(((x) >> BIT_SHIFT_TA2_V1_8814B) & BIT_MASK_TA2_V1_8814B)
+#define BIT_SET_TA2_V1_8814B(x, v)                                             \
+	(BIT_CLEAR_TA2_V1_8814B(x) | BIT_TA2_V1_8814B(v))
+
+/* 2 REG_TRANSMIT_ADDRSS_3_H_8814B (TA3 REGISTER) */
+
+#define BIT_SHIFT_TA3_H_V1_8814B 0
+#define BIT_MASK_TA3_H_V1_8814B 0xffff
+#define BIT_TA3_H_V1_8814B(x)                                                  \
+	(((x) & BIT_MASK_TA3_H_V1_8814B) << BIT_SHIFT_TA3_H_V1_8814B)
+#define BITS_TA3_H_V1_8814B                                                    \
+	(BIT_MASK_TA3_H_V1_8814B << BIT_SHIFT_TA3_H_V1_8814B)
+#define BIT_CLEAR_TA3_H_V1_8814B(x) ((x) & (~BITS_TA3_H_V1_8814B))
+#define BIT_GET_TA3_H_V1_8814B(x)                                              \
+	(((x) >> BIT_SHIFT_TA3_H_V1_8814B) & BIT_MASK_TA3_H_V1_8814B)
+#define BIT_SET_TA3_H_V1_8814B(x, v)                                           \
+	(BIT_CLEAR_TA3_H_V1_8814B(x) | BIT_TA3_H_V1_8814B(v))
+
+/* 2 REG_TRANSMIT_ADDRSS_4_8814B (TA4 REGISTER) */
+
+#define BIT_SHIFT_TA4_V1_8814B 0
+#define BIT_MASK_TA4_V1_8814B 0xffffffffL
+#define BIT_TA4_V1_8814B(x)                                                    \
+	(((x) & BIT_MASK_TA4_V1_8814B) << BIT_SHIFT_TA4_V1_8814B)
+#define BITS_TA4_V1_8814B (BIT_MASK_TA4_V1_8814B << BIT_SHIFT_TA4_V1_8814B)
+#define BIT_CLEAR_TA4_V1_8814B(x) ((x) & (~BITS_TA4_V1_8814B))
+#define BIT_GET_TA4_V1_8814B(x)                                                \
+	(((x) >> BIT_SHIFT_TA4_V1_8814B) & BIT_MASK_TA4_V1_8814B)
+#define BIT_SET_TA4_V1_8814B(x, v)                                             \
+	(BIT_CLEAR_TA4_V1_8814B(x) | BIT_TA4_V1_8814B(v))
+
+/* 2 REG_TRANSMIT_ADDRSS_4_H_8814B (TA4 REGISTER) */
+
+#define BIT_SHIFT_TA4_H_V1_8814B 0
+#define BIT_MASK_TA4_H_V1_8814B 0xffff
+#define BIT_TA4_H_V1_8814B(x)                                                  \
+	(((x) & BIT_MASK_TA4_H_V1_8814B) << BIT_SHIFT_TA4_H_V1_8814B)
+#define BITS_TA4_H_V1_8814B                                                    \
+	(BIT_MASK_TA4_H_V1_8814B << BIT_SHIFT_TA4_H_V1_8814B)
+#define BIT_CLEAR_TA4_H_V1_8814B(x) ((x) & (~BITS_TA4_H_V1_8814B))
+#define BIT_GET_TA4_H_V1_8814B(x)                                              \
+	(((x) >> BIT_SHIFT_TA4_H_V1_8814B) & BIT_MASK_TA4_H_V1_8814B)
+#define BIT_SET_TA4_H_V1_8814B(x, v)                                           \
+	(BIT_CLEAR_TA4_H_V1_8814B(x) | BIT_TA4_H_V1_8814B(v))
+
+/* 2 REG_RSVD_8814B */
+
+/* 2 REG_RSVD_8814B */
+
+/* 2 REG_RSVD_8814B */
+
+/* 2 REG_RSVD_8814B */
+
+/* 2 REG_RSVD_8814B */
+
+/* 2 REG_RSVD_8814B */
+
+/* 2 REG_RSVD_8814B */
+
+/* 2 REG_RSVD_8814B */
+
+/* 2 REG_RSVD_8814B */
+
+/* 2 REG_RSVD_8814B */
+
+/* 2 REG_RSVD_8814B */
+
+/* 2 REG_RSVD_8814B */
+
+/* 2 REG_RSVD_8814B */
+
+/* 2 REG_RSVD_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_MACID1_8814B */
+
+#define BIT_SHIFT_MACID1_0_8814B 0
+#define BIT_MASK_MACID1_0_8814B 0xffffffffL
+#define BIT_MACID1_0_8814B(x)                                                  \
+	(((x) & BIT_MASK_MACID1_0_8814B) << BIT_SHIFT_MACID1_0_8814B)
+#define BITS_MACID1_0_8814B                                                    \
+	(BIT_MASK_MACID1_0_8814B << BIT_SHIFT_MACID1_0_8814B)
+#define BIT_CLEAR_MACID1_0_8814B(x) ((x) & (~BITS_MACID1_0_8814B))
+#define BIT_GET_MACID1_0_8814B(x)                                              \
+	(((x) >> BIT_SHIFT_MACID1_0_8814B) & BIT_MASK_MACID1_0_8814B)
+#define BIT_SET_MACID1_0_8814B(x, v)                                           \
+	(BIT_CLEAR_MACID1_0_8814B(x) | BIT_MACID1_0_8814B(v))
+
+/* 2 REG_MACID1_1_8814B */
+
+#define BIT_SHIFT_MACID1_1_8814B 0
+#define BIT_MASK_MACID1_1_8814B 0xffff
+#define BIT_MACID1_1_8814B(x)                                                  \
+	(((x) & BIT_MASK_MACID1_1_8814B) << BIT_SHIFT_MACID1_1_8814B)
+#define BITS_MACID1_1_8814B                                                    \
+	(BIT_MASK_MACID1_1_8814B << BIT_SHIFT_MACID1_1_8814B)
+#define BIT_CLEAR_MACID1_1_8814B(x) ((x) & (~BITS_MACID1_1_8814B))
+#define BIT_GET_MACID1_1_8814B(x)                                              \
+	(((x) >> BIT_SHIFT_MACID1_1_8814B) & BIT_MASK_MACID1_1_8814B)
+#define BIT_SET_MACID1_1_8814B(x, v)                                           \
+	(BIT_CLEAR_MACID1_1_8814B(x) | BIT_MACID1_1_8814B(v))
+
+/* 2 REG_BSSID1_8814B */
+
+#define BIT_SHIFT_BSSID1_0_8814B 0
+#define BIT_MASK_BSSID1_0_8814B 0xffffffffL
+#define BIT_BSSID1_0_8814B(x)                                                  \
+	(((x) & BIT_MASK_BSSID1_0_8814B) << BIT_SHIFT_BSSID1_0_8814B)
+#define BITS_BSSID1_0_8814B                                                    \
+	(BIT_MASK_BSSID1_0_8814B << BIT_SHIFT_BSSID1_0_8814B)
+#define BIT_CLEAR_BSSID1_0_8814B(x) ((x) & (~BITS_BSSID1_0_8814B))
+#define BIT_GET_BSSID1_0_8814B(x)                                              \
+	(((x) >> BIT_SHIFT_BSSID1_0_8814B) & BIT_MASK_BSSID1_0_8814B)
+#define BIT_SET_BSSID1_0_8814B(x, v)                                           \
+	(BIT_CLEAR_BSSID1_0_8814B(x) | BIT_BSSID1_0_8814B(v))
+
+/* 2 REG_BSSID1_1_8814B */
+
+#define BIT_SHIFT_BSSID1_1_8814B 0
+#define BIT_MASK_BSSID1_1_8814B 0xffff
+#define BIT_BSSID1_1_8814B(x)                                                  \
+	(((x) & BIT_MASK_BSSID1_1_8814B) << BIT_SHIFT_BSSID1_1_8814B)
+#define BITS_BSSID1_1_8814B                                                    \
+	(BIT_MASK_BSSID1_1_8814B << BIT_SHIFT_BSSID1_1_8814B)
+#define BIT_CLEAR_BSSID1_1_8814B(x) ((x) & (~BITS_BSSID1_1_8814B))
+#define BIT_GET_BSSID1_1_8814B(x)                                              \
+	(((x) >> BIT_SHIFT_BSSID1_1_8814B) & BIT_MASK_BSSID1_1_8814B)
+#define BIT_SET_BSSID1_1_8814B(x, v)                                           \
+	(BIT_CLEAR_BSSID1_1_8814B(x) | BIT_BSSID1_1_8814B(v))
+
+/* 2 REG_BCN_PSR_RPT1_8814B */
+
+#define BIT_SHIFT_DTIM_CNT1_8814B 24
+#define BIT_MASK_DTIM_CNT1_8814B 0xff
+#define BIT_DTIM_CNT1_8814B(x)                                                 \
+	(((x) & BIT_MASK_DTIM_CNT1_8814B) << BIT_SHIFT_DTIM_CNT1_8814B)
+#define BITS_DTIM_CNT1_8814B                                                   \
+	(BIT_MASK_DTIM_CNT1_8814B << BIT_SHIFT_DTIM_CNT1_8814B)
+#define BIT_CLEAR_DTIM_CNT1_8814B(x) ((x) & (~BITS_DTIM_CNT1_8814B))
+#define BIT_GET_DTIM_CNT1_8814B(x)                                             \
+	(((x) >> BIT_SHIFT_DTIM_CNT1_8814B) & BIT_MASK_DTIM_CNT1_8814B)
+#define BIT_SET_DTIM_CNT1_8814B(x, v)                                          \
+	(BIT_CLEAR_DTIM_CNT1_8814B(x) | BIT_DTIM_CNT1_8814B(v))
+
+#define BIT_SHIFT_DTIM_PERIOD1_8814B 16
+#define BIT_MASK_DTIM_PERIOD1_8814B 0xff
+#define BIT_DTIM_PERIOD1_8814B(x)                                              \
+	(((x) & BIT_MASK_DTIM_PERIOD1_8814B) << BIT_SHIFT_DTIM_PERIOD1_8814B)
+#define BITS_DTIM_PERIOD1_8814B                                                \
+	(BIT_MASK_DTIM_PERIOD1_8814B << BIT_SHIFT_DTIM_PERIOD1_8814B)
+#define BIT_CLEAR_DTIM_PERIOD1_8814B(x) ((x) & (~BITS_DTIM_PERIOD1_8814B))
+#define BIT_GET_DTIM_PERIOD1_8814B(x)                                          \
+	(((x) >> BIT_SHIFT_DTIM_PERIOD1_8814B) & BIT_MASK_DTIM_PERIOD1_8814B)
+#define BIT_SET_DTIM_PERIOD1_8814B(x, v)                                       \
+	(BIT_CLEAR_DTIM_PERIOD1_8814B(x) | BIT_DTIM_PERIOD1_8814B(v))
+
+#define BIT_DTIM1_8814B BIT(15)
+#define BIT_TIM1_8814B BIT(14)
+
+#define BIT_SHIFT_PS_AID_1_8814B 0
+#define BIT_MASK_PS_AID_1_8814B 0x7ff
+#define BIT_PS_AID_1_8814B(x)                                                  \
+	(((x) & BIT_MASK_PS_AID_1_8814B) << BIT_SHIFT_PS_AID_1_8814B)
+#define BITS_PS_AID_1_8814B                                                    \
+	(BIT_MASK_PS_AID_1_8814B << BIT_SHIFT_PS_AID_1_8814B)
+#define BIT_CLEAR_PS_AID_1_8814B(x) ((x) & (~BITS_PS_AID_1_8814B))
+#define BIT_GET_PS_AID_1_8814B(x)                                              \
+	(((x) >> BIT_SHIFT_PS_AID_1_8814B) & BIT_MASK_PS_AID_1_8814B)
+#define BIT_SET_PS_AID_1_8814B(x, v)                                           \
+	(BIT_CLEAR_PS_AID_1_8814B(x) | BIT_PS_AID_1_8814B(v))
+
+/* 2 REG_ASSOCIATED_BFMEE_SEL_8814B */
+#define BIT_TXUSER_ID1_8814B BIT(25)
+
+#define BIT_SHIFT_AID1_8814B 16
+#define BIT_MASK_AID1_8814B 0x1ff
+#define BIT_AID1_8814B(x) (((x) & BIT_MASK_AID1_8814B) << BIT_SHIFT_AID1_8814B)
+#define BITS_AID1_8814B (BIT_MASK_AID1_8814B << BIT_SHIFT_AID1_8814B)
+#define BIT_CLEAR_AID1_8814B(x) ((x) & (~BITS_AID1_8814B))
+#define BIT_GET_AID1_8814B(x)                                                  \
+	(((x) >> BIT_SHIFT_AID1_8814B) & BIT_MASK_AID1_8814B)
+#define BIT_SET_AID1_8814B(x, v) (BIT_CLEAR_AID1_8814B(x) | BIT_AID1_8814B(v))
+
+#define BIT_TXUSER_ID0_8814B BIT(9)
+
+#define BIT_SHIFT_AID0_8814B 0
+#define BIT_MASK_AID0_8814B 0x1ff
+#define BIT_AID0_8814B(x) (((x) & BIT_MASK_AID0_8814B) << BIT_SHIFT_AID0_8814B)
+#define BITS_AID0_8814B (BIT_MASK_AID0_8814B << BIT_SHIFT_AID0_8814B)
+#define BIT_CLEAR_AID0_8814B(x) ((x) & (~BITS_AID0_8814B))
+#define BIT_GET_AID0_8814B(x)                                                  \
+	(((x) >> BIT_SHIFT_AID0_8814B) & BIT_MASK_AID0_8814B)
+#define BIT_SET_AID0_8814B(x, v) (BIT_CLEAR_AID0_8814B(x) | BIT_AID0_8814B(v))
+
+/* 2 REG_SND_PTCL_CTRL_8814B */
+
+#define BIT_SHIFT_NDP_RX_STANDBY_TIMER_8814B 24
+#define BIT_MASK_NDP_RX_STANDBY_TIMER_8814B 0xff
+#define BIT_NDP_RX_STANDBY_TIMER_8814B(x)                                      \
+	(((x) & BIT_MASK_NDP_RX_STANDBY_TIMER_8814B)                           \
+	 << BIT_SHIFT_NDP_RX_STANDBY_TIMER_8814B)
+#define BITS_NDP_RX_STANDBY_TIMER_8814B                                        \
+	(BIT_MASK_NDP_RX_STANDBY_TIMER_8814B                                   \
+	 << BIT_SHIFT_NDP_RX_STANDBY_TIMER_8814B)
+#define BIT_CLEAR_NDP_RX_STANDBY_TIMER_8814B(x)                                \
+	((x) & (~BITS_NDP_RX_STANDBY_TIMER_8814B))
+#define BIT_GET_NDP_RX_STANDBY_TIMER_8814B(x)                                  \
+	(((x) >> BIT_SHIFT_NDP_RX_STANDBY_TIMER_8814B) &                       \
+	 BIT_MASK_NDP_RX_STANDBY_TIMER_8814B)
+#define BIT_SET_NDP_RX_STANDBY_TIMER_8814B(x, v)                               \
+	(BIT_CLEAR_NDP_RX_STANDBY_TIMER_8814B(x) |                             \
+	 BIT_NDP_RX_STANDBY_TIMER_8814B(v))
+
+#define BIT_SHIFT_CSI_RPT_OFFSET_HT_8814B 16
+#define BIT_MASK_CSI_RPT_OFFSET_HT_8814B 0xff
+#define BIT_CSI_RPT_OFFSET_HT_8814B(x)                                         \
+	(((x) & BIT_MASK_CSI_RPT_OFFSET_HT_8814B)                              \
+	 << BIT_SHIFT_CSI_RPT_OFFSET_HT_8814B)
+#define BITS_CSI_RPT_OFFSET_HT_8814B                                           \
+	(BIT_MASK_CSI_RPT_OFFSET_HT_8814B << BIT_SHIFT_CSI_RPT_OFFSET_HT_8814B)
+#define BIT_CLEAR_CSI_RPT_OFFSET_HT_8814B(x)                                   \
+	((x) & (~BITS_CSI_RPT_OFFSET_HT_8814B))
+#define BIT_GET_CSI_RPT_OFFSET_HT_8814B(x)                                     \
+	(((x) >> BIT_SHIFT_CSI_RPT_OFFSET_HT_8814B) &                          \
+	 BIT_MASK_CSI_RPT_OFFSET_HT_8814B)
+#define BIT_SET_CSI_RPT_OFFSET_HT_8814B(x, v)                                  \
+	(BIT_CLEAR_CSI_RPT_OFFSET_HT_8814B(x) | BIT_CSI_RPT_OFFSET_HT_8814B(v))
+
+#define BIT_VHTNDP_RPTPOLL_CSI_STR_OFFSET_SEL_8814B BIT(15)
+#define BIT_R_WMAC_CSI_CHKSUM_DIS_8814B BIT(14)
+
+#define BIT_SHIFT_R_CSI_RPT_OFFSET_VHT_V1_8814B 8
+#define BIT_MASK_R_CSI_RPT_OFFSET_VHT_V1_8814B 0x3f
+#define BIT_R_CSI_RPT_OFFSET_VHT_V1_8814B(x)                                   \
+	(((x) & BIT_MASK_R_CSI_RPT_OFFSET_VHT_V1_8814B)                        \
+	 << BIT_SHIFT_R_CSI_RPT_OFFSET_VHT_V1_8814B)
+#define BITS_R_CSI_RPT_OFFSET_VHT_V1_8814B                                     \
+	(BIT_MASK_R_CSI_RPT_OFFSET_VHT_V1_8814B                                \
+	 << BIT_SHIFT_R_CSI_RPT_OFFSET_VHT_V1_8814B)
+#define BIT_CLEAR_R_CSI_RPT_OFFSET_VHT_V1_8814B(x)                             \
+	((x) & (~BITS_R_CSI_RPT_OFFSET_VHT_V1_8814B))
+#define BIT_GET_R_CSI_RPT_OFFSET_VHT_V1_8814B(x)                               \
+	(((x) >> BIT_SHIFT_R_CSI_RPT_OFFSET_VHT_V1_8814B) &                    \
+	 BIT_MASK_R_CSI_RPT_OFFSET_VHT_V1_8814B)
+#define BIT_SET_R_CSI_RPT_OFFSET_VHT_V1_8814B(x, v)                            \
+	(BIT_CLEAR_R_CSI_RPT_OFFSET_VHT_V1_8814B(x) |                          \
+	 BIT_R_CSI_RPT_OFFSET_VHT_V1_8814B(v))
+
+#define BIT_R_WMAC_USE_NSTS_8814B BIT(7)
+#define BIT_R_DISABLE_CHECK_VHTSIGB_CRC_8814B BIT(6)
+#define BIT_R_DISABLE_CHECK_VHTSIGA_CRC_8814B BIT(5)
+#define BIT_R_WMAC_BFPARAM_SEL_8814B BIT(4)
+#define BIT_R_WMAC_CSISEQ_SEL_8814B BIT(3)
+#define BIT_R_WMAC_CSI_WITHHTC_EN_8814B BIT(2)
+#define BIT_R_WMAC_HT_NDPA_EN_8814B BIT(1)
+#define BIT_R_WMAC_VHT_NDPA_EN_8814B BIT(0)
+
+/* 2 REG_RX_CSI_RPT_INFO_8814B */
+#define BIT_WRITE_ENABLE_8814B BIT(31)
+#define BIT_WMAC_CHECK_SOUNDING_SEQ_8814B BIT(30)
+
+#define BIT_SHIFT_VHTHT_MIMO_CTRL_FIELD_8814B 1
+#define BIT_MASK_VHTHT_MIMO_CTRL_FIELD_8814B 0xffffff
+#define BIT_VHTHT_MIMO_CTRL_FIELD_8814B(x)                                     \
+	(((x) & BIT_MASK_VHTHT_MIMO_CTRL_FIELD_8814B)                          \
+	 << BIT_SHIFT_VHTHT_MIMO_CTRL_FIELD_8814B)
+#define BITS_VHTHT_MIMO_CTRL_FIELD_8814B                                       \
+	(BIT_MASK_VHTHT_MIMO_CTRL_FIELD_8814B                                  \
+	 << BIT_SHIFT_VHTHT_MIMO_CTRL_FIELD_8814B)
+#define BIT_CLEAR_VHTHT_MIMO_CTRL_FIELD_8814B(x)                               \
+	((x) & (~BITS_VHTHT_MIMO_CTRL_FIELD_8814B))
+#define BIT_GET_VHTHT_MIMO_CTRL_FIELD_8814B(x)                                 \
+	(((x) >> BIT_SHIFT_VHTHT_MIMO_CTRL_FIELD_8814B) &                      \
+	 BIT_MASK_VHTHT_MIMO_CTRL_FIELD_8814B)
+#define BIT_SET_VHTHT_MIMO_CTRL_FIELD_8814B(x, v)                              \
+	(BIT_CLEAR_VHTHT_MIMO_CTRL_FIELD_8814B(x) |                            \
+	 BIT_VHTHT_MIMO_CTRL_FIELD_8814B(v))
+
+#define BIT_CSI_INTERRUPT_STATUS_8814B BIT(0)
+
+/* 2 REG_NS_ARP_CTRL_8814B */
+#define BIT_R_WMAC_NSARP_RSPEN_8814B BIT(15)
+#define BIT_R_WMAC_NSARP_RARP_8814B BIT(9)
+#define BIT_R_WMAC_NSARP_RIPV6_8814B BIT(8)
+
+#define BIT_SHIFT_R_WMAC_NSARP_MODEN_8814B 6
+#define BIT_MASK_R_WMAC_NSARP_MODEN_8814B 0x3
+#define BIT_R_WMAC_NSARP_MODEN_8814B(x)                                        \
+	(((x) & BIT_MASK_R_WMAC_NSARP_MODEN_8814B)                             \
+	 << BIT_SHIFT_R_WMAC_NSARP_MODEN_8814B)
+#define BITS_R_WMAC_NSARP_MODEN_8814B                                          \
+	(BIT_MASK_R_WMAC_NSARP_MODEN_8814B                                     \
+	 << BIT_SHIFT_R_WMAC_NSARP_MODEN_8814B)
+#define BIT_CLEAR_R_WMAC_NSARP_MODEN_8814B(x)                                  \
+	((x) & (~BITS_R_WMAC_NSARP_MODEN_8814B))
+#define BIT_GET_R_WMAC_NSARP_MODEN_8814B(x)                                    \
+	(((x) >> BIT_SHIFT_R_WMAC_NSARP_MODEN_8814B) &                         \
+	 BIT_MASK_R_WMAC_NSARP_MODEN_8814B)
+#define BIT_SET_R_WMAC_NSARP_MODEN_8814B(x, v)                                 \
+	(BIT_CLEAR_R_WMAC_NSARP_MODEN_8814B(x) |                               \
+	 BIT_R_WMAC_NSARP_MODEN_8814B(v))
+
+#define BIT_SHIFT_R_WMAC_NSARP_RSPFTP_8814B 4
+#define BIT_MASK_R_WMAC_NSARP_RSPFTP_8814B 0x3
+#define BIT_R_WMAC_NSARP_RSPFTP_8814B(x)                                       \
+	(((x) & BIT_MASK_R_WMAC_NSARP_RSPFTP_8814B)                            \
+	 << BIT_SHIFT_R_WMAC_NSARP_RSPFTP_8814B)
+#define BITS_R_WMAC_NSARP_RSPFTP_8814B                                         \
+	(BIT_MASK_R_WMAC_NSARP_RSPFTP_8814B                                    \
+	 << BIT_SHIFT_R_WMAC_NSARP_RSPFTP_8814B)
+#define BIT_CLEAR_R_WMAC_NSARP_RSPFTP_8814B(x)                                 \
+	((x) & (~BITS_R_WMAC_NSARP_RSPFTP_8814B))
+#define BIT_GET_R_WMAC_NSARP_RSPFTP_8814B(x)                                   \
+	(((x) >> BIT_SHIFT_R_WMAC_NSARP_RSPFTP_8814B) &                        \
+	 BIT_MASK_R_WMAC_NSARP_RSPFTP_8814B)
+#define BIT_SET_R_WMAC_NSARP_RSPFTP_8814B(x, v)                                \
+	(BIT_CLEAR_R_WMAC_NSARP_RSPFTP_8814B(x) |                              \
+	 BIT_R_WMAC_NSARP_RSPFTP_8814B(v))
+
+#define BIT_SHIFT_R_WMAC_NSARP_RSPSEC_8814B 0
+#define BIT_MASK_R_WMAC_NSARP_RSPSEC_8814B 0xf
+#define BIT_R_WMAC_NSARP_RSPSEC_8814B(x)                                       \
+	(((x) & BIT_MASK_R_WMAC_NSARP_RSPSEC_8814B)                            \
+	 << BIT_SHIFT_R_WMAC_NSARP_RSPSEC_8814B)
+#define BITS_R_WMAC_NSARP_RSPSEC_8814B                                         \
+	(BIT_MASK_R_WMAC_NSARP_RSPSEC_8814B                                    \
+	 << BIT_SHIFT_R_WMAC_NSARP_RSPSEC_8814B)
+#define BIT_CLEAR_R_WMAC_NSARP_RSPSEC_8814B(x)                                 \
+	((x) & (~BITS_R_WMAC_NSARP_RSPSEC_8814B))
+#define BIT_GET_R_WMAC_NSARP_RSPSEC_8814B(x)                                   \
+	(((x) >> BIT_SHIFT_R_WMAC_NSARP_RSPSEC_8814B) &                        \
+	 BIT_MASK_R_WMAC_NSARP_RSPSEC_8814B)
+#define BIT_SET_R_WMAC_NSARP_RSPSEC_8814B(x, v)                                \
+	(BIT_CLEAR_R_WMAC_NSARP_RSPSEC_8814B(x) |                              \
+	 BIT_R_WMAC_NSARP_RSPSEC_8814B(v))
+
+/* 2 REG_NS_ARP_INFO_8814B */
+#define BIT_REQ_IS_MCNS_8814B BIT(23)
+#define BIT_REQ_IS_UCNS_8814B BIT(22)
+#define BIT_REQ_IS_USNS_8814B BIT(21)
+#define BIT_REQ_IS_ARP_8814B BIT(20)
+#define BIT_EXPRSP_MH_WITHQC_8814B BIT(19)
+
+#define BIT_SHIFT_EXPRSP_SECTYPE_8814B 16
+#define BIT_MASK_EXPRSP_SECTYPE_8814B 0x7
+#define BIT_EXPRSP_SECTYPE_8814B(x)                                            \
+	(((x) & BIT_MASK_EXPRSP_SECTYPE_8814B)                                 \
+	 << BIT_SHIFT_EXPRSP_SECTYPE_8814B)
+#define BITS_EXPRSP_SECTYPE_8814B                                              \
+	(BIT_MASK_EXPRSP_SECTYPE_8814B << BIT_SHIFT_EXPRSP_SECTYPE_8814B)
+#define BIT_CLEAR_EXPRSP_SECTYPE_8814B(x) ((x) & (~BITS_EXPRSP_SECTYPE_8814B))
+#define BIT_GET_EXPRSP_SECTYPE_8814B(x)                                        \
+	(((x) >> BIT_SHIFT_EXPRSP_SECTYPE_8814B) &                             \
+	 BIT_MASK_EXPRSP_SECTYPE_8814B)
+#define BIT_SET_EXPRSP_SECTYPE_8814B(x, v)                                     \
+	(BIT_CLEAR_EXPRSP_SECTYPE_8814B(x) | BIT_EXPRSP_SECTYPE_8814B(v))
+
+#define BIT_SHIFT_EXPRSP_CHKSM_7_TO_0_8814B 8
+#define BIT_MASK_EXPRSP_CHKSM_7_TO_0_8814B 0xff
+#define BIT_EXPRSP_CHKSM_7_TO_0_8814B(x)                                       \
+	(((x) & BIT_MASK_EXPRSP_CHKSM_7_TO_0_8814B)                            \
+	 << BIT_SHIFT_EXPRSP_CHKSM_7_TO_0_8814B)
+#define BITS_EXPRSP_CHKSM_7_TO_0_8814B                                         \
+	(BIT_MASK_EXPRSP_CHKSM_7_TO_0_8814B                                    \
+	 << BIT_SHIFT_EXPRSP_CHKSM_7_TO_0_8814B)
+#define BIT_CLEAR_EXPRSP_CHKSM_7_TO_0_8814B(x)                                 \
+	((x) & (~BITS_EXPRSP_CHKSM_7_TO_0_8814B))
+#define BIT_GET_EXPRSP_CHKSM_7_TO_0_8814B(x)                                   \
+	(((x) >> BIT_SHIFT_EXPRSP_CHKSM_7_TO_0_8814B) &                        \
+	 BIT_MASK_EXPRSP_CHKSM_7_TO_0_8814B)
+#define BIT_SET_EXPRSP_CHKSM_7_TO_0_8814B(x, v)                                \
+	(BIT_CLEAR_EXPRSP_CHKSM_7_TO_0_8814B(x) |                              \
+	 BIT_EXPRSP_CHKSM_7_TO_0_8814B(v))
+
+#define BIT_SHIFT_EXPRSP_CHKSM_15_TO_8_8814B 0
+#define BIT_MASK_EXPRSP_CHKSM_15_TO_8_8814B 0xff
+#define BIT_EXPRSP_CHKSM_15_TO_8_8814B(x)                                      \
+	(((x) & BIT_MASK_EXPRSP_CHKSM_15_TO_8_8814B)                           \
+	 << BIT_SHIFT_EXPRSP_CHKSM_15_TO_8_8814B)
+#define BITS_EXPRSP_CHKSM_15_TO_8_8814B                                        \
+	(BIT_MASK_EXPRSP_CHKSM_15_TO_8_8814B                                   \
+	 << BIT_SHIFT_EXPRSP_CHKSM_15_TO_8_8814B)
+#define BIT_CLEAR_EXPRSP_CHKSM_15_TO_8_8814B(x)                                \
+	((x) & (~BITS_EXPRSP_CHKSM_15_TO_8_8814B))
+#define BIT_GET_EXPRSP_CHKSM_15_TO_8_8814B(x)                                  \
+	(((x) >> BIT_SHIFT_EXPRSP_CHKSM_15_TO_8_8814B) &                       \
+	 BIT_MASK_EXPRSP_CHKSM_15_TO_8_8814B)
+#define BIT_SET_EXPRSP_CHKSM_15_TO_8_8814B(x, v)                               \
+	(BIT_CLEAR_EXPRSP_CHKSM_15_TO_8_8814B(x) |                             \
+	 BIT_EXPRSP_CHKSM_15_TO_8_8814B(v))
+
+/* 2 REG_BEAMFORMING_INFO_NSARP_V1_8814B */
+
+#define BIT_SHIFT_WMAC_ARPIP_8814B 0
+#define BIT_MASK_WMAC_ARPIP_8814B 0xffffffffL
+#define BIT_WMAC_ARPIP_8814B(x)                                                \
+	(((x) & BIT_MASK_WMAC_ARPIP_8814B) << BIT_SHIFT_WMAC_ARPIP_8814B)
+#define BITS_WMAC_ARPIP_8814B                                                  \
+	(BIT_MASK_WMAC_ARPIP_8814B << BIT_SHIFT_WMAC_ARPIP_8814B)
+#define BIT_CLEAR_WMAC_ARPIP_8814B(x) ((x) & (~BITS_WMAC_ARPIP_8814B))
+#define BIT_GET_WMAC_ARPIP_8814B(x)                                            \
+	(((x) >> BIT_SHIFT_WMAC_ARPIP_8814B) & BIT_MASK_WMAC_ARPIP_8814B)
+#define BIT_SET_WMAC_ARPIP_8814B(x, v)                                         \
+	(BIT_CLEAR_WMAC_ARPIP_8814B(x) | BIT_WMAC_ARPIP_8814B(v))
+
+/* 2 REG_BEAMFORMING_INFO_NSARP_8814B */
+
+#define BIT_SHIFT_BEAMFORMING_INFO_8814B 0
+#define BIT_MASK_BEAMFORMING_INFO_8814B 0xffffffffL
+#define BIT_BEAMFORMING_INFO_8814B(x)                                          \
+	(((x) & BIT_MASK_BEAMFORMING_INFO_8814B)                               \
+	 << BIT_SHIFT_BEAMFORMING_INFO_8814B)
+#define BITS_BEAMFORMING_INFO_8814B                                            \
+	(BIT_MASK_BEAMFORMING_INFO_8814B << BIT_SHIFT_BEAMFORMING_INFO_8814B)
+#define BIT_CLEAR_BEAMFORMING_INFO_8814B(x)                                    \
+	((x) & (~BITS_BEAMFORMING_INFO_8814B))
+#define BIT_GET_BEAMFORMING_INFO_8814B(x)                                      \
+	(((x) >> BIT_SHIFT_BEAMFORMING_INFO_8814B) &                           \
+	 BIT_MASK_BEAMFORMING_INFO_8814B)
+#define BIT_SET_BEAMFORMING_INFO_8814B(x, v)                                   \
+	(BIT_CLEAR_BEAMFORMING_INFO_8814B(x) | BIT_BEAMFORMING_INFO_8814B(v))
+
+/* 2 REG_IPV6_8814B */
+
+#define BIT_SHIFT_R_WMAC_IPV6_MYIPAD_0_8814B 0
+#define BIT_MASK_R_WMAC_IPV6_MYIPAD_0_8814B 0xffffffffL
+#define BIT_R_WMAC_IPV6_MYIPAD_0_8814B(x)                                      \
+	(((x) & BIT_MASK_R_WMAC_IPV6_MYIPAD_0_8814B)                           \
+	 << BIT_SHIFT_R_WMAC_IPV6_MYIPAD_0_8814B)
+#define BITS_R_WMAC_IPV6_MYIPAD_0_8814B                                        \
+	(BIT_MASK_R_WMAC_IPV6_MYIPAD_0_8814B                                   \
+	 << BIT_SHIFT_R_WMAC_IPV6_MYIPAD_0_8814B)
+#define BIT_CLEAR_R_WMAC_IPV6_MYIPAD_0_8814B(x)                                \
+	((x) & (~BITS_R_WMAC_IPV6_MYIPAD_0_8814B))
+#define BIT_GET_R_WMAC_IPV6_MYIPAD_0_8814B(x)                                  \
+	(((x) >> BIT_SHIFT_R_WMAC_IPV6_MYIPAD_0_8814B) &                       \
+	 BIT_MASK_R_WMAC_IPV6_MYIPAD_0_8814B)
+#define BIT_SET_R_WMAC_IPV6_MYIPAD_0_8814B(x, v)                               \
+	(BIT_CLEAR_R_WMAC_IPV6_MYIPAD_0_8814B(x) |                             \
+	 BIT_R_WMAC_IPV6_MYIPAD_0_8814B(v))
+
+/* 2 REG_IPV6_1_8814B */
+
+#define BIT_SHIFT_R_WMAC_IPV6_MYIPAD_1_8814B 0
+#define BIT_MASK_R_WMAC_IPV6_MYIPAD_1_8814B 0xffffffffL
+#define BIT_R_WMAC_IPV6_MYIPAD_1_8814B(x)                                      \
+	(((x) & BIT_MASK_R_WMAC_IPV6_MYIPAD_1_8814B)                           \
+	 << BIT_SHIFT_R_WMAC_IPV6_MYIPAD_1_8814B)
+#define BITS_R_WMAC_IPV6_MYIPAD_1_8814B                                        \
+	(BIT_MASK_R_WMAC_IPV6_MYIPAD_1_8814B                                   \
+	 << BIT_SHIFT_R_WMAC_IPV6_MYIPAD_1_8814B)
+#define BIT_CLEAR_R_WMAC_IPV6_MYIPAD_1_8814B(x)                                \
+	((x) & (~BITS_R_WMAC_IPV6_MYIPAD_1_8814B))
+#define BIT_GET_R_WMAC_IPV6_MYIPAD_1_8814B(x)                                  \
+	(((x) >> BIT_SHIFT_R_WMAC_IPV6_MYIPAD_1_8814B) &                       \
+	 BIT_MASK_R_WMAC_IPV6_MYIPAD_1_8814B)
+#define BIT_SET_R_WMAC_IPV6_MYIPAD_1_8814B(x, v)                               \
+	(BIT_CLEAR_R_WMAC_IPV6_MYIPAD_1_8814B(x) |                             \
+	 BIT_R_WMAC_IPV6_MYIPAD_1_8814B(v))
+
+/* 2 REG_IPV6_2_8814B */
+
+#define BIT_SHIFT_R_WMAC_IPV6_MYIPAD_2_8814B 0
+#define BIT_MASK_R_WMAC_IPV6_MYIPAD_2_8814B 0xffffffffL
+#define BIT_R_WMAC_IPV6_MYIPAD_2_8814B(x)                                      \
+	(((x) & BIT_MASK_R_WMAC_IPV6_MYIPAD_2_8814B)                           \
+	 << BIT_SHIFT_R_WMAC_IPV6_MYIPAD_2_8814B)
+#define BITS_R_WMAC_IPV6_MYIPAD_2_8814B                                        \
+	(BIT_MASK_R_WMAC_IPV6_MYIPAD_2_8814B                                   \
+	 << BIT_SHIFT_R_WMAC_IPV6_MYIPAD_2_8814B)
+#define BIT_CLEAR_R_WMAC_IPV6_MYIPAD_2_8814B(x)                                \
+	((x) & (~BITS_R_WMAC_IPV6_MYIPAD_2_8814B))
+#define BIT_GET_R_WMAC_IPV6_MYIPAD_2_8814B(x)                                  \
+	(((x) >> BIT_SHIFT_R_WMAC_IPV6_MYIPAD_2_8814B) &                       \
+	 BIT_MASK_R_WMAC_IPV6_MYIPAD_2_8814B)
+#define BIT_SET_R_WMAC_IPV6_MYIPAD_2_8814B(x, v)                               \
+	(BIT_CLEAR_R_WMAC_IPV6_MYIPAD_2_8814B(x) |                             \
+	 BIT_R_WMAC_IPV6_MYIPAD_2_8814B(v))
+
+/* 2 REG_IPV6_3_8814B */
+
+#define BIT_SHIFT_R_WMAC_IPV6_MYIPAD_3_8814B 0
+#define BIT_MASK_R_WMAC_IPV6_MYIPAD_3_8814B 0xffffffffL
+#define BIT_R_WMAC_IPV6_MYIPAD_3_8814B(x)                                      \
+	(((x) & BIT_MASK_R_WMAC_IPV6_MYIPAD_3_8814B)                           \
+	 << BIT_SHIFT_R_WMAC_IPV6_MYIPAD_3_8814B)
+#define BITS_R_WMAC_IPV6_MYIPAD_3_8814B                                        \
+	(BIT_MASK_R_WMAC_IPV6_MYIPAD_3_8814B                                   \
+	 << BIT_SHIFT_R_WMAC_IPV6_MYIPAD_3_8814B)
+#define BIT_CLEAR_R_WMAC_IPV6_MYIPAD_3_8814B(x)                                \
+	((x) & (~BITS_R_WMAC_IPV6_MYIPAD_3_8814B))
+#define BIT_GET_R_WMAC_IPV6_MYIPAD_3_8814B(x)                                  \
+	(((x) >> BIT_SHIFT_R_WMAC_IPV6_MYIPAD_3_8814B) &                       \
+	 BIT_MASK_R_WMAC_IPV6_MYIPAD_3_8814B)
+#define BIT_SET_R_WMAC_IPV6_MYIPAD_3_8814B(x, v)                               \
+	(BIT_CLEAR_R_WMAC_IPV6_MYIPAD_3_8814B(x) |                             \
+	 BIT_R_WMAC_IPV6_MYIPAD_3_8814B(v))
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_WMAC_RTX_CTX_SUBTYPE_CFG_8814B */
+
+#define BIT_SHIFT_R_WMAC_CTX_SUBTYPE_8814B 4
+#define BIT_MASK_R_WMAC_CTX_SUBTYPE_8814B 0xf
+#define BIT_R_WMAC_CTX_SUBTYPE_8814B(x)                                        \
+	(((x) & BIT_MASK_R_WMAC_CTX_SUBTYPE_8814B)                             \
+	 << BIT_SHIFT_R_WMAC_CTX_SUBTYPE_8814B)
+#define BITS_R_WMAC_CTX_SUBTYPE_8814B                                          \
+	(BIT_MASK_R_WMAC_CTX_SUBTYPE_8814B                                     \
+	 << BIT_SHIFT_R_WMAC_CTX_SUBTYPE_8814B)
+#define BIT_CLEAR_R_WMAC_CTX_SUBTYPE_8814B(x)                                  \
+	((x) & (~BITS_R_WMAC_CTX_SUBTYPE_8814B))
+#define BIT_GET_R_WMAC_CTX_SUBTYPE_8814B(x)                                    \
+	(((x) >> BIT_SHIFT_R_WMAC_CTX_SUBTYPE_8814B) &                         \
+	 BIT_MASK_R_WMAC_CTX_SUBTYPE_8814B)
+#define BIT_SET_R_WMAC_CTX_SUBTYPE_8814B(x, v)                                 \
+	(BIT_CLEAR_R_WMAC_CTX_SUBTYPE_8814B(x) |                               \
+	 BIT_R_WMAC_CTX_SUBTYPE_8814B(v))
+
+#define BIT_SHIFT_R_WMAC_RTX_SUBTYPE_8814B 0
+#define BIT_MASK_R_WMAC_RTX_SUBTYPE_8814B 0xf
+#define BIT_R_WMAC_RTX_SUBTYPE_8814B(x)                                        \
+	(((x) & BIT_MASK_R_WMAC_RTX_SUBTYPE_8814B)                             \
+	 << BIT_SHIFT_R_WMAC_RTX_SUBTYPE_8814B)
+#define BITS_R_WMAC_RTX_SUBTYPE_8814B                                          \
+	(BIT_MASK_R_WMAC_RTX_SUBTYPE_8814B                                     \
+	 << BIT_SHIFT_R_WMAC_RTX_SUBTYPE_8814B)
+#define BIT_CLEAR_R_WMAC_RTX_SUBTYPE_8814B(x)                                  \
+	((x) & (~BITS_R_WMAC_RTX_SUBTYPE_8814B))
+#define BIT_GET_R_WMAC_RTX_SUBTYPE_8814B(x)                                    \
+	(((x) >> BIT_SHIFT_R_WMAC_RTX_SUBTYPE_8814B) &                         \
+	 BIT_MASK_R_WMAC_RTX_SUBTYPE_8814B)
+#define BIT_SET_R_WMAC_RTX_SUBTYPE_8814B(x, v)                                 \
+	(BIT_CLEAR_R_WMAC_RTX_SUBTYPE_8814B(x) |                               \
+	 BIT_R_WMAC_RTX_SUBTYPE_8814B(v))
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_WMAC_SWAES_CFG_8814B */
+
+/* 2 REG_BT_COEX_V2_8814B */
+#define BIT_GNT_BT_POLARITY_8814B BIT(12)
+#define BIT_GNT_BT_BYPASS_PRIORITY_8814B BIT(8)
+
+#define BIT_SHIFT_TIMER_8814B 0
+#define BIT_MASK_TIMER_8814B 0xff
+#define BIT_TIMER_8814B(x)                                                     \
+	(((x) & BIT_MASK_TIMER_8814B) << BIT_SHIFT_TIMER_8814B)
+#define BITS_TIMER_8814B (BIT_MASK_TIMER_8814B << BIT_SHIFT_TIMER_8814B)
+#define BIT_CLEAR_TIMER_8814B(x) ((x) & (~BITS_TIMER_8814B))
+#define BIT_GET_TIMER_8814B(x)                                                 \
+	(((x) >> BIT_SHIFT_TIMER_8814B) & BIT_MASK_TIMER_8814B)
+#define BIT_SET_TIMER_8814B(x, v)                                              \
+	(BIT_CLEAR_TIMER_8814B(x) | BIT_TIMER_8814B(v))
+
+/* 2 REG_BT_COEX_8814B */
+#define BIT_R_GNT_BT_RFC_SW_8814B BIT(12)
+#define BIT_R_GNT_BT_RFC_SW_EN_8814B BIT(11)
+#define BIT_R_GNT_BT_BB_SW_8814B BIT(10)
+#define BIT_R_GNT_BT_BB_SW_EN_8814B BIT(9)
+#define BIT_R_BT_CNT_THREN_8814B BIT(8)
+
+#define BIT_SHIFT_R_BT_CNT_THR_8814B 0
+#define BIT_MASK_R_BT_CNT_THR_8814B 0xff
+#define BIT_R_BT_CNT_THR_8814B(x)                                              \
+	(((x) & BIT_MASK_R_BT_CNT_THR_8814B) << BIT_SHIFT_R_BT_CNT_THR_8814B)
+#define BITS_R_BT_CNT_THR_8814B                                                \
+	(BIT_MASK_R_BT_CNT_THR_8814B << BIT_SHIFT_R_BT_CNT_THR_8814B)
+#define BIT_CLEAR_R_BT_CNT_THR_8814B(x) ((x) & (~BITS_R_BT_CNT_THR_8814B))
+#define BIT_GET_R_BT_CNT_THR_8814B(x)                                          \
+	(((x) >> BIT_SHIFT_R_BT_CNT_THR_8814B) & BIT_MASK_R_BT_CNT_THR_8814B)
+#define BIT_SET_R_BT_CNT_THR_8814B(x, v)                                       \
+	(BIT_CLEAR_R_BT_CNT_THR_8814B(x) | BIT_R_BT_CNT_THR_8814B(v))
+
+/* 2 REG_WLAN_ACT_MASK_CTRL_8814B */
+
+#define BIT_SHIFT_RXMYRTS_NAV_V1_8814B 8
+#define BIT_MASK_RXMYRTS_NAV_V1_8814B 0xff
+#define BIT_RXMYRTS_NAV_V1_8814B(x)                                            \
+	(((x) & BIT_MASK_RXMYRTS_NAV_V1_8814B)                                 \
+	 << BIT_SHIFT_RXMYRTS_NAV_V1_8814B)
+#define BITS_RXMYRTS_NAV_V1_8814B                                              \
+	(BIT_MASK_RXMYRTS_NAV_V1_8814B << BIT_SHIFT_RXMYRTS_NAV_V1_8814B)
+#define BIT_CLEAR_RXMYRTS_NAV_V1_8814B(x) ((x) & (~BITS_RXMYRTS_NAV_V1_8814B))
+#define BIT_GET_RXMYRTS_NAV_V1_8814B(x)                                        \
+	(((x) >> BIT_SHIFT_RXMYRTS_NAV_V1_8814B) &                             \
+	 BIT_MASK_RXMYRTS_NAV_V1_8814B)
+#define BIT_SET_RXMYRTS_NAV_V1_8814B(x, v)                                     \
+	(BIT_CLEAR_RXMYRTS_NAV_V1_8814B(x) | BIT_RXMYRTS_NAV_V1_8814B(v))
+
+#define BIT_SHIFT_RTSRST_V1_8814B 0
+#define BIT_MASK_RTSRST_V1_8814B 0xff
+#define BIT_RTSRST_V1_8814B(x)                                                 \
+	(((x) & BIT_MASK_RTSRST_V1_8814B) << BIT_SHIFT_RTSRST_V1_8814B)
+#define BITS_RTSRST_V1_8814B                                                   \
+	(BIT_MASK_RTSRST_V1_8814B << BIT_SHIFT_RTSRST_V1_8814B)
+#define BIT_CLEAR_RTSRST_V1_8814B(x) ((x) & (~BITS_RTSRST_V1_8814B))
+#define BIT_GET_RTSRST_V1_8814B(x)                                             \
+	(((x) >> BIT_SHIFT_RTSRST_V1_8814B) & BIT_MASK_RTSRST_V1_8814B)
+#define BIT_SET_RTSRST_V1_8814B(x, v)                                          \
+	(BIT_CLEAR_RTSRST_V1_8814B(x) | BIT_RTSRST_V1_8814B(v))
+
+/* 2 REG_WLAN_ACT_MASK_CTRL_1_8814B */
+#define BIT_WLRX_TER_BY_CTL_1_8814B BIT(11)
+#define BIT_WLRX_TER_BY_AD_1_8814B BIT(10)
+#define BIT_ANT_DIVERSITY_SEL_1_8814B BIT(9)
+#define BIT_ANTSEL_FOR_BT_CTRL_EN_1_8814B BIT(8)
+#define BIT_WLACT_LOW_GNTWL_EN_1_8814B BIT(2)
+#define BIT_WLACT_HIGH_GNTBT_EN_1_8814B BIT(1)
+#define BIT_NAV_UPPER_1_V1_8814B BIT(0)
+
+/* 2 REG_BT_COEX_ENHANCED_INTR_CTRL_8814B */
+
+#define BIT_SHIFT_BT_STAT_DELAY_8814B 12
+#define BIT_MASK_BT_STAT_DELAY_8814B 0xf
+#define BIT_BT_STAT_DELAY_8814B(x)                                             \
+	(((x) & BIT_MASK_BT_STAT_DELAY_8814B) << BIT_SHIFT_BT_STAT_DELAY_8814B)
+#define BITS_BT_STAT_DELAY_8814B                                               \
+	(BIT_MASK_BT_STAT_DELAY_8814B << BIT_SHIFT_BT_STAT_DELAY_8814B)
+#define BIT_CLEAR_BT_STAT_DELAY_8814B(x) ((x) & (~BITS_BT_STAT_DELAY_8814B))
+#define BIT_GET_BT_STAT_DELAY_8814B(x)                                         \
+	(((x) >> BIT_SHIFT_BT_STAT_DELAY_8814B) & BIT_MASK_BT_STAT_DELAY_8814B)
+#define BIT_SET_BT_STAT_DELAY_8814B(x, v)                                      \
+	(BIT_CLEAR_BT_STAT_DELAY_8814B(x) | BIT_BT_STAT_DELAY_8814B(v))
+
+#define BIT_SHIFT_BT_TRX_INIT_DETECT_8814B 8
+#define BIT_MASK_BT_TRX_INIT_DETECT_8814B 0xf
+#define BIT_BT_TRX_INIT_DETECT_8814B(x)                                        \
+	(((x) & BIT_MASK_BT_TRX_INIT_DETECT_8814B)                             \
+	 << BIT_SHIFT_BT_TRX_INIT_DETECT_8814B)
+#define BITS_BT_TRX_INIT_DETECT_8814B                                          \
+	(BIT_MASK_BT_TRX_INIT_DETECT_8814B                                     \
+	 << BIT_SHIFT_BT_TRX_INIT_DETECT_8814B)
+#define BIT_CLEAR_BT_TRX_INIT_DETECT_8814B(x)                                  \
+	((x) & (~BITS_BT_TRX_INIT_DETECT_8814B))
+#define BIT_GET_BT_TRX_INIT_DETECT_8814B(x)                                    \
+	(((x) >> BIT_SHIFT_BT_TRX_INIT_DETECT_8814B) &                         \
+	 BIT_MASK_BT_TRX_INIT_DETECT_8814B)
+#define BIT_SET_BT_TRX_INIT_DETECT_8814B(x, v)                                 \
+	(BIT_CLEAR_BT_TRX_INIT_DETECT_8814B(x) |                               \
+	 BIT_BT_TRX_INIT_DETECT_8814B(v))
+
+#define BIT_SHIFT_BT_PRI_DETECT_TO_8814B 4
+#define BIT_MASK_BT_PRI_DETECT_TO_8814B 0xf
+#define BIT_BT_PRI_DETECT_TO_8814B(x)                                          \
+	(((x) & BIT_MASK_BT_PRI_DETECT_TO_8814B)                               \
+	 << BIT_SHIFT_BT_PRI_DETECT_TO_8814B)
+#define BITS_BT_PRI_DETECT_TO_8814B                                            \
+	(BIT_MASK_BT_PRI_DETECT_TO_8814B << BIT_SHIFT_BT_PRI_DETECT_TO_8814B)
+#define BIT_CLEAR_BT_PRI_DETECT_TO_8814B(x)                                    \
+	((x) & (~BITS_BT_PRI_DETECT_TO_8814B))
+#define BIT_GET_BT_PRI_DETECT_TO_8814B(x)                                      \
+	(((x) >> BIT_SHIFT_BT_PRI_DETECT_TO_8814B) &                           \
+	 BIT_MASK_BT_PRI_DETECT_TO_8814B)
+#define BIT_SET_BT_PRI_DETECT_TO_8814B(x, v)                                   \
+	(BIT_CLEAR_BT_PRI_DETECT_TO_8814B(x) | BIT_BT_PRI_DETECT_TO_8814B(v))
+
+#define BIT_R_GRANTALL_WLMASK_8814B BIT(3)
+#define BIT_STATIS_BT_EN_8814B BIT(2)
+#define BIT_WL_ACT_MASK_ENABLE_8814B BIT(1)
+#define BIT_ENHANCED_BT_8814B BIT(0)
+
+/* 2 REG_BT_ACT_STATISTICS_8814B */
+
+#define BIT_SHIFT_STATIS_BT_HI_RX_8814B 16
+#define BIT_MASK_STATIS_BT_HI_RX_8814B 0xffff
+#define BIT_STATIS_BT_HI_RX_8814B(x)                                           \
+	(((x) & BIT_MASK_STATIS_BT_HI_RX_8814B)                                \
+	 << BIT_SHIFT_STATIS_BT_HI_RX_8814B)
+#define BITS_STATIS_BT_HI_RX_8814B                                             \
+	(BIT_MASK_STATIS_BT_HI_RX_8814B << BIT_SHIFT_STATIS_BT_HI_RX_8814B)
+#define BIT_CLEAR_STATIS_BT_HI_RX_8814B(x) ((x) & (~BITS_STATIS_BT_HI_RX_8814B))
+#define BIT_GET_STATIS_BT_HI_RX_8814B(x)                                       \
+	(((x) >> BIT_SHIFT_STATIS_BT_HI_RX_8814B) &                            \
+	 BIT_MASK_STATIS_BT_HI_RX_8814B)
+#define BIT_SET_STATIS_BT_HI_RX_8814B(x, v)                                    \
+	(BIT_CLEAR_STATIS_BT_HI_RX_8814B(x) | BIT_STATIS_BT_HI_RX_8814B(v))
+
+#define BIT_SHIFT_STATIS_BT_HI_TX_8814B 0
+#define BIT_MASK_STATIS_BT_HI_TX_8814B 0xffff
+#define BIT_STATIS_BT_HI_TX_8814B(x)                                           \
+	(((x) & BIT_MASK_STATIS_BT_HI_TX_8814B)                                \
+	 << BIT_SHIFT_STATIS_BT_HI_TX_8814B)
+#define BITS_STATIS_BT_HI_TX_8814B                                             \
+	(BIT_MASK_STATIS_BT_HI_TX_8814B << BIT_SHIFT_STATIS_BT_HI_TX_8814B)
+#define BIT_CLEAR_STATIS_BT_HI_TX_8814B(x) ((x) & (~BITS_STATIS_BT_HI_TX_8814B))
+#define BIT_GET_STATIS_BT_HI_TX_8814B(x)                                       \
+	(((x) >> BIT_SHIFT_STATIS_BT_HI_TX_8814B) &                            \
+	 BIT_MASK_STATIS_BT_HI_TX_8814B)
+#define BIT_SET_STATIS_BT_HI_TX_8814B(x, v)                                    \
+	(BIT_CLEAR_STATIS_BT_HI_TX_8814B(x) | BIT_STATIS_BT_HI_TX_8814B(v))
+
+/* 2 REG_BT_ACT_STATISTICS_1_8814B */
+
+#define BIT_SHIFT_STATIS_BT_LO_RX_1_8814B 16
+#define BIT_MASK_STATIS_BT_LO_RX_1_8814B 0xffff
+#define BIT_STATIS_BT_LO_RX_1_8814B(x)                                         \
+	(((x) & BIT_MASK_STATIS_BT_LO_RX_1_8814B)                              \
+	 << BIT_SHIFT_STATIS_BT_LO_RX_1_8814B)
+#define BITS_STATIS_BT_LO_RX_1_8814B                                           \
+	(BIT_MASK_STATIS_BT_LO_RX_1_8814B << BIT_SHIFT_STATIS_BT_LO_RX_1_8814B)
+#define BIT_CLEAR_STATIS_BT_LO_RX_1_8814B(x)                                   \
+	((x) & (~BITS_STATIS_BT_LO_RX_1_8814B))
+#define BIT_GET_STATIS_BT_LO_RX_1_8814B(x)                                     \
+	(((x) >> BIT_SHIFT_STATIS_BT_LO_RX_1_8814B) &                          \
+	 BIT_MASK_STATIS_BT_LO_RX_1_8814B)
+#define BIT_SET_STATIS_BT_LO_RX_1_8814B(x, v)                                  \
+	(BIT_CLEAR_STATIS_BT_LO_RX_1_8814B(x) | BIT_STATIS_BT_LO_RX_1_8814B(v))
+
+#define BIT_SHIFT_STATIS_BT_LO_TX_1_8814B 0
+#define BIT_MASK_STATIS_BT_LO_TX_1_8814B 0xffff
+#define BIT_STATIS_BT_LO_TX_1_8814B(x)                                         \
+	(((x) & BIT_MASK_STATIS_BT_LO_TX_1_8814B)                              \
+	 << BIT_SHIFT_STATIS_BT_LO_TX_1_8814B)
+#define BITS_STATIS_BT_LO_TX_1_8814B                                           \
+	(BIT_MASK_STATIS_BT_LO_TX_1_8814B << BIT_SHIFT_STATIS_BT_LO_TX_1_8814B)
+#define BIT_CLEAR_STATIS_BT_LO_TX_1_8814B(x)                                   \
+	((x) & (~BITS_STATIS_BT_LO_TX_1_8814B))
+#define BIT_GET_STATIS_BT_LO_TX_1_8814B(x)                                     \
+	(((x) >> BIT_SHIFT_STATIS_BT_LO_TX_1_8814B) &                          \
+	 BIT_MASK_STATIS_BT_LO_TX_1_8814B)
+#define BIT_SET_STATIS_BT_LO_TX_1_8814B(x, v)                                  \
+	(BIT_CLEAR_STATIS_BT_LO_TX_1_8814B(x) | BIT_STATIS_BT_LO_TX_1_8814B(v))
+
+/* 2 REG_BT_STATISTICS_CONTROL_REGISTER_8814B */
+
+#define BIT_SHIFT_R_BT_CMD_RPT_8814B 16
+#define BIT_MASK_R_BT_CMD_RPT_8814B 0xffff
+#define BIT_R_BT_CMD_RPT_8814B(x)                                              \
+	(((x) & BIT_MASK_R_BT_CMD_RPT_8814B) << BIT_SHIFT_R_BT_CMD_RPT_8814B)
+#define BITS_R_BT_CMD_RPT_8814B                                                \
+	(BIT_MASK_R_BT_CMD_RPT_8814B << BIT_SHIFT_R_BT_CMD_RPT_8814B)
+#define BIT_CLEAR_R_BT_CMD_RPT_8814B(x) ((x) & (~BITS_R_BT_CMD_RPT_8814B))
+#define BIT_GET_R_BT_CMD_RPT_8814B(x)                                          \
+	(((x) >> BIT_SHIFT_R_BT_CMD_RPT_8814B) & BIT_MASK_R_BT_CMD_RPT_8814B)
+#define BIT_SET_R_BT_CMD_RPT_8814B(x, v)                                       \
+	(BIT_CLEAR_R_BT_CMD_RPT_8814B(x) | BIT_R_BT_CMD_RPT_8814B(v))
+
+#define BIT_SHIFT_R_RPT_FROM_BT_8814B 8
+#define BIT_MASK_R_RPT_FROM_BT_8814B 0xff
+#define BIT_R_RPT_FROM_BT_8814B(x)                                             \
+	(((x) & BIT_MASK_R_RPT_FROM_BT_8814B) << BIT_SHIFT_R_RPT_FROM_BT_8814B)
+#define BITS_R_RPT_FROM_BT_8814B                                               \
+	(BIT_MASK_R_RPT_FROM_BT_8814B << BIT_SHIFT_R_RPT_FROM_BT_8814B)
+#define BIT_CLEAR_R_RPT_FROM_BT_8814B(x) ((x) & (~BITS_R_RPT_FROM_BT_8814B))
+#define BIT_GET_R_RPT_FROM_BT_8814B(x)                                         \
+	(((x) >> BIT_SHIFT_R_RPT_FROM_BT_8814B) & BIT_MASK_R_RPT_FROM_BT_8814B)
+#define BIT_SET_R_RPT_FROM_BT_8814B(x, v)                                      \
+	(BIT_CLEAR_R_RPT_FROM_BT_8814B(x) | BIT_R_RPT_FROM_BT_8814B(v))
+
+#define BIT_SHIFT_BT_HID_ISR_SET_8814B 6
+#define BIT_MASK_BT_HID_ISR_SET_8814B 0x3
+#define BIT_BT_HID_ISR_SET_8814B(x)                                            \
+	(((x) & BIT_MASK_BT_HID_ISR_SET_8814B)                                 \
+	 << BIT_SHIFT_BT_HID_ISR_SET_8814B)
+#define BITS_BT_HID_ISR_SET_8814B                                              \
+	(BIT_MASK_BT_HID_ISR_SET_8814B << BIT_SHIFT_BT_HID_ISR_SET_8814B)
+#define BIT_CLEAR_BT_HID_ISR_SET_8814B(x) ((x) & (~BITS_BT_HID_ISR_SET_8814B))
+#define BIT_GET_BT_HID_ISR_SET_8814B(x)                                        \
+	(((x) >> BIT_SHIFT_BT_HID_ISR_SET_8814B) &                             \
+	 BIT_MASK_BT_HID_ISR_SET_8814B)
+#define BIT_SET_BT_HID_ISR_SET_8814B(x, v)                                     \
+	(BIT_CLEAR_BT_HID_ISR_SET_8814B(x) | BIT_BT_HID_ISR_SET_8814B(v))
+
+#define BIT_TDMA_BT_START_NOTIFY_8814B BIT(5)
+#define BIT_ENABLE_TDMA_FW_MODE_8814B BIT(4)
+#define BIT_ENABLE_PTA_TDMA_MODE_8814B BIT(3)
+#define BIT_ENABLE_COEXIST_TAB_IN_TDMA_8814B BIT(2)
+#define BIT_GPIO2_GPIO3_EXANGE_OR_NO_BT_CCA_8814B BIT(1)
+#define BIT_RTK_BT_ENABLE_8814B BIT(0)
+
+/* 2 REG_BT_STATUS_REPORT_REGISTER_8814B */
+
+#define BIT_SHIFT_BT_PROFILE_8814B 24
+#define BIT_MASK_BT_PROFILE_8814B 0xff
+#define BIT_BT_PROFILE_8814B(x)                                                \
+	(((x) & BIT_MASK_BT_PROFILE_8814B) << BIT_SHIFT_BT_PROFILE_8814B)
+#define BITS_BT_PROFILE_8814B                                                  \
+	(BIT_MASK_BT_PROFILE_8814B << BIT_SHIFT_BT_PROFILE_8814B)
+#define BIT_CLEAR_BT_PROFILE_8814B(x) ((x) & (~BITS_BT_PROFILE_8814B))
+#define BIT_GET_BT_PROFILE_8814B(x)                                            \
+	(((x) >> BIT_SHIFT_BT_PROFILE_8814B) & BIT_MASK_BT_PROFILE_8814B)
+#define BIT_SET_BT_PROFILE_8814B(x, v)                                         \
+	(BIT_CLEAR_BT_PROFILE_8814B(x) | BIT_BT_PROFILE_8814B(v))
+
+#define BIT_SHIFT_BT_POWER_8814B 16
+#define BIT_MASK_BT_POWER_8814B 0xff
+#define BIT_BT_POWER_8814B(x)                                                  \
+	(((x) & BIT_MASK_BT_POWER_8814B) << BIT_SHIFT_BT_POWER_8814B)
+#define BITS_BT_POWER_8814B                                                    \
+	(BIT_MASK_BT_POWER_8814B << BIT_SHIFT_BT_POWER_8814B)
+#define BIT_CLEAR_BT_POWER_8814B(x) ((x) & (~BITS_BT_POWER_8814B))
+#define BIT_GET_BT_POWER_8814B(x)                                              \
+	(((x) >> BIT_SHIFT_BT_POWER_8814B) & BIT_MASK_BT_POWER_8814B)
+#define BIT_SET_BT_POWER_8814B(x, v)                                           \
+	(BIT_CLEAR_BT_POWER_8814B(x) | BIT_BT_POWER_8814B(v))
+
+#define BIT_SHIFT_BT_PREDECT_STATUS_8814B 8
+#define BIT_MASK_BT_PREDECT_STATUS_8814B 0xff
+#define BIT_BT_PREDECT_STATUS_8814B(x)                                         \
+	(((x) & BIT_MASK_BT_PREDECT_STATUS_8814B)                              \
+	 << BIT_SHIFT_BT_PREDECT_STATUS_8814B)
+#define BITS_BT_PREDECT_STATUS_8814B                                           \
+	(BIT_MASK_BT_PREDECT_STATUS_8814B << BIT_SHIFT_BT_PREDECT_STATUS_8814B)
+#define BIT_CLEAR_BT_PREDECT_STATUS_8814B(x)                                   \
+	((x) & (~BITS_BT_PREDECT_STATUS_8814B))
+#define BIT_GET_BT_PREDECT_STATUS_8814B(x)                                     \
+	(((x) >> BIT_SHIFT_BT_PREDECT_STATUS_8814B) &                          \
+	 BIT_MASK_BT_PREDECT_STATUS_8814B)
+#define BIT_SET_BT_PREDECT_STATUS_8814B(x, v)                                  \
+	(BIT_CLEAR_BT_PREDECT_STATUS_8814B(x) | BIT_BT_PREDECT_STATUS_8814B(v))
+
+#define BIT_SHIFT_BT_CMD_INFO_8814B 0
+#define BIT_MASK_BT_CMD_INFO_8814B 0xff
+#define BIT_BT_CMD_INFO_8814B(x)                                               \
+	(((x) & BIT_MASK_BT_CMD_INFO_8814B) << BIT_SHIFT_BT_CMD_INFO_8814B)
+#define BITS_BT_CMD_INFO_8814B                                                 \
+	(BIT_MASK_BT_CMD_INFO_8814B << BIT_SHIFT_BT_CMD_INFO_8814B)
+#define BIT_CLEAR_BT_CMD_INFO_8814B(x) ((x) & (~BITS_BT_CMD_INFO_8814B))
+#define BIT_GET_BT_CMD_INFO_8814B(x)                                           \
+	(((x) >> BIT_SHIFT_BT_CMD_INFO_8814B) & BIT_MASK_BT_CMD_INFO_8814B)
+#define BIT_SET_BT_CMD_INFO_8814B(x, v)                                        \
+	(BIT_CLEAR_BT_CMD_INFO_8814B(x) | BIT_BT_CMD_INFO_8814B(v))
+
+/* 2 REG_BT_INTERRUPT_CONTROL_REGISTER_8814B */
+#define BIT_EN_MAC_NULL_PKT_NOTIFY_8814B BIT(31)
+#define BIT_EN_WLAN_RPT_AND_BT_QUERY_8814B BIT(30)
+#define BIT_EN_BT_STSTUS_RPT_8814B BIT(29)
+#define BIT_EN_BT_POWER_8814B BIT(28)
+#define BIT_EN_BT_CHANNEL_8814B BIT(27)
+#define BIT_EN_BT_SLOT_CHANGE_8814B BIT(26)
+#define BIT_EN_BT_PROFILE_OR_HID_8814B BIT(25)
+#define BIT_WLAN_RPT_NOTIFY_8814B BIT(24)
+
+#define BIT_SHIFT_WLAN_RPT_DATA_8814B 16
+#define BIT_MASK_WLAN_RPT_DATA_8814B 0xff
+#define BIT_WLAN_RPT_DATA_8814B(x)                                             \
+	(((x) & BIT_MASK_WLAN_RPT_DATA_8814B) << BIT_SHIFT_WLAN_RPT_DATA_8814B)
+#define BITS_WLAN_RPT_DATA_8814B                                               \
+	(BIT_MASK_WLAN_RPT_DATA_8814B << BIT_SHIFT_WLAN_RPT_DATA_8814B)
+#define BIT_CLEAR_WLAN_RPT_DATA_8814B(x) ((x) & (~BITS_WLAN_RPT_DATA_8814B))
+#define BIT_GET_WLAN_RPT_DATA_8814B(x)                                         \
+	(((x) >> BIT_SHIFT_WLAN_RPT_DATA_8814B) & BIT_MASK_WLAN_RPT_DATA_8814B)
+#define BIT_SET_WLAN_RPT_DATA_8814B(x, v)                                      \
+	(BIT_CLEAR_WLAN_RPT_DATA_8814B(x) | BIT_WLAN_RPT_DATA_8814B(v))
+
+#define BIT_SHIFT_CMD_ID_8814B 8
+#define BIT_MASK_CMD_ID_8814B 0xff
+#define BIT_CMD_ID_8814B(x)                                                    \
+	(((x) & BIT_MASK_CMD_ID_8814B) << BIT_SHIFT_CMD_ID_8814B)
+#define BITS_CMD_ID_8814B (BIT_MASK_CMD_ID_8814B << BIT_SHIFT_CMD_ID_8814B)
+#define BIT_CLEAR_CMD_ID_8814B(x) ((x) & (~BITS_CMD_ID_8814B))
+#define BIT_GET_CMD_ID_8814B(x)                                                \
+	(((x) >> BIT_SHIFT_CMD_ID_8814B) & BIT_MASK_CMD_ID_8814B)
+#define BIT_SET_CMD_ID_8814B(x, v)                                             \
+	(BIT_CLEAR_CMD_ID_8814B(x) | BIT_CMD_ID_8814B(v))
+
+#define BIT_SHIFT_BT_DATA_8814B 0
+#define BIT_MASK_BT_DATA_8814B 0xff
+#define BIT_BT_DATA_8814B(x)                                                   \
+	(((x) & BIT_MASK_BT_DATA_8814B) << BIT_SHIFT_BT_DATA_8814B)
+#define BITS_BT_DATA_8814B (BIT_MASK_BT_DATA_8814B << BIT_SHIFT_BT_DATA_8814B)
+#define BIT_CLEAR_BT_DATA_8814B(x) ((x) & (~BITS_BT_DATA_8814B))
+#define BIT_GET_BT_DATA_8814B(x)                                               \
+	(((x) >> BIT_SHIFT_BT_DATA_8814B) & BIT_MASK_BT_DATA_8814B)
+#define BIT_SET_BT_DATA_8814B(x, v)                                            \
+	(BIT_CLEAR_BT_DATA_8814B(x) | BIT_BT_DATA_8814B(v))
+
+/* 2 REG_WLAN_REPORT_TIME_OUT_CONTROL_REGISTER_8814B */
+
+#define BIT_SHIFT_WLAN_RPT_TO_8814B 0
+#define BIT_MASK_WLAN_RPT_TO_8814B 0xff
+#define BIT_WLAN_RPT_TO_8814B(x)                                               \
+	(((x) & BIT_MASK_WLAN_RPT_TO_8814B) << BIT_SHIFT_WLAN_RPT_TO_8814B)
+#define BITS_WLAN_RPT_TO_8814B                                                 \
+	(BIT_MASK_WLAN_RPT_TO_8814B << BIT_SHIFT_WLAN_RPT_TO_8814B)
+#define BIT_CLEAR_WLAN_RPT_TO_8814B(x) ((x) & (~BITS_WLAN_RPT_TO_8814B))
+#define BIT_GET_WLAN_RPT_TO_8814B(x)                                           \
+	(((x) >> BIT_SHIFT_WLAN_RPT_TO_8814B) & BIT_MASK_WLAN_RPT_TO_8814B)
+#define BIT_SET_WLAN_RPT_TO_8814B(x, v)                                        \
+	(BIT_CLEAR_WLAN_RPT_TO_8814B(x) | BIT_WLAN_RPT_TO_8814B(v))
+
+/* 2 REG_BT_ISOLATION_TABLE_REGISTER_REGISTER_8814B */
+
+#define BIT_SHIFT_ISOLATION_CHK_0_8814B 1
+#define BIT_MASK_ISOLATION_CHK_0_8814B 0x7fffff
+#define BIT_ISOLATION_CHK_0_8814B(x)                                           \
+	(((x) & BIT_MASK_ISOLATION_CHK_0_8814B)                                \
+	 << BIT_SHIFT_ISOLATION_CHK_0_8814B)
+#define BITS_ISOLATION_CHK_0_8814B                                             \
+	(BIT_MASK_ISOLATION_CHK_0_8814B << BIT_SHIFT_ISOLATION_CHK_0_8814B)
+#define BIT_CLEAR_ISOLATION_CHK_0_8814B(x) ((x) & (~BITS_ISOLATION_CHK_0_8814B))
+#define BIT_GET_ISOLATION_CHK_0_8814B(x)                                       \
+	(((x) >> BIT_SHIFT_ISOLATION_CHK_0_8814B) &                            \
+	 BIT_MASK_ISOLATION_CHK_0_8814B)
+#define BIT_SET_ISOLATION_CHK_0_8814B(x, v)                                    \
+	(BIT_CLEAR_ISOLATION_CHK_0_8814B(x) | BIT_ISOLATION_CHK_0_8814B(v))
+
+#define BIT_ISOLATION_EN_8814B BIT(0)
+
+/* 2 REG_BT_ISOLATION_TABLE_REGISTER_REGISTER_1_8814B */
+
+#define BIT_SHIFT_ISOLATION_CHK_1_8814B 0
+#define BIT_MASK_ISOLATION_CHK_1_8814B 0xffffffffL
+#define BIT_ISOLATION_CHK_1_8814B(x)                                           \
+	(((x) & BIT_MASK_ISOLATION_CHK_1_8814B)                                \
+	 << BIT_SHIFT_ISOLATION_CHK_1_8814B)
+#define BITS_ISOLATION_CHK_1_8814B                                             \
+	(BIT_MASK_ISOLATION_CHK_1_8814B << BIT_SHIFT_ISOLATION_CHK_1_8814B)
+#define BIT_CLEAR_ISOLATION_CHK_1_8814B(x) ((x) & (~BITS_ISOLATION_CHK_1_8814B))
+#define BIT_GET_ISOLATION_CHK_1_8814B(x)                                       \
+	(((x) >> BIT_SHIFT_ISOLATION_CHK_1_8814B) &                            \
+	 BIT_MASK_ISOLATION_CHK_1_8814B)
+#define BIT_SET_ISOLATION_CHK_1_8814B(x, v)                                    \
+	(BIT_CLEAR_ISOLATION_CHK_1_8814B(x) | BIT_ISOLATION_CHK_1_8814B(v))
+
+/* 2 REG_BT_ISOLATION_TABLE_REGISTER_REGISTER_2_8814B */
+
+#define BIT_SHIFT_ISOLATION_CHK_2_8814B 0
+#define BIT_MASK_ISOLATION_CHK_2_8814B 0xffffff
+#define BIT_ISOLATION_CHK_2_8814B(x)                                           \
+	(((x) & BIT_MASK_ISOLATION_CHK_2_8814B)                                \
+	 << BIT_SHIFT_ISOLATION_CHK_2_8814B)
+#define BITS_ISOLATION_CHK_2_8814B                                             \
+	(BIT_MASK_ISOLATION_CHK_2_8814B << BIT_SHIFT_ISOLATION_CHK_2_8814B)
+#define BIT_CLEAR_ISOLATION_CHK_2_8814B(x) ((x) & (~BITS_ISOLATION_CHK_2_8814B))
+#define BIT_GET_ISOLATION_CHK_2_8814B(x)                                       \
+	(((x) >> BIT_SHIFT_ISOLATION_CHK_2_8814B) &                            \
+	 BIT_MASK_ISOLATION_CHK_2_8814B)
+#define BIT_SET_ISOLATION_CHK_2_8814B(x, v)                                    \
+	(BIT_CLEAR_ISOLATION_CHK_2_8814B(x) | BIT_ISOLATION_CHK_2_8814B(v))
+
+/* 2 REG_BT_INTERRUPT_STATUS_REGISTER_8814B */
+#define BIT_BT_HID_ISR_8814B BIT(7)
+#define BIT_BT_QUERY_ISR_8814B BIT(6)
+#define BIT_MAC_NULL_PKT_NOTIFY_ISR_8814B BIT(5)
+#define BIT_WLAN_RPT_ISR_8814B BIT(4)
+#define BIT_BT_POWER_ISR_8814B BIT(3)
+#define BIT_BT_CHANNEL_ISR_8814B BIT(2)
+#define BIT_BT_SLOT_CHANGE_ISR_8814B BIT(1)
+#define BIT_BT_PROFILE_ISR_8814B BIT(0)
+
+/* 2 REG_BT_TDMA_TIME_REGISTER_8814B */
+
+#define BIT_SHIFT_BT_TIME_8814B 6
+#define BIT_MASK_BT_TIME_8814B 0x3ffffff
+#define BIT_BT_TIME_8814B(x)                                                   \
+	(((x) & BIT_MASK_BT_TIME_8814B) << BIT_SHIFT_BT_TIME_8814B)
+#define BITS_BT_TIME_8814B (BIT_MASK_BT_TIME_8814B << BIT_SHIFT_BT_TIME_8814B)
+#define BIT_CLEAR_BT_TIME_8814B(x) ((x) & (~BITS_BT_TIME_8814B))
+#define BIT_GET_BT_TIME_8814B(x)                                               \
+	(((x) >> BIT_SHIFT_BT_TIME_8814B) & BIT_MASK_BT_TIME_8814B)
+#define BIT_SET_BT_TIME_8814B(x, v)                                            \
+	(BIT_CLEAR_BT_TIME_8814B(x) | BIT_BT_TIME_8814B(v))
+
+#define BIT_SHIFT_BT_RPT_SAMPLE_RATE_8814B 0
+#define BIT_MASK_BT_RPT_SAMPLE_RATE_8814B 0x3f
+#define BIT_BT_RPT_SAMPLE_RATE_8814B(x)                                        \
+	(((x) & BIT_MASK_BT_RPT_SAMPLE_RATE_8814B)                             \
+	 << BIT_SHIFT_BT_RPT_SAMPLE_RATE_8814B)
+#define BITS_BT_RPT_SAMPLE_RATE_8814B                                          \
+	(BIT_MASK_BT_RPT_SAMPLE_RATE_8814B                                     \
+	 << BIT_SHIFT_BT_RPT_SAMPLE_RATE_8814B)
+#define BIT_CLEAR_BT_RPT_SAMPLE_RATE_8814B(x)                                  \
+	((x) & (~BITS_BT_RPT_SAMPLE_RATE_8814B))
+#define BIT_GET_BT_RPT_SAMPLE_RATE_8814B(x)                                    \
+	(((x) >> BIT_SHIFT_BT_RPT_SAMPLE_RATE_8814B) &                         \
+	 BIT_MASK_BT_RPT_SAMPLE_RATE_8814B)
+#define BIT_SET_BT_RPT_SAMPLE_RATE_8814B(x, v)                                 \
+	(BIT_CLEAR_BT_RPT_SAMPLE_RATE_8814B(x) |                               \
+	 BIT_BT_RPT_SAMPLE_RATE_8814B(v))
+
+/* 2 REG_BT_ACT_REGISTER_8814B */
+
+#define BIT_SHIFT_BT_EISR_EN_8814B 16
+#define BIT_MASK_BT_EISR_EN_8814B 0xff
+#define BIT_BT_EISR_EN_8814B(x)                                                \
+	(((x) & BIT_MASK_BT_EISR_EN_8814B) << BIT_SHIFT_BT_EISR_EN_8814B)
+#define BITS_BT_EISR_EN_8814B                                                  \
+	(BIT_MASK_BT_EISR_EN_8814B << BIT_SHIFT_BT_EISR_EN_8814B)
+#define BIT_CLEAR_BT_EISR_EN_8814B(x) ((x) & (~BITS_BT_EISR_EN_8814B))
+#define BIT_GET_BT_EISR_EN_8814B(x)                                            \
+	(((x) >> BIT_SHIFT_BT_EISR_EN_8814B) & BIT_MASK_BT_EISR_EN_8814B)
+#define BIT_SET_BT_EISR_EN_8814B(x, v)                                         \
+	(BIT_CLEAR_BT_EISR_EN_8814B(x) | BIT_BT_EISR_EN_8814B(v))
+
+#define BIT_BT_ACT_FALLING_ISR_8814B BIT(10)
+#define BIT_BT_ACT_RISING_ISR_8814B BIT(9)
+#define BIT_TDMA_TO_ISR_8814B BIT(8)
+
+#define BIT_SHIFT_BT_CH_8814B 0
+#define BIT_MASK_BT_CH_8814B 0xff
+#define BIT_BT_CH_8814B(x)                                                     \
+	(((x) & BIT_MASK_BT_CH_8814B) << BIT_SHIFT_BT_CH_8814B)
+#define BITS_BT_CH_8814B (BIT_MASK_BT_CH_8814B << BIT_SHIFT_BT_CH_8814B)
+#define BIT_CLEAR_BT_CH_8814B(x) ((x) & (~BITS_BT_CH_8814B))
+#define BIT_GET_BT_CH_8814B(x)                                                 \
+	(((x) >> BIT_SHIFT_BT_CH_8814B) & BIT_MASK_BT_CH_8814B)
+#define BIT_SET_BT_CH_8814B(x, v)                                              \
+	(BIT_CLEAR_BT_CH_8814B(x) | BIT_BT_CH_8814B(v))
+
+/* 2 REG_OBFF_CTRL_BASIC_8814B */
+#define BIT_OBFF_EN_V1_8814B BIT(31)
+
+#define BIT_SHIFT_OBFF_STATE_V1_8814B 28
+#define BIT_MASK_OBFF_STATE_V1_8814B 0x3
+#define BIT_OBFF_STATE_V1_8814B(x)                                             \
+	(((x) & BIT_MASK_OBFF_STATE_V1_8814B) << BIT_SHIFT_OBFF_STATE_V1_8814B)
+#define BITS_OBFF_STATE_V1_8814B                                               \
+	(BIT_MASK_OBFF_STATE_V1_8814B << BIT_SHIFT_OBFF_STATE_V1_8814B)
+#define BIT_CLEAR_OBFF_STATE_V1_8814B(x) ((x) & (~BITS_OBFF_STATE_V1_8814B))
+#define BIT_GET_OBFF_STATE_V1_8814B(x)                                         \
+	(((x) >> BIT_SHIFT_OBFF_STATE_V1_8814B) & BIT_MASK_OBFF_STATE_V1_8814B)
+#define BIT_SET_OBFF_STATE_V1_8814B(x, v)                                      \
+	(BIT_CLEAR_OBFF_STATE_V1_8814B(x) | BIT_OBFF_STATE_V1_8814B(v))
+
+#define BIT_OBFF_ACT_RXDMA_EN_8814B BIT(27)
+#define BIT_OBFF_BLOCK_INT_EN_8814B BIT(26)
+#define BIT_OBFF_AUTOACT_EN_8814B BIT(25)
+#define BIT_OBFF_AUTOIDLE_EN_8814B BIT(24)
+
+#define BIT_SHIFT_WAKE_MAX_PLS_8814B 20
+#define BIT_MASK_WAKE_MAX_PLS_8814B 0x7
+#define BIT_WAKE_MAX_PLS_8814B(x)                                              \
+	(((x) & BIT_MASK_WAKE_MAX_PLS_8814B) << BIT_SHIFT_WAKE_MAX_PLS_8814B)
+#define BITS_WAKE_MAX_PLS_8814B                                                \
+	(BIT_MASK_WAKE_MAX_PLS_8814B << BIT_SHIFT_WAKE_MAX_PLS_8814B)
+#define BIT_CLEAR_WAKE_MAX_PLS_8814B(x) ((x) & (~BITS_WAKE_MAX_PLS_8814B))
+#define BIT_GET_WAKE_MAX_PLS_8814B(x)                                          \
+	(((x) >> BIT_SHIFT_WAKE_MAX_PLS_8814B) & BIT_MASK_WAKE_MAX_PLS_8814B)
+#define BIT_SET_WAKE_MAX_PLS_8814B(x, v)                                       \
+	(BIT_CLEAR_WAKE_MAX_PLS_8814B(x) | BIT_WAKE_MAX_PLS_8814B(v))
+
+#define BIT_SHIFT_WAKE_MIN_PLS_8814B 16
+#define BIT_MASK_WAKE_MIN_PLS_8814B 0x7
+#define BIT_WAKE_MIN_PLS_8814B(x)                                              \
+	(((x) & BIT_MASK_WAKE_MIN_PLS_8814B) << BIT_SHIFT_WAKE_MIN_PLS_8814B)
+#define BITS_WAKE_MIN_PLS_8814B                                                \
+	(BIT_MASK_WAKE_MIN_PLS_8814B << BIT_SHIFT_WAKE_MIN_PLS_8814B)
+#define BIT_CLEAR_WAKE_MIN_PLS_8814B(x) ((x) & (~BITS_WAKE_MIN_PLS_8814B))
+#define BIT_GET_WAKE_MIN_PLS_8814B(x)                                          \
+	(((x) >> BIT_SHIFT_WAKE_MIN_PLS_8814B) & BIT_MASK_WAKE_MIN_PLS_8814B)
+#define BIT_SET_WAKE_MIN_PLS_8814B(x, v)                                       \
+	(BIT_CLEAR_WAKE_MIN_PLS_8814B(x) | BIT_WAKE_MIN_PLS_8814B(v))
+
+#define BIT_SHIFT_WAKE_MAX_F2F_8814B 12
+#define BIT_MASK_WAKE_MAX_F2F_8814B 0x7
+#define BIT_WAKE_MAX_F2F_8814B(x)                                              \
+	(((x) & BIT_MASK_WAKE_MAX_F2F_8814B) << BIT_SHIFT_WAKE_MAX_F2F_8814B)
+#define BITS_WAKE_MAX_F2F_8814B                                                \
+	(BIT_MASK_WAKE_MAX_F2F_8814B << BIT_SHIFT_WAKE_MAX_F2F_8814B)
+#define BIT_CLEAR_WAKE_MAX_F2F_8814B(x) ((x) & (~BITS_WAKE_MAX_F2F_8814B))
+#define BIT_GET_WAKE_MAX_F2F_8814B(x)                                          \
+	(((x) >> BIT_SHIFT_WAKE_MAX_F2F_8814B) & BIT_MASK_WAKE_MAX_F2F_8814B)
+#define BIT_SET_WAKE_MAX_F2F_8814B(x, v)                                       \
+	(BIT_CLEAR_WAKE_MAX_F2F_8814B(x) | BIT_WAKE_MAX_F2F_8814B(v))
+
+#define BIT_SHIFT_WAKE_MIN_F2F_8814B 8
+#define BIT_MASK_WAKE_MIN_F2F_8814B 0x7
+#define BIT_WAKE_MIN_F2F_8814B(x)                                              \
+	(((x) & BIT_MASK_WAKE_MIN_F2F_8814B) << BIT_SHIFT_WAKE_MIN_F2F_8814B)
+#define BITS_WAKE_MIN_F2F_8814B                                                \
+	(BIT_MASK_WAKE_MIN_F2F_8814B << BIT_SHIFT_WAKE_MIN_F2F_8814B)
+#define BIT_CLEAR_WAKE_MIN_F2F_8814B(x) ((x) & (~BITS_WAKE_MIN_F2F_8814B))
+#define BIT_GET_WAKE_MIN_F2F_8814B(x)                                          \
+	(((x) >> BIT_SHIFT_WAKE_MIN_F2F_8814B) & BIT_MASK_WAKE_MIN_F2F_8814B)
+#define BIT_SET_WAKE_MIN_F2F_8814B(x, v)                                       \
+	(BIT_CLEAR_WAKE_MIN_F2F_8814B(x) | BIT_WAKE_MIN_F2F_8814B(v))
+
+#define BIT_APP_CPU_ACT_V1_8814B BIT(3)
+#define BIT_APP_OBFF_V1_8814B BIT(2)
+#define BIT_APP_IDLE_V1_8814B BIT(1)
+#define BIT_APP_INIT_V1_8814B BIT(0)
+
+/* 2 REG_OBFF_CTRL2_TIMER_8814B */
+
+#define BIT_SHIFT_RX_HIGH_TIMER_IDX_8814B 24
+#define BIT_MASK_RX_HIGH_TIMER_IDX_8814B 0x7
+#define BIT_RX_HIGH_TIMER_IDX_8814B(x)                                         \
+	(((x) & BIT_MASK_RX_HIGH_TIMER_IDX_8814B)                              \
+	 << BIT_SHIFT_RX_HIGH_TIMER_IDX_8814B)
+#define BITS_RX_HIGH_TIMER_IDX_8814B                                           \
+	(BIT_MASK_RX_HIGH_TIMER_IDX_8814B << BIT_SHIFT_RX_HIGH_TIMER_IDX_8814B)
+#define BIT_CLEAR_RX_HIGH_TIMER_IDX_8814B(x)                                   \
+	((x) & (~BITS_RX_HIGH_TIMER_IDX_8814B))
+#define BIT_GET_RX_HIGH_TIMER_IDX_8814B(x)                                     \
+	(((x) >> BIT_SHIFT_RX_HIGH_TIMER_IDX_8814B) &                          \
+	 BIT_MASK_RX_HIGH_TIMER_IDX_8814B)
+#define BIT_SET_RX_HIGH_TIMER_IDX_8814B(x, v)                                  \
+	(BIT_CLEAR_RX_HIGH_TIMER_IDX_8814B(x) | BIT_RX_HIGH_TIMER_IDX_8814B(v))
+
+#define BIT_SHIFT_RX_MED_TIMER_IDX_8814B 16
+#define BIT_MASK_RX_MED_TIMER_IDX_8814B 0x7
+#define BIT_RX_MED_TIMER_IDX_8814B(x)                                          \
+	(((x) & BIT_MASK_RX_MED_TIMER_IDX_8814B)                               \
+	 << BIT_SHIFT_RX_MED_TIMER_IDX_8814B)
+#define BITS_RX_MED_TIMER_IDX_8814B                                            \
+	(BIT_MASK_RX_MED_TIMER_IDX_8814B << BIT_SHIFT_RX_MED_TIMER_IDX_8814B)
+#define BIT_CLEAR_RX_MED_TIMER_IDX_8814B(x)                                    \
+	((x) & (~BITS_RX_MED_TIMER_IDX_8814B))
+#define BIT_GET_RX_MED_TIMER_IDX_8814B(x)                                      \
+	(((x) >> BIT_SHIFT_RX_MED_TIMER_IDX_8814B) &                           \
+	 BIT_MASK_RX_MED_TIMER_IDX_8814B)
+#define BIT_SET_RX_MED_TIMER_IDX_8814B(x, v)                                   \
+	(BIT_CLEAR_RX_MED_TIMER_IDX_8814B(x) | BIT_RX_MED_TIMER_IDX_8814B(v))
+
+#define BIT_SHIFT_RX_LOW_TIMER_IDX_8814B 8
+#define BIT_MASK_RX_LOW_TIMER_IDX_8814B 0x7
+#define BIT_RX_LOW_TIMER_IDX_8814B(x)                                          \
+	(((x) & BIT_MASK_RX_LOW_TIMER_IDX_8814B)                               \
+	 << BIT_SHIFT_RX_LOW_TIMER_IDX_8814B)
+#define BITS_RX_LOW_TIMER_IDX_8814B                                            \
+	(BIT_MASK_RX_LOW_TIMER_IDX_8814B << BIT_SHIFT_RX_LOW_TIMER_IDX_8814B)
+#define BIT_CLEAR_RX_LOW_TIMER_IDX_8814B(x)                                    \
+	((x) & (~BITS_RX_LOW_TIMER_IDX_8814B))
+#define BIT_GET_RX_LOW_TIMER_IDX_8814B(x)                                      \
+	(((x) >> BIT_SHIFT_RX_LOW_TIMER_IDX_8814B) &                           \
+	 BIT_MASK_RX_LOW_TIMER_IDX_8814B)
+#define BIT_SET_RX_LOW_TIMER_IDX_8814B(x, v)                                   \
+	(BIT_CLEAR_RX_LOW_TIMER_IDX_8814B(x) | BIT_RX_LOW_TIMER_IDX_8814B(v))
+
+#define BIT_SHIFT_OBFF_INT_TIMER_IDX_8814B 0
+#define BIT_MASK_OBFF_INT_TIMER_IDX_8814B 0x7
+#define BIT_OBFF_INT_TIMER_IDX_8814B(x)                                        \
+	(((x) & BIT_MASK_OBFF_INT_TIMER_IDX_8814B)                             \
+	 << BIT_SHIFT_OBFF_INT_TIMER_IDX_8814B)
+#define BITS_OBFF_INT_TIMER_IDX_8814B                                          \
+	(BIT_MASK_OBFF_INT_TIMER_IDX_8814B                                     \
+	 << BIT_SHIFT_OBFF_INT_TIMER_IDX_8814B)
+#define BIT_CLEAR_OBFF_INT_TIMER_IDX_8814B(x)                                  \
+	((x) & (~BITS_OBFF_INT_TIMER_IDX_8814B))
+#define BIT_GET_OBFF_INT_TIMER_IDX_8814B(x)                                    \
+	(((x) >> BIT_SHIFT_OBFF_INT_TIMER_IDX_8814B) &                         \
+	 BIT_MASK_OBFF_INT_TIMER_IDX_8814B)
+#define BIT_SET_OBFF_INT_TIMER_IDX_8814B(x, v)                                 \
+	(BIT_CLEAR_OBFF_INT_TIMER_IDX_8814B(x) |                               \
+	 BIT_OBFF_INT_TIMER_IDX_8814B(v))
+
+/* 2 REG_LTR_CTRL_BASIC_8814B */
+#define BIT_LTR_EN_V1_8814B BIT(31)
+#define BIT_LTR_HW_EN_V1_8814B BIT(30)
+#define BIT_LRT_ACT_CTS_EN_8814B BIT(29)
+#define BIT_LTR_ACT_RXPKT_EN_8814B BIT(28)
+#define BIT_LTR_ACT_RXDMA_EN_8814B BIT(27)
+#define BIT_LTR_IDLE_NO_SNOOP_8814B BIT(26)
+#define BIT_SPDUP_MGTPKT_8814B BIT(25)
+#define BIT_RX_AGG_EN_8814B BIT(24)
+#define BIT_APP_LTR_ACT_8814B BIT(23)
+#define BIT_APP_LTR_IDLE_8814B BIT(22)
+
+#define BIT_SHIFT_HIGH_RATE_TRIG_SEL_8814B 20
+#define BIT_MASK_HIGH_RATE_TRIG_SEL_8814B 0x3
+#define BIT_HIGH_RATE_TRIG_SEL_8814B(x)                                        \
+	(((x) & BIT_MASK_HIGH_RATE_TRIG_SEL_8814B)                             \
+	 << BIT_SHIFT_HIGH_RATE_TRIG_SEL_8814B)
+#define BITS_HIGH_RATE_TRIG_SEL_8814B                                          \
+	(BIT_MASK_HIGH_RATE_TRIG_SEL_8814B                                     \
+	 << BIT_SHIFT_HIGH_RATE_TRIG_SEL_8814B)
+#define BIT_CLEAR_HIGH_RATE_TRIG_SEL_8814B(x)                                  \
+	((x) & (~BITS_HIGH_RATE_TRIG_SEL_8814B))
+#define BIT_GET_HIGH_RATE_TRIG_SEL_8814B(x)                                    \
+	(((x) >> BIT_SHIFT_HIGH_RATE_TRIG_SEL_8814B) &                         \
+	 BIT_MASK_HIGH_RATE_TRIG_SEL_8814B)
+#define BIT_SET_HIGH_RATE_TRIG_SEL_8814B(x, v)                                 \
+	(BIT_CLEAR_HIGH_RATE_TRIG_SEL_8814B(x) |                               \
+	 BIT_HIGH_RATE_TRIG_SEL_8814B(v))
+
+#define BIT_SHIFT_MED_RATE_TRIG_SEL_8814B 18
+#define BIT_MASK_MED_RATE_TRIG_SEL_8814B 0x3
+#define BIT_MED_RATE_TRIG_SEL_8814B(x)                                         \
+	(((x) & BIT_MASK_MED_RATE_TRIG_SEL_8814B)                              \
+	 << BIT_SHIFT_MED_RATE_TRIG_SEL_8814B)
+#define BITS_MED_RATE_TRIG_SEL_8814B                                           \
+	(BIT_MASK_MED_RATE_TRIG_SEL_8814B << BIT_SHIFT_MED_RATE_TRIG_SEL_8814B)
+#define BIT_CLEAR_MED_RATE_TRIG_SEL_8814B(x)                                   \
+	((x) & (~BITS_MED_RATE_TRIG_SEL_8814B))
+#define BIT_GET_MED_RATE_TRIG_SEL_8814B(x)                                     \
+	(((x) >> BIT_SHIFT_MED_RATE_TRIG_SEL_8814B) &                          \
+	 BIT_MASK_MED_RATE_TRIG_SEL_8814B)
+#define BIT_SET_MED_RATE_TRIG_SEL_8814B(x, v)                                  \
+	(BIT_CLEAR_MED_RATE_TRIG_SEL_8814B(x) | BIT_MED_RATE_TRIG_SEL_8814B(v))
+
+#define BIT_SHIFT_LOW_RATE_TRIG_SEL_8814B 16
+#define BIT_MASK_LOW_RATE_TRIG_SEL_8814B 0x3
+#define BIT_LOW_RATE_TRIG_SEL_8814B(x)                                         \
+	(((x) & BIT_MASK_LOW_RATE_TRIG_SEL_8814B)                              \
+	 << BIT_SHIFT_LOW_RATE_TRIG_SEL_8814B)
+#define BITS_LOW_RATE_TRIG_SEL_8814B                                           \
+	(BIT_MASK_LOW_RATE_TRIG_SEL_8814B << BIT_SHIFT_LOW_RATE_TRIG_SEL_8814B)
+#define BIT_CLEAR_LOW_RATE_TRIG_SEL_8814B(x)                                   \
+	((x) & (~BITS_LOW_RATE_TRIG_SEL_8814B))
+#define BIT_GET_LOW_RATE_TRIG_SEL_8814B(x)                                     \
+	(((x) >> BIT_SHIFT_LOW_RATE_TRIG_SEL_8814B) &                          \
+	 BIT_MASK_LOW_RATE_TRIG_SEL_8814B)
+#define BIT_SET_LOW_RATE_TRIG_SEL_8814B(x, v)                                  \
+	(BIT_CLEAR_LOW_RATE_TRIG_SEL_8814B(x) | BIT_LOW_RATE_TRIG_SEL_8814B(v))
+
+#define BIT_SHIFT_HIGH_RATE_BD_IDX_8814B 8
+#define BIT_MASK_HIGH_RATE_BD_IDX_8814B 0x7f
+#define BIT_HIGH_RATE_BD_IDX_8814B(x)                                          \
+	(((x) & BIT_MASK_HIGH_RATE_BD_IDX_8814B)                               \
+	 << BIT_SHIFT_HIGH_RATE_BD_IDX_8814B)
+#define BITS_HIGH_RATE_BD_IDX_8814B                                            \
+	(BIT_MASK_HIGH_RATE_BD_IDX_8814B << BIT_SHIFT_HIGH_RATE_BD_IDX_8814B)
+#define BIT_CLEAR_HIGH_RATE_BD_IDX_8814B(x)                                    \
+	((x) & (~BITS_HIGH_RATE_BD_IDX_8814B))
+#define BIT_GET_HIGH_RATE_BD_IDX_8814B(x)                                      \
+	(((x) >> BIT_SHIFT_HIGH_RATE_BD_IDX_8814B) &                           \
+	 BIT_MASK_HIGH_RATE_BD_IDX_8814B)
+#define BIT_SET_HIGH_RATE_BD_IDX_8814B(x, v)                                   \
+	(BIT_CLEAR_HIGH_RATE_BD_IDX_8814B(x) | BIT_HIGH_RATE_BD_IDX_8814B(v))
+
+#define BIT_SHIFT_LOW_RATE_BD_IDX_8814B 0
+#define BIT_MASK_LOW_RATE_BD_IDX_8814B 0x7f
+#define BIT_LOW_RATE_BD_IDX_8814B(x)                                           \
+	(((x) & BIT_MASK_LOW_RATE_BD_IDX_8814B)                                \
+	 << BIT_SHIFT_LOW_RATE_BD_IDX_8814B)
+#define BITS_LOW_RATE_BD_IDX_8814B                                             \
+	(BIT_MASK_LOW_RATE_BD_IDX_8814B << BIT_SHIFT_LOW_RATE_BD_IDX_8814B)
+#define BIT_CLEAR_LOW_RATE_BD_IDX_8814B(x) ((x) & (~BITS_LOW_RATE_BD_IDX_8814B))
+#define BIT_GET_LOW_RATE_BD_IDX_8814B(x)                                       \
+	(((x) >> BIT_SHIFT_LOW_RATE_BD_IDX_8814B) &                            \
+	 BIT_MASK_LOW_RATE_BD_IDX_8814B)
+#define BIT_SET_LOW_RATE_BD_IDX_8814B(x, v)                                    \
+	(BIT_CLEAR_LOW_RATE_BD_IDX_8814B(x) | BIT_LOW_RATE_BD_IDX_8814B(v))
+
+/* 2 REG_LTR_CTRL2_TIMER_THRESHOLD_8814B */
+
+#define BIT_SHIFT_RX_EMPTY_TIMER_IDX_8814B 24
+#define BIT_MASK_RX_EMPTY_TIMER_IDX_8814B 0x7
+#define BIT_RX_EMPTY_TIMER_IDX_8814B(x)                                        \
+	(((x) & BIT_MASK_RX_EMPTY_TIMER_IDX_8814B)                             \
+	 << BIT_SHIFT_RX_EMPTY_TIMER_IDX_8814B)
+#define BITS_RX_EMPTY_TIMER_IDX_8814B                                          \
+	(BIT_MASK_RX_EMPTY_TIMER_IDX_8814B                                     \
+	 << BIT_SHIFT_RX_EMPTY_TIMER_IDX_8814B)
+#define BIT_CLEAR_RX_EMPTY_TIMER_IDX_8814B(x)                                  \
+	((x) & (~BITS_RX_EMPTY_TIMER_IDX_8814B))
+#define BIT_GET_RX_EMPTY_TIMER_IDX_8814B(x)                                    \
+	(((x) >> BIT_SHIFT_RX_EMPTY_TIMER_IDX_8814B) &                         \
+	 BIT_MASK_RX_EMPTY_TIMER_IDX_8814B)
+#define BIT_SET_RX_EMPTY_TIMER_IDX_8814B(x, v)                                 \
+	(BIT_CLEAR_RX_EMPTY_TIMER_IDX_8814B(x) |                               \
+	 BIT_RX_EMPTY_TIMER_IDX_8814B(v))
+
+#define BIT_SHIFT_RX_AFULL_TH_IDX_8814B 20
+#define BIT_MASK_RX_AFULL_TH_IDX_8814B 0x7
+#define BIT_RX_AFULL_TH_IDX_8814B(x)                                           \
+	(((x) & BIT_MASK_RX_AFULL_TH_IDX_8814B)                                \
+	 << BIT_SHIFT_RX_AFULL_TH_IDX_8814B)
+#define BITS_RX_AFULL_TH_IDX_8814B                                             \
+	(BIT_MASK_RX_AFULL_TH_IDX_8814B << BIT_SHIFT_RX_AFULL_TH_IDX_8814B)
+#define BIT_CLEAR_RX_AFULL_TH_IDX_8814B(x) ((x) & (~BITS_RX_AFULL_TH_IDX_8814B))
+#define BIT_GET_RX_AFULL_TH_IDX_8814B(x)                                       \
+	(((x) >> BIT_SHIFT_RX_AFULL_TH_IDX_8814B) &                            \
+	 BIT_MASK_RX_AFULL_TH_IDX_8814B)
+#define BIT_SET_RX_AFULL_TH_IDX_8814B(x, v)                                    \
+	(BIT_CLEAR_RX_AFULL_TH_IDX_8814B(x) | BIT_RX_AFULL_TH_IDX_8814B(v))
+
+#define BIT_SHIFT_RX_HIGH_TH_IDX_8814B 16
+#define BIT_MASK_RX_HIGH_TH_IDX_8814B 0x7
+#define BIT_RX_HIGH_TH_IDX_8814B(x)                                            \
+	(((x) & BIT_MASK_RX_HIGH_TH_IDX_8814B)                                 \
+	 << BIT_SHIFT_RX_HIGH_TH_IDX_8814B)
+#define BITS_RX_HIGH_TH_IDX_8814B                                              \
+	(BIT_MASK_RX_HIGH_TH_IDX_8814B << BIT_SHIFT_RX_HIGH_TH_IDX_8814B)
+#define BIT_CLEAR_RX_HIGH_TH_IDX_8814B(x) ((x) & (~BITS_RX_HIGH_TH_IDX_8814B))
+#define BIT_GET_RX_HIGH_TH_IDX_8814B(x)                                        \
+	(((x) >> BIT_SHIFT_RX_HIGH_TH_IDX_8814B) &                             \
+	 BIT_MASK_RX_HIGH_TH_IDX_8814B)
+#define BIT_SET_RX_HIGH_TH_IDX_8814B(x, v)                                     \
+	(BIT_CLEAR_RX_HIGH_TH_IDX_8814B(x) | BIT_RX_HIGH_TH_IDX_8814B(v))
+
+#define BIT_SHIFT_RX_MED_TH_IDX_8814B 12
+#define BIT_MASK_RX_MED_TH_IDX_8814B 0x7
+#define BIT_RX_MED_TH_IDX_8814B(x)                                             \
+	(((x) & BIT_MASK_RX_MED_TH_IDX_8814B) << BIT_SHIFT_RX_MED_TH_IDX_8814B)
+#define BITS_RX_MED_TH_IDX_8814B                                               \
+	(BIT_MASK_RX_MED_TH_IDX_8814B << BIT_SHIFT_RX_MED_TH_IDX_8814B)
+#define BIT_CLEAR_RX_MED_TH_IDX_8814B(x) ((x) & (~BITS_RX_MED_TH_IDX_8814B))
+#define BIT_GET_RX_MED_TH_IDX_8814B(x)                                         \
+	(((x) >> BIT_SHIFT_RX_MED_TH_IDX_8814B) & BIT_MASK_RX_MED_TH_IDX_8814B)
+#define BIT_SET_RX_MED_TH_IDX_8814B(x, v)                                      \
+	(BIT_CLEAR_RX_MED_TH_IDX_8814B(x) | BIT_RX_MED_TH_IDX_8814B(v))
+
+#define BIT_SHIFT_RX_LOW_TH_IDX_8814B 8
+#define BIT_MASK_RX_LOW_TH_IDX_8814B 0x7
+#define BIT_RX_LOW_TH_IDX_8814B(x)                                             \
+	(((x) & BIT_MASK_RX_LOW_TH_IDX_8814B) << BIT_SHIFT_RX_LOW_TH_IDX_8814B)
+#define BITS_RX_LOW_TH_IDX_8814B                                               \
+	(BIT_MASK_RX_LOW_TH_IDX_8814B << BIT_SHIFT_RX_LOW_TH_IDX_8814B)
+#define BIT_CLEAR_RX_LOW_TH_IDX_8814B(x) ((x) & (~BITS_RX_LOW_TH_IDX_8814B))
+#define BIT_GET_RX_LOW_TH_IDX_8814B(x)                                         \
+	(((x) >> BIT_SHIFT_RX_LOW_TH_IDX_8814B) & BIT_MASK_RX_LOW_TH_IDX_8814B)
+#define BIT_SET_RX_LOW_TH_IDX_8814B(x, v)                                      \
+	(BIT_CLEAR_RX_LOW_TH_IDX_8814B(x) | BIT_RX_LOW_TH_IDX_8814B(v))
+
+#define BIT_SHIFT_LTR_SPACE_IDX_8814B 4
+#define BIT_MASK_LTR_SPACE_IDX_8814B 0x3
+#define BIT_LTR_SPACE_IDX_8814B(x)                                             \
+	(((x) & BIT_MASK_LTR_SPACE_IDX_8814B) << BIT_SHIFT_LTR_SPACE_IDX_8814B)
+#define BITS_LTR_SPACE_IDX_8814B                                               \
+	(BIT_MASK_LTR_SPACE_IDX_8814B << BIT_SHIFT_LTR_SPACE_IDX_8814B)
+#define BIT_CLEAR_LTR_SPACE_IDX_8814B(x) ((x) & (~BITS_LTR_SPACE_IDX_8814B))
+#define BIT_GET_LTR_SPACE_IDX_8814B(x)                                         \
+	(((x) >> BIT_SHIFT_LTR_SPACE_IDX_8814B) & BIT_MASK_LTR_SPACE_IDX_8814B)
+#define BIT_SET_LTR_SPACE_IDX_8814B(x, v)                                      \
+	(BIT_CLEAR_LTR_SPACE_IDX_8814B(x) | BIT_LTR_SPACE_IDX_8814B(v))
+
+#define BIT_SHIFT_LTR_IDLE_TIMER_IDX_8814B 0
+#define BIT_MASK_LTR_IDLE_TIMER_IDX_8814B 0x7
+#define BIT_LTR_IDLE_TIMER_IDX_8814B(x)                                        \
+	(((x) & BIT_MASK_LTR_IDLE_TIMER_IDX_8814B)                             \
+	 << BIT_SHIFT_LTR_IDLE_TIMER_IDX_8814B)
+#define BITS_LTR_IDLE_TIMER_IDX_8814B                                          \
+	(BIT_MASK_LTR_IDLE_TIMER_IDX_8814B                                     \
+	 << BIT_SHIFT_LTR_IDLE_TIMER_IDX_8814B)
+#define BIT_CLEAR_LTR_IDLE_TIMER_IDX_8814B(x)                                  \
+	((x) & (~BITS_LTR_IDLE_TIMER_IDX_8814B))
+#define BIT_GET_LTR_IDLE_TIMER_IDX_8814B(x)                                    \
+	(((x) >> BIT_SHIFT_LTR_IDLE_TIMER_IDX_8814B) &                         \
+	 BIT_MASK_LTR_IDLE_TIMER_IDX_8814B)
+#define BIT_SET_LTR_IDLE_TIMER_IDX_8814B(x, v)                                 \
+	(BIT_CLEAR_LTR_IDLE_TIMER_IDX_8814B(x) |                               \
+	 BIT_LTR_IDLE_TIMER_IDX_8814B(v))
+
+/* 2 REG_LTR_IDLE_LATENCY_V1_8814B */
+
+#define BIT_SHIFT_LTR_IDLE_L_8814B 0
+#define BIT_MASK_LTR_IDLE_L_8814B 0xffffffffL
+#define BIT_LTR_IDLE_L_8814B(x)                                                \
+	(((x) & BIT_MASK_LTR_IDLE_L_8814B) << BIT_SHIFT_LTR_IDLE_L_8814B)
+#define BITS_LTR_IDLE_L_8814B                                                  \
+	(BIT_MASK_LTR_IDLE_L_8814B << BIT_SHIFT_LTR_IDLE_L_8814B)
+#define BIT_CLEAR_LTR_IDLE_L_8814B(x) ((x) & (~BITS_LTR_IDLE_L_8814B))
+#define BIT_GET_LTR_IDLE_L_8814B(x)                                            \
+	(((x) >> BIT_SHIFT_LTR_IDLE_L_8814B) & BIT_MASK_LTR_IDLE_L_8814B)
+#define BIT_SET_LTR_IDLE_L_8814B(x, v)                                         \
+	(BIT_CLEAR_LTR_IDLE_L_8814B(x) | BIT_LTR_IDLE_L_8814B(v))
+
+/* 2 REG_LTR_ACTIVE_LATENCY_V1_8814B */
+
+#define BIT_SHIFT_LTR_ACT_L_8814B 0
+#define BIT_MASK_LTR_ACT_L_8814B 0xffffffffL
+#define BIT_LTR_ACT_L_8814B(x)                                                 \
+	(((x) & BIT_MASK_LTR_ACT_L_8814B) << BIT_SHIFT_LTR_ACT_L_8814B)
+#define BITS_LTR_ACT_L_8814B                                                   \
+	(BIT_MASK_LTR_ACT_L_8814B << BIT_SHIFT_LTR_ACT_L_8814B)
+#define BIT_CLEAR_LTR_ACT_L_8814B(x) ((x) & (~BITS_LTR_ACT_L_8814B))
+#define BIT_GET_LTR_ACT_L_8814B(x)                                             \
+	(((x) >> BIT_SHIFT_LTR_ACT_L_8814B) & BIT_MASK_LTR_ACT_L_8814B)
+#define BIT_SET_LTR_ACT_L_8814B(x, v)                                          \
+	(BIT_CLEAR_LTR_ACT_L_8814B(x) | BIT_LTR_ACT_L_8814B(v))
+
+#define BIT_SHIFT_ANT_ADDR2_1_8814B 0
+#define BIT_MASK_ANT_ADDR2_1_8814B 0xffffffffL
+#define BIT_ANT_ADDR2_1_8814B(x)                                               \
+	(((x) & BIT_MASK_ANT_ADDR2_1_8814B) << BIT_SHIFT_ANT_ADDR2_1_8814B)
+#define BITS_ANT_ADDR2_1_8814B                                                 \
+	(BIT_MASK_ANT_ADDR2_1_8814B << BIT_SHIFT_ANT_ADDR2_1_8814B)
+#define BIT_CLEAR_ANT_ADDR2_1_8814B(x) ((x) & (~BITS_ANT_ADDR2_1_8814B))
+#define BIT_GET_ANT_ADDR2_1_8814B(x)                                           \
+	(((x) >> BIT_SHIFT_ANT_ADDR2_1_8814B) & BIT_MASK_ANT_ADDR2_1_8814B)
+#define BIT_SET_ANT_ADDR2_1_8814B(x, v)                                        \
+	(BIT_CLEAR_ANT_ADDR2_1_8814B(x) | BIT_ANT_ADDR2_1_8814B(v))
+
+/* 2 REG_SMART_ANT_CTRL_8814B */
+#define BIT_ANTTRN_SWITCH_8814B BIT(19)
+#define BIT_APPEND_MACID_IN_RESP_EN_1_8814B BIT(18)
+#define BIT_ADDR2_MATCH_EN_1_8814B BIT(17)
+#define BIT_ANTTRN_EN_1_8814B BIT(16)
+
+#define BIT_SHIFT_ANT_ADDR2_2_8814B 0
+#define BIT_MASK_ANT_ADDR2_2_8814B 0xffff
+#define BIT_ANT_ADDR2_2_8814B(x)                                               \
+	(((x) & BIT_MASK_ANT_ADDR2_2_8814B) << BIT_SHIFT_ANT_ADDR2_2_8814B)
+#define BITS_ANT_ADDR2_2_8814B                                                 \
+	(BIT_MASK_ANT_ADDR2_2_8814B << BIT_SHIFT_ANT_ADDR2_2_8814B)
+#define BIT_CLEAR_ANT_ADDR2_2_8814B(x) ((x) & (~BITS_ANT_ADDR2_2_8814B))
+#define BIT_GET_ANT_ADDR2_2_8814B(x)                                           \
+	(((x) >> BIT_SHIFT_ANT_ADDR2_2_8814B) & BIT_MASK_ANT_ADDR2_2_8814B)
+#define BIT_SET_ANT_ADDR2_2_8814B(x, v)                                        \
+	(BIT_CLEAR_ANT_ADDR2_2_8814B(x) | BIT_ANT_ADDR2_2_8814B(v))
+
+/* 2 REG_CONTROL_FRAME_REPORT_8814B */
+
+#define BIT_SHIFT_CONTROL_FRAME_REPORT_8814B 0
+#define BIT_MASK_CONTROL_FRAME_REPORT_8814B 0xffffffffL
+#define BIT_CONTROL_FRAME_REPORT_8814B(x)                                      \
+	(((x) & BIT_MASK_CONTROL_FRAME_REPORT_8814B)                           \
+	 << BIT_SHIFT_CONTROL_FRAME_REPORT_8814B)
+#define BITS_CONTROL_FRAME_REPORT_8814B                                        \
+	(BIT_MASK_CONTROL_FRAME_REPORT_8814B                                   \
+	 << BIT_SHIFT_CONTROL_FRAME_REPORT_8814B)
+#define BIT_CLEAR_CONTROL_FRAME_REPORT_8814B(x)                                \
+	((x) & (~BITS_CONTROL_FRAME_REPORT_8814B))
+#define BIT_GET_CONTROL_FRAME_REPORT_8814B(x)                                  \
+	(((x) >> BIT_SHIFT_CONTROL_FRAME_REPORT_8814B) &                       \
+	 BIT_MASK_CONTROL_FRAME_REPORT_8814B)
+#define BIT_SET_CONTROL_FRAME_REPORT_8814B(x, v)                               \
+	(BIT_CLEAR_CONTROL_FRAME_REPORT_8814B(x) |                             \
+	 BIT_CONTROL_FRAME_REPORT_8814B(v))
+
+/* 2 REG_CONTROL_FRAME_CNT_CTRL_8814B */
+#define BIT_ALLCNTRST_8814B BIT(9)
+#define BIT__ALLCNTEN_8814B BIT(8)
+
+#define BIT_SHIFT_ADDR_8814B 4
+#define BIT_MASK_ADDR_8814B 0xf
+#define BIT_ADDR_8814B(x) (((x) & BIT_MASK_ADDR_8814B) << BIT_SHIFT_ADDR_8814B)
+#define BITS_ADDR_8814B (BIT_MASK_ADDR_8814B << BIT_SHIFT_ADDR_8814B)
+#define BIT_CLEAR_ADDR_8814B(x) ((x) & (~BITS_ADDR_8814B))
+#define BIT_GET_ADDR_8814B(x)                                                  \
+	(((x) >> BIT_SHIFT_ADDR_8814B) & BIT_MASK_ADDR_8814B)
+#define BIT_SET_ADDR_8814B(x, v) (BIT_CLEAR_ADDR_8814B(x) | BIT_ADDR_8814B(v))
+
+#define BIT_SHIFT_CTRL_SEL_8814B 0
+#define BIT_MASK_CTRL_SEL_8814B 0xf
+#define BIT_CTRL_SEL_8814B(x)                                                  \
+	(((x) & BIT_MASK_CTRL_SEL_8814B) << BIT_SHIFT_CTRL_SEL_8814B)
+#define BITS_CTRL_SEL_8814B                                                    \
+	(BIT_MASK_CTRL_SEL_8814B << BIT_SHIFT_CTRL_SEL_8814B)
+#define BIT_CLEAR_CTRL_SEL_8814B(x) ((x) & (~BITS_CTRL_SEL_8814B))
+#define BIT_GET_CTRL_SEL_8814B(x)                                              \
+	(((x) >> BIT_SHIFT_CTRL_SEL_8814B) & BIT_MASK_CTRL_SEL_8814B)
+#define BIT_SET_CTRL_SEL_8814B(x, v)                                           \
+	(BIT_CLEAR_CTRL_SEL_8814B(x) | BIT_CTRL_SEL_8814B(v))
+
+/* 2 REG_IQ_DUMP_8814B */
+
+#define BIT_SHIFT_DUMP_OK_ADDR_8814B 16
+#define BIT_MASK_DUMP_OK_ADDR_8814B 0xffff
+#define BIT_DUMP_OK_ADDR_8814B(x)                                              \
+	(((x) & BIT_MASK_DUMP_OK_ADDR_8814B) << BIT_SHIFT_DUMP_OK_ADDR_8814B)
+#define BITS_DUMP_OK_ADDR_8814B                                                \
+	(BIT_MASK_DUMP_OK_ADDR_8814B << BIT_SHIFT_DUMP_OK_ADDR_8814B)
+#define BIT_CLEAR_DUMP_OK_ADDR_8814B(x) ((x) & (~BITS_DUMP_OK_ADDR_8814B))
+#define BIT_GET_DUMP_OK_ADDR_8814B(x)                                          \
+	(((x) >> BIT_SHIFT_DUMP_OK_ADDR_8814B) & BIT_MASK_DUMP_OK_ADDR_8814B)
+#define BIT_SET_DUMP_OK_ADDR_8814B(x, v)                                       \
+	(BIT_CLEAR_DUMP_OK_ADDR_8814B(x) | BIT_DUMP_OK_ADDR_8814B(v))
+
+#define BIT_SHIFT_R_TRIG_TIME_SEL_8814B 8
+#define BIT_MASK_R_TRIG_TIME_SEL_8814B 0x7f
+#define BIT_R_TRIG_TIME_SEL_8814B(x)                                           \
+	(((x) & BIT_MASK_R_TRIG_TIME_SEL_8814B)                                \
+	 << BIT_SHIFT_R_TRIG_TIME_SEL_8814B)
+#define BITS_R_TRIG_TIME_SEL_8814B                                             \
+	(BIT_MASK_R_TRIG_TIME_SEL_8814B << BIT_SHIFT_R_TRIG_TIME_SEL_8814B)
+#define BIT_CLEAR_R_TRIG_TIME_SEL_8814B(x) ((x) & (~BITS_R_TRIG_TIME_SEL_8814B))
+#define BIT_GET_R_TRIG_TIME_SEL_8814B(x)                                       \
+	(((x) >> BIT_SHIFT_R_TRIG_TIME_SEL_8814B) &                            \
+	 BIT_MASK_R_TRIG_TIME_SEL_8814B)
+#define BIT_SET_R_TRIG_TIME_SEL_8814B(x, v)                                    \
+	(BIT_CLEAR_R_TRIG_TIME_SEL_8814B(x) | BIT_R_TRIG_TIME_SEL_8814B(v))
+
+#define BIT_SHIFT_R_MAC_TRIG_SEL_8814B 6
+#define BIT_MASK_R_MAC_TRIG_SEL_8814B 0x3
+#define BIT_R_MAC_TRIG_SEL_8814B(x)                                            \
+	(((x) & BIT_MASK_R_MAC_TRIG_SEL_8814B)                                 \
+	 << BIT_SHIFT_R_MAC_TRIG_SEL_8814B)
+#define BITS_R_MAC_TRIG_SEL_8814B                                              \
+	(BIT_MASK_R_MAC_TRIG_SEL_8814B << BIT_SHIFT_R_MAC_TRIG_SEL_8814B)
+#define BIT_CLEAR_R_MAC_TRIG_SEL_8814B(x) ((x) & (~BITS_R_MAC_TRIG_SEL_8814B))
+#define BIT_GET_R_MAC_TRIG_SEL_8814B(x)                                        \
+	(((x) >> BIT_SHIFT_R_MAC_TRIG_SEL_8814B) &                             \
+	 BIT_MASK_R_MAC_TRIG_SEL_8814B)
+#define BIT_SET_R_MAC_TRIG_SEL_8814B(x, v)                                     \
+	(BIT_CLEAR_R_MAC_TRIG_SEL_8814B(x) | BIT_R_MAC_TRIG_SEL_8814B(v))
+
+#define BIT_MAC_TRIG_REG_8814B BIT(5)
+
+#define BIT_SHIFT_R_LEVEL_PULSE_SEL_8814B 3
+#define BIT_MASK_R_LEVEL_PULSE_SEL_8814B 0x3
+#define BIT_R_LEVEL_PULSE_SEL_8814B(x)                                         \
+	(((x) & BIT_MASK_R_LEVEL_PULSE_SEL_8814B)                              \
+	 << BIT_SHIFT_R_LEVEL_PULSE_SEL_8814B)
+#define BITS_R_LEVEL_PULSE_SEL_8814B                                           \
+	(BIT_MASK_R_LEVEL_PULSE_SEL_8814B << BIT_SHIFT_R_LEVEL_PULSE_SEL_8814B)
+#define BIT_CLEAR_R_LEVEL_PULSE_SEL_8814B(x)                                   \
+	((x) & (~BITS_R_LEVEL_PULSE_SEL_8814B))
+#define BIT_GET_R_LEVEL_PULSE_SEL_8814B(x)                                     \
+	(((x) >> BIT_SHIFT_R_LEVEL_PULSE_SEL_8814B) &                          \
+	 BIT_MASK_R_LEVEL_PULSE_SEL_8814B)
+#define BIT_SET_R_LEVEL_PULSE_SEL_8814B(x, v)                                  \
+	(BIT_CLEAR_R_LEVEL_PULSE_SEL_8814B(x) | BIT_R_LEVEL_PULSE_SEL_8814B(v))
+
+#define BIT_EN_LA_MAC_8814B BIT(2)
+#define BIT_R_EN_IQDUMP_8814B BIT(1)
+#define BIT_R_IQDATA_DUMP_8814B BIT(0)
+
+/* 2 REG_IQ_DUMP_1_8814B */
+
+#define BIT_SHIFT_R_WMAC_MASK_LA_MAC_1_8814B 0
+#define BIT_MASK_R_WMAC_MASK_LA_MAC_1_8814B 0xffffffffL
+#define BIT_R_WMAC_MASK_LA_MAC_1_8814B(x)                                      \
+	(((x) & BIT_MASK_R_WMAC_MASK_LA_MAC_1_8814B)                           \
+	 << BIT_SHIFT_R_WMAC_MASK_LA_MAC_1_8814B)
+#define BITS_R_WMAC_MASK_LA_MAC_1_8814B                                        \
+	(BIT_MASK_R_WMAC_MASK_LA_MAC_1_8814B                                   \
+	 << BIT_SHIFT_R_WMAC_MASK_LA_MAC_1_8814B)
+#define BIT_CLEAR_R_WMAC_MASK_LA_MAC_1_8814B(x)                                \
+	((x) & (~BITS_R_WMAC_MASK_LA_MAC_1_8814B))
+#define BIT_GET_R_WMAC_MASK_LA_MAC_1_8814B(x)                                  \
+	(((x) >> BIT_SHIFT_R_WMAC_MASK_LA_MAC_1_8814B) &                       \
+	 BIT_MASK_R_WMAC_MASK_LA_MAC_1_8814B)
+#define BIT_SET_R_WMAC_MASK_LA_MAC_1_8814B(x, v)                               \
+	(BIT_CLEAR_R_WMAC_MASK_LA_MAC_1_8814B(x) |                             \
+	 BIT_R_WMAC_MASK_LA_MAC_1_8814B(v))
+
+/* 2 REG_IQ_DUMP_2_8814B */
+
+#define BIT_SHIFT_R_WMAC_MATCH_REF_MAC_2_8814B 0
+#define BIT_MASK_R_WMAC_MATCH_REF_MAC_2_8814B 0xffffffffL
+#define BIT_R_WMAC_MATCH_REF_MAC_2_8814B(x)                                    \
+	(((x) & BIT_MASK_R_WMAC_MATCH_REF_MAC_2_8814B)                         \
+	 << BIT_SHIFT_R_WMAC_MATCH_REF_MAC_2_8814B)
+#define BITS_R_WMAC_MATCH_REF_MAC_2_8814B                                      \
+	(BIT_MASK_R_WMAC_MATCH_REF_MAC_2_8814B                                 \
+	 << BIT_SHIFT_R_WMAC_MATCH_REF_MAC_2_8814B)
+#define BIT_CLEAR_R_WMAC_MATCH_REF_MAC_2_8814B(x)                              \
+	((x) & (~BITS_R_WMAC_MATCH_REF_MAC_2_8814B))
+#define BIT_GET_R_WMAC_MATCH_REF_MAC_2_8814B(x)                                \
+	(((x) >> BIT_SHIFT_R_WMAC_MATCH_REF_MAC_2_8814B) &                     \
+	 BIT_MASK_R_WMAC_MATCH_REF_MAC_2_8814B)
+#define BIT_SET_R_WMAC_MATCH_REF_MAC_2_8814B(x, v)                             \
+	(BIT_CLEAR_R_WMAC_MATCH_REF_MAC_2_8814B(x) |                           \
+	 BIT_R_WMAC_MATCH_REF_MAC_2_8814B(v))
+
+/* 2 REG_WMAC_FTM_CTL_8814B */
+#define BIT_RXFTM_TXACK_SC_8814B BIT(6)
+#define BIT_RXFTM_TXACK_BW_8814B BIT(5)
+#define BIT_RXFTM_EN_8814B BIT(3)
+#define BIT_RXFTMREQ_BYDRV_8814B BIT(2)
+#define BIT_RXFTMREQ_EN_8814B BIT(1)
+#define BIT_FTM_EN_8814B BIT(0)
+
+/* 2 REG_WMAC_IQ_MDPK_FUNC_8814B */
+
+/* 2 REG_WMAC_OPTION_FUNCTION_8814B */
+
+#define BIT_SHIFT_R_OFDM_LEN_8814B 26
+#define BIT_MASK_R_OFDM_LEN_8814B 0x3f
+#define BIT_R_OFDM_LEN_8814B(x)                                                \
+	(((x) & BIT_MASK_R_OFDM_LEN_8814B) << BIT_SHIFT_R_OFDM_LEN_8814B)
+#define BITS_R_OFDM_LEN_8814B                                                  \
+	(BIT_MASK_R_OFDM_LEN_8814B << BIT_SHIFT_R_OFDM_LEN_8814B)
+#define BIT_CLEAR_R_OFDM_LEN_8814B(x) ((x) & (~BITS_R_OFDM_LEN_8814B))
+#define BIT_GET_R_OFDM_LEN_8814B(x)                                            \
+	(((x) >> BIT_SHIFT_R_OFDM_LEN_8814B) & BIT_MASK_R_OFDM_LEN_8814B)
+#define BIT_SET_R_OFDM_LEN_8814B(x, v)                                         \
+	(BIT_CLEAR_R_OFDM_LEN_8814B(x) | BIT_R_OFDM_LEN_8814B(v))
+
+#define BIT_SHIFT_R_CCK_LEN_8814B 0
+#define BIT_MASK_R_CCK_LEN_8814B 0xffff
+#define BIT_R_CCK_LEN_8814B(x)                                                 \
+	(((x) & BIT_MASK_R_CCK_LEN_8814B) << BIT_SHIFT_R_CCK_LEN_8814B)
+#define BITS_R_CCK_LEN_8814B                                                   \
+	(BIT_MASK_R_CCK_LEN_8814B << BIT_SHIFT_R_CCK_LEN_8814B)
+#define BIT_CLEAR_R_CCK_LEN_8814B(x) ((x) & (~BITS_R_CCK_LEN_8814B))
+#define BIT_GET_R_CCK_LEN_8814B(x)                                             \
+	(((x) >> BIT_SHIFT_R_CCK_LEN_8814B) & BIT_MASK_R_CCK_LEN_8814B)
+#define BIT_SET_R_CCK_LEN_8814B(x, v)                                          \
+	(BIT_CLEAR_R_CCK_LEN_8814B(x) | BIT_R_CCK_LEN_8814B(v))
+
+/* 2 REG_WMAC_OPTION_FUNCTION_1_8814B */
+
+#define BIT_SHIFT_R_WMAC_RXFIFO_FULL_TH_1_8814B 24
+#define BIT_MASK_R_WMAC_RXFIFO_FULL_TH_1_8814B 0xff
+#define BIT_R_WMAC_RXFIFO_FULL_TH_1_8814B(x)                                   \
+	(((x) & BIT_MASK_R_WMAC_RXFIFO_FULL_TH_1_8814B)                        \
+	 << BIT_SHIFT_R_WMAC_RXFIFO_FULL_TH_1_8814B)
+#define BITS_R_WMAC_RXFIFO_FULL_TH_1_8814B                                     \
+	(BIT_MASK_R_WMAC_RXFIFO_FULL_TH_1_8814B                                \
+	 << BIT_SHIFT_R_WMAC_RXFIFO_FULL_TH_1_8814B)
+#define BIT_CLEAR_R_WMAC_RXFIFO_FULL_TH_1_8814B(x)                             \
+	((x) & (~BITS_R_WMAC_RXFIFO_FULL_TH_1_8814B))
+#define BIT_GET_R_WMAC_RXFIFO_FULL_TH_1_8814B(x)                               \
+	(((x) >> BIT_SHIFT_R_WMAC_RXFIFO_FULL_TH_1_8814B) &                    \
+	 BIT_MASK_R_WMAC_RXFIFO_FULL_TH_1_8814B)
+#define BIT_SET_R_WMAC_RXFIFO_FULL_TH_1_8814B(x, v)                            \
+	(BIT_CLEAR_R_WMAC_RXFIFO_FULL_TH_1_8814B(x) |                          \
+	 BIT_R_WMAC_RXFIFO_FULL_TH_1_8814B(v))
+
+#define BIT_R_WMAC_RX_SYNCFIFO_SYNC_1_8814B BIT(23)
+#define BIT_R_WMAC_RXRST_DLY_1_8814B BIT(22)
+#define BIT_R_WMAC_SRCH_TXRPT_REF_DROP_1_8814B BIT(21)
+#define BIT_R_WMAC_SRCH_TXRPT_UA1_1_8814B BIT(20)
+#define BIT_R_WMAC_SRCH_TXRPT_TYPE_1_8814B BIT(19)
+#define BIT_R_WMAC_NDP_RST_1_8814B BIT(18)
+#define BIT_R_WMAC_POWINT_EN_1_8814B BIT(17)
+#define BIT_R_WMAC_SRCH_TXRPT_PERPKT_1_8814B BIT(16)
+#define BIT_R_WMAC_SRCH_TXRPT_MID_1_8814B BIT(15)
+#define BIT_R_WMAC_PFIN_TOEN_1_8814B BIT(14)
+#define BIT_R_WMAC_FIL_SECERR_1_8814B BIT(13)
+#define BIT_R_WMAC_FIL_CTLPKTLEN_1_8814B BIT(12)
+#define BIT_R_WMAC_FIL_FCTYPE_1_8814B BIT(11)
+#define BIT_R_WMAC_FIL_FCPROVER_1_8814B BIT(10)
+#define BIT_R_WMAC_PHYSTS_SNIF_1_8814B BIT(9)
+#define BIT_R_WMAC_PHYSTS_PLCP_1_8814B BIT(8)
+#define BIT_R_MAC_TCR_VBONF_RD_1_8814B BIT(7)
+#define BIT_R_WMAC_TCR_MPAR_NDP_1_8814B BIT(6)
+#define BIT_R_WMAC_NDP_FILTER_1_8814B BIT(5)
+#define BIT_R_WMAC_RXLEN_SEL_1_8814B BIT(4)
+#define BIT_R_WMAC_RXLEN_SEL1_1_8814B BIT(3)
+#define BIT_R_OFDM_FILTER_1_8814B BIT(2)
+#define BIT_R_WMAC_CHK_OFDM_LEN_1_8814B BIT(1)
+#define BIT_R_WMAC_CHK_CCK_LEN_1_8814B BIT(0)
+
+/* 2 REG_WMAC_OPTION_FUNCTION_2_8814B */
+
+#define BIT_SHIFT_R_WMAC_RX_FIL_LEN_2_8814B 0
+#define BIT_MASK_R_WMAC_RX_FIL_LEN_2_8814B 0xffff
+#define BIT_R_WMAC_RX_FIL_LEN_2_8814B(x)                                       \
+	(((x) & BIT_MASK_R_WMAC_RX_FIL_LEN_2_8814B)                            \
+	 << BIT_SHIFT_R_WMAC_RX_FIL_LEN_2_8814B)
+#define BITS_R_WMAC_RX_FIL_LEN_2_8814B                                         \
+	(BIT_MASK_R_WMAC_RX_FIL_LEN_2_8814B                                    \
+	 << BIT_SHIFT_R_WMAC_RX_FIL_LEN_2_8814B)
+#define BIT_CLEAR_R_WMAC_RX_FIL_LEN_2_8814B(x)                                 \
+	((x) & (~BITS_R_WMAC_RX_FIL_LEN_2_8814B))
+#define BIT_GET_R_WMAC_RX_FIL_LEN_2_8814B(x)                                   \
+	(((x) >> BIT_SHIFT_R_WMAC_RX_FIL_LEN_2_8814B) &                        \
+	 BIT_MASK_R_WMAC_RX_FIL_LEN_2_8814B)
+#define BIT_SET_R_WMAC_RX_FIL_LEN_2_8814B(x, v)                                \
+	(BIT_CLEAR_R_WMAC_RX_FIL_LEN_2_8814B(x) |                              \
+	 BIT_R_WMAC_RX_FIL_LEN_2_8814B(v))
+
+/* 2 REG_RX_FILTER_FUNCTION_8814B */
+#define BIT_R_WMAC_MHRDDY_LATCH_8814B BIT(14)
+#define BIT_R_WMAC_MHRDDY_CLR_8814B BIT(13)
+#define BIT_R_RXPKTCTL_FSM_BASED_MPDURDY1_8814B BIT(12)
+#define BIT_WMAC_DIS_VHT_PLCP_CHK_MU_8814B BIT(11)
+#define BIT_R_CHK_DELIMIT_LEN_8814B BIT(10)
+#define BIT_R_REAPTER_ADDR_MATCH_8814B BIT(9)
+#define BIT_R_RXPKTCTL_FSM_BASED_MPDURDY_8814B BIT(8)
+#define BIT_R_LATCH_MACHRDY_8814B BIT(7)
+#define BIT_R_WMAC_RXFIL_REND_8814B BIT(6)
+#define BIT_R_WMAC_MPDURDY_CLR_8814B BIT(5)
+#define BIT_R_WMAC_CLRRXSEC_8814B BIT(4)
+#define BIT_R_WMAC_RXFIL_RDEL_8814B BIT(3)
+#define BIT_R_WMAC_RXFIL_FCSE_8814B BIT(2)
+#define BIT_R_WMAC_RXFIL_MESH_DEL_8814B BIT(1)
+#define BIT_R_WMAC_RXFIL_MASKM_8814B BIT(0)
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NDP_SIG_8814B */
+
+#define BIT_SHIFT_R_WMAC_TXNDP_SIGB_8814B 0
+#define BIT_MASK_R_WMAC_TXNDP_SIGB_8814B 0x1fffff
+#define BIT_R_WMAC_TXNDP_SIGB_8814B(x)                                         \
+	(((x) & BIT_MASK_R_WMAC_TXNDP_SIGB_8814B)                              \
+	 << BIT_SHIFT_R_WMAC_TXNDP_SIGB_8814B)
+#define BITS_R_WMAC_TXNDP_SIGB_8814B                                           \
+	(BIT_MASK_R_WMAC_TXNDP_SIGB_8814B << BIT_SHIFT_R_WMAC_TXNDP_SIGB_8814B)
+#define BIT_CLEAR_R_WMAC_TXNDP_SIGB_8814B(x)                                   \
+	((x) & (~BITS_R_WMAC_TXNDP_SIGB_8814B))
+#define BIT_GET_R_WMAC_TXNDP_SIGB_8814B(x)                                     \
+	(((x) >> BIT_SHIFT_R_WMAC_TXNDP_SIGB_8814B) &                          \
+	 BIT_MASK_R_WMAC_TXNDP_SIGB_8814B)
+#define BIT_SET_R_WMAC_TXNDP_SIGB_8814B(x, v)                                  \
+	(BIT_CLEAR_R_WMAC_TXNDP_SIGB_8814B(x) | BIT_R_WMAC_TXNDP_SIGB_8814B(v))
+
+/* 2 REG_TXCMD_INFO_FOR_RSP_PKT_8814B */
+
+#define BIT_SHIFT_R_MAC_DBG_SHIFT_8814B 8
+#define BIT_MASK_R_MAC_DBG_SHIFT_8814B 0x7
+#define BIT_R_MAC_DBG_SHIFT_8814B(x)                                           \
+	(((x) & BIT_MASK_R_MAC_DBG_SHIFT_8814B)                                \
+	 << BIT_SHIFT_R_MAC_DBG_SHIFT_8814B)
+#define BITS_R_MAC_DBG_SHIFT_8814B                                             \
+	(BIT_MASK_R_MAC_DBG_SHIFT_8814B << BIT_SHIFT_R_MAC_DBG_SHIFT_8814B)
+#define BIT_CLEAR_R_MAC_DBG_SHIFT_8814B(x) ((x) & (~BITS_R_MAC_DBG_SHIFT_8814B))
+#define BIT_GET_R_MAC_DBG_SHIFT_8814B(x)                                       \
+	(((x) >> BIT_SHIFT_R_MAC_DBG_SHIFT_8814B) &                            \
+	 BIT_MASK_R_MAC_DBG_SHIFT_8814B)
+#define BIT_SET_R_MAC_DBG_SHIFT_8814B(x, v)                                    \
+	(BIT_CLEAR_R_MAC_DBG_SHIFT_8814B(x) | BIT_R_MAC_DBG_SHIFT_8814B(v))
+
+#define BIT_SHIFT_R_MAC_DBG_SEL_8814B 0
+#define BIT_MASK_R_MAC_DBG_SEL_8814B 0x3
+#define BIT_R_MAC_DBG_SEL_8814B(x)                                             \
+	(((x) & BIT_MASK_R_MAC_DBG_SEL_8814B) << BIT_SHIFT_R_MAC_DBG_SEL_8814B)
+#define BITS_R_MAC_DBG_SEL_8814B                                               \
+	(BIT_MASK_R_MAC_DBG_SEL_8814B << BIT_SHIFT_R_MAC_DBG_SEL_8814B)
+#define BIT_CLEAR_R_MAC_DBG_SEL_8814B(x) ((x) & (~BITS_R_MAC_DBG_SEL_8814B))
+#define BIT_GET_R_MAC_DBG_SEL_8814B(x)                                         \
+	(((x) >> BIT_SHIFT_R_MAC_DBG_SEL_8814B) & BIT_MASK_R_MAC_DBG_SEL_8814B)
+#define BIT_SET_R_MAC_DBG_SEL_8814B(x, v)                                      \
+	(BIT_CLEAR_R_MAC_DBG_SEL_8814B(x) | BIT_R_MAC_DBG_SEL_8814B(v))
+
+/* 2 REG_TXCMD_INFO_FOR_RSP_PKT_1_8814B */
+
+#define BIT_SHIFT_R_MAC_DEBUG_1_8814B 0
+#define BIT_MASK_R_MAC_DEBUG_1_8814B 0xffffffffL
+#define BIT_R_MAC_DEBUG_1_8814B(x)                                             \
+	(((x) & BIT_MASK_R_MAC_DEBUG_1_8814B) << BIT_SHIFT_R_MAC_DEBUG_1_8814B)
+#define BITS_R_MAC_DEBUG_1_8814B                                               \
+	(BIT_MASK_R_MAC_DEBUG_1_8814B << BIT_SHIFT_R_MAC_DEBUG_1_8814B)
+#define BIT_CLEAR_R_MAC_DEBUG_1_8814B(x) ((x) & (~BITS_R_MAC_DEBUG_1_8814B))
+#define BIT_GET_R_MAC_DEBUG_1_8814B(x)                                         \
+	(((x) >> BIT_SHIFT_R_MAC_DEBUG_1_8814B) & BIT_MASK_R_MAC_DEBUG_1_8814B)
+#define BIT_SET_R_MAC_DEBUG_1_8814B(x, v)                                      \
+	(BIT_CLEAR_R_MAC_DEBUG_1_8814B(x) | BIT_R_MAC_DEBUG_1_8814B(v))
+
+/* 2 REG_WSEC_OPTION_8814B */
+#define BIT_RXDEC_BM_MGNT_8814B BIT(22)
+#define BIT_TXENC_BM_MGNT_8814B BIT(21)
+#define BIT_RXDEC_UNI_MGNT_8814B BIT(20)
+#define BIT_TXENC_UNI_MGNT_8814B BIT(19)
+
+/* 2 REG_RTS_ADDRESS_0_8814B */
+
+/* 2 REG_RTS_ADDRESS_0_1_8814B */
+
+/* 2 REG_RTS_ADDRESS_1_8814B */
+
+/* 2 REG_RTS_ADDRESS_1_1_8814B */
+
+/* 2 REG_WL2LTECOEX_INDIRECT_ACCESS_CTRL_V1_8814B */
+#define BIT_LTECOEX_ACCESS_START_V1_8814B BIT(31)
+#define BIT_LTECOEX_WRITE_MODE_V1_8814B BIT(30)
+#define BIT_LTECOEX_READY_BIT_V1_8814B BIT(29)
+
+#define BIT_SHIFT_WRITE_BYTE_EN_V1_8814B 16
+#define BIT_MASK_WRITE_BYTE_EN_V1_8814B 0xf
+#define BIT_WRITE_BYTE_EN_V1_8814B(x)                                          \
+	(((x) & BIT_MASK_WRITE_BYTE_EN_V1_8814B)                               \
+	 << BIT_SHIFT_WRITE_BYTE_EN_V1_8814B)
+#define BITS_WRITE_BYTE_EN_V1_8814B                                            \
+	(BIT_MASK_WRITE_BYTE_EN_V1_8814B << BIT_SHIFT_WRITE_BYTE_EN_V1_8814B)
+#define BIT_CLEAR_WRITE_BYTE_EN_V1_8814B(x)                                    \
+	((x) & (~BITS_WRITE_BYTE_EN_V1_8814B))
+#define BIT_GET_WRITE_BYTE_EN_V1_8814B(x)                                      \
+	(((x) >> BIT_SHIFT_WRITE_BYTE_EN_V1_8814B) &                           \
+	 BIT_MASK_WRITE_BYTE_EN_V1_8814B)
+#define BIT_SET_WRITE_BYTE_EN_V1_8814B(x, v)                                   \
+	(BIT_CLEAR_WRITE_BYTE_EN_V1_8814B(x) | BIT_WRITE_BYTE_EN_V1_8814B(v))
+
+#define BIT_SHIFT_LTECOEX_REG_ADDR_V1_8814B 0
+#define BIT_MASK_LTECOEX_REG_ADDR_V1_8814B 0xffff
+#define BIT_LTECOEX_REG_ADDR_V1_8814B(x)                                       \
+	(((x) & BIT_MASK_LTECOEX_REG_ADDR_V1_8814B)                            \
+	 << BIT_SHIFT_LTECOEX_REG_ADDR_V1_8814B)
+#define BITS_LTECOEX_REG_ADDR_V1_8814B                                         \
+	(BIT_MASK_LTECOEX_REG_ADDR_V1_8814B                                    \
+	 << BIT_SHIFT_LTECOEX_REG_ADDR_V1_8814B)
+#define BIT_CLEAR_LTECOEX_REG_ADDR_V1_8814B(x)                                 \
+	((x) & (~BITS_LTECOEX_REG_ADDR_V1_8814B))
+#define BIT_GET_LTECOEX_REG_ADDR_V1_8814B(x)                                   \
+	(((x) >> BIT_SHIFT_LTECOEX_REG_ADDR_V1_8814B) &                        \
+	 BIT_MASK_LTECOEX_REG_ADDR_V1_8814B)
+#define BIT_SET_LTECOEX_REG_ADDR_V1_8814B(x, v)                                \
+	(BIT_CLEAR_LTECOEX_REG_ADDR_V1_8814B(x) |                              \
+	 BIT_LTECOEX_REG_ADDR_V1_8814B(v))
+
+/* 2 REG_WL2LTECOEX_INDIRECT_ACCESS_WRITE_DATA_V1_8814B */
+
+#define BIT_SHIFT_LTECOEX_W_DATA_V1_8814B 0
+#define BIT_MASK_LTECOEX_W_DATA_V1_8814B 0xffffffffL
+#define BIT_LTECOEX_W_DATA_V1_8814B(x)                                         \
+	(((x) & BIT_MASK_LTECOEX_W_DATA_V1_8814B)                              \
+	 << BIT_SHIFT_LTECOEX_W_DATA_V1_8814B)
+#define BITS_LTECOEX_W_DATA_V1_8814B                                           \
+	(BIT_MASK_LTECOEX_W_DATA_V1_8814B << BIT_SHIFT_LTECOEX_W_DATA_V1_8814B)
+#define BIT_CLEAR_LTECOEX_W_DATA_V1_8814B(x)                                   \
+	((x) & (~BITS_LTECOEX_W_DATA_V1_8814B))
+#define BIT_GET_LTECOEX_W_DATA_V1_8814B(x)                                     \
+	(((x) >> BIT_SHIFT_LTECOEX_W_DATA_V1_8814B) &                          \
+	 BIT_MASK_LTECOEX_W_DATA_V1_8814B)
+#define BIT_SET_LTECOEX_W_DATA_V1_8814B(x, v)                                  \
+	(BIT_CLEAR_LTECOEX_W_DATA_V1_8814B(x) | BIT_LTECOEX_W_DATA_V1_8814B(v))
+
+/* 2 REG_WL2LTECOEX_INDIRECT_ACCESS_READ_DATA_V1_8814B */
+
+#define BIT_SHIFT_LTECOEX_R_DATA_V1_8814B 0
+#define BIT_MASK_LTECOEX_R_DATA_V1_8814B 0xffffffffL
+#define BIT_LTECOEX_R_DATA_V1_8814B(x)                                         \
+	(((x) & BIT_MASK_LTECOEX_R_DATA_V1_8814B)                              \
+	 << BIT_SHIFT_LTECOEX_R_DATA_V1_8814B)
+#define BITS_LTECOEX_R_DATA_V1_8814B                                           \
+	(BIT_MASK_LTECOEX_R_DATA_V1_8814B << BIT_SHIFT_LTECOEX_R_DATA_V1_8814B)
+#define BIT_CLEAR_LTECOEX_R_DATA_V1_8814B(x)                                   \
+	((x) & (~BITS_LTECOEX_R_DATA_V1_8814B))
+#define BIT_GET_LTECOEX_R_DATA_V1_8814B(x)                                     \
+	(((x) >> BIT_SHIFT_LTECOEX_R_DATA_V1_8814B) &                          \
+	 BIT_MASK_LTECOEX_R_DATA_V1_8814B)
+#define BIT_SET_LTECOEX_R_DATA_V1_8814B(x, v)                                  \
+	(BIT_CLEAR_LTECOEX_R_DATA_V1_8814B(x) | BIT_LTECOEX_R_DATA_V1_8814B(v))
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_PCIE_CFG_FORCE_LINK_L_8814B */
+#define BIT_PCIE_CFG_FORCE_EN_8814B BIT(7)
+
+/* 2 REG_PCIE_CFG_FORCE_LINK_H_8814B */
+#define BIT_PCIE_CFG_TRXACT_DIS_IDLE_TIMER_8814B BIT(6)
+
+#define BIT_SHIFT_PCIE_CFG_LINK_STATE_8814B 0
+#define BIT_MASK_PCIE_CFG_LINK_STATE_8814B 0x3f
+#define BIT_PCIE_CFG_LINK_STATE_8814B(x)                                       \
+	(((x) & BIT_MASK_PCIE_CFG_LINK_STATE_8814B)                            \
+	 << BIT_SHIFT_PCIE_CFG_LINK_STATE_8814B)
+#define BITS_PCIE_CFG_LINK_STATE_8814B                                         \
+	(BIT_MASK_PCIE_CFG_LINK_STATE_8814B                                    \
+	 << BIT_SHIFT_PCIE_CFG_LINK_STATE_8814B)
+#define BIT_CLEAR_PCIE_CFG_LINK_STATE_8814B(x)                                 \
+	((x) & (~BITS_PCIE_CFG_LINK_STATE_8814B))
+#define BIT_GET_PCIE_CFG_LINK_STATE_8814B(x)                                   \
+	(((x) >> BIT_SHIFT_PCIE_CFG_LINK_STATE_8814B) &                        \
+	 BIT_MASK_PCIE_CFG_LINK_STATE_8814B)
+#define BIT_SET_PCIE_CFG_LINK_STATE_8814B(x, v)                                \
+	(BIT_CLEAR_PCIE_CFG_LINK_STATE_8814B(x) |                              \
+	 BIT_PCIE_CFG_LINK_STATE_8814B(v))
+
+/* 2 REG_PCIE_CFG_DEFAULT_ACK_FREQUENCY_8814B */
+
+#define BIT_SHIFT_PCIE_CFG_DEFAULT_ACK_FREQUENCY_8814B 0
+#define BIT_MASK_PCIE_CFG_DEFAULT_ACK_FREQUENCY_8814B 0xff
+#define BIT_PCIE_CFG_DEFAULT_ACK_FREQUENCY_8814B(x)                            \
+	(((x) & BIT_MASK_PCIE_CFG_DEFAULT_ACK_FREQUENCY_8814B)                 \
+	 << BIT_SHIFT_PCIE_CFG_DEFAULT_ACK_FREQUENCY_8814B)
+#define BITS_PCIE_CFG_DEFAULT_ACK_FREQUENCY_8814B                              \
+	(BIT_MASK_PCIE_CFG_DEFAULT_ACK_FREQUENCY_8814B                         \
+	 << BIT_SHIFT_PCIE_CFG_DEFAULT_ACK_FREQUENCY_8814B)
+#define BIT_CLEAR_PCIE_CFG_DEFAULT_ACK_FREQUENCY_8814B(x)                      \
+	((x) & (~BITS_PCIE_CFG_DEFAULT_ACK_FREQUENCY_8814B))
+#define BIT_GET_PCIE_CFG_DEFAULT_ACK_FREQUENCY_8814B(x)                        \
+	(((x) >> BIT_SHIFT_PCIE_CFG_DEFAULT_ACK_FREQUENCY_8814B) &             \
+	 BIT_MASK_PCIE_CFG_DEFAULT_ACK_FREQUENCY_8814B)
+#define BIT_SET_PCIE_CFG_DEFAULT_ACK_FREQUENCY_8814B(x, v)                     \
+	(BIT_CLEAR_PCIE_CFG_DEFAULT_ACK_FREQUENCY_8814B(x) |                   \
+	 BIT_PCIE_CFG_DEFAULT_ACK_FREQUENCY_8814B(v))
+
+/* 2 REG_PCIE_CFG_CX_NFTS_8814B */
+
+#define BIT_SHIFT_PCIE_CFG_CX_NFTS_8814B 0
+#define BIT_MASK_PCIE_CFG_CX_NFTS_8814B 0xff
+#define BIT_PCIE_CFG_CX_NFTS_8814B(x)                                          \
+	(((x) & BIT_MASK_PCIE_CFG_CX_NFTS_8814B)                               \
+	 << BIT_SHIFT_PCIE_CFG_CX_NFTS_8814B)
+#define BITS_PCIE_CFG_CX_NFTS_8814B                                            \
+	(BIT_MASK_PCIE_CFG_CX_NFTS_8814B << BIT_SHIFT_PCIE_CFG_CX_NFTS_8814B)
+#define BIT_CLEAR_PCIE_CFG_CX_NFTS_8814B(x)                                    \
+	((x) & (~BITS_PCIE_CFG_CX_NFTS_8814B))
+#define BIT_GET_PCIE_CFG_CX_NFTS_8814B(x)                                      \
+	(((x) >> BIT_SHIFT_PCIE_CFG_CX_NFTS_8814B) &                           \
+	 BIT_MASK_PCIE_CFG_CX_NFTS_8814B)
+#define BIT_SET_PCIE_CFG_CX_NFTS_8814B(x, v)                                   \
+	(BIT_CLEAR_PCIE_CFG_CX_NFTS_8814B(x) | BIT_PCIE_CFG_CX_NFTS_8814B(v))
+
+/* 2 REG_PCIE_CFG_DEFAULT_ENTR_LATENCY_8814B */
+#define BIT_PCIE_CFG_REAL_EN_L0S_8814B BIT(7)
+#define BIT_PCIE_CFG_ENTER_ASPM_8814B BIT(6)
+
+#define BIT_SHIFT_PCIE_CFG_DEFAULT_L1_ENTR_LATENCY_8814B 3
+#define BIT_MASK_PCIE_CFG_DEFAULT_L1_ENTR_LATENCY_8814B 0x7
+#define BIT_PCIE_CFG_DEFAULT_L1_ENTR_LATENCY_8814B(x)                          \
+	(((x) & BIT_MASK_PCIE_CFG_DEFAULT_L1_ENTR_LATENCY_8814B)               \
+	 << BIT_SHIFT_PCIE_CFG_DEFAULT_L1_ENTR_LATENCY_8814B)
+#define BITS_PCIE_CFG_DEFAULT_L1_ENTR_LATENCY_8814B                            \
+	(BIT_MASK_PCIE_CFG_DEFAULT_L1_ENTR_LATENCY_8814B                       \
+	 << BIT_SHIFT_PCIE_CFG_DEFAULT_L1_ENTR_LATENCY_8814B)
+#define BIT_CLEAR_PCIE_CFG_DEFAULT_L1_ENTR_LATENCY_8814B(x)                    \
+	((x) & (~BITS_PCIE_CFG_DEFAULT_L1_ENTR_LATENCY_8814B))
+#define BIT_GET_PCIE_CFG_DEFAULT_L1_ENTR_LATENCY_8814B(x)                      \
+	(((x) >> BIT_SHIFT_PCIE_CFG_DEFAULT_L1_ENTR_LATENCY_8814B) &           \
+	 BIT_MASK_PCIE_CFG_DEFAULT_L1_ENTR_LATENCY_8814B)
+#define BIT_SET_PCIE_CFG_DEFAULT_L1_ENTR_LATENCY_8814B(x, v)                   \
+	(BIT_CLEAR_PCIE_CFG_DEFAULT_L1_ENTR_LATENCY_8814B(x) |                 \
+	 BIT_PCIE_CFG_DEFAULT_L1_ENTR_LATENCY_8814B(v))
+
+#define BIT_SHIFT_PCIE_CFG_DEFAULT_L0S_ENTR_LATENCY_8814B 0
+#define BIT_MASK_PCIE_CFG_DEFAULT_L0S_ENTR_LATENCY_8814B 0x7
+#define BIT_PCIE_CFG_DEFAULT_L0S_ENTR_LATENCY_8814B(x)                         \
+	(((x) & BIT_MASK_PCIE_CFG_DEFAULT_L0S_ENTR_LATENCY_8814B)              \
+	 << BIT_SHIFT_PCIE_CFG_DEFAULT_L0S_ENTR_LATENCY_8814B)
+#define BITS_PCIE_CFG_DEFAULT_L0S_ENTR_LATENCY_8814B                           \
+	(BIT_MASK_PCIE_CFG_DEFAULT_L0S_ENTR_LATENCY_8814B                      \
+	 << BIT_SHIFT_PCIE_CFG_DEFAULT_L0S_ENTR_LATENCY_8814B)
+#define BIT_CLEAR_PCIE_CFG_DEFAULT_L0S_ENTR_LATENCY_8814B(x)                   \
+	((x) & (~BITS_PCIE_CFG_DEFAULT_L0S_ENTR_LATENCY_8814B))
+#define BIT_GET_PCIE_CFG_DEFAULT_L0S_ENTR_LATENCY_8814B(x)                     \
+	(((x) >> BIT_SHIFT_PCIE_CFG_DEFAULT_L0S_ENTR_LATENCY_8814B) &          \
+	 BIT_MASK_PCIE_CFG_DEFAULT_L0S_ENTR_LATENCY_8814B)
+#define BIT_SET_PCIE_CFG_DEFAULT_L0S_ENTR_LATENCY_8814B(x, v)                  \
+	(BIT_CLEAR_PCIE_CFG_DEFAULT_L0S_ENTR_LATENCY_8814B(x) |                \
+	 BIT_PCIE_CFG_DEFAULT_L0S_ENTR_LATENCY_8814B(v))
+
+/* 2 REG_PCIE_CFG_L1_MISC_SEL_8814B */
+#define BIT_PCIE_CFG_L1_RIDLE_SEL_8814B BIT(6)
+#define BIT_PCIE_CFG_L1_TIMEOUT_SEL_8814B BIT(5)
+#define BIT_PCIE_CFG_L1_EIDLE_SEL_8814B BIT(4)
+
+#define BIT_SHIFT_PCIE_CFG_DEFAULT_LINK_RATE_8814B 0
+#define BIT_MASK_PCIE_CFG_DEFAULT_LINK_RATE_8814B 0xf
+#define BIT_PCIE_CFG_DEFAULT_LINK_RATE_8814B(x)                                \
+	(((x) & BIT_MASK_PCIE_CFG_DEFAULT_LINK_RATE_8814B)                     \
+	 << BIT_SHIFT_PCIE_CFG_DEFAULT_LINK_RATE_8814B)
+#define BITS_PCIE_CFG_DEFAULT_LINK_RATE_8814B                                  \
+	(BIT_MASK_PCIE_CFG_DEFAULT_LINK_RATE_8814B                             \
+	 << BIT_SHIFT_PCIE_CFG_DEFAULT_LINK_RATE_8814B)
+#define BIT_CLEAR_PCIE_CFG_DEFAULT_LINK_RATE_8814B(x)                          \
+	((x) & (~BITS_PCIE_CFG_DEFAULT_LINK_RATE_8814B))
+#define BIT_GET_PCIE_CFG_DEFAULT_LINK_RATE_8814B(x)                            \
+	(((x) >> BIT_SHIFT_PCIE_CFG_DEFAULT_LINK_RATE_8814B) &                 \
+	 BIT_MASK_PCIE_CFG_DEFAULT_LINK_RATE_8814B)
+#define BIT_SET_PCIE_CFG_DEFAULT_LINK_RATE_8814B(x, v)                         \
+	(BIT_CLEAR_PCIE_CFG_DEFAULT_LINK_RATE_8814B(x) |                       \
+	 BIT_PCIE_CFG_DEFAULT_LINK_RATE_8814B(v))
+
+/* 2 REG_PCIE_CFG_TIMER_CTRL_MAX_FUNC_NUM_OFF_8814B */
+#define BIT_PCIE_CFG_REAL_PTM_ENABLE_8814B BIT(6)
+#define BIT_PCIE_CFG_REAL_EN_L1SUB_8814B BIT(5)
+
+#define BIT_SHIFT_PCIE_CFG_MAX_FUNC_NUM_8814B 0
+#define BIT_MASK_PCIE_CFG_MAX_FUNC_NUM_8814B 0x7
+#define BIT_PCIE_CFG_MAX_FUNC_NUM_8814B(x)                                     \
+	(((x) & BIT_MASK_PCIE_CFG_MAX_FUNC_NUM_8814B)                          \
+	 << BIT_SHIFT_PCIE_CFG_MAX_FUNC_NUM_8814B)
+#define BITS_PCIE_CFG_MAX_FUNC_NUM_8814B                                       \
+	(BIT_MASK_PCIE_CFG_MAX_FUNC_NUM_8814B                                  \
+	 << BIT_SHIFT_PCIE_CFG_MAX_FUNC_NUM_8814B)
+#define BIT_CLEAR_PCIE_CFG_MAX_FUNC_NUM_8814B(x)                               \
+	((x) & (~BITS_PCIE_CFG_MAX_FUNC_NUM_8814B))
+#define BIT_GET_PCIE_CFG_MAX_FUNC_NUM_8814B(x)                                 \
+	(((x) >> BIT_SHIFT_PCIE_CFG_MAX_FUNC_NUM_8814B) &                      \
+	 BIT_MASK_PCIE_CFG_MAX_FUNC_NUM_8814B)
+#define BIT_SET_PCIE_CFG_MAX_FUNC_NUM_8814B(x, v)                              \
+	(BIT_CLEAR_PCIE_CFG_MAX_FUNC_NUM_8814B(x) |                            \
+	 BIT_PCIE_CFG_MAX_FUNC_NUM_8814B(v))
+
+/* 2 REG_PCIE_CFG_FORCE_CLKREQ_N_PAD_8814B */
+#define BIT_PCIE_CFG_REAL_EN_64BITS_8814B BIT(5)
+#define BIT_PCIE_CFG_REAL_EN_CLKREQ_8814B BIT(4)
+#define BIT_PCIE_CFG_REAL_EN_L1_8814B BIT(3)
+#define BIT_PCIE_CFG_WAKE_N_EN_8814B BIT(2)
+#define BIT_PCIE_CFG_BYPASS_LTR_OPTION_8814B BIT(1)
+#define BIT_PCIE_CFG_FORCE_CLKREQ_N_PAD_8814B BIT(0)
+
+/* 2 REG_PCIE_CFG_TIMER_MODIFIER_FOR_ACK_NAK_LATENCY_8814B */
+
+#define BIT_SHIFT_PCIE_CFG_TIMER_MOD_ACK_NAK_8814B 0
+#define BIT_MASK_PCIE_CFG_TIMER_MOD_ACK_NAK_8814B 0xff
+#define BIT_PCIE_CFG_TIMER_MOD_ACK_NAK_8814B(x)                                \
+	(((x) & BIT_MASK_PCIE_CFG_TIMER_MOD_ACK_NAK_8814B)                     \
+	 << BIT_SHIFT_PCIE_CFG_TIMER_MOD_ACK_NAK_8814B)
+#define BITS_PCIE_CFG_TIMER_MOD_ACK_NAK_8814B                                  \
+	(BIT_MASK_PCIE_CFG_TIMER_MOD_ACK_NAK_8814B                             \
+	 << BIT_SHIFT_PCIE_CFG_TIMER_MOD_ACK_NAK_8814B)
+#define BIT_CLEAR_PCIE_CFG_TIMER_MOD_ACK_NAK_8814B(x)                          \
+	((x) & (~BITS_PCIE_CFG_TIMER_MOD_ACK_NAK_8814B))
+#define BIT_GET_PCIE_CFG_TIMER_MOD_ACK_NAK_8814B(x)                            \
+	(((x) >> BIT_SHIFT_PCIE_CFG_TIMER_MOD_ACK_NAK_8814B) &                 \
+	 BIT_MASK_PCIE_CFG_TIMER_MOD_ACK_NAK_8814B)
+#define BIT_SET_PCIE_CFG_TIMER_MOD_ACK_NAK_8814B(x, v)                         \
+	(BIT_CLEAR_PCIE_CFG_TIMER_MOD_ACK_NAK_8814B(x) |                       \
+	 BIT_PCIE_CFG_TIMER_MOD_ACK_NAK_8814B(v))
+
+/* 2 REG_PCIE_CFG_TIMER_MODIFIER_FOR_FLOW_CONTROL_WATCHDOG_8814B */
+#define BIT_PCIE_CFG_BYPASS_L1_SUBSTATE_OPTION_8814B BIT(7)
+
+#define BIT_SHIFT_PCIE_CFG_FAST_LINK_SCALING_FACTOR_8814B 5
+#define BIT_MASK_PCIE_CFG_FAST_LINK_SCALING_FACTOR_8814B 0x3
+#define BIT_PCIE_CFG_FAST_LINK_SCALING_FACTOR_8814B(x)                         \
+	(((x) & BIT_MASK_PCIE_CFG_FAST_LINK_SCALING_FACTOR_8814B)              \
+	 << BIT_SHIFT_PCIE_CFG_FAST_LINK_SCALING_FACTOR_8814B)
+#define BITS_PCIE_CFG_FAST_LINK_SCALING_FACTOR_8814B                           \
+	(BIT_MASK_PCIE_CFG_FAST_LINK_SCALING_FACTOR_8814B                      \
+	 << BIT_SHIFT_PCIE_CFG_FAST_LINK_SCALING_FACTOR_8814B)
+#define BIT_CLEAR_PCIE_CFG_FAST_LINK_SCALING_FACTOR_8814B(x)                   \
+	((x) & (~BITS_PCIE_CFG_FAST_LINK_SCALING_FACTOR_8814B))
+#define BIT_GET_PCIE_CFG_FAST_LINK_SCALING_FACTOR_8814B(x)                     \
+	(((x) >> BIT_SHIFT_PCIE_CFG_FAST_LINK_SCALING_FACTOR_8814B) &          \
+	 BIT_MASK_PCIE_CFG_FAST_LINK_SCALING_FACTOR_8814B)
+#define BIT_SET_PCIE_CFG_FAST_LINK_SCALING_FACTOR_8814B(x, v)                  \
+	(BIT_CLEAR_PCIE_CFG_FAST_LINK_SCALING_FACTOR_8814B(x) |                \
+	 BIT_PCIE_CFG_FAST_LINK_SCALING_FACTOR_8814B(v))
+
+#define BIT_SHIFT_PCIE_CFG_UPDATE_FREQ_TIMER_8814B 0
+#define BIT_MASK_PCIE_CFG_UPDATE_FREQ_TIMER_8814B 0x1f
+#define BIT_PCIE_CFG_UPDATE_FREQ_TIMER_8814B(x)                                \
+	(((x) & BIT_MASK_PCIE_CFG_UPDATE_FREQ_TIMER_8814B)                     \
+	 << BIT_SHIFT_PCIE_CFG_UPDATE_FREQ_TIMER_8814B)
+#define BITS_PCIE_CFG_UPDATE_FREQ_TIMER_8814B                                  \
+	(BIT_MASK_PCIE_CFG_UPDATE_FREQ_TIMER_8814B                             \
+	 << BIT_SHIFT_PCIE_CFG_UPDATE_FREQ_TIMER_8814B)
+#define BIT_CLEAR_PCIE_CFG_UPDATE_FREQ_TIMER_8814B(x)                          \
+	((x) & (~BITS_PCIE_CFG_UPDATE_FREQ_TIMER_8814B))
+#define BIT_GET_PCIE_CFG_UPDATE_FREQ_TIMER_8814B(x)                            \
+	(((x) >> BIT_SHIFT_PCIE_CFG_UPDATE_FREQ_TIMER_8814B) &                 \
+	 BIT_MASK_PCIE_CFG_UPDATE_FREQ_TIMER_8814B)
+#define BIT_SET_PCIE_CFG_UPDATE_FREQ_TIMER_8814B(x, v)                         \
+	(BIT_CLEAR_PCIE_CFG_UPDATE_FREQ_TIMER_8814B(x) |                       \
+	 BIT_PCIE_CFG_UPDATE_FREQ_TIMER_8814B(v))
+
+/* 2 REG_PCIE_CFG_SKP_INTERVAL_VALUE_L_8814B */
+
+#define BIT_SHIFT_PCIE_CFG_SKP_INTERVAL_VALUE_L_8814B 0
+#define BIT_MASK_PCIE_CFG_SKP_INTERVAL_VALUE_L_8814B 0xff
+#define BIT_PCIE_CFG_SKP_INTERVAL_VALUE_L_8814B(x)                             \
+	(((x) & BIT_MASK_PCIE_CFG_SKP_INTERVAL_VALUE_L_8814B)                  \
+	 << BIT_SHIFT_PCIE_CFG_SKP_INTERVAL_VALUE_L_8814B)
+#define BITS_PCIE_CFG_SKP_INTERVAL_VALUE_L_8814B                               \
+	(BIT_MASK_PCIE_CFG_SKP_INTERVAL_VALUE_L_8814B                          \
+	 << BIT_SHIFT_PCIE_CFG_SKP_INTERVAL_VALUE_L_8814B)
+#define BIT_CLEAR_PCIE_CFG_SKP_INTERVAL_VALUE_L_8814B(x)                       \
+	((x) & (~BITS_PCIE_CFG_SKP_INTERVAL_VALUE_L_8814B))
+#define BIT_GET_PCIE_CFG_SKP_INTERVAL_VALUE_L_8814B(x)                         \
+	(((x) >> BIT_SHIFT_PCIE_CFG_SKP_INTERVAL_VALUE_L_8814B) &              \
+	 BIT_MASK_PCIE_CFG_SKP_INTERVAL_VALUE_L_8814B)
+#define BIT_SET_PCIE_CFG_SKP_INTERVAL_VALUE_L_8814B(x, v)                      \
+	(BIT_CLEAR_PCIE_CFG_SKP_INTERVAL_VALUE_L_8814B(x) |                    \
+	 BIT_PCIE_CFG_SKP_INTERVAL_VALUE_L_8814B(v))
+
+/* 2 REG_PCIE_CFG_SKP_INTERVAL_VALUE_H_8814B */
+#define BIT_PCIE_CFG_DISABLE_FC_WATCHDOG_TIMER_8814B BIT(7)
+
+#define BIT_SHIFT_PCIE_CFG_SKP_INTERVAL_VALUE_H_8814B 0
+#define BIT_MASK_PCIE_CFG_SKP_INTERVAL_VALUE_H_8814B 0x7
+#define BIT_PCIE_CFG_SKP_INTERVAL_VALUE_H_8814B(x)                             \
+	(((x) & BIT_MASK_PCIE_CFG_SKP_INTERVAL_VALUE_H_8814B)                  \
+	 << BIT_SHIFT_PCIE_CFG_SKP_INTERVAL_VALUE_H_8814B)
+#define BITS_PCIE_CFG_SKP_INTERVAL_VALUE_H_8814B                               \
+	(BIT_MASK_PCIE_CFG_SKP_INTERVAL_VALUE_H_8814B                          \
+	 << BIT_SHIFT_PCIE_CFG_SKP_INTERVAL_VALUE_H_8814B)
+#define BIT_CLEAR_PCIE_CFG_SKP_INTERVAL_VALUE_H_8814B(x)                       \
+	((x) & (~BITS_PCIE_CFG_SKP_INTERVAL_VALUE_H_8814B))
+#define BIT_GET_PCIE_CFG_SKP_INTERVAL_VALUE_H_8814B(x)                         \
+	(((x) >> BIT_SHIFT_PCIE_CFG_SKP_INTERVAL_VALUE_H_8814B) &              \
+	 BIT_MASK_PCIE_CFG_SKP_INTERVAL_VALUE_H_8814B)
+#define BIT_SET_PCIE_CFG_SKP_INTERVAL_VALUE_H_8814B(x, v)                      \
+	(BIT_CLEAR_PCIE_CFG_SKP_INTERVAL_VALUE_H_8814B(x) |                    \
+	 BIT_PCIE_CFG_SKP_INTERVAL_VALUE_H_8814B(v))
+
+/* 2 REG_PCIE_CFG_L1_UNIT_SEL_8814B */
+
+#define BIT_SHIFT_PCIE_CFG_L1_UNIT_SEL_8814B 0
+#define BIT_MASK_PCIE_CFG_L1_UNIT_SEL_8814B 0xff
+#define BIT_PCIE_CFG_L1_UNIT_SEL_8814B(x)                                      \
+	(((x) & BIT_MASK_PCIE_CFG_L1_UNIT_SEL_8814B)                           \
+	 << BIT_SHIFT_PCIE_CFG_L1_UNIT_SEL_8814B)
+#define BITS_PCIE_CFG_L1_UNIT_SEL_8814B                                        \
+	(BIT_MASK_PCIE_CFG_L1_UNIT_SEL_8814B                                   \
+	 << BIT_SHIFT_PCIE_CFG_L1_UNIT_SEL_8814B)
+#define BIT_CLEAR_PCIE_CFG_L1_UNIT_SEL_8814B(x)                                \
+	((x) & (~BITS_PCIE_CFG_L1_UNIT_SEL_8814B))
+#define BIT_GET_PCIE_CFG_L1_UNIT_SEL_8814B(x)                                  \
+	(((x) >> BIT_SHIFT_PCIE_CFG_L1_UNIT_SEL_8814B) &                       \
+	 BIT_MASK_PCIE_CFG_L1_UNIT_SEL_8814B)
+#define BIT_SET_PCIE_CFG_L1_UNIT_SEL_8814B(x, v)                               \
+	(BIT_CLEAR_PCIE_CFG_L1_UNIT_SEL_8814B(x) |                             \
+	 BIT_PCIE_CFG_L1_UNIT_SEL_8814B(v))
+
+/* 2 REG_PCIE_CFG_MIN_CLKREQ_SEL_8814B */
+
+#define BIT_SHIFT_PCIE_CFG_MIN_CLKREQ_SEL_8814B 0
+#define BIT_MASK_PCIE_CFG_MIN_CLKREQ_SEL_8814B 0xf
+#define BIT_PCIE_CFG_MIN_CLKREQ_SEL_8814B(x)                                   \
+	(((x) & BIT_MASK_PCIE_CFG_MIN_CLKREQ_SEL_8814B)                        \
+	 << BIT_SHIFT_PCIE_CFG_MIN_CLKREQ_SEL_8814B)
+#define BITS_PCIE_CFG_MIN_CLKREQ_SEL_8814B                                     \
+	(BIT_MASK_PCIE_CFG_MIN_CLKREQ_SEL_8814B                                \
+	 << BIT_SHIFT_PCIE_CFG_MIN_CLKREQ_SEL_8814B)
+#define BIT_CLEAR_PCIE_CFG_MIN_CLKREQ_SEL_8814B(x)                             \
+	((x) & (~BITS_PCIE_CFG_MIN_CLKREQ_SEL_8814B))
+#define BIT_GET_PCIE_CFG_MIN_CLKREQ_SEL_8814B(x)                               \
+	(((x) >> BIT_SHIFT_PCIE_CFG_MIN_CLKREQ_SEL_8814B) &                    \
+	 BIT_MASK_PCIE_CFG_MIN_CLKREQ_SEL_8814B)
+#define BIT_SET_PCIE_CFG_MIN_CLKREQ_SEL_8814B(x, v)                            \
+	(BIT_CLEAR_PCIE_CFG_MIN_CLKREQ_SEL_8814B(x) |                          \
+	 BIT_PCIE_CFG_MIN_CLKREQ_SEL_8814B(v))
+
+/* 2 REG_SDIO_TX_CTRL_8814B */
+
+#define BIT_SHIFT_SDIO_INT_TIMEOUT_8814B 16
+#define BIT_MASK_SDIO_INT_TIMEOUT_8814B 0xffff
+#define BIT_SDIO_INT_TIMEOUT_8814B(x)                                          \
+	(((x) & BIT_MASK_SDIO_INT_TIMEOUT_8814B)                               \
+	 << BIT_SHIFT_SDIO_INT_TIMEOUT_8814B)
+#define BITS_SDIO_INT_TIMEOUT_8814B                                            \
+	(BIT_MASK_SDIO_INT_TIMEOUT_8814B << BIT_SHIFT_SDIO_INT_TIMEOUT_8814B)
+#define BIT_CLEAR_SDIO_INT_TIMEOUT_8814B(x)                                    \
+	((x) & (~BITS_SDIO_INT_TIMEOUT_8814B))
+#define BIT_GET_SDIO_INT_TIMEOUT_8814B(x)                                      \
+	(((x) >> BIT_SHIFT_SDIO_INT_TIMEOUT_8814B) &                           \
+	 BIT_MASK_SDIO_INT_TIMEOUT_8814B)
+#define BIT_SET_SDIO_INT_TIMEOUT_8814B(x, v)                                   \
+	(BIT_CLEAR_SDIO_INT_TIMEOUT_8814B(x) | BIT_SDIO_INT_TIMEOUT_8814B(v))
+
+#define BIT_IO_ERR_STATUS_8814B BIT(15)
+#define BIT_REPLY_ERRCRC_IN_DATA_8814B BIT(9)
+#define BIT_EN_CMD53_OVERLAP_8814B BIT(8)
+#define BIT_REPLY_ERR_IN_R5_8814B BIT(7)
+#define BIT_R18A_EN_8814B BIT(6)
+#define BIT_SDIO_CMD_FORCE_VLD_8814B BIT(5)
+#define BIT_INIT_CMD_EN_8814B BIT(4)
+#define BIT_EN_RXDMA_MASK_INT_8814B BIT(2)
+#define BIT_EN_MASK_TIMER_8814B BIT(1)
+#define BIT_CMD_ERR_STOP_INT_EN_8814B BIT(0)
+
+/* 2 REG_SDIO_HIMR_8814B */
+#define BIT_SDIO_CRCERR_MSK_8814B BIT(31)
+#define BIT_SDIO_HSISR3_IND_MSK_8814B BIT(30)
+#define BIT_SDIO_HSISR2_IND_MSK_8814B BIT(29)
+#define BIT_SDIO_HEISR_IND_MSK_8814B BIT(28)
+#define BIT_SDIO_CTWEND_MSK_8814B BIT(27)
+#define BIT_SDIO_ATIMEND_E_MSK_8814B BIT(26)
+#define BIT_SDIIO_ATIMEND_MSK_8814B BIT(25)
+#define BIT_SDIO_OCPINT_MSK_8814B BIT(24)
+#define BIT_SDIO_PSTIMEOUT_MSK_8814B BIT(23)
+#define BIT_SDIO_GTINT4_MSK_8814B BIT(22)
+#define BIT_SDIO_GTINT3_MSK_8814B BIT(21)
+#define BIT_SDIO_HSISR_IND_MSK_8814B BIT(20)
+#define BIT_SDIO_CPWM2_MSK_8814B BIT(19)
+#define BIT_SDIO_CPWM1_MSK_8814B BIT(18)
+#define BIT_SDIO_C2HCMD_INT_MSK_8814B BIT(17)
+#define BIT_SDIO_BCNERLY_INT_MSK_8814B BIT(16)
+#define BIT_SDIO_TXBCNERR_MSK_8814B BIT(7)
+#define BIT_SDIO_TXBCNOK_MSK_8814B BIT(6)
+#define BIT_SDIO_RXFOVW_MSK_8814B BIT(5)
+#define BIT_SDIO_TXFOVW_MSK_8814B BIT(4)
+#define BIT_SDIO_RXERR_MSK_8814B BIT(3)
+#define BIT_SDIO_TXERR_MSK_8814B BIT(2)
+#define BIT_SDIO_AVAL_MSK_8814B BIT(1)
+#define BIT_RX_REQUEST_MSK_8814B BIT(0)
+
+/* 2 REG_SDIO_HISR_8814B */
+#define BIT_SDIO_CRCERR_8814B BIT(31)
+#define BIT_SDIO_HSISR3_IND_8814B BIT(30)
+#define BIT_SDIO_HSISR2_IND_8814B BIT(29)
+#define BIT_SDIO_HEISR_IND_8814B BIT(28)
+#define BIT_SDIO_CTWEND_8814B BIT(27)
+#define BIT_SDIO_ATIMEND_E_8814B BIT(26)
+#define BIT_SDIO_ATIMEND_8814B BIT(25)
+#define BIT_SDIO_OCPINT_8814B BIT(24)
+#define BIT_SDIO_PSTIMEOUT_8814B BIT(23)
+#define BIT_SDIO_GTINT4_8814B BIT(22)
+#define BIT_SDIO_GTINT3_8814B BIT(21)
+#define BIT_SDIO_HSISR_IND_8814B BIT(20)
+#define BIT_SDIO_CPWM2_8814B BIT(19)
+#define BIT_SDIO_CPWM1_8814B BIT(18)
+#define BIT_SDIO_C2HCMD_INT_8814B BIT(17)
+#define BIT_SDIO_BCNERLY_INT_8814B BIT(16)
+#define BIT_SDIO_TXBCNERR_8814B BIT(7)
+#define BIT_SDIO_TXBCNOK_8814B BIT(6)
+#define BIT_SDIO_RXFOVW_8814B BIT(5)
+#define BIT_SDIO_TXFOVW_8814B BIT(4)
+#define BIT_SDIO_RXERR_8814B BIT(3)
+#define BIT_SDIO_TXERR_8814B BIT(2)
+#define BIT_SDIO_AVAL_8814B BIT(1)
+#define BIT_RX_REQUEST_8814B BIT(0)
+
+/* 2 REG_SDIO_RX_REQ_LEN_8814B */
+
+#define BIT_SHIFT_RX_REQ_LEN_V1_8814B 0
+#define BIT_MASK_RX_REQ_LEN_V1_8814B 0x3ffff
+#define BIT_RX_REQ_LEN_V1_8814B(x)                                             \
+	(((x) & BIT_MASK_RX_REQ_LEN_V1_8814B) << BIT_SHIFT_RX_REQ_LEN_V1_8814B)
+#define BITS_RX_REQ_LEN_V1_8814B                                               \
+	(BIT_MASK_RX_REQ_LEN_V1_8814B << BIT_SHIFT_RX_REQ_LEN_V1_8814B)
+#define BIT_CLEAR_RX_REQ_LEN_V1_8814B(x) ((x) & (~BITS_RX_REQ_LEN_V1_8814B))
+#define BIT_GET_RX_REQ_LEN_V1_8814B(x)                                         \
+	(((x) >> BIT_SHIFT_RX_REQ_LEN_V1_8814B) & BIT_MASK_RX_REQ_LEN_V1_8814B)
+#define BIT_SET_RX_REQ_LEN_V1_8814B(x, v)                                      \
+	(BIT_CLEAR_RX_REQ_LEN_V1_8814B(x) | BIT_RX_REQ_LEN_V1_8814B(v))
+
+/* 2 REG_SDIO_FREE_TXPG_SEQ_V1_8814B */
+
+#define BIT_SHIFT_FREE_TXPG_SEQ_8814B 0
+#define BIT_MASK_FREE_TXPG_SEQ_8814B 0xff
+#define BIT_FREE_TXPG_SEQ_8814B(x)                                             \
+	(((x) & BIT_MASK_FREE_TXPG_SEQ_8814B) << BIT_SHIFT_FREE_TXPG_SEQ_8814B)
+#define BITS_FREE_TXPG_SEQ_8814B                                               \
+	(BIT_MASK_FREE_TXPG_SEQ_8814B << BIT_SHIFT_FREE_TXPG_SEQ_8814B)
+#define BIT_CLEAR_FREE_TXPG_SEQ_8814B(x) ((x) & (~BITS_FREE_TXPG_SEQ_8814B))
+#define BIT_GET_FREE_TXPG_SEQ_8814B(x)                                         \
+	(((x) >> BIT_SHIFT_FREE_TXPG_SEQ_8814B) & BIT_MASK_FREE_TXPG_SEQ_8814B)
+#define BIT_SET_FREE_TXPG_SEQ_8814B(x, v)                                      \
+	(BIT_CLEAR_FREE_TXPG_SEQ_8814B(x) | BIT_FREE_TXPG_SEQ_8814B(v))
+
+/* 2 REG_SDIO_FREE_TXPG_8814B */
+
+#define BIT_SHIFT_MID_FREEPG_V1_8814B 16
+#define BIT_MASK_MID_FREEPG_V1_8814B 0xfff
+#define BIT_MID_FREEPG_V1_8814B(x)                                             \
+	(((x) & BIT_MASK_MID_FREEPG_V1_8814B) << BIT_SHIFT_MID_FREEPG_V1_8814B)
+#define BITS_MID_FREEPG_V1_8814B                                               \
+	(BIT_MASK_MID_FREEPG_V1_8814B << BIT_SHIFT_MID_FREEPG_V1_8814B)
+#define BIT_CLEAR_MID_FREEPG_V1_8814B(x) ((x) & (~BITS_MID_FREEPG_V1_8814B))
+#define BIT_GET_MID_FREEPG_V1_8814B(x)                                         \
+	(((x) >> BIT_SHIFT_MID_FREEPG_V1_8814B) & BIT_MASK_MID_FREEPG_V1_8814B)
+#define BIT_SET_MID_FREEPG_V1_8814B(x, v)                                      \
+	(BIT_CLEAR_MID_FREEPG_V1_8814B(x) | BIT_MID_FREEPG_V1_8814B(v))
+
+#define BIT_SHIFT_HIQ_FREEPG_V1_8814B 0
+#define BIT_MASK_HIQ_FREEPG_V1_8814B 0xfff
+#define BIT_HIQ_FREEPG_V1_8814B(x)                                             \
+	(((x) & BIT_MASK_HIQ_FREEPG_V1_8814B) << BIT_SHIFT_HIQ_FREEPG_V1_8814B)
+#define BITS_HIQ_FREEPG_V1_8814B                                               \
+	(BIT_MASK_HIQ_FREEPG_V1_8814B << BIT_SHIFT_HIQ_FREEPG_V1_8814B)
+#define BIT_CLEAR_HIQ_FREEPG_V1_8814B(x) ((x) & (~BITS_HIQ_FREEPG_V1_8814B))
+#define BIT_GET_HIQ_FREEPG_V1_8814B(x)                                         \
+	(((x) >> BIT_SHIFT_HIQ_FREEPG_V1_8814B) & BIT_MASK_HIQ_FREEPG_V1_8814B)
+#define BIT_SET_HIQ_FREEPG_V1_8814B(x, v)                                      \
+	(BIT_CLEAR_HIQ_FREEPG_V1_8814B(x) | BIT_HIQ_FREEPG_V1_8814B(v))
+
+/* 2 REG_SDIO_FREE_TXPG2_8814B */
+
+#define BIT_SHIFT_PUB_FREEPG_V1_8814B 16
+#define BIT_MASK_PUB_FREEPG_V1_8814B 0xfff
+#define BIT_PUB_FREEPG_V1_8814B(x)                                             \
+	(((x) & BIT_MASK_PUB_FREEPG_V1_8814B) << BIT_SHIFT_PUB_FREEPG_V1_8814B)
+#define BITS_PUB_FREEPG_V1_8814B                                               \
+	(BIT_MASK_PUB_FREEPG_V1_8814B << BIT_SHIFT_PUB_FREEPG_V1_8814B)
+#define BIT_CLEAR_PUB_FREEPG_V1_8814B(x) ((x) & (~BITS_PUB_FREEPG_V1_8814B))
+#define BIT_GET_PUB_FREEPG_V1_8814B(x)                                         \
+	(((x) >> BIT_SHIFT_PUB_FREEPG_V1_8814B) & BIT_MASK_PUB_FREEPG_V1_8814B)
+#define BIT_SET_PUB_FREEPG_V1_8814B(x, v)                                      \
+	(BIT_CLEAR_PUB_FREEPG_V1_8814B(x) | BIT_PUB_FREEPG_V1_8814B(v))
+
+#define BIT_SHIFT_LOW_FREEPG_V1_8814B 0
+#define BIT_MASK_LOW_FREEPG_V1_8814B 0xfff
+#define BIT_LOW_FREEPG_V1_8814B(x)                                             \
+	(((x) & BIT_MASK_LOW_FREEPG_V1_8814B) << BIT_SHIFT_LOW_FREEPG_V1_8814B)
+#define BITS_LOW_FREEPG_V1_8814B                                               \
+	(BIT_MASK_LOW_FREEPG_V1_8814B << BIT_SHIFT_LOW_FREEPG_V1_8814B)
+#define BIT_CLEAR_LOW_FREEPG_V1_8814B(x) ((x) & (~BITS_LOW_FREEPG_V1_8814B))
+#define BIT_GET_LOW_FREEPG_V1_8814B(x)                                         \
+	(((x) >> BIT_SHIFT_LOW_FREEPG_V1_8814B) & BIT_MASK_LOW_FREEPG_V1_8814B)
+#define BIT_SET_LOW_FREEPG_V1_8814B(x, v)                                      \
+	(BIT_CLEAR_LOW_FREEPG_V1_8814B(x) | BIT_LOW_FREEPG_V1_8814B(v))
+
+/* 2 REG_SDIO_OQT_FREE_TXPG_V1_8814B */
+
+#define BIT_SHIFT_NOAC_OQT_FREEPG_V1_8814B 24
+#define BIT_MASK_NOAC_OQT_FREEPG_V1_8814B 0xff
+#define BIT_NOAC_OQT_FREEPG_V1_8814B(x)                                        \
+	(((x) & BIT_MASK_NOAC_OQT_FREEPG_V1_8814B)                             \
+	 << BIT_SHIFT_NOAC_OQT_FREEPG_V1_8814B)
+#define BITS_NOAC_OQT_FREEPG_V1_8814B                                          \
+	(BIT_MASK_NOAC_OQT_FREEPG_V1_8814B                                     \
+	 << BIT_SHIFT_NOAC_OQT_FREEPG_V1_8814B)
+#define BIT_CLEAR_NOAC_OQT_FREEPG_V1_8814B(x)                                  \
+	((x) & (~BITS_NOAC_OQT_FREEPG_V1_8814B))
+#define BIT_GET_NOAC_OQT_FREEPG_V1_8814B(x)                                    \
+	(((x) >> BIT_SHIFT_NOAC_OQT_FREEPG_V1_8814B) &                         \
+	 BIT_MASK_NOAC_OQT_FREEPG_V1_8814B)
+#define BIT_SET_NOAC_OQT_FREEPG_V1_8814B(x, v)                                 \
+	(BIT_CLEAR_NOAC_OQT_FREEPG_V1_8814B(x) |                               \
+	 BIT_NOAC_OQT_FREEPG_V1_8814B(v))
+
+#define BIT_SHIFT_AC_OQT_FREEPG_V1_8814B 16
+#define BIT_MASK_AC_OQT_FREEPG_V1_8814B 0xff
+#define BIT_AC_OQT_FREEPG_V1_8814B(x)                                          \
+	(((x) & BIT_MASK_AC_OQT_FREEPG_V1_8814B)                               \
+	 << BIT_SHIFT_AC_OQT_FREEPG_V1_8814B)
+#define BITS_AC_OQT_FREEPG_V1_8814B                                            \
+	(BIT_MASK_AC_OQT_FREEPG_V1_8814B << BIT_SHIFT_AC_OQT_FREEPG_V1_8814B)
+#define BIT_CLEAR_AC_OQT_FREEPG_V1_8814B(x)                                    \
+	((x) & (~BITS_AC_OQT_FREEPG_V1_8814B))
+#define BIT_GET_AC_OQT_FREEPG_V1_8814B(x)                                      \
+	(((x) >> BIT_SHIFT_AC_OQT_FREEPG_V1_8814B) &                           \
+	 BIT_MASK_AC_OQT_FREEPG_V1_8814B)
+#define BIT_SET_AC_OQT_FREEPG_V1_8814B(x, v)                                   \
+	(BIT_CLEAR_AC_OQT_FREEPG_V1_8814B(x) | BIT_AC_OQT_FREEPG_V1_8814B(v))
+
+#define BIT_SHIFT_EXQ_FREEPG_V1_8814B 0
+#define BIT_MASK_EXQ_FREEPG_V1_8814B 0xfff
+#define BIT_EXQ_FREEPG_V1_8814B(x)                                             \
+	(((x) & BIT_MASK_EXQ_FREEPG_V1_8814B) << BIT_SHIFT_EXQ_FREEPG_V1_8814B)
+#define BITS_EXQ_FREEPG_V1_8814B                                               \
+	(BIT_MASK_EXQ_FREEPG_V1_8814B << BIT_SHIFT_EXQ_FREEPG_V1_8814B)
+#define BIT_CLEAR_EXQ_FREEPG_V1_8814B(x) ((x) & (~BITS_EXQ_FREEPG_V1_8814B))
+#define BIT_GET_EXQ_FREEPG_V1_8814B(x)                                         \
+	(((x) >> BIT_SHIFT_EXQ_FREEPG_V1_8814B) & BIT_MASK_EXQ_FREEPG_V1_8814B)
+#define BIT_SET_EXQ_FREEPG_V1_8814B(x, v)                                      \
+	(BIT_CLEAR_EXQ_FREEPG_V1_8814B(x) | BIT_EXQ_FREEPG_V1_8814B(v))
+
+/* 2 REG_SDIO_HTSFR_INFO_8814B */
+
+#define BIT_SHIFT_HTSFR1_8814B 16
+#define BIT_MASK_HTSFR1_8814B 0xffff
+#define BIT_HTSFR1_8814B(x)                                                    \
+	(((x) & BIT_MASK_HTSFR1_8814B) << BIT_SHIFT_HTSFR1_8814B)
+#define BITS_HTSFR1_8814B (BIT_MASK_HTSFR1_8814B << BIT_SHIFT_HTSFR1_8814B)
+#define BIT_CLEAR_HTSFR1_8814B(x) ((x) & (~BITS_HTSFR1_8814B))
+#define BIT_GET_HTSFR1_8814B(x)                                                \
+	(((x) >> BIT_SHIFT_HTSFR1_8814B) & BIT_MASK_HTSFR1_8814B)
+#define BIT_SET_HTSFR1_8814B(x, v)                                             \
+	(BIT_CLEAR_HTSFR1_8814B(x) | BIT_HTSFR1_8814B(v))
+
+#define BIT_SHIFT_HTSFR0_8814B 0
+#define BIT_MASK_HTSFR0_8814B 0xffff
+#define BIT_HTSFR0_8814B(x)                                                    \
+	(((x) & BIT_MASK_HTSFR0_8814B) << BIT_SHIFT_HTSFR0_8814B)
+#define BITS_HTSFR0_8814B (BIT_MASK_HTSFR0_8814B << BIT_SHIFT_HTSFR0_8814B)
+#define BIT_CLEAR_HTSFR0_8814B(x) ((x) & (~BITS_HTSFR0_8814B))
+#define BIT_GET_HTSFR0_8814B(x)                                                \
+	(((x) >> BIT_SHIFT_HTSFR0_8814B) & BIT_MASK_HTSFR0_8814B)
+#define BIT_SET_HTSFR0_8814B(x, v)                                             \
+	(BIT_CLEAR_HTSFR0_8814B(x) | BIT_HTSFR0_8814B(v))
+
+/* 2 REG_SDIO_HCPWM1_V2_8814B */
+#define BIT_TOGGLE_8814B BIT(7)
+#define BIT_CUR_PS_8814B BIT(0)
+
+/* 2 REG_SDIO_HCPWM2_V2_8814B */
+
+/* 2 REG_SDIO_INDIRECT_REG_CFG_8814B */
+#define BIT_INDIRECT_REG_RDY_8814B BIT(20)
+#define BIT_INDIRECT_REG_R_8814B BIT(19)
+#define BIT_INDIRECT_REG_W_8814B BIT(18)
+
+#define BIT_SHIFT_INDIRECT_REG_SIZE_8814B 16
+#define BIT_MASK_INDIRECT_REG_SIZE_8814B 0x3
+#define BIT_INDIRECT_REG_SIZE_8814B(x)                                         \
+	(((x) & BIT_MASK_INDIRECT_REG_SIZE_8814B)                              \
+	 << BIT_SHIFT_INDIRECT_REG_SIZE_8814B)
+#define BITS_INDIRECT_REG_SIZE_8814B                                           \
+	(BIT_MASK_INDIRECT_REG_SIZE_8814B << BIT_SHIFT_INDIRECT_REG_SIZE_8814B)
+#define BIT_CLEAR_INDIRECT_REG_SIZE_8814B(x)                                   \
+	((x) & (~BITS_INDIRECT_REG_SIZE_8814B))
+#define BIT_GET_INDIRECT_REG_SIZE_8814B(x)                                     \
+	(((x) >> BIT_SHIFT_INDIRECT_REG_SIZE_8814B) &                          \
+	 BIT_MASK_INDIRECT_REG_SIZE_8814B)
+#define BIT_SET_INDIRECT_REG_SIZE_8814B(x, v)                                  \
+	(BIT_CLEAR_INDIRECT_REG_SIZE_8814B(x) | BIT_INDIRECT_REG_SIZE_8814B(v))
+
+#define BIT_SHIFT_INDIRECT_REG_ADDR_8814B 0
+#define BIT_MASK_INDIRECT_REG_ADDR_8814B 0xffff
+#define BIT_INDIRECT_REG_ADDR_8814B(x)                                         \
+	(((x) & BIT_MASK_INDIRECT_REG_ADDR_8814B)                              \
+	 << BIT_SHIFT_INDIRECT_REG_ADDR_8814B)
+#define BITS_INDIRECT_REG_ADDR_8814B                                           \
+	(BIT_MASK_INDIRECT_REG_ADDR_8814B << BIT_SHIFT_INDIRECT_REG_ADDR_8814B)
+#define BIT_CLEAR_INDIRECT_REG_ADDR_8814B(x)                                   \
+	((x) & (~BITS_INDIRECT_REG_ADDR_8814B))
+#define BIT_GET_INDIRECT_REG_ADDR_8814B(x)                                     \
+	(((x) >> BIT_SHIFT_INDIRECT_REG_ADDR_8814B) &                          \
+	 BIT_MASK_INDIRECT_REG_ADDR_8814B)
+#define BIT_SET_INDIRECT_REG_ADDR_8814B(x, v)                                  \
+	(BIT_CLEAR_INDIRECT_REG_ADDR_8814B(x) | BIT_INDIRECT_REG_ADDR_8814B(v))
+
+/* 2 REG_SDIO_INDIRECT_REG_DATA_8814B */
+
+#define BIT_SHIFT_INDIRECT_REG_DATA_8814B 0
+#define BIT_MASK_INDIRECT_REG_DATA_8814B 0xffffffffL
+#define BIT_INDIRECT_REG_DATA_8814B(x)                                         \
+	(((x) & BIT_MASK_INDIRECT_REG_DATA_8814B)                              \
+	 << BIT_SHIFT_INDIRECT_REG_DATA_8814B)
+#define BITS_INDIRECT_REG_DATA_8814B                                           \
+	(BIT_MASK_INDIRECT_REG_DATA_8814B << BIT_SHIFT_INDIRECT_REG_DATA_8814B)
+#define BIT_CLEAR_INDIRECT_REG_DATA_8814B(x)                                   \
+	((x) & (~BITS_INDIRECT_REG_DATA_8814B))
+#define BIT_GET_INDIRECT_REG_DATA_8814B(x)                                     \
+	(((x) >> BIT_SHIFT_INDIRECT_REG_DATA_8814B) &                          \
+	 BIT_MASK_INDIRECT_REG_DATA_8814B)
+#define BIT_SET_INDIRECT_REG_DATA_8814B(x, v)                                  \
+	(BIT_CLEAR_INDIRECT_REG_DATA_8814B(x) | BIT_INDIRECT_REG_DATA_8814B(v))
+
+/* 2 REG_SDIO_H2C_8814B */
+
+#define BIT_SHIFT_SDIO_H2C_MSG_8814B 0
+#define BIT_MASK_SDIO_H2C_MSG_8814B 0xffffffffL
+#define BIT_SDIO_H2C_MSG_8814B(x)                                              \
+	(((x) & BIT_MASK_SDIO_H2C_MSG_8814B) << BIT_SHIFT_SDIO_H2C_MSG_8814B)
+#define BITS_SDIO_H2C_MSG_8814B                                                \
+	(BIT_MASK_SDIO_H2C_MSG_8814B << BIT_SHIFT_SDIO_H2C_MSG_8814B)
+#define BIT_CLEAR_SDIO_H2C_MSG_8814B(x) ((x) & (~BITS_SDIO_H2C_MSG_8814B))
+#define BIT_GET_SDIO_H2C_MSG_8814B(x)                                          \
+	(((x) >> BIT_SHIFT_SDIO_H2C_MSG_8814B) & BIT_MASK_SDIO_H2C_MSG_8814B)
+#define BIT_SET_SDIO_H2C_MSG_8814B(x, v)                                       \
+	(BIT_CLEAR_SDIO_H2C_MSG_8814B(x) | BIT_SDIO_H2C_MSG_8814B(v))
+
+/* 2 REG_SDIO_C2H_8814B */
+
+#define BIT_SHIFT_SDIO_C2H_MSG_8814B 0
+#define BIT_MASK_SDIO_C2H_MSG_8814B 0xffffffffL
+#define BIT_SDIO_C2H_MSG_8814B(x)                                              \
+	(((x) & BIT_MASK_SDIO_C2H_MSG_8814B) << BIT_SHIFT_SDIO_C2H_MSG_8814B)
+#define BITS_SDIO_C2H_MSG_8814B                                                \
+	(BIT_MASK_SDIO_C2H_MSG_8814B << BIT_SHIFT_SDIO_C2H_MSG_8814B)
+#define BIT_CLEAR_SDIO_C2H_MSG_8814B(x) ((x) & (~BITS_SDIO_C2H_MSG_8814B))
+#define BIT_GET_SDIO_C2H_MSG_8814B(x)                                          \
+	(((x) >> BIT_SHIFT_SDIO_C2H_MSG_8814B) & BIT_MASK_SDIO_C2H_MSG_8814B)
+#define BIT_SET_SDIO_C2H_MSG_8814B(x, v)                                       \
+	(BIT_CLEAR_SDIO_C2H_MSG_8814B(x) | BIT_SDIO_C2H_MSG_8814B(v))
+
+/* 2 REG_SDIO_HRPWM1_8814B */
+#define BIT_TOGGLE_8814B BIT(7)
+#define BIT_ACK_8814B BIT(6)
+#define BIT_REQ_PS_8814B BIT(0)
+
+/* 2 REG_SDIO_HRPWM2_8814B */
+
+/* 2 REG_SDIO_HPS_CLKR_8814B */
+
+/* 2 REG_SDIO_BUS_CTRL_8814B */
+#define BIT_PAD_CLK_XHGE_EN_8814B BIT(3)
+#define BIT_INTER_CLK_EN_8814B BIT(2)
+#define BIT_EN_RPT_TXCRC_8814B BIT(1)
+#define BIT_DIS_RXDMA_STS_8814B BIT(0)
+
+/* 2 REG_SDIO_HSUS_CTRL_8814B */
+#define BIT_INTR_CTRL_8814B BIT(4)
+#define BIT_SDIO_VOLTAGE_8814B BIT(3)
+#define BIT_BYPASS_INIT_8814B BIT(2)
+#define BIT_HCI_RESUME_RDY_8814B BIT(1)
+#define BIT_HCI_SUS_REQ_8814B BIT(0)
+
+/* 2 REG_SDIO_RESPONSE_TIMER_8814B */
+
+#define BIT_SHIFT_CMDIN_2RESP_TIMER_8814B 0
+#define BIT_MASK_CMDIN_2RESP_TIMER_8814B 0xffff
+#define BIT_CMDIN_2RESP_TIMER_8814B(x)                                         \
+	(((x) & BIT_MASK_CMDIN_2RESP_TIMER_8814B)                              \
+	 << BIT_SHIFT_CMDIN_2RESP_TIMER_8814B)
+#define BITS_CMDIN_2RESP_TIMER_8814B                                           \
+	(BIT_MASK_CMDIN_2RESP_TIMER_8814B << BIT_SHIFT_CMDIN_2RESP_TIMER_8814B)
+#define BIT_CLEAR_CMDIN_2RESP_TIMER_8814B(x)                                   \
+	((x) & (~BITS_CMDIN_2RESP_TIMER_8814B))
+#define BIT_GET_CMDIN_2RESP_TIMER_8814B(x)                                     \
+	(((x) >> BIT_SHIFT_CMDIN_2RESP_TIMER_8814B) &                          \
+	 BIT_MASK_CMDIN_2RESP_TIMER_8814B)
+#define BIT_SET_CMDIN_2RESP_TIMER_8814B(x, v)                                  \
+	(BIT_CLEAR_CMDIN_2RESP_TIMER_8814B(x) | BIT_CMDIN_2RESP_TIMER_8814B(v))
+
+/* 2 REG_SDIO_CMD_CRC_8814B */
+
+#define BIT_SHIFT_SDIO_CMD_CRC_V1_8814B 0
+#define BIT_MASK_SDIO_CMD_CRC_V1_8814B 0xff
+#define BIT_SDIO_CMD_CRC_V1_8814B(x)                                           \
+	(((x) & BIT_MASK_SDIO_CMD_CRC_V1_8814B)                                \
+	 << BIT_SHIFT_SDIO_CMD_CRC_V1_8814B)
+#define BITS_SDIO_CMD_CRC_V1_8814B                                             \
+	(BIT_MASK_SDIO_CMD_CRC_V1_8814B << BIT_SHIFT_SDIO_CMD_CRC_V1_8814B)
+#define BIT_CLEAR_SDIO_CMD_CRC_V1_8814B(x) ((x) & (~BITS_SDIO_CMD_CRC_V1_8814B))
+#define BIT_GET_SDIO_CMD_CRC_V1_8814B(x)                                       \
+	(((x) >> BIT_SHIFT_SDIO_CMD_CRC_V1_8814B) &                            \
+	 BIT_MASK_SDIO_CMD_CRC_V1_8814B)
+#define BIT_SET_SDIO_CMD_CRC_V1_8814B(x, v)                                    \
+	(BIT_CLEAR_SDIO_CMD_CRC_V1_8814B(x) | BIT_SDIO_CMD_CRC_V1_8814B(v))
+
+/* 2 REG_SDIO_HSISR_8814B */
+#define BIT_DRV_WLAN_INT_CLR_8814B BIT(1)
+#define BIT_DRV_WLAN_INT_8814B BIT(0)
+
+/* 2 REG_SDIO_ERR_RPT_8814B */
+#define BIT_HR_FF_OVF_8814B BIT(6)
+#define BIT_HR_FF_UDN_8814B BIT(5)
+#define BIT_TXDMA_BUSY_ERR_8814B BIT(4)
+#define BIT_TXDMA_VLD_ERR_8814B BIT(3)
+#define BIT_QSEL_UNKNOWN_ERR_8814B BIT(2)
+#define BIT_QSEL_MIS_ERR_8814B BIT(1)
+#define BIT_SDIO_OVERRD_ERR_8814B BIT(0)
+
+/* 2 REG_SDIO_CMD_ERRCNT_8814B */
+
+#define BIT_SHIFT_CMD_CRC_ERR_CNT_8814B 0
+#define BIT_MASK_CMD_CRC_ERR_CNT_8814B 0xff
+#define BIT_CMD_CRC_ERR_CNT_8814B(x)                                           \
+	(((x) & BIT_MASK_CMD_CRC_ERR_CNT_8814B)                                \
+	 << BIT_SHIFT_CMD_CRC_ERR_CNT_8814B)
+#define BITS_CMD_CRC_ERR_CNT_8814B                                             \
+	(BIT_MASK_CMD_CRC_ERR_CNT_8814B << BIT_SHIFT_CMD_CRC_ERR_CNT_8814B)
+#define BIT_CLEAR_CMD_CRC_ERR_CNT_8814B(x) ((x) & (~BITS_CMD_CRC_ERR_CNT_8814B))
+#define BIT_GET_CMD_CRC_ERR_CNT_8814B(x)                                       \
+	(((x) >> BIT_SHIFT_CMD_CRC_ERR_CNT_8814B) &                            \
+	 BIT_MASK_CMD_CRC_ERR_CNT_8814B)
+#define BIT_SET_CMD_CRC_ERR_CNT_8814B(x, v)                                    \
+	(BIT_CLEAR_CMD_CRC_ERR_CNT_8814B(x) | BIT_CMD_CRC_ERR_CNT_8814B(v))
+
+/* 2 REG_SDIO_DATA_ERRCNT_8814B */
+
+#define BIT_SHIFT_DATA_CRC_ERR_CNT_8814B 0
+#define BIT_MASK_DATA_CRC_ERR_CNT_8814B 0xff
+#define BIT_DATA_CRC_ERR_CNT_8814B(x)                                          \
+	(((x) & BIT_MASK_DATA_CRC_ERR_CNT_8814B)                               \
+	 << BIT_SHIFT_DATA_CRC_ERR_CNT_8814B)
+#define BITS_DATA_CRC_ERR_CNT_8814B                                            \
+	(BIT_MASK_DATA_CRC_ERR_CNT_8814B << BIT_SHIFT_DATA_CRC_ERR_CNT_8814B)
+#define BIT_CLEAR_DATA_CRC_ERR_CNT_8814B(x)                                    \
+	((x) & (~BITS_DATA_CRC_ERR_CNT_8814B))
+#define BIT_GET_DATA_CRC_ERR_CNT_8814B(x)                                      \
+	(((x) >> BIT_SHIFT_DATA_CRC_ERR_CNT_8814B) &                           \
+	 BIT_MASK_DATA_CRC_ERR_CNT_8814B)
+#define BIT_SET_DATA_CRC_ERR_CNT_8814B(x, v)                                   \
+	(BIT_CLEAR_DATA_CRC_ERR_CNT_8814B(x) | BIT_DATA_CRC_ERR_CNT_8814B(v))
+
+/* 2 REG_SDIO_CMD_ERR_CONTENT_8814B */
+
+#define BIT_SHIFT_SDIO_CMD_ERR_CONTENT_8814B 0
+#define BIT_MASK_SDIO_CMD_ERR_CONTENT_8814B 0xffffffffffL
+#define BIT_SDIO_CMD_ERR_CONTENT_8814B(x)                                      \
+	(((x) & BIT_MASK_SDIO_CMD_ERR_CONTENT_8814B)                           \
+	 << BIT_SHIFT_SDIO_CMD_ERR_CONTENT_8814B)
+#define BITS_SDIO_CMD_ERR_CONTENT_8814B                                        \
+	(BIT_MASK_SDIO_CMD_ERR_CONTENT_8814B                                   \
+	 << BIT_SHIFT_SDIO_CMD_ERR_CONTENT_8814B)
+#define BIT_CLEAR_SDIO_CMD_ERR_CONTENT_8814B(x)                                \
+	((x) & (~BITS_SDIO_CMD_ERR_CONTENT_8814B))
+#define BIT_GET_SDIO_CMD_ERR_CONTENT_8814B(x)                                  \
+	(((x) >> BIT_SHIFT_SDIO_CMD_ERR_CONTENT_8814B) &                       \
+	 BIT_MASK_SDIO_CMD_ERR_CONTENT_8814B)
+#define BIT_SET_SDIO_CMD_ERR_CONTENT_8814B(x, v)                               \
+	(BIT_CLEAR_SDIO_CMD_ERR_CONTENT_8814B(x) |                             \
+	 BIT_SDIO_CMD_ERR_CONTENT_8814B(v))
+
+/* 2 REG_SDIO_CRC_ERR_IDX_8814B */
+#define BIT_D3_CRC_ERR_8814B BIT(4)
+#define BIT_D2_CRC_ERR_8814B BIT(3)
+#define BIT_D1_CRC_ERR_8814B BIT(2)
+#define BIT_D0_CRC_ERR_8814B BIT(1)
+#define BIT_CMD_CRC_ERR_8814B BIT(0)
+
+/* 2 REG_SDIO_DATA_CRC_8814B */
+
+#define BIT_SHIFT_SDIO_DATA_CRC_8814B 0
+#define BIT_MASK_SDIO_DATA_CRC_8814B 0xffff
+#define BIT_SDIO_DATA_CRC_8814B(x)                                             \
+	(((x) & BIT_MASK_SDIO_DATA_CRC_8814B) << BIT_SHIFT_SDIO_DATA_CRC_8814B)
+#define BITS_SDIO_DATA_CRC_8814B                                               \
+	(BIT_MASK_SDIO_DATA_CRC_8814B << BIT_SHIFT_SDIO_DATA_CRC_8814B)
+#define BIT_CLEAR_SDIO_DATA_CRC_8814B(x) ((x) & (~BITS_SDIO_DATA_CRC_8814B))
+#define BIT_GET_SDIO_DATA_CRC_8814B(x)                                         \
+	(((x) >> BIT_SHIFT_SDIO_DATA_CRC_8814B) & BIT_MASK_SDIO_DATA_CRC_8814B)
+#define BIT_SET_SDIO_DATA_CRC_8814B(x, v)                                      \
+	(BIT_CLEAR_SDIO_DATA_CRC_8814B(x) | BIT_SDIO_DATA_CRC_8814B(v))
+
+/* 2 REG_SDIO_DATA_REPLY_TIME_8814B */
+
+#define BIT_SHIFT_SDIO_DATA_REPLY_TIME_8814B 0
+#define BIT_MASK_SDIO_DATA_REPLY_TIME_8814B 0x7
+#define BIT_SDIO_DATA_REPLY_TIME_8814B(x)                                      \
+	(((x) & BIT_MASK_SDIO_DATA_REPLY_TIME_8814B)                           \
+	 << BIT_SHIFT_SDIO_DATA_REPLY_TIME_8814B)
+#define BITS_SDIO_DATA_REPLY_TIME_8814B                                        \
+	(BIT_MASK_SDIO_DATA_REPLY_TIME_8814B                                   \
+	 << BIT_SHIFT_SDIO_DATA_REPLY_TIME_8814B)
+#define BIT_CLEAR_SDIO_DATA_REPLY_TIME_8814B(x)                                \
+	((x) & (~BITS_SDIO_DATA_REPLY_TIME_8814B))
+#define BIT_GET_SDIO_DATA_REPLY_TIME_8814B(x)                                  \
+	(((x) >> BIT_SHIFT_SDIO_DATA_REPLY_TIME_8814B) &                       \
+	 BIT_MASK_SDIO_DATA_REPLY_TIME_8814B)
+#define BIT_SET_SDIO_DATA_REPLY_TIME_8814B(x, v)                               \
+	(BIT_CLEAR_SDIO_DATA_REPLY_TIME_8814B(x) |                             \
+	 BIT_SDIO_DATA_REPLY_TIME_8814B(v))
+
+#endif
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/halmac/halmac_bit_8821c.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/halmac/halmac_bit_8821c.h
--- linux-5.6.3/3rdparty/rtl8821ce/hal/halmac/halmac_bit_8821c.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/halmac/halmac_bit_8821c.h	2020-04-10 16:35:06.804659507 +0300
@@ -0,0 +1,19483 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ ******************************************************************************/
+
+#ifndef __INC_HALMAC_BIT_8821C_H
+#define __INC_HALMAC_BIT_8821C_H
+
+#define CPU_OPT_WIDTH 0x1F
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_SYS_ISO_CTRL_8821C */
+#define BIT_PWC_EV12V_8821C BIT(15)
+#define BIT_PWC_EV25V_8821C BIT(14)
+#define BIT_PA33V_EN_8821C BIT(13)
+#define BIT_PA12V_EN_8821C BIT(12)
+#define BIT_UA33V_EN_8821C BIT(11)
+#define BIT_UA12V_EN_8821C BIT(10)
+#define BIT_ISO_RFDIO_8821C BIT(9)
+#define BIT_ISO_EB2CORE_8821C BIT(8)
+#define BIT_ISO_DIOE_8821C BIT(7)
+#define BIT_ISO_WLPON2PP_8821C BIT(6)
+#define BIT_ISO_IP2MAC_WA2PP_8821C BIT(5)
+#define BIT_ISO_PD2CORE_8821C BIT(4)
+#define BIT_ISO_PA2PCIE_8821C BIT(3)
+#define BIT_ISO_UD2CORE_8821C BIT(2)
+#define BIT_ISO_UA2USB_8821C BIT(1)
+#define BIT_ISO_WD2PP_8821C BIT(0)
+
+/* 2 REG_SYS_FUNC_EN_8821C */
+#define BIT_FEN_MREGEN_8821C BIT(15)
+#define BIT_FEN_HWPDN_8821C BIT(14)
+#define BIT_EN_25_1_8821C BIT(13)
+#define BIT_FEN_ELDR_8821C BIT(12)
+#define BIT_FEN_DCORE_8821C BIT(11)
+#define BIT_FEN_CPUEN_8821C BIT(10)
+#define BIT_FEN_DIOE_8821C BIT(9)
+#define BIT_FEN_PCIED_8821C BIT(8)
+#define BIT_FEN_PPLL_8821C BIT(7)
+#define BIT_FEN_PCIEA_8821C BIT(6)
+#define BIT_FEN_DIO_PCIE_8821C BIT(5)
+#define BIT_FEN_USBD_8821C BIT(4)
+#define BIT_FEN_UPLL_8821C BIT(3)
+#define BIT_FEN_USBA_8821C BIT(2)
+#define BIT_FEN_BB_GLB_RSTN_8821C BIT(1)
+#define BIT_FEN_BBRSTB_8821C BIT(0)
+
+/* 2 REG_SYS_PW_CTRL_8821C */
+#define BIT_SOP_EABM_8821C BIT(31)
+#define BIT_SOP_ACKF_8821C BIT(30)
+#define BIT_SOP_ERCK_8821C BIT(29)
+#define BIT_SOP_ESWR_8821C BIT(28)
+#define BIT_SOP_PWMM_8821C BIT(27)
+#define BIT_SOP_EECK_8821C BIT(26)
+#define BIT_SOP_EXTL_8821C BIT(24)
+#define BIT_SYM_OP_RING_12M_8821C BIT(22)
+#define BIT_ROP_SWPR_8821C BIT(21)
+#define BIT_DIS_HW_LPLDM_8821C BIT(20)
+#define BIT_OPT_SWRST_WLMCU_8821C BIT(19)
+#define BIT_RDY_SYSPWR_8821C BIT(17)
+#define BIT_EN_WLON_8821C BIT(16)
+#define BIT_APDM_HPDN_8821C BIT(15)
+#define BIT_AFSM_PCIE_SUS_EN_8821C BIT(12)
+#define BIT_AFSM_WLSUS_EN_8821C BIT(11)
+#define BIT_APFM_SWLPS_8821C BIT(10)
+#define BIT_APFM_OFFMAC_8821C BIT(9)
+#define BIT_APFN_ONMAC_8821C BIT(8)
+#define BIT_CHIP_PDN_EN_8821C BIT(7)
+#define BIT_RDY_MACDIS_8821C BIT(6)
+#define BIT_RING_CLK_12M_EN_8821C BIT(4)
+#define BIT_PFM_WOWL_8821C BIT(3)
+#define BIT_PFM_LDKP_8821C BIT(2)
+#define BIT_WL_HCI_ALD_8821C BIT(1)
+#define BIT_PFM_LDALL_8821C BIT(0)
+
+/* 2 REG_SYS_CLK_CTRL_8821C */
+#define BIT_LDO_DUMMY_8821C BIT(15)
+#define BIT_CPU_CLK_EN_8821C BIT(14)
+#define BIT_SYMREG_CLK_EN_8821C BIT(13)
+#define BIT_HCI_CLK_EN_8821C BIT(12)
+#define BIT_MAC_CLK_EN_8821C BIT(11)
+#define BIT_SEC_CLK_EN_8821C BIT(10)
+#define BIT_PHY_SSC_RSTB_8821C BIT(9)
+#define BIT_EXT_32K_EN_8821C BIT(8)
+#define BIT_WL_CLK_TEST_8821C BIT(7)
+#define BIT_OP_SPS_PWM_EN_8821C BIT(6)
+#define BIT_LOADER_CLK_EN_8821C BIT(5)
+#define BIT_MACSLP_8821C BIT(4)
+#define BIT_WAKEPAD_EN_8821C BIT(3)
+#define BIT_ROMD16V_EN_8821C BIT(2)
+#define BIT_CKANA12M_EN_8821C BIT(1)
+#define BIT_CNTD16V_EN_8821C BIT(0)
+
+/* 2 REG_SYS_EEPROM_CTRL_8821C */
+
+#define BIT_SHIFT_VPDIDX_8821C 8
+#define BIT_MASK_VPDIDX_8821C 0xff
+#define BIT_VPDIDX_8821C(x)                                                    \
+	(((x) & BIT_MASK_VPDIDX_8821C) << BIT_SHIFT_VPDIDX_8821C)
+#define BITS_VPDIDX_8821C (BIT_MASK_VPDIDX_8821C << BIT_SHIFT_VPDIDX_8821C)
+#define BIT_CLEAR_VPDIDX_8821C(x) ((x) & (~BITS_VPDIDX_8821C))
+#define BIT_GET_VPDIDX_8821C(x)                                                \
+	(((x) >> BIT_SHIFT_VPDIDX_8821C) & BIT_MASK_VPDIDX_8821C)
+#define BIT_SET_VPDIDX_8821C(x, v)                                             \
+	(BIT_CLEAR_VPDIDX_8821C(x) | BIT_VPDIDX_8821C(v))
+
+#define BIT_SHIFT_EEM1_0_8821C 6
+#define BIT_MASK_EEM1_0_8821C 0x3
+#define BIT_EEM1_0_8821C(x)                                                    \
+	(((x) & BIT_MASK_EEM1_0_8821C) << BIT_SHIFT_EEM1_0_8821C)
+#define BITS_EEM1_0_8821C (BIT_MASK_EEM1_0_8821C << BIT_SHIFT_EEM1_0_8821C)
+#define BIT_CLEAR_EEM1_0_8821C(x) ((x) & (~BITS_EEM1_0_8821C))
+#define BIT_GET_EEM1_0_8821C(x)                                                \
+	(((x) >> BIT_SHIFT_EEM1_0_8821C) & BIT_MASK_EEM1_0_8821C)
+#define BIT_SET_EEM1_0_8821C(x, v)                                             \
+	(BIT_CLEAR_EEM1_0_8821C(x) | BIT_EEM1_0_8821C(v))
+
+#define BIT_AUTOLOAD_SUS_8821C BIT(5)
+#define BIT_EERPOMSEL_8821C BIT(4)
+#define BIT_EECS_V1_8821C BIT(3)
+#define BIT_EESK_V1_8821C BIT(2)
+#define BIT_EEDI_V1_8821C BIT(1)
+#define BIT_EEDO_V1_8821C BIT(0)
+
+/* 2 REG_EE_VPD_8821C */
+
+#define BIT_SHIFT_VPD_DATA_8821C 0
+#define BIT_MASK_VPD_DATA_8821C 0xffffffffL
+#define BIT_VPD_DATA_8821C(x)                                                  \
+	(((x) & BIT_MASK_VPD_DATA_8821C) << BIT_SHIFT_VPD_DATA_8821C)
+#define BITS_VPD_DATA_8821C                                                    \
+	(BIT_MASK_VPD_DATA_8821C << BIT_SHIFT_VPD_DATA_8821C)
+#define BIT_CLEAR_VPD_DATA_8821C(x) ((x) & (~BITS_VPD_DATA_8821C))
+#define BIT_GET_VPD_DATA_8821C(x)                                              \
+	(((x) >> BIT_SHIFT_VPD_DATA_8821C) & BIT_MASK_VPD_DATA_8821C)
+#define BIT_SET_VPD_DATA_8821C(x, v)                                           \
+	(BIT_CLEAR_VPD_DATA_8821C(x) | BIT_VPD_DATA_8821C(v))
+
+/* 2 REG_SYS_SWR_CTRL1_8821C */
+#define BIT_C2_L_BIT0_8821C BIT(31)
+
+#define BIT_SHIFT_C1_L_8821C 29
+#define BIT_MASK_C1_L_8821C 0x3
+#define BIT_C1_L_8821C(x) (((x) & BIT_MASK_C1_L_8821C) << BIT_SHIFT_C1_L_8821C)
+#define BITS_C1_L_8821C (BIT_MASK_C1_L_8821C << BIT_SHIFT_C1_L_8821C)
+#define BIT_CLEAR_C1_L_8821C(x) ((x) & (~BITS_C1_L_8821C))
+#define BIT_GET_C1_L_8821C(x)                                                  \
+	(((x) >> BIT_SHIFT_C1_L_8821C) & BIT_MASK_C1_L_8821C)
+#define BIT_SET_C1_L_8821C(x, v) (BIT_CLEAR_C1_L_8821C(x) | BIT_C1_L_8821C(v))
+
+#define BIT_SHIFT_REG_FREQ_L_8821C 25
+#define BIT_MASK_REG_FREQ_L_8821C 0x7
+#define BIT_REG_FREQ_L_8821C(x)                                                \
+	(((x) & BIT_MASK_REG_FREQ_L_8821C) << BIT_SHIFT_REG_FREQ_L_8821C)
+#define BITS_REG_FREQ_L_8821C                                                  \
+	(BIT_MASK_REG_FREQ_L_8821C << BIT_SHIFT_REG_FREQ_L_8821C)
+#define BIT_CLEAR_REG_FREQ_L_8821C(x) ((x) & (~BITS_REG_FREQ_L_8821C))
+#define BIT_GET_REG_FREQ_L_8821C(x)                                            \
+	(((x) >> BIT_SHIFT_REG_FREQ_L_8821C) & BIT_MASK_REG_FREQ_L_8821C)
+#define BIT_SET_REG_FREQ_L_8821C(x, v)                                         \
+	(BIT_CLEAR_REG_FREQ_L_8821C(x) | BIT_REG_FREQ_L_8821C(v))
+
+#define BIT_REG_EN_DUTY_8821C BIT(24)
+
+#define BIT_SHIFT_REG_MODE_8821C 22
+#define BIT_MASK_REG_MODE_8821C 0x3
+#define BIT_REG_MODE_8821C(x)                                                  \
+	(((x) & BIT_MASK_REG_MODE_8821C) << BIT_SHIFT_REG_MODE_8821C)
+#define BITS_REG_MODE_8821C                                                    \
+	(BIT_MASK_REG_MODE_8821C << BIT_SHIFT_REG_MODE_8821C)
+#define BIT_CLEAR_REG_MODE_8821C(x) ((x) & (~BITS_REG_MODE_8821C))
+#define BIT_GET_REG_MODE_8821C(x)                                              \
+	(((x) >> BIT_SHIFT_REG_MODE_8821C) & BIT_MASK_REG_MODE_8821C)
+#define BIT_SET_REG_MODE_8821C(x, v)                                           \
+	(BIT_CLEAR_REG_MODE_8821C(x) | BIT_REG_MODE_8821C(v))
+
+#define BIT_REG_EN_SP_8821C BIT(21)
+#define BIT_REG_AUTO_L_8821C BIT(20)
+#define BIT_SW18_SELD_BIT0_8821C BIT(19)
+#define BIT_SW18_POWOCP_8821C BIT(18)
+
+#define BIT_SHIFT_OCP_L1_8821C 15
+#define BIT_MASK_OCP_L1_8821C 0x7
+#define BIT_OCP_L1_8821C(x)                                                    \
+	(((x) & BIT_MASK_OCP_L1_8821C) << BIT_SHIFT_OCP_L1_8821C)
+#define BITS_OCP_L1_8821C (BIT_MASK_OCP_L1_8821C << BIT_SHIFT_OCP_L1_8821C)
+#define BIT_CLEAR_OCP_L1_8821C(x) ((x) & (~BITS_OCP_L1_8821C))
+#define BIT_GET_OCP_L1_8821C(x)                                                \
+	(((x) >> BIT_SHIFT_OCP_L1_8821C) & BIT_MASK_OCP_L1_8821C)
+#define BIT_SET_OCP_L1_8821C(x, v)                                             \
+	(BIT_CLEAR_OCP_L1_8821C(x) | BIT_OCP_L1_8821C(v))
+
+#define BIT_SHIFT_CF_L_8821C 13
+#define BIT_MASK_CF_L_8821C 0x3
+#define BIT_CF_L_8821C(x) (((x) & BIT_MASK_CF_L_8821C) << BIT_SHIFT_CF_L_8821C)
+#define BITS_CF_L_8821C (BIT_MASK_CF_L_8821C << BIT_SHIFT_CF_L_8821C)
+#define BIT_CLEAR_CF_L_8821C(x) ((x) & (~BITS_CF_L_8821C))
+#define BIT_GET_CF_L_8821C(x)                                                  \
+	(((x) >> BIT_SHIFT_CF_L_8821C) & BIT_MASK_CF_L_8821C)
+#define BIT_SET_CF_L_8821C(x, v) (BIT_CLEAR_CF_L_8821C(x) | BIT_CF_L_8821C(v))
+
+#define BIT_SW18_FPWM_8821C BIT(11)
+#define BIT_SW18_SWEN_8821C BIT(9)
+#define BIT_SW18_LDEN_8821C BIT(8)
+#define BIT_MAC_ID_EN_8821C BIT(7)
+#define BIT_AFE_BGEN_8821C BIT(0)
+
+/* 2 REG_SYS_SWR_CTRL2_8821C */
+#define BIT_POW_ZCD_L_8821C BIT(31)
+#define BIT_AUTOZCD_L_8821C BIT(30)
+
+#define BIT_SHIFT_REG_DELAY_8821C 28
+#define BIT_MASK_REG_DELAY_8821C 0x3
+#define BIT_REG_DELAY_8821C(x)                                                 \
+	(((x) & BIT_MASK_REG_DELAY_8821C) << BIT_SHIFT_REG_DELAY_8821C)
+#define BITS_REG_DELAY_8821C                                                   \
+	(BIT_MASK_REG_DELAY_8821C << BIT_SHIFT_REG_DELAY_8821C)
+#define BIT_CLEAR_REG_DELAY_8821C(x) ((x) & (~BITS_REG_DELAY_8821C))
+#define BIT_GET_REG_DELAY_8821C(x)                                             \
+	(((x) >> BIT_SHIFT_REG_DELAY_8821C) & BIT_MASK_REG_DELAY_8821C)
+#define BIT_SET_REG_DELAY_8821C(x, v)                                          \
+	(BIT_CLEAR_REG_DELAY_8821C(x) | BIT_REG_DELAY_8821C(v))
+
+#define BIT_SHIFT_V15ADJ_L1_V1_8821C 24
+#define BIT_MASK_V15ADJ_L1_V1_8821C 0x7
+#define BIT_V15ADJ_L1_V1_8821C(x)                                              \
+	(((x) & BIT_MASK_V15ADJ_L1_V1_8821C) << BIT_SHIFT_V15ADJ_L1_V1_8821C)
+#define BITS_V15ADJ_L1_V1_8821C                                                \
+	(BIT_MASK_V15ADJ_L1_V1_8821C << BIT_SHIFT_V15ADJ_L1_V1_8821C)
+#define BIT_CLEAR_V15ADJ_L1_V1_8821C(x) ((x) & (~BITS_V15ADJ_L1_V1_8821C))
+#define BIT_GET_V15ADJ_L1_V1_8821C(x)                                          \
+	(((x) >> BIT_SHIFT_V15ADJ_L1_V1_8821C) & BIT_MASK_V15ADJ_L1_V1_8821C)
+#define BIT_SET_V15ADJ_L1_V1_8821C(x, v)                                       \
+	(BIT_CLEAR_V15ADJ_L1_V1_8821C(x) | BIT_V15ADJ_L1_V1_8821C(v))
+
+#define BIT_SHIFT_VOL_L1_V1_8821C 20
+#define BIT_MASK_VOL_L1_V1_8821C 0xf
+#define BIT_VOL_L1_V1_8821C(x)                                                 \
+	(((x) & BIT_MASK_VOL_L1_V1_8821C) << BIT_SHIFT_VOL_L1_V1_8821C)
+#define BITS_VOL_L1_V1_8821C                                                   \
+	(BIT_MASK_VOL_L1_V1_8821C << BIT_SHIFT_VOL_L1_V1_8821C)
+#define BIT_CLEAR_VOL_L1_V1_8821C(x) ((x) & (~BITS_VOL_L1_V1_8821C))
+#define BIT_GET_VOL_L1_V1_8821C(x)                                             \
+	(((x) >> BIT_SHIFT_VOL_L1_V1_8821C) & BIT_MASK_VOL_L1_V1_8821C)
+#define BIT_SET_VOL_L1_V1_8821C(x, v)                                          \
+	(BIT_CLEAR_VOL_L1_V1_8821C(x) | BIT_VOL_L1_V1_8821C(v))
+
+#define BIT_SHIFT_IN_L1_V1_8821C 17
+#define BIT_MASK_IN_L1_V1_8821C 0x7
+#define BIT_IN_L1_V1_8821C(x)                                                  \
+	(((x) & BIT_MASK_IN_L1_V1_8821C) << BIT_SHIFT_IN_L1_V1_8821C)
+#define BITS_IN_L1_V1_8821C                                                    \
+	(BIT_MASK_IN_L1_V1_8821C << BIT_SHIFT_IN_L1_V1_8821C)
+#define BIT_CLEAR_IN_L1_V1_8821C(x) ((x) & (~BITS_IN_L1_V1_8821C))
+#define BIT_GET_IN_L1_V1_8821C(x)                                              \
+	(((x) >> BIT_SHIFT_IN_L1_V1_8821C) & BIT_MASK_IN_L1_V1_8821C)
+#define BIT_SET_IN_L1_V1_8821C(x, v)                                           \
+	(BIT_CLEAR_IN_L1_V1_8821C(x) | BIT_IN_L1_V1_8821C(v))
+
+#define BIT_SHIFT_TBOX_L1_8821C 15
+#define BIT_MASK_TBOX_L1_8821C 0x3
+#define BIT_TBOX_L1_8821C(x)                                                   \
+	(((x) & BIT_MASK_TBOX_L1_8821C) << BIT_SHIFT_TBOX_L1_8821C)
+#define BITS_TBOX_L1_8821C (BIT_MASK_TBOX_L1_8821C << BIT_SHIFT_TBOX_L1_8821C)
+#define BIT_CLEAR_TBOX_L1_8821C(x) ((x) & (~BITS_TBOX_L1_8821C))
+#define BIT_GET_TBOX_L1_8821C(x)                                               \
+	(((x) >> BIT_SHIFT_TBOX_L1_8821C) & BIT_MASK_TBOX_L1_8821C)
+#define BIT_SET_TBOX_L1_8821C(x, v)                                            \
+	(BIT_CLEAR_TBOX_L1_8821C(x) | BIT_TBOX_L1_8821C(v))
+
+#define BIT_SW18_SEL_8821C BIT(13)
+
+/* 2 REG_NOT_VALID_8821C */
+#define BIT_SW18_SD_8821C BIT(10)
+
+#define BIT_SHIFT_R3_L_8821C 7
+#define BIT_MASK_R3_L_8821C 0x3
+#define BIT_R3_L_8821C(x) (((x) & BIT_MASK_R3_L_8821C) << BIT_SHIFT_R3_L_8821C)
+#define BITS_R3_L_8821C (BIT_MASK_R3_L_8821C << BIT_SHIFT_R3_L_8821C)
+#define BIT_CLEAR_R3_L_8821C(x) ((x) & (~BITS_R3_L_8821C))
+#define BIT_GET_R3_L_8821C(x)                                                  \
+	(((x) >> BIT_SHIFT_R3_L_8821C) & BIT_MASK_R3_L_8821C)
+#define BIT_SET_R3_L_8821C(x, v) (BIT_CLEAR_R3_L_8821C(x) | BIT_R3_L_8821C(v))
+
+#define BIT_SHIFT_SW18_R2_8821C 5
+#define BIT_MASK_SW18_R2_8821C 0x3
+#define BIT_SW18_R2_8821C(x)                                                   \
+	(((x) & BIT_MASK_SW18_R2_8821C) << BIT_SHIFT_SW18_R2_8821C)
+#define BITS_SW18_R2_8821C (BIT_MASK_SW18_R2_8821C << BIT_SHIFT_SW18_R2_8821C)
+#define BIT_CLEAR_SW18_R2_8821C(x) ((x) & (~BITS_SW18_R2_8821C))
+#define BIT_GET_SW18_R2_8821C(x)                                               \
+	(((x) >> BIT_SHIFT_SW18_R2_8821C) & BIT_MASK_SW18_R2_8821C)
+#define BIT_SET_SW18_R2_8821C(x, v)                                            \
+	(BIT_CLEAR_SW18_R2_8821C(x) | BIT_SW18_R2_8821C(v))
+
+#define BIT_SHIFT_SW18_R1_8821C 3
+#define BIT_MASK_SW18_R1_8821C 0x3
+#define BIT_SW18_R1_8821C(x)                                                   \
+	(((x) & BIT_MASK_SW18_R1_8821C) << BIT_SHIFT_SW18_R1_8821C)
+#define BITS_SW18_R1_8821C (BIT_MASK_SW18_R1_8821C << BIT_SHIFT_SW18_R1_8821C)
+#define BIT_CLEAR_SW18_R1_8821C(x) ((x) & (~BITS_SW18_R1_8821C))
+#define BIT_GET_SW18_R1_8821C(x)                                               \
+	(((x) >> BIT_SHIFT_SW18_R1_8821C) & BIT_MASK_SW18_R1_8821C)
+#define BIT_SET_SW18_R1_8821C(x, v)                                            \
+	(BIT_CLEAR_SW18_R1_8821C(x) | BIT_SW18_R1_8821C(v))
+
+#define BIT_SHIFT_C3_L_C3_8821C 1
+#define BIT_MASK_C3_L_C3_8821C 0x3
+#define BIT_C3_L_C3_8821C(x)                                                   \
+	(((x) & BIT_MASK_C3_L_C3_8821C) << BIT_SHIFT_C3_L_C3_8821C)
+#define BITS_C3_L_C3_8821C (BIT_MASK_C3_L_C3_8821C << BIT_SHIFT_C3_L_C3_8821C)
+#define BIT_CLEAR_C3_L_C3_8821C(x) ((x) & (~BITS_C3_L_C3_8821C))
+#define BIT_GET_C3_L_C3_8821C(x)                                               \
+	(((x) >> BIT_SHIFT_C3_L_C3_8821C) & BIT_MASK_C3_L_C3_8821C)
+#define BIT_SET_C3_L_C3_8821C(x, v)                                            \
+	(BIT_CLEAR_C3_L_C3_8821C(x) | BIT_C3_L_C3_8821C(v))
+
+#define BIT_C2_L_BIT1_8821C BIT(0)
+
+/* 2 REG_SYS_SWR_CTRL3_8821C */
+#define BIT_SPS18_OCP_DIS_8821C BIT(31)
+
+#define BIT_SHIFT_SPS18_OCP_TH_8821C 16
+#define BIT_MASK_SPS18_OCP_TH_8821C 0x7fff
+#define BIT_SPS18_OCP_TH_8821C(x)                                              \
+	(((x) & BIT_MASK_SPS18_OCP_TH_8821C) << BIT_SHIFT_SPS18_OCP_TH_8821C)
+#define BITS_SPS18_OCP_TH_8821C                                                \
+	(BIT_MASK_SPS18_OCP_TH_8821C << BIT_SHIFT_SPS18_OCP_TH_8821C)
+#define BIT_CLEAR_SPS18_OCP_TH_8821C(x) ((x) & (~BITS_SPS18_OCP_TH_8821C))
+#define BIT_GET_SPS18_OCP_TH_8821C(x)                                          \
+	(((x) >> BIT_SHIFT_SPS18_OCP_TH_8821C) & BIT_MASK_SPS18_OCP_TH_8821C)
+#define BIT_SET_SPS18_OCP_TH_8821C(x, v)                                       \
+	(BIT_CLEAR_SPS18_OCP_TH_8821C(x) | BIT_SPS18_OCP_TH_8821C(v))
+
+#define BIT_SHIFT_OCP_WINDOW_8821C 0
+#define BIT_MASK_OCP_WINDOW_8821C 0xffff
+#define BIT_OCP_WINDOW_8821C(x)                                                \
+	(((x) & BIT_MASK_OCP_WINDOW_8821C) << BIT_SHIFT_OCP_WINDOW_8821C)
+#define BITS_OCP_WINDOW_8821C                                                  \
+	(BIT_MASK_OCP_WINDOW_8821C << BIT_SHIFT_OCP_WINDOW_8821C)
+#define BIT_CLEAR_OCP_WINDOW_8821C(x) ((x) & (~BITS_OCP_WINDOW_8821C))
+#define BIT_GET_OCP_WINDOW_8821C(x)                                            \
+	(((x) >> BIT_SHIFT_OCP_WINDOW_8821C) & BIT_MASK_OCP_WINDOW_8821C)
+#define BIT_SET_OCP_WINDOW_8821C(x, v)                                         \
+	(BIT_CLEAR_OCP_WINDOW_8821C(x) | BIT_OCP_WINDOW_8821C(v))
+
+/* 2 REG_RSV_CTRL_8821C */
+#define BIT_HREG_DBG_8821C BIT(23)
+#define BIT_WLMCUIOIF_8821C BIT(8)
+#define BIT_LOCK_ALL_EN_8821C BIT(7)
+#define BIT_R_DIS_PRST_8821C BIT(6)
+#define BIT_WLOCK_1C_B6_8821C BIT(5)
+#define BIT_WLOCK_40_8821C BIT(4)
+#define BIT_WLOCK_08_8821C BIT(3)
+#define BIT_WLOCK_04_8821C BIT(2)
+#define BIT_WLOCK_00_8821C BIT(1)
+#define BIT_WLOCK_ALL_8821C BIT(0)
+
+/* 2 REG_RF_CTRL_8821C */
+#define BIT_RF_SDMRSTB_8821C BIT(2)
+#define BIT_RF_RSTB_8821C BIT(1)
+#define BIT_RF_EN_8821C BIT(0)
+
+/* 2 REG_AFE_LDO_CTRL_8821C */
+
+#define BIT_SHIFT_LPLDH12_RSV_8821C 29
+#define BIT_MASK_LPLDH12_RSV_8821C 0x7
+#define BIT_LPLDH12_RSV_8821C(x)                                               \
+	(((x) & BIT_MASK_LPLDH12_RSV_8821C) << BIT_SHIFT_LPLDH12_RSV_8821C)
+#define BITS_LPLDH12_RSV_8821C                                                 \
+	(BIT_MASK_LPLDH12_RSV_8821C << BIT_SHIFT_LPLDH12_RSV_8821C)
+#define BIT_CLEAR_LPLDH12_RSV_8821C(x) ((x) & (~BITS_LPLDH12_RSV_8821C))
+#define BIT_GET_LPLDH12_RSV_8821C(x)                                           \
+	(((x) >> BIT_SHIFT_LPLDH12_RSV_8821C) & BIT_MASK_LPLDH12_RSV_8821C)
+#define BIT_SET_LPLDH12_RSV_8821C(x, v)                                        \
+	(BIT_CLEAR_LPLDH12_RSV_8821C(x) | BIT_LPLDH12_RSV_8821C(v))
+
+#define BIT_LPLDH12_SLP_8821C BIT(28)
+
+#define BIT_SHIFT_LPLDH12_VADJ_8821C 24
+#define BIT_MASK_LPLDH12_VADJ_8821C 0xf
+#define BIT_LPLDH12_VADJ_8821C(x)                                              \
+	(((x) & BIT_MASK_LPLDH12_VADJ_8821C) << BIT_SHIFT_LPLDH12_VADJ_8821C)
+#define BITS_LPLDH12_VADJ_8821C                                                \
+	(BIT_MASK_LPLDH12_VADJ_8821C << BIT_SHIFT_LPLDH12_VADJ_8821C)
+#define BIT_CLEAR_LPLDH12_VADJ_8821C(x) ((x) & (~BITS_LPLDH12_VADJ_8821C))
+#define BIT_GET_LPLDH12_VADJ_8821C(x)                                          \
+	(((x) >> BIT_SHIFT_LPLDH12_VADJ_8821C) & BIT_MASK_LPLDH12_VADJ_8821C)
+#define BIT_SET_LPLDH12_VADJ_8821C(x, v)                                       \
+	(BIT_CLEAR_LPLDH12_VADJ_8821C(x) | BIT_LPLDH12_VADJ_8821C(v))
+
+#define BIT_PCIE_CALIB_EN_8821C BIT(17)
+#define BIT_LDH12_EN_8821C BIT(16)
+#define BIT_WLBBOFF_BIG_PWC_EN_8821C BIT(14)
+#define BIT_WLBBOFF_SMALL_PWC_EN_8821C BIT(13)
+#define BIT_WLMACOFF_BIG_PWC_EN_8821C BIT(12)
+#define BIT_WLPON_PWC_EN_8821C BIT(11)
+#define BIT_POW_REGU_P1_8821C BIT(10)
+#define BIT_LDOV12W_EN_8821C BIT(8)
+#define BIT_EX_XTAL_DRV_DIGI_8821C BIT(7)
+#define BIT_EX_XTAL_DRV_USB_8821C BIT(6)
+#define BIT_EX_XTAL_DRV_AFE_8821C BIT(5)
+#define BIT_EX_XTAL_DRV_RF2_8821C BIT(4)
+#define BIT_EX_XTAL_DRV_RF1_8821C BIT(3)
+#define BIT_POW_REGU_P0_8821C BIT(2)
+
+/* 2 REG_NOT_VALID_8821C */
+#define BIT_POW_PLL_LDO_8821C BIT(0)
+
+/* 2 REG_AFE_CTRL1_8821C */
+#define BIT_AGPIO_GPE_8821C BIT(31)
+
+#define BIT_SHIFT_XTAL_CAP_XI_8821C 25
+#define BIT_MASK_XTAL_CAP_XI_8821C 0x3f
+#define BIT_XTAL_CAP_XI_8821C(x)                                               \
+	(((x) & BIT_MASK_XTAL_CAP_XI_8821C) << BIT_SHIFT_XTAL_CAP_XI_8821C)
+#define BITS_XTAL_CAP_XI_8821C                                                 \
+	(BIT_MASK_XTAL_CAP_XI_8821C << BIT_SHIFT_XTAL_CAP_XI_8821C)
+#define BIT_CLEAR_XTAL_CAP_XI_8821C(x) ((x) & (~BITS_XTAL_CAP_XI_8821C))
+#define BIT_GET_XTAL_CAP_XI_8821C(x)                                           \
+	(((x) >> BIT_SHIFT_XTAL_CAP_XI_8821C) & BIT_MASK_XTAL_CAP_XI_8821C)
+#define BIT_SET_XTAL_CAP_XI_8821C(x, v)                                        \
+	(BIT_CLEAR_XTAL_CAP_XI_8821C(x) | BIT_XTAL_CAP_XI_8821C(v))
+
+#define BIT_SHIFT_XTAL_DRV_DIGI_8821C 23
+#define BIT_MASK_XTAL_DRV_DIGI_8821C 0x3
+#define BIT_XTAL_DRV_DIGI_8821C(x)                                             \
+	(((x) & BIT_MASK_XTAL_DRV_DIGI_8821C) << BIT_SHIFT_XTAL_DRV_DIGI_8821C)
+#define BITS_XTAL_DRV_DIGI_8821C                                               \
+	(BIT_MASK_XTAL_DRV_DIGI_8821C << BIT_SHIFT_XTAL_DRV_DIGI_8821C)
+#define BIT_CLEAR_XTAL_DRV_DIGI_8821C(x) ((x) & (~BITS_XTAL_DRV_DIGI_8821C))
+#define BIT_GET_XTAL_DRV_DIGI_8821C(x)                                         \
+	(((x) >> BIT_SHIFT_XTAL_DRV_DIGI_8821C) & BIT_MASK_XTAL_DRV_DIGI_8821C)
+#define BIT_SET_XTAL_DRV_DIGI_8821C(x, v)                                      \
+	(BIT_CLEAR_XTAL_DRV_DIGI_8821C(x) | BIT_XTAL_DRV_DIGI_8821C(v))
+
+#define BIT_XTAL_DRV_USB_BIT1_8821C BIT(22)
+
+#define BIT_SHIFT_MAC_CLK_SEL_8821C 20
+#define BIT_MASK_MAC_CLK_SEL_8821C 0x3
+#define BIT_MAC_CLK_SEL_8821C(x)                                               \
+	(((x) & BIT_MASK_MAC_CLK_SEL_8821C) << BIT_SHIFT_MAC_CLK_SEL_8821C)
+#define BITS_MAC_CLK_SEL_8821C                                                 \
+	(BIT_MASK_MAC_CLK_SEL_8821C << BIT_SHIFT_MAC_CLK_SEL_8821C)
+#define BIT_CLEAR_MAC_CLK_SEL_8821C(x) ((x) & (~BITS_MAC_CLK_SEL_8821C))
+#define BIT_GET_MAC_CLK_SEL_8821C(x)                                           \
+	(((x) >> BIT_SHIFT_MAC_CLK_SEL_8821C) & BIT_MASK_MAC_CLK_SEL_8821C)
+#define BIT_SET_MAC_CLK_SEL_8821C(x, v)                                        \
+	(BIT_CLEAR_MAC_CLK_SEL_8821C(x) | BIT_MAC_CLK_SEL_8821C(v))
+
+#define BIT_XTAL_DRV_USB_BIT0_8821C BIT(19)
+
+#define BIT_SHIFT_XTAL_DRV_AFE_8821C 17
+#define BIT_MASK_XTAL_DRV_AFE_8821C 0x3
+#define BIT_XTAL_DRV_AFE_8821C(x)                                              \
+	(((x) & BIT_MASK_XTAL_DRV_AFE_8821C) << BIT_SHIFT_XTAL_DRV_AFE_8821C)
+#define BITS_XTAL_DRV_AFE_8821C                                                \
+	(BIT_MASK_XTAL_DRV_AFE_8821C << BIT_SHIFT_XTAL_DRV_AFE_8821C)
+#define BIT_CLEAR_XTAL_DRV_AFE_8821C(x) ((x) & (~BITS_XTAL_DRV_AFE_8821C))
+#define BIT_GET_XTAL_DRV_AFE_8821C(x)                                          \
+	(((x) >> BIT_SHIFT_XTAL_DRV_AFE_8821C) & BIT_MASK_XTAL_DRV_AFE_8821C)
+#define BIT_SET_XTAL_DRV_AFE_8821C(x, v)                                       \
+	(BIT_CLEAR_XTAL_DRV_AFE_8821C(x) | BIT_XTAL_DRV_AFE_8821C(v))
+
+#define BIT_SHIFT_XTAL_DRV_RF2_8821C 15
+#define BIT_MASK_XTAL_DRV_RF2_8821C 0x3
+#define BIT_XTAL_DRV_RF2_8821C(x)                                              \
+	(((x) & BIT_MASK_XTAL_DRV_RF2_8821C) << BIT_SHIFT_XTAL_DRV_RF2_8821C)
+#define BITS_XTAL_DRV_RF2_8821C                                                \
+	(BIT_MASK_XTAL_DRV_RF2_8821C << BIT_SHIFT_XTAL_DRV_RF2_8821C)
+#define BIT_CLEAR_XTAL_DRV_RF2_8821C(x) ((x) & (~BITS_XTAL_DRV_RF2_8821C))
+#define BIT_GET_XTAL_DRV_RF2_8821C(x)                                          \
+	(((x) >> BIT_SHIFT_XTAL_DRV_RF2_8821C) & BIT_MASK_XTAL_DRV_RF2_8821C)
+#define BIT_SET_XTAL_DRV_RF2_8821C(x, v)                                       \
+	(BIT_CLEAR_XTAL_DRV_RF2_8821C(x) | BIT_XTAL_DRV_RF2_8821C(v))
+
+#define BIT_SHIFT_XTAL_DRV_RF1_8821C 13
+#define BIT_MASK_XTAL_DRV_RF1_8821C 0x3
+#define BIT_XTAL_DRV_RF1_8821C(x)                                              \
+	(((x) & BIT_MASK_XTAL_DRV_RF1_8821C) << BIT_SHIFT_XTAL_DRV_RF1_8821C)
+#define BITS_XTAL_DRV_RF1_8821C                                                \
+	(BIT_MASK_XTAL_DRV_RF1_8821C << BIT_SHIFT_XTAL_DRV_RF1_8821C)
+#define BIT_CLEAR_XTAL_DRV_RF1_8821C(x) ((x) & (~BITS_XTAL_DRV_RF1_8821C))
+#define BIT_GET_XTAL_DRV_RF1_8821C(x)                                          \
+	(((x) >> BIT_SHIFT_XTAL_DRV_RF1_8821C) & BIT_MASK_XTAL_DRV_RF1_8821C)
+#define BIT_SET_XTAL_DRV_RF1_8821C(x, v)                                       \
+	(BIT_CLEAR_XTAL_DRV_RF1_8821C(x) | BIT_XTAL_DRV_RF1_8821C(v))
+
+#define BIT_XTAL_DELAY_DIGI_8821C BIT(12)
+#define BIT_XTAL_DELAY_USB_8821C BIT(11)
+#define BIT_XTAL_DELAY_AFE_8821C BIT(10)
+
+#define BIT_SHIFT_XTAL_LDO_VREF_8821C 7
+#define BIT_MASK_XTAL_LDO_VREF_8821C 0x7
+#define BIT_XTAL_LDO_VREF_8821C(x)                                             \
+	(((x) & BIT_MASK_XTAL_LDO_VREF_8821C) << BIT_SHIFT_XTAL_LDO_VREF_8821C)
+#define BITS_XTAL_LDO_VREF_8821C                                               \
+	(BIT_MASK_XTAL_LDO_VREF_8821C << BIT_SHIFT_XTAL_LDO_VREF_8821C)
+#define BIT_CLEAR_XTAL_LDO_VREF_8821C(x) ((x) & (~BITS_XTAL_LDO_VREF_8821C))
+#define BIT_GET_XTAL_LDO_VREF_8821C(x)                                         \
+	(((x) >> BIT_SHIFT_XTAL_LDO_VREF_8821C) & BIT_MASK_XTAL_LDO_VREF_8821C)
+#define BIT_SET_XTAL_LDO_VREF_8821C(x, v)                                      \
+	(BIT_CLEAR_XTAL_LDO_VREF_8821C(x) | BIT_XTAL_LDO_VREF_8821C(v))
+
+#define BIT_XTAL_XQSEL_RF_8821C BIT(6)
+#define BIT_XTAL_XQSEL_8821C BIT(5)
+
+#define BIT_SHIFT_XTAL_GMN_V2_8821C 3
+#define BIT_MASK_XTAL_GMN_V2_8821C 0x3
+#define BIT_XTAL_GMN_V2_8821C(x)                                               \
+	(((x) & BIT_MASK_XTAL_GMN_V2_8821C) << BIT_SHIFT_XTAL_GMN_V2_8821C)
+#define BITS_XTAL_GMN_V2_8821C                                                 \
+	(BIT_MASK_XTAL_GMN_V2_8821C << BIT_SHIFT_XTAL_GMN_V2_8821C)
+#define BIT_CLEAR_XTAL_GMN_V2_8821C(x) ((x) & (~BITS_XTAL_GMN_V2_8821C))
+#define BIT_GET_XTAL_GMN_V2_8821C(x)                                           \
+	(((x) >> BIT_SHIFT_XTAL_GMN_V2_8821C) & BIT_MASK_XTAL_GMN_V2_8821C)
+#define BIT_SET_XTAL_GMN_V2_8821C(x, v)                                        \
+	(BIT_CLEAR_XTAL_GMN_V2_8821C(x) | BIT_XTAL_GMN_V2_8821C(v))
+
+#define BIT_SHIFT_XTAL_GMP_V2_8821C 1
+#define BIT_MASK_XTAL_GMP_V2_8821C 0x3
+#define BIT_XTAL_GMP_V2_8821C(x)                                               \
+	(((x) & BIT_MASK_XTAL_GMP_V2_8821C) << BIT_SHIFT_XTAL_GMP_V2_8821C)
+#define BITS_XTAL_GMP_V2_8821C                                                 \
+	(BIT_MASK_XTAL_GMP_V2_8821C << BIT_SHIFT_XTAL_GMP_V2_8821C)
+#define BIT_CLEAR_XTAL_GMP_V2_8821C(x) ((x) & (~BITS_XTAL_GMP_V2_8821C))
+#define BIT_GET_XTAL_GMP_V2_8821C(x)                                           \
+	(((x) >> BIT_SHIFT_XTAL_GMP_V2_8821C) & BIT_MASK_XTAL_GMP_V2_8821C)
+#define BIT_SET_XTAL_GMP_V2_8821C(x, v)                                        \
+	(BIT_CLEAR_XTAL_GMP_V2_8821C(x) | BIT_XTAL_GMP_V2_8821C(v))
+
+#define BIT_XTAL_EN_8821C BIT(0)
+
+/* 2 REG_AFE_CTRL2_8821C */
+
+#define BIT_SHIFT_REG_C3_V4_8821C 30
+#define BIT_MASK_REG_C3_V4_8821C 0x3
+#define BIT_REG_C3_V4_8821C(x)                                                 \
+	(((x) & BIT_MASK_REG_C3_V4_8821C) << BIT_SHIFT_REG_C3_V4_8821C)
+#define BITS_REG_C3_V4_8821C                                                   \
+	(BIT_MASK_REG_C3_V4_8821C << BIT_SHIFT_REG_C3_V4_8821C)
+#define BIT_CLEAR_REG_C3_V4_8821C(x) ((x) & (~BITS_REG_C3_V4_8821C))
+#define BIT_GET_REG_C3_V4_8821C(x)                                             \
+	(((x) >> BIT_SHIFT_REG_C3_V4_8821C) & BIT_MASK_REG_C3_V4_8821C)
+#define BIT_SET_REG_C3_V4_8821C(x, v)                                          \
+	(BIT_CLEAR_REG_C3_V4_8821C(x) | BIT_REG_C3_V4_8821C(v))
+
+#define BIT_REG_CP_BIT1_8821C BIT(29)
+
+#define BIT_SHIFT_REG_RS_V4_8821C 26
+#define BIT_MASK_REG_RS_V4_8821C 0x7
+#define BIT_REG_RS_V4_8821C(x)                                                 \
+	(((x) & BIT_MASK_REG_RS_V4_8821C) << BIT_SHIFT_REG_RS_V4_8821C)
+#define BITS_REG_RS_V4_8821C                                                   \
+	(BIT_MASK_REG_RS_V4_8821C << BIT_SHIFT_REG_RS_V4_8821C)
+#define BIT_CLEAR_REG_RS_V4_8821C(x) ((x) & (~BITS_REG_RS_V4_8821C))
+#define BIT_GET_REG_RS_V4_8821C(x)                                             \
+	(((x) >> BIT_SHIFT_REG_RS_V4_8821C) & BIT_MASK_REG_RS_V4_8821C)
+#define BIT_SET_REG_RS_V4_8821C(x, v)                                          \
+	(BIT_CLEAR_REG_RS_V4_8821C(x) | BIT_REG_RS_V4_8821C(v))
+
+#define BIT_SHIFT_REG__CS_8821C 24
+#define BIT_MASK_REG__CS_8821C 0x3
+#define BIT_REG__CS_8821C(x)                                                   \
+	(((x) & BIT_MASK_REG__CS_8821C) << BIT_SHIFT_REG__CS_8821C)
+#define BITS_REG__CS_8821C (BIT_MASK_REG__CS_8821C << BIT_SHIFT_REG__CS_8821C)
+#define BIT_CLEAR_REG__CS_8821C(x) ((x) & (~BITS_REG__CS_8821C))
+#define BIT_GET_REG__CS_8821C(x)                                               \
+	(((x) >> BIT_SHIFT_REG__CS_8821C) & BIT_MASK_REG__CS_8821C)
+#define BIT_SET_REG__CS_8821C(x, v)                                            \
+	(BIT_CLEAR_REG__CS_8821C(x) | BIT_REG__CS_8821C(v))
+
+#define BIT_SHIFT_REG_CP_OFFSET_8821C 21
+#define BIT_MASK_REG_CP_OFFSET_8821C 0x7
+#define BIT_REG_CP_OFFSET_8821C(x)                                             \
+	(((x) & BIT_MASK_REG_CP_OFFSET_8821C) << BIT_SHIFT_REG_CP_OFFSET_8821C)
+#define BITS_REG_CP_OFFSET_8821C                                               \
+	(BIT_MASK_REG_CP_OFFSET_8821C << BIT_SHIFT_REG_CP_OFFSET_8821C)
+#define BIT_CLEAR_REG_CP_OFFSET_8821C(x) ((x) & (~BITS_REG_CP_OFFSET_8821C))
+#define BIT_GET_REG_CP_OFFSET_8821C(x)                                         \
+	(((x) >> BIT_SHIFT_REG_CP_OFFSET_8821C) & BIT_MASK_REG_CP_OFFSET_8821C)
+#define BIT_SET_REG_CP_OFFSET_8821C(x, v)                                      \
+	(BIT_CLEAR_REG_CP_OFFSET_8821C(x) | BIT_REG_CP_OFFSET_8821C(v))
+
+#define BIT_SHIFT_CP_BIAS_8821C 18
+#define BIT_MASK_CP_BIAS_8821C 0x7
+#define BIT_CP_BIAS_8821C(x)                                                   \
+	(((x) & BIT_MASK_CP_BIAS_8821C) << BIT_SHIFT_CP_BIAS_8821C)
+#define BITS_CP_BIAS_8821C (BIT_MASK_CP_BIAS_8821C << BIT_SHIFT_CP_BIAS_8821C)
+#define BIT_CLEAR_CP_BIAS_8821C(x) ((x) & (~BITS_CP_BIAS_8821C))
+#define BIT_GET_CP_BIAS_8821C(x)                                               \
+	(((x) >> BIT_SHIFT_CP_BIAS_8821C) & BIT_MASK_CP_BIAS_8821C)
+#define BIT_SET_CP_BIAS_8821C(x, v)                                            \
+	(BIT_CLEAR_CP_BIAS_8821C(x) | BIT_CP_BIAS_8821C(v))
+
+#define BIT_REG_IDOUBLE_V2_8821C BIT(17)
+#define BIT_EN_SYN_8821C BIT(16)
+
+#define BIT_SHIFT_MCCO_8821C 14
+#define BIT_MASK_MCCO_8821C 0x3
+#define BIT_MCCO_8821C(x) (((x) & BIT_MASK_MCCO_8821C) << BIT_SHIFT_MCCO_8821C)
+#define BITS_MCCO_8821C (BIT_MASK_MCCO_8821C << BIT_SHIFT_MCCO_8821C)
+#define BIT_CLEAR_MCCO_8821C(x) ((x) & (~BITS_MCCO_8821C))
+#define BIT_GET_MCCO_8821C(x)                                                  \
+	(((x) >> BIT_SHIFT_MCCO_8821C) & BIT_MASK_MCCO_8821C)
+#define BIT_SET_MCCO_8821C(x, v) (BIT_CLEAR_MCCO_8821C(x) | BIT_MCCO_8821C(v))
+
+#define BIT_SHIFT_REG_LDO_SEL_8821C 12
+#define BIT_MASK_REG_LDO_SEL_8821C 0x3
+#define BIT_REG_LDO_SEL_8821C(x)                                               \
+	(((x) & BIT_MASK_REG_LDO_SEL_8821C) << BIT_SHIFT_REG_LDO_SEL_8821C)
+#define BITS_REG_LDO_SEL_8821C                                                 \
+	(BIT_MASK_REG_LDO_SEL_8821C << BIT_SHIFT_REG_LDO_SEL_8821C)
+#define BIT_CLEAR_REG_LDO_SEL_8821C(x) ((x) & (~BITS_REG_LDO_SEL_8821C))
+#define BIT_GET_REG_LDO_SEL_8821C(x)                                           \
+	(((x) >> BIT_SHIFT_REG_LDO_SEL_8821C) & BIT_MASK_REG_LDO_SEL_8821C)
+#define BIT_SET_REG_LDO_SEL_8821C(x, v)                                        \
+	(BIT_CLEAR_REG_LDO_SEL_8821C(x) | BIT_REG_LDO_SEL_8821C(v))
+
+#define BIT_REG_KVCO_V2_8821C BIT(10)
+#define BIT_AGPIO_GPO_8821C BIT(9)
+
+#define BIT_SHIFT_AGPIO_DRV_8821C 7
+#define BIT_MASK_AGPIO_DRV_8821C 0x3
+#define BIT_AGPIO_DRV_8821C(x)                                                 \
+	(((x) & BIT_MASK_AGPIO_DRV_8821C) << BIT_SHIFT_AGPIO_DRV_8821C)
+#define BITS_AGPIO_DRV_8821C                                                   \
+	(BIT_MASK_AGPIO_DRV_8821C << BIT_SHIFT_AGPIO_DRV_8821C)
+#define BIT_CLEAR_AGPIO_DRV_8821C(x) ((x) & (~BITS_AGPIO_DRV_8821C))
+#define BIT_GET_AGPIO_DRV_8821C(x)                                             \
+	(((x) >> BIT_SHIFT_AGPIO_DRV_8821C) & BIT_MASK_AGPIO_DRV_8821C)
+#define BIT_SET_AGPIO_DRV_8821C(x, v)                                          \
+	(BIT_CLEAR_AGPIO_DRV_8821C(x) | BIT_AGPIO_DRV_8821C(v))
+
+#define BIT_SHIFT_XTAL_CAP_XO_8821C 1
+#define BIT_MASK_XTAL_CAP_XO_8821C 0x3f
+#define BIT_XTAL_CAP_XO_8821C(x)                                               \
+	(((x) & BIT_MASK_XTAL_CAP_XO_8821C) << BIT_SHIFT_XTAL_CAP_XO_8821C)
+#define BITS_XTAL_CAP_XO_8821C                                                 \
+	(BIT_MASK_XTAL_CAP_XO_8821C << BIT_SHIFT_XTAL_CAP_XO_8821C)
+#define BIT_CLEAR_XTAL_CAP_XO_8821C(x) ((x) & (~BITS_XTAL_CAP_XO_8821C))
+#define BIT_GET_XTAL_CAP_XO_8821C(x)                                           \
+	(((x) >> BIT_SHIFT_XTAL_CAP_XO_8821C) & BIT_MASK_XTAL_CAP_XO_8821C)
+#define BIT_SET_XTAL_CAP_XO_8821C(x, v)                                        \
+	(BIT_CLEAR_XTAL_CAP_XO_8821C(x) | BIT_XTAL_CAP_XO_8821C(v))
+
+#define BIT_POW_PLL_8821C BIT(0)
+
+/* 2 REG_AFE_CTRL3_8821C */
+
+#define BIT_SHIFT_PS_8821C 7
+#define BIT_MASK_PS_8821C 0x7
+#define BIT_PS_8821C(x) (((x) & BIT_MASK_PS_8821C) << BIT_SHIFT_PS_8821C)
+#define BITS_PS_8821C (BIT_MASK_PS_8821C << BIT_SHIFT_PS_8821C)
+#define BIT_CLEAR_PS_8821C(x) ((x) & (~BITS_PS_8821C))
+#define BIT_GET_PS_8821C(x) (((x) >> BIT_SHIFT_PS_8821C) & BIT_MASK_PS_8821C)
+#define BIT_SET_PS_8821C(x, v) (BIT_CLEAR_PS_8821C(x) | BIT_PS_8821C(v))
+
+#define BIT_PSEN_8821C BIT(6)
+#define BIT_DOGENB_8821C BIT(5)
+#define BIT_REG_MBIAS_8821C BIT(4)
+
+#define BIT_SHIFT_REG_R3_V4_8821C 1
+#define BIT_MASK_REG_R3_V4_8821C 0x7
+#define BIT_REG_R3_V4_8821C(x)                                                 \
+	(((x) & BIT_MASK_REG_R3_V4_8821C) << BIT_SHIFT_REG_R3_V4_8821C)
+#define BITS_REG_R3_V4_8821C                                                   \
+	(BIT_MASK_REG_R3_V4_8821C << BIT_SHIFT_REG_R3_V4_8821C)
+#define BIT_CLEAR_REG_R3_V4_8821C(x) ((x) & (~BITS_REG_R3_V4_8821C))
+#define BIT_GET_REG_R3_V4_8821C(x)                                             \
+	(((x) >> BIT_SHIFT_REG_R3_V4_8821C) & BIT_MASK_REG_R3_V4_8821C)
+#define BIT_SET_REG_R3_V4_8821C(x, v)                                          \
+	(BIT_CLEAR_REG_R3_V4_8821C(x) | BIT_REG_R3_V4_8821C(v))
+
+#define BIT_REG_CP_BIT0_8821C BIT(0)
+
+/* 2 REG_EFUSE_CTRL_8821C */
+#define BIT_EF_FLAG_8821C BIT(31)
+
+#define BIT_SHIFT_EF_PGPD_8821C 28
+#define BIT_MASK_EF_PGPD_8821C 0x7
+#define BIT_EF_PGPD_8821C(x)                                                   \
+	(((x) & BIT_MASK_EF_PGPD_8821C) << BIT_SHIFT_EF_PGPD_8821C)
+#define BITS_EF_PGPD_8821C (BIT_MASK_EF_PGPD_8821C << BIT_SHIFT_EF_PGPD_8821C)
+#define BIT_CLEAR_EF_PGPD_8821C(x) ((x) & (~BITS_EF_PGPD_8821C))
+#define BIT_GET_EF_PGPD_8821C(x)                                               \
+	(((x) >> BIT_SHIFT_EF_PGPD_8821C) & BIT_MASK_EF_PGPD_8821C)
+#define BIT_SET_EF_PGPD_8821C(x, v)                                            \
+	(BIT_CLEAR_EF_PGPD_8821C(x) | BIT_EF_PGPD_8821C(v))
+
+#define BIT_SHIFT_EF_RDT_8821C 24
+#define BIT_MASK_EF_RDT_8821C 0xf
+#define BIT_EF_RDT_8821C(x)                                                    \
+	(((x) & BIT_MASK_EF_RDT_8821C) << BIT_SHIFT_EF_RDT_8821C)
+#define BITS_EF_RDT_8821C (BIT_MASK_EF_RDT_8821C << BIT_SHIFT_EF_RDT_8821C)
+#define BIT_CLEAR_EF_RDT_8821C(x) ((x) & (~BITS_EF_RDT_8821C))
+#define BIT_GET_EF_RDT_8821C(x)                                                \
+	(((x) >> BIT_SHIFT_EF_RDT_8821C) & BIT_MASK_EF_RDT_8821C)
+#define BIT_SET_EF_RDT_8821C(x, v)                                             \
+	(BIT_CLEAR_EF_RDT_8821C(x) | BIT_EF_RDT_8821C(v))
+
+#define BIT_SHIFT_EF_PGTS_8821C 20
+#define BIT_MASK_EF_PGTS_8821C 0xf
+#define BIT_EF_PGTS_8821C(x)                                                   \
+	(((x) & BIT_MASK_EF_PGTS_8821C) << BIT_SHIFT_EF_PGTS_8821C)
+#define BITS_EF_PGTS_8821C (BIT_MASK_EF_PGTS_8821C << BIT_SHIFT_EF_PGTS_8821C)
+#define BIT_CLEAR_EF_PGTS_8821C(x) ((x) & (~BITS_EF_PGTS_8821C))
+#define BIT_GET_EF_PGTS_8821C(x)                                               \
+	(((x) >> BIT_SHIFT_EF_PGTS_8821C) & BIT_MASK_EF_PGTS_8821C)
+#define BIT_SET_EF_PGTS_8821C(x, v)                                            \
+	(BIT_CLEAR_EF_PGTS_8821C(x) | BIT_EF_PGTS_8821C(v))
+
+#define BIT_EF_PDWN_8821C BIT(19)
+#define BIT_EF_ALDEN_8821C BIT(18)
+
+#define BIT_SHIFT_EF_ADDR_8821C 8
+#define BIT_MASK_EF_ADDR_8821C 0x3ff
+#define BIT_EF_ADDR_8821C(x)                                                   \
+	(((x) & BIT_MASK_EF_ADDR_8821C) << BIT_SHIFT_EF_ADDR_8821C)
+#define BITS_EF_ADDR_8821C (BIT_MASK_EF_ADDR_8821C << BIT_SHIFT_EF_ADDR_8821C)
+#define BIT_CLEAR_EF_ADDR_8821C(x) ((x) & (~BITS_EF_ADDR_8821C))
+#define BIT_GET_EF_ADDR_8821C(x)                                               \
+	(((x) >> BIT_SHIFT_EF_ADDR_8821C) & BIT_MASK_EF_ADDR_8821C)
+#define BIT_SET_EF_ADDR_8821C(x, v)                                            \
+	(BIT_CLEAR_EF_ADDR_8821C(x) | BIT_EF_ADDR_8821C(v))
+
+#define BIT_SHIFT_EF_DATA_8821C 0
+#define BIT_MASK_EF_DATA_8821C 0xff
+#define BIT_EF_DATA_8821C(x)                                                   \
+	(((x) & BIT_MASK_EF_DATA_8821C) << BIT_SHIFT_EF_DATA_8821C)
+#define BITS_EF_DATA_8821C (BIT_MASK_EF_DATA_8821C << BIT_SHIFT_EF_DATA_8821C)
+#define BIT_CLEAR_EF_DATA_8821C(x) ((x) & (~BITS_EF_DATA_8821C))
+#define BIT_GET_EF_DATA_8821C(x)                                               \
+	(((x) >> BIT_SHIFT_EF_DATA_8821C) & BIT_MASK_EF_DATA_8821C)
+#define BIT_SET_EF_DATA_8821C(x, v)                                            \
+	(BIT_CLEAR_EF_DATA_8821C(x) | BIT_EF_DATA_8821C(v))
+
+/* 2 REG_LDO_EFUSE_CTRL_8821C */
+#define BIT_LDOE25_EN_8821C BIT(31)
+
+#define BIT_SHIFT_LDOE25_V12ADJ_L_8821C 27
+#define BIT_MASK_LDOE25_V12ADJ_L_8821C 0xf
+#define BIT_LDOE25_V12ADJ_L_8821C(x)                                           \
+	(((x) & BIT_MASK_LDOE25_V12ADJ_L_8821C)                                \
+	 << BIT_SHIFT_LDOE25_V12ADJ_L_8821C)
+#define BITS_LDOE25_V12ADJ_L_8821C                                             \
+	(BIT_MASK_LDOE25_V12ADJ_L_8821C << BIT_SHIFT_LDOE25_V12ADJ_L_8821C)
+#define BIT_CLEAR_LDOE25_V12ADJ_L_8821C(x) ((x) & (~BITS_LDOE25_V12ADJ_L_8821C))
+#define BIT_GET_LDOE25_V12ADJ_L_8821C(x)                                       \
+	(((x) >> BIT_SHIFT_LDOE25_V12ADJ_L_8821C) &                            \
+	 BIT_MASK_LDOE25_V12ADJ_L_8821C)
+#define BIT_SET_LDOE25_V12ADJ_L_8821C(x, v)                                    \
+	(BIT_CLEAR_LDOE25_V12ADJ_L_8821C(x) | BIT_LDOE25_V12ADJ_L_8821C(v))
+
+#define BIT_EF_CRES_SEL_8821C BIT(26)
+
+#define BIT_SHIFT_EF_SCAN_START_V1_8821C 16
+#define BIT_MASK_EF_SCAN_START_V1_8821C 0x3ff
+#define BIT_EF_SCAN_START_V1_8821C(x)                                          \
+	(((x) & BIT_MASK_EF_SCAN_START_V1_8821C)                               \
+	 << BIT_SHIFT_EF_SCAN_START_V1_8821C)
+#define BITS_EF_SCAN_START_V1_8821C                                            \
+	(BIT_MASK_EF_SCAN_START_V1_8821C << BIT_SHIFT_EF_SCAN_START_V1_8821C)
+#define BIT_CLEAR_EF_SCAN_START_V1_8821C(x)                                    \
+	((x) & (~BITS_EF_SCAN_START_V1_8821C))
+#define BIT_GET_EF_SCAN_START_V1_8821C(x)                                      \
+	(((x) >> BIT_SHIFT_EF_SCAN_START_V1_8821C) &                           \
+	 BIT_MASK_EF_SCAN_START_V1_8821C)
+#define BIT_SET_EF_SCAN_START_V1_8821C(x, v)                                   \
+	(BIT_CLEAR_EF_SCAN_START_V1_8821C(x) | BIT_EF_SCAN_START_V1_8821C(v))
+
+#define BIT_SHIFT_EF_SCAN_END_8821C 12
+#define BIT_MASK_EF_SCAN_END_8821C 0xf
+#define BIT_EF_SCAN_END_8821C(x)                                               \
+	(((x) & BIT_MASK_EF_SCAN_END_8821C) << BIT_SHIFT_EF_SCAN_END_8821C)
+#define BITS_EF_SCAN_END_8821C                                                 \
+	(BIT_MASK_EF_SCAN_END_8821C << BIT_SHIFT_EF_SCAN_END_8821C)
+#define BIT_CLEAR_EF_SCAN_END_8821C(x) ((x) & (~BITS_EF_SCAN_END_8821C))
+#define BIT_GET_EF_SCAN_END_8821C(x)                                           \
+	(((x) >> BIT_SHIFT_EF_SCAN_END_8821C) & BIT_MASK_EF_SCAN_END_8821C)
+#define BIT_SET_EF_SCAN_END_8821C(x, v)                                        \
+	(BIT_CLEAR_EF_SCAN_END_8821C(x) | BIT_EF_SCAN_END_8821C(v))
+
+#define BIT_EF_PD_DIS_8821C BIT(11)
+
+#define BIT_SHIFT_EF_CELL_SEL_8821C 8
+#define BIT_MASK_EF_CELL_SEL_8821C 0x3
+#define BIT_EF_CELL_SEL_8821C(x)                                               \
+	(((x) & BIT_MASK_EF_CELL_SEL_8821C) << BIT_SHIFT_EF_CELL_SEL_8821C)
+#define BITS_EF_CELL_SEL_8821C                                                 \
+	(BIT_MASK_EF_CELL_SEL_8821C << BIT_SHIFT_EF_CELL_SEL_8821C)
+#define BIT_CLEAR_EF_CELL_SEL_8821C(x) ((x) & (~BITS_EF_CELL_SEL_8821C))
+#define BIT_GET_EF_CELL_SEL_8821C(x)                                           \
+	(((x) >> BIT_SHIFT_EF_CELL_SEL_8821C) & BIT_MASK_EF_CELL_SEL_8821C)
+#define BIT_SET_EF_CELL_SEL_8821C(x, v)                                        \
+	(BIT_CLEAR_EF_CELL_SEL_8821C(x) | BIT_EF_CELL_SEL_8821C(v))
+
+#define BIT_EF_TRPT_8821C BIT(7)
+
+#define BIT_SHIFT_EF_TTHD_8821C 0
+#define BIT_MASK_EF_TTHD_8821C 0x7f
+#define BIT_EF_TTHD_8821C(x)                                                   \
+	(((x) & BIT_MASK_EF_TTHD_8821C) << BIT_SHIFT_EF_TTHD_8821C)
+#define BITS_EF_TTHD_8821C (BIT_MASK_EF_TTHD_8821C << BIT_SHIFT_EF_TTHD_8821C)
+#define BIT_CLEAR_EF_TTHD_8821C(x) ((x) & (~BITS_EF_TTHD_8821C))
+#define BIT_GET_EF_TTHD_8821C(x)                                               \
+	(((x) >> BIT_SHIFT_EF_TTHD_8821C) & BIT_MASK_EF_TTHD_8821C)
+#define BIT_SET_EF_TTHD_8821C(x, v)                                            \
+	(BIT_CLEAR_EF_TTHD_8821C(x) | BIT_EF_TTHD_8821C(v))
+
+/* 2 REG_PWR_OPTION_CTRL_8821C */
+
+#define BIT_SHIFT_DBG_SEL_V1_8821C 16
+#define BIT_MASK_DBG_SEL_V1_8821C 0xff
+#define BIT_DBG_SEL_V1_8821C(x)                                                \
+	(((x) & BIT_MASK_DBG_SEL_V1_8821C) << BIT_SHIFT_DBG_SEL_V1_8821C)
+#define BITS_DBG_SEL_V1_8821C                                                  \
+	(BIT_MASK_DBG_SEL_V1_8821C << BIT_SHIFT_DBG_SEL_V1_8821C)
+#define BIT_CLEAR_DBG_SEL_V1_8821C(x) ((x) & (~BITS_DBG_SEL_V1_8821C))
+#define BIT_GET_DBG_SEL_V1_8821C(x)                                            \
+	(((x) >> BIT_SHIFT_DBG_SEL_V1_8821C) & BIT_MASK_DBG_SEL_V1_8821C)
+#define BIT_SET_DBG_SEL_V1_8821C(x, v)                                         \
+	(BIT_CLEAR_DBG_SEL_V1_8821C(x) | BIT_DBG_SEL_V1_8821C(v))
+
+#define BIT_SHIFT_DBG_SEL_BYTE_8821C 14
+#define BIT_MASK_DBG_SEL_BYTE_8821C 0x3
+#define BIT_DBG_SEL_BYTE_8821C(x)                                              \
+	(((x) & BIT_MASK_DBG_SEL_BYTE_8821C) << BIT_SHIFT_DBG_SEL_BYTE_8821C)
+#define BITS_DBG_SEL_BYTE_8821C                                                \
+	(BIT_MASK_DBG_SEL_BYTE_8821C << BIT_SHIFT_DBG_SEL_BYTE_8821C)
+#define BIT_CLEAR_DBG_SEL_BYTE_8821C(x) ((x) & (~BITS_DBG_SEL_BYTE_8821C))
+#define BIT_GET_DBG_SEL_BYTE_8821C(x)                                          \
+	(((x) >> BIT_SHIFT_DBG_SEL_BYTE_8821C) & BIT_MASK_DBG_SEL_BYTE_8821C)
+#define BIT_SET_DBG_SEL_BYTE_8821C(x, v)                                       \
+	(BIT_CLEAR_DBG_SEL_BYTE_8821C(x) | BIT_DBG_SEL_BYTE_8821C(v))
+
+#define BIT_SHIFT_STD_L1_V1_8821C 12
+#define BIT_MASK_STD_L1_V1_8821C 0x3
+#define BIT_STD_L1_V1_8821C(x)                                                 \
+	(((x) & BIT_MASK_STD_L1_V1_8821C) << BIT_SHIFT_STD_L1_V1_8821C)
+#define BITS_STD_L1_V1_8821C                                                   \
+	(BIT_MASK_STD_L1_V1_8821C << BIT_SHIFT_STD_L1_V1_8821C)
+#define BIT_CLEAR_STD_L1_V1_8821C(x) ((x) & (~BITS_STD_L1_V1_8821C))
+#define BIT_GET_STD_L1_V1_8821C(x)                                             \
+	(((x) >> BIT_SHIFT_STD_L1_V1_8821C) & BIT_MASK_STD_L1_V1_8821C)
+#define BIT_SET_STD_L1_V1_8821C(x, v)                                          \
+	(BIT_CLEAR_STD_L1_V1_8821C(x) | BIT_STD_L1_V1_8821C(v))
+
+#define BIT_SYSON_DBG_PAD_E2_8821C BIT(11)
+#define BIT_SYSON_LED_PAD_E2_8821C BIT(10)
+#define BIT_SYSON_GPEE_PAD_E2_8821C BIT(9)
+#define BIT_SYSON_PCI_PAD_E2_8821C BIT(8)
+#define BIT_AUTO_SW_LDO_VOL_EN_8821C BIT(7)
+
+#define BIT_SHIFT_SYSON_SPS0WWV_WT_8821C 4
+#define BIT_MASK_SYSON_SPS0WWV_WT_8821C 0x3
+#define BIT_SYSON_SPS0WWV_WT_8821C(x)                                          \
+	(((x) & BIT_MASK_SYSON_SPS0WWV_WT_8821C)                               \
+	 << BIT_SHIFT_SYSON_SPS0WWV_WT_8821C)
+#define BITS_SYSON_SPS0WWV_WT_8821C                                            \
+	(BIT_MASK_SYSON_SPS0WWV_WT_8821C << BIT_SHIFT_SYSON_SPS0WWV_WT_8821C)
+#define BIT_CLEAR_SYSON_SPS0WWV_WT_8821C(x)                                    \
+	((x) & (~BITS_SYSON_SPS0WWV_WT_8821C))
+#define BIT_GET_SYSON_SPS0WWV_WT_8821C(x)                                      \
+	(((x) >> BIT_SHIFT_SYSON_SPS0WWV_WT_8821C) &                           \
+	 BIT_MASK_SYSON_SPS0WWV_WT_8821C)
+#define BIT_SET_SYSON_SPS0WWV_WT_8821C(x, v)                                   \
+	(BIT_CLEAR_SYSON_SPS0WWV_WT_8821C(x) | BIT_SYSON_SPS0WWV_WT_8821C(v))
+
+#define BIT_SHIFT_SYSON_SPS0LDO_WT_8821C 2
+#define BIT_MASK_SYSON_SPS0LDO_WT_8821C 0x3
+#define BIT_SYSON_SPS0LDO_WT_8821C(x)                                          \
+	(((x) & BIT_MASK_SYSON_SPS0LDO_WT_8821C)                               \
+	 << BIT_SHIFT_SYSON_SPS0LDO_WT_8821C)
+#define BITS_SYSON_SPS0LDO_WT_8821C                                            \
+	(BIT_MASK_SYSON_SPS0LDO_WT_8821C << BIT_SHIFT_SYSON_SPS0LDO_WT_8821C)
+#define BIT_CLEAR_SYSON_SPS0LDO_WT_8821C(x)                                    \
+	((x) & (~BITS_SYSON_SPS0LDO_WT_8821C))
+#define BIT_GET_SYSON_SPS0LDO_WT_8821C(x)                                      \
+	(((x) >> BIT_SHIFT_SYSON_SPS0LDO_WT_8821C) &                           \
+	 BIT_MASK_SYSON_SPS0LDO_WT_8821C)
+#define BIT_SET_SYSON_SPS0LDO_WT_8821C(x, v)                                   \
+	(BIT_CLEAR_SYSON_SPS0LDO_WT_8821C(x) | BIT_SYSON_SPS0LDO_WT_8821C(v))
+
+#define BIT_SHIFT_SYSON_RCLK_SCALE_8821C 0
+#define BIT_MASK_SYSON_RCLK_SCALE_8821C 0x3
+#define BIT_SYSON_RCLK_SCALE_8821C(x)                                          \
+	(((x) & BIT_MASK_SYSON_RCLK_SCALE_8821C)                               \
+	 << BIT_SHIFT_SYSON_RCLK_SCALE_8821C)
+#define BITS_SYSON_RCLK_SCALE_8821C                                            \
+	(BIT_MASK_SYSON_RCLK_SCALE_8821C << BIT_SHIFT_SYSON_RCLK_SCALE_8821C)
+#define BIT_CLEAR_SYSON_RCLK_SCALE_8821C(x)                                    \
+	((x) & (~BITS_SYSON_RCLK_SCALE_8821C))
+#define BIT_GET_SYSON_RCLK_SCALE_8821C(x)                                      \
+	(((x) >> BIT_SHIFT_SYSON_RCLK_SCALE_8821C) &                           \
+	 BIT_MASK_SYSON_RCLK_SCALE_8821C)
+#define BIT_SET_SYSON_RCLK_SCALE_8821C(x, v)                                   \
+	(BIT_CLEAR_SYSON_RCLK_SCALE_8821C(x) | BIT_SYSON_RCLK_SCALE_8821C(v))
+
+/* 2 REG_CAL_TIMER_8821C */
+
+#define BIT_SHIFT_MATCH_CNT_8821C 8
+#define BIT_MASK_MATCH_CNT_8821C 0xff
+#define BIT_MATCH_CNT_8821C(x)                                                 \
+	(((x) & BIT_MASK_MATCH_CNT_8821C) << BIT_SHIFT_MATCH_CNT_8821C)
+#define BITS_MATCH_CNT_8821C                                                   \
+	(BIT_MASK_MATCH_CNT_8821C << BIT_SHIFT_MATCH_CNT_8821C)
+#define BIT_CLEAR_MATCH_CNT_8821C(x) ((x) & (~BITS_MATCH_CNT_8821C))
+#define BIT_GET_MATCH_CNT_8821C(x)                                             \
+	(((x) >> BIT_SHIFT_MATCH_CNT_8821C) & BIT_MASK_MATCH_CNT_8821C)
+#define BIT_SET_MATCH_CNT_8821C(x, v)                                          \
+	(BIT_CLEAR_MATCH_CNT_8821C(x) | BIT_MATCH_CNT_8821C(v))
+
+#define BIT_SHIFT_CAL_SCAL_8821C 0
+#define BIT_MASK_CAL_SCAL_8821C 0xff
+#define BIT_CAL_SCAL_8821C(x)                                                  \
+	(((x) & BIT_MASK_CAL_SCAL_8821C) << BIT_SHIFT_CAL_SCAL_8821C)
+#define BITS_CAL_SCAL_8821C                                                    \
+	(BIT_MASK_CAL_SCAL_8821C << BIT_SHIFT_CAL_SCAL_8821C)
+#define BIT_CLEAR_CAL_SCAL_8821C(x) ((x) & (~BITS_CAL_SCAL_8821C))
+#define BIT_GET_CAL_SCAL_8821C(x)                                              \
+	(((x) >> BIT_SHIFT_CAL_SCAL_8821C) & BIT_MASK_CAL_SCAL_8821C)
+#define BIT_SET_CAL_SCAL_8821C(x, v)                                           \
+	(BIT_CLEAR_CAL_SCAL_8821C(x) | BIT_CAL_SCAL_8821C(v))
+
+/* 2 REG_ACLK_MON_8821C */
+
+#define BIT_SHIFT_RCLK_MON_8821C 5
+#define BIT_MASK_RCLK_MON_8821C 0x7ff
+#define BIT_RCLK_MON_8821C(x)                                                  \
+	(((x) & BIT_MASK_RCLK_MON_8821C) << BIT_SHIFT_RCLK_MON_8821C)
+#define BITS_RCLK_MON_8821C                                                    \
+	(BIT_MASK_RCLK_MON_8821C << BIT_SHIFT_RCLK_MON_8821C)
+#define BIT_CLEAR_RCLK_MON_8821C(x) ((x) & (~BITS_RCLK_MON_8821C))
+#define BIT_GET_RCLK_MON_8821C(x)                                              \
+	(((x) >> BIT_SHIFT_RCLK_MON_8821C) & BIT_MASK_RCLK_MON_8821C)
+#define BIT_SET_RCLK_MON_8821C(x, v)                                           \
+	(BIT_CLEAR_RCLK_MON_8821C(x) | BIT_RCLK_MON_8821C(v))
+
+#define BIT_CAL_EN_8821C BIT(4)
+
+#define BIT_SHIFT_DPSTU_8821C 2
+#define BIT_MASK_DPSTU_8821C 0x3
+#define BIT_DPSTU_8821C(x)                                                     \
+	(((x) & BIT_MASK_DPSTU_8821C) << BIT_SHIFT_DPSTU_8821C)
+#define BITS_DPSTU_8821C (BIT_MASK_DPSTU_8821C << BIT_SHIFT_DPSTU_8821C)
+#define BIT_CLEAR_DPSTU_8821C(x) ((x) & (~BITS_DPSTU_8821C))
+#define BIT_GET_DPSTU_8821C(x)                                                 \
+	(((x) >> BIT_SHIFT_DPSTU_8821C) & BIT_MASK_DPSTU_8821C)
+#define BIT_SET_DPSTU_8821C(x, v)                                              \
+	(BIT_CLEAR_DPSTU_8821C(x) | BIT_DPSTU_8821C(v))
+
+#define BIT_SUS_16X_8821C BIT(1)
+
+/* 2 REG_GPIO_MUXCFG_8821C */
+#define BIT_FSPI_EN_8821C BIT(19)
+#define BIT_WL_RTS_EXT_32K_SEL_8821C BIT(18)
+#define BIT_WLGP_SPI_EN_8821C BIT(16)
+#define BIT_SIC_LBK_8821C BIT(15)
+#define BIT_ENHTP_8821C BIT(14)
+#define BIT_ENSIC_8821C BIT(12)
+#define BIT_SIC_SWRST_8821C BIT(11)
+#define BIT_PO_WIFI_PTA_PINS_8821C BIT(10)
+#define BIT_PO_BT_PTA_PINS_8821C BIT(9)
+#define BIT_ENUART_8821C BIT(8)
+
+#define BIT_SHIFT_BTMODE_8821C 6
+#define BIT_MASK_BTMODE_8821C 0x3
+#define BIT_BTMODE_8821C(x)                                                    \
+	(((x) & BIT_MASK_BTMODE_8821C) << BIT_SHIFT_BTMODE_8821C)
+#define BITS_BTMODE_8821C (BIT_MASK_BTMODE_8821C << BIT_SHIFT_BTMODE_8821C)
+#define BIT_CLEAR_BTMODE_8821C(x) ((x) & (~BITS_BTMODE_8821C))
+#define BIT_GET_BTMODE_8821C(x)                                                \
+	(((x) >> BIT_SHIFT_BTMODE_8821C) & BIT_MASK_BTMODE_8821C)
+#define BIT_SET_BTMODE_8821C(x, v)                                             \
+	(BIT_CLEAR_BTMODE_8821C(x) | BIT_BTMODE_8821C(v))
+
+#define BIT_ENBT_8821C BIT(5)
+#define BIT_EROM_EN_8821C BIT(4)
+#define BIT_WLRFE_6_7_EN_8821C BIT(3)
+#define BIT_WLRFE_4_5_EN_8821C BIT(2)
+
+#define BIT_SHIFT_GPIOSEL_8821C 0
+#define BIT_MASK_GPIOSEL_8821C 0x3
+#define BIT_GPIOSEL_8821C(x)                                                   \
+	(((x) & BIT_MASK_GPIOSEL_8821C) << BIT_SHIFT_GPIOSEL_8821C)
+#define BITS_GPIOSEL_8821C (BIT_MASK_GPIOSEL_8821C << BIT_SHIFT_GPIOSEL_8821C)
+#define BIT_CLEAR_GPIOSEL_8821C(x) ((x) & (~BITS_GPIOSEL_8821C))
+#define BIT_GET_GPIOSEL_8821C(x)                                               \
+	(((x) >> BIT_SHIFT_GPIOSEL_8821C) & BIT_MASK_GPIOSEL_8821C)
+#define BIT_SET_GPIOSEL_8821C(x, v)                                            \
+	(BIT_CLEAR_GPIOSEL_8821C(x) | BIT_GPIOSEL_8821C(v))
+
+/* 2 REG_GPIO_PIN_CTRL_8821C */
+
+#define BIT_SHIFT_GPIO_MOD_7_TO_0_8821C 24
+#define BIT_MASK_GPIO_MOD_7_TO_0_8821C 0xff
+#define BIT_GPIO_MOD_7_TO_0_8821C(x)                                           \
+	(((x) & BIT_MASK_GPIO_MOD_7_TO_0_8821C)                                \
+	 << BIT_SHIFT_GPIO_MOD_7_TO_0_8821C)
+#define BITS_GPIO_MOD_7_TO_0_8821C                                             \
+	(BIT_MASK_GPIO_MOD_7_TO_0_8821C << BIT_SHIFT_GPIO_MOD_7_TO_0_8821C)
+#define BIT_CLEAR_GPIO_MOD_7_TO_0_8821C(x) ((x) & (~BITS_GPIO_MOD_7_TO_0_8821C))
+#define BIT_GET_GPIO_MOD_7_TO_0_8821C(x)                                       \
+	(((x) >> BIT_SHIFT_GPIO_MOD_7_TO_0_8821C) &                            \
+	 BIT_MASK_GPIO_MOD_7_TO_0_8821C)
+#define BIT_SET_GPIO_MOD_7_TO_0_8821C(x, v)                                    \
+	(BIT_CLEAR_GPIO_MOD_7_TO_0_8821C(x) | BIT_GPIO_MOD_7_TO_0_8821C(v))
+
+#define BIT_SHIFT_GPIO_IO_SEL_7_TO_0_8821C 16
+#define BIT_MASK_GPIO_IO_SEL_7_TO_0_8821C 0xff
+#define BIT_GPIO_IO_SEL_7_TO_0_8821C(x)                                        \
+	(((x) & BIT_MASK_GPIO_IO_SEL_7_TO_0_8821C)                             \
+	 << BIT_SHIFT_GPIO_IO_SEL_7_TO_0_8821C)
+#define BITS_GPIO_IO_SEL_7_TO_0_8821C                                          \
+	(BIT_MASK_GPIO_IO_SEL_7_TO_0_8821C                                     \
+	 << BIT_SHIFT_GPIO_IO_SEL_7_TO_0_8821C)
+#define BIT_CLEAR_GPIO_IO_SEL_7_TO_0_8821C(x)                                  \
+	((x) & (~BITS_GPIO_IO_SEL_7_TO_0_8821C))
+#define BIT_GET_GPIO_IO_SEL_7_TO_0_8821C(x)                                    \
+	(((x) >> BIT_SHIFT_GPIO_IO_SEL_7_TO_0_8821C) &                         \
+	 BIT_MASK_GPIO_IO_SEL_7_TO_0_8821C)
+#define BIT_SET_GPIO_IO_SEL_7_TO_0_8821C(x, v)                                 \
+	(BIT_CLEAR_GPIO_IO_SEL_7_TO_0_8821C(x) |                               \
+	 BIT_GPIO_IO_SEL_7_TO_0_8821C(v))
+
+#define BIT_SHIFT_GPIO_OUT_7_TO_0_8821C 8
+#define BIT_MASK_GPIO_OUT_7_TO_0_8821C 0xff
+#define BIT_GPIO_OUT_7_TO_0_8821C(x)                                           \
+	(((x) & BIT_MASK_GPIO_OUT_7_TO_0_8821C)                                \
+	 << BIT_SHIFT_GPIO_OUT_7_TO_0_8821C)
+#define BITS_GPIO_OUT_7_TO_0_8821C                                             \
+	(BIT_MASK_GPIO_OUT_7_TO_0_8821C << BIT_SHIFT_GPIO_OUT_7_TO_0_8821C)
+#define BIT_CLEAR_GPIO_OUT_7_TO_0_8821C(x) ((x) & (~BITS_GPIO_OUT_7_TO_0_8821C))
+#define BIT_GET_GPIO_OUT_7_TO_0_8821C(x)                                       \
+	(((x) >> BIT_SHIFT_GPIO_OUT_7_TO_0_8821C) &                            \
+	 BIT_MASK_GPIO_OUT_7_TO_0_8821C)
+#define BIT_SET_GPIO_OUT_7_TO_0_8821C(x, v)                                    \
+	(BIT_CLEAR_GPIO_OUT_7_TO_0_8821C(x) | BIT_GPIO_OUT_7_TO_0_8821C(v))
+
+#define BIT_SHIFT_GPIO_IN_7_TO_0_8821C 0
+#define BIT_MASK_GPIO_IN_7_TO_0_8821C 0xff
+#define BIT_GPIO_IN_7_TO_0_8821C(x)                                            \
+	(((x) & BIT_MASK_GPIO_IN_7_TO_0_8821C)                                 \
+	 << BIT_SHIFT_GPIO_IN_7_TO_0_8821C)
+#define BITS_GPIO_IN_7_TO_0_8821C                                              \
+	(BIT_MASK_GPIO_IN_7_TO_0_8821C << BIT_SHIFT_GPIO_IN_7_TO_0_8821C)
+#define BIT_CLEAR_GPIO_IN_7_TO_0_8821C(x) ((x) & (~BITS_GPIO_IN_7_TO_0_8821C))
+#define BIT_GET_GPIO_IN_7_TO_0_8821C(x)                                        \
+	(((x) >> BIT_SHIFT_GPIO_IN_7_TO_0_8821C) &                             \
+	 BIT_MASK_GPIO_IN_7_TO_0_8821C)
+#define BIT_SET_GPIO_IN_7_TO_0_8821C(x, v)                                     \
+	(BIT_CLEAR_GPIO_IN_7_TO_0_8821C(x) | BIT_GPIO_IN_7_TO_0_8821C(v))
+
+/* 2 REG_GPIO_INTM_8821C */
+
+#define BIT_SHIFT_MUXDBG_SEL_8821C 30
+#define BIT_MASK_MUXDBG_SEL_8821C 0x3
+#define BIT_MUXDBG_SEL_8821C(x)                                                \
+	(((x) & BIT_MASK_MUXDBG_SEL_8821C) << BIT_SHIFT_MUXDBG_SEL_8821C)
+#define BITS_MUXDBG_SEL_8821C                                                  \
+	(BIT_MASK_MUXDBG_SEL_8821C << BIT_SHIFT_MUXDBG_SEL_8821C)
+#define BIT_CLEAR_MUXDBG_SEL_8821C(x) ((x) & (~BITS_MUXDBG_SEL_8821C))
+#define BIT_GET_MUXDBG_SEL_8821C(x)                                            \
+	(((x) >> BIT_SHIFT_MUXDBG_SEL_8821C) & BIT_MASK_MUXDBG_SEL_8821C)
+#define BIT_SET_MUXDBG_SEL_8821C(x, v)                                         \
+	(BIT_CLEAR_MUXDBG_SEL_8821C(x) | BIT_MUXDBG_SEL_8821C(v))
+
+#define BIT_EXTWOL_SEL_8821C BIT(17)
+#define BIT_EXTWOL_EN_8821C BIT(16)
+#define BIT_GPIOF_INT_MD_8821C BIT(15)
+#define BIT_GPIOE_INT_MD_8821C BIT(14)
+#define BIT_GPIOD_INT_MD_8821C BIT(13)
+#define BIT_GPIOF_INT_MD_8821C BIT(15)
+#define BIT_GPIOE_INT_MD_8821C BIT(14)
+#define BIT_GPIOD_INT_MD_8821C BIT(13)
+#define BIT_GPIOC_INT_MD_8821C BIT(12)
+#define BIT_GPIOB_INT_MD_8821C BIT(11)
+#define BIT_GPIOA_INT_MD_8821C BIT(10)
+#define BIT_GPIO9_INT_MD_8821C BIT(9)
+#define BIT_GPIO8_INT_MD_8821C BIT(8)
+#define BIT_GPIO7_INT_MD_8821C BIT(7)
+#define BIT_GPIO6_INT_MD_8821C BIT(6)
+#define BIT_GPIO5_INT_MD_8821C BIT(5)
+#define BIT_GPIO4_INT_MD_8821C BIT(4)
+#define BIT_GPIO3_INT_MD_8821C BIT(3)
+#define BIT_GPIO2_INT_MD_8821C BIT(2)
+#define BIT_GPIO1_INT_MD_8821C BIT(1)
+#define BIT_GPIO0_INT_MD_8821C BIT(0)
+
+/* 2 REG_LED_CFG_8821C */
+#define BIT_GPIO3_WL_CTRL_EN_8821C BIT(27)
+#define BIT_LNAON_SEL_EN_8821C BIT(26)
+#define BIT_PAPE_SEL_EN_8821C BIT(25)
+#define BIT_DPDT_WLBT_SEL_8821C BIT(24)
+#define BIT_DPDT_SEL_EN_8821C BIT(23)
+#define BIT_GPIO13_14_WL_CTRL_EN_8821C BIT(22)
+#define BIT_LED2DIS_8821C BIT(21)
+#define BIT_LED2PL_8821C BIT(20)
+#define BIT_LED2SV_8821C BIT(19)
+
+#define BIT_SHIFT_LED2CM_8821C 16
+#define BIT_MASK_LED2CM_8821C 0x7
+#define BIT_LED2CM_8821C(x)                                                    \
+	(((x) & BIT_MASK_LED2CM_8821C) << BIT_SHIFT_LED2CM_8821C)
+#define BITS_LED2CM_8821C (BIT_MASK_LED2CM_8821C << BIT_SHIFT_LED2CM_8821C)
+#define BIT_CLEAR_LED2CM_8821C(x) ((x) & (~BITS_LED2CM_8821C))
+#define BIT_GET_LED2CM_8821C(x)                                                \
+	(((x) >> BIT_SHIFT_LED2CM_8821C) & BIT_MASK_LED2CM_8821C)
+#define BIT_SET_LED2CM_8821C(x, v)                                             \
+	(BIT_CLEAR_LED2CM_8821C(x) | BIT_LED2CM_8821C(v))
+
+#define BIT_LED1DIS_8821C BIT(15)
+#define BIT_LED1PL_8821C BIT(12)
+#define BIT_LED1SV_8821C BIT(11)
+
+#define BIT_SHIFT_LED1CM_8821C 8
+#define BIT_MASK_LED1CM_8821C 0x7
+#define BIT_LED1CM_8821C(x)                                                    \
+	(((x) & BIT_MASK_LED1CM_8821C) << BIT_SHIFT_LED1CM_8821C)
+#define BITS_LED1CM_8821C (BIT_MASK_LED1CM_8821C << BIT_SHIFT_LED1CM_8821C)
+#define BIT_CLEAR_LED1CM_8821C(x) ((x) & (~BITS_LED1CM_8821C))
+#define BIT_GET_LED1CM_8821C(x)                                                \
+	(((x) >> BIT_SHIFT_LED1CM_8821C) & BIT_MASK_LED1CM_8821C)
+#define BIT_SET_LED1CM_8821C(x, v)                                             \
+	(BIT_CLEAR_LED1CM_8821C(x) | BIT_LED1CM_8821C(v))
+
+#define BIT_LED0DIS_8821C BIT(7)
+
+#define BIT_SHIFT_AFE_LDO_SWR_CHECK_8821C 5
+#define BIT_MASK_AFE_LDO_SWR_CHECK_8821C 0x3
+#define BIT_AFE_LDO_SWR_CHECK_8821C(x)                                         \
+	(((x) & BIT_MASK_AFE_LDO_SWR_CHECK_8821C)                              \
+	 << BIT_SHIFT_AFE_LDO_SWR_CHECK_8821C)
+#define BITS_AFE_LDO_SWR_CHECK_8821C                                           \
+	(BIT_MASK_AFE_LDO_SWR_CHECK_8821C << BIT_SHIFT_AFE_LDO_SWR_CHECK_8821C)
+#define BIT_CLEAR_AFE_LDO_SWR_CHECK_8821C(x)                                   \
+	((x) & (~BITS_AFE_LDO_SWR_CHECK_8821C))
+#define BIT_GET_AFE_LDO_SWR_CHECK_8821C(x)                                     \
+	(((x) >> BIT_SHIFT_AFE_LDO_SWR_CHECK_8821C) &                          \
+	 BIT_MASK_AFE_LDO_SWR_CHECK_8821C)
+#define BIT_SET_AFE_LDO_SWR_CHECK_8821C(x, v)                                  \
+	(BIT_CLEAR_AFE_LDO_SWR_CHECK_8821C(x) | BIT_AFE_LDO_SWR_CHECK_8821C(v))
+
+#define BIT_LED0PL_8821C BIT(4)
+#define BIT_LED0SV_8821C BIT(3)
+
+#define BIT_SHIFT_LED0CM_8821C 0
+#define BIT_MASK_LED0CM_8821C 0x7
+#define BIT_LED0CM_8821C(x)                                                    \
+	(((x) & BIT_MASK_LED0CM_8821C) << BIT_SHIFT_LED0CM_8821C)
+#define BITS_LED0CM_8821C (BIT_MASK_LED0CM_8821C << BIT_SHIFT_LED0CM_8821C)
+#define BIT_CLEAR_LED0CM_8821C(x) ((x) & (~BITS_LED0CM_8821C))
+#define BIT_GET_LED0CM_8821C(x)                                                \
+	(((x) >> BIT_SHIFT_LED0CM_8821C) & BIT_MASK_LED0CM_8821C)
+#define BIT_SET_LED0CM_8821C(x, v)                                             \
+	(BIT_CLEAR_LED0CM_8821C(x) | BIT_LED0CM_8821C(v))
+
+/* 2 REG_FSIMR_8821C */
+#define BIT_FS_PDNINT_EN_8821C BIT(31)
+#define BIT_NFC_INT_PAD_EN_8821C BIT(30)
+#define BIT_FS_SPS_OCP_INT_EN_8821C BIT(29)
+#define BIT_FS_PWMERR_INT_EN_8821C BIT(28)
+#define BIT_FS_GPIOF_INT_EN_8821C BIT(27)
+#define BIT_FS_GPIOE_INT_EN_8821C BIT(26)
+#define BIT_FS_GPIOD_INT_EN_8821C BIT(25)
+#define BIT_FS_GPIOC_INT_EN_8821C BIT(24)
+#define BIT_FS_GPIOB_INT_EN_8821C BIT(23)
+#define BIT_FS_GPIOA_INT_EN_8821C BIT(22)
+#define BIT_FS_GPIO9_INT_EN_8821C BIT(21)
+#define BIT_FS_GPIO8_INT_EN_8821C BIT(20)
+#define BIT_FS_GPIO7_INT_EN_8821C BIT(19)
+#define BIT_FS_GPIO6_INT_EN_8821C BIT(18)
+#define BIT_FS_GPIO5_INT_EN_8821C BIT(17)
+#define BIT_FS_GPIO4_INT_EN_8821C BIT(16)
+#define BIT_FS_GPIO3_INT_EN_8821C BIT(15)
+#define BIT_FS_GPIO2_INT_EN_8821C BIT(14)
+#define BIT_FS_GPIO1_INT_EN_8821C BIT(13)
+#define BIT_FS_GPIO0_INT_EN_8821C BIT(12)
+#define BIT_FS_HCI_SUS_EN_8821C BIT(11)
+#define BIT_FS_HCI_RES_EN_8821C BIT(10)
+#define BIT_FS_HCI_RESET_EN_8821C BIT(9)
+#define BIT_USB_SCSI_CMD_EN_8821C BIT(8)
+#define BIT_FS_BTON_STS_UPDATE_MSK_EN_8821C BIT(7)
+#define BIT_ACT2RECOVERY_INT_EN_V1_8821C BIT(6)
+#define BIT_GEN1GEN2_SWITCH_8821C BIT(5)
+#define BIT_HCI_TXDMA_REQ_HIMR_8821C BIT(4)
+#define BIT_FS_32K_LEAVE_SETTING_MAK_8821C BIT(3)
+#define BIT_FS_32K_ENTER_SETTING_MAK_8821C BIT(2)
+#define BIT_FS_USB_LPMRSM_MSK_8821C BIT(1)
+#define BIT_FS_USB_LPMINT_MSK_8821C BIT(0)
+
+/* 2 REG_FSISR_8821C */
+#define BIT_FS_PDNINT_8821C BIT(31)
+#define BIT_FS_SPS_OCP_INT_8821C BIT(29)
+#define BIT_FS_PWMERR_INT_8821C BIT(28)
+#define BIT_FS_GPIOF_INT_8821C BIT(27)
+#define BIT_FS_GPIOE_INT_8821C BIT(26)
+#define BIT_FS_GPIOD_INT_8821C BIT(25)
+#define BIT_FS_GPIOC_INT_8821C BIT(24)
+#define BIT_FS_GPIOB_INT_8821C BIT(23)
+#define BIT_FS_GPIOA_INT_8821C BIT(22)
+#define BIT_FS_GPIO9_INT_8821C BIT(21)
+#define BIT_FS_GPIO8_INT_8821C BIT(20)
+#define BIT_FS_GPIO7_INT_8821C BIT(19)
+#define BIT_FS_GPIO6_INT_8821C BIT(18)
+#define BIT_FS_GPIO5_INT_8821C BIT(17)
+#define BIT_FS_GPIO4_INT_8821C BIT(16)
+#define BIT_FS_GPIO3_INT_8821C BIT(15)
+#define BIT_FS_GPIO2_INT_8821C BIT(14)
+#define BIT_FS_GPIO1_INT_8821C BIT(13)
+#define BIT_FS_GPIO0_INT_8821C BIT(12)
+#define BIT_FS_HCI_SUS_INT_8821C BIT(11)
+#define BIT_FS_HCI_RES_INT_8821C BIT(10)
+#define BIT_FS_HCI_RESET_INT_8821C BIT(9)
+#define BIT_USB_SCSI_CMD_INT_8821C BIT(8)
+#define BIT_ACT2RECOVERY_8821C BIT(6)
+#define BIT_GEN1GEN2_SWITCH_8821C BIT(5)
+#define BIT_HCI_TXDMA_REQ_HISR_8821C BIT(4)
+#define BIT_FS_32K_LEAVE_SETTING_INT_8821C BIT(3)
+#define BIT_FS_32K_ENTER_SETTING_INT_8821C BIT(2)
+#define BIT_FS_USB_LPMRSM_INT_8821C BIT(1)
+#define BIT_FS_USB_LPMINT_INT_8821C BIT(0)
+
+/* 2 REG_HSIMR_8821C */
+#define BIT_GPIOF_INT_EN_8821C BIT(31)
+#define BIT_GPIOE_INT_EN_8821C BIT(30)
+#define BIT_GPIOD_INT_EN_8821C BIT(29)
+#define BIT_GPIOC_INT_EN_8821C BIT(28)
+#define BIT_GPIOB_INT_EN_8821C BIT(27)
+#define BIT_GPIOA_INT_EN_8821C BIT(26)
+#define BIT_GPIO9_INT_EN_8821C BIT(25)
+#define BIT_GPIO8_INT_EN_8821C BIT(24)
+#define BIT_GPIO7_INT_EN_8821C BIT(23)
+#define BIT_GPIO6_INT_EN_8821C BIT(22)
+#define BIT_GPIO5_INT_EN_8821C BIT(21)
+#define BIT_GPIO4_INT_EN_8821C BIT(20)
+#define BIT_GPIO3_INT_EN_8821C BIT(19)
+#define BIT_GPIO2_INT_EN_V1_8821C BIT(18)
+#define BIT_GPIO1_INT_EN_8821C BIT(17)
+#define BIT_GPIO0_INT_EN_8821C BIT(16)
+#define BIT_PDNINT_EN_8821C BIT(7)
+#define BIT_RON_INT_EN_8821C BIT(6)
+#define BIT_SPS_OCP_INT_EN_8821C BIT(5)
+#define BIT_GPIO15_0_INT_EN_8821C BIT(0)
+
+/* 2 REG_HSISR_8821C */
+#define BIT_GPIOF_INT_8821C BIT(31)
+#define BIT_GPIOE_INT_8821C BIT(30)
+#define BIT_GPIOD_INT_8821C BIT(29)
+#define BIT_GPIOC_INT_8821C BIT(28)
+#define BIT_GPIOB_INT_8821C BIT(27)
+#define BIT_GPIOA_INT_8821C BIT(26)
+#define BIT_GPIO9_INT_8821C BIT(25)
+#define BIT_GPIO8_INT_8821C BIT(24)
+#define BIT_GPIO7_INT_8821C BIT(23)
+#define BIT_GPIO6_INT_8821C BIT(22)
+#define BIT_GPIO5_INT_8821C BIT(21)
+#define BIT_GPIO4_INT_8821C BIT(20)
+#define BIT_GPIO3_INT_8821C BIT(19)
+#define BIT_GPIO2_INT_V1_8821C BIT(18)
+#define BIT_GPIO1_INT_8821C BIT(17)
+#define BIT_GPIO0_INT_8821C BIT(16)
+#define BIT_PDNINT_8821C BIT(7)
+#define BIT_RON_INT_8821C BIT(6)
+#define BIT_SPS_OCP_INT_8821C BIT(5)
+#define BIT_GPIO15_0_INT_8821C BIT(0)
+
+/* 2 REG_GPIO_EXT_CTRL_8821C */
+
+#define BIT_SHIFT_GPIO_MOD_15_TO_8_8821C 24
+#define BIT_MASK_GPIO_MOD_15_TO_8_8821C 0xff
+#define BIT_GPIO_MOD_15_TO_8_8821C(x)                                          \
+	(((x) & BIT_MASK_GPIO_MOD_15_TO_8_8821C)                               \
+	 << BIT_SHIFT_GPIO_MOD_15_TO_8_8821C)
+#define BITS_GPIO_MOD_15_TO_8_8821C                                            \
+	(BIT_MASK_GPIO_MOD_15_TO_8_8821C << BIT_SHIFT_GPIO_MOD_15_TO_8_8821C)
+#define BIT_CLEAR_GPIO_MOD_15_TO_8_8821C(x)                                    \
+	((x) & (~BITS_GPIO_MOD_15_TO_8_8821C))
+#define BIT_GET_GPIO_MOD_15_TO_8_8821C(x)                                      \
+	(((x) >> BIT_SHIFT_GPIO_MOD_15_TO_8_8821C) &                           \
+	 BIT_MASK_GPIO_MOD_15_TO_8_8821C)
+#define BIT_SET_GPIO_MOD_15_TO_8_8821C(x, v)                                   \
+	(BIT_CLEAR_GPIO_MOD_15_TO_8_8821C(x) | BIT_GPIO_MOD_15_TO_8_8821C(v))
+
+#define BIT_SHIFT_GPIO_IO_SEL_15_TO_8_8821C 16
+#define BIT_MASK_GPIO_IO_SEL_15_TO_8_8821C 0xff
+#define BIT_GPIO_IO_SEL_15_TO_8_8821C(x)                                       \
+	(((x) & BIT_MASK_GPIO_IO_SEL_15_TO_8_8821C)                            \
+	 << BIT_SHIFT_GPIO_IO_SEL_15_TO_8_8821C)
+#define BITS_GPIO_IO_SEL_15_TO_8_8821C                                         \
+	(BIT_MASK_GPIO_IO_SEL_15_TO_8_8821C                                    \
+	 << BIT_SHIFT_GPIO_IO_SEL_15_TO_8_8821C)
+#define BIT_CLEAR_GPIO_IO_SEL_15_TO_8_8821C(x)                                 \
+	((x) & (~BITS_GPIO_IO_SEL_15_TO_8_8821C))
+#define BIT_GET_GPIO_IO_SEL_15_TO_8_8821C(x)                                   \
+	(((x) >> BIT_SHIFT_GPIO_IO_SEL_15_TO_8_8821C) &                        \
+	 BIT_MASK_GPIO_IO_SEL_15_TO_8_8821C)
+#define BIT_SET_GPIO_IO_SEL_15_TO_8_8821C(x, v)                                \
+	(BIT_CLEAR_GPIO_IO_SEL_15_TO_8_8821C(x) |                              \
+	 BIT_GPIO_IO_SEL_15_TO_8_8821C(v))
+
+#define BIT_SHIFT_GPIO_OUT_15_TO_8_8821C 8
+#define BIT_MASK_GPIO_OUT_15_TO_8_8821C 0xff
+#define BIT_GPIO_OUT_15_TO_8_8821C(x)                                          \
+	(((x) & BIT_MASK_GPIO_OUT_15_TO_8_8821C)                               \
+	 << BIT_SHIFT_GPIO_OUT_15_TO_8_8821C)
+#define BITS_GPIO_OUT_15_TO_8_8821C                                            \
+	(BIT_MASK_GPIO_OUT_15_TO_8_8821C << BIT_SHIFT_GPIO_OUT_15_TO_8_8821C)
+#define BIT_CLEAR_GPIO_OUT_15_TO_8_8821C(x)                                    \
+	((x) & (~BITS_GPIO_OUT_15_TO_8_8821C))
+#define BIT_GET_GPIO_OUT_15_TO_8_8821C(x)                                      \
+	(((x) >> BIT_SHIFT_GPIO_OUT_15_TO_8_8821C) &                           \
+	 BIT_MASK_GPIO_OUT_15_TO_8_8821C)
+#define BIT_SET_GPIO_OUT_15_TO_8_8821C(x, v)                                   \
+	(BIT_CLEAR_GPIO_OUT_15_TO_8_8821C(x) | BIT_GPIO_OUT_15_TO_8_8821C(v))
+
+#define BIT_SHIFT_GPIO_IN_15_TO_8_8821C 0
+#define BIT_MASK_GPIO_IN_15_TO_8_8821C 0xff
+#define BIT_GPIO_IN_15_TO_8_8821C(x)                                           \
+	(((x) & BIT_MASK_GPIO_IN_15_TO_8_8821C)                                \
+	 << BIT_SHIFT_GPIO_IN_15_TO_8_8821C)
+#define BITS_GPIO_IN_15_TO_8_8821C                                             \
+	(BIT_MASK_GPIO_IN_15_TO_8_8821C << BIT_SHIFT_GPIO_IN_15_TO_8_8821C)
+#define BIT_CLEAR_GPIO_IN_15_TO_8_8821C(x) ((x) & (~BITS_GPIO_IN_15_TO_8_8821C))
+#define BIT_GET_GPIO_IN_15_TO_8_8821C(x)                                       \
+	(((x) >> BIT_SHIFT_GPIO_IN_15_TO_8_8821C) &                            \
+	 BIT_MASK_GPIO_IN_15_TO_8_8821C)
+#define BIT_SET_GPIO_IN_15_TO_8_8821C(x, v)                                    \
+	(BIT_CLEAR_GPIO_IN_15_TO_8_8821C(x) | BIT_GPIO_IN_15_TO_8_8821C(v))
+
+/* 2 REG_PAD_CTRL1_8821C */
+#define BIT_PAPE_WLBT_SEL_8821C BIT(29)
+#define BIT_LNAON_WLBT_SEL_8821C BIT(28)
+#define BIT_BTGP_GPG3_FEN_8821C BIT(26)
+#define BIT_BTGP_GPG2_FEN_8821C BIT(25)
+#define BIT_BTGP_JTAG_EN_8821C BIT(24)
+#define BIT_XTAL_CLK_EXTARNAL_EN_8821C BIT(23)
+#define BIT_BTGP_UART0_EN_8821C BIT(22)
+#define BIT_BTGP_UART1_EN_8821C BIT(21)
+#define BIT_BTGP_SPI_EN_8821C BIT(20)
+#define BIT_BTGP_GPIO_E2_8821C BIT(19)
+#define BIT_BTGP_GPIO_EN_8821C BIT(18)
+
+#define BIT_SHIFT_BTGP_GPIO_SL_8821C 16
+#define BIT_MASK_BTGP_GPIO_SL_8821C 0x3
+#define BIT_BTGP_GPIO_SL_8821C(x)                                              \
+	(((x) & BIT_MASK_BTGP_GPIO_SL_8821C) << BIT_SHIFT_BTGP_GPIO_SL_8821C)
+#define BITS_BTGP_GPIO_SL_8821C                                                \
+	(BIT_MASK_BTGP_GPIO_SL_8821C << BIT_SHIFT_BTGP_GPIO_SL_8821C)
+#define BIT_CLEAR_BTGP_GPIO_SL_8821C(x) ((x) & (~BITS_BTGP_GPIO_SL_8821C))
+#define BIT_GET_BTGP_GPIO_SL_8821C(x)                                          \
+	(((x) >> BIT_SHIFT_BTGP_GPIO_SL_8821C) & BIT_MASK_BTGP_GPIO_SL_8821C)
+#define BIT_SET_BTGP_GPIO_SL_8821C(x, v)                                       \
+	(BIT_CLEAR_BTGP_GPIO_SL_8821C(x) | BIT_BTGP_GPIO_SL_8821C(v))
+
+#define BIT_PAD_SDIO_SR_8821C BIT(14)
+#define BIT_GPIO14_OUTPUT_PL_8821C BIT(13)
+#define BIT_HOST_WAKE_PAD_PULL_EN_8821C BIT(12)
+#define BIT_HOST_WAKE_PAD_SL_8821C BIT(11)
+#define BIT_PAD_LNAON_SR_8821C BIT(10)
+#define BIT_PAD_LNAON_E2_8821C BIT(9)
+#define BIT_SW_LNAON_G_SEL_DATA_8821C BIT(8)
+#define BIT_SW_LNAON_A_SEL_DATA_8821C BIT(7)
+#define BIT_PAD_PAPE_SR_8821C BIT(6)
+#define BIT_PAD_PAPE_E2_8821C BIT(5)
+#define BIT_SW_PAPE_G_SEL_DATA_8821C BIT(4)
+#define BIT_SW_PAPE_A_SEL_DATA_8821C BIT(3)
+#define BIT_PAD_DPDT_SR_8821C BIT(2)
+#define BIT_PAD_DPDT_PAD_E2_8821C BIT(1)
+#define BIT_SW_DPDT_SEL_DATA_8821C BIT(0)
+
+/* 2 REG_WL_BT_PWR_CTRL_8821C */
+#define BIT_ISO_BD2PP_8821C BIT(31)
+#define BIT_LDOV12B_EN_8821C BIT(30)
+#define BIT_CKEN_BTGPS_8821C BIT(29)
+#define BIT_FEN_BTGPS_8821C BIT(28)
+#define BIT_BTCPU_BOOTSEL_8821C BIT(27)
+#define BIT_SPI_SPEEDUP_8821C BIT(26)
+#define BIT_DEVWAKE_PAD_TYPE_SEL_8821C BIT(24)
+#define BIT_CLKREQ_PAD_TYPE_SEL_8821C BIT(23)
+#define BIT_ISO_BTPON2PP_8821C BIT(22)
+#define BIT_BT_HWROF_EN_8821C BIT(19)
+#define BIT_BT_FUNC_EN_8821C BIT(18)
+#define BIT_BT_HWPDN_SL_8821C BIT(17)
+#define BIT_BT_DISN_EN_8821C BIT(16)
+#define BIT_BT_PDN_PULL_EN_8821C BIT(15)
+#define BIT_WL_PDN_PULL_EN_8821C BIT(14)
+#define BIT_EXTERNAL_REQUEST_PL_8821C BIT(13)
+#define BIT_GPIO0_2_3_PULL_LOW_EN_8821C BIT(12)
+#define BIT_ISO_BA2PP_8821C BIT(11)
+#define BIT_BT_AFE_LDO_EN_8821C BIT(10)
+#define BIT_BT_AFE_PLL_EN_8821C BIT(9)
+#define BIT_BT_DIG_CLK_EN_8821C BIT(8)
+#define BIT_WL_DRV_EXIST_IDX_8821C BIT(5)
+#define BIT_DOP_EHPAD_8821C BIT(4)
+#define BIT_WL_HWROF_EN_8821C BIT(3)
+#define BIT_WL_FUNC_EN_8821C BIT(2)
+#define BIT_WL_HWPDN_SL_8821C BIT(1)
+#define BIT_WL_HWPDN_EN_8821C BIT(0)
+
+/* 2 REG_SDM_DEBUG_8821C */
+
+#define BIT_SHIFT_WLCLK_PHASE_8821C 0
+#define BIT_MASK_WLCLK_PHASE_8821C 0x1f
+#define BIT_WLCLK_PHASE_8821C(x)                                               \
+	(((x) & BIT_MASK_WLCLK_PHASE_8821C) << BIT_SHIFT_WLCLK_PHASE_8821C)
+#define BITS_WLCLK_PHASE_8821C                                                 \
+	(BIT_MASK_WLCLK_PHASE_8821C << BIT_SHIFT_WLCLK_PHASE_8821C)
+#define BIT_CLEAR_WLCLK_PHASE_8821C(x) ((x) & (~BITS_WLCLK_PHASE_8821C))
+#define BIT_GET_WLCLK_PHASE_8821C(x)                                           \
+	(((x) >> BIT_SHIFT_WLCLK_PHASE_8821C) & BIT_MASK_WLCLK_PHASE_8821C)
+#define BIT_SET_WLCLK_PHASE_8821C(x, v)                                        \
+	(BIT_CLEAR_WLCLK_PHASE_8821C(x) | BIT_WLCLK_PHASE_8821C(v))
+
+/* 2 REG_SYS_SDIO_CTRL_8821C */
+#define BIT_DBG_GNT_WL_BT_8821C BIT(27)
+#define BIT_LTE_MUX_CTRL_PATH_8821C BIT(26)
+#define BIT_LTE_COEX_UART_8821C BIT(25)
+#define BIT_3W_LTE_WL_GPIO_8821C BIT(24)
+#define BIT_SDIO_INT_POLARITY_8821C BIT(19)
+#define BIT_SDIO_INT_8821C BIT(18)
+#define BIT_SDIO_OFF_EN_8821C BIT(17)
+#define BIT_SDIO_ON_EN_8821C BIT(16)
+#define BIT_PCIE_WAIT_TIMEOUT_EVENT_8821C BIT(10)
+#define BIT_PCIE_WAIT_TIME_8821C BIT(9)
+#define BIT_MPCIE_REFCLK_XTAL_SEL_8821C BIT(8)
+#define BIT_RES_USB_MASS_STORAGE_DESC_8821C BIT(1)
+#define BIT_USB_WAIT_TIME_8821C BIT(0)
+
+/* 2 REG_HCI_OPT_CTRL_8821C */
+
+#define BIT_SHIFT_TSFT_SEL_8821C 29
+#define BIT_MASK_TSFT_SEL_8821C 0x7
+#define BIT_TSFT_SEL_8821C(x)                                                  \
+	(((x) & BIT_MASK_TSFT_SEL_8821C) << BIT_SHIFT_TSFT_SEL_8821C)
+#define BITS_TSFT_SEL_8821C                                                    \
+	(BIT_MASK_TSFT_SEL_8821C << BIT_SHIFT_TSFT_SEL_8821C)
+#define BIT_CLEAR_TSFT_SEL_8821C(x) ((x) & (~BITS_TSFT_SEL_8821C))
+#define BIT_GET_TSFT_SEL_8821C(x)                                              \
+	(((x) >> BIT_SHIFT_TSFT_SEL_8821C) & BIT_MASK_TSFT_SEL_8821C)
+#define BIT_SET_TSFT_SEL_8821C(x, v)                                           \
+	(BIT_CLEAR_TSFT_SEL_8821C(x) | BIT_TSFT_SEL_8821C(v))
+
+#define BIT_SDIO_PAD_E5_8821C BIT(18)
+#define BIT_USB_HOST_PWR_OFF_EN_8821C BIT(12)
+#define BIT_SYM_LPS_BLOCK_EN_8821C BIT(11)
+#define BIT_USB_LPM_ACT_EN_8821C BIT(10)
+#define BIT_USB_LPM_NY_8821C BIT(9)
+#define BIT_USB_SUS_DIS_8821C BIT(8)
+
+#define BIT_SHIFT_SDIO_PAD_E_8821C 5
+#define BIT_MASK_SDIO_PAD_E_8821C 0x7
+#define BIT_SDIO_PAD_E_8821C(x)                                                \
+	(((x) & BIT_MASK_SDIO_PAD_E_8821C) << BIT_SHIFT_SDIO_PAD_E_8821C)
+#define BITS_SDIO_PAD_E_8821C                                                  \
+	(BIT_MASK_SDIO_PAD_E_8821C << BIT_SHIFT_SDIO_PAD_E_8821C)
+#define BIT_CLEAR_SDIO_PAD_E_8821C(x) ((x) & (~BITS_SDIO_PAD_E_8821C))
+#define BIT_GET_SDIO_PAD_E_8821C(x)                                            \
+	(((x) >> BIT_SHIFT_SDIO_PAD_E_8821C) & BIT_MASK_SDIO_PAD_E_8821C)
+#define BIT_SET_SDIO_PAD_E_8821C(x, v)                                         \
+	(BIT_CLEAR_SDIO_PAD_E_8821C(x) | BIT_SDIO_PAD_E_8821C(v))
+
+#define BIT_USB_LPPLL_EN_8821C BIT(4)
+#define BIT_ROP_SW15_8821C BIT(2)
+#define BIT_PCI_CKRDY_OPT_8821C BIT(1)
+#define BIT_PCI_VAUX_EN_8821C BIT(0)
+
+/* 2 REG_AFE_CTRL4_8821C */
+
+/* 2 REG_LDO_SWR_CTRL_8821C */
+#define BIT_ZCD_HW_AUTO_EN_8821C BIT(27)
+#define BIT_ZCD_REGSEL_8821C BIT(26)
+
+#define BIT_SHIFT_AUTO_ZCD_IN_CODE_8821C 21
+#define BIT_MASK_AUTO_ZCD_IN_CODE_8821C 0x1f
+#define BIT_AUTO_ZCD_IN_CODE_8821C(x)                                          \
+	(((x) & BIT_MASK_AUTO_ZCD_IN_CODE_8821C)                               \
+	 << BIT_SHIFT_AUTO_ZCD_IN_CODE_8821C)
+#define BITS_AUTO_ZCD_IN_CODE_8821C                                            \
+	(BIT_MASK_AUTO_ZCD_IN_CODE_8821C << BIT_SHIFT_AUTO_ZCD_IN_CODE_8821C)
+#define BIT_CLEAR_AUTO_ZCD_IN_CODE_8821C(x)                                    \
+	((x) & (~BITS_AUTO_ZCD_IN_CODE_8821C))
+#define BIT_GET_AUTO_ZCD_IN_CODE_8821C(x)                                      \
+	(((x) >> BIT_SHIFT_AUTO_ZCD_IN_CODE_8821C) &                           \
+	 BIT_MASK_AUTO_ZCD_IN_CODE_8821C)
+#define BIT_SET_AUTO_ZCD_IN_CODE_8821C(x, v)                                   \
+	(BIT_CLEAR_AUTO_ZCD_IN_CODE_8821C(x) | BIT_AUTO_ZCD_IN_CODE_8821C(v))
+
+#define BIT_SHIFT_ZCD_CODE_IN_L_8821C 16
+#define BIT_MASK_ZCD_CODE_IN_L_8821C 0x1f
+#define BIT_ZCD_CODE_IN_L_8821C(x)                                             \
+	(((x) & BIT_MASK_ZCD_CODE_IN_L_8821C) << BIT_SHIFT_ZCD_CODE_IN_L_8821C)
+#define BITS_ZCD_CODE_IN_L_8821C                                               \
+	(BIT_MASK_ZCD_CODE_IN_L_8821C << BIT_SHIFT_ZCD_CODE_IN_L_8821C)
+#define BIT_CLEAR_ZCD_CODE_IN_L_8821C(x) ((x) & (~BITS_ZCD_CODE_IN_L_8821C))
+#define BIT_GET_ZCD_CODE_IN_L_8821C(x)                                         \
+	(((x) >> BIT_SHIFT_ZCD_CODE_IN_L_8821C) & BIT_MASK_ZCD_CODE_IN_L_8821C)
+#define BIT_SET_ZCD_CODE_IN_L_8821C(x, v)                                      \
+	(BIT_CLEAR_ZCD_CODE_IN_L_8821C(x) | BIT_ZCD_CODE_IN_L_8821C(v))
+
+#define BIT_SHIFT_LDO_HV5_DUMMY_8821C 14
+#define BIT_MASK_LDO_HV5_DUMMY_8821C 0x3
+#define BIT_LDO_HV5_DUMMY_8821C(x)                                             \
+	(((x) & BIT_MASK_LDO_HV5_DUMMY_8821C) << BIT_SHIFT_LDO_HV5_DUMMY_8821C)
+#define BITS_LDO_HV5_DUMMY_8821C                                               \
+	(BIT_MASK_LDO_HV5_DUMMY_8821C << BIT_SHIFT_LDO_HV5_DUMMY_8821C)
+#define BIT_CLEAR_LDO_HV5_DUMMY_8821C(x) ((x) & (~BITS_LDO_HV5_DUMMY_8821C))
+#define BIT_GET_LDO_HV5_DUMMY_8821C(x)                                         \
+	(((x) >> BIT_SHIFT_LDO_HV5_DUMMY_8821C) & BIT_MASK_LDO_HV5_DUMMY_8821C)
+#define BIT_SET_LDO_HV5_DUMMY_8821C(x, v)                                      \
+	(BIT_CLEAR_LDO_HV5_DUMMY_8821C(x) | BIT_LDO_HV5_DUMMY_8821C(v))
+
+#define BIT_SHIFT_REG_VTUNE33_BIT0_TO_BIT1_8821C 12
+#define BIT_MASK_REG_VTUNE33_BIT0_TO_BIT1_8821C 0x3
+#define BIT_REG_VTUNE33_BIT0_TO_BIT1_8821C(x)                                  \
+	(((x) & BIT_MASK_REG_VTUNE33_BIT0_TO_BIT1_8821C)                       \
+	 << BIT_SHIFT_REG_VTUNE33_BIT0_TO_BIT1_8821C)
+#define BITS_REG_VTUNE33_BIT0_TO_BIT1_8821C                                    \
+	(BIT_MASK_REG_VTUNE33_BIT0_TO_BIT1_8821C                               \
+	 << BIT_SHIFT_REG_VTUNE33_BIT0_TO_BIT1_8821C)
+#define BIT_CLEAR_REG_VTUNE33_BIT0_TO_BIT1_8821C(x)                            \
+	((x) & (~BITS_REG_VTUNE33_BIT0_TO_BIT1_8821C))
+#define BIT_GET_REG_VTUNE33_BIT0_TO_BIT1_8821C(x)                              \
+	(((x) >> BIT_SHIFT_REG_VTUNE33_BIT0_TO_BIT1_8821C) &                   \
+	 BIT_MASK_REG_VTUNE33_BIT0_TO_BIT1_8821C)
+#define BIT_SET_REG_VTUNE33_BIT0_TO_BIT1_8821C(x, v)                           \
+	(BIT_CLEAR_REG_VTUNE33_BIT0_TO_BIT1_8821C(x) |                         \
+	 BIT_REG_VTUNE33_BIT0_TO_BIT1_8821C(v))
+
+#define BIT_SHIFT_REG_STANDBY33_BIT0_TO_BIT1_8821C 10
+#define BIT_MASK_REG_STANDBY33_BIT0_TO_BIT1_8821C 0x3
+#define BIT_REG_STANDBY33_BIT0_TO_BIT1_8821C(x)                                \
+	(((x) & BIT_MASK_REG_STANDBY33_BIT0_TO_BIT1_8821C)                     \
+	 << BIT_SHIFT_REG_STANDBY33_BIT0_TO_BIT1_8821C)
+#define BITS_REG_STANDBY33_BIT0_TO_BIT1_8821C                                  \
+	(BIT_MASK_REG_STANDBY33_BIT0_TO_BIT1_8821C                             \
+	 << BIT_SHIFT_REG_STANDBY33_BIT0_TO_BIT1_8821C)
+#define BIT_CLEAR_REG_STANDBY33_BIT0_TO_BIT1_8821C(x)                          \
+	((x) & (~BITS_REG_STANDBY33_BIT0_TO_BIT1_8821C))
+#define BIT_GET_REG_STANDBY33_BIT0_TO_BIT1_8821C(x)                            \
+	(((x) >> BIT_SHIFT_REG_STANDBY33_BIT0_TO_BIT1_8821C) &                 \
+	 BIT_MASK_REG_STANDBY33_BIT0_TO_BIT1_8821C)
+#define BIT_SET_REG_STANDBY33_BIT0_TO_BIT1_8821C(x, v)                         \
+	(BIT_CLEAR_REG_STANDBY33_BIT0_TO_BIT1_8821C(x) |                       \
+	 BIT_REG_STANDBY33_BIT0_TO_BIT1_8821C(v))
+
+#define BIT_SHIFT_REG_LOAD33_BIT0_TO_BIT1_8821C 8
+#define BIT_MASK_REG_LOAD33_BIT0_TO_BIT1_8821C 0x3
+#define BIT_REG_LOAD33_BIT0_TO_BIT1_8821C(x)                                   \
+	(((x) & BIT_MASK_REG_LOAD33_BIT0_TO_BIT1_8821C)                        \
+	 << BIT_SHIFT_REG_LOAD33_BIT0_TO_BIT1_8821C)
+#define BITS_REG_LOAD33_BIT0_TO_BIT1_8821C                                     \
+	(BIT_MASK_REG_LOAD33_BIT0_TO_BIT1_8821C                                \
+	 << BIT_SHIFT_REG_LOAD33_BIT0_TO_BIT1_8821C)
+#define BIT_CLEAR_REG_LOAD33_BIT0_TO_BIT1_8821C(x)                             \
+	((x) & (~BITS_REG_LOAD33_BIT0_TO_BIT1_8821C))
+#define BIT_GET_REG_LOAD33_BIT0_TO_BIT1_8821C(x)                               \
+	(((x) >> BIT_SHIFT_REG_LOAD33_BIT0_TO_BIT1_8821C) &                    \
+	 BIT_MASK_REG_LOAD33_BIT0_TO_BIT1_8821C)
+#define BIT_SET_REG_LOAD33_BIT0_TO_BIT1_8821C(x, v)                            \
+	(BIT_CLEAR_REG_LOAD33_BIT0_TO_BIT1_8821C(x) |                          \
+	 BIT_REG_LOAD33_BIT0_TO_BIT1_8821C(v))
+
+#define BIT_REG_BYPASS_L_8821C BIT(7)
+#define BIT_REG_LDOF_L_8821C BIT(6)
+#define BIT_REG_OCPS_L_8821C BIT(5)
+#define BIT_ARENB_L_8821C BIT(3)
+
+#define BIT_SHIFT_CFC_L_8821C 1
+#define BIT_MASK_CFC_L_8821C 0x3
+#define BIT_CFC_L_8821C(x)                                                     \
+	(((x) & BIT_MASK_CFC_L_8821C) << BIT_SHIFT_CFC_L_8821C)
+#define BITS_CFC_L_8821C (BIT_MASK_CFC_L_8821C << BIT_SHIFT_CFC_L_8821C)
+#define BIT_CLEAR_CFC_L_8821C(x) ((x) & (~BITS_CFC_L_8821C))
+#define BIT_GET_CFC_L_8821C(x)                                                 \
+	(((x) >> BIT_SHIFT_CFC_L_8821C) & BIT_MASK_CFC_L_8821C)
+#define BIT_SET_CFC_L_8821C(x, v)                                              \
+	(BIT_CLEAR_CFC_L_8821C(x) | BIT_CFC_L_8821C(v))
+
+#define BIT_REG_TYPE_L_8821C BIT(0)
+
+/* 2 REG_MCUFW_CTRL_8821C */
+
+#define BIT_SHIFT_RPWM_8821C 24
+#define BIT_MASK_RPWM_8821C 0xff
+#define BIT_RPWM_8821C(x) (((x) & BIT_MASK_RPWM_8821C) << BIT_SHIFT_RPWM_8821C)
+#define BITS_RPWM_8821C (BIT_MASK_RPWM_8821C << BIT_SHIFT_RPWM_8821C)
+#define BIT_CLEAR_RPWM_8821C(x) ((x) & (~BITS_RPWM_8821C))
+#define BIT_GET_RPWM_8821C(x)                                                  \
+	(((x) >> BIT_SHIFT_RPWM_8821C) & BIT_MASK_RPWM_8821C)
+#define BIT_SET_RPWM_8821C(x, v) (BIT_CLEAR_RPWM_8821C(x) | BIT_RPWM_8821C(v))
+
+#define BIT_ANA_PORT_EN_8821C BIT(22)
+#define BIT_MAC_PORT_EN_8821C BIT(21)
+#define BIT_BOOT_FSPI_EN_8821C BIT(20)
+#define BIT_ROM_DLEN_8821C BIT(19)
+
+#define BIT_SHIFT_ROM_PGE_8821C 16
+#define BIT_MASK_ROM_PGE_8821C 0x7
+#define BIT_ROM_PGE_8821C(x)                                                   \
+	(((x) & BIT_MASK_ROM_PGE_8821C) << BIT_SHIFT_ROM_PGE_8821C)
+#define BITS_ROM_PGE_8821C (BIT_MASK_ROM_PGE_8821C << BIT_SHIFT_ROM_PGE_8821C)
+#define BIT_CLEAR_ROM_PGE_8821C(x) ((x) & (~BITS_ROM_PGE_8821C))
+#define BIT_GET_ROM_PGE_8821C(x)                                               \
+	(((x) >> BIT_SHIFT_ROM_PGE_8821C) & BIT_MASK_ROM_PGE_8821C)
+#define BIT_SET_ROM_PGE_8821C(x, v)                                            \
+	(BIT_CLEAR_ROM_PGE_8821C(x) | BIT_ROM_PGE_8821C(v))
+
+#define BIT_FW_INIT_RDY_8821C BIT(15)
+#define BIT_FW_DW_RDY_8821C BIT(14)
+
+#define BIT_SHIFT_CPU_CLK_SEL_8821C 12
+#define BIT_MASK_CPU_CLK_SEL_8821C 0x3
+#define BIT_CPU_CLK_SEL_8821C(x)                                               \
+	(((x) & BIT_MASK_CPU_CLK_SEL_8821C) << BIT_SHIFT_CPU_CLK_SEL_8821C)
+#define BITS_CPU_CLK_SEL_8821C                                                 \
+	(BIT_MASK_CPU_CLK_SEL_8821C << BIT_SHIFT_CPU_CLK_SEL_8821C)
+#define BIT_CLEAR_CPU_CLK_SEL_8821C(x) ((x) & (~BITS_CPU_CLK_SEL_8821C))
+#define BIT_GET_CPU_CLK_SEL_8821C(x)                                           \
+	(((x) >> BIT_SHIFT_CPU_CLK_SEL_8821C) & BIT_MASK_CPU_CLK_SEL_8821C)
+#define BIT_SET_CPU_CLK_SEL_8821C(x, v)                                        \
+	(BIT_CLEAR_CPU_CLK_SEL_8821C(x) | BIT_CPU_CLK_SEL_8821C(v))
+
+#define BIT_CCLK_CHG_MASK_8821C BIT(11)
+#define BIT_EMEM__TXBUF_CHKSUM_OK_8821C BIT(10)
+#define BIT_EMEM_TXBUF_DW_RDY_8821C BIT(9)
+#define BIT_EMEM_CHKSUM_OK_8821C BIT(8)
+#define BIT_EMEM_DW_OK_8821C BIT(7)
+#define BIT_DMEM_CHKSUM_OK_8821C BIT(6)
+#define BIT_DMEM_DW_OK_8821C BIT(5)
+#define BIT_IMEM_CHKSUM_OK_8821C BIT(4)
+#define BIT_IMEM_DW_OK_8821C BIT(3)
+#define BIT_IMEM_BOOT_LOAD_CHKSUM_OK_8821C BIT(2)
+#define BIT_IMEM_BOOT_LOAD_DW_OK_8821C BIT(1)
+#define BIT_MCUFWDL_EN_8821C BIT(0)
+
+/* 2 REG_MCU_TST_CFG_8821C */
+
+#define BIT_SHIFT_C2H_MSG_8821C 0
+#define BIT_MASK_C2H_MSG_8821C 0xffff
+#define BIT_C2H_MSG_8821C(x)                                                   \
+	(((x) & BIT_MASK_C2H_MSG_8821C) << BIT_SHIFT_C2H_MSG_8821C)
+#define BITS_C2H_MSG_8821C (BIT_MASK_C2H_MSG_8821C << BIT_SHIFT_C2H_MSG_8821C)
+#define BIT_CLEAR_C2H_MSG_8821C(x) ((x) & (~BITS_C2H_MSG_8821C))
+#define BIT_GET_C2H_MSG_8821C(x)                                               \
+	(((x) >> BIT_SHIFT_C2H_MSG_8821C) & BIT_MASK_C2H_MSG_8821C)
+#define BIT_SET_C2H_MSG_8821C(x, v)                                            \
+	(BIT_CLEAR_C2H_MSG_8821C(x) | BIT_C2H_MSG_8821C(v))
+
+/* 2 REG_HMEBOX_E0_E1_8821C */
+
+#define BIT_SHIFT_HOST_MSG_E1_8821C 16
+#define BIT_MASK_HOST_MSG_E1_8821C 0xffff
+#define BIT_HOST_MSG_E1_8821C(x)                                               \
+	(((x) & BIT_MASK_HOST_MSG_E1_8821C) << BIT_SHIFT_HOST_MSG_E1_8821C)
+#define BITS_HOST_MSG_E1_8821C                                                 \
+	(BIT_MASK_HOST_MSG_E1_8821C << BIT_SHIFT_HOST_MSG_E1_8821C)
+#define BIT_CLEAR_HOST_MSG_E1_8821C(x) ((x) & (~BITS_HOST_MSG_E1_8821C))
+#define BIT_GET_HOST_MSG_E1_8821C(x)                                           \
+	(((x) >> BIT_SHIFT_HOST_MSG_E1_8821C) & BIT_MASK_HOST_MSG_E1_8821C)
+#define BIT_SET_HOST_MSG_E1_8821C(x, v)                                        \
+	(BIT_CLEAR_HOST_MSG_E1_8821C(x) | BIT_HOST_MSG_E1_8821C(v))
+
+#define BIT_SHIFT_HOST_MSG_E0_8821C 0
+#define BIT_MASK_HOST_MSG_E0_8821C 0xffff
+#define BIT_HOST_MSG_E0_8821C(x)                                               \
+	(((x) & BIT_MASK_HOST_MSG_E0_8821C) << BIT_SHIFT_HOST_MSG_E0_8821C)
+#define BITS_HOST_MSG_E0_8821C                                                 \
+	(BIT_MASK_HOST_MSG_E0_8821C << BIT_SHIFT_HOST_MSG_E0_8821C)
+#define BIT_CLEAR_HOST_MSG_E0_8821C(x) ((x) & (~BITS_HOST_MSG_E0_8821C))
+#define BIT_GET_HOST_MSG_E0_8821C(x)                                           \
+	(((x) >> BIT_SHIFT_HOST_MSG_E0_8821C) & BIT_MASK_HOST_MSG_E0_8821C)
+#define BIT_SET_HOST_MSG_E0_8821C(x, v)                                        \
+	(BIT_CLEAR_HOST_MSG_E0_8821C(x) | BIT_HOST_MSG_E0_8821C(v))
+
+/* 2 REG_HMEBOX_E2_E3_8821C */
+
+#define BIT_SHIFT_HOST_MSG_E3_8821C 16
+#define BIT_MASK_HOST_MSG_E3_8821C 0xffff
+#define BIT_HOST_MSG_E3_8821C(x)                                               \
+	(((x) & BIT_MASK_HOST_MSG_E3_8821C) << BIT_SHIFT_HOST_MSG_E3_8821C)
+#define BITS_HOST_MSG_E3_8821C                                                 \
+	(BIT_MASK_HOST_MSG_E3_8821C << BIT_SHIFT_HOST_MSG_E3_8821C)
+#define BIT_CLEAR_HOST_MSG_E3_8821C(x) ((x) & (~BITS_HOST_MSG_E3_8821C))
+#define BIT_GET_HOST_MSG_E3_8821C(x)                                           \
+	(((x) >> BIT_SHIFT_HOST_MSG_E3_8821C) & BIT_MASK_HOST_MSG_E3_8821C)
+#define BIT_SET_HOST_MSG_E3_8821C(x, v)                                        \
+	(BIT_CLEAR_HOST_MSG_E3_8821C(x) | BIT_HOST_MSG_E3_8821C(v))
+
+#define BIT_SHIFT_HOST_MSG_E2_8821C 0
+#define BIT_MASK_HOST_MSG_E2_8821C 0xffff
+#define BIT_HOST_MSG_E2_8821C(x)                                               \
+	(((x) & BIT_MASK_HOST_MSG_E2_8821C) << BIT_SHIFT_HOST_MSG_E2_8821C)
+#define BITS_HOST_MSG_E2_8821C                                                 \
+	(BIT_MASK_HOST_MSG_E2_8821C << BIT_SHIFT_HOST_MSG_E2_8821C)
+#define BIT_CLEAR_HOST_MSG_E2_8821C(x) ((x) & (~BITS_HOST_MSG_E2_8821C))
+#define BIT_GET_HOST_MSG_E2_8821C(x)                                           \
+	(((x) >> BIT_SHIFT_HOST_MSG_E2_8821C) & BIT_MASK_HOST_MSG_E2_8821C)
+#define BIT_SET_HOST_MSG_E2_8821C(x, v)                                        \
+	(BIT_CLEAR_HOST_MSG_E2_8821C(x) | BIT_HOST_MSG_E2_8821C(v))
+
+/* 2 REG_WLLPS_CTRL_8821C */
+#define BIT_WLLPSOP_EABM_8821C BIT(31)
+#define BIT_WLLPSOP_ACKF_8821C BIT(30)
+#define BIT_WLLPSOP_DLDM_8821C BIT(29)
+#define BIT_WLLPSOP_ESWR_8821C BIT(28)
+#define BIT_WLLPSOP_PWMM_8821C BIT(27)
+#define BIT_WLLPSOP_EECK_8821C BIT(26)
+#define BIT_WLLPSOP_WLMACOFF_8821C BIT(25)
+#define BIT_WLLPSOP_EXTAL_8821C BIT(24)
+#define BIT_WL_SYNPON_VOLTSPDN_8821C BIT(23)
+#define BIT_WLLPSOP_WLBBOFF_8821C BIT(22)
+#define BIT_WLLPSOP_WLMEM_DS_8821C BIT(21)
+
+#define BIT_SHIFT_LPLDH12_VADJ_STEP_DN_8821C 12
+#define BIT_MASK_LPLDH12_VADJ_STEP_DN_8821C 0xf
+#define BIT_LPLDH12_VADJ_STEP_DN_8821C(x)                                      \
+	(((x) & BIT_MASK_LPLDH12_VADJ_STEP_DN_8821C)                           \
+	 << BIT_SHIFT_LPLDH12_VADJ_STEP_DN_8821C)
+#define BITS_LPLDH12_VADJ_STEP_DN_8821C                                        \
+	(BIT_MASK_LPLDH12_VADJ_STEP_DN_8821C                                   \
+	 << BIT_SHIFT_LPLDH12_VADJ_STEP_DN_8821C)
+#define BIT_CLEAR_LPLDH12_VADJ_STEP_DN_8821C(x)                                \
+	((x) & (~BITS_LPLDH12_VADJ_STEP_DN_8821C))
+#define BIT_GET_LPLDH12_VADJ_STEP_DN_8821C(x)                                  \
+	(((x) >> BIT_SHIFT_LPLDH12_VADJ_STEP_DN_8821C) &                       \
+	 BIT_MASK_LPLDH12_VADJ_STEP_DN_8821C)
+#define BIT_SET_LPLDH12_VADJ_STEP_DN_8821C(x, v)                               \
+	(BIT_CLEAR_LPLDH12_VADJ_STEP_DN_8821C(x) |                             \
+	 BIT_LPLDH12_VADJ_STEP_DN_8821C(v))
+
+#define BIT_SHIFT_V15ADJ_L1_STEP_DN_8821C 8
+#define BIT_MASK_V15ADJ_L1_STEP_DN_8821C 0x7
+#define BIT_V15ADJ_L1_STEP_DN_8821C(x)                                         \
+	(((x) & BIT_MASK_V15ADJ_L1_STEP_DN_8821C)                              \
+	 << BIT_SHIFT_V15ADJ_L1_STEP_DN_8821C)
+#define BITS_V15ADJ_L1_STEP_DN_8821C                                           \
+	(BIT_MASK_V15ADJ_L1_STEP_DN_8821C << BIT_SHIFT_V15ADJ_L1_STEP_DN_8821C)
+#define BIT_CLEAR_V15ADJ_L1_STEP_DN_8821C(x)                                   \
+	((x) & (~BITS_V15ADJ_L1_STEP_DN_8821C))
+#define BIT_GET_V15ADJ_L1_STEP_DN_8821C(x)                                     \
+	(((x) >> BIT_SHIFT_V15ADJ_L1_STEP_DN_8821C) &                          \
+	 BIT_MASK_V15ADJ_L1_STEP_DN_8821C)
+#define BIT_SET_V15ADJ_L1_STEP_DN_8821C(x, v)                                  \
+	(BIT_CLEAR_V15ADJ_L1_STEP_DN_8821C(x) | BIT_V15ADJ_L1_STEP_DN_8821C(v))
+
+#define BIT_REGU_32K_CLK_EN_8821C BIT(1)
+#define BIT_WL_LPS_EN_8821C BIT(0)
+
+/* 2 REG_AFE_CTRL5_8821C */
+#define BIT_BB_DBG_SEL_AFE_SDM_BIT0_8821C BIT(31)
+#define BIT_ORDER_SDM_8821C BIT(30)
+#define BIT_RFE_SEL_SDM_8821C BIT(29)
+
+#define BIT_SHIFT_REF_SEL_8821C 25
+#define BIT_MASK_REF_SEL_8821C 0xf
+#define BIT_REF_SEL_8821C(x)                                                   \
+	(((x) & BIT_MASK_REF_SEL_8821C) << BIT_SHIFT_REF_SEL_8821C)
+#define BITS_REF_SEL_8821C (BIT_MASK_REF_SEL_8821C << BIT_SHIFT_REF_SEL_8821C)
+#define BIT_CLEAR_REF_SEL_8821C(x) ((x) & (~BITS_REF_SEL_8821C))
+#define BIT_GET_REF_SEL_8821C(x)                                               \
+	(((x) >> BIT_SHIFT_REF_SEL_8821C) & BIT_MASK_REF_SEL_8821C)
+#define BIT_SET_REF_SEL_8821C(x, v)                                            \
+	(BIT_CLEAR_REF_SEL_8821C(x) | BIT_REF_SEL_8821C(v))
+
+#define BIT_SHIFT_F0F_SDM_8821C 12
+#define BIT_MASK_F0F_SDM_8821C 0x1fff
+#define BIT_F0F_SDM_8821C(x)                                                   \
+	(((x) & BIT_MASK_F0F_SDM_8821C) << BIT_SHIFT_F0F_SDM_8821C)
+#define BITS_F0F_SDM_8821C (BIT_MASK_F0F_SDM_8821C << BIT_SHIFT_F0F_SDM_8821C)
+#define BIT_CLEAR_F0F_SDM_8821C(x) ((x) & (~BITS_F0F_SDM_8821C))
+#define BIT_GET_F0F_SDM_8821C(x)                                               \
+	(((x) >> BIT_SHIFT_F0F_SDM_8821C) & BIT_MASK_F0F_SDM_8821C)
+#define BIT_SET_F0F_SDM_8821C(x, v)                                            \
+	(BIT_CLEAR_F0F_SDM_8821C(x) | BIT_F0F_SDM_8821C(v))
+
+#define BIT_SHIFT_F0N_SDM_8821C 9
+#define BIT_MASK_F0N_SDM_8821C 0x7
+#define BIT_F0N_SDM_8821C(x)                                                   \
+	(((x) & BIT_MASK_F0N_SDM_8821C) << BIT_SHIFT_F0N_SDM_8821C)
+#define BITS_F0N_SDM_8821C (BIT_MASK_F0N_SDM_8821C << BIT_SHIFT_F0N_SDM_8821C)
+#define BIT_CLEAR_F0N_SDM_8821C(x) ((x) & (~BITS_F0N_SDM_8821C))
+#define BIT_GET_F0N_SDM_8821C(x)                                               \
+	(((x) >> BIT_SHIFT_F0N_SDM_8821C) & BIT_MASK_F0N_SDM_8821C)
+#define BIT_SET_F0N_SDM_8821C(x, v)                                            \
+	(BIT_CLEAR_F0N_SDM_8821C(x) | BIT_F0N_SDM_8821C(v))
+
+#define BIT_SHIFT_DIVN_SDM_8821C 3
+#define BIT_MASK_DIVN_SDM_8821C 0x3f
+#define BIT_DIVN_SDM_8821C(x)                                                  \
+	(((x) & BIT_MASK_DIVN_SDM_8821C) << BIT_SHIFT_DIVN_SDM_8821C)
+#define BITS_DIVN_SDM_8821C                                                    \
+	(BIT_MASK_DIVN_SDM_8821C << BIT_SHIFT_DIVN_SDM_8821C)
+#define BIT_CLEAR_DIVN_SDM_8821C(x) ((x) & (~BITS_DIVN_SDM_8821C))
+#define BIT_GET_DIVN_SDM_8821C(x)                                              \
+	(((x) >> BIT_SHIFT_DIVN_SDM_8821C) & BIT_MASK_DIVN_SDM_8821C)
+#define BIT_SET_DIVN_SDM_8821C(x, v)                                           \
+	(BIT_CLEAR_DIVN_SDM_8821C(x) | BIT_DIVN_SDM_8821C(v))
+
+/* 2 REG_GPIO_DEBOUNCE_CTRL_8821C */
+#define BIT_WLGP_DBC1EN_8821C BIT(15)
+
+#define BIT_SHIFT_WLGP_DBC1_8821C 8
+#define BIT_MASK_WLGP_DBC1_8821C 0xf
+#define BIT_WLGP_DBC1_8821C(x)                                                 \
+	(((x) & BIT_MASK_WLGP_DBC1_8821C) << BIT_SHIFT_WLGP_DBC1_8821C)
+#define BITS_WLGP_DBC1_8821C                                                   \
+	(BIT_MASK_WLGP_DBC1_8821C << BIT_SHIFT_WLGP_DBC1_8821C)
+#define BIT_CLEAR_WLGP_DBC1_8821C(x) ((x) & (~BITS_WLGP_DBC1_8821C))
+#define BIT_GET_WLGP_DBC1_8821C(x)                                             \
+	(((x) >> BIT_SHIFT_WLGP_DBC1_8821C) & BIT_MASK_WLGP_DBC1_8821C)
+#define BIT_SET_WLGP_DBC1_8821C(x, v)                                          \
+	(BIT_CLEAR_WLGP_DBC1_8821C(x) | BIT_WLGP_DBC1_8821C(v))
+
+#define BIT_WLGP_DBC0EN_8821C BIT(7)
+
+#define BIT_SHIFT_WLGP_DBC0_8821C 0
+#define BIT_MASK_WLGP_DBC0_8821C 0xf
+#define BIT_WLGP_DBC0_8821C(x)                                                 \
+	(((x) & BIT_MASK_WLGP_DBC0_8821C) << BIT_SHIFT_WLGP_DBC0_8821C)
+#define BITS_WLGP_DBC0_8821C                                                   \
+	(BIT_MASK_WLGP_DBC0_8821C << BIT_SHIFT_WLGP_DBC0_8821C)
+#define BIT_CLEAR_WLGP_DBC0_8821C(x) ((x) & (~BITS_WLGP_DBC0_8821C))
+#define BIT_GET_WLGP_DBC0_8821C(x)                                             \
+	(((x) >> BIT_SHIFT_WLGP_DBC0_8821C) & BIT_MASK_WLGP_DBC0_8821C)
+#define BIT_SET_WLGP_DBC0_8821C(x, v)                                          \
+	(BIT_CLEAR_WLGP_DBC0_8821C(x) | BIT_WLGP_DBC0_8821C(v))
+
+/* 2 REG_RPWM2_8821C */
+
+#define BIT_SHIFT_RPWM2_8821C 16
+#define BIT_MASK_RPWM2_8821C 0xffff
+#define BIT_RPWM2_8821C(x)                                                     \
+	(((x) & BIT_MASK_RPWM2_8821C) << BIT_SHIFT_RPWM2_8821C)
+#define BITS_RPWM2_8821C (BIT_MASK_RPWM2_8821C << BIT_SHIFT_RPWM2_8821C)
+#define BIT_CLEAR_RPWM2_8821C(x) ((x) & (~BITS_RPWM2_8821C))
+#define BIT_GET_RPWM2_8821C(x)                                                 \
+	(((x) >> BIT_SHIFT_RPWM2_8821C) & BIT_MASK_RPWM2_8821C)
+#define BIT_SET_RPWM2_8821C(x, v)                                              \
+	(BIT_CLEAR_RPWM2_8821C(x) | BIT_RPWM2_8821C(v))
+
+/* 2 REG_SYSON_FSM_MON_8821C */
+
+#define BIT_SHIFT_FSM_MON_SEL_8821C 24
+#define BIT_MASK_FSM_MON_SEL_8821C 0x7
+#define BIT_FSM_MON_SEL_8821C(x)                                               \
+	(((x) & BIT_MASK_FSM_MON_SEL_8821C) << BIT_SHIFT_FSM_MON_SEL_8821C)
+#define BITS_FSM_MON_SEL_8821C                                                 \
+	(BIT_MASK_FSM_MON_SEL_8821C << BIT_SHIFT_FSM_MON_SEL_8821C)
+#define BIT_CLEAR_FSM_MON_SEL_8821C(x) ((x) & (~BITS_FSM_MON_SEL_8821C))
+#define BIT_GET_FSM_MON_SEL_8821C(x)                                           \
+	(((x) >> BIT_SHIFT_FSM_MON_SEL_8821C) & BIT_MASK_FSM_MON_SEL_8821C)
+#define BIT_SET_FSM_MON_SEL_8821C(x, v)                                        \
+	(BIT_CLEAR_FSM_MON_SEL_8821C(x) | BIT_FSM_MON_SEL_8821C(v))
+
+#define BIT_DOP_ELDO_8821C BIT(23)
+#define BIT_FSM_MON_UPD_8821C BIT(15)
+
+#define BIT_SHIFT_FSM_PAR_8821C 0
+#define BIT_MASK_FSM_PAR_8821C 0x7fff
+#define BIT_FSM_PAR_8821C(x)                                                   \
+	(((x) & BIT_MASK_FSM_PAR_8821C) << BIT_SHIFT_FSM_PAR_8821C)
+#define BITS_FSM_PAR_8821C (BIT_MASK_FSM_PAR_8821C << BIT_SHIFT_FSM_PAR_8821C)
+#define BIT_CLEAR_FSM_PAR_8821C(x) ((x) & (~BITS_FSM_PAR_8821C))
+#define BIT_GET_FSM_PAR_8821C(x)                                               \
+	(((x) >> BIT_SHIFT_FSM_PAR_8821C) & BIT_MASK_FSM_PAR_8821C)
+#define BIT_SET_FSM_PAR_8821C(x, v)                                            \
+	(BIT_CLEAR_FSM_PAR_8821C(x) | BIT_FSM_PAR_8821C(v))
+
+/* 2 REG_AFE_CTRL6_8821C */
+
+#define BIT_SHIFT_BB_DBG_SEL_AFE_SDM_BIT3_1_8821C 0
+#define BIT_MASK_BB_DBG_SEL_AFE_SDM_BIT3_1_8821C 0x7
+#define BIT_BB_DBG_SEL_AFE_SDM_BIT3_1_8821C(x)                                 \
+	(((x) & BIT_MASK_BB_DBG_SEL_AFE_SDM_BIT3_1_8821C)                      \
+	 << BIT_SHIFT_BB_DBG_SEL_AFE_SDM_BIT3_1_8821C)
+#define BITS_BB_DBG_SEL_AFE_SDM_BIT3_1_8821C                                   \
+	(BIT_MASK_BB_DBG_SEL_AFE_SDM_BIT3_1_8821C                              \
+	 << BIT_SHIFT_BB_DBG_SEL_AFE_SDM_BIT3_1_8821C)
+#define BIT_CLEAR_BB_DBG_SEL_AFE_SDM_BIT3_1_8821C(x)                           \
+	((x) & (~BITS_BB_DBG_SEL_AFE_SDM_BIT3_1_8821C))
+#define BIT_GET_BB_DBG_SEL_AFE_SDM_BIT3_1_8821C(x)                             \
+	(((x) >> BIT_SHIFT_BB_DBG_SEL_AFE_SDM_BIT3_1_8821C) &                  \
+	 BIT_MASK_BB_DBG_SEL_AFE_SDM_BIT3_1_8821C)
+#define BIT_SET_BB_DBG_SEL_AFE_SDM_BIT3_1_8821C(x, v)                          \
+	(BIT_CLEAR_BB_DBG_SEL_AFE_SDM_BIT3_1_8821C(x) |                        \
+	 BIT_BB_DBG_SEL_AFE_SDM_BIT3_1_8821C(v))
+
+/* 2 REG_PMC_DBG_CTRL1_8821C */
+#define BIT_BT_INT_EN_8821C BIT(31)
+
+#define BIT_SHIFT_RD_WR_WIFI_BT_INFO_8821C 16
+#define BIT_MASK_RD_WR_WIFI_BT_INFO_8821C 0x7fff
+#define BIT_RD_WR_WIFI_BT_INFO_8821C(x)                                        \
+	(((x) & BIT_MASK_RD_WR_WIFI_BT_INFO_8821C)                             \
+	 << BIT_SHIFT_RD_WR_WIFI_BT_INFO_8821C)
+#define BITS_RD_WR_WIFI_BT_INFO_8821C                                          \
+	(BIT_MASK_RD_WR_WIFI_BT_INFO_8821C                                     \
+	 << BIT_SHIFT_RD_WR_WIFI_BT_INFO_8821C)
+#define BIT_CLEAR_RD_WR_WIFI_BT_INFO_8821C(x)                                  \
+	((x) & (~BITS_RD_WR_WIFI_BT_INFO_8821C))
+#define BIT_GET_RD_WR_WIFI_BT_INFO_8821C(x)                                    \
+	(((x) >> BIT_SHIFT_RD_WR_WIFI_BT_INFO_8821C) &                         \
+	 BIT_MASK_RD_WR_WIFI_BT_INFO_8821C)
+#define BIT_SET_RD_WR_WIFI_BT_INFO_8821C(x, v)                                 \
+	(BIT_CLEAR_RD_WR_WIFI_BT_INFO_8821C(x) |                               \
+	 BIT_RD_WR_WIFI_BT_INFO_8821C(v))
+
+#define BIT_PMC_WR_OVF_8821C BIT(8)
+
+#define BIT_SHIFT_WLPMC_ERRINT_8821C 0
+#define BIT_MASK_WLPMC_ERRINT_8821C 0xff
+#define BIT_WLPMC_ERRINT_8821C(x)                                              \
+	(((x) & BIT_MASK_WLPMC_ERRINT_8821C) << BIT_SHIFT_WLPMC_ERRINT_8821C)
+#define BITS_WLPMC_ERRINT_8821C                                                \
+	(BIT_MASK_WLPMC_ERRINT_8821C << BIT_SHIFT_WLPMC_ERRINT_8821C)
+#define BIT_CLEAR_WLPMC_ERRINT_8821C(x) ((x) & (~BITS_WLPMC_ERRINT_8821C))
+#define BIT_GET_WLPMC_ERRINT_8821C(x)                                          \
+	(((x) >> BIT_SHIFT_WLPMC_ERRINT_8821C) & BIT_MASK_WLPMC_ERRINT_8821C)
+#define BIT_SET_WLPMC_ERRINT_8821C(x, v)                                       \
+	(BIT_CLEAR_WLPMC_ERRINT_8821C(x) | BIT_WLPMC_ERRINT_8821C(v))
+
+/* 2 REG_AFE_CTRL7_8821C */
+
+#define BIT_SHIFT_SEL_V_8821C 30
+#define BIT_MASK_SEL_V_8821C 0x3
+#define BIT_SEL_V_8821C(x)                                                     \
+	(((x) & BIT_MASK_SEL_V_8821C) << BIT_SHIFT_SEL_V_8821C)
+#define BITS_SEL_V_8821C (BIT_MASK_SEL_V_8821C << BIT_SHIFT_SEL_V_8821C)
+#define BIT_CLEAR_SEL_V_8821C(x) ((x) & (~BITS_SEL_V_8821C))
+#define BIT_GET_SEL_V_8821C(x)                                                 \
+	(((x) >> BIT_SHIFT_SEL_V_8821C) & BIT_MASK_SEL_V_8821C)
+#define BIT_SET_SEL_V_8821C(x, v)                                              \
+	(BIT_CLEAR_SEL_V_8821C(x) | BIT_SEL_V_8821C(v))
+
+#define BIT_SEL_LDO_PC_8821C BIT(29)
+
+#define BIT_SHIFT_CK_MON_SEL_8821C 26
+#define BIT_MASK_CK_MON_SEL_8821C 0x7
+#define BIT_CK_MON_SEL_8821C(x)                                                \
+	(((x) & BIT_MASK_CK_MON_SEL_8821C) << BIT_SHIFT_CK_MON_SEL_8821C)
+#define BITS_CK_MON_SEL_8821C                                                  \
+	(BIT_MASK_CK_MON_SEL_8821C << BIT_SHIFT_CK_MON_SEL_8821C)
+#define BIT_CLEAR_CK_MON_SEL_8821C(x) ((x) & (~BITS_CK_MON_SEL_8821C))
+#define BIT_GET_CK_MON_SEL_8821C(x)                                            \
+	(((x) >> BIT_SHIFT_CK_MON_SEL_8821C) & BIT_MASK_CK_MON_SEL_8821C)
+#define BIT_SET_CK_MON_SEL_8821C(x, v)                                         \
+	(BIT_CLEAR_CK_MON_SEL_8821C(x) | BIT_CK_MON_SEL_8821C(v))
+
+#define BIT_CK_MON_EN_8821C BIT(25)
+#define BIT_FREF_EDGE_8821C BIT(24)
+#define BIT_CK320M_EN_8821C BIT(23)
+#define BIT_CK_5M_EN_8821C BIT(22)
+#define BIT_TESTEN_8821C BIT(21)
+
+/* 2 REG_HIMR0_8821C */
+#define BIT_TIMEOUT_INTERRUPT2_MASK_8821C BIT(31)
+#define BIT_TIMEOUT_INTERRUTP1_MASK_8821C BIT(30)
+#define BIT_PSTIMEOUT_MSK_8821C BIT(29)
+#define BIT_GTINT4_MSK_8821C BIT(28)
+#define BIT_GTINT3_MSK_8821C BIT(27)
+#define BIT_TXBCN0ERR_MSK_8821C BIT(26)
+#define BIT_TXBCN0OK_MSK_8821C BIT(25)
+#define BIT_TSF_BIT32_TOGGLE_MSK_8821C BIT(24)
+#define BIT_BCNDMAINT0_MSK_8821C BIT(20)
+#define BIT_BCNDERR0_MSK_8821C BIT(16)
+#define BIT_HSISR_IND_ON_INT_MSK_8821C BIT(15)
+#define BIT_BCNDMAINT_E_MSK_8821C BIT(14)
+#define BIT_CTWEND_MSK_8821C BIT(12)
+#define BIT_HISR1_IND_MSK_8821C BIT(11)
+#define BIT_C2HCMD_MSK_8821C BIT(10)
+#define BIT_CPWM2_MSK_8821C BIT(9)
+#define BIT_CPWM_MSK_8821C BIT(8)
+#define BIT_HIGHDOK_MSK_8821C BIT(7)
+#define BIT_MGTDOK_MSK_8821C BIT(6)
+#define BIT_BKDOK_MSK_8821C BIT(5)
+#define BIT_BEDOK_MSK_8821C BIT(4)
+#define BIT_VIDOK_MSK_8821C BIT(3)
+#define BIT_VODOK_MSK_8821C BIT(2)
+#define BIT_RDU_MSK_8821C BIT(1)
+#define BIT_RXOK_MSK_8821C BIT(0)
+
+/* 2 REG_HISR0_8821C */
+#define BIT_PSTIMEOUT2_8821C BIT(31)
+#define BIT_PSTIMEOUT1_8821C BIT(30)
+#define BIT_PSTIMEOUT_8821C BIT(29)
+#define BIT_GTINT4_8821C BIT(28)
+#define BIT_GTINT3_8821C BIT(27)
+#define BIT_TXBCN0ERR_8821C BIT(26)
+#define BIT_TXBCN0OK_8821C BIT(25)
+#define BIT_TSF_BIT32_TOGGLE_8821C BIT(24)
+#define BIT_BCNDMAINT0_8821C BIT(20)
+#define BIT_BCNDERR0_8821C BIT(16)
+#define BIT_HSISR_IND_ON_INT_8821C BIT(15)
+#define BIT_BCNDMAINT_E_8821C BIT(14)
+#define BIT_CTWEND_8821C BIT(12)
+#define BIT_HISR1_IND_INT_8821C BIT(11)
+#define BIT_C2HCMD_8821C BIT(10)
+#define BIT_CPWM2_8821C BIT(9)
+#define BIT_CPWM_8821C BIT(8)
+#define BIT_HIGHDOK_8821C BIT(7)
+#define BIT_MGTDOK_8821C BIT(6)
+#define BIT_BKDOK_8821C BIT(5)
+#define BIT_BEDOK_8821C BIT(4)
+#define BIT_VIDOK_8821C BIT(3)
+#define BIT_VODOK_8821C BIT(2)
+#define BIT_RDU_8821C BIT(1)
+#define BIT_RXOK_8821C BIT(0)
+
+/* 2 REG_HIMR1_8821C */
+#define BIT_TXFIFO_TH_INT_8821C BIT(30)
+#define BIT_BTON_STS_UPDATE_MASK_8821C BIT(29)
+#define BIT_MCU_ERR_MASK_8821C BIT(28)
+#define BIT_BCNDMAINT7__MSK_8821C BIT(27)
+#define BIT_BCNDMAINT6__MSK_8821C BIT(26)
+#define BIT_BCNDMAINT5__MSK_8821C BIT(25)
+#define BIT_BCNDMAINT4__MSK_8821C BIT(24)
+#define BIT_BCNDMAINT3_MSK_8821C BIT(23)
+#define BIT_BCNDMAINT2_MSK_8821C BIT(22)
+#define BIT_BCNDMAINT1_MSK_8821C BIT(21)
+#define BIT_BCNDERR7_MSK_8821C BIT(20)
+#define BIT_BCNDERR6_MSK_8821C BIT(19)
+#define BIT_BCNDERR5_MSK_8821C BIT(18)
+#define BIT_BCNDERR4_MSK_8821C BIT(17)
+#define BIT_BCNDERR3_MSK_8821C BIT(16)
+#define BIT_BCNDERR2_MSK_8821C BIT(15)
+#define BIT_BCNDERR1_MSK_8821C BIT(14)
+#define BIT_ATIMEND_E_MSK_8821C BIT(13)
+#define BIT_ATIMEND__MSK_8821C BIT(12)
+#define BIT_TXERR_MSK_8821C BIT(11)
+#define BIT_RXERR_MSK_8821C BIT(10)
+#define BIT_TXFOVW_MSK_8821C BIT(9)
+#define BIT_FOVW_MSK_8821C BIT(8)
+#define BIT_CPU_MGQ_TXDONE_MSK_8821C BIT(5)
+#define BIT_PS_TIMER_C_MSK_8821C BIT(4)
+#define BIT_PS_TIMER_B_MSK_8821C BIT(3)
+#define BIT_PS_TIMER_A_MSK_8821C BIT(2)
+#define BIT_CPUMGQ_TX_TIMER_MSK_8821C BIT(1)
+
+/* 2 REG_HISR1_8821C */
+#define BIT_TXFIFO_TH_INT_8821C BIT(30)
+#define BIT_BTON_STS_UPDATE_INT_8821C BIT(29)
+#define BIT_MCU_ERR_8821C BIT(28)
+#define BIT_BCNDMAINT7_8821C BIT(27)
+#define BIT_BCNDMAINT6_8821C BIT(26)
+#define BIT_BCNDMAINT5_8821C BIT(25)
+#define BIT_BCNDMAINT4_8821C BIT(24)
+#define BIT_BCNDMAINT3_8821C BIT(23)
+#define BIT_BCNDMAINT2_8821C BIT(22)
+#define BIT_BCNDMAINT1_8821C BIT(21)
+#define BIT_BCNDERR7_8821C BIT(20)
+#define BIT_BCNDERR6_8821C BIT(19)
+#define BIT_BCNDERR5_8821C BIT(18)
+#define BIT_BCNDERR4_8821C BIT(17)
+#define BIT_BCNDERR3_8821C BIT(16)
+#define BIT_BCNDERR2_8821C BIT(15)
+#define BIT_BCNDERR1_8821C BIT(14)
+#define BIT_ATIMEND_E_8821C BIT(13)
+#define BIT_ATIMEND_8821C BIT(12)
+#define BIT_TXERR_INT_8821C BIT(11)
+#define BIT_RXERR_INT_8821C BIT(10)
+#define BIT_TXFOVW_8821C BIT(9)
+#define BIT_FOVW_8821C BIT(8)
+
+/* 2 REG_NOT_VALID_8821C */
+#define BIT_CPU_MGQ_TXDONE_8821C BIT(5)
+#define BIT_PS_TIMER_C_8821C BIT(4)
+#define BIT_PS_TIMER_B_8821C BIT(3)
+#define BIT_PS_TIMER_A_8821C BIT(2)
+#define BIT_CPUMGQ_TX_TIMER_8821C BIT(1)
+
+/* 2 REG_DBG_PORT_SEL_8821C */
+
+#define BIT_SHIFT_DEBUG_ST_8821C 0
+#define BIT_MASK_DEBUG_ST_8821C 0xffffffffL
+#define BIT_DEBUG_ST_8821C(x)                                                  \
+	(((x) & BIT_MASK_DEBUG_ST_8821C) << BIT_SHIFT_DEBUG_ST_8821C)
+#define BITS_DEBUG_ST_8821C                                                    \
+	(BIT_MASK_DEBUG_ST_8821C << BIT_SHIFT_DEBUG_ST_8821C)
+#define BIT_CLEAR_DEBUG_ST_8821C(x) ((x) & (~BITS_DEBUG_ST_8821C))
+#define BIT_GET_DEBUG_ST_8821C(x)                                              \
+	(((x) >> BIT_SHIFT_DEBUG_ST_8821C) & BIT_MASK_DEBUG_ST_8821C)
+#define BIT_SET_DEBUG_ST_8821C(x, v)                                           \
+	(BIT_CLEAR_DEBUG_ST_8821C(x) | BIT_DEBUG_ST_8821C(v))
+
+/* 2 REG_PAD_CTRL2_8821C */
+#define BIT_USB3_USB2_TRANSITION_8821C BIT(20)
+
+#define BIT_SHIFT_USB23_SW_MODE_V1_8821C 18
+#define BIT_MASK_USB23_SW_MODE_V1_8821C 0x3
+#define BIT_USB23_SW_MODE_V1_8821C(x)                                          \
+	(((x) & BIT_MASK_USB23_SW_MODE_V1_8821C)                               \
+	 << BIT_SHIFT_USB23_SW_MODE_V1_8821C)
+#define BITS_USB23_SW_MODE_V1_8821C                                            \
+	(BIT_MASK_USB23_SW_MODE_V1_8821C << BIT_SHIFT_USB23_SW_MODE_V1_8821C)
+#define BIT_CLEAR_USB23_SW_MODE_V1_8821C(x)                                    \
+	((x) & (~BITS_USB23_SW_MODE_V1_8821C))
+#define BIT_GET_USB23_SW_MODE_V1_8821C(x)                                      \
+	(((x) >> BIT_SHIFT_USB23_SW_MODE_V1_8821C) &                           \
+	 BIT_MASK_USB23_SW_MODE_V1_8821C)
+#define BIT_SET_USB23_SW_MODE_V1_8821C(x, v)                                   \
+	(BIT_CLEAR_USB23_SW_MODE_V1_8821C(x) | BIT_USB23_SW_MODE_V1_8821C(v))
+
+#define BIT_NO_PDN_CHIPOFF_V1_8821C BIT(17)
+#define BIT_RSM_EN_V1_8821C BIT(16)
+
+#define BIT_SHIFT_MATCH_CNT_8821C 8
+#define BIT_MASK_MATCH_CNT_8821C 0xff
+#define BIT_MATCH_CNT_8821C(x)                                                 \
+	(((x) & BIT_MASK_MATCH_CNT_8821C) << BIT_SHIFT_MATCH_CNT_8821C)
+#define BITS_MATCH_CNT_8821C                                                   \
+	(BIT_MASK_MATCH_CNT_8821C << BIT_SHIFT_MATCH_CNT_8821C)
+#define BIT_CLEAR_MATCH_CNT_8821C(x) ((x) & (~BITS_MATCH_CNT_8821C))
+#define BIT_GET_MATCH_CNT_8821C(x)                                             \
+	(((x) >> BIT_SHIFT_MATCH_CNT_8821C) & BIT_MASK_MATCH_CNT_8821C)
+#define BIT_SET_MATCH_CNT_8821C(x, v)                                          \
+	(BIT_CLEAR_MATCH_CNT_8821C(x) | BIT_MATCH_CNT_8821C(v))
+
+#define BIT_LD_B12V_EN_8821C BIT(7)
+#define BIT_EECS_IOSEL_V1_8821C BIT(6)
+#define BIT_EECS_DATA_O_V1_8821C BIT(5)
+#define BIT_EECS_DATA_I_V1_8821C BIT(4)
+#define BIT_EESK_IOSEL_V1_8821C BIT(2)
+#define BIT_EESK_DATA_O_V1_8821C BIT(1)
+#define BIT_EESK_DATA_I_V1_8821C BIT(0)
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_PMC_DBG_CTRL2_8821C */
+
+#define BIT_SHIFT_EFUSE_BURN_GNT_8821C 24
+#define BIT_MASK_EFUSE_BURN_GNT_8821C 0xff
+#define BIT_EFUSE_BURN_GNT_8821C(x)                                            \
+	(((x) & BIT_MASK_EFUSE_BURN_GNT_8821C)                                 \
+	 << BIT_SHIFT_EFUSE_BURN_GNT_8821C)
+#define BITS_EFUSE_BURN_GNT_8821C                                              \
+	(BIT_MASK_EFUSE_BURN_GNT_8821C << BIT_SHIFT_EFUSE_BURN_GNT_8821C)
+#define BIT_CLEAR_EFUSE_BURN_GNT_8821C(x) ((x) & (~BITS_EFUSE_BURN_GNT_8821C))
+#define BIT_GET_EFUSE_BURN_GNT_8821C(x)                                        \
+	(((x) >> BIT_SHIFT_EFUSE_BURN_GNT_8821C) &                             \
+	 BIT_MASK_EFUSE_BURN_GNT_8821C)
+#define BIT_SET_EFUSE_BURN_GNT_8821C(x, v)                                     \
+	(BIT_CLEAR_EFUSE_BURN_GNT_8821C(x) | BIT_EFUSE_BURN_GNT_8821C(v))
+
+#define BIT_STOP_WL_PMC_8821C BIT(9)
+#define BIT_STOP_SYM_PMC_8821C BIT(8)
+#define BIT_BT_ACCESS_WL_PAGE0_8821C BIT(6)
+#define BIT_REG_RST_WLPMC_8821C BIT(5)
+#define BIT_REG_RST_PD12N_8821C BIT(4)
+#define BIT_SYSON_DIS_WLREG_WRMSK_8821C BIT(3)
+#define BIT_SYSON_DIS_PMCREG_WRMSK_8821C BIT(2)
+
+#define BIT_SHIFT_SYSON_REG_ARB_8821C 0
+#define BIT_MASK_SYSON_REG_ARB_8821C 0x3
+#define BIT_SYSON_REG_ARB_8821C(x)                                             \
+	(((x) & BIT_MASK_SYSON_REG_ARB_8821C) << BIT_SHIFT_SYSON_REG_ARB_8821C)
+#define BITS_SYSON_REG_ARB_8821C                                               \
+	(BIT_MASK_SYSON_REG_ARB_8821C << BIT_SHIFT_SYSON_REG_ARB_8821C)
+#define BIT_CLEAR_SYSON_REG_ARB_8821C(x) ((x) & (~BITS_SYSON_REG_ARB_8821C))
+#define BIT_GET_SYSON_REG_ARB_8821C(x)                                         \
+	(((x) >> BIT_SHIFT_SYSON_REG_ARB_8821C) & BIT_MASK_SYSON_REG_ARB_8821C)
+#define BIT_SET_SYSON_REG_ARB_8821C(x, v)                                      \
+	(BIT_CLEAR_SYSON_REG_ARB_8821C(x) | BIT_SYSON_REG_ARB_8821C(v))
+
+/* 2 REG_BIST_CTRL_8821C */
+#define BIT_BIST_USB_DIS_8821C BIT(27)
+#define BIT_BIST_PCI_DIS_8821C BIT(26)
+#define BIT_BIST_BT_DIS_8821C BIT(25)
+#define BIT_BIST_WL_DIS_8821C BIT(24)
+
+#define BIT_SHIFT_BIST_RPT_SEL_8821C 16
+#define BIT_MASK_BIST_RPT_SEL_8821C 0xf
+#define BIT_BIST_RPT_SEL_8821C(x)                                              \
+	(((x) & BIT_MASK_BIST_RPT_SEL_8821C) << BIT_SHIFT_BIST_RPT_SEL_8821C)
+#define BITS_BIST_RPT_SEL_8821C                                                \
+	(BIT_MASK_BIST_RPT_SEL_8821C << BIT_SHIFT_BIST_RPT_SEL_8821C)
+#define BIT_CLEAR_BIST_RPT_SEL_8821C(x) ((x) & (~BITS_BIST_RPT_SEL_8821C))
+#define BIT_GET_BIST_RPT_SEL_8821C(x)                                          \
+	(((x) >> BIT_SHIFT_BIST_RPT_SEL_8821C) & BIT_MASK_BIST_RPT_SEL_8821C)
+#define BIT_SET_BIST_RPT_SEL_8821C(x, v)                                       \
+	(BIT_CLEAR_BIST_RPT_SEL_8821C(x) | BIT_BIST_RPT_SEL_8821C(v))
+
+#define BIT_BIST_RESUME_PS_8821C BIT(4)
+#define BIT_BIST_RESUME_8821C BIT(3)
+#define BIT_BIST_NORMAL_8821C BIT(2)
+#define BIT_BIST_RSTN_8821C BIT(1)
+#define BIT_BIST_CLK_EN_8821C BIT(0)
+
+/* 2 REG_BIST_RPT_8821C */
+
+#define BIT_SHIFT_MBIST_REPORT_8821C 0
+#define BIT_MASK_MBIST_REPORT_8821C 0xffffffffL
+#define BIT_MBIST_REPORT_8821C(x)                                              \
+	(((x) & BIT_MASK_MBIST_REPORT_8821C) << BIT_SHIFT_MBIST_REPORT_8821C)
+#define BITS_MBIST_REPORT_8821C                                                \
+	(BIT_MASK_MBIST_REPORT_8821C << BIT_SHIFT_MBIST_REPORT_8821C)
+#define BIT_CLEAR_MBIST_REPORT_8821C(x) ((x) & (~BITS_MBIST_REPORT_8821C))
+#define BIT_GET_MBIST_REPORT_8821C(x)                                          \
+	(((x) >> BIT_SHIFT_MBIST_REPORT_8821C) & BIT_MASK_MBIST_REPORT_8821C)
+#define BIT_SET_MBIST_REPORT_8821C(x, v)                                       \
+	(BIT_CLEAR_MBIST_REPORT_8821C(x) | BIT_MBIST_REPORT_8821C(v))
+
+/* 2 REG_MEM_CTRL_8821C */
+#define BIT_UMEM_RME_8821C BIT(31)
+
+#define BIT_SHIFT_BT_SPRAM_8821C 28
+#define BIT_MASK_BT_SPRAM_8821C 0x3
+#define BIT_BT_SPRAM_8821C(x)                                                  \
+	(((x) & BIT_MASK_BT_SPRAM_8821C) << BIT_SHIFT_BT_SPRAM_8821C)
+#define BITS_BT_SPRAM_8821C                                                    \
+	(BIT_MASK_BT_SPRAM_8821C << BIT_SHIFT_BT_SPRAM_8821C)
+#define BIT_CLEAR_BT_SPRAM_8821C(x) ((x) & (~BITS_BT_SPRAM_8821C))
+#define BIT_GET_BT_SPRAM_8821C(x)                                              \
+	(((x) >> BIT_SHIFT_BT_SPRAM_8821C) & BIT_MASK_BT_SPRAM_8821C)
+#define BIT_SET_BT_SPRAM_8821C(x, v)                                           \
+	(BIT_CLEAR_BT_SPRAM_8821C(x) | BIT_BT_SPRAM_8821C(v))
+
+#define BIT_SHIFT_BT_ROM_8821C 24
+#define BIT_MASK_BT_ROM_8821C 0xf
+#define BIT_BT_ROM_8821C(x)                                                    \
+	(((x) & BIT_MASK_BT_ROM_8821C) << BIT_SHIFT_BT_ROM_8821C)
+#define BITS_BT_ROM_8821C (BIT_MASK_BT_ROM_8821C << BIT_SHIFT_BT_ROM_8821C)
+#define BIT_CLEAR_BT_ROM_8821C(x) ((x) & (~BITS_BT_ROM_8821C))
+#define BIT_GET_BT_ROM_8821C(x)                                                \
+	(((x) >> BIT_SHIFT_BT_ROM_8821C) & BIT_MASK_BT_ROM_8821C)
+#define BIT_SET_BT_ROM_8821C(x, v)                                             \
+	(BIT_CLEAR_BT_ROM_8821C(x) | BIT_BT_ROM_8821C(v))
+
+#define BIT_SHIFT_PCI_DPRAM_8821C 10
+#define BIT_MASK_PCI_DPRAM_8821C 0x3
+#define BIT_PCI_DPRAM_8821C(x)                                                 \
+	(((x) & BIT_MASK_PCI_DPRAM_8821C) << BIT_SHIFT_PCI_DPRAM_8821C)
+#define BITS_PCI_DPRAM_8821C                                                   \
+	(BIT_MASK_PCI_DPRAM_8821C << BIT_SHIFT_PCI_DPRAM_8821C)
+#define BIT_CLEAR_PCI_DPRAM_8821C(x) ((x) & (~BITS_PCI_DPRAM_8821C))
+#define BIT_GET_PCI_DPRAM_8821C(x)                                             \
+	(((x) >> BIT_SHIFT_PCI_DPRAM_8821C) & BIT_MASK_PCI_DPRAM_8821C)
+#define BIT_SET_PCI_DPRAM_8821C(x, v)                                          \
+	(BIT_CLEAR_PCI_DPRAM_8821C(x) | BIT_PCI_DPRAM_8821C(v))
+
+#define BIT_SHIFT_PCI_SPRAM_8821C 8
+#define BIT_MASK_PCI_SPRAM_8821C 0x3
+#define BIT_PCI_SPRAM_8821C(x)                                                 \
+	(((x) & BIT_MASK_PCI_SPRAM_8821C) << BIT_SHIFT_PCI_SPRAM_8821C)
+#define BITS_PCI_SPRAM_8821C                                                   \
+	(BIT_MASK_PCI_SPRAM_8821C << BIT_SHIFT_PCI_SPRAM_8821C)
+#define BIT_CLEAR_PCI_SPRAM_8821C(x) ((x) & (~BITS_PCI_SPRAM_8821C))
+#define BIT_GET_PCI_SPRAM_8821C(x)                                             \
+	(((x) >> BIT_SHIFT_PCI_SPRAM_8821C) & BIT_MASK_PCI_SPRAM_8821C)
+#define BIT_SET_PCI_SPRAM_8821C(x, v)                                          \
+	(BIT_CLEAR_PCI_SPRAM_8821C(x) | BIT_PCI_SPRAM_8821C(v))
+
+#define BIT_SHIFT_USB_SPRAM_8821C 6
+#define BIT_MASK_USB_SPRAM_8821C 0x3
+#define BIT_USB_SPRAM_8821C(x)                                                 \
+	(((x) & BIT_MASK_USB_SPRAM_8821C) << BIT_SHIFT_USB_SPRAM_8821C)
+#define BITS_USB_SPRAM_8821C                                                   \
+	(BIT_MASK_USB_SPRAM_8821C << BIT_SHIFT_USB_SPRAM_8821C)
+#define BIT_CLEAR_USB_SPRAM_8821C(x) ((x) & (~BITS_USB_SPRAM_8821C))
+#define BIT_GET_USB_SPRAM_8821C(x)                                             \
+	(((x) >> BIT_SHIFT_USB_SPRAM_8821C) & BIT_MASK_USB_SPRAM_8821C)
+#define BIT_SET_USB_SPRAM_8821C(x, v)                                          \
+	(BIT_CLEAR_USB_SPRAM_8821C(x) | BIT_USB_SPRAM_8821C(v))
+
+#define BIT_SHIFT_USB_SPRF_8821C 4
+#define BIT_MASK_USB_SPRF_8821C 0x3
+#define BIT_USB_SPRF_8821C(x)                                                  \
+	(((x) & BIT_MASK_USB_SPRF_8821C) << BIT_SHIFT_USB_SPRF_8821C)
+#define BITS_USB_SPRF_8821C                                                    \
+	(BIT_MASK_USB_SPRF_8821C << BIT_SHIFT_USB_SPRF_8821C)
+#define BIT_CLEAR_USB_SPRF_8821C(x) ((x) & (~BITS_USB_SPRF_8821C))
+#define BIT_GET_USB_SPRF_8821C(x)                                              \
+	(((x) >> BIT_SHIFT_USB_SPRF_8821C) & BIT_MASK_USB_SPRF_8821C)
+#define BIT_SET_USB_SPRF_8821C(x, v)                                           \
+	(BIT_CLEAR_USB_SPRF_8821C(x) | BIT_USB_SPRF_8821C(v))
+
+#define BIT_SHIFT_MCU_ROM_8821C 0
+#define BIT_MASK_MCU_ROM_8821C 0xf
+#define BIT_MCU_ROM_8821C(x)                                                   \
+	(((x) & BIT_MASK_MCU_ROM_8821C) << BIT_SHIFT_MCU_ROM_8821C)
+#define BITS_MCU_ROM_8821C (BIT_MASK_MCU_ROM_8821C << BIT_SHIFT_MCU_ROM_8821C)
+#define BIT_CLEAR_MCU_ROM_8821C(x) ((x) & (~BITS_MCU_ROM_8821C))
+#define BIT_GET_MCU_ROM_8821C(x)                                               \
+	(((x) >> BIT_SHIFT_MCU_ROM_8821C) & BIT_MASK_MCU_ROM_8821C)
+#define BIT_SET_MCU_ROM_8821C(x, v)                                            \
+	(BIT_CLEAR_MCU_ROM_8821C(x) | BIT_MCU_ROM_8821C(v))
+
+/* 2 REG_AFE_CTRL8_8821C */
+#define BIT_SYN_AGPIO_8821C BIT(20)
+#define BIT_XTAL_LP_8821C BIT(4)
+#define BIT_XTAL_GM_SEP_8821C BIT(3)
+
+#define BIT_SHIFT_XTAL_SEL_TOK_8821C 0
+#define BIT_MASK_XTAL_SEL_TOK_8821C 0x7
+#define BIT_XTAL_SEL_TOK_8821C(x)                                              \
+	(((x) & BIT_MASK_XTAL_SEL_TOK_8821C) << BIT_SHIFT_XTAL_SEL_TOK_8821C)
+#define BITS_XTAL_SEL_TOK_8821C                                                \
+	(BIT_MASK_XTAL_SEL_TOK_8821C << BIT_SHIFT_XTAL_SEL_TOK_8821C)
+#define BIT_CLEAR_XTAL_SEL_TOK_8821C(x) ((x) & (~BITS_XTAL_SEL_TOK_8821C))
+#define BIT_GET_XTAL_SEL_TOK_8821C(x)                                          \
+	(((x) >> BIT_SHIFT_XTAL_SEL_TOK_8821C) & BIT_MASK_XTAL_SEL_TOK_8821C)
+#define BIT_SET_XTAL_SEL_TOK_8821C(x, v)                                       \
+	(BIT_CLEAR_XTAL_SEL_TOK_8821C(x) | BIT_XTAL_SEL_TOK_8821C(v))
+
+/* 2 REG_USB_SIE_INTF_8821C */
+#define BIT_RD_SEL_8821C BIT(31)
+#define BIT_USB_SIE_INTF_WE_V1_8821C BIT(30)
+#define BIT_USB_SIE_INTF_BYIOREG_V1_8821C BIT(29)
+#define BIT_USB_SIE_SELECT_8821C BIT(28)
+
+#define BIT_SHIFT_USB_SIE_INTF_ADDR_V1_8821C 16
+#define BIT_MASK_USB_SIE_INTF_ADDR_V1_8821C 0x1ff
+#define BIT_USB_SIE_INTF_ADDR_V1_8821C(x)                                      \
+	(((x) & BIT_MASK_USB_SIE_INTF_ADDR_V1_8821C)                           \
+	 << BIT_SHIFT_USB_SIE_INTF_ADDR_V1_8821C)
+#define BITS_USB_SIE_INTF_ADDR_V1_8821C                                        \
+	(BIT_MASK_USB_SIE_INTF_ADDR_V1_8821C                                   \
+	 << BIT_SHIFT_USB_SIE_INTF_ADDR_V1_8821C)
+#define BIT_CLEAR_USB_SIE_INTF_ADDR_V1_8821C(x)                                \
+	((x) & (~BITS_USB_SIE_INTF_ADDR_V1_8821C))
+#define BIT_GET_USB_SIE_INTF_ADDR_V1_8821C(x)                                  \
+	(((x) >> BIT_SHIFT_USB_SIE_INTF_ADDR_V1_8821C) &                       \
+	 BIT_MASK_USB_SIE_INTF_ADDR_V1_8821C)
+#define BIT_SET_USB_SIE_INTF_ADDR_V1_8821C(x, v)                               \
+	(BIT_CLEAR_USB_SIE_INTF_ADDR_V1_8821C(x) |                             \
+	 BIT_USB_SIE_INTF_ADDR_V1_8821C(v))
+
+#define BIT_SHIFT_USB_SIE_INTF_RD_8821C 8
+#define BIT_MASK_USB_SIE_INTF_RD_8821C 0xff
+#define BIT_USB_SIE_INTF_RD_8821C(x)                                           \
+	(((x) & BIT_MASK_USB_SIE_INTF_RD_8821C)                                \
+	 << BIT_SHIFT_USB_SIE_INTF_RD_8821C)
+#define BITS_USB_SIE_INTF_RD_8821C                                             \
+	(BIT_MASK_USB_SIE_INTF_RD_8821C << BIT_SHIFT_USB_SIE_INTF_RD_8821C)
+#define BIT_CLEAR_USB_SIE_INTF_RD_8821C(x) ((x) & (~BITS_USB_SIE_INTF_RD_8821C))
+#define BIT_GET_USB_SIE_INTF_RD_8821C(x)                                       \
+	(((x) >> BIT_SHIFT_USB_SIE_INTF_RD_8821C) &                            \
+	 BIT_MASK_USB_SIE_INTF_RD_8821C)
+#define BIT_SET_USB_SIE_INTF_RD_8821C(x, v)                                    \
+	(BIT_CLEAR_USB_SIE_INTF_RD_8821C(x) | BIT_USB_SIE_INTF_RD_8821C(v))
+
+#define BIT_SHIFT_USB_SIE_INTF_WD_8821C 0
+#define BIT_MASK_USB_SIE_INTF_WD_8821C 0xff
+#define BIT_USB_SIE_INTF_WD_8821C(x)                                           \
+	(((x) & BIT_MASK_USB_SIE_INTF_WD_8821C)                                \
+	 << BIT_SHIFT_USB_SIE_INTF_WD_8821C)
+#define BITS_USB_SIE_INTF_WD_8821C                                             \
+	(BIT_MASK_USB_SIE_INTF_WD_8821C << BIT_SHIFT_USB_SIE_INTF_WD_8821C)
+#define BIT_CLEAR_USB_SIE_INTF_WD_8821C(x) ((x) & (~BITS_USB_SIE_INTF_WD_8821C))
+#define BIT_GET_USB_SIE_INTF_WD_8821C(x)                                       \
+	(((x) >> BIT_SHIFT_USB_SIE_INTF_WD_8821C) &                            \
+	 BIT_MASK_USB_SIE_INTF_WD_8821C)
+#define BIT_SET_USB_SIE_INTF_WD_8821C(x, v)                                    \
+	(BIT_CLEAR_USB_SIE_INTF_WD_8821C(x) | BIT_USB_SIE_INTF_WD_8821C(v))
+
+/* 2 REG_PCIE_MIO_INTF_8821C */
+
+#define BIT_SHIFT_PCIE_MIO_ADDR_PAGE_8821C 16
+#define BIT_MASK_PCIE_MIO_ADDR_PAGE_8821C 0x3
+#define BIT_PCIE_MIO_ADDR_PAGE_8821C(x)                                        \
+	(((x) & BIT_MASK_PCIE_MIO_ADDR_PAGE_8821C)                             \
+	 << BIT_SHIFT_PCIE_MIO_ADDR_PAGE_8821C)
+#define BITS_PCIE_MIO_ADDR_PAGE_8821C                                          \
+	(BIT_MASK_PCIE_MIO_ADDR_PAGE_8821C                                     \
+	 << BIT_SHIFT_PCIE_MIO_ADDR_PAGE_8821C)
+#define BIT_CLEAR_PCIE_MIO_ADDR_PAGE_8821C(x)                                  \
+	((x) & (~BITS_PCIE_MIO_ADDR_PAGE_8821C))
+#define BIT_GET_PCIE_MIO_ADDR_PAGE_8821C(x)                                    \
+	(((x) >> BIT_SHIFT_PCIE_MIO_ADDR_PAGE_8821C) &                         \
+	 BIT_MASK_PCIE_MIO_ADDR_PAGE_8821C)
+#define BIT_SET_PCIE_MIO_ADDR_PAGE_8821C(x, v)                                 \
+	(BIT_CLEAR_PCIE_MIO_ADDR_PAGE_8821C(x) |                               \
+	 BIT_PCIE_MIO_ADDR_PAGE_8821C(v))
+
+#define BIT_PCIE_MIO_BYIOREG_8821C BIT(13)
+#define BIT_PCIE_MIO_RE_8821C BIT(12)
+
+#define BIT_SHIFT_PCIE_MIO_WE_8821C 8
+#define BIT_MASK_PCIE_MIO_WE_8821C 0xf
+#define BIT_PCIE_MIO_WE_8821C(x)                                               \
+	(((x) & BIT_MASK_PCIE_MIO_WE_8821C) << BIT_SHIFT_PCIE_MIO_WE_8821C)
+#define BITS_PCIE_MIO_WE_8821C                                                 \
+	(BIT_MASK_PCIE_MIO_WE_8821C << BIT_SHIFT_PCIE_MIO_WE_8821C)
+#define BIT_CLEAR_PCIE_MIO_WE_8821C(x) ((x) & (~BITS_PCIE_MIO_WE_8821C))
+#define BIT_GET_PCIE_MIO_WE_8821C(x)                                           \
+	(((x) >> BIT_SHIFT_PCIE_MIO_WE_8821C) & BIT_MASK_PCIE_MIO_WE_8821C)
+#define BIT_SET_PCIE_MIO_WE_8821C(x, v)                                        \
+	(BIT_CLEAR_PCIE_MIO_WE_8821C(x) | BIT_PCIE_MIO_WE_8821C(v))
+
+#define BIT_SHIFT_PCIE_MIO_ADDR_8821C 0
+#define BIT_MASK_PCIE_MIO_ADDR_8821C 0xff
+#define BIT_PCIE_MIO_ADDR_8821C(x)                                             \
+	(((x) & BIT_MASK_PCIE_MIO_ADDR_8821C) << BIT_SHIFT_PCIE_MIO_ADDR_8821C)
+#define BITS_PCIE_MIO_ADDR_8821C                                               \
+	(BIT_MASK_PCIE_MIO_ADDR_8821C << BIT_SHIFT_PCIE_MIO_ADDR_8821C)
+#define BIT_CLEAR_PCIE_MIO_ADDR_8821C(x) ((x) & (~BITS_PCIE_MIO_ADDR_8821C))
+#define BIT_GET_PCIE_MIO_ADDR_8821C(x)                                         \
+	(((x) >> BIT_SHIFT_PCIE_MIO_ADDR_8821C) & BIT_MASK_PCIE_MIO_ADDR_8821C)
+#define BIT_SET_PCIE_MIO_ADDR_8821C(x, v)                                      \
+	(BIT_CLEAR_PCIE_MIO_ADDR_8821C(x) | BIT_PCIE_MIO_ADDR_8821C(v))
+
+/* 2 REG_PCIE_MIO_INTD_8821C */
+
+#define BIT_SHIFT_PCIE_MIO_DATA_8821C 0
+#define BIT_MASK_PCIE_MIO_DATA_8821C 0xffffffffL
+#define BIT_PCIE_MIO_DATA_8821C(x)                                             \
+	(((x) & BIT_MASK_PCIE_MIO_DATA_8821C) << BIT_SHIFT_PCIE_MIO_DATA_8821C)
+#define BITS_PCIE_MIO_DATA_8821C                                               \
+	(BIT_MASK_PCIE_MIO_DATA_8821C << BIT_SHIFT_PCIE_MIO_DATA_8821C)
+#define BIT_CLEAR_PCIE_MIO_DATA_8821C(x) ((x) & (~BITS_PCIE_MIO_DATA_8821C))
+#define BIT_GET_PCIE_MIO_DATA_8821C(x)                                         \
+	(((x) >> BIT_SHIFT_PCIE_MIO_DATA_8821C) & BIT_MASK_PCIE_MIO_DATA_8821C)
+#define BIT_SET_PCIE_MIO_DATA_8821C(x, v)                                      \
+	(BIT_CLEAR_PCIE_MIO_DATA_8821C(x) | BIT_PCIE_MIO_DATA_8821C(v))
+
+/* 2 REG_WLRF1_8821C */
+
+#define BIT_SHIFT_WLRF1_CTRL_8821C 24
+#define BIT_MASK_WLRF1_CTRL_8821C 0xff
+#define BIT_WLRF1_CTRL_8821C(x)                                                \
+	(((x) & BIT_MASK_WLRF1_CTRL_8821C) << BIT_SHIFT_WLRF1_CTRL_8821C)
+#define BITS_WLRF1_CTRL_8821C                                                  \
+	(BIT_MASK_WLRF1_CTRL_8821C << BIT_SHIFT_WLRF1_CTRL_8821C)
+#define BIT_CLEAR_WLRF1_CTRL_8821C(x) ((x) & (~BITS_WLRF1_CTRL_8821C))
+#define BIT_GET_WLRF1_CTRL_8821C(x)                                            \
+	(((x) >> BIT_SHIFT_WLRF1_CTRL_8821C) & BIT_MASK_WLRF1_CTRL_8821C)
+#define BIT_SET_WLRF1_CTRL_8821C(x, v)                                         \
+	(BIT_CLEAR_WLRF1_CTRL_8821C(x) | BIT_WLRF1_CTRL_8821C(v))
+
+/* 2 REG_SYS_CFG1_8821C */
+
+#define BIT_SHIFT_TRP_ICFG_8821C 28
+#define BIT_MASK_TRP_ICFG_8821C 0xf
+#define BIT_TRP_ICFG_8821C(x)                                                  \
+	(((x) & BIT_MASK_TRP_ICFG_8821C) << BIT_SHIFT_TRP_ICFG_8821C)
+#define BITS_TRP_ICFG_8821C                                                    \
+	(BIT_MASK_TRP_ICFG_8821C << BIT_SHIFT_TRP_ICFG_8821C)
+#define BIT_CLEAR_TRP_ICFG_8821C(x) ((x) & (~BITS_TRP_ICFG_8821C))
+#define BIT_GET_TRP_ICFG_8821C(x)                                              \
+	(((x) >> BIT_SHIFT_TRP_ICFG_8821C) & BIT_MASK_TRP_ICFG_8821C)
+#define BIT_SET_TRP_ICFG_8821C(x, v)                                           \
+	(BIT_CLEAR_TRP_ICFG_8821C(x) | BIT_TRP_ICFG_8821C(v))
+
+#define BIT_RF_TYPE_ID_8821C BIT(27)
+#define BIT_BD_HCI_SEL_8821C BIT(26)
+#define BIT_BD_PKG_SEL_8821C BIT(25)
+#define BIT_SPSLDO_SEL_8821C BIT(24)
+#define BIT_RTL_ID_8821C BIT(23)
+#define BIT_PAD_HWPD_IDN_8821C BIT(22)
+#define BIT_TESTMODE_8821C BIT(20)
+
+#define BIT_SHIFT_VENDOR_ID_8821C 16
+#define BIT_MASK_VENDOR_ID_8821C 0xf
+#define BIT_VENDOR_ID_8821C(x)                                                 \
+	(((x) & BIT_MASK_VENDOR_ID_8821C) << BIT_SHIFT_VENDOR_ID_8821C)
+#define BITS_VENDOR_ID_8821C                                                   \
+	(BIT_MASK_VENDOR_ID_8821C << BIT_SHIFT_VENDOR_ID_8821C)
+#define BIT_CLEAR_VENDOR_ID_8821C(x) ((x) & (~BITS_VENDOR_ID_8821C))
+#define BIT_GET_VENDOR_ID_8821C(x)                                             \
+	(((x) >> BIT_SHIFT_VENDOR_ID_8821C) & BIT_MASK_VENDOR_ID_8821C)
+#define BIT_SET_VENDOR_ID_8821C(x, v)                                          \
+	(BIT_CLEAR_VENDOR_ID_8821C(x) | BIT_VENDOR_ID_8821C(v))
+
+#define BIT_SHIFT_CHIP_VER_8821C 12
+#define BIT_MASK_CHIP_VER_8821C 0xf
+#define BIT_CHIP_VER_8821C(x)                                                  \
+	(((x) & BIT_MASK_CHIP_VER_8821C) << BIT_SHIFT_CHIP_VER_8821C)
+#define BITS_CHIP_VER_8821C                                                    \
+	(BIT_MASK_CHIP_VER_8821C << BIT_SHIFT_CHIP_VER_8821C)
+#define BIT_CLEAR_CHIP_VER_8821C(x) ((x) & (~BITS_CHIP_VER_8821C))
+#define BIT_GET_CHIP_VER_8821C(x)                                              \
+	(((x) >> BIT_SHIFT_CHIP_VER_8821C) & BIT_MASK_CHIP_VER_8821C)
+#define BIT_SET_CHIP_VER_8821C(x, v)                                           \
+	(BIT_CLEAR_CHIP_VER_8821C(x) | BIT_CHIP_VER_8821C(v))
+
+#define BIT_BD_MAC3_8821C BIT(11)
+#define BIT_BD_MAC1_8821C BIT(10)
+#define BIT_BD_MAC2_8821C BIT(9)
+#define BIT_SIC_IDLE_8821C BIT(8)
+#define BIT_SW_OFFLOAD_EN_8821C BIT(7)
+#define BIT_OCP_SHUTDN_8821C BIT(6)
+#define BIT_V15_VLD_8821C BIT(5)
+#define BIT_PCIRSTB_8821C BIT(4)
+#define BIT_PCLK_VLD_8821C BIT(3)
+#define BIT_UCLK_VLD_8821C BIT(2)
+#define BIT_ACLK_VLD_8821C BIT(1)
+#define BIT_XCLK_VLD_8821C BIT(0)
+
+/* 2 REG_SYS_STATUS1_8821C */
+
+#define BIT_SHIFT_RF_RL_ID_8821C 28
+#define BIT_MASK_RF_RL_ID_8821C 0xf
+#define BIT_RF_RL_ID_8821C(x)                                                  \
+	(((x) & BIT_MASK_RF_RL_ID_8821C) << BIT_SHIFT_RF_RL_ID_8821C)
+#define BITS_RF_RL_ID_8821C                                                    \
+	(BIT_MASK_RF_RL_ID_8821C << BIT_SHIFT_RF_RL_ID_8821C)
+#define BIT_CLEAR_RF_RL_ID_8821C(x) ((x) & (~BITS_RF_RL_ID_8821C))
+#define BIT_GET_RF_RL_ID_8821C(x)                                              \
+	(((x) >> BIT_SHIFT_RF_RL_ID_8821C) & BIT_MASK_RF_RL_ID_8821C)
+#define BIT_SET_RF_RL_ID_8821C(x, v)                                           \
+	(BIT_CLEAR_RF_RL_ID_8821C(x) | BIT_RF_RL_ID_8821C(v))
+
+#define BIT_HPHY_ICFG_8821C BIT(19)
+
+#define BIT_SHIFT_SEL_0XC0_8821C 16
+#define BIT_MASK_SEL_0XC0_8821C 0x3
+#define BIT_SEL_0XC0_8821C(x)                                                  \
+	(((x) & BIT_MASK_SEL_0XC0_8821C) << BIT_SHIFT_SEL_0XC0_8821C)
+#define BITS_SEL_0XC0_8821C                                                    \
+	(BIT_MASK_SEL_0XC0_8821C << BIT_SHIFT_SEL_0XC0_8821C)
+#define BIT_CLEAR_SEL_0XC0_8821C(x) ((x) & (~BITS_SEL_0XC0_8821C))
+#define BIT_GET_SEL_0XC0_8821C(x)                                              \
+	(((x) >> BIT_SHIFT_SEL_0XC0_8821C) & BIT_MASK_SEL_0XC0_8821C)
+#define BIT_SET_SEL_0XC0_8821C(x, v)                                           \
+	(BIT_CLEAR_SEL_0XC0_8821C(x) | BIT_SEL_0XC0_8821C(v))
+
+#define BIT_SHIFT_HCI_SEL_V4_8821C 12
+#define BIT_MASK_HCI_SEL_V4_8821C 0x3
+#define BIT_HCI_SEL_V4_8821C(x)                                                \
+	(((x) & BIT_MASK_HCI_SEL_V4_8821C) << BIT_SHIFT_HCI_SEL_V4_8821C)
+#define BITS_HCI_SEL_V4_8821C                                                  \
+	(BIT_MASK_HCI_SEL_V4_8821C << BIT_SHIFT_HCI_SEL_V4_8821C)
+#define BIT_CLEAR_HCI_SEL_V4_8821C(x) ((x) & (~BITS_HCI_SEL_V4_8821C))
+#define BIT_GET_HCI_SEL_V4_8821C(x)                                            \
+	(((x) >> BIT_SHIFT_HCI_SEL_V4_8821C) & BIT_MASK_HCI_SEL_V4_8821C)
+#define BIT_SET_HCI_SEL_V4_8821C(x, v)                                         \
+	(BIT_CLEAR_HCI_SEL_V4_8821C(x) | BIT_HCI_SEL_V4_8821C(v))
+
+#define BIT_USB_OPERATION_MODE_8821C BIT(10)
+#define BIT_BT_PDN_8821C BIT(9)
+#define BIT_AUTO_WLPON_8821C BIT(8)
+#define BIT_WL_MODE_8821C BIT(7)
+#define BIT_PKG_SEL_HCI_8821C BIT(6)
+
+#define BIT_SHIFT_PAD_HCI_SEL_V2_8821C 3
+#define BIT_MASK_PAD_HCI_SEL_V2_8821C 0x3
+#define BIT_PAD_HCI_SEL_V2_8821C(x)                                            \
+	(((x) & BIT_MASK_PAD_HCI_SEL_V2_8821C)                                 \
+	 << BIT_SHIFT_PAD_HCI_SEL_V2_8821C)
+#define BITS_PAD_HCI_SEL_V2_8821C                                              \
+	(BIT_MASK_PAD_HCI_SEL_V2_8821C << BIT_SHIFT_PAD_HCI_SEL_V2_8821C)
+#define BIT_CLEAR_PAD_HCI_SEL_V2_8821C(x) ((x) & (~BITS_PAD_HCI_SEL_V2_8821C))
+#define BIT_GET_PAD_HCI_SEL_V2_8821C(x)                                        \
+	(((x) >> BIT_SHIFT_PAD_HCI_SEL_V2_8821C) &                             \
+	 BIT_MASK_PAD_HCI_SEL_V2_8821C)
+#define BIT_SET_PAD_HCI_SEL_V2_8821C(x, v)                                     \
+	(BIT_CLEAR_PAD_HCI_SEL_V2_8821C(x) | BIT_PAD_HCI_SEL_V2_8821C(v))
+
+#define BIT_SHIFT_EFS_HCI_SEL_8821C 0
+#define BIT_MASK_EFS_HCI_SEL_8821C 0x3
+#define BIT_EFS_HCI_SEL_8821C(x)                                               \
+	(((x) & BIT_MASK_EFS_HCI_SEL_8821C) << BIT_SHIFT_EFS_HCI_SEL_8821C)
+#define BITS_EFS_HCI_SEL_8821C                                                 \
+	(BIT_MASK_EFS_HCI_SEL_8821C << BIT_SHIFT_EFS_HCI_SEL_8821C)
+#define BIT_CLEAR_EFS_HCI_SEL_8821C(x) ((x) & (~BITS_EFS_HCI_SEL_8821C))
+#define BIT_GET_EFS_HCI_SEL_8821C(x)                                           \
+	(((x) >> BIT_SHIFT_EFS_HCI_SEL_8821C) & BIT_MASK_EFS_HCI_SEL_8821C)
+#define BIT_SET_EFS_HCI_SEL_8821C(x, v)                                        \
+	(BIT_CLEAR_EFS_HCI_SEL_8821C(x) | BIT_EFS_HCI_SEL_8821C(v))
+
+/* 2 REG_SYS_STATUS2_8821C */
+#define BIT_SIO_ALDN_8821C BIT(19)
+#define BIT_USB_ALDN_8821C BIT(18)
+#define BIT_PCI_ALDN_8821C BIT(17)
+#define BIT_SYS_ALDN_8821C BIT(16)
+
+#define BIT_SHIFT_EPVID1_8821C 8
+#define BIT_MASK_EPVID1_8821C 0xff
+#define BIT_EPVID1_8821C(x)                                                    \
+	(((x) & BIT_MASK_EPVID1_8821C) << BIT_SHIFT_EPVID1_8821C)
+#define BITS_EPVID1_8821C (BIT_MASK_EPVID1_8821C << BIT_SHIFT_EPVID1_8821C)
+#define BIT_CLEAR_EPVID1_8821C(x) ((x) & (~BITS_EPVID1_8821C))
+#define BIT_GET_EPVID1_8821C(x)                                                \
+	(((x) >> BIT_SHIFT_EPVID1_8821C) & BIT_MASK_EPVID1_8821C)
+#define BIT_SET_EPVID1_8821C(x, v)                                             \
+	(BIT_CLEAR_EPVID1_8821C(x) | BIT_EPVID1_8821C(v))
+
+#define BIT_SHIFT_EPVID0_8821C 0
+#define BIT_MASK_EPVID0_8821C 0xff
+#define BIT_EPVID0_8821C(x)                                                    \
+	(((x) & BIT_MASK_EPVID0_8821C) << BIT_SHIFT_EPVID0_8821C)
+#define BITS_EPVID0_8821C (BIT_MASK_EPVID0_8821C << BIT_SHIFT_EPVID0_8821C)
+#define BIT_CLEAR_EPVID0_8821C(x) ((x) & (~BITS_EPVID0_8821C))
+#define BIT_GET_EPVID0_8821C(x)                                                \
+	(((x) >> BIT_SHIFT_EPVID0_8821C) & BIT_MASK_EPVID0_8821C)
+#define BIT_SET_EPVID0_8821C(x, v)                                             \
+	(BIT_CLEAR_EPVID0_8821C(x) | BIT_EPVID0_8821C(v))
+
+/* 2 REG_SYS_CFG2_8821C */
+#define BIT_HCI_SEL_EMBEDDED_8821C BIT(8)
+
+#define BIT_SHIFT_HW_ID_8821C 0
+#define BIT_MASK_HW_ID_8821C 0xff
+#define BIT_HW_ID_8821C(x)                                                     \
+	(((x) & BIT_MASK_HW_ID_8821C) << BIT_SHIFT_HW_ID_8821C)
+#define BITS_HW_ID_8821C (BIT_MASK_HW_ID_8821C << BIT_SHIFT_HW_ID_8821C)
+#define BIT_CLEAR_HW_ID_8821C(x) ((x) & (~BITS_HW_ID_8821C))
+#define BIT_GET_HW_ID_8821C(x)                                                 \
+	(((x) >> BIT_SHIFT_HW_ID_8821C) & BIT_MASK_HW_ID_8821C)
+#define BIT_SET_HW_ID_8821C(x, v)                                              \
+	(BIT_CLEAR_HW_ID_8821C(x) | BIT_HW_ID_8821C(v))
+
+/* 2 REG_SYS_CFG3_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_SYS_CFG5_8821C */
+#define BIT_LPS_STATUS_8821C BIT(3)
+#define BIT_HCI_TXDMA_BUSY_8821C BIT(2)
+#define BIT_HCI_TXDMA_ALLOW_8821C BIT(1)
+#define BIT_FW_CTRL_HCI_TXDMA_EN_8821C BIT(0)
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_CPU_DMEM_CON_8821C */
+#define BIT_WDT_AUTO_MODE_8821C BIT(22)
+#define BIT_WDT_PLATFORM_EN_8821C BIT(21)
+#define BIT_WDT_CPU_EN_8821C BIT(20)
+#define BIT_WDT_OPT_IOWRAPPER_8821C BIT(19)
+#define BIT_ANA_PORT_IDLE_8821C BIT(18)
+#define BIT_MAC_PORT_IDLE_8821C BIT(17)
+#define BIT_WL_PLATFORM_RST_8821C BIT(16)
+#define BIT_WL_SECURITY_CLK_8821C BIT(15)
+
+#define BIT_SHIFT_CPU_DMEM_CON_8821C 0
+#define BIT_MASK_CPU_DMEM_CON_8821C 0xff
+#define BIT_CPU_DMEM_CON_8821C(x)                                              \
+	(((x) & BIT_MASK_CPU_DMEM_CON_8821C) << BIT_SHIFT_CPU_DMEM_CON_8821C)
+#define BITS_CPU_DMEM_CON_8821C                                                \
+	(BIT_MASK_CPU_DMEM_CON_8821C << BIT_SHIFT_CPU_DMEM_CON_8821C)
+#define BIT_CLEAR_CPU_DMEM_CON_8821C(x) ((x) & (~BITS_CPU_DMEM_CON_8821C))
+#define BIT_GET_CPU_DMEM_CON_8821C(x)                                          \
+	(((x) >> BIT_SHIFT_CPU_DMEM_CON_8821C) & BIT_MASK_CPU_DMEM_CON_8821C)
+#define BIT_SET_CPU_DMEM_CON_8821C(x, v)                                       \
+	(BIT_CLEAR_CPU_DMEM_CON_8821C(x) | BIT_CPU_DMEM_CON_8821C(v))
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_BOOT_REASON_8821C */
+
+#define BIT_SHIFT_BOOT_REASON_V1_8821C 0
+#define BIT_MASK_BOOT_REASON_V1_8821C 0x7
+#define BIT_BOOT_REASON_V1_8821C(x)                                            \
+	(((x) & BIT_MASK_BOOT_REASON_V1_8821C)                                 \
+	 << BIT_SHIFT_BOOT_REASON_V1_8821C)
+#define BITS_BOOT_REASON_V1_8821C                                              \
+	(BIT_MASK_BOOT_REASON_V1_8821C << BIT_SHIFT_BOOT_REASON_V1_8821C)
+#define BIT_CLEAR_BOOT_REASON_V1_8821C(x) ((x) & (~BITS_BOOT_REASON_V1_8821C))
+#define BIT_GET_BOOT_REASON_V1_8821C(x)                                        \
+	(((x) >> BIT_SHIFT_BOOT_REASON_V1_8821C) &                             \
+	 BIT_MASK_BOOT_REASON_V1_8821C)
+#define BIT_SET_BOOT_REASON_V1_8821C(x, v)                                     \
+	(BIT_CLEAR_BOOT_REASON_V1_8821C(x) | BIT_BOOT_REASON_V1_8821C(v))
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NFCPAD_CTRL_8821C */
+#define BIT_PAD_SHUTDW_8821C BIT(18)
+#define BIT_SYSON_NFC_PAD_8821C BIT(17)
+#define BIT_NFC_INT_PAD_CTRL_8821C BIT(16)
+#define BIT_NFC_RFDIS_PAD_CTRL_8821C BIT(15)
+#define BIT_NFC_CLK_PAD_CTRL_8821C BIT(14)
+#define BIT_NFC_DATA_PAD_CTRL_8821C BIT(13)
+#define BIT_NFC_PAD_PULL_CTRL_8821C BIT(12)
+
+#define BIT_SHIFT_NFCPAD_IO_SEL_8821C 8
+#define BIT_MASK_NFCPAD_IO_SEL_8821C 0xf
+#define BIT_NFCPAD_IO_SEL_8821C(x)                                             \
+	(((x) & BIT_MASK_NFCPAD_IO_SEL_8821C) << BIT_SHIFT_NFCPAD_IO_SEL_8821C)
+#define BITS_NFCPAD_IO_SEL_8821C                                               \
+	(BIT_MASK_NFCPAD_IO_SEL_8821C << BIT_SHIFT_NFCPAD_IO_SEL_8821C)
+#define BIT_CLEAR_NFCPAD_IO_SEL_8821C(x) ((x) & (~BITS_NFCPAD_IO_SEL_8821C))
+#define BIT_GET_NFCPAD_IO_SEL_8821C(x)                                         \
+	(((x) >> BIT_SHIFT_NFCPAD_IO_SEL_8821C) & BIT_MASK_NFCPAD_IO_SEL_8821C)
+#define BIT_SET_NFCPAD_IO_SEL_8821C(x, v)                                      \
+	(BIT_CLEAR_NFCPAD_IO_SEL_8821C(x) | BIT_NFCPAD_IO_SEL_8821C(v))
+
+#define BIT_SHIFT_NFCPAD_OUT_8821C 4
+#define BIT_MASK_NFCPAD_OUT_8821C 0xf
+#define BIT_NFCPAD_OUT_8821C(x)                                                \
+	(((x) & BIT_MASK_NFCPAD_OUT_8821C) << BIT_SHIFT_NFCPAD_OUT_8821C)
+#define BITS_NFCPAD_OUT_8821C                                                  \
+	(BIT_MASK_NFCPAD_OUT_8821C << BIT_SHIFT_NFCPAD_OUT_8821C)
+#define BIT_CLEAR_NFCPAD_OUT_8821C(x) ((x) & (~BITS_NFCPAD_OUT_8821C))
+#define BIT_GET_NFCPAD_OUT_8821C(x)                                            \
+	(((x) >> BIT_SHIFT_NFCPAD_OUT_8821C) & BIT_MASK_NFCPAD_OUT_8821C)
+#define BIT_SET_NFCPAD_OUT_8821C(x, v)                                         \
+	(BIT_CLEAR_NFCPAD_OUT_8821C(x) | BIT_NFCPAD_OUT_8821C(v))
+
+#define BIT_SHIFT_NFCPAD_IN_8821C 0
+#define BIT_MASK_NFCPAD_IN_8821C 0xf
+#define BIT_NFCPAD_IN_8821C(x)                                                 \
+	(((x) & BIT_MASK_NFCPAD_IN_8821C) << BIT_SHIFT_NFCPAD_IN_8821C)
+#define BITS_NFCPAD_IN_8821C                                                   \
+	(BIT_MASK_NFCPAD_IN_8821C << BIT_SHIFT_NFCPAD_IN_8821C)
+#define BIT_CLEAR_NFCPAD_IN_8821C(x) ((x) & (~BITS_NFCPAD_IN_8821C))
+#define BIT_GET_NFCPAD_IN_8821C(x)                                             \
+	(((x) >> BIT_SHIFT_NFCPAD_IN_8821C) & BIT_MASK_NFCPAD_IN_8821C)
+#define BIT_SET_NFCPAD_IN_8821C(x, v)                                          \
+	(BIT_CLEAR_NFCPAD_IN_8821C(x) | BIT_NFCPAD_IN_8821C(v))
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_HIMR2_8821C */
+#define BIT_BCNDMAINT_P4_MSK_8821C BIT(31)
+#define BIT_BCNDMAINT_P3_MSK_8821C BIT(30)
+#define BIT_BCNDMAINT_P2_MSK_8821C BIT(29)
+#define BIT_BCNDMAINT_P1_MSK_8821C BIT(28)
+#define BIT_ATIMEND7_MSK_8821C BIT(22)
+#define BIT_ATIMEND6_MSK_8821C BIT(21)
+#define BIT_ATIMEND5_MSK_8821C BIT(20)
+#define BIT_ATIMEND4_MSK_8821C BIT(19)
+#define BIT_ATIMEND3_MSK_8821C BIT(18)
+#define BIT_ATIMEND2_MSK_8821C BIT(17)
+#define BIT_ATIMEND1_MSK_8821C BIT(16)
+#define BIT_TXBCN7OK_MSK_8821C BIT(14)
+#define BIT_TXBCN6OK_MSK_8821C BIT(13)
+#define BIT_TXBCN5OK_MSK_8821C BIT(12)
+#define BIT_TXBCN4OK_MSK_8821C BIT(11)
+#define BIT_TXBCN3OK_MSK_8821C BIT(10)
+#define BIT_TXBCN2OK_MSK_8821C BIT(9)
+#define BIT_TXBCN1OK_MSK_V1_8821C BIT(8)
+#define BIT_TXBCN7ERR_MSK_8821C BIT(6)
+#define BIT_TXBCN6ERR_MSK_8821C BIT(5)
+#define BIT_TXBCN5ERR_MSK_8821C BIT(4)
+#define BIT_TXBCN4ERR_MSK_8821C BIT(3)
+#define BIT_TXBCN3ERR_MSK_8821C BIT(2)
+#define BIT_TXBCN2ERR_MSK_8821C BIT(1)
+#define BIT_TXBCN1ERR_MSK_V1_8821C BIT(0)
+
+/* 2 REG_HISR2_8821C */
+#define BIT_BCNDMAINT_P4_8821C BIT(31)
+#define BIT_BCNDMAINT_P3_8821C BIT(30)
+#define BIT_BCNDMAINT_P2_8821C BIT(29)
+#define BIT_BCNDMAINT_P1_8821C BIT(28)
+#define BIT_ATIMEND7_8821C BIT(22)
+#define BIT_ATIMEND6_8821C BIT(21)
+#define BIT_ATIMEND5_8821C BIT(20)
+#define BIT_ATIMEND4_8821C BIT(19)
+#define BIT_ATIMEND3_8821C BIT(18)
+#define BIT_ATIMEND2_8821C BIT(17)
+#define BIT_ATIMEND1_8821C BIT(16)
+#define BIT_TXBCN7OK_8821C BIT(14)
+#define BIT_TXBCN6OK_8821C BIT(13)
+#define BIT_TXBCN5OK_8821C BIT(12)
+#define BIT_TXBCN4OK_8821C BIT(11)
+#define BIT_TXBCN3OK_8821C BIT(10)
+#define BIT_TXBCN2OK_8821C BIT(9)
+#define BIT_TXBCN1OK_8821C BIT(8)
+#define BIT_TXBCN7ERR_8821C BIT(6)
+#define BIT_TXBCN6ERR_8821C BIT(5)
+#define BIT_TXBCN5ERR_8821C BIT(4)
+#define BIT_TXBCN4ERR_8821C BIT(3)
+#define BIT_TXBCN3ERR_8821C BIT(2)
+#define BIT_TXBCN2ERR_8821C BIT(1)
+#define BIT_TXBCN1ERR_8821C BIT(0)
+
+/* 2 REG_HIMR3_8821C */
+#define BIT_WDT_PLATFORM_INT_MSK_8821C BIT(18)
+#define BIT_WDT_CPU_INT_MSK_8821C BIT(17)
+#define BIT_SETH2CDOK_MASK_8821C BIT(16)
+#define BIT_H2C_CMD_FULL_MASK_8821C BIT(15)
+#define BIT_PWR_INT_127_MASK_8821C BIT(14)
+#define BIT_TXSHORTCUT_TXDESUPDATEOK_MASK_8821C BIT(13)
+#define BIT_TXSHORTCUT_BKUPDATEOK_MASK_8821C BIT(12)
+#define BIT_TXSHORTCUT_BEUPDATEOK_MASK_8821C BIT(11)
+#define BIT_TXSHORTCUT_VIUPDATEOK_MAS_8821C BIT(10)
+#define BIT_TXSHORTCUT_VOUPDATEOK_MASK_8821C BIT(9)
+#define BIT_PWR_INT_127_MASK_V1_8821C BIT(8)
+#define BIT_PWR_INT_126TO96_MASK_8821C BIT(7)
+#define BIT_PWR_INT_95TO64_MASK_8821C BIT(6)
+#define BIT_PWR_INT_63TO32_MASK_8821C BIT(5)
+#define BIT_PWR_INT_31TO0_MASK_8821C BIT(4)
+#define BIT_DDMA0_LP_INT_MSK_8821C BIT(1)
+#define BIT_DDMA0_HP_INT_MSK_8821C BIT(0)
+
+/* 2 REG_HISR3_8821C */
+#define BIT_WDT_PLATFORM_INT_8821C BIT(18)
+#define BIT_WDT_CPU_INT_8821C BIT(17)
+#define BIT_SETH2CDOK_8821C BIT(16)
+#define BIT_H2C_CMD_FULL_8821C BIT(15)
+#define BIT_PWR_INT_127_8821C BIT(14)
+#define BIT_TXSHORTCUT_TXDESUPDATEOK_8821C BIT(13)
+#define BIT_TXSHORTCUT_BKUPDATEOK_8821C BIT(12)
+#define BIT_TXSHORTCUT_BEUPDATEOK_8821C BIT(11)
+#define BIT_TXSHORTCUT_VIUPDATEOK_8821C BIT(10)
+#define BIT_TXSHORTCUT_VOUPDATEOK_8821C BIT(9)
+#define BIT_PWR_INT_127_V1_8821C BIT(8)
+#define BIT_PWR_INT_126TO96_8821C BIT(7)
+#define BIT_PWR_INT_95TO64_8821C BIT(6)
+#define BIT_PWR_INT_63TO32_8821C BIT(5)
+#define BIT_PWR_INT_31TO0_8821C BIT(4)
+#define BIT_DDMA0_LP_INT_8821C BIT(1)
+#define BIT_DDMA0_HP_INT_8821C BIT(0)
+
+/* 2 REG_SW_MDIO_8821C */
+#define BIT_DIS_TIMEOUT_IO_8821C BIT(24)
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_H2C_PKT_READADDR_8821C */
+
+#define BIT_SHIFT_H2C_PKT_READADDR_8821C 0
+#define BIT_MASK_H2C_PKT_READADDR_8821C 0x3ffff
+#define BIT_H2C_PKT_READADDR_8821C(x)                                          \
+	(((x) & BIT_MASK_H2C_PKT_READADDR_8821C)                               \
+	 << BIT_SHIFT_H2C_PKT_READADDR_8821C)
+#define BITS_H2C_PKT_READADDR_8821C                                            \
+	(BIT_MASK_H2C_PKT_READADDR_8821C << BIT_SHIFT_H2C_PKT_READADDR_8821C)
+#define BIT_CLEAR_H2C_PKT_READADDR_8821C(x)                                    \
+	((x) & (~BITS_H2C_PKT_READADDR_8821C))
+#define BIT_GET_H2C_PKT_READADDR_8821C(x)                                      \
+	(((x) >> BIT_SHIFT_H2C_PKT_READADDR_8821C) &                           \
+	 BIT_MASK_H2C_PKT_READADDR_8821C)
+#define BIT_SET_H2C_PKT_READADDR_8821C(x, v)                                   \
+	(BIT_CLEAR_H2C_PKT_READADDR_8821C(x) | BIT_H2C_PKT_READADDR_8821C(v))
+
+/* 2 REG_H2C_PKT_WRITEADDR_8821C */
+
+#define BIT_SHIFT_H2C_PKT_WRITEADDR_8821C 0
+#define BIT_MASK_H2C_PKT_WRITEADDR_8821C 0x3ffff
+#define BIT_H2C_PKT_WRITEADDR_8821C(x)                                         \
+	(((x) & BIT_MASK_H2C_PKT_WRITEADDR_8821C)                              \
+	 << BIT_SHIFT_H2C_PKT_WRITEADDR_8821C)
+#define BITS_H2C_PKT_WRITEADDR_8821C                                           \
+	(BIT_MASK_H2C_PKT_WRITEADDR_8821C << BIT_SHIFT_H2C_PKT_WRITEADDR_8821C)
+#define BIT_CLEAR_H2C_PKT_WRITEADDR_8821C(x)                                   \
+	((x) & (~BITS_H2C_PKT_WRITEADDR_8821C))
+#define BIT_GET_H2C_PKT_WRITEADDR_8821C(x)                                     \
+	(((x) >> BIT_SHIFT_H2C_PKT_WRITEADDR_8821C) &                          \
+	 BIT_MASK_H2C_PKT_WRITEADDR_8821C)
+#define BIT_SET_H2C_PKT_WRITEADDR_8821C(x, v)                                  \
+	(BIT_CLEAR_H2C_PKT_WRITEADDR_8821C(x) | BIT_H2C_PKT_WRITEADDR_8821C(v))
+
+/* 2 REG_MEM_PWR_CRTL_8821C */
+#define BIT_MEM_BB_SD_8821C BIT(17)
+#define BIT_MEM_BB_DS_8821C BIT(16)
+#define BIT_MEM_BT_DS_8821C BIT(10)
+#define BIT_MEM_SDIO_LS_8821C BIT(9)
+#define BIT_MEM_SDIO_DS_8821C BIT(8)
+#define BIT_MEM_USB_LS_8821C BIT(7)
+#define BIT_MEM_USB_DS_8821C BIT(6)
+#define BIT_MEM_PCI_LS_8821C BIT(5)
+#define BIT_MEM_PCI_DS_8821C BIT(4)
+#define BIT_MEM_WLMAC_LS_8821C BIT(3)
+#define BIT_MEM_WLMAC_DS_8821C BIT(2)
+#define BIT_MEM_WLMCU_LS_8821C BIT(1)
+#define BIT_MEM_WLMCU_DS_8821C BIT(0)
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_FW_DBG6_8821C */
+
+#define BIT_SHIFT_FW_DBG6_8821C 0
+#define BIT_MASK_FW_DBG6_8821C 0xffffffffL
+#define BIT_FW_DBG6_8821C(x)                                                   \
+	(((x) & BIT_MASK_FW_DBG6_8821C) << BIT_SHIFT_FW_DBG6_8821C)
+#define BITS_FW_DBG6_8821C (BIT_MASK_FW_DBG6_8821C << BIT_SHIFT_FW_DBG6_8821C)
+#define BIT_CLEAR_FW_DBG6_8821C(x) ((x) & (~BITS_FW_DBG6_8821C))
+#define BIT_GET_FW_DBG6_8821C(x)                                               \
+	(((x) >> BIT_SHIFT_FW_DBG6_8821C) & BIT_MASK_FW_DBG6_8821C)
+#define BIT_SET_FW_DBG6_8821C(x, v)                                            \
+	(BIT_CLEAR_FW_DBG6_8821C(x) | BIT_FW_DBG6_8821C(v))
+
+/* 2 REG_FW_DBG7_8821C */
+
+#define BIT_SHIFT_FW_DBG7_8821C 0
+#define BIT_MASK_FW_DBG7_8821C 0xffffffffL
+#define BIT_FW_DBG7_8821C(x)                                                   \
+	(((x) & BIT_MASK_FW_DBG7_8821C) << BIT_SHIFT_FW_DBG7_8821C)
+#define BITS_FW_DBG7_8821C (BIT_MASK_FW_DBG7_8821C << BIT_SHIFT_FW_DBG7_8821C)
+#define BIT_CLEAR_FW_DBG7_8821C(x) ((x) & (~BITS_FW_DBG7_8821C))
+#define BIT_GET_FW_DBG7_8821C(x)                                               \
+	(((x) >> BIT_SHIFT_FW_DBG7_8821C) & BIT_MASK_FW_DBG7_8821C)
+#define BIT_SET_FW_DBG7_8821C(x, v)                                            \
+	(BIT_CLEAR_FW_DBG7_8821C(x) | BIT_FW_DBG7_8821C(v))
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_CR_8821C */
+
+#define BIT_SHIFT_LBMODE_8821C 24
+#define BIT_MASK_LBMODE_8821C 0x1f
+#define BIT_LBMODE_8821C(x)                                                    \
+	(((x) & BIT_MASK_LBMODE_8821C) << BIT_SHIFT_LBMODE_8821C)
+#define BITS_LBMODE_8821C (BIT_MASK_LBMODE_8821C << BIT_SHIFT_LBMODE_8821C)
+#define BIT_CLEAR_LBMODE_8821C(x) ((x) & (~BITS_LBMODE_8821C))
+#define BIT_GET_LBMODE_8821C(x)                                                \
+	(((x) >> BIT_SHIFT_LBMODE_8821C) & BIT_MASK_LBMODE_8821C)
+#define BIT_SET_LBMODE_8821C(x, v)                                             \
+	(BIT_CLEAR_LBMODE_8821C(x) | BIT_LBMODE_8821C(v))
+
+#define BIT_SHIFT_NETYPE1_8821C 18
+#define BIT_MASK_NETYPE1_8821C 0x3
+#define BIT_NETYPE1_8821C(x)                                                   \
+	(((x) & BIT_MASK_NETYPE1_8821C) << BIT_SHIFT_NETYPE1_8821C)
+#define BITS_NETYPE1_8821C (BIT_MASK_NETYPE1_8821C << BIT_SHIFT_NETYPE1_8821C)
+#define BIT_CLEAR_NETYPE1_8821C(x) ((x) & (~BITS_NETYPE1_8821C))
+#define BIT_GET_NETYPE1_8821C(x)                                               \
+	(((x) >> BIT_SHIFT_NETYPE1_8821C) & BIT_MASK_NETYPE1_8821C)
+#define BIT_SET_NETYPE1_8821C(x, v)                                            \
+	(BIT_CLEAR_NETYPE1_8821C(x) | BIT_NETYPE1_8821C(v))
+
+#define BIT_SHIFT_NETYPE0_8821C 16
+#define BIT_MASK_NETYPE0_8821C 0x3
+#define BIT_NETYPE0_8821C(x)                                                   \
+	(((x) & BIT_MASK_NETYPE0_8821C) << BIT_SHIFT_NETYPE0_8821C)
+#define BITS_NETYPE0_8821C (BIT_MASK_NETYPE0_8821C << BIT_SHIFT_NETYPE0_8821C)
+#define BIT_CLEAR_NETYPE0_8821C(x) ((x) & (~BITS_NETYPE0_8821C))
+#define BIT_GET_NETYPE0_8821C(x)                                               \
+	(((x) >> BIT_SHIFT_NETYPE0_8821C) & BIT_MASK_NETYPE0_8821C)
+#define BIT_SET_NETYPE0_8821C(x, v)                                            \
+	(BIT_CLEAR_NETYPE0_8821C(x) | BIT_NETYPE0_8821C(v))
+
+#define BIT_COUNTER_STS_EN_8821C BIT(13)
+#define BIT_I2C_MAILBOX_EN_8821C BIT(12)
+#define BIT_SHCUT_EN_8821C BIT(11)
+#define BIT_32K_CAL_TMR_EN_8821C BIT(10)
+#define BIT_MAC_SEC_EN_8821C BIT(9)
+#define BIT_ENSWBCN_8821C BIT(8)
+#define BIT_MACRXEN_8821C BIT(7)
+#define BIT_MACTXEN_8821C BIT(6)
+#define BIT_SCHEDULE_EN_8821C BIT(5)
+#define BIT_PROTOCOL_EN_8821C BIT(4)
+#define BIT_RXDMA_EN_8821C BIT(3)
+#define BIT_TXDMA_EN_8821C BIT(2)
+#define BIT_HCI_RXDMA_EN_8821C BIT(1)
+#define BIT_HCI_TXDMA_EN_8821C BIT(0)
+
+/* 2 REG_PG_SIZE_8821C */
+
+#define BIT_SHIFT_DBG_FIFO_SEL_8821C 16
+#define BIT_MASK_DBG_FIFO_SEL_8821C 0xff
+#define BIT_DBG_FIFO_SEL_8821C(x)                                              \
+	(((x) & BIT_MASK_DBG_FIFO_SEL_8821C) << BIT_SHIFT_DBG_FIFO_SEL_8821C)
+#define BITS_DBG_FIFO_SEL_8821C                                                \
+	(BIT_MASK_DBG_FIFO_SEL_8821C << BIT_SHIFT_DBG_FIFO_SEL_8821C)
+#define BIT_CLEAR_DBG_FIFO_SEL_8821C(x) ((x) & (~BITS_DBG_FIFO_SEL_8821C))
+#define BIT_GET_DBG_FIFO_SEL_8821C(x)                                          \
+	(((x) >> BIT_SHIFT_DBG_FIFO_SEL_8821C) & BIT_MASK_DBG_FIFO_SEL_8821C)
+#define BIT_SET_DBG_FIFO_SEL_8821C(x, v)                                       \
+	(BIT_CLEAR_DBG_FIFO_SEL_8821C(x) | BIT_DBG_FIFO_SEL_8821C(v))
+
+/* 2 REG_PKT_BUFF_ACCESS_CTRL_8821C */
+
+#define BIT_SHIFT_PKT_BUFF_ACCESS_CTRL_8821C 0
+#define BIT_MASK_PKT_BUFF_ACCESS_CTRL_8821C 0xff
+#define BIT_PKT_BUFF_ACCESS_CTRL_8821C(x)                                      \
+	(((x) & BIT_MASK_PKT_BUFF_ACCESS_CTRL_8821C)                           \
+	 << BIT_SHIFT_PKT_BUFF_ACCESS_CTRL_8821C)
+#define BITS_PKT_BUFF_ACCESS_CTRL_8821C                                        \
+	(BIT_MASK_PKT_BUFF_ACCESS_CTRL_8821C                                   \
+	 << BIT_SHIFT_PKT_BUFF_ACCESS_CTRL_8821C)
+#define BIT_CLEAR_PKT_BUFF_ACCESS_CTRL_8821C(x)                                \
+	((x) & (~BITS_PKT_BUFF_ACCESS_CTRL_8821C))
+#define BIT_GET_PKT_BUFF_ACCESS_CTRL_8821C(x)                                  \
+	(((x) >> BIT_SHIFT_PKT_BUFF_ACCESS_CTRL_8821C) &                       \
+	 BIT_MASK_PKT_BUFF_ACCESS_CTRL_8821C)
+#define BIT_SET_PKT_BUFF_ACCESS_CTRL_8821C(x, v)                               \
+	(BIT_CLEAR_PKT_BUFF_ACCESS_CTRL_8821C(x) |                             \
+	 BIT_PKT_BUFF_ACCESS_CTRL_8821C(v))
+
+/* 2 REG_TSF_CLK_STATE_8821C */
+#define BIT_TSF_CLK_STABLE_8821C BIT(15)
+
+/* 2 REG_TXDMA_PQ_MAP_8821C */
+
+#define BIT_SHIFT_TXDMA_H2C_MAP_8821C 16
+#define BIT_MASK_TXDMA_H2C_MAP_8821C 0x3
+#define BIT_TXDMA_H2C_MAP_8821C(x)                                             \
+	(((x) & BIT_MASK_TXDMA_H2C_MAP_8821C) << BIT_SHIFT_TXDMA_H2C_MAP_8821C)
+#define BITS_TXDMA_H2C_MAP_8821C                                               \
+	(BIT_MASK_TXDMA_H2C_MAP_8821C << BIT_SHIFT_TXDMA_H2C_MAP_8821C)
+#define BIT_CLEAR_TXDMA_H2C_MAP_8821C(x) ((x) & (~BITS_TXDMA_H2C_MAP_8821C))
+#define BIT_GET_TXDMA_H2C_MAP_8821C(x)                                         \
+	(((x) >> BIT_SHIFT_TXDMA_H2C_MAP_8821C) & BIT_MASK_TXDMA_H2C_MAP_8821C)
+#define BIT_SET_TXDMA_H2C_MAP_8821C(x, v)                                      \
+	(BIT_CLEAR_TXDMA_H2C_MAP_8821C(x) | BIT_TXDMA_H2C_MAP_8821C(v))
+
+#define BIT_SHIFT_TXDMA_HIQ_MAP_8821C 14
+#define BIT_MASK_TXDMA_HIQ_MAP_8821C 0x3
+#define BIT_TXDMA_HIQ_MAP_8821C(x)                                             \
+	(((x) & BIT_MASK_TXDMA_HIQ_MAP_8821C) << BIT_SHIFT_TXDMA_HIQ_MAP_8821C)
+#define BITS_TXDMA_HIQ_MAP_8821C                                               \
+	(BIT_MASK_TXDMA_HIQ_MAP_8821C << BIT_SHIFT_TXDMA_HIQ_MAP_8821C)
+#define BIT_CLEAR_TXDMA_HIQ_MAP_8821C(x) ((x) & (~BITS_TXDMA_HIQ_MAP_8821C))
+#define BIT_GET_TXDMA_HIQ_MAP_8821C(x)                                         \
+	(((x) >> BIT_SHIFT_TXDMA_HIQ_MAP_8821C) & BIT_MASK_TXDMA_HIQ_MAP_8821C)
+#define BIT_SET_TXDMA_HIQ_MAP_8821C(x, v)                                      \
+	(BIT_CLEAR_TXDMA_HIQ_MAP_8821C(x) | BIT_TXDMA_HIQ_MAP_8821C(v))
+
+#define BIT_SHIFT_TXDMA_MGQ_MAP_8821C 12
+#define BIT_MASK_TXDMA_MGQ_MAP_8821C 0x3
+#define BIT_TXDMA_MGQ_MAP_8821C(x)                                             \
+	(((x) & BIT_MASK_TXDMA_MGQ_MAP_8821C) << BIT_SHIFT_TXDMA_MGQ_MAP_8821C)
+#define BITS_TXDMA_MGQ_MAP_8821C                                               \
+	(BIT_MASK_TXDMA_MGQ_MAP_8821C << BIT_SHIFT_TXDMA_MGQ_MAP_8821C)
+#define BIT_CLEAR_TXDMA_MGQ_MAP_8821C(x) ((x) & (~BITS_TXDMA_MGQ_MAP_8821C))
+#define BIT_GET_TXDMA_MGQ_MAP_8821C(x)                                         \
+	(((x) >> BIT_SHIFT_TXDMA_MGQ_MAP_8821C) & BIT_MASK_TXDMA_MGQ_MAP_8821C)
+#define BIT_SET_TXDMA_MGQ_MAP_8821C(x, v)                                      \
+	(BIT_CLEAR_TXDMA_MGQ_MAP_8821C(x) | BIT_TXDMA_MGQ_MAP_8821C(v))
+
+#define BIT_SHIFT_TXDMA_BKQ_MAP_8821C 10
+#define BIT_MASK_TXDMA_BKQ_MAP_8821C 0x3
+#define BIT_TXDMA_BKQ_MAP_8821C(x)                                             \
+	(((x) & BIT_MASK_TXDMA_BKQ_MAP_8821C) << BIT_SHIFT_TXDMA_BKQ_MAP_8821C)
+#define BITS_TXDMA_BKQ_MAP_8821C                                               \
+	(BIT_MASK_TXDMA_BKQ_MAP_8821C << BIT_SHIFT_TXDMA_BKQ_MAP_8821C)
+#define BIT_CLEAR_TXDMA_BKQ_MAP_8821C(x) ((x) & (~BITS_TXDMA_BKQ_MAP_8821C))
+#define BIT_GET_TXDMA_BKQ_MAP_8821C(x)                                         \
+	(((x) >> BIT_SHIFT_TXDMA_BKQ_MAP_8821C) & BIT_MASK_TXDMA_BKQ_MAP_8821C)
+#define BIT_SET_TXDMA_BKQ_MAP_8821C(x, v)                                      \
+	(BIT_CLEAR_TXDMA_BKQ_MAP_8821C(x) | BIT_TXDMA_BKQ_MAP_8821C(v))
+
+#define BIT_SHIFT_TXDMA_BEQ_MAP_8821C 8
+#define BIT_MASK_TXDMA_BEQ_MAP_8821C 0x3
+#define BIT_TXDMA_BEQ_MAP_8821C(x)                                             \
+	(((x) & BIT_MASK_TXDMA_BEQ_MAP_8821C) << BIT_SHIFT_TXDMA_BEQ_MAP_8821C)
+#define BITS_TXDMA_BEQ_MAP_8821C                                               \
+	(BIT_MASK_TXDMA_BEQ_MAP_8821C << BIT_SHIFT_TXDMA_BEQ_MAP_8821C)
+#define BIT_CLEAR_TXDMA_BEQ_MAP_8821C(x) ((x) & (~BITS_TXDMA_BEQ_MAP_8821C))
+#define BIT_GET_TXDMA_BEQ_MAP_8821C(x)                                         \
+	(((x) >> BIT_SHIFT_TXDMA_BEQ_MAP_8821C) & BIT_MASK_TXDMA_BEQ_MAP_8821C)
+#define BIT_SET_TXDMA_BEQ_MAP_8821C(x, v)                                      \
+	(BIT_CLEAR_TXDMA_BEQ_MAP_8821C(x) | BIT_TXDMA_BEQ_MAP_8821C(v))
+
+#define BIT_SHIFT_TXDMA_VIQ_MAP_8821C 6
+#define BIT_MASK_TXDMA_VIQ_MAP_8821C 0x3
+#define BIT_TXDMA_VIQ_MAP_8821C(x)                                             \
+	(((x) & BIT_MASK_TXDMA_VIQ_MAP_8821C) << BIT_SHIFT_TXDMA_VIQ_MAP_8821C)
+#define BITS_TXDMA_VIQ_MAP_8821C                                               \
+	(BIT_MASK_TXDMA_VIQ_MAP_8821C << BIT_SHIFT_TXDMA_VIQ_MAP_8821C)
+#define BIT_CLEAR_TXDMA_VIQ_MAP_8821C(x) ((x) & (~BITS_TXDMA_VIQ_MAP_8821C))
+#define BIT_GET_TXDMA_VIQ_MAP_8821C(x)                                         \
+	(((x) >> BIT_SHIFT_TXDMA_VIQ_MAP_8821C) & BIT_MASK_TXDMA_VIQ_MAP_8821C)
+#define BIT_SET_TXDMA_VIQ_MAP_8821C(x, v)                                      \
+	(BIT_CLEAR_TXDMA_VIQ_MAP_8821C(x) | BIT_TXDMA_VIQ_MAP_8821C(v))
+
+#define BIT_SHIFT_TXDMA_VOQ_MAP_8821C 4
+#define BIT_MASK_TXDMA_VOQ_MAP_8821C 0x3
+#define BIT_TXDMA_VOQ_MAP_8821C(x)                                             \
+	(((x) & BIT_MASK_TXDMA_VOQ_MAP_8821C) << BIT_SHIFT_TXDMA_VOQ_MAP_8821C)
+#define BITS_TXDMA_VOQ_MAP_8821C                                               \
+	(BIT_MASK_TXDMA_VOQ_MAP_8821C << BIT_SHIFT_TXDMA_VOQ_MAP_8821C)
+#define BIT_CLEAR_TXDMA_VOQ_MAP_8821C(x) ((x) & (~BITS_TXDMA_VOQ_MAP_8821C))
+#define BIT_GET_TXDMA_VOQ_MAP_8821C(x)                                         \
+	(((x) >> BIT_SHIFT_TXDMA_VOQ_MAP_8821C) & BIT_MASK_TXDMA_VOQ_MAP_8821C)
+#define BIT_SET_TXDMA_VOQ_MAP_8821C(x, v)                                      \
+	(BIT_CLEAR_TXDMA_VOQ_MAP_8821C(x) | BIT_TXDMA_VOQ_MAP_8821C(v))
+
+#define BIT_RXDMA_AGG_EN_8821C BIT(2)
+#define BIT_RXSHFT_EN_8821C BIT(1)
+#define BIT_RXDMA_ARBBW_EN_8821C BIT(0)
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_TRXFF_BNDY_8821C */
+
+#define BIT_SHIFT_RXFFOVFL_RSV_V2_8821C 8
+#define BIT_MASK_RXFFOVFL_RSV_V2_8821C 0xf
+#define BIT_RXFFOVFL_RSV_V2_8821C(x)                                           \
+	(((x) & BIT_MASK_RXFFOVFL_RSV_V2_8821C)                                \
+	 << BIT_SHIFT_RXFFOVFL_RSV_V2_8821C)
+#define BITS_RXFFOVFL_RSV_V2_8821C                                             \
+	(BIT_MASK_RXFFOVFL_RSV_V2_8821C << BIT_SHIFT_RXFFOVFL_RSV_V2_8821C)
+#define BIT_CLEAR_RXFFOVFL_RSV_V2_8821C(x) ((x) & (~BITS_RXFFOVFL_RSV_V2_8821C))
+#define BIT_GET_RXFFOVFL_RSV_V2_8821C(x)                                       \
+	(((x) >> BIT_SHIFT_RXFFOVFL_RSV_V2_8821C) &                            \
+	 BIT_MASK_RXFFOVFL_RSV_V2_8821C)
+#define BIT_SET_RXFFOVFL_RSV_V2_8821C(x, v)                                    \
+	(BIT_CLEAR_RXFFOVFL_RSV_V2_8821C(x) | BIT_RXFFOVFL_RSV_V2_8821C(v))
+
+/* 2 REG_PTA_I2C_MBOX_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+#define BIT_SHIFT_I2C_M_STATUS_8821C 8
+#define BIT_MASK_I2C_M_STATUS_8821C 0xf
+#define BIT_I2C_M_STATUS_8821C(x)                                              \
+	(((x) & BIT_MASK_I2C_M_STATUS_8821C) << BIT_SHIFT_I2C_M_STATUS_8821C)
+#define BITS_I2C_M_STATUS_8821C                                                \
+	(BIT_MASK_I2C_M_STATUS_8821C << BIT_SHIFT_I2C_M_STATUS_8821C)
+#define BIT_CLEAR_I2C_M_STATUS_8821C(x) ((x) & (~BITS_I2C_M_STATUS_8821C))
+#define BIT_GET_I2C_M_STATUS_8821C(x)                                          \
+	(((x) >> BIT_SHIFT_I2C_M_STATUS_8821C) & BIT_MASK_I2C_M_STATUS_8821C)
+#define BIT_SET_I2C_M_STATUS_8821C(x, v)                                       \
+	(BIT_CLEAR_I2C_M_STATUS_8821C(x) | BIT_I2C_M_STATUS_8821C(v))
+
+#define BIT_SHIFT_I2C_M_BUS_GNT_FW_8821C 4
+#define BIT_MASK_I2C_M_BUS_GNT_FW_8821C 0x7
+#define BIT_I2C_M_BUS_GNT_FW_8821C(x)                                          \
+	(((x) & BIT_MASK_I2C_M_BUS_GNT_FW_8821C)                               \
+	 << BIT_SHIFT_I2C_M_BUS_GNT_FW_8821C)
+#define BITS_I2C_M_BUS_GNT_FW_8821C                                            \
+	(BIT_MASK_I2C_M_BUS_GNT_FW_8821C << BIT_SHIFT_I2C_M_BUS_GNT_FW_8821C)
+#define BIT_CLEAR_I2C_M_BUS_GNT_FW_8821C(x)                                    \
+	((x) & (~BITS_I2C_M_BUS_GNT_FW_8821C))
+#define BIT_GET_I2C_M_BUS_GNT_FW_8821C(x)                                      \
+	(((x) >> BIT_SHIFT_I2C_M_BUS_GNT_FW_8821C) &                           \
+	 BIT_MASK_I2C_M_BUS_GNT_FW_8821C)
+#define BIT_SET_I2C_M_BUS_GNT_FW_8821C(x, v)                                   \
+	(BIT_CLEAR_I2C_M_BUS_GNT_FW_8821C(x) | BIT_I2C_M_BUS_GNT_FW_8821C(v))
+
+#define BIT_I2C_M_GNT_FW_8821C BIT(3)
+
+#define BIT_SHIFT_I2C_M_SPEED_8821C 1
+#define BIT_MASK_I2C_M_SPEED_8821C 0x3
+#define BIT_I2C_M_SPEED_8821C(x)                                               \
+	(((x) & BIT_MASK_I2C_M_SPEED_8821C) << BIT_SHIFT_I2C_M_SPEED_8821C)
+#define BITS_I2C_M_SPEED_8821C                                                 \
+	(BIT_MASK_I2C_M_SPEED_8821C << BIT_SHIFT_I2C_M_SPEED_8821C)
+#define BIT_CLEAR_I2C_M_SPEED_8821C(x) ((x) & (~BITS_I2C_M_SPEED_8821C))
+#define BIT_GET_I2C_M_SPEED_8821C(x)                                           \
+	(((x) >> BIT_SHIFT_I2C_M_SPEED_8821C) & BIT_MASK_I2C_M_SPEED_8821C)
+#define BIT_SET_I2C_M_SPEED_8821C(x, v)                                        \
+	(BIT_CLEAR_I2C_M_SPEED_8821C(x) | BIT_I2C_M_SPEED_8821C(v))
+
+#define BIT_I2C_M_UNLOCK_8821C BIT(0)
+
+/* 2 REG_RXFF_BNDY_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+#define BIT_SHIFT_RXFF0_BNDY_V2_8821C 0
+#define BIT_MASK_RXFF0_BNDY_V2_8821C 0x3ffff
+#define BIT_RXFF0_BNDY_V2_8821C(x)                                             \
+	(((x) & BIT_MASK_RXFF0_BNDY_V2_8821C) << BIT_SHIFT_RXFF0_BNDY_V2_8821C)
+#define BITS_RXFF0_BNDY_V2_8821C                                               \
+	(BIT_MASK_RXFF0_BNDY_V2_8821C << BIT_SHIFT_RXFF0_BNDY_V2_8821C)
+#define BIT_CLEAR_RXFF0_BNDY_V2_8821C(x) ((x) & (~BITS_RXFF0_BNDY_V2_8821C))
+#define BIT_GET_RXFF0_BNDY_V2_8821C(x)                                         \
+	(((x) >> BIT_SHIFT_RXFF0_BNDY_V2_8821C) & BIT_MASK_RXFF0_BNDY_V2_8821C)
+#define BIT_SET_RXFF0_BNDY_V2_8821C(x, v)                                      \
+	(BIT_CLEAR_RXFF0_BNDY_V2_8821C(x) | BIT_RXFF0_BNDY_V2_8821C(v))
+
+/* 2 REG_FE1IMR_8821C */
+#define BIT_FS_RXDMA2_DONE_INT_EN_8821C BIT(28)
+#define BIT_FS_RXDONE3_INT_EN_8821C BIT(27)
+#define BIT_FS_RXDONE2_INT_EN_8821C BIT(26)
+#define BIT_FS_RX_BCN_P4_INT_EN_8821C BIT(25)
+#define BIT_FS_RX_BCN_P3_INT_EN_8821C BIT(24)
+#define BIT_FS_RX_BCN_P2_INT_EN_8821C BIT(23)
+#define BIT_FS_RX_BCN_P1_INT_EN_8821C BIT(22)
+#define BIT_FS_RX_BCN_P0_INT_EN_8821C BIT(21)
+#define BIT_FS_RX_UMD0_INT_EN_8821C BIT(20)
+#define BIT_FS_RX_UMD1_INT_EN_8821C BIT(19)
+#define BIT_FS_RX_BMD0_INT_EN_8821C BIT(18)
+#define BIT_FS_RX_BMD1_INT_EN_8821C BIT(17)
+#define BIT_FS_RXDONE_INT_EN_8821C BIT(16)
+#define BIT_FS_WWLAN_INT_EN_8821C BIT(15)
+#define BIT_FS_SOUND_DONE_INT_EN_8821C BIT(14)
+#define BIT_FS_LP_STBY_INT_EN_8821C BIT(13)
+#define BIT_FS_TRL_MTR_INT_EN_8821C BIT(12)
+#define BIT_FS_BF1_PRETO_INT_EN_8821C BIT(11)
+#define BIT_FS_BF0_PRETO_INT_EN_8821C BIT(10)
+#define BIT_FS_PTCL_RELEASE_MACID_INT_EN_8821C BIT(9)
+#define BIT_FS_LTE_COEX_EN_8821C BIT(6)
+#define BIT_FS_WLACTOFF_INT_EN_8821C BIT(5)
+#define BIT_FS_WLACTON_INT_EN_8821C BIT(4)
+#define BIT_FS_BTCMD_INT_EN_8821C BIT(3)
+#define BIT_FS_REG_MAILBOX_TO_I2C_INT_EN_8821C BIT(2)
+#define BIT_FS_TRPC_TO_INT_EN_V1_8821C BIT(1)
+#define BIT_FS_RPC_O_T_INT_EN_V1_8821C BIT(0)
+
+/* 2 REG_FE1ISR_8821C */
+#define BIT_FS_RXDMA2_DONE_INT_8821C BIT(28)
+#define BIT_FS_RXDONE3_INT_8821C BIT(27)
+#define BIT_FS_RXDONE2_INT_8821C BIT(26)
+#define BIT_FS_RX_BCN_P4_INT_8821C BIT(25)
+#define BIT_FS_RX_BCN_P3_INT_8821C BIT(24)
+#define BIT_FS_RX_BCN_P2_INT_8821C BIT(23)
+#define BIT_FS_RX_BCN_P1_INT_8821C BIT(22)
+#define BIT_FS_RX_BCN_P0_INT_8821C BIT(21)
+#define BIT_FS_RX_UMD0_INT_8821C BIT(20)
+#define BIT_FS_RX_UMD1_INT_8821C BIT(19)
+#define BIT_FS_RX_BMD0_INT_8821C BIT(18)
+#define BIT_FS_RX_BMD1_INT_8821C BIT(17)
+#define BIT_FS_RXDONE_INT_8821C BIT(16)
+#define BIT_FS_WWLAN_INT_8821C BIT(15)
+#define BIT_FS_SOUND_DONE_INT_8821C BIT(14)
+#define BIT_FS_LP_STBY_INT_8821C BIT(13)
+#define BIT_FS_TRL_MTR_INT_8821C BIT(12)
+#define BIT_FS_BF1_PRETO_INT_8821C BIT(11)
+#define BIT_FS_BF0_PRETO_INT_8821C BIT(10)
+#define BIT_FS_PTCL_RELEASE_MACID_INT_8821C BIT(9)
+#define BIT_FS_LTE_COEX_INT_8821C BIT(6)
+#define BIT_FS_WLACTOFF_INT_8821C BIT(5)
+#define BIT_FS_WLACTON_INT_8821C BIT(4)
+#define BIT_FS_BCN_RX_INT_INT_8821C BIT(3)
+#define BIT_FS_MAILBOX_TO_I2C_INT_8821C BIT(2)
+#define BIT_FS_TRPC_TO_INT_8821C BIT(1)
+#define BIT_FS_RPC_O_T_INT_8821C BIT(0)
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_CPWM_8821C */
+#define BIT_CPWM_TOGGLING_8821C BIT(31)
+
+#define BIT_SHIFT_CPWM_MOD_8821C 24
+#define BIT_MASK_CPWM_MOD_8821C 0x7f
+#define BIT_CPWM_MOD_8821C(x)                                                  \
+	(((x) & BIT_MASK_CPWM_MOD_8821C) << BIT_SHIFT_CPWM_MOD_8821C)
+#define BITS_CPWM_MOD_8821C                                                    \
+	(BIT_MASK_CPWM_MOD_8821C << BIT_SHIFT_CPWM_MOD_8821C)
+#define BIT_CLEAR_CPWM_MOD_8821C(x) ((x) & (~BITS_CPWM_MOD_8821C))
+#define BIT_GET_CPWM_MOD_8821C(x)                                              \
+	(((x) >> BIT_SHIFT_CPWM_MOD_8821C) & BIT_MASK_CPWM_MOD_8821C)
+#define BIT_SET_CPWM_MOD_8821C(x, v)                                           \
+	(BIT_CLEAR_CPWM_MOD_8821C(x) | BIT_CPWM_MOD_8821C(v))
+
+/* 2 REG_FWIMR_8821C */
+#define BIT_FS_TXBCNOK_MB7_INT_EN_8821C BIT(31)
+#define BIT_FS_TXBCNOK_MB6_INT_EN_8821C BIT(30)
+#define BIT_FS_TXBCNOK_MB5_INT_EN_8821C BIT(29)
+#define BIT_FS_TXBCNOK_MB4_INT_EN_8821C BIT(28)
+#define BIT_FS_TXBCNOK_MB3_INT_EN_8821C BIT(27)
+#define BIT_FS_TXBCNOK_MB2_INT_EN_8821C BIT(26)
+#define BIT_FS_TXBCNOK_MB1_INT_EN_8821C BIT(25)
+#define BIT_FS_TXBCNOK_MB0_INT_EN_8821C BIT(24)
+#define BIT_FS_TXBCNERR_MB7_INT_EN_8821C BIT(23)
+#define BIT_FS_TXBCNERR_MB6_INT_EN_8821C BIT(22)
+#define BIT_FS_TXBCNERR_MB5_INT_EN_8821C BIT(21)
+#define BIT_FS_TXBCNERR_MB4_INT_EN_8821C BIT(20)
+#define BIT_FS_TXBCNERR_MB3_INT_EN_8821C BIT(19)
+#define BIT_FS_TXBCNERR_MB2_INT_EN_8821C BIT(18)
+#define BIT_FS_TXBCNERR_MB1_INT_EN_8821C BIT(17)
+#define BIT_FS_TXBCNERR_MB0_INT_EN_8821C BIT(16)
+#define BIT_CPU_MGQ_TXDONE_INT_EN_8821C BIT(15)
+#define BIT_SIFS_OVERSPEC_INT_EN_8821C BIT(14)
+#define BIT_FS_MGNTQ_RPTR_RELEASE_INT_EN_8821C BIT(13)
+#define BIT_FS_MGNTQFF_TO_INT_EN_8821C BIT(12)
+#define BIT_FS_DDMA1_LP_INT_EN_8821C BIT(11)
+#define BIT_FS_DDMA1_HP_INT_EN_8821C BIT(10)
+#define BIT_FS_DDMA0_LP_INT_EN_8821C BIT(9)
+#define BIT_FS_DDMA0_HP_INT_EN_8821C BIT(8)
+#define BIT_FS_TRXRPT_INT_EN_8821C BIT(7)
+#define BIT_FS_C2H_W_READY_INT_EN_8821C BIT(6)
+#define BIT_FS_HRCV_INT_EN_8821C BIT(5)
+#define BIT_FS_H2CCMD_INT_EN_8821C BIT(4)
+#define BIT_FS_TXPKTIN_INT_EN_8821C BIT(3)
+#define BIT_FS_ERRORHDL_INT_EN_8821C BIT(2)
+#define BIT_FS_TXCCX_INT_EN_8821C BIT(1)
+#define BIT_FS_TXCLOSE_INT_EN_8821C BIT(0)
+
+/* 2 REG_FWISR_8821C */
+#define BIT_FS_TXBCNOK_MB7_INT_8821C BIT(31)
+#define BIT_FS_TXBCNOK_MB6_INT_8821C BIT(30)
+#define BIT_FS_TXBCNOK_MB5_INT_8821C BIT(29)
+#define BIT_FS_TXBCNOK_MB4_INT_8821C BIT(28)
+#define BIT_FS_TXBCNOK_MB3_INT_8821C BIT(27)
+#define BIT_FS_TXBCNOK_MB2_INT_8821C BIT(26)
+#define BIT_FS_TXBCNOK_MB1_INT_8821C BIT(25)
+#define BIT_FS_TXBCNOK_MB0_INT_8821C BIT(24)
+#define BIT_FS_TXBCNERR_MB7_INT_8821C BIT(23)
+#define BIT_FS_TXBCNERR_MB6_INT_8821C BIT(22)
+#define BIT_FS_TXBCNERR_MB5_INT_8821C BIT(21)
+#define BIT_FS_TXBCNERR_MB4_INT_8821C BIT(20)
+#define BIT_FS_TXBCNERR_MB3_INT_8821C BIT(19)
+#define BIT_FS_TXBCNERR_MB2_INT_8821C BIT(18)
+#define BIT_FS_TXBCNERR_MB1_INT_8821C BIT(17)
+#define BIT_FS_TXBCNERR_MB0_INT_8821C BIT(16)
+#define BIT_CPU_MGQ_TXDONE_INT_8821C BIT(15)
+#define BIT_SIFS_OVERSPEC_INT_8821C BIT(14)
+#define BIT_FS_MGNTQ_RPTR_RELEASE_INT_8821C BIT(13)
+#define BIT_FS_MGNTQFF_TO_INT_8821C BIT(12)
+#define BIT_FS_DDMA1_LP_INT_8821C BIT(11)
+#define BIT_FS_DDMA1_HP_INT_8821C BIT(10)
+#define BIT_FS_DDMA0_LP_INT_8821C BIT(9)
+#define BIT_FS_DDMA0_HP_INT_8821C BIT(8)
+#define BIT_FS_TRXRPT_INT_8821C BIT(7)
+#define BIT_FS_C2H_W_READY_INT_8821C BIT(6)
+#define BIT_FS_HRCV_INT_8821C BIT(5)
+#define BIT_FS_H2CCMD_INT_8821C BIT(4)
+#define BIT_FS_TXPKTIN_INT_8821C BIT(3)
+#define BIT_FS_ERRORHDL_INT_8821C BIT(2)
+#define BIT_FS_TXCCX_INT_8821C BIT(1)
+#define BIT_FS_TXCLOSE_INT_8821C BIT(0)
+
+/* 2 REG_FTIMR_8821C */
+#define BIT_PS_TIMER_C_EARLY_INT_EN_8821C BIT(23)
+#define BIT_PS_TIMER_B_EARLY_INT_EN_8821C BIT(22)
+#define BIT_PS_TIMER_A_EARLY_INT_EN_8821C BIT(21)
+#define BIT_CPUMGQ_TX_TIMER_EARLY_INT_EN_8821C BIT(20)
+#define BIT_PS_TIMER_C_INT_EN_8821C BIT(19)
+#define BIT_PS_TIMER_B_INT_EN_8821C BIT(18)
+#define BIT_PS_TIMER_A_INT_EN_8821C BIT(17)
+#define BIT_CPUMGQ_TX_TIMER_INT_EN_8821C BIT(16)
+#define BIT_FS_PS_TIMEOUT2_EN_8821C BIT(15)
+#define BIT_FS_PS_TIMEOUT1_EN_8821C BIT(14)
+#define BIT_FS_PS_TIMEOUT0_EN_8821C BIT(13)
+#define BIT_FS_GTINT8_EN_8821C BIT(8)
+#define BIT_FS_GTINT7_EN_8821C BIT(7)
+#define BIT_FS_GTINT6_EN_8821C BIT(6)
+#define BIT_FS_GTINT5_EN_8821C BIT(5)
+#define BIT_FS_GTINT4_EN_8821C BIT(4)
+#define BIT_FS_GTINT3_EN_8821C BIT(3)
+#define BIT_FS_GTINT2_EN_8821C BIT(2)
+#define BIT_FS_GTINT1_EN_8821C BIT(1)
+#define BIT_FS_GTINT0_EN_8821C BIT(0)
+
+/* 2 REG_FTISR_8821C */
+#define BIT_PS_TIMER_C_EARLY__INT_8821C BIT(23)
+#define BIT_PS_TIMER_B_EARLY__INT_8821C BIT(22)
+#define BIT_PS_TIMER_A_EARLY__INT_8821C BIT(21)
+#define BIT_CPUMGQ_TX_TIMER_EARLY_INT_8821C BIT(20)
+#define BIT_PS_TIMER_C_INT_8821C BIT(19)
+#define BIT_PS_TIMER_B_INT_8821C BIT(18)
+#define BIT_PS_TIMER_A_INT_8821C BIT(17)
+#define BIT_CPUMGQ_TX_TIMER_INT_8821C BIT(16)
+#define BIT_FS_PS_TIMEOUT2_INT_8821C BIT(15)
+#define BIT_FS_PS_TIMEOUT1_INT_8821C BIT(14)
+#define BIT_FS_PS_TIMEOUT0_INT_8821C BIT(13)
+#define BIT_FS_GTINT8_INT_8821C BIT(8)
+#define BIT_FS_GTINT7_INT_8821C BIT(7)
+#define BIT_FS_GTINT6_INT_8821C BIT(6)
+#define BIT_FS_GTINT5_INT_8821C BIT(5)
+#define BIT_FS_GTINT4_INT_8821C BIT(4)
+#define BIT_FS_GTINT3_INT_8821C BIT(3)
+#define BIT_FS_GTINT2_INT_8821C BIT(2)
+#define BIT_FS_GTINT1_INT_8821C BIT(1)
+#define BIT_FS_GTINT0_INT_8821C BIT(0)
+
+/* 2 REG_PKTBUF_DBG_CTRL_8821C */
+
+#define BIT_SHIFT_PKTBUF_WRITE_EN_8821C 24
+#define BIT_MASK_PKTBUF_WRITE_EN_8821C 0xff
+#define BIT_PKTBUF_WRITE_EN_8821C(x)                                           \
+	(((x) & BIT_MASK_PKTBUF_WRITE_EN_8821C)                                \
+	 << BIT_SHIFT_PKTBUF_WRITE_EN_8821C)
+#define BITS_PKTBUF_WRITE_EN_8821C                                             \
+	(BIT_MASK_PKTBUF_WRITE_EN_8821C << BIT_SHIFT_PKTBUF_WRITE_EN_8821C)
+#define BIT_CLEAR_PKTBUF_WRITE_EN_8821C(x) ((x) & (~BITS_PKTBUF_WRITE_EN_8821C))
+#define BIT_GET_PKTBUF_WRITE_EN_8821C(x)                                       \
+	(((x) >> BIT_SHIFT_PKTBUF_WRITE_EN_8821C) &                            \
+	 BIT_MASK_PKTBUF_WRITE_EN_8821C)
+#define BIT_SET_PKTBUF_WRITE_EN_8821C(x, v)                                    \
+	(BIT_CLEAR_PKTBUF_WRITE_EN_8821C(x) | BIT_PKTBUF_WRITE_EN_8821C(v))
+
+#define BIT_TXRPTBUF_DBG_8821C BIT(23)
+
+/* 2 REG_NOT_VALID_8821C */
+#define BIT_TXPKTBUF_DBG_V2_8821C BIT(20)
+#define BIT_RXPKTBUF_DBG_8821C BIT(16)
+
+#define BIT_SHIFT_PKTBUF_DBG_ADDR_8821C 0
+#define BIT_MASK_PKTBUF_DBG_ADDR_8821C 0x1fff
+#define BIT_PKTBUF_DBG_ADDR_8821C(x)                                           \
+	(((x) & BIT_MASK_PKTBUF_DBG_ADDR_8821C)                                \
+	 << BIT_SHIFT_PKTBUF_DBG_ADDR_8821C)
+#define BITS_PKTBUF_DBG_ADDR_8821C                                             \
+	(BIT_MASK_PKTBUF_DBG_ADDR_8821C << BIT_SHIFT_PKTBUF_DBG_ADDR_8821C)
+#define BIT_CLEAR_PKTBUF_DBG_ADDR_8821C(x) ((x) & (~BITS_PKTBUF_DBG_ADDR_8821C))
+#define BIT_GET_PKTBUF_DBG_ADDR_8821C(x)                                       \
+	(((x) >> BIT_SHIFT_PKTBUF_DBG_ADDR_8821C) &                            \
+	 BIT_MASK_PKTBUF_DBG_ADDR_8821C)
+#define BIT_SET_PKTBUF_DBG_ADDR_8821C(x, v)                                    \
+	(BIT_CLEAR_PKTBUF_DBG_ADDR_8821C(x) | BIT_PKTBUF_DBG_ADDR_8821C(v))
+
+/* 2 REG_PKTBUF_DBG_DATA_L_8821C */
+
+#define BIT_SHIFT_PKTBUF_DBG_DATA_L_8821C 0
+#define BIT_MASK_PKTBUF_DBG_DATA_L_8821C 0xffffffffL
+#define BIT_PKTBUF_DBG_DATA_L_8821C(x)                                         \
+	(((x) & BIT_MASK_PKTBUF_DBG_DATA_L_8821C)                              \
+	 << BIT_SHIFT_PKTBUF_DBG_DATA_L_8821C)
+#define BITS_PKTBUF_DBG_DATA_L_8821C                                           \
+	(BIT_MASK_PKTBUF_DBG_DATA_L_8821C << BIT_SHIFT_PKTBUF_DBG_DATA_L_8821C)
+#define BIT_CLEAR_PKTBUF_DBG_DATA_L_8821C(x)                                   \
+	((x) & (~BITS_PKTBUF_DBG_DATA_L_8821C))
+#define BIT_GET_PKTBUF_DBG_DATA_L_8821C(x)                                     \
+	(((x) >> BIT_SHIFT_PKTBUF_DBG_DATA_L_8821C) &                          \
+	 BIT_MASK_PKTBUF_DBG_DATA_L_8821C)
+#define BIT_SET_PKTBUF_DBG_DATA_L_8821C(x, v)                                  \
+	(BIT_CLEAR_PKTBUF_DBG_DATA_L_8821C(x) | BIT_PKTBUF_DBG_DATA_L_8821C(v))
+
+/* 2 REG_PKTBUF_DBG_DATA_H_8821C */
+
+#define BIT_SHIFT_PKTBUF_DBG_DATA_H_8821C 0
+#define BIT_MASK_PKTBUF_DBG_DATA_H_8821C 0xffffffffL
+#define BIT_PKTBUF_DBG_DATA_H_8821C(x)                                         \
+	(((x) & BIT_MASK_PKTBUF_DBG_DATA_H_8821C)                              \
+	 << BIT_SHIFT_PKTBUF_DBG_DATA_H_8821C)
+#define BITS_PKTBUF_DBG_DATA_H_8821C                                           \
+	(BIT_MASK_PKTBUF_DBG_DATA_H_8821C << BIT_SHIFT_PKTBUF_DBG_DATA_H_8821C)
+#define BIT_CLEAR_PKTBUF_DBG_DATA_H_8821C(x)                                   \
+	((x) & (~BITS_PKTBUF_DBG_DATA_H_8821C))
+#define BIT_GET_PKTBUF_DBG_DATA_H_8821C(x)                                     \
+	(((x) >> BIT_SHIFT_PKTBUF_DBG_DATA_H_8821C) &                          \
+	 BIT_MASK_PKTBUF_DBG_DATA_H_8821C)
+#define BIT_SET_PKTBUF_DBG_DATA_H_8821C(x, v)                                  \
+	(BIT_CLEAR_PKTBUF_DBG_DATA_H_8821C(x) | BIT_PKTBUF_DBG_DATA_H_8821C(v))
+
+/* 2 REG_CPWM2_8821C */
+
+#define BIT_SHIFT_L0S_TO_RCVY_NUM_8821C 16
+#define BIT_MASK_L0S_TO_RCVY_NUM_8821C 0xff
+#define BIT_L0S_TO_RCVY_NUM_8821C(x)                                           \
+	(((x) & BIT_MASK_L0S_TO_RCVY_NUM_8821C)                                \
+	 << BIT_SHIFT_L0S_TO_RCVY_NUM_8821C)
+#define BITS_L0S_TO_RCVY_NUM_8821C                                             \
+	(BIT_MASK_L0S_TO_RCVY_NUM_8821C << BIT_SHIFT_L0S_TO_RCVY_NUM_8821C)
+#define BIT_CLEAR_L0S_TO_RCVY_NUM_8821C(x) ((x) & (~BITS_L0S_TO_RCVY_NUM_8821C))
+#define BIT_GET_L0S_TO_RCVY_NUM_8821C(x)                                       \
+	(((x) >> BIT_SHIFT_L0S_TO_RCVY_NUM_8821C) &                            \
+	 BIT_MASK_L0S_TO_RCVY_NUM_8821C)
+#define BIT_SET_L0S_TO_RCVY_NUM_8821C(x, v)                                    \
+	(BIT_CLEAR_L0S_TO_RCVY_NUM_8821C(x) | BIT_L0S_TO_RCVY_NUM_8821C(v))
+
+#define BIT_CPWM2_TOGGLING_8821C BIT(15)
+
+#define BIT_SHIFT_CPWM2_MOD_8821C 0
+#define BIT_MASK_CPWM2_MOD_8821C 0x7fff
+#define BIT_CPWM2_MOD_8821C(x)                                                 \
+	(((x) & BIT_MASK_CPWM2_MOD_8821C) << BIT_SHIFT_CPWM2_MOD_8821C)
+#define BITS_CPWM2_MOD_8821C                                                   \
+	(BIT_MASK_CPWM2_MOD_8821C << BIT_SHIFT_CPWM2_MOD_8821C)
+#define BIT_CLEAR_CPWM2_MOD_8821C(x) ((x) & (~BITS_CPWM2_MOD_8821C))
+#define BIT_GET_CPWM2_MOD_8821C(x)                                             \
+	(((x) >> BIT_SHIFT_CPWM2_MOD_8821C) & BIT_MASK_CPWM2_MOD_8821C)
+#define BIT_SET_CPWM2_MOD_8821C(x, v)                                          \
+	(BIT_CLEAR_CPWM2_MOD_8821C(x) | BIT_CPWM2_MOD_8821C(v))
+
+/* 2 REG_TC0_CTRL_8821C */
+#define BIT_TC0INT_EN_8821C BIT(26)
+#define BIT_TC0MODE_8821C BIT(25)
+#define BIT_TC0EN_8821C BIT(24)
+
+#define BIT_SHIFT_TC0DATA_8821C 0
+#define BIT_MASK_TC0DATA_8821C 0xffffff
+#define BIT_TC0DATA_8821C(x)                                                   \
+	(((x) & BIT_MASK_TC0DATA_8821C) << BIT_SHIFT_TC0DATA_8821C)
+#define BITS_TC0DATA_8821C (BIT_MASK_TC0DATA_8821C << BIT_SHIFT_TC0DATA_8821C)
+#define BIT_CLEAR_TC0DATA_8821C(x) ((x) & (~BITS_TC0DATA_8821C))
+#define BIT_GET_TC0DATA_8821C(x)                                               \
+	(((x) >> BIT_SHIFT_TC0DATA_8821C) & BIT_MASK_TC0DATA_8821C)
+#define BIT_SET_TC0DATA_8821C(x, v)                                            \
+	(BIT_CLEAR_TC0DATA_8821C(x) | BIT_TC0DATA_8821C(v))
+
+/* 2 REG_TC1_CTRL_8821C */
+#define BIT_TC1INT_EN_8821C BIT(26)
+#define BIT_TC1MODE_8821C BIT(25)
+#define BIT_TC1EN_8821C BIT(24)
+
+#define BIT_SHIFT_TC1DATA_8821C 0
+#define BIT_MASK_TC1DATA_8821C 0xffffff
+#define BIT_TC1DATA_8821C(x)                                                   \
+	(((x) & BIT_MASK_TC1DATA_8821C) << BIT_SHIFT_TC1DATA_8821C)
+#define BITS_TC1DATA_8821C (BIT_MASK_TC1DATA_8821C << BIT_SHIFT_TC1DATA_8821C)
+#define BIT_CLEAR_TC1DATA_8821C(x) ((x) & (~BITS_TC1DATA_8821C))
+#define BIT_GET_TC1DATA_8821C(x)                                               \
+	(((x) >> BIT_SHIFT_TC1DATA_8821C) & BIT_MASK_TC1DATA_8821C)
+#define BIT_SET_TC1DATA_8821C(x, v)                                            \
+	(BIT_CLEAR_TC1DATA_8821C(x) | BIT_TC1DATA_8821C(v))
+
+/* 2 REG_TC2_CTRL_8821C */
+#define BIT_TC2INT_EN_8821C BIT(26)
+#define BIT_TC2MODE_8821C BIT(25)
+#define BIT_TC2EN_8821C BIT(24)
+
+#define BIT_SHIFT_TC2DATA_8821C 0
+#define BIT_MASK_TC2DATA_8821C 0xffffff
+#define BIT_TC2DATA_8821C(x)                                                   \
+	(((x) & BIT_MASK_TC2DATA_8821C) << BIT_SHIFT_TC2DATA_8821C)
+#define BITS_TC2DATA_8821C (BIT_MASK_TC2DATA_8821C << BIT_SHIFT_TC2DATA_8821C)
+#define BIT_CLEAR_TC2DATA_8821C(x) ((x) & (~BITS_TC2DATA_8821C))
+#define BIT_GET_TC2DATA_8821C(x)                                               \
+	(((x) >> BIT_SHIFT_TC2DATA_8821C) & BIT_MASK_TC2DATA_8821C)
+#define BIT_SET_TC2DATA_8821C(x, v)                                            \
+	(BIT_CLEAR_TC2DATA_8821C(x) | BIT_TC2DATA_8821C(v))
+
+/* 2 REG_TC3_CTRL_8821C */
+#define BIT_TC3INT_EN_8821C BIT(26)
+#define BIT_TC3MODE_8821C BIT(25)
+#define BIT_TC3EN_8821C BIT(24)
+
+#define BIT_SHIFT_TC3DATA_8821C 0
+#define BIT_MASK_TC3DATA_8821C 0xffffff
+#define BIT_TC3DATA_8821C(x)                                                   \
+	(((x) & BIT_MASK_TC3DATA_8821C) << BIT_SHIFT_TC3DATA_8821C)
+#define BITS_TC3DATA_8821C (BIT_MASK_TC3DATA_8821C << BIT_SHIFT_TC3DATA_8821C)
+#define BIT_CLEAR_TC3DATA_8821C(x) ((x) & (~BITS_TC3DATA_8821C))
+#define BIT_GET_TC3DATA_8821C(x)                                               \
+	(((x) >> BIT_SHIFT_TC3DATA_8821C) & BIT_MASK_TC3DATA_8821C)
+#define BIT_SET_TC3DATA_8821C(x, v)                                            \
+	(BIT_CLEAR_TC3DATA_8821C(x) | BIT_TC3DATA_8821C(v))
+
+/* 2 REG_TC4_CTRL_8821C */
+#define BIT_TC4INT_EN_8821C BIT(26)
+#define BIT_TC4MODE_8821C BIT(25)
+#define BIT_TC4EN_8821C BIT(24)
+
+#define BIT_SHIFT_TC4DATA_8821C 0
+#define BIT_MASK_TC4DATA_8821C 0xffffff
+#define BIT_TC4DATA_8821C(x)                                                   \
+	(((x) & BIT_MASK_TC4DATA_8821C) << BIT_SHIFT_TC4DATA_8821C)
+#define BITS_TC4DATA_8821C (BIT_MASK_TC4DATA_8821C << BIT_SHIFT_TC4DATA_8821C)
+#define BIT_CLEAR_TC4DATA_8821C(x) ((x) & (~BITS_TC4DATA_8821C))
+#define BIT_GET_TC4DATA_8821C(x)                                               \
+	(((x) >> BIT_SHIFT_TC4DATA_8821C) & BIT_MASK_TC4DATA_8821C)
+#define BIT_SET_TC4DATA_8821C(x, v)                                            \
+	(BIT_CLEAR_TC4DATA_8821C(x) | BIT_TC4DATA_8821C(v))
+
+/* 2 REG_TCUNIT_BASE_8821C */
+
+#define BIT_SHIFT_TCUNIT_BASE_8821C 0
+#define BIT_MASK_TCUNIT_BASE_8821C 0x3fff
+#define BIT_TCUNIT_BASE_8821C(x)                                               \
+	(((x) & BIT_MASK_TCUNIT_BASE_8821C) << BIT_SHIFT_TCUNIT_BASE_8821C)
+#define BITS_TCUNIT_BASE_8821C                                                 \
+	(BIT_MASK_TCUNIT_BASE_8821C << BIT_SHIFT_TCUNIT_BASE_8821C)
+#define BIT_CLEAR_TCUNIT_BASE_8821C(x) ((x) & (~BITS_TCUNIT_BASE_8821C))
+#define BIT_GET_TCUNIT_BASE_8821C(x)                                           \
+	(((x) >> BIT_SHIFT_TCUNIT_BASE_8821C) & BIT_MASK_TCUNIT_BASE_8821C)
+#define BIT_SET_TCUNIT_BASE_8821C(x, v)                                        \
+	(BIT_CLEAR_TCUNIT_BASE_8821C(x) | BIT_TCUNIT_BASE_8821C(v))
+
+/* 2 REG_TC5_CTRL_8821C */
+#define BIT_TC5INT_EN_8821C BIT(26)
+#define BIT_TC5MODE_8821C BIT(25)
+#define BIT_TC5EN_8821C BIT(24)
+
+#define BIT_SHIFT_TC5DATA_8821C 0
+#define BIT_MASK_TC5DATA_8821C 0xffffff
+#define BIT_TC5DATA_8821C(x)                                                   \
+	(((x) & BIT_MASK_TC5DATA_8821C) << BIT_SHIFT_TC5DATA_8821C)
+#define BITS_TC5DATA_8821C (BIT_MASK_TC5DATA_8821C << BIT_SHIFT_TC5DATA_8821C)
+#define BIT_CLEAR_TC5DATA_8821C(x) ((x) & (~BITS_TC5DATA_8821C))
+#define BIT_GET_TC5DATA_8821C(x)                                               \
+	(((x) >> BIT_SHIFT_TC5DATA_8821C) & BIT_MASK_TC5DATA_8821C)
+#define BIT_SET_TC5DATA_8821C(x, v)                                            \
+	(BIT_CLEAR_TC5DATA_8821C(x) | BIT_TC5DATA_8821C(v))
+
+/* 2 REG_TC6_CTRL_8821C */
+#define BIT_TC6INT_EN_8821C BIT(26)
+#define BIT_TC6MODE_8821C BIT(25)
+#define BIT_TC6EN_8821C BIT(24)
+
+#define BIT_SHIFT_TC6DATA_8821C 0
+#define BIT_MASK_TC6DATA_8821C 0xffffff
+#define BIT_TC6DATA_8821C(x)                                                   \
+	(((x) & BIT_MASK_TC6DATA_8821C) << BIT_SHIFT_TC6DATA_8821C)
+#define BITS_TC6DATA_8821C (BIT_MASK_TC6DATA_8821C << BIT_SHIFT_TC6DATA_8821C)
+#define BIT_CLEAR_TC6DATA_8821C(x) ((x) & (~BITS_TC6DATA_8821C))
+#define BIT_GET_TC6DATA_8821C(x)                                               \
+	(((x) >> BIT_SHIFT_TC6DATA_8821C) & BIT_MASK_TC6DATA_8821C)
+#define BIT_SET_TC6DATA_8821C(x, v)                                            \
+	(BIT_CLEAR_TC6DATA_8821C(x) | BIT_TC6DATA_8821C(v))
+
+/* 2 REG_MBIST_DRF_FAIL_8821C */
+
+#define BIT_SHIFT_8051_MBIST_DRF_FAIL_8821C 26
+#define BIT_MASK_8051_MBIST_DRF_FAIL_8821C 0x3f
+#define BIT_8051_MBIST_DRF_FAIL_8821C(x)                                       \
+	(((x) & BIT_MASK_8051_MBIST_DRF_FAIL_8821C)                            \
+	 << BIT_SHIFT_8051_MBIST_DRF_FAIL_8821C)
+#define BITS_8051_MBIST_DRF_FAIL_8821C                                         \
+	(BIT_MASK_8051_MBIST_DRF_FAIL_8821C                                    \
+	 << BIT_SHIFT_8051_MBIST_DRF_FAIL_8821C)
+#define BIT_CLEAR_8051_MBIST_DRF_FAIL_8821C(x)                                 \
+	((x) & (~BITS_8051_MBIST_DRF_FAIL_8821C))
+#define BIT_GET_8051_MBIST_DRF_FAIL_8821C(x)                                   \
+	(((x) >> BIT_SHIFT_8051_MBIST_DRF_FAIL_8821C) &                        \
+	 BIT_MASK_8051_MBIST_DRF_FAIL_8821C)
+#define BIT_SET_8051_MBIST_DRF_FAIL_8821C(x, v)                                \
+	(BIT_CLEAR_8051_MBIST_DRF_FAIL_8821C(x) |                              \
+	 BIT_8051_MBIST_DRF_FAIL_8821C(v))
+
+#define BIT_SHIFT_USB_MBIST_DRF_FAIL_8821C 24
+#define BIT_MASK_USB_MBIST_DRF_FAIL_8821C 0x3
+#define BIT_USB_MBIST_DRF_FAIL_8821C(x)                                        \
+	(((x) & BIT_MASK_USB_MBIST_DRF_FAIL_8821C)                             \
+	 << BIT_SHIFT_USB_MBIST_DRF_FAIL_8821C)
+#define BITS_USB_MBIST_DRF_FAIL_8821C                                          \
+	(BIT_MASK_USB_MBIST_DRF_FAIL_8821C                                     \
+	 << BIT_SHIFT_USB_MBIST_DRF_FAIL_8821C)
+#define BIT_CLEAR_USB_MBIST_DRF_FAIL_8821C(x)                                  \
+	((x) & (~BITS_USB_MBIST_DRF_FAIL_8821C))
+#define BIT_GET_USB_MBIST_DRF_FAIL_8821C(x)                                    \
+	(((x) >> BIT_SHIFT_USB_MBIST_DRF_FAIL_8821C) &                         \
+	 BIT_MASK_USB_MBIST_DRF_FAIL_8821C)
+#define BIT_SET_USB_MBIST_DRF_FAIL_8821C(x, v)                                 \
+	(BIT_CLEAR_USB_MBIST_DRF_FAIL_8821C(x) |                               \
+	 BIT_USB_MBIST_DRF_FAIL_8821C(v))
+
+#define BIT_SHIFT_PCIE_MBIST_DRF_FAIL_8821C 18
+#define BIT_MASK_PCIE_MBIST_DRF_FAIL_8821C 0x3f
+#define BIT_PCIE_MBIST_DRF_FAIL_8821C(x)                                       \
+	(((x) & BIT_MASK_PCIE_MBIST_DRF_FAIL_8821C)                            \
+	 << BIT_SHIFT_PCIE_MBIST_DRF_FAIL_8821C)
+#define BITS_PCIE_MBIST_DRF_FAIL_8821C                                         \
+	(BIT_MASK_PCIE_MBIST_DRF_FAIL_8821C                                    \
+	 << BIT_SHIFT_PCIE_MBIST_DRF_FAIL_8821C)
+#define BIT_CLEAR_PCIE_MBIST_DRF_FAIL_8821C(x)                                 \
+	((x) & (~BITS_PCIE_MBIST_DRF_FAIL_8821C))
+#define BIT_GET_PCIE_MBIST_DRF_FAIL_8821C(x)                                   \
+	(((x) >> BIT_SHIFT_PCIE_MBIST_DRF_FAIL_8821C) &                        \
+	 BIT_MASK_PCIE_MBIST_DRF_FAIL_8821C)
+#define BIT_SET_PCIE_MBIST_DRF_FAIL_8821C(x, v)                                \
+	(BIT_CLEAR_PCIE_MBIST_DRF_FAIL_8821C(x) |                              \
+	 BIT_PCIE_MBIST_DRF_FAIL_8821C(v))
+
+#define BIT_SHIFT_MAC_MBIST_DRF_FAIL_8821C 0
+#define BIT_MASK_MAC_MBIST_DRF_FAIL_8821C 0x3ffff
+#define BIT_MAC_MBIST_DRF_FAIL_8821C(x)                                        \
+	(((x) & BIT_MASK_MAC_MBIST_DRF_FAIL_8821C)                             \
+	 << BIT_SHIFT_MAC_MBIST_DRF_FAIL_8821C)
+#define BITS_MAC_MBIST_DRF_FAIL_8821C                                          \
+	(BIT_MASK_MAC_MBIST_DRF_FAIL_8821C                                     \
+	 << BIT_SHIFT_MAC_MBIST_DRF_FAIL_8821C)
+#define BIT_CLEAR_MAC_MBIST_DRF_FAIL_8821C(x)                                  \
+	((x) & (~BITS_MAC_MBIST_DRF_FAIL_8821C))
+#define BIT_GET_MAC_MBIST_DRF_FAIL_8821C(x)                                    \
+	(((x) >> BIT_SHIFT_MAC_MBIST_DRF_FAIL_8821C) &                         \
+	 BIT_MASK_MAC_MBIST_DRF_FAIL_8821C)
+#define BIT_SET_MAC_MBIST_DRF_FAIL_8821C(x, v)                                 \
+	(BIT_CLEAR_MAC_MBIST_DRF_FAIL_8821C(x) |                               \
+	 BIT_MAC_MBIST_DRF_FAIL_8821C(v))
+
+/* 2 REG_MBIST_START_PAUSE_8821C */
+
+#define BIT_SHIFT_8051_MBIST_START_PAUSE_V1_8821C 26
+#define BIT_MASK_8051_MBIST_START_PAUSE_V1_8821C 0x3f
+#define BIT_8051_MBIST_START_PAUSE_V1_8821C(x)                                 \
+	(((x) & BIT_MASK_8051_MBIST_START_PAUSE_V1_8821C)                      \
+	 << BIT_SHIFT_8051_MBIST_START_PAUSE_V1_8821C)
+#define BITS_8051_MBIST_START_PAUSE_V1_8821C                                   \
+	(BIT_MASK_8051_MBIST_START_PAUSE_V1_8821C                              \
+	 << BIT_SHIFT_8051_MBIST_START_PAUSE_V1_8821C)
+#define BIT_CLEAR_8051_MBIST_START_PAUSE_V1_8821C(x)                           \
+	((x) & (~BITS_8051_MBIST_START_PAUSE_V1_8821C))
+#define BIT_GET_8051_MBIST_START_PAUSE_V1_8821C(x)                             \
+	(((x) >> BIT_SHIFT_8051_MBIST_START_PAUSE_V1_8821C) &                  \
+	 BIT_MASK_8051_MBIST_START_PAUSE_V1_8821C)
+#define BIT_SET_8051_MBIST_START_PAUSE_V1_8821C(x, v)                          \
+	(BIT_CLEAR_8051_MBIST_START_PAUSE_V1_8821C(x) |                        \
+	 BIT_8051_MBIST_START_PAUSE_V1_8821C(v))
+
+#define BIT_SHIFT_USB_MBIST_START_PAUSE_V1_8821C 24
+#define BIT_MASK_USB_MBIST_START_PAUSE_V1_8821C 0x3
+#define BIT_USB_MBIST_START_PAUSE_V1_8821C(x)                                  \
+	(((x) & BIT_MASK_USB_MBIST_START_PAUSE_V1_8821C)                       \
+	 << BIT_SHIFT_USB_MBIST_START_PAUSE_V1_8821C)
+#define BITS_USB_MBIST_START_PAUSE_V1_8821C                                    \
+	(BIT_MASK_USB_MBIST_START_PAUSE_V1_8821C                               \
+	 << BIT_SHIFT_USB_MBIST_START_PAUSE_V1_8821C)
+#define BIT_CLEAR_USB_MBIST_START_PAUSE_V1_8821C(x)                            \
+	((x) & (~BITS_USB_MBIST_START_PAUSE_V1_8821C))
+#define BIT_GET_USB_MBIST_START_PAUSE_V1_8821C(x)                              \
+	(((x) >> BIT_SHIFT_USB_MBIST_START_PAUSE_V1_8821C) &                   \
+	 BIT_MASK_USB_MBIST_START_PAUSE_V1_8821C)
+#define BIT_SET_USB_MBIST_START_PAUSE_V1_8821C(x, v)                           \
+	(BIT_CLEAR_USB_MBIST_START_PAUSE_V1_8821C(x) |                         \
+	 BIT_USB_MBIST_START_PAUSE_V1_8821C(v))
+
+#define BIT_SHIFT_PCIE_MBIST_START_PAUSE_V1_8821C 18
+#define BIT_MASK_PCIE_MBIST_START_PAUSE_V1_8821C 0x3f
+#define BIT_PCIE_MBIST_START_PAUSE_V1_8821C(x)                                 \
+	(((x) & BIT_MASK_PCIE_MBIST_START_PAUSE_V1_8821C)                      \
+	 << BIT_SHIFT_PCIE_MBIST_START_PAUSE_V1_8821C)
+#define BITS_PCIE_MBIST_START_PAUSE_V1_8821C                                   \
+	(BIT_MASK_PCIE_MBIST_START_PAUSE_V1_8821C                              \
+	 << BIT_SHIFT_PCIE_MBIST_START_PAUSE_V1_8821C)
+#define BIT_CLEAR_PCIE_MBIST_START_PAUSE_V1_8821C(x)                           \
+	((x) & (~BITS_PCIE_MBIST_START_PAUSE_V1_8821C))
+#define BIT_GET_PCIE_MBIST_START_PAUSE_V1_8821C(x)                             \
+	(((x) >> BIT_SHIFT_PCIE_MBIST_START_PAUSE_V1_8821C) &                  \
+	 BIT_MASK_PCIE_MBIST_START_PAUSE_V1_8821C)
+#define BIT_SET_PCIE_MBIST_START_PAUSE_V1_8821C(x, v)                          \
+	(BIT_CLEAR_PCIE_MBIST_START_PAUSE_V1_8821C(x) |                        \
+	 BIT_PCIE_MBIST_START_PAUSE_V1_8821C(v))
+
+#define BIT_SHIFT_MAC_MBIST_START_PAUSE_V1_8821C 0
+#define BIT_MASK_MAC_MBIST_START_PAUSE_V1_8821C 0x3ffff
+#define BIT_MAC_MBIST_START_PAUSE_V1_8821C(x)                                  \
+	(((x) & BIT_MASK_MAC_MBIST_START_PAUSE_V1_8821C)                       \
+	 << BIT_SHIFT_MAC_MBIST_START_PAUSE_V1_8821C)
+#define BITS_MAC_MBIST_START_PAUSE_V1_8821C                                    \
+	(BIT_MASK_MAC_MBIST_START_PAUSE_V1_8821C                               \
+	 << BIT_SHIFT_MAC_MBIST_START_PAUSE_V1_8821C)
+#define BIT_CLEAR_MAC_MBIST_START_PAUSE_V1_8821C(x)                            \
+	((x) & (~BITS_MAC_MBIST_START_PAUSE_V1_8821C))
+#define BIT_GET_MAC_MBIST_START_PAUSE_V1_8821C(x)                              \
+	(((x) >> BIT_SHIFT_MAC_MBIST_START_PAUSE_V1_8821C) &                   \
+	 BIT_MASK_MAC_MBIST_START_PAUSE_V1_8821C)
+#define BIT_SET_MAC_MBIST_START_PAUSE_V1_8821C(x, v)                           \
+	(BIT_CLEAR_MAC_MBIST_START_PAUSE_V1_8821C(x) |                         \
+	 BIT_MAC_MBIST_START_PAUSE_V1_8821C(v))
+
+/* 2 REG_MBIST_DONE_8821C */
+
+#define BIT_SHIFT_8051_MBIST_DONE_V1_8821C 26
+#define BIT_MASK_8051_MBIST_DONE_V1_8821C 0x3f
+#define BIT_8051_MBIST_DONE_V1_8821C(x)                                        \
+	(((x) & BIT_MASK_8051_MBIST_DONE_V1_8821C)                             \
+	 << BIT_SHIFT_8051_MBIST_DONE_V1_8821C)
+#define BITS_8051_MBIST_DONE_V1_8821C                                          \
+	(BIT_MASK_8051_MBIST_DONE_V1_8821C                                     \
+	 << BIT_SHIFT_8051_MBIST_DONE_V1_8821C)
+#define BIT_CLEAR_8051_MBIST_DONE_V1_8821C(x)                                  \
+	((x) & (~BITS_8051_MBIST_DONE_V1_8821C))
+#define BIT_GET_8051_MBIST_DONE_V1_8821C(x)                                    \
+	(((x) >> BIT_SHIFT_8051_MBIST_DONE_V1_8821C) &                         \
+	 BIT_MASK_8051_MBIST_DONE_V1_8821C)
+#define BIT_SET_8051_MBIST_DONE_V1_8821C(x, v)                                 \
+	(BIT_CLEAR_8051_MBIST_DONE_V1_8821C(x) |                               \
+	 BIT_8051_MBIST_DONE_V1_8821C(v))
+
+#define BIT_SHIFT_USB_MBIST_DONE_V1_8821C 24
+#define BIT_MASK_USB_MBIST_DONE_V1_8821C 0x3
+#define BIT_USB_MBIST_DONE_V1_8821C(x)                                         \
+	(((x) & BIT_MASK_USB_MBIST_DONE_V1_8821C)                              \
+	 << BIT_SHIFT_USB_MBIST_DONE_V1_8821C)
+#define BITS_USB_MBIST_DONE_V1_8821C                                           \
+	(BIT_MASK_USB_MBIST_DONE_V1_8821C << BIT_SHIFT_USB_MBIST_DONE_V1_8821C)
+#define BIT_CLEAR_USB_MBIST_DONE_V1_8821C(x)                                   \
+	((x) & (~BITS_USB_MBIST_DONE_V1_8821C))
+#define BIT_GET_USB_MBIST_DONE_V1_8821C(x)                                     \
+	(((x) >> BIT_SHIFT_USB_MBIST_DONE_V1_8821C) &                          \
+	 BIT_MASK_USB_MBIST_DONE_V1_8821C)
+#define BIT_SET_USB_MBIST_DONE_V1_8821C(x, v)                                  \
+	(BIT_CLEAR_USB_MBIST_DONE_V1_8821C(x) | BIT_USB_MBIST_DONE_V1_8821C(v))
+
+#define BIT_SHIFT_PCIE_MBIST_DONE_V1_8821C 18
+#define BIT_MASK_PCIE_MBIST_DONE_V1_8821C 0x3f
+#define BIT_PCIE_MBIST_DONE_V1_8821C(x)                                        \
+	(((x) & BIT_MASK_PCIE_MBIST_DONE_V1_8821C)                             \
+	 << BIT_SHIFT_PCIE_MBIST_DONE_V1_8821C)
+#define BITS_PCIE_MBIST_DONE_V1_8821C                                          \
+	(BIT_MASK_PCIE_MBIST_DONE_V1_8821C                                     \
+	 << BIT_SHIFT_PCIE_MBIST_DONE_V1_8821C)
+#define BIT_CLEAR_PCIE_MBIST_DONE_V1_8821C(x)                                  \
+	((x) & (~BITS_PCIE_MBIST_DONE_V1_8821C))
+#define BIT_GET_PCIE_MBIST_DONE_V1_8821C(x)                                    \
+	(((x) >> BIT_SHIFT_PCIE_MBIST_DONE_V1_8821C) &                         \
+	 BIT_MASK_PCIE_MBIST_DONE_V1_8821C)
+#define BIT_SET_PCIE_MBIST_DONE_V1_8821C(x, v)                                 \
+	(BIT_CLEAR_PCIE_MBIST_DONE_V1_8821C(x) |                               \
+	 BIT_PCIE_MBIST_DONE_V1_8821C(v))
+
+#define BIT_SHIFT_MAC_MBIST_DONE_V1_8821C 0
+#define BIT_MASK_MAC_MBIST_DONE_V1_8821C 0x3ffff
+#define BIT_MAC_MBIST_DONE_V1_8821C(x)                                         \
+	(((x) & BIT_MASK_MAC_MBIST_DONE_V1_8821C)                              \
+	 << BIT_SHIFT_MAC_MBIST_DONE_V1_8821C)
+#define BITS_MAC_MBIST_DONE_V1_8821C                                           \
+	(BIT_MASK_MAC_MBIST_DONE_V1_8821C << BIT_SHIFT_MAC_MBIST_DONE_V1_8821C)
+#define BIT_CLEAR_MAC_MBIST_DONE_V1_8821C(x)                                   \
+	((x) & (~BITS_MAC_MBIST_DONE_V1_8821C))
+#define BIT_GET_MAC_MBIST_DONE_V1_8821C(x)                                     \
+	(((x) >> BIT_SHIFT_MAC_MBIST_DONE_V1_8821C) &                          \
+	 BIT_MASK_MAC_MBIST_DONE_V1_8821C)
+#define BIT_SET_MAC_MBIST_DONE_V1_8821C(x, v)                                  \
+	(BIT_CLEAR_MAC_MBIST_DONE_V1_8821C(x) | BIT_MAC_MBIST_DONE_V1_8821C(v))
+
+/* 2 REG_MBIST_READ_BIST_RPT_8821C */
+
+#define BIT_SHIFT_MBIST_READ_BIST_RPT_8821C 0
+#define BIT_MASK_MBIST_READ_BIST_RPT_8821C 0xffffffffL
+#define BIT_MBIST_READ_BIST_RPT_8821C(x)                                       \
+	(((x) & BIT_MASK_MBIST_READ_BIST_RPT_8821C)                            \
+	 << BIT_SHIFT_MBIST_READ_BIST_RPT_8821C)
+#define BITS_MBIST_READ_BIST_RPT_8821C                                         \
+	(BIT_MASK_MBIST_READ_BIST_RPT_8821C                                    \
+	 << BIT_SHIFT_MBIST_READ_BIST_RPT_8821C)
+#define BIT_CLEAR_MBIST_READ_BIST_RPT_8821C(x)                                 \
+	((x) & (~BITS_MBIST_READ_BIST_RPT_8821C))
+#define BIT_GET_MBIST_READ_BIST_RPT_8821C(x)                                   \
+	(((x) >> BIT_SHIFT_MBIST_READ_BIST_RPT_8821C) &                        \
+	 BIT_MASK_MBIST_READ_BIST_RPT_8821C)
+#define BIT_SET_MBIST_READ_BIST_RPT_8821C(x, v)                                \
+	(BIT_CLEAR_MBIST_READ_BIST_RPT_8821C(x) |                              \
+	 BIT_MBIST_READ_BIST_RPT_8821C(v))
+
+/* 2 REG_AES_DECRPT_DATA_8821C */
+
+#define BIT_SHIFT_IPS_CFG_ADDR_8821C 0
+#define BIT_MASK_IPS_CFG_ADDR_8821C 0xff
+#define BIT_IPS_CFG_ADDR_8821C(x)                                              \
+	(((x) & BIT_MASK_IPS_CFG_ADDR_8821C) << BIT_SHIFT_IPS_CFG_ADDR_8821C)
+#define BITS_IPS_CFG_ADDR_8821C                                                \
+	(BIT_MASK_IPS_CFG_ADDR_8821C << BIT_SHIFT_IPS_CFG_ADDR_8821C)
+#define BIT_CLEAR_IPS_CFG_ADDR_8821C(x) ((x) & (~BITS_IPS_CFG_ADDR_8821C))
+#define BIT_GET_IPS_CFG_ADDR_8821C(x)                                          \
+	(((x) >> BIT_SHIFT_IPS_CFG_ADDR_8821C) & BIT_MASK_IPS_CFG_ADDR_8821C)
+#define BIT_SET_IPS_CFG_ADDR_8821C(x, v)                                       \
+	(BIT_CLEAR_IPS_CFG_ADDR_8821C(x) | BIT_IPS_CFG_ADDR_8821C(v))
+
+/* 2 REG_AES_DECRPT_CFG_8821C */
+
+#define BIT_SHIFT_IPS_CFG_DATA_8821C 0
+#define BIT_MASK_IPS_CFG_DATA_8821C 0xffffffffL
+#define BIT_IPS_CFG_DATA_8821C(x)                                              \
+	(((x) & BIT_MASK_IPS_CFG_DATA_8821C) << BIT_SHIFT_IPS_CFG_DATA_8821C)
+#define BITS_IPS_CFG_DATA_8821C                                                \
+	(BIT_MASK_IPS_CFG_DATA_8821C << BIT_SHIFT_IPS_CFG_DATA_8821C)
+#define BIT_CLEAR_IPS_CFG_DATA_8821C(x) ((x) & (~BITS_IPS_CFG_DATA_8821C))
+#define BIT_GET_IPS_CFG_DATA_8821C(x)                                          \
+	(((x) >> BIT_SHIFT_IPS_CFG_DATA_8821C) & BIT_MASK_IPS_CFG_DATA_8821C)
+#define BIT_SET_IPS_CFG_DATA_8821C(x, v)                                       \
+	(BIT_CLEAR_IPS_CFG_DATA_8821C(x) | BIT_IPS_CFG_DATA_8821C(v))
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_TMETER_8821C */
+#define BIT_TEMP_VALID_8821C BIT(31)
+
+#define BIT_SHIFT_TEMP_VALUE_8821C 24
+#define BIT_MASK_TEMP_VALUE_8821C 0x3f
+#define BIT_TEMP_VALUE_8821C(x)                                                \
+	(((x) & BIT_MASK_TEMP_VALUE_8821C) << BIT_SHIFT_TEMP_VALUE_8821C)
+#define BITS_TEMP_VALUE_8821C                                                  \
+	(BIT_MASK_TEMP_VALUE_8821C << BIT_SHIFT_TEMP_VALUE_8821C)
+#define BIT_CLEAR_TEMP_VALUE_8821C(x) ((x) & (~BITS_TEMP_VALUE_8821C))
+#define BIT_GET_TEMP_VALUE_8821C(x)                                            \
+	(((x) >> BIT_SHIFT_TEMP_VALUE_8821C) & BIT_MASK_TEMP_VALUE_8821C)
+#define BIT_SET_TEMP_VALUE_8821C(x, v)                                         \
+	(BIT_CLEAR_TEMP_VALUE_8821C(x) | BIT_TEMP_VALUE_8821C(v))
+
+#define BIT_SHIFT_REG_TMETER_TIMER_8821C 8
+#define BIT_MASK_REG_TMETER_TIMER_8821C 0xfff
+#define BIT_REG_TMETER_TIMER_8821C(x)                                          \
+	(((x) & BIT_MASK_REG_TMETER_TIMER_8821C)                               \
+	 << BIT_SHIFT_REG_TMETER_TIMER_8821C)
+#define BITS_REG_TMETER_TIMER_8821C                                            \
+	(BIT_MASK_REG_TMETER_TIMER_8821C << BIT_SHIFT_REG_TMETER_TIMER_8821C)
+#define BIT_CLEAR_REG_TMETER_TIMER_8821C(x)                                    \
+	((x) & (~BITS_REG_TMETER_TIMER_8821C))
+#define BIT_GET_REG_TMETER_TIMER_8821C(x)                                      \
+	(((x) >> BIT_SHIFT_REG_TMETER_TIMER_8821C) &                           \
+	 BIT_MASK_REG_TMETER_TIMER_8821C)
+#define BIT_SET_REG_TMETER_TIMER_8821C(x, v)                                   \
+	(BIT_CLEAR_REG_TMETER_TIMER_8821C(x) | BIT_REG_TMETER_TIMER_8821C(v))
+
+#define BIT_SHIFT_REG_TEMP_DELTA_8821C 2
+#define BIT_MASK_REG_TEMP_DELTA_8821C 0x3f
+#define BIT_REG_TEMP_DELTA_8821C(x)                                            \
+	(((x) & BIT_MASK_REG_TEMP_DELTA_8821C)                                 \
+	 << BIT_SHIFT_REG_TEMP_DELTA_8821C)
+#define BITS_REG_TEMP_DELTA_8821C                                              \
+	(BIT_MASK_REG_TEMP_DELTA_8821C << BIT_SHIFT_REG_TEMP_DELTA_8821C)
+#define BIT_CLEAR_REG_TEMP_DELTA_8821C(x) ((x) & (~BITS_REG_TEMP_DELTA_8821C))
+#define BIT_GET_REG_TEMP_DELTA_8821C(x)                                        \
+	(((x) >> BIT_SHIFT_REG_TEMP_DELTA_8821C) &                             \
+	 BIT_MASK_REG_TEMP_DELTA_8821C)
+#define BIT_SET_REG_TEMP_DELTA_8821C(x, v)                                     \
+	(BIT_CLEAR_REG_TEMP_DELTA_8821C(x) | BIT_REG_TEMP_DELTA_8821C(v))
+
+#define BIT_REG_TMETER_EN_8821C BIT(0)
+
+/* 2 REG_OSC_32K_CTRL_8821C */
+
+#define BIT_SHIFT_OSC_32K_CLKGEN_0_8821C 16
+#define BIT_MASK_OSC_32K_CLKGEN_0_8821C 0xffff
+#define BIT_OSC_32K_CLKGEN_0_8821C(x)                                          \
+	(((x) & BIT_MASK_OSC_32K_CLKGEN_0_8821C)                               \
+	 << BIT_SHIFT_OSC_32K_CLKGEN_0_8821C)
+#define BITS_OSC_32K_CLKGEN_0_8821C                                            \
+	(BIT_MASK_OSC_32K_CLKGEN_0_8821C << BIT_SHIFT_OSC_32K_CLKGEN_0_8821C)
+#define BIT_CLEAR_OSC_32K_CLKGEN_0_8821C(x)                                    \
+	((x) & (~BITS_OSC_32K_CLKGEN_0_8821C))
+#define BIT_GET_OSC_32K_CLKGEN_0_8821C(x)                                      \
+	(((x) >> BIT_SHIFT_OSC_32K_CLKGEN_0_8821C) &                           \
+	 BIT_MASK_OSC_32K_CLKGEN_0_8821C)
+#define BIT_SET_OSC_32K_CLKGEN_0_8821C(x, v)                                   \
+	(BIT_CLEAR_OSC_32K_CLKGEN_0_8821C(x) | BIT_OSC_32K_CLKGEN_0_8821C(v))
+
+#define BIT_SHIFT_OSC_32K_RES_COMP_8821C 4
+#define BIT_MASK_OSC_32K_RES_COMP_8821C 0x3
+#define BIT_OSC_32K_RES_COMP_8821C(x)                                          \
+	(((x) & BIT_MASK_OSC_32K_RES_COMP_8821C)                               \
+	 << BIT_SHIFT_OSC_32K_RES_COMP_8821C)
+#define BITS_OSC_32K_RES_COMP_8821C                                            \
+	(BIT_MASK_OSC_32K_RES_COMP_8821C << BIT_SHIFT_OSC_32K_RES_COMP_8821C)
+#define BIT_CLEAR_OSC_32K_RES_COMP_8821C(x)                                    \
+	((x) & (~BITS_OSC_32K_RES_COMP_8821C))
+#define BIT_GET_OSC_32K_RES_COMP_8821C(x)                                      \
+	(((x) >> BIT_SHIFT_OSC_32K_RES_COMP_8821C) &                           \
+	 BIT_MASK_OSC_32K_RES_COMP_8821C)
+#define BIT_SET_OSC_32K_RES_COMP_8821C(x, v)                                   \
+	(BIT_CLEAR_OSC_32K_RES_COMP_8821C(x) | BIT_OSC_32K_RES_COMP_8821C(v))
+
+#define BIT_OSC_32K_OUT_SEL_8821C BIT(3)
+#define BIT_ISO_WL_2_OSC_32K_8821C BIT(1)
+#define BIT_POW_CKGEN_8821C BIT(0)
+
+/* 2 REG_32K_CAL_REG1_8821C */
+#define BIT_CAL_32K_REG_WR_8821C BIT(31)
+#define BIT_CAL_32K_DBG_SEL_8821C BIT(22)
+
+#define BIT_SHIFT_CAL_32K_REG_ADDR_8821C 16
+#define BIT_MASK_CAL_32K_REG_ADDR_8821C 0x3f
+#define BIT_CAL_32K_REG_ADDR_8821C(x)                                          \
+	(((x) & BIT_MASK_CAL_32K_REG_ADDR_8821C)                               \
+	 << BIT_SHIFT_CAL_32K_REG_ADDR_8821C)
+#define BITS_CAL_32K_REG_ADDR_8821C                                            \
+	(BIT_MASK_CAL_32K_REG_ADDR_8821C << BIT_SHIFT_CAL_32K_REG_ADDR_8821C)
+#define BIT_CLEAR_CAL_32K_REG_ADDR_8821C(x)                                    \
+	((x) & (~BITS_CAL_32K_REG_ADDR_8821C))
+#define BIT_GET_CAL_32K_REG_ADDR_8821C(x)                                      \
+	(((x) >> BIT_SHIFT_CAL_32K_REG_ADDR_8821C) &                           \
+	 BIT_MASK_CAL_32K_REG_ADDR_8821C)
+#define BIT_SET_CAL_32K_REG_ADDR_8821C(x, v)                                   \
+	(BIT_CLEAR_CAL_32K_REG_ADDR_8821C(x) | BIT_CAL_32K_REG_ADDR_8821C(v))
+
+#define BIT_SHIFT_CAL_32K_REG_DATA_8821C 0
+#define BIT_MASK_CAL_32K_REG_DATA_8821C 0xffff
+#define BIT_CAL_32K_REG_DATA_8821C(x)                                          \
+	(((x) & BIT_MASK_CAL_32K_REG_DATA_8821C)                               \
+	 << BIT_SHIFT_CAL_32K_REG_DATA_8821C)
+#define BITS_CAL_32K_REG_DATA_8821C                                            \
+	(BIT_MASK_CAL_32K_REG_DATA_8821C << BIT_SHIFT_CAL_32K_REG_DATA_8821C)
+#define BIT_CLEAR_CAL_32K_REG_DATA_8821C(x)                                    \
+	((x) & (~BITS_CAL_32K_REG_DATA_8821C))
+#define BIT_GET_CAL_32K_REG_DATA_8821C(x)                                      \
+	(((x) >> BIT_SHIFT_CAL_32K_REG_DATA_8821C) &                           \
+	 BIT_MASK_CAL_32K_REG_DATA_8821C)
+#define BIT_SET_CAL_32K_REG_DATA_8821C(x, v)                                   \
+	(BIT_CLEAR_CAL_32K_REG_DATA_8821C(x) | BIT_CAL_32K_REG_DATA_8821C(v))
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_C2HEVT_8821C */
+
+#define BIT_SHIFT_C2HEVT_MSG_V1_8821C 0
+#define BIT_MASK_C2HEVT_MSG_V1_8821C 0xffffffffL
+#define BIT_C2HEVT_MSG_V1_8821C(x)                                             \
+	(((x) & BIT_MASK_C2HEVT_MSG_V1_8821C) << BIT_SHIFT_C2HEVT_MSG_V1_8821C)
+#define BITS_C2HEVT_MSG_V1_8821C                                               \
+	(BIT_MASK_C2HEVT_MSG_V1_8821C << BIT_SHIFT_C2HEVT_MSG_V1_8821C)
+#define BIT_CLEAR_C2HEVT_MSG_V1_8821C(x) ((x) & (~BITS_C2HEVT_MSG_V1_8821C))
+#define BIT_GET_C2HEVT_MSG_V1_8821C(x)                                         \
+	(((x) >> BIT_SHIFT_C2HEVT_MSG_V1_8821C) & BIT_MASK_C2HEVT_MSG_V1_8821C)
+#define BIT_SET_C2HEVT_MSG_V1_8821C(x, v)                                      \
+	(BIT_CLEAR_C2HEVT_MSG_V1_8821C(x) | BIT_C2HEVT_MSG_V1_8821C(v))
+
+/* 2 REG_C2HEVT_1_8821C */
+
+#define BIT_SHIFT_C2HEVT_MSG_1_8821C 0
+#define BIT_MASK_C2HEVT_MSG_1_8821C 0xffffffffL
+#define BIT_C2HEVT_MSG_1_8821C(x)                                              \
+	(((x) & BIT_MASK_C2HEVT_MSG_1_8821C) << BIT_SHIFT_C2HEVT_MSG_1_8821C)
+#define BITS_C2HEVT_MSG_1_8821C                                                \
+	(BIT_MASK_C2HEVT_MSG_1_8821C << BIT_SHIFT_C2HEVT_MSG_1_8821C)
+#define BIT_CLEAR_C2HEVT_MSG_1_8821C(x) ((x) & (~BITS_C2HEVT_MSG_1_8821C))
+#define BIT_GET_C2HEVT_MSG_1_8821C(x)                                          \
+	(((x) >> BIT_SHIFT_C2HEVT_MSG_1_8821C) & BIT_MASK_C2HEVT_MSG_1_8821C)
+#define BIT_SET_C2HEVT_MSG_1_8821C(x, v)                                       \
+	(BIT_CLEAR_C2HEVT_MSG_1_8821C(x) | BIT_C2HEVT_MSG_1_8821C(v))
+
+/* 2 REG_C2HEVT_2_8821C */
+
+#define BIT_SHIFT_C2HEVT_MSG_2_8821C 0
+#define BIT_MASK_C2HEVT_MSG_2_8821C 0xffffffffL
+#define BIT_C2HEVT_MSG_2_8821C(x)                                              \
+	(((x) & BIT_MASK_C2HEVT_MSG_2_8821C) << BIT_SHIFT_C2HEVT_MSG_2_8821C)
+#define BITS_C2HEVT_MSG_2_8821C                                                \
+	(BIT_MASK_C2HEVT_MSG_2_8821C << BIT_SHIFT_C2HEVT_MSG_2_8821C)
+#define BIT_CLEAR_C2HEVT_MSG_2_8821C(x) ((x) & (~BITS_C2HEVT_MSG_2_8821C))
+#define BIT_GET_C2HEVT_MSG_2_8821C(x)                                          \
+	(((x) >> BIT_SHIFT_C2HEVT_MSG_2_8821C) & BIT_MASK_C2HEVT_MSG_2_8821C)
+#define BIT_SET_C2HEVT_MSG_2_8821C(x, v)                                       \
+	(BIT_CLEAR_C2HEVT_MSG_2_8821C(x) | BIT_C2HEVT_MSG_2_8821C(v))
+
+/* 2 REG_C2HEVT_3_8821C */
+
+#define BIT_SHIFT_C2HEVT_MSG_3_8821C 0
+#define BIT_MASK_C2HEVT_MSG_3_8821C 0xffffffffL
+#define BIT_C2HEVT_MSG_3_8821C(x)                                              \
+	(((x) & BIT_MASK_C2HEVT_MSG_3_8821C) << BIT_SHIFT_C2HEVT_MSG_3_8821C)
+#define BITS_C2HEVT_MSG_3_8821C                                                \
+	(BIT_MASK_C2HEVT_MSG_3_8821C << BIT_SHIFT_C2HEVT_MSG_3_8821C)
+#define BIT_CLEAR_C2HEVT_MSG_3_8821C(x) ((x) & (~BITS_C2HEVT_MSG_3_8821C))
+#define BIT_GET_C2HEVT_MSG_3_8821C(x)                                          \
+	(((x) >> BIT_SHIFT_C2HEVT_MSG_3_8821C) & BIT_MASK_C2HEVT_MSG_3_8821C)
+#define BIT_SET_C2HEVT_MSG_3_8821C(x, v)                                       \
+	(BIT_CLEAR_C2HEVT_MSG_3_8821C(x) | BIT_C2HEVT_MSG_3_8821C(v))
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_SW_DEFINED_PAGE1_8821C */
+
+#define BIT_SHIFT_SW_DEFINED_PAGE1_V1_8821C 0
+#define BIT_MASK_SW_DEFINED_PAGE1_V1_8821C 0xffffffffL
+#define BIT_SW_DEFINED_PAGE1_V1_8821C(x)                                       \
+	(((x) & BIT_MASK_SW_DEFINED_PAGE1_V1_8821C)                            \
+	 << BIT_SHIFT_SW_DEFINED_PAGE1_V1_8821C)
+#define BITS_SW_DEFINED_PAGE1_V1_8821C                                         \
+	(BIT_MASK_SW_DEFINED_PAGE1_V1_8821C                                    \
+	 << BIT_SHIFT_SW_DEFINED_PAGE1_V1_8821C)
+#define BIT_CLEAR_SW_DEFINED_PAGE1_V1_8821C(x)                                 \
+	((x) & (~BITS_SW_DEFINED_PAGE1_V1_8821C))
+#define BIT_GET_SW_DEFINED_PAGE1_V1_8821C(x)                                   \
+	(((x) >> BIT_SHIFT_SW_DEFINED_PAGE1_V1_8821C) &                        \
+	 BIT_MASK_SW_DEFINED_PAGE1_V1_8821C)
+#define BIT_SET_SW_DEFINED_PAGE1_V1_8821C(x, v)                                \
+	(BIT_CLEAR_SW_DEFINED_PAGE1_V1_8821C(x) |                              \
+	 BIT_SW_DEFINED_PAGE1_V1_8821C(v))
+
+/* 2 REG_SW_DEFINED_PAGE2_8821C */
+
+#define BIT_SHIFT_SW_DEFINED_PAGE2_8821C 0
+#define BIT_MASK_SW_DEFINED_PAGE2_8821C 0xffffffffL
+#define BIT_SW_DEFINED_PAGE2_8821C(x)                                          \
+	(((x) & BIT_MASK_SW_DEFINED_PAGE2_8821C)                               \
+	 << BIT_SHIFT_SW_DEFINED_PAGE2_8821C)
+#define BITS_SW_DEFINED_PAGE2_8821C                                            \
+	(BIT_MASK_SW_DEFINED_PAGE2_8821C << BIT_SHIFT_SW_DEFINED_PAGE2_8821C)
+#define BIT_CLEAR_SW_DEFINED_PAGE2_8821C(x)                                    \
+	((x) & (~BITS_SW_DEFINED_PAGE2_8821C))
+#define BIT_GET_SW_DEFINED_PAGE2_8821C(x)                                      \
+	(((x) >> BIT_SHIFT_SW_DEFINED_PAGE2_8821C) &                           \
+	 BIT_MASK_SW_DEFINED_PAGE2_8821C)
+#define BIT_SET_SW_DEFINED_PAGE2_8821C(x, v)                                   \
+	(BIT_CLEAR_SW_DEFINED_PAGE2_8821C(x) | BIT_SW_DEFINED_PAGE2_8821C(v))
+
+/* 2 REG_MCUTST_I_8821C */
+
+#define BIT_SHIFT_MCUDMSG_I_8821C 0
+#define BIT_MASK_MCUDMSG_I_8821C 0xffffffffL
+#define BIT_MCUDMSG_I_8821C(x)                                                 \
+	(((x) & BIT_MASK_MCUDMSG_I_8821C) << BIT_SHIFT_MCUDMSG_I_8821C)
+#define BITS_MCUDMSG_I_8821C                                                   \
+	(BIT_MASK_MCUDMSG_I_8821C << BIT_SHIFT_MCUDMSG_I_8821C)
+#define BIT_CLEAR_MCUDMSG_I_8821C(x) ((x) & (~BITS_MCUDMSG_I_8821C))
+#define BIT_GET_MCUDMSG_I_8821C(x)                                             \
+	(((x) >> BIT_SHIFT_MCUDMSG_I_8821C) & BIT_MASK_MCUDMSG_I_8821C)
+#define BIT_SET_MCUDMSG_I_8821C(x, v)                                          \
+	(BIT_CLEAR_MCUDMSG_I_8821C(x) | BIT_MCUDMSG_I_8821C(v))
+
+/* 2 REG_MCUTST_II_8821C */
+
+#define BIT_SHIFT_MCUDMSG_II_8821C 0
+#define BIT_MASK_MCUDMSG_II_8821C 0xffffffffL
+#define BIT_MCUDMSG_II_8821C(x)                                                \
+	(((x) & BIT_MASK_MCUDMSG_II_8821C) << BIT_SHIFT_MCUDMSG_II_8821C)
+#define BITS_MCUDMSG_II_8821C                                                  \
+	(BIT_MASK_MCUDMSG_II_8821C << BIT_SHIFT_MCUDMSG_II_8821C)
+#define BIT_CLEAR_MCUDMSG_II_8821C(x) ((x) & (~BITS_MCUDMSG_II_8821C))
+#define BIT_GET_MCUDMSG_II_8821C(x)                                            \
+	(((x) >> BIT_SHIFT_MCUDMSG_II_8821C) & BIT_MASK_MCUDMSG_II_8821C)
+#define BIT_SET_MCUDMSG_II_8821C(x, v)                                         \
+	(BIT_CLEAR_MCUDMSG_II_8821C(x) | BIT_MCUDMSG_II_8821C(v))
+
+/* 2 REG_FMETHR_8821C */
+#define BIT_FMSG_INT_8821C BIT(31)
+
+#define BIT_SHIFT_FW_MSG_8821C 0
+#define BIT_MASK_FW_MSG_8821C 0xffffffffL
+#define BIT_FW_MSG_8821C(x)                                                    \
+	(((x) & BIT_MASK_FW_MSG_8821C) << BIT_SHIFT_FW_MSG_8821C)
+#define BITS_FW_MSG_8821C (BIT_MASK_FW_MSG_8821C << BIT_SHIFT_FW_MSG_8821C)
+#define BIT_CLEAR_FW_MSG_8821C(x) ((x) & (~BITS_FW_MSG_8821C))
+#define BIT_GET_FW_MSG_8821C(x)                                                \
+	(((x) >> BIT_SHIFT_FW_MSG_8821C) & BIT_MASK_FW_MSG_8821C)
+#define BIT_SET_FW_MSG_8821C(x, v)                                             \
+	(BIT_CLEAR_FW_MSG_8821C(x) | BIT_FW_MSG_8821C(v))
+
+/* 2 REG_HMETFR_8821C */
+
+#define BIT_SHIFT_HRCV_MSG_8821C 24
+#define BIT_MASK_HRCV_MSG_8821C 0xff
+#define BIT_HRCV_MSG_8821C(x)                                                  \
+	(((x) & BIT_MASK_HRCV_MSG_8821C) << BIT_SHIFT_HRCV_MSG_8821C)
+#define BITS_HRCV_MSG_8821C                                                    \
+	(BIT_MASK_HRCV_MSG_8821C << BIT_SHIFT_HRCV_MSG_8821C)
+#define BIT_CLEAR_HRCV_MSG_8821C(x) ((x) & (~BITS_HRCV_MSG_8821C))
+#define BIT_GET_HRCV_MSG_8821C(x)                                              \
+	(((x) >> BIT_SHIFT_HRCV_MSG_8821C) & BIT_MASK_HRCV_MSG_8821C)
+#define BIT_SET_HRCV_MSG_8821C(x, v)                                           \
+	(BIT_CLEAR_HRCV_MSG_8821C(x) | BIT_HRCV_MSG_8821C(v))
+
+#define BIT_INT_BOX3_8821C BIT(3)
+#define BIT_INT_BOX2_8821C BIT(2)
+#define BIT_INT_BOX1_8821C BIT(1)
+#define BIT_INT_BOX0_8821C BIT(0)
+
+/* 2 REG_HMEBOX0_8821C */
+
+#define BIT_SHIFT_HOST_MSG_0_8821C 0
+#define BIT_MASK_HOST_MSG_0_8821C 0xffffffffL
+#define BIT_HOST_MSG_0_8821C(x)                                                \
+	(((x) & BIT_MASK_HOST_MSG_0_8821C) << BIT_SHIFT_HOST_MSG_0_8821C)
+#define BITS_HOST_MSG_0_8821C                                                  \
+	(BIT_MASK_HOST_MSG_0_8821C << BIT_SHIFT_HOST_MSG_0_8821C)
+#define BIT_CLEAR_HOST_MSG_0_8821C(x) ((x) & (~BITS_HOST_MSG_0_8821C))
+#define BIT_GET_HOST_MSG_0_8821C(x)                                            \
+	(((x) >> BIT_SHIFT_HOST_MSG_0_8821C) & BIT_MASK_HOST_MSG_0_8821C)
+#define BIT_SET_HOST_MSG_0_8821C(x, v)                                         \
+	(BIT_CLEAR_HOST_MSG_0_8821C(x) | BIT_HOST_MSG_0_8821C(v))
+
+/* 2 REG_HMEBOX1_8821C */
+
+#define BIT_SHIFT_HOST_MSG_1_8821C 0
+#define BIT_MASK_HOST_MSG_1_8821C 0xffffffffL
+#define BIT_HOST_MSG_1_8821C(x)                                                \
+	(((x) & BIT_MASK_HOST_MSG_1_8821C) << BIT_SHIFT_HOST_MSG_1_8821C)
+#define BITS_HOST_MSG_1_8821C                                                  \
+	(BIT_MASK_HOST_MSG_1_8821C << BIT_SHIFT_HOST_MSG_1_8821C)
+#define BIT_CLEAR_HOST_MSG_1_8821C(x) ((x) & (~BITS_HOST_MSG_1_8821C))
+#define BIT_GET_HOST_MSG_1_8821C(x)                                            \
+	(((x) >> BIT_SHIFT_HOST_MSG_1_8821C) & BIT_MASK_HOST_MSG_1_8821C)
+#define BIT_SET_HOST_MSG_1_8821C(x, v)                                         \
+	(BIT_CLEAR_HOST_MSG_1_8821C(x) | BIT_HOST_MSG_1_8821C(v))
+
+/* 2 REG_HMEBOX2_8821C */
+
+#define BIT_SHIFT_HOST_MSG_2_8821C 0
+#define BIT_MASK_HOST_MSG_2_8821C 0xffffffffL
+#define BIT_HOST_MSG_2_8821C(x)                                                \
+	(((x) & BIT_MASK_HOST_MSG_2_8821C) << BIT_SHIFT_HOST_MSG_2_8821C)
+#define BITS_HOST_MSG_2_8821C                                                  \
+	(BIT_MASK_HOST_MSG_2_8821C << BIT_SHIFT_HOST_MSG_2_8821C)
+#define BIT_CLEAR_HOST_MSG_2_8821C(x) ((x) & (~BITS_HOST_MSG_2_8821C))
+#define BIT_GET_HOST_MSG_2_8821C(x)                                            \
+	(((x) >> BIT_SHIFT_HOST_MSG_2_8821C) & BIT_MASK_HOST_MSG_2_8821C)
+#define BIT_SET_HOST_MSG_2_8821C(x, v)                                         \
+	(BIT_CLEAR_HOST_MSG_2_8821C(x) | BIT_HOST_MSG_2_8821C(v))
+
+/* 2 REG_HMEBOX3_8821C */
+
+#define BIT_SHIFT_HOST_MSG_3_8821C 0
+#define BIT_MASK_HOST_MSG_3_8821C 0xffffffffL
+#define BIT_HOST_MSG_3_8821C(x)                                                \
+	(((x) & BIT_MASK_HOST_MSG_3_8821C) << BIT_SHIFT_HOST_MSG_3_8821C)
+#define BITS_HOST_MSG_3_8821C                                                  \
+	(BIT_MASK_HOST_MSG_3_8821C << BIT_SHIFT_HOST_MSG_3_8821C)
+#define BIT_CLEAR_HOST_MSG_3_8821C(x) ((x) & (~BITS_HOST_MSG_3_8821C))
+#define BIT_GET_HOST_MSG_3_8821C(x)                                            \
+	(((x) >> BIT_SHIFT_HOST_MSG_3_8821C) & BIT_MASK_HOST_MSG_3_8821C)
+#define BIT_SET_HOST_MSG_3_8821C(x, v)                                         \
+	(BIT_CLEAR_HOST_MSG_3_8821C(x) | BIT_HOST_MSG_3_8821C(v))
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_BB_ACCESS_CTRL_8821C */
+
+#define BIT_SHIFT_BB_WRITE_READ_8821C 30
+#define BIT_MASK_BB_WRITE_READ_8821C 0x3
+#define BIT_BB_WRITE_READ_8821C(x)                                             \
+	(((x) & BIT_MASK_BB_WRITE_READ_8821C) << BIT_SHIFT_BB_WRITE_READ_8821C)
+#define BITS_BB_WRITE_READ_8821C                                               \
+	(BIT_MASK_BB_WRITE_READ_8821C << BIT_SHIFT_BB_WRITE_READ_8821C)
+#define BIT_CLEAR_BB_WRITE_READ_8821C(x) ((x) & (~BITS_BB_WRITE_READ_8821C))
+#define BIT_GET_BB_WRITE_READ_8821C(x)                                         \
+	(((x) >> BIT_SHIFT_BB_WRITE_READ_8821C) & BIT_MASK_BB_WRITE_READ_8821C)
+#define BIT_SET_BB_WRITE_READ_8821C(x, v)                                      \
+	(BIT_CLEAR_BB_WRITE_READ_8821C(x) | BIT_BB_WRITE_READ_8821C(v))
+
+#define BIT_SHIFT_BB_WRITE_EN_8821C 12
+#define BIT_MASK_BB_WRITE_EN_8821C 0xf
+#define BIT_BB_WRITE_EN_8821C(x)                                               \
+	(((x) & BIT_MASK_BB_WRITE_EN_8821C) << BIT_SHIFT_BB_WRITE_EN_8821C)
+#define BITS_BB_WRITE_EN_8821C                                                 \
+	(BIT_MASK_BB_WRITE_EN_8821C << BIT_SHIFT_BB_WRITE_EN_8821C)
+#define BIT_CLEAR_BB_WRITE_EN_8821C(x) ((x) & (~BITS_BB_WRITE_EN_8821C))
+#define BIT_GET_BB_WRITE_EN_8821C(x)                                           \
+	(((x) >> BIT_SHIFT_BB_WRITE_EN_8821C) & BIT_MASK_BB_WRITE_EN_8821C)
+#define BIT_SET_BB_WRITE_EN_8821C(x, v)                                        \
+	(BIT_CLEAR_BB_WRITE_EN_8821C(x) | BIT_BB_WRITE_EN_8821C(v))
+
+#define BIT_SHIFT_BB_ADDR_8821C 2
+#define BIT_MASK_BB_ADDR_8821C 0x1ff
+#define BIT_BB_ADDR_8821C(x)                                                   \
+	(((x) & BIT_MASK_BB_ADDR_8821C) << BIT_SHIFT_BB_ADDR_8821C)
+#define BITS_BB_ADDR_8821C (BIT_MASK_BB_ADDR_8821C << BIT_SHIFT_BB_ADDR_8821C)
+#define BIT_CLEAR_BB_ADDR_8821C(x) ((x) & (~BITS_BB_ADDR_8821C))
+#define BIT_GET_BB_ADDR_8821C(x)                                               \
+	(((x) >> BIT_SHIFT_BB_ADDR_8821C) & BIT_MASK_BB_ADDR_8821C)
+#define BIT_SET_BB_ADDR_8821C(x, v)                                            \
+	(BIT_CLEAR_BB_ADDR_8821C(x) | BIT_BB_ADDR_8821C(v))
+
+#define BIT_BB_ERRACC_8821C BIT(0)
+
+/* 2 REG_BB_ACCESS_DATA_8821C */
+
+#define BIT_SHIFT_BB_DATA_8821C 0
+#define BIT_MASK_BB_DATA_8821C 0xffffffffL
+#define BIT_BB_DATA_8821C(x)                                                   \
+	(((x) & BIT_MASK_BB_DATA_8821C) << BIT_SHIFT_BB_DATA_8821C)
+#define BITS_BB_DATA_8821C (BIT_MASK_BB_DATA_8821C << BIT_SHIFT_BB_DATA_8821C)
+#define BIT_CLEAR_BB_DATA_8821C(x) ((x) & (~BITS_BB_DATA_8821C))
+#define BIT_GET_BB_DATA_8821C(x)                                               \
+	(((x) >> BIT_SHIFT_BB_DATA_8821C) & BIT_MASK_BB_DATA_8821C)
+#define BIT_SET_BB_DATA_8821C(x, v)                                            \
+	(BIT_CLEAR_BB_DATA_8821C(x) | BIT_BB_DATA_8821C(v))
+
+/* 2 REG_HMEBOX_E0_8821C */
+
+#define BIT_SHIFT_HMEBOX_E0_8821C 0
+#define BIT_MASK_HMEBOX_E0_8821C 0xffffffffL
+#define BIT_HMEBOX_E0_8821C(x)                                                 \
+	(((x) & BIT_MASK_HMEBOX_E0_8821C) << BIT_SHIFT_HMEBOX_E0_8821C)
+#define BITS_HMEBOX_E0_8821C                                                   \
+	(BIT_MASK_HMEBOX_E0_8821C << BIT_SHIFT_HMEBOX_E0_8821C)
+#define BIT_CLEAR_HMEBOX_E0_8821C(x) ((x) & (~BITS_HMEBOX_E0_8821C))
+#define BIT_GET_HMEBOX_E0_8821C(x)                                             \
+	(((x) >> BIT_SHIFT_HMEBOX_E0_8821C) & BIT_MASK_HMEBOX_E0_8821C)
+#define BIT_SET_HMEBOX_E0_8821C(x, v)                                          \
+	(BIT_CLEAR_HMEBOX_E0_8821C(x) | BIT_HMEBOX_E0_8821C(v))
+
+/* 2 REG_HMEBOX_E1_8821C */
+
+#define BIT_SHIFT_HMEBOX_E1_8821C 0
+#define BIT_MASK_HMEBOX_E1_8821C 0xffffffffL
+#define BIT_HMEBOX_E1_8821C(x)                                                 \
+	(((x) & BIT_MASK_HMEBOX_E1_8821C) << BIT_SHIFT_HMEBOX_E1_8821C)
+#define BITS_HMEBOX_E1_8821C                                                   \
+	(BIT_MASK_HMEBOX_E1_8821C << BIT_SHIFT_HMEBOX_E1_8821C)
+#define BIT_CLEAR_HMEBOX_E1_8821C(x) ((x) & (~BITS_HMEBOX_E1_8821C))
+#define BIT_GET_HMEBOX_E1_8821C(x)                                             \
+	(((x) >> BIT_SHIFT_HMEBOX_E1_8821C) & BIT_MASK_HMEBOX_E1_8821C)
+#define BIT_SET_HMEBOX_E1_8821C(x, v)                                          \
+	(BIT_CLEAR_HMEBOX_E1_8821C(x) | BIT_HMEBOX_E1_8821C(v))
+
+/* 2 REG_HMEBOX_E2_8821C */
+
+#define BIT_SHIFT_HMEBOX_E2_8821C 0
+#define BIT_MASK_HMEBOX_E2_8821C 0xffffffffL
+#define BIT_HMEBOX_E2_8821C(x)                                                 \
+	(((x) & BIT_MASK_HMEBOX_E2_8821C) << BIT_SHIFT_HMEBOX_E2_8821C)
+#define BITS_HMEBOX_E2_8821C                                                   \
+	(BIT_MASK_HMEBOX_E2_8821C << BIT_SHIFT_HMEBOX_E2_8821C)
+#define BIT_CLEAR_HMEBOX_E2_8821C(x) ((x) & (~BITS_HMEBOX_E2_8821C))
+#define BIT_GET_HMEBOX_E2_8821C(x)                                             \
+	(((x) >> BIT_SHIFT_HMEBOX_E2_8821C) & BIT_MASK_HMEBOX_E2_8821C)
+#define BIT_SET_HMEBOX_E2_8821C(x, v)                                          \
+	(BIT_CLEAR_HMEBOX_E2_8821C(x) | BIT_HMEBOX_E2_8821C(v))
+
+/* 2 REG_HMEBOX_E3_8821C */
+
+#define BIT_SHIFT_HMEBOX_E3_8821C 0
+#define BIT_MASK_HMEBOX_E3_8821C 0xffffffffL
+#define BIT_HMEBOX_E3_8821C(x)                                                 \
+	(((x) & BIT_MASK_HMEBOX_E3_8821C) << BIT_SHIFT_HMEBOX_E3_8821C)
+#define BITS_HMEBOX_E3_8821C                                                   \
+	(BIT_MASK_HMEBOX_E3_8821C << BIT_SHIFT_HMEBOX_E3_8821C)
+#define BIT_CLEAR_HMEBOX_E3_8821C(x) ((x) & (~BITS_HMEBOX_E3_8821C))
+#define BIT_GET_HMEBOX_E3_8821C(x)                                             \
+	(((x) >> BIT_SHIFT_HMEBOX_E3_8821C) & BIT_MASK_HMEBOX_E3_8821C)
+#define BIT_SET_HMEBOX_E3_8821C(x, v)                                          \
+	(BIT_CLEAR_HMEBOX_E3_8821C(x) | BIT_HMEBOX_E3_8821C(v))
+
+/* 2 REG_CR_EXT_8821C */
+
+#define BIT_SHIFT_PHY_REQ_DELAY_8821C 24
+#define BIT_MASK_PHY_REQ_DELAY_8821C 0xf
+#define BIT_PHY_REQ_DELAY_8821C(x)                                             \
+	(((x) & BIT_MASK_PHY_REQ_DELAY_8821C) << BIT_SHIFT_PHY_REQ_DELAY_8821C)
+#define BITS_PHY_REQ_DELAY_8821C                                               \
+	(BIT_MASK_PHY_REQ_DELAY_8821C << BIT_SHIFT_PHY_REQ_DELAY_8821C)
+#define BIT_CLEAR_PHY_REQ_DELAY_8821C(x) ((x) & (~BITS_PHY_REQ_DELAY_8821C))
+#define BIT_GET_PHY_REQ_DELAY_8821C(x)                                         \
+	(((x) >> BIT_SHIFT_PHY_REQ_DELAY_8821C) & BIT_MASK_PHY_REQ_DELAY_8821C)
+#define BIT_SET_PHY_REQ_DELAY_8821C(x, v)                                      \
+	(BIT_CLEAR_PHY_REQ_DELAY_8821C(x) | BIT_PHY_REQ_DELAY_8821C(v))
+
+/* 2 REG_NOT_VALID_8821C */
+#define BIT_SPD_DOWN_8821C BIT(16)
+
+/* 2 REG_NOT_VALID_8821C */
+
+#define BIT_SHIFT_NETYPE4_8821C 4
+#define BIT_MASK_NETYPE4_8821C 0x3
+#define BIT_NETYPE4_8821C(x)                                                   \
+	(((x) & BIT_MASK_NETYPE4_8821C) << BIT_SHIFT_NETYPE4_8821C)
+#define BITS_NETYPE4_8821C (BIT_MASK_NETYPE4_8821C << BIT_SHIFT_NETYPE4_8821C)
+#define BIT_CLEAR_NETYPE4_8821C(x) ((x) & (~BITS_NETYPE4_8821C))
+#define BIT_GET_NETYPE4_8821C(x)                                               \
+	(((x) >> BIT_SHIFT_NETYPE4_8821C) & BIT_MASK_NETYPE4_8821C)
+#define BIT_SET_NETYPE4_8821C(x, v)                                            \
+	(BIT_CLEAR_NETYPE4_8821C(x) | BIT_NETYPE4_8821C(v))
+
+#define BIT_SHIFT_NETYPE3_8821C 2
+#define BIT_MASK_NETYPE3_8821C 0x3
+#define BIT_NETYPE3_8821C(x)                                                   \
+	(((x) & BIT_MASK_NETYPE3_8821C) << BIT_SHIFT_NETYPE3_8821C)
+#define BITS_NETYPE3_8821C (BIT_MASK_NETYPE3_8821C << BIT_SHIFT_NETYPE3_8821C)
+#define BIT_CLEAR_NETYPE3_8821C(x) ((x) & (~BITS_NETYPE3_8821C))
+#define BIT_GET_NETYPE3_8821C(x)                                               \
+	(((x) >> BIT_SHIFT_NETYPE3_8821C) & BIT_MASK_NETYPE3_8821C)
+#define BIT_SET_NETYPE3_8821C(x, v)                                            \
+	(BIT_CLEAR_NETYPE3_8821C(x) | BIT_NETYPE3_8821C(v))
+
+#define BIT_SHIFT_NETYPE2_8821C 0
+#define BIT_MASK_NETYPE2_8821C 0x3
+#define BIT_NETYPE2_8821C(x)                                                   \
+	(((x) & BIT_MASK_NETYPE2_8821C) << BIT_SHIFT_NETYPE2_8821C)
+#define BITS_NETYPE2_8821C (BIT_MASK_NETYPE2_8821C << BIT_SHIFT_NETYPE2_8821C)
+#define BIT_CLEAR_NETYPE2_8821C(x) ((x) & (~BITS_NETYPE2_8821C))
+#define BIT_GET_NETYPE2_8821C(x)                                               \
+	(((x) >> BIT_SHIFT_NETYPE2_8821C) & BIT_MASK_NETYPE2_8821C)
+#define BIT_SET_NETYPE2_8821C(x, v)                                            \
+	(BIT_CLEAR_NETYPE2_8821C(x) | BIT_NETYPE2_8821C(v))
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_FWFF_8821C */
+
+#define BIT_SHIFT_PKTNUM_TH_V1_8821C 24
+#define BIT_MASK_PKTNUM_TH_V1_8821C 0xff
+#define BIT_PKTNUM_TH_V1_8821C(x)                                              \
+	(((x) & BIT_MASK_PKTNUM_TH_V1_8821C) << BIT_SHIFT_PKTNUM_TH_V1_8821C)
+#define BITS_PKTNUM_TH_V1_8821C                                                \
+	(BIT_MASK_PKTNUM_TH_V1_8821C << BIT_SHIFT_PKTNUM_TH_V1_8821C)
+#define BIT_CLEAR_PKTNUM_TH_V1_8821C(x) ((x) & (~BITS_PKTNUM_TH_V1_8821C))
+#define BIT_GET_PKTNUM_TH_V1_8821C(x)                                          \
+	(((x) >> BIT_SHIFT_PKTNUM_TH_V1_8821C) & BIT_MASK_PKTNUM_TH_V1_8821C)
+#define BIT_SET_PKTNUM_TH_V1_8821C(x, v)                                       \
+	(BIT_CLEAR_PKTNUM_TH_V1_8821C(x) | BIT_PKTNUM_TH_V1_8821C(v))
+
+#define BIT_SHIFT_TIMER_TH_8821C 16
+#define BIT_MASK_TIMER_TH_8821C 0xff
+#define BIT_TIMER_TH_8821C(x)                                                  \
+	(((x) & BIT_MASK_TIMER_TH_8821C) << BIT_SHIFT_TIMER_TH_8821C)
+#define BITS_TIMER_TH_8821C                                                    \
+	(BIT_MASK_TIMER_TH_8821C << BIT_SHIFT_TIMER_TH_8821C)
+#define BIT_CLEAR_TIMER_TH_8821C(x) ((x) & (~BITS_TIMER_TH_8821C))
+#define BIT_GET_TIMER_TH_8821C(x)                                              \
+	(((x) >> BIT_SHIFT_TIMER_TH_8821C) & BIT_MASK_TIMER_TH_8821C)
+#define BIT_SET_TIMER_TH_8821C(x, v)                                           \
+	(BIT_CLEAR_TIMER_TH_8821C(x) | BIT_TIMER_TH_8821C(v))
+
+#define BIT_SHIFT_RXPKT1ENADDR_8821C 0
+#define BIT_MASK_RXPKT1ENADDR_8821C 0xffff
+#define BIT_RXPKT1ENADDR_8821C(x)                                              \
+	(((x) & BIT_MASK_RXPKT1ENADDR_8821C) << BIT_SHIFT_RXPKT1ENADDR_8821C)
+#define BITS_RXPKT1ENADDR_8821C                                                \
+	(BIT_MASK_RXPKT1ENADDR_8821C << BIT_SHIFT_RXPKT1ENADDR_8821C)
+#define BIT_CLEAR_RXPKT1ENADDR_8821C(x) ((x) & (~BITS_RXPKT1ENADDR_8821C))
+#define BIT_GET_RXPKT1ENADDR_8821C(x)                                          \
+	(((x) >> BIT_SHIFT_RXPKT1ENADDR_8821C) & BIT_MASK_RXPKT1ENADDR_8821C)
+#define BIT_SET_RXPKT1ENADDR_8821C(x, v)                                       \
+	(BIT_CLEAR_RXPKT1ENADDR_8821C(x) | BIT_RXPKT1ENADDR_8821C(v))
+
+/* 2 REG_RXFF_PTR_V1_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+#define BIT_SHIFT_RXFF0_RDPTR_V2_8821C 0
+#define BIT_MASK_RXFF0_RDPTR_V2_8821C 0x3ffff
+#define BIT_RXFF0_RDPTR_V2_8821C(x)                                            \
+	(((x) & BIT_MASK_RXFF0_RDPTR_V2_8821C)                                 \
+	 << BIT_SHIFT_RXFF0_RDPTR_V2_8821C)
+#define BITS_RXFF0_RDPTR_V2_8821C                                              \
+	(BIT_MASK_RXFF0_RDPTR_V2_8821C << BIT_SHIFT_RXFF0_RDPTR_V2_8821C)
+#define BIT_CLEAR_RXFF0_RDPTR_V2_8821C(x) ((x) & (~BITS_RXFF0_RDPTR_V2_8821C))
+#define BIT_GET_RXFF0_RDPTR_V2_8821C(x)                                        \
+	(((x) >> BIT_SHIFT_RXFF0_RDPTR_V2_8821C) &                             \
+	 BIT_MASK_RXFF0_RDPTR_V2_8821C)
+#define BIT_SET_RXFF0_RDPTR_V2_8821C(x, v)                                     \
+	(BIT_CLEAR_RXFF0_RDPTR_V2_8821C(x) | BIT_RXFF0_RDPTR_V2_8821C(v))
+
+/* 2 REG_RXFF_WTR_V1_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+#define BIT_SHIFT_RXFF0_WTPTR_V2_8821C 0
+#define BIT_MASK_RXFF0_WTPTR_V2_8821C 0x3ffff
+#define BIT_RXFF0_WTPTR_V2_8821C(x)                                            \
+	(((x) & BIT_MASK_RXFF0_WTPTR_V2_8821C)                                 \
+	 << BIT_SHIFT_RXFF0_WTPTR_V2_8821C)
+#define BITS_RXFF0_WTPTR_V2_8821C                                              \
+	(BIT_MASK_RXFF0_WTPTR_V2_8821C << BIT_SHIFT_RXFF0_WTPTR_V2_8821C)
+#define BIT_CLEAR_RXFF0_WTPTR_V2_8821C(x) ((x) & (~BITS_RXFF0_WTPTR_V2_8821C))
+#define BIT_GET_RXFF0_WTPTR_V2_8821C(x)                                        \
+	(((x) >> BIT_SHIFT_RXFF0_WTPTR_V2_8821C) &                             \
+	 BIT_MASK_RXFF0_WTPTR_V2_8821C)
+#define BIT_SET_RXFF0_WTPTR_V2_8821C(x, v)                                     \
+	(BIT_CLEAR_RXFF0_WTPTR_V2_8821C(x) | BIT_RXFF0_WTPTR_V2_8821C(v))
+
+/* 2 REG_FE2IMR_8821C */
+#define BIT__FE4ISR__IND_MSK_8821C BIT(29)
+#define BIT_FS_TXSC_DESC_DONE_INT_EN_8821C BIT(28)
+#define BIT_FS_TXSC_BKDONE_INT_EN_8821C BIT(27)
+#define BIT_FS_TXSC_BEDONE_INT_EN_8821C BIT(26)
+#define BIT_FS_TXSC_VIDONE_INT_EN_8821C BIT(25)
+#define BIT_FS_TXSC_VODONE_INT_EN_8821C BIT(24)
+#define BIT_FS_ATIM_MB7_INT_EN_8821C BIT(23)
+#define BIT_FS_ATIM_MB6_INT_EN_8821C BIT(22)
+#define BIT_FS_ATIM_MB5_INT_EN_8821C BIT(21)
+#define BIT_FS_ATIM_MB4_INT_EN_8821C BIT(20)
+#define BIT_FS_ATIM_MB3_INT_EN_8821C BIT(19)
+#define BIT_FS_ATIM_MB2_INT_EN_8821C BIT(18)
+#define BIT_FS_ATIM_MB1_INT_EN_8821C BIT(17)
+#define BIT_FS_ATIM_MB0_INT_EN_8821C BIT(16)
+#define BIT_FS_TBTT4INT_EN_8821C BIT(11)
+#define BIT_FS_TBTT3INT_EN_8821C BIT(10)
+#define BIT_FS_TBTT2INT_EN_8821C BIT(9)
+#define BIT_FS_TBTT1INT_EN_8821C BIT(8)
+#define BIT_FS_TBTT0_MB7INT_EN_8821C BIT(7)
+#define BIT_FS_TBTT0_MB6INT_EN_8821C BIT(6)
+#define BIT_FS_TBTT0_MB5INT_EN_8821C BIT(5)
+#define BIT_FS_TBTT0_MB4INT_EN_8821C BIT(4)
+#define BIT_FS_TBTT0_MB3INT_EN_8821C BIT(3)
+#define BIT_FS_TBTT0_MB2INT_EN_8821C BIT(2)
+#define BIT_FS_TBTT0_MB1INT_EN_8821C BIT(1)
+#define BIT_FS_TBTT0_INT_EN_8821C BIT(0)
+
+/* 2 REG_FE2ISR_8821C */
+#define BIT__FE4ISR__IND_INT_8821C BIT(29)
+#define BIT_FS_TXSC_DESC_DONE_INT_8821C BIT(28)
+#define BIT_FS_TXSC_BKDONE_INT_8821C BIT(27)
+#define BIT_FS_TXSC_BEDONE_INT_8821C BIT(26)
+#define BIT_FS_TXSC_VIDONE_INT_8821C BIT(25)
+#define BIT_FS_TXSC_VODONE_INT_8821C BIT(24)
+#define BIT_FS_ATIM_MB7_INT_8821C BIT(23)
+#define BIT_FS_ATIM_MB6_INT_8821C BIT(22)
+#define BIT_FS_ATIM_MB5_INT_8821C BIT(21)
+#define BIT_FS_ATIM_MB4_INT_8821C BIT(20)
+#define BIT_FS_ATIM_MB3_INT_8821C BIT(19)
+#define BIT_FS_ATIM_MB2_INT_8821C BIT(18)
+#define BIT_FS_ATIM_MB1_INT_8821C BIT(17)
+#define BIT_FS_ATIM_MB0_INT_8821C BIT(16)
+#define BIT_FS_TBTT4INT_8821C BIT(11)
+#define BIT_FS_TBTT3INT_8821C BIT(10)
+#define BIT_FS_TBTT2INT_8821C BIT(9)
+#define BIT_FS_TBTT1INT_8821C BIT(8)
+#define BIT_FS_TBTT0_MB7INT_8821C BIT(7)
+#define BIT_FS_TBTT0_MB6INT_8821C BIT(6)
+#define BIT_FS_TBTT0_MB5INT_8821C BIT(5)
+#define BIT_FS_TBTT0_MB4INT_8821C BIT(4)
+#define BIT_FS_TBTT0_MB3INT_8821C BIT(3)
+#define BIT_FS_TBTT0_MB2INT_8821C BIT(2)
+#define BIT_FS_TBTT0_MB1INT_8821C BIT(1)
+#define BIT_FS_TBTT0_INT_8821C BIT(0)
+
+/* 2 REG_FE3IMR_8821C */
+#define BIT_FS_CLI3_MTI_BCNIVLEAR_INT__EN_8821C BIT(31)
+#define BIT_FS_CLI2_MTI_BCNIVLEAR_INT__EN_8821C BIT(30)
+#define BIT_FS_CLI1_MTI_BCNIVLEAR_INT__EN_8821C BIT(29)
+#define BIT_FS_CLI0_MTI_BCNIVLEAR_INT__EN_8821C BIT(28)
+#define BIT_FS_BCNDMA4_INT_EN_8821C BIT(27)
+#define BIT_FS_BCNDMA3_INT_EN_8821C BIT(26)
+#define BIT_FS_BCNDMA2_INT_EN_8821C BIT(25)
+#define BIT_FS_BCNDMA1_INT_EN_8821C BIT(24)
+#define BIT_FS_BCNDMA0_MB7_INT_EN_8821C BIT(23)
+#define BIT_FS_BCNDMA0_MB6_INT_EN_8821C BIT(22)
+#define BIT_FS_BCNDMA0_MB5_INT_EN_8821C BIT(21)
+#define BIT_FS_BCNDMA0_MB4_INT_EN_8821C BIT(20)
+#define BIT_FS_BCNDMA0_MB3_INT_EN_8821C BIT(19)
+#define BIT_FS_BCNDMA0_MB2_INT_EN_8821C BIT(18)
+#define BIT_FS_BCNDMA0_MB1_INT_EN_8821C BIT(17)
+#define BIT_FS_BCNDMA0_INT_EN_8821C BIT(16)
+#define BIT_FS_MTI_BCNIVLEAR_INT__EN_8821C BIT(15)
+#define BIT_FS_BCNERLY4_INT_EN_8821C BIT(11)
+#define BIT_FS_BCNERLY3_INT_EN_8821C BIT(10)
+#define BIT_FS_BCNERLY2_INT_EN_8821C BIT(9)
+#define BIT_FS_BCNERLY1_INT_EN_8821C BIT(8)
+#define BIT_FS_BCNERLY0_MB7INT_EN_8821C BIT(7)
+#define BIT_FS_BCNERLY0_MB6INT_EN_8821C BIT(6)
+#define BIT_FS_BCNERLY0_MB5INT_EN_8821C BIT(5)
+#define BIT_FS_BCNERLY0_MB4INT_EN_8821C BIT(4)
+#define BIT_FS_BCNERLY0_MB3INT_EN_8821C BIT(3)
+#define BIT_FS_BCNERLY0_MB2INT_EN_8821C BIT(2)
+#define BIT_FS_BCNERLY0_MB1INT_EN_8821C BIT(1)
+#define BIT_FS_BCNERLY0_INT_EN_8821C BIT(0)
+
+/* 2 REG_FE3ISR_8821C */
+#define BIT_FS_CLI3_MTI_BCNIVLEAR_INT_8821C BIT(31)
+#define BIT_FS_CLI2_MTI_BCNIVLEAR_INT_8821C BIT(30)
+#define BIT_FS_CLI1_MTI_BCNIVLEAR_INT_8821C BIT(29)
+#define BIT_FS_CLI0_MTI_BCNIVLEAR_INT_8821C BIT(28)
+#define BIT_FS_BCNDMA4_INT_8821C BIT(27)
+#define BIT_FS_BCNDMA3_INT_8821C BIT(26)
+#define BIT_FS_BCNDMA2_INT_8821C BIT(25)
+#define BIT_FS_BCNDMA1_INT_8821C BIT(24)
+#define BIT_FS_BCNDMA0_MB7_INT_8821C BIT(23)
+#define BIT_FS_BCNDMA0_MB6_INT_8821C BIT(22)
+#define BIT_FS_BCNDMA0_MB5_INT_8821C BIT(21)
+#define BIT_FS_BCNDMA0_MB4_INT_8821C BIT(20)
+#define BIT_FS_BCNDMA0_MB3_INT_8821C BIT(19)
+#define BIT_FS_BCNDMA0_MB2_INT_8821C BIT(18)
+#define BIT_FS_BCNDMA0_MB1_INT_8821C BIT(17)
+#define BIT_FS_BCNDMA0_INT_8821C BIT(16)
+#define BIT_FS_MTI_BCNIVLEAR_INT_8821C BIT(15)
+#define BIT_FS_BCNERLY4_INT_8821C BIT(11)
+#define BIT_FS_BCNERLY3_INT_8821C BIT(10)
+#define BIT_FS_BCNERLY2_INT_8821C BIT(9)
+#define BIT_FS_BCNERLY1_INT_8821C BIT(8)
+#define BIT_FS_BCNERLY0_MB7INT_8821C BIT(7)
+#define BIT_FS_BCNERLY0_MB6INT_8821C BIT(6)
+#define BIT_FS_BCNERLY0_MB5INT_8821C BIT(5)
+#define BIT_FS_BCNERLY0_MB4INT_8821C BIT(4)
+#define BIT_FS_BCNERLY0_MB3INT_8821C BIT(3)
+#define BIT_FS_BCNERLY0_MB2INT_8821C BIT(2)
+#define BIT_FS_BCNERLY0_MB1INT_8821C BIT(1)
+#define BIT_FS_BCNERLY0_INT_8821C BIT(0)
+
+/* 2 REG_FE4IMR_8821C */
+#define BIT_FS_CLI3_TXPKTIN_INT_EN_8821C BIT(19)
+#define BIT_FS_CLI2_TXPKTIN_INT_EN_8821C BIT(18)
+#define BIT_FS_CLI1_TXPKTIN_INT_EN_8821C BIT(17)
+#define BIT_FS_CLI0_TXPKTIN_INT_EN_8821C BIT(16)
+#define BIT_FS_CLI3_RX_UMD0_INT_EN_8821C BIT(15)
+#define BIT_FS_CLI3_RX_UMD1_INT_EN_8821C BIT(14)
+#define BIT_FS_CLI3_RX_BMD0_INT_EN_8821C BIT(13)
+#define BIT_FS_CLI3_RX_BMD1_INT_EN_8821C BIT(12)
+#define BIT_FS_CLI2_RX_UMD0_INT_EN_8821C BIT(11)
+#define BIT_FS_CLI2_RX_UMD1_INT_EN_8821C BIT(10)
+#define BIT_FS_CLI2_RX_BMD0_INT_EN_8821C BIT(9)
+#define BIT_FS_CLI2_RX_BMD1_INT_EN_8821C BIT(8)
+#define BIT_FS_CLI1_RX_UMD0_INT_EN_8821C BIT(7)
+#define BIT_FS_CLI1_RX_UMD1_INT_EN_8821C BIT(6)
+#define BIT_FS_CLI1_RX_BMD0_INT_EN_8821C BIT(5)
+#define BIT_FS_CLI1_RX_BMD1_INT_EN_8821C BIT(4)
+#define BIT_FS_CLI0_RX_UMD0_INT_EN_8821C BIT(3)
+#define BIT_FS_CLI0_RX_UMD1_INT_EN_8821C BIT(2)
+#define BIT_FS_CLI0_RX_BMD0_INT_EN_8821C BIT(1)
+#define BIT_FS_CLI0_RX_BMD1_INT_EN_8821C BIT(0)
+
+/* 2 REG_FE4ISR_8821C */
+#define BIT_FS_CLI3_TXPKTIN_INT_8821C BIT(19)
+#define BIT_FS_CLI2_TXPKTIN_INT_8821C BIT(18)
+#define BIT_FS_CLI1_TXPKTIN_INT_8821C BIT(17)
+#define BIT_FS_CLI0_TXPKTIN_INT_8821C BIT(16)
+#define BIT_FS_CLI3_RX_UMD0_INT_8821C BIT(15)
+#define BIT_FS_CLI3_RX_UMD1_INT_8821C BIT(14)
+#define BIT_FS_CLI3_RX_BMD0_INT_8821C BIT(13)
+#define BIT_FS_CLI3_RX_BMD1_INT_8821C BIT(12)
+#define BIT_FS_CLI2_RX_UMD0_INT_8821C BIT(11)
+#define BIT_FS_CLI2_RX_UMD1_INT_8821C BIT(10)
+#define BIT_FS_CLI2_RX_BMD0_INT_8821C BIT(9)
+#define BIT_FS_CLI2_RX_BMD1_INT_8821C BIT(8)
+#define BIT_FS_CLI1_RX_UMD0_INT_8821C BIT(7)
+#define BIT_FS_CLI1_RX_UMD1_INT_8821C BIT(6)
+#define BIT_FS_CLI1_RX_BMD0_INT_8821C BIT(5)
+#define BIT_FS_CLI1_RX_BMD1_INT_8821C BIT(4)
+#define BIT_FS_CLI0_RX_UMD0_INT_8821C BIT(3)
+#define BIT_FS_CLI0_RX_UMD1_INT_8821C BIT(2)
+#define BIT_FS_CLI0_RX_BMD0_INT_8821C BIT(1)
+#define BIT_FS_CLI0_RX_BMD1_INT_8821C BIT(0)
+
+/* 2 REG_FT1IMR_8821C */
+#define BIT__FT2ISR__IND_MSK_8821C BIT(30)
+#define BIT_FTM_PTT_INT_EN_8821C BIT(29)
+#define BIT_RXFTMREQ_INT_EN_8821C BIT(28)
+#define BIT_RXFTM_INT_EN_8821C BIT(27)
+#define BIT_TXFTM_INT_EN_8821C BIT(26)
+#define BIT_FS_H2C_CMD_OK_INT_EN_8821C BIT(25)
+#define BIT_FS_H2C_CMD_FULL_INT_EN_8821C BIT(24)
+#define BIT_FS_MACID_PWRCHANGE5_INT_EN_8821C BIT(23)
+#define BIT_FS_MACID_PWRCHANGE4_INT_EN_8821C BIT(22)
+#define BIT_FS_MACID_PWRCHANGE3_INT_EN_8821C BIT(21)
+#define BIT_FS_MACID_PWRCHANGE2_INT_EN_8821C BIT(20)
+#define BIT_FS_MACID_PWRCHANGE1_INT_EN_8821C BIT(19)
+#define BIT_FS_MACID_PWRCHANGE0_INT_EN_8821C BIT(18)
+#define BIT_FS_CTWEND2_INT_EN_8821C BIT(17)
+#define BIT_FS_CTWEND1_INT_EN_8821C BIT(16)
+#define BIT_FS_CTWEND0_INT_EN_8821C BIT(15)
+#define BIT_FS_TX_NULL1_INT_EN_8821C BIT(14)
+#define BIT_FS_TX_NULL0_INT_EN_8821C BIT(13)
+#define BIT_FS_TSF_BIT32_TOGGLE_EN_8821C BIT(12)
+#define BIT_FS_P2P_RFON2_INT_EN_8821C BIT(11)
+#define BIT_FS_P2P_RFOFF2_INT_EN_8821C BIT(10)
+#define BIT_FS_P2P_RFON1_INT_EN_8821C BIT(9)
+#define BIT_FS_P2P_RFOFF1_INT_EN_8821C BIT(8)
+#define BIT_FS_P2P_RFON0_INT_EN_8821C BIT(7)
+#define BIT_FS_P2P_RFOFF0_INT_EN_8821C BIT(6)
+#define BIT_FS_RX_UAPSDMD1_EN_8821C BIT(5)
+#define BIT_FS_RX_UAPSDMD0_EN_8821C BIT(4)
+#define BIT_FS_TRIGGER_PKT_EN_8821C BIT(3)
+#define BIT_FS_EOSP_INT_EN_8821C BIT(2)
+#define BIT_FS_RPWM2_INT_EN_8821C BIT(1)
+#define BIT_FS_RPWM_INT_EN_8821C BIT(0)
+
+/* 2 REG_FT1ISR_8821C */
+#define BIT__FT2ISR__IND_INT_8821C BIT(30)
+#define BIT_FTM_PTT_INT_8821C BIT(29)
+#define BIT_RXFTMREQ_INT_8821C BIT(28)
+#define BIT_RXFTM_INT_8821C BIT(27)
+#define BIT_TXFTM_INT_8821C BIT(26)
+#define BIT_FS_H2C_CMD_OK_INT_8821C BIT(25)
+#define BIT_FS_H2C_CMD_FULL_INT_8821C BIT(24)
+#define BIT_FS_MACID_PWRCHANGE5_INT_8821C BIT(23)
+#define BIT_FS_MACID_PWRCHANGE4_INT_8821C BIT(22)
+#define BIT_FS_MACID_PWRCHANGE3_INT_8821C BIT(21)
+#define BIT_FS_MACID_PWRCHANGE2_INT_8821C BIT(20)
+#define BIT_FS_MACID_PWRCHANGE1_INT_8821C BIT(19)
+#define BIT_FS_MACID_PWRCHANGE0_INT_8821C BIT(18)
+#define BIT_FS_CTWEND2_INT_8821C BIT(17)
+#define BIT_FS_CTWEND1_INT_8821C BIT(16)
+#define BIT_FS_CTWEND0_INT_8821C BIT(15)
+#define BIT_FS_TX_NULL1_INT_8821C BIT(14)
+#define BIT_FS_TX_NULL0_INT_8821C BIT(13)
+#define BIT_FS_TSF_BIT32_TOGGLE_INT_8821C BIT(12)
+#define BIT_FS_P2P_RFON2_INT_8821C BIT(11)
+#define BIT_FS_P2P_RFOFF2_INT_8821C BIT(10)
+#define BIT_FS_P2P_RFON1_INT_8821C BIT(9)
+#define BIT_FS_P2P_RFOFF1_INT_8821C BIT(8)
+#define BIT_FS_P2P_RFON0_INT_8821C BIT(7)
+#define BIT_FS_P2P_RFOFF0_INT_8821C BIT(6)
+#define BIT_FS_RX_UAPSDMD1_INT_8821C BIT(5)
+#define BIT_FS_RX_UAPSDMD0_INT_8821C BIT(4)
+#define BIT_FS_TRIGGER_PKT_INT_8821C BIT(3)
+#define BIT_FS_EOSP_INT_8821C BIT(2)
+#define BIT_FS_RPWM2_INT_8821C BIT(1)
+#define BIT_FS_RPWM_INT_8821C BIT(0)
+
+/* 2 REG_SPWR0_8821C */
+
+#define BIT_SHIFT_MID_31TO0_8821C 0
+#define BIT_MASK_MID_31TO0_8821C 0xffffffffL
+#define BIT_MID_31TO0_8821C(x)                                                 \
+	(((x) & BIT_MASK_MID_31TO0_8821C) << BIT_SHIFT_MID_31TO0_8821C)
+#define BITS_MID_31TO0_8821C                                                   \
+	(BIT_MASK_MID_31TO0_8821C << BIT_SHIFT_MID_31TO0_8821C)
+#define BIT_CLEAR_MID_31TO0_8821C(x) ((x) & (~BITS_MID_31TO0_8821C))
+#define BIT_GET_MID_31TO0_8821C(x)                                             \
+	(((x) >> BIT_SHIFT_MID_31TO0_8821C) & BIT_MASK_MID_31TO0_8821C)
+#define BIT_SET_MID_31TO0_8821C(x, v)                                          \
+	(BIT_CLEAR_MID_31TO0_8821C(x) | BIT_MID_31TO0_8821C(v))
+
+/* 2 REG_SPWR1_8821C */
+
+#define BIT_SHIFT_MID_63TO32_8821C 0
+#define BIT_MASK_MID_63TO32_8821C 0xffffffffL
+#define BIT_MID_63TO32_8821C(x)                                                \
+	(((x) & BIT_MASK_MID_63TO32_8821C) << BIT_SHIFT_MID_63TO32_8821C)
+#define BITS_MID_63TO32_8821C                                                  \
+	(BIT_MASK_MID_63TO32_8821C << BIT_SHIFT_MID_63TO32_8821C)
+#define BIT_CLEAR_MID_63TO32_8821C(x) ((x) & (~BITS_MID_63TO32_8821C))
+#define BIT_GET_MID_63TO32_8821C(x)                                            \
+	(((x) >> BIT_SHIFT_MID_63TO32_8821C) & BIT_MASK_MID_63TO32_8821C)
+#define BIT_SET_MID_63TO32_8821C(x, v)                                         \
+	(BIT_CLEAR_MID_63TO32_8821C(x) | BIT_MID_63TO32_8821C(v))
+
+/* 2 REG_SPWR2_8821C */
+
+#define BIT_SHIFT_MID_95O64_8821C 0
+#define BIT_MASK_MID_95O64_8821C 0xffffffffL
+#define BIT_MID_95O64_8821C(x)                                                 \
+	(((x) & BIT_MASK_MID_95O64_8821C) << BIT_SHIFT_MID_95O64_8821C)
+#define BITS_MID_95O64_8821C                                                   \
+	(BIT_MASK_MID_95O64_8821C << BIT_SHIFT_MID_95O64_8821C)
+#define BIT_CLEAR_MID_95O64_8821C(x) ((x) & (~BITS_MID_95O64_8821C))
+#define BIT_GET_MID_95O64_8821C(x)                                             \
+	(((x) >> BIT_SHIFT_MID_95O64_8821C) & BIT_MASK_MID_95O64_8821C)
+#define BIT_SET_MID_95O64_8821C(x, v)                                          \
+	(BIT_CLEAR_MID_95O64_8821C(x) | BIT_MID_95O64_8821C(v))
+
+/* 2 REG_SPWR3_8821C */
+
+#define BIT_SHIFT_MID_127TO96_8821C 0
+#define BIT_MASK_MID_127TO96_8821C 0xffffffffL
+#define BIT_MID_127TO96_8821C(x)                                               \
+	(((x) & BIT_MASK_MID_127TO96_8821C) << BIT_SHIFT_MID_127TO96_8821C)
+#define BITS_MID_127TO96_8821C                                                 \
+	(BIT_MASK_MID_127TO96_8821C << BIT_SHIFT_MID_127TO96_8821C)
+#define BIT_CLEAR_MID_127TO96_8821C(x) ((x) & (~BITS_MID_127TO96_8821C))
+#define BIT_GET_MID_127TO96_8821C(x)                                           \
+	(((x) >> BIT_SHIFT_MID_127TO96_8821C) & BIT_MASK_MID_127TO96_8821C)
+#define BIT_SET_MID_127TO96_8821C(x, v)                                        \
+	(BIT_CLEAR_MID_127TO96_8821C(x) | BIT_MID_127TO96_8821C(v))
+
+/* 2 REG_POWSEQ_8821C */
+
+#define BIT_SHIFT_SEQNUM_MID_8821C 16
+#define BIT_MASK_SEQNUM_MID_8821C 0xffff
+#define BIT_SEQNUM_MID_8821C(x)                                                \
+	(((x) & BIT_MASK_SEQNUM_MID_8821C) << BIT_SHIFT_SEQNUM_MID_8821C)
+#define BITS_SEQNUM_MID_8821C                                                  \
+	(BIT_MASK_SEQNUM_MID_8821C << BIT_SHIFT_SEQNUM_MID_8821C)
+#define BIT_CLEAR_SEQNUM_MID_8821C(x) ((x) & (~BITS_SEQNUM_MID_8821C))
+#define BIT_GET_SEQNUM_MID_8821C(x)                                            \
+	(((x) >> BIT_SHIFT_SEQNUM_MID_8821C) & BIT_MASK_SEQNUM_MID_8821C)
+#define BIT_SET_SEQNUM_MID_8821C(x, v)                                         \
+	(BIT_CLEAR_SEQNUM_MID_8821C(x) | BIT_SEQNUM_MID_8821C(v))
+
+#define BIT_SHIFT_REF_MID_8821C 0
+#define BIT_MASK_REF_MID_8821C 0x7f
+#define BIT_REF_MID_8821C(x)                                                   \
+	(((x) & BIT_MASK_REF_MID_8821C) << BIT_SHIFT_REF_MID_8821C)
+#define BITS_REF_MID_8821C (BIT_MASK_REF_MID_8821C << BIT_SHIFT_REF_MID_8821C)
+#define BIT_CLEAR_REF_MID_8821C(x) ((x) & (~BITS_REF_MID_8821C))
+#define BIT_GET_REF_MID_8821C(x)                                               \
+	(((x) >> BIT_SHIFT_REF_MID_8821C) & BIT_MASK_REF_MID_8821C)
+#define BIT_SET_REF_MID_8821C(x, v)                                            \
+	(BIT_CLEAR_REF_MID_8821C(x) | BIT_REF_MID_8821C(v))
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_TC7_CTRL_V1_8821C */
+#define BIT_TC7INT_EN_8821C BIT(26)
+#define BIT_TC7MODE_8821C BIT(25)
+#define BIT_TC7EN_8821C BIT(24)
+
+#define BIT_SHIFT_TC7DATA_8821C 0
+#define BIT_MASK_TC7DATA_8821C 0xffffff
+#define BIT_TC7DATA_8821C(x)                                                   \
+	(((x) & BIT_MASK_TC7DATA_8821C) << BIT_SHIFT_TC7DATA_8821C)
+#define BITS_TC7DATA_8821C (BIT_MASK_TC7DATA_8821C << BIT_SHIFT_TC7DATA_8821C)
+#define BIT_CLEAR_TC7DATA_8821C(x) ((x) & (~BITS_TC7DATA_8821C))
+#define BIT_GET_TC7DATA_8821C(x)                                               \
+	(((x) >> BIT_SHIFT_TC7DATA_8821C) & BIT_MASK_TC7DATA_8821C)
+#define BIT_SET_TC7DATA_8821C(x, v)                                            \
+	(BIT_CLEAR_TC7DATA_8821C(x) | BIT_TC7DATA_8821C(v))
+
+/* 2 REG_TC8_CTRL_V1_8821C */
+#define BIT_TC8INT_EN_8821C BIT(26)
+#define BIT_TC8MODE_8821C BIT(25)
+#define BIT_TC8EN_8821C BIT(24)
+
+#define BIT_SHIFT_TC8DATA_8821C 0
+#define BIT_MASK_TC8DATA_8821C 0xffffff
+#define BIT_TC8DATA_8821C(x)                                                   \
+	(((x) & BIT_MASK_TC8DATA_8821C) << BIT_SHIFT_TC8DATA_8821C)
+#define BITS_TC8DATA_8821C (BIT_MASK_TC8DATA_8821C << BIT_SHIFT_TC8DATA_8821C)
+#define BIT_CLEAR_TC8DATA_8821C(x) ((x) & (~BITS_TC8DATA_8821C))
+#define BIT_GET_TC8DATA_8821C(x)                                               \
+	(((x) >> BIT_SHIFT_TC8DATA_8821C) & BIT_MASK_TC8DATA_8821C)
+#define BIT_SET_TC8DATA_8821C(x, v)                                            \
+	(BIT_CLEAR_TC8DATA_8821C(x) | BIT_TC8DATA_8821C(v))
+
+/* 2 REG_RX_BCN_TBTT_ITVL0_8821C */
+
+#define BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT2_8821C 24
+#define BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT2_8821C 0xff
+#define BIT_RX_BCN_TBTT_ITVL_CLIENT2_8821C(x)                                  \
+	(((x) & BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT2_8821C)                       \
+	 << BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT2_8821C)
+#define BITS_RX_BCN_TBTT_ITVL_CLIENT2_8821C                                    \
+	(BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT2_8821C                               \
+	 << BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT2_8821C)
+#define BIT_CLEAR_RX_BCN_TBTT_ITVL_CLIENT2_8821C(x)                            \
+	((x) & (~BITS_RX_BCN_TBTT_ITVL_CLIENT2_8821C))
+#define BIT_GET_RX_BCN_TBTT_ITVL_CLIENT2_8821C(x)                              \
+	(((x) >> BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT2_8821C) &                   \
+	 BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT2_8821C)
+#define BIT_SET_RX_BCN_TBTT_ITVL_CLIENT2_8821C(x, v)                           \
+	(BIT_CLEAR_RX_BCN_TBTT_ITVL_CLIENT2_8821C(x) |                         \
+	 BIT_RX_BCN_TBTT_ITVL_CLIENT2_8821C(v))
+
+#define BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT1_8821C 16
+#define BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT1_8821C 0xff
+#define BIT_RX_BCN_TBTT_ITVL_CLIENT1_8821C(x)                                  \
+	(((x) & BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT1_8821C)                       \
+	 << BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT1_8821C)
+#define BITS_RX_BCN_TBTT_ITVL_CLIENT1_8821C                                    \
+	(BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT1_8821C                               \
+	 << BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT1_8821C)
+#define BIT_CLEAR_RX_BCN_TBTT_ITVL_CLIENT1_8821C(x)                            \
+	((x) & (~BITS_RX_BCN_TBTT_ITVL_CLIENT1_8821C))
+#define BIT_GET_RX_BCN_TBTT_ITVL_CLIENT1_8821C(x)                              \
+	(((x) >> BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT1_8821C) &                   \
+	 BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT1_8821C)
+#define BIT_SET_RX_BCN_TBTT_ITVL_CLIENT1_8821C(x, v)                           \
+	(BIT_CLEAR_RX_BCN_TBTT_ITVL_CLIENT1_8821C(x) |                         \
+	 BIT_RX_BCN_TBTT_ITVL_CLIENT1_8821C(v))
+
+#define BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT0_8821C 8
+#define BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT0_8821C 0xff
+#define BIT_RX_BCN_TBTT_ITVL_CLIENT0_8821C(x)                                  \
+	(((x) & BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT0_8821C)                       \
+	 << BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT0_8821C)
+#define BITS_RX_BCN_TBTT_ITVL_CLIENT0_8821C                                    \
+	(BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT0_8821C                               \
+	 << BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT0_8821C)
+#define BIT_CLEAR_RX_BCN_TBTT_ITVL_CLIENT0_8821C(x)                            \
+	((x) & (~BITS_RX_BCN_TBTT_ITVL_CLIENT0_8821C))
+#define BIT_GET_RX_BCN_TBTT_ITVL_CLIENT0_8821C(x)                              \
+	(((x) >> BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT0_8821C) &                   \
+	 BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT0_8821C)
+#define BIT_SET_RX_BCN_TBTT_ITVL_CLIENT0_8821C(x, v)                           \
+	(BIT_CLEAR_RX_BCN_TBTT_ITVL_CLIENT0_8821C(x) |                         \
+	 BIT_RX_BCN_TBTT_ITVL_CLIENT0_8821C(v))
+
+#define BIT_SHIFT_RX_BCN_TBTT_ITVL_PORT0_8821C 0
+#define BIT_MASK_RX_BCN_TBTT_ITVL_PORT0_8821C 0xff
+#define BIT_RX_BCN_TBTT_ITVL_PORT0_8821C(x)                                    \
+	(((x) & BIT_MASK_RX_BCN_TBTT_ITVL_PORT0_8821C)                         \
+	 << BIT_SHIFT_RX_BCN_TBTT_ITVL_PORT0_8821C)
+#define BITS_RX_BCN_TBTT_ITVL_PORT0_8821C                                      \
+	(BIT_MASK_RX_BCN_TBTT_ITVL_PORT0_8821C                                 \
+	 << BIT_SHIFT_RX_BCN_TBTT_ITVL_PORT0_8821C)
+#define BIT_CLEAR_RX_BCN_TBTT_ITVL_PORT0_8821C(x)                              \
+	((x) & (~BITS_RX_BCN_TBTT_ITVL_PORT0_8821C))
+#define BIT_GET_RX_BCN_TBTT_ITVL_PORT0_8821C(x)                                \
+	(((x) >> BIT_SHIFT_RX_BCN_TBTT_ITVL_PORT0_8821C) &                     \
+	 BIT_MASK_RX_BCN_TBTT_ITVL_PORT0_8821C)
+#define BIT_SET_RX_BCN_TBTT_ITVL_PORT0_8821C(x, v)                             \
+	(BIT_CLEAR_RX_BCN_TBTT_ITVL_PORT0_8821C(x) |                           \
+	 BIT_RX_BCN_TBTT_ITVL_PORT0_8821C(v))
+
+/* 2 REG_RX_BCN_TBTT_ITVL1_8821C */
+
+#define BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT3_8821C 0
+#define BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT3_8821C 0xff
+#define BIT_RX_BCN_TBTT_ITVL_CLIENT3_8821C(x)                                  \
+	(((x) & BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT3_8821C)                       \
+	 << BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT3_8821C)
+#define BITS_RX_BCN_TBTT_ITVL_CLIENT3_8821C                                    \
+	(BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT3_8821C                               \
+	 << BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT3_8821C)
+#define BIT_CLEAR_RX_BCN_TBTT_ITVL_CLIENT3_8821C(x)                            \
+	((x) & (~BITS_RX_BCN_TBTT_ITVL_CLIENT3_8821C))
+#define BIT_GET_RX_BCN_TBTT_ITVL_CLIENT3_8821C(x)                              \
+	(((x) >> BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT3_8821C) &                   \
+	 BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT3_8821C)
+#define BIT_SET_RX_BCN_TBTT_ITVL_CLIENT3_8821C(x, v)                           \
+	(BIT_CLEAR_RX_BCN_TBTT_ITVL_CLIENT3_8821C(x) |                         \
+	 BIT_RX_BCN_TBTT_ITVL_CLIENT3_8821C(v))
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_IO_WRAP_ERR_FLAG_8821C */
+#define BIT_IO_WRAP_ERR_8821C BIT(0)
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_SPEED_SENSOR_8821C */
+#define BIT_DSS_1_RST_N_8821C BIT(31)
+#define BIT_DSS_1_SPEED_EN_8821C BIT(30)
+#define BIT_DSS_1_WIRE_SEL_8821C BIT(29)
+#define BIT_DSS_ENCLK_8821C BIT(28)
+
+#define BIT_SHIFT_DSS_1_RO_SEL_8821C 24
+#define BIT_MASK_DSS_1_RO_SEL_8821C 0x7
+#define BIT_DSS_1_RO_SEL_8821C(x)                                              \
+	(((x) & BIT_MASK_DSS_1_RO_SEL_8821C) << BIT_SHIFT_DSS_1_RO_SEL_8821C)
+#define BITS_DSS_1_RO_SEL_8821C                                                \
+	(BIT_MASK_DSS_1_RO_SEL_8821C << BIT_SHIFT_DSS_1_RO_SEL_8821C)
+#define BIT_CLEAR_DSS_1_RO_SEL_8821C(x) ((x) & (~BITS_DSS_1_RO_SEL_8821C))
+#define BIT_GET_DSS_1_RO_SEL_8821C(x)                                          \
+	(((x) >> BIT_SHIFT_DSS_1_RO_SEL_8821C) & BIT_MASK_DSS_1_RO_SEL_8821C)
+#define BIT_SET_DSS_1_RO_SEL_8821C(x, v)                                       \
+	(BIT_CLEAR_DSS_1_RO_SEL_8821C(x) | BIT_DSS_1_RO_SEL_8821C(v))
+
+#define BIT_SHIFT_DSS_1_DATA_IN_8821C 0
+#define BIT_MASK_DSS_1_DATA_IN_8821C 0xfffff
+#define BIT_DSS_1_DATA_IN_8821C(x)                                             \
+	(((x) & BIT_MASK_DSS_1_DATA_IN_8821C) << BIT_SHIFT_DSS_1_DATA_IN_8821C)
+#define BITS_DSS_1_DATA_IN_8821C                                               \
+	(BIT_MASK_DSS_1_DATA_IN_8821C << BIT_SHIFT_DSS_1_DATA_IN_8821C)
+#define BIT_CLEAR_DSS_1_DATA_IN_8821C(x) ((x) & (~BITS_DSS_1_DATA_IN_8821C))
+#define BIT_GET_DSS_1_DATA_IN_8821C(x)                                         \
+	(((x) >> BIT_SHIFT_DSS_1_DATA_IN_8821C) & BIT_MASK_DSS_1_DATA_IN_8821C)
+#define BIT_SET_DSS_1_DATA_IN_8821C(x, v)                                      \
+	(BIT_CLEAR_DSS_1_DATA_IN_8821C(x) | BIT_DSS_1_DATA_IN_8821C(v))
+
+/* 2 REG_SPEED_SENSOR1_8821C */
+#define BIT_DSS_1_READY_8821C BIT(31)
+#define BIT_DSS_1_WSORT_GO_8821C BIT(30)
+
+#define BIT_SHIFT_DSS_1_COUNT_OUT_8821C 0
+#define BIT_MASK_DSS_1_COUNT_OUT_8821C 0xfffff
+#define BIT_DSS_1_COUNT_OUT_8821C(x)                                           \
+	(((x) & BIT_MASK_DSS_1_COUNT_OUT_8821C)                                \
+	 << BIT_SHIFT_DSS_1_COUNT_OUT_8821C)
+#define BITS_DSS_1_COUNT_OUT_8821C                                             \
+	(BIT_MASK_DSS_1_COUNT_OUT_8821C << BIT_SHIFT_DSS_1_COUNT_OUT_8821C)
+#define BIT_CLEAR_DSS_1_COUNT_OUT_8821C(x) ((x) & (~BITS_DSS_1_COUNT_OUT_8821C))
+#define BIT_GET_DSS_1_COUNT_OUT_8821C(x)                                       \
+	(((x) >> BIT_SHIFT_DSS_1_COUNT_OUT_8821C) &                            \
+	 BIT_MASK_DSS_1_COUNT_OUT_8821C)
+#define BIT_SET_DSS_1_COUNT_OUT_8821C(x, v)                                    \
+	(BIT_CLEAR_DSS_1_COUNT_OUT_8821C(x) | BIT_DSS_1_COUNT_OUT_8821C(v))
+
+/* 2 REG_SPEED_SENSOR2_8821C */
+#define BIT_DSS_2_RST_N_8821C BIT(31)
+#define BIT_DSS_2_SPEED_EN_8821C BIT(30)
+#define BIT_DSS_2_WIRE_SEL_8821C BIT(29)
+#define BIT_DSS_ENCLK_8821C BIT(28)
+
+#define BIT_SHIFT_DSS_2_RO_SEL_8821C 24
+#define BIT_MASK_DSS_2_RO_SEL_8821C 0x7
+#define BIT_DSS_2_RO_SEL_8821C(x)                                              \
+	(((x) & BIT_MASK_DSS_2_RO_SEL_8821C) << BIT_SHIFT_DSS_2_RO_SEL_8821C)
+#define BITS_DSS_2_RO_SEL_8821C                                                \
+	(BIT_MASK_DSS_2_RO_SEL_8821C << BIT_SHIFT_DSS_2_RO_SEL_8821C)
+#define BIT_CLEAR_DSS_2_RO_SEL_8821C(x) ((x) & (~BITS_DSS_2_RO_SEL_8821C))
+#define BIT_GET_DSS_2_RO_SEL_8821C(x)                                          \
+	(((x) >> BIT_SHIFT_DSS_2_RO_SEL_8821C) & BIT_MASK_DSS_2_RO_SEL_8821C)
+#define BIT_SET_DSS_2_RO_SEL_8821C(x, v)                                       \
+	(BIT_CLEAR_DSS_2_RO_SEL_8821C(x) | BIT_DSS_2_RO_SEL_8821C(v))
+
+#define BIT_SHIFT_DSS_2_DATA_IN_8821C 0
+#define BIT_MASK_DSS_2_DATA_IN_8821C 0xfffff
+#define BIT_DSS_2_DATA_IN_8821C(x)                                             \
+	(((x) & BIT_MASK_DSS_2_DATA_IN_8821C) << BIT_SHIFT_DSS_2_DATA_IN_8821C)
+#define BITS_DSS_2_DATA_IN_8821C                                               \
+	(BIT_MASK_DSS_2_DATA_IN_8821C << BIT_SHIFT_DSS_2_DATA_IN_8821C)
+#define BIT_CLEAR_DSS_2_DATA_IN_8821C(x) ((x) & (~BITS_DSS_2_DATA_IN_8821C))
+#define BIT_GET_DSS_2_DATA_IN_8821C(x)                                         \
+	(((x) >> BIT_SHIFT_DSS_2_DATA_IN_8821C) & BIT_MASK_DSS_2_DATA_IN_8821C)
+#define BIT_SET_DSS_2_DATA_IN_8821C(x, v)                                      \
+	(BIT_CLEAR_DSS_2_DATA_IN_8821C(x) | BIT_DSS_2_DATA_IN_8821C(v))
+
+/* 2 REG_SPEED_SENSOR3_8821C */
+#define BIT_DSS_2_READY_8821C BIT(31)
+#define BIT_DSS_2_WSORT_GO_8821C BIT(30)
+
+#define BIT_SHIFT_DSS_2_COUNT_OUT_8821C 0
+#define BIT_MASK_DSS_2_COUNT_OUT_8821C 0xfffff
+#define BIT_DSS_2_COUNT_OUT_8821C(x)                                           \
+	(((x) & BIT_MASK_DSS_2_COUNT_OUT_8821C)                                \
+	 << BIT_SHIFT_DSS_2_COUNT_OUT_8821C)
+#define BITS_DSS_2_COUNT_OUT_8821C                                             \
+	(BIT_MASK_DSS_2_COUNT_OUT_8821C << BIT_SHIFT_DSS_2_COUNT_OUT_8821C)
+#define BIT_CLEAR_DSS_2_COUNT_OUT_8821C(x) ((x) & (~BITS_DSS_2_COUNT_OUT_8821C))
+#define BIT_GET_DSS_2_COUNT_OUT_8821C(x)                                       \
+	(((x) >> BIT_SHIFT_DSS_2_COUNT_OUT_8821C) &                            \
+	 BIT_MASK_DSS_2_COUNT_OUT_8821C)
+#define BIT_SET_DSS_2_COUNT_OUT_8821C(x, v)                                    \
+	(BIT_CLEAR_DSS_2_COUNT_OUT_8821C(x) | BIT_DSS_2_COUNT_OUT_8821C(v))
+
+/* 2 REG_SPEED_SENSOR4_8821C */
+#define BIT_DSS_3_RST_N_8821C BIT(31)
+#define BIT_DSS_3_SPEED_EN_8821C BIT(30)
+#define BIT_DSS_3_WIRE_SEL_8821C BIT(29)
+#define BIT_DSS_ENCLK_8821C BIT(28)
+
+#define BIT_SHIFT_DSS_3_RO_SEL_8821C 24
+#define BIT_MASK_DSS_3_RO_SEL_8821C 0x7
+#define BIT_DSS_3_RO_SEL_8821C(x)                                              \
+	(((x) & BIT_MASK_DSS_3_RO_SEL_8821C) << BIT_SHIFT_DSS_3_RO_SEL_8821C)
+#define BITS_DSS_3_RO_SEL_8821C                                                \
+	(BIT_MASK_DSS_3_RO_SEL_8821C << BIT_SHIFT_DSS_3_RO_SEL_8821C)
+#define BIT_CLEAR_DSS_3_RO_SEL_8821C(x) ((x) & (~BITS_DSS_3_RO_SEL_8821C))
+#define BIT_GET_DSS_3_RO_SEL_8821C(x)                                          \
+	(((x) >> BIT_SHIFT_DSS_3_RO_SEL_8821C) & BIT_MASK_DSS_3_RO_SEL_8821C)
+#define BIT_SET_DSS_3_RO_SEL_8821C(x, v)                                       \
+	(BIT_CLEAR_DSS_3_RO_SEL_8821C(x) | BIT_DSS_3_RO_SEL_8821C(v))
+
+#define BIT_SHIFT_DSS_3_DATA_IN_8821C 0
+#define BIT_MASK_DSS_3_DATA_IN_8821C 0xfffff
+#define BIT_DSS_3_DATA_IN_8821C(x)                                             \
+	(((x) & BIT_MASK_DSS_3_DATA_IN_8821C) << BIT_SHIFT_DSS_3_DATA_IN_8821C)
+#define BITS_DSS_3_DATA_IN_8821C                                               \
+	(BIT_MASK_DSS_3_DATA_IN_8821C << BIT_SHIFT_DSS_3_DATA_IN_8821C)
+#define BIT_CLEAR_DSS_3_DATA_IN_8821C(x) ((x) & (~BITS_DSS_3_DATA_IN_8821C))
+#define BIT_GET_DSS_3_DATA_IN_8821C(x)                                         \
+	(((x) >> BIT_SHIFT_DSS_3_DATA_IN_8821C) & BIT_MASK_DSS_3_DATA_IN_8821C)
+#define BIT_SET_DSS_3_DATA_IN_8821C(x, v)                                      \
+	(BIT_CLEAR_DSS_3_DATA_IN_8821C(x) | BIT_DSS_3_DATA_IN_8821C(v))
+
+/* 2 REG_SPEED_SENSOR5_8821C */
+#define BIT_DSS_3_READY_8821C BIT(31)
+#define BIT_DSS_3_WSORT_GO_8821C BIT(30)
+
+#define BIT_SHIFT_DSS_3_COUNT_OUT_8821C 0
+#define BIT_MASK_DSS_3_COUNT_OUT_8821C 0xfffff
+#define BIT_DSS_3_COUNT_OUT_8821C(x)                                           \
+	(((x) & BIT_MASK_DSS_3_COUNT_OUT_8821C)                                \
+	 << BIT_SHIFT_DSS_3_COUNT_OUT_8821C)
+#define BITS_DSS_3_COUNT_OUT_8821C                                             \
+	(BIT_MASK_DSS_3_COUNT_OUT_8821C << BIT_SHIFT_DSS_3_COUNT_OUT_8821C)
+#define BIT_CLEAR_DSS_3_COUNT_OUT_8821C(x) ((x) & (~BITS_DSS_3_COUNT_OUT_8821C))
+#define BIT_GET_DSS_3_COUNT_OUT_8821C(x)                                       \
+	(((x) >> BIT_SHIFT_DSS_3_COUNT_OUT_8821C) &                            \
+	 BIT_MASK_DSS_3_COUNT_OUT_8821C)
+#define BIT_SET_DSS_3_COUNT_OUT_8821C(x, v)                                    \
+	(BIT_CLEAR_DSS_3_COUNT_OUT_8821C(x) | BIT_DSS_3_COUNT_OUT_8821C(v))
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_COUNTER_CTRL_8821C */
+
+#define BIT_SHIFT_COUNTER_BASE_8821C 16
+#define BIT_MASK_COUNTER_BASE_8821C 0x1fff
+#define BIT_COUNTER_BASE_8821C(x)                                              \
+	(((x) & BIT_MASK_COUNTER_BASE_8821C) << BIT_SHIFT_COUNTER_BASE_8821C)
+#define BITS_COUNTER_BASE_8821C                                                \
+	(BIT_MASK_COUNTER_BASE_8821C << BIT_SHIFT_COUNTER_BASE_8821C)
+#define BIT_CLEAR_COUNTER_BASE_8821C(x) ((x) & (~BITS_COUNTER_BASE_8821C))
+#define BIT_GET_COUNTER_BASE_8821C(x)                                          \
+	(((x) >> BIT_SHIFT_COUNTER_BASE_8821C) & BIT_MASK_COUNTER_BASE_8821C)
+#define BIT_SET_COUNTER_BASE_8821C(x, v)                                       \
+	(BIT_CLEAR_COUNTER_BASE_8821C(x) | BIT_COUNTER_BASE_8821C(v))
+
+#define BIT_EN_RTS_REQ_8821C BIT(9)
+#define BIT_EN_EDCA_REQ_8821C BIT(8)
+#define BIT_EN_PTCL_REQ_8821C BIT(7)
+#define BIT_EN_SCH_REQ_8821C BIT(6)
+#define BIT_USB_COUNT_EN_8821C BIT(5)
+#define BIT_PCIE_COUNT_EN_8821C BIT(4)
+#define BIT_RQPN_COUNT_EN_8821C BIT(3)
+#define BIT_RDE_COUNT_EN_8821C BIT(2)
+#define BIT_TDE_COUNT_EN_8821C BIT(1)
+#define BIT_DISABLE_COUNTER_8821C BIT(0)
+
+/* 2 REG_COUNTER_THRESHOLD_8821C */
+#define BIT_SEL_ALL_MACID_8821C BIT(31)
+
+#define BIT_SHIFT_COUNTER_MACID_8821C 24
+#define BIT_MASK_COUNTER_MACID_8821C 0x7f
+#define BIT_COUNTER_MACID_8821C(x)                                             \
+	(((x) & BIT_MASK_COUNTER_MACID_8821C) << BIT_SHIFT_COUNTER_MACID_8821C)
+#define BITS_COUNTER_MACID_8821C                                               \
+	(BIT_MASK_COUNTER_MACID_8821C << BIT_SHIFT_COUNTER_MACID_8821C)
+#define BIT_CLEAR_COUNTER_MACID_8821C(x) ((x) & (~BITS_COUNTER_MACID_8821C))
+#define BIT_GET_COUNTER_MACID_8821C(x)                                         \
+	(((x) >> BIT_SHIFT_COUNTER_MACID_8821C) & BIT_MASK_COUNTER_MACID_8821C)
+#define BIT_SET_COUNTER_MACID_8821C(x, v)                                      \
+	(BIT_CLEAR_COUNTER_MACID_8821C(x) | BIT_COUNTER_MACID_8821C(v))
+
+#define BIT_SHIFT_AGG_VALUE2_8821C 16
+#define BIT_MASK_AGG_VALUE2_8821C 0x7f
+#define BIT_AGG_VALUE2_8821C(x)                                                \
+	(((x) & BIT_MASK_AGG_VALUE2_8821C) << BIT_SHIFT_AGG_VALUE2_8821C)
+#define BITS_AGG_VALUE2_8821C                                                  \
+	(BIT_MASK_AGG_VALUE2_8821C << BIT_SHIFT_AGG_VALUE2_8821C)
+#define BIT_CLEAR_AGG_VALUE2_8821C(x) ((x) & (~BITS_AGG_VALUE2_8821C))
+#define BIT_GET_AGG_VALUE2_8821C(x)                                            \
+	(((x) >> BIT_SHIFT_AGG_VALUE2_8821C) & BIT_MASK_AGG_VALUE2_8821C)
+#define BIT_SET_AGG_VALUE2_8821C(x, v)                                         \
+	(BIT_CLEAR_AGG_VALUE2_8821C(x) | BIT_AGG_VALUE2_8821C(v))
+
+#define BIT_SHIFT_AGG_VALUE1_8821C 8
+#define BIT_MASK_AGG_VALUE1_8821C 0x7f
+#define BIT_AGG_VALUE1_8821C(x)                                                \
+	(((x) & BIT_MASK_AGG_VALUE1_8821C) << BIT_SHIFT_AGG_VALUE1_8821C)
+#define BITS_AGG_VALUE1_8821C                                                  \
+	(BIT_MASK_AGG_VALUE1_8821C << BIT_SHIFT_AGG_VALUE1_8821C)
+#define BIT_CLEAR_AGG_VALUE1_8821C(x) ((x) & (~BITS_AGG_VALUE1_8821C))
+#define BIT_GET_AGG_VALUE1_8821C(x)                                            \
+	(((x) >> BIT_SHIFT_AGG_VALUE1_8821C) & BIT_MASK_AGG_VALUE1_8821C)
+#define BIT_SET_AGG_VALUE1_8821C(x, v)                                         \
+	(BIT_CLEAR_AGG_VALUE1_8821C(x) | BIT_AGG_VALUE1_8821C(v))
+
+#define BIT_SHIFT_AGG_VALUE0_8821C 0
+#define BIT_MASK_AGG_VALUE0_8821C 0x7f
+#define BIT_AGG_VALUE0_8821C(x)                                                \
+	(((x) & BIT_MASK_AGG_VALUE0_8821C) << BIT_SHIFT_AGG_VALUE0_8821C)
+#define BITS_AGG_VALUE0_8821C                                                  \
+	(BIT_MASK_AGG_VALUE0_8821C << BIT_SHIFT_AGG_VALUE0_8821C)
+#define BIT_CLEAR_AGG_VALUE0_8821C(x) ((x) & (~BITS_AGG_VALUE0_8821C))
+#define BIT_GET_AGG_VALUE0_8821C(x)                                            \
+	(((x) >> BIT_SHIFT_AGG_VALUE0_8821C) & BIT_MASK_AGG_VALUE0_8821C)
+#define BIT_SET_AGG_VALUE0_8821C(x, v)                                         \
+	(BIT_CLEAR_AGG_VALUE0_8821C(x) | BIT_AGG_VALUE0_8821C(v))
+
+/* 2 REG_COUNTER_SET_8821C */
+
+#define BIT_SHIFT_REQUEST_RESET_8821C 16
+#define BIT_MASK_REQUEST_RESET_8821C 0xffff
+#define BIT_REQUEST_RESET_8821C(x)                                             \
+	(((x) & BIT_MASK_REQUEST_RESET_8821C) << BIT_SHIFT_REQUEST_RESET_8821C)
+#define BITS_REQUEST_RESET_8821C                                               \
+	(BIT_MASK_REQUEST_RESET_8821C << BIT_SHIFT_REQUEST_RESET_8821C)
+#define BIT_CLEAR_REQUEST_RESET_8821C(x) ((x) & (~BITS_REQUEST_RESET_8821C))
+#define BIT_GET_REQUEST_RESET_8821C(x)                                         \
+	(((x) >> BIT_SHIFT_REQUEST_RESET_8821C) & BIT_MASK_REQUEST_RESET_8821C)
+#define BIT_SET_REQUEST_RESET_8821C(x, v)                                      \
+	(BIT_CLEAR_REQUEST_RESET_8821C(x) | BIT_REQUEST_RESET_8821C(v))
+
+#define BIT_SHIFT_REQUEST_START_8821C 0
+#define BIT_MASK_REQUEST_START_8821C 0xffff
+#define BIT_REQUEST_START_8821C(x)                                             \
+	(((x) & BIT_MASK_REQUEST_START_8821C) << BIT_SHIFT_REQUEST_START_8821C)
+#define BITS_REQUEST_START_8821C                                               \
+	(BIT_MASK_REQUEST_START_8821C << BIT_SHIFT_REQUEST_START_8821C)
+#define BIT_CLEAR_REQUEST_START_8821C(x) ((x) & (~BITS_REQUEST_START_8821C))
+#define BIT_GET_REQUEST_START_8821C(x)                                         \
+	(((x) >> BIT_SHIFT_REQUEST_START_8821C) & BIT_MASK_REQUEST_START_8821C)
+#define BIT_SET_REQUEST_START_8821C(x, v)                                      \
+	(BIT_CLEAR_REQUEST_START_8821C(x) | BIT_REQUEST_START_8821C(v))
+
+/* 2 REG_COUNTER_OVERFLOW_8821C */
+
+#define BIT_SHIFT_CNT_OVF_REG_8821C 0
+#define BIT_MASK_CNT_OVF_REG_8821C 0xffff
+#define BIT_CNT_OVF_REG_8821C(x)                                               \
+	(((x) & BIT_MASK_CNT_OVF_REG_8821C) << BIT_SHIFT_CNT_OVF_REG_8821C)
+#define BITS_CNT_OVF_REG_8821C                                                 \
+	(BIT_MASK_CNT_OVF_REG_8821C << BIT_SHIFT_CNT_OVF_REG_8821C)
+#define BIT_CLEAR_CNT_OVF_REG_8821C(x) ((x) & (~BITS_CNT_OVF_REG_8821C))
+#define BIT_GET_CNT_OVF_REG_8821C(x)                                           \
+	(((x) >> BIT_SHIFT_CNT_OVF_REG_8821C) & BIT_MASK_CNT_OVF_REG_8821C)
+#define BIT_SET_CNT_OVF_REG_8821C(x, v)                                        \
+	(BIT_CLEAR_CNT_OVF_REG_8821C(x) | BIT_CNT_OVF_REG_8821C(v))
+
+/* 2 REG_TXDMA_LEN_THRESHOLD_8821C */
+
+#define BIT_SHIFT_TDE_LEN_TH1_8821C 16
+#define BIT_MASK_TDE_LEN_TH1_8821C 0xffff
+#define BIT_TDE_LEN_TH1_8821C(x)                                               \
+	(((x) & BIT_MASK_TDE_LEN_TH1_8821C) << BIT_SHIFT_TDE_LEN_TH1_8821C)
+#define BITS_TDE_LEN_TH1_8821C                                                 \
+	(BIT_MASK_TDE_LEN_TH1_8821C << BIT_SHIFT_TDE_LEN_TH1_8821C)
+#define BIT_CLEAR_TDE_LEN_TH1_8821C(x) ((x) & (~BITS_TDE_LEN_TH1_8821C))
+#define BIT_GET_TDE_LEN_TH1_8821C(x)                                           \
+	(((x) >> BIT_SHIFT_TDE_LEN_TH1_8821C) & BIT_MASK_TDE_LEN_TH1_8821C)
+#define BIT_SET_TDE_LEN_TH1_8821C(x, v)                                        \
+	(BIT_CLEAR_TDE_LEN_TH1_8821C(x) | BIT_TDE_LEN_TH1_8821C(v))
+
+#define BIT_SHIFT_TDE_LEN_TH0_8821C 0
+#define BIT_MASK_TDE_LEN_TH0_8821C 0xffff
+#define BIT_TDE_LEN_TH0_8821C(x)                                               \
+	(((x) & BIT_MASK_TDE_LEN_TH0_8821C) << BIT_SHIFT_TDE_LEN_TH0_8821C)
+#define BITS_TDE_LEN_TH0_8821C                                                 \
+	(BIT_MASK_TDE_LEN_TH0_8821C << BIT_SHIFT_TDE_LEN_TH0_8821C)
+#define BIT_CLEAR_TDE_LEN_TH0_8821C(x) ((x) & (~BITS_TDE_LEN_TH0_8821C))
+#define BIT_GET_TDE_LEN_TH0_8821C(x)                                           \
+	(((x) >> BIT_SHIFT_TDE_LEN_TH0_8821C) & BIT_MASK_TDE_LEN_TH0_8821C)
+#define BIT_SET_TDE_LEN_TH0_8821C(x, v)                                        \
+	(BIT_CLEAR_TDE_LEN_TH0_8821C(x) | BIT_TDE_LEN_TH0_8821C(v))
+
+/* 2 REG_RXDMA_LEN_THRESHOLD_8821C */
+
+#define BIT_SHIFT_RDE_LEN_TH1_8821C 16
+#define BIT_MASK_RDE_LEN_TH1_8821C 0xffff
+#define BIT_RDE_LEN_TH1_8821C(x)                                               \
+	(((x) & BIT_MASK_RDE_LEN_TH1_8821C) << BIT_SHIFT_RDE_LEN_TH1_8821C)
+#define BITS_RDE_LEN_TH1_8821C                                                 \
+	(BIT_MASK_RDE_LEN_TH1_8821C << BIT_SHIFT_RDE_LEN_TH1_8821C)
+#define BIT_CLEAR_RDE_LEN_TH1_8821C(x) ((x) & (~BITS_RDE_LEN_TH1_8821C))
+#define BIT_GET_RDE_LEN_TH1_8821C(x)                                           \
+	(((x) >> BIT_SHIFT_RDE_LEN_TH1_8821C) & BIT_MASK_RDE_LEN_TH1_8821C)
+#define BIT_SET_RDE_LEN_TH1_8821C(x, v)                                        \
+	(BIT_CLEAR_RDE_LEN_TH1_8821C(x) | BIT_RDE_LEN_TH1_8821C(v))
+
+#define BIT_SHIFT_RDE_LEN_TH0_8821C 0
+#define BIT_MASK_RDE_LEN_TH0_8821C 0xffff
+#define BIT_RDE_LEN_TH0_8821C(x)                                               \
+	(((x) & BIT_MASK_RDE_LEN_TH0_8821C) << BIT_SHIFT_RDE_LEN_TH0_8821C)
+#define BITS_RDE_LEN_TH0_8821C                                                 \
+	(BIT_MASK_RDE_LEN_TH0_8821C << BIT_SHIFT_RDE_LEN_TH0_8821C)
+#define BIT_CLEAR_RDE_LEN_TH0_8821C(x) ((x) & (~BITS_RDE_LEN_TH0_8821C))
+#define BIT_GET_RDE_LEN_TH0_8821C(x)                                           \
+	(((x) >> BIT_SHIFT_RDE_LEN_TH0_8821C) & BIT_MASK_RDE_LEN_TH0_8821C)
+#define BIT_SET_RDE_LEN_TH0_8821C(x, v)                                        \
+	(BIT_CLEAR_RDE_LEN_TH0_8821C(x) | BIT_RDE_LEN_TH0_8821C(v))
+
+/* 2 REG_PCIE_EXEC_TIME_THRESHOLD_8821C */
+
+#define BIT_SHIFT_COUNT_INT_SEL_8821C 16
+#define BIT_MASK_COUNT_INT_SEL_8821C 0x3
+#define BIT_COUNT_INT_SEL_8821C(x)                                             \
+	(((x) & BIT_MASK_COUNT_INT_SEL_8821C) << BIT_SHIFT_COUNT_INT_SEL_8821C)
+#define BITS_COUNT_INT_SEL_8821C                                               \
+	(BIT_MASK_COUNT_INT_SEL_8821C << BIT_SHIFT_COUNT_INT_SEL_8821C)
+#define BIT_CLEAR_COUNT_INT_SEL_8821C(x) ((x) & (~BITS_COUNT_INT_SEL_8821C))
+#define BIT_GET_COUNT_INT_SEL_8821C(x)                                         \
+	(((x) >> BIT_SHIFT_COUNT_INT_SEL_8821C) & BIT_MASK_COUNT_INT_SEL_8821C)
+#define BIT_SET_COUNT_INT_SEL_8821C(x, v)                                      \
+	(BIT_CLEAR_COUNT_INT_SEL_8821C(x) | BIT_COUNT_INT_SEL_8821C(v))
+
+#define BIT_SHIFT_EXEC_TIME_TH_8821C 0
+#define BIT_MASK_EXEC_TIME_TH_8821C 0xffff
+#define BIT_EXEC_TIME_TH_8821C(x)                                              \
+	(((x) & BIT_MASK_EXEC_TIME_TH_8821C) << BIT_SHIFT_EXEC_TIME_TH_8821C)
+#define BITS_EXEC_TIME_TH_8821C                                                \
+	(BIT_MASK_EXEC_TIME_TH_8821C << BIT_SHIFT_EXEC_TIME_TH_8821C)
+#define BIT_CLEAR_EXEC_TIME_TH_8821C(x) ((x) & (~BITS_EXEC_TIME_TH_8821C))
+#define BIT_GET_EXEC_TIME_TH_8821C(x)                                          \
+	(((x) >> BIT_SHIFT_EXEC_TIME_TH_8821C) & BIT_MASK_EXEC_TIME_TH_8821C)
+#define BIT_SET_EXEC_TIME_TH_8821C(x, v)                                       \
+	(BIT_CLEAR_EXEC_TIME_TH_8821C(x) | BIT_EXEC_TIME_TH_8821C(v))
+
+/* 2 REG_FT2IMR_8821C */
+#define BIT_FS_CLI3_RX_UAPSDMD1_EN_8821C BIT(31)
+#define BIT_FS_CLI3_RX_UAPSDMD0_EN_8821C BIT(30)
+#define BIT_FS_CLI3_TRIGGER_PKT_EN_8821C BIT(29)
+#define BIT_FS_CLI3_EOSP_INT_EN_8821C BIT(28)
+#define BIT_FS_CLI2_RX_UAPSDMD1_EN_8821C BIT(27)
+#define BIT_FS_CLI2_RX_UAPSDMD0_EN_8821C BIT(26)
+#define BIT_FS_CLI2_TRIGGER_PKT_EN_8821C BIT(25)
+#define BIT_FS_CLI2_EOSP_INT_EN_8821C BIT(24)
+#define BIT_FS_CLI1_RX_UAPSDMD1_EN_8821C BIT(23)
+#define BIT_FS_CLI1_RX_UAPSDMD0_EN_8821C BIT(22)
+#define BIT_FS_CLI1_TRIGGER_PKT_EN_8821C BIT(21)
+#define BIT_FS_CLI1_EOSP_INT_EN_8821C BIT(20)
+#define BIT_FS_CLI0_RX_UAPSDMD1_EN_8821C BIT(19)
+#define BIT_FS_CLI0_RX_UAPSDMD0_EN_8821C BIT(18)
+#define BIT_FS_CLI0_TRIGGER_PKT_EN_8821C BIT(17)
+#define BIT_FS_CLI0_EOSP_INT_EN_8821C BIT(16)
+#define BIT_FS_TSF_BIT32_TOGGLE_P2P2_EN_8821C BIT(9)
+#define BIT_FS_TSF_BIT32_TOGGLE_P2P1_EN_8821C BIT(8)
+#define BIT_FS_CLI3_TX_NULL1_INT_EN_8821C BIT(7)
+#define BIT_FS_CLI3_TX_NULL0_INT_EN_8821C BIT(6)
+#define BIT_FS_CLI2_TX_NULL1_INT_EN_8821C BIT(5)
+#define BIT_FS_CLI2_TX_NULL0_INT_EN_8821C BIT(4)
+#define BIT_FS_CLI1_TX_NULL1_INT_EN_8821C BIT(3)
+#define BIT_FS_CLI1_TX_NULL0_INT_EN_8821C BIT(2)
+#define BIT_FS_CLI0_TX_NULL1_INT_EN_8821C BIT(1)
+#define BIT_FS_CLI0_TX_NULL0_INT_EN_8821C BIT(0)
+
+/* 2 REG_FT2ISR_8821C */
+#define BIT_FS_CLI3_RX_UAPSDMD1_INT_8821C BIT(31)
+#define BIT_FS_CLI3_RX_UAPSDMD0_INT_8821C BIT(30)
+#define BIT_FS_CLI3_TRIGGER_PKT_INT_8821C BIT(29)
+#define BIT_FS_CLI3_EOSP_INT_8821C BIT(28)
+#define BIT_FS_CLI2_RX_UAPSDMD1_INT_8821C BIT(27)
+#define BIT_FS_CLI2_RX_UAPSDMD0_INT_8821C BIT(26)
+#define BIT_FS_CLI2_TRIGGER_PKT_INT_8821C BIT(25)
+#define BIT_FS_CLI2_EOSP_INT_8821C BIT(24)
+#define BIT_FS_CLI1_RX_UAPSDMD1_INT_8821C BIT(23)
+#define BIT_FS_CLI1_RX_UAPSDMD0_INT_8821C BIT(22)
+#define BIT_FS_CLI1_TRIGGER_PKT_INT_8821C BIT(21)
+#define BIT_FS_CLI1_EOSP_INT_8821C BIT(20)
+#define BIT_FS_CLI0_RX_UAPSDMD1_INT_8821C BIT(19)
+#define BIT_FS_CLI0_RX_UAPSDMD0_INT_8821C BIT(18)
+#define BIT_FS_CLI0_TRIGGER_PKT_INT_8821C BIT(17)
+#define BIT_FS_CLI0_EOSP_INT_8821C BIT(16)
+#define BIT_FS_TSF_BIT32_TOGGLE_P2P2_INT_8821C BIT(9)
+#define BIT_FS_TSF_BIT32_TOGGLE_P2P1_INT_8821C BIT(8)
+#define BIT_FS_CLI3_TX_NULL1_INT_8821C BIT(7)
+#define BIT_FS_CLI3_TX_NULL0_INT_8821C BIT(6)
+#define BIT_FS_CLI2_TX_NULL1_INT_8821C BIT(5)
+#define BIT_FS_CLI2_TX_NULL0_INT_8821C BIT(4)
+#define BIT_FS_CLI1_TX_NULL1_INT_8821C BIT(3)
+#define BIT_FS_CLI1_TX_NULL0_INT_8821C BIT(2)
+#define BIT_FS_CLI0_TX_NULL1_INT_8821C BIT(1)
+#define BIT_FS_CLI0_TX_NULL0_INT_8821C BIT(0)
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_MSG2_8821C */
+
+#define BIT_SHIFT_FW_MSG2_8821C 0
+#define BIT_MASK_FW_MSG2_8821C 0xffffffffL
+#define BIT_FW_MSG2_8821C(x)                                                   \
+	(((x) & BIT_MASK_FW_MSG2_8821C) << BIT_SHIFT_FW_MSG2_8821C)
+#define BITS_FW_MSG2_8821C (BIT_MASK_FW_MSG2_8821C << BIT_SHIFT_FW_MSG2_8821C)
+#define BIT_CLEAR_FW_MSG2_8821C(x) ((x) & (~BITS_FW_MSG2_8821C))
+#define BIT_GET_FW_MSG2_8821C(x)                                               \
+	(((x) >> BIT_SHIFT_FW_MSG2_8821C) & BIT_MASK_FW_MSG2_8821C)
+#define BIT_SET_FW_MSG2_8821C(x, v)                                            \
+	(BIT_CLEAR_FW_MSG2_8821C(x) | BIT_FW_MSG2_8821C(v))
+
+/* 2 REG_MSG3_8821C */
+
+#define BIT_SHIFT_FW_MSG3_8821C 0
+#define BIT_MASK_FW_MSG3_8821C 0xffffffffL
+#define BIT_FW_MSG3_8821C(x)                                                   \
+	(((x) & BIT_MASK_FW_MSG3_8821C) << BIT_SHIFT_FW_MSG3_8821C)
+#define BITS_FW_MSG3_8821C (BIT_MASK_FW_MSG3_8821C << BIT_SHIFT_FW_MSG3_8821C)
+#define BIT_CLEAR_FW_MSG3_8821C(x) ((x) & (~BITS_FW_MSG3_8821C))
+#define BIT_GET_FW_MSG3_8821C(x)                                               \
+	(((x) >> BIT_SHIFT_FW_MSG3_8821C) & BIT_MASK_FW_MSG3_8821C)
+#define BIT_SET_FW_MSG3_8821C(x, v)                                            \
+	(BIT_CLEAR_FW_MSG3_8821C(x) | BIT_FW_MSG3_8821C(v))
+
+/* 2 REG_MSG4_8821C */
+
+#define BIT_SHIFT_FW_MSG4_8821C 0
+#define BIT_MASK_FW_MSG4_8821C 0xffffffffL
+#define BIT_FW_MSG4_8821C(x)                                                   \
+	(((x) & BIT_MASK_FW_MSG4_8821C) << BIT_SHIFT_FW_MSG4_8821C)
+#define BITS_FW_MSG4_8821C (BIT_MASK_FW_MSG4_8821C << BIT_SHIFT_FW_MSG4_8821C)
+#define BIT_CLEAR_FW_MSG4_8821C(x) ((x) & (~BITS_FW_MSG4_8821C))
+#define BIT_GET_FW_MSG4_8821C(x)                                               \
+	(((x) >> BIT_SHIFT_FW_MSG4_8821C) & BIT_MASK_FW_MSG4_8821C)
+#define BIT_SET_FW_MSG4_8821C(x, v)                                            \
+	(BIT_CLEAR_FW_MSG4_8821C(x) | BIT_FW_MSG4_8821C(v))
+
+/* 2 REG_MSG5_8821C */
+
+#define BIT_SHIFT_FW_MSG5_8821C 0
+#define BIT_MASK_FW_MSG5_8821C 0xffffffffL
+#define BIT_FW_MSG5_8821C(x)                                                   \
+	(((x) & BIT_MASK_FW_MSG5_8821C) << BIT_SHIFT_FW_MSG5_8821C)
+#define BITS_FW_MSG5_8821C (BIT_MASK_FW_MSG5_8821C << BIT_SHIFT_FW_MSG5_8821C)
+#define BIT_CLEAR_FW_MSG5_8821C(x) ((x) & (~BITS_FW_MSG5_8821C))
+#define BIT_GET_FW_MSG5_8821C(x)                                               \
+	(((x) >> BIT_SHIFT_FW_MSG5_8821C) & BIT_MASK_FW_MSG5_8821C)
+#define BIT_SET_FW_MSG5_8821C(x, v)                                            \
+	(BIT_CLEAR_FW_MSG5_8821C(x) | BIT_FW_MSG5_8821C(v))
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_FIFOPAGE_CTRL_1_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+#define BIT_SHIFT_TX_OQT_HE_FREE_SPACE_V1_8821C 16
+#define BIT_MASK_TX_OQT_HE_FREE_SPACE_V1_8821C 0xff
+#define BIT_TX_OQT_HE_FREE_SPACE_V1_8821C(x)                                   \
+	(((x) & BIT_MASK_TX_OQT_HE_FREE_SPACE_V1_8821C)                        \
+	 << BIT_SHIFT_TX_OQT_HE_FREE_SPACE_V1_8821C)
+#define BITS_TX_OQT_HE_FREE_SPACE_V1_8821C                                     \
+	(BIT_MASK_TX_OQT_HE_FREE_SPACE_V1_8821C                                \
+	 << BIT_SHIFT_TX_OQT_HE_FREE_SPACE_V1_8821C)
+#define BIT_CLEAR_TX_OQT_HE_FREE_SPACE_V1_8821C(x)                             \
+	((x) & (~BITS_TX_OQT_HE_FREE_SPACE_V1_8821C))
+#define BIT_GET_TX_OQT_HE_FREE_SPACE_V1_8821C(x)                               \
+	(((x) >> BIT_SHIFT_TX_OQT_HE_FREE_SPACE_V1_8821C) &                    \
+	 BIT_MASK_TX_OQT_HE_FREE_SPACE_V1_8821C)
+#define BIT_SET_TX_OQT_HE_FREE_SPACE_V1_8821C(x, v)                            \
+	(BIT_CLEAR_TX_OQT_HE_FREE_SPACE_V1_8821C(x) |                          \
+	 BIT_TX_OQT_HE_FREE_SPACE_V1_8821C(v))
+
+/* 2 REG_NOT_VALID_8821C */
+
+#define BIT_SHIFT_TX_OQT_NL_FREE_SPACE_V1_8821C 0
+#define BIT_MASK_TX_OQT_NL_FREE_SPACE_V1_8821C 0xff
+#define BIT_TX_OQT_NL_FREE_SPACE_V1_8821C(x)                                   \
+	(((x) & BIT_MASK_TX_OQT_NL_FREE_SPACE_V1_8821C)                        \
+	 << BIT_SHIFT_TX_OQT_NL_FREE_SPACE_V1_8821C)
+#define BITS_TX_OQT_NL_FREE_SPACE_V1_8821C                                     \
+	(BIT_MASK_TX_OQT_NL_FREE_SPACE_V1_8821C                                \
+	 << BIT_SHIFT_TX_OQT_NL_FREE_SPACE_V1_8821C)
+#define BIT_CLEAR_TX_OQT_NL_FREE_SPACE_V1_8821C(x)                             \
+	((x) & (~BITS_TX_OQT_NL_FREE_SPACE_V1_8821C))
+#define BIT_GET_TX_OQT_NL_FREE_SPACE_V1_8821C(x)                               \
+	(((x) >> BIT_SHIFT_TX_OQT_NL_FREE_SPACE_V1_8821C) &                    \
+	 BIT_MASK_TX_OQT_NL_FREE_SPACE_V1_8821C)
+#define BIT_SET_TX_OQT_NL_FREE_SPACE_V1_8821C(x, v)                            \
+	(BIT_CLEAR_TX_OQT_NL_FREE_SPACE_V1_8821C(x) |                          \
+	 BIT_TX_OQT_NL_FREE_SPACE_V1_8821C(v))
+
+/* 2 REG_FIFOPAGE_CTRL_2_8821C */
+#define BIT_BCN_VALID_1_V1_8821C BIT(31)
+
+/* 2 REG_NOT_VALID_8821C */
+
+#define BIT_SHIFT_BCN_HEAD_1_V1_8821C 16
+#define BIT_MASK_BCN_HEAD_1_V1_8821C 0xfff
+#define BIT_BCN_HEAD_1_V1_8821C(x)                                             \
+	(((x) & BIT_MASK_BCN_HEAD_1_V1_8821C) << BIT_SHIFT_BCN_HEAD_1_V1_8821C)
+#define BITS_BCN_HEAD_1_V1_8821C                                               \
+	(BIT_MASK_BCN_HEAD_1_V1_8821C << BIT_SHIFT_BCN_HEAD_1_V1_8821C)
+#define BIT_CLEAR_BCN_HEAD_1_V1_8821C(x) ((x) & (~BITS_BCN_HEAD_1_V1_8821C))
+#define BIT_GET_BCN_HEAD_1_V1_8821C(x)                                         \
+	(((x) >> BIT_SHIFT_BCN_HEAD_1_V1_8821C) & BIT_MASK_BCN_HEAD_1_V1_8821C)
+#define BIT_SET_BCN_HEAD_1_V1_8821C(x, v)                                      \
+	(BIT_CLEAR_BCN_HEAD_1_V1_8821C(x) | BIT_BCN_HEAD_1_V1_8821C(v))
+
+#define BIT_BCN_VALID_V1_8821C BIT(15)
+
+/* 2 REG_NOT_VALID_8821C */
+
+#define BIT_SHIFT_BCN_HEAD_V1_8821C 0
+#define BIT_MASK_BCN_HEAD_V1_8821C 0xfff
+#define BIT_BCN_HEAD_V1_8821C(x)                                               \
+	(((x) & BIT_MASK_BCN_HEAD_V1_8821C) << BIT_SHIFT_BCN_HEAD_V1_8821C)
+#define BITS_BCN_HEAD_V1_8821C                                                 \
+	(BIT_MASK_BCN_HEAD_V1_8821C << BIT_SHIFT_BCN_HEAD_V1_8821C)
+#define BIT_CLEAR_BCN_HEAD_V1_8821C(x) ((x) & (~BITS_BCN_HEAD_V1_8821C))
+#define BIT_GET_BCN_HEAD_V1_8821C(x)                                           \
+	(((x) >> BIT_SHIFT_BCN_HEAD_V1_8821C) & BIT_MASK_BCN_HEAD_V1_8821C)
+#define BIT_SET_BCN_HEAD_V1_8821C(x, v)                                        \
+	(BIT_CLEAR_BCN_HEAD_V1_8821C(x) | BIT_BCN_HEAD_V1_8821C(v))
+
+/* 2 REG_AUTO_LLT_V1_8821C */
+
+#define BIT_SHIFT_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8821C 24
+#define BIT_MASK_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8821C 0xff
+#define BIT_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8821C(x)                            \
+	(((x) & BIT_MASK_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8821C)                 \
+	 << BIT_SHIFT_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8821C)
+#define BITS_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8821C                              \
+	(BIT_MASK_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8821C                         \
+	 << BIT_SHIFT_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8821C)
+#define BIT_CLEAR_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8821C(x)                      \
+	((x) & (~BITS_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8821C))
+#define BIT_GET_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8821C(x)                        \
+	(((x) >> BIT_SHIFT_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8821C) &             \
+	 BIT_MASK_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8821C)
+#define BIT_SET_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8821C(x, v)                     \
+	(BIT_CLEAR_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8821C(x) |                   \
+	 BIT_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8821C(v))
+
+#define BIT_SHIFT_LLT_FREE_PAGE_V1_8821C 8
+#define BIT_MASK_LLT_FREE_PAGE_V1_8821C 0xffff
+#define BIT_LLT_FREE_PAGE_V1_8821C(x)                                          \
+	(((x) & BIT_MASK_LLT_FREE_PAGE_V1_8821C)                               \
+	 << BIT_SHIFT_LLT_FREE_PAGE_V1_8821C)
+#define BITS_LLT_FREE_PAGE_V1_8821C                                            \
+	(BIT_MASK_LLT_FREE_PAGE_V1_8821C << BIT_SHIFT_LLT_FREE_PAGE_V1_8821C)
+#define BIT_CLEAR_LLT_FREE_PAGE_V1_8821C(x)                                    \
+	((x) & (~BITS_LLT_FREE_PAGE_V1_8821C))
+#define BIT_GET_LLT_FREE_PAGE_V1_8821C(x)                                      \
+	(((x) >> BIT_SHIFT_LLT_FREE_PAGE_V1_8821C) &                           \
+	 BIT_MASK_LLT_FREE_PAGE_V1_8821C)
+#define BIT_SET_LLT_FREE_PAGE_V1_8821C(x, v)                                   \
+	(BIT_CLEAR_LLT_FREE_PAGE_V1_8821C(x) | BIT_LLT_FREE_PAGE_V1_8821C(v))
+
+#define BIT_SHIFT_BLK_DESC_NUM_8821C 4
+#define BIT_MASK_BLK_DESC_NUM_8821C 0xf
+#define BIT_BLK_DESC_NUM_8821C(x)                                              \
+	(((x) & BIT_MASK_BLK_DESC_NUM_8821C) << BIT_SHIFT_BLK_DESC_NUM_8821C)
+#define BITS_BLK_DESC_NUM_8821C                                                \
+	(BIT_MASK_BLK_DESC_NUM_8821C << BIT_SHIFT_BLK_DESC_NUM_8821C)
+#define BIT_CLEAR_BLK_DESC_NUM_8821C(x) ((x) & (~BITS_BLK_DESC_NUM_8821C))
+#define BIT_GET_BLK_DESC_NUM_8821C(x)                                          \
+	(((x) >> BIT_SHIFT_BLK_DESC_NUM_8821C) & BIT_MASK_BLK_DESC_NUM_8821C)
+#define BIT_SET_BLK_DESC_NUM_8821C(x, v)                                       \
+	(BIT_CLEAR_BLK_DESC_NUM_8821C(x) | BIT_BLK_DESC_NUM_8821C(v))
+
+#define BIT_R_BCN_HEAD_SEL_8821C BIT(3)
+#define BIT_R_EN_BCN_SW_HEAD_SEL_8821C BIT(2)
+#define BIT_LLT_DBG_SEL_8821C BIT(1)
+#define BIT_AUTO_INIT_LLT_V1_8821C BIT(0)
+
+/* 2 REG_TXDMA_OFFSET_CHK_8821C */
+#define BIT_EM_CHKSUM_FIN_8821C BIT(31)
+#define BIT_EMN_PCIE_DMA_MOD_8821C BIT(30)
+#define BIT_EN_TXQUE_CLR_8821C BIT(29)
+#define BIT_EN_PCIE_FIFO_MODE_8821C BIT(28)
+
+#define BIT_SHIFT_PG_UNDER_TH_V1_8821C 16
+#define BIT_MASK_PG_UNDER_TH_V1_8821C 0xfff
+#define BIT_PG_UNDER_TH_V1_8821C(x)                                            \
+	(((x) & BIT_MASK_PG_UNDER_TH_V1_8821C)                                 \
+	 << BIT_SHIFT_PG_UNDER_TH_V1_8821C)
+#define BITS_PG_UNDER_TH_V1_8821C                                              \
+	(BIT_MASK_PG_UNDER_TH_V1_8821C << BIT_SHIFT_PG_UNDER_TH_V1_8821C)
+#define BIT_CLEAR_PG_UNDER_TH_V1_8821C(x) ((x) & (~BITS_PG_UNDER_TH_V1_8821C))
+#define BIT_GET_PG_UNDER_TH_V1_8821C(x)                                        \
+	(((x) >> BIT_SHIFT_PG_UNDER_TH_V1_8821C) &                             \
+	 BIT_MASK_PG_UNDER_TH_V1_8821C)
+#define BIT_SET_PG_UNDER_TH_V1_8821C(x, v)                                     \
+	(BIT_CLEAR_PG_UNDER_TH_V1_8821C(x) | BIT_PG_UNDER_TH_V1_8821C(v))
+
+/* 2 REG_NOT_VALID_8821C */
+#define BIT_SDIO_TXDESC_CHKSUM_EN_8821C BIT(13)
+#define BIT_RST_RDPTR_8821C BIT(12)
+#define BIT_RST_WRPTR_8821C BIT(11)
+#define BIT_CHK_PG_TH_EN_8821C BIT(10)
+#define BIT_DROP_DATA_EN_8821C BIT(9)
+#define BIT_CHECK_OFFSET_EN_8821C BIT(8)
+
+#define BIT_SHIFT_CHECK_OFFSET_8821C 0
+#define BIT_MASK_CHECK_OFFSET_8821C 0xff
+#define BIT_CHECK_OFFSET_8821C(x)                                              \
+	(((x) & BIT_MASK_CHECK_OFFSET_8821C) << BIT_SHIFT_CHECK_OFFSET_8821C)
+#define BITS_CHECK_OFFSET_8821C                                                \
+	(BIT_MASK_CHECK_OFFSET_8821C << BIT_SHIFT_CHECK_OFFSET_8821C)
+#define BIT_CLEAR_CHECK_OFFSET_8821C(x) ((x) & (~BITS_CHECK_OFFSET_8821C))
+#define BIT_GET_CHECK_OFFSET_8821C(x)                                          \
+	(((x) >> BIT_SHIFT_CHECK_OFFSET_8821C) & BIT_MASK_CHECK_OFFSET_8821C)
+#define BIT_SET_CHECK_OFFSET_8821C(x, v)                                       \
+	(BIT_CLEAR_CHECK_OFFSET_8821C(x) | BIT_CHECK_OFFSET_8821C(v))
+
+/* 2 REG_TXDMA_STATUS_8821C */
+#define BIT_TXPKTBUF_REQ_ERR_8821C BIT(18)
+#define BIT_HI_OQT_UDN_8821C BIT(17)
+#define BIT_HI_OQT_OVF_8821C BIT(16)
+#define BIT_PAYLOAD_CHKSUM_ERR_8821C BIT(15)
+#define BIT_PAYLOAD_UDN_8821C BIT(14)
+#define BIT_PAYLOAD_OVF_8821C BIT(13)
+#define BIT_DSC_CHKSUM_FAIL_8821C BIT(12)
+#define BIT_UNKNOWN_QSEL_8821C BIT(11)
+#define BIT_EP_QSEL_DIFF_8821C BIT(10)
+#define BIT_TX_OFFS_UNMATCH_8821C BIT(9)
+#define BIT_TXOQT_UDN_8821C BIT(8)
+#define BIT_TXOQT_OVF_8821C BIT(7)
+#define BIT_TXDMA_SFF_UDN_8821C BIT(6)
+#define BIT_TXDMA_SFF_OVF_8821C BIT(5)
+#define BIT_LLT_NULL_PG_8821C BIT(4)
+#define BIT_PAGE_UDN_8821C BIT(3)
+#define BIT_PAGE_OVF_8821C BIT(2)
+#define BIT_TXFF_PG_UDN_8821C BIT(1)
+#define BIT_TXFF_PG_OVF_8821C BIT(0)
+
+/* 2 REG_TX_DMA_DBG_8821C */
+
+/* 2 REG_TQPNT1_8821C */
+#define BIT_HPQ_INT_EN_8821C BIT(31)
+
+#define BIT_SHIFT_HPQ_HIGH_TH_V1_8821C 16
+#define BIT_MASK_HPQ_HIGH_TH_V1_8821C 0xfff
+#define BIT_HPQ_HIGH_TH_V1_8821C(x)                                            \
+	(((x) & BIT_MASK_HPQ_HIGH_TH_V1_8821C)                                 \
+	 << BIT_SHIFT_HPQ_HIGH_TH_V1_8821C)
+#define BITS_HPQ_HIGH_TH_V1_8821C                                              \
+	(BIT_MASK_HPQ_HIGH_TH_V1_8821C << BIT_SHIFT_HPQ_HIGH_TH_V1_8821C)
+#define BIT_CLEAR_HPQ_HIGH_TH_V1_8821C(x) ((x) & (~BITS_HPQ_HIGH_TH_V1_8821C))
+#define BIT_GET_HPQ_HIGH_TH_V1_8821C(x)                                        \
+	(((x) >> BIT_SHIFT_HPQ_HIGH_TH_V1_8821C) &                             \
+	 BIT_MASK_HPQ_HIGH_TH_V1_8821C)
+#define BIT_SET_HPQ_HIGH_TH_V1_8821C(x, v)                                     \
+	(BIT_CLEAR_HPQ_HIGH_TH_V1_8821C(x) | BIT_HPQ_HIGH_TH_V1_8821C(v))
+
+#define BIT_SHIFT_HPQ_LOW_TH_V1_8821C 0
+#define BIT_MASK_HPQ_LOW_TH_V1_8821C 0xfff
+#define BIT_HPQ_LOW_TH_V1_8821C(x)                                             \
+	(((x) & BIT_MASK_HPQ_LOW_TH_V1_8821C) << BIT_SHIFT_HPQ_LOW_TH_V1_8821C)
+#define BITS_HPQ_LOW_TH_V1_8821C                                               \
+	(BIT_MASK_HPQ_LOW_TH_V1_8821C << BIT_SHIFT_HPQ_LOW_TH_V1_8821C)
+#define BIT_CLEAR_HPQ_LOW_TH_V1_8821C(x) ((x) & (~BITS_HPQ_LOW_TH_V1_8821C))
+#define BIT_GET_HPQ_LOW_TH_V1_8821C(x)                                         \
+	(((x) >> BIT_SHIFT_HPQ_LOW_TH_V1_8821C) & BIT_MASK_HPQ_LOW_TH_V1_8821C)
+#define BIT_SET_HPQ_LOW_TH_V1_8821C(x, v)                                      \
+	(BIT_CLEAR_HPQ_LOW_TH_V1_8821C(x) | BIT_HPQ_LOW_TH_V1_8821C(v))
+
+/* 2 REG_TQPNT2_8821C */
+#define BIT_NPQ_INT_EN_8821C BIT(31)
+
+#define BIT_SHIFT_NPQ_HIGH_TH_V1_8821C 16
+#define BIT_MASK_NPQ_HIGH_TH_V1_8821C 0xfff
+#define BIT_NPQ_HIGH_TH_V1_8821C(x)                                            \
+	(((x) & BIT_MASK_NPQ_HIGH_TH_V1_8821C)                                 \
+	 << BIT_SHIFT_NPQ_HIGH_TH_V1_8821C)
+#define BITS_NPQ_HIGH_TH_V1_8821C                                              \
+	(BIT_MASK_NPQ_HIGH_TH_V1_8821C << BIT_SHIFT_NPQ_HIGH_TH_V1_8821C)
+#define BIT_CLEAR_NPQ_HIGH_TH_V1_8821C(x) ((x) & (~BITS_NPQ_HIGH_TH_V1_8821C))
+#define BIT_GET_NPQ_HIGH_TH_V1_8821C(x)                                        \
+	(((x) >> BIT_SHIFT_NPQ_HIGH_TH_V1_8821C) &                             \
+	 BIT_MASK_NPQ_HIGH_TH_V1_8821C)
+#define BIT_SET_NPQ_HIGH_TH_V1_8821C(x, v)                                     \
+	(BIT_CLEAR_NPQ_HIGH_TH_V1_8821C(x) | BIT_NPQ_HIGH_TH_V1_8821C(v))
+
+#define BIT_SHIFT_NPQ_LOW_TH_V1_8821C 0
+#define BIT_MASK_NPQ_LOW_TH_V1_8821C 0xfff
+#define BIT_NPQ_LOW_TH_V1_8821C(x)                                             \
+	(((x) & BIT_MASK_NPQ_LOW_TH_V1_8821C) << BIT_SHIFT_NPQ_LOW_TH_V1_8821C)
+#define BITS_NPQ_LOW_TH_V1_8821C                                               \
+	(BIT_MASK_NPQ_LOW_TH_V1_8821C << BIT_SHIFT_NPQ_LOW_TH_V1_8821C)
+#define BIT_CLEAR_NPQ_LOW_TH_V1_8821C(x) ((x) & (~BITS_NPQ_LOW_TH_V1_8821C))
+#define BIT_GET_NPQ_LOW_TH_V1_8821C(x)                                         \
+	(((x) >> BIT_SHIFT_NPQ_LOW_TH_V1_8821C) & BIT_MASK_NPQ_LOW_TH_V1_8821C)
+#define BIT_SET_NPQ_LOW_TH_V1_8821C(x, v)                                      \
+	(BIT_CLEAR_NPQ_LOW_TH_V1_8821C(x) | BIT_NPQ_LOW_TH_V1_8821C(v))
+
+/* 2 REG_TQPNT3_8821C */
+#define BIT_LPQ_INT_EN_8821C BIT(31)
+
+#define BIT_SHIFT_LPQ_HIGH_TH_V1_8821C 16
+#define BIT_MASK_LPQ_HIGH_TH_V1_8821C 0xfff
+#define BIT_LPQ_HIGH_TH_V1_8821C(x)                                            \
+	(((x) & BIT_MASK_LPQ_HIGH_TH_V1_8821C)                                 \
+	 << BIT_SHIFT_LPQ_HIGH_TH_V1_8821C)
+#define BITS_LPQ_HIGH_TH_V1_8821C                                              \
+	(BIT_MASK_LPQ_HIGH_TH_V1_8821C << BIT_SHIFT_LPQ_HIGH_TH_V1_8821C)
+#define BIT_CLEAR_LPQ_HIGH_TH_V1_8821C(x) ((x) & (~BITS_LPQ_HIGH_TH_V1_8821C))
+#define BIT_GET_LPQ_HIGH_TH_V1_8821C(x)                                        \
+	(((x) >> BIT_SHIFT_LPQ_HIGH_TH_V1_8821C) &                             \
+	 BIT_MASK_LPQ_HIGH_TH_V1_8821C)
+#define BIT_SET_LPQ_HIGH_TH_V1_8821C(x, v)                                     \
+	(BIT_CLEAR_LPQ_HIGH_TH_V1_8821C(x) | BIT_LPQ_HIGH_TH_V1_8821C(v))
+
+#define BIT_SHIFT_LPQ_LOW_TH_V1_8821C 0
+#define BIT_MASK_LPQ_LOW_TH_V1_8821C 0xfff
+#define BIT_LPQ_LOW_TH_V1_8821C(x)                                             \
+	(((x) & BIT_MASK_LPQ_LOW_TH_V1_8821C) << BIT_SHIFT_LPQ_LOW_TH_V1_8821C)
+#define BITS_LPQ_LOW_TH_V1_8821C                                               \
+	(BIT_MASK_LPQ_LOW_TH_V1_8821C << BIT_SHIFT_LPQ_LOW_TH_V1_8821C)
+#define BIT_CLEAR_LPQ_LOW_TH_V1_8821C(x) ((x) & (~BITS_LPQ_LOW_TH_V1_8821C))
+#define BIT_GET_LPQ_LOW_TH_V1_8821C(x)                                         \
+	(((x) >> BIT_SHIFT_LPQ_LOW_TH_V1_8821C) & BIT_MASK_LPQ_LOW_TH_V1_8821C)
+#define BIT_SET_LPQ_LOW_TH_V1_8821C(x, v)                                      \
+	(BIT_CLEAR_LPQ_LOW_TH_V1_8821C(x) | BIT_LPQ_LOW_TH_V1_8821C(v))
+
+/* 2 REG_TQPNT4_8821C */
+#define BIT_EXQ_INT_EN_8821C BIT(31)
+
+#define BIT_SHIFT_EXQ_HIGH_TH_V1_8821C 16
+#define BIT_MASK_EXQ_HIGH_TH_V1_8821C 0xfff
+#define BIT_EXQ_HIGH_TH_V1_8821C(x)                                            \
+	(((x) & BIT_MASK_EXQ_HIGH_TH_V1_8821C)                                 \
+	 << BIT_SHIFT_EXQ_HIGH_TH_V1_8821C)
+#define BITS_EXQ_HIGH_TH_V1_8821C                                              \
+	(BIT_MASK_EXQ_HIGH_TH_V1_8821C << BIT_SHIFT_EXQ_HIGH_TH_V1_8821C)
+#define BIT_CLEAR_EXQ_HIGH_TH_V1_8821C(x) ((x) & (~BITS_EXQ_HIGH_TH_V1_8821C))
+#define BIT_GET_EXQ_HIGH_TH_V1_8821C(x)                                        \
+	(((x) >> BIT_SHIFT_EXQ_HIGH_TH_V1_8821C) &                             \
+	 BIT_MASK_EXQ_HIGH_TH_V1_8821C)
+#define BIT_SET_EXQ_HIGH_TH_V1_8821C(x, v)                                     \
+	(BIT_CLEAR_EXQ_HIGH_TH_V1_8821C(x) | BIT_EXQ_HIGH_TH_V1_8821C(v))
+
+#define BIT_SHIFT_EXQ_LOW_TH_V1_8821C 0
+#define BIT_MASK_EXQ_LOW_TH_V1_8821C 0xfff
+#define BIT_EXQ_LOW_TH_V1_8821C(x)                                             \
+	(((x) & BIT_MASK_EXQ_LOW_TH_V1_8821C) << BIT_SHIFT_EXQ_LOW_TH_V1_8821C)
+#define BITS_EXQ_LOW_TH_V1_8821C                                               \
+	(BIT_MASK_EXQ_LOW_TH_V1_8821C << BIT_SHIFT_EXQ_LOW_TH_V1_8821C)
+#define BIT_CLEAR_EXQ_LOW_TH_V1_8821C(x) ((x) & (~BITS_EXQ_LOW_TH_V1_8821C))
+#define BIT_GET_EXQ_LOW_TH_V1_8821C(x)                                         \
+	(((x) >> BIT_SHIFT_EXQ_LOW_TH_V1_8821C) & BIT_MASK_EXQ_LOW_TH_V1_8821C)
+#define BIT_SET_EXQ_LOW_TH_V1_8821C(x, v)                                      \
+	(BIT_CLEAR_EXQ_LOW_TH_V1_8821C(x) | BIT_EXQ_LOW_TH_V1_8821C(v))
+
+/* 2 REG_RQPN_CTRL_1_8821C */
+
+#define BIT_SHIFT_TXPKTNUM_H_8821C 16
+#define BIT_MASK_TXPKTNUM_H_8821C 0xffff
+#define BIT_TXPKTNUM_H_8821C(x)                                                \
+	(((x) & BIT_MASK_TXPKTNUM_H_8821C) << BIT_SHIFT_TXPKTNUM_H_8821C)
+#define BITS_TXPKTNUM_H_8821C                                                  \
+	(BIT_MASK_TXPKTNUM_H_8821C << BIT_SHIFT_TXPKTNUM_H_8821C)
+#define BIT_CLEAR_TXPKTNUM_H_8821C(x) ((x) & (~BITS_TXPKTNUM_H_8821C))
+#define BIT_GET_TXPKTNUM_H_8821C(x)                                            \
+	(((x) >> BIT_SHIFT_TXPKTNUM_H_8821C) & BIT_MASK_TXPKTNUM_H_8821C)
+#define BIT_SET_TXPKTNUM_H_8821C(x, v)                                         \
+	(BIT_CLEAR_TXPKTNUM_H_8821C(x) | BIT_TXPKTNUM_H_8821C(v))
+
+#define BIT_SHIFT_TXPKTNUM_V2_8821C 0
+#define BIT_MASK_TXPKTNUM_V2_8821C 0xffff
+#define BIT_TXPKTNUM_V2_8821C(x)                                               \
+	(((x) & BIT_MASK_TXPKTNUM_V2_8821C) << BIT_SHIFT_TXPKTNUM_V2_8821C)
+#define BITS_TXPKTNUM_V2_8821C                                                 \
+	(BIT_MASK_TXPKTNUM_V2_8821C << BIT_SHIFT_TXPKTNUM_V2_8821C)
+#define BIT_CLEAR_TXPKTNUM_V2_8821C(x) ((x) & (~BITS_TXPKTNUM_V2_8821C))
+#define BIT_GET_TXPKTNUM_V2_8821C(x)                                           \
+	(((x) >> BIT_SHIFT_TXPKTNUM_V2_8821C) & BIT_MASK_TXPKTNUM_V2_8821C)
+#define BIT_SET_TXPKTNUM_V2_8821C(x, v)                                        \
+	(BIT_CLEAR_TXPKTNUM_V2_8821C(x) | BIT_TXPKTNUM_V2_8821C(v))
+
+/* 2 REG_RQPN_CTRL_2_8821C */
+#define BIT_LD_RQPN_8821C BIT(31)
+#define BIT_EXQ_PUBLIC_DIS_V1_8821C BIT(19)
+#define BIT_NPQ_PUBLIC_DIS_V1_8821C BIT(18)
+#define BIT_LPQ_PUBLIC_DIS_V1_8821C BIT(17)
+#define BIT_HPQ_PUBLIC_DIS_V1_8821C BIT(16)
+#define BIT_SDIO_TXAGG_ALIGN_ADJUST_EN_8821C BIT(15)
+
+#define BIT_SHIFT_SDIO_TXAGG_ALIGN_SIZE_8821C 0
+#define BIT_MASK_SDIO_TXAGG_ALIGN_SIZE_8821C 0xfff
+#define BIT_SDIO_TXAGG_ALIGN_SIZE_8821C(x)                                     \
+	(((x) & BIT_MASK_SDIO_TXAGG_ALIGN_SIZE_8821C)                          \
+	 << BIT_SHIFT_SDIO_TXAGG_ALIGN_SIZE_8821C)
+#define BITS_SDIO_TXAGG_ALIGN_SIZE_8821C                                       \
+	(BIT_MASK_SDIO_TXAGG_ALIGN_SIZE_8821C                                  \
+	 << BIT_SHIFT_SDIO_TXAGG_ALIGN_SIZE_8821C)
+#define BIT_CLEAR_SDIO_TXAGG_ALIGN_SIZE_8821C(x)                               \
+	((x) & (~BITS_SDIO_TXAGG_ALIGN_SIZE_8821C))
+#define BIT_GET_SDIO_TXAGG_ALIGN_SIZE_8821C(x)                                 \
+	(((x) >> BIT_SHIFT_SDIO_TXAGG_ALIGN_SIZE_8821C) &                      \
+	 BIT_MASK_SDIO_TXAGG_ALIGN_SIZE_8821C)
+#define BIT_SET_SDIO_TXAGG_ALIGN_SIZE_8821C(x, v)                              \
+	(BIT_CLEAR_SDIO_TXAGG_ALIGN_SIZE_8821C(x) |                            \
+	 BIT_SDIO_TXAGG_ALIGN_SIZE_8821C(v))
+
+/* 2 REG_FIFOPAGE_INFO_1_8821C */
+
+#define BIT_SHIFT_HPQ_AVAL_PG_V1_8821C 16
+#define BIT_MASK_HPQ_AVAL_PG_V1_8821C 0xfff
+#define BIT_HPQ_AVAL_PG_V1_8821C(x)                                            \
+	(((x) & BIT_MASK_HPQ_AVAL_PG_V1_8821C)                                 \
+	 << BIT_SHIFT_HPQ_AVAL_PG_V1_8821C)
+#define BITS_HPQ_AVAL_PG_V1_8821C                                              \
+	(BIT_MASK_HPQ_AVAL_PG_V1_8821C << BIT_SHIFT_HPQ_AVAL_PG_V1_8821C)
+#define BIT_CLEAR_HPQ_AVAL_PG_V1_8821C(x) ((x) & (~BITS_HPQ_AVAL_PG_V1_8821C))
+#define BIT_GET_HPQ_AVAL_PG_V1_8821C(x)                                        \
+	(((x) >> BIT_SHIFT_HPQ_AVAL_PG_V1_8821C) &                             \
+	 BIT_MASK_HPQ_AVAL_PG_V1_8821C)
+#define BIT_SET_HPQ_AVAL_PG_V1_8821C(x, v)                                     \
+	(BIT_CLEAR_HPQ_AVAL_PG_V1_8821C(x) | BIT_HPQ_AVAL_PG_V1_8821C(v))
+
+#define BIT_SHIFT_HPQ_V1_8821C 0
+#define BIT_MASK_HPQ_V1_8821C 0xfff
+#define BIT_HPQ_V1_8821C(x)                                                    \
+	(((x) & BIT_MASK_HPQ_V1_8821C) << BIT_SHIFT_HPQ_V1_8821C)
+#define BITS_HPQ_V1_8821C (BIT_MASK_HPQ_V1_8821C << BIT_SHIFT_HPQ_V1_8821C)
+#define BIT_CLEAR_HPQ_V1_8821C(x) ((x) & (~BITS_HPQ_V1_8821C))
+#define BIT_GET_HPQ_V1_8821C(x)                                                \
+	(((x) >> BIT_SHIFT_HPQ_V1_8821C) & BIT_MASK_HPQ_V1_8821C)
+#define BIT_SET_HPQ_V1_8821C(x, v)                                             \
+	(BIT_CLEAR_HPQ_V1_8821C(x) | BIT_HPQ_V1_8821C(v))
+
+/* 2 REG_FIFOPAGE_INFO_2_8821C */
+
+#define BIT_SHIFT_LPQ_AVAL_PG_V1_8821C 16
+#define BIT_MASK_LPQ_AVAL_PG_V1_8821C 0xfff
+#define BIT_LPQ_AVAL_PG_V1_8821C(x)                                            \
+	(((x) & BIT_MASK_LPQ_AVAL_PG_V1_8821C)                                 \
+	 << BIT_SHIFT_LPQ_AVAL_PG_V1_8821C)
+#define BITS_LPQ_AVAL_PG_V1_8821C                                              \
+	(BIT_MASK_LPQ_AVAL_PG_V1_8821C << BIT_SHIFT_LPQ_AVAL_PG_V1_8821C)
+#define BIT_CLEAR_LPQ_AVAL_PG_V1_8821C(x) ((x) & (~BITS_LPQ_AVAL_PG_V1_8821C))
+#define BIT_GET_LPQ_AVAL_PG_V1_8821C(x)                                        \
+	(((x) >> BIT_SHIFT_LPQ_AVAL_PG_V1_8821C) &                             \
+	 BIT_MASK_LPQ_AVAL_PG_V1_8821C)
+#define BIT_SET_LPQ_AVAL_PG_V1_8821C(x, v)                                     \
+	(BIT_CLEAR_LPQ_AVAL_PG_V1_8821C(x) | BIT_LPQ_AVAL_PG_V1_8821C(v))
+
+#define BIT_SHIFT_LPQ_V1_8821C 0
+#define BIT_MASK_LPQ_V1_8821C 0xfff
+#define BIT_LPQ_V1_8821C(x)                                                    \
+	(((x) & BIT_MASK_LPQ_V1_8821C) << BIT_SHIFT_LPQ_V1_8821C)
+#define BITS_LPQ_V1_8821C (BIT_MASK_LPQ_V1_8821C << BIT_SHIFT_LPQ_V1_8821C)
+#define BIT_CLEAR_LPQ_V1_8821C(x) ((x) & (~BITS_LPQ_V1_8821C))
+#define BIT_GET_LPQ_V1_8821C(x)                                                \
+	(((x) >> BIT_SHIFT_LPQ_V1_8821C) & BIT_MASK_LPQ_V1_8821C)
+#define BIT_SET_LPQ_V1_8821C(x, v)                                             \
+	(BIT_CLEAR_LPQ_V1_8821C(x) | BIT_LPQ_V1_8821C(v))
+
+/* 2 REG_FIFOPAGE_INFO_3_8821C */
+
+#define BIT_SHIFT_NPQ_AVAL_PG_V1_8821C 16
+#define BIT_MASK_NPQ_AVAL_PG_V1_8821C 0xfff
+#define BIT_NPQ_AVAL_PG_V1_8821C(x)                                            \
+	(((x) & BIT_MASK_NPQ_AVAL_PG_V1_8821C)                                 \
+	 << BIT_SHIFT_NPQ_AVAL_PG_V1_8821C)
+#define BITS_NPQ_AVAL_PG_V1_8821C                                              \
+	(BIT_MASK_NPQ_AVAL_PG_V1_8821C << BIT_SHIFT_NPQ_AVAL_PG_V1_8821C)
+#define BIT_CLEAR_NPQ_AVAL_PG_V1_8821C(x) ((x) & (~BITS_NPQ_AVAL_PG_V1_8821C))
+#define BIT_GET_NPQ_AVAL_PG_V1_8821C(x)                                        \
+	(((x) >> BIT_SHIFT_NPQ_AVAL_PG_V1_8821C) &                             \
+	 BIT_MASK_NPQ_AVAL_PG_V1_8821C)
+#define BIT_SET_NPQ_AVAL_PG_V1_8821C(x, v)                                     \
+	(BIT_CLEAR_NPQ_AVAL_PG_V1_8821C(x) | BIT_NPQ_AVAL_PG_V1_8821C(v))
+
+#define BIT_SHIFT_NPQ_V1_8821C 0
+#define BIT_MASK_NPQ_V1_8821C 0xfff
+#define BIT_NPQ_V1_8821C(x)                                                    \
+	(((x) & BIT_MASK_NPQ_V1_8821C) << BIT_SHIFT_NPQ_V1_8821C)
+#define BITS_NPQ_V1_8821C (BIT_MASK_NPQ_V1_8821C << BIT_SHIFT_NPQ_V1_8821C)
+#define BIT_CLEAR_NPQ_V1_8821C(x) ((x) & (~BITS_NPQ_V1_8821C))
+#define BIT_GET_NPQ_V1_8821C(x)                                                \
+	(((x) >> BIT_SHIFT_NPQ_V1_8821C) & BIT_MASK_NPQ_V1_8821C)
+#define BIT_SET_NPQ_V1_8821C(x, v)                                             \
+	(BIT_CLEAR_NPQ_V1_8821C(x) | BIT_NPQ_V1_8821C(v))
+
+/* 2 REG_FIFOPAGE_INFO_4_8821C */
+
+#define BIT_SHIFT_EXQ_AVAL_PG_V1_8821C 16
+#define BIT_MASK_EXQ_AVAL_PG_V1_8821C 0xfff
+#define BIT_EXQ_AVAL_PG_V1_8821C(x)                                            \
+	(((x) & BIT_MASK_EXQ_AVAL_PG_V1_8821C)                                 \
+	 << BIT_SHIFT_EXQ_AVAL_PG_V1_8821C)
+#define BITS_EXQ_AVAL_PG_V1_8821C                                              \
+	(BIT_MASK_EXQ_AVAL_PG_V1_8821C << BIT_SHIFT_EXQ_AVAL_PG_V1_8821C)
+#define BIT_CLEAR_EXQ_AVAL_PG_V1_8821C(x) ((x) & (~BITS_EXQ_AVAL_PG_V1_8821C))
+#define BIT_GET_EXQ_AVAL_PG_V1_8821C(x)                                        \
+	(((x) >> BIT_SHIFT_EXQ_AVAL_PG_V1_8821C) &                             \
+	 BIT_MASK_EXQ_AVAL_PG_V1_8821C)
+#define BIT_SET_EXQ_AVAL_PG_V1_8821C(x, v)                                     \
+	(BIT_CLEAR_EXQ_AVAL_PG_V1_8821C(x) | BIT_EXQ_AVAL_PG_V1_8821C(v))
+
+#define BIT_SHIFT_EXQ_V1_8821C 0
+#define BIT_MASK_EXQ_V1_8821C 0xfff
+#define BIT_EXQ_V1_8821C(x)                                                    \
+	(((x) & BIT_MASK_EXQ_V1_8821C) << BIT_SHIFT_EXQ_V1_8821C)
+#define BITS_EXQ_V1_8821C (BIT_MASK_EXQ_V1_8821C << BIT_SHIFT_EXQ_V1_8821C)
+#define BIT_CLEAR_EXQ_V1_8821C(x) ((x) & (~BITS_EXQ_V1_8821C))
+#define BIT_GET_EXQ_V1_8821C(x)                                                \
+	(((x) >> BIT_SHIFT_EXQ_V1_8821C) & BIT_MASK_EXQ_V1_8821C)
+#define BIT_SET_EXQ_V1_8821C(x, v)                                             \
+	(BIT_CLEAR_EXQ_V1_8821C(x) | BIT_EXQ_V1_8821C(v))
+
+/* 2 REG_FIFOPAGE_INFO_5_8821C */
+
+#define BIT_SHIFT_PUBQ_AVAL_PG_V1_8821C 16
+#define BIT_MASK_PUBQ_AVAL_PG_V1_8821C 0xfff
+#define BIT_PUBQ_AVAL_PG_V1_8821C(x)                                           \
+	(((x) & BIT_MASK_PUBQ_AVAL_PG_V1_8821C)                                \
+	 << BIT_SHIFT_PUBQ_AVAL_PG_V1_8821C)
+#define BITS_PUBQ_AVAL_PG_V1_8821C                                             \
+	(BIT_MASK_PUBQ_AVAL_PG_V1_8821C << BIT_SHIFT_PUBQ_AVAL_PG_V1_8821C)
+#define BIT_CLEAR_PUBQ_AVAL_PG_V1_8821C(x) ((x) & (~BITS_PUBQ_AVAL_PG_V1_8821C))
+#define BIT_GET_PUBQ_AVAL_PG_V1_8821C(x)                                       \
+	(((x) >> BIT_SHIFT_PUBQ_AVAL_PG_V1_8821C) &                            \
+	 BIT_MASK_PUBQ_AVAL_PG_V1_8821C)
+#define BIT_SET_PUBQ_AVAL_PG_V1_8821C(x, v)                                    \
+	(BIT_CLEAR_PUBQ_AVAL_PG_V1_8821C(x) | BIT_PUBQ_AVAL_PG_V1_8821C(v))
+
+#define BIT_SHIFT_PUBQ_V1_8821C 0
+#define BIT_MASK_PUBQ_V1_8821C 0xfff
+#define BIT_PUBQ_V1_8821C(x)                                                   \
+	(((x) & BIT_MASK_PUBQ_V1_8821C) << BIT_SHIFT_PUBQ_V1_8821C)
+#define BITS_PUBQ_V1_8821C (BIT_MASK_PUBQ_V1_8821C << BIT_SHIFT_PUBQ_V1_8821C)
+#define BIT_CLEAR_PUBQ_V1_8821C(x) ((x) & (~BITS_PUBQ_V1_8821C))
+#define BIT_GET_PUBQ_V1_8821C(x)                                               \
+	(((x) >> BIT_SHIFT_PUBQ_V1_8821C) & BIT_MASK_PUBQ_V1_8821C)
+#define BIT_SET_PUBQ_V1_8821C(x, v)                                            \
+	(BIT_CLEAR_PUBQ_V1_8821C(x) | BIT_PUBQ_V1_8821C(v))
+
+/* 2 REG_H2C_HEAD_8821C */
+
+#define BIT_SHIFT_H2C_HEAD_8821C 0
+#define BIT_MASK_H2C_HEAD_8821C 0x3ffff
+#define BIT_H2C_HEAD_8821C(x)                                                  \
+	(((x) & BIT_MASK_H2C_HEAD_8821C) << BIT_SHIFT_H2C_HEAD_8821C)
+#define BITS_H2C_HEAD_8821C                                                    \
+	(BIT_MASK_H2C_HEAD_8821C << BIT_SHIFT_H2C_HEAD_8821C)
+#define BIT_CLEAR_H2C_HEAD_8821C(x) ((x) & (~BITS_H2C_HEAD_8821C))
+#define BIT_GET_H2C_HEAD_8821C(x)                                              \
+	(((x) >> BIT_SHIFT_H2C_HEAD_8821C) & BIT_MASK_H2C_HEAD_8821C)
+#define BIT_SET_H2C_HEAD_8821C(x, v)                                           \
+	(BIT_CLEAR_H2C_HEAD_8821C(x) | BIT_H2C_HEAD_8821C(v))
+
+/* 2 REG_H2C_TAIL_8821C */
+
+#define BIT_SHIFT_H2C_TAIL_8821C 0
+#define BIT_MASK_H2C_TAIL_8821C 0x3ffff
+#define BIT_H2C_TAIL_8821C(x)                                                  \
+	(((x) & BIT_MASK_H2C_TAIL_8821C) << BIT_SHIFT_H2C_TAIL_8821C)
+#define BITS_H2C_TAIL_8821C                                                    \
+	(BIT_MASK_H2C_TAIL_8821C << BIT_SHIFT_H2C_TAIL_8821C)
+#define BIT_CLEAR_H2C_TAIL_8821C(x) ((x) & (~BITS_H2C_TAIL_8821C))
+#define BIT_GET_H2C_TAIL_8821C(x)                                              \
+	(((x) >> BIT_SHIFT_H2C_TAIL_8821C) & BIT_MASK_H2C_TAIL_8821C)
+#define BIT_SET_H2C_TAIL_8821C(x, v)                                           \
+	(BIT_CLEAR_H2C_TAIL_8821C(x) | BIT_H2C_TAIL_8821C(v))
+
+/* 2 REG_H2C_READ_ADDR_8821C */
+
+#define BIT_SHIFT_H2C_READ_ADDR_8821C 0
+#define BIT_MASK_H2C_READ_ADDR_8821C 0x3ffff
+#define BIT_H2C_READ_ADDR_8821C(x)                                             \
+	(((x) & BIT_MASK_H2C_READ_ADDR_8821C) << BIT_SHIFT_H2C_READ_ADDR_8821C)
+#define BITS_H2C_READ_ADDR_8821C                                               \
+	(BIT_MASK_H2C_READ_ADDR_8821C << BIT_SHIFT_H2C_READ_ADDR_8821C)
+#define BIT_CLEAR_H2C_READ_ADDR_8821C(x) ((x) & (~BITS_H2C_READ_ADDR_8821C))
+#define BIT_GET_H2C_READ_ADDR_8821C(x)                                         \
+	(((x) >> BIT_SHIFT_H2C_READ_ADDR_8821C) & BIT_MASK_H2C_READ_ADDR_8821C)
+#define BIT_SET_H2C_READ_ADDR_8821C(x, v)                                      \
+	(BIT_CLEAR_H2C_READ_ADDR_8821C(x) | BIT_H2C_READ_ADDR_8821C(v))
+
+/* 2 REG_H2C_WR_ADDR_8821C */
+
+#define BIT_SHIFT_H2C_WR_ADDR_8821C 0
+#define BIT_MASK_H2C_WR_ADDR_8821C 0x3ffff
+#define BIT_H2C_WR_ADDR_8821C(x)                                               \
+	(((x) & BIT_MASK_H2C_WR_ADDR_8821C) << BIT_SHIFT_H2C_WR_ADDR_8821C)
+#define BITS_H2C_WR_ADDR_8821C                                                 \
+	(BIT_MASK_H2C_WR_ADDR_8821C << BIT_SHIFT_H2C_WR_ADDR_8821C)
+#define BIT_CLEAR_H2C_WR_ADDR_8821C(x) ((x) & (~BITS_H2C_WR_ADDR_8821C))
+#define BIT_GET_H2C_WR_ADDR_8821C(x)                                           \
+	(((x) >> BIT_SHIFT_H2C_WR_ADDR_8821C) & BIT_MASK_H2C_WR_ADDR_8821C)
+#define BIT_SET_H2C_WR_ADDR_8821C(x, v)                                        \
+	(BIT_CLEAR_H2C_WR_ADDR_8821C(x) | BIT_H2C_WR_ADDR_8821C(v))
+
+/* 2 REG_H2C_INFO_8821C */
+#define BIT_H2C_SPACE_VLD_8821C BIT(3)
+#define BIT_H2C_WR_ADDR_RST_8821C BIT(2)
+
+#define BIT_SHIFT_H2C_LEN_SEL_8821C 0
+#define BIT_MASK_H2C_LEN_SEL_8821C 0x3
+#define BIT_H2C_LEN_SEL_8821C(x)                                               \
+	(((x) & BIT_MASK_H2C_LEN_SEL_8821C) << BIT_SHIFT_H2C_LEN_SEL_8821C)
+#define BITS_H2C_LEN_SEL_8821C                                                 \
+	(BIT_MASK_H2C_LEN_SEL_8821C << BIT_SHIFT_H2C_LEN_SEL_8821C)
+#define BIT_CLEAR_H2C_LEN_SEL_8821C(x) ((x) & (~BITS_H2C_LEN_SEL_8821C))
+#define BIT_GET_H2C_LEN_SEL_8821C(x)                                           \
+	(((x) >> BIT_SHIFT_H2C_LEN_SEL_8821C) & BIT_MASK_H2C_LEN_SEL_8821C)
+#define BIT_SET_H2C_LEN_SEL_8821C(x, v)                                        \
+	(BIT_CLEAR_H2C_LEN_SEL_8821C(x) | BIT_H2C_LEN_SEL_8821C(v))
+
+/* 2 REG_RXDMA_AGG_PG_TH_8821C */
+#define BIT_USB_RXDMA_AGG_EN_8821C BIT(31)
+#define BIT_EN_PRE_CALC_8821C BIT(29)
+#define BIT_RXAGG_SW_EN_8821C BIT(28)
+#define BIT_RXAGG_SW_TRIG_8821C BIT(27)
+
+/* 2 REG_NOT_VALID_8821C */
+
+#define BIT_SHIFT_PKT_NUM_WOL_8821C 16
+#define BIT_MASK_PKT_NUM_WOL_8821C 0xff
+#define BIT_PKT_NUM_WOL_8821C(x)                                               \
+	(((x) & BIT_MASK_PKT_NUM_WOL_8821C) << BIT_SHIFT_PKT_NUM_WOL_8821C)
+#define BITS_PKT_NUM_WOL_8821C                                                 \
+	(BIT_MASK_PKT_NUM_WOL_8821C << BIT_SHIFT_PKT_NUM_WOL_8821C)
+#define BIT_CLEAR_PKT_NUM_WOL_8821C(x) ((x) & (~BITS_PKT_NUM_WOL_8821C))
+#define BIT_GET_PKT_NUM_WOL_8821C(x)                                           \
+	(((x) >> BIT_SHIFT_PKT_NUM_WOL_8821C) & BIT_MASK_PKT_NUM_WOL_8821C)
+#define BIT_SET_PKT_NUM_WOL_8821C(x, v)                                        \
+	(BIT_CLEAR_PKT_NUM_WOL_8821C(x) | BIT_PKT_NUM_WOL_8821C(v))
+
+#define BIT_SHIFT_DMA_AGG_TO_V1_8821C 8
+#define BIT_MASK_DMA_AGG_TO_V1_8821C 0xff
+#define BIT_DMA_AGG_TO_V1_8821C(x)                                             \
+	(((x) & BIT_MASK_DMA_AGG_TO_V1_8821C) << BIT_SHIFT_DMA_AGG_TO_V1_8821C)
+#define BITS_DMA_AGG_TO_V1_8821C                                               \
+	(BIT_MASK_DMA_AGG_TO_V1_8821C << BIT_SHIFT_DMA_AGG_TO_V1_8821C)
+#define BIT_CLEAR_DMA_AGG_TO_V1_8821C(x) ((x) & (~BITS_DMA_AGG_TO_V1_8821C))
+#define BIT_GET_DMA_AGG_TO_V1_8821C(x)                                         \
+	(((x) >> BIT_SHIFT_DMA_AGG_TO_V1_8821C) & BIT_MASK_DMA_AGG_TO_V1_8821C)
+#define BIT_SET_DMA_AGG_TO_V1_8821C(x, v)                                      \
+	(BIT_CLEAR_DMA_AGG_TO_V1_8821C(x) | BIT_DMA_AGG_TO_V1_8821C(v))
+
+#define BIT_SHIFT_RXDMA_AGG_PG_TH_8821C 0
+#define BIT_MASK_RXDMA_AGG_PG_TH_8821C 0xff
+#define BIT_RXDMA_AGG_PG_TH_8821C(x)                                           \
+	(((x) & BIT_MASK_RXDMA_AGG_PG_TH_8821C)                                \
+	 << BIT_SHIFT_RXDMA_AGG_PG_TH_8821C)
+#define BITS_RXDMA_AGG_PG_TH_8821C                                             \
+	(BIT_MASK_RXDMA_AGG_PG_TH_8821C << BIT_SHIFT_RXDMA_AGG_PG_TH_8821C)
+#define BIT_CLEAR_RXDMA_AGG_PG_TH_8821C(x) ((x) & (~BITS_RXDMA_AGG_PG_TH_8821C))
+#define BIT_GET_RXDMA_AGG_PG_TH_8821C(x)                                       \
+	(((x) >> BIT_SHIFT_RXDMA_AGG_PG_TH_8821C) &                            \
+	 BIT_MASK_RXDMA_AGG_PG_TH_8821C)
+#define BIT_SET_RXDMA_AGG_PG_TH_8821C(x, v)                                    \
+	(BIT_CLEAR_RXDMA_AGG_PG_TH_8821C(x) | BIT_RXDMA_AGG_PG_TH_8821C(v))
+
+/* 2 REG_RXPKT_NUM_8821C */
+
+#define BIT_SHIFT_RXPKT_NUM_8821C 24
+#define BIT_MASK_RXPKT_NUM_8821C 0xff
+#define BIT_RXPKT_NUM_8821C(x)                                                 \
+	(((x) & BIT_MASK_RXPKT_NUM_8821C) << BIT_SHIFT_RXPKT_NUM_8821C)
+#define BITS_RXPKT_NUM_8821C                                                   \
+	(BIT_MASK_RXPKT_NUM_8821C << BIT_SHIFT_RXPKT_NUM_8821C)
+#define BIT_CLEAR_RXPKT_NUM_8821C(x) ((x) & (~BITS_RXPKT_NUM_8821C))
+#define BIT_GET_RXPKT_NUM_8821C(x)                                             \
+	(((x) >> BIT_SHIFT_RXPKT_NUM_8821C) & BIT_MASK_RXPKT_NUM_8821C)
+#define BIT_SET_RXPKT_NUM_8821C(x, v)                                          \
+	(BIT_CLEAR_RXPKT_NUM_8821C(x) | BIT_RXPKT_NUM_8821C(v))
+
+#define BIT_SHIFT_FW_UPD_RDPTR19_TO_16_8821C 20
+#define BIT_MASK_FW_UPD_RDPTR19_TO_16_8821C 0xf
+#define BIT_FW_UPD_RDPTR19_TO_16_8821C(x)                                      \
+	(((x) & BIT_MASK_FW_UPD_RDPTR19_TO_16_8821C)                           \
+	 << BIT_SHIFT_FW_UPD_RDPTR19_TO_16_8821C)
+#define BITS_FW_UPD_RDPTR19_TO_16_8821C                                        \
+	(BIT_MASK_FW_UPD_RDPTR19_TO_16_8821C                                   \
+	 << BIT_SHIFT_FW_UPD_RDPTR19_TO_16_8821C)
+#define BIT_CLEAR_FW_UPD_RDPTR19_TO_16_8821C(x)                                \
+	((x) & (~BITS_FW_UPD_RDPTR19_TO_16_8821C))
+#define BIT_GET_FW_UPD_RDPTR19_TO_16_8821C(x)                                  \
+	(((x) >> BIT_SHIFT_FW_UPD_RDPTR19_TO_16_8821C) &                       \
+	 BIT_MASK_FW_UPD_RDPTR19_TO_16_8821C)
+#define BIT_SET_FW_UPD_RDPTR19_TO_16_8821C(x, v)                               \
+	(BIT_CLEAR_FW_UPD_RDPTR19_TO_16_8821C(x) |                             \
+	 BIT_FW_UPD_RDPTR19_TO_16_8821C(v))
+
+#define BIT_RXDMA_REQ_8821C BIT(19)
+#define BIT_RW_RELEASE_EN_8821C BIT(18)
+#define BIT_RXDMA_IDLE_8821C BIT(17)
+#define BIT_RXPKT_RELEASE_POLL_8821C BIT(16)
+
+#define BIT_SHIFT_FW_UPD_RDPTR_8821C 0
+#define BIT_MASK_FW_UPD_RDPTR_8821C 0xffff
+#define BIT_FW_UPD_RDPTR_8821C(x)                                              \
+	(((x) & BIT_MASK_FW_UPD_RDPTR_8821C) << BIT_SHIFT_FW_UPD_RDPTR_8821C)
+#define BITS_FW_UPD_RDPTR_8821C                                                \
+	(BIT_MASK_FW_UPD_RDPTR_8821C << BIT_SHIFT_FW_UPD_RDPTR_8821C)
+#define BIT_CLEAR_FW_UPD_RDPTR_8821C(x) ((x) & (~BITS_FW_UPD_RDPTR_8821C))
+#define BIT_GET_FW_UPD_RDPTR_8821C(x)                                          \
+	(((x) >> BIT_SHIFT_FW_UPD_RDPTR_8821C) & BIT_MASK_FW_UPD_RDPTR_8821C)
+#define BIT_SET_FW_UPD_RDPTR_8821C(x, v)                                       \
+	(BIT_CLEAR_FW_UPD_RDPTR_8821C(x) | BIT_FW_UPD_RDPTR_8821C(v))
+
+/* 2 REG_RXDMA_STATUS_8821C */
+#define BIT_C2H_PKT_OVF_8821C BIT(7)
+#define BIT_AGG_CONFGI_ISSUE_8821C BIT(6)
+#define BIT_FW_POLL_ISSUE_8821C BIT(5)
+#define BIT_RX_DATA_UDN_8821C BIT(4)
+#define BIT_RX_SFF_UDN_8821C BIT(3)
+#define BIT_RX_SFF_OVF_8821C BIT(2)
+#define BIT_RXPKT_OVF_8821C BIT(0)
+
+/* 2 REG_RXDMA_DPR_8821C */
+
+#define BIT_SHIFT_RDE_DEBUG_8821C 0
+#define BIT_MASK_RDE_DEBUG_8821C 0xffffffffL
+#define BIT_RDE_DEBUG_8821C(x)                                                 \
+	(((x) & BIT_MASK_RDE_DEBUG_8821C) << BIT_SHIFT_RDE_DEBUG_8821C)
+#define BITS_RDE_DEBUG_8821C                                                   \
+	(BIT_MASK_RDE_DEBUG_8821C << BIT_SHIFT_RDE_DEBUG_8821C)
+#define BIT_CLEAR_RDE_DEBUG_8821C(x) ((x) & (~BITS_RDE_DEBUG_8821C))
+#define BIT_GET_RDE_DEBUG_8821C(x)                                             \
+	(((x) >> BIT_SHIFT_RDE_DEBUG_8821C) & BIT_MASK_RDE_DEBUG_8821C)
+#define BIT_SET_RDE_DEBUG_8821C(x, v)                                          \
+	(BIT_CLEAR_RDE_DEBUG_8821C(x) | BIT_RDE_DEBUG_8821C(v))
+
+/* 2 REG_RXDMA_MODE_8821C */
+
+#define BIT_SHIFT_PKTNUM_TH_V2_8821C 24
+#define BIT_MASK_PKTNUM_TH_V2_8821C 0x1f
+#define BIT_PKTNUM_TH_V2_8821C(x)                                              \
+	(((x) & BIT_MASK_PKTNUM_TH_V2_8821C) << BIT_SHIFT_PKTNUM_TH_V2_8821C)
+#define BITS_PKTNUM_TH_V2_8821C                                                \
+	(BIT_MASK_PKTNUM_TH_V2_8821C << BIT_SHIFT_PKTNUM_TH_V2_8821C)
+#define BIT_CLEAR_PKTNUM_TH_V2_8821C(x) ((x) & (~BITS_PKTNUM_TH_V2_8821C))
+#define BIT_GET_PKTNUM_TH_V2_8821C(x)                                          \
+	(((x) >> BIT_SHIFT_PKTNUM_TH_V2_8821C) & BIT_MASK_PKTNUM_TH_V2_8821C)
+#define BIT_SET_PKTNUM_TH_V2_8821C(x, v)                                       \
+	(BIT_CLEAR_PKTNUM_TH_V2_8821C(x) | BIT_PKTNUM_TH_V2_8821C(v))
+
+#define BIT_TXBA_BREAK_USBAGG_8821C BIT(23)
+
+#define BIT_SHIFT_PKTLEN_PARA_8821C 16
+#define BIT_MASK_PKTLEN_PARA_8821C 0x7
+#define BIT_PKTLEN_PARA_8821C(x)                                               \
+	(((x) & BIT_MASK_PKTLEN_PARA_8821C) << BIT_SHIFT_PKTLEN_PARA_8821C)
+#define BITS_PKTLEN_PARA_8821C                                                 \
+	(BIT_MASK_PKTLEN_PARA_8821C << BIT_SHIFT_PKTLEN_PARA_8821C)
+#define BIT_CLEAR_PKTLEN_PARA_8821C(x) ((x) & (~BITS_PKTLEN_PARA_8821C))
+#define BIT_GET_PKTLEN_PARA_8821C(x)                                           \
+	(((x) >> BIT_SHIFT_PKTLEN_PARA_8821C) & BIT_MASK_PKTLEN_PARA_8821C)
+#define BIT_SET_PKTLEN_PARA_8821C(x, v)                                        \
+	(BIT_CLEAR_PKTLEN_PARA_8821C(x) | BIT_PKTLEN_PARA_8821C(v))
+
+#define BIT_SHIFT_BURST_SIZE_8821C 4
+#define BIT_MASK_BURST_SIZE_8821C 0x3
+#define BIT_BURST_SIZE_8821C(x)                                                \
+	(((x) & BIT_MASK_BURST_SIZE_8821C) << BIT_SHIFT_BURST_SIZE_8821C)
+#define BITS_BURST_SIZE_8821C                                                  \
+	(BIT_MASK_BURST_SIZE_8821C << BIT_SHIFT_BURST_SIZE_8821C)
+#define BIT_CLEAR_BURST_SIZE_8821C(x) ((x) & (~BITS_BURST_SIZE_8821C))
+#define BIT_GET_BURST_SIZE_8821C(x)                                            \
+	(((x) >> BIT_SHIFT_BURST_SIZE_8821C) & BIT_MASK_BURST_SIZE_8821C)
+#define BIT_SET_BURST_SIZE_8821C(x, v)                                         \
+	(BIT_CLEAR_BURST_SIZE_8821C(x) | BIT_BURST_SIZE_8821C(v))
+
+#define BIT_SHIFT_BURST_CNT_8821C 2
+#define BIT_MASK_BURST_CNT_8821C 0x3
+#define BIT_BURST_CNT_8821C(x)                                                 \
+	(((x) & BIT_MASK_BURST_CNT_8821C) << BIT_SHIFT_BURST_CNT_8821C)
+#define BITS_BURST_CNT_8821C                                                   \
+	(BIT_MASK_BURST_CNT_8821C << BIT_SHIFT_BURST_CNT_8821C)
+#define BIT_CLEAR_BURST_CNT_8821C(x) ((x) & (~BITS_BURST_CNT_8821C))
+#define BIT_GET_BURST_CNT_8821C(x)                                             \
+	(((x) >> BIT_SHIFT_BURST_CNT_8821C) & BIT_MASK_BURST_CNT_8821C)
+#define BIT_SET_BURST_CNT_8821C(x, v)                                          \
+	(BIT_CLEAR_BURST_CNT_8821C(x) | BIT_BURST_CNT_8821C(v))
+
+#define BIT_DMA_MODE_8821C BIT(1)
+
+/* 2 REG_C2H_PKT_8821C */
+
+#define BIT_SHIFT_R_C2H_STR_ADDR_16_TO_19_8821C 24
+#define BIT_MASK_R_C2H_STR_ADDR_16_TO_19_8821C 0xf
+#define BIT_R_C2H_STR_ADDR_16_TO_19_8821C(x)                                   \
+	(((x) & BIT_MASK_R_C2H_STR_ADDR_16_TO_19_8821C)                        \
+	 << BIT_SHIFT_R_C2H_STR_ADDR_16_TO_19_8821C)
+#define BITS_R_C2H_STR_ADDR_16_TO_19_8821C                                     \
+	(BIT_MASK_R_C2H_STR_ADDR_16_TO_19_8821C                                \
+	 << BIT_SHIFT_R_C2H_STR_ADDR_16_TO_19_8821C)
+#define BIT_CLEAR_R_C2H_STR_ADDR_16_TO_19_8821C(x)                             \
+	((x) & (~BITS_R_C2H_STR_ADDR_16_TO_19_8821C))
+#define BIT_GET_R_C2H_STR_ADDR_16_TO_19_8821C(x)                               \
+	(((x) >> BIT_SHIFT_R_C2H_STR_ADDR_16_TO_19_8821C) &                    \
+	 BIT_MASK_R_C2H_STR_ADDR_16_TO_19_8821C)
+#define BIT_SET_R_C2H_STR_ADDR_16_TO_19_8821C(x, v)                            \
+	(BIT_CLEAR_R_C2H_STR_ADDR_16_TO_19_8821C(x) |                          \
+	 BIT_R_C2H_STR_ADDR_16_TO_19_8821C(v))
+
+#define BIT_R_C2H_PKT_REQ_8821C BIT(16)
+
+#define BIT_SHIFT_R_C2H_STR_ADDR_8821C 0
+#define BIT_MASK_R_C2H_STR_ADDR_8821C 0xffff
+#define BIT_R_C2H_STR_ADDR_8821C(x)                                            \
+	(((x) & BIT_MASK_R_C2H_STR_ADDR_8821C)                                 \
+	 << BIT_SHIFT_R_C2H_STR_ADDR_8821C)
+#define BITS_R_C2H_STR_ADDR_8821C                                              \
+	(BIT_MASK_R_C2H_STR_ADDR_8821C << BIT_SHIFT_R_C2H_STR_ADDR_8821C)
+#define BIT_CLEAR_R_C2H_STR_ADDR_8821C(x) ((x) & (~BITS_R_C2H_STR_ADDR_8821C))
+#define BIT_GET_R_C2H_STR_ADDR_8821C(x)                                        \
+	(((x) >> BIT_SHIFT_R_C2H_STR_ADDR_8821C) &                             \
+	 BIT_MASK_R_C2H_STR_ADDR_8821C)
+#define BIT_SET_R_C2H_STR_ADDR_8821C(x, v)                                     \
+	(BIT_CLEAR_R_C2H_STR_ADDR_8821C(x) | BIT_R_C2H_STR_ADDR_8821C(v))
+
+/* 2 REG_FWFF_C2H_8821C */
+
+#define BIT_SHIFT_C2H_DMA_ADDR_8821C 0
+#define BIT_MASK_C2H_DMA_ADDR_8821C 0x3ffff
+#define BIT_C2H_DMA_ADDR_8821C(x)                                              \
+	(((x) & BIT_MASK_C2H_DMA_ADDR_8821C) << BIT_SHIFT_C2H_DMA_ADDR_8821C)
+#define BITS_C2H_DMA_ADDR_8821C                                                \
+	(BIT_MASK_C2H_DMA_ADDR_8821C << BIT_SHIFT_C2H_DMA_ADDR_8821C)
+#define BIT_CLEAR_C2H_DMA_ADDR_8821C(x) ((x) & (~BITS_C2H_DMA_ADDR_8821C))
+#define BIT_GET_C2H_DMA_ADDR_8821C(x)                                          \
+	(((x) >> BIT_SHIFT_C2H_DMA_ADDR_8821C) & BIT_MASK_C2H_DMA_ADDR_8821C)
+#define BIT_SET_C2H_DMA_ADDR_8821C(x, v)                                       \
+	(BIT_CLEAR_C2H_DMA_ADDR_8821C(x) | BIT_C2H_DMA_ADDR_8821C(v))
+
+/* 2 REG_FWFF_CTRL_8821C */
+#define BIT_FWFF_DMAPKT_REQ_8821C BIT(31)
+
+#define BIT_SHIFT_FWFF_DMA_PKT_NUM_8821C 16
+#define BIT_MASK_FWFF_DMA_PKT_NUM_8821C 0xff
+#define BIT_FWFF_DMA_PKT_NUM_8821C(x)                                          \
+	(((x) & BIT_MASK_FWFF_DMA_PKT_NUM_8821C)                               \
+	 << BIT_SHIFT_FWFF_DMA_PKT_NUM_8821C)
+#define BITS_FWFF_DMA_PKT_NUM_8821C                                            \
+	(BIT_MASK_FWFF_DMA_PKT_NUM_8821C << BIT_SHIFT_FWFF_DMA_PKT_NUM_8821C)
+#define BIT_CLEAR_FWFF_DMA_PKT_NUM_8821C(x)                                    \
+	((x) & (~BITS_FWFF_DMA_PKT_NUM_8821C))
+#define BIT_GET_FWFF_DMA_PKT_NUM_8821C(x)                                      \
+	(((x) >> BIT_SHIFT_FWFF_DMA_PKT_NUM_8821C) &                           \
+	 BIT_MASK_FWFF_DMA_PKT_NUM_8821C)
+#define BIT_SET_FWFF_DMA_PKT_NUM_8821C(x, v)                                   \
+	(BIT_CLEAR_FWFF_DMA_PKT_NUM_8821C(x) | BIT_FWFF_DMA_PKT_NUM_8821C(v))
+
+#define BIT_SHIFT_FWFF_STR_ADDR_8821C 0
+#define BIT_MASK_FWFF_STR_ADDR_8821C 0xffff
+#define BIT_FWFF_STR_ADDR_8821C(x)                                             \
+	(((x) & BIT_MASK_FWFF_STR_ADDR_8821C) << BIT_SHIFT_FWFF_STR_ADDR_8821C)
+#define BITS_FWFF_STR_ADDR_8821C                                               \
+	(BIT_MASK_FWFF_STR_ADDR_8821C << BIT_SHIFT_FWFF_STR_ADDR_8821C)
+#define BIT_CLEAR_FWFF_STR_ADDR_8821C(x) ((x) & (~BITS_FWFF_STR_ADDR_8821C))
+#define BIT_GET_FWFF_STR_ADDR_8821C(x)                                         \
+	(((x) >> BIT_SHIFT_FWFF_STR_ADDR_8821C) & BIT_MASK_FWFF_STR_ADDR_8821C)
+#define BIT_SET_FWFF_STR_ADDR_8821C(x, v)                                      \
+	(BIT_CLEAR_FWFF_STR_ADDR_8821C(x) | BIT_FWFF_STR_ADDR_8821C(v))
+
+/* 2 REG_FWFF_PKT_INFO_8821C */
+
+#define BIT_SHIFT_FWFF_PKT_QUEUED_8821C 16
+#define BIT_MASK_FWFF_PKT_QUEUED_8821C 0xff
+#define BIT_FWFF_PKT_QUEUED_8821C(x)                                           \
+	(((x) & BIT_MASK_FWFF_PKT_QUEUED_8821C)                                \
+	 << BIT_SHIFT_FWFF_PKT_QUEUED_8821C)
+#define BITS_FWFF_PKT_QUEUED_8821C                                             \
+	(BIT_MASK_FWFF_PKT_QUEUED_8821C << BIT_SHIFT_FWFF_PKT_QUEUED_8821C)
+#define BIT_CLEAR_FWFF_PKT_QUEUED_8821C(x) ((x) & (~BITS_FWFF_PKT_QUEUED_8821C))
+#define BIT_GET_FWFF_PKT_QUEUED_8821C(x)                                       \
+	(((x) >> BIT_SHIFT_FWFF_PKT_QUEUED_8821C) &                            \
+	 BIT_MASK_FWFF_PKT_QUEUED_8821C)
+#define BIT_SET_FWFF_PKT_QUEUED_8821C(x, v)                                    \
+	(BIT_CLEAR_FWFF_PKT_QUEUED_8821C(x) | BIT_FWFF_PKT_QUEUED_8821C(v))
+
+#define BIT_SHIFT_FWFF_PKT_STR_ADDR_8821C 0
+#define BIT_MASK_FWFF_PKT_STR_ADDR_8821C 0xffff
+#define BIT_FWFF_PKT_STR_ADDR_8821C(x)                                         \
+	(((x) & BIT_MASK_FWFF_PKT_STR_ADDR_8821C)                              \
+	 << BIT_SHIFT_FWFF_PKT_STR_ADDR_8821C)
+#define BITS_FWFF_PKT_STR_ADDR_8821C                                           \
+	(BIT_MASK_FWFF_PKT_STR_ADDR_8821C << BIT_SHIFT_FWFF_PKT_STR_ADDR_8821C)
+#define BIT_CLEAR_FWFF_PKT_STR_ADDR_8821C(x)                                   \
+	((x) & (~BITS_FWFF_PKT_STR_ADDR_8821C))
+#define BIT_GET_FWFF_PKT_STR_ADDR_8821C(x)                                     \
+	(((x) >> BIT_SHIFT_FWFF_PKT_STR_ADDR_8821C) &                          \
+	 BIT_MASK_FWFF_PKT_STR_ADDR_8821C)
+#define BIT_SET_FWFF_PKT_STR_ADDR_8821C(x, v)                                  \
+	(BIT_CLEAR_FWFF_PKT_STR_ADDR_8821C(x) | BIT_FWFF_PKT_STR_ADDR_8821C(v))
+
+/* 2 REG_DDMA_CH0SA_8821C */
+
+#define BIT_SHIFT_DDMACH0_SA_8821C 0
+#define BIT_MASK_DDMACH0_SA_8821C 0xffffffffL
+#define BIT_DDMACH0_SA_8821C(x)                                                \
+	(((x) & BIT_MASK_DDMACH0_SA_8821C) << BIT_SHIFT_DDMACH0_SA_8821C)
+#define BITS_DDMACH0_SA_8821C                                                  \
+	(BIT_MASK_DDMACH0_SA_8821C << BIT_SHIFT_DDMACH0_SA_8821C)
+#define BIT_CLEAR_DDMACH0_SA_8821C(x) ((x) & (~BITS_DDMACH0_SA_8821C))
+#define BIT_GET_DDMACH0_SA_8821C(x)                                            \
+	(((x) >> BIT_SHIFT_DDMACH0_SA_8821C) & BIT_MASK_DDMACH0_SA_8821C)
+#define BIT_SET_DDMACH0_SA_8821C(x, v)                                         \
+	(BIT_CLEAR_DDMACH0_SA_8821C(x) | BIT_DDMACH0_SA_8821C(v))
+
+/* 2 REG_DDMA_CH0DA_8821C */
+
+#define BIT_SHIFT_DDMACH0_DA_8821C 0
+#define BIT_MASK_DDMACH0_DA_8821C 0xffffffffL
+#define BIT_DDMACH0_DA_8821C(x)                                                \
+	(((x) & BIT_MASK_DDMACH0_DA_8821C) << BIT_SHIFT_DDMACH0_DA_8821C)
+#define BITS_DDMACH0_DA_8821C                                                  \
+	(BIT_MASK_DDMACH0_DA_8821C << BIT_SHIFT_DDMACH0_DA_8821C)
+#define BIT_CLEAR_DDMACH0_DA_8821C(x) ((x) & (~BITS_DDMACH0_DA_8821C))
+#define BIT_GET_DDMACH0_DA_8821C(x)                                            \
+	(((x) >> BIT_SHIFT_DDMACH0_DA_8821C) & BIT_MASK_DDMACH0_DA_8821C)
+#define BIT_SET_DDMACH0_DA_8821C(x, v)                                         \
+	(BIT_CLEAR_DDMACH0_DA_8821C(x) | BIT_DDMACH0_DA_8821C(v))
+
+/* 2 REG_DDMA_CH0CTRL_8821C */
+#define BIT_DDMACH0_OWN_8821C BIT(31)
+#define BIT_DDMACH0_IDMEM_ERR_8821C BIT(30)
+#define BIT_DDMACH0_CHKSUM_EN_8821C BIT(29)
+#define BIT_DDMACH0_DA_W_DISABLE_8821C BIT(28)
+#define BIT_DDMACH0_CHKSUM_STS_8821C BIT(27)
+#define BIT_DDMACH0_DDMA_MODE_8821C BIT(26)
+#define BIT_DDMACH0_RESET_CHKSUM_STS_8821C BIT(25)
+#define BIT_DDMACH0_CHKSUM_CONT_8821C BIT(24)
+
+#define BIT_SHIFT_DDMACH0_DLEN_8821C 0
+#define BIT_MASK_DDMACH0_DLEN_8821C 0x3ffff
+#define BIT_DDMACH0_DLEN_8821C(x)                                              \
+	(((x) & BIT_MASK_DDMACH0_DLEN_8821C) << BIT_SHIFT_DDMACH0_DLEN_8821C)
+#define BITS_DDMACH0_DLEN_8821C                                                \
+	(BIT_MASK_DDMACH0_DLEN_8821C << BIT_SHIFT_DDMACH0_DLEN_8821C)
+#define BIT_CLEAR_DDMACH0_DLEN_8821C(x) ((x) & (~BITS_DDMACH0_DLEN_8821C))
+#define BIT_GET_DDMACH0_DLEN_8821C(x)                                          \
+	(((x) >> BIT_SHIFT_DDMACH0_DLEN_8821C) & BIT_MASK_DDMACH0_DLEN_8821C)
+#define BIT_SET_DDMACH0_DLEN_8821C(x, v)                                       \
+	(BIT_CLEAR_DDMACH0_DLEN_8821C(x) | BIT_DDMACH0_DLEN_8821C(v))
+
+/* 2 REG_DDMA_CH1SA_8821C */
+
+#define BIT_SHIFT_DDMACH1_SA_8821C 0
+#define BIT_MASK_DDMACH1_SA_8821C 0xffffffffL
+#define BIT_DDMACH1_SA_8821C(x)                                                \
+	(((x) & BIT_MASK_DDMACH1_SA_8821C) << BIT_SHIFT_DDMACH1_SA_8821C)
+#define BITS_DDMACH1_SA_8821C                                                  \
+	(BIT_MASK_DDMACH1_SA_8821C << BIT_SHIFT_DDMACH1_SA_8821C)
+#define BIT_CLEAR_DDMACH1_SA_8821C(x) ((x) & (~BITS_DDMACH1_SA_8821C))
+#define BIT_GET_DDMACH1_SA_8821C(x)                                            \
+	(((x) >> BIT_SHIFT_DDMACH1_SA_8821C) & BIT_MASK_DDMACH1_SA_8821C)
+#define BIT_SET_DDMACH1_SA_8821C(x, v)                                         \
+	(BIT_CLEAR_DDMACH1_SA_8821C(x) | BIT_DDMACH1_SA_8821C(v))
+
+/* 2 REG_DDMA_CH1DA_8821C */
+
+#define BIT_SHIFT_DDMACH1_DA_8821C 0
+#define BIT_MASK_DDMACH1_DA_8821C 0xffffffffL
+#define BIT_DDMACH1_DA_8821C(x)                                                \
+	(((x) & BIT_MASK_DDMACH1_DA_8821C) << BIT_SHIFT_DDMACH1_DA_8821C)
+#define BITS_DDMACH1_DA_8821C                                                  \
+	(BIT_MASK_DDMACH1_DA_8821C << BIT_SHIFT_DDMACH1_DA_8821C)
+#define BIT_CLEAR_DDMACH1_DA_8821C(x) ((x) & (~BITS_DDMACH1_DA_8821C))
+#define BIT_GET_DDMACH1_DA_8821C(x)                                            \
+	(((x) >> BIT_SHIFT_DDMACH1_DA_8821C) & BIT_MASK_DDMACH1_DA_8821C)
+#define BIT_SET_DDMACH1_DA_8821C(x, v)                                         \
+	(BIT_CLEAR_DDMACH1_DA_8821C(x) | BIT_DDMACH1_DA_8821C(v))
+
+/* 2 REG_DDMA_CH1CTRL_8821C */
+#define BIT_DDMACH1_OWN_8821C BIT(31)
+#define BIT_DDMACH1_IDMEM_ERR_8821C BIT(30)
+#define BIT_DDMACH1_CHKSUM_EN_8821C BIT(29)
+#define BIT_DDMACH1_DA_W_DISABLE_8821C BIT(28)
+#define BIT_DDMACH1_CHKSUM_STS_8821C BIT(27)
+#define BIT_DDMACH1_DDMA_MODE_8821C BIT(26)
+#define BIT_DDMACH1_RESET_CHKSUM_STS_8821C BIT(25)
+#define BIT_DDMACH1_CHKSUM_CONT_8821C BIT(24)
+
+#define BIT_SHIFT_DDMACH1_DLEN_8821C 0
+#define BIT_MASK_DDMACH1_DLEN_8821C 0x3ffff
+#define BIT_DDMACH1_DLEN_8821C(x)                                              \
+	(((x) & BIT_MASK_DDMACH1_DLEN_8821C) << BIT_SHIFT_DDMACH1_DLEN_8821C)
+#define BITS_DDMACH1_DLEN_8821C                                                \
+	(BIT_MASK_DDMACH1_DLEN_8821C << BIT_SHIFT_DDMACH1_DLEN_8821C)
+#define BIT_CLEAR_DDMACH1_DLEN_8821C(x) ((x) & (~BITS_DDMACH1_DLEN_8821C))
+#define BIT_GET_DDMACH1_DLEN_8821C(x)                                          \
+	(((x) >> BIT_SHIFT_DDMACH1_DLEN_8821C) & BIT_MASK_DDMACH1_DLEN_8821C)
+#define BIT_SET_DDMACH1_DLEN_8821C(x, v)                                       \
+	(BIT_CLEAR_DDMACH1_DLEN_8821C(x) | BIT_DDMACH1_DLEN_8821C(v))
+
+/* 2 REG_DDMA_CH2SA_8821C */
+
+#define BIT_SHIFT_DDMACH2_SA_8821C 0
+#define BIT_MASK_DDMACH2_SA_8821C 0xffffffffL
+#define BIT_DDMACH2_SA_8821C(x)                                                \
+	(((x) & BIT_MASK_DDMACH2_SA_8821C) << BIT_SHIFT_DDMACH2_SA_8821C)
+#define BITS_DDMACH2_SA_8821C                                                  \
+	(BIT_MASK_DDMACH2_SA_8821C << BIT_SHIFT_DDMACH2_SA_8821C)
+#define BIT_CLEAR_DDMACH2_SA_8821C(x) ((x) & (~BITS_DDMACH2_SA_8821C))
+#define BIT_GET_DDMACH2_SA_8821C(x)                                            \
+	(((x) >> BIT_SHIFT_DDMACH2_SA_8821C) & BIT_MASK_DDMACH2_SA_8821C)
+#define BIT_SET_DDMACH2_SA_8821C(x, v)                                         \
+	(BIT_CLEAR_DDMACH2_SA_8821C(x) | BIT_DDMACH2_SA_8821C(v))
+
+/* 2 REG_DDMA_CH2DA_8821C */
+
+#define BIT_SHIFT_DDMACH2_DA_8821C 0
+#define BIT_MASK_DDMACH2_DA_8821C 0xffffffffL
+#define BIT_DDMACH2_DA_8821C(x)                                                \
+	(((x) & BIT_MASK_DDMACH2_DA_8821C) << BIT_SHIFT_DDMACH2_DA_8821C)
+#define BITS_DDMACH2_DA_8821C                                                  \
+	(BIT_MASK_DDMACH2_DA_8821C << BIT_SHIFT_DDMACH2_DA_8821C)
+#define BIT_CLEAR_DDMACH2_DA_8821C(x) ((x) & (~BITS_DDMACH2_DA_8821C))
+#define BIT_GET_DDMACH2_DA_8821C(x)                                            \
+	(((x) >> BIT_SHIFT_DDMACH2_DA_8821C) & BIT_MASK_DDMACH2_DA_8821C)
+#define BIT_SET_DDMACH2_DA_8821C(x, v)                                         \
+	(BIT_CLEAR_DDMACH2_DA_8821C(x) | BIT_DDMACH2_DA_8821C(v))
+
+/* 2 REG_DDMA_CH2CTRL_8821C */
+#define BIT_DDMACH2_OWN_8821C BIT(31)
+#define BIT_DDMACH2_IDMEM_ERR_8821C BIT(30)
+#define BIT_DDMACH2_CHKSUM_EN_8821C BIT(29)
+#define BIT_DDMACH2_DA_W_DISABLE_8821C BIT(28)
+#define BIT_DDMACH2_CHKSUM_STS_8821C BIT(27)
+#define BIT_DDMACH2_DDMA_MODE_8821C BIT(26)
+#define BIT_DDMACH2_RESET_CHKSUM_STS_8821C BIT(25)
+#define BIT_DDMACH2_CHKSUM_CONT_8821C BIT(24)
+
+#define BIT_SHIFT_DDMACH2_DLEN_8821C 0
+#define BIT_MASK_DDMACH2_DLEN_8821C 0x3ffff
+#define BIT_DDMACH2_DLEN_8821C(x)                                              \
+	(((x) & BIT_MASK_DDMACH2_DLEN_8821C) << BIT_SHIFT_DDMACH2_DLEN_8821C)
+#define BITS_DDMACH2_DLEN_8821C                                                \
+	(BIT_MASK_DDMACH2_DLEN_8821C << BIT_SHIFT_DDMACH2_DLEN_8821C)
+#define BIT_CLEAR_DDMACH2_DLEN_8821C(x) ((x) & (~BITS_DDMACH2_DLEN_8821C))
+#define BIT_GET_DDMACH2_DLEN_8821C(x)                                          \
+	(((x) >> BIT_SHIFT_DDMACH2_DLEN_8821C) & BIT_MASK_DDMACH2_DLEN_8821C)
+#define BIT_SET_DDMACH2_DLEN_8821C(x, v)                                       \
+	(BIT_CLEAR_DDMACH2_DLEN_8821C(x) | BIT_DDMACH2_DLEN_8821C(v))
+
+/* 2 REG_DDMA_CH3SA_8821C */
+
+#define BIT_SHIFT_DDMACH3_SA_8821C 0
+#define BIT_MASK_DDMACH3_SA_8821C 0xffffffffL
+#define BIT_DDMACH3_SA_8821C(x)                                                \
+	(((x) & BIT_MASK_DDMACH3_SA_8821C) << BIT_SHIFT_DDMACH3_SA_8821C)
+#define BITS_DDMACH3_SA_8821C                                                  \
+	(BIT_MASK_DDMACH3_SA_8821C << BIT_SHIFT_DDMACH3_SA_8821C)
+#define BIT_CLEAR_DDMACH3_SA_8821C(x) ((x) & (~BITS_DDMACH3_SA_8821C))
+#define BIT_GET_DDMACH3_SA_8821C(x)                                            \
+	(((x) >> BIT_SHIFT_DDMACH3_SA_8821C) & BIT_MASK_DDMACH3_SA_8821C)
+#define BIT_SET_DDMACH3_SA_8821C(x, v)                                         \
+	(BIT_CLEAR_DDMACH3_SA_8821C(x) | BIT_DDMACH3_SA_8821C(v))
+
+/* 2 REG_DDMA_CH3DA_8821C */
+
+#define BIT_SHIFT_DDMACH3_DA_8821C 0
+#define BIT_MASK_DDMACH3_DA_8821C 0xffffffffL
+#define BIT_DDMACH3_DA_8821C(x)                                                \
+	(((x) & BIT_MASK_DDMACH3_DA_8821C) << BIT_SHIFT_DDMACH3_DA_8821C)
+#define BITS_DDMACH3_DA_8821C                                                  \
+	(BIT_MASK_DDMACH3_DA_8821C << BIT_SHIFT_DDMACH3_DA_8821C)
+#define BIT_CLEAR_DDMACH3_DA_8821C(x) ((x) & (~BITS_DDMACH3_DA_8821C))
+#define BIT_GET_DDMACH3_DA_8821C(x)                                            \
+	(((x) >> BIT_SHIFT_DDMACH3_DA_8821C) & BIT_MASK_DDMACH3_DA_8821C)
+#define BIT_SET_DDMACH3_DA_8821C(x, v)                                         \
+	(BIT_CLEAR_DDMACH3_DA_8821C(x) | BIT_DDMACH3_DA_8821C(v))
+
+/* 2 REG_DDMA_CH3CTRL_8821C */
+#define BIT_DDMACH3_OWN_8821C BIT(31)
+#define BIT_DDMACH3_IDMEM_ERR_8821C BIT(30)
+#define BIT_DDMACH3_CHKSUM_EN_8821C BIT(29)
+#define BIT_DDMACH3_DA_W_DISABLE_8821C BIT(28)
+#define BIT_DDMACH3_CHKSUM_STS_8821C BIT(27)
+#define BIT_DDMACH3_DDMA_MODE_8821C BIT(26)
+#define BIT_DDMACH3_RESET_CHKSUM_STS_8821C BIT(25)
+#define BIT_DDMACH3_CHKSUM_CONT_8821C BIT(24)
+
+#define BIT_SHIFT_DDMACH3_DLEN_8821C 0
+#define BIT_MASK_DDMACH3_DLEN_8821C 0x3ffff
+#define BIT_DDMACH3_DLEN_8821C(x)                                              \
+	(((x) & BIT_MASK_DDMACH3_DLEN_8821C) << BIT_SHIFT_DDMACH3_DLEN_8821C)
+#define BITS_DDMACH3_DLEN_8821C                                                \
+	(BIT_MASK_DDMACH3_DLEN_8821C << BIT_SHIFT_DDMACH3_DLEN_8821C)
+#define BIT_CLEAR_DDMACH3_DLEN_8821C(x) ((x) & (~BITS_DDMACH3_DLEN_8821C))
+#define BIT_GET_DDMACH3_DLEN_8821C(x)                                          \
+	(((x) >> BIT_SHIFT_DDMACH3_DLEN_8821C) & BIT_MASK_DDMACH3_DLEN_8821C)
+#define BIT_SET_DDMACH3_DLEN_8821C(x, v)                                       \
+	(BIT_CLEAR_DDMACH3_DLEN_8821C(x) | BIT_DDMACH3_DLEN_8821C(v))
+
+/* 2 REG_DDMA_CH4SA_8821C */
+
+#define BIT_SHIFT_DDMACH4_SA_8821C 0
+#define BIT_MASK_DDMACH4_SA_8821C 0xffffffffL
+#define BIT_DDMACH4_SA_8821C(x)                                                \
+	(((x) & BIT_MASK_DDMACH4_SA_8821C) << BIT_SHIFT_DDMACH4_SA_8821C)
+#define BITS_DDMACH4_SA_8821C                                                  \
+	(BIT_MASK_DDMACH4_SA_8821C << BIT_SHIFT_DDMACH4_SA_8821C)
+#define BIT_CLEAR_DDMACH4_SA_8821C(x) ((x) & (~BITS_DDMACH4_SA_8821C))
+#define BIT_GET_DDMACH4_SA_8821C(x)                                            \
+	(((x) >> BIT_SHIFT_DDMACH4_SA_8821C) & BIT_MASK_DDMACH4_SA_8821C)
+#define BIT_SET_DDMACH4_SA_8821C(x, v)                                         \
+	(BIT_CLEAR_DDMACH4_SA_8821C(x) | BIT_DDMACH4_SA_8821C(v))
+
+/* 2 REG_DDMA_CH4DA_8821C */
+
+#define BIT_SHIFT_DDMACH4_DA_8821C 0
+#define BIT_MASK_DDMACH4_DA_8821C 0xffffffffL
+#define BIT_DDMACH4_DA_8821C(x)                                                \
+	(((x) & BIT_MASK_DDMACH4_DA_8821C) << BIT_SHIFT_DDMACH4_DA_8821C)
+#define BITS_DDMACH4_DA_8821C                                                  \
+	(BIT_MASK_DDMACH4_DA_8821C << BIT_SHIFT_DDMACH4_DA_8821C)
+#define BIT_CLEAR_DDMACH4_DA_8821C(x) ((x) & (~BITS_DDMACH4_DA_8821C))
+#define BIT_GET_DDMACH4_DA_8821C(x)                                            \
+	(((x) >> BIT_SHIFT_DDMACH4_DA_8821C) & BIT_MASK_DDMACH4_DA_8821C)
+#define BIT_SET_DDMACH4_DA_8821C(x, v)                                         \
+	(BIT_CLEAR_DDMACH4_DA_8821C(x) | BIT_DDMACH4_DA_8821C(v))
+
+/* 2 REG_DDMA_CH4CTRL_8821C */
+#define BIT_DDMACH4_OWN_8821C BIT(31)
+#define BIT_DDMACH4_IDMEM_ERR_8821C BIT(30)
+#define BIT_DDMACH4_CHKSUM_EN_8821C BIT(29)
+#define BIT_DDMACH4_DA_W_DISABLE_8821C BIT(28)
+#define BIT_DDMACH4_CHKSUM_STS_8821C BIT(27)
+#define BIT_DDMACH4_DDMA_MODE_8821C BIT(26)
+#define BIT_DDMACH4_RESET_CHKSUM_STS_8821C BIT(25)
+#define BIT_DDMACH4_CHKSUM_CONT_8821C BIT(24)
+
+#define BIT_SHIFT_DDMACH4_DLEN_8821C 0
+#define BIT_MASK_DDMACH4_DLEN_8821C 0x3ffff
+#define BIT_DDMACH4_DLEN_8821C(x)                                              \
+	(((x) & BIT_MASK_DDMACH4_DLEN_8821C) << BIT_SHIFT_DDMACH4_DLEN_8821C)
+#define BITS_DDMACH4_DLEN_8821C                                                \
+	(BIT_MASK_DDMACH4_DLEN_8821C << BIT_SHIFT_DDMACH4_DLEN_8821C)
+#define BIT_CLEAR_DDMACH4_DLEN_8821C(x) ((x) & (~BITS_DDMACH4_DLEN_8821C))
+#define BIT_GET_DDMACH4_DLEN_8821C(x)                                          \
+	(((x) >> BIT_SHIFT_DDMACH4_DLEN_8821C) & BIT_MASK_DDMACH4_DLEN_8821C)
+#define BIT_SET_DDMACH4_DLEN_8821C(x, v)                                       \
+	(BIT_CLEAR_DDMACH4_DLEN_8821C(x) | BIT_DDMACH4_DLEN_8821C(v))
+
+/* 2 REG_DDMA_CH5SA_8821C */
+
+#define BIT_SHIFT_DDMACH5_SA_8821C 0
+#define BIT_MASK_DDMACH5_SA_8821C 0xffffffffL
+#define BIT_DDMACH5_SA_8821C(x)                                                \
+	(((x) & BIT_MASK_DDMACH5_SA_8821C) << BIT_SHIFT_DDMACH5_SA_8821C)
+#define BITS_DDMACH5_SA_8821C                                                  \
+	(BIT_MASK_DDMACH5_SA_8821C << BIT_SHIFT_DDMACH5_SA_8821C)
+#define BIT_CLEAR_DDMACH5_SA_8821C(x) ((x) & (~BITS_DDMACH5_SA_8821C))
+#define BIT_GET_DDMACH5_SA_8821C(x)                                            \
+	(((x) >> BIT_SHIFT_DDMACH5_SA_8821C) & BIT_MASK_DDMACH5_SA_8821C)
+#define BIT_SET_DDMACH5_SA_8821C(x, v)                                         \
+	(BIT_CLEAR_DDMACH5_SA_8821C(x) | BIT_DDMACH5_SA_8821C(v))
+
+/* 2 REG_DDMA_CH5DA_8821C */
+
+#define BIT_SHIFT_DDMACH5_DA_8821C 0
+#define BIT_MASK_DDMACH5_DA_8821C 0xffffffffL
+#define BIT_DDMACH5_DA_8821C(x)                                                \
+	(((x) & BIT_MASK_DDMACH5_DA_8821C) << BIT_SHIFT_DDMACH5_DA_8821C)
+#define BITS_DDMACH5_DA_8821C                                                  \
+	(BIT_MASK_DDMACH5_DA_8821C << BIT_SHIFT_DDMACH5_DA_8821C)
+#define BIT_CLEAR_DDMACH5_DA_8821C(x) ((x) & (~BITS_DDMACH5_DA_8821C))
+#define BIT_GET_DDMACH5_DA_8821C(x)                                            \
+	(((x) >> BIT_SHIFT_DDMACH5_DA_8821C) & BIT_MASK_DDMACH5_DA_8821C)
+#define BIT_SET_DDMACH5_DA_8821C(x, v)                                         \
+	(BIT_CLEAR_DDMACH5_DA_8821C(x) | BIT_DDMACH5_DA_8821C(v))
+
+/* 2 REG_DDMA_CH5CTRL_8821C */
+#define BIT_DDMACH5_OWN_8821C BIT(31)
+#define BIT_DDMACH5_IDMEM_ERR_8821C BIT(30)
+#define BIT_DDMACH5_CHKSUM_EN_8821C BIT(29)
+#define BIT_DDMACH5_DA_W_DISABLE_8821C BIT(28)
+#define BIT_DDMACH5_CHKSUM_STS_8821C BIT(27)
+#define BIT_DDMACH5_DDMA_MODE_8821C BIT(26)
+#define BIT_DDMACH5_RESET_CHKSUM_STS_8821C BIT(25)
+#define BIT_DDMACH5_CHKSUM_CONT_8821C BIT(24)
+
+#define BIT_SHIFT_DDMACH5_DLEN_8821C 0
+#define BIT_MASK_DDMACH5_DLEN_8821C 0x3ffff
+#define BIT_DDMACH5_DLEN_8821C(x)                                              \
+	(((x) & BIT_MASK_DDMACH5_DLEN_8821C) << BIT_SHIFT_DDMACH5_DLEN_8821C)
+#define BITS_DDMACH5_DLEN_8821C                                                \
+	(BIT_MASK_DDMACH5_DLEN_8821C << BIT_SHIFT_DDMACH5_DLEN_8821C)
+#define BIT_CLEAR_DDMACH5_DLEN_8821C(x) ((x) & (~BITS_DDMACH5_DLEN_8821C))
+#define BIT_GET_DDMACH5_DLEN_8821C(x)                                          \
+	(((x) >> BIT_SHIFT_DDMACH5_DLEN_8821C) & BIT_MASK_DDMACH5_DLEN_8821C)
+#define BIT_SET_DDMACH5_DLEN_8821C(x, v)                                       \
+	(BIT_CLEAR_DDMACH5_DLEN_8821C(x) | BIT_DDMACH5_DLEN_8821C(v))
+
+/* 2 REG_DDMA_INT_MSK_8821C */
+#define BIT_DDMACH5_MSK_8821C BIT(5)
+#define BIT_DDMACH4_MSK_8821C BIT(4)
+#define BIT_DDMACH3_MSK_8821C BIT(3)
+#define BIT_DDMACH2_MSK_8821C BIT(2)
+#define BIT_DDMACH1_MSK_8821C BIT(1)
+#define BIT_DDMACH0_MSK_8821C BIT(0)
+
+/* 2 REG_DDMA_CHSTATUS_8821C */
+#define BIT_DDMACH5_BUSY_8821C BIT(5)
+#define BIT_DDMACH4_BUSY_8821C BIT(4)
+#define BIT_DDMACH3_BUSY_8821C BIT(3)
+#define BIT_DDMACH2_BUSY_8821C BIT(2)
+#define BIT_DDMACH1_BUSY_8821C BIT(1)
+#define BIT_DDMACH0_BUSY_8821C BIT(0)
+
+/* 2 REG_DDMA_CHKSUM_8821C */
+
+#define BIT_SHIFT_IDDMA0_CHKSUM_8821C 0
+#define BIT_MASK_IDDMA0_CHKSUM_8821C 0xffff
+#define BIT_IDDMA0_CHKSUM_8821C(x)                                             \
+	(((x) & BIT_MASK_IDDMA0_CHKSUM_8821C) << BIT_SHIFT_IDDMA0_CHKSUM_8821C)
+#define BITS_IDDMA0_CHKSUM_8821C                                               \
+	(BIT_MASK_IDDMA0_CHKSUM_8821C << BIT_SHIFT_IDDMA0_CHKSUM_8821C)
+#define BIT_CLEAR_IDDMA0_CHKSUM_8821C(x) ((x) & (~BITS_IDDMA0_CHKSUM_8821C))
+#define BIT_GET_IDDMA0_CHKSUM_8821C(x)                                         \
+	(((x) >> BIT_SHIFT_IDDMA0_CHKSUM_8821C) & BIT_MASK_IDDMA0_CHKSUM_8821C)
+#define BIT_SET_IDDMA0_CHKSUM_8821C(x, v)                                      \
+	(BIT_CLEAR_IDDMA0_CHKSUM_8821C(x) | BIT_IDDMA0_CHKSUM_8821C(v))
+
+/* 2 REG_DDMA_MONITOR_8821C */
+#define BIT_IDDMA0_PERMU_UNDERFLOW_8821C BIT(14)
+#define BIT_IDDMA0_FIFO_UNDERFLOW_8821C BIT(13)
+#define BIT_IDDMA0_FIFO_OVERFLOW_8821C BIT(12)
+#define BIT_CH5_ERR_8821C BIT(5)
+#define BIT_CH4_ERR_8821C BIT(4)
+#define BIT_CH3_ERR_8821C BIT(3)
+#define BIT_CH2_ERR_8821C BIT(2)
+#define BIT_CH1_ERR_8821C BIT(1)
+#define BIT_CH0_ERR_8821C BIT(0)
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_PCIE_CTRL_8821C */
+#define BIT_PCIEIO_PERSTB_SEL_8821C BIT(31)
+
+#define BIT_SHIFT_PCIE_MAX_RXDMA_8821C 28
+#define BIT_MASK_PCIE_MAX_RXDMA_8821C 0x7
+#define BIT_PCIE_MAX_RXDMA_8821C(x)                                            \
+	(((x) & BIT_MASK_PCIE_MAX_RXDMA_8821C)                                 \
+	 << BIT_SHIFT_PCIE_MAX_RXDMA_8821C)
+#define BITS_PCIE_MAX_RXDMA_8821C                                              \
+	(BIT_MASK_PCIE_MAX_RXDMA_8821C << BIT_SHIFT_PCIE_MAX_RXDMA_8821C)
+#define BIT_CLEAR_PCIE_MAX_RXDMA_8821C(x) ((x) & (~BITS_PCIE_MAX_RXDMA_8821C))
+#define BIT_GET_PCIE_MAX_RXDMA_8821C(x)                                        \
+	(((x) >> BIT_SHIFT_PCIE_MAX_RXDMA_8821C) &                             \
+	 BIT_MASK_PCIE_MAX_RXDMA_8821C)
+#define BIT_SET_PCIE_MAX_RXDMA_8821C(x, v)                                     \
+	(BIT_CLEAR_PCIE_MAX_RXDMA_8821C(x) | BIT_PCIE_MAX_RXDMA_8821C(v))
+
+#define BIT_MULRW_8821C BIT(27)
+
+#define BIT_SHIFT_PCIE_MAX_TXDMA_8821C 24
+#define BIT_MASK_PCIE_MAX_TXDMA_8821C 0x7
+#define BIT_PCIE_MAX_TXDMA_8821C(x)                                            \
+	(((x) & BIT_MASK_PCIE_MAX_TXDMA_8821C)                                 \
+	 << BIT_SHIFT_PCIE_MAX_TXDMA_8821C)
+#define BITS_PCIE_MAX_TXDMA_8821C                                              \
+	(BIT_MASK_PCIE_MAX_TXDMA_8821C << BIT_SHIFT_PCIE_MAX_TXDMA_8821C)
+#define BIT_CLEAR_PCIE_MAX_TXDMA_8821C(x) ((x) & (~BITS_PCIE_MAX_TXDMA_8821C))
+#define BIT_GET_PCIE_MAX_TXDMA_8821C(x)                                        \
+	(((x) >> BIT_SHIFT_PCIE_MAX_TXDMA_8821C) &                             \
+	 BIT_MASK_PCIE_MAX_TXDMA_8821C)
+#define BIT_SET_PCIE_MAX_TXDMA_8821C(x, v)                                     \
+	(BIT_CLEAR_PCIE_MAX_TXDMA_8821C(x) | BIT_PCIE_MAX_TXDMA_8821C(v))
+
+#define BIT_EN_CPL_TIMEOUT_PS_8821C BIT(22)
+#define BIT_REG_TXDMA_FAIL_PS_8821C BIT(21)
+#define BIT_PCIE_RST_TRXDMA_INTF_8821C BIT(20)
+#define BIT_EN_HWENTR_L1_8821C BIT(19)
+#define BIT_EN_ADV_CLKGATE_8821C BIT(18)
+#define BIT_PCIE_EN_SWENT_L23_8821C BIT(17)
+#define BIT_PCIE_EN_HWEXT_L1_8821C BIT(16)
+#define BIT_RX_CLOSE_EN_8821C BIT(15)
+#define BIT_STOP_BCNQ_8821C BIT(14)
+#define BIT_STOP_MGQ_8821C BIT(13)
+#define BIT_STOP_VOQ_8821C BIT(12)
+#define BIT_STOP_VIQ_8821C BIT(11)
+#define BIT_STOP_BEQ_8821C BIT(10)
+#define BIT_STOP_BKQ_8821C BIT(9)
+#define BIT_STOP_RXQ_8821C BIT(8)
+#define BIT_STOP_HI7Q_8821C BIT(7)
+#define BIT_STOP_HI6Q_8821C BIT(6)
+#define BIT_STOP_HI5Q_8821C BIT(5)
+#define BIT_STOP_HI4Q_8821C BIT(4)
+#define BIT_STOP_HI3Q_8821C BIT(3)
+#define BIT_STOP_HI2Q_8821C BIT(2)
+#define BIT_STOP_HI1Q_8821C BIT(1)
+#define BIT_STOP_HI0Q_8821C BIT(0)
+
+/* 2 REG_INT_MIG_8821C */
+
+#define BIT_SHIFT_TXTTIMER_MATCH_NUM_8821C 28
+#define BIT_MASK_TXTTIMER_MATCH_NUM_8821C 0xf
+#define BIT_TXTTIMER_MATCH_NUM_8821C(x)                                        \
+	(((x) & BIT_MASK_TXTTIMER_MATCH_NUM_8821C)                             \
+	 << BIT_SHIFT_TXTTIMER_MATCH_NUM_8821C)
+#define BITS_TXTTIMER_MATCH_NUM_8821C                                          \
+	(BIT_MASK_TXTTIMER_MATCH_NUM_8821C                                     \
+	 << BIT_SHIFT_TXTTIMER_MATCH_NUM_8821C)
+#define BIT_CLEAR_TXTTIMER_MATCH_NUM_8821C(x)                                  \
+	((x) & (~BITS_TXTTIMER_MATCH_NUM_8821C))
+#define BIT_GET_TXTTIMER_MATCH_NUM_8821C(x)                                    \
+	(((x) >> BIT_SHIFT_TXTTIMER_MATCH_NUM_8821C) &                         \
+	 BIT_MASK_TXTTIMER_MATCH_NUM_8821C)
+#define BIT_SET_TXTTIMER_MATCH_NUM_8821C(x, v)                                 \
+	(BIT_CLEAR_TXTTIMER_MATCH_NUM_8821C(x) |                               \
+	 BIT_TXTTIMER_MATCH_NUM_8821C(v))
+
+#define BIT_SHIFT_TXPKT_NUM_MATCH_8821C 24
+#define BIT_MASK_TXPKT_NUM_MATCH_8821C 0xf
+#define BIT_TXPKT_NUM_MATCH_8821C(x)                                           \
+	(((x) & BIT_MASK_TXPKT_NUM_MATCH_8821C)                                \
+	 << BIT_SHIFT_TXPKT_NUM_MATCH_8821C)
+#define BITS_TXPKT_NUM_MATCH_8821C                                             \
+	(BIT_MASK_TXPKT_NUM_MATCH_8821C << BIT_SHIFT_TXPKT_NUM_MATCH_8821C)
+#define BIT_CLEAR_TXPKT_NUM_MATCH_8821C(x) ((x) & (~BITS_TXPKT_NUM_MATCH_8821C))
+#define BIT_GET_TXPKT_NUM_MATCH_8821C(x)                                       \
+	(((x) >> BIT_SHIFT_TXPKT_NUM_MATCH_8821C) &                            \
+	 BIT_MASK_TXPKT_NUM_MATCH_8821C)
+#define BIT_SET_TXPKT_NUM_MATCH_8821C(x, v)                                    \
+	(BIT_CLEAR_TXPKT_NUM_MATCH_8821C(x) | BIT_TXPKT_NUM_MATCH_8821C(v))
+
+#define BIT_SHIFT_RXTTIMER_MATCH_NUM_8821C 20
+#define BIT_MASK_RXTTIMER_MATCH_NUM_8821C 0xf
+#define BIT_RXTTIMER_MATCH_NUM_8821C(x)                                        \
+	(((x) & BIT_MASK_RXTTIMER_MATCH_NUM_8821C)                             \
+	 << BIT_SHIFT_RXTTIMER_MATCH_NUM_8821C)
+#define BITS_RXTTIMER_MATCH_NUM_8821C                                          \
+	(BIT_MASK_RXTTIMER_MATCH_NUM_8821C                                     \
+	 << BIT_SHIFT_RXTTIMER_MATCH_NUM_8821C)
+#define BIT_CLEAR_RXTTIMER_MATCH_NUM_8821C(x)                                  \
+	((x) & (~BITS_RXTTIMER_MATCH_NUM_8821C))
+#define BIT_GET_RXTTIMER_MATCH_NUM_8821C(x)                                    \
+	(((x) >> BIT_SHIFT_RXTTIMER_MATCH_NUM_8821C) &                         \
+	 BIT_MASK_RXTTIMER_MATCH_NUM_8821C)
+#define BIT_SET_RXTTIMER_MATCH_NUM_8821C(x, v)                                 \
+	(BIT_CLEAR_RXTTIMER_MATCH_NUM_8821C(x) |                               \
+	 BIT_RXTTIMER_MATCH_NUM_8821C(v))
+
+#define BIT_SHIFT_RXPKT_NUM_MATCH_8821C 16
+#define BIT_MASK_RXPKT_NUM_MATCH_8821C 0xf
+#define BIT_RXPKT_NUM_MATCH_8821C(x)                                           \
+	(((x) & BIT_MASK_RXPKT_NUM_MATCH_8821C)                                \
+	 << BIT_SHIFT_RXPKT_NUM_MATCH_8821C)
+#define BITS_RXPKT_NUM_MATCH_8821C                                             \
+	(BIT_MASK_RXPKT_NUM_MATCH_8821C << BIT_SHIFT_RXPKT_NUM_MATCH_8821C)
+#define BIT_CLEAR_RXPKT_NUM_MATCH_8821C(x) ((x) & (~BITS_RXPKT_NUM_MATCH_8821C))
+#define BIT_GET_RXPKT_NUM_MATCH_8821C(x)                                       \
+	(((x) >> BIT_SHIFT_RXPKT_NUM_MATCH_8821C) &                            \
+	 BIT_MASK_RXPKT_NUM_MATCH_8821C)
+#define BIT_SET_RXPKT_NUM_MATCH_8821C(x, v)                                    \
+	(BIT_CLEAR_RXPKT_NUM_MATCH_8821C(x) | BIT_RXPKT_NUM_MATCH_8821C(v))
+
+#define BIT_SHIFT_MIGRATE_TIMER_8821C 0
+#define BIT_MASK_MIGRATE_TIMER_8821C 0xffff
+#define BIT_MIGRATE_TIMER_8821C(x)                                             \
+	(((x) & BIT_MASK_MIGRATE_TIMER_8821C) << BIT_SHIFT_MIGRATE_TIMER_8821C)
+#define BITS_MIGRATE_TIMER_8821C                                               \
+	(BIT_MASK_MIGRATE_TIMER_8821C << BIT_SHIFT_MIGRATE_TIMER_8821C)
+#define BIT_CLEAR_MIGRATE_TIMER_8821C(x) ((x) & (~BITS_MIGRATE_TIMER_8821C))
+#define BIT_GET_MIGRATE_TIMER_8821C(x)                                         \
+	(((x) >> BIT_SHIFT_MIGRATE_TIMER_8821C) & BIT_MASK_MIGRATE_TIMER_8821C)
+#define BIT_SET_MIGRATE_TIMER_8821C(x, v)                                      \
+	(BIT_CLEAR_MIGRATE_TIMER_8821C(x) | BIT_MIGRATE_TIMER_8821C(v))
+
+/* 2 REG_BCNQ_TXBD_DESA_8821C */
+
+#define BIT_SHIFT_BCNQ_TXBD_DESA_8821C 0
+#define BIT_MASK_BCNQ_TXBD_DESA_8821C 0xffffffffffffffffL
+#define BIT_BCNQ_TXBD_DESA_8821C(x)                                            \
+	(((x) & BIT_MASK_BCNQ_TXBD_DESA_8821C)                                 \
+	 << BIT_SHIFT_BCNQ_TXBD_DESA_8821C)
+#define BITS_BCNQ_TXBD_DESA_8821C                                              \
+	(BIT_MASK_BCNQ_TXBD_DESA_8821C << BIT_SHIFT_BCNQ_TXBD_DESA_8821C)
+#define BIT_CLEAR_BCNQ_TXBD_DESA_8821C(x) ((x) & (~BITS_BCNQ_TXBD_DESA_8821C))
+#define BIT_GET_BCNQ_TXBD_DESA_8821C(x)                                        \
+	(((x) >> BIT_SHIFT_BCNQ_TXBD_DESA_8821C) &                             \
+	 BIT_MASK_BCNQ_TXBD_DESA_8821C)
+#define BIT_SET_BCNQ_TXBD_DESA_8821C(x, v)                                     \
+	(BIT_CLEAR_BCNQ_TXBD_DESA_8821C(x) | BIT_BCNQ_TXBD_DESA_8821C(v))
+
+/* 2 REG_MGQ_TXBD_DESA_8821C */
+
+#define BIT_SHIFT_MGQ_TXBD_DESA_8821C 0
+#define BIT_MASK_MGQ_TXBD_DESA_8821C 0xffffffffffffffffL
+#define BIT_MGQ_TXBD_DESA_8821C(x)                                             \
+	(((x) & BIT_MASK_MGQ_TXBD_DESA_8821C) << BIT_SHIFT_MGQ_TXBD_DESA_8821C)
+#define BITS_MGQ_TXBD_DESA_8821C                                               \
+	(BIT_MASK_MGQ_TXBD_DESA_8821C << BIT_SHIFT_MGQ_TXBD_DESA_8821C)
+#define BIT_CLEAR_MGQ_TXBD_DESA_8821C(x) ((x) & (~BITS_MGQ_TXBD_DESA_8821C))
+#define BIT_GET_MGQ_TXBD_DESA_8821C(x)                                         \
+	(((x) >> BIT_SHIFT_MGQ_TXBD_DESA_8821C) & BIT_MASK_MGQ_TXBD_DESA_8821C)
+#define BIT_SET_MGQ_TXBD_DESA_8821C(x, v)                                      \
+	(BIT_CLEAR_MGQ_TXBD_DESA_8821C(x) | BIT_MGQ_TXBD_DESA_8821C(v))
+
+/* 2 REG_VOQ_TXBD_DESA_8821C */
+
+#define BIT_SHIFT_VOQ_TXBD_DESA_8821C 0
+#define BIT_MASK_VOQ_TXBD_DESA_8821C 0xffffffffffffffffL
+#define BIT_VOQ_TXBD_DESA_8821C(x)                                             \
+	(((x) & BIT_MASK_VOQ_TXBD_DESA_8821C) << BIT_SHIFT_VOQ_TXBD_DESA_8821C)
+#define BITS_VOQ_TXBD_DESA_8821C                                               \
+	(BIT_MASK_VOQ_TXBD_DESA_8821C << BIT_SHIFT_VOQ_TXBD_DESA_8821C)
+#define BIT_CLEAR_VOQ_TXBD_DESA_8821C(x) ((x) & (~BITS_VOQ_TXBD_DESA_8821C))
+#define BIT_GET_VOQ_TXBD_DESA_8821C(x)                                         \
+	(((x) >> BIT_SHIFT_VOQ_TXBD_DESA_8821C) & BIT_MASK_VOQ_TXBD_DESA_8821C)
+#define BIT_SET_VOQ_TXBD_DESA_8821C(x, v)                                      \
+	(BIT_CLEAR_VOQ_TXBD_DESA_8821C(x) | BIT_VOQ_TXBD_DESA_8821C(v))
+
+/* 2 REG_VIQ_TXBD_DESA_8821C */
+
+#define BIT_SHIFT_VIQ_TXBD_DESA_8821C 0
+#define BIT_MASK_VIQ_TXBD_DESA_8821C 0xffffffffffffffffL
+#define BIT_VIQ_TXBD_DESA_8821C(x)                                             \
+	(((x) & BIT_MASK_VIQ_TXBD_DESA_8821C) << BIT_SHIFT_VIQ_TXBD_DESA_8821C)
+#define BITS_VIQ_TXBD_DESA_8821C                                               \
+	(BIT_MASK_VIQ_TXBD_DESA_8821C << BIT_SHIFT_VIQ_TXBD_DESA_8821C)
+#define BIT_CLEAR_VIQ_TXBD_DESA_8821C(x) ((x) & (~BITS_VIQ_TXBD_DESA_8821C))
+#define BIT_GET_VIQ_TXBD_DESA_8821C(x)                                         \
+	(((x) >> BIT_SHIFT_VIQ_TXBD_DESA_8821C) & BIT_MASK_VIQ_TXBD_DESA_8821C)
+#define BIT_SET_VIQ_TXBD_DESA_8821C(x, v)                                      \
+	(BIT_CLEAR_VIQ_TXBD_DESA_8821C(x) | BIT_VIQ_TXBD_DESA_8821C(v))
+
+/* 2 REG_BEQ_TXBD_DESA_8821C */
+
+#define BIT_SHIFT_BEQ_TXBD_DESA_8821C 0
+#define BIT_MASK_BEQ_TXBD_DESA_8821C 0xffffffffffffffffL
+#define BIT_BEQ_TXBD_DESA_8821C(x)                                             \
+	(((x) & BIT_MASK_BEQ_TXBD_DESA_8821C) << BIT_SHIFT_BEQ_TXBD_DESA_8821C)
+#define BITS_BEQ_TXBD_DESA_8821C                                               \
+	(BIT_MASK_BEQ_TXBD_DESA_8821C << BIT_SHIFT_BEQ_TXBD_DESA_8821C)
+#define BIT_CLEAR_BEQ_TXBD_DESA_8821C(x) ((x) & (~BITS_BEQ_TXBD_DESA_8821C))
+#define BIT_GET_BEQ_TXBD_DESA_8821C(x)                                         \
+	(((x) >> BIT_SHIFT_BEQ_TXBD_DESA_8821C) & BIT_MASK_BEQ_TXBD_DESA_8821C)
+#define BIT_SET_BEQ_TXBD_DESA_8821C(x, v)                                      \
+	(BIT_CLEAR_BEQ_TXBD_DESA_8821C(x) | BIT_BEQ_TXBD_DESA_8821C(v))
+
+/* 2 REG_BKQ_TXBD_DESA_8821C */
+
+#define BIT_SHIFT_BKQ_TXBD_DESA_8821C 0
+#define BIT_MASK_BKQ_TXBD_DESA_8821C 0xffffffffffffffffL
+#define BIT_BKQ_TXBD_DESA_8821C(x)                                             \
+	(((x) & BIT_MASK_BKQ_TXBD_DESA_8821C) << BIT_SHIFT_BKQ_TXBD_DESA_8821C)
+#define BITS_BKQ_TXBD_DESA_8821C                                               \
+	(BIT_MASK_BKQ_TXBD_DESA_8821C << BIT_SHIFT_BKQ_TXBD_DESA_8821C)
+#define BIT_CLEAR_BKQ_TXBD_DESA_8821C(x) ((x) & (~BITS_BKQ_TXBD_DESA_8821C))
+#define BIT_GET_BKQ_TXBD_DESA_8821C(x)                                         \
+	(((x) >> BIT_SHIFT_BKQ_TXBD_DESA_8821C) & BIT_MASK_BKQ_TXBD_DESA_8821C)
+#define BIT_SET_BKQ_TXBD_DESA_8821C(x, v)                                      \
+	(BIT_CLEAR_BKQ_TXBD_DESA_8821C(x) | BIT_BKQ_TXBD_DESA_8821C(v))
+
+/* 2 REG_RXQ_RXBD_DESA_8821C */
+
+#define BIT_SHIFT_RXQ_RXBD_DESA_8821C 0
+#define BIT_MASK_RXQ_RXBD_DESA_8821C 0xffffffffffffffffL
+#define BIT_RXQ_RXBD_DESA_8821C(x)                                             \
+	(((x) & BIT_MASK_RXQ_RXBD_DESA_8821C) << BIT_SHIFT_RXQ_RXBD_DESA_8821C)
+#define BITS_RXQ_RXBD_DESA_8821C                                               \
+	(BIT_MASK_RXQ_RXBD_DESA_8821C << BIT_SHIFT_RXQ_RXBD_DESA_8821C)
+#define BIT_CLEAR_RXQ_RXBD_DESA_8821C(x) ((x) & (~BITS_RXQ_RXBD_DESA_8821C))
+#define BIT_GET_RXQ_RXBD_DESA_8821C(x)                                         \
+	(((x) >> BIT_SHIFT_RXQ_RXBD_DESA_8821C) & BIT_MASK_RXQ_RXBD_DESA_8821C)
+#define BIT_SET_RXQ_RXBD_DESA_8821C(x, v)                                      \
+	(BIT_CLEAR_RXQ_RXBD_DESA_8821C(x) | BIT_RXQ_RXBD_DESA_8821C(v))
+
+/* 2 REG_HI0Q_TXBD_DESA_8821C */
+
+#define BIT_SHIFT_HI0Q_TXBD_DESA_8821C 0
+#define BIT_MASK_HI0Q_TXBD_DESA_8821C 0xffffffffffffffffL
+#define BIT_HI0Q_TXBD_DESA_8821C(x)                                            \
+	(((x) & BIT_MASK_HI0Q_TXBD_DESA_8821C)                                 \
+	 << BIT_SHIFT_HI0Q_TXBD_DESA_8821C)
+#define BITS_HI0Q_TXBD_DESA_8821C                                              \
+	(BIT_MASK_HI0Q_TXBD_DESA_8821C << BIT_SHIFT_HI0Q_TXBD_DESA_8821C)
+#define BIT_CLEAR_HI0Q_TXBD_DESA_8821C(x) ((x) & (~BITS_HI0Q_TXBD_DESA_8821C))
+#define BIT_GET_HI0Q_TXBD_DESA_8821C(x)                                        \
+	(((x) >> BIT_SHIFT_HI0Q_TXBD_DESA_8821C) &                             \
+	 BIT_MASK_HI0Q_TXBD_DESA_8821C)
+#define BIT_SET_HI0Q_TXBD_DESA_8821C(x, v)                                     \
+	(BIT_CLEAR_HI0Q_TXBD_DESA_8821C(x) | BIT_HI0Q_TXBD_DESA_8821C(v))
+
+/* 2 REG_HI1Q_TXBD_DESA_8821C */
+
+#define BIT_SHIFT_HI1Q_TXBD_DESA_8821C 0
+#define BIT_MASK_HI1Q_TXBD_DESA_8821C 0xffffffffffffffffL
+#define BIT_HI1Q_TXBD_DESA_8821C(x)                                            \
+	(((x) & BIT_MASK_HI1Q_TXBD_DESA_8821C)                                 \
+	 << BIT_SHIFT_HI1Q_TXBD_DESA_8821C)
+#define BITS_HI1Q_TXBD_DESA_8821C                                              \
+	(BIT_MASK_HI1Q_TXBD_DESA_8821C << BIT_SHIFT_HI1Q_TXBD_DESA_8821C)
+#define BIT_CLEAR_HI1Q_TXBD_DESA_8821C(x) ((x) & (~BITS_HI1Q_TXBD_DESA_8821C))
+#define BIT_GET_HI1Q_TXBD_DESA_8821C(x)                                        \
+	(((x) >> BIT_SHIFT_HI1Q_TXBD_DESA_8821C) &                             \
+	 BIT_MASK_HI1Q_TXBD_DESA_8821C)
+#define BIT_SET_HI1Q_TXBD_DESA_8821C(x, v)                                     \
+	(BIT_CLEAR_HI1Q_TXBD_DESA_8821C(x) | BIT_HI1Q_TXBD_DESA_8821C(v))
+
+/* 2 REG_HI2Q_TXBD_DESA_8821C */
+
+#define BIT_SHIFT_HI2Q_TXBD_DESA_8821C 0
+#define BIT_MASK_HI2Q_TXBD_DESA_8821C 0xffffffffffffffffL
+#define BIT_HI2Q_TXBD_DESA_8821C(x)                                            \
+	(((x) & BIT_MASK_HI2Q_TXBD_DESA_8821C)                                 \
+	 << BIT_SHIFT_HI2Q_TXBD_DESA_8821C)
+#define BITS_HI2Q_TXBD_DESA_8821C                                              \
+	(BIT_MASK_HI2Q_TXBD_DESA_8821C << BIT_SHIFT_HI2Q_TXBD_DESA_8821C)
+#define BIT_CLEAR_HI2Q_TXBD_DESA_8821C(x) ((x) & (~BITS_HI2Q_TXBD_DESA_8821C))
+#define BIT_GET_HI2Q_TXBD_DESA_8821C(x)                                        \
+	(((x) >> BIT_SHIFT_HI2Q_TXBD_DESA_8821C) &                             \
+	 BIT_MASK_HI2Q_TXBD_DESA_8821C)
+#define BIT_SET_HI2Q_TXBD_DESA_8821C(x, v)                                     \
+	(BIT_CLEAR_HI2Q_TXBD_DESA_8821C(x) | BIT_HI2Q_TXBD_DESA_8821C(v))
+
+/* 2 REG_HI3Q_TXBD_DESA_8821C */
+
+#define BIT_SHIFT_HI3Q_TXBD_DESA_8821C 0
+#define BIT_MASK_HI3Q_TXBD_DESA_8821C 0xffffffffffffffffL
+#define BIT_HI3Q_TXBD_DESA_8821C(x)                                            \
+	(((x) & BIT_MASK_HI3Q_TXBD_DESA_8821C)                                 \
+	 << BIT_SHIFT_HI3Q_TXBD_DESA_8821C)
+#define BITS_HI3Q_TXBD_DESA_8821C                                              \
+	(BIT_MASK_HI3Q_TXBD_DESA_8821C << BIT_SHIFT_HI3Q_TXBD_DESA_8821C)
+#define BIT_CLEAR_HI3Q_TXBD_DESA_8821C(x) ((x) & (~BITS_HI3Q_TXBD_DESA_8821C))
+#define BIT_GET_HI3Q_TXBD_DESA_8821C(x)                                        \
+	(((x) >> BIT_SHIFT_HI3Q_TXBD_DESA_8821C) &                             \
+	 BIT_MASK_HI3Q_TXBD_DESA_8821C)
+#define BIT_SET_HI3Q_TXBD_DESA_8821C(x, v)                                     \
+	(BIT_CLEAR_HI3Q_TXBD_DESA_8821C(x) | BIT_HI3Q_TXBD_DESA_8821C(v))
+
+/* 2 REG_HI4Q_TXBD_DESA_8821C */
+
+#define BIT_SHIFT_HI4Q_TXBD_DESA_8821C 0
+#define BIT_MASK_HI4Q_TXBD_DESA_8821C 0xffffffffffffffffL
+#define BIT_HI4Q_TXBD_DESA_8821C(x)                                            \
+	(((x) & BIT_MASK_HI4Q_TXBD_DESA_8821C)                                 \
+	 << BIT_SHIFT_HI4Q_TXBD_DESA_8821C)
+#define BITS_HI4Q_TXBD_DESA_8821C                                              \
+	(BIT_MASK_HI4Q_TXBD_DESA_8821C << BIT_SHIFT_HI4Q_TXBD_DESA_8821C)
+#define BIT_CLEAR_HI4Q_TXBD_DESA_8821C(x) ((x) & (~BITS_HI4Q_TXBD_DESA_8821C))
+#define BIT_GET_HI4Q_TXBD_DESA_8821C(x)                                        \
+	(((x) >> BIT_SHIFT_HI4Q_TXBD_DESA_8821C) &                             \
+	 BIT_MASK_HI4Q_TXBD_DESA_8821C)
+#define BIT_SET_HI4Q_TXBD_DESA_8821C(x, v)                                     \
+	(BIT_CLEAR_HI4Q_TXBD_DESA_8821C(x) | BIT_HI4Q_TXBD_DESA_8821C(v))
+
+/* 2 REG_HI5Q_TXBD_DESA_8821C */
+
+#define BIT_SHIFT_HI5Q_TXBD_DESA_8821C 0
+#define BIT_MASK_HI5Q_TXBD_DESA_8821C 0xffffffffffffffffL
+#define BIT_HI5Q_TXBD_DESA_8821C(x)                                            \
+	(((x) & BIT_MASK_HI5Q_TXBD_DESA_8821C)                                 \
+	 << BIT_SHIFT_HI5Q_TXBD_DESA_8821C)
+#define BITS_HI5Q_TXBD_DESA_8821C                                              \
+	(BIT_MASK_HI5Q_TXBD_DESA_8821C << BIT_SHIFT_HI5Q_TXBD_DESA_8821C)
+#define BIT_CLEAR_HI5Q_TXBD_DESA_8821C(x) ((x) & (~BITS_HI5Q_TXBD_DESA_8821C))
+#define BIT_GET_HI5Q_TXBD_DESA_8821C(x)                                        \
+	(((x) >> BIT_SHIFT_HI5Q_TXBD_DESA_8821C) &                             \
+	 BIT_MASK_HI5Q_TXBD_DESA_8821C)
+#define BIT_SET_HI5Q_TXBD_DESA_8821C(x, v)                                     \
+	(BIT_CLEAR_HI5Q_TXBD_DESA_8821C(x) | BIT_HI5Q_TXBD_DESA_8821C(v))
+
+/* 2 REG_HI6Q_TXBD_DESA_8821C */
+
+#define BIT_SHIFT_HI6Q_TXBD_DESA_8821C 0
+#define BIT_MASK_HI6Q_TXBD_DESA_8821C 0xffffffffffffffffL
+#define BIT_HI6Q_TXBD_DESA_8821C(x)                                            \
+	(((x) & BIT_MASK_HI6Q_TXBD_DESA_8821C)                                 \
+	 << BIT_SHIFT_HI6Q_TXBD_DESA_8821C)
+#define BITS_HI6Q_TXBD_DESA_8821C                                              \
+	(BIT_MASK_HI6Q_TXBD_DESA_8821C << BIT_SHIFT_HI6Q_TXBD_DESA_8821C)
+#define BIT_CLEAR_HI6Q_TXBD_DESA_8821C(x) ((x) & (~BITS_HI6Q_TXBD_DESA_8821C))
+#define BIT_GET_HI6Q_TXBD_DESA_8821C(x)                                        \
+	(((x) >> BIT_SHIFT_HI6Q_TXBD_DESA_8821C) &                             \
+	 BIT_MASK_HI6Q_TXBD_DESA_8821C)
+#define BIT_SET_HI6Q_TXBD_DESA_8821C(x, v)                                     \
+	(BIT_CLEAR_HI6Q_TXBD_DESA_8821C(x) | BIT_HI6Q_TXBD_DESA_8821C(v))
+
+/* 2 REG_HI7Q_TXBD_DESA_8821C */
+
+#define BIT_SHIFT_HI7Q_TXBD_DESA_8821C 0
+#define BIT_MASK_HI7Q_TXBD_DESA_8821C 0xffffffffffffffffL
+#define BIT_HI7Q_TXBD_DESA_8821C(x)                                            \
+	(((x) & BIT_MASK_HI7Q_TXBD_DESA_8821C)                                 \
+	 << BIT_SHIFT_HI7Q_TXBD_DESA_8821C)
+#define BITS_HI7Q_TXBD_DESA_8821C                                              \
+	(BIT_MASK_HI7Q_TXBD_DESA_8821C << BIT_SHIFT_HI7Q_TXBD_DESA_8821C)
+#define BIT_CLEAR_HI7Q_TXBD_DESA_8821C(x) ((x) & (~BITS_HI7Q_TXBD_DESA_8821C))
+#define BIT_GET_HI7Q_TXBD_DESA_8821C(x)                                        \
+	(((x) >> BIT_SHIFT_HI7Q_TXBD_DESA_8821C) &                             \
+	 BIT_MASK_HI7Q_TXBD_DESA_8821C)
+#define BIT_SET_HI7Q_TXBD_DESA_8821C(x, v)                                     \
+	(BIT_CLEAR_HI7Q_TXBD_DESA_8821C(x) | BIT_HI7Q_TXBD_DESA_8821C(v))
+
+/* 2 REG_MGQ_TXBD_NUM_8821C */
+#define BIT_PCIE_MGQ_FLAG_8821C BIT(14)
+
+#define BIT_SHIFT_MGQ_DESC_MODE_8821C 12
+#define BIT_MASK_MGQ_DESC_MODE_8821C 0x3
+#define BIT_MGQ_DESC_MODE_8821C(x)                                             \
+	(((x) & BIT_MASK_MGQ_DESC_MODE_8821C) << BIT_SHIFT_MGQ_DESC_MODE_8821C)
+#define BITS_MGQ_DESC_MODE_8821C                                               \
+	(BIT_MASK_MGQ_DESC_MODE_8821C << BIT_SHIFT_MGQ_DESC_MODE_8821C)
+#define BIT_CLEAR_MGQ_DESC_MODE_8821C(x) ((x) & (~BITS_MGQ_DESC_MODE_8821C))
+#define BIT_GET_MGQ_DESC_MODE_8821C(x)                                         \
+	(((x) >> BIT_SHIFT_MGQ_DESC_MODE_8821C) & BIT_MASK_MGQ_DESC_MODE_8821C)
+#define BIT_SET_MGQ_DESC_MODE_8821C(x, v)                                      \
+	(BIT_CLEAR_MGQ_DESC_MODE_8821C(x) | BIT_MGQ_DESC_MODE_8821C(v))
+
+#define BIT_SHIFT_MGQ_DESC_NUM_8821C 0
+#define BIT_MASK_MGQ_DESC_NUM_8821C 0xfff
+#define BIT_MGQ_DESC_NUM_8821C(x)                                              \
+	(((x) & BIT_MASK_MGQ_DESC_NUM_8821C) << BIT_SHIFT_MGQ_DESC_NUM_8821C)
+#define BITS_MGQ_DESC_NUM_8821C                                                \
+	(BIT_MASK_MGQ_DESC_NUM_8821C << BIT_SHIFT_MGQ_DESC_NUM_8821C)
+#define BIT_CLEAR_MGQ_DESC_NUM_8821C(x) ((x) & (~BITS_MGQ_DESC_NUM_8821C))
+#define BIT_GET_MGQ_DESC_NUM_8821C(x)                                          \
+	(((x) >> BIT_SHIFT_MGQ_DESC_NUM_8821C) & BIT_MASK_MGQ_DESC_NUM_8821C)
+#define BIT_SET_MGQ_DESC_NUM_8821C(x, v)                                       \
+	(BIT_CLEAR_MGQ_DESC_NUM_8821C(x) | BIT_MGQ_DESC_NUM_8821C(v))
+
+/* 2 REG_RX_RXBD_NUM_8821C */
+#define BIT_SYS_32_64_8821C BIT(15)
+
+#define BIT_SHIFT_BCNQ_DESC_MODE_8821C 13
+#define BIT_MASK_BCNQ_DESC_MODE_8821C 0x3
+#define BIT_BCNQ_DESC_MODE_8821C(x)                                            \
+	(((x) & BIT_MASK_BCNQ_DESC_MODE_8821C)                                 \
+	 << BIT_SHIFT_BCNQ_DESC_MODE_8821C)
+#define BITS_BCNQ_DESC_MODE_8821C                                              \
+	(BIT_MASK_BCNQ_DESC_MODE_8821C << BIT_SHIFT_BCNQ_DESC_MODE_8821C)
+#define BIT_CLEAR_BCNQ_DESC_MODE_8821C(x) ((x) & (~BITS_BCNQ_DESC_MODE_8821C))
+#define BIT_GET_BCNQ_DESC_MODE_8821C(x)                                        \
+	(((x) >> BIT_SHIFT_BCNQ_DESC_MODE_8821C) &                             \
+	 BIT_MASK_BCNQ_DESC_MODE_8821C)
+#define BIT_SET_BCNQ_DESC_MODE_8821C(x, v)                                     \
+	(BIT_CLEAR_BCNQ_DESC_MODE_8821C(x) | BIT_BCNQ_DESC_MODE_8821C(v))
+
+#define BIT_PCIE_BCNQ_FLAG_8821C BIT(12)
+
+#define BIT_SHIFT_RXQ_DESC_NUM_8821C 0
+#define BIT_MASK_RXQ_DESC_NUM_8821C 0xfff
+#define BIT_RXQ_DESC_NUM_8821C(x)                                              \
+	(((x) & BIT_MASK_RXQ_DESC_NUM_8821C) << BIT_SHIFT_RXQ_DESC_NUM_8821C)
+#define BITS_RXQ_DESC_NUM_8821C                                                \
+	(BIT_MASK_RXQ_DESC_NUM_8821C << BIT_SHIFT_RXQ_DESC_NUM_8821C)
+#define BIT_CLEAR_RXQ_DESC_NUM_8821C(x) ((x) & (~BITS_RXQ_DESC_NUM_8821C))
+#define BIT_GET_RXQ_DESC_NUM_8821C(x)                                          \
+	(((x) >> BIT_SHIFT_RXQ_DESC_NUM_8821C) & BIT_MASK_RXQ_DESC_NUM_8821C)
+#define BIT_SET_RXQ_DESC_NUM_8821C(x, v)                                       \
+	(BIT_CLEAR_RXQ_DESC_NUM_8821C(x) | BIT_RXQ_DESC_NUM_8821C(v))
+
+/* 2 REG_VOQ_TXBD_NUM_8821C */
+#define BIT_PCIE_VOQ_FLAG_8821C BIT(14)
+
+#define BIT_SHIFT_VOQ_DESC_MODE_8821C 12
+#define BIT_MASK_VOQ_DESC_MODE_8821C 0x3
+#define BIT_VOQ_DESC_MODE_8821C(x)                                             \
+	(((x) & BIT_MASK_VOQ_DESC_MODE_8821C) << BIT_SHIFT_VOQ_DESC_MODE_8821C)
+#define BITS_VOQ_DESC_MODE_8821C                                               \
+	(BIT_MASK_VOQ_DESC_MODE_8821C << BIT_SHIFT_VOQ_DESC_MODE_8821C)
+#define BIT_CLEAR_VOQ_DESC_MODE_8821C(x) ((x) & (~BITS_VOQ_DESC_MODE_8821C))
+#define BIT_GET_VOQ_DESC_MODE_8821C(x)                                         \
+	(((x) >> BIT_SHIFT_VOQ_DESC_MODE_8821C) & BIT_MASK_VOQ_DESC_MODE_8821C)
+#define BIT_SET_VOQ_DESC_MODE_8821C(x, v)                                      \
+	(BIT_CLEAR_VOQ_DESC_MODE_8821C(x) | BIT_VOQ_DESC_MODE_8821C(v))
+
+#define BIT_SHIFT_VOQ_DESC_NUM_8821C 0
+#define BIT_MASK_VOQ_DESC_NUM_8821C 0xfff
+#define BIT_VOQ_DESC_NUM_8821C(x)                                              \
+	(((x) & BIT_MASK_VOQ_DESC_NUM_8821C) << BIT_SHIFT_VOQ_DESC_NUM_8821C)
+#define BITS_VOQ_DESC_NUM_8821C                                                \
+	(BIT_MASK_VOQ_DESC_NUM_8821C << BIT_SHIFT_VOQ_DESC_NUM_8821C)
+#define BIT_CLEAR_VOQ_DESC_NUM_8821C(x) ((x) & (~BITS_VOQ_DESC_NUM_8821C))
+#define BIT_GET_VOQ_DESC_NUM_8821C(x)                                          \
+	(((x) >> BIT_SHIFT_VOQ_DESC_NUM_8821C) & BIT_MASK_VOQ_DESC_NUM_8821C)
+#define BIT_SET_VOQ_DESC_NUM_8821C(x, v)                                       \
+	(BIT_CLEAR_VOQ_DESC_NUM_8821C(x) | BIT_VOQ_DESC_NUM_8821C(v))
+
+/* 2 REG_VIQ_TXBD_NUM_8821C */
+#define BIT_PCIE_VIQ_FLAG_8821C BIT(14)
+
+#define BIT_SHIFT_VIQ_DESC_MODE_8821C 12
+#define BIT_MASK_VIQ_DESC_MODE_8821C 0x3
+#define BIT_VIQ_DESC_MODE_8821C(x)                                             \
+	(((x) & BIT_MASK_VIQ_DESC_MODE_8821C) << BIT_SHIFT_VIQ_DESC_MODE_8821C)
+#define BITS_VIQ_DESC_MODE_8821C                                               \
+	(BIT_MASK_VIQ_DESC_MODE_8821C << BIT_SHIFT_VIQ_DESC_MODE_8821C)
+#define BIT_CLEAR_VIQ_DESC_MODE_8821C(x) ((x) & (~BITS_VIQ_DESC_MODE_8821C))
+#define BIT_GET_VIQ_DESC_MODE_8821C(x)                                         \
+	(((x) >> BIT_SHIFT_VIQ_DESC_MODE_8821C) & BIT_MASK_VIQ_DESC_MODE_8821C)
+#define BIT_SET_VIQ_DESC_MODE_8821C(x, v)                                      \
+	(BIT_CLEAR_VIQ_DESC_MODE_8821C(x) | BIT_VIQ_DESC_MODE_8821C(v))
+
+#define BIT_SHIFT_VIQ_DESC_NUM_8821C 0
+#define BIT_MASK_VIQ_DESC_NUM_8821C 0xfff
+#define BIT_VIQ_DESC_NUM_8821C(x)                                              \
+	(((x) & BIT_MASK_VIQ_DESC_NUM_8821C) << BIT_SHIFT_VIQ_DESC_NUM_8821C)
+#define BITS_VIQ_DESC_NUM_8821C                                                \
+	(BIT_MASK_VIQ_DESC_NUM_8821C << BIT_SHIFT_VIQ_DESC_NUM_8821C)
+#define BIT_CLEAR_VIQ_DESC_NUM_8821C(x) ((x) & (~BITS_VIQ_DESC_NUM_8821C))
+#define BIT_GET_VIQ_DESC_NUM_8821C(x)                                          \
+	(((x) >> BIT_SHIFT_VIQ_DESC_NUM_8821C) & BIT_MASK_VIQ_DESC_NUM_8821C)
+#define BIT_SET_VIQ_DESC_NUM_8821C(x, v)                                       \
+	(BIT_CLEAR_VIQ_DESC_NUM_8821C(x) | BIT_VIQ_DESC_NUM_8821C(v))
+
+/* 2 REG_BEQ_TXBD_NUM_8821C */
+#define BIT_PCIE_BEQ_FLAG_8821C BIT(14)
+
+#define BIT_SHIFT_BEQ_DESC_MODE_8821C 12
+#define BIT_MASK_BEQ_DESC_MODE_8821C 0x3
+#define BIT_BEQ_DESC_MODE_8821C(x)                                             \
+	(((x) & BIT_MASK_BEQ_DESC_MODE_8821C) << BIT_SHIFT_BEQ_DESC_MODE_8821C)
+#define BITS_BEQ_DESC_MODE_8821C                                               \
+	(BIT_MASK_BEQ_DESC_MODE_8821C << BIT_SHIFT_BEQ_DESC_MODE_8821C)
+#define BIT_CLEAR_BEQ_DESC_MODE_8821C(x) ((x) & (~BITS_BEQ_DESC_MODE_8821C))
+#define BIT_GET_BEQ_DESC_MODE_8821C(x)                                         \
+	(((x) >> BIT_SHIFT_BEQ_DESC_MODE_8821C) & BIT_MASK_BEQ_DESC_MODE_8821C)
+#define BIT_SET_BEQ_DESC_MODE_8821C(x, v)                                      \
+	(BIT_CLEAR_BEQ_DESC_MODE_8821C(x) | BIT_BEQ_DESC_MODE_8821C(v))
+
+#define BIT_SHIFT_BEQ_DESC_NUM_8821C 0
+#define BIT_MASK_BEQ_DESC_NUM_8821C 0xfff
+#define BIT_BEQ_DESC_NUM_8821C(x)                                              \
+	(((x) & BIT_MASK_BEQ_DESC_NUM_8821C) << BIT_SHIFT_BEQ_DESC_NUM_8821C)
+#define BITS_BEQ_DESC_NUM_8821C                                                \
+	(BIT_MASK_BEQ_DESC_NUM_8821C << BIT_SHIFT_BEQ_DESC_NUM_8821C)
+#define BIT_CLEAR_BEQ_DESC_NUM_8821C(x) ((x) & (~BITS_BEQ_DESC_NUM_8821C))
+#define BIT_GET_BEQ_DESC_NUM_8821C(x)                                          \
+	(((x) >> BIT_SHIFT_BEQ_DESC_NUM_8821C) & BIT_MASK_BEQ_DESC_NUM_8821C)
+#define BIT_SET_BEQ_DESC_NUM_8821C(x, v)                                       \
+	(BIT_CLEAR_BEQ_DESC_NUM_8821C(x) | BIT_BEQ_DESC_NUM_8821C(v))
+
+/* 2 REG_BKQ_TXBD_NUM_8821C */
+#define BIT_PCIE_BKQ_FLAG_8821C BIT(14)
+
+#define BIT_SHIFT_BKQ_DESC_MODE_8821C 12
+#define BIT_MASK_BKQ_DESC_MODE_8821C 0x3
+#define BIT_BKQ_DESC_MODE_8821C(x)                                             \
+	(((x) & BIT_MASK_BKQ_DESC_MODE_8821C) << BIT_SHIFT_BKQ_DESC_MODE_8821C)
+#define BITS_BKQ_DESC_MODE_8821C                                               \
+	(BIT_MASK_BKQ_DESC_MODE_8821C << BIT_SHIFT_BKQ_DESC_MODE_8821C)
+#define BIT_CLEAR_BKQ_DESC_MODE_8821C(x) ((x) & (~BITS_BKQ_DESC_MODE_8821C))
+#define BIT_GET_BKQ_DESC_MODE_8821C(x)                                         \
+	(((x) >> BIT_SHIFT_BKQ_DESC_MODE_8821C) & BIT_MASK_BKQ_DESC_MODE_8821C)
+#define BIT_SET_BKQ_DESC_MODE_8821C(x, v)                                      \
+	(BIT_CLEAR_BKQ_DESC_MODE_8821C(x) | BIT_BKQ_DESC_MODE_8821C(v))
+
+#define BIT_SHIFT_BKQ_DESC_NUM_8821C 0
+#define BIT_MASK_BKQ_DESC_NUM_8821C 0xfff
+#define BIT_BKQ_DESC_NUM_8821C(x)                                              \
+	(((x) & BIT_MASK_BKQ_DESC_NUM_8821C) << BIT_SHIFT_BKQ_DESC_NUM_8821C)
+#define BITS_BKQ_DESC_NUM_8821C                                                \
+	(BIT_MASK_BKQ_DESC_NUM_8821C << BIT_SHIFT_BKQ_DESC_NUM_8821C)
+#define BIT_CLEAR_BKQ_DESC_NUM_8821C(x) ((x) & (~BITS_BKQ_DESC_NUM_8821C))
+#define BIT_GET_BKQ_DESC_NUM_8821C(x)                                          \
+	(((x) >> BIT_SHIFT_BKQ_DESC_NUM_8821C) & BIT_MASK_BKQ_DESC_NUM_8821C)
+#define BIT_SET_BKQ_DESC_NUM_8821C(x, v)                                       \
+	(BIT_CLEAR_BKQ_DESC_NUM_8821C(x) | BIT_BKQ_DESC_NUM_8821C(v))
+
+/* 2 REG_HI0Q_TXBD_NUM_8821C */
+#define BIT_HI0Q_FLAG_8821C BIT(14)
+
+#define BIT_SHIFT_HI0Q_DESC_MODE_8821C 12
+#define BIT_MASK_HI0Q_DESC_MODE_8821C 0x3
+#define BIT_HI0Q_DESC_MODE_8821C(x)                                            \
+	(((x) & BIT_MASK_HI0Q_DESC_MODE_8821C)                                 \
+	 << BIT_SHIFT_HI0Q_DESC_MODE_8821C)
+#define BITS_HI0Q_DESC_MODE_8821C                                              \
+	(BIT_MASK_HI0Q_DESC_MODE_8821C << BIT_SHIFT_HI0Q_DESC_MODE_8821C)
+#define BIT_CLEAR_HI0Q_DESC_MODE_8821C(x) ((x) & (~BITS_HI0Q_DESC_MODE_8821C))
+#define BIT_GET_HI0Q_DESC_MODE_8821C(x)                                        \
+	(((x) >> BIT_SHIFT_HI0Q_DESC_MODE_8821C) &                             \
+	 BIT_MASK_HI0Q_DESC_MODE_8821C)
+#define BIT_SET_HI0Q_DESC_MODE_8821C(x, v)                                     \
+	(BIT_CLEAR_HI0Q_DESC_MODE_8821C(x) | BIT_HI0Q_DESC_MODE_8821C(v))
+
+#define BIT_SHIFT_HI0Q_DESC_NUM_8821C 0
+#define BIT_MASK_HI0Q_DESC_NUM_8821C 0xfff
+#define BIT_HI0Q_DESC_NUM_8821C(x)                                             \
+	(((x) & BIT_MASK_HI0Q_DESC_NUM_8821C) << BIT_SHIFT_HI0Q_DESC_NUM_8821C)
+#define BITS_HI0Q_DESC_NUM_8821C                                               \
+	(BIT_MASK_HI0Q_DESC_NUM_8821C << BIT_SHIFT_HI0Q_DESC_NUM_8821C)
+#define BIT_CLEAR_HI0Q_DESC_NUM_8821C(x) ((x) & (~BITS_HI0Q_DESC_NUM_8821C))
+#define BIT_GET_HI0Q_DESC_NUM_8821C(x)                                         \
+	(((x) >> BIT_SHIFT_HI0Q_DESC_NUM_8821C) & BIT_MASK_HI0Q_DESC_NUM_8821C)
+#define BIT_SET_HI0Q_DESC_NUM_8821C(x, v)                                      \
+	(BIT_CLEAR_HI0Q_DESC_NUM_8821C(x) | BIT_HI0Q_DESC_NUM_8821C(v))
+
+/* 2 REG_HI1Q_TXBD_NUM_8821C */
+#define BIT_HI1Q_FLAG_8821C BIT(14)
+
+#define BIT_SHIFT_HI1Q_DESC_MODE_8821C 12
+#define BIT_MASK_HI1Q_DESC_MODE_8821C 0x3
+#define BIT_HI1Q_DESC_MODE_8821C(x)                                            \
+	(((x) & BIT_MASK_HI1Q_DESC_MODE_8821C)                                 \
+	 << BIT_SHIFT_HI1Q_DESC_MODE_8821C)
+#define BITS_HI1Q_DESC_MODE_8821C                                              \
+	(BIT_MASK_HI1Q_DESC_MODE_8821C << BIT_SHIFT_HI1Q_DESC_MODE_8821C)
+#define BIT_CLEAR_HI1Q_DESC_MODE_8821C(x) ((x) & (~BITS_HI1Q_DESC_MODE_8821C))
+#define BIT_GET_HI1Q_DESC_MODE_8821C(x)                                        \
+	(((x) >> BIT_SHIFT_HI1Q_DESC_MODE_8821C) &                             \
+	 BIT_MASK_HI1Q_DESC_MODE_8821C)
+#define BIT_SET_HI1Q_DESC_MODE_8821C(x, v)                                     \
+	(BIT_CLEAR_HI1Q_DESC_MODE_8821C(x) | BIT_HI1Q_DESC_MODE_8821C(v))
+
+#define BIT_SHIFT_HI1Q_DESC_NUM_8821C 0
+#define BIT_MASK_HI1Q_DESC_NUM_8821C 0xfff
+#define BIT_HI1Q_DESC_NUM_8821C(x)                                             \
+	(((x) & BIT_MASK_HI1Q_DESC_NUM_8821C) << BIT_SHIFT_HI1Q_DESC_NUM_8821C)
+#define BITS_HI1Q_DESC_NUM_8821C                                               \
+	(BIT_MASK_HI1Q_DESC_NUM_8821C << BIT_SHIFT_HI1Q_DESC_NUM_8821C)
+#define BIT_CLEAR_HI1Q_DESC_NUM_8821C(x) ((x) & (~BITS_HI1Q_DESC_NUM_8821C))
+#define BIT_GET_HI1Q_DESC_NUM_8821C(x)                                         \
+	(((x) >> BIT_SHIFT_HI1Q_DESC_NUM_8821C) & BIT_MASK_HI1Q_DESC_NUM_8821C)
+#define BIT_SET_HI1Q_DESC_NUM_8821C(x, v)                                      \
+	(BIT_CLEAR_HI1Q_DESC_NUM_8821C(x) | BIT_HI1Q_DESC_NUM_8821C(v))
+
+/* 2 REG_HI2Q_TXBD_NUM_8821C */
+#define BIT_HI2Q_FLAG_8821C BIT(14)
+
+#define BIT_SHIFT_HI2Q_DESC_MODE_8821C 12
+#define BIT_MASK_HI2Q_DESC_MODE_8821C 0x3
+#define BIT_HI2Q_DESC_MODE_8821C(x)                                            \
+	(((x) & BIT_MASK_HI2Q_DESC_MODE_8821C)                                 \
+	 << BIT_SHIFT_HI2Q_DESC_MODE_8821C)
+#define BITS_HI2Q_DESC_MODE_8821C                                              \
+	(BIT_MASK_HI2Q_DESC_MODE_8821C << BIT_SHIFT_HI2Q_DESC_MODE_8821C)
+#define BIT_CLEAR_HI2Q_DESC_MODE_8821C(x) ((x) & (~BITS_HI2Q_DESC_MODE_8821C))
+#define BIT_GET_HI2Q_DESC_MODE_8821C(x)                                        \
+	(((x) >> BIT_SHIFT_HI2Q_DESC_MODE_8821C) &                             \
+	 BIT_MASK_HI2Q_DESC_MODE_8821C)
+#define BIT_SET_HI2Q_DESC_MODE_8821C(x, v)                                     \
+	(BIT_CLEAR_HI2Q_DESC_MODE_8821C(x) | BIT_HI2Q_DESC_MODE_8821C(v))
+
+#define BIT_SHIFT_HI2Q_DESC_NUM_8821C 0
+#define BIT_MASK_HI2Q_DESC_NUM_8821C 0xfff
+#define BIT_HI2Q_DESC_NUM_8821C(x)                                             \
+	(((x) & BIT_MASK_HI2Q_DESC_NUM_8821C) << BIT_SHIFT_HI2Q_DESC_NUM_8821C)
+#define BITS_HI2Q_DESC_NUM_8821C                                               \
+	(BIT_MASK_HI2Q_DESC_NUM_8821C << BIT_SHIFT_HI2Q_DESC_NUM_8821C)
+#define BIT_CLEAR_HI2Q_DESC_NUM_8821C(x) ((x) & (~BITS_HI2Q_DESC_NUM_8821C))
+#define BIT_GET_HI2Q_DESC_NUM_8821C(x)                                         \
+	(((x) >> BIT_SHIFT_HI2Q_DESC_NUM_8821C) & BIT_MASK_HI2Q_DESC_NUM_8821C)
+#define BIT_SET_HI2Q_DESC_NUM_8821C(x, v)                                      \
+	(BIT_CLEAR_HI2Q_DESC_NUM_8821C(x) | BIT_HI2Q_DESC_NUM_8821C(v))
+
+/* 2 REG_HI3Q_TXBD_NUM_8821C */
+#define BIT_HI3Q_FLAG_8821C BIT(14)
+
+#define BIT_SHIFT_HI3Q_DESC_MODE_8821C 12
+#define BIT_MASK_HI3Q_DESC_MODE_8821C 0x3
+#define BIT_HI3Q_DESC_MODE_8821C(x)                                            \
+	(((x) & BIT_MASK_HI3Q_DESC_MODE_8821C)                                 \
+	 << BIT_SHIFT_HI3Q_DESC_MODE_8821C)
+#define BITS_HI3Q_DESC_MODE_8821C                                              \
+	(BIT_MASK_HI3Q_DESC_MODE_8821C << BIT_SHIFT_HI3Q_DESC_MODE_8821C)
+#define BIT_CLEAR_HI3Q_DESC_MODE_8821C(x) ((x) & (~BITS_HI3Q_DESC_MODE_8821C))
+#define BIT_GET_HI3Q_DESC_MODE_8821C(x)                                        \
+	(((x) >> BIT_SHIFT_HI3Q_DESC_MODE_8821C) &                             \
+	 BIT_MASK_HI3Q_DESC_MODE_8821C)
+#define BIT_SET_HI3Q_DESC_MODE_8821C(x, v)                                     \
+	(BIT_CLEAR_HI3Q_DESC_MODE_8821C(x) | BIT_HI3Q_DESC_MODE_8821C(v))
+
+#define BIT_SHIFT_HI3Q_DESC_NUM_8821C 0
+#define BIT_MASK_HI3Q_DESC_NUM_8821C 0xfff
+#define BIT_HI3Q_DESC_NUM_8821C(x)                                             \
+	(((x) & BIT_MASK_HI3Q_DESC_NUM_8821C) << BIT_SHIFT_HI3Q_DESC_NUM_8821C)
+#define BITS_HI3Q_DESC_NUM_8821C                                               \
+	(BIT_MASK_HI3Q_DESC_NUM_8821C << BIT_SHIFT_HI3Q_DESC_NUM_8821C)
+#define BIT_CLEAR_HI3Q_DESC_NUM_8821C(x) ((x) & (~BITS_HI3Q_DESC_NUM_8821C))
+#define BIT_GET_HI3Q_DESC_NUM_8821C(x)                                         \
+	(((x) >> BIT_SHIFT_HI3Q_DESC_NUM_8821C) & BIT_MASK_HI3Q_DESC_NUM_8821C)
+#define BIT_SET_HI3Q_DESC_NUM_8821C(x, v)                                      \
+	(BIT_CLEAR_HI3Q_DESC_NUM_8821C(x) | BIT_HI3Q_DESC_NUM_8821C(v))
+
+/* 2 REG_HI4Q_TXBD_NUM_8821C */
+#define BIT_HI4Q_FLAG_8821C BIT(14)
+
+#define BIT_SHIFT_HI4Q_DESC_MODE_8821C 12
+#define BIT_MASK_HI4Q_DESC_MODE_8821C 0x3
+#define BIT_HI4Q_DESC_MODE_8821C(x)                                            \
+	(((x) & BIT_MASK_HI4Q_DESC_MODE_8821C)                                 \
+	 << BIT_SHIFT_HI4Q_DESC_MODE_8821C)
+#define BITS_HI4Q_DESC_MODE_8821C                                              \
+	(BIT_MASK_HI4Q_DESC_MODE_8821C << BIT_SHIFT_HI4Q_DESC_MODE_8821C)
+#define BIT_CLEAR_HI4Q_DESC_MODE_8821C(x) ((x) & (~BITS_HI4Q_DESC_MODE_8821C))
+#define BIT_GET_HI4Q_DESC_MODE_8821C(x)                                        \
+	(((x) >> BIT_SHIFT_HI4Q_DESC_MODE_8821C) &                             \
+	 BIT_MASK_HI4Q_DESC_MODE_8821C)
+#define BIT_SET_HI4Q_DESC_MODE_8821C(x, v)                                     \
+	(BIT_CLEAR_HI4Q_DESC_MODE_8821C(x) | BIT_HI4Q_DESC_MODE_8821C(v))
+
+#define BIT_SHIFT_HI4Q_DESC_NUM_8821C 0
+#define BIT_MASK_HI4Q_DESC_NUM_8821C 0xfff
+#define BIT_HI4Q_DESC_NUM_8821C(x)                                             \
+	(((x) & BIT_MASK_HI4Q_DESC_NUM_8821C) << BIT_SHIFT_HI4Q_DESC_NUM_8821C)
+#define BITS_HI4Q_DESC_NUM_8821C                                               \
+	(BIT_MASK_HI4Q_DESC_NUM_8821C << BIT_SHIFT_HI4Q_DESC_NUM_8821C)
+#define BIT_CLEAR_HI4Q_DESC_NUM_8821C(x) ((x) & (~BITS_HI4Q_DESC_NUM_8821C))
+#define BIT_GET_HI4Q_DESC_NUM_8821C(x)                                         \
+	(((x) >> BIT_SHIFT_HI4Q_DESC_NUM_8821C) & BIT_MASK_HI4Q_DESC_NUM_8821C)
+#define BIT_SET_HI4Q_DESC_NUM_8821C(x, v)                                      \
+	(BIT_CLEAR_HI4Q_DESC_NUM_8821C(x) | BIT_HI4Q_DESC_NUM_8821C(v))
+
+/* 2 REG_HI5Q_TXBD_NUM_8821C */
+#define BIT_HI5Q_FLAG_8821C BIT(14)
+
+#define BIT_SHIFT_HI5Q_DESC_MODE_8821C 12
+#define BIT_MASK_HI5Q_DESC_MODE_8821C 0x3
+#define BIT_HI5Q_DESC_MODE_8821C(x)                                            \
+	(((x) & BIT_MASK_HI5Q_DESC_MODE_8821C)                                 \
+	 << BIT_SHIFT_HI5Q_DESC_MODE_8821C)
+#define BITS_HI5Q_DESC_MODE_8821C                                              \
+	(BIT_MASK_HI5Q_DESC_MODE_8821C << BIT_SHIFT_HI5Q_DESC_MODE_8821C)
+#define BIT_CLEAR_HI5Q_DESC_MODE_8821C(x) ((x) & (~BITS_HI5Q_DESC_MODE_8821C))
+#define BIT_GET_HI5Q_DESC_MODE_8821C(x)                                        \
+	(((x) >> BIT_SHIFT_HI5Q_DESC_MODE_8821C) &                             \
+	 BIT_MASK_HI5Q_DESC_MODE_8821C)
+#define BIT_SET_HI5Q_DESC_MODE_8821C(x, v)                                     \
+	(BIT_CLEAR_HI5Q_DESC_MODE_8821C(x) | BIT_HI5Q_DESC_MODE_8821C(v))
+
+#define BIT_SHIFT_HI5Q_DESC_NUM_8821C 0
+#define BIT_MASK_HI5Q_DESC_NUM_8821C 0xfff
+#define BIT_HI5Q_DESC_NUM_8821C(x)                                             \
+	(((x) & BIT_MASK_HI5Q_DESC_NUM_8821C) << BIT_SHIFT_HI5Q_DESC_NUM_8821C)
+#define BITS_HI5Q_DESC_NUM_8821C                                               \
+	(BIT_MASK_HI5Q_DESC_NUM_8821C << BIT_SHIFT_HI5Q_DESC_NUM_8821C)
+#define BIT_CLEAR_HI5Q_DESC_NUM_8821C(x) ((x) & (~BITS_HI5Q_DESC_NUM_8821C))
+#define BIT_GET_HI5Q_DESC_NUM_8821C(x)                                         \
+	(((x) >> BIT_SHIFT_HI5Q_DESC_NUM_8821C) & BIT_MASK_HI5Q_DESC_NUM_8821C)
+#define BIT_SET_HI5Q_DESC_NUM_8821C(x, v)                                      \
+	(BIT_CLEAR_HI5Q_DESC_NUM_8821C(x) | BIT_HI5Q_DESC_NUM_8821C(v))
+
+/* 2 REG_HI6Q_TXBD_NUM_8821C */
+#define BIT_HI6Q_FLAG_8821C BIT(14)
+
+#define BIT_SHIFT_HI6Q_DESC_MODE_8821C 12
+#define BIT_MASK_HI6Q_DESC_MODE_8821C 0x3
+#define BIT_HI6Q_DESC_MODE_8821C(x)                                            \
+	(((x) & BIT_MASK_HI6Q_DESC_MODE_8821C)                                 \
+	 << BIT_SHIFT_HI6Q_DESC_MODE_8821C)
+#define BITS_HI6Q_DESC_MODE_8821C                                              \
+	(BIT_MASK_HI6Q_DESC_MODE_8821C << BIT_SHIFT_HI6Q_DESC_MODE_8821C)
+#define BIT_CLEAR_HI6Q_DESC_MODE_8821C(x) ((x) & (~BITS_HI6Q_DESC_MODE_8821C))
+#define BIT_GET_HI6Q_DESC_MODE_8821C(x)                                        \
+	(((x) >> BIT_SHIFT_HI6Q_DESC_MODE_8821C) &                             \
+	 BIT_MASK_HI6Q_DESC_MODE_8821C)
+#define BIT_SET_HI6Q_DESC_MODE_8821C(x, v)                                     \
+	(BIT_CLEAR_HI6Q_DESC_MODE_8821C(x) | BIT_HI6Q_DESC_MODE_8821C(v))
+
+#define BIT_SHIFT_HI6Q_DESC_NUM_8821C 0
+#define BIT_MASK_HI6Q_DESC_NUM_8821C 0xfff
+#define BIT_HI6Q_DESC_NUM_8821C(x)                                             \
+	(((x) & BIT_MASK_HI6Q_DESC_NUM_8821C) << BIT_SHIFT_HI6Q_DESC_NUM_8821C)
+#define BITS_HI6Q_DESC_NUM_8821C                                               \
+	(BIT_MASK_HI6Q_DESC_NUM_8821C << BIT_SHIFT_HI6Q_DESC_NUM_8821C)
+#define BIT_CLEAR_HI6Q_DESC_NUM_8821C(x) ((x) & (~BITS_HI6Q_DESC_NUM_8821C))
+#define BIT_GET_HI6Q_DESC_NUM_8821C(x)                                         \
+	(((x) >> BIT_SHIFT_HI6Q_DESC_NUM_8821C) & BIT_MASK_HI6Q_DESC_NUM_8821C)
+#define BIT_SET_HI6Q_DESC_NUM_8821C(x, v)                                      \
+	(BIT_CLEAR_HI6Q_DESC_NUM_8821C(x) | BIT_HI6Q_DESC_NUM_8821C(v))
+
+/* 2 REG_HI7Q_TXBD_NUM_8821C */
+#define BIT_HI7Q_FLAG_8821C BIT(14)
+
+#define BIT_SHIFT_HI7Q_DESC_MODE_8821C 12
+#define BIT_MASK_HI7Q_DESC_MODE_8821C 0x3
+#define BIT_HI7Q_DESC_MODE_8821C(x)                                            \
+	(((x) & BIT_MASK_HI7Q_DESC_MODE_8821C)                                 \
+	 << BIT_SHIFT_HI7Q_DESC_MODE_8821C)
+#define BITS_HI7Q_DESC_MODE_8821C                                              \
+	(BIT_MASK_HI7Q_DESC_MODE_8821C << BIT_SHIFT_HI7Q_DESC_MODE_8821C)
+#define BIT_CLEAR_HI7Q_DESC_MODE_8821C(x) ((x) & (~BITS_HI7Q_DESC_MODE_8821C))
+#define BIT_GET_HI7Q_DESC_MODE_8821C(x)                                        \
+	(((x) >> BIT_SHIFT_HI7Q_DESC_MODE_8821C) &                             \
+	 BIT_MASK_HI7Q_DESC_MODE_8821C)
+#define BIT_SET_HI7Q_DESC_MODE_8821C(x, v)                                     \
+	(BIT_CLEAR_HI7Q_DESC_MODE_8821C(x) | BIT_HI7Q_DESC_MODE_8821C(v))
+
+#define BIT_SHIFT_HI7Q_DESC_NUM_8821C 0
+#define BIT_MASK_HI7Q_DESC_NUM_8821C 0xfff
+#define BIT_HI7Q_DESC_NUM_8821C(x)                                             \
+	(((x) & BIT_MASK_HI7Q_DESC_NUM_8821C) << BIT_SHIFT_HI7Q_DESC_NUM_8821C)
+#define BITS_HI7Q_DESC_NUM_8821C                                               \
+	(BIT_MASK_HI7Q_DESC_NUM_8821C << BIT_SHIFT_HI7Q_DESC_NUM_8821C)
+#define BIT_CLEAR_HI7Q_DESC_NUM_8821C(x) ((x) & (~BITS_HI7Q_DESC_NUM_8821C))
+#define BIT_GET_HI7Q_DESC_NUM_8821C(x)                                         \
+	(((x) >> BIT_SHIFT_HI7Q_DESC_NUM_8821C) & BIT_MASK_HI7Q_DESC_NUM_8821C)
+#define BIT_SET_HI7Q_DESC_NUM_8821C(x, v)                                      \
+	(BIT_CLEAR_HI7Q_DESC_NUM_8821C(x) | BIT_HI7Q_DESC_NUM_8821C(v))
+
+/* 2 REG_TSFTIMER_HCI_8821C */
+
+#define BIT_SHIFT_TSFT2_HCI_8821C 16
+#define BIT_MASK_TSFT2_HCI_8821C 0xffff
+#define BIT_TSFT2_HCI_8821C(x)                                                 \
+	(((x) & BIT_MASK_TSFT2_HCI_8821C) << BIT_SHIFT_TSFT2_HCI_8821C)
+#define BITS_TSFT2_HCI_8821C                                                   \
+	(BIT_MASK_TSFT2_HCI_8821C << BIT_SHIFT_TSFT2_HCI_8821C)
+#define BIT_CLEAR_TSFT2_HCI_8821C(x) ((x) & (~BITS_TSFT2_HCI_8821C))
+#define BIT_GET_TSFT2_HCI_8821C(x)                                             \
+	(((x) >> BIT_SHIFT_TSFT2_HCI_8821C) & BIT_MASK_TSFT2_HCI_8821C)
+#define BIT_SET_TSFT2_HCI_8821C(x, v)                                          \
+	(BIT_CLEAR_TSFT2_HCI_8821C(x) | BIT_TSFT2_HCI_8821C(v))
+
+#define BIT_SHIFT_TSFT1_HCI_8821C 0
+#define BIT_MASK_TSFT1_HCI_8821C 0xffff
+#define BIT_TSFT1_HCI_8821C(x)                                                 \
+	(((x) & BIT_MASK_TSFT1_HCI_8821C) << BIT_SHIFT_TSFT1_HCI_8821C)
+#define BITS_TSFT1_HCI_8821C                                                   \
+	(BIT_MASK_TSFT1_HCI_8821C << BIT_SHIFT_TSFT1_HCI_8821C)
+#define BIT_CLEAR_TSFT1_HCI_8821C(x) ((x) & (~BITS_TSFT1_HCI_8821C))
+#define BIT_GET_TSFT1_HCI_8821C(x)                                             \
+	(((x) >> BIT_SHIFT_TSFT1_HCI_8821C) & BIT_MASK_TSFT1_HCI_8821C)
+#define BIT_SET_TSFT1_HCI_8821C(x, v)                                          \
+	(BIT_CLEAR_TSFT1_HCI_8821C(x) | BIT_TSFT1_HCI_8821C(v))
+
+/* 2 REG_BD_RWPTR_CLR_8821C */
+#define BIT_CLR_HI7Q_HW_IDX_8821C BIT(29)
+#define BIT_CLR_HI6Q_HW_IDX_8821C BIT(28)
+#define BIT_CLR_HI5Q_HW_IDX_8821C BIT(27)
+#define BIT_CLR_HI4Q_HW_IDX_8821C BIT(26)
+#define BIT_CLR_HI3Q_HW_IDX_8821C BIT(25)
+#define BIT_CLR_HI2Q_HW_IDX_8821C BIT(24)
+#define BIT_CLR_HI1Q_HW_IDX_8821C BIT(23)
+#define BIT_CLR_HI0Q_HW_IDX_8821C BIT(22)
+#define BIT_CLR_BKQ_HW_IDX_8821C BIT(21)
+#define BIT_CLR_BEQ_HW_IDX_8821C BIT(20)
+#define BIT_CLR_VIQ_HW_IDX_8821C BIT(19)
+#define BIT_CLR_VOQ_HW_IDX_8821C BIT(18)
+#define BIT_CLR_MGQ_HW_IDX_8821C BIT(17)
+#define BIT_CLR_RXQ_HW_IDX_8821C BIT(16)
+#define BIT_CLR_HI7Q_HOST_IDX_8821C BIT(13)
+#define BIT_CLR_HI6Q_HOST_IDX_8821C BIT(12)
+#define BIT_CLR_HI5Q_HOST_IDX_8821C BIT(11)
+#define BIT_CLR_HI4Q_HOST_IDX_8821C BIT(10)
+#define BIT_CLR_HI3Q_HOST_IDX_8821C BIT(9)
+#define BIT_CLR_HI2Q_HOST_IDX_8821C BIT(8)
+#define BIT_CLR_HI1Q_HOST_IDX_8821C BIT(7)
+#define BIT_CLR_HI0Q_HOST_IDX_8821C BIT(6)
+#define BIT_CLR_BKQ_HOST_IDX_8821C BIT(5)
+#define BIT_CLR_BEQ_HOST_IDX_8821C BIT(4)
+#define BIT_CLR_VIQ_HOST_IDX_8821C BIT(3)
+#define BIT_CLR_VOQ_HOST_IDX_8821C BIT(2)
+#define BIT_CLR_MGQ_HOST_IDX_8821C BIT(1)
+#define BIT_CLR_RXQ_HOST_IDX_8821C BIT(0)
+
+/* 2 REG_VOQ_TXBD_IDX_8821C */
+
+#define BIT_SHIFT_VOQ_HW_IDX_8821C 16
+#define BIT_MASK_VOQ_HW_IDX_8821C 0xfff
+#define BIT_VOQ_HW_IDX_8821C(x)                                                \
+	(((x) & BIT_MASK_VOQ_HW_IDX_8821C) << BIT_SHIFT_VOQ_HW_IDX_8821C)
+#define BITS_VOQ_HW_IDX_8821C                                                  \
+	(BIT_MASK_VOQ_HW_IDX_8821C << BIT_SHIFT_VOQ_HW_IDX_8821C)
+#define BIT_CLEAR_VOQ_HW_IDX_8821C(x) ((x) & (~BITS_VOQ_HW_IDX_8821C))
+#define BIT_GET_VOQ_HW_IDX_8821C(x)                                            \
+	(((x) >> BIT_SHIFT_VOQ_HW_IDX_8821C) & BIT_MASK_VOQ_HW_IDX_8821C)
+#define BIT_SET_VOQ_HW_IDX_8821C(x, v)                                         \
+	(BIT_CLEAR_VOQ_HW_IDX_8821C(x) | BIT_VOQ_HW_IDX_8821C(v))
+
+#define BIT_SHIFT_VOQ_HOST_IDX_8821C 0
+#define BIT_MASK_VOQ_HOST_IDX_8821C 0xfff
+#define BIT_VOQ_HOST_IDX_8821C(x)                                              \
+	(((x) & BIT_MASK_VOQ_HOST_IDX_8821C) << BIT_SHIFT_VOQ_HOST_IDX_8821C)
+#define BITS_VOQ_HOST_IDX_8821C                                                \
+	(BIT_MASK_VOQ_HOST_IDX_8821C << BIT_SHIFT_VOQ_HOST_IDX_8821C)
+#define BIT_CLEAR_VOQ_HOST_IDX_8821C(x) ((x) & (~BITS_VOQ_HOST_IDX_8821C))
+#define BIT_GET_VOQ_HOST_IDX_8821C(x)                                          \
+	(((x) >> BIT_SHIFT_VOQ_HOST_IDX_8821C) & BIT_MASK_VOQ_HOST_IDX_8821C)
+#define BIT_SET_VOQ_HOST_IDX_8821C(x, v)                                       \
+	(BIT_CLEAR_VOQ_HOST_IDX_8821C(x) | BIT_VOQ_HOST_IDX_8821C(v))
+
+/* 2 REG_VIQ_TXBD_IDX_8821C */
+
+#define BIT_SHIFT_VIQ_HW_IDX_8821C 16
+#define BIT_MASK_VIQ_HW_IDX_8821C 0xfff
+#define BIT_VIQ_HW_IDX_8821C(x)                                                \
+	(((x) & BIT_MASK_VIQ_HW_IDX_8821C) << BIT_SHIFT_VIQ_HW_IDX_8821C)
+#define BITS_VIQ_HW_IDX_8821C                                                  \
+	(BIT_MASK_VIQ_HW_IDX_8821C << BIT_SHIFT_VIQ_HW_IDX_8821C)
+#define BIT_CLEAR_VIQ_HW_IDX_8821C(x) ((x) & (~BITS_VIQ_HW_IDX_8821C))
+#define BIT_GET_VIQ_HW_IDX_8821C(x)                                            \
+	(((x) >> BIT_SHIFT_VIQ_HW_IDX_8821C) & BIT_MASK_VIQ_HW_IDX_8821C)
+#define BIT_SET_VIQ_HW_IDX_8821C(x, v)                                         \
+	(BIT_CLEAR_VIQ_HW_IDX_8821C(x) | BIT_VIQ_HW_IDX_8821C(v))
+
+#define BIT_SHIFT_VIQ_HOST_IDX_8821C 0
+#define BIT_MASK_VIQ_HOST_IDX_8821C 0xfff
+#define BIT_VIQ_HOST_IDX_8821C(x)                                              \
+	(((x) & BIT_MASK_VIQ_HOST_IDX_8821C) << BIT_SHIFT_VIQ_HOST_IDX_8821C)
+#define BITS_VIQ_HOST_IDX_8821C                                                \
+	(BIT_MASK_VIQ_HOST_IDX_8821C << BIT_SHIFT_VIQ_HOST_IDX_8821C)
+#define BIT_CLEAR_VIQ_HOST_IDX_8821C(x) ((x) & (~BITS_VIQ_HOST_IDX_8821C))
+#define BIT_GET_VIQ_HOST_IDX_8821C(x)                                          \
+	(((x) >> BIT_SHIFT_VIQ_HOST_IDX_8821C) & BIT_MASK_VIQ_HOST_IDX_8821C)
+#define BIT_SET_VIQ_HOST_IDX_8821C(x, v)                                       \
+	(BIT_CLEAR_VIQ_HOST_IDX_8821C(x) | BIT_VIQ_HOST_IDX_8821C(v))
+
+/* 2 REG_BEQ_TXBD_IDX_8821C */
+
+#define BIT_SHIFT_BEQ_HW_IDX_8821C 16
+#define BIT_MASK_BEQ_HW_IDX_8821C 0xfff
+#define BIT_BEQ_HW_IDX_8821C(x)                                                \
+	(((x) & BIT_MASK_BEQ_HW_IDX_8821C) << BIT_SHIFT_BEQ_HW_IDX_8821C)
+#define BITS_BEQ_HW_IDX_8821C                                                  \
+	(BIT_MASK_BEQ_HW_IDX_8821C << BIT_SHIFT_BEQ_HW_IDX_8821C)
+#define BIT_CLEAR_BEQ_HW_IDX_8821C(x) ((x) & (~BITS_BEQ_HW_IDX_8821C))
+#define BIT_GET_BEQ_HW_IDX_8821C(x)                                            \
+	(((x) >> BIT_SHIFT_BEQ_HW_IDX_8821C) & BIT_MASK_BEQ_HW_IDX_8821C)
+#define BIT_SET_BEQ_HW_IDX_8821C(x, v)                                         \
+	(BIT_CLEAR_BEQ_HW_IDX_8821C(x) | BIT_BEQ_HW_IDX_8821C(v))
+
+#define BIT_SHIFT_BEQ_HOST_IDX_8821C 0
+#define BIT_MASK_BEQ_HOST_IDX_8821C 0xfff
+#define BIT_BEQ_HOST_IDX_8821C(x)                                              \
+	(((x) & BIT_MASK_BEQ_HOST_IDX_8821C) << BIT_SHIFT_BEQ_HOST_IDX_8821C)
+#define BITS_BEQ_HOST_IDX_8821C                                                \
+	(BIT_MASK_BEQ_HOST_IDX_8821C << BIT_SHIFT_BEQ_HOST_IDX_8821C)
+#define BIT_CLEAR_BEQ_HOST_IDX_8821C(x) ((x) & (~BITS_BEQ_HOST_IDX_8821C))
+#define BIT_GET_BEQ_HOST_IDX_8821C(x)                                          \
+	(((x) >> BIT_SHIFT_BEQ_HOST_IDX_8821C) & BIT_MASK_BEQ_HOST_IDX_8821C)
+#define BIT_SET_BEQ_HOST_IDX_8821C(x, v)                                       \
+	(BIT_CLEAR_BEQ_HOST_IDX_8821C(x) | BIT_BEQ_HOST_IDX_8821C(v))
+
+/* 2 REG_BKQ_TXBD_IDX_8821C */
+
+#define BIT_SHIFT_BKQ_HW_IDX_8821C 16
+#define BIT_MASK_BKQ_HW_IDX_8821C 0xfff
+#define BIT_BKQ_HW_IDX_8821C(x)                                                \
+	(((x) & BIT_MASK_BKQ_HW_IDX_8821C) << BIT_SHIFT_BKQ_HW_IDX_8821C)
+#define BITS_BKQ_HW_IDX_8821C                                                  \
+	(BIT_MASK_BKQ_HW_IDX_8821C << BIT_SHIFT_BKQ_HW_IDX_8821C)
+#define BIT_CLEAR_BKQ_HW_IDX_8821C(x) ((x) & (~BITS_BKQ_HW_IDX_8821C))
+#define BIT_GET_BKQ_HW_IDX_8821C(x)                                            \
+	(((x) >> BIT_SHIFT_BKQ_HW_IDX_8821C) & BIT_MASK_BKQ_HW_IDX_8821C)
+#define BIT_SET_BKQ_HW_IDX_8821C(x, v)                                         \
+	(BIT_CLEAR_BKQ_HW_IDX_8821C(x) | BIT_BKQ_HW_IDX_8821C(v))
+
+#define BIT_SHIFT_BKQ_HOST_IDX_8821C 0
+#define BIT_MASK_BKQ_HOST_IDX_8821C 0xfff
+#define BIT_BKQ_HOST_IDX_8821C(x)                                              \
+	(((x) & BIT_MASK_BKQ_HOST_IDX_8821C) << BIT_SHIFT_BKQ_HOST_IDX_8821C)
+#define BITS_BKQ_HOST_IDX_8821C                                                \
+	(BIT_MASK_BKQ_HOST_IDX_8821C << BIT_SHIFT_BKQ_HOST_IDX_8821C)
+#define BIT_CLEAR_BKQ_HOST_IDX_8821C(x) ((x) & (~BITS_BKQ_HOST_IDX_8821C))
+#define BIT_GET_BKQ_HOST_IDX_8821C(x)                                          \
+	(((x) >> BIT_SHIFT_BKQ_HOST_IDX_8821C) & BIT_MASK_BKQ_HOST_IDX_8821C)
+#define BIT_SET_BKQ_HOST_IDX_8821C(x, v)                                       \
+	(BIT_CLEAR_BKQ_HOST_IDX_8821C(x) | BIT_BKQ_HOST_IDX_8821C(v))
+
+/* 2 REG_MGQ_TXBD_IDX_8821C */
+
+#define BIT_SHIFT_MGQ_HW_IDX_8821C 16
+#define BIT_MASK_MGQ_HW_IDX_8821C 0xfff
+#define BIT_MGQ_HW_IDX_8821C(x)                                                \
+	(((x) & BIT_MASK_MGQ_HW_IDX_8821C) << BIT_SHIFT_MGQ_HW_IDX_8821C)
+#define BITS_MGQ_HW_IDX_8821C                                                  \
+	(BIT_MASK_MGQ_HW_IDX_8821C << BIT_SHIFT_MGQ_HW_IDX_8821C)
+#define BIT_CLEAR_MGQ_HW_IDX_8821C(x) ((x) & (~BITS_MGQ_HW_IDX_8821C))
+#define BIT_GET_MGQ_HW_IDX_8821C(x)                                            \
+	(((x) >> BIT_SHIFT_MGQ_HW_IDX_8821C) & BIT_MASK_MGQ_HW_IDX_8821C)
+#define BIT_SET_MGQ_HW_IDX_8821C(x, v)                                         \
+	(BIT_CLEAR_MGQ_HW_IDX_8821C(x) | BIT_MGQ_HW_IDX_8821C(v))
+
+#define BIT_SHIFT_MGQ_HOST_IDX_8821C 0
+#define BIT_MASK_MGQ_HOST_IDX_8821C 0xfff
+#define BIT_MGQ_HOST_IDX_8821C(x)                                              \
+	(((x) & BIT_MASK_MGQ_HOST_IDX_8821C) << BIT_SHIFT_MGQ_HOST_IDX_8821C)
+#define BITS_MGQ_HOST_IDX_8821C                                                \
+	(BIT_MASK_MGQ_HOST_IDX_8821C << BIT_SHIFT_MGQ_HOST_IDX_8821C)
+#define BIT_CLEAR_MGQ_HOST_IDX_8821C(x) ((x) & (~BITS_MGQ_HOST_IDX_8821C))
+#define BIT_GET_MGQ_HOST_IDX_8821C(x)                                          \
+	(((x) >> BIT_SHIFT_MGQ_HOST_IDX_8821C) & BIT_MASK_MGQ_HOST_IDX_8821C)
+#define BIT_SET_MGQ_HOST_IDX_8821C(x, v)                                       \
+	(BIT_CLEAR_MGQ_HOST_IDX_8821C(x) | BIT_MGQ_HOST_IDX_8821C(v))
+
+/* 2 REG_RXQ_RXBD_IDX_8821C */
+
+#define BIT_SHIFT_RXQ_HW_IDX_8821C 16
+#define BIT_MASK_RXQ_HW_IDX_8821C 0xfff
+#define BIT_RXQ_HW_IDX_8821C(x)                                                \
+	(((x) & BIT_MASK_RXQ_HW_IDX_8821C) << BIT_SHIFT_RXQ_HW_IDX_8821C)
+#define BITS_RXQ_HW_IDX_8821C                                                  \
+	(BIT_MASK_RXQ_HW_IDX_8821C << BIT_SHIFT_RXQ_HW_IDX_8821C)
+#define BIT_CLEAR_RXQ_HW_IDX_8821C(x) ((x) & (~BITS_RXQ_HW_IDX_8821C))
+#define BIT_GET_RXQ_HW_IDX_8821C(x)                                            \
+	(((x) >> BIT_SHIFT_RXQ_HW_IDX_8821C) & BIT_MASK_RXQ_HW_IDX_8821C)
+#define BIT_SET_RXQ_HW_IDX_8821C(x, v)                                         \
+	(BIT_CLEAR_RXQ_HW_IDX_8821C(x) | BIT_RXQ_HW_IDX_8821C(v))
+
+#define BIT_SHIFT_RXQ_HOST_IDX_8821C 0
+#define BIT_MASK_RXQ_HOST_IDX_8821C 0xfff
+#define BIT_RXQ_HOST_IDX_8821C(x)                                              \
+	(((x) & BIT_MASK_RXQ_HOST_IDX_8821C) << BIT_SHIFT_RXQ_HOST_IDX_8821C)
+#define BITS_RXQ_HOST_IDX_8821C                                                \
+	(BIT_MASK_RXQ_HOST_IDX_8821C << BIT_SHIFT_RXQ_HOST_IDX_8821C)
+#define BIT_CLEAR_RXQ_HOST_IDX_8821C(x) ((x) & (~BITS_RXQ_HOST_IDX_8821C))
+#define BIT_GET_RXQ_HOST_IDX_8821C(x)                                          \
+	(((x) >> BIT_SHIFT_RXQ_HOST_IDX_8821C) & BIT_MASK_RXQ_HOST_IDX_8821C)
+#define BIT_SET_RXQ_HOST_IDX_8821C(x, v)                                       \
+	(BIT_CLEAR_RXQ_HOST_IDX_8821C(x) | BIT_RXQ_HOST_IDX_8821C(v))
+
+/* 2 REG_HI0Q_TXBD_IDX_8821C */
+
+#define BIT_SHIFT_HI0Q_HW_IDX_8821C 16
+#define BIT_MASK_HI0Q_HW_IDX_8821C 0xfff
+#define BIT_HI0Q_HW_IDX_8821C(x)                                               \
+	(((x) & BIT_MASK_HI0Q_HW_IDX_8821C) << BIT_SHIFT_HI0Q_HW_IDX_8821C)
+#define BITS_HI0Q_HW_IDX_8821C                                                 \
+	(BIT_MASK_HI0Q_HW_IDX_8821C << BIT_SHIFT_HI0Q_HW_IDX_8821C)
+#define BIT_CLEAR_HI0Q_HW_IDX_8821C(x) ((x) & (~BITS_HI0Q_HW_IDX_8821C))
+#define BIT_GET_HI0Q_HW_IDX_8821C(x)                                           \
+	(((x) >> BIT_SHIFT_HI0Q_HW_IDX_8821C) & BIT_MASK_HI0Q_HW_IDX_8821C)
+#define BIT_SET_HI0Q_HW_IDX_8821C(x, v)                                        \
+	(BIT_CLEAR_HI0Q_HW_IDX_8821C(x) | BIT_HI0Q_HW_IDX_8821C(v))
+
+#define BIT_SHIFT_HI0Q_HOST_IDX_8821C 0
+#define BIT_MASK_HI0Q_HOST_IDX_8821C 0xfff
+#define BIT_HI0Q_HOST_IDX_8821C(x)                                             \
+	(((x) & BIT_MASK_HI0Q_HOST_IDX_8821C) << BIT_SHIFT_HI0Q_HOST_IDX_8821C)
+#define BITS_HI0Q_HOST_IDX_8821C                                               \
+	(BIT_MASK_HI0Q_HOST_IDX_8821C << BIT_SHIFT_HI0Q_HOST_IDX_8821C)
+#define BIT_CLEAR_HI0Q_HOST_IDX_8821C(x) ((x) & (~BITS_HI0Q_HOST_IDX_8821C))
+#define BIT_GET_HI0Q_HOST_IDX_8821C(x)                                         \
+	(((x) >> BIT_SHIFT_HI0Q_HOST_IDX_8821C) & BIT_MASK_HI0Q_HOST_IDX_8821C)
+#define BIT_SET_HI0Q_HOST_IDX_8821C(x, v)                                      \
+	(BIT_CLEAR_HI0Q_HOST_IDX_8821C(x) | BIT_HI0Q_HOST_IDX_8821C(v))
+
+/* 2 REG_HI1Q_TXBD_IDX_8821C */
+
+#define BIT_SHIFT_HI1Q_HW_IDX_8821C 16
+#define BIT_MASK_HI1Q_HW_IDX_8821C 0xfff
+#define BIT_HI1Q_HW_IDX_8821C(x)                                               \
+	(((x) & BIT_MASK_HI1Q_HW_IDX_8821C) << BIT_SHIFT_HI1Q_HW_IDX_8821C)
+#define BITS_HI1Q_HW_IDX_8821C                                                 \
+	(BIT_MASK_HI1Q_HW_IDX_8821C << BIT_SHIFT_HI1Q_HW_IDX_8821C)
+#define BIT_CLEAR_HI1Q_HW_IDX_8821C(x) ((x) & (~BITS_HI1Q_HW_IDX_8821C))
+#define BIT_GET_HI1Q_HW_IDX_8821C(x)                                           \
+	(((x) >> BIT_SHIFT_HI1Q_HW_IDX_8821C) & BIT_MASK_HI1Q_HW_IDX_8821C)
+#define BIT_SET_HI1Q_HW_IDX_8821C(x, v)                                        \
+	(BIT_CLEAR_HI1Q_HW_IDX_8821C(x) | BIT_HI1Q_HW_IDX_8821C(v))
+
+#define BIT_SHIFT_HI1Q_HOST_IDX_8821C 0
+#define BIT_MASK_HI1Q_HOST_IDX_8821C 0xfff
+#define BIT_HI1Q_HOST_IDX_8821C(x)                                             \
+	(((x) & BIT_MASK_HI1Q_HOST_IDX_8821C) << BIT_SHIFT_HI1Q_HOST_IDX_8821C)
+#define BITS_HI1Q_HOST_IDX_8821C                                               \
+	(BIT_MASK_HI1Q_HOST_IDX_8821C << BIT_SHIFT_HI1Q_HOST_IDX_8821C)
+#define BIT_CLEAR_HI1Q_HOST_IDX_8821C(x) ((x) & (~BITS_HI1Q_HOST_IDX_8821C))
+#define BIT_GET_HI1Q_HOST_IDX_8821C(x)                                         \
+	(((x) >> BIT_SHIFT_HI1Q_HOST_IDX_8821C) & BIT_MASK_HI1Q_HOST_IDX_8821C)
+#define BIT_SET_HI1Q_HOST_IDX_8821C(x, v)                                      \
+	(BIT_CLEAR_HI1Q_HOST_IDX_8821C(x) | BIT_HI1Q_HOST_IDX_8821C(v))
+
+/* 2 REG_HI2Q_TXBD_IDX_8821C */
+
+#define BIT_SHIFT_HI2Q_HW_IDX_8821C 16
+#define BIT_MASK_HI2Q_HW_IDX_8821C 0xfff
+#define BIT_HI2Q_HW_IDX_8821C(x)                                               \
+	(((x) & BIT_MASK_HI2Q_HW_IDX_8821C) << BIT_SHIFT_HI2Q_HW_IDX_8821C)
+#define BITS_HI2Q_HW_IDX_8821C                                                 \
+	(BIT_MASK_HI2Q_HW_IDX_8821C << BIT_SHIFT_HI2Q_HW_IDX_8821C)
+#define BIT_CLEAR_HI2Q_HW_IDX_8821C(x) ((x) & (~BITS_HI2Q_HW_IDX_8821C))
+#define BIT_GET_HI2Q_HW_IDX_8821C(x)                                           \
+	(((x) >> BIT_SHIFT_HI2Q_HW_IDX_8821C) & BIT_MASK_HI2Q_HW_IDX_8821C)
+#define BIT_SET_HI2Q_HW_IDX_8821C(x, v)                                        \
+	(BIT_CLEAR_HI2Q_HW_IDX_8821C(x) | BIT_HI2Q_HW_IDX_8821C(v))
+
+#define BIT_SHIFT_HI2Q_HOST_IDX_8821C 0
+#define BIT_MASK_HI2Q_HOST_IDX_8821C 0xfff
+#define BIT_HI2Q_HOST_IDX_8821C(x)                                             \
+	(((x) & BIT_MASK_HI2Q_HOST_IDX_8821C) << BIT_SHIFT_HI2Q_HOST_IDX_8821C)
+#define BITS_HI2Q_HOST_IDX_8821C                                               \
+	(BIT_MASK_HI2Q_HOST_IDX_8821C << BIT_SHIFT_HI2Q_HOST_IDX_8821C)
+#define BIT_CLEAR_HI2Q_HOST_IDX_8821C(x) ((x) & (~BITS_HI2Q_HOST_IDX_8821C))
+#define BIT_GET_HI2Q_HOST_IDX_8821C(x)                                         \
+	(((x) >> BIT_SHIFT_HI2Q_HOST_IDX_8821C) & BIT_MASK_HI2Q_HOST_IDX_8821C)
+#define BIT_SET_HI2Q_HOST_IDX_8821C(x, v)                                      \
+	(BIT_CLEAR_HI2Q_HOST_IDX_8821C(x) | BIT_HI2Q_HOST_IDX_8821C(v))
+
+/* 2 REG_HI3Q_TXBD_IDX_8821C */
+
+#define BIT_SHIFT_HI3Q_HW_IDX_8821C 16
+#define BIT_MASK_HI3Q_HW_IDX_8821C 0xfff
+#define BIT_HI3Q_HW_IDX_8821C(x)                                               \
+	(((x) & BIT_MASK_HI3Q_HW_IDX_8821C) << BIT_SHIFT_HI3Q_HW_IDX_8821C)
+#define BITS_HI3Q_HW_IDX_8821C                                                 \
+	(BIT_MASK_HI3Q_HW_IDX_8821C << BIT_SHIFT_HI3Q_HW_IDX_8821C)
+#define BIT_CLEAR_HI3Q_HW_IDX_8821C(x) ((x) & (~BITS_HI3Q_HW_IDX_8821C))
+#define BIT_GET_HI3Q_HW_IDX_8821C(x)                                           \
+	(((x) >> BIT_SHIFT_HI3Q_HW_IDX_8821C) & BIT_MASK_HI3Q_HW_IDX_8821C)
+#define BIT_SET_HI3Q_HW_IDX_8821C(x, v)                                        \
+	(BIT_CLEAR_HI3Q_HW_IDX_8821C(x) | BIT_HI3Q_HW_IDX_8821C(v))
+
+#define BIT_SHIFT_HI3Q_HOST_IDX_8821C 0
+#define BIT_MASK_HI3Q_HOST_IDX_8821C 0xfff
+#define BIT_HI3Q_HOST_IDX_8821C(x)                                             \
+	(((x) & BIT_MASK_HI3Q_HOST_IDX_8821C) << BIT_SHIFT_HI3Q_HOST_IDX_8821C)
+#define BITS_HI3Q_HOST_IDX_8821C                                               \
+	(BIT_MASK_HI3Q_HOST_IDX_8821C << BIT_SHIFT_HI3Q_HOST_IDX_8821C)
+#define BIT_CLEAR_HI3Q_HOST_IDX_8821C(x) ((x) & (~BITS_HI3Q_HOST_IDX_8821C))
+#define BIT_GET_HI3Q_HOST_IDX_8821C(x)                                         \
+	(((x) >> BIT_SHIFT_HI3Q_HOST_IDX_8821C) & BIT_MASK_HI3Q_HOST_IDX_8821C)
+#define BIT_SET_HI3Q_HOST_IDX_8821C(x, v)                                      \
+	(BIT_CLEAR_HI3Q_HOST_IDX_8821C(x) | BIT_HI3Q_HOST_IDX_8821C(v))
+
+/* 2 REG_HI4Q_TXBD_IDX_8821C */
+
+#define BIT_SHIFT_HI4Q_HW_IDX_8821C 16
+#define BIT_MASK_HI4Q_HW_IDX_8821C 0xfff
+#define BIT_HI4Q_HW_IDX_8821C(x)                                               \
+	(((x) & BIT_MASK_HI4Q_HW_IDX_8821C) << BIT_SHIFT_HI4Q_HW_IDX_8821C)
+#define BITS_HI4Q_HW_IDX_8821C                                                 \
+	(BIT_MASK_HI4Q_HW_IDX_8821C << BIT_SHIFT_HI4Q_HW_IDX_8821C)
+#define BIT_CLEAR_HI4Q_HW_IDX_8821C(x) ((x) & (~BITS_HI4Q_HW_IDX_8821C))
+#define BIT_GET_HI4Q_HW_IDX_8821C(x)                                           \
+	(((x) >> BIT_SHIFT_HI4Q_HW_IDX_8821C) & BIT_MASK_HI4Q_HW_IDX_8821C)
+#define BIT_SET_HI4Q_HW_IDX_8821C(x, v)                                        \
+	(BIT_CLEAR_HI4Q_HW_IDX_8821C(x) | BIT_HI4Q_HW_IDX_8821C(v))
+
+#define BIT_SHIFT_HI4Q_HOST_IDX_8821C 0
+#define BIT_MASK_HI4Q_HOST_IDX_8821C 0xfff
+#define BIT_HI4Q_HOST_IDX_8821C(x)                                             \
+	(((x) & BIT_MASK_HI4Q_HOST_IDX_8821C) << BIT_SHIFT_HI4Q_HOST_IDX_8821C)
+#define BITS_HI4Q_HOST_IDX_8821C                                               \
+	(BIT_MASK_HI4Q_HOST_IDX_8821C << BIT_SHIFT_HI4Q_HOST_IDX_8821C)
+#define BIT_CLEAR_HI4Q_HOST_IDX_8821C(x) ((x) & (~BITS_HI4Q_HOST_IDX_8821C))
+#define BIT_GET_HI4Q_HOST_IDX_8821C(x)                                         \
+	(((x) >> BIT_SHIFT_HI4Q_HOST_IDX_8821C) & BIT_MASK_HI4Q_HOST_IDX_8821C)
+#define BIT_SET_HI4Q_HOST_IDX_8821C(x, v)                                      \
+	(BIT_CLEAR_HI4Q_HOST_IDX_8821C(x) | BIT_HI4Q_HOST_IDX_8821C(v))
+
+/* 2 REG_HI5Q_TXBD_IDX_8821C */
+
+#define BIT_SHIFT_HI5Q_HW_IDX_8821C 16
+#define BIT_MASK_HI5Q_HW_IDX_8821C 0xfff
+#define BIT_HI5Q_HW_IDX_8821C(x)                                               \
+	(((x) & BIT_MASK_HI5Q_HW_IDX_8821C) << BIT_SHIFT_HI5Q_HW_IDX_8821C)
+#define BITS_HI5Q_HW_IDX_8821C                                                 \
+	(BIT_MASK_HI5Q_HW_IDX_8821C << BIT_SHIFT_HI5Q_HW_IDX_8821C)
+#define BIT_CLEAR_HI5Q_HW_IDX_8821C(x) ((x) & (~BITS_HI5Q_HW_IDX_8821C))
+#define BIT_GET_HI5Q_HW_IDX_8821C(x)                                           \
+	(((x) >> BIT_SHIFT_HI5Q_HW_IDX_8821C) & BIT_MASK_HI5Q_HW_IDX_8821C)
+#define BIT_SET_HI5Q_HW_IDX_8821C(x, v)                                        \
+	(BIT_CLEAR_HI5Q_HW_IDX_8821C(x) | BIT_HI5Q_HW_IDX_8821C(v))
+
+#define BIT_SHIFT_HI5Q_HOST_IDX_8821C 0
+#define BIT_MASK_HI5Q_HOST_IDX_8821C 0xfff
+#define BIT_HI5Q_HOST_IDX_8821C(x)                                             \
+	(((x) & BIT_MASK_HI5Q_HOST_IDX_8821C) << BIT_SHIFT_HI5Q_HOST_IDX_8821C)
+#define BITS_HI5Q_HOST_IDX_8821C                                               \
+	(BIT_MASK_HI5Q_HOST_IDX_8821C << BIT_SHIFT_HI5Q_HOST_IDX_8821C)
+#define BIT_CLEAR_HI5Q_HOST_IDX_8821C(x) ((x) & (~BITS_HI5Q_HOST_IDX_8821C))
+#define BIT_GET_HI5Q_HOST_IDX_8821C(x)                                         \
+	(((x) >> BIT_SHIFT_HI5Q_HOST_IDX_8821C) & BIT_MASK_HI5Q_HOST_IDX_8821C)
+#define BIT_SET_HI5Q_HOST_IDX_8821C(x, v)                                      \
+	(BIT_CLEAR_HI5Q_HOST_IDX_8821C(x) | BIT_HI5Q_HOST_IDX_8821C(v))
+
+/* 2 REG_HI6Q_TXBD_IDX_8821C */
+
+#define BIT_SHIFT_HI6Q_HW_IDX_8821C 16
+#define BIT_MASK_HI6Q_HW_IDX_8821C 0xfff
+#define BIT_HI6Q_HW_IDX_8821C(x)                                               \
+	(((x) & BIT_MASK_HI6Q_HW_IDX_8821C) << BIT_SHIFT_HI6Q_HW_IDX_8821C)
+#define BITS_HI6Q_HW_IDX_8821C                                                 \
+	(BIT_MASK_HI6Q_HW_IDX_8821C << BIT_SHIFT_HI6Q_HW_IDX_8821C)
+#define BIT_CLEAR_HI6Q_HW_IDX_8821C(x) ((x) & (~BITS_HI6Q_HW_IDX_8821C))
+#define BIT_GET_HI6Q_HW_IDX_8821C(x)                                           \
+	(((x) >> BIT_SHIFT_HI6Q_HW_IDX_8821C) & BIT_MASK_HI6Q_HW_IDX_8821C)
+#define BIT_SET_HI6Q_HW_IDX_8821C(x, v)                                        \
+	(BIT_CLEAR_HI6Q_HW_IDX_8821C(x) | BIT_HI6Q_HW_IDX_8821C(v))
+
+#define BIT_SHIFT_HI6Q_HOST_IDX_8821C 0
+#define BIT_MASK_HI6Q_HOST_IDX_8821C 0xfff
+#define BIT_HI6Q_HOST_IDX_8821C(x)                                             \
+	(((x) & BIT_MASK_HI6Q_HOST_IDX_8821C) << BIT_SHIFT_HI6Q_HOST_IDX_8821C)
+#define BITS_HI6Q_HOST_IDX_8821C                                               \
+	(BIT_MASK_HI6Q_HOST_IDX_8821C << BIT_SHIFT_HI6Q_HOST_IDX_8821C)
+#define BIT_CLEAR_HI6Q_HOST_IDX_8821C(x) ((x) & (~BITS_HI6Q_HOST_IDX_8821C))
+#define BIT_GET_HI6Q_HOST_IDX_8821C(x)                                         \
+	(((x) >> BIT_SHIFT_HI6Q_HOST_IDX_8821C) & BIT_MASK_HI6Q_HOST_IDX_8821C)
+#define BIT_SET_HI6Q_HOST_IDX_8821C(x, v)                                      \
+	(BIT_CLEAR_HI6Q_HOST_IDX_8821C(x) | BIT_HI6Q_HOST_IDX_8821C(v))
+
+/* 2 REG_HI7Q_TXBD_IDX_8821C */
+
+#define BIT_SHIFT_HI7Q_HW_IDX_8821C 16
+#define BIT_MASK_HI7Q_HW_IDX_8821C 0xfff
+#define BIT_HI7Q_HW_IDX_8821C(x)                                               \
+	(((x) & BIT_MASK_HI7Q_HW_IDX_8821C) << BIT_SHIFT_HI7Q_HW_IDX_8821C)
+#define BITS_HI7Q_HW_IDX_8821C                                                 \
+	(BIT_MASK_HI7Q_HW_IDX_8821C << BIT_SHIFT_HI7Q_HW_IDX_8821C)
+#define BIT_CLEAR_HI7Q_HW_IDX_8821C(x) ((x) & (~BITS_HI7Q_HW_IDX_8821C))
+#define BIT_GET_HI7Q_HW_IDX_8821C(x)                                           \
+	(((x) >> BIT_SHIFT_HI7Q_HW_IDX_8821C) & BIT_MASK_HI7Q_HW_IDX_8821C)
+#define BIT_SET_HI7Q_HW_IDX_8821C(x, v)                                        \
+	(BIT_CLEAR_HI7Q_HW_IDX_8821C(x) | BIT_HI7Q_HW_IDX_8821C(v))
+
+#define BIT_SHIFT_HI7Q_HOST_IDX_8821C 0
+#define BIT_MASK_HI7Q_HOST_IDX_8821C 0xfff
+#define BIT_HI7Q_HOST_IDX_8821C(x)                                             \
+	(((x) & BIT_MASK_HI7Q_HOST_IDX_8821C) << BIT_SHIFT_HI7Q_HOST_IDX_8821C)
+#define BITS_HI7Q_HOST_IDX_8821C                                               \
+	(BIT_MASK_HI7Q_HOST_IDX_8821C << BIT_SHIFT_HI7Q_HOST_IDX_8821C)
+#define BIT_CLEAR_HI7Q_HOST_IDX_8821C(x) ((x) & (~BITS_HI7Q_HOST_IDX_8821C))
+#define BIT_GET_HI7Q_HOST_IDX_8821C(x)                                         \
+	(((x) >> BIT_SHIFT_HI7Q_HOST_IDX_8821C) & BIT_MASK_HI7Q_HOST_IDX_8821C)
+#define BIT_SET_HI7Q_HOST_IDX_8821C(x, v)                                      \
+	(BIT_CLEAR_HI7Q_HOST_IDX_8821C(x) | BIT_HI7Q_HOST_IDX_8821C(v))
+
+/* 2 REG_DBG_SEL_V1_8821C */
+
+#define BIT_SHIFT_DBG_SEL_8821C 0
+#define BIT_MASK_DBG_SEL_8821C 0xff
+#define BIT_DBG_SEL_8821C(x)                                                   \
+	(((x) & BIT_MASK_DBG_SEL_8821C) << BIT_SHIFT_DBG_SEL_8821C)
+#define BITS_DBG_SEL_8821C (BIT_MASK_DBG_SEL_8821C << BIT_SHIFT_DBG_SEL_8821C)
+#define BIT_CLEAR_DBG_SEL_8821C(x) ((x) & (~BITS_DBG_SEL_8821C))
+#define BIT_GET_DBG_SEL_8821C(x)                                               \
+	(((x) >> BIT_SHIFT_DBG_SEL_8821C) & BIT_MASK_DBG_SEL_8821C)
+#define BIT_SET_DBG_SEL_8821C(x, v)                                            \
+	(BIT_CLEAR_DBG_SEL_8821C(x) | BIT_DBG_SEL_8821C(v))
+
+/* 2 REG_PCIE_HRPWM1_V1_8821C */
+
+#define BIT_SHIFT_PCIE_HRPWM_8821C 0
+#define BIT_MASK_PCIE_HRPWM_8821C 0xff
+#define BIT_PCIE_HRPWM_8821C(x)                                                \
+	(((x) & BIT_MASK_PCIE_HRPWM_8821C) << BIT_SHIFT_PCIE_HRPWM_8821C)
+#define BITS_PCIE_HRPWM_8821C                                                  \
+	(BIT_MASK_PCIE_HRPWM_8821C << BIT_SHIFT_PCIE_HRPWM_8821C)
+#define BIT_CLEAR_PCIE_HRPWM_8821C(x) ((x) & (~BITS_PCIE_HRPWM_8821C))
+#define BIT_GET_PCIE_HRPWM_8821C(x)                                            \
+	(((x) >> BIT_SHIFT_PCIE_HRPWM_8821C) & BIT_MASK_PCIE_HRPWM_8821C)
+#define BIT_SET_PCIE_HRPWM_8821C(x, v)                                         \
+	(BIT_CLEAR_PCIE_HRPWM_8821C(x) | BIT_PCIE_HRPWM_8821C(v))
+
+/* 2 REG_PCIE_HCPWM1_V1_8821C */
+
+#define BIT_SHIFT_PCIE_HCPWM_8821C 0
+#define BIT_MASK_PCIE_HCPWM_8821C 0xff
+#define BIT_PCIE_HCPWM_8821C(x)                                                \
+	(((x) & BIT_MASK_PCIE_HCPWM_8821C) << BIT_SHIFT_PCIE_HCPWM_8821C)
+#define BITS_PCIE_HCPWM_8821C                                                  \
+	(BIT_MASK_PCIE_HCPWM_8821C << BIT_SHIFT_PCIE_HCPWM_8821C)
+#define BIT_CLEAR_PCIE_HCPWM_8821C(x) ((x) & (~BITS_PCIE_HCPWM_8821C))
+#define BIT_GET_PCIE_HCPWM_8821C(x)                                            \
+	(((x) >> BIT_SHIFT_PCIE_HCPWM_8821C) & BIT_MASK_PCIE_HCPWM_8821C)
+#define BIT_SET_PCIE_HCPWM_8821C(x, v)                                         \
+	(BIT_CLEAR_PCIE_HCPWM_8821C(x) | BIT_PCIE_HCPWM_8821C(v))
+
+/* 2 REG_PCIE_CTRL2_8821C */
+#define BIT_DIS_TXDMA_PRE_8821C BIT(7)
+#define BIT_DIS_RXDMA_PRE_8821C BIT(6)
+
+#define BIT_SHIFT_HPS_CLKR_PCIE_8821C 4
+#define BIT_MASK_HPS_CLKR_PCIE_8821C 0x3
+#define BIT_HPS_CLKR_PCIE_8821C(x)                                             \
+	(((x) & BIT_MASK_HPS_CLKR_PCIE_8821C) << BIT_SHIFT_HPS_CLKR_PCIE_8821C)
+#define BITS_HPS_CLKR_PCIE_8821C                                               \
+	(BIT_MASK_HPS_CLKR_PCIE_8821C << BIT_SHIFT_HPS_CLKR_PCIE_8821C)
+#define BIT_CLEAR_HPS_CLKR_PCIE_8821C(x) ((x) & (~BITS_HPS_CLKR_PCIE_8821C))
+#define BIT_GET_HPS_CLKR_PCIE_8821C(x)                                         \
+	(((x) >> BIT_SHIFT_HPS_CLKR_PCIE_8821C) & BIT_MASK_HPS_CLKR_PCIE_8821C)
+#define BIT_SET_HPS_CLKR_PCIE_8821C(x, v)                                      \
+	(BIT_CLEAR_HPS_CLKR_PCIE_8821C(x) | BIT_HPS_CLKR_PCIE_8821C(v))
+
+#define BIT_PCIE_INT_8821C BIT(3)
+#define BIT_TXFLAG_EXIT_L1_EN_8821C BIT(2)
+#define BIT_EN_RXDMA_ALIGN_8821C BIT(1)
+#define BIT_EN_TXDMA_ALIGN_8821C BIT(0)
+
+/* 2 REG_PCIE_HRPWM2_V1_8821C */
+
+#define BIT_SHIFT_PCIE_HRPWM2_8821C 0
+#define BIT_MASK_PCIE_HRPWM2_8821C 0xffff
+#define BIT_PCIE_HRPWM2_8821C(x)                                               \
+	(((x) & BIT_MASK_PCIE_HRPWM2_8821C) << BIT_SHIFT_PCIE_HRPWM2_8821C)
+#define BITS_PCIE_HRPWM2_8821C                                                 \
+	(BIT_MASK_PCIE_HRPWM2_8821C << BIT_SHIFT_PCIE_HRPWM2_8821C)
+#define BIT_CLEAR_PCIE_HRPWM2_8821C(x) ((x) & (~BITS_PCIE_HRPWM2_8821C))
+#define BIT_GET_PCIE_HRPWM2_8821C(x)                                           \
+	(((x) >> BIT_SHIFT_PCIE_HRPWM2_8821C) & BIT_MASK_PCIE_HRPWM2_8821C)
+#define BIT_SET_PCIE_HRPWM2_8821C(x, v)                                        \
+	(BIT_CLEAR_PCIE_HRPWM2_8821C(x) | BIT_PCIE_HRPWM2_8821C(v))
+
+/* 2 REG_PCIE_HCPWM2_V1_8821C */
+
+#define BIT_SHIFT_PCIE_HCPWM2_8821C 0
+#define BIT_MASK_PCIE_HCPWM2_8821C 0xffff
+#define BIT_PCIE_HCPWM2_8821C(x)                                               \
+	(((x) & BIT_MASK_PCIE_HCPWM2_8821C) << BIT_SHIFT_PCIE_HCPWM2_8821C)
+#define BITS_PCIE_HCPWM2_8821C                                                 \
+	(BIT_MASK_PCIE_HCPWM2_8821C << BIT_SHIFT_PCIE_HCPWM2_8821C)
+#define BIT_CLEAR_PCIE_HCPWM2_8821C(x) ((x) & (~BITS_PCIE_HCPWM2_8821C))
+#define BIT_GET_PCIE_HCPWM2_8821C(x)                                           \
+	(((x) >> BIT_SHIFT_PCIE_HCPWM2_8821C) & BIT_MASK_PCIE_HCPWM2_8821C)
+#define BIT_SET_PCIE_HCPWM2_8821C(x, v)                                        \
+	(BIT_CLEAR_PCIE_HCPWM2_8821C(x) | BIT_PCIE_HCPWM2_8821C(v))
+
+/* 2 REG_PCIE_H2C_MSG_V1_8821C */
+
+#define BIT_SHIFT_DRV2FW_INFO_8821C 0
+#define BIT_MASK_DRV2FW_INFO_8821C 0xffffffffL
+#define BIT_DRV2FW_INFO_8821C(x)                                               \
+	(((x) & BIT_MASK_DRV2FW_INFO_8821C) << BIT_SHIFT_DRV2FW_INFO_8821C)
+#define BITS_DRV2FW_INFO_8821C                                                 \
+	(BIT_MASK_DRV2FW_INFO_8821C << BIT_SHIFT_DRV2FW_INFO_8821C)
+#define BIT_CLEAR_DRV2FW_INFO_8821C(x) ((x) & (~BITS_DRV2FW_INFO_8821C))
+#define BIT_GET_DRV2FW_INFO_8821C(x)                                           \
+	(((x) >> BIT_SHIFT_DRV2FW_INFO_8821C) & BIT_MASK_DRV2FW_INFO_8821C)
+#define BIT_SET_DRV2FW_INFO_8821C(x, v)                                        \
+	(BIT_CLEAR_DRV2FW_INFO_8821C(x) | BIT_DRV2FW_INFO_8821C(v))
+
+/* 2 REG_PCIE_C2H_MSG_V1_8821C */
+
+#define BIT_SHIFT_HCI_PCIE_C2H_MSG_8821C 0
+#define BIT_MASK_HCI_PCIE_C2H_MSG_8821C 0xffffffffL
+#define BIT_HCI_PCIE_C2H_MSG_8821C(x)                                          \
+	(((x) & BIT_MASK_HCI_PCIE_C2H_MSG_8821C)                               \
+	 << BIT_SHIFT_HCI_PCIE_C2H_MSG_8821C)
+#define BITS_HCI_PCIE_C2H_MSG_8821C                                            \
+	(BIT_MASK_HCI_PCIE_C2H_MSG_8821C << BIT_SHIFT_HCI_PCIE_C2H_MSG_8821C)
+#define BIT_CLEAR_HCI_PCIE_C2H_MSG_8821C(x)                                    \
+	((x) & (~BITS_HCI_PCIE_C2H_MSG_8821C))
+#define BIT_GET_HCI_PCIE_C2H_MSG_8821C(x)                                      \
+	(((x) >> BIT_SHIFT_HCI_PCIE_C2H_MSG_8821C) &                           \
+	 BIT_MASK_HCI_PCIE_C2H_MSG_8821C)
+#define BIT_SET_HCI_PCIE_C2H_MSG_8821C(x, v)                                   \
+	(BIT_CLEAR_HCI_PCIE_C2H_MSG_8821C(x) | BIT_HCI_PCIE_C2H_MSG_8821C(v))
+
+/* 2 REG_DBI_WDATA_V1_8821C */
+
+#define BIT_SHIFT_DBI_WDATA_8821C 0
+#define BIT_MASK_DBI_WDATA_8821C 0xffffffffL
+#define BIT_DBI_WDATA_8821C(x)                                                 \
+	(((x) & BIT_MASK_DBI_WDATA_8821C) << BIT_SHIFT_DBI_WDATA_8821C)
+#define BITS_DBI_WDATA_8821C                                                   \
+	(BIT_MASK_DBI_WDATA_8821C << BIT_SHIFT_DBI_WDATA_8821C)
+#define BIT_CLEAR_DBI_WDATA_8821C(x) ((x) & (~BITS_DBI_WDATA_8821C))
+#define BIT_GET_DBI_WDATA_8821C(x)                                             \
+	(((x) >> BIT_SHIFT_DBI_WDATA_8821C) & BIT_MASK_DBI_WDATA_8821C)
+#define BIT_SET_DBI_WDATA_8821C(x, v)                                          \
+	(BIT_CLEAR_DBI_WDATA_8821C(x) | BIT_DBI_WDATA_8821C(v))
+
+/* 2 REG_DBI_RDATA_V1_8821C */
+
+#define BIT_SHIFT_DBI_RDATA_8821C 0
+#define BIT_MASK_DBI_RDATA_8821C 0xffffffffL
+#define BIT_DBI_RDATA_8821C(x)                                                 \
+	(((x) & BIT_MASK_DBI_RDATA_8821C) << BIT_SHIFT_DBI_RDATA_8821C)
+#define BITS_DBI_RDATA_8821C                                                   \
+	(BIT_MASK_DBI_RDATA_8821C << BIT_SHIFT_DBI_RDATA_8821C)
+#define BIT_CLEAR_DBI_RDATA_8821C(x) ((x) & (~BITS_DBI_RDATA_8821C))
+#define BIT_GET_DBI_RDATA_8821C(x)                                             \
+	(((x) >> BIT_SHIFT_DBI_RDATA_8821C) & BIT_MASK_DBI_RDATA_8821C)
+#define BIT_SET_DBI_RDATA_8821C(x, v)                                          \
+	(BIT_CLEAR_DBI_RDATA_8821C(x) | BIT_DBI_RDATA_8821C(v))
+
+/* 2 REG_DBI_FLAG_V1_8821C */
+#define BIT_EN_STUCK_DBG_8821C BIT(26)
+#define BIT_RX_STUCK_8821C BIT(25)
+#define BIT_TX_STUCK_8821C BIT(24)
+#define BIT_DBI_RFLAG_8821C BIT(17)
+#define BIT_DBI_WFLAG_8821C BIT(16)
+
+#define BIT_SHIFT_DBI_WREN_8821C 12
+#define BIT_MASK_DBI_WREN_8821C 0xf
+#define BIT_DBI_WREN_8821C(x)                                                  \
+	(((x) & BIT_MASK_DBI_WREN_8821C) << BIT_SHIFT_DBI_WREN_8821C)
+#define BITS_DBI_WREN_8821C                                                    \
+	(BIT_MASK_DBI_WREN_8821C << BIT_SHIFT_DBI_WREN_8821C)
+#define BIT_CLEAR_DBI_WREN_8821C(x) ((x) & (~BITS_DBI_WREN_8821C))
+#define BIT_GET_DBI_WREN_8821C(x)                                              \
+	(((x) >> BIT_SHIFT_DBI_WREN_8821C) & BIT_MASK_DBI_WREN_8821C)
+#define BIT_SET_DBI_WREN_8821C(x, v)                                           \
+	(BIT_CLEAR_DBI_WREN_8821C(x) | BIT_DBI_WREN_8821C(v))
+
+#define BIT_SHIFT_DBI_ADDR_8821C 0
+#define BIT_MASK_DBI_ADDR_8821C 0xfff
+#define BIT_DBI_ADDR_8821C(x)                                                  \
+	(((x) & BIT_MASK_DBI_ADDR_8821C) << BIT_SHIFT_DBI_ADDR_8821C)
+#define BITS_DBI_ADDR_8821C                                                    \
+	(BIT_MASK_DBI_ADDR_8821C << BIT_SHIFT_DBI_ADDR_8821C)
+#define BIT_CLEAR_DBI_ADDR_8821C(x) ((x) & (~BITS_DBI_ADDR_8821C))
+#define BIT_GET_DBI_ADDR_8821C(x)                                              \
+	(((x) >> BIT_SHIFT_DBI_ADDR_8821C) & BIT_MASK_DBI_ADDR_8821C)
+#define BIT_SET_DBI_ADDR_8821C(x, v)                                           \
+	(BIT_CLEAR_DBI_ADDR_8821C(x) | BIT_DBI_ADDR_8821C(v))
+
+/* 2 REG_MDIO_V1_8821C */
+
+#define BIT_SHIFT_MDIO_RDATA_8821C 16
+#define BIT_MASK_MDIO_RDATA_8821C 0xffff
+#define BIT_MDIO_RDATA_8821C(x)                                                \
+	(((x) & BIT_MASK_MDIO_RDATA_8821C) << BIT_SHIFT_MDIO_RDATA_8821C)
+#define BITS_MDIO_RDATA_8821C                                                  \
+	(BIT_MASK_MDIO_RDATA_8821C << BIT_SHIFT_MDIO_RDATA_8821C)
+#define BIT_CLEAR_MDIO_RDATA_8821C(x) ((x) & (~BITS_MDIO_RDATA_8821C))
+#define BIT_GET_MDIO_RDATA_8821C(x)                                            \
+	(((x) >> BIT_SHIFT_MDIO_RDATA_8821C) & BIT_MASK_MDIO_RDATA_8821C)
+#define BIT_SET_MDIO_RDATA_8821C(x, v)                                         \
+	(BIT_CLEAR_MDIO_RDATA_8821C(x) | BIT_MDIO_RDATA_8821C(v))
+
+#define BIT_SHIFT_MDIO_WDATA_8821C 0
+#define BIT_MASK_MDIO_WDATA_8821C 0xffff
+#define BIT_MDIO_WDATA_8821C(x)                                                \
+	(((x) & BIT_MASK_MDIO_WDATA_8821C) << BIT_SHIFT_MDIO_WDATA_8821C)
+#define BITS_MDIO_WDATA_8821C                                                  \
+	(BIT_MASK_MDIO_WDATA_8821C << BIT_SHIFT_MDIO_WDATA_8821C)
+#define BIT_CLEAR_MDIO_WDATA_8821C(x) ((x) & (~BITS_MDIO_WDATA_8821C))
+#define BIT_GET_MDIO_WDATA_8821C(x)                                            \
+	(((x) >> BIT_SHIFT_MDIO_WDATA_8821C) & BIT_MASK_MDIO_WDATA_8821C)
+#define BIT_SET_MDIO_WDATA_8821C(x, v)                                         \
+	(BIT_CLEAR_MDIO_WDATA_8821C(x) | BIT_MDIO_WDATA_8821C(v))
+
+/* 2 REG_PCIE_MIX_CFG_8821C */
+
+#define BIT_SHIFT_MDIO_PHY_ADDR_8821C 24
+#define BIT_MASK_MDIO_PHY_ADDR_8821C 0x1f
+#define BIT_MDIO_PHY_ADDR_8821C(x)                                             \
+	(((x) & BIT_MASK_MDIO_PHY_ADDR_8821C) << BIT_SHIFT_MDIO_PHY_ADDR_8821C)
+#define BITS_MDIO_PHY_ADDR_8821C                                               \
+	(BIT_MASK_MDIO_PHY_ADDR_8821C << BIT_SHIFT_MDIO_PHY_ADDR_8821C)
+#define BIT_CLEAR_MDIO_PHY_ADDR_8821C(x) ((x) & (~BITS_MDIO_PHY_ADDR_8821C))
+#define BIT_GET_MDIO_PHY_ADDR_8821C(x)                                         \
+	(((x) >> BIT_SHIFT_MDIO_PHY_ADDR_8821C) & BIT_MASK_MDIO_PHY_ADDR_8821C)
+#define BIT_SET_MDIO_PHY_ADDR_8821C(x, v)                                      \
+	(BIT_CLEAR_MDIO_PHY_ADDR_8821C(x) | BIT_MDIO_PHY_ADDR_8821C(v))
+
+#define BIT_SHIFT_WATCH_DOG_RECORD_V1_8821C 10
+#define BIT_MASK_WATCH_DOG_RECORD_V1_8821C 0x3fff
+#define BIT_WATCH_DOG_RECORD_V1_8821C(x)                                       \
+	(((x) & BIT_MASK_WATCH_DOG_RECORD_V1_8821C)                            \
+	 << BIT_SHIFT_WATCH_DOG_RECORD_V1_8821C)
+#define BITS_WATCH_DOG_RECORD_V1_8821C                                         \
+	(BIT_MASK_WATCH_DOG_RECORD_V1_8821C                                    \
+	 << BIT_SHIFT_WATCH_DOG_RECORD_V1_8821C)
+#define BIT_CLEAR_WATCH_DOG_RECORD_V1_8821C(x)                                 \
+	((x) & (~BITS_WATCH_DOG_RECORD_V1_8821C))
+#define BIT_GET_WATCH_DOG_RECORD_V1_8821C(x)                                   \
+	(((x) >> BIT_SHIFT_WATCH_DOG_RECORD_V1_8821C) &                        \
+	 BIT_MASK_WATCH_DOG_RECORD_V1_8821C)
+#define BIT_SET_WATCH_DOG_RECORD_V1_8821C(x, v)                                \
+	(BIT_CLEAR_WATCH_DOG_RECORD_V1_8821C(x) |                              \
+	 BIT_WATCH_DOG_RECORD_V1_8821C(v))
+
+#define BIT_R_IO_TIMEOUT_FLAG_V1_8821C BIT(9)
+#define BIT_EN_WATCH_DOG_8821C BIT(8)
+#define BIT_ECRC_EN_V1_8821C BIT(7)
+#define BIT_MDIO_RFLAG_V1_8821C BIT(6)
+#define BIT_MDIO_WFLAG_V1_8821C BIT(5)
+
+#define BIT_SHIFT_MDIO_REG_ADDR_V1_8821C 0
+#define BIT_MASK_MDIO_REG_ADDR_V1_8821C 0x1f
+#define BIT_MDIO_REG_ADDR_V1_8821C(x)                                          \
+	(((x) & BIT_MASK_MDIO_REG_ADDR_V1_8821C)                               \
+	 << BIT_SHIFT_MDIO_REG_ADDR_V1_8821C)
+#define BITS_MDIO_REG_ADDR_V1_8821C                                            \
+	(BIT_MASK_MDIO_REG_ADDR_V1_8821C << BIT_SHIFT_MDIO_REG_ADDR_V1_8821C)
+#define BIT_CLEAR_MDIO_REG_ADDR_V1_8821C(x)                                    \
+	((x) & (~BITS_MDIO_REG_ADDR_V1_8821C))
+#define BIT_GET_MDIO_REG_ADDR_V1_8821C(x)                                      \
+	(((x) >> BIT_SHIFT_MDIO_REG_ADDR_V1_8821C) &                           \
+	 BIT_MASK_MDIO_REG_ADDR_V1_8821C)
+#define BIT_SET_MDIO_REG_ADDR_V1_8821C(x, v)                                   \
+	(BIT_CLEAR_MDIO_REG_ADDR_V1_8821C(x) | BIT_MDIO_REG_ADDR_V1_8821C(v))
+
+/* 2 REG_HCI_MIX_CFG_8821C */
+#define BIT_HOST_GEN2_SUPPORT_8821C BIT(20)
+
+#define BIT_SHIFT_TXDMA_ERR_FLAG_8821C 16
+#define BIT_MASK_TXDMA_ERR_FLAG_8821C 0xf
+#define BIT_TXDMA_ERR_FLAG_8821C(x)                                            \
+	(((x) & BIT_MASK_TXDMA_ERR_FLAG_8821C)                                 \
+	 << BIT_SHIFT_TXDMA_ERR_FLAG_8821C)
+#define BITS_TXDMA_ERR_FLAG_8821C                                              \
+	(BIT_MASK_TXDMA_ERR_FLAG_8821C << BIT_SHIFT_TXDMA_ERR_FLAG_8821C)
+#define BIT_CLEAR_TXDMA_ERR_FLAG_8821C(x) ((x) & (~BITS_TXDMA_ERR_FLAG_8821C))
+#define BIT_GET_TXDMA_ERR_FLAG_8821C(x)                                        \
+	(((x) >> BIT_SHIFT_TXDMA_ERR_FLAG_8821C) &                             \
+	 BIT_MASK_TXDMA_ERR_FLAG_8821C)
+#define BIT_SET_TXDMA_ERR_FLAG_8821C(x, v)                                     \
+	(BIT_CLEAR_TXDMA_ERR_FLAG_8821C(x) | BIT_TXDMA_ERR_FLAG_8821C(v))
+
+#define BIT_SHIFT_EARLY_MODE_SEL_8821C 12
+#define BIT_MASK_EARLY_MODE_SEL_8821C 0xf
+#define BIT_EARLY_MODE_SEL_8821C(x)                                            \
+	(((x) & BIT_MASK_EARLY_MODE_SEL_8821C)                                 \
+	 << BIT_SHIFT_EARLY_MODE_SEL_8821C)
+#define BITS_EARLY_MODE_SEL_8821C                                              \
+	(BIT_MASK_EARLY_MODE_SEL_8821C << BIT_SHIFT_EARLY_MODE_SEL_8821C)
+#define BIT_CLEAR_EARLY_MODE_SEL_8821C(x) ((x) & (~BITS_EARLY_MODE_SEL_8821C))
+#define BIT_GET_EARLY_MODE_SEL_8821C(x)                                        \
+	(((x) >> BIT_SHIFT_EARLY_MODE_SEL_8821C) &                             \
+	 BIT_MASK_EARLY_MODE_SEL_8821C)
+#define BIT_SET_EARLY_MODE_SEL_8821C(x, v)                                     \
+	(BIT_CLEAR_EARLY_MODE_SEL_8821C(x) | BIT_EARLY_MODE_SEL_8821C(v))
+
+#define BIT_EPHY_RX50_EN_8821C BIT(11)
+
+#define BIT_SHIFT_MSI_TIMEOUT_ID_V1_8821C 8
+#define BIT_MASK_MSI_TIMEOUT_ID_V1_8821C 0x7
+#define BIT_MSI_TIMEOUT_ID_V1_8821C(x)                                         \
+	(((x) & BIT_MASK_MSI_TIMEOUT_ID_V1_8821C)                              \
+	 << BIT_SHIFT_MSI_TIMEOUT_ID_V1_8821C)
+#define BITS_MSI_TIMEOUT_ID_V1_8821C                                           \
+	(BIT_MASK_MSI_TIMEOUT_ID_V1_8821C << BIT_SHIFT_MSI_TIMEOUT_ID_V1_8821C)
+#define BIT_CLEAR_MSI_TIMEOUT_ID_V1_8821C(x)                                   \
+	((x) & (~BITS_MSI_TIMEOUT_ID_V1_8821C))
+#define BIT_GET_MSI_TIMEOUT_ID_V1_8821C(x)                                     \
+	(((x) >> BIT_SHIFT_MSI_TIMEOUT_ID_V1_8821C) &                          \
+	 BIT_MASK_MSI_TIMEOUT_ID_V1_8821C)
+#define BIT_SET_MSI_TIMEOUT_ID_V1_8821C(x, v)                                  \
+	(BIT_CLEAR_MSI_TIMEOUT_ID_V1_8821C(x) | BIT_MSI_TIMEOUT_ID_V1_8821C(v))
+
+#define BIT_RADDR_RD_8821C BIT(7)
+#define BIT_EN_MUL_TAG_8821C BIT(6)
+#define BIT_EN_EARLY_MODE_8821C BIT(5)
+#define BIT_L0S_LINK_OFF_8821C BIT(4)
+#define BIT_ACT_LINK_OFF_8821C BIT(3)
+#define BIT_EN_SLOW_MAC_TX_8821C BIT(2)
+#define BIT_EN_SLOW_MAC_RX_8821C BIT(1)
+
+/* 2 REG_STC_INT_CS_8821C(PCIE STATE CHANGE INTERRUPT CONTROL AND STATUS) */
+#define BIT_STC_INT_EN_8821C BIT(31)
+
+#define BIT_SHIFT_STC_INT_FLAG_8821C 16
+#define BIT_MASK_STC_INT_FLAG_8821C 0xff
+#define BIT_STC_INT_FLAG_8821C(x)                                              \
+	(((x) & BIT_MASK_STC_INT_FLAG_8821C) << BIT_SHIFT_STC_INT_FLAG_8821C)
+#define BITS_STC_INT_FLAG_8821C                                                \
+	(BIT_MASK_STC_INT_FLAG_8821C << BIT_SHIFT_STC_INT_FLAG_8821C)
+#define BIT_CLEAR_STC_INT_FLAG_8821C(x) ((x) & (~BITS_STC_INT_FLAG_8821C))
+#define BIT_GET_STC_INT_FLAG_8821C(x)                                          \
+	(((x) >> BIT_SHIFT_STC_INT_FLAG_8821C) & BIT_MASK_STC_INT_FLAG_8821C)
+#define BIT_SET_STC_INT_FLAG_8821C(x, v)                                       \
+	(BIT_CLEAR_STC_INT_FLAG_8821C(x) | BIT_STC_INT_FLAG_8821C(v))
+
+#define BIT_SHIFT_STC_INT_IDX_8821C 8
+#define BIT_MASK_STC_INT_IDX_8821C 0x7
+#define BIT_STC_INT_IDX_8821C(x)                                               \
+	(((x) & BIT_MASK_STC_INT_IDX_8821C) << BIT_SHIFT_STC_INT_IDX_8821C)
+#define BITS_STC_INT_IDX_8821C                                                 \
+	(BIT_MASK_STC_INT_IDX_8821C << BIT_SHIFT_STC_INT_IDX_8821C)
+#define BIT_CLEAR_STC_INT_IDX_8821C(x) ((x) & (~BITS_STC_INT_IDX_8821C))
+#define BIT_GET_STC_INT_IDX_8821C(x)                                           \
+	(((x) >> BIT_SHIFT_STC_INT_IDX_8821C) & BIT_MASK_STC_INT_IDX_8821C)
+#define BIT_SET_STC_INT_IDX_8821C(x, v)                                        \
+	(BIT_CLEAR_STC_INT_IDX_8821C(x) | BIT_STC_INT_IDX_8821C(v))
+
+#define BIT_SHIFT_STC_INT_REALTIME_CS_8821C 0
+#define BIT_MASK_STC_INT_REALTIME_CS_8821C 0x3f
+#define BIT_STC_INT_REALTIME_CS_8821C(x)                                       \
+	(((x) & BIT_MASK_STC_INT_REALTIME_CS_8821C)                            \
+	 << BIT_SHIFT_STC_INT_REALTIME_CS_8821C)
+#define BITS_STC_INT_REALTIME_CS_8821C                                         \
+	(BIT_MASK_STC_INT_REALTIME_CS_8821C                                    \
+	 << BIT_SHIFT_STC_INT_REALTIME_CS_8821C)
+#define BIT_CLEAR_STC_INT_REALTIME_CS_8821C(x)                                 \
+	((x) & (~BITS_STC_INT_REALTIME_CS_8821C))
+#define BIT_GET_STC_INT_REALTIME_CS_8821C(x)                                   \
+	(((x) >> BIT_SHIFT_STC_INT_REALTIME_CS_8821C) &                        \
+	 BIT_MASK_STC_INT_REALTIME_CS_8821C)
+#define BIT_SET_STC_INT_REALTIME_CS_8821C(x, v)                                \
+	(BIT_CLEAR_STC_INT_REALTIME_CS_8821C(x) |                              \
+	 BIT_STC_INT_REALTIME_CS_8821C(v))
+
+/* 2 REG_ST_INT_CFG_8821C(PCIE STATE CHANGE INTERRUPT CONFIGURATION) */
+#define BIT_STC_INT_GRP_EN_8821C BIT(31)
+
+#define BIT_SHIFT_STC_INT_EXPECT_LS_8821C 8
+#define BIT_MASK_STC_INT_EXPECT_LS_8821C 0x3f
+#define BIT_STC_INT_EXPECT_LS_8821C(x)                                         \
+	(((x) & BIT_MASK_STC_INT_EXPECT_LS_8821C)                              \
+	 << BIT_SHIFT_STC_INT_EXPECT_LS_8821C)
+#define BITS_STC_INT_EXPECT_LS_8821C                                           \
+	(BIT_MASK_STC_INT_EXPECT_LS_8821C << BIT_SHIFT_STC_INT_EXPECT_LS_8821C)
+#define BIT_CLEAR_STC_INT_EXPECT_LS_8821C(x)                                   \
+	((x) & (~BITS_STC_INT_EXPECT_LS_8821C))
+#define BIT_GET_STC_INT_EXPECT_LS_8821C(x)                                     \
+	(((x) >> BIT_SHIFT_STC_INT_EXPECT_LS_8821C) &                          \
+	 BIT_MASK_STC_INT_EXPECT_LS_8821C)
+#define BIT_SET_STC_INT_EXPECT_LS_8821C(x, v)                                  \
+	(BIT_CLEAR_STC_INT_EXPECT_LS_8821C(x) | BIT_STC_INT_EXPECT_LS_8821C(v))
+
+#define BIT_SHIFT_STC_INT_EXPECT_CS_8821C 0
+#define BIT_MASK_STC_INT_EXPECT_CS_8821C 0x3f
+#define BIT_STC_INT_EXPECT_CS_8821C(x)                                         \
+	(((x) & BIT_MASK_STC_INT_EXPECT_CS_8821C)                              \
+	 << BIT_SHIFT_STC_INT_EXPECT_CS_8821C)
+#define BITS_STC_INT_EXPECT_CS_8821C                                           \
+	(BIT_MASK_STC_INT_EXPECT_CS_8821C << BIT_SHIFT_STC_INT_EXPECT_CS_8821C)
+#define BIT_CLEAR_STC_INT_EXPECT_CS_8821C(x)                                   \
+	((x) & (~BITS_STC_INT_EXPECT_CS_8821C))
+#define BIT_GET_STC_INT_EXPECT_CS_8821C(x)                                     \
+	(((x) >> BIT_SHIFT_STC_INT_EXPECT_CS_8821C) &                          \
+	 BIT_MASK_STC_INT_EXPECT_CS_8821C)
+#define BIT_SET_STC_INT_EXPECT_CS_8821C(x, v)                                  \
+	(BIT_CLEAR_STC_INT_EXPECT_CS_8821C(x) | BIT_STC_INT_EXPECT_CS_8821C(v))
+
+/* 2 REG_CMU_DLY_CTRL_8821C(PCIE PHY CLOCK MGT UNIT DELAY CONTROL ) */
+#define BIT_CMU_DLY_EN_8821C BIT(31)
+#define BIT_CMU_DLY_MODE_8821C BIT(30)
+
+#define BIT_SHIFT_CMU_DLY_PRE_DIV_8821C 0
+#define BIT_MASK_CMU_DLY_PRE_DIV_8821C 0xff
+#define BIT_CMU_DLY_PRE_DIV_8821C(x)                                           \
+	(((x) & BIT_MASK_CMU_DLY_PRE_DIV_8821C)                                \
+	 << BIT_SHIFT_CMU_DLY_PRE_DIV_8821C)
+#define BITS_CMU_DLY_PRE_DIV_8821C                                             \
+	(BIT_MASK_CMU_DLY_PRE_DIV_8821C << BIT_SHIFT_CMU_DLY_PRE_DIV_8821C)
+#define BIT_CLEAR_CMU_DLY_PRE_DIV_8821C(x) ((x) & (~BITS_CMU_DLY_PRE_DIV_8821C))
+#define BIT_GET_CMU_DLY_PRE_DIV_8821C(x)                                       \
+	(((x) >> BIT_SHIFT_CMU_DLY_PRE_DIV_8821C) &                            \
+	 BIT_MASK_CMU_DLY_PRE_DIV_8821C)
+#define BIT_SET_CMU_DLY_PRE_DIV_8821C(x, v)                                    \
+	(BIT_CLEAR_CMU_DLY_PRE_DIV_8821C(x) | BIT_CMU_DLY_PRE_DIV_8821C(v))
+
+/* 2 REG_CMU_DLY_CFG_8821C(PCIE PHY CLOCK MGT UNIT DELAY CONFIGURATION ) */
+
+#define BIT_SHIFT_CMU_DLY_LTR_A2I_8821C 24
+#define BIT_MASK_CMU_DLY_LTR_A2I_8821C 0xff
+#define BIT_CMU_DLY_LTR_A2I_8821C(x)                                           \
+	(((x) & BIT_MASK_CMU_DLY_LTR_A2I_8821C)                                \
+	 << BIT_SHIFT_CMU_DLY_LTR_A2I_8821C)
+#define BITS_CMU_DLY_LTR_A2I_8821C                                             \
+	(BIT_MASK_CMU_DLY_LTR_A2I_8821C << BIT_SHIFT_CMU_DLY_LTR_A2I_8821C)
+#define BIT_CLEAR_CMU_DLY_LTR_A2I_8821C(x) ((x) & (~BITS_CMU_DLY_LTR_A2I_8821C))
+#define BIT_GET_CMU_DLY_LTR_A2I_8821C(x)                                       \
+	(((x) >> BIT_SHIFT_CMU_DLY_LTR_A2I_8821C) &                            \
+	 BIT_MASK_CMU_DLY_LTR_A2I_8821C)
+#define BIT_SET_CMU_DLY_LTR_A2I_8821C(x, v)                                    \
+	(BIT_CLEAR_CMU_DLY_LTR_A2I_8821C(x) | BIT_CMU_DLY_LTR_A2I_8821C(v))
+
+#define BIT_SHIFT_CMU_DLY_LTR_I2A_8821C 16
+#define BIT_MASK_CMU_DLY_LTR_I2A_8821C 0xff
+#define BIT_CMU_DLY_LTR_I2A_8821C(x)                                           \
+	(((x) & BIT_MASK_CMU_DLY_LTR_I2A_8821C)                                \
+	 << BIT_SHIFT_CMU_DLY_LTR_I2A_8821C)
+#define BITS_CMU_DLY_LTR_I2A_8821C                                             \
+	(BIT_MASK_CMU_DLY_LTR_I2A_8821C << BIT_SHIFT_CMU_DLY_LTR_I2A_8821C)
+#define BIT_CLEAR_CMU_DLY_LTR_I2A_8821C(x) ((x) & (~BITS_CMU_DLY_LTR_I2A_8821C))
+#define BIT_GET_CMU_DLY_LTR_I2A_8821C(x)                                       \
+	(((x) >> BIT_SHIFT_CMU_DLY_LTR_I2A_8821C) &                            \
+	 BIT_MASK_CMU_DLY_LTR_I2A_8821C)
+#define BIT_SET_CMU_DLY_LTR_I2A_8821C(x, v)                                    \
+	(BIT_CLEAR_CMU_DLY_LTR_I2A_8821C(x) | BIT_CMU_DLY_LTR_I2A_8821C(v))
+
+#define BIT_SHIFT_CMU_DLY_LTR_IDLE_8821C 8
+#define BIT_MASK_CMU_DLY_LTR_IDLE_8821C 0xff
+#define BIT_CMU_DLY_LTR_IDLE_8821C(x)                                          \
+	(((x) & BIT_MASK_CMU_DLY_LTR_IDLE_8821C)                               \
+	 << BIT_SHIFT_CMU_DLY_LTR_IDLE_8821C)
+#define BITS_CMU_DLY_LTR_IDLE_8821C                                            \
+	(BIT_MASK_CMU_DLY_LTR_IDLE_8821C << BIT_SHIFT_CMU_DLY_LTR_IDLE_8821C)
+#define BIT_CLEAR_CMU_DLY_LTR_IDLE_8821C(x)                                    \
+	((x) & (~BITS_CMU_DLY_LTR_IDLE_8821C))
+#define BIT_GET_CMU_DLY_LTR_IDLE_8821C(x)                                      \
+	(((x) >> BIT_SHIFT_CMU_DLY_LTR_IDLE_8821C) &                           \
+	 BIT_MASK_CMU_DLY_LTR_IDLE_8821C)
+#define BIT_SET_CMU_DLY_LTR_IDLE_8821C(x, v)                                   \
+	(BIT_CLEAR_CMU_DLY_LTR_IDLE_8821C(x) | BIT_CMU_DLY_LTR_IDLE_8821C(v))
+
+#define BIT_SHIFT_CMU_DLY_LTR_ACT_8821C 0
+#define BIT_MASK_CMU_DLY_LTR_ACT_8821C 0xff
+#define BIT_CMU_DLY_LTR_ACT_8821C(x)                                           \
+	(((x) & BIT_MASK_CMU_DLY_LTR_ACT_8821C)                                \
+	 << BIT_SHIFT_CMU_DLY_LTR_ACT_8821C)
+#define BITS_CMU_DLY_LTR_ACT_8821C                                             \
+	(BIT_MASK_CMU_DLY_LTR_ACT_8821C << BIT_SHIFT_CMU_DLY_LTR_ACT_8821C)
+#define BIT_CLEAR_CMU_DLY_LTR_ACT_8821C(x) ((x) & (~BITS_CMU_DLY_LTR_ACT_8821C))
+#define BIT_GET_CMU_DLY_LTR_ACT_8821C(x)                                       \
+	(((x) >> BIT_SHIFT_CMU_DLY_LTR_ACT_8821C) &                            \
+	 BIT_MASK_CMU_DLY_LTR_ACT_8821C)
+#define BIT_SET_CMU_DLY_LTR_ACT_8821C(x, v)                                    \
+	(BIT_CLEAR_CMU_DLY_LTR_ACT_8821C(x) | BIT_CMU_DLY_LTR_ACT_8821C(v))
+
+/* 2 REG_H2CQ_TXBD_DESA_8821C */
+
+#define BIT_SHIFT_H2CQ_TXBD_DESA_8821C 0
+#define BIT_MASK_H2CQ_TXBD_DESA_8821C 0xffffffffffffffffL
+#define BIT_H2CQ_TXBD_DESA_8821C(x)                                            \
+	(((x) & BIT_MASK_H2CQ_TXBD_DESA_8821C)                                 \
+	 << BIT_SHIFT_H2CQ_TXBD_DESA_8821C)
+#define BITS_H2CQ_TXBD_DESA_8821C                                              \
+	(BIT_MASK_H2CQ_TXBD_DESA_8821C << BIT_SHIFT_H2CQ_TXBD_DESA_8821C)
+#define BIT_CLEAR_H2CQ_TXBD_DESA_8821C(x) ((x) & (~BITS_H2CQ_TXBD_DESA_8821C))
+#define BIT_GET_H2CQ_TXBD_DESA_8821C(x)                                        \
+	(((x) >> BIT_SHIFT_H2CQ_TXBD_DESA_8821C) &                             \
+	 BIT_MASK_H2CQ_TXBD_DESA_8821C)
+#define BIT_SET_H2CQ_TXBD_DESA_8821C(x, v)                                     \
+	(BIT_CLEAR_H2CQ_TXBD_DESA_8821C(x) | BIT_H2CQ_TXBD_DESA_8821C(v))
+
+/* 2 REG_H2CQ_TXBD_NUM_8821C */
+#define BIT_PCIE_H2CQ_FLAG_8821C BIT(14)
+
+#define BIT_SHIFT_H2CQ_DESC_MODE_8821C 12
+#define BIT_MASK_H2CQ_DESC_MODE_8821C 0x3
+#define BIT_H2CQ_DESC_MODE_8821C(x)                                            \
+	(((x) & BIT_MASK_H2CQ_DESC_MODE_8821C)                                 \
+	 << BIT_SHIFT_H2CQ_DESC_MODE_8821C)
+#define BITS_H2CQ_DESC_MODE_8821C                                              \
+	(BIT_MASK_H2CQ_DESC_MODE_8821C << BIT_SHIFT_H2CQ_DESC_MODE_8821C)
+#define BIT_CLEAR_H2CQ_DESC_MODE_8821C(x) ((x) & (~BITS_H2CQ_DESC_MODE_8821C))
+#define BIT_GET_H2CQ_DESC_MODE_8821C(x)                                        \
+	(((x) >> BIT_SHIFT_H2CQ_DESC_MODE_8821C) &                             \
+	 BIT_MASK_H2CQ_DESC_MODE_8821C)
+#define BIT_SET_H2CQ_DESC_MODE_8821C(x, v)                                     \
+	(BIT_CLEAR_H2CQ_DESC_MODE_8821C(x) | BIT_H2CQ_DESC_MODE_8821C(v))
+
+#define BIT_SHIFT_H2CQ_DESC_NUM_8821C 0
+#define BIT_MASK_H2CQ_DESC_NUM_8821C 0xfff
+#define BIT_H2CQ_DESC_NUM_8821C(x)                                             \
+	(((x) & BIT_MASK_H2CQ_DESC_NUM_8821C) << BIT_SHIFT_H2CQ_DESC_NUM_8821C)
+#define BITS_H2CQ_DESC_NUM_8821C                                               \
+	(BIT_MASK_H2CQ_DESC_NUM_8821C << BIT_SHIFT_H2CQ_DESC_NUM_8821C)
+#define BIT_CLEAR_H2CQ_DESC_NUM_8821C(x) ((x) & (~BITS_H2CQ_DESC_NUM_8821C))
+#define BIT_GET_H2CQ_DESC_NUM_8821C(x)                                         \
+	(((x) >> BIT_SHIFT_H2CQ_DESC_NUM_8821C) & BIT_MASK_H2CQ_DESC_NUM_8821C)
+#define BIT_SET_H2CQ_DESC_NUM_8821C(x, v)                                      \
+	(BIT_CLEAR_H2CQ_DESC_NUM_8821C(x) | BIT_H2CQ_DESC_NUM_8821C(v))
+
+/* 2 REG_H2CQ_TXBD_IDX_8821C */
+
+#define BIT_SHIFT_H2CQ_HW_IDX_8821C 16
+#define BIT_MASK_H2CQ_HW_IDX_8821C 0xfff
+#define BIT_H2CQ_HW_IDX_8821C(x)                                               \
+	(((x) & BIT_MASK_H2CQ_HW_IDX_8821C) << BIT_SHIFT_H2CQ_HW_IDX_8821C)
+#define BITS_H2CQ_HW_IDX_8821C                                                 \
+	(BIT_MASK_H2CQ_HW_IDX_8821C << BIT_SHIFT_H2CQ_HW_IDX_8821C)
+#define BIT_CLEAR_H2CQ_HW_IDX_8821C(x) ((x) & (~BITS_H2CQ_HW_IDX_8821C))
+#define BIT_GET_H2CQ_HW_IDX_8821C(x)                                           \
+	(((x) >> BIT_SHIFT_H2CQ_HW_IDX_8821C) & BIT_MASK_H2CQ_HW_IDX_8821C)
+#define BIT_SET_H2CQ_HW_IDX_8821C(x, v)                                        \
+	(BIT_CLEAR_H2CQ_HW_IDX_8821C(x) | BIT_H2CQ_HW_IDX_8821C(v))
+
+#define BIT_SHIFT_H2CQ_HOST_IDX_8821C 0
+#define BIT_MASK_H2CQ_HOST_IDX_8821C 0xfff
+#define BIT_H2CQ_HOST_IDX_8821C(x)                                             \
+	(((x) & BIT_MASK_H2CQ_HOST_IDX_8821C) << BIT_SHIFT_H2CQ_HOST_IDX_8821C)
+#define BITS_H2CQ_HOST_IDX_8821C                                               \
+	(BIT_MASK_H2CQ_HOST_IDX_8821C << BIT_SHIFT_H2CQ_HOST_IDX_8821C)
+#define BIT_CLEAR_H2CQ_HOST_IDX_8821C(x) ((x) & (~BITS_H2CQ_HOST_IDX_8821C))
+#define BIT_GET_H2CQ_HOST_IDX_8821C(x)                                         \
+	(((x) >> BIT_SHIFT_H2CQ_HOST_IDX_8821C) & BIT_MASK_H2CQ_HOST_IDX_8821C)
+#define BIT_SET_H2CQ_HOST_IDX_8821C(x, v)                                      \
+	(BIT_CLEAR_H2CQ_HOST_IDX_8821C(x) | BIT_H2CQ_HOST_IDX_8821C(v))
+
+/* 2 REG_H2CQ_CSR_8821C[31:0] (H2CQ CONTROL AND STATUS) */
+#define BIT_H2CQ_FULL_8821C BIT(31)
+#define BIT_CLR_H2CQ_HOST_IDX_8821C BIT(16)
+#define BIT_CLR_H2CQ_HW_IDX_8821C BIT(8)
+#define BIT_STOP_H2CQ_8821C BIT(0)
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_Q0_INFO_8821C */
+
+#define BIT_SHIFT_QUEUEMACID_Q0_V1_8821C 25
+#define BIT_MASK_QUEUEMACID_Q0_V1_8821C 0x7f
+#define BIT_QUEUEMACID_Q0_V1_8821C(x)                                          \
+	(((x) & BIT_MASK_QUEUEMACID_Q0_V1_8821C)                               \
+	 << BIT_SHIFT_QUEUEMACID_Q0_V1_8821C)
+#define BITS_QUEUEMACID_Q0_V1_8821C                                            \
+	(BIT_MASK_QUEUEMACID_Q0_V1_8821C << BIT_SHIFT_QUEUEMACID_Q0_V1_8821C)
+#define BIT_CLEAR_QUEUEMACID_Q0_V1_8821C(x)                                    \
+	((x) & (~BITS_QUEUEMACID_Q0_V1_8821C))
+#define BIT_GET_QUEUEMACID_Q0_V1_8821C(x)                                      \
+	(((x) >> BIT_SHIFT_QUEUEMACID_Q0_V1_8821C) &                           \
+	 BIT_MASK_QUEUEMACID_Q0_V1_8821C)
+#define BIT_SET_QUEUEMACID_Q0_V1_8821C(x, v)                                   \
+	(BIT_CLEAR_QUEUEMACID_Q0_V1_8821C(x) | BIT_QUEUEMACID_Q0_V1_8821C(v))
+
+#define BIT_SHIFT_QUEUEAC_Q0_V1_8821C 23
+#define BIT_MASK_QUEUEAC_Q0_V1_8821C 0x3
+#define BIT_QUEUEAC_Q0_V1_8821C(x)                                             \
+	(((x) & BIT_MASK_QUEUEAC_Q0_V1_8821C) << BIT_SHIFT_QUEUEAC_Q0_V1_8821C)
+#define BITS_QUEUEAC_Q0_V1_8821C                                               \
+	(BIT_MASK_QUEUEAC_Q0_V1_8821C << BIT_SHIFT_QUEUEAC_Q0_V1_8821C)
+#define BIT_CLEAR_QUEUEAC_Q0_V1_8821C(x) ((x) & (~BITS_QUEUEAC_Q0_V1_8821C))
+#define BIT_GET_QUEUEAC_Q0_V1_8821C(x)                                         \
+	(((x) >> BIT_SHIFT_QUEUEAC_Q0_V1_8821C) & BIT_MASK_QUEUEAC_Q0_V1_8821C)
+#define BIT_SET_QUEUEAC_Q0_V1_8821C(x, v)                                      \
+	(BIT_CLEAR_QUEUEAC_Q0_V1_8821C(x) | BIT_QUEUEAC_Q0_V1_8821C(v))
+
+#define BIT_TIDEMPTY_Q0_V1_8821C BIT(22)
+
+#define BIT_SHIFT_TAIL_PKT_Q0_V2_8821C 11
+#define BIT_MASK_TAIL_PKT_Q0_V2_8821C 0x7ff
+#define BIT_TAIL_PKT_Q0_V2_8821C(x)                                            \
+	(((x) & BIT_MASK_TAIL_PKT_Q0_V2_8821C)                                 \
+	 << BIT_SHIFT_TAIL_PKT_Q0_V2_8821C)
+#define BITS_TAIL_PKT_Q0_V2_8821C                                              \
+	(BIT_MASK_TAIL_PKT_Q0_V2_8821C << BIT_SHIFT_TAIL_PKT_Q0_V2_8821C)
+#define BIT_CLEAR_TAIL_PKT_Q0_V2_8821C(x) ((x) & (~BITS_TAIL_PKT_Q0_V2_8821C))
+#define BIT_GET_TAIL_PKT_Q0_V2_8821C(x)                                        \
+	(((x) >> BIT_SHIFT_TAIL_PKT_Q0_V2_8821C) &                             \
+	 BIT_MASK_TAIL_PKT_Q0_V2_8821C)
+#define BIT_SET_TAIL_PKT_Q0_V2_8821C(x, v)                                     \
+	(BIT_CLEAR_TAIL_PKT_Q0_V2_8821C(x) | BIT_TAIL_PKT_Q0_V2_8821C(v))
+
+#define BIT_SHIFT_HEAD_PKT_Q0_V1_8821C 0
+#define BIT_MASK_HEAD_PKT_Q0_V1_8821C 0x7ff
+#define BIT_HEAD_PKT_Q0_V1_8821C(x)                                            \
+	(((x) & BIT_MASK_HEAD_PKT_Q0_V1_8821C)                                 \
+	 << BIT_SHIFT_HEAD_PKT_Q0_V1_8821C)
+#define BITS_HEAD_PKT_Q0_V1_8821C                                              \
+	(BIT_MASK_HEAD_PKT_Q0_V1_8821C << BIT_SHIFT_HEAD_PKT_Q0_V1_8821C)
+#define BIT_CLEAR_HEAD_PKT_Q0_V1_8821C(x) ((x) & (~BITS_HEAD_PKT_Q0_V1_8821C))
+#define BIT_GET_HEAD_PKT_Q0_V1_8821C(x)                                        \
+	(((x) >> BIT_SHIFT_HEAD_PKT_Q0_V1_8821C) &                             \
+	 BIT_MASK_HEAD_PKT_Q0_V1_8821C)
+#define BIT_SET_HEAD_PKT_Q0_V1_8821C(x, v)                                     \
+	(BIT_CLEAR_HEAD_PKT_Q0_V1_8821C(x) | BIT_HEAD_PKT_Q0_V1_8821C(v))
+
+/* 2 REG_Q1_INFO_8821C */
+
+#define BIT_SHIFT_QUEUEMACID_Q1_V1_8821C 25
+#define BIT_MASK_QUEUEMACID_Q1_V1_8821C 0x7f
+#define BIT_QUEUEMACID_Q1_V1_8821C(x)                                          \
+	(((x) & BIT_MASK_QUEUEMACID_Q1_V1_8821C)                               \
+	 << BIT_SHIFT_QUEUEMACID_Q1_V1_8821C)
+#define BITS_QUEUEMACID_Q1_V1_8821C                                            \
+	(BIT_MASK_QUEUEMACID_Q1_V1_8821C << BIT_SHIFT_QUEUEMACID_Q1_V1_8821C)
+#define BIT_CLEAR_QUEUEMACID_Q1_V1_8821C(x)                                    \
+	((x) & (~BITS_QUEUEMACID_Q1_V1_8821C))
+#define BIT_GET_QUEUEMACID_Q1_V1_8821C(x)                                      \
+	(((x) >> BIT_SHIFT_QUEUEMACID_Q1_V1_8821C) &                           \
+	 BIT_MASK_QUEUEMACID_Q1_V1_8821C)
+#define BIT_SET_QUEUEMACID_Q1_V1_8821C(x, v)                                   \
+	(BIT_CLEAR_QUEUEMACID_Q1_V1_8821C(x) | BIT_QUEUEMACID_Q1_V1_8821C(v))
+
+#define BIT_SHIFT_QUEUEAC_Q1_V1_8821C 23
+#define BIT_MASK_QUEUEAC_Q1_V1_8821C 0x3
+#define BIT_QUEUEAC_Q1_V1_8821C(x)                                             \
+	(((x) & BIT_MASK_QUEUEAC_Q1_V1_8821C) << BIT_SHIFT_QUEUEAC_Q1_V1_8821C)
+#define BITS_QUEUEAC_Q1_V1_8821C                                               \
+	(BIT_MASK_QUEUEAC_Q1_V1_8821C << BIT_SHIFT_QUEUEAC_Q1_V1_8821C)
+#define BIT_CLEAR_QUEUEAC_Q1_V1_8821C(x) ((x) & (~BITS_QUEUEAC_Q1_V1_8821C))
+#define BIT_GET_QUEUEAC_Q1_V1_8821C(x)                                         \
+	(((x) >> BIT_SHIFT_QUEUEAC_Q1_V1_8821C) & BIT_MASK_QUEUEAC_Q1_V1_8821C)
+#define BIT_SET_QUEUEAC_Q1_V1_8821C(x, v)                                      \
+	(BIT_CLEAR_QUEUEAC_Q1_V1_8821C(x) | BIT_QUEUEAC_Q1_V1_8821C(v))
+
+#define BIT_TIDEMPTY_Q1_V1_8821C BIT(22)
+
+#define BIT_SHIFT_TAIL_PKT_Q1_V2_8821C 11
+#define BIT_MASK_TAIL_PKT_Q1_V2_8821C 0x7ff
+#define BIT_TAIL_PKT_Q1_V2_8821C(x)                                            \
+	(((x) & BIT_MASK_TAIL_PKT_Q1_V2_8821C)                                 \
+	 << BIT_SHIFT_TAIL_PKT_Q1_V2_8821C)
+#define BITS_TAIL_PKT_Q1_V2_8821C                                              \
+	(BIT_MASK_TAIL_PKT_Q1_V2_8821C << BIT_SHIFT_TAIL_PKT_Q1_V2_8821C)
+#define BIT_CLEAR_TAIL_PKT_Q1_V2_8821C(x) ((x) & (~BITS_TAIL_PKT_Q1_V2_8821C))
+#define BIT_GET_TAIL_PKT_Q1_V2_8821C(x)                                        \
+	(((x) >> BIT_SHIFT_TAIL_PKT_Q1_V2_8821C) &                             \
+	 BIT_MASK_TAIL_PKT_Q1_V2_8821C)
+#define BIT_SET_TAIL_PKT_Q1_V2_8821C(x, v)                                     \
+	(BIT_CLEAR_TAIL_PKT_Q1_V2_8821C(x) | BIT_TAIL_PKT_Q1_V2_8821C(v))
+
+#define BIT_SHIFT_HEAD_PKT_Q1_V1_8821C 0
+#define BIT_MASK_HEAD_PKT_Q1_V1_8821C 0x7ff
+#define BIT_HEAD_PKT_Q1_V1_8821C(x)                                            \
+	(((x) & BIT_MASK_HEAD_PKT_Q1_V1_8821C)                                 \
+	 << BIT_SHIFT_HEAD_PKT_Q1_V1_8821C)
+#define BITS_HEAD_PKT_Q1_V1_8821C                                              \
+	(BIT_MASK_HEAD_PKT_Q1_V1_8821C << BIT_SHIFT_HEAD_PKT_Q1_V1_8821C)
+#define BIT_CLEAR_HEAD_PKT_Q1_V1_8821C(x) ((x) & (~BITS_HEAD_PKT_Q1_V1_8821C))
+#define BIT_GET_HEAD_PKT_Q1_V1_8821C(x)                                        \
+	(((x) >> BIT_SHIFT_HEAD_PKT_Q1_V1_8821C) &                             \
+	 BIT_MASK_HEAD_PKT_Q1_V1_8821C)
+#define BIT_SET_HEAD_PKT_Q1_V1_8821C(x, v)                                     \
+	(BIT_CLEAR_HEAD_PKT_Q1_V1_8821C(x) | BIT_HEAD_PKT_Q1_V1_8821C(v))
+
+/* 2 REG_Q2_INFO_8821C */
+
+#define BIT_SHIFT_QUEUEMACID_Q2_V1_8821C 25
+#define BIT_MASK_QUEUEMACID_Q2_V1_8821C 0x7f
+#define BIT_QUEUEMACID_Q2_V1_8821C(x)                                          \
+	(((x) & BIT_MASK_QUEUEMACID_Q2_V1_8821C)                               \
+	 << BIT_SHIFT_QUEUEMACID_Q2_V1_8821C)
+#define BITS_QUEUEMACID_Q2_V1_8821C                                            \
+	(BIT_MASK_QUEUEMACID_Q2_V1_8821C << BIT_SHIFT_QUEUEMACID_Q2_V1_8821C)
+#define BIT_CLEAR_QUEUEMACID_Q2_V1_8821C(x)                                    \
+	((x) & (~BITS_QUEUEMACID_Q2_V1_8821C))
+#define BIT_GET_QUEUEMACID_Q2_V1_8821C(x)                                      \
+	(((x) >> BIT_SHIFT_QUEUEMACID_Q2_V1_8821C) &                           \
+	 BIT_MASK_QUEUEMACID_Q2_V1_8821C)
+#define BIT_SET_QUEUEMACID_Q2_V1_8821C(x, v)                                   \
+	(BIT_CLEAR_QUEUEMACID_Q2_V1_8821C(x) | BIT_QUEUEMACID_Q2_V1_8821C(v))
+
+#define BIT_SHIFT_QUEUEAC_Q2_V1_8821C 23
+#define BIT_MASK_QUEUEAC_Q2_V1_8821C 0x3
+#define BIT_QUEUEAC_Q2_V1_8821C(x)                                             \
+	(((x) & BIT_MASK_QUEUEAC_Q2_V1_8821C) << BIT_SHIFT_QUEUEAC_Q2_V1_8821C)
+#define BITS_QUEUEAC_Q2_V1_8821C                                               \
+	(BIT_MASK_QUEUEAC_Q2_V1_8821C << BIT_SHIFT_QUEUEAC_Q2_V1_8821C)
+#define BIT_CLEAR_QUEUEAC_Q2_V1_8821C(x) ((x) & (~BITS_QUEUEAC_Q2_V1_8821C))
+#define BIT_GET_QUEUEAC_Q2_V1_8821C(x)                                         \
+	(((x) >> BIT_SHIFT_QUEUEAC_Q2_V1_8821C) & BIT_MASK_QUEUEAC_Q2_V1_8821C)
+#define BIT_SET_QUEUEAC_Q2_V1_8821C(x, v)                                      \
+	(BIT_CLEAR_QUEUEAC_Q2_V1_8821C(x) | BIT_QUEUEAC_Q2_V1_8821C(v))
+
+#define BIT_TIDEMPTY_Q2_V1_8821C BIT(22)
+
+#define BIT_SHIFT_TAIL_PKT_Q2_V2_8821C 11
+#define BIT_MASK_TAIL_PKT_Q2_V2_8821C 0x7ff
+#define BIT_TAIL_PKT_Q2_V2_8821C(x)                                            \
+	(((x) & BIT_MASK_TAIL_PKT_Q2_V2_8821C)                                 \
+	 << BIT_SHIFT_TAIL_PKT_Q2_V2_8821C)
+#define BITS_TAIL_PKT_Q2_V2_8821C                                              \
+	(BIT_MASK_TAIL_PKT_Q2_V2_8821C << BIT_SHIFT_TAIL_PKT_Q2_V2_8821C)
+#define BIT_CLEAR_TAIL_PKT_Q2_V2_8821C(x) ((x) & (~BITS_TAIL_PKT_Q2_V2_8821C))
+#define BIT_GET_TAIL_PKT_Q2_V2_8821C(x)                                        \
+	(((x) >> BIT_SHIFT_TAIL_PKT_Q2_V2_8821C) &                             \
+	 BIT_MASK_TAIL_PKT_Q2_V2_8821C)
+#define BIT_SET_TAIL_PKT_Q2_V2_8821C(x, v)                                     \
+	(BIT_CLEAR_TAIL_PKT_Q2_V2_8821C(x) | BIT_TAIL_PKT_Q2_V2_8821C(v))
+
+#define BIT_SHIFT_HEAD_PKT_Q2_V1_8821C 0
+#define BIT_MASK_HEAD_PKT_Q2_V1_8821C 0x7ff
+#define BIT_HEAD_PKT_Q2_V1_8821C(x)                                            \
+	(((x) & BIT_MASK_HEAD_PKT_Q2_V1_8821C)                                 \
+	 << BIT_SHIFT_HEAD_PKT_Q2_V1_8821C)
+#define BITS_HEAD_PKT_Q2_V1_8821C                                              \
+	(BIT_MASK_HEAD_PKT_Q2_V1_8821C << BIT_SHIFT_HEAD_PKT_Q2_V1_8821C)
+#define BIT_CLEAR_HEAD_PKT_Q2_V1_8821C(x) ((x) & (~BITS_HEAD_PKT_Q2_V1_8821C))
+#define BIT_GET_HEAD_PKT_Q2_V1_8821C(x)                                        \
+	(((x) >> BIT_SHIFT_HEAD_PKT_Q2_V1_8821C) &                             \
+	 BIT_MASK_HEAD_PKT_Q2_V1_8821C)
+#define BIT_SET_HEAD_PKT_Q2_V1_8821C(x, v)                                     \
+	(BIT_CLEAR_HEAD_PKT_Q2_V1_8821C(x) | BIT_HEAD_PKT_Q2_V1_8821C(v))
+
+/* 2 REG_Q3_INFO_8821C */
+
+#define BIT_SHIFT_QUEUEMACID_Q3_V1_8821C 25
+#define BIT_MASK_QUEUEMACID_Q3_V1_8821C 0x7f
+#define BIT_QUEUEMACID_Q3_V1_8821C(x)                                          \
+	(((x) & BIT_MASK_QUEUEMACID_Q3_V1_8821C)                               \
+	 << BIT_SHIFT_QUEUEMACID_Q3_V1_8821C)
+#define BITS_QUEUEMACID_Q3_V1_8821C                                            \
+	(BIT_MASK_QUEUEMACID_Q3_V1_8821C << BIT_SHIFT_QUEUEMACID_Q3_V1_8821C)
+#define BIT_CLEAR_QUEUEMACID_Q3_V1_8821C(x)                                    \
+	((x) & (~BITS_QUEUEMACID_Q3_V1_8821C))
+#define BIT_GET_QUEUEMACID_Q3_V1_8821C(x)                                      \
+	(((x) >> BIT_SHIFT_QUEUEMACID_Q3_V1_8821C) &                           \
+	 BIT_MASK_QUEUEMACID_Q3_V1_8821C)
+#define BIT_SET_QUEUEMACID_Q3_V1_8821C(x, v)                                   \
+	(BIT_CLEAR_QUEUEMACID_Q3_V1_8821C(x) | BIT_QUEUEMACID_Q3_V1_8821C(v))
+
+#define BIT_SHIFT_QUEUEAC_Q3_V1_8821C 23
+#define BIT_MASK_QUEUEAC_Q3_V1_8821C 0x3
+#define BIT_QUEUEAC_Q3_V1_8821C(x)                                             \
+	(((x) & BIT_MASK_QUEUEAC_Q3_V1_8821C) << BIT_SHIFT_QUEUEAC_Q3_V1_8821C)
+#define BITS_QUEUEAC_Q3_V1_8821C                                               \
+	(BIT_MASK_QUEUEAC_Q3_V1_8821C << BIT_SHIFT_QUEUEAC_Q3_V1_8821C)
+#define BIT_CLEAR_QUEUEAC_Q3_V1_8821C(x) ((x) & (~BITS_QUEUEAC_Q3_V1_8821C))
+#define BIT_GET_QUEUEAC_Q3_V1_8821C(x)                                         \
+	(((x) >> BIT_SHIFT_QUEUEAC_Q3_V1_8821C) & BIT_MASK_QUEUEAC_Q3_V1_8821C)
+#define BIT_SET_QUEUEAC_Q3_V1_8821C(x, v)                                      \
+	(BIT_CLEAR_QUEUEAC_Q3_V1_8821C(x) | BIT_QUEUEAC_Q3_V1_8821C(v))
+
+#define BIT_TIDEMPTY_Q3_V1_8821C BIT(22)
+
+#define BIT_SHIFT_TAIL_PKT_Q3_V2_8821C 11
+#define BIT_MASK_TAIL_PKT_Q3_V2_8821C 0x7ff
+#define BIT_TAIL_PKT_Q3_V2_8821C(x)                                            \
+	(((x) & BIT_MASK_TAIL_PKT_Q3_V2_8821C)                                 \
+	 << BIT_SHIFT_TAIL_PKT_Q3_V2_8821C)
+#define BITS_TAIL_PKT_Q3_V2_8821C                                              \
+	(BIT_MASK_TAIL_PKT_Q3_V2_8821C << BIT_SHIFT_TAIL_PKT_Q3_V2_8821C)
+#define BIT_CLEAR_TAIL_PKT_Q3_V2_8821C(x) ((x) & (~BITS_TAIL_PKT_Q3_V2_8821C))
+#define BIT_GET_TAIL_PKT_Q3_V2_8821C(x)                                        \
+	(((x) >> BIT_SHIFT_TAIL_PKT_Q3_V2_8821C) &                             \
+	 BIT_MASK_TAIL_PKT_Q3_V2_8821C)
+#define BIT_SET_TAIL_PKT_Q3_V2_8821C(x, v)                                     \
+	(BIT_CLEAR_TAIL_PKT_Q3_V2_8821C(x) | BIT_TAIL_PKT_Q3_V2_8821C(v))
+
+#define BIT_SHIFT_HEAD_PKT_Q3_V1_8821C 0
+#define BIT_MASK_HEAD_PKT_Q3_V1_8821C 0x7ff
+#define BIT_HEAD_PKT_Q3_V1_8821C(x)                                            \
+	(((x) & BIT_MASK_HEAD_PKT_Q3_V1_8821C)                                 \
+	 << BIT_SHIFT_HEAD_PKT_Q3_V1_8821C)
+#define BITS_HEAD_PKT_Q3_V1_8821C                                              \
+	(BIT_MASK_HEAD_PKT_Q3_V1_8821C << BIT_SHIFT_HEAD_PKT_Q3_V1_8821C)
+#define BIT_CLEAR_HEAD_PKT_Q3_V1_8821C(x) ((x) & (~BITS_HEAD_PKT_Q3_V1_8821C))
+#define BIT_GET_HEAD_PKT_Q3_V1_8821C(x)                                        \
+	(((x) >> BIT_SHIFT_HEAD_PKT_Q3_V1_8821C) &                             \
+	 BIT_MASK_HEAD_PKT_Q3_V1_8821C)
+#define BIT_SET_HEAD_PKT_Q3_V1_8821C(x, v)                                     \
+	(BIT_CLEAR_HEAD_PKT_Q3_V1_8821C(x) | BIT_HEAD_PKT_Q3_V1_8821C(v))
+
+/* 2 REG_MGQ_INFO_8821C */
+
+#define BIT_SHIFT_QUEUEMACID_MGQ_V1_8821C 25
+#define BIT_MASK_QUEUEMACID_MGQ_V1_8821C 0x7f
+#define BIT_QUEUEMACID_MGQ_V1_8821C(x)                                         \
+	(((x) & BIT_MASK_QUEUEMACID_MGQ_V1_8821C)                              \
+	 << BIT_SHIFT_QUEUEMACID_MGQ_V1_8821C)
+#define BITS_QUEUEMACID_MGQ_V1_8821C                                           \
+	(BIT_MASK_QUEUEMACID_MGQ_V1_8821C << BIT_SHIFT_QUEUEMACID_MGQ_V1_8821C)
+#define BIT_CLEAR_QUEUEMACID_MGQ_V1_8821C(x)                                   \
+	((x) & (~BITS_QUEUEMACID_MGQ_V1_8821C))
+#define BIT_GET_QUEUEMACID_MGQ_V1_8821C(x)                                     \
+	(((x) >> BIT_SHIFT_QUEUEMACID_MGQ_V1_8821C) &                          \
+	 BIT_MASK_QUEUEMACID_MGQ_V1_8821C)
+#define BIT_SET_QUEUEMACID_MGQ_V1_8821C(x, v)                                  \
+	(BIT_CLEAR_QUEUEMACID_MGQ_V1_8821C(x) | BIT_QUEUEMACID_MGQ_V1_8821C(v))
+
+#define BIT_SHIFT_QUEUEAC_MGQ_V1_8821C 23
+#define BIT_MASK_QUEUEAC_MGQ_V1_8821C 0x3
+#define BIT_QUEUEAC_MGQ_V1_8821C(x)                                            \
+	(((x) & BIT_MASK_QUEUEAC_MGQ_V1_8821C)                                 \
+	 << BIT_SHIFT_QUEUEAC_MGQ_V1_8821C)
+#define BITS_QUEUEAC_MGQ_V1_8821C                                              \
+	(BIT_MASK_QUEUEAC_MGQ_V1_8821C << BIT_SHIFT_QUEUEAC_MGQ_V1_8821C)
+#define BIT_CLEAR_QUEUEAC_MGQ_V1_8821C(x) ((x) & (~BITS_QUEUEAC_MGQ_V1_8821C))
+#define BIT_GET_QUEUEAC_MGQ_V1_8821C(x)                                        \
+	(((x) >> BIT_SHIFT_QUEUEAC_MGQ_V1_8821C) &                             \
+	 BIT_MASK_QUEUEAC_MGQ_V1_8821C)
+#define BIT_SET_QUEUEAC_MGQ_V1_8821C(x, v)                                     \
+	(BIT_CLEAR_QUEUEAC_MGQ_V1_8821C(x) | BIT_QUEUEAC_MGQ_V1_8821C(v))
+
+#define BIT_TIDEMPTY_MGQ_V1_8821C BIT(22)
+
+#define BIT_SHIFT_TAIL_PKT_MGQ_V2_8821C 11
+#define BIT_MASK_TAIL_PKT_MGQ_V2_8821C 0x7ff
+#define BIT_TAIL_PKT_MGQ_V2_8821C(x)                                           \
+	(((x) & BIT_MASK_TAIL_PKT_MGQ_V2_8821C)                                \
+	 << BIT_SHIFT_TAIL_PKT_MGQ_V2_8821C)
+#define BITS_TAIL_PKT_MGQ_V2_8821C                                             \
+	(BIT_MASK_TAIL_PKT_MGQ_V2_8821C << BIT_SHIFT_TAIL_PKT_MGQ_V2_8821C)
+#define BIT_CLEAR_TAIL_PKT_MGQ_V2_8821C(x) ((x) & (~BITS_TAIL_PKT_MGQ_V2_8821C))
+#define BIT_GET_TAIL_PKT_MGQ_V2_8821C(x)                                       \
+	(((x) >> BIT_SHIFT_TAIL_PKT_MGQ_V2_8821C) &                            \
+	 BIT_MASK_TAIL_PKT_MGQ_V2_8821C)
+#define BIT_SET_TAIL_PKT_MGQ_V2_8821C(x, v)                                    \
+	(BIT_CLEAR_TAIL_PKT_MGQ_V2_8821C(x) | BIT_TAIL_PKT_MGQ_V2_8821C(v))
+
+#define BIT_SHIFT_HEAD_PKT_MGQ_V1_8821C 0
+#define BIT_MASK_HEAD_PKT_MGQ_V1_8821C 0x7ff
+#define BIT_HEAD_PKT_MGQ_V1_8821C(x)                                           \
+	(((x) & BIT_MASK_HEAD_PKT_MGQ_V1_8821C)                                \
+	 << BIT_SHIFT_HEAD_PKT_MGQ_V1_8821C)
+#define BITS_HEAD_PKT_MGQ_V1_8821C                                             \
+	(BIT_MASK_HEAD_PKT_MGQ_V1_8821C << BIT_SHIFT_HEAD_PKT_MGQ_V1_8821C)
+#define BIT_CLEAR_HEAD_PKT_MGQ_V1_8821C(x) ((x) & (~BITS_HEAD_PKT_MGQ_V1_8821C))
+#define BIT_GET_HEAD_PKT_MGQ_V1_8821C(x)                                       \
+	(((x) >> BIT_SHIFT_HEAD_PKT_MGQ_V1_8821C) &                            \
+	 BIT_MASK_HEAD_PKT_MGQ_V1_8821C)
+#define BIT_SET_HEAD_PKT_MGQ_V1_8821C(x, v)                                    \
+	(BIT_CLEAR_HEAD_PKT_MGQ_V1_8821C(x) | BIT_HEAD_PKT_MGQ_V1_8821C(v))
+
+/* 2 REG_HIQ_INFO_8821C */
+
+#define BIT_SHIFT_QUEUEMACID_HIQ_V1_8821C 25
+#define BIT_MASK_QUEUEMACID_HIQ_V1_8821C 0x7f
+#define BIT_QUEUEMACID_HIQ_V1_8821C(x)                                         \
+	(((x) & BIT_MASK_QUEUEMACID_HIQ_V1_8821C)                              \
+	 << BIT_SHIFT_QUEUEMACID_HIQ_V1_8821C)
+#define BITS_QUEUEMACID_HIQ_V1_8821C                                           \
+	(BIT_MASK_QUEUEMACID_HIQ_V1_8821C << BIT_SHIFT_QUEUEMACID_HIQ_V1_8821C)
+#define BIT_CLEAR_QUEUEMACID_HIQ_V1_8821C(x)                                   \
+	((x) & (~BITS_QUEUEMACID_HIQ_V1_8821C))
+#define BIT_GET_QUEUEMACID_HIQ_V1_8821C(x)                                     \
+	(((x) >> BIT_SHIFT_QUEUEMACID_HIQ_V1_8821C) &                          \
+	 BIT_MASK_QUEUEMACID_HIQ_V1_8821C)
+#define BIT_SET_QUEUEMACID_HIQ_V1_8821C(x, v)                                  \
+	(BIT_CLEAR_QUEUEMACID_HIQ_V1_8821C(x) | BIT_QUEUEMACID_HIQ_V1_8821C(v))
+
+#define BIT_SHIFT_QUEUEAC_HIQ_V1_8821C 23
+#define BIT_MASK_QUEUEAC_HIQ_V1_8821C 0x3
+#define BIT_QUEUEAC_HIQ_V1_8821C(x)                                            \
+	(((x) & BIT_MASK_QUEUEAC_HIQ_V1_8821C)                                 \
+	 << BIT_SHIFT_QUEUEAC_HIQ_V1_8821C)
+#define BITS_QUEUEAC_HIQ_V1_8821C                                              \
+	(BIT_MASK_QUEUEAC_HIQ_V1_8821C << BIT_SHIFT_QUEUEAC_HIQ_V1_8821C)
+#define BIT_CLEAR_QUEUEAC_HIQ_V1_8821C(x) ((x) & (~BITS_QUEUEAC_HIQ_V1_8821C))
+#define BIT_GET_QUEUEAC_HIQ_V1_8821C(x)                                        \
+	(((x) >> BIT_SHIFT_QUEUEAC_HIQ_V1_8821C) &                             \
+	 BIT_MASK_QUEUEAC_HIQ_V1_8821C)
+#define BIT_SET_QUEUEAC_HIQ_V1_8821C(x, v)                                     \
+	(BIT_CLEAR_QUEUEAC_HIQ_V1_8821C(x) | BIT_QUEUEAC_HIQ_V1_8821C(v))
+
+#define BIT_TIDEMPTY_HIQ_V1_8821C BIT(22)
+
+#define BIT_SHIFT_TAIL_PKT_HIQ_V2_8821C 11
+#define BIT_MASK_TAIL_PKT_HIQ_V2_8821C 0x7ff
+#define BIT_TAIL_PKT_HIQ_V2_8821C(x)                                           \
+	(((x) & BIT_MASK_TAIL_PKT_HIQ_V2_8821C)                                \
+	 << BIT_SHIFT_TAIL_PKT_HIQ_V2_8821C)
+#define BITS_TAIL_PKT_HIQ_V2_8821C                                             \
+	(BIT_MASK_TAIL_PKT_HIQ_V2_8821C << BIT_SHIFT_TAIL_PKT_HIQ_V2_8821C)
+#define BIT_CLEAR_TAIL_PKT_HIQ_V2_8821C(x) ((x) & (~BITS_TAIL_PKT_HIQ_V2_8821C))
+#define BIT_GET_TAIL_PKT_HIQ_V2_8821C(x)                                       \
+	(((x) >> BIT_SHIFT_TAIL_PKT_HIQ_V2_8821C) &                            \
+	 BIT_MASK_TAIL_PKT_HIQ_V2_8821C)
+#define BIT_SET_TAIL_PKT_HIQ_V2_8821C(x, v)                                    \
+	(BIT_CLEAR_TAIL_PKT_HIQ_V2_8821C(x) | BIT_TAIL_PKT_HIQ_V2_8821C(v))
+
+#define BIT_SHIFT_HEAD_PKT_HIQ_V1_8821C 0
+#define BIT_MASK_HEAD_PKT_HIQ_V1_8821C 0x7ff
+#define BIT_HEAD_PKT_HIQ_V1_8821C(x)                                           \
+	(((x) & BIT_MASK_HEAD_PKT_HIQ_V1_8821C)                                \
+	 << BIT_SHIFT_HEAD_PKT_HIQ_V1_8821C)
+#define BITS_HEAD_PKT_HIQ_V1_8821C                                             \
+	(BIT_MASK_HEAD_PKT_HIQ_V1_8821C << BIT_SHIFT_HEAD_PKT_HIQ_V1_8821C)
+#define BIT_CLEAR_HEAD_PKT_HIQ_V1_8821C(x) ((x) & (~BITS_HEAD_PKT_HIQ_V1_8821C))
+#define BIT_GET_HEAD_PKT_HIQ_V1_8821C(x)                                       \
+	(((x) >> BIT_SHIFT_HEAD_PKT_HIQ_V1_8821C) &                            \
+	 BIT_MASK_HEAD_PKT_HIQ_V1_8821C)
+#define BIT_SET_HEAD_PKT_HIQ_V1_8821C(x, v)                                    \
+	(BIT_CLEAR_HEAD_PKT_HIQ_V1_8821C(x) | BIT_HEAD_PKT_HIQ_V1_8821C(v))
+
+/* 2 REG_BCNQ_INFO_8821C */
+
+#define BIT_SHIFT_BCNQ_HEAD_PG_V1_8821C 0
+#define BIT_MASK_BCNQ_HEAD_PG_V1_8821C 0xfff
+#define BIT_BCNQ_HEAD_PG_V1_8821C(x)                                           \
+	(((x) & BIT_MASK_BCNQ_HEAD_PG_V1_8821C)                                \
+	 << BIT_SHIFT_BCNQ_HEAD_PG_V1_8821C)
+#define BITS_BCNQ_HEAD_PG_V1_8821C                                             \
+	(BIT_MASK_BCNQ_HEAD_PG_V1_8821C << BIT_SHIFT_BCNQ_HEAD_PG_V1_8821C)
+#define BIT_CLEAR_BCNQ_HEAD_PG_V1_8821C(x) ((x) & (~BITS_BCNQ_HEAD_PG_V1_8821C))
+#define BIT_GET_BCNQ_HEAD_PG_V1_8821C(x)                                       \
+	(((x) >> BIT_SHIFT_BCNQ_HEAD_PG_V1_8821C) &                            \
+	 BIT_MASK_BCNQ_HEAD_PG_V1_8821C)
+#define BIT_SET_BCNQ_HEAD_PG_V1_8821C(x, v)                                    \
+	(BIT_CLEAR_BCNQ_HEAD_PG_V1_8821C(x) | BIT_BCNQ_HEAD_PG_V1_8821C(v))
+
+/* 2 REG_TXPKT_EMPTY_8821C */
+#define BIT_BCNQ_EMPTY_8821C BIT(11)
+#define BIT_HQQ_EMPTY_8821C BIT(10)
+#define BIT_MQQ_EMPTY_8821C BIT(9)
+#define BIT_MGQ_CPU_EMPTY_8821C BIT(8)
+#define BIT_AC7Q_EMPTY_8821C BIT(7)
+#define BIT_AC6Q_EMPTY_8821C BIT(6)
+#define BIT_AC5Q_EMPTY_8821C BIT(5)
+#define BIT_AC4Q_EMPTY_8821C BIT(4)
+#define BIT_AC3Q_EMPTY_8821C BIT(3)
+#define BIT_AC2Q_EMPTY_8821C BIT(2)
+#define BIT_AC1Q_EMPTY_8821C BIT(1)
+#define BIT_AC0Q_EMPTY_8821C BIT(0)
+
+/* 2 REG_CPU_MGQ_INFO_8821C */
+#define BIT_BCN1_POLL_8821C BIT(30)
+#define BIT_CPUMGT_POLL_8821C BIT(29)
+#define BIT_BCN_POLL_8821C BIT(28)
+#define BIT_CPUMGQ_FW_NUM_V1_8821C BIT(12)
+
+#define BIT_SHIFT_FW_FREE_TAIL_V1_8821C 0
+#define BIT_MASK_FW_FREE_TAIL_V1_8821C 0xfff
+#define BIT_FW_FREE_TAIL_V1_8821C(x)                                           \
+	(((x) & BIT_MASK_FW_FREE_TAIL_V1_8821C)                                \
+	 << BIT_SHIFT_FW_FREE_TAIL_V1_8821C)
+#define BITS_FW_FREE_TAIL_V1_8821C                                             \
+	(BIT_MASK_FW_FREE_TAIL_V1_8821C << BIT_SHIFT_FW_FREE_TAIL_V1_8821C)
+#define BIT_CLEAR_FW_FREE_TAIL_V1_8821C(x) ((x) & (~BITS_FW_FREE_TAIL_V1_8821C))
+#define BIT_GET_FW_FREE_TAIL_V1_8821C(x)                                       \
+	(((x) >> BIT_SHIFT_FW_FREE_TAIL_V1_8821C) &                            \
+	 BIT_MASK_FW_FREE_TAIL_V1_8821C)
+#define BIT_SET_FW_FREE_TAIL_V1_8821C(x, v)                                    \
+	(BIT_CLEAR_FW_FREE_TAIL_V1_8821C(x) | BIT_FW_FREE_TAIL_V1_8821C(v))
+
+/* 2 REG_FWHW_TXQ_CTRL_8821C */
+#define BIT_RTS_LIMIT_IN_OFDM_8821C BIT(23)
+#define BIT_EN_BCNQ_DL_8821C BIT(22)
+#define BIT_EN_RD_RESP_NAV_BK_8821C BIT(21)
+#define BIT_EN_WR_FREE_TAIL_8821C BIT(20)
+
+#define BIT_SHIFT_EN_QUEUE_RPT_8821C 8
+#define BIT_MASK_EN_QUEUE_RPT_8821C 0xff
+#define BIT_EN_QUEUE_RPT_8821C(x)                                              \
+	(((x) & BIT_MASK_EN_QUEUE_RPT_8821C) << BIT_SHIFT_EN_QUEUE_RPT_8821C)
+#define BITS_EN_QUEUE_RPT_8821C                                                \
+	(BIT_MASK_EN_QUEUE_RPT_8821C << BIT_SHIFT_EN_QUEUE_RPT_8821C)
+#define BIT_CLEAR_EN_QUEUE_RPT_8821C(x) ((x) & (~BITS_EN_QUEUE_RPT_8821C))
+#define BIT_GET_EN_QUEUE_RPT_8821C(x)                                          \
+	(((x) >> BIT_SHIFT_EN_QUEUE_RPT_8821C) & BIT_MASK_EN_QUEUE_RPT_8821C)
+#define BIT_SET_EN_QUEUE_RPT_8821C(x, v)                                       \
+	(BIT_CLEAR_EN_QUEUE_RPT_8821C(x) | BIT_EN_QUEUE_RPT_8821C(v))
+
+#define BIT_EN_RTY_BK_8821C BIT(7)
+#define BIT_EN_USE_INI_RAT_8821C BIT(6)
+#define BIT_EN_RTS_NAV_BK_8821C BIT(5)
+#define BIT_DIS_SSN_CHECK_8821C BIT(4)
+#define BIT_MACID_MATCH_RTS_8821C BIT(3)
+#define BIT_EN_BCN_TRXRPT_V1_8821C BIT(2)
+#define BIT_R_EN_FTMRPT_V1_8821C BIT(1)
+#define BIT_R_BMC_NAV_PROTECT_8821C BIT(0)
+
+/* 2 REG_DATAFB_SEL_8821C */
+#define BIT_BROADCAST_RTY_EN_8821C BIT(3)
+#define BIT_EN_RTY_BK_COD_8821C BIT(2)
+
+#define BIT_SHIFT__R_DATA_FALLBACK_SEL_8821C 0
+#define BIT_MASK__R_DATA_FALLBACK_SEL_8821C 0x3
+#define BIT__R_DATA_FALLBACK_SEL_8821C(x)                                      \
+	(((x) & BIT_MASK__R_DATA_FALLBACK_SEL_8821C)                           \
+	 << BIT_SHIFT__R_DATA_FALLBACK_SEL_8821C)
+#define BITS__R_DATA_FALLBACK_SEL_8821C                                        \
+	(BIT_MASK__R_DATA_FALLBACK_SEL_8821C                                   \
+	 << BIT_SHIFT__R_DATA_FALLBACK_SEL_8821C)
+#define BIT_CLEAR__R_DATA_FALLBACK_SEL_8821C(x)                                \
+	((x) & (~BITS__R_DATA_FALLBACK_SEL_8821C))
+#define BIT_GET__R_DATA_FALLBACK_SEL_8821C(x)                                  \
+	(((x) >> BIT_SHIFT__R_DATA_FALLBACK_SEL_8821C) &                       \
+	 BIT_MASK__R_DATA_FALLBACK_SEL_8821C)
+#define BIT_SET__R_DATA_FALLBACK_SEL_8821C(x, v)                               \
+	(BIT_CLEAR__R_DATA_FALLBACK_SEL_8821C(x) |                             \
+	 BIT__R_DATA_FALLBACK_SEL_8821C(v))
+
+/* 2 REG_BCNQ_BDNY_V1_8821C */
+
+#define BIT_SHIFT_BCNQ_PGBNDY_V1_8821C 0
+#define BIT_MASK_BCNQ_PGBNDY_V1_8821C 0xfff
+#define BIT_BCNQ_PGBNDY_V1_8821C(x)                                            \
+	(((x) & BIT_MASK_BCNQ_PGBNDY_V1_8821C)                                 \
+	 << BIT_SHIFT_BCNQ_PGBNDY_V1_8821C)
+#define BITS_BCNQ_PGBNDY_V1_8821C                                              \
+	(BIT_MASK_BCNQ_PGBNDY_V1_8821C << BIT_SHIFT_BCNQ_PGBNDY_V1_8821C)
+#define BIT_CLEAR_BCNQ_PGBNDY_V1_8821C(x) ((x) & (~BITS_BCNQ_PGBNDY_V1_8821C))
+#define BIT_GET_BCNQ_PGBNDY_V1_8821C(x)                                        \
+	(((x) >> BIT_SHIFT_BCNQ_PGBNDY_V1_8821C) &                             \
+	 BIT_MASK_BCNQ_PGBNDY_V1_8821C)
+#define BIT_SET_BCNQ_PGBNDY_V1_8821C(x, v)                                     \
+	(BIT_CLEAR_BCNQ_PGBNDY_V1_8821C(x) | BIT_BCNQ_PGBNDY_V1_8821C(v))
+
+/* 2 REG_LIFETIME_EN_8821C */
+#define BIT_BT_INT_CPU_8821C BIT(7)
+#define BIT_BT_INT_PTA_8821C BIT(6)
+#define BIT_EN_CTRL_RTYBIT_8821C BIT(4)
+#define BIT_LIFETIME_BK_EN_8821C BIT(3)
+#define BIT_LIFETIME_BE_EN_8821C BIT(2)
+#define BIT_LIFETIME_VI_EN_8821C BIT(1)
+#define BIT_LIFETIME_VO_EN_8821C BIT(0)
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_SPEC_SIFS_8821C */
+
+#define BIT_SHIFT_SPEC_SIFS_OFDM_PTCL_8821C 8
+#define BIT_MASK_SPEC_SIFS_OFDM_PTCL_8821C 0xff
+#define BIT_SPEC_SIFS_OFDM_PTCL_8821C(x)                                       \
+	(((x) & BIT_MASK_SPEC_SIFS_OFDM_PTCL_8821C)                            \
+	 << BIT_SHIFT_SPEC_SIFS_OFDM_PTCL_8821C)
+#define BITS_SPEC_SIFS_OFDM_PTCL_8821C                                         \
+	(BIT_MASK_SPEC_SIFS_OFDM_PTCL_8821C                                    \
+	 << BIT_SHIFT_SPEC_SIFS_OFDM_PTCL_8821C)
+#define BIT_CLEAR_SPEC_SIFS_OFDM_PTCL_8821C(x)                                 \
+	((x) & (~BITS_SPEC_SIFS_OFDM_PTCL_8821C))
+#define BIT_GET_SPEC_SIFS_OFDM_PTCL_8821C(x)                                   \
+	(((x) >> BIT_SHIFT_SPEC_SIFS_OFDM_PTCL_8821C) &                        \
+	 BIT_MASK_SPEC_SIFS_OFDM_PTCL_8821C)
+#define BIT_SET_SPEC_SIFS_OFDM_PTCL_8821C(x, v)                                \
+	(BIT_CLEAR_SPEC_SIFS_OFDM_PTCL_8821C(x) |                              \
+	 BIT_SPEC_SIFS_OFDM_PTCL_8821C(v))
+
+#define BIT_SHIFT_SPEC_SIFS_CCK_PTCL_8821C 0
+#define BIT_MASK_SPEC_SIFS_CCK_PTCL_8821C 0xff
+#define BIT_SPEC_SIFS_CCK_PTCL_8821C(x)                                        \
+	(((x) & BIT_MASK_SPEC_SIFS_CCK_PTCL_8821C)                             \
+	 << BIT_SHIFT_SPEC_SIFS_CCK_PTCL_8821C)
+#define BITS_SPEC_SIFS_CCK_PTCL_8821C                                          \
+	(BIT_MASK_SPEC_SIFS_CCK_PTCL_8821C                                     \
+	 << BIT_SHIFT_SPEC_SIFS_CCK_PTCL_8821C)
+#define BIT_CLEAR_SPEC_SIFS_CCK_PTCL_8821C(x)                                  \
+	((x) & (~BITS_SPEC_SIFS_CCK_PTCL_8821C))
+#define BIT_GET_SPEC_SIFS_CCK_PTCL_8821C(x)                                    \
+	(((x) >> BIT_SHIFT_SPEC_SIFS_CCK_PTCL_8821C) &                         \
+	 BIT_MASK_SPEC_SIFS_CCK_PTCL_8821C)
+#define BIT_SET_SPEC_SIFS_CCK_PTCL_8821C(x, v)                                 \
+	(BIT_CLEAR_SPEC_SIFS_CCK_PTCL_8821C(x) |                               \
+	 BIT_SPEC_SIFS_CCK_PTCL_8821C(v))
+
+/* 2 REG_RETRY_LIMIT_8821C */
+
+#define BIT_SHIFT_SRL_8821C 8
+#define BIT_MASK_SRL_8821C 0x3f
+#define BIT_SRL_8821C(x) (((x) & BIT_MASK_SRL_8821C) << BIT_SHIFT_SRL_8821C)
+#define BITS_SRL_8821C (BIT_MASK_SRL_8821C << BIT_SHIFT_SRL_8821C)
+#define BIT_CLEAR_SRL_8821C(x) ((x) & (~BITS_SRL_8821C))
+#define BIT_GET_SRL_8821C(x) (((x) >> BIT_SHIFT_SRL_8821C) & BIT_MASK_SRL_8821C)
+#define BIT_SET_SRL_8821C(x, v) (BIT_CLEAR_SRL_8821C(x) | BIT_SRL_8821C(v))
+
+#define BIT_SHIFT_LRL_8821C 0
+#define BIT_MASK_LRL_8821C 0x3f
+#define BIT_LRL_8821C(x) (((x) & BIT_MASK_LRL_8821C) << BIT_SHIFT_LRL_8821C)
+#define BITS_LRL_8821C (BIT_MASK_LRL_8821C << BIT_SHIFT_LRL_8821C)
+#define BIT_CLEAR_LRL_8821C(x) ((x) & (~BITS_LRL_8821C))
+#define BIT_GET_LRL_8821C(x) (((x) >> BIT_SHIFT_LRL_8821C) & BIT_MASK_LRL_8821C)
+#define BIT_SET_LRL_8821C(x, v) (BIT_CLEAR_LRL_8821C(x) | BIT_LRL_8821C(v))
+
+/* 2 REG_TXBF_CTRL_8821C */
+#define BIT_R_ENABLE_NDPA_8821C BIT(31)
+#define BIT_USE_NDPA_PARAMETER_8821C BIT(30)
+#define BIT_R_PROP_TXBF_8821C BIT(29)
+#define BIT_R_EN_NDPA_INT_8821C BIT(28)
+#define BIT_R_TXBF1_80M_8821C BIT(27)
+#define BIT_R_TXBF1_40M_8821C BIT(26)
+#define BIT_R_TXBF1_20M_8821C BIT(25)
+
+#define BIT_SHIFT_R_TXBF1_AID_8821C 16
+#define BIT_MASK_R_TXBF1_AID_8821C 0x1ff
+#define BIT_R_TXBF1_AID_8821C(x)                                               \
+	(((x) & BIT_MASK_R_TXBF1_AID_8821C) << BIT_SHIFT_R_TXBF1_AID_8821C)
+#define BITS_R_TXBF1_AID_8821C                                                 \
+	(BIT_MASK_R_TXBF1_AID_8821C << BIT_SHIFT_R_TXBF1_AID_8821C)
+#define BIT_CLEAR_R_TXBF1_AID_8821C(x) ((x) & (~BITS_R_TXBF1_AID_8821C))
+#define BIT_GET_R_TXBF1_AID_8821C(x)                                           \
+	(((x) >> BIT_SHIFT_R_TXBF1_AID_8821C) & BIT_MASK_R_TXBF1_AID_8821C)
+#define BIT_SET_R_TXBF1_AID_8821C(x, v)                                        \
+	(BIT_CLEAR_R_TXBF1_AID_8821C(x) | BIT_R_TXBF1_AID_8821C(v))
+
+#define BIT_DIS_NDP_BFEN_8821C BIT(15)
+#define BIT_R_TXBCN_NOBLOCK_NDP_8821C BIT(14)
+#define BIT_R_TXBF0_80M_8821C BIT(11)
+#define BIT_R_TXBF0_40M_8821C BIT(10)
+#define BIT_R_TXBF0_20M_8821C BIT(9)
+
+#define BIT_SHIFT_R_TXBF0_AID_8821C 0
+#define BIT_MASK_R_TXBF0_AID_8821C 0x1ff
+#define BIT_R_TXBF0_AID_8821C(x)                                               \
+	(((x) & BIT_MASK_R_TXBF0_AID_8821C) << BIT_SHIFT_R_TXBF0_AID_8821C)
+#define BITS_R_TXBF0_AID_8821C                                                 \
+	(BIT_MASK_R_TXBF0_AID_8821C << BIT_SHIFT_R_TXBF0_AID_8821C)
+#define BIT_CLEAR_R_TXBF0_AID_8821C(x) ((x) & (~BITS_R_TXBF0_AID_8821C))
+#define BIT_GET_R_TXBF0_AID_8821C(x)                                           \
+	(((x) >> BIT_SHIFT_R_TXBF0_AID_8821C) & BIT_MASK_R_TXBF0_AID_8821C)
+#define BIT_SET_R_TXBF0_AID_8821C(x, v)                                        \
+	(BIT_CLEAR_R_TXBF0_AID_8821C(x) | BIT_R_TXBF0_AID_8821C(v))
+
+/* 2 REG_DARFRC_8821C */
+
+#define BIT_SHIFT_DARF_RC4_8821C 24
+#define BIT_MASK_DARF_RC4_8821C 0x1f
+#define BIT_DARF_RC4_8821C(x)                                                  \
+	(((x) & BIT_MASK_DARF_RC4_8821C) << BIT_SHIFT_DARF_RC4_8821C)
+#define BITS_DARF_RC4_8821C                                                    \
+	(BIT_MASK_DARF_RC4_8821C << BIT_SHIFT_DARF_RC4_8821C)
+#define BIT_CLEAR_DARF_RC4_8821C(x) ((x) & (~BITS_DARF_RC4_8821C))
+#define BIT_GET_DARF_RC4_8821C(x)                                              \
+	(((x) >> BIT_SHIFT_DARF_RC4_8821C) & BIT_MASK_DARF_RC4_8821C)
+#define BIT_SET_DARF_RC4_8821C(x, v)                                           \
+	(BIT_CLEAR_DARF_RC4_8821C(x) | BIT_DARF_RC4_8821C(v))
+
+#define BIT_SHIFT_DARF_RC3_8821C 16
+#define BIT_MASK_DARF_RC3_8821C 0x1f
+#define BIT_DARF_RC3_8821C(x)                                                  \
+	(((x) & BIT_MASK_DARF_RC3_8821C) << BIT_SHIFT_DARF_RC3_8821C)
+#define BITS_DARF_RC3_8821C                                                    \
+	(BIT_MASK_DARF_RC3_8821C << BIT_SHIFT_DARF_RC3_8821C)
+#define BIT_CLEAR_DARF_RC3_8821C(x) ((x) & (~BITS_DARF_RC3_8821C))
+#define BIT_GET_DARF_RC3_8821C(x)                                              \
+	(((x) >> BIT_SHIFT_DARF_RC3_8821C) & BIT_MASK_DARF_RC3_8821C)
+#define BIT_SET_DARF_RC3_8821C(x, v)                                           \
+	(BIT_CLEAR_DARF_RC3_8821C(x) | BIT_DARF_RC3_8821C(v))
+
+#define BIT_SHIFT_DARF_RC2_8821C 8
+#define BIT_MASK_DARF_RC2_8821C 0x1f
+#define BIT_DARF_RC2_8821C(x)                                                  \
+	(((x) & BIT_MASK_DARF_RC2_8821C) << BIT_SHIFT_DARF_RC2_8821C)
+#define BITS_DARF_RC2_8821C                                                    \
+	(BIT_MASK_DARF_RC2_8821C << BIT_SHIFT_DARF_RC2_8821C)
+#define BIT_CLEAR_DARF_RC2_8821C(x) ((x) & (~BITS_DARF_RC2_8821C))
+#define BIT_GET_DARF_RC2_8821C(x)                                              \
+	(((x) >> BIT_SHIFT_DARF_RC2_8821C) & BIT_MASK_DARF_RC2_8821C)
+#define BIT_SET_DARF_RC2_8821C(x, v)                                           \
+	(BIT_CLEAR_DARF_RC2_8821C(x) | BIT_DARF_RC2_8821C(v))
+
+#define BIT_SHIFT_DARF_RC1_8821C 0
+#define BIT_MASK_DARF_RC1_8821C 0x1f
+#define BIT_DARF_RC1_8821C(x)                                                  \
+	(((x) & BIT_MASK_DARF_RC1_8821C) << BIT_SHIFT_DARF_RC1_8821C)
+#define BITS_DARF_RC1_8821C                                                    \
+	(BIT_MASK_DARF_RC1_8821C << BIT_SHIFT_DARF_RC1_8821C)
+#define BIT_CLEAR_DARF_RC1_8821C(x) ((x) & (~BITS_DARF_RC1_8821C))
+#define BIT_GET_DARF_RC1_8821C(x)                                              \
+	(((x) >> BIT_SHIFT_DARF_RC1_8821C) & BIT_MASK_DARF_RC1_8821C)
+#define BIT_SET_DARF_RC1_8821C(x, v)                                           \
+	(BIT_CLEAR_DARF_RC1_8821C(x) | BIT_DARF_RC1_8821C(v))
+
+/* 2 REG_DARFRCH_8821C */
+
+#define BIT_SHIFT_DARF_RC8_V1_8821C 24
+#define BIT_MASK_DARF_RC8_V1_8821C 0x1f
+#define BIT_DARF_RC8_V1_8821C(x)                                               \
+	(((x) & BIT_MASK_DARF_RC8_V1_8821C) << BIT_SHIFT_DARF_RC8_V1_8821C)
+#define BITS_DARF_RC8_V1_8821C                                                 \
+	(BIT_MASK_DARF_RC8_V1_8821C << BIT_SHIFT_DARF_RC8_V1_8821C)
+#define BIT_CLEAR_DARF_RC8_V1_8821C(x) ((x) & (~BITS_DARF_RC8_V1_8821C))
+#define BIT_GET_DARF_RC8_V1_8821C(x)                                           \
+	(((x) >> BIT_SHIFT_DARF_RC8_V1_8821C) & BIT_MASK_DARF_RC8_V1_8821C)
+#define BIT_SET_DARF_RC8_V1_8821C(x, v)                                        \
+	(BIT_CLEAR_DARF_RC8_V1_8821C(x) | BIT_DARF_RC8_V1_8821C(v))
+
+#define BIT_SHIFT_DARF_RC7_V1_8821C 16
+#define BIT_MASK_DARF_RC7_V1_8821C 0x1f
+#define BIT_DARF_RC7_V1_8821C(x)                                               \
+	(((x) & BIT_MASK_DARF_RC7_V1_8821C) << BIT_SHIFT_DARF_RC7_V1_8821C)
+#define BITS_DARF_RC7_V1_8821C                                                 \
+	(BIT_MASK_DARF_RC7_V1_8821C << BIT_SHIFT_DARF_RC7_V1_8821C)
+#define BIT_CLEAR_DARF_RC7_V1_8821C(x) ((x) & (~BITS_DARF_RC7_V1_8821C))
+#define BIT_GET_DARF_RC7_V1_8821C(x)                                           \
+	(((x) >> BIT_SHIFT_DARF_RC7_V1_8821C) & BIT_MASK_DARF_RC7_V1_8821C)
+#define BIT_SET_DARF_RC7_V1_8821C(x, v)                                        \
+	(BIT_CLEAR_DARF_RC7_V1_8821C(x) | BIT_DARF_RC7_V1_8821C(v))
+
+#define BIT_SHIFT_DARF_RC6_V1_8821C 8
+#define BIT_MASK_DARF_RC6_V1_8821C 0x1f
+#define BIT_DARF_RC6_V1_8821C(x)                                               \
+	(((x) & BIT_MASK_DARF_RC6_V1_8821C) << BIT_SHIFT_DARF_RC6_V1_8821C)
+#define BITS_DARF_RC6_V1_8821C                                                 \
+	(BIT_MASK_DARF_RC6_V1_8821C << BIT_SHIFT_DARF_RC6_V1_8821C)
+#define BIT_CLEAR_DARF_RC6_V1_8821C(x) ((x) & (~BITS_DARF_RC6_V1_8821C))
+#define BIT_GET_DARF_RC6_V1_8821C(x)                                           \
+	(((x) >> BIT_SHIFT_DARF_RC6_V1_8821C) & BIT_MASK_DARF_RC6_V1_8821C)
+#define BIT_SET_DARF_RC6_V1_8821C(x, v)                                        \
+	(BIT_CLEAR_DARF_RC6_V1_8821C(x) | BIT_DARF_RC6_V1_8821C(v))
+
+#define BIT_SHIFT_DARF_RC5_V1_8821C 0
+#define BIT_MASK_DARF_RC5_V1_8821C 0x1f
+#define BIT_DARF_RC5_V1_8821C(x)                                               \
+	(((x) & BIT_MASK_DARF_RC5_V1_8821C) << BIT_SHIFT_DARF_RC5_V1_8821C)
+#define BITS_DARF_RC5_V1_8821C                                                 \
+	(BIT_MASK_DARF_RC5_V1_8821C << BIT_SHIFT_DARF_RC5_V1_8821C)
+#define BIT_CLEAR_DARF_RC5_V1_8821C(x) ((x) & (~BITS_DARF_RC5_V1_8821C))
+#define BIT_GET_DARF_RC5_V1_8821C(x)                                           \
+	(((x) >> BIT_SHIFT_DARF_RC5_V1_8821C) & BIT_MASK_DARF_RC5_V1_8821C)
+#define BIT_SET_DARF_RC5_V1_8821C(x, v)                                        \
+	(BIT_CLEAR_DARF_RC5_V1_8821C(x) | BIT_DARF_RC5_V1_8821C(v))
+
+/* 2 REG_RARFRC_8821C */
+
+#define BIT_SHIFT_RARF_RC4_8821C 24
+#define BIT_MASK_RARF_RC4_8821C 0x1f
+#define BIT_RARF_RC4_8821C(x)                                                  \
+	(((x) & BIT_MASK_RARF_RC4_8821C) << BIT_SHIFT_RARF_RC4_8821C)
+#define BITS_RARF_RC4_8821C                                                    \
+	(BIT_MASK_RARF_RC4_8821C << BIT_SHIFT_RARF_RC4_8821C)
+#define BIT_CLEAR_RARF_RC4_8821C(x) ((x) & (~BITS_RARF_RC4_8821C))
+#define BIT_GET_RARF_RC4_8821C(x)                                              \
+	(((x) >> BIT_SHIFT_RARF_RC4_8821C) & BIT_MASK_RARF_RC4_8821C)
+#define BIT_SET_RARF_RC4_8821C(x, v)                                           \
+	(BIT_CLEAR_RARF_RC4_8821C(x) | BIT_RARF_RC4_8821C(v))
+
+#define BIT_SHIFT_RARF_RC3_8821C 16
+#define BIT_MASK_RARF_RC3_8821C 0x1f
+#define BIT_RARF_RC3_8821C(x)                                                  \
+	(((x) & BIT_MASK_RARF_RC3_8821C) << BIT_SHIFT_RARF_RC3_8821C)
+#define BITS_RARF_RC3_8821C                                                    \
+	(BIT_MASK_RARF_RC3_8821C << BIT_SHIFT_RARF_RC3_8821C)
+#define BIT_CLEAR_RARF_RC3_8821C(x) ((x) & (~BITS_RARF_RC3_8821C))
+#define BIT_GET_RARF_RC3_8821C(x)                                              \
+	(((x) >> BIT_SHIFT_RARF_RC3_8821C) & BIT_MASK_RARF_RC3_8821C)
+#define BIT_SET_RARF_RC3_8821C(x, v)                                           \
+	(BIT_CLEAR_RARF_RC3_8821C(x) | BIT_RARF_RC3_8821C(v))
+
+#define BIT_SHIFT_RARF_RC2_8821C 8
+#define BIT_MASK_RARF_RC2_8821C 0x1f
+#define BIT_RARF_RC2_8821C(x)                                                  \
+	(((x) & BIT_MASK_RARF_RC2_8821C) << BIT_SHIFT_RARF_RC2_8821C)
+#define BITS_RARF_RC2_8821C                                                    \
+	(BIT_MASK_RARF_RC2_8821C << BIT_SHIFT_RARF_RC2_8821C)
+#define BIT_CLEAR_RARF_RC2_8821C(x) ((x) & (~BITS_RARF_RC2_8821C))
+#define BIT_GET_RARF_RC2_8821C(x)                                              \
+	(((x) >> BIT_SHIFT_RARF_RC2_8821C) & BIT_MASK_RARF_RC2_8821C)
+#define BIT_SET_RARF_RC2_8821C(x, v)                                           \
+	(BIT_CLEAR_RARF_RC2_8821C(x) | BIT_RARF_RC2_8821C(v))
+
+#define BIT_SHIFT_RARF_RC1_8821C 0
+#define BIT_MASK_RARF_RC1_8821C 0x1f
+#define BIT_RARF_RC1_8821C(x)                                                  \
+	(((x) & BIT_MASK_RARF_RC1_8821C) << BIT_SHIFT_RARF_RC1_8821C)
+#define BITS_RARF_RC1_8821C                                                    \
+	(BIT_MASK_RARF_RC1_8821C << BIT_SHIFT_RARF_RC1_8821C)
+#define BIT_CLEAR_RARF_RC1_8821C(x) ((x) & (~BITS_RARF_RC1_8821C))
+#define BIT_GET_RARF_RC1_8821C(x)                                              \
+	(((x) >> BIT_SHIFT_RARF_RC1_8821C) & BIT_MASK_RARF_RC1_8821C)
+#define BIT_SET_RARF_RC1_8821C(x, v)                                           \
+	(BIT_CLEAR_RARF_RC1_8821C(x) | BIT_RARF_RC1_8821C(v))
+
+/* 2 REG_RARFRCH_8821C */
+
+#define BIT_SHIFT_RARF_RC8_V1_8821C 24
+#define BIT_MASK_RARF_RC8_V1_8821C 0x1f
+#define BIT_RARF_RC8_V1_8821C(x)                                               \
+	(((x) & BIT_MASK_RARF_RC8_V1_8821C) << BIT_SHIFT_RARF_RC8_V1_8821C)
+#define BITS_RARF_RC8_V1_8821C                                                 \
+	(BIT_MASK_RARF_RC8_V1_8821C << BIT_SHIFT_RARF_RC8_V1_8821C)
+#define BIT_CLEAR_RARF_RC8_V1_8821C(x) ((x) & (~BITS_RARF_RC8_V1_8821C))
+#define BIT_GET_RARF_RC8_V1_8821C(x)                                           \
+	(((x) >> BIT_SHIFT_RARF_RC8_V1_8821C) & BIT_MASK_RARF_RC8_V1_8821C)
+#define BIT_SET_RARF_RC8_V1_8821C(x, v)                                        \
+	(BIT_CLEAR_RARF_RC8_V1_8821C(x) | BIT_RARF_RC8_V1_8821C(v))
+
+#define BIT_SHIFT_RARF_RC7_V1_8821C 16
+#define BIT_MASK_RARF_RC7_V1_8821C 0x1f
+#define BIT_RARF_RC7_V1_8821C(x)                                               \
+	(((x) & BIT_MASK_RARF_RC7_V1_8821C) << BIT_SHIFT_RARF_RC7_V1_8821C)
+#define BITS_RARF_RC7_V1_8821C                                                 \
+	(BIT_MASK_RARF_RC7_V1_8821C << BIT_SHIFT_RARF_RC7_V1_8821C)
+#define BIT_CLEAR_RARF_RC7_V1_8821C(x) ((x) & (~BITS_RARF_RC7_V1_8821C))
+#define BIT_GET_RARF_RC7_V1_8821C(x)                                           \
+	(((x) >> BIT_SHIFT_RARF_RC7_V1_8821C) & BIT_MASK_RARF_RC7_V1_8821C)
+#define BIT_SET_RARF_RC7_V1_8821C(x, v)                                        \
+	(BIT_CLEAR_RARF_RC7_V1_8821C(x) | BIT_RARF_RC7_V1_8821C(v))
+
+#define BIT_SHIFT_RARF_RC6_V1_8821C 8
+#define BIT_MASK_RARF_RC6_V1_8821C 0x1f
+#define BIT_RARF_RC6_V1_8821C(x)                                               \
+	(((x) & BIT_MASK_RARF_RC6_V1_8821C) << BIT_SHIFT_RARF_RC6_V1_8821C)
+#define BITS_RARF_RC6_V1_8821C                                                 \
+	(BIT_MASK_RARF_RC6_V1_8821C << BIT_SHIFT_RARF_RC6_V1_8821C)
+#define BIT_CLEAR_RARF_RC6_V1_8821C(x) ((x) & (~BITS_RARF_RC6_V1_8821C))
+#define BIT_GET_RARF_RC6_V1_8821C(x)                                           \
+	(((x) >> BIT_SHIFT_RARF_RC6_V1_8821C) & BIT_MASK_RARF_RC6_V1_8821C)
+#define BIT_SET_RARF_RC6_V1_8821C(x, v)                                        \
+	(BIT_CLEAR_RARF_RC6_V1_8821C(x) | BIT_RARF_RC6_V1_8821C(v))
+
+#define BIT_SHIFT_RARF_RC5_V1_8821C 0
+#define BIT_MASK_RARF_RC5_V1_8821C 0x1f
+#define BIT_RARF_RC5_V1_8821C(x)                                               \
+	(((x) & BIT_MASK_RARF_RC5_V1_8821C) << BIT_SHIFT_RARF_RC5_V1_8821C)
+#define BITS_RARF_RC5_V1_8821C                                                 \
+	(BIT_MASK_RARF_RC5_V1_8821C << BIT_SHIFT_RARF_RC5_V1_8821C)
+#define BIT_CLEAR_RARF_RC5_V1_8821C(x) ((x) & (~BITS_RARF_RC5_V1_8821C))
+#define BIT_GET_RARF_RC5_V1_8821C(x)                                           \
+	(((x) >> BIT_SHIFT_RARF_RC5_V1_8821C) & BIT_MASK_RARF_RC5_V1_8821C)
+#define BIT_SET_RARF_RC5_V1_8821C(x, v)                                        \
+	(BIT_CLEAR_RARF_RC5_V1_8821C(x) | BIT_RARF_RC5_V1_8821C(v))
+
+/* 2 REG_RRSR_8821C */
+
+#define BIT_SHIFT_RRSR_RSC_8821C 21
+#define BIT_MASK_RRSR_RSC_8821C 0x3
+#define BIT_RRSR_RSC_8821C(x)                                                  \
+	(((x) & BIT_MASK_RRSR_RSC_8821C) << BIT_SHIFT_RRSR_RSC_8821C)
+#define BITS_RRSR_RSC_8821C                                                    \
+	(BIT_MASK_RRSR_RSC_8821C << BIT_SHIFT_RRSR_RSC_8821C)
+#define BIT_CLEAR_RRSR_RSC_8821C(x) ((x) & (~BITS_RRSR_RSC_8821C))
+#define BIT_GET_RRSR_RSC_8821C(x)                                              \
+	(((x) >> BIT_SHIFT_RRSR_RSC_8821C) & BIT_MASK_RRSR_RSC_8821C)
+#define BIT_SET_RRSR_RSC_8821C(x, v)                                           \
+	(BIT_CLEAR_RRSR_RSC_8821C(x) | BIT_RRSR_RSC_8821C(v))
+
+#define BIT_SHIFT_RRSC_BITMAP_8821C 0
+#define BIT_MASK_RRSC_BITMAP_8821C 0xfffff
+#define BIT_RRSC_BITMAP_8821C(x)                                               \
+	(((x) & BIT_MASK_RRSC_BITMAP_8821C) << BIT_SHIFT_RRSC_BITMAP_8821C)
+#define BITS_RRSC_BITMAP_8821C                                                 \
+	(BIT_MASK_RRSC_BITMAP_8821C << BIT_SHIFT_RRSC_BITMAP_8821C)
+#define BIT_CLEAR_RRSC_BITMAP_8821C(x) ((x) & (~BITS_RRSC_BITMAP_8821C))
+#define BIT_GET_RRSC_BITMAP_8821C(x)                                           \
+	(((x) >> BIT_SHIFT_RRSC_BITMAP_8821C) & BIT_MASK_RRSC_BITMAP_8821C)
+#define BIT_SET_RRSC_BITMAP_8821C(x, v)                                        \
+	(BIT_CLEAR_RRSC_BITMAP_8821C(x) | BIT_RRSC_BITMAP_8821C(v))
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_ARFR0_8821C */
+
+#define BIT_SHIFT_ARFRL0_8821C 0
+#define BIT_MASK_ARFRL0_8821C 0xffffffffL
+#define BIT_ARFRL0_8821C(x)                                                    \
+	(((x) & BIT_MASK_ARFRL0_8821C) << BIT_SHIFT_ARFRL0_8821C)
+#define BITS_ARFRL0_8821C (BIT_MASK_ARFRL0_8821C << BIT_SHIFT_ARFRL0_8821C)
+#define BIT_CLEAR_ARFRL0_8821C(x) ((x) & (~BITS_ARFRL0_8821C))
+#define BIT_GET_ARFRL0_8821C(x)                                                \
+	(((x) >> BIT_SHIFT_ARFRL0_8821C) & BIT_MASK_ARFRL0_8821C)
+#define BIT_SET_ARFRL0_8821C(x, v)                                             \
+	(BIT_CLEAR_ARFRL0_8821C(x) | BIT_ARFRL0_8821C(v))
+
+/* 2 REG_ARFRH0_8821C */
+
+#define BIT_SHIFT_ARFRH0_8821C 0
+#define BIT_MASK_ARFRH0_8821C 0xffffffffL
+#define BIT_ARFRH0_8821C(x)                                                    \
+	(((x) & BIT_MASK_ARFRH0_8821C) << BIT_SHIFT_ARFRH0_8821C)
+#define BITS_ARFRH0_8821C (BIT_MASK_ARFRH0_8821C << BIT_SHIFT_ARFRH0_8821C)
+#define BIT_CLEAR_ARFRH0_8821C(x) ((x) & (~BITS_ARFRH0_8821C))
+#define BIT_GET_ARFRH0_8821C(x)                                                \
+	(((x) >> BIT_SHIFT_ARFRH0_8821C) & BIT_MASK_ARFRH0_8821C)
+#define BIT_SET_ARFRH0_8821C(x, v)                                             \
+	(BIT_CLEAR_ARFRH0_8821C(x) | BIT_ARFRH0_8821C(v))
+
+/* 2 REG_ARFR1_V1_8821C */
+
+#define BIT_SHIFT_ARFRL1_8821C 0
+#define BIT_MASK_ARFRL1_8821C 0xffffffffL
+#define BIT_ARFRL1_8821C(x)                                                    \
+	(((x) & BIT_MASK_ARFRL1_8821C) << BIT_SHIFT_ARFRL1_8821C)
+#define BITS_ARFRL1_8821C (BIT_MASK_ARFRL1_8821C << BIT_SHIFT_ARFRL1_8821C)
+#define BIT_CLEAR_ARFRL1_8821C(x) ((x) & (~BITS_ARFRL1_8821C))
+#define BIT_GET_ARFRL1_8821C(x)                                                \
+	(((x) >> BIT_SHIFT_ARFRL1_8821C) & BIT_MASK_ARFRL1_8821C)
+#define BIT_SET_ARFRL1_8821C(x, v)                                             \
+	(BIT_CLEAR_ARFRL1_8821C(x) | BIT_ARFRL1_8821C(v))
+
+/* 2 REG_ARFRH1_V1_8821C */
+
+#define BIT_SHIFT_ARFRH1_8821C 0
+#define BIT_MASK_ARFRH1_8821C 0xffffffffL
+#define BIT_ARFRH1_8821C(x)                                                    \
+	(((x) & BIT_MASK_ARFRH1_8821C) << BIT_SHIFT_ARFRH1_8821C)
+#define BITS_ARFRH1_8821C (BIT_MASK_ARFRH1_8821C << BIT_SHIFT_ARFRH1_8821C)
+#define BIT_CLEAR_ARFRH1_8821C(x) ((x) & (~BITS_ARFRH1_8821C))
+#define BIT_GET_ARFRH1_8821C(x)                                                \
+	(((x) >> BIT_SHIFT_ARFRH1_8821C) & BIT_MASK_ARFRH1_8821C)
+#define BIT_SET_ARFRH1_8821C(x, v)                                             \
+	(BIT_CLEAR_ARFRH1_8821C(x) | BIT_ARFRH1_8821C(v))
+
+/* 2 REG_CCK_CHECK_8821C */
+#define BIT_CHECK_CCK_EN_8821C BIT(7)
+#define BIT_EN_BCN_PKT_REL_8821C BIT(6)
+#define BIT_BCN_PORT_SEL_8821C BIT(5)
+#define BIT_MOREDATA_BYPASS_8821C BIT(4)
+#define BIT_EN_CLR_CMD_REL_BCN_PKT_8821C BIT(3)
+#define BIT_R_EN_SET_MOREDATA_8821C BIT(2)
+#define BIT__R_DIS_CLEAR_MACID_RELEASE_8821C BIT(1)
+#define BIT__R_MACID_RELEASE_EN_8821C BIT(0)
+
+/* 2 REG_AMPDU_MAX_TIME_V1_8821C */
+
+#define BIT_SHIFT_AMPDU_MAX_TIME_8821C 0
+#define BIT_MASK_AMPDU_MAX_TIME_8821C 0xff
+#define BIT_AMPDU_MAX_TIME_8821C(x)                                            \
+	(((x) & BIT_MASK_AMPDU_MAX_TIME_8821C)                                 \
+	 << BIT_SHIFT_AMPDU_MAX_TIME_8821C)
+#define BITS_AMPDU_MAX_TIME_8821C                                              \
+	(BIT_MASK_AMPDU_MAX_TIME_8821C << BIT_SHIFT_AMPDU_MAX_TIME_8821C)
+#define BIT_CLEAR_AMPDU_MAX_TIME_8821C(x) ((x) & (~BITS_AMPDU_MAX_TIME_8821C))
+#define BIT_GET_AMPDU_MAX_TIME_8821C(x)                                        \
+	(((x) >> BIT_SHIFT_AMPDU_MAX_TIME_8821C) &                             \
+	 BIT_MASK_AMPDU_MAX_TIME_8821C)
+#define BIT_SET_AMPDU_MAX_TIME_8821C(x, v)                                     \
+	(BIT_CLEAR_AMPDU_MAX_TIME_8821C(x) | BIT_AMPDU_MAX_TIME_8821C(v))
+
+/* 2 REG_BCNQ1_BDNY_V1_8821C */
+
+#define BIT_SHIFT_BCNQ1_PGBNDY_V1_8821C 0
+#define BIT_MASK_BCNQ1_PGBNDY_V1_8821C 0xfff
+#define BIT_BCNQ1_PGBNDY_V1_8821C(x)                                           \
+	(((x) & BIT_MASK_BCNQ1_PGBNDY_V1_8821C)                                \
+	 << BIT_SHIFT_BCNQ1_PGBNDY_V1_8821C)
+#define BITS_BCNQ1_PGBNDY_V1_8821C                                             \
+	(BIT_MASK_BCNQ1_PGBNDY_V1_8821C << BIT_SHIFT_BCNQ1_PGBNDY_V1_8821C)
+#define BIT_CLEAR_BCNQ1_PGBNDY_V1_8821C(x) ((x) & (~BITS_BCNQ1_PGBNDY_V1_8821C))
+#define BIT_GET_BCNQ1_PGBNDY_V1_8821C(x)                                       \
+	(((x) >> BIT_SHIFT_BCNQ1_PGBNDY_V1_8821C) &                            \
+	 BIT_MASK_BCNQ1_PGBNDY_V1_8821C)
+#define BIT_SET_BCNQ1_PGBNDY_V1_8821C(x, v)                                    \
+	(BIT_CLEAR_BCNQ1_PGBNDY_V1_8821C(x) | BIT_BCNQ1_PGBNDY_V1_8821C(v))
+
+/* 2 REG_AMPDU_MAX_LENGTH_8821C */
+
+#define BIT_SHIFT_AMPDU_MAX_LENGTH_8821C 0
+#define BIT_MASK_AMPDU_MAX_LENGTH_8821C 0xffffffffL
+#define BIT_AMPDU_MAX_LENGTH_8821C(x)                                          \
+	(((x) & BIT_MASK_AMPDU_MAX_LENGTH_8821C)                               \
+	 << BIT_SHIFT_AMPDU_MAX_LENGTH_8821C)
+#define BITS_AMPDU_MAX_LENGTH_8821C                                            \
+	(BIT_MASK_AMPDU_MAX_LENGTH_8821C << BIT_SHIFT_AMPDU_MAX_LENGTH_8821C)
+#define BIT_CLEAR_AMPDU_MAX_LENGTH_8821C(x)                                    \
+	((x) & (~BITS_AMPDU_MAX_LENGTH_8821C))
+#define BIT_GET_AMPDU_MAX_LENGTH_8821C(x)                                      \
+	(((x) >> BIT_SHIFT_AMPDU_MAX_LENGTH_8821C) &                           \
+	 BIT_MASK_AMPDU_MAX_LENGTH_8821C)
+#define BIT_SET_AMPDU_MAX_LENGTH_8821C(x, v)                                   \
+	(BIT_CLEAR_AMPDU_MAX_LENGTH_8821C(x) | BIT_AMPDU_MAX_LENGTH_8821C(v))
+
+/* 2 REG_ACQ_STOP_8821C */
+#define BIT_AC7Q_STOP_8821C BIT(7)
+#define BIT_AC6Q_STOP_8821C BIT(6)
+#define BIT_AC5Q_STOP_8821C BIT(5)
+#define BIT_AC4Q_STOP_8821C BIT(4)
+#define BIT_AC3Q_STOP_8821C BIT(3)
+#define BIT_AC2Q_STOP_8821C BIT(2)
+#define BIT_AC1Q_STOP_8821C BIT(1)
+#define BIT_AC0Q_STOP_8821C BIT(0)
+
+/* 2 REG_NDPA_RATE_8821C */
+
+#define BIT_SHIFT_R_NDPA_RATE_V1_8821C 0
+#define BIT_MASK_R_NDPA_RATE_V1_8821C 0xff
+#define BIT_R_NDPA_RATE_V1_8821C(x)                                            \
+	(((x) & BIT_MASK_R_NDPA_RATE_V1_8821C)                                 \
+	 << BIT_SHIFT_R_NDPA_RATE_V1_8821C)
+#define BITS_R_NDPA_RATE_V1_8821C                                              \
+	(BIT_MASK_R_NDPA_RATE_V1_8821C << BIT_SHIFT_R_NDPA_RATE_V1_8821C)
+#define BIT_CLEAR_R_NDPA_RATE_V1_8821C(x) ((x) & (~BITS_R_NDPA_RATE_V1_8821C))
+#define BIT_GET_R_NDPA_RATE_V1_8821C(x)                                        \
+	(((x) >> BIT_SHIFT_R_NDPA_RATE_V1_8821C) &                             \
+	 BIT_MASK_R_NDPA_RATE_V1_8821C)
+#define BIT_SET_R_NDPA_RATE_V1_8821C(x, v)                                     \
+	(BIT_CLEAR_R_NDPA_RATE_V1_8821C(x) | BIT_R_NDPA_RATE_V1_8821C(v))
+
+/* 2 REG_TX_HANG_CTRL_8821C */
+#define BIT_R_EN_GNT_BT_AWAKE_8821C BIT(3)
+#define BIT_EN_EOF_V1_8821C BIT(2)
+#define BIT_DIS_OQT_BLOCK_8821C BIT(1)
+#define BIT_SEARCH_QUEUE_EN_8821C BIT(0)
+
+/* 2 REG_NDPA_OPT_CTRL_8821C */
+#define BIT_R_DIS_MACID_RELEASE_RTY_8821C BIT(5)
+
+#define BIT_SHIFT_BW_SIGTA_8821C 3
+#define BIT_MASK_BW_SIGTA_8821C 0x3
+#define BIT_BW_SIGTA_8821C(x)                                                  \
+	(((x) & BIT_MASK_BW_SIGTA_8821C) << BIT_SHIFT_BW_SIGTA_8821C)
+#define BITS_BW_SIGTA_8821C                                                    \
+	(BIT_MASK_BW_SIGTA_8821C << BIT_SHIFT_BW_SIGTA_8821C)
+#define BIT_CLEAR_BW_SIGTA_8821C(x) ((x) & (~BITS_BW_SIGTA_8821C))
+#define BIT_GET_BW_SIGTA_8821C(x)                                              \
+	(((x) >> BIT_SHIFT_BW_SIGTA_8821C) & BIT_MASK_BW_SIGTA_8821C)
+#define BIT_SET_BW_SIGTA_8821C(x, v)                                           \
+	(BIT_CLEAR_BW_SIGTA_8821C(x) | BIT_BW_SIGTA_8821C(v))
+
+#define BIT_EN_BAR_SIGTA_8821C BIT(2)
+
+#define BIT_SHIFT_R_NDPA_BW_8821C 0
+#define BIT_MASK_R_NDPA_BW_8821C 0x3
+#define BIT_R_NDPA_BW_8821C(x)                                                 \
+	(((x) & BIT_MASK_R_NDPA_BW_8821C) << BIT_SHIFT_R_NDPA_BW_8821C)
+#define BITS_R_NDPA_BW_8821C                                                   \
+	(BIT_MASK_R_NDPA_BW_8821C << BIT_SHIFT_R_NDPA_BW_8821C)
+#define BIT_CLEAR_R_NDPA_BW_8821C(x) ((x) & (~BITS_R_NDPA_BW_8821C))
+#define BIT_GET_R_NDPA_BW_8821C(x)                                             \
+	(((x) >> BIT_SHIFT_R_NDPA_BW_8821C) & BIT_MASK_R_NDPA_BW_8821C)
+#define BIT_SET_R_NDPA_BW_8821C(x, v)                                          \
+	(BIT_CLEAR_R_NDPA_BW_8821C(x) | BIT_R_NDPA_BW_8821C(v))
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_RD_RESP_PKT_TH_8821C */
+
+#define BIT_SHIFT_RD_RESP_PKT_TH_V1_8821C 0
+#define BIT_MASK_RD_RESP_PKT_TH_V1_8821C 0x3f
+#define BIT_RD_RESP_PKT_TH_V1_8821C(x)                                         \
+	(((x) & BIT_MASK_RD_RESP_PKT_TH_V1_8821C)                              \
+	 << BIT_SHIFT_RD_RESP_PKT_TH_V1_8821C)
+#define BITS_RD_RESP_PKT_TH_V1_8821C                                           \
+	(BIT_MASK_RD_RESP_PKT_TH_V1_8821C << BIT_SHIFT_RD_RESP_PKT_TH_V1_8821C)
+#define BIT_CLEAR_RD_RESP_PKT_TH_V1_8821C(x)                                   \
+	((x) & (~BITS_RD_RESP_PKT_TH_V1_8821C))
+#define BIT_GET_RD_RESP_PKT_TH_V1_8821C(x)                                     \
+	(((x) >> BIT_SHIFT_RD_RESP_PKT_TH_V1_8821C) &                          \
+	 BIT_MASK_RD_RESP_PKT_TH_V1_8821C)
+#define BIT_SET_RD_RESP_PKT_TH_V1_8821C(x, v)                                  \
+	(BIT_CLEAR_RD_RESP_PKT_TH_V1_8821C(x) | BIT_RD_RESP_PKT_TH_V1_8821C(v))
+
+/* 2 REG_CMDQ_INFO_8821C */
+
+#define BIT_SHIFT_QUEUEMACID_CMDQ_V1_8821C 25
+#define BIT_MASK_QUEUEMACID_CMDQ_V1_8821C 0x7f
+#define BIT_QUEUEMACID_CMDQ_V1_8821C(x)                                        \
+	(((x) & BIT_MASK_QUEUEMACID_CMDQ_V1_8821C)                             \
+	 << BIT_SHIFT_QUEUEMACID_CMDQ_V1_8821C)
+#define BITS_QUEUEMACID_CMDQ_V1_8821C                                          \
+	(BIT_MASK_QUEUEMACID_CMDQ_V1_8821C                                     \
+	 << BIT_SHIFT_QUEUEMACID_CMDQ_V1_8821C)
+#define BIT_CLEAR_QUEUEMACID_CMDQ_V1_8821C(x)                                  \
+	((x) & (~BITS_QUEUEMACID_CMDQ_V1_8821C))
+#define BIT_GET_QUEUEMACID_CMDQ_V1_8821C(x)                                    \
+	(((x) >> BIT_SHIFT_QUEUEMACID_CMDQ_V1_8821C) &                         \
+	 BIT_MASK_QUEUEMACID_CMDQ_V1_8821C)
+#define BIT_SET_QUEUEMACID_CMDQ_V1_8821C(x, v)                                 \
+	(BIT_CLEAR_QUEUEMACID_CMDQ_V1_8821C(x) |                               \
+	 BIT_QUEUEMACID_CMDQ_V1_8821C(v))
+
+#define BIT_SHIFT_QUEUEAC_CMDQ_V1_8821C 23
+#define BIT_MASK_QUEUEAC_CMDQ_V1_8821C 0x3
+#define BIT_QUEUEAC_CMDQ_V1_8821C(x)                                           \
+	(((x) & BIT_MASK_QUEUEAC_CMDQ_V1_8821C)                                \
+	 << BIT_SHIFT_QUEUEAC_CMDQ_V1_8821C)
+#define BITS_QUEUEAC_CMDQ_V1_8821C                                             \
+	(BIT_MASK_QUEUEAC_CMDQ_V1_8821C << BIT_SHIFT_QUEUEAC_CMDQ_V1_8821C)
+#define BIT_CLEAR_QUEUEAC_CMDQ_V1_8821C(x) ((x) & (~BITS_QUEUEAC_CMDQ_V1_8821C))
+#define BIT_GET_QUEUEAC_CMDQ_V1_8821C(x)                                       \
+	(((x) >> BIT_SHIFT_QUEUEAC_CMDQ_V1_8821C) &                            \
+	 BIT_MASK_QUEUEAC_CMDQ_V1_8821C)
+#define BIT_SET_QUEUEAC_CMDQ_V1_8821C(x, v)                                    \
+	(BIT_CLEAR_QUEUEAC_CMDQ_V1_8821C(x) | BIT_QUEUEAC_CMDQ_V1_8821C(v))
+
+#define BIT_TIDEMPTY_CMDQ_V1_8821C BIT(22)
+
+#define BIT_SHIFT_TAIL_PKT_Q4_V2_8821C 11
+#define BIT_MASK_TAIL_PKT_Q4_V2_8821C 0x7ff
+#define BIT_TAIL_PKT_Q4_V2_8821C(x)                                            \
+	(((x) & BIT_MASK_TAIL_PKT_Q4_V2_8821C)                                 \
+	 << BIT_SHIFT_TAIL_PKT_Q4_V2_8821C)
+#define BITS_TAIL_PKT_Q4_V2_8821C                                              \
+	(BIT_MASK_TAIL_PKT_Q4_V2_8821C << BIT_SHIFT_TAIL_PKT_Q4_V2_8821C)
+#define BIT_CLEAR_TAIL_PKT_Q4_V2_8821C(x) ((x) & (~BITS_TAIL_PKT_Q4_V2_8821C))
+#define BIT_GET_TAIL_PKT_Q4_V2_8821C(x)                                        \
+	(((x) >> BIT_SHIFT_TAIL_PKT_Q4_V2_8821C) &                             \
+	 BIT_MASK_TAIL_PKT_Q4_V2_8821C)
+#define BIT_SET_TAIL_PKT_Q4_V2_8821C(x, v)                                     \
+	(BIT_CLEAR_TAIL_PKT_Q4_V2_8821C(x) | BIT_TAIL_PKT_Q4_V2_8821C(v))
+
+#define BIT_SHIFT_HEAD_PKT_CMDQ_V1_8821C 0
+#define BIT_MASK_HEAD_PKT_CMDQ_V1_8821C 0x7ff
+#define BIT_HEAD_PKT_CMDQ_V1_8821C(x)                                          \
+	(((x) & BIT_MASK_HEAD_PKT_CMDQ_V1_8821C)                               \
+	 << BIT_SHIFT_HEAD_PKT_CMDQ_V1_8821C)
+#define BITS_HEAD_PKT_CMDQ_V1_8821C                                            \
+	(BIT_MASK_HEAD_PKT_CMDQ_V1_8821C << BIT_SHIFT_HEAD_PKT_CMDQ_V1_8821C)
+#define BIT_CLEAR_HEAD_PKT_CMDQ_V1_8821C(x)                                    \
+	((x) & (~BITS_HEAD_PKT_CMDQ_V1_8821C))
+#define BIT_GET_HEAD_PKT_CMDQ_V1_8821C(x)                                      \
+	(((x) >> BIT_SHIFT_HEAD_PKT_CMDQ_V1_8821C) &                           \
+	 BIT_MASK_HEAD_PKT_CMDQ_V1_8821C)
+#define BIT_SET_HEAD_PKT_CMDQ_V1_8821C(x, v)                                   \
+	(BIT_CLEAR_HEAD_PKT_CMDQ_V1_8821C(x) | BIT_HEAD_PKT_CMDQ_V1_8821C(v))
+
+/* 2 REG_Q4_INFO_8821C */
+
+#define BIT_SHIFT_QUEUEMACID_Q4_V1_8821C 25
+#define BIT_MASK_QUEUEMACID_Q4_V1_8821C 0x7f
+#define BIT_QUEUEMACID_Q4_V1_8821C(x)                                          \
+	(((x) & BIT_MASK_QUEUEMACID_Q4_V1_8821C)                               \
+	 << BIT_SHIFT_QUEUEMACID_Q4_V1_8821C)
+#define BITS_QUEUEMACID_Q4_V1_8821C                                            \
+	(BIT_MASK_QUEUEMACID_Q4_V1_8821C << BIT_SHIFT_QUEUEMACID_Q4_V1_8821C)
+#define BIT_CLEAR_QUEUEMACID_Q4_V1_8821C(x)                                    \
+	((x) & (~BITS_QUEUEMACID_Q4_V1_8821C))
+#define BIT_GET_QUEUEMACID_Q4_V1_8821C(x)                                      \
+	(((x) >> BIT_SHIFT_QUEUEMACID_Q4_V1_8821C) &                           \
+	 BIT_MASK_QUEUEMACID_Q4_V1_8821C)
+#define BIT_SET_QUEUEMACID_Q4_V1_8821C(x, v)                                   \
+	(BIT_CLEAR_QUEUEMACID_Q4_V1_8821C(x) | BIT_QUEUEMACID_Q4_V1_8821C(v))
+
+#define BIT_SHIFT_QUEUEAC_Q4_V1_8821C 23
+#define BIT_MASK_QUEUEAC_Q4_V1_8821C 0x3
+#define BIT_QUEUEAC_Q4_V1_8821C(x)                                             \
+	(((x) & BIT_MASK_QUEUEAC_Q4_V1_8821C) << BIT_SHIFT_QUEUEAC_Q4_V1_8821C)
+#define BITS_QUEUEAC_Q4_V1_8821C                                               \
+	(BIT_MASK_QUEUEAC_Q4_V1_8821C << BIT_SHIFT_QUEUEAC_Q4_V1_8821C)
+#define BIT_CLEAR_QUEUEAC_Q4_V1_8821C(x) ((x) & (~BITS_QUEUEAC_Q4_V1_8821C))
+#define BIT_GET_QUEUEAC_Q4_V1_8821C(x)                                         \
+	(((x) >> BIT_SHIFT_QUEUEAC_Q4_V1_8821C) & BIT_MASK_QUEUEAC_Q4_V1_8821C)
+#define BIT_SET_QUEUEAC_Q4_V1_8821C(x, v)                                      \
+	(BIT_CLEAR_QUEUEAC_Q4_V1_8821C(x) | BIT_QUEUEAC_Q4_V1_8821C(v))
+
+#define BIT_TIDEMPTY_Q4_V1_8821C BIT(22)
+
+#define BIT_SHIFT_TAIL_PKT_Q4_V2_8821C 11
+#define BIT_MASK_TAIL_PKT_Q4_V2_8821C 0x7ff
+#define BIT_TAIL_PKT_Q4_V2_8821C(x)                                            \
+	(((x) & BIT_MASK_TAIL_PKT_Q4_V2_8821C)                                 \
+	 << BIT_SHIFT_TAIL_PKT_Q4_V2_8821C)
+#define BITS_TAIL_PKT_Q4_V2_8821C                                              \
+	(BIT_MASK_TAIL_PKT_Q4_V2_8821C << BIT_SHIFT_TAIL_PKT_Q4_V2_8821C)
+#define BIT_CLEAR_TAIL_PKT_Q4_V2_8821C(x) ((x) & (~BITS_TAIL_PKT_Q4_V2_8821C))
+#define BIT_GET_TAIL_PKT_Q4_V2_8821C(x)                                        \
+	(((x) >> BIT_SHIFT_TAIL_PKT_Q4_V2_8821C) &                             \
+	 BIT_MASK_TAIL_PKT_Q4_V2_8821C)
+#define BIT_SET_TAIL_PKT_Q4_V2_8821C(x, v)                                     \
+	(BIT_CLEAR_TAIL_PKT_Q4_V2_8821C(x) | BIT_TAIL_PKT_Q4_V2_8821C(v))
+
+#define BIT_SHIFT_HEAD_PKT_Q4_V1_8821C 0
+#define BIT_MASK_HEAD_PKT_Q4_V1_8821C 0x7ff
+#define BIT_HEAD_PKT_Q4_V1_8821C(x)                                            \
+	(((x) & BIT_MASK_HEAD_PKT_Q4_V1_8821C)                                 \
+	 << BIT_SHIFT_HEAD_PKT_Q4_V1_8821C)
+#define BITS_HEAD_PKT_Q4_V1_8821C                                              \
+	(BIT_MASK_HEAD_PKT_Q4_V1_8821C << BIT_SHIFT_HEAD_PKT_Q4_V1_8821C)
+#define BIT_CLEAR_HEAD_PKT_Q4_V1_8821C(x) ((x) & (~BITS_HEAD_PKT_Q4_V1_8821C))
+#define BIT_GET_HEAD_PKT_Q4_V1_8821C(x)                                        \
+	(((x) >> BIT_SHIFT_HEAD_PKT_Q4_V1_8821C) &                             \
+	 BIT_MASK_HEAD_PKT_Q4_V1_8821C)
+#define BIT_SET_HEAD_PKT_Q4_V1_8821C(x, v)                                     \
+	(BIT_CLEAR_HEAD_PKT_Q4_V1_8821C(x) | BIT_HEAD_PKT_Q4_V1_8821C(v))
+
+/* 2 REG_Q5_INFO_8821C */
+
+#define BIT_SHIFT_QUEUEMACID_Q5_V1_8821C 25
+#define BIT_MASK_QUEUEMACID_Q5_V1_8821C 0x7f
+#define BIT_QUEUEMACID_Q5_V1_8821C(x)                                          \
+	(((x) & BIT_MASK_QUEUEMACID_Q5_V1_8821C)                               \
+	 << BIT_SHIFT_QUEUEMACID_Q5_V1_8821C)
+#define BITS_QUEUEMACID_Q5_V1_8821C                                            \
+	(BIT_MASK_QUEUEMACID_Q5_V1_8821C << BIT_SHIFT_QUEUEMACID_Q5_V1_8821C)
+#define BIT_CLEAR_QUEUEMACID_Q5_V1_8821C(x)                                    \
+	((x) & (~BITS_QUEUEMACID_Q5_V1_8821C))
+#define BIT_GET_QUEUEMACID_Q5_V1_8821C(x)                                      \
+	(((x) >> BIT_SHIFT_QUEUEMACID_Q5_V1_8821C) &                           \
+	 BIT_MASK_QUEUEMACID_Q5_V1_8821C)
+#define BIT_SET_QUEUEMACID_Q5_V1_8821C(x, v)                                   \
+	(BIT_CLEAR_QUEUEMACID_Q5_V1_8821C(x) | BIT_QUEUEMACID_Q5_V1_8821C(v))
+
+#define BIT_SHIFT_QUEUEAC_Q5_V1_8821C 23
+#define BIT_MASK_QUEUEAC_Q5_V1_8821C 0x3
+#define BIT_QUEUEAC_Q5_V1_8821C(x)                                             \
+	(((x) & BIT_MASK_QUEUEAC_Q5_V1_8821C) << BIT_SHIFT_QUEUEAC_Q5_V1_8821C)
+#define BITS_QUEUEAC_Q5_V1_8821C                                               \
+	(BIT_MASK_QUEUEAC_Q5_V1_8821C << BIT_SHIFT_QUEUEAC_Q5_V1_8821C)
+#define BIT_CLEAR_QUEUEAC_Q5_V1_8821C(x) ((x) & (~BITS_QUEUEAC_Q5_V1_8821C))
+#define BIT_GET_QUEUEAC_Q5_V1_8821C(x)                                         \
+	(((x) >> BIT_SHIFT_QUEUEAC_Q5_V1_8821C) & BIT_MASK_QUEUEAC_Q5_V1_8821C)
+#define BIT_SET_QUEUEAC_Q5_V1_8821C(x, v)                                      \
+	(BIT_CLEAR_QUEUEAC_Q5_V1_8821C(x) | BIT_QUEUEAC_Q5_V1_8821C(v))
+
+#define BIT_TIDEMPTY_Q5_V1_8821C BIT(22)
+
+#define BIT_SHIFT_TAIL_PKT_Q5_V2_8821C 11
+#define BIT_MASK_TAIL_PKT_Q5_V2_8821C 0x7ff
+#define BIT_TAIL_PKT_Q5_V2_8821C(x)                                            \
+	(((x) & BIT_MASK_TAIL_PKT_Q5_V2_8821C)                                 \
+	 << BIT_SHIFT_TAIL_PKT_Q5_V2_8821C)
+#define BITS_TAIL_PKT_Q5_V2_8821C                                              \
+	(BIT_MASK_TAIL_PKT_Q5_V2_8821C << BIT_SHIFT_TAIL_PKT_Q5_V2_8821C)
+#define BIT_CLEAR_TAIL_PKT_Q5_V2_8821C(x) ((x) & (~BITS_TAIL_PKT_Q5_V2_8821C))
+#define BIT_GET_TAIL_PKT_Q5_V2_8821C(x)                                        \
+	(((x) >> BIT_SHIFT_TAIL_PKT_Q5_V2_8821C) &                             \
+	 BIT_MASK_TAIL_PKT_Q5_V2_8821C)
+#define BIT_SET_TAIL_PKT_Q5_V2_8821C(x, v)                                     \
+	(BIT_CLEAR_TAIL_PKT_Q5_V2_8821C(x) | BIT_TAIL_PKT_Q5_V2_8821C(v))
+
+#define BIT_SHIFT_HEAD_PKT_Q5_V1_8821C 0
+#define BIT_MASK_HEAD_PKT_Q5_V1_8821C 0x7ff
+#define BIT_HEAD_PKT_Q5_V1_8821C(x)                                            \
+	(((x) & BIT_MASK_HEAD_PKT_Q5_V1_8821C)                                 \
+	 << BIT_SHIFT_HEAD_PKT_Q5_V1_8821C)
+#define BITS_HEAD_PKT_Q5_V1_8821C                                              \
+	(BIT_MASK_HEAD_PKT_Q5_V1_8821C << BIT_SHIFT_HEAD_PKT_Q5_V1_8821C)
+#define BIT_CLEAR_HEAD_PKT_Q5_V1_8821C(x) ((x) & (~BITS_HEAD_PKT_Q5_V1_8821C))
+#define BIT_GET_HEAD_PKT_Q5_V1_8821C(x)                                        \
+	(((x) >> BIT_SHIFT_HEAD_PKT_Q5_V1_8821C) &                             \
+	 BIT_MASK_HEAD_PKT_Q5_V1_8821C)
+#define BIT_SET_HEAD_PKT_Q5_V1_8821C(x, v)                                     \
+	(BIT_CLEAR_HEAD_PKT_Q5_V1_8821C(x) | BIT_HEAD_PKT_Q5_V1_8821C(v))
+
+/* 2 REG_Q6_INFO_8821C */
+
+#define BIT_SHIFT_QUEUEMACID_Q6_V1_8821C 25
+#define BIT_MASK_QUEUEMACID_Q6_V1_8821C 0x7f
+#define BIT_QUEUEMACID_Q6_V1_8821C(x)                                          \
+	(((x) & BIT_MASK_QUEUEMACID_Q6_V1_8821C)                               \
+	 << BIT_SHIFT_QUEUEMACID_Q6_V1_8821C)
+#define BITS_QUEUEMACID_Q6_V1_8821C                                            \
+	(BIT_MASK_QUEUEMACID_Q6_V1_8821C << BIT_SHIFT_QUEUEMACID_Q6_V1_8821C)
+#define BIT_CLEAR_QUEUEMACID_Q6_V1_8821C(x)                                    \
+	((x) & (~BITS_QUEUEMACID_Q6_V1_8821C))
+#define BIT_GET_QUEUEMACID_Q6_V1_8821C(x)                                      \
+	(((x) >> BIT_SHIFT_QUEUEMACID_Q6_V1_8821C) &                           \
+	 BIT_MASK_QUEUEMACID_Q6_V1_8821C)
+#define BIT_SET_QUEUEMACID_Q6_V1_8821C(x, v)                                   \
+	(BIT_CLEAR_QUEUEMACID_Q6_V1_8821C(x) | BIT_QUEUEMACID_Q6_V1_8821C(v))
+
+#define BIT_SHIFT_QUEUEAC_Q6_V1_8821C 23
+#define BIT_MASK_QUEUEAC_Q6_V1_8821C 0x3
+#define BIT_QUEUEAC_Q6_V1_8821C(x)                                             \
+	(((x) & BIT_MASK_QUEUEAC_Q6_V1_8821C) << BIT_SHIFT_QUEUEAC_Q6_V1_8821C)
+#define BITS_QUEUEAC_Q6_V1_8821C                                               \
+	(BIT_MASK_QUEUEAC_Q6_V1_8821C << BIT_SHIFT_QUEUEAC_Q6_V1_8821C)
+#define BIT_CLEAR_QUEUEAC_Q6_V1_8821C(x) ((x) & (~BITS_QUEUEAC_Q6_V1_8821C))
+#define BIT_GET_QUEUEAC_Q6_V1_8821C(x)                                         \
+	(((x) >> BIT_SHIFT_QUEUEAC_Q6_V1_8821C) & BIT_MASK_QUEUEAC_Q6_V1_8821C)
+#define BIT_SET_QUEUEAC_Q6_V1_8821C(x, v)                                      \
+	(BIT_CLEAR_QUEUEAC_Q6_V1_8821C(x) | BIT_QUEUEAC_Q6_V1_8821C(v))
+
+#define BIT_TIDEMPTY_Q6_V1_8821C BIT(22)
+
+#define BIT_SHIFT_TAIL_PKT_Q6_V2_8821C 11
+#define BIT_MASK_TAIL_PKT_Q6_V2_8821C 0x7ff
+#define BIT_TAIL_PKT_Q6_V2_8821C(x)                                            \
+	(((x) & BIT_MASK_TAIL_PKT_Q6_V2_8821C)                                 \
+	 << BIT_SHIFT_TAIL_PKT_Q6_V2_8821C)
+#define BITS_TAIL_PKT_Q6_V2_8821C                                              \
+	(BIT_MASK_TAIL_PKT_Q6_V2_8821C << BIT_SHIFT_TAIL_PKT_Q6_V2_8821C)
+#define BIT_CLEAR_TAIL_PKT_Q6_V2_8821C(x) ((x) & (~BITS_TAIL_PKT_Q6_V2_8821C))
+#define BIT_GET_TAIL_PKT_Q6_V2_8821C(x)                                        \
+	(((x) >> BIT_SHIFT_TAIL_PKT_Q6_V2_8821C) &                             \
+	 BIT_MASK_TAIL_PKT_Q6_V2_8821C)
+#define BIT_SET_TAIL_PKT_Q6_V2_8821C(x, v)                                     \
+	(BIT_CLEAR_TAIL_PKT_Q6_V2_8821C(x) | BIT_TAIL_PKT_Q6_V2_8821C(v))
+
+#define BIT_SHIFT_HEAD_PKT_Q6_V1_8821C 0
+#define BIT_MASK_HEAD_PKT_Q6_V1_8821C 0x7ff
+#define BIT_HEAD_PKT_Q6_V1_8821C(x)                                            \
+	(((x) & BIT_MASK_HEAD_PKT_Q6_V1_8821C)                                 \
+	 << BIT_SHIFT_HEAD_PKT_Q6_V1_8821C)
+#define BITS_HEAD_PKT_Q6_V1_8821C                                              \
+	(BIT_MASK_HEAD_PKT_Q6_V1_8821C << BIT_SHIFT_HEAD_PKT_Q6_V1_8821C)
+#define BIT_CLEAR_HEAD_PKT_Q6_V1_8821C(x) ((x) & (~BITS_HEAD_PKT_Q6_V1_8821C))
+#define BIT_GET_HEAD_PKT_Q6_V1_8821C(x)                                        \
+	(((x) >> BIT_SHIFT_HEAD_PKT_Q6_V1_8821C) &                             \
+	 BIT_MASK_HEAD_PKT_Q6_V1_8821C)
+#define BIT_SET_HEAD_PKT_Q6_V1_8821C(x, v)                                     \
+	(BIT_CLEAR_HEAD_PKT_Q6_V1_8821C(x) | BIT_HEAD_PKT_Q6_V1_8821C(v))
+
+/* 2 REG_Q7_INFO_8821C */
+
+#define BIT_SHIFT_QUEUEMACID_Q7_V1_8821C 25
+#define BIT_MASK_QUEUEMACID_Q7_V1_8821C 0x7f
+#define BIT_QUEUEMACID_Q7_V1_8821C(x)                                          \
+	(((x) & BIT_MASK_QUEUEMACID_Q7_V1_8821C)                               \
+	 << BIT_SHIFT_QUEUEMACID_Q7_V1_8821C)
+#define BITS_QUEUEMACID_Q7_V1_8821C                                            \
+	(BIT_MASK_QUEUEMACID_Q7_V1_8821C << BIT_SHIFT_QUEUEMACID_Q7_V1_8821C)
+#define BIT_CLEAR_QUEUEMACID_Q7_V1_8821C(x)                                    \
+	((x) & (~BITS_QUEUEMACID_Q7_V1_8821C))
+#define BIT_GET_QUEUEMACID_Q7_V1_8821C(x)                                      \
+	(((x) >> BIT_SHIFT_QUEUEMACID_Q7_V1_8821C) &                           \
+	 BIT_MASK_QUEUEMACID_Q7_V1_8821C)
+#define BIT_SET_QUEUEMACID_Q7_V1_8821C(x, v)                                   \
+	(BIT_CLEAR_QUEUEMACID_Q7_V1_8821C(x) | BIT_QUEUEMACID_Q7_V1_8821C(v))
+
+#define BIT_SHIFT_QUEUEAC_Q7_V1_8821C 23
+#define BIT_MASK_QUEUEAC_Q7_V1_8821C 0x3
+#define BIT_QUEUEAC_Q7_V1_8821C(x)                                             \
+	(((x) & BIT_MASK_QUEUEAC_Q7_V1_8821C) << BIT_SHIFT_QUEUEAC_Q7_V1_8821C)
+#define BITS_QUEUEAC_Q7_V1_8821C                                               \
+	(BIT_MASK_QUEUEAC_Q7_V1_8821C << BIT_SHIFT_QUEUEAC_Q7_V1_8821C)
+#define BIT_CLEAR_QUEUEAC_Q7_V1_8821C(x) ((x) & (~BITS_QUEUEAC_Q7_V1_8821C))
+#define BIT_GET_QUEUEAC_Q7_V1_8821C(x)                                         \
+	(((x) >> BIT_SHIFT_QUEUEAC_Q7_V1_8821C) & BIT_MASK_QUEUEAC_Q7_V1_8821C)
+#define BIT_SET_QUEUEAC_Q7_V1_8821C(x, v)                                      \
+	(BIT_CLEAR_QUEUEAC_Q7_V1_8821C(x) | BIT_QUEUEAC_Q7_V1_8821C(v))
+
+#define BIT_TIDEMPTY_Q7_V1_8821C BIT(22)
+
+#define BIT_SHIFT_TAIL_PKT_Q7_V2_8821C 11
+#define BIT_MASK_TAIL_PKT_Q7_V2_8821C 0x7ff
+#define BIT_TAIL_PKT_Q7_V2_8821C(x)                                            \
+	(((x) & BIT_MASK_TAIL_PKT_Q7_V2_8821C)                                 \
+	 << BIT_SHIFT_TAIL_PKT_Q7_V2_8821C)
+#define BITS_TAIL_PKT_Q7_V2_8821C                                              \
+	(BIT_MASK_TAIL_PKT_Q7_V2_8821C << BIT_SHIFT_TAIL_PKT_Q7_V2_8821C)
+#define BIT_CLEAR_TAIL_PKT_Q7_V2_8821C(x) ((x) & (~BITS_TAIL_PKT_Q7_V2_8821C))
+#define BIT_GET_TAIL_PKT_Q7_V2_8821C(x)                                        \
+	(((x) >> BIT_SHIFT_TAIL_PKT_Q7_V2_8821C) &                             \
+	 BIT_MASK_TAIL_PKT_Q7_V2_8821C)
+#define BIT_SET_TAIL_PKT_Q7_V2_8821C(x, v)                                     \
+	(BIT_CLEAR_TAIL_PKT_Q7_V2_8821C(x) | BIT_TAIL_PKT_Q7_V2_8821C(v))
+
+#define BIT_SHIFT_HEAD_PKT_Q7_V1_8821C 0
+#define BIT_MASK_HEAD_PKT_Q7_V1_8821C 0x7ff
+#define BIT_HEAD_PKT_Q7_V1_8821C(x)                                            \
+	(((x) & BIT_MASK_HEAD_PKT_Q7_V1_8821C)                                 \
+	 << BIT_SHIFT_HEAD_PKT_Q7_V1_8821C)
+#define BITS_HEAD_PKT_Q7_V1_8821C                                              \
+	(BIT_MASK_HEAD_PKT_Q7_V1_8821C << BIT_SHIFT_HEAD_PKT_Q7_V1_8821C)
+#define BIT_CLEAR_HEAD_PKT_Q7_V1_8821C(x) ((x) & (~BITS_HEAD_PKT_Q7_V1_8821C))
+#define BIT_GET_HEAD_PKT_Q7_V1_8821C(x)                                        \
+	(((x) >> BIT_SHIFT_HEAD_PKT_Q7_V1_8821C) &                             \
+	 BIT_MASK_HEAD_PKT_Q7_V1_8821C)
+#define BIT_SET_HEAD_PKT_Q7_V1_8821C(x, v)                                     \
+	(BIT_CLEAR_HEAD_PKT_Q7_V1_8821C(x) | BIT_HEAD_PKT_Q7_V1_8821C(v))
+
+/* 2 REG_WMAC_LBK_BUF_HD_V1_8821C */
+
+#define BIT_SHIFT_WMAC_LBK_BUF_HEAD_V1_8821C 0
+#define BIT_MASK_WMAC_LBK_BUF_HEAD_V1_8821C 0xfff
+#define BIT_WMAC_LBK_BUF_HEAD_V1_8821C(x)                                      \
+	(((x) & BIT_MASK_WMAC_LBK_BUF_HEAD_V1_8821C)                           \
+	 << BIT_SHIFT_WMAC_LBK_BUF_HEAD_V1_8821C)
+#define BITS_WMAC_LBK_BUF_HEAD_V1_8821C                                        \
+	(BIT_MASK_WMAC_LBK_BUF_HEAD_V1_8821C                                   \
+	 << BIT_SHIFT_WMAC_LBK_BUF_HEAD_V1_8821C)
+#define BIT_CLEAR_WMAC_LBK_BUF_HEAD_V1_8821C(x)                                \
+	((x) & (~BITS_WMAC_LBK_BUF_HEAD_V1_8821C))
+#define BIT_GET_WMAC_LBK_BUF_HEAD_V1_8821C(x)                                  \
+	(((x) >> BIT_SHIFT_WMAC_LBK_BUF_HEAD_V1_8821C) &                       \
+	 BIT_MASK_WMAC_LBK_BUF_HEAD_V1_8821C)
+#define BIT_SET_WMAC_LBK_BUF_HEAD_V1_8821C(x, v)                               \
+	(BIT_CLEAR_WMAC_LBK_BUF_HEAD_V1_8821C(x) |                             \
+	 BIT_WMAC_LBK_BUF_HEAD_V1_8821C(v))
+
+/* 2 REG_MGQ_BDNY_V1_8821C */
+
+#define BIT_SHIFT_MGQ_PGBNDY_V1_8821C 0
+#define BIT_MASK_MGQ_PGBNDY_V1_8821C 0xfff
+#define BIT_MGQ_PGBNDY_V1_8821C(x)                                             \
+	(((x) & BIT_MASK_MGQ_PGBNDY_V1_8821C) << BIT_SHIFT_MGQ_PGBNDY_V1_8821C)
+#define BITS_MGQ_PGBNDY_V1_8821C                                               \
+	(BIT_MASK_MGQ_PGBNDY_V1_8821C << BIT_SHIFT_MGQ_PGBNDY_V1_8821C)
+#define BIT_CLEAR_MGQ_PGBNDY_V1_8821C(x) ((x) & (~BITS_MGQ_PGBNDY_V1_8821C))
+#define BIT_GET_MGQ_PGBNDY_V1_8821C(x)                                         \
+	(((x) >> BIT_SHIFT_MGQ_PGBNDY_V1_8821C) & BIT_MASK_MGQ_PGBNDY_V1_8821C)
+#define BIT_SET_MGQ_PGBNDY_V1_8821C(x, v)                                      \
+	(BIT_CLEAR_MGQ_PGBNDY_V1_8821C(x) | BIT_MGQ_PGBNDY_V1_8821C(v))
+
+/* 2 REG_TXRPT_CTRL_8821C */
+
+#define BIT_SHIFT_TRXRPT_TIMER_TH_8821C 24
+#define BIT_MASK_TRXRPT_TIMER_TH_8821C 0xff
+#define BIT_TRXRPT_TIMER_TH_8821C(x)                                           \
+	(((x) & BIT_MASK_TRXRPT_TIMER_TH_8821C)                                \
+	 << BIT_SHIFT_TRXRPT_TIMER_TH_8821C)
+#define BITS_TRXRPT_TIMER_TH_8821C                                             \
+	(BIT_MASK_TRXRPT_TIMER_TH_8821C << BIT_SHIFT_TRXRPT_TIMER_TH_8821C)
+#define BIT_CLEAR_TRXRPT_TIMER_TH_8821C(x) ((x) & (~BITS_TRXRPT_TIMER_TH_8821C))
+#define BIT_GET_TRXRPT_TIMER_TH_8821C(x)                                       \
+	(((x) >> BIT_SHIFT_TRXRPT_TIMER_TH_8821C) &                            \
+	 BIT_MASK_TRXRPT_TIMER_TH_8821C)
+#define BIT_SET_TRXRPT_TIMER_TH_8821C(x, v)                                    \
+	(BIT_CLEAR_TRXRPT_TIMER_TH_8821C(x) | BIT_TRXRPT_TIMER_TH_8821C(v))
+
+#define BIT_SHIFT_TRXRPT_LEN_TH_8821C 16
+#define BIT_MASK_TRXRPT_LEN_TH_8821C 0xff
+#define BIT_TRXRPT_LEN_TH_8821C(x)                                             \
+	(((x) & BIT_MASK_TRXRPT_LEN_TH_8821C) << BIT_SHIFT_TRXRPT_LEN_TH_8821C)
+#define BITS_TRXRPT_LEN_TH_8821C                                               \
+	(BIT_MASK_TRXRPT_LEN_TH_8821C << BIT_SHIFT_TRXRPT_LEN_TH_8821C)
+#define BIT_CLEAR_TRXRPT_LEN_TH_8821C(x) ((x) & (~BITS_TRXRPT_LEN_TH_8821C))
+#define BIT_GET_TRXRPT_LEN_TH_8821C(x)                                         \
+	(((x) >> BIT_SHIFT_TRXRPT_LEN_TH_8821C) & BIT_MASK_TRXRPT_LEN_TH_8821C)
+#define BIT_SET_TRXRPT_LEN_TH_8821C(x, v)                                      \
+	(BIT_CLEAR_TRXRPT_LEN_TH_8821C(x) | BIT_TRXRPT_LEN_TH_8821C(v))
+
+#define BIT_SHIFT_TRXRPT_READ_PTR_8821C 8
+#define BIT_MASK_TRXRPT_READ_PTR_8821C 0xff
+#define BIT_TRXRPT_READ_PTR_8821C(x)                                           \
+	(((x) & BIT_MASK_TRXRPT_READ_PTR_8821C)                                \
+	 << BIT_SHIFT_TRXRPT_READ_PTR_8821C)
+#define BITS_TRXRPT_READ_PTR_8821C                                             \
+	(BIT_MASK_TRXRPT_READ_PTR_8821C << BIT_SHIFT_TRXRPT_READ_PTR_8821C)
+#define BIT_CLEAR_TRXRPT_READ_PTR_8821C(x) ((x) & (~BITS_TRXRPT_READ_PTR_8821C))
+#define BIT_GET_TRXRPT_READ_PTR_8821C(x)                                       \
+	(((x) >> BIT_SHIFT_TRXRPT_READ_PTR_8821C) &                            \
+	 BIT_MASK_TRXRPT_READ_PTR_8821C)
+#define BIT_SET_TRXRPT_READ_PTR_8821C(x, v)                                    \
+	(BIT_CLEAR_TRXRPT_READ_PTR_8821C(x) | BIT_TRXRPT_READ_PTR_8821C(v))
+
+#define BIT_SHIFT_TRXRPT_WRITE_PTR_8821C 0
+#define BIT_MASK_TRXRPT_WRITE_PTR_8821C 0xff
+#define BIT_TRXRPT_WRITE_PTR_8821C(x)                                          \
+	(((x) & BIT_MASK_TRXRPT_WRITE_PTR_8821C)                               \
+	 << BIT_SHIFT_TRXRPT_WRITE_PTR_8821C)
+#define BITS_TRXRPT_WRITE_PTR_8821C                                            \
+	(BIT_MASK_TRXRPT_WRITE_PTR_8821C << BIT_SHIFT_TRXRPT_WRITE_PTR_8821C)
+#define BIT_CLEAR_TRXRPT_WRITE_PTR_8821C(x)                                    \
+	((x) & (~BITS_TRXRPT_WRITE_PTR_8821C))
+#define BIT_GET_TRXRPT_WRITE_PTR_8821C(x)                                      \
+	(((x) >> BIT_SHIFT_TRXRPT_WRITE_PTR_8821C) &                           \
+	 BIT_MASK_TRXRPT_WRITE_PTR_8821C)
+#define BIT_SET_TRXRPT_WRITE_PTR_8821C(x, v)                                   \
+	(BIT_CLEAR_TRXRPT_WRITE_PTR_8821C(x) | BIT_TRXRPT_WRITE_PTR_8821C(v))
+
+/* 2 REG_INIRTS_RATE_SEL_8821C */
+#define BIT_LEAG_RTS_BW_DUP_8821C BIT(5)
+
+/* 2 REG_BASIC_CFEND_RATE_8821C */
+
+#define BIT_SHIFT_BASIC_CFEND_RATE_8821C 0
+#define BIT_MASK_BASIC_CFEND_RATE_8821C 0x1f
+#define BIT_BASIC_CFEND_RATE_8821C(x)                                          \
+	(((x) & BIT_MASK_BASIC_CFEND_RATE_8821C)                               \
+	 << BIT_SHIFT_BASIC_CFEND_RATE_8821C)
+#define BITS_BASIC_CFEND_RATE_8821C                                            \
+	(BIT_MASK_BASIC_CFEND_RATE_8821C << BIT_SHIFT_BASIC_CFEND_RATE_8821C)
+#define BIT_CLEAR_BASIC_CFEND_RATE_8821C(x)                                    \
+	((x) & (~BITS_BASIC_CFEND_RATE_8821C))
+#define BIT_GET_BASIC_CFEND_RATE_8821C(x)                                      \
+	(((x) >> BIT_SHIFT_BASIC_CFEND_RATE_8821C) &                           \
+	 BIT_MASK_BASIC_CFEND_RATE_8821C)
+#define BIT_SET_BASIC_CFEND_RATE_8821C(x, v)                                   \
+	(BIT_CLEAR_BASIC_CFEND_RATE_8821C(x) | BIT_BASIC_CFEND_RATE_8821C(v))
+
+/* 2 REG_STBC_CFEND_RATE_8821C */
+
+#define BIT_SHIFT_STBC_CFEND_RATE_8821C 0
+#define BIT_MASK_STBC_CFEND_RATE_8821C 0x1f
+#define BIT_STBC_CFEND_RATE_8821C(x)                                           \
+	(((x) & BIT_MASK_STBC_CFEND_RATE_8821C)                                \
+	 << BIT_SHIFT_STBC_CFEND_RATE_8821C)
+#define BITS_STBC_CFEND_RATE_8821C                                             \
+	(BIT_MASK_STBC_CFEND_RATE_8821C << BIT_SHIFT_STBC_CFEND_RATE_8821C)
+#define BIT_CLEAR_STBC_CFEND_RATE_8821C(x) ((x) & (~BITS_STBC_CFEND_RATE_8821C))
+#define BIT_GET_STBC_CFEND_RATE_8821C(x)                                       \
+	(((x) >> BIT_SHIFT_STBC_CFEND_RATE_8821C) &                            \
+	 BIT_MASK_STBC_CFEND_RATE_8821C)
+#define BIT_SET_STBC_CFEND_RATE_8821C(x, v)                                    \
+	(BIT_CLEAR_STBC_CFEND_RATE_8821C(x) | BIT_STBC_CFEND_RATE_8821C(v))
+
+/* 2 REG_DATA_SC_8821C */
+
+#define BIT_SHIFT_TXSC_40M_8821C 4
+#define BIT_MASK_TXSC_40M_8821C 0xf
+#define BIT_TXSC_40M_8821C(x)                                                  \
+	(((x) & BIT_MASK_TXSC_40M_8821C) << BIT_SHIFT_TXSC_40M_8821C)
+#define BITS_TXSC_40M_8821C                                                    \
+	(BIT_MASK_TXSC_40M_8821C << BIT_SHIFT_TXSC_40M_8821C)
+#define BIT_CLEAR_TXSC_40M_8821C(x) ((x) & (~BITS_TXSC_40M_8821C))
+#define BIT_GET_TXSC_40M_8821C(x)                                              \
+	(((x) >> BIT_SHIFT_TXSC_40M_8821C) & BIT_MASK_TXSC_40M_8821C)
+#define BIT_SET_TXSC_40M_8821C(x, v)                                           \
+	(BIT_CLEAR_TXSC_40M_8821C(x) | BIT_TXSC_40M_8821C(v))
+
+#define BIT_SHIFT_TXSC_20M_8821C 0
+#define BIT_MASK_TXSC_20M_8821C 0xf
+#define BIT_TXSC_20M_8821C(x)                                                  \
+	(((x) & BIT_MASK_TXSC_20M_8821C) << BIT_SHIFT_TXSC_20M_8821C)
+#define BITS_TXSC_20M_8821C                                                    \
+	(BIT_MASK_TXSC_20M_8821C << BIT_SHIFT_TXSC_20M_8821C)
+#define BIT_CLEAR_TXSC_20M_8821C(x) ((x) & (~BITS_TXSC_20M_8821C))
+#define BIT_GET_TXSC_20M_8821C(x)                                              \
+	(((x) >> BIT_SHIFT_TXSC_20M_8821C) & BIT_MASK_TXSC_20M_8821C)
+#define BIT_SET_TXSC_20M_8821C(x, v)                                           \
+	(BIT_CLEAR_TXSC_20M_8821C(x) | BIT_TXSC_20M_8821C(v))
+
+/* 2 REG_MACID_SLEEP3_8821C */
+
+#define BIT_SHIFT_MACID127_96_PKTSLEEP_8821C 0
+#define BIT_MASK_MACID127_96_PKTSLEEP_8821C 0xffffffffL
+#define BIT_MACID127_96_PKTSLEEP_8821C(x)                                      \
+	(((x) & BIT_MASK_MACID127_96_PKTSLEEP_8821C)                           \
+	 << BIT_SHIFT_MACID127_96_PKTSLEEP_8821C)
+#define BITS_MACID127_96_PKTSLEEP_8821C                                        \
+	(BIT_MASK_MACID127_96_PKTSLEEP_8821C                                   \
+	 << BIT_SHIFT_MACID127_96_PKTSLEEP_8821C)
+#define BIT_CLEAR_MACID127_96_PKTSLEEP_8821C(x)                                \
+	((x) & (~BITS_MACID127_96_PKTSLEEP_8821C))
+#define BIT_GET_MACID127_96_PKTSLEEP_8821C(x)                                  \
+	(((x) >> BIT_SHIFT_MACID127_96_PKTSLEEP_8821C) &                       \
+	 BIT_MASK_MACID127_96_PKTSLEEP_8821C)
+#define BIT_SET_MACID127_96_PKTSLEEP_8821C(x, v)                               \
+	(BIT_CLEAR_MACID127_96_PKTSLEEP_8821C(x) |                             \
+	 BIT_MACID127_96_PKTSLEEP_8821C(v))
+
+/* 2 REG_MACID_SLEEP1_8821C */
+
+#define BIT_SHIFT_MACID63_32_PKTSLEEP_8821C 0
+#define BIT_MASK_MACID63_32_PKTSLEEP_8821C 0xffffffffL
+#define BIT_MACID63_32_PKTSLEEP_8821C(x)                                       \
+	(((x) & BIT_MASK_MACID63_32_PKTSLEEP_8821C)                            \
+	 << BIT_SHIFT_MACID63_32_PKTSLEEP_8821C)
+#define BITS_MACID63_32_PKTSLEEP_8821C                                         \
+	(BIT_MASK_MACID63_32_PKTSLEEP_8821C                                    \
+	 << BIT_SHIFT_MACID63_32_PKTSLEEP_8821C)
+#define BIT_CLEAR_MACID63_32_PKTSLEEP_8821C(x)                                 \
+	((x) & (~BITS_MACID63_32_PKTSLEEP_8821C))
+#define BIT_GET_MACID63_32_PKTSLEEP_8821C(x)                                   \
+	(((x) >> BIT_SHIFT_MACID63_32_PKTSLEEP_8821C) &                        \
+	 BIT_MASK_MACID63_32_PKTSLEEP_8821C)
+#define BIT_SET_MACID63_32_PKTSLEEP_8821C(x, v)                                \
+	(BIT_CLEAR_MACID63_32_PKTSLEEP_8821C(x) |                              \
+	 BIT_MACID63_32_PKTSLEEP_8821C(v))
+
+/* 2 REG_ARFR2_V1_8821C */
+
+#define BIT_SHIFT_ARFRL2_8821C 0
+#define BIT_MASK_ARFRL2_8821C 0xffffffffL
+#define BIT_ARFRL2_8821C(x)                                                    \
+	(((x) & BIT_MASK_ARFRL2_8821C) << BIT_SHIFT_ARFRL2_8821C)
+#define BITS_ARFRL2_8821C (BIT_MASK_ARFRL2_8821C << BIT_SHIFT_ARFRL2_8821C)
+#define BIT_CLEAR_ARFRL2_8821C(x) ((x) & (~BITS_ARFRL2_8821C))
+#define BIT_GET_ARFRL2_8821C(x)                                                \
+	(((x) >> BIT_SHIFT_ARFRL2_8821C) & BIT_MASK_ARFRL2_8821C)
+#define BIT_SET_ARFRL2_8821C(x, v)                                             \
+	(BIT_CLEAR_ARFRL2_8821C(x) | BIT_ARFRL2_8821C(v))
+
+/* 2 REG_ARFRH2_V1_8821C */
+
+#define BIT_SHIFT_ARFRH2_8821C 0
+#define BIT_MASK_ARFRH2_8821C 0xffffffffL
+#define BIT_ARFRH2_8821C(x)                                                    \
+	(((x) & BIT_MASK_ARFRH2_8821C) << BIT_SHIFT_ARFRH2_8821C)
+#define BITS_ARFRH2_8821C (BIT_MASK_ARFRH2_8821C << BIT_SHIFT_ARFRH2_8821C)
+#define BIT_CLEAR_ARFRH2_8821C(x) ((x) & (~BITS_ARFRH2_8821C))
+#define BIT_GET_ARFRH2_8821C(x)                                                \
+	(((x) >> BIT_SHIFT_ARFRH2_8821C) & BIT_MASK_ARFRH2_8821C)
+#define BIT_SET_ARFRH2_8821C(x, v)                                             \
+	(BIT_CLEAR_ARFRH2_8821C(x) | BIT_ARFRH2_8821C(v))
+
+/* 2 REG_ARFR3_V1_8821C */
+
+#define BIT_SHIFT_ARFRL3_8821C 0
+#define BIT_MASK_ARFRL3_8821C 0xffffffffL
+#define BIT_ARFRL3_8821C(x)                                                    \
+	(((x) & BIT_MASK_ARFRL3_8821C) << BIT_SHIFT_ARFRL3_8821C)
+#define BITS_ARFRL3_8821C (BIT_MASK_ARFRL3_8821C << BIT_SHIFT_ARFRL3_8821C)
+#define BIT_CLEAR_ARFRL3_8821C(x) ((x) & (~BITS_ARFRL3_8821C))
+#define BIT_GET_ARFRL3_8821C(x)                                                \
+	(((x) >> BIT_SHIFT_ARFRL3_8821C) & BIT_MASK_ARFRL3_8821C)
+#define BIT_SET_ARFRL3_8821C(x, v)                                             \
+	(BIT_CLEAR_ARFRL3_8821C(x) | BIT_ARFRL3_8821C(v))
+
+/* 2 REG_ARFRH3_V1_8821C */
+
+#define BIT_SHIFT_ARFRH3_8821C 0
+#define BIT_MASK_ARFRH3_8821C 0xffffffffL
+#define BIT_ARFRH3_8821C(x)                                                    \
+	(((x) & BIT_MASK_ARFRH3_8821C) << BIT_SHIFT_ARFRH3_8821C)
+#define BITS_ARFRH3_8821C (BIT_MASK_ARFRH3_8821C << BIT_SHIFT_ARFRH3_8821C)
+#define BIT_CLEAR_ARFRH3_8821C(x) ((x) & (~BITS_ARFRH3_8821C))
+#define BIT_GET_ARFRH3_8821C(x)                                                \
+	(((x) >> BIT_SHIFT_ARFRH3_8821C) & BIT_MASK_ARFRH3_8821C)
+#define BIT_SET_ARFRH3_8821C(x, v)                                             \
+	(BIT_CLEAR_ARFRH3_8821C(x) | BIT_ARFRH3_8821C(v))
+
+/* 2 REG_ARFR4_8821C */
+
+#define BIT_SHIFT_ARFRL4_8821C 0
+#define BIT_MASK_ARFRL4_8821C 0xffffffffL
+#define BIT_ARFRL4_8821C(x)                                                    \
+	(((x) & BIT_MASK_ARFRL4_8821C) << BIT_SHIFT_ARFRL4_8821C)
+#define BITS_ARFRL4_8821C (BIT_MASK_ARFRL4_8821C << BIT_SHIFT_ARFRL4_8821C)
+#define BIT_CLEAR_ARFRL4_8821C(x) ((x) & (~BITS_ARFRL4_8821C))
+#define BIT_GET_ARFRL4_8821C(x)                                                \
+	(((x) >> BIT_SHIFT_ARFRL4_8821C) & BIT_MASK_ARFRL4_8821C)
+#define BIT_SET_ARFRL4_8821C(x, v)                                             \
+	(BIT_CLEAR_ARFRL4_8821C(x) | BIT_ARFRL4_8821C(v))
+
+/* 2 REG_ARFRH4_8821C */
+
+#define BIT_SHIFT_ARFRH4_8821C 0
+#define BIT_MASK_ARFRH4_8821C 0xffffffffL
+#define BIT_ARFRH4_8821C(x)                                                    \
+	(((x) & BIT_MASK_ARFRH4_8821C) << BIT_SHIFT_ARFRH4_8821C)
+#define BITS_ARFRH4_8821C (BIT_MASK_ARFRH4_8821C << BIT_SHIFT_ARFRH4_8821C)
+#define BIT_CLEAR_ARFRH4_8821C(x) ((x) & (~BITS_ARFRH4_8821C))
+#define BIT_GET_ARFRH4_8821C(x)                                                \
+	(((x) >> BIT_SHIFT_ARFRH4_8821C) & BIT_MASK_ARFRH4_8821C)
+#define BIT_SET_ARFRH4_8821C(x, v)                                             \
+	(BIT_CLEAR_ARFRH4_8821C(x) | BIT_ARFRH4_8821C(v))
+
+/* 2 REG_ARFR5_8821C */
+
+#define BIT_SHIFT_ARFRL5_8821C 0
+#define BIT_MASK_ARFRL5_8821C 0xffffffffL
+#define BIT_ARFRL5_8821C(x)                                                    \
+	(((x) & BIT_MASK_ARFRL5_8821C) << BIT_SHIFT_ARFRL5_8821C)
+#define BITS_ARFRL5_8821C (BIT_MASK_ARFRL5_8821C << BIT_SHIFT_ARFRL5_8821C)
+#define BIT_CLEAR_ARFRL5_8821C(x) ((x) & (~BITS_ARFRL5_8821C))
+#define BIT_GET_ARFRL5_8821C(x)                                                \
+	(((x) >> BIT_SHIFT_ARFRL5_8821C) & BIT_MASK_ARFRL5_8821C)
+#define BIT_SET_ARFRL5_8821C(x, v)                                             \
+	(BIT_CLEAR_ARFRL5_8821C(x) | BIT_ARFRL5_8821C(v))
+
+/* 2 REG_ARFRH5_8821C */
+
+#define BIT_SHIFT_ARFRH5_8821C 0
+#define BIT_MASK_ARFRH5_8821C 0xffffffffL
+#define BIT_ARFRH5_8821C(x)                                                    \
+	(((x) & BIT_MASK_ARFRH5_8821C) << BIT_SHIFT_ARFRH5_8821C)
+#define BITS_ARFRH5_8821C (BIT_MASK_ARFRH5_8821C << BIT_SHIFT_ARFRH5_8821C)
+#define BIT_CLEAR_ARFRH5_8821C(x) ((x) & (~BITS_ARFRH5_8821C))
+#define BIT_GET_ARFRH5_8821C(x)                                                \
+	(((x) >> BIT_SHIFT_ARFRH5_8821C) & BIT_MASK_ARFRH5_8821C)
+#define BIT_SET_ARFRH5_8821C(x, v)                                             \
+	(BIT_CLEAR_ARFRH5_8821C(x) | BIT_ARFRH5_8821C(v))
+
+/* 2 REG_TXRPT_START_OFFSET_8821C */
+
+#define BIT_SHIFT_R_MUTAB_TXRPT_OFFSET_8821C 24
+#define BIT_MASK_R_MUTAB_TXRPT_OFFSET_8821C 0xff
+#define BIT_R_MUTAB_TXRPT_OFFSET_8821C(x)                                      \
+	(((x) & BIT_MASK_R_MUTAB_TXRPT_OFFSET_8821C)                           \
+	 << BIT_SHIFT_R_MUTAB_TXRPT_OFFSET_8821C)
+#define BITS_R_MUTAB_TXRPT_OFFSET_8821C                                        \
+	(BIT_MASK_R_MUTAB_TXRPT_OFFSET_8821C                                   \
+	 << BIT_SHIFT_R_MUTAB_TXRPT_OFFSET_8821C)
+#define BIT_CLEAR_R_MUTAB_TXRPT_OFFSET_8821C(x)                                \
+	((x) & (~BITS_R_MUTAB_TXRPT_OFFSET_8821C))
+#define BIT_GET_R_MUTAB_TXRPT_OFFSET_8821C(x)                                  \
+	(((x) >> BIT_SHIFT_R_MUTAB_TXRPT_OFFSET_8821C) &                       \
+	 BIT_MASK_R_MUTAB_TXRPT_OFFSET_8821C)
+#define BIT_SET_R_MUTAB_TXRPT_OFFSET_8821C(x, v)                               \
+	(BIT_CLEAR_R_MUTAB_TXRPT_OFFSET_8821C(x) |                             \
+	 BIT_R_MUTAB_TXRPT_OFFSET_8821C(v))
+
+#define BIT__R_RPTFIFO_1K_8821C BIT(16)
+
+#define BIT_SHIFT_MACID_CTRL_OFFSET_8821C 8
+#define BIT_MASK_MACID_CTRL_OFFSET_8821C 0xff
+#define BIT_MACID_CTRL_OFFSET_8821C(x)                                         \
+	(((x) & BIT_MASK_MACID_CTRL_OFFSET_8821C)                              \
+	 << BIT_SHIFT_MACID_CTRL_OFFSET_8821C)
+#define BITS_MACID_CTRL_OFFSET_8821C                                           \
+	(BIT_MASK_MACID_CTRL_OFFSET_8821C << BIT_SHIFT_MACID_CTRL_OFFSET_8821C)
+#define BIT_CLEAR_MACID_CTRL_OFFSET_8821C(x)                                   \
+	((x) & (~BITS_MACID_CTRL_OFFSET_8821C))
+#define BIT_GET_MACID_CTRL_OFFSET_8821C(x)                                     \
+	(((x) >> BIT_SHIFT_MACID_CTRL_OFFSET_8821C) &                          \
+	 BIT_MASK_MACID_CTRL_OFFSET_8821C)
+#define BIT_SET_MACID_CTRL_OFFSET_8821C(x, v)                                  \
+	(BIT_CLEAR_MACID_CTRL_OFFSET_8821C(x) | BIT_MACID_CTRL_OFFSET_8821C(v))
+
+#define BIT_SHIFT_AMPDU_TXRPT_OFFSET_8821C 0
+#define BIT_MASK_AMPDU_TXRPT_OFFSET_8821C 0xff
+#define BIT_AMPDU_TXRPT_OFFSET_8821C(x)                                        \
+	(((x) & BIT_MASK_AMPDU_TXRPT_OFFSET_8821C)                             \
+	 << BIT_SHIFT_AMPDU_TXRPT_OFFSET_8821C)
+#define BITS_AMPDU_TXRPT_OFFSET_8821C                                          \
+	(BIT_MASK_AMPDU_TXRPT_OFFSET_8821C                                     \
+	 << BIT_SHIFT_AMPDU_TXRPT_OFFSET_8821C)
+#define BIT_CLEAR_AMPDU_TXRPT_OFFSET_8821C(x)                                  \
+	((x) & (~BITS_AMPDU_TXRPT_OFFSET_8821C))
+#define BIT_GET_AMPDU_TXRPT_OFFSET_8821C(x)                                    \
+	(((x) >> BIT_SHIFT_AMPDU_TXRPT_OFFSET_8821C) &                         \
+	 BIT_MASK_AMPDU_TXRPT_OFFSET_8821C)
+#define BIT_SET_AMPDU_TXRPT_OFFSET_8821C(x, v)                                 \
+	(BIT_CLEAR_AMPDU_TXRPT_OFFSET_8821C(x) |                               \
+	 BIT_AMPDU_TXRPT_OFFSET_8821C(v))
+
+/* 2 REG_POWER_STAGE1_8821C */
+#define BIT_PTA_WL_PRI_MASK_CPU_MGQ_8821C BIT(31)
+#define BIT_PTA_WL_PRI_MASK_BCNQ_8821C BIT(30)
+#define BIT_PTA_WL_PRI_MASK_HIQ_8821C BIT(29)
+#define BIT_PTA_WL_PRI_MASK_MGQ_8821C BIT(28)
+#define BIT_PTA_WL_PRI_MASK_BK_8821C BIT(27)
+#define BIT_PTA_WL_PRI_MASK_BE_8821C BIT(26)
+#define BIT_PTA_WL_PRI_MASK_VI_8821C BIT(25)
+#define BIT_PTA_WL_PRI_MASK_VO_8821C BIT(24)
+
+#define BIT_SHIFT_POWER_STAGE1_8821C 0
+#define BIT_MASK_POWER_STAGE1_8821C 0xffffff
+#define BIT_POWER_STAGE1_8821C(x)                                              \
+	(((x) & BIT_MASK_POWER_STAGE1_8821C) << BIT_SHIFT_POWER_STAGE1_8821C)
+#define BITS_POWER_STAGE1_8821C                                                \
+	(BIT_MASK_POWER_STAGE1_8821C << BIT_SHIFT_POWER_STAGE1_8821C)
+#define BIT_CLEAR_POWER_STAGE1_8821C(x) ((x) & (~BITS_POWER_STAGE1_8821C))
+#define BIT_GET_POWER_STAGE1_8821C(x)                                          \
+	(((x) >> BIT_SHIFT_POWER_STAGE1_8821C) & BIT_MASK_POWER_STAGE1_8821C)
+#define BIT_SET_POWER_STAGE1_8821C(x, v)                                       \
+	(BIT_CLEAR_POWER_STAGE1_8821C(x) | BIT_POWER_STAGE1_8821C(v))
+
+/* 2 REG_POWER_STAGE2_8821C */
+#define BIT__R_CTRL_PKT_POW_ADJ_8821C BIT(24)
+
+#define BIT_SHIFT_POWER_STAGE2_8821C 0
+#define BIT_MASK_POWER_STAGE2_8821C 0xffffff
+#define BIT_POWER_STAGE2_8821C(x)                                              \
+	(((x) & BIT_MASK_POWER_STAGE2_8821C) << BIT_SHIFT_POWER_STAGE2_8821C)
+#define BITS_POWER_STAGE2_8821C                                                \
+	(BIT_MASK_POWER_STAGE2_8821C << BIT_SHIFT_POWER_STAGE2_8821C)
+#define BIT_CLEAR_POWER_STAGE2_8821C(x) ((x) & (~BITS_POWER_STAGE2_8821C))
+#define BIT_GET_POWER_STAGE2_8821C(x)                                          \
+	(((x) >> BIT_SHIFT_POWER_STAGE2_8821C) & BIT_MASK_POWER_STAGE2_8821C)
+#define BIT_SET_POWER_STAGE2_8821C(x, v)                                       \
+	(BIT_CLEAR_POWER_STAGE2_8821C(x) | BIT_POWER_STAGE2_8821C(v))
+
+/* 2 REG_SW_AMPDU_BURST_MODE_CTRL_8821C */
+
+#define BIT_SHIFT_PAD_NUM_THRES_8821C 24
+#define BIT_MASK_PAD_NUM_THRES_8821C 0x3f
+#define BIT_PAD_NUM_THRES_8821C(x)                                             \
+	(((x) & BIT_MASK_PAD_NUM_THRES_8821C) << BIT_SHIFT_PAD_NUM_THRES_8821C)
+#define BITS_PAD_NUM_THRES_8821C                                               \
+	(BIT_MASK_PAD_NUM_THRES_8821C << BIT_SHIFT_PAD_NUM_THRES_8821C)
+#define BIT_CLEAR_PAD_NUM_THRES_8821C(x) ((x) & (~BITS_PAD_NUM_THRES_8821C))
+#define BIT_GET_PAD_NUM_THRES_8821C(x)                                         \
+	(((x) >> BIT_SHIFT_PAD_NUM_THRES_8821C) & BIT_MASK_PAD_NUM_THRES_8821C)
+#define BIT_SET_PAD_NUM_THRES_8821C(x, v)                                      \
+	(BIT_CLEAR_PAD_NUM_THRES_8821C(x) | BIT_PAD_NUM_THRES_8821C(v))
+
+#define BIT_R_DMA_THIS_QUEUE_BK_8821C BIT(23)
+#define BIT_R_DMA_THIS_QUEUE_BE_8821C BIT(22)
+#define BIT_R_DMA_THIS_QUEUE_VI_8821C BIT(21)
+#define BIT_R_DMA_THIS_QUEUE_VO_8821C BIT(20)
+
+#define BIT_SHIFT_R_TOTAL_LEN_TH_8821C 8
+#define BIT_MASK_R_TOTAL_LEN_TH_8821C 0xfff
+#define BIT_R_TOTAL_LEN_TH_8821C(x)                                            \
+	(((x) & BIT_MASK_R_TOTAL_LEN_TH_8821C)                                 \
+	 << BIT_SHIFT_R_TOTAL_LEN_TH_8821C)
+#define BITS_R_TOTAL_LEN_TH_8821C                                              \
+	(BIT_MASK_R_TOTAL_LEN_TH_8821C << BIT_SHIFT_R_TOTAL_LEN_TH_8821C)
+#define BIT_CLEAR_R_TOTAL_LEN_TH_8821C(x) ((x) & (~BITS_R_TOTAL_LEN_TH_8821C))
+#define BIT_GET_R_TOTAL_LEN_TH_8821C(x)                                        \
+	(((x) >> BIT_SHIFT_R_TOTAL_LEN_TH_8821C) &                             \
+	 BIT_MASK_R_TOTAL_LEN_TH_8821C)
+#define BIT_SET_R_TOTAL_LEN_TH_8821C(x, v)                                     \
+	(BIT_CLEAR_R_TOTAL_LEN_TH_8821C(x) | BIT_R_TOTAL_LEN_TH_8821C(v))
+
+#define BIT_EN_NEW_EARLY_8821C BIT(7)
+#define BIT_PRE_TX_CMD_8821C BIT(6)
+
+#define BIT_SHIFT_NUM_SCL_EN_8821C 4
+#define BIT_MASK_NUM_SCL_EN_8821C 0x3
+#define BIT_NUM_SCL_EN_8821C(x)                                                \
+	(((x) & BIT_MASK_NUM_SCL_EN_8821C) << BIT_SHIFT_NUM_SCL_EN_8821C)
+#define BITS_NUM_SCL_EN_8821C                                                  \
+	(BIT_MASK_NUM_SCL_EN_8821C << BIT_SHIFT_NUM_SCL_EN_8821C)
+#define BIT_CLEAR_NUM_SCL_EN_8821C(x) ((x) & (~BITS_NUM_SCL_EN_8821C))
+#define BIT_GET_NUM_SCL_EN_8821C(x)                                            \
+	(((x) >> BIT_SHIFT_NUM_SCL_EN_8821C) & BIT_MASK_NUM_SCL_EN_8821C)
+#define BIT_SET_NUM_SCL_EN_8821C(x, v)                                         \
+	(BIT_CLEAR_NUM_SCL_EN_8821C(x) | BIT_NUM_SCL_EN_8821C(v))
+
+#define BIT_BK_EN_8821C BIT(3)
+#define BIT_BE_EN_8821C BIT(2)
+#define BIT_VI_EN_8821C BIT(1)
+#define BIT_VO_EN_8821C BIT(0)
+
+/* 2 REG_PKT_LIFE_TIME_8821C */
+
+#define BIT_SHIFT_PKT_LIFTIME_BEBK_8821C 16
+#define BIT_MASK_PKT_LIFTIME_BEBK_8821C 0xffff
+#define BIT_PKT_LIFTIME_BEBK_8821C(x)                                          \
+	(((x) & BIT_MASK_PKT_LIFTIME_BEBK_8821C)                               \
+	 << BIT_SHIFT_PKT_LIFTIME_BEBK_8821C)
+#define BITS_PKT_LIFTIME_BEBK_8821C                                            \
+	(BIT_MASK_PKT_LIFTIME_BEBK_8821C << BIT_SHIFT_PKT_LIFTIME_BEBK_8821C)
+#define BIT_CLEAR_PKT_LIFTIME_BEBK_8821C(x)                                    \
+	((x) & (~BITS_PKT_LIFTIME_BEBK_8821C))
+#define BIT_GET_PKT_LIFTIME_BEBK_8821C(x)                                      \
+	(((x) >> BIT_SHIFT_PKT_LIFTIME_BEBK_8821C) &                           \
+	 BIT_MASK_PKT_LIFTIME_BEBK_8821C)
+#define BIT_SET_PKT_LIFTIME_BEBK_8821C(x, v)                                   \
+	(BIT_CLEAR_PKT_LIFTIME_BEBK_8821C(x) | BIT_PKT_LIFTIME_BEBK_8821C(v))
+
+#define BIT_SHIFT_PKT_LIFTIME_VOVI_8821C 0
+#define BIT_MASK_PKT_LIFTIME_VOVI_8821C 0xffff
+#define BIT_PKT_LIFTIME_VOVI_8821C(x)                                          \
+	(((x) & BIT_MASK_PKT_LIFTIME_VOVI_8821C)                               \
+	 << BIT_SHIFT_PKT_LIFTIME_VOVI_8821C)
+#define BITS_PKT_LIFTIME_VOVI_8821C                                            \
+	(BIT_MASK_PKT_LIFTIME_VOVI_8821C << BIT_SHIFT_PKT_LIFTIME_VOVI_8821C)
+#define BIT_CLEAR_PKT_LIFTIME_VOVI_8821C(x)                                    \
+	((x) & (~BITS_PKT_LIFTIME_VOVI_8821C))
+#define BIT_GET_PKT_LIFTIME_VOVI_8821C(x)                                      \
+	(((x) >> BIT_SHIFT_PKT_LIFTIME_VOVI_8821C) &                           \
+	 BIT_MASK_PKT_LIFTIME_VOVI_8821C)
+#define BIT_SET_PKT_LIFTIME_VOVI_8821C(x, v)                                   \
+	(BIT_CLEAR_PKT_LIFTIME_VOVI_8821C(x) | BIT_PKT_LIFTIME_VOVI_8821C(v))
+
+/* 2 REG_STBC_SETTING_8821C */
+
+#define BIT_SHIFT_CDEND_TXTIME_L_8821C 4
+#define BIT_MASK_CDEND_TXTIME_L_8821C 0xf
+#define BIT_CDEND_TXTIME_L_8821C(x)                                            \
+	(((x) & BIT_MASK_CDEND_TXTIME_L_8821C)                                 \
+	 << BIT_SHIFT_CDEND_TXTIME_L_8821C)
+#define BITS_CDEND_TXTIME_L_8821C                                              \
+	(BIT_MASK_CDEND_TXTIME_L_8821C << BIT_SHIFT_CDEND_TXTIME_L_8821C)
+#define BIT_CLEAR_CDEND_TXTIME_L_8821C(x) ((x) & (~BITS_CDEND_TXTIME_L_8821C))
+#define BIT_GET_CDEND_TXTIME_L_8821C(x)                                        \
+	(((x) >> BIT_SHIFT_CDEND_TXTIME_L_8821C) &                             \
+	 BIT_MASK_CDEND_TXTIME_L_8821C)
+#define BIT_SET_CDEND_TXTIME_L_8821C(x, v)                                     \
+	(BIT_CLEAR_CDEND_TXTIME_L_8821C(x) | BIT_CDEND_TXTIME_L_8821C(v))
+
+#define BIT_SHIFT_NESS_8821C 2
+#define BIT_MASK_NESS_8821C 0x3
+#define BIT_NESS_8821C(x) (((x) & BIT_MASK_NESS_8821C) << BIT_SHIFT_NESS_8821C)
+#define BITS_NESS_8821C (BIT_MASK_NESS_8821C << BIT_SHIFT_NESS_8821C)
+#define BIT_CLEAR_NESS_8821C(x) ((x) & (~BITS_NESS_8821C))
+#define BIT_GET_NESS_8821C(x)                                                  \
+	(((x) >> BIT_SHIFT_NESS_8821C) & BIT_MASK_NESS_8821C)
+#define BIT_SET_NESS_8821C(x, v) (BIT_CLEAR_NESS_8821C(x) | BIT_NESS_8821C(v))
+
+#define BIT_SHIFT_STBC_CFEND_8821C 0
+#define BIT_MASK_STBC_CFEND_8821C 0x3
+#define BIT_STBC_CFEND_8821C(x)                                                \
+	(((x) & BIT_MASK_STBC_CFEND_8821C) << BIT_SHIFT_STBC_CFEND_8821C)
+#define BITS_STBC_CFEND_8821C                                                  \
+	(BIT_MASK_STBC_CFEND_8821C << BIT_SHIFT_STBC_CFEND_8821C)
+#define BIT_CLEAR_STBC_CFEND_8821C(x) ((x) & (~BITS_STBC_CFEND_8821C))
+#define BIT_GET_STBC_CFEND_8821C(x)                                            \
+	(((x) >> BIT_SHIFT_STBC_CFEND_8821C) & BIT_MASK_STBC_CFEND_8821C)
+#define BIT_SET_STBC_CFEND_8821C(x, v)                                         \
+	(BIT_CLEAR_STBC_CFEND_8821C(x) | BIT_STBC_CFEND_8821C(v))
+
+/* 2 REG_STBC_SETTING2_8821C */
+
+#define BIT_SHIFT_CDEND_TXTIME_H_8821C 0
+#define BIT_MASK_CDEND_TXTIME_H_8821C 0x1f
+#define BIT_CDEND_TXTIME_H_8821C(x)                                            \
+	(((x) & BIT_MASK_CDEND_TXTIME_H_8821C)                                 \
+	 << BIT_SHIFT_CDEND_TXTIME_H_8821C)
+#define BITS_CDEND_TXTIME_H_8821C                                              \
+	(BIT_MASK_CDEND_TXTIME_H_8821C << BIT_SHIFT_CDEND_TXTIME_H_8821C)
+#define BIT_CLEAR_CDEND_TXTIME_H_8821C(x) ((x) & (~BITS_CDEND_TXTIME_H_8821C))
+#define BIT_GET_CDEND_TXTIME_H_8821C(x)                                        \
+	(((x) >> BIT_SHIFT_CDEND_TXTIME_H_8821C) &                             \
+	 BIT_MASK_CDEND_TXTIME_H_8821C)
+#define BIT_SET_CDEND_TXTIME_H_8821C(x, v)                                     \
+	(BIT_CLEAR_CDEND_TXTIME_H_8821C(x) | BIT_CDEND_TXTIME_H_8821C(v))
+
+/* 2 REG_QUEUE_CTRL_8821C */
+#define BIT_PTA_EDCCA_EN_8821C BIT(5)
+#define BIT_PTA_WL_TX_EN_8821C BIT(4)
+#define BIT_R_USE_DATA_BW_8821C BIT(3)
+#define BIT_TRI_PKT_INT_MODE1_8821C BIT(2)
+#define BIT_TRI_PKT_INT_MODE0_8821C BIT(1)
+#define BIT_ACQ_MODE_SEL_8821C BIT(0)
+
+/* 2 REG_SINGLE_AMPDU_CTRL_8821C */
+#define BIT_EN_SINGLE_APMDU_8821C BIT(7)
+
+/* 2 REG_PROT_MODE_CTRL_8821C */
+
+#define BIT_SHIFT_RTS_MAX_AGG_NUM_8821C 24
+#define BIT_MASK_RTS_MAX_AGG_NUM_8821C 0x3f
+#define BIT_RTS_MAX_AGG_NUM_8821C(x)                                           \
+	(((x) & BIT_MASK_RTS_MAX_AGG_NUM_8821C)                                \
+	 << BIT_SHIFT_RTS_MAX_AGG_NUM_8821C)
+#define BITS_RTS_MAX_AGG_NUM_8821C                                             \
+	(BIT_MASK_RTS_MAX_AGG_NUM_8821C << BIT_SHIFT_RTS_MAX_AGG_NUM_8821C)
+#define BIT_CLEAR_RTS_MAX_AGG_NUM_8821C(x) ((x) & (~BITS_RTS_MAX_AGG_NUM_8821C))
+#define BIT_GET_RTS_MAX_AGG_NUM_8821C(x)                                       \
+	(((x) >> BIT_SHIFT_RTS_MAX_AGG_NUM_8821C) &                            \
+	 BIT_MASK_RTS_MAX_AGG_NUM_8821C)
+#define BIT_SET_RTS_MAX_AGG_NUM_8821C(x, v)                                    \
+	(BIT_CLEAR_RTS_MAX_AGG_NUM_8821C(x) | BIT_RTS_MAX_AGG_NUM_8821C(v))
+
+#define BIT_SHIFT_MAX_AGG_NUM_8821C 16
+#define BIT_MASK_MAX_AGG_NUM_8821C 0x3f
+#define BIT_MAX_AGG_NUM_8821C(x)                                               \
+	(((x) & BIT_MASK_MAX_AGG_NUM_8821C) << BIT_SHIFT_MAX_AGG_NUM_8821C)
+#define BITS_MAX_AGG_NUM_8821C                                                 \
+	(BIT_MASK_MAX_AGG_NUM_8821C << BIT_SHIFT_MAX_AGG_NUM_8821C)
+#define BIT_CLEAR_MAX_AGG_NUM_8821C(x) ((x) & (~BITS_MAX_AGG_NUM_8821C))
+#define BIT_GET_MAX_AGG_NUM_8821C(x)                                           \
+	(((x) >> BIT_SHIFT_MAX_AGG_NUM_8821C) & BIT_MASK_MAX_AGG_NUM_8821C)
+#define BIT_SET_MAX_AGG_NUM_8821C(x, v)                                        \
+	(BIT_CLEAR_MAX_AGG_NUM_8821C(x) | BIT_MAX_AGG_NUM_8821C(v))
+
+#define BIT_SHIFT_RTS_TXTIME_TH_8821C 8
+#define BIT_MASK_RTS_TXTIME_TH_8821C 0xff
+#define BIT_RTS_TXTIME_TH_8821C(x)                                             \
+	(((x) & BIT_MASK_RTS_TXTIME_TH_8821C) << BIT_SHIFT_RTS_TXTIME_TH_8821C)
+#define BITS_RTS_TXTIME_TH_8821C                                               \
+	(BIT_MASK_RTS_TXTIME_TH_8821C << BIT_SHIFT_RTS_TXTIME_TH_8821C)
+#define BIT_CLEAR_RTS_TXTIME_TH_8821C(x) ((x) & (~BITS_RTS_TXTIME_TH_8821C))
+#define BIT_GET_RTS_TXTIME_TH_8821C(x)                                         \
+	(((x) >> BIT_SHIFT_RTS_TXTIME_TH_8821C) & BIT_MASK_RTS_TXTIME_TH_8821C)
+#define BIT_SET_RTS_TXTIME_TH_8821C(x, v)                                      \
+	(BIT_CLEAR_RTS_TXTIME_TH_8821C(x) | BIT_RTS_TXTIME_TH_8821C(v))
+
+#define BIT_SHIFT_RTS_LEN_TH_8821C 0
+#define BIT_MASK_RTS_LEN_TH_8821C 0xff
+#define BIT_RTS_LEN_TH_8821C(x)                                                \
+	(((x) & BIT_MASK_RTS_LEN_TH_8821C) << BIT_SHIFT_RTS_LEN_TH_8821C)
+#define BITS_RTS_LEN_TH_8821C                                                  \
+	(BIT_MASK_RTS_LEN_TH_8821C << BIT_SHIFT_RTS_LEN_TH_8821C)
+#define BIT_CLEAR_RTS_LEN_TH_8821C(x) ((x) & (~BITS_RTS_LEN_TH_8821C))
+#define BIT_GET_RTS_LEN_TH_8821C(x)                                            \
+	(((x) >> BIT_SHIFT_RTS_LEN_TH_8821C) & BIT_MASK_RTS_LEN_TH_8821C)
+#define BIT_SET_RTS_LEN_TH_8821C(x, v)                                         \
+	(BIT_CLEAR_RTS_LEN_TH_8821C(x) | BIT_RTS_LEN_TH_8821C(v))
+
+/* 2 REG_BAR_MODE_CTRL_8821C */
+
+#define BIT_SHIFT_BAR_RTY_LMT_8821C 16
+#define BIT_MASK_BAR_RTY_LMT_8821C 0x3
+#define BIT_BAR_RTY_LMT_8821C(x)                                               \
+	(((x) & BIT_MASK_BAR_RTY_LMT_8821C) << BIT_SHIFT_BAR_RTY_LMT_8821C)
+#define BITS_BAR_RTY_LMT_8821C                                                 \
+	(BIT_MASK_BAR_RTY_LMT_8821C << BIT_SHIFT_BAR_RTY_LMT_8821C)
+#define BIT_CLEAR_BAR_RTY_LMT_8821C(x) ((x) & (~BITS_BAR_RTY_LMT_8821C))
+#define BIT_GET_BAR_RTY_LMT_8821C(x)                                           \
+	(((x) >> BIT_SHIFT_BAR_RTY_LMT_8821C) & BIT_MASK_BAR_RTY_LMT_8821C)
+#define BIT_SET_BAR_RTY_LMT_8821C(x, v)                                        \
+	(BIT_CLEAR_BAR_RTY_LMT_8821C(x) | BIT_BAR_RTY_LMT_8821C(v))
+
+#define BIT_SHIFT_BAR_PKT_TXTIME_TH_8821C 8
+#define BIT_MASK_BAR_PKT_TXTIME_TH_8821C 0xff
+#define BIT_BAR_PKT_TXTIME_TH_8821C(x)                                         \
+	(((x) & BIT_MASK_BAR_PKT_TXTIME_TH_8821C)                              \
+	 << BIT_SHIFT_BAR_PKT_TXTIME_TH_8821C)
+#define BITS_BAR_PKT_TXTIME_TH_8821C                                           \
+	(BIT_MASK_BAR_PKT_TXTIME_TH_8821C << BIT_SHIFT_BAR_PKT_TXTIME_TH_8821C)
+#define BIT_CLEAR_BAR_PKT_TXTIME_TH_8821C(x)                                   \
+	((x) & (~BITS_BAR_PKT_TXTIME_TH_8821C))
+#define BIT_GET_BAR_PKT_TXTIME_TH_8821C(x)                                     \
+	(((x) >> BIT_SHIFT_BAR_PKT_TXTIME_TH_8821C) &                          \
+	 BIT_MASK_BAR_PKT_TXTIME_TH_8821C)
+#define BIT_SET_BAR_PKT_TXTIME_TH_8821C(x, v)                                  \
+	(BIT_CLEAR_BAR_PKT_TXTIME_TH_8821C(x) | BIT_BAR_PKT_TXTIME_TH_8821C(v))
+
+#define BIT_BAR_EN_V1_8821C BIT(6)
+
+#define BIT_SHIFT_BAR_PKTNUM_TH_V1_8821C 0
+#define BIT_MASK_BAR_PKTNUM_TH_V1_8821C 0x3f
+#define BIT_BAR_PKTNUM_TH_V1_8821C(x)                                          \
+	(((x) & BIT_MASK_BAR_PKTNUM_TH_V1_8821C)                               \
+	 << BIT_SHIFT_BAR_PKTNUM_TH_V1_8821C)
+#define BITS_BAR_PKTNUM_TH_V1_8821C                                            \
+	(BIT_MASK_BAR_PKTNUM_TH_V1_8821C << BIT_SHIFT_BAR_PKTNUM_TH_V1_8821C)
+#define BIT_CLEAR_BAR_PKTNUM_TH_V1_8821C(x)                                    \
+	((x) & (~BITS_BAR_PKTNUM_TH_V1_8821C))
+#define BIT_GET_BAR_PKTNUM_TH_V1_8821C(x)                                      \
+	(((x) >> BIT_SHIFT_BAR_PKTNUM_TH_V1_8821C) &                           \
+	 BIT_MASK_BAR_PKTNUM_TH_V1_8821C)
+#define BIT_SET_BAR_PKTNUM_TH_V1_8821C(x, v)                                   \
+	(BIT_CLEAR_BAR_PKTNUM_TH_V1_8821C(x) | BIT_BAR_PKTNUM_TH_V1_8821C(v))
+
+/* 2 REG_RA_TRY_RATE_AGG_LMT_8821C */
+
+#define BIT_SHIFT_RA_TRY_RATE_AGG_LMT_V1_8821C 0
+#define BIT_MASK_RA_TRY_RATE_AGG_LMT_V1_8821C 0x3f
+#define BIT_RA_TRY_RATE_AGG_LMT_V1_8821C(x)                                    \
+	(((x) & BIT_MASK_RA_TRY_RATE_AGG_LMT_V1_8821C)                         \
+	 << BIT_SHIFT_RA_TRY_RATE_AGG_LMT_V1_8821C)
+#define BITS_RA_TRY_RATE_AGG_LMT_V1_8821C                                      \
+	(BIT_MASK_RA_TRY_RATE_AGG_LMT_V1_8821C                                 \
+	 << BIT_SHIFT_RA_TRY_RATE_AGG_LMT_V1_8821C)
+#define BIT_CLEAR_RA_TRY_RATE_AGG_LMT_V1_8821C(x)                              \
+	((x) & (~BITS_RA_TRY_RATE_AGG_LMT_V1_8821C))
+#define BIT_GET_RA_TRY_RATE_AGG_LMT_V1_8821C(x)                                \
+	(((x) >> BIT_SHIFT_RA_TRY_RATE_AGG_LMT_V1_8821C) &                     \
+	 BIT_MASK_RA_TRY_RATE_AGG_LMT_V1_8821C)
+#define BIT_SET_RA_TRY_RATE_AGG_LMT_V1_8821C(x, v)                             \
+	(BIT_CLEAR_RA_TRY_RATE_AGG_LMT_V1_8821C(x) |                           \
+	 BIT_RA_TRY_RATE_AGG_LMT_V1_8821C(v))
+
+/* 2 REG_MACID_SLEEP2_8821C */
+
+#define BIT_SHIFT_MACID95_64PKTSLEEP_8821C 0
+#define BIT_MASK_MACID95_64PKTSLEEP_8821C 0xffffffffL
+#define BIT_MACID95_64PKTSLEEP_8821C(x)                                        \
+	(((x) & BIT_MASK_MACID95_64PKTSLEEP_8821C)                             \
+	 << BIT_SHIFT_MACID95_64PKTSLEEP_8821C)
+#define BITS_MACID95_64PKTSLEEP_8821C                                          \
+	(BIT_MASK_MACID95_64PKTSLEEP_8821C                                     \
+	 << BIT_SHIFT_MACID95_64PKTSLEEP_8821C)
+#define BIT_CLEAR_MACID95_64PKTSLEEP_8821C(x)                                  \
+	((x) & (~BITS_MACID95_64PKTSLEEP_8821C))
+#define BIT_GET_MACID95_64PKTSLEEP_8821C(x)                                    \
+	(((x) >> BIT_SHIFT_MACID95_64PKTSLEEP_8821C) &                         \
+	 BIT_MASK_MACID95_64PKTSLEEP_8821C)
+#define BIT_SET_MACID95_64PKTSLEEP_8821C(x, v)                                 \
+	(BIT_CLEAR_MACID95_64PKTSLEEP_8821C(x) |                               \
+	 BIT_MACID95_64PKTSLEEP_8821C(v))
+
+/* 2 REG_MACID_SLEEP_8821C */
+
+#define BIT_SHIFT_MACID31_0_PKTSLEEP_8821C 0
+#define BIT_MASK_MACID31_0_PKTSLEEP_8821C 0xffffffffL
+#define BIT_MACID31_0_PKTSLEEP_8821C(x)                                        \
+	(((x) & BIT_MASK_MACID31_0_PKTSLEEP_8821C)                             \
+	 << BIT_SHIFT_MACID31_0_PKTSLEEP_8821C)
+#define BITS_MACID31_0_PKTSLEEP_8821C                                          \
+	(BIT_MASK_MACID31_0_PKTSLEEP_8821C                                     \
+	 << BIT_SHIFT_MACID31_0_PKTSLEEP_8821C)
+#define BIT_CLEAR_MACID31_0_PKTSLEEP_8821C(x)                                  \
+	((x) & (~BITS_MACID31_0_PKTSLEEP_8821C))
+#define BIT_GET_MACID31_0_PKTSLEEP_8821C(x)                                    \
+	(((x) >> BIT_SHIFT_MACID31_0_PKTSLEEP_8821C) &                         \
+	 BIT_MASK_MACID31_0_PKTSLEEP_8821C)
+#define BIT_SET_MACID31_0_PKTSLEEP_8821C(x, v)                                 \
+	(BIT_CLEAR_MACID31_0_PKTSLEEP_8821C(x) |                               \
+	 BIT_MACID31_0_PKTSLEEP_8821C(v))
+
+/* 2 REG_HW_SEQ0_8821C */
+
+#define BIT_SHIFT_HW_SSN_SEQ0_8821C 0
+#define BIT_MASK_HW_SSN_SEQ0_8821C 0xfff
+#define BIT_HW_SSN_SEQ0_8821C(x)                                               \
+	(((x) & BIT_MASK_HW_SSN_SEQ0_8821C) << BIT_SHIFT_HW_SSN_SEQ0_8821C)
+#define BITS_HW_SSN_SEQ0_8821C                                                 \
+	(BIT_MASK_HW_SSN_SEQ0_8821C << BIT_SHIFT_HW_SSN_SEQ0_8821C)
+#define BIT_CLEAR_HW_SSN_SEQ0_8821C(x) ((x) & (~BITS_HW_SSN_SEQ0_8821C))
+#define BIT_GET_HW_SSN_SEQ0_8821C(x)                                           \
+	(((x) >> BIT_SHIFT_HW_SSN_SEQ0_8821C) & BIT_MASK_HW_SSN_SEQ0_8821C)
+#define BIT_SET_HW_SSN_SEQ0_8821C(x, v)                                        \
+	(BIT_CLEAR_HW_SSN_SEQ0_8821C(x) | BIT_HW_SSN_SEQ0_8821C(v))
+
+/* 2 REG_HW_SEQ1_8821C */
+
+#define BIT_SHIFT_HW_SSN_SEQ1_8821C 0
+#define BIT_MASK_HW_SSN_SEQ1_8821C 0xfff
+#define BIT_HW_SSN_SEQ1_8821C(x)                                               \
+	(((x) & BIT_MASK_HW_SSN_SEQ1_8821C) << BIT_SHIFT_HW_SSN_SEQ1_8821C)
+#define BITS_HW_SSN_SEQ1_8821C                                                 \
+	(BIT_MASK_HW_SSN_SEQ1_8821C << BIT_SHIFT_HW_SSN_SEQ1_8821C)
+#define BIT_CLEAR_HW_SSN_SEQ1_8821C(x) ((x) & (~BITS_HW_SSN_SEQ1_8821C))
+#define BIT_GET_HW_SSN_SEQ1_8821C(x)                                           \
+	(((x) >> BIT_SHIFT_HW_SSN_SEQ1_8821C) & BIT_MASK_HW_SSN_SEQ1_8821C)
+#define BIT_SET_HW_SSN_SEQ1_8821C(x, v)                                        \
+	(BIT_CLEAR_HW_SSN_SEQ1_8821C(x) | BIT_HW_SSN_SEQ1_8821C(v))
+
+/* 2 REG_HW_SEQ2_8821C */
+
+#define BIT_SHIFT_HW_SSN_SEQ2_8821C 0
+#define BIT_MASK_HW_SSN_SEQ2_8821C 0xfff
+#define BIT_HW_SSN_SEQ2_8821C(x)                                               \
+	(((x) & BIT_MASK_HW_SSN_SEQ2_8821C) << BIT_SHIFT_HW_SSN_SEQ2_8821C)
+#define BITS_HW_SSN_SEQ2_8821C                                                 \
+	(BIT_MASK_HW_SSN_SEQ2_8821C << BIT_SHIFT_HW_SSN_SEQ2_8821C)
+#define BIT_CLEAR_HW_SSN_SEQ2_8821C(x) ((x) & (~BITS_HW_SSN_SEQ2_8821C))
+#define BIT_GET_HW_SSN_SEQ2_8821C(x)                                           \
+	(((x) >> BIT_SHIFT_HW_SSN_SEQ2_8821C) & BIT_MASK_HW_SSN_SEQ2_8821C)
+#define BIT_SET_HW_SSN_SEQ2_8821C(x, v)                                        \
+	(BIT_CLEAR_HW_SSN_SEQ2_8821C(x) | BIT_HW_SSN_SEQ2_8821C(v))
+
+/* 2 REG_HW_SEQ3_8821C */
+
+#define BIT_SHIFT_CSI_HWSEQ_SEL_8821C 12
+#define BIT_MASK_CSI_HWSEQ_SEL_8821C 0x3
+#define BIT_CSI_HWSEQ_SEL_8821C(x)                                             \
+	(((x) & BIT_MASK_CSI_HWSEQ_SEL_8821C) << BIT_SHIFT_CSI_HWSEQ_SEL_8821C)
+#define BITS_CSI_HWSEQ_SEL_8821C                                               \
+	(BIT_MASK_CSI_HWSEQ_SEL_8821C << BIT_SHIFT_CSI_HWSEQ_SEL_8821C)
+#define BIT_CLEAR_CSI_HWSEQ_SEL_8821C(x) ((x) & (~BITS_CSI_HWSEQ_SEL_8821C))
+#define BIT_GET_CSI_HWSEQ_SEL_8821C(x)                                         \
+	(((x) >> BIT_SHIFT_CSI_HWSEQ_SEL_8821C) & BIT_MASK_CSI_HWSEQ_SEL_8821C)
+#define BIT_SET_CSI_HWSEQ_SEL_8821C(x, v)                                      \
+	(BIT_CLEAR_CSI_HWSEQ_SEL_8821C(x) | BIT_CSI_HWSEQ_SEL_8821C(v))
+
+#define BIT_SHIFT_HW_SSN_SEQ3_8821C 0
+#define BIT_MASK_HW_SSN_SEQ3_8821C 0xfff
+#define BIT_HW_SSN_SEQ3_8821C(x)                                               \
+	(((x) & BIT_MASK_HW_SSN_SEQ3_8821C) << BIT_SHIFT_HW_SSN_SEQ3_8821C)
+#define BITS_HW_SSN_SEQ3_8821C                                                 \
+	(BIT_MASK_HW_SSN_SEQ3_8821C << BIT_SHIFT_HW_SSN_SEQ3_8821C)
+#define BIT_CLEAR_HW_SSN_SEQ3_8821C(x) ((x) & (~BITS_HW_SSN_SEQ3_8821C))
+#define BIT_GET_HW_SSN_SEQ3_8821C(x)                                           \
+	(((x) >> BIT_SHIFT_HW_SSN_SEQ3_8821C) & BIT_MASK_HW_SSN_SEQ3_8821C)
+#define BIT_SET_HW_SSN_SEQ3_8821C(x, v)                                        \
+	(BIT_CLEAR_HW_SSN_SEQ3_8821C(x) | BIT_HW_SSN_SEQ3_8821C(v))
+
+/* 2 REG_NULL_PKT_STATUS_V1_8821C */
+
+#define BIT_SHIFT_PTCL_TOTAL_PG_V2_8821C 2
+#define BIT_MASK_PTCL_TOTAL_PG_V2_8821C 0x3fff
+#define BIT_PTCL_TOTAL_PG_V2_8821C(x)                                          \
+	(((x) & BIT_MASK_PTCL_TOTAL_PG_V2_8821C)                               \
+	 << BIT_SHIFT_PTCL_TOTAL_PG_V2_8821C)
+#define BITS_PTCL_TOTAL_PG_V2_8821C                                            \
+	(BIT_MASK_PTCL_TOTAL_PG_V2_8821C << BIT_SHIFT_PTCL_TOTAL_PG_V2_8821C)
+#define BIT_CLEAR_PTCL_TOTAL_PG_V2_8821C(x)                                    \
+	((x) & (~BITS_PTCL_TOTAL_PG_V2_8821C))
+#define BIT_GET_PTCL_TOTAL_PG_V2_8821C(x)                                      \
+	(((x) >> BIT_SHIFT_PTCL_TOTAL_PG_V2_8821C) &                           \
+	 BIT_MASK_PTCL_TOTAL_PG_V2_8821C)
+#define BIT_SET_PTCL_TOTAL_PG_V2_8821C(x, v)                                   \
+	(BIT_CLEAR_PTCL_TOTAL_PG_V2_8821C(x) | BIT_PTCL_TOTAL_PG_V2_8821C(v))
+
+#define BIT_TX_NULL_1_8821C BIT(1)
+#define BIT_TX_NULL_0_8821C BIT(0)
+
+/* 2 REG_PTCL_ERR_STATUS_8821C */
+#define BIT_PTCL_RATE_TABLE_INVALID_8821C BIT(7)
+#define BIT_FTM_T2R_ERROR_8821C BIT(6)
+#define BIT_PTCL_ERR0_8821C BIT(5)
+#define BIT_PTCL_ERR1_8821C BIT(4)
+#define BIT_PTCL_ERR2_8821C BIT(3)
+#define BIT_PTCL_ERR3_8821C BIT(2)
+#define BIT_PTCL_ERR4_8821C BIT(1)
+#define BIT_PTCL_ERR5_8821C BIT(0)
+
+/* 2 REG_NULL_PKT_STATUS_EXTEND_8821C */
+#define BIT_CLI3_TX_NULL_1_8821C BIT(7)
+#define BIT_CLI3_TX_NULL_0_8821C BIT(6)
+#define BIT_CLI2_TX_NULL_1_8821C BIT(5)
+#define BIT_CLI2_TX_NULL_0_8821C BIT(4)
+#define BIT_CLI1_TX_NULL_1_8821C BIT(3)
+#define BIT_CLI1_TX_NULL_0_8821C BIT(2)
+#define BIT_CLI0_TX_NULL_1_8821C BIT(1)
+#define BIT_CLI0_TX_NULL_0_8821C BIT(0)
+
+/* 2 REG_VIDEO_ENHANCEMENT_FUN_8821C */
+#define BIT_HIQ_DROP_8821C BIT(7)
+#define BIT_MGQ_DROP_8821C BIT(6)
+#define BIT_VIDEO_JUST_DROP_8821C BIT(1)
+#define BIT_VIDEO_ENHANCEMENT_FUN_EN_8821C BIT(0)
+
+/* 2 REG_PRECNT_CTRL_8821C */
+#define BIT_EN_PRECNT_8821C BIT(11)
+
+#define BIT_SHIFT_PRECNT_TH_8821C 0
+#define BIT_MASK_PRECNT_TH_8821C 0x7ff
+#define BIT_PRECNT_TH_8821C(x)                                                 \
+	(((x) & BIT_MASK_PRECNT_TH_8821C) << BIT_SHIFT_PRECNT_TH_8821C)
+#define BITS_PRECNT_TH_8821C                                                   \
+	(BIT_MASK_PRECNT_TH_8821C << BIT_SHIFT_PRECNT_TH_8821C)
+#define BIT_CLEAR_PRECNT_TH_8821C(x) ((x) & (~BITS_PRECNT_TH_8821C))
+#define BIT_GET_PRECNT_TH_8821C(x)                                             \
+	(((x) >> BIT_SHIFT_PRECNT_TH_8821C) & BIT_MASK_PRECNT_TH_8821C)
+#define BIT_SET_PRECNT_TH_8821C(x, v)                                          \
+	(BIT_CLEAR_PRECNT_TH_8821C(x) | BIT_PRECNT_TH_8821C(v))
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_BT_POLLUTE_PKT_CNT_8821C */
+
+#define BIT_SHIFT_BT_POLLUTE_PKT_CNT_8821C 0
+#define BIT_MASK_BT_POLLUTE_PKT_CNT_8821C 0xffff
+#define BIT_BT_POLLUTE_PKT_CNT_8821C(x)                                        \
+	(((x) & BIT_MASK_BT_POLLUTE_PKT_CNT_8821C)                             \
+	 << BIT_SHIFT_BT_POLLUTE_PKT_CNT_8821C)
+#define BITS_BT_POLLUTE_PKT_CNT_8821C                                          \
+	(BIT_MASK_BT_POLLUTE_PKT_CNT_8821C                                     \
+	 << BIT_SHIFT_BT_POLLUTE_PKT_CNT_8821C)
+#define BIT_CLEAR_BT_POLLUTE_PKT_CNT_8821C(x)                                  \
+	((x) & (~BITS_BT_POLLUTE_PKT_CNT_8821C))
+#define BIT_GET_BT_POLLUTE_PKT_CNT_8821C(x)                                    \
+	(((x) >> BIT_SHIFT_BT_POLLUTE_PKT_CNT_8821C) &                         \
+	 BIT_MASK_BT_POLLUTE_PKT_CNT_8821C)
+#define BIT_SET_BT_POLLUTE_PKT_CNT_8821C(x, v)                                 \
+	(BIT_CLEAR_BT_POLLUTE_PKT_CNT_8821C(x) |                               \
+	 BIT_BT_POLLUTE_PKT_CNT_8821C(v))
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_PTCL_DBG_8821C */
+
+#define BIT_SHIFT_PTCL_DBG_8821C 0
+#define BIT_MASK_PTCL_DBG_8821C 0xffffffffL
+#define BIT_PTCL_DBG_8821C(x)                                                  \
+	(((x) & BIT_MASK_PTCL_DBG_8821C) << BIT_SHIFT_PTCL_DBG_8821C)
+#define BITS_PTCL_DBG_8821C                                                    \
+	(BIT_MASK_PTCL_DBG_8821C << BIT_SHIFT_PTCL_DBG_8821C)
+#define BIT_CLEAR_PTCL_DBG_8821C(x) ((x) & (~BITS_PTCL_DBG_8821C))
+#define BIT_GET_PTCL_DBG_8821C(x)                                              \
+	(((x) >> BIT_SHIFT_PTCL_DBG_8821C) & BIT_MASK_PTCL_DBG_8821C)
+#define BIT_SET_PTCL_DBG_8821C(x, v)                                           \
+	(BIT_CLEAR_PTCL_DBG_8821C(x) | BIT_PTCL_DBG_8821C(v))
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_CPUMGQ_TIMER_CTRL2_8821C */
+
+#define BIT_SHIFT_TRI_HEAD_ADDR_8821C 16
+#define BIT_MASK_TRI_HEAD_ADDR_8821C 0xfff
+#define BIT_TRI_HEAD_ADDR_8821C(x)                                             \
+	(((x) & BIT_MASK_TRI_HEAD_ADDR_8821C) << BIT_SHIFT_TRI_HEAD_ADDR_8821C)
+#define BITS_TRI_HEAD_ADDR_8821C                                               \
+	(BIT_MASK_TRI_HEAD_ADDR_8821C << BIT_SHIFT_TRI_HEAD_ADDR_8821C)
+#define BIT_CLEAR_TRI_HEAD_ADDR_8821C(x) ((x) & (~BITS_TRI_HEAD_ADDR_8821C))
+#define BIT_GET_TRI_HEAD_ADDR_8821C(x)                                         \
+	(((x) >> BIT_SHIFT_TRI_HEAD_ADDR_8821C) & BIT_MASK_TRI_HEAD_ADDR_8821C)
+#define BIT_SET_TRI_HEAD_ADDR_8821C(x, v)                                      \
+	(BIT_CLEAR_TRI_HEAD_ADDR_8821C(x) | BIT_TRI_HEAD_ADDR_8821C(v))
+
+#define BIT_DROP_TH_EN_8821C BIT(8)
+
+#define BIT_SHIFT_DROP_TH_8821C 0
+#define BIT_MASK_DROP_TH_8821C 0xff
+#define BIT_DROP_TH_8821C(x)                                                   \
+	(((x) & BIT_MASK_DROP_TH_8821C) << BIT_SHIFT_DROP_TH_8821C)
+#define BITS_DROP_TH_8821C (BIT_MASK_DROP_TH_8821C << BIT_SHIFT_DROP_TH_8821C)
+#define BIT_CLEAR_DROP_TH_8821C(x) ((x) & (~BITS_DROP_TH_8821C))
+#define BIT_GET_DROP_TH_8821C(x)                                               \
+	(((x) >> BIT_SHIFT_DROP_TH_8821C) & BIT_MASK_DROP_TH_8821C)
+#define BIT_SET_DROP_TH_8821C(x, v)                                            \
+	(BIT_CLEAR_DROP_TH_8821C(x) | BIT_DROP_TH_8821C(v))
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_DUMMY_PAGE4_V1_8821C */
+
+/* 2 REG_MOREDATA_8821C */
+#define BIT_MOREDATA_CTRL2_EN_V1_8821C BIT(3)
+#define BIT_MOREDATA_CTRL1_EN_V1_8821C BIT(2)
+#define BIT_PKTIN_MOREDATA_REPLACE_ENABLE_V1_8821C BIT(0)
+
+/* 2 REG_Q0_Q1_INFO_8821C */
+#define BIT_QUEUE_MACID_AC_NOT_THE_SAME_8821C BIT(31)
+
+#define BIT_SHIFT_GTAB_ID_8821C 28
+#define BIT_MASK_GTAB_ID_8821C 0x7
+#define BIT_GTAB_ID_8821C(x)                                                   \
+	(((x) & BIT_MASK_GTAB_ID_8821C) << BIT_SHIFT_GTAB_ID_8821C)
+#define BITS_GTAB_ID_8821C (BIT_MASK_GTAB_ID_8821C << BIT_SHIFT_GTAB_ID_8821C)
+#define BIT_CLEAR_GTAB_ID_8821C(x) ((x) & (~BITS_GTAB_ID_8821C))
+#define BIT_GET_GTAB_ID_8821C(x)                                               \
+	(((x) >> BIT_SHIFT_GTAB_ID_8821C) & BIT_MASK_GTAB_ID_8821C)
+#define BIT_SET_GTAB_ID_8821C(x, v)                                            \
+	(BIT_CLEAR_GTAB_ID_8821C(x) | BIT_GTAB_ID_8821C(v))
+
+#define BIT_SHIFT_AC1_PKT_INFO_8821C 16
+#define BIT_MASK_AC1_PKT_INFO_8821C 0xfff
+#define BIT_AC1_PKT_INFO_8821C(x)                                              \
+	(((x) & BIT_MASK_AC1_PKT_INFO_8821C) << BIT_SHIFT_AC1_PKT_INFO_8821C)
+#define BITS_AC1_PKT_INFO_8821C                                                \
+	(BIT_MASK_AC1_PKT_INFO_8821C << BIT_SHIFT_AC1_PKT_INFO_8821C)
+#define BIT_CLEAR_AC1_PKT_INFO_8821C(x) ((x) & (~BITS_AC1_PKT_INFO_8821C))
+#define BIT_GET_AC1_PKT_INFO_8821C(x)                                          \
+	(((x) >> BIT_SHIFT_AC1_PKT_INFO_8821C) & BIT_MASK_AC1_PKT_INFO_8821C)
+#define BIT_SET_AC1_PKT_INFO_8821C(x, v)                                       \
+	(BIT_CLEAR_AC1_PKT_INFO_8821C(x) | BIT_AC1_PKT_INFO_8821C(v))
+
+#define BIT_QUEUE_MACID_AC_NOT_THE_SAME_V1_8821C BIT(15)
+
+#define BIT_SHIFT_GTAB_ID_V1_8821C 12
+#define BIT_MASK_GTAB_ID_V1_8821C 0x7
+#define BIT_GTAB_ID_V1_8821C(x)                                                \
+	(((x) & BIT_MASK_GTAB_ID_V1_8821C) << BIT_SHIFT_GTAB_ID_V1_8821C)
+#define BITS_GTAB_ID_V1_8821C                                                  \
+	(BIT_MASK_GTAB_ID_V1_8821C << BIT_SHIFT_GTAB_ID_V1_8821C)
+#define BIT_CLEAR_GTAB_ID_V1_8821C(x) ((x) & (~BITS_GTAB_ID_V1_8821C))
+#define BIT_GET_GTAB_ID_V1_8821C(x)                                            \
+	(((x) >> BIT_SHIFT_GTAB_ID_V1_8821C) & BIT_MASK_GTAB_ID_V1_8821C)
+#define BIT_SET_GTAB_ID_V1_8821C(x, v)                                         \
+	(BIT_CLEAR_GTAB_ID_V1_8821C(x) | BIT_GTAB_ID_V1_8821C(v))
+
+#define BIT_SHIFT_AC0_PKT_INFO_8821C 0
+#define BIT_MASK_AC0_PKT_INFO_8821C 0xfff
+#define BIT_AC0_PKT_INFO_8821C(x)                                              \
+	(((x) & BIT_MASK_AC0_PKT_INFO_8821C) << BIT_SHIFT_AC0_PKT_INFO_8821C)
+#define BITS_AC0_PKT_INFO_8821C                                                \
+	(BIT_MASK_AC0_PKT_INFO_8821C << BIT_SHIFT_AC0_PKT_INFO_8821C)
+#define BIT_CLEAR_AC0_PKT_INFO_8821C(x) ((x) & (~BITS_AC0_PKT_INFO_8821C))
+#define BIT_GET_AC0_PKT_INFO_8821C(x)                                          \
+	(((x) >> BIT_SHIFT_AC0_PKT_INFO_8821C) & BIT_MASK_AC0_PKT_INFO_8821C)
+#define BIT_SET_AC0_PKT_INFO_8821C(x, v)                                       \
+	(BIT_CLEAR_AC0_PKT_INFO_8821C(x) | BIT_AC0_PKT_INFO_8821C(v))
+
+/* 2 REG_Q2_Q3_INFO_8821C */
+#define BIT_QUEUE_MACID_AC_NOT_THE_SAME_8821C BIT(31)
+
+#define BIT_SHIFT_GTAB_ID_8821C 28
+#define BIT_MASK_GTAB_ID_8821C 0x7
+#define BIT_GTAB_ID_8821C(x)                                                   \
+	(((x) & BIT_MASK_GTAB_ID_8821C) << BIT_SHIFT_GTAB_ID_8821C)
+#define BITS_GTAB_ID_8821C (BIT_MASK_GTAB_ID_8821C << BIT_SHIFT_GTAB_ID_8821C)
+#define BIT_CLEAR_GTAB_ID_8821C(x) ((x) & (~BITS_GTAB_ID_8821C))
+#define BIT_GET_GTAB_ID_8821C(x)                                               \
+	(((x) >> BIT_SHIFT_GTAB_ID_8821C) & BIT_MASK_GTAB_ID_8821C)
+#define BIT_SET_GTAB_ID_8821C(x, v)                                            \
+	(BIT_CLEAR_GTAB_ID_8821C(x) | BIT_GTAB_ID_8821C(v))
+
+#define BIT_SHIFT_AC3_PKT_INFO_8821C 16
+#define BIT_MASK_AC3_PKT_INFO_8821C 0xfff
+#define BIT_AC3_PKT_INFO_8821C(x)                                              \
+	(((x) & BIT_MASK_AC3_PKT_INFO_8821C) << BIT_SHIFT_AC3_PKT_INFO_8821C)
+#define BITS_AC3_PKT_INFO_8821C                                                \
+	(BIT_MASK_AC3_PKT_INFO_8821C << BIT_SHIFT_AC3_PKT_INFO_8821C)
+#define BIT_CLEAR_AC3_PKT_INFO_8821C(x) ((x) & (~BITS_AC3_PKT_INFO_8821C))
+#define BIT_GET_AC3_PKT_INFO_8821C(x)                                          \
+	(((x) >> BIT_SHIFT_AC3_PKT_INFO_8821C) & BIT_MASK_AC3_PKT_INFO_8821C)
+#define BIT_SET_AC3_PKT_INFO_8821C(x, v)                                       \
+	(BIT_CLEAR_AC3_PKT_INFO_8821C(x) | BIT_AC3_PKT_INFO_8821C(v))
+
+#define BIT_QUEUE_MACID_AC_NOT_THE_SAME_V1_8821C BIT(15)
+
+#define BIT_SHIFT_GTAB_ID_V1_8821C 12
+#define BIT_MASK_GTAB_ID_V1_8821C 0x7
+#define BIT_GTAB_ID_V1_8821C(x)                                                \
+	(((x) & BIT_MASK_GTAB_ID_V1_8821C) << BIT_SHIFT_GTAB_ID_V1_8821C)
+#define BITS_GTAB_ID_V1_8821C                                                  \
+	(BIT_MASK_GTAB_ID_V1_8821C << BIT_SHIFT_GTAB_ID_V1_8821C)
+#define BIT_CLEAR_GTAB_ID_V1_8821C(x) ((x) & (~BITS_GTAB_ID_V1_8821C))
+#define BIT_GET_GTAB_ID_V1_8821C(x)                                            \
+	(((x) >> BIT_SHIFT_GTAB_ID_V1_8821C) & BIT_MASK_GTAB_ID_V1_8821C)
+#define BIT_SET_GTAB_ID_V1_8821C(x, v)                                         \
+	(BIT_CLEAR_GTAB_ID_V1_8821C(x) | BIT_GTAB_ID_V1_8821C(v))
+
+#define BIT_SHIFT_AC2_PKT_INFO_8821C 0
+#define BIT_MASK_AC2_PKT_INFO_8821C 0xfff
+#define BIT_AC2_PKT_INFO_8821C(x)                                              \
+	(((x) & BIT_MASK_AC2_PKT_INFO_8821C) << BIT_SHIFT_AC2_PKT_INFO_8821C)
+#define BITS_AC2_PKT_INFO_8821C                                                \
+	(BIT_MASK_AC2_PKT_INFO_8821C << BIT_SHIFT_AC2_PKT_INFO_8821C)
+#define BIT_CLEAR_AC2_PKT_INFO_8821C(x) ((x) & (~BITS_AC2_PKT_INFO_8821C))
+#define BIT_GET_AC2_PKT_INFO_8821C(x)                                          \
+	(((x) >> BIT_SHIFT_AC2_PKT_INFO_8821C) & BIT_MASK_AC2_PKT_INFO_8821C)
+#define BIT_SET_AC2_PKT_INFO_8821C(x, v)                                       \
+	(BIT_CLEAR_AC2_PKT_INFO_8821C(x) | BIT_AC2_PKT_INFO_8821C(v))
+
+/* 2 REG_Q4_Q5_INFO_8821C */
+#define BIT_QUEUE_MACID_AC_NOT_THE_SAME_8821C BIT(31)
+
+#define BIT_SHIFT_GTAB_ID_8821C 28
+#define BIT_MASK_GTAB_ID_8821C 0x7
+#define BIT_GTAB_ID_8821C(x)                                                   \
+	(((x) & BIT_MASK_GTAB_ID_8821C) << BIT_SHIFT_GTAB_ID_8821C)
+#define BITS_GTAB_ID_8821C (BIT_MASK_GTAB_ID_8821C << BIT_SHIFT_GTAB_ID_8821C)
+#define BIT_CLEAR_GTAB_ID_8821C(x) ((x) & (~BITS_GTAB_ID_8821C))
+#define BIT_GET_GTAB_ID_8821C(x)                                               \
+	(((x) >> BIT_SHIFT_GTAB_ID_8821C) & BIT_MASK_GTAB_ID_8821C)
+#define BIT_SET_GTAB_ID_8821C(x, v)                                            \
+	(BIT_CLEAR_GTAB_ID_8821C(x) | BIT_GTAB_ID_8821C(v))
+
+#define BIT_SHIFT_AC5_PKT_INFO_8821C 16
+#define BIT_MASK_AC5_PKT_INFO_8821C 0xfff
+#define BIT_AC5_PKT_INFO_8821C(x)                                              \
+	(((x) & BIT_MASK_AC5_PKT_INFO_8821C) << BIT_SHIFT_AC5_PKT_INFO_8821C)
+#define BITS_AC5_PKT_INFO_8821C                                                \
+	(BIT_MASK_AC5_PKT_INFO_8821C << BIT_SHIFT_AC5_PKT_INFO_8821C)
+#define BIT_CLEAR_AC5_PKT_INFO_8821C(x) ((x) & (~BITS_AC5_PKT_INFO_8821C))
+#define BIT_GET_AC5_PKT_INFO_8821C(x)                                          \
+	(((x) >> BIT_SHIFT_AC5_PKT_INFO_8821C) & BIT_MASK_AC5_PKT_INFO_8821C)
+#define BIT_SET_AC5_PKT_INFO_8821C(x, v)                                       \
+	(BIT_CLEAR_AC5_PKT_INFO_8821C(x) | BIT_AC5_PKT_INFO_8821C(v))
+
+#define BIT_QUEUE_MACID_AC_NOT_THE_SAME_V1_8821C BIT(15)
+
+#define BIT_SHIFT_GTAB_ID_V1_8821C 12
+#define BIT_MASK_GTAB_ID_V1_8821C 0x7
+#define BIT_GTAB_ID_V1_8821C(x)                                                \
+	(((x) & BIT_MASK_GTAB_ID_V1_8821C) << BIT_SHIFT_GTAB_ID_V1_8821C)
+#define BITS_GTAB_ID_V1_8821C                                                  \
+	(BIT_MASK_GTAB_ID_V1_8821C << BIT_SHIFT_GTAB_ID_V1_8821C)
+#define BIT_CLEAR_GTAB_ID_V1_8821C(x) ((x) & (~BITS_GTAB_ID_V1_8821C))
+#define BIT_GET_GTAB_ID_V1_8821C(x)                                            \
+	(((x) >> BIT_SHIFT_GTAB_ID_V1_8821C) & BIT_MASK_GTAB_ID_V1_8821C)
+#define BIT_SET_GTAB_ID_V1_8821C(x, v)                                         \
+	(BIT_CLEAR_GTAB_ID_V1_8821C(x) | BIT_GTAB_ID_V1_8821C(v))
+
+#define BIT_SHIFT_AC4_PKT_INFO_8821C 0
+#define BIT_MASK_AC4_PKT_INFO_8821C 0xfff
+#define BIT_AC4_PKT_INFO_8821C(x)                                              \
+	(((x) & BIT_MASK_AC4_PKT_INFO_8821C) << BIT_SHIFT_AC4_PKT_INFO_8821C)
+#define BITS_AC4_PKT_INFO_8821C                                                \
+	(BIT_MASK_AC4_PKT_INFO_8821C << BIT_SHIFT_AC4_PKT_INFO_8821C)
+#define BIT_CLEAR_AC4_PKT_INFO_8821C(x) ((x) & (~BITS_AC4_PKT_INFO_8821C))
+#define BIT_GET_AC4_PKT_INFO_8821C(x)                                          \
+	(((x) >> BIT_SHIFT_AC4_PKT_INFO_8821C) & BIT_MASK_AC4_PKT_INFO_8821C)
+#define BIT_SET_AC4_PKT_INFO_8821C(x, v)                                       \
+	(BIT_CLEAR_AC4_PKT_INFO_8821C(x) | BIT_AC4_PKT_INFO_8821C(v))
+
+/* 2 REG_Q6_Q7_INFO_8821C */
+#define BIT_QUEUE_MACID_AC_NOT_THE_SAME_8821C BIT(31)
+
+#define BIT_SHIFT_GTAB_ID_8821C 28
+#define BIT_MASK_GTAB_ID_8821C 0x7
+#define BIT_GTAB_ID_8821C(x)                                                   \
+	(((x) & BIT_MASK_GTAB_ID_8821C) << BIT_SHIFT_GTAB_ID_8821C)
+#define BITS_GTAB_ID_8821C (BIT_MASK_GTAB_ID_8821C << BIT_SHIFT_GTAB_ID_8821C)
+#define BIT_CLEAR_GTAB_ID_8821C(x) ((x) & (~BITS_GTAB_ID_8821C))
+#define BIT_GET_GTAB_ID_8821C(x)                                               \
+	(((x) >> BIT_SHIFT_GTAB_ID_8821C) & BIT_MASK_GTAB_ID_8821C)
+#define BIT_SET_GTAB_ID_8821C(x, v)                                            \
+	(BIT_CLEAR_GTAB_ID_8821C(x) | BIT_GTAB_ID_8821C(v))
+
+#define BIT_SHIFT_AC7_PKT_INFO_8821C 16
+#define BIT_MASK_AC7_PKT_INFO_8821C 0xfff
+#define BIT_AC7_PKT_INFO_8821C(x)                                              \
+	(((x) & BIT_MASK_AC7_PKT_INFO_8821C) << BIT_SHIFT_AC7_PKT_INFO_8821C)
+#define BITS_AC7_PKT_INFO_8821C                                                \
+	(BIT_MASK_AC7_PKT_INFO_8821C << BIT_SHIFT_AC7_PKT_INFO_8821C)
+#define BIT_CLEAR_AC7_PKT_INFO_8821C(x) ((x) & (~BITS_AC7_PKT_INFO_8821C))
+#define BIT_GET_AC7_PKT_INFO_8821C(x)                                          \
+	(((x) >> BIT_SHIFT_AC7_PKT_INFO_8821C) & BIT_MASK_AC7_PKT_INFO_8821C)
+#define BIT_SET_AC7_PKT_INFO_8821C(x, v)                                       \
+	(BIT_CLEAR_AC7_PKT_INFO_8821C(x) | BIT_AC7_PKT_INFO_8821C(v))
+
+#define BIT_QUEUE_MACID_AC_NOT_THE_SAME_V1_8821C BIT(15)
+
+#define BIT_SHIFT_GTAB_ID_V1_8821C 12
+#define BIT_MASK_GTAB_ID_V1_8821C 0x7
+#define BIT_GTAB_ID_V1_8821C(x)                                                \
+	(((x) & BIT_MASK_GTAB_ID_V1_8821C) << BIT_SHIFT_GTAB_ID_V1_8821C)
+#define BITS_GTAB_ID_V1_8821C                                                  \
+	(BIT_MASK_GTAB_ID_V1_8821C << BIT_SHIFT_GTAB_ID_V1_8821C)
+#define BIT_CLEAR_GTAB_ID_V1_8821C(x) ((x) & (~BITS_GTAB_ID_V1_8821C))
+#define BIT_GET_GTAB_ID_V1_8821C(x)                                            \
+	(((x) >> BIT_SHIFT_GTAB_ID_V1_8821C) & BIT_MASK_GTAB_ID_V1_8821C)
+#define BIT_SET_GTAB_ID_V1_8821C(x, v)                                         \
+	(BIT_CLEAR_GTAB_ID_V1_8821C(x) | BIT_GTAB_ID_V1_8821C(v))
+
+#define BIT_SHIFT_AC6_PKT_INFO_8821C 0
+#define BIT_MASK_AC6_PKT_INFO_8821C 0xfff
+#define BIT_AC6_PKT_INFO_8821C(x)                                              \
+	(((x) & BIT_MASK_AC6_PKT_INFO_8821C) << BIT_SHIFT_AC6_PKT_INFO_8821C)
+#define BITS_AC6_PKT_INFO_8821C                                                \
+	(BIT_MASK_AC6_PKT_INFO_8821C << BIT_SHIFT_AC6_PKT_INFO_8821C)
+#define BIT_CLEAR_AC6_PKT_INFO_8821C(x) ((x) & (~BITS_AC6_PKT_INFO_8821C))
+#define BIT_GET_AC6_PKT_INFO_8821C(x)                                          \
+	(((x) >> BIT_SHIFT_AC6_PKT_INFO_8821C) & BIT_MASK_AC6_PKT_INFO_8821C)
+#define BIT_SET_AC6_PKT_INFO_8821C(x, v)                                       \
+	(BIT_CLEAR_AC6_PKT_INFO_8821C(x) | BIT_AC6_PKT_INFO_8821C(v))
+
+/* 2 REG_MGQ_HIQ_INFO_8821C */
+
+#define BIT_SHIFT_HIQ_PKT_INFO_8821C 16
+#define BIT_MASK_HIQ_PKT_INFO_8821C 0xfff
+#define BIT_HIQ_PKT_INFO_8821C(x)                                              \
+	(((x) & BIT_MASK_HIQ_PKT_INFO_8821C) << BIT_SHIFT_HIQ_PKT_INFO_8821C)
+#define BITS_HIQ_PKT_INFO_8821C                                                \
+	(BIT_MASK_HIQ_PKT_INFO_8821C << BIT_SHIFT_HIQ_PKT_INFO_8821C)
+#define BIT_CLEAR_HIQ_PKT_INFO_8821C(x) ((x) & (~BITS_HIQ_PKT_INFO_8821C))
+#define BIT_GET_HIQ_PKT_INFO_8821C(x)                                          \
+	(((x) >> BIT_SHIFT_HIQ_PKT_INFO_8821C) & BIT_MASK_HIQ_PKT_INFO_8821C)
+#define BIT_SET_HIQ_PKT_INFO_8821C(x, v)                                       \
+	(BIT_CLEAR_HIQ_PKT_INFO_8821C(x) | BIT_HIQ_PKT_INFO_8821C(v))
+
+#define BIT_SHIFT_MGQ_PKT_INFO_8821C 0
+#define BIT_MASK_MGQ_PKT_INFO_8821C 0xfff
+#define BIT_MGQ_PKT_INFO_8821C(x)                                              \
+	(((x) & BIT_MASK_MGQ_PKT_INFO_8821C) << BIT_SHIFT_MGQ_PKT_INFO_8821C)
+#define BITS_MGQ_PKT_INFO_8821C                                                \
+	(BIT_MASK_MGQ_PKT_INFO_8821C << BIT_SHIFT_MGQ_PKT_INFO_8821C)
+#define BIT_CLEAR_MGQ_PKT_INFO_8821C(x) ((x) & (~BITS_MGQ_PKT_INFO_8821C))
+#define BIT_GET_MGQ_PKT_INFO_8821C(x)                                          \
+	(((x) >> BIT_SHIFT_MGQ_PKT_INFO_8821C) & BIT_MASK_MGQ_PKT_INFO_8821C)
+#define BIT_SET_MGQ_PKT_INFO_8821C(x, v)                                       \
+	(BIT_CLEAR_MGQ_PKT_INFO_8821C(x) | BIT_MGQ_PKT_INFO_8821C(v))
+
+/* 2 REG_CMDQ_BCNQ_INFO_8821C */
+
+#define BIT_SHIFT_CMDQ_PKT_INFO_8821C 16
+#define BIT_MASK_CMDQ_PKT_INFO_8821C 0xfff
+#define BIT_CMDQ_PKT_INFO_8821C(x)                                             \
+	(((x) & BIT_MASK_CMDQ_PKT_INFO_8821C) << BIT_SHIFT_CMDQ_PKT_INFO_8821C)
+#define BITS_CMDQ_PKT_INFO_8821C                                               \
+	(BIT_MASK_CMDQ_PKT_INFO_8821C << BIT_SHIFT_CMDQ_PKT_INFO_8821C)
+#define BIT_CLEAR_CMDQ_PKT_INFO_8821C(x) ((x) & (~BITS_CMDQ_PKT_INFO_8821C))
+#define BIT_GET_CMDQ_PKT_INFO_8821C(x)                                         \
+	(((x) >> BIT_SHIFT_CMDQ_PKT_INFO_8821C) & BIT_MASK_CMDQ_PKT_INFO_8821C)
+#define BIT_SET_CMDQ_PKT_INFO_8821C(x, v)                                      \
+	(BIT_CLEAR_CMDQ_PKT_INFO_8821C(x) | BIT_CMDQ_PKT_INFO_8821C(v))
+
+#define BIT_SHIFT_BCNQ_PKT_INFO_8821C 0
+#define BIT_MASK_BCNQ_PKT_INFO_8821C 0xfff
+#define BIT_BCNQ_PKT_INFO_8821C(x)                                             \
+	(((x) & BIT_MASK_BCNQ_PKT_INFO_8821C) << BIT_SHIFT_BCNQ_PKT_INFO_8821C)
+#define BITS_BCNQ_PKT_INFO_8821C                                               \
+	(BIT_MASK_BCNQ_PKT_INFO_8821C << BIT_SHIFT_BCNQ_PKT_INFO_8821C)
+#define BIT_CLEAR_BCNQ_PKT_INFO_8821C(x) ((x) & (~BITS_BCNQ_PKT_INFO_8821C))
+#define BIT_GET_BCNQ_PKT_INFO_8821C(x)                                         \
+	(((x) >> BIT_SHIFT_BCNQ_PKT_INFO_8821C) & BIT_MASK_BCNQ_PKT_INFO_8821C)
+#define BIT_SET_BCNQ_PKT_INFO_8821C(x, v)                                      \
+	(BIT_CLEAR_BCNQ_PKT_INFO_8821C(x) | BIT_BCNQ_PKT_INFO_8821C(v))
+
+/* 2 REG_USEREG_SETTING_8821C */
+#define BIT_NDPA_USEREG_8821C BIT(21)
+
+#define BIT_SHIFT_RETRY_USEREG_8821C 19
+#define BIT_MASK_RETRY_USEREG_8821C 0x3
+#define BIT_RETRY_USEREG_8821C(x)                                              \
+	(((x) & BIT_MASK_RETRY_USEREG_8821C) << BIT_SHIFT_RETRY_USEREG_8821C)
+#define BITS_RETRY_USEREG_8821C                                                \
+	(BIT_MASK_RETRY_USEREG_8821C << BIT_SHIFT_RETRY_USEREG_8821C)
+#define BIT_CLEAR_RETRY_USEREG_8821C(x) ((x) & (~BITS_RETRY_USEREG_8821C))
+#define BIT_GET_RETRY_USEREG_8821C(x)                                          \
+	(((x) >> BIT_SHIFT_RETRY_USEREG_8821C) & BIT_MASK_RETRY_USEREG_8821C)
+#define BIT_SET_RETRY_USEREG_8821C(x, v)                                       \
+	(BIT_CLEAR_RETRY_USEREG_8821C(x) | BIT_RETRY_USEREG_8821C(v))
+
+#define BIT_SHIFT_TRYPKT_USEREG_8821C 17
+#define BIT_MASK_TRYPKT_USEREG_8821C 0x3
+#define BIT_TRYPKT_USEREG_8821C(x)                                             \
+	(((x) & BIT_MASK_TRYPKT_USEREG_8821C) << BIT_SHIFT_TRYPKT_USEREG_8821C)
+#define BITS_TRYPKT_USEREG_8821C                                               \
+	(BIT_MASK_TRYPKT_USEREG_8821C << BIT_SHIFT_TRYPKT_USEREG_8821C)
+#define BIT_CLEAR_TRYPKT_USEREG_8821C(x) ((x) & (~BITS_TRYPKT_USEREG_8821C))
+#define BIT_GET_TRYPKT_USEREG_8821C(x)                                         \
+	(((x) >> BIT_SHIFT_TRYPKT_USEREG_8821C) & BIT_MASK_TRYPKT_USEREG_8821C)
+#define BIT_SET_TRYPKT_USEREG_8821C(x, v)                                      \
+	(BIT_CLEAR_TRYPKT_USEREG_8821C(x) | BIT_TRYPKT_USEREG_8821C(v))
+
+#define BIT_CTLPKT_USEREG_8821C BIT(16)
+
+/* 2 REG_AESIV_SETTING_8821C */
+
+#define BIT_SHIFT_AESIV_OFFSET_8821C 0
+#define BIT_MASK_AESIV_OFFSET_8821C 0xfff
+#define BIT_AESIV_OFFSET_8821C(x)                                              \
+	(((x) & BIT_MASK_AESIV_OFFSET_8821C) << BIT_SHIFT_AESIV_OFFSET_8821C)
+#define BITS_AESIV_OFFSET_8821C                                                \
+	(BIT_MASK_AESIV_OFFSET_8821C << BIT_SHIFT_AESIV_OFFSET_8821C)
+#define BIT_CLEAR_AESIV_OFFSET_8821C(x) ((x) & (~BITS_AESIV_OFFSET_8821C))
+#define BIT_GET_AESIV_OFFSET_8821C(x)                                          \
+	(((x) >> BIT_SHIFT_AESIV_OFFSET_8821C) & BIT_MASK_AESIV_OFFSET_8821C)
+#define BIT_SET_AESIV_OFFSET_8821C(x, v)                                       \
+	(BIT_CLEAR_AESIV_OFFSET_8821C(x) | BIT_AESIV_OFFSET_8821C(v))
+
+/* 2 REG_BF0_TIME_SETTING_8821C */
+#define BIT_BF0_TIMER_SET_8821C BIT(31)
+#define BIT_BF0_TIMER_CLR_8821C BIT(30)
+#define BIT_BF0_UPDATE_EN_8821C BIT(29)
+#define BIT_BF0_TIMER_EN_8821C BIT(28)
+
+#define BIT_SHIFT_BF0_PRETIME_OVER_8821C 16
+#define BIT_MASK_BF0_PRETIME_OVER_8821C 0xfff
+#define BIT_BF0_PRETIME_OVER_8821C(x)                                          \
+	(((x) & BIT_MASK_BF0_PRETIME_OVER_8821C)                               \
+	 << BIT_SHIFT_BF0_PRETIME_OVER_8821C)
+#define BITS_BF0_PRETIME_OVER_8821C                                            \
+	(BIT_MASK_BF0_PRETIME_OVER_8821C << BIT_SHIFT_BF0_PRETIME_OVER_8821C)
+#define BIT_CLEAR_BF0_PRETIME_OVER_8821C(x)                                    \
+	((x) & (~BITS_BF0_PRETIME_OVER_8821C))
+#define BIT_GET_BF0_PRETIME_OVER_8821C(x)                                      \
+	(((x) >> BIT_SHIFT_BF0_PRETIME_OVER_8821C) &                           \
+	 BIT_MASK_BF0_PRETIME_OVER_8821C)
+#define BIT_SET_BF0_PRETIME_OVER_8821C(x, v)                                   \
+	(BIT_CLEAR_BF0_PRETIME_OVER_8821C(x) | BIT_BF0_PRETIME_OVER_8821C(v))
+
+#define BIT_SHIFT_BF0_LIFETIME_8821C 0
+#define BIT_MASK_BF0_LIFETIME_8821C 0xffff
+#define BIT_BF0_LIFETIME_8821C(x)                                              \
+	(((x) & BIT_MASK_BF0_LIFETIME_8821C) << BIT_SHIFT_BF0_LIFETIME_8821C)
+#define BITS_BF0_LIFETIME_8821C                                                \
+	(BIT_MASK_BF0_LIFETIME_8821C << BIT_SHIFT_BF0_LIFETIME_8821C)
+#define BIT_CLEAR_BF0_LIFETIME_8821C(x) ((x) & (~BITS_BF0_LIFETIME_8821C))
+#define BIT_GET_BF0_LIFETIME_8821C(x)                                          \
+	(((x) >> BIT_SHIFT_BF0_LIFETIME_8821C) & BIT_MASK_BF0_LIFETIME_8821C)
+#define BIT_SET_BF0_LIFETIME_8821C(x, v)                                       \
+	(BIT_CLEAR_BF0_LIFETIME_8821C(x) | BIT_BF0_LIFETIME_8821C(v))
+
+/* 2 REG_BF1_TIME_SETTING_8821C */
+#define BIT_BF1_TIMER_SET_8821C BIT(31)
+#define BIT_BF1_TIMER_CLR_8821C BIT(30)
+#define BIT_BF1_UPDATE_EN_8821C BIT(29)
+#define BIT_BF1_TIMER_EN_8821C BIT(28)
+
+#define BIT_SHIFT_BF1_PRETIME_OVER_8821C 16
+#define BIT_MASK_BF1_PRETIME_OVER_8821C 0xfff
+#define BIT_BF1_PRETIME_OVER_8821C(x)                                          \
+	(((x) & BIT_MASK_BF1_PRETIME_OVER_8821C)                               \
+	 << BIT_SHIFT_BF1_PRETIME_OVER_8821C)
+#define BITS_BF1_PRETIME_OVER_8821C                                            \
+	(BIT_MASK_BF1_PRETIME_OVER_8821C << BIT_SHIFT_BF1_PRETIME_OVER_8821C)
+#define BIT_CLEAR_BF1_PRETIME_OVER_8821C(x)                                    \
+	((x) & (~BITS_BF1_PRETIME_OVER_8821C))
+#define BIT_GET_BF1_PRETIME_OVER_8821C(x)                                      \
+	(((x) >> BIT_SHIFT_BF1_PRETIME_OVER_8821C) &                           \
+	 BIT_MASK_BF1_PRETIME_OVER_8821C)
+#define BIT_SET_BF1_PRETIME_OVER_8821C(x, v)                                   \
+	(BIT_CLEAR_BF1_PRETIME_OVER_8821C(x) | BIT_BF1_PRETIME_OVER_8821C(v))
+
+#define BIT_SHIFT_BF1_LIFETIME_8821C 0
+#define BIT_MASK_BF1_LIFETIME_8821C 0xffff
+#define BIT_BF1_LIFETIME_8821C(x)                                              \
+	(((x) & BIT_MASK_BF1_LIFETIME_8821C) << BIT_SHIFT_BF1_LIFETIME_8821C)
+#define BITS_BF1_LIFETIME_8821C                                                \
+	(BIT_MASK_BF1_LIFETIME_8821C << BIT_SHIFT_BF1_LIFETIME_8821C)
+#define BIT_CLEAR_BF1_LIFETIME_8821C(x) ((x) & (~BITS_BF1_LIFETIME_8821C))
+#define BIT_GET_BF1_LIFETIME_8821C(x)                                          \
+	(((x) >> BIT_SHIFT_BF1_LIFETIME_8821C) & BIT_MASK_BF1_LIFETIME_8821C)
+#define BIT_SET_BF1_LIFETIME_8821C(x, v)                                       \
+	(BIT_CLEAR_BF1_LIFETIME_8821C(x) | BIT_BF1_LIFETIME_8821C(v))
+
+/* 2 REG_BF_TIMEOUT_EN_8821C */
+#define BIT_EN_VHT_LDPC_8821C BIT(9)
+#define BIT_EN_HT_LDPC_8821C BIT(8)
+#define BIT_BF1_TIMEOUT_EN_8821C BIT(1)
+#define BIT_BF0_TIMEOUT_EN_8821C BIT(0)
+
+/* 2 REG_MACID_RELEASE0_8821C */
+
+#define BIT_SHIFT_MACID31_0_RELEASE_8821C 0
+#define BIT_MASK_MACID31_0_RELEASE_8821C 0xffffffffL
+#define BIT_MACID31_0_RELEASE_8821C(x)                                         \
+	(((x) & BIT_MASK_MACID31_0_RELEASE_8821C)                              \
+	 << BIT_SHIFT_MACID31_0_RELEASE_8821C)
+#define BITS_MACID31_0_RELEASE_8821C                                           \
+	(BIT_MASK_MACID31_0_RELEASE_8821C << BIT_SHIFT_MACID31_0_RELEASE_8821C)
+#define BIT_CLEAR_MACID31_0_RELEASE_8821C(x)                                   \
+	((x) & (~BITS_MACID31_0_RELEASE_8821C))
+#define BIT_GET_MACID31_0_RELEASE_8821C(x)                                     \
+	(((x) >> BIT_SHIFT_MACID31_0_RELEASE_8821C) &                          \
+	 BIT_MASK_MACID31_0_RELEASE_8821C)
+#define BIT_SET_MACID31_0_RELEASE_8821C(x, v)                                  \
+	(BIT_CLEAR_MACID31_0_RELEASE_8821C(x) | BIT_MACID31_0_RELEASE_8821C(v))
+
+/* 2 REG_MACID_RELEASE1_8821C */
+
+#define BIT_SHIFT_MACID63_32_RELEASE_8821C 0
+#define BIT_MASK_MACID63_32_RELEASE_8821C 0xffffffffL
+#define BIT_MACID63_32_RELEASE_8821C(x)                                        \
+	(((x) & BIT_MASK_MACID63_32_RELEASE_8821C)                             \
+	 << BIT_SHIFT_MACID63_32_RELEASE_8821C)
+#define BITS_MACID63_32_RELEASE_8821C                                          \
+	(BIT_MASK_MACID63_32_RELEASE_8821C                                     \
+	 << BIT_SHIFT_MACID63_32_RELEASE_8821C)
+#define BIT_CLEAR_MACID63_32_RELEASE_8821C(x)                                  \
+	((x) & (~BITS_MACID63_32_RELEASE_8821C))
+#define BIT_GET_MACID63_32_RELEASE_8821C(x)                                    \
+	(((x) >> BIT_SHIFT_MACID63_32_RELEASE_8821C) &                         \
+	 BIT_MASK_MACID63_32_RELEASE_8821C)
+#define BIT_SET_MACID63_32_RELEASE_8821C(x, v)                                 \
+	(BIT_CLEAR_MACID63_32_RELEASE_8821C(x) |                               \
+	 BIT_MACID63_32_RELEASE_8821C(v))
+
+/* 2 REG_MACID_RELEASE2_8821C */
+
+#define BIT_SHIFT_MACID95_64_RELEASE_8821C 0
+#define BIT_MASK_MACID95_64_RELEASE_8821C 0xffffffffL
+#define BIT_MACID95_64_RELEASE_8821C(x)                                        \
+	(((x) & BIT_MASK_MACID95_64_RELEASE_8821C)                             \
+	 << BIT_SHIFT_MACID95_64_RELEASE_8821C)
+#define BITS_MACID95_64_RELEASE_8821C                                          \
+	(BIT_MASK_MACID95_64_RELEASE_8821C                                     \
+	 << BIT_SHIFT_MACID95_64_RELEASE_8821C)
+#define BIT_CLEAR_MACID95_64_RELEASE_8821C(x)                                  \
+	((x) & (~BITS_MACID95_64_RELEASE_8821C))
+#define BIT_GET_MACID95_64_RELEASE_8821C(x)                                    \
+	(((x) >> BIT_SHIFT_MACID95_64_RELEASE_8821C) &                         \
+	 BIT_MASK_MACID95_64_RELEASE_8821C)
+#define BIT_SET_MACID95_64_RELEASE_8821C(x, v)                                 \
+	(BIT_CLEAR_MACID95_64_RELEASE_8821C(x) |                               \
+	 BIT_MACID95_64_RELEASE_8821C(v))
+
+/* 2 REG_MACID_RELEASE3_8821C */
+
+#define BIT_SHIFT_MACID127_96_RELEASE_8821C 0
+#define BIT_MASK_MACID127_96_RELEASE_8821C 0xffffffffL
+#define BIT_MACID127_96_RELEASE_8821C(x)                                       \
+	(((x) & BIT_MASK_MACID127_96_RELEASE_8821C)                            \
+	 << BIT_SHIFT_MACID127_96_RELEASE_8821C)
+#define BITS_MACID127_96_RELEASE_8821C                                         \
+	(BIT_MASK_MACID127_96_RELEASE_8821C                                    \
+	 << BIT_SHIFT_MACID127_96_RELEASE_8821C)
+#define BIT_CLEAR_MACID127_96_RELEASE_8821C(x)                                 \
+	((x) & (~BITS_MACID127_96_RELEASE_8821C))
+#define BIT_GET_MACID127_96_RELEASE_8821C(x)                                   \
+	(((x) >> BIT_SHIFT_MACID127_96_RELEASE_8821C) &                        \
+	 BIT_MASK_MACID127_96_RELEASE_8821C)
+#define BIT_SET_MACID127_96_RELEASE_8821C(x, v)                                \
+	(BIT_CLEAR_MACID127_96_RELEASE_8821C(x) |                              \
+	 BIT_MACID127_96_RELEASE_8821C(v))
+
+/* 2 REG_MACID_RELEASE_SETTING_8821C */
+#define BIT_MACID_VALUE_8821C BIT(7)
+
+#define BIT_SHIFT_MACID_OFFSET_8821C 0
+#define BIT_MASK_MACID_OFFSET_8821C 0x7f
+#define BIT_MACID_OFFSET_8821C(x)                                              \
+	(((x) & BIT_MASK_MACID_OFFSET_8821C) << BIT_SHIFT_MACID_OFFSET_8821C)
+#define BITS_MACID_OFFSET_8821C                                                \
+	(BIT_MASK_MACID_OFFSET_8821C << BIT_SHIFT_MACID_OFFSET_8821C)
+#define BIT_CLEAR_MACID_OFFSET_8821C(x) ((x) & (~BITS_MACID_OFFSET_8821C))
+#define BIT_GET_MACID_OFFSET_8821C(x)                                          \
+	(((x) >> BIT_SHIFT_MACID_OFFSET_8821C) & BIT_MASK_MACID_OFFSET_8821C)
+#define BIT_SET_MACID_OFFSET_8821C(x, v)                                       \
+	(BIT_CLEAR_MACID_OFFSET_8821C(x) | BIT_MACID_OFFSET_8821C(v))
+
+/* 2 REG_FAST_EDCA_VOVI_SETTING_8821C */
+
+#define BIT_SHIFT_VI_FAST_EDCA_TO_8821C 24
+#define BIT_MASK_VI_FAST_EDCA_TO_8821C 0xff
+#define BIT_VI_FAST_EDCA_TO_8821C(x)                                           \
+	(((x) & BIT_MASK_VI_FAST_EDCA_TO_8821C)                                \
+	 << BIT_SHIFT_VI_FAST_EDCA_TO_8821C)
+#define BITS_VI_FAST_EDCA_TO_8821C                                             \
+	(BIT_MASK_VI_FAST_EDCA_TO_8821C << BIT_SHIFT_VI_FAST_EDCA_TO_8821C)
+#define BIT_CLEAR_VI_FAST_EDCA_TO_8821C(x) ((x) & (~BITS_VI_FAST_EDCA_TO_8821C))
+#define BIT_GET_VI_FAST_EDCA_TO_8821C(x)                                       \
+	(((x) >> BIT_SHIFT_VI_FAST_EDCA_TO_8821C) &                            \
+	 BIT_MASK_VI_FAST_EDCA_TO_8821C)
+#define BIT_SET_VI_FAST_EDCA_TO_8821C(x, v)                                    \
+	(BIT_CLEAR_VI_FAST_EDCA_TO_8821C(x) | BIT_VI_FAST_EDCA_TO_8821C(v))
+
+#define BIT_VI_THRESHOLD_SEL_8821C BIT(23)
+
+#define BIT_SHIFT_VI_FAST_EDCA_PKT_TH_8821C 16
+#define BIT_MASK_VI_FAST_EDCA_PKT_TH_8821C 0x7f
+#define BIT_VI_FAST_EDCA_PKT_TH_8821C(x)                                       \
+	(((x) & BIT_MASK_VI_FAST_EDCA_PKT_TH_8821C)                            \
+	 << BIT_SHIFT_VI_FAST_EDCA_PKT_TH_8821C)
+#define BITS_VI_FAST_EDCA_PKT_TH_8821C                                         \
+	(BIT_MASK_VI_FAST_EDCA_PKT_TH_8821C                                    \
+	 << BIT_SHIFT_VI_FAST_EDCA_PKT_TH_8821C)
+#define BIT_CLEAR_VI_FAST_EDCA_PKT_TH_8821C(x)                                 \
+	((x) & (~BITS_VI_FAST_EDCA_PKT_TH_8821C))
+#define BIT_GET_VI_FAST_EDCA_PKT_TH_8821C(x)                                   \
+	(((x) >> BIT_SHIFT_VI_FAST_EDCA_PKT_TH_8821C) &                        \
+	 BIT_MASK_VI_FAST_EDCA_PKT_TH_8821C)
+#define BIT_SET_VI_FAST_EDCA_PKT_TH_8821C(x, v)                                \
+	(BIT_CLEAR_VI_FAST_EDCA_PKT_TH_8821C(x) |                              \
+	 BIT_VI_FAST_EDCA_PKT_TH_8821C(v))
+
+#define BIT_SHIFT_VO_FAST_EDCA_TO_8821C 8
+#define BIT_MASK_VO_FAST_EDCA_TO_8821C 0xff
+#define BIT_VO_FAST_EDCA_TO_8821C(x)                                           \
+	(((x) & BIT_MASK_VO_FAST_EDCA_TO_8821C)                                \
+	 << BIT_SHIFT_VO_FAST_EDCA_TO_8821C)
+#define BITS_VO_FAST_EDCA_TO_8821C                                             \
+	(BIT_MASK_VO_FAST_EDCA_TO_8821C << BIT_SHIFT_VO_FAST_EDCA_TO_8821C)
+#define BIT_CLEAR_VO_FAST_EDCA_TO_8821C(x) ((x) & (~BITS_VO_FAST_EDCA_TO_8821C))
+#define BIT_GET_VO_FAST_EDCA_TO_8821C(x)                                       \
+	(((x) >> BIT_SHIFT_VO_FAST_EDCA_TO_8821C) &                            \
+	 BIT_MASK_VO_FAST_EDCA_TO_8821C)
+#define BIT_SET_VO_FAST_EDCA_TO_8821C(x, v)                                    \
+	(BIT_CLEAR_VO_FAST_EDCA_TO_8821C(x) | BIT_VO_FAST_EDCA_TO_8821C(v))
+
+#define BIT_VO_THRESHOLD_SEL_8821C BIT(7)
+
+#define BIT_SHIFT_VO_FAST_EDCA_PKT_TH_8821C 0
+#define BIT_MASK_VO_FAST_EDCA_PKT_TH_8821C 0x7f
+#define BIT_VO_FAST_EDCA_PKT_TH_8821C(x)                                       \
+	(((x) & BIT_MASK_VO_FAST_EDCA_PKT_TH_8821C)                            \
+	 << BIT_SHIFT_VO_FAST_EDCA_PKT_TH_8821C)
+#define BITS_VO_FAST_EDCA_PKT_TH_8821C                                         \
+	(BIT_MASK_VO_FAST_EDCA_PKT_TH_8821C                                    \
+	 << BIT_SHIFT_VO_FAST_EDCA_PKT_TH_8821C)
+#define BIT_CLEAR_VO_FAST_EDCA_PKT_TH_8821C(x)                                 \
+	((x) & (~BITS_VO_FAST_EDCA_PKT_TH_8821C))
+#define BIT_GET_VO_FAST_EDCA_PKT_TH_8821C(x)                                   \
+	(((x) >> BIT_SHIFT_VO_FAST_EDCA_PKT_TH_8821C) &                        \
+	 BIT_MASK_VO_FAST_EDCA_PKT_TH_8821C)
+#define BIT_SET_VO_FAST_EDCA_PKT_TH_8821C(x, v)                                \
+	(BIT_CLEAR_VO_FAST_EDCA_PKT_TH_8821C(x) |                              \
+	 BIT_VO_FAST_EDCA_PKT_TH_8821C(v))
+
+/* 2 REG_FAST_EDCA_BEBK_SETTING_8821C */
+
+#define BIT_SHIFT_BK_FAST_EDCA_TO_8821C 24
+#define BIT_MASK_BK_FAST_EDCA_TO_8821C 0xff
+#define BIT_BK_FAST_EDCA_TO_8821C(x)                                           \
+	(((x) & BIT_MASK_BK_FAST_EDCA_TO_8821C)                                \
+	 << BIT_SHIFT_BK_FAST_EDCA_TO_8821C)
+#define BITS_BK_FAST_EDCA_TO_8821C                                             \
+	(BIT_MASK_BK_FAST_EDCA_TO_8821C << BIT_SHIFT_BK_FAST_EDCA_TO_8821C)
+#define BIT_CLEAR_BK_FAST_EDCA_TO_8821C(x) ((x) & (~BITS_BK_FAST_EDCA_TO_8821C))
+#define BIT_GET_BK_FAST_EDCA_TO_8821C(x)                                       \
+	(((x) >> BIT_SHIFT_BK_FAST_EDCA_TO_8821C) &                            \
+	 BIT_MASK_BK_FAST_EDCA_TO_8821C)
+#define BIT_SET_BK_FAST_EDCA_TO_8821C(x, v)                                    \
+	(BIT_CLEAR_BK_FAST_EDCA_TO_8821C(x) | BIT_BK_FAST_EDCA_TO_8821C(v))
+
+#define BIT_BK_THRESHOLD_SEL_8821C BIT(23)
+
+#define BIT_SHIFT_BK_FAST_EDCA_PKT_TH_8821C 16
+#define BIT_MASK_BK_FAST_EDCA_PKT_TH_8821C 0x7f
+#define BIT_BK_FAST_EDCA_PKT_TH_8821C(x)                                       \
+	(((x) & BIT_MASK_BK_FAST_EDCA_PKT_TH_8821C)                            \
+	 << BIT_SHIFT_BK_FAST_EDCA_PKT_TH_8821C)
+#define BITS_BK_FAST_EDCA_PKT_TH_8821C                                         \
+	(BIT_MASK_BK_FAST_EDCA_PKT_TH_8821C                                    \
+	 << BIT_SHIFT_BK_FAST_EDCA_PKT_TH_8821C)
+#define BIT_CLEAR_BK_FAST_EDCA_PKT_TH_8821C(x)                                 \
+	((x) & (~BITS_BK_FAST_EDCA_PKT_TH_8821C))
+#define BIT_GET_BK_FAST_EDCA_PKT_TH_8821C(x)                                   \
+	(((x) >> BIT_SHIFT_BK_FAST_EDCA_PKT_TH_8821C) &                        \
+	 BIT_MASK_BK_FAST_EDCA_PKT_TH_8821C)
+#define BIT_SET_BK_FAST_EDCA_PKT_TH_8821C(x, v)                                \
+	(BIT_CLEAR_BK_FAST_EDCA_PKT_TH_8821C(x) |                              \
+	 BIT_BK_FAST_EDCA_PKT_TH_8821C(v))
+
+#define BIT_SHIFT_BE_FAST_EDCA_TO_8821C 8
+#define BIT_MASK_BE_FAST_EDCA_TO_8821C 0xff
+#define BIT_BE_FAST_EDCA_TO_8821C(x)                                           \
+	(((x) & BIT_MASK_BE_FAST_EDCA_TO_8821C)                                \
+	 << BIT_SHIFT_BE_FAST_EDCA_TO_8821C)
+#define BITS_BE_FAST_EDCA_TO_8821C                                             \
+	(BIT_MASK_BE_FAST_EDCA_TO_8821C << BIT_SHIFT_BE_FAST_EDCA_TO_8821C)
+#define BIT_CLEAR_BE_FAST_EDCA_TO_8821C(x) ((x) & (~BITS_BE_FAST_EDCA_TO_8821C))
+#define BIT_GET_BE_FAST_EDCA_TO_8821C(x)                                       \
+	(((x) >> BIT_SHIFT_BE_FAST_EDCA_TO_8821C) &                            \
+	 BIT_MASK_BE_FAST_EDCA_TO_8821C)
+#define BIT_SET_BE_FAST_EDCA_TO_8821C(x, v)                                    \
+	(BIT_CLEAR_BE_FAST_EDCA_TO_8821C(x) | BIT_BE_FAST_EDCA_TO_8821C(v))
+
+#define BIT_BE_THRESHOLD_SEL_8821C BIT(7)
+
+#define BIT_SHIFT_BE_FAST_EDCA_PKT_TH_8821C 0
+#define BIT_MASK_BE_FAST_EDCA_PKT_TH_8821C 0x7f
+#define BIT_BE_FAST_EDCA_PKT_TH_8821C(x)                                       \
+	(((x) & BIT_MASK_BE_FAST_EDCA_PKT_TH_8821C)                            \
+	 << BIT_SHIFT_BE_FAST_EDCA_PKT_TH_8821C)
+#define BITS_BE_FAST_EDCA_PKT_TH_8821C                                         \
+	(BIT_MASK_BE_FAST_EDCA_PKT_TH_8821C                                    \
+	 << BIT_SHIFT_BE_FAST_EDCA_PKT_TH_8821C)
+#define BIT_CLEAR_BE_FAST_EDCA_PKT_TH_8821C(x)                                 \
+	((x) & (~BITS_BE_FAST_EDCA_PKT_TH_8821C))
+#define BIT_GET_BE_FAST_EDCA_PKT_TH_8821C(x)                                   \
+	(((x) >> BIT_SHIFT_BE_FAST_EDCA_PKT_TH_8821C) &                        \
+	 BIT_MASK_BE_FAST_EDCA_PKT_TH_8821C)
+#define BIT_SET_BE_FAST_EDCA_PKT_TH_8821C(x, v)                                \
+	(BIT_CLEAR_BE_FAST_EDCA_PKT_TH_8821C(x) |                              \
+	 BIT_BE_FAST_EDCA_PKT_TH_8821C(v))
+
+/* 2 REG_MACID_DROP0_8821C */
+
+#define BIT_SHIFT_MACID31_0_DROP_8821C 0
+#define BIT_MASK_MACID31_0_DROP_8821C 0xffffffffL
+#define BIT_MACID31_0_DROP_8821C(x)                                            \
+	(((x) & BIT_MASK_MACID31_0_DROP_8821C)                                 \
+	 << BIT_SHIFT_MACID31_0_DROP_8821C)
+#define BITS_MACID31_0_DROP_8821C                                              \
+	(BIT_MASK_MACID31_0_DROP_8821C << BIT_SHIFT_MACID31_0_DROP_8821C)
+#define BIT_CLEAR_MACID31_0_DROP_8821C(x) ((x) & (~BITS_MACID31_0_DROP_8821C))
+#define BIT_GET_MACID31_0_DROP_8821C(x)                                        \
+	(((x) >> BIT_SHIFT_MACID31_0_DROP_8821C) &                             \
+	 BIT_MASK_MACID31_0_DROP_8821C)
+#define BIT_SET_MACID31_0_DROP_8821C(x, v)                                     \
+	(BIT_CLEAR_MACID31_0_DROP_8821C(x) | BIT_MACID31_0_DROP_8821C(v))
+
+/* 2 REG_MACID_DROP1_8821C */
+
+#define BIT_SHIFT_MACID63_32_DROP_8821C 0
+#define BIT_MASK_MACID63_32_DROP_8821C 0xffffffffL
+#define BIT_MACID63_32_DROP_8821C(x)                                           \
+	(((x) & BIT_MASK_MACID63_32_DROP_8821C)                                \
+	 << BIT_SHIFT_MACID63_32_DROP_8821C)
+#define BITS_MACID63_32_DROP_8821C                                             \
+	(BIT_MASK_MACID63_32_DROP_8821C << BIT_SHIFT_MACID63_32_DROP_8821C)
+#define BIT_CLEAR_MACID63_32_DROP_8821C(x) ((x) & (~BITS_MACID63_32_DROP_8821C))
+#define BIT_GET_MACID63_32_DROP_8821C(x)                                       \
+	(((x) >> BIT_SHIFT_MACID63_32_DROP_8821C) &                            \
+	 BIT_MASK_MACID63_32_DROP_8821C)
+#define BIT_SET_MACID63_32_DROP_8821C(x, v)                                    \
+	(BIT_CLEAR_MACID63_32_DROP_8821C(x) | BIT_MACID63_32_DROP_8821C(v))
+
+/* 2 REG_MACID_DROP2_8821C */
+
+#define BIT_SHIFT_MACID95_64_DROP_8821C 0
+#define BIT_MASK_MACID95_64_DROP_8821C 0xffffffffL
+#define BIT_MACID95_64_DROP_8821C(x)                                           \
+	(((x) & BIT_MASK_MACID95_64_DROP_8821C)                                \
+	 << BIT_SHIFT_MACID95_64_DROP_8821C)
+#define BITS_MACID95_64_DROP_8821C                                             \
+	(BIT_MASK_MACID95_64_DROP_8821C << BIT_SHIFT_MACID95_64_DROP_8821C)
+#define BIT_CLEAR_MACID95_64_DROP_8821C(x) ((x) & (~BITS_MACID95_64_DROP_8821C))
+#define BIT_GET_MACID95_64_DROP_8821C(x)                                       \
+	(((x) >> BIT_SHIFT_MACID95_64_DROP_8821C) &                            \
+	 BIT_MASK_MACID95_64_DROP_8821C)
+#define BIT_SET_MACID95_64_DROP_8821C(x, v)                                    \
+	(BIT_CLEAR_MACID95_64_DROP_8821C(x) | BIT_MACID95_64_DROP_8821C(v))
+
+/* 2 REG_MACID_DROP3_8821C */
+
+#define BIT_SHIFT_MACID127_96_DROP_8821C 0
+#define BIT_MASK_MACID127_96_DROP_8821C 0xffffffffL
+#define BIT_MACID127_96_DROP_8821C(x)                                          \
+	(((x) & BIT_MASK_MACID127_96_DROP_8821C)                               \
+	 << BIT_SHIFT_MACID127_96_DROP_8821C)
+#define BITS_MACID127_96_DROP_8821C                                            \
+	(BIT_MASK_MACID127_96_DROP_8821C << BIT_SHIFT_MACID127_96_DROP_8821C)
+#define BIT_CLEAR_MACID127_96_DROP_8821C(x)                                    \
+	((x) & (~BITS_MACID127_96_DROP_8821C))
+#define BIT_GET_MACID127_96_DROP_8821C(x)                                      \
+	(((x) >> BIT_SHIFT_MACID127_96_DROP_8821C) &                           \
+	 BIT_MASK_MACID127_96_DROP_8821C)
+#define BIT_SET_MACID127_96_DROP_8821C(x, v)                                   \
+	(BIT_CLEAR_MACID127_96_DROP_8821C(x) | BIT_MACID127_96_DROP_8821C(v))
+
+/* 2 REG_R_MACID_RELEASE_SUCCESS_0_8821C */
+
+#define BIT_SHIFT_R_MACID_RELEASE_SUCCESS_0_8821C 0
+#define BIT_MASK_R_MACID_RELEASE_SUCCESS_0_8821C 0xffffffffL
+#define BIT_R_MACID_RELEASE_SUCCESS_0_8821C(x)                                 \
+	(((x) & BIT_MASK_R_MACID_RELEASE_SUCCESS_0_8821C)                      \
+	 << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_0_8821C)
+#define BITS_R_MACID_RELEASE_SUCCESS_0_8821C                                   \
+	(BIT_MASK_R_MACID_RELEASE_SUCCESS_0_8821C                              \
+	 << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_0_8821C)
+#define BIT_CLEAR_R_MACID_RELEASE_SUCCESS_0_8821C(x)                           \
+	((x) & (~BITS_R_MACID_RELEASE_SUCCESS_0_8821C))
+#define BIT_GET_R_MACID_RELEASE_SUCCESS_0_8821C(x)                             \
+	(((x) >> BIT_SHIFT_R_MACID_RELEASE_SUCCESS_0_8821C) &                  \
+	 BIT_MASK_R_MACID_RELEASE_SUCCESS_0_8821C)
+#define BIT_SET_R_MACID_RELEASE_SUCCESS_0_8821C(x, v)                          \
+	(BIT_CLEAR_R_MACID_RELEASE_SUCCESS_0_8821C(x) |                        \
+	 BIT_R_MACID_RELEASE_SUCCESS_0_8821C(v))
+
+/* 2 REG_R_MACID_RELEASE_SUCCESS_1_8821C */
+
+#define BIT_SHIFT_R_MACID_RELEASE_SUCCESS_1_8821C 0
+#define BIT_MASK_R_MACID_RELEASE_SUCCESS_1_8821C 0xffffffffL
+#define BIT_R_MACID_RELEASE_SUCCESS_1_8821C(x)                                 \
+	(((x) & BIT_MASK_R_MACID_RELEASE_SUCCESS_1_8821C)                      \
+	 << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_1_8821C)
+#define BITS_R_MACID_RELEASE_SUCCESS_1_8821C                                   \
+	(BIT_MASK_R_MACID_RELEASE_SUCCESS_1_8821C                              \
+	 << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_1_8821C)
+#define BIT_CLEAR_R_MACID_RELEASE_SUCCESS_1_8821C(x)                           \
+	((x) & (~BITS_R_MACID_RELEASE_SUCCESS_1_8821C))
+#define BIT_GET_R_MACID_RELEASE_SUCCESS_1_8821C(x)                             \
+	(((x) >> BIT_SHIFT_R_MACID_RELEASE_SUCCESS_1_8821C) &                  \
+	 BIT_MASK_R_MACID_RELEASE_SUCCESS_1_8821C)
+#define BIT_SET_R_MACID_RELEASE_SUCCESS_1_8821C(x, v)                          \
+	(BIT_CLEAR_R_MACID_RELEASE_SUCCESS_1_8821C(x) |                        \
+	 BIT_R_MACID_RELEASE_SUCCESS_1_8821C(v))
+
+/* 2 REG_R_MACID_RELEASE_SUCCESS_2_8821C */
+
+#define BIT_SHIFT_R_MACID_RELEASE_SUCCESS_2_8821C 0
+#define BIT_MASK_R_MACID_RELEASE_SUCCESS_2_8821C 0xffffffffL
+#define BIT_R_MACID_RELEASE_SUCCESS_2_8821C(x)                                 \
+	(((x) & BIT_MASK_R_MACID_RELEASE_SUCCESS_2_8821C)                      \
+	 << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_2_8821C)
+#define BITS_R_MACID_RELEASE_SUCCESS_2_8821C                                   \
+	(BIT_MASK_R_MACID_RELEASE_SUCCESS_2_8821C                              \
+	 << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_2_8821C)
+#define BIT_CLEAR_R_MACID_RELEASE_SUCCESS_2_8821C(x)                           \
+	((x) & (~BITS_R_MACID_RELEASE_SUCCESS_2_8821C))
+#define BIT_GET_R_MACID_RELEASE_SUCCESS_2_8821C(x)                             \
+	(((x) >> BIT_SHIFT_R_MACID_RELEASE_SUCCESS_2_8821C) &                  \
+	 BIT_MASK_R_MACID_RELEASE_SUCCESS_2_8821C)
+#define BIT_SET_R_MACID_RELEASE_SUCCESS_2_8821C(x, v)                          \
+	(BIT_CLEAR_R_MACID_RELEASE_SUCCESS_2_8821C(x) |                        \
+	 BIT_R_MACID_RELEASE_SUCCESS_2_8821C(v))
+
+/* 2 REG_R_MACID_RELEASE_SUCCESS_3_8821C */
+
+#define BIT_SHIFT_R_MACID_RELEASE_SUCCESS_3_8821C 0
+#define BIT_MASK_R_MACID_RELEASE_SUCCESS_3_8821C 0xffffffffL
+#define BIT_R_MACID_RELEASE_SUCCESS_3_8821C(x)                                 \
+	(((x) & BIT_MASK_R_MACID_RELEASE_SUCCESS_3_8821C)                      \
+	 << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_3_8821C)
+#define BITS_R_MACID_RELEASE_SUCCESS_3_8821C                                   \
+	(BIT_MASK_R_MACID_RELEASE_SUCCESS_3_8821C                              \
+	 << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_3_8821C)
+#define BIT_CLEAR_R_MACID_RELEASE_SUCCESS_3_8821C(x)                           \
+	((x) & (~BITS_R_MACID_RELEASE_SUCCESS_3_8821C))
+#define BIT_GET_R_MACID_RELEASE_SUCCESS_3_8821C(x)                             \
+	(((x) >> BIT_SHIFT_R_MACID_RELEASE_SUCCESS_3_8821C) &                  \
+	 BIT_MASK_R_MACID_RELEASE_SUCCESS_3_8821C)
+#define BIT_SET_R_MACID_RELEASE_SUCCESS_3_8821C(x, v)                          \
+	(BIT_CLEAR_R_MACID_RELEASE_SUCCESS_3_8821C(x) |                        \
+	 BIT_R_MACID_RELEASE_SUCCESS_3_8821C(v))
+
+/* 2 REG_MGQ_FIFO_WRITE_POINTER_8821C */
+#define BIT_MGQ_FIFO_OV_8821C BIT(7)
+#define BIT_MGQ_FIFO_WPTR_ERROR_8821C BIT(6)
+#define BIT_EN_MGQ_FIFO_LIFETIME_8821C BIT(5)
+
+#define BIT_SHIFT_MGQ_FIFO_WPTR_8821C 0
+#define BIT_MASK_MGQ_FIFO_WPTR_8821C 0x1f
+#define BIT_MGQ_FIFO_WPTR_8821C(x)                                             \
+	(((x) & BIT_MASK_MGQ_FIFO_WPTR_8821C) << BIT_SHIFT_MGQ_FIFO_WPTR_8821C)
+#define BITS_MGQ_FIFO_WPTR_8821C                                               \
+	(BIT_MASK_MGQ_FIFO_WPTR_8821C << BIT_SHIFT_MGQ_FIFO_WPTR_8821C)
+#define BIT_CLEAR_MGQ_FIFO_WPTR_8821C(x) ((x) & (~BITS_MGQ_FIFO_WPTR_8821C))
+#define BIT_GET_MGQ_FIFO_WPTR_8821C(x)                                         \
+	(((x) >> BIT_SHIFT_MGQ_FIFO_WPTR_8821C) & BIT_MASK_MGQ_FIFO_WPTR_8821C)
+#define BIT_SET_MGQ_FIFO_WPTR_8821C(x, v)                                      \
+	(BIT_CLEAR_MGQ_FIFO_WPTR_8821C(x) | BIT_MGQ_FIFO_WPTR_8821C(v))
+
+/* 2 REG_MGQ_FIFO_READ_POINTER_8821C */
+
+#define BIT_SHIFT_MGQ_FIFO_SIZE_8821C 14
+#define BIT_MASK_MGQ_FIFO_SIZE_8821C 0x3
+#define BIT_MGQ_FIFO_SIZE_8821C(x)                                             \
+	(((x) & BIT_MASK_MGQ_FIFO_SIZE_8821C) << BIT_SHIFT_MGQ_FIFO_SIZE_8821C)
+#define BITS_MGQ_FIFO_SIZE_8821C                                               \
+	(BIT_MASK_MGQ_FIFO_SIZE_8821C << BIT_SHIFT_MGQ_FIFO_SIZE_8821C)
+#define BIT_CLEAR_MGQ_FIFO_SIZE_8821C(x) ((x) & (~BITS_MGQ_FIFO_SIZE_8821C))
+#define BIT_GET_MGQ_FIFO_SIZE_8821C(x)                                         \
+	(((x) >> BIT_SHIFT_MGQ_FIFO_SIZE_8821C) & BIT_MASK_MGQ_FIFO_SIZE_8821C)
+#define BIT_SET_MGQ_FIFO_SIZE_8821C(x, v)                                      \
+	(BIT_CLEAR_MGQ_FIFO_SIZE_8821C(x) | BIT_MGQ_FIFO_SIZE_8821C(v))
+
+#define BIT_MGQ_FIFO_PAUSE_8821C BIT(13)
+
+#define BIT_SHIFT_MGQ_FIFO_RPTR_8821C 8
+#define BIT_MASK_MGQ_FIFO_RPTR_8821C 0x1f
+#define BIT_MGQ_FIFO_RPTR_8821C(x)                                             \
+	(((x) & BIT_MASK_MGQ_FIFO_RPTR_8821C) << BIT_SHIFT_MGQ_FIFO_RPTR_8821C)
+#define BITS_MGQ_FIFO_RPTR_8821C                                               \
+	(BIT_MASK_MGQ_FIFO_RPTR_8821C << BIT_SHIFT_MGQ_FIFO_RPTR_8821C)
+#define BIT_CLEAR_MGQ_FIFO_RPTR_8821C(x) ((x) & (~BITS_MGQ_FIFO_RPTR_8821C))
+#define BIT_GET_MGQ_FIFO_RPTR_8821C(x)                                         \
+	(((x) >> BIT_SHIFT_MGQ_FIFO_RPTR_8821C) & BIT_MASK_MGQ_FIFO_RPTR_8821C)
+#define BIT_SET_MGQ_FIFO_RPTR_8821C(x, v)                                      \
+	(BIT_CLEAR_MGQ_FIFO_RPTR_8821C(x) | BIT_MGQ_FIFO_RPTR_8821C(v))
+
+/* 2 REG_MGQ_FIFO_ENABLE_8821C */
+#define BIT_MGQ_FIFO_EN_8821C BIT(15)
+
+#define BIT_SHIFT_MGQ_FIFO_PG_SIZE_8821C 12
+#define BIT_MASK_MGQ_FIFO_PG_SIZE_8821C 0x7
+#define BIT_MGQ_FIFO_PG_SIZE_8821C(x)                                          \
+	(((x) & BIT_MASK_MGQ_FIFO_PG_SIZE_8821C)                               \
+	 << BIT_SHIFT_MGQ_FIFO_PG_SIZE_8821C)
+#define BITS_MGQ_FIFO_PG_SIZE_8821C                                            \
+	(BIT_MASK_MGQ_FIFO_PG_SIZE_8821C << BIT_SHIFT_MGQ_FIFO_PG_SIZE_8821C)
+#define BIT_CLEAR_MGQ_FIFO_PG_SIZE_8821C(x)                                    \
+	((x) & (~BITS_MGQ_FIFO_PG_SIZE_8821C))
+#define BIT_GET_MGQ_FIFO_PG_SIZE_8821C(x)                                      \
+	(((x) >> BIT_SHIFT_MGQ_FIFO_PG_SIZE_8821C) &                           \
+	 BIT_MASK_MGQ_FIFO_PG_SIZE_8821C)
+#define BIT_SET_MGQ_FIFO_PG_SIZE_8821C(x, v)                                   \
+	(BIT_CLEAR_MGQ_FIFO_PG_SIZE_8821C(x) | BIT_MGQ_FIFO_PG_SIZE_8821C(v))
+
+#define BIT_SHIFT_MGQ_FIFO_START_PG_8821C 0
+#define BIT_MASK_MGQ_FIFO_START_PG_8821C 0xfff
+#define BIT_MGQ_FIFO_START_PG_8821C(x)                                         \
+	(((x) & BIT_MASK_MGQ_FIFO_START_PG_8821C)                              \
+	 << BIT_SHIFT_MGQ_FIFO_START_PG_8821C)
+#define BITS_MGQ_FIFO_START_PG_8821C                                           \
+	(BIT_MASK_MGQ_FIFO_START_PG_8821C << BIT_SHIFT_MGQ_FIFO_START_PG_8821C)
+#define BIT_CLEAR_MGQ_FIFO_START_PG_8821C(x)                                   \
+	((x) & (~BITS_MGQ_FIFO_START_PG_8821C))
+#define BIT_GET_MGQ_FIFO_START_PG_8821C(x)                                     \
+	(((x) >> BIT_SHIFT_MGQ_FIFO_START_PG_8821C) &                          \
+	 BIT_MASK_MGQ_FIFO_START_PG_8821C)
+#define BIT_SET_MGQ_FIFO_START_PG_8821C(x, v)                                  \
+	(BIT_CLEAR_MGQ_FIFO_START_PG_8821C(x) | BIT_MGQ_FIFO_START_PG_8821C(v))
+
+/* 2 REG_MGQ_FIFO_RELEASE_INT_MASK_8821C */
+
+#define BIT_SHIFT_MGQ_FIFO_REL_INT_MASK_8821C 0
+#define BIT_MASK_MGQ_FIFO_REL_INT_MASK_8821C 0xffff
+#define BIT_MGQ_FIFO_REL_INT_MASK_8821C(x)                                     \
+	(((x) & BIT_MASK_MGQ_FIFO_REL_INT_MASK_8821C)                          \
+	 << BIT_SHIFT_MGQ_FIFO_REL_INT_MASK_8821C)
+#define BITS_MGQ_FIFO_REL_INT_MASK_8821C                                       \
+	(BIT_MASK_MGQ_FIFO_REL_INT_MASK_8821C                                  \
+	 << BIT_SHIFT_MGQ_FIFO_REL_INT_MASK_8821C)
+#define BIT_CLEAR_MGQ_FIFO_REL_INT_MASK_8821C(x)                               \
+	((x) & (~BITS_MGQ_FIFO_REL_INT_MASK_8821C))
+#define BIT_GET_MGQ_FIFO_REL_INT_MASK_8821C(x)                                 \
+	(((x) >> BIT_SHIFT_MGQ_FIFO_REL_INT_MASK_8821C) &                      \
+	 BIT_MASK_MGQ_FIFO_REL_INT_MASK_8821C)
+#define BIT_SET_MGQ_FIFO_REL_INT_MASK_8821C(x, v)                              \
+	(BIT_CLEAR_MGQ_FIFO_REL_INT_MASK_8821C(x) |                            \
+	 BIT_MGQ_FIFO_REL_INT_MASK_8821C(v))
+
+/* 2 REG_MGQ_FIFO_RELEASE_INT_FLAG_8821C */
+
+#define BIT_SHIFT_MGQ_FIFO_REL_INT_FLAG_8821C 0
+#define BIT_MASK_MGQ_FIFO_REL_INT_FLAG_8821C 0xffff
+#define BIT_MGQ_FIFO_REL_INT_FLAG_8821C(x)                                     \
+	(((x) & BIT_MASK_MGQ_FIFO_REL_INT_FLAG_8821C)                          \
+	 << BIT_SHIFT_MGQ_FIFO_REL_INT_FLAG_8821C)
+#define BITS_MGQ_FIFO_REL_INT_FLAG_8821C                                       \
+	(BIT_MASK_MGQ_FIFO_REL_INT_FLAG_8821C                                  \
+	 << BIT_SHIFT_MGQ_FIFO_REL_INT_FLAG_8821C)
+#define BIT_CLEAR_MGQ_FIFO_REL_INT_FLAG_8821C(x)                               \
+	((x) & (~BITS_MGQ_FIFO_REL_INT_FLAG_8821C))
+#define BIT_GET_MGQ_FIFO_REL_INT_FLAG_8821C(x)                                 \
+	(((x) >> BIT_SHIFT_MGQ_FIFO_REL_INT_FLAG_8821C) &                      \
+	 BIT_MASK_MGQ_FIFO_REL_INT_FLAG_8821C)
+#define BIT_SET_MGQ_FIFO_REL_INT_FLAG_8821C(x, v)                              \
+	(BIT_CLEAR_MGQ_FIFO_REL_INT_FLAG_8821C(x) |                            \
+	 BIT_MGQ_FIFO_REL_INT_FLAG_8821C(v))
+
+/* 2 REG_MGQ_FIFO_VALID_MAP_8821C */
+
+#define BIT_SHIFT_MGQ_FIFO_PKT_VALID_MAP_8821C 0
+#define BIT_MASK_MGQ_FIFO_PKT_VALID_MAP_8821C 0xffff
+#define BIT_MGQ_FIFO_PKT_VALID_MAP_8821C(x)                                    \
+	(((x) & BIT_MASK_MGQ_FIFO_PKT_VALID_MAP_8821C)                         \
+	 << BIT_SHIFT_MGQ_FIFO_PKT_VALID_MAP_8821C)
+#define BITS_MGQ_FIFO_PKT_VALID_MAP_8821C                                      \
+	(BIT_MASK_MGQ_FIFO_PKT_VALID_MAP_8821C                                 \
+	 << BIT_SHIFT_MGQ_FIFO_PKT_VALID_MAP_8821C)
+#define BIT_CLEAR_MGQ_FIFO_PKT_VALID_MAP_8821C(x)                              \
+	((x) & (~BITS_MGQ_FIFO_PKT_VALID_MAP_8821C))
+#define BIT_GET_MGQ_FIFO_PKT_VALID_MAP_8821C(x)                                \
+	(((x) >> BIT_SHIFT_MGQ_FIFO_PKT_VALID_MAP_8821C) &                     \
+	 BIT_MASK_MGQ_FIFO_PKT_VALID_MAP_8821C)
+#define BIT_SET_MGQ_FIFO_PKT_VALID_MAP_8821C(x, v)                             \
+	(BIT_CLEAR_MGQ_FIFO_PKT_VALID_MAP_8821C(x) |                           \
+	 BIT_MGQ_FIFO_PKT_VALID_MAP_8821C(v))
+
+/* 2 REG_MGQ_FIFO_LIFETIME_8821C */
+
+#define BIT_SHIFT_MGQ_FIFO_LIFETIME_8821C 0
+#define BIT_MASK_MGQ_FIFO_LIFETIME_8821C 0xffff
+#define BIT_MGQ_FIFO_LIFETIME_8821C(x)                                         \
+	(((x) & BIT_MASK_MGQ_FIFO_LIFETIME_8821C)                              \
+	 << BIT_SHIFT_MGQ_FIFO_LIFETIME_8821C)
+#define BITS_MGQ_FIFO_LIFETIME_8821C                                           \
+	(BIT_MASK_MGQ_FIFO_LIFETIME_8821C << BIT_SHIFT_MGQ_FIFO_LIFETIME_8821C)
+#define BIT_CLEAR_MGQ_FIFO_LIFETIME_8821C(x)                                   \
+	((x) & (~BITS_MGQ_FIFO_LIFETIME_8821C))
+#define BIT_GET_MGQ_FIFO_LIFETIME_8821C(x)                                     \
+	(((x) >> BIT_SHIFT_MGQ_FIFO_LIFETIME_8821C) &                          \
+	 BIT_MASK_MGQ_FIFO_LIFETIME_8821C)
+#define BIT_SET_MGQ_FIFO_LIFETIME_8821C(x, v)                                  \
+	(BIT_CLEAR_MGQ_FIFO_LIFETIME_8821C(x) | BIT_MGQ_FIFO_LIFETIME_8821C(v))
+
+/* 2 REG_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8821C */
+
+#define BIT_SHIFT_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8821C 0
+#define BIT_MASK_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8821C 0x7f
+#define BIT_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8821C(x)                      \
+	(((x) & BIT_MASK_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8821C)           \
+	 << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8821C)
+#define BITS_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8821C                        \
+	(BIT_MASK_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8821C                   \
+	 << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8821C)
+#define BIT_CLEAR_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8821C(x)                \
+	((x) & (~BITS_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8821C))
+#define BIT_GET_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8821C(x)                  \
+	(((x) >> BIT_SHIFT_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8821C) &       \
+	 BIT_MASK_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8821C)
+#define BIT_SET_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8821C(x, v)               \
+	(BIT_CLEAR_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8821C(x) |             \
+	 BIT_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8821C(v))
+
+/* 2 REG_SHCUT_SETTING_8821C */
+
+/* 2 REG_SHCUT_LLC_ETH_TYPE0_8821C */
+
+/* 2 REG_SHCUT_LLC_ETH_TYPE1_8821C */
+
+/* 2 REG_SHCUT_LLC_OUI0_8821C */
+
+/* 2 REG_SHCUT_LLC_OUI1_8821C */
+
+/* 2 REG_SHCUT_LLC_OUI2_8821C */
+
+/* 2 REG_MU_TX_CTL_8821C */
+#define BIT_R_MU_P1_WAIT_STATE_EN_8821C BIT(16)
+
+#define BIT_SHIFT_R_MU_RL_8821C 12
+#define BIT_MASK_R_MU_RL_8821C 0xf
+#define BIT_R_MU_RL_8821C(x)                                                   \
+	(((x) & BIT_MASK_R_MU_RL_8821C) << BIT_SHIFT_R_MU_RL_8821C)
+#define BITS_R_MU_RL_8821C (BIT_MASK_R_MU_RL_8821C << BIT_SHIFT_R_MU_RL_8821C)
+#define BIT_CLEAR_R_MU_RL_8821C(x) ((x) & (~BITS_R_MU_RL_8821C))
+#define BIT_GET_R_MU_RL_8821C(x)                                               \
+	(((x) >> BIT_SHIFT_R_MU_RL_8821C) & BIT_MASK_R_MU_RL_8821C)
+#define BIT_SET_R_MU_RL_8821C(x, v)                                            \
+	(BIT_CLEAR_R_MU_RL_8821C(x) | BIT_R_MU_RL_8821C(v))
+
+#define BIT_R_FORCE_P1_RATEDOWN_8821C BIT(11)
+
+#define BIT_SHIFT_R_MU_TAB_SEL_8821C 8
+#define BIT_MASK_R_MU_TAB_SEL_8821C 0x7
+#define BIT_R_MU_TAB_SEL_8821C(x)                                              \
+	(((x) & BIT_MASK_R_MU_TAB_SEL_8821C) << BIT_SHIFT_R_MU_TAB_SEL_8821C)
+#define BITS_R_MU_TAB_SEL_8821C                                                \
+	(BIT_MASK_R_MU_TAB_SEL_8821C << BIT_SHIFT_R_MU_TAB_SEL_8821C)
+#define BIT_CLEAR_R_MU_TAB_SEL_8821C(x) ((x) & (~BITS_R_MU_TAB_SEL_8821C))
+#define BIT_GET_R_MU_TAB_SEL_8821C(x)                                          \
+	(((x) >> BIT_SHIFT_R_MU_TAB_SEL_8821C) & BIT_MASK_R_MU_TAB_SEL_8821C)
+#define BIT_SET_R_MU_TAB_SEL_8821C(x, v)                                       \
+	(BIT_CLEAR_R_MU_TAB_SEL_8821C(x) | BIT_R_MU_TAB_SEL_8821C(v))
+
+#define BIT_R_EN_MU_MIMO_8821C BIT(7)
+#define BIT_R_EN_REVERS_GTAB_8821C BIT(6)
+
+#define BIT_SHIFT_R_MU_TABLE_VALID_8821C 0
+#define BIT_MASK_R_MU_TABLE_VALID_8821C 0x3f
+#define BIT_R_MU_TABLE_VALID_8821C(x)                                          \
+	(((x) & BIT_MASK_R_MU_TABLE_VALID_8821C)                               \
+	 << BIT_SHIFT_R_MU_TABLE_VALID_8821C)
+#define BITS_R_MU_TABLE_VALID_8821C                                            \
+	(BIT_MASK_R_MU_TABLE_VALID_8821C << BIT_SHIFT_R_MU_TABLE_VALID_8821C)
+#define BIT_CLEAR_R_MU_TABLE_VALID_8821C(x)                                    \
+	((x) & (~BITS_R_MU_TABLE_VALID_8821C))
+#define BIT_GET_R_MU_TABLE_VALID_8821C(x)                                      \
+	(((x) >> BIT_SHIFT_R_MU_TABLE_VALID_8821C) &                           \
+	 BIT_MASK_R_MU_TABLE_VALID_8821C)
+#define BIT_SET_R_MU_TABLE_VALID_8821C(x, v)                                   \
+	(BIT_CLEAR_R_MU_TABLE_VALID_8821C(x) | BIT_R_MU_TABLE_VALID_8821C(v))
+
+/* 2 REG_MU_STA_GID_VLD_8821C */
+
+#define BIT_SHIFT_R_MU_STA_GTAB_VALID_8821C 0
+#define BIT_MASK_R_MU_STA_GTAB_VALID_8821C 0xffffffffL
+#define BIT_R_MU_STA_GTAB_VALID_8821C(x)                                       \
+	(((x) & BIT_MASK_R_MU_STA_GTAB_VALID_8821C)                            \
+	 << BIT_SHIFT_R_MU_STA_GTAB_VALID_8821C)
+#define BITS_R_MU_STA_GTAB_VALID_8821C                                         \
+	(BIT_MASK_R_MU_STA_GTAB_VALID_8821C                                    \
+	 << BIT_SHIFT_R_MU_STA_GTAB_VALID_8821C)
+#define BIT_CLEAR_R_MU_STA_GTAB_VALID_8821C(x)                                 \
+	((x) & (~BITS_R_MU_STA_GTAB_VALID_8821C))
+#define BIT_GET_R_MU_STA_GTAB_VALID_8821C(x)                                   \
+	(((x) >> BIT_SHIFT_R_MU_STA_GTAB_VALID_8821C) &                        \
+	 BIT_MASK_R_MU_STA_GTAB_VALID_8821C)
+#define BIT_SET_R_MU_STA_GTAB_VALID_8821C(x, v)                                \
+	(BIT_CLEAR_R_MU_STA_GTAB_VALID_8821C(x) |                              \
+	 BIT_R_MU_STA_GTAB_VALID_8821C(v))
+
+/* 2 REG_MU_STA_USER_POS_INFO_8821C */
+
+#define BIT_SHIFT_R_MU_STA_GTAB_POSITION_L_8821C 0
+#define BIT_MASK_R_MU_STA_GTAB_POSITION_L_8821C 0xffffffffL
+#define BIT_R_MU_STA_GTAB_POSITION_L_8821C(x)                                  \
+	(((x) & BIT_MASK_R_MU_STA_GTAB_POSITION_L_8821C)                       \
+	 << BIT_SHIFT_R_MU_STA_GTAB_POSITION_L_8821C)
+#define BITS_R_MU_STA_GTAB_POSITION_L_8821C                                    \
+	(BIT_MASK_R_MU_STA_GTAB_POSITION_L_8821C                               \
+	 << BIT_SHIFT_R_MU_STA_GTAB_POSITION_L_8821C)
+#define BIT_CLEAR_R_MU_STA_GTAB_POSITION_L_8821C(x)                            \
+	((x) & (~BITS_R_MU_STA_GTAB_POSITION_L_8821C))
+#define BIT_GET_R_MU_STA_GTAB_POSITION_L_8821C(x)                              \
+	(((x) >> BIT_SHIFT_R_MU_STA_GTAB_POSITION_L_8821C) &                   \
+	 BIT_MASK_R_MU_STA_GTAB_POSITION_L_8821C)
+#define BIT_SET_R_MU_STA_GTAB_POSITION_L_8821C(x, v)                           \
+	(BIT_CLEAR_R_MU_STA_GTAB_POSITION_L_8821C(x) |                         \
+	 BIT_R_MU_STA_GTAB_POSITION_L_8821C(v))
+
+/* 2 REG_MU_STA_USER_POS_INFO_H_8821C */
+
+#define BIT_SHIFT_R_MU_STA_GTAB_POSITION_H_8821C 0
+#define BIT_MASK_R_MU_STA_GTAB_POSITION_H_8821C 0xffffffffL
+#define BIT_R_MU_STA_GTAB_POSITION_H_8821C(x)                                  \
+	(((x) & BIT_MASK_R_MU_STA_GTAB_POSITION_H_8821C)                       \
+	 << BIT_SHIFT_R_MU_STA_GTAB_POSITION_H_8821C)
+#define BITS_R_MU_STA_GTAB_POSITION_H_8821C                                    \
+	(BIT_MASK_R_MU_STA_GTAB_POSITION_H_8821C                               \
+	 << BIT_SHIFT_R_MU_STA_GTAB_POSITION_H_8821C)
+#define BIT_CLEAR_R_MU_STA_GTAB_POSITION_H_8821C(x)                            \
+	((x) & (~BITS_R_MU_STA_GTAB_POSITION_H_8821C))
+#define BIT_GET_R_MU_STA_GTAB_POSITION_H_8821C(x)                              \
+	(((x) >> BIT_SHIFT_R_MU_STA_GTAB_POSITION_H_8821C) &                   \
+	 BIT_MASK_R_MU_STA_GTAB_POSITION_H_8821C)
+#define BIT_SET_R_MU_STA_GTAB_POSITION_H_8821C(x, v)                           \
+	(BIT_CLEAR_R_MU_STA_GTAB_POSITION_H_8821C(x) |                         \
+	 BIT_R_MU_STA_GTAB_POSITION_H_8821C(v))
+
+/* 2 REG_MU_TRX_DBG_CNT_8821C */
+#define BIT_MU_DNGCNT_RST_8821C BIT(20)
+
+#define BIT_SHIFT_MU_DBGCNT_SEL_8821C 16
+#define BIT_MASK_MU_DBGCNT_SEL_8821C 0xf
+#define BIT_MU_DBGCNT_SEL_8821C(x)                                             \
+	(((x) & BIT_MASK_MU_DBGCNT_SEL_8821C) << BIT_SHIFT_MU_DBGCNT_SEL_8821C)
+#define BITS_MU_DBGCNT_SEL_8821C                                               \
+	(BIT_MASK_MU_DBGCNT_SEL_8821C << BIT_SHIFT_MU_DBGCNT_SEL_8821C)
+#define BIT_CLEAR_MU_DBGCNT_SEL_8821C(x) ((x) & (~BITS_MU_DBGCNT_SEL_8821C))
+#define BIT_GET_MU_DBGCNT_SEL_8821C(x)                                         \
+	(((x) >> BIT_SHIFT_MU_DBGCNT_SEL_8821C) & BIT_MASK_MU_DBGCNT_SEL_8821C)
+#define BIT_SET_MU_DBGCNT_SEL_8821C(x, v)                                      \
+	(BIT_CLEAR_MU_DBGCNT_SEL_8821C(x) | BIT_MU_DBGCNT_SEL_8821C(v))
+
+#define BIT_SHIFT_MU_DNGCNT_8821C 0
+#define BIT_MASK_MU_DNGCNT_8821C 0xffff
+#define BIT_MU_DNGCNT_8821C(x)                                                 \
+	(((x) & BIT_MASK_MU_DNGCNT_8821C) << BIT_SHIFT_MU_DNGCNT_8821C)
+#define BITS_MU_DNGCNT_8821C                                                   \
+	(BIT_MASK_MU_DNGCNT_8821C << BIT_SHIFT_MU_DNGCNT_8821C)
+#define BIT_CLEAR_MU_DNGCNT_8821C(x) ((x) & (~BITS_MU_DNGCNT_8821C))
+#define BIT_GET_MU_DNGCNT_8821C(x)                                             \
+	(((x) >> BIT_SHIFT_MU_DNGCNT_8821C) & BIT_MASK_MU_DNGCNT_8821C)
+#define BIT_SET_MU_DNGCNT_8821C(x, v)                                          \
+	(BIT_CLEAR_MU_DNGCNT_8821C(x) | BIT_MU_DNGCNT_8821C(v))
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_EDCA_VO_PARAM_8821C */
+
+#define BIT_SHIFT_TXOPLIMIT_8821C 16
+#define BIT_MASK_TXOPLIMIT_8821C 0x7ff
+#define BIT_TXOPLIMIT_8821C(x)                                                 \
+	(((x) & BIT_MASK_TXOPLIMIT_8821C) << BIT_SHIFT_TXOPLIMIT_8821C)
+#define BITS_TXOPLIMIT_8821C                                                   \
+	(BIT_MASK_TXOPLIMIT_8821C << BIT_SHIFT_TXOPLIMIT_8821C)
+#define BIT_CLEAR_TXOPLIMIT_8821C(x) ((x) & (~BITS_TXOPLIMIT_8821C))
+#define BIT_GET_TXOPLIMIT_8821C(x)                                             \
+	(((x) >> BIT_SHIFT_TXOPLIMIT_8821C) & BIT_MASK_TXOPLIMIT_8821C)
+#define BIT_SET_TXOPLIMIT_8821C(x, v)                                          \
+	(BIT_CLEAR_TXOPLIMIT_8821C(x) | BIT_TXOPLIMIT_8821C(v))
+
+#define BIT_SHIFT_CW_8821C 8
+#define BIT_MASK_CW_8821C 0xff
+#define BIT_CW_8821C(x) (((x) & BIT_MASK_CW_8821C) << BIT_SHIFT_CW_8821C)
+#define BITS_CW_8821C (BIT_MASK_CW_8821C << BIT_SHIFT_CW_8821C)
+#define BIT_CLEAR_CW_8821C(x) ((x) & (~BITS_CW_8821C))
+#define BIT_GET_CW_8821C(x) (((x) >> BIT_SHIFT_CW_8821C) & BIT_MASK_CW_8821C)
+#define BIT_SET_CW_8821C(x, v) (BIT_CLEAR_CW_8821C(x) | BIT_CW_8821C(v))
+
+#define BIT_SHIFT_AIFS_8821C 0
+#define BIT_MASK_AIFS_8821C 0xff
+#define BIT_AIFS_8821C(x) (((x) & BIT_MASK_AIFS_8821C) << BIT_SHIFT_AIFS_8821C)
+#define BITS_AIFS_8821C (BIT_MASK_AIFS_8821C << BIT_SHIFT_AIFS_8821C)
+#define BIT_CLEAR_AIFS_8821C(x) ((x) & (~BITS_AIFS_8821C))
+#define BIT_GET_AIFS_8821C(x)                                                  \
+	(((x) >> BIT_SHIFT_AIFS_8821C) & BIT_MASK_AIFS_8821C)
+#define BIT_SET_AIFS_8821C(x, v) (BIT_CLEAR_AIFS_8821C(x) | BIT_AIFS_8821C(v))
+
+/* 2 REG_EDCA_VI_PARAM_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+#define BIT_SHIFT_TXOPLIMIT_8821C 16
+#define BIT_MASK_TXOPLIMIT_8821C 0x7ff
+#define BIT_TXOPLIMIT_8821C(x)                                                 \
+	(((x) & BIT_MASK_TXOPLIMIT_8821C) << BIT_SHIFT_TXOPLIMIT_8821C)
+#define BITS_TXOPLIMIT_8821C                                                   \
+	(BIT_MASK_TXOPLIMIT_8821C << BIT_SHIFT_TXOPLIMIT_8821C)
+#define BIT_CLEAR_TXOPLIMIT_8821C(x) ((x) & (~BITS_TXOPLIMIT_8821C))
+#define BIT_GET_TXOPLIMIT_8821C(x)                                             \
+	(((x) >> BIT_SHIFT_TXOPLIMIT_8821C) & BIT_MASK_TXOPLIMIT_8821C)
+#define BIT_SET_TXOPLIMIT_8821C(x, v)                                          \
+	(BIT_CLEAR_TXOPLIMIT_8821C(x) | BIT_TXOPLIMIT_8821C(v))
+
+#define BIT_SHIFT_CW_8821C 8
+#define BIT_MASK_CW_8821C 0xff
+#define BIT_CW_8821C(x) (((x) & BIT_MASK_CW_8821C) << BIT_SHIFT_CW_8821C)
+#define BITS_CW_8821C (BIT_MASK_CW_8821C << BIT_SHIFT_CW_8821C)
+#define BIT_CLEAR_CW_8821C(x) ((x) & (~BITS_CW_8821C))
+#define BIT_GET_CW_8821C(x) (((x) >> BIT_SHIFT_CW_8821C) & BIT_MASK_CW_8821C)
+#define BIT_SET_CW_8821C(x, v) (BIT_CLEAR_CW_8821C(x) | BIT_CW_8821C(v))
+
+#define BIT_SHIFT_AIFS_8821C 0
+#define BIT_MASK_AIFS_8821C 0xff
+#define BIT_AIFS_8821C(x) (((x) & BIT_MASK_AIFS_8821C) << BIT_SHIFT_AIFS_8821C)
+#define BITS_AIFS_8821C (BIT_MASK_AIFS_8821C << BIT_SHIFT_AIFS_8821C)
+#define BIT_CLEAR_AIFS_8821C(x) ((x) & (~BITS_AIFS_8821C))
+#define BIT_GET_AIFS_8821C(x)                                                  \
+	(((x) >> BIT_SHIFT_AIFS_8821C) & BIT_MASK_AIFS_8821C)
+#define BIT_SET_AIFS_8821C(x, v) (BIT_CLEAR_AIFS_8821C(x) | BIT_AIFS_8821C(v))
+
+/* 2 REG_EDCA_BE_PARAM_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+#define BIT_SHIFT_TXOPLIMIT_8821C 16
+#define BIT_MASK_TXOPLIMIT_8821C 0x7ff
+#define BIT_TXOPLIMIT_8821C(x)                                                 \
+	(((x) & BIT_MASK_TXOPLIMIT_8821C) << BIT_SHIFT_TXOPLIMIT_8821C)
+#define BITS_TXOPLIMIT_8821C                                                   \
+	(BIT_MASK_TXOPLIMIT_8821C << BIT_SHIFT_TXOPLIMIT_8821C)
+#define BIT_CLEAR_TXOPLIMIT_8821C(x) ((x) & (~BITS_TXOPLIMIT_8821C))
+#define BIT_GET_TXOPLIMIT_8821C(x)                                             \
+	(((x) >> BIT_SHIFT_TXOPLIMIT_8821C) & BIT_MASK_TXOPLIMIT_8821C)
+#define BIT_SET_TXOPLIMIT_8821C(x, v)                                          \
+	(BIT_CLEAR_TXOPLIMIT_8821C(x) | BIT_TXOPLIMIT_8821C(v))
+
+#define BIT_SHIFT_CW_8821C 8
+#define BIT_MASK_CW_8821C 0xff
+#define BIT_CW_8821C(x) (((x) & BIT_MASK_CW_8821C) << BIT_SHIFT_CW_8821C)
+#define BITS_CW_8821C (BIT_MASK_CW_8821C << BIT_SHIFT_CW_8821C)
+#define BIT_CLEAR_CW_8821C(x) ((x) & (~BITS_CW_8821C))
+#define BIT_GET_CW_8821C(x) (((x) >> BIT_SHIFT_CW_8821C) & BIT_MASK_CW_8821C)
+#define BIT_SET_CW_8821C(x, v) (BIT_CLEAR_CW_8821C(x) | BIT_CW_8821C(v))
+
+#define BIT_SHIFT_AIFS_8821C 0
+#define BIT_MASK_AIFS_8821C 0xff
+#define BIT_AIFS_8821C(x) (((x) & BIT_MASK_AIFS_8821C) << BIT_SHIFT_AIFS_8821C)
+#define BITS_AIFS_8821C (BIT_MASK_AIFS_8821C << BIT_SHIFT_AIFS_8821C)
+#define BIT_CLEAR_AIFS_8821C(x) ((x) & (~BITS_AIFS_8821C))
+#define BIT_GET_AIFS_8821C(x)                                                  \
+	(((x) >> BIT_SHIFT_AIFS_8821C) & BIT_MASK_AIFS_8821C)
+#define BIT_SET_AIFS_8821C(x, v) (BIT_CLEAR_AIFS_8821C(x) | BIT_AIFS_8821C(v))
+
+/* 2 REG_EDCA_BK_PARAM_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+#define BIT_SHIFT_TXOPLIMIT_8821C 16
+#define BIT_MASK_TXOPLIMIT_8821C 0x7ff
+#define BIT_TXOPLIMIT_8821C(x)                                                 \
+	(((x) & BIT_MASK_TXOPLIMIT_8821C) << BIT_SHIFT_TXOPLIMIT_8821C)
+#define BITS_TXOPLIMIT_8821C                                                   \
+	(BIT_MASK_TXOPLIMIT_8821C << BIT_SHIFT_TXOPLIMIT_8821C)
+#define BIT_CLEAR_TXOPLIMIT_8821C(x) ((x) & (~BITS_TXOPLIMIT_8821C))
+#define BIT_GET_TXOPLIMIT_8821C(x)                                             \
+	(((x) >> BIT_SHIFT_TXOPLIMIT_8821C) & BIT_MASK_TXOPLIMIT_8821C)
+#define BIT_SET_TXOPLIMIT_8821C(x, v)                                          \
+	(BIT_CLEAR_TXOPLIMIT_8821C(x) | BIT_TXOPLIMIT_8821C(v))
+
+#define BIT_SHIFT_CW_8821C 8
+#define BIT_MASK_CW_8821C 0xff
+#define BIT_CW_8821C(x) (((x) & BIT_MASK_CW_8821C) << BIT_SHIFT_CW_8821C)
+#define BITS_CW_8821C (BIT_MASK_CW_8821C << BIT_SHIFT_CW_8821C)
+#define BIT_CLEAR_CW_8821C(x) ((x) & (~BITS_CW_8821C))
+#define BIT_GET_CW_8821C(x) (((x) >> BIT_SHIFT_CW_8821C) & BIT_MASK_CW_8821C)
+#define BIT_SET_CW_8821C(x, v) (BIT_CLEAR_CW_8821C(x) | BIT_CW_8821C(v))
+
+#define BIT_SHIFT_AIFS_8821C 0
+#define BIT_MASK_AIFS_8821C 0xff
+#define BIT_AIFS_8821C(x) (((x) & BIT_MASK_AIFS_8821C) << BIT_SHIFT_AIFS_8821C)
+#define BITS_AIFS_8821C (BIT_MASK_AIFS_8821C << BIT_SHIFT_AIFS_8821C)
+#define BIT_CLEAR_AIFS_8821C(x) ((x) & (~BITS_AIFS_8821C))
+#define BIT_GET_AIFS_8821C(x)                                                  \
+	(((x) >> BIT_SHIFT_AIFS_8821C) & BIT_MASK_AIFS_8821C)
+#define BIT_SET_AIFS_8821C(x, v) (BIT_CLEAR_AIFS_8821C(x) | BIT_AIFS_8821C(v))
+
+/* 2 REG_BCNTCFG_8821C */
+
+#define BIT_SHIFT_BCNCW_MAX_8821C 12
+#define BIT_MASK_BCNCW_MAX_8821C 0xf
+#define BIT_BCNCW_MAX_8821C(x)                                                 \
+	(((x) & BIT_MASK_BCNCW_MAX_8821C) << BIT_SHIFT_BCNCW_MAX_8821C)
+#define BITS_BCNCW_MAX_8821C                                                   \
+	(BIT_MASK_BCNCW_MAX_8821C << BIT_SHIFT_BCNCW_MAX_8821C)
+#define BIT_CLEAR_BCNCW_MAX_8821C(x) ((x) & (~BITS_BCNCW_MAX_8821C))
+#define BIT_GET_BCNCW_MAX_8821C(x)                                             \
+	(((x) >> BIT_SHIFT_BCNCW_MAX_8821C) & BIT_MASK_BCNCW_MAX_8821C)
+#define BIT_SET_BCNCW_MAX_8821C(x, v)                                          \
+	(BIT_CLEAR_BCNCW_MAX_8821C(x) | BIT_BCNCW_MAX_8821C(v))
+
+#define BIT_SHIFT_BCNCW_MIN_8821C 8
+#define BIT_MASK_BCNCW_MIN_8821C 0xf
+#define BIT_BCNCW_MIN_8821C(x)                                                 \
+	(((x) & BIT_MASK_BCNCW_MIN_8821C) << BIT_SHIFT_BCNCW_MIN_8821C)
+#define BITS_BCNCW_MIN_8821C                                                   \
+	(BIT_MASK_BCNCW_MIN_8821C << BIT_SHIFT_BCNCW_MIN_8821C)
+#define BIT_CLEAR_BCNCW_MIN_8821C(x) ((x) & (~BITS_BCNCW_MIN_8821C))
+#define BIT_GET_BCNCW_MIN_8821C(x)                                             \
+	(((x) >> BIT_SHIFT_BCNCW_MIN_8821C) & BIT_MASK_BCNCW_MIN_8821C)
+#define BIT_SET_BCNCW_MIN_8821C(x, v)                                          \
+	(BIT_CLEAR_BCNCW_MIN_8821C(x) | BIT_BCNCW_MIN_8821C(v))
+
+#define BIT_SHIFT_BCNIFS_8821C 0
+#define BIT_MASK_BCNIFS_8821C 0xff
+#define BIT_BCNIFS_8821C(x)                                                    \
+	(((x) & BIT_MASK_BCNIFS_8821C) << BIT_SHIFT_BCNIFS_8821C)
+#define BITS_BCNIFS_8821C (BIT_MASK_BCNIFS_8821C << BIT_SHIFT_BCNIFS_8821C)
+#define BIT_CLEAR_BCNIFS_8821C(x) ((x) & (~BITS_BCNIFS_8821C))
+#define BIT_GET_BCNIFS_8821C(x)                                                \
+	(((x) >> BIT_SHIFT_BCNIFS_8821C) & BIT_MASK_BCNIFS_8821C)
+#define BIT_SET_BCNIFS_8821C(x, v)                                             \
+	(BIT_CLEAR_BCNIFS_8821C(x) | BIT_BCNIFS_8821C(v))
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_PIFS_8821C */
+
+#define BIT_SHIFT_PIFS_8821C 0
+#define BIT_MASK_PIFS_8821C 0xff
+#define BIT_PIFS_8821C(x) (((x) & BIT_MASK_PIFS_8821C) << BIT_SHIFT_PIFS_8821C)
+#define BITS_PIFS_8821C (BIT_MASK_PIFS_8821C << BIT_SHIFT_PIFS_8821C)
+#define BIT_CLEAR_PIFS_8821C(x) ((x) & (~BITS_PIFS_8821C))
+#define BIT_GET_PIFS_8821C(x)                                                  \
+	(((x) >> BIT_SHIFT_PIFS_8821C) & BIT_MASK_PIFS_8821C)
+#define BIT_SET_PIFS_8821C(x, v) (BIT_CLEAR_PIFS_8821C(x) | BIT_PIFS_8821C(v))
+
+/* 2 REG_RDG_PIFS_8821C */
+
+#define BIT_SHIFT_RDG_PIFS_8821C 0
+#define BIT_MASK_RDG_PIFS_8821C 0xff
+#define BIT_RDG_PIFS_8821C(x)                                                  \
+	(((x) & BIT_MASK_RDG_PIFS_8821C) << BIT_SHIFT_RDG_PIFS_8821C)
+#define BITS_RDG_PIFS_8821C                                                    \
+	(BIT_MASK_RDG_PIFS_8821C << BIT_SHIFT_RDG_PIFS_8821C)
+#define BIT_CLEAR_RDG_PIFS_8821C(x) ((x) & (~BITS_RDG_PIFS_8821C))
+#define BIT_GET_RDG_PIFS_8821C(x)                                              \
+	(((x) >> BIT_SHIFT_RDG_PIFS_8821C) & BIT_MASK_RDG_PIFS_8821C)
+#define BIT_SET_RDG_PIFS_8821C(x, v)                                           \
+	(BIT_CLEAR_RDG_PIFS_8821C(x) | BIT_RDG_PIFS_8821C(v))
+
+/* 2 REG_SIFS_8821C */
+
+#define BIT_SHIFT_SIFS_OFDM_TRX_8821C 24
+#define BIT_MASK_SIFS_OFDM_TRX_8821C 0xff
+#define BIT_SIFS_OFDM_TRX_8821C(x)                                             \
+	(((x) & BIT_MASK_SIFS_OFDM_TRX_8821C) << BIT_SHIFT_SIFS_OFDM_TRX_8821C)
+#define BITS_SIFS_OFDM_TRX_8821C                                               \
+	(BIT_MASK_SIFS_OFDM_TRX_8821C << BIT_SHIFT_SIFS_OFDM_TRX_8821C)
+#define BIT_CLEAR_SIFS_OFDM_TRX_8821C(x) ((x) & (~BITS_SIFS_OFDM_TRX_8821C))
+#define BIT_GET_SIFS_OFDM_TRX_8821C(x)                                         \
+	(((x) >> BIT_SHIFT_SIFS_OFDM_TRX_8821C) & BIT_MASK_SIFS_OFDM_TRX_8821C)
+#define BIT_SET_SIFS_OFDM_TRX_8821C(x, v)                                      \
+	(BIT_CLEAR_SIFS_OFDM_TRX_8821C(x) | BIT_SIFS_OFDM_TRX_8821C(v))
+
+#define BIT_SHIFT_SIFS_CCK_TRX_8821C 16
+#define BIT_MASK_SIFS_CCK_TRX_8821C 0xff
+#define BIT_SIFS_CCK_TRX_8821C(x)                                              \
+	(((x) & BIT_MASK_SIFS_CCK_TRX_8821C) << BIT_SHIFT_SIFS_CCK_TRX_8821C)
+#define BITS_SIFS_CCK_TRX_8821C                                                \
+	(BIT_MASK_SIFS_CCK_TRX_8821C << BIT_SHIFT_SIFS_CCK_TRX_8821C)
+#define BIT_CLEAR_SIFS_CCK_TRX_8821C(x) ((x) & (~BITS_SIFS_CCK_TRX_8821C))
+#define BIT_GET_SIFS_CCK_TRX_8821C(x)                                          \
+	(((x) >> BIT_SHIFT_SIFS_CCK_TRX_8821C) & BIT_MASK_SIFS_CCK_TRX_8821C)
+#define BIT_SET_SIFS_CCK_TRX_8821C(x, v)                                       \
+	(BIT_CLEAR_SIFS_CCK_TRX_8821C(x) | BIT_SIFS_CCK_TRX_8821C(v))
+
+#define BIT_SHIFT_SIFS_OFDM_CTX_8821C 8
+#define BIT_MASK_SIFS_OFDM_CTX_8821C 0xff
+#define BIT_SIFS_OFDM_CTX_8821C(x)                                             \
+	(((x) & BIT_MASK_SIFS_OFDM_CTX_8821C) << BIT_SHIFT_SIFS_OFDM_CTX_8821C)
+#define BITS_SIFS_OFDM_CTX_8821C                                               \
+	(BIT_MASK_SIFS_OFDM_CTX_8821C << BIT_SHIFT_SIFS_OFDM_CTX_8821C)
+#define BIT_CLEAR_SIFS_OFDM_CTX_8821C(x) ((x) & (~BITS_SIFS_OFDM_CTX_8821C))
+#define BIT_GET_SIFS_OFDM_CTX_8821C(x)                                         \
+	(((x) >> BIT_SHIFT_SIFS_OFDM_CTX_8821C) & BIT_MASK_SIFS_OFDM_CTX_8821C)
+#define BIT_SET_SIFS_OFDM_CTX_8821C(x, v)                                      \
+	(BIT_CLEAR_SIFS_OFDM_CTX_8821C(x) | BIT_SIFS_OFDM_CTX_8821C(v))
+
+#define BIT_SHIFT_SIFS_CCK_CTX_8821C 0
+#define BIT_MASK_SIFS_CCK_CTX_8821C 0xff
+#define BIT_SIFS_CCK_CTX_8821C(x)                                              \
+	(((x) & BIT_MASK_SIFS_CCK_CTX_8821C) << BIT_SHIFT_SIFS_CCK_CTX_8821C)
+#define BITS_SIFS_CCK_CTX_8821C                                                \
+	(BIT_MASK_SIFS_CCK_CTX_8821C << BIT_SHIFT_SIFS_CCK_CTX_8821C)
+#define BIT_CLEAR_SIFS_CCK_CTX_8821C(x) ((x) & (~BITS_SIFS_CCK_CTX_8821C))
+#define BIT_GET_SIFS_CCK_CTX_8821C(x)                                          \
+	(((x) >> BIT_SHIFT_SIFS_CCK_CTX_8821C) & BIT_MASK_SIFS_CCK_CTX_8821C)
+#define BIT_SET_SIFS_CCK_CTX_8821C(x, v)                                       \
+	(BIT_CLEAR_SIFS_CCK_CTX_8821C(x) | BIT_SIFS_CCK_CTX_8821C(v))
+
+/* 2 REG_TSFTR_SYN_OFFSET_8821C */
+
+#define BIT_SHIFT_TSFTR_SNC_OFFSET_8821C 0
+#define BIT_MASK_TSFTR_SNC_OFFSET_8821C 0xffff
+#define BIT_TSFTR_SNC_OFFSET_8821C(x)                                          \
+	(((x) & BIT_MASK_TSFTR_SNC_OFFSET_8821C)                               \
+	 << BIT_SHIFT_TSFTR_SNC_OFFSET_8821C)
+#define BITS_TSFTR_SNC_OFFSET_8821C                                            \
+	(BIT_MASK_TSFTR_SNC_OFFSET_8821C << BIT_SHIFT_TSFTR_SNC_OFFSET_8821C)
+#define BIT_CLEAR_TSFTR_SNC_OFFSET_8821C(x)                                    \
+	((x) & (~BITS_TSFTR_SNC_OFFSET_8821C))
+#define BIT_GET_TSFTR_SNC_OFFSET_8821C(x)                                      \
+	(((x) >> BIT_SHIFT_TSFTR_SNC_OFFSET_8821C) &                           \
+	 BIT_MASK_TSFTR_SNC_OFFSET_8821C)
+#define BIT_SET_TSFTR_SNC_OFFSET_8821C(x, v)                                   \
+	(BIT_CLEAR_TSFTR_SNC_OFFSET_8821C(x) | BIT_TSFTR_SNC_OFFSET_8821C(v))
+
+/* 2 REG_AGGR_BREAK_TIME_8821C */
+
+#define BIT_SHIFT_AGGR_BK_TIME_8821C 0
+#define BIT_MASK_AGGR_BK_TIME_8821C 0xff
+#define BIT_AGGR_BK_TIME_8821C(x)                                              \
+	(((x) & BIT_MASK_AGGR_BK_TIME_8821C) << BIT_SHIFT_AGGR_BK_TIME_8821C)
+#define BITS_AGGR_BK_TIME_8821C                                                \
+	(BIT_MASK_AGGR_BK_TIME_8821C << BIT_SHIFT_AGGR_BK_TIME_8821C)
+#define BIT_CLEAR_AGGR_BK_TIME_8821C(x) ((x) & (~BITS_AGGR_BK_TIME_8821C))
+#define BIT_GET_AGGR_BK_TIME_8821C(x)                                          \
+	(((x) >> BIT_SHIFT_AGGR_BK_TIME_8821C) & BIT_MASK_AGGR_BK_TIME_8821C)
+#define BIT_SET_AGGR_BK_TIME_8821C(x, v)                                       \
+	(BIT_CLEAR_AGGR_BK_TIME_8821C(x) | BIT_AGGR_BK_TIME_8821C(v))
+
+/* 2 REG_SLOT_8821C */
+
+#define BIT_SHIFT_SLOT_8821C 0
+#define BIT_MASK_SLOT_8821C 0xff
+#define BIT_SLOT_8821C(x) (((x) & BIT_MASK_SLOT_8821C) << BIT_SHIFT_SLOT_8821C)
+#define BITS_SLOT_8821C (BIT_MASK_SLOT_8821C << BIT_SHIFT_SLOT_8821C)
+#define BIT_CLEAR_SLOT_8821C(x) ((x) & (~BITS_SLOT_8821C))
+#define BIT_GET_SLOT_8821C(x)                                                  \
+	(((x) >> BIT_SHIFT_SLOT_8821C) & BIT_MASK_SLOT_8821C)
+#define BIT_SET_SLOT_8821C(x, v) (BIT_CLEAR_SLOT_8821C(x) | BIT_SLOT_8821C(v))
+
+/* 2 REG_NOA_ON_ERLY_TIME_8821C */
+
+#define BIT_SHIFT__NOA_ON_ERLY_TIME_8821C 0
+#define BIT_MASK__NOA_ON_ERLY_TIME_8821C 0xff
+#define BIT__NOA_ON_ERLY_TIME_8821C(x)                                         \
+	(((x) & BIT_MASK__NOA_ON_ERLY_TIME_8821C)                              \
+	 << BIT_SHIFT__NOA_ON_ERLY_TIME_8821C)
+#define BITS__NOA_ON_ERLY_TIME_8821C                                           \
+	(BIT_MASK__NOA_ON_ERLY_TIME_8821C << BIT_SHIFT__NOA_ON_ERLY_TIME_8821C)
+#define BIT_CLEAR__NOA_ON_ERLY_TIME_8821C(x)                                   \
+	((x) & (~BITS__NOA_ON_ERLY_TIME_8821C))
+#define BIT_GET__NOA_ON_ERLY_TIME_8821C(x)                                     \
+	(((x) >> BIT_SHIFT__NOA_ON_ERLY_TIME_8821C) &                          \
+	 BIT_MASK__NOA_ON_ERLY_TIME_8821C)
+#define BIT_SET__NOA_ON_ERLY_TIME_8821C(x, v)                                  \
+	(BIT_CLEAR__NOA_ON_ERLY_TIME_8821C(x) | BIT__NOA_ON_ERLY_TIME_8821C(v))
+
+/* 2 REG_NOA_OFF_ERLY_TIME_8821C */
+
+#define BIT_SHIFT__NOA_OFF_ERLY_TIME_8821C 0
+#define BIT_MASK__NOA_OFF_ERLY_TIME_8821C 0xff
+#define BIT__NOA_OFF_ERLY_TIME_8821C(x)                                        \
+	(((x) & BIT_MASK__NOA_OFF_ERLY_TIME_8821C)                             \
+	 << BIT_SHIFT__NOA_OFF_ERLY_TIME_8821C)
+#define BITS__NOA_OFF_ERLY_TIME_8821C                                          \
+	(BIT_MASK__NOA_OFF_ERLY_TIME_8821C                                     \
+	 << BIT_SHIFT__NOA_OFF_ERLY_TIME_8821C)
+#define BIT_CLEAR__NOA_OFF_ERLY_TIME_8821C(x)                                  \
+	((x) & (~BITS__NOA_OFF_ERLY_TIME_8821C))
+#define BIT_GET__NOA_OFF_ERLY_TIME_8821C(x)                                    \
+	(((x) >> BIT_SHIFT__NOA_OFF_ERLY_TIME_8821C) &                         \
+	 BIT_MASK__NOA_OFF_ERLY_TIME_8821C)
+#define BIT_SET__NOA_OFF_ERLY_TIME_8821C(x, v)                                 \
+	(BIT_CLEAR__NOA_OFF_ERLY_TIME_8821C(x) |                               \
+	 BIT__NOA_OFF_ERLY_TIME_8821C(v))
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_TX_PTCL_CTRL_8821C */
+#define BIT_DIS_EDCCA_8821C BIT(15)
+#define BIT_DIS_CCA_8821C BIT(14)
+#define BIT_LSIG_TXOP_TXCMD_NAV_8821C BIT(13)
+#define BIT_SIFS_BK_EN_8821C BIT(12)
+
+#define BIT_SHIFT_TXQ_NAV_MSK_8821C 8
+#define BIT_MASK_TXQ_NAV_MSK_8821C 0xf
+#define BIT_TXQ_NAV_MSK_8821C(x)                                               \
+	(((x) & BIT_MASK_TXQ_NAV_MSK_8821C) << BIT_SHIFT_TXQ_NAV_MSK_8821C)
+#define BITS_TXQ_NAV_MSK_8821C                                                 \
+	(BIT_MASK_TXQ_NAV_MSK_8821C << BIT_SHIFT_TXQ_NAV_MSK_8821C)
+#define BIT_CLEAR_TXQ_NAV_MSK_8821C(x) ((x) & (~BITS_TXQ_NAV_MSK_8821C))
+#define BIT_GET_TXQ_NAV_MSK_8821C(x)                                           \
+	(((x) >> BIT_SHIFT_TXQ_NAV_MSK_8821C) & BIT_MASK_TXQ_NAV_MSK_8821C)
+#define BIT_SET_TXQ_NAV_MSK_8821C(x, v)                                        \
+	(BIT_CLEAR_TXQ_NAV_MSK_8821C(x) | BIT_TXQ_NAV_MSK_8821C(v))
+
+#define BIT_DIS_CW_8821C BIT(7)
+#define BIT_NAV_END_TXOP_8821C BIT(6)
+#define BIT_RDG_END_TXOP_8821C BIT(5)
+#define BIT_AC_INBCN_HOLD_8821C BIT(4)
+#define BIT_MGTQ_TXOP_EN_8821C BIT(3)
+#define BIT_MGTQ_RTSMF_EN_8821C BIT(2)
+#define BIT_HIQ_RTSMF_EN_8821C BIT(1)
+#define BIT_BCN_RTSMF_EN_8821C BIT(0)
+
+/* 2 REG_TXPAUSE_8821C */
+#define BIT_STOP_BCN_HI_MGT_8821C BIT(7)
+#define BIT_MAC_STOPBCNQ_8821C BIT(6)
+#define BIT_MAC_STOPHIQ_8821C BIT(5)
+#define BIT_MAC_STOPMGQ_8821C BIT(4)
+#define BIT_MAC_STOPBK_8821C BIT(3)
+#define BIT_MAC_STOPBE_8821C BIT(2)
+#define BIT_MAC_STOPVI_8821C BIT(1)
+#define BIT_MAC_STOPVO_8821C BIT(0)
+
+/* 2 REG_DIS_TXREQ_CLR_8821C */
+#define BIT_DIS_BT_CCA_8821C BIT(7)
+#define BIT_DIS_TXREQ_CLR_HI_8821C BIT(5)
+#define BIT_DIS_TXREQ_CLR_MGQ_8821C BIT(4)
+#define BIT_DIS_TXREQ_CLR_VO_8821C BIT(3)
+#define BIT_DIS_TXREQ_CLR_VI_8821C BIT(2)
+#define BIT_DIS_TXREQ_CLR_BE_8821C BIT(1)
+#define BIT_DIS_TXREQ_CLR_BK_8821C BIT(0)
+
+/* 2 REG_RD_CTRL_8821C */
+#define BIT_EN_CLR_TXREQ_INCCA_8821C BIT(15)
+#define BIT_DIS_TX_OVER_BCNQ_8821C BIT(14)
+#define BIT_EN_BCNERR_INCCCA_8821C BIT(13)
+#define BIT_EDCCA_MSK_CNTDOWN_EN_8821C BIT(11)
+#define BIT_DIS_TXOP_CFE_8821C BIT(10)
+#define BIT_DIS_LSIG_CFE_8821C BIT(9)
+#define BIT_DIS_STBC_CFE_8821C BIT(8)
+#define BIT_BKQ_RD_INIT_EN_8821C BIT(7)
+#define BIT_BEQ_RD_INIT_EN_8821C BIT(6)
+#define BIT_VIQ_RD_INIT_EN_8821C BIT(5)
+#define BIT_VOQ_RD_INIT_EN_8821C BIT(4)
+#define BIT_BKQ_RD_RESP_EN_8821C BIT(3)
+#define BIT_BEQ_RD_RESP_EN_8821C BIT(2)
+#define BIT_VIQ_RD_RESP_EN_8821C BIT(1)
+#define BIT_VOQ_RD_RESP_EN_8821C BIT(0)
+
+/* 2 REG_MBSSID_CTRL_8821C */
+#define BIT_MBID_BCNQ7_EN_8821C BIT(7)
+#define BIT_MBID_BCNQ6_EN_8821C BIT(6)
+#define BIT_MBID_BCNQ5_EN_8821C BIT(5)
+#define BIT_MBID_BCNQ4_EN_8821C BIT(4)
+#define BIT_MBID_BCNQ3_EN_8821C BIT(3)
+#define BIT_MBID_BCNQ2_EN_8821C BIT(2)
+#define BIT_MBID_BCNQ1_EN_8821C BIT(1)
+#define BIT_MBID_BCNQ0_EN_8821C BIT(0)
+
+/* 2 REG_P2PPS_CTRL_8821C */
+#define BIT_P2P_CTW_ALLSTASLEEP_8821C BIT(7)
+#define BIT_P2P_OFF_DISTX_EN_8821C BIT(6)
+#define BIT_PWR_MGT_EN_8821C BIT(5)
+#define BIT_P2P_NOA1_EN_8821C BIT(2)
+#define BIT_P2P_NOA0_EN_8821C BIT(1)
+
+/* 2 REG_PKT_LIFETIME_CTRL_8821C */
+#define BIT_EN_P2P_CTWND1_8821C BIT(23)
+#define BIT_EN_BKF_CLR_TXREQ_8821C BIT(22)
+#define BIT_EN_TSFBIT32_RST_P2P_8821C BIT(21)
+#define BIT_EN_BCN_TX_BTCCA_8821C BIT(20)
+#define BIT_DIS_PKT_TX_ATIM_8821C BIT(19)
+#define BIT_DIS_BCN_DIS_CTN_8821C BIT(18)
+#define BIT_EN_NAVEND_RST_TXOP_8821C BIT(17)
+#define BIT_EN_FILTER_CCA_8821C BIT(16)
+
+#define BIT_SHIFT_CCA_FILTER_THRS_8821C 8
+#define BIT_MASK_CCA_FILTER_THRS_8821C 0xff
+#define BIT_CCA_FILTER_THRS_8821C(x)                                           \
+	(((x) & BIT_MASK_CCA_FILTER_THRS_8821C)                                \
+	 << BIT_SHIFT_CCA_FILTER_THRS_8821C)
+#define BITS_CCA_FILTER_THRS_8821C                                             \
+	(BIT_MASK_CCA_FILTER_THRS_8821C << BIT_SHIFT_CCA_FILTER_THRS_8821C)
+#define BIT_CLEAR_CCA_FILTER_THRS_8821C(x) ((x) & (~BITS_CCA_FILTER_THRS_8821C))
+#define BIT_GET_CCA_FILTER_THRS_8821C(x)                                       \
+	(((x) >> BIT_SHIFT_CCA_FILTER_THRS_8821C) &                            \
+	 BIT_MASK_CCA_FILTER_THRS_8821C)
+#define BIT_SET_CCA_FILTER_THRS_8821C(x, v)                                    \
+	(BIT_CLEAR_CCA_FILTER_THRS_8821C(x) | BIT_CCA_FILTER_THRS_8821C(v))
+
+#define BIT_SHIFT_EDCCA_THRS_8821C 0
+#define BIT_MASK_EDCCA_THRS_8821C 0xff
+#define BIT_EDCCA_THRS_8821C(x)                                                \
+	(((x) & BIT_MASK_EDCCA_THRS_8821C) << BIT_SHIFT_EDCCA_THRS_8821C)
+#define BITS_EDCCA_THRS_8821C                                                  \
+	(BIT_MASK_EDCCA_THRS_8821C << BIT_SHIFT_EDCCA_THRS_8821C)
+#define BIT_CLEAR_EDCCA_THRS_8821C(x) ((x) & (~BITS_EDCCA_THRS_8821C))
+#define BIT_GET_EDCCA_THRS_8821C(x)                                            \
+	(((x) >> BIT_SHIFT_EDCCA_THRS_8821C) & BIT_MASK_EDCCA_THRS_8821C)
+#define BIT_SET_EDCCA_THRS_8821C(x, v)                                         \
+	(BIT_CLEAR_EDCCA_THRS_8821C(x) | BIT_EDCCA_THRS_8821C(v))
+
+/* 2 REG_P2PPS_SPEC_STATE_8821C */
+#define BIT_SPEC_POWER_STATE_8821C BIT(7)
+#define BIT_SPEC_CTWINDOW_ON_8821C BIT(6)
+#define BIT_SPEC_BEACON_AREA_ON_8821C BIT(5)
+#define BIT_SPEC_CTWIN_EARLY_DISTX_8821C BIT(4)
+#define BIT_SPEC_NOA1_OFF_PERIOD_8821C BIT(3)
+#define BIT_SPEC_FORCE_DOZE1_8821C BIT(2)
+#define BIT_SPEC_NOA0_OFF_PERIOD_8821C BIT(1)
+#define BIT_SPEC_FORCE_DOZE0_8821C BIT(0)
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_BAR_TX_CTRL_8821C */
+
+/* 2 REG_P2PON_DIS_TXTIME_8821C */
+
+#define BIT_SHIFT_P2PON_DIS_TXTIME_8821C 0
+#define BIT_MASK_P2PON_DIS_TXTIME_8821C 0xff
+#define BIT_P2PON_DIS_TXTIME_8821C(x)                                          \
+	(((x) & BIT_MASK_P2PON_DIS_TXTIME_8821C)                               \
+	 << BIT_SHIFT_P2PON_DIS_TXTIME_8821C)
+#define BITS_P2PON_DIS_TXTIME_8821C                                            \
+	(BIT_MASK_P2PON_DIS_TXTIME_8821C << BIT_SHIFT_P2PON_DIS_TXTIME_8821C)
+#define BIT_CLEAR_P2PON_DIS_TXTIME_8821C(x)                                    \
+	((x) & (~BITS_P2PON_DIS_TXTIME_8821C))
+#define BIT_GET_P2PON_DIS_TXTIME_8821C(x)                                      \
+	(((x) >> BIT_SHIFT_P2PON_DIS_TXTIME_8821C) &                           \
+	 BIT_MASK_P2PON_DIS_TXTIME_8821C)
+#define BIT_SET_P2PON_DIS_TXTIME_8821C(x, v)                                   \
+	(BIT_CLEAR_P2PON_DIS_TXTIME_8821C(x) | BIT_P2PON_DIS_TXTIME_8821C(v))
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_TBTT_PROHIBIT_8821C */
+
+#define BIT_SHIFT_TBTT_HOLD_TIME_AP_8821C 8
+#define BIT_MASK_TBTT_HOLD_TIME_AP_8821C 0xfff
+#define BIT_TBTT_HOLD_TIME_AP_8821C(x)                                         \
+	(((x) & BIT_MASK_TBTT_HOLD_TIME_AP_8821C)                              \
+	 << BIT_SHIFT_TBTT_HOLD_TIME_AP_8821C)
+#define BITS_TBTT_HOLD_TIME_AP_8821C                                           \
+	(BIT_MASK_TBTT_HOLD_TIME_AP_8821C << BIT_SHIFT_TBTT_HOLD_TIME_AP_8821C)
+#define BIT_CLEAR_TBTT_HOLD_TIME_AP_8821C(x)                                   \
+	((x) & (~BITS_TBTT_HOLD_TIME_AP_8821C))
+#define BIT_GET_TBTT_HOLD_TIME_AP_8821C(x)                                     \
+	(((x) >> BIT_SHIFT_TBTT_HOLD_TIME_AP_8821C) &                          \
+	 BIT_MASK_TBTT_HOLD_TIME_AP_8821C)
+#define BIT_SET_TBTT_HOLD_TIME_AP_8821C(x, v)                                  \
+	(BIT_CLEAR_TBTT_HOLD_TIME_AP_8821C(x) | BIT_TBTT_HOLD_TIME_AP_8821C(v))
+
+#define BIT_SHIFT_TBTT_PROHIBIT_SETUP_8821C 0
+#define BIT_MASK_TBTT_PROHIBIT_SETUP_8821C 0xf
+#define BIT_TBTT_PROHIBIT_SETUP_8821C(x)                                       \
+	(((x) & BIT_MASK_TBTT_PROHIBIT_SETUP_8821C)                            \
+	 << BIT_SHIFT_TBTT_PROHIBIT_SETUP_8821C)
+#define BITS_TBTT_PROHIBIT_SETUP_8821C                                         \
+	(BIT_MASK_TBTT_PROHIBIT_SETUP_8821C                                    \
+	 << BIT_SHIFT_TBTT_PROHIBIT_SETUP_8821C)
+#define BIT_CLEAR_TBTT_PROHIBIT_SETUP_8821C(x)                                 \
+	((x) & (~BITS_TBTT_PROHIBIT_SETUP_8821C))
+#define BIT_GET_TBTT_PROHIBIT_SETUP_8821C(x)                                   \
+	(((x) >> BIT_SHIFT_TBTT_PROHIBIT_SETUP_8821C) &                        \
+	 BIT_MASK_TBTT_PROHIBIT_SETUP_8821C)
+#define BIT_SET_TBTT_PROHIBIT_SETUP_8821C(x, v)                                \
+	(BIT_CLEAR_TBTT_PROHIBIT_SETUP_8821C(x) |                              \
+	 BIT_TBTT_PROHIBIT_SETUP_8821C(v))
+
+/* 2 REG_P2PPS_STATE_8821C */
+#define BIT_POWER_STATE_8821C BIT(7)
+#define BIT_CTWINDOW_ON_8821C BIT(6)
+#define BIT_BEACON_AREA_ON_8821C BIT(5)
+#define BIT_CTWIN_EARLY_DISTX_8821C BIT(4)
+#define BIT_NOA1_OFF_PERIOD_8821C BIT(3)
+#define BIT_FORCE_DOZE1_8821C BIT(2)
+#define BIT_NOA0_OFF_PERIOD_8821C BIT(1)
+#define BIT_FORCE_DOZE0_8821C BIT(0)
+
+/* 2 REG_RD_NAV_NXT_8821C */
+
+#define BIT_SHIFT_RD_NAV_PROT_NXT_8821C 0
+#define BIT_MASK_RD_NAV_PROT_NXT_8821C 0xffff
+#define BIT_RD_NAV_PROT_NXT_8821C(x)                                           \
+	(((x) & BIT_MASK_RD_NAV_PROT_NXT_8821C)                                \
+	 << BIT_SHIFT_RD_NAV_PROT_NXT_8821C)
+#define BITS_RD_NAV_PROT_NXT_8821C                                             \
+	(BIT_MASK_RD_NAV_PROT_NXT_8821C << BIT_SHIFT_RD_NAV_PROT_NXT_8821C)
+#define BIT_CLEAR_RD_NAV_PROT_NXT_8821C(x) ((x) & (~BITS_RD_NAV_PROT_NXT_8821C))
+#define BIT_GET_RD_NAV_PROT_NXT_8821C(x)                                       \
+	(((x) >> BIT_SHIFT_RD_NAV_PROT_NXT_8821C) &                            \
+	 BIT_MASK_RD_NAV_PROT_NXT_8821C)
+#define BIT_SET_RD_NAV_PROT_NXT_8821C(x, v)                                    \
+	(BIT_CLEAR_RD_NAV_PROT_NXT_8821C(x) | BIT_RD_NAV_PROT_NXT_8821C(v))
+
+/* 2 REG_NAV_PROT_LEN_8821C */
+
+#define BIT_SHIFT_NAV_PROT_LEN_8821C 0
+#define BIT_MASK_NAV_PROT_LEN_8821C 0xffff
+#define BIT_NAV_PROT_LEN_8821C(x)                                              \
+	(((x) & BIT_MASK_NAV_PROT_LEN_8821C) << BIT_SHIFT_NAV_PROT_LEN_8821C)
+#define BITS_NAV_PROT_LEN_8821C                                                \
+	(BIT_MASK_NAV_PROT_LEN_8821C << BIT_SHIFT_NAV_PROT_LEN_8821C)
+#define BIT_CLEAR_NAV_PROT_LEN_8821C(x) ((x) & (~BITS_NAV_PROT_LEN_8821C))
+#define BIT_GET_NAV_PROT_LEN_8821C(x)                                          \
+	(((x) >> BIT_SHIFT_NAV_PROT_LEN_8821C) & BIT_MASK_NAV_PROT_LEN_8821C)
+#define BIT_SET_NAV_PROT_LEN_8821C(x, v)                                       \
+	(BIT_CLEAR_NAV_PROT_LEN_8821C(x) | BIT_NAV_PROT_LEN_8821C(v))
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_BCN_CTRL_8821C */
+#define BIT_DIS_RX_BSSID_FIT_8821C BIT(6)
+#define BIT_P0_EN_TXBCN_RPT_8821C BIT(5)
+#define BIT_DIS_TSF_UDT_8821C BIT(4)
+#define BIT_EN_BCN_FUNCTION_8821C BIT(3)
+#define BIT_P0_EN_RXBCN_RPT_8821C BIT(2)
+#define BIT_EN_P2P_CTWINDOW_8821C BIT(1)
+#define BIT_EN_P2P_BCNQ_AREA_8821C BIT(0)
+
+/* 2 REG_BCN_CTRL_CLINT0_8821C */
+#define BIT_CLI0_DIS_RX_BSSID_FIT_8821C BIT(6)
+#define BIT_CLI0_DIS_TSF_UDT_8821C BIT(4)
+#define BIT_CLI0_EN_BCN_FUNCTION_8821C BIT(3)
+#define BIT_CLI0_EN_RXBCN_RPT_8821C BIT(2)
+#define BIT_CLI0_ENP2P_CTWINDOW_8821C BIT(1)
+#define BIT_CLI0_ENP2P_BCNQ_AREA_8821C BIT(0)
+
+/* 2 REG_MBID_NUM_8821C */
+#define BIT_EN_PRE_DL_BEACON_8821C BIT(3)
+
+#define BIT_SHIFT_MBID_BCN_NUM_8821C 0
+#define BIT_MASK_MBID_BCN_NUM_8821C 0x7
+#define BIT_MBID_BCN_NUM_8821C(x)                                              \
+	(((x) & BIT_MASK_MBID_BCN_NUM_8821C) << BIT_SHIFT_MBID_BCN_NUM_8821C)
+#define BITS_MBID_BCN_NUM_8821C                                                \
+	(BIT_MASK_MBID_BCN_NUM_8821C << BIT_SHIFT_MBID_BCN_NUM_8821C)
+#define BIT_CLEAR_MBID_BCN_NUM_8821C(x) ((x) & (~BITS_MBID_BCN_NUM_8821C))
+#define BIT_GET_MBID_BCN_NUM_8821C(x)                                          \
+	(((x) >> BIT_SHIFT_MBID_BCN_NUM_8821C) & BIT_MASK_MBID_BCN_NUM_8821C)
+#define BIT_SET_MBID_BCN_NUM_8821C(x, v)                                       \
+	(BIT_CLEAR_MBID_BCN_NUM_8821C(x) | BIT_MBID_BCN_NUM_8821C(v))
+
+/* 2 REG_DUAL_TSF_RST_8821C */
+#define BIT_FREECNT_RST_8821C BIT(5)
+#define BIT_TSFTR_CLI3_RST_8821C BIT(4)
+#define BIT_TSFTR_CLI2_RST_8821C BIT(3)
+#define BIT_TSFTR_CLI1_RST_8821C BIT(2)
+#define BIT_TSFTR_CLI0_RST_8821C BIT(1)
+#define BIT_TSFTR_RST_8821C BIT(0)
+
+/* 2 REG_MBSSID_BCN_SPACE_8821C */
+
+#define BIT_SHIFT_BCN_TIMER_SEL_FWRD_8821C 28
+#define BIT_MASK_BCN_TIMER_SEL_FWRD_8821C 0x7
+#define BIT_BCN_TIMER_SEL_FWRD_8821C(x)                                        \
+	(((x) & BIT_MASK_BCN_TIMER_SEL_FWRD_8821C)                             \
+	 << BIT_SHIFT_BCN_TIMER_SEL_FWRD_8821C)
+#define BITS_BCN_TIMER_SEL_FWRD_8821C                                          \
+	(BIT_MASK_BCN_TIMER_SEL_FWRD_8821C                                     \
+	 << BIT_SHIFT_BCN_TIMER_SEL_FWRD_8821C)
+#define BIT_CLEAR_BCN_TIMER_SEL_FWRD_8821C(x)                                  \
+	((x) & (~BITS_BCN_TIMER_SEL_FWRD_8821C))
+#define BIT_GET_BCN_TIMER_SEL_FWRD_8821C(x)                                    \
+	(((x) >> BIT_SHIFT_BCN_TIMER_SEL_FWRD_8821C) &                         \
+	 BIT_MASK_BCN_TIMER_SEL_FWRD_8821C)
+#define BIT_SET_BCN_TIMER_SEL_FWRD_8821C(x, v)                                 \
+	(BIT_CLEAR_BCN_TIMER_SEL_FWRD_8821C(x) |                               \
+	 BIT_BCN_TIMER_SEL_FWRD_8821C(v))
+
+#define BIT_SHIFT_BCN_SPACE_CLINT0_8821C 16
+#define BIT_MASK_BCN_SPACE_CLINT0_8821C 0xfff
+#define BIT_BCN_SPACE_CLINT0_8821C(x)                                          \
+	(((x) & BIT_MASK_BCN_SPACE_CLINT0_8821C)                               \
+	 << BIT_SHIFT_BCN_SPACE_CLINT0_8821C)
+#define BITS_BCN_SPACE_CLINT0_8821C                                            \
+	(BIT_MASK_BCN_SPACE_CLINT0_8821C << BIT_SHIFT_BCN_SPACE_CLINT0_8821C)
+#define BIT_CLEAR_BCN_SPACE_CLINT0_8821C(x)                                    \
+	((x) & (~BITS_BCN_SPACE_CLINT0_8821C))
+#define BIT_GET_BCN_SPACE_CLINT0_8821C(x)                                      \
+	(((x) >> BIT_SHIFT_BCN_SPACE_CLINT0_8821C) &                           \
+	 BIT_MASK_BCN_SPACE_CLINT0_8821C)
+#define BIT_SET_BCN_SPACE_CLINT0_8821C(x, v)                                   \
+	(BIT_CLEAR_BCN_SPACE_CLINT0_8821C(x) | BIT_BCN_SPACE_CLINT0_8821C(v))
+
+#define BIT_SHIFT_BCN_SPACE0_8821C 0
+#define BIT_MASK_BCN_SPACE0_8821C 0xffff
+#define BIT_BCN_SPACE0_8821C(x)                                                \
+	(((x) & BIT_MASK_BCN_SPACE0_8821C) << BIT_SHIFT_BCN_SPACE0_8821C)
+#define BITS_BCN_SPACE0_8821C                                                  \
+	(BIT_MASK_BCN_SPACE0_8821C << BIT_SHIFT_BCN_SPACE0_8821C)
+#define BIT_CLEAR_BCN_SPACE0_8821C(x) ((x) & (~BITS_BCN_SPACE0_8821C))
+#define BIT_GET_BCN_SPACE0_8821C(x)                                            \
+	(((x) >> BIT_SHIFT_BCN_SPACE0_8821C) & BIT_MASK_BCN_SPACE0_8821C)
+#define BIT_SET_BCN_SPACE0_8821C(x, v)                                         \
+	(BIT_CLEAR_BCN_SPACE0_8821C(x) | BIT_BCN_SPACE0_8821C(v))
+
+/* 2 REG_DRVERLYINT_8821C */
+
+#define BIT_SHIFT_DRVERLYITV_8821C 0
+#define BIT_MASK_DRVERLYITV_8821C 0xff
+#define BIT_DRVERLYITV_8821C(x)                                                \
+	(((x) & BIT_MASK_DRVERLYITV_8821C) << BIT_SHIFT_DRVERLYITV_8821C)
+#define BITS_DRVERLYITV_8821C                                                  \
+	(BIT_MASK_DRVERLYITV_8821C << BIT_SHIFT_DRVERLYITV_8821C)
+#define BIT_CLEAR_DRVERLYITV_8821C(x) ((x) & (~BITS_DRVERLYITV_8821C))
+#define BIT_GET_DRVERLYITV_8821C(x)                                            \
+	(((x) >> BIT_SHIFT_DRVERLYITV_8821C) & BIT_MASK_DRVERLYITV_8821C)
+#define BIT_SET_DRVERLYITV_8821C(x, v)                                         \
+	(BIT_CLEAR_DRVERLYITV_8821C(x) | BIT_DRVERLYITV_8821C(v))
+
+/* 2 REG_BCNDMATIM_8821C */
+
+#define BIT_SHIFT_BCNDMATIM_8821C 0
+#define BIT_MASK_BCNDMATIM_8821C 0xff
+#define BIT_BCNDMATIM_8821C(x)                                                 \
+	(((x) & BIT_MASK_BCNDMATIM_8821C) << BIT_SHIFT_BCNDMATIM_8821C)
+#define BITS_BCNDMATIM_8821C                                                   \
+	(BIT_MASK_BCNDMATIM_8821C << BIT_SHIFT_BCNDMATIM_8821C)
+#define BIT_CLEAR_BCNDMATIM_8821C(x) ((x) & (~BITS_BCNDMATIM_8821C))
+#define BIT_GET_BCNDMATIM_8821C(x)                                             \
+	(((x) >> BIT_SHIFT_BCNDMATIM_8821C) & BIT_MASK_BCNDMATIM_8821C)
+#define BIT_SET_BCNDMATIM_8821C(x, v)                                          \
+	(BIT_CLEAR_BCNDMATIM_8821C(x) | BIT_BCNDMATIM_8821C(v))
+
+/* 2 REG_ATIMWND_8821C */
+
+#define BIT_SHIFT_ATIMWND0_8821C 0
+#define BIT_MASK_ATIMWND0_8821C 0xffff
+#define BIT_ATIMWND0_8821C(x)                                                  \
+	(((x) & BIT_MASK_ATIMWND0_8821C) << BIT_SHIFT_ATIMWND0_8821C)
+#define BITS_ATIMWND0_8821C                                                    \
+	(BIT_MASK_ATIMWND0_8821C << BIT_SHIFT_ATIMWND0_8821C)
+#define BIT_CLEAR_ATIMWND0_8821C(x) ((x) & (~BITS_ATIMWND0_8821C))
+#define BIT_GET_ATIMWND0_8821C(x)                                              \
+	(((x) >> BIT_SHIFT_ATIMWND0_8821C) & BIT_MASK_ATIMWND0_8821C)
+#define BIT_SET_ATIMWND0_8821C(x, v)                                           \
+	(BIT_CLEAR_ATIMWND0_8821C(x) | BIT_ATIMWND0_8821C(v))
+
+/* 2 REG_USTIME_TSF_8821C */
+
+#define BIT_SHIFT_USTIME_TSF_V1_8821C 0
+#define BIT_MASK_USTIME_TSF_V1_8821C 0xff
+#define BIT_USTIME_TSF_V1_8821C(x)                                             \
+	(((x) & BIT_MASK_USTIME_TSF_V1_8821C) << BIT_SHIFT_USTIME_TSF_V1_8821C)
+#define BITS_USTIME_TSF_V1_8821C                                               \
+	(BIT_MASK_USTIME_TSF_V1_8821C << BIT_SHIFT_USTIME_TSF_V1_8821C)
+#define BIT_CLEAR_USTIME_TSF_V1_8821C(x) ((x) & (~BITS_USTIME_TSF_V1_8821C))
+#define BIT_GET_USTIME_TSF_V1_8821C(x)                                         \
+	(((x) >> BIT_SHIFT_USTIME_TSF_V1_8821C) & BIT_MASK_USTIME_TSF_V1_8821C)
+#define BIT_SET_USTIME_TSF_V1_8821C(x, v)                                      \
+	(BIT_CLEAR_USTIME_TSF_V1_8821C(x) | BIT_USTIME_TSF_V1_8821C(v))
+
+/* 2 REG_BCN_MAX_ERR_8821C */
+
+#define BIT_SHIFT_BCN_MAX_ERR_8821C 0
+#define BIT_MASK_BCN_MAX_ERR_8821C 0xff
+#define BIT_BCN_MAX_ERR_8821C(x)                                               \
+	(((x) & BIT_MASK_BCN_MAX_ERR_8821C) << BIT_SHIFT_BCN_MAX_ERR_8821C)
+#define BITS_BCN_MAX_ERR_8821C                                                 \
+	(BIT_MASK_BCN_MAX_ERR_8821C << BIT_SHIFT_BCN_MAX_ERR_8821C)
+#define BIT_CLEAR_BCN_MAX_ERR_8821C(x) ((x) & (~BITS_BCN_MAX_ERR_8821C))
+#define BIT_GET_BCN_MAX_ERR_8821C(x)                                           \
+	(((x) >> BIT_SHIFT_BCN_MAX_ERR_8821C) & BIT_MASK_BCN_MAX_ERR_8821C)
+#define BIT_SET_BCN_MAX_ERR_8821C(x, v)                                        \
+	(BIT_CLEAR_BCN_MAX_ERR_8821C(x) | BIT_BCN_MAX_ERR_8821C(v))
+
+/* 2 REG_RXTSF_OFFSET_CCK_8821C */
+
+#define BIT_SHIFT_CCK_RXTSF_OFFSET_8821C 0
+#define BIT_MASK_CCK_RXTSF_OFFSET_8821C 0xff
+#define BIT_CCK_RXTSF_OFFSET_8821C(x)                                          \
+	(((x) & BIT_MASK_CCK_RXTSF_OFFSET_8821C)                               \
+	 << BIT_SHIFT_CCK_RXTSF_OFFSET_8821C)
+#define BITS_CCK_RXTSF_OFFSET_8821C                                            \
+	(BIT_MASK_CCK_RXTSF_OFFSET_8821C << BIT_SHIFT_CCK_RXTSF_OFFSET_8821C)
+#define BIT_CLEAR_CCK_RXTSF_OFFSET_8821C(x)                                    \
+	((x) & (~BITS_CCK_RXTSF_OFFSET_8821C))
+#define BIT_GET_CCK_RXTSF_OFFSET_8821C(x)                                      \
+	(((x) >> BIT_SHIFT_CCK_RXTSF_OFFSET_8821C) &                           \
+	 BIT_MASK_CCK_RXTSF_OFFSET_8821C)
+#define BIT_SET_CCK_RXTSF_OFFSET_8821C(x, v)                                   \
+	(BIT_CLEAR_CCK_RXTSF_OFFSET_8821C(x) | BIT_CCK_RXTSF_OFFSET_8821C(v))
+
+/* 2 REG_RXTSF_OFFSET_OFDM_8821C */
+
+#define BIT_SHIFT_OFDM_RXTSF_OFFSET_8821C 0
+#define BIT_MASK_OFDM_RXTSF_OFFSET_8821C 0xff
+#define BIT_OFDM_RXTSF_OFFSET_8821C(x)                                         \
+	(((x) & BIT_MASK_OFDM_RXTSF_OFFSET_8821C)                              \
+	 << BIT_SHIFT_OFDM_RXTSF_OFFSET_8821C)
+#define BITS_OFDM_RXTSF_OFFSET_8821C                                           \
+	(BIT_MASK_OFDM_RXTSF_OFFSET_8821C << BIT_SHIFT_OFDM_RXTSF_OFFSET_8821C)
+#define BIT_CLEAR_OFDM_RXTSF_OFFSET_8821C(x)                                   \
+	((x) & (~BITS_OFDM_RXTSF_OFFSET_8821C))
+#define BIT_GET_OFDM_RXTSF_OFFSET_8821C(x)                                     \
+	(((x) >> BIT_SHIFT_OFDM_RXTSF_OFFSET_8821C) &                          \
+	 BIT_MASK_OFDM_RXTSF_OFFSET_8821C)
+#define BIT_SET_OFDM_RXTSF_OFFSET_8821C(x, v)                                  \
+	(BIT_CLEAR_OFDM_RXTSF_OFFSET_8821C(x) | BIT_OFDM_RXTSF_OFFSET_8821C(v))
+
+/* 2 REG_TSFTR_8821C */
+
+#define BIT_SHIFT_TSF_TIMER_V1_8821C 0
+#define BIT_MASK_TSF_TIMER_V1_8821C 0xffffffffL
+#define BIT_TSF_TIMER_V1_8821C(x)                                              \
+	(((x) & BIT_MASK_TSF_TIMER_V1_8821C) << BIT_SHIFT_TSF_TIMER_V1_8821C)
+#define BITS_TSF_TIMER_V1_8821C                                                \
+	(BIT_MASK_TSF_TIMER_V1_8821C << BIT_SHIFT_TSF_TIMER_V1_8821C)
+#define BIT_CLEAR_TSF_TIMER_V1_8821C(x) ((x) & (~BITS_TSF_TIMER_V1_8821C))
+#define BIT_GET_TSF_TIMER_V1_8821C(x)                                          \
+	(((x) >> BIT_SHIFT_TSF_TIMER_V1_8821C) & BIT_MASK_TSF_TIMER_V1_8821C)
+#define BIT_SET_TSF_TIMER_V1_8821C(x, v)                                       \
+	(BIT_CLEAR_TSF_TIMER_V1_8821C(x) | BIT_TSF_TIMER_V1_8821C(v))
+
+/* 2 REG_TSFTR_1_8821C */
+
+#define BIT_SHIFT_TSF_TIMER_V2_8821C 0
+#define BIT_MASK_TSF_TIMER_V2_8821C 0xffffffffL
+#define BIT_TSF_TIMER_V2_8821C(x)                                              \
+	(((x) & BIT_MASK_TSF_TIMER_V2_8821C) << BIT_SHIFT_TSF_TIMER_V2_8821C)
+#define BITS_TSF_TIMER_V2_8821C                                                \
+	(BIT_MASK_TSF_TIMER_V2_8821C << BIT_SHIFT_TSF_TIMER_V2_8821C)
+#define BIT_CLEAR_TSF_TIMER_V2_8821C(x) ((x) & (~BITS_TSF_TIMER_V2_8821C))
+#define BIT_GET_TSF_TIMER_V2_8821C(x)                                          \
+	(((x) >> BIT_SHIFT_TSF_TIMER_V2_8821C) & BIT_MASK_TSF_TIMER_V2_8821C)
+#define BIT_SET_TSF_TIMER_V2_8821C(x, v)                                       \
+	(BIT_CLEAR_TSF_TIMER_V2_8821C(x) | BIT_TSF_TIMER_V2_8821C(v))
+
+/* 2 REG_FREERUN_CNT_8821C */
+
+#define BIT_SHIFT_FREERUN_CNT_V1_8821C 0
+#define BIT_MASK_FREERUN_CNT_V1_8821C 0xffffffffL
+#define BIT_FREERUN_CNT_V1_8821C(x)                                            \
+	(((x) & BIT_MASK_FREERUN_CNT_V1_8821C)                                 \
+	 << BIT_SHIFT_FREERUN_CNT_V1_8821C)
+#define BITS_FREERUN_CNT_V1_8821C                                              \
+	(BIT_MASK_FREERUN_CNT_V1_8821C << BIT_SHIFT_FREERUN_CNT_V1_8821C)
+#define BIT_CLEAR_FREERUN_CNT_V1_8821C(x) ((x) & (~BITS_FREERUN_CNT_V1_8821C))
+#define BIT_GET_FREERUN_CNT_V1_8821C(x)                                        \
+	(((x) >> BIT_SHIFT_FREERUN_CNT_V1_8821C) &                             \
+	 BIT_MASK_FREERUN_CNT_V1_8821C)
+#define BIT_SET_FREERUN_CNT_V1_8821C(x, v)                                     \
+	(BIT_CLEAR_FREERUN_CNT_V1_8821C(x) | BIT_FREERUN_CNT_V1_8821C(v))
+
+/* 2 REG_FREERUN_CNT_1_8821C */
+
+#define BIT_SHIFT_FREERUN_CNT_V2_8821C 0
+#define BIT_MASK_FREERUN_CNT_V2_8821C 0xffffffffL
+#define BIT_FREERUN_CNT_V2_8821C(x)                                            \
+	(((x) & BIT_MASK_FREERUN_CNT_V2_8821C)                                 \
+	 << BIT_SHIFT_FREERUN_CNT_V2_8821C)
+#define BITS_FREERUN_CNT_V2_8821C                                              \
+	(BIT_MASK_FREERUN_CNT_V2_8821C << BIT_SHIFT_FREERUN_CNT_V2_8821C)
+#define BIT_CLEAR_FREERUN_CNT_V2_8821C(x) ((x) & (~BITS_FREERUN_CNT_V2_8821C))
+#define BIT_GET_FREERUN_CNT_V2_8821C(x)                                        \
+	(((x) >> BIT_SHIFT_FREERUN_CNT_V2_8821C) &                             \
+	 BIT_MASK_FREERUN_CNT_V2_8821C)
+#define BIT_SET_FREERUN_CNT_V2_8821C(x, v)                                     \
+	(BIT_CLEAR_FREERUN_CNT_V2_8821C(x) | BIT_FREERUN_CNT_V2_8821C(v))
+
+/* 2 REG_ATIMWND1_V1_8821C */
+
+#define BIT_SHIFT_ATIMWND1_V1_8821C 0
+#define BIT_MASK_ATIMWND1_V1_8821C 0xff
+#define BIT_ATIMWND1_V1_8821C(x)                                               \
+	(((x) & BIT_MASK_ATIMWND1_V1_8821C) << BIT_SHIFT_ATIMWND1_V1_8821C)
+#define BITS_ATIMWND1_V1_8821C                                                 \
+	(BIT_MASK_ATIMWND1_V1_8821C << BIT_SHIFT_ATIMWND1_V1_8821C)
+#define BIT_CLEAR_ATIMWND1_V1_8821C(x) ((x) & (~BITS_ATIMWND1_V1_8821C))
+#define BIT_GET_ATIMWND1_V1_8821C(x)                                           \
+	(((x) >> BIT_SHIFT_ATIMWND1_V1_8821C) & BIT_MASK_ATIMWND1_V1_8821C)
+#define BIT_SET_ATIMWND1_V1_8821C(x, v)                                        \
+	(BIT_CLEAR_ATIMWND1_V1_8821C(x) | BIT_ATIMWND1_V1_8821C(v))
+
+/* 2 REG_TBTT_PROHIBIT_INFRA_8821C */
+
+#define BIT_SHIFT_TBTT_PROHIBIT_INFRA_8821C 0
+#define BIT_MASK_TBTT_PROHIBIT_INFRA_8821C 0xff
+#define BIT_TBTT_PROHIBIT_INFRA_8821C(x)                                       \
+	(((x) & BIT_MASK_TBTT_PROHIBIT_INFRA_8821C)                            \
+	 << BIT_SHIFT_TBTT_PROHIBIT_INFRA_8821C)
+#define BITS_TBTT_PROHIBIT_INFRA_8821C                                         \
+	(BIT_MASK_TBTT_PROHIBIT_INFRA_8821C                                    \
+	 << BIT_SHIFT_TBTT_PROHIBIT_INFRA_8821C)
+#define BIT_CLEAR_TBTT_PROHIBIT_INFRA_8821C(x)                                 \
+	((x) & (~BITS_TBTT_PROHIBIT_INFRA_8821C))
+#define BIT_GET_TBTT_PROHIBIT_INFRA_8821C(x)                                   \
+	(((x) >> BIT_SHIFT_TBTT_PROHIBIT_INFRA_8821C) &                        \
+	 BIT_MASK_TBTT_PROHIBIT_INFRA_8821C)
+#define BIT_SET_TBTT_PROHIBIT_INFRA_8821C(x, v)                                \
+	(BIT_CLEAR_TBTT_PROHIBIT_INFRA_8821C(x) |                              \
+	 BIT_TBTT_PROHIBIT_INFRA_8821C(v))
+
+/* 2 REG_CTWND_8821C */
+
+#define BIT_SHIFT_CTWND_8821C 0
+#define BIT_MASK_CTWND_8821C 0xff
+#define BIT_CTWND_8821C(x)                                                     \
+	(((x) & BIT_MASK_CTWND_8821C) << BIT_SHIFT_CTWND_8821C)
+#define BITS_CTWND_8821C (BIT_MASK_CTWND_8821C << BIT_SHIFT_CTWND_8821C)
+#define BIT_CLEAR_CTWND_8821C(x) ((x) & (~BITS_CTWND_8821C))
+#define BIT_GET_CTWND_8821C(x)                                                 \
+	(((x) >> BIT_SHIFT_CTWND_8821C) & BIT_MASK_CTWND_8821C)
+#define BIT_SET_CTWND_8821C(x, v)                                              \
+	(BIT_CLEAR_CTWND_8821C(x) | BIT_CTWND_8821C(v))
+
+/* 2 REG_BCNIVLCUNT_8821C */
+
+#define BIT_SHIFT_BCNIVLCUNT_8821C 0
+#define BIT_MASK_BCNIVLCUNT_8821C 0x7f
+#define BIT_BCNIVLCUNT_8821C(x)                                                \
+	(((x) & BIT_MASK_BCNIVLCUNT_8821C) << BIT_SHIFT_BCNIVLCUNT_8821C)
+#define BITS_BCNIVLCUNT_8821C                                                  \
+	(BIT_MASK_BCNIVLCUNT_8821C << BIT_SHIFT_BCNIVLCUNT_8821C)
+#define BIT_CLEAR_BCNIVLCUNT_8821C(x) ((x) & (~BITS_BCNIVLCUNT_8821C))
+#define BIT_GET_BCNIVLCUNT_8821C(x)                                            \
+	(((x) >> BIT_SHIFT_BCNIVLCUNT_8821C) & BIT_MASK_BCNIVLCUNT_8821C)
+#define BIT_SET_BCNIVLCUNT_8821C(x, v)                                         \
+	(BIT_CLEAR_BCNIVLCUNT_8821C(x) | BIT_BCNIVLCUNT_8821C(v))
+
+/* 2 REG_BCNDROPCTRL_8821C */
+#define BIT_BEACON_DROP_EN_8821C BIT(7)
+
+#define BIT_SHIFT_BEACON_DROP_IVL_8821C 0
+#define BIT_MASK_BEACON_DROP_IVL_8821C 0x7f
+#define BIT_BEACON_DROP_IVL_8821C(x)                                           \
+	(((x) & BIT_MASK_BEACON_DROP_IVL_8821C)                                \
+	 << BIT_SHIFT_BEACON_DROP_IVL_8821C)
+#define BITS_BEACON_DROP_IVL_8821C                                             \
+	(BIT_MASK_BEACON_DROP_IVL_8821C << BIT_SHIFT_BEACON_DROP_IVL_8821C)
+#define BIT_CLEAR_BEACON_DROP_IVL_8821C(x) ((x) & (~BITS_BEACON_DROP_IVL_8821C))
+#define BIT_GET_BEACON_DROP_IVL_8821C(x)                                       \
+	(((x) >> BIT_SHIFT_BEACON_DROP_IVL_8821C) &                            \
+	 BIT_MASK_BEACON_DROP_IVL_8821C)
+#define BIT_SET_BEACON_DROP_IVL_8821C(x, v)                                    \
+	(BIT_CLEAR_BEACON_DROP_IVL_8821C(x) | BIT_BEACON_DROP_IVL_8821C(v))
+
+/* 2 REG_HGQ_TIMEOUT_PERIOD_8821C */
+
+#define BIT_SHIFT_HGQ_TIMEOUT_PERIOD_8821C 0
+#define BIT_MASK_HGQ_TIMEOUT_PERIOD_8821C 0xff
+#define BIT_HGQ_TIMEOUT_PERIOD_8821C(x)                                        \
+	(((x) & BIT_MASK_HGQ_TIMEOUT_PERIOD_8821C)                             \
+	 << BIT_SHIFT_HGQ_TIMEOUT_PERIOD_8821C)
+#define BITS_HGQ_TIMEOUT_PERIOD_8821C                                          \
+	(BIT_MASK_HGQ_TIMEOUT_PERIOD_8821C                                     \
+	 << BIT_SHIFT_HGQ_TIMEOUT_PERIOD_8821C)
+#define BIT_CLEAR_HGQ_TIMEOUT_PERIOD_8821C(x)                                  \
+	((x) & (~BITS_HGQ_TIMEOUT_PERIOD_8821C))
+#define BIT_GET_HGQ_TIMEOUT_PERIOD_8821C(x)                                    \
+	(((x) >> BIT_SHIFT_HGQ_TIMEOUT_PERIOD_8821C) &                         \
+	 BIT_MASK_HGQ_TIMEOUT_PERIOD_8821C)
+#define BIT_SET_HGQ_TIMEOUT_PERIOD_8821C(x, v)                                 \
+	(BIT_CLEAR_HGQ_TIMEOUT_PERIOD_8821C(x) |                               \
+	 BIT_HGQ_TIMEOUT_PERIOD_8821C(v))
+
+/* 2 REG_TXCMD_TIMEOUT_PERIOD_8821C */
+
+#define BIT_SHIFT_TXCMD_TIMEOUT_PERIOD_8821C 0
+#define BIT_MASK_TXCMD_TIMEOUT_PERIOD_8821C 0xff
+#define BIT_TXCMD_TIMEOUT_PERIOD_8821C(x)                                      \
+	(((x) & BIT_MASK_TXCMD_TIMEOUT_PERIOD_8821C)                           \
+	 << BIT_SHIFT_TXCMD_TIMEOUT_PERIOD_8821C)
+#define BITS_TXCMD_TIMEOUT_PERIOD_8821C                                        \
+	(BIT_MASK_TXCMD_TIMEOUT_PERIOD_8821C                                   \
+	 << BIT_SHIFT_TXCMD_TIMEOUT_PERIOD_8821C)
+#define BIT_CLEAR_TXCMD_TIMEOUT_PERIOD_8821C(x)                                \
+	((x) & (~BITS_TXCMD_TIMEOUT_PERIOD_8821C))
+#define BIT_GET_TXCMD_TIMEOUT_PERIOD_8821C(x)                                  \
+	(((x) >> BIT_SHIFT_TXCMD_TIMEOUT_PERIOD_8821C) &                       \
+	 BIT_MASK_TXCMD_TIMEOUT_PERIOD_8821C)
+#define BIT_SET_TXCMD_TIMEOUT_PERIOD_8821C(x, v)                               \
+	(BIT_CLEAR_TXCMD_TIMEOUT_PERIOD_8821C(x) |                             \
+	 BIT_TXCMD_TIMEOUT_PERIOD_8821C(v))
+
+/* 2 REG_MISC_CTRL_8821C */
+#define BIT_AUTO_SYNC_BY_TBTT_8821C BIT(6)
+#define BIT_DIS_TRX_CAL_BCN_8821C BIT(5)
+#define BIT_DIS_TX_CAL_TBTT_8821C BIT(4)
+#define BIT_EN_FREECNT_8821C BIT(3)
+#define BIT_BCN_AGGRESSION_8821C BIT(2)
+
+#define BIT_SHIFT_DIS_SECONDARY_CCA_8821C 0
+#define BIT_MASK_DIS_SECONDARY_CCA_8821C 0x3
+#define BIT_DIS_SECONDARY_CCA_8821C(x)                                         \
+	(((x) & BIT_MASK_DIS_SECONDARY_CCA_8821C)                              \
+	 << BIT_SHIFT_DIS_SECONDARY_CCA_8821C)
+#define BITS_DIS_SECONDARY_CCA_8821C                                           \
+	(BIT_MASK_DIS_SECONDARY_CCA_8821C << BIT_SHIFT_DIS_SECONDARY_CCA_8821C)
+#define BIT_CLEAR_DIS_SECONDARY_CCA_8821C(x)                                   \
+	((x) & (~BITS_DIS_SECONDARY_CCA_8821C))
+#define BIT_GET_DIS_SECONDARY_CCA_8821C(x)                                     \
+	(((x) >> BIT_SHIFT_DIS_SECONDARY_CCA_8821C) &                          \
+	 BIT_MASK_DIS_SECONDARY_CCA_8821C)
+#define BIT_SET_DIS_SECONDARY_CCA_8821C(x, v)                                  \
+	(BIT_CLEAR_DIS_SECONDARY_CCA_8821C(x) | BIT_DIS_SECONDARY_CCA_8821C(v))
+
+/* 2 REG_BCN_CTRL_CLINT1_8821C */
+#define BIT_CLI1_DIS_RX_BSSID_FIT_8821C BIT(6)
+#define BIT_CLI1_DIS_TSF_UDT_8821C BIT(4)
+#define BIT_CLI1_EN_BCN_FUNCTION_8821C BIT(3)
+#define BIT_CLI1_EN_RXBCN_RPT_8821C BIT(2)
+#define BIT_CLI1_ENP2P_CTWINDOW_8821C BIT(1)
+#define BIT_CLI1_ENP2P_BCNQ_AREA_8821C BIT(0)
+
+/* 2 REG_BCN_CTRL_CLINT2_8821C */
+#define BIT_CLI2_DIS_RX_BSSID_FIT_8821C BIT(6)
+#define BIT_CLI2_DIS_TSF_UDT_8821C BIT(4)
+#define BIT_CLI2_EN_BCN_FUNCTION_8821C BIT(3)
+#define BIT_CLI2_EN_RXBCN_RPT_8821C BIT(2)
+#define BIT_CLI2_ENP2P_CTWINDOW_8821C BIT(1)
+#define BIT_CLI2_ENP2P_BCNQ_AREA_8821C BIT(0)
+
+/* 2 REG_BCN_CTRL_CLINT3_8821C */
+#define BIT_CLI3_DIS_RX_BSSID_FIT_8821C BIT(6)
+#define BIT_CLI3_DIS_TSF_UDT_8821C BIT(4)
+#define BIT_CLI3_EN_BCN_FUNCTION_8821C BIT(3)
+#define BIT_CLI3_EN_RXBCN_RPT_8821C BIT(2)
+#define BIT_CLI3_ENP2P_CTWINDOW_8821C BIT(1)
+#define BIT_CLI3_ENP2P_BCNQ_AREA_8821C BIT(0)
+
+/* 2 REG_EXTEND_CTRL_8821C */
+#define BIT_EN_TSFBIT32_RST_P2P2_8821C BIT(5)
+#define BIT_EN_TSFBIT32_RST_P2P1_8821C BIT(4)
+
+#define BIT_SHIFT_PORT_SEL_8821C 0
+#define BIT_MASK_PORT_SEL_8821C 0x7
+#define BIT_PORT_SEL_8821C(x)                                                  \
+	(((x) & BIT_MASK_PORT_SEL_8821C) << BIT_SHIFT_PORT_SEL_8821C)
+#define BITS_PORT_SEL_8821C                                                    \
+	(BIT_MASK_PORT_SEL_8821C << BIT_SHIFT_PORT_SEL_8821C)
+#define BIT_CLEAR_PORT_SEL_8821C(x) ((x) & (~BITS_PORT_SEL_8821C))
+#define BIT_GET_PORT_SEL_8821C(x)                                              \
+	(((x) >> BIT_SHIFT_PORT_SEL_8821C) & BIT_MASK_PORT_SEL_8821C)
+#define BIT_SET_PORT_SEL_8821C(x, v)                                           \
+	(BIT_CLEAR_PORT_SEL_8821C(x) | BIT_PORT_SEL_8821C(v))
+
+/* 2 REG_P2PPS1_SPEC_STATE_8821C */
+#define BIT_P2P1_SPEC_POWER_STATE_8821C BIT(7)
+#define BIT_P2P1_SPEC_CTWINDOW_ON_8821C BIT(6)
+#define BIT_P2P1_SPEC_BCN_AREA_ON_8821C BIT(5)
+#define BIT_P2P1_SPEC_CTWIN_EARLY_DISTX_8821C BIT(4)
+#define BIT_P2P1_SPEC_NOA1_OFF_PERIOD_8821C BIT(3)
+#define BIT_P2P1_SPEC_FORCE_DOZE1_8821C BIT(2)
+#define BIT_P2P1_SPEC_NOA0_OFF_PERIOD_8821C BIT(1)
+#define BIT_P2P1_SPEC_FORCE_DOZE0_8821C BIT(0)
+
+/* 2 REG_P2PPS1_STATE_8821C */
+#define BIT_P2P1_POWER_STATE_8821C BIT(7)
+#define BIT_P2P1_CTWINDOW_ON_8821C BIT(6)
+#define BIT_P2P1_BEACON_AREA_ON_8821C BIT(5)
+#define BIT_P2P1_CTWIN_EARLY_DISTX_8821C BIT(4)
+#define BIT_P2P1_NOA1_OFF_PERIOD_8821C BIT(3)
+#define BIT_P2P1_FORCE_DOZE1_8821C BIT(2)
+#define BIT_P2P1_NOA0_OFF_PERIOD_8821C BIT(1)
+#define BIT_P2P1_FORCE_DOZE0_8821C BIT(0)
+
+/* 2 REG_P2PPS2_SPEC_STATE_8821C */
+#define BIT_P2P2_SPEC_POWER_STATE_8821C BIT(7)
+#define BIT_P2P2_SPEC_CTWINDOW_ON_8821C BIT(6)
+#define BIT_P2P2_SPEC_BCN_AREA_ON_8821C BIT(5)
+#define BIT_P2P2_SPEC_CTWIN_EARLY_DISTX_8821C BIT(4)
+#define BIT_P2P2_SPEC_NOA1_OFF_PERIOD_8821C BIT(3)
+#define BIT_P2P2_SPEC_FORCE_DOZE1_8821C BIT(2)
+#define BIT_P2P2_SPEC_NOA0_OFF_PERIOD_8821C BIT(1)
+#define BIT_P2P2_SPEC_FORCE_DOZE0_8821C BIT(0)
+
+/* 2 REG_P2PPS2_STATE_8821C */
+#define BIT_P2P2_POWER_STATE_8821C BIT(7)
+#define BIT_P2P2_CTWINDOW_ON_8821C BIT(6)
+#define BIT_P2P2_BEACON_AREA_ON_8821C BIT(5)
+#define BIT_P2P2_CTWIN_EARLY_DISTX_8821C BIT(4)
+#define BIT_P2P2_NOA1_OFF_PERIOD_8821C BIT(3)
+#define BIT_P2P2_FORCE_DOZE1_8821C BIT(2)
+#define BIT_P2P2_NOA0_OFF_PERIOD_8821C BIT(1)
+#define BIT_P2P2_FORCE_DOZE0_8821C BIT(0)
+
+/* 2 REG_PS_TIMER0_8821C */
+
+#define BIT_SHIFT_PSTIMER0_INT_8821C 5
+#define BIT_MASK_PSTIMER0_INT_8821C 0x7ffffff
+#define BIT_PSTIMER0_INT_8821C(x)                                              \
+	(((x) & BIT_MASK_PSTIMER0_INT_8821C) << BIT_SHIFT_PSTIMER0_INT_8821C)
+#define BITS_PSTIMER0_INT_8821C                                                \
+	(BIT_MASK_PSTIMER0_INT_8821C << BIT_SHIFT_PSTIMER0_INT_8821C)
+#define BIT_CLEAR_PSTIMER0_INT_8821C(x) ((x) & (~BITS_PSTIMER0_INT_8821C))
+#define BIT_GET_PSTIMER0_INT_8821C(x)                                          \
+	(((x) >> BIT_SHIFT_PSTIMER0_INT_8821C) & BIT_MASK_PSTIMER0_INT_8821C)
+#define BIT_SET_PSTIMER0_INT_8821C(x, v)                                       \
+	(BIT_CLEAR_PSTIMER0_INT_8821C(x) | BIT_PSTIMER0_INT_8821C(v))
+
+/* 2 REG_PS_TIMER1_8821C */
+
+#define BIT_SHIFT_PSTIMER1_INT_8821C 5
+#define BIT_MASK_PSTIMER1_INT_8821C 0x7ffffff
+#define BIT_PSTIMER1_INT_8821C(x)                                              \
+	(((x) & BIT_MASK_PSTIMER1_INT_8821C) << BIT_SHIFT_PSTIMER1_INT_8821C)
+#define BITS_PSTIMER1_INT_8821C                                                \
+	(BIT_MASK_PSTIMER1_INT_8821C << BIT_SHIFT_PSTIMER1_INT_8821C)
+#define BIT_CLEAR_PSTIMER1_INT_8821C(x) ((x) & (~BITS_PSTIMER1_INT_8821C))
+#define BIT_GET_PSTIMER1_INT_8821C(x)                                          \
+	(((x) >> BIT_SHIFT_PSTIMER1_INT_8821C) & BIT_MASK_PSTIMER1_INT_8821C)
+#define BIT_SET_PSTIMER1_INT_8821C(x, v)                                       \
+	(BIT_CLEAR_PSTIMER1_INT_8821C(x) | BIT_PSTIMER1_INT_8821C(v))
+
+/* 2 REG_PS_TIMER2_8821C */
+
+#define BIT_SHIFT_PSTIMER2_INT_8821C 5
+#define BIT_MASK_PSTIMER2_INT_8821C 0x7ffffff
+#define BIT_PSTIMER2_INT_8821C(x)                                              \
+	(((x) & BIT_MASK_PSTIMER2_INT_8821C) << BIT_SHIFT_PSTIMER2_INT_8821C)
+#define BITS_PSTIMER2_INT_8821C                                                \
+	(BIT_MASK_PSTIMER2_INT_8821C << BIT_SHIFT_PSTIMER2_INT_8821C)
+#define BIT_CLEAR_PSTIMER2_INT_8821C(x) ((x) & (~BITS_PSTIMER2_INT_8821C))
+#define BIT_GET_PSTIMER2_INT_8821C(x)                                          \
+	(((x) >> BIT_SHIFT_PSTIMER2_INT_8821C) & BIT_MASK_PSTIMER2_INT_8821C)
+#define BIT_SET_PSTIMER2_INT_8821C(x, v)                                       \
+	(BIT_CLEAR_PSTIMER2_INT_8821C(x) | BIT_PSTIMER2_INT_8821C(v))
+
+/* 2 REG_TBTT_CTN_AREA_8821C */
+
+#define BIT_SHIFT_TBTT_CTN_AREA_8821C 0
+#define BIT_MASK_TBTT_CTN_AREA_8821C 0xff
+#define BIT_TBTT_CTN_AREA_8821C(x)                                             \
+	(((x) & BIT_MASK_TBTT_CTN_AREA_8821C) << BIT_SHIFT_TBTT_CTN_AREA_8821C)
+#define BITS_TBTT_CTN_AREA_8821C                                               \
+	(BIT_MASK_TBTT_CTN_AREA_8821C << BIT_SHIFT_TBTT_CTN_AREA_8821C)
+#define BIT_CLEAR_TBTT_CTN_AREA_8821C(x) ((x) & (~BITS_TBTT_CTN_AREA_8821C))
+#define BIT_GET_TBTT_CTN_AREA_8821C(x)                                         \
+	(((x) >> BIT_SHIFT_TBTT_CTN_AREA_8821C) & BIT_MASK_TBTT_CTN_AREA_8821C)
+#define BIT_SET_TBTT_CTN_AREA_8821C(x, v)                                      \
+	(BIT_CLEAR_TBTT_CTN_AREA_8821C(x) | BIT_TBTT_CTN_AREA_8821C(v))
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_FORCE_BCN_IFS_8821C */
+
+#define BIT_SHIFT_FORCE_BCN_IFS_8821C 0
+#define BIT_MASK_FORCE_BCN_IFS_8821C 0xff
+#define BIT_FORCE_BCN_IFS_8821C(x)                                             \
+	(((x) & BIT_MASK_FORCE_BCN_IFS_8821C) << BIT_SHIFT_FORCE_BCN_IFS_8821C)
+#define BITS_FORCE_BCN_IFS_8821C                                               \
+	(BIT_MASK_FORCE_BCN_IFS_8821C << BIT_SHIFT_FORCE_BCN_IFS_8821C)
+#define BIT_CLEAR_FORCE_BCN_IFS_8821C(x) ((x) & (~BITS_FORCE_BCN_IFS_8821C))
+#define BIT_GET_FORCE_BCN_IFS_8821C(x)                                         \
+	(((x) >> BIT_SHIFT_FORCE_BCN_IFS_8821C) & BIT_MASK_FORCE_BCN_IFS_8821C)
+#define BIT_SET_FORCE_BCN_IFS_8821C(x, v)                                      \
+	(BIT_CLEAR_FORCE_BCN_IFS_8821C(x) | BIT_FORCE_BCN_IFS_8821C(v))
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_TXOP_MIN_8821C */
+
+#define BIT_SHIFT_TXOP_MIN_8821C 0
+#define BIT_MASK_TXOP_MIN_8821C 0x3fff
+#define BIT_TXOP_MIN_8821C(x)                                                  \
+	(((x) & BIT_MASK_TXOP_MIN_8821C) << BIT_SHIFT_TXOP_MIN_8821C)
+#define BITS_TXOP_MIN_8821C                                                    \
+	(BIT_MASK_TXOP_MIN_8821C << BIT_SHIFT_TXOP_MIN_8821C)
+#define BIT_CLEAR_TXOP_MIN_8821C(x) ((x) & (~BITS_TXOP_MIN_8821C))
+#define BIT_GET_TXOP_MIN_8821C(x)                                              \
+	(((x) >> BIT_SHIFT_TXOP_MIN_8821C) & BIT_MASK_TXOP_MIN_8821C)
+#define BIT_SET_TXOP_MIN_8821C(x, v)                                           \
+	(BIT_CLEAR_TXOP_MIN_8821C(x) | BIT_TXOP_MIN_8821C(v))
+
+/* 2 REG_PRE_BKF_TIME_8821C */
+
+#define BIT_SHIFT_PRE_BKF_TIME_8821C 0
+#define BIT_MASK_PRE_BKF_TIME_8821C 0xff
+#define BIT_PRE_BKF_TIME_8821C(x)                                              \
+	(((x) & BIT_MASK_PRE_BKF_TIME_8821C) << BIT_SHIFT_PRE_BKF_TIME_8821C)
+#define BITS_PRE_BKF_TIME_8821C                                                \
+	(BIT_MASK_PRE_BKF_TIME_8821C << BIT_SHIFT_PRE_BKF_TIME_8821C)
+#define BIT_CLEAR_PRE_BKF_TIME_8821C(x) ((x) & (~BITS_PRE_BKF_TIME_8821C))
+#define BIT_GET_PRE_BKF_TIME_8821C(x)                                          \
+	(((x) >> BIT_SHIFT_PRE_BKF_TIME_8821C) & BIT_MASK_PRE_BKF_TIME_8821C)
+#define BIT_SET_PRE_BKF_TIME_8821C(x, v)                                       \
+	(BIT_CLEAR_PRE_BKF_TIME_8821C(x) | BIT_PRE_BKF_TIME_8821C(v))
+
+/* 2 REG_CROSS_TXOP_CTRL_8821C */
+#define BIT_TXFAIL_BREACK_TXOP_EN_8821C BIT(3)
+#define BIT_DTIM_BYPASS_8821C BIT(2)
+#define BIT_RTS_NAV_TXOP_8821C BIT(1)
+#define BIT_NOT_CROSS_TXOP_8821C BIT(0)
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_ATIMWND2_8821C */
+
+#define BIT_SHIFT_ATIMWND2_8821C 0
+#define BIT_MASK_ATIMWND2_8821C 0xff
+#define BIT_ATIMWND2_8821C(x)                                                  \
+	(((x) & BIT_MASK_ATIMWND2_8821C) << BIT_SHIFT_ATIMWND2_8821C)
+#define BITS_ATIMWND2_8821C                                                    \
+	(BIT_MASK_ATIMWND2_8821C << BIT_SHIFT_ATIMWND2_8821C)
+#define BIT_CLEAR_ATIMWND2_8821C(x) ((x) & (~BITS_ATIMWND2_8821C))
+#define BIT_GET_ATIMWND2_8821C(x)                                              \
+	(((x) >> BIT_SHIFT_ATIMWND2_8821C) & BIT_MASK_ATIMWND2_8821C)
+#define BIT_SET_ATIMWND2_8821C(x, v)                                           \
+	(BIT_CLEAR_ATIMWND2_8821C(x) | BIT_ATIMWND2_8821C(v))
+
+/* 2 REG_ATIMWND3_8821C */
+
+#define BIT_SHIFT_ATIMWND3_8821C 0
+#define BIT_MASK_ATIMWND3_8821C 0xff
+#define BIT_ATIMWND3_8821C(x)                                                  \
+	(((x) & BIT_MASK_ATIMWND3_8821C) << BIT_SHIFT_ATIMWND3_8821C)
+#define BITS_ATIMWND3_8821C                                                    \
+	(BIT_MASK_ATIMWND3_8821C << BIT_SHIFT_ATIMWND3_8821C)
+#define BIT_CLEAR_ATIMWND3_8821C(x) ((x) & (~BITS_ATIMWND3_8821C))
+#define BIT_GET_ATIMWND3_8821C(x)                                              \
+	(((x) >> BIT_SHIFT_ATIMWND3_8821C) & BIT_MASK_ATIMWND3_8821C)
+#define BIT_SET_ATIMWND3_8821C(x, v)                                           \
+	(BIT_CLEAR_ATIMWND3_8821C(x) | BIT_ATIMWND3_8821C(v))
+
+/* 2 REG_ATIMWND4_8821C */
+
+#define BIT_SHIFT_ATIMWND4_8821C 0
+#define BIT_MASK_ATIMWND4_8821C 0xff
+#define BIT_ATIMWND4_8821C(x)                                                  \
+	(((x) & BIT_MASK_ATIMWND4_8821C) << BIT_SHIFT_ATIMWND4_8821C)
+#define BITS_ATIMWND4_8821C                                                    \
+	(BIT_MASK_ATIMWND4_8821C << BIT_SHIFT_ATIMWND4_8821C)
+#define BIT_CLEAR_ATIMWND4_8821C(x) ((x) & (~BITS_ATIMWND4_8821C))
+#define BIT_GET_ATIMWND4_8821C(x)                                              \
+	(((x) >> BIT_SHIFT_ATIMWND4_8821C) & BIT_MASK_ATIMWND4_8821C)
+#define BIT_SET_ATIMWND4_8821C(x, v)                                           \
+	(BIT_CLEAR_ATIMWND4_8821C(x) | BIT_ATIMWND4_8821C(v))
+
+/* 2 REG_ATIMWND5_8821C */
+
+#define BIT_SHIFT_ATIMWND5_8821C 0
+#define BIT_MASK_ATIMWND5_8821C 0xff
+#define BIT_ATIMWND5_8821C(x)                                                  \
+	(((x) & BIT_MASK_ATIMWND5_8821C) << BIT_SHIFT_ATIMWND5_8821C)
+#define BITS_ATIMWND5_8821C                                                    \
+	(BIT_MASK_ATIMWND5_8821C << BIT_SHIFT_ATIMWND5_8821C)
+#define BIT_CLEAR_ATIMWND5_8821C(x) ((x) & (~BITS_ATIMWND5_8821C))
+#define BIT_GET_ATIMWND5_8821C(x)                                              \
+	(((x) >> BIT_SHIFT_ATIMWND5_8821C) & BIT_MASK_ATIMWND5_8821C)
+#define BIT_SET_ATIMWND5_8821C(x, v)                                           \
+	(BIT_CLEAR_ATIMWND5_8821C(x) | BIT_ATIMWND5_8821C(v))
+
+/* 2 REG_ATIMWND6_8821C */
+
+#define BIT_SHIFT_ATIMWND6_8821C 0
+#define BIT_MASK_ATIMWND6_8821C 0xff
+#define BIT_ATIMWND6_8821C(x)                                                  \
+	(((x) & BIT_MASK_ATIMWND6_8821C) << BIT_SHIFT_ATIMWND6_8821C)
+#define BITS_ATIMWND6_8821C                                                    \
+	(BIT_MASK_ATIMWND6_8821C << BIT_SHIFT_ATIMWND6_8821C)
+#define BIT_CLEAR_ATIMWND6_8821C(x) ((x) & (~BITS_ATIMWND6_8821C))
+#define BIT_GET_ATIMWND6_8821C(x)                                              \
+	(((x) >> BIT_SHIFT_ATIMWND6_8821C) & BIT_MASK_ATIMWND6_8821C)
+#define BIT_SET_ATIMWND6_8821C(x, v)                                           \
+	(BIT_CLEAR_ATIMWND6_8821C(x) | BIT_ATIMWND6_8821C(v))
+
+/* 2 REG_ATIMWND7_8821C */
+
+#define BIT_SHIFT_ATIMWND7_8821C 0
+#define BIT_MASK_ATIMWND7_8821C 0xff
+#define BIT_ATIMWND7_8821C(x)                                                  \
+	(((x) & BIT_MASK_ATIMWND7_8821C) << BIT_SHIFT_ATIMWND7_8821C)
+#define BITS_ATIMWND7_8821C                                                    \
+	(BIT_MASK_ATIMWND7_8821C << BIT_SHIFT_ATIMWND7_8821C)
+#define BIT_CLEAR_ATIMWND7_8821C(x) ((x) & (~BITS_ATIMWND7_8821C))
+#define BIT_GET_ATIMWND7_8821C(x)                                              \
+	(((x) >> BIT_SHIFT_ATIMWND7_8821C) & BIT_MASK_ATIMWND7_8821C)
+#define BIT_SET_ATIMWND7_8821C(x, v)                                           \
+	(BIT_CLEAR_ATIMWND7_8821C(x) | BIT_ATIMWND7_8821C(v))
+
+/* 2 REG_ATIMUGT_8821C */
+
+#define BIT_SHIFT_ATIM_URGENT_8821C 0
+#define BIT_MASK_ATIM_URGENT_8821C 0xff
+#define BIT_ATIM_URGENT_8821C(x)                                               \
+	(((x) & BIT_MASK_ATIM_URGENT_8821C) << BIT_SHIFT_ATIM_URGENT_8821C)
+#define BITS_ATIM_URGENT_8821C                                                 \
+	(BIT_MASK_ATIM_URGENT_8821C << BIT_SHIFT_ATIM_URGENT_8821C)
+#define BIT_CLEAR_ATIM_URGENT_8821C(x) ((x) & (~BITS_ATIM_URGENT_8821C))
+#define BIT_GET_ATIM_URGENT_8821C(x)                                           \
+	(((x) >> BIT_SHIFT_ATIM_URGENT_8821C) & BIT_MASK_ATIM_URGENT_8821C)
+#define BIT_SET_ATIM_URGENT_8821C(x, v)                                        \
+	(BIT_CLEAR_ATIM_URGENT_8821C(x) | BIT_ATIM_URGENT_8821C(v))
+
+/* 2 REG_HIQ_NO_LMT_EN_8821C */
+#define BIT_HIQ_NO_LMT_EN_VAP7_8821C BIT(7)
+#define BIT_HIQ_NO_LMT_EN_VAP6_8821C BIT(6)
+#define BIT_HIQ_NO_LMT_EN_VAP5_8821C BIT(5)
+#define BIT_HIQ_NO_LMT_EN_VAP4_8821C BIT(4)
+#define BIT_HIQ_NO_LMT_EN_VAP3_8821C BIT(3)
+#define BIT_HIQ_NO_LMT_EN_VAP2_8821C BIT(2)
+#define BIT_HIQ_NO_LMT_EN_VAP1_8821C BIT(1)
+#define BIT_HIQ_NO_LMT_EN_ROOT_8821C BIT(0)
+
+/* 2 REG_DTIM_COUNTER_ROOT_8821C */
+
+#define BIT_SHIFT_DTIM_COUNT_ROOT_8821C 0
+#define BIT_MASK_DTIM_COUNT_ROOT_8821C 0xff
+#define BIT_DTIM_COUNT_ROOT_8821C(x)                                           \
+	(((x) & BIT_MASK_DTIM_COUNT_ROOT_8821C)                                \
+	 << BIT_SHIFT_DTIM_COUNT_ROOT_8821C)
+#define BITS_DTIM_COUNT_ROOT_8821C                                             \
+	(BIT_MASK_DTIM_COUNT_ROOT_8821C << BIT_SHIFT_DTIM_COUNT_ROOT_8821C)
+#define BIT_CLEAR_DTIM_COUNT_ROOT_8821C(x) ((x) & (~BITS_DTIM_COUNT_ROOT_8821C))
+#define BIT_GET_DTIM_COUNT_ROOT_8821C(x)                                       \
+	(((x) >> BIT_SHIFT_DTIM_COUNT_ROOT_8821C) &                            \
+	 BIT_MASK_DTIM_COUNT_ROOT_8821C)
+#define BIT_SET_DTIM_COUNT_ROOT_8821C(x, v)                                    \
+	(BIT_CLEAR_DTIM_COUNT_ROOT_8821C(x) | BIT_DTIM_COUNT_ROOT_8821C(v))
+
+/* 2 REG_DTIM_COUNTER_VAP1_8821C */
+
+#define BIT_SHIFT_DTIM_COUNT_VAP1_8821C 0
+#define BIT_MASK_DTIM_COUNT_VAP1_8821C 0xff
+#define BIT_DTIM_COUNT_VAP1_8821C(x)                                           \
+	(((x) & BIT_MASK_DTIM_COUNT_VAP1_8821C)                                \
+	 << BIT_SHIFT_DTIM_COUNT_VAP1_8821C)
+#define BITS_DTIM_COUNT_VAP1_8821C                                             \
+	(BIT_MASK_DTIM_COUNT_VAP1_8821C << BIT_SHIFT_DTIM_COUNT_VAP1_8821C)
+#define BIT_CLEAR_DTIM_COUNT_VAP1_8821C(x) ((x) & (~BITS_DTIM_COUNT_VAP1_8821C))
+#define BIT_GET_DTIM_COUNT_VAP1_8821C(x)                                       \
+	(((x) >> BIT_SHIFT_DTIM_COUNT_VAP1_8821C) &                            \
+	 BIT_MASK_DTIM_COUNT_VAP1_8821C)
+#define BIT_SET_DTIM_COUNT_VAP1_8821C(x, v)                                    \
+	(BIT_CLEAR_DTIM_COUNT_VAP1_8821C(x) | BIT_DTIM_COUNT_VAP1_8821C(v))
+
+/* 2 REG_DTIM_COUNTER_VAP2_8821C */
+
+#define BIT_SHIFT_DTIM_COUNT_VAP2_8821C 0
+#define BIT_MASK_DTIM_COUNT_VAP2_8821C 0xff
+#define BIT_DTIM_COUNT_VAP2_8821C(x)                                           \
+	(((x) & BIT_MASK_DTIM_COUNT_VAP2_8821C)                                \
+	 << BIT_SHIFT_DTIM_COUNT_VAP2_8821C)
+#define BITS_DTIM_COUNT_VAP2_8821C                                             \
+	(BIT_MASK_DTIM_COUNT_VAP2_8821C << BIT_SHIFT_DTIM_COUNT_VAP2_8821C)
+#define BIT_CLEAR_DTIM_COUNT_VAP2_8821C(x) ((x) & (~BITS_DTIM_COUNT_VAP2_8821C))
+#define BIT_GET_DTIM_COUNT_VAP2_8821C(x)                                       \
+	(((x) >> BIT_SHIFT_DTIM_COUNT_VAP2_8821C) &                            \
+	 BIT_MASK_DTIM_COUNT_VAP2_8821C)
+#define BIT_SET_DTIM_COUNT_VAP2_8821C(x, v)                                    \
+	(BIT_CLEAR_DTIM_COUNT_VAP2_8821C(x) | BIT_DTIM_COUNT_VAP2_8821C(v))
+
+/* 2 REG_DTIM_COUNTER_VAP3_8821C */
+
+#define BIT_SHIFT_DTIM_COUNT_VAP3_8821C 0
+#define BIT_MASK_DTIM_COUNT_VAP3_8821C 0xff
+#define BIT_DTIM_COUNT_VAP3_8821C(x)                                           \
+	(((x) & BIT_MASK_DTIM_COUNT_VAP3_8821C)                                \
+	 << BIT_SHIFT_DTIM_COUNT_VAP3_8821C)
+#define BITS_DTIM_COUNT_VAP3_8821C                                             \
+	(BIT_MASK_DTIM_COUNT_VAP3_8821C << BIT_SHIFT_DTIM_COUNT_VAP3_8821C)
+#define BIT_CLEAR_DTIM_COUNT_VAP3_8821C(x) ((x) & (~BITS_DTIM_COUNT_VAP3_8821C))
+#define BIT_GET_DTIM_COUNT_VAP3_8821C(x)                                       \
+	(((x) >> BIT_SHIFT_DTIM_COUNT_VAP3_8821C) &                            \
+	 BIT_MASK_DTIM_COUNT_VAP3_8821C)
+#define BIT_SET_DTIM_COUNT_VAP3_8821C(x, v)                                    \
+	(BIT_CLEAR_DTIM_COUNT_VAP3_8821C(x) | BIT_DTIM_COUNT_VAP3_8821C(v))
+
+/* 2 REG_DTIM_COUNTER_VAP4_8821C */
+
+#define BIT_SHIFT_DTIM_COUNT_VAP4_8821C 0
+#define BIT_MASK_DTIM_COUNT_VAP4_8821C 0xff
+#define BIT_DTIM_COUNT_VAP4_8821C(x)                                           \
+	(((x) & BIT_MASK_DTIM_COUNT_VAP4_8821C)                                \
+	 << BIT_SHIFT_DTIM_COUNT_VAP4_8821C)
+#define BITS_DTIM_COUNT_VAP4_8821C                                             \
+	(BIT_MASK_DTIM_COUNT_VAP4_8821C << BIT_SHIFT_DTIM_COUNT_VAP4_8821C)
+#define BIT_CLEAR_DTIM_COUNT_VAP4_8821C(x) ((x) & (~BITS_DTIM_COUNT_VAP4_8821C))
+#define BIT_GET_DTIM_COUNT_VAP4_8821C(x)                                       \
+	(((x) >> BIT_SHIFT_DTIM_COUNT_VAP4_8821C) &                            \
+	 BIT_MASK_DTIM_COUNT_VAP4_8821C)
+#define BIT_SET_DTIM_COUNT_VAP4_8821C(x, v)                                    \
+	(BIT_CLEAR_DTIM_COUNT_VAP4_8821C(x) | BIT_DTIM_COUNT_VAP4_8821C(v))
+
+/* 2 REG_DTIM_COUNTER_VAP5_8821C */
+
+#define BIT_SHIFT_DTIM_COUNT_VAP5_8821C 0
+#define BIT_MASK_DTIM_COUNT_VAP5_8821C 0xff
+#define BIT_DTIM_COUNT_VAP5_8821C(x)                                           \
+	(((x) & BIT_MASK_DTIM_COUNT_VAP5_8821C)                                \
+	 << BIT_SHIFT_DTIM_COUNT_VAP5_8821C)
+#define BITS_DTIM_COUNT_VAP5_8821C                                             \
+	(BIT_MASK_DTIM_COUNT_VAP5_8821C << BIT_SHIFT_DTIM_COUNT_VAP5_8821C)
+#define BIT_CLEAR_DTIM_COUNT_VAP5_8821C(x) ((x) & (~BITS_DTIM_COUNT_VAP5_8821C))
+#define BIT_GET_DTIM_COUNT_VAP5_8821C(x)                                       \
+	(((x) >> BIT_SHIFT_DTIM_COUNT_VAP5_8821C) &                            \
+	 BIT_MASK_DTIM_COUNT_VAP5_8821C)
+#define BIT_SET_DTIM_COUNT_VAP5_8821C(x, v)                                    \
+	(BIT_CLEAR_DTIM_COUNT_VAP5_8821C(x) | BIT_DTIM_COUNT_VAP5_8821C(v))
+
+/* 2 REG_DTIM_COUNTER_VAP6_8821C */
+
+#define BIT_SHIFT_DTIM_COUNT_VAP6_8821C 0
+#define BIT_MASK_DTIM_COUNT_VAP6_8821C 0xff
+#define BIT_DTIM_COUNT_VAP6_8821C(x)                                           \
+	(((x) & BIT_MASK_DTIM_COUNT_VAP6_8821C)                                \
+	 << BIT_SHIFT_DTIM_COUNT_VAP6_8821C)
+#define BITS_DTIM_COUNT_VAP6_8821C                                             \
+	(BIT_MASK_DTIM_COUNT_VAP6_8821C << BIT_SHIFT_DTIM_COUNT_VAP6_8821C)
+#define BIT_CLEAR_DTIM_COUNT_VAP6_8821C(x) ((x) & (~BITS_DTIM_COUNT_VAP6_8821C))
+#define BIT_GET_DTIM_COUNT_VAP6_8821C(x)                                       \
+	(((x) >> BIT_SHIFT_DTIM_COUNT_VAP6_8821C) &                            \
+	 BIT_MASK_DTIM_COUNT_VAP6_8821C)
+#define BIT_SET_DTIM_COUNT_VAP6_8821C(x, v)                                    \
+	(BIT_CLEAR_DTIM_COUNT_VAP6_8821C(x) | BIT_DTIM_COUNT_VAP6_8821C(v))
+
+/* 2 REG_DTIM_COUNTER_VAP7_8821C */
+
+#define BIT_SHIFT_DTIM_COUNT_VAP7_8821C 0
+#define BIT_MASK_DTIM_COUNT_VAP7_8821C 0xff
+#define BIT_DTIM_COUNT_VAP7_8821C(x)                                           \
+	(((x) & BIT_MASK_DTIM_COUNT_VAP7_8821C)                                \
+	 << BIT_SHIFT_DTIM_COUNT_VAP7_8821C)
+#define BITS_DTIM_COUNT_VAP7_8821C                                             \
+	(BIT_MASK_DTIM_COUNT_VAP7_8821C << BIT_SHIFT_DTIM_COUNT_VAP7_8821C)
+#define BIT_CLEAR_DTIM_COUNT_VAP7_8821C(x) ((x) & (~BITS_DTIM_COUNT_VAP7_8821C))
+#define BIT_GET_DTIM_COUNT_VAP7_8821C(x)                                       \
+	(((x) >> BIT_SHIFT_DTIM_COUNT_VAP7_8821C) &                            \
+	 BIT_MASK_DTIM_COUNT_VAP7_8821C)
+#define BIT_SET_DTIM_COUNT_VAP7_8821C(x, v)                                    \
+	(BIT_CLEAR_DTIM_COUNT_VAP7_8821C(x) | BIT_DTIM_COUNT_VAP7_8821C(v))
+
+/* 2 REG_DIS_ATIM_8821C */
+#define BIT_DIS_ATIM_VAP7_8821C BIT(7)
+#define BIT_DIS_ATIM_VAP6_8821C BIT(6)
+#define BIT_DIS_ATIM_VAP5_8821C BIT(5)
+#define BIT_DIS_ATIM_VAP4_8821C BIT(4)
+#define BIT_DIS_ATIM_VAP3_8821C BIT(3)
+#define BIT_DIS_ATIM_VAP2_8821C BIT(2)
+#define BIT_DIS_ATIM_VAP1_8821C BIT(1)
+#define BIT_DIS_ATIM_ROOT_8821C BIT(0)
+
+/* 2 REG_EARLY_128US_8821C */
+
+#define BIT_SHIFT_TSFT_SEL_TIMER1_8821C 3
+#define BIT_MASK_TSFT_SEL_TIMER1_8821C 0x7
+#define BIT_TSFT_SEL_TIMER1_8821C(x)                                           \
+	(((x) & BIT_MASK_TSFT_SEL_TIMER1_8821C)                                \
+	 << BIT_SHIFT_TSFT_SEL_TIMER1_8821C)
+#define BITS_TSFT_SEL_TIMER1_8821C                                             \
+	(BIT_MASK_TSFT_SEL_TIMER1_8821C << BIT_SHIFT_TSFT_SEL_TIMER1_8821C)
+#define BIT_CLEAR_TSFT_SEL_TIMER1_8821C(x) ((x) & (~BITS_TSFT_SEL_TIMER1_8821C))
+#define BIT_GET_TSFT_SEL_TIMER1_8821C(x)                                       \
+	(((x) >> BIT_SHIFT_TSFT_SEL_TIMER1_8821C) &                            \
+	 BIT_MASK_TSFT_SEL_TIMER1_8821C)
+#define BIT_SET_TSFT_SEL_TIMER1_8821C(x, v)                                    \
+	(BIT_CLEAR_TSFT_SEL_TIMER1_8821C(x) | BIT_TSFT_SEL_TIMER1_8821C(v))
+
+#define BIT_SHIFT_EARLY_128US_8821C 0
+#define BIT_MASK_EARLY_128US_8821C 0x7
+#define BIT_EARLY_128US_8821C(x)                                               \
+	(((x) & BIT_MASK_EARLY_128US_8821C) << BIT_SHIFT_EARLY_128US_8821C)
+#define BITS_EARLY_128US_8821C                                                 \
+	(BIT_MASK_EARLY_128US_8821C << BIT_SHIFT_EARLY_128US_8821C)
+#define BIT_CLEAR_EARLY_128US_8821C(x) ((x) & (~BITS_EARLY_128US_8821C))
+#define BIT_GET_EARLY_128US_8821C(x)                                           \
+	(((x) >> BIT_SHIFT_EARLY_128US_8821C) & BIT_MASK_EARLY_128US_8821C)
+#define BIT_SET_EARLY_128US_8821C(x, v)                                        \
+	(BIT_CLEAR_EARLY_128US_8821C(x) | BIT_EARLY_128US_8821C(v))
+
+/* 2 REG_P2PPS1_CTRL_8821C */
+#define BIT_P2P1_CTW_ALLSTASLEEP_8821C BIT(7)
+#define BIT_P2P1_OFF_DISTX_EN_8821C BIT(6)
+#define BIT_P2P1_PWR_MGT_EN_8821C BIT(5)
+#define BIT_P2P1_NOA1_EN_8821C BIT(2)
+#define BIT_P2P1_NOA0_EN_8821C BIT(1)
+
+/* 2 REG_P2PPS2_CTRL_8821C */
+#define BIT_P2P2_CTW_ALLSTASLEEP_8821C BIT(7)
+#define BIT_P2P2_OFF_DISTX_EN_8821C BIT(6)
+#define BIT_P2P2_PWR_MGT_EN_8821C BIT(5)
+#define BIT_P2P2_NOA1_EN_8821C BIT(2)
+#define BIT_P2P2_NOA0_EN_8821C BIT(1)
+
+/* 2 REG_TIMER0_SRC_SEL_8821C */
+
+#define BIT_SHIFT_SYNC_CLI_SEL_8821C 4
+#define BIT_MASK_SYNC_CLI_SEL_8821C 0x7
+#define BIT_SYNC_CLI_SEL_8821C(x)                                              \
+	(((x) & BIT_MASK_SYNC_CLI_SEL_8821C) << BIT_SHIFT_SYNC_CLI_SEL_8821C)
+#define BITS_SYNC_CLI_SEL_8821C                                                \
+	(BIT_MASK_SYNC_CLI_SEL_8821C << BIT_SHIFT_SYNC_CLI_SEL_8821C)
+#define BIT_CLEAR_SYNC_CLI_SEL_8821C(x) ((x) & (~BITS_SYNC_CLI_SEL_8821C))
+#define BIT_GET_SYNC_CLI_SEL_8821C(x)                                          \
+	(((x) >> BIT_SHIFT_SYNC_CLI_SEL_8821C) & BIT_MASK_SYNC_CLI_SEL_8821C)
+#define BIT_SET_SYNC_CLI_SEL_8821C(x, v)                                       \
+	(BIT_CLEAR_SYNC_CLI_SEL_8821C(x) | BIT_SYNC_CLI_SEL_8821C(v))
+
+#define BIT_SHIFT_TSFT_SEL_TIMER0_8821C 0
+#define BIT_MASK_TSFT_SEL_TIMER0_8821C 0x7
+#define BIT_TSFT_SEL_TIMER0_8821C(x)                                           \
+	(((x) & BIT_MASK_TSFT_SEL_TIMER0_8821C)                                \
+	 << BIT_SHIFT_TSFT_SEL_TIMER0_8821C)
+#define BITS_TSFT_SEL_TIMER0_8821C                                             \
+	(BIT_MASK_TSFT_SEL_TIMER0_8821C << BIT_SHIFT_TSFT_SEL_TIMER0_8821C)
+#define BIT_CLEAR_TSFT_SEL_TIMER0_8821C(x) ((x) & (~BITS_TSFT_SEL_TIMER0_8821C))
+#define BIT_GET_TSFT_SEL_TIMER0_8821C(x)                                       \
+	(((x) >> BIT_SHIFT_TSFT_SEL_TIMER0_8821C) &                            \
+	 BIT_MASK_TSFT_SEL_TIMER0_8821C)
+#define BIT_SET_TSFT_SEL_TIMER0_8821C(x, v)                                    \
+	(BIT_CLEAR_TSFT_SEL_TIMER0_8821C(x) | BIT_TSFT_SEL_TIMER0_8821C(v))
+
+/* 2 REG_NOA_UNIT_SEL_8821C */
+
+#define BIT_SHIFT_NOA_UNIT2_SEL_8821C 8
+#define BIT_MASK_NOA_UNIT2_SEL_8821C 0x7
+#define BIT_NOA_UNIT2_SEL_8821C(x)                                             \
+	(((x) & BIT_MASK_NOA_UNIT2_SEL_8821C) << BIT_SHIFT_NOA_UNIT2_SEL_8821C)
+#define BITS_NOA_UNIT2_SEL_8821C                                               \
+	(BIT_MASK_NOA_UNIT2_SEL_8821C << BIT_SHIFT_NOA_UNIT2_SEL_8821C)
+#define BIT_CLEAR_NOA_UNIT2_SEL_8821C(x) ((x) & (~BITS_NOA_UNIT2_SEL_8821C))
+#define BIT_GET_NOA_UNIT2_SEL_8821C(x)                                         \
+	(((x) >> BIT_SHIFT_NOA_UNIT2_SEL_8821C) & BIT_MASK_NOA_UNIT2_SEL_8821C)
+#define BIT_SET_NOA_UNIT2_SEL_8821C(x, v)                                      \
+	(BIT_CLEAR_NOA_UNIT2_SEL_8821C(x) | BIT_NOA_UNIT2_SEL_8821C(v))
+
+#define BIT_SHIFT_NOA_UNIT1_SEL_8821C 4
+#define BIT_MASK_NOA_UNIT1_SEL_8821C 0x7
+#define BIT_NOA_UNIT1_SEL_8821C(x)                                             \
+	(((x) & BIT_MASK_NOA_UNIT1_SEL_8821C) << BIT_SHIFT_NOA_UNIT1_SEL_8821C)
+#define BITS_NOA_UNIT1_SEL_8821C                                               \
+	(BIT_MASK_NOA_UNIT1_SEL_8821C << BIT_SHIFT_NOA_UNIT1_SEL_8821C)
+#define BIT_CLEAR_NOA_UNIT1_SEL_8821C(x) ((x) & (~BITS_NOA_UNIT1_SEL_8821C))
+#define BIT_GET_NOA_UNIT1_SEL_8821C(x)                                         \
+	(((x) >> BIT_SHIFT_NOA_UNIT1_SEL_8821C) & BIT_MASK_NOA_UNIT1_SEL_8821C)
+#define BIT_SET_NOA_UNIT1_SEL_8821C(x, v)                                      \
+	(BIT_CLEAR_NOA_UNIT1_SEL_8821C(x) | BIT_NOA_UNIT1_SEL_8821C(v))
+
+#define BIT_SHIFT_NOA_UNIT0_SEL_8821C 0
+#define BIT_MASK_NOA_UNIT0_SEL_8821C 0x7
+#define BIT_NOA_UNIT0_SEL_8821C(x)                                             \
+	(((x) & BIT_MASK_NOA_UNIT0_SEL_8821C) << BIT_SHIFT_NOA_UNIT0_SEL_8821C)
+#define BITS_NOA_UNIT0_SEL_8821C                                               \
+	(BIT_MASK_NOA_UNIT0_SEL_8821C << BIT_SHIFT_NOA_UNIT0_SEL_8821C)
+#define BIT_CLEAR_NOA_UNIT0_SEL_8821C(x) ((x) & (~BITS_NOA_UNIT0_SEL_8821C))
+#define BIT_GET_NOA_UNIT0_SEL_8821C(x)                                         \
+	(((x) >> BIT_SHIFT_NOA_UNIT0_SEL_8821C) & BIT_MASK_NOA_UNIT0_SEL_8821C)
+#define BIT_SET_NOA_UNIT0_SEL_8821C(x, v)                                      \
+	(BIT_CLEAR_NOA_UNIT0_SEL_8821C(x) | BIT_NOA_UNIT0_SEL_8821C(v))
+
+/* 2 REG_P2POFF_DIS_TXTIME_8821C */
+
+#define BIT_SHIFT_P2POFF_DIS_TXTIME_8821C 0
+#define BIT_MASK_P2POFF_DIS_TXTIME_8821C 0xff
+#define BIT_P2POFF_DIS_TXTIME_8821C(x)                                         \
+	(((x) & BIT_MASK_P2POFF_DIS_TXTIME_8821C)                              \
+	 << BIT_SHIFT_P2POFF_DIS_TXTIME_8821C)
+#define BITS_P2POFF_DIS_TXTIME_8821C                                           \
+	(BIT_MASK_P2POFF_DIS_TXTIME_8821C << BIT_SHIFT_P2POFF_DIS_TXTIME_8821C)
+#define BIT_CLEAR_P2POFF_DIS_TXTIME_8821C(x)                                   \
+	((x) & (~BITS_P2POFF_DIS_TXTIME_8821C))
+#define BIT_GET_P2POFF_DIS_TXTIME_8821C(x)                                     \
+	(((x) >> BIT_SHIFT_P2POFF_DIS_TXTIME_8821C) &                          \
+	 BIT_MASK_P2POFF_DIS_TXTIME_8821C)
+#define BIT_SET_P2POFF_DIS_TXTIME_8821C(x, v)                                  \
+	(BIT_CLEAR_P2POFF_DIS_TXTIME_8821C(x) | BIT_P2POFF_DIS_TXTIME_8821C(v))
+
+/* 2 REG_MBSSID_BCN_SPACE2_8821C */
+
+#define BIT_SHIFT_BCN_SPACE_CLINT2_8821C 16
+#define BIT_MASK_BCN_SPACE_CLINT2_8821C 0xfff
+#define BIT_BCN_SPACE_CLINT2_8821C(x)                                          \
+	(((x) & BIT_MASK_BCN_SPACE_CLINT2_8821C)                               \
+	 << BIT_SHIFT_BCN_SPACE_CLINT2_8821C)
+#define BITS_BCN_SPACE_CLINT2_8821C                                            \
+	(BIT_MASK_BCN_SPACE_CLINT2_8821C << BIT_SHIFT_BCN_SPACE_CLINT2_8821C)
+#define BIT_CLEAR_BCN_SPACE_CLINT2_8821C(x)                                    \
+	((x) & (~BITS_BCN_SPACE_CLINT2_8821C))
+#define BIT_GET_BCN_SPACE_CLINT2_8821C(x)                                      \
+	(((x) >> BIT_SHIFT_BCN_SPACE_CLINT2_8821C) &                           \
+	 BIT_MASK_BCN_SPACE_CLINT2_8821C)
+#define BIT_SET_BCN_SPACE_CLINT2_8821C(x, v)                                   \
+	(BIT_CLEAR_BCN_SPACE_CLINT2_8821C(x) | BIT_BCN_SPACE_CLINT2_8821C(v))
+
+#define BIT_SHIFT_BCN_SPACE_CLINT1_8821C 0
+#define BIT_MASK_BCN_SPACE_CLINT1_8821C 0xfff
+#define BIT_BCN_SPACE_CLINT1_8821C(x)                                          \
+	(((x) & BIT_MASK_BCN_SPACE_CLINT1_8821C)                               \
+	 << BIT_SHIFT_BCN_SPACE_CLINT1_8821C)
+#define BITS_BCN_SPACE_CLINT1_8821C                                            \
+	(BIT_MASK_BCN_SPACE_CLINT1_8821C << BIT_SHIFT_BCN_SPACE_CLINT1_8821C)
+#define BIT_CLEAR_BCN_SPACE_CLINT1_8821C(x)                                    \
+	((x) & (~BITS_BCN_SPACE_CLINT1_8821C))
+#define BIT_GET_BCN_SPACE_CLINT1_8821C(x)                                      \
+	(((x) >> BIT_SHIFT_BCN_SPACE_CLINT1_8821C) &                           \
+	 BIT_MASK_BCN_SPACE_CLINT1_8821C)
+#define BIT_SET_BCN_SPACE_CLINT1_8821C(x, v)                                   \
+	(BIT_CLEAR_BCN_SPACE_CLINT1_8821C(x) | BIT_BCN_SPACE_CLINT1_8821C(v))
+
+/* 2 REG_MBSSID_BCN_SPACE3_8821C */
+
+#define BIT_SHIFT_SUB_BCN_SPACE_8821C 16
+#define BIT_MASK_SUB_BCN_SPACE_8821C 0xff
+#define BIT_SUB_BCN_SPACE_8821C(x)                                             \
+	(((x) & BIT_MASK_SUB_BCN_SPACE_8821C) << BIT_SHIFT_SUB_BCN_SPACE_8821C)
+#define BITS_SUB_BCN_SPACE_8821C                                               \
+	(BIT_MASK_SUB_BCN_SPACE_8821C << BIT_SHIFT_SUB_BCN_SPACE_8821C)
+#define BIT_CLEAR_SUB_BCN_SPACE_8821C(x) ((x) & (~BITS_SUB_BCN_SPACE_8821C))
+#define BIT_GET_SUB_BCN_SPACE_8821C(x)                                         \
+	(((x) >> BIT_SHIFT_SUB_BCN_SPACE_8821C) & BIT_MASK_SUB_BCN_SPACE_8821C)
+#define BIT_SET_SUB_BCN_SPACE_8821C(x, v)                                      \
+	(BIT_CLEAR_SUB_BCN_SPACE_8821C(x) | BIT_SUB_BCN_SPACE_8821C(v))
+
+#define BIT_SHIFT_BCN_SPACE_CLINT3_8821C 0
+#define BIT_MASK_BCN_SPACE_CLINT3_8821C 0xfff
+#define BIT_BCN_SPACE_CLINT3_8821C(x)                                          \
+	(((x) & BIT_MASK_BCN_SPACE_CLINT3_8821C)                               \
+	 << BIT_SHIFT_BCN_SPACE_CLINT3_8821C)
+#define BITS_BCN_SPACE_CLINT3_8821C                                            \
+	(BIT_MASK_BCN_SPACE_CLINT3_8821C << BIT_SHIFT_BCN_SPACE_CLINT3_8821C)
+#define BIT_CLEAR_BCN_SPACE_CLINT3_8821C(x)                                    \
+	((x) & (~BITS_BCN_SPACE_CLINT3_8821C))
+#define BIT_GET_BCN_SPACE_CLINT3_8821C(x)                                      \
+	(((x) >> BIT_SHIFT_BCN_SPACE_CLINT3_8821C) &                           \
+	 BIT_MASK_BCN_SPACE_CLINT3_8821C)
+#define BIT_SET_BCN_SPACE_CLINT3_8821C(x, v)                                   \
+	(BIT_CLEAR_BCN_SPACE_CLINT3_8821C(x) | BIT_BCN_SPACE_CLINT3_8821C(v))
+
+/* 2 REG_ACMHWCTRL_8821C */
+#define BIT_BEQ_ACM_STATUS_8821C BIT(7)
+#define BIT_VIQ_ACM_STATUS_8821C BIT(6)
+#define BIT_VOQ_ACM_STATUS_8821C BIT(5)
+#define BIT_BEQ_ACM_EN_8821C BIT(3)
+#define BIT_VIQ_ACM_EN_8821C BIT(2)
+#define BIT_VOQ_ACM_EN_8821C BIT(1)
+#define BIT_ACMHWEN_8821C BIT(0)
+
+/* 2 REG_ACMRSTCTRL_8821C */
+#define BIT_BE_ACM_RESET_USED_TIME_8821C BIT(2)
+#define BIT_VI_ACM_RESET_USED_TIME_8821C BIT(1)
+#define BIT_VO_ACM_RESET_USED_TIME_8821C BIT(0)
+
+/* 2 REG_ACMAVG_8821C */
+
+#define BIT_SHIFT_AVGPERIOD_8821C 0
+#define BIT_MASK_AVGPERIOD_8821C 0xffff
+#define BIT_AVGPERIOD_8821C(x)                                                 \
+	(((x) & BIT_MASK_AVGPERIOD_8821C) << BIT_SHIFT_AVGPERIOD_8821C)
+#define BITS_AVGPERIOD_8821C                                                   \
+	(BIT_MASK_AVGPERIOD_8821C << BIT_SHIFT_AVGPERIOD_8821C)
+#define BIT_CLEAR_AVGPERIOD_8821C(x) ((x) & (~BITS_AVGPERIOD_8821C))
+#define BIT_GET_AVGPERIOD_8821C(x)                                             \
+	(((x) >> BIT_SHIFT_AVGPERIOD_8821C) & BIT_MASK_AVGPERIOD_8821C)
+#define BIT_SET_AVGPERIOD_8821C(x, v)                                          \
+	(BIT_CLEAR_AVGPERIOD_8821C(x) | BIT_AVGPERIOD_8821C(v))
+
+/* 2 REG_VO_ADMTIME_8821C */
+
+#define BIT_SHIFT_VO_ADMITTED_TIME_8821C 0
+#define BIT_MASK_VO_ADMITTED_TIME_8821C 0xffff
+#define BIT_VO_ADMITTED_TIME_8821C(x)                                          \
+	(((x) & BIT_MASK_VO_ADMITTED_TIME_8821C)                               \
+	 << BIT_SHIFT_VO_ADMITTED_TIME_8821C)
+#define BITS_VO_ADMITTED_TIME_8821C                                            \
+	(BIT_MASK_VO_ADMITTED_TIME_8821C << BIT_SHIFT_VO_ADMITTED_TIME_8821C)
+#define BIT_CLEAR_VO_ADMITTED_TIME_8821C(x)                                    \
+	((x) & (~BITS_VO_ADMITTED_TIME_8821C))
+#define BIT_GET_VO_ADMITTED_TIME_8821C(x)                                      \
+	(((x) >> BIT_SHIFT_VO_ADMITTED_TIME_8821C) &                           \
+	 BIT_MASK_VO_ADMITTED_TIME_8821C)
+#define BIT_SET_VO_ADMITTED_TIME_8821C(x, v)                                   \
+	(BIT_CLEAR_VO_ADMITTED_TIME_8821C(x) | BIT_VO_ADMITTED_TIME_8821C(v))
+
+/* 2 REG_VI_ADMTIME_8821C */
+
+#define BIT_SHIFT_VI_ADMITTED_TIME_8821C 0
+#define BIT_MASK_VI_ADMITTED_TIME_8821C 0xffff
+#define BIT_VI_ADMITTED_TIME_8821C(x)                                          \
+	(((x) & BIT_MASK_VI_ADMITTED_TIME_8821C)                               \
+	 << BIT_SHIFT_VI_ADMITTED_TIME_8821C)
+#define BITS_VI_ADMITTED_TIME_8821C                                            \
+	(BIT_MASK_VI_ADMITTED_TIME_8821C << BIT_SHIFT_VI_ADMITTED_TIME_8821C)
+#define BIT_CLEAR_VI_ADMITTED_TIME_8821C(x)                                    \
+	((x) & (~BITS_VI_ADMITTED_TIME_8821C))
+#define BIT_GET_VI_ADMITTED_TIME_8821C(x)                                      \
+	(((x) >> BIT_SHIFT_VI_ADMITTED_TIME_8821C) &                           \
+	 BIT_MASK_VI_ADMITTED_TIME_8821C)
+#define BIT_SET_VI_ADMITTED_TIME_8821C(x, v)                                   \
+	(BIT_CLEAR_VI_ADMITTED_TIME_8821C(x) | BIT_VI_ADMITTED_TIME_8821C(v))
+
+/* 2 REG_BE_ADMTIME_8821C */
+
+#define BIT_SHIFT_BE_ADMITTED_TIME_8821C 0
+#define BIT_MASK_BE_ADMITTED_TIME_8821C 0xffff
+#define BIT_BE_ADMITTED_TIME_8821C(x)                                          \
+	(((x) & BIT_MASK_BE_ADMITTED_TIME_8821C)                               \
+	 << BIT_SHIFT_BE_ADMITTED_TIME_8821C)
+#define BITS_BE_ADMITTED_TIME_8821C                                            \
+	(BIT_MASK_BE_ADMITTED_TIME_8821C << BIT_SHIFT_BE_ADMITTED_TIME_8821C)
+#define BIT_CLEAR_BE_ADMITTED_TIME_8821C(x)                                    \
+	((x) & (~BITS_BE_ADMITTED_TIME_8821C))
+#define BIT_GET_BE_ADMITTED_TIME_8821C(x)                                      \
+	(((x) >> BIT_SHIFT_BE_ADMITTED_TIME_8821C) &                           \
+	 BIT_MASK_BE_ADMITTED_TIME_8821C)
+#define BIT_SET_BE_ADMITTED_TIME_8821C(x, v)                                   \
+	(BIT_CLEAR_BE_ADMITTED_TIME_8821C(x) | BIT_BE_ADMITTED_TIME_8821C(v))
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_EDCA_RANDOM_GEN_8821C */
+
+#define BIT_SHIFT_RANDOM_GEN_8821C 0
+#define BIT_MASK_RANDOM_GEN_8821C 0xffffff
+#define BIT_RANDOM_GEN_8821C(x)                                                \
+	(((x) & BIT_MASK_RANDOM_GEN_8821C) << BIT_SHIFT_RANDOM_GEN_8821C)
+#define BITS_RANDOM_GEN_8821C                                                  \
+	(BIT_MASK_RANDOM_GEN_8821C << BIT_SHIFT_RANDOM_GEN_8821C)
+#define BIT_CLEAR_RANDOM_GEN_8821C(x) ((x) & (~BITS_RANDOM_GEN_8821C))
+#define BIT_GET_RANDOM_GEN_8821C(x)                                            \
+	(((x) >> BIT_SHIFT_RANDOM_GEN_8821C) & BIT_MASK_RANDOM_GEN_8821C)
+#define BIT_SET_RANDOM_GEN_8821C(x, v)                                         \
+	(BIT_CLEAR_RANDOM_GEN_8821C(x) | BIT_RANDOM_GEN_8821C(v))
+
+/* 2 REG_TXCMD_NOA_SEL_8821C */
+
+#define BIT_SHIFT_NOA_SEL_V2_8821C 4
+#define BIT_MASK_NOA_SEL_V2_8821C 0x7
+#define BIT_NOA_SEL_V2_8821C(x)                                                \
+	(((x) & BIT_MASK_NOA_SEL_V2_8821C) << BIT_SHIFT_NOA_SEL_V2_8821C)
+#define BITS_NOA_SEL_V2_8821C                                                  \
+	(BIT_MASK_NOA_SEL_V2_8821C << BIT_SHIFT_NOA_SEL_V2_8821C)
+#define BIT_CLEAR_NOA_SEL_V2_8821C(x) ((x) & (~BITS_NOA_SEL_V2_8821C))
+#define BIT_GET_NOA_SEL_V2_8821C(x)                                            \
+	(((x) >> BIT_SHIFT_NOA_SEL_V2_8821C) & BIT_MASK_NOA_SEL_V2_8821C)
+#define BIT_SET_NOA_SEL_V2_8821C(x, v)                                         \
+	(BIT_CLEAR_NOA_SEL_V2_8821C(x) | BIT_NOA_SEL_V2_8821C(v))
+
+#define BIT_SHIFT_TXCMD_SEG_SEL_8821C 0
+#define BIT_MASK_TXCMD_SEG_SEL_8821C 0xf
+#define BIT_TXCMD_SEG_SEL_8821C(x)                                             \
+	(((x) & BIT_MASK_TXCMD_SEG_SEL_8821C) << BIT_SHIFT_TXCMD_SEG_SEL_8821C)
+#define BITS_TXCMD_SEG_SEL_8821C                                               \
+	(BIT_MASK_TXCMD_SEG_SEL_8821C << BIT_SHIFT_TXCMD_SEG_SEL_8821C)
+#define BIT_CLEAR_TXCMD_SEG_SEL_8821C(x) ((x) & (~BITS_TXCMD_SEG_SEL_8821C))
+#define BIT_GET_TXCMD_SEG_SEL_8821C(x)                                         \
+	(((x) >> BIT_SHIFT_TXCMD_SEG_SEL_8821C) & BIT_MASK_TXCMD_SEG_SEL_8821C)
+#define BIT_SET_TXCMD_SEG_SEL_8821C(x, v)                                      \
+	(BIT_CLEAR_TXCMD_SEG_SEL_8821C(x) | BIT_TXCMD_SEG_SEL_8821C(v))
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOA_PARAM_8821C */
+
+#define BIT_SHIFT_NOA_DURATION_V1_8821C 0
+#define BIT_MASK_NOA_DURATION_V1_8821C 0xffffffffL
+#define BIT_NOA_DURATION_V1_8821C(x)                                           \
+	(((x) & BIT_MASK_NOA_DURATION_V1_8821C)                                \
+	 << BIT_SHIFT_NOA_DURATION_V1_8821C)
+#define BITS_NOA_DURATION_V1_8821C                                             \
+	(BIT_MASK_NOA_DURATION_V1_8821C << BIT_SHIFT_NOA_DURATION_V1_8821C)
+#define BIT_CLEAR_NOA_DURATION_V1_8821C(x) ((x) & (~BITS_NOA_DURATION_V1_8821C))
+#define BIT_GET_NOA_DURATION_V1_8821C(x)                                       \
+	(((x) >> BIT_SHIFT_NOA_DURATION_V1_8821C) &                            \
+	 BIT_MASK_NOA_DURATION_V1_8821C)
+#define BIT_SET_NOA_DURATION_V1_8821C(x, v)                                    \
+	(BIT_CLEAR_NOA_DURATION_V1_8821C(x) | BIT_NOA_DURATION_V1_8821C(v))
+
+/* 2 REG_NOA_PARAM_1_8821C */
+
+#define BIT_SHIFT_NOA_INTERVAL_V1_8821C 0
+#define BIT_MASK_NOA_INTERVAL_V1_8821C 0xffffffffL
+#define BIT_NOA_INTERVAL_V1_8821C(x)                                           \
+	(((x) & BIT_MASK_NOA_INTERVAL_V1_8821C)                                \
+	 << BIT_SHIFT_NOA_INTERVAL_V1_8821C)
+#define BITS_NOA_INTERVAL_V1_8821C                                             \
+	(BIT_MASK_NOA_INTERVAL_V1_8821C << BIT_SHIFT_NOA_INTERVAL_V1_8821C)
+#define BIT_CLEAR_NOA_INTERVAL_V1_8821C(x) ((x) & (~BITS_NOA_INTERVAL_V1_8821C))
+#define BIT_GET_NOA_INTERVAL_V1_8821C(x)                                       \
+	(((x) >> BIT_SHIFT_NOA_INTERVAL_V1_8821C) &                            \
+	 BIT_MASK_NOA_INTERVAL_V1_8821C)
+#define BIT_SET_NOA_INTERVAL_V1_8821C(x, v)                                    \
+	(BIT_CLEAR_NOA_INTERVAL_V1_8821C(x) | BIT_NOA_INTERVAL_V1_8821C(v))
+
+/* 2 REG_NOA_PARAM_2_8821C */
+
+#define BIT_SHIFT_NOA_START_TIME_V1_8821C 0
+#define BIT_MASK_NOA_START_TIME_V1_8821C 0xffffffffL
+#define BIT_NOA_START_TIME_V1_8821C(x)                                         \
+	(((x) & BIT_MASK_NOA_START_TIME_V1_8821C)                              \
+	 << BIT_SHIFT_NOA_START_TIME_V1_8821C)
+#define BITS_NOA_START_TIME_V1_8821C                                           \
+	(BIT_MASK_NOA_START_TIME_V1_8821C << BIT_SHIFT_NOA_START_TIME_V1_8821C)
+#define BIT_CLEAR_NOA_START_TIME_V1_8821C(x)                                   \
+	((x) & (~BITS_NOA_START_TIME_V1_8821C))
+#define BIT_GET_NOA_START_TIME_V1_8821C(x)                                     \
+	(((x) >> BIT_SHIFT_NOA_START_TIME_V1_8821C) &                          \
+	 BIT_MASK_NOA_START_TIME_V1_8821C)
+#define BIT_SET_NOA_START_TIME_V1_8821C(x, v)                                  \
+	(BIT_CLEAR_NOA_START_TIME_V1_8821C(x) | BIT_NOA_START_TIME_V1_8821C(v))
+
+/* 2 REG_NOA_PARAM_3_8821C */
+
+#define BIT_SHIFT_NOA_COUNT_V1_8821C 0
+#define BIT_MASK_NOA_COUNT_V1_8821C 0xffffffffL
+#define BIT_NOA_COUNT_V1_8821C(x)                                              \
+	(((x) & BIT_MASK_NOA_COUNT_V1_8821C) << BIT_SHIFT_NOA_COUNT_V1_8821C)
+#define BITS_NOA_COUNT_V1_8821C                                                \
+	(BIT_MASK_NOA_COUNT_V1_8821C << BIT_SHIFT_NOA_COUNT_V1_8821C)
+#define BIT_CLEAR_NOA_COUNT_V1_8821C(x) ((x) & (~BITS_NOA_COUNT_V1_8821C))
+#define BIT_GET_NOA_COUNT_V1_8821C(x)                                          \
+	(((x) >> BIT_SHIFT_NOA_COUNT_V1_8821C) & BIT_MASK_NOA_COUNT_V1_8821C)
+#define BIT_SET_NOA_COUNT_V1_8821C(x, v)                                       \
+	(BIT_CLEAR_NOA_COUNT_V1_8821C(x) | BIT_NOA_COUNT_V1_8821C(v))
+
+/* 2 REG_P2P_RST_8821C */
+#define BIT_P2P2_PWR_RST1_8821C BIT(5)
+#define BIT_P2P2_PWR_RST0_8821C BIT(4)
+#define BIT_P2P1_PWR_RST1_8821C BIT(3)
+#define BIT_P2P1_PWR_RST0_8821C BIT(2)
+#define BIT_P2P_PWR_RST1_V1_8821C BIT(1)
+#define BIT_P2P_PWR_RST0_V1_8821C BIT(0)
+
+/* 2 REG_SCHEDULER_RST_8821C */
+#define BIT_SYNC_CLI_ONCE_RIGHT_NOW_8821C BIT(2)
+#define BIT_SYNC_CLI_ONCE_BY_TBTT_8821C BIT(1)
+#define BIT_SCHEDULER_RST_V1_8821C BIT(0)
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_SCH_TXCMD_8821C */
+
+#define BIT_SHIFT_SCH_TXCMD_8821C 0
+#define BIT_MASK_SCH_TXCMD_8821C 0xffffffffL
+#define BIT_SCH_TXCMD_8821C(x)                                                 \
+	(((x) & BIT_MASK_SCH_TXCMD_8821C) << BIT_SHIFT_SCH_TXCMD_8821C)
+#define BITS_SCH_TXCMD_8821C                                                   \
+	(BIT_MASK_SCH_TXCMD_8821C << BIT_SHIFT_SCH_TXCMD_8821C)
+#define BIT_CLEAR_SCH_TXCMD_8821C(x) ((x) & (~BITS_SCH_TXCMD_8821C))
+#define BIT_GET_SCH_TXCMD_8821C(x)                                             \
+	(((x) >> BIT_SHIFT_SCH_TXCMD_8821C) & BIT_MASK_SCH_TXCMD_8821C)
+#define BIT_SET_SCH_TXCMD_8821C(x, v)                                          \
+	(BIT_CLEAR_SCH_TXCMD_8821C(x) | BIT_SCH_TXCMD_8821C(v))
+
+/* 2 REG_PAGE5_DUMMY_8821C */
+#define BIT_ECO_TXOP_BREAK_FORCE_CFEND_8821C BIT(0)
+
+/* 2 REG_CPUMGQ_TX_TIMER_8821C */
+
+#define BIT_SHIFT_CPUMGQ_TX_TIMER_V1_8821C 0
+#define BIT_MASK_CPUMGQ_TX_TIMER_V1_8821C 0xffffffffL
+#define BIT_CPUMGQ_TX_TIMER_V1_8821C(x)                                        \
+	(((x) & BIT_MASK_CPUMGQ_TX_TIMER_V1_8821C)                             \
+	 << BIT_SHIFT_CPUMGQ_TX_TIMER_V1_8821C)
+#define BITS_CPUMGQ_TX_TIMER_V1_8821C                                          \
+	(BIT_MASK_CPUMGQ_TX_TIMER_V1_8821C                                     \
+	 << BIT_SHIFT_CPUMGQ_TX_TIMER_V1_8821C)
+#define BIT_CLEAR_CPUMGQ_TX_TIMER_V1_8821C(x)                                  \
+	((x) & (~BITS_CPUMGQ_TX_TIMER_V1_8821C))
+#define BIT_GET_CPUMGQ_TX_TIMER_V1_8821C(x)                                    \
+	(((x) >> BIT_SHIFT_CPUMGQ_TX_TIMER_V1_8821C) &                         \
+	 BIT_MASK_CPUMGQ_TX_TIMER_V1_8821C)
+#define BIT_SET_CPUMGQ_TX_TIMER_V1_8821C(x, v)                                 \
+	(BIT_CLEAR_CPUMGQ_TX_TIMER_V1_8821C(x) |                               \
+	 BIT_CPUMGQ_TX_TIMER_V1_8821C(v))
+
+/* 2 REG_PS_TIMER_A_8821C */
+
+#define BIT_SHIFT_PS_TIMER_A_V1_8821C 0
+#define BIT_MASK_PS_TIMER_A_V1_8821C 0xffffffffL
+#define BIT_PS_TIMER_A_V1_8821C(x)                                             \
+	(((x) & BIT_MASK_PS_TIMER_A_V1_8821C) << BIT_SHIFT_PS_TIMER_A_V1_8821C)
+#define BITS_PS_TIMER_A_V1_8821C                                               \
+	(BIT_MASK_PS_TIMER_A_V1_8821C << BIT_SHIFT_PS_TIMER_A_V1_8821C)
+#define BIT_CLEAR_PS_TIMER_A_V1_8821C(x) ((x) & (~BITS_PS_TIMER_A_V1_8821C))
+#define BIT_GET_PS_TIMER_A_V1_8821C(x)                                         \
+	(((x) >> BIT_SHIFT_PS_TIMER_A_V1_8821C) & BIT_MASK_PS_TIMER_A_V1_8821C)
+#define BIT_SET_PS_TIMER_A_V1_8821C(x, v)                                      \
+	(BIT_CLEAR_PS_TIMER_A_V1_8821C(x) | BIT_PS_TIMER_A_V1_8821C(v))
+
+/* 2 REG_PS_TIMER_B_8821C */
+
+#define BIT_SHIFT_PS_TIMER_B_V1_8821C 0
+#define BIT_MASK_PS_TIMER_B_V1_8821C 0xffffffffL
+#define BIT_PS_TIMER_B_V1_8821C(x)                                             \
+	(((x) & BIT_MASK_PS_TIMER_B_V1_8821C) << BIT_SHIFT_PS_TIMER_B_V1_8821C)
+#define BITS_PS_TIMER_B_V1_8821C                                               \
+	(BIT_MASK_PS_TIMER_B_V1_8821C << BIT_SHIFT_PS_TIMER_B_V1_8821C)
+#define BIT_CLEAR_PS_TIMER_B_V1_8821C(x) ((x) & (~BITS_PS_TIMER_B_V1_8821C))
+#define BIT_GET_PS_TIMER_B_V1_8821C(x)                                         \
+	(((x) >> BIT_SHIFT_PS_TIMER_B_V1_8821C) & BIT_MASK_PS_TIMER_B_V1_8821C)
+#define BIT_SET_PS_TIMER_B_V1_8821C(x, v)                                      \
+	(BIT_CLEAR_PS_TIMER_B_V1_8821C(x) | BIT_PS_TIMER_B_V1_8821C(v))
+
+/* 2 REG_PS_TIMER_C_8821C */
+
+#define BIT_SHIFT_PS_TIMER_C_V1_8821C 0
+#define BIT_MASK_PS_TIMER_C_V1_8821C 0xffffffffL
+#define BIT_PS_TIMER_C_V1_8821C(x)                                             \
+	(((x) & BIT_MASK_PS_TIMER_C_V1_8821C) << BIT_SHIFT_PS_TIMER_C_V1_8821C)
+#define BITS_PS_TIMER_C_V1_8821C                                               \
+	(BIT_MASK_PS_TIMER_C_V1_8821C << BIT_SHIFT_PS_TIMER_C_V1_8821C)
+#define BIT_CLEAR_PS_TIMER_C_V1_8821C(x) ((x) & (~BITS_PS_TIMER_C_V1_8821C))
+#define BIT_GET_PS_TIMER_C_V1_8821C(x)                                         \
+	(((x) >> BIT_SHIFT_PS_TIMER_C_V1_8821C) & BIT_MASK_PS_TIMER_C_V1_8821C)
+#define BIT_SET_PS_TIMER_C_V1_8821C(x, v)                                      \
+	(BIT_CLEAR_PS_TIMER_C_V1_8821C(x) | BIT_PS_TIMER_C_V1_8821C(v))
+
+/* 2 REG_PS_TIMER_ABC_CPUMGQ_TIMER_CRTL_8821C */
+#define BIT_CPUMGQ_TIMER_EN_8821C BIT(31)
+#define BIT_CPUMGQ_TX_EN_8821C BIT(28)
+
+#define BIT_SHIFT_CPUMGQ_TIMER_TSF_SEL_8821C 24
+#define BIT_MASK_CPUMGQ_TIMER_TSF_SEL_8821C 0x7
+#define BIT_CPUMGQ_TIMER_TSF_SEL_8821C(x)                                      \
+	(((x) & BIT_MASK_CPUMGQ_TIMER_TSF_SEL_8821C)                           \
+	 << BIT_SHIFT_CPUMGQ_TIMER_TSF_SEL_8821C)
+#define BITS_CPUMGQ_TIMER_TSF_SEL_8821C                                        \
+	(BIT_MASK_CPUMGQ_TIMER_TSF_SEL_8821C                                   \
+	 << BIT_SHIFT_CPUMGQ_TIMER_TSF_SEL_8821C)
+#define BIT_CLEAR_CPUMGQ_TIMER_TSF_SEL_8821C(x)                                \
+	((x) & (~BITS_CPUMGQ_TIMER_TSF_SEL_8821C))
+#define BIT_GET_CPUMGQ_TIMER_TSF_SEL_8821C(x)                                  \
+	(((x) >> BIT_SHIFT_CPUMGQ_TIMER_TSF_SEL_8821C) &                       \
+	 BIT_MASK_CPUMGQ_TIMER_TSF_SEL_8821C)
+#define BIT_SET_CPUMGQ_TIMER_TSF_SEL_8821C(x, v)                               \
+	(BIT_CLEAR_CPUMGQ_TIMER_TSF_SEL_8821C(x) |                             \
+	 BIT_CPUMGQ_TIMER_TSF_SEL_8821C(v))
+
+#define BIT_PS_TIMER_C_EN_8821C BIT(23)
+
+#define BIT_SHIFT_PS_TIMER_C_TSF_SEL_8821C 16
+#define BIT_MASK_PS_TIMER_C_TSF_SEL_8821C 0x7
+#define BIT_PS_TIMER_C_TSF_SEL_8821C(x)                                        \
+	(((x) & BIT_MASK_PS_TIMER_C_TSF_SEL_8821C)                             \
+	 << BIT_SHIFT_PS_TIMER_C_TSF_SEL_8821C)
+#define BITS_PS_TIMER_C_TSF_SEL_8821C                                          \
+	(BIT_MASK_PS_TIMER_C_TSF_SEL_8821C                                     \
+	 << BIT_SHIFT_PS_TIMER_C_TSF_SEL_8821C)
+#define BIT_CLEAR_PS_TIMER_C_TSF_SEL_8821C(x)                                  \
+	((x) & (~BITS_PS_TIMER_C_TSF_SEL_8821C))
+#define BIT_GET_PS_TIMER_C_TSF_SEL_8821C(x)                                    \
+	(((x) >> BIT_SHIFT_PS_TIMER_C_TSF_SEL_8821C) &                         \
+	 BIT_MASK_PS_TIMER_C_TSF_SEL_8821C)
+#define BIT_SET_PS_TIMER_C_TSF_SEL_8821C(x, v)                                 \
+	(BIT_CLEAR_PS_TIMER_C_TSF_SEL_8821C(x) |                               \
+	 BIT_PS_TIMER_C_TSF_SEL_8821C(v))
+
+#define BIT_PS_TIMER_B_EN_8821C BIT(15)
+
+#define BIT_SHIFT_PS_TIMER_B_TSF_SEL_8821C 8
+#define BIT_MASK_PS_TIMER_B_TSF_SEL_8821C 0x7
+#define BIT_PS_TIMER_B_TSF_SEL_8821C(x)                                        \
+	(((x) & BIT_MASK_PS_TIMER_B_TSF_SEL_8821C)                             \
+	 << BIT_SHIFT_PS_TIMER_B_TSF_SEL_8821C)
+#define BITS_PS_TIMER_B_TSF_SEL_8821C                                          \
+	(BIT_MASK_PS_TIMER_B_TSF_SEL_8821C                                     \
+	 << BIT_SHIFT_PS_TIMER_B_TSF_SEL_8821C)
+#define BIT_CLEAR_PS_TIMER_B_TSF_SEL_8821C(x)                                  \
+	((x) & (~BITS_PS_TIMER_B_TSF_SEL_8821C))
+#define BIT_GET_PS_TIMER_B_TSF_SEL_8821C(x)                                    \
+	(((x) >> BIT_SHIFT_PS_TIMER_B_TSF_SEL_8821C) &                         \
+	 BIT_MASK_PS_TIMER_B_TSF_SEL_8821C)
+#define BIT_SET_PS_TIMER_B_TSF_SEL_8821C(x, v)                                 \
+	(BIT_CLEAR_PS_TIMER_B_TSF_SEL_8821C(x) |                               \
+	 BIT_PS_TIMER_B_TSF_SEL_8821C(v))
+
+#define BIT_PS_TIMER_A_EN_8821C BIT(7)
+
+#define BIT_SHIFT_PS_TIMER_A_TSF_SEL_8821C 0
+#define BIT_MASK_PS_TIMER_A_TSF_SEL_8821C 0x7
+#define BIT_PS_TIMER_A_TSF_SEL_8821C(x)                                        \
+	(((x) & BIT_MASK_PS_TIMER_A_TSF_SEL_8821C)                             \
+	 << BIT_SHIFT_PS_TIMER_A_TSF_SEL_8821C)
+#define BITS_PS_TIMER_A_TSF_SEL_8821C                                          \
+	(BIT_MASK_PS_TIMER_A_TSF_SEL_8821C                                     \
+	 << BIT_SHIFT_PS_TIMER_A_TSF_SEL_8821C)
+#define BIT_CLEAR_PS_TIMER_A_TSF_SEL_8821C(x)                                  \
+	((x) & (~BITS_PS_TIMER_A_TSF_SEL_8821C))
+#define BIT_GET_PS_TIMER_A_TSF_SEL_8821C(x)                                    \
+	(((x) >> BIT_SHIFT_PS_TIMER_A_TSF_SEL_8821C) &                         \
+	 BIT_MASK_PS_TIMER_A_TSF_SEL_8821C)
+#define BIT_SET_PS_TIMER_A_TSF_SEL_8821C(x, v)                                 \
+	(BIT_CLEAR_PS_TIMER_A_TSF_SEL_8821C(x) |                               \
+	 BIT_PS_TIMER_A_TSF_SEL_8821C(v))
+
+/* 2 REG_CPUMGQ_TX_TIMER_EARLY_8821C */
+
+#define BIT_SHIFT_CPUMGQ_TX_TIMER_EARLY_8821C 0
+#define BIT_MASK_CPUMGQ_TX_TIMER_EARLY_8821C 0xff
+#define BIT_CPUMGQ_TX_TIMER_EARLY_8821C(x)                                     \
+	(((x) & BIT_MASK_CPUMGQ_TX_TIMER_EARLY_8821C)                          \
+	 << BIT_SHIFT_CPUMGQ_TX_TIMER_EARLY_8821C)
+#define BITS_CPUMGQ_TX_TIMER_EARLY_8821C                                       \
+	(BIT_MASK_CPUMGQ_TX_TIMER_EARLY_8821C                                  \
+	 << BIT_SHIFT_CPUMGQ_TX_TIMER_EARLY_8821C)
+#define BIT_CLEAR_CPUMGQ_TX_TIMER_EARLY_8821C(x)                               \
+	((x) & (~BITS_CPUMGQ_TX_TIMER_EARLY_8821C))
+#define BIT_GET_CPUMGQ_TX_TIMER_EARLY_8821C(x)                                 \
+	(((x) >> BIT_SHIFT_CPUMGQ_TX_TIMER_EARLY_8821C) &                      \
+	 BIT_MASK_CPUMGQ_TX_TIMER_EARLY_8821C)
+#define BIT_SET_CPUMGQ_TX_TIMER_EARLY_8821C(x, v)                              \
+	(BIT_CLEAR_CPUMGQ_TX_TIMER_EARLY_8821C(x) |                            \
+	 BIT_CPUMGQ_TX_TIMER_EARLY_8821C(v))
+
+/* 2 REG_PS_TIMER_A_EARLY_8821C */
+
+#define BIT_SHIFT_PS_TIMER_A_EARLY_8821C 0
+#define BIT_MASK_PS_TIMER_A_EARLY_8821C 0xff
+#define BIT_PS_TIMER_A_EARLY_8821C(x)                                          \
+	(((x) & BIT_MASK_PS_TIMER_A_EARLY_8821C)                               \
+	 << BIT_SHIFT_PS_TIMER_A_EARLY_8821C)
+#define BITS_PS_TIMER_A_EARLY_8821C                                            \
+	(BIT_MASK_PS_TIMER_A_EARLY_8821C << BIT_SHIFT_PS_TIMER_A_EARLY_8821C)
+#define BIT_CLEAR_PS_TIMER_A_EARLY_8821C(x)                                    \
+	((x) & (~BITS_PS_TIMER_A_EARLY_8821C))
+#define BIT_GET_PS_TIMER_A_EARLY_8821C(x)                                      \
+	(((x) >> BIT_SHIFT_PS_TIMER_A_EARLY_8821C) &                           \
+	 BIT_MASK_PS_TIMER_A_EARLY_8821C)
+#define BIT_SET_PS_TIMER_A_EARLY_8821C(x, v)                                   \
+	(BIT_CLEAR_PS_TIMER_A_EARLY_8821C(x) | BIT_PS_TIMER_A_EARLY_8821C(v))
+
+/* 2 REG_PS_TIMER_B_EARLY_8821C */
+
+#define BIT_SHIFT_PS_TIMER_B_EARLY_8821C 0
+#define BIT_MASK_PS_TIMER_B_EARLY_8821C 0xff
+#define BIT_PS_TIMER_B_EARLY_8821C(x)                                          \
+	(((x) & BIT_MASK_PS_TIMER_B_EARLY_8821C)                               \
+	 << BIT_SHIFT_PS_TIMER_B_EARLY_8821C)
+#define BITS_PS_TIMER_B_EARLY_8821C                                            \
+	(BIT_MASK_PS_TIMER_B_EARLY_8821C << BIT_SHIFT_PS_TIMER_B_EARLY_8821C)
+#define BIT_CLEAR_PS_TIMER_B_EARLY_8821C(x)                                    \
+	((x) & (~BITS_PS_TIMER_B_EARLY_8821C))
+#define BIT_GET_PS_TIMER_B_EARLY_8821C(x)                                      \
+	(((x) >> BIT_SHIFT_PS_TIMER_B_EARLY_8821C) &                           \
+	 BIT_MASK_PS_TIMER_B_EARLY_8821C)
+#define BIT_SET_PS_TIMER_B_EARLY_8821C(x, v)                                   \
+	(BIT_CLEAR_PS_TIMER_B_EARLY_8821C(x) | BIT_PS_TIMER_B_EARLY_8821C(v))
+
+/* 2 REG_PS_TIMER_C_EARLY_8821C */
+
+#define BIT_SHIFT_PS_TIMER_C_EARLY_8821C 0
+#define BIT_MASK_PS_TIMER_C_EARLY_8821C 0xff
+#define BIT_PS_TIMER_C_EARLY_8821C(x)                                          \
+	(((x) & BIT_MASK_PS_TIMER_C_EARLY_8821C)                               \
+	 << BIT_SHIFT_PS_TIMER_C_EARLY_8821C)
+#define BITS_PS_TIMER_C_EARLY_8821C                                            \
+	(BIT_MASK_PS_TIMER_C_EARLY_8821C << BIT_SHIFT_PS_TIMER_C_EARLY_8821C)
+#define BIT_CLEAR_PS_TIMER_C_EARLY_8821C(x)                                    \
+	((x) & (~BITS_PS_TIMER_C_EARLY_8821C))
+#define BIT_GET_PS_TIMER_C_EARLY_8821C(x)                                      \
+	(((x) >> BIT_SHIFT_PS_TIMER_C_EARLY_8821C) &                           \
+	 BIT_MASK_PS_TIMER_C_EARLY_8821C)
+#define BIT_SET_PS_TIMER_C_EARLY_8821C(x, v)                                   \
+	(BIT_CLEAR_PS_TIMER_C_EARLY_8821C(x) | BIT_PS_TIMER_C_EARLY_8821C(v))
+
+/* 2 REG_CPUMGQ_PARAMETER_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+#define BIT_MAC_STOP_CPUMGQ_8821C BIT(16)
+
+#define BIT_SHIFT_CW_8821C 8
+#define BIT_MASK_CW_8821C 0xff
+#define BIT_CW_8821C(x) (((x) & BIT_MASK_CW_8821C) << BIT_SHIFT_CW_8821C)
+#define BITS_CW_8821C (BIT_MASK_CW_8821C << BIT_SHIFT_CW_8821C)
+#define BIT_CLEAR_CW_8821C(x) ((x) & (~BITS_CW_8821C))
+#define BIT_GET_CW_8821C(x) (((x) >> BIT_SHIFT_CW_8821C) & BIT_MASK_CW_8821C)
+#define BIT_SET_CW_8821C(x, v) (BIT_CLEAR_CW_8821C(x) | BIT_CW_8821C(v))
+
+#define BIT_SHIFT_AIFS_8821C 0
+#define BIT_MASK_AIFS_8821C 0xff
+#define BIT_AIFS_8821C(x) (((x) & BIT_MASK_AIFS_8821C) << BIT_SHIFT_AIFS_8821C)
+#define BITS_AIFS_8821C (BIT_MASK_AIFS_8821C << BIT_SHIFT_AIFS_8821C)
+#define BIT_CLEAR_AIFS_8821C(x) ((x) & (~BITS_AIFS_8821C))
+#define BIT_GET_AIFS_8821C(x)                                                  \
+	(((x) >> BIT_SHIFT_AIFS_8821C) & BIT_MASK_AIFS_8821C)
+#define BIT_SET_AIFS_8821C(x, v) (BIT_CLEAR_AIFS_8821C(x) | BIT_AIFS_8821C(v))
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_RSVD_8821C */
+
+/* 2 REG_RSVD_8821C */
+
+/* 2 REG_RSVD_8821C */
+
+/* 2 REG_RSVD_8821C */
+
+/* 2 REG_RSVD_8821C */
+
+/* 2 REG_RSVD_8821C */
+
+/* 2 REG_RSVD_8821C */
+
+/* 2 REG_RSVD_8821C */
+
+/* 2 REG_RSVD_8821C */
+
+/* 2 REG_RSVD_8821C */
+
+/* 2 REG_RSVD_8821C */
+
+/* 2 REG_RSVD_8821C */
+
+/* 2 REG_RSVD_8821C */
+
+/* 2 REG_RSVD_8821C */
+
+/* 2 REG_RSVD_8821C */
+
+/* 2 REG_RSVD_8821C */
+
+/* 2 REG_RSVD_8821C */
+
+/* 2 REG_RSVD_8821C */
+
+/* 2 REG_RSVD_8821C */
+
+/* 2 REG_RSVD_8821C */
+
+/* 2 REG_RSVD_8821C */
+
+/* 2 REG_RSVD_8821C */
+
+/* 2 REG_RSVD_8821C */
+
+/* 2 REG_RSVD_8821C */
+
+/* 2 REG_RSVD_8821C */
+
+/* 2 REG_RSVD_8821C */
+
+/* 2 REG_RSVD_8821C */
+
+/* 2 REG_RSVD_8821C */
+
+/* 2 REG_RSVD_8821C */
+
+/* 2 REG_RSVD_8821C */
+
+/* 2 REG_RSVD_8821C */
+
+/* 2 REG_RSVD_8821C */
+
+/* 2 REG_RSVD_8821C */
+
+/* 2 REG_RSVD_8821C */
+
+/* 2 REG_RSVD_8821C */
+
+/* 2 REG_RSVD_8821C */
+
+/* 2 REG_RSVD_8821C */
+
+/* 2 REG_RSVD_8821C */
+
+/* 2 REG_RSVD_8821C */
+
+/* 2 REG_RSVD_8821C */
+
+/* 2 REG_RSVD_8821C */
+
+/* 2 REG_RSVD_8821C */
+
+/* 2 REG_RSVD_8821C */
+
+/* 2 REG_RSVD_8821C */
+
+/* 2 REG_RSVD_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_WMAC_CR_8821C (WMAC CR AND APSD CONTROL REGISTER) */
+#define BIT_IC_MACPHY_M_8821C BIT(0)
+
+/* 2 REG_WMAC_FWPKT_CR_8821C */
+#define BIT_FWEN_8821C BIT(7)
+#define BIT_PHYSTS_PKT_CTRL_8821C BIT(6)
+#define BIT_FWFULL_TO_RXFF_EN_8821C BIT(5)
+#define BIT_APPHDR_MIDSRCH_FAIL_8821C BIT(4)
+#define BIT_FWPARSING_EN_8821C BIT(3)
+
+#define BIT_SHIFT_APPEND_MHDR_LEN_8821C 0
+#define BIT_MASK_APPEND_MHDR_LEN_8821C 0x7
+#define BIT_APPEND_MHDR_LEN_8821C(x)                                           \
+	(((x) & BIT_MASK_APPEND_MHDR_LEN_8821C)                                \
+	 << BIT_SHIFT_APPEND_MHDR_LEN_8821C)
+#define BITS_APPEND_MHDR_LEN_8821C                                             \
+	(BIT_MASK_APPEND_MHDR_LEN_8821C << BIT_SHIFT_APPEND_MHDR_LEN_8821C)
+#define BIT_CLEAR_APPEND_MHDR_LEN_8821C(x) ((x) & (~BITS_APPEND_MHDR_LEN_8821C))
+#define BIT_GET_APPEND_MHDR_LEN_8821C(x)                                       \
+	(((x) >> BIT_SHIFT_APPEND_MHDR_LEN_8821C) &                            \
+	 BIT_MASK_APPEND_MHDR_LEN_8821C)
+#define BIT_SET_APPEND_MHDR_LEN_8821C(x, v)                                    \
+	(BIT_CLEAR_APPEND_MHDR_LEN_8821C(x) | BIT_APPEND_MHDR_LEN_8821C(v))
+
+/* 2 REG_FW_STS_FILTER_8821C */
+#define BIT_DATA_FW_STS_FILTER_8821C BIT(2)
+#define BIT_CTRL_FW_STS_FILTER_8821C BIT(1)
+#define BIT_MGNT_FW_STS_FILTER_8821C BIT(0)
+
+/* 2 REG_RSVD_8821C */
+
+/* 2 REG_TCR_8821C (TRANSMISSION CONFIGURATION REGISTER) */
+#define BIT_WMAC_EN_RTS_ADDR_8821C BIT(31)
+#define BIT_WMAC_DISABLE_CCK_8821C BIT(30)
+#define BIT_WMAC_RAW_LEN_8821C BIT(29)
+#define BIT_WMAC_NOTX_IN_RXNDP_8821C BIT(28)
+#define BIT_WMAC_EN_EOF_8821C BIT(27)
+#define BIT_WMAC_BF_SEL_8821C BIT(26)
+#define BIT_WMAC_ANTMODE_SEL_8821C BIT(25)
+#define BIT_WMAC_TCRPWRMGT_HWCTL_8821C BIT(24)
+#define BIT_WMAC_SMOOTH_VAL_8821C BIT(23)
+#define BIT_FETCH_MPDU_AFTER_WSEC_RDY_8821C BIT(20)
+#define BIT_WMAC_TCR_EN_20MST_8821C BIT(19)
+#define BIT_WMAC_DIS_SIGTA_8821C BIT(18)
+#define BIT_WMAC_DIS_A2B0_8821C BIT(17)
+#define BIT_WMAC_MSK_SIGBCRC_8821C BIT(16)
+#define BIT_WMAC_TCR_ERRSTEN_3_8821C BIT(15)
+#define BIT_WMAC_TCR_ERRSTEN_2_8821C BIT(14)
+#define BIT_WMAC_TCR_ERRSTEN_1_8821C BIT(13)
+#define BIT_WMAC_TCR_ERRSTEN_0_8821C BIT(12)
+#define BIT_WMAC_TCR_TXSK_PERPKT_8821C BIT(11)
+#define BIT_ICV_8821C BIT(10)
+#define BIT_CFEND_FORMAT_8821C BIT(9)
+#define BIT_CRC_8821C BIT(8)
+#define BIT_PWRBIT_OW_EN_8821C BIT(7)
+#define BIT_PWR_ST_8821C BIT(6)
+#define BIT_WMAC_TCR_UPD_TIMIE_8821C BIT(5)
+#define BIT_WMAC_TCR_UPD_HGQMD_8821C BIT(4)
+#define BIT_VHTSIGA1_TXPS_8821C BIT(3)
+#define BIT_PAD_SEL_8821C BIT(2)
+#define BIT_DIS_GCLK_8821C BIT(1)
+
+/* 2 REG_RCR_8821C (RECEIVE CONFIGURATION REGISTER) */
+#define BIT_APP_FCS_8821C BIT(31)
+#define BIT_APP_MIC_8821C BIT(30)
+#define BIT_APP_ICV_8821C BIT(29)
+#define BIT_APP_PHYSTS_8821C BIT(28)
+#define BIT_APP_BASSN_8821C BIT(27)
+#define BIT_VHT_DACK_8821C BIT(26)
+#define BIT_TCPOFLD_EN_8821C BIT(25)
+#define BIT_ENMBID_8821C BIT(24)
+#define BIT_LSIGEN_8821C BIT(23)
+#define BIT_MFBEN_8821C BIT(22)
+#define BIT_DISCHKPPDLLEN_8821C BIT(21)
+#define BIT_PKTCTL_DLEN_8821C BIT(20)
+#define BIT_TIM_PARSER_EN_8821C BIT(18)
+#define BIT_BC_MD_EN_8821C BIT(17)
+#define BIT_UC_MD_EN_8821C BIT(16)
+#define BIT_RXSK_PERPKT_8821C BIT(15)
+#define BIT_HTC_LOC_CTRL_8821C BIT(14)
+#define BIT_RPFM_CAM_ENABLE_8821C BIT(12)
+#define BIT_TA_BCN_8821C BIT(11)
+#define BIT_DISDECMYPKT_8821C BIT(10)
+#define BIT_AICV_8821C BIT(9)
+#define BIT_ACRC32_8821C BIT(8)
+#define BIT_CBSSID_BCN_8821C BIT(7)
+#define BIT_CBSSID_DATA_8821C BIT(6)
+#define BIT_APWRMGT_8821C BIT(5)
+#define BIT_ADD3_8821C BIT(4)
+#define BIT_AB_8821C BIT(3)
+#define BIT_AM_8821C BIT(2)
+#define BIT_APM_8821C BIT(1)
+#define BIT_AAP_8821C BIT(0)
+
+/* 2 REG_RX_PKT_LIMIT_8821C (RX PACKET LENGTH LIMIT REGISTER) */
+
+#define BIT_SHIFT_RXPKTLMT_8821C 0
+#define BIT_MASK_RXPKTLMT_8821C 0x3f
+#define BIT_RXPKTLMT_8821C(x)                                                  \
+	(((x) & BIT_MASK_RXPKTLMT_8821C) << BIT_SHIFT_RXPKTLMT_8821C)
+#define BITS_RXPKTLMT_8821C                                                    \
+	(BIT_MASK_RXPKTLMT_8821C << BIT_SHIFT_RXPKTLMT_8821C)
+#define BIT_CLEAR_RXPKTLMT_8821C(x) ((x) & (~BITS_RXPKTLMT_8821C))
+#define BIT_GET_RXPKTLMT_8821C(x)                                              \
+	(((x) >> BIT_SHIFT_RXPKTLMT_8821C) & BIT_MASK_RXPKTLMT_8821C)
+#define BIT_SET_RXPKTLMT_8821C(x, v)                                           \
+	(BIT_CLEAR_RXPKTLMT_8821C(x) | BIT_RXPKTLMT_8821C(v))
+
+/* 2 REG_RX_DLK_TIME_8821C (RX DEADLOCK TIME REGISTER) */
+
+#define BIT_SHIFT_RX_DLK_TIME_8821C 0
+#define BIT_MASK_RX_DLK_TIME_8821C 0xff
+#define BIT_RX_DLK_TIME_8821C(x)                                               \
+	(((x) & BIT_MASK_RX_DLK_TIME_8821C) << BIT_SHIFT_RX_DLK_TIME_8821C)
+#define BITS_RX_DLK_TIME_8821C                                                 \
+	(BIT_MASK_RX_DLK_TIME_8821C << BIT_SHIFT_RX_DLK_TIME_8821C)
+#define BIT_CLEAR_RX_DLK_TIME_8821C(x) ((x) & (~BITS_RX_DLK_TIME_8821C))
+#define BIT_GET_RX_DLK_TIME_8821C(x)                                           \
+	(((x) >> BIT_SHIFT_RX_DLK_TIME_8821C) & BIT_MASK_RX_DLK_TIME_8821C)
+#define BIT_SET_RX_DLK_TIME_8821C(x, v)                                        \
+	(BIT_CLEAR_RX_DLK_TIME_8821C(x) | BIT_RX_DLK_TIME_8821C(v))
+
+/* 2 REG_RSVD_8821C */
+
+/* 2 REG_RX_DRVINFO_SZ_8821C (RX DRIVER INFO SIZE REGISTER) */
+#define BIT_PHYSTS_PER_PKT_MODE_8821C BIT(7)
+
+#define BIT_SHIFT_DRVINFO_SZ_V1_8821C 0
+#define BIT_MASK_DRVINFO_SZ_V1_8821C 0xf
+#define BIT_DRVINFO_SZ_V1_8821C(x)                                             \
+	(((x) & BIT_MASK_DRVINFO_SZ_V1_8821C) << BIT_SHIFT_DRVINFO_SZ_V1_8821C)
+#define BITS_DRVINFO_SZ_V1_8821C                                               \
+	(BIT_MASK_DRVINFO_SZ_V1_8821C << BIT_SHIFT_DRVINFO_SZ_V1_8821C)
+#define BIT_CLEAR_DRVINFO_SZ_V1_8821C(x) ((x) & (~BITS_DRVINFO_SZ_V1_8821C))
+#define BIT_GET_DRVINFO_SZ_V1_8821C(x)                                         \
+	(((x) >> BIT_SHIFT_DRVINFO_SZ_V1_8821C) & BIT_MASK_DRVINFO_SZ_V1_8821C)
+#define BIT_SET_DRVINFO_SZ_V1_8821C(x, v)                                      \
+	(BIT_CLEAR_DRVINFO_SZ_V1_8821C(x) | BIT_DRVINFO_SZ_V1_8821C(v))
+
+/* 2 REG_MACID_8821C	(MAC ID REGISTER) */
+
+#define BIT_SHIFT_MACID_V1_8821C 0
+#define BIT_MASK_MACID_V1_8821C 0xffffffffL
+#define BIT_MACID_V1_8821C(x)                                                  \
+	(((x) & BIT_MASK_MACID_V1_8821C) << BIT_SHIFT_MACID_V1_8821C)
+#define BITS_MACID_V1_8821C                                                    \
+	(BIT_MASK_MACID_V1_8821C << BIT_SHIFT_MACID_V1_8821C)
+#define BIT_CLEAR_MACID_V1_8821C(x) ((x) & (~BITS_MACID_V1_8821C))
+#define BIT_GET_MACID_V1_8821C(x)                                              \
+	(((x) >> BIT_SHIFT_MACID_V1_8821C) & BIT_MASK_MACID_V1_8821C)
+#define BIT_SET_MACID_V1_8821C(x, v)                                           \
+	(BIT_CLEAR_MACID_V1_8821C(x) | BIT_MACID_V1_8821C(v))
+
+/* 2 REG_MACID_H_8821C	(MAC ID REGISTER) */
+
+#define BIT_SHIFT_MACID_H_V1_8821C 0
+#define BIT_MASK_MACID_H_V1_8821C 0xffff
+#define BIT_MACID_H_V1_8821C(x)                                                \
+	(((x) & BIT_MASK_MACID_H_V1_8821C) << BIT_SHIFT_MACID_H_V1_8821C)
+#define BITS_MACID_H_V1_8821C                                                  \
+	(BIT_MASK_MACID_H_V1_8821C << BIT_SHIFT_MACID_H_V1_8821C)
+#define BIT_CLEAR_MACID_H_V1_8821C(x) ((x) & (~BITS_MACID_H_V1_8821C))
+#define BIT_GET_MACID_H_V1_8821C(x)                                            \
+	(((x) >> BIT_SHIFT_MACID_H_V1_8821C) & BIT_MASK_MACID_H_V1_8821C)
+#define BIT_SET_MACID_H_V1_8821C(x, v)                                         \
+	(BIT_CLEAR_MACID_H_V1_8821C(x) | BIT_MACID_H_V1_8821C(v))
+
+/* 2 REG_BSSID_8821C (BSSID REGISTER) */
+
+#define BIT_SHIFT_BSSID_V1_8821C 0
+#define BIT_MASK_BSSID_V1_8821C 0xffffffffL
+#define BIT_BSSID_V1_8821C(x)                                                  \
+	(((x) & BIT_MASK_BSSID_V1_8821C) << BIT_SHIFT_BSSID_V1_8821C)
+#define BITS_BSSID_V1_8821C                                                    \
+	(BIT_MASK_BSSID_V1_8821C << BIT_SHIFT_BSSID_V1_8821C)
+#define BIT_CLEAR_BSSID_V1_8821C(x) ((x) & (~BITS_BSSID_V1_8821C))
+#define BIT_GET_BSSID_V1_8821C(x)                                              \
+	(((x) >> BIT_SHIFT_BSSID_V1_8821C) & BIT_MASK_BSSID_V1_8821C)
+#define BIT_SET_BSSID_V1_8821C(x, v)                                           \
+	(BIT_CLEAR_BSSID_V1_8821C(x) | BIT_BSSID_V1_8821C(v))
+
+/* 2 REG_BSSID_H_8821C	(BSSID REGISTER) */
+
+/* 2 REG_NOT_VALID_8821C */
+
+#define BIT_SHIFT_BSSID_H_V1_8821C 0
+#define BIT_MASK_BSSID_H_V1_8821C 0xffff
+#define BIT_BSSID_H_V1_8821C(x)                                                \
+	(((x) & BIT_MASK_BSSID_H_V1_8821C) << BIT_SHIFT_BSSID_H_V1_8821C)
+#define BITS_BSSID_H_V1_8821C                                                  \
+	(BIT_MASK_BSSID_H_V1_8821C << BIT_SHIFT_BSSID_H_V1_8821C)
+#define BIT_CLEAR_BSSID_H_V1_8821C(x) ((x) & (~BITS_BSSID_H_V1_8821C))
+#define BIT_GET_BSSID_H_V1_8821C(x)                                            \
+	(((x) >> BIT_SHIFT_BSSID_H_V1_8821C) & BIT_MASK_BSSID_H_V1_8821C)
+#define BIT_SET_BSSID_H_V1_8821C(x, v)                                         \
+	(BIT_CLEAR_BSSID_H_V1_8821C(x) | BIT_BSSID_H_V1_8821C(v))
+
+/* 2 REG_MAR_8821C (MULTICAST ADDRESS REGISTER) */
+
+#define BIT_SHIFT_MAR_V1_8821C 0
+#define BIT_MASK_MAR_V1_8821C 0xffffffffL
+#define BIT_MAR_V1_8821C(x)                                                    \
+	(((x) & BIT_MASK_MAR_V1_8821C) << BIT_SHIFT_MAR_V1_8821C)
+#define BITS_MAR_V1_8821C (BIT_MASK_MAR_V1_8821C << BIT_SHIFT_MAR_V1_8821C)
+#define BIT_CLEAR_MAR_V1_8821C(x) ((x) & (~BITS_MAR_V1_8821C))
+#define BIT_GET_MAR_V1_8821C(x)                                                \
+	(((x) >> BIT_SHIFT_MAR_V1_8821C) & BIT_MASK_MAR_V1_8821C)
+#define BIT_SET_MAR_V1_8821C(x, v)                                             \
+	(BIT_CLEAR_MAR_V1_8821C(x) | BIT_MAR_V1_8821C(v))
+
+/* 2 REG_MAR_H_8821C (MULTICAST ADDRESS REGISTER) */
+
+#define BIT_SHIFT_MAR_H_V1_8821C 0
+#define BIT_MASK_MAR_H_V1_8821C 0xffffffffL
+#define BIT_MAR_H_V1_8821C(x)                                                  \
+	(((x) & BIT_MASK_MAR_H_V1_8821C) << BIT_SHIFT_MAR_H_V1_8821C)
+#define BITS_MAR_H_V1_8821C                                                    \
+	(BIT_MASK_MAR_H_V1_8821C << BIT_SHIFT_MAR_H_V1_8821C)
+#define BIT_CLEAR_MAR_H_V1_8821C(x) ((x) & (~BITS_MAR_H_V1_8821C))
+#define BIT_GET_MAR_H_V1_8821C(x)                                              \
+	(((x) >> BIT_SHIFT_MAR_H_V1_8821C) & BIT_MASK_MAR_H_V1_8821C)
+#define BIT_SET_MAR_H_V1_8821C(x, v)                                           \
+	(BIT_CLEAR_MAR_H_V1_8821C(x) | BIT_MAR_H_V1_8821C(v))
+
+/* 2 REG_MBIDCAMCFG_1_8821C (MBSSID CAM CONFIGURATION REGISTER) */
+
+#define BIT_SHIFT_MBIDCAM_RWDATA_L_8821C 0
+#define BIT_MASK_MBIDCAM_RWDATA_L_8821C 0xffffffffL
+#define BIT_MBIDCAM_RWDATA_L_8821C(x)                                          \
+	(((x) & BIT_MASK_MBIDCAM_RWDATA_L_8821C)                               \
+	 << BIT_SHIFT_MBIDCAM_RWDATA_L_8821C)
+#define BITS_MBIDCAM_RWDATA_L_8821C                                            \
+	(BIT_MASK_MBIDCAM_RWDATA_L_8821C << BIT_SHIFT_MBIDCAM_RWDATA_L_8821C)
+#define BIT_CLEAR_MBIDCAM_RWDATA_L_8821C(x)                                    \
+	((x) & (~BITS_MBIDCAM_RWDATA_L_8821C))
+#define BIT_GET_MBIDCAM_RWDATA_L_8821C(x)                                      \
+	(((x) >> BIT_SHIFT_MBIDCAM_RWDATA_L_8821C) &                           \
+	 BIT_MASK_MBIDCAM_RWDATA_L_8821C)
+#define BIT_SET_MBIDCAM_RWDATA_L_8821C(x, v)                                   \
+	(BIT_CLEAR_MBIDCAM_RWDATA_L_8821C(x) | BIT_MBIDCAM_RWDATA_L_8821C(v))
+
+/* 2 REG_MBIDCAMCFG_2_8821C (MBSSID CAM CONFIGURATION REGISTER) */
+#define BIT_MBIDCAM_POLL_8821C BIT(31)
+#define BIT_MBIDCAM_WT_EN_8821C BIT(30)
+
+#define BIT_SHIFT_MBIDCAM_ADDR_8821C 24
+#define BIT_MASK_MBIDCAM_ADDR_8821C 0x1f
+#define BIT_MBIDCAM_ADDR_8821C(x)                                              \
+	(((x) & BIT_MASK_MBIDCAM_ADDR_8821C) << BIT_SHIFT_MBIDCAM_ADDR_8821C)
+#define BITS_MBIDCAM_ADDR_8821C                                                \
+	(BIT_MASK_MBIDCAM_ADDR_8821C << BIT_SHIFT_MBIDCAM_ADDR_8821C)
+#define BIT_CLEAR_MBIDCAM_ADDR_8821C(x) ((x) & (~BITS_MBIDCAM_ADDR_8821C))
+#define BIT_GET_MBIDCAM_ADDR_8821C(x)                                          \
+	(((x) >> BIT_SHIFT_MBIDCAM_ADDR_8821C) & BIT_MASK_MBIDCAM_ADDR_8821C)
+#define BIT_SET_MBIDCAM_ADDR_8821C(x, v)                                       \
+	(BIT_CLEAR_MBIDCAM_ADDR_8821C(x) | BIT_MBIDCAM_ADDR_8821C(v))
+
+#define BIT_MBIDCAM_VALID_8821C BIT(23)
+#define BIT_LSIC_TXOP_EN_8821C BIT(17)
+#define BIT_CTS_EN_8821C BIT(16)
+
+#define BIT_SHIFT_MBIDCAM_RWDATA_H_8821C 0
+#define BIT_MASK_MBIDCAM_RWDATA_H_8821C 0xffff
+#define BIT_MBIDCAM_RWDATA_H_8821C(x)                                          \
+	(((x) & BIT_MASK_MBIDCAM_RWDATA_H_8821C)                               \
+	 << BIT_SHIFT_MBIDCAM_RWDATA_H_8821C)
+#define BITS_MBIDCAM_RWDATA_H_8821C                                            \
+	(BIT_MASK_MBIDCAM_RWDATA_H_8821C << BIT_SHIFT_MBIDCAM_RWDATA_H_8821C)
+#define BIT_CLEAR_MBIDCAM_RWDATA_H_8821C(x)                                    \
+	((x) & (~BITS_MBIDCAM_RWDATA_H_8821C))
+#define BIT_GET_MBIDCAM_RWDATA_H_8821C(x)                                      \
+	(((x) >> BIT_SHIFT_MBIDCAM_RWDATA_H_8821C) &                           \
+	 BIT_MASK_MBIDCAM_RWDATA_H_8821C)
+#define BIT_SET_MBIDCAM_RWDATA_H_8821C(x, v)                                   \
+	(BIT_CLEAR_MBIDCAM_RWDATA_H_8821C(x) | BIT_MBIDCAM_RWDATA_H_8821C(v))
+
+/* 2 REG_WMAC_TCR_TSFT_OFS_8821C */
+
+#define BIT_SHIFT_WMAC_TCR_TSFT_OFS_8821C 0
+#define BIT_MASK_WMAC_TCR_TSFT_OFS_8821C 0xffff
+#define BIT_WMAC_TCR_TSFT_OFS_8821C(x)                                         \
+	(((x) & BIT_MASK_WMAC_TCR_TSFT_OFS_8821C)                              \
+	 << BIT_SHIFT_WMAC_TCR_TSFT_OFS_8821C)
+#define BITS_WMAC_TCR_TSFT_OFS_8821C                                           \
+	(BIT_MASK_WMAC_TCR_TSFT_OFS_8821C << BIT_SHIFT_WMAC_TCR_TSFT_OFS_8821C)
+#define BIT_CLEAR_WMAC_TCR_TSFT_OFS_8821C(x)                                   \
+	((x) & (~BITS_WMAC_TCR_TSFT_OFS_8821C))
+#define BIT_GET_WMAC_TCR_TSFT_OFS_8821C(x)                                     \
+	(((x) >> BIT_SHIFT_WMAC_TCR_TSFT_OFS_8821C) &                          \
+	 BIT_MASK_WMAC_TCR_TSFT_OFS_8821C)
+#define BIT_SET_WMAC_TCR_TSFT_OFS_8821C(x, v)                                  \
+	(BIT_CLEAR_WMAC_TCR_TSFT_OFS_8821C(x) | BIT_WMAC_TCR_TSFT_OFS_8821C(v))
+
+/* 2 REG_UDF_THSD_8821C */
+
+#define BIT_SHIFT_UDF_THSD_8821C 0
+#define BIT_MASK_UDF_THSD_8821C 0xff
+#define BIT_UDF_THSD_8821C(x)                                                  \
+	(((x) & BIT_MASK_UDF_THSD_8821C) << BIT_SHIFT_UDF_THSD_8821C)
+#define BITS_UDF_THSD_8821C                                                    \
+	(BIT_MASK_UDF_THSD_8821C << BIT_SHIFT_UDF_THSD_8821C)
+#define BIT_CLEAR_UDF_THSD_8821C(x) ((x) & (~BITS_UDF_THSD_8821C))
+#define BIT_GET_UDF_THSD_8821C(x)                                              \
+	(((x) >> BIT_SHIFT_UDF_THSD_8821C) & BIT_MASK_UDF_THSD_8821C)
+#define BIT_SET_UDF_THSD_8821C(x, v)                                           \
+	(BIT_CLEAR_UDF_THSD_8821C(x) | BIT_UDF_THSD_8821C(v))
+
+/* 2 REG_ZLD_NUM_8821C */
+
+#define BIT_SHIFT_ZLD_NUM_8821C 0
+#define BIT_MASK_ZLD_NUM_8821C 0xff
+#define BIT_ZLD_NUM_8821C(x)                                                   \
+	(((x) & BIT_MASK_ZLD_NUM_8821C) << BIT_SHIFT_ZLD_NUM_8821C)
+#define BITS_ZLD_NUM_8821C (BIT_MASK_ZLD_NUM_8821C << BIT_SHIFT_ZLD_NUM_8821C)
+#define BIT_CLEAR_ZLD_NUM_8821C(x) ((x) & (~BITS_ZLD_NUM_8821C))
+#define BIT_GET_ZLD_NUM_8821C(x)                                               \
+	(((x) >> BIT_SHIFT_ZLD_NUM_8821C) & BIT_MASK_ZLD_NUM_8821C)
+#define BIT_SET_ZLD_NUM_8821C(x, v)                                            \
+	(BIT_CLEAR_ZLD_NUM_8821C(x) | BIT_ZLD_NUM_8821C(v))
+
+/* 2 REG_STMP_THSD_8821C */
+
+#define BIT_SHIFT_STMP_THSD_8821C 0
+#define BIT_MASK_STMP_THSD_8821C 0xff
+#define BIT_STMP_THSD_8821C(x)                                                 \
+	(((x) & BIT_MASK_STMP_THSD_8821C) << BIT_SHIFT_STMP_THSD_8821C)
+#define BITS_STMP_THSD_8821C                                                   \
+	(BIT_MASK_STMP_THSD_8821C << BIT_SHIFT_STMP_THSD_8821C)
+#define BIT_CLEAR_STMP_THSD_8821C(x) ((x) & (~BITS_STMP_THSD_8821C))
+#define BIT_GET_STMP_THSD_8821C(x)                                             \
+	(((x) >> BIT_SHIFT_STMP_THSD_8821C) & BIT_MASK_STMP_THSD_8821C)
+#define BIT_SET_STMP_THSD_8821C(x, v)                                          \
+	(BIT_CLEAR_STMP_THSD_8821C(x) | BIT_STMP_THSD_8821C(v))
+
+/* 2 REG_WMAC_TXTIMEOUT_8821C */
+
+#define BIT_SHIFT_WMAC_TXTIMEOUT_8821C 0
+#define BIT_MASK_WMAC_TXTIMEOUT_8821C 0xff
+#define BIT_WMAC_TXTIMEOUT_8821C(x)                                            \
+	(((x) & BIT_MASK_WMAC_TXTIMEOUT_8821C)                                 \
+	 << BIT_SHIFT_WMAC_TXTIMEOUT_8821C)
+#define BITS_WMAC_TXTIMEOUT_8821C                                              \
+	(BIT_MASK_WMAC_TXTIMEOUT_8821C << BIT_SHIFT_WMAC_TXTIMEOUT_8821C)
+#define BIT_CLEAR_WMAC_TXTIMEOUT_8821C(x) ((x) & (~BITS_WMAC_TXTIMEOUT_8821C))
+#define BIT_GET_WMAC_TXTIMEOUT_8821C(x)                                        \
+	(((x) >> BIT_SHIFT_WMAC_TXTIMEOUT_8821C) &                             \
+	 BIT_MASK_WMAC_TXTIMEOUT_8821C)
+#define BIT_SET_WMAC_TXTIMEOUT_8821C(x, v)                                     \
+	(BIT_CLEAR_WMAC_TXTIMEOUT_8821C(x) | BIT_WMAC_TXTIMEOUT_8821C(v))
+
+/* 2 REG_MCU_TEST_2_V1_8821C */
+
+#define BIT_SHIFT_MCU_RSVD_2_V1_8821C 0
+#define BIT_MASK_MCU_RSVD_2_V1_8821C 0xffff
+#define BIT_MCU_RSVD_2_V1_8821C(x)                                             \
+	(((x) & BIT_MASK_MCU_RSVD_2_V1_8821C) << BIT_SHIFT_MCU_RSVD_2_V1_8821C)
+#define BITS_MCU_RSVD_2_V1_8821C                                               \
+	(BIT_MASK_MCU_RSVD_2_V1_8821C << BIT_SHIFT_MCU_RSVD_2_V1_8821C)
+#define BIT_CLEAR_MCU_RSVD_2_V1_8821C(x) ((x) & (~BITS_MCU_RSVD_2_V1_8821C))
+#define BIT_GET_MCU_RSVD_2_V1_8821C(x)                                         \
+	(((x) >> BIT_SHIFT_MCU_RSVD_2_V1_8821C) & BIT_MASK_MCU_RSVD_2_V1_8821C)
+#define BIT_SET_MCU_RSVD_2_V1_8821C(x, v)                                      \
+	(BIT_CLEAR_MCU_RSVD_2_V1_8821C(x) | BIT_MCU_RSVD_2_V1_8821C(v))
+
+/* 2 REG_USTIME_EDCA_8821C (US TIME TUNING FOR EDCA REGISTER) */
+
+#define BIT_SHIFT_USTIME_EDCA_8821C 0
+#define BIT_MASK_USTIME_EDCA_8821C 0xff
+#define BIT_USTIME_EDCA_8821C(x)                                               \
+	(((x) & BIT_MASK_USTIME_EDCA_8821C) << BIT_SHIFT_USTIME_EDCA_8821C)
+#define BITS_USTIME_EDCA_8821C                                                 \
+	(BIT_MASK_USTIME_EDCA_8821C << BIT_SHIFT_USTIME_EDCA_8821C)
+#define BIT_CLEAR_USTIME_EDCA_8821C(x) ((x) & (~BITS_USTIME_EDCA_8821C))
+#define BIT_GET_USTIME_EDCA_8821C(x)                                           \
+	(((x) >> BIT_SHIFT_USTIME_EDCA_8821C) & BIT_MASK_USTIME_EDCA_8821C)
+#define BIT_SET_USTIME_EDCA_8821C(x, v)                                        \
+	(BIT_CLEAR_USTIME_EDCA_8821C(x) | BIT_USTIME_EDCA_8821C(v))
+
+/* 2 REG_ACKTO_CCK_8821C (ACK TIMEOUT REGISTER FOR CCK RATE) */
+
+#define BIT_SHIFT_ACKTO_CCK_8821C 0
+#define BIT_MASK_ACKTO_CCK_8821C 0xff
+#define BIT_ACKTO_CCK_8821C(x)                                                 \
+	(((x) & BIT_MASK_ACKTO_CCK_8821C) << BIT_SHIFT_ACKTO_CCK_8821C)
+#define BITS_ACKTO_CCK_8821C                                                   \
+	(BIT_MASK_ACKTO_CCK_8821C << BIT_SHIFT_ACKTO_CCK_8821C)
+#define BIT_CLEAR_ACKTO_CCK_8821C(x) ((x) & (~BITS_ACKTO_CCK_8821C))
+#define BIT_GET_ACKTO_CCK_8821C(x)                                             \
+	(((x) >> BIT_SHIFT_ACKTO_CCK_8821C) & BIT_MASK_ACKTO_CCK_8821C)
+#define BIT_SET_ACKTO_CCK_8821C(x, v)                                          \
+	(BIT_CLEAR_ACKTO_CCK_8821C(x) | BIT_ACKTO_CCK_8821C(v))
+
+/* 2 REG_MAC_SPEC_SIFS_8821C (SPECIFICATION SIFS REGISTER) */
+
+#define BIT_SHIFT_SPEC_SIFS_OFDM_8821C 8
+#define BIT_MASK_SPEC_SIFS_OFDM_8821C 0xff
+#define BIT_SPEC_SIFS_OFDM_8821C(x)                                            \
+	(((x) & BIT_MASK_SPEC_SIFS_OFDM_8821C)                                 \
+	 << BIT_SHIFT_SPEC_SIFS_OFDM_8821C)
+#define BITS_SPEC_SIFS_OFDM_8821C                                              \
+	(BIT_MASK_SPEC_SIFS_OFDM_8821C << BIT_SHIFT_SPEC_SIFS_OFDM_8821C)
+#define BIT_CLEAR_SPEC_SIFS_OFDM_8821C(x) ((x) & (~BITS_SPEC_SIFS_OFDM_8821C))
+#define BIT_GET_SPEC_SIFS_OFDM_8821C(x)                                        \
+	(((x) >> BIT_SHIFT_SPEC_SIFS_OFDM_8821C) &                             \
+	 BIT_MASK_SPEC_SIFS_OFDM_8821C)
+#define BIT_SET_SPEC_SIFS_OFDM_8821C(x, v)                                     \
+	(BIT_CLEAR_SPEC_SIFS_OFDM_8821C(x) | BIT_SPEC_SIFS_OFDM_8821C(v))
+
+#define BIT_SHIFT_SPEC_SIFS_CCK_8821C 0
+#define BIT_MASK_SPEC_SIFS_CCK_8821C 0xff
+#define BIT_SPEC_SIFS_CCK_8821C(x)                                             \
+	(((x) & BIT_MASK_SPEC_SIFS_CCK_8821C) << BIT_SHIFT_SPEC_SIFS_CCK_8821C)
+#define BITS_SPEC_SIFS_CCK_8821C                                               \
+	(BIT_MASK_SPEC_SIFS_CCK_8821C << BIT_SHIFT_SPEC_SIFS_CCK_8821C)
+#define BIT_CLEAR_SPEC_SIFS_CCK_8821C(x) ((x) & (~BITS_SPEC_SIFS_CCK_8821C))
+#define BIT_GET_SPEC_SIFS_CCK_8821C(x)                                         \
+	(((x) >> BIT_SHIFT_SPEC_SIFS_CCK_8821C) & BIT_MASK_SPEC_SIFS_CCK_8821C)
+#define BIT_SET_SPEC_SIFS_CCK_8821C(x, v)                                      \
+	(BIT_CLEAR_SPEC_SIFS_CCK_8821C(x) | BIT_SPEC_SIFS_CCK_8821C(v))
+
+/* 2 REG_RESP_SIFS_CCK_8821C (RESPONSE SIFS FOR CCK REGISTER) */
+
+#define BIT_SHIFT_SIFS_R2T_CCK_8821C 8
+#define BIT_MASK_SIFS_R2T_CCK_8821C 0xff
+#define BIT_SIFS_R2T_CCK_8821C(x)                                              \
+	(((x) & BIT_MASK_SIFS_R2T_CCK_8821C) << BIT_SHIFT_SIFS_R2T_CCK_8821C)
+#define BITS_SIFS_R2T_CCK_8821C                                                \
+	(BIT_MASK_SIFS_R2T_CCK_8821C << BIT_SHIFT_SIFS_R2T_CCK_8821C)
+#define BIT_CLEAR_SIFS_R2T_CCK_8821C(x) ((x) & (~BITS_SIFS_R2T_CCK_8821C))
+#define BIT_GET_SIFS_R2T_CCK_8821C(x)                                          \
+	(((x) >> BIT_SHIFT_SIFS_R2T_CCK_8821C) & BIT_MASK_SIFS_R2T_CCK_8821C)
+#define BIT_SET_SIFS_R2T_CCK_8821C(x, v)                                       \
+	(BIT_CLEAR_SIFS_R2T_CCK_8821C(x) | BIT_SIFS_R2T_CCK_8821C(v))
+
+#define BIT_SHIFT_SIFS_T2T_CCK_8821C 0
+#define BIT_MASK_SIFS_T2T_CCK_8821C 0xff
+#define BIT_SIFS_T2T_CCK_8821C(x)                                              \
+	(((x) & BIT_MASK_SIFS_T2T_CCK_8821C) << BIT_SHIFT_SIFS_T2T_CCK_8821C)
+#define BITS_SIFS_T2T_CCK_8821C                                                \
+	(BIT_MASK_SIFS_T2T_CCK_8821C << BIT_SHIFT_SIFS_T2T_CCK_8821C)
+#define BIT_CLEAR_SIFS_T2T_CCK_8821C(x) ((x) & (~BITS_SIFS_T2T_CCK_8821C))
+#define BIT_GET_SIFS_T2T_CCK_8821C(x)                                          \
+	(((x) >> BIT_SHIFT_SIFS_T2T_CCK_8821C) & BIT_MASK_SIFS_T2T_CCK_8821C)
+#define BIT_SET_SIFS_T2T_CCK_8821C(x, v)                                       \
+	(BIT_CLEAR_SIFS_T2T_CCK_8821C(x) | BIT_SIFS_T2T_CCK_8821C(v))
+
+/* 2 REG_RESP_SIFS_OFDM_8821C (RESPONSE SIFS FOR OFDM REGISTER) */
+
+#define BIT_SHIFT_SIFS_R2T_OFDM_8821C 8
+#define BIT_MASK_SIFS_R2T_OFDM_8821C 0xff
+#define BIT_SIFS_R2T_OFDM_8821C(x)                                             \
+	(((x) & BIT_MASK_SIFS_R2T_OFDM_8821C) << BIT_SHIFT_SIFS_R2T_OFDM_8821C)
+#define BITS_SIFS_R2T_OFDM_8821C                                               \
+	(BIT_MASK_SIFS_R2T_OFDM_8821C << BIT_SHIFT_SIFS_R2T_OFDM_8821C)
+#define BIT_CLEAR_SIFS_R2T_OFDM_8821C(x) ((x) & (~BITS_SIFS_R2T_OFDM_8821C))
+#define BIT_GET_SIFS_R2T_OFDM_8821C(x)                                         \
+	(((x) >> BIT_SHIFT_SIFS_R2T_OFDM_8821C) & BIT_MASK_SIFS_R2T_OFDM_8821C)
+#define BIT_SET_SIFS_R2T_OFDM_8821C(x, v)                                      \
+	(BIT_CLEAR_SIFS_R2T_OFDM_8821C(x) | BIT_SIFS_R2T_OFDM_8821C(v))
+
+#define BIT_SHIFT_SIFS_T2T_OFDM_8821C 0
+#define BIT_MASK_SIFS_T2T_OFDM_8821C 0xff
+#define BIT_SIFS_T2T_OFDM_8821C(x)                                             \
+	(((x) & BIT_MASK_SIFS_T2T_OFDM_8821C) << BIT_SHIFT_SIFS_T2T_OFDM_8821C)
+#define BITS_SIFS_T2T_OFDM_8821C                                               \
+	(BIT_MASK_SIFS_T2T_OFDM_8821C << BIT_SHIFT_SIFS_T2T_OFDM_8821C)
+#define BIT_CLEAR_SIFS_T2T_OFDM_8821C(x) ((x) & (~BITS_SIFS_T2T_OFDM_8821C))
+#define BIT_GET_SIFS_T2T_OFDM_8821C(x)                                         \
+	(((x) >> BIT_SHIFT_SIFS_T2T_OFDM_8821C) & BIT_MASK_SIFS_T2T_OFDM_8821C)
+#define BIT_SET_SIFS_T2T_OFDM_8821C(x, v)                                      \
+	(BIT_CLEAR_SIFS_T2T_OFDM_8821C(x) | BIT_SIFS_T2T_OFDM_8821C(v))
+
+/* 2 REG_ACKTO_8821C (ACK TIMEOUT REGISTER) */
+
+#define BIT_SHIFT_ACKTO_8821C 0
+#define BIT_MASK_ACKTO_8821C 0xff
+#define BIT_ACKTO_8821C(x)                                                     \
+	(((x) & BIT_MASK_ACKTO_8821C) << BIT_SHIFT_ACKTO_8821C)
+#define BITS_ACKTO_8821C (BIT_MASK_ACKTO_8821C << BIT_SHIFT_ACKTO_8821C)
+#define BIT_CLEAR_ACKTO_8821C(x) ((x) & (~BITS_ACKTO_8821C))
+#define BIT_GET_ACKTO_8821C(x)                                                 \
+	(((x) >> BIT_SHIFT_ACKTO_8821C) & BIT_MASK_ACKTO_8821C)
+#define BIT_SET_ACKTO_8821C(x, v)                                              \
+	(BIT_CLEAR_ACKTO_8821C(x) | BIT_ACKTO_8821C(v))
+
+/* 2 REG_CTS2TO_8821C (CTS2 TIMEOUT REGISTER) */
+
+#define BIT_SHIFT_CTS2TO_8821C 0
+#define BIT_MASK_CTS2TO_8821C 0xff
+#define BIT_CTS2TO_8821C(x)                                                    \
+	(((x) & BIT_MASK_CTS2TO_8821C) << BIT_SHIFT_CTS2TO_8821C)
+#define BITS_CTS2TO_8821C (BIT_MASK_CTS2TO_8821C << BIT_SHIFT_CTS2TO_8821C)
+#define BIT_CLEAR_CTS2TO_8821C(x) ((x) & (~BITS_CTS2TO_8821C))
+#define BIT_GET_CTS2TO_8821C(x)                                                \
+	(((x) >> BIT_SHIFT_CTS2TO_8821C) & BIT_MASK_CTS2TO_8821C)
+#define BIT_SET_CTS2TO_8821C(x, v)                                             \
+	(BIT_CLEAR_CTS2TO_8821C(x) | BIT_CTS2TO_8821C(v))
+
+/* 2 REG_EIFS_8821C (EIFS REGISTER) */
+
+#define BIT_SHIFT_EIFS_8821C 0
+#define BIT_MASK_EIFS_8821C 0xffff
+#define BIT_EIFS_8821C(x) (((x) & BIT_MASK_EIFS_8821C) << BIT_SHIFT_EIFS_8821C)
+#define BITS_EIFS_8821C (BIT_MASK_EIFS_8821C << BIT_SHIFT_EIFS_8821C)
+#define BIT_CLEAR_EIFS_8821C(x) ((x) & (~BITS_EIFS_8821C))
+#define BIT_GET_EIFS_8821C(x)                                                  \
+	(((x) >> BIT_SHIFT_EIFS_8821C) & BIT_MASK_EIFS_8821C)
+#define BIT_SET_EIFS_8821C(x, v) (BIT_CLEAR_EIFS_8821C(x) | BIT_EIFS_8821C(v))
+
+/* 2 REG_RPFM_MAP0_8821C */
+#define BIT_MGT_RPFM15EN_8821C BIT(15)
+#define BIT_MGT_RPFM14EN_8821C BIT(14)
+#define BIT_MGT_RPFM13EN_8821C BIT(13)
+#define BIT_MGT_RPFM12EN_8821C BIT(12)
+#define BIT_MGT_RPFM11EN_8821C BIT(11)
+#define BIT_MGT_RPFM10EN_8821C BIT(10)
+#define BIT_MGT_RPFM9EN_8821C BIT(9)
+#define BIT_MGT_RPFM8EN_8821C BIT(8)
+#define BIT_MGT_RPFM7EN_8821C BIT(7)
+#define BIT_MGT_RPFM6EN_8821C BIT(6)
+#define BIT_MGT_RPFM5EN_8821C BIT(5)
+#define BIT_MGT_RPFM4EN_8821C BIT(4)
+#define BIT_MGT_RPFM3EN_8821C BIT(3)
+#define BIT_MGT_RPFM2EN_8821C BIT(2)
+#define BIT_MGT_RPFM1EN_8821C BIT(1)
+#define BIT_MGT_RPFM0EN_8821C BIT(0)
+
+/* 2 REG_RPFM_MAP1_V1_8821C */
+#define BIT_DATA_RPFM15EN_8821C BIT(15)
+#define BIT_DATA_RPFM14EN_8821C BIT(14)
+#define BIT_DATA_RPFM13EN_8821C BIT(13)
+#define BIT_DATA_RPFM12EN_8821C BIT(12)
+#define BIT_DATA_RPFM11EN_8821C BIT(11)
+#define BIT_DATA_RPFM10EN_8821C BIT(10)
+#define BIT_DATA_RPFM9EN_8821C BIT(9)
+#define BIT_DATA_RPFM8EN_8821C BIT(8)
+#define BIT_DATA_RPFM7EN_8821C BIT(7)
+#define BIT_DATA_RPFM6EN_8821C BIT(6)
+#define BIT_DATA_RPFM5EN_8821C BIT(5)
+#define BIT_DATA_RPFM4EN_8821C BIT(4)
+#define BIT_DATA_RPFM3EN_8821C BIT(3)
+#define BIT_DATA_RPFM2EN_8821C BIT(2)
+#define BIT_DATA_RPFM1EN_8821C BIT(1)
+#define BIT_DATA_RPFM0EN_8821C BIT(0)
+
+/* 2 REG_RPFM_CAM_CMD_8821C (RX PAYLOAD FRAME MASK CAM COMMAND REGISTER) */
+#define BIT_RPFM_CAM_POLLING_8821C BIT(31)
+#define BIT_RPFM_CAM_CLR_8821C BIT(30)
+#define BIT_RPFM_CAM_WE_8821C BIT(16)
+
+#define BIT_SHIFT_RPFM_CAM_ADDR_8821C 0
+#define BIT_MASK_RPFM_CAM_ADDR_8821C 0x7f
+#define BIT_RPFM_CAM_ADDR_8821C(x)                                             \
+	(((x) & BIT_MASK_RPFM_CAM_ADDR_8821C) << BIT_SHIFT_RPFM_CAM_ADDR_8821C)
+#define BITS_RPFM_CAM_ADDR_8821C                                               \
+	(BIT_MASK_RPFM_CAM_ADDR_8821C << BIT_SHIFT_RPFM_CAM_ADDR_8821C)
+#define BIT_CLEAR_RPFM_CAM_ADDR_8821C(x) ((x) & (~BITS_RPFM_CAM_ADDR_8821C))
+#define BIT_GET_RPFM_CAM_ADDR_8821C(x)                                         \
+	(((x) >> BIT_SHIFT_RPFM_CAM_ADDR_8821C) & BIT_MASK_RPFM_CAM_ADDR_8821C)
+#define BIT_SET_RPFM_CAM_ADDR_8821C(x, v)                                      \
+	(BIT_CLEAR_RPFM_CAM_ADDR_8821C(x) | BIT_RPFM_CAM_ADDR_8821C(v))
+
+/* 2 REG_RPFM_CAM_RWD_8821C (ACK TIMEOUT REGISTER) */
+
+#define BIT_SHIFT_RPFM_CAM_RWD_8821C 0
+#define BIT_MASK_RPFM_CAM_RWD_8821C 0xffffffffL
+#define BIT_RPFM_CAM_RWD_8821C(x)                                              \
+	(((x) & BIT_MASK_RPFM_CAM_RWD_8821C) << BIT_SHIFT_RPFM_CAM_RWD_8821C)
+#define BITS_RPFM_CAM_RWD_8821C                                                \
+	(BIT_MASK_RPFM_CAM_RWD_8821C << BIT_SHIFT_RPFM_CAM_RWD_8821C)
+#define BIT_CLEAR_RPFM_CAM_RWD_8821C(x) ((x) & (~BITS_RPFM_CAM_RWD_8821C))
+#define BIT_GET_RPFM_CAM_RWD_8821C(x)                                          \
+	(((x) >> BIT_SHIFT_RPFM_CAM_RWD_8821C) & BIT_MASK_RPFM_CAM_RWD_8821C)
+#define BIT_SET_RPFM_CAM_RWD_8821C(x, v)                                       \
+	(BIT_CLEAR_RPFM_CAM_RWD_8821C(x) | BIT_RPFM_CAM_RWD_8821C(v))
+
+/* 2 REG_NAV_CTRL_8821C (NAV CONTROL REGISTER) */
+
+#define BIT_SHIFT_NAV_UPPER_8821C 16
+#define BIT_MASK_NAV_UPPER_8821C 0xff
+#define BIT_NAV_UPPER_8821C(x)                                                 \
+	(((x) & BIT_MASK_NAV_UPPER_8821C) << BIT_SHIFT_NAV_UPPER_8821C)
+#define BITS_NAV_UPPER_8821C                                                   \
+	(BIT_MASK_NAV_UPPER_8821C << BIT_SHIFT_NAV_UPPER_8821C)
+#define BIT_CLEAR_NAV_UPPER_8821C(x) ((x) & (~BITS_NAV_UPPER_8821C))
+#define BIT_GET_NAV_UPPER_8821C(x)                                             \
+	(((x) >> BIT_SHIFT_NAV_UPPER_8821C) & BIT_MASK_NAV_UPPER_8821C)
+#define BIT_SET_NAV_UPPER_8821C(x, v)                                          \
+	(BIT_CLEAR_NAV_UPPER_8821C(x) | BIT_NAV_UPPER_8821C(v))
+
+#define BIT_SHIFT_RXMYRTS_NAV_8821C 8
+#define BIT_MASK_RXMYRTS_NAV_8821C 0xf
+#define BIT_RXMYRTS_NAV_8821C(x)                                               \
+	(((x) & BIT_MASK_RXMYRTS_NAV_8821C) << BIT_SHIFT_RXMYRTS_NAV_8821C)
+#define BITS_RXMYRTS_NAV_8821C                                                 \
+	(BIT_MASK_RXMYRTS_NAV_8821C << BIT_SHIFT_RXMYRTS_NAV_8821C)
+#define BIT_CLEAR_RXMYRTS_NAV_8821C(x) ((x) & (~BITS_RXMYRTS_NAV_8821C))
+#define BIT_GET_RXMYRTS_NAV_8821C(x)                                           \
+	(((x) >> BIT_SHIFT_RXMYRTS_NAV_8821C) & BIT_MASK_RXMYRTS_NAV_8821C)
+#define BIT_SET_RXMYRTS_NAV_8821C(x, v)                                        \
+	(BIT_CLEAR_RXMYRTS_NAV_8821C(x) | BIT_RXMYRTS_NAV_8821C(v))
+
+#define BIT_SHIFT_RTSRST_8821C 0
+#define BIT_MASK_RTSRST_8821C 0xff
+#define BIT_RTSRST_8821C(x)                                                    \
+	(((x) & BIT_MASK_RTSRST_8821C) << BIT_SHIFT_RTSRST_8821C)
+#define BITS_RTSRST_8821C (BIT_MASK_RTSRST_8821C << BIT_SHIFT_RTSRST_8821C)
+#define BIT_CLEAR_RTSRST_8821C(x) ((x) & (~BITS_RTSRST_8821C))
+#define BIT_GET_RTSRST_8821C(x)                                                \
+	(((x) >> BIT_SHIFT_RTSRST_8821C) & BIT_MASK_RTSRST_8821C)
+#define BIT_SET_RTSRST_8821C(x, v)                                             \
+	(BIT_CLEAR_RTSRST_8821C(x) | BIT_RTSRST_8821C(v))
+
+/* 2 REG_BACAMCMD_8821C (BLOCK ACK CAM COMMAND REGISTER) */
+#define BIT_BACAM_POLL_8821C BIT(31)
+#define BIT_BACAM_RST_8821C BIT(17)
+#define BIT_BACAM_RW_8821C BIT(16)
+
+#define BIT_SHIFT_TXSBM_8821C 14
+#define BIT_MASK_TXSBM_8821C 0x3
+#define BIT_TXSBM_8821C(x)                                                     \
+	(((x) & BIT_MASK_TXSBM_8821C) << BIT_SHIFT_TXSBM_8821C)
+#define BITS_TXSBM_8821C (BIT_MASK_TXSBM_8821C << BIT_SHIFT_TXSBM_8821C)
+#define BIT_CLEAR_TXSBM_8821C(x) ((x) & (~BITS_TXSBM_8821C))
+#define BIT_GET_TXSBM_8821C(x)                                                 \
+	(((x) >> BIT_SHIFT_TXSBM_8821C) & BIT_MASK_TXSBM_8821C)
+#define BIT_SET_TXSBM_8821C(x, v)                                              \
+	(BIT_CLEAR_TXSBM_8821C(x) | BIT_TXSBM_8821C(v))
+
+#define BIT_SHIFT_BACAM_ADDR_8821C 0
+#define BIT_MASK_BACAM_ADDR_8821C 0x3f
+#define BIT_BACAM_ADDR_8821C(x)                                                \
+	(((x) & BIT_MASK_BACAM_ADDR_8821C) << BIT_SHIFT_BACAM_ADDR_8821C)
+#define BITS_BACAM_ADDR_8821C                                                  \
+	(BIT_MASK_BACAM_ADDR_8821C << BIT_SHIFT_BACAM_ADDR_8821C)
+#define BIT_CLEAR_BACAM_ADDR_8821C(x) ((x) & (~BITS_BACAM_ADDR_8821C))
+#define BIT_GET_BACAM_ADDR_8821C(x)                                            \
+	(((x) >> BIT_SHIFT_BACAM_ADDR_8821C) & BIT_MASK_BACAM_ADDR_8821C)
+#define BIT_SET_BACAM_ADDR_8821C(x, v)                                         \
+	(BIT_CLEAR_BACAM_ADDR_8821C(x) | BIT_BACAM_ADDR_8821C(v))
+
+/* 2 REG_BACAMCONTENT_8821C (BLOCK ACK CAM CONTENT REGISTER) */
+
+#define BIT_SHIFT_BA_CONTENT_L_8821C 0
+#define BIT_MASK_BA_CONTENT_L_8821C 0xffffffffL
+#define BIT_BA_CONTENT_L_8821C(x)                                              \
+	(((x) & BIT_MASK_BA_CONTENT_L_8821C) << BIT_SHIFT_BA_CONTENT_L_8821C)
+#define BITS_BA_CONTENT_L_8821C                                                \
+	(BIT_MASK_BA_CONTENT_L_8821C << BIT_SHIFT_BA_CONTENT_L_8821C)
+#define BIT_CLEAR_BA_CONTENT_L_8821C(x) ((x) & (~BITS_BA_CONTENT_L_8821C))
+#define BIT_GET_BA_CONTENT_L_8821C(x)                                          \
+	(((x) >> BIT_SHIFT_BA_CONTENT_L_8821C) & BIT_MASK_BA_CONTENT_L_8821C)
+#define BIT_SET_BA_CONTENT_L_8821C(x, v)                                       \
+	(BIT_CLEAR_BA_CONTENT_L_8821C(x) | BIT_BA_CONTENT_L_8821C(v))
+
+/* 2 REG_BACAMCONTENT_H_8821C (BLOCK ACK CAM CONTENT REGISTER) */
+
+#define BIT_SHIFT_BA_CONTENT_H_8821C 0
+#define BIT_MASK_BA_CONTENT_H_8821C 0xffffffffL
+#define BIT_BA_CONTENT_H_8821C(x)                                              \
+	(((x) & BIT_MASK_BA_CONTENT_H_8821C) << BIT_SHIFT_BA_CONTENT_H_8821C)
+#define BITS_BA_CONTENT_H_8821C                                                \
+	(BIT_MASK_BA_CONTENT_H_8821C << BIT_SHIFT_BA_CONTENT_H_8821C)
+#define BIT_CLEAR_BA_CONTENT_H_8821C(x) ((x) & (~BITS_BA_CONTENT_H_8821C))
+#define BIT_GET_BA_CONTENT_H_8821C(x)                                          \
+	(((x) >> BIT_SHIFT_BA_CONTENT_H_8821C) & BIT_MASK_BA_CONTENT_H_8821C)
+#define BIT_SET_BA_CONTENT_H_8821C(x, v)                                       \
+	(BIT_CLEAR_BA_CONTENT_H_8821C(x) | BIT_BA_CONTENT_H_8821C(v))
+
+/* 2 REG_LBDLY_8821C (LOOPBACK DELAY REGISTER) */
+
+#define BIT_SHIFT_LBDLY_8821C 0
+#define BIT_MASK_LBDLY_8821C 0x1f
+#define BIT_LBDLY_8821C(x)                                                     \
+	(((x) & BIT_MASK_LBDLY_8821C) << BIT_SHIFT_LBDLY_8821C)
+#define BITS_LBDLY_8821C (BIT_MASK_LBDLY_8821C << BIT_SHIFT_LBDLY_8821C)
+#define BIT_CLEAR_LBDLY_8821C(x) ((x) & (~BITS_LBDLY_8821C))
+#define BIT_GET_LBDLY_8821C(x)                                                 \
+	(((x) >> BIT_SHIFT_LBDLY_8821C) & BIT_MASK_LBDLY_8821C)
+#define BIT_SET_LBDLY_8821C(x, v)                                              \
+	(BIT_CLEAR_LBDLY_8821C(x) | BIT_LBDLY_8821C(v))
+
+/* 2 REG_WMAC_BACAM_RPMEN_8821C */
+
+#define BIT_SHIFT_BITMAP_SSNBK_COUNTER_8821C 2
+#define BIT_MASK_BITMAP_SSNBK_COUNTER_8821C 0x3f
+#define BIT_BITMAP_SSNBK_COUNTER_8821C(x)                                      \
+	(((x) & BIT_MASK_BITMAP_SSNBK_COUNTER_8821C)                           \
+	 << BIT_SHIFT_BITMAP_SSNBK_COUNTER_8821C)
+#define BITS_BITMAP_SSNBK_COUNTER_8821C                                        \
+	(BIT_MASK_BITMAP_SSNBK_COUNTER_8821C                                   \
+	 << BIT_SHIFT_BITMAP_SSNBK_COUNTER_8821C)
+#define BIT_CLEAR_BITMAP_SSNBK_COUNTER_8821C(x)                                \
+	((x) & (~BITS_BITMAP_SSNBK_COUNTER_8821C))
+#define BIT_GET_BITMAP_SSNBK_COUNTER_8821C(x)                                  \
+	(((x) >> BIT_SHIFT_BITMAP_SSNBK_COUNTER_8821C) &                       \
+	 BIT_MASK_BITMAP_SSNBK_COUNTER_8821C)
+#define BIT_SET_BITMAP_SSNBK_COUNTER_8821C(x, v)                               \
+	(BIT_CLEAR_BITMAP_SSNBK_COUNTER_8821C(x) |                             \
+	 BIT_BITMAP_SSNBK_COUNTER_8821C(v))
+
+#define BIT_BITMAP_EN_8821C BIT(1)
+#define BIT_WMAC_BACAM_RPMEN_8821C BIT(0)
+
+/* 2 REG_TX_RX_8821C STATUS */
+
+#define BIT_SHIFT_RXPKT_TYPE_8821C 2
+#define BIT_MASK_RXPKT_TYPE_8821C 0x3f
+#define BIT_RXPKT_TYPE_8821C(x)                                                \
+	(((x) & BIT_MASK_RXPKT_TYPE_8821C) << BIT_SHIFT_RXPKT_TYPE_8821C)
+#define BITS_RXPKT_TYPE_8821C                                                  \
+	(BIT_MASK_RXPKT_TYPE_8821C << BIT_SHIFT_RXPKT_TYPE_8821C)
+#define BIT_CLEAR_RXPKT_TYPE_8821C(x) ((x) & (~BITS_RXPKT_TYPE_8821C))
+#define BIT_GET_RXPKT_TYPE_8821C(x)                                            \
+	(((x) >> BIT_SHIFT_RXPKT_TYPE_8821C) & BIT_MASK_RXPKT_TYPE_8821C)
+#define BIT_SET_RXPKT_TYPE_8821C(x, v)                                         \
+	(BIT_CLEAR_RXPKT_TYPE_8821C(x) | BIT_RXPKT_TYPE_8821C(v))
+
+#define BIT_TXACT_IND_8821C BIT(1)
+#define BIT_RXACT_IND_8821C BIT(0)
+
+/* 2 REG_WMAC_BITMAP_CTL_8821C */
+#define BIT_BITMAP_VO_8821C BIT(7)
+#define BIT_BITMAP_VI_8821C BIT(6)
+#define BIT_BITMAP_BE_8821C BIT(5)
+#define BIT_BITMAP_BK_8821C BIT(4)
+
+#define BIT_SHIFT_BITMAP_CONDITION_8821C 2
+#define BIT_MASK_BITMAP_CONDITION_8821C 0x3
+#define BIT_BITMAP_CONDITION_8821C(x)                                          \
+	(((x) & BIT_MASK_BITMAP_CONDITION_8821C)                               \
+	 << BIT_SHIFT_BITMAP_CONDITION_8821C)
+#define BITS_BITMAP_CONDITION_8821C                                            \
+	(BIT_MASK_BITMAP_CONDITION_8821C << BIT_SHIFT_BITMAP_CONDITION_8821C)
+#define BIT_CLEAR_BITMAP_CONDITION_8821C(x)                                    \
+	((x) & (~BITS_BITMAP_CONDITION_8821C))
+#define BIT_GET_BITMAP_CONDITION_8821C(x)                                      \
+	(((x) >> BIT_SHIFT_BITMAP_CONDITION_8821C) &                           \
+	 BIT_MASK_BITMAP_CONDITION_8821C)
+#define BIT_SET_BITMAP_CONDITION_8821C(x, v)                                   \
+	(BIT_CLEAR_BITMAP_CONDITION_8821C(x) | BIT_BITMAP_CONDITION_8821C(v))
+
+#define BIT_BITMAP_SSNBK_COUNTER_CLR_8821C BIT(1)
+#define BIT_BITMAP_FORCE_8821C BIT(0)
+
+/* 2 REG_RXERR_RPT_8821C (RX ERROR REPORT REGISTER) */
+
+#define BIT_SHIFT_RXERR_RPT_SEL_V1_3_0_8821C 28
+#define BIT_MASK_RXERR_RPT_SEL_V1_3_0_8821C 0xf
+#define BIT_RXERR_RPT_SEL_V1_3_0_8821C(x)                                      \
+	(((x) & BIT_MASK_RXERR_RPT_SEL_V1_3_0_8821C)                           \
+	 << BIT_SHIFT_RXERR_RPT_SEL_V1_3_0_8821C)
+#define BITS_RXERR_RPT_SEL_V1_3_0_8821C                                        \
+	(BIT_MASK_RXERR_RPT_SEL_V1_3_0_8821C                                   \
+	 << BIT_SHIFT_RXERR_RPT_SEL_V1_3_0_8821C)
+#define BIT_CLEAR_RXERR_RPT_SEL_V1_3_0_8821C(x)                                \
+	((x) & (~BITS_RXERR_RPT_SEL_V1_3_0_8821C))
+#define BIT_GET_RXERR_RPT_SEL_V1_3_0_8821C(x)                                  \
+	(((x) >> BIT_SHIFT_RXERR_RPT_SEL_V1_3_0_8821C) &                       \
+	 BIT_MASK_RXERR_RPT_SEL_V1_3_0_8821C)
+#define BIT_SET_RXERR_RPT_SEL_V1_3_0_8821C(x, v)                               \
+	(BIT_CLEAR_RXERR_RPT_SEL_V1_3_0_8821C(x) |                             \
+	 BIT_RXERR_RPT_SEL_V1_3_0_8821C(v))
+
+#define BIT_RXERR_RPT_RST_8821C BIT(27)
+#define BIT_RXERR_RPT_SEL_V1_4_8821C BIT(26)
+#define BIT_W1S_8821C BIT(23)
+#define BIT_UD_SELECT_BSSID_8821C BIT(22)
+
+#define BIT_SHIFT_UD_SUB_TYPE_8821C 18
+#define BIT_MASK_UD_SUB_TYPE_8821C 0xf
+#define BIT_UD_SUB_TYPE_8821C(x)                                               \
+	(((x) & BIT_MASK_UD_SUB_TYPE_8821C) << BIT_SHIFT_UD_SUB_TYPE_8821C)
+#define BITS_UD_SUB_TYPE_8821C                                                 \
+	(BIT_MASK_UD_SUB_TYPE_8821C << BIT_SHIFT_UD_SUB_TYPE_8821C)
+#define BIT_CLEAR_UD_SUB_TYPE_8821C(x) ((x) & (~BITS_UD_SUB_TYPE_8821C))
+#define BIT_GET_UD_SUB_TYPE_8821C(x)                                           \
+	(((x) >> BIT_SHIFT_UD_SUB_TYPE_8821C) & BIT_MASK_UD_SUB_TYPE_8821C)
+#define BIT_SET_UD_SUB_TYPE_8821C(x, v)                                        \
+	(BIT_CLEAR_UD_SUB_TYPE_8821C(x) | BIT_UD_SUB_TYPE_8821C(v))
+
+#define BIT_SHIFT_UD_TYPE_8821C 16
+#define BIT_MASK_UD_TYPE_8821C 0x3
+#define BIT_UD_TYPE_8821C(x)                                                   \
+	(((x) & BIT_MASK_UD_TYPE_8821C) << BIT_SHIFT_UD_TYPE_8821C)
+#define BITS_UD_TYPE_8821C (BIT_MASK_UD_TYPE_8821C << BIT_SHIFT_UD_TYPE_8821C)
+#define BIT_CLEAR_UD_TYPE_8821C(x) ((x) & (~BITS_UD_TYPE_8821C))
+#define BIT_GET_UD_TYPE_8821C(x)                                               \
+	(((x) >> BIT_SHIFT_UD_TYPE_8821C) & BIT_MASK_UD_TYPE_8821C)
+#define BIT_SET_UD_TYPE_8821C(x, v)                                            \
+	(BIT_CLEAR_UD_TYPE_8821C(x) | BIT_UD_TYPE_8821C(v))
+
+#define BIT_SHIFT_RPT_COUNTER_8821C 0
+#define BIT_MASK_RPT_COUNTER_8821C 0xffff
+#define BIT_RPT_COUNTER_8821C(x)                                               \
+	(((x) & BIT_MASK_RPT_COUNTER_8821C) << BIT_SHIFT_RPT_COUNTER_8821C)
+#define BITS_RPT_COUNTER_8821C                                                 \
+	(BIT_MASK_RPT_COUNTER_8821C << BIT_SHIFT_RPT_COUNTER_8821C)
+#define BIT_CLEAR_RPT_COUNTER_8821C(x) ((x) & (~BITS_RPT_COUNTER_8821C))
+#define BIT_GET_RPT_COUNTER_8821C(x)                                           \
+	(((x) >> BIT_SHIFT_RPT_COUNTER_8821C) & BIT_MASK_RPT_COUNTER_8821C)
+#define BIT_SET_RPT_COUNTER_8821C(x, v)                                        \
+	(BIT_CLEAR_RPT_COUNTER_8821C(x) | BIT_RPT_COUNTER_8821C(v))
+
+/* 2 REG_WMAC_TRXPTCL_CTL_8821C	(WMAC TX/RX PROTOCOL CONTROL REGISTER) */
+#define BIT_EN_TXCTS_INTXOP_8821C BIT(32)
+#define BIT_BLK_EDCA_BBSLP_8821C BIT(31)
+#define BIT_BLK_EDCA_BBSBY_8821C BIT(30)
+#define BIT_ACKTO_BLOCK_SCH_EN_8821C BIT(27)
+#define BIT_EIFS_BLOCK_SCH_EN_8821C BIT(26)
+#define BIT_PLCPCHK_RST_EIFS_8821C BIT(25)
+#define BIT_CCA_RST_EIFS_8821C BIT(24)
+#define BIT_DIS_UPD_MYRXPKTNAV_8821C BIT(23)
+#define BIT_EARLY_TXBA_8821C BIT(22)
+
+#define BIT_SHIFT_RESP_CHNBUSY_8821C 20
+#define BIT_MASK_RESP_CHNBUSY_8821C 0x3
+#define BIT_RESP_CHNBUSY_8821C(x)                                              \
+	(((x) & BIT_MASK_RESP_CHNBUSY_8821C) << BIT_SHIFT_RESP_CHNBUSY_8821C)
+#define BITS_RESP_CHNBUSY_8821C                                                \
+	(BIT_MASK_RESP_CHNBUSY_8821C << BIT_SHIFT_RESP_CHNBUSY_8821C)
+#define BIT_CLEAR_RESP_CHNBUSY_8821C(x) ((x) & (~BITS_RESP_CHNBUSY_8821C))
+#define BIT_GET_RESP_CHNBUSY_8821C(x)                                          \
+	(((x) >> BIT_SHIFT_RESP_CHNBUSY_8821C) & BIT_MASK_RESP_CHNBUSY_8821C)
+#define BIT_SET_RESP_CHNBUSY_8821C(x, v)                                       \
+	(BIT_CLEAR_RESP_CHNBUSY_8821C(x) | BIT_RESP_CHNBUSY_8821C(v))
+
+#define BIT_RESP_DCTS_EN_8821C BIT(19)
+#define BIT_RESP_DCFE_EN_8821C BIT(18)
+#define BIT_RESP_SPLCPEN_8821C BIT(17)
+#define BIT_RESP_SGIEN_8821C BIT(16)
+#define BIT_RESP_LDPC_EN_8821C BIT(15)
+#define BIT_DIS_RESP_ACKINCCA_8821C BIT(14)
+#define BIT_DIS_RESP_CTSINCCA_8821C BIT(13)
+
+#define BIT_SHIFT_R_WMAC_SECOND_CCA_TIMER_8821C 10
+#define BIT_MASK_R_WMAC_SECOND_CCA_TIMER_8821C 0x7
+#define BIT_R_WMAC_SECOND_CCA_TIMER_8821C(x)                                   \
+	(((x) & BIT_MASK_R_WMAC_SECOND_CCA_TIMER_8821C)                        \
+	 << BIT_SHIFT_R_WMAC_SECOND_CCA_TIMER_8821C)
+#define BITS_R_WMAC_SECOND_CCA_TIMER_8821C                                     \
+	(BIT_MASK_R_WMAC_SECOND_CCA_TIMER_8821C                                \
+	 << BIT_SHIFT_R_WMAC_SECOND_CCA_TIMER_8821C)
+#define BIT_CLEAR_R_WMAC_SECOND_CCA_TIMER_8821C(x)                             \
+	((x) & (~BITS_R_WMAC_SECOND_CCA_TIMER_8821C))
+#define BIT_GET_R_WMAC_SECOND_CCA_TIMER_8821C(x)                               \
+	(((x) >> BIT_SHIFT_R_WMAC_SECOND_CCA_TIMER_8821C) &                    \
+	 BIT_MASK_R_WMAC_SECOND_CCA_TIMER_8821C)
+#define BIT_SET_R_WMAC_SECOND_CCA_TIMER_8821C(x, v)                            \
+	(BIT_CLEAR_R_WMAC_SECOND_CCA_TIMER_8821C(x) |                          \
+	 BIT_R_WMAC_SECOND_CCA_TIMER_8821C(v))
+
+#define BIT_SHIFT_RFMOD_8821C 7
+#define BIT_MASK_RFMOD_8821C 0x3
+#define BIT_RFMOD_8821C(x)                                                     \
+	(((x) & BIT_MASK_RFMOD_8821C) << BIT_SHIFT_RFMOD_8821C)
+#define BITS_RFMOD_8821C (BIT_MASK_RFMOD_8821C << BIT_SHIFT_RFMOD_8821C)
+#define BIT_CLEAR_RFMOD_8821C(x) ((x) & (~BITS_RFMOD_8821C))
+#define BIT_GET_RFMOD_8821C(x)                                                 \
+	(((x) >> BIT_SHIFT_RFMOD_8821C) & BIT_MASK_RFMOD_8821C)
+#define BIT_SET_RFMOD_8821C(x, v)                                              \
+	(BIT_CLEAR_RFMOD_8821C(x) | BIT_RFMOD_8821C(v))
+
+#define BIT_SHIFT_RESP_CTS_DYNBW_SEL_8821C 5
+#define BIT_MASK_RESP_CTS_DYNBW_SEL_8821C 0x3
+#define BIT_RESP_CTS_DYNBW_SEL_8821C(x)                                        \
+	(((x) & BIT_MASK_RESP_CTS_DYNBW_SEL_8821C)                             \
+	 << BIT_SHIFT_RESP_CTS_DYNBW_SEL_8821C)
+#define BITS_RESP_CTS_DYNBW_SEL_8821C                                          \
+	(BIT_MASK_RESP_CTS_DYNBW_SEL_8821C                                     \
+	 << BIT_SHIFT_RESP_CTS_DYNBW_SEL_8821C)
+#define BIT_CLEAR_RESP_CTS_DYNBW_SEL_8821C(x)                                  \
+	((x) & (~BITS_RESP_CTS_DYNBW_SEL_8821C))
+#define BIT_GET_RESP_CTS_DYNBW_SEL_8821C(x)                                    \
+	(((x) >> BIT_SHIFT_RESP_CTS_DYNBW_SEL_8821C) &                         \
+	 BIT_MASK_RESP_CTS_DYNBW_SEL_8821C)
+#define BIT_SET_RESP_CTS_DYNBW_SEL_8821C(x, v)                                 \
+	(BIT_CLEAR_RESP_CTS_DYNBW_SEL_8821C(x) |                               \
+	 BIT_RESP_CTS_DYNBW_SEL_8821C(v))
+
+#define BIT_DLY_TX_WAIT_RXANTSEL_8821C BIT(4)
+#define BIT_TXRESP_BY_RXANTSEL_8821C BIT(3)
+
+#define BIT_SHIFT_ORIG_DCTS_CHK_8821C 0
+#define BIT_MASK_ORIG_DCTS_CHK_8821C 0x3
+#define BIT_ORIG_DCTS_CHK_8821C(x)                                             \
+	(((x) & BIT_MASK_ORIG_DCTS_CHK_8821C) << BIT_SHIFT_ORIG_DCTS_CHK_8821C)
+#define BITS_ORIG_DCTS_CHK_8821C                                               \
+	(BIT_MASK_ORIG_DCTS_CHK_8821C << BIT_SHIFT_ORIG_DCTS_CHK_8821C)
+#define BIT_CLEAR_ORIG_DCTS_CHK_8821C(x) ((x) & (~BITS_ORIG_DCTS_CHK_8821C))
+#define BIT_GET_ORIG_DCTS_CHK_8821C(x)                                         \
+	(((x) >> BIT_SHIFT_ORIG_DCTS_CHK_8821C) & BIT_MASK_ORIG_DCTS_CHK_8821C)
+#define BIT_SET_ORIG_DCTS_CHK_8821C(x, v)                                      \
+	(BIT_CLEAR_ORIG_DCTS_CHK_8821C(x) | BIT_ORIG_DCTS_CHK_8821C(v))
+
+/* 2 REG_WMAC_TRXPTCL_CTL_H_8821C */
+
+#define BIT_SHIFT_ACKBA_TYPSEL_8821C 28
+#define BIT_MASK_ACKBA_TYPSEL_8821C 0xf
+#define BIT_ACKBA_TYPSEL_8821C(x)                                              \
+	(((x) & BIT_MASK_ACKBA_TYPSEL_8821C) << BIT_SHIFT_ACKBA_TYPSEL_8821C)
+#define BITS_ACKBA_TYPSEL_8821C                                                \
+	(BIT_MASK_ACKBA_TYPSEL_8821C << BIT_SHIFT_ACKBA_TYPSEL_8821C)
+#define BIT_CLEAR_ACKBA_TYPSEL_8821C(x) ((x) & (~BITS_ACKBA_TYPSEL_8821C))
+#define BIT_GET_ACKBA_TYPSEL_8821C(x)                                          \
+	(((x) >> BIT_SHIFT_ACKBA_TYPSEL_8821C) & BIT_MASK_ACKBA_TYPSEL_8821C)
+#define BIT_SET_ACKBA_TYPSEL_8821C(x, v)                                       \
+	(BIT_CLEAR_ACKBA_TYPSEL_8821C(x) | BIT_ACKBA_TYPSEL_8821C(v))
+
+#define BIT_SHIFT_ACKBA_ACKPCHK_8821C 24
+#define BIT_MASK_ACKBA_ACKPCHK_8821C 0xf
+#define BIT_ACKBA_ACKPCHK_8821C(x)                                             \
+	(((x) & BIT_MASK_ACKBA_ACKPCHK_8821C) << BIT_SHIFT_ACKBA_ACKPCHK_8821C)
+#define BITS_ACKBA_ACKPCHK_8821C                                               \
+	(BIT_MASK_ACKBA_ACKPCHK_8821C << BIT_SHIFT_ACKBA_ACKPCHK_8821C)
+#define BIT_CLEAR_ACKBA_ACKPCHK_8821C(x) ((x) & (~BITS_ACKBA_ACKPCHK_8821C))
+#define BIT_GET_ACKBA_ACKPCHK_8821C(x)                                         \
+	(((x) >> BIT_SHIFT_ACKBA_ACKPCHK_8821C) & BIT_MASK_ACKBA_ACKPCHK_8821C)
+#define BIT_SET_ACKBA_ACKPCHK_8821C(x, v)                                      \
+	(BIT_CLEAR_ACKBA_ACKPCHK_8821C(x) | BIT_ACKBA_ACKPCHK_8821C(v))
+
+#define BIT_SHIFT_ACKBAR_TYPESEL_8821C 16
+#define BIT_MASK_ACKBAR_TYPESEL_8821C 0xff
+#define BIT_ACKBAR_TYPESEL_8821C(x)                                            \
+	(((x) & BIT_MASK_ACKBAR_TYPESEL_8821C)                                 \
+	 << BIT_SHIFT_ACKBAR_TYPESEL_8821C)
+#define BITS_ACKBAR_TYPESEL_8821C                                              \
+	(BIT_MASK_ACKBAR_TYPESEL_8821C << BIT_SHIFT_ACKBAR_TYPESEL_8821C)
+#define BIT_CLEAR_ACKBAR_TYPESEL_8821C(x) ((x) & (~BITS_ACKBAR_TYPESEL_8821C))
+#define BIT_GET_ACKBAR_TYPESEL_8821C(x)                                        \
+	(((x) >> BIT_SHIFT_ACKBAR_TYPESEL_8821C) &                             \
+	 BIT_MASK_ACKBAR_TYPESEL_8821C)
+#define BIT_SET_ACKBAR_TYPESEL_8821C(x, v)                                     \
+	(BIT_CLEAR_ACKBAR_TYPESEL_8821C(x) | BIT_ACKBAR_TYPESEL_8821C(v))
+
+#define BIT_SHIFT_ACKBAR_ACKPCHK_8821C 12
+#define BIT_MASK_ACKBAR_ACKPCHK_8821C 0xf
+#define BIT_ACKBAR_ACKPCHK_8821C(x)                                            \
+	(((x) & BIT_MASK_ACKBAR_ACKPCHK_8821C)                                 \
+	 << BIT_SHIFT_ACKBAR_ACKPCHK_8821C)
+#define BITS_ACKBAR_ACKPCHK_8821C                                              \
+	(BIT_MASK_ACKBAR_ACKPCHK_8821C << BIT_SHIFT_ACKBAR_ACKPCHK_8821C)
+#define BIT_CLEAR_ACKBAR_ACKPCHK_8821C(x) ((x) & (~BITS_ACKBAR_ACKPCHK_8821C))
+#define BIT_GET_ACKBAR_ACKPCHK_8821C(x)                                        \
+	(((x) >> BIT_SHIFT_ACKBAR_ACKPCHK_8821C) &                             \
+	 BIT_MASK_ACKBAR_ACKPCHK_8821C)
+#define BIT_SET_ACKBAR_ACKPCHK_8821C(x, v)                                     \
+	(BIT_CLEAR_ACKBAR_ACKPCHK_8821C(x) | BIT_ACKBAR_ACKPCHK_8821C(v))
+
+#define BIT_RXBA_IGNOREA2_V1_8821C BIT(10)
+#define BIT_EN_SAVE_ALL_TXOPADDR_V1_8821C BIT(9)
+#define BIT_EN_TXCTS_TO_TXOPOWNER_INRXNAV_V1_8821C BIT(8)
+#define BIT_DIS_TXBA_AMPDUFCSERR_V1_8821C BIT(7)
+#define BIT_DIS_TXBA_RXBARINFULL_V1_8821C BIT(6)
+#define BIT_DIS_TXCFE_INFULL_V1_8821C BIT(5)
+#define BIT_DIS_TXCTS_INFULL_V1_8821C BIT(4)
+#define BIT_EN_TXACKBA_IN_TX_RDG_V1_8821C BIT(3)
+#define BIT_EN_TXACKBA_IN_TXOP_V1_8821C BIT(2)
+#define BIT_EN_TXCTS_IN_RXNAV_V1_8821C BIT(1)
+#define BIT_EN_TXCTS_INTXOP_V1_8821C BIT(0)
+
+/* 2 REG_CAMCMD_8821C (CAM COMMAND REGISTER) */
+#define BIT_SECCAM_POLLING_8821C BIT(31)
+#define BIT_SECCAM_CLR_8821C BIT(30)
+#define BIT_MFBCAM_CLR_8821C BIT(29)
+#define BIT_SECCAM_WE_8821C BIT(16)
+
+#define BIT_SHIFT_SECCAM_ADDR_V2_8821C 0
+#define BIT_MASK_SECCAM_ADDR_V2_8821C 0x3ff
+#define BIT_SECCAM_ADDR_V2_8821C(x)                                            \
+	(((x) & BIT_MASK_SECCAM_ADDR_V2_8821C)                                 \
+	 << BIT_SHIFT_SECCAM_ADDR_V2_8821C)
+#define BITS_SECCAM_ADDR_V2_8821C                                              \
+	(BIT_MASK_SECCAM_ADDR_V2_8821C << BIT_SHIFT_SECCAM_ADDR_V2_8821C)
+#define BIT_CLEAR_SECCAM_ADDR_V2_8821C(x) ((x) & (~BITS_SECCAM_ADDR_V2_8821C))
+#define BIT_GET_SECCAM_ADDR_V2_8821C(x)                                        \
+	(((x) >> BIT_SHIFT_SECCAM_ADDR_V2_8821C) &                             \
+	 BIT_MASK_SECCAM_ADDR_V2_8821C)
+#define BIT_SET_SECCAM_ADDR_V2_8821C(x, v)                                     \
+	(BIT_CLEAR_SECCAM_ADDR_V2_8821C(x) | BIT_SECCAM_ADDR_V2_8821C(v))
+
+/* 2 REG_CAMWRITE_8821C (CAM WRITE REGISTER) */
+
+#define BIT_SHIFT_CAMW_DATA_8821C 0
+#define BIT_MASK_CAMW_DATA_8821C 0xffffffffL
+#define BIT_CAMW_DATA_8821C(x)                                                 \
+	(((x) & BIT_MASK_CAMW_DATA_8821C) << BIT_SHIFT_CAMW_DATA_8821C)
+#define BITS_CAMW_DATA_8821C                                                   \
+	(BIT_MASK_CAMW_DATA_8821C << BIT_SHIFT_CAMW_DATA_8821C)
+#define BIT_CLEAR_CAMW_DATA_8821C(x) ((x) & (~BITS_CAMW_DATA_8821C))
+#define BIT_GET_CAMW_DATA_8821C(x)                                             \
+	(((x) >> BIT_SHIFT_CAMW_DATA_8821C) & BIT_MASK_CAMW_DATA_8821C)
+#define BIT_SET_CAMW_DATA_8821C(x, v)                                          \
+	(BIT_CLEAR_CAMW_DATA_8821C(x) | BIT_CAMW_DATA_8821C(v))
+
+/* 2 REG_CAMREAD_8821C (CAM READ REGISTER) */
+
+#define BIT_SHIFT_CAMR_DATA_8821C 0
+#define BIT_MASK_CAMR_DATA_8821C 0xffffffffL
+#define BIT_CAMR_DATA_8821C(x)                                                 \
+	(((x) & BIT_MASK_CAMR_DATA_8821C) << BIT_SHIFT_CAMR_DATA_8821C)
+#define BITS_CAMR_DATA_8821C                                                   \
+	(BIT_MASK_CAMR_DATA_8821C << BIT_SHIFT_CAMR_DATA_8821C)
+#define BIT_CLEAR_CAMR_DATA_8821C(x) ((x) & (~BITS_CAMR_DATA_8821C))
+#define BIT_GET_CAMR_DATA_8821C(x)                                             \
+	(((x) >> BIT_SHIFT_CAMR_DATA_8821C) & BIT_MASK_CAMR_DATA_8821C)
+#define BIT_SET_CAMR_DATA_8821C(x, v)                                          \
+	(BIT_CLEAR_CAMR_DATA_8821C(x) | BIT_CAMR_DATA_8821C(v))
+
+/* 2 REG_CAMDBG_8821C (CAM DEBUG REGISTER) */
+#define BIT_SECCAM_INFO_8821C BIT(31)
+#define BIT_SEC_KEYFOUND_8821C BIT(15)
+
+#define BIT_SHIFT_CAMDBG_SEC_TYPE_8821C 12
+#define BIT_MASK_CAMDBG_SEC_TYPE_8821C 0x7
+#define BIT_CAMDBG_SEC_TYPE_8821C(x)                                           \
+	(((x) & BIT_MASK_CAMDBG_SEC_TYPE_8821C)                                \
+	 << BIT_SHIFT_CAMDBG_SEC_TYPE_8821C)
+#define BITS_CAMDBG_SEC_TYPE_8821C                                             \
+	(BIT_MASK_CAMDBG_SEC_TYPE_8821C << BIT_SHIFT_CAMDBG_SEC_TYPE_8821C)
+#define BIT_CLEAR_CAMDBG_SEC_TYPE_8821C(x) ((x) & (~BITS_CAMDBG_SEC_TYPE_8821C))
+#define BIT_GET_CAMDBG_SEC_TYPE_8821C(x)                                       \
+	(((x) >> BIT_SHIFT_CAMDBG_SEC_TYPE_8821C) &                            \
+	 BIT_MASK_CAMDBG_SEC_TYPE_8821C)
+#define BIT_SET_CAMDBG_SEC_TYPE_8821C(x, v)                                    \
+	(BIT_CLEAR_CAMDBG_SEC_TYPE_8821C(x) | BIT_CAMDBG_SEC_TYPE_8821C(v))
+
+#define BIT_CAMDBG_EXT_SECTYPE_8821C BIT(11)
+
+#define BIT_SHIFT_CAMDBG_MIC_KEY_IDX_8821C 5
+#define BIT_MASK_CAMDBG_MIC_KEY_IDX_8821C 0x1f
+#define BIT_CAMDBG_MIC_KEY_IDX_8821C(x)                                        \
+	(((x) & BIT_MASK_CAMDBG_MIC_KEY_IDX_8821C)                             \
+	 << BIT_SHIFT_CAMDBG_MIC_KEY_IDX_8821C)
+#define BITS_CAMDBG_MIC_KEY_IDX_8821C                                          \
+	(BIT_MASK_CAMDBG_MIC_KEY_IDX_8821C                                     \
+	 << BIT_SHIFT_CAMDBG_MIC_KEY_IDX_8821C)
+#define BIT_CLEAR_CAMDBG_MIC_KEY_IDX_8821C(x)                                  \
+	((x) & (~BITS_CAMDBG_MIC_KEY_IDX_8821C))
+#define BIT_GET_CAMDBG_MIC_KEY_IDX_8821C(x)                                    \
+	(((x) >> BIT_SHIFT_CAMDBG_MIC_KEY_IDX_8821C) &                         \
+	 BIT_MASK_CAMDBG_MIC_KEY_IDX_8821C)
+#define BIT_SET_CAMDBG_MIC_KEY_IDX_8821C(x, v)                                 \
+	(BIT_CLEAR_CAMDBG_MIC_KEY_IDX_8821C(x) |                               \
+	 BIT_CAMDBG_MIC_KEY_IDX_8821C(v))
+
+#define BIT_SHIFT_CAMDBG_SEC_KEY_IDX_8821C 0
+#define BIT_MASK_CAMDBG_SEC_KEY_IDX_8821C 0x1f
+#define BIT_CAMDBG_SEC_KEY_IDX_8821C(x)                                        \
+	(((x) & BIT_MASK_CAMDBG_SEC_KEY_IDX_8821C)                             \
+	 << BIT_SHIFT_CAMDBG_SEC_KEY_IDX_8821C)
+#define BITS_CAMDBG_SEC_KEY_IDX_8821C                                          \
+	(BIT_MASK_CAMDBG_SEC_KEY_IDX_8821C                                     \
+	 << BIT_SHIFT_CAMDBG_SEC_KEY_IDX_8821C)
+#define BIT_CLEAR_CAMDBG_SEC_KEY_IDX_8821C(x)                                  \
+	((x) & (~BITS_CAMDBG_SEC_KEY_IDX_8821C))
+#define BIT_GET_CAMDBG_SEC_KEY_IDX_8821C(x)                                    \
+	(((x) >> BIT_SHIFT_CAMDBG_SEC_KEY_IDX_8821C) &                         \
+	 BIT_MASK_CAMDBG_SEC_KEY_IDX_8821C)
+#define BIT_SET_CAMDBG_SEC_KEY_IDX_8821C(x, v)                                 \
+	(BIT_CLEAR_CAMDBG_SEC_KEY_IDX_8821C(x) |                               \
+	 BIT_CAMDBG_SEC_KEY_IDX_8821C(v))
+
+/* 2 REG_SECCFG_8821C (SECURITY CONFIGURATION REGISTER) */
+#define BIT_DIS_GCLK_WAPI_8821C BIT(15)
+#define BIT_DIS_GCLK_AES_8821C BIT(14)
+#define BIT_DIS_GCLK_TKIP_8821C BIT(13)
+#define BIT_AES_SEL_QC_1_8821C BIT(12)
+#define BIT_AES_SEL_QC_0_8821C BIT(11)
+#define BIT_CHK_BMC_8821C BIT(9)
+#define BIT_CHK_KEYID_8821C BIT(8)
+#define BIT_RXBCUSEDK_8821C BIT(7)
+#define BIT_TXBCUSEDK_8821C BIT(6)
+#define BIT_NOSKMC_8821C BIT(5)
+#define BIT_SKBYA2_8821C BIT(4)
+#define BIT_RXDEC_8821C BIT(3)
+#define BIT_TXENC_8821C BIT(2)
+#define BIT_RXUHUSEDK_8821C BIT(1)
+#define BIT_TXUHUSEDK_8821C BIT(0)
+
+/* 2 REG_RXFILTER_CATEGORY_1_8821C */
+
+#define BIT_SHIFT_RXFILTER_CATEGORY_1_8821C 0
+#define BIT_MASK_RXFILTER_CATEGORY_1_8821C 0xff
+#define BIT_RXFILTER_CATEGORY_1_8821C(x)                                       \
+	(((x) & BIT_MASK_RXFILTER_CATEGORY_1_8821C)                            \
+	 << BIT_SHIFT_RXFILTER_CATEGORY_1_8821C)
+#define BITS_RXFILTER_CATEGORY_1_8821C                                         \
+	(BIT_MASK_RXFILTER_CATEGORY_1_8821C                                    \
+	 << BIT_SHIFT_RXFILTER_CATEGORY_1_8821C)
+#define BIT_CLEAR_RXFILTER_CATEGORY_1_8821C(x)                                 \
+	((x) & (~BITS_RXFILTER_CATEGORY_1_8821C))
+#define BIT_GET_RXFILTER_CATEGORY_1_8821C(x)                                   \
+	(((x) >> BIT_SHIFT_RXFILTER_CATEGORY_1_8821C) &                        \
+	 BIT_MASK_RXFILTER_CATEGORY_1_8821C)
+#define BIT_SET_RXFILTER_CATEGORY_1_8821C(x, v)                                \
+	(BIT_CLEAR_RXFILTER_CATEGORY_1_8821C(x) |                              \
+	 BIT_RXFILTER_CATEGORY_1_8821C(v))
+
+/* 2 REG_RXFILTER_ACTION_1_8821C */
+
+#define BIT_SHIFT_RXFILTER_ACTION_1_8821C 0
+#define BIT_MASK_RXFILTER_ACTION_1_8821C 0xff
+#define BIT_RXFILTER_ACTION_1_8821C(x)                                         \
+	(((x) & BIT_MASK_RXFILTER_ACTION_1_8821C)                              \
+	 << BIT_SHIFT_RXFILTER_ACTION_1_8821C)
+#define BITS_RXFILTER_ACTION_1_8821C                                           \
+	(BIT_MASK_RXFILTER_ACTION_1_8821C << BIT_SHIFT_RXFILTER_ACTION_1_8821C)
+#define BIT_CLEAR_RXFILTER_ACTION_1_8821C(x)                                   \
+	((x) & (~BITS_RXFILTER_ACTION_1_8821C))
+#define BIT_GET_RXFILTER_ACTION_1_8821C(x)                                     \
+	(((x) >> BIT_SHIFT_RXFILTER_ACTION_1_8821C) &                          \
+	 BIT_MASK_RXFILTER_ACTION_1_8821C)
+#define BIT_SET_RXFILTER_ACTION_1_8821C(x, v)                                  \
+	(BIT_CLEAR_RXFILTER_ACTION_1_8821C(x) | BIT_RXFILTER_ACTION_1_8821C(v))
+
+/* 2 REG_RXFILTER_CATEGORY_2_8821C */
+
+#define BIT_SHIFT_RXFILTER_CATEGORY_2_8821C 0
+#define BIT_MASK_RXFILTER_CATEGORY_2_8821C 0xff
+#define BIT_RXFILTER_CATEGORY_2_8821C(x)                                       \
+	(((x) & BIT_MASK_RXFILTER_CATEGORY_2_8821C)                            \
+	 << BIT_SHIFT_RXFILTER_CATEGORY_2_8821C)
+#define BITS_RXFILTER_CATEGORY_2_8821C                                         \
+	(BIT_MASK_RXFILTER_CATEGORY_2_8821C                                    \
+	 << BIT_SHIFT_RXFILTER_CATEGORY_2_8821C)
+#define BIT_CLEAR_RXFILTER_CATEGORY_2_8821C(x)                                 \
+	((x) & (~BITS_RXFILTER_CATEGORY_2_8821C))
+#define BIT_GET_RXFILTER_CATEGORY_2_8821C(x)                                   \
+	(((x) >> BIT_SHIFT_RXFILTER_CATEGORY_2_8821C) &                        \
+	 BIT_MASK_RXFILTER_CATEGORY_2_8821C)
+#define BIT_SET_RXFILTER_CATEGORY_2_8821C(x, v)                                \
+	(BIT_CLEAR_RXFILTER_CATEGORY_2_8821C(x) |                              \
+	 BIT_RXFILTER_CATEGORY_2_8821C(v))
+
+/* 2 REG_RXFILTER_ACTION_2_8821C */
+
+#define BIT_SHIFT_RXFILTER_ACTION_2_8821C 0
+#define BIT_MASK_RXFILTER_ACTION_2_8821C 0xff
+#define BIT_RXFILTER_ACTION_2_8821C(x)                                         \
+	(((x) & BIT_MASK_RXFILTER_ACTION_2_8821C)                              \
+	 << BIT_SHIFT_RXFILTER_ACTION_2_8821C)
+#define BITS_RXFILTER_ACTION_2_8821C                                           \
+	(BIT_MASK_RXFILTER_ACTION_2_8821C << BIT_SHIFT_RXFILTER_ACTION_2_8821C)
+#define BIT_CLEAR_RXFILTER_ACTION_2_8821C(x)                                   \
+	((x) & (~BITS_RXFILTER_ACTION_2_8821C))
+#define BIT_GET_RXFILTER_ACTION_2_8821C(x)                                     \
+	(((x) >> BIT_SHIFT_RXFILTER_ACTION_2_8821C) &                          \
+	 BIT_MASK_RXFILTER_ACTION_2_8821C)
+#define BIT_SET_RXFILTER_ACTION_2_8821C(x, v)                                  \
+	(BIT_CLEAR_RXFILTER_ACTION_2_8821C(x) | BIT_RXFILTER_ACTION_2_8821C(v))
+
+/* 2 REG_RXFILTER_CATEGORY_3_8821C */
+
+#define BIT_SHIFT_RXFILTER_CATEGORY_3_8821C 0
+#define BIT_MASK_RXFILTER_CATEGORY_3_8821C 0xff
+#define BIT_RXFILTER_CATEGORY_3_8821C(x)                                       \
+	(((x) & BIT_MASK_RXFILTER_CATEGORY_3_8821C)                            \
+	 << BIT_SHIFT_RXFILTER_CATEGORY_3_8821C)
+#define BITS_RXFILTER_CATEGORY_3_8821C                                         \
+	(BIT_MASK_RXFILTER_CATEGORY_3_8821C                                    \
+	 << BIT_SHIFT_RXFILTER_CATEGORY_3_8821C)
+#define BIT_CLEAR_RXFILTER_CATEGORY_3_8821C(x)                                 \
+	((x) & (~BITS_RXFILTER_CATEGORY_3_8821C))
+#define BIT_GET_RXFILTER_CATEGORY_3_8821C(x)                                   \
+	(((x) >> BIT_SHIFT_RXFILTER_CATEGORY_3_8821C) &                        \
+	 BIT_MASK_RXFILTER_CATEGORY_3_8821C)
+#define BIT_SET_RXFILTER_CATEGORY_3_8821C(x, v)                                \
+	(BIT_CLEAR_RXFILTER_CATEGORY_3_8821C(x) |                              \
+	 BIT_RXFILTER_CATEGORY_3_8821C(v))
+
+/* 2 REG_RXFILTER_ACTION_3_8821C */
+
+#define BIT_SHIFT_RXFILTER_ACTION_3_8821C 0
+#define BIT_MASK_RXFILTER_ACTION_3_8821C 0xff
+#define BIT_RXFILTER_ACTION_3_8821C(x)                                         \
+	(((x) & BIT_MASK_RXFILTER_ACTION_3_8821C)                              \
+	 << BIT_SHIFT_RXFILTER_ACTION_3_8821C)
+#define BITS_RXFILTER_ACTION_3_8821C                                           \
+	(BIT_MASK_RXFILTER_ACTION_3_8821C << BIT_SHIFT_RXFILTER_ACTION_3_8821C)
+#define BIT_CLEAR_RXFILTER_ACTION_3_8821C(x)                                   \
+	((x) & (~BITS_RXFILTER_ACTION_3_8821C))
+#define BIT_GET_RXFILTER_ACTION_3_8821C(x)                                     \
+	(((x) >> BIT_SHIFT_RXFILTER_ACTION_3_8821C) &                          \
+	 BIT_MASK_RXFILTER_ACTION_3_8821C)
+#define BIT_SET_RXFILTER_ACTION_3_8821C(x, v)                                  \
+	(BIT_CLEAR_RXFILTER_ACTION_3_8821C(x) | BIT_RXFILTER_ACTION_3_8821C(v))
+
+/* 2 REG_RXFLTMAP3_8821C (RX FILTER MAP GROUP 3) */
+#define BIT_MGTFLT15EN_FW_8821C BIT(15)
+#define BIT_MGTFLT14EN_FW_8821C BIT(14)
+#define BIT_MGTFLT13EN_FW_8821C BIT(13)
+#define BIT_MGTFLT12EN_FW_8821C BIT(12)
+#define BIT_MGTFLT11EN_FW_8821C BIT(11)
+#define BIT_MGTFLT10EN_FW_8821C BIT(10)
+#define BIT_MGTFLT9EN_FW_8821C BIT(9)
+#define BIT_MGTFLT8EN_FW_8821C BIT(8)
+#define BIT_MGTFLT7EN_FW_8821C BIT(7)
+#define BIT_MGTFLT6EN_FW_8821C BIT(6)
+#define BIT_MGTFLT5EN_FW_8821C BIT(5)
+#define BIT_MGTFLT4EN_FW_8821C BIT(4)
+#define BIT_MGTFLT3EN_FW_8821C BIT(3)
+#define BIT_MGTFLT2EN_FW_8821C BIT(2)
+#define BIT_MGTFLT1EN_FW_8821C BIT(1)
+#define BIT_MGTFLT0EN_FW_8821C BIT(0)
+
+/* 2 REG_RXFLTMAP4_8821C (RX FILTER MAP GROUP 4) */
+#define BIT_CTRLFLT15EN_FW_8821C BIT(15)
+#define BIT_CTRLFLT14EN_FW_8821C BIT(14)
+#define BIT_CTRLFLT13EN_FW_8821C BIT(13)
+#define BIT_CTRLFLT12EN_FW_8821C BIT(12)
+#define BIT_CTRLFLT11EN_FW_8821C BIT(11)
+#define BIT_CTRLFLT10EN_FW_8821C BIT(10)
+#define BIT_CTRLFLT9EN_FW_8821C BIT(9)
+#define BIT_CTRLFLT8EN_FW_8821C BIT(8)
+#define BIT_CTRLFLT7EN_FW_8821C BIT(7)
+#define BIT_CTRLFLT6EN_FW_8821C BIT(6)
+#define BIT_CTRLFLT5EN_FW_8821C BIT(5)
+#define BIT_CTRLFLT4EN_FW_8821C BIT(4)
+#define BIT_CTRLFLT3EN_FW_8821C BIT(3)
+#define BIT_CTRLFLT2EN_FW_8821C BIT(2)
+#define BIT_CTRLFLT1EN_FW_8821C BIT(1)
+#define BIT_CTRLFLT0EN_FW_8821C BIT(0)
+
+/* 2 REG_RXFLTMAP5_8821C (RX FILTER MAP GROUP 5) */
+#define BIT_DATAFLT15EN_FW_8821C BIT(15)
+#define BIT_DATAFLT14EN_FW_8821C BIT(14)
+#define BIT_DATAFLT13EN_FW_8821C BIT(13)
+#define BIT_DATAFLT12EN_FW_8821C BIT(12)
+#define BIT_DATAFLT11EN_FW_8821C BIT(11)
+#define BIT_DATAFLT10EN_FW_8821C BIT(10)
+#define BIT_DATAFLT9EN_FW_8821C BIT(9)
+#define BIT_DATAFLT8EN_FW_8821C BIT(8)
+#define BIT_DATAFLT7EN_FW_8821C BIT(7)
+#define BIT_DATAFLT6EN_FW_8821C BIT(6)
+#define BIT_DATAFLT5EN_FW_8821C BIT(5)
+#define BIT_DATAFLT4EN_FW_8821C BIT(4)
+#define BIT_DATAFLT3EN_FW_8821C BIT(3)
+#define BIT_DATAFLT2EN_FW_8821C BIT(2)
+#define BIT_DATAFLT1EN_FW_8821C BIT(1)
+#define BIT_DATAFLT0EN_FW_8821C BIT(0)
+
+/* 2 REG_RXFLTMAP6_8821C (RX FILTER MAP GROUP 6) */
+#define BIT_ACTIONFLT15EN_FW_8821C BIT(15)
+#define BIT_ACTIONFLT14EN_FW_8821C BIT(14)
+#define BIT_ACTIONFLT13EN_FW_8821C BIT(13)
+#define BIT_ACTIONFLT12EN_FW_8821C BIT(12)
+#define BIT_ACTIONFLT11EN_FW_8821C BIT(11)
+#define BIT_ACTIONFLT10EN_FW_8821C BIT(10)
+#define BIT_ACTIONFLT9EN_FW_8821C BIT(9)
+#define BIT_ACTIONFLT8EN_FW_8821C BIT(8)
+#define BIT_ACTIONFLT7EN_FW_8821C BIT(7)
+#define BIT_ACTIONFLT6EN_FW_8821C BIT(6)
+#define BIT_ACTIONFLT5EN_FW_8821C BIT(5)
+#define BIT_ACTIONFLT4EN_FW_8821C BIT(4)
+#define BIT_ACTIONFLT3EN_FW_8821C BIT(3)
+#define BIT_ACTIONFLT2EN_FW_8821C BIT(2)
+#define BIT_ACTIONFLT1EN_FW_8821C BIT(1)
+#define BIT_ACTIONFLT0EN_FW_8821C BIT(0)
+
+/* 2 REG_WOW_CTRL_8821C (WAKE ON WLAN CONTROL REGISTER) */
+
+#define BIT_SHIFT_PSF_BSSIDSEL_B2B1_8821C 6
+#define BIT_MASK_PSF_BSSIDSEL_B2B1_8821C 0x3
+#define BIT_PSF_BSSIDSEL_B2B1_8821C(x)                                         \
+	(((x) & BIT_MASK_PSF_BSSIDSEL_B2B1_8821C)                              \
+	 << BIT_SHIFT_PSF_BSSIDSEL_B2B1_8821C)
+#define BITS_PSF_BSSIDSEL_B2B1_8821C                                           \
+	(BIT_MASK_PSF_BSSIDSEL_B2B1_8821C << BIT_SHIFT_PSF_BSSIDSEL_B2B1_8821C)
+#define BIT_CLEAR_PSF_BSSIDSEL_B2B1_8821C(x)                                   \
+	((x) & (~BITS_PSF_BSSIDSEL_B2B1_8821C))
+#define BIT_GET_PSF_BSSIDSEL_B2B1_8821C(x)                                     \
+	(((x) >> BIT_SHIFT_PSF_BSSIDSEL_B2B1_8821C) &                          \
+	 BIT_MASK_PSF_BSSIDSEL_B2B1_8821C)
+#define BIT_SET_PSF_BSSIDSEL_B2B1_8821C(x, v)                                  \
+	(BIT_CLEAR_PSF_BSSIDSEL_B2B1_8821C(x) | BIT_PSF_BSSIDSEL_B2B1_8821C(v))
+
+#define BIT_WOWHCI_8821C BIT(5)
+#define BIT_PSF_BSSIDSEL_B0_8821C BIT(4)
+#define BIT_UWF_8821C BIT(3)
+#define BIT_MAGIC_8821C BIT(2)
+#define BIT_WOWEN_8821C BIT(1)
+#define BIT_FORCE_WAKEUP_8821C BIT(0)
+
+/* 2 REG_NAN_RX_TSF_FILTER_8821C(NAN_RX_TSF_ADDRESS_FILTER) */
+#define BIT_CHK_TSF_TA_8821C BIT(2)
+#define BIT_CHK_TSF_CBSSID_8821C BIT(1)
+#define BIT_CHK_TSF_EN_8821C BIT(0)
+
+/* 2 REG_PS_RX_INFO_8821C (POWER SAVE RX INFORMATION REGISTER) */
+
+#define BIT_SHIFT_PORTSEL__PS_RX_INFO_8821C 5
+#define BIT_MASK_PORTSEL__PS_RX_INFO_8821C 0x7
+#define BIT_PORTSEL__PS_RX_INFO_8821C(x)                                       \
+	(((x) & BIT_MASK_PORTSEL__PS_RX_INFO_8821C)                            \
+	 << BIT_SHIFT_PORTSEL__PS_RX_INFO_8821C)
+#define BITS_PORTSEL__PS_RX_INFO_8821C                                         \
+	(BIT_MASK_PORTSEL__PS_RX_INFO_8821C                                    \
+	 << BIT_SHIFT_PORTSEL__PS_RX_INFO_8821C)
+#define BIT_CLEAR_PORTSEL__PS_RX_INFO_8821C(x)                                 \
+	((x) & (~BITS_PORTSEL__PS_RX_INFO_8821C))
+#define BIT_GET_PORTSEL__PS_RX_INFO_8821C(x)                                   \
+	(((x) >> BIT_SHIFT_PORTSEL__PS_RX_INFO_8821C) &                        \
+	 BIT_MASK_PORTSEL__PS_RX_INFO_8821C)
+#define BIT_SET_PORTSEL__PS_RX_INFO_8821C(x, v)                                \
+	(BIT_CLEAR_PORTSEL__PS_RX_INFO_8821C(x) |                              \
+	 BIT_PORTSEL__PS_RX_INFO_8821C(v))
+
+#define BIT_RXCTRLIN0_8821C BIT(4)
+#define BIT_RXMGTIN0_8821C BIT(3)
+#define BIT_RXDATAIN2_8821C BIT(2)
+#define BIT_RXDATAIN1_8821C BIT(1)
+#define BIT_RXDATAIN0_8821C BIT(0)
+
+/* 2 REG_WMMPS_UAPSD_TID_8821C (WMM POWER SAVE UAPSD TID REGISTER) */
+#define BIT_WMMPS_UAPSD_TID7_8821C BIT(7)
+#define BIT_WMMPS_UAPSD_TID6_8821C BIT(6)
+#define BIT_WMMPS_UAPSD_TID5_8821C BIT(5)
+#define BIT_WMMPS_UAPSD_TID4_8821C BIT(4)
+#define BIT_WMMPS_UAPSD_TID3_8821C BIT(3)
+#define BIT_WMMPS_UAPSD_TID2_8821C BIT(2)
+#define BIT_WMMPS_UAPSD_TID1_8821C BIT(1)
+#define BIT_WMMPS_UAPSD_TID0_8821C BIT(0)
+
+/* 2 REG_LPNAV_CTRL_8821C (LOW POWER NAV CONTROL REGISTER) */
+#define BIT_LPNAV_EN_8821C BIT(31)
+
+#define BIT_SHIFT_LPNAV_EARLY_8821C 16
+#define BIT_MASK_LPNAV_EARLY_8821C 0x7fff
+#define BIT_LPNAV_EARLY_8821C(x)                                               \
+	(((x) & BIT_MASK_LPNAV_EARLY_8821C) << BIT_SHIFT_LPNAV_EARLY_8821C)
+#define BITS_LPNAV_EARLY_8821C                                                 \
+	(BIT_MASK_LPNAV_EARLY_8821C << BIT_SHIFT_LPNAV_EARLY_8821C)
+#define BIT_CLEAR_LPNAV_EARLY_8821C(x) ((x) & (~BITS_LPNAV_EARLY_8821C))
+#define BIT_GET_LPNAV_EARLY_8821C(x)                                           \
+	(((x) >> BIT_SHIFT_LPNAV_EARLY_8821C) & BIT_MASK_LPNAV_EARLY_8821C)
+#define BIT_SET_LPNAV_EARLY_8821C(x, v)                                        \
+	(BIT_CLEAR_LPNAV_EARLY_8821C(x) | BIT_LPNAV_EARLY_8821C(v))
+
+#define BIT_SHIFT_LPNAV_TH_8821C 0
+#define BIT_MASK_LPNAV_TH_8821C 0xffff
+#define BIT_LPNAV_TH_8821C(x)                                                  \
+	(((x) & BIT_MASK_LPNAV_TH_8821C) << BIT_SHIFT_LPNAV_TH_8821C)
+#define BITS_LPNAV_TH_8821C                                                    \
+	(BIT_MASK_LPNAV_TH_8821C << BIT_SHIFT_LPNAV_TH_8821C)
+#define BIT_CLEAR_LPNAV_TH_8821C(x) ((x) & (~BITS_LPNAV_TH_8821C))
+#define BIT_GET_LPNAV_TH_8821C(x)                                              \
+	(((x) >> BIT_SHIFT_LPNAV_TH_8821C) & BIT_MASK_LPNAV_TH_8821C)
+#define BIT_SET_LPNAV_TH_8821C(x, v)                                           \
+	(BIT_CLEAR_LPNAV_TH_8821C(x) | BIT_LPNAV_TH_8821C(v))
+
+/* 2 REG_WKFMCAM_CMD_8821C (WAKEUP FRAME CAM COMMAND REGISTER) */
+#define BIT_WKFCAM_POLLING_V1_8821C BIT(31)
+#define BIT_WKFCAM_CLR_V1_8821C BIT(30)
+#define BIT_WKFCAM_WE_8821C BIT(16)
+
+#define BIT_SHIFT_WKFCAM_ADDR_V2_8821C 8
+#define BIT_MASK_WKFCAM_ADDR_V2_8821C 0xff
+#define BIT_WKFCAM_ADDR_V2_8821C(x)                                            \
+	(((x) & BIT_MASK_WKFCAM_ADDR_V2_8821C)                                 \
+	 << BIT_SHIFT_WKFCAM_ADDR_V2_8821C)
+#define BITS_WKFCAM_ADDR_V2_8821C                                              \
+	(BIT_MASK_WKFCAM_ADDR_V2_8821C << BIT_SHIFT_WKFCAM_ADDR_V2_8821C)
+#define BIT_CLEAR_WKFCAM_ADDR_V2_8821C(x) ((x) & (~BITS_WKFCAM_ADDR_V2_8821C))
+#define BIT_GET_WKFCAM_ADDR_V2_8821C(x)                                        \
+	(((x) >> BIT_SHIFT_WKFCAM_ADDR_V2_8821C) &                             \
+	 BIT_MASK_WKFCAM_ADDR_V2_8821C)
+#define BIT_SET_WKFCAM_ADDR_V2_8821C(x, v)                                     \
+	(BIT_CLEAR_WKFCAM_ADDR_V2_8821C(x) | BIT_WKFCAM_ADDR_V2_8821C(v))
+
+#define BIT_SHIFT_WKFCAM_CAM_NUM_V1_8821C 0
+#define BIT_MASK_WKFCAM_CAM_NUM_V1_8821C 0xff
+#define BIT_WKFCAM_CAM_NUM_V1_8821C(x)                                         \
+	(((x) & BIT_MASK_WKFCAM_CAM_NUM_V1_8821C)                              \
+	 << BIT_SHIFT_WKFCAM_CAM_NUM_V1_8821C)
+#define BITS_WKFCAM_CAM_NUM_V1_8821C                                           \
+	(BIT_MASK_WKFCAM_CAM_NUM_V1_8821C << BIT_SHIFT_WKFCAM_CAM_NUM_V1_8821C)
+#define BIT_CLEAR_WKFCAM_CAM_NUM_V1_8821C(x)                                   \
+	((x) & (~BITS_WKFCAM_CAM_NUM_V1_8821C))
+#define BIT_GET_WKFCAM_CAM_NUM_V1_8821C(x)                                     \
+	(((x) >> BIT_SHIFT_WKFCAM_CAM_NUM_V1_8821C) &                          \
+	 BIT_MASK_WKFCAM_CAM_NUM_V1_8821C)
+#define BIT_SET_WKFCAM_CAM_NUM_V1_8821C(x, v)                                  \
+	(BIT_CLEAR_WKFCAM_CAM_NUM_V1_8821C(x) | BIT_WKFCAM_CAM_NUM_V1_8821C(v))
+
+/* 2 REG_WKFMCAM_RWD_8821C (WAKEUP FRAME READ/WRITE DATA) */
+
+#define BIT_SHIFT_WKFMCAM_RWD_8821C 0
+#define BIT_MASK_WKFMCAM_RWD_8821C 0xffffffffL
+#define BIT_WKFMCAM_RWD_8821C(x)                                               \
+	(((x) & BIT_MASK_WKFMCAM_RWD_8821C) << BIT_SHIFT_WKFMCAM_RWD_8821C)
+#define BITS_WKFMCAM_RWD_8821C                                                 \
+	(BIT_MASK_WKFMCAM_RWD_8821C << BIT_SHIFT_WKFMCAM_RWD_8821C)
+#define BIT_CLEAR_WKFMCAM_RWD_8821C(x) ((x) & (~BITS_WKFMCAM_RWD_8821C))
+#define BIT_GET_WKFMCAM_RWD_8821C(x)                                           \
+	(((x) >> BIT_SHIFT_WKFMCAM_RWD_8821C) & BIT_MASK_WKFMCAM_RWD_8821C)
+#define BIT_SET_WKFMCAM_RWD_8821C(x, v)                                        \
+	(BIT_CLEAR_WKFMCAM_RWD_8821C(x) | BIT_WKFMCAM_RWD_8821C(v))
+
+/* 2 REG_RXFLTMAP0_8821C (RX FILTER MAP GROUP 0) */
+#define BIT_MGTFLT15EN_8821C BIT(15)
+#define BIT_MGTFLT14EN_8821C BIT(14)
+#define BIT_MGTFLT13EN_8821C BIT(13)
+#define BIT_MGTFLT12EN_8821C BIT(12)
+#define BIT_MGTFLT11EN_8821C BIT(11)
+#define BIT_MGTFLT10EN_8821C BIT(10)
+#define BIT_MGTFLT9EN_8821C BIT(9)
+#define BIT_MGTFLT8EN_8821C BIT(8)
+#define BIT_MGTFLT7EN_8821C BIT(7)
+#define BIT_MGTFLT6EN_8821C BIT(6)
+#define BIT_MGTFLT5EN_8821C BIT(5)
+#define BIT_MGTFLT4EN_8821C BIT(4)
+#define BIT_MGTFLT3EN_8821C BIT(3)
+#define BIT_MGTFLT2EN_8821C BIT(2)
+#define BIT_MGTFLT1EN_8821C BIT(1)
+#define BIT_MGTFLT0EN_8821C BIT(0)
+
+/* 2 REG_RXFLTMAP1_8821C (RX FILTER MAP GROUP 1) */
+#define BIT_CTRLFLT15EN_8821C BIT(15)
+#define BIT_CTRLFLT14EN_8821C BIT(14)
+#define BIT_CTRLFLT13EN_8821C BIT(13)
+#define BIT_CTRLFLT12EN_8821C BIT(12)
+#define BIT_CTRLFLT11EN_8821C BIT(11)
+#define BIT_CTRLFLT10EN_8821C BIT(10)
+#define BIT_CTRLFLT9EN_8821C BIT(9)
+#define BIT_CTRLFLT8EN_8821C BIT(8)
+#define BIT_CTRLFLT7EN_8821C BIT(7)
+#define BIT_CTRLFLT6EN_8821C BIT(6)
+#define BIT_CTRLFLT5EN_8821C BIT(5)
+#define BIT_CTRLFLT4EN_8821C BIT(4)
+#define BIT_CTRLFLT3EN_8821C BIT(3)
+#define BIT_CTRLFLT2EN_8821C BIT(2)
+#define BIT_CTRLFLT1EN_8821C BIT(1)
+#define BIT_CTRLFLT0EN_8821C BIT(0)
+
+/* 2 REG_RXFLTMAP2_8821C (RX FILTER MAP GROUP 2) */
+#define BIT_DATAFLT15EN_8821C BIT(15)
+#define BIT_DATAFLT14EN_8821C BIT(14)
+#define BIT_DATAFLT13EN_8821C BIT(13)
+#define BIT_DATAFLT12EN_8821C BIT(12)
+#define BIT_DATAFLT11EN_8821C BIT(11)
+#define BIT_DATAFLT10EN_8821C BIT(10)
+#define BIT_DATAFLT9EN_8821C BIT(9)
+#define BIT_DATAFLT8EN_8821C BIT(8)
+#define BIT_DATAFLT7EN_8821C BIT(7)
+#define BIT_DATAFLT6EN_8821C BIT(6)
+#define BIT_DATAFLT5EN_8821C BIT(5)
+#define BIT_DATAFLT4EN_8821C BIT(4)
+#define BIT_DATAFLT3EN_8821C BIT(3)
+#define BIT_DATAFLT2EN_8821C BIT(2)
+#define BIT_DATAFLT1EN_8821C BIT(1)
+#define BIT_DATAFLT0EN_8821C BIT(0)
+
+/* 2 REG_RSVD_8821C */
+
+/* 2 REG_BCN_PSR_RPT_8821C (BEACON PARSER REPORT REGISTER) */
+
+#define BIT_SHIFT_DTIM_CNT_8821C 24
+#define BIT_MASK_DTIM_CNT_8821C 0xff
+#define BIT_DTIM_CNT_8821C(x)                                                  \
+	(((x) & BIT_MASK_DTIM_CNT_8821C) << BIT_SHIFT_DTIM_CNT_8821C)
+#define BITS_DTIM_CNT_8821C                                                    \
+	(BIT_MASK_DTIM_CNT_8821C << BIT_SHIFT_DTIM_CNT_8821C)
+#define BIT_CLEAR_DTIM_CNT_8821C(x) ((x) & (~BITS_DTIM_CNT_8821C))
+#define BIT_GET_DTIM_CNT_8821C(x)                                              \
+	(((x) >> BIT_SHIFT_DTIM_CNT_8821C) & BIT_MASK_DTIM_CNT_8821C)
+#define BIT_SET_DTIM_CNT_8821C(x, v)                                           \
+	(BIT_CLEAR_DTIM_CNT_8821C(x) | BIT_DTIM_CNT_8821C(v))
+
+#define BIT_SHIFT_DTIM_PERIOD_8821C 16
+#define BIT_MASK_DTIM_PERIOD_8821C 0xff
+#define BIT_DTIM_PERIOD_8821C(x)                                               \
+	(((x) & BIT_MASK_DTIM_PERIOD_8821C) << BIT_SHIFT_DTIM_PERIOD_8821C)
+#define BITS_DTIM_PERIOD_8821C                                                 \
+	(BIT_MASK_DTIM_PERIOD_8821C << BIT_SHIFT_DTIM_PERIOD_8821C)
+#define BIT_CLEAR_DTIM_PERIOD_8821C(x) ((x) & (~BITS_DTIM_PERIOD_8821C))
+#define BIT_GET_DTIM_PERIOD_8821C(x)                                           \
+	(((x) >> BIT_SHIFT_DTIM_PERIOD_8821C) & BIT_MASK_DTIM_PERIOD_8821C)
+#define BIT_SET_DTIM_PERIOD_8821C(x, v)                                        \
+	(BIT_CLEAR_DTIM_PERIOD_8821C(x) | BIT_DTIM_PERIOD_8821C(v))
+
+#define BIT_DTIM_8821C BIT(15)
+#define BIT_TIM_8821C BIT(14)
+#define BIT_RPT_VALID_8821C BIT(13)
+
+#define BIT_SHIFT_PS_AID_0_8821C 0
+#define BIT_MASK_PS_AID_0_8821C 0x7ff
+#define BIT_PS_AID_0_8821C(x)                                                  \
+	(((x) & BIT_MASK_PS_AID_0_8821C) << BIT_SHIFT_PS_AID_0_8821C)
+#define BITS_PS_AID_0_8821C                                                    \
+	(BIT_MASK_PS_AID_0_8821C << BIT_SHIFT_PS_AID_0_8821C)
+#define BIT_CLEAR_PS_AID_0_8821C(x) ((x) & (~BITS_PS_AID_0_8821C))
+#define BIT_GET_PS_AID_0_8821C(x)                                              \
+	(((x) >> BIT_SHIFT_PS_AID_0_8821C) & BIT_MASK_PS_AID_0_8821C)
+#define BIT_SET_PS_AID_0_8821C(x, v)                                           \
+	(BIT_CLEAR_PS_AID_0_8821C(x) | BIT_PS_AID_0_8821C(v))
+
+/* 2 REG_FLC_RPC_8821C (FW LPS CONDITION -- RX PKT COUNTER) */
+
+#define BIT_SHIFT_FLC_RPC_8821C 0
+#define BIT_MASK_FLC_RPC_8821C 0xff
+#define BIT_FLC_RPC_8821C(x)                                                   \
+	(((x) & BIT_MASK_FLC_RPC_8821C) << BIT_SHIFT_FLC_RPC_8821C)
+#define BITS_FLC_RPC_8821C (BIT_MASK_FLC_RPC_8821C << BIT_SHIFT_FLC_RPC_8821C)
+#define BIT_CLEAR_FLC_RPC_8821C(x) ((x) & (~BITS_FLC_RPC_8821C))
+#define BIT_GET_FLC_RPC_8821C(x)                                               \
+	(((x) >> BIT_SHIFT_FLC_RPC_8821C) & BIT_MASK_FLC_RPC_8821C)
+#define BIT_SET_FLC_RPC_8821C(x, v)                                            \
+	(BIT_CLEAR_FLC_RPC_8821C(x) | BIT_FLC_RPC_8821C(v))
+
+/* 2 REG_FLC_RPCT_8821C (FLC_RPC THRESHOLD) */
+
+#define BIT_SHIFT_FLC_RPCT_8821C 0
+#define BIT_MASK_FLC_RPCT_8821C 0xff
+#define BIT_FLC_RPCT_8821C(x)                                                  \
+	(((x) & BIT_MASK_FLC_RPCT_8821C) << BIT_SHIFT_FLC_RPCT_8821C)
+#define BITS_FLC_RPCT_8821C                                                    \
+	(BIT_MASK_FLC_RPCT_8821C << BIT_SHIFT_FLC_RPCT_8821C)
+#define BIT_CLEAR_FLC_RPCT_8821C(x) ((x) & (~BITS_FLC_RPCT_8821C))
+#define BIT_GET_FLC_RPCT_8821C(x)                                              \
+	(((x) >> BIT_SHIFT_FLC_RPCT_8821C) & BIT_MASK_FLC_RPCT_8821C)
+#define BIT_SET_FLC_RPCT_8821C(x, v)                                           \
+	(BIT_CLEAR_FLC_RPCT_8821C(x) | BIT_FLC_RPCT_8821C(v))
+
+/* 2 REG_FLC_PTS_8821C (PKT TYPE SELECTION OF FLC_RPC T) */
+#define BIT_CMF_8821C BIT(2)
+#define BIT_CCF_8821C BIT(1)
+#define BIT_CDF_8821C BIT(0)
+
+/* 2 REG_FLC_TRPC_8821C (TIMER OF FLC_RPC) */
+#define BIT_FLC_RPCT_V1_8821C BIT(7)
+#define BIT_MODE_8821C BIT(6)
+
+#define BIT_SHIFT_TRPCD_8821C 0
+#define BIT_MASK_TRPCD_8821C 0x3f
+#define BIT_TRPCD_8821C(x)                                                     \
+	(((x) & BIT_MASK_TRPCD_8821C) << BIT_SHIFT_TRPCD_8821C)
+#define BITS_TRPCD_8821C (BIT_MASK_TRPCD_8821C << BIT_SHIFT_TRPCD_8821C)
+#define BIT_CLEAR_TRPCD_8821C(x) ((x) & (~BITS_TRPCD_8821C))
+#define BIT_GET_TRPCD_8821C(x)                                                 \
+	(((x) >> BIT_SHIFT_TRPCD_8821C) & BIT_MASK_TRPCD_8821C)
+#define BIT_SET_TRPCD_8821C(x, v)                                              \
+	(BIT_CLEAR_TRPCD_8821C(x) | BIT_TRPCD_8821C(v))
+
+/* 2 REG_RXPKTMON_CTRL_8821C */
+
+#define BIT_SHIFT_RXBKQPKT_SEQ_8821C 20
+#define BIT_MASK_RXBKQPKT_SEQ_8821C 0xf
+#define BIT_RXBKQPKT_SEQ_8821C(x)                                              \
+	(((x) & BIT_MASK_RXBKQPKT_SEQ_8821C) << BIT_SHIFT_RXBKQPKT_SEQ_8821C)
+#define BITS_RXBKQPKT_SEQ_8821C                                                \
+	(BIT_MASK_RXBKQPKT_SEQ_8821C << BIT_SHIFT_RXBKQPKT_SEQ_8821C)
+#define BIT_CLEAR_RXBKQPKT_SEQ_8821C(x) ((x) & (~BITS_RXBKQPKT_SEQ_8821C))
+#define BIT_GET_RXBKQPKT_SEQ_8821C(x)                                          \
+	(((x) >> BIT_SHIFT_RXBKQPKT_SEQ_8821C) & BIT_MASK_RXBKQPKT_SEQ_8821C)
+#define BIT_SET_RXBKQPKT_SEQ_8821C(x, v)                                       \
+	(BIT_CLEAR_RXBKQPKT_SEQ_8821C(x) | BIT_RXBKQPKT_SEQ_8821C(v))
+
+#define BIT_SHIFT_RXBEQPKT_SEQ_8821C 16
+#define BIT_MASK_RXBEQPKT_SEQ_8821C 0xf
+#define BIT_RXBEQPKT_SEQ_8821C(x)                                              \
+	(((x) & BIT_MASK_RXBEQPKT_SEQ_8821C) << BIT_SHIFT_RXBEQPKT_SEQ_8821C)
+#define BITS_RXBEQPKT_SEQ_8821C                                                \
+	(BIT_MASK_RXBEQPKT_SEQ_8821C << BIT_SHIFT_RXBEQPKT_SEQ_8821C)
+#define BIT_CLEAR_RXBEQPKT_SEQ_8821C(x) ((x) & (~BITS_RXBEQPKT_SEQ_8821C))
+#define BIT_GET_RXBEQPKT_SEQ_8821C(x)                                          \
+	(((x) >> BIT_SHIFT_RXBEQPKT_SEQ_8821C) & BIT_MASK_RXBEQPKT_SEQ_8821C)
+#define BIT_SET_RXBEQPKT_SEQ_8821C(x, v)                                       \
+	(BIT_CLEAR_RXBEQPKT_SEQ_8821C(x) | BIT_RXBEQPKT_SEQ_8821C(v))
+
+#define BIT_SHIFT_RXVIQPKT_SEQ_8821C 12
+#define BIT_MASK_RXVIQPKT_SEQ_8821C 0xf
+#define BIT_RXVIQPKT_SEQ_8821C(x)                                              \
+	(((x) & BIT_MASK_RXVIQPKT_SEQ_8821C) << BIT_SHIFT_RXVIQPKT_SEQ_8821C)
+#define BITS_RXVIQPKT_SEQ_8821C                                                \
+	(BIT_MASK_RXVIQPKT_SEQ_8821C << BIT_SHIFT_RXVIQPKT_SEQ_8821C)
+#define BIT_CLEAR_RXVIQPKT_SEQ_8821C(x) ((x) & (~BITS_RXVIQPKT_SEQ_8821C))
+#define BIT_GET_RXVIQPKT_SEQ_8821C(x)                                          \
+	(((x) >> BIT_SHIFT_RXVIQPKT_SEQ_8821C) & BIT_MASK_RXVIQPKT_SEQ_8821C)
+#define BIT_SET_RXVIQPKT_SEQ_8821C(x, v)                                       \
+	(BIT_CLEAR_RXVIQPKT_SEQ_8821C(x) | BIT_RXVIQPKT_SEQ_8821C(v))
+
+#define BIT_SHIFT_RXVOQPKT_SEQ_8821C 8
+#define BIT_MASK_RXVOQPKT_SEQ_8821C 0xf
+#define BIT_RXVOQPKT_SEQ_8821C(x)                                              \
+	(((x) & BIT_MASK_RXVOQPKT_SEQ_8821C) << BIT_SHIFT_RXVOQPKT_SEQ_8821C)
+#define BITS_RXVOQPKT_SEQ_8821C                                                \
+	(BIT_MASK_RXVOQPKT_SEQ_8821C << BIT_SHIFT_RXVOQPKT_SEQ_8821C)
+#define BIT_CLEAR_RXVOQPKT_SEQ_8821C(x) ((x) & (~BITS_RXVOQPKT_SEQ_8821C))
+#define BIT_GET_RXVOQPKT_SEQ_8821C(x)                                          \
+	(((x) >> BIT_SHIFT_RXVOQPKT_SEQ_8821C) & BIT_MASK_RXVOQPKT_SEQ_8821C)
+#define BIT_SET_RXVOQPKT_SEQ_8821C(x, v)                                       \
+	(BIT_CLEAR_RXVOQPKT_SEQ_8821C(x) | BIT_RXVOQPKT_SEQ_8821C(v))
+
+#define BIT_RXBKQPKT_ERR_8821C BIT(7)
+#define BIT_RXBEQPKT_ERR_8821C BIT(6)
+#define BIT_RXVIQPKT_ERR_8821C BIT(5)
+#define BIT_RXVOQPKT_ERR_8821C BIT(4)
+#define BIT_RXDMA_MON_EN_8821C BIT(2)
+#define BIT_RXPKT_MON_RST_8821C BIT(1)
+#define BIT_RXPKT_MON_EN_8821C BIT(0)
+
+/* 2 REG_STATE_MON_8821C */
+
+#define BIT_SHIFT_STATE_SEL_8821C 24
+#define BIT_MASK_STATE_SEL_8821C 0x1f
+#define BIT_STATE_SEL_8821C(x)                                                 \
+	(((x) & BIT_MASK_STATE_SEL_8821C) << BIT_SHIFT_STATE_SEL_8821C)
+#define BITS_STATE_SEL_8821C                                                   \
+	(BIT_MASK_STATE_SEL_8821C << BIT_SHIFT_STATE_SEL_8821C)
+#define BIT_CLEAR_STATE_SEL_8821C(x) ((x) & (~BITS_STATE_SEL_8821C))
+#define BIT_GET_STATE_SEL_8821C(x)                                             \
+	(((x) >> BIT_SHIFT_STATE_SEL_8821C) & BIT_MASK_STATE_SEL_8821C)
+#define BIT_SET_STATE_SEL_8821C(x, v)                                          \
+	(BIT_CLEAR_STATE_SEL_8821C(x) | BIT_STATE_SEL_8821C(v))
+
+#define BIT_SHIFT_STATE_INFO_8821C 8
+#define BIT_MASK_STATE_INFO_8821C 0xff
+#define BIT_STATE_INFO_8821C(x)                                                \
+	(((x) & BIT_MASK_STATE_INFO_8821C) << BIT_SHIFT_STATE_INFO_8821C)
+#define BITS_STATE_INFO_8821C                                                  \
+	(BIT_MASK_STATE_INFO_8821C << BIT_SHIFT_STATE_INFO_8821C)
+#define BIT_CLEAR_STATE_INFO_8821C(x) ((x) & (~BITS_STATE_INFO_8821C))
+#define BIT_GET_STATE_INFO_8821C(x)                                            \
+	(((x) >> BIT_SHIFT_STATE_INFO_8821C) & BIT_MASK_STATE_INFO_8821C)
+#define BIT_SET_STATE_INFO_8821C(x, v)                                         \
+	(BIT_CLEAR_STATE_INFO_8821C(x) | BIT_STATE_INFO_8821C(v))
+
+#define BIT_UPD_NXT_STATE_8821C BIT(7)
+
+#define BIT_SHIFT_CUR_STATE_8821C 0
+#define BIT_MASK_CUR_STATE_8821C 0x7f
+#define BIT_CUR_STATE_8821C(x)                                                 \
+	(((x) & BIT_MASK_CUR_STATE_8821C) << BIT_SHIFT_CUR_STATE_8821C)
+#define BITS_CUR_STATE_8821C                                                   \
+	(BIT_MASK_CUR_STATE_8821C << BIT_SHIFT_CUR_STATE_8821C)
+#define BIT_CLEAR_CUR_STATE_8821C(x) ((x) & (~BITS_CUR_STATE_8821C))
+#define BIT_GET_CUR_STATE_8821C(x)                                             \
+	(((x) >> BIT_SHIFT_CUR_STATE_8821C) & BIT_MASK_CUR_STATE_8821C)
+#define BIT_SET_CUR_STATE_8821C(x, v)                                          \
+	(BIT_CLEAR_CUR_STATE_8821C(x) | BIT_CUR_STATE_8821C(v))
+
+/* 2 REG_ERROR_MON_8821C */
+#define BIT_MACRX_ERR_1_8821C BIT(17)
+#define BIT_MACRX_ERR_0_8821C BIT(16)
+#define BIT_MACTX_ERR_3_8821C BIT(3)
+#define BIT_MACTX_ERR_2_8821C BIT(2)
+#define BIT_MACTX_ERR_1_8821C BIT(1)
+#define BIT_MACTX_ERR_0_8821C BIT(0)
+
+/* 2 REG_SEARCH_MACID_8821C */
+#define BIT_EN_TXRPTBUF_CLK_8821C BIT(31)
+
+#define BIT_SHIFT_INFO_INDEX_OFFSET_8821C 16
+#define BIT_MASK_INFO_INDEX_OFFSET_8821C 0x1fff
+#define BIT_INFO_INDEX_OFFSET_8821C(x)                                         \
+	(((x) & BIT_MASK_INFO_INDEX_OFFSET_8821C)                              \
+	 << BIT_SHIFT_INFO_INDEX_OFFSET_8821C)
+#define BITS_INFO_INDEX_OFFSET_8821C                                           \
+	(BIT_MASK_INFO_INDEX_OFFSET_8821C << BIT_SHIFT_INFO_INDEX_OFFSET_8821C)
+#define BIT_CLEAR_INFO_INDEX_OFFSET_8821C(x)                                   \
+	((x) & (~BITS_INFO_INDEX_OFFSET_8821C))
+#define BIT_GET_INFO_INDEX_OFFSET_8821C(x)                                     \
+	(((x) >> BIT_SHIFT_INFO_INDEX_OFFSET_8821C) &                          \
+	 BIT_MASK_INFO_INDEX_OFFSET_8821C)
+#define BIT_SET_INFO_INDEX_OFFSET_8821C(x, v)                                  \
+	(BIT_CLEAR_INFO_INDEX_OFFSET_8821C(x) | BIT_INFO_INDEX_OFFSET_8821C(v))
+
+#define BIT_WMAC_SRCH_FIFOFULL_8821C BIT(15)
+#define BIT_DIS_INFOSRCH_8821C BIT(14)
+#define BIT_DISABLE_B0_8821C BIT(13)
+
+#define BIT_SHIFT_INFO_ADDR_OFFSET_8821C 0
+#define BIT_MASK_INFO_ADDR_OFFSET_8821C 0x1fff
+#define BIT_INFO_ADDR_OFFSET_8821C(x)                                          \
+	(((x) & BIT_MASK_INFO_ADDR_OFFSET_8821C)                               \
+	 << BIT_SHIFT_INFO_ADDR_OFFSET_8821C)
+#define BITS_INFO_ADDR_OFFSET_8821C                                            \
+	(BIT_MASK_INFO_ADDR_OFFSET_8821C << BIT_SHIFT_INFO_ADDR_OFFSET_8821C)
+#define BIT_CLEAR_INFO_ADDR_OFFSET_8821C(x)                                    \
+	((x) & (~BITS_INFO_ADDR_OFFSET_8821C))
+#define BIT_GET_INFO_ADDR_OFFSET_8821C(x)                                      \
+	(((x) >> BIT_SHIFT_INFO_ADDR_OFFSET_8821C) &                           \
+	 BIT_MASK_INFO_ADDR_OFFSET_8821C)
+#define BIT_SET_INFO_ADDR_OFFSET_8821C(x, v)                                   \
+	(BIT_CLEAR_INFO_ADDR_OFFSET_8821C(x) | BIT_INFO_ADDR_OFFSET_8821C(v))
+
+/* 2 REG_BT_COEX_TABLE_8821C (BT-COEXISTENCE CONTROL REGISTER) */
+
+#define BIT_SHIFT_COEX_TABLE_1_8821C 0
+#define BIT_MASK_COEX_TABLE_1_8821C 0xffffffffL
+#define BIT_COEX_TABLE_1_8821C(x)                                              \
+	(((x) & BIT_MASK_COEX_TABLE_1_8821C) << BIT_SHIFT_COEX_TABLE_1_8821C)
+#define BITS_COEX_TABLE_1_8821C                                                \
+	(BIT_MASK_COEX_TABLE_1_8821C << BIT_SHIFT_COEX_TABLE_1_8821C)
+#define BIT_CLEAR_COEX_TABLE_1_8821C(x) ((x) & (~BITS_COEX_TABLE_1_8821C))
+#define BIT_GET_COEX_TABLE_1_8821C(x)                                          \
+	(((x) >> BIT_SHIFT_COEX_TABLE_1_8821C) & BIT_MASK_COEX_TABLE_1_8821C)
+#define BIT_SET_COEX_TABLE_1_8821C(x, v)                                       \
+	(BIT_CLEAR_COEX_TABLE_1_8821C(x) | BIT_COEX_TABLE_1_8821C(v))
+
+/* 2 REG_BT_COEX_TABLE2_8821C (BT-COEXISTENCE CONTROL REGISTER) */
+
+#define BIT_SHIFT_COEX_TABLE_2_8821C 0
+#define BIT_MASK_COEX_TABLE_2_8821C 0xffffffffL
+#define BIT_COEX_TABLE_2_8821C(x)                                              \
+	(((x) & BIT_MASK_COEX_TABLE_2_8821C) << BIT_SHIFT_COEX_TABLE_2_8821C)
+#define BITS_COEX_TABLE_2_8821C                                                \
+	(BIT_MASK_COEX_TABLE_2_8821C << BIT_SHIFT_COEX_TABLE_2_8821C)
+#define BIT_CLEAR_COEX_TABLE_2_8821C(x) ((x) & (~BITS_COEX_TABLE_2_8821C))
+#define BIT_GET_COEX_TABLE_2_8821C(x)                                          \
+	(((x) >> BIT_SHIFT_COEX_TABLE_2_8821C) & BIT_MASK_COEX_TABLE_2_8821C)
+#define BIT_SET_COEX_TABLE_2_8821C(x, v)                                       \
+	(BIT_CLEAR_COEX_TABLE_2_8821C(x) | BIT_COEX_TABLE_2_8821C(v))
+
+/* 2 REG_BT_COEX_BREAK_TABLE_8821C (BT-COEXISTENCE CONTROL REGISTER) */
+
+#define BIT_SHIFT_BREAK_TABLE_2_8821C 16
+#define BIT_MASK_BREAK_TABLE_2_8821C 0xffff
+#define BIT_BREAK_TABLE_2_8821C(x)                                             \
+	(((x) & BIT_MASK_BREAK_TABLE_2_8821C) << BIT_SHIFT_BREAK_TABLE_2_8821C)
+#define BITS_BREAK_TABLE_2_8821C                                               \
+	(BIT_MASK_BREAK_TABLE_2_8821C << BIT_SHIFT_BREAK_TABLE_2_8821C)
+#define BIT_CLEAR_BREAK_TABLE_2_8821C(x) ((x) & (~BITS_BREAK_TABLE_2_8821C))
+#define BIT_GET_BREAK_TABLE_2_8821C(x)                                         \
+	(((x) >> BIT_SHIFT_BREAK_TABLE_2_8821C) & BIT_MASK_BREAK_TABLE_2_8821C)
+#define BIT_SET_BREAK_TABLE_2_8821C(x, v)                                      \
+	(BIT_CLEAR_BREAK_TABLE_2_8821C(x) | BIT_BREAK_TABLE_2_8821C(v))
+
+#define BIT_SHIFT_BREAK_TABLE_1_8821C 0
+#define BIT_MASK_BREAK_TABLE_1_8821C 0xffff
+#define BIT_BREAK_TABLE_1_8821C(x)                                             \
+	(((x) & BIT_MASK_BREAK_TABLE_1_8821C) << BIT_SHIFT_BREAK_TABLE_1_8821C)
+#define BITS_BREAK_TABLE_1_8821C                                               \
+	(BIT_MASK_BREAK_TABLE_1_8821C << BIT_SHIFT_BREAK_TABLE_1_8821C)
+#define BIT_CLEAR_BREAK_TABLE_1_8821C(x) ((x) & (~BITS_BREAK_TABLE_1_8821C))
+#define BIT_GET_BREAK_TABLE_1_8821C(x)                                         \
+	(((x) >> BIT_SHIFT_BREAK_TABLE_1_8821C) & BIT_MASK_BREAK_TABLE_1_8821C)
+#define BIT_SET_BREAK_TABLE_1_8821C(x, v)                                      \
+	(BIT_CLEAR_BREAK_TABLE_1_8821C(x) | BIT_BREAK_TABLE_1_8821C(v))
+
+/* 2 REG_BT_COEX_TABLE_H_8821C (BT-COEXISTENCE CONTROL REGISTER) */
+#define BIT_PRI_MASK_RX_RESP_V1_8821C BIT(30)
+#define BIT_PRI_MASK_RXOFDM_V1_8821C BIT(29)
+#define BIT_PRI_MASK_RXCCK_V1_8821C BIT(28)
+
+#define BIT_SHIFT_PRI_MASK_TXAC_8821C 21
+#define BIT_MASK_PRI_MASK_TXAC_8821C 0x7f
+#define BIT_PRI_MASK_TXAC_8821C(x)                                             \
+	(((x) & BIT_MASK_PRI_MASK_TXAC_8821C) << BIT_SHIFT_PRI_MASK_TXAC_8821C)
+#define BITS_PRI_MASK_TXAC_8821C                                               \
+	(BIT_MASK_PRI_MASK_TXAC_8821C << BIT_SHIFT_PRI_MASK_TXAC_8821C)
+#define BIT_CLEAR_PRI_MASK_TXAC_8821C(x) ((x) & (~BITS_PRI_MASK_TXAC_8821C))
+#define BIT_GET_PRI_MASK_TXAC_8821C(x)                                         \
+	(((x) >> BIT_SHIFT_PRI_MASK_TXAC_8821C) & BIT_MASK_PRI_MASK_TXAC_8821C)
+#define BIT_SET_PRI_MASK_TXAC_8821C(x, v)                                      \
+	(BIT_CLEAR_PRI_MASK_TXAC_8821C(x) | BIT_PRI_MASK_TXAC_8821C(v))
+
+#define BIT_SHIFT_PRI_MASK_NAV_8821C 13
+#define BIT_MASK_PRI_MASK_NAV_8821C 0xff
+#define BIT_PRI_MASK_NAV_8821C(x)                                              \
+	(((x) & BIT_MASK_PRI_MASK_NAV_8821C) << BIT_SHIFT_PRI_MASK_NAV_8821C)
+#define BITS_PRI_MASK_NAV_8821C                                                \
+	(BIT_MASK_PRI_MASK_NAV_8821C << BIT_SHIFT_PRI_MASK_NAV_8821C)
+#define BIT_CLEAR_PRI_MASK_NAV_8821C(x) ((x) & (~BITS_PRI_MASK_NAV_8821C))
+#define BIT_GET_PRI_MASK_NAV_8821C(x)                                          \
+	(((x) >> BIT_SHIFT_PRI_MASK_NAV_8821C) & BIT_MASK_PRI_MASK_NAV_8821C)
+#define BIT_SET_PRI_MASK_NAV_8821C(x, v)                                       \
+	(BIT_CLEAR_PRI_MASK_NAV_8821C(x) | BIT_PRI_MASK_NAV_8821C(v))
+
+#define BIT_PRI_MASK_CCK_V1_8821C BIT(12)
+#define BIT_PRI_MASK_OFDM_V1_8821C BIT(11)
+#define BIT_PRI_MASK_RTY_V1_8821C BIT(10)
+
+#define BIT_SHIFT_PRI_MASK_NUM_8821C 6
+#define BIT_MASK_PRI_MASK_NUM_8821C 0xf
+#define BIT_PRI_MASK_NUM_8821C(x)                                              \
+	(((x) & BIT_MASK_PRI_MASK_NUM_8821C) << BIT_SHIFT_PRI_MASK_NUM_8821C)
+#define BITS_PRI_MASK_NUM_8821C                                                \
+	(BIT_MASK_PRI_MASK_NUM_8821C << BIT_SHIFT_PRI_MASK_NUM_8821C)
+#define BIT_CLEAR_PRI_MASK_NUM_8821C(x) ((x) & (~BITS_PRI_MASK_NUM_8821C))
+#define BIT_GET_PRI_MASK_NUM_8821C(x)                                          \
+	(((x) >> BIT_SHIFT_PRI_MASK_NUM_8821C) & BIT_MASK_PRI_MASK_NUM_8821C)
+#define BIT_SET_PRI_MASK_NUM_8821C(x, v)                                       \
+	(BIT_CLEAR_PRI_MASK_NUM_8821C(x) | BIT_PRI_MASK_NUM_8821C(v))
+
+#define BIT_SHIFT_PRI_MASK_TYPE_8821C 2
+#define BIT_MASK_PRI_MASK_TYPE_8821C 0xf
+#define BIT_PRI_MASK_TYPE_8821C(x)                                             \
+	(((x) & BIT_MASK_PRI_MASK_TYPE_8821C) << BIT_SHIFT_PRI_MASK_TYPE_8821C)
+#define BITS_PRI_MASK_TYPE_8821C                                               \
+	(BIT_MASK_PRI_MASK_TYPE_8821C << BIT_SHIFT_PRI_MASK_TYPE_8821C)
+#define BIT_CLEAR_PRI_MASK_TYPE_8821C(x) ((x) & (~BITS_PRI_MASK_TYPE_8821C))
+#define BIT_GET_PRI_MASK_TYPE_8821C(x)                                         \
+	(((x) >> BIT_SHIFT_PRI_MASK_TYPE_8821C) & BIT_MASK_PRI_MASK_TYPE_8821C)
+#define BIT_SET_PRI_MASK_TYPE_8821C(x, v)                                      \
+	(BIT_CLEAR_PRI_MASK_TYPE_8821C(x) | BIT_PRI_MASK_TYPE_8821C(v))
+
+#define BIT_OOB_V1_8821C BIT(1)
+#define BIT_ANT_SEL_V1_8821C BIT(0)
+
+/* 2 REG_RXCMD_0_8821C */
+#define BIT_RXCMD_EN_8821C BIT(31)
+
+#define BIT_SHIFT_RXCMD_INFO_8821C 0
+#define BIT_MASK_RXCMD_INFO_8821C 0x7fffffffL
+#define BIT_RXCMD_INFO_8821C(x)                                                \
+	(((x) & BIT_MASK_RXCMD_INFO_8821C) << BIT_SHIFT_RXCMD_INFO_8821C)
+#define BITS_RXCMD_INFO_8821C                                                  \
+	(BIT_MASK_RXCMD_INFO_8821C << BIT_SHIFT_RXCMD_INFO_8821C)
+#define BIT_CLEAR_RXCMD_INFO_8821C(x) ((x) & (~BITS_RXCMD_INFO_8821C))
+#define BIT_GET_RXCMD_INFO_8821C(x)                                            \
+	(((x) >> BIT_SHIFT_RXCMD_INFO_8821C) & BIT_MASK_RXCMD_INFO_8821C)
+#define BIT_SET_RXCMD_INFO_8821C(x, v)                                         \
+	(BIT_CLEAR_RXCMD_INFO_8821C(x) | BIT_RXCMD_INFO_8821C(v))
+
+/* 2 REG_RXCMD_1_8821C */
+
+#define BIT_SHIFT_CSI_RADDR_LATCH_8821C 24
+#define BIT_MASK_CSI_RADDR_LATCH_8821C 0xff
+#define BIT_CSI_RADDR_LATCH_8821C(x)                                           \
+	(((x) & BIT_MASK_CSI_RADDR_LATCH_8821C)                                \
+	 << BIT_SHIFT_CSI_RADDR_LATCH_8821C)
+#define BITS_CSI_RADDR_LATCH_8821C                                             \
+	(BIT_MASK_CSI_RADDR_LATCH_8821C << BIT_SHIFT_CSI_RADDR_LATCH_8821C)
+#define BIT_CLEAR_CSI_RADDR_LATCH_8821C(x) ((x) & (~BITS_CSI_RADDR_LATCH_8821C))
+#define BIT_GET_CSI_RADDR_LATCH_8821C(x)                                       \
+	(((x) >> BIT_SHIFT_CSI_RADDR_LATCH_8821C) &                            \
+	 BIT_MASK_CSI_RADDR_LATCH_8821C)
+#define BIT_SET_CSI_RADDR_LATCH_8821C(x, v)                                    \
+	(BIT_CLEAR_CSI_RADDR_LATCH_8821C(x) | BIT_CSI_RADDR_LATCH_8821C(v))
+
+#define BIT_SHIFT_CSI_WADDR_LATCH_8821C 16
+#define BIT_MASK_CSI_WADDR_LATCH_8821C 0xff
+#define BIT_CSI_WADDR_LATCH_8821C(x)                                           \
+	(((x) & BIT_MASK_CSI_WADDR_LATCH_8821C)                                \
+	 << BIT_SHIFT_CSI_WADDR_LATCH_8821C)
+#define BITS_CSI_WADDR_LATCH_8821C                                             \
+	(BIT_MASK_CSI_WADDR_LATCH_8821C << BIT_SHIFT_CSI_WADDR_LATCH_8821C)
+#define BIT_CLEAR_CSI_WADDR_LATCH_8821C(x) ((x) & (~BITS_CSI_WADDR_LATCH_8821C))
+#define BIT_GET_CSI_WADDR_LATCH_8821C(x)                                       \
+	(((x) >> BIT_SHIFT_CSI_WADDR_LATCH_8821C) &                            \
+	 BIT_MASK_CSI_WADDR_LATCH_8821C)
+#define BIT_SET_CSI_WADDR_LATCH_8821C(x, v)                                    \
+	(BIT_CLEAR_CSI_WADDR_LATCH_8821C(x) | BIT_CSI_WADDR_LATCH_8821C(v))
+
+#define BIT_SHIFT_RXCMD_PRD_8821C 0
+#define BIT_MASK_RXCMD_PRD_8821C 0xffff
+#define BIT_RXCMD_PRD_8821C(x)                                                 \
+	(((x) & BIT_MASK_RXCMD_PRD_8821C) << BIT_SHIFT_RXCMD_PRD_8821C)
+#define BITS_RXCMD_PRD_8821C                                                   \
+	(BIT_MASK_RXCMD_PRD_8821C << BIT_SHIFT_RXCMD_PRD_8821C)
+#define BIT_CLEAR_RXCMD_PRD_8821C(x) ((x) & (~BITS_RXCMD_PRD_8821C))
+#define BIT_GET_RXCMD_PRD_8821C(x)                                             \
+	(((x) >> BIT_SHIFT_RXCMD_PRD_8821C) & BIT_MASK_RXCMD_PRD_8821C)
+#define BIT_SET_RXCMD_PRD_8821C(x, v)                                          \
+	(BIT_CLEAR_RXCMD_PRD_8821C(x) | BIT_RXCMD_PRD_8821C(v))
+
+/* 2 REG_WMAC_RESP_TXINFO_8821C (RESPONSE TXINFO REGISTER) */
+
+#define BIT_SHIFT_WMAC_RESP_MFB_8821C 25
+#define BIT_MASK_WMAC_RESP_MFB_8821C 0x7f
+#define BIT_WMAC_RESP_MFB_8821C(x)                                             \
+	(((x) & BIT_MASK_WMAC_RESP_MFB_8821C) << BIT_SHIFT_WMAC_RESP_MFB_8821C)
+#define BITS_WMAC_RESP_MFB_8821C                                               \
+	(BIT_MASK_WMAC_RESP_MFB_8821C << BIT_SHIFT_WMAC_RESP_MFB_8821C)
+#define BIT_CLEAR_WMAC_RESP_MFB_8821C(x) ((x) & (~BITS_WMAC_RESP_MFB_8821C))
+#define BIT_GET_WMAC_RESP_MFB_8821C(x)                                         \
+	(((x) >> BIT_SHIFT_WMAC_RESP_MFB_8821C) & BIT_MASK_WMAC_RESP_MFB_8821C)
+#define BIT_SET_WMAC_RESP_MFB_8821C(x, v)                                      \
+	(BIT_CLEAR_WMAC_RESP_MFB_8821C(x) | BIT_WMAC_RESP_MFB_8821C(v))
+
+#define BIT_SHIFT_WMAC_ANTINF_SEL_8821C 23
+#define BIT_MASK_WMAC_ANTINF_SEL_8821C 0x3
+#define BIT_WMAC_ANTINF_SEL_8821C(x)                                           \
+	(((x) & BIT_MASK_WMAC_ANTINF_SEL_8821C)                                \
+	 << BIT_SHIFT_WMAC_ANTINF_SEL_8821C)
+#define BITS_WMAC_ANTINF_SEL_8821C                                             \
+	(BIT_MASK_WMAC_ANTINF_SEL_8821C << BIT_SHIFT_WMAC_ANTINF_SEL_8821C)
+#define BIT_CLEAR_WMAC_ANTINF_SEL_8821C(x) ((x) & (~BITS_WMAC_ANTINF_SEL_8821C))
+#define BIT_GET_WMAC_ANTINF_SEL_8821C(x)                                       \
+	(((x) >> BIT_SHIFT_WMAC_ANTINF_SEL_8821C) &                            \
+	 BIT_MASK_WMAC_ANTINF_SEL_8821C)
+#define BIT_SET_WMAC_ANTINF_SEL_8821C(x, v)                                    \
+	(BIT_CLEAR_WMAC_ANTINF_SEL_8821C(x) | BIT_WMAC_ANTINF_SEL_8821C(v))
+
+#define BIT_SHIFT_WMAC_ANTSEL_SEL_8821C 21
+#define BIT_MASK_WMAC_ANTSEL_SEL_8821C 0x3
+#define BIT_WMAC_ANTSEL_SEL_8821C(x)                                           \
+	(((x) & BIT_MASK_WMAC_ANTSEL_SEL_8821C)                                \
+	 << BIT_SHIFT_WMAC_ANTSEL_SEL_8821C)
+#define BITS_WMAC_ANTSEL_SEL_8821C                                             \
+	(BIT_MASK_WMAC_ANTSEL_SEL_8821C << BIT_SHIFT_WMAC_ANTSEL_SEL_8821C)
+#define BIT_CLEAR_WMAC_ANTSEL_SEL_8821C(x) ((x) & (~BITS_WMAC_ANTSEL_SEL_8821C))
+#define BIT_GET_WMAC_ANTSEL_SEL_8821C(x)                                       \
+	(((x) >> BIT_SHIFT_WMAC_ANTSEL_SEL_8821C) &                            \
+	 BIT_MASK_WMAC_ANTSEL_SEL_8821C)
+#define BIT_SET_WMAC_ANTSEL_SEL_8821C(x, v)                                    \
+	(BIT_CLEAR_WMAC_ANTSEL_SEL_8821C(x) | BIT_WMAC_ANTSEL_SEL_8821C(v))
+
+#define BIT_SHIFT_R_WMAC_RESP_TXPOWER_8821C 18
+#define BIT_MASK_R_WMAC_RESP_TXPOWER_8821C 0x7
+#define BIT_R_WMAC_RESP_TXPOWER_8821C(x)                                       \
+	(((x) & BIT_MASK_R_WMAC_RESP_TXPOWER_8821C)                            \
+	 << BIT_SHIFT_R_WMAC_RESP_TXPOWER_8821C)
+#define BITS_R_WMAC_RESP_TXPOWER_8821C                                         \
+	(BIT_MASK_R_WMAC_RESP_TXPOWER_8821C                                    \
+	 << BIT_SHIFT_R_WMAC_RESP_TXPOWER_8821C)
+#define BIT_CLEAR_R_WMAC_RESP_TXPOWER_8821C(x)                                 \
+	((x) & (~BITS_R_WMAC_RESP_TXPOWER_8821C))
+#define BIT_GET_R_WMAC_RESP_TXPOWER_8821C(x)                                   \
+	(((x) >> BIT_SHIFT_R_WMAC_RESP_TXPOWER_8821C) &                        \
+	 BIT_MASK_R_WMAC_RESP_TXPOWER_8821C)
+#define BIT_SET_R_WMAC_RESP_TXPOWER_8821C(x, v)                                \
+	(BIT_CLEAR_R_WMAC_RESP_TXPOWER_8821C(x) |                              \
+	 BIT_R_WMAC_RESP_TXPOWER_8821C(v))
+
+#define BIT_SHIFT_WMAC_RESP_TXANT_8821C 0
+#define BIT_MASK_WMAC_RESP_TXANT_8821C 0x3ffff
+#define BIT_WMAC_RESP_TXANT_8821C(x)                                           \
+	(((x) & BIT_MASK_WMAC_RESP_TXANT_8821C)                                \
+	 << BIT_SHIFT_WMAC_RESP_TXANT_8821C)
+#define BITS_WMAC_RESP_TXANT_8821C                                             \
+	(BIT_MASK_WMAC_RESP_TXANT_8821C << BIT_SHIFT_WMAC_RESP_TXANT_8821C)
+#define BIT_CLEAR_WMAC_RESP_TXANT_8821C(x) ((x) & (~BITS_WMAC_RESP_TXANT_8821C))
+#define BIT_GET_WMAC_RESP_TXANT_8821C(x)                                       \
+	(((x) >> BIT_SHIFT_WMAC_RESP_TXANT_8821C) &                            \
+	 BIT_MASK_WMAC_RESP_TXANT_8821C)
+#define BIT_SET_WMAC_RESP_TXANT_8821C(x, v)                                    \
+	(BIT_CLEAR_WMAC_RESP_TXANT_8821C(x) | BIT_WMAC_RESP_TXANT_8821C(v))
+
+/* 2 REG_BBPSF_CTRL_8821C */
+#define BIT_CTL_IDLE_CLR_CSI_RPT_8821C BIT(31)
+#define BIT_WMAC_USE_NDPARATE_8821C BIT(30)
+
+#define BIT_SHIFT_WMAC_CSI_RATE_8821C 24
+#define BIT_MASK_WMAC_CSI_RATE_8821C 0x3f
+#define BIT_WMAC_CSI_RATE_8821C(x)                                             \
+	(((x) & BIT_MASK_WMAC_CSI_RATE_8821C) << BIT_SHIFT_WMAC_CSI_RATE_8821C)
+#define BITS_WMAC_CSI_RATE_8821C                                               \
+	(BIT_MASK_WMAC_CSI_RATE_8821C << BIT_SHIFT_WMAC_CSI_RATE_8821C)
+#define BIT_CLEAR_WMAC_CSI_RATE_8821C(x) ((x) & (~BITS_WMAC_CSI_RATE_8821C))
+#define BIT_GET_WMAC_CSI_RATE_8821C(x)                                         \
+	(((x) >> BIT_SHIFT_WMAC_CSI_RATE_8821C) & BIT_MASK_WMAC_CSI_RATE_8821C)
+#define BIT_SET_WMAC_CSI_RATE_8821C(x, v)                                      \
+	(BIT_CLEAR_WMAC_CSI_RATE_8821C(x) | BIT_WMAC_CSI_RATE_8821C(v))
+
+#define BIT_SHIFT_WMAC_RESP_TXRATE_8821C 16
+#define BIT_MASK_WMAC_RESP_TXRATE_8821C 0xff
+#define BIT_WMAC_RESP_TXRATE_8821C(x)                                          \
+	(((x) & BIT_MASK_WMAC_RESP_TXRATE_8821C)                               \
+	 << BIT_SHIFT_WMAC_RESP_TXRATE_8821C)
+#define BITS_WMAC_RESP_TXRATE_8821C                                            \
+	(BIT_MASK_WMAC_RESP_TXRATE_8821C << BIT_SHIFT_WMAC_RESP_TXRATE_8821C)
+#define BIT_CLEAR_WMAC_RESP_TXRATE_8821C(x)                                    \
+	((x) & (~BITS_WMAC_RESP_TXRATE_8821C))
+#define BIT_GET_WMAC_RESP_TXRATE_8821C(x)                                      \
+	(((x) >> BIT_SHIFT_WMAC_RESP_TXRATE_8821C) &                           \
+	 BIT_MASK_WMAC_RESP_TXRATE_8821C)
+#define BIT_SET_WMAC_RESP_TXRATE_8821C(x, v)                                   \
+	(BIT_CLEAR_WMAC_RESP_TXRATE_8821C(x) | BIT_WMAC_RESP_TXRATE_8821C(v))
+
+#define BIT_CSI_FORCE_RATE_EN_8821C BIT(15)
+
+#define BIT_SHIFT_CSI_RSC_8821C 13
+#define BIT_MASK_CSI_RSC_8821C 0x3
+#define BIT_CSI_RSC_8821C(x)                                                   \
+	(((x) & BIT_MASK_CSI_RSC_8821C) << BIT_SHIFT_CSI_RSC_8821C)
+#define BITS_CSI_RSC_8821C (BIT_MASK_CSI_RSC_8821C << BIT_SHIFT_CSI_RSC_8821C)
+#define BIT_CLEAR_CSI_RSC_8821C(x) ((x) & (~BITS_CSI_RSC_8821C))
+#define BIT_GET_CSI_RSC_8821C(x)                                               \
+	(((x) >> BIT_SHIFT_CSI_RSC_8821C) & BIT_MASK_CSI_RSC_8821C)
+#define BIT_SET_CSI_RSC_8821C(x, v)                                            \
+	(BIT_CLEAR_CSI_RSC_8821C(x) | BIT_CSI_RSC_8821C(v))
+
+#define BIT_CSI_GID_SEL_8821C BIT(12)
+#define BIT_RDCSIMD_FLAG_TRIG_SEL_8821C BIT(11)
+#define BIT_NDPVLD_POS_RST_FFPTR_DIS_V1_8821C BIT(10)
+#define BIT_NDPVLD_PROTECT_RDRDY_DIS_8821C BIT(9)
+#define BIT_RDCSI_EMPTY_APPZERO_8821C BIT(8)
+#define BIT_BBPSF_MPDUCHKEN_8821C BIT(5)
+#define BIT_BBPSF_MHCHKEN_8821C BIT(4)
+#define BIT_BBPSF_ERRCHKEN_8821C BIT(3)
+
+#define BIT_SHIFT_BBPSF_ERRTHR_8821C 0
+#define BIT_MASK_BBPSF_ERRTHR_8821C 0x7
+#define BIT_BBPSF_ERRTHR_8821C(x)                                              \
+	(((x) & BIT_MASK_BBPSF_ERRTHR_8821C) << BIT_SHIFT_BBPSF_ERRTHR_8821C)
+#define BITS_BBPSF_ERRTHR_8821C                                                \
+	(BIT_MASK_BBPSF_ERRTHR_8821C << BIT_SHIFT_BBPSF_ERRTHR_8821C)
+#define BIT_CLEAR_BBPSF_ERRTHR_8821C(x) ((x) & (~BITS_BBPSF_ERRTHR_8821C))
+#define BIT_GET_BBPSF_ERRTHR_8821C(x)                                          \
+	(((x) >> BIT_SHIFT_BBPSF_ERRTHR_8821C) & BIT_MASK_BBPSF_ERRTHR_8821C)
+#define BIT_SET_BBPSF_ERRTHR_8821C(x, v)                                       \
+	(BIT_CLEAR_BBPSF_ERRTHR_8821C(x) | BIT_BBPSF_ERRTHR_8821C(v))
+
+/* 2 REG_P2P_RX_BCN_NOA_8821C (P2P RX BEACON NOA REGISTER) */
+#define BIT_NOA_PARSER_EN_8821C BIT(15)
+#define BIT_BSSID_SEL_8821C BIT(14)
+
+#define BIT_SHIFT_P2P_OUI_TYPE_8821C 0
+#define BIT_MASK_P2P_OUI_TYPE_8821C 0xff
+#define BIT_P2P_OUI_TYPE_8821C(x)                                              \
+	(((x) & BIT_MASK_P2P_OUI_TYPE_8821C) << BIT_SHIFT_P2P_OUI_TYPE_8821C)
+#define BITS_P2P_OUI_TYPE_8821C                                                \
+	(BIT_MASK_P2P_OUI_TYPE_8821C << BIT_SHIFT_P2P_OUI_TYPE_8821C)
+#define BIT_CLEAR_P2P_OUI_TYPE_8821C(x) ((x) & (~BITS_P2P_OUI_TYPE_8821C))
+#define BIT_GET_P2P_OUI_TYPE_8821C(x)                                          \
+	(((x) >> BIT_SHIFT_P2P_OUI_TYPE_8821C) & BIT_MASK_P2P_OUI_TYPE_8821C)
+#define BIT_SET_P2P_OUI_TYPE_8821C(x, v)                                       \
+	(BIT_CLEAR_P2P_OUI_TYPE_8821C(x) | BIT_P2P_OUI_TYPE_8821C(v))
+
+/* 2 REG_RSVD_8821C */
+
+/* 2 REG_ASSOCIATED_BFMER0_INFO_8821C (ASSOCIATED BEAMFORMER0 INFO REGISTER) */
+
+#define BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0_V1_8821C 0
+#define BIT_MASK_R_WMAC_SOUNDING_RXADD_R0_V1_8821C 0xffffffffL
+#define BIT_R_WMAC_SOUNDING_RXADD_R0_V1_8821C(x)                               \
+	(((x) & BIT_MASK_R_WMAC_SOUNDING_RXADD_R0_V1_8821C)                    \
+	 << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0_V1_8821C)
+#define BITS_R_WMAC_SOUNDING_RXADD_R0_V1_8821C                                 \
+	(BIT_MASK_R_WMAC_SOUNDING_RXADD_R0_V1_8821C                            \
+	 << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0_V1_8821C)
+#define BIT_CLEAR_R_WMAC_SOUNDING_RXADD_R0_V1_8821C(x)                         \
+	((x) & (~BITS_R_WMAC_SOUNDING_RXADD_R0_V1_8821C))
+#define BIT_GET_R_WMAC_SOUNDING_RXADD_R0_V1_8821C(x)                           \
+	(((x) >> BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0_V1_8821C) &                \
+	 BIT_MASK_R_WMAC_SOUNDING_RXADD_R0_V1_8821C)
+#define BIT_SET_R_WMAC_SOUNDING_RXADD_R0_V1_8821C(x, v)                        \
+	(BIT_CLEAR_R_WMAC_SOUNDING_RXADD_R0_V1_8821C(x) |                      \
+	 BIT_R_WMAC_SOUNDING_RXADD_R0_V1_8821C(v))
+
+/* 2 REG_ASSOCIATED_BFMER0_INFO_H_8821C */
+
+#define BIT_SHIFT_R_WMAC_TXCSI_AID0_8821C 16
+#define BIT_MASK_R_WMAC_TXCSI_AID0_8821C 0x1ff
+#define BIT_R_WMAC_TXCSI_AID0_8821C(x)                                         \
+	(((x) & BIT_MASK_R_WMAC_TXCSI_AID0_8821C)                              \
+	 << BIT_SHIFT_R_WMAC_TXCSI_AID0_8821C)
+#define BITS_R_WMAC_TXCSI_AID0_8821C                                           \
+	(BIT_MASK_R_WMAC_TXCSI_AID0_8821C << BIT_SHIFT_R_WMAC_TXCSI_AID0_8821C)
+#define BIT_CLEAR_R_WMAC_TXCSI_AID0_8821C(x)                                   \
+	((x) & (~BITS_R_WMAC_TXCSI_AID0_8821C))
+#define BIT_GET_R_WMAC_TXCSI_AID0_8821C(x)                                     \
+	(((x) >> BIT_SHIFT_R_WMAC_TXCSI_AID0_8821C) &                          \
+	 BIT_MASK_R_WMAC_TXCSI_AID0_8821C)
+#define BIT_SET_R_WMAC_TXCSI_AID0_8821C(x, v)                                  \
+	(BIT_CLEAR_R_WMAC_TXCSI_AID0_8821C(x) | BIT_R_WMAC_TXCSI_AID0_8821C(v))
+
+#define BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0_H_V1_8821C 0
+#define BIT_MASK_R_WMAC_SOUNDING_RXADD_R0_H_V1_8821C 0xffff
+#define BIT_R_WMAC_SOUNDING_RXADD_R0_H_V1_8821C(x)                             \
+	(((x) & BIT_MASK_R_WMAC_SOUNDING_RXADD_R0_H_V1_8821C)                  \
+	 << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0_H_V1_8821C)
+#define BITS_R_WMAC_SOUNDING_RXADD_R0_H_V1_8821C                               \
+	(BIT_MASK_R_WMAC_SOUNDING_RXADD_R0_H_V1_8821C                          \
+	 << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0_H_V1_8821C)
+#define BIT_CLEAR_R_WMAC_SOUNDING_RXADD_R0_H_V1_8821C(x)                       \
+	((x) & (~BITS_R_WMAC_SOUNDING_RXADD_R0_H_V1_8821C))
+#define BIT_GET_R_WMAC_SOUNDING_RXADD_R0_H_V1_8821C(x)                         \
+	(((x) >> BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0_H_V1_8821C) &              \
+	 BIT_MASK_R_WMAC_SOUNDING_RXADD_R0_H_V1_8821C)
+#define BIT_SET_R_WMAC_SOUNDING_RXADD_R0_H_V1_8821C(x, v)                      \
+	(BIT_CLEAR_R_WMAC_SOUNDING_RXADD_R0_H_V1_8821C(x) |                    \
+	 BIT_R_WMAC_SOUNDING_RXADD_R0_H_V1_8821C(v))
+
+/* 2 REG_ASSOCIATED_BFMER1_INFO_8821C (ASSOCIATED BEAMFORMER1 INFO REGISTER) */
+
+#define BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1_V1_8821C 0
+#define BIT_MASK_R_WMAC_SOUNDING_RXADD_R1_V1_8821C 0xffffffffL
+#define BIT_R_WMAC_SOUNDING_RXADD_R1_V1_8821C(x)                               \
+	(((x) & BIT_MASK_R_WMAC_SOUNDING_RXADD_R1_V1_8821C)                    \
+	 << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1_V1_8821C)
+#define BITS_R_WMAC_SOUNDING_RXADD_R1_V1_8821C                                 \
+	(BIT_MASK_R_WMAC_SOUNDING_RXADD_R1_V1_8821C                            \
+	 << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1_V1_8821C)
+#define BIT_CLEAR_R_WMAC_SOUNDING_RXADD_R1_V1_8821C(x)                         \
+	((x) & (~BITS_R_WMAC_SOUNDING_RXADD_R1_V1_8821C))
+#define BIT_GET_R_WMAC_SOUNDING_RXADD_R1_V1_8821C(x)                           \
+	(((x) >> BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1_V1_8821C) &                \
+	 BIT_MASK_R_WMAC_SOUNDING_RXADD_R1_V1_8821C)
+#define BIT_SET_R_WMAC_SOUNDING_RXADD_R1_V1_8821C(x, v)                        \
+	(BIT_CLEAR_R_WMAC_SOUNDING_RXADD_R1_V1_8821C(x) |                      \
+	 BIT_R_WMAC_SOUNDING_RXADD_R1_V1_8821C(v))
+
+/* 2 REG_ASSOCIATED_BFMER1_INFO_H_8821C */
+
+#define BIT_SHIFT_R_WMAC_TXCSI_AID1_8821C 16
+#define BIT_MASK_R_WMAC_TXCSI_AID1_8821C 0x1ff
+#define BIT_R_WMAC_TXCSI_AID1_8821C(x)                                         \
+	(((x) & BIT_MASK_R_WMAC_TXCSI_AID1_8821C)                              \
+	 << BIT_SHIFT_R_WMAC_TXCSI_AID1_8821C)
+#define BITS_R_WMAC_TXCSI_AID1_8821C                                           \
+	(BIT_MASK_R_WMAC_TXCSI_AID1_8821C << BIT_SHIFT_R_WMAC_TXCSI_AID1_8821C)
+#define BIT_CLEAR_R_WMAC_TXCSI_AID1_8821C(x)                                   \
+	((x) & (~BITS_R_WMAC_TXCSI_AID1_8821C))
+#define BIT_GET_R_WMAC_TXCSI_AID1_8821C(x)                                     \
+	(((x) >> BIT_SHIFT_R_WMAC_TXCSI_AID1_8821C) &                          \
+	 BIT_MASK_R_WMAC_TXCSI_AID1_8821C)
+#define BIT_SET_R_WMAC_TXCSI_AID1_8821C(x, v)                                  \
+	(BIT_CLEAR_R_WMAC_TXCSI_AID1_8821C(x) | BIT_R_WMAC_TXCSI_AID1_8821C(v))
+
+#define BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1_H_V1_8821C 0
+#define BIT_MASK_R_WMAC_SOUNDING_RXADD_R1_H_V1_8821C 0xffff
+#define BIT_R_WMAC_SOUNDING_RXADD_R1_H_V1_8821C(x)                             \
+	(((x) & BIT_MASK_R_WMAC_SOUNDING_RXADD_R1_H_V1_8821C)                  \
+	 << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1_H_V1_8821C)
+#define BITS_R_WMAC_SOUNDING_RXADD_R1_H_V1_8821C                               \
+	(BIT_MASK_R_WMAC_SOUNDING_RXADD_R1_H_V1_8821C                          \
+	 << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1_H_V1_8821C)
+#define BIT_CLEAR_R_WMAC_SOUNDING_RXADD_R1_H_V1_8821C(x)                       \
+	((x) & (~BITS_R_WMAC_SOUNDING_RXADD_R1_H_V1_8821C))
+#define BIT_GET_R_WMAC_SOUNDING_RXADD_R1_H_V1_8821C(x)                         \
+	(((x) >> BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1_H_V1_8821C) &              \
+	 BIT_MASK_R_WMAC_SOUNDING_RXADD_R1_H_V1_8821C)
+#define BIT_SET_R_WMAC_SOUNDING_RXADD_R1_H_V1_8821C(x, v)                      \
+	(BIT_CLEAR_R_WMAC_SOUNDING_RXADD_R1_H_V1_8821C(x) |                    \
+	 BIT_R_WMAC_SOUNDING_RXADD_R1_H_V1_8821C(v))
+
+/* 2 REG_TX_CSI_RPT_PARAM_BW20_8821C (TX CSI REPORT PARAMETER REGISTER) */
+
+#define BIT_SHIFT_R_WMAC_BFINFO_20M_1_8821C 16
+#define BIT_MASK_R_WMAC_BFINFO_20M_1_8821C 0xfff
+#define BIT_R_WMAC_BFINFO_20M_1_8821C(x)                                       \
+	(((x) & BIT_MASK_R_WMAC_BFINFO_20M_1_8821C)                            \
+	 << BIT_SHIFT_R_WMAC_BFINFO_20M_1_8821C)
+#define BITS_R_WMAC_BFINFO_20M_1_8821C                                         \
+	(BIT_MASK_R_WMAC_BFINFO_20M_1_8821C                                    \
+	 << BIT_SHIFT_R_WMAC_BFINFO_20M_1_8821C)
+#define BIT_CLEAR_R_WMAC_BFINFO_20M_1_8821C(x)                                 \
+	((x) & (~BITS_R_WMAC_BFINFO_20M_1_8821C))
+#define BIT_GET_R_WMAC_BFINFO_20M_1_8821C(x)                                   \
+	(((x) >> BIT_SHIFT_R_WMAC_BFINFO_20M_1_8821C) &                        \
+	 BIT_MASK_R_WMAC_BFINFO_20M_1_8821C)
+#define BIT_SET_R_WMAC_BFINFO_20M_1_8821C(x, v)                                \
+	(BIT_CLEAR_R_WMAC_BFINFO_20M_1_8821C(x) |                              \
+	 BIT_R_WMAC_BFINFO_20M_1_8821C(v))
+
+#define BIT_SHIFT_R_WMAC_BFINFO_20M_0_8821C 0
+#define BIT_MASK_R_WMAC_BFINFO_20M_0_8821C 0xfff
+#define BIT_R_WMAC_BFINFO_20M_0_8821C(x)                                       \
+	(((x) & BIT_MASK_R_WMAC_BFINFO_20M_0_8821C)                            \
+	 << BIT_SHIFT_R_WMAC_BFINFO_20M_0_8821C)
+#define BITS_R_WMAC_BFINFO_20M_0_8821C                                         \
+	(BIT_MASK_R_WMAC_BFINFO_20M_0_8821C                                    \
+	 << BIT_SHIFT_R_WMAC_BFINFO_20M_0_8821C)
+#define BIT_CLEAR_R_WMAC_BFINFO_20M_0_8821C(x)                                 \
+	((x) & (~BITS_R_WMAC_BFINFO_20M_0_8821C))
+#define BIT_GET_R_WMAC_BFINFO_20M_0_8821C(x)                                   \
+	(((x) >> BIT_SHIFT_R_WMAC_BFINFO_20M_0_8821C) &                        \
+	 BIT_MASK_R_WMAC_BFINFO_20M_0_8821C)
+#define BIT_SET_R_WMAC_BFINFO_20M_0_8821C(x, v)                                \
+	(BIT_CLEAR_R_WMAC_BFINFO_20M_0_8821C(x) |                              \
+	 BIT_R_WMAC_BFINFO_20M_0_8821C(v))
+
+/* 2 REG_TX_CSI_RPT_PARAM_BW40_8821C (TX CSI REPORT PARAMETER_BW40 REGISTER) */
+
+#define BIT_SHIFT_WMAC_RESP_ANTCD_8821C 0
+#define BIT_MASK_WMAC_RESP_ANTCD_8821C 0xf
+#define BIT_WMAC_RESP_ANTCD_8821C(x)                                           \
+	(((x) & BIT_MASK_WMAC_RESP_ANTCD_8821C)                                \
+	 << BIT_SHIFT_WMAC_RESP_ANTCD_8821C)
+#define BITS_WMAC_RESP_ANTCD_8821C                                             \
+	(BIT_MASK_WMAC_RESP_ANTCD_8821C << BIT_SHIFT_WMAC_RESP_ANTCD_8821C)
+#define BIT_CLEAR_WMAC_RESP_ANTCD_8821C(x) ((x) & (~BITS_WMAC_RESP_ANTCD_8821C))
+#define BIT_GET_WMAC_RESP_ANTCD_8821C(x)                                       \
+	(((x) >> BIT_SHIFT_WMAC_RESP_ANTCD_8821C) &                            \
+	 BIT_MASK_WMAC_RESP_ANTCD_8821C)
+#define BIT_SET_WMAC_RESP_ANTCD_8821C(x, v)                                    \
+	(BIT_CLEAR_WMAC_RESP_ANTCD_8821C(x) | BIT_WMAC_RESP_ANTCD_8821C(v))
+
+/* 2 REG_RSVD_8821C */
+
+/* 2 REG_BCN_PSR_RPT2_8821C (BEACON PARSER REPORT REGISTER2) */
+
+#define BIT_SHIFT_DTIM_CNT2_8821C 24
+#define BIT_MASK_DTIM_CNT2_8821C 0xff
+#define BIT_DTIM_CNT2_8821C(x)                                                 \
+	(((x) & BIT_MASK_DTIM_CNT2_8821C) << BIT_SHIFT_DTIM_CNT2_8821C)
+#define BITS_DTIM_CNT2_8821C                                                   \
+	(BIT_MASK_DTIM_CNT2_8821C << BIT_SHIFT_DTIM_CNT2_8821C)
+#define BIT_CLEAR_DTIM_CNT2_8821C(x) ((x) & (~BITS_DTIM_CNT2_8821C))
+#define BIT_GET_DTIM_CNT2_8821C(x)                                             \
+	(((x) >> BIT_SHIFT_DTIM_CNT2_8821C) & BIT_MASK_DTIM_CNT2_8821C)
+#define BIT_SET_DTIM_CNT2_8821C(x, v)                                          \
+	(BIT_CLEAR_DTIM_CNT2_8821C(x) | BIT_DTIM_CNT2_8821C(v))
+
+#define BIT_SHIFT_DTIM_PERIOD2_8821C 16
+#define BIT_MASK_DTIM_PERIOD2_8821C 0xff
+#define BIT_DTIM_PERIOD2_8821C(x)                                              \
+	(((x) & BIT_MASK_DTIM_PERIOD2_8821C) << BIT_SHIFT_DTIM_PERIOD2_8821C)
+#define BITS_DTIM_PERIOD2_8821C                                                \
+	(BIT_MASK_DTIM_PERIOD2_8821C << BIT_SHIFT_DTIM_PERIOD2_8821C)
+#define BIT_CLEAR_DTIM_PERIOD2_8821C(x) ((x) & (~BITS_DTIM_PERIOD2_8821C))
+#define BIT_GET_DTIM_PERIOD2_8821C(x)                                          \
+	(((x) >> BIT_SHIFT_DTIM_PERIOD2_8821C) & BIT_MASK_DTIM_PERIOD2_8821C)
+#define BIT_SET_DTIM_PERIOD2_8821C(x, v)                                       \
+	(BIT_CLEAR_DTIM_PERIOD2_8821C(x) | BIT_DTIM_PERIOD2_8821C(v))
+
+#define BIT_DTIM2_8821C BIT(15)
+#define BIT_TIM2_8821C BIT(14)
+
+#define BIT_SHIFT_PS_AID_2_8821C 0
+#define BIT_MASK_PS_AID_2_8821C 0x7ff
+#define BIT_PS_AID_2_8821C(x)                                                  \
+	(((x) & BIT_MASK_PS_AID_2_8821C) << BIT_SHIFT_PS_AID_2_8821C)
+#define BITS_PS_AID_2_8821C                                                    \
+	(BIT_MASK_PS_AID_2_8821C << BIT_SHIFT_PS_AID_2_8821C)
+#define BIT_CLEAR_PS_AID_2_8821C(x) ((x) & (~BITS_PS_AID_2_8821C))
+#define BIT_GET_PS_AID_2_8821C(x)                                              \
+	(((x) >> BIT_SHIFT_PS_AID_2_8821C) & BIT_MASK_PS_AID_2_8821C)
+#define BIT_SET_PS_AID_2_8821C(x, v)                                           \
+	(BIT_CLEAR_PS_AID_2_8821C(x) | BIT_PS_AID_2_8821C(v))
+
+/* 2 REG_BCN_PSR_RPT3_8821C (BEACON PARSER REPORT REGISTER3) */
+
+#define BIT_SHIFT_DTIM_CNT3_8821C 24
+#define BIT_MASK_DTIM_CNT3_8821C 0xff
+#define BIT_DTIM_CNT3_8821C(x)                                                 \
+	(((x) & BIT_MASK_DTIM_CNT3_8821C) << BIT_SHIFT_DTIM_CNT3_8821C)
+#define BITS_DTIM_CNT3_8821C                                                   \
+	(BIT_MASK_DTIM_CNT3_8821C << BIT_SHIFT_DTIM_CNT3_8821C)
+#define BIT_CLEAR_DTIM_CNT3_8821C(x) ((x) & (~BITS_DTIM_CNT3_8821C))
+#define BIT_GET_DTIM_CNT3_8821C(x)                                             \
+	(((x) >> BIT_SHIFT_DTIM_CNT3_8821C) & BIT_MASK_DTIM_CNT3_8821C)
+#define BIT_SET_DTIM_CNT3_8821C(x, v)                                          \
+	(BIT_CLEAR_DTIM_CNT3_8821C(x) | BIT_DTIM_CNT3_8821C(v))
+
+#define BIT_SHIFT_DTIM_PERIOD3_8821C 16
+#define BIT_MASK_DTIM_PERIOD3_8821C 0xff
+#define BIT_DTIM_PERIOD3_8821C(x)                                              \
+	(((x) & BIT_MASK_DTIM_PERIOD3_8821C) << BIT_SHIFT_DTIM_PERIOD3_8821C)
+#define BITS_DTIM_PERIOD3_8821C                                                \
+	(BIT_MASK_DTIM_PERIOD3_8821C << BIT_SHIFT_DTIM_PERIOD3_8821C)
+#define BIT_CLEAR_DTIM_PERIOD3_8821C(x) ((x) & (~BITS_DTIM_PERIOD3_8821C))
+#define BIT_GET_DTIM_PERIOD3_8821C(x)                                          \
+	(((x) >> BIT_SHIFT_DTIM_PERIOD3_8821C) & BIT_MASK_DTIM_PERIOD3_8821C)
+#define BIT_SET_DTIM_PERIOD3_8821C(x, v)                                       \
+	(BIT_CLEAR_DTIM_PERIOD3_8821C(x) | BIT_DTIM_PERIOD3_8821C(v))
+
+#define BIT_DTIM3_8821C BIT(15)
+#define BIT_TIM3_8821C BIT(14)
+
+#define BIT_SHIFT_PS_AID_3_8821C 0
+#define BIT_MASK_PS_AID_3_8821C 0x7ff
+#define BIT_PS_AID_3_8821C(x)                                                  \
+	(((x) & BIT_MASK_PS_AID_3_8821C) << BIT_SHIFT_PS_AID_3_8821C)
+#define BITS_PS_AID_3_8821C                                                    \
+	(BIT_MASK_PS_AID_3_8821C << BIT_SHIFT_PS_AID_3_8821C)
+#define BIT_CLEAR_PS_AID_3_8821C(x) ((x) & (~BITS_PS_AID_3_8821C))
+#define BIT_GET_PS_AID_3_8821C(x)                                              \
+	(((x) >> BIT_SHIFT_PS_AID_3_8821C) & BIT_MASK_PS_AID_3_8821C)
+#define BIT_SET_PS_AID_3_8821C(x, v)                                           \
+	(BIT_CLEAR_PS_AID_3_8821C(x) | BIT_PS_AID_3_8821C(v))
+
+/* 2 REG_BCN_PSR_RPT4_8821C (BEACON PARSER REPORT REGISTER4) */
+
+#define BIT_SHIFT_DTIM_CNT4_8821C 24
+#define BIT_MASK_DTIM_CNT4_8821C 0xff
+#define BIT_DTIM_CNT4_8821C(x)                                                 \
+	(((x) & BIT_MASK_DTIM_CNT4_8821C) << BIT_SHIFT_DTIM_CNT4_8821C)
+#define BITS_DTIM_CNT4_8821C                                                   \
+	(BIT_MASK_DTIM_CNT4_8821C << BIT_SHIFT_DTIM_CNT4_8821C)
+#define BIT_CLEAR_DTIM_CNT4_8821C(x) ((x) & (~BITS_DTIM_CNT4_8821C))
+#define BIT_GET_DTIM_CNT4_8821C(x)                                             \
+	(((x) >> BIT_SHIFT_DTIM_CNT4_8821C) & BIT_MASK_DTIM_CNT4_8821C)
+#define BIT_SET_DTIM_CNT4_8821C(x, v)                                          \
+	(BIT_CLEAR_DTIM_CNT4_8821C(x) | BIT_DTIM_CNT4_8821C(v))
+
+#define BIT_SHIFT_DTIM_PERIOD4_8821C 16
+#define BIT_MASK_DTIM_PERIOD4_8821C 0xff
+#define BIT_DTIM_PERIOD4_8821C(x)                                              \
+	(((x) & BIT_MASK_DTIM_PERIOD4_8821C) << BIT_SHIFT_DTIM_PERIOD4_8821C)
+#define BITS_DTIM_PERIOD4_8821C                                                \
+	(BIT_MASK_DTIM_PERIOD4_8821C << BIT_SHIFT_DTIM_PERIOD4_8821C)
+#define BIT_CLEAR_DTIM_PERIOD4_8821C(x) ((x) & (~BITS_DTIM_PERIOD4_8821C))
+#define BIT_GET_DTIM_PERIOD4_8821C(x)                                          \
+	(((x) >> BIT_SHIFT_DTIM_PERIOD4_8821C) & BIT_MASK_DTIM_PERIOD4_8821C)
+#define BIT_SET_DTIM_PERIOD4_8821C(x, v)                                       \
+	(BIT_CLEAR_DTIM_PERIOD4_8821C(x) | BIT_DTIM_PERIOD4_8821C(v))
+
+#define BIT_DTIM4_8821C BIT(15)
+#define BIT_TIM4_8821C BIT(14)
+
+#define BIT_SHIFT_PS_AID_4_8821C 0
+#define BIT_MASK_PS_AID_4_8821C 0x7ff
+#define BIT_PS_AID_4_8821C(x)                                                  \
+	(((x) & BIT_MASK_PS_AID_4_8821C) << BIT_SHIFT_PS_AID_4_8821C)
+#define BITS_PS_AID_4_8821C                                                    \
+	(BIT_MASK_PS_AID_4_8821C << BIT_SHIFT_PS_AID_4_8821C)
+#define BIT_CLEAR_PS_AID_4_8821C(x) ((x) & (~BITS_PS_AID_4_8821C))
+#define BIT_GET_PS_AID_4_8821C(x)                                              \
+	(((x) >> BIT_SHIFT_PS_AID_4_8821C) & BIT_MASK_PS_AID_4_8821C)
+#define BIT_SET_PS_AID_4_8821C(x, v)                                           \
+	(BIT_CLEAR_PS_AID_4_8821C(x) | BIT_PS_AID_4_8821C(v))
+
+/* 2 REG_A1_ADDR_MASK_8821C (A1 ADDR MASK REGISTER) */
+
+#define BIT_SHIFT_A1_ADDR_MASK_8821C 0
+#define BIT_MASK_A1_ADDR_MASK_8821C 0xffffffffL
+#define BIT_A1_ADDR_MASK_8821C(x)                                              \
+	(((x) & BIT_MASK_A1_ADDR_MASK_8821C) << BIT_SHIFT_A1_ADDR_MASK_8821C)
+#define BITS_A1_ADDR_MASK_8821C                                                \
+	(BIT_MASK_A1_ADDR_MASK_8821C << BIT_SHIFT_A1_ADDR_MASK_8821C)
+#define BIT_CLEAR_A1_ADDR_MASK_8821C(x) ((x) & (~BITS_A1_ADDR_MASK_8821C))
+#define BIT_GET_A1_ADDR_MASK_8821C(x)                                          \
+	(((x) >> BIT_SHIFT_A1_ADDR_MASK_8821C) & BIT_MASK_A1_ADDR_MASK_8821C)
+#define BIT_SET_A1_ADDR_MASK_8821C(x, v)                                       \
+	(BIT_CLEAR_A1_ADDR_MASK_8821C(x) | BIT_A1_ADDR_MASK_8821C(v))
+
+/* 2 REG_RSVD_8821C */
+
+/* 2 REG_RSVD_8821C */
+
+/* 2 REG_RSVD_8821C */
+
+/* 2 REG_RSVD_8821C */
+
+/* 2 REG_MACID2_8821C (MAC ID2 REGISTER) */
+
+#define BIT_SHIFT_MACID2_V1_8821C 0
+#define BIT_MASK_MACID2_V1_8821C 0xffffffffL
+#define BIT_MACID2_V1_8821C(x)                                                 \
+	(((x) & BIT_MASK_MACID2_V1_8821C) << BIT_SHIFT_MACID2_V1_8821C)
+#define BITS_MACID2_V1_8821C                                                   \
+	(BIT_MASK_MACID2_V1_8821C << BIT_SHIFT_MACID2_V1_8821C)
+#define BIT_CLEAR_MACID2_V1_8821C(x) ((x) & (~BITS_MACID2_V1_8821C))
+#define BIT_GET_MACID2_V1_8821C(x)                                             \
+	(((x) >> BIT_SHIFT_MACID2_V1_8821C) & BIT_MASK_MACID2_V1_8821C)
+#define BIT_SET_MACID2_V1_8821C(x, v)                                          \
+	(BIT_CLEAR_MACID2_V1_8821C(x) | BIT_MACID2_V1_8821C(v))
+
+/* 2 REG_MACID2_H_8821C (MAC ID2 REGISTER) */
+
+#define BIT_SHIFT_MACID2_H_V1_8821C 0
+#define BIT_MASK_MACID2_H_V1_8821C 0xffff
+#define BIT_MACID2_H_V1_8821C(x)                                               \
+	(((x) & BIT_MASK_MACID2_H_V1_8821C) << BIT_SHIFT_MACID2_H_V1_8821C)
+#define BITS_MACID2_H_V1_8821C                                                 \
+	(BIT_MASK_MACID2_H_V1_8821C << BIT_SHIFT_MACID2_H_V1_8821C)
+#define BIT_CLEAR_MACID2_H_V1_8821C(x) ((x) & (~BITS_MACID2_H_V1_8821C))
+#define BIT_GET_MACID2_H_V1_8821C(x)                                           \
+	(((x) >> BIT_SHIFT_MACID2_H_V1_8821C) & BIT_MASK_MACID2_H_V1_8821C)
+#define BIT_SET_MACID2_H_V1_8821C(x, v)                                        \
+	(BIT_CLEAR_MACID2_H_V1_8821C(x) | BIT_MACID2_H_V1_8821C(v))
+
+/* 2 REG_BSSID2_8821C (BSSID2 REGISTER) */
+
+#define BIT_SHIFT_BSSID2_V1_8821C 0
+#define BIT_MASK_BSSID2_V1_8821C 0xffffffffL
+#define BIT_BSSID2_V1_8821C(x)                                                 \
+	(((x) & BIT_MASK_BSSID2_V1_8821C) << BIT_SHIFT_BSSID2_V1_8821C)
+#define BITS_BSSID2_V1_8821C                                                   \
+	(BIT_MASK_BSSID2_V1_8821C << BIT_SHIFT_BSSID2_V1_8821C)
+#define BIT_CLEAR_BSSID2_V1_8821C(x) ((x) & (~BITS_BSSID2_V1_8821C))
+#define BIT_GET_BSSID2_V1_8821C(x)                                             \
+	(((x) >> BIT_SHIFT_BSSID2_V1_8821C) & BIT_MASK_BSSID2_V1_8821C)
+#define BIT_SET_BSSID2_V1_8821C(x, v)                                          \
+	(BIT_CLEAR_BSSID2_V1_8821C(x) | BIT_BSSID2_V1_8821C(v))
+
+/* 2 REG_BSSID2_H_8821C (BSSID2 REGISTER) */
+
+#define BIT_SHIFT_BSSID2_H_V1_8821C 0
+#define BIT_MASK_BSSID2_H_V1_8821C 0xffff
+#define BIT_BSSID2_H_V1_8821C(x)                                               \
+	(((x) & BIT_MASK_BSSID2_H_V1_8821C) << BIT_SHIFT_BSSID2_H_V1_8821C)
+#define BITS_BSSID2_H_V1_8821C                                                 \
+	(BIT_MASK_BSSID2_H_V1_8821C << BIT_SHIFT_BSSID2_H_V1_8821C)
+#define BIT_CLEAR_BSSID2_H_V1_8821C(x) ((x) & (~BITS_BSSID2_H_V1_8821C))
+#define BIT_GET_BSSID2_H_V1_8821C(x)                                           \
+	(((x) >> BIT_SHIFT_BSSID2_H_V1_8821C) & BIT_MASK_BSSID2_H_V1_8821C)
+#define BIT_SET_BSSID2_H_V1_8821C(x, v)                                        \
+	(BIT_CLEAR_BSSID2_H_V1_8821C(x) | BIT_BSSID2_H_V1_8821C(v))
+
+/* 2 REG_MACID3_8821C (MAC ID3 REGISTER) */
+
+#define BIT_SHIFT_MACID3_V1_8821C 0
+#define BIT_MASK_MACID3_V1_8821C 0xffffffffL
+#define BIT_MACID3_V1_8821C(x)                                                 \
+	(((x) & BIT_MASK_MACID3_V1_8821C) << BIT_SHIFT_MACID3_V1_8821C)
+#define BITS_MACID3_V1_8821C                                                   \
+	(BIT_MASK_MACID3_V1_8821C << BIT_SHIFT_MACID3_V1_8821C)
+#define BIT_CLEAR_MACID3_V1_8821C(x) ((x) & (~BITS_MACID3_V1_8821C))
+#define BIT_GET_MACID3_V1_8821C(x)                                             \
+	(((x) >> BIT_SHIFT_MACID3_V1_8821C) & BIT_MASK_MACID3_V1_8821C)
+#define BIT_SET_MACID3_V1_8821C(x, v)                                          \
+	(BIT_CLEAR_MACID3_V1_8821C(x) | BIT_MACID3_V1_8821C(v))
+
+/* 2 REG_MACID3_H_8821C (MAC ID3 REGISTER) */
+
+#define BIT_SHIFT_MACID3_H_V1_8821C 0
+#define BIT_MASK_MACID3_H_V1_8821C 0xffff
+#define BIT_MACID3_H_V1_8821C(x)                                               \
+	(((x) & BIT_MASK_MACID3_H_V1_8821C) << BIT_SHIFT_MACID3_H_V1_8821C)
+#define BITS_MACID3_H_V1_8821C                                                 \
+	(BIT_MASK_MACID3_H_V1_8821C << BIT_SHIFT_MACID3_H_V1_8821C)
+#define BIT_CLEAR_MACID3_H_V1_8821C(x) ((x) & (~BITS_MACID3_H_V1_8821C))
+#define BIT_GET_MACID3_H_V1_8821C(x)                                           \
+	(((x) >> BIT_SHIFT_MACID3_H_V1_8821C) & BIT_MASK_MACID3_H_V1_8821C)
+#define BIT_SET_MACID3_H_V1_8821C(x, v)                                        \
+	(BIT_CLEAR_MACID3_H_V1_8821C(x) | BIT_MACID3_H_V1_8821C(v))
+
+/* 2 REG_BSSID3_8821C (BSSID3 REGISTER) */
+
+#define BIT_SHIFT_BSSID3_V1_8821C 0
+#define BIT_MASK_BSSID3_V1_8821C 0xffffffffL
+#define BIT_BSSID3_V1_8821C(x)                                                 \
+	(((x) & BIT_MASK_BSSID3_V1_8821C) << BIT_SHIFT_BSSID3_V1_8821C)
+#define BITS_BSSID3_V1_8821C                                                   \
+	(BIT_MASK_BSSID3_V1_8821C << BIT_SHIFT_BSSID3_V1_8821C)
+#define BIT_CLEAR_BSSID3_V1_8821C(x) ((x) & (~BITS_BSSID3_V1_8821C))
+#define BIT_GET_BSSID3_V1_8821C(x)                                             \
+	(((x) >> BIT_SHIFT_BSSID3_V1_8821C) & BIT_MASK_BSSID3_V1_8821C)
+#define BIT_SET_BSSID3_V1_8821C(x, v)                                          \
+	(BIT_CLEAR_BSSID3_V1_8821C(x) | BIT_BSSID3_V1_8821C(v))
+
+/* 2 REG_BSSID3_H_8821C (BSSID3 REGISTER) */
+
+#define BIT_SHIFT_BSSID3_H_V1_8821C 0
+#define BIT_MASK_BSSID3_H_V1_8821C 0xffff
+#define BIT_BSSID3_H_V1_8821C(x)                                               \
+	(((x) & BIT_MASK_BSSID3_H_V1_8821C) << BIT_SHIFT_BSSID3_H_V1_8821C)
+#define BITS_BSSID3_H_V1_8821C                                                 \
+	(BIT_MASK_BSSID3_H_V1_8821C << BIT_SHIFT_BSSID3_H_V1_8821C)
+#define BIT_CLEAR_BSSID3_H_V1_8821C(x) ((x) & (~BITS_BSSID3_H_V1_8821C))
+#define BIT_GET_BSSID3_H_V1_8821C(x)                                           \
+	(((x) >> BIT_SHIFT_BSSID3_H_V1_8821C) & BIT_MASK_BSSID3_H_V1_8821C)
+#define BIT_SET_BSSID3_H_V1_8821C(x, v)                                        \
+	(BIT_CLEAR_BSSID3_H_V1_8821C(x) | BIT_BSSID3_H_V1_8821C(v))
+
+/* 2 REG_MACID4_8821C (MAC ID4 REGISTER) */
+
+#define BIT_SHIFT_MACID4_V1_8821C 0
+#define BIT_MASK_MACID4_V1_8821C 0xffffffffL
+#define BIT_MACID4_V1_8821C(x)                                                 \
+	(((x) & BIT_MASK_MACID4_V1_8821C) << BIT_SHIFT_MACID4_V1_8821C)
+#define BITS_MACID4_V1_8821C                                                   \
+	(BIT_MASK_MACID4_V1_8821C << BIT_SHIFT_MACID4_V1_8821C)
+#define BIT_CLEAR_MACID4_V1_8821C(x) ((x) & (~BITS_MACID4_V1_8821C))
+#define BIT_GET_MACID4_V1_8821C(x)                                             \
+	(((x) >> BIT_SHIFT_MACID4_V1_8821C) & BIT_MASK_MACID4_V1_8821C)
+#define BIT_SET_MACID4_V1_8821C(x, v)                                          \
+	(BIT_CLEAR_MACID4_V1_8821C(x) | BIT_MACID4_V1_8821C(v))
+
+/* 2 REG_MACID4_H_8821C (MAC ID4 REGISTER) */
+
+#define BIT_SHIFT_MACID4_H_V1_8821C 0
+#define BIT_MASK_MACID4_H_V1_8821C 0xffff
+#define BIT_MACID4_H_V1_8821C(x)                                               \
+	(((x) & BIT_MASK_MACID4_H_V1_8821C) << BIT_SHIFT_MACID4_H_V1_8821C)
+#define BITS_MACID4_H_V1_8821C                                                 \
+	(BIT_MASK_MACID4_H_V1_8821C << BIT_SHIFT_MACID4_H_V1_8821C)
+#define BIT_CLEAR_MACID4_H_V1_8821C(x) ((x) & (~BITS_MACID4_H_V1_8821C))
+#define BIT_GET_MACID4_H_V1_8821C(x)                                           \
+	(((x) >> BIT_SHIFT_MACID4_H_V1_8821C) & BIT_MASK_MACID4_H_V1_8821C)
+#define BIT_SET_MACID4_H_V1_8821C(x, v)                                        \
+	(BIT_CLEAR_MACID4_H_V1_8821C(x) | BIT_MACID4_H_V1_8821C(v))
+
+/* 2 REG_BSSID4_8821C (BSSID4 REGISTER) */
+
+#define BIT_SHIFT_BSSID4_V1_8821C 0
+#define BIT_MASK_BSSID4_V1_8821C 0xffffffffL
+#define BIT_BSSID4_V1_8821C(x)                                                 \
+	(((x) & BIT_MASK_BSSID4_V1_8821C) << BIT_SHIFT_BSSID4_V1_8821C)
+#define BITS_BSSID4_V1_8821C                                                   \
+	(BIT_MASK_BSSID4_V1_8821C << BIT_SHIFT_BSSID4_V1_8821C)
+#define BIT_CLEAR_BSSID4_V1_8821C(x) ((x) & (~BITS_BSSID4_V1_8821C))
+#define BIT_GET_BSSID4_V1_8821C(x)                                             \
+	(((x) >> BIT_SHIFT_BSSID4_V1_8821C) & BIT_MASK_BSSID4_V1_8821C)
+#define BIT_SET_BSSID4_V1_8821C(x, v)                                          \
+	(BIT_CLEAR_BSSID4_V1_8821C(x) | BIT_BSSID4_V1_8821C(v))
+
+/* 2 REG_BSSID4_H_8821C (BSSID4 REGISTER) */
+
+#define BIT_SHIFT_BSSID4_H_V1_8821C 0
+#define BIT_MASK_BSSID4_H_V1_8821C 0xffff
+#define BIT_BSSID4_H_V1_8821C(x)                                               \
+	(((x) & BIT_MASK_BSSID4_H_V1_8821C) << BIT_SHIFT_BSSID4_H_V1_8821C)
+#define BITS_BSSID4_H_V1_8821C                                                 \
+	(BIT_MASK_BSSID4_H_V1_8821C << BIT_SHIFT_BSSID4_H_V1_8821C)
+#define BIT_CLEAR_BSSID4_H_V1_8821C(x) ((x) & (~BITS_BSSID4_H_V1_8821C))
+#define BIT_GET_BSSID4_H_V1_8821C(x)                                           \
+	(((x) >> BIT_SHIFT_BSSID4_H_V1_8821C) & BIT_MASK_BSSID4_H_V1_8821C)
+#define BIT_SET_BSSID4_H_V1_8821C(x, v)                                        \
+	(BIT_CLEAR_BSSID4_H_V1_8821C(x) | BIT_BSSID4_H_V1_8821C(v))
+
+/* 2 REG_NOA_REPORT_8821C */
+
+/* 2 REG_NOA_REPORT_1_8821C */
+
+/* 2 REG_NOA_REPORT_2_8821C */
+
+/* 2 REG_NOA_REPORT_3_8821C */
+
+/* 2 REG_PWRBIT_SETTING_8821C */
+#define BIT_CLI3_PWRBIT_OW_EN_8821C BIT(7)
+#define BIT_CLI3_PWR_ST_8821C BIT(6)
+#define BIT_CLI2_PWRBIT_OW_EN_8821C BIT(5)
+#define BIT_CLI2_PWR_ST_8821C BIT(4)
+#define BIT_CLI1_PWRBIT_OW_EN_8821C BIT(3)
+#define BIT_CLI1_PWR_ST_8821C BIT(2)
+#define BIT_CLI0_PWRBIT_OW_EN_8821C BIT(1)
+#define BIT_CLI0_PWR_ST_8821C BIT(0)
+
+/* 2 REG_RSVD_8821C */
+
+/* 2 REG_RSVD_8821C */
+
+/* 2 REG_RSVD_8821C */
+
+/* 2 REG_RSVD_8821C */
+
+/* 2 REG_RSVD_8821C */
+
+/* 2 REG_RSVD_8821C */
+
+/* 2 REG_MU_BF_OPTION_8821C */
+#define BIT_WMAC_RESP_NONSTA1_DIS_8821C BIT(7)
+#define BIT_WMAC_TXMU_ACKPOLICY_EN_8821C BIT(6)
+
+#define BIT_SHIFT_WMAC_TXMU_ACKPOLICY_8821C 4
+#define BIT_MASK_WMAC_TXMU_ACKPOLICY_8821C 0x3
+#define BIT_WMAC_TXMU_ACKPOLICY_8821C(x)                                       \
+	(((x) & BIT_MASK_WMAC_TXMU_ACKPOLICY_8821C)                            \
+	 << BIT_SHIFT_WMAC_TXMU_ACKPOLICY_8821C)
+#define BITS_WMAC_TXMU_ACKPOLICY_8821C                                         \
+	(BIT_MASK_WMAC_TXMU_ACKPOLICY_8821C                                    \
+	 << BIT_SHIFT_WMAC_TXMU_ACKPOLICY_8821C)
+#define BIT_CLEAR_WMAC_TXMU_ACKPOLICY_8821C(x)                                 \
+	((x) & (~BITS_WMAC_TXMU_ACKPOLICY_8821C))
+#define BIT_GET_WMAC_TXMU_ACKPOLICY_8821C(x)                                   \
+	(((x) >> BIT_SHIFT_WMAC_TXMU_ACKPOLICY_8821C) &                        \
+	 BIT_MASK_WMAC_TXMU_ACKPOLICY_8821C)
+#define BIT_SET_WMAC_TXMU_ACKPOLICY_8821C(x, v)                                \
+	(BIT_CLEAR_WMAC_TXMU_ACKPOLICY_8821C(x) |                              \
+	 BIT_WMAC_TXMU_ACKPOLICY_8821C(v))
+
+#define BIT_SHIFT_WMAC_MU_BFEE_PORT_SEL_8821C 1
+#define BIT_MASK_WMAC_MU_BFEE_PORT_SEL_8821C 0x7
+#define BIT_WMAC_MU_BFEE_PORT_SEL_8821C(x)                                     \
+	(((x) & BIT_MASK_WMAC_MU_BFEE_PORT_SEL_8821C)                          \
+	 << BIT_SHIFT_WMAC_MU_BFEE_PORT_SEL_8821C)
+#define BITS_WMAC_MU_BFEE_PORT_SEL_8821C                                       \
+	(BIT_MASK_WMAC_MU_BFEE_PORT_SEL_8821C                                  \
+	 << BIT_SHIFT_WMAC_MU_BFEE_PORT_SEL_8821C)
+#define BIT_CLEAR_WMAC_MU_BFEE_PORT_SEL_8821C(x)                               \
+	((x) & (~BITS_WMAC_MU_BFEE_PORT_SEL_8821C))
+#define BIT_GET_WMAC_MU_BFEE_PORT_SEL_8821C(x)                                 \
+	(((x) >> BIT_SHIFT_WMAC_MU_BFEE_PORT_SEL_8821C) &                      \
+	 BIT_MASK_WMAC_MU_BFEE_PORT_SEL_8821C)
+#define BIT_SET_WMAC_MU_BFEE_PORT_SEL_8821C(x, v)                              \
+	(BIT_CLEAR_WMAC_MU_BFEE_PORT_SEL_8821C(x) |                            \
+	 BIT_WMAC_MU_BFEE_PORT_SEL_8821C(v))
+
+#define BIT_WMAC_MU_BFEE_DIS_8821C BIT(0)
+
+/* 2 REG_WMAC_PAUSE_BB_CLR_TH_8821C */
+
+#define BIT_SHIFT_WMAC_PAUSE_BB_CLR_TH_8821C 0
+#define BIT_MASK_WMAC_PAUSE_BB_CLR_TH_8821C 0xff
+#define BIT_WMAC_PAUSE_BB_CLR_TH_8821C(x)                                      \
+	(((x) & BIT_MASK_WMAC_PAUSE_BB_CLR_TH_8821C)                           \
+	 << BIT_SHIFT_WMAC_PAUSE_BB_CLR_TH_8821C)
+#define BITS_WMAC_PAUSE_BB_CLR_TH_8821C                                        \
+	(BIT_MASK_WMAC_PAUSE_BB_CLR_TH_8821C                                   \
+	 << BIT_SHIFT_WMAC_PAUSE_BB_CLR_TH_8821C)
+#define BIT_CLEAR_WMAC_PAUSE_BB_CLR_TH_8821C(x)                                \
+	((x) & (~BITS_WMAC_PAUSE_BB_CLR_TH_8821C))
+#define BIT_GET_WMAC_PAUSE_BB_CLR_TH_8821C(x)                                  \
+	(((x) >> BIT_SHIFT_WMAC_PAUSE_BB_CLR_TH_8821C) &                       \
+	 BIT_MASK_WMAC_PAUSE_BB_CLR_TH_8821C)
+#define BIT_SET_WMAC_PAUSE_BB_CLR_TH_8821C(x, v)                               \
+	(BIT_CLEAR_WMAC_PAUSE_BB_CLR_TH_8821C(x) |                             \
+	 BIT_WMAC_PAUSE_BB_CLR_TH_8821C(v))
+
+/* 2 REG_WMAC_MU_ARB_8821C */
+#define BIT_WMAC_ARB_HW_ADAPT_EN_8821C BIT(7)
+#define BIT_WMAC_ARB_SW_EN_8821C BIT(6)
+
+#define BIT_SHIFT_WMAC_ARB_SW_STATE_8821C 0
+#define BIT_MASK_WMAC_ARB_SW_STATE_8821C 0x3f
+#define BIT_WMAC_ARB_SW_STATE_8821C(x)                                         \
+	(((x) & BIT_MASK_WMAC_ARB_SW_STATE_8821C)                              \
+	 << BIT_SHIFT_WMAC_ARB_SW_STATE_8821C)
+#define BITS_WMAC_ARB_SW_STATE_8821C                                           \
+	(BIT_MASK_WMAC_ARB_SW_STATE_8821C << BIT_SHIFT_WMAC_ARB_SW_STATE_8821C)
+#define BIT_CLEAR_WMAC_ARB_SW_STATE_8821C(x)                                   \
+	((x) & (~BITS_WMAC_ARB_SW_STATE_8821C))
+#define BIT_GET_WMAC_ARB_SW_STATE_8821C(x)                                     \
+	(((x) >> BIT_SHIFT_WMAC_ARB_SW_STATE_8821C) &                          \
+	 BIT_MASK_WMAC_ARB_SW_STATE_8821C)
+#define BIT_SET_WMAC_ARB_SW_STATE_8821C(x, v)                                  \
+	(BIT_CLEAR_WMAC_ARB_SW_STATE_8821C(x) | BIT_WMAC_ARB_SW_STATE_8821C(v))
+
+/* 2 REG_WMAC_MU_OPTION_8821C */
+
+#define BIT_SHIFT_WMAC_MU_DBGSEL_8821C 5
+#define BIT_MASK_WMAC_MU_DBGSEL_8821C 0x3
+#define BIT_WMAC_MU_DBGSEL_8821C(x)                                            \
+	(((x) & BIT_MASK_WMAC_MU_DBGSEL_8821C)                                 \
+	 << BIT_SHIFT_WMAC_MU_DBGSEL_8821C)
+#define BITS_WMAC_MU_DBGSEL_8821C                                              \
+	(BIT_MASK_WMAC_MU_DBGSEL_8821C << BIT_SHIFT_WMAC_MU_DBGSEL_8821C)
+#define BIT_CLEAR_WMAC_MU_DBGSEL_8821C(x) ((x) & (~BITS_WMAC_MU_DBGSEL_8821C))
+#define BIT_GET_WMAC_MU_DBGSEL_8821C(x)                                        \
+	(((x) >> BIT_SHIFT_WMAC_MU_DBGSEL_8821C) &                             \
+	 BIT_MASK_WMAC_MU_DBGSEL_8821C)
+#define BIT_SET_WMAC_MU_DBGSEL_8821C(x, v)                                     \
+	(BIT_CLEAR_WMAC_MU_DBGSEL_8821C(x) | BIT_WMAC_MU_DBGSEL_8821C(v))
+
+#define BIT_SHIFT_WMAC_MU_CPRD_TIMEOUT_8821C 0
+#define BIT_MASK_WMAC_MU_CPRD_TIMEOUT_8821C 0x1f
+#define BIT_WMAC_MU_CPRD_TIMEOUT_8821C(x)                                      \
+	(((x) & BIT_MASK_WMAC_MU_CPRD_TIMEOUT_8821C)                           \
+	 << BIT_SHIFT_WMAC_MU_CPRD_TIMEOUT_8821C)
+#define BITS_WMAC_MU_CPRD_TIMEOUT_8821C                                        \
+	(BIT_MASK_WMAC_MU_CPRD_TIMEOUT_8821C                                   \
+	 << BIT_SHIFT_WMAC_MU_CPRD_TIMEOUT_8821C)
+#define BIT_CLEAR_WMAC_MU_CPRD_TIMEOUT_8821C(x)                                \
+	((x) & (~BITS_WMAC_MU_CPRD_TIMEOUT_8821C))
+#define BIT_GET_WMAC_MU_CPRD_TIMEOUT_8821C(x)                                  \
+	(((x) >> BIT_SHIFT_WMAC_MU_CPRD_TIMEOUT_8821C) &                       \
+	 BIT_MASK_WMAC_MU_CPRD_TIMEOUT_8821C)
+#define BIT_SET_WMAC_MU_CPRD_TIMEOUT_8821C(x, v)                               \
+	(BIT_CLEAR_WMAC_MU_CPRD_TIMEOUT_8821C(x) |                             \
+	 BIT_WMAC_MU_CPRD_TIMEOUT_8821C(v))
+
+/* 2 REG_WMAC_MU_BF_CTL_8821C */
+#define BIT_WMAC_INVLD_BFPRT_CHK_8821C BIT(15)
+#define BIT_WMAC_RETXBFRPTSEQ_UPD_8821C BIT(14)
+
+#define BIT_SHIFT_WMAC_MU_BFRPTSEG_SEL_8821C 12
+#define BIT_MASK_WMAC_MU_BFRPTSEG_SEL_8821C 0x3
+#define BIT_WMAC_MU_BFRPTSEG_SEL_8821C(x)                                      \
+	(((x) & BIT_MASK_WMAC_MU_BFRPTSEG_SEL_8821C)                           \
+	 << BIT_SHIFT_WMAC_MU_BFRPTSEG_SEL_8821C)
+#define BITS_WMAC_MU_BFRPTSEG_SEL_8821C                                        \
+	(BIT_MASK_WMAC_MU_BFRPTSEG_SEL_8821C                                   \
+	 << BIT_SHIFT_WMAC_MU_BFRPTSEG_SEL_8821C)
+#define BIT_CLEAR_WMAC_MU_BFRPTSEG_SEL_8821C(x)                                \
+	((x) & (~BITS_WMAC_MU_BFRPTSEG_SEL_8821C))
+#define BIT_GET_WMAC_MU_BFRPTSEG_SEL_8821C(x)                                  \
+	(((x) >> BIT_SHIFT_WMAC_MU_BFRPTSEG_SEL_8821C) &                       \
+	 BIT_MASK_WMAC_MU_BFRPTSEG_SEL_8821C)
+#define BIT_SET_WMAC_MU_BFRPTSEG_SEL_8821C(x, v)                               \
+	(BIT_CLEAR_WMAC_MU_BFRPTSEG_SEL_8821C(x) |                             \
+	 BIT_WMAC_MU_BFRPTSEG_SEL_8821C(v))
+
+#define BIT_SHIFT_WMAC_MU_BF_MYAID_8821C 0
+#define BIT_MASK_WMAC_MU_BF_MYAID_8821C 0xfff
+#define BIT_WMAC_MU_BF_MYAID_8821C(x)                                          \
+	(((x) & BIT_MASK_WMAC_MU_BF_MYAID_8821C)                               \
+	 << BIT_SHIFT_WMAC_MU_BF_MYAID_8821C)
+#define BITS_WMAC_MU_BF_MYAID_8821C                                            \
+	(BIT_MASK_WMAC_MU_BF_MYAID_8821C << BIT_SHIFT_WMAC_MU_BF_MYAID_8821C)
+#define BIT_CLEAR_WMAC_MU_BF_MYAID_8821C(x)                                    \
+	((x) & (~BITS_WMAC_MU_BF_MYAID_8821C))
+#define BIT_GET_WMAC_MU_BF_MYAID_8821C(x)                                      \
+	(((x) >> BIT_SHIFT_WMAC_MU_BF_MYAID_8821C) &                           \
+	 BIT_MASK_WMAC_MU_BF_MYAID_8821C)
+#define BIT_SET_WMAC_MU_BF_MYAID_8821C(x, v)                                   \
+	(BIT_CLEAR_WMAC_MU_BF_MYAID_8821C(x) | BIT_WMAC_MU_BF_MYAID_8821C(v))
+
+/* 2 REG_WMAC_MU_BFRPT_PARA_8821C */
+
+#define BIT_SHIFT_BFRPT_PARA_USERID_SEL_8821C 12
+#define BIT_MASK_BFRPT_PARA_USERID_SEL_8821C 0x7
+#define BIT_BFRPT_PARA_USERID_SEL_8821C(x)                                     \
+	(((x) & BIT_MASK_BFRPT_PARA_USERID_SEL_8821C)                          \
+	 << BIT_SHIFT_BFRPT_PARA_USERID_SEL_8821C)
+#define BITS_BFRPT_PARA_USERID_SEL_8821C                                       \
+	(BIT_MASK_BFRPT_PARA_USERID_SEL_8821C                                  \
+	 << BIT_SHIFT_BFRPT_PARA_USERID_SEL_8821C)
+#define BIT_CLEAR_BFRPT_PARA_USERID_SEL_8821C(x)                               \
+	((x) & (~BITS_BFRPT_PARA_USERID_SEL_8821C))
+#define BIT_GET_BFRPT_PARA_USERID_SEL_8821C(x)                                 \
+	(((x) >> BIT_SHIFT_BFRPT_PARA_USERID_SEL_8821C) &                      \
+	 BIT_MASK_BFRPT_PARA_USERID_SEL_8821C)
+#define BIT_SET_BFRPT_PARA_USERID_SEL_8821C(x, v)                              \
+	(BIT_CLEAR_BFRPT_PARA_USERID_SEL_8821C(x) |                            \
+	 BIT_BFRPT_PARA_USERID_SEL_8821C(v))
+
+#define BIT_SHIFT_BFRPT_PARA_8821C 0
+#define BIT_MASK_BFRPT_PARA_8821C 0xfff
+#define BIT_BFRPT_PARA_8821C(x)                                                \
+	(((x) & BIT_MASK_BFRPT_PARA_8821C) << BIT_SHIFT_BFRPT_PARA_8821C)
+#define BITS_BFRPT_PARA_8821C                                                  \
+	(BIT_MASK_BFRPT_PARA_8821C << BIT_SHIFT_BFRPT_PARA_8821C)
+#define BIT_CLEAR_BFRPT_PARA_8821C(x) ((x) & (~BITS_BFRPT_PARA_8821C))
+#define BIT_GET_BFRPT_PARA_8821C(x)                                            \
+	(((x) >> BIT_SHIFT_BFRPT_PARA_8821C) & BIT_MASK_BFRPT_PARA_8821C)
+#define BIT_SET_BFRPT_PARA_8821C(x, v)                                         \
+	(BIT_CLEAR_BFRPT_PARA_8821C(x) | BIT_BFRPT_PARA_8821C(v))
+
+/* 2 REG_WMAC_ASSOCIATED_MU_BFMEE2_8821C */
+#define BIT_STATUS_BFEE2_8821C BIT(10)
+#define BIT_WMAC_MU_BFEE2_EN_8821C BIT(9)
+
+#define BIT_SHIFT_WMAC_MU_BFEE2_AID_8821C 0
+#define BIT_MASK_WMAC_MU_BFEE2_AID_8821C 0x1ff
+#define BIT_WMAC_MU_BFEE2_AID_8821C(x)                                         \
+	(((x) & BIT_MASK_WMAC_MU_BFEE2_AID_8821C)                              \
+	 << BIT_SHIFT_WMAC_MU_BFEE2_AID_8821C)
+#define BITS_WMAC_MU_BFEE2_AID_8821C                                           \
+	(BIT_MASK_WMAC_MU_BFEE2_AID_8821C << BIT_SHIFT_WMAC_MU_BFEE2_AID_8821C)
+#define BIT_CLEAR_WMAC_MU_BFEE2_AID_8821C(x)                                   \
+	((x) & (~BITS_WMAC_MU_BFEE2_AID_8821C))
+#define BIT_GET_WMAC_MU_BFEE2_AID_8821C(x)                                     \
+	(((x) >> BIT_SHIFT_WMAC_MU_BFEE2_AID_8821C) &                          \
+	 BIT_MASK_WMAC_MU_BFEE2_AID_8821C)
+#define BIT_SET_WMAC_MU_BFEE2_AID_8821C(x, v)                                  \
+	(BIT_CLEAR_WMAC_MU_BFEE2_AID_8821C(x) | BIT_WMAC_MU_BFEE2_AID_8821C(v))
+
+/* 2 REG_WMAC_ASSOCIATED_MU_BFMEE3_8821C */
+#define BIT_STATUS_BFEE3_8821C BIT(10)
+#define BIT_WMAC_MU_BFEE3_EN_8821C BIT(9)
+
+#define BIT_SHIFT_WMAC_MU_BFEE3_AID_8821C 0
+#define BIT_MASK_WMAC_MU_BFEE3_AID_8821C 0x1ff
+#define BIT_WMAC_MU_BFEE3_AID_8821C(x)                                         \
+	(((x) & BIT_MASK_WMAC_MU_BFEE3_AID_8821C)                              \
+	 << BIT_SHIFT_WMAC_MU_BFEE3_AID_8821C)
+#define BITS_WMAC_MU_BFEE3_AID_8821C                                           \
+	(BIT_MASK_WMAC_MU_BFEE3_AID_8821C << BIT_SHIFT_WMAC_MU_BFEE3_AID_8821C)
+#define BIT_CLEAR_WMAC_MU_BFEE3_AID_8821C(x)                                   \
+	((x) & (~BITS_WMAC_MU_BFEE3_AID_8821C))
+#define BIT_GET_WMAC_MU_BFEE3_AID_8821C(x)                                     \
+	(((x) >> BIT_SHIFT_WMAC_MU_BFEE3_AID_8821C) &                          \
+	 BIT_MASK_WMAC_MU_BFEE3_AID_8821C)
+#define BIT_SET_WMAC_MU_BFEE3_AID_8821C(x, v)                                  \
+	(BIT_CLEAR_WMAC_MU_BFEE3_AID_8821C(x) | BIT_WMAC_MU_BFEE3_AID_8821C(v))
+
+/* 2 REG_WMAC_ASSOCIATED_MU_BFMEE4_8821C */
+#define BIT_STATUS_BFEE4_8821C BIT(10)
+#define BIT_WMAC_MU_BFEE4_EN_8821C BIT(9)
+
+#define BIT_SHIFT_WMAC_MU_BFEE4_AID_8821C 0
+#define BIT_MASK_WMAC_MU_BFEE4_AID_8821C 0x1ff
+#define BIT_WMAC_MU_BFEE4_AID_8821C(x)                                         \
+	(((x) & BIT_MASK_WMAC_MU_BFEE4_AID_8821C)                              \
+	 << BIT_SHIFT_WMAC_MU_BFEE4_AID_8821C)
+#define BITS_WMAC_MU_BFEE4_AID_8821C                                           \
+	(BIT_MASK_WMAC_MU_BFEE4_AID_8821C << BIT_SHIFT_WMAC_MU_BFEE4_AID_8821C)
+#define BIT_CLEAR_WMAC_MU_BFEE4_AID_8821C(x)                                   \
+	((x) & (~BITS_WMAC_MU_BFEE4_AID_8821C))
+#define BIT_GET_WMAC_MU_BFEE4_AID_8821C(x)                                     \
+	(((x) >> BIT_SHIFT_WMAC_MU_BFEE4_AID_8821C) &                          \
+	 BIT_MASK_WMAC_MU_BFEE4_AID_8821C)
+#define BIT_SET_WMAC_MU_BFEE4_AID_8821C(x, v)                                  \
+	(BIT_CLEAR_WMAC_MU_BFEE4_AID_8821C(x) | BIT_WMAC_MU_BFEE4_AID_8821C(v))
+
+/* 2 REG_WMAC_ASSOCIATED_MU_BFMEE5_8821C */
+#define BIT_BIT_STATUS_BFEE5_8821C BIT(10)
+#define BIT_WMAC_MU_BFEE5_EN_8821C BIT(9)
+
+#define BIT_SHIFT_WMAC_MU_BFEE5_AID_8821C 0
+#define BIT_MASK_WMAC_MU_BFEE5_AID_8821C 0x1ff
+#define BIT_WMAC_MU_BFEE5_AID_8821C(x)                                         \
+	(((x) & BIT_MASK_WMAC_MU_BFEE5_AID_8821C)                              \
+	 << BIT_SHIFT_WMAC_MU_BFEE5_AID_8821C)
+#define BITS_WMAC_MU_BFEE5_AID_8821C                                           \
+	(BIT_MASK_WMAC_MU_BFEE5_AID_8821C << BIT_SHIFT_WMAC_MU_BFEE5_AID_8821C)
+#define BIT_CLEAR_WMAC_MU_BFEE5_AID_8821C(x)                                   \
+	((x) & (~BITS_WMAC_MU_BFEE5_AID_8821C))
+#define BIT_GET_WMAC_MU_BFEE5_AID_8821C(x)                                     \
+	(((x) >> BIT_SHIFT_WMAC_MU_BFEE5_AID_8821C) &                          \
+	 BIT_MASK_WMAC_MU_BFEE5_AID_8821C)
+#define BIT_SET_WMAC_MU_BFEE5_AID_8821C(x, v)                                  \
+	(BIT_CLEAR_WMAC_MU_BFEE5_AID_8821C(x) | BIT_WMAC_MU_BFEE5_AID_8821C(v))
+
+/* 2 REG_WMAC_ASSOCIATED_MU_BFMEE6_8821C */
+#define BIT_STATUS_BFEE6_8821C BIT(10)
+#define BIT_WMAC_MU_BFEE6_EN_8821C BIT(9)
+
+#define BIT_SHIFT_WMAC_MU_BFEE6_AID_8821C 0
+#define BIT_MASK_WMAC_MU_BFEE6_AID_8821C 0x1ff
+#define BIT_WMAC_MU_BFEE6_AID_8821C(x)                                         \
+	(((x) & BIT_MASK_WMAC_MU_BFEE6_AID_8821C)                              \
+	 << BIT_SHIFT_WMAC_MU_BFEE6_AID_8821C)
+#define BITS_WMAC_MU_BFEE6_AID_8821C                                           \
+	(BIT_MASK_WMAC_MU_BFEE6_AID_8821C << BIT_SHIFT_WMAC_MU_BFEE6_AID_8821C)
+#define BIT_CLEAR_WMAC_MU_BFEE6_AID_8821C(x)                                   \
+	((x) & (~BITS_WMAC_MU_BFEE6_AID_8821C))
+#define BIT_GET_WMAC_MU_BFEE6_AID_8821C(x)                                     \
+	(((x) >> BIT_SHIFT_WMAC_MU_BFEE6_AID_8821C) &                          \
+	 BIT_MASK_WMAC_MU_BFEE6_AID_8821C)
+#define BIT_SET_WMAC_MU_BFEE6_AID_8821C(x, v)                                  \
+	(BIT_CLEAR_WMAC_MU_BFEE6_AID_8821C(x) | BIT_WMAC_MU_BFEE6_AID_8821C(v))
+
+/* 2 REG_WMAC_ASSOCIATED_MU_BFMEE7_8821C */
+#define BIT_STATUS_BFEE7_8821C BIT(10)
+#define BIT_WMAC_MU_BFEE7_EN_8821C BIT(9)
+
+#define BIT_SHIFT_WMAC_MU_BFEE7_AID_8821C 0
+#define BIT_MASK_WMAC_MU_BFEE7_AID_8821C 0x1ff
+#define BIT_WMAC_MU_BFEE7_AID_8821C(x)                                         \
+	(((x) & BIT_MASK_WMAC_MU_BFEE7_AID_8821C)                              \
+	 << BIT_SHIFT_WMAC_MU_BFEE7_AID_8821C)
+#define BITS_WMAC_MU_BFEE7_AID_8821C                                           \
+	(BIT_MASK_WMAC_MU_BFEE7_AID_8821C << BIT_SHIFT_WMAC_MU_BFEE7_AID_8821C)
+#define BIT_CLEAR_WMAC_MU_BFEE7_AID_8821C(x)                                   \
+	((x) & (~BITS_WMAC_MU_BFEE7_AID_8821C))
+#define BIT_GET_WMAC_MU_BFEE7_AID_8821C(x)                                     \
+	(((x) >> BIT_SHIFT_WMAC_MU_BFEE7_AID_8821C) &                          \
+	 BIT_MASK_WMAC_MU_BFEE7_AID_8821C)
+#define BIT_SET_WMAC_MU_BFEE7_AID_8821C(x, v)                                  \
+	(BIT_CLEAR_WMAC_MU_BFEE7_AID_8821C(x) | BIT_WMAC_MU_BFEE7_AID_8821C(v))
+
+/* 2 REG_WMAC_BB_STOP_RX_COUNTER_8821C */
+#define BIT_RST_ALL_COUNTER_8821C BIT(31)
+
+#define BIT_SHIFT_ABORT_RX_VBON_COUNTER_8821C 16
+#define BIT_MASK_ABORT_RX_VBON_COUNTER_8821C 0xff
+#define BIT_ABORT_RX_VBON_COUNTER_8821C(x)                                     \
+	(((x) & BIT_MASK_ABORT_RX_VBON_COUNTER_8821C)                          \
+	 << BIT_SHIFT_ABORT_RX_VBON_COUNTER_8821C)
+#define BITS_ABORT_RX_VBON_COUNTER_8821C                                       \
+	(BIT_MASK_ABORT_RX_VBON_COUNTER_8821C                                  \
+	 << BIT_SHIFT_ABORT_RX_VBON_COUNTER_8821C)
+#define BIT_CLEAR_ABORT_RX_VBON_COUNTER_8821C(x)                               \
+	((x) & (~BITS_ABORT_RX_VBON_COUNTER_8821C))
+#define BIT_GET_ABORT_RX_VBON_COUNTER_8821C(x)                                 \
+	(((x) >> BIT_SHIFT_ABORT_RX_VBON_COUNTER_8821C) &                      \
+	 BIT_MASK_ABORT_RX_VBON_COUNTER_8821C)
+#define BIT_SET_ABORT_RX_VBON_COUNTER_8821C(x, v)                              \
+	(BIT_CLEAR_ABORT_RX_VBON_COUNTER_8821C(x) |                            \
+	 BIT_ABORT_RX_VBON_COUNTER_8821C(v))
+
+#define BIT_SHIFT_ABORT_RX_RDRDY_COUNTER_8821C 8
+#define BIT_MASK_ABORT_RX_RDRDY_COUNTER_8821C 0xff
+#define BIT_ABORT_RX_RDRDY_COUNTER_8821C(x)                                    \
+	(((x) & BIT_MASK_ABORT_RX_RDRDY_COUNTER_8821C)                         \
+	 << BIT_SHIFT_ABORT_RX_RDRDY_COUNTER_8821C)
+#define BITS_ABORT_RX_RDRDY_COUNTER_8821C                                      \
+	(BIT_MASK_ABORT_RX_RDRDY_COUNTER_8821C                                 \
+	 << BIT_SHIFT_ABORT_RX_RDRDY_COUNTER_8821C)
+#define BIT_CLEAR_ABORT_RX_RDRDY_COUNTER_8821C(x)                              \
+	((x) & (~BITS_ABORT_RX_RDRDY_COUNTER_8821C))
+#define BIT_GET_ABORT_RX_RDRDY_COUNTER_8821C(x)                                \
+	(((x) >> BIT_SHIFT_ABORT_RX_RDRDY_COUNTER_8821C) &                     \
+	 BIT_MASK_ABORT_RX_RDRDY_COUNTER_8821C)
+#define BIT_SET_ABORT_RX_RDRDY_COUNTER_8821C(x, v)                             \
+	(BIT_CLEAR_ABORT_RX_RDRDY_COUNTER_8821C(x) |                           \
+	 BIT_ABORT_RX_RDRDY_COUNTER_8821C(v))
+
+#define BIT_SHIFT_VBON_EARLY_FALLING_COUNTER_8821C 0
+#define BIT_MASK_VBON_EARLY_FALLING_COUNTER_8821C 0xff
+#define BIT_VBON_EARLY_FALLING_COUNTER_8821C(x)                                \
+	(((x) & BIT_MASK_VBON_EARLY_FALLING_COUNTER_8821C)                     \
+	 << BIT_SHIFT_VBON_EARLY_FALLING_COUNTER_8821C)
+#define BITS_VBON_EARLY_FALLING_COUNTER_8821C                                  \
+	(BIT_MASK_VBON_EARLY_FALLING_COUNTER_8821C                             \
+	 << BIT_SHIFT_VBON_EARLY_FALLING_COUNTER_8821C)
+#define BIT_CLEAR_VBON_EARLY_FALLING_COUNTER_8821C(x)                          \
+	((x) & (~BITS_VBON_EARLY_FALLING_COUNTER_8821C))
+#define BIT_GET_VBON_EARLY_FALLING_COUNTER_8821C(x)                            \
+	(((x) >> BIT_SHIFT_VBON_EARLY_FALLING_COUNTER_8821C) &                 \
+	 BIT_MASK_VBON_EARLY_FALLING_COUNTER_8821C)
+#define BIT_SET_VBON_EARLY_FALLING_COUNTER_8821C(x, v)                         \
+	(BIT_CLEAR_VBON_EARLY_FALLING_COUNTER_8821C(x) |                       \
+	 BIT_VBON_EARLY_FALLING_COUNTER_8821C(v))
+
+/* 2 REG_WMAC_PLCP_MONITOR_8821C */
+#define BIT_WMAC_PLCP_TRX_SEL_8821C BIT(31)
+
+#define BIT_SHIFT_WMAC_PLCP_RDSIG_SEL_8821C 28
+#define BIT_MASK_WMAC_PLCP_RDSIG_SEL_8821C 0x7
+#define BIT_WMAC_PLCP_RDSIG_SEL_8821C(x)                                       \
+	(((x) & BIT_MASK_WMAC_PLCP_RDSIG_SEL_8821C)                            \
+	 << BIT_SHIFT_WMAC_PLCP_RDSIG_SEL_8821C)
+#define BITS_WMAC_PLCP_RDSIG_SEL_8821C                                         \
+	(BIT_MASK_WMAC_PLCP_RDSIG_SEL_8821C                                    \
+	 << BIT_SHIFT_WMAC_PLCP_RDSIG_SEL_8821C)
+#define BIT_CLEAR_WMAC_PLCP_RDSIG_SEL_8821C(x)                                 \
+	((x) & (~BITS_WMAC_PLCP_RDSIG_SEL_8821C))
+#define BIT_GET_WMAC_PLCP_RDSIG_SEL_8821C(x)                                   \
+	(((x) >> BIT_SHIFT_WMAC_PLCP_RDSIG_SEL_8821C) &                        \
+	 BIT_MASK_WMAC_PLCP_RDSIG_SEL_8821C)
+#define BIT_SET_WMAC_PLCP_RDSIG_SEL_8821C(x, v)                                \
+	(BIT_CLEAR_WMAC_PLCP_RDSIG_SEL_8821C(x) |                              \
+	 BIT_WMAC_PLCP_RDSIG_SEL_8821C(v))
+
+#define BIT_SHIFT_WMAC_RATE_IDX_8821C 24
+#define BIT_MASK_WMAC_RATE_IDX_8821C 0xf
+#define BIT_WMAC_RATE_IDX_8821C(x)                                             \
+	(((x) & BIT_MASK_WMAC_RATE_IDX_8821C) << BIT_SHIFT_WMAC_RATE_IDX_8821C)
+#define BITS_WMAC_RATE_IDX_8821C                                               \
+	(BIT_MASK_WMAC_RATE_IDX_8821C << BIT_SHIFT_WMAC_RATE_IDX_8821C)
+#define BIT_CLEAR_WMAC_RATE_IDX_8821C(x) ((x) & (~BITS_WMAC_RATE_IDX_8821C))
+#define BIT_GET_WMAC_RATE_IDX_8821C(x)                                         \
+	(((x) >> BIT_SHIFT_WMAC_RATE_IDX_8821C) & BIT_MASK_WMAC_RATE_IDX_8821C)
+#define BIT_SET_WMAC_RATE_IDX_8821C(x, v)                                      \
+	(BIT_CLEAR_WMAC_RATE_IDX_8821C(x) | BIT_WMAC_RATE_IDX_8821C(v))
+
+#define BIT_SHIFT_WMAC_PLCP_RDSIG_8821C 0
+#define BIT_MASK_WMAC_PLCP_RDSIG_8821C 0xffffff
+#define BIT_WMAC_PLCP_RDSIG_8821C(x)                                           \
+	(((x) & BIT_MASK_WMAC_PLCP_RDSIG_8821C)                                \
+	 << BIT_SHIFT_WMAC_PLCP_RDSIG_8821C)
+#define BITS_WMAC_PLCP_RDSIG_8821C                                             \
+	(BIT_MASK_WMAC_PLCP_RDSIG_8821C << BIT_SHIFT_WMAC_PLCP_RDSIG_8821C)
+#define BIT_CLEAR_WMAC_PLCP_RDSIG_8821C(x) ((x) & (~BITS_WMAC_PLCP_RDSIG_8821C))
+#define BIT_GET_WMAC_PLCP_RDSIG_8821C(x)                                       \
+	(((x) >> BIT_SHIFT_WMAC_PLCP_RDSIG_8821C) &                            \
+	 BIT_MASK_WMAC_PLCP_RDSIG_8821C)
+#define BIT_SET_WMAC_PLCP_RDSIG_8821C(x, v)                                    \
+	(BIT_CLEAR_WMAC_PLCP_RDSIG_8821C(x) | BIT_WMAC_PLCP_RDSIG_8821C(v))
+
+/* 2 REG_WMAC_PLCP_MONITOR_MUTX_8821C */
+#define BIT_WMAC_MUTX_IDX_8821C BIT(24)
+
+#define BIT_SHIFT_WMAC_PLCP_RDSIG_8821C 0
+#define BIT_MASK_WMAC_PLCP_RDSIG_8821C 0xffffff
+#define BIT_WMAC_PLCP_RDSIG_8821C(x)                                           \
+	(((x) & BIT_MASK_WMAC_PLCP_RDSIG_8821C)                                \
+	 << BIT_SHIFT_WMAC_PLCP_RDSIG_8821C)
+#define BITS_WMAC_PLCP_RDSIG_8821C                                             \
+	(BIT_MASK_WMAC_PLCP_RDSIG_8821C << BIT_SHIFT_WMAC_PLCP_RDSIG_8821C)
+#define BIT_CLEAR_WMAC_PLCP_RDSIG_8821C(x) ((x) & (~BITS_WMAC_PLCP_RDSIG_8821C))
+#define BIT_GET_WMAC_PLCP_RDSIG_8821C(x)                                       \
+	(((x) >> BIT_SHIFT_WMAC_PLCP_RDSIG_8821C) &                            \
+	 BIT_MASK_WMAC_PLCP_RDSIG_8821C)
+#define BIT_SET_WMAC_PLCP_RDSIG_8821C(x, v)                                    \
+	(BIT_CLEAR_WMAC_PLCP_RDSIG_8821C(x) | BIT_WMAC_PLCP_RDSIG_8821C(v))
+
+/* 2 REG_RSVD_8821C */
+
+/* 2 REG_TRANSMIT_ADDRSS_0_8821C (TA0 REGISTER) */
+
+#define BIT_SHIFT_TA0_V1_8821C 0
+#define BIT_MASK_TA0_V1_8821C 0xffffffffL
+#define BIT_TA0_V1_8821C(x)                                                    \
+	(((x) & BIT_MASK_TA0_V1_8821C) << BIT_SHIFT_TA0_V1_8821C)
+#define BITS_TA0_V1_8821C (BIT_MASK_TA0_V1_8821C << BIT_SHIFT_TA0_V1_8821C)
+#define BIT_CLEAR_TA0_V1_8821C(x) ((x) & (~BITS_TA0_V1_8821C))
+#define BIT_GET_TA0_V1_8821C(x)                                                \
+	(((x) >> BIT_SHIFT_TA0_V1_8821C) & BIT_MASK_TA0_V1_8821C)
+#define BIT_SET_TA0_V1_8821C(x, v)                                             \
+	(BIT_CLEAR_TA0_V1_8821C(x) | BIT_TA0_V1_8821C(v))
+
+/* 2 REG_TRANSMIT_ADDRSS_0_H_8821C (TA0 REGISTER) */
+
+#define BIT_SHIFT_TA0_H_V1_8821C 0
+#define BIT_MASK_TA0_H_V1_8821C 0xffff
+#define BIT_TA0_H_V1_8821C(x)                                                  \
+	(((x) & BIT_MASK_TA0_H_V1_8821C) << BIT_SHIFT_TA0_H_V1_8821C)
+#define BITS_TA0_H_V1_8821C                                                    \
+	(BIT_MASK_TA0_H_V1_8821C << BIT_SHIFT_TA0_H_V1_8821C)
+#define BIT_CLEAR_TA0_H_V1_8821C(x) ((x) & (~BITS_TA0_H_V1_8821C))
+#define BIT_GET_TA0_H_V1_8821C(x)                                              \
+	(((x) >> BIT_SHIFT_TA0_H_V1_8821C) & BIT_MASK_TA0_H_V1_8821C)
+#define BIT_SET_TA0_H_V1_8821C(x, v)                                           \
+	(BIT_CLEAR_TA0_H_V1_8821C(x) | BIT_TA0_H_V1_8821C(v))
+
+/* 2 REG_TRANSMIT_ADDRSS_1_8821C (TA1 REGISTER) */
+
+#define BIT_SHIFT_TA1_V1_8821C 0
+#define BIT_MASK_TA1_V1_8821C 0xffffffffL
+#define BIT_TA1_V1_8821C(x)                                                    \
+	(((x) & BIT_MASK_TA1_V1_8821C) << BIT_SHIFT_TA1_V1_8821C)
+#define BITS_TA1_V1_8821C (BIT_MASK_TA1_V1_8821C << BIT_SHIFT_TA1_V1_8821C)
+#define BIT_CLEAR_TA1_V1_8821C(x) ((x) & (~BITS_TA1_V1_8821C))
+#define BIT_GET_TA1_V1_8821C(x)                                                \
+	(((x) >> BIT_SHIFT_TA1_V1_8821C) & BIT_MASK_TA1_V1_8821C)
+#define BIT_SET_TA1_V1_8821C(x, v)                                             \
+	(BIT_CLEAR_TA1_V1_8821C(x) | BIT_TA1_V1_8821C(v))
+
+/* 2 REG_TRANSMIT_ADDRSS_1_H_8821C (TA1 REGISTER) */
+
+#define BIT_SHIFT_TA1_H_V1_8821C 0
+#define BIT_MASK_TA1_H_V1_8821C 0xffff
+#define BIT_TA1_H_V1_8821C(x)                                                  \
+	(((x) & BIT_MASK_TA1_H_V1_8821C) << BIT_SHIFT_TA1_H_V1_8821C)
+#define BITS_TA1_H_V1_8821C                                                    \
+	(BIT_MASK_TA1_H_V1_8821C << BIT_SHIFT_TA1_H_V1_8821C)
+#define BIT_CLEAR_TA1_H_V1_8821C(x) ((x) & (~BITS_TA1_H_V1_8821C))
+#define BIT_GET_TA1_H_V1_8821C(x)                                              \
+	(((x) >> BIT_SHIFT_TA1_H_V1_8821C) & BIT_MASK_TA1_H_V1_8821C)
+#define BIT_SET_TA1_H_V1_8821C(x, v)                                           \
+	(BIT_CLEAR_TA1_H_V1_8821C(x) | BIT_TA1_H_V1_8821C(v))
+
+/* 2 REG_TRANSMIT_ADDRSS_2_8821C (TA2 REGISTER) */
+
+#define BIT_SHIFT_TA2_V1_8821C 0
+#define BIT_MASK_TA2_V1_8821C 0xffffffffL
+#define BIT_TA2_V1_8821C(x)                                                    \
+	(((x) & BIT_MASK_TA2_V1_8821C) << BIT_SHIFT_TA2_V1_8821C)
+#define BITS_TA2_V1_8821C (BIT_MASK_TA2_V1_8821C << BIT_SHIFT_TA2_V1_8821C)
+#define BIT_CLEAR_TA2_V1_8821C(x) ((x) & (~BITS_TA2_V1_8821C))
+#define BIT_GET_TA2_V1_8821C(x)                                                \
+	(((x) >> BIT_SHIFT_TA2_V1_8821C) & BIT_MASK_TA2_V1_8821C)
+#define BIT_SET_TA2_V1_8821C(x, v)                                             \
+	(BIT_CLEAR_TA2_V1_8821C(x) | BIT_TA2_V1_8821C(v))
+
+/* 2 REG_TRANSMIT_ADDRSS_2_H_8821C (TA2 REGISTER) */
+
+#define BIT_SHIFT_TA2_H_V1_8821C 0
+#define BIT_MASK_TA2_H_V1_8821C 0xffff
+#define BIT_TA2_H_V1_8821C(x)                                                  \
+	(((x) & BIT_MASK_TA2_H_V1_8821C) << BIT_SHIFT_TA2_H_V1_8821C)
+#define BITS_TA2_H_V1_8821C                                                    \
+	(BIT_MASK_TA2_H_V1_8821C << BIT_SHIFT_TA2_H_V1_8821C)
+#define BIT_CLEAR_TA2_H_V1_8821C(x) ((x) & (~BITS_TA2_H_V1_8821C))
+#define BIT_GET_TA2_H_V1_8821C(x)                                              \
+	(((x) >> BIT_SHIFT_TA2_H_V1_8821C) & BIT_MASK_TA2_H_V1_8821C)
+#define BIT_SET_TA2_H_V1_8821C(x, v)                                           \
+	(BIT_CLEAR_TA2_H_V1_8821C(x) | BIT_TA2_H_V1_8821C(v))
+
+/* 2 REG_TRANSMIT_ADDRSS_3_8821C (TA3 REGISTER) */
+
+#define BIT_SHIFT_TA2_V1_8821C 0
+#define BIT_MASK_TA2_V1_8821C 0xffffffffL
+#define BIT_TA2_V1_8821C(x)                                                    \
+	(((x) & BIT_MASK_TA2_V1_8821C) << BIT_SHIFT_TA2_V1_8821C)
+#define BITS_TA2_V1_8821C (BIT_MASK_TA2_V1_8821C << BIT_SHIFT_TA2_V1_8821C)
+#define BIT_CLEAR_TA2_V1_8821C(x) ((x) & (~BITS_TA2_V1_8821C))
+#define BIT_GET_TA2_V1_8821C(x)                                                \
+	(((x) >> BIT_SHIFT_TA2_V1_8821C) & BIT_MASK_TA2_V1_8821C)
+#define BIT_SET_TA2_V1_8821C(x, v)                                             \
+	(BIT_CLEAR_TA2_V1_8821C(x) | BIT_TA2_V1_8821C(v))
+
+/* 2 REG_TRANSMIT_ADDRSS_3_H_8821C (TA3 REGISTER) */
+
+#define BIT_SHIFT_TA3_H_V1_8821C 0
+#define BIT_MASK_TA3_H_V1_8821C 0xffff
+#define BIT_TA3_H_V1_8821C(x)                                                  \
+	(((x) & BIT_MASK_TA3_H_V1_8821C) << BIT_SHIFT_TA3_H_V1_8821C)
+#define BITS_TA3_H_V1_8821C                                                    \
+	(BIT_MASK_TA3_H_V1_8821C << BIT_SHIFT_TA3_H_V1_8821C)
+#define BIT_CLEAR_TA3_H_V1_8821C(x) ((x) & (~BITS_TA3_H_V1_8821C))
+#define BIT_GET_TA3_H_V1_8821C(x)                                              \
+	(((x) >> BIT_SHIFT_TA3_H_V1_8821C) & BIT_MASK_TA3_H_V1_8821C)
+#define BIT_SET_TA3_H_V1_8821C(x, v)                                           \
+	(BIT_CLEAR_TA3_H_V1_8821C(x) | BIT_TA3_H_V1_8821C(v))
+
+/* 2 REG_TRANSMIT_ADDRSS_4_8821C (TA4 REGISTER) */
+
+#define BIT_SHIFT_TA4_V1_8821C 0
+#define BIT_MASK_TA4_V1_8821C 0xffffffffL
+#define BIT_TA4_V1_8821C(x)                                                    \
+	(((x) & BIT_MASK_TA4_V1_8821C) << BIT_SHIFT_TA4_V1_8821C)
+#define BITS_TA4_V1_8821C (BIT_MASK_TA4_V1_8821C << BIT_SHIFT_TA4_V1_8821C)
+#define BIT_CLEAR_TA4_V1_8821C(x) ((x) & (~BITS_TA4_V1_8821C))
+#define BIT_GET_TA4_V1_8821C(x)                                                \
+	(((x) >> BIT_SHIFT_TA4_V1_8821C) & BIT_MASK_TA4_V1_8821C)
+#define BIT_SET_TA4_V1_8821C(x, v)                                             \
+	(BIT_CLEAR_TA4_V1_8821C(x) | BIT_TA4_V1_8821C(v))
+
+/* 2 REG_TRANSMIT_ADDRSS_4_H_8821C (TA4 REGISTER) */
+
+#define BIT_SHIFT_TA4_H_V1_8821C 0
+#define BIT_MASK_TA4_H_V1_8821C 0xffff
+#define BIT_TA4_H_V1_8821C(x)                                                  \
+	(((x) & BIT_MASK_TA4_H_V1_8821C) << BIT_SHIFT_TA4_H_V1_8821C)
+#define BITS_TA4_H_V1_8821C                                                    \
+	(BIT_MASK_TA4_H_V1_8821C << BIT_SHIFT_TA4_H_V1_8821C)
+#define BIT_CLEAR_TA4_H_V1_8821C(x) ((x) & (~BITS_TA4_H_V1_8821C))
+#define BIT_GET_TA4_H_V1_8821C(x)                                              \
+	(((x) >> BIT_SHIFT_TA4_H_V1_8821C) & BIT_MASK_TA4_H_V1_8821C)
+#define BIT_SET_TA4_H_V1_8821C(x, v)                                           \
+	(BIT_CLEAR_TA4_H_V1_8821C(x) | BIT_TA4_H_V1_8821C(v))
+
+/* 2 REG_RSVD_8821C */
+
+/* 2 REG_RSVD_8821C */
+
+/* 2 REG_RSVD_8821C */
+
+/* 2 REG_RSVD_8821C */
+
+/* 2 REG_RSVD_8821C */
+
+/* 2 REG_RSVD_8821C */
+
+/* 2 REG_RSVD_8821C */
+
+/* 2 REG_RSVD_8821C */
+
+/* 2 REG_RSVD_8821C */
+
+/* 2 REG_RSVD_8821C */
+
+/* 2 REG_RSVD_8821C */
+
+/* 2 REG_RSVD_8821C */
+
+/* 2 REG_RSVD_8821C */
+
+/* 2 REG_RSVD_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_MACID1_8821C */
+
+#define BIT_SHIFT_MACID1_0_8821C 0
+#define BIT_MASK_MACID1_0_8821C 0xffffffffL
+#define BIT_MACID1_0_8821C(x)                                                  \
+	(((x) & BIT_MASK_MACID1_0_8821C) << BIT_SHIFT_MACID1_0_8821C)
+#define BITS_MACID1_0_8821C                                                    \
+	(BIT_MASK_MACID1_0_8821C << BIT_SHIFT_MACID1_0_8821C)
+#define BIT_CLEAR_MACID1_0_8821C(x) ((x) & (~BITS_MACID1_0_8821C))
+#define BIT_GET_MACID1_0_8821C(x)                                              \
+	(((x) >> BIT_SHIFT_MACID1_0_8821C) & BIT_MASK_MACID1_0_8821C)
+#define BIT_SET_MACID1_0_8821C(x, v)                                           \
+	(BIT_CLEAR_MACID1_0_8821C(x) | BIT_MACID1_0_8821C(v))
+
+/* 2 REG_MACID1_1_8821C */
+
+#define BIT_SHIFT_MACID1_1_8821C 0
+#define BIT_MASK_MACID1_1_8821C 0xffff
+#define BIT_MACID1_1_8821C(x)                                                  \
+	(((x) & BIT_MASK_MACID1_1_8821C) << BIT_SHIFT_MACID1_1_8821C)
+#define BITS_MACID1_1_8821C                                                    \
+	(BIT_MASK_MACID1_1_8821C << BIT_SHIFT_MACID1_1_8821C)
+#define BIT_CLEAR_MACID1_1_8821C(x) ((x) & (~BITS_MACID1_1_8821C))
+#define BIT_GET_MACID1_1_8821C(x)                                              \
+	(((x) >> BIT_SHIFT_MACID1_1_8821C) & BIT_MASK_MACID1_1_8821C)
+#define BIT_SET_MACID1_1_8821C(x, v)                                           \
+	(BIT_CLEAR_MACID1_1_8821C(x) | BIT_MACID1_1_8821C(v))
+
+/* 2 REG_BSSID1_8821C */
+
+#define BIT_SHIFT_BSSID1_0_8821C 0
+#define BIT_MASK_BSSID1_0_8821C 0xffffffffL
+#define BIT_BSSID1_0_8821C(x)                                                  \
+	(((x) & BIT_MASK_BSSID1_0_8821C) << BIT_SHIFT_BSSID1_0_8821C)
+#define BITS_BSSID1_0_8821C                                                    \
+	(BIT_MASK_BSSID1_0_8821C << BIT_SHIFT_BSSID1_0_8821C)
+#define BIT_CLEAR_BSSID1_0_8821C(x) ((x) & (~BITS_BSSID1_0_8821C))
+#define BIT_GET_BSSID1_0_8821C(x)                                              \
+	(((x) >> BIT_SHIFT_BSSID1_0_8821C) & BIT_MASK_BSSID1_0_8821C)
+#define BIT_SET_BSSID1_0_8821C(x, v)                                           \
+	(BIT_CLEAR_BSSID1_0_8821C(x) | BIT_BSSID1_0_8821C(v))
+
+/* 2 REG_BSSID1_1_8821C */
+
+#define BIT_SHIFT_BSSID1_1_8821C 0
+#define BIT_MASK_BSSID1_1_8821C 0xffff
+#define BIT_BSSID1_1_8821C(x)                                                  \
+	(((x) & BIT_MASK_BSSID1_1_8821C) << BIT_SHIFT_BSSID1_1_8821C)
+#define BITS_BSSID1_1_8821C                                                    \
+	(BIT_MASK_BSSID1_1_8821C << BIT_SHIFT_BSSID1_1_8821C)
+#define BIT_CLEAR_BSSID1_1_8821C(x) ((x) & (~BITS_BSSID1_1_8821C))
+#define BIT_GET_BSSID1_1_8821C(x)                                              \
+	(((x) >> BIT_SHIFT_BSSID1_1_8821C) & BIT_MASK_BSSID1_1_8821C)
+#define BIT_SET_BSSID1_1_8821C(x, v)                                           \
+	(BIT_CLEAR_BSSID1_1_8821C(x) | BIT_BSSID1_1_8821C(v))
+
+/* 2 REG_BCN_PSR_RPT1_8821C */
+
+#define BIT_SHIFT_DTIM_CNT1_8821C 24
+#define BIT_MASK_DTIM_CNT1_8821C 0xff
+#define BIT_DTIM_CNT1_8821C(x)                                                 \
+	(((x) & BIT_MASK_DTIM_CNT1_8821C) << BIT_SHIFT_DTIM_CNT1_8821C)
+#define BITS_DTIM_CNT1_8821C                                                   \
+	(BIT_MASK_DTIM_CNT1_8821C << BIT_SHIFT_DTIM_CNT1_8821C)
+#define BIT_CLEAR_DTIM_CNT1_8821C(x) ((x) & (~BITS_DTIM_CNT1_8821C))
+#define BIT_GET_DTIM_CNT1_8821C(x)                                             \
+	(((x) >> BIT_SHIFT_DTIM_CNT1_8821C) & BIT_MASK_DTIM_CNT1_8821C)
+#define BIT_SET_DTIM_CNT1_8821C(x, v)                                          \
+	(BIT_CLEAR_DTIM_CNT1_8821C(x) | BIT_DTIM_CNT1_8821C(v))
+
+#define BIT_SHIFT_DTIM_PERIOD1_8821C 16
+#define BIT_MASK_DTIM_PERIOD1_8821C 0xff
+#define BIT_DTIM_PERIOD1_8821C(x)                                              \
+	(((x) & BIT_MASK_DTIM_PERIOD1_8821C) << BIT_SHIFT_DTIM_PERIOD1_8821C)
+#define BITS_DTIM_PERIOD1_8821C                                                \
+	(BIT_MASK_DTIM_PERIOD1_8821C << BIT_SHIFT_DTIM_PERIOD1_8821C)
+#define BIT_CLEAR_DTIM_PERIOD1_8821C(x) ((x) & (~BITS_DTIM_PERIOD1_8821C))
+#define BIT_GET_DTIM_PERIOD1_8821C(x)                                          \
+	(((x) >> BIT_SHIFT_DTIM_PERIOD1_8821C) & BIT_MASK_DTIM_PERIOD1_8821C)
+#define BIT_SET_DTIM_PERIOD1_8821C(x, v)                                       \
+	(BIT_CLEAR_DTIM_PERIOD1_8821C(x) | BIT_DTIM_PERIOD1_8821C(v))
+
+#define BIT_DTIM1_8821C BIT(15)
+#define BIT_TIM1_8821C BIT(14)
+
+#define BIT_SHIFT_PS_AID_1_8821C 0
+#define BIT_MASK_PS_AID_1_8821C 0x7ff
+#define BIT_PS_AID_1_8821C(x)                                                  \
+	(((x) & BIT_MASK_PS_AID_1_8821C) << BIT_SHIFT_PS_AID_1_8821C)
+#define BITS_PS_AID_1_8821C                                                    \
+	(BIT_MASK_PS_AID_1_8821C << BIT_SHIFT_PS_AID_1_8821C)
+#define BIT_CLEAR_PS_AID_1_8821C(x) ((x) & (~BITS_PS_AID_1_8821C))
+#define BIT_GET_PS_AID_1_8821C(x)                                              \
+	(((x) >> BIT_SHIFT_PS_AID_1_8821C) & BIT_MASK_PS_AID_1_8821C)
+#define BIT_SET_PS_AID_1_8821C(x, v)                                           \
+	(BIT_CLEAR_PS_AID_1_8821C(x) | BIT_PS_AID_1_8821C(v))
+
+/* 2 REG_ASSOCIATED_BFMEE_SEL_8821C */
+#define BIT_TXUSER_ID1_8821C BIT(25)
+
+#define BIT_SHIFT_AID1_8821C 16
+#define BIT_MASK_AID1_8821C 0x1ff
+#define BIT_AID1_8821C(x) (((x) & BIT_MASK_AID1_8821C) << BIT_SHIFT_AID1_8821C)
+#define BITS_AID1_8821C (BIT_MASK_AID1_8821C << BIT_SHIFT_AID1_8821C)
+#define BIT_CLEAR_AID1_8821C(x) ((x) & (~BITS_AID1_8821C))
+#define BIT_GET_AID1_8821C(x)                                                  \
+	(((x) >> BIT_SHIFT_AID1_8821C) & BIT_MASK_AID1_8821C)
+#define BIT_SET_AID1_8821C(x, v) (BIT_CLEAR_AID1_8821C(x) | BIT_AID1_8821C(v))
+
+#define BIT_TXUSER_ID0_8821C BIT(9)
+
+#define BIT_SHIFT_AID0_8821C 0
+#define BIT_MASK_AID0_8821C 0x1ff
+#define BIT_AID0_8821C(x) (((x) & BIT_MASK_AID0_8821C) << BIT_SHIFT_AID0_8821C)
+#define BITS_AID0_8821C (BIT_MASK_AID0_8821C << BIT_SHIFT_AID0_8821C)
+#define BIT_CLEAR_AID0_8821C(x) ((x) & (~BITS_AID0_8821C))
+#define BIT_GET_AID0_8821C(x)                                                  \
+	(((x) >> BIT_SHIFT_AID0_8821C) & BIT_MASK_AID0_8821C)
+#define BIT_SET_AID0_8821C(x, v) (BIT_CLEAR_AID0_8821C(x) | BIT_AID0_8821C(v))
+
+/* 2 REG_SND_PTCL_CTRL_8821C */
+
+#define BIT_SHIFT_NDP_RX_STANDBY_TIMER_8821C 24
+#define BIT_MASK_NDP_RX_STANDBY_TIMER_8821C 0xff
+#define BIT_NDP_RX_STANDBY_TIMER_8821C(x)                                      \
+	(((x) & BIT_MASK_NDP_RX_STANDBY_TIMER_8821C)                           \
+	 << BIT_SHIFT_NDP_RX_STANDBY_TIMER_8821C)
+#define BITS_NDP_RX_STANDBY_TIMER_8821C                                        \
+	(BIT_MASK_NDP_RX_STANDBY_TIMER_8821C                                   \
+	 << BIT_SHIFT_NDP_RX_STANDBY_TIMER_8821C)
+#define BIT_CLEAR_NDP_RX_STANDBY_TIMER_8821C(x)                                \
+	((x) & (~BITS_NDP_RX_STANDBY_TIMER_8821C))
+#define BIT_GET_NDP_RX_STANDBY_TIMER_8821C(x)                                  \
+	(((x) >> BIT_SHIFT_NDP_RX_STANDBY_TIMER_8821C) &                       \
+	 BIT_MASK_NDP_RX_STANDBY_TIMER_8821C)
+#define BIT_SET_NDP_RX_STANDBY_TIMER_8821C(x, v)                               \
+	(BIT_CLEAR_NDP_RX_STANDBY_TIMER_8821C(x) |                             \
+	 BIT_NDP_RX_STANDBY_TIMER_8821C(v))
+
+#define BIT_SHIFT_CSI_RPT_OFFSET_HT_8821C 16
+#define BIT_MASK_CSI_RPT_OFFSET_HT_8821C 0xff
+#define BIT_CSI_RPT_OFFSET_HT_8821C(x)                                         \
+	(((x) & BIT_MASK_CSI_RPT_OFFSET_HT_8821C)                              \
+	 << BIT_SHIFT_CSI_RPT_OFFSET_HT_8821C)
+#define BITS_CSI_RPT_OFFSET_HT_8821C                                           \
+	(BIT_MASK_CSI_RPT_OFFSET_HT_8821C << BIT_SHIFT_CSI_RPT_OFFSET_HT_8821C)
+#define BIT_CLEAR_CSI_RPT_OFFSET_HT_8821C(x)                                   \
+	((x) & (~BITS_CSI_RPT_OFFSET_HT_8821C))
+#define BIT_GET_CSI_RPT_OFFSET_HT_8821C(x)                                     \
+	(((x) >> BIT_SHIFT_CSI_RPT_OFFSET_HT_8821C) &                          \
+	 BIT_MASK_CSI_RPT_OFFSET_HT_8821C)
+#define BIT_SET_CSI_RPT_OFFSET_HT_8821C(x, v)                                  \
+	(BIT_CLEAR_CSI_RPT_OFFSET_HT_8821C(x) | BIT_CSI_RPT_OFFSET_HT_8821C(v))
+
+#define BIT_SHIFT_R_WMAC_VHT_CATEGORY_8821C 8
+#define BIT_MASK_R_WMAC_VHT_CATEGORY_8821C 0xff
+#define BIT_R_WMAC_VHT_CATEGORY_8821C(x)                                       \
+	(((x) & BIT_MASK_R_WMAC_VHT_CATEGORY_8821C)                            \
+	 << BIT_SHIFT_R_WMAC_VHT_CATEGORY_8821C)
+#define BITS_R_WMAC_VHT_CATEGORY_8821C                                         \
+	(BIT_MASK_R_WMAC_VHT_CATEGORY_8821C                                    \
+	 << BIT_SHIFT_R_WMAC_VHT_CATEGORY_8821C)
+#define BIT_CLEAR_R_WMAC_VHT_CATEGORY_8821C(x)                                 \
+	((x) & (~BITS_R_WMAC_VHT_CATEGORY_8821C))
+#define BIT_GET_R_WMAC_VHT_CATEGORY_8821C(x)                                   \
+	(((x) >> BIT_SHIFT_R_WMAC_VHT_CATEGORY_8821C) &                        \
+	 BIT_MASK_R_WMAC_VHT_CATEGORY_8821C)
+#define BIT_SET_R_WMAC_VHT_CATEGORY_8821C(x, v)                                \
+	(BIT_CLEAR_R_WMAC_VHT_CATEGORY_8821C(x) |                              \
+	 BIT_R_WMAC_VHT_CATEGORY_8821C(v))
+
+#define BIT_R_WMAC_USE_NSTS_8821C BIT(7)
+#define BIT_R_DISABLE_CHECK_VHTSIGB_CRC_8821C BIT(6)
+#define BIT_R_DISABLE_CHECK_VHTSIGA_CRC_8821C BIT(5)
+#define BIT_R_WMAC_BFPARAM_SEL_8821C BIT(4)
+#define BIT_R_WMAC_CSISEQ_SEL_8821C BIT(3)
+#define BIT_R_WMAC_CSI_WITHHTC_EN_8821C BIT(2)
+#define BIT_R_WMAC_HT_NDPA_EN_8821C BIT(1)
+#define BIT_R_WMAC_VHT_NDPA_EN_8821C BIT(0)
+
+/* 2 REG_RX_CSI_RPT_INFO_8821C */
+
+/* 2 REG_NS_ARP_CTRL_8821C */
+#define BIT_R_WMAC_NSARP_RSPEN_8821C BIT(15)
+#define BIT_R_WMAC_NSARP_RARP_8821C BIT(9)
+#define BIT_R_WMAC_NSARP_RIPV6_8821C BIT(8)
+
+#define BIT_SHIFT_R_WMAC_NSARP_MODEN_8821C 6
+#define BIT_MASK_R_WMAC_NSARP_MODEN_8821C 0x3
+#define BIT_R_WMAC_NSARP_MODEN_8821C(x)                                        \
+	(((x) & BIT_MASK_R_WMAC_NSARP_MODEN_8821C)                             \
+	 << BIT_SHIFT_R_WMAC_NSARP_MODEN_8821C)
+#define BITS_R_WMAC_NSARP_MODEN_8821C                                          \
+	(BIT_MASK_R_WMAC_NSARP_MODEN_8821C                                     \
+	 << BIT_SHIFT_R_WMAC_NSARP_MODEN_8821C)
+#define BIT_CLEAR_R_WMAC_NSARP_MODEN_8821C(x)                                  \
+	((x) & (~BITS_R_WMAC_NSARP_MODEN_8821C))
+#define BIT_GET_R_WMAC_NSARP_MODEN_8821C(x)                                    \
+	(((x) >> BIT_SHIFT_R_WMAC_NSARP_MODEN_8821C) &                         \
+	 BIT_MASK_R_WMAC_NSARP_MODEN_8821C)
+#define BIT_SET_R_WMAC_NSARP_MODEN_8821C(x, v)                                 \
+	(BIT_CLEAR_R_WMAC_NSARP_MODEN_8821C(x) |                               \
+	 BIT_R_WMAC_NSARP_MODEN_8821C(v))
+
+#define BIT_SHIFT_R_WMAC_NSARP_RSPFTP_8821C 4
+#define BIT_MASK_R_WMAC_NSARP_RSPFTP_8821C 0x3
+#define BIT_R_WMAC_NSARP_RSPFTP_8821C(x)                                       \
+	(((x) & BIT_MASK_R_WMAC_NSARP_RSPFTP_8821C)                            \
+	 << BIT_SHIFT_R_WMAC_NSARP_RSPFTP_8821C)
+#define BITS_R_WMAC_NSARP_RSPFTP_8821C                                         \
+	(BIT_MASK_R_WMAC_NSARP_RSPFTP_8821C                                    \
+	 << BIT_SHIFT_R_WMAC_NSARP_RSPFTP_8821C)
+#define BIT_CLEAR_R_WMAC_NSARP_RSPFTP_8821C(x)                                 \
+	((x) & (~BITS_R_WMAC_NSARP_RSPFTP_8821C))
+#define BIT_GET_R_WMAC_NSARP_RSPFTP_8821C(x)                                   \
+	(((x) >> BIT_SHIFT_R_WMAC_NSARP_RSPFTP_8821C) &                        \
+	 BIT_MASK_R_WMAC_NSARP_RSPFTP_8821C)
+#define BIT_SET_R_WMAC_NSARP_RSPFTP_8821C(x, v)                                \
+	(BIT_CLEAR_R_WMAC_NSARP_RSPFTP_8821C(x) |                              \
+	 BIT_R_WMAC_NSARP_RSPFTP_8821C(v))
+
+#define BIT_SHIFT_R_WMAC_NSARP_RSPSEC_8821C 0
+#define BIT_MASK_R_WMAC_NSARP_RSPSEC_8821C 0xf
+#define BIT_R_WMAC_NSARP_RSPSEC_8821C(x)                                       \
+	(((x) & BIT_MASK_R_WMAC_NSARP_RSPSEC_8821C)                            \
+	 << BIT_SHIFT_R_WMAC_NSARP_RSPSEC_8821C)
+#define BITS_R_WMAC_NSARP_RSPSEC_8821C                                         \
+	(BIT_MASK_R_WMAC_NSARP_RSPSEC_8821C                                    \
+	 << BIT_SHIFT_R_WMAC_NSARP_RSPSEC_8821C)
+#define BIT_CLEAR_R_WMAC_NSARP_RSPSEC_8821C(x)                                 \
+	((x) & (~BITS_R_WMAC_NSARP_RSPSEC_8821C))
+#define BIT_GET_R_WMAC_NSARP_RSPSEC_8821C(x)                                   \
+	(((x) >> BIT_SHIFT_R_WMAC_NSARP_RSPSEC_8821C) &                        \
+	 BIT_MASK_R_WMAC_NSARP_RSPSEC_8821C)
+#define BIT_SET_R_WMAC_NSARP_RSPSEC_8821C(x, v)                                \
+	(BIT_CLEAR_R_WMAC_NSARP_RSPSEC_8821C(x) |                              \
+	 BIT_R_WMAC_NSARP_RSPSEC_8821C(v))
+
+/* 2 REG_NS_ARP_INFO_8821C */
+#define BIT_REQ_IS_MCNS_8821C BIT(23)
+#define BIT_REQ_IS_UCNS_8821C BIT(22)
+#define BIT_REQ_IS_USNS_8821C BIT(21)
+#define BIT_REQ_IS_ARP_8821C BIT(20)
+#define BIT_EXPRSP_MH_WITHQC_8821C BIT(19)
+
+#define BIT_SHIFT_EXPRSP_SECTYPE_8821C 16
+#define BIT_MASK_EXPRSP_SECTYPE_8821C 0x7
+#define BIT_EXPRSP_SECTYPE_8821C(x)                                            \
+	(((x) & BIT_MASK_EXPRSP_SECTYPE_8821C)                                 \
+	 << BIT_SHIFT_EXPRSP_SECTYPE_8821C)
+#define BITS_EXPRSP_SECTYPE_8821C                                              \
+	(BIT_MASK_EXPRSP_SECTYPE_8821C << BIT_SHIFT_EXPRSP_SECTYPE_8821C)
+#define BIT_CLEAR_EXPRSP_SECTYPE_8821C(x) ((x) & (~BITS_EXPRSP_SECTYPE_8821C))
+#define BIT_GET_EXPRSP_SECTYPE_8821C(x)                                        \
+	(((x) >> BIT_SHIFT_EXPRSP_SECTYPE_8821C) &                             \
+	 BIT_MASK_EXPRSP_SECTYPE_8821C)
+#define BIT_SET_EXPRSP_SECTYPE_8821C(x, v)                                     \
+	(BIT_CLEAR_EXPRSP_SECTYPE_8821C(x) | BIT_EXPRSP_SECTYPE_8821C(v))
+
+#define BIT_SHIFT_EXPRSP_CHKSM_7_TO_0_8821C 8
+#define BIT_MASK_EXPRSP_CHKSM_7_TO_0_8821C 0xff
+#define BIT_EXPRSP_CHKSM_7_TO_0_8821C(x)                                       \
+	(((x) & BIT_MASK_EXPRSP_CHKSM_7_TO_0_8821C)                            \
+	 << BIT_SHIFT_EXPRSP_CHKSM_7_TO_0_8821C)
+#define BITS_EXPRSP_CHKSM_7_TO_0_8821C                                         \
+	(BIT_MASK_EXPRSP_CHKSM_7_TO_0_8821C                                    \
+	 << BIT_SHIFT_EXPRSP_CHKSM_7_TO_0_8821C)
+#define BIT_CLEAR_EXPRSP_CHKSM_7_TO_0_8821C(x)                                 \
+	((x) & (~BITS_EXPRSP_CHKSM_7_TO_0_8821C))
+#define BIT_GET_EXPRSP_CHKSM_7_TO_0_8821C(x)                                   \
+	(((x) >> BIT_SHIFT_EXPRSP_CHKSM_7_TO_0_8821C) &                        \
+	 BIT_MASK_EXPRSP_CHKSM_7_TO_0_8821C)
+#define BIT_SET_EXPRSP_CHKSM_7_TO_0_8821C(x, v)                                \
+	(BIT_CLEAR_EXPRSP_CHKSM_7_TO_0_8821C(x) |                              \
+	 BIT_EXPRSP_CHKSM_7_TO_0_8821C(v))
+
+#define BIT_SHIFT_EXPRSP_CHKSM_15_TO_8_8821C 0
+#define BIT_MASK_EXPRSP_CHKSM_15_TO_8_8821C 0xff
+#define BIT_EXPRSP_CHKSM_15_TO_8_8821C(x)                                      \
+	(((x) & BIT_MASK_EXPRSP_CHKSM_15_TO_8_8821C)                           \
+	 << BIT_SHIFT_EXPRSP_CHKSM_15_TO_8_8821C)
+#define BITS_EXPRSP_CHKSM_15_TO_8_8821C                                        \
+	(BIT_MASK_EXPRSP_CHKSM_15_TO_8_8821C                                   \
+	 << BIT_SHIFT_EXPRSP_CHKSM_15_TO_8_8821C)
+#define BIT_CLEAR_EXPRSP_CHKSM_15_TO_8_8821C(x)                                \
+	((x) & (~BITS_EXPRSP_CHKSM_15_TO_8_8821C))
+#define BIT_GET_EXPRSP_CHKSM_15_TO_8_8821C(x)                                  \
+	(((x) >> BIT_SHIFT_EXPRSP_CHKSM_15_TO_8_8821C) &                       \
+	 BIT_MASK_EXPRSP_CHKSM_15_TO_8_8821C)
+#define BIT_SET_EXPRSP_CHKSM_15_TO_8_8821C(x, v)                               \
+	(BIT_CLEAR_EXPRSP_CHKSM_15_TO_8_8821C(x) |                             \
+	 BIT_EXPRSP_CHKSM_15_TO_8_8821C(v))
+
+/* 2 REG_BEAMFORMING_INFO_NSARP_V1_8821C */
+
+#define BIT_SHIFT_WMAC_ARPIP_8821C 0
+#define BIT_MASK_WMAC_ARPIP_8821C 0xffffffffL
+#define BIT_WMAC_ARPIP_8821C(x)                                                \
+	(((x) & BIT_MASK_WMAC_ARPIP_8821C) << BIT_SHIFT_WMAC_ARPIP_8821C)
+#define BITS_WMAC_ARPIP_8821C                                                  \
+	(BIT_MASK_WMAC_ARPIP_8821C << BIT_SHIFT_WMAC_ARPIP_8821C)
+#define BIT_CLEAR_WMAC_ARPIP_8821C(x) ((x) & (~BITS_WMAC_ARPIP_8821C))
+#define BIT_GET_WMAC_ARPIP_8821C(x)                                            \
+	(((x) >> BIT_SHIFT_WMAC_ARPIP_8821C) & BIT_MASK_WMAC_ARPIP_8821C)
+#define BIT_SET_WMAC_ARPIP_8821C(x, v)                                         \
+	(BIT_CLEAR_WMAC_ARPIP_8821C(x) | BIT_WMAC_ARPIP_8821C(v))
+
+/* 2 REG_BEAMFORMING_INFO_NSARP_8821C */
+
+#define BIT_SHIFT_BEAMFORMING_INFO_8821C 0
+#define BIT_MASK_BEAMFORMING_INFO_8821C 0xffffffffL
+#define BIT_BEAMFORMING_INFO_8821C(x)                                          \
+	(((x) & BIT_MASK_BEAMFORMING_INFO_8821C)                               \
+	 << BIT_SHIFT_BEAMFORMING_INFO_8821C)
+#define BITS_BEAMFORMING_INFO_8821C                                            \
+	(BIT_MASK_BEAMFORMING_INFO_8821C << BIT_SHIFT_BEAMFORMING_INFO_8821C)
+#define BIT_CLEAR_BEAMFORMING_INFO_8821C(x)                                    \
+	((x) & (~BITS_BEAMFORMING_INFO_8821C))
+#define BIT_GET_BEAMFORMING_INFO_8821C(x)                                      \
+	(((x) >> BIT_SHIFT_BEAMFORMING_INFO_8821C) &                           \
+	 BIT_MASK_BEAMFORMING_INFO_8821C)
+#define BIT_SET_BEAMFORMING_INFO_8821C(x, v)                                   \
+	(BIT_CLEAR_BEAMFORMING_INFO_8821C(x) | BIT_BEAMFORMING_INFO_8821C(v))
+
+/* 2 REG_IPV6_8821C */
+
+#define BIT_SHIFT_R_WMAC_IPV6_MYIPAD_0_8821C 0
+#define BIT_MASK_R_WMAC_IPV6_MYIPAD_0_8821C 0xffffffffL
+#define BIT_R_WMAC_IPV6_MYIPAD_0_8821C(x)                                      \
+	(((x) & BIT_MASK_R_WMAC_IPV6_MYIPAD_0_8821C)                           \
+	 << BIT_SHIFT_R_WMAC_IPV6_MYIPAD_0_8821C)
+#define BITS_R_WMAC_IPV6_MYIPAD_0_8821C                                        \
+	(BIT_MASK_R_WMAC_IPV6_MYIPAD_0_8821C                                   \
+	 << BIT_SHIFT_R_WMAC_IPV6_MYIPAD_0_8821C)
+#define BIT_CLEAR_R_WMAC_IPV6_MYIPAD_0_8821C(x)                                \
+	((x) & (~BITS_R_WMAC_IPV6_MYIPAD_0_8821C))
+#define BIT_GET_R_WMAC_IPV6_MYIPAD_0_8821C(x)                                  \
+	(((x) >> BIT_SHIFT_R_WMAC_IPV6_MYIPAD_0_8821C) &                       \
+	 BIT_MASK_R_WMAC_IPV6_MYIPAD_0_8821C)
+#define BIT_SET_R_WMAC_IPV6_MYIPAD_0_8821C(x, v)                               \
+	(BIT_CLEAR_R_WMAC_IPV6_MYIPAD_0_8821C(x) |                             \
+	 BIT_R_WMAC_IPV6_MYIPAD_0_8821C(v))
+
+/* 2 REG_IPV6_1_8821C */
+
+#define BIT_SHIFT_R_WMAC_IPV6_MYIPAD_1_8821C 0
+#define BIT_MASK_R_WMAC_IPV6_MYIPAD_1_8821C 0xffffffffL
+#define BIT_R_WMAC_IPV6_MYIPAD_1_8821C(x)                                      \
+	(((x) & BIT_MASK_R_WMAC_IPV6_MYIPAD_1_8821C)                           \
+	 << BIT_SHIFT_R_WMAC_IPV6_MYIPAD_1_8821C)
+#define BITS_R_WMAC_IPV6_MYIPAD_1_8821C                                        \
+	(BIT_MASK_R_WMAC_IPV6_MYIPAD_1_8821C                                   \
+	 << BIT_SHIFT_R_WMAC_IPV6_MYIPAD_1_8821C)
+#define BIT_CLEAR_R_WMAC_IPV6_MYIPAD_1_8821C(x)                                \
+	((x) & (~BITS_R_WMAC_IPV6_MYIPAD_1_8821C))
+#define BIT_GET_R_WMAC_IPV6_MYIPAD_1_8821C(x)                                  \
+	(((x) >> BIT_SHIFT_R_WMAC_IPV6_MYIPAD_1_8821C) &                       \
+	 BIT_MASK_R_WMAC_IPV6_MYIPAD_1_8821C)
+#define BIT_SET_R_WMAC_IPV6_MYIPAD_1_8821C(x, v)                               \
+	(BIT_CLEAR_R_WMAC_IPV6_MYIPAD_1_8821C(x) |                             \
+	 BIT_R_WMAC_IPV6_MYIPAD_1_8821C(v))
+
+/* 2 REG_IPV6_2_8821C */
+
+#define BIT_SHIFT_R_WMAC_IPV6_MYIPAD_2_8821C 0
+#define BIT_MASK_R_WMAC_IPV6_MYIPAD_2_8821C 0xffffffffL
+#define BIT_R_WMAC_IPV6_MYIPAD_2_8821C(x)                                      \
+	(((x) & BIT_MASK_R_WMAC_IPV6_MYIPAD_2_8821C)                           \
+	 << BIT_SHIFT_R_WMAC_IPV6_MYIPAD_2_8821C)
+#define BITS_R_WMAC_IPV6_MYIPAD_2_8821C                                        \
+	(BIT_MASK_R_WMAC_IPV6_MYIPAD_2_8821C                                   \
+	 << BIT_SHIFT_R_WMAC_IPV6_MYIPAD_2_8821C)
+#define BIT_CLEAR_R_WMAC_IPV6_MYIPAD_2_8821C(x)                                \
+	((x) & (~BITS_R_WMAC_IPV6_MYIPAD_2_8821C))
+#define BIT_GET_R_WMAC_IPV6_MYIPAD_2_8821C(x)                                  \
+	(((x) >> BIT_SHIFT_R_WMAC_IPV6_MYIPAD_2_8821C) &                       \
+	 BIT_MASK_R_WMAC_IPV6_MYIPAD_2_8821C)
+#define BIT_SET_R_WMAC_IPV6_MYIPAD_2_8821C(x, v)                               \
+	(BIT_CLEAR_R_WMAC_IPV6_MYIPAD_2_8821C(x) |                             \
+	 BIT_R_WMAC_IPV6_MYIPAD_2_8821C(v))
+
+/* 2 REG_IPV6_3_8821C */
+
+#define BIT_SHIFT_R_WMAC_IPV6_MYIPAD_3_8821C 0
+#define BIT_MASK_R_WMAC_IPV6_MYIPAD_3_8821C 0xffffffffL
+#define BIT_R_WMAC_IPV6_MYIPAD_3_8821C(x)                                      \
+	(((x) & BIT_MASK_R_WMAC_IPV6_MYIPAD_3_8821C)                           \
+	 << BIT_SHIFT_R_WMAC_IPV6_MYIPAD_3_8821C)
+#define BITS_R_WMAC_IPV6_MYIPAD_3_8821C                                        \
+	(BIT_MASK_R_WMAC_IPV6_MYIPAD_3_8821C                                   \
+	 << BIT_SHIFT_R_WMAC_IPV6_MYIPAD_3_8821C)
+#define BIT_CLEAR_R_WMAC_IPV6_MYIPAD_3_8821C(x)                                \
+	((x) & (~BITS_R_WMAC_IPV6_MYIPAD_3_8821C))
+#define BIT_GET_R_WMAC_IPV6_MYIPAD_3_8821C(x)                                  \
+	(((x) >> BIT_SHIFT_R_WMAC_IPV6_MYIPAD_3_8821C) &                       \
+	 BIT_MASK_R_WMAC_IPV6_MYIPAD_3_8821C)
+#define BIT_SET_R_WMAC_IPV6_MYIPAD_3_8821C(x, v)                               \
+	(BIT_CLEAR_R_WMAC_IPV6_MYIPAD_3_8821C(x) |                             \
+	 BIT_R_WMAC_IPV6_MYIPAD_3_8821C(v))
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_WMAC_RTX_CTX_SUBTYPE_CFG_8821C */
+
+#define BIT_SHIFT_R_WMAC_CTX_SUBTYPE_8821C 4
+#define BIT_MASK_R_WMAC_CTX_SUBTYPE_8821C 0xf
+#define BIT_R_WMAC_CTX_SUBTYPE_8821C(x)                                        \
+	(((x) & BIT_MASK_R_WMAC_CTX_SUBTYPE_8821C)                             \
+	 << BIT_SHIFT_R_WMAC_CTX_SUBTYPE_8821C)
+#define BITS_R_WMAC_CTX_SUBTYPE_8821C                                          \
+	(BIT_MASK_R_WMAC_CTX_SUBTYPE_8821C                                     \
+	 << BIT_SHIFT_R_WMAC_CTX_SUBTYPE_8821C)
+#define BIT_CLEAR_R_WMAC_CTX_SUBTYPE_8821C(x)                                  \
+	((x) & (~BITS_R_WMAC_CTX_SUBTYPE_8821C))
+#define BIT_GET_R_WMAC_CTX_SUBTYPE_8821C(x)                                    \
+	(((x) >> BIT_SHIFT_R_WMAC_CTX_SUBTYPE_8821C) &                         \
+	 BIT_MASK_R_WMAC_CTX_SUBTYPE_8821C)
+#define BIT_SET_R_WMAC_CTX_SUBTYPE_8821C(x, v)                                 \
+	(BIT_CLEAR_R_WMAC_CTX_SUBTYPE_8821C(x) |                               \
+	 BIT_R_WMAC_CTX_SUBTYPE_8821C(v))
+
+#define BIT_SHIFT_R_WMAC_RTX_SUBTYPE_8821C 0
+#define BIT_MASK_R_WMAC_RTX_SUBTYPE_8821C 0xf
+#define BIT_R_WMAC_RTX_SUBTYPE_8821C(x)                                        \
+	(((x) & BIT_MASK_R_WMAC_RTX_SUBTYPE_8821C)                             \
+	 << BIT_SHIFT_R_WMAC_RTX_SUBTYPE_8821C)
+#define BITS_R_WMAC_RTX_SUBTYPE_8821C                                          \
+	(BIT_MASK_R_WMAC_RTX_SUBTYPE_8821C                                     \
+	 << BIT_SHIFT_R_WMAC_RTX_SUBTYPE_8821C)
+#define BIT_CLEAR_R_WMAC_RTX_SUBTYPE_8821C(x)                                  \
+	((x) & (~BITS_R_WMAC_RTX_SUBTYPE_8821C))
+#define BIT_GET_R_WMAC_RTX_SUBTYPE_8821C(x)                                    \
+	(((x) >> BIT_SHIFT_R_WMAC_RTX_SUBTYPE_8821C) &                         \
+	 BIT_MASK_R_WMAC_RTX_SUBTYPE_8821C)
+#define BIT_SET_R_WMAC_RTX_SUBTYPE_8821C(x, v)                                 \
+	(BIT_CLEAR_R_WMAC_RTX_SUBTYPE_8821C(x) |                               \
+	 BIT_R_WMAC_RTX_SUBTYPE_8821C(v))
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_WMAC_SWAES_CFG_8821C */
+
+/* 2 REG_BT_COEX_V2_8821C */
+#define BIT_GNT_BT_POLARITY_8821C BIT(12)
+#define BIT_GNT_BT_BYPASS_PRIORITY_8821C BIT(8)
+
+#define BIT_SHIFT_TIMER_8821C 0
+#define BIT_MASK_TIMER_8821C 0xff
+#define BIT_TIMER_8821C(x)                                                     \
+	(((x) & BIT_MASK_TIMER_8821C) << BIT_SHIFT_TIMER_8821C)
+#define BITS_TIMER_8821C (BIT_MASK_TIMER_8821C << BIT_SHIFT_TIMER_8821C)
+#define BIT_CLEAR_TIMER_8821C(x) ((x) & (~BITS_TIMER_8821C))
+#define BIT_GET_TIMER_8821C(x)                                                 \
+	(((x) >> BIT_SHIFT_TIMER_8821C) & BIT_MASK_TIMER_8821C)
+#define BIT_SET_TIMER_8821C(x, v)                                              \
+	(BIT_CLEAR_TIMER_8821C(x) | BIT_TIMER_8821C(v))
+
+/* 2 REG_BT_COEX_8821C */
+#define BIT_R_GNT_BT_RFC_SW_8821C BIT(12)
+#define BIT_R_GNT_BT_RFC_SW_EN_8821C BIT(11)
+#define BIT_R_GNT_BT_BB_SW_8821C BIT(10)
+#define BIT_R_GNT_BT_BB_SW_EN_8821C BIT(9)
+#define BIT_R_BT_CNT_THREN_8821C BIT(8)
+
+#define BIT_SHIFT_R_BT_CNT_THR_8821C 0
+#define BIT_MASK_R_BT_CNT_THR_8821C 0xff
+#define BIT_R_BT_CNT_THR_8821C(x)                                              \
+	(((x) & BIT_MASK_R_BT_CNT_THR_8821C) << BIT_SHIFT_R_BT_CNT_THR_8821C)
+#define BITS_R_BT_CNT_THR_8821C                                                \
+	(BIT_MASK_R_BT_CNT_THR_8821C << BIT_SHIFT_R_BT_CNT_THR_8821C)
+#define BIT_CLEAR_R_BT_CNT_THR_8821C(x) ((x) & (~BITS_R_BT_CNT_THR_8821C))
+#define BIT_GET_R_BT_CNT_THR_8821C(x)                                          \
+	(((x) >> BIT_SHIFT_R_BT_CNT_THR_8821C) & BIT_MASK_R_BT_CNT_THR_8821C)
+#define BIT_SET_R_BT_CNT_THR_8821C(x, v)                                       \
+	(BIT_CLEAR_R_BT_CNT_THR_8821C(x) | BIT_R_BT_CNT_THR_8821C(v))
+
+/* 2 REG_WLAN_ACT_MASK_CTRL_8821C */
+
+#define BIT_SHIFT_RXMYRTS_NAV_V1_8821C 8
+#define BIT_MASK_RXMYRTS_NAV_V1_8821C 0xff
+#define BIT_RXMYRTS_NAV_V1_8821C(x)                                            \
+	(((x) & BIT_MASK_RXMYRTS_NAV_V1_8821C)                                 \
+	 << BIT_SHIFT_RXMYRTS_NAV_V1_8821C)
+#define BITS_RXMYRTS_NAV_V1_8821C                                              \
+	(BIT_MASK_RXMYRTS_NAV_V1_8821C << BIT_SHIFT_RXMYRTS_NAV_V1_8821C)
+#define BIT_CLEAR_RXMYRTS_NAV_V1_8821C(x) ((x) & (~BITS_RXMYRTS_NAV_V1_8821C))
+#define BIT_GET_RXMYRTS_NAV_V1_8821C(x)                                        \
+	(((x) >> BIT_SHIFT_RXMYRTS_NAV_V1_8821C) &                             \
+	 BIT_MASK_RXMYRTS_NAV_V1_8821C)
+#define BIT_SET_RXMYRTS_NAV_V1_8821C(x, v)                                     \
+	(BIT_CLEAR_RXMYRTS_NAV_V1_8821C(x) | BIT_RXMYRTS_NAV_V1_8821C(v))
+
+#define BIT_SHIFT_RTSRST_V1_8821C 0
+#define BIT_MASK_RTSRST_V1_8821C 0xff
+#define BIT_RTSRST_V1_8821C(x)                                                 \
+	(((x) & BIT_MASK_RTSRST_V1_8821C) << BIT_SHIFT_RTSRST_V1_8821C)
+#define BITS_RTSRST_V1_8821C                                                   \
+	(BIT_MASK_RTSRST_V1_8821C << BIT_SHIFT_RTSRST_V1_8821C)
+#define BIT_CLEAR_RTSRST_V1_8821C(x) ((x) & (~BITS_RTSRST_V1_8821C))
+#define BIT_GET_RTSRST_V1_8821C(x)                                             \
+	(((x) >> BIT_SHIFT_RTSRST_V1_8821C) & BIT_MASK_RTSRST_V1_8821C)
+#define BIT_SET_RTSRST_V1_8821C(x, v)                                          \
+	(BIT_CLEAR_RTSRST_V1_8821C(x) | BIT_RTSRST_V1_8821C(v))
+
+/* 2 REG_WLAN_ACT_MASK_CTRL_1_8821C */
+#define BIT_WLRX_TER_BY_CTL_1_8821C BIT(11)
+#define BIT_WLRX_TER_BY_AD_1_8821C BIT(10)
+#define BIT_ANT_DIVERSITY_SEL_1_8821C BIT(9)
+#define BIT_ANTSEL_FOR_BT_CTRL_EN_1_8821C BIT(8)
+#define BIT_WLACT_LOW_GNTWL_EN_1_8821C BIT(2)
+#define BIT_WLACT_HIGH_GNTBT_EN_1_8821C BIT(1)
+#define BIT_NAV_UPPER_1_V1_8821C BIT(0)
+
+/* 2 REG_BT_COEX_ENHANCED_INTR_CTRL_8821C */
+
+#define BIT_SHIFT_BT_STAT_DELAY_8821C 12
+#define BIT_MASK_BT_STAT_DELAY_8821C 0xf
+#define BIT_BT_STAT_DELAY_8821C(x)                                             \
+	(((x) & BIT_MASK_BT_STAT_DELAY_8821C) << BIT_SHIFT_BT_STAT_DELAY_8821C)
+#define BITS_BT_STAT_DELAY_8821C                                               \
+	(BIT_MASK_BT_STAT_DELAY_8821C << BIT_SHIFT_BT_STAT_DELAY_8821C)
+#define BIT_CLEAR_BT_STAT_DELAY_8821C(x) ((x) & (~BITS_BT_STAT_DELAY_8821C))
+#define BIT_GET_BT_STAT_DELAY_8821C(x)                                         \
+	(((x) >> BIT_SHIFT_BT_STAT_DELAY_8821C) & BIT_MASK_BT_STAT_DELAY_8821C)
+#define BIT_SET_BT_STAT_DELAY_8821C(x, v)                                      \
+	(BIT_CLEAR_BT_STAT_DELAY_8821C(x) | BIT_BT_STAT_DELAY_8821C(v))
+
+#define BIT_SHIFT_BT_TRX_INIT_DETECT_8821C 8
+#define BIT_MASK_BT_TRX_INIT_DETECT_8821C 0xf
+#define BIT_BT_TRX_INIT_DETECT_8821C(x)                                        \
+	(((x) & BIT_MASK_BT_TRX_INIT_DETECT_8821C)                             \
+	 << BIT_SHIFT_BT_TRX_INIT_DETECT_8821C)
+#define BITS_BT_TRX_INIT_DETECT_8821C                                          \
+	(BIT_MASK_BT_TRX_INIT_DETECT_8821C                                     \
+	 << BIT_SHIFT_BT_TRX_INIT_DETECT_8821C)
+#define BIT_CLEAR_BT_TRX_INIT_DETECT_8821C(x)                                  \
+	((x) & (~BITS_BT_TRX_INIT_DETECT_8821C))
+#define BIT_GET_BT_TRX_INIT_DETECT_8821C(x)                                    \
+	(((x) >> BIT_SHIFT_BT_TRX_INIT_DETECT_8821C) &                         \
+	 BIT_MASK_BT_TRX_INIT_DETECT_8821C)
+#define BIT_SET_BT_TRX_INIT_DETECT_8821C(x, v)                                 \
+	(BIT_CLEAR_BT_TRX_INIT_DETECT_8821C(x) |                               \
+	 BIT_BT_TRX_INIT_DETECT_8821C(v))
+
+#define BIT_SHIFT_BT_PRI_DETECT_TO_8821C 4
+#define BIT_MASK_BT_PRI_DETECT_TO_8821C 0xf
+#define BIT_BT_PRI_DETECT_TO_8821C(x)                                          \
+	(((x) & BIT_MASK_BT_PRI_DETECT_TO_8821C)                               \
+	 << BIT_SHIFT_BT_PRI_DETECT_TO_8821C)
+#define BITS_BT_PRI_DETECT_TO_8821C                                            \
+	(BIT_MASK_BT_PRI_DETECT_TO_8821C << BIT_SHIFT_BT_PRI_DETECT_TO_8821C)
+#define BIT_CLEAR_BT_PRI_DETECT_TO_8821C(x)                                    \
+	((x) & (~BITS_BT_PRI_DETECT_TO_8821C))
+#define BIT_GET_BT_PRI_DETECT_TO_8821C(x)                                      \
+	(((x) >> BIT_SHIFT_BT_PRI_DETECT_TO_8821C) &                           \
+	 BIT_MASK_BT_PRI_DETECT_TO_8821C)
+#define BIT_SET_BT_PRI_DETECT_TO_8821C(x, v)                                   \
+	(BIT_CLEAR_BT_PRI_DETECT_TO_8821C(x) | BIT_BT_PRI_DETECT_TO_8821C(v))
+
+#define BIT_R_GRANTALL_WLMASK_8821C BIT(3)
+#define BIT_STATIS_BT_EN_8821C BIT(2)
+#define BIT_WL_ACT_MASK_ENABLE_8821C BIT(1)
+#define BIT_ENHANCED_BT_8821C BIT(0)
+
+/* 2 REG_BT_ACT_STATISTICS_8821C */
+
+#define BIT_SHIFT_STATIS_BT_HI_RX_8821C 16
+#define BIT_MASK_STATIS_BT_HI_RX_8821C 0xffff
+#define BIT_STATIS_BT_HI_RX_8821C(x)                                           \
+	(((x) & BIT_MASK_STATIS_BT_HI_RX_8821C)                                \
+	 << BIT_SHIFT_STATIS_BT_HI_RX_8821C)
+#define BITS_STATIS_BT_HI_RX_8821C                                             \
+	(BIT_MASK_STATIS_BT_HI_RX_8821C << BIT_SHIFT_STATIS_BT_HI_RX_8821C)
+#define BIT_CLEAR_STATIS_BT_HI_RX_8821C(x) ((x) & (~BITS_STATIS_BT_HI_RX_8821C))
+#define BIT_GET_STATIS_BT_HI_RX_8821C(x)                                       \
+	(((x) >> BIT_SHIFT_STATIS_BT_HI_RX_8821C) &                            \
+	 BIT_MASK_STATIS_BT_HI_RX_8821C)
+#define BIT_SET_STATIS_BT_HI_RX_8821C(x, v)                                    \
+	(BIT_CLEAR_STATIS_BT_HI_RX_8821C(x) | BIT_STATIS_BT_HI_RX_8821C(v))
+
+#define BIT_SHIFT_STATIS_BT_HI_TX_8821C 0
+#define BIT_MASK_STATIS_BT_HI_TX_8821C 0xffff
+#define BIT_STATIS_BT_HI_TX_8821C(x)                                           \
+	(((x) & BIT_MASK_STATIS_BT_HI_TX_8821C)                                \
+	 << BIT_SHIFT_STATIS_BT_HI_TX_8821C)
+#define BITS_STATIS_BT_HI_TX_8821C                                             \
+	(BIT_MASK_STATIS_BT_HI_TX_8821C << BIT_SHIFT_STATIS_BT_HI_TX_8821C)
+#define BIT_CLEAR_STATIS_BT_HI_TX_8821C(x) ((x) & (~BITS_STATIS_BT_HI_TX_8821C))
+#define BIT_GET_STATIS_BT_HI_TX_8821C(x)                                       \
+	(((x) >> BIT_SHIFT_STATIS_BT_HI_TX_8821C) &                            \
+	 BIT_MASK_STATIS_BT_HI_TX_8821C)
+#define BIT_SET_STATIS_BT_HI_TX_8821C(x, v)                                    \
+	(BIT_CLEAR_STATIS_BT_HI_TX_8821C(x) | BIT_STATIS_BT_HI_TX_8821C(v))
+
+/* 2 REG_BT_ACT_STATISTICS_1_8821C */
+
+#define BIT_SHIFT_STATIS_BT_LO_RX_1_8821C 16
+#define BIT_MASK_STATIS_BT_LO_RX_1_8821C 0xffff
+#define BIT_STATIS_BT_LO_RX_1_8821C(x)                                         \
+	(((x) & BIT_MASK_STATIS_BT_LO_RX_1_8821C)                              \
+	 << BIT_SHIFT_STATIS_BT_LO_RX_1_8821C)
+#define BITS_STATIS_BT_LO_RX_1_8821C                                           \
+	(BIT_MASK_STATIS_BT_LO_RX_1_8821C << BIT_SHIFT_STATIS_BT_LO_RX_1_8821C)
+#define BIT_CLEAR_STATIS_BT_LO_RX_1_8821C(x)                                   \
+	((x) & (~BITS_STATIS_BT_LO_RX_1_8821C))
+#define BIT_GET_STATIS_BT_LO_RX_1_8821C(x)                                     \
+	(((x) >> BIT_SHIFT_STATIS_BT_LO_RX_1_8821C) &                          \
+	 BIT_MASK_STATIS_BT_LO_RX_1_8821C)
+#define BIT_SET_STATIS_BT_LO_RX_1_8821C(x, v)                                  \
+	(BIT_CLEAR_STATIS_BT_LO_RX_1_8821C(x) | BIT_STATIS_BT_LO_RX_1_8821C(v))
+
+#define BIT_SHIFT_STATIS_BT_LO_TX_1_8821C 0
+#define BIT_MASK_STATIS_BT_LO_TX_1_8821C 0xffff
+#define BIT_STATIS_BT_LO_TX_1_8821C(x)                                         \
+	(((x) & BIT_MASK_STATIS_BT_LO_TX_1_8821C)                              \
+	 << BIT_SHIFT_STATIS_BT_LO_TX_1_8821C)
+#define BITS_STATIS_BT_LO_TX_1_8821C                                           \
+	(BIT_MASK_STATIS_BT_LO_TX_1_8821C << BIT_SHIFT_STATIS_BT_LO_TX_1_8821C)
+#define BIT_CLEAR_STATIS_BT_LO_TX_1_8821C(x)                                   \
+	((x) & (~BITS_STATIS_BT_LO_TX_1_8821C))
+#define BIT_GET_STATIS_BT_LO_TX_1_8821C(x)                                     \
+	(((x) >> BIT_SHIFT_STATIS_BT_LO_TX_1_8821C) &                          \
+	 BIT_MASK_STATIS_BT_LO_TX_1_8821C)
+#define BIT_SET_STATIS_BT_LO_TX_1_8821C(x, v)                                  \
+	(BIT_CLEAR_STATIS_BT_LO_TX_1_8821C(x) | BIT_STATIS_BT_LO_TX_1_8821C(v))
+
+/* 2 REG_BT_STATISTICS_CONTROL_REGISTER_8821C */
+
+#define BIT_SHIFT_R_BT_CMD_RPT_8821C 16
+#define BIT_MASK_R_BT_CMD_RPT_8821C 0xffff
+#define BIT_R_BT_CMD_RPT_8821C(x)                                              \
+	(((x) & BIT_MASK_R_BT_CMD_RPT_8821C) << BIT_SHIFT_R_BT_CMD_RPT_8821C)
+#define BITS_R_BT_CMD_RPT_8821C                                                \
+	(BIT_MASK_R_BT_CMD_RPT_8821C << BIT_SHIFT_R_BT_CMD_RPT_8821C)
+#define BIT_CLEAR_R_BT_CMD_RPT_8821C(x) ((x) & (~BITS_R_BT_CMD_RPT_8821C))
+#define BIT_GET_R_BT_CMD_RPT_8821C(x)                                          \
+	(((x) >> BIT_SHIFT_R_BT_CMD_RPT_8821C) & BIT_MASK_R_BT_CMD_RPT_8821C)
+#define BIT_SET_R_BT_CMD_RPT_8821C(x, v)                                       \
+	(BIT_CLEAR_R_BT_CMD_RPT_8821C(x) | BIT_R_BT_CMD_RPT_8821C(v))
+
+#define BIT_SHIFT_R_RPT_FROM_BT_8821C 8
+#define BIT_MASK_R_RPT_FROM_BT_8821C 0xff
+#define BIT_R_RPT_FROM_BT_8821C(x)                                             \
+	(((x) & BIT_MASK_R_RPT_FROM_BT_8821C) << BIT_SHIFT_R_RPT_FROM_BT_8821C)
+#define BITS_R_RPT_FROM_BT_8821C                                               \
+	(BIT_MASK_R_RPT_FROM_BT_8821C << BIT_SHIFT_R_RPT_FROM_BT_8821C)
+#define BIT_CLEAR_R_RPT_FROM_BT_8821C(x) ((x) & (~BITS_R_RPT_FROM_BT_8821C))
+#define BIT_GET_R_RPT_FROM_BT_8821C(x)                                         \
+	(((x) >> BIT_SHIFT_R_RPT_FROM_BT_8821C) & BIT_MASK_R_RPT_FROM_BT_8821C)
+#define BIT_SET_R_RPT_FROM_BT_8821C(x, v)                                      \
+	(BIT_CLEAR_R_RPT_FROM_BT_8821C(x) | BIT_R_RPT_FROM_BT_8821C(v))
+
+#define BIT_SHIFT_BT_HID_ISR_SET_8821C 6
+#define BIT_MASK_BT_HID_ISR_SET_8821C 0x3
+#define BIT_BT_HID_ISR_SET_8821C(x)                                            \
+	(((x) & BIT_MASK_BT_HID_ISR_SET_8821C)                                 \
+	 << BIT_SHIFT_BT_HID_ISR_SET_8821C)
+#define BITS_BT_HID_ISR_SET_8821C                                              \
+	(BIT_MASK_BT_HID_ISR_SET_8821C << BIT_SHIFT_BT_HID_ISR_SET_8821C)
+#define BIT_CLEAR_BT_HID_ISR_SET_8821C(x) ((x) & (~BITS_BT_HID_ISR_SET_8821C))
+#define BIT_GET_BT_HID_ISR_SET_8821C(x)                                        \
+	(((x) >> BIT_SHIFT_BT_HID_ISR_SET_8821C) &                             \
+	 BIT_MASK_BT_HID_ISR_SET_8821C)
+#define BIT_SET_BT_HID_ISR_SET_8821C(x, v)                                     \
+	(BIT_CLEAR_BT_HID_ISR_SET_8821C(x) | BIT_BT_HID_ISR_SET_8821C(v))
+
+#define BIT_TDMA_BT_START_NOTIFY_8821C BIT(5)
+#define BIT_ENABLE_TDMA_FW_MODE_8821C BIT(4)
+#define BIT_ENABLE_PTA_TDMA_MODE_8821C BIT(3)
+#define BIT_ENABLE_COEXIST_TAB_IN_TDMA_8821C BIT(2)
+#define BIT_GPIO2_GPIO3_EXANGE_OR_NO_BT_CCA_8821C BIT(1)
+#define BIT_RTK_BT_ENABLE_8821C BIT(0)
+
+/* 2 REG_BT_STATUS_REPORT_REGISTER_8821C */
+
+#define BIT_SHIFT_BT_PROFILE_8821C 24
+#define BIT_MASK_BT_PROFILE_8821C 0xff
+#define BIT_BT_PROFILE_8821C(x)                                                \
+	(((x) & BIT_MASK_BT_PROFILE_8821C) << BIT_SHIFT_BT_PROFILE_8821C)
+#define BITS_BT_PROFILE_8821C                                                  \
+	(BIT_MASK_BT_PROFILE_8821C << BIT_SHIFT_BT_PROFILE_8821C)
+#define BIT_CLEAR_BT_PROFILE_8821C(x) ((x) & (~BITS_BT_PROFILE_8821C))
+#define BIT_GET_BT_PROFILE_8821C(x)                                            \
+	(((x) >> BIT_SHIFT_BT_PROFILE_8821C) & BIT_MASK_BT_PROFILE_8821C)
+#define BIT_SET_BT_PROFILE_8821C(x, v)                                         \
+	(BIT_CLEAR_BT_PROFILE_8821C(x) | BIT_BT_PROFILE_8821C(v))
+
+#define BIT_SHIFT_BT_POWER_8821C 16
+#define BIT_MASK_BT_POWER_8821C 0xff
+#define BIT_BT_POWER_8821C(x)                                                  \
+	(((x) & BIT_MASK_BT_POWER_8821C) << BIT_SHIFT_BT_POWER_8821C)
+#define BITS_BT_POWER_8821C                                                    \
+	(BIT_MASK_BT_POWER_8821C << BIT_SHIFT_BT_POWER_8821C)
+#define BIT_CLEAR_BT_POWER_8821C(x) ((x) & (~BITS_BT_POWER_8821C))
+#define BIT_GET_BT_POWER_8821C(x)                                              \
+	(((x) >> BIT_SHIFT_BT_POWER_8821C) & BIT_MASK_BT_POWER_8821C)
+#define BIT_SET_BT_POWER_8821C(x, v)                                           \
+	(BIT_CLEAR_BT_POWER_8821C(x) | BIT_BT_POWER_8821C(v))
+
+#define BIT_SHIFT_BT_PREDECT_STATUS_8821C 8
+#define BIT_MASK_BT_PREDECT_STATUS_8821C 0xff
+#define BIT_BT_PREDECT_STATUS_8821C(x)                                         \
+	(((x) & BIT_MASK_BT_PREDECT_STATUS_8821C)                              \
+	 << BIT_SHIFT_BT_PREDECT_STATUS_8821C)
+#define BITS_BT_PREDECT_STATUS_8821C                                           \
+	(BIT_MASK_BT_PREDECT_STATUS_8821C << BIT_SHIFT_BT_PREDECT_STATUS_8821C)
+#define BIT_CLEAR_BT_PREDECT_STATUS_8821C(x)                                   \
+	((x) & (~BITS_BT_PREDECT_STATUS_8821C))
+#define BIT_GET_BT_PREDECT_STATUS_8821C(x)                                     \
+	(((x) >> BIT_SHIFT_BT_PREDECT_STATUS_8821C) &                          \
+	 BIT_MASK_BT_PREDECT_STATUS_8821C)
+#define BIT_SET_BT_PREDECT_STATUS_8821C(x, v)                                  \
+	(BIT_CLEAR_BT_PREDECT_STATUS_8821C(x) | BIT_BT_PREDECT_STATUS_8821C(v))
+
+#define BIT_SHIFT_BT_CMD_INFO_8821C 0
+#define BIT_MASK_BT_CMD_INFO_8821C 0xff
+#define BIT_BT_CMD_INFO_8821C(x)                                               \
+	(((x) & BIT_MASK_BT_CMD_INFO_8821C) << BIT_SHIFT_BT_CMD_INFO_8821C)
+#define BITS_BT_CMD_INFO_8821C                                                 \
+	(BIT_MASK_BT_CMD_INFO_8821C << BIT_SHIFT_BT_CMD_INFO_8821C)
+#define BIT_CLEAR_BT_CMD_INFO_8821C(x) ((x) & (~BITS_BT_CMD_INFO_8821C))
+#define BIT_GET_BT_CMD_INFO_8821C(x)                                           \
+	(((x) >> BIT_SHIFT_BT_CMD_INFO_8821C) & BIT_MASK_BT_CMD_INFO_8821C)
+#define BIT_SET_BT_CMD_INFO_8821C(x, v)                                        \
+	(BIT_CLEAR_BT_CMD_INFO_8821C(x) | BIT_BT_CMD_INFO_8821C(v))
+
+/* 2 REG_BT_INTERRUPT_CONTROL_REGISTER_8821C */
+#define BIT_EN_MAC_NULL_PKT_NOTIFY_8821C BIT(31)
+#define BIT_EN_WLAN_RPT_AND_BT_QUERY_8821C BIT(30)
+#define BIT_EN_BT_STSTUS_RPT_8821C BIT(29)
+#define BIT_EN_BT_POWER_8821C BIT(28)
+#define BIT_EN_BT_CHANNEL_8821C BIT(27)
+#define BIT_EN_BT_SLOT_CHANGE_8821C BIT(26)
+#define BIT_EN_BT_PROFILE_OR_HID_8821C BIT(25)
+#define BIT_WLAN_RPT_NOTIFY_8821C BIT(24)
+
+#define BIT_SHIFT_WLAN_RPT_DATA_8821C 16
+#define BIT_MASK_WLAN_RPT_DATA_8821C 0xff
+#define BIT_WLAN_RPT_DATA_8821C(x)                                             \
+	(((x) & BIT_MASK_WLAN_RPT_DATA_8821C) << BIT_SHIFT_WLAN_RPT_DATA_8821C)
+#define BITS_WLAN_RPT_DATA_8821C                                               \
+	(BIT_MASK_WLAN_RPT_DATA_8821C << BIT_SHIFT_WLAN_RPT_DATA_8821C)
+#define BIT_CLEAR_WLAN_RPT_DATA_8821C(x) ((x) & (~BITS_WLAN_RPT_DATA_8821C))
+#define BIT_GET_WLAN_RPT_DATA_8821C(x)                                         \
+	(((x) >> BIT_SHIFT_WLAN_RPT_DATA_8821C) & BIT_MASK_WLAN_RPT_DATA_8821C)
+#define BIT_SET_WLAN_RPT_DATA_8821C(x, v)                                      \
+	(BIT_CLEAR_WLAN_RPT_DATA_8821C(x) | BIT_WLAN_RPT_DATA_8821C(v))
+
+#define BIT_SHIFT_CMD_ID_8821C 8
+#define BIT_MASK_CMD_ID_8821C 0xff
+#define BIT_CMD_ID_8821C(x)                                                    \
+	(((x) & BIT_MASK_CMD_ID_8821C) << BIT_SHIFT_CMD_ID_8821C)
+#define BITS_CMD_ID_8821C (BIT_MASK_CMD_ID_8821C << BIT_SHIFT_CMD_ID_8821C)
+#define BIT_CLEAR_CMD_ID_8821C(x) ((x) & (~BITS_CMD_ID_8821C))
+#define BIT_GET_CMD_ID_8821C(x)                                                \
+	(((x) >> BIT_SHIFT_CMD_ID_8821C) & BIT_MASK_CMD_ID_8821C)
+#define BIT_SET_CMD_ID_8821C(x, v)                                             \
+	(BIT_CLEAR_CMD_ID_8821C(x) | BIT_CMD_ID_8821C(v))
+
+#define BIT_SHIFT_BT_DATA_8821C 0
+#define BIT_MASK_BT_DATA_8821C 0xff
+#define BIT_BT_DATA_8821C(x)                                                   \
+	(((x) & BIT_MASK_BT_DATA_8821C) << BIT_SHIFT_BT_DATA_8821C)
+#define BITS_BT_DATA_8821C (BIT_MASK_BT_DATA_8821C << BIT_SHIFT_BT_DATA_8821C)
+#define BIT_CLEAR_BT_DATA_8821C(x) ((x) & (~BITS_BT_DATA_8821C))
+#define BIT_GET_BT_DATA_8821C(x)                                               \
+	(((x) >> BIT_SHIFT_BT_DATA_8821C) & BIT_MASK_BT_DATA_8821C)
+#define BIT_SET_BT_DATA_8821C(x, v)                                            \
+	(BIT_CLEAR_BT_DATA_8821C(x) | BIT_BT_DATA_8821C(v))
+
+/* 2 REG_WLAN_REPORT_TIME_OUT_CONTROL_REGISTER_8821C */
+
+#define BIT_SHIFT_WLAN_RPT_TO_8821C 0
+#define BIT_MASK_WLAN_RPT_TO_8821C 0xff
+#define BIT_WLAN_RPT_TO_8821C(x)                                               \
+	(((x) & BIT_MASK_WLAN_RPT_TO_8821C) << BIT_SHIFT_WLAN_RPT_TO_8821C)
+#define BITS_WLAN_RPT_TO_8821C                                                 \
+	(BIT_MASK_WLAN_RPT_TO_8821C << BIT_SHIFT_WLAN_RPT_TO_8821C)
+#define BIT_CLEAR_WLAN_RPT_TO_8821C(x) ((x) & (~BITS_WLAN_RPT_TO_8821C))
+#define BIT_GET_WLAN_RPT_TO_8821C(x)                                           \
+	(((x) >> BIT_SHIFT_WLAN_RPT_TO_8821C) & BIT_MASK_WLAN_RPT_TO_8821C)
+#define BIT_SET_WLAN_RPT_TO_8821C(x, v)                                        \
+	(BIT_CLEAR_WLAN_RPT_TO_8821C(x) | BIT_WLAN_RPT_TO_8821C(v))
+
+/* 2 REG_BT_ISOLATION_TABLE_REGISTER_REGISTER_8821C */
+
+#define BIT_SHIFT_ISOLATION_CHK_0_8821C 1
+#define BIT_MASK_ISOLATION_CHK_0_8821C 0x7fffff
+#define BIT_ISOLATION_CHK_0_8821C(x)                                           \
+	(((x) & BIT_MASK_ISOLATION_CHK_0_8821C)                                \
+	 << BIT_SHIFT_ISOLATION_CHK_0_8821C)
+#define BITS_ISOLATION_CHK_0_8821C                                             \
+	(BIT_MASK_ISOLATION_CHK_0_8821C << BIT_SHIFT_ISOLATION_CHK_0_8821C)
+#define BIT_CLEAR_ISOLATION_CHK_0_8821C(x) ((x) & (~BITS_ISOLATION_CHK_0_8821C))
+#define BIT_GET_ISOLATION_CHK_0_8821C(x)                                       \
+	(((x) >> BIT_SHIFT_ISOLATION_CHK_0_8821C) &                            \
+	 BIT_MASK_ISOLATION_CHK_0_8821C)
+#define BIT_SET_ISOLATION_CHK_0_8821C(x, v)                                    \
+	(BIT_CLEAR_ISOLATION_CHK_0_8821C(x) | BIT_ISOLATION_CHK_0_8821C(v))
+
+#define BIT_ISOLATION_EN_8821C BIT(0)
+
+/* 2 REG_BT_ISOLATION_TABLE_REGISTER_REGISTER_1_8821C */
+
+#define BIT_SHIFT_ISOLATION_CHK_1_8821C 0
+#define BIT_MASK_ISOLATION_CHK_1_8821C 0xffffffffL
+#define BIT_ISOLATION_CHK_1_8821C(x)                                           \
+	(((x) & BIT_MASK_ISOLATION_CHK_1_8821C)                                \
+	 << BIT_SHIFT_ISOLATION_CHK_1_8821C)
+#define BITS_ISOLATION_CHK_1_8821C                                             \
+	(BIT_MASK_ISOLATION_CHK_1_8821C << BIT_SHIFT_ISOLATION_CHK_1_8821C)
+#define BIT_CLEAR_ISOLATION_CHK_1_8821C(x) ((x) & (~BITS_ISOLATION_CHK_1_8821C))
+#define BIT_GET_ISOLATION_CHK_1_8821C(x)                                       \
+	(((x) >> BIT_SHIFT_ISOLATION_CHK_1_8821C) &                            \
+	 BIT_MASK_ISOLATION_CHK_1_8821C)
+#define BIT_SET_ISOLATION_CHK_1_8821C(x, v)                                    \
+	(BIT_CLEAR_ISOLATION_CHK_1_8821C(x) | BIT_ISOLATION_CHK_1_8821C(v))
+
+/* 2 REG_BT_ISOLATION_TABLE_REGISTER_REGISTER_2_8821C */
+
+#define BIT_SHIFT_ISOLATION_CHK_2_8821C 0
+#define BIT_MASK_ISOLATION_CHK_2_8821C 0xffffff
+#define BIT_ISOLATION_CHK_2_8821C(x)                                           \
+	(((x) & BIT_MASK_ISOLATION_CHK_2_8821C)                                \
+	 << BIT_SHIFT_ISOLATION_CHK_2_8821C)
+#define BITS_ISOLATION_CHK_2_8821C                                             \
+	(BIT_MASK_ISOLATION_CHK_2_8821C << BIT_SHIFT_ISOLATION_CHK_2_8821C)
+#define BIT_CLEAR_ISOLATION_CHK_2_8821C(x) ((x) & (~BITS_ISOLATION_CHK_2_8821C))
+#define BIT_GET_ISOLATION_CHK_2_8821C(x)                                       \
+	(((x) >> BIT_SHIFT_ISOLATION_CHK_2_8821C) &                            \
+	 BIT_MASK_ISOLATION_CHK_2_8821C)
+#define BIT_SET_ISOLATION_CHK_2_8821C(x, v)                                    \
+	(BIT_CLEAR_ISOLATION_CHK_2_8821C(x) | BIT_ISOLATION_CHK_2_8821C(v))
+
+/* 2 REG_BT_INTERRUPT_STATUS_REGISTER_8821C */
+#define BIT_BT_HID_ISR_8821C BIT(7)
+#define BIT_BT_QUERY_ISR_8821C BIT(6)
+#define BIT_MAC_NULL_PKT_NOTIFY_ISR_8821C BIT(5)
+#define BIT_WLAN_RPT_ISR_8821C BIT(4)
+#define BIT_BT_POWER_ISR_8821C BIT(3)
+#define BIT_BT_CHANNEL_ISR_8821C BIT(2)
+#define BIT_BT_SLOT_CHANGE_ISR_8821C BIT(1)
+#define BIT_BT_PROFILE_ISR_8821C BIT(0)
+
+/* 2 REG_BT_TDMA_TIME_REGISTER_8821C */
+
+#define BIT_SHIFT_BT_TIME_8821C 6
+#define BIT_MASK_BT_TIME_8821C 0x3ffffff
+#define BIT_BT_TIME_8821C(x)                                                   \
+	(((x) & BIT_MASK_BT_TIME_8821C) << BIT_SHIFT_BT_TIME_8821C)
+#define BITS_BT_TIME_8821C (BIT_MASK_BT_TIME_8821C << BIT_SHIFT_BT_TIME_8821C)
+#define BIT_CLEAR_BT_TIME_8821C(x) ((x) & (~BITS_BT_TIME_8821C))
+#define BIT_GET_BT_TIME_8821C(x)                                               \
+	(((x) >> BIT_SHIFT_BT_TIME_8821C) & BIT_MASK_BT_TIME_8821C)
+#define BIT_SET_BT_TIME_8821C(x, v)                                            \
+	(BIT_CLEAR_BT_TIME_8821C(x) | BIT_BT_TIME_8821C(v))
+
+#define BIT_SHIFT_BT_RPT_SAMPLE_RATE_8821C 0
+#define BIT_MASK_BT_RPT_SAMPLE_RATE_8821C 0x3f
+#define BIT_BT_RPT_SAMPLE_RATE_8821C(x)                                        \
+	(((x) & BIT_MASK_BT_RPT_SAMPLE_RATE_8821C)                             \
+	 << BIT_SHIFT_BT_RPT_SAMPLE_RATE_8821C)
+#define BITS_BT_RPT_SAMPLE_RATE_8821C                                          \
+	(BIT_MASK_BT_RPT_SAMPLE_RATE_8821C                                     \
+	 << BIT_SHIFT_BT_RPT_SAMPLE_RATE_8821C)
+#define BIT_CLEAR_BT_RPT_SAMPLE_RATE_8821C(x)                                  \
+	((x) & (~BITS_BT_RPT_SAMPLE_RATE_8821C))
+#define BIT_GET_BT_RPT_SAMPLE_RATE_8821C(x)                                    \
+	(((x) >> BIT_SHIFT_BT_RPT_SAMPLE_RATE_8821C) &                         \
+	 BIT_MASK_BT_RPT_SAMPLE_RATE_8821C)
+#define BIT_SET_BT_RPT_SAMPLE_RATE_8821C(x, v)                                 \
+	(BIT_CLEAR_BT_RPT_SAMPLE_RATE_8821C(x) |                               \
+	 BIT_BT_RPT_SAMPLE_RATE_8821C(v))
+
+/* 2 REG_BT_ACT_REGISTER_8821C */
+
+#define BIT_SHIFT_BT_EISR_EN_8821C 16
+#define BIT_MASK_BT_EISR_EN_8821C 0xff
+#define BIT_BT_EISR_EN_8821C(x)                                                \
+	(((x) & BIT_MASK_BT_EISR_EN_8821C) << BIT_SHIFT_BT_EISR_EN_8821C)
+#define BITS_BT_EISR_EN_8821C                                                  \
+	(BIT_MASK_BT_EISR_EN_8821C << BIT_SHIFT_BT_EISR_EN_8821C)
+#define BIT_CLEAR_BT_EISR_EN_8821C(x) ((x) & (~BITS_BT_EISR_EN_8821C))
+#define BIT_GET_BT_EISR_EN_8821C(x)                                            \
+	(((x) >> BIT_SHIFT_BT_EISR_EN_8821C) & BIT_MASK_BT_EISR_EN_8821C)
+#define BIT_SET_BT_EISR_EN_8821C(x, v)                                         \
+	(BIT_CLEAR_BT_EISR_EN_8821C(x) | BIT_BT_EISR_EN_8821C(v))
+
+#define BIT_BT_ACT_FALLING_ISR_8821C BIT(10)
+#define BIT_BT_ACT_RISING_ISR_8821C BIT(9)
+#define BIT_TDMA_TO_ISR_8821C BIT(8)
+
+#define BIT_SHIFT_BT_CH_8821C 0
+#define BIT_MASK_BT_CH_8821C 0xff
+#define BIT_BT_CH_8821C(x)                                                     \
+	(((x) & BIT_MASK_BT_CH_8821C) << BIT_SHIFT_BT_CH_8821C)
+#define BITS_BT_CH_8821C (BIT_MASK_BT_CH_8821C << BIT_SHIFT_BT_CH_8821C)
+#define BIT_CLEAR_BT_CH_8821C(x) ((x) & (~BITS_BT_CH_8821C))
+#define BIT_GET_BT_CH_8821C(x)                                                 \
+	(((x) >> BIT_SHIFT_BT_CH_8821C) & BIT_MASK_BT_CH_8821C)
+#define BIT_SET_BT_CH_8821C(x, v)                                              \
+	(BIT_CLEAR_BT_CH_8821C(x) | BIT_BT_CH_8821C(v))
+
+/* 2 REG_OBFF_CTRL_BASIC_8821C */
+#define BIT_OBFF_EN_V1_8821C BIT(31)
+
+#define BIT_SHIFT_OBFF_STATE_V1_8821C 28
+#define BIT_MASK_OBFF_STATE_V1_8821C 0x3
+#define BIT_OBFF_STATE_V1_8821C(x)                                             \
+	(((x) & BIT_MASK_OBFF_STATE_V1_8821C) << BIT_SHIFT_OBFF_STATE_V1_8821C)
+#define BITS_OBFF_STATE_V1_8821C                                               \
+	(BIT_MASK_OBFF_STATE_V1_8821C << BIT_SHIFT_OBFF_STATE_V1_8821C)
+#define BIT_CLEAR_OBFF_STATE_V1_8821C(x) ((x) & (~BITS_OBFF_STATE_V1_8821C))
+#define BIT_GET_OBFF_STATE_V1_8821C(x)                                         \
+	(((x) >> BIT_SHIFT_OBFF_STATE_V1_8821C) & BIT_MASK_OBFF_STATE_V1_8821C)
+#define BIT_SET_OBFF_STATE_V1_8821C(x, v)                                      \
+	(BIT_CLEAR_OBFF_STATE_V1_8821C(x) | BIT_OBFF_STATE_V1_8821C(v))
+
+#define BIT_OBFF_ACT_RXDMA_EN_8821C BIT(27)
+#define BIT_OBFF_BLOCK_INT_EN_8821C BIT(26)
+#define BIT_OBFF_AUTOACT_EN_8821C BIT(25)
+#define BIT_OBFF_AUTOIDLE_EN_8821C BIT(24)
+
+#define BIT_SHIFT_WAKE_MAX_PLS_8821C 20
+#define BIT_MASK_WAKE_MAX_PLS_8821C 0x7
+#define BIT_WAKE_MAX_PLS_8821C(x)                                              \
+	(((x) & BIT_MASK_WAKE_MAX_PLS_8821C) << BIT_SHIFT_WAKE_MAX_PLS_8821C)
+#define BITS_WAKE_MAX_PLS_8821C                                                \
+	(BIT_MASK_WAKE_MAX_PLS_8821C << BIT_SHIFT_WAKE_MAX_PLS_8821C)
+#define BIT_CLEAR_WAKE_MAX_PLS_8821C(x) ((x) & (~BITS_WAKE_MAX_PLS_8821C))
+#define BIT_GET_WAKE_MAX_PLS_8821C(x)                                          \
+	(((x) >> BIT_SHIFT_WAKE_MAX_PLS_8821C) & BIT_MASK_WAKE_MAX_PLS_8821C)
+#define BIT_SET_WAKE_MAX_PLS_8821C(x, v)                                       \
+	(BIT_CLEAR_WAKE_MAX_PLS_8821C(x) | BIT_WAKE_MAX_PLS_8821C(v))
+
+#define BIT_SHIFT_WAKE_MIN_PLS_8821C 16
+#define BIT_MASK_WAKE_MIN_PLS_8821C 0x7
+#define BIT_WAKE_MIN_PLS_8821C(x)                                              \
+	(((x) & BIT_MASK_WAKE_MIN_PLS_8821C) << BIT_SHIFT_WAKE_MIN_PLS_8821C)
+#define BITS_WAKE_MIN_PLS_8821C                                                \
+	(BIT_MASK_WAKE_MIN_PLS_8821C << BIT_SHIFT_WAKE_MIN_PLS_8821C)
+#define BIT_CLEAR_WAKE_MIN_PLS_8821C(x) ((x) & (~BITS_WAKE_MIN_PLS_8821C))
+#define BIT_GET_WAKE_MIN_PLS_8821C(x)                                          \
+	(((x) >> BIT_SHIFT_WAKE_MIN_PLS_8821C) & BIT_MASK_WAKE_MIN_PLS_8821C)
+#define BIT_SET_WAKE_MIN_PLS_8821C(x, v)                                       \
+	(BIT_CLEAR_WAKE_MIN_PLS_8821C(x) | BIT_WAKE_MIN_PLS_8821C(v))
+
+#define BIT_SHIFT_WAKE_MAX_F2F_8821C 12
+#define BIT_MASK_WAKE_MAX_F2F_8821C 0x7
+#define BIT_WAKE_MAX_F2F_8821C(x)                                              \
+	(((x) & BIT_MASK_WAKE_MAX_F2F_8821C) << BIT_SHIFT_WAKE_MAX_F2F_8821C)
+#define BITS_WAKE_MAX_F2F_8821C                                                \
+	(BIT_MASK_WAKE_MAX_F2F_8821C << BIT_SHIFT_WAKE_MAX_F2F_8821C)
+#define BIT_CLEAR_WAKE_MAX_F2F_8821C(x) ((x) & (~BITS_WAKE_MAX_F2F_8821C))
+#define BIT_GET_WAKE_MAX_F2F_8821C(x)                                          \
+	(((x) >> BIT_SHIFT_WAKE_MAX_F2F_8821C) & BIT_MASK_WAKE_MAX_F2F_8821C)
+#define BIT_SET_WAKE_MAX_F2F_8821C(x, v)                                       \
+	(BIT_CLEAR_WAKE_MAX_F2F_8821C(x) | BIT_WAKE_MAX_F2F_8821C(v))
+
+#define BIT_SHIFT_WAKE_MIN_F2F_8821C 8
+#define BIT_MASK_WAKE_MIN_F2F_8821C 0x7
+#define BIT_WAKE_MIN_F2F_8821C(x)                                              \
+	(((x) & BIT_MASK_WAKE_MIN_F2F_8821C) << BIT_SHIFT_WAKE_MIN_F2F_8821C)
+#define BITS_WAKE_MIN_F2F_8821C                                                \
+	(BIT_MASK_WAKE_MIN_F2F_8821C << BIT_SHIFT_WAKE_MIN_F2F_8821C)
+#define BIT_CLEAR_WAKE_MIN_F2F_8821C(x) ((x) & (~BITS_WAKE_MIN_F2F_8821C))
+#define BIT_GET_WAKE_MIN_F2F_8821C(x)                                          \
+	(((x) >> BIT_SHIFT_WAKE_MIN_F2F_8821C) & BIT_MASK_WAKE_MIN_F2F_8821C)
+#define BIT_SET_WAKE_MIN_F2F_8821C(x, v)                                       \
+	(BIT_CLEAR_WAKE_MIN_F2F_8821C(x) | BIT_WAKE_MIN_F2F_8821C(v))
+
+#define BIT_APP_CPU_ACT_V1_8821C BIT(3)
+#define BIT_APP_OBFF_V1_8821C BIT(2)
+#define BIT_APP_IDLE_V1_8821C BIT(1)
+#define BIT_APP_INIT_V1_8821C BIT(0)
+
+/* 2 REG_OBFF_CTRL2_TIMER_8821C */
+
+#define BIT_SHIFT_RX_HIGH_TIMER_IDX_8821C 24
+#define BIT_MASK_RX_HIGH_TIMER_IDX_8821C 0x7
+#define BIT_RX_HIGH_TIMER_IDX_8821C(x)                                         \
+	(((x) & BIT_MASK_RX_HIGH_TIMER_IDX_8821C)                              \
+	 << BIT_SHIFT_RX_HIGH_TIMER_IDX_8821C)
+#define BITS_RX_HIGH_TIMER_IDX_8821C                                           \
+	(BIT_MASK_RX_HIGH_TIMER_IDX_8821C << BIT_SHIFT_RX_HIGH_TIMER_IDX_8821C)
+#define BIT_CLEAR_RX_HIGH_TIMER_IDX_8821C(x)                                   \
+	((x) & (~BITS_RX_HIGH_TIMER_IDX_8821C))
+#define BIT_GET_RX_HIGH_TIMER_IDX_8821C(x)                                     \
+	(((x) >> BIT_SHIFT_RX_HIGH_TIMER_IDX_8821C) &                          \
+	 BIT_MASK_RX_HIGH_TIMER_IDX_8821C)
+#define BIT_SET_RX_HIGH_TIMER_IDX_8821C(x, v)                                  \
+	(BIT_CLEAR_RX_HIGH_TIMER_IDX_8821C(x) | BIT_RX_HIGH_TIMER_IDX_8821C(v))
+
+#define BIT_SHIFT_RX_MED_TIMER_IDX_8821C 16
+#define BIT_MASK_RX_MED_TIMER_IDX_8821C 0x7
+#define BIT_RX_MED_TIMER_IDX_8821C(x)                                          \
+	(((x) & BIT_MASK_RX_MED_TIMER_IDX_8821C)                               \
+	 << BIT_SHIFT_RX_MED_TIMER_IDX_8821C)
+#define BITS_RX_MED_TIMER_IDX_8821C                                            \
+	(BIT_MASK_RX_MED_TIMER_IDX_8821C << BIT_SHIFT_RX_MED_TIMER_IDX_8821C)
+#define BIT_CLEAR_RX_MED_TIMER_IDX_8821C(x)                                    \
+	((x) & (~BITS_RX_MED_TIMER_IDX_8821C))
+#define BIT_GET_RX_MED_TIMER_IDX_8821C(x)                                      \
+	(((x) >> BIT_SHIFT_RX_MED_TIMER_IDX_8821C) &                           \
+	 BIT_MASK_RX_MED_TIMER_IDX_8821C)
+#define BIT_SET_RX_MED_TIMER_IDX_8821C(x, v)                                   \
+	(BIT_CLEAR_RX_MED_TIMER_IDX_8821C(x) | BIT_RX_MED_TIMER_IDX_8821C(v))
+
+#define BIT_SHIFT_RX_LOW_TIMER_IDX_8821C 8
+#define BIT_MASK_RX_LOW_TIMER_IDX_8821C 0x7
+#define BIT_RX_LOW_TIMER_IDX_8821C(x)                                          \
+	(((x) & BIT_MASK_RX_LOW_TIMER_IDX_8821C)                               \
+	 << BIT_SHIFT_RX_LOW_TIMER_IDX_8821C)
+#define BITS_RX_LOW_TIMER_IDX_8821C                                            \
+	(BIT_MASK_RX_LOW_TIMER_IDX_8821C << BIT_SHIFT_RX_LOW_TIMER_IDX_8821C)
+#define BIT_CLEAR_RX_LOW_TIMER_IDX_8821C(x)                                    \
+	((x) & (~BITS_RX_LOW_TIMER_IDX_8821C))
+#define BIT_GET_RX_LOW_TIMER_IDX_8821C(x)                                      \
+	(((x) >> BIT_SHIFT_RX_LOW_TIMER_IDX_8821C) &                           \
+	 BIT_MASK_RX_LOW_TIMER_IDX_8821C)
+#define BIT_SET_RX_LOW_TIMER_IDX_8821C(x, v)                                   \
+	(BIT_CLEAR_RX_LOW_TIMER_IDX_8821C(x) | BIT_RX_LOW_TIMER_IDX_8821C(v))
+
+#define BIT_SHIFT_OBFF_INT_TIMER_IDX_8821C 0
+#define BIT_MASK_OBFF_INT_TIMER_IDX_8821C 0x7
+#define BIT_OBFF_INT_TIMER_IDX_8821C(x)                                        \
+	(((x) & BIT_MASK_OBFF_INT_TIMER_IDX_8821C)                             \
+	 << BIT_SHIFT_OBFF_INT_TIMER_IDX_8821C)
+#define BITS_OBFF_INT_TIMER_IDX_8821C                                          \
+	(BIT_MASK_OBFF_INT_TIMER_IDX_8821C                                     \
+	 << BIT_SHIFT_OBFF_INT_TIMER_IDX_8821C)
+#define BIT_CLEAR_OBFF_INT_TIMER_IDX_8821C(x)                                  \
+	((x) & (~BITS_OBFF_INT_TIMER_IDX_8821C))
+#define BIT_GET_OBFF_INT_TIMER_IDX_8821C(x)                                    \
+	(((x) >> BIT_SHIFT_OBFF_INT_TIMER_IDX_8821C) &                         \
+	 BIT_MASK_OBFF_INT_TIMER_IDX_8821C)
+#define BIT_SET_OBFF_INT_TIMER_IDX_8821C(x, v)                                 \
+	(BIT_CLEAR_OBFF_INT_TIMER_IDX_8821C(x) |                               \
+	 BIT_OBFF_INT_TIMER_IDX_8821C(v))
+
+/* 2 REG_LTR_CTRL_BASIC_8821C */
+#define BIT_LTR_EN_V1_8821C BIT(31)
+#define BIT_LTR_HW_EN_V1_8821C BIT(30)
+#define BIT_LRT_ACT_CTS_EN_8821C BIT(29)
+#define BIT_LTR_ACT_RXPKT_EN_8821C BIT(28)
+#define BIT_LTR_ACT_RXDMA_EN_8821C BIT(27)
+#define BIT_LTR_IDLE_NO_SNOOP_8821C BIT(26)
+#define BIT_SPDUP_MGTPKT_8821C BIT(25)
+#define BIT_RX_AGG_EN_8821C BIT(24)
+#define BIT_APP_LTR_ACT_8821C BIT(23)
+#define BIT_APP_LTR_IDLE_8821C BIT(22)
+
+#define BIT_SHIFT_HIGH_RATE_TRIG_SEL_8821C 20
+#define BIT_MASK_HIGH_RATE_TRIG_SEL_8821C 0x3
+#define BIT_HIGH_RATE_TRIG_SEL_8821C(x)                                        \
+	(((x) & BIT_MASK_HIGH_RATE_TRIG_SEL_8821C)                             \
+	 << BIT_SHIFT_HIGH_RATE_TRIG_SEL_8821C)
+#define BITS_HIGH_RATE_TRIG_SEL_8821C                                          \
+	(BIT_MASK_HIGH_RATE_TRIG_SEL_8821C                                     \
+	 << BIT_SHIFT_HIGH_RATE_TRIG_SEL_8821C)
+#define BIT_CLEAR_HIGH_RATE_TRIG_SEL_8821C(x)                                  \
+	((x) & (~BITS_HIGH_RATE_TRIG_SEL_8821C))
+#define BIT_GET_HIGH_RATE_TRIG_SEL_8821C(x)                                    \
+	(((x) >> BIT_SHIFT_HIGH_RATE_TRIG_SEL_8821C) &                         \
+	 BIT_MASK_HIGH_RATE_TRIG_SEL_8821C)
+#define BIT_SET_HIGH_RATE_TRIG_SEL_8821C(x, v)                                 \
+	(BIT_CLEAR_HIGH_RATE_TRIG_SEL_8821C(x) |                               \
+	 BIT_HIGH_RATE_TRIG_SEL_8821C(v))
+
+#define BIT_SHIFT_MED_RATE_TRIG_SEL_8821C 18
+#define BIT_MASK_MED_RATE_TRIG_SEL_8821C 0x3
+#define BIT_MED_RATE_TRIG_SEL_8821C(x)                                         \
+	(((x) & BIT_MASK_MED_RATE_TRIG_SEL_8821C)                              \
+	 << BIT_SHIFT_MED_RATE_TRIG_SEL_8821C)
+#define BITS_MED_RATE_TRIG_SEL_8821C                                           \
+	(BIT_MASK_MED_RATE_TRIG_SEL_8821C << BIT_SHIFT_MED_RATE_TRIG_SEL_8821C)
+#define BIT_CLEAR_MED_RATE_TRIG_SEL_8821C(x)                                   \
+	((x) & (~BITS_MED_RATE_TRIG_SEL_8821C))
+#define BIT_GET_MED_RATE_TRIG_SEL_8821C(x)                                     \
+	(((x) >> BIT_SHIFT_MED_RATE_TRIG_SEL_8821C) &                          \
+	 BIT_MASK_MED_RATE_TRIG_SEL_8821C)
+#define BIT_SET_MED_RATE_TRIG_SEL_8821C(x, v)                                  \
+	(BIT_CLEAR_MED_RATE_TRIG_SEL_8821C(x) | BIT_MED_RATE_TRIG_SEL_8821C(v))
+
+#define BIT_SHIFT_LOW_RATE_TRIG_SEL_8821C 16
+#define BIT_MASK_LOW_RATE_TRIG_SEL_8821C 0x3
+#define BIT_LOW_RATE_TRIG_SEL_8821C(x)                                         \
+	(((x) & BIT_MASK_LOW_RATE_TRIG_SEL_8821C)                              \
+	 << BIT_SHIFT_LOW_RATE_TRIG_SEL_8821C)
+#define BITS_LOW_RATE_TRIG_SEL_8821C                                           \
+	(BIT_MASK_LOW_RATE_TRIG_SEL_8821C << BIT_SHIFT_LOW_RATE_TRIG_SEL_8821C)
+#define BIT_CLEAR_LOW_RATE_TRIG_SEL_8821C(x)                                   \
+	((x) & (~BITS_LOW_RATE_TRIG_SEL_8821C))
+#define BIT_GET_LOW_RATE_TRIG_SEL_8821C(x)                                     \
+	(((x) >> BIT_SHIFT_LOW_RATE_TRIG_SEL_8821C) &                          \
+	 BIT_MASK_LOW_RATE_TRIG_SEL_8821C)
+#define BIT_SET_LOW_RATE_TRIG_SEL_8821C(x, v)                                  \
+	(BIT_CLEAR_LOW_RATE_TRIG_SEL_8821C(x) | BIT_LOW_RATE_TRIG_SEL_8821C(v))
+
+#define BIT_SHIFT_HIGH_RATE_BD_IDX_8821C 8
+#define BIT_MASK_HIGH_RATE_BD_IDX_8821C 0x7f
+#define BIT_HIGH_RATE_BD_IDX_8821C(x)                                          \
+	(((x) & BIT_MASK_HIGH_RATE_BD_IDX_8821C)                               \
+	 << BIT_SHIFT_HIGH_RATE_BD_IDX_8821C)
+#define BITS_HIGH_RATE_BD_IDX_8821C                                            \
+	(BIT_MASK_HIGH_RATE_BD_IDX_8821C << BIT_SHIFT_HIGH_RATE_BD_IDX_8821C)
+#define BIT_CLEAR_HIGH_RATE_BD_IDX_8821C(x)                                    \
+	((x) & (~BITS_HIGH_RATE_BD_IDX_8821C))
+#define BIT_GET_HIGH_RATE_BD_IDX_8821C(x)                                      \
+	(((x) >> BIT_SHIFT_HIGH_RATE_BD_IDX_8821C) &                           \
+	 BIT_MASK_HIGH_RATE_BD_IDX_8821C)
+#define BIT_SET_HIGH_RATE_BD_IDX_8821C(x, v)                                   \
+	(BIT_CLEAR_HIGH_RATE_BD_IDX_8821C(x) | BIT_HIGH_RATE_BD_IDX_8821C(v))
+
+#define BIT_SHIFT_LOW_RATE_BD_IDX_8821C 0
+#define BIT_MASK_LOW_RATE_BD_IDX_8821C 0x7f
+#define BIT_LOW_RATE_BD_IDX_8821C(x)                                           \
+	(((x) & BIT_MASK_LOW_RATE_BD_IDX_8821C)                                \
+	 << BIT_SHIFT_LOW_RATE_BD_IDX_8821C)
+#define BITS_LOW_RATE_BD_IDX_8821C                                             \
+	(BIT_MASK_LOW_RATE_BD_IDX_8821C << BIT_SHIFT_LOW_RATE_BD_IDX_8821C)
+#define BIT_CLEAR_LOW_RATE_BD_IDX_8821C(x) ((x) & (~BITS_LOW_RATE_BD_IDX_8821C))
+#define BIT_GET_LOW_RATE_BD_IDX_8821C(x)                                       \
+	(((x) >> BIT_SHIFT_LOW_RATE_BD_IDX_8821C) &                            \
+	 BIT_MASK_LOW_RATE_BD_IDX_8821C)
+#define BIT_SET_LOW_RATE_BD_IDX_8821C(x, v)                                    \
+	(BIT_CLEAR_LOW_RATE_BD_IDX_8821C(x) | BIT_LOW_RATE_BD_IDX_8821C(v))
+
+/* 2 REG_LTR_CTRL2_TIMER_THRESHOLD_8821C */
+
+#define BIT_SHIFT_RX_EMPTY_TIMER_IDX_8821C 24
+#define BIT_MASK_RX_EMPTY_TIMER_IDX_8821C 0x7
+#define BIT_RX_EMPTY_TIMER_IDX_8821C(x)                                        \
+	(((x) & BIT_MASK_RX_EMPTY_TIMER_IDX_8821C)                             \
+	 << BIT_SHIFT_RX_EMPTY_TIMER_IDX_8821C)
+#define BITS_RX_EMPTY_TIMER_IDX_8821C                                          \
+	(BIT_MASK_RX_EMPTY_TIMER_IDX_8821C                                     \
+	 << BIT_SHIFT_RX_EMPTY_TIMER_IDX_8821C)
+#define BIT_CLEAR_RX_EMPTY_TIMER_IDX_8821C(x)                                  \
+	((x) & (~BITS_RX_EMPTY_TIMER_IDX_8821C))
+#define BIT_GET_RX_EMPTY_TIMER_IDX_8821C(x)                                    \
+	(((x) >> BIT_SHIFT_RX_EMPTY_TIMER_IDX_8821C) &                         \
+	 BIT_MASK_RX_EMPTY_TIMER_IDX_8821C)
+#define BIT_SET_RX_EMPTY_TIMER_IDX_8821C(x, v)                                 \
+	(BIT_CLEAR_RX_EMPTY_TIMER_IDX_8821C(x) |                               \
+	 BIT_RX_EMPTY_TIMER_IDX_8821C(v))
+
+#define BIT_SHIFT_RX_AFULL_TH_IDX_8821C 20
+#define BIT_MASK_RX_AFULL_TH_IDX_8821C 0x7
+#define BIT_RX_AFULL_TH_IDX_8821C(x)                                           \
+	(((x) & BIT_MASK_RX_AFULL_TH_IDX_8821C)                                \
+	 << BIT_SHIFT_RX_AFULL_TH_IDX_8821C)
+#define BITS_RX_AFULL_TH_IDX_8821C                                             \
+	(BIT_MASK_RX_AFULL_TH_IDX_8821C << BIT_SHIFT_RX_AFULL_TH_IDX_8821C)
+#define BIT_CLEAR_RX_AFULL_TH_IDX_8821C(x) ((x) & (~BITS_RX_AFULL_TH_IDX_8821C))
+#define BIT_GET_RX_AFULL_TH_IDX_8821C(x)                                       \
+	(((x) >> BIT_SHIFT_RX_AFULL_TH_IDX_8821C) &                            \
+	 BIT_MASK_RX_AFULL_TH_IDX_8821C)
+#define BIT_SET_RX_AFULL_TH_IDX_8821C(x, v)                                    \
+	(BIT_CLEAR_RX_AFULL_TH_IDX_8821C(x) | BIT_RX_AFULL_TH_IDX_8821C(v))
+
+#define BIT_SHIFT_RX_HIGH_TH_IDX_8821C 16
+#define BIT_MASK_RX_HIGH_TH_IDX_8821C 0x7
+#define BIT_RX_HIGH_TH_IDX_8821C(x)                                            \
+	(((x) & BIT_MASK_RX_HIGH_TH_IDX_8821C)                                 \
+	 << BIT_SHIFT_RX_HIGH_TH_IDX_8821C)
+#define BITS_RX_HIGH_TH_IDX_8821C                                              \
+	(BIT_MASK_RX_HIGH_TH_IDX_8821C << BIT_SHIFT_RX_HIGH_TH_IDX_8821C)
+#define BIT_CLEAR_RX_HIGH_TH_IDX_8821C(x) ((x) & (~BITS_RX_HIGH_TH_IDX_8821C))
+#define BIT_GET_RX_HIGH_TH_IDX_8821C(x)                                        \
+	(((x) >> BIT_SHIFT_RX_HIGH_TH_IDX_8821C) &                             \
+	 BIT_MASK_RX_HIGH_TH_IDX_8821C)
+#define BIT_SET_RX_HIGH_TH_IDX_8821C(x, v)                                     \
+	(BIT_CLEAR_RX_HIGH_TH_IDX_8821C(x) | BIT_RX_HIGH_TH_IDX_8821C(v))
+
+#define BIT_SHIFT_RX_MED_TH_IDX_8821C 12
+#define BIT_MASK_RX_MED_TH_IDX_8821C 0x7
+#define BIT_RX_MED_TH_IDX_8821C(x)                                             \
+	(((x) & BIT_MASK_RX_MED_TH_IDX_8821C) << BIT_SHIFT_RX_MED_TH_IDX_8821C)
+#define BITS_RX_MED_TH_IDX_8821C                                               \
+	(BIT_MASK_RX_MED_TH_IDX_8821C << BIT_SHIFT_RX_MED_TH_IDX_8821C)
+#define BIT_CLEAR_RX_MED_TH_IDX_8821C(x) ((x) & (~BITS_RX_MED_TH_IDX_8821C))
+#define BIT_GET_RX_MED_TH_IDX_8821C(x)                                         \
+	(((x) >> BIT_SHIFT_RX_MED_TH_IDX_8821C) & BIT_MASK_RX_MED_TH_IDX_8821C)
+#define BIT_SET_RX_MED_TH_IDX_8821C(x, v)                                      \
+	(BIT_CLEAR_RX_MED_TH_IDX_8821C(x) | BIT_RX_MED_TH_IDX_8821C(v))
+
+#define BIT_SHIFT_RX_LOW_TH_IDX_8821C 8
+#define BIT_MASK_RX_LOW_TH_IDX_8821C 0x7
+#define BIT_RX_LOW_TH_IDX_8821C(x)                                             \
+	(((x) & BIT_MASK_RX_LOW_TH_IDX_8821C) << BIT_SHIFT_RX_LOW_TH_IDX_8821C)
+#define BITS_RX_LOW_TH_IDX_8821C                                               \
+	(BIT_MASK_RX_LOW_TH_IDX_8821C << BIT_SHIFT_RX_LOW_TH_IDX_8821C)
+#define BIT_CLEAR_RX_LOW_TH_IDX_8821C(x) ((x) & (~BITS_RX_LOW_TH_IDX_8821C))
+#define BIT_GET_RX_LOW_TH_IDX_8821C(x)                                         \
+	(((x) >> BIT_SHIFT_RX_LOW_TH_IDX_8821C) & BIT_MASK_RX_LOW_TH_IDX_8821C)
+#define BIT_SET_RX_LOW_TH_IDX_8821C(x, v)                                      \
+	(BIT_CLEAR_RX_LOW_TH_IDX_8821C(x) | BIT_RX_LOW_TH_IDX_8821C(v))
+
+#define BIT_SHIFT_LTR_SPACE_IDX_8821C 4
+#define BIT_MASK_LTR_SPACE_IDX_8821C 0x3
+#define BIT_LTR_SPACE_IDX_8821C(x)                                             \
+	(((x) & BIT_MASK_LTR_SPACE_IDX_8821C) << BIT_SHIFT_LTR_SPACE_IDX_8821C)
+#define BITS_LTR_SPACE_IDX_8821C                                               \
+	(BIT_MASK_LTR_SPACE_IDX_8821C << BIT_SHIFT_LTR_SPACE_IDX_8821C)
+#define BIT_CLEAR_LTR_SPACE_IDX_8821C(x) ((x) & (~BITS_LTR_SPACE_IDX_8821C))
+#define BIT_GET_LTR_SPACE_IDX_8821C(x)                                         \
+	(((x) >> BIT_SHIFT_LTR_SPACE_IDX_8821C) & BIT_MASK_LTR_SPACE_IDX_8821C)
+#define BIT_SET_LTR_SPACE_IDX_8821C(x, v)                                      \
+	(BIT_CLEAR_LTR_SPACE_IDX_8821C(x) | BIT_LTR_SPACE_IDX_8821C(v))
+
+#define BIT_SHIFT_LTR_IDLE_TIMER_IDX_8821C 0
+#define BIT_MASK_LTR_IDLE_TIMER_IDX_8821C 0x7
+#define BIT_LTR_IDLE_TIMER_IDX_8821C(x)                                        \
+	(((x) & BIT_MASK_LTR_IDLE_TIMER_IDX_8821C)                             \
+	 << BIT_SHIFT_LTR_IDLE_TIMER_IDX_8821C)
+#define BITS_LTR_IDLE_TIMER_IDX_8821C                                          \
+	(BIT_MASK_LTR_IDLE_TIMER_IDX_8821C                                     \
+	 << BIT_SHIFT_LTR_IDLE_TIMER_IDX_8821C)
+#define BIT_CLEAR_LTR_IDLE_TIMER_IDX_8821C(x)                                  \
+	((x) & (~BITS_LTR_IDLE_TIMER_IDX_8821C))
+#define BIT_GET_LTR_IDLE_TIMER_IDX_8821C(x)                                    \
+	(((x) >> BIT_SHIFT_LTR_IDLE_TIMER_IDX_8821C) &                         \
+	 BIT_MASK_LTR_IDLE_TIMER_IDX_8821C)
+#define BIT_SET_LTR_IDLE_TIMER_IDX_8821C(x, v)                                 \
+	(BIT_CLEAR_LTR_IDLE_TIMER_IDX_8821C(x) |                               \
+	 BIT_LTR_IDLE_TIMER_IDX_8821C(v))
+
+/* 2 REG_LTR_IDLE_LATENCY_V1_8821C */
+
+#define BIT_SHIFT_LTR_IDLE_L_8821C 0
+#define BIT_MASK_LTR_IDLE_L_8821C 0xffffffffL
+#define BIT_LTR_IDLE_L_8821C(x)                                                \
+	(((x) & BIT_MASK_LTR_IDLE_L_8821C) << BIT_SHIFT_LTR_IDLE_L_8821C)
+#define BITS_LTR_IDLE_L_8821C                                                  \
+	(BIT_MASK_LTR_IDLE_L_8821C << BIT_SHIFT_LTR_IDLE_L_8821C)
+#define BIT_CLEAR_LTR_IDLE_L_8821C(x) ((x) & (~BITS_LTR_IDLE_L_8821C))
+#define BIT_GET_LTR_IDLE_L_8821C(x)                                            \
+	(((x) >> BIT_SHIFT_LTR_IDLE_L_8821C) & BIT_MASK_LTR_IDLE_L_8821C)
+#define BIT_SET_LTR_IDLE_L_8821C(x, v)                                         \
+	(BIT_CLEAR_LTR_IDLE_L_8821C(x) | BIT_LTR_IDLE_L_8821C(v))
+
+/* 2 REG_LTR_ACTIVE_LATENCY_V1_8821C */
+
+#define BIT_SHIFT_LTR_ACT_L_8821C 0
+#define BIT_MASK_LTR_ACT_L_8821C 0xffffffffL
+#define BIT_LTR_ACT_L_8821C(x)                                                 \
+	(((x) & BIT_MASK_LTR_ACT_L_8821C) << BIT_SHIFT_LTR_ACT_L_8821C)
+#define BITS_LTR_ACT_L_8821C                                                   \
+	(BIT_MASK_LTR_ACT_L_8821C << BIT_SHIFT_LTR_ACT_L_8821C)
+#define BIT_CLEAR_LTR_ACT_L_8821C(x) ((x) & (~BITS_LTR_ACT_L_8821C))
+#define BIT_GET_LTR_ACT_L_8821C(x)                                             \
+	(((x) >> BIT_SHIFT_LTR_ACT_L_8821C) & BIT_MASK_LTR_ACT_L_8821C)
+#define BIT_SET_LTR_ACT_L_8821C(x, v)                                          \
+	(BIT_CLEAR_LTR_ACT_L_8821C(x) | BIT_LTR_ACT_L_8821C(v))
+
+/* 2 REG_ANTENNA_TRAINING_CONTROL_REGISTER_8821C */
+
+#define BIT_SHIFT_TRAIN_STA_ADDR_0_8821C 0
+#define BIT_MASK_TRAIN_STA_ADDR_0_8821C 0xffffffffL
+#define BIT_TRAIN_STA_ADDR_0_8821C(x)                                          \
+	(((x) & BIT_MASK_TRAIN_STA_ADDR_0_8821C)                               \
+	 << BIT_SHIFT_TRAIN_STA_ADDR_0_8821C)
+#define BITS_TRAIN_STA_ADDR_0_8821C                                            \
+	(BIT_MASK_TRAIN_STA_ADDR_0_8821C << BIT_SHIFT_TRAIN_STA_ADDR_0_8821C)
+#define BIT_CLEAR_TRAIN_STA_ADDR_0_8821C(x)                                    \
+	((x) & (~BITS_TRAIN_STA_ADDR_0_8821C))
+#define BIT_GET_TRAIN_STA_ADDR_0_8821C(x)                                      \
+	(((x) >> BIT_SHIFT_TRAIN_STA_ADDR_0_8821C) &                           \
+	 BIT_MASK_TRAIN_STA_ADDR_0_8821C)
+#define BIT_SET_TRAIN_STA_ADDR_0_8821C(x, v)                                   \
+	(BIT_CLEAR_TRAIN_STA_ADDR_0_8821C(x) | BIT_TRAIN_STA_ADDR_0_8821C(v))
+
+/* 2 REG_ANTENNA_TRAINING_CONTROL_REGISTER_1_8821C */
+#define BIT_APPEND_MACID_IN_RESP_EN_1_8821C BIT(18)
+#define BIT_ADDR2_MATCH_EN_1_8821C BIT(17)
+#define BIT_ANTTRN_EN_1_8821C BIT(16)
+
+#define BIT_SHIFT_TRAIN_STA_ADDR_1_8821C 0
+#define BIT_MASK_TRAIN_STA_ADDR_1_8821C 0xffff
+#define BIT_TRAIN_STA_ADDR_1_8821C(x)                                          \
+	(((x) & BIT_MASK_TRAIN_STA_ADDR_1_8821C)                               \
+	 << BIT_SHIFT_TRAIN_STA_ADDR_1_8821C)
+#define BITS_TRAIN_STA_ADDR_1_8821C                                            \
+	(BIT_MASK_TRAIN_STA_ADDR_1_8821C << BIT_SHIFT_TRAIN_STA_ADDR_1_8821C)
+#define BIT_CLEAR_TRAIN_STA_ADDR_1_8821C(x)                                    \
+	((x) & (~BITS_TRAIN_STA_ADDR_1_8821C))
+#define BIT_GET_TRAIN_STA_ADDR_1_8821C(x)                                      \
+	(((x) >> BIT_SHIFT_TRAIN_STA_ADDR_1_8821C) &                           \
+	 BIT_MASK_TRAIN_STA_ADDR_1_8821C)
+#define BIT_SET_TRAIN_STA_ADDR_1_8821C(x, v)                                   \
+	(BIT_CLEAR_TRAIN_STA_ADDR_1_8821C(x) | BIT_TRAIN_STA_ADDR_1_8821C(v))
+
+/* 2 REG_WMAC_PKTCNT_RWD_8821C */
+
+#define BIT_SHIFT_PKTCNT_BSSIDMAP_8821C 4
+#define BIT_MASK_PKTCNT_BSSIDMAP_8821C 0xf
+#define BIT_PKTCNT_BSSIDMAP_8821C(x)                                           \
+	(((x) & BIT_MASK_PKTCNT_BSSIDMAP_8821C)                                \
+	 << BIT_SHIFT_PKTCNT_BSSIDMAP_8821C)
+#define BITS_PKTCNT_BSSIDMAP_8821C                                             \
+	(BIT_MASK_PKTCNT_BSSIDMAP_8821C << BIT_SHIFT_PKTCNT_BSSIDMAP_8821C)
+#define BIT_CLEAR_PKTCNT_BSSIDMAP_8821C(x) ((x) & (~BITS_PKTCNT_BSSIDMAP_8821C))
+#define BIT_GET_PKTCNT_BSSIDMAP_8821C(x)                                       \
+	(((x) >> BIT_SHIFT_PKTCNT_BSSIDMAP_8821C) &                            \
+	 BIT_MASK_PKTCNT_BSSIDMAP_8821C)
+#define BIT_SET_PKTCNT_BSSIDMAP_8821C(x, v)                                    \
+	(BIT_CLEAR_PKTCNT_BSSIDMAP_8821C(x) | BIT_PKTCNT_BSSIDMAP_8821C(v))
+
+#define BIT_PKTCNT_CNTRST_8821C BIT(1)
+#define BIT_PKTCNT_CNTEN_8821C BIT(0)
+
+/* 2 REG_WMAC_PKTCNT_CTRL_8821C */
+#define BIT_WMAC_PKTCNT_TRST_8821C BIT(9)
+#define BIT_WMAC_PKTCNT_FEN_8821C BIT(8)
+
+#define BIT_SHIFT_WMAC_PKTCNT_CFGAD_8821C 0
+#define BIT_MASK_WMAC_PKTCNT_CFGAD_8821C 0xff
+#define BIT_WMAC_PKTCNT_CFGAD_8821C(x)                                         \
+	(((x) & BIT_MASK_WMAC_PKTCNT_CFGAD_8821C)                              \
+	 << BIT_SHIFT_WMAC_PKTCNT_CFGAD_8821C)
+#define BITS_WMAC_PKTCNT_CFGAD_8821C                                           \
+	(BIT_MASK_WMAC_PKTCNT_CFGAD_8821C << BIT_SHIFT_WMAC_PKTCNT_CFGAD_8821C)
+#define BIT_CLEAR_WMAC_PKTCNT_CFGAD_8821C(x)                                   \
+	((x) & (~BITS_WMAC_PKTCNT_CFGAD_8821C))
+#define BIT_GET_WMAC_PKTCNT_CFGAD_8821C(x)                                     \
+	(((x) >> BIT_SHIFT_WMAC_PKTCNT_CFGAD_8821C) &                          \
+	 BIT_MASK_WMAC_PKTCNT_CFGAD_8821C)
+#define BIT_SET_WMAC_PKTCNT_CFGAD_8821C(x, v)                                  \
+	(BIT_CLEAR_WMAC_PKTCNT_CFGAD_8821C(x) | BIT_WMAC_PKTCNT_CFGAD_8821C(v))
+
+/* 2 REG_IQ_DUMP_8821C */
+
+#define BIT_SHIFT_DUMP_OK_ADDR_8821C 16
+#define BIT_MASK_DUMP_OK_ADDR_8821C 0xffff
+#define BIT_DUMP_OK_ADDR_8821C(x)                                              \
+	(((x) & BIT_MASK_DUMP_OK_ADDR_8821C) << BIT_SHIFT_DUMP_OK_ADDR_8821C)
+#define BITS_DUMP_OK_ADDR_8821C                                                \
+	(BIT_MASK_DUMP_OK_ADDR_8821C << BIT_SHIFT_DUMP_OK_ADDR_8821C)
+#define BIT_CLEAR_DUMP_OK_ADDR_8821C(x) ((x) & (~BITS_DUMP_OK_ADDR_8821C))
+#define BIT_GET_DUMP_OK_ADDR_8821C(x)                                          \
+	(((x) >> BIT_SHIFT_DUMP_OK_ADDR_8821C) & BIT_MASK_DUMP_OK_ADDR_8821C)
+#define BIT_SET_DUMP_OK_ADDR_8821C(x, v)                                       \
+	(BIT_CLEAR_DUMP_OK_ADDR_8821C(x) | BIT_DUMP_OK_ADDR_8821C(v))
+
+#define BIT_SHIFT_R_TRIG_TIME_SEL_8821C 8
+#define BIT_MASK_R_TRIG_TIME_SEL_8821C 0x7f
+#define BIT_R_TRIG_TIME_SEL_8821C(x)                                           \
+	(((x) & BIT_MASK_R_TRIG_TIME_SEL_8821C)                                \
+	 << BIT_SHIFT_R_TRIG_TIME_SEL_8821C)
+#define BITS_R_TRIG_TIME_SEL_8821C                                             \
+	(BIT_MASK_R_TRIG_TIME_SEL_8821C << BIT_SHIFT_R_TRIG_TIME_SEL_8821C)
+#define BIT_CLEAR_R_TRIG_TIME_SEL_8821C(x) ((x) & (~BITS_R_TRIG_TIME_SEL_8821C))
+#define BIT_GET_R_TRIG_TIME_SEL_8821C(x)                                       \
+	(((x) >> BIT_SHIFT_R_TRIG_TIME_SEL_8821C) &                            \
+	 BIT_MASK_R_TRIG_TIME_SEL_8821C)
+#define BIT_SET_R_TRIG_TIME_SEL_8821C(x, v)                                    \
+	(BIT_CLEAR_R_TRIG_TIME_SEL_8821C(x) | BIT_R_TRIG_TIME_SEL_8821C(v))
+
+#define BIT_SHIFT_R_MAC_TRIG_SEL_8821C 6
+#define BIT_MASK_R_MAC_TRIG_SEL_8821C 0x3
+#define BIT_R_MAC_TRIG_SEL_8821C(x)                                            \
+	(((x) & BIT_MASK_R_MAC_TRIG_SEL_8821C)                                 \
+	 << BIT_SHIFT_R_MAC_TRIG_SEL_8821C)
+#define BITS_R_MAC_TRIG_SEL_8821C                                              \
+	(BIT_MASK_R_MAC_TRIG_SEL_8821C << BIT_SHIFT_R_MAC_TRIG_SEL_8821C)
+#define BIT_CLEAR_R_MAC_TRIG_SEL_8821C(x) ((x) & (~BITS_R_MAC_TRIG_SEL_8821C))
+#define BIT_GET_R_MAC_TRIG_SEL_8821C(x)                                        \
+	(((x) >> BIT_SHIFT_R_MAC_TRIG_SEL_8821C) &                             \
+	 BIT_MASK_R_MAC_TRIG_SEL_8821C)
+#define BIT_SET_R_MAC_TRIG_SEL_8821C(x, v)                                     \
+	(BIT_CLEAR_R_MAC_TRIG_SEL_8821C(x) | BIT_R_MAC_TRIG_SEL_8821C(v))
+
+#define BIT_MAC_TRIG_REG_8821C BIT(5)
+
+#define BIT_SHIFT_R_LEVEL_PULSE_SEL_8821C 3
+#define BIT_MASK_R_LEVEL_PULSE_SEL_8821C 0x3
+#define BIT_R_LEVEL_PULSE_SEL_8821C(x)                                         \
+	(((x) & BIT_MASK_R_LEVEL_PULSE_SEL_8821C)                              \
+	 << BIT_SHIFT_R_LEVEL_PULSE_SEL_8821C)
+#define BITS_R_LEVEL_PULSE_SEL_8821C                                           \
+	(BIT_MASK_R_LEVEL_PULSE_SEL_8821C << BIT_SHIFT_R_LEVEL_PULSE_SEL_8821C)
+#define BIT_CLEAR_R_LEVEL_PULSE_SEL_8821C(x)                                   \
+	((x) & (~BITS_R_LEVEL_PULSE_SEL_8821C))
+#define BIT_GET_R_LEVEL_PULSE_SEL_8821C(x)                                     \
+	(((x) >> BIT_SHIFT_R_LEVEL_PULSE_SEL_8821C) &                          \
+	 BIT_MASK_R_LEVEL_PULSE_SEL_8821C)
+#define BIT_SET_R_LEVEL_PULSE_SEL_8821C(x, v)                                  \
+	(BIT_CLEAR_R_LEVEL_PULSE_SEL_8821C(x) | BIT_R_LEVEL_PULSE_SEL_8821C(v))
+
+#define BIT_EN_LA_MAC_8821C BIT(2)
+#define BIT_R_EN_IQDUMP_8821C BIT(1)
+#define BIT_R_IQDATA_DUMP_8821C BIT(0)
+
+/* 2 REG_IQ_DUMP_1_8821C */
+
+#define BIT_SHIFT_R_WMAC_MASK_LA_MAC_1_8821C 0
+#define BIT_MASK_R_WMAC_MASK_LA_MAC_1_8821C 0xffffffffL
+#define BIT_R_WMAC_MASK_LA_MAC_1_8821C(x)                                      \
+	(((x) & BIT_MASK_R_WMAC_MASK_LA_MAC_1_8821C)                           \
+	 << BIT_SHIFT_R_WMAC_MASK_LA_MAC_1_8821C)
+#define BITS_R_WMAC_MASK_LA_MAC_1_8821C                                        \
+	(BIT_MASK_R_WMAC_MASK_LA_MAC_1_8821C                                   \
+	 << BIT_SHIFT_R_WMAC_MASK_LA_MAC_1_8821C)
+#define BIT_CLEAR_R_WMAC_MASK_LA_MAC_1_8821C(x)                                \
+	((x) & (~BITS_R_WMAC_MASK_LA_MAC_1_8821C))
+#define BIT_GET_R_WMAC_MASK_LA_MAC_1_8821C(x)                                  \
+	(((x) >> BIT_SHIFT_R_WMAC_MASK_LA_MAC_1_8821C) &                       \
+	 BIT_MASK_R_WMAC_MASK_LA_MAC_1_8821C)
+#define BIT_SET_R_WMAC_MASK_LA_MAC_1_8821C(x, v)                               \
+	(BIT_CLEAR_R_WMAC_MASK_LA_MAC_1_8821C(x) |                             \
+	 BIT_R_WMAC_MASK_LA_MAC_1_8821C(v))
+
+/* 2 REG_IQ_DUMP_2_8821C */
+
+#define BIT_SHIFT_R_WMAC_MATCH_REF_MAC_2_8821C 0
+#define BIT_MASK_R_WMAC_MATCH_REF_MAC_2_8821C 0xffffffffL
+#define BIT_R_WMAC_MATCH_REF_MAC_2_8821C(x)                                    \
+	(((x) & BIT_MASK_R_WMAC_MATCH_REF_MAC_2_8821C)                         \
+	 << BIT_SHIFT_R_WMAC_MATCH_REF_MAC_2_8821C)
+#define BITS_R_WMAC_MATCH_REF_MAC_2_8821C                                      \
+	(BIT_MASK_R_WMAC_MATCH_REF_MAC_2_8821C                                 \
+	 << BIT_SHIFT_R_WMAC_MATCH_REF_MAC_2_8821C)
+#define BIT_CLEAR_R_WMAC_MATCH_REF_MAC_2_8821C(x)                              \
+	((x) & (~BITS_R_WMAC_MATCH_REF_MAC_2_8821C))
+#define BIT_GET_R_WMAC_MATCH_REF_MAC_2_8821C(x)                                \
+	(((x) >> BIT_SHIFT_R_WMAC_MATCH_REF_MAC_2_8821C) &                     \
+	 BIT_MASK_R_WMAC_MATCH_REF_MAC_2_8821C)
+#define BIT_SET_R_WMAC_MATCH_REF_MAC_2_8821C(x, v)                             \
+	(BIT_CLEAR_R_WMAC_MATCH_REF_MAC_2_8821C(x) |                           \
+	 BIT_R_WMAC_MATCH_REF_MAC_2_8821C(v))
+
+/* 2 REG_WMAC_FTM_CTL_8821C */
+#define BIT_RXFTM_TXACK_SC_8821C BIT(6)
+#define BIT_RXFTM_TXACK_BW_8821C BIT(5)
+#define BIT_RXFTM_EN_8821C BIT(3)
+#define BIT_RXFTMREQ_BYDRV_8821C BIT(2)
+#define BIT_RXFTMREQ_EN_8821C BIT(1)
+#define BIT_FTM_EN_8821C BIT(0)
+
+/* 2 REG_WMAC_IQ_MDPK_FUNC_8821C */
+
+/* 2 REG_WMAC_OPTION_FUNCTION_8821C */
+
+#define BIT_SHIFT_R_OFDM_LEN_8821C 26
+#define BIT_MASK_R_OFDM_LEN_8821C 0x3f
+#define BIT_R_OFDM_LEN_8821C(x)                                                \
+	(((x) & BIT_MASK_R_OFDM_LEN_8821C) << BIT_SHIFT_R_OFDM_LEN_8821C)
+#define BITS_R_OFDM_LEN_8821C                                                  \
+	(BIT_MASK_R_OFDM_LEN_8821C << BIT_SHIFT_R_OFDM_LEN_8821C)
+#define BIT_CLEAR_R_OFDM_LEN_8821C(x) ((x) & (~BITS_R_OFDM_LEN_8821C))
+#define BIT_GET_R_OFDM_LEN_8821C(x)                                            \
+	(((x) >> BIT_SHIFT_R_OFDM_LEN_8821C) & BIT_MASK_R_OFDM_LEN_8821C)
+#define BIT_SET_R_OFDM_LEN_8821C(x, v)                                         \
+	(BIT_CLEAR_R_OFDM_LEN_8821C(x) | BIT_R_OFDM_LEN_8821C(v))
+
+#define BIT_SHIFT_R_CCK_LEN_8821C 0
+#define BIT_MASK_R_CCK_LEN_8821C 0xffff
+#define BIT_R_CCK_LEN_8821C(x)                                                 \
+	(((x) & BIT_MASK_R_CCK_LEN_8821C) << BIT_SHIFT_R_CCK_LEN_8821C)
+#define BITS_R_CCK_LEN_8821C                                                   \
+	(BIT_MASK_R_CCK_LEN_8821C << BIT_SHIFT_R_CCK_LEN_8821C)
+#define BIT_CLEAR_R_CCK_LEN_8821C(x) ((x) & (~BITS_R_CCK_LEN_8821C))
+#define BIT_GET_R_CCK_LEN_8821C(x)                                             \
+	(((x) >> BIT_SHIFT_R_CCK_LEN_8821C) & BIT_MASK_R_CCK_LEN_8821C)
+#define BIT_SET_R_CCK_LEN_8821C(x, v)                                          \
+	(BIT_CLEAR_R_CCK_LEN_8821C(x) | BIT_R_CCK_LEN_8821C(v))
+
+/* 2 REG_WMAC_OPTION_FUNCTION_1_8821C */
+
+#define BIT_SHIFT_R_WMAC_RXFIFO_FULL_TH_1_8821C 24
+#define BIT_MASK_R_WMAC_RXFIFO_FULL_TH_1_8821C 0xff
+#define BIT_R_WMAC_RXFIFO_FULL_TH_1_8821C(x)                                   \
+	(((x) & BIT_MASK_R_WMAC_RXFIFO_FULL_TH_1_8821C)                        \
+	 << BIT_SHIFT_R_WMAC_RXFIFO_FULL_TH_1_8821C)
+#define BITS_R_WMAC_RXFIFO_FULL_TH_1_8821C                                     \
+	(BIT_MASK_R_WMAC_RXFIFO_FULL_TH_1_8821C                                \
+	 << BIT_SHIFT_R_WMAC_RXFIFO_FULL_TH_1_8821C)
+#define BIT_CLEAR_R_WMAC_RXFIFO_FULL_TH_1_8821C(x)                             \
+	((x) & (~BITS_R_WMAC_RXFIFO_FULL_TH_1_8821C))
+#define BIT_GET_R_WMAC_RXFIFO_FULL_TH_1_8821C(x)                               \
+	(((x) >> BIT_SHIFT_R_WMAC_RXFIFO_FULL_TH_1_8821C) &                    \
+	 BIT_MASK_R_WMAC_RXFIFO_FULL_TH_1_8821C)
+#define BIT_SET_R_WMAC_RXFIFO_FULL_TH_1_8821C(x, v)                            \
+	(BIT_CLEAR_R_WMAC_RXFIFO_FULL_TH_1_8821C(x) |                          \
+	 BIT_R_WMAC_RXFIFO_FULL_TH_1_8821C(v))
+
+#define BIT_R_WMAC_RX_SYNCFIFO_SYNC_1_8821C BIT(23)
+#define BIT_R_WMAC_RXRST_DLY_1_8821C BIT(22)
+#define BIT_R_WMAC_SRCH_TXRPT_REF_DROP_1_8821C BIT(21)
+#define BIT_R_WMAC_SRCH_TXRPT_UA1_1_8821C BIT(20)
+#define BIT_R_WMAC_SRCH_TXRPT_TYPE_1_8821C BIT(19)
+#define BIT_R_WMAC_NDP_RST_1_8821C BIT(18)
+#define BIT_R_WMAC_POWINT_EN_1_8821C BIT(17)
+#define BIT_R_WMAC_SRCH_TXRPT_PERPKT_1_8821C BIT(16)
+#define BIT_R_WMAC_SRCH_TXRPT_MID_1_8821C BIT(15)
+#define BIT_R_WMAC_PFIN_TOEN_1_8821C BIT(14)
+#define BIT_R_WMAC_FIL_SECERR_1_8821C BIT(13)
+#define BIT_R_WMAC_FIL_CTLPKTLEN_1_8821C BIT(12)
+#define BIT_R_WMAC_FIL_FCTYPE_1_8821C BIT(11)
+#define BIT_R_WMAC_FIL_FCPROVER_1_8821C BIT(10)
+#define BIT_R_WMAC_PHYSTS_SNIF_1_8821C BIT(9)
+#define BIT_R_WMAC_PHYSTS_PLCP_1_8821C BIT(8)
+#define BIT_R_MAC_TCR_VBONF_RD_1_8821C BIT(7)
+#define BIT_R_WMAC_TCR_MPAR_NDP_1_8821C BIT(6)
+#define BIT_R_WMAC_NDP_FILTER_1_8821C BIT(5)
+#define BIT_R_WMAC_RXLEN_SEL_1_8821C BIT(4)
+#define BIT_R_WMAC_RXLEN_SEL1_1_8821C BIT(3)
+#define BIT_R_OFDM_FILTER_1_8821C BIT(2)
+#define BIT_R_WMAC_CHK_OFDM_LEN_1_8821C BIT(1)
+#define BIT_R_WMAC_CHK_CCK_LEN_1_8821C BIT(0)
+
+/* 2 REG_WMAC_OPTION_FUNCTION_2_8821C */
+
+#define BIT_SHIFT_R_WMAC_RX_FIL_LEN_2_8821C 0
+#define BIT_MASK_R_WMAC_RX_FIL_LEN_2_8821C 0xffff
+#define BIT_R_WMAC_RX_FIL_LEN_2_8821C(x)                                       \
+	(((x) & BIT_MASK_R_WMAC_RX_FIL_LEN_2_8821C)                            \
+	 << BIT_SHIFT_R_WMAC_RX_FIL_LEN_2_8821C)
+#define BITS_R_WMAC_RX_FIL_LEN_2_8821C                                         \
+	(BIT_MASK_R_WMAC_RX_FIL_LEN_2_8821C                                    \
+	 << BIT_SHIFT_R_WMAC_RX_FIL_LEN_2_8821C)
+#define BIT_CLEAR_R_WMAC_RX_FIL_LEN_2_8821C(x)                                 \
+	((x) & (~BITS_R_WMAC_RX_FIL_LEN_2_8821C))
+#define BIT_GET_R_WMAC_RX_FIL_LEN_2_8821C(x)                                   \
+	(((x) >> BIT_SHIFT_R_WMAC_RX_FIL_LEN_2_8821C) &                        \
+	 BIT_MASK_R_WMAC_RX_FIL_LEN_2_8821C)
+#define BIT_SET_R_WMAC_RX_FIL_LEN_2_8821C(x, v)                                \
+	(BIT_CLEAR_R_WMAC_RX_FIL_LEN_2_8821C(x) |                              \
+	 BIT_R_WMAC_RX_FIL_LEN_2_8821C(v))
+
+/* 2 REG_RX_FILTER_FUNCTION_8821C */
+#define BIT_R_WMAC_MHRDDY_LATCH_8821C BIT(14)
+#define BIT_R_WMAC_MHRDDY_CLR_8821C BIT(13)
+#define BIT_R_RXPKTCTL_FSM_BASED_MPDURDY1_8821C BIT(12)
+#define BIT_WMAC_DIS_VHT_PLCP_CHK_MU_8821C BIT(11)
+#define BIT_R_CHK_DELIMIT_LEN_8821C BIT(10)
+#define BIT_R_REAPTER_ADDR_MATCH_8821C BIT(9)
+#define BIT_R_RXPKTCTL_FSM_BASED_MPDURDY_8821C BIT(8)
+#define BIT_R_LATCH_MACHRDY_8821C BIT(7)
+#define BIT_R_WMAC_RXFIL_REND_8821C BIT(6)
+#define BIT_R_WMAC_MPDURDY_CLR_8821C BIT(5)
+#define BIT_R_WMAC_CLRRXSEC_8821C BIT(4)
+#define BIT_R_WMAC_RXFIL_RDEL_8821C BIT(3)
+#define BIT_R_WMAC_RXFIL_FCSE_8821C BIT(2)
+#define BIT_R_WMAC_RXFIL_MESH_DEL_8821C BIT(1)
+#define BIT_R_WMAC_RXFIL_MASKM_8821C BIT(0)
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NDP_SIG_8821C */
+
+#define BIT_SHIFT_R_WMAC_TXNDP_SIGB_8821C 0
+#define BIT_MASK_R_WMAC_TXNDP_SIGB_8821C 0x1fffff
+#define BIT_R_WMAC_TXNDP_SIGB_8821C(x)                                         \
+	(((x) & BIT_MASK_R_WMAC_TXNDP_SIGB_8821C)                              \
+	 << BIT_SHIFT_R_WMAC_TXNDP_SIGB_8821C)
+#define BITS_R_WMAC_TXNDP_SIGB_8821C                                           \
+	(BIT_MASK_R_WMAC_TXNDP_SIGB_8821C << BIT_SHIFT_R_WMAC_TXNDP_SIGB_8821C)
+#define BIT_CLEAR_R_WMAC_TXNDP_SIGB_8821C(x)                                   \
+	((x) & (~BITS_R_WMAC_TXNDP_SIGB_8821C))
+#define BIT_GET_R_WMAC_TXNDP_SIGB_8821C(x)                                     \
+	(((x) >> BIT_SHIFT_R_WMAC_TXNDP_SIGB_8821C) &                          \
+	 BIT_MASK_R_WMAC_TXNDP_SIGB_8821C)
+#define BIT_SET_R_WMAC_TXNDP_SIGB_8821C(x, v)                                  \
+	(BIT_CLEAR_R_WMAC_TXNDP_SIGB_8821C(x) | BIT_R_WMAC_TXNDP_SIGB_8821C(v))
+
+/* 2 REG_TXCMD_INFO_FOR_RSP_PKT_8821C */
+
+#define BIT_SHIFT_R_MAC_DBG_SHIFT_8821C 8
+#define BIT_MASK_R_MAC_DBG_SHIFT_8821C 0x7
+#define BIT_R_MAC_DBG_SHIFT_8821C(x)                                           \
+	(((x) & BIT_MASK_R_MAC_DBG_SHIFT_8821C)                                \
+	 << BIT_SHIFT_R_MAC_DBG_SHIFT_8821C)
+#define BITS_R_MAC_DBG_SHIFT_8821C                                             \
+	(BIT_MASK_R_MAC_DBG_SHIFT_8821C << BIT_SHIFT_R_MAC_DBG_SHIFT_8821C)
+#define BIT_CLEAR_R_MAC_DBG_SHIFT_8821C(x) ((x) & (~BITS_R_MAC_DBG_SHIFT_8821C))
+#define BIT_GET_R_MAC_DBG_SHIFT_8821C(x)                                       \
+	(((x) >> BIT_SHIFT_R_MAC_DBG_SHIFT_8821C) &                            \
+	 BIT_MASK_R_MAC_DBG_SHIFT_8821C)
+#define BIT_SET_R_MAC_DBG_SHIFT_8821C(x, v)                                    \
+	(BIT_CLEAR_R_MAC_DBG_SHIFT_8821C(x) | BIT_R_MAC_DBG_SHIFT_8821C(v))
+
+#define BIT_SHIFT_R_MAC_DBG_SEL_8821C 0
+#define BIT_MASK_R_MAC_DBG_SEL_8821C 0x3
+#define BIT_R_MAC_DBG_SEL_8821C(x)                                             \
+	(((x) & BIT_MASK_R_MAC_DBG_SEL_8821C) << BIT_SHIFT_R_MAC_DBG_SEL_8821C)
+#define BITS_R_MAC_DBG_SEL_8821C                                               \
+	(BIT_MASK_R_MAC_DBG_SEL_8821C << BIT_SHIFT_R_MAC_DBG_SEL_8821C)
+#define BIT_CLEAR_R_MAC_DBG_SEL_8821C(x) ((x) & (~BITS_R_MAC_DBG_SEL_8821C))
+#define BIT_GET_R_MAC_DBG_SEL_8821C(x)                                         \
+	(((x) >> BIT_SHIFT_R_MAC_DBG_SEL_8821C) & BIT_MASK_R_MAC_DBG_SEL_8821C)
+#define BIT_SET_R_MAC_DBG_SEL_8821C(x, v)                                      \
+	(BIT_CLEAR_R_MAC_DBG_SEL_8821C(x) | BIT_R_MAC_DBG_SEL_8821C(v))
+
+/* 2 REG_TXCMD_INFO_FOR_RSP_PKT_1_8821C */
+
+#define BIT_SHIFT_R_MAC_DEBUG_1_8821C 0
+#define BIT_MASK_R_MAC_DEBUG_1_8821C 0xffffffffL
+#define BIT_R_MAC_DEBUG_1_8821C(x)                                             \
+	(((x) & BIT_MASK_R_MAC_DEBUG_1_8821C) << BIT_SHIFT_R_MAC_DEBUG_1_8821C)
+#define BITS_R_MAC_DEBUG_1_8821C                                               \
+	(BIT_MASK_R_MAC_DEBUG_1_8821C << BIT_SHIFT_R_MAC_DEBUG_1_8821C)
+#define BIT_CLEAR_R_MAC_DEBUG_1_8821C(x) ((x) & (~BITS_R_MAC_DEBUG_1_8821C))
+#define BIT_GET_R_MAC_DEBUG_1_8821C(x)                                         \
+	(((x) >> BIT_SHIFT_R_MAC_DEBUG_1_8821C) & BIT_MASK_R_MAC_DEBUG_1_8821C)
+#define BIT_SET_R_MAC_DEBUG_1_8821C(x, v)                                      \
+	(BIT_CLEAR_R_MAC_DEBUG_1_8821C(x) | BIT_R_MAC_DEBUG_1_8821C(v))
+
+/* 2 REG_WSEC_OPTION_8821C */
+#define BIT_RXDEC_BM_MGNT_8821C BIT(22)
+#define BIT_TXENC_BM_MGNT_8821C BIT(21)
+#define BIT_RXDEC_UNI_MGNT_8821C BIT(20)
+#define BIT_TXENC_UNI_MGNT_8821C BIT(19)
+
+/* 2 REG_RTS_ADDRESS_0_8821C */
+
+/* 2 REG_RTS_ADDRESS_0_1_8821C */
+
+/* 2 REG_RTS_ADDRESS_1_8821C */
+
+/* 2 REG_RTS_ADDRESS_1_1_8821C */
+
+/* 2 REG_WL2LTECOEX_INDIRECT_ACCESS_CTRL_V1_8821C */
+#define BIT_LTECOEX_ACCESS_START_V1_8821C BIT(31)
+#define BIT_LTECOEX_WRITE_MODE_V1_8821C BIT(30)
+#define BIT_LTECOEX_READY_BIT_V1_8821C BIT(29)
+
+#define BIT_SHIFT_WRITE_BYTE_EN_V1_8821C 16
+#define BIT_MASK_WRITE_BYTE_EN_V1_8821C 0xf
+#define BIT_WRITE_BYTE_EN_V1_8821C(x)                                          \
+	(((x) & BIT_MASK_WRITE_BYTE_EN_V1_8821C)                               \
+	 << BIT_SHIFT_WRITE_BYTE_EN_V1_8821C)
+#define BITS_WRITE_BYTE_EN_V1_8821C                                            \
+	(BIT_MASK_WRITE_BYTE_EN_V1_8821C << BIT_SHIFT_WRITE_BYTE_EN_V1_8821C)
+#define BIT_CLEAR_WRITE_BYTE_EN_V1_8821C(x)                                    \
+	((x) & (~BITS_WRITE_BYTE_EN_V1_8821C))
+#define BIT_GET_WRITE_BYTE_EN_V1_8821C(x)                                      \
+	(((x) >> BIT_SHIFT_WRITE_BYTE_EN_V1_8821C) &                           \
+	 BIT_MASK_WRITE_BYTE_EN_V1_8821C)
+#define BIT_SET_WRITE_BYTE_EN_V1_8821C(x, v)                                   \
+	(BIT_CLEAR_WRITE_BYTE_EN_V1_8821C(x) | BIT_WRITE_BYTE_EN_V1_8821C(v))
+
+#define BIT_SHIFT_LTECOEX_REG_ADDR_V1_8821C 0
+#define BIT_MASK_LTECOEX_REG_ADDR_V1_8821C 0xffff
+#define BIT_LTECOEX_REG_ADDR_V1_8821C(x)                                       \
+	(((x) & BIT_MASK_LTECOEX_REG_ADDR_V1_8821C)                            \
+	 << BIT_SHIFT_LTECOEX_REG_ADDR_V1_8821C)
+#define BITS_LTECOEX_REG_ADDR_V1_8821C                                         \
+	(BIT_MASK_LTECOEX_REG_ADDR_V1_8821C                                    \
+	 << BIT_SHIFT_LTECOEX_REG_ADDR_V1_8821C)
+#define BIT_CLEAR_LTECOEX_REG_ADDR_V1_8821C(x)                                 \
+	((x) & (~BITS_LTECOEX_REG_ADDR_V1_8821C))
+#define BIT_GET_LTECOEX_REG_ADDR_V1_8821C(x)                                   \
+	(((x) >> BIT_SHIFT_LTECOEX_REG_ADDR_V1_8821C) &                        \
+	 BIT_MASK_LTECOEX_REG_ADDR_V1_8821C)
+#define BIT_SET_LTECOEX_REG_ADDR_V1_8821C(x, v)                                \
+	(BIT_CLEAR_LTECOEX_REG_ADDR_V1_8821C(x) |                              \
+	 BIT_LTECOEX_REG_ADDR_V1_8821C(v))
+
+/* 2 REG_WL2LTECOEX_INDIRECT_ACCESS_WRITE_DATA_V1_8821C */
+
+#define BIT_SHIFT_LTECOEX_W_DATA_V1_8821C 0
+#define BIT_MASK_LTECOEX_W_DATA_V1_8821C 0xffffffffL
+#define BIT_LTECOEX_W_DATA_V1_8821C(x)                                         \
+	(((x) & BIT_MASK_LTECOEX_W_DATA_V1_8821C)                              \
+	 << BIT_SHIFT_LTECOEX_W_DATA_V1_8821C)
+#define BITS_LTECOEX_W_DATA_V1_8821C                                           \
+	(BIT_MASK_LTECOEX_W_DATA_V1_8821C << BIT_SHIFT_LTECOEX_W_DATA_V1_8821C)
+#define BIT_CLEAR_LTECOEX_W_DATA_V1_8821C(x)                                   \
+	((x) & (~BITS_LTECOEX_W_DATA_V1_8821C))
+#define BIT_GET_LTECOEX_W_DATA_V1_8821C(x)                                     \
+	(((x) >> BIT_SHIFT_LTECOEX_W_DATA_V1_8821C) &                          \
+	 BIT_MASK_LTECOEX_W_DATA_V1_8821C)
+#define BIT_SET_LTECOEX_W_DATA_V1_8821C(x, v)                                  \
+	(BIT_CLEAR_LTECOEX_W_DATA_V1_8821C(x) | BIT_LTECOEX_W_DATA_V1_8821C(v))
+
+/* 2 REG_WL2LTECOEX_INDIRECT_ACCESS_READ_DATA_V1_8821C */
+
+#define BIT_SHIFT_LTECOEX_R_DATA_V1_8821C 0
+#define BIT_MASK_LTECOEX_R_DATA_V1_8821C 0xffffffffL
+#define BIT_LTECOEX_R_DATA_V1_8821C(x)                                         \
+	(((x) & BIT_MASK_LTECOEX_R_DATA_V1_8821C)                              \
+	 << BIT_SHIFT_LTECOEX_R_DATA_V1_8821C)
+#define BITS_LTECOEX_R_DATA_V1_8821C                                           \
+	(BIT_MASK_LTECOEX_R_DATA_V1_8821C << BIT_SHIFT_LTECOEX_R_DATA_V1_8821C)
+#define BIT_CLEAR_LTECOEX_R_DATA_V1_8821C(x)                                   \
+	((x) & (~BITS_LTECOEX_R_DATA_V1_8821C))
+#define BIT_GET_LTECOEX_R_DATA_V1_8821C(x)                                     \
+	(((x) >> BIT_SHIFT_LTECOEX_R_DATA_V1_8821C) &                          \
+	 BIT_MASK_LTECOEX_R_DATA_V1_8821C)
+#define BIT_SET_LTECOEX_R_DATA_V1_8821C(x, v)                                  \
+	(BIT_CLEAR_LTECOEX_R_DATA_V1_8821C(x) | BIT_LTECOEX_R_DATA_V1_8821C(v))
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_SDIO_TX_CTRL_8821C */
+
+#define BIT_SHIFT_SDIO_INT_TIMEOUT_8821C 16
+#define BIT_MASK_SDIO_INT_TIMEOUT_8821C 0xffff
+#define BIT_SDIO_INT_TIMEOUT_8821C(x)                                          \
+	(((x) & BIT_MASK_SDIO_INT_TIMEOUT_8821C)                               \
+	 << BIT_SHIFT_SDIO_INT_TIMEOUT_8821C)
+#define BITS_SDIO_INT_TIMEOUT_8821C                                            \
+	(BIT_MASK_SDIO_INT_TIMEOUT_8821C << BIT_SHIFT_SDIO_INT_TIMEOUT_8821C)
+#define BIT_CLEAR_SDIO_INT_TIMEOUT_8821C(x)                                    \
+	((x) & (~BITS_SDIO_INT_TIMEOUT_8821C))
+#define BIT_GET_SDIO_INT_TIMEOUT_8821C(x)                                      \
+	(((x) >> BIT_SHIFT_SDIO_INT_TIMEOUT_8821C) &                           \
+	 BIT_MASK_SDIO_INT_TIMEOUT_8821C)
+#define BIT_SET_SDIO_INT_TIMEOUT_8821C(x, v)                                   \
+	(BIT_CLEAR_SDIO_INT_TIMEOUT_8821C(x) | BIT_SDIO_INT_TIMEOUT_8821C(v))
+
+#define BIT_IO_ERR_STATUS_8821C BIT(15)
+#define BIT_REPLY_ERRCRC_IN_DATA_8821C BIT(9)
+#define BIT_EN_CMD53_OVERLAP_8821C BIT(8)
+#define BIT_REPLY_ERR_IN_R5_8821C BIT(7)
+#define BIT_R18A_EN_8821C BIT(6)
+#define BIT_SDIO_CMD_FORCE_VLD_8821C BIT(5)
+#define BIT_INIT_CMD_EN_8821C BIT(4)
+#define BIT_EN_RXDMA_MASK_INT_8821C BIT(2)
+#define BIT_EN_MASK_TIMER_8821C BIT(1)
+#define BIT_CMD_ERR_STOP_INT_EN_8821C BIT(0)
+
+/* 2 REG_SDIO_HIMR_8821C */
+#define BIT_SDIO_CRCERR_MSK_8821C BIT(31)
+#define BIT_SDIO_HSISR3_IND_MSK_8821C BIT(30)
+#define BIT_SDIO_HSISR2_IND_MSK_8821C BIT(29)
+#define BIT_SDIO_HEISR_IND_MSK_8821C BIT(28)
+#define BIT_SDIO_CTWEND_MSK_8821C BIT(27)
+#define BIT_SDIO_ATIMEND_E_MSK_8821C BIT(26)
+#define BIT_SDIIO_ATIMEND_MSK_8821C BIT(25)
+#define BIT_SDIO_OCPINT_MSK_8821C BIT(24)
+#define BIT_SDIO_PSTIMEOUT_MSK_8821C BIT(23)
+#define BIT_SDIO_GTINT4_MSK_8821C BIT(22)
+#define BIT_SDIO_GTINT3_MSK_8821C BIT(21)
+#define BIT_SDIO_HSISR_IND_MSK_8821C BIT(20)
+#define BIT_SDIO_CPWM2_MSK_8821C BIT(19)
+#define BIT_SDIO_CPWM1_MSK_8821C BIT(18)
+#define BIT_SDIO_C2HCMD_INT_MSK_8821C BIT(17)
+#define BIT_SDIO_BCNERLY_INT_MSK_8821C BIT(16)
+#define BIT_SDIO_TXBCNERR_MSK_8821C BIT(7)
+#define BIT_SDIO_TXBCNOK_MSK_8821C BIT(6)
+#define BIT_SDIO_RXFOVW_MSK_8821C BIT(5)
+#define BIT_SDIO_TXFOVW_MSK_8821C BIT(4)
+#define BIT_SDIO_RXERR_MSK_8821C BIT(3)
+#define BIT_SDIO_TXERR_MSK_8821C BIT(2)
+#define BIT_SDIO_AVAL_MSK_8821C BIT(1)
+#define BIT_RX_REQUEST_MSK_8821C BIT(0)
+
+/* 2 REG_SDIO_HISR_8821C */
+#define BIT_SDIO_CRCERR_8821C BIT(31)
+#define BIT_SDIO_HSISR3_IND_8821C BIT(30)
+#define BIT_SDIO_HSISR2_IND_8821C BIT(29)
+#define BIT_SDIO_HEISR_IND_8821C BIT(28)
+#define BIT_SDIO_CTWEND_8821C BIT(27)
+#define BIT_SDIO_ATIMEND_E_8821C BIT(26)
+#define BIT_SDIO_ATIMEND_8821C BIT(25)
+#define BIT_SDIO_OCPINT_8821C BIT(24)
+#define BIT_SDIO_PSTIMEOUT_8821C BIT(23)
+#define BIT_SDIO_GTINT4_8821C BIT(22)
+#define BIT_SDIO_GTINT3_8821C BIT(21)
+#define BIT_SDIO_HSISR_IND_8821C BIT(20)
+#define BIT_SDIO_CPWM2_8821C BIT(19)
+#define BIT_SDIO_CPWM1_8821C BIT(18)
+#define BIT_SDIO_C2HCMD_INT_8821C BIT(17)
+#define BIT_SDIO_BCNERLY_INT_8821C BIT(16)
+#define BIT_SDIO_TXBCNERR_8821C BIT(7)
+#define BIT_SDIO_TXBCNOK_8821C BIT(6)
+#define BIT_SDIO_RXFOVW_8821C BIT(5)
+#define BIT_SDIO_TXFOVW_8821C BIT(4)
+#define BIT_SDIO_RXERR_8821C BIT(3)
+#define BIT_SDIO_TXERR_8821C BIT(2)
+#define BIT_SDIO_AVAL_8821C BIT(1)
+#define BIT_RX_REQUEST_8821C BIT(0)
+
+/* 2 REG_SDIO_RX_REQ_LEN_8821C */
+
+#define BIT_SHIFT_RX_REQ_LEN_V1_8821C 0
+#define BIT_MASK_RX_REQ_LEN_V1_8821C 0x3ffff
+#define BIT_RX_REQ_LEN_V1_8821C(x)                                             \
+	(((x) & BIT_MASK_RX_REQ_LEN_V1_8821C) << BIT_SHIFT_RX_REQ_LEN_V1_8821C)
+#define BITS_RX_REQ_LEN_V1_8821C                                               \
+	(BIT_MASK_RX_REQ_LEN_V1_8821C << BIT_SHIFT_RX_REQ_LEN_V1_8821C)
+#define BIT_CLEAR_RX_REQ_LEN_V1_8821C(x) ((x) & (~BITS_RX_REQ_LEN_V1_8821C))
+#define BIT_GET_RX_REQ_LEN_V1_8821C(x)                                         \
+	(((x) >> BIT_SHIFT_RX_REQ_LEN_V1_8821C) & BIT_MASK_RX_REQ_LEN_V1_8821C)
+#define BIT_SET_RX_REQ_LEN_V1_8821C(x, v)                                      \
+	(BIT_CLEAR_RX_REQ_LEN_V1_8821C(x) | BIT_RX_REQ_LEN_V1_8821C(v))
+
+/* 2 REG_SDIO_FREE_TXPG_SEQ_V1_8821C */
+
+#define BIT_SHIFT_FREE_TXPG_SEQ_8821C 0
+#define BIT_MASK_FREE_TXPG_SEQ_8821C 0xff
+#define BIT_FREE_TXPG_SEQ_8821C(x)                                             \
+	(((x) & BIT_MASK_FREE_TXPG_SEQ_8821C) << BIT_SHIFT_FREE_TXPG_SEQ_8821C)
+#define BITS_FREE_TXPG_SEQ_8821C                                               \
+	(BIT_MASK_FREE_TXPG_SEQ_8821C << BIT_SHIFT_FREE_TXPG_SEQ_8821C)
+#define BIT_CLEAR_FREE_TXPG_SEQ_8821C(x) ((x) & (~BITS_FREE_TXPG_SEQ_8821C))
+#define BIT_GET_FREE_TXPG_SEQ_8821C(x)                                         \
+	(((x) >> BIT_SHIFT_FREE_TXPG_SEQ_8821C) & BIT_MASK_FREE_TXPG_SEQ_8821C)
+#define BIT_SET_FREE_TXPG_SEQ_8821C(x, v)                                      \
+	(BIT_CLEAR_FREE_TXPG_SEQ_8821C(x) | BIT_FREE_TXPG_SEQ_8821C(v))
+
+/* 2 REG_SDIO_FREE_TXPG_8821C */
+
+#define BIT_SHIFT_MID_FREEPG_V1_8821C 16
+#define BIT_MASK_MID_FREEPG_V1_8821C 0xfff
+#define BIT_MID_FREEPG_V1_8821C(x)                                             \
+	(((x) & BIT_MASK_MID_FREEPG_V1_8821C) << BIT_SHIFT_MID_FREEPG_V1_8821C)
+#define BITS_MID_FREEPG_V1_8821C                                               \
+	(BIT_MASK_MID_FREEPG_V1_8821C << BIT_SHIFT_MID_FREEPG_V1_8821C)
+#define BIT_CLEAR_MID_FREEPG_V1_8821C(x) ((x) & (~BITS_MID_FREEPG_V1_8821C))
+#define BIT_GET_MID_FREEPG_V1_8821C(x)                                         \
+	(((x) >> BIT_SHIFT_MID_FREEPG_V1_8821C) & BIT_MASK_MID_FREEPG_V1_8821C)
+#define BIT_SET_MID_FREEPG_V1_8821C(x, v)                                      \
+	(BIT_CLEAR_MID_FREEPG_V1_8821C(x) | BIT_MID_FREEPG_V1_8821C(v))
+
+#define BIT_SHIFT_HIQ_FREEPG_V1_8821C 0
+#define BIT_MASK_HIQ_FREEPG_V1_8821C 0xfff
+#define BIT_HIQ_FREEPG_V1_8821C(x)                                             \
+	(((x) & BIT_MASK_HIQ_FREEPG_V1_8821C) << BIT_SHIFT_HIQ_FREEPG_V1_8821C)
+#define BITS_HIQ_FREEPG_V1_8821C                                               \
+	(BIT_MASK_HIQ_FREEPG_V1_8821C << BIT_SHIFT_HIQ_FREEPG_V1_8821C)
+#define BIT_CLEAR_HIQ_FREEPG_V1_8821C(x) ((x) & (~BITS_HIQ_FREEPG_V1_8821C))
+#define BIT_GET_HIQ_FREEPG_V1_8821C(x)                                         \
+	(((x) >> BIT_SHIFT_HIQ_FREEPG_V1_8821C) & BIT_MASK_HIQ_FREEPG_V1_8821C)
+#define BIT_SET_HIQ_FREEPG_V1_8821C(x, v)                                      \
+	(BIT_CLEAR_HIQ_FREEPG_V1_8821C(x) | BIT_HIQ_FREEPG_V1_8821C(v))
+
+/* 2 REG_SDIO_FREE_TXPG2_8821C */
+
+#define BIT_SHIFT_PUB_FREEPG_V1_8821C 16
+#define BIT_MASK_PUB_FREEPG_V1_8821C 0xfff
+#define BIT_PUB_FREEPG_V1_8821C(x)                                             \
+	(((x) & BIT_MASK_PUB_FREEPG_V1_8821C) << BIT_SHIFT_PUB_FREEPG_V1_8821C)
+#define BITS_PUB_FREEPG_V1_8821C                                               \
+	(BIT_MASK_PUB_FREEPG_V1_8821C << BIT_SHIFT_PUB_FREEPG_V1_8821C)
+#define BIT_CLEAR_PUB_FREEPG_V1_8821C(x) ((x) & (~BITS_PUB_FREEPG_V1_8821C))
+#define BIT_GET_PUB_FREEPG_V1_8821C(x)                                         \
+	(((x) >> BIT_SHIFT_PUB_FREEPG_V1_8821C) & BIT_MASK_PUB_FREEPG_V1_8821C)
+#define BIT_SET_PUB_FREEPG_V1_8821C(x, v)                                      \
+	(BIT_CLEAR_PUB_FREEPG_V1_8821C(x) | BIT_PUB_FREEPG_V1_8821C(v))
+
+#define BIT_SHIFT_LOW_FREEPG_V1_8821C 0
+#define BIT_MASK_LOW_FREEPG_V1_8821C 0xfff
+#define BIT_LOW_FREEPG_V1_8821C(x)                                             \
+	(((x) & BIT_MASK_LOW_FREEPG_V1_8821C) << BIT_SHIFT_LOW_FREEPG_V1_8821C)
+#define BITS_LOW_FREEPG_V1_8821C                                               \
+	(BIT_MASK_LOW_FREEPG_V1_8821C << BIT_SHIFT_LOW_FREEPG_V1_8821C)
+#define BIT_CLEAR_LOW_FREEPG_V1_8821C(x) ((x) & (~BITS_LOW_FREEPG_V1_8821C))
+#define BIT_GET_LOW_FREEPG_V1_8821C(x)                                         \
+	(((x) >> BIT_SHIFT_LOW_FREEPG_V1_8821C) & BIT_MASK_LOW_FREEPG_V1_8821C)
+#define BIT_SET_LOW_FREEPG_V1_8821C(x, v)                                      \
+	(BIT_CLEAR_LOW_FREEPG_V1_8821C(x) | BIT_LOW_FREEPG_V1_8821C(v))
+
+/* 2 REG_SDIO_OQT_FREE_TXPG_V1_8821C */
+
+#define BIT_SHIFT_NOAC_OQT_FREEPG_V1_8821C 24
+#define BIT_MASK_NOAC_OQT_FREEPG_V1_8821C 0xff
+#define BIT_NOAC_OQT_FREEPG_V1_8821C(x)                                        \
+	(((x) & BIT_MASK_NOAC_OQT_FREEPG_V1_8821C)                             \
+	 << BIT_SHIFT_NOAC_OQT_FREEPG_V1_8821C)
+#define BITS_NOAC_OQT_FREEPG_V1_8821C                                          \
+	(BIT_MASK_NOAC_OQT_FREEPG_V1_8821C                                     \
+	 << BIT_SHIFT_NOAC_OQT_FREEPG_V1_8821C)
+#define BIT_CLEAR_NOAC_OQT_FREEPG_V1_8821C(x)                                  \
+	((x) & (~BITS_NOAC_OQT_FREEPG_V1_8821C))
+#define BIT_GET_NOAC_OQT_FREEPG_V1_8821C(x)                                    \
+	(((x) >> BIT_SHIFT_NOAC_OQT_FREEPG_V1_8821C) &                         \
+	 BIT_MASK_NOAC_OQT_FREEPG_V1_8821C)
+#define BIT_SET_NOAC_OQT_FREEPG_V1_8821C(x, v)                                 \
+	(BIT_CLEAR_NOAC_OQT_FREEPG_V1_8821C(x) |                               \
+	 BIT_NOAC_OQT_FREEPG_V1_8821C(v))
+
+#define BIT_SHIFT_AC_OQT_FREEPG_V1_8821C 16
+#define BIT_MASK_AC_OQT_FREEPG_V1_8821C 0xff
+#define BIT_AC_OQT_FREEPG_V1_8821C(x)                                          \
+	(((x) & BIT_MASK_AC_OQT_FREEPG_V1_8821C)                               \
+	 << BIT_SHIFT_AC_OQT_FREEPG_V1_8821C)
+#define BITS_AC_OQT_FREEPG_V1_8821C                                            \
+	(BIT_MASK_AC_OQT_FREEPG_V1_8821C << BIT_SHIFT_AC_OQT_FREEPG_V1_8821C)
+#define BIT_CLEAR_AC_OQT_FREEPG_V1_8821C(x)                                    \
+	((x) & (~BITS_AC_OQT_FREEPG_V1_8821C))
+#define BIT_GET_AC_OQT_FREEPG_V1_8821C(x)                                      \
+	(((x) >> BIT_SHIFT_AC_OQT_FREEPG_V1_8821C) &                           \
+	 BIT_MASK_AC_OQT_FREEPG_V1_8821C)
+#define BIT_SET_AC_OQT_FREEPG_V1_8821C(x, v)                                   \
+	(BIT_CLEAR_AC_OQT_FREEPG_V1_8821C(x) | BIT_AC_OQT_FREEPG_V1_8821C(v))
+
+#define BIT_SHIFT_EXQ_FREEPG_V1_8821C 0
+#define BIT_MASK_EXQ_FREEPG_V1_8821C 0xfff
+#define BIT_EXQ_FREEPG_V1_8821C(x)                                             \
+	(((x) & BIT_MASK_EXQ_FREEPG_V1_8821C) << BIT_SHIFT_EXQ_FREEPG_V1_8821C)
+#define BITS_EXQ_FREEPG_V1_8821C                                               \
+	(BIT_MASK_EXQ_FREEPG_V1_8821C << BIT_SHIFT_EXQ_FREEPG_V1_8821C)
+#define BIT_CLEAR_EXQ_FREEPG_V1_8821C(x) ((x) & (~BITS_EXQ_FREEPG_V1_8821C))
+#define BIT_GET_EXQ_FREEPG_V1_8821C(x)                                         \
+	(((x) >> BIT_SHIFT_EXQ_FREEPG_V1_8821C) & BIT_MASK_EXQ_FREEPG_V1_8821C)
+#define BIT_SET_EXQ_FREEPG_V1_8821C(x, v)                                      \
+	(BIT_CLEAR_EXQ_FREEPG_V1_8821C(x) | BIT_EXQ_FREEPG_V1_8821C(v))
+
+/* 2 REG_SDIO_HTSFR_INFO_8821C */
+
+#define BIT_SHIFT_HTSFR1_8821C 16
+#define BIT_MASK_HTSFR1_8821C 0xffff
+#define BIT_HTSFR1_8821C(x)                                                    \
+	(((x) & BIT_MASK_HTSFR1_8821C) << BIT_SHIFT_HTSFR1_8821C)
+#define BITS_HTSFR1_8821C (BIT_MASK_HTSFR1_8821C << BIT_SHIFT_HTSFR1_8821C)
+#define BIT_CLEAR_HTSFR1_8821C(x) ((x) & (~BITS_HTSFR1_8821C))
+#define BIT_GET_HTSFR1_8821C(x)                                                \
+	(((x) >> BIT_SHIFT_HTSFR1_8821C) & BIT_MASK_HTSFR1_8821C)
+#define BIT_SET_HTSFR1_8821C(x, v)                                             \
+	(BIT_CLEAR_HTSFR1_8821C(x) | BIT_HTSFR1_8821C(v))
+
+#define BIT_SHIFT_HTSFR0_8821C 0
+#define BIT_MASK_HTSFR0_8821C 0xffff
+#define BIT_HTSFR0_8821C(x)                                                    \
+	(((x) & BIT_MASK_HTSFR0_8821C) << BIT_SHIFT_HTSFR0_8821C)
+#define BITS_HTSFR0_8821C (BIT_MASK_HTSFR0_8821C << BIT_SHIFT_HTSFR0_8821C)
+#define BIT_CLEAR_HTSFR0_8821C(x) ((x) & (~BITS_HTSFR0_8821C))
+#define BIT_GET_HTSFR0_8821C(x)                                                \
+	(((x) >> BIT_SHIFT_HTSFR0_8821C) & BIT_MASK_HTSFR0_8821C)
+#define BIT_SET_HTSFR0_8821C(x, v)                                             \
+	(BIT_CLEAR_HTSFR0_8821C(x) | BIT_HTSFR0_8821C(v))
+
+/* 2 REG_SDIO_HCPWM1_V2_8821C */
+#define BIT_TOGGLE_8821C BIT(7)
+#define BIT_CUR_PS_8821C BIT(0)
+
+/* 2 REG_SDIO_HCPWM2_V2_8821C */
+
+/* 2 REG_SDIO_INDIRECT_REG_CFG_8821C */
+#define BIT_INDIRECT_REG_RDY_8821C BIT(20)
+#define BIT_INDIRECT_REG_R_8821C BIT(19)
+#define BIT_INDIRECT_REG_W_8821C BIT(18)
+
+#define BIT_SHIFT_INDIRECT_REG_SIZE_8821C 16
+#define BIT_MASK_INDIRECT_REG_SIZE_8821C 0x3
+#define BIT_INDIRECT_REG_SIZE_8821C(x)                                         \
+	(((x) & BIT_MASK_INDIRECT_REG_SIZE_8821C)                              \
+	 << BIT_SHIFT_INDIRECT_REG_SIZE_8821C)
+#define BITS_INDIRECT_REG_SIZE_8821C                                           \
+	(BIT_MASK_INDIRECT_REG_SIZE_8821C << BIT_SHIFT_INDIRECT_REG_SIZE_8821C)
+#define BIT_CLEAR_INDIRECT_REG_SIZE_8821C(x)                                   \
+	((x) & (~BITS_INDIRECT_REG_SIZE_8821C))
+#define BIT_GET_INDIRECT_REG_SIZE_8821C(x)                                     \
+	(((x) >> BIT_SHIFT_INDIRECT_REG_SIZE_8821C) &                          \
+	 BIT_MASK_INDIRECT_REG_SIZE_8821C)
+#define BIT_SET_INDIRECT_REG_SIZE_8821C(x, v)                                  \
+	(BIT_CLEAR_INDIRECT_REG_SIZE_8821C(x) | BIT_INDIRECT_REG_SIZE_8821C(v))
+
+#define BIT_SHIFT_INDIRECT_REG_ADDR_8821C 0
+#define BIT_MASK_INDIRECT_REG_ADDR_8821C 0xffff
+#define BIT_INDIRECT_REG_ADDR_8821C(x)                                         \
+	(((x) & BIT_MASK_INDIRECT_REG_ADDR_8821C)                              \
+	 << BIT_SHIFT_INDIRECT_REG_ADDR_8821C)
+#define BITS_INDIRECT_REG_ADDR_8821C                                           \
+	(BIT_MASK_INDIRECT_REG_ADDR_8821C << BIT_SHIFT_INDIRECT_REG_ADDR_8821C)
+#define BIT_CLEAR_INDIRECT_REG_ADDR_8821C(x)                                   \
+	((x) & (~BITS_INDIRECT_REG_ADDR_8821C))
+#define BIT_GET_INDIRECT_REG_ADDR_8821C(x)                                     \
+	(((x) >> BIT_SHIFT_INDIRECT_REG_ADDR_8821C) &                          \
+	 BIT_MASK_INDIRECT_REG_ADDR_8821C)
+#define BIT_SET_INDIRECT_REG_ADDR_8821C(x, v)                                  \
+	(BIT_CLEAR_INDIRECT_REG_ADDR_8821C(x) | BIT_INDIRECT_REG_ADDR_8821C(v))
+
+/* 2 REG_SDIO_INDIRECT_REG_DATA_8821C */
+
+#define BIT_SHIFT_INDIRECT_REG_DATA_8821C 0
+#define BIT_MASK_INDIRECT_REG_DATA_8821C 0xffffffffL
+#define BIT_INDIRECT_REG_DATA_8821C(x)                                         \
+	(((x) & BIT_MASK_INDIRECT_REG_DATA_8821C)                              \
+	 << BIT_SHIFT_INDIRECT_REG_DATA_8821C)
+#define BITS_INDIRECT_REG_DATA_8821C                                           \
+	(BIT_MASK_INDIRECT_REG_DATA_8821C << BIT_SHIFT_INDIRECT_REG_DATA_8821C)
+#define BIT_CLEAR_INDIRECT_REG_DATA_8821C(x)                                   \
+	((x) & (~BITS_INDIRECT_REG_DATA_8821C))
+#define BIT_GET_INDIRECT_REG_DATA_8821C(x)                                     \
+	(((x) >> BIT_SHIFT_INDIRECT_REG_DATA_8821C) &                          \
+	 BIT_MASK_INDIRECT_REG_DATA_8821C)
+#define BIT_SET_INDIRECT_REG_DATA_8821C(x, v)                                  \
+	(BIT_CLEAR_INDIRECT_REG_DATA_8821C(x) | BIT_INDIRECT_REG_DATA_8821C(v))
+
+/* 2 REG_SDIO_H2C_8821C */
+
+#define BIT_SHIFT_SDIO_H2C_MSG_8821C 0
+#define BIT_MASK_SDIO_H2C_MSG_8821C 0xffffffffL
+#define BIT_SDIO_H2C_MSG_8821C(x)                                              \
+	(((x) & BIT_MASK_SDIO_H2C_MSG_8821C) << BIT_SHIFT_SDIO_H2C_MSG_8821C)
+#define BITS_SDIO_H2C_MSG_8821C                                                \
+	(BIT_MASK_SDIO_H2C_MSG_8821C << BIT_SHIFT_SDIO_H2C_MSG_8821C)
+#define BIT_CLEAR_SDIO_H2C_MSG_8821C(x) ((x) & (~BITS_SDIO_H2C_MSG_8821C))
+#define BIT_GET_SDIO_H2C_MSG_8821C(x)                                          \
+	(((x) >> BIT_SHIFT_SDIO_H2C_MSG_8821C) & BIT_MASK_SDIO_H2C_MSG_8821C)
+#define BIT_SET_SDIO_H2C_MSG_8821C(x, v)                                       \
+	(BIT_CLEAR_SDIO_H2C_MSG_8821C(x) | BIT_SDIO_H2C_MSG_8821C(v))
+
+/* 2 REG_SDIO_C2H_8821C */
+
+#define BIT_SHIFT_SDIO_C2H_MSG_8821C 0
+#define BIT_MASK_SDIO_C2H_MSG_8821C 0xffffffffL
+#define BIT_SDIO_C2H_MSG_8821C(x)                                              \
+	(((x) & BIT_MASK_SDIO_C2H_MSG_8821C) << BIT_SHIFT_SDIO_C2H_MSG_8821C)
+#define BITS_SDIO_C2H_MSG_8821C                                                \
+	(BIT_MASK_SDIO_C2H_MSG_8821C << BIT_SHIFT_SDIO_C2H_MSG_8821C)
+#define BIT_CLEAR_SDIO_C2H_MSG_8821C(x) ((x) & (~BITS_SDIO_C2H_MSG_8821C))
+#define BIT_GET_SDIO_C2H_MSG_8821C(x)                                          \
+	(((x) >> BIT_SHIFT_SDIO_C2H_MSG_8821C) & BIT_MASK_SDIO_C2H_MSG_8821C)
+#define BIT_SET_SDIO_C2H_MSG_8821C(x, v)                                       \
+	(BIT_CLEAR_SDIO_C2H_MSG_8821C(x) | BIT_SDIO_C2H_MSG_8821C(v))
+
+/* 2 REG_SDIO_HRPWM1_8821C */
+#define BIT_TOGGLE_8821C BIT(7)
+#define BIT_ACK_8821C BIT(6)
+#define BIT_REQ_PS_8821C BIT(0)
+
+/* 2 REG_SDIO_HRPWM2_8821C */
+
+/* 2 REG_SDIO_HPS_CLKR_8821C */
+
+/* 2 REG_SDIO_BUS_CTRL_8821C */
+#define BIT_PAD_CLK_XHGE_EN_8821C BIT(3)
+#define BIT_INTER_CLK_EN_8821C BIT(2)
+#define BIT_EN_RPT_TXCRC_8821C BIT(1)
+#define BIT_DIS_RXDMA_STS_8821C BIT(0)
+
+/* 2 REG_SDIO_HSUS_CTRL_8821C */
+#define BIT_INTR_CTRL_8821C BIT(4)
+#define BIT_SDIO_VOLTAGE_8821C BIT(3)
+#define BIT_BYPASS_INIT_8821C BIT(2)
+#define BIT_HCI_RESUME_RDY_8821C BIT(1)
+#define BIT_HCI_SUS_REQ_8821C BIT(0)
+
+/* 2 REG_SDIO_RESPONSE_TIMER_8821C */
+
+#define BIT_SHIFT_CMDIN_2RESP_TIMER_8821C 0
+#define BIT_MASK_CMDIN_2RESP_TIMER_8821C 0xffff
+#define BIT_CMDIN_2RESP_TIMER_8821C(x)                                         \
+	(((x) & BIT_MASK_CMDIN_2RESP_TIMER_8821C)                              \
+	 << BIT_SHIFT_CMDIN_2RESP_TIMER_8821C)
+#define BITS_CMDIN_2RESP_TIMER_8821C                                           \
+	(BIT_MASK_CMDIN_2RESP_TIMER_8821C << BIT_SHIFT_CMDIN_2RESP_TIMER_8821C)
+#define BIT_CLEAR_CMDIN_2RESP_TIMER_8821C(x)                                   \
+	((x) & (~BITS_CMDIN_2RESP_TIMER_8821C))
+#define BIT_GET_CMDIN_2RESP_TIMER_8821C(x)                                     \
+	(((x) >> BIT_SHIFT_CMDIN_2RESP_TIMER_8821C) &                          \
+	 BIT_MASK_CMDIN_2RESP_TIMER_8821C)
+#define BIT_SET_CMDIN_2RESP_TIMER_8821C(x, v)                                  \
+	(BIT_CLEAR_CMDIN_2RESP_TIMER_8821C(x) | BIT_CMDIN_2RESP_TIMER_8821C(v))
+
+/* 2 REG_SDIO_CMD_CRC_8821C */
+
+#define BIT_SHIFT_SDIO_CMD_CRC_V1_8821C 0
+#define BIT_MASK_SDIO_CMD_CRC_V1_8821C 0xff
+#define BIT_SDIO_CMD_CRC_V1_8821C(x)                                           \
+	(((x) & BIT_MASK_SDIO_CMD_CRC_V1_8821C)                                \
+	 << BIT_SHIFT_SDIO_CMD_CRC_V1_8821C)
+#define BITS_SDIO_CMD_CRC_V1_8821C                                             \
+	(BIT_MASK_SDIO_CMD_CRC_V1_8821C << BIT_SHIFT_SDIO_CMD_CRC_V1_8821C)
+#define BIT_CLEAR_SDIO_CMD_CRC_V1_8821C(x) ((x) & (~BITS_SDIO_CMD_CRC_V1_8821C))
+#define BIT_GET_SDIO_CMD_CRC_V1_8821C(x)                                       \
+	(((x) >> BIT_SHIFT_SDIO_CMD_CRC_V1_8821C) &                            \
+	 BIT_MASK_SDIO_CMD_CRC_V1_8821C)
+#define BIT_SET_SDIO_CMD_CRC_V1_8821C(x, v)                                    \
+	(BIT_CLEAR_SDIO_CMD_CRC_V1_8821C(x) | BIT_SDIO_CMD_CRC_V1_8821C(v))
+
+/* 2 REG_SDIO_HSISR_8821C */
+#define BIT_DRV_WLAN_INT_CLR_8821C BIT(1)
+#define BIT_DRV_WLAN_INT_8821C BIT(0)
+
+/* 2 REG_SDIO_ERR_RPT_8821C */
+#define BIT_HR_FF_OVF_8821C BIT(6)
+#define BIT_HR_FF_UDN_8821C BIT(5)
+#define BIT_TXDMA_BUSY_ERR_8821C BIT(4)
+#define BIT_TXDMA_VLD_ERR_8821C BIT(3)
+#define BIT_QSEL_UNKNOWN_ERR_8821C BIT(2)
+#define BIT_QSEL_MIS_ERR_8821C BIT(1)
+#define BIT_SDIO_OVERRD_ERR_8821C BIT(0)
+
+/* 2 REG_SDIO_CMD_ERRCNT_8821C */
+
+#define BIT_SHIFT_CMD_CRC_ERR_CNT_8821C 0
+#define BIT_MASK_CMD_CRC_ERR_CNT_8821C 0xff
+#define BIT_CMD_CRC_ERR_CNT_8821C(x)                                           \
+	(((x) & BIT_MASK_CMD_CRC_ERR_CNT_8821C)                                \
+	 << BIT_SHIFT_CMD_CRC_ERR_CNT_8821C)
+#define BITS_CMD_CRC_ERR_CNT_8821C                                             \
+	(BIT_MASK_CMD_CRC_ERR_CNT_8821C << BIT_SHIFT_CMD_CRC_ERR_CNT_8821C)
+#define BIT_CLEAR_CMD_CRC_ERR_CNT_8821C(x) ((x) & (~BITS_CMD_CRC_ERR_CNT_8821C))
+#define BIT_GET_CMD_CRC_ERR_CNT_8821C(x)                                       \
+	(((x) >> BIT_SHIFT_CMD_CRC_ERR_CNT_8821C) &                            \
+	 BIT_MASK_CMD_CRC_ERR_CNT_8821C)
+#define BIT_SET_CMD_CRC_ERR_CNT_8821C(x, v)                                    \
+	(BIT_CLEAR_CMD_CRC_ERR_CNT_8821C(x) | BIT_CMD_CRC_ERR_CNT_8821C(v))
+
+/* 2 REG_SDIO_DATA_ERRCNT_8821C */
+
+#define BIT_SHIFT_DATA_CRC_ERR_CNT_8821C 0
+#define BIT_MASK_DATA_CRC_ERR_CNT_8821C 0xff
+#define BIT_DATA_CRC_ERR_CNT_8821C(x)                                          \
+	(((x) & BIT_MASK_DATA_CRC_ERR_CNT_8821C)                               \
+	 << BIT_SHIFT_DATA_CRC_ERR_CNT_8821C)
+#define BITS_DATA_CRC_ERR_CNT_8821C                                            \
+	(BIT_MASK_DATA_CRC_ERR_CNT_8821C << BIT_SHIFT_DATA_CRC_ERR_CNT_8821C)
+#define BIT_CLEAR_DATA_CRC_ERR_CNT_8821C(x)                                    \
+	((x) & (~BITS_DATA_CRC_ERR_CNT_8821C))
+#define BIT_GET_DATA_CRC_ERR_CNT_8821C(x)                                      \
+	(((x) >> BIT_SHIFT_DATA_CRC_ERR_CNT_8821C) &                           \
+	 BIT_MASK_DATA_CRC_ERR_CNT_8821C)
+#define BIT_SET_DATA_CRC_ERR_CNT_8821C(x, v)                                   \
+	(BIT_CLEAR_DATA_CRC_ERR_CNT_8821C(x) | BIT_DATA_CRC_ERR_CNT_8821C(v))
+
+/* 2 REG_SDIO_CMD_ERR_CONTENT_8821C */
+
+#define BIT_SHIFT_SDIO_CMD_ERR_CONTENT_8821C 0
+#define BIT_MASK_SDIO_CMD_ERR_CONTENT_8821C 0xffffffffffL
+#define BIT_SDIO_CMD_ERR_CONTENT_8821C(x)                                      \
+	(((x) & BIT_MASK_SDIO_CMD_ERR_CONTENT_8821C)                           \
+	 << BIT_SHIFT_SDIO_CMD_ERR_CONTENT_8821C)
+#define BITS_SDIO_CMD_ERR_CONTENT_8821C                                        \
+	(BIT_MASK_SDIO_CMD_ERR_CONTENT_8821C                                   \
+	 << BIT_SHIFT_SDIO_CMD_ERR_CONTENT_8821C)
+#define BIT_CLEAR_SDIO_CMD_ERR_CONTENT_8821C(x)                                \
+	((x) & (~BITS_SDIO_CMD_ERR_CONTENT_8821C))
+#define BIT_GET_SDIO_CMD_ERR_CONTENT_8821C(x)                                  \
+	(((x) >> BIT_SHIFT_SDIO_CMD_ERR_CONTENT_8821C) &                       \
+	 BIT_MASK_SDIO_CMD_ERR_CONTENT_8821C)
+#define BIT_SET_SDIO_CMD_ERR_CONTENT_8821C(x, v)                               \
+	(BIT_CLEAR_SDIO_CMD_ERR_CONTENT_8821C(x) |                             \
+	 BIT_SDIO_CMD_ERR_CONTENT_8821C(v))
+
+/* 2 REG_SDIO_CRC_ERR_IDX_8821C */
+#define BIT_D3_CRC_ERR_8821C BIT(4)
+#define BIT_D2_CRC_ERR_8821C BIT(3)
+#define BIT_D1_CRC_ERR_8821C BIT(2)
+#define BIT_D0_CRC_ERR_8821C BIT(1)
+#define BIT_CMD_CRC_ERR_8821C BIT(0)
+
+/* 2 REG_SDIO_DATA_CRC_8821C */
+
+#define BIT_SHIFT_SDIO_DATA_CRC_8821C 0
+#define BIT_MASK_SDIO_DATA_CRC_8821C 0xffff
+#define BIT_SDIO_DATA_CRC_8821C(x)                                             \
+	(((x) & BIT_MASK_SDIO_DATA_CRC_8821C) << BIT_SHIFT_SDIO_DATA_CRC_8821C)
+#define BITS_SDIO_DATA_CRC_8821C                                               \
+	(BIT_MASK_SDIO_DATA_CRC_8821C << BIT_SHIFT_SDIO_DATA_CRC_8821C)
+#define BIT_CLEAR_SDIO_DATA_CRC_8821C(x) ((x) & (~BITS_SDIO_DATA_CRC_8821C))
+#define BIT_GET_SDIO_DATA_CRC_8821C(x)                                         \
+	(((x) >> BIT_SHIFT_SDIO_DATA_CRC_8821C) & BIT_MASK_SDIO_DATA_CRC_8821C)
+#define BIT_SET_SDIO_DATA_CRC_8821C(x, v)                                      \
+	(BIT_CLEAR_SDIO_DATA_CRC_8821C(x) | BIT_SDIO_DATA_CRC_8821C(v))
+
+/* 2 REG_SDIO_DATA_REPLY_TIME_8821C */
+
+#define BIT_SHIFT_SDIO_DATA_REPLY_TIME_8821C 0
+#define BIT_MASK_SDIO_DATA_REPLY_TIME_8821C 0x7
+#define BIT_SDIO_DATA_REPLY_TIME_8821C(x)                                      \
+	(((x) & BIT_MASK_SDIO_DATA_REPLY_TIME_8821C)                           \
+	 << BIT_SHIFT_SDIO_DATA_REPLY_TIME_8821C)
+#define BITS_SDIO_DATA_REPLY_TIME_8821C                                        \
+	(BIT_MASK_SDIO_DATA_REPLY_TIME_8821C                                   \
+	 << BIT_SHIFT_SDIO_DATA_REPLY_TIME_8821C)
+#define BIT_CLEAR_SDIO_DATA_REPLY_TIME_8821C(x)                                \
+	((x) & (~BITS_SDIO_DATA_REPLY_TIME_8821C))
+#define BIT_GET_SDIO_DATA_REPLY_TIME_8821C(x)                                  \
+	(((x) >> BIT_SHIFT_SDIO_DATA_REPLY_TIME_8821C) &                       \
+	 BIT_MASK_SDIO_DATA_REPLY_TIME_8821C)
+#define BIT_SET_SDIO_DATA_REPLY_TIME_8821C(x, v)                               \
+	(BIT_CLEAR_SDIO_DATA_REPLY_TIME_8821C(x) |                             \
+	 BIT_SDIO_DATA_REPLY_TIME_8821C(v))
+
+#endif
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/halmac/halmac_bit_8822b.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/halmac/halmac_bit_8822b.h
--- linux-5.6.3/3rdparty/rtl8821ce/hal/halmac/halmac_bit_8822b.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/halmac/halmac_bit_8822b.h	2020-04-10 16:35:06.808659694 +0300
@@ -0,0 +1,17870 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ ******************************************************************************/
+
+#ifndef __INC_HALMAC_BIT_8822B_H
+#define __INC_HALMAC_BIT_8822B_H
+
+#define CPU_OPT_WIDTH 0x1F
+
+/* 2 REG_NOT_VALID_8822B */
+
+/* 2 REG_SYS_ISO_CTRL_8822B */
+#define BIT_PWC_EV12V_8822B BIT(15)
+#define BIT_PWC_EV25V_8822B BIT(14)
+#define BIT_PA33V_EN_8822B BIT(13)
+#define BIT_PA12V_EN_8822B BIT(12)
+#define BIT_UA33V_EN_8822B BIT(11)
+#define BIT_UA12V_EN_8822B BIT(10)
+#define BIT_ISO_RFDIO_8822B BIT(9)
+#define BIT_ISO_EB2CORE_8822B BIT(8)
+#define BIT_ISO_DIOE_8822B BIT(7)
+#define BIT_ISO_WLPON2PP_8822B BIT(6)
+#define BIT_ISO_IP2MAC_WA2PP_8822B BIT(5)
+#define BIT_ISO_PD2CORE_8822B BIT(4)
+#define BIT_ISO_PA2PCIE_8822B BIT(3)
+#define BIT_ISO_UD2CORE_8822B BIT(2)
+#define BIT_ISO_UA2USB_8822B BIT(1)
+#define BIT_ISO_WD2PP_8822B BIT(0)
+
+/* 2 REG_SYS_FUNC_EN_8822B */
+#define BIT_FEN_MREGEN_8822B BIT(15)
+#define BIT_FEN_HWPDN_8822B BIT(14)
+#define BIT_EN_25_1_8822B BIT(13)
+#define BIT_FEN_ELDR_8822B BIT(12)
+#define BIT_FEN_DCORE_8822B BIT(11)
+#define BIT_FEN_CPUEN_8822B BIT(10)
+#define BIT_FEN_DIOE_8822B BIT(9)
+#define BIT_FEN_PCIED_8822B BIT(8)
+#define BIT_FEN_PPLL_8822B BIT(7)
+#define BIT_FEN_PCIEA_8822B BIT(6)
+#define BIT_FEN_DIO_PCIE_8822B BIT(5)
+#define BIT_FEN_USBD_8822B BIT(4)
+#define BIT_FEN_UPLL_8822B BIT(3)
+#define BIT_FEN_USBA_8822B BIT(2)
+#define BIT_FEN_BB_GLB_RSTN_8822B BIT(1)
+#define BIT_FEN_BBRSTB_8822B BIT(0)
+
+/* 2 REG_SYS_PW_CTRL_8822B */
+#define BIT_SOP_EABM_8822B BIT(31)
+#define BIT_SOP_ACKF_8822B BIT(30)
+#define BIT_SOP_ERCK_8822B BIT(29)
+#define BIT_SOP_ESWR_8822B BIT(28)
+#define BIT_SOP_PWMM_8822B BIT(27)
+#define BIT_SOP_EECK_8822B BIT(26)
+#define BIT_SOP_EXTL_8822B BIT(24)
+#define BIT_SYM_OP_RING_12M_8822B BIT(22)
+#define BIT_ROP_SWPR_8822B BIT(21)
+#define BIT_DIS_HW_LPLDM_8822B BIT(20)
+#define BIT_OPT_SWRST_WLMCU_8822B BIT(19)
+#define BIT_RDY_SYSPWR_8822B BIT(17)
+#define BIT_EN_WLON_8822B BIT(16)
+#define BIT_APDM_HPDN_8822B BIT(15)
+#define BIT_AFSM_PCIE_SUS_EN_8822B BIT(12)
+#define BIT_AFSM_WLSUS_EN_8822B BIT(11)
+#define BIT_APFM_SWLPS_8822B BIT(10)
+#define BIT_APFM_OFFMAC_8822B BIT(9)
+#define BIT_APFN_ONMAC_8822B BIT(8)
+#define BIT_CHIP_PDN_EN_8822B BIT(7)
+#define BIT_RDY_MACDIS_8822B BIT(6)
+#define BIT_RING_CLK_12M_EN_8822B BIT(4)
+#define BIT_PFM_WOWL_8822B BIT(3)
+#define BIT_PFM_LDKP_8822B BIT(2)
+#define BIT_WL_HCI_ALD_8822B BIT(1)
+#define BIT_PFM_LDALL_8822B BIT(0)
+
+/* 2 REG_SYS_CLK_CTRL_8822B */
+#define BIT_LDO_DUMMY_8822B BIT(15)
+#define BIT_CPU_CLK_EN_8822B BIT(14)
+#define BIT_SYMREG_CLK_EN_8822B BIT(13)
+#define BIT_HCI_CLK_EN_8822B BIT(12)
+#define BIT_MAC_CLK_EN_8822B BIT(11)
+#define BIT_SEC_CLK_EN_8822B BIT(10)
+#define BIT_PHY_SSC_RSTB_8822B BIT(9)
+#define BIT_EXT_32K_EN_8822B BIT(8)
+#define BIT_WL_CLK_TEST_8822B BIT(7)
+#define BIT_OP_SPS_PWM_EN_8822B BIT(6)
+#define BIT_LOADER_CLK_EN_8822B BIT(5)
+#define BIT_MACSLP_8822B BIT(4)
+#define BIT_WAKEPAD_EN_8822B BIT(3)
+#define BIT_ROMD16V_EN_8822B BIT(2)
+#define BIT_CKANA12M_EN_8822B BIT(1)
+#define BIT_CNTD16V_EN_8822B BIT(0)
+
+/* 2 REG_SYS_EEPROM_CTRL_8822B */
+
+#define BIT_SHIFT_VPDIDX_8822B 8
+#define BIT_MASK_VPDIDX_8822B 0xff
+#define BIT_VPDIDX_8822B(x)                                                    \
+	(((x) & BIT_MASK_VPDIDX_8822B) << BIT_SHIFT_VPDIDX_8822B)
+#define BITS_VPDIDX_8822B (BIT_MASK_VPDIDX_8822B << BIT_SHIFT_VPDIDX_8822B)
+#define BIT_CLEAR_VPDIDX_8822B(x) ((x) & (~BITS_VPDIDX_8822B))
+#define BIT_GET_VPDIDX_8822B(x)                                                \
+	(((x) >> BIT_SHIFT_VPDIDX_8822B) & BIT_MASK_VPDIDX_8822B)
+#define BIT_SET_VPDIDX_8822B(x, v)                                             \
+	(BIT_CLEAR_VPDIDX_8822B(x) | BIT_VPDIDX_8822B(v))
+
+#define BIT_SHIFT_EEM1_0_8822B 6
+#define BIT_MASK_EEM1_0_8822B 0x3
+#define BIT_EEM1_0_8822B(x)                                                    \
+	(((x) & BIT_MASK_EEM1_0_8822B) << BIT_SHIFT_EEM1_0_8822B)
+#define BITS_EEM1_0_8822B (BIT_MASK_EEM1_0_8822B << BIT_SHIFT_EEM1_0_8822B)
+#define BIT_CLEAR_EEM1_0_8822B(x) ((x) & (~BITS_EEM1_0_8822B))
+#define BIT_GET_EEM1_0_8822B(x)                                                \
+	(((x) >> BIT_SHIFT_EEM1_0_8822B) & BIT_MASK_EEM1_0_8822B)
+#define BIT_SET_EEM1_0_8822B(x, v)                                             \
+	(BIT_CLEAR_EEM1_0_8822B(x) | BIT_EEM1_0_8822B(v))
+
+#define BIT_AUTOLOAD_SUS_8822B BIT(5)
+#define BIT_EERPOMSEL_8822B BIT(4)
+#define BIT_EECS_V1_8822B BIT(3)
+#define BIT_EESK_V1_8822B BIT(2)
+#define BIT_EEDI_V1_8822B BIT(1)
+#define BIT_EEDO_V1_8822B BIT(0)
+
+/* 2 REG_EE_VPD_8822B */
+
+#define BIT_SHIFT_VPD_DATA_8822B 0
+#define BIT_MASK_VPD_DATA_8822B 0xffffffffL
+#define BIT_VPD_DATA_8822B(x)                                                  \
+	(((x) & BIT_MASK_VPD_DATA_8822B) << BIT_SHIFT_VPD_DATA_8822B)
+#define BITS_VPD_DATA_8822B                                                    \
+	(BIT_MASK_VPD_DATA_8822B << BIT_SHIFT_VPD_DATA_8822B)
+#define BIT_CLEAR_VPD_DATA_8822B(x) ((x) & (~BITS_VPD_DATA_8822B))
+#define BIT_GET_VPD_DATA_8822B(x)                                              \
+	(((x) >> BIT_SHIFT_VPD_DATA_8822B) & BIT_MASK_VPD_DATA_8822B)
+#define BIT_SET_VPD_DATA_8822B(x, v)                                           \
+	(BIT_CLEAR_VPD_DATA_8822B(x) | BIT_VPD_DATA_8822B(v))
+
+/* 2 REG_SYS_SWR_CTRL1_8822B */
+#define BIT_C2_L_BIT0_8822B BIT(31)
+
+#define BIT_SHIFT_C1_L_8822B 29
+#define BIT_MASK_C1_L_8822B 0x3
+#define BIT_C1_L_8822B(x) (((x) & BIT_MASK_C1_L_8822B) << BIT_SHIFT_C1_L_8822B)
+#define BITS_C1_L_8822B (BIT_MASK_C1_L_8822B << BIT_SHIFT_C1_L_8822B)
+#define BIT_CLEAR_C1_L_8822B(x) ((x) & (~BITS_C1_L_8822B))
+#define BIT_GET_C1_L_8822B(x)                                                  \
+	(((x) >> BIT_SHIFT_C1_L_8822B) & BIT_MASK_C1_L_8822B)
+#define BIT_SET_C1_L_8822B(x, v) (BIT_CLEAR_C1_L_8822B(x) | BIT_C1_L_8822B(v))
+
+#define BIT_SHIFT_REG_FREQ_L_8822B 25
+#define BIT_MASK_REG_FREQ_L_8822B 0x7
+#define BIT_REG_FREQ_L_8822B(x)                                                \
+	(((x) & BIT_MASK_REG_FREQ_L_8822B) << BIT_SHIFT_REG_FREQ_L_8822B)
+#define BITS_REG_FREQ_L_8822B                                                  \
+	(BIT_MASK_REG_FREQ_L_8822B << BIT_SHIFT_REG_FREQ_L_8822B)
+#define BIT_CLEAR_REG_FREQ_L_8822B(x) ((x) & (~BITS_REG_FREQ_L_8822B))
+#define BIT_GET_REG_FREQ_L_8822B(x)                                            \
+	(((x) >> BIT_SHIFT_REG_FREQ_L_8822B) & BIT_MASK_REG_FREQ_L_8822B)
+#define BIT_SET_REG_FREQ_L_8822B(x, v)                                         \
+	(BIT_CLEAR_REG_FREQ_L_8822B(x) | BIT_REG_FREQ_L_8822B(v))
+
+#define BIT_REG_EN_DUTY_8822B BIT(24)
+
+#define BIT_SHIFT_REG_MODE_8822B 22
+#define BIT_MASK_REG_MODE_8822B 0x3
+#define BIT_REG_MODE_8822B(x)                                                  \
+	(((x) & BIT_MASK_REG_MODE_8822B) << BIT_SHIFT_REG_MODE_8822B)
+#define BITS_REG_MODE_8822B                                                    \
+	(BIT_MASK_REG_MODE_8822B << BIT_SHIFT_REG_MODE_8822B)
+#define BIT_CLEAR_REG_MODE_8822B(x) ((x) & (~BITS_REG_MODE_8822B))
+#define BIT_GET_REG_MODE_8822B(x)                                              \
+	(((x) >> BIT_SHIFT_REG_MODE_8822B) & BIT_MASK_REG_MODE_8822B)
+#define BIT_SET_REG_MODE_8822B(x, v)                                           \
+	(BIT_CLEAR_REG_MODE_8822B(x) | BIT_REG_MODE_8822B(v))
+
+#define BIT_REG_EN_SP_8822B BIT(21)
+#define BIT_REG_AUTO_L_8822B BIT(20)
+#define BIT_SW18_SELD_BIT0_8822B BIT(19)
+#define BIT_SW18_POWOCP_8822B BIT(18)
+
+#define BIT_SHIFT_OCP_L1_8822B 15
+#define BIT_MASK_OCP_L1_8822B 0x7
+#define BIT_OCP_L1_8822B(x)                                                    \
+	(((x) & BIT_MASK_OCP_L1_8822B) << BIT_SHIFT_OCP_L1_8822B)
+#define BITS_OCP_L1_8822B (BIT_MASK_OCP_L1_8822B << BIT_SHIFT_OCP_L1_8822B)
+#define BIT_CLEAR_OCP_L1_8822B(x) ((x) & (~BITS_OCP_L1_8822B))
+#define BIT_GET_OCP_L1_8822B(x)                                                \
+	(((x) >> BIT_SHIFT_OCP_L1_8822B) & BIT_MASK_OCP_L1_8822B)
+#define BIT_SET_OCP_L1_8822B(x, v)                                             \
+	(BIT_CLEAR_OCP_L1_8822B(x) | BIT_OCP_L1_8822B(v))
+
+#define BIT_SHIFT_CF_L_8822B 13
+#define BIT_MASK_CF_L_8822B 0x3
+#define BIT_CF_L_8822B(x) (((x) & BIT_MASK_CF_L_8822B) << BIT_SHIFT_CF_L_8822B)
+#define BITS_CF_L_8822B (BIT_MASK_CF_L_8822B << BIT_SHIFT_CF_L_8822B)
+#define BIT_CLEAR_CF_L_8822B(x) ((x) & (~BITS_CF_L_8822B))
+#define BIT_GET_CF_L_8822B(x)                                                  \
+	(((x) >> BIT_SHIFT_CF_L_8822B) & BIT_MASK_CF_L_8822B)
+#define BIT_SET_CF_L_8822B(x, v) (BIT_CLEAR_CF_L_8822B(x) | BIT_CF_L_8822B(v))
+
+#define BIT_SW18_FPWM_8822B BIT(11)
+#define BIT_SW18_SWEN_8822B BIT(9)
+#define BIT_SW18_LDEN_8822B BIT(8)
+#define BIT_MAC_ID_EN_8822B BIT(7)
+#define BIT_AFE_BGEN_8822B BIT(0)
+
+/* 2 REG_SYS_SWR_CTRL2_8822B */
+#define BIT_POW_ZCD_L_8822B BIT(31)
+#define BIT_AUTOZCD_L_8822B BIT(30)
+
+#define BIT_SHIFT_REG_DELAY_8822B 28
+#define BIT_MASK_REG_DELAY_8822B 0x3
+#define BIT_REG_DELAY_8822B(x)                                                 \
+	(((x) & BIT_MASK_REG_DELAY_8822B) << BIT_SHIFT_REG_DELAY_8822B)
+#define BITS_REG_DELAY_8822B                                                   \
+	(BIT_MASK_REG_DELAY_8822B << BIT_SHIFT_REG_DELAY_8822B)
+#define BIT_CLEAR_REG_DELAY_8822B(x) ((x) & (~BITS_REG_DELAY_8822B))
+#define BIT_GET_REG_DELAY_8822B(x)                                             \
+	(((x) >> BIT_SHIFT_REG_DELAY_8822B) & BIT_MASK_REG_DELAY_8822B)
+#define BIT_SET_REG_DELAY_8822B(x, v)                                          \
+	(BIT_CLEAR_REG_DELAY_8822B(x) | BIT_REG_DELAY_8822B(v))
+
+#define BIT_SHIFT_V15ADJ_L1_V1_8822B 24
+#define BIT_MASK_V15ADJ_L1_V1_8822B 0x7
+#define BIT_V15ADJ_L1_V1_8822B(x)                                              \
+	(((x) & BIT_MASK_V15ADJ_L1_V1_8822B) << BIT_SHIFT_V15ADJ_L1_V1_8822B)
+#define BITS_V15ADJ_L1_V1_8822B                                                \
+	(BIT_MASK_V15ADJ_L1_V1_8822B << BIT_SHIFT_V15ADJ_L1_V1_8822B)
+#define BIT_CLEAR_V15ADJ_L1_V1_8822B(x) ((x) & (~BITS_V15ADJ_L1_V1_8822B))
+#define BIT_GET_V15ADJ_L1_V1_8822B(x)                                          \
+	(((x) >> BIT_SHIFT_V15ADJ_L1_V1_8822B) & BIT_MASK_V15ADJ_L1_V1_8822B)
+#define BIT_SET_V15ADJ_L1_V1_8822B(x, v)                                       \
+	(BIT_CLEAR_V15ADJ_L1_V1_8822B(x) | BIT_V15ADJ_L1_V1_8822B(v))
+
+#define BIT_SHIFT_VOL_L1_V1_8822B 20
+#define BIT_MASK_VOL_L1_V1_8822B 0xf
+#define BIT_VOL_L1_V1_8822B(x)                                                 \
+	(((x) & BIT_MASK_VOL_L1_V1_8822B) << BIT_SHIFT_VOL_L1_V1_8822B)
+#define BITS_VOL_L1_V1_8822B                                                   \
+	(BIT_MASK_VOL_L1_V1_8822B << BIT_SHIFT_VOL_L1_V1_8822B)
+#define BIT_CLEAR_VOL_L1_V1_8822B(x) ((x) & (~BITS_VOL_L1_V1_8822B))
+#define BIT_GET_VOL_L1_V1_8822B(x)                                             \
+	(((x) >> BIT_SHIFT_VOL_L1_V1_8822B) & BIT_MASK_VOL_L1_V1_8822B)
+#define BIT_SET_VOL_L1_V1_8822B(x, v)                                          \
+	(BIT_CLEAR_VOL_L1_V1_8822B(x) | BIT_VOL_L1_V1_8822B(v))
+
+#define BIT_SHIFT_IN_L1_V1_8822B 17
+#define BIT_MASK_IN_L1_V1_8822B 0x7
+#define BIT_IN_L1_V1_8822B(x)                                                  \
+	(((x) & BIT_MASK_IN_L1_V1_8822B) << BIT_SHIFT_IN_L1_V1_8822B)
+#define BITS_IN_L1_V1_8822B                                                    \
+	(BIT_MASK_IN_L1_V1_8822B << BIT_SHIFT_IN_L1_V1_8822B)
+#define BIT_CLEAR_IN_L1_V1_8822B(x) ((x) & (~BITS_IN_L1_V1_8822B))
+#define BIT_GET_IN_L1_V1_8822B(x)                                              \
+	(((x) >> BIT_SHIFT_IN_L1_V1_8822B) & BIT_MASK_IN_L1_V1_8822B)
+#define BIT_SET_IN_L1_V1_8822B(x, v)                                           \
+	(BIT_CLEAR_IN_L1_V1_8822B(x) | BIT_IN_L1_V1_8822B(v))
+
+#define BIT_SHIFT_TBOX_L1_8822B 15
+#define BIT_MASK_TBOX_L1_8822B 0x3
+#define BIT_TBOX_L1_8822B(x)                                                   \
+	(((x) & BIT_MASK_TBOX_L1_8822B) << BIT_SHIFT_TBOX_L1_8822B)
+#define BITS_TBOX_L1_8822B (BIT_MASK_TBOX_L1_8822B << BIT_SHIFT_TBOX_L1_8822B)
+#define BIT_CLEAR_TBOX_L1_8822B(x) ((x) & (~BITS_TBOX_L1_8822B))
+#define BIT_GET_TBOX_L1_8822B(x)                                               \
+	(((x) >> BIT_SHIFT_TBOX_L1_8822B) & BIT_MASK_TBOX_L1_8822B)
+#define BIT_SET_TBOX_L1_8822B(x, v)                                            \
+	(BIT_CLEAR_TBOX_L1_8822B(x) | BIT_TBOX_L1_8822B(v))
+
+#define BIT_SW18_SEL_8822B BIT(13)
+
+/* 2 REG_NOT_VALID_8822B */
+#define BIT_SW18_SD_8822B BIT(10)
+
+#define BIT_SHIFT_R3_L_8822B 7
+#define BIT_MASK_R3_L_8822B 0x3
+#define BIT_R3_L_8822B(x) (((x) & BIT_MASK_R3_L_8822B) << BIT_SHIFT_R3_L_8822B)
+#define BITS_R3_L_8822B (BIT_MASK_R3_L_8822B << BIT_SHIFT_R3_L_8822B)
+#define BIT_CLEAR_R3_L_8822B(x) ((x) & (~BITS_R3_L_8822B))
+#define BIT_GET_R3_L_8822B(x)                                                  \
+	(((x) >> BIT_SHIFT_R3_L_8822B) & BIT_MASK_R3_L_8822B)
+#define BIT_SET_R3_L_8822B(x, v) (BIT_CLEAR_R3_L_8822B(x) | BIT_R3_L_8822B(v))
+
+#define BIT_SHIFT_SW18_R2_8822B 5
+#define BIT_MASK_SW18_R2_8822B 0x3
+#define BIT_SW18_R2_8822B(x)                                                   \
+	(((x) & BIT_MASK_SW18_R2_8822B) << BIT_SHIFT_SW18_R2_8822B)
+#define BITS_SW18_R2_8822B (BIT_MASK_SW18_R2_8822B << BIT_SHIFT_SW18_R2_8822B)
+#define BIT_CLEAR_SW18_R2_8822B(x) ((x) & (~BITS_SW18_R2_8822B))
+#define BIT_GET_SW18_R2_8822B(x)                                               \
+	(((x) >> BIT_SHIFT_SW18_R2_8822B) & BIT_MASK_SW18_R2_8822B)
+#define BIT_SET_SW18_R2_8822B(x, v)                                            \
+	(BIT_CLEAR_SW18_R2_8822B(x) | BIT_SW18_R2_8822B(v))
+
+#define BIT_SHIFT_SW18_R1_8822B 3
+#define BIT_MASK_SW18_R1_8822B 0x3
+#define BIT_SW18_R1_8822B(x)                                                   \
+	(((x) & BIT_MASK_SW18_R1_8822B) << BIT_SHIFT_SW18_R1_8822B)
+#define BITS_SW18_R1_8822B (BIT_MASK_SW18_R1_8822B << BIT_SHIFT_SW18_R1_8822B)
+#define BIT_CLEAR_SW18_R1_8822B(x) ((x) & (~BITS_SW18_R1_8822B))
+#define BIT_GET_SW18_R1_8822B(x)                                               \
+	(((x) >> BIT_SHIFT_SW18_R1_8822B) & BIT_MASK_SW18_R1_8822B)
+#define BIT_SET_SW18_R1_8822B(x, v)                                            \
+	(BIT_CLEAR_SW18_R1_8822B(x) | BIT_SW18_R1_8822B(v))
+
+#define BIT_SHIFT_C3_L_C3_8822B 1
+#define BIT_MASK_C3_L_C3_8822B 0x3
+#define BIT_C3_L_C3_8822B(x)                                                   \
+	(((x) & BIT_MASK_C3_L_C3_8822B) << BIT_SHIFT_C3_L_C3_8822B)
+#define BITS_C3_L_C3_8822B (BIT_MASK_C3_L_C3_8822B << BIT_SHIFT_C3_L_C3_8822B)
+#define BIT_CLEAR_C3_L_C3_8822B(x) ((x) & (~BITS_C3_L_C3_8822B))
+#define BIT_GET_C3_L_C3_8822B(x)                                               \
+	(((x) >> BIT_SHIFT_C3_L_C3_8822B) & BIT_MASK_C3_L_C3_8822B)
+#define BIT_SET_C3_L_C3_8822B(x, v)                                            \
+	(BIT_CLEAR_C3_L_C3_8822B(x) | BIT_C3_L_C3_8822B(v))
+
+#define BIT_C2_L_BIT1_8822B BIT(0)
+
+/* 2 REG_SYS_SWR_CTRL3_8822B */
+#define BIT_SPS18_OCP_DIS_8822B BIT(31)
+
+#define BIT_SHIFT_SPS18_OCP_TH_8822B 16
+#define BIT_MASK_SPS18_OCP_TH_8822B 0x7fff
+#define BIT_SPS18_OCP_TH_8822B(x)                                              \
+	(((x) & BIT_MASK_SPS18_OCP_TH_8822B) << BIT_SHIFT_SPS18_OCP_TH_8822B)
+#define BITS_SPS18_OCP_TH_8822B                                                \
+	(BIT_MASK_SPS18_OCP_TH_8822B << BIT_SHIFT_SPS18_OCP_TH_8822B)
+#define BIT_CLEAR_SPS18_OCP_TH_8822B(x) ((x) & (~BITS_SPS18_OCP_TH_8822B))
+#define BIT_GET_SPS18_OCP_TH_8822B(x)                                          \
+	(((x) >> BIT_SHIFT_SPS18_OCP_TH_8822B) & BIT_MASK_SPS18_OCP_TH_8822B)
+#define BIT_SET_SPS18_OCP_TH_8822B(x, v)                                       \
+	(BIT_CLEAR_SPS18_OCP_TH_8822B(x) | BIT_SPS18_OCP_TH_8822B(v))
+
+#define BIT_SHIFT_OCP_WINDOW_8822B 0
+#define BIT_MASK_OCP_WINDOW_8822B 0xffff
+#define BIT_OCP_WINDOW_8822B(x)                                                \
+	(((x) & BIT_MASK_OCP_WINDOW_8822B) << BIT_SHIFT_OCP_WINDOW_8822B)
+#define BITS_OCP_WINDOW_8822B                                                  \
+	(BIT_MASK_OCP_WINDOW_8822B << BIT_SHIFT_OCP_WINDOW_8822B)
+#define BIT_CLEAR_OCP_WINDOW_8822B(x) ((x) & (~BITS_OCP_WINDOW_8822B))
+#define BIT_GET_OCP_WINDOW_8822B(x)                                            \
+	(((x) >> BIT_SHIFT_OCP_WINDOW_8822B) & BIT_MASK_OCP_WINDOW_8822B)
+#define BIT_SET_OCP_WINDOW_8822B(x, v)                                         \
+	(BIT_CLEAR_OCP_WINDOW_8822B(x) | BIT_OCP_WINDOW_8822B(v))
+
+/* 2 REG_RSV_CTRL_8822B */
+#define BIT_HREG_DBG_8822B BIT(23)
+#define BIT_WLMCUIOIF_8822B BIT(8)
+#define BIT_LOCK_ALL_EN_8822B BIT(7)
+#define BIT_R_DIS_PRST_8822B BIT(6)
+#define BIT_WLOCK_1C_B6_8822B BIT(5)
+#define BIT_WLOCK_40_8822B BIT(4)
+#define BIT_WLOCK_08_8822B BIT(3)
+#define BIT_WLOCK_04_8822B BIT(2)
+#define BIT_WLOCK_00_8822B BIT(1)
+#define BIT_WLOCK_ALL_8822B BIT(0)
+
+/* 2 REG_RF_CTRL_8822B */
+#define BIT_RF_SDMRSTB_8822B BIT(2)
+#define BIT_RF_RSTB_8822B BIT(1)
+#define BIT_RF_EN_8822B BIT(0)
+
+/* 2 REG_AFE_LDO_CTRL_8822B */
+
+#define BIT_SHIFT_LPLDH12_RSV_8822B 29
+#define BIT_MASK_LPLDH12_RSV_8822B 0x7
+#define BIT_LPLDH12_RSV_8822B(x)                                               \
+	(((x) & BIT_MASK_LPLDH12_RSV_8822B) << BIT_SHIFT_LPLDH12_RSV_8822B)
+#define BITS_LPLDH12_RSV_8822B                                                 \
+	(BIT_MASK_LPLDH12_RSV_8822B << BIT_SHIFT_LPLDH12_RSV_8822B)
+#define BIT_CLEAR_LPLDH12_RSV_8822B(x) ((x) & (~BITS_LPLDH12_RSV_8822B))
+#define BIT_GET_LPLDH12_RSV_8822B(x)                                           \
+	(((x) >> BIT_SHIFT_LPLDH12_RSV_8822B) & BIT_MASK_LPLDH12_RSV_8822B)
+#define BIT_SET_LPLDH12_RSV_8822B(x, v)                                        \
+	(BIT_CLEAR_LPLDH12_RSV_8822B(x) | BIT_LPLDH12_RSV_8822B(v))
+
+#define BIT_LPLDH12_SLP_8822B BIT(28)
+
+#define BIT_SHIFT_LPLDH12_VADJ_8822B 24
+#define BIT_MASK_LPLDH12_VADJ_8822B 0xf
+#define BIT_LPLDH12_VADJ_8822B(x)                                              \
+	(((x) & BIT_MASK_LPLDH12_VADJ_8822B) << BIT_SHIFT_LPLDH12_VADJ_8822B)
+#define BITS_LPLDH12_VADJ_8822B                                                \
+	(BIT_MASK_LPLDH12_VADJ_8822B << BIT_SHIFT_LPLDH12_VADJ_8822B)
+#define BIT_CLEAR_LPLDH12_VADJ_8822B(x) ((x) & (~BITS_LPLDH12_VADJ_8822B))
+#define BIT_GET_LPLDH12_VADJ_8822B(x)                                          \
+	(((x) >> BIT_SHIFT_LPLDH12_VADJ_8822B) & BIT_MASK_LPLDH12_VADJ_8822B)
+#define BIT_SET_LPLDH12_VADJ_8822B(x, v)                                       \
+	(BIT_CLEAR_LPLDH12_VADJ_8822B(x) | BIT_LPLDH12_VADJ_8822B(v))
+
+#define BIT_LDH12_EN_8822B BIT(16)
+#define BIT_WLBBOFF_BIG_PWC_EN_8822B BIT(14)
+#define BIT_WLBBOFF_SMALL_PWC_EN_8822B BIT(13)
+#define BIT_WLMACOFF_BIG_PWC_EN_8822B BIT(12)
+#define BIT_WLPON_PWC_EN_8822B BIT(11)
+#define BIT_POW_REGU_P1_8822B BIT(10)
+#define BIT_LDOV12W_EN_8822B BIT(8)
+#define BIT_EX_XTAL_DRV_DIGI_8822B BIT(7)
+#define BIT_EX_XTAL_DRV_USB_8822B BIT(6)
+#define BIT_EX_XTAL_DRV_AFE_8822B BIT(5)
+#define BIT_EX_XTAL_DRV_RF2_8822B BIT(4)
+#define BIT_EX_XTAL_DRV_RF1_8822B BIT(3)
+#define BIT_POW_REGU_P0_8822B BIT(2)
+
+/* 2 REG_NOT_VALID_8822B */
+#define BIT_POW_PLL_LDO_8822B BIT(0)
+
+/* 2 REG_AFE_CTRL1_8822B */
+#define BIT_AGPIO_GPE_8822B BIT(31)
+
+#define BIT_SHIFT_XTAL_CAP_XI_8822B 25
+#define BIT_MASK_XTAL_CAP_XI_8822B 0x3f
+#define BIT_XTAL_CAP_XI_8822B(x)                                               \
+	(((x) & BIT_MASK_XTAL_CAP_XI_8822B) << BIT_SHIFT_XTAL_CAP_XI_8822B)
+#define BITS_XTAL_CAP_XI_8822B                                                 \
+	(BIT_MASK_XTAL_CAP_XI_8822B << BIT_SHIFT_XTAL_CAP_XI_8822B)
+#define BIT_CLEAR_XTAL_CAP_XI_8822B(x) ((x) & (~BITS_XTAL_CAP_XI_8822B))
+#define BIT_GET_XTAL_CAP_XI_8822B(x)                                           \
+	(((x) >> BIT_SHIFT_XTAL_CAP_XI_8822B) & BIT_MASK_XTAL_CAP_XI_8822B)
+#define BIT_SET_XTAL_CAP_XI_8822B(x, v)                                        \
+	(BIT_CLEAR_XTAL_CAP_XI_8822B(x) | BIT_XTAL_CAP_XI_8822B(v))
+
+#define BIT_SHIFT_XTAL_DRV_DIGI_8822B 23
+#define BIT_MASK_XTAL_DRV_DIGI_8822B 0x3
+#define BIT_XTAL_DRV_DIGI_8822B(x)                                             \
+	(((x) & BIT_MASK_XTAL_DRV_DIGI_8822B) << BIT_SHIFT_XTAL_DRV_DIGI_8822B)
+#define BITS_XTAL_DRV_DIGI_8822B                                               \
+	(BIT_MASK_XTAL_DRV_DIGI_8822B << BIT_SHIFT_XTAL_DRV_DIGI_8822B)
+#define BIT_CLEAR_XTAL_DRV_DIGI_8822B(x) ((x) & (~BITS_XTAL_DRV_DIGI_8822B))
+#define BIT_GET_XTAL_DRV_DIGI_8822B(x)                                         \
+	(((x) >> BIT_SHIFT_XTAL_DRV_DIGI_8822B) & BIT_MASK_XTAL_DRV_DIGI_8822B)
+#define BIT_SET_XTAL_DRV_DIGI_8822B(x, v)                                      \
+	(BIT_CLEAR_XTAL_DRV_DIGI_8822B(x) | BIT_XTAL_DRV_DIGI_8822B(v))
+
+#define BIT_XTAL_DRV_USB_BIT1_8822B BIT(22)
+
+#define BIT_SHIFT_MAC_CLK_SEL_8822B 20
+#define BIT_MASK_MAC_CLK_SEL_8822B 0x3
+#define BIT_MAC_CLK_SEL_8822B(x)                                               \
+	(((x) & BIT_MASK_MAC_CLK_SEL_8822B) << BIT_SHIFT_MAC_CLK_SEL_8822B)
+#define BITS_MAC_CLK_SEL_8822B                                                 \
+	(BIT_MASK_MAC_CLK_SEL_8822B << BIT_SHIFT_MAC_CLK_SEL_8822B)
+#define BIT_CLEAR_MAC_CLK_SEL_8822B(x) ((x) & (~BITS_MAC_CLK_SEL_8822B))
+#define BIT_GET_MAC_CLK_SEL_8822B(x)                                           \
+	(((x) >> BIT_SHIFT_MAC_CLK_SEL_8822B) & BIT_MASK_MAC_CLK_SEL_8822B)
+#define BIT_SET_MAC_CLK_SEL_8822B(x, v)                                        \
+	(BIT_CLEAR_MAC_CLK_SEL_8822B(x) | BIT_MAC_CLK_SEL_8822B(v))
+
+#define BIT_XTAL_DRV_USB_BIT0_8822B BIT(19)
+
+#define BIT_SHIFT_XTAL_DRV_AFE_8822B 17
+#define BIT_MASK_XTAL_DRV_AFE_8822B 0x3
+#define BIT_XTAL_DRV_AFE_8822B(x)                                              \
+	(((x) & BIT_MASK_XTAL_DRV_AFE_8822B) << BIT_SHIFT_XTAL_DRV_AFE_8822B)
+#define BITS_XTAL_DRV_AFE_8822B                                                \
+	(BIT_MASK_XTAL_DRV_AFE_8822B << BIT_SHIFT_XTAL_DRV_AFE_8822B)
+#define BIT_CLEAR_XTAL_DRV_AFE_8822B(x) ((x) & (~BITS_XTAL_DRV_AFE_8822B))
+#define BIT_GET_XTAL_DRV_AFE_8822B(x)                                          \
+	(((x) >> BIT_SHIFT_XTAL_DRV_AFE_8822B) & BIT_MASK_XTAL_DRV_AFE_8822B)
+#define BIT_SET_XTAL_DRV_AFE_8822B(x, v)                                       \
+	(BIT_CLEAR_XTAL_DRV_AFE_8822B(x) | BIT_XTAL_DRV_AFE_8822B(v))
+
+#define BIT_SHIFT_XTAL_DRV_RF2_8822B 15
+#define BIT_MASK_XTAL_DRV_RF2_8822B 0x3
+#define BIT_XTAL_DRV_RF2_8822B(x)                                              \
+	(((x) & BIT_MASK_XTAL_DRV_RF2_8822B) << BIT_SHIFT_XTAL_DRV_RF2_8822B)
+#define BITS_XTAL_DRV_RF2_8822B                                                \
+	(BIT_MASK_XTAL_DRV_RF2_8822B << BIT_SHIFT_XTAL_DRV_RF2_8822B)
+#define BIT_CLEAR_XTAL_DRV_RF2_8822B(x) ((x) & (~BITS_XTAL_DRV_RF2_8822B))
+#define BIT_GET_XTAL_DRV_RF2_8822B(x)                                          \
+	(((x) >> BIT_SHIFT_XTAL_DRV_RF2_8822B) & BIT_MASK_XTAL_DRV_RF2_8822B)
+#define BIT_SET_XTAL_DRV_RF2_8822B(x, v)                                       \
+	(BIT_CLEAR_XTAL_DRV_RF2_8822B(x) | BIT_XTAL_DRV_RF2_8822B(v))
+
+#define BIT_SHIFT_XTAL_DRV_RF1_8822B 13
+#define BIT_MASK_XTAL_DRV_RF1_8822B 0x3
+#define BIT_XTAL_DRV_RF1_8822B(x)                                              \
+	(((x) & BIT_MASK_XTAL_DRV_RF1_8822B) << BIT_SHIFT_XTAL_DRV_RF1_8822B)
+#define BITS_XTAL_DRV_RF1_8822B                                                \
+	(BIT_MASK_XTAL_DRV_RF1_8822B << BIT_SHIFT_XTAL_DRV_RF1_8822B)
+#define BIT_CLEAR_XTAL_DRV_RF1_8822B(x) ((x) & (~BITS_XTAL_DRV_RF1_8822B))
+#define BIT_GET_XTAL_DRV_RF1_8822B(x)                                          \
+	(((x) >> BIT_SHIFT_XTAL_DRV_RF1_8822B) & BIT_MASK_XTAL_DRV_RF1_8822B)
+#define BIT_SET_XTAL_DRV_RF1_8822B(x, v)                                       \
+	(BIT_CLEAR_XTAL_DRV_RF1_8822B(x) | BIT_XTAL_DRV_RF1_8822B(v))
+
+#define BIT_XTAL_DELAY_DIGI_8822B BIT(12)
+#define BIT_XTAL_DELAY_USB_8822B BIT(11)
+#define BIT_XTAL_DELAY_AFE_8822B BIT(10)
+
+#define BIT_SHIFT_XTAL_LDO_VREF_8822B 7
+#define BIT_MASK_XTAL_LDO_VREF_8822B 0x7
+#define BIT_XTAL_LDO_VREF_8822B(x)                                             \
+	(((x) & BIT_MASK_XTAL_LDO_VREF_8822B) << BIT_SHIFT_XTAL_LDO_VREF_8822B)
+#define BITS_XTAL_LDO_VREF_8822B                                               \
+	(BIT_MASK_XTAL_LDO_VREF_8822B << BIT_SHIFT_XTAL_LDO_VREF_8822B)
+#define BIT_CLEAR_XTAL_LDO_VREF_8822B(x) ((x) & (~BITS_XTAL_LDO_VREF_8822B))
+#define BIT_GET_XTAL_LDO_VREF_8822B(x)                                         \
+	(((x) >> BIT_SHIFT_XTAL_LDO_VREF_8822B) & BIT_MASK_XTAL_LDO_VREF_8822B)
+#define BIT_SET_XTAL_LDO_VREF_8822B(x, v)                                      \
+	(BIT_CLEAR_XTAL_LDO_VREF_8822B(x) | BIT_XTAL_LDO_VREF_8822B(v))
+
+#define BIT_XTAL_XQSEL_RF_8822B BIT(6)
+#define BIT_XTAL_XQSEL_8822B BIT(5)
+
+#define BIT_SHIFT_XTAL_GMN_V2_8822B 3
+#define BIT_MASK_XTAL_GMN_V2_8822B 0x3
+#define BIT_XTAL_GMN_V2_8822B(x)                                               \
+	(((x) & BIT_MASK_XTAL_GMN_V2_8822B) << BIT_SHIFT_XTAL_GMN_V2_8822B)
+#define BITS_XTAL_GMN_V2_8822B                                                 \
+	(BIT_MASK_XTAL_GMN_V2_8822B << BIT_SHIFT_XTAL_GMN_V2_8822B)
+#define BIT_CLEAR_XTAL_GMN_V2_8822B(x) ((x) & (~BITS_XTAL_GMN_V2_8822B))
+#define BIT_GET_XTAL_GMN_V2_8822B(x)                                           \
+	(((x) >> BIT_SHIFT_XTAL_GMN_V2_8822B) & BIT_MASK_XTAL_GMN_V2_8822B)
+#define BIT_SET_XTAL_GMN_V2_8822B(x, v)                                        \
+	(BIT_CLEAR_XTAL_GMN_V2_8822B(x) | BIT_XTAL_GMN_V2_8822B(v))
+
+#define BIT_SHIFT_XTAL_GMP_V2_8822B 1
+#define BIT_MASK_XTAL_GMP_V2_8822B 0x3
+#define BIT_XTAL_GMP_V2_8822B(x)                                               \
+	(((x) & BIT_MASK_XTAL_GMP_V2_8822B) << BIT_SHIFT_XTAL_GMP_V2_8822B)
+#define BITS_XTAL_GMP_V2_8822B                                                 \
+	(BIT_MASK_XTAL_GMP_V2_8822B << BIT_SHIFT_XTAL_GMP_V2_8822B)
+#define BIT_CLEAR_XTAL_GMP_V2_8822B(x) ((x) & (~BITS_XTAL_GMP_V2_8822B))
+#define BIT_GET_XTAL_GMP_V2_8822B(x)                                           \
+	(((x) >> BIT_SHIFT_XTAL_GMP_V2_8822B) & BIT_MASK_XTAL_GMP_V2_8822B)
+#define BIT_SET_XTAL_GMP_V2_8822B(x, v)                                        \
+	(BIT_CLEAR_XTAL_GMP_V2_8822B(x) | BIT_XTAL_GMP_V2_8822B(v))
+
+#define BIT_XTAL_EN_8822B BIT(0)
+
+/* 2 REG_AFE_CTRL2_8822B */
+
+#define BIT_SHIFT_REG_C3_V4_8822B 30
+#define BIT_MASK_REG_C3_V4_8822B 0x3
+#define BIT_REG_C3_V4_8822B(x)                                                 \
+	(((x) & BIT_MASK_REG_C3_V4_8822B) << BIT_SHIFT_REG_C3_V4_8822B)
+#define BITS_REG_C3_V4_8822B                                                   \
+	(BIT_MASK_REG_C3_V4_8822B << BIT_SHIFT_REG_C3_V4_8822B)
+#define BIT_CLEAR_REG_C3_V4_8822B(x) ((x) & (~BITS_REG_C3_V4_8822B))
+#define BIT_GET_REG_C3_V4_8822B(x)                                             \
+	(((x) >> BIT_SHIFT_REG_C3_V4_8822B) & BIT_MASK_REG_C3_V4_8822B)
+#define BIT_SET_REG_C3_V4_8822B(x, v)                                          \
+	(BIT_CLEAR_REG_C3_V4_8822B(x) | BIT_REG_C3_V4_8822B(v))
+
+#define BIT_REG_CP_BIT1_8822B BIT(29)
+
+#define BIT_SHIFT_REG_RS_V4_8822B 26
+#define BIT_MASK_REG_RS_V4_8822B 0x7
+#define BIT_REG_RS_V4_8822B(x)                                                 \
+	(((x) & BIT_MASK_REG_RS_V4_8822B) << BIT_SHIFT_REG_RS_V4_8822B)
+#define BITS_REG_RS_V4_8822B                                                   \
+	(BIT_MASK_REG_RS_V4_8822B << BIT_SHIFT_REG_RS_V4_8822B)
+#define BIT_CLEAR_REG_RS_V4_8822B(x) ((x) & (~BITS_REG_RS_V4_8822B))
+#define BIT_GET_REG_RS_V4_8822B(x)                                             \
+	(((x) >> BIT_SHIFT_REG_RS_V4_8822B) & BIT_MASK_REG_RS_V4_8822B)
+#define BIT_SET_REG_RS_V4_8822B(x, v)                                          \
+	(BIT_CLEAR_REG_RS_V4_8822B(x) | BIT_REG_RS_V4_8822B(v))
+
+#define BIT_SHIFT_REG__CS_8822B 24
+#define BIT_MASK_REG__CS_8822B 0x3
+#define BIT_REG__CS_8822B(x)                                                   \
+	(((x) & BIT_MASK_REG__CS_8822B) << BIT_SHIFT_REG__CS_8822B)
+#define BITS_REG__CS_8822B (BIT_MASK_REG__CS_8822B << BIT_SHIFT_REG__CS_8822B)
+#define BIT_CLEAR_REG__CS_8822B(x) ((x) & (~BITS_REG__CS_8822B))
+#define BIT_GET_REG__CS_8822B(x)                                               \
+	(((x) >> BIT_SHIFT_REG__CS_8822B) & BIT_MASK_REG__CS_8822B)
+#define BIT_SET_REG__CS_8822B(x, v)                                            \
+	(BIT_CLEAR_REG__CS_8822B(x) | BIT_REG__CS_8822B(v))
+
+#define BIT_SHIFT_REG_CP_OFFSET_8822B 21
+#define BIT_MASK_REG_CP_OFFSET_8822B 0x7
+#define BIT_REG_CP_OFFSET_8822B(x)                                             \
+	(((x) & BIT_MASK_REG_CP_OFFSET_8822B) << BIT_SHIFT_REG_CP_OFFSET_8822B)
+#define BITS_REG_CP_OFFSET_8822B                                               \
+	(BIT_MASK_REG_CP_OFFSET_8822B << BIT_SHIFT_REG_CP_OFFSET_8822B)
+#define BIT_CLEAR_REG_CP_OFFSET_8822B(x) ((x) & (~BITS_REG_CP_OFFSET_8822B))
+#define BIT_GET_REG_CP_OFFSET_8822B(x)                                         \
+	(((x) >> BIT_SHIFT_REG_CP_OFFSET_8822B) & BIT_MASK_REG_CP_OFFSET_8822B)
+#define BIT_SET_REG_CP_OFFSET_8822B(x, v)                                      \
+	(BIT_CLEAR_REG_CP_OFFSET_8822B(x) | BIT_REG_CP_OFFSET_8822B(v))
+
+#define BIT_SHIFT_CP_BIAS_8822B 18
+#define BIT_MASK_CP_BIAS_8822B 0x7
+#define BIT_CP_BIAS_8822B(x)                                                   \
+	(((x) & BIT_MASK_CP_BIAS_8822B) << BIT_SHIFT_CP_BIAS_8822B)
+#define BITS_CP_BIAS_8822B (BIT_MASK_CP_BIAS_8822B << BIT_SHIFT_CP_BIAS_8822B)
+#define BIT_CLEAR_CP_BIAS_8822B(x) ((x) & (~BITS_CP_BIAS_8822B))
+#define BIT_GET_CP_BIAS_8822B(x)                                               \
+	(((x) >> BIT_SHIFT_CP_BIAS_8822B) & BIT_MASK_CP_BIAS_8822B)
+#define BIT_SET_CP_BIAS_8822B(x, v)                                            \
+	(BIT_CLEAR_CP_BIAS_8822B(x) | BIT_CP_BIAS_8822B(v))
+
+#define BIT_REG_IDOUBLE_V2_8822B BIT(17)
+#define BIT_EN_SYN_8822B BIT(16)
+
+#define BIT_SHIFT_MCCO_8822B 14
+#define BIT_MASK_MCCO_8822B 0x3
+#define BIT_MCCO_8822B(x) (((x) & BIT_MASK_MCCO_8822B) << BIT_SHIFT_MCCO_8822B)
+#define BITS_MCCO_8822B (BIT_MASK_MCCO_8822B << BIT_SHIFT_MCCO_8822B)
+#define BIT_CLEAR_MCCO_8822B(x) ((x) & (~BITS_MCCO_8822B))
+#define BIT_GET_MCCO_8822B(x)                                                  \
+	(((x) >> BIT_SHIFT_MCCO_8822B) & BIT_MASK_MCCO_8822B)
+#define BIT_SET_MCCO_8822B(x, v) (BIT_CLEAR_MCCO_8822B(x) | BIT_MCCO_8822B(v))
+
+#define BIT_SHIFT_REG_LDO_SEL_8822B 12
+#define BIT_MASK_REG_LDO_SEL_8822B 0x3
+#define BIT_REG_LDO_SEL_8822B(x)                                               \
+	(((x) & BIT_MASK_REG_LDO_SEL_8822B) << BIT_SHIFT_REG_LDO_SEL_8822B)
+#define BITS_REG_LDO_SEL_8822B                                                 \
+	(BIT_MASK_REG_LDO_SEL_8822B << BIT_SHIFT_REG_LDO_SEL_8822B)
+#define BIT_CLEAR_REG_LDO_SEL_8822B(x) ((x) & (~BITS_REG_LDO_SEL_8822B))
+#define BIT_GET_REG_LDO_SEL_8822B(x)                                           \
+	(((x) >> BIT_SHIFT_REG_LDO_SEL_8822B) & BIT_MASK_REG_LDO_SEL_8822B)
+#define BIT_SET_REG_LDO_SEL_8822B(x, v)                                        \
+	(BIT_CLEAR_REG_LDO_SEL_8822B(x) | BIT_REG_LDO_SEL_8822B(v))
+
+#define BIT_REG_KVCO_V2_8822B BIT(10)
+#define BIT_AGPIO_GPO_8822B BIT(9)
+
+#define BIT_SHIFT_AGPIO_DRV_8822B 7
+#define BIT_MASK_AGPIO_DRV_8822B 0x3
+#define BIT_AGPIO_DRV_8822B(x)                                                 \
+	(((x) & BIT_MASK_AGPIO_DRV_8822B) << BIT_SHIFT_AGPIO_DRV_8822B)
+#define BITS_AGPIO_DRV_8822B                                                   \
+	(BIT_MASK_AGPIO_DRV_8822B << BIT_SHIFT_AGPIO_DRV_8822B)
+#define BIT_CLEAR_AGPIO_DRV_8822B(x) ((x) & (~BITS_AGPIO_DRV_8822B))
+#define BIT_GET_AGPIO_DRV_8822B(x)                                             \
+	(((x) >> BIT_SHIFT_AGPIO_DRV_8822B) & BIT_MASK_AGPIO_DRV_8822B)
+#define BIT_SET_AGPIO_DRV_8822B(x, v)                                          \
+	(BIT_CLEAR_AGPIO_DRV_8822B(x) | BIT_AGPIO_DRV_8822B(v))
+
+#define BIT_SHIFT_XTAL_CAP_XO_8822B 1
+#define BIT_MASK_XTAL_CAP_XO_8822B 0x3f
+#define BIT_XTAL_CAP_XO_8822B(x)                                               \
+	(((x) & BIT_MASK_XTAL_CAP_XO_8822B) << BIT_SHIFT_XTAL_CAP_XO_8822B)
+#define BITS_XTAL_CAP_XO_8822B                                                 \
+	(BIT_MASK_XTAL_CAP_XO_8822B << BIT_SHIFT_XTAL_CAP_XO_8822B)
+#define BIT_CLEAR_XTAL_CAP_XO_8822B(x) ((x) & (~BITS_XTAL_CAP_XO_8822B))
+#define BIT_GET_XTAL_CAP_XO_8822B(x)                                           \
+	(((x) >> BIT_SHIFT_XTAL_CAP_XO_8822B) & BIT_MASK_XTAL_CAP_XO_8822B)
+#define BIT_SET_XTAL_CAP_XO_8822B(x, v)                                        \
+	(BIT_CLEAR_XTAL_CAP_XO_8822B(x) | BIT_XTAL_CAP_XO_8822B(v))
+
+#define BIT_POW_PLL_8822B BIT(0)
+
+/* 2 REG_AFE_CTRL3_8822B */
+
+#define BIT_SHIFT_PS_8822B 7
+#define BIT_MASK_PS_8822B 0x7
+#define BIT_PS_8822B(x) (((x) & BIT_MASK_PS_8822B) << BIT_SHIFT_PS_8822B)
+#define BITS_PS_8822B (BIT_MASK_PS_8822B << BIT_SHIFT_PS_8822B)
+#define BIT_CLEAR_PS_8822B(x) ((x) & (~BITS_PS_8822B))
+#define BIT_GET_PS_8822B(x) (((x) >> BIT_SHIFT_PS_8822B) & BIT_MASK_PS_8822B)
+#define BIT_SET_PS_8822B(x, v) (BIT_CLEAR_PS_8822B(x) | BIT_PS_8822B(v))
+
+#define BIT_PSEN_8822B BIT(6)
+#define BIT_DOGENB_8822B BIT(5)
+#define BIT_REG_MBIAS_8822B BIT(4)
+
+#define BIT_SHIFT_REG_R3_V4_8822B 1
+#define BIT_MASK_REG_R3_V4_8822B 0x7
+#define BIT_REG_R3_V4_8822B(x)                                                 \
+	(((x) & BIT_MASK_REG_R3_V4_8822B) << BIT_SHIFT_REG_R3_V4_8822B)
+#define BITS_REG_R3_V4_8822B                                                   \
+	(BIT_MASK_REG_R3_V4_8822B << BIT_SHIFT_REG_R3_V4_8822B)
+#define BIT_CLEAR_REG_R3_V4_8822B(x) ((x) & (~BITS_REG_R3_V4_8822B))
+#define BIT_GET_REG_R3_V4_8822B(x)                                             \
+	(((x) >> BIT_SHIFT_REG_R3_V4_8822B) & BIT_MASK_REG_R3_V4_8822B)
+#define BIT_SET_REG_R3_V4_8822B(x, v)                                          \
+	(BIT_CLEAR_REG_R3_V4_8822B(x) | BIT_REG_R3_V4_8822B(v))
+
+#define BIT_REG_CP_BIT0_8822B BIT(0)
+
+/* 2 REG_EFUSE_CTRL_8822B */
+#define BIT_EF_FLAG_8822B BIT(31)
+
+#define BIT_SHIFT_EF_PGPD_8822B 28
+#define BIT_MASK_EF_PGPD_8822B 0x7
+#define BIT_EF_PGPD_8822B(x)                                                   \
+	(((x) & BIT_MASK_EF_PGPD_8822B) << BIT_SHIFT_EF_PGPD_8822B)
+#define BITS_EF_PGPD_8822B (BIT_MASK_EF_PGPD_8822B << BIT_SHIFT_EF_PGPD_8822B)
+#define BIT_CLEAR_EF_PGPD_8822B(x) ((x) & (~BITS_EF_PGPD_8822B))
+#define BIT_GET_EF_PGPD_8822B(x)                                               \
+	(((x) >> BIT_SHIFT_EF_PGPD_8822B) & BIT_MASK_EF_PGPD_8822B)
+#define BIT_SET_EF_PGPD_8822B(x, v)                                            \
+	(BIT_CLEAR_EF_PGPD_8822B(x) | BIT_EF_PGPD_8822B(v))
+
+#define BIT_SHIFT_EF_RDT_8822B 24
+#define BIT_MASK_EF_RDT_8822B 0xf
+#define BIT_EF_RDT_8822B(x)                                                    \
+	(((x) & BIT_MASK_EF_RDT_8822B) << BIT_SHIFT_EF_RDT_8822B)
+#define BITS_EF_RDT_8822B (BIT_MASK_EF_RDT_8822B << BIT_SHIFT_EF_RDT_8822B)
+#define BIT_CLEAR_EF_RDT_8822B(x) ((x) & (~BITS_EF_RDT_8822B))
+#define BIT_GET_EF_RDT_8822B(x)                                                \
+	(((x) >> BIT_SHIFT_EF_RDT_8822B) & BIT_MASK_EF_RDT_8822B)
+#define BIT_SET_EF_RDT_8822B(x, v)                                             \
+	(BIT_CLEAR_EF_RDT_8822B(x) | BIT_EF_RDT_8822B(v))
+
+#define BIT_SHIFT_EF_PGTS_8822B 20
+#define BIT_MASK_EF_PGTS_8822B 0xf
+#define BIT_EF_PGTS_8822B(x)                                                   \
+	(((x) & BIT_MASK_EF_PGTS_8822B) << BIT_SHIFT_EF_PGTS_8822B)
+#define BITS_EF_PGTS_8822B (BIT_MASK_EF_PGTS_8822B << BIT_SHIFT_EF_PGTS_8822B)
+#define BIT_CLEAR_EF_PGTS_8822B(x) ((x) & (~BITS_EF_PGTS_8822B))
+#define BIT_GET_EF_PGTS_8822B(x)                                               \
+	(((x) >> BIT_SHIFT_EF_PGTS_8822B) & BIT_MASK_EF_PGTS_8822B)
+#define BIT_SET_EF_PGTS_8822B(x, v)                                            \
+	(BIT_CLEAR_EF_PGTS_8822B(x) | BIT_EF_PGTS_8822B(v))
+
+#define BIT_EF_PDWN_8822B BIT(19)
+#define BIT_EF_ALDEN_8822B BIT(18)
+
+#define BIT_SHIFT_EF_ADDR_8822B 8
+#define BIT_MASK_EF_ADDR_8822B 0x3ff
+#define BIT_EF_ADDR_8822B(x)                                                   \
+	(((x) & BIT_MASK_EF_ADDR_8822B) << BIT_SHIFT_EF_ADDR_8822B)
+#define BITS_EF_ADDR_8822B (BIT_MASK_EF_ADDR_8822B << BIT_SHIFT_EF_ADDR_8822B)
+#define BIT_CLEAR_EF_ADDR_8822B(x) ((x) & (~BITS_EF_ADDR_8822B))
+#define BIT_GET_EF_ADDR_8822B(x)                                               \
+	(((x) >> BIT_SHIFT_EF_ADDR_8822B) & BIT_MASK_EF_ADDR_8822B)
+#define BIT_SET_EF_ADDR_8822B(x, v)                                            \
+	(BIT_CLEAR_EF_ADDR_8822B(x) | BIT_EF_ADDR_8822B(v))
+
+#define BIT_SHIFT_EF_DATA_8822B 0
+#define BIT_MASK_EF_DATA_8822B 0xff
+#define BIT_EF_DATA_8822B(x)                                                   \
+	(((x) & BIT_MASK_EF_DATA_8822B) << BIT_SHIFT_EF_DATA_8822B)
+#define BITS_EF_DATA_8822B (BIT_MASK_EF_DATA_8822B << BIT_SHIFT_EF_DATA_8822B)
+#define BIT_CLEAR_EF_DATA_8822B(x) ((x) & (~BITS_EF_DATA_8822B))
+#define BIT_GET_EF_DATA_8822B(x)                                               \
+	(((x) >> BIT_SHIFT_EF_DATA_8822B) & BIT_MASK_EF_DATA_8822B)
+#define BIT_SET_EF_DATA_8822B(x, v)                                            \
+	(BIT_CLEAR_EF_DATA_8822B(x) | BIT_EF_DATA_8822B(v))
+
+/* 2 REG_LDO_EFUSE_CTRL_8822B */
+#define BIT_LDOE25_EN_8822B BIT(31)
+
+#define BIT_SHIFT_LDOE25_V12ADJ_L_8822B 27
+#define BIT_MASK_LDOE25_V12ADJ_L_8822B 0xf
+#define BIT_LDOE25_V12ADJ_L_8822B(x)                                           \
+	(((x) & BIT_MASK_LDOE25_V12ADJ_L_8822B)                                \
+	 << BIT_SHIFT_LDOE25_V12ADJ_L_8822B)
+#define BITS_LDOE25_V12ADJ_L_8822B                                             \
+	(BIT_MASK_LDOE25_V12ADJ_L_8822B << BIT_SHIFT_LDOE25_V12ADJ_L_8822B)
+#define BIT_CLEAR_LDOE25_V12ADJ_L_8822B(x) ((x) & (~BITS_LDOE25_V12ADJ_L_8822B))
+#define BIT_GET_LDOE25_V12ADJ_L_8822B(x)                                       \
+	(((x) >> BIT_SHIFT_LDOE25_V12ADJ_L_8822B) &                            \
+	 BIT_MASK_LDOE25_V12ADJ_L_8822B)
+#define BIT_SET_LDOE25_V12ADJ_L_8822B(x, v)                                    \
+	(BIT_CLEAR_LDOE25_V12ADJ_L_8822B(x) | BIT_LDOE25_V12ADJ_L_8822B(v))
+
+#define BIT_EF_CRES_SEL_8822B BIT(26)
+
+#define BIT_SHIFT_EF_SCAN_START_V1_8822B 16
+#define BIT_MASK_EF_SCAN_START_V1_8822B 0x3ff
+#define BIT_EF_SCAN_START_V1_8822B(x)                                          \
+	(((x) & BIT_MASK_EF_SCAN_START_V1_8822B)                               \
+	 << BIT_SHIFT_EF_SCAN_START_V1_8822B)
+#define BITS_EF_SCAN_START_V1_8822B                                            \
+	(BIT_MASK_EF_SCAN_START_V1_8822B << BIT_SHIFT_EF_SCAN_START_V1_8822B)
+#define BIT_CLEAR_EF_SCAN_START_V1_8822B(x)                                    \
+	((x) & (~BITS_EF_SCAN_START_V1_8822B))
+#define BIT_GET_EF_SCAN_START_V1_8822B(x)                                      \
+	(((x) >> BIT_SHIFT_EF_SCAN_START_V1_8822B) &                           \
+	 BIT_MASK_EF_SCAN_START_V1_8822B)
+#define BIT_SET_EF_SCAN_START_V1_8822B(x, v)                                   \
+	(BIT_CLEAR_EF_SCAN_START_V1_8822B(x) | BIT_EF_SCAN_START_V1_8822B(v))
+
+#define BIT_SHIFT_EF_SCAN_END_8822B 12
+#define BIT_MASK_EF_SCAN_END_8822B 0xf
+#define BIT_EF_SCAN_END_8822B(x)                                               \
+	(((x) & BIT_MASK_EF_SCAN_END_8822B) << BIT_SHIFT_EF_SCAN_END_8822B)
+#define BITS_EF_SCAN_END_8822B                                                 \
+	(BIT_MASK_EF_SCAN_END_8822B << BIT_SHIFT_EF_SCAN_END_8822B)
+#define BIT_CLEAR_EF_SCAN_END_8822B(x) ((x) & (~BITS_EF_SCAN_END_8822B))
+#define BIT_GET_EF_SCAN_END_8822B(x)                                           \
+	(((x) >> BIT_SHIFT_EF_SCAN_END_8822B) & BIT_MASK_EF_SCAN_END_8822B)
+#define BIT_SET_EF_SCAN_END_8822B(x, v)                                        \
+	(BIT_CLEAR_EF_SCAN_END_8822B(x) | BIT_EF_SCAN_END_8822B(v))
+
+#define BIT_EF_PD_DIS_8822B BIT(11)
+
+#define BIT_SHIFT_EF_CELL_SEL_8822B 8
+#define BIT_MASK_EF_CELL_SEL_8822B 0x3
+#define BIT_EF_CELL_SEL_8822B(x)                                               \
+	(((x) & BIT_MASK_EF_CELL_SEL_8822B) << BIT_SHIFT_EF_CELL_SEL_8822B)
+#define BITS_EF_CELL_SEL_8822B                                                 \
+	(BIT_MASK_EF_CELL_SEL_8822B << BIT_SHIFT_EF_CELL_SEL_8822B)
+#define BIT_CLEAR_EF_CELL_SEL_8822B(x) ((x) & (~BITS_EF_CELL_SEL_8822B))
+#define BIT_GET_EF_CELL_SEL_8822B(x)                                           \
+	(((x) >> BIT_SHIFT_EF_CELL_SEL_8822B) & BIT_MASK_EF_CELL_SEL_8822B)
+#define BIT_SET_EF_CELL_SEL_8822B(x, v)                                        \
+	(BIT_CLEAR_EF_CELL_SEL_8822B(x) | BIT_EF_CELL_SEL_8822B(v))
+
+#define BIT_EF_TRPT_8822B BIT(7)
+
+#define BIT_SHIFT_EF_TTHD_8822B 0
+#define BIT_MASK_EF_TTHD_8822B 0x7f
+#define BIT_EF_TTHD_8822B(x)                                                   \
+	(((x) & BIT_MASK_EF_TTHD_8822B) << BIT_SHIFT_EF_TTHD_8822B)
+#define BITS_EF_TTHD_8822B (BIT_MASK_EF_TTHD_8822B << BIT_SHIFT_EF_TTHD_8822B)
+#define BIT_CLEAR_EF_TTHD_8822B(x) ((x) & (~BITS_EF_TTHD_8822B))
+#define BIT_GET_EF_TTHD_8822B(x)                                               \
+	(((x) >> BIT_SHIFT_EF_TTHD_8822B) & BIT_MASK_EF_TTHD_8822B)
+#define BIT_SET_EF_TTHD_8822B(x, v)                                            \
+	(BIT_CLEAR_EF_TTHD_8822B(x) | BIT_EF_TTHD_8822B(v))
+
+/* 2 REG_PWR_OPTION_CTRL_8822B */
+
+#define BIT_SHIFT_DBG_SEL_V1_8822B 16
+#define BIT_MASK_DBG_SEL_V1_8822B 0xff
+#define BIT_DBG_SEL_V1_8822B(x)                                                \
+	(((x) & BIT_MASK_DBG_SEL_V1_8822B) << BIT_SHIFT_DBG_SEL_V1_8822B)
+#define BITS_DBG_SEL_V1_8822B                                                  \
+	(BIT_MASK_DBG_SEL_V1_8822B << BIT_SHIFT_DBG_SEL_V1_8822B)
+#define BIT_CLEAR_DBG_SEL_V1_8822B(x) ((x) & (~BITS_DBG_SEL_V1_8822B))
+#define BIT_GET_DBG_SEL_V1_8822B(x)                                            \
+	(((x) >> BIT_SHIFT_DBG_SEL_V1_8822B) & BIT_MASK_DBG_SEL_V1_8822B)
+#define BIT_SET_DBG_SEL_V1_8822B(x, v)                                         \
+	(BIT_CLEAR_DBG_SEL_V1_8822B(x) | BIT_DBG_SEL_V1_8822B(v))
+
+#define BIT_SHIFT_DBG_SEL_BYTE_8822B 14
+#define BIT_MASK_DBG_SEL_BYTE_8822B 0x3
+#define BIT_DBG_SEL_BYTE_8822B(x)                                              \
+	(((x) & BIT_MASK_DBG_SEL_BYTE_8822B) << BIT_SHIFT_DBG_SEL_BYTE_8822B)
+#define BITS_DBG_SEL_BYTE_8822B                                                \
+	(BIT_MASK_DBG_SEL_BYTE_8822B << BIT_SHIFT_DBG_SEL_BYTE_8822B)
+#define BIT_CLEAR_DBG_SEL_BYTE_8822B(x) ((x) & (~BITS_DBG_SEL_BYTE_8822B))
+#define BIT_GET_DBG_SEL_BYTE_8822B(x)                                          \
+	(((x) >> BIT_SHIFT_DBG_SEL_BYTE_8822B) & BIT_MASK_DBG_SEL_BYTE_8822B)
+#define BIT_SET_DBG_SEL_BYTE_8822B(x, v)                                       \
+	(BIT_CLEAR_DBG_SEL_BYTE_8822B(x) | BIT_DBG_SEL_BYTE_8822B(v))
+
+#define BIT_SHIFT_STD_L1_V1_8822B 12
+#define BIT_MASK_STD_L1_V1_8822B 0x3
+#define BIT_STD_L1_V1_8822B(x)                                                 \
+	(((x) & BIT_MASK_STD_L1_V1_8822B) << BIT_SHIFT_STD_L1_V1_8822B)
+#define BITS_STD_L1_V1_8822B                                                   \
+	(BIT_MASK_STD_L1_V1_8822B << BIT_SHIFT_STD_L1_V1_8822B)
+#define BIT_CLEAR_STD_L1_V1_8822B(x) ((x) & (~BITS_STD_L1_V1_8822B))
+#define BIT_GET_STD_L1_V1_8822B(x)                                             \
+	(((x) >> BIT_SHIFT_STD_L1_V1_8822B) & BIT_MASK_STD_L1_V1_8822B)
+#define BIT_SET_STD_L1_V1_8822B(x, v)                                          \
+	(BIT_CLEAR_STD_L1_V1_8822B(x) | BIT_STD_L1_V1_8822B(v))
+
+#define BIT_SYSON_DBG_PAD_E2_8822B BIT(11)
+#define BIT_SYSON_LED_PAD_E2_8822B BIT(10)
+#define BIT_SYSON_GPEE_PAD_E2_8822B BIT(9)
+#define BIT_SYSON_PCI_PAD_E2_8822B BIT(8)
+#define BIT_AUTO_SW_LDO_VOL_EN_8822B BIT(7)
+
+#define BIT_SHIFT_SYSON_SPS0WWV_WT_8822B 4
+#define BIT_MASK_SYSON_SPS0WWV_WT_8822B 0x3
+#define BIT_SYSON_SPS0WWV_WT_8822B(x)                                          \
+	(((x) & BIT_MASK_SYSON_SPS0WWV_WT_8822B)                               \
+	 << BIT_SHIFT_SYSON_SPS0WWV_WT_8822B)
+#define BITS_SYSON_SPS0WWV_WT_8822B                                            \
+	(BIT_MASK_SYSON_SPS0WWV_WT_8822B << BIT_SHIFT_SYSON_SPS0WWV_WT_8822B)
+#define BIT_CLEAR_SYSON_SPS0WWV_WT_8822B(x)                                    \
+	((x) & (~BITS_SYSON_SPS0WWV_WT_8822B))
+#define BIT_GET_SYSON_SPS0WWV_WT_8822B(x)                                      \
+	(((x) >> BIT_SHIFT_SYSON_SPS0WWV_WT_8822B) &                           \
+	 BIT_MASK_SYSON_SPS0WWV_WT_8822B)
+#define BIT_SET_SYSON_SPS0WWV_WT_8822B(x, v)                                   \
+	(BIT_CLEAR_SYSON_SPS0WWV_WT_8822B(x) | BIT_SYSON_SPS0WWV_WT_8822B(v))
+
+#define BIT_SHIFT_SYSON_SPS0LDO_WT_8822B 2
+#define BIT_MASK_SYSON_SPS0LDO_WT_8822B 0x3
+#define BIT_SYSON_SPS0LDO_WT_8822B(x)                                          \
+	(((x) & BIT_MASK_SYSON_SPS0LDO_WT_8822B)                               \
+	 << BIT_SHIFT_SYSON_SPS0LDO_WT_8822B)
+#define BITS_SYSON_SPS0LDO_WT_8822B                                            \
+	(BIT_MASK_SYSON_SPS0LDO_WT_8822B << BIT_SHIFT_SYSON_SPS0LDO_WT_8822B)
+#define BIT_CLEAR_SYSON_SPS0LDO_WT_8822B(x)                                    \
+	((x) & (~BITS_SYSON_SPS0LDO_WT_8822B))
+#define BIT_GET_SYSON_SPS0LDO_WT_8822B(x)                                      \
+	(((x) >> BIT_SHIFT_SYSON_SPS0LDO_WT_8822B) &                           \
+	 BIT_MASK_SYSON_SPS0LDO_WT_8822B)
+#define BIT_SET_SYSON_SPS0LDO_WT_8822B(x, v)                                   \
+	(BIT_CLEAR_SYSON_SPS0LDO_WT_8822B(x) | BIT_SYSON_SPS0LDO_WT_8822B(v))
+
+#define BIT_SHIFT_SYSON_RCLK_SCALE_8822B 0
+#define BIT_MASK_SYSON_RCLK_SCALE_8822B 0x3
+#define BIT_SYSON_RCLK_SCALE_8822B(x)                                          \
+	(((x) & BIT_MASK_SYSON_RCLK_SCALE_8822B)                               \
+	 << BIT_SHIFT_SYSON_RCLK_SCALE_8822B)
+#define BITS_SYSON_RCLK_SCALE_8822B                                            \
+	(BIT_MASK_SYSON_RCLK_SCALE_8822B << BIT_SHIFT_SYSON_RCLK_SCALE_8822B)
+#define BIT_CLEAR_SYSON_RCLK_SCALE_8822B(x)                                    \
+	((x) & (~BITS_SYSON_RCLK_SCALE_8822B))
+#define BIT_GET_SYSON_RCLK_SCALE_8822B(x)                                      \
+	(((x) >> BIT_SHIFT_SYSON_RCLK_SCALE_8822B) &                           \
+	 BIT_MASK_SYSON_RCLK_SCALE_8822B)
+#define BIT_SET_SYSON_RCLK_SCALE_8822B(x, v)                                   \
+	(BIT_CLEAR_SYSON_RCLK_SCALE_8822B(x) | BIT_SYSON_RCLK_SCALE_8822B(v))
+
+/* 2 REG_CAL_TIMER_8822B */
+
+#define BIT_SHIFT_MATCH_CNT_8822B 8
+#define BIT_MASK_MATCH_CNT_8822B 0xff
+#define BIT_MATCH_CNT_8822B(x)                                                 \
+	(((x) & BIT_MASK_MATCH_CNT_8822B) << BIT_SHIFT_MATCH_CNT_8822B)
+#define BITS_MATCH_CNT_8822B                                                   \
+	(BIT_MASK_MATCH_CNT_8822B << BIT_SHIFT_MATCH_CNT_8822B)
+#define BIT_CLEAR_MATCH_CNT_8822B(x) ((x) & (~BITS_MATCH_CNT_8822B))
+#define BIT_GET_MATCH_CNT_8822B(x)                                             \
+	(((x) >> BIT_SHIFT_MATCH_CNT_8822B) & BIT_MASK_MATCH_CNT_8822B)
+#define BIT_SET_MATCH_CNT_8822B(x, v)                                          \
+	(BIT_CLEAR_MATCH_CNT_8822B(x) | BIT_MATCH_CNT_8822B(v))
+
+#define BIT_SHIFT_CAL_SCAL_8822B 0
+#define BIT_MASK_CAL_SCAL_8822B 0xff
+#define BIT_CAL_SCAL_8822B(x)                                                  \
+	(((x) & BIT_MASK_CAL_SCAL_8822B) << BIT_SHIFT_CAL_SCAL_8822B)
+#define BITS_CAL_SCAL_8822B                                                    \
+	(BIT_MASK_CAL_SCAL_8822B << BIT_SHIFT_CAL_SCAL_8822B)
+#define BIT_CLEAR_CAL_SCAL_8822B(x) ((x) & (~BITS_CAL_SCAL_8822B))
+#define BIT_GET_CAL_SCAL_8822B(x)                                              \
+	(((x) >> BIT_SHIFT_CAL_SCAL_8822B) & BIT_MASK_CAL_SCAL_8822B)
+#define BIT_SET_CAL_SCAL_8822B(x, v)                                           \
+	(BIT_CLEAR_CAL_SCAL_8822B(x) | BIT_CAL_SCAL_8822B(v))
+
+/* 2 REG_ACLK_MON_8822B */
+
+#define BIT_SHIFT_RCLK_MON_8822B 5
+#define BIT_MASK_RCLK_MON_8822B 0x7ff
+#define BIT_RCLK_MON_8822B(x)                                                  \
+	(((x) & BIT_MASK_RCLK_MON_8822B) << BIT_SHIFT_RCLK_MON_8822B)
+#define BITS_RCLK_MON_8822B                                                    \
+	(BIT_MASK_RCLK_MON_8822B << BIT_SHIFT_RCLK_MON_8822B)
+#define BIT_CLEAR_RCLK_MON_8822B(x) ((x) & (~BITS_RCLK_MON_8822B))
+#define BIT_GET_RCLK_MON_8822B(x)                                              \
+	(((x) >> BIT_SHIFT_RCLK_MON_8822B) & BIT_MASK_RCLK_MON_8822B)
+#define BIT_SET_RCLK_MON_8822B(x, v)                                           \
+	(BIT_CLEAR_RCLK_MON_8822B(x) | BIT_RCLK_MON_8822B(v))
+
+#define BIT_CAL_EN_8822B BIT(4)
+
+#define BIT_SHIFT_DPSTU_8822B 2
+#define BIT_MASK_DPSTU_8822B 0x3
+#define BIT_DPSTU_8822B(x)                                                     \
+	(((x) & BIT_MASK_DPSTU_8822B) << BIT_SHIFT_DPSTU_8822B)
+#define BITS_DPSTU_8822B (BIT_MASK_DPSTU_8822B << BIT_SHIFT_DPSTU_8822B)
+#define BIT_CLEAR_DPSTU_8822B(x) ((x) & (~BITS_DPSTU_8822B))
+#define BIT_GET_DPSTU_8822B(x)                                                 \
+	(((x) >> BIT_SHIFT_DPSTU_8822B) & BIT_MASK_DPSTU_8822B)
+#define BIT_SET_DPSTU_8822B(x, v)                                              \
+	(BIT_CLEAR_DPSTU_8822B(x) | BIT_DPSTU_8822B(v))
+
+#define BIT_SUS_16X_8822B BIT(1)
+
+/* 2 REG_GPIO_MUXCFG_8822B */
+#define BIT_FSPI_EN_8822B BIT(19)
+#define BIT_WL_RTS_EXT_32K_SEL_8822B BIT(18)
+#define BIT_WLGP_SPI_EN_8822B BIT(16)
+#define BIT_SIC_LBK_8822B BIT(15)
+#define BIT_ENHTP_8822B BIT(14)
+#define BIT_ENSIC_8822B BIT(12)
+#define BIT_SIC_SWRST_8822B BIT(11)
+#define BIT_PO_WIFI_PTA_PINS_8822B BIT(10)
+#define BIT_PO_BT_PTA_PINS_8822B BIT(9)
+#define BIT_ENUART_8822B BIT(8)
+
+#define BIT_SHIFT_BTMODE_8822B 6
+#define BIT_MASK_BTMODE_8822B 0x3
+#define BIT_BTMODE_8822B(x)                                                    \
+	(((x) & BIT_MASK_BTMODE_8822B) << BIT_SHIFT_BTMODE_8822B)
+#define BITS_BTMODE_8822B (BIT_MASK_BTMODE_8822B << BIT_SHIFT_BTMODE_8822B)
+#define BIT_CLEAR_BTMODE_8822B(x) ((x) & (~BITS_BTMODE_8822B))
+#define BIT_GET_BTMODE_8822B(x)                                                \
+	(((x) >> BIT_SHIFT_BTMODE_8822B) & BIT_MASK_BTMODE_8822B)
+#define BIT_SET_BTMODE_8822B(x, v)                                             \
+	(BIT_CLEAR_BTMODE_8822B(x) | BIT_BTMODE_8822B(v))
+
+#define BIT_ENBT_8822B BIT(5)
+#define BIT_EROM_EN_8822B BIT(4)
+#define BIT_WLRFE_6_7_EN_8822B BIT(3)
+#define BIT_WLRFE_4_5_EN_8822B BIT(2)
+
+#define BIT_SHIFT_GPIOSEL_8822B 0
+#define BIT_MASK_GPIOSEL_8822B 0x3
+#define BIT_GPIOSEL_8822B(x)                                                   \
+	(((x) & BIT_MASK_GPIOSEL_8822B) << BIT_SHIFT_GPIOSEL_8822B)
+#define BITS_GPIOSEL_8822B (BIT_MASK_GPIOSEL_8822B << BIT_SHIFT_GPIOSEL_8822B)
+#define BIT_CLEAR_GPIOSEL_8822B(x) ((x) & (~BITS_GPIOSEL_8822B))
+#define BIT_GET_GPIOSEL_8822B(x)                                               \
+	(((x) >> BIT_SHIFT_GPIOSEL_8822B) & BIT_MASK_GPIOSEL_8822B)
+#define BIT_SET_GPIOSEL_8822B(x, v)                                            \
+	(BIT_CLEAR_GPIOSEL_8822B(x) | BIT_GPIOSEL_8822B(v))
+
+/* 2 REG_GPIO_PIN_CTRL_8822B */
+
+#define BIT_SHIFT_GPIO_MOD_7_TO_0_8822B 24
+#define BIT_MASK_GPIO_MOD_7_TO_0_8822B 0xff
+#define BIT_GPIO_MOD_7_TO_0_8822B(x)                                           \
+	(((x) & BIT_MASK_GPIO_MOD_7_TO_0_8822B)                                \
+	 << BIT_SHIFT_GPIO_MOD_7_TO_0_8822B)
+#define BITS_GPIO_MOD_7_TO_0_8822B                                             \
+	(BIT_MASK_GPIO_MOD_7_TO_0_8822B << BIT_SHIFT_GPIO_MOD_7_TO_0_8822B)
+#define BIT_CLEAR_GPIO_MOD_7_TO_0_8822B(x) ((x) & (~BITS_GPIO_MOD_7_TO_0_8822B))
+#define BIT_GET_GPIO_MOD_7_TO_0_8822B(x)                                       \
+	(((x) >> BIT_SHIFT_GPIO_MOD_7_TO_0_8822B) &                            \
+	 BIT_MASK_GPIO_MOD_7_TO_0_8822B)
+#define BIT_SET_GPIO_MOD_7_TO_0_8822B(x, v)                                    \
+	(BIT_CLEAR_GPIO_MOD_7_TO_0_8822B(x) | BIT_GPIO_MOD_7_TO_0_8822B(v))
+
+#define BIT_SHIFT_GPIO_IO_SEL_7_TO_0_8822B 16
+#define BIT_MASK_GPIO_IO_SEL_7_TO_0_8822B 0xff
+#define BIT_GPIO_IO_SEL_7_TO_0_8822B(x)                                        \
+	(((x) & BIT_MASK_GPIO_IO_SEL_7_TO_0_8822B)                             \
+	 << BIT_SHIFT_GPIO_IO_SEL_7_TO_0_8822B)
+#define BITS_GPIO_IO_SEL_7_TO_0_8822B                                          \
+	(BIT_MASK_GPIO_IO_SEL_7_TO_0_8822B                                     \
+	 << BIT_SHIFT_GPIO_IO_SEL_7_TO_0_8822B)
+#define BIT_CLEAR_GPIO_IO_SEL_7_TO_0_8822B(x)                                  \
+	((x) & (~BITS_GPIO_IO_SEL_7_TO_0_8822B))
+#define BIT_GET_GPIO_IO_SEL_7_TO_0_8822B(x)                                    \
+	(((x) >> BIT_SHIFT_GPIO_IO_SEL_7_TO_0_8822B) &                         \
+	 BIT_MASK_GPIO_IO_SEL_7_TO_0_8822B)
+#define BIT_SET_GPIO_IO_SEL_7_TO_0_8822B(x, v)                                 \
+	(BIT_CLEAR_GPIO_IO_SEL_7_TO_0_8822B(x) |                               \
+	 BIT_GPIO_IO_SEL_7_TO_0_8822B(v))
+
+#define BIT_SHIFT_GPIO_OUT_7_TO_0_8822B 8
+#define BIT_MASK_GPIO_OUT_7_TO_0_8822B 0xff
+#define BIT_GPIO_OUT_7_TO_0_8822B(x)                                           \
+	(((x) & BIT_MASK_GPIO_OUT_7_TO_0_8822B)                                \
+	 << BIT_SHIFT_GPIO_OUT_7_TO_0_8822B)
+#define BITS_GPIO_OUT_7_TO_0_8822B                                             \
+	(BIT_MASK_GPIO_OUT_7_TO_0_8822B << BIT_SHIFT_GPIO_OUT_7_TO_0_8822B)
+#define BIT_CLEAR_GPIO_OUT_7_TO_0_8822B(x) ((x) & (~BITS_GPIO_OUT_7_TO_0_8822B))
+#define BIT_GET_GPIO_OUT_7_TO_0_8822B(x)                                       \
+	(((x) >> BIT_SHIFT_GPIO_OUT_7_TO_0_8822B) &                            \
+	 BIT_MASK_GPIO_OUT_7_TO_0_8822B)
+#define BIT_SET_GPIO_OUT_7_TO_0_8822B(x, v)                                    \
+	(BIT_CLEAR_GPIO_OUT_7_TO_0_8822B(x) | BIT_GPIO_OUT_7_TO_0_8822B(v))
+
+#define BIT_SHIFT_GPIO_IN_7_TO_0_8822B 0
+#define BIT_MASK_GPIO_IN_7_TO_0_8822B 0xff
+#define BIT_GPIO_IN_7_TO_0_8822B(x)                                            \
+	(((x) & BIT_MASK_GPIO_IN_7_TO_0_8822B)                                 \
+	 << BIT_SHIFT_GPIO_IN_7_TO_0_8822B)
+#define BITS_GPIO_IN_7_TO_0_8822B                                              \
+	(BIT_MASK_GPIO_IN_7_TO_0_8822B << BIT_SHIFT_GPIO_IN_7_TO_0_8822B)
+#define BIT_CLEAR_GPIO_IN_7_TO_0_8822B(x) ((x) & (~BITS_GPIO_IN_7_TO_0_8822B))
+#define BIT_GET_GPIO_IN_7_TO_0_8822B(x)                                        \
+	(((x) >> BIT_SHIFT_GPIO_IN_7_TO_0_8822B) &                             \
+	 BIT_MASK_GPIO_IN_7_TO_0_8822B)
+#define BIT_SET_GPIO_IN_7_TO_0_8822B(x, v)                                     \
+	(BIT_CLEAR_GPIO_IN_7_TO_0_8822B(x) | BIT_GPIO_IN_7_TO_0_8822B(v))
+
+/* 2 REG_GPIO_INTM_8822B */
+
+#define BIT_SHIFT_MUXDBG_SEL_8822B 30
+#define BIT_MASK_MUXDBG_SEL_8822B 0x3
+#define BIT_MUXDBG_SEL_8822B(x)                                                \
+	(((x) & BIT_MASK_MUXDBG_SEL_8822B) << BIT_SHIFT_MUXDBG_SEL_8822B)
+#define BITS_MUXDBG_SEL_8822B                                                  \
+	(BIT_MASK_MUXDBG_SEL_8822B << BIT_SHIFT_MUXDBG_SEL_8822B)
+#define BIT_CLEAR_MUXDBG_SEL_8822B(x) ((x) & (~BITS_MUXDBG_SEL_8822B))
+#define BIT_GET_MUXDBG_SEL_8822B(x)                                            \
+	(((x) >> BIT_SHIFT_MUXDBG_SEL_8822B) & BIT_MASK_MUXDBG_SEL_8822B)
+#define BIT_SET_MUXDBG_SEL_8822B(x, v)                                         \
+	(BIT_CLEAR_MUXDBG_SEL_8822B(x) | BIT_MUXDBG_SEL_8822B(v))
+
+#define BIT_EXTWOL_SEL_8822B BIT(17)
+#define BIT_EXTWOL_EN_8822B BIT(16)
+#define BIT_GPIOF_INT_MD_8822B BIT(15)
+#define BIT_GPIOE_INT_MD_8822B BIT(14)
+#define BIT_GPIOD_INT_MD_8822B BIT(13)
+#define BIT_GPIOF_INT_MD_8822B BIT(15)
+#define BIT_GPIOE_INT_MD_8822B BIT(14)
+#define BIT_GPIOD_INT_MD_8822B BIT(13)
+#define BIT_GPIOC_INT_MD_8822B BIT(12)
+#define BIT_GPIOB_INT_MD_8822B BIT(11)
+#define BIT_GPIOA_INT_MD_8822B BIT(10)
+#define BIT_GPIO9_INT_MD_8822B BIT(9)
+#define BIT_GPIO8_INT_MD_8822B BIT(8)
+#define BIT_GPIO7_INT_MD_8822B BIT(7)
+#define BIT_GPIO6_INT_MD_8822B BIT(6)
+#define BIT_GPIO5_INT_MD_8822B BIT(5)
+#define BIT_GPIO4_INT_MD_8822B BIT(4)
+#define BIT_GPIO3_INT_MD_8822B BIT(3)
+#define BIT_GPIO2_INT_MD_8822B BIT(2)
+#define BIT_GPIO1_INT_MD_8822B BIT(1)
+#define BIT_GPIO0_INT_MD_8822B BIT(0)
+
+/* 2 REG_LED_CFG_8822B */
+#define BIT_GPIO3_WL_CTRL_EN_8822B BIT(27)
+#define BIT_LNAON_SEL_EN_8822B BIT(26)
+#define BIT_PAPE_SEL_EN_8822B BIT(25)
+#define BIT_DPDT_WLBT_SEL_8822B BIT(24)
+#define BIT_DPDT_SEL_EN_8822B BIT(23)
+#define BIT_GPIO13_14_WL_CTRL_EN_8822B BIT(22)
+#define BIT_GPIO13_14_WL_CTRL_EN_8822B BIT(22)
+#define BIT_LED2DIS_8822B BIT(21)
+#define BIT_LED2PL_8822B BIT(20)
+#define BIT_LED2SV_8822B BIT(19)
+
+#define BIT_SHIFT_LED2CM_8822B 16
+#define BIT_MASK_LED2CM_8822B 0x7
+#define BIT_LED2CM_8822B(x)                                                    \
+	(((x) & BIT_MASK_LED2CM_8822B) << BIT_SHIFT_LED2CM_8822B)
+#define BITS_LED2CM_8822B (BIT_MASK_LED2CM_8822B << BIT_SHIFT_LED2CM_8822B)
+#define BIT_CLEAR_LED2CM_8822B(x) ((x) & (~BITS_LED2CM_8822B))
+#define BIT_GET_LED2CM_8822B(x)                                                \
+	(((x) >> BIT_SHIFT_LED2CM_8822B) & BIT_MASK_LED2CM_8822B)
+#define BIT_SET_LED2CM_8822B(x, v)                                             \
+	(BIT_CLEAR_LED2CM_8822B(x) | BIT_LED2CM_8822B(v))
+
+#define BIT_LED1DIS_8822B BIT(15)
+#define BIT_LED1PL_8822B BIT(12)
+#define BIT_LED1SV_8822B BIT(11)
+
+#define BIT_SHIFT_LED1CM_8822B 8
+#define BIT_MASK_LED1CM_8822B 0x7
+#define BIT_LED1CM_8822B(x)                                                    \
+	(((x) & BIT_MASK_LED1CM_8822B) << BIT_SHIFT_LED1CM_8822B)
+#define BITS_LED1CM_8822B (BIT_MASK_LED1CM_8822B << BIT_SHIFT_LED1CM_8822B)
+#define BIT_CLEAR_LED1CM_8822B(x) ((x) & (~BITS_LED1CM_8822B))
+#define BIT_GET_LED1CM_8822B(x)                                                \
+	(((x) >> BIT_SHIFT_LED1CM_8822B) & BIT_MASK_LED1CM_8822B)
+#define BIT_SET_LED1CM_8822B(x, v)                                             \
+	(BIT_CLEAR_LED1CM_8822B(x) | BIT_LED1CM_8822B(v))
+
+#define BIT_LED0DIS_8822B BIT(7)
+
+#define BIT_SHIFT_AFE_LDO_SWR_CHECK_8822B 5
+#define BIT_MASK_AFE_LDO_SWR_CHECK_8822B 0x3
+#define BIT_AFE_LDO_SWR_CHECK_8822B(x)                                         \
+	(((x) & BIT_MASK_AFE_LDO_SWR_CHECK_8822B)                              \
+	 << BIT_SHIFT_AFE_LDO_SWR_CHECK_8822B)
+#define BITS_AFE_LDO_SWR_CHECK_8822B                                           \
+	(BIT_MASK_AFE_LDO_SWR_CHECK_8822B << BIT_SHIFT_AFE_LDO_SWR_CHECK_8822B)
+#define BIT_CLEAR_AFE_LDO_SWR_CHECK_8822B(x)                                   \
+	((x) & (~BITS_AFE_LDO_SWR_CHECK_8822B))
+#define BIT_GET_AFE_LDO_SWR_CHECK_8822B(x)                                     \
+	(((x) >> BIT_SHIFT_AFE_LDO_SWR_CHECK_8822B) &                          \
+	 BIT_MASK_AFE_LDO_SWR_CHECK_8822B)
+#define BIT_SET_AFE_LDO_SWR_CHECK_8822B(x, v)                                  \
+	(BIT_CLEAR_AFE_LDO_SWR_CHECK_8822B(x) | BIT_AFE_LDO_SWR_CHECK_8822B(v))
+
+#define BIT_LED0PL_8822B BIT(4)
+#define BIT_LED0SV_8822B BIT(3)
+
+#define BIT_SHIFT_LED0CM_8822B 0
+#define BIT_MASK_LED0CM_8822B 0x7
+#define BIT_LED0CM_8822B(x)                                                    \
+	(((x) & BIT_MASK_LED0CM_8822B) << BIT_SHIFT_LED0CM_8822B)
+#define BITS_LED0CM_8822B (BIT_MASK_LED0CM_8822B << BIT_SHIFT_LED0CM_8822B)
+#define BIT_CLEAR_LED0CM_8822B(x) ((x) & (~BITS_LED0CM_8822B))
+#define BIT_GET_LED0CM_8822B(x)                                                \
+	(((x) >> BIT_SHIFT_LED0CM_8822B) & BIT_MASK_LED0CM_8822B)
+#define BIT_SET_LED0CM_8822B(x, v)                                             \
+	(BIT_CLEAR_LED0CM_8822B(x) | BIT_LED0CM_8822B(v))
+
+/* 2 REG_FSIMR_8822B */
+#define BIT_FS_PDNINT_EN_8822B BIT(31)
+#define BIT_NFC_INT_PAD_EN_8822B BIT(30)
+#define BIT_FS_SPS_OCP_INT_EN_8822B BIT(29)
+#define BIT_FS_PWMERR_INT_EN_8822B BIT(28)
+#define BIT_FS_GPIOF_INT_EN_8822B BIT(27)
+#define BIT_FS_GPIOE_INT_EN_8822B BIT(26)
+#define BIT_FS_GPIOD_INT_EN_8822B BIT(25)
+#define BIT_FS_GPIOC_INT_EN_8822B BIT(24)
+#define BIT_FS_GPIOB_INT_EN_8822B BIT(23)
+#define BIT_FS_GPIOA_INT_EN_8822B BIT(22)
+#define BIT_FS_GPIO9_INT_EN_8822B BIT(21)
+#define BIT_FS_GPIO8_INT_EN_8822B BIT(20)
+#define BIT_FS_GPIO7_INT_EN_8822B BIT(19)
+#define BIT_FS_GPIO6_INT_EN_8822B BIT(18)
+#define BIT_FS_GPIO5_INT_EN_8822B BIT(17)
+#define BIT_FS_GPIO4_INT_EN_8822B BIT(16)
+#define BIT_FS_GPIO3_INT_EN_8822B BIT(15)
+#define BIT_FS_GPIO2_INT_EN_8822B BIT(14)
+#define BIT_FS_GPIO1_INT_EN_8822B BIT(13)
+#define BIT_FS_GPIO0_INT_EN_8822B BIT(12)
+#define BIT_FS_HCI_SUS_EN_8822B BIT(11)
+#define BIT_FS_HCI_RES_EN_8822B BIT(10)
+#define BIT_FS_HCI_RESET_EN_8822B BIT(9)
+#define BIT_FS_BTON_STS_UPDATE_MSK_EN_8822B BIT(7)
+#define BIT_ACT2RECOVERY_INT_EN_V1_8822B BIT(6)
+#define BIT_GEN1GEN2_SWITCH_8822B BIT(5)
+#define BIT_HCI_TXDMA_REQ_HIMR_8822B BIT(4)
+#define BIT_FS_32K_LEAVE_SETTING_MAK_8822B BIT(3)
+#define BIT_FS_32K_ENTER_SETTING_MAK_8822B BIT(2)
+#define BIT_FS_USB_LPMRSM_MSK_8822B BIT(1)
+#define BIT_FS_USB_LPMINT_MSK_8822B BIT(0)
+
+/* 2 REG_FSISR_8822B */
+#define BIT_FS_PDNINT_8822B BIT(31)
+#define BIT_FS_SPS_OCP_INT_8822B BIT(29)
+#define BIT_FS_PWMERR_INT_8822B BIT(28)
+#define BIT_FS_GPIOF_INT_8822B BIT(27)
+#define BIT_FS_GPIOE_INT_8822B BIT(26)
+#define BIT_FS_GPIOD_INT_8822B BIT(25)
+#define BIT_FS_GPIOC_INT_8822B BIT(24)
+#define BIT_FS_GPIOB_INT_8822B BIT(23)
+#define BIT_FS_GPIOA_INT_8822B BIT(22)
+#define BIT_FS_GPIO9_INT_8822B BIT(21)
+#define BIT_FS_GPIO8_INT_8822B BIT(20)
+#define BIT_FS_GPIO7_INT_8822B BIT(19)
+#define BIT_FS_GPIO6_INT_8822B BIT(18)
+#define BIT_FS_GPIO5_INT_8822B BIT(17)
+#define BIT_FS_GPIO4_INT_8822B BIT(16)
+#define BIT_FS_GPIO3_INT_8822B BIT(15)
+#define BIT_FS_GPIO2_INT_8822B BIT(14)
+#define BIT_FS_GPIO1_INT_8822B BIT(13)
+#define BIT_FS_GPIO0_INT_8822B BIT(12)
+#define BIT_FS_HCI_SUS_INT_8822B BIT(11)
+#define BIT_FS_HCI_RES_INT_8822B BIT(10)
+#define BIT_FS_HCI_RESET_INT_8822B BIT(9)
+#define BIT_ACT2RECOVERY_8822B BIT(6)
+#define BIT_GEN1GEN2_SWITCH_8822B BIT(5)
+#define BIT_HCI_TXDMA_REQ_HISR_8822B BIT(4)
+#define BIT_FS_32K_LEAVE_SETTING_INT_8822B BIT(3)
+#define BIT_FS_32K_ENTER_SETTING_INT_8822B BIT(2)
+#define BIT_FS_USB_LPMRSM_INT_8822B BIT(1)
+#define BIT_FS_USB_LPMINT_INT_8822B BIT(0)
+
+/* 2 REG_HSIMR_8822B */
+#define BIT_GPIOF_INT_EN_8822B BIT(31)
+#define BIT_GPIOE_INT_EN_8822B BIT(30)
+#define BIT_GPIOD_INT_EN_8822B BIT(29)
+#define BIT_GPIOC_INT_EN_8822B BIT(28)
+#define BIT_GPIOB_INT_EN_8822B BIT(27)
+#define BIT_GPIOA_INT_EN_8822B BIT(26)
+#define BIT_GPIO9_INT_EN_8822B BIT(25)
+#define BIT_GPIO8_INT_EN_8822B BIT(24)
+#define BIT_GPIO7_INT_EN_8822B BIT(23)
+#define BIT_GPIO6_INT_EN_8822B BIT(22)
+#define BIT_GPIO5_INT_EN_8822B BIT(21)
+#define BIT_GPIO4_INT_EN_8822B BIT(20)
+#define BIT_GPIO3_INT_EN_8822B BIT(19)
+#define BIT_GPIO2_INT_EN_V1_8822B BIT(18)
+#define BIT_GPIO1_INT_EN_8822B BIT(17)
+#define BIT_GPIO0_INT_EN_8822B BIT(16)
+#define BIT_PDNINT_EN_8822B BIT(7)
+#define BIT_RON_INT_EN_8822B BIT(6)
+#define BIT_SPS_OCP_INT_EN_8822B BIT(5)
+#define BIT_GPIO15_0_INT_EN_8822B BIT(0)
+
+/* 2 REG_HSISR_8822B */
+#define BIT_GPIOF_INT_8822B BIT(31)
+#define BIT_GPIOE_INT_8822B BIT(30)
+#define BIT_GPIOD_INT_8822B BIT(29)
+#define BIT_GPIOC_INT_8822B BIT(28)
+#define BIT_GPIOB_INT_8822B BIT(27)
+#define BIT_GPIOA_INT_8822B BIT(26)
+#define BIT_GPIO9_INT_8822B BIT(25)
+#define BIT_GPIO8_INT_8822B BIT(24)
+#define BIT_GPIO7_INT_8822B BIT(23)
+#define BIT_GPIO6_INT_8822B BIT(22)
+#define BIT_GPIO5_INT_8822B BIT(21)
+#define BIT_GPIO4_INT_8822B BIT(20)
+#define BIT_GPIO3_INT_8822B BIT(19)
+#define BIT_GPIO2_INT_V1_8822B BIT(18)
+#define BIT_GPIO1_INT_8822B BIT(17)
+#define BIT_GPIO0_INT_8822B BIT(16)
+#define BIT_PDNINT_8822B BIT(7)
+#define BIT_RON_INT_8822B BIT(6)
+#define BIT_SPS_OCP_INT_8822B BIT(5)
+#define BIT_GPIO15_0_INT_8822B BIT(0)
+
+/* 2 REG_GPIO_EXT_CTRL_8822B */
+
+#define BIT_SHIFT_GPIO_MOD_15_TO_8_8822B 24
+#define BIT_MASK_GPIO_MOD_15_TO_8_8822B 0xff
+#define BIT_GPIO_MOD_15_TO_8_8822B(x)                                          \
+	(((x) & BIT_MASK_GPIO_MOD_15_TO_8_8822B)                               \
+	 << BIT_SHIFT_GPIO_MOD_15_TO_8_8822B)
+#define BITS_GPIO_MOD_15_TO_8_8822B                                            \
+	(BIT_MASK_GPIO_MOD_15_TO_8_8822B << BIT_SHIFT_GPIO_MOD_15_TO_8_8822B)
+#define BIT_CLEAR_GPIO_MOD_15_TO_8_8822B(x)                                    \
+	((x) & (~BITS_GPIO_MOD_15_TO_8_8822B))
+#define BIT_GET_GPIO_MOD_15_TO_8_8822B(x)                                      \
+	(((x) >> BIT_SHIFT_GPIO_MOD_15_TO_8_8822B) &                           \
+	 BIT_MASK_GPIO_MOD_15_TO_8_8822B)
+#define BIT_SET_GPIO_MOD_15_TO_8_8822B(x, v)                                   \
+	(BIT_CLEAR_GPIO_MOD_15_TO_8_8822B(x) | BIT_GPIO_MOD_15_TO_8_8822B(v))
+
+#define BIT_SHIFT_GPIO_IO_SEL_15_TO_8_8822B 16
+#define BIT_MASK_GPIO_IO_SEL_15_TO_8_8822B 0xff
+#define BIT_GPIO_IO_SEL_15_TO_8_8822B(x)                                       \
+	(((x) & BIT_MASK_GPIO_IO_SEL_15_TO_8_8822B)                            \
+	 << BIT_SHIFT_GPIO_IO_SEL_15_TO_8_8822B)
+#define BITS_GPIO_IO_SEL_15_TO_8_8822B                                         \
+	(BIT_MASK_GPIO_IO_SEL_15_TO_8_8822B                                    \
+	 << BIT_SHIFT_GPIO_IO_SEL_15_TO_8_8822B)
+#define BIT_CLEAR_GPIO_IO_SEL_15_TO_8_8822B(x)                                 \
+	((x) & (~BITS_GPIO_IO_SEL_15_TO_8_8822B))
+#define BIT_GET_GPIO_IO_SEL_15_TO_8_8822B(x)                                   \
+	(((x) >> BIT_SHIFT_GPIO_IO_SEL_15_TO_8_8822B) &                        \
+	 BIT_MASK_GPIO_IO_SEL_15_TO_8_8822B)
+#define BIT_SET_GPIO_IO_SEL_15_TO_8_8822B(x, v)                                \
+	(BIT_CLEAR_GPIO_IO_SEL_15_TO_8_8822B(x) |                              \
+	 BIT_GPIO_IO_SEL_15_TO_8_8822B(v))
+
+#define BIT_SHIFT_GPIO_OUT_15_TO_8_8822B 8
+#define BIT_MASK_GPIO_OUT_15_TO_8_8822B 0xff
+#define BIT_GPIO_OUT_15_TO_8_8822B(x)                                          \
+	(((x) & BIT_MASK_GPIO_OUT_15_TO_8_8822B)                               \
+	 << BIT_SHIFT_GPIO_OUT_15_TO_8_8822B)
+#define BITS_GPIO_OUT_15_TO_8_8822B                                            \
+	(BIT_MASK_GPIO_OUT_15_TO_8_8822B << BIT_SHIFT_GPIO_OUT_15_TO_8_8822B)
+#define BIT_CLEAR_GPIO_OUT_15_TO_8_8822B(x)                                    \
+	((x) & (~BITS_GPIO_OUT_15_TO_8_8822B))
+#define BIT_GET_GPIO_OUT_15_TO_8_8822B(x)                                      \
+	(((x) >> BIT_SHIFT_GPIO_OUT_15_TO_8_8822B) &                           \
+	 BIT_MASK_GPIO_OUT_15_TO_8_8822B)
+#define BIT_SET_GPIO_OUT_15_TO_8_8822B(x, v)                                   \
+	(BIT_CLEAR_GPIO_OUT_15_TO_8_8822B(x) | BIT_GPIO_OUT_15_TO_8_8822B(v))
+
+#define BIT_SHIFT_GPIO_IN_15_TO_8_8822B 0
+#define BIT_MASK_GPIO_IN_15_TO_8_8822B 0xff
+#define BIT_GPIO_IN_15_TO_8_8822B(x)                                           \
+	(((x) & BIT_MASK_GPIO_IN_15_TO_8_8822B)                                \
+	 << BIT_SHIFT_GPIO_IN_15_TO_8_8822B)
+#define BITS_GPIO_IN_15_TO_8_8822B                                             \
+	(BIT_MASK_GPIO_IN_15_TO_8_8822B << BIT_SHIFT_GPIO_IN_15_TO_8_8822B)
+#define BIT_CLEAR_GPIO_IN_15_TO_8_8822B(x) ((x) & (~BITS_GPIO_IN_15_TO_8_8822B))
+#define BIT_GET_GPIO_IN_15_TO_8_8822B(x)                                       \
+	(((x) >> BIT_SHIFT_GPIO_IN_15_TO_8_8822B) &                            \
+	 BIT_MASK_GPIO_IN_15_TO_8_8822B)
+#define BIT_SET_GPIO_IN_15_TO_8_8822B(x, v)                                    \
+	(BIT_CLEAR_GPIO_IN_15_TO_8_8822B(x) | BIT_GPIO_IN_15_TO_8_8822B(v))
+
+/* 2 REG_PAD_CTRL1_8822B */
+#define BIT_PAPE_WLBT_SEL_8822B BIT(29)
+#define BIT_LNAON_WLBT_SEL_8822B BIT(28)
+#define BIT_BTGP_GPG3_FEN_8822B BIT(26)
+#define BIT_BTGP_GPG2_FEN_8822B BIT(25)
+#define BIT_BTGP_JTAG_EN_8822B BIT(24)
+#define BIT_XTAL_CLK_EXTARNAL_EN_8822B BIT(23)
+#define BIT_BTGP_UART0_EN_8822B BIT(22)
+#define BIT_BTGP_UART1_EN_8822B BIT(21)
+#define BIT_BTGP_SPI_EN_8822B BIT(20)
+#define BIT_BTGP_GPIO_E2_8822B BIT(19)
+#define BIT_BTGP_GPIO_EN_8822B BIT(18)
+
+#define BIT_SHIFT_BTGP_GPIO_SL_8822B 16
+#define BIT_MASK_BTGP_GPIO_SL_8822B 0x3
+#define BIT_BTGP_GPIO_SL_8822B(x)                                              \
+	(((x) & BIT_MASK_BTGP_GPIO_SL_8822B) << BIT_SHIFT_BTGP_GPIO_SL_8822B)
+#define BITS_BTGP_GPIO_SL_8822B                                                \
+	(BIT_MASK_BTGP_GPIO_SL_8822B << BIT_SHIFT_BTGP_GPIO_SL_8822B)
+#define BIT_CLEAR_BTGP_GPIO_SL_8822B(x) ((x) & (~BITS_BTGP_GPIO_SL_8822B))
+#define BIT_GET_BTGP_GPIO_SL_8822B(x)                                          \
+	(((x) >> BIT_SHIFT_BTGP_GPIO_SL_8822B) & BIT_MASK_BTGP_GPIO_SL_8822B)
+#define BIT_SET_BTGP_GPIO_SL_8822B(x, v)                                       \
+	(BIT_CLEAR_BTGP_GPIO_SL_8822B(x) | BIT_BTGP_GPIO_SL_8822B(v))
+
+#define BIT_PAD_SDIO_SR_8822B BIT(14)
+#define BIT_GPIO14_OUTPUT_PL_8822B BIT(13)
+#define BIT_HOST_WAKE_PAD_PULL_EN_8822B BIT(12)
+#define BIT_HOST_WAKE_PAD_SL_8822B BIT(11)
+#define BIT_PAD_LNAON_SR_8822B BIT(10)
+#define BIT_PAD_LNAON_E2_8822B BIT(9)
+#define BIT_SW_LNAON_G_SEL_DATA_8822B BIT(8)
+#define BIT_SW_LNAON_A_SEL_DATA_8822B BIT(7)
+#define BIT_PAD_PAPE_SR_8822B BIT(6)
+#define BIT_PAD_PAPE_E2_8822B BIT(5)
+#define BIT_SW_PAPE_G_SEL_DATA_8822B BIT(4)
+#define BIT_SW_PAPE_A_SEL_DATA_8822B BIT(3)
+#define BIT_PAD_DPDT_SR_8822B BIT(2)
+#define BIT_PAD_DPDT_PAD_E2_8822B BIT(1)
+#define BIT_SW_DPDT_SEL_DATA_8822B BIT(0)
+
+/* 2 REG_WL_BT_PWR_CTRL_8822B */
+#define BIT_ISO_BD2PP_8822B BIT(31)
+#define BIT_LDOV12B_EN_8822B BIT(30)
+#define BIT_CKEN_BTGPS_8822B BIT(29)
+#define BIT_FEN_BTGPS_8822B BIT(28)
+#define BIT_BTCPU_BOOTSEL_8822B BIT(27)
+#define BIT_SPI_SPEEDUP_8822B BIT(26)
+#define BIT_DEVWAKE_PAD_TYPE_SEL_8822B BIT(24)
+#define BIT_CLKREQ_PAD_TYPE_SEL_8822B BIT(23)
+#define BIT_ISO_BTPON2PP_8822B BIT(22)
+#define BIT_BT_HWROF_EN_8822B BIT(19)
+#define BIT_BT_FUNC_EN_8822B BIT(18)
+#define BIT_BT_HWPDN_SL_8822B BIT(17)
+#define BIT_BT_DISN_EN_8822B BIT(16)
+#define BIT_BT_PDN_PULL_EN_8822B BIT(15)
+#define BIT_WL_PDN_PULL_EN_8822B BIT(14)
+#define BIT_EXTERNAL_REQUEST_PL_8822B BIT(13)
+#define BIT_GPIO0_2_3_PULL_LOW_EN_8822B BIT(12)
+#define BIT_ISO_BA2PP_8822B BIT(11)
+#define BIT_BT_AFE_LDO_EN_8822B BIT(10)
+#define BIT_BT_AFE_PLL_EN_8822B BIT(9)
+#define BIT_BT_DIG_CLK_EN_8822B BIT(8)
+#define BIT_WL_DRV_EXIST_IDX_8822B BIT(5)
+#define BIT_DOP_EHPAD_8822B BIT(4)
+#define BIT_WL_HWROF_EN_8822B BIT(3)
+#define BIT_WL_FUNC_EN_8822B BIT(2)
+#define BIT_WL_HWPDN_SL_8822B BIT(1)
+#define BIT_WL_HWPDN_EN_8822B BIT(0)
+
+/* 2 REG_SDM_DEBUG_8822B */
+
+#define BIT_SHIFT_WLCLK_PHASE_8822B 0
+#define BIT_MASK_WLCLK_PHASE_8822B 0x1f
+#define BIT_WLCLK_PHASE_8822B(x)                                               \
+	(((x) & BIT_MASK_WLCLK_PHASE_8822B) << BIT_SHIFT_WLCLK_PHASE_8822B)
+#define BITS_WLCLK_PHASE_8822B                                                 \
+	(BIT_MASK_WLCLK_PHASE_8822B << BIT_SHIFT_WLCLK_PHASE_8822B)
+#define BIT_CLEAR_WLCLK_PHASE_8822B(x) ((x) & (~BITS_WLCLK_PHASE_8822B))
+#define BIT_GET_WLCLK_PHASE_8822B(x)                                           \
+	(((x) >> BIT_SHIFT_WLCLK_PHASE_8822B) & BIT_MASK_WLCLK_PHASE_8822B)
+#define BIT_SET_WLCLK_PHASE_8822B(x, v)                                        \
+	(BIT_CLEAR_WLCLK_PHASE_8822B(x) | BIT_WLCLK_PHASE_8822B(v))
+
+/* 2 REG_SYS_SDIO_CTRL_8822B */
+#define BIT_DBG_GNT_WL_BT_8822B BIT(27)
+#define BIT_LTE_MUX_CTRL_PATH_8822B BIT(26)
+#define BIT_LTE_COEX_UART_8822B BIT(25)
+#define BIT_3W_LTE_WL_GPIO_8822B BIT(24)
+#define BIT_SDIO_INT_POLARITY_8822B BIT(19)
+#define BIT_SDIO_INT_8822B BIT(18)
+#define BIT_SDIO_OFF_EN_8822B BIT(17)
+#define BIT_SDIO_ON_EN_8822B BIT(16)
+#define BIT_PCIE_WAIT_TIMEOUT_EVENT_8822B BIT(10)
+#define BIT_PCIE_WAIT_TIME_8822B BIT(9)
+#define BIT_MPCIE_REFCLK_XTAL_SEL_8822B BIT(8)
+
+#define BIT_SHIFT_SI_AUTHORIZATION_8822B 0
+#define BIT_MASK_SI_AUTHORIZATION_8822B 0xff
+#define BIT_SI_AUTHORIZATION_8822B(x)                                          \
+	(((x) & BIT_MASK_SI_AUTHORIZATION_8822B)                               \
+	 << BIT_SHIFT_SI_AUTHORIZATION_8822B)
+#define BITS_SI_AUTHORIZATION_8822B                                            \
+	(BIT_MASK_SI_AUTHORIZATION_8822B << BIT_SHIFT_SI_AUTHORIZATION_8822B)
+#define BIT_CLEAR_SI_AUTHORIZATION_8822B(x)                                    \
+	((x) & (~BITS_SI_AUTHORIZATION_8822B))
+#define BIT_GET_SI_AUTHORIZATION_8822B(x)                                      \
+	(((x) >> BIT_SHIFT_SI_AUTHORIZATION_8822B) &                           \
+	 BIT_MASK_SI_AUTHORIZATION_8822B)
+#define BIT_SET_SI_AUTHORIZATION_8822B(x, v)                                   \
+	(BIT_CLEAR_SI_AUTHORIZATION_8822B(x) | BIT_SI_AUTHORIZATION_8822B(v))
+
+/* 2 REG_HCI_OPT_CTRL_8822B */
+
+#define BIT_SHIFT_TSFT_SEL_8822B 29
+#define BIT_MASK_TSFT_SEL_8822B 0x7
+#define BIT_TSFT_SEL_8822B(x)                                                  \
+	(((x) & BIT_MASK_TSFT_SEL_8822B) << BIT_SHIFT_TSFT_SEL_8822B)
+#define BITS_TSFT_SEL_8822B                                                    \
+	(BIT_MASK_TSFT_SEL_8822B << BIT_SHIFT_TSFT_SEL_8822B)
+#define BIT_CLEAR_TSFT_SEL_8822B(x) ((x) & (~BITS_TSFT_SEL_8822B))
+#define BIT_GET_TSFT_SEL_8822B(x)                                              \
+	(((x) >> BIT_SHIFT_TSFT_SEL_8822B) & BIT_MASK_TSFT_SEL_8822B)
+#define BIT_SET_TSFT_SEL_8822B(x, v)                                           \
+	(BIT_CLEAR_TSFT_SEL_8822B(x) | BIT_TSFT_SEL_8822B(v))
+
+#define BIT_USB_HOST_PWR_OFF_EN_8822B BIT(12)
+#define BIT_SYM_LPS_BLOCK_EN_8822B BIT(11)
+#define BIT_USB_LPM_ACT_EN_8822B BIT(10)
+#define BIT_USB_LPM_NY_8822B BIT(9)
+#define BIT_USB_SUS_DIS_8822B BIT(8)
+
+#define BIT_SHIFT_SDIO_PAD_E_8822B 5
+#define BIT_MASK_SDIO_PAD_E_8822B 0x7
+#define BIT_SDIO_PAD_E_8822B(x)                                                \
+	(((x) & BIT_MASK_SDIO_PAD_E_8822B) << BIT_SHIFT_SDIO_PAD_E_8822B)
+#define BITS_SDIO_PAD_E_8822B                                                  \
+	(BIT_MASK_SDIO_PAD_E_8822B << BIT_SHIFT_SDIO_PAD_E_8822B)
+#define BIT_CLEAR_SDIO_PAD_E_8822B(x) ((x) & (~BITS_SDIO_PAD_E_8822B))
+#define BIT_GET_SDIO_PAD_E_8822B(x)                                            \
+	(((x) >> BIT_SHIFT_SDIO_PAD_E_8822B) & BIT_MASK_SDIO_PAD_E_8822B)
+#define BIT_SET_SDIO_PAD_E_8822B(x, v)                                         \
+	(BIT_CLEAR_SDIO_PAD_E_8822B(x) | BIT_SDIO_PAD_E_8822B(v))
+
+#define BIT_USB_LPPLL_EN_8822B BIT(4)
+#define BIT_ROP_SW15_8822B BIT(2)
+#define BIT_PCI_CKRDY_OPT_8822B BIT(1)
+#define BIT_PCI_VAUX_EN_8822B BIT(0)
+
+/* 2 REG_AFE_CTRL4_8822B */
+
+/* 2 REG_LDO_SWR_CTRL_8822B */
+#define BIT_ZCD_HW_AUTO_EN_8822B BIT(27)
+#define BIT_ZCD_REGSEL_8822B BIT(26)
+
+#define BIT_SHIFT_AUTO_ZCD_IN_CODE_8822B 21
+#define BIT_MASK_AUTO_ZCD_IN_CODE_8822B 0x1f
+#define BIT_AUTO_ZCD_IN_CODE_8822B(x)                                          \
+	(((x) & BIT_MASK_AUTO_ZCD_IN_CODE_8822B)                               \
+	 << BIT_SHIFT_AUTO_ZCD_IN_CODE_8822B)
+#define BITS_AUTO_ZCD_IN_CODE_8822B                                            \
+	(BIT_MASK_AUTO_ZCD_IN_CODE_8822B << BIT_SHIFT_AUTO_ZCD_IN_CODE_8822B)
+#define BIT_CLEAR_AUTO_ZCD_IN_CODE_8822B(x)                                    \
+	((x) & (~BITS_AUTO_ZCD_IN_CODE_8822B))
+#define BIT_GET_AUTO_ZCD_IN_CODE_8822B(x)                                      \
+	(((x) >> BIT_SHIFT_AUTO_ZCD_IN_CODE_8822B) &                           \
+	 BIT_MASK_AUTO_ZCD_IN_CODE_8822B)
+#define BIT_SET_AUTO_ZCD_IN_CODE_8822B(x, v)                                   \
+	(BIT_CLEAR_AUTO_ZCD_IN_CODE_8822B(x) | BIT_AUTO_ZCD_IN_CODE_8822B(v))
+
+#define BIT_SHIFT_ZCD_CODE_IN_L_8822B 16
+#define BIT_MASK_ZCD_CODE_IN_L_8822B 0x1f
+#define BIT_ZCD_CODE_IN_L_8822B(x)                                             \
+	(((x) & BIT_MASK_ZCD_CODE_IN_L_8822B) << BIT_SHIFT_ZCD_CODE_IN_L_8822B)
+#define BITS_ZCD_CODE_IN_L_8822B                                               \
+	(BIT_MASK_ZCD_CODE_IN_L_8822B << BIT_SHIFT_ZCD_CODE_IN_L_8822B)
+#define BIT_CLEAR_ZCD_CODE_IN_L_8822B(x) ((x) & (~BITS_ZCD_CODE_IN_L_8822B))
+#define BIT_GET_ZCD_CODE_IN_L_8822B(x)                                         \
+	(((x) >> BIT_SHIFT_ZCD_CODE_IN_L_8822B) & BIT_MASK_ZCD_CODE_IN_L_8822B)
+#define BIT_SET_ZCD_CODE_IN_L_8822B(x, v)                                      \
+	(BIT_CLEAR_ZCD_CODE_IN_L_8822B(x) | BIT_ZCD_CODE_IN_L_8822B(v))
+
+#define BIT_SHIFT_LDO_HV5_DUMMY_8822B 14
+#define BIT_MASK_LDO_HV5_DUMMY_8822B 0x3
+#define BIT_LDO_HV5_DUMMY_8822B(x)                                             \
+	(((x) & BIT_MASK_LDO_HV5_DUMMY_8822B) << BIT_SHIFT_LDO_HV5_DUMMY_8822B)
+#define BITS_LDO_HV5_DUMMY_8822B                                               \
+	(BIT_MASK_LDO_HV5_DUMMY_8822B << BIT_SHIFT_LDO_HV5_DUMMY_8822B)
+#define BIT_CLEAR_LDO_HV5_DUMMY_8822B(x) ((x) & (~BITS_LDO_HV5_DUMMY_8822B))
+#define BIT_GET_LDO_HV5_DUMMY_8822B(x)                                         \
+	(((x) >> BIT_SHIFT_LDO_HV5_DUMMY_8822B) & BIT_MASK_LDO_HV5_DUMMY_8822B)
+#define BIT_SET_LDO_HV5_DUMMY_8822B(x, v)                                      \
+	(BIT_CLEAR_LDO_HV5_DUMMY_8822B(x) | BIT_LDO_HV5_DUMMY_8822B(v))
+
+#define BIT_SHIFT_REG_VTUNE33_BIT0_TO_BIT1_8822B 12
+#define BIT_MASK_REG_VTUNE33_BIT0_TO_BIT1_8822B 0x3
+#define BIT_REG_VTUNE33_BIT0_TO_BIT1_8822B(x)                                  \
+	(((x) & BIT_MASK_REG_VTUNE33_BIT0_TO_BIT1_8822B)                       \
+	 << BIT_SHIFT_REG_VTUNE33_BIT0_TO_BIT1_8822B)
+#define BITS_REG_VTUNE33_BIT0_TO_BIT1_8822B                                    \
+	(BIT_MASK_REG_VTUNE33_BIT0_TO_BIT1_8822B                               \
+	 << BIT_SHIFT_REG_VTUNE33_BIT0_TO_BIT1_8822B)
+#define BIT_CLEAR_REG_VTUNE33_BIT0_TO_BIT1_8822B(x)                            \
+	((x) & (~BITS_REG_VTUNE33_BIT0_TO_BIT1_8822B))
+#define BIT_GET_REG_VTUNE33_BIT0_TO_BIT1_8822B(x)                              \
+	(((x) >> BIT_SHIFT_REG_VTUNE33_BIT0_TO_BIT1_8822B) &                   \
+	 BIT_MASK_REG_VTUNE33_BIT0_TO_BIT1_8822B)
+#define BIT_SET_REG_VTUNE33_BIT0_TO_BIT1_8822B(x, v)                           \
+	(BIT_CLEAR_REG_VTUNE33_BIT0_TO_BIT1_8822B(x) |                         \
+	 BIT_REG_VTUNE33_BIT0_TO_BIT1_8822B(v))
+
+#define BIT_SHIFT_REG_STANDBY33_BIT0_TO_BIT1_8822B 10
+#define BIT_MASK_REG_STANDBY33_BIT0_TO_BIT1_8822B 0x3
+#define BIT_REG_STANDBY33_BIT0_TO_BIT1_8822B(x)                                \
+	(((x) & BIT_MASK_REG_STANDBY33_BIT0_TO_BIT1_8822B)                     \
+	 << BIT_SHIFT_REG_STANDBY33_BIT0_TO_BIT1_8822B)
+#define BITS_REG_STANDBY33_BIT0_TO_BIT1_8822B                                  \
+	(BIT_MASK_REG_STANDBY33_BIT0_TO_BIT1_8822B                             \
+	 << BIT_SHIFT_REG_STANDBY33_BIT0_TO_BIT1_8822B)
+#define BIT_CLEAR_REG_STANDBY33_BIT0_TO_BIT1_8822B(x)                          \
+	((x) & (~BITS_REG_STANDBY33_BIT0_TO_BIT1_8822B))
+#define BIT_GET_REG_STANDBY33_BIT0_TO_BIT1_8822B(x)                            \
+	(((x) >> BIT_SHIFT_REG_STANDBY33_BIT0_TO_BIT1_8822B) &                 \
+	 BIT_MASK_REG_STANDBY33_BIT0_TO_BIT1_8822B)
+#define BIT_SET_REG_STANDBY33_BIT0_TO_BIT1_8822B(x, v)                         \
+	(BIT_CLEAR_REG_STANDBY33_BIT0_TO_BIT1_8822B(x) |                       \
+	 BIT_REG_STANDBY33_BIT0_TO_BIT1_8822B(v))
+
+#define BIT_SHIFT_REG_LOAD33_BIT0_TO_BIT1_8822B 8
+#define BIT_MASK_REG_LOAD33_BIT0_TO_BIT1_8822B 0x3
+#define BIT_REG_LOAD33_BIT0_TO_BIT1_8822B(x)                                   \
+	(((x) & BIT_MASK_REG_LOAD33_BIT0_TO_BIT1_8822B)                        \
+	 << BIT_SHIFT_REG_LOAD33_BIT0_TO_BIT1_8822B)
+#define BITS_REG_LOAD33_BIT0_TO_BIT1_8822B                                     \
+	(BIT_MASK_REG_LOAD33_BIT0_TO_BIT1_8822B                                \
+	 << BIT_SHIFT_REG_LOAD33_BIT0_TO_BIT1_8822B)
+#define BIT_CLEAR_REG_LOAD33_BIT0_TO_BIT1_8822B(x)                             \
+	((x) & (~BITS_REG_LOAD33_BIT0_TO_BIT1_8822B))
+#define BIT_GET_REG_LOAD33_BIT0_TO_BIT1_8822B(x)                               \
+	(((x) >> BIT_SHIFT_REG_LOAD33_BIT0_TO_BIT1_8822B) &                    \
+	 BIT_MASK_REG_LOAD33_BIT0_TO_BIT1_8822B)
+#define BIT_SET_REG_LOAD33_BIT0_TO_BIT1_8822B(x, v)                            \
+	(BIT_CLEAR_REG_LOAD33_BIT0_TO_BIT1_8822B(x) |                          \
+	 BIT_REG_LOAD33_BIT0_TO_BIT1_8822B(v))
+
+#define BIT_REG_BYPASS_L_8822B BIT(7)
+#define BIT_REG_LDOF_L_8822B BIT(6)
+#define BIT_REG_TYPE_L_V1_8822B BIT(5)
+#define BIT_ARENB_L_8822B BIT(3)
+
+#define BIT_SHIFT_CFC_L_8822B 1
+#define BIT_MASK_CFC_L_8822B 0x3
+#define BIT_CFC_L_8822B(x)                                                     \
+	(((x) & BIT_MASK_CFC_L_8822B) << BIT_SHIFT_CFC_L_8822B)
+#define BITS_CFC_L_8822B (BIT_MASK_CFC_L_8822B << BIT_SHIFT_CFC_L_8822B)
+#define BIT_CLEAR_CFC_L_8822B(x) ((x) & (~BITS_CFC_L_8822B))
+#define BIT_GET_CFC_L_8822B(x)                                                 \
+	(((x) >> BIT_SHIFT_CFC_L_8822B) & BIT_MASK_CFC_L_8822B)
+#define BIT_SET_CFC_L_8822B(x, v)                                              \
+	(BIT_CLEAR_CFC_L_8822B(x) | BIT_CFC_L_8822B(v))
+
+#define BIT_REG_OCPS_L_V1_8822B BIT(0)
+
+/* 2 REG_MCUFW_CTRL_8822B */
+
+#define BIT_SHIFT_RPWM_8822B 24
+#define BIT_MASK_RPWM_8822B 0xff
+#define BIT_RPWM_8822B(x) (((x) & BIT_MASK_RPWM_8822B) << BIT_SHIFT_RPWM_8822B)
+#define BITS_RPWM_8822B (BIT_MASK_RPWM_8822B << BIT_SHIFT_RPWM_8822B)
+#define BIT_CLEAR_RPWM_8822B(x) ((x) & (~BITS_RPWM_8822B))
+#define BIT_GET_RPWM_8822B(x)                                                  \
+	(((x) >> BIT_SHIFT_RPWM_8822B) & BIT_MASK_RPWM_8822B)
+#define BIT_SET_RPWM_8822B(x, v) (BIT_CLEAR_RPWM_8822B(x) | BIT_RPWM_8822B(v))
+
+#define BIT_ANA_PORT_EN_8822B BIT(22)
+#define BIT_MAC_PORT_EN_8822B BIT(21)
+#define BIT_BOOT_FSPI_EN_8822B BIT(20)
+#define BIT_ROM_DLEN_8822B BIT(19)
+
+#define BIT_SHIFT_ROM_PGE_8822B 16
+#define BIT_MASK_ROM_PGE_8822B 0x7
+#define BIT_ROM_PGE_8822B(x)                                                   \
+	(((x) & BIT_MASK_ROM_PGE_8822B) << BIT_SHIFT_ROM_PGE_8822B)
+#define BITS_ROM_PGE_8822B (BIT_MASK_ROM_PGE_8822B << BIT_SHIFT_ROM_PGE_8822B)
+#define BIT_CLEAR_ROM_PGE_8822B(x) ((x) & (~BITS_ROM_PGE_8822B))
+#define BIT_GET_ROM_PGE_8822B(x)                                               \
+	(((x) >> BIT_SHIFT_ROM_PGE_8822B) & BIT_MASK_ROM_PGE_8822B)
+#define BIT_SET_ROM_PGE_8822B(x, v)                                            \
+	(BIT_CLEAR_ROM_PGE_8822B(x) | BIT_ROM_PGE_8822B(v))
+
+#define BIT_FW_INIT_RDY_8822B BIT(15)
+#define BIT_FW_DW_RDY_8822B BIT(14)
+
+#define BIT_SHIFT_CPU_CLK_SEL_8822B 12
+#define BIT_MASK_CPU_CLK_SEL_8822B 0x3
+#define BIT_CPU_CLK_SEL_8822B(x)                                               \
+	(((x) & BIT_MASK_CPU_CLK_SEL_8822B) << BIT_SHIFT_CPU_CLK_SEL_8822B)
+#define BITS_CPU_CLK_SEL_8822B                                                 \
+	(BIT_MASK_CPU_CLK_SEL_8822B << BIT_SHIFT_CPU_CLK_SEL_8822B)
+#define BIT_CLEAR_CPU_CLK_SEL_8822B(x) ((x) & (~BITS_CPU_CLK_SEL_8822B))
+#define BIT_GET_CPU_CLK_SEL_8822B(x)                                           \
+	(((x) >> BIT_SHIFT_CPU_CLK_SEL_8822B) & BIT_MASK_CPU_CLK_SEL_8822B)
+#define BIT_SET_CPU_CLK_SEL_8822B(x, v)                                        \
+	(BIT_CLEAR_CPU_CLK_SEL_8822B(x) | BIT_CPU_CLK_SEL_8822B(v))
+
+#define BIT_CCLK_CHG_MASK_8822B BIT(11)
+#define BIT_EMEM__TXBUF_CHKSUM_OK_8822B BIT(10)
+#define BIT_EMEM_TXBUF_DW_RDY_8822B BIT(9)
+#define BIT_EMEM_CHKSUM_OK_8822B BIT(8)
+#define BIT_EMEM_DW_OK_8822B BIT(7)
+#define BIT_DMEM_CHKSUM_OK_8822B BIT(6)
+#define BIT_DMEM_DW_OK_8822B BIT(5)
+#define BIT_IMEM_CHKSUM_OK_8822B BIT(4)
+#define BIT_IMEM_DW_OK_8822B BIT(3)
+#define BIT_IMEM_BOOT_LOAD_CHKSUM_OK_8822B BIT(2)
+#define BIT_IMEM_BOOT_LOAD_DW_OK_8822B BIT(1)
+#define BIT_MCUFWDL_EN_8822B BIT(0)
+
+/* 2 REG_MCU_TST_CFG_8822B */
+
+#define BIT_SHIFT_C2H_MSG_8822B 0
+#define BIT_MASK_C2H_MSG_8822B 0xffff
+#define BIT_C2H_MSG_8822B(x)                                                   \
+	(((x) & BIT_MASK_C2H_MSG_8822B) << BIT_SHIFT_C2H_MSG_8822B)
+#define BITS_C2H_MSG_8822B (BIT_MASK_C2H_MSG_8822B << BIT_SHIFT_C2H_MSG_8822B)
+#define BIT_CLEAR_C2H_MSG_8822B(x) ((x) & (~BITS_C2H_MSG_8822B))
+#define BIT_GET_C2H_MSG_8822B(x)                                               \
+	(((x) >> BIT_SHIFT_C2H_MSG_8822B) & BIT_MASK_C2H_MSG_8822B)
+#define BIT_SET_C2H_MSG_8822B(x, v)                                            \
+	(BIT_CLEAR_C2H_MSG_8822B(x) | BIT_C2H_MSG_8822B(v))
+
+/* 2 REG_HMEBOX_E0_E1_8822B */
+
+#define BIT_SHIFT_HOST_MSG_E1_8822B 16
+#define BIT_MASK_HOST_MSG_E1_8822B 0xffff
+#define BIT_HOST_MSG_E1_8822B(x)                                               \
+	(((x) & BIT_MASK_HOST_MSG_E1_8822B) << BIT_SHIFT_HOST_MSG_E1_8822B)
+#define BITS_HOST_MSG_E1_8822B                                                 \
+	(BIT_MASK_HOST_MSG_E1_8822B << BIT_SHIFT_HOST_MSG_E1_8822B)
+#define BIT_CLEAR_HOST_MSG_E1_8822B(x) ((x) & (~BITS_HOST_MSG_E1_8822B))
+#define BIT_GET_HOST_MSG_E1_8822B(x)                                           \
+	(((x) >> BIT_SHIFT_HOST_MSG_E1_8822B) & BIT_MASK_HOST_MSG_E1_8822B)
+#define BIT_SET_HOST_MSG_E1_8822B(x, v)                                        \
+	(BIT_CLEAR_HOST_MSG_E1_8822B(x) | BIT_HOST_MSG_E1_8822B(v))
+
+#define BIT_SHIFT_HOST_MSG_E0_8822B 0
+#define BIT_MASK_HOST_MSG_E0_8822B 0xffff
+#define BIT_HOST_MSG_E0_8822B(x)                                               \
+	(((x) & BIT_MASK_HOST_MSG_E0_8822B) << BIT_SHIFT_HOST_MSG_E0_8822B)
+#define BITS_HOST_MSG_E0_8822B                                                 \
+	(BIT_MASK_HOST_MSG_E0_8822B << BIT_SHIFT_HOST_MSG_E0_8822B)
+#define BIT_CLEAR_HOST_MSG_E0_8822B(x) ((x) & (~BITS_HOST_MSG_E0_8822B))
+#define BIT_GET_HOST_MSG_E0_8822B(x)                                           \
+	(((x) >> BIT_SHIFT_HOST_MSG_E0_8822B) & BIT_MASK_HOST_MSG_E0_8822B)
+#define BIT_SET_HOST_MSG_E0_8822B(x, v)                                        \
+	(BIT_CLEAR_HOST_MSG_E0_8822B(x) | BIT_HOST_MSG_E0_8822B(v))
+
+/* 2 REG_HMEBOX_E2_E3_8822B */
+
+#define BIT_SHIFT_HOST_MSG_E3_8822B 16
+#define BIT_MASK_HOST_MSG_E3_8822B 0xffff
+#define BIT_HOST_MSG_E3_8822B(x)                                               \
+	(((x) & BIT_MASK_HOST_MSG_E3_8822B) << BIT_SHIFT_HOST_MSG_E3_8822B)
+#define BITS_HOST_MSG_E3_8822B                                                 \
+	(BIT_MASK_HOST_MSG_E3_8822B << BIT_SHIFT_HOST_MSG_E3_8822B)
+#define BIT_CLEAR_HOST_MSG_E3_8822B(x) ((x) & (~BITS_HOST_MSG_E3_8822B))
+#define BIT_GET_HOST_MSG_E3_8822B(x)                                           \
+	(((x) >> BIT_SHIFT_HOST_MSG_E3_8822B) & BIT_MASK_HOST_MSG_E3_8822B)
+#define BIT_SET_HOST_MSG_E3_8822B(x, v)                                        \
+	(BIT_CLEAR_HOST_MSG_E3_8822B(x) | BIT_HOST_MSG_E3_8822B(v))
+
+#define BIT_SHIFT_HOST_MSG_E2_8822B 0
+#define BIT_MASK_HOST_MSG_E2_8822B 0xffff
+#define BIT_HOST_MSG_E2_8822B(x)                                               \
+	(((x) & BIT_MASK_HOST_MSG_E2_8822B) << BIT_SHIFT_HOST_MSG_E2_8822B)
+#define BITS_HOST_MSG_E2_8822B                                                 \
+	(BIT_MASK_HOST_MSG_E2_8822B << BIT_SHIFT_HOST_MSG_E2_8822B)
+#define BIT_CLEAR_HOST_MSG_E2_8822B(x) ((x) & (~BITS_HOST_MSG_E2_8822B))
+#define BIT_GET_HOST_MSG_E2_8822B(x)                                           \
+	(((x) >> BIT_SHIFT_HOST_MSG_E2_8822B) & BIT_MASK_HOST_MSG_E2_8822B)
+#define BIT_SET_HOST_MSG_E2_8822B(x, v)                                        \
+	(BIT_CLEAR_HOST_MSG_E2_8822B(x) | BIT_HOST_MSG_E2_8822B(v))
+
+/* 2 REG_WLLPS_CTRL_8822B */
+#define BIT_WLLPSOP_EABM_8822B BIT(31)
+#define BIT_WLLPSOP_ACKF_8822B BIT(30)
+#define BIT_WLLPSOP_DLDM_8822B BIT(29)
+#define BIT_WLLPSOP_ESWR_8822B BIT(28)
+#define BIT_WLLPSOP_PWMM_8822B BIT(27)
+#define BIT_WLLPSOP_EECK_8822B BIT(26)
+#define BIT_WLLPSOP_WLMACOFF_8822B BIT(25)
+#define BIT_WLLPSOP_EXTAL_8822B BIT(24)
+#define BIT_WL_SYNPON_VOLTSPDN_8822B BIT(23)
+#define BIT_WLLPSOP_WLBBOFF_8822B BIT(22)
+#define BIT_WLLPSOP_WLMEM_DS_8822B BIT(21)
+
+#define BIT_SHIFT_LPLDH12_VADJ_STEP_DN_8822B 12
+#define BIT_MASK_LPLDH12_VADJ_STEP_DN_8822B 0xf
+#define BIT_LPLDH12_VADJ_STEP_DN_8822B(x)                                      \
+	(((x) & BIT_MASK_LPLDH12_VADJ_STEP_DN_8822B)                           \
+	 << BIT_SHIFT_LPLDH12_VADJ_STEP_DN_8822B)
+#define BITS_LPLDH12_VADJ_STEP_DN_8822B                                        \
+	(BIT_MASK_LPLDH12_VADJ_STEP_DN_8822B                                   \
+	 << BIT_SHIFT_LPLDH12_VADJ_STEP_DN_8822B)
+#define BIT_CLEAR_LPLDH12_VADJ_STEP_DN_8822B(x)                                \
+	((x) & (~BITS_LPLDH12_VADJ_STEP_DN_8822B))
+#define BIT_GET_LPLDH12_VADJ_STEP_DN_8822B(x)                                  \
+	(((x) >> BIT_SHIFT_LPLDH12_VADJ_STEP_DN_8822B) &                       \
+	 BIT_MASK_LPLDH12_VADJ_STEP_DN_8822B)
+#define BIT_SET_LPLDH12_VADJ_STEP_DN_8822B(x, v)                               \
+	(BIT_CLEAR_LPLDH12_VADJ_STEP_DN_8822B(x) |                             \
+	 BIT_LPLDH12_VADJ_STEP_DN_8822B(v))
+
+#define BIT_SHIFT_V15ADJ_L1_STEP_DN_8822B 8
+#define BIT_MASK_V15ADJ_L1_STEP_DN_8822B 0x7
+#define BIT_V15ADJ_L1_STEP_DN_8822B(x)                                         \
+	(((x) & BIT_MASK_V15ADJ_L1_STEP_DN_8822B)                              \
+	 << BIT_SHIFT_V15ADJ_L1_STEP_DN_8822B)
+#define BITS_V15ADJ_L1_STEP_DN_8822B                                           \
+	(BIT_MASK_V15ADJ_L1_STEP_DN_8822B << BIT_SHIFT_V15ADJ_L1_STEP_DN_8822B)
+#define BIT_CLEAR_V15ADJ_L1_STEP_DN_8822B(x)                                   \
+	((x) & (~BITS_V15ADJ_L1_STEP_DN_8822B))
+#define BIT_GET_V15ADJ_L1_STEP_DN_8822B(x)                                     \
+	(((x) >> BIT_SHIFT_V15ADJ_L1_STEP_DN_8822B) &                          \
+	 BIT_MASK_V15ADJ_L1_STEP_DN_8822B)
+#define BIT_SET_V15ADJ_L1_STEP_DN_8822B(x, v)                                  \
+	(BIT_CLEAR_V15ADJ_L1_STEP_DN_8822B(x) | BIT_V15ADJ_L1_STEP_DN_8822B(v))
+
+#define BIT_REGU_32K_CLK_EN_8822B BIT(1)
+#define BIT_WL_LPS_EN_8822B BIT(0)
+
+/* 2 REG_AFE_CTRL5_8822B */
+#define BIT_BB_DBG_SEL_AFE_SDM_BIT0_8822B BIT(31)
+#define BIT_ORDER_SDM_8822B BIT(30)
+#define BIT_RFE_SEL_SDM_8822B BIT(29)
+
+#define BIT_SHIFT_REF_SEL_8822B 25
+#define BIT_MASK_REF_SEL_8822B 0xf
+#define BIT_REF_SEL_8822B(x)                                                   \
+	(((x) & BIT_MASK_REF_SEL_8822B) << BIT_SHIFT_REF_SEL_8822B)
+#define BITS_REF_SEL_8822B (BIT_MASK_REF_SEL_8822B << BIT_SHIFT_REF_SEL_8822B)
+#define BIT_CLEAR_REF_SEL_8822B(x) ((x) & (~BITS_REF_SEL_8822B))
+#define BIT_GET_REF_SEL_8822B(x)                                               \
+	(((x) >> BIT_SHIFT_REF_SEL_8822B) & BIT_MASK_REF_SEL_8822B)
+#define BIT_SET_REF_SEL_8822B(x, v)                                            \
+	(BIT_CLEAR_REF_SEL_8822B(x) | BIT_REF_SEL_8822B(v))
+
+#define BIT_SHIFT_F0F_SDM_8822B 12
+#define BIT_MASK_F0F_SDM_8822B 0x1fff
+#define BIT_F0F_SDM_8822B(x)                                                   \
+	(((x) & BIT_MASK_F0F_SDM_8822B) << BIT_SHIFT_F0F_SDM_8822B)
+#define BITS_F0F_SDM_8822B (BIT_MASK_F0F_SDM_8822B << BIT_SHIFT_F0F_SDM_8822B)
+#define BIT_CLEAR_F0F_SDM_8822B(x) ((x) & (~BITS_F0F_SDM_8822B))
+#define BIT_GET_F0F_SDM_8822B(x)                                               \
+	(((x) >> BIT_SHIFT_F0F_SDM_8822B) & BIT_MASK_F0F_SDM_8822B)
+#define BIT_SET_F0F_SDM_8822B(x, v)                                            \
+	(BIT_CLEAR_F0F_SDM_8822B(x) | BIT_F0F_SDM_8822B(v))
+
+#define BIT_SHIFT_F0N_SDM_8822B 9
+#define BIT_MASK_F0N_SDM_8822B 0x7
+#define BIT_F0N_SDM_8822B(x)                                                   \
+	(((x) & BIT_MASK_F0N_SDM_8822B) << BIT_SHIFT_F0N_SDM_8822B)
+#define BITS_F0N_SDM_8822B (BIT_MASK_F0N_SDM_8822B << BIT_SHIFT_F0N_SDM_8822B)
+#define BIT_CLEAR_F0N_SDM_8822B(x) ((x) & (~BITS_F0N_SDM_8822B))
+#define BIT_GET_F0N_SDM_8822B(x)                                               \
+	(((x) >> BIT_SHIFT_F0N_SDM_8822B) & BIT_MASK_F0N_SDM_8822B)
+#define BIT_SET_F0N_SDM_8822B(x, v)                                            \
+	(BIT_CLEAR_F0N_SDM_8822B(x) | BIT_F0N_SDM_8822B(v))
+
+#define BIT_SHIFT_DIVN_SDM_8822B 3
+#define BIT_MASK_DIVN_SDM_8822B 0x3f
+#define BIT_DIVN_SDM_8822B(x)                                                  \
+	(((x) & BIT_MASK_DIVN_SDM_8822B) << BIT_SHIFT_DIVN_SDM_8822B)
+#define BITS_DIVN_SDM_8822B                                                    \
+	(BIT_MASK_DIVN_SDM_8822B << BIT_SHIFT_DIVN_SDM_8822B)
+#define BIT_CLEAR_DIVN_SDM_8822B(x) ((x) & (~BITS_DIVN_SDM_8822B))
+#define BIT_GET_DIVN_SDM_8822B(x)                                              \
+	(((x) >> BIT_SHIFT_DIVN_SDM_8822B) & BIT_MASK_DIVN_SDM_8822B)
+#define BIT_SET_DIVN_SDM_8822B(x, v)                                           \
+	(BIT_CLEAR_DIVN_SDM_8822B(x) | BIT_DIVN_SDM_8822B(v))
+
+/* 2 REG_GPIO_DEBOUNCE_CTRL_8822B */
+#define BIT_WLGP_DBC1EN_8822B BIT(15)
+
+#define BIT_SHIFT_WLGP_DBC1_8822B 8
+#define BIT_MASK_WLGP_DBC1_8822B 0xf
+#define BIT_WLGP_DBC1_8822B(x)                                                 \
+	(((x) & BIT_MASK_WLGP_DBC1_8822B) << BIT_SHIFT_WLGP_DBC1_8822B)
+#define BITS_WLGP_DBC1_8822B                                                   \
+	(BIT_MASK_WLGP_DBC1_8822B << BIT_SHIFT_WLGP_DBC1_8822B)
+#define BIT_CLEAR_WLGP_DBC1_8822B(x) ((x) & (~BITS_WLGP_DBC1_8822B))
+#define BIT_GET_WLGP_DBC1_8822B(x)                                             \
+	(((x) >> BIT_SHIFT_WLGP_DBC1_8822B) & BIT_MASK_WLGP_DBC1_8822B)
+#define BIT_SET_WLGP_DBC1_8822B(x, v)                                          \
+	(BIT_CLEAR_WLGP_DBC1_8822B(x) | BIT_WLGP_DBC1_8822B(v))
+
+#define BIT_WLGP_DBC0EN_8822B BIT(7)
+
+#define BIT_SHIFT_WLGP_DBC0_8822B 0
+#define BIT_MASK_WLGP_DBC0_8822B 0xf
+#define BIT_WLGP_DBC0_8822B(x)                                                 \
+	(((x) & BIT_MASK_WLGP_DBC0_8822B) << BIT_SHIFT_WLGP_DBC0_8822B)
+#define BITS_WLGP_DBC0_8822B                                                   \
+	(BIT_MASK_WLGP_DBC0_8822B << BIT_SHIFT_WLGP_DBC0_8822B)
+#define BIT_CLEAR_WLGP_DBC0_8822B(x) ((x) & (~BITS_WLGP_DBC0_8822B))
+#define BIT_GET_WLGP_DBC0_8822B(x)                                             \
+	(((x) >> BIT_SHIFT_WLGP_DBC0_8822B) & BIT_MASK_WLGP_DBC0_8822B)
+#define BIT_SET_WLGP_DBC0_8822B(x, v)                                          \
+	(BIT_CLEAR_WLGP_DBC0_8822B(x) | BIT_WLGP_DBC0_8822B(v))
+
+/* 2 REG_RPWM2_8822B */
+
+#define BIT_SHIFT_RPWM2_8822B 16
+#define BIT_MASK_RPWM2_8822B 0xffff
+#define BIT_RPWM2_8822B(x)                                                     \
+	(((x) & BIT_MASK_RPWM2_8822B) << BIT_SHIFT_RPWM2_8822B)
+#define BITS_RPWM2_8822B (BIT_MASK_RPWM2_8822B << BIT_SHIFT_RPWM2_8822B)
+#define BIT_CLEAR_RPWM2_8822B(x) ((x) & (~BITS_RPWM2_8822B))
+#define BIT_GET_RPWM2_8822B(x)                                                 \
+	(((x) >> BIT_SHIFT_RPWM2_8822B) & BIT_MASK_RPWM2_8822B)
+#define BIT_SET_RPWM2_8822B(x, v)                                              \
+	(BIT_CLEAR_RPWM2_8822B(x) | BIT_RPWM2_8822B(v))
+
+/* 2 REG_SYSON_FSM_MON_8822B */
+
+#define BIT_SHIFT_FSM_MON_SEL_8822B 24
+#define BIT_MASK_FSM_MON_SEL_8822B 0x7
+#define BIT_FSM_MON_SEL_8822B(x)                                               \
+	(((x) & BIT_MASK_FSM_MON_SEL_8822B) << BIT_SHIFT_FSM_MON_SEL_8822B)
+#define BITS_FSM_MON_SEL_8822B                                                 \
+	(BIT_MASK_FSM_MON_SEL_8822B << BIT_SHIFT_FSM_MON_SEL_8822B)
+#define BIT_CLEAR_FSM_MON_SEL_8822B(x) ((x) & (~BITS_FSM_MON_SEL_8822B))
+#define BIT_GET_FSM_MON_SEL_8822B(x)                                           \
+	(((x) >> BIT_SHIFT_FSM_MON_SEL_8822B) & BIT_MASK_FSM_MON_SEL_8822B)
+#define BIT_SET_FSM_MON_SEL_8822B(x, v)                                        \
+	(BIT_CLEAR_FSM_MON_SEL_8822B(x) | BIT_FSM_MON_SEL_8822B(v))
+
+#define BIT_DOP_ELDO_8822B BIT(23)
+#define BIT_FSM_MON_UPD_8822B BIT(15)
+
+#define BIT_SHIFT_FSM_PAR_8822B 0
+#define BIT_MASK_FSM_PAR_8822B 0x7fff
+#define BIT_FSM_PAR_8822B(x)                                                   \
+	(((x) & BIT_MASK_FSM_PAR_8822B) << BIT_SHIFT_FSM_PAR_8822B)
+#define BITS_FSM_PAR_8822B (BIT_MASK_FSM_PAR_8822B << BIT_SHIFT_FSM_PAR_8822B)
+#define BIT_CLEAR_FSM_PAR_8822B(x) ((x) & (~BITS_FSM_PAR_8822B))
+#define BIT_GET_FSM_PAR_8822B(x)                                               \
+	(((x) >> BIT_SHIFT_FSM_PAR_8822B) & BIT_MASK_FSM_PAR_8822B)
+#define BIT_SET_FSM_PAR_8822B(x, v)                                            \
+	(BIT_CLEAR_FSM_PAR_8822B(x) | BIT_FSM_PAR_8822B(v))
+
+/* 2 REG_AFE_CTRL6_8822B */
+
+#define BIT_SHIFT_BB_DBG_SEL_AFE_SDM_BIT3_1_8822B 0
+#define BIT_MASK_BB_DBG_SEL_AFE_SDM_BIT3_1_8822B 0x7
+#define BIT_BB_DBG_SEL_AFE_SDM_BIT3_1_8822B(x)                                 \
+	(((x) & BIT_MASK_BB_DBG_SEL_AFE_SDM_BIT3_1_8822B)                      \
+	 << BIT_SHIFT_BB_DBG_SEL_AFE_SDM_BIT3_1_8822B)
+#define BITS_BB_DBG_SEL_AFE_SDM_BIT3_1_8822B                                   \
+	(BIT_MASK_BB_DBG_SEL_AFE_SDM_BIT3_1_8822B                              \
+	 << BIT_SHIFT_BB_DBG_SEL_AFE_SDM_BIT3_1_8822B)
+#define BIT_CLEAR_BB_DBG_SEL_AFE_SDM_BIT3_1_8822B(x)                           \
+	((x) & (~BITS_BB_DBG_SEL_AFE_SDM_BIT3_1_8822B))
+#define BIT_GET_BB_DBG_SEL_AFE_SDM_BIT3_1_8822B(x)                             \
+	(((x) >> BIT_SHIFT_BB_DBG_SEL_AFE_SDM_BIT3_1_8822B) &                  \
+	 BIT_MASK_BB_DBG_SEL_AFE_SDM_BIT3_1_8822B)
+#define BIT_SET_BB_DBG_SEL_AFE_SDM_BIT3_1_8822B(x, v)                          \
+	(BIT_CLEAR_BB_DBG_SEL_AFE_SDM_BIT3_1_8822B(x) |                        \
+	 BIT_BB_DBG_SEL_AFE_SDM_BIT3_1_8822B(v))
+
+/* 2 REG_PMC_DBG_CTRL1_8822B */
+#define BIT_BT_INT_EN_8822B BIT(31)
+
+#define BIT_SHIFT_RD_WR_WIFI_BT_INFO_8822B 16
+#define BIT_MASK_RD_WR_WIFI_BT_INFO_8822B 0x7fff
+#define BIT_RD_WR_WIFI_BT_INFO_8822B(x)                                        \
+	(((x) & BIT_MASK_RD_WR_WIFI_BT_INFO_8822B)                             \
+	 << BIT_SHIFT_RD_WR_WIFI_BT_INFO_8822B)
+#define BITS_RD_WR_WIFI_BT_INFO_8822B                                          \
+	(BIT_MASK_RD_WR_WIFI_BT_INFO_8822B                                     \
+	 << BIT_SHIFT_RD_WR_WIFI_BT_INFO_8822B)
+#define BIT_CLEAR_RD_WR_WIFI_BT_INFO_8822B(x)                                  \
+	((x) & (~BITS_RD_WR_WIFI_BT_INFO_8822B))
+#define BIT_GET_RD_WR_WIFI_BT_INFO_8822B(x)                                    \
+	(((x) >> BIT_SHIFT_RD_WR_WIFI_BT_INFO_8822B) &                         \
+	 BIT_MASK_RD_WR_WIFI_BT_INFO_8822B)
+#define BIT_SET_RD_WR_WIFI_BT_INFO_8822B(x, v)                                 \
+	(BIT_CLEAR_RD_WR_WIFI_BT_INFO_8822B(x) |                               \
+	 BIT_RD_WR_WIFI_BT_INFO_8822B(v))
+
+#define BIT_PMC_WR_OVF_8822B BIT(8)
+
+#define BIT_SHIFT_WLPMC_ERRINT_8822B 0
+#define BIT_MASK_WLPMC_ERRINT_8822B 0xff
+#define BIT_WLPMC_ERRINT_8822B(x)                                              \
+	(((x) & BIT_MASK_WLPMC_ERRINT_8822B) << BIT_SHIFT_WLPMC_ERRINT_8822B)
+#define BITS_WLPMC_ERRINT_8822B                                                \
+	(BIT_MASK_WLPMC_ERRINT_8822B << BIT_SHIFT_WLPMC_ERRINT_8822B)
+#define BIT_CLEAR_WLPMC_ERRINT_8822B(x) ((x) & (~BITS_WLPMC_ERRINT_8822B))
+#define BIT_GET_WLPMC_ERRINT_8822B(x)                                          \
+	(((x) >> BIT_SHIFT_WLPMC_ERRINT_8822B) & BIT_MASK_WLPMC_ERRINT_8822B)
+#define BIT_SET_WLPMC_ERRINT_8822B(x, v)                                       \
+	(BIT_CLEAR_WLPMC_ERRINT_8822B(x) | BIT_WLPMC_ERRINT_8822B(v))
+
+/* 2 REG_AFE_CTRL7_8822B */
+
+#define BIT_SHIFT_SEL_V_8822B 30
+#define BIT_MASK_SEL_V_8822B 0x3
+#define BIT_SEL_V_8822B(x)                                                     \
+	(((x) & BIT_MASK_SEL_V_8822B) << BIT_SHIFT_SEL_V_8822B)
+#define BITS_SEL_V_8822B (BIT_MASK_SEL_V_8822B << BIT_SHIFT_SEL_V_8822B)
+#define BIT_CLEAR_SEL_V_8822B(x) ((x) & (~BITS_SEL_V_8822B))
+#define BIT_GET_SEL_V_8822B(x)                                                 \
+	(((x) >> BIT_SHIFT_SEL_V_8822B) & BIT_MASK_SEL_V_8822B)
+#define BIT_SET_SEL_V_8822B(x, v)                                              \
+	(BIT_CLEAR_SEL_V_8822B(x) | BIT_SEL_V_8822B(v))
+
+#define BIT_SEL_LDO_PC_8822B BIT(29)
+
+#define BIT_SHIFT_CK_MON_SEL_8822B 26
+#define BIT_MASK_CK_MON_SEL_8822B 0x7
+#define BIT_CK_MON_SEL_8822B(x)                                                \
+	(((x) & BIT_MASK_CK_MON_SEL_8822B) << BIT_SHIFT_CK_MON_SEL_8822B)
+#define BITS_CK_MON_SEL_8822B                                                  \
+	(BIT_MASK_CK_MON_SEL_8822B << BIT_SHIFT_CK_MON_SEL_8822B)
+#define BIT_CLEAR_CK_MON_SEL_8822B(x) ((x) & (~BITS_CK_MON_SEL_8822B))
+#define BIT_GET_CK_MON_SEL_8822B(x)                                            \
+	(((x) >> BIT_SHIFT_CK_MON_SEL_8822B) & BIT_MASK_CK_MON_SEL_8822B)
+#define BIT_SET_CK_MON_SEL_8822B(x, v)                                         \
+	(BIT_CLEAR_CK_MON_SEL_8822B(x) | BIT_CK_MON_SEL_8822B(v))
+
+#define BIT_CK_MON_EN_8822B BIT(25)
+#define BIT_FREF_EDGE_8822B BIT(24)
+#define BIT_CK320M_EN_8822B BIT(23)
+#define BIT_CK_5M_EN_8822B BIT(22)
+#define BIT_TESTEN_8822B BIT(21)
+
+/* 2 REG_HIMR0_8822B */
+#define BIT_TIMEOUT_INTERRUPT2_MASK_8822B BIT(31)
+#define BIT_TIMEOUT_INTERRUTP1_MASK_8822B BIT(30)
+#define BIT_PSTIMEOUT_MSK_8822B BIT(29)
+#define BIT_GTINT4_MSK_8822B BIT(28)
+#define BIT_GTINT3_MSK_8822B BIT(27)
+#define BIT_TXBCN0ERR_MSK_8822B BIT(26)
+#define BIT_TXBCN0OK_MSK_8822B BIT(25)
+#define BIT_TSF_BIT32_TOGGLE_MSK_8822B BIT(24)
+#define BIT_BCNDMAINT0_MSK_8822B BIT(20)
+#define BIT_BCNDERR0_MSK_8822B BIT(16)
+#define BIT_HSISR_IND_ON_INT_MSK_8822B BIT(15)
+#define BIT_HISR3_IND_INT_MSK_8822B BIT(14)
+#define BIT_HISR2_IND_INT_MSK_8822B BIT(13)
+#define BIT_HISR1_IND_MSK_8822B BIT(11)
+#define BIT_C2HCMD_MSK_8822B BIT(10)
+#define BIT_CPWM2_MSK_8822B BIT(9)
+#define BIT_CPWM_MSK_8822B BIT(8)
+#define BIT_HIGHDOK_MSK_8822B BIT(7)
+#define BIT_MGTDOK_MSK_8822B BIT(6)
+#define BIT_BKDOK_MSK_8822B BIT(5)
+#define BIT_BEDOK_MSK_8822B BIT(4)
+#define BIT_VIDOK_MSK_8822B BIT(3)
+#define BIT_VODOK_MSK_8822B BIT(2)
+#define BIT_RDU_MSK_8822B BIT(1)
+#define BIT_RXOK_MSK_8822B BIT(0)
+
+/* 2 REG_HISR0_8822B */
+#define BIT_PSTIMEOUT2_8822B BIT(31)
+#define BIT_PSTIMEOUT1_8822B BIT(30)
+#define BIT_PSTIMEOUT_8822B BIT(29)
+#define BIT_GTINT4_8822B BIT(28)
+#define BIT_GTINT3_8822B BIT(27)
+#define BIT_TXBCN0ERR_8822B BIT(26)
+#define BIT_TXBCN0OK_8822B BIT(25)
+#define BIT_TSF_BIT32_TOGGLE_8822B BIT(24)
+#define BIT_BCNDMAINT0_8822B BIT(20)
+#define BIT_BCNDERR0_8822B BIT(16)
+#define BIT_HSISR_IND_ON_INT_8822B BIT(15)
+#define BIT_HISR3_IND_INT_8822B BIT(14)
+#define BIT_HISR2_IND_INT_8822B BIT(13)
+#define BIT_HISR1_IND_INT_8822B BIT(11)
+#define BIT_C2HCMD_8822B BIT(10)
+#define BIT_CPWM2_8822B BIT(9)
+#define BIT_CPWM_8822B BIT(8)
+#define BIT_HIGHDOK_8822B BIT(7)
+#define BIT_MGTDOK_8822B BIT(6)
+#define BIT_BKDOK_8822B BIT(5)
+#define BIT_BEDOK_8822B BIT(4)
+#define BIT_VIDOK_8822B BIT(3)
+#define BIT_VODOK_8822B BIT(2)
+#define BIT_RDU_8822B BIT(1)
+#define BIT_RXOK_8822B BIT(0)
+
+/* 2 REG_HIMR1_8822B */
+#define BIT_TXFIFO_TH_INT_8822B BIT(30)
+#define BIT_BTON_STS_UPDATE_MASK_8822B BIT(29)
+#define BIT_BCNDMAINT7__MSK_8822B BIT(27)
+#define BIT_BCNDMAINT6__MSK_8822B BIT(26)
+#define BIT_BCNDMAINT5__MSK_8822B BIT(25)
+#define BIT_BCNDMAINT4__MSK_8822B BIT(24)
+#define BIT_BCNDMAINT3_MSK_8822B BIT(23)
+#define BIT_BCNDMAINT2_MSK_8822B BIT(22)
+#define BIT_BCNDMAINT1_MSK_8822B BIT(21)
+#define BIT_BCNDERR7_MSK_8822B BIT(20)
+#define BIT_BCNDERR6_MSK_8822B BIT(19)
+#define BIT_BCNDERR5_MSK_8822B BIT(18)
+#define BIT_BCNDERR4_MSK_8822B BIT(17)
+#define BIT_BCNDERR3_MSK_8822B BIT(16)
+#define BIT_BCNDERR2_MSK_8822B BIT(15)
+#define BIT_BCNDERR1_MSK_8822B BIT(14)
+#define BIT_ATIMEND_E_V1_MSK_8822B BIT(12)
+#define BIT_TXERR_MSK_8822B BIT(11)
+#define BIT_RXERR_MSK_8822B BIT(10)
+#define BIT_TXFOVW_MSK_8822B BIT(9)
+#define BIT_FOVW_MSK_8822B BIT(8)
+#define BIT_CPU_MGQ_TXDONE_MSK_8822B BIT(5)
+#define BIT_PS_TIMER_C_MSK_8822B BIT(4)
+#define BIT_PS_TIMER_B_MSK_8822B BIT(3)
+#define BIT_PS_TIMER_A_MSK_8822B BIT(2)
+#define BIT_CPUMGQ_TX_TIMER_MSK_8822B BIT(1)
+
+/* 2 REG_HISR1_8822B */
+#define BIT_TXFIFO_TH_INT_8822B BIT(30)
+#define BIT_BTON_STS_UPDATE_INT_8822B BIT(29)
+#define BIT_BCNDMAINT7_8822B BIT(27)
+#define BIT_BCNDMAINT6_8822B BIT(26)
+#define BIT_BCNDMAINT5_8822B BIT(25)
+#define BIT_BCNDMAINT4_8822B BIT(24)
+#define BIT_BCNDMAINT3_8822B BIT(23)
+#define BIT_BCNDMAINT2_8822B BIT(22)
+#define BIT_BCNDMAINT1_8822B BIT(21)
+#define BIT_BCNDERR7_8822B BIT(20)
+#define BIT_BCNDERR6_8822B BIT(19)
+#define BIT_BCNDERR5_8822B BIT(18)
+#define BIT_BCNDERR4_8822B BIT(17)
+#define BIT_BCNDERR3_8822B BIT(16)
+#define BIT_BCNDERR2_8822B BIT(15)
+#define BIT_BCNDERR1_8822B BIT(14)
+#define BIT_ATIMEND_E_V1_INT_8822B BIT(12)
+#define BIT_TXERR_INT_8822B BIT(11)
+#define BIT_RXERR_INT_8822B BIT(10)
+#define BIT_TXFOVW_8822B BIT(9)
+#define BIT_FOVW_8822B BIT(8)
+#define BIT_CPU_MGQ_TXDONE_8822B BIT(5)
+#define BIT_PS_TIMER_C_8822B BIT(4)
+#define BIT_PS_TIMER_B_8822B BIT(3)
+#define BIT_PS_TIMER_A_8822B BIT(2)
+#define BIT_CPUMGQ_TX_TIMER_8822B BIT(1)
+
+/* 2 REG_DBG_PORT_SEL_8822B */
+
+#define BIT_SHIFT_DEBUG_ST_8822B 0
+#define BIT_MASK_DEBUG_ST_8822B 0xffffffffL
+#define BIT_DEBUG_ST_8822B(x)                                                  \
+	(((x) & BIT_MASK_DEBUG_ST_8822B) << BIT_SHIFT_DEBUG_ST_8822B)
+#define BITS_DEBUG_ST_8822B                                                    \
+	(BIT_MASK_DEBUG_ST_8822B << BIT_SHIFT_DEBUG_ST_8822B)
+#define BIT_CLEAR_DEBUG_ST_8822B(x) ((x) & (~BITS_DEBUG_ST_8822B))
+#define BIT_GET_DEBUG_ST_8822B(x)                                              \
+	(((x) >> BIT_SHIFT_DEBUG_ST_8822B) & BIT_MASK_DEBUG_ST_8822B)
+#define BIT_SET_DEBUG_ST_8822B(x, v)                                           \
+	(BIT_CLEAR_DEBUG_ST_8822B(x) | BIT_DEBUG_ST_8822B(v))
+
+/* 2 REG_PAD_CTRL2_8822B */
+#define BIT_USB3_USB2_TRANSITION_8822B BIT(20)
+
+#define BIT_SHIFT_USB23_SW_MODE_V1_8822B 18
+#define BIT_MASK_USB23_SW_MODE_V1_8822B 0x3
+#define BIT_USB23_SW_MODE_V1_8822B(x)                                          \
+	(((x) & BIT_MASK_USB23_SW_MODE_V1_8822B)                               \
+	 << BIT_SHIFT_USB23_SW_MODE_V1_8822B)
+#define BITS_USB23_SW_MODE_V1_8822B                                            \
+	(BIT_MASK_USB23_SW_MODE_V1_8822B << BIT_SHIFT_USB23_SW_MODE_V1_8822B)
+#define BIT_CLEAR_USB23_SW_MODE_V1_8822B(x)                                    \
+	((x) & (~BITS_USB23_SW_MODE_V1_8822B))
+#define BIT_GET_USB23_SW_MODE_V1_8822B(x)                                      \
+	(((x) >> BIT_SHIFT_USB23_SW_MODE_V1_8822B) &                           \
+	 BIT_MASK_USB23_SW_MODE_V1_8822B)
+#define BIT_SET_USB23_SW_MODE_V1_8822B(x, v)                                   \
+	(BIT_CLEAR_USB23_SW_MODE_V1_8822B(x) | BIT_USB23_SW_MODE_V1_8822B(v))
+
+#define BIT_NO_PDN_CHIPOFF_V1_8822B BIT(17)
+#define BIT_RSM_EN_V1_8822B BIT(16)
+
+#define BIT_SHIFT_MATCH_CNT_8822B 8
+#define BIT_MASK_MATCH_CNT_8822B 0xff
+#define BIT_MATCH_CNT_8822B(x)                                                 \
+	(((x) & BIT_MASK_MATCH_CNT_8822B) << BIT_SHIFT_MATCH_CNT_8822B)
+#define BITS_MATCH_CNT_8822B                                                   \
+	(BIT_MASK_MATCH_CNT_8822B << BIT_SHIFT_MATCH_CNT_8822B)
+#define BIT_CLEAR_MATCH_CNT_8822B(x) ((x) & (~BITS_MATCH_CNT_8822B))
+#define BIT_GET_MATCH_CNT_8822B(x)                                             \
+	(((x) >> BIT_SHIFT_MATCH_CNT_8822B) & BIT_MASK_MATCH_CNT_8822B)
+#define BIT_SET_MATCH_CNT_8822B(x, v)                                          \
+	(BIT_CLEAR_MATCH_CNT_8822B(x) | BIT_MATCH_CNT_8822B(v))
+
+#define BIT_LD_B12V_EN_8822B BIT(7)
+#define BIT_EECS_IOSEL_V1_8822B BIT(6)
+#define BIT_EECS_DATA_O_V1_8822B BIT(5)
+#define BIT_EECS_DATA_I_V1_8822B BIT(4)
+#define BIT_EESK_IOSEL_V1_8822B BIT(2)
+#define BIT_EESK_DATA_O_V1_8822B BIT(1)
+#define BIT_EESK_DATA_I_V1_8822B BIT(0)
+
+/* 2 REG_NOT_VALID_8822B */
+
+/* 2 REG_PMC_DBG_CTRL2_8822B */
+
+#define BIT_SHIFT_EFUSE_BURN_GNT_8822B 24
+#define BIT_MASK_EFUSE_BURN_GNT_8822B 0xff
+#define BIT_EFUSE_BURN_GNT_8822B(x)                                            \
+	(((x) & BIT_MASK_EFUSE_BURN_GNT_8822B)                                 \
+	 << BIT_SHIFT_EFUSE_BURN_GNT_8822B)
+#define BITS_EFUSE_BURN_GNT_8822B                                              \
+	(BIT_MASK_EFUSE_BURN_GNT_8822B << BIT_SHIFT_EFUSE_BURN_GNT_8822B)
+#define BIT_CLEAR_EFUSE_BURN_GNT_8822B(x) ((x) & (~BITS_EFUSE_BURN_GNT_8822B))
+#define BIT_GET_EFUSE_BURN_GNT_8822B(x)                                        \
+	(((x) >> BIT_SHIFT_EFUSE_BURN_GNT_8822B) &                             \
+	 BIT_MASK_EFUSE_BURN_GNT_8822B)
+#define BIT_SET_EFUSE_BURN_GNT_8822B(x, v)                                     \
+	(BIT_CLEAR_EFUSE_BURN_GNT_8822B(x) | BIT_EFUSE_BURN_GNT_8822B(v))
+
+#define BIT_STOP_WL_PMC_8822B BIT(9)
+#define BIT_STOP_SYM_PMC_8822B BIT(8)
+#define BIT_REG_RST_WLPMC_8822B BIT(5)
+#define BIT_REG_RST_PD12N_8822B BIT(4)
+#define BIT_SYSON_DIS_WLREG_WRMSK_8822B BIT(3)
+#define BIT_SYSON_DIS_PMCREG_WRMSK_8822B BIT(2)
+
+#define BIT_SHIFT_SYSON_REG_ARB_8822B 0
+#define BIT_MASK_SYSON_REG_ARB_8822B 0x3
+#define BIT_SYSON_REG_ARB_8822B(x)                                             \
+	(((x) & BIT_MASK_SYSON_REG_ARB_8822B) << BIT_SHIFT_SYSON_REG_ARB_8822B)
+#define BITS_SYSON_REG_ARB_8822B                                               \
+	(BIT_MASK_SYSON_REG_ARB_8822B << BIT_SHIFT_SYSON_REG_ARB_8822B)
+#define BIT_CLEAR_SYSON_REG_ARB_8822B(x) ((x) & (~BITS_SYSON_REG_ARB_8822B))
+#define BIT_GET_SYSON_REG_ARB_8822B(x)                                         \
+	(((x) >> BIT_SHIFT_SYSON_REG_ARB_8822B) & BIT_MASK_SYSON_REG_ARB_8822B)
+#define BIT_SET_SYSON_REG_ARB_8822B(x, v)                                      \
+	(BIT_CLEAR_SYSON_REG_ARB_8822B(x) | BIT_SYSON_REG_ARB_8822B(v))
+
+/* 2 REG_BIST_CTRL_8822B */
+#define BIT_BIST_USB_DIS_8822B BIT(27)
+#define BIT_BIST_PCI_DIS_8822B BIT(26)
+#define BIT_BIST_BT_DIS_8822B BIT(25)
+#define BIT_BIST_WL_DIS_8822B BIT(24)
+
+#define BIT_SHIFT_BIST_RPT_SEL_8822B 16
+#define BIT_MASK_BIST_RPT_SEL_8822B 0xf
+#define BIT_BIST_RPT_SEL_8822B(x)                                              \
+	(((x) & BIT_MASK_BIST_RPT_SEL_8822B) << BIT_SHIFT_BIST_RPT_SEL_8822B)
+#define BITS_BIST_RPT_SEL_8822B                                                \
+	(BIT_MASK_BIST_RPT_SEL_8822B << BIT_SHIFT_BIST_RPT_SEL_8822B)
+#define BIT_CLEAR_BIST_RPT_SEL_8822B(x) ((x) & (~BITS_BIST_RPT_SEL_8822B))
+#define BIT_GET_BIST_RPT_SEL_8822B(x)                                          \
+	(((x) >> BIT_SHIFT_BIST_RPT_SEL_8822B) & BIT_MASK_BIST_RPT_SEL_8822B)
+#define BIT_SET_BIST_RPT_SEL_8822B(x, v)                                       \
+	(BIT_CLEAR_BIST_RPT_SEL_8822B(x) | BIT_BIST_RPT_SEL_8822B(v))
+
+#define BIT_BIST_RESUME_PS_8822B BIT(4)
+#define BIT_BIST_RESUME_8822B BIT(3)
+#define BIT_BIST_NORMAL_8822B BIT(2)
+#define BIT_BIST_RSTN_8822B BIT(1)
+#define BIT_BIST_CLK_EN_8822B BIT(0)
+
+/* 2 REG_BIST_RPT_8822B */
+
+#define BIT_SHIFT_MBIST_REPORT_8822B 0
+#define BIT_MASK_MBIST_REPORT_8822B 0xffffffffL
+#define BIT_MBIST_REPORT_8822B(x)                                              \
+	(((x) & BIT_MASK_MBIST_REPORT_8822B) << BIT_SHIFT_MBIST_REPORT_8822B)
+#define BITS_MBIST_REPORT_8822B                                                \
+	(BIT_MASK_MBIST_REPORT_8822B << BIT_SHIFT_MBIST_REPORT_8822B)
+#define BIT_CLEAR_MBIST_REPORT_8822B(x) ((x) & (~BITS_MBIST_REPORT_8822B))
+#define BIT_GET_MBIST_REPORT_8822B(x)                                          \
+	(((x) >> BIT_SHIFT_MBIST_REPORT_8822B) & BIT_MASK_MBIST_REPORT_8822B)
+#define BIT_SET_MBIST_REPORT_8822B(x, v)                                       \
+	(BIT_CLEAR_MBIST_REPORT_8822B(x) | BIT_MBIST_REPORT_8822B(v))
+
+/* 2 REG_MEM_CTRL_8822B */
+#define BIT_UMEM_RME_8822B BIT(31)
+
+#define BIT_SHIFT_BT_SPRAM_8822B 28
+#define BIT_MASK_BT_SPRAM_8822B 0x3
+#define BIT_BT_SPRAM_8822B(x)                                                  \
+	(((x) & BIT_MASK_BT_SPRAM_8822B) << BIT_SHIFT_BT_SPRAM_8822B)
+#define BITS_BT_SPRAM_8822B                                                    \
+	(BIT_MASK_BT_SPRAM_8822B << BIT_SHIFT_BT_SPRAM_8822B)
+#define BIT_CLEAR_BT_SPRAM_8822B(x) ((x) & (~BITS_BT_SPRAM_8822B))
+#define BIT_GET_BT_SPRAM_8822B(x)                                              \
+	(((x) >> BIT_SHIFT_BT_SPRAM_8822B) & BIT_MASK_BT_SPRAM_8822B)
+#define BIT_SET_BT_SPRAM_8822B(x, v)                                           \
+	(BIT_CLEAR_BT_SPRAM_8822B(x) | BIT_BT_SPRAM_8822B(v))
+
+#define BIT_SHIFT_BT_ROM_8822B 24
+#define BIT_MASK_BT_ROM_8822B 0xf
+#define BIT_BT_ROM_8822B(x)                                                    \
+	(((x) & BIT_MASK_BT_ROM_8822B) << BIT_SHIFT_BT_ROM_8822B)
+#define BITS_BT_ROM_8822B (BIT_MASK_BT_ROM_8822B << BIT_SHIFT_BT_ROM_8822B)
+#define BIT_CLEAR_BT_ROM_8822B(x) ((x) & (~BITS_BT_ROM_8822B))
+#define BIT_GET_BT_ROM_8822B(x)                                                \
+	(((x) >> BIT_SHIFT_BT_ROM_8822B) & BIT_MASK_BT_ROM_8822B)
+#define BIT_SET_BT_ROM_8822B(x, v)                                             \
+	(BIT_CLEAR_BT_ROM_8822B(x) | BIT_BT_ROM_8822B(v))
+
+#define BIT_SHIFT_PCI_DPRAM_8822B 10
+#define BIT_MASK_PCI_DPRAM_8822B 0x3
+#define BIT_PCI_DPRAM_8822B(x)                                                 \
+	(((x) & BIT_MASK_PCI_DPRAM_8822B) << BIT_SHIFT_PCI_DPRAM_8822B)
+#define BITS_PCI_DPRAM_8822B                                                   \
+	(BIT_MASK_PCI_DPRAM_8822B << BIT_SHIFT_PCI_DPRAM_8822B)
+#define BIT_CLEAR_PCI_DPRAM_8822B(x) ((x) & (~BITS_PCI_DPRAM_8822B))
+#define BIT_GET_PCI_DPRAM_8822B(x)                                             \
+	(((x) >> BIT_SHIFT_PCI_DPRAM_8822B) & BIT_MASK_PCI_DPRAM_8822B)
+#define BIT_SET_PCI_DPRAM_8822B(x, v)                                          \
+	(BIT_CLEAR_PCI_DPRAM_8822B(x) | BIT_PCI_DPRAM_8822B(v))
+
+#define BIT_SHIFT_PCI_SPRAM_8822B 8
+#define BIT_MASK_PCI_SPRAM_8822B 0x3
+#define BIT_PCI_SPRAM_8822B(x)                                                 \
+	(((x) & BIT_MASK_PCI_SPRAM_8822B) << BIT_SHIFT_PCI_SPRAM_8822B)
+#define BITS_PCI_SPRAM_8822B                                                   \
+	(BIT_MASK_PCI_SPRAM_8822B << BIT_SHIFT_PCI_SPRAM_8822B)
+#define BIT_CLEAR_PCI_SPRAM_8822B(x) ((x) & (~BITS_PCI_SPRAM_8822B))
+#define BIT_GET_PCI_SPRAM_8822B(x)                                             \
+	(((x) >> BIT_SHIFT_PCI_SPRAM_8822B) & BIT_MASK_PCI_SPRAM_8822B)
+#define BIT_SET_PCI_SPRAM_8822B(x, v)                                          \
+	(BIT_CLEAR_PCI_SPRAM_8822B(x) | BIT_PCI_SPRAM_8822B(v))
+
+#define BIT_SHIFT_USB_SPRAM_8822B 6
+#define BIT_MASK_USB_SPRAM_8822B 0x3
+#define BIT_USB_SPRAM_8822B(x)                                                 \
+	(((x) & BIT_MASK_USB_SPRAM_8822B) << BIT_SHIFT_USB_SPRAM_8822B)
+#define BITS_USB_SPRAM_8822B                                                   \
+	(BIT_MASK_USB_SPRAM_8822B << BIT_SHIFT_USB_SPRAM_8822B)
+#define BIT_CLEAR_USB_SPRAM_8822B(x) ((x) & (~BITS_USB_SPRAM_8822B))
+#define BIT_GET_USB_SPRAM_8822B(x)                                             \
+	(((x) >> BIT_SHIFT_USB_SPRAM_8822B) & BIT_MASK_USB_SPRAM_8822B)
+#define BIT_SET_USB_SPRAM_8822B(x, v)                                          \
+	(BIT_CLEAR_USB_SPRAM_8822B(x) | BIT_USB_SPRAM_8822B(v))
+
+#define BIT_SHIFT_USB_SPRF_8822B 4
+#define BIT_MASK_USB_SPRF_8822B 0x3
+#define BIT_USB_SPRF_8822B(x)                                                  \
+	(((x) & BIT_MASK_USB_SPRF_8822B) << BIT_SHIFT_USB_SPRF_8822B)
+#define BITS_USB_SPRF_8822B                                                    \
+	(BIT_MASK_USB_SPRF_8822B << BIT_SHIFT_USB_SPRF_8822B)
+#define BIT_CLEAR_USB_SPRF_8822B(x) ((x) & (~BITS_USB_SPRF_8822B))
+#define BIT_GET_USB_SPRF_8822B(x)                                              \
+	(((x) >> BIT_SHIFT_USB_SPRF_8822B) & BIT_MASK_USB_SPRF_8822B)
+#define BIT_SET_USB_SPRF_8822B(x, v)                                           \
+	(BIT_CLEAR_USB_SPRF_8822B(x) | BIT_USB_SPRF_8822B(v))
+
+#define BIT_SHIFT_MCU_ROM_8822B 0
+#define BIT_MASK_MCU_ROM_8822B 0xf
+#define BIT_MCU_ROM_8822B(x)                                                   \
+	(((x) & BIT_MASK_MCU_ROM_8822B) << BIT_SHIFT_MCU_ROM_8822B)
+#define BITS_MCU_ROM_8822B (BIT_MASK_MCU_ROM_8822B << BIT_SHIFT_MCU_ROM_8822B)
+#define BIT_CLEAR_MCU_ROM_8822B(x) ((x) & (~BITS_MCU_ROM_8822B))
+#define BIT_GET_MCU_ROM_8822B(x)                                               \
+	(((x) >> BIT_SHIFT_MCU_ROM_8822B) & BIT_MASK_MCU_ROM_8822B)
+#define BIT_SET_MCU_ROM_8822B(x, v)                                            \
+	(BIT_CLEAR_MCU_ROM_8822B(x) | BIT_MCU_ROM_8822B(v))
+
+/* 2 REG_AFE_CTRL8_8822B */
+#define BIT_SYN_AGPIO_8822B BIT(20)
+#define BIT_XTAL_LP_8822B BIT(4)
+#define BIT_XTAL_GM_SEP_8822B BIT(3)
+
+#define BIT_SHIFT_XTAL_SEL_TOK_8822B 0
+#define BIT_MASK_XTAL_SEL_TOK_8822B 0x7
+#define BIT_XTAL_SEL_TOK_8822B(x)                                              \
+	(((x) & BIT_MASK_XTAL_SEL_TOK_8822B) << BIT_SHIFT_XTAL_SEL_TOK_8822B)
+#define BITS_XTAL_SEL_TOK_8822B                                                \
+	(BIT_MASK_XTAL_SEL_TOK_8822B << BIT_SHIFT_XTAL_SEL_TOK_8822B)
+#define BIT_CLEAR_XTAL_SEL_TOK_8822B(x) ((x) & (~BITS_XTAL_SEL_TOK_8822B))
+#define BIT_GET_XTAL_SEL_TOK_8822B(x)                                          \
+	(((x) >> BIT_SHIFT_XTAL_SEL_TOK_8822B) & BIT_MASK_XTAL_SEL_TOK_8822B)
+#define BIT_SET_XTAL_SEL_TOK_8822B(x, v)                                       \
+	(BIT_CLEAR_XTAL_SEL_TOK_8822B(x) | BIT_XTAL_SEL_TOK_8822B(v))
+
+/* 2 REG_USB_SIE_INTF_8822B */
+#define BIT_RD_SEL_8822B BIT(31)
+#define BIT_USB_SIE_INTF_WE_V1_8822B BIT(30)
+#define BIT_USB_SIE_INTF_BYIOREG_V1_8822B BIT(29)
+#define BIT_USB_SIE_SELECT_8822B BIT(28)
+
+#define BIT_SHIFT_USB_SIE_INTF_ADDR_V1_8822B 16
+#define BIT_MASK_USB_SIE_INTF_ADDR_V1_8822B 0x1ff
+#define BIT_USB_SIE_INTF_ADDR_V1_8822B(x)                                      \
+	(((x) & BIT_MASK_USB_SIE_INTF_ADDR_V1_8822B)                           \
+	 << BIT_SHIFT_USB_SIE_INTF_ADDR_V1_8822B)
+#define BITS_USB_SIE_INTF_ADDR_V1_8822B                                        \
+	(BIT_MASK_USB_SIE_INTF_ADDR_V1_8822B                                   \
+	 << BIT_SHIFT_USB_SIE_INTF_ADDR_V1_8822B)
+#define BIT_CLEAR_USB_SIE_INTF_ADDR_V1_8822B(x)                                \
+	((x) & (~BITS_USB_SIE_INTF_ADDR_V1_8822B))
+#define BIT_GET_USB_SIE_INTF_ADDR_V1_8822B(x)                                  \
+	(((x) >> BIT_SHIFT_USB_SIE_INTF_ADDR_V1_8822B) &                       \
+	 BIT_MASK_USB_SIE_INTF_ADDR_V1_8822B)
+#define BIT_SET_USB_SIE_INTF_ADDR_V1_8822B(x, v)                               \
+	(BIT_CLEAR_USB_SIE_INTF_ADDR_V1_8822B(x) |                             \
+	 BIT_USB_SIE_INTF_ADDR_V1_8822B(v))
+
+#define BIT_SHIFT_USB_SIE_INTF_RD_8822B 8
+#define BIT_MASK_USB_SIE_INTF_RD_8822B 0xff
+#define BIT_USB_SIE_INTF_RD_8822B(x)                                           \
+	(((x) & BIT_MASK_USB_SIE_INTF_RD_8822B)                                \
+	 << BIT_SHIFT_USB_SIE_INTF_RD_8822B)
+#define BITS_USB_SIE_INTF_RD_8822B                                             \
+	(BIT_MASK_USB_SIE_INTF_RD_8822B << BIT_SHIFT_USB_SIE_INTF_RD_8822B)
+#define BIT_CLEAR_USB_SIE_INTF_RD_8822B(x) ((x) & (~BITS_USB_SIE_INTF_RD_8822B))
+#define BIT_GET_USB_SIE_INTF_RD_8822B(x)                                       \
+	(((x) >> BIT_SHIFT_USB_SIE_INTF_RD_8822B) &                            \
+	 BIT_MASK_USB_SIE_INTF_RD_8822B)
+#define BIT_SET_USB_SIE_INTF_RD_8822B(x, v)                                    \
+	(BIT_CLEAR_USB_SIE_INTF_RD_8822B(x) | BIT_USB_SIE_INTF_RD_8822B(v))
+
+#define BIT_SHIFT_USB_SIE_INTF_WD_8822B 0
+#define BIT_MASK_USB_SIE_INTF_WD_8822B 0xff
+#define BIT_USB_SIE_INTF_WD_8822B(x)                                           \
+	(((x) & BIT_MASK_USB_SIE_INTF_WD_8822B)                                \
+	 << BIT_SHIFT_USB_SIE_INTF_WD_8822B)
+#define BITS_USB_SIE_INTF_WD_8822B                                             \
+	(BIT_MASK_USB_SIE_INTF_WD_8822B << BIT_SHIFT_USB_SIE_INTF_WD_8822B)
+#define BIT_CLEAR_USB_SIE_INTF_WD_8822B(x) ((x) & (~BITS_USB_SIE_INTF_WD_8822B))
+#define BIT_GET_USB_SIE_INTF_WD_8822B(x)                                       \
+	(((x) >> BIT_SHIFT_USB_SIE_INTF_WD_8822B) &                            \
+	 BIT_MASK_USB_SIE_INTF_WD_8822B)
+#define BIT_SET_USB_SIE_INTF_WD_8822B(x, v)                                    \
+	(BIT_CLEAR_USB_SIE_INTF_WD_8822B(x) | BIT_USB_SIE_INTF_WD_8822B(v))
+
+/* 2 REG_PCIE_MIO_INTF_8822B */
+#define BIT_PCIE_MIO_BYIOREG_8822B BIT(13)
+#define BIT_PCIE_MIO_RE_8822B BIT(12)
+
+#define BIT_SHIFT_PCIE_MIO_WE_8822B 8
+#define BIT_MASK_PCIE_MIO_WE_8822B 0xf
+#define BIT_PCIE_MIO_WE_8822B(x)                                               \
+	(((x) & BIT_MASK_PCIE_MIO_WE_8822B) << BIT_SHIFT_PCIE_MIO_WE_8822B)
+#define BITS_PCIE_MIO_WE_8822B                                                 \
+	(BIT_MASK_PCIE_MIO_WE_8822B << BIT_SHIFT_PCIE_MIO_WE_8822B)
+#define BIT_CLEAR_PCIE_MIO_WE_8822B(x) ((x) & (~BITS_PCIE_MIO_WE_8822B))
+#define BIT_GET_PCIE_MIO_WE_8822B(x)                                           \
+	(((x) >> BIT_SHIFT_PCIE_MIO_WE_8822B) & BIT_MASK_PCIE_MIO_WE_8822B)
+#define BIT_SET_PCIE_MIO_WE_8822B(x, v)                                        \
+	(BIT_CLEAR_PCIE_MIO_WE_8822B(x) | BIT_PCIE_MIO_WE_8822B(v))
+
+#define BIT_SHIFT_PCIE_MIO_ADDR_8822B 0
+#define BIT_MASK_PCIE_MIO_ADDR_8822B 0xff
+#define BIT_PCIE_MIO_ADDR_8822B(x)                                             \
+	(((x) & BIT_MASK_PCIE_MIO_ADDR_8822B) << BIT_SHIFT_PCIE_MIO_ADDR_8822B)
+#define BITS_PCIE_MIO_ADDR_8822B                                               \
+	(BIT_MASK_PCIE_MIO_ADDR_8822B << BIT_SHIFT_PCIE_MIO_ADDR_8822B)
+#define BIT_CLEAR_PCIE_MIO_ADDR_8822B(x) ((x) & (~BITS_PCIE_MIO_ADDR_8822B))
+#define BIT_GET_PCIE_MIO_ADDR_8822B(x)                                         \
+	(((x) >> BIT_SHIFT_PCIE_MIO_ADDR_8822B) & BIT_MASK_PCIE_MIO_ADDR_8822B)
+#define BIT_SET_PCIE_MIO_ADDR_8822B(x, v)                                      \
+	(BIT_CLEAR_PCIE_MIO_ADDR_8822B(x) | BIT_PCIE_MIO_ADDR_8822B(v))
+
+/* 2 REG_PCIE_MIO_INTD_8822B */
+
+#define BIT_SHIFT_PCIE_MIO_DATA_8822B 0
+#define BIT_MASK_PCIE_MIO_DATA_8822B 0xffffffffL
+#define BIT_PCIE_MIO_DATA_8822B(x)                                             \
+	(((x) & BIT_MASK_PCIE_MIO_DATA_8822B) << BIT_SHIFT_PCIE_MIO_DATA_8822B)
+#define BITS_PCIE_MIO_DATA_8822B                                               \
+	(BIT_MASK_PCIE_MIO_DATA_8822B << BIT_SHIFT_PCIE_MIO_DATA_8822B)
+#define BIT_CLEAR_PCIE_MIO_DATA_8822B(x) ((x) & (~BITS_PCIE_MIO_DATA_8822B))
+#define BIT_GET_PCIE_MIO_DATA_8822B(x)                                         \
+	(((x) >> BIT_SHIFT_PCIE_MIO_DATA_8822B) & BIT_MASK_PCIE_MIO_DATA_8822B)
+#define BIT_SET_PCIE_MIO_DATA_8822B(x, v)                                      \
+	(BIT_CLEAR_PCIE_MIO_DATA_8822B(x) | BIT_PCIE_MIO_DATA_8822B(v))
+
+/* 2 REG_WLRF1_8822B */
+
+#define BIT_SHIFT_WLRF1_CTRL_8822B 24
+#define BIT_MASK_WLRF1_CTRL_8822B 0xff
+#define BIT_WLRF1_CTRL_8822B(x)                                                \
+	(((x) & BIT_MASK_WLRF1_CTRL_8822B) << BIT_SHIFT_WLRF1_CTRL_8822B)
+#define BITS_WLRF1_CTRL_8822B                                                  \
+	(BIT_MASK_WLRF1_CTRL_8822B << BIT_SHIFT_WLRF1_CTRL_8822B)
+#define BIT_CLEAR_WLRF1_CTRL_8822B(x) ((x) & (~BITS_WLRF1_CTRL_8822B))
+#define BIT_GET_WLRF1_CTRL_8822B(x)                                            \
+	(((x) >> BIT_SHIFT_WLRF1_CTRL_8822B) & BIT_MASK_WLRF1_CTRL_8822B)
+#define BIT_SET_WLRF1_CTRL_8822B(x, v)                                         \
+	(BIT_CLEAR_WLRF1_CTRL_8822B(x) | BIT_WLRF1_CTRL_8822B(v))
+
+/* 2 REG_SYS_CFG1_8822B */
+
+#define BIT_SHIFT_TRP_ICFG_8822B 28
+#define BIT_MASK_TRP_ICFG_8822B 0xf
+#define BIT_TRP_ICFG_8822B(x)                                                  \
+	(((x) & BIT_MASK_TRP_ICFG_8822B) << BIT_SHIFT_TRP_ICFG_8822B)
+#define BITS_TRP_ICFG_8822B                                                    \
+	(BIT_MASK_TRP_ICFG_8822B << BIT_SHIFT_TRP_ICFG_8822B)
+#define BIT_CLEAR_TRP_ICFG_8822B(x) ((x) & (~BITS_TRP_ICFG_8822B))
+#define BIT_GET_TRP_ICFG_8822B(x)                                              \
+	(((x) >> BIT_SHIFT_TRP_ICFG_8822B) & BIT_MASK_TRP_ICFG_8822B)
+#define BIT_SET_TRP_ICFG_8822B(x, v)                                           \
+	(BIT_CLEAR_TRP_ICFG_8822B(x) | BIT_TRP_ICFG_8822B(v))
+
+#define BIT_RF_TYPE_ID_8822B BIT(27)
+#define BIT_BD_HCI_SEL_8822B BIT(26)
+#define BIT_BD_PKG_SEL_8822B BIT(25)
+#define BIT_SPSLDO_SEL_8822B BIT(24)
+#define BIT_RTL_ID_8822B BIT(23)
+#define BIT_PAD_HWPD_IDN_8822B BIT(22)
+#define BIT_TESTMODE_8822B BIT(20)
+
+#define BIT_SHIFT_VENDOR_ID_8822B 16
+#define BIT_MASK_VENDOR_ID_8822B 0xf
+#define BIT_VENDOR_ID_8822B(x)                                                 \
+	(((x) & BIT_MASK_VENDOR_ID_8822B) << BIT_SHIFT_VENDOR_ID_8822B)
+#define BITS_VENDOR_ID_8822B                                                   \
+	(BIT_MASK_VENDOR_ID_8822B << BIT_SHIFT_VENDOR_ID_8822B)
+#define BIT_CLEAR_VENDOR_ID_8822B(x) ((x) & (~BITS_VENDOR_ID_8822B))
+#define BIT_GET_VENDOR_ID_8822B(x)                                             \
+	(((x) >> BIT_SHIFT_VENDOR_ID_8822B) & BIT_MASK_VENDOR_ID_8822B)
+#define BIT_SET_VENDOR_ID_8822B(x, v)                                          \
+	(BIT_CLEAR_VENDOR_ID_8822B(x) | BIT_VENDOR_ID_8822B(v))
+
+#define BIT_SHIFT_CHIP_VER_8822B 12
+#define BIT_MASK_CHIP_VER_8822B 0xf
+#define BIT_CHIP_VER_8822B(x)                                                  \
+	(((x) & BIT_MASK_CHIP_VER_8822B) << BIT_SHIFT_CHIP_VER_8822B)
+#define BITS_CHIP_VER_8822B                                                    \
+	(BIT_MASK_CHIP_VER_8822B << BIT_SHIFT_CHIP_VER_8822B)
+#define BIT_CLEAR_CHIP_VER_8822B(x) ((x) & (~BITS_CHIP_VER_8822B))
+#define BIT_GET_CHIP_VER_8822B(x)                                              \
+	(((x) >> BIT_SHIFT_CHIP_VER_8822B) & BIT_MASK_CHIP_VER_8822B)
+#define BIT_SET_CHIP_VER_8822B(x, v)                                           \
+	(BIT_CLEAR_CHIP_VER_8822B(x) | BIT_CHIP_VER_8822B(v))
+
+#define BIT_BD_MAC3_8822B BIT(11)
+#define BIT_BD_MAC1_8822B BIT(10)
+#define BIT_BD_MAC2_8822B BIT(9)
+#define BIT_SIC_IDLE_8822B BIT(8)
+#define BIT_SW_OFFLOAD_EN_8822B BIT(7)
+#define BIT_OCP_SHUTDN_8822B BIT(6)
+#define BIT_V15_VLD_8822B BIT(5)
+#define BIT_PCIRSTB_8822B BIT(4)
+#define BIT_PCLK_VLD_8822B BIT(3)
+#define BIT_UCLK_VLD_8822B BIT(2)
+#define BIT_ACLK_VLD_8822B BIT(1)
+#define BIT_XCLK_VLD_8822B BIT(0)
+
+/* 2 REG_SYS_STATUS1_8822B */
+
+#define BIT_SHIFT_RF_RL_ID_8822B 28
+#define BIT_MASK_RF_RL_ID_8822B 0xf
+#define BIT_RF_RL_ID_8822B(x)                                                  \
+	(((x) & BIT_MASK_RF_RL_ID_8822B) << BIT_SHIFT_RF_RL_ID_8822B)
+#define BITS_RF_RL_ID_8822B                                                    \
+	(BIT_MASK_RF_RL_ID_8822B << BIT_SHIFT_RF_RL_ID_8822B)
+#define BIT_CLEAR_RF_RL_ID_8822B(x) ((x) & (~BITS_RF_RL_ID_8822B))
+#define BIT_GET_RF_RL_ID_8822B(x)                                              \
+	(((x) >> BIT_SHIFT_RF_RL_ID_8822B) & BIT_MASK_RF_RL_ID_8822B)
+#define BIT_SET_RF_RL_ID_8822B(x, v)                                           \
+	(BIT_CLEAR_RF_RL_ID_8822B(x) | BIT_RF_RL_ID_8822B(v))
+
+#define BIT_HPHY_ICFG_8822B BIT(19)
+
+#define BIT_SHIFT_SEL_0XC0_8822B 16
+#define BIT_MASK_SEL_0XC0_8822B 0x3
+#define BIT_SEL_0XC0_8822B(x)                                                  \
+	(((x) & BIT_MASK_SEL_0XC0_8822B) << BIT_SHIFT_SEL_0XC0_8822B)
+#define BITS_SEL_0XC0_8822B                                                    \
+	(BIT_MASK_SEL_0XC0_8822B << BIT_SHIFT_SEL_0XC0_8822B)
+#define BIT_CLEAR_SEL_0XC0_8822B(x) ((x) & (~BITS_SEL_0XC0_8822B))
+#define BIT_GET_SEL_0XC0_8822B(x)                                              \
+	(((x) >> BIT_SHIFT_SEL_0XC0_8822B) & BIT_MASK_SEL_0XC0_8822B)
+#define BIT_SET_SEL_0XC0_8822B(x, v)                                           \
+	(BIT_CLEAR_SEL_0XC0_8822B(x) | BIT_SEL_0XC0_8822B(v))
+
+#define BIT_SHIFT_HCI_SEL_V3_8822B 12
+#define BIT_MASK_HCI_SEL_V3_8822B 0x7
+#define BIT_HCI_SEL_V3_8822B(x)                                                \
+	(((x) & BIT_MASK_HCI_SEL_V3_8822B) << BIT_SHIFT_HCI_SEL_V3_8822B)
+#define BITS_HCI_SEL_V3_8822B                                                  \
+	(BIT_MASK_HCI_SEL_V3_8822B << BIT_SHIFT_HCI_SEL_V3_8822B)
+#define BIT_CLEAR_HCI_SEL_V3_8822B(x) ((x) & (~BITS_HCI_SEL_V3_8822B))
+#define BIT_GET_HCI_SEL_V3_8822B(x)                                            \
+	(((x) >> BIT_SHIFT_HCI_SEL_V3_8822B) & BIT_MASK_HCI_SEL_V3_8822B)
+#define BIT_SET_HCI_SEL_V3_8822B(x, v)                                         \
+	(BIT_CLEAR_HCI_SEL_V3_8822B(x) | BIT_HCI_SEL_V3_8822B(v))
+
+#define BIT_USB_OPERATION_MODE_8822B BIT(10)
+#define BIT_BT_PDN_8822B BIT(9)
+#define BIT_AUTO_WLPON_8822B BIT(8)
+#define BIT_WL_MODE_8822B BIT(7)
+#define BIT_PKG_SEL_HCI_8822B BIT(6)
+
+#define BIT_SHIFT_PAD_HCI_SEL_V1_8822B 3
+#define BIT_MASK_PAD_HCI_SEL_V1_8822B 0x7
+#define BIT_PAD_HCI_SEL_V1_8822B(x)                                            \
+	(((x) & BIT_MASK_PAD_HCI_SEL_V1_8822B)                                 \
+	 << BIT_SHIFT_PAD_HCI_SEL_V1_8822B)
+#define BITS_PAD_HCI_SEL_V1_8822B                                              \
+	(BIT_MASK_PAD_HCI_SEL_V1_8822B << BIT_SHIFT_PAD_HCI_SEL_V1_8822B)
+#define BIT_CLEAR_PAD_HCI_SEL_V1_8822B(x) ((x) & (~BITS_PAD_HCI_SEL_V1_8822B))
+#define BIT_GET_PAD_HCI_SEL_V1_8822B(x)                                        \
+	(((x) >> BIT_SHIFT_PAD_HCI_SEL_V1_8822B) &                             \
+	 BIT_MASK_PAD_HCI_SEL_V1_8822B)
+#define BIT_SET_PAD_HCI_SEL_V1_8822B(x, v)                                     \
+	(BIT_CLEAR_PAD_HCI_SEL_V1_8822B(x) | BIT_PAD_HCI_SEL_V1_8822B(v))
+
+#define BIT_SHIFT_EFS_HCI_SEL_V1_8822B 0
+#define BIT_MASK_EFS_HCI_SEL_V1_8822B 0x7
+#define BIT_EFS_HCI_SEL_V1_8822B(x)                                            \
+	(((x) & BIT_MASK_EFS_HCI_SEL_V1_8822B)                                 \
+	 << BIT_SHIFT_EFS_HCI_SEL_V1_8822B)
+#define BITS_EFS_HCI_SEL_V1_8822B                                              \
+	(BIT_MASK_EFS_HCI_SEL_V1_8822B << BIT_SHIFT_EFS_HCI_SEL_V1_8822B)
+#define BIT_CLEAR_EFS_HCI_SEL_V1_8822B(x) ((x) & (~BITS_EFS_HCI_SEL_V1_8822B))
+#define BIT_GET_EFS_HCI_SEL_V1_8822B(x)                                        \
+	(((x) >> BIT_SHIFT_EFS_HCI_SEL_V1_8822B) &                             \
+	 BIT_MASK_EFS_HCI_SEL_V1_8822B)
+#define BIT_SET_EFS_HCI_SEL_V1_8822B(x, v)                                     \
+	(BIT_CLEAR_EFS_HCI_SEL_V1_8822B(x) | BIT_EFS_HCI_SEL_V1_8822B(v))
+
+/* 2 REG_SYS_STATUS2_8822B */
+#define BIT_SIO_ALDN_8822B BIT(19)
+#define BIT_USB_ALDN_8822B BIT(18)
+#define BIT_PCI_ALDN_8822B BIT(17)
+#define BIT_SYS_ALDN_8822B BIT(16)
+
+#define BIT_SHIFT_EPVID1_8822B 8
+#define BIT_MASK_EPVID1_8822B 0xff
+#define BIT_EPVID1_8822B(x)                                                    \
+	(((x) & BIT_MASK_EPVID1_8822B) << BIT_SHIFT_EPVID1_8822B)
+#define BITS_EPVID1_8822B (BIT_MASK_EPVID1_8822B << BIT_SHIFT_EPVID1_8822B)
+#define BIT_CLEAR_EPVID1_8822B(x) ((x) & (~BITS_EPVID1_8822B))
+#define BIT_GET_EPVID1_8822B(x)                                                \
+	(((x) >> BIT_SHIFT_EPVID1_8822B) & BIT_MASK_EPVID1_8822B)
+#define BIT_SET_EPVID1_8822B(x, v)                                             \
+	(BIT_CLEAR_EPVID1_8822B(x) | BIT_EPVID1_8822B(v))
+
+#define BIT_SHIFT_EPVID0_8822B 0
+#define BIT_MASK_EPVID0_8822B 0xff
+#define BIT_EPVID0_8822B(x)                                                    \
+	(((x) & BIT_MASK_EPVID0_8822B) << BIT_SHIFT_EPVID0_8822B)
+#define BITS_EPVID0_8822B (BIT_MASK_EPVID0_8822B << BIT_SHIFT_EPVID0_8822B)
+#define BIT_CLEAR_EPVID0_8822B(x) ((x) & (~BITS_EPVID0_8822B))
+#define BIT_GET_EPVID0_8822B(x)                                                \
+	(((x) >> BIT_SHIFT_EPVID0_8822B) & BIT_MASK_EPVID0_8822B)
+#define BIT_SET_EPVID0_8822B(x, v)                                             \
+	(BIT_CLEAR_EPVID0_8822B(x) | BIT_EPVID0_8822B(v))
+
+/* 2 REG_SYS_CFG2_8822B */
+#define BIT_HCI_SEL_EMBEDDED_8822B BIT(8)
+
+#define BIT_SHIFT_HW_ID_8822B 0
+#define BIT_MASK_HW_ID_8822B 0xff
+#define BIT_HW_ID_8822B(x)                                                     \
+	(((x) & BIT_MASK_HW_ID_8822B) << BIT_SHIFT_HW_ID_8822B)
+#define BITS_HW_ID_8822B (BIT_MASK_HW_ID_8822B << BIT_SHIFT_HW_ID_8822B)
+#define BIT_CLEAR_HW_ID_8822B(x) ((x) & (~BITS_HW_ID_8822B))
+#define BIT_GET_HW_ID_8822B(x)                                                 \
+	(((x) >> BIT_SHIFT_HW_ID_8822B) & BIT_MASK_HW_ID_8822B)
+#define BIT_SET_HW_ID_8822B(x, v)                                              \
+	(BIT_CLEAR_HW_ID_8822B(x) | BIT_HW_ID_8822B(v))
+
+/* 2 REG_SYS_CFG3_8822B */
+#define BIT_PWC_MA33V_8822B BIT(15)
+#define BIT_PWC_MA12V_8822B BIT(14)
+#define BIT_PWC_MD12V_8822B BIT(13)
+#define BIT_PWC_PD12V_8822B BIT(12)
+#define BIT_PWC_UD12V_8822B BIT(11)
+#define BIT_ISO_MA2MD_8822B BIT(1)
+#define BIT_ISO_MD2PP_8822B BIT(0)
+
+/* 2 REG_SYS_CFG4_8822B */
+
+/* 2 REG_SYS_CFG5_8822B */
+#define BIT_LPS_STATUS_8822B BIT(3)
+#define BIT_HCI_TXDMA_BUSY_8822B BIT(2)
+#define BIT_HCI_TXDMA_ALLOW_8822B BIT(1)
+#define BIT_FW_CTRL_HCI_TXDMA_EN_8822B BIT(0)
+
+/* 2 REG_CPU_DMEM_CON_8822B */
+#define BIT_WDT_OPT_IOWRAPPER_8822B BIT(19)
+#define BIT_ANA_PORT_IDLE_8822B BIT(18)
+#define BIT_MAC_PORT_IDLE_8822B BIT(17)
+#define BIT_WL_PLATFORM_RST_8822B BIT(16)
+#define BIT_WL_SECURITY_CLK_8822B BIT(15)
+
+#define BIT_SHIFT_CPU_DMEM_CON_8822B 0
+#define BIT_MASK_CPU_DMEM_CON_8822B 0xff
+#define BIT_CPU_DMEM_CON_8822B(x)                                              \
+	(((x) & BIT_MASK_CPU_DMEM_CON_8822B) << BIT_SHIFT_CPU_DMEM_CON_8822B)
+#define BITS_CPU_DMEM_CON_8822B                                                \
+	(BIT_MASK_CPU_DMEM_CON_8822B << BIT_SHIFT_CPU_DMEM_CON_8822B)
+#define BIT_CLEAR_CPU_DMEM_CON_8822B(x) ((x) & (~BITS_CPU_DMEM_CON_8822B))
+#define BIT_GET_CPU_DMEM_CON_8822B(x)                                          \
+	(((x) >> BIT_SHIFT_CPU_DMEM_CON_8822B) & BIT_MASK_CPU_DMEM_CON_8822B)
+#define BIT_SET_CPU_DMEM_CON_8822B(x, v)                                       \
+	(BIT_CLEAR_CPU_DMEM_CON_8822B(x) | BIT_CPU_DMEM_CON_8822B(v))
+
+/* 2 REG_BOOT_REASON_8822B */
+
+#define BIT_SHIFT_BOOT_REASON_V1_8822B 0
+#define BIT_MASK_BOOT_REASON_V1_8822B 0x7
+#define BIT_BOOT_REASON_V1_8822B(x)                                            \
+	(((x) & BIT_MASK_BOOT_REASON_V1_8822B)                                 \
+	 << BIT_SHIFT_BOOT_REASON_V1_8822B)
+#define BITS_BOOT_REASON_V1_8822B                                              \
+	(BIT_MASK_BOOT_REASON_V1_8822B << BIT_SHIFT_BOOT_REASON_V1_8822B)
+#define BIT_CLEAR_BOOT_REASON_V1_8822B(x) ((x) & (~BITS_BOOT_REASON_V1_8822B))
+#define BIT_GET_BOOT_REASON_V1_8822B(x)                                        \
+	(((x) >> BIT_SHIFT_BOOT_REASON_V1_8822B) &                             \
+	 BIT_MASK_BOOT_REASON_V1_8822B)
+#define BIT_SET_BOOT_REASON_V1_8822B(x, v)                                     \
+	(BIT_CLEAR_BOOT_REASON_V1_8822B(x) | BIT_BOOT_REASON_V1_8822B(v))
+
+/* 2 REG_NFCPAD_CTRL_8822B */
+#define BIT_PAD_SHUTDW_8822B BIT(18)
+#define BIT_SYSON_NFC_PAD_8822B BIT(17)
+#define BIT_NFC_INT_PAD_CTRL_8822B BIT(16)
+#define BIT_NFC_RFDIS_PAD_CTRL_8822B BIT(15)
+#define BIT_NFC_CLK_PAD_CTRL_8822B BIT(14)
+#define BIT_NFC_DATA_PAD_CTRL_8822B BIT(13)
+#define BIT_NFC_PAD_PULL_CTRL_8822B BIT(12)
+
+#define BIT_SHIFT_NFCPAD_IO_SEL_8822B 8
+#define BIT_MASK_NFCPAD_IO_SEL_8822B 0xf
+#define BIT_NFCPAD_IO_SEL_8822B(x)                                             \
+	(((x) & BIT_MASK_NFCPAD_IO_SEL_8822B) << BIT_SHIFT_NFCPAD_IO_SEL_8822B)
+#define BITS_NFCPAD_IO_SEL_8822B                                               \
+	(BIT_MASK_NFCPAD_IO_SEL_8822B << BIT_SHIFT_NFCPAD_IO_SEL_8822B)
+#define BIT_CLEAR_NFCPAD_IO_SEL_8822B(x) ((x) & (~BITS_NFCPAD_IO_SEL_8822B))
+#define BIT_GET_NFCPAD_IO_SEL_8822B(x)                                         \
+	(((x) >> BIT_SHIFT_NFCPAD_IO_SEL_8822B) & BIT_MASK_NFCPAD_IO_SEL_8822B)
+#define BIT_SET_NFCPAD_IO_SEL_8822B(x, v)                                      \
+	(BIT_CLEAR_NFCPAD_IO_SEL_8822B(x) | BIT_NFCPAD_IO_SEL_8822B(v))
+
+#define BIT_SHIFT_NFCPAD_OUT_8822B 4
+#define BIT_MASK_NFCPAD_OUT_8822B 0xf
+#define BIT_NFCPAD_OUT_8822B(x)                                                \
+	(((x) & BIT_MASK_NFCPAD_OUT_8822B) << BIT_SHIFT_NFCPAD_OUT_8822B)
+#define BITS_NFCPAD_OUT_8822B                                                  \
+	(BIT_MASK_NFCPAD_OUT_8822B << BIT_SHIFT_NFCPAD_OUT_8822B)
+#define BIT_CLEAR_NFCPAD_OUT_8822B(x) ((x) & (~BITS_NFCPAD_OUT_8822B))
+#define BIT_GET_NFCPAD_OUT_8822B(x)                                            \
+	(((x) >> BIT_SHIFT_NFCPAD_OUT_8822B) & BIT_MASK_NFCPAD_OUT_8822B)
+#define BIT_SET_NFCPAD_OUT_8822B(x, v)                                         \
+	(BIT_CLEAR_NFCPAD_OUT_8822B(x) | BIT_NFCPAD_OUT_8822B(v))
+
+#define BIT_SHIFT_NFCPAD_IN_8822B 0
+#define BIT_MASK_NFCPAD_IN_8822B 0xf
+#define BIT_NFCPAD_IN_8822B(x)                                                 \
+	(((x) & BIT_MASK_NFCPAD_IN_8822B) << BIT_SHIFT_NFCPAD_IN_8822B)
+#define BITS_NFCPAD_IN_8822B                                                   \
+	(BIT_MASK_NFCPAD_IN_8822B << BIT_SHIFT_NFCPAD_IN_8822B)
+#define BIT_CLEAR_NFCPAD_IN_8822B(x) ((x) & (~BITS_NFCPAD_IN_8822B))
+#define BIT_GET_NFCPAD_IN_8822B(x)                                             \
+	(((x) >> BIT_SHIFT_NFCPAD_IN_8822B) & BIT_MASK_NFCPAD_IN_8822B)
+#define BIT_SET_NFCPAD_IN_8822B(x, v)                                          \
+	(BIT_CLEAR_NFCPAD_IN_8822B(x) | BIT_NFCPAD_IN_8822B(v))
+
+/* 2 REG_HIMR2_8822B */
+#define BIT_BCNDMAINT_P4_MSK_8822B BIT(31)
+#define BIT_BCNDMAINT_P3_MSK_8822B BIT(30)
+#define BIT_BCNDMAINT_P2_MSK_8822B BIT(29)
+#define BIT_BCNDMAINT_P1_MSK_8822B BIT(28)
+#define BIT_ATIMEND7_MSK_8822B BIT(22)
+#define BIT_ATIMEND6_MSK_8822B BIT(21)
+#define BIT_ATIMEND5_MSK_8822B BIT(20)
+#define BIT_ATIMEND4_MSK_8822B BIT(19)
+#define BIT_ATIMEND3_MSK_8822B BIT(18)
+#define BIT_ATIMEND2_MSK_8822B BIT(17)
+#define BIT_ATIMEND1_MSK_8822B BIT(16)
+#define BIT_TXBCN7OK_MSK_8822B BIT(14)
+#define BIT_TXBCN6OK_MSK_8822B BIT(13)
+#define BIT_TXBCN5OK_MSK_8822B BIT(12)
+#define BIT_TXBCN4OK_MSK_8822B BIT(11)
+#define BIT_TXBCN3OK_MSK_8822B BIT(10)
+#define BIT_TXBCN2OK_MSK_8822B BIT(9)
+#define BIT_TXBCN1OK_MSK_V1_8822B BIT(8)
+#define BIT_TXBCN7ERR_MSK_8822B BIT(6)
+#define BIT_TXBCN6ERR_MSK_8822B BIT(5)
+#define BIT_TXBCN5ERR_MSK_8822B BIT(4)
+#define BIT_TXBCN4ERR_MSK_8822B BIT(3)
+#define BIT_TXBCN3ERR_MSK_8822B BIT(2)
+#define BIT_TXBCN2ERR_MSK_8822B BIT(1)
+#define BIT_TXBCN1ERR_MSK_V1_8822B BIT(0)
+
+/* 2 REG_HISR2_8822B */
+#define BIT_BCNDMAINT_P4_8822B BIT(31)
+#define BIT_BCNDMAINT_P3_8822B BIT(30)
+#define BIT_BCNDMAINT_P2_8822B BIT(29)
+#define BIT_BCNDMAINT_P1_8822B BIT(28)
+#define BIT_ATIMEND7_8822B BIT(22)
+#define BIT_ATIMEND6_8822B BIT(21)
+#define BIT_ATIMEND5_8822B BIT(20)
+#define BIT_ATIMEND4_8822B BIT(19)
+#define BIT_ATIMEND3_8822B BIT(18)
+#define BIT_ATIMEND2_8822B BIT(17)
+#define BIT_ATIMEND1_8822B BIT(16)
+#define BIT_TXBCN7OK_8822B BIT(14)
+#define BIT_TXBCN6OK_8822B BIT(13)
+#define BIT_TXBCN5OK_8822B BIT(12)
+#define BIT_TXBCN4OK_8822B BIT(11)
+#define BIT_TXBCN3OK_8822B BIT(10)
+#define BIT_TXBCN2OK_8822B BIT(9)
+#define BIT_TXBCN1OK_8822B BIT(8)
+#define BIT_TXBCN7ERR_8822B BIT(6)
+#define BIT_TXBCN6ERR_8822B BIT(5)
+#define BIT_TXBCN5ERR_8822B BIT(4)
+#define BIT_TXBCN4ERR_8822B BIT(3)
+#define BIT_TXBCN3ERR_8822B BIT(2)
+#define BIT_TXBCN2ERR_8822B BIT(1)
+#define BIT_TXBCN1ERR_8822B BIT(0)
+
+/* 2 REG_HIMR3_8822B */
+#define BIT_WDT_PLATFORM_INT_MSK_8822B BIT(18)
+#define BIT_WDT_CPU_INT_MSK_8822B BIT(17)
+#define BIT_SETH2CDOK_MASK_8822B BIT(16)
+#define BIT_H2C_CMD_FULL_MASK_8822B BIT(15)
+#define BIT_PWR_INT_127_MASK_8822B BIT(14)
+#define BIT_TXSHORTCUT_TXDESUPDATEOK_MASK_8822B BIT(13)
+#define BIT_TXSHORTCUT_BKUPDATEOK_MASK_8822B BIT(12)
+#define BIT_TXSHORTCUT_BEUPDATEOK_MASK_8822B BIT(11)
+#define BIT_TXSHORTCUT_VIUPDATEOK_MAS_8822B BIT(10)
+#define BIT_TXSHORTCUT_VOUPDATEOK_MASK_8822B BIT(9)
+#define BIT_PWR_INT_127_MASK_V1_8822B BIT(8)
+#define BIT_PWR_INT_126TO96_MASK_8822B BIT(7)
+#define BIT_PWR_INT_95TO64_MASK_8822B BIT(6)
+#define BIT_PWR_INT_63TO32_MASK_8822B BIT(5)
+#define BIT_PWR_INT_31TO0_MASK_8822B BIT(4)
+#define BIT_DDMA0_LP_INT_MSK_8822B BIT(1)
+#define BIT_DDMA0_HP_INT_MSK_8822B BIT(0)
+
+/* 2 REG_HISR3_8822B */
+#define BIT_WDT_PLATFORM_INT_8822B BIT(18)
+#define BIT_WDT_CPU_INT_8822B BIT(17)
+#define BIT_SETH2CDOK_8822B BIT(16)
+#define BIT_H2C_CMD_FULL_8822B BIT(15)
+#define BIT_PWR_INT_127_8822B BIT(14)
+#define BIT_TXSHORTCUT_TXDESUPDATEOK_8822B BIT(13)
+#define BIT_TXSHORTCUT_BKUPDATEOK_8822B BIT(12)
+#define BIT_TXSHORTCUT_BEUPDATEOK_8822B BIT(11)
+#define BIT_TXSHORTCUT_VIUPDATEOK_8822B BIT(10)
+#define BIT_TXSHORTCUT_VOUPDATEOK_8822B BIT(9)
+#define BIT_PWR_INT_127_V1_8822B BIT(8)
+#define BIT_PWR_INT_126TO96_8822B BIT(7)
+#define BIT_PWR_INT_95TO64_8822B BIT(6)
+#define BIT_PWR_INT_63TO32_8822B BIT(5)
+#define BIT_PWR_INT_31TO0_8822B BIT(4)
+#define BIT_DDMA0_LP_INT_8822B BIT(1)
+#define BIT_DDMA0_HP_INT_8822B BIT(0)
+
+/* 2 REG_SW_MDIO_8822B */
+#define BIT_DIS_TIMEOUT_IO_8822B BIT(24)
+
+/* 2 REG_SW_FLUSH_8822B */
+#define BIT_FLUSH_HOLDN_EN_8822B BIT(25)
+#define BIT_FLUSH_WR_EN_8822B BIT(24)
+#define BIT_SW_FLASH_CONTROL_8822B BIT(23)
+#define BIT_SW_FLASH_WEN_E_8822B BIT(19)
+#define BIT_SW_FLASH_HOLDN_E_8822B BIT(18)
+#define BIT_SW_FLASH_SO_E_8822B BIT(17)
+#define BIT_SW_FLASH_SI_E_8822B BIT(16)
+#define BIT_SW_FLASH_SK_O_8822B BIT(13)
+#define BIT_SW_FLASH_CEN_O_8822B BIT(12)
+#define BIT_SW_FLASH_WEN_O_8822B BIT(11)
+#define BIT_SW_FLASH_HOLDN_O_8822B BIT(10)
+#define BIT_SW_FLASH_SO_O_8822B BIT(9)
+#define BIT_SW_FLASH_SI_O_8822B BIT(8)
+#define BIT_SW_FLASH_WEN_I_8822B BIT(3)
+#define BIT_SW_FLASH_HOLDN_I_8822B BIT(2)
+#define BIT_SW_FLASH_SO_I_8822B BIT(1)
+#define BIT_SW_FLASH_SI_I_8822B BIT(0)
+
+/* 2 REG_H2C_PKT_READADDR_8822B */
+
+#define BIT_SHIFT_H2C_PKT_READADDR_8822B 0
+#define BIT_MASK_H2C_PKT_READADDR_8822B 0x3ffff
+#define BIT_H2C_PKT_READADDR_8822B(x)                                          \
+	(((x) & BIT_MASK_H2C_PKT_READADDR_8822B)                               \
+	 << BIT_SHIFT_H2C_PKT_READADDR_8822B)
+#define BITS_H2C_PKT_READADDR_8822B                                            \
+	(BIT_MASK_H2C_PKT_READADDR_8822B << BIT_SHIFT_H2C_PKT_READADDR_8822B)
+#define BIT_CLEAR_H2C_PKT_READADDR_8822B(x)                                    \
+	((x) & (~BITS_H2C_PKT_READADDR_8822B))
+#define BIT_GET_H2C_PKT_READADDR_8822B(x)                                      \
+	(((x) >> BIT_SHIFT_H2C_PKT_READADDR_8822B) &                           \
+	 BIT_MASK_H2C_PKT_READADDR_8822B)
+#define BIT_SET_H2C_PKT_READADDR_8822B(x, v)                                   \
+	(BIT_CLEAR_H2C_PKT_READADDR_8822B(x) | BIT_H2C_PKT_READADDR_8822B(v))
+
+/* 2 REG_H2C_PKT_WRITEADDR_8822B */
+
+#define BIT_SHIFT_H2C_PKT_WRITEADDR_8822B 0
+#define BIT_MASK_H2C_PKT_WRITEADDR_8822B 0x3ffff
+#define BIT_H2C_PKT_WRITEADDR_8822B(x)                                         \
+	(((x) & BIT_MASK_H2C_PKT_WRITEADDR_8822B)                              \
+	 << BIT_SHIFT_H2C_PKT_WRITEADDR_8822B)
+#define BITS_H2C_PKT_WRITEADDR_8822B                                           \
+	(BIT_MASK_H2C_PKT_WRITEADDR_8822B << BIT_SHIFT_H2C_PKT_WRITEADDR_8822B)
+#define BIT_CLEAR_H2C_PKT_WRITEADDR_8822B(x)                                   \
+	((x) & (~BITS_H2C_PKT_WRITEADDR_8822B))
+#define BIT_GET_H2C_PKT_WRITEADDR_8822B(x)                                     \
+	(((x) >> BIT_SHIFT_H2C_PKT_WRITEADDR_8822B) &                          \
+	 BIT_MASK_H2C_PKT_WRITEADDR_8822B)
+#define BIT_SET_H2C_PKT_WRITEADDR_8822B(x, v)                                  \
+	(BIT_CLEAR_H2C_PKT_WRITEADDR_8822B(x) | BIT_H2C_PKT_WRITEADDR_8822B(v))
+
+/* 2 REG_MEM_PWR_CRTL_8822B */
+#define BIT_MEM_BB_SD_8822B BIT(17)
+#define BIT_MEM_BB_DS_8822B BIT(16)
+#define BIT_MEM_BT_DS_8822B BIT(10)
+#define BIT_MEM_SDIO_LS_8822B BIT(9)
+#define BIT_MEM_SDIO_DS_8822B BIT(8)
+#define BIT_MEM_USB_LS_8822B BIT(7)
+#define BIT_MEM_USB_DS_8822B BIT(6)
+#define BIT_MEM_PCI_LS_8822B BIT(5)
+#define BIT_MEM_PCI_DS_8822B BIT(4)
+#define BIT_MEM_WLMAC_LS_8822B BIT(3)
+#define BIT_MEM_WLMAC_DS_8822B BIT(2)
+#define BIT_MEM_WLMCU_LS_8822B BIT(1)
+#define BIT_MEM_WLMCU_DS_8822B BIT(0)
+
+/* 2 REG_FW_DBG0_8822B */
+
+#define BIT_SHIFT_FW_DBG0_8822B 0
+#define BIT_MASK_FW_DBG0_8822B 0xffffffffL
+#define BIT_FW_DBG0_8822B(x)                                                   \
+	(((x) & BIT_MASK_FW_DBG0_8822B) << BIT_SHIFT_FW_DBG0_8822B)
+#define BITS_FW_DBG0_8822B (BIT_MASK_FW_DBG0_8822B << BIT_SHIFT_FW_DBG0_8822B)
+#define BIT_CLEAR_FW_DBG0_8822B(x) ((x) & (~BITS_FW_DBG0_8822B))
+#define BIT_GET_FW_DBG0_8822B(x)                                               \
+	(((x) >> BIT_SHIFT_FW_DBG0_8822B) & BIT_MASK_FW_DBG0_8822B)
+#define BIT_SET_FW_DBG0_8822B(x, v)                                            \
+	(BIT_CLEAR_FW_DBG0_8822B(x) | BIT_FW_DBG0_8822B(v))
+
+/* 2 REG_FW_DBG1_8822B */
+
+#define BIT_SHIFT_FW_DBG1_8822B 0
+#define BIT_MASK_FW_DBG1_8822B 0xffffffffL
+#define BIT_FW_DBG1_8822B(x)                                                   \
+	(((x) & BIT_MASK_FW_DBG1_8822B) << BIT_SHIFT_FW_DBG1_8822B)
+#define BITS_FW_DBG1_8822B (BIT_MASK_FW_DBG1_8822B << BIT_SHIFT_FW_DBG1_8822B)
+#define BIT_CLEAR_FW_DBG1_8822B(x) ((x) & (~BITS_FW_DBG1_8822B))
+#define BIT_GET_FW_DBG1_8822B(x)                                               \
+	(((x) >> BIT_SHIFT_FW_DBG1_8822B) & BIT_MASK_FW_DBG1_8822B)
+#define BIT_SET_FW_DBG1_8822B(x, v)                                            \
+	(BIT_CLEAR_FW_DBG1_8822B(x) | BIT_FW_DBG1_8822B(v))
+
+/* 2 REG_FW_DBG2_8822B */
+
+#define BIT_SHIFT_FW_DBG2_8822B 0
+#define BIT_MASK_FW_DBG2_8822B 0xffffffffL
+#define BIT_FW_DBG2_8822B(x)                                                   \
+	(((x) & BIT_MASK_FW_DBG2_8822B) << BIT_SHIFT_FW_DBG2_8822B)
+#define BITS_FW_DBG2_8822B (BIT_MASK_FW_DBG2_8822B << BIT_SHIFT_FW_DBG2_8822B)
+#define BIT_CLEAR_FW_DBG2_8822B(x) ((x) & (~BITS_FW_DBG2_8822B))
+#define BIT_GET_FW_DBG2_8822B(x)                                               \
+	(((x) >> BIT_SHIFT_FW_DBG2_8822B) & BIT_MASK_FW_DBG2_8822B)
+#define BIT_SET_FW_DBG2_8822B(x, v)                                            \
+	(BIT_CLEAR_FW_DBG2_8822B(x) | BIT_FW_DBG2_8822B(v))
+
+/* 2 REG_FW_DBG3_8822B */
+
+#define BIT_SHIFT_FW_DBG3_8822B 0
+#define BIT_MASK_FW_DBG3_8822B 0xffffffffL
+#define BIT_FW_DBG3_8822B(x)                                                   \
+	(((x) & BIT_MASK_FW_DBG3_8822B) << BIT_SHIFT_FW_DBG3_8822B)
+#define BITS_FW_DBG3_8822B (BIT_MASK_FW_DBG3_8822B << BIT_SHIFT_FW_DBG3_8822B)
+#define BIT_CLEAR_FW_DBG3_8822B(x) ((x) & (~BITS_FW_DBG3_8822B))
+#define BIT_GET_FW_DBG3_8822B(x)                                               \
+	(((x) >> BIT_SHIFT_FW_DBG3_8822B) & BIT_MASK_FW_DBG3_8822B)
+#define BIT_SET_FW_DBG3_8822B(x, v)                                            \
+	(BIT_CLEAR_FW_DBG3_8822B(x) | BIT_FW_DBG3_8822B(v))
+
+/* 2 REG_FW_DBG4_8822B */
+
+#define BIT_SHIFT_FW_DBG4_8822B 0
+#define BIT_MASK_FW_DBG4_8822B 0xffffffffL
+#define BIT_FW_DBG4_8822B(x)                                                   \
+	(((x) & BIT_MASK_FW_DBG4_8822B) << BIT_SHIFT_FW_DBG4_8822B)
+#define BITS_FW_DBG4_8822B (BIT_MASK_FW_DBG4_8822B << BIT_SHIFT_FW_DBG4_8822B)
+#define BIT_CLEAR_FW_DBG4_8822B(x) ((x) & (~BITS_FW_DBG4_8822B))
+#define BIT_GET_FW_DBG4_8822B(x)                                               \
+	(((x) >> BIT_SHIFT_FW_DBG4_8822B) & BIT_MASK_FW_DBG4_8822B)
+#define BIT_SET_FW_DBG4_8822B(x, v)                                            \
+	(BIT_CLEAR_FW_DBG4_8822B(x) | BIT_FW_DBG4_8822B(v))
+
+/* 2 REG_FW_DBG5_8822B */
+
+#define BIT_SHIFT_FW_DBG5_8822B 0
+#define BIT_MASK_FW_DBG5_8822B 0xffffffffL
+#define BIT_FW_DBG5_8822B(x)                                                   \
+	(((x) & BIT_MASK_FW_DBG5_8822B) << BIT_SHIFT_FW_DBG5_8822B)
+#define BITS_FW_DBG5_8822B (BIT_MASK_FW_DBG5_8822B << BIT_SHIFT_FW_DBG5_8822B)
+#define BIT_CLEAR_FW_DBG5_8822B(x) ((x) & (~BITS_FW_DBG5_8822B))
+#define BIT_GET_FW_DBG5_8822B(x)                                               \
+	(((x) >> BIT_SHIFT_FW_DBG5_8822B) & BIT_MASK_FW_DBG5_8822B)
+#define BIT_SET_FW_DBG5_8822B(x, v)                                            \
+	(BIT_CLEAR_FW_DBG5_8822B(x) | BIT_FW_DBG5_8822B(v))
+
+/* 2 REG_FW_DBG6_8822B */
+
+#define BIT_SHIFT_FW_DBG6_8822B 0
+#define BIT_MASK_FW_DBG6_8822B 0xffffffffL
+#define BIT_FW_DBG6_8822B(x)                                                   \
+	(((x) & BIT_MASK_FW_DBG6_8822B) << BIT_SHIFT_FW_DBG6_8822B)
+#define BITS_FW_DBG6_8822B (BIT_MASK_FW_DBG6_8822B << BIT_SHIFT_FW_DBG6_8822B)
+#define BIT_CLEAR_FW_DBG6_8822B(x) ((x) & (~BITS_FW_DBG6_8822B))
+#define BIT_GET_FW_DBG6_8822B(x)                                               \
+	(((x) >> BIT_SHIFT_FW_DBG6_8822B) & BIT_MASK_FW_DBG6_8822B)
+#define BIT_SET_FW_DBG6_8822B(x, v)                                            \
+	(BIT_CLEAR_FW_DBG6_8822B(x) | BIT_FW_DBG6_8822B(v))
+
+/* 2 REG_FW_DBG7_8822B */
+
+#define BIT_SHIFT_FW_DBG7_8822B 0
+#define BIT_MASK_FW_DBG7_8822B 0xffffffffL
+#define BIT_FW_DBG7_8822B(x)                                                   \
+	(((x) & BIT_MASK_FW_DBG7_8822B) << BIT_SHIFT_FW_DBG7_8822B)
+#define BITS_FW_DBG7_8822B (BIT_MASK_FW_DBG7_8822B << BIT_SHIFT_FW_DBG7_8822B)
+#define BIT_CLEAR_FW_DBG7_8822B(x) ((x) & (~BITS_FW_DBG7_8822B))
+#define BIT_GET_FW_DBG7_8822B(x)                                               \
+	(((x) >> BIT_SHIFT_FW_DBG7_8822B) & BIT_MASK_FW_DBG7_8822B)
+#define BIT_SET_FW_DBG7_8822B(x, v)                                            \
+	(BIT_CLEAR_FW_DBG7_8822B(x) | BIT_FW_DBG7_8822B(v))
+
+/* 2 REG_NOT_VALID_8822B */
+
+/* 2 REG_CR_8822B */
+
+#define BIT_SHIFT_LBMODE_8822B 24
+#define BIT_MASK_LBMODE_8822B 0x1f
+#define BIT_LBMODE_8822B(x)                                                    \
+	(((x) & BIT_MASK_LBMODE_8822B) << BIT_SHIFT_LBMODE_8822B)
+#define BITS_LBMODE_8822B (BIT_MASK_LBMODE_8822B << BIT_SHIFT_LBMODE_8822B)
+#define BIT_CLEAR_LBMODE_8822B(x) ((x) & (~BITS_LBMODE_8822B))
+#define BIT_GET_LBMODE_8822B(x)                                                \
+	(((x) >> BIT_SHIFT_LBMODE_8822B) & BIT_MASK_LBMODE_8822B)
+#define BIT_SET_LBMODE_8822B(x, v)                                             \
+	(BIT_CLEAR_LBMODE_8822B(x) | BIT_LBMODE_8822B(v))
+
+#define BIT_SHIFT_NETYPE1_8822B 18
+#define BIT_MASK_NETYPE1_8822B 0x3
+#define BIT_NETYPE1_8822B(x)                                                   \
+	(((x) & BIT_MASK_NETYPE1_8822B) << BIT_SHIFT_NETYPE1_8822B)
+#define BITS_NETYPE1_8822B (BIT_MASK_NETYPE1_8822B << BIT_SHIFT_NETYPE1_8822B)
+#define BIT_CLEAR_NETYPE1_8822B(x) ((x) & (~BITS_NETYPE1_8822B))
+#define BIT_GET_NETYPE1_8822B(x)                                               \
+	(((x) >> BIT_SHIFT_NETYPE1_8822B) & BIT_MASK_NETYPE1_8822B)
+#define BIT_SET_NETYPE1_8822B(x, v)                                            \
+	(BIT_CLEAR_NETYPE1_8822B(x) | BIT_NETYPE1_8822B(v))
+
+#define BIT_SHIFT_NETYPE0_8822B 16
+#define BIT_MASK_NETYPE0_8822B 0x3
+#define BIT_NETYPE0_8822B(x)                                                   \
+	(((x) & BIT_MASK_NETYPE0_8822B) << BIT_SHIFT_NETYPE0_8822B)
+#define BITS_NETYPE0_8822B (BIT_MASK_NETYPE0_8822B << BIT_SHIFT_NETYPE0_8822B)
+#define BIT_CLEAR_NETYPE0_8822B(x) ((x) & (~BITS_NETYPE0_8822B))
+#define BIT_GET_NETYPE0_8822B(x)                                               \
+	(((x) >> BIT_SHIFT_NETYPE0_8822B) & BIT_MASK_NETYPE0_8822B)
+#define BIT_SET_NETYPE0_8822B(x, v)                                            \
+	(BIT_CLEAR_NETYPE0_8822B(x) | BIT_NETYPE0_8822B(v))
+
+#define BIT_I2C_MAILBOX_EN_8822B BIT(12)
+#define BIT_SHCUT_EN_8822B BIT(11)
+#define BIT_32K_CAL_TMR_EN_8822B BIT(10)
+#define BIT_MAC_SEC_EN_8822B BIT(9)
+#define BIT_ENSWBCN_8822B BIT(8)
+#define BIT_MACRXEN_8822B BIT(7)
+#define BIT_MACTXEN_8822B BIT(6)
+#define BIT_SCHEDULE_EN_8822B BIT(5)
+#define BIT_PROTOCOL_EN_8822B BIT(4)
+#define BIT_RXDMA_EN_8822B BIT(3)
+#define BIT_TXDMA_EN_8822B BIT(2)
+#define BIT_HCI_RXDMA_EN_8822B BIT(1)
+#define BIT_HCI_TXDMA_EN_8822B BIT(0)
+
+/* 2 REG_TSF_CLK_STATE_8822B */
+#define BIT_TSF_CLK_STABLE_8822B BIT(15)
+
+/* 2 REG_TXDMA_PQ_MAP_8822B */
+
+#define BIT_SHIFT_TXDMA_HIQ_MAP_8822B 14
+#define BIT_MASK_TXDMA_HIQ_MAP_8822B 0x3
+#define BIT_TXDMA_HIQ_MAP_8822B(x)                                             \
+	(((x) & BIT_MASK_TXDMA_HIQ_MAP_8822B) << BIT_SHIFT_TXDMA_HIQ_MAP_8822B)
+#define BITS_TXDMA_HIQ_MAP_8822B                                               \
+	(BIT_MASK_TXDMA_HIQ_MAP_8822B << BIT_SHIFT_TXDMA_HIQ_MAP_8822B)
+#define BIT_CLEAR_TXDMA_HIQ_MAP_8822B(x) ((x) & (~BITS_TXDMA_HIQ_MAP_8822B))
+#define BIT_GET_TXDMA_HIQ_MAP_8822B(x)                                         \
+	(((x) >> BIT_SHIFT_TXDMA_HIQ_MAP_8822B) & BIT_MASK_TXDMA_HIQ_MAP_8822B)
+#define BIT_SET_TXDMA_HIQ_MAP_8822B(x, v)                                      \
+	(BIT_CLEAR_TXDMA_HIQ_MAP_8822B(x) | BIT_TXDMA_HIQ_MAP_8822B(v))
+
+#define BIT_SHIFT_TXDMA_MGQ_MAP_8822B 12
+#define BIT_MASK_TXDMA_MGQ_MAP_8822B 0x3
+#define BIT_TXDMA_MGQ_MAP_8822B(x)                                             \
+	(((x) & BIT_MASK_TXDMA_MGQ_MAP_8822B) << BIT_SHIFT_TXDMA_MGQ_MAP_8822B)
+#define BITS_TXDMA_MGQ_MAP_8822B                                               \
+	(BIT_MASK_TXDMA_MGQ_MAP_8822B << BIT_SHIFT_TXDMA_MGQ_MAP_8822B)
+#define BIT_CLEAR_TXDMA_MGQ_MAP_8822B(x) ((x) & (~BITS_TXDMA_MGQ_MAP_8822B))
+#define BIT_GET_TXDMA_MGQ_MAP_8822B(x)                                         \
+	(((x) >> BIT_SHIFT_TXDMA_MGQ_MAP_8822B) & BIT_MASK_TXDMA_MGQ_MAP_8822B)
+#define BIT_SET_TXDMA_MGQ_MAP_8822B(x, v)                                      \
+	(BIT_CLEAR_TXDMA_MGQ_MAP_8822B(x) | BIT_TXDMA_MGQ_MAP_8822B(v))
+
+#define BIT_SHIFT_TXDMA_BKQ_MAP_8822B 10
+#define BIT_MASK_TXDMA_BKQ_MAP_8822B 0x3
+#define BIT_TXDMA_BKQ_MAP_8822B(x)                                             \
+	(((x) & BIT_MASK_TXDMA_BKQ_MAP_8822B) << BIT_SHIFT_TXDMA_BKQ_MAP_8822B)
+#define BITS_TXDMA_BKQ_MAP_8822B                                               \
+	(BIT_MASK_TXDMA_BKQ_MAP_8822B << BIT_SHIFT_TXDMA_BKQ_MAP_8822B)
+#define BIT_CLEAR_TXDMA_BKQ_MAP_8822B(x) ((x) & (~BITS_TXDMA_BKQ_MAP_8822B))
+#define BIT_GET_TXDMA_BKQ_MAP_8822B(x)                                         \
+	(((x) >> BIT_SHIFT_TXDMA_BKQ_MAP_8822B) & BIT_MASK_TXDMA_BKQ_MAP_8822B)
+#define BIT_SET_TXDMA_BKQ_MAP_8822B(x, v)                                      \
+	(BIT_CLEAR_TXDMA_BKQ_MAP_8822B(x) | BIT_TXDMA_BKQ_MAP_8822B(v))
+
+#define BIT_SHIFT_TXDMA_BEQ_MAP_8822B 8
+#define BIT_MASK_TXDMA_BEQ_MAP_8822B 0x3
+#define BIT_TXDMA_BEQ_MAP_8822B(x)                                             \
+	(((x) & BIT_MASK_TXDMA_BEQ_MAP_8822B) << BIT_SHIFT_TXDMA_BEQ_MAP_8822B)
+#define BITS_TXDMA_BEQ_MAP_8822B                                               \
+	(BIT_MASK_TXDMA_BEQ_MAP_8822B << BIT_SHIFT_TXDMA_BEQ_MAP_8822B)
+#define BIT_CLEAR_TXDMA_BEQ_MAP_8822B(x) ((x) & (~BITS_TXDMA_BEQ_MAP_8822B))
+#define BIT_GET_TXDMA_BEQ_MAP_8822B(x)                                         \
+	(((x) >> BIT_SHIFT_TXDMA_BEQ_MAP_8822B) & BIT_MASK_TXDMA_BEQ_MAP_8822B)
+#define BIT_SET_TXDMA_BEQ_MAP_8822B(x, v)                                      \
+	(BIT_CLEAR_TXDMA_BEQ_MAP_8822B(x) | BIT_TXDMA_BEQ_MAP_8822B(v))
+
+#define BIT_SHIFT_TXDMA_VIQ_MAP_8822B 6
+#define BIT_MASK_TXDMA_VIQ_MAP_8822B 0x3
+#define BIT_TXDMA_VIQ_MAP_8822B(x)                                             \
+	(((x) & BIT_MASK_TXDMA_VIQ_MAP_8822B) << BIT_SHIFT_TXDMA_VIQ_MAP_8822B)
+#define BITS_TXDMA_VIQ_MAP_8822B                                               \
+	(BIT_MASK_TXDMA_VIQ_MAP_8822B << BIT_SHIFT_TXDMA_VIQ_MAP_8822B)
+#define BIT_CLEAR_TXDMA_VIQ_MAP_8822B(x) ((x) & (~BITS_TXDMA_VIQ_MAP_8822B))
+#define BIT_GET_TXDMA_VIQ_MAP_8822B(x)                                         \
+	(((x) >> BIT_SHIFT_TXDMA_VIQ_MAP_8822B) & BIT_MASK_TXDMA_VIQ_MAP_8822B)
+#define BIT_SET_TXDMA_VIQ_MAP_8822B(x, v)                                      \
+	(BIT_CLEAR_TXDMA_VIQ_MAP_8822B(x) | BIT_TXDMA_VIQ_MAP_8822B(v))
+
+#define BIT_SHIFT_TXDMA_VOQ_MAP_8822B 4
+#define BIT_MASK_TXDMA_VOQ_MAP_8822B 0x3
+#define BIT_TXDMA_VOQ_MAP_8822B(x)                                             \
+	(((x) & BIT_MASK_TXDMA_VOQ_MAP_8822B) << BIT_SHIFT_TXDMA_VOQ_MAP_8822B)
+#define BITS_TXDMA_VOQ_MAP_8822B                                               \
+	(BIT_MASK_TXDMA_VOQ_MAP_8822B << BIT_SHIFT_TXDMA_VOQ_MAP_8822B)
+#define BIT_CLEAR_TXDMA_VOQ_MAP_8822B(x) ((x) & (~BITS_TXDMA_VOQ_MAP_8822B))
+#define BIT_GET_TXDMA_VOQ_MAP_8822B(x)                                         \
+	(((x) >> BIT_SHIFT_TXDMA_VOQ_MAP_8822B) & BIT_MASK_TXDMA_VOQ_MAP_8822B)
+#define BIT_SET_TXDMA_VOQ_MAP_8822B(x, v)                                      \
+	(BIT_CLEAR_TXDMA_VOQ_MAP_8822B(x) | BIT_TXDMA_VOQ_MAP_8822B(v))
+
+#define BIT_RXDMA_AGG_EN_8822B BIT(2)
+#define BIT_RXSHFT_EN_8822B BIT(1)
+#define BIT_RXDMA_ARBBW_EN_8822B BIT(0)
+
+/* 2 REG_TRXFF_BNDY_8822B */
+
+#define BIT_SHIFT_RXFFOVFL_RSV_V2_8822B 8
+#define BIT_MASK_RXFFOVFL_RSV_V2_8822B 0xf
+#define BIT_RXFFOVFL_RSV_V2_8822B(x)                                           \
+	(((x) & BIT_MASK_RXFFOVFL_RSV_V2_8822B)                                \
+	 << BIT_SHIFT_RXFFOVFL_RSV_V2_8822B)
+#define BITS_RXFFOVFL_RSV_V2_8822B                                             \
+	(BIT_MASK_RXFFOVFL_RSV_V2_8822B << BIT_SHIFT_RXFFOVFL_RSV_V2_8822B)
+#define BIT_CLEAR_RXFFOVFL_RSV_V2_8822B(x) ((x) & (~BITS_RXFFOVFL_RSV_V2_8822B))
+#define BIT_GET_RXFFOVFL_RSV_V2_8822B(x)                                       \
+	(((x) >> BIT_SHIFT_RXFFOVFL_RSV_V2_8822B) &                            \
+	 BIT_MASK_RXFFOVFL_RSV_V2_8822B)
+#define BIT_SET_RXFFOVFL_RSV_V2_8822B(x, v)                                    \
+	(BIT_CLEAR_RXFFOVFL_RSV_V2_8822B(x) | BIT_RXFFOVFL_RSV_V2_8822B(v))
+
+#define BIT_SHIFT_TXPKTBUF_PGBNDY_8822B 0
+#define BIT_MASK_TXPKTBUF_PGBNDY_8822B 0xff
+#define BIT_TXPKTBUF_PGBNDY_8822B(x)                                           \
+	(((x) & BIT_MASK_TXPKTBUF_PGBNDY_8822B)                                \
+	 << BIT_SHIFT_TXPKTBUF_PGBNDY_8822B)
+#define BITS_TXPKTBUF_PGBNDY_8822B                                             \
+	(BIT_MASK_TXPKTBUF_PGBNDY_8822B << BIT_SHIFT_TXPKTBUF_PGBNDY_8822B)
+#define BIT_CLEAR_TXPKTBUF_PGBNDY_8822B(x) ((x) & (~BITS_TXPKTBUF_PGBNDY_8822B))
+#define BIT_GET_TXPKTBUF_PGBNDY_8822B(x)                                       \
+	(((x) >> BIT_SHIFT_TXPKTBUF_PGBNDY_8822B) &                            \
+	 BIT_MASK_TXPKTBUF_PGBNDY_8822B)
+#define BIT_SET_TXPKTBUF_PGBNDY_8822B(x, v)                                    \
+	(BIT_CLEAR_TXPKTBUF_PGBNDY_8822B(x) | BIT_TXPKTBUF_PGBNDY_8822B(v))
+
+/* 2 REG_PTA_I2C_MBOX_8822B */
+
+/* 2 REG_NOT_VALID_8822B */
+
+#define BIT_SHIFT_I2C_M_STATUS_8822B 8
+#define BIT_MASK_I2C_M_STATUS_8822B 0xf
+#define BIT_I2C_M_STATUS_8822B(x)                                              \
+	(((x) & BIT_MASK_I2C_M_STATUS_8822B) << BIT_SHIFT_I2C_M_STATUS_8822B)
+#define BITS_I2C_M_STATUS_8822B                                                \
+	(BIT_MASK_I2C_M_STATUS_8822B << BIT_SHIFT_I2C_M_STATUS_8822B)
+#define BIT_CLEAR_I2C_M_STATUS_8822B(x) ((x) & (~BITS_I2C_M_STATUS_8822B))
+#define BIT_GET_I2C_M_STATUS_8822B(x)                                          \
+	(((x) >> BIT_SHIFT_I2C_M_STATUS_8822B) & BIT_MASK_I2C_M_STATUS_8822B)
+#define BIT_SET_I2C_M_STATUS_8822B(x, v)                                       \
+	(BIT_CLEAR_I2C_M_STATUS_8822B(x) | BIT_I2C_M_STATUS_8822B(v))
+
+#define BIT_SHIFT_I2C_M_BUS_GNT_FW_8822B 4
+#define BIT_MASK_I2C_M_BUS_GNT_FW_8822B 0x7
+#define BIT_I2C_M_BUS_GNT_FW_8822B(x)                                          \
+	(((x) & BIT_MASK_I2C_M_BUS_GNT_FW_8822B)                               \
+	 << BIT_SHIFT_I2C_M_BUS_GNT_FW_8822B)
+#define BITS_I2C_M_BUS_GNT_FW_8822B                                            \
+	(BIT_MASK_I2C_M_BUS_GNT_FW_8822B << BIT_SHIFT_I2C_M_BUS_GNT_FW_8822B)
+#define BIT_CLEAR_I2C_M_BUS_GNT_FW_8822B(x)                                    \
+	((x) & (~BITS_I2C_M_BUS_GNT_FW_8822B))
+#define BIT_GET_I2C_M_BUS_GNT_FW_8822B(x)                                      \
+	(((x) >> BIT_SHIFT_I2C_M_BUS_GNT_FW_8822B) &                           \
+	 BIT_MASK_I2C_M_BUS_GNT_FW_8822B)
+#define BIT_SET_I2C_M_BUS_GNT_FW_8822B(x, v)                                   \
+	(BIT_CLEAR_I2C_M_BUS_GNT_FW_8822B(x) | BIT_I2C_M_BUS_GNT_FW_8822B(v))
+
+#define BIT_I2C_M_GNT_FW_8822B BIT(3)
+
+#define BIT_SHIFT_I2C_M_SPEED_8822B 1
+#define BIT_MASK_I2C_M_SPEED_8822B 0x3
+#define BIT_I2C_M_SPEED_8822B(x)                                               \
+	(((x) & BIT_MASK_I2C_M_SPEED_8822B) << BIT_SHIFT_I2C_M_SPEED_8822B)
+#define BITS_I2C_M_SPEED_8822B                                                 \
+	(BIT_MASK_I2C_M_SPEED_8822B << BIT_SHIFT_I2C_M_SPEED_8822B)
+#define BIT_CLEAR_I2C_M_SPEED_8822B(x) ((x) & (~BITS_I2C_M_SPEED_8822B))
+#define BIT_GET_I2C_M_SPEED_8822B(x)                                           \
+	(((x) >> BIT_SHIFT_I2C_M_SPEED_8822B) & BIT_MASK_I2C_M_SPEED_8822B)
+#define BIT_SET_I2C_M_SPEED_8822B(x, v)                                        \
+	(BIT_CLEAR_I2C_M_SPEED_8822B(x) | BIT_I2C_M_SPEED_8822B(v))
+
+#define BIT_I2C_M_UNLOCK_8822B BIT(0)
+
+/* 2 REG_RXFF_BNDY_8822B */
+
+/* 2 REG_NOT_VALID_8822B */
+
+#define BIT_SHIFT_RXFF0_BNDY_V2_8822B 0
+#define BIT_MASK_RXFF0_BNDY_V2_8822B 0x3ffff
+#define BIT_RXFF0_BNDY_V2_8822B(x)                                             \
+	(((x) & BIT_MASK_RXFF0_BNDY_V2_8822B) << BIT_SHIFT_RXFF0_BNDY_V2_8822B)
+#define BITS_RXFF0_BNDY_V2_8822B                                               \
+	(BIT_MASK_RXFF0_BNDY_V2_8822B << BIT_SHIFT_RXFF0_BNDY_V2_8822B)
+#define BIT_CLEAR_RXFF0_BNDY_V2_8822B(x) ((x) & (~BITS_RXFF0_BNDY_V2_8822B))
+#define BIT_GET_RXFF0_BNDY_V2_8822B(x)                                         \
+	(((x) >> BIT_SHIFT_RXFF0_BNDY_V2_8822B) & BIT_MASK_RXFF0_BNDY_V2_8822B)
+#define BIT_SET_RXFF0_BNDY_V2_8822B(x, v)                                      \
+	(BIT_CLEAR_RXFF0_BNDY_V2_8822B(x) | BIT_RXFF0_BNDY_V2_8822B(v))
+
+/* 2 REG_FE1IMR_8822B */
+#define BIT_FS_RXDMA2_DONE_INT_EN_8822B BIT(28)
+#define BIT_FS_RXDONE3_INT_EN_8822B BIT(27)
+#define BIT_FS_RXDONE2_INT_EN_8822B BIT(26)
+#define BIT_FS_RX_BCN_P4_INT_EN_8822B BIT(25)
+#define BIT_FS_RX_BCN_P3_INT_EN_8822B BIT(24)
+#define BIT_FS_RX_BCN_P2_INT_EN_8822B BIT(23)
+#define BIT_FS_RX_BCN_P1_INT_EN_8822B BIT(22)
+#define BIT_FS_RX_BCN_P0_INT_EN_8822B BIT(21)
+#define BIT_FS_RX_UMD0_INT_EN_8822B BIT(20)
+#define BIT_FS_RX_UMD1_INT_EN_8822B BIT(19)
+#define BIT_FS_RX_BMD0_INT_EN_8822B BIT(18)
+#define BIT_FS_RX_BMD1_INT_EN_8822B BIT(17)
+#define BIT_FS_RXDONE_INT_EN_8822B BIT(16)
+#define BIT_FS_WWLAN_INT_EN_8822B BIT(15)
+#define BIT_FS_SOUND_DONE_INT_EN_8822B BIT(14)
+#define BIT_FS_LP_STBY_INT_EN_8822B BIT(13)
+#define BIT_FS_TRL_MTR_INT_EN_8822B BIT(12)
+#define BIT_FS_BF1_PRETO_INT_EN_8822B BIT(11)
+#define BIT_FS_BF0_PRETO_INT_EN_8822B BIT(10)
+#define BIT_FS_PTCL_RELEASE_MACID_INT_EN_8822B BIT(9)
+#define BIT_FS_LTE_COEX_EN_8822B BIT(6)
+#define BIT_FS_WLACTOFF_INT_EN_8822B BIT(5)
+#define BIT_FS_WLACTON_INT_EN_8822B BIT(4)
+#define BIT_FS_BTCMD_INT_EN_8822B BIT(3)
+#define BIT_FS_REG_MAILBOX_TO_I2C_INT_EN_8822B BIT(2)
+#define BIT_FS_TRPC_TO_INT_EN_V1_8822B BIT(1)
+#define BIT_FS_RPC_O_T_INT_EN_V1_8822B BIT(0)
+
+/* 2 REG_FE1ISR_8822B */
+#define BIT_FS_RXDMA2_DONE_INT_8822B BIT(28)
+#define BIT_FS_RXDONE3_INT_8822B BIT(27)
+#define BIT_FS_RXDONE2_INT_8822B BIT(26)
+#define BIT_FS_RX_BCN_P4_INT_8822B BIT(25)
+#define BIT_FS_RX_BCN_P3_INT_8822B BIT(24)
+#define BIT_FS_RX_BCN_P2_INT_8822B BIT(23)
+#define BIT_FS_RX_BCN_P1_INT_8822B BIT(22)
+#define BIT_FS_RX_BCN_P0_INT_8822B BIT(21)
+#define BIT_FS_RX_UMD0_INT_8822B BIT(20)
+#define BIT_FS_RX_UMD1_INT_8822B BIT(19)
+#define BIT_FS_RX_BMD0_INT_8822B BIT(18)
+#define BIT_FS_RX_BMD1_INT_8822B BIT(17)
+#define BIT_FS_RXDONE_INT_8822B BIT(16)
+#define BIT_FS_WWLAN_INT_8822B BIT(15)
+#define BIT_FS_SOUND_DONE_INT_8822B BIT(14)
+#define BIT_FS_LP_STBY_INT_8822B BIT(13)
+#define BIT_FS_TRL_MTR_INT_8822B BIT(12)
+#define BIT_FS_BF1_PRETO_INT_8822B BIT(11)
+#define BIT_FS_BF0_PRETO_INT_8822B BIT(10)
+#define BIT_FS_PTCL_RELEASE_MACID_INT_8822B BIT(9)
+#define BIT_FS_LTE_COEX_INT_8822B BIT(6)
+#define BIT_FS_WLACTOFF_INT_8822B BIT(5)
+#define BIT_FS_WLACTON_INT_8822B BIT(4)
+#define BIT_FS_BCN_RX_INT_INT_8822B BIT(3)
+#define BIT_FS_MAILBOX_TO_I2C_INT_8822B BIT(2)
+#define BIT_FS_TRPC_TO_INT_8822B BIT(1)
+#define BIT_FS_RPC_O_T_INT_8822B BIT(0)
+
+/* 2 REG_NOT_VALID_8822B */
+
+/* 2 REG_CPWM_8822B */
+#define BIT_CPWM_TOGGLING_8822B BIT(31)
+
+#define BIT_SHIFT_CPWM_MOD_8822B 24
+#define BIT_MASK_CPWM_MOD_8822B 0x7f
+#define BIT_CPWM_MOD_8822B(x)                                                  \
+	(((x) & BIT_MASK_CPWM_MOD_8822B) << BIT_SHIFT_CPWM_MOD_8822B)
+#define BITS_CPWM_MOD_8822B                                                    \
+	(BIT_MASK_CPWM_MOD_8822B << BIT_SHIFT_CPWM_MOD_8822B)
+#define BIT_CLEAR_CPWM_MOD_8822B(x) ((x) & (~BITS_CPWM_MOD_8822B))
+#define BIT_GET_CPWM_MOD_8822B(x)                                              \
+	(((x) >> BIT_SHIFT_CPWM_MOD_8822B) & BIT_MASK_CPWM_MOD_8822B)
+#define BIT_SET_CPWM_MOD_8822B(x, v)                                           \
+	(BIT_CLEAR_CPWM_MOD_8822B(x) | BIT_CPWM_MOD_8822B(v))
+
+/* 2 REG_FWIMR_8822B */
+#define BIT_FS_TXBCNOK_MB7_INT_EN_8822B BIT(31)
+#define BIT_FS_TXBCNOK_MB6_INT_EN_8822B BIT(30)
+#define BIT_FS_TXBCNOK_MB5_INT_EN_8822B BIT(29)
+#define BIT_FS_TXBCNOK_MB4_INT_EN_8822B BIT(28)
+#define BIT_FS_TXBCNOK_MB3_INT_EN_8822B BIT(27)
+#define BIT_FS_TXBCNOK_MB2_INT_EN_8822B BIT(26)
+#define BIT_FS_TXBCNOK_MB1_INT_EN_8822B BIT(25)
+#define BIT_FS_TXBCNOK_MB0_INT_EN_8822B BIT(24)
+#define BIT_FS_TXBCNERR_MB7_INT_EN_8822B BIT(23)
+#define BIT_FS_TXBCNERR_MB6_INT_EN_8822B BIT(22)
+#define BIT_FS_TXBCNERR_MB5_INT_EN_8822B BIT(21)
+#define BIT_FS_TXBCNERR_MB4_INT_EN_8822B BIT(20)
+#define BIT_FS_TXBCNERR_MB3_INT_EN_8822B BIT(19)
+#define BIT_FS_TXBCNERR_MB2_INT_EN_8822B BIT(18)
+#define BIT_FS_TXBCNERR_MB1_INT_EN_8822B BIT(17)
+#define BIT_FS_TXBCNERR_MB0_INT_EN_8822B BIT(16)
+#define BIT_CPU_MGQ_TXDONE_INT_EN_8822B BIT(15)
+#define BIT_SIFS_OVERSPEC_INT_EN_8822B BIT(14)
+#define BIT_FS_MGNTQ_RPTR_RELEASE_INT_EN_8822B BIT(13)
+#define BIT_FS_MGNTQFF_TO_INT_EN_8822B BIT(12)
+#define BIT_FS_CPUMGQ_ERR_INT_EN_8822B BIT(11)
+#define BIT_FS_DDMA0_LP_INT_EN_8822B BIT(9)
+#define BIT_FS_DDMA0_HP_INT_EN_8822B BIT(8)
+#define BIT_FS_TRXRPT_INT_EN_8822B BIT(7)
+#define BIT_FS_C2H_W_READY_INT_EN_8822B BIT(6)
+#define BIT_FS_HRCV_INT_EN_8822B BIT(5)
+#define BIT_FS_H2CCMD_INT_EN_8822B BIT(4)
+#define BIT_FS_TXPKTIN_INT_EN_8822B BIT(3)
+#define BIT_FS_ERRORHDL_INT_EN_8822B BIT(2)
+#define BIT_FS_TXCCX_INT_EN_8822B BIT(1)
+#define BIT_FS_TXCLOSE_INT_EN_8822B BIT(0)
+
+/* 2 REG_FWISR_8822B */
+#define BIT_FS_TXBCNOK_MB7_INT_8822B BIT(31)
+#define BIT_FS_TXBCNOK_MB6_INT_8822B BIT(30)
+#define BIT_FS_TXBCNOK_MB5_INT_8822B BIT(29)
+#define BIT_FS_TXBCNOK_MB4_INT_8822B BIT(28)
+#define BIT_FS_TXBCNOK_MB3_INT_8822B BIT(27)
+#define BIT_FS_TXBCNOK_MB2_INT_8822B BIT(26)
+#define BIT_FS_TXBCNOK_MB1_INT_8822B BIT(25)
+#define BIT_FS_TXBCNOK_MB0_INT_8822B BIT(24)
+#define BIT_FS_TXBCNERR_MB7_INT_8822B BIT(23)
+#define BIT_FS_TXBCNERR_MB6_INT_8822B BIT(22)
+#define BIT_FS_TXBCNERR_MB5_INT_8822B BIT(21)
+#define BIT_FS_TXBCNERR_MB4_INT_8822B BIT(20)
+#define BIT_FS_TXBCNERR_MB3_INT_8822B BIT(19)
+#define BIT_FS_TXBCNERR_MB2_INT_8822B BIT(18)
+#define BIT_FS_TXBCNERR_MB1_INT_8822B BIT(17)
+#define BIT_FS_TXBCNERR_MB0_INT_8822B BIT(16)
+#define BIT_CPU_MGQ_TXDONE_INT_8822B BIT(15)
+#define BIT_SIFS_OVERSPEC_INT_8822B BIT(14)
+#define BIT_FS_MGNTQ_RPTR_RELEASE_INT_8822B BIT(13)
+#define BIT_FS_MGNTQFF_TO_INT_8822B BIT(12)
+#define BIT_FS_CPUMGQ_ERR_INT_8822B BIT(11)
+#define BIT_FS_DDMA0_LP_INT_8822B BIT(9)
+#define BIT_FS_DDMA0_HP_INT_8822B BIT(8)
+#define BIT_FS_TRXRPT_INT_8822B BIT(7)
+#define BIT_FS_C2H_W_READY_INT_8822B BIT(6)
+#define BIT_FS_HRCV_INT_8822B BIT(5)
+#define BIT_FS_H2CCMD_INT_8822B BIT(4)
+#define BIT_FS_TXPKTIN_INT_8822B BIT(3)
+#define BIT_FS_ERRORHDL_INT_8822B BIT(2)
+#define BIT_FS_TXCCX_INT_8822B BIT(1)
+#define BIT_FS_TXCLOSE_INT_8822B BIT(0)
+
+/* 2 REG_FTIMR_8822B */
+#define BIT_PS_TIMER_C_EARLY_INT_EN_8822B BIT(23)
+#define BIT_PS_TIMER_B_EARLY_INT_EN_8822B BIT(22)
+#define BIT_PS_TIMER_A_EARLY_INT_EN_8822B BIT(21)
+#define BIT_CPUMGQ_TX_TIMER_EARLY_INT_EN_8822B BIT(20)
+#define BIT_PS_TIMER_C_INT_EN_8822B BIT(19)
+#define BIT_PS_TIMER_B_INT_EN_8822B BIT(18)
+#define BIT_PS_TIMER_A_INT_EN_8822B BIT(17)
+#define BIT_CPUMGQ_TX_TIMER_INT_EN_8822B BIT(16)
+#define BIT_FS_PS_TIMEOUT2_EN_8822B BIT(15)
+#define BIT_FS_PS_TIMEOUT1_EN_8822B BIT(14)
+#define BIT_FS_PS_TIMEOUT0_EN_8822B BIT(13)
+#define BIT_FS_GTINT8_EN_8822B BIT(8)
+#define BIT_FS_GTINT7_EN_8822B BIT(7)
+#define BIT_FS_GTINT6_EN_8822B BIT(6)
+#define BIT_FS_GTINT5_EN_8822B BIT(5)
+#define BIT_FS_GTINT4_EN_8822B BIT(4)
+#define BIT_FS_GTINT3_EN_8822B BIT(3)
+#define BIT_FS_GTINT2_EN_8822B BIT(2)
+#define BIT_FS_GTINT1_EN_8822B BIT(1)
+#define BIT_FS_GTINT0_EN_8822B BIT(0)
+
+/* 2 REG_FTISR_8822B */
+#define BIT_PS_TIMER_C_EARLY__INT_8822B BIT(23)
+#define BIT_PS_TIMER_B_EARLY__INT_8822B BIT(22)
+#define BIT_PS_TIMER_A_EARLY__INT_8822B BIT(21)
+#define BIT_CPUMGQ_TX_TIMER_EARLY_INT_8822B BIT(20)
+#define BIT_PS_TIMER_C_INT_8822B BIT(19)
+#define BIT_PS_TIMER_B_INT_8822B BIT(18)
+#define BIT_PS_TIMER_A_INT_8822B BIT(17)
+#define BIT_CPUMGQ_TX_TIMER_INT_8822B BIT(16)
+#define BIT_FS_PS_TIMEOUT2_INT_8822B BIT(15)
+#define BIT_FS_PS_TIMEOUT1_INT_8822B BIT(14)
+#define BIT_FS_PS_TIMEOUT0_INT_8822B BIT(13)
+#define BIT_FS_GTINT8_INT_8822B BIT(8)
+#define BIT_FS_GTINT7_INT_8822B BIT(7)
+#define BIT_FS_GTINT6_INT_8822B BIT(6)
+#define BIT_FS_GTINT5_INT_8822B BIT(5)
+#define BIT_FS_GTINT4_INT_8822B BIT(4)
+#define BIT_FS_GTINT3_INT_8822B BIT(3)
+#define BIT_FS_GTINT2_INT_8822B BIT(2)
+#define BIT_FS_GTINT1_INT_8822B BIT(1)
+#define BIT_FS_GTINT0_INT_8822B BIT(0)
+
+/* 2 REG_PKTBUF_DBG_CTRL_8822B */
+
+#define BIT_SHIFT_PKTBUF_WRITE_EN_8822B 24
+#define BIT_MASK_PKTBUF_WRITE_EN_8822B 0xff
+#define BIT_PKTBUF_WRITE_EN_8822B(x)                                           \
+	(((x) & BIT_MASK_PKTBUF_WRITE_EN_8822B)                                \
+	 << BIT_SHIFT_PKTBUF_WRITE_EN_8822B)
+#define BITS_PKTBUF_WRITE_EN_8822B                                             \
+	(BIT_MASK_PKTBUF_WRITE_EN_8822B << BIT_SHIFT_PKTBUF_WRITE_EN_8822B)
+#define BIT_CLEAR_PKTBUF_WRITE_EN_8822B(x) ((x) & (~BITS_PKTBUF_WRITE_EN_8822B))
+#define BIT_GET_PKTBUF_WRITE_EN_8822B(x)                                       \
+	(((x) >> BIT_SHIFT_PKTBUF_WRITE_EN_8822B) &                            \
+	 BIT_MASK_PKTBUF_WRITE_EN_8822B)
+#define BIT_SET_PKTBUF_WRITE_EN_8822B(x, v)                                    \
+	(BIT_CLEAR_PKTBUF_WRITE_EN_8822B(x) | BIT_PKTBUF_WRITE_EN_8822B(v))
+
+#define BIT_TXRPTBUF_DBG_8822B BIT(23)
+
+/* 2 REG_NOT_VALID_8822B */
+#define BIT_TXPKTBUF_DBG_V2_8822B BIT(20)
+#define BIT_RXPKTBUF_DBG_8822B BIT(16)
+
+#define BIT_SHIFT_PKTBUF_DBG_ADDR_8822B 0
+#define BIT_MASK_PKTBUF_DBG_ADDR_8822B 0x1fff
+#define BIT_PKTBUF_DBG_ADDR_8822B(x)                                           \
+	(((x) & BIT_MASK_PKTBUF_DBG_ADDR_8822B)                                \
+	 << BIT_SHIFT_PKTBUF_DBG_ADDR_8822B)
+#define BITS_PKTBUF_DBG_ADDR_8822B                                             \
+	(BIT_MASK_PKTBUF_DBG_ADDR_8822B << BIT_SHIFT_PKTBUF_DBG_ADDR_8822B)
+#define BIT_CLEAR_PKTBUF_DBG_ADDR_8822B(x) ((x) & (~BITS_PKTBUF_DBG_ADDR_8822B))
+#define BIT_GET_PKTBUF_DBG_ADDR_8822B(x)                                       \
+	(((x) >> BIT_SHIFT_PKTBUF_DBG_ADDR_8822B) &                            \
+	 BIT_MASK_PKTBUF_DBG_ADDR_8822B)
+#define BIT_SET_PKTBUF_DBG_ADDR_8822B(x, v)                                    \
+	(BIT_CLEAR_PKTBUF_DBG_ADDR_8822B(x) | BIT_PKTBUF_DBG_ADDR_8822B(v))
+
+/* 2 REG_PKTBUF_DBG_DATA_L_8822B */
+
+#define BIT_SHIFT_PKTBUF_DBG_DATA_L_8822B 0
+#define BIT_MASK_PKTBUF_DBG_DATA_L_8822B 0xffffffffL
+#define BIT_PKTBUF_DBG_DATA_L_8822B(x)                                         \
+	(((x) & BIT_MASK_PKTBUF_DBG_DATA_L_8822B)                              \
+	 << BIT_SHIFT_PKTBUF_DBG_DATA_L_8822B)
+#define BITS_PKTBUF_DBG_DATA_L_8822B                                           \
+	(BIT_MASK_PKTBUF_DBG_DATA_L_8822B << BIT_SHIFT_PKTBUF_DBG_DATA_L_8822B)
+#define BIT_CLEAR_PKTBUF_DBG_DATA_L_8822B(x)                                   \
+	((x) & (~BITS_PKTBUF_DBG_DATA_L_8822B))
+#define BIT_GET_PKTBUF_DBG_DATA_L_8822B(x)                                     \
+	(((x) >> BIT_SHIFT_PKTBUF_DBG_DATA_L_8822B) &                          \
+	 BIT_MASK_PKTBUF_DBG_DATA_L_8822B)
+#define BIT_SET_PKTBUF_DBG_DATA_L_8822B(x, v)                                  \
+	(BIT_CLEAR_PKTBUF_DBG_DATA_L_8822B(x) | BIT_PKTBUF_DBG_DATA_L_8822B(v))
+
+/* 2 REG_PKTBUF_DBG_DATA_H_8822B */
+
+#define BIT_SHIFT_PKTBUF_DBG_DATA_H_8822B 0
+#define BIT_MASK_PKTBUF_DBG_DATA_H_8822B 0xffffffffL
+#define BIT_PKTBUF_DBG_DATA_H_8822B(x)                                         \
+	(((x) & BIT_MASK_PKTBUF_DBG_DATA_H_8822B)                              \
+	 << BIT_SHIFT_PKTBUF_DBG_DATA_H_8822B)
+#define BITS_PKTBUF_DBG_DATA_H_8822B                                           \
+	(BIT_MASK_PKTBUF_DBG_DATA_H_8822B << BIT_SHIFT_PKTBUF_DBG_DATA_H_8822B)
+#define BIT_CLEAR_PKTBUF_DBG_DATA_H_8822B(x)                                   \
+	((x) & (~BITS_PKTBUF_DBG_DATA_H_8822B))
+#define BIT_GET_PKTBUF_DBG_DATA_H_8822B(x)                                     \
+	(((x) >> BIT_SHIFT_PKTBUF_DBG_DATA_H_8822B) &                          \
+	 BIT_MASK_PKTBUF_DBG_DATA_H_8822B)
+#define BIT_SET_PKTBUF_DBG_DATA_H_8822B(x, v)                                  \
+	(BIT_CLEAR_PKTBUF_DBG_DATA_H_8822B(x) | BIT_PKTBUF_DBG_DATA_H_8822B(v))
+
+/* 2 REG_CPWM2_8822B */
+
+#define BIT_SHIFT_L0S_TO_RCVY_NUM_8822B 16
+#define BIT_MASK_L0S_TO_RCVY_NUM_8822B 0xff
+#define BIT_L0S_TO_RCVY_NUM_8822B(x)                                           \
+	(((x) & BIT_MASK_L0S_TO_RCVY_NUM_8822B)                                \
+	 << BIT_SHIFT_L0S_TO_RCVY_NUM_8822B)
+#define BITS_L0S_TO_RCVY_NUM_8822B                                             \
+	(BIT_MASK_L0S_TO_RCVY_NUM_8822B << BIT_SHIFT_L0S_TO_RCVY_NUM_8822B)
+#define BIT_CLEAR_L0S_TO_RCVY_NUM_8822B(x) ((x) & (~BITS_L0S_TO_RCVY_NUM_8822B))
+#define BIT_GET_L0S_TO_RCVY_NUM_8822B(x)                                       \
+	(((x) >> BIT_SHIFT_L0S_TO_RCVY_NUM_8822B) &                            \
+	 BIT_MASK_L0S_TO_RCVY_NUM_8822B)
+#define BIT_SET_L0S_TO_RCVY_NUM_8822B(x, v)                                    \
+	(BIT_CLEAR_L0S_TO_RCVY_NUM_8822B(x) | BIT_L0S_TO_RCVY_NUM_8822B(v))
+
+#define BIT_CPWM2_TOGGLING_8822B BIT(15)
+
+#define BIT_SHIFT_CPWM2_MOD_8822B 0
+#define BIT_MASK_CPWM2_MOD_8822B 0x7fff
+#define BIT_CPWM2_MOD_8822B(x)                                                 \
+	(((x) & BIT_MASK_CPWM2_MOD_8822B) << BIT_SHIFT_CPWM2_MOD_8822B)
+#define BITS_CPWM2_MOD_8822B                                                   \
+	(BIT_MASK_CPWM2_MOD_8822B << BIT_SHIFT_CPWM2_MOD_8822B)
+#define BIT_CLEAR_CPWM2_MOD_8822B(x) ((x) & (~BITS_CPWM2_MOD_8822B))
+#define BIT_GET_CPWM2_MOD_8822B(x)                                             \
+	(((x) >> BIT_SHIFT_CPWM2_MOD_8822B) & BIT_MASK_CPWM2_MOD_8822B)
+#define BIT_SET_CPWM2_MOD_8822B(x, v)                                          \
+	(BIT_CLEAR_CPWM2_MOD_8822B(x) | BIT_CPWM2_MOD_8822B(v))
+
+/* 2 REG_NOT_VALID_8822B */
+
+/* 2 REG_TC0_CTRL_8822B */
+#define BIT_TC0INT_EN_8822B BIT(26)
+#define BIT_TC0MODE_8822B BIT(25)
+#define BIT_TC0EN_8822B BIT(24)
+
+#define BIT_SHIFT_TC0DATA_8822B 0
+#define BIT_MASK_TC0DATA_8822B 0xffffff
+#define BIT_TC0DATA_8822B(x)                                                   \
+	(((x) & BIT_MASK_TC0DATA_8822B) << BIT_SHIFT_TC0DATA_8822B)
+#define BITS_TC0DATA_8822B (BIT_MASK_TC0DATA_8822B << BIT_SHIFT_TC0DATA_8822B)
+#define BIT_CLEAR_TC0DATA_8822B(x) ((x) & (~BITS_TC0DATA_8822B))
+#define BIT_GET_TC0DATA_8822B(x)                                               \
+	(((x) >> BIT_SHIFT_TC0DATA_8822B) & BIT_MASK_TC0DATA_8822B)
+#define BIT_SET_TC0DATA_8822B(x, v)                                            \
+	(BIT_CLEAR_TC0DATA_8822B(x) | BIT_TC0DATA_8822B(v))
+
+/* 2 REG_TC1_CTRL_8822B */
+#define BIT_TC1INT_EN_8822B BIT(26)
+#define BIT_TC1MODE_8822B BIT(25)
+#define BIT_TC1EN_8822B BIT(24)
+
+#define BIT_SHIFT_TC1DATA_8822B 0
+#define BIT_MASK_TC1DATA_8822B 0xffffff
+#define BIT_TC1DATA_8822B(x)                                                   \
+	(((x) & BIT_MASK_TC1DATA_8822B) << BIT_SHIFT_TC1DATA_8822B)
+#define BITS_TC1DATA_8822B (BIT_MASK_TC1DATA_8822B << BIT_SHIFT_TC1DATA_8822B)
+#define BIT_CLEAR_TC1DATA_8822B(x) ((x) & (~BITS_TC1DATA_8822B))
+#define BIT_GET_TC1DATA_8822B(x)                                               \
+	(((x) >> BIT_SHIFT_TC1DATA_8822B) & BIT_MASK_TC1DATA_8822B)
+#define BIT_SET_TC1DATA_8822B(x, v)                                            \
+	(BIT_CLEAR_TC1DATA_8822B(x) | BIT_TC1DATA_8822B(v))
+
+/* 2 REG_TC2_CTRL_8822B */
+#define BIT_TC2INT_EN_8822B BIT(26)
+#define BIT_TC2MODE_8822B BIT(25)
+#define BIT_TC2EN_8822B BIT(24)
+
+#define BIT_SHIFT_TC2DATA_8822B 0
+#define BIT_MASK_TC2DATA_8822B 0xffffff
+#define BIT_TC2DATA_8822B(x)                                                   \
+	(((x) & BIT_MASK_TC2DATA_8822B) << BIT_SHIFT_TC2DATA_8822B)
+#define BITS_TC2DATA_8822B (BIT_MASK_TC2DATA_8822B << BIT_SHIFT_TC2DATA_8822B)
+#define BIT_CLEAR_TC2DATA_8822B(x) ((x) & (~BITS_TC2DATA_8822B))
+#define BIT_GET_TC2DATA_8822B(x)                                               \
+	(((x) >> BIT_SHIFT_TC2DATA_8822B) & BIT_MASK_TC2DATA_8822B)
+#define BIT_SET_TC2DATA_8822B(x, v)                                            \
+	(BIT_CLEAR_TC2DATA_8822B(x) | BIT_TC2DATA_8822B(v))
+
+/* 2 REG_TC3_CTRL_8822B */
+#define BIT_TC3INT_EN_8822B BIT(26)
+#define BIT_TC3MODE_8822B BIT(25)
+#define BIT_TC3EN_8822B BIT(24)
+
+#define BIT_SHIFT_TC3DATA_8822B 0
+#define BIT_MASK_TC3DATA_8822B 0xffffff
+#define BIT_TC3DATA_8822B(x)                                                   \
+	(((x) & BIT_MASK_TC3DATA_8822B) << BIT_SHIFT_TC3DATA_8822B)
+#define BITS_TC3DATA_8822B (BIT_MASK_TC3DATA_8822B << BIT_SHIFT_TC3DATA_8822B)
+#define BIT_CLEAR_TC3DATA_8822B(x) ((x) & (~BITS_TC3DATA_8822B))
+#define BIT_GET_TC3DATA_8822B(x)                                               \
+	(((x) >> BIT_SHIFT_TC3DATA_8822B) & BIT_MASK_TC3DATA_8822B)
+#define BIT_SET_TC3DATA_8822B(x, v)                                            \
+	(BIT_CLEAR_TC3DATA_8822B(x) | BIT_TC3DATA_8822B(v))
+
+/* 2 REG_TC4_CTRL_8822B */
+#define BIT_TC4INT_EN_8822B BIT(26)
+#define BIT_TC4MODE_8822B BIT(25)
+#define BIT_TC4EN_8822B BIT(24)
+
+#define BIT_SHIFT_TC4DATA_8822B 0
+#define BIT_MASK_TC4DATA_8822B 0xffffff
+#define BIT_TC4DATA_8822B(x)                                                   \
+	(((x) & BIT_MASK_TC4DATA_8822B) << BIT_SHIFT_TC4DATA_8822B)
+#define BITS_TC4DATA_8822B (BIT_MASK_TC4DATA_8822B << BIT_SHIFT_TC4DATA_8822B)
+#define BIT_CLEAR_TC4DATA_8822B(x) ((x) & (~BITS_TC4DATA_8822B))
+#define BIT_GET_TC4DATA_8822B(x)                                               \
+	(((x) >> BIT_SHIFT_TC4DATA_8822B) & BIT_MASK_TC4DATA_8822B)
+#define BIT_SET_TC4DATA_8822B(x, v)                                            \
+	(BIT_CLEAR_TC4DATA_8822B(x) | BIT_TC4DATA_8822B(v))
+
+/* 2 REG_TCUNIT_BASE_8822B */
+
+#define BIT_SHIFT_TCUNIT_BASE_8822B 0
+#define BIT_MASK_TCUNIT_BASE_8822B 0x3fff
+#define BIT_TCUNIT_BASE_8822B(x)                                               \
+	(((x) & BIT_MASK_TCUNIT_BASE_8822B) << BIT_SHIFT_TCUNIT_BASE_8822B)
+#define BITS_TCUNIT_BASE_8822B                                                 \
+	(BIT_MASK_TCUNIT_BASE_8822B << BIT_SHIFT_TCUNIT_BASE_8822B)
+#define BIT_CLEAR_TCUNIT_BASE_8822B(x) ((x) & (~BITS_TCUNIT_BASE_8822B))
+#define BIT_GET_TCUNIT_BASE_8822B(x)                                           \
+	(((x) >> BIT_SHIFT_TCUNIT_BASE_8822B) & BIT_MASK_TCUNIT_BASE_8822B)
+#define BIT_SET_TCUNIT_BASE_8822B(x, v)                                        \
+	(BIT_CLEAR_TCUNIT_BASE_8822B(x) | BIT_TCUNIT_BASE_8822B(v))
+
+/* 2 REG_TC5_CTRL_8822B */
+#define BIT_TC5INT_EN_8822B BIT(26)
+#define BIT_TC5MODE_8822B BIT(25)
+#define BIT_TC5EN_8822B BIT(24)
+
+#define BIT_SHIFT_TC5DATA_8822B 0
+#define BIT_MASK_TC5DATA_8822B 0xffffff
+#define BIT_TC5DATA_8822B(x)                                                   \
+	(((x) & BIT_MASK_TC5DATA_8822B) << BIT_SHIFT_TC5DATA_8822B)
+#define BITS_TC5DATA_8822B (BIT_MASK_TC5DATA_8822B << BIT_SHIFT_TC5DATA_8822B)
+#define BIT_CLEAR_TC5DATA_8822B(x) ((x) & (~BITS_TC5DATA_8822B))
+#define BIT_GET_TC5DATA_8822B(x)                                               \
+	(((x) >> BIT_SHIFT_TC5DATA_8822B) & BIT_MASK_TC5DATA_8822B)
+#define BIT_SET_TC5DATA_8822B(x, v)                                            \
+	(BIT_CLEAR_TC5DATA_8822B(x) | BIT_TC5DATA_8822B(v))
+
+/* 2 REG_TC6_CTRL_8822B */
+#define BIT_TC6INT_EN_8822B BIT(26)
+#define BIT_TC6MODE_8822B BIT(25)
+#define BIT_TC6EN_8822B BIT(24)
+
+#define BIT_SHIFT_TC6DATA_8822B 0
+#define BIT_MASK_TC6DATA_8822B 0xffffff
+#define BIT_TC6DATA_8822B(x)                                                   \
+	(((x) & BIT_MASK_TC6DATA_8822B) << BIT_SHIFT_TC6DATA_8822B)
+#define BITS_TC6DATA_8822B (BIT_MASK_TC6DATA_8822B << BIT_SHIFT_TC6DATA_8822B)
+#define BIT_CLEAR_TC6DATA_8822B(x) ((x) & (~BITS_TC6DATA_8822B))
+#define BIT_GET_TC6DATA_8822B(x)                                               \
+	(((x) >> BIT_SHIFT_TC6DATA_8822B) & BIT_MASK_TC6DATA_8822B)
+#define BIT_SET_TC6DATA_8822B(x, v)                                            \
+	(BIT_CLEAR_TC6DATA_8822B(x) | BIT_TC6DATA_8822B(v))
+
+/* 2 REG_MBIST_FAIL_8822B */
+
+#define BIT_SHIFT_8051_MBIST_FAIL_8822B 26
+#define BIT_MASK_8051_MBIST_FAIL_8822B 0x7
+#define BIT_8051_MBIST_FAIL_8822B(x)                                           \
+	(((x) & BIT_MASK_8051_MBIST_FAIL_8822B)                                \
+	 << BIT_SHIFT_8051_MBIST_FAIL_8822B)
+#define BITS_8051_MBIST_FAIL_8822B                                             \
+	(BIT_MASK_8051_MBIST_FAIL_8822B << BIT_SHIFT_8051_MBIST_FAIL_8822B)
+#define BIT_CLEAR_8051_MBIST_FAIL_8822B(x) ((x) & (~BITS_8051_MBIST_FAIL_8822B))
+#define BIT_GET_8051_MBIST_FAIL_8822B(x)                                       \
+	(((x) >> BIT_SHIFT_8051_MBIST_FAIL_8822B) &                            \
+	 BIT_MASK_8051_MBIST_FAIL_8822B)
+#define BIT_SET_8051_MBIST_FAIL_8822B(x, v)                                    \
+	(BIT_CLEAR_8051_MBIST_FAIL_8822B(x) | BIT_8051_MBIST_FAIL_8822B(v))
+
+#define BIT_SHIFT_USB_MBIST_FAIL_8822B 24
+#define BIT_MASK_USB_MBIST_FAIL_8822B 0x3
+#define BIT_USB_MBIST_FAIL_8822B(x)                                            \
+	(((x) & BIT_MASK_USB_MBIST_FAIL_8822B)                                 \
+	 << BIT_SHIFT_USB_MBIST_FAIL_8822B)
+#define BITS_USB_MBIST_FAIL_8822B                                              \
+	(BIT_MASK_USB_MBIST_FAIL_8822B << BIT_SHIFT_USB_MBIST_FAIL_8822B)
+#define BIT_CLEAR_USB_MBIST_FAIL_8822B(x) ((x) & (~BITS_USB_MBIST_FAIL_8822B))
+#define BIT_GET_USB_MBIST_FAIL_8822B(x)                                        \
+	(((x) >> BIT_SHIFT_USB_MBIST_FAIL_8822B) &                             \
+	 BIT_MASK_USB_MBIST_FAIL_8822B)
+#define BIT_SET_USB_MBIST_FAIL_8822B(x, v)                                     \
+	(BIT_CLEAR_USB_MBIST_FAIL_8822B(x) | BIT_USB_MBIST_FAIL_8822B(v))
+
+#define BIT_SHIFT_PCIE_MBIST_FAIL_8822B 16
+#define BIT_MASK_PCIE_MBIST_FAIL_8822B 0x3f
+#define BIT_PCIE_MBIST_FAIL_8822B(x)                                           \
+	(((x) & BIT_MASK_PCIE_MBIST_FAIL_8822B)                                \
+	 << BIT_SHIFT_PCIE_MBIST_FAIL_8822B)
+#define BITS_PCIE_MBIST_FAIL_8822B                                             \
+	(BIT_MASK_PCIE_MBIST_FAIL_8822B << BIT_SHIFT_PCIE_MBIST_FAIL_8822B)
+#define BIT_CLEAR_PCIE_MBIST_FAIL_8822B(x) ((x) & (~BITS_PCIE_MBIST_FAIL_8822B))
+#define BIT_GET_PCIE_MBIST_FAIL_8822B(x)                                       \
+	(((x) >> BIT_SHIFT_PCIE_MBIST_FAIL_8822B) &                            \
+	 BIT_MASK_PCIE_MBIST_FAIL_8822B)
+#define BIT_SET_PCIE_MBIST_FAIL_8822B(x, v)                                    \
+	(BIT_CLEAR_PCIE_MBIST_FAIL_8822B(x) | BIT_PCIE_MBIST_FAIL_8822B(v))
+
+#define BIT_SHIFT_MAC_MBIST_FAIL_8822B 0
+#define BIT_MASK_MAC_MBIST_FAIL_8822B 0xfff
+#define BIT_MAC_MBIST_FAIL_8822B(x)                                            \
+	(((x) & BIT_MASK_MAC_MBIST_FAIL_8822B)                                 \
+	 << BIT_SHIFT_MAC_MBIST_FAIL_8822B)
+#define BITS_MAC_MBIST_FAIL_8822B                                              \
+	(BIT_MASK_MAC_MBIST_FAIL_8822B << BIT_SHIFT_MAC_MBIST_FAIL_8822B)
+#define BIT_CLEAR_MAC_MBIST_FAIL_8822B(x) ((x) & (~BITS_MAC_MBIST_FAIL_8822B))
+#define BIT_GET_MAC_MBIST_FAIL_8822B(x)                                        \
+	(((x) >> BIT_SHIFT_MAC_MBIST_FAIL_8822B) &                             \
+	 BIT_MASK_MAC_MBIST_FAIL_8822B)
+#define BIT_SET_MAC_MBIST_FAIL_8822B(x, v)                                     \
+	(BIT_CLEAR_MAC_MBIST_FAIL_8822B(x) | BIT_MAC_MBIST_FAIL_8822B(v))
+
+/* 2 REG_MBIST_START_PAUSE_8822B */
+
+#define BIT_SHIFT_8051_MBIST_START_PAUSE_8822B 26
+#define BIT_MASK_8051_MBIST_START_PAUSE_8822B 0x7
+#define BIT_8051_MBIST_START_PAUSE_8822B(x)                                    \
+	(((x) & BIT_MASK_8051_MBIST_START_PAUSE_8822B)                         \
+	 << BIT_SHIFT_8051_MBIST_START_PAUSE_8822B)
+#define BITS_8051_MBIST_START_PAUSE_8822B                                      \
+	(BIT_MASK_8051_MBIST_START_PAUSE_8822B                                 \
+	 << BIT_SHIFT_8051_MBIST_START_PAUSE_8822B)
+#define BIT_CLEAR_8051_MBIST_START_PAUSE_8822B(x)                              \
+	((x) & (~BITS_8051_MBIST_START_PAUSE_8822B))
+#define BIT_GET_8051_MBIST_START_PAUSE_8822B(x)                                \
+	(((x) >> BIT_SHIFT_8051_MBIST_START_PAUSE_8822B) &                     \
+	 BIT_MASK_8051_MBIST_START_PAUSE_8822B)
+#define BIT_SET_8051_MBIST_START_PAUSE_8822B(x, v)                             \
+	(BIT_CLEAR_8051_MBIST_START_PAUSE_8822B(x) |                           \
+	 BIT_8051_MBIST_START_PAUSE_8822B(v))
+
+#define BIT_SHIFT_USB_MBIST_START_PAUSE_8822B 24
+#define BIT_MASK_USB_MBIST_START_PAUSE_8822B 0x3
+#define BIT_USB_MBIST_START_PAUSE_8822B(x)                                     \
+	(((x) & BIT_MASK_USB_MBIST_START_PAUSE_8822B)                          \
+	 << BIT_SHIFT_USB_MBIST_START_PAUSE_8822B)
+#define BITS_USB_MBIST_START_PAUSE_8822B                                       \
+	(BIT_MASK_USB_MBIST_START_PAUSE_8822B                                  \
+	 << BIT_SHIFT_USB_MBIST_START_PAUSE_8822B)
+#define BIT_CLEAR_USB_MBIST_START_PAUSE_8822B(x)                               \
+	((x) & (~BITS_USB_MBIST_START_PAUSE_8822B))
+#define BIT_GET_USB_MBIST_START_PAUSE_8822B(x)                                 \
+	(((x) >> BIT_SHIFT_USB_MBIST_START_PAUSE_8822B) &                      \
+	 BIT_MASK_USB_MBIST_START_PAUSE_8822B)
+#define BIT_SET_USB_MBIST_START_PAUSE_8822B(x, v)                              \
+	(BIT_CLEAR_USB_MBIST_START_PAUSE_8822B(x) |                            \
+	 BIT_USB_MBIST_START_PAUSE_8822B(v))
+
+#define BIT_SHIFT_PCIE_MBIST_START_PAUSE_8822B 16
+#define BIT_MASK_PCIE_MBIST_START_PAUSE_8822B 0x3f
+#define BIT_PCIE_MBIST_START_PAUSE_8822B(x)                                    \
+	(((x) & BIT_MASK_PCIE_MBIST_START_PAUSE_8822B)                         \
+	 << BIT_SHIFT_PCIE_MBIST_START_PAUSE_8822B)
+#define BITS_PCIE_MBIST_START_PAUSE_8822B                                      \
+	(BIT_MASK_PCIE_MBIST_START_PAUSE_8822B                                 \
+	 << BIT_SHIFT_PCIE_MBIST_START_PAUSE_8822B)
+#define BIT_CLEAR_PCIE_MBIST_START_PAUSE_8822B(x)                              \
+	((x) & (~BITS_PCIE_MBIST_START_PAUSE_8822B))
+#define BIT_GET_PCIE_MBIST_START_PAUSE_8822B(x)                                \
+	(((x) >> BIT_SHIFT_PCIE_MBIST_START_PAUSE_8822B) &                     \
+	 BIT_MASK_PCIE_MBIST_START_PAUSE_8822B)
+#define BIT_SET_PCIE_MBIST_START_PAUSE_8822B(x, v)                             \
+	(BIT_CLEAR_PCIE_MBIST_START_PAUSE_8822B(x) |                           \
+	 BIT_PCIE_MBIST_START_PAUSE_8822B(v))
+
+#define BIT_SHIFT_MAC_MBIST_START_PAUSE_8822B 0
+#define BIT_MASK_MAC_MBIST_START_PAUSE_8822B 0xfff
+#define BIT_MAC_MBIST_START_PAUSE_8822B(x)                                     \
+	(((x) & BIT_MASK_MAC_MBIST_START_PAUSE_8822B)                          \
+	 << BIT_SHIFT_MAC_MBIST_START_PAUSE_8822B)
+#define BITS_MAC_MBIST_START_PAUSE_8822B                                       \
+	(BIT_MASK_MAC_MBIST_START_PAUSE_8822B                                  \
+	 << BIT_SHIFT_MAC_MBIST_START_PAUSE_8822B)
+#define BIT_CLEAR_MAC_MBIST_START_PAUSE_8822B(x)                               \
+	((x) & (~BITS_MAC_MBIST_START_PAUSE_8822B))
+#define BIT_GET_MAC_MBIST_START_PAUSE_8822B(x)                                 \
+	(((x) >> BIT_SHIFT_MAC_MBIST_START_PAUSE_8822B) &                      \
+	 BIT_MASK_MAC_MBIST_START_PAUSE_8822B)
+#define BIT_SET_MAC_MBIST_START_PAUSE_8822B(x, v)                              \
+	(BIT_CLEAR_MAC_MBIST_START_PAUSE_8822B(x) |                            \
+	 BIT_MAC_MBIST_START_PAUSE_8822B(v))
+
+/* 2 REG_MBIST_DONE_8822B */
+
+#define BIT_SHIFT_8051_MBIST_DONE_8822B 26
+#define BIT_MASK_8051_MBIST_DONE_8822B 0x7
+#define BIT_8051_MBIST_DONE_8822B(x)                                           \
+	(((x) & BIT_MASK_8051_MBIST_DONE_8822B)                                \
+	 << BIT_SHIFT_8051_MBIST_DONE_8822B)
+#define BITS_8051_MBIST_DONE_8822B                                             \
+	(BIT_MASK_8051_MBIST_DONE_8822B << BIT_SHIFT_8051_MBIST_DONE_8822B)
+#define BIT_CLEAR_8051_MBIST_DONE_8822B(x) ((x) & (~BITS_8051_MBIST_DONE_8822B))
+#define BIT_GET_8051_MBIST_DONE_8822B(x)                                       \
+	(((x) >> BIT_SHIFT_8051_MBIST_DONE_8822B) &                            \
+	 BIT_MASK_8051_MBIST_DONE_8822B)
+#define BIT_SET_8051_MBIST_DONE_8822B(x, v)                                    \
+	(BIT_CLEAR_8051_MBIST_DONE_8822B(x) | BIT_8051_MBIST_DONE_8822B(v))
+
+#define BIT_SHIFT_USB_MBIST_DONE_8822B 24
+#define BIT_MASK_USB_MBIST_DONE_8822B 0x3
+#define BIT_USB_MBIST_DONE_8822B(x)                                            \
+	(((x) & BIT_MASK_USB_MBIST_DONE_8822B)                                 \
+	 << BIT_SHIFT_USB_MBIST_DONE_8822B)
+#define BITS_USB_MBIST_DONE_8822B                                              \
+	(BIT_MASK_USB_MBIST_DONE_8822B << BIT_SHIFT_USB_MBIST_DONE_8822B)
+#define BIT_CLEAR_USB_MBIST_DONE_8822B(x) ((x) & (~BITS_USB_MBIST_DONE_8822B))
+#define BIT_GET_USB_MBIST_DONE_8822B(x)                                        \
+	(((x) >> BIT_SHIFT_USB_MBIST_DONE_8822B) &                             \
+	 BIT_MASK_USB_MBIST_DONE_8822B)
+#define BIT_SET_USB_MBIST_DONE_8822B(x, v)                                     \
+	(BIT_CLEAR_USB_MBIST_DONE_8822B(x) | BIT_USB_MBIST_DONE_8822B(v))
+
+#define BIT_SHIFT_PCIE_MBIST_DONE_8822B 16
+#define BIT_MASK_PCIE_MBIST_DONE_8822B 0x3f
+#define BIT_PCIE_MBIST_DONE_8822B(x)                                           \
+	(((x) & BIT_MASK_PCIE_MBIST_DONE_8822B)                                \
+	 << BIT_SHIFT_PCIE_MBIST_DONE_8822B)
+#define BITS_PCIE_MBIST_DONE_8822B                                             \
+	(BIT_MASK_PCIE_MBIST_DONE_8822B << BIT_SHIFT_PCIE_MBIST_DONE_8822B)
+#define BIT_CLEAR_PCIE_MBIST_DONE_8822B(x) ((x) & (~BITS_PCIE_MBIST_DONE_8822B))
+#define BIT_GET_PCIE_MBIST_DONE_8822B(x)                                       \
+	(((x) >> BIT_SHIFT_PCIE_MBIST_DONE_8822B) &                            \
+	 BIT_MASK_PCIE_MBIST_DONE_8822B)
+#define BIT_SET_PCIE_MBIST_DONE_8822B(x, v)                                    \
+	(BIT_CLEAR_PCIE_MBIST_DONE_8822B(x) | BIT_PCIE_MBIST_DONE_8822B(v))
+
+#define BIT_SHIFT_MAC_MBIST_DONE_8822B 0
+#define BIT_MASK_MAC_MBIST_DONE_8822B 0xfff
+#define BIT_MAC_MBIST_DONE_8822B(x)                                            \
+	(((x) & BIT_MASK_MAC_MBIST_DONE_8822B)                                 \
+	 << BIT_SHIFT_MAC_MBIST_DONE_8822B)
+#define BITS_MAC_MBIST_DONE_8822B                                              \
+	(BIT_MASK_MAC_MBIST_DONE_8822B << BIT_SHIFT_MAC_MBIST_DONE_8822B)
+#define BIT_CLEAR_MAC_MBIST_DONE_8822B(x) ((x) & (~BITS_MAC_MBIST_DONE_8822B))
+#define BIT_GET_MAC_MBIST_DONE_8822B(x)                                        \
+	(((x) >> BIT_SHIFT_MAC_MBIST_DONE_8822B) &                             \
+	 BIT_MASK_MAC_MBIST_DONE_8822B)
+#define BIT_SET_MAC_MBIST_DONE_8822B(x, v)                                     \
+	(BIT_CLEAR_MAC_MBIST_DONE_8822B(x) | BIT_MAC_MBIST_DONE_8822B(v))
+
+/* 2 REG_MBIST_FAIL_NRML_8822B */
+
+#define BIT_SHIFT_MBIST_FAIL_NRML_8822B 0
+#define BIT_MASK_MBIST_FAIL_NRML_8822B 0xffffffffL
+#define BIT_MBIST_FAIL_NRML_8822B(x)                                           \
+	(((x) & BIT_MASK_MBIST_FAIL_NRML_8822B)                                \
+	 << BIT_SHIFT_MBIST_FAIL_NRML_8822B)
+#define BITS_MBIST_FAIL_NRML_8822B                                             \
+	(BIT_MASK_MBIST_FAIL_NRML_8822B << BIT_SHIFT_MBIST_FAIL_NRML_8822B)
+#define BIT_CLEAR_MBIST_FAIL_NRML_8822B(x) ((x) & (~BITS_MBIST_FAIL_NRML_8822B))
+#define BIT_GET_MBIST_FAIL_NRML_8822B(x)                                       \
+	(((x) >> BIT_SHIFT_MBIST_FAIL_NRML_8822B) &                            \
+	 BIT_MASK_MBIST_FAIL_NRML_8822B)
+#define BIT_SET_MBIST_FAIL_NRML_8822B(x, v)                                    \
+	(BIT_CLEAR_MBIST_FAIL_NRML_8822B(x) | BIT_MBIST_FAIL_NRML_8822B(v))
+
+/* 2 REG_AES_DECRPT_DATA_8822B */
+
+#define BIT_SHIFT_IPS_CFG_ADDR_8822B 0
+#define BIT_MASK_IPS_CFG_ADDR_8822B 0xff
+#define BIT_IPS_CFG_ADDR_8822B(x)                                              \
+	(((x) & BIT_MASK_IPS_CFG_ADDR_8822B) << BIT_SHIFT_IPS_CFG_ADDR_8822B)
+#define BITS_IPS_CFG_ADDR_8822B                                                \
+	(BIT_MASK_IPS_CFG_ADDR_8822B << BIT_SHIFT_IPS_CFG_ADDR_8822B)
+#define BIT_CLEAR_IPS_CFG_ADDR_8822B(x) ((x) & (~BITS_IPS_CFG_ADDR_8822B))
+#define BIT_GET_IPS_CFG_ADDR_8822B(x)                                          \
+	(((x) >> BIT_SHIFT_IPS_CFG_ADDR_8822B) & BIT_MASK_IPS_CFG_ADDR_8822B)
+#define BIT_SET_IPS_CFG_ADDR_8822B(x, v)                                       \
+	(BIT_CLEAR_IPS_CFG_ADDR_8822B(x) | BIT_IPS_CFG_ADDR_8822B(v))
+
+/* 2 REG_AES_DECRPT_CFG_8822B */
+
+#define BIT_SHIFT_IPS_CFG_DATA_8822B 0
+#define BIT_MASK_IPS_CFG_DATA_8822B 0xffffffffL
+#define BIT_IPS_CFG_DATA_8822B(x)                                              \
+	(((x) & BIT_MASK_IPS_CFG_DATA_8822B) << BIT_SHIFT_IPS_CFG_DATA_8822B)
+#define BITS_IPS_CFG_DATA_8822B                                                \
+	(BIT_MASK_IPS_CFG_DATA_8822B << BIT_SHIFT_IPS_CFG_DATA_8822B)
+#define BIT_CLEAR_IPS_CFG_DATA_8822B(x) ((x) & (~BITS_IPS_CFG_DATA_8822B))
+#define BIT_GET_IPS_CFG_DATA_8822B(x)                                          \
+	(((x) >> BIT_SHIFT_IPS_CFG_DATA_8822B) & BIT_MASK_IPS_CFG_DATA_8822B)
+#define BIT_SET_IPS_CFG_DATA_8822B(x, v)                                       \
+	(BIT_CLEAR_IPS_CFG_DATA_8822B(x) | BIT_IPS_CFG_DATA_8822B(v))
+
+/* 2 REG_NOT_VALID_8822B */
+
+/* 2 REG_NOT_VALID_8822B */
+
+/* 2 REG_TMETER_8822B */
+#define BIT_TEMP_VALID_8822B BIT(31)
+
+#define BIT_SHIFT_TEMP_VALUE_8822B 24
+#define BIT_MASK_TEMP_VALUE_8822B 0x3f
+#define BIT_TEMP_VALUE_8822B(x)                                                \
+	(((x) & BIT_MASK_TEMP_VALUE_8822B) << BIT_SHIFT_TEMP_VALUE_8822B)
+#define BITS_TEMP_VALUE_8822B                                                  \
+	(BIT_MASK_TEMP_VALUE_8822B << BIT_SHIFT_TEMP_VALUE_8822B)
+#define BIT_CLEAR_TEMP_VALUE_8822B(x) ((x) & (~BITS_TEMP_VALUE_8822B))
+#define BIT_GET_TEMP_VALUE_8822B(x)                                            \
+	(((x) >> BIT_SHIFT_TEMP_VALUE_8822B) & BIT_MASK_TEMP_VALUE_8822B)
+#define BIT_SET_TEMP_VALUE_8822B(x, v)                                         \
+	(BIT_CLEAR_TEMP_VALUE_8822B(x) | BIT_TEMP_VALUE_8822B(v))
+
+#define BIT_SHIFT_REG_TMETER_TIMER_8822B 8
+#define BIT_MASK_REG_TMETER_TIMER_8822B 0xfff
+#define BIT_REG_TMETER_TIMER_8822B(x)                                          \
+	(((x) & BIT_MASK_REG_TMETER_TIMER_8822B)                               \
+	 << BIT_SHIFT_REG_TMETER_TIMER_8822B)
+#define BITS_REG_TMETER_TIMER_8822B                                            \
+	(BIT_MASK_REG_TMETER_TIMER_8822B << BIT_SHIFT_REG_TMETER_TIMER_8822B)
+#define BIT_CLEAR_REG_TMETER_TIMER_8822B(x)                                    \
+	((x) & (~BITS_REG_TMETER_TIMER_8822B))
+#define BIT_GET_REG_TMETER_TIMER_8822B(x)                                      \
+	(((x) >> BIT_SHIFT_REG_TMETER_TIMER_8822B) &                           \
+	 BIT_MASK_REG_TMETER_TIMER_8822B)
+#define BIT_SET_REG_TMETER_TIMER_8822B(x, v)                                   \
+	(BIT_CLEAR_REG_TMETER_TIMER_8822B(x) | BIT_REG_TMETER_TIMER_8822B(v))
+
+#define BIT_SHIFT_REG_TEMP_DELTA_8822B 2
+#define BIT_MASK_REG_TEMP_DELTA_8822B 0x3f
+#define BIT_REG_TEMP_DELTA_8822B(x)                                            \
+	(((x) & BIT_MASK_REG_TEMP_DELTA_8822B)                                 \
+	 << BIT_SHIFT_REG_TEMP_DELTA_8822B)
+#define BITS_REG_TEMP_DELTA_8822B                                              \
+	(BIT_MASK_REG_TEMP_DELTA_8822B << BIT_SHIFT_REG_TEMP_DELTA_8822B)
+#define BIT_CLEAR_REG_TEMP_DELTA_8822B(x) ((x) & (~BITS_REG_TEMP_DELTA_8822B))
+#define BIT_GET_REG_TEMP_DELTA_8822B(x)                                        \
+	(((x) >> BIT_SHIFT_REG_TEMP_DELTA_8822B) &                             \
+	 BIT_MASK_REG_TEMP_DELTA_8822B)
+#define BIT_SET_REG_TEMP_DELTA_8822B(x, v)                                     \
+	(BIT_CLEAR_REG_TEMP_DELTA_8822B(x) | BIT_REG_TEMP_DELTA_8822B(v))
+
+#define BIT_REG_TMETER_EN_8822B BIT(0)
+
+/* 2 REG_OSC_32K_CTRL_8822B */
+
+#define BIT_SHIFT_OSC_32K_CLKGEN_0_8822B 16
+#define BIT_MASK_OSC_32K_CLKGEN_0_8822B 0xffff
+#define BIT_OSC_32K_CLKGEN_0_8822B(x)                                          \
+	(((x) & BIT_MASK_OSC_32K_CLKGEN_0_8822B)                               \
+	 << BIT_SHIFT_OSC_32K_CLKGEN_0_8822B)
+#define BITS_OSC_32K_CLKGEN_0_8822B                                            \
+	(BIT_MASK_OSC_32K_CLKGEN_0_8822B << BIT_SHIFT_OSC_32K_CLKGEN_0_8822B)
+#define BIT_CLEAR_OSC_32K_CLKGEN_0_8822B(x)                                    \
+	((x) & (~BITS_OSC_32K_CLKGEN_0_8822B))
+#define BIT_GET_OSC_32K_CLKGEN_0_8822B(x)                                      \
+	(((x) >> BIT_SHIFT_OSC_32K_CLKGEN_0_8822B) &                           \
+	 BIT_MASK_OSC_32K_CLKGEN_0_8822B)
+#define BIT_SET_OSC_32K_CLKGEN_0_8822B(x, v)                                   \
+	(BIT_CLEAR_OSC_32K_CLKGEN_0_8822B(x) | BIT_OSC_32K_CLKGEN_0_8822B(v))
+
+#define BIT_SHIFT_OSC_32K_RES_COMP_8822B 4
+#define BIT_MASK_OSC_32K_RES_COMP_8822B 0x3
+#define BIT_OSC_32K_RES_COMP_8822B(x)                                          \
+	(((x) & BIT_MASK_OSC_32K_RES_COMP_8822B)                               \
+	 << BIT_SHIFT_OSC_32K_RES_COMP_8822B)
+#define BITS_OSC_32K_RES_COMP_8822B                                            \
+	(BIT_MASK_OSC_32K_RES_COMP_8822B << BIT_SHIFT_OSC_32K_RES_COMP_8822B)
+#define BIT_CLEAR_OSC_32K_RES_COMP_8822B(x)                                    \
+	((x) & (~BITS_OSC_32K_RES_COMP_8822B))
+#define BIT_GET_OSC_32K_RES_COMP_8822B(x)                                      \
+	(((x) >> BIT_SHIFT_OSC_32K_RES_COMP_8822B) &                           \
+	 BIT_MASK_OSC_32K_RES_COMP_8822B)
+#define BIT_SET_OSC_32K_RES_COMP_8822B(x, v)                                   \
+	(BIT_CLEAR_OSC_32K_RES_COMP_8822B(x) | BIT_OSC_32K_RES_COMP_8822B(v))
+
+#define BIT_OSC_32K_OUT_SEL_8822B BIT(3)
+#define BIT_ISO_WL_2_OSC_32K_8822B BIT(1)
+#define BIT_POW_CKGEN_8822B BIT(0)
+
+/* 2 REG_32K_CAL_REG1_8822B */
+#define BIT_CAL_32K_REG_WR_8822B BIT(31)
+#define BIT_CAL_32K_DBG_SEL_8822B BIT(22)
+
+#define BIT_SHIFT_CAL_32K_REG_ADDR_8822B 16
+#define BIT_MASK_CAL_32K_REG_ADDR_8822B 0x3f
+#define BIT_CAL_32K_REG_ADDR_8822B(x)                                          \
+	(((x) & BIT_MASK_CAL_32K_REG_ADDR_8822B)                               \
+	 << BIT_SHIFT_CAL_32K_REG_ADDR_8822B)
+#define BITS_CAL_32K_REG_ADDR_8822B                                            \
+	(BIT_MASK_CAL_32K_REG_ADDR_8822B << BIT_SHIFT_CAL_32K_REG_ADDR_8822B)
+#define BIT_CLEAR_CAL_32K_REG_ADDR_8822B(x)                                    \
+	((x) & (~BITS_CAL_32K_REG_ADDR_8822B))
+#define BIT_GET_CAL_32K_REG_ADDR_8822B(x)                                      \
+	(((x) >> BIT_SHIFT_CAL_32K_REG_ADDR_8822B) &                           \
+	 BIT_MASK_CAL_32K_REG_ADDR_8822B)
+#define BIT_SET_CAL_32K_REG_ADDR_8822B(x, v)                                   \
+	(BIT_CLEAR_CAL_32K_REG_ADDR_8822B(x) | BIT_CAL_32K_REG_ADDR_8822B(v))
+
+#define BIT_SHIFT_CAL_32K_REG_DATA_8822B 0
+#define BIT_MASK_CAL_32K_REG_DATA_8822B 0xffff
+#define BIT_CAL_32K_REG_DATA_8822B(x)                                          \
+	(((x) & BIT_MASK_CAL_32K_REG_DATA_8822B)                               \
+	 << BIT_SHIFT_CAL_32K_REG_DATA_8822B)
+#define BITS_CAL_32K_REG_DATA_8822B                                            \
+	(BIT_MASK_CAL_32K_REG_DATA_8822B << BIT_SHIFT_CAL_32K_REG_DATA_8822B)
+#define BIT_CLEAR_CAL_32K_REG_DATA_8822B(x)                                    \
+	((x) & (~BITS_CAL_32K_REG_DATA_8822B))
+#define BIT_GET_CAL_32K_REG_DATA_8822B(x)                                      \
+	(((x) >> BIT_SHIFT_CAL_32K_REG_DATA_8822B) &                           \
+	 BIT_MASK_CAL_32K_REG_DATA_8822B)
+#define BIT_SET_CAL_32K_REG_DATA_8822B(x, v)                                   \
+	(BIT_CLEAR_CAL_32K_REG_DATA_8822B(x) | BIT_CAL_32K_REG_DATA_8822B(v))
+
+/* 2 REG_NOT_VALID_8822B */
+
+/* 2 REG_C2HEVT_8822B */
+
+#define BIT_SHIFT_C2HEVT_MSG_V1_8822B 0
+#define BIT_MASK_C2HEVT_MSG_V1_8822B 0xffffffffL
+#define BIT_C2HEVT_MSG_V1_8822B(x)                                             \
+	(((x) & BIT_MASK_C2HEVT_MSG_V1_8822B) << BIT_SHIFT_C2HEVT_MSG_V1_8822B)
+#define BITS_C2HEVT_MSG_V1_8822B                                               \
+	(BIT_MASK_C2HEVT_MSG_V1_8822B << BIT_SHIFT_C2HEVT_MSG_V1_8822B)
+#define BIT_CLEAR_C2HEVT_MSG_V1_8822B(x) ((x) & (~BITS_C2HEVT_MSG_V1_8822B))
+#define BIT_GET_C2HEVT_MSG_V1_8822B(x)                                         \
+	(((x) >> BIT_SHIFT_C2HEVT_MSG_V1_8822B) & BIT_MASK_C2HEVT_MSG_V1_8822B)
+#define BIT_SET_C2HEVT_MSG_V1_8822B(x, v)                                      \
+	(BIT_CLEAR_C2HEVT_MSG_V1_8822B(x) | BIT_C2HEVT_MSG_V1_8822B(v))
+
+/* 2 REG_C2HEVT_1_8822B */
+
+#define BIT_SHIFT_C2HEVT_MSG_1_8822B 0
+#define BIT_MASK_C2HEVT_MSG_1_8822B 0xffffffffL
+#define BIT_C2HEVT_MSG_1_8822B(x)                                              \
+	(((x) & BIT_MASK_C2HEVT_MSG_1_8822B) << BIT_SHIFT_C2HEVT_MSG_1_8822B)
+#define BITS_C2HEVT_MSG_1_8822B                                                \
+	(BIT_MASK_C2HEVT_MSG_1_8822B << BIT_SHIFT_C2HEVT_MSG_1_8822B)
+#define BIT_CLEAR_C2HEVT_MSG_1_8822B(x) ((x) & (~BITS_C2HEVT_MSG_1_8822B))
+#define BIT_GET_C2HEVT_MSG_1_8822B(x)                                          \
+	(((x) >> BIT_SHIFT_C2HEVT_MSG_1_8822B) & BIT_MASK_C2HEVT_MSG_1_8822B)
+#define BIT_SET_C2HEVT_MSG_1_8822B(x, v)                                       \
+	(BIT_CLEAR_C2HEVT_MSG_1_8822B(x) | BIT_C2HEVT_MSG_1_8822B(v))
+
+/* 2 REG_C2HEVT_2_8822B */
+
+#define BIT_SHIFT_C2HEVT_MSG_2_8822B 0
+#define BIT_MASK_C2HEVT_MSG_2_8822B 0xffffffffL
+#define BIT_C2HEVT_MSG_2_8822B(x)                                              \
+	(((x) & BIT_MASK_C2HEVT_MSG_2_8822B) << BIT_SHIFT_C2HEVT_MSG_2_8822B)
+#define BITS_C2HEVT_MSG_2_8822B                                                \
+	(BIT_MASK_C2HEVT_MSG_2_8822B << BIT_SHIFT_C2HEVT_MSG_2_8822B)
+#define BIT_CLEAR_C2HEVT_MSG_2_8822B(x) ((x) & (~BITS_C2HEVT_MSG_2_8822B))
+#define BIT_GET_C2HEVT_MSG_2_8822B(x)                                          \
+	(((x) >> BIT_SHIFT_C2HEVT_MSG_2_8822B) & BIT_MASK_C2HEVT_MSG_2_8822B)
+#define BIT_SET_C2HEVT_MSG_2_8822B(x, v)                                       \
+	(BIT_CLEAR_C2HEVT_MSG_2_8822B(x) | BIT_C2HEVT_MSG_2_8822B(v))
+
+/* 2 REG_C2HEVT_3_8822B */
+
+#define BIT_SHIFT_C2HEVT_MSG_3_8822B 0
+#define BIT_MASK_C2HEVT_MSG_3_8822B 0xffffffffL
+#define BIT_C2HEVT_MSG_3_8822B(x)                                              \
+	(((x) & BIT_MASK_C2HEVT_MSG_3_8822B) << BIT_SHIFT_C2HEVT_MSG_3_8822B)
+#define BITS_C2HEVT_MSG_3_8822B                                                \
+	(BIT_MASK_C2HEVT_MSG_3_8822B << BIT_SHIFT_C2HEVT_MSG_3_8822B)
+#define BIT_CLEAR_C2HEVT_MSG_3_8822B(x) ((x) & (~BITS_C2HEVT_MSG_3_8822B))
+#define BIT_GET_C2HEVT_MSG_3_8822B(x)                                          \
+	(((x) >> BIT_SHIFT_C2HEVT_MSG_3_8822B) & BIT_MASK_C2HEVT_MSG_3_8822B)
+#define BIT_SET_C2HEVT_MSG_3_8822B(x, v)                                       \
+	(BIT_CLEAR_C2HEVT_MSG_3_8822B(x) | BIT_C2HEVT_MSG_3_8822B(v))
+
+/* 2 REG_SW_DEFINED_PAGE1_8822B */
+
+#define BIT_SHIFT_SW_DEFINED_PAGE1_8822B 0
+#define BIT_MASK_SW_DEFINED_PAGE1_8822B 0xffffffffffffffffL
+#define BIT_SW_DEFINED_PAGE1_8822B(x)                                          \
+	(((x) & BIT_MASK_SW_DEFINED_PAGE1_8822B)                               \
+	 << BIT_SHIFT_SW_DEFINED_PAGE1_8822B)
+#define BITS_SW_DEFINED_PAGE1_8822B                                            \
+	(BIT_MASK_SW_DEFINED_PAGE1_8822B << BIT_SHIFT_SW_DEFINED_PAGE1_8822B)
+#define BIT_CLEAR_SW_DEFINED_PAGE1_8822B(x)                                    \
+	((x) & (~BITS_SW_DEFINED_PAGE1_8822B))
+#define BIT_GET_SW_DEFINED_PAGE1_8822B(x)                                      \
+	(((x) >> BIT_SHIFT_SW_DEFINED_PAGE1_8822B) &                           \
+	 BIT_MASK_SW_DEFINED_PAGE1_8822B)
+#define BIT_SET_SW_DEFINED_PAGE1_8822B(x, v)                                   \
+	(BIT_CLEAR_SW_DEFINED_PAGE1_8822B(x) | BIT_SW_DEFINED_PAGE1_8822B(v))
+
+/* 2 REG_MCUTST_I_8822B */
+
+#define BIT_SHIFT_MCUDMSG_I_8822B 0
+#define BIT_MASK_MCUDMSG_I_8822B 0xffffffffL
+#define BIT_MCUDMSG_I_8822B(x)                                                 \
+	(((x) & BIT_MASK_MCUDMSG_I_8822B) << BIT_SHIFT_MCUDMSG_I_8822B)
+#define BITS_MCUDMSG_I_8822B                                                   \
+	(BIT_MASK_MCUDMSG_I_8822B << BIT_SHIFT_MCUDMSG_I_8822B)
+#define BIT_CLEAR_MCUDMSG_I_8822B(x) ((x) & (~BITS_MCUDMSG_I_8822B))
+#define BIT_GET_MCUDMSG_I_8822B(x)                                             \
+	(((x) >> BIT_SHIFT_MCUDMSG_I_8822B) & BIT_MASK_MCUDMSG_I_8822B)
+#define BIT_SET_MCUDMSG_I_8822B(x, v)                                          \
+	(BIT_CLEAR_MCUDMSG_I_8822B(x) | BIT_MCUDMSG_I_8822B(v))
+
+/* 2 REG_MCUTST_II_8822B */
+
+#define BIT_SHIFT_MCUDMSG_II_8822B 0
+#define BIT_MASK_MCUDMSG_II_8822B 0xffffffffL
+#define BIT_MCUDMSG_II_8822B(x)                                                \
+	(((x) & BIT_MASK_MCUDMSG_II_8822B) << BIT_SHIFT_MCUDMSG_II_8822B)
+#define BITS_MCUDMSG_II_8822B                                                  \
+	(BIT_MASK_MCUDMSG_II_8822B << BIT_SHIFT_MCUDMSG_II_8822B)
+#define BIT_CLEAR_MCUDMSG_II_8822B(x) ((x) & (~BITS_MCUDMSG_II_8822B))
+#define BIT_GET_MCUDMSG_II_8822B(x)                                            \
+	(((x) >> BIT_SHIFT_MCUDMSG_II_8822B) & BIT_MASK_MCUDMSG_II_8822B)
+#define BIT_SET_MCUDMSG_II_8822B(x, v)                                         \
+	(BIT_CLEAR_MCUDMSG_II_8822B(x) | BIT_MCUDMSG_II_8822B(v))
+
+/* 2 REG_FMETHR_8822B */
+#define BIT_FMSG_INT_8822B BIT(31)
+
+#define BIT_SHIFT_FW_MSG_8822B 0
+#define BIT_MASK_FW_MSG_8822B 0xffffffffL
+#define BIT_FW_MSG_8822B(x)                                                    \
+	(((x) & BIT_MASK_FW_MSG_8822B) << BIT_SHIFT_FW_MSG_8822B)
+#define BITS_FW_MSG_8822B (BIT_MASK_FW_MSG_8822B << BIT_SHIFT_FW_MSG_8822B)
+#define BIT_CLEAR_FW_MSG_8822B(x) ((x) & (~BITS_FW_MSG_8822B))
+#define BIT_GET_FW_MSG_8822B(x)                                                \
+	(((x) >> BIT_SHIFT_FW_MSG_8822B) & BIT_MASK_FW_MSG_8822B)
+#define BIT_SET_FW_MSG_8822B(x, v)                                             \
+	(BIT_CLEAR_FW_MSG_8822B(x) | BIT_FW_MSG_8822B(v))
+
+/* 2 REG_HMETFR_8822B */
+
+#define BIT_SHIFT_HRCV_MSG_8822B 24
+#define BIT_MASK_HRCV_MSG_8822B 0xff
+#define BIT_HRCV_MSG_8822B(x)                                                  \
+	(((x) & BIT_MASK_HRCV_MSG_8822B) << BIT_SHIFT_HRCV_MSG_8822B)
+#define BITS_HRCV_MSG_8822B                                                    \
+	(BIT_MASK_HRCV_MSG_8822B << BIT_SHIFT_HRCV_MSG_8822B)
+#define BIT_CLEAR_HRCV_MSG_8822B(x) ((x) & (~BITS_HRCV_MSG_8822B))
+#define BIT_GET_HRCV_MSG_8822B(x)                                              \
+	(((x) >> BIT_SHIFT_HRCV_MSG_8822B) & BIT_MASK_HRCV_MSG_8822B)
+#define BIT_SET_HRCV_MSG_8822B(x, v)                                           \
+	(BIT_CLEAR_HRCV_MSG_8822B(x) | BIT_HRCV_MSG_8822B(v))
+
+#define BIT_INT_BOX3_8822B BIT(3)
+#define BIT_INT_BOX2_8822B BIT(2)
+#define BIT_INT_BOX1_8822B BIT(1)
+#define BIT_INT_BOX0_8822B BIT(0)
+
+/* 2 REG_HMEBOX0_8822B */
+
+#define BIT_SHIFT_HOST_MSG_0_8822B 0
+#define BIT_MASK_HOST_MSG_0_8822B 0xffffffffL
+#define BIT_HOST_MSG_0_8822B(x)                                                \
+	(((x) & BIT_MASK_HOST_MSG_0_8822B) << BIT_SHIFT_HOST_MSG_0_8822B)
+#define BITS_HOST_MSG_0_8822B                                                  \
+	(BIT_MASK_HOST_MSG_0_8822B << BIT_SHIFT_HOST_MSG_0_8822B)
+#define BIT_CLEAR_HOST_MSG_0_8822B(x) ((x) & (~BITS_HOST_MSG_0_8822B))
+#define BIT_GET_HOST_MSG_0_8822B(x)                                            \
+	(((x) >> BIT_SHIFT_HOST_MSG_0_8822B) & BIT_MASK_HOST_MSG_0_8822B)
+#define BIT_SET_HOST_MSG_0_8822B(x, v)                                         \
+	(BIT_CLEAR_HOST_MSG_0_8822B(x) | BIT_HOST_MSG_0_8822B(v))
+
+/* 2 REG_HMEBOX1_8822B */
+
+#define BIT_SHIFT_HOST_MSG_1_8822B 0
+#define BIT_MASK_HOST_MSG_1_8822B 0xffffffffL
+#define BIT_HOST_MSG_1_8822B(x)                                                \
+	(((x) & BIT_MASK_HOST_MSG_1_8822B) << BIT_SHIFT_HOST_MSG_1_8822B)
+#define BITS_HOST_MSG_1_8822B                                                  \
+	(BIT_MASK_HOST_MSG_1_8822B << BIT_SHIFT_HOST_MSG_1_8822B)
+#define BIT_CLEAR_HOST_MSG_1_8822B(x) ((x) & (~BITS_HOST_MSG_1_8822B))
+#define BIT_GET_HOST_MSG_1_8822B(x)                                            \
+	(((x) >> BIT_SHIFT_HOST_MSG_1_8822B) & BIT_MASK_HOST_MSG_1_8822B)
+#define BIT_SET_HOST_MSG_1_8822B(x, v)                                         \
+	(BIT_CLEAR_HOST_MSG_1_8822B(x) | BIT_HOST_MSG_1_8822B(v))
+
+/* 2 REG_HMEBOX2_8822B */
+
+#define BIT_SHIFT_HOST_MSG_2_8822B 0
+#define BIT_MASK_HOST_MSG_2_8822B 0xffffffffL
+#define BIT_HOST_MSG_2_8822B(x)                                                \
+	(((x) & BIT_MASK_HOST_MSG_2_8822B) << BIT_SHIFT_HOST_MSG_2_8822B)
+#define BITS_HOST_MSG_2_8822B                                                  \
+	(BIT_MASK_HOST_MSG_2_8822B << BIT_SHIFT_HOST_MSG_2_8822B)
+#define BIT_CLEAR_HOST_MSG_2_8822B(x) ((x) & (~BITS_HOST_MSG_2_8822B))
+#define BIT_GET_HOST_MSG_2_8822B(x)                                            \
+	(((x) >> BIT_SHIFT_HOST_MSG_2_8822B) & BIT_MASK_HOST_MSG_2_8822B)
+#define BIT_SET_HOST_MSG_2_8822B(x, v)                                         \
+	(BIT_CLEAR_HOST_MSG_2_8822B(x) | BIT_HOST_MSG_2_8822B(v))
+
+/* 2 REG_HMEBOX3_8822B */
+
+#define BIT_SHIFT_HOST_MSG_3_8822B 0
+#define BIT_MASK_HOST_MSG_3_8822B 0xffffffffL
+#define BIT_HOST_MSG_3_8822B(x)                                                \
+	(((x) & BIT_MASK_HOST_MSG_3_8822B) << BIT_SHIFT_HOST_MSG_3_8822B)
+#define BITS_HOST_MSG_3_8822B                                                  \
+	(BIT_MASK_HOST_MSG_3_8822B << BIT_SHIFT_HOST_MSG_3_8822B)
+#define BIT_CLEAR_HOST_MSG_3_8822B(x) ((x) & (~BITS_HOST_MSG_3_8822B))
+#define BIT_GET_HOST_MSG_3_8822B(x)                                            \
+	(((x) >> BIT_SHIFT_HOST_MSG_3_8822B) & BIT_MASK_HOST_MSG_3_8822B)
+#define BIT_SET_HOST_MSG_3_8822B(x, v)                                         \
+	(BIT_CLEAR_HOST_MSG_3_8822B(x) | BIT_HOST_MSG_3_8822B(v))
+
+/* 2 REG_LLT_INIT_8822B */
+
+#define BIT_SHIFT_LLTE_RWM_8822B 30
+#define BIT_MASK_LLTE_RWM_8822B 0x3
+#define BIT_LLTE_RWM_8822B(x)                                                  \
+	(((x) & BIT_MASK_LLTE_RWM_8822B) << BIT_SHIFT_LLTE_RWM_8822B)
+#define BITS_LLTE_RWM_8822B                                                    \
+	(BIT_MASK_LLTE_RWM_8822B << BIT_SHIFT_LLTE_RWM_8822B)
+#define BIT_CLEAR_LLTE_RWM_8822B(x) ((x) & (~BITS_LLTE_RWM_8822B))
+#define BIT_GET_LLTE_RWM_8822B(x)                                              \
+	(((x) >> BIT_SHIFT_LLTE_RWM_8822B) & BIT_MASK_LLTE_RWM_8822B)
+#define BIT_SET_LLTE_RWM_8822B(x, v)                                           \
+	(BIT_CLEAR_LLTE_RWM_8822B(x) | BIT_LLTE_RWM_8822B(v))
+
+#define BIT_SHIFT_LLTINI_PDATA_V1_8822B 16
+#define BIT_MASK_LLTINI_PDATA_V1_8822B 0xfff
+#define BIT_LLTINI_PDATA_V1_8822B(x)                                           \
+	(((x) & BIT_MASK_LLTINI_PDATA_V1_8822B)                                \
+	 << BIT_SHIFT_LLTINI_PDATA_V1_8822B)
+#define BITS_LLTINI_PDATA_V1_8822B                                             \
+	(BIT_MASK_LLTINI_PDATA_V1_8822B << BIT_SHIFT_LLTINI_PDATA_V1_8822B)
+#define BIT_CLEAR_LLTINI_PDATA_V1_8822B(x) ((x) & (~BITS_LLTINI_PDATA_V1_8822B))
+#define BIT_GET_LLTINI_PDATA_V1_8822B(x)                                       \
+	(((x) >> BIT_SHIFT_LLTINI_PDATA_V1_8822B) &                            \
+	 BIT_MASK_LLTINI_PDATA_V1_8822B)
+#define BIT_SET_LLTINI_PDATA_V1_8822B(x, v)                                    \
+	(BIT_CLEAR_LLTINI_PDATA_V1_8822B(x) | BIT_LLTINI_PDATA_V1_8822B(v))
+
+#define BIT_SHIFT_LLTINI_HDATA_V1_8822B 0
+#define BIT_MASK_LLTINI_HDATA_V1_8822B 0xfff
+#define BIT_LLTINI_HDATA_V1_8822B(x)                                           \
+	(((x) & BIT_MASK_LLTINI_HDATA_V1_8822B)                                \
+	 << BIT_SHIFT_LLTINI_HDATA_V1_8822B)
+#define BITS_LLTINI_HDATA_V1_8822B                                             \
+	(BIT_MASK_LLTINI_HDATA_V1_8822B << BIT_SHIFT_LLTINI_HDATA_V1_8822B)
+#define BIT_CLEAR_LLTINI_HDATA_V1_8822B(x) ((x) & (~BITS_LLTINI_HDATA_V1_8822B))
+#define BIT_GET_LLTINI_HDATA_V1_8822B(x)                                       \
+	(((x) >> BIT_SHIFT_LLTINI_HDATA_V1_8822B) &                            \
+	 BIT_MASK_LLTINI_HDATA_V1_8822B)
+#define BIT_SET_LLTINI_HDATA_V1_8822B(x, v)                                    \
+	(BIT_CLEAR_LLTINI_HDATA_V1_8822B(x) | BIT_LLTINI_HDATA_V1_8822B(v))
+
+/* 2 REG_LLT_INIT_ADDR_8822B */
+
+#define BIT_SHIFT_LLTINI_ADDR_V1_8822B 0
+#define BIT_MASK_LLTINI_ADDR_V1_8822B 0xfff
+#define BIT_LLTINI_ADDR_V1_8822B(x)                                            \
+	(((x) & BIT_MASK_LLTINI_ADDR_V1_8822B)                                 \
+	 << BIT_SHIFT_LLTINI_ADDR_V1_8822B)
+#define BITS_LLTINI_ADDR_V1_8822B                                              \
+	(BIT_MASK_LLTINI_ADDR_V1_8822B << BIT_SHIFT_LLTINI_ADDR_V1_8822B)
+#define BIT_CLEAR_LLTINI_ADDR_V1_8822B(x) ((x) & (~BITS_LLTINI_ADDR_V1_8822B))
+#define BIT_GET_LLTINI_ADDR_V1_8822B(x)                                        \
+	(((x) >> BIT_SHIFT_LLTINI_ADDR_V1_8822B) &                             \
+	 BIT_MASK_LLTINI_ADDR_V1_8822B)
+#define BIT_SET_LLTINI_ADDR_V1_8822B(x, v)                                     \
+	(BIT_CLEAR_LLTINI_ADDR_V1_8822B(x) | BIT_LLTINI_ADDR_V1_8822B(v))
+
+/* 2 REG_BB_ACCESS_CTRL_8822B */
+
+#define BIT_SHIFT_BB_WRITE_READ_8822B 30
+#define BIT_MASK_BB_WRITE_READ_8822B 0x3
+#define BIT_BB_WRITE_READ_8822B(x)                                             \
+	(((x) & BIT_MASK_BB_WRITE_READ_8822B) << BIT_SHIFT_BB_WRITE_READ_8822B)
+#define BITS_BB_WRITE_READ_8822B                                               \
+	(BIT_MASK_BB_WRITE_READ_8822B << BIT_SHIFT_BB_WRITE_READ_8822B)
+#define BIT_CLEAR_BB_WRITE_READ_8822B(x) ((x) & (~BITS_BB_WRITE_READ_8822B))
+#define BIT_GET_BB_WRITE_READ_8822B(x)                                         \
+	(((x) >> BIT_SHIFT_BB_WRITE_READ_8822B) & BIT_MASK_BB_WRITE_READ_8822B)
+#define BIT_SET_BB_WRITE_READ_8822B(x, v)                                      \
+	(BIT_CLEAR_BB_WRITE_READ_8822B(x) | BIT_BB_WRITE_READ_8822B(v))
+
+#define BIT_SHIFT_BB_WRITE_EN_8822B 12
+#define BIT_MASK_BB_WRITE_EN_8822B 0xf
+#define BIT_BB_WRITE_EN_8822B(x)                                               \
+	(((x) & BIT_MASK_BB_WRITE_EN_8822B) << BIT_SHIFT_BB_WRITE_EN_8822B)
+#define BITS_BB_WRITE_EN_8822B                                                 \
+	(BIT_MASK_BB_WRITE_EN_8822B << BIT_SHIFT_BB_WRITE_EN_8822B)
+#define BIT_CLEAR_BB_WRITE_EN_8822B(x) ((x) & (~BITS_BB_WRITE_EN_8822B))
+#define BIT_GET_BB_WRITE_EN_8822B(x)                                           \
+	(((x) >> BIT_SHIFT_BB_WRITE_EN_8822B) & BIT_MASK_BB_WRITE_EN_8822B)
+#define BIT_SET_BB_WRITE_EN_8822B(x, v)                                        \
+	(BIT_CLEAR_BB_WRITE_EN_8822B(x) | BIT_BB_WRITE_EN_8822B(v))
+
+#define BIT_SHIFT_BB_ADDR_8822B 2
+#define BIT_MASK_BB_ADDR_8822B 0x1ff
+#define BIT_BB_ADDR_8822B(x)                                                   \
+	(((x) & BIT_MASK_BB_ADDR_8822B) << BIT_SHIFT_BB_ADDR_8822B)
+#define BITS_BB_ADDR_8822B (BIT_MASK_BB_ADDR_8822B << BIT_SHIFT_BB_ADDR_8822B)
+#define BIT_CLEAR_BB_ADDR_8822B(x) ((x) & (~BITS_BB_ADDR_8822B))
+#define BIT_GET_BB_ADDR_8822B(x)                                               \
+	(((x) >> BIT_SHIFT_BB_ADDR_8822B) & BIT_MASK_BB_ADDR_8822B)
+#define BIT_SET_BB_ADDR_8822B(x, v)                                            \
+	(BIT_CLEAR_BB_ADDR_8822B(x) | BIT_BB_ADDR_8822B(v))
+
+#define BIT_BB_ERRACC_8822B BIT(0)
+
+/* 2 REG_BB_ACCESS_DATA_8822B */
+
+#define BIT_SHIFT_BB_DATA_8822B 0
+#define BIT_MASK_BB_DATA_8822B 0xffffffffL
+#define BIT_BB_DATA_8822B(x)                                                   \
+	(((x) & BIT_MASK_BB_DATA_8822B) << BIT_SHIFT_BB_DATA_8822B)
+#define BITS_BB_DATA_8822B (BIT_MASK_BB_DATA_8822B << BIT_SHIFT_BB_DATA_8822B)
+#define BIT_CLEAR_BB_DATA_8822B(x) ((x) & (~BITS_BB_DATA_8822B))
+#define BIT_GET_BB_DATA_8822B(x)                                               \
+	(((x) >> BIT_SHIFT_BB_DATA_8822B) & BIT_MASK_BB_DATA_8822B)
+#define BIT_SET_BB_DATA_8822B(x, v)                                            \
+	(BIT_CLEAR_BB_DATA_8822B(x) | BIT_BB_DATA_8822B(v))
+
+/* 2 REG_HMEBOX_E0_8822B */
+
+#define BIT_SHIFT_HMEBOX_E0_8822B 0
+#define BIT_MASK_HMEBOX_E0_8822B 0xffffffffL
+#define BIT_HMEBOX_E0_8822B(x)                                                 \
+	(((x) & BIT_MASK_HMEBOX_E0_8822B) << BIT_SHIFT_HMEBOX_E0_8822B)
+#define BITS_HMEBOX_E0_8822B                                                   \
+	(BIT_MASK_HMEBOX_E0_8822B << BIT_SHIFT_HMEBOX_E0_8822B)
+#define BIT_CLEAR_HMEBOX_E0_8822B(x) ((x) & (~BITS_HMEBOX_E0_8822B))
+#define BIT_GET_HMEBOX_E0_8822B(x)                                             \
+	(((x) >> BIT_SHIFT_HMEBOX_E0_8822B) & BIT_MASK_HMEBOX_E0_8822B)
+#define BIT_SET_HMEBOX_E0_8822B(x, v)                                          \
+	(BIT_CLEAR_HMEBOX_E0_8822B(x) | BIT_HMEBOX_E0_8822B(v))
+
+/* 2 REG_HMEBOX_E1_8822B */
+
+#define BIT_SHIFT_HMEBOX_E1_8822B 0
+#define BIT_MASK_HMEBOX_E1_8822B 0xffffffffL
+#define BIT_HMEBOX_E1_8822B(x)                                                 \
+	(((x) & BIT_MASK_HMEBOX_E1_8822B) << BIT_SHIFT_HMEBOX_E1_8822B)
+#define BITS_HMEBOX_E1_8822B                                                   \
+	(BIT_MASK_HMEBOX_E1_8822B << BIT_SHIFT_HMEBOX_E1_8822B)
+#define BIT_CLEAR_HMEBOX_E1_8822B(x) ((x) & (~BITS_HMEBOX_E1_8822B))
+#define BIT_GET_HMEBOX_E1_8822B(x)                                             \
+	(((x) >> BIT_SHIFT_HMEBOX_E1_8822B) & BIT_MASK_HMEBOX_E1_8822B)
+#define BIT_SET_HMEBOX_E1_8822B(x, v)                                          \
+	(BIT_CLEAR_HMEBOX_E1_8822B(x) | BIT_HMEBOX_E1_8822B(v))
+
+/* 2 REG_HMEBOX_E2_8822B */
+
+#define BIT_SHIFT_HMEBOX_E2_8822B 0
+#define BIT_MASK_HMEBOX_E2_8822B 0xffffffffL
+#define BIT_HMEBOX_E2_8822B(x)                                                 \
+	(((x) & BIT_MASK_HMEBOX_E2_8822B) << BIT_SHIFT_HMEBOX_E2_8822B)
+#define BITS_HMEBOX_E2_8822B                                                   \
+	(BIT_MASK_HMEBOX_E2_8822B << BIT_SHIFT_HMEBOX_E2_8822B)
+#define BIT_CLEAR_HMEBOX_E2_8822B(x) ((x) & (~BITS_HMEBOX_E2_8822B))
+#define BIT_GET_HMEBOX_E2_8822B(x)                                             \
+	(((x) >> BIT_SHIFT_HMEBOX_E2_8822B) & BIT_MASK_HMEBOX_E2_8822B)
+#define BIT_SET_HMEBOX_E2_8822B(x, v)                                          \
+	(BIT_CLEAR_HMEBOX_E2_8822B(x) | BIT_HMEBOX_E2_8822B(v))
+
+/* 2 REG_HMEBOX_E3_8822B */
+
+#define BIT_SHIFT_HMEBOX_E3_8822B 0
+#define BIT_MASK_HMEBOX_E3_8822B 0xffffffffL
+#define BIT_HMEBOX_E3_8822B(x)                                                 \
+	(((x) & BIT_MASK_HMEBOX_E3_8822B) << BIT_SHIFT_HMEBOX_E3_8822B)
+#define BITS_HMEBOX_E3_8822B                                                   \
+	(BIT_MASK_HMEBOX_E3_8822B << BIT_SHIFT_HMEBOX_E3_8822B)
+#define BIT_CLEAR_HMEBOX_E3_8822B(x) ((x) & (~BITS_HMEBOX_E3_8822B))
+#define BIT_GET_HMEBOX_E3_8822B(x)                                             \
+	(((x) >> BIT_SHIFT_HMEBOX_E3_8822B) & BIT_MASK_HMEBOX_E3_8822B)
+#define BIT_SET_HMEBOX_E3_8822B(x, v)                                          \
+	(BIT_CLEAR_HMEBOX_E3_8822B(x) | BIT_HMEBOX_E3_8822B(v))
+
+/* 2 REG_NOT_VALID_8822B */
+
+/* 2 REG_CR_EXT_8822B */
+
+#define BIT_SHIFT_PHY_REQ_DELAY_8822B 24
+#define BIT_MASK_PHY_REQ_DELAY_8822B 0xf
+#define BIT_PHY_REQ_DELAY_8822B(x)                                             \
+	(((x) & BIT_MASK_PHY_REQ_DELAY_8822B) << BIT_SHIFT_PHY_REQ_DELAY_8822B)
+#define BITS_PHY_REQ_DELAY_8822B                                               \
+	(BIT_MASK_PHY_REQ_DELAY_8822B << BIT_SHIFT_PHY_REQ_DELAY_8822B)
+#define BIT_CLEAR_PHY_REQ_DELAY_8822B(x) ((x) & (~BITS_PHY_REQ_DELAY_8822B))
+#define BIT_GET_PHY_REQ_DELAY_8822B(x)                                         \
+	(((x) >> BIT_SHIFT_PHY_REQ_DELAY_8822B) & BIT_MASK_PHY_REQ_DELAY_8822B)
+#define BIT_SET_PHY_REQ_DELAY_8822B(x, v)                                      \
+	(BIT_CLEAR_PHY_REQ_DELAY_8822B(x) | BIT_PHY_REQ_DELAY_8822B(v))
+
+#define BIT_SPD_DOWN_8822B BIT(16)
+
+#define BIT_SHIFT_NETYPE4_8822B 4
+#define BIT_MASK_NETYPE4_8822B 0x3
+#define BIT_NETYPE4_8822B(x)                                                   \
+	(((x) & BIT_MASK_NETYPE4_8822B) << BIT_SHIFT_NETYPE4_8822B)
+#define BITS_NETYPE4_8822B (BIT_MASK_NETYPE4_8822B << BIT_SHIFT_NETYPE4_8822B)
+#define BIT_CLEAR_NETYPE4_8822B(x) ((x) & (~BITS_NETYPE4_8822B))
+#define BIT_GET_NETYPE4_8822B(x)                                               \
+	(((x) >> BIT_SHIFT_NETYPE4_8822B) & BIT_MASK_NETYPE4_8822B)
+#define BIT_SET_NETYPE4_8822B(x, v)                                            \
+	(BIT_CLEAR_NETYPE4_8822B(x) | BIT_NETYPE4_8822B(v))
+
+#define BIT_SHIFT_NETYPE3_8822B 2
+#define BIT_MASK_NETYPE3_8822B 0x3
+#define BIT_NETYPE3_8822B(x)                                                   \
+	(((x) & BIT_MASK_NETYPE3_8822B) << BIT_SHIFT_NETYPE3_8822B)
+#define BITS_NETYPE3_8822B (BIT_MASK_NETYPE3_8822B << BIT_SHIFT_NETYPE3_8822B)
+#define BIT_CLEAR_NETYPE3_8822B(x) ((x) & (~BITS_NETYPE3_8822B))
+#define BIT_GET_NETYPE3_8822B(x)                                               \
+	(((x) >> BIT_SHIFT_NETYPE3_8822B) & BIT_MASK_NETYPE3_8822B)
+#define BIT_SET_NETYPE3_8822B(x, v)                                            \
+	(BIT_CLEAR_NETYPE3_8822B(x) | BIT_NETYPE3_8822B(v))
+
+#define BIT_SHIFT_NETYPE2_8822B 0
+#define BIT_MASK_NETYPE2_8822B 0x3
+#define BIT_NETYPE2_8822B(x)                                                   \
+	(((x) & BIT_MASK_NETYPE2_8822B) << BIT_SHIFT_NETYPE2_8822B)
+#define BITS_NETYPE2_8822B (BIT_MASK_NETYPE2_8822B << BIT_SHIFT_NETYPE2_8822B)
+#define BIT_CLEAR_NETYPE2_8822B(x) ((x) & (~BITS_NETYPE2_8822B))
+#define BIT_GET_NETYPE2_8822B(x)                                               \
+	(((x) >> BIT_SHIFT_NETYPE2_8822B) & BIT_MASK_NETYPE2_8822B)
+#define BIT_SET_NETYPE2_8822B(x, v)                                            \
+	(BIT_CLEAR_NETYPE2_8822B(x) | BIT_NETYPE2_8822B(v))
+
+/* 2 REG_FWFF_8822B */
+
+#define BIT_SHIFT_PKTNUM_TH_V1_8822B 24
+#define BIT_MASK_PKTNUM_TH_V1_8822B 0xff
+#define BIT_PKTNUM_TH_V1_8822B(x)                                              \
+	(((x) & BIT_MASK_PKTNUM_TH_V1_8822B) << BIT_SHIFT_PKTNUM_TH_V1_8822B)
+#define BITS_PKTNUM_TH_V1_8822B                                                \
+	(BIT_MASK_PKTNUM_TH_V1_8822B << BIT_SHIFT_PKTNUM_TH_V1_8822B)
+#define BIT_CLEAR_PKTNUM_TH_V1_8822B(x) ((x) & (~BITS_PKTNUM_TH_V1_8822B))
+#define BIT_GET_PKTNUM_TH_V1_8822B(x)                                          \
+	(((x) >> BIT_SHIFT_PKTNUM_TH_V1_8822B) & BIT_MASK_PKTNUM_TH_V1_8822B)
+#define BIT_SET_PKTNUM_TH_V1_8822B(x, v)                                       \
+	(BIT_CLEAR_PKTNUM_TH_V1_8822B(x) | BIT_PKTNUM_TH_V1_8822B(v))
+
+#define BIT_SHIFT_TIMER_TH_8822B 16
+#define BIT_MASK_TIMER_TH_8822B 0xff
+#define BIT_TIMER_TH_8822B(x)                                                  \
+	(((x) & BIT_MASK_TIMER_TH_8822B) << BIT_SHIFT_TIMER_TH_8822B)
+#define BITS_TIMER_TH_8822B                                                    \
+	(BIT_MASK_TIMER_TH_8822B << BIT_SHIFT_TIMER_TH_8822B)
+#define BIT_CLEAR_TIMER_TH_8822B(x) ((x) & (~BITS_TIMER_TH_8822B))
+#define BIT_GET_TIMER_TH_8822B(x)                                              \
+	(((x) >> BIT_SHIFT_TIMER_TH_8822B) & BIT_MASK_TIMER_TH_8822B)
+#define BIT_SET_TIMER_TH_8822B(x, v)                                           \
+	(BIT_CLEAR_TIMER_TH_8822B(x) | BIT_TIMER_TH_8822B(v))
+
+#define BIT_SHIFT_RXPKT1ENADDR_8822B 0
+#define BIT_MASK_RXPKT1ENADDR_8822B 0xffff
+#define BIT_RXPKT1ENADDR_8822B(x)                                              \
+	(((x) & BIT_MASK_RXPKT1ENADDR_8822B) << BIT_SHIFT_RXPKT1ENADDR_8822B)
+#define BITS_RXPKT1ENADDR_8822B                                                \
+	(BIT_MASK_RXPKT1ENADDR_8822B << BIT_SHIFT_RXPKT1ENADDR_8822B)
+#define BIT_CLEAR_RXPKT1ENADDR_8822B(x) ((x) & (~BITS_RXPKT1ENADDR_8822B))
+#define BIT_GET_RXPKT1ENADDR_8822B(x)                                          \
+	(((x) >> BIT_SHIFT_RXPKT1ENADDR_8822B) & BIT_MASK_RXPKT1ENADDR_8822B)
+#define BIT_SET_RXPKT1ENADDR_8822B(x, v)                                       \
+	(BIT_CLEAR_RXPKT1ENADDR_8822B(x) | BIT_RXPKT1ENADDR_8822B(v))
+
+/* 2 REG_RXFF_PTR_V1_8822B */
+
+/* 2 REG_NOT_VALID_8822B */
+
+#define BIT_SHIFT_RXFF0_RDPTR_V2_8822B 0
+#define BIT_MASK_RXFF0_RDPTR_V2_8822B 0x3ffff
+#define BIT_RXFF0_RDPTR_V2_8822B(x)                                            \
+	(((x) & BIT_MASK_RXFF0_RDPTR_V2_8822B)                                 \
+	 << BIT_SHIFT_RXFF0_RDPTR_V2_8822B)
+#define BITS_RXFF0_RDPTR_V2_8822B                                              \
+	(BIT_MASK_RXFF0_RDPTR_V2_8822B << BIT_SHIFT_RXFF0_RDPTR_V2_8822B)
+#define BIT_CLEAR_RXFF0_RDPTR_V2_8822B(x) ((x) & (~BITS_RXFF0_RDPTR_V2_8822B))
+#define BIT_GET_RXFF0_RDPTR_V2_8822B(x)                                        \
+	(((x) >> BIT_SHIFT_RXFF0_RDPTR_V2_8822B) &                             \
+	 BIT_MASK_RXFF0_RDPTR_V2_8822B)
+#define BIT_SET_RXFF0_RDPTR_V2_8822B(x, v)                                     \
+	(BIT_CLEAR_RXFF0_RDPTR_V2_8822B(x) | BIT_RXFF0_RDPTR_V2_8822B(v))
+
+/* 2 REG_RXFF_WTR_V1_8822B */
+
+/* 2 REG_NOT_VALID_8822B */
+
+#define BIT_SHIFT_RXFF0_WTPTR_V2_8822B 0
+#define BIT_MASK_RXFF0_WTPTR_V2_8822B 0x3ffff
+#define BIT_RXFF0_WTPTR_V2_8822B(x)                                            \
+	(((x) & BIT_MASK_RXFF0_WTPTR_V2_8822B)                                 \
+	 << BIT_SHIFT_RXFF0_WTPTR_V2_8822B)
+#define BITS_RXFF0_WTPTR_V2_8822B                                              \
+	(BIT_MASK_RXFF0_WTPTR_V2_8822B << BIT_SHIFT_RXFF0_WTPTR_V2_8822B)
+#define BIT_CLEAR_RXFF0_WTPTR_V2_8822B(x) ((x) & (~BITS_RXFF0_WTPTR_V2_8822B))
+#define BIT_GET_RXFF0_WTPTR_V2_8822B(x)                                        \
+	(((x) >> BIT_SHIFT_RXFF0_WTPTR_V2_8822B) &                             \
+	 BIT_MASK_RXFF0_WTPTR_V2_8822B)
+#define BIT_SET_RXFF0_WTPTR_V2_8822B(x, v)                                     \
+	(BIT_CLEAR_RXFF0_WTPTR_V2_8822B(x) | BIT_RXFF0_WTPTR_V2_8822B(v))
+
+/* 2 REG_FE2IMR_8822B */
+#define BIT__FE4ISR__IND_MSK_8822B BIT(29)
+#define BIT_FS_TXSC_DESC_DONE_INT_EN_8822B BIT(28)
+#define BIT_FS_TXSC_BKDONE_INT_EN_8822B BIT(27)
+#define BIT_FS_TXSC_BEDONE_INT_EN_8822B BIT(26)
+#define BIT_FS_TXSC_VIDONE_INT_EN_8822B BIT(25)
+#define BIT_FS_TXSC_VODONE_INT_EN_8822B BIT(24)
+#define BIT_FS_ATIM_MB7_INT_EN_8822B BIT(23)
+#define BIT_FS_ATIM_MB6_INT_EN_8822B BIT(22)
+#define BIT_FS_ATIM_MB5_INT_EN_8822B BIT(21)
+#define BIT_FS_ATIM_MB4_INT_EN_8822B BIT(20)
+#define BIT_FS_ATIM_MB3_INT_EN_8822B BIT(19)
+#define BIT_FS_ATIM_MB2_INT_EN_8822B BIT(18)
+#define BIT_FS_ATIM_MB1_INT_EN_8822B BIT(17)
+#define BIT_FS_ATIM_MB0_INT_EN_8822B BIT(16)
+#define BIT_FS_TBTT4INT_EN_8822B BIT(11)
+#define BIT_FS_TBTT3INT_EN_8822B BIT(10)
+#define BIT_FS_TBTT2INT_EN_8822B BIT(9)
+#define BIT_FS_TBTT1INT_EN_8822B BIT(8)
+#define BIT_FS_TBTT0_MB7INT_EN_8822B BIT(7)
+#define BIT_FS_TBTT0_MB6INT_EN_8822B BIT(6)
+#define BIT_FS_TBTT0_MB5INT_EN_8822B BIT(5)
+#define BIT_FS_TBTT0_MB4INT_EN_8822B BIT(4)
+#define BIT_FS_TBTT0_MB3INT_EN_8822B BIT(3)
+#define BIT_FS_TBTT0_MB2INT_EN_8822B BIT(2)
+#define BIT_FS_TBTT0_MB1INT_EN_8822B BIT(1)
+#define BIT_FS_TBTT0_INT_EN_8822B BIT(0)
+
+/* 2 REG_FE2ISR_8822B */
+#define BIT__FE4ISR__IND_INT_8822B BIT(29)
+#define BIT_FS_TXSC_DESC_DONE_INT_8822B BIT(28)
+#define BIT_FS_TXSC_BKDONE_INT_8822B BIT(27)
+#define BIT_FS_TXSC_BEDONE_INT_8822B BIT(26)
+#define BIT_FS_TXSC_VIDONE_INT_8822B BIT(25)
+#define BIT_FS_TXSC_VODONE_INT_8822B BIT(24)
+#define BIT_FS_ATIM_MB7_INT_8822B BIT(23)
+#define BIT_FS_ATIM_MB6_INT_8822B BIT(22)
+#define BIT_FS_ATIM_MB5_INT_8822B BIT(21)
+#define BIT_FS_ATIM_MB4_INT_8822B BIT(20)
+#define BIT_FS_ATIM_MB3_INT_8822B BIT(19)
+#define BIT_FS_ATIM_MB2_INT_8822B BIT(18)
+#define BIT_FS_ATIM_MB1_INT_8822B BIT(17)
+#define BIT_FS_ATIM_MB0_INT_8822B BIT(16)
+#define BIT_FS_TBTT4INT_8822B BIT(11)
+#define BIT_FS_TBTT3INT_8822B BIT(10)
+#define BIT_FS_TBTT2INT_8822B BIT(9)
+#define BIT_FS_TBTT1INT_8822B BIT(8)
+#define BIT_FS_TBTT0_MB7INT_8822B BIT(7)
+#define BIT_FS_TBTT0_MB6INT_8822B BIT(6)
+#define BIT_FS_TBTT0_MB5INT_8822B BIT(5)
+#define BIT_FS_TBTT0_MB4INT_8822B BIT(4)
+#define BIT_FS_TBTT0_MB3INT_8822B BIT(3)
+#define BIT_FS_TBTT0_MB2INT_8822B BIT(2)
+#define BIT_FS_TBTT0_MB1INT_8822B BIT(1)
+#define BIT_FS_TBTT0_INT_8822B BIT(0)
+
+/* 2 REG_FE3IMR_8822B */
+#define BIT_FS_CLI3_MTI_BCNIVLEAR_INT__EN_8822B BIT(31)
+#define BIT_FS_CLI2_MTI_BCNIVLEAR_INT__EN_8822B BIT(30)
+#define BIT_FS_CLI1_MTI_BCNIVLEAR_INT__EN_8822B BIT(29)
+#define BIT_FS_CLI0_MTI_BCNIVLEAR_INT__EN_8822B BIT(28)
+#define BIT_FS_BCNDMA4_INT_EN_8822B BIT(27)
+#define BIT_FS_BCNDMA3_INT_EN_8822B BIT(26)
+#define BIT_FS_BCNDMA2_INT_EN_8822B BIT(25)
+#define BIT_FS_BCNDMA1_INT_EN_8822B BIT(24)
+#define BIT_FS_BCNDMA0_MB7_INT_EN_8822B BIT(23)
+#define BIT_FS_BCNDMA0_MB6_INT_EN_8822B BIT(22)
+#define BIT_FS_BCNDMA0_MB5_INT_EN_8822B BIT(21)
+#define BIT_FS_BCNDMA0_MB4_INT_EN_8822B BIT(20)
+#define BIT_FS_BCNDMA0_MB3_INT_EN_8822B BIT(19)
+#define BIT_FS_BCNDMA0_MB2_INT_EN_8822B BIT(18)
+#define BIT_FS_BCNDMA0_MB1_INT_EN_8822B BIT(17)
+#define BIT_FS_BCNDMA0_INT_EN_8822B BIT(16)
+#define BIT_FS_MTI_BCNIVLEAR_INT__EN_8822B BIT(15)
+#define BIT_FS_BCNERLY4_INT_EN_8822B BIT(11)
+#define BIT_FS_BCNERLY3_INT_EN_8822B BIT(10)
+#define BIT_FS_BCNERLY2_INT_EN_8822B BIT(9)
+#define BIT_FS_BCNERLY1_INT_EN_8822B BIT(8)
+#define BIT_FS_BCNERLY0_MB7INT_EN_8822B BIT(7)
+#define BIT_FS_BCNERLY0_MB6INT_EN_8822B BIT(6)
+#define BIT_FS_BCNERLY0_MB5INT_EN_8822B BIT(5)
+#define BIT_FS_BCNERLY0_MB4INT_EN_8822B BIT(4)
+#define BIT_FS_BCNERLY0_MB3INT_EN_8822B BIT(3)
+#define BIT_FS_BCNERLY0_MB2INT_EN_8822B BIT(2)
+#define BIT_FS_BCNERLY0_MB1INT_EN_8822B BIT(1)
+#define BIT_FS_BCNERLY0_INT_EN_8822B BIT(0)
+
+/* 2 REG_FE3ISR_8822B */
+#define BIT_FS_CLI3_MTI_BCNIVLEAR_INT_8822B BIT(31)
+#define BIT_FS_CLI2_MTI_BCNIVLEAR_INT_8822B BIT(30)
+#define BIT_FS_CLI1_MTI_BCNIVLEAR_INT_8822B BIT(29)
+#define BIT_FS_CLI0_MTI_BCNIVLEAR_INT_8822B BIT(28)
+#define BIT_FS_BCNDMA4_INT_8822B BIT(27)
+#define BIT_FS_BCNDMA3_INT_8822B BIT(26)
+#define BIT_FS_BCNDMA2_INT_8822B BIT(25)
+#define BIT_FS_BCNDMA1_INT_8822B BIT(24)
+#define BIT_FS_BCNDMA0_MB7_INT_8822B BIT(23)
+#define BIT_FS_BCNDMA0_MB6_INT_8822B BIT(22)
+#define BIT_FS_BCNDMA0_MB5_INT_8822B BIT(21)
+#define BIT_FS_BCNDMA0_MB4_INT_8822B BIT(20)
+#define BIT_FS_BCNDMA0_MB3_INT_8822B BIT(19)
+#define BIT_FS_BCNDMA0_MB2_INT_8822B BIT(18)
+#define BIT_FS_BCNDMA0_MB1_INT_8822B BIT(17)
+#define BIT_FS_BCNDMA0_INT_8822B BIT(16)
+#define BIT_FS_MTI_BCNIVLEAR_INT_8822B BIT(15)
+#define BIT_FS_BCNERLY4_INT_8822B BIT(11)
+#define BIT_FS_BCNERLY3_INT_8822B BIT(10)
+#define BIT_FS_BCNERLY2_INT_8822B BIT(9)
+#define BIT_FS_BCNERLY1_INT_8822B BIT(8)
+#define BIT_FS_BCNERLY0_MB7INT_8822B BIT(7)
+#define BIT_FS_BCNERLY0_MB6INT_8822B BIT(6)
+#define BIT_FS_BCNERLY0_MB5INT_8822B BIT(5)
+#define BIT_FS_BCNERLY0_MB4INT_8822B BIT(4)
+#define BIT_FS_BCNERLY0_MB3INT_8822B BIT(3)
+#define BIT_FS_BCNERLY0_MB2INT_8822B BIT(2)
+#define BIT_FS_BCNERLY0_MB1INT_8822B BIT(1)
+#define BIT_FS_BCNERLY0_INT_8822B BIT(0)
+
+/* 2 REG_FE4IMR_8822B */
+#define BIT_FS_CLI3_TXPKTIN_INT_EN_8822B BIT(19)
+#define BIT_FS_CLI2_TXPKTIN_INT_EN_8822B BIT(18)
+#define BIT_FS_CLI1_TXPKTIN_INT_EN_8822B BIT(17)
+#define BIT_FS_CLI0_TXPKTIN_INT_EN_8822B BIT(16)
+#define BIT_FS_CLI3_RX_UMD0_INT_EN_8822B BIT(15)
+#define BIT_FS_CLI3_RX_UMD1_INT_EN_8822B BIT(14)
+#define BIT_FS_CLI3_RX_BMD0_INT_EN_8822B BIT(13)
+#define BIT_FS_CLI3_RX_BMD1_INT_EN_8822B BIT(12)
+#define BIT_FS_CLI2_RX_UMD0_INT_EN_8822B BIT(11)
+#define BIT_FS_CLI2_RX_UMD1_INT_EN_8822B BIT(10)
+#define BIT_FS_CLI2_RX_BMD0_INT_EN_8822B BIT(9)
+#define BIT_FS_CLI2_RX_BMD1_INT_EN_8822B BIT(8)
+#define BIT_FS_CLI1_RX_UMD0_INT_EN_8822B BIT(7)
+#define BIT_FS_CLI1_RX_UMD1_INT_EN_8822B BIT(6)
+#define BIT_FS_CLI1_RX_BMD0_INT_EN_8822B BIT(5)
+#define BIT_FS_CLI1_RX_BMD1_INT_EN_8822B BIT(4)
+#define BIT_FS_CLI0_RX_UMD0_INT_EN_8822B BIT(3)
+#define BIT_FS_CLI0_RX_UMD1_INT_EN_8822B BIT(2)
+#define BIT_FS_CLI0_RX_BMD0_INT_EN_8822B BIT(1)
+#define BIT_FS_CLI0_RX_BMD1_INT_EN_8822B BIT(0)
+
+/* 2 REG_FE4ISR_8822B */
+#define BIT_FS_CLI3_TXPKTIN_INT_8822B BIT(19)
+#define BIT_FS_CLI2_TXPKTIN_INT_8822B BIT(18)
+#define BIT_FS_CLI1_TXPKTIN_INT_8822B BIT(17)
+#define BIT_FS_CLI0_TXPKTIN_INT_8822B BIT(16)
+#define BIT_FS_CLI3_RX_UMD0_INT_8822B BIT(15)
+#define BIT_FS_CLI3_RX_UMD1_INT_8822B BIT(14)
+#define BIT_FS_CLI3_RX_BMD0_INT_8822B BIT(13)
+#define BIT_FS_CLI3_RX_BMD1_INT_8822B BIT(12)
+#define BIT_FS_CLI2_RX_UMD0_INT_8822B BIT(11)
+#define BIT_FS_CLI2_RX_UMD1_INT_8822B BIT(10)
+#define BIT_FS_CLI2_RX_BMD0_INT_8822B BIT(9)
+#define BIT_FS_CLI2_RX_BMD1_INT_8822B BIT(8)
+#define BIT_FS_CLI1_RX_UMD0_INT_8822B BIT(7)
+#define BIT_FS_CLI1_RX_UMD1_INT_8822B BIT(6)
+#define BIT_FS_CLI1_RX_BMD0_INT_8822B BIT(5)
+#define BIT_FS_CLI1_RX_BMD1_INT_8822B BIT(4)
+#define BIT_FS_CLI0_RX_UMD0_INT_8822B BIT(3)
+#define BIT_FS_CLI0_RX_UMD1_INT_8822B BIT(2)
+#define BIT_FS_CLI0_RX_BMD0_INT_8822B BIT(1)
+#define BIT_FS_CLI0_RX_BMD1_INT_8822B BIT(0)
+
+/* 2 REG_FT1IMR_8822B */
+#define BIT__FT2ISR__IND_MSK_8822B BIT(30)
+#define BIT_FTM_PTT_INT_EN_8822B BIT(29)
+#define BIT_RXFTMREQ_INT_EN_8822B BIT(28)
+#define BIT_RXFTM_INT_EN_8822B BIT(27)
+#define BIT_TXFTM_INT_EN_8822B BIT(26)
+#define BIT_FS_H2C_CMD_OK_INT_EN_8822B BIT(25)
+#define BIT_FS_H2C_CMD_FULL_INT_EN_8822B BIT(24)
+#define BIT_FS_MACID_PWRCHANGE5_INT_EN_8822B BIT(23)
+#define BIT_FS_MACID_PWRCHANGE4_INT_EN_8822B BIT(22)
+#define BIT_FS_MACID_PWRCHANGE3_INT_EN_8822B BIT(21)
+#define BIT_FS_MACID_PWRCHANGE2_INT_EN_8822B BIT(20)
+#define BIT_FS_MACID_PWRCHANGE1_INT_EN_8822B BIT(19)
+#define BIT_FS_MACID_PWRCHANGE0_INT_EN_8822B BIT(18)
+#define BIT_FS_CTWEND2_INT_EN_8822B BIT(17)
+#define BIT_FS_CTWEND1_INT_EN_8822B BIT(16)
+#define BIT_FS_CTWEND0_INT_EN_8822B BIT(15)
+#define BIT_FS_TX_NULL1_INT_EN_8822B BIT(14)
+#define BIT_FS_TX_NULL0_INT_EN_8822B BIT(13)
+#define BIT_FS_TSF_BIT32_TOGGLE_EN_8822B BIT(12)
+#define BIT_FS_P2P_RFON2_INT_EN_8822B BIT(11)
+#define BIT_FS_P2P_RFOFF2_INT_EN_8822B BIT(10)
+#define BIT_FS_P2P_RFON1_INT_EN_8822B BIT(9)
+#define BIT_FS_P2P_RFOFF1_INT_EN_8822B BIT(8)
+#define BIT_FS_P2P_RFON0_INT_EN_8822B BIT(7)
+#define BIT_FS_P2P_RFOFF0_INT_EN_8822B BIT(6)
+#define BIT_FS_RX_UAPSDMD1_EN_8822B BIT(5)
+#define BIT_FS_RX_UAPSDMD0_EN_8822B BIT(4)
+#define BIT_FS_TRIGGER_PKT_EN_8822B BIT(3)
+#define BIT_FS_EOSP_INT_EN_8822B BIT(2)
+#define BIT_FS_RPWM2_INT_EN_8822B BIT(1)
+#define BIT_FS_RPWM_INT_EN_8822B BIT(0)
+
+/* 2 REG_FT1ISR_8822B */
+#define BIT__FT2ISR__IND_INT_8822B BIT(30)
+#define BIT_FTM_PTT_INT_8822B BIT(29)
+#define BIT_RXFTMREQ_INT_8822B BIT(28)
+#define BIT_RXFTM_INT_8822B BIT(27)
+#define BIT_TXFTM_INT_8822B BIT(26)
+#define BIT_FS_H2C_CMD_OK_INT_8822B BIT(25)
+#define BIT_FS_H2C_CMD_FULL_INT_8822B BIT(24)
+#define BIT_FS_MACID_PWRCHANGE5_INT_8822B BIT(23)
+#define BIT_FS_MACID_PWRCHANGE4_INT_8822B BIT(22)
+#define BIT_FS_MACID_PWRCHANGE3_INT_8822B BIT(21)
+#define BIT_FS_MACID_PWRCHANGE2_INT_8822B BIT(20)
+#define BIT_FS_MACID_PWRCHANGE1_INT_8822B BIT(19)
+#define BIT_FS_MACID_PWRCHANGE0_INT_8822B BIT(18)
+#define BIT_FS_CTWEND2_INT_8822B BIT(17)
+#define BIT_FS_CTWEND1_INT_8822B BIT(16)
+#define BIT_FS_CTWEND0_INT_8822B BIT(15)
+#define BIT_FS_TX_NULL1_INT_8822B BIT(14)
+#define BIT_FS_TX_NULL0_INT_8822B BIT(13)
+#define BIT_FS_TSF_BIT32_TOGGLE_INT_8822B BIT(12)
+#define BIT_FS_P2P_RFON2_INT_8822B BIT(11)
+#define BIT_FS_P2P_RFOFF2_INT_8822B BIT(10)
+#define BIT_FS_P2P_RFON1_INT_8822B BIT(9)
+#define BIT_FS_P2P_RFOFF1_INT_8822B BIT(8)
+#define BIT_FS_P2P_RFON0_INT_8822B BIT(7)
+#define BIT_FS_P2P_RFOFF0_INT_8822B BIT(6)
+#define BIT_FS_RX_UAPSDMD1_INT_8822B BIT(5)
+#define BIT_FS_RX_UAPSDMD0_INT_8822B BIT(4)
+#define BIT_FS_TRIGGER_PKT_INT_8822B BIT(3)
+#define BIT_FS_EOSP_INT_8822B BIT(2)
+#define BIT_FS_RPWM2_INT_8822B BIT(1)
+#define BIT_FS_RPWM_INT_8822B BIT(0)
+
+/* 2 REG_SPWR0_8822B */
+
+#define BIT_SHIFT_MID_31TO0_8822B 0
+#define BIT_MASK_MID_31TO0_8822B 0xffffffffL
+#define BIT_MID_31TO0_8822B(x)                                                 \
+	(((x) & BIT_MASK_MID_31TO0_8822B) << BIT_SHIFT_MID_31TO0_8822B)
+#define BITS_MID_31TO0_8822B                                                   \
+	(BIT_MASK_MID_31TO0_8822B << BIT_SHIFT_MID_31TO0_8822B)
+#define BIT_CLEAR_MID_31TO0_8822B(x) ((x) & (~BITS_MID_31TO0_8822B))
+#define BIT_GET_MID_31TO0_8822B(x)                                             \
+	(((x) >> BIT_SHIFT_MID_31TO0_8822B) & BIT_MASK_MID_31TO0_8822B)
+#define BIT_SET_MID_31TO0_8822B(x, v)                                          \
+	(BIT_CLEAR_MID_31TO0_8822B(x) | BIT_MID_31TO0_8822B(v))
+
+/* 2 REG_SPWR1_8822B */
+
+#define BIT_SHIFT_MID_63TO32_8822B 0
+#define BIT_MASK_MID_63TO32_8822B 0xffffffffL
+#define BIT_MID_63TO32_8822B(x)                                                \
+	(((x) & BIT_MASK_MID_63TO32_8822B) << BIT_SHIFT_MID_63TO32_8822B)
+#define BITS_MID_63TO32_8822B                                                  \
+	(BIT_MASK_MID_63TO32_8822B << BIT_SHIFT_MID_63TO32_8822B)
+#define BIT_CLEAR_MID_63TO32_8822B(x) ((x) & (~BITS_MID_63TO32_8822B))
+#define BIT_GET_MID_63TO32_8822B(x)                                            \
+	(((x) >> BIT_SHIFT_MID_63TO32_8822B) & BIT_MASK_MID_63TO32_8822B)
+#define BIT_SET_MID_63TO32_8822B(x, v)                                         \
+	(BIT_CLEAR_MID_63TO32_8822B(x) | BIT_MID_63TO32_8822B(v))
+
+/* 2 REG_SPWR2_8822B */
+
+#define BIT_SHIFT_MID_95O64_8822B 0
+#define BIT_MASK_MID_95O64_8822B 0xffffffffL
+#define BIT_MID_95O64_8822B(x)                                                 \
+	(((x) & BIT_MASK_MID_95O64_8822B) << BIT_SHIFT_MID_95O64_8822B)
+#define BITS_MID_95O64_8822B                                                   \
+	(BIT_MASK_MID_95O64_8822B << BIT_SHIFT_MID_95O64_8822B)
+#define BIT_CLEAR_MID_95O64_8822B(x) ((x) & (~BITS_MID_95O64_8822B))
+#define BIT_GET_MID_95O64_8822B(x)                                             \
+	(((x) >> BIT_SHIFT_MID_95O64_8822B) & BIT_MASK_MID_95O64_8822B)
+#define BIT_SET_MID_95O64_8822B(x, v)                                          \
+	(BIT_CLEAR_MID_95O64_8822B(x) | BIT_MID_95O64_8822B(v))
+
+/* 2 REG_SPWR3_8822B */
+
+#define BIT_SHIFT_MID_127TO96_8822B 0
+#define BIT_MASK_MID_127TO96_8822B 0xffffffffL
+#define BIT_MID_127TO96_8822B(x)                                               \
+	(((x) & BIT_MASK_MID_127TO96_8822B) << BIT_SHIFT_MID_127TO96_8822B)
+#define BITS_MID_127TO96_8822B                                                 \
+	(BIT_MASK_MID_127TO96_8822B << BIT_SHIFT_MID_127TO96_8822B)
+#define BIT_CLEAR_MID_127TO96_8822B(x) ((x) & (~BITS_MID_127TO96_8822B))
+#define BIT_GET_MID_127TO96_8822B(x)                                           \
+	(((x) >> BIT_SHIFT_MID_127TO96_8822B) & BIT_MASK_MID_127TO96_8822B)
+#define BIT_SET_MID_127TO96_8822B(x, v)                                        \
+	(BIT_CLEAR_MID_127TO96_8822B(x) | BIT_MID_127TO96_8822B(v))
+
+/* 2 REG_POWSEQ_8822B */
+
+#define BIT_SHIFT_SEQNUM_MID_8822B 16
+#define BIT_MASK_SEQNUM_MID_8822B 0xffff
+#define BIT_SEQNUM_MID_8822B(x)                                                \
+	(((x) & BIT_MASK_SEQNUM_MID_8822B) << BIT_SHIFT_SEQNUM_MID_8822B)
+#define BITS_SEQNUM_MID_8822B                                                  \
+	(BIT_MASK_SEQNUM_MID_8822B << BIT_SHIFT_SEQNUM_MID_8822B)
+#define BIT_CLEAR_SEQNUM_MID_8822B(x) ((x) & (~BITS_SEQNUM_MID_8822B))
+#define BIT_GET_SEQNUM_MID_8822B(x)                                            \
+	(((x) >> BIT_SHIFT_SEQNUM_MID_8822B) & BIT_MASK_SEQNUM_MID_8822B)
+#define BIT_SET_SEQNUM_MID_8822B(x, v)                                         \
+	(BIT_CLEAR_SEQNUM_MID_8822B(x) | BIT_SEQNUM_MID_8822B(v))
+
+#define BIT_SHIFT_REF_MID_8822B 0
+#define BIT_MASK_REF_MID_8822B 0x7f
+#define BIT_REF_MID_8822B(x)                                                   \
+	(((x) & BIT_MASK_REF_MID_8822B) << BIT_SHIFT_REF_MID_8822B)
+#define BITS_REF_MID_8822B (BIT_MASK_REF_MID_8822B << BIT_SHIFT_REF_MID_8822B)
+#define BIT_CLEAR_REF_MID_8822B(x) ((x) & (~BITS_REF_MID_8822B))
+#define BIT_GET_REF_MID_8822B(x)                                               \
+	(((x) >> BIT_SHIFT_REF_MID_8822B) & BIT_MASK_REF_MID_8822B)
+#define BIT_SET_REF_MID_8822B(x, v)                                            \
+	(BIT_CLEAR_REF_MID_8822B(x) | BIT_REF_MID_8822B(v))
+
+/* 2 REG_TC7_CTRL_V1_8822B */
+#define BIT_TC7INT_EN_8822B BIT(26)
+#define BIT_TC7MODE_8822B BIT(25)
+#define BIT_TC7EN_8822B BIT(24)
+
+#define BIT_SHIFT_TC7DATA_8822B 0
+#define BIT_MASK_TC7DATA_8822B 0xffffff
+#define BIT_TC7DATA_8822B(x)                                                   \
+	(((x) & BIT_MASK_TC7DATA_8822B) << BIT_SHIFT_TC7DATA_8822B)
+#define BITS_TC7DATA_8822B (BIT_MASK_TC7DATA_8822B << BIT_SHIFT_TC7DATA_8822B)
+#define BIT_CLEAR_TC7DATA_8822B(x) ((x) & (~BITS_TC7DATA_8822B))
+#define BIT_GET_TC7DATA_8822B(x)                                               \
+	(((x) >> BIT_SHIFT_TC7DATA_8822B) & BIT_MASK_TC7DATA_8822B)
+#define BIT_SET_TC7DATA_8822B(x, v)                                            \
+	(BIT_CLEAR_TC7DATA_8822B(x) | BIT_TC7DATA_8822B(v))
+
+/* 2 REG_TC8_CTRL_V1_8822B */
+#define BIT_TC8INT_EN_8822B BIT(26)
+#define BIT_TC8MODE_8822B BIT(25)
+#define BIT_TC8EN_8822B BIT(24)
+
+#define BIT_SHIFT_TC8DATA_8822B 0
+#define BIT_MASK_TC8DATA_8822B 0xffffff
+#define BIT_TC8DATA_8822B(x)                                                   \
+	(((x) & BIT_MASK_TC8DATA_8822B) << BIT_SHIFT_TC8DATA_8822B)
+#define BITS_TC8DATA_8822B (BIT_MASK_TC8DATA_8822B << BIT_SHIFT_TC8DATA_8822B)
+#define BIT_CLEAR_TC8DATA_8822B(x) ((x) & (~BITS_TC8DATA_8822B))
+#define BIT_GET_TC8DATA_8822B(x)                                               \
+	(((x) >> BIT_SHIFT_TC8DATA_8822B) & BIT_MASK_TC8DATA_8822B)
+#define BIT_SET_TC8DATA_8822B(x, v)                                            \
+	(BIT_CLEAR_TC8DATA_8822B(x) | BIT_TC8DATA_8822B(v))
+
+/* 2 REG_FT2IMR_8822B */
+#define BIT_FS_CLI3_RX_UAPSDMD1_EN_8822B BIT(31)
+#define BIT_FS_CLI3_RX_UAPSDMD0_EN_8822B BIT(30)
+#define BIT_FS_CLI3_TRIGGER_PKT_EN_8822B BIT(29)
+#define BIT_FS_CLI3_EOSP_INT_EN_8822B BIT(28)
+#define BIT_FS_CLI2_RX_UAPSDMD1_EN_8822B BIT(27)
+#define BIT_FS_CLI2_RX_UAPSDMD0_EN_8822B BIT(26)
+#define BIT_FS_CLI2_TRIGGER_PKT_EN_8822B BIT(25)
+#define BIT_FS_CLI2_EOSP_INT_EN_8822B BIT(24)
+#define BIT_FS_CLI1_RX_UAPSDMD1_EN_8822B BIT(23)
+#define BIT_FS_CLI1_RX_UAPSDMD0_EN_8822B BIT(22)
+#define BIT_FS_CLI1_TRIGGER_PKT_EN_8822B BIT(21)
+#define BIT_FS_CLI1_EOSP_INT_EN_8822B BIT(20)
+#define BIT_FS_CLI0_RX_UAPSDMD1_EN_8822B BIT(19)
+#define BIT_FS_CLI0_RX_UAPSDMD0_EN_8822B BIT(18)
+#define BIT_FS_CLI0_TRIGGER_PKT_EN_8822B BIT(17)
+#define BIT_FS_CLI0_EOSP_INT_EN_8822B BIT(16)
+#define BIT_FS_TSF_BIT32_TOGGLE_P2P2_EN_8822B BIT(9)
+#define BIT_FS_TSF_BIT32_TOGGLE_P2P1_EN_8822B BIT(8)
+#define BIT_FS_CLI3_TX_NULL1_INT_EN_8822B BIT(7)
+#define BIT_FS_CLI3_TX_NULL0_INT_EN_8822B BIT(6)
+#define BIT_FS_CLI2_TX_NULL1_INT_EN_8822B BIT(5)
+#define BIT_FS_CLI2_TX_NULL0_INT_EN_8822B BIT(4)
+#define BIT_FS_CLI1_TX_NULL1_INT_EN_8822B BIT(3)
+#define BIT_FS_CLI1_TX_NULL0_INT_EN_8822B BIT(2)
+#define BIT_FS_CLI0_TX_NULL1_INT_EN_8822B BIT(1)
+#define BIT_FS_CLI0_TX_NULL0_INT_EN_8822B BIT(0)
+
+/* 2 REG_FT2ISR_8822B */
+#define BIT_FS_CLI3_RX_UAPSDMD1_INT_8822B BIT(31)
+#define BIT_FS_CLI3_RX_UAPSDMD0_INT_8822B BIT(30)
+#define BIT_FS_CLI3_TRIGGER_PKT_INT_8822B BIT(29)
+#define BIT_FS_CLI3_EOSP_INT_8822B BIT(28)
+#define BIT_FS_CLI2_RX_UAPSDMD1_INT_8822B BIT(27)
+#define BIT_FS_CLI2_RX_UAPSDMD0_INT_8822B BIT(26)
+#define BIT_FS_CLI2_TRIGGER_PKT_INT_8822B BIT(25)
+#define BIT_FS_CLI2_EOSP_INT_8822B BIT(24)
+#define BIT_FS_CLI1_RX_UAPSDMD1_INT_8822B BIT(23)
+#define BIT_FS_CLI1_RX_UAPSDMD0_INT_8822B BIT(22)
+#define BIT_FS_CLI1_TRIGGER_PKT_INT_8822B BIT(21)
+#define BIT_FS_CLI1_EOSP_INT_8822B BIT(20)
+#define BIT_FS_CLI0_RX_UAPSDMD1_INT_8822B BIT(19)
+#define BIT_FS_CLI0_RX_UAPSDMD0_INT_8822B BIT(18)
+#define BIT_FS_CLI0_TRIGGER_PKT_INT_8822B BIT(17)
+#define BIT_FS_CLI0_EOSP_INT_8822B BIT(16)
+#define BIT_FS_TSF_BIT32_TOGGLE_P2P2_INT_8822B BIT(9)
+#define BIT_FS_TSF_BIT32_TOGGLE_P2P1_INT_8822B BIT(8)
+#define BIT_FS_CLI3_TX_NULL1_INT_8822B BIT(7)
+#define BIT_FS_CLI3_TX_NULL0_INT_8822B BIT(6)
+#define BIT_FS_CLI2_TX_NULL1_INT_8822B BIT(5)
+#define BIT_FS_CLI2_TX_NULL0_INT_8822B BIT(4)
+#define BIT_FS_CLI1_TX_NULL1_INT_8822B BIT(3)
+#define BIT_FS_CLI1_TX_NULL0_INT_8822B BIT(2)
+#define BIT_FS_CLI0_TX_NULL1_INT_8822B BIT(1)
+#define BIT_FS_CLI0_TX_NULL0_INT_8822B BIT(0)
+
+/* 2 REG_MSG2_8822B */
+
+#define BIT_SHIFT_FW_MSG2_8822B 0
+#define BIT_MASK_FW_MSG2_8822B 0xffffffffL
+#define BIT_FW_MSG2_8822B(x)                                                   \
+	(((x) & BIT_MASK_FW_MSG2_8822B) << BIT_SHIFT_FW_MSG2_8822B)
+#define BITS_FW_MSG2_8822B (BIT_MASK_FW_MSG2_8822B << BIT_SHIFT_FW_MSG2_8822B)
+#define BIT_CLEAR_FW_MSG2_8822B(x) ((x) & (~BITS_FW_MSG2_8822B))
+#define BIT_GET_FW_MSG2_8822B(x)                                               \
+	(((x) >> BIT_SHIFT_FW_MSG2_8822B) & BIT_MASK_FW_MSG2_8822B)
+#define BIT_SET_FW_MSG2_8822B(x, v)                                            \
+	(BIT_CLEAR_FW_MSG2_8822B(x) | BIT_FW_MSG2_8822B(v))
+
+/* 2 REG_MSG3_8822B */
+
+#define BIT_SHIFT_FW_MSG3_8822B 0
+#define BIT_MASK_FW_MSG3_8822B 0xffffffffL
+#define BIT_FW_MSG3_8822B(x)                                                   \
+	(((x) & BIT_MASK_FW_MSG3_8822B) << BIT_SHIFT_FW_MSG3_8822B)
+#define BITS_FW_MSG3_8822B (BIT_MASK_FW_MSG3_8822B << BIT_SHIFT_FW_MSG3_8822B)
+#define BIT_CLEAR_FW_MSG3_8822B(x) ((x) & (~BITS_FW_MSG3_8822B))
+#define BIT_GET_FW_MSG3_8822B(x)                                               \
+	(((x) >> BIT_SHIFT_FW_MSG3_8822B) & BIT_MASK_FW_MSG3_8822B)
+#define BIT_SET_FW_MSG3_8822B(x, v)                                            \
+	(BIT_CLEAR_FW_MSG3_8822B(x) | BIT_FW_MSG3_8822B(v))
+
+/* 2 REG_MSG4_8822B */
+
+#define BIT_SHIFT_FW_MSG4_8822B 0
+#define BIT_MASK_FW_MSG4_8822B 0xffffffffL
+#define BIT_FW_MSG4_8822B(x)                                                   \
+	(((x) & BIT_MASK_FW_MSG4_8822B) << BIT_SHIFT_FW_MSG4_8822B)
+#define BITS_FW_MSG4_8822B (BIT_MASK_FW_MSG4_8822B << BIT_SHIFT_FW_MSG4_8822B)
+#define BIT_CLEAR_FW_MSG4_8822B(x) ((x) & (~BITS_FW_MSG4_8822B))
+#define BIT_GET_FW_MSG4_8822B(x)                                               \
+	(((x) >> BIT_SHIFT_FW_MSG4_8822B) & BIT_MASK_FW_MSG4_8822B)
+#define BIT_SET_FW_MSG4_8822B(x, v)                                            \
+	(BIT_CLEAR_FW_MSG4_8822B(x) | BIT_FW_MSG4_8822B(v))
+
+/* 2 REG_MSG5_8822B */
+
+#define BIT_SHIFT_FW_MSG5_8822B 0
+#define BIT_MASK_FW_MSG5_8822B 0xffffffffL
+#define BIT_FW_MSG5_8822B(x)                                                   \
+	(((x) & BIT_MASK_FW_MSG5_8822B) << BIT_SHIFT_FW_MSG5_8822B)
+#define BITS_FW_MSG5_8822B (BIT_MASK_FW_MSG5_8822B << BIT_SHIFT_FW_MSG5_8822B)
+#define BIT_CLEAR_FW_MSG5_8822B(x) ((x) & (~BITS_FW_MSG5_8822B))
+#define BIT_GET_FW_MSG5_8822B(x)                                               \
+	(((x) >> BIT_SHIFT_FW_MSG5_8822B) & BIT_MASK_FW_MSG5_8822B)
+#define BIT_SET_FW_MSG5_8822B(x, v)                                            \
+	(BIT_CLEAR_FW_MSG5_8822B(x) | BIT_FW_MSG5_8822B(v))
+
+/* 2 REG_NOT_VALID_8822B */
+
+/* 2 REG_FIFOPAGE_CTRL_1_8822B */
+
+#define BIT_SHIFT_TX_OQT_HE_FREE_SPACE_V1_8822B 16
+#define BIT_MASK_TX_OQT_HE_FREE_SPACE_V1_8822B 0xff
+#define BIT_TX_OQT_HE_FREE_SPACE_V1_8822B(x)                                   \
+	(((x) & BIT_MASK_TX_OQT_HE_FREE_SPACE_V1_8822B)                        \
+	 << BIT_SHIFT_TX_OQT_HE_FREE_SPACE_V1_8822B)
+#define BITS_TX_OQT_HE_FREE_SPACE_V1_8822B                                     \
+	(BIT_MASK_TX_OQT_HE_FREE_SPACE_V1_8822B                                \
+	 << BIT_SHIFT_TX_OQT_HE_FREE_SPACE_V1_8822B)
+#define BIT_CLEAR_TX_OQT_HE_FREE_SPACE_V1_8822B(x)                             \
+	((x) & (~BITS_TX_OQT_HE_FREE_SPACE_V1_8822B))
+#define BIT_GET_TX_OQT_HE_FREE_SPACE_V1_8822B(x)                               \
+	(((x) >> BIT_SHIFT_TX_OQT_HE_FREE_SPACE_V1_8822B) &                    \
+	 BIT_MASK_TX_OQT_HE_FREE_SPACE_V1_8822B)
+#define BIT_SET_TX_OQT_HE_FREE_SPACE_V1_8822B(x, v)                            \
+	(BIT_CLEAR_TX_OQT_HE_FREE_SPACE_V1_8822B(x) |                          \
+	 BIT_TX_OQT_HE_FREE_SPACE_V1_8822B(v))
+
+#define BIT_SHIFT_TX_OQT_NL_FREE_SPACE_V1_8822B 0
+#define BIT_MASK_TX_OQT_NL_FREE_SPACE_V1_8822B 0xff
+#define BIT_TX_OQT_NL_FREE_SPACE_V1_8822B(x)                                   \
+	(((x) & BIT_MASK_TX_OQT_NL_FREE_SPACE_V1_8822B)                        \
+	 << BIT_SHIFT_TX_OQT_NL_FREE_SPACE_V1_8822B)
+#define BITS_TX_OQT_NL_FREE_SPACE_V1_8822B                                     \
+	(BIT_MASK_TX_OQT_NL_FREE_SPACE_V1_8822B                                \
+	 << BIT_SHIFT_TX_OQT_NL_FREE_SPACE_V1_8822B)
+#define BIT_CLEAR_TX_OQT_NL_FREE_SPACE_V1_8822B(x)                             \
+	((x) & (~BITS_TX_OQT_NL_FREE_SPACE_V1_8822B))
+#define BIT_GET_TX_OQT_NL_FREE_SPACE_V1_8822B(x)                               \
+	(((x) >> BIT_SHIFT_TX_OQT_NL_FREE_SPACE_V1_8822B) &                    \
+	 BIT_MASK_TX_OQT_NL_FREE_SPACE_V1_8822B)
+#define BIT_SET_TX_OQT_NL_FREE_SPACE_V1_8822B(x, v)                            \
+	(BIT_CLEAR_TX_OQT_NL_FREE_SPACE_V1_8822B(x) |                          \
+	 BIT_TX_OQT_NL_FREE_SPACE_V1_8822B(v))
+
+/* 2 REG_FIFOPAGE_CTRL_2_8822B */
+#define BIT_BCN_VALID_1_V1_8822B BIT(31)
+
+#define BIT_SHIFT_BCN_HEAD_1_V1_8822B 16
+#define BIT_MASK_BCN_HEAD_1_V1_8822B 0xfff
+#define BIT_BCN_HEAD_1_V1_8822B(x)                                             \
+	(((x) & BIT_MASK_BCN_HEAD_1_V1_8822B) << BIT_SHIFT_BCN_HEAD_1_V1_8822B)
+#define BITS_BCN_HEAD_1_V1_8822B                                               \
+	(BIT_MASK_BCN_HEAD_1_V1_8822B << BIT_SHIFT_BCN_HEAD_1_V1_8822B)
+#define BIT_CLEAR_BCN_HEAD_1_V1_8822B(x) ((x) & (~BITS_BCN_HEAD_1_V1_8822B))
+#define BIT_GET_BCN_HEAD_1_V1_8822B(x)                                         \
+	(((x) >> BIT_SHIFT_BCN_HEAD_1_V1_8822B) & BIT_MASK_BCN_HEAD_1_V1_8822B)
+#define BIT_SET_BCN_HEAD_1_V1_8822B(x, v)                                      \
+	(BIT_CLEAR_BCN_HEAD_1_V1_8822B(x) | BIT_BCN_HEAD_1_V1_8822B(v))
+
+#define BIT_BCN_VALID_V1_8822B BIT(15)
+
+#define BIT_SHIFT_BCN_HEAD_V1_8822B 0
+#define BIT_MASK_BCN_HEAD_V1_8822B 0xfff
+#define BIT_BCN_HEAD_V1_8822B(x)                                               \
+	(((x) & BIT_MASK_BCN_HEAD_V1_8822B) << BIT_SHIFT_BCN_HEAD_V1_8822B)
+#define BITS_BCN_HEAD_V1_8822B                                                 \
+	(BIT_MASK_BCN_HEAD_V1_8822B << BIT_SHIFT_BCN_HEAD_V1_8822B)
+#define BIT_CLEAR_BCN_HEAD_V1_8822B(x) ((x) & (~BITS_BCN_HEAD_V1_8822B))
+#define BIT_GET_BCN_HEAD_V1_8822B(x)                                           \
+	(((x) >> BIT_SHIFT_BCN_HEAD_V1_8822B) & BIT_MASK_BCN_HEAD_V1_8822B)
+#define BIT_SET_BCN_HEAD_V1_8822B(x, v)                                        \
+	(BIT_CLEAR_BCN_HEAD_V1_8822B(x) | BIT_BCN_HEAD_V1_8822B(v))
+
+/* 2 REG_AUTO_LLT_V1_8822B */
+
+#define BIT_SHIFT_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8822B 24
+#define BIT_MASK_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8822B 0xff
+#define BIT_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8822B(x)                            \
+	(((x) & BIT_MASK_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8822B)                 \
+	 << BIT_SHIFT_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8822B)
+#define BITS_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8822B                              \
+	(BIT_MASK_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8822B                         \
+	 << BIT_SHIFT_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8822B)
+#define BIT_CLEAR_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8822B(x)                      \
+	((x) & (~BITS_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8822B))
+#define BIT_GET_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8822B(x)                        \
+	(((x) >> BIT_SHIFT_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8822B) &             \
+	 BIT_MASK_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8822B)
+#define BIT_SET_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8822B(x, v)                     \
+	(BIT_CLEAR_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8822B(x) |                   \
+	 BIT_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8822B(v))
+
+#define BIT_SHIFT_LLT_FREE_PAGE_V1_8822B 8
+#define BIT_MASK_LLT_FREE_PAGE_V1_8822B 0xffff
+#define BIT_LLT_FREE_PAGE_V1_8822B(x)                                          \
+	(((x) & BIT_MASK_LLT_FREE_PAGE_V1_8822B)                               \
+	 << BIT_SHIFT_LLT_FREE_PAGE_V1_8822B)
+#define BITS_LLT_FREE_PAGE_V1_8822B                                            \
+	(BIT_MASK_LLT_FREE_PAGE_V1_8822B << BIT_SHIFT_LLT_FREE_PAGE_V1_8822B)
+#define BIT_CLEAR_LLT_FREE_PAGE_V1_8822B(x)                                    \
+	((x) & (~BITS_LLT_FREE_PAGE_V1_8822B))
+#define BIT_GET_LLT_FREE_PAGE_V1_8822B(x)                                      \
+	(((x) >> BIT_SHIFT_LLT_FREE_PAGE_V1_8822B) &                           \
+	 BIT_MASK_LLT_FREE_PAGE_V1_8822B)
+#define BIT_SET_LLT_FREE_PAGE_V1_8822B(x, v)                                   \
+	(BIT_CLEAR_LLT_FREE_PAGE_V1_8822B(x) | BIT_LLT_FREE_PAGE_V1_8822B(v))
+
+#define BIT_SHIFT_BLK_DESC_NUM_8822B 4
+#define BIT_MASK_BLK_DESC_NUM_8822B 0xf
+#define BIT_BLK_DESC_NUM_8822B(x)                                              \
+	(((x) & BIT_MASK_BLK_DESC_NUM_8822B) << BIT_SHIFT_BLK_DESC_NUM_8822B)
+#define BITS_BLK_DESC_NUM_8822B                                                \
+	(BIT_MASK_BLK_DESC_NUM_8822B << BIT_SHIFT_BLK_DESC_NUM_8822B)
+#define BIT_CLEAR_BLK_DESC_NUM_8822B(x) ((x) & (~BITS_BLK_DESC_NUM_8822B))
+#define BIT_GET_BLK_DESC_NUM_8822B(x)                                          \
+	(((x) >> BIT_SHIFT_BLK_DESC_NUM_8822B) & BIT_MASK_BLK_DESC_NUM_8822B)
+#define BIT_SET_BLK_DESC_NUM_8822B(x, v)                                       \
+	(BIT_CLEAR_BLK_DESC_NUM_8822B(x) | BIT_BLK_DESC_NUM_8822B(v))
+
+#define BIT_R_BCN_HEAD_SEL_8822B BIT(3)
+#define BIT_R_EN_BCN_SW_HEAD_SEL_8822B BIT(2)
+#define BIT_LLT_DBG_SEL_8822B BIT(1)
+#define BIT_AUTO_INIT_LLT_V1_8822B BIT(0)
+
+/* 2 REG_TXDMA_OFFSET_CHK_8822B */
+#define BIT_EM_CHKSUM_FIN_8822B BIT(31)
+#define BIT_EMN_PCIE_DMA_MOD_8822B BIT(30)
+#define BIT_EN_TXQUE_CLR_8822B BIT(29)
+#define BIT_EN_PCIE_FIFO_MODE_8822B BIT(28)
+
+#define BIT_SHIFT_PG_UNDER_TH_V1_8822B 16
+#define BIT_MASK_PG_UNDER_TH_V1_8822B 0xfff
+#define BIT_PG_UNDER_TH_V1_8822B(x)                                            \
+	(((x) & BIT_MASK_PG_UNDER_TH_V1_8822B)                                 \
+	 << BIT_SHIFT_PG_UNDER_TH_V1_8822B)
+#define BITS_PG_UNDER_TH_V1_8822B                                              \
+	(BIT_MASK_PG_UNDER_TH_V1_8822B << BIT_SHIFT_PG_UNDER_TH_V1_8822B)
+#define BIT_CLEAR_PG_UNDER_TH_V1_8822B(x) ((x) & (~BITS_PG_UNDER_TH_V1_8822B))
+#define BIT_GET_PG_UNDER_TH_V1_8822B(x)                                        \
+	(((x) >> BIT_SHIFT_PG_UNDER_TH_V1_8822B) &                             \
+	 BIT_MASK_PG_UNDER_TH_V1_8822B)
+#define BIT_SET_PG_UNDER_TH_V1_8822B(x, v)                                     \
+	(BIT_CLEAR_PG_UNDER_TH_V1_8822B(x) | BIT_PG_UNDER_TH_V1_8822B(v))
+
+#define BIT_RESTORE_H2C_ADDRESS_8822B BIT(15)
+#define BIT_SDIO_TXDESC_CHKSUM_EN_8822B BIT(13)
+#define BIT_RST_RDPTR_8822B BIT(12)
+#define BIT_RST_WRPTR_8822B BIT(11)
+#define BIT_CHK_PG_TH_EN_8822B BIT(10)
+#define BIT_DROP_DATA_EN_8822B BIT(9)
+#define BIT_CHECK_OFFSET_EN_8822B BIT(8)
+
+#define BIT_SHIFT_CHECK_OFFSET_8822B 0
+#define BIT_MASK_CHECK_OFFSET_8822B 0xff
+#define BIT_CHECK_OFFSET_8822B(x)                                              \
+	(((x) & BIT_MASK_CHECK_OFFSET_8822B) << BIT_SHIFT_CHECK_OFFSET_8822B)
+#define BITS_CHECK_OFFSET_8822B                                                \
+	(BIT_MASK_CHECK_OFFSET_8822B << BIT_SHIFT_CHECK_OFFSET_8822B)
+#define BIT_CLEAR_CHECK_OFFSET_8822B(x) ((x) & (~BITS_CHECK_OFFSET_8822B))
+#define BIT_GET_CHECK_OFFSET_8822B(x)                                          \
+	(((x) >> BIT_SHIFT_CHECK_OFFSET_8822B) & BIT_MASK_CHECK_OFFSET_8822B)
+#define BIT_SET_CHECK_OFFSET_8822B(x, v)                                       \
+	(BIT_CLEAR_CHECK_OFFSET_8822B(x) | BIT_CHECK_OFFSET_8822B(v))
+
+/* 2 REG_TXDMA_STATUS_8822B */
+#define BIT_HI_OQT_UDN_8822B BIT(17)
+#define BIT_HI_OQT_OVF_8822B BIT(16)
+#define BIT_PAYLOAD_CHKSUM_ERR_8822B BIT(15)
+#define BIT_PAYLOAD_UDN_8822B BIT(14)
+#define BIT_PAYLOAD_OVF_8822B BIT(13)
+#define BIT_DSC_CHKSUM_FAIL_8822B BIT(12)
+#define BIT_UNKNOWN_QSEL_8822B BIT(11)
+#define BIT_EP_QSEL_DIFF_8822B BIT(10)
+#define BIT_TX_OFFS_UNMATCH_8822B BIT(9)
+#define BIT_TXOQT_UDN_8822B BIT(8)
+#define BIT_TXOQT_OVF_8822B BIT(7)
+#define BIT_TXDMA_SFF_UDN_8822B BIT(6)
+#define BIT_TXDMA_SFF_OVF_8822B BIT(5)
+#define BIT_LLT_NULL_PG_8822B BIT(4)
+#define BIT_PAGE_UDN_8822B BIT(3)
+#define BIT_PAGE_OVF_8822B BIT(2)
+#define BIT_TXFF_PG_UDN_8822B BIT(1)
+#define BIT_TXFF_PG_OVF_8822B BIT(0)
+
+/* 2 REG_TX_DMA_DBG_8822B */
+
+/* 2 REG_TQPNT1_8822B */
+
+#define BIT_SHIFT_HPQ_HIGH_TH_V1_8822B 16
+#define BIT_MASK_HPQ_HIGH_TH_V1_8822B 0xfff
+#define BIT_HPQ_HIGH_TH_V1_8822B(x)                                            \
+	(((x) & BIT_MASK_HPQ_HIGH_TH_V1_8822B)                                 \
+	 << BIT_SHIFT_HPQ_HIGH_TH_V1_8822B)
+#define BITS_HPQ_HIGH_TH_V1_8822B                                              \
+	(BIT_MASK_HPQ_HIGH_TH_V1_8822B << BIT_SHIFT_HPQ_HIGH_TH_V1_8822B)
+#define BIT_CLEAR_HPQ_HIGH_TH_V1_8822B(x) ((x) & (~BITS_HPQ_HIGH_TH_V1_8822B))
+#define BIT_GET_HPQ_HIGH_TH_V1_8822B(x)                                        \
+	(((x) >> BIT_SHIFT_HPQ_HIGH_TH_V1_8822B) &                             \
+	 BIT_MASK_HPQ_HIGH_TH_V1_8822B)
+#define BIT_SET_HPQ_HIGH_TH_V1_8822B(x, v)                                     \
+	(BIT_CLEAR_HPQ_HIGH_TH_V1_8822B(x) | BIT_HPQ_HIGH_TH_V1_8822B(v))
+
+#define BIT_SHIFT_HPQ_LOW_TH_V1_8822B 0
+#define BIT_MASK_HPQ_LOW_TH_V1_8822B 0xfff
+#define BIT_HPQ_LOW_TH_V1_8822B(x)                                             \
+	(((x) & BIT_MASK_HPQ_LOW_TH_V1_8822B) << BIT_SHIFT_HPQ_LOW_TH_V1_8822B)
+#define BITS_HPQ_LOW_TH_V1_8822B                                               \
+	(BIT_MASK_HPQ_LOW_TH_V1_8822B << BIT_SHIFT_HPQ_LOW_TH_V1_8822B)
+#define BIT_CLEAR_HPQ_LOW_TH_V1_8822B(x) ((x) & (~BITS_HPQ_LOW_TH_V1_8822B))
+#define BIT_GET_HPQ_LOW_TH_V1_8822B(x)                                         \
+	(((x) >> BIT_SHIFT_HPQ_LOW_TH_V1_8822B) & BIT_MASK_HPQ_LOW_TH_V1_8822B)
+#define BIT_SET_HPQ_LOW_TH_V1_8822B(x, v)                                      \
+	(BIT_CLEAR_HPQ_LOW_TH_V1_8822B(x) | BIT_HPQ_LOW_TH_V1_8822B(v))
+
+/* 2 REG_TQPNT2_8822B */
+
+#define BIT_SHIFT_NPQ_HIGH_TH_V1_8822B 16
+#define BIT_MASK_NPQ_HIGH_TH_V1_8822B 0xfff
+#define BIT_NPQ_HIGH_TH_V1_8822B(x)                                            \
+	(((x) & BIT_MASK_NPQ_HIGH_TH_V1_8822B)                                 \
+	 << BIT_SHIFT_NPQ_HIGH_TH_V1_8822B)
+#define BITS_NPQ_HIGH_TH_V1_8822B                                              \
+	(BIT_MASK_NPQ_HIGH_TH_V1_8822B << BIT_SHIFT_NPQ_HIGH_TH_V1_8822B)
+#define BIT_CLEAR_NPQ_HIGH_TH_V1_8822B(x) ((x) & (~BITS_NPQ_HIGH_TH_V1_8822B))
+#define BIT_GET_NPQ_HIGH_TH_V1_8822B(x)                                        \
+	(((x) >> BIT_SHIFT_NPQ_HIGH_TH_V1_8822B) &                             \
+	 BIT_MASK_NPQ_HIGH_TH_V1_8822B)
+#define BIT_SET_NPQ_HIGH_TH_V1_8822B(x, v)                                     \
+	(BIT_CLEAR_NPQ_HIGH_TH_V1_8822B(x) | BIT_NPQ_HIGH_TH_V1_8822B(v))
+
+#define BIT_SHIFT_NPQ_LOW_TH_V1_8822B 0
+#define BIT_MASK_NPQ_LOW_TH_V1_8822B 0xfff
+#define BIT_NPQ_LOW_TH_V1_8822B(x)                                             \
+	(((x) & BIT_MASK_NPQ_LOW_TH_V1_8822B) << BIT_SHIFT_NPQ_LOW_TH_V1_8822B)
+#define BITS_NPQ_LOW_TH_V1_8822B                                               \
+	(BIT_MASK_NPQ_LOW_TH_V1_8822B << BIT_SHIFT_NPQ_LOW_TH_V1_8822B)
+#define BIT_CLEAR_NPQ_LOW_TH_V1_8822B(x) ((x) & (~BITS_NPQ_LOW_TH_V1_8822B))
+#define BIT_GET_NPQ_LOW_TH_V1_8822B(x)                                         \
+	(((x) >> BIT_SHIFT_NPQ_LOW_TH_V1_8822B) & BIT_MASK_NPQ_LOW_TH_V1_8822B)
+#define BIT_SET_NPQ_LOW_TH_V1_8822B(x, v)                                      \
+	(BIT_CLEAR_NPQ_LOW_TH_V1_8822B(x) | BIT_NPQ_LOW_TH_V1_8822B(v))
+
+/* 2 REG_TQPNT3_8822B */
+
+#define BIT_SHIFT_LPQ_HIGH_TH_V1_8822B 16
+#define BIT_MASK_LPQ_HIGH_TH_V1_8822B 0xfff
+#define BIT_LPQ_HIGH_TH_V1_8822B(x)                                            \
+	(((x) & BIT_MASK_LPQ_HIGH_TH_V1_8822B)                                 \
+	 << BIT_SHIFT_LPQ_HIGH_TH_V1_8822B)
+#define BITS_LPQ_HIGH_TH_V1_8822B                                              \
+	(BIT_MASK_LPQ_HIGH_TH_V1_8822B << BIT_SHIFT_LPQ_HIGH_TH_V1_8822B)
+#define BIT_CLEAR_LPQ_HIGH_TH_V1_8822B(x) ((x) & (~BITS_LPQ_HIGH_TH_V1_8822B))
+#define BIT_GET_LPQ_HIGH_TH_V1_8822B(x)                                        \
+	(((x) >> BIT_SHIFT_LPQ_HIGH_TH_V1_8822B) &                             \
+	 BIT_MASK_LPQ_HIGH_TH_V1_8822B)
+#define BIT_SET_LPQ_HIGH_TH_V1_8822B(x, v)                                     \
+	(BIT_CLEAR_LPQ_HIGH_TH_V1_8822B(x) | BIT_LPQ_HIGH_TH_V1_8822B(v))
+
+#define BIT_SHIFT_LPQ_LOW_TH_V1_8822B 0
+#define BIT_MASK_LPQ_LOW_TH_V1_8822B 0xfff
+#define BIT_LPQ_LOW_TH_V1_8822B(x)                                             \
+	(((x) & BIT_MASK_LPQ_LOW_TH_V1_8822B) << BIT_SHIFT_LPQ_LOW_TH_V1_8822B)
+#define BITS_LPQ_LOW_TH_V1_8822B                                               \
+	(BIT_MASK_LPQ_LOW_TH_V1_8822B << BIT_SHIFT_LPQ_LOW_TH_V1_8822B)
+#define BIT_CLEAR_LPQ_LOW_TH_V1_8822B(x) ((x) & (~BITS_LPQ_LOW_TH_V1_8822B))
+#define BIT_GET_LPQ_LOW_TH_V1_8822B(x)                                         \
+	(((x) >> BIT_SHIFT_LPQ_LOW_TH_V1_8822B) & BIT_MASK_LPQ_LOW_TH_V1_8822B)
+#define BIT_SET_LPQ_LOW_TH_V1_8822B(x, v)                                      \
+	(BIT_CLEAR_LPQ_LOW_TH_V1_8822B(x) | BIT_LPQ_LOW_TH_V1_8822B(v))
+
+/* 2 REG_TQPNT4_8822B */
+
+#define BIT_SHIFT_EXQ_HIGH_TH_V1_8822B 16
+#define BIT_MASK_EXQ_HIGH_TH_V1_8822B 0xfff
+#define BIT_EXQ_HIGH_TH_V1_8822B(x)                                            \
+	(((x) & BIT_MASK_EXQ_HIGH_TH_V1_8822B)                                 \
+	 << BIT_SHIFT_EXQ_HIGH_TH_V1_8822B)
+#define BITS_EXQ_HIGH_TH_V1_8822B                                              \
+	(BIT_MASK_EXQ_HIGH_TH_V1_8822B << BIT_SHIFT_EXQ_HIGH_TH_V1_8822B)
+#define BIT_CLEAR_EXQ_HIGH_TH_V1_8822B(x) ((x) & (~BITS_EXQ_HIGH_TH_V1_8822B))
+#define BIT_GET_EXQ_HIGH_TH_V1_8822B(x)                                        \
+	(((x) >> BIT_SHIFT_EXQ_HIGH_TH_V1_8822B) &                             \
+	 BIT_MASK_EXQ_HIGH_TH_V1_8822B)
+#define BIT_SET_EXQ_HIGH_TH_V1_8822B(x, v)                                     \
+	(BIT_CLEAR_EXQ_HIGH_TH_V1_8822B(x) | BIT_EXQ_HIGH_TH_V1_8822B(v))
+
+#define BIT_SHIFT_EXQ_LOW_TH_V1_8822B 0
+#define BIT_MASK_EXQ_LOW_TH_V1_8822B 0xfff
+#define BIT_EXQ_LOW_TH_V1_8822B(x)                                             \
+	(((x) & BIT_MASK_EXQ_LOW_TH_V1_8822B) << BIT_SHIFT_EXQ_LOW_TH_V1_8822B)
+#define BITS_EXQ_LOW_TH_V1_8822B                                               \
+	(BIT_MASK_EXQ_LOW_TH_V1_8822B << BIT_SHIFT_EXQ_LOW_TH_V1_8822B)
+#define BIT_CLEAR_EXQ_LOW_TH_V1_8822B(x) ((x) & (~BITS_EXQ_LOW_TH_V1_8822B))
+#define BIT_GET_EXQ_LOW_TH_V1_8822B(x)                                         \
+	(((x) >> BIT_SHIFT_EXQ_LOW_TH_V1_8822B) & BIT_MASK_EXQ_LOW_TH_V1_8822B)
+#define BIT_SET_EXQ_LOW_TH_V1_8822B(x, v)                                      \
+	(BIT_CLEAR_EXQ_LOW_TH_V1_8822B(x) | BIT_EXQ_LOW_TH_V1_8822B(v))
+
+/* 2 REG_RQPN_CTRL_1_8822B */
+
+#define BIT_SHIFT_TXPKTNUM_H_8822B 16
+#define BIT_MASK_TXPKTNUM_H_8822B 0xffff
+#define BIT_TXPKTNUM_H_8822B(x)                                                \
+	(((x) & BIT_MASK_TXPKTNUM_H_8822B) << BIT_SHIFT_TXPKTNUM_H_8822B)
+#define BITS_TXPKTNUM_H_8822B                                                  \
+	(BIT_MASK_TXPKTNUM_H_8822B << BIT_SHIFT_TXPKTNUM_H_8822B)
+#define BIT_CLEAR_TXPKTNUM_H_8822B(x) ((x) & (~BITS_TXPKTNUM_H_8822B))
+#define BIT_GET_TXPKTNUM_H_8822B(x)                                            \
+	(((x) >> BIT_SHIFT_TXPKTNUM_H_8822B) & BIT_MASK_TXPKTNUM_H_8822B)
+#define BIT_SET_TXPKTNUM_H_8822B(x, v)                                         \
+	(BIT_CLEAR_TXPKTNUM_H_8822B(x) | BIT_TXPKTNUM_H_8822B(v))
+
+#define BIT_SHIFT_TXPKTNUM_V2_8822B 0
+#define BIT_MASK_TXPKTNUM_V2_8822B 0xffff
+#define BIT_TXPKTNUM_V2_8822B(x)                                               \
+	(((x) & BIT_MASK_TXPKTNUM_V2_8822B) << BIT_SHIFT_TXPKTNUM_V2_8822B)
+#define BITS_TXPKTNUM_V2_8822B                                                 \
+	(BIT_MASK_TXPKTNUM_V2_8822B << BIT_SHIFT_TXPKTNUM_V2_8822B)
+#define BIT_CLEAR_TXPKTNUM_V2_8822B(x) ((x) & (~BITS_TXPKTNUM_V2_8822B))
+#define BIT_GET_TXPKTNUM_V2_8822B(x)                                           \
+	(((x) >> BIT_SHIFT_TXPKTNUM_V2_8822B) & BIT_MASK_TXPKTNUM_V2_8822B)
+#define BIT_SET_TXPKTNUM_V2_8822B(x, v)                                        \
+	(BIT_CLEAR_TXPKTNUM_V2_8822B(x) | BIT_TXPKTNUM_V2_8822B(v))
+
+/* 2 REG_RQPN_CTRL_2_8822B */
+#define BIT_LD_RQPN_8822B BIT(31)
+#define BIT_EXQ_PUBLIC_DIS_V1_8822B BIT(19)
+#define BIT_NPQ_PUBLIC_DIS_V1_8822B BIT(18)
+#define BIT_LPQ_PUBLIC_DIS_V1_8822B BIT(17)
+#define BIT_HPQ_PUBLIC_DIS_V1_8822B BIT(16)
+
+/* 2 REG_FIFOPAGE_INFO_1_8822B */
+
+#define BIT_SHIFT_HPQ_AVAL_PG_V1_8822B 16
+#define BIT_MASK_HPQ_AVAL_PG_V1_8822B 0xfff
+#define BIT_HPQ_AVAL_PG_V1_8822B(x)                                            \
+	(((x) & BIT_MASK_HPQ_AVAL_PG_V1_8822B)                                 \
+	 << BIT_SHIFT_HPQ_AVAL_PG_V1_8822B)
+#define BITS_HPQ_AVAL_PG_V1_8822B                                              \
+	(BIT_MASK_HPQ_AVAL_PG_V1_8822B << BIT_SHIFT_HPQ_AVAL_PG_V1_8822B)
+#define BIT_CLEAR_HPQ_AVAL_PG_V1_8822B(x) ((x) & (~BITS_HPQ_AVAL_PG_V1_8822B))
+#define BIT_GET_HPQ_AVAL_PG_V1_8822B(x)                                        \
+	(((x) >> BIT_SHIFT_HPQ_AVAL_PG_V1_8822B) &                             \
+	 BIT_MASK_HPQ_AVAL_PG_V1_8822B)
+#define BIT_SET_HPQ_AVAL_PG_V1_8822B(x, v)                                     \
+	(BIT_CLEAR_HPQ_AVAL_PG_V1_8822B(x) | BIT_HPQ_AVAL_PG_V1_8822B(v))
+
+#define BIT_SHIFT_HPQ_V1_8822B 0
+#define BIT_MASK_HPQ_V1_8822B 0xfff
+#define BIT_HPQ_V1_8822B(x)                                                    \
+	(((x) & BIT_MASK_HPQ_V1_8822B) << BIT_SHIFT_HPQ_V1_8822B)
+#define BITS_HPQ_V1_8822B (BIT_MASK_HPQ_V1_8822B << BIT_SHIFT_HPQ_V1_8822B)
+#define BIT_CLEAR_HPQ_V1_8822B(x) ((x) & (~BITS_HPQ_V1_8822B))
+#define BIT_GET_HPQ_V1_8822B(x)                                                \
+	(((x) >> BIT_SHIFT_HPQ_V1_8822B) & BIT_MASK_HPQ_V1_8822B)
+#define BIT_SET_HPQ_V1_8822B(x, v)                                             \
+	(BIT_CLEAR_HPQ_V1_8822B(x) | BIT_HPQ_V1_8822B(v))
+
+/* 2 REG_FIFOPAGE_INFO_2_8822B */
+
+#define BIT_SHIFT_LPQ_AVAL_PG_V1_8822B 16
+#define BIT_MASK_LPQ_AVAL_PG_V1_8822B 0xfff
+#define BIT_LPQ_AVAL_PG_V1_8822B(x)                                            \
+	(((x) & BIT_MASK_LPQ_AVAL_PG_V1_8822B)                                 \
+	 << BIT_SHIFT_LPQ_AVAL_PG_V1_8822B)
+#define BITS_LPQ_AVAL_PG_V1_8822B                                              \
+	(BIT_MASK_LPQ_AVAL_PG_V1_8822B << BIT_SHIFT_LPQ_AVAL_PG_V1_8822B)
+#define BIT_CLEAR_LPQ_AVAL_PG_V1_8822B(x) ((x) & (~BITS_LPQ_AVAL_PG_V1_8822B))
+#define BIT_GET_LPQ_AVAL_PG_V1_8822B(x)                                        \
+	(((x) >> BIT_SHIFT_LPQ_AVAL_PG_V1_8822B) &                             \
+	 BIT_MASK_LPQ_AVAL_PG_V1_8822B)
+#define BIT_SET_LPQ_AVAL_PG_V1_8822B(x, v)                                     \
+	(BIT_CLEAR_LPQ_AVAL_PG_V1_8822B(x) | BIT_LPQ_AVAL_PG_V1_8822B(v))
+
+#define BIT_SHIFT_LPQ_V1_8822B 0
+#define BIT_MASK_LPQ_V1_8822B 0xfff
+#define BIT_LPQ_V1_8822B(x)                                                    \
+	(((x) & BIT_MASK_LPQ_V1_8822B) << BIT_SHIFT_LPQ_V1_8822B)
+#define BITS_LPQ_V1_8822B (BIT_MASK_LPQ_V1_8822B << BIT_SHIFT_LPQ_V1_8822B)
+#define BIT_CLEAR_LPQ_V1_8822B(x) ((x) & (~BITS_LPQ_V1_8822B))
+#define BIT_GET_LPQ_V1_8822B(x)                                                \
+	(((x) >> BIT_SHIFT_LPQ_V1_8822B) & BIT_MASK_LPQ_V1_8822B)
+#define BIT_SET_LPQ_V1_8822B(x, v)                                             \
+	(BIT_CLEAR_LPQ_V1_8822B(x) | BIT_LPQ_V1_8822B(v))
+
+/* 2 REG_FIFOPAGE_INFO_3_8822B */
+
+#define BIT_SHIFT_NPQ_AVAL_PG_V1_8822B 16
+#define BIT_MASK_NPQ_AVAL_PG_V1_8822B 0xfff
+#define BIT_NPQ_AVAL_PG_V1_8822B(x)                                            \
+	(((x) & BIT_MASK_NPQ_AVAL_PG_V1_8822B)                                 \
+	 << BIT_SHIFT_NPQ_AVAL_PG_V1_8822B)
+#define BITS_NPQ_AVAL_PG_V1_8822B                                              \
+	(BIT_MASK_NPQ_AVAL_PG_V1_8822B << BIT_SHIFT_NPQ_AVAL_PG_V1_8822B)
+#define BIT_CLEAR_NPQ_AVAL_PG_V1_8822B(x) ((x) & (~BITS_NPQ_AVAL_PG_V1_8822B))
+#define BIT_GET_NPQ_AVAL_PG_V1_8822B(x)                                        \
+	(((x) >> BIT_SHIFT_NPQ_AVAL_PG_V1_8822B) &                             \
+	 BIT_MASK_NPQ_AVAL_PG_V1_8822B)
+#define BIT_SET_NPQ_AVAL_PG_V1_8822B(x, v)                                     \
+	(BIT_CLEAR_NPQ_AVAL_PG_V1_8822B(x) | BIT_NPQ_AVAL_PG_V1_8822B(v))
+
+#define BIT_SHIFT_NPQ_V1_8822B 0
+#define BIT_MASK_NPQ_V1_8822B 0xfff
+#define BIT_NPQ_V1_8822B(x)                                                    \
+	(((x) & BIT_MASK_NPQ_V1_8822B) << BIT_SHIFT_NPQ_V1_8822B)
+#define BITS_NPQ_V1_8822B (BIT_MASK_NPQ_V1_8822B << BIT_SHIFT_NPQ_V1_8822B)
+#define BIT_CLEAR_NPQ_V1_8822B(x) ((x) & (~BITS_NPQ_V1_8822B))
+#define BIT_GET_NPQ_V1_8822B(x)                                                \
+	(((x) >> BIT_SHIFT_NPQ_V1_8822B) & BIT_MASK_NPQ_V1_8822B)
+#define BIT_SET_NPQ_V1_8822B(x, v)                                             \
+	(BIT_CLEAR_NPQ_V1_8822B(x) | BIT_NPQ_V1_8822B(v))
+
+/* 2 REG_FIFOPAGE_INFO_4_8822B */
+
+#define BIT_SHIFT_EXQ_AVAL_PG_V1_8822B 16
+#define BIT_MASK_EXQ_AVAL_PG_V1_8822B 0xfff
+#define BIT_EXQ_AVAL_PG_V1_8822B(x)                                            \
+	(((x) & BIT_MASK_EXQ_AVAL_PG_V1_8822B)                                 \
+	 << BIT_SHIFT_EXQ_AVAL_PG_V1_8822B)
+#define BITS_EXQ_AVAL_PG_V1_8822B                                              \
+	(BIT_MASK_EXQ_AVAL_PG_V1_8822B << BIT_SHIFT_EXQ_AVAL_PG_V1_8822B)
+#define BIT_CLEAR_EXQ_AVAL_PG_V1_8822B(x) ((x) & (~BITS_EXQ_AVAL_PG_V1_8822B))
+#define BIT_GET_EXQ_AVAL_PG_V1_8822B(x)                                        \
+	(((x) >> BIT_SHIFT_EXQ_AVAL_PG_V1_8822B) &                             \
+	 BIT_MASK_EXQ_AVAL_PG_V1_8822B)
+#define BIT_SET_EXQ_AVAL_PG_V1_8822B(x, v)                                     \
+	(BIT_CLEAR_EXQ_AVAL_PG_V1_8822B(x) | BIT_EXQ_AVAL_PG_V1_8822B(v))
+
+#define BIT_SHIFT_EXQ_V1_8822B 0
+#define BIT_MASK_EXQ_V1_8822B 0xfff
+#define BIT_EXQ_V1_8822B(x)                                                    \
+	(((x) & BIT_MASK_EXQ_V1_8822B) << BIT_SHIFT_EXQ_V1_8822B)
+#define BITS_EXQ_V1_8822B (BIT_MASK_EXQ_V1_8822B << BIT_SHIFT_EXQ_V1_8822B)
+#define BIT_CLEAR_EXQ_V1_8822B(x) ((x) & (~BITS_EXQ_V1_8822B))
+#define BIT_GET_EXQ_V1_8822B(x)                                                \
+	(((x) >> BIT_SHIFT_EXQ_V1_8822B) & BIT_MASK_EXQ_V1_8822B)
+#define BIT_SET_EXQ_V1_8822B(x, v)                                             \
+	(BIT_CLEAR_EXQ_V1_8822B(x) | BIT_EXQ_V1_8822B(v))
+
+/* 2 REG_FIFOPAGE_INFO_5_8822B */
+
+#define BIT_SHIFT_PUBQ_AVAL_PG_V1_8822B 16
+#define BIT_MASK_PUBQ_AVAL_PG_V1_8822B 0xfff
+#define BIT_PUBQ_AVAL_PG_V1_8822B(x)                                           \
+	(((x) & BIT_MASK_PUBQ_AVAL_PG_V1_8822B)                                \
+	 << BIT_SHIFT_PUBQ_AVAL_PG_V1_8822B)
+#define BITS_PUBQ_AVAL_PG_V1_8822B                                             \
+	(BIT_MASK_PUBQ_AVAL_PG_V1_8822B << BIT_SHIFT_PUBQ_AVAL_PG_V1_8822B)
+#define BIT_CLEAR_PUBQ_AVAL_PG_V1_8822B(x) ((x) & (~BITS_PUBQ_AVAL_PG_V1_8822B))
+#define BIT_GET_PUBQ_AVAL_PG_V1_8822B(x)                                       \
+	(((x) >> BIT_SHIFT_PUBQ_AVAL_PG_V1_8822B) &                            \
+	 BIT_MASK_PUBQ_AVAL_PG_V1_8822B)
+#define BIT_SET_PUBQ_AVAL_PG_V1_8822B(x, v)                                    \
+	(BIT_CLEAR_PUBQ_AVAL_PG_V1_8822B(x) | BIT_PUBQ_AVAL_PG_V1_8822B(v))
+
+#define BIT_SHIFT_PUBQ_V1_8822B 0
+#define BIT_MASK_PUBQ_V1_8822B 0xfff
+#define BIT_PUBQ_V1_8822B(x)                                                   \
+	(((x) & BIT_MASK_PUBQ_V1_8822B) << BIT_SHIFT_PUBQ_V1_8822B)
+#define BITS_PUBQ_V1_8822B (BIT_MASK_PUBQ_V1_8822B << BIT_SHIFT_PUBQ_V1_8822B)
+#define BIT_CLEAR_PUBQ_V1_8822B(x) ((x) & (~BITS_PUBQ_V1_8822B))
+#define BIT_GET_PUBQ_V1_8822B(x)                                               \
+	(((x) >> BIT_SHIFT_PUBQ_V1_8822B) & BIT_MASK_PUBQ_V1_8822B)
+#define BIT_SET_PUBQ_V1_8822B(x, v)                                            \
+	(BIT_CLEAR_PUBQ_V1_8822B(x) | BIT_PUBQ_V1_8822B(v))
+
+/* 2 REG_H2C_HEAD_8822B */
+
+#define BIT_SHIFT_H2C_HEAD_8822B 0
+#define BIT_MASK_H2C_HEAD_8822B 0x3ffff
+#define BIT_H2C_HEAD_8822B(x)                                                  \
+	(((x) & BIT_MASK_H2C_HEAD_8822B) << BIT_SHIFT_H2C_HEAD_8822B)
+#define BITS_H2C_HEAD_8822B                                                    \
+	(BIT_MASK_H2C_HEAD_8822B << BIT_SHIFT_H2C_HEAD_8822B)
+#define BIT_CLEAR_H2C_HEAD_8822B(x) ((x) & (~BITS_H2C_HEAD_8822B))
+#define BIT_GET_H2C_HEAD_8822B(x)                                              \
+	(((x) >> BIT_SHIFT_H2C_HEAD_8822B) & BIT_MASK_H2C_HEAD_8822B)
+#define BIT_SET_H2C_HEAD_8822B(x, v)                                           \
+	(BIT_CLEAR_H2C_HEAD_8822B(x) | BIT_H2C_HEAD_8822B(v))
+
+/* 2 REG_H2C_TAIL_8822B */
+
+#define BIT_SHIFT_H2C_TAIL_8822B 0
+#define BIT_MASK_H2C_TAIL_8822B 0x3ffff
+#define BIT_H2C_TAIL_8822B(x)                                                  \
+	(((x) & BIT_MASK_H2C_TAIL_8822B) << BIT_SHIFT_H2C_TAIL_8822B)
+#define BITS_H2C_TAIL_8822B                                                    \
+	(BIT_MASK_H2C_TAIL_8822B << BIT_SHIFT_H2C_TAIL_8822B)
+#define BIT_CLEAR_H2C_TAIL_8822B(x) ((x) & (~BITS_H2C_TAIL_8822B))
+#define BIT_GET_H2C_TAIL_8822B(x)                                              \
+	(((x) >> BIT_SHIFT_H2C_TAIL_8822B) & BIT_MASK_H2C_TAIL_8822B)
+#define BIT_SET_H2C_TAIL_8822B(x, v)                                           \
+	(BIT_CLEAR_H2C_TAIL_8822B(x) | BIT_H2C_TAIL_8822B(v))
+
+/* 2 REG_H2C_READ_ADDR_8822B */
+
+#define BIT_SHIFT_H2C_READ_ADDR_8822B 0
+#define BIT_MASK_H2C_READ_ADDR_8822B 0x3ffff
+#define BIT_H2C_READ_ADDR_8822B(x)                                             \
+	(((x) & BIT_MASK_H2C_READ_ADDR_8822B) << BIT_SHIFT_H2C_READ_ADDR_8822B)
+#define BITS_H2C_READ_ADDR_8822B                                               \
+	(BIT_MASK_H2C_READ_ADDR_8822B << BIT_SHIFT_H2C_READ_ADDR_8822B)
+#define BIT_CLEAR_H2C_READ_ADDR_8822B(x) ((x) & (~BITS_H2C_READ_ADDR_8822B))
+#define BIT_GET_H2C_READ_ADDR_8822B(x)                                         \
+	(((x) >> BIT_SHIFT_H2C_READ_ADDR_8822B) & BIT_MASK_H2C_READ_ADDR_8822B)
+#define BIT_SET_H2C_READ_ADDR_8822B(x, v)                                      \
+	(BIT_CLEAR_H2C_READ_ADDR_8822B(x) | BIT_H2C_READ_ADDR_8822B(v))
+
+/* 2 REG_H2C_WR_ADDR_8822B */
+
+#define BIT_SHIFT_H2C_WR_ADDR_8822B 0
+#define BIT_MASK_H2C_WR_ADDR_8822B 0x3ffff
+#define BIT_H2C_WR_ADDR_8822B(x)                                               \
+	(((x) & BIT_MASK_H2C_WR_ADDR_8822B) << BIT_SHIFT_H2C_WR_ADDR_8822B)
+#define BITS_H2C_WR_ADDR_8822B                                                 \
+	(BIT_MASK_H2C_WR_ADDR_8822B << BIT_SHIFT_H2C_WR_ADDR_8822B)
+#define BIT_CLEAR_H2C_WR_ADDR_8822B(x) ((x) & (~BITS_H2C_WR_ADDR_8822B))
+#define BIT_GET_H2C_WR_ADDR_8822B(x)                                           \
+	(((x) >> BIT_SHIFT_H2C_WR_ADDR_8822B) & BIT_MASK_H2C_WR_ADDR_8822B)
+#define BIT_SET_H2C_WR_ADDR_8822B(x, v)                                        \
+	(BIT_CLEAR_H2C_WR_ADDR_8822B(x) | BIT_H2C_WR_ADDR_8822B(v))
+
+/* 2 REG_H2C_INFO_8822B */
+#define BIT_H2C_SPACE_VLD_8822B BIT(3)
+#define BIT_H2C_WR_ADDR_RST_8822B BIT(2)
+
+#define BIT_SHIFT_H2C_LEN_SEL_8822B 0
+#define BIT_MASK_H2C_LEN_SEL_8822B 0x3
+#define BIT_H2C_LEN_SEL_8822B(x)                                               \
+	(((x) & BIT_MASK_H2C_LEN_SEL_8822B) << BIT_SHIFT_H2C_LEN_SEL_8822B)
+#define BITS_H2C_LEN_SEL_8822B                                                 \
+	(BIT_MASK_H2C_LEN_SEL_8822B << BIT_SHIFT_H2C_LEN_SEL_8822B)
+#define BIT_CLEAR_H2C_LEN_SEL_8822B(x) ((x) & (~BITS_H2C_LEN_SEL_8822B))
+#define BIT_GET_H2C_LEN_SEL_8822B(x)                                           \
+	(((x) >> BIT_SHIFT_H2C_LEN_SEL_8822B) & BIT_MASK_H2C_LEN_SEL_8822B)
+#define BIT_SET_H2C_LEN_SEL_8822B(x, v)                                        \
+	(BIT_CLEAR_H2C_LEN_SEL_8822B(x) | BIT_H2C_LEN_SEL_8822B(v))
+
+/* 2 REG_RXDMA_AGG_PG_TH_8822B */
+#define BIT_USB_RXDMA_AGG_EN_8822B BIT(31)
+#define BIT_EN_PRE_CALC_8822B BIT(29)
+#define BIT_RXAGG_SW_EN_8822B BIT(28)
+#define BIT_RXAGG_SW_TRIG_8822B BIT(27)
+
+#define BIT_SHIFT_PKT_NUM_WOL_8822B 16
+#define BIT_MASK_PKT_NUM_WOL_8822B 0xff
+#define BIT_PKT_NUM_WOL_8822B(x)                                               \
+	(((x) & BIT_MASK_PKT_NUM_WOL_8822B) << BIT_SHIFT_PKT_NUM_WOL_8822B)
+#define BITS_PKT_NUM_WOL_8822B                                                 \
+	(BIT_MASK_PKT_NUM_WOL_8822B << BIT_SHIFT_PKT_NUM_WOL_8822B)
+#define BIT_CLEAR_PKT_NUM_WOL_8822B(x) ((x) & (~BITS_PKT_NUM_WOL_8822B))
+#define BIT_GET_PKT_NUM_WOL_8822B(x)                                           \
+	(((x) >> BIT_SHIFT_PKT_NUM_WOL_8822B) & BIT_MASK_PKT_NUM_WOL_8822B)
+#define BIT_SET_PKT_NUM_WOL_8822B(x, v)                                        \
+	(BIT_CLEAR_PKT_NUM_WOL_8822B(x) | BIT_PKT_NUM_WOL_8822B(v))
+
+#define BIT_SHIFT_DMA_AGG_TO_V1_8822B 8
+#define BIT_MASK_DMA_AGG_TO_V1_8822B 0xff
+#define BIT_DMA_AGG_TO_V1_8822B(x)                                             \
+	(((x) & BIT_MASK_DMA_AGG_TO_V1_8822B) << BIT_SHIFT_DMA_AGG_TO_V1_8822B)
+#define BITS_DMA_AGG_TO_V1_8822B                                               \
+	(BIT_MASK_DMA_AGG_TO_V1_8822B << BIT_SHIFT_DMA_AGG_TO_V1_8822B)
+#define BIT_CLEAR_DMA_AGG_TO_V1_8822B(x) ((x) & (~BITS_DMA_AGG_TO_V1_8822B))
+#define BIT_GET_DMA_AGG_TO_V1_8822B(x)                                         \
+	(((x) >> BIT_SHIFT_DMA_AGG_TO_V1_8822B) & BIT_MASK_DMA_AGG_TO_V1_8822B)
+#define BIT_SET_DMA_AGG_TO_V1_8822B(x, v)                                      \
+	(BIT_CLEAR_DMA_AGG_TO_V1_8822B(x) | BIT_DMA_AGG_TO_V1_8822B(v))
+
+#define BIT_SHIFT_RXDMA_AGG_PG_TH_8822B 0
+#define BIT_MASK_RXDMA_AGG_PG_TH_8822B 0xff
+#define BIT_RXDMA_AGG_PG_TH_8822B(x)                                           \
+	(((x) & BIT_MASK_RXDMA_AGG_PG_TH_8822B)                                \
+	 << BIT_SHIFT_RXDMA_AGG_PG_TH_8822B)
+#define BITS_RXDMA_AGG_PG_TH_8822B                                             \
+	(BIT_MASK_RXDMA_AGG_PG_TH_8822B << BIT_SHIFT_RXDMA_AGG_PG_TH_8822B)
+#define BIT_CLEAR_RXDMA_AGG_PG_TH_8822B(x) ((x) & (~BITS_RXDMA_AGG_PG_TH_8822B))
+#define BIT_GET_RXDMA_AGG_PG_TH_8822B(x)                                       \
+	(((x) >> BIT_SHIFT_RXDMA_AGG_PG_TH_8822B) &                            \
+	 BIT_MASK_RXDMA_AGG_PG_TH_8822B)
+#define BIT_SET_RXDMA_AGG_PG_TH_8822B(x, v)                                    \
+	(BIT_CLEAR_RXDMA_AGG_PG_TH_8822B(x) | BIT_RXDMA_AGG_PG_TH_8822B(v))
+
+/* 2 REG_RXPKT_NUM_8822B */
+
+#define BIT_SHIFT_RXPKT_NUM_8822B 24
+#define BIT_MASK_RXPKT_NUM_8822B 0xff
+#define BIT_RXPKT_NUM_8822B(x)                                                 \
+	(((x) & BIT_MASK_RXPKT_NUM_8822B) << BIT_SHIFT_RXPKT_NUM_8822B)
+#define BITS_RXPKT_NUM_8822B                                                   \
+	(BIT_MASK_RXPKT_NUM_8822B << BIT_SHIFT_RXPKT_NUM_8822B)
+#define BIT_CLEAR_RXPKT_NUM_8822B(x) ((x) & (~BITS_RXPKT_NUM_8822B))
+#define BIT_GET_RXPKT_NUM_8822B(x)                                             \
+	(((x) >> BIT_SHIFT_RXPKT_NUM_8822B) & BIT_MASK_RXPKT_NUM_8822B)
+#define BIT_SET_RXPKT_NUM_8822B(x, v)                                          \
+	(BIT_CLEAR_RXPKT_NUM_8822B(x) | BIT_RXPKT_NUM_8822B(v))
+
+#define BIT_SHIFT_FW_UPD_RDPTR19_TO_16_8822B 20
+#define BIT_MASK_FW_UPD_RDPTR19_TO_16_8822B 0xf
+#define BIT_FW_UPD_RDPTR19_TO_16_8822B(x)                                      \
+	(((x) & BIT_MASK_FW_UPD_RDPTR19_TO_16_8822B)                           \
+	 << BIT_SHIFT_FW_UPD_RDPTR19_TO_16_8822B)
+#define BITS_FW_UPD_RDPTR19_TO_16_8822B                                        \
+	(BIT_MASK_FW_UPD_RDPTR19_TO_16_8822B                                   \
+	 << BIT_SHIFT_FW_UPD_RDPTR19_TO_16_8822B)
+#define BIT_CLEAR_FW_UPD_RDPTR19_TO_16_8822B(x)                                \
+	((x) & (~BITS_FW_UPD_RDPTR19_TO_16_8822B))
+#define BIT_GET_FW_UPD_RDPTR19_TO_16_8822B(x)                                  \
+	(((x) >> BIT_SHIFT_FW_UPD_RDPTR19_TO_16_8822B) &                       \
+	 BIT_MASK_FW_UPD_RDPTR19_TO_16_8822B)
+#define BIT_SET_FW_UPD_RDPTR19_TO_16_8822B(x, v)                               \
+	(BIT_CLEAR_FW_UPD_RDPTR19_TO_16_8822B(x) |                             \
+	 BIT_FW_UPD_RDPTR19_TO_16_8822B(v))
+
+#define BIT_RXDMA_REQ_8822B BIT(19)
+#define BIT_RW_RELEASE_EN_8822B BIT(18)
+#define BIT_RXDMA_IDLE_8822B BIT(17)
+#define BIT_RXPKT_RELEASE_POLL_8822B BIT(16)
+
+#define BIT_SHIFT_FW_UPD_RDPTR_8822B 0
+#define BIT_MASK_FW_UPD_RDPTR_8822B 0xffff
+#define BIT_FW_UPD_RDPTR_8822B(x)                                              \
+	(((x) & BIT_MASK_FW_UPD_RDPTR_8822B) << BIT_SHIFT_FW_UPD_RDPTR_8822B)
+#define BITS_FW_UPD_RDPTR_8822B                                                \
+	(BIT_MASK_FW_UPD_RDPTR_8822B << BIT_SHIFT_FW_UPD_RDPTR_8822B)
+#define BIT_CLEAR_FW_UPD_RDPTR_8822B(x) ((x) & (~BITS_FW_UPD_RDPTR_8822B))
+#define BIT_GET_FW_UPD_RDPTR_8822B(x)                                          \
+	(((x) >> BIT_SHIFT_FW_UPD_RDPTR_8822B) & BIT_MASK_FW_UPD_RDPTR_8822B)
+#define BIT_SET_FW_UPD_RDPTR_8822B(x, v)                                       \
+	(BIT_CLEAR_FW_UPD_RDPTR_8822B(x) | BIT_FW_UPD_RDPTR_8822B(v))
+
+/* 2 REG_RXDMA_STATUS_8822B */
+#define BIT_C2H_PKT_OVF_8822B BIT(7)
+#define BIT_AGG_CONFGI_ISSUE_8822B BIT(6)
+#define BIT_FW_POLL_ISSUE_8822B BIT(5)
+#define BIT_RX_DATA_UDN_8822B BIT(4)
+#define BIT_RX_SFF_UDN_8822B BIT(3)
+#define BIT_RX_SFF_OVF_8822B BIT(2)
+#define BIT_RXPKT_OVF_8822B BIT(0)
+
+/* 2 REG_RXDMA_DPR_8822B */
+
+#define BIT_SHIFT_RDE_DEBUG_8822B 0
+#define BIT_MASK_RDE_DEBUG_8822B 0xffffffffL
+#define BIT_RDE_DEBUG_8822B(x)                                                 \
+	(((x) & BIT_MASK_RDE_DEBUG_8822B) << BIT_SHIFT_RDE_DEBUG_8822B)
+#define BITS_RDE_DEBUG_8822B                                                   \
+	(BIT_MASK_RDE_DEBUG_8822B << BIT_SHIFT_RDE_DEBUG_8822B)
+#define BIT_CLEAR_RDE_DEBUG_8822B(x) ((x) & (~BITS_RDE_DEBUG_8822B))
+#define BIT_GET_RDE_DEBUG_8822B(x)                                             \
+	(((x) >> BIT_SHIFT_RDE_DEBUG_8822B) & BIT_MASK_RDE_DEBUG_8822B)
+#define BIT_SET_RDE_DEBUG_8822B(x, v)                                          \
+	(BIT_CLEAR_RDE_DEBUG_8822B(x) | BIT_RDE_DEBUG_8822B(v))
+
+/* 2 REG_RXDMA_MODE_8822B */
+
+#define BIT_SHIFT_PKTNUM_TH_V2_8822B 24
+#define BIT_MASK_PKTNUM_TH_V2_8822B 0x1f
+#define BIT_PKTNUM_TH_V2_8822B(x)                                              \
+	(((x) & BIT_MASK_PKTNUM_TH_V2_8822B) << BIT_SHIFT_PKTNUM_TH_V2_8822B)
+#define BITS_PKTNUM_TH_V2_8822B                                                \
+	(BIT_MASK_PKTNUM_TH_V2_8822B << BIT_SHIFT_PKTNUM_TH_V2_8822B)
+#define BIT_CLEAR_PKTNUM_TH_V2_8822B(x) ((x) & (~BITS_PKTNUM_TH_V2_8822B))
+#define BIT_GET_PKTNUM_TH_V2_8822B(x)                                          \
+	(((x) >> BIT_SHIFT_PKTNUM_TH_V2_8822B) & BIT_MASK_PKTNUM_TH_V2_8822B)
+#define BIT_SET_PKTNUM_TH_V2_8822B(x, v)                                       \
+	(BIT_CLEAR_PKTNUM_TH_V2_8822B(x) | BIT_PKTNUM_TH_V2_8822B(v))
+
+#define BIT_TXBA_BREAK_USBAGG_8822B BIT(23)
+
+#define BIT_SHIFT_PKTLEN_PARA_8822B 16
+#define BIT_MASK_PKTLEN_PARA_8822B 0x7
+#define BIT_PKTLEN_PARA_8822B(x)                                               \
+	(((x) & BIT_MASK_PKTLEN_PARA_8822B) << BIT_SHIFT_PKTLEN_PARA_8822B)
+#define BITS_PKTLEN_PARA_8822B                                                 \
+	(BIT_MASK_PKTLEN_PARA_8822B << BIT_SHIFT_PKTLEN_PARA_8822B)
+#define BIT_CLEAR_PKTLEN_PARA_8822B(x) ((x) & (~BITS_PKTLEN_PARA_8822B))
+#define BIT_GET_PKTLEN_PARA_8822B(x)                                           \
+	(((x) >> BIT_SHIFT_PKTLEN_PARA_8822B) & BIT_MASK_PKTLEN_PARA_8822B)
+#define BIT_SET_PKTLEN_PARA_8822B(x, v)                                        \
+	(BIT_CLEAR_PKTLEN_PARA_8822B(x) | BIT_PKTLEN_PARA_8822B(v))
+
+/* 2 REG_NOT_VALID_8822B */
+
+/* 2 REG_NOT_VALID_8822B */
+
+/* 2 REG_NOT_VALID_8822B */
+
+#define BIT_SHIFT_BURST_SIZE_8822B 4
+#define BIT_MASK_BURST_SIZE_8822B 0x3
+#define BIT_BURST_SIZE_8822B(x)                                                \
+	(((x) & BIT_MASK_BURST_SIZE_8822B) << BIT_SHIFT_BURST_SIZE_8822B)
+#define BITS_BURST_SIZE_8822B                                                  \
+	(BIT_MASK_BURST_SIZE_8822B << BIT_SHIFT_BURST_SIZE_8822B)
+#define BIT_CLEAR_BURST_SIZE_8822B(x) ((x) & (~BITS_BURST_SIZE_8822B))
+#define BIT_GET_BURST_SIZE_8822B(x)                                            \
+	(((x) >> BIT_SHIFT_BURST_SIZE_8822B) & BIT_MASK_BURST_SIZE_8822B)
+#define BIT_SET_BURST_SIZE_8822B(x, v)                                         \
+	(BIT_CLEAR_BURST_SIZE_8822B(x) | BIT_BURST_SIZE_8822B(v))
+
+#define BIT_SHIFT_BURST_CNT_8822B 2
+#define BIT_MASK_BURST_CNT_8822B 0x3
+#define BIT_BURST_CNT_8822B(x)                                                 \
+	(((x) & BIT_MASK_BURST_CNT_8822B) << BIT_SHIFT_BURST_CNT_8822B)
+#define BITS_BURST_CNT_8822B                                                   \
+	(BIT_MASK_BURST_CNT_8822B << BIT_SHIFT_BURST_CNT_8822B)
+#define BIT_CLEAR_BURST_CNT_8822B(x) ((x) & (~BITS_BURST_CNT_8822B))
+#define BIT_GET_BURST_CNT_8822B(x)                                             \
+	(((x) >> BIT_SHIFT_BURST_CNT_8822B) & BIT_MASK_BURST_CNT_8822B)
+#define BIT_SET_BURST_CNT_8822B(x, v)                                          \
+	(BIT_CLEAR_BURST_CNT_8822B(x) | BIT_BURST_CNT_8822B(v))
+
+#define BIT_DMA_MODE_8822B BIT(1)
+
+/* 2 REG_C2H_PKT_8822B */
+
+#define BIT_SHIFT_R_C2H_STR_ADDR_16_TO_19_8822B 24
+#define BIT_MASK_R_C2H_STR_ADDR_16_TO_19_8822B 0xf
+#define BIT_R_C2H_STR_ADDR_16_TO_19_8822B(x)                                   \
+	(((x) & BIT_MASK_R_C2H_STR_ADDR_16_TO_19_8822B)                        \
+	 << BIT_SHIFT_R_C2H_STR_ADDR_16_TO_19_8822B)
+#define BITS_R_C2H_STR_ADDR_16_TO_19_8822B                                     \
+	(BIT_MASK_R_C2H_STR_ADDR_16_TO_19_8822B                                \
+	 << BIT_SHIFT_R_C2H_STR_ADDR_16_TO_19_8822B)
+#define BIT_CLEAR_R_C2H_STR_ADDR_16_TO_19_8822B(x)                             \
+	((x) & (~BITS_R_C2H_STR_ADDR_16_TO_19_8822B))
+#define BIT_GET_R_C2H_STR_ADDR_16_TO_19_8822B(x)                               \
+	(((x) >> BIT_SHIFT_R_C2H_STR_ADDR_16_TO_19_8822B) &                    \
+	 BIT_MASK_R_C2H_STR_ADDR_16_TO_19_8822B)
+#define BIT_SET_R_C2H_STR_ADDR_16_TO_19_8822B(x, v)                            \
+	(BIT_CLEAR_R_C2H_STR_ADDR_16_TO_19_8822B(x) |                          \
+	 BIT_R_C2H_STR_ADDR_16_TO_19_8822B(v))
+
+#define BIT_R_C2H_PKT_REQ_8822B BIT(16)
+
+#define BIT_SHIFT_R_C2H_STR_ADDR_8822B 0
+#define BIT_MASK_R_C2H_STR_ADDR_8822B 0xffff
+#define BIT_R_C2H_STR_ADDR_8822B(x)                                            \
+	(((x) & BIT_MASK_R_C2H_STR_ADDR_8822B)                                 \
+	 << BIT_SHIFT_R_C2H_STR_ADDR_8822B)
+#define BITS_R_C2H_STR_ADDR_8822B                                              \
+	(BIT_MASK_R_C2H_STR_ADDR_8822B << BIT_SHIFT_R_C2H_STR_ADDR_8822B)
+#define BIT_CLEAR_R_C2H_STR_ADDR_8822B(x) ((x) & (~BITS_R_C2H_STR_ADDR_8822B))
+#define BIT_GET_R_C2H_STR_ADDR_8822B(x)                                        \
+	(((x) >> BIT_SHIFT_R_C2H_STR_ADDR_8822B) &                             \
+	 BIT_MASK_R_C2H_STR_ADDR_8822B)
+#define BIT_SET_R_C2H_STR_ADDR_8822B(x, v)                                     \
+	(BIT_CLEAR_R_C2H_STR_ADDR_8822B(x) | BIT_R_C2H_STR_ADDR_8822B(v))
+
+/* 2 REG_FWFF_C2H_8822B */
+
+#define BIT_SHIFT_C2H_DMA_ADDR_8822B 0
+#define BIT_MASK_C2H_DMA_ADDR_8822B 0x3ffff
+#define BIT_C2H_DMA_ADDR_8822B(x)                                              \
+	(((x) & BIT_MASK_C2H_DMA_ADDR_8822B) << BIT_SHIFT_C2H_DMA_ADDR_8822B)
+#define BITS_C2H_DMA_ADDR_8822B                                                \
+	(BIT_MASK_C2H_DMA_ADDR_8822B << BIT_SHIFT_C2H_DMA_ADDR_8822B)
+#define BIT_CLEAR_C2H_DMA_ADDR_8822B(x) ((x) & (~BITS_C2H_DMA_ADDR_8822B))
+#define BIT_GET_C2H_DMA_ADDR_8822B(x)                                          \
+	(((x) >> BIT_SHIFT_C2H_DMA_ADDR_8822B) & BIT_MASK_C2H_DMA_ADDR_8822B)
+#define BIT_SET_C2H_DMA_ADDR_8822B(x, v)                                       \
+	(BIT_CLEAR_C2H_DMA_ADDR_8822B(x) | BIT_C2H_DMA_ADDR_8822B(v))
+
+/* 2 REG_FWFF_CTRL_8822B */
+#define BIT_FWFF_DMAPKT_REQ_8822B BIT(31)
+
+#define BIT_SHIFT_FWFF_DMA_PKT_NUM_8822B 16
+#define BIT_MASK_FWFF_DMA_PKT_NUM_8822B 0xff
+#define BIT_FWFF_DMA_PKT_NUM_8822B(x)                                          \
+	(((x) & BIT_MASK_FWFF_DMA_PKT_NUM_8822B)                               \
+	 << BIT_SHIFT_FWFF_DMA_PKT_NUM_8822B)
+#define BITS_FWFF_DMA_PKT_NUM_8822B                                            \
+	(BIT_MASK_FWFF_DMA_PKT_NUM_8822B << BIT_SHIFT_FWFF_DMA_PKT_NUM_8822B)
+#define BIT_CLEAR_FWFF_DMA_PKT_NUM_8822B(x)                                    \
+	((x) & (~BITS_FWFF_DMA_PKT_NUM_8822B))
+#define BIT_GET_FWFF_DMA_PKT_NUM_8822B(x)                                      \
+	(((x) >> BIT_SHIFT_FWFF_DMA_PKT_NUM_8822B) &                           \
+	 BIT_MASK_FWFF_DMA_PKT_NUM_8822B)
+#define BIT_SET_FWFF_DMA_PKT_NUM_8822B(x, v)                                   \
+	(BIT_CLEAR_FWFF_DMA_PKT_NUM_8822B(x) | BIT_FWFF_DMA_PKT_NUM_8822B(v))
+
+#define BIT_SHIFT_FWFF_STR_ADDR_8822B 0
+#define BIT_MASK_FWFF_STR_ADDR_8822B 0xffff
+#define BIT_FWFF_STR_ADDR_8822B(x)                                             \
+	(((x) & BIT_MASK_FWFF_STR_ADDR_8822B) << BIT_SHIFT_FWFF_STR_ADDR_8822B)
+#define BITS_FWFF_STR_ADDR_8822B                                               \
+	(BIT_MASK_FWFF_STR_ADDR_8822B << BIT_SHIFT_FWFF_STR_ADDR_8822B)
+#define BIT_CLEAR_FWFF_STR_ADDR_8822B(x) ((x) & (~BITS_FWFF_STR_ADDR_8822B))
+#define BIT_GET_FWFF_STR_ADDR_8822B(x)                                         \
+	(((x) >> BIT_SHIFT_FWFF_STR_ADDR_8822B) & BIT_MASK_FWFF_STR_ADDR_8822B)
+#define BIT_SET_FWFF_STR_ADDR_8822B(x, v)                                      \
+	(BIT_CLEAR_FWFF_STR_ADDR_8822B(x) | BIT_FWFF_STR_ADDR_8822B(v))
+
+/* 2 REG_FWFF_PKT_INFO_8822B */
+
+#define BIT_SHIFT_FWFF_PKT_QUEUED_8822B 16
+#define BIT_MASK_FWFF_PKT_QUEUED_8822B 0xff
+#define BIT_FWFF_PKT_QUEUED_8822B(x)                                           \
+	(((x) & BIT_MASK_FWFF_PKT_QUEUED_8822B)                                \
+	 << BIT_SHIFT_FWFF_PKT_QUEUED_8822B)
+#define BITS_FWFF_PKT_QUEUED_8822B                                             \
+	(BIT_MASK_FWFF_PKT_QUEUED_8822B << BIT_SHIFT_FWFF_PKT_QUEUED_8822B)
+#define BIT_CLEAR_FWFF_PKT_QUEUED_8822B(x) ((x) & (~BITS_FWFF_PKT_QUEUED_8822B))
+#define BIT_GET_FWFF_PKT_QUEUED_8822B(x)                                       \
+	(((x) >> BIT_SHIFT_FWFF_PKT_QUEUED_8822B) &                            \
+	 BIT_MASK_FWFF_PKT_QUEUED_8822B)
+#define BIT_SET_FWFF_PKT_QUEUED_8822B(x, v)                                    \
+	(BIT_CLEAR_FWFF_PKT_QUEUED_8822B(x) | BIT_FWFF_PKT_QUEUED_8822B(v))
+
+#define BIT_SHIFT_FWFF_PKT_STR_ADDR_8822B 0
+#define BIT_MASK_FWFF_PKT_STR_ADDR_8822B 0xffff
+#define BIT_FWFF_PKT_STR_ADDR_8822B(x)                                         \
+	(((x) & BIT_MASK_FWFF_PKT_STR_ADDR_8822B)                              \
+	 << BIT_SHIFT_FWFF_PKT_STR_ADDR_8822B)
+#define BITS_FWFF_PKT_STR_ADDR_8822B                                           \
+	(BIT_MASK_FWFF_PKT_STR_ADDR_8822B << BIT_SHIFT_FWFF_PKT_STR_ADDR_8822B)
+#define BIT_CLEAR_FWFF_PKT_STR_ADDR_8822B(x)                                   \
+	((x) & (~BITS_FWFF_PKT_STR_ADDR_8822B))
+#define BIT_GET_FWFF_PKT_STR_ADDR_8822B(x)                                     \
+	(((x) >> BIT_SHIFT_FWFF_PKT_STR_ADDR_8822B) &                          \
+	 BIT_MASK_FWFF_PKT_STR_ADDR_8822B)
+#define BIT_SET_FWFF_PKT_STR_ADDR_8822B(x, v)                                  \
+	(BIT_CLEAR_FWFF_PKT_STR_ADDR_8822B(x) | BIT_FWFF_PKT_STR_ADDR_8822B(v))
+
+/* 2 REG_NOT_VALID_8822B */
+
+/* 2 REG_DDMA_CH0SA_8822B */
+
+#define BIT_SHIFT_DDMACH0_SA_8822B 0
+#define BIT_MASK_DDMACH0_SA_8822B 0xffffffffL
+#define BIT_DDMACH0_SA_8822B(x)                                                \
+	(((x) & BIT_MASK_DDMACH0_SA_8822B) << BIT_SHIFT_DDMACH0_SA_8822B)
+#define BITS_DDMACH0_SA_8822B                                                  \
+	(BIT_MASK_DDMACH0_SA_8822B << BIT_SHIFT_DDMACH0_SA_8822B)
+#define BIT_CLEAR_DDMACH0_SA_8822B(x) ((x) & (~BITS_DDMACH0_SA_8822B))
+#define BIT_GET_DDMACH0_SA_8822B(x)                                            \
+	(((x) >> BIT_SHIFT_DDMACH0_SA_8822B) & BIT_MASK_DDMACH0_SA_8822B)
+#define BIT_SET_DDMACH0_SA_8822B(x, v)                                         \
+	(BIT_CLEAR_DDMACH0_SA_8822B(x) | BIT_DDMACH0_SA_8822B(v))
+
+/* 2 REG_DDMA_CH0DA_8822B */
+
+#define BIT_SHIFT_DDMACH0_DA_8822B 0
+#define BIT_MASK_DDMACH0_DA_8822B 0xffffffffL
+#define BIT_DDMACH0_DA_8822B(x)                                                \
+	(((x) & BIT_MASK_DDMACH0_DA_8822B) << BIT_SHIFT_DDMACH0_DA_8822B)
+#define BITS_DDMACH0_DA_8822B                                                  \
+	(BIT_MASK_DDMACH0_DA_8822B << BIT_SHIFT_DDMACH0_DA_8822B)
+#define BIT_CLEAR_DDMACH0_DA_8822B(x) ((x) & (~BITS_DDMACH0_DA_8822B))
+#define BIT_GET_DDMACH0_DA_8822B(x)                                            \
+	(((x) >> BIT_SHIFT_DDMACH0_DA_8822B) & BIT_MASK_DDMACH0_DA_8822B)
+#define BIT_SET_DDMACH0_DA_8822B(x, v)                                         \
+	(BIT_CLEAR_DDMACH0_DA_8822B(x) | BIT_DDMACH0_DA_8822B(v))
+
+/* 2 REG_DDMA_CH0CTRL_8822B */
+#define BIT_DDMACH0_OWN_8822B BIT(31)
+#define BIT_DDMACH0_IDMEM_ERR_8822B BIT(30)
+#define BIT_DDMACH0_CHKSUM_EN_8822B BIT(29)
+#define BIT_DDMACH0_DA_W_DISABLE_8822B BIT(28)
+#define BIT_DDMACH0_CHKSUM_STS_8822B BIT(27)
+#define BIT_DDMACH0_DDMA_MODE_8822B BIT(26)
+#define BIT_DDMACH0_RESET_CHKSUM_STS_8822B BIT(25)
+#define BIT_DDMACH0_CHKSUM_CONT_8822B BIT(24)
+
+#define BIT_SHIFT_DDMACH0_DLEN_8822B 0
+#define BIT_MASK_DDMACH0_DLEN_8822B 0x3ffff
+#define BIT_DDMACH0_DLEN_8822B(x)                                              \
+	(((x) & BIT_MASK_DDMACH0_DLEN_8822B) << BIT_SHIFT_DDMACH0_DLEN_8822B)
+#define BITS_DDMACH0_DLEN_8822B                                                \
+	(BIT_MASK_DDMACH0_DLEN_8822B << BIT_SHIFT_DDMACH0_DLEN_8822B)
+#define BIT_CLEAR_DDMACH0_DLEN_8822B(x) ((x) & (~BITS_DDMACH0_DLEN_8822B))
+#define BIT_GET_DDMACH0_DLEN_8822B(x)                                          \
+	(((x) >> BIT_SHIFT_DDMACH0_DLEN_8822B) & BIT_MASK_DDMACH0_DLEN_8822B)
+#define BIT_SET_DDMACH0_DLEN_8822B(x, v)                                       \
+	(BIT_CLEAR_DDMACH0_DLEN_8822B(x) | BIT_DDMACH0_DLEN_8822B(v))
+
+/* 2 REG_DDMA_CH1SA_8822B */
+
+#define BIT_SHIFT_DDMACH1_SA_8822B 0
+#define BIT_MASK_DDMACH1_SA_8822B 0xffffffffL
+#define BIT_DDMACH1_SA_8822B(x)                                                \
+	(((x) & BIT_MASK_DDMACH1_SA_8822B) << BIT_SHIFT_DDMACH1_SA_8822B)
+#define BITS_DDMACH1_SA_8822B                                                  \
+	(BIT_MASK_DDMACH1_SA_8822B << BIT_SHIFT_DDMACH1_SA_8822B)
+#define BIT_CLEAR_DDMACH1_SA_8822B(x) ((x) & (~BITS_DDMACH1_SA_8822B))
+#define BIT_GET_DDMACH1_SA_8822B(x)                                            \
+	(((x) >> BIT_SHIFT_DDMACH1_SA_8822B) & BIT_MASK_DDMACH1_SA_8822B)
+#define BIT_SET_DDMACH1_SA_8822B(x, v)                                         \
+	(BIT_CLEAR_DDMACH1_SA_8822B(x) | BIT_DDMACH1_SA_8822B(v))
+
+/* 2 REG_DDMA_CH1DA_8822B */
+
+#define BIT_SHIFT_DDMACH1_DA_8822B 0
+#define BIT_MASK_DDMACH1_DA_8822B 0xffffffffL
+#define BIT_DDMACH1_DA_8822B(x)                                                \
+	(((x) & BIT_MASK_DDMACH1_DA_8822B) << BIT_SHIFT_DDMACH1_DA_8822B)
+#define BITS_DDMACH1_DA_8822B                                                  \
+	(BIT_MASK_DDMACH1_DA_8822B << BIT_SHIFT_DDMACH1_DA_8822B)
+#define BIT_CLEAR_DDMACH1_DA_8822B(x) ((x) & (~BITS_DDMACH1_DA_8822B))
+#define BIT_GET_DDMACH1_DA_8822B(x)                                            \
+	(((x) >> BIT_SHIFT_DDMACH1_DA_8822B) & BIT_MASK_DDMACH1_DA_8822B)
+#define BIT_SET_DDMACH1_DA_8822B(x, v)                                         \
+	(BIT_CLEAR_DDMACH1_DA_8822B(x) | BIT_DDMACH1_DA_8822B(v))
+
+/* 2 REG_DDMA_CH1CTRL_8822B */
+#define BIT_DDMACH1_OWN_8822B BIT(31)
+#define BIT_DDMACH1_IDMEM_ERR_8822B BIT(30)
+#define BIT_DDMACH1_CHKSUM_EN_8822B BIT(29)
+#define BIT_DDMACH1_DA_W_DISABLE_8822B BIT(28)
+#define BIT_DDMACH1_CHKSUM_STS_8822B BIT(27)
+#define BIT_DDMACH1_DDMA_MODE_8822B BIT(26)
+#define BIT_DDMACH1_RESET_CHKSUM_STS_8822B BIT(25)
+#define BIT_DDMACH1_CHKSUM_CONT_8822B BIT(24)
+
+#define BIT_SHIFT_DDMACH1_DLEN_8822B 0
+#define BIT_MASK_DDMACH1_DLEN_8822B 0x3ffff
+#define BIT_DDMACH1_DLEN_8822B(x)                                              \
+	(((x) & BIT_MASK_DDMACH1_DLEN_8822B) << BIT_SHIFT_DDMACH1_DLEN_8822B)
+#define BITS_DDMACH1_DLEN_8822B                                                \
+	(BIT_MASK_DDMACH1_DLEN_8822B << BIT_SHIFT_DDMACH1_DLEN_8822B)
+#define BIT_CLEAR_DDMACH1_DLEN_8822B(x) ((x) & (~BITS_DDMACH1_DLEN_8822B))
+#define BIT_GET_DDMACH1_DLEN_8822B(x)                                          \
+	(((x) >> BIT_SHIFT_DDMACH1_DLEN_8822B) & BIT_MASK_DDMACH1_DLEN_8822B)
+#define BIT_SET_DDMACH1_DLEN_8822B(x, v)                                       \
+	(BIT_CLEAR_DDMACH1_DLEN_8822B(x) | BIT_DDMACH1_DLEN_8822B(v))
+
+/* 2 REG_DDMA_CH2SA_8822B */
+
+#define BIT_SHIFT_DDMACH2_SA_8822B 0
+#define BIT_MASK_DDMACH2_SA_8822B 0xffffffffL
+#define BIT_DDMACH2_SA_8822B(x)                                                \
+	(((x) & BIT_MASK_DDMACH2_SA_8822B) << BIT_SHIFT_DDMACH2_SA_8822B)
+#define BITS_DDMACH2_SA_8822B                                                  \
+	(BIT_MASK_DDMACH2_SA_8822B << BIT_SHIFT_DDMACH2_SA_8822B)
+#define BIT_CLEAR_DDMACH2_SA_8822B(x) ((x) & (~BITS_DDMACH2_SA_8822B))
+#define BIT_GET_DDMACH2_SA_8822B(x)                                            \
+	(((x) >> BIT_SHIFT_DDMACH2_SA_8822B) & BIT_MASK_DDMACH2_SA_8822B)
+#define BIT_SET_DDMACH2_SA_8822B(x, v)                                         \
+	(BIT_CLEAR_DDMACH2_SA_8822B(x) | BIT_DDMACH2_SA_8822B(v))
+
+/* 2 REG_DDMA_CH2DA_8822B */
+
+#define BIT_SHIFT_DDMACH2_DA_8822B 0
+#define BIT_MASK_DDMACH2_DA_8822B 0xffffffffL
+#define BIT_DDMACH2_DA_8822B(x)                                                \
+	(((x) & BIT_MASK_DDMACH2_DA_8822B) << BIT_SHIFT_DDMACH2_DA_8822B)
+#define BITS_DDMACH2_DA_8822B                                                  \
+	(BIT_MASK_DDMACH2_DA_8822B << BIT_SHIFT_DDMACH2_DA_8822B)
+#define BIT_CLEAR_DDMACH2_DA_8822B(x) ((x) & (~BITS_DDMACH2_DA_8822B))
+#define BIT_GET_DDMACH2_DA_8822B(x)                                            \
+	(((x) >> BIT_SHIFT_DDMACH2_DA_8822B) & BIT_MASK_DDMACH2_DA_8822B)
+#define BIT_SET_DDMACH2_DA_8822B(x, v)                                         \
+	(BIT_CLEAR_DDMACH2_DA_8822B(x) | BIT_DDMACH2_DA_8822B(v))
+
+/* 2 REG_DDMA_CH2CTRL_8822B */
+#define BIT_DDMACH2_OWN_8822B BIT(31)
+#define BIT_DDMACH2_IDMEM_ERR_8822B BIT(30)
+#define BIT_DDMACH2_CHKSUM_EN_8822B BIT(29)
+#define BIT_DDMACH2_DA_W_DISABLE_8822B BIT(28)
+#define BIT_DDMACH2_CHKSUM_STS_8822B BIT(27)
+#define BIT_DDMACH2_DDMA_MODE_8822B BIT(26)
+#define BIT_DDMACH2_RESET_CHKSUM_STS_8822B BIT(25)
+#define BIT_DDMACH2_CHKSUM_CONT_8822B BIT(24)
+
+#define BIT_SHIFT_DDMACH2_DLEN_8822B 0
+#define BIT_MASK_DDMACH2_DLEN_8822B 0x3ffff
+#define BIT_DDMACH2_DLEN_8822B(x)                                              \
+	(((x) & BIT_MASK_DDMACH2_DLEN_8822B) << BIT_SHIFT_DDMACH2_DLEN_8822B)
+#define BITS_DDMACH2_DLEN_8822B                                                \
+	(BIT_MASK_DDMACH2_DLEN_8822B << BIT_SHIFT_DDMACH2_DLEN_8822B)
+#define BIT_CLEAR_DDMACH2_DLEN_8822B(x) ((x) & (~BITS_DDMACH2_DLEN_8822B))
+#define BIT_GET_DDMACH2_DLEN_8822B(x)                                          \
+	(((x) >> BIT_SHIFT_DDMACH2_DLEN_8822B) & BIT_MASK_DDMACH2_DLEN_8822B)
+#define BIT_SET_DDMACH2_DLEN_8822B(x, v)                                       \
+	(BIT_CLEAR_DDMACH2_DLEN_8822B(x) | BIT_DDMACH2_DLEN_8822B(v))
+
+/* 2 REG_DDMA_CH3SA_8822B */
+
+#define BIT_SHIFT_DDMACH3_SA_8822B 0
+#define BIT_MASK_DDMACH3_SA_8822B 0xffffffffL
+#define BIT_DDMACH3_SA_8822B(x)                                                \
+	(((x) & BIT_MASK_DDMACH3_SA_8822B) << BIT_SHIFT_DDMACH3_SA_8822B)
+#define BITS_DDMACH3_SA_8822B                                                  \
+	(BIT_MASK_DDMACH3_SA_8822B << BIT_SHIFT_DDMACH3_SA_8822B)
+#define BIT_CLEAR_DDMACH3_SA_8822B(x) ((x) & (~BITS_DDMACH3_SA_8822B))
+#define BIT_GET_DDMACH3_SA_8822B(x)                                            \
+	(((x) >> BIT_SHIFT_DDMACH3_SA_8822B) & BIT_MASK_DDMACH3_SA_8822B)
+#define BIT_SET_DDMACH3_SA_8822B(x, v)                                         \
+	(BIT_CLEAR_DDMACH3_SA_8822B(x) | BIT_DDMACH3_SA_8822B(v))
+
+/* 2 REG_DDMA_CH3DA_8822B */
+
+#define BIT_SHIFT_DDMACH3_DA_8822B 0
+#define BIT_MASK_DDMACH3_DA_8822B 0xffffffffL
+#define BIT_DDMACH3_DA_8822B(x)                                                \
+	(((x) & BIT_MASK_DDMACH3_DA_8822B) << BIT_SHIFT_DDMACH3_DA_8822B)
+#define BITS_DDMACH3_DA_8822B                                                  \
+	(BIT_MASK_DDMACH3_DA_8822B << BIT_SHIFT_DDMACH3_DA_8822B)
+#define BIT_CLEAR_DDMACH3_DA_8822B(x) ((x) & (~BITS_DDMACH3_DA_8822B))
+#define BIT_GET_DDMACH3_DA_8822B(x)                                            \
+	(((x) >> BIT_SHIFT_DDMACH3_DA_8822B) & BIT_MASK_DDMACH3_DA_8822B)
+#define BIT_SET_DDMACH3_DA_8822B(x, v)                                         \
+	(BIT_CLEAR_DDMACH3_DA_8822B(x) | BIT_DDMACH3_DA_8822B(v))
+
+/* 2 REG_DDMA_CH3CTRL_8822B */
+#define BIT_DDMACH3_OWN_8822B BIT(31)
+#define BIT_DDMACH3_IDMEM_ERR_8822B BIT(30)
+#define BIT_DDMACH3_CHKSUM_EN_8822B BIT(29)
+#define BIT_DDMACH3_DA_W_DISABLE_8822B BIT(28)
+#define BIT_DDMACH3_CHKSUM_STS_8822B BIT(27)
+#define BIT_DDMACH3_DDMA_MODE_8822B BIT(26)
+#define BIT_DDMACH3_RESET_CHKSUM_STS_8822B BIT(25)
+#define BIT_DDMACH3_CHKSUM_CONT_8822B BIT(24)
+
+#define BIT_SHIFT_DDMACH3_DLEN_8822B 0
+#define BIT_MASK_DDMACH3_DLEN_8822B 0x3ffff
+#define BIT_DDMACH3_DLEN_8822B(x)                                              \
+	(((x) & BIT_MASK_DDMACH3_DLEN_8822B) << BIT_SHIFT_DDMACH3_DLEN_8822B)
+#define BITS_DDMACH3_DLEN_8822B                                                \
+	(BIT_MASK_DDMACH3_DLEN_8822B << BIT_SHIFT_DDMACH3_DLEN_8822B)
+#define BIT_CLEAR_DDMACH3_DLEN_8822B(x) ((x) & (~BITS_DDMACH3_DLEN_8822B))
+#define BIT_GET_DDMACH3_DLEN_8822B(x)                                          \
+	(((x) >> BIT_SHIFT_DDMACH3_DLEN_8822B) & BIT_MASK_DDMACH3_DLEN_8822B)
+#define BIT_SET_DDMACH3_DLEN_8822B(x, v)                                       \
+	(BIT_CLEAR_DDMACH3_DLEN_8822B(x) | BIT_DDMACH3_DLEN_8822B(v))
+
+/* 2 REG_DDMA_CH4SA_8822B */
+
+#define BIT_SHIFT_DDMACH4_SA_8822B 0
+#define BIT_MASK_DDMACH4_SA_8822B 0xffffffffL
+#define BIT_DDMACH4_SA_8822B(x)                                                \
+	(((x) & BIT_MASK_DDMACH4_SA_8822B) << BIT_SHIFT_DDMACH4_SA_8822B)
+#define BITS_DDMACH4_SA_8822B                                                  \
+	(BIT_MASK_DDMACH4_SA_8822B << BIT_SHIFT_DDMACH4_SA_8822B)
+#define BIT_CLEAR_DDMACH4_SA_8822B(x) ((x) & (~BITS_DDMACH4_SA_8822B))
+#define BIT_GET_DDMACH4_SA_8822B(x)                                            \
+	(((x) >> BIT_SHIFT_DDMACH4_SA_8822B) & BIT_MASK_DDMACH4_SA_8822B)
+#define BIT_SET_DDMACH4_SA_8822B(x, v)                                         \
+	(BIT_CLEAR_DDMACH4_SA_8822B(x) | BIT_DDMACH4_SA_8822B(v))
+
+/* 2 REG_DDMA_CH4DA_8822B */
+
+#define BIT_SHIFT_DDMACH4_DA_8822B 0
+#define BIT_MASK_DDMACH4_DA_8822B 0xffffffffL
+#define BIT_DDMACH4_DA_8822B(x)                                                \
+	(((x) & BIT_MASK_DDMACH4_DA_8822B) << BIT_SHIFT_DDMACH4_DA_8822B)
+#define BITS_DDMACH4_DA_8822B                                                  \
+	(BIT_MASK_DDMACH4_DA_8822B << BIT_SHIFT_DDMACH4_DA_8822B)
+#define BIT_CLEAR_DDMACH4_DA_8822B(x) ((x) & (~BITS_DDMACH4_DA_8822B))
+#define BIT_GET_DDMACH4_DA_8822B(x)                                            \
+	(((x) >> BIT_SHIFT_DDMACH4_DA_8822B) & BIT_MASK_DDMACH4_DA_8822B)
+#define BIT_SET_DDMACH4_DA_8822B(x, v)                                         \
+	(BIT_CLEAR_DDMACH4_DA_8822B(x) | BIT_DDMACH4_DA_8822B(v))
+
+/* 2 REG_DDMA_CH4CTRL_8822B */
+#define BIT_DDMACH4_OWN_8822B BIT(31)
+#define BIT_DDMACH4_IDMEM_ERR_8822B BIT(30)
+#define BIT_DDMACH4_CHKSUM_EN_8822B BIT(29)
+#define BIT_DDMACH4_DA_W_DISABLE_8822B BIT(28)
+#define BIT_DDMACH4_CHKSUM_STS_8822B BIT(27)
+#define BIT_DDMACH4_DDMA_MODE_8822B BIT(26)
+#define BIT_DDMACH4_RESET_CHKSUM_STS_8822B BIT(25)
+#define BIT_DDMACH4_CHKSUM_CONT_8822B BIT(24)
+
+#define BIT_SHIFT_DDMACH4_DLEN_8822B 0
+#define BIT_MASK_DDMACH4_DLEN_8822B 0x3ffff
+#define BIT_DDMACH4_DLEN_8822B(x)                                              \
+	(((x) & BIT_MASK_DDMACH4_DLEN_8822B) << BIT_SHIFT_DDMACH4_DLEN_8822B)
+#define BITS_DDMACH4_DLEN_8822B                                                \
+	(BIT_MASK_DDMACH4_DLEN_8822B << BIT_SHIFT_DDMACH4_DLEN_8822B)
+#define BIT_CLEAR_DDMACH4_DLEN_8822B(x) ((x) & (~BITS_DDMACH4_DLEN_8822B))
+#define BIT_GET_DDMACH4_DLEN_8822B(x)                                          \
+	(((x) >> BIT_SHIFT_DDMACH4_DLEN_8822B) & BIT_MASK_DDMACH4_DLEN_8822B)
+#define BIT_SET_DDMACH4_DLEN_8822B(x, v)                                       \
+	(BIT_CLEAR_DDMACH4_DLEN_8822B(x) | BIT_DDMACH4_DLEN_8822B(v))
+
+/* 2 REG_DDMA_CH5SA_8822B */
+
+#define BIT_SHIFT_DDMACH5_SA_8822B 0
+#define BIT_MASK_DDMACH5_SA_8822B 0xffffffffL
+#define BIT_DDMACH5_SA_8822B(x)                                                \
+	(((x) & BIT_MASK_DDMACH5_SA_8822B) << BIT_SHIFT_DDMACH5_SA_8822B)
+#define BITS_DDMACH5_SA_8822B                                                  \
+	(BIT_MASK_DDMACH5_SA_8822B << BIT_SHIFT_DDMACH5_SA_8822B)
+#define BIT_CLEAR_DDMACH5_SA_8822B(x) ((x) & (~BITS_DDMACH5_SA_8822B))
+#define BIT_GET_DDMACH5_SA_8822B(x)                                            \
+	(((x) >> BIT_SHIFT_DDMACH5_SA_8822B) & BIT_MASK_DDMACH5_SA_8822B)
+#define BIT_SET_DDMACH5_SA_8822B(x, v)                                         \
+	(BIT_CLEAR_DDMACH5_SA_8822B(x) | BIT_DDMACH5_SA_8822B(v))
+
+/* 2 REG_DDMA_CH5DA_8822B */
+
+#define BIT_SHIFT_DDMACH5_DA_8822B 0
+#define BIT_MASK_DDMACH5_DA_8822B 0xffffffffL
+#define BIT_DDMACH5_DA_8822B(x)                                                \
+	(((x) & BIT_MASK_DDMACH5_DA_8822B) << BIT_SHIFT_DDMACH5_DA_8822B)
+#define BITS_DDMACH5_DA_8822B                                                  \
+	(BIT_MASK_DDMACH5_DA_8822B << BIT_SHIFT_DDMACH5_DA_8822B)
+#define BIT_CLEAR_DDMACH5_DA_8822B(x) ((x) & (~BITS_DDMACH5_DA_8822B))
+#define BIT_GET_DDMACH5_DA_8822B(x)                                            \
+	(((x) >> BIT_SHIFT_DDMACH5_DA_8822B) & BIT_MASK_DDMACH5_DA_8822B)
+#define BIT_SET_DDMACH5_DA_8822B(x, v)                                         \
+	(BIT_CLEAR_DDMACH5_DA_8822B(x) | BIT_DDMACH5_DA_8822B(v))
+
+/* 2 REG_REG_DDMA_CH5CTRL_8822B */
+#define BIT_DDMACH5_OWN_8822B BIT(31)
+#define BIT_DDMACH5_IDMEM_ERR_8822B BIT(30)
+#define BIT_DDMACH5_CHKSUM_EN_8822B BIT(29)
+#define BIT_DDMACH5_DA_W_DISABLE_8822B BIT(28)
+#define BIT_DDMACH5_CHKSUM_STS_8822B BIT(27)
+#define BIT_DDMACH5_DDMA_MODE_8822B BIT(26)
+#define BIT_DDMACH5_RESET_CHKSUM_STS_8822B BIT(25)
+#define BIT_DDMACH5_CHKSUM_CONT_8822B BIT(24)
+
+#define BIT_SHIFT_DDMACH5_DLEN_8822B 0
+#define BIT_MASK_DDMACH5_DLEN_8822B 0x3ffff
+#define BIT_DDMACH5_DLEN_8822B(x)                                              \
+	(((x) & BIT_MASK_DDMACH5_DLEN_8822B) << BIT_SHIFT_DDMACH5_DLEN_8822B)
+#define BITS_DDMACH5_DLEN_8822B                                                \
+	(BIT_MASK_DDMACH5_DLEN_8822B << BIT_SHIFT_DDMACH5_DLEN_8822B)
+#define BIT_CLEAR_DDMACH5_DLEN_8822B(x) ((x) & (~BITS_DDMACH5_DLEN_8822B))
+#define BIT_GET_DDMACH5_DLEN_8822B(x)                                          \
+	(((x) >> BIT_SHIFT_DDMACH5_DLEN_8822B) & BIT_MASK_DDMACH5_DLEN_8822B)
+#define BIT_SET_DDMACH5_DLEN_8822B(x, v)                                       \
+	(BIT_CLEAR_DDMACH5_DLEN_8822B(x) | BIT_DDMACH5_DLEN_8822B(v))
+
+/* 2 REG_DDMA_INT_MSK_8822B */
+#define BIT_DDMACH5_MSK_8822B BIT(5)
+#define BIT_DDMACH4_MSK_8822B BIT(4)
+#define BIT_DDMACH3_MSK_8822B BIT(3)
+#define BIT_DDMACH2_MSK_8822B BIT(2)
+#define BIT_DDMACH1_MSK_8822B BIT(1)
+#define BIT_DDMACH0_MSK_8822B BIT(0)
+
+/* 2 REG_DDMA_CHSTATUS_8822B */
+#define BIT_DDMACH5_BUSY_8822B BIT(5)
+#define BIT_DDMACH4_BUSY_8822B BIT(4)
+#define BIT_DDMACH3_BUSY_8822B BIT(3)
+#define BIT_DDMACH2_BUSY_8822B BIT(2)
+#define BIT_DDMACH1_BUSY_8822B BIT(1)
+#define BIT_DDMACH0_BUSY_8822B BIT(0)
+
+/* 2 REG_DDMA_CHKSUM_8822B */
+
+#define BIT_SHIFT_IDDMA0_CHKSUM_8822B 0
+#define BIT_MASK_IDDMA0_CHKSUM_8822B 0xffff
+#define BIT_IDDMA0_CHKSUM_8822B(x)                                             \
+	(((x) & BIT_MASK_IDDMA0_CHKSUM_8822B) << BIT_SHIFT_IDDMA0_CHKSUM_8822B)
+#define BITS_IDDMA0_CHKSUM_8822B                                               \
+	(BIT_MASK_IDDMA0_CHKSUM_8822B << BIT_SHIFT_IDDMA0_CHKSUM_8822B)
+#define BIT_CLEAR_IDDMA0_CHKSUM_8822B(x) ((x) & (~BITS_IDDMA0_CHKSUM_8822B))
+#define BIT_GET_IDDMA0_CHKSUM_8822B(x)                                         \
+	(((x) >> BIT_SHIFT_IDDMA0_CHKSUM_8822B) & BIT_MASK_IDDMA0_CHKSUM_8822B)
+#define BIT_SET_IDDMA0_CHKSUM_8822B(x, v)                                      \
+	(BIT_CLEAR_IDDMA0_CHKSUM_8822B(x) | BIT_IDDMA0_CHKSUM_8822B(v))
+
+/* 2 REG_DDMA_MONITOR_8822B */
+#define BIT_IDDMA0_PERMU_UNDERFLOW_8822B BIT(14)
+#define BIT_IDDMA0_FIFO_UNDERFLOW_8822B BIT(13)
+#define BIT_IDDMA0_FIFO_OVERFLOW_8822B BIT(12)
+#define BIT_CH5_ERR_8822B BIT(5)
+#define BIT_CH4_ERR_8822B BIT(4)
+#define BIT_CH3_ERR_8822B BIT(3)
+#define BIT_CH2_ERR_8822B BIT(2)
+#define BIT_CH1_ERR_8822B BIT(1)
+#define BIT_CH0_ERR_8822B BIT(0)
+
+/* 2 REG_NOT_VALID_8822B */
+
+/* 2 REG_PCIE_CTRL_8822B */
+#define BIT_PCIEIO_PERSTB_SEL_8822B BIT(31)
+
+#define BIT_SHIFT_PCIE_MAX_RXDMA_8822B 28
+#define BIT_MASK_PCIE_MAX_RXDMA_8822B 0x7
+#define BIT_PCIE_MAX_RXDMA_8822B(x)                                            \
+	(((x) & BIT_MASK_PCIE_MAX_RXDMA_8822B)                                 \
+	 << BIT_SHIFT_PCIE_MAX_RXDMA_8822B)
+#define BITS_PCIE_MAX_RXDMA_8822B                                              \
+	(BIT_MASK_PCIE_MAX_RXDMA_8822B << BIT_SHIFT_PCIE_MAX_RXDMA_8822B)
+#define BIT_CLEAR_PCIE_MAX_RXDMA_8822B(x) ((x) & (~BITS_PCIE_MAX_RXDMA_8822B))
+#define BIT_GET_PCIE_MAX_RXDMA_8822B(x)                                        \
+	(((x) >> BIT_SHIFT_PCIE_MAX_RXDMA_8822B) &                             \
+	 BIT_MASK_PCIE_MAX_RXDMA_8822B)
+#define BIT_SET_PCIE_MAX_RXDMA_8822B(x, v)                                     \
+	(BIT_CLEAR_PCIE_MAX_RXDMA_8822B(x) | BIT_PCIE_MAX_RXDMA_8822B(v))
+
+#define BIT_MULRW_8822B BIT(27)
+
+#define BIT_SHIFT_PCIE_MAX_TXDMA_8822B 24
+#define BIT_MASK_PCIE_MAX_TXDMA_8822B 0x7
+#define BIT_PCIE_MAX_TXDMA_8822B(x)                                            \
+	(((x) & BIT_MASK_PCIE_MAX_TXDMA_8822B)                                 \
+	 << BIT_SHIFT_PCIE_MAX_TXDMA_8822B)
+#define BITS_PCIE_MAX_TXDMA_8822B                                              \
+	(BIT_MASK_PCIE_MAX_TXDMA_8822B << BIT_SHIFT_PCIE_MAX_TXDMA_8822B)
+#define BIT_CLEAR_PCIE_MAX_TXDMA_8822B(x) ((x) & (~BITS_PCIE_MAX_TXDMA_8822B))
+#define BIT_GET_PCIE_MAX_TXDMA_8822B(x)                                        \
+	(((x) >> BIT_SHIFT_PCIE_MAX_TXDMA_8822B) &                             \
+	 BIT_MASK_PCIE_MAX_TXDMA_8822B)
+#define BIT_SET_PCIE_MAX_TXDMA_8822B(x, v)                                     \
+	(BIT_CLEAR_PCIE_MAX_TXDMA_8822B(x) | BIT_PCIE_MAX_TXDMA_8822B(v))
+
+#define BIT_EN_CPL_TIMEOUT_PS_8822B BIT(22)
+#define BIT_REG_TXDMA_FAIL_PS_8822B BIT(21)
+#define BIT_PCIE_RST_TRXDMA_INTF_8822B BIT(20)
+#define BIT_EN_HWENTR_L1_8822B BIT(19)
+#define BIT_EN_ADV_CLKGATE_8822B BIT(18)
+#define BIT_PCIE_EN_SWENT_L23_8822B BIT(17)
+#define BIT_PCIE_EN_HWEXT_L1_8822B BIT(16)
+#define BIT_RX_CLOSE_EN_8822B BIT(15)
+#define BIT_STOP_BCNQ_8822B BIT(14)
+#define BIT_STOP_MGQ_8822B BIT(13)
+#define BIT_STOP_VOQ_8822B BIT(12)
+#define BIT_STOP_VIQ_8822B BIT(11)
+#define BIT_STOP_BEQ_8822B BIT(10)
+#define BIT_STOP_BKQ_8822B BIT(9)
+#define BIT_STOP_RXQ_8822B BIT(8)
+#define BIT_STOP_HI7Q_8822B BIT(7)
+#define BIT_STOP_HI6Q_8822B BIT(6)
+#define BIT_STOP_HI5Q_8822B BIT(5)
+#define BIT_STOP_HI4Q_8822B BIT(4)
+#define BIT_STOP_HI3Q_8822B BIT(3)
+#define BIT_STOP_HI2Q_8822B BIT(2)
+#define BIT_STOP_HI1Q_8822B BIT(1)
+#define BIT_STOP_HI0Q_8822B BIT(0)
+
+/* 2 REG_INT_MIG_8822B */
+
+#define BIT_SHIFT_TXTTIMER_MATCH_NUM_8822B 28
+#define BIT_MASK_TXTTIMER_MATCH_NUM_8822B 0xf
+#define BIT_TXTTIMER_MATCH_NUM_8822B(x)                                        \
+	(((x) & BIT_MASK_TXTTIMER_MATCH_NUM_8822B)                             \
+	 << BIT_SHIFT_TXTTIMER_MATCH_NUM_8822B)
+#define BITS_TXTTIMER_MATCH_NUM_8822B                                          \
+	(BIT_MASK_TXTTIMER_MATCH_NUM_8822B                                     \
+	 << BIT_SHIFT_TXTTIMER_MATCH_NUM_8822B)
+#define BIT_CLEAR_TXTTIMER_MATCH_NUM_8822B(x)                                  \
+	((x) & (~BITS_TXTTIMER_MATCH_NUM_8822B))
+#define BIT_GET_TXTTIMER_MATCH_NUM_8822B(x)                                    \
+	(((x) >> BIT_SHIFT_TXTTIMER_MATCH_NUM_8822B) &                         \
+	 BIT_MASK_TXTTIMER_MATCH_NUM_8822B)
+#define BIT_SET_TXTTIMER_MATCH_NUM_8822B(x, v)                                 \
+	(BIT_CLEAR_TXTTIMER_MATCH_NUM_8822B(x) |                               \
+	 BIT_TXTTIMER_MATCH_NUM_8822B(v))
+
+#define BIT_SHIFT_TXPKT_NUM_MATCH_8822B 24
+#define BIT_MASK_TXPKT_NUM_MATCH_8822B 0xf
+#define BIT_TXPKT_NUM_MATCH_8822B(x)                                           \
+	(((x) & BIT_MASK_TXPKT_NUM_MATCH_8822B)                                \
+	 << BIT_SHIFT_TXPKT_NUM_MATCH_8822B)
+#define BITS_TXPKT_NUM_MATCH_8822B                                             \
+	(BIT_MASK_TXPKT_NUM_MATCH_8822B << BIT_SHIFT_TXPKT_NUM_MATCH_8822B)
+#define BIT_CLEAR_TXPKT_NUM_MATCH_8822B(x) ((x) & (~BITS_TXPKT_NUM_MATCH_8822B))
+#define BIT_GET_TXPKT_NUM_MATCH_8822B(x)                                       \
+	(((x) >> BIT_SHIFT_TXPKT_NUM_MATCH_8822B) &                            \
+	 BIT_MASK_TXPKT_NUM_MATCH_8822B)
+#define BIT_SET_TXPKT_NUM_MATCH_8822B(x, v)                                    \
+	(BIT_CLEAR_TXPKT_NUM_MATCH_8822B(x) | BIT_TXPKT_NUM_MATCH_8822B(v))
+
+#define BIT_SHIFT_RXTTIMER_MATCH_NUM_8822B 20
+#define BIT_MASK_RXTTIMER_MATCH_NUM_8822B 0xf
+#define BIT_RXTTIMER_MATCH_NUM_8822B(x)                                        \
+	(((x) & BIT_MASK_RXTTIMER_MATCH_NUM_8822B)                             \
+	 << BIT_SHIFT_RXTTIMER_MATCH_NUM_8822B)
+#define BITS_RXTTIMER_MATCH_NUM_8822B                                          \
+	(BIT_MASK_RXTTIMER_MATCH_NUM_8822B                                     \
+	 << BIT_SHIFT_RXTTIMER_MATCH_NUM_8822B)
+#define BIT_CLEAR_RXTTIMER_MATCH_NUM_8822B(x)                                  \
+	((x) & (~BITS_RXTTIMER_MATCH_NUM_8822B))
+#define BIT_GET_RXTTIMER_MATCH_NUM_8822B(x)                                    \
+	(((x) >> BIT_SHIFT_RXTTIMER_MATCH_NUM_8822B) &                         \
+	 BIT_MASK_RXTTIMER_MATCH_NUM_8822B)
+#define BIT_SET_RXTTIMER_MATCH_NUM_8822B(x, v)                                 \
+	(BIT_CLEAR_RXTTIMER_MATCH_NUM_8822B(x) |                               \
+	 BIT_RXTTIMER_MATCH_NUM_8822B(v))
+
+#define BIT_SHIFT_RXPKT_NUM_MATCH_8822B 16
+#define BIT_MASK_RXPKT_NUM_MATCH_8822B 0xf
+#define BIT_RXPKT_NUM_MATCH_8822B(x)                                           \
+	(((x) & BIT_MASK_RXPKT_NUM_MATCH_8822B)                                \
+	 << BIT_SHIFT_RXPKT_NUM_MATCH_8822B)
+#define BITS_RXPKT_NUM_MATCH_8822B                                             \
+	(BIT_MASK_RXPKT_NUM_MATCH_8822B << BIT_SHIFT_RXPKT_NUM_MATCH_8822B)
+#define BIT_CLEAR_RXPKT_NUM_MATCH_8822B(x) ((x) & (~BITS_RXPKT_NUM_MATCH_8822B))
+#define BIT_GET_RXPKT_NUM_MATCH_8822B(x)                                       \
+	(((x) >> BIT_SHIFT_RXPKT_NUM_MATCH_8822B) &                            \
+	 BIT_MASK_RXPKT_NUM_MATCH_8822B)
+#define BIT_SET_RXPKT_NUM_MATCH_8822B(x, v)                                    \
+	(BIT_CLEAR_RXPKT_NUM_MATCH_8822B(x) | BIT_RXPKT_NUM_MATCH_8822B(v))
+
+#define BIT_SHIFT_MIGRATE_TIMER_8822B 0
+#define BIT_MASK_MIGRATE_TIMER_8822B 0xffff
+#define BIT_MIGRATE_TIMER_8822B(x)                                             \
+	(((x) & BIT_MASK_MIGRATE_TIMER_8822B) << BIT_SHIFT_MIGRATE_TIMER_8822B)
+#define BITS_MIGRATE_TIMER_8822B                                               \
+	(BIT_MASK_MIGRATE_TIMER_8822B << BIT_SHIFT_MIGRATE_TIMER_8822B)
+#define BIT_CLEAR_MIGRATE_TIMER_8822B(x) ((x) & (~BITS_MIGRATE_TIMER_8822B))
+#define BIT_GET_MIGRATE_TIMER_8822B(x)                                         \
+	(((x) >> BIT_SHIFT_MIGRATE_TIMER_8822B) & BIT_MASK_MIGRATE_TIMER_8822B)
+#define BIT_SET_MIGRATE_TIMER_8822B(x, v)                                      \
+	(BIT_CLEAR_MIGRATE_TIMER_8822B(x) | BIT_MIGRATE_TIMER_8822B(v))
+
+/* 2 REG_BCNQ_TXBD_DESA_8822B */
+
+#define BIT_SHIFT_BCNQ_TXBD_DESA_8822B 0
+#define BIT_MASK_BCNQ_TXBD_DESA_8822B 0xffffffffffffffffL
+#define BIT_BCNQ_TXBD_DESA_8822B(x)                                            \
+	(((x) & BIT_MASK_BCNQ_TXBD_DESA_8822B)                                 \
+	 << BIT_SHIFT_BCNQ_TXBD_DESA_8822B)
+#define BITS_BCNQ_TXBD_DESA_8822B                                              \
+	(BIT_MASK_BCNQ_TXBD_DESA_8822B << BIT_SHIFT_BCNQ_TXBD_DESA_8822B)
+#define BIT_CLEAR_BCNQ_TXBD_DESA_8822B(x) ((x) & (~BITS_BCNQ_TXBD_DESA_8822B))
+#define BIT_GET_BCNQ_TXBD_DESA_8822B(x)                                        \
+	(((x) >> BIT_SHIFT_BCNQ_TXBD_DESA_8822B) &                             \
+	 BIT_MASK_BCNQ_TXBD_DESA_8822B)
+#define BIT_SET_BCNQ_TXBD_DESA_8822B(x, v)                                     \
+	(BIT_CLEAR_BCNQ_TXBD_DESA_8822B(x) | BIT_BCNQ_TXBD_DESA_8822B(v))
+
+/* 2 REG_MGQ_TXBD_DESA_8822B */
+
+#define BIT_SHIFT_MGQ_TXBD_DESA_8822B 0
+#define BIT_MASK_MGQ_TXBD_DESA_8822B 0xffffffffffffffffL
+#define BIT_MGQ_TXBD_DESA_8822B(x)                                             \
+	(((x) & BIT_MASK_MGQ_TXBD_DESA_8822B) << BIT_SHIFT_MGQ_TXBD_DESA_8822B)
+#define BITS_MGQ_TXBD_DESA_8822B                                               \
+	(BIT_MASK_MGQ_TXBD_DESA_8822B << BIT_SHIFT_MGQ_TXBD_DESA_8822B)
+#define BIT_CLEAR_MGQ_TXBD_DESA_8822B(x) ((x) & (~BITS_MGQ_TXBD_DESA_8822B))
+#define BIT_GET_MGQ_TXBD_DESA_8822B(x)                                         \
+	(((x) >> BIT_SHIFT_MGQ_TXBD_DESA_8822B) & BIT_MASK_MGQ_TXBD_DESA_8822B)
+#define BIT_SET_MGQ_TXBD_DESA_8822B(x, v)                                      \
+	(BIT_CLEAR_MGQ_TXBD_DESA_8822B(x) | BIT_MGQ_TXBD_DESA_8822B(v))
+
+/* 2 REG_VOQ_TXBD_DESA_8822B */
+
+#define BIT_SHIFT_VOQ_TXBD_DESA_8822B 0
+#define BIT_MASK_VOQ_TXBD_DESA_8822B 0xffffffffffffffffL
+#define BIT_VOQ_TXBD_DESA_8822B(x)                                             \
+	(((x) & BIT_MASK_VOQ_TXBD_DESA_8822B) << BIT_SHIFT_VOQ_TXBD_DESA_8822B)
+#define BITS_VOQ_TXBD_DESA_8822B                                               \
+	(BIT_MASK_VOQ_TXBD_DESA_8822B << BIT_SHIFT_VOQ_TXBD_DESA_8822B)
+#define BIT_CLEAR_VOQ_TXBD_DESA_8822B(x) ((x) & (~BITS_VOQ_TXBD_DESA_8822B))
+#define BIT_GET_VOQ_TXBD_DESA_8822B(x)                                         \
+	(((x) >> BIT_SHIFT_VOQ_TXBD_DESA_8822B) & BIT_MASK_VOQ_TXBD_DESA_8822B)
+#define BIT_SET_VOQ_TXBD_DESA_8822B(x, v)                                      \
+	(BIT_CLEAR_VOQ_TXBD_DESA_8822B(x) | BIT_VOQ_TXBD_DESA_8822B(v))
+
+/* 2 REG_VIQ_TXBD_DESA_8822B */
+
+#define BIT_SHIFT_VIQ_TXBD_DESA_8822B 0
+#define BIT_MASK_VIQ_TXBD_DESA_8822B 0xffffffffffffffffL
+#define BIT_VIQ_TXBD_DESA_8822B(x)                                             \
+	(((x) & BIT_MASK_VIQ_TXBD_DESA_8822B) << BIT_SHIFT_VIQ_TXBD_DESA_8822B)
+#define BITS_VIQ_TXBD_DESA_8822B                                               \
+	(BIT_MASK_VIQ_TXBD_DESA_8822B << BIT_SHIFT_VIQ_TXBD_DESA_8822B)
+#define BIT_CLEAR_VIQ_TXBD_DESA_8822B(x) ((x) & (~BITS_VIQ_TXBD_DESA_8822B))
+#define BIT_GET_VIQ_TXBD_DESA_8822B(x)                                         \
+	(((x) >> BIT_SHIFT_VIQ_TXBD_DESA_8822B) & BIT_MASK_VIQ_TXBD_DESA_8822B)
+#define BIT_SET_VIQ_TXBD_DESA_8822B(x, v)                                      \
+	(BIT_CLEAR_VIQ_TXBD_DESA_8822B(x) | BIT_VIQ_TXBD_DESA_8822B(v))
+
+/* 2 REG_BEQ_TXBD_DESA_8822B */
+
+#define BIT_SHIFT_BEQ_TXBD_DESA_8822B 0
+#define BIT_MASK_BEQ_TXBD_DESA_8822B 0xffffffffffffffffL
+#define BIT_BEQ_TXBD_DESA_8822B(x)                                             \
+	(((x) & BIT_MASK_BEQ_TXBD_DESA_8822B) << BIT_SHIFT_BEQ_TXBD_DESA_8822B)
+#define BITS_BEQ_TXBD_DESA_8822B                                               \
+	(BIT_MASK_BEQ_TXBD_DESA_8822B << BIT_SHIFT_BEQ_TXBD_DESA_8822B)
+#define BIT_CLEAR_BEQ_TXBD_DESA_8822B(x) ((x) & (~BITS_BEQ_TXBD_DESA_8822B))
+#define BIT_GET_BEQ_TXBD_DESA_8822B(x)                                         \
+	(((x) >> BIT_SHIFT_BEQ_TXBD_DESA_8822B) & BIT_MASK_BEQ_TXBD_DESA_8822B)
+#define BIT_SET_BEQ_TXBD_DESA_8822B(x, v)                                      \
+	(BIT_CLEAR_BEQ_TXBD_DESA_8822B(x) | BIT_BEQ_TXBD_DESA_8822B(v))
+
+/* 2 REG_BKQ_TXBD_DESA_8822B */
+
+#define BIT_SHIFT_BKQ_TXBD_DESA_8822B 0
+#define BIT_MASK_BKQ_TXBD_DESA_8822B 0xffffffffffffffffL
+#define BIT_BKQ_TXBD_DESA_8822B(x)                                             \
+	(((x) & BIT_MASK_BKQ_TXBD_DESA_8822B) << BIT_SHIFT_BKQ_TXBD_DESA_8822B)
+#define BITS_BKQ_TXBD_DESA_8822B                                               \
+	(BIT_MASK_BKQ_TXBD_DESA_8822B << BIT_SHIFT_BKQ_TXBD_DESA_8822B)
+#define BIT_CLEAR_BKQ_TXBD_DESA_8822B(x) ((x) & (~BITS_BKQ_TXBD_DESA_8822B))
+#define BIT_GET_BKQ_TXBD_DESA_8822B(x)                                         \
+	(((x) >> BIT_SHIFT_BKQ_TXBD_DESA_8822B) & BIT_MASK_BKQ_TXBD_DESA_8822B)
+#define BIT_SET_BKQ_TXBD_DESA_8822B(x, v)                                      \
+	(BIT_CLEAR_BKQ_TXBD_DESA_8822B(x) | BIT_BKQ_TXBD_DESA_8822B(v))
+
+/* 2 REG_RXQ_RXBD_DESA_8822B */
+
+#define BIT_SHIFT_RXQ_RXBD_DESA_8822B 0
+#define BIT_MASK_RXQ_RXBD_DESA_8822B 0xffffffffffffffffL
+#define BIT_RXQ_RXBD_DESA_8822B(x)                                             \
+	(((x) & BIT_MASK_RXQ_RXBD_DESA_8822B) << BIT_SHIFT_RXQ_RXBD_DESA_8822B)
+#define BITS_RXQ_RXBD_DESA_8822B                                               \
+	(BIT_MASK_RXQ_RXBD_DESA_8822B << BIT_SHIFT_RXQ_RXBD_DESA_8822B)
+#define BIT_CLEAR_RXQ_RXBD_DESA_8822B(x) ((x) & (~BITS_RXQ_RXBD_DESA_8822B))
+#define BIT_GET_RXQ_RXBD_DESA_8822B(x)                                         \
+	(((x) >> BIT_SHIFT_RXQ_RXBD_DESA_8822B) & BIT_MASK_RXQ_RXBD_DESA_8822B)
+#define BIT_SET_RXQ_RXBD_DESA_8822B(x, v)                                      \
+	(BIT_CLEAR_RXQ_RXBD_DESA_8822B(x) | BIT_RXQ_RXBD_DESA_8822B(v))
+
+/* 2 REG_HI0Q_TXBD_DESA_8822B */
+
+#define BIT_SHIFT_HI0Q_TXBD_DESA_8822B 0
+#define BIT_MASK_HI0Q_TXBD_DESA_8822B 0xffffffffffffffffL
+#define BIT_HI0Q_TXBD_DESA_8822B(x)                                            \
+	(((x) & BIT_MASK_HI0Q_TXBD_DESA_8822B)                                 \
+	 << BIT_SHIFT_HI0Q_TXBD_DESA_8822B)
+#define BITS_HI0Q_TXBD_DESA_8822B                                              \
+	(BIT_MASK_HI0Q_TXBD_DESA_8822B << BIT_SHIFT_HI0Q_TXBD_DESA_8822B)
+#define BIT_CLEAR_HI0Q_TXBD_DESA_8822B(x) ((x) & (~BITS_HI0Q_TXBD_DESA_8822B))
+#define BIT_GET_HI0Q_TXBD_DESA_8822B(x)                                        \
+	(((x) >> BIT_SHIFT_HI0Q_TXBD_DESA_8822B) &                             \
+	 BIT_MASK_HI0Q_TXBD_DESA_8822B)
+#define BIT_SET_HI0Q_TXBD_DESA_8822B(x, v)                                     \
+	(BIT_CLEAR_HI0Q_TXBD_DESA_8822B(x) | BIT_HI0Q_TXBD_DESA_8822B(v))
+
+/* 2 REG_HI1Q_TXBD_DESA_8822B */
+
+#define BIT_SHIFT_HI1Q_TXBD_DESA_8822B 0
+#define BIT_MASK_HI1Q_TXBD_DESA_8822B 0xffffffffffffffffL
+#define BIT_HI1Q_TXBD_DESA_8822B(x)                                            \
+	(((x) & BIT_MASK_HI1Q_TXBD_DESA_8822B)                                 \
+	 << BIT_SHIFT_HI1Q_TXBD_DESA_8822B)
+#define BITS_HI1Q_TXBD_DESA_8822B                                              \
+	(BIT_MASK_HI1Q_TXBD_DESA_8822B << BIT_SHIFT_HI1Q_TXBD_DESA_8822B)
+#define BIT_CLEAR_HI1Q_TXBD_DESA_8822B(x) ((x) & (~BITS_HI1Q_TXBD_DESA_8822B))
+#define BIT_GET_HI1Q_TXBD_DESA_8822B(x)                                        \
+	(((x) >> BIT_SHIFT_HI1Q_TXBD_DESA_8822B) &                             \
+	 BIT_MASK_HI1Q_TXBD_DESA_8822B)
+#define BIT_SET_HI1Q_TXBD_DESA_8822B(x, v)                                     \
+	(BIT_CLEAR_HI1Q_TXBD_DESA_8822B(x) | BIT_HI1Q_TXBD_DESA_8822B(v))
+
+/* 2 REG_HI2Q_TXBD_DESA_8822B */
+
+#define BIT_SHIFT_HI2Q_TXBD_DESA_8822B 0
+#define BIT_MASK_HI2Q_TXBD_DESA_8822B 0xffffffffffffffffL
+#define BIT_HI2Q_TXBD_DESA_8822B(x)                                            \
+	(((x) & BIT_MASK_HI2Q_TXBD_DESA_8822B)                                 \
+	 << BIT_SHIFT_HI2Q_TXBD_DESA_8822B)
+#define BITS_HI2Q_TXBD_DESA_8822B                                              \
+	(BIT_MASK_HI2Q_TXBD_DESA_8822B << BIT_SHIFT_HI2Q_TXBD_DESA_8822B)
+#define BIT_CLEAR_HI2Q_TXBD_DESA_8822B(x) ((x) & (~BITS_HI2Q_TXBD_DESA_8822B))
+#define BIT_GET_HI2Q_TXBD_DESA_8822B(x)                                        \
+	(((x) >> BIT_SHIFT_HI2Q_TXBD_DESA_8822B) &                             \
+	 BIT_MASK_HI2Q_TXBD_DESA_8822B)
+#define BIT_SET_HI2Q_TXBD_DESA_8822B(x, v)                                     \
+	(BIT_CLEAR_HI2Q_TXBD_DESA_8822B(x) | BIT_HI2Q_TXBD_DESA_8822B(v))
+
+/* 2 REG_HI3Q_TXBD_DESA_8822B */
+
+#define BIT_SHIFT_HI3Q_TXBD_DESA_8822B 0
+#define BIT_MASK_HI3Q_TXBD_DESA_8822B 0xffffffffffffffffL
+#define BIT_HI3Q_TXBD_DESA_8822B(x)                                            \
+	(((x) & BIT_MASK_HI3Q_TXBD_DESA_8822B)                                 \
+	 << BIT_SHIFT_HI3Q_TXBD_DESA_8822B)
+#define BITS_HI3Q_TXBD_DESA_8822B                                              \
+	(BIT_MASK_HI3Q_TXBD_DESA_8822B << BIT_SHIFT_HI3Q_TXBD_DESA_8822B)
+#define BIT_CLEAR_HI3Q_TXBD_DESA_8822B(x) ((x) & (~BITS_HI3Q_TXBD_DESA_8822B))
+#define BIT_GET_HI3Q_TXBD_DESA_8822B(x)                                        \
+	(((x) >> BIT_SHIFT_HI3Q_TXBD_DESA_8822B) &                             \
+	 BIT_MASK_HI3Q_TXBD_DESA_8822B)
+#define BIT_SET_HI3Q_TXBD_DESA_8822B(x, v)                                     \
+	(BIT_CLEAR_HI3Q_TXBD_DESA_8822B(x) | BIT_HI3Q_TXBD_DESA_8822B(v))
+
+/* 2 REG_HI4Q_TXBD_DESA_8822B */
+
+#define BIT_SHIFT_HI4Q_TXBD_DESA_8822B 0
+#define BIT_MASK_HI4Q_TXBD_DESA_8822B 0xffffffffffffffffL
+#define BIT_HI4Q_TXBD_DESA_8822B(x)                                            \
+	(((x) & BIT_MASK_HI4Q_TXBD_DESA_8822B)                                 \
+	 << BIT_SHIFT_HI4Q_TXBD_DESA_8822B)
+#define BITS_HI4Q_TXBD_DESA_8822B                                              \
+	(BIT_MASK_HI4Q_TXBD_DESA_8822B << BIT_SHIFT_HI4Q_TXBD_DESA_8822B)
+#define BIT_CLEAR_HI4Q_TXBD_DESA_8822B(x) ((x) & (~BITS_HI4Q_TXBD_DESA_8822B))
+#define BIT_GET_HI4Q_TXBD_DESA_8822B(x)                                        \
+	(((x) >> BIT_SHIFT_HI4Q_TXBD_DESA_8822B) &                             \
+	 BIT_MASK_HI4Q_TXBD_DESA_8822B)
+#define BIT_SET_HI4Q_TXBD_DESA_8822B(x, v)                                     \
+	(BIT_CLEAR_HI4Q_TXBD_DESA_8822B(x) | BIT_HI4Q_TXBD_DESA_8822B(v))
+
+/* 2 REG_HI5Q_TXBD_DESA_8822B */
+
+#define BIT_SHIFT_HI5Q_TXBD_DESA_8822B 0
+#define BIT_MASK_HI5Q_TXBD_DESA_8822B 0xffffffffffffffffL
+#define BIT_HI5Q_TXBD_DESA_8822B(x)                                            \
+	(((x) & BIT_MASK_HI5Q_TXBD_DESA_8822B)                                 \
+	 << BIT_SHIFT_HI5Q_TXBD_DESA_8822B)
+#define BITS_HI5Q_TXBD_DESA_8822B                                              \
+	(BIT_MASK_HI5Q_TXBD_DESA_8822B << BIT_SHIFT_HI5Q_TXBD_DESA_8822B)
+#define BIT_CLEAR_HI5Q_TXBD_DESA_8822B(x) ((x) & (~BITS_HI5Q_TXBD_DESA_8822B))
+#define BIT_GET_HI5Q_TXBD_DESA_8822B(x)                                        \
+	(((x) >> BIT_SHIFT_HI5Q_TXBD_DESA_8822B) &                             \
+	 BIT_MASK_HI5Q_TXBD_DESA_8822B)
+#define BIT_SET_HI5Q_TXBD_DESA_8822B(x, v)                                     \
+	(BIT_CLEAR_HI5Q_TXBD_DESA_8822B(x) | BIT_HI5Q_TXBD_DESA_8822B(v))
+
+/* 2 REG_HI6Q_TXBD_DESA_8822B */
+
+#define BIT_SHIFT_HI6Q_TXBD_DESA_8822B 0
+#define BIT_MASK_HI6Q_TXBD_DESA_8822B 0xffffffffffffffffL
+#define BIT_HI6Q_TXBD_DESA_8822B(x)                                            \
+	(((x) & BIT_MASK_HI6Q_TXBD_DESA_8822B)                                 \
+	 << BIT_SHIFT_HI6Q_TXBD_DESA_8822B)
+#define BITS_HI6Q_TXBD_DESA_8822B                                              \
+	(BIT_MASK_HI6Q_TXBD_DESA_8822B << BIT_SHIFT_HI6Q_TXBD_DESA_8822B)
+#define BIT_CLEAR_HI6Q_TXBD_DESA_8822B(x) ((x) & (~BITS_HI6Q_TXBD_DESA_8822B))
+#define BIT_GET_HI6Q_TXBD_DESA_8822B(x)                                        \
+	(((x) >> BIT_SHIFT_HI6Q_TXBD_DESA_8822B) &                             \
+	 BIT_MASK_HI6Q_TXBD_DESA_8822B)
+#define BIT_SET_HI6Q_TXBD_DESA_8822B(x, v)                                     \
+	(BIT_CLEAR_HI6Q_TXBD_DESA_8822B(x) | BIT_HI6Q_TXBD_DESA_8822B(v))
+
+/* 2 REG_HI7Q_TXBD_DESA_8822B */
+
+#define BIT_SHIFT_HI7Q_TXBD_DESA_8822B 0
+#define BIT_MASK_HI7Q_TXBD_DESA_8822B 0xffffffffffffffffL
+#define BIT_HI7Q_TXBD_DESA_8822B(x)                                            \
+	(((x) & BIT_MASK_HI7Q_TXBD_DESA_8822B)                                 \
+	 << BIT_SHIFT_HI7Q_TXBD_DESA_8822B)
+#define BITS_HI7Q_TXBD_DESA_8822B                                              \
+	(BIT_MASK_HI7Q_TXBD_DESA_8822B << BIT_SHIFT_HI7Q_TXBD_DESA_8822B)
+#define BIT_CLEAR_HI7Q_TXBD_DESA_8822B(x) ((x) & (~BITS_HI7Q_TXBD_DESA_8822B))
+#define BIT_GET_HI7Q_TXBD_DESA_8822B(x)                                        \
+	(((x) >> BIT_SHIFT_HI7Q_TXBD_DESA_8822B) &                             \
+	 BIT_MASK_HI7Q_TXBD_DESA_8822B)
+#define BIT_SET_HI7Q_TXBD_DESA_8822B(x, v)                                     \
+	(BIT_CLEAR_HI7Q_TXBD_DESA_8822B(x) | BIT_HI7Q_TXBD_DESA_8822B(v))
+
+/* 2 REG_MGQ_TXBD_NUM_8822B */
+#define BIT_PCIE_MGQ_FLAG_8822B BIT(14)
+
+#define BIT_SHIFT_MGQ_DESC_MODE_8822B 12
+#define BIT_MASK_MGQ_DESC_MODE_8822B 0x3
+#define BIT_MGQ_DESC_MODE_8822B(x)                                             \
+	(((x) & BIT_MASK_MGQ_DESC_MODE_8822B) << BIT_SHIFT_MGQ_DESC_MODE_8822B)
+#define BITS_MGQ_DESC_MODE_8822B                                               \
+	(BIT_MASK_MGQ_DESC_MODE_8822B << BIT_SHIFT_MGQ_DESC_MODE_8822B)
+#define BIT_CLEAR_MGQ_DESC_MODE_8822B(x) ((x) & (~BITS_MGQ_DESC_MODE_8822B))
+#define BIT_GET_MGQ_DESC_MODE_8822B(x)                                         \
+	(((x) >> BIT_SHIFT_MGQ_DESC_MODE_8822B) & BIT_MASK_MGQ_DESC_MODE_8822B)
+#define BIT_SET_MGQ_DESC_MODE_8822B(x, v)                                      \
+	(BIT_CLEAR_MGQ_DESC_MODE_8822B(x) | BIT_MGQ_DESC_MODE_8822B(v))
+
+#define BIT_SHIFT_MGQ_DESC_NUM_8822B 0
+#define BIT_MASK_MGQ_DESC_NUM_8822B 0xfff
+#define BIT_MGQ_DESC_NUM_8822B(x)                                              \
+	(((x) & BIT_MASK_MGQ_DESC_NUM_8822B) << BIT_SHIFT_MGQ_DESC_NUM_8822B)
+#define BITS_MGQ_DESC_NUM_8822B                                                \
+	(BIT_MASK_MGQ_DESC_NUM_8822B << BIT_SHIFT_MGQ_DESC_NUM_8822B)
+#define BIT_CLEAR_MGQ_DESC_NUM_8822B(x) ((x) & (~BITS_MGQ_DESC_NUM_8822B))
+#define BIT_GET_MGQ_DESC_NUM_8822B(x)                                          \
+	(((x) >> BIT_SHIFT_MGQ_DESC_NUM_8822B) & BIT_MASK_MGQ_DESC_NUM_8822B)
+#define BIT_SET_MGQ_DESC_NUM_8822B(x, v)                                       \
+	(BIT_CLEAR_MGQ_DESC_NUM_8822B(x) | BIT_MGQ_DESC_NUM_8822B(v))
+
+/* 2 REG_RX_RXBD_NUM_8822B */
+#define BIT_SYS_32_64_8822B BIT(15)
+
+#define BIT_SHIFT_BCNQ_DESC_MODE_8822B 13
+#define BIT_MASK_BCNQ_DESC_MODE_8822B 0x3
+#define BIT_BCNQ_DESC_MODE_8822B(x)                                            \
+	(((x) & BIT_MASK_BCNQ_DESC_MODE_8822B)                                 \
+	 << BIT_SHIFT_BCNQ_DESC_MODE_8822B)
+#define BITS_BCNQ_DESC_MODE_8822B                                              \
+	(BIT_MASK_BCNQ_DESC_MODE_8822B << BIT_SHIFT_BCNQ_DESC_MODE_8822B)
+#define BIT_CLEAR_BCNQ_DESC_MODE_8822B(x) ((x) & (~BITS_BCNQ_DESC_MODE_8822B))
+#define BIT_GET_BCNQ_DESC_MODE_8822B(x)                                        \
+	(((x) >> BIT_SHIFT_BCNQ_DESC_MODE_8822B) &                             \
+	 BIT_MASK_BCNQ_DESC_MODE_8822B)
+#define BIT_SET_BCNQ_DESC_MODE_8822B(x, v)                                     \
+	(BIT_CLEAR_BCNQ_DESC_MODE_8822B(x) | BIT_BCNQ_DESC_MODE_8822B(v))
+
+#define BIT_PCIE_BCNQ_FLAG_8822B BIT(12)
+
+#define BIT_SHIFT_RXQ_DESC_NUM_8822B 0
+#define BIT_MASK_RXQ_DESC_NUM_8822B 0xfff
+#define BIT_RXQ_DESC_NUM_8822B(x)                                              \
+	(((x) & BIT_MASK_RXQ_DESC_NUM_8822B) << BIT_SHIFT_RXQ_DESC_NUM_8822B)
+#define BITS_RXQ_DESC_NUM_8822B                                                \
+	(BIT_MASK_RXQ_DESC_NUM_8822B << BIT_SHIFT_RXQ_DESC_NUM_8822B)
+#define BIT_CLEAR_RXQ_DESC_NUM_8822B(x) ((x) & (~BITS_RXQ_DESC_NUM_8822B))
+#define BIT_GET_RXQ_DESC_NUM_8822B(x)                                          \
+	(((x) >> BIT_SHIFT_RXQ_DESC_NUM_8822B) & BIT_MASK_RXQ_DESC_NUM_8822B)
+#define BIT_SET_RXQ_DESC_NUM_8822B(x, v)                                       \
+	(BIT_CLEAR_RXQ_DESC_NUM_8822B(x) | BIT_RXQ_DESC_NUM_8822B(v))
+
+/* 2 REG_VOQ_TXBD_NUM_8822B */
+#define BIT_PCIE_VOQ_FLAG_8822B BIT(14)
+
+#define BIT_SHIFT_VOQ_DESC_MODE_8822B 12
+#define BIT_MASK_VOQ_DESC_MODE_8822B 0x3
+#define BIT_VOQ_DESC_MODE_8822B(x)                                             \
+	(((x) & BIT_MASK_VOQ_DESC_MODE_8822B) << BIT_SHIFT_VOQ_DESC_MODE_8822B)
+#define BITS_VOQ_DESC_MODE_8822B                                               \
+	(BIT_MASK_VOQ_DESC_MODE_8822B << BIT_SHIFT_VOQ_DESC_MODE_8822B)
+#define BIT_CLEAR_VOQ_DESC_MODE_8822B(x) ((x) & (~BITS_VOQ_DESC_MODE_8822B))
+#define BIT_GET_VOQ_DESC_MODE_8822B(x)                                         \
+	(((x) >> BIT_SHIFT_VOQ_DESC_MODE_8822B) & BIT_MASK_VOQ_DESC_MODE_8822B)
+#define BIT_SET_VOQ_DESC_MODE_8822B(x, v)                                      \
+	(BIT_CLEAR_VOQ_DESC_MODE_8822B(x) | BIT_VOQ_DESC_MODE_8822B(v))
+
+#define BIT_SHIFT_VOQ_DESC_NUM_8822B 0
+#define BIT_MASK_VOQ_DESC_NUM_8822B 0xfff
+#define BIT_VOQ_DESC_NUM_8822B(x)                                              \
+	(((x) & BIT_MASK_VOQ_DESC_NUM_8822B) << BIT_SHIFT_VOQ_DESC_NUM_8822B)
+#define BITS_VOQ_DESC_NUM_8822B                                                \
+	(BIT_MASK_VOQ_DESC_NUM_8822B << BIT_SHIFT_VOQ_DESC_NUM_8822B)
+#define BIT_CLEAR_VOQ_DESC_NUM_8822B(x) ((x) & (~BITS_VOQ_DESC_NUM_8822B))
+#define BIT_GET_VOQ_DESC_NUM_8822B(x)                                          \
+	(((x) >> BIT_SHIFT_VOQ_DESC_NUM_8822B) & BIT_MASK_VOQ_DESC_NUM_8822B)
+#define BIT_SET_VOQ_DESC_NUM_8822B(x, v)                                       \
+	(BIT_CLEAR_VOQ_DESC_NUM_8822B(x) | BIT_VOQ_DESC_NUM_8822B(v))
+
+/* 2 REG_VIQ_TXBD_NUM_8822B */
+#define BIT_PCIE_VIQ_FLAG_8822B BIT(14)
+
+#define BIT_SHIFT_VIQ_DESC_MODE_8822B 12
+#define BIT_MASK_VIQ_DESC_MODE_8822B 0x3
+#define BIT_VIQ_DESC_MODE_8822B(x)                                             \
+	(((x) & BIT_MASK_VIQ_DESC_MODE_8822B) << BIT_SHIFT_VIQ_DESC_MODE_8822B)
+#define BITS_VIQ_DESC_MODE_8822B                                               \
+	(BIT_MASK_VIQ_DESC_MODE_8822B << BIT_SHIFT_VIQ_DESC_MODE_8822B)
+#define BIT_CLEAR_VIQ_DESC_MODE_8822B(x) ((x) & (~BITS_VIQ_DESC_MODE_8822B))
+#define BIT_GET_VIQ_DESC_MODE_8822B(x)                                         \
+	(((x) >> BIT_SHIFT_VIQ_DESC_MODE_8822B) & BIT_MASK_VIQ_DESC_MODE_8822B)
+#define BIT_SET_VIQ_DESC_MODE_8822B(x, v)                                      \
+	(BIT_CLEAR_VIQ_DESC_MODE_8822B(x) | BIT_VIQ_DESC_MODE_8822B(v))
+
+#define BIT_SHIFT_VIQ_DESC_NUM_8822B 0
+#define BIT_MASK_VIQ_DESC_NUM_8822B 0xfff
+#define BIT_VIQ_DESC_NUM_8822B(x)                                              \
+	(((x) & BIT_MASK_VIQ_DESC_NUM_8822B) << BIT_SHIFT_VIQ_DESC_NUM_8822B)
+#define BITS_VIQ_DESC_NUM_8822B                                                \
+	(BIT_MASK_VIQ_DESC_NUM_8822B << BIT_SHIFT_VIQ_DESC_NUM_8822B)
+#define BIT_CLEAR_VIQ_DESC_NUM_8822B(x) ((x) & (~BITS_VIQ_DESC_NUM_8822B))
+#define BIT_GET_VIQ_DESC_NUM_8822B(x)                                          \
+	(((x) >> BIT_SHIFT_VIQ_DESC_NUM_8822B) & BIT_MASK_VIQ_DESC_NUM_8822B)
+#define BIT_SET_VIQ_DESC_NUM_8822B(x, v)                                       \
+	(BIT_CLEAR_VIQ_DESC_NUM_8822B(x) | BIT_VIQ_DESC_NUM_8822B(v))
+
+/* 2 REG_BEQ_TXBD_NUM_8822B */
+#define BIT_PCIE_BEQ_FLAG_8822B BIT(14)
+
+#define BIT_SHIFT_BEQ_DESC_MODE_8822B 12
+#define BIT_MASK_BEQ_DESC_MODE_8822B 0x3
+#define BIT_BEQ_DESC_MODE_8822B(x)                                             \
+	(((x) & BIT_MASK_BEQ_DESC_MODE_8822B) << BIT_SHIFT_BEQ_DESC_MODE_8822B)
+#define BITS_BEQ_DESC_MODE_8822B                                               \
+	(BIT_MASK_BEQ_DESC_MODE_8822B << BIT_SHIFT_BEQ_DESC_MODE_8822B)
+#define BIT_CLEAR_BEQ_DESC_MODE_8822B(x) ((x) & (~BITS_BEQ_DESC_MODE_8822B))
+#define BIT_GET_BEQ_DESC_MODE_8822B(x)                                         \
+	(((x) >> BIT_SHIFT_BEQ_DESC_MODE_8822B) & BIT_MASK_BEQ_DESC_MODE_8822B)
+#define BIT_SET_BEQ_DESC_MODE_8822B(x, v)                                      \
+	(BIT_CLEAR_BEQ_DESC_MODE_8822B(x) | BIT_BEQ_DESC_MODE_8822B(v))
+
+#define BIT_SHIFT_BEQ_DESC_NUM_8822B 0
+#define BIT_MASK_BEQ_DESC_NUM_8822B 0xfff
+#define BIT_BEQ_DESC_NUM_8822B(x)                                              \
+	(((x) & BIT_MASK_BEQ_DESC_NUM_8822B) << BIT_SHIFT_BEQ_DESC_NUM_8822B)
+#define BITS_BEQ_DESC_NUM_8822B                                                \
+	(BIT_MASK_BEQ_DESC_NUM_8822B << BIT_SHIFT_BEQ_DESC_NUM_8822B)
+#define BIT_CLEAR_BEQ_DESC_NUM_8822B(x) ((x) & (~BITS_BEQ_DESC_NUM_8822B))
+#define BIT_GET_BEQ_DESC_NUM_8822B(x)                                          \
+	(((x) >> BIT_SHIFT_BEQ_DESC_NUM_8822B) & BIT_MASK_BEQ_DESC_NUM_8822B)
+#define BIT_SET_BEQ_DESC_NUM_8822B(x, v)                                       \
+	(BIT_CLEAR_BEQ_DESC_NUM_8822B(x) | BIT_BEQ_DESC_NUM_8822B(v))
+
+/* 2 REG_BKQ_TXBD_NUM_8822B */
+#define BIT_PCIE_BKQ_FLAG_8822B BIT(14)
+
+#define BIT_SHIFT_BKQ_DESC_MODE_8822B 12
+#define BIT_MASK_BKQ_DESC_MODE_8822B 0x3
+#define BIT_BKQ_DESC_MODE_8822B(x)                                             \
+	(((x) & BIT_MASK_BKQ_DESC_MODE_8822B) << BIT_SHIFT_BKQ_DESC_MODE_8822B)
+#define BITS_BKQ_DESC_MODE_8822B                                               \
+	(BIT_MASK_BKQ_DESC_MODE_8822B << BIT_SHIFT_BKQ_DESC_MODE_8822B)
+#define BIT_CLEAR_BKQ_DESC_MODE_8822B(x) ((x) & (~BITS_BKQ_DESC_MODE_8822B))
+#define BIT_GET_BKQ_DESC_MODE_8822B(x)                                         \
+	(((x) >> BIT_SHIFT_BKQ_DESC_MODE_8822B) & BIT_MASK_BKQ_DESC_MODE_8822B)
+#define BIT_SET_BKQ_DESC_MODE_8822B(x, v)                                      \
+	(BIT_CLEAR_BKQ_DESC_MODE_8822B(x) | BIT_BKQ_DESC_MODE_8822B(v))
+
+#define BIT_SHIFT_BKQ_DESC_NUM_8822B 0
+#define BIT_MASK_BKQ_DESC_NUM_8822B 0xfff
+#define BIT_BKQ_DESC_NUM_8822B(x)                                              \
+	(((x) & BIT_MASK_BKQ_DESC_NUM_8822B) << BIT_SHIFT_BKQ_DESC_NUM_8822B)
+#define BITS_BKQ_DESC_NUM_8822B                                                \
+	(BIT_MASK_BKQ_DESC_NUM_8822B << BIT_SHIFT_BKQ_DESC_NUM_8822B)
+#define BIT_CLEAR_BKQ_DESC_NUM_8822B(x) ((x) & (~BITS_BKQ_DESC_NUM_8822B))
+#define BIT_GET_BKQ_DESC_NUM_8822B(x)                                          \
+	(((x) >> BIT_SHIFT_BKQ_DESC_NUM_8822B) & BIT_MASK_BKQ_DESC_NUM_8822B)
+#define BIT_SET_BKQ_DESC_NUM_8822B(x, v)                                       \
+	(BIT_CLEAR_BKQ_DESC_NUM_8822B(x) | BIT_BKQ_DESC_NUM_8822B(v))
+
+/* 2 REG_HI0Q_TXBD_NUM_8822B */
+#define BIT_HI0Q_FLAG_8822B BIT(14)
+
+#define BIT_SHIFT_HI0Q_DESC_MODE_8822B 12
+#define BIT_MASK_HI0Q_DESC_MODE_8822B 0x3
+#define BIT_HI0Q_DESC_MODE_8822B(x)                                            \
+	(((x) & BIT_MASK_HI0Q_DESC_MODE_8822B)                                 \
+	 << BIT_SHIFT_HI0Q_DESC_MODE_8822B)
+#define BITS_HI0Q_DESC_MODE_8822B                                              \
+	(BIT_MASK_HI0Q_DESC_MODE_8822B << BIT_SHIFT_HI0Q_DESC_MODE_8822B)
+#define BIT_CLEAR_HI0Q_DESC_MODE_8822B(x) ((x) & (~BITS_HI0Q_DESC_MODE_8822B))
+#define BIT_GET_HI0Q_DESC_MODE_8822B(x)                                        \
+	(((x) >> BIT_SHIFT_HI0Q_DESC_MODE_8822B) &                             \
+	 BIT_MASK_HI0Q_DESC_MODE_8822B)
+#define BIT_SET_HI0Q_DESC_MODE_8822B(x, v)                                     \
+	(BIT_CLEAR_HI0Q_DESC_MODE_8822B(x) | BIT_HI0Q_DESC_MODE_8822B(v))
+
+#define BIT_SHIFT_HI0Q_DESC_NUM_8822B 0
+#define BIT_MASK_HI0Q_DESC_NUM_8822B 0xfff
+#define BIT_HI0Q_DESC_NUM_8822B(x)                                             \
+	(((x) & BIT_MASK_HI0Q_DESC_NUM_8822B) << BIT_SHIFT_HI0Q_DESC_NUM_8822B)
+#define BITS_HI0Q_DESC_NUM_8822B                                               \
+	(BIT_MASK_HI0Q_DESC_NUM_8822B << BIT_SHIFT_HI0Q_DESC_NUM_8822B)
+#define BIT_CLEAR_HI0Q_DESC_NUM_8822B(x) ((x) & (~BITS_HI0Q_DESC_NUM_8822B))
+#define BIT_GET_HI0Q_DESC_NUM_8822B(x)                                         \
+	(((x) >> BIT_SHIFT_HI0Q_DESC_NUM_8822B) & BIT_MASK_HI0Q_DESC_NUM_8822B)
+#define BIT_SET_HI0Q_DESC_NUM_8822B(x, v)                                      \
+	(BIT_CLEAR_HI0Q_DESC_NUM_8822B(x) | BIT_HI0Q_DESC_NUM_8822B(v))
+
+/* 2 REG_HI1Q_TXBD_NUM_8822B */
+#define BIT_HI1Q_FLAG_8822B BIT(14)
+
+#define BIT_SHIFT_HI1Q_DESC_MODE_8822B 12
+#define BIT_MASK_HI1Q_DESC_MODE_8822B 0x3
+#define BIT_HI1Q_DESC_MODE_8822B(x)                                            \
+	(((x) & BIT_MASK_HI1Q_DESC_MODE_8822B)                                 \
+	 << BIT_SHIFT_HI1Q_DESC_MODE_8822B)
+#define BITS_HI1Q_DESC_MODE_8822B                                              \
+	(BIT_MASK_HI1Q_DESC_MODE_8822B << BIT_SHIFT_HI1Q_DESC_MODE_8822B)
+#define BIT_CLEAR_HI1Q_DESC_MODE_8822B(x) ((x) & (~BITS_HI1Q_DESC_MODE_8822B))
+#define BIT_GET_HI1Q_DESC_MODE_8822B(x)                                        \
+	(((x) >> BIT_SHIFT_HI1Q_DESC_MODE_8822B) &                             \
+	 BIT_MASK_HI1Q_DESC_MODE_8822B)
+#define BIT_SET_HI1Q_DESC_MODE_8822B(x, v)                                     \
+	(BIT_CLEAR_HI1Q_DESC_MODE_8822B(x) | BIT_HI1Q_DESC_MODE_8822B(v))
+
+#define BIT_SHIFT_HI1Q_DESC_NUM_8822B 0
+#define BIT_MASK_HI1Q_DESC_NUM_8822B 0xfff
+#define BIT_HI1Q_DESC_NUM_8822B(x)                                             \
+	(((x) & BIT_MASK_HI1Q_DESC_NUM_8822B) << BIT_SHIFT_HI1Q_DESC_NUM_8822B)
+#define BITS_HI1Q_DESC_NUM_8822B                                               \
+	(BIT_MASK_HI1Q_DESC_NUM_8822B << BIT_SHIFT_HI1Q_DESC_NUM_8822B)
+#define BIT_CLEAR_HI1Q_DESC_NUM_8822B(x) ((x) & (~BITS_HI1Q_DESC_NUM_8822B))
+#define BIT_GET_HI1Q_DESC_NUM_8822B(x)                                         \
+	(((x) >> BIT_SHIFT_HI1Q_DESC_NUM_8822B) & BIT_MASK_HI1Q_DESC_NUM_8822B)
+#define BIT_SET_HI1Q_DESC_NUM_8822B(x, v)                                      \
+	(BIT_CLEAR_HI1Q_DESC_NUM_8822B(x) | BIT_HI1Q_DESC_NUM_8822B(v))
+
+/* 2 REG_HI2Q_TXBD_NUM_8822B */
+#define BIT_HI2Q_FLAG_8822B BIT(14)
+
+#define BIT_SHIFT_HI2Q_DESC_MODE_8822B 12
+#define BIT_MASK_HI2Q_DESC_MODE_8822B 0x3
+#define BIT_HI2Q_DESC_MODE_8822B(x)                                            \
+	(((x) & BIT_MASK_HI2Q_DESC_MODE_8822B)                                 \
+	 << BIT_SHIFT_HI2Q_DESC_MODE_8822B)
+#define BITS_HI2Q_DESC_MODE_8822B                                              \
+	(BIT_MASK_HI2Q_DESC_MODE_8822B << BIT_SHIFT_HI2Q_DESC_MODE_8822B)
+#define BIT_CLEAR_HI2Q_DESC_MODE_8822B(x) ((x) & (~BITS_HI2Q_DESC_MODE_8822B))
+#define BIT_GET_HI2Q_DESC_MODE_8822B(x)                                        \
+	(((x) >> BIT_SHIFT_HI2Q_DESC_MODE_8822B) &                             \
+	 BIT_MASK_HI2Q_DESC_MODE_8822B)
+#define BIT_SET_HI2Q_DESC_MODE_8822B(x, v)                                     \
+	(BIT_CLEAR_HI2Q_DESC_MODE_8822B(x) | BIT_HI2Q_DESC_MODE_8822B(v))
+
+#define BIT_SHIFT_HI2Q_DESC_NUM_8822B 0
+#define BIT_MASK_HI2Q_DESC_NUM_8822B 0xfff
+#define BIT_HI2Q_DESC_NUM_8822B(x)                                             \
+	(((x) & BIT_MASK_HI2Q_DESC_NUM_8822B) << BIT_SHIFT_HI2Q_DESC_NUM_8822B)
+#define BITS_HI2Q_DESC_NUM_8822B                                               \
+	(BIT_MASK_HI2Q_DESC_NUM_8822B << BIT_SHIFT_HI2Q_DESC_NUM_8822B)
+#define BIT_CLEAR_HI2Q_DESC_NUM_8822B(x) ((x) & (~BITS_HI2Q_DESC_NUM_8822B))
+#define BIT_GET_HI2Q_DESC_NUM_8822B(x)                                         \
+	(((x) >> BIT_SHIFT_HI2Q_DESC_NUM_8822B) & BIT_MASK_HI2Q_DESC_NUM_8822B)
+#define BIT_SET_HI2Q_DESC_NUM_8822B(x, v)                                      \
+	(BIT_CLEAR_HI2Q_DESC_NUM_8822B(x) | BIT_HI2Q_DESC_NUM_8822B(v))
+
+/* 2 REG_HI3Q_TXBD_NUM_8822B */
+#define BIT_HI3Q_FLAG_8822B BIT(14)
+
+#define BIT_SHIFT_HI3Q_DESC_MODE_8822B 12
+#define BIT_MASK_HI3Q_DESC_MODE_8822B 0x3
+#define BIT_HI3Q_DESC_MODE_8822B(x)                                            \
+	(((x) & BIT_MASK_HI3Q_DESC_MODE_8822B)                                 \
+	 << BIT_SHIFT_HI3Q_DESC_MODE_8822B)
+#define BITS_HI3Q_DESC_MODE_8822B                                              \
+	(BIT_MASK_HI3Q_DESC_MODE_8822B << BIT_SHIFT_HI3Q_DESC_MODE_8822B)
+#define BIT_CLEAR_HI3Q_DESC_MODE_8822B(x) ((x) & (~BITS_HI3Q_DESC_MODE_8822B))
+#define BIT_GET_HI3Q_DESC_MODE_8822B(x)                                        \
+	(((x) >> BIT_SHIFT_HI3Q_DESC_MODE_8822B) &                             \
+	 BIT_MASK_HI3Q_DESC_MODE_8822B)
+#define BIT_SET_HI3Q_DESC_MODE_8822B(x, v)                                     \
+	(BIT_CLEAR_HI3Q_DESC_MODE_8822B(x) | BIT_HI3Q_DESC_MODE_8822B(v))
+
+#define BIT_SHIFT_HI3Q_DESC_NUM_8822B 0
+#define BIT_MASK_HI3Q_DESC_NUM_8822B 0xfff
+#define BIT_HI3Q_DESC_NUM_8822B(x)                                             \
+	(((x) & BIT_MASK_HI3Q_DESC_NUM_8822B) << BIT_SHIFT_HI3Q_DESC_NUM_8822B)
+#define BITS_HI3Q_DESC_NUM_8822B                                               \
+	(BIT_MASK_HI3Q_DESC_NUM_8822B << BIT_SHIFT_HI3Q_DESC_NUM_8822B)
+#define BIT_CLEAR_HI3Q_DESC_NUM_8822B(x) ((x) & (~BITS_HI3Q_DESC_NUM_8822B))
+#define BIT_GET_HI3Q_DESC_NUM_8822B(x)                                         \
+	(((x) >> BIT_SHIFT_HI3Q_DESC_NUM_8822B) & BIT_MASK_HI3Q_DESC_NUM_8822B)
+#define BIT_SET_HI3Q_DESC_NUM_8822B(x, v)                                      \
+	(BIT_CLEAR_HI3Q_DESC_NUM_8822B(x) | BIT_HI3Q_DESC_NUM_8822B(v))
+
+/* 2 REG_HI4Q_TXBD_NUM_8822B */
+#define BIT_HI4Q_FLAG_8822B BIT(14)
+
+#define BIT_SHIFT_HI4Q_DESC_MODE_8822B 12
+#define BIT_MASK_HI4Q_DESC_MODE_8822B 0x3
+#define BIT_HI4Q_DESC_MODE_8822B(x)                                            \
+	(((x) & BIT_MASK_HI4Q_DESC_MODE_8822B)                                 \
+	 << BIT_SHIFT_HI4Q_DESC_MODE_8822B)
+#define BITS_HI4Q_DESC_MODE_8822B                                              \
+	(BIT_MASK_HI4Q_DESC_MODE_8822B << BIT_SHIFT_HI4Q_DESC_MODE_8822B)
+#define BIT_CLEAR_HI4Q_DESC_MODE_8822B(x) ((x) & (~BITS_HI4Q_DESC_MODE_8822B))
+#define BIT_GET_HI4Q_DESC_MODE_8822B(x)                                        \
+	(((x) >> BIT_SHIFT_HI4Q_DESC_MODE_8822B) &                             \
+	 BIT_MASK_HI4Q_DESC_MODE_8822B)
+#define BIT_SET_HI4Q_DESC_MODE_8822B(x, v)                                     \
+	(BIT_CLEAR_HI4Q_DESC_MODE_8822B(x) | BIT_HI4Q_DESC_MODE_8822B(v))
+
+#define BIT_SHIFT_HI4Q_DESC_NUM_8822B 0
+#define BIT_MASK_HI4Q_DESC_NUM_8822B 0xfff
+#define BIT_HI4Q_DESC_NUM_8822B(x)                                             \
+	(((x) & BIT_MASK_HI4Q_DESC_NUM_8822B) << BIT_SHIFT_HI4Q_DESC_NUM_8822B)
+#define BITS_HI4Q_DESC_NUM_8822B                                               \
+	(BIT_MASK_HI4Q_DESC_NUM_8822B << BIT_SHIFT_HI4Q_DESC_NUM_8822B)
+#define BIT_CLEAR_HI4Q_DESC_NUM_8822B(x) ((x) & (~BITS_HI4Q_DESC_NUM_8822B))
+#define BIT_GET_HI4Q_DESC_NUM_8822B(x)                                         \
+	(((x) >> BIT_SHIFT_HI4Q_DESC_NUM_8822B) & BIT_MASK_HI4Q_DESC_NUM_8822B)
+#define BIT_SET_HI4Q_DESC_NUM_8822B(x, v)                                      \
+	(BIT_CLEAR_HI4Q_DESC_NUM_8822B(x) | BIT_HI4Q_DESC_NUM_8822B(v))
+
+/* 2 REG_HI5Q_TXBD_NUM_8822B */
+#define BIT_HI5Q_FLAG_8822B BIT(14)
+
+#define BIT_SHIFT_HI5Q_DESC_MODE_8822B 12
+#define BIT_MASK_HI5Q_DESC_MODE_8822B 0x3
+#define BIT_HI5Q_DESC_MODE_8822B(x)                                            \
+	(((x) & BIT_MASK_HI5Q_DESC_MODE_8822B)                                 \
+	 << BIT_SHIFT_HI5Q_DESC_MODE_8822B)
+#define BITS_HI5Q_DESC_MODE_8822B                                              \
+	(BIT_MASK_HI5Q_DESC_MODE_8822B << BIT_SHIFT_HI5Q_DESC_MODE_8822B)
+#define BIT_CLEAR_HI5Q_DESC_MODE_8822B(x) ((x) & (~BITS_HI5Q_DESC_MODE_8822B))
+#define BIT_GET_HI5Q_DESC_MODE_8822B(x)                                        \
+	(((x) >> BIT_SHIFT_HI5Q_DESC_MODE_8822B) &                             \
+	 BIT_MASK_HI5Q_DESC_MODE_8822B)
+#define BIT_SET_HI5Q_DESC_MODE_8822B(x, v)                                     \
+	(BIT_CLEAR_HI5Q_DESC_MODE_8822B(x) | BIT_HI5Q_DESC_MODE_8822B(v))
+
+#define BIT_SHIFT_HI5Q_DESC_NUM_8822B 0
+#define BIT_MASK_HI5Q_DESC_NUM_8822B 0xfff
+#define BIT_HI5Q_DESC_NUM_8822B(x)                                             \
+	(((x) & BIT_MASK_HI5Q_DESC_NUM_8822B) << BIT_SHIFT_HI5Q_DESC_NUM_8822B)
+#define BITS_HI5Q_DESC_NUM_8822B                                               \
+	(BIT_MASK_HI5Q_DESC_NUM_8822B << BIT_SHIFT_HI5Q_DESC_NUM_8822B)
+#define BIT_CLEAR_HI5Q_DESC_NUM_8822B(x) ((x) & (~BITS_HI5Q_DESC_NUM_8822B))
+#define BIT_GET_HI5Q_DESC_NUM_8822B(x)                                         \
+	(((x) >> BIT_SHIFT_HI5Q_DESC_NUM_8822B) & BIT_MASK_HI5Q_DESC_NUM_8822B)
+#define BIT_SET_HI5Q_DESC_NUM_8822B(x, v)                                      \
+	(BIT_CLEAR_HI5Q_DESC_NUM_8822B(x) | BIT_HI5Q_DESC_NUM_8822B(v))
+
+/* 2 REG_HI6Q_TXBD_NUM_8822B */
+#define BIT_HI6Q_FLAG_8822B BIT(14)
+
+#define BIT_SHIFT_HI6Q_DESC_MODE_8822B 12
+#define BIT_MASK_HI6Q_DESC_MODE_8822B 0x3
+#define BIT_HI6Q_DESC_MODE_8822B(x)                                            \
+	(((x) & BIT_MASK_HI6Q_DESC_MODE_8822B)                                 \
+	 << BIT_SHIFT_HI6Q_DESC_MODE_8822B)
+#define BITS_HI6Q_DESC_MODE_8822B                                              \
+	(BIT_MASK_HI6Q_DESC_MODE_8822B << BIT_SHIFT_HI6Q_DESC_MODE_8822B)
+#define BIT_CLEAR_HI6Q_DESC_MODE_8822B(x) ((x) & (~BITS_HI6Q_DESC_MODE_8822B))
+#define BIT_GET_HI6Q_DESC_MODE_8822B(x)                                        \
+	(((x) >> BIT_SHIFT_HI6Q_DESC_MODE_8822B) &                             \
+	 BIT_MASK_HI6Q_DESC_MODE_8822B)
+#define BIT_SET_HI6Q_DESC_MODE_8822B(x, v)                                     \
+	(BIT_CLEAR_HI6Q_DESC_MODE_8822B(x) | BIT_HI6Q_DESC_MODE_8822B(v))
+
+#define BIT_SHIFT_HI6Q_DESC_NUM_8822B 0
+#define BIT_MASK_HI6Q_DESC_NUM_8822B 0xfff
+#define BIT_HI6Q_DESC_NUM_8822B(x)                                             \
+	(((x) & BIT_MASK_HI6Q_DESC_NUM_8822B) << BIT_SHIFT_HI6Q_DESC_NUM_8822B)
+#define BITS_HI6Q_DESC_NUM_8822B                                               \
+	(BIT_MASK_HI6Q_DESC_NUM_8822B << BIT_SHIFT_HI6Q_DESC_NUM_8822B)
+#define BIT_CLEAR_HI6Q_DESC_NUM_8822B(x) ((x) & (~BITS_HI6Q_DESC_NUM_8822B))
+#define BIT_GET_HI6Q_DESC_NUM_8822B(x)                                         \
+	(((x) >> BIT_SHIFT_HI6Q_DESC_NUM_8822B) & BIT_MASK_HI6Q_DESC_NUM_8822B)
+#define BIT_SET_HI6Q_DESC_NUM_8822B(x, v)                                      \
+	(BIT_CLEAR_HI6Q_DESC_NUM_8822B(x) | BIT_HI6Q_DESC_NUM_8822B(v))
+
+/* 2 REG_HI7Q_TXBD_NUM_8822B */
+#define BIT_HI7Q_FLAG_8822B BIT(14)
+
+#define BIT_SHIFT_HI7Q_DESC_MODE_8822B 12
+#define BIT_MASK_HI7Q_DESC_MODE_8822B 0x3
+#define BIT_HI7Q_DESC_MODE_8822B(x)                                            \
+	(((x) & BIT_MASK_HI7Q_DESC_MODE_8822B)                                 \
+	 << BIT_SHIFT_HI7Q_DESC_MODE_8822B)
+#define BITS_HI7Q_DESC_MODE_8822B                                              \
+	(BIT_MASK_HI7Q_DESC_MODE_8822B << BIT_SHIFT_HI7Q_DESC_MODE_8822B)
+#define BIT_CLEAR_HI7Q_DESC_MODE_8822B(x) ((x) & (~BITS_HI7Q_DESC_MODE_8822B))
+#define BIT_GET_HI7Q_DESC_MODE_8822B(x)                                        \
+	(((x) >> BIT_SHIFT_HI7Q_DESC_MODE_8822B) &                             \
+	 BIT_MASK_HI7Q_DESC_MODE_8822B)
+#define BIT_SET_HI7Q_DESC_MODE_8822B(x, v)                                     \
+	(BIT_CLEAR_HI7Q_DESC_MODE_8822B(x) | BIT_HI7Q_DESC_MODE_8822B(v))
+
+#define BIT_SHIFT_HI7Q_DESC_NUM_8822B 0
+#define BIT_MASK_HI7Q_DESC_NUM_8822B 0xfff
+#define BIT_HI7Q_DESC_NUM_8822B(x)                                             \
+	(((x) & BIT_MASK_HI7Q_DESC_NUM_8822B) << BIT_SHIFT_HI7Q_DESC_NUM_8822B)
+#define BITS_HI7Q_DESC_NUM_8822B                                               \
+	(BIT_MASK_HI7Q_DESC_NUM_8822B << BIT_SHIFT_HI7Q_DESC_NUM_8822B)
+#define BIT_CLEAR_HI7Q_DESC_NUM_8822B(x) ((x) & (~BITS_HI7Q_DESC_NUM_8822B))
+#define BIT_GET_HI7Q_DESC_NUM_8822B(x)                                         \
+	(((x) >> BIT_SHIFT_HI7Q_DESC_NUM_8822B) & BIT_MASK_HI7Q_DESC_NUM_8822B)
+#define BIT_SET_HI7Q_DESC_NUM_8822B(x, v)                                      \
+	(BIT_CLEAR_HI7Q_DESC_NUM_8822B(x) | BIT_HI7Q_DESC_NUM_8822B(v))
+
+/* 2 REG_TSFTIMER_HCI_8822B */
+
+#define BIT_SHIFT_TSFT2_HCI_8822B 16
+#define BIT_MASK_TSFT2_HCI_8822B 0xffff
+#define BIT_TSFT2_HCI_8822B(x)                                                 \
+	(((x) & BIT_MASK_TSFT2_HCI_8822B) << BIT_SHIFT_TSFT2_HCI_8822B)
+#define BITS_TSFT2_HCI_8822B                                                   \
+	(BIT_MASK_TSFT2_HCI_8822B << BIT_SHIFT_TSFT2_HCI_8822B)
+#define BIT_CLEAR_TSFT2_HCI_8822B(x) ((x) & (~BITS_TSFT2_HCI_8822B))
+#define BIT_GET_TSFT2_HCI_8822B(x)                                             \
+	(((x) >> BIT_SHIFT_TSFT2_HCI_8822B) & BIT_MASK_TSFT2_HCI_8822B)
+#define BIT_SET_TSFT2_HCI_8822B(x, v)                                          \
+	(BIT_CLEAR_TSFT2_HCI_8822B(x) | BIT_TSFT2_HCI_8822B(v))
+
+#define BIT_SHIFT_TSFT1_HCI_8822B 0
+#define BIT_MASK_TSFT1_HCI_8822B 0xffff
+#define BIT_TSFT1_HCI_8822B(x)                                                 \
+	(((x) & BIT_MASK_TSFT1_HCI_8822B) << BIT_SHIFT_TSFT1_HCI_8822B)
+#define BITS_TSFT1_HCI_8822B                                                   \
+	(BIT_MASK_TSFT1_HCI_8822B << BIT_SHIFT_TSFT1_HCI_8822B)
+#define BIT_CLEAR_TSFT1_HCI_8822B(x) ((x) & (~BITS_TSFT1_HCI_8822B))
+#define BIT_GET_TSFT1_HCI_8822B(x)                                             \
+	(((x) >> BIT_SHIFT_TSFT1_HCI_8822B) & BIT_MASK_TSFT1_HCI_8822B)
+#define BIT_SET_TSFT1_HCI_8822B(x, v)                                          \
+	(BIT_CLEAR_TSFT1_HCI_8822B(x) | BIT_TSFT1_HCI_8822B(v))
+
+/* 2 REG_BD_RWPTR_CLR_8822B */
+#define BIT_CLR_HI7Q_HW_IDX_8822B BIT(29)
+#define BIT_CLR_HI6Q_HW_IDX_8822B BIT(28)
+#define BIT_CLR_HI5Q_HW_IDX_8822B BIT(27)
+#define BIT_CLR_HI4Q_HW_IDX_8822B BIT(26)
+#define BIT_CLR_HI3Q_HW_IDX_8822B BIT(25)
+#define BIT_CLR_HI2Q_HW_IDX_8822B BIT(24)
+#define BIT_CLR_HI1Q_HW_IDX_8822B BIT(23)
+#define BIT_CLR_HI0Q_HW_IDX_8822B BIT(22)
+#define BIT_CLR_BKQ_HW_IDX_8822B BIT(21)
+#define BIT_CLR_BEQ_HW_IDX_8822B BIT(20)
+#define BIT_CLR_VIQ_HW_IDX_8822B BIT(19)
+#define BIT_CLR_VOQ_HW_IDX_8822B BIT(18)
+#define BIT_CLR_MGQ_HW_IDX_8822B BIT(17)
+#define BIT_CLR_RXQ_HW_IDX_8822B BIT(16)
+#define BIT_CLR_HI7Q_HOST_IDX_8822B BIT(13)
+#define BIT_CLR_HI6Q_HOST_IDX_8822B BIT(12)
+#define BIT_CLR_HI5Q_HOST_IDX_8822B BIT(11)
+#define BIT_CLR_HI4Q_HOST_IDX_8822B BIT(10)
+#define BIT_CLR_HI3Q_HOST_IDX_8822B BIT(9)
+#define BIT_CLR_HI2Q_HOST_IDX_8822B BIT(8)
+#define BIT_CLR_HI1Q_HOST_IDX_8822B BIT(7)
+#define BIT_CLR_HI0Q_HOST_IDX_8822B BIT(6)
+#define BIT_CLR_BKQ_HOST_IDX_8822B BIT(5)
+#define BIT_CLR_BEQ_HOST_IDX_8822B BIT(4)
+#define BIT_CLR_VIQ_HOST_IDX_8822B BIT(3)
+#define BIT_CLR_VOQ_HOST_IDX_8822B BIT(2)
+#define BIT_CLR_MGQ_HOST_IDX_8822B BIT(1)
+#define BIT_CLR_RXQ_HOST_IDX_8822B BIT(0)
+
+/* 2 REG_VOQ_TXBD_IDX_8822B */
+
+#define BIT_SHIFT_VOQ_HW_IDX_8822B 16
+#define BIT_MASK_VOQ_HW_IDX_8822B 0xfff
+#define BIT_VOQ_HW_IDX_8822B(x)                                                \
+	(((x) & BIT_MASK_VOQ_HW_IDX_8822B) << BIT_SHIFT_VOQ_HW_IDX_8822B)
+#define BITS_VOQ_HW_IDX_8822B                                                  \
+	(BIT_MASK_VOQ_HW_IDX_8822B << BIT_SHIFT_VOQ_HW_IDX_8822B)
+#define BIT_CLEAR_VOQ_HW_IDX_8822B(x) ((x) & (~BITS_VOQ_HW_IDX_8822B))
+#define BIT_GET_VOQ_HW_IDX_8822B(x)                                            \
+	(((x) >> BIT_SHIFT_VOQ_HW_IDX_8822B) & BIT_MASK_VOQ_HW_IDX_8822B)
+#define BIT_SET_VOQ_HW_IDX_8822B(x, v)                                         \
+	(BIT_CLEAR_VOQ_HW_IDX_8822B(x) | BIT_VOQ_HW_IDX_8822B(v))
+
+#define BIT_SHIFT_VOQ_HOST_IDX_8822B 0
+#define BIT_MASK_VOQ_HOST_IDX_8822B 0xfff
+#define BIT_VOQ_HOST_IDX_8822B(x)                                              \
+	(((x) & BIT_MASK_VOQ_HOST_IDX_8822B) << BIT_SHIFT_VOQ_HOST_IDX_8822B)
+#define BITS_VOQ_HOST_IDX_8822B                                                \
+	(BIT_MASK_VOQ_HOST_IDX_8822B << BIT_SHIFT_VOQ_HOST_IDX_8822B)
+#define BIT_CLEAR_VOQ_HOST_IDX_8822B(x) ((x) & (~BITS_VOQ_HOST_IDX_8822B))
+#define BIT_GET_VOQ_HOST_IDX_8822B(x)                                          \
+	(((x) >> BIT_SHIFT_VOQ_HOST_IDX_8822B) & BIT_MASK_VOQ_HOST_IDX_8822B)
+#define BIT_SET_VOQ_HOST_IDX_8822B(x, v)                                       \
+	(BIT_CLEAR_VOQ_HOST_IDX_8822B(x) | BIT_VOQ_HOST_IDX_8822B(v))
+
+/* 2 REG_VIQ_TXBD_IDX_8822B */
+
+#define BIT_SHIFT_VIQ_HW_IDX_8822B 16
+#define BIT_MASK_VIQ_HW_IDX_8822B 0xfff
+#define BIT_VIQ_HW_IDX_8822B(x)                                                \
+	(((x) & BIT_MASK_VIQ_HW_IDX_8822B) << BIT_SHIFT_VIQ_HW_IDX_8822B)
+#define BITS_VIQ_HW_IDX_8822B                                                  \
+	(BIT_MASK_VIQ_HW_IDX_8822B << BIT_SHIFT_VIQ_HW_IDX_8822B)
+#define BIT_CLEAR_VIQ_HW_IDX_8822B(x) ((x) & (~BITS_VIQ_HW_IDX_8822B))
+#define BIT_GET_VIQ_HW_IDX_8822B(x)                                            \
+	(((x) >> BIT_SHIFT_VIQ_HW_IDX_8822B) & BIT_MASK_VIQ_HW_IDX_8822B)
+#define BIT_SET_VIQ_HW_IDX_8822B(x, v)                                         \
+	(BIT_CLEAR_VIQ_HW_IDX_8822B(x) | BIT_VIQ_HW_IDX_8822B(v))
+
+#define BIT_SHIFT_VIQ_HOST_IDX_8822B 0
+#define BIT_MASK_VIQ_HOST_IDX_8822B 0xfff
+#define BIT_VIQ_HOST_IDX_8822B(x)                                              \
+	(((x) & BIT_MASK_VIQ_HOST_IDX_8822B) << BIT_SHIFT_VIQ_HOST_IDX_8822B)
+#define BITS_VIQ_HOST_IDX_8822B                                                \
+	(BIT_MASK_VIQ_HOST_IDX_8822B << BIT_SHIFT_VIQ_HOST_IDX_8822B)
+#define BIT_CLEAR_VIQ_HOST_IDX_8822B(x) ((x) & (~BITS_VIQ_HOST_IDX_8822B))
+#define BIT_GET_VIQ_HOST_IDX_8822B(x)                                          \
+	(((x) >> BIT_SHIFT_VIQ_HOST_IDX_8822B) & BIT_MASK_VIQ_HOST_IDX_8822B)
+#define BIT_SET_VIQ_HOST_IDX_8822B(x, v)                                       \
+	(BIT_CLEAR_VIQ_HOST_IDX_8822B(x) | BIT_VIQ_HOST_IDX_8822B(v))
+
+/* 2 REG_BEQ_TXBD_IDX_8822B */
+
+#define BIT_SHIFT_BEQ_HW_IDX_8822B 16
+#define BIT_MASK_BEQ_HW_IDX_8822B 0xfff
+#define BIT_BEQ_HW_IDX_8822B(x)                                                \
+	(((x) & BIT_MASK_BEQ_HW_IDX_8822B) << BIT_SHIFT_BEQ_HW_IDX_8822B)
+#define BITS_BEQ_HW_IDX_8822B                                                  \
+	(BIT_MASK_BEQ_HW_IDX_8822B << BIT_SHIFT_BEQ_HW_IDX_8822B)
+#define BIT_CLEAR_BEQ_HW_IDX_8822B(x) ((x) & (~BITS_BEQ_HW_IDX_8822B))
+#define BIT_GET_BEQ_HW_IDX_8822B(x)                                            \
+	(((x) >> BIT_SHIFT_BEQ_HW_IDX_8822B) & BIT_MASK_BEQ_HW_IDX_8822B)
+#define BIT_SET_BEQ_HW_IDX_8822B(x, v)                                         \
+	(BIT_CLEAR_BEQ_HW_IDX_8822B(x) | BIT_BEQ_HW_IDX_8822B(v))
+
+#define BIT_SHIFT_BEQ_HOST_IDX_8822B 0
+#define BIT_MASK_BEQ_HOST_IDX_8822B 0xfff
+#define BIT_BEQ_HOST_IDX_8822B(x)                                              \
+	(((x) & BIT_MASK_BEQ_HOST_IDX_8822B) << BIT_SHIFT_BEQ_HOST_IDX_8822B)
+#define BITS_BEQ_HOST_IDX_8822B                                                \
+	(BIT_MASK_BEQ_HOST_IDX_8822B << BIT_SHIFT_BEQ_HOST_IDX_8822B)
+#define BIT_CLEAR_BEQ_HOST_IDX_8822B(x) ((x) & (~BITS_BEQ_HOST_IDX_8822B))
+#define BIT_GET_BEQ_HOST_IDX_8822B(x)                                          \
+	(((x) >> BIT_SHIFT_BEQ_HOST_IDX_8822B) & BIT_MASK_BEQ_HOST_IDX_8822B)
+#define BIT_SET_BEQ_HOST_IDX_8822B(x, v)                                       \
+	(BIT_CLEAR_BEQ_HOST_IDX_8822B(x) | BIT_BEQ_HOST_IDX_8822B(v))
+
+/* 2 REG_BKQ_TXBD_IDX_8822B */
+
+#define BIT_SHIFT_BKQ_HW_IDX_8822B 16
+#define BIT_MASK_BKQ_HW_IDX_8822B 0xfff
+#define BIT_BKQ_HW_IDX_8822B(x)                                                \
+	(((x) & BIT_MASK_BKQ_HW_IDX_8822B) << BIT_SHIFT_BKQ_HW_IDX_8822B)
+#define BITS_BKQ_HW_IDX_8822B                                                  \
+	(BIT_MASK_BKQ_HW_IDX_8822B << BIT_SHIFT_BKQ_HW_IDX_8822B)
+#define BIT_CLEAR_BKQ_HW_IDX_8822B(x) ((x) & (~BITS_BKQ_HW_IDX_8822B))
+#define BIT_GET_BKQ_HW_IDX_8822B(x)                                            \
+	(((x) >> BIT_SHIFT_BKQ_HW_IDX_8822B) & BIT_MASK_BKQ_HW_IDX_8822B)
+#define BIT_SET_BKQ_HW_IDX_8822B(x, v)                                         \
+	(BIT_CLEAR_BKQ_HW_IDX_8822B(x) | BIT_BKQ_HW_IDX_8822B(v))
+
+#define BIT_SHIFT_BKQ_HOST_IDX_8822B 0
+#define BIT_MASK_BKQ_HOST_IDX_8822B 0xfff
+#define BIT_BKQ_HOST_IDX_8822B(x)                                              \
+	(((x) & BIT_MASK_BKQ_HOST_IDX_8822B) << BIT_SHIFT_BKQ_HOST_IDX_8822B)
+#define BITS_BKQ_HOST_IDX_8822B                                                \
+	(BIT_MASK_BKQ_HOST_IDX_8822B << BIT_SHIFT_BKQ_HOST_IDX_8822B)
+#define BIT_CLEAR_BKQ_HOST_IDX_8822B(x) ((x) & (~BITS_BKQ_HOST_IDX_8822B))
+#define BIT_GET_BKQ_HOST_IDX_8822B(x)                                          \
+	(((x) >> BIT_SHIFT_BKQ_HOST_IDX_8822B) & BIT_MASK_BKQ_HOST_IDX_8822B)
+#define BIT_SET_BKQ_HOST_IDX_8822B(x, v)                                       \
+	(BIT_CLEAR_BKQ_HOST_IDX_8822B(x) | BIT_BKQ_HOST_IDX_8822B(v))
+
+/* 2 REG_MGQ_TXBD_IDX_8822B */
+
+#define BIT_SHIFT_MGQ_HW_IDX_8822B 16
+#define BIT_MASK_MGQ_HW_IDX_8822B 0xfff
+#define BIT_MGQ_HW_IDX_8822B(x)                                                \
+	(((x) & BIT_MASK_MGQ_HW_IDX_8822B) << BIT_SHIFT_MGQ_HW_IDX_8822B)
+#define BITS_MGQ_HW_IDX_8822B                                                  \
+	(BIT_MASK_MGQ_HW_IDX_8822B << BIT_SHIFT_MGQ_HW_IDX_8822B)
+#define BIT_CLEAR_MGQ_HW_IDX_8822B(x) ((x) & (~BITS_MGQ_HW_IDX_8822B))
+#define BIT_GET_MGQ_HW_IDX_8822B(x)                                            \
+	(((x) >> BIT_SHIFT_MGQ_HW_IDX_8822B) & BIT_MASK_MGQ_HW_IDX_8822B)
+#define BIT_SET_MGQ_HW_IDX_8822B(x, v)                                         \
+	(BIT_CLEAR_MGQ_HW_IDX_8822B(x) | BIT_MGQ_HW_IDX_8822B(v))
+
+#define BIT_SHIFT_MGQ_HOST_IDX_8822B 0
+#define BIT_MASK_MGQ_HOST_IDX_8822B 0xfff
+#define BIT_MGQ_HOST_IDX_8822B(x)                                              \
+	(((x) & BIT_MASK_MGQ_HOST_IDX_8822B) << BIT_SHIFT_MGQ_HOST_IDX_8822B)
+#define BITS_MGQ_HOST_IDX_8822B                                                \
+	(BIT_MASK_MGQ_HOST_IDX_8822B << BIT_SHIFT_MGQ_HOST_IDX_8822B)
+#define BIT_CLEAR_MGQ_HOST_IDX_8822B(x) ((x) & (~BITS_MGQ_HOST_IDX_8822B))
+#define BIT_GET_MGQ_HOST_IDX_8822B(x)                                          \
+	(((x) >> BIT_SHIFT_MGQ_HOST_IDX_8822B) & BIT_MASK_MGQ_HOST_IDX_8822B)
+#define BIT_SET_MGQ_HOST_IDX_8822B(x, v)                                       \
+	(BIT_CLEAR_MGQ_HOST_IDX_8822B(x) | BIT_MGQ_HOST_IDX_8822B(v))
+
+/* 2 REG_RXQ_RXBD_IDX_8822B */
+
+#define BIT_SHIFT_RXQ_HW_IDX_8822B 16
+#define BIT_MASK_RXQ_HW_IDX_8822B 0xfff
+#define BIT_RXQ_HW_IDX_8822B(x)                                                \
+	(((x) & BIT_MASK_RXQ_HW_IDX_8822B) << BIT_SHIFT_RXQ_HW_IDX_8822B)
+#define BITS_RXQ_HW_IDX_8822B                                                  \
+	(BIT_MASK_RXQ_HW_IDX_8822B << BIT_SHIFT_RXQ_HW_IDX_8822B)
+#define BIT_CLEAR_RXQ_HW_IDX_8822B(x) ((x) & (~BITS_RXQ_HW_IDX_8822B))
+#define BIT_GET_RXQ_HW_IDX_8822B(x)                                            \
+	(((x) >> BIT_SHIFT_RXQ_HW_IDX_8822B) & BIT_MASK_RXQ_HW_IDX_8822B)
+#define BIT_SET_RXQ_HW_IDX_8822B(x, v)                                         \
+	(BIT_CLEAR_RXQ_HW_IDX_8822B(x) | BIT_RXQ_HW_IDX_8822B(v))
+
+#define BIT_SHIFT_RXQ_HOST_IDX_8822B 0
+#define BIT_MASK_RXQ_HOST_IDX_8822B 0xfff
+#define BIT_RXQ_HOST_IDX_8822B(x)                                              \
+	(((x) & BIT_MASK_RXQ_HOST_IDX_8822B) << BIT_SHIFT_RXQ_HOST_IDX_8822B)
+#define BITS_RXQ_HOST_IDX_8822B                                                \
+	(BIT_MASK_RXQ_HOST_IDX_8822B << BIT_SHIFT_RXQ_HOST_IDX_8822B)
+#define BIT_CLEAR_RXQ_HOST_IDX_8822B(x) ((x) & (~BITS_RXQ_HOST_IDX_8822B))
+#define BIT_GET_RXQ_HOST_IDX_8822B(x)                                          \
+	(((x) >> BIT_SHIFT_RXQ_HOST_IDX_8822B) & BIT_MASK_RXQ_HOST_IDX_8822B)
+#define BIT_SET_RXQ_HOST_IDX_8822B(x, v)                                       \
+	(BIT_CLEAR_RXQ_HOST_IDX_8822B(x) | BIT_RXQ_HOST_IDX_8822B(v))
+
+/* 2 REG_HI0Q_TXBD_IDX_8822B */
+
+#define BIT_SHIFT_HI0Q_HW_IDX_8822B 16
+#define BIT_MASK_HI0Q_HW_IDX_8822B 0xfff
+#define BIT_HI0Q_HW_IDX_8822B(x)                                               \
+	(((x) & BIT_MASK_HI0Q_HW_IDX_8822B) << BIT_SHIFT_HI0Q_HW_IDX_8822B)
+#define BITS_HI0Q_HW_IDX_8822B                                                 \
+	(BIT_MASK_HI0Q_HW_IDX_8822B << BIT_SHIFT_HI0Q_HW_IDX_8822B)
+#define BIT_CLEAR_HI0Q_HW_IDX_8822B(x) ((x) & (~BITS_HI0Q_HW_IDX_8822B))
+#define BIT_GET_HI0Q_HW_IDX_8822B(x)                                           \
+	(((x) >> BIT_SHIFT_HI0Q_HW_IDX_8822B) & BIT_MASK_HI0Q_HW_IDX_8822B)
+#define BIT_SET_HI0Q_HW_IDX_8822B(x, v)                                        \
+	(BIT_CLEAR_HI0Q_HW_IDX_8822B(x) | BIT_HI0Q_HW_IDX_8822B(v))
+
+#define BIT_SHIFT_HI0Q_HOST_IDX_8822B 0
+#define BIT_MASK_HI0Q_HOST_IDX_8822B 0xfff
+#define BIT_HI0Q_HOST_IDX_8822B(x)                                             \
+	(((x) & BIT_MASK_HI0Q_HOST_IDX_8822B) << BIT_SHIFT_HI0Q_HOST_IDX_8822B)
+#define BITS_HI0Q_HOST_IDX_8822B                                               \
+	(BIT_MASK_HI0Q_HOST_IDX_8822B << BIT_SHIFT_HI0Q_HOST_IDX_8822B)
+#define BIT_CLEAR_HI0Q_HOST_IDX_8822B(x) ((x) & (~BITS_HI0Q_HOST_IDX_8822B))
+#define BIT_GET_HI0Q_HOST_IDX_8822B(x)                                         \
+	(((x) >> BIT_SHIFT_HI0Q_HOST_IDX_8822B) & BIT_MASK_HI0Q_HOST_IDX_8822B)
+#define BIT_SET_HI0Q_HOST_IDX_8822B(x, v)                                      \
+	(BIT_CLEAR_HI0Q_HOST_IDX_8822B(x) | BIT_HI0Q_HOST_IDX_8822B(v))
+
+/* 2 REG_HI1Q_TXBD_IDX_8822B */
+
+#define BIT_SHIFT_HI1Q_HW_IDX_8822B 16
+#define BIT_MASK_HI1Q_HW_IDX_8822B 0xfff
+#define BIT_HI1Q_HW_IDX_8822B(x)                                               \
+	(((x) & BIT_MASK_HI1Q_HW_IDX_8822B) << BIT_SHIFT_HI1Q_HW_IDX_8822B)
+#define BITS_HI1Q_HW_IDX_8822B                                                 \
+	(BIT_MASK_HI1Q_HW_IDX_8822B << BIT_SHIFT_HI1Q_HW_IDX_8822B)
+#define BIT_CLEAR_HI1Q_HW_IDX_8822B(x) ((x) & (~BITS_HI1Q_HW_IDX_8822B))
+#define BIT_GET_HI1Q_HW_IDX_8822B(x)                                           \
+	(((x) >> BIT_SHIFT_HI1Q_HW_IDX_8822B) & BIT_MASK_HI1Q_HW_IDX_8822B)
+#define BIT_SET_HI1Q_HW_IDX_8822B(x, v)                                        \
+	(BIT_CLEAR_HI1Q_HW_IDX_8822B(x) | BIT_HI1Q_HW_IDX_8822B(v))
+
+#define BIT_SHIFT_HI1Q_HOST_IDX_8822B 0
+#define BIT_MASK_HI1Q_HOST_IDX_8822B 0xfff
+#define BIT_HI1Q_HOST_IDX_8822B(x)                                             \
+	(((x) & BIT_MASK_HI1Q_HOST_IDX_8822B) << BIT_SHIFT_HI1Q_HOST_IDX_8822B)
+#define BITS_HI1Q_HOST_IDX_8822B                                               \
+	(BIT_MASK_HI1Q_HOST_IDX_8822B << BIT_SHIFT_HI1Q_HOST_IDX_8822B)
+#define BIT_CLEAR_HI1Q_HOST_IDX_8822B(x) ((x) & (~BITS_HI1Q_HOST_IDX_8822B))
+#define BIT_GET_HI1Q_HOST_IDX_8822B(x)                                         \
+	(((x) >> BIT_SHIFT_HI1Q_HOST_IDX_8822B) & BIT_MASK_HI1Q_HOST_IDX_8822B)
+#define BIT_SET_HI1Q_HOST_IDX_8822B(x, v)                                      \
+	(BIT_CLEAR_HI1Q_HOST_IDX_8822B(x) | BIT_HI1Q_HOST_IDX_8822B(v))
+
+/* 2 REG_HI2Q_TXBD_IDX_8822B */
+
+#define BIT_SHIFT_HI2Q_HW_IDX_8822B 16
+#define BIT_MASK_HI2Q_HW_IDX_8822B 0xfff
+#define BIT_HI2Q_HW_IDX_8822B(x)                                               \
+	(((x) & BIT_MASK_HI2Q_HW_IDX_8822B) << BIT_SHIFT_HI2Q_HW_IDX_8822B)
+#define BITS_HI2Q_HW_IDX_8822B                                                 \
+	(BIT_MASK_HI2Q_HW_IDX_8822B << BIT_SHIFT_HI2Q_HW_IDX_8822B)
+#define BIT_CLEAR_HI2Q_HW_IDX_8822B(x) ((x) & (~BITS_HI2Q_HW_IDX_8822B))
+#define BIT_GET_HI2Q_HW_IDX_8822B(x)                                           \
+	(((x) >> BIT_SHIFT_HI2Q_HW_IDX_8822B) & BIT_MASK_HI2Q_HW_IDX_8822B)
+#define BIT_SET_HI2Q_HW_IDX_8822B(x, v)                                        \
+	(BIT_CLEAR_HI2Q_HW_IDX_8822B(x) | BIT_HI2Q_HW_IDX_8822B(v))
+
+#define BIT_SHIFT_HI2Q_HOST_IDX_8822B 0
+#define BIT_MASK_HI2Q_HOST_IDX_8822B 0xfff
+#define BIT_HI2Q_HOST_IDX_8822B(x)                                             \
+	(((x) & BIT_MASK_HI2Q_HOST_IDX_8822B) << BIT_SHIFT_HI2Q_HOST_IDX_8822B)
+#define BITS_HI2Q_HOST_IDX_8822B                                               \
+	(BIT_MASK_HI2Q_HOST_IDX_8822B << BIT_SHIFT_HI2Q_HOST_IDX_8822B)
+#define BIT_CLEAR_HI2Q_HOST_IDX_8822B(x) ((x) & (~BITS_HI2Q_HOST_IDX_8822B))
+#define BIT_GET_HI2Q_HOST_IDX_8822B(x)                                         \
+	(((x) >> BIT_SHIFT_HI2Q_HOST_IDX_8822B) & BIT_MASK_HI2Q_HOST_IDX_8822B)
+#define BIT_SET_HI2Q_HOST_IDX_8822B(x, v)                                      \
+	(BIT_CLEAR_HI2Q_HOST_IDX_8822B(x) | BIT_HI2Q_HOST_IDX_8822B(v))
+
+/* 2 REG_HI3Q_TXBD_IDX_8822B */
+
+#define BIT_SHIFT_HI3Q_HW_IDX_8822B 16
+#define BIT_MASK_HI3Q_HW_IDX_8822B 0xfff
+#define BIT_HI3Q_HW_IDX_8822B(x)                                               \
+	(((x) & BIT_MASK_HI3Q_HW_IDX_8822B) << BIT_SHIFT_HI3Q_HW_IDX_8822B)
+#define BITS_HI3Q_HW_IDX_8822B                                                 \
+	(BIT_MASK_HI3Q_HW_IDX_8822B << BIT_SHIFT_HI3Q_HW_IDX_8822B)
+#define BIT_CLEAR_HI3Q_HW_IDX_8822B(x) ((x) & (~BITS_HI3Q_HW_IDX_8822B))
+#define BIT_GET_HI3Q_HW_IDX_8822B(x)                                           \
+	(((x) >> BIT_SHIFT_HI3Q_HW_IDX_8822B) & BIT_MASK_HI3Q_HW_IDX_8822B)
+#define BIT_SET_HI3Q_HW_IDX_8822B(x, v)                                        \
+	(BIT_CLEAR_HI3Q_HW_IDX_8822B(x) | BIT_HI3Q_HW_IDX_8822B(v))
+
+#define BIT_SHIFT_HI3Q_HOST_IDX_8822B 0
+#define BIT_MASK_HI3Q_HOST_IDX_8822B 0xfff
+#define BIT_HI3Q_HOST_IDX_8822B(x)                                             \
+	(((x) & BIT_MASK_HI3Q_HOST_IDX_8822B) << BIT_SHIFT_HI3Q_HOST_IDX_8822B)
+#define BITS_HI3Q_HOST_IDX_8822B                                               \
+	(BIT_MASK_HI3Q_HOST_IDX_8822B << BIT_SHIFT_HI3Q_HOST_IDX_8822B)
+#define BIT_CLEAR_HI3Q_HOST_IDX_8822B(x) ((x) & (~BITS_HI3Q_HOST_IDX_8822B))
+#define BIT_GET_HI3Q_HOST_IDX_8822B(x)                                         \
+	(((x) >> BIT_SHIFT_HI3Q_HOST_IDX_8822B) & BIT_MASK_HI3Q_HOST_IDX_8822B)
+#define BIT_SET_HI3Q_HOST_IDX_8822B(x, v)                                      \
+	(BIT_CLEAR_HI3Q_HOST_IDX_8822B(x) | BIT_HI3Q_HOST_IDX_8822B(v))
+
+/* 2 REG_HI4Q_TXBD_IDX_8822B */
+
+#define BIT_SHIFT_HI4Q_HW_IDX_8822B 16
+#define BIT_MASK_HI4Q_HW_IDX_8822B 0xfff
+#define BIT_HI4Q_HW_IDX_8822B(x)                                               \
+	(((x) & BIT_MASK_HI4Q_HW_IDX_8822B) << BIT_SHIFT_HI4Q_HW_IDX_8822B)
+#define BITS_HI4Q_HW_IDX_8822B                                                 \
+	(BIT_MASK_HI4Q_HW_IDX_8822B << BIT_SHIFT_HI4Q_HW_IDX_8822B)
+#define BIT_CLEAR_HI4Q_HW_IDX_8822B(x) ((x) & (~BITS_HI4Q_HW_IDX_8822B))
+#define BIT_GET_HI4Q_HW_IDX_8822B(x)                                           \
+	(((x) >> BIT_SHIFT_HI4Q_HW_IDX_8822B) & BIT_MASK_HI4Q_HW_IDX_8822B)
+#define BIT_SET_HI4Q_HW_IDX_8822B(x, v)                                        \
+	(BIT_CLEAR_HI4Q_HW_IDX_8822B(x) | BIT_HI4Q_HW_IDX_8822B(v))
+
+#define BIT_SHIFT_HI4Q_HOST_IDX_8822B 0
+#define BIT_MASK_HI4Q_HOST_IDX_8822B 0xfff
+#define BIT_HI4Q_HOST_IDX_8822B(x)                                             \
+	(((x) & BIT_MASK_HI4Q_HOST_IDX_8822B) << BIT_SHIFT_HI4Q_HOST_IDX_8822B)
+#define BITS_HI4Q_HOST_IDX_8822B                                               \
+	(BIT_MASK_HI4Q_HOST_IDX_8822B << BIT_SHIFT_HI4Q_HOST_IDX_8822B)
+#define BIT_CLEAR_HI4Q_HOST_IDX_8822B(x) ((x) & (~BITS_HI4Q_HOST_IDX_8822B))
+#define BIT_GET_HI4Q_HOST_IDX_8822B(x)                                         \
+	(((x) >> BIT_SHIFT_HI4Q_HOST_IDX_8822B) & BIT_MASK_HI4Q_HOST_IDX_8822B)
+#define BIT_SET_HI4Q_HOST_IDX_8822B(x, v)                                      \
+	(BIT_CLEAR_HI4Q_HOST_IDX_8822B(x) | BIT_HI4Q_HOST_IDX_8822B(v))
+
+/* 2 REG_HI5Q_TXBD_IDX_8822B */
+
+#define BIT_SHIFT_HI5Q_HW_IDX_8822B 16
+#define BIT_MASK_HI5Q_HW_IDX_8822B 0xfff
+#define BIT_HI5Q_HW_IDX_8822B(x)                                               \
+	(((x) & BIT_MASK_HI5Q_HW_IDX_8822B) << BIT_SHIFT_HI5Q_HW_IDX_8822B)
+#define BITS_HI5Q_HW_IDX_8822B                                                 \
+	(BIT_MASK_HI5Q_HW_IDX_8822B << BIT_SHIFT_HI5Q_HW_IDX_8822B)
+#define BIT_CLEAR_HI5Q_HW_IDX_8822B(x) ((x) & (~BITS_HI5Q_HW_IDX_8822B))
+#define BIT_GET_HI5Q_HW_IDX_8822B(x)                                           \
+	(((x) >> BIT_SHIFT_HI5Q_HW_IDX_8822B) & BIT_MASK_HI5Q_HW_IDX_8822B)
+#define BIT_SET_HI5Q_HW_IDX_8822B(x, v)                                        \
+	(BIT_CLEAR_HI5Q_HW_IDX_8822B(x) | BIT_HI5Q_HW_IDX_8822B(v))
+
+#define BIT_SHIFT_HI5Q_HOST_IDX_8822B 0
+#define BIT_MASK_HI5Q_HOST_IDX_8822B 0xfff
+#define BIT_HI5Q_HOST_IDX_8822B(x)                                             \
+	(((x) & BIT_MASK_HI5Q_HOST_IDX_8822B) << BIT_SHIFT_HI5Q_HOST_IDX_8822B)
+#define BITS_HI5Q_HOST_IDX_8822B                                               \
+	(BIT_MASK_HI5Q_HOST_IDX_8822B << BIT_SHIFT_HI5Q_HOST_IDX_8822B)
+#define BIT_CLEAR_HI5Q_HOST_IDX_8822B(x) ((x) & (~BITS_HI5Q_HOST_IDX_8822B))
+#define BIT_GET_HI5Q_HOST_IDX_8822B(x)                                         \
+	(((x) >> BIT_SHIFT_HI5Q_HOST_IDX_8822B) & BIT_MASK_HI5Q_HOST_IDX_8822B)
+#define BIT_SET_HI5Q_HOST_IDX_8822B(x, v)                                      \
+	(BIT_CLEAR_HI5Q_HOST_IDX_8822B(x) | BIT_HI5Q_HOST_IDX_8822B(v))
+
+/* 2 REG_HI6Q_TXBD_IDX_8822B */
+
+#define BIT_SHIFT_HI6Q_HW_IDX_8822B 16
+#define BIT_MASK_HI6Q_HW_IDX_8822B 0xfff
+#define BIT_HI6Q_HW_IDX_8822B(x)                                               \
+	(((x) & BIT_MASK_HI6Q_HW_IDX_8822B) << BIT_SHIFT_HI6Q_HW_IDX_8822B)
+#define BITS_HI6Q_HW_IDX_8822B                                                 \
+	(BIT_MASK_HI6Q_HW_IDX_8822B << BIT_SHIFT_HI6Q_HW_IDX_8822B)
+#define BIT_CLEAR_HI6Q_HW_IDX_8822B(x) ((x) & (~BITS_HI6Q_HW_IDX_8822B))
+#define BIT_GET_HI6Q_HW_IDX_8822B(x)                                           \
+	(((x) >> BIT_SHIFT_HI6Q_HW_IDX_8822B) & BIT_MASK_HI6Q_HW_IDX_8822B)
+#define BIT_SET_HI6Q_HW_IDX_8822B(x, v)                                        \
+	(BIT_CLEAR_HI6Q_HW_IDX_8822B(x) | BIT_HI6Q_HW_IDX_8822B(v))
+
+#define BIT_SHIFT_HI6Q_HOST_IDX_8822B 0
+#define BIT_MASK_HI6Q_HOST_IDX_8822B 0xfff
+#define BIT_HI6Q_HOST_IDX_8822B(x)                                             \
+	(((x) & BIT_MASK_HI6Q_HOST_IDX_8822B) << BIT_SHIFT_HI6Q_HOST_IDX_8822B)
+#define BITS_HI6Q_HOST_IDX_8822B                                               \
+	(BIT_MASK_HI6Q_HOST_IDX_8822B << BIT_SHIFT_HI6Q_HOST_IDX_8822B)
+#define BIT_CLEAR_HI6Q_HOST_IDX_8822B(x) ((x) & (~BITS_HI6Q_HOST_IDX_8822B))
+#define BIT_GET_HI6Q_HOST_IDX_8822B(x)                                         \
+	(((x) >> BIT_SHIFT_HI6Q_HOST_IDX_8822B) & BIT_MASK_HI6Q_HOST_IDX_8822B)
+#define BIT_SET_HI6Q_HOST_IDX_8822B(x, v)                                      \
+	(BIT_CLEAR_HI6Q_HOST_IDX_8822B(x) | BIT_HI6Q_HOST_IDX_8822B(v))
+
+/* 2 REG_HI7Q_TXBD_IDX_8822B */
+
+#define BIT_SHIFT_HI7Q_HW_IDX_8822B 16
+#define BIT_MASK_HI7Q_HW_IDX_8822B 0xfff
+#define BIT_HI7Q_HW_IDX_8822B(x)                                               \
+	(((x) & BIT_MASK_HI7Q_HW_IDX_8822B) << BIT_SHIFT_HI7Q_HW_IDX_8822B)
+#define BITS_HI7Q_HW_IDX_8822B                                                 \
+	(BIT_MASK_HI7Q_HW_IDX_8822B << BIT_SHIFT_HI7Q_HW_IDX_8822B)
+#define BIT_CLEAR_HI7Q_HW_IDX_8822B(x) ((x) & (~BITS_HI7Q_HW_IDX_8822B))
+#define BIT_GET_HI7Q_HW_IDX_8822B(x)                                           \
+	(((x) >> BIT_SHIFT_HI7Q_HW_IDX_8822B) & BIT_MASK_HI7Q_HW_IDX_8822B)
+#define BIT_SET_HI7Q_HW_IDX_8822B(x, v)                                        \
+	(BIT_CLEAR_HI7Q_HW_IDX_8822B(x) | BIT_HI7Q_HW_IDX_8822B(v))
+
+#define BIT_SHIFT_HI7Q_HOST_IDX_8822B 0
+#define BIT_MASK_HI7Q_HOST_IDX_8822B 0xfff
+#define BIT_HI7Q_HOST_IDX_8822B(x)                                             \
+	(((x) & BIT_MASK_HI7Q_HOST_IDX_8822B) << BIT_SHIFT_HI7Q_HOST_IDX_8822B)
+#define BITS_HI7Q_HOST_IDX_8822B                                               \
+	(BIT_MASK_HI7Q_HOST_IDX_8822B << BIT_SHIFT_HI7Q_HOST_IDX_8822B)
+#define BIT_CLEAR_HI7Q_HOST_IDX_8822B(x) ((x) & (~BITS_HI7Q_HOST_IDX_8822B))
+#define BIT_GET_HI7Q_HOST_IDX_8822B(x)                                         \
+	(((x) >> BIT_SHIFT_HI7Q_HOST_IDX_8822B) & BIT_MASK_HI7Q_HOST_IDX_8822B)
+#define BIT_SET_HI7Q_HOST_IDX_8822B(x, v)                                      \
+	(BIT_CLEAR_HI7Q_HOST_IDX_8822B(x) | BIT_HI7Q_HOST_IDX_8822B(v))
+
+/* 2 REG_DBG_SEL_V1_8822B */
+
+#define BIT_SHIFT_DBG_SEL_8822B 0
+#define BIT_MASK_DBG_SEL_8822B 0xff
+#define BIT_DBG_SEL_8822B(x)                                                   \
+	(((x) & BIT_MASK_DBG_SEL_8822B) << BIT_SHIFT_DBG_SEL_8822B)
+#define BITS_DBG_SEL_8822B (BIT_MASK_DBG_SEL_8822B << BIT_SHIFT_DBG_SEL_8822B)
+#define BIT_CLEAR_DBG_SEL_8822B(x) ((x) & (~BITS_DBG_SEL_8822B))
+#define BIT_GET_DBG_SEL_8822B(x)                                               \
+	(((x) >> BIT_SHIFT_DBG_SEL_8822B) & BIT_MASK_DBG_SEL_8822B)
+#define BIT_SET_DBG_SEL_8822B(x, v)                                            \
+	(BIT_CLEAR_DBG_SEL_8822B(x) | BIT_DBG_SEL_8822B(v))
+
+/* 2 REG_PCIE_HRPWM1_V1_8822B */
+
+#define BIT_SHIFT_PCIE_HRPWM_8822B 0
+#define BIT_MASK_PCIE_HRPWM_8822B 0xff
+#define BIT_PCIE_HRPWM_8822B(x)                                                \
+	(((x) & BIT_MASK_PCIE_HRPWM_8822B) << BIT_SHIFT_PCIE_HRPWM_8822B)
+#define BITS_PCIE_HRPWM_8822B                                                  \
+	(BIT_MASK_PCIE_HRPWM_8822B << BIT_SHIFT_PCIE_HRPWM_8822B)
+#define BIT_CLEAR_PCIE_HRPWM_8822B(x) ((x) & (~BITS_PCIE_HRPWM_8822B))
+#define BIT_GET_PCIE_HRPWM_8822B(x)                                            \
+	(((x) >> BIT_SHIFT_PCIE_HRPWM_8822B) & BIT_MASK_PCIE_HRPWM_8822B)
+#define BIT_SET_PCIE_HRPWM_8822B(x, v)                                         \
+	(BIT_CLEAR_PCIE_HRPWM_8822B(x) | BIT_PCIE_HRPWM_8822B(v))
+
+/* 2 REG_PCIE_HCPWM1_V1_8822B */
+
+#define BIT_SHIFT_PCIE_HCPWM_8822B 0
+#define BIT_MASK_PCIE_HCPWM_8822B 0xff
+#define BIT_PCIE_HCPWM_8822B(x)                                                \
+	(((x) & BIT_MASK_PCIE_HCPWM_8822B) << BIT_SHIFT_PCIE_HCPWM_8822B)
+#define BITS_PCIE_HCPWM_8822B                                                  \
+	(BIT_MASK_PCIE_HCPWM_8822B << BIT_SHIFT_PCIE_HCPWM_8822B)
+#define BIT_CLEAR_PCIE_HCPWM_8822B(x) ((x) & (~BITS_PCIE_HCPWM_8822B))
+#define BIT_GET_PCIE_HCPWM_8822B(x)                                            \
+	(((x) >> BIT_SHIFT_PCIE_HCPWM_8822B) & BIT_MASK_PCIE_HCPWM_8822B)
+#define BIT_SET_PCIE_HCPWM_8822B(x, v)                                         \
+	(BIT_CLEAR_PCIE_HCPWM_8822B(x) | BIT_PCIE_HCPWM_8822B(v))
+
+/* 2 REG_PCIE_CTRL2_8822B */
+#define BIT_DIS_TXDMA_PRE_8822B BIT(7)
+#define BIT_DIS_RXDMA_PRE_8822B BIT(6)
+
+#define BIT_SHIFT_HPS_CLKR_PCIE_8822B 4
+#define BIT_MASK_HPS_CLKR_PCIE_8822B 0x3
+#define BIT_HPS_CLKR_PCIE_8822B(x)                                             \
+	(((x) & BIT_MASK_HPS_CLKR_PCIE_8822B) << BIT_SHIFT_HPS_CLKR_PCIE_8822B)
+#define BITS_HPS_CLKR_PCIE_8822B                                               \
+	(BIT_MASK_HPS_CLKR_PCIE_8822B << BIT_SHIFT_HPS_CLKR_PCIE_8822B)
+#define BIT_CLEAR_HPS_CLKR_PCIE_8822B(x) ((x) & (~BITS_HPS_CLKR_PCIE_8822B))
+#define BIT_GET_HPS_CLKR_PCIE_8822B(x)                                         \
+	(((x) >> BIT_SHIFT_HPS_CLKR_PCIE_8822B) & BIT_MASK_HPS_CLKR_PCIE_8822B)
+#define BIT_SET_HPS_CLKR_PCIE_8822B(x, v)                                      \
+	(BIT_CLEAR_HPS_CLKR_PCIE_8822B(x) | BIT_HPS_CLKR_PCIE_8822B(v))
+
+#define BIT_PCIE_INT_8822B BIT(3)
+#define BIT_TXFLAG_EXIT_L1_EN_8822B BIT(2)
+#define BIT_EN_RXDMA_ALIGN_8822B BIT(1)
+#define BIT_EN_TXDMA_ALIGN_8822B BIT(0)
+
+/* 2 REG_PCIE_HRPWM2_V1_8822B */
+
+#define BIT_SHIFT_PCIE_HRPWM2_8822B 0
+#define BIT_MASK_PCIE_HRPWM2_8822B 0xffff
+#define BIT_PCIE_HRPWM2_8822B(x)                                               \
+	(((x) & BIT_MASK_PCIE_HRPWM2_8822B) << BIT_SHIFT_PCIE_HRPWM2_8822B)
+#define BITS_PCIE_HRPWM2_8822B                                                 \
+	(BIT_MASK_PCIE_HRPWM2_8822B << BIT_SHIFT_PCIE_HRPWM2_8822B)
+#define BIT_CLEAR_PCIE_HRPWM2_8822B(x) ((x) & (~BITS_PCIE_HRPWM2_8822B))
+#define BIT_GET_PCIE_HRPWM2_8822B(x)                                           \
+	(((x) >> BIT_SHIFT_PCIE_HRPWM2_8822B) & BIT_MASK_PCIE_HRPWM2_8822B)
+#define BIT_SET_PCIE_HRPWM2_8822B(x, v)                                        \
+	(BIT_CLEAR_PCIE_HRPWM2_8822B(x) | BIT_PCIE_HRPWM2_8822B(v))
+
+/* 2 REG_PCIE_HCPWM2_V1_8822B */
+
+#define BIT_SHIFT_PCIE_HCPWM2_8822B 0
+#define BIT_MASK_PCIE_HCPWM2_8822B 0xffff
+#define BIT_PCIE_HCPWM2_8822B(x)                                               \
+	(((x) & BIT_MASK_PCIE_HCPWM2_8822B) << BIT_SHIFT_PCIE_HCPWM2_8822B)
+#define BITS_PCIE_HCPWM2_8822B                                                 \
+	(BIT_MASK_PCIE_HCPWM2_8822B << BIT_SHIFT_PCIE_HCPWM2_8822B)
+#define BIT_CLEAR_PCIE_HCPWM2_8822B(x) ((x) & (~BITS_PCIE_HCPWM2_8822B))
+#define BIT_GET_PCIE_HCPWM2_8822B(x)                                           \
+	(((x) >> BIT_SHIFT_PCIE_HCPWM2_8822B) & BIT_MASK_PCIE_HCPWM2_8822B)
+#define BIT_SET_PCIE_HCPWM2_8822B(x, v)                                        \
+	(BIT_CLEAR_PCIE_HCPWM2_8822B(x) | BIT_PCIE_HCPWM2_8822B(v))
+
+/* 2 REG_PCIE_H2C_MSG_V1_8822B */
+
+#define BIT_SHIFT_DRV2FW_INFO_8822B 0
+#define BIT_MASK_DRV2FW_INFO_8822B 0xffffffffL
+#define BIT_DRV2FW_INFO_8822B(x)                                               \
+	(((x) & BIT_MASK_DRV2FW_INFO_8822B) << BIT_SHIFT_DRV2FW_INFO_8822B)
+#define BITS_DRV2FW_INFO_8822B                                                 \
+	(BIT_MASK_DRV2FW_INFO_8822B << BIT_SHIFT_DRV2FW_INFO_8822B)
+#define BIT_CLEAR_DRV2FW_INFO_8822B(x) ((x) & (~BITS_DRV2FW_INFO_8822B))
+#define BIT_GET_DRV2FW_INFO_8822B(x)                                           \
+	(((x) >> BIT_SHIFT_DRV2FW_INFO_8822B) & BIT_MASK_DRV2FW_INFO_8822B)
+#define BIT_SET_DRV2FW_INFO_8822B(x, v)                                        \
+	(BIT_CLEAR_DRV2FW_INFO_8822B(x) | BIT_DRV2FW_INFO_8822B(v))
+
+/* 2 REG_PCIE_C2H_MSG_V1_8822B */
+
+#define BIT_SHIFT_HCI_PCIE_C2H_MSG_8822B 0
+#define BIT_MASK_HCI_PCIE_C2H_MSG_8822B 0xffffffffL
+#define BIT_HCI_PCIE_C2H_MSG_8822B(x)                                          \
+	(((x) & BIT_MASK_HCI_PCIE_C2H_MSG_8822B)                               \
+	 << BIT_SHIFT_HCI_PCIE_C2H_MSG_8822B)
+#define BITS_HCI_PCIE_C2H_MSG_8822B                                            \
+	(BIT_MASK_HCI_PCIE_C2H_MSG_8822B << BIT_SHIFT_HCI_PCIE_C2H_MSG_8822B)
+#define BIT_CLEAR_HCI_PCIE_C2H_MSG_8822B(x)                                    \
+	((x) & (~BITS_HCI_PCIE_C2H_MSG_8822B))
+#define BIT_GET_HCI_PCIE_C2H_MSG_8822B(x)                                      \
+	(((x) >> BIT_SHIFT_HCI_PCIE_C2H_MSG_8822B) &                           \
+	 BIT_MASK_HCI_PCIE_C2H_MSG_8822B)
+#define BIT_SET_HCI_PCIE_C2H_MSG_8822B(x, v)                                   \
+	(BIT_CLEAR_HCI_PCIE_C2H_MSG_8822B(x) | BIT_HCI_PCIE_C2H_MSG_8822B(v))
+
+/* 2 REG_DBI_WDATA_V1_8822B */
+
+#define BIT_SHIFT_DBI_WDATA_8822B 0
+#define BIT_MASK_DBI_WDATA_8822B 0xffffffffL
+#define BIT_DBI_WDATA_8822B(x)                                                 \
+	(((x) & BIT_MASK_DBI_WDATA_8822B) << BIT_SHIFT_DBI_WDATA_8822B)
+#define BITS_DBI_WDATA_8822B                                                   \
+	(BIT_MASK_DBI_WDATA_8822B << BIT_SHIFT_DBI_WDATA_8822B)
+#define BIT_CLEAR_DBI_WDATA_8822B(x) ((x) & (~BITS_DBI_WDATA_8822B))
+#define BIT_GET_DBI_WDATA_8822B(x)                                             \
+	(((x) >> BIT_SHIFT_DBI_WDATA_8822B) & BIT_MASK_DBI_WDATA_8822B)
+#define BIT_SET_DBI_WDATA_8822B(x, v)                                          \
+	(BIT_CLEAR_DBI_WDATA_8822B(x) | BIT_DBI_WDATA_8822B(v))
+
+/* 2 REG_DBI_RDATA_V1_8822B */
+
+#define BIT_SHIFT_DBI_RDATA_8822B 0
+#define BIT_MASK_DBI_RDATA_8822B 0xffffffffL
+#define BIT_DBI_RDATA_8822B(x)                                                 \
+	(((x) & BIT_MASK_DBI_RDATA_8822B) << BIT_SHIFT_DBI_RDATA_8822B)
+#define BITS_DBI_RDATA_8822B                                                   \
+	(BIT_MASK_DBI_RDATA_8822B << BIT_SHIFT_DBI_RDATA_8822B)
+#define BIT_CLEAR_DBI_RDATA_8822B(x) ((x) & (~BITS_DBI_RDATA_8822B))
+#define BIT_GET_DBI_RDATA_8822B(x)                                             \
+	(((x) >> BIT_SHIFT_DBI_RDATA_8822B) & BIT_MASK_DBI_RDATA_8822B)
+#define BIT_SET_DBI_RDATA_8822B(x, v)                                          \
+	(BIT_CLEAR_DBI_RDATA_8822B(x) | BIT_DBI_RDATA_8822B(v))
+
+/* 2 REG_DBI_FLAG_V1_8822B */
+#define BIT_EN_STUCK_DBG_8822B BIT(26)
+#define BIT_RX_STUCK_8822B BIT(25)
+#define BIT_TX_STUCK_8822B BIT(24)
+#define BIT_DBI_RFLAG_8822B BIT(17)
+#define BIT_DBI_WFLAG_8822B BIT(16)
+
+#define BIT_SHIFT_DBI_WREN_8822B 12
+#define BIT_MASK_DBI_WREN_8822B 0xf
+#define BIT_DBI_WREN_8822B(x)                                                  \
+	(((x) & BIT_MASK_DBI_WREN_8822B) << BIT_SHIFT_DBI_WREN_8822B)
+#define BITS_DBI_WREN_8822B                                                    \
+	(BIT_MASK_DBI_WREN_8822B << BIT_SHIFT_DBI_WREN_8822B)
+#define BIT_CLEAR_DBI_WREN_8822B(x) ((x) & (~BITS_DBI_WREN_8822B))
+#define BIT_GET_DBI_WREN_8822B(x)                                              \
+	(((x) >> BIT_SHIFT_DBI_WREN_8822B) & BIT_MASK_DBI_WREN_8822B)
+#define BIT_SET_DBI_WREN_8822B(x, v)                                           \
+	(BIT_CLEAR_DBI_WREN_8822B(x) | BIT_DBI_WREN_8822B(v))
+
+#define BIT_SHIFT_DBI_ADDR_8822B 0
+#define BIT_MASK_DBI_ADDR_8822B 0xfff
+#define BIT_DBI_ADDR_8822B(x)                                                  \
+	(((x) & BIT_MASK_DBI_ADDR_8822B) << BIT_SHIFT_DBI_ADDR_8822B)
+#define BITS_DBI_ADDR_8822B                                                    \
+	(BIT_MASK_DBI_ADDR_8822B << BIT_SHIFT_DBI_ADDR_8822B)
+#define BIT_CLEAR_DBI_ADDR_8822B(x) ((x) & (~BITS_DBI_ADDR_8822B))
+#define BIT_GET_DBI_ADDR_8822B(x)                                              \
+	(((x) >> BIT_SHIFT_DBI_ADDR_8822B) & BIT_MASK_DBI_ADDR_8822B)
+#define BIT_SET_DBI_ADDR_8822B(x, v)                                           \
+	(BIT_CLEAR_DBI_ADDR_8822B(x) | BIT_DBI_ADDR_8822B(v))
+
+/* 2 REG_MDIO_V1_8822B */
+
+#define BIT_SHIFT_MDIO_RDATA_8822B 16
+#define BIT_MASK_MDIO_RDATA_8822B 0xffff
+#define BIT_MDIO_RDATA_8822B(x)                                                \
+	(((x) & BIT_MASK_MDIO_RDATA_8822B) << BIT_SHIFT_MDIO_RDATA_8822B)
+#define BITS_MDIO_RDATA_8822B                                                  \
+	(BIT_MASK_MDIO_RDATA_8822B << BIT_SHIFT_MDIO_RDATA_8822B)
+#define BIT_CLEAR_MDIO_RDATA_8822B(x) ((x) & (~BITS_MDIO_RDATA_8822B))
+#define BIT_GET_MDIO_RDATA_8822B(x)                                            \
+	(((x) >> BIT_SHIFT_MDIO_RDATA_8822B) & BIT_MASK_MDIO_RDATA_8822B)
+#define BIT_SET_MDIO_RDATA_8822B(x, v)                                         \
+	(BIT_CLEAR_MDIO_RDATA_8822B(x) | BIT_MDIO_RDATA_8822B(v))
+
+#define BIT_SHIFT_MDIO_WDATA_8822B 0
+#define BIT_MASK_MDIO_WDATA_8822B 0xffff
+#define BIT_MDIO_WDATA_8822B(x)                                                \
+	(((x) & BIT_MASK_MDIO_WDATA_8822B) << BIT_SHIFT_MDIO_WDATA_8822B)
+#define BITS_MDIO_WDATA_8822B                                                  \
+	(BIT_MASK_MDIO_WDATA_8822B << BIT_SHIFT_MDIO_WDATA_8822B)
+#define BIT_CLEAR_MDIO_WDATA_8822B(x) ((x) & (~BITS_MDIO_WDATA_8822B))
+#define BIT_GET_MDIO_WDATA_8822B(x)                                            \
+	(((x) >> BIT_SHIFT_MDIO_WDATA_8822B) & BIT_MASK_MDIO_WDATA_8822B)
+#define BIT_SET_MDIO_WDATA_8822B(x, v)                                         \
+	(BIT_CLEAR_MDIO_WDATA_8822B(x) | BIT_MDIO_WDATA_8822B(v))
+
+/* 2 REG_PCIE_MIX_CFG_8822B */
+
+#define BIT_SHIFT_MDIO_PHY_ADDR_8822B 24
+#define BIT_MASK_MDIO_PHY_ADDR_8822B 0x1f
+#define BIT_MDIO_PHY_ADDR_8822B(x)                                             \
+	(((x) & BIT_MASK_MDIO_PHY_ADDR_8822B) << BIT_SHIFT_MDIO_PHY_ADDR_8822B)
+#define BITS_MDIO_PHY_ADDR_8822B                                               \
+	(BIT_MASK_MDIO_PHY_ADDR_8822B << BIT_SHIFT_MDIO_PHY_ADDR_8822B)
+#define BIT_CLEAR_MDIO_PHY_ADDR_8822B(x) ((x) & (~BITS_MDIO_PHY_ADDR_8822B))
+#define BIT_GET_MDIO_PHY_ADDR_8822B(x)                                         \
+	(((x) >> BIT_SHIFT_MDIO_PHY_ADDR_8822B) & BIT_MASK_MDIO_PHY_ADDR_8822B)
+#define BIT_SET_MDIO_PHY_ADDR_8822B(x, v)                                      \
+	(BIT_CLEAR_MDIO_PHY_ADDR_8822B(x) | BIT_MDIO_PHY_ADDR_8822B(v))
+
+#define BIT_SHIFT_WATCH_DOG_RECORD_V1_8822B 10
+#define BIT_MASK_WATCH_DOG_RECORD_V1_8822B 0x3fff
+#define BIT_WATCH_DOG_RECORD_V1_8822B(x)                                       \
+	(((x) & BIT_MASK_WATCH_DOG_RECORD_V1_8822B)                            \
+	 << BIT_SHIFT_WATCH_DOG_RECORD_V1_8822B)
+#define BITS_WATCH_DOG_RECORD_V1_8822B                                         \
+	(BIT_MASK_WATCH_DOG_RECORD_V1_8822B                                    \
+	 << BIT_SHIFT_WATCH_DOG_RECORD_V1_8822B)
+#define BIT_CLEAR_WATCH_DOG_RECORD_V1_8822B(x)                                 \
+	((x) & (~BITS_WATCH_DOG_RECORD_V1_8822B))
+#define BIT_GET_WATCH_DOG_RECORD_V1_8822B(x)                                   \
+	(((x) >> BIT_SHIFT_WATCH_DOG_RECORD_V1_8822B) &                        \
+	 BIT_MASK_WATCH_DOG_RECORD_V1_8822B)
+#define BIT_SET_WATCH_DOG_RECORD_V1_8822B(x, v)                                \
+	(BIT_CLEAR_WATCH_DOG_RECORD_V1_8822B(x) |                              \
+	 BIT_WATCH_DOG_RECORD_V1_8822B(v))
+
+#define BIT_R_IO_TIMEOUT_FLAG_V1_8822B BIT(9)
+#define BIT_EN_WATCH_DOG_8822B BIT(8)
+#define BIT_ECRC_EN_V1_8822B BIT(7)
+#define BIT_MDIO_RFLAG_V1_8822B BIT(6)
+#define BIT_MDIO_WFLAG_V1_8822B BIT(5)
+
+#define BIT_SHIFT_MDIO_REG_ADDR_V1_8822B 0
+#define BIT_MASK_MDIO_REG_ADDR_V1_8822B 0x1f
+#define BIT_MDIO_REG_ADDR_V1_8822B(x)                                          \
+	(((x) & BIT_MASK_MDIO_REG_ADDR_V1_8822B)                               \
+	 << BIT_SHIFT_MDIO_REG_ADDR_V1_8822B)
+#define BITS_MDIO_REG_ADDR_V1_8822B                                            \
+	(BIT_MASK_MDIO_REG_ADDR_V1_8822B << BIT_SHIFT_MDIO_REG_ADDR_V1_8822B)
+#define BIT_CLEAR_MDIO_REG_ADDR_V1_8822B(x)                                    \
+	((x) & (~BITS_MDIO_REG_ADDR_V1_8822B))
+#define BIT_GET_MDIO_REG_ADDR_V1_8822B(x)                                      \
+	(((x) >> BIT_SHIFT_MDIO_REG_ADDR_V1_8822B) &                           \
+	 BIT_MASK_MDIO_REG_ADDR_V1_8822B)
+#define BIT_SET_MDIO_REG_ADDR_V1_8822B(x, v)                                   \
+	(BIT_CLEAR_MDIO_REG_ADDR_V1_8822B(x) | BIT_MDIO_REG_ADDR_V1_8822B(v))
+
+/* 2 REG_HCI_MIX_CFG_8822B */
+#define BIT_HOST_GEN2_SUPPORT_8822B BIT(20)
+
+#define BIT_SHIFT_TXDMA_ERR_FLAG_8822B 16
+#define BIT_MASK_TXDMA_ERR_FLAG_8822B 0xf
+#define BIT_TXDMA_ERR_FLAG_8822B(x)                                            \
+	(((x) & BIT_MASK_TXDMA_ERR_FLAG_8822B)                                 \
+	 << BIT_SHIFT_TXDMA_ERR_FLAG_8822B)
+#define BITS_TXDMA_ERR_FLAG_8822B                                              \
+	(BIT_MASK_TXDMA_ERR_FLAG_8822B << BIT_SHIFT_TXDMA_ERR_FLAG_8822B)
+#define BIT_CLEAR_TXDMA_ERR_FLAG_8822B(x) ((x) & (~BITS_TXDMA_ERR_FLAG_8822B))
+#define BIT_GET_TXDMA_ERR_FLAG_8822B(x)                                        \
+	(((x) >> BIT_SHIFT_TXDMA_ERR_FLAG_8822B) &                             \
+	 BIT_MASK_TXDMA_ERR_FLAG_8822B)
+#define BIT_SET_TXDMA_ERR_FLAG_8822B(x, v)                                     \
+	(BIT_CLEAR_TXDMA_ERR_FLAG_8822B(x) | BIT_TXDMA_ERR_FLAG_8822B(v))
+
+#define BIT_SHIFT_EARLY_MODE_SEL_8822B 12
+#define BIT_MASK_EARLY_MODE_SEL_8822B 0xf
+#define BIT_EARLY_MODE_SEL_8822B(x)                                            \
+	(((x) & BIT_MASK_EARLY_MODE_SEL_8822B)                                 \
+	 << BIT_SHIFT_EARLY_MODE_SEL_8822B)
+#define BITS_EARLY_MODE_SEL_8822B                                              \
+	(BIT_MASK_EARLY_MODE_SEL_8822B << BIT_SHIFT_EARLY_MODE_SEL_8822B)
+#define BIT_CLEAR_EARLY_MODE_SEL_8822B(x) ((x) & (~BITS_EARLY_MODE_SEL_8822B))
+#define BIT_GET_EARLY_MODE_SEL_8822B(x)                                        \
+	(((x) >> BIT_SHIFT_EARLY_MODE_SEL_8822B) &                             \
+	 BIT_MASK_EARLY_MODE_SEL_8822B)
+#define BIT_SET_EARLY_MODE_SEL_8822B(x, v)                                     \
+	(BIT_CLEAR_EARLY_MODE_SEL_8822B(x) | BIT_EARLY_MODE_SEL_8822B(v))
+
+#define BIT_EPHY_RX50_EN_8822B BIT(11)
+
+#define BIT_SHIFT_MSI_TIMEOUT_ID_V1_8822B 8
+#define BIT_MASK_MSI_TIMEOUT_ID_V1_8822B 0x7
+#define BIT_MSI_TIMEOUT_ID_V1_8822B(x)                                         \
+	(((x) & BIT_MASK_MSI_TIMEOUT_ID_V1_8822B)                              \
+	 << BIT_SHIFT_MSI_TIMEOUT_ID_V1_8822B)
+#define BITS_MSI_TIMEOUT_ID_V1_8822B                                           \
+	(BIT_MASK_MSI_TIMEOUT_ID_V1_8822B << BIT_SHIFT_MSI_TIMEOUT_ID_V1_8822B)
+#define BIT_CLEAR_MSI_TIMEOUT_ID_V1_8822B(x)                                   \
+	((x) & (~BITS_MSI_TIMEOUT_ID_V1_8822B))
+#define BIT_GET_MSI_TIMEOUT_ID_V1_8822B(x)                                     \
+	(((x) >> BIT_SHIFT_MSI_TIMEOUT_ID_V1_8822B) &                          \
+	 BIT_MASK_MSI_TIMEOUT_ID_V1_8822B)
+#define BIT_SET_MSI_TIMEOUT_ID_V1_8822B(x, v)                                  \
+	(BIT_CLEAR_MSI_TIMEOUT_ID_V1_8822B(x) | BIT_MSI_TIMEOUT_ID_V1_8822B(v))
+
+#define BIT_RADDR_RD_8822B BIT(7)
+#define BIT_EN_MUL_TAG_8822B BIT(6)
+#define BIT_EN_EARLY_MODE_8822B BIT(5)
+#define BIT_L0S_LINK_OFF_8822B BIT(4)
+#define BIT_ACT_LINK_OFF_8822B BIT(3)
+#define BIT_EN_SLOW_MAC_TX_8822B BIT(2)
+#define BIT_EN_SLOW_MAC_RX_8822B BIT(1)
+
+/* 2 REG_STC_INT_CS_8822B(PCIE STATE CHANGE INTERRUPT CONTROL AND STATUS) */
+#define BIT_STC_INT_EN_8822B BIT(31)
+
+#define BIT_SHIFT_STC_INT_FLAG_8822B 16
+#define BIT_MASK_STC_INT_FLAG_8822B 0xff
+#define BIT_STC_INT_FLAG_8822B(x)                                              \
+	(((x) & BIT_MASK_STC_INT_FLAG_8822B) << BIT_SHIFT_STC_INT_FLAG_8822B)
+#define BITS_STC_INT_FLAG_8822B                                                \
+	(BIT_MASK_STC_INT_FLAG_8822B << BIT_SHIFT_STC_INT_FLAG_8822B)
+#define BIT_CLEAR_STC_INT_FLAG_8822B(x) ((x) & (~BITS_STC_INT_FLAG_8822B))
+#define BIT_GET_STC_INT_FLAG_8822B(x)                                          \
+	(((x) >> BIT_SHIFT_STC_INT_FLAG_8822B) & BIT_MASK_STC_INT_FLAG_8822B)
+#define BIT_SET_STC_INT_FLAG_8822B(x, v)                                       \
+	(BIT_CLEAR_STC_INT_FLAG_8822B(x) | BIT_STC_INT_FLAG_8822B(v))
+
+#define BIT_SHIFT_STC_INT_IDX_8822B 8
+#define BIT_MASK_STC_INT_IDX_8822B 0x7
+#define BIT_STC_INT_IDX_8822B(x)                                               \
+	(((x) & BIT_MASK_STC_INT_IDX_8822B) << BIT_SHIFT_STC_INT_IDX_8822B)
+#define BITS_STC_INT_IDX_8822B                                                 \
+	(BIT_MASK_STC_INT_IDX_8822B << BIT_SHIFT_STC_INT_IDX_8822B)
+#define BIT_CLEAR_STC_INT_IDX_8822B(x) ((x) & (~BITS_STC_INT_IDX_8822B))
+#define BIT_GET_STC_INT_IDX_8822B(x)                                           \
+	(((x) >> BIT_SHIFT_STC_INT_IDX_8822B) & BIT_MASK_STC_INT_IDX_8822B)
+#define BIT_SET_STC_INT_IDX_8822B(x, v)                                        \
+	(BIT_CLEAR_STC_INT_IDX_8822B(x) | BIT_STC_INT_IDX_8822B(v))
+
+#define BIT_SHIFT_STC_INT_REALTIME_CS_8822B 0
+#define BIT_MASK_STC_INT_REALTIME_CS_8822B 0x3f
+#define BIT_STC_INT_REALTIME_CS_8822B(x)                                       \
+	(((x) & BIT_MASK_STC_INT_REALTIME_CS_8822B)                            \
+	 << BIT_SHIFT_STC_INT_REALTIME_CS_8822B)
+#define BITS_STC_INT_REALTIME_CS_8822B                                         \
+	(BIT_MASK_STC_INT_REALTIME_CS_8822B                                    \
+	 << BIT_SHIFT_STC_INT_REALTIME_CS_8822B)
+#define BIT_CLEAR_STC_INT_REALTIME_CS_8822B(x)                                 \
+	((x) & (~BITS_STC_INT_REALTIME_CS_8822B))
+#define BIT_GET_STC_INT_REALTIME_CS_8822B(x)                                   \
+	(((x) >> BIT_SHIFT_STC_INT_REALTIME_CS_8822B) &                        \
+	 BIT_MASK_STC_INT_REALTIME_CS_8822B)
+#define BIT_SET_STC_INT_REALTIME_CS_8822B(x, v)                                \
+	(BIT_CLEAR_STC_INT_REALTIME_CS_8822B(x) |                              \
+	 BIT_STC_INT_REALTIME_CS_8822B(v))
+
+/* 2 REG_ST_INT_CFG_8822B(PCIE STATE CHANGE INTERRUPT CONFIGURATION) */
+#define BIT_STC_INT_GRP_EN_8822B BIT(31)
+
+#define BIT_SHIFT_STC_INT_EXPECT_LS_8822B 8
+#define BIT_MASK_STC_INT_EXPECT_LS_8822B 0x3f
+#define BIT_STC_INT_EXPECT_LS_8822B(x)                                         \
+	(((x) & BIT_MASK_STC_INT_EXPECT_LS_8822B)                              \
+	 << BIT_SHIFT_STC_INT_EXPECT_LS_8822B)
+#define BITS_STC_INT_EXPECT_LS_8822B                                           \
+	(BIT_MASK_STC_INT_EXPECT_LS_8822B << BIT_SHIFT_STC_INT_EXPECT_LS_8822B)
+#define BIT_CLEAR_STC_INT_EXPECT_LS_8822B(x)                                   \
+	((x) & (~BITS_STC_INT_EXPECT_LS_8822B))
+#define BIT_GET_STC_INT_EXPECT_LS_8822B(x)                                     \
+	(((x) >> BIT_SHIFT_STC_INT_EXPECT_LS_8822B) &                          \
+	 BIT_MASK_STC_INT_EXPECT_LS_8822B)
+#define BIT_SET_STC_INT_EXPECT_LS_8822B(x, v)                                  \
+	(BIT_CLEAR_STC_INT_EXPECT_LS_8822B(x) | BIT_STC_INT_EXPECT_LS_8822B(v))
+
+#define BIT_SHIFT_STC_INT_EXPECT_CS_8822B 0
+#define BIT_MASK_STC_INT_EXPECT_CS_8822B 0x3f
+#define BIT_STC_INT_EXPECT_CS_8822B(x)                                         \
+	(((x) & BIT_MASK_STC_INT_EXPECT_CS_8822B)                              \
+	 << BIT_SHIFT_STC_INT_EXPECT_CS_8822B)
+#define BITS_STC_INT_EXPECT_CS_8822B                                           \
+	(BIT_MASK_STC_INT_EXPECT_CS_8822B << BIT_SHIFT_STC_INT_EXPECT_CS_8822B)
+#define BIT_CLEAR_STC_INT_EXPECT_CS_8822B(x)                                   \
+	((x) & (~BITS_STC_INT_EXPECT_CS_8822B))
+#define BIT_GET_STC_INT_EXPECT_CS_8822B(x)                                     \
+	(((x) >> BIT_SHIFT_STC_INT_EXPECT_CS_8822B) &                          \
+	 BIT_MASK_STC_INT_EXPECT_CS_8822B)
+#define BIT_SET_STC_INT_EXPECT_CS_8822B(x, v)                                  \
+	(BIT_CLEAR_STC_INT_EXPECT_CS_8822B(x) | BIT_STC_INT_EXPECT_CS_8822B(v))
+
+/* 2 REG_CMU_DLY_CTRL_8822B(PCIE PHY CLOCK MGT UNIT DELAY CONTROL ) */
+#define BIT_CMU_DLY_EN_8822B BIT(31)
+#define BIT_CMU_DLY_MODE_8822B BIT(30)
+
+#define BIT_SHIFT_CMU_DLY_PRE_DIV_8822B 0
+#define BIT_MASK_CMU_DLY_PRE_DIV_8822B 0xff
+#define BIT_CMU_DLY_PRE_DIV_8822B(x)                                           \
+	(((x) & BIT_MASK_CMU_DLY_PRE_DIV_8822B)                                \
+	 << BIT_SHIFT_CMU_DLY_PRE_DIV_8822B)
+#define BITS_CMU_DLY_PRE_DIV_8822B                                             \
+	(BIT_MASK_CMU_DLY_PRE_DIV_8822B << BIT_SHIFT_CMU_DLY_PRE_DIV_8822B)
+#define BIT_CLEAR_CMU_DLY_PRE_DIV_8822B(x) ((x) & (~BITS_CMU_DLY_PRE_DIV_8822B))
+#define BIT_GET_CMU_DLY_PRE_DIV_8822B(x)                                       \
+	(((x) >> BIT_SHIFT_CMU_DLY_PRE_DIV_8822B) &                            \
+	 BIT_MASK_CMU_DLY_PRE_DIV_8822B)
+#define BIT_SET_CMU_DLY_PRE_DIV_8822B(x, v)                                    \
+	(BIT_CLEAR_CMU_DLY_PRE_DIV_8822B(x) | BIT_CMU_DLY_PRE_DIV_8822B(v))
+
+/* 2 REG_CMU_DLY_CFG_8822B(PCIE PHY CLOCK MGT UNIT DELAY CONFIGURATION ) */
+
+#define BIT_SHIFT_CMU_DLY_LTR_A2I_8822B 24
+#define BIT_MASK_CMU_DLY_LTR_A2I_8822B 0xff
+#define BIT_CMU_DLY_LTR_A2I_8822B(x)                                           \
+	(((x) & BIT_MASK_CMU_DLY_LTR_A2I_8822B)                                \
+	 << BIT_SHIFT_CMU_DLY_LTR_A2I_8822B)
+#define BITS_CMU_DLY_LTR_A2I_8822B                                             \
+	(BIT_MASK_CMU_DLY_LTR_A2I_8822B << BIT_SHIFT_CMU_DLY_LTR_A2I_8822B)
+#define BIT_CLEAR_CMU_DLY_LTR_A2I_8822B(x) ((x) & (~BITS_CMU_DLY_LTR_A2I_8822B))
+#define BIT_GET_CMU_DLY_LTR_A2I_8822B(x)                                       \
+	(((x) >> BIT_SHIFT_CMU_DLY_LTR_A2I_8822B) &                            \
+	 BIT_MASK_CMU_DLY_LTR_A2I_8822B)
+#define BIT_SET_CMU_DLY_LTR_A2I_8822B(x, v)                                    \
+	(BIT_CLEAR_CMU_DLY_LTR_A2I_8822B(x) | BIT_CMU_DLY_LTR_A2I_8822B(v))
+
+#define BIT_SHIFT_CMU_DLY_LTR_I2A_8822B 16
+#define BIT_MASK_CMU_DLY_LTR_I2A_8822B 0xff
+#define BIT_CMU_DLY_LTR_I2A_8822B(x)                                           \
+	(((x) & BIT_MASK_CMU_DLY_LTR_I2A_8822B)                                \
+	 << BIT_SHIFT_CMU_DLY_LTR_I2A_8822B)
+#define BITS_CMU_DLY_LTR_I2A_8822B                                             \
+	(BIT_MASK_CMU_DLY_LTR_I2A_8822B << BIT_SHIFT_CMU_DLY_LTR_I2A_8822B)
+#define BIT_CLEAR_CMU_DLY_LTR_I2A_8822B(x) ((x) & (~BITS_CMU_DLY_LTR_I2A_8822B))
+#define BIT_GET_CMU_DLY_LTR_I2A_8822B(x)                                       \
+	(((x) >> BIT_SHIFT_CMU_DLY_LTR_I2A_8822B) &                            \
+	 BIT_MASK_CMU_DLY_LTR_I2A_8822B)
+#define BIT_SET_CMU_DLY_LTR_I2A_8822B(x, v)                                    \
+	(BIT_CLEAR_CMU_DLY_LTR_I2A_8822B(x) | BIT_CMU_DLY_LTR_I2A_8822B(v))
+
+#define BIT_SHIFT_CMU_DLY_LTR_IDLE_8822B 8
+#define BIT_MASK_CMU_DLY_LTR_IDLE_8822B 0xff
+#define BIT_CMU_DLY_LTR_IDLE_8822B(x)                                          \
+	(((x) & BIT_MASK_CMU_DLY_LTR_IDLE_8822B)                               \
+	 << BIT_SHIFT_CMU_DLY_LTR_IDLE_8822B)
+#define BITS_CMU_DLY_LTR_IDLE_8822B                                            \
+	(BIT_MASK_CMU_DLY_LTR_IDLE_8822B << BIT_SHIFT_CMU_DLY_LTR_IDLE_8822B)
+#define BIT_CLEAR_CMU_DLY_LTR_IDLE_8822B(x)                                    \
+	((x) & (~BITS_CMU_DLY_LTR_IDLE_8822B))
+#define BIT_GET_CMU_DLY_LTR_IDLE_8822B(x)                                      \
+	(((x) >> BIT_SHIFT_CMU_DLY_LTR_IDLE_8822B) &                           \
+	 BIT_MASK_CMU_DLY_LTR_IDLE_8822B)
+#define BIT_SET_CMU_DLY_LTR_IDLE_8822B(x, v)                                   \
+	(BIT_CLEAR_CMU_DLY_LTR_IDLE_8822B(x) | BIT_CMU_DLY_LTR_IDLE_8822B(v))
+
+#define BIT_SHIFT_CMU_DLY_LTR_ACT_8822B 0
+#define BIT_MASK_CMU_DLY_LTR_ACT_8822B 0xff
+#define BIT_CMU_DLY_LTR_ACT_8822B(x)                                           \
+	(((x) & BIT_MASK_CMU_DLY_LTR_ACT_8822B)                                \
+	 << BIT_SHIFT_CMU_DLY_LTR_ACT_8822B)
+#define BITS_CMU_DLY_LTR_ACT_8822B                                             \
+	(BIT_MASK_CMU_DLY_LTR_ACT_8822B << BIT_SHIFT_CMU_DLY_LTR_ACT_8822B)
+#define BIT_CLEAR_CMU_DLY_LTR_ACT_8822B(x) ((x) & (~BITS_CMU_DLY_LTR_ACT_8822B))
+#define BIT_GET_CMU_DLY_LTR_ACT_8822B(x)                                       \
+	(((x) >> BIT_SHIFT_CMU_DLY_LTR_ACT_8822B) &                            \
+	 BIT_MASK_CMU_DLY_LTR_ACT_8822B)
+#define BIT_SET_CMU_DLY_LTR_ACT_8822B(x, v)                                    \
+	(BIT_CLEAR_CMU_DLY_LTR_ACT_8822B(x) | BIT_CMU_DLY_LTR_ACT_8822B(v))
+
+/* 2 REG_H2CQ_TXBD_DESA_8822B */
+
+#define BIT_SHIFT_H2CQ_TXBD_DESA_8822B 0
+#define BIT_MASK_H2CQ_TXBD_DESA_8822B 0xffffffffffffffffL
+#define BIT_H2CQ_TXBD_DESA_8822B(x)                                            \
+	(((x) & BIT_MASK_H2CQ_TXBD_DESA_8822B)                                 \
+	 << BIT_SHIFT_H2CQ_TXBD_DESA_8822B)
+#define BITS_H2CQ_TXBD_DESA_8822B                                              \
+	(BIT_MASK_H2CQ_TXBD_DESA_8822B << BIT_SHIFT_H2CQ_TXBD_DESA_8822B)
+#define BIT_CLEAR_H2CQ_TXBD_DESA_8822B(x) ((x) & (~BITS_H2CQ_TXBD_DESA_8822B))
+#define BIT_GET_H2CQ_TXBD_DESA_8822B(x)                                        \
+	(((x) >> BIT_SHIFT_H2CQ_TXBD_DESA_8822B) &                             \
+	 BIT_MASK_H2CQ_TXBD_DESA_8822B)
+#define BIT_SET_H2CQ_TXBD_DESA_8822B(x, v)                                     \
+	(BIT_CLEAR_H2CQ_TXBD_DESA_8822B(x) | BIT_H2CQ_TXBD_DESA_8822B(v))
+
+/* 2 REG_H2CQ_TXBD_NUM_8822B */
+#define BIT_PCIE_H2CQ_FLAG_8822B BIT(14)
+
+#define BIT_SHIFT_H2CQ_DESC_MODE_8822B 12
+#define BIT_MASK_H2CQ_DESC_MODE_8822B 0x3
+#define BIT_H2CQ_DESC_MODE_8822B(x)                                            \
+	(((x) & BIT_MASK_H2CQ_DESC_MODE_8822B)                                 \
+	 << BIT_SHIFT_H2CQ_DESC_MODE_8822B)
+#define BITS_H2CQ_DESC_MODE_8822B                                              \
+	(BIT_MASK_H2CQ_DESC_MODE_8822B << BIT_SHIFT_H2CQ_DESC_MODE_8822B)
+#define BIT_CLEAR_H2CQ_DESC_MODE_8822B(x) ((x) & (~BITS_H2CQ_DESC_MODE_8822B))
+#define BIT_GET_H2CQ_DESC_MODE_8822B(x)                                        \
+	(((x) >> BIT_SHIFT_H2CQ_DESC_MODE_8822B) &                             \
+	 BIT_MASK_H2CQ_DESC_MODE_8822B)
+#define BIT_SET_H2CQ_DESC_MODE_8822B(x, v)                                     \
+	(BIT_CLEAR_H2CQ_DESC_MODE_8822B(x) | BIT_H2CQ_DESC_MODE_8822B(v))
+
+#define BIT_SHIFT_H2CQ_DESC_NUM_8822B 0
+#define BIT_MASK_H2CQ_DESC_NUM_8822B 0xfff
+#define BIT_H2CQ_DESC_NUM_8822B(x)                                             \
+	(((x) & BIT_MASK_H2CQ_DESC_NUM_8822B) << BIT_SHIFT_H2CQ_DESC_NUM_8822B)
+#define BITS_H2CQ_DESC_NUM_8822B                                               \
+	(BIT_MASK_H2CQ_DESC_NUM_8822B << BIT_SHIFT_H2CQ_DESC_NUM_8822B)
+#define BIT_CLEAR_H2CQ_DESC_NUM_8822B(x) ((x) & (~BITS_H2CQ_DESC_NUM_8822B))
+#define BIT_GET_H2CQ_DESC_NUM_8822B(x)                                         \
+	(((x) >> BIT_SHIFT_H2CQ_DESC_NUM_8822B) & BIT_MASK_H2CQ_DESC_NUM_8822B)
+#define BIT_SET_H2CQ_DESC_NUM_8822B(x, v)                                      \
+	(BIT_CLEAR_H2CQ_DESC_NUM_8822B(x) | BIT_H2CQ_DESC_NUM_8822B(v))
+
+/* 2 REG_H2CQ_TXBD_IDX_8822B */
+
+#define BIT_SHIFT_H2CQ_HW_IDX_8822B 16
+#define BIT_MASK_H2CQ_HW_IDX_8822B 0xfff
+#define BIT_H2CQ_HW_IDX_8822B(x)                                               \
+	(((x) & BIT_MASK_H2CQ_HW_IDX_8822B) << BIT_SHIFT_H2CQ_HW_IDX_8822B)
+#define BITS_H2CQ_HW_IDX_8822B                                                 \
+	(BIT_MASK_H2CQ_HW_IDX_8822B << BIT_SHIFT_H2CQ_HW_IDX_8822B)
+#define BIT_CLEAR_H2CQ_HW_IDX_8822B(x) ((x) & (~BITS_H2CQ_HW_IDX_8822B))
+#define BIT_GET_H2CQ_HW_IDX_8822B(x)                                           \
+	(((x) >> BIT_SHIFT_H2CQ_HW_IDX_8822B) & BIT_MASK_H2CQ_HW_IDX_8822B)
+#define BIT_SET_H2CQ_HW_IDX_8822B(x, v)                                        \
+	(BIT_CLEAR_H2CQ_HW_IDX_8822B(x) | BIT_H2CQ_HW_IDX_8822B(v))
+
+#define BIT_SHIFT_H2CQ_HOST_IDX_8822B 0
+#define BIT_MASK_H2CQ_HOST_IDX_8822B 0xfff
+#define BIT_H2CQ_HOST_IDX_8822B(x)                                             \
+	(((x) & BIT_MASK_H2CQ_HOST_IDX_8822B) << BIT_SHIFT_H2CQ_HOST_IDX_8822B)
+#define BITS_H2CQ_HOST_IDX_8822B                                               \
+	(BIT_MASK_H2CQ_HOST_IDX_8822B << BIT_SHIFT_H2CQ_HOST_IDX_8822B)
+#define BIT_CLEAR_H2CQ_HOST_IDX_8822B(x) ((x) & (~BITS_H2CQ_HOST_IDX_8822B))
+#define BIT_GET_H2CQ_HOST_IDX_8822B(x)                                         \
+	(((x) >> BIT_SHIFT_H2CQ_HOST_IDX_8822B) & BIT_MASK_H2CQ_HOST_IDX_8822B)
+#define BIT_SET_H2CQ_HOST_IDX_8822B(x, v)                                      \
+	(BIT_CLEAR_H2CQ_HOST_IDX_8822B(x) | BIT_H2CQ_HOST_IDX_8822B(v))
+
+/* 2 REG_H2CQ_CSR_8822B[31:0] (H2CQ CONTROL AND STATUS) */
+#define BIT_H2CQ_FULL_8822B BIT(31)
+#define BIT_CLR_H2CQ_HOST_IDX_8822B BIT(16)
+#define BIT_CLR_H2CQ_HW_IDX_8822B BIT(8)
+#define BIT_STOP_H2CQ_8822B BIT(0)
+
+/* 2 REG_CHANGE_PCIE_SPEED_8822B */
+#define BIT_CHANGE_PCIE_SPEED_8822B BIT(18)
+
+#define BIT_SHIFT_GEN1_GEN2_8822B 16
+#define BIT_MASK_GEN1_GEN2_8822B 0x3
+#define BIT_GEN1_GEN2_8822B(x)                                                 \
+	(((x) & BIT_MASK_GEN1_GEN2_8822B) << BIT_SHIFT_GEN1_GEN2_8822B)
+#define BITS_GEN1_GEN2_8822B                                                   \
+	(BIT_MASK_GEN1_GEN2_8822B << BIT_SHIFT_GEN1_GEN2_8822B)
+#define BIT_CLEAR_GEN1_GEN2_8822B(x) ((x) & (~BITS_GEN1_GEN2_8822B))
+#define BIT_GET_GEN1_GEN2_8822B(x)                                             \
+	(((x) >> BIT_SHIFT_GEN1_GEN2_8822B) & BIT_MASK_GEN1_GEN2_8822B)
+#define BIT_SET_GEN1_GEN2_8822B(x, v)                                          \
+	(BIT_CLEAR_GEN1_GEN2_8822B(x) | BIT_GEN1_GEN2_8822B(v))
+
+#define BIT_SHIFT_RXDMA_ERROR_COUNTER_8822B 8
+#define BIT_MASK_RXDMA_ERROR_COUNTER_8822B 0xff
+#define BIT_RXDMA_ERROR_COUNTER_8822B(x)                                       \
+	(((x) & BIT_MASK_RXDMA_ERROR_COUNTER_8822B)                            \
+	 << BIT_SHIFT_RXDMA_ERROR_COUNTER_8822B)
+#define BITS_RXDMA_ERROR_COUNTER_8822B                                         \
+	(BIT_MASK_RXDMA_ERROR_COUNTER_8822B                                    \
+	 << BIT_SHIFT_RXDMA_ERROR_COUNTER_8822B)
+#define BIT_CLEAR_RXDMA_ERROR_COUNTER_8822B(x)                                 \
+	((x) & (~BITS_RXDMA_ERROR_COUNTER_8822B))
+#define BIT_GET_RXDMA_ERROR_COUNTER_8822B(x)                                   \
+	(((x) >> BIT_SHIFT_RXDMA_ERROR_COUNTER_8822B) &                        \
+	 BIT_MASK_RXDMA_ERROR_COUNTER_8822B)
+#define BIT_SET_RXDMA_ERROR_COUNTER_8822B(x, v)                                \
+	(BIT_CLEAR_RXDMA_ERROR_COUNTER_8822B(x) |                              \
+	 BIT_RXDMA_ERROR_COUNTER_8822B(v))
+
+#define BIT_TXDMA_ERROR_HANDLE_STATUS_8822B BIT(7)
+#define BIT_TXDMA_ERROR_PULSE_8822B BIT(6)
+#define BIT_TXDMA_STUCK_ERROR_HANDLE_ENABLE_8822B BIT(5)
+#define BIT_TXDMA_RETURN_ERROR_ENABLE_8822B BIT(4)
+#define BIT_RXDMA_ERROR_HANDLE_STATUS_8822B BIT(3)
+
+#define BIT_SHIFT_AUTO_HANG_RELEASE_8822B 0
+#define BIT_MASK_AUTO_HANG_RELEASE_8822B 0x7
+#define BIT_AUTO_HANG_RELEASE_8822B(x)                                         \
+	(((x) & BIT_MASK_AUTO_HANG_RELEASE_8822B)                              \
+	 << BIT_SHIFT_AUTO_HANG_RELEASE_8822B)
+#define BITS_AUTO_HANG_RELEASE_8822B                                           \
+	(BIT_MASK_AUTO_HANG_RELEASE_8822B << BIT_SHIFT_AUTO_HANG_RELEASE_8822B)
+#define BIT_CLEAR_AUTO_HANG_RELEASE_8822B(x)                                   \
+	((x) & (~BITS_AUTO_HANG_RELEASE_8822B))
+#define BIT_GET_AUTO_HANG_RELEASE_8822B(x)                                     \
+	(((x) >> BIT_SHIFT_AUTO_HANG_RELEASE_8822B) &                          \
+	 BIT_MASK_AUTO_HANG_RELEASE_8822B)
+#define BIT_SET_AUTO_HANG_RELEASE_8822B(x, v)                                  \
+	(BIT_CLEAR_AUTO_HANG_RELEASE_8822B(x) | BIT_AUTO_HANG_RELEASE_8822B(v))
+
+/* 2 REG_OLD_DEHANG_8822B */
+#define BIT_OLD_DEHANG_8822B BIT(1)
+
+/* 2 REG_Q0_INFO_8822B */
+
+#define BIT_SHIFT_QUEUEMACID_Q0_V1_8822B 25
+#define BIT_MASK_QUEUEMACID_Q0_V1_8822B 0x7f
+#define BIT_QUEUEMACID_Q0_V1_8822B(x)                                          \
+	(((x) & BIT_MASK_QUEUEMACID_Q0_V1_8822B)                               \
+	 << BIT_SHIFT_QUEUEMACID_Q0_V1_8822B)
+#define BITS_QUEUEMACID_Q0_V1_8822B                                            \
+	(BIT_MASK_QUEUEMACID_Q0_V1_8822B << BIT_SHIFT_QUEUEMACID_Q0_V1_8822B)
+#define BIT_CLEAR_QUEUEMACID_Q0_V1_8822B(x)                                    \
+	((x) & (~BITS_QUEUEMACID_Q0_V1_8822B))
+#define BIT_GET_QUEUEMACID_Q0_V1_8822B(x)                                      \
+	(((x) >> BIT_SHIFT_QUEUEMACID_Q0_V1_8822B) &                           \
+	 BIT_MASK_QUEUEMACID_Q0_V1_8822B)
+#define BIT_SET_QUEUEMACID_Q0_V1_8822B(x, v)                                   \
+	(BIT_CLEAR_QUEUEMACID_Q0_V1_8822B(x) | BIT_QUEUEMACID_Q0_V1_8822B(v))
+
+#define BIT_SHIFT_QUEUEAC_Q0_V1_8822B 23
+#define BIT_MASK_QUEUEAC_Q0_V1_8822B 0x3
+#define BIT_QUEUEAC_Q0_V1_8822B(x)                                             \
+	(((x) & BIT_MASK_QUEUEAC_Q0_V1_8822B) << BIT_SHIFT_QUEUEAC_Q0_V1_8822B)
+#define BITS_QUEUEAC_Q0_V1_8822B                                               \
+	(BIT_MASK_QUEUEAC_Q0_V1_8822B << BIT_SHIFT_QUEUEAC_Q0_V1_8822B)
+#define BIT_CLEAR_QUEUEAC_Q0_V1_8822B(x) ((x) & (~BITS_QUEUEAC_Q0_V1_8822B))
+#define BIT_GET_QUEUEAC_Q0_V1_8822B(x)                                         \
+	(((x) >> BIT_SHIFT_QUEUEAC_Q0_V1_8822B) & BIT_MASK_QUEUEAC_Q0_V1_8822B)
+#define BIT_SET_QUEUEAC_Q0_V1_8822B(x, v)                                      \
+	(BIT_CLEAR_QUEUEAC_Q0_V1_8822B(x) | BIT_QUEUEAC_Q0_V1_8822B(v))
+
+#define BIT_TIDEMPTY_Q0_V1_8822B BIT(22)
+
+#define BIT_SHIFT_TAIL_PKT_Q0_V2_8822B 11
+#define BIT_MASK_TAIL_PKT_Q0_V2_8822B 0x7ff
+#define BIT_TAIL_PKT_Q0_V2_8822B(x)                                            \
+	(((x) & BIT_MASK_TAIL_PKT_Q0_V2_8822B)                                 \
+	 << BIT_SHIFT_TAIL_PKT_Q0_V2_8822B)
+#define BITS_TAIL_PKT_Q0_V2_8822B                                              \
+	(BIT_MASK_TAIL_PKT_Q0_V2_8822B << BIT_SHIFT_TAIL_PKT_Q0_V2_8822B)
+#define BIT_CLEAR_TAIL_PKT_Q0_V2_8822B(x) ((x) & (~BITS_TAIL_PKT_Q0_V2_8822B))
+#define BIT_GET_TAIL_PKT_Q0_V2_8822B(x)                                        \
+	(((x) >> BIT_SHIFT_TAIL_PKT_Q0_V2_8822B) &                             \
+	 BIT_MASK_TAIL_PKT_Q0_V2_8822B)
+#define BIT_SET_TAIL_PKT_Q0_V2_8822B(x, v)                                     \
+	(BIT_CLEAR_TAIL_PKT_Q0_V2_8822B(x) | BIT_TAIL_PKT_Q0_V2_8822B(v))
+
+#define BIT_SHIFT_HEAD_PKT_Q0_V1_8822B 0
+#define BIT_MASK_HEAD_PKT_Q0_V1_8822B 0x7ff
+#define BIT_HEAD_PKT_Q0_V1_8822B(x)                                            \
+	(((x) & BIT_MASK_HEAD_PKT_Q0_V1_8822B)                                 \
+	 << BIT_SHIFT_HEAD_PKT_Q0_V1_8822B)
+#define BITS_HEAD_PKT_Q0_V1_8822B                                              \
+	(BIT_MASK_HEAD_PKT_Q0_V1_8822B << BIT_SHIFT_HEAD_PKT_Q0_V1_8822B)
+#define BIT_CLEAR_HEAD_PKT_Q0_V1_8822B(x) ((x) & (~BITS_HEAD_PKT_Q0_V1_8822B))
+#define BIT_GET_HEAD_PKT_Q0_V1_8822B(x)                                        \
+	(((x) >> BIT_SHIFT_HEAD_PKT_Q0_V1_8822B) &                             \
+	 BIT_MASK_HEAD_PKT_Q0_V1_8822B)
+#define BIT_SET_HEAD_PKT_Q0_V1_8822B(x, v)                                     \
+	(BIT_CLEAR_HEAD_PKT_Q0_V1_8822B(x) | BIT_HEAD_PKT_Q0_V1_8822B(v))
+
+/* 2 REG_Q1_INFO_8822B */
+
+#define BIT_SHIFT_QUEUEMACID_Q1_V1_8822B 25
+#define BIT_MASK_QUEUEMACID_Q1_V1_8822B 0x7f
+#define BIT_QUEUEMACID_Q1_V1_8822B(x)                                          \
+	(((x) & BIT_MASK_QUEUEMACID_Q1_V1_8822B)                               \
+	 << BIT_SHIFT_QUEUEMACID_Q1_V1_8822B)
+#define BITS_QUEUEMACID_Q1_V1_8822B                                            \
+	(BIT_MASK_QUEUEMACID_Q1_V1_8822B << BIT_SHIFT_QUEUEMACID_Q1_V1_8822B)
+#define BIT_CLEAR_QUEUEMACID_Q1_V1_8822B(x)                                    \
+	((x) & (~BITS_QUEUEMACID_Q1_V1_8822B))
+#define BIT_GET_QUEUEMACID_Q1_V1_8822B(x)                                      \
+	(((x) >> BIT_SHIFT_QUEUEMACID_Q1_V1_8822B) &                           \
+	 BIT_MASK_QUEUEMACID_Q1_V1_8822B)
+#define BIT_SET_QUEUEMACID_Q1_V1_8822B(x, v)                                   \
+	(BIT_CLEAR_QUEUEMACID_Q1_V1_8822B(x) | BIT_QUEUEMACID_Q1_V1_8822B(v))
+
+#define BIT_SHIFT_QUEUEAC_Q1_V1_8822B 23
+#define BIT_MASK_QUEUEAC_Q1_V1_8822B 0x3
+#define BIT_QUEUEAC_Q1_V1_8822B(x)                                             \
+	(((x) & BIT_MASK_QUEUEAC_Q1_V1_8822B) << BIT_SHIFT_QUEUEAC_Q1_V1_8822B)
+#define BITS_QUEUEAC_Q1_V1_8822B                                               \
+	(BIT_MASK_QUEUEAC_Q1_V1_8822B << BIT_SHIFT_QUEUEAC_Q1_V1_8822B)
+#define BIT_CLEAR_QUEUEAC_Q1_V1_8822B(x) ((x) & (~BITS_QUEUEAC_Q1_V1_8822B))
+#define BIT_GET_QUEUEAC_Q1_V1_8822B(x)                                         \
+	(((x) >> BIT_SHIFT_QUEUEAC_Q1_V1_8822B) & BIT_MASK_QUEUEAC_Q1_V1_8822B)
+#define BIT_SET_QUEUEAC_Q1_V1_8822B(x, v)                                      \
+	(BIT_CLEAR_QUEUEAC_Q1_V1_8822B(x) | BIT_QUEUEAC_Q1_V1_8822B(v))
+
+#define BIT_TIDEMPTY_Q1_V1_8822B BIT(22)
+
+#define BIT_SHIFT_TAIL_PKT_Q1_V2_8822B 11
+#define BIT_MASK_TAIL_PKT_Q1_V2_8822B 0x7ff
+#define BIT_TAIL_PKT_Q1_V2_8822B(x)                                            \
+	(((x) & BIT_MASK_TAIL_PKT_Q1_V2_8822B)                                 \
+	 << BIT_SHIFT_TAIL_PKT_Q1_V2_8822B)
+#define BITS_TAIL_PKT_Q1_V2_8822B                                              \
+	(BIT_MASK_TAIL_PKT_Q1_V2_8822B << BIT_SHIFT_TAIL_PKT_Q1_V2_8822B)
+#define BIT_CLEAR_TAIL_PKT_Q1_V2_8822B(x) ((x) & (~BITS_TAIL_PKT_Q1_V2_8822B))
+#define BIT_GET_TAIL_PKT_Q1_V2_8822B(x)                                        \
+	(((x) >> BIT_SHIFT_TAIL_PKT_Q1_V2_8822B) &                             \
+	 BIT_MASK_TAIL_PKT_Q1_V2_8822B)
+#define BIT_SET_TAIL_PKT_Q1_V2_8822B(x, v)                                     \
+	(BIT_CLEAR_TAIL_PKT_Q1_V2_8822B(x) | BIT_TAIL_PKT_Q1_V2_8822B(v))
+
+#define BIT_SHIFT_HEAD_PKT_Q1_V1_8822B 0
+#define BIT_MASK_HEAD_PKT_Q1_V1_8822B 0x7ff
+#define BIT_HEAD_PKT_Q1_V1_8822B(x)                                            \
+	(((x) & BIT_MASK_HEAD_PKT_Q1_V1_8822B)                                 \
+	 << BIT_SHIFT_HEAD_PKT_Q1_V1_8822B)
+#define BITS_HEAD_PKT_Q1_V1_8822B                                              \
+	(BIT_MASK_HEAD_PKT_Q1_V1_8822B << BIT_SHIFT_HEAD_PKT_Q1_V1_8822B)
+#define BIT_CLEAR_HEAD_PKT_Q1_V1_8822B(x) ((x) & (~BITS_HEAD_PKT_Q1_V1_8822B))
+#define BIT_GET_HEAD_PKT_Q1_V1_8822B(x)                                        \
+	(((x) >> BIT_SHIFT_HEAD_PKT_Q1_V1_8822B) &                             \
+	 BIT_MASK_HEAD_PKT_Q1_V1_8822B)
+#define BIT_SET_HEAD_PKT_Q1_V1_8822B(x, v)                                     \
+	(BIT_CLEAR_HEAD_PKT_Q1_V1_8822B(x) | BIT_HEAD_PKT_Q1_V1_8822B(v))
+
+/* 2 REG_Q2_INFO_8822B */
+
+#define BIT_SHIFT_QUEUEMACID_Q2_V1_8822B 25
+#define BIT_MASK_QUEUEMACID_Q2_V1_8822B 0x7f
+#define BIT_QUEUEMACID_Q2_V1_8822B(x)                                          \
+	(((x) & BIT_MASK_QUEUEMACID_Q2_V1_8822B)                               \
+	 << BIT_SHIFT_QUEUEMACID_Q2_V1_8822B)
+#define BITS_QUEUEMACID_Q2_V1_8822B                                            \
+	(BIT_MASK_QUEUEMACID_Q2_V1_8822B << BIT_SHIFT_QUEUEMACID_Q2_V1_8822B)
+#define BIT_CLEAR_QUEUEMACID_Q2_V1_8822B(x)                                    \
+	((x) & (~BITS_QUEUEMACID_Q2_V1_8822B))
+#define BIT_GET_QUEUEMACID_Q2_V1_8822B(x)                                      \
+	(((x) >> BIT_SHIFT_QUEUEMACID_Q2_V1_8822B) &                           \
+	 BIT_MASK_QUEUEMACID_Q2_V1_8822B)
+#define BIT_SET_QUEUEMACID_Q2_V1_8822B(x, v)                                   \
+	(BIT_CLEAR_QUEUEMACID_Q2_V1_8822B(x) | BIT_QUEUEMACID_Q2_V1_8822B(v))
+
+#define BIT_SHIFT_QUEUEAC_Q2_V1_8822B 23
+#define BIT_MASK_QUEUEAC_Q2_V1_8822B 0x3
+#define BIT_QUEUEAC_Q2_V1_8822B(x)                                             \
+	(((x) & BIT_MASK_QUEUEAC_Q2_V1_8822B) << BIT_SHIFT_QUEUEAC_Q2_V1_8822B)
+#define BITS_QUEUEAC_Q2_V1_8822B                                               \
+	(BIT_MASK_QUEUEAC_Q2_V1_8822B << BIT_SHIFT_QUEUEAC_Q2_V1_8822B)
+#define BIT_CLEAR_QUEUEAC_Q2_V1_8822B(x) ((x) & (~BITS_QUEUEAC_Q2_V1_8822B))
+#define BIT_GET_QUEUEAC_Q2_V1_8822B(x)                                         \
+	(((x) >> BIT_SHIFT_QUEUEAC_Q2_V1_8822B) & BIT_MASK_QUEUEAC_Q2_V1_8822B)
+#define BIT_SET_QUEUEAC_Q2_V1_8822B(x, v)                                      \
+	(BIT_CLEAR_QUEUEAC_Q2_V1_8822B(x) | BIT_QUEUEAC_Q2_V1_8822B(v))
+
+#define BIT_TIDEMPTY_Q2_V1_8822B BIT(22)
+
+#define BIT_SHIFT_TAIL_PKT_Q2_V2_8822B 11
+#define BIT_MASK_TAIL_PKT_Q2_V2_8822B 0x7ff
+#define BIT_TAIL_PKT_Q2_V2_8822B(x)                                            \
+	(((x) & BIT_MASK_TAIL_PKT_Q2_V2_8822B)                                 \
+	 << BIT_SHIFT_TAIL_PKT_Q2_V2_8822B)
+#define BITS_TAIL_PKT_Q2_V2_8822B                                              \
+	(BIT_MASK_TAIL_PKT_Q2_V2_8822B << BIT_SHIFT_TAIL_PKT_Q2_V2_8822B)
+#define BIT_CLEAR_TAIL_PKT_Q2_V2_8822B(x) ((x) & (~BITS_TAIL_PKT_Q2_V2_8822B))
+#define BIT_GET_TAIL_PKT_Q2_V2_8822B(x)                                        \
+	(((x) >> BIT_SHIFT_TAIL_PKT_Q2_V2_8822B) &                             \
+	 BIT_MASK_TAIL_PKT_Q2_V2_8822B)
+#define BIT_SET_TAIL_PKT_Q2_V2_8822B(x, v)                                     \
+	(BIT_CLEAR_TAIL_PKT_Q2_V2_8822B(x) | BIT_TAIL_PKT_Q2_V2_8822B(v))
+
+#define BIT_SHIFT_HEAD_PKT_Q2_V1_8822B 0
+#define BIT_MASK_HEAD_PKT_Q2_V1_8822B 0x7ff
+#define BIT_HEAD_PKT_Q2_V1_8822B(x)                                            \
+	(((x) & BIT_MASK_HEAD_PKT_Q2_V1_8822B)                                 \
+	 << BIT_SHIFT_HEAD_PKT_Q2_V1_8822B)
+#define BITS_HEAD_PKT_Q2_V1_8822B                                              \
+	(BIT_MASK_HEAD_PKT_Q2_V1_8822B << BIT_SHIFT_HEAD_PKT_Q2_V1_8822B)
+#define BIT_CLEAR_HEAD_PKT_Q2_V1_8822B(x) ((x) & (~BITS_HEAD_PKT_Q2_V1_8822B))
+#define BIT_GET_HEAD_PKT_Q2_V1_8822B(x)                                        \
+	(((x) >> BIT_SHIFT_HEAD_PKT_Q2_V1_8822B) &                             \
+	 BIT_MASK_HEAD_PKT_Q2_V1_8822B)
+#define BIT_SET_HEAD_PKT_Q2_V1_8822B(x, v)                                     \
+	(BIT_CLEAR_HEAD_PKT_Q2_V1_8822B(x) | BIT_HEAD_PKT_Q2_V1_8822B(v))
+
+/* 2 REG_Q3_INFO_8822B */
+
+#define BIT_SHIFT_QUEUEMACID_Q3_V1_8822B 25
+#define BIT_MASK_QUEUEMACID_Q3_V1_8822B 0x7f
+#define BIT_QUEUEMACID_Q3_V1_8822B(x)                                          \
+	(((x) & BIT_MASK_QUEUEMACID_Q3_V1_8822B)                               \
+	 << BIT_SHIFT_QUEUEMACID_Q3_V1_8822B)
+#define BITS_QUEUEMACID_Q3_V1_8822B                                            \
+	(BIT_MASK_QUEUEMACID_Q3_V1_8822B << BIT_SHIFT_QUEUEMACID_Q3_V1_8822B)
+#define BIT_CLEAR_QUEUEMACID_Q3_V1_8822B(x)                                    \
+	((x) & (~BITS_QUEUEMACID_Q3_V1_8822B))
+#define BIT_GET_QUEUEMACID_Q3_V1_8822B(x)                                      \
+	(((x) >> BIT_SHIFT_QUEUEMACID_Q3_V1_8822B) &                           \
+	 BIT_MASK_QUEUEMACID_Q3_V1_8822B)
+#define BIT_SET_QUEUEMACID_Q3_V1_8822B(x, v)                                   \
+	(BIT_CLEAR_QUEUEMACID_Q3_V1_8822B(x) | BIT_QUEUEMACID_Q3_V1_8822B(v))
+
+#define BIT_SHIFT_QUEUEAC_Q3_V1_8822B 23
+#define BIT_MASK_QUEUEAC_Q3_V1_8822B 0x3
+#define BIT_QUEUEAC_Q3_V1_8822B(x)                                             \
+	(((x) & BIT_MASK_QUEUEAC_Q3_V1_8822B) << BIT_SHIFT_QUEUEAC_Q3_V1_8822B)
+#define BITS_QUEUEAC_Q3_V1_8822B                                               \
+	(BIT_MASK_QUEUEAC_Q3_V1_8822B << BIT_SHIFT_QUEUEAC_Q3_V1_8822B)
+#define BIT_CLEAR_QUEUEAC_Q3_V1_8822B(x) ((x) & (~BITS_QUEUEAC_Q3_V1_8822B))
+#define BIT_GET_QUEUEAC_Q3_V1_8822B(x)                                         \
+	(((x) >> BIT_SHIFT_QUEUEAC_Q3_V1_8822B) & BIT_MASK_QUEUEAC_Q3_V1_8822B)
+#define BIT_SET_QUEUEAC_Q3_V1_8822B(x, v)                                      \
+	(BIT_CLEAR_QUEUEAC_Q3_V1_8822B(x) | BIT_QUEUEAC_Q3_V1_8822B(v))
+
+#define BIT_TIDEMPTY_Q3_V1_8822B BIT(22)
+
+#define BIT_SHIFT_TAIL_PKT_Q3_V2_8822B 11
+#define BIT_MASK_TAIL_PKT_Q3_V2_8822B 0x7ff
+#define BIT_TAIL_PKT_Q3_V2_8822B(x)                                            \
+	(((x) & BIT_MASK_TAIL_PKT_Q3_V2_8822B)                                 \
+	 << BIT_SHIFT_TAIL_PKT_Q3_V2_8822B)
+#define BITS_TAIL_PKT_Q3_V2_8822B                                              \
+	(BIT_MASK_TAIL_PKT_Q3_V2_8822B << BIT_SHIFT_TAIL_PKT_Q3_V2_8822B)
+#define BIT_CLEAR_TAIL_PKT_Q3_V2_8822B(x) ((x) & (~BITS_TAIL_PKT_Q3_V2_8822B))
+#define BIT_GET_TAIL_PKT_Q3_V2_8822B(x)                                        \
+	(((x) >> BIT_SHIFT_TAIL_PKT_Q3_V2_8822B) &                             \
+	 BIT_MASK_TAIL_PKT_Q3_V2_8822B)
+#define BIT_SET_TAIL_PKT_Q3_V2_8822B(x, v)                                     \
+	(BIT_CLEAR_TAIL_PKT_Q3_V2_8822B(x) | BIT_TAIL_PKT_Q3_V2_8822B(v))
+
+#define BIT_SHIFT_HEAD_PKT_Q3_V1_8822B 0
+#define BIT_MASK_HEAD_PKT_Q3_V1_8822B 0x7ff
+#define BIT_HEAD_PKT_Q3_V1_8822B(x)                                            \
+	(((x) & BIT_MASK_HEAD_PKT_Q3_V1_8822B)                                 \
+	 << BIT_SHIFT_HEAD_PKT_Q3_V1_8822B)
+#define BITS_HEAD_PKT_Q3_V1_8822B                                              \
+	(BIT_MASK_HEAD_PKT_Q3_V1_8822B << BIT_SHIFT_HEAD_PKT_Q3_V1_8822B)
+#define BIT_CLEAR_HEAD_PKT_Q3_V1_8822B(x) ((x) & (~BITS_HEAD_PKT_Q3_V1_8822B))
+#define BIT_GET_HEAD_PKT_Q3_V1_8822B(x)                                        \
+	(((x) >> BIT_SHIFT_HEAD_PKT_Q3_V1_8822B) &                             \
+	 BIT_MASK_HEAD_PKT_Q3_V1_8822B)
+#define BIT_SET_HEAD_PKT_Q3_V1_8822B(x, v)                                     \
+	(BIT_CLEAR_HEAD_PKT_Q3_V1_8822B(x) | BIT_HEAD_PKT_Q3_V1_8822B(v))
+
+/* 2 REG_MGQ_INFO_8822B */
+
+#define BIT_SHIFT_QUEUEMACID_MGQ_V1_8822B 25
+#define BIT_MASK_QUEUEMACID_MGQ_V1_8822B 0x7f
+#define BIT_QUEUEMACID_MGQ_V1_8822B(x)                                         \
+	(((x) & BIT_MASK_QUEUEMACID_MGQ_V1_8822B)                              \
+	 << BIT_SHIFT_QUEUEMACID_MGQ_V1_8822B)
+#define BITS_QUEUEMACID_MGQ_V1_8822B                                           \
+	(BIT_MASK_QUEUEMACID_MGQ_V1_8822B << BIT_SHIFT_QUEUEMACID_MGQ_V1_8822B)
+#define BIT_CLEAR_QUEUEMACID_MGQ_V1_8822B(x)                                   \
+	((x) & (~BITS_QUEUEMACID_MGQ_V1_8822B))
+#define BIT_GET_QUEUEMACID_MGQ_V1_8822B(x)                                     \
+	(((x) >> BIT_SHIFT_QUEUEMACID_MGQ_V1_8822B) &                          \
+	 BIT_MASK_QUEUEMACID_MGQ_V1_8822B)
+#define BIT_SET_QUEUEMACID_MGQ_V1_8822B(x, v)                                  \
+	(BIT_CLEAR_QUEUEMACID_MGQ_V1_8822B(x) | BIT_QUEUEMACID_MGQ_V1_8822B(v))
+
+#define BIT_SHIFT_QUEUEAC_MGQ_V1_8822B 23
+#define BIT_MASK_QUEUEAC_MGQ_V1_8822B 0x3
+#define BIT_QUEUEAC_MGQ_V1_8822B(x)                                            \
+	(((x) & BIT_MASK_QUEUEAC_MGQ_V1_8822B)                                 \
+	 << BIT_SHIFT_QUEUEAC_MGQ_V1_8822B)
+#define BITS_QUEUEAC_MGQ_V1_8822B                                              \
+	(BIT_MASK_QUEUEAC_MGQ_V1_8822B << BIT_SHIFT_QUEUEAC_MGQ_V1_8822B)
+#define BIT_CLEAR_QUEUEAC_MGQ_V1_8822B(x) ((x) & (~BITS_QUEUEAC_MGQ_V1_8822B))
+#define BIT_GET_QUEUEAC_MGQ_V1_8822B(x)                                        \
+	(((x) >> BIT_SHIFT_QUEUEAC_MGQ_V1_8822B) &                             \
+	 BIT_MASK_QUEUEAC_MGQ_V1_8822B)
+#define BIT_SET_QUEUEAC_MGQ_V1_8822B(x, v)                                     \
+	(BIT_CLEAR_QUEUEAC_MGQ_V1_8822B(x) | BIT_QUEUEAC_MGQ_V1_8822B(v))
+
+#define BIT_TIDEMPTY_MGQ_V1_8822B BIT(22)
+
+#define BIT_SHIFT_TAIL_PKT_MGQ_V2_8822B 11
+#define BIT_MASK_TAIL_PKT_MGQ_V2_8822B 0x7ff
+#define BIT_TAIL_PKT_MGQ_V2_8822B(x)                                           \
+	(((x) & BIT_MASK_TAIL_PKT_MGQ_V2_8822B)                                \
+	 << BIT_SHIFT_TAIL_PKT_MGQ_V2_8822B)
+#define BITS_TAIL_PKT_MGQ_V2_8822B                                             \
+	(BIT_MASK_TAIL_PKT_MGQ_V2_8822B << BIT_SHIFT_TAIL_PKT_MGQ_V2_8822B)
+#define BIT_CLEAR_TAIL_PKT_MGQ_V2_8822B(x) ((x) & (~BITS_TAIL_PKT_MGQ_V2_8822B))
+#define BIT_GET_TAIL_PKT_MGQ_V2_8822B(x)                                       \
+	(((x) >> BIT_SHIFT_TAIL_PKT_MGQ_V2_8822B) &                            \
+	 BIT_MASK_TAIL_PKT_MGQ_V2_8822B)
+#define BIT_SET_TAIL_PKT_MGQ_V2_8822B(x, v)                                    \
+	(BIT_CLEAR_TAIL_PKT_MGQ_V2_8822B(x) | BIT_TAIL_PKT_MGQ_V2_8822B(v))
+
+#define BIT_SHIFT_HEAD_PKT_MGQ_V1_8822B 0
+#define BIT_MASK_HEAD_PKT_MGQ_V1_8822B 0x7ff
+#define BIT_HEAD_PKT_MGQ_V1_8822B(x)                                           \
+	(((x) & BIT_MASK_HEAD_PKT_MGQ_V1_8822B)                                \
+	 << BIT_SHIFT_HEAD_PKT_MGQ_V1_8822B)
+#define BITS_HEAD_PKT_MGQ_V1_8822B                                             \
+	(BIT_MASK_HEAD_PKT_MGQ_V1_8822B << BIT_SHIFT_HEAD_PKT_MGQ_V1_8822B)
+#define BIT_CLEAR_HEAD_PKT_MGQ_V1_8822B(x) ((x) & (~BITS_HEAD_PKT_MGQ_V1_8822B))
+#define BIT_GET_HEAD_PKT_MGQ_V1_8822B(x)                                       \
+	(((x) >> BIT_SHIFT_HEAD_PKT_MGQ_V1_8822B) &                            \
+	 BIT_MASK_HEAD_PKT_MGQ_V1_8822B)
+#define BIT_SET_HEAD_PKT_MGQ_V1_8822B(x, v)                                    \
+	(BIT_CLEAR_HEAD_PKT_MGQ_V1_8822B(x) | BIT_HEAD_PKT_MGQ_V1_8822B(v))
+
+/* 2 REG_HIQ_INFO_8822B */
+
+#define BIT_SHIFT_QUEUEMACID_HIQ_V1_8822B 25
+#define BIT_MASK_QUEUEMACID_HIQ_V1_8822B 0x7f
+#define BIT_QUEUEMACID_HIQ_V1_8822B(x)                                         \
+	(((x) & BIT_MASK_QUEUEMACID_HIQ_V1_8822B)                              \
+	 << BIT_SHIFT_QUEUEMACID_HIQ_V1_8822B)
+#define BITS_QUEUEMACID_HIQ_V1_8822B                                           \
+	(BIT_MASK_QUEUEMACID_HIQ_V1_8822B << BIT_SHIFT_QUEUEMACID_HIQ_V1_8822B)
+#define BIT_CLEAR_QUEUEMACID_HIQ_V1_8822B(x)                                   \
+	((x) & (~BITS_QUEUEMACID_HIQ_V1_8822B))
+#define BIT_GET_QUEUEMACID_HIQ_V1_8822B(x)                                     \
+	(((x) >> BIT_SHIFT_QUEUEMACID_HIQ_V1_8822B) &                          \
+	 BIT_MASK_QUEUEMACID_HIQ_V1_8822B)
+#define BIT_SET_QUEUEMACID_HIQ_V1_8822B(x, v)                                  \
+	(BIT_CLEAR_QUEUEMACID_HIQ_V1_8822B(x) | BIT_QUEUEMACID_HIQ_V1_8822B(v))
+
+#define BIT_SHIFT_QUEUEAC_HIQ_V1_8822B 23
+#define BIT_MASK_QUEUEAC_HIQ_V1_8822B 0x3
+#define BIT_QUEUEAC_HIQ_V1_8822B(x)                                            \
+	(((x) & BIT_MASK_QUEUEAC_HIQ_V1_8822B)                                 \
+	 << BIT_SHIFT_QUEUEAC_HIQ_V1_8822B)
+#define BITS_QUEUEAC_HIQ_V1_8822B                                              \
+	(BIT_MASK_QUEUEAC_HIQ_V1_8822B << BIT_SHIFT_QUEUEAC_HIQ_V1_8822B)
+#define BIT_CLEAR_QUEUEAC_HIQ_V1_8822B(x) ((x) & (~BITS_QUEUEAC_HIQ_V1_8822B))
+#define BIT_GET_QUEUEAC_HIQ_V1_8822B(x)                                        \
+	(((x) >> BIT_SHIFT_QUEUEAC_HIQ_V1_8822B) &                             \
+	 BIT_MASK_QUEUEAC_HIQ_V1_8822B)
+#define BIT_SET_QUEUEAC_HIQ_V1_8822B(x, v)                                     \
+	(BIT_CLEAR_QUEUEAC_HIQ_V1_8822B(x) | BIT_QUEUEAC_HIQ_V1_8822B(v))
+
+#define BIT_TIDEMPTY_HIQ_V1_8822B BIT(22)
+
+#define BIT_SHIFT_TAIL_PKT_HIQ_V2_8822B 11
+#define BIT_MASK_TAIL_PKT_HIQ_V2_8822B 0x7ff
+#define BIT_TAIL_PKT_HIQ_V2_8822B(x)                                           \
+	(((x) & BIT_MASK_TAIL_PKT_HIQ_V2_8822B)                                \
+	 << BIT_SHIFT_TAIL_PKT_HIQ_V2_8822B)
+#define BITS_TAIL_PKT_HIQ_V2_8822B                                             \
+	(BIT_MASK_TAIL_PKT_HIQ_V2_8822B << BIT_SHIFT_TAIL_PKT_HIQ_V2_8822B)
+#define BIT_CLEAR_TAIL_PKT_HIQ_V2_8822B(x) ((x) & (~BITS_TAIL_PKT_HIQ_V2_8822B))
+#define BIT_GET_TAIL_PKT_HIQ_V2_8822B(x)                                       \
+	(((x) >> BIT_SHIFT_TAIL_PKT_HIQ_V2_8822B) &                            \
+	 BIT_MASK_TAIL_PKT_HIQ_V2_8822B)
+#define BIT_SET_TAIL_PKT_HIQ_V2_8822B(x, v)                                    \
+	(BIT_CLEAR_TAIL_PKT_HIQ_V2_8822B(x) | BIT_TAIL_PKT_HIQ_V2_8822B(v))
+
+#define BIT_SHIFT_HEAD_PKT_HIQ_V1_8822B 0
+#define BIT_MASK_HEAD_PKT_HIQ_V1_8822B 0x7ff
+#define BIT_HEAD_PKT_HIQ_V1_8822B(x)                                           \
+	(((x) & BIT_MASK_HEAD_PKT_HIQ_V1_8822B)                                \
+	 << BIT_SHIFT_HEAD_PKT_HIQ_V1_8822B)
+#define BITS_HEAD_PKT_HIQ_V1_8822B                                             \
+	(BIT_MASK_HEAD_PKT_HIQ_V1_8822B << BIT_SHIFT_HEAD_PKT_HIQ_V1_8822B)
+#define BIT_CLEAR_HEAD_PKT_HIQ_V1_8822B(x) ((x) & (~BITS_HEAD_PKT_HIQ_V1_8822B))
+#define BIT_GET_HEAD_PKT_HIQ_V1_8822B(x)                                       \
+	(((x) >> BIT_SHIFT_HEAD_PKT_HIQ_V1_8822B) &                            \
+	 BIT_MASK_HEAD_PKT_HIQ_V1_8822B)
+#define BIT_SET_HEAD_PKT_HIQ_V1_8822B(x, v)                                    \
+	(BIT_CLEAR_HEAD_PKT_HIQ_V1_8822B(x) | BIT_HEAD_PKT_HIQ_V1_8822B(v))
+
+/* 2 REG_BCNQ_INFO_8822B */
+
+#define BIT_SHIFT_BCNQ_HEAD_PG_V1_8822B 0
+#define BIT_MASK_BCNQ_HEAD_PG_V1_8822B 0xfff
+#define BIT_BCNQ_HEAD_PG_V1_8822B(x)                                           \
+	(((x) & BIT_MASK_BCNQ_HEAD_PG_V1_8822B)                                \
+	 << BIT_SHIFT_BCNQ_HEAD_PG_V1_8822B)
+#define BITS_BCNQ_HEAD_PG_V1_8822B                                             \
+	(BIT_MASK_BCNQ_HEAD_PG_V1_8822B << BIT_SHIFT_BCNQ_HEAD_PG_V1_8822B)
+#define BIT_CLEAR_BCNQ_HEAD_PG_V1_8822B(x) ((x) & (~BITS_BCNQ_HEAD_PG_V1_8822B))
+#define BIT_GET_BCNQ_HEAD_PG_V1_8822B(x)                                       \
+	(((x) >> BIT_SHIFT_BCNQ_HEAD_PG_V1_8822B) &                            \
+	 BIT_MASK_BCNQ_HEAD_PG_V1_8822B)
+#define BIT_SET_BCNQ_HEAD_PG_V1_8822B(x, v)                                    \
+	(BIT_CLEAR_BCNQ_HEAD_PG_V1_8822B(x) | BIT_BCNQ_HEAD_PG_V1_8822B(v))
+
+/* 2 REG_TXPKT_EMPTY_8822B */
+#define BIT_BCNQ_EMPTY_8822B BIT(11)
+#define BIT_HQQ_EMPTY_8822B BIT(10)
+#define BIT_MQQ_EMPTY_8822B BIT(9)
+#define BIT_MGQ_CPU_EMPTY_8822B BIT(8)
+#define BIT_AC7Q_EMPTY_8822B BIT(7)
+#define BIT_AC6Q_EMPTY_8822B BIT(6)
+#define BIT_AC5Q_EMPTY_8822B BIT(5)
+#define BIT_AC4Q_EMPTY_8822B BIT(4)
+#define BIT_AC3Q_EMPTY_8822B BIT(3)
+#define BIT_AC2Q_EMPTY_8822B BIT(2)
+#define BIT_AC1Q_EMPTY_8822B BIT(1)
+#define BIT_AC0Q_EMPTY_8822B BIT(0)
+
+/* 2 REG_CPU_MGQ_INFO_8822B */
+#define BIT_BCN1_POLL_8822B BIT(30)
+#define BIT_CPUMGT_POLL_8822B BIT(29)
+#define BIT_BCN_POLL_8822B BIT(28)
+#define BIT_CPUMGQ_FW_NUM_V1_8822B BIT(12)
+
+#define BIT_SHIFT_FW_FREE_TAIL_V1_8822B 0
+#define BIT_MASK_FW_FREE_TAIL_V1_8822B 0xfff
+#define BIT_FW_FREE_TAIL_V1_8822B(x)                                           \
+	(((x) & BIT_MASK_FW_FREE_TAIL_V1_8822B)                                \
+	 << BIT_SHIFT_FW_FREE_TAIL_V1_8822B)
+#define BITS_FW_FREE_TAIL_V1_8822B                                             \
+	(BIT_MASK_FW_FREE_TAIL_V1_8822B << BIT_SHIFT_FW_FREE_TAIL_V1_8822B)
+#define BIT_CLEAR_FW_FREE_TAIL_V1_8822B(x) ((x) & (~BITS_FW_FREE_TAIL_V1_8822B))
+#define BIT_GET_FW_FREE_TAIL_V1_8822B(x)                                       \
+	(((x) >> BIT_SHIFT_FW_FREE_TAIL_V1_8822B) &                            \
+	 BIT_MASK_FW_FREE_TAIL_V1_8822B)
+#define BIT_SET_FW_FREE_TAIL_V1_8822B(x, v)                                    \
+	(BIT_CLEAR_FW_FREE_TAIL_V1_8822B(x) | BIT_FW_FREE_TAIL_V1_8822B(v))
+
+/* 2 REG_FWHW_TXQ_CTRL_8822B */
+#define BIT_RTS_LIMIT_IN_OFDM_8822B BIT(23)
+#define BIT_EN_BCNQ_DL_8822B BIT(22)
+#define BIT_EN_RD_RESP_NAV_BK_8822B BIT(21)
+#define BIT_EN_WR_FREE_TAIL_8822B BIT(20)
+
+#define BIT_SHIFT_EN_QUEUE_RPT_8822B 8
+#define BIT_MASK_EN_QUEUE_RPT_8822B 0xff
+#define BIT_EN_QUEUE_RPT_8822B(x)                                              \
+	(((x) & BIT_MASK_EN_QUEUE_RPT_8822B) << BIT_SHIFT_EN_QUEUE_RPT_8822B)
+#define BITS_EN_QUEUE_RPT_8822B                                                \
+	(BIT_MASK_EN_QUEUE_RPT_8822B << BIT_SHIFT_EN_QUEUE_RPT_8822B)
+#define BIT_CLEAR_EN_QUEUE_RPT_8822B(x) ((x) & (~BITS_EN_QUEUE_RPT_8822B))
+#define BIT_GET_EN_QUEUE_RPT_8822B(x)                                          \
+	(((x) >> BIT_SHIFT_EN_QUEUE_RPT_8822B) & BIT_MASK_EN_QUEUE_RPT_8822B)
+#define BIT_SET_EN_QUEUE_RPT_8822B(x, v)                                       \
+	(BIT_CLEAR_EN_QUEUE_RPT_8822B(x) | BIT_EN_QUEUE_RPT_8822B(v))
+
+#define BIT_EN_RTY_BK_8822B BIT(7)
+#define BIT_EN_USE_INI_RAT_8822B BIT(6)
+#define BIT_EN_RTS_NAV_BK_8822B BIT(5)
+#define BIT_DIS_SSN_CHECK_8822B BIT(4)
+#define BIT_MACID_MATCH_RTS_8822B BIT(3)
+#define BIT_EN_BCN_TRXRPT_V1_8822B BIT(2)
+#define BIT_EN_FTMACKRPT_8822B BIT(1)
+#define BIT_EN_FTMRPT_8822B BIT(0)
+
+/* 2 REG_DATAFB_SEL_8822B */
+
+#define BIT_SHIFT__R_DATA_FALLBACK_SEL_8822B 0
+#define BIT_MASK__R_DATA_FALLBACK_SEL_8822B 0x3
+#define BIT__R_DATA_FALLBACK_SEL_8822B(x)                                      \
+	(((x) & BIT_MASK__R_DATA_FALLBACK_SEL_8822B)                           \
+	 << BIT_SHIFT__R_DATA_FALLBACK_SEL_8822B)
+#define BITS__R_DATA_FALLBACK_SEL_8822B                                        \
+	(BIT_MASK__R_DATA_FALLBACK_SEL_8822B                                   \
+	 << BIT_SHIFT__R_DATA_FALLBACK_SEL_8822B)
+#define BIT_CLEAR__R_DATA_FALLBACK_SEL_8822B(x)                                \
+	((x) & (~BITS__R_DATA_FALLBACK_SEL_8822B))
+#define BIT_GET__R_DATA_FALLBACK_SEL_8822B(x)                                  \
+	(((x) >> BIT_SHIFT__R_DATA_FALLBACK_SEL_8822B) &                       \
+	 BIT_MASK__R_DATA_FALLBACK_SEL_8822B)
+#define BIT_SET__R_DATA_FALLBACK_SEL_8822B(x, v)                               \
+	(BIT_CLEAR__R_DATA_FALLBACK_SEL_8822B(x) |                             \
+	 BIT__R_DATA_FALLBACK_SEL_8822B(v))
+
+/* 2 REG_BCNQ_BDNY_V1_8822B */
+
+#define BIT_SHIFT_BCNQ_PGBNDY_V1_8822B 0
+#define BIT_MASK_BCNQ_PGBNDY_V1_8822B 0xfff
+#define BIT_BCNQ_PGBNDY_V1_8822B(x)                                            \
+	(((x) & BIT_MASK_BCNQ_PGBNDY_V1_8822B)                                 \
+	 << BIT_SHIFT_BCNQ_PGBNDY_V1_8822B)
+#define BITS_BCNQ_PGBNDY_V1_8822B                                              \
+	(BIT_MASK_BCNQ_PGBNDY_V1_8822B << BIT_SHIFT_BCNQ_PGBNDY_V1_8822B)
+#define BIT_CLEAR_BCNQ_PGBNDY_V1_8822B(x) ((x) & (~BITS_BCNQ_PGBNDY_V1_8822B))
+#define BIT_GET_BCNQ_PGBNDY_V1_8822B(x)                                        \
+	(((x) >> BIT_SHIFT_BCNQ_PGBNDY_V1_8822B) &                             \
+	 BIT_MASK_BCNQ_PGBNDY_V1_8822B)
+#define BIT_SET_BCNQ_PGBNDY_V1_8822B(x, v)                                     \
+	(BIT_CLEAR_BCNQ_PGBNDY_V1_8822B(x) | BIT_BCNQ_PGBNDY_V1_8822B(v))
+
+/* 2 REG_LIFETIME_EN_8822B */
+#define BIT_BT_INT_CPU_8822B BIT(7)
+#define BIT_BT_INT_PTA_8822B BIT(6)
+#define BIT_EN_CTRL_RTYBIT_8822B BIT(4)
+#define BIT_LIFETIME_BK_EN_8822B BIT(3)
+#define BIT_LIFETIME_BE_EN_8822B BIT(2)
+#define BIT_LIFETIME_VI_EN_8822B BIT(1)
+#define BIT_LIFETIME_VO_EN_8822B BIT(0)
+
+/* 2 REG_SPEC_SIFS_8822B */
+
+#define BIT_SHIFT_SPEC_SIFS_OFDM_PTCL_8822B 8
+#define BIT_MASK_SPEC_SIFS_OFDM_PTCL_8822B 0xff
+#define BIT_SPEC_SIFS_OFDM_PTCL_8822B(x)                                       \
+	(((x) & BIT_MASK_SPEC_SIFS_OFDM_PTCL_8822B)                            \
+	 << BIT_SHIFT_SPEC_SIFS_OFDM_PTCL_8822B)
+#define BITS_SPEC_SIFS_OFDM_PTCL_8822B                                         \
+	(BIT_MASK_SPEC_SIFS_OFDM_PTCL_8822B                                    \
+	 << BIT_SHIFT_SPEC_SIFS_OFDM_PTCL_8822B)
+#define BIT_CLEAR_SPEC_SIFS_OFDM_PTCL_8822B(x)                                 \
+	((x) & (~BITS_SPEC_SIFS_OFDM_PTCL_8822B))
+#define BIT_GET_SPEC_SIFS_OFDM_PTCL_8822B(x)                                   \
+	(((x) >> BIT_SHIFT_SPEC_SIFS_OFDM_PTCL_8822B) &                        \
+	 BIT_MASK_SPEC_SIFS_OFDM_PTCL_8822B)
+#define BIT_SET_SPEC_SIFS_OFDM_PTCL_8822B(x, v)                                \
+	(BIT_CLEAR_SPEC_SIFS_OFDM_PTCL_8822B(x) |                              \
+	 BIT_SPEC_SIFS_OFDM_PTCL_8822B(v))
+
+#define BIT_SHIFT_SPEC_SIFS_CCK_PTCL_8822B 0
+#define BIT_MASK_SPEC_SIFS_CCK_PTCL_8822B 0xff
+#define BIT_SPEC_SIFS_CCK_PTCL_8822B(x)                                        \
+	(((x) & BIT_MASK_SPEC_SIFS_CCK_PTCL_8822B)                             \
+	 << BIT_SHIFT_SPEC_SIFS_CCK_PTCL_8822B)
+#define BITS_SPEC_SIFS_CCK_PTCL_8822B                                          \
+	(BIT_MASK_SPEC_SIFS_CCK_PTCL_8822B                                     \
+	 << BIT_SHIFT_SPEC_SIFS_CCK_PTCL_8822B)
+#define BIT_CLEAR_SPEC_SIFS_CCK_PTCL_8822B(x)                                  \
+	((x) & (~BITS_SPEC_SIFS_CCK_PTCL_8822B))
+#define BIT_GET_SPEC_SIFS_CCK_PTCL_8822B(x)                                    \
+	(((x) >> BIT_SHIFT_SPEC_SIFS_CCK_PTCL_8822B) &                         \
+	 BIT_MASK_SPEC_SIFS_CCK_PTCL_8822B)
+#define BIT_SET_SPEC_SIFS_CCK_PTCL_8822B(x, v)                                 \
+	(BIT_CLEAR_SPEC_SIFS_CCK_PTCL_8822B(x) |                               \
+	 BIT_SPEC_SIFS_CCK_PTCL_8822B(v))
+
+/* 2 REG_RETRY_LIMIT_8822B */
+
+#define BIT_SHIFT_SRL_8822B 8
+#define BIT_MASK_SRL_8822B 0x3f
+#define BIT_SRL_8822B(x) (((x) & BIT_MASK_SRL_8822B) << BIT_SHIFT_SRL_8822B)
+#define BITS_SRL_8822B (BIT_MASK_SRL_8822B << BIT_SHIFT_SRL_8822B)
+#define BIT_CLEAR_SRL_8822B(x) ((x) & (~BITS_SRL_8822B))
+#define BIT_GET_SRL_8822B(x) (((x) >> BIT_SHIFT_SRL_8822B) & BIT_MASK_SRL_8822B)
+#define BIT_SET_SRL_8822B(x, v) (BIT_CLEAR_SRL_8822B(x) | BIT_SRL_8822B(v))
+
+#define BIT_SHIFT_LRL_8822B 0
+#define BIT_MASK_LRL_8822B 0x3f
+#define BIT_LRL_8822B(x) (((x) & BIT_MASK_LRL_8822B) << BIT_SHIFT_LRL_8822B)
+#define BITS_LRL_8822B (BIT_MASK_LRL_8822B << BIT_SHIFT_LRL_8822B)
+#define BIT_CLEAR_LRL_8822B(x) ((x) & (~BITS_LRL_8822B))
+#define BIT_GET_LRL_8822B(x) (((x) >> BIT_SHIFT_LRL_8822B) & BIT_MASK_LRL_8822B)
+#define BIT_SET_LRL_8822B(x, v) (BIT_CLEAR_LRL_8822B(x) | BIT_LRL_8822B(v))
+
+/* 2 REG_TXBF_CTRL_8822B */
+#define BIT_R_ENABLE_NDPA_8822B BIT(31)
+#define BIT_USE_NDPA_PARAMETER_8822B BIT(30)
+#define BIT_R_PROP_TXBF_8822B BIT(29)
+#define BIT_R_EN_NDPA_INT_8822B BIT(28)
+#define BIT_R_TXBF1_80M_8822B BIT(27)
+#define BIT_R_TXBF1_40M_8822B BIT(26)
+#define BIT_R_TXBF1_20M_8822B BIT(25)
+
+#define BIT_SHIFT_R_TXBF1_AID_8822B 16
+#define BIT_MASK_R_TXBF1_AID_8822B 0x1ff
+#define BIT_R_TXBF1_AID_8822B(x)                                               \
+	(((x) & BIT_MASK_R_TXBF1_AID_8822B) << BIT_SHIFT_R_TXBF1_AID_8822B)
+#define BITS_R_TXBF1_AID_8822B                                                 \
+	(BIT_MASK_R_TXBF1_AID_8822B << BIT_SHIFT_R_TXBF1_AID_8822B)
+#define BIT_CLEAR_R_TXBF1_AID_8822B(x) ((x) & (~BITS_R_TXBF1_AID_8822B))
+#define BIT_GET_R_TXBF1_AID_8822B(x)                                           \
+	(((x) >> BIT_SHIFT_R_TXBF1_AID_8822B) & BIT_MASK_R_TXBF1_AID_8822B)
+#define BIT_SET_R_TXBF1_AID_8822B(x, v)                                        \
+	(BIT_CLEAR_R_TXBF1_AID_8822B(x) | BIT_R_TXBF1_AID_8822B(v))
+
+#define BIT_DIS_NDP_BFEN_8822B BIT(15)
+#define BIT_R_TXBCN_NOBLOCK_NDP_8822B BIT(14)
+#define BIT_R_TXBF0_80M_8822B BIT(11)
+#define BIT_R_TXBF0_40M_8822B BIT(10)
+#define BIT_R_TXBF0_20M_8822B BIT(9)
+
+#define BIT_SHIFT_R_TXBF0_AID_8822B 0
+#define BIT_MASK_R_TXBF0_AID_8822B 0x1ff
+#define BIT_R_TXBF0_AID_8822B(x)                                               \
+	(((x) & BIT_MASK_R_TXBF0_AID_8822B) << BIT_SHIFT_R_TXBF0_AID_8822B)
+#define BITS_R_TXBF0_AID_8822B                                                 \
+	(BIT_MASK_R_TXBF0_AID_8822B << BIT_SHIFT_R_TXBF0_AID_8822B)
+#define BIT_CLEAR_R_TXBF0_AID_8822B(x) ((x) & (~BITS_R_TXBF0_AID_8822B))
+#define BIT_GET_R_TXBF0_AID_8822B(x)                                           \
+	(((x) >> BIT_SHIFT_R_TXBF0_AID_8822B) & BIT_MASK_R_TXBF0_AID_8822B)
+#define BIT_SET_R_TXBF0_AID_8822B(x, v)                                        \
+	(BIT_CLEAR_R_TXBF0_AID_8822B(x) | BIT_R_TXBF0_AID_8822B(v))
+
+/* 2 REG_DARFRC_8822B */
+
+#define BIT_SHIFT_DARF_RC8_8822B (56 & CPU_OPT_WIDTH)
+#define BIT_MASK_DARF_RC8_8822B 0x1f
+#define BIT_DARF_RC8_8822B(x)                                                  \
+	(((x) & BIT_MASK_DARF_RC8_8822B) << BIT_SHIFT_DARF_RC8_8822B)
+#define BITS_DARF_RC8_8822B                                                    \
+	(BIT_MASK_DARF_RC8_8822B << BIT_SHIFT_DARF_RC8_8822B)
+#define BIT_CLEAR_DARF_RC8_8822B(x) ((x) & (~BITS_DARF_RC8_8822B))
+#define BIT_GET_DARF_RC8_8822B(x)                                              \
+	(((x) >> BIT_SHIFT_DARF_RC8_8822B) & BIT_MASK_DARF_RC8_8822B)
+#define BIT_SET_DARF_RC8_8822B(x, v)                                           \
+	(BIT_CLEAR_DARF_RC8_8822B(x) | BIT_DARF_RC8_8822B(v))
+
+#define BIT_SHIFT_DARF_RC7_8822B (48 & CPU_OPT_WIDTH)
+#define BIT_MASK_DARF_RC7_8822B 0x1f
+#define BIT_DARF_RC7_8822B(x)                                                  \
+	(((x) & BIT_MASK_DARF_RC7_8822B) << BIT_SHIFT_DARF_RC7_8822B)
+#define BITS_DARF_RC7_8822B                                                    \
+	(BIT_MASK_DARF_RC7_8822B << BIT_SHIFT_DARF_RC7_8822B)
+#define BIT_CLEAR_DARF_RC7_8822B(x) ((x) & (~BITS_DARF_RC7_8822B))
+#define BIT_GET_DARF_RC7_8822B(x)                                              \
+	(((x) >> BIT_SHIFT_DARF_RC7_8822B) & BIT_MASK_DARF_RC7_8822B)
+#define BIT_SET_DARF_RC7_8822B(x, v)                                           \
+	(BIT_CLEAR_DARF_RC7_8822B(x) | BIT_DARF_RC7_8822B(v))
+
+#define BIT_SHIFT_DARF_RC6_8822B (40 & CPU_OPT_WIDTH)
+#define BIT_MASK_DARF_RC6_8822B 0x1f
+#define BIT_DARF_RC6_8822B(x)                                                  \
+	(((x) & BIT_MASK_DARF_RC6_8822B) << BIT_SHIFT_DARF_RC6_8822B)
+#define BITS_DARF_RC6_8822B                                                    \
+	(BIT_MASK_DARF_RC6_8822B << BIT_SHIFT_DARF_RC6_8822B)
+#define BIT_CLEAR_DARF_RC6_8822B(x) ((x) & (~BITS_DARF_RC6_8822B))
+#define BIT_GET_DARF_RC6_8822B(x)                                              \
+	(((x) >> BIT_SHIFT_DARF_RC6_8822B) & BIT_MASK_DARF_RC6_8822B)
+#define BIT_SET_DARF_RC6_8822B(x, v)                                           \
+	(BIT_CLEAR_DARF_RC6_8822B(x) | BIT_DARF_RC6_8822B(v))
+
+#define BIT_SHIFT_DARF_RC5_8822B (32 & CPU_OPT_WIDTH)
+#define BIT_MASK_DARF_RC5_8822B 0x1f
+#define BIT_DARF_RC5_8822B(x)                                                  \
+	(((x) & BIT_MASK_DARF_RC5_8822B) << BIT_SHIFT_DARF_RC5_8822B)
+#define BITS_DARF_RC5_8822B                                                    \
+	(BIT_MASK_DARF_RC5_8822B << BIT_SHIFT_DARF_RC5_8822B)
+#define BIT_CLEAR_DARF_RC5_8822B(x) ((x) & (~BITS_DARF_RC5_8822B))
+#define BIT_GET_DARF_RC5_8822B(x)                                              \
+	(((x) >> BIT_SHIFT_DARF_RC5_8822B) & BIT_MASK_DARF_RC5_8822B)
+#define BIT_SET_DARF_RC5_8822B(x, v)                                           \
+	(BIT_CLEAR_DARF_RC5_8822B(x) | BIT_DARF_RC5_8822B(v))
+
+#define BIT_SHIFT_DARF_RC4_8822B 24
+#define BIT_MASK_DARF_RC4_8822B 0x1f
+#define BIT_DARF_RC4_8822B(x)                                                  \
+	(((x) & BIT_MASK_DARF_RC4_8822B) << BIT_SHIFT_DARF_RC4_8822B)
+#define BITS_DARF_RC4_8822B                                                    \
+	(BIT_MASK_DARF_RC4_8822B << BIT_SHIFT_DARF_RC4_8822B)
+#define BIT_CLEAR_DARF_RC4_8822B(x) ((x) & (~BITS_DARF_RC4_8822B))
+#define BIT_GET_DARF_RC4_8822B(x)                                              \
+	(((x) >> BIT_SHIFT_DARF_RC4_8822B) & BIT_MASK_DARF_RC4_8822B)
+#define BIT_SET_DARF_RC4_8822B(x, v)                                           \
+	(BIT_CLEAR_DARF_RC4_8822B(x) | BIT_DARF_RC4_8822B(v))
+
+#define BIT_SHIFT_DARF_RC3_8822B 16
+#define BIT_MASK_DARF_RC3_8822B 0x1f
+#define BIT_DARF_RC3_8822B(x)                                                  \
+	(((x) & BIT_MASK_DARF_RC3_8822B) << BIT_SHIFT_DARF_RC3_8822B)
+#define BITS_DARF_RC3_8822B                                                    \
+	(BIT_MASK_DARF_RC3_8822B << BIT_SHIFT_DARF_RC3_8822B)
+#define BIT_CLEAR_DARF_RC3_8822B(x) ((x) & (~BITS_DARF_RC3_8822B))
+#define BIT_GET_DARF_RC3_8822B(x)                                              \
+	(((x) >> BIT_SHIFT_DARF_RC3_8822B) & BIT_MASK_DARF_RC3_8822B)
+#define BIT_SET_DARF_RC3_8822B(x, v)                                           \
+	(BIT_CLEAR_DARF_RC3_8822B(x) | BIT_DARF_RC3_8822B(v))
+
+#define BIT_SHIFT_DARF_RC2_8822B 8
+#define BIT_MASK_DARF_RC2_8822B 0x1f
+#define BIT_DARF_RC2_8822B(x)                                                  \
+	(((x) & BIT_MASK_DARF_RC2_8822B) << BIT_SHIFT_DARF_RC2_8822B)
+#define BITS_DARF_RC2_8822B                                                    \
+	(BIT_MASK_DARF_RC2_8822B << BIT_SHIFT_DARF_RC2_8822B)
+#define BIT_CLEAR_DARF_RC2_8822B(x) ((x) & (~BITS_DARF_RC2_8822B))
+#define BIT_GET_DARF_RC2_8822B(x)                                              \
+	(((x) >> BIT_SHIFT_DARF_RC2_8822B) & BIT_MASK_DARF_RC2_8822B)
+#define BIT_SET_DARF_RC2_8822B(x, v)                                           \
+	(BIT_CLEAR_DARF_RC2_8822B(x) | BIT_DARF_RC2_8822B(v))
+
+#define BIT_SHIFT_DARF_RC1_8822B 0
+#define BIT_MASK_DARF_RC1_8822B 0x1f
+#define BIT_DARF_RC1_8822B(x)                                                  \
+	(((x) & BIT_MASK_DARF_RC1_8822B) << BIT_SHIFT_DARF_RC1_8822B)
+#define BITS_DARF_RC1_8822B                                                    \
+	(BIT_MASK_DARF_RC1_8822B << BIT_SHIFT_DARF_RC1_8822B)
+#define BIT_CLEAR_DARF_RC1_8822B(x) ((x) & (~BITS_DARF_RC1_8822B))
+#define BIT_GET_DARF_RC1_8822B(x)                                              \
+	(((x) >> BIT_SHIFT_DARF_RC1_8822B) & BIT_MASK_DARF_RC1_8822B)
+#define BIT_SET_DARF_RC1_8822B(x, v)                                           \
+	(BIT_CLEAR_DARF_RC1_8822B(x) | BIT_DARF_RC1_8822B(v))
+
+/* 2 REG_RARFRC_8822B */
+
+#define BIT_SHIFT_RARF_RC8_8822B (56 & CPU_OPT_WIDTH)
+#define BIT_MASK_RARF_RC8_8822B 0x1f
+#define BIT_RARF_RC8_8822B(x)                                                  \
+	(((x) & BIT_MASK_RARF_RC8_8822B) << BIT_SHIFT_RARF_RC8_8822B)
+#define BITS_RARF_RC8_8822B                                                    \
+	(BIT_MASK_RARF_RC8_8822B << BIT_SHIFT_RARF_RC8_8822B)
+#define BIT_CLEAR_RARF_RC8_8822B(x) ((x) & (~BITS_RARF_RC8_8822B))
+#define BIT_GET_RARF_RC8_8822B(x)                                              \
+	(((x) >> BIT_SHIFT_RARF_RC8_8822B) & BIT_MASK_RARF_RC8_8822B)
+#define BIT_SET_RARF_RC8_8822B(x, v)                                           \
+	(BIT_CLEAR_RARF_RC8_8822B(x) | BIT_RARF_RC8_8822B(v))
+
+#define BIT_SHIFT_RARF_RC7_8822B (48 & CPU_OPT_WIDTH)
+#define BIT_MASK_RARF_RC7_8822B 0x1f
+#define BIT_RARF_RC7_8822B(x)                                                  \
+	(((x) & BIT_MASK_RARF_RC7_8822B) << BIT_SHIFT_RARF_RC7_8822B)
+#define BITS_RARF_RC7_8822B                                                    \
+	(BIT_MASK_RARF_RC7_8822B << BIT_SHIFT_RARF_RC7_8822B)
+#define BIT_CLEAR_RARF_RC7_8822B(x) ((x) & (~BITS_RARF_RC7_8822B))
+#define BIT_GET_RARF_RC7_8822B(x)                                              \
+	(((x) >> BIT_SHIFT_RARF_RC7_8822B) & BIT_MASK_RARF_RC7_8822B)
+#define BIT_SET_RARF_RC7_8822B(x, v)                                           \
+	(BIT_CLEAR_RARF_RC7_8822B(x) | BIT_RARF_RC7_8822B(v))
+
+#define BIT_SHIFT_RARF_RC6_8822B (40 & CPU_OPT_WIDTH)
+#define BIT_MASK_RARF_RC6_8822B 0x1f
+#define BIT_RARF_RC6_8822B(x)                                                  \
+	(((x) & BIT_MASK_RARF_RC6_8822B) << BIT_SHIFT_RARF_RC6_8822B)
+#define BITS_RARF_RC6_8822B                                                    \
+	(BIT_MASK_RARF_RC6_8822B << BIT_SHIFT_RARF_RC6_8822B)
+#define BIT_CLEAR_RARF_RC6_8822B(x) ((x) & (~BITS_RARF_RC6_8822B))
+#define BIT_GET_RARF_RC6_8822B(x)                                              \
+	(((x) >> BIT_SHIFT_RARF_RC6_8822B) & BIT_MASK_RARF_RC6_8822B)
+#define BIT_SET_RARF_RC6_8822B(x, v)                                           \
+	(BIT_CLEAR_RARF_RC6_8822B(x) | BIT_RARF_RC6_8822B(v))
+
+#define BIT_SHIFT_RARF_RC5_8822B (32 & CPU_OPT_WIDTH)
+#define BIT_MASK_RARF_RC5_8822B 0x1f
+#define BIT_RARF_RC5_8822B(x)                                                  \
+	(((x) & BIT_MASK_RARF_RC5_8822B) << BIT_SHIFT_RARF_RC5_8822B)
+#define BITS_RARF_RC5_8822B                                                    \
+	(BIT_MASK_RARF_RC5_8822B << BIT_SHIFT_RARF_RC5_8822B)
+#define BIT_CLEAR_RARF_RC5_8822B(x) ((x) & (~BITS_RARF_RC5_8822B))
+#define BIT_GET_RARF_RC5_8822B(x)                                              \
+	(((x) >> BIT_SHIFT_RARF_RC5_8822B) & BIT_MASK_RARF_RC5_8822B)
+#define BIT_SET_RARF_RC5_8822B(x, v)                                           \
+	(BIT_CLEAR_RARF_RC5_8822B(x) | BIT_RARF_RC5_8822B(v))
+
+#define BIT_SHIFT_RARF_RC4_8822B 24
+#define BIT_MASK_RARF_RC4_8822B 0x1f
+#define BIT_RARF_RC4_8822B(x)                                                  \
+	(((x) & BIT_MASK_RARF_RC4_8822B) << BIT_SHIFT_RARF_RC4_8822B)
+#define BITS_RARF_RC4_8822B                                                    \
+	(BIT_MASK_RARF_RC4_8822B << BIT_SHIFT_RARF_RC4_8822B)
+#define BIT_CLEAR_RARF_RC4_8822B(x) ((x) & (~BITS_RARF_RC4_8822B))
+#define BIT_GET_RARF_RC4_8822B(x)                                              \
+	(((x) >> BIT_SHIFT_RARF_RC4_8822B) & BIT_MASK_RARF_RC4_8822B)
+#define BIT_SET_RARF_RC4_8822B(x, v)                                           \
+	(BIT_CLEAR_RARF_RC4_8822B(x) | BIT_RARF_RC4_8822B(v))
+
+#define BIT_SHIFT_RARF_RC3_8822B 16
+#define BIT_MASK_RARF_RC3_8822B 0x1f
+#define BIT_RARF_RC3_8822B(x)                                                  \
+	(((x) & BIT_MASK_RARF_RC3_8822B) << BIT_SHIFT_RARF_RC3_8822B)
+#define BITS_RARF_RC3_8822B                                                    \
+	(BIT_MASK_RARF_RC3_8822B << BIT_SHIFT_RARF_RC3_8822B)
+#define BIT_CLEAR_RARF_RC3_8822B(x) ((x) & (~BITS_RARF_RC3_8822B))
+#define BIT_GET_RARF_RC3_8822B(x)                                              \
+	(((x) >> BIT_SHIFT_RARF_RC3_8822B) & BIT_MASK_RARF_RC3_8822B)
+#define BIT_SET_RARF_RC3_8822B(x, v)                                           \
+	(BIT_CLEAR_RARF_RC3_8822B(x) | BIT_RARF_RC3_8822B(v))
+
+#define BIT_SHIFT_RARF_RC2_8822B 8
+#define BIT_MASK_RARF_RC2_8822B 0x1f
+#define BIT_RARF_RC2_8822B(x)                                                  \
+	(((x) & BIT_MASK_RARF_RC2_8822B) << BIT_SHIFT_RARF_RC2_8822B)
+#define BITS_RARF_RC2_8822B                                                    \
+	(BIT_MASK_RARF_RC2_8822B << BIT_SHIFT_RARF_RC2_8822B)
+#define BIT_CLEAR_RARF_RC2_8822B(x) ((x) & (~BITS_RARF_RC2_8822B))
+#define BIT_GET_RARF_RC2_8822B(x)                                              \
+	(((x) >> BIT_SHIFT_RARF_RC2_8822B) & BIT_MASK_RARF_RC2_8822B)
+#define BIT_SET_RARF_RC2_8822B(x, v)                                           \
+	(BIT_CLEAR_RARF_RC2_8822B(x) | BIT_RARF_RC2_8822B(v))
+
+#define BIT_SHIFT_RARF_RC1_8822B 0
+#define BIT_MASK_RARF_RC1_8822B 0x1f
+#define BIT_RARF_RC1_8822B(x)                                                  \
+	(((x) & BIT_MASK_RARF_RC1_8822B) << BIT_SHIFT_RARF_RC1_8822B)
+#define BITS_RARF_RC1_8822B                                                    \
+	(BIT_MASK_RARF_RC1_8822B << BIT_SHIFT_RARF_RC1_8822B)
+#define BIT_CLEAR_RARF_RC1_8822B(x) ((x) & (~BITS_RARF_RC1_8822B))
+#define BIT_GET_RARF_RC1_8822B(x)                                              \
+	(((x) >> BIT_SHIFT_RARF_RC1_8822B) & BIT_MASK_RARF_RC1_8822B)
+#define BIT_SET_RARF_RC1_8822B(x, v)                                           \
+	(BIT_CLEAR_RARF_RC1_8822B(x) | BIT_RARF_RC1_8822B(v))
+
+/* 2 REG_RRSR_8822B */
+
+#define BIT_SHIFT_RRSR_RSC_8822B 21
+#define BIT_MASK_RRSR_RSC_8822B 0x3
+#define BIT_RRSR_RSC_8822B(x)                                                  \
+	(((x) & BIT_MASK_RRSR_RSC_8822B) << BIT_SHIFT_RRSR_RSC_8822B)
+#define BITS_RRSR_RSC_8822B                                                    \
+	(BIT_MASK_RRSR_RSC_8822B << BIT_SHIFT_RRSR_RSC_8822B)
+#define BIT_CLEAR_RRSR_RSC_8822B(x) ((x) & (~BITS_RRSR_RSC_8822B))
+#define BIT_GET_RRSR_RSC_8822B(x)                                              \
+	(((x) >> BIT_SHIFT_RRSR_RSC_8822B) & BIT_MASK_RRSR_RSC_8822B)
+#define BIT_SET_RRSR_RSC_8822B(x, v)                                           \
+	(BIT_CLEAR_RRSR_RSC_8822B(x) | BIT_RRSR_RSC_8822B(v))
+
+#define BIT_RRSR_BW_8822B BIT(20)
+
+#define BIT_SHIFT_RRSC_BITMAP_8822B 0
+#define BIT_MASK_RRSC_BITMAP_8822B 0xfffff
+#define BIT_RRSC_BITMAP_8822B(x)                                               \
+	(((x) & BIT_MASK_RRSC_BITMAP_8822B) << BIT_SHIFT_RRSC_BITMAP_8822B)
+#define BITS_RRSC_BITMAP_8822B                                                 \
+	(BIT_MASK_RRSC_BITMAP_8822B << BIT_SHIFT_RRSC_BITMAP_8822B)
+#define BIT_CLEAR_RRSC_BITMAP_8822B(x) ((x) & (~BITS_RRSC_BITMAP_8822B))
+#define BIT_GET_RRSC_BITMAP_8822B(x)                                           \
+	(((x) >> BIT_SHIFT_RRSC_BITMAP_8822B) & BIT_MASK_RRSC_BITMAP_8822B)
+#define BIT_SET_RRSC_BITMAP_8822B(x, v)                                        \
+	(BIT_CLEAR_RRSC_BITMAP_8822B(x) | BIT_RRSC_BITMAP_8822B(v))
+
+/* 2 REG_ARFR0_8822B */
+
+#define BIT_SHIFT_ARFR0_V1_8822B 0
+#define BIT_MASK_ARFR0_V1_8822B 0xffffffffffffffffL
+#define BIT_ARFR0_V1_8822B(x)                                                  \
+	(((x) & BIT_MASK_ARFR0_V1_8822B) << BIT_SHIFT_ARFR0_V1_8822B)
+#define BITS_ARFR0_V1_8822B                                                    \
+	(BIT_MASK_ARFR0_V1_8822B << BIT_SHIFT_ARFR0_V1_8822B)
+#define BIT_CLEAR_ARFR0_V1_8822B(x) ((x) & (~BITS_ARFR0_V1_8822B))
+#define BIT_GET_ARFR0_V1_8822B(x)                                              \
+	(((x) >> BIT_SHIFT_ARFR0_V1_8822B) & BIT_MASK_ARFR0_V1_8822B)
+#define BIT_SET_ARFR0_V1_8822B(x, v)                                           \
+	(BIT_CLEAR_ARFR0_V1_8822B(x) | BIT_ARFR0_V1_8822B(v))
+
+/* 2 REG_ARFR1_V1_8822B */
+
+#define BIT_SHIFT_ARFR1_V1_8822B 0
+#define BIT_MASK_ARFR1_V1_8822B 0xffffffffffffffffL
+#define BIT_ARFR1_V1_8822B(x)                                                  \
+	(((x) & BIT_MASK_ARFR1_V1_8822B) << BIT_SHIFT_ARFR1_V1_8822B)
+#define BITS_ARFR1_V1_8822B                                                    \
+	(BIT_MASK_ARFR1_V1_8822B << BIT_SHIFT_ARFR1_V1_8822B)
+#define BIT_CLEAR_ARFR1_V1_8822B(x) ((x) & (~BITS_ARFR1_V1_8822B))
+#define BIT_GET_ARFR1_V1_8822B(x)                                              \
+	(((x) >> BIT_SHIFT_ARFR1_V1_8822B) & BIT_MASK_ARFR1_V1_8822B)
+#define BIT_SET_ARFR1_V1_8822B(x, v)                                           \
+	(BIT_CLEAR_ARFR1_V1_8822B(x) | BIT_ARFR1_V1_8822B(v))
+
+/* 2 REG_CCK_CHECK_8822B */
+#define BIT_CHECK_CCK_EN_8822B BIT(7)
+#define BIT_EN_BCN_PKT_REL_8822B BIT(6)
+#define BIT_BCN_PORT_SEL_8822B BIT(5)
+#define BIT_MOREDATA_BYPASS_8822B BIT(4)
+#define BIT_EN_CLR_CMD_REL_BCN_PKT_8822B BIT(3)
+#define BIT_R_EN_SET_MOREDATA_8822B BIT(2)
+#define BIT__R_DIS_CLEAR_MACID_RELEASE_8822B BIT(1)
+#define BIT__R_MACID_RELEASE_EN_8822B BIT(0)
+
+/* 2 REG_AMPDU_MAX_TIME_V1_8822B */
+
+#define BIT_SHIFT_AMPDU_MAX_TIME_8822B 0
+#define BIT_MASK_AMPDU_MAX_TIME_8822B 0xff
+#define BIT_AMPDU_MAX_TIME_8822B(x)                                            \
+	(((x) & BIT_MASK_AMPDU_MAX_TIME_8822B)                                 \
+	 << BIT_SHIFT_AMPDU_MAX_TIME_8822B)
+#define BITS_AMPDU_MAX_TIME_8822B                                              \
+	(BIT_MASK_AMPDU_MAX_TIME_8822B << BIT_SHIFT_AMPDU_MAX_TIME_8822B)
+#define BIT_CLEAR_AMPDU_MAX_TIME_8822B(x) ((x) & (~BITS_AMPDU_MAX_TIME_8822B))
+#define BIT_GET_AMPDU_MAX_TIME_8822B(x)                                        \
+	(((x) >> BIT_SHIFT_AMPDU_MAX_TIME_8822B) &                             \
+	 BIT_MASK_AMPDU_MAX_TIME_8822B)
+#define BIT_SET_AMPDU_MAX_TIME_8822B(x, v)                                     \
+	(BIT_CLEAR_AMPDU_MAX_TIME_8822B(x) | BIT_AMPDU_MAX_TIME_8822B(v))
+
+/* 2 REG_BCNQ1_BDNY_V1_8822B */
+
+#define BIT_SHIFT_BCNQ1_PGBNDY_V1_8822B 0
+#define BIT_MASK_BCNQ1_PGBNDY_V1_8822B 0xfff
+#define BIT_BCNQ1_PGBNDY_V1_8822B(x)                                           \
+	(((x) & BIT_MASK_BCNQ1_PGBNDY_V1_8822B)                                \
+	 << BIT_SHIFT_BCNQ1_PGBNDY_V1_8822B)
+#define BITS_BCNQ1_PGBNDY_V1_8822B                                             \
+	(BIT_MASK_BCNQ1_PGBNDY_V1_8822B << BIT_SHIFT_BCNQ1_PGBNDY_V1_8822B)
+#define BIT_CLEAR_BCNQ1_PGBNDY_V1_8822B(x) ((x) & (~BITS_BCNQ1_PGBNDY_V1_8822B))
+#define BIT_GET_BCNQ1_PGBNDY_V1_8822B(x)                                       \
+	(((x) >> BIT_SHIFT_BCNQ1_PGBNDY_V1_8822B) &                            \
+	 BIT_MASK_BCNQ1_PGBNDY_V1_8822B)
+#define BIT_SET_BCNQ1_PGBNDY_V1_8822B(x, v)                                    \
+	(BIT_CLEAR_BCNQ1_PGBNDY_V1_8822B(x) | BIT_BCNQ1_PGBNDY_V1_8822B(v))
+
+/* 2 REG_AMPDU_MAX_LENGTH_8822B */
+
+#define BIT_SHIFT_AMPDU_MAX_LENGTH_8822B 0
+#define BIT_MASK_AMPDU_MAX_LENGTH_8822B 0xffffffffL
+#define BIT_AMPDU_MAX_LENGTH_8822B(x)                                          \
+	(((x) & BIT_MASK_AMPDU_MAX_LENGTH_8822B)                               \
+	 << BIT_SHIFT_AMPDU_MAX_LENGTH_8822B)
+#define BITS_AMPDU_MAX_LENGTH_8822B                                            \
+	(BIT_MASK_AMPDU_MAX_LENGTH_8822B << BIT_SHIFT_AMPDU_MAX_LENGTH_8822B)
+#define BIT_CLEAR_AMPDU_MAX_LENGTH_8822B(x)                                    \
+	((x) & (~BITS_AMPDU_MAX_LENGTH_8822B))
+#define BIT_GET_AMPDU_MAX_LENGTH_8822B(x)                                      \
+	(((x) >> BIT_SHIFT_AMPDU_MAX_LENGTH_8822B) &                           \
+	 BIT_MASK_AMPDU_MAX_LENGTH_8822B)
+#define BIT_SET_AMPDU_MAX_LENGTH_8822B(x, v)                                   \
+	(BIT_CLEAR_AMPDU_MAX_LENGTH_8822B(x) | BIT_AMPDU_MAX_LENGTH_8822B(v))
+
+/* 2 REG_ACQ_STOP_8822B */
+#define BIT_AC7Q_STOP_8822B BIT(7)
+#define BIT_AC6Q_STOP_8822B BIT(6)
+#define BIT_AC5Q_STOP_8822B BIT(5)
+#define BIT_AC4Q_STOP_8822B BIT(4)
+#define BIT_AC3Q_STOP_8822B BIT(3)
+#define BIT_AC2Q_STOP_8822B BIT(2)
+#define BIT_AC1Q_STOP_8822B BIT(1)
+#define BIT_AC0Q_STOP_8822B BIT(0)
+
+/* 2 REG_NDPA_RATE_8822B */
+
+#define BIT_SHIFT_R_NDPA_RATE_V1_8822B 0
+#define BIT_MASK_R_NDPA_RATE_V1_8822B 0xff
+#define BIT_R_NDPA_RATE_V1_8822B(x)                                            \
+	(((x) & BIT_MASK_R_NDPA_RATE_V1_8822B)                                 \
+	 << BIT_SHIFT_R_NDPA_RATE_V1_8822B)
+#define BITS_R_NDPA_RATE_V1_8822B                                              \
+	(BIT_MASK_R_NDPA_RATE_V1_8822B << BIT_SHIFT_R_NDPA_RATE_V1_8822B)
+#define BIT_CLEAR_R_NDPA_RATE_V1_8822B(x) ((x) & (~BITS_R_NDPA_RATE_V1_8822B))
+#define BIT_GET_R_NDPA_RATE_V1_8822B(x)                                        \
+	(((x) >> BIT_SHIFT_R_NDPA_RATE_V1_8822B) &                             \
+	 BIT_MASK_R_NDPA_RATE_V1_8822B)
+#define BIT_SET_R_NDPA_RATE_V1_8822B(x, v)                                     \
+	(BIT_CLEAR_R_NDPA_RATE_V1_8822B(x) | BIT_R_NDPA_RATE_V1_8822B(v))
+
+/* 2 REG_TX_HANG_CTRL_8822B */
+#define BIT_R_EN_GNT_BT_AWAKE_8822B BIT(3)
+#define BIT_EN_EOF_V1_8822B BIT(2)
+#define BIT_DIS_OQT_BLOCK_8822B BIT(1)
+#define BIT_SEARCH_QUEUE_EN_8822B BIT(0)
+
+/* 2 REG_NDPA_OPT_CTRL_8822B */
+#define BIT_R_DIS_MACID_RELEASE_RTY_8822B BIT(5)
+
+#define BIT_SHIFT_BW_SIGTA_8822B 3
+#define BIT_MASK_BW_SIGTA_8822B 0x3
+#define BIT_BW_SIGTA_8822B(x)                                                  \
+	(((x) & BIT_MASK_BW_SIGTA_8822B) << BIT_SHIFT_BW_SIGTA_8822B)
+#define BITS_BW_SIGTA_8822B                                                    \
+	(BIT_MASK_BW_SIGTA_8822B << BIT_SHIFT_BW_SIGTA_8822B)
+#define BIT_CLEAR_BW_SIGTA_8822B(x) ((x) & (~BITS_BW_SIGTA_8822B))
+#define BIT_GET_BW_SIGTA_8822B(x)                                              \
+	(((x) >> BIT_SHIFT_BW_SIGTA_8822B) & BIT_MASK_BW_SIGTA_8822B)
+#define BIT_SET_BW_SIGTA_8822B(x, v)                                           \
+	(BIT_CLEAR_BW_SIGTA_8822B(x) | BIT_BW_SIGTA_8822B(v))
+
+#define BIT_EN_BAR_SIGTA_8822B BIT(2)
+
+#define BIT_SHIFT_R_NDPA_BW_8822B 0
+#define BIT_MASK_R_NDPA_BW_8822B 0x3
+#define BIT_R_NDPA_BW_8822B(x)                                                 \
+	(((x) & BIT_MASK_R_NDPA_BW_8822B) << BIT_SHIFT_R_NDPA_BW_8822B)
+#define BITS_R_NDPA_BW_8822B                                                   \
+	(BIT_MASK_R_NDPA_BW_8822B << BIT_SHIFT_R_NDPA_BW_8822B)
+#define BIT_CLEAR_R_NDPA_BW_8822B(x) ((x) & (~BITS_R_NDPA_BW_8822B))
+#define BIT_GET_R_NDPA_BW_8822B(x)                                             \
+	(((x) >> BIT_SHIFT_R_NDPA_BW_8822B) & BIT_MASK_R_NDPA_BW_8822B)
+#define BIT_SET_R_NDPA_BW_8822B(x, v)                                          \
+	(BIT_CLEAR_R_NDPA_BW_8822B(x) | BIT_R_NDPA_BW_8822B(v))
+
+/* 2 REG_RD_RESP_PKT_TH_8822B */
+
+#define BIT_SHIFT_RD_RESP_PKT_TH_V1_8822B 0
+#define BIT_MASK_RD_RESP_PKT_TH_V1_8822B 0x3f
+#define BIT_RD_RESP_PKT_TH_V1_8822B(x)                                         \
+	(((x) & BIT_MASK_RD_RESP_PKT_TH_V1_8822B)                              \
+	 << BIT_SHIFT_RD_RESP_PKT_TH_V1_8822B)
+#define BITS_RD_RESP_PKT_TH_V1_8822B                                           \
+	(BIT_MASK_RD_RESP_PKT_TH_V1_8822B << BIT_SHIFT_RD_RESP_PKT_TH_V1_8822B)
+#define BIT_CLEAR_RD_RESP_PKT_TH_V1_8822B(x)                                   \
+	((x) & (~BITS_RD_RESP_PKT_TH_V1_8822B))
+#define BIT_GET_RD_RESP_PKT_TH_V1_8822B(x)                                     \
+	(((x) >> BIT_SHIFT_RD_RESP_PKT_TH_V1_8822B) &                          \
+	 BIT_MASK_RD_RESP_PKT_TH_V1_8822B)
+#define BIT_SET_RD_RESP_PKT_TH_V1_8822B(x, v)                                  \
+	(BIT_CLEAR_RD_RESP_PKT_TH_V1_8822B(x) | BIT_RD_RESP_PKT_TH_V1_8822B(v))
+
+/* 2 REG_CMDQ_INFO_8822B */
+
+#define BIT_SHIFT_QUEUEMACID_CMDQ_V1_8822B 25
+#define BIT_MASK_QUEUEMACID_CMDQ_V1_8822B 0x7f
+#define BIT_QUEUEMACID_CMDQ_V1_8822B(x)                                        \
+	(((x) & BIT_MASK_QUEUEMACID_CMDQ_V1_8822B)                             \
+	 << BIT_SHIFT_QUEUEMACID_CMDQ_V1_8822B)
+#define BITS_QUEUEMACID_CMDQ_V1_8822B                                          \
+	(BIT_MASK_QUEUEMACID_CMDQ_V1_8822B                                     \
+	 << BIT_SHIFT_QUEUEMACID_CMDQ_V1_8822B)
+#define BIT_CLEAR_QUEUEMACID_CMDQ_V1_8822B(x)                                  \
+	((x) & (~BITS_QUEUEMACID_CMDQ_V1_8822B))
+#define BIT_GET_QUEUEMACID_CMDQ_V1_8822B(x)                                    \
+	(((x) >> BIT_SHIFT_QUEUEMACID_CMDQ_V1_8822B) &                         \
+	 BIT_MASK_QUEUEMACID_CMDQ_V1_8822B)
+#define BIT_SET_QUEUEMACID_CMDQ_V1_8822B(x, v)                                 \
+	(BIT_CLEAR_QUEUEMACID_CMDQ_V1_8822B(x) |                               \
+	 BIT_QUEUEMACID_CMDQ_V1_8822B(v))
+
+#define BIT_SHIFT_QUEUEAC_CMDQ_V1_8822B 23
+#define BIT_MASK_QUEUEAC_CMDQ_V1_8822B 0x3
+#define BIT_QUEUEAC_CMDQ_V1_8822B(x)                                           \
+	(((x) & BIT_MASK_QUEUEAC_CMDQ_V1_8822B)                                \
+	 << BIT_SHIFT_QUEUEAC_CMDQ_V1_8822B)
+#define BITS_QUEUEAC_CMDQ_V1_8822B                                             \
+	(BIT_MASK_QUEUEAC_CMDQ_V1_8822B << BIT_SHIFT_QUEUEAC_CMDQ_V1_8822B)
+#define BIT_CLEAR_QUEUEAC_CMDQ_V1_8822B(x) ((x) & (~BITS_QUEUEAC_CMDQ_V1_8822B))
+#define BIT_GET_QUEUEAC_CMDQ_V1_8822B(x)                                       \
+	(((x) >> BIT_SHIFT_QUEUEAC_CMDQ_V1_8822B) &                            \
+	 BIT_MASK_QUEUEAC_CMDQ_V1_8822B)
+#define BIT_SET_QUEUEAC_CMDQ_V1_8822B(x, v)                                    \
+	(BIT_CLEAR_QUEUEAC_CMDQ_V1_8822B(x) | BIT_QUEUEAC_CMDQ_V1_8822B(v))
+
+#define BIT_TIDEMPTY_CMDQ_V1_8822B BIT(22)
+
+#define BIT_SHIFT_TAIL_PKT_CMDQ_V2_8822B 11
+#define BIT_MASK_TAIL_PKT_CMDQ_V2_8822B 0x7ff
+#define BIT_TAIL_PKT_CMDQ_V2_8822B(x)                                          \
+	(((x) & BIT_MASK_TAIL_PKT_CMDQ_V2_8822B)                               \
+	 << BIT_SHIFT_TAIL_PKT_CMDQ_V2_8822B)
+#define BITS_TAIL_PKT_CMDQ_V2_8822B                                            \
+	(BIT_MASK_TAIL_PKT_CMDQ_V2_8822B << BIT_SHIFT_TAIL_PKT_CMDQ_V2_8822B)
+#define BIT_CLEAR_TAIL_PKT_CMDQ_V2_8822B(x)                                    \
+	((x) & (~BITS_TAIL_PKT_CMDQ_V2_8822B))
+#define BIT_GET_TAIL_PKT_CMDQ_V2_8822B(x)                                      \
+	(((x) >> BIT_SHIFT_TAIL_PKT_CMDQ_V2_8822B) &                           \
+	 BIT_MASK_TAIL_PKT_CMDQ_V2_8822B)
+#define BIT_SET_TAIL_PKT_CMDQ_V2_8822B(x, v)                                   \
+	(BIT_CLEAR_TAIL_PKT_CMDQ_V2_8822B(x) | BIT_TAIL_PKT_CMDQ_V2_8822B(v))
+
+#define BIT_SHIFT_HEAD_PKT_CMDQ_V1_8822B 0
+#define BIT_MASK_HEAD_PKT_CMDQ_V1_8822B 0x7ff
+#define BIT_HEAD_PKT_CMDQ_V1_8822B(x)                                          \
+	(((x) & BIT_MASK_HEAD_PKT_CMDQ_V1_8822B)                               \
+	 << BIT_SHIFT_HEAD_PKT_CMDQ_V1_8822B)
+#define BITS_HEAD_PKT_CMDQ_V1_8822B                                            \
+	(BIT_MASK_HEAD_PKT_CMDQ_V1_8822B << BIT_SHIFT_HEAD_PKT_CMDQ_V1_8822B)
+#define BIT_CLEAR_HEAD_PKT_CMDQ_V1_8822B(x)                                    \
+	((x) & (~BITS_HEAD_PKT_CMDQ_V1_8822B))
+#define BIT_GET_HEAD_PKT_CMDQ_V1_8822B(x)                                      \
+	(((x) >> BIT_SHIFT_HEAD_PKT_CMDQ_V1_8822B) &                           \
+	 BIT_MASK_HEAD_PKT_CMDQ_V1_8822B)
+#define BIT_SET_HEAD_PKT_CMDQ_V1_8822B(x, v)                                   \
+	(BIT_CLEAR_HEAD_PKT_CMDQ_V1_8822B(x) | BIT_HEAD_PKT_CMDQ_V1_8822B(v))
+
+/* 2 REG_Q4_INFO_8822B */
+
+#define BIT_SHIFT_QUEUEMACID_Q4_V1_8822B 25
+#define BIT_MASK_QUEUEMACID_Q4_V1_8822B 0x7f
+#define BIT_QUEUEMACID_Q4_V1_8822B(x)                                          \
+	(((x) & BIT_MASK_QUEUEMACID_Q4_V1_8822B)                               \
+	 << BIT_SHIFT_QUEUEMACID_Q4_V1_8822B)
+#define BITS_QUEUEMACID_Q4_V1_8822B                                            \
+	(BIT_MASK_QUEUEMACID_Q4_V1_8822B << BIT_SHIFT_QUEUEMACID_Q4_V1_8822B)
+#define BIT_CLEAR_QUEUEMACID_Q4_V1_8822B(x)                                    \
+	((x) & (~BITS_QUEUEMACID_Q4_V1_8822B))
+#define BIT_GET_QUEUEMACID_Q4_V1_8822B(x)                                      \
+	(((x) >> BIT_SHIFT_QUEUEMACID_Q4_V1_8822B) &                           \
+	 BIT_MASK_QUEUEMACID_Q4_V1_8822B)
+#define BIT_SET_QUEUEMACID_Q4_V1_8822B(x, v)                                   \
+	(BIT_CLEAR_QUEUEMACID_Q4_V1_8822B(x) | BIT_QUEUEMACID_Q4_V1_8822B(v))
+
+#define BIT_SHIFT_QUEUEAC_Q4_V1_8822B 23
+#define BIT_MASK_QUEUEAC_Q4_V1_8822B 0x3
+#define BIT_QUEUEAC_Q4_V1_8822B(x)                                             \
+	(((x) & BIT_MASK_QUEUEAC_Q4_V1_8822B) << BIT_SHIFT_QUEUEAC_Q4_V1_8822B)
+#define BITS_QUEUEAC_Q4_V1_8822B                                               \
+	(BIT_MASK_QUEUEAC_Q4_V1_8822B << BIT_SHIFT_QUEUEAC_Q4_V1_8822B)
+#define BIT_CLEAR_QUEUEAC_Q4_V1_8822B(x) ((x) & (~BITS_QUEUEAC_Q4_V1_8822B))
+#define BIT_GET_QUEUEAC_Q4_V1_8822B(x)                                         \
+	(((x) >> BIT_SHIFT_QUEUEAC_Q4_V1_8822B) & BIT_MASK_QUEUEAC_Q4_V1_8822B)
+#define BIT_SET_QUEUEAC_Q4_V1_8822B(x, v)                                      \
+	(BIT_CLEAR_QUEUEAC_Q4_V1_8822B(x) | BIT_QUEUEAC_Q4_V1_8822B(v))
+
+#define BIT_TIDEMPTY_Q4_V1_8822B BIT(22)
+
+#define BIT_SHIFT_TAIL_PKT_Q4_V2_8822B 11
+#define BIT_MASK_TAIL_PKT_Q4_V2_8822B 0x7ff
+#define BIT_TAIL_PKT_Q4_V2_8822B(x)                                            \
+	(((x) & BIT_MASK_TAIL_PKT_Q4_V2_8822B)                                 \
+	 << BIT_SHIFT_TAIL_PKT_Q4_V2_8822B)
+#define BITS_TAIL_PKT_Q4_V2_8822B                                              \
+	(BIT_MASK_TAIL_PKT_Q4_V2_8822B << BIT_SHIFT_TAIL_PKT_Q4_V2_8822B)
+#define BIT_CLEAR_TAIL_PKT_Q4_V2_8822B(x) ((x) & (~BITS_TAIL_PKT_Q4_V2_8822B))
+#define BIT_GET_TAIL_PKT_Q4_V2_8822B(x)                                        \
+	(((x) >> BIT_SHIFT_TAIL_PKT_Q4_V2_8822B) &                             \
+	 BIT_MASK_TAIL_PKT_Q4_V2_8822B)
+#define BIT_SET_TAIL_PKT_Q4_V2_8822B(x, v)                                     \
+	(BIT_CLEAR_TAIL_PKT_Q4_V2_8822B(x) | BIT_TAIL_PKT_Q4_V2_8822B(v))
+
+#define BIT_SHIFT_HEAD_PKT_Q4_V1_8822B 0
+#define BIT_MASK_HEAD_PKT_Q4_V1_8822B 0x7ff
+#define BIT_HEAD_PKT_Q4_V1_8822B(x)                                            \
+	(((x) & BIT_MASK_HEAD_PKT_Q4_V1_8822B)                                 \
+	 << BIT_SHIFT_HEAD_PKT_Q4_V1_8822B)
+#define BITS_HEAD_PKT_Q4_V1_8822B                                              \
+	(BIT_MASK_HEAD_PKT_Q4_V1_8822B << BIT_SHIFT_HEAD_PKT_Q4_V1_8822B)
+#define BIT_CLEAR_HEAD_PKT_Q4_V1_8822B(x) ((x) & (~BITS_HEAD_PKT_Q4_V1_8822B))
+#define BIT_GET_HEAD_PKT_Q4_V1_8822B(x)                                        \
+	(((x) >> BIT_SHIFT_HEAD_PKT_Q4_V1_8822B) &                             \
+	 BIT_MASK_HEAD_PKT_Q4_V1_8822B)
+#define BIT_SET_HEAD_PKT_Q4_V1_8822B(x, v)                                     \
+	(BIT_CLEAR_HEAD_PKT_Q4_V1_8822B(x) | BIT_HEAD_PKT_Q4_V1_8822B(v))
+
+/* 2 REG_Q5_INFO_8822B */
+
+#define BIT_SHIFT_QUEUEMACID_Q5_V1_8822B 25
+#define BIT_MASK_QUEUEMACID_Q5_V1_8822B 0x7f
+#define BIT_QUEUEMACID_Q5_V1_8822B(x)                                          \
+	(((x) & BIT_MASK_QUEUEMACID_Q5_V1_8822B)                               \
+	 << BIT_SHIFT_QUEUEMACID_Q5_V1_8822B)
+#define BITS_QUEUEMACID_Q5_V1_8822B                                            \
+	(BIT_MASK_QUEUEMACID_Q5_V1_8822B << BIT_SHIFT_QUEUEMACID_Q5_V1_8822B)
+#define BIT_CLEAR_QUEUEMACID_Q5_V1_8822B(x)                                    \
+	((x) & (~BITS_QUEUEMACID_Q5_V1_8822B))
+#define BIT_GET_QUEUEMACID_Q5_V1_8822B(x)                                      \
+	(((x) >> BIT_SHIFT_QUEUEMACID_Q5_V1_8822B) &                           \
+	 BIT_MASK_QUEUEMACID_Q5_V1_8822B)
+#define BIT_SET_QUEUEMACID_Q5_V1_8822B(x, v)                                   \
+	(BIT_CLEAR_QUEUEMACID_Q5_V1_8822B(x) | BIT_QUEUEMACID_Q5_V1_8822B(v))
+
+#define BIT_SHIFT_QUEUEAC_Q5_V1_8822B 23
+#define BIT_MASK_QUEUEAC_Q5_V1_8822B 0x3
+#define BIT_QUEUEAC_Q5_V1_8822B(x)                                             \
+	(((x) & BIT_MASK_QUEUEAC_Q5_V1_8822B) << BIT_SHIFT_QUEUEAC_Q5_V1_8822B)
+#define BITS_QUEUEAC_Q5_V1_8822B                                               \
+	(BIT_MASK_QUEUEAC_Q5_V1_8822B << BIT_SHIFT_QUEUEAC_Q5_V1_8822B)
+#define BIT_CLEAR_QUEUEAC_Q5_V1_8822B(x) ((x) & (~BITS_QUEUEAC_Q5_V1_8822B))
+#define BIT_GET_QUEUEAC_Q5_V1_8822B(x)                                         \
+	(((x) >> BIT_SHIFT_QUEUEAC_Q5_V1_8822B) & BIT_MASK_QUEUEAC_Q5_V1_8822B)
+#define BIT_SET_QUEUEAC_Q5_V1_8822B(x, v)                                      \
+	(BIT_CLEAR_QUEUEAC_Q5_V1_8822B(x) | BIT_QUEUEAC_Q5_V1_8822B(v))
+
+#define BIT_TIDEMPTY_Q5_V1_8822B BIT(22)
+
+#define BIT_SHIFT_TAIL_PKT_Q5_V2_8822B 11
+#define BIT_MASK_TAIL_PKT_Q5_V2_8822B 0x7ff
+#define BIT_TAIL_PKT_Q5_V2_8822B(x)                                            \
+	(((x) & BIT_MASK_TAIL_PKT_Q5_V2_8822B)                                 \
+	 << BIT_SHIFT_TAIL_PKT_Q5_V2_8822B)
+#define BITS_TAIL_PKT_Q5_V2_8822B                                              \
+	(BIT_MASK_TAIL_PKT_Q5_V2_8822B << BIT_SHIFT_TAIL_PKT_Q5_V2_8822B)
+#define BIT_CLEAR_TAIL_PKT_Q5_V2_8822B(x) ((x) & (~BITS_TAIL_PKT_Q5_V2_8822B))
+#define BIT_GET_TAIL_PKT_Q5_V2_8822B(x)                                        \
+	(((x) >> BIT_SHIFT_TAIL_PKT_Q5_V2_8822B) &                             \
+	 BIT_MASK_TAIL_PKT_Q5_V2_8822B)
+#define BIT_SET_TAIL_PKT_Q5_V2_8822B(x, v)                                     \
+	(BIT_CLEAR_TAIL_PKT_Q5_V2_8822B(x) | BIT_TAIL_PKT_Q5_V2_8822B(v))
+
+#define BIT_SHIFT_HEAD_PKT_Q5_V1_8822B 0
+#define BIT_MASK_HEAD_PKT_Q5_V1_8822B 0x7ff
+#define BIT_HEAD_PKT_Q5_V1_8822B(x)                                            \
+	(((x) & BIT_MASK_HEAD_PKT_Q5_V1_8822B)                                 \
+	 << BIT_SHIFT_HEAD_PKT_Q5_V1_8822B)
+#define BITS_HEAD_PKT_Q5_V1_8822B                                              \
+	(BIT_MASK_HEAD_PKT_Q5_V1_8822B << BIT_SHIFT_HEAD_PKT_Q5_V1_8822B)
+#define BIT_CLEAR_HEAD_PKT_Q5_V1_8822B(x) ((x) & (~BITS_HEAD_PKT_Q5_V1_8822B))
+#define BIT_GET_HEAD_PKT_Q5_V1_8822B(x)                                        \
+	(((x) >> BIT_SHIFT_HEAD_PKT_Q5_V1_8822B) &                             \
+	 BIT_MASK_HEAD_PKT_Q5_V1_8822B)
+#define BIT_SET_HEAD_PKT_Q5_V1_8822B(x, v)                                     \
+	(BIT_CLEAR_HEAD_PKT_Q5_V1_8822B(x) | BIT_HEAD_PKT_Q5_V1_8822B(v))
+
+/* 2 REG_Q6_INFO_8822B */
+
+#define BIT_SHIFT_QUEUEMACID_Q6_V1_8822B 25
+#define BIT_MASK_QUEUEMACID_Q6_V1_8822B 0x7f
+#define BIT_QUEUEMACID_Q6_V1_8822B(x)                                          \
+	(((x) & BIT_MASK_QUEUEMACID_Q6_V1_8822B)                               \
+	 << BIT_SHIFT_QUEUEMACID_Q6_V1_8822B)
+#define BITS_QUEUEMACID_Q6_V1_8822B                                            \
+	(BIT_MASK_QUEUEMACID_Q6_V1_8822B << BIT_SHIFT_QUEUEMACID_Q6_V1_8822B)
+#define BIT_CLEAR_QUEUEMACID_Q6_V1_8822B(x)                                    \
+	((x) & (~BITS_QUEUEMACID_Q6_V1_8822B))
+#define BIT_GET_QUEUEMACID_Q6_V1_8822B(x)                                      \
+	(((x) >> BIT_SHIFT_QUEUEMACID_Q6_V1_8822B) &                           \
+	 BIT_MASK_QUEUEMACID_Q6_V1_8822B)
+#define BIT_SET_QUEUEMACID_Q6_V1_8822B(x, v)                                   \
+	(BIT_CLEAR_QUEUEMACID_Q6_V1_8822B(x) | BIT_QUEUEMACID_Q6_V1_8822B(v))
+
+#define BIT_SHIFT_QUEUEAC_Q6_V1_8822B 23
+#define BIT_MASK_QUEUEAC_Q6_V1_8822B 0x3
+#define BIT_QUEUEAC_Q6_V1_8822B(x)                                             \
+	(((x) & BIT_MASK_QUEUEAC_Q6_V1_8822B) << BIT_SHIFT_QUEUEAC_Q6_V1_8822B)
+#define BITS_QUEUEAC_Q6_V1_8822B                                               \
+	(BIT_MASK_QUEUEAC_Q6_V1_8822B << BIT_SHIFT_QUEUEAC_Q6_V1_8822B)
+#define BIT_CLEAR_QUEUEAC_Q6_V1_8822B(x) ((x) & (~BITS_QUEUEAC_Q6_V1_8822B))
+#define BIT_GET_QUEUEAC_Q6_V1_8822B(x)                                         \
+	(((x) >> BIT_SHIFT_QUEUEAC_Q6_V1_8822B) & BIT_MASK_QUEUEAC_Q6_V1_8822B)
+#define BIT_SET_QUEUEAC_Q6_V1_8822B(x, v)                                      \
+	(BIT_CLEAR_QUEUEAC_Q6_V1_8822B(x) | BIT_QUEUEAC_Q6_V1_8822B(v))
+
+#define BIT_TIDEMPTY_Q6_V1_8822B BIT(22)
+
+#define BIT_SHIFT_TAIL_PKT_Q6_V2_8822B 11
+#define BIT_MASK_TAIL_PKT_Q6_V2_8822B 0x7ff
+#define BIT_TAIL_PKT_Q6_V2_8822B(x)                                            \
+	(((x) & BIT_MASK_TAIL_PKT_Q6_V2_8822B)                                 \
+	 << BIT_SHIFT_TAIL_PKT_Q6_V2_8822B)
+#define BITS_TAIL_PKT_Q6_V2_8822B                                              \
+	(BIT_MASK_TAIL_PKT_Q6_V2_8822B << BIT_SHIFT_TAIL_PKT_Q6_V2_8822B)
+#define BIT_CLEAR_TAIL_PKT_Q6_V2_8822B(x) ((x) & (~BITS_TAIL_PKT_Q6_V2_8822B))
+#define BIT_GET_TAIL_PKT_Q6_V2_8822B(x)                                        \
+	(((x) >> BIT_SHIFT_TAIL_PKT_Q6_V2_8822B) &                             \
+	 BIT_MASK_TAIL_PKT_Q6_V2_8822B)
+#define BIT_SET_TAIL_PKT_Q6_V2_8822B(x, v)                                     \
+	(BIT_CLEAR_TAIL_PKT_Q6_V2_8822B(x) | BIT_TAIL_PKT_Q6_V2_8822B(v))
+
+#define BIT_SHIFT_HEAD_PKT_Q6_V1_8822B 0
+#define BIT_MASK_HEAD_PKT_Q6_V1_8822B 0x7ff
+#define BIT_HEAD_PKT_Q6_V1_8822B(x)                                            \
+	(((x) & BIT_MASK_HEAD_PKT_Q6_V1_8822B)                                 \
+	 << BIT_SHIFT_HEAD_PKT_Q6_V1_8822B)
+#define BITS_HEAD_PKT_Q6_V1_8822B                                              \
+	(BIT_MASK_HEAD_PKT_Q6_V1_8822B << BIT_SHIFT_HEAD_PKT_Q6_V1_8822B)
+#define BIT_CLEAR_HEAD_PKT_Q6_V1_8822B(x) ((x) & (~BITS_HEAD_PKT_Q6_V1_8822B))
+#define BIT_GET_HEAD_PKT_Q6_V1_8822B(x)                                        \
+	(((x) >> BIT_SHIFT_HEAD_PKT_Q6_V1_8822B) &                             \
+	 BIT_MASK_HEAD_PKT_Q6_V1_8822B)
+#define BIT_SET_HEAD_PKT_Q6_V1_8822B(x, v)                                     \
+	(BIT_CLEAR_HEAD_PKT_Q6_V1_8822B(x) | BIT_HEAD_PKT_Q6_V1_8822B(v))
+
+/* 2 REG_Q7_INFO_8822B */
+
+#define BIT_SHIFT_QUEUEMACID_Q7_V1_8822B 25
+#define BIT_MASK_QUEUEMACID_Q7_V1_8822B 0x7f
+#define BIT_QUEUEMACID_Q7_V1_8822B(x)                                          \
+	(((x) & BIT_MASK_QUEUEMACID_Q7_V1_8822B)                               \
+	 << BIT_SHIFT_QUEUEMACID_Q7_V1_8822B)
+#define BITS_QUEUEMACID_Q7_V1_8822B                                            \
+	(BIT_MASK_QUEUEMACID_Q7_V1_8822B << BIT_SHIFT_QUEUEMACID_Q7_V1_8822B)
+#define BIT_CLEAR_QUEUEMACID_Q7_V1_8822B(x)                                    \
+	((x) & (~BITS_QUEUEMACID_Q7_V1_8822B))
+#define BIT_GET_QUEUEMACID_Q7_V1_8822B(x)                                      \
+	(((x) >> BIT_SHIFT_QUEUEMACID_Q7_V1_8822B) &                           \
+	 BIT_MASK_QUEUEMACID_Q7_V1_8822B)
+#define BIT_SET_QUEUEMACID_Q7_V1_8822B(x, v)                                   \
+	(BIT_CLEAR_QUEUEMACID_Q7_V1_8822B(x) | BIT_QUEUEMACID_Q7_V1_8822B(v))
+
+#define BIT_SHIFT_QUEUEAC_Q7_V1_8822B 23
+#define BIT_MASK_QUEUEAC_Q7_V1_8822B 0x3
+#define BIT_QUEUEAC_Q7_V1_8822B(x)                                             \
+	(((x) & BIT_MASK_QUEUEAC_Q7_V1_8822B) << BIT_SHIFT_QUEUEAC_Q7_V1_8822B)
+#define BITS_QUEUEAC_Q7_V1_8822B                                               \
+	(BIT_MASK_QUEUEAC_Q7_V1_8822B << BIT_SHIFT_QUEUEAC_Q7_V1_8822B)
+#define BIT_CLEAR_QUEUEAC_Q7_V1_8822B(x) ((x) & (~BITS_QUEUEAC_Q7_V1_8822B))
+#define BIT_GET_QUEUEAC_Q7_V1_8822B(x)                                         \
+	(((x) >> BIT_SHIFT_QUEUEAC_Q7_V1_8822B) & BIT_MASK_QUEUEAC_Q7_V1_8822B)
+#define BIT_SET_QUEUEAC_Q7_V1_8822B(x, v)                                      \
+	(BIT_CLEAR_QUEUEAC_Q7_V1_8822B(x) | BIT_QUEUEAC_Q7_V1_8822B(v))
+
+#define BIT_TIDEMPTY_Q7_V1_8822B BIT(22)
+
+#define BIT_SHIFT_TAIL_PKT_Q7_V2_8822B 11
+#define BIT_MASK_TAIL_PKT_Q7_V2_8822B 0x7ff
+#define BIT_TAIL_PKT_Q7_V2_8822B(x)                                            \
+	(((x) & BIT_MASK_TAIL_PKT_Q7_V2_8822B)                                 \
+	 << BIT_SHIFT_TAIL_PKT_Q7_V2_8822B)
+#define BITS_TAIL_PKT_Q7_V2_8822B                                              \
+	(BIT_MASK_TAIL_PKT_Q7_V2_8822B << BIT_SHIFT_TAIL_PKT_Q7_V2_8822B)
+#define BIT_CLEAR_TAIL_PKT_Q7_V2_8822B(x) ((x) & (~BITS_TAIL_PKT_Q7_V2_8822B))
+#define BIT_GET_TAIL_PKT_Q7_V2_8822B(x)                                        \
+	(((x) >> BIT_SHIFT_TAIL_PKT_Q7_V2_8822B) &                             \
+	 BIT_MASK_TAIL_PKT_Q7_V2_8822B)
+#define BIT_SET_TAIL_PKT_Q7_V2_8822B(x, v)                                     \
+	(BIT_CLEAR_TAIL_PKT_Q7_V2_8822B(x) | BIT_TAIL_PKT_Q7_V2_8822B(v))
+
+#define BIT_SHIFT_HEAD_PKT_Q7_V1_8822B 0
+#define BIT_MASK_HEAD_PKT_Q7_V1_8822B 0x7ff
+#define BIT_HEAD_PKT_Q7_V1_8822B(x)                                            \
+	(((x) & BIT_MASK_HEAD_PKT_Q7_V1_8822B)                                 \
+	 << BIT_SHIFT_HEAD_PKT_Q7_V1_8822B)
+#define BITS_HEAD_PKT_Q7_V1_8822B                                              \
+	(BIT_MASK_HEAD_PKT_Q7_V1_8822B << BIT_SHIFT_HEAD_PKT_Q7_V1_8822B)
+#define BIT_CLEAR_HEAD_PKT_Q7_V1_8822B(x) ((x) & (~BITS_HEAD_PKT_Q7_V1_8822B))
+#define BIT_GET_HEAD_PKT_Q7_V1_8822B(x)                                        \
+	(((x) >> BIT_SHIFT_HEAD_PKT_Q7_V1_8822B) &                             \
+	 BIT_MASK_HEAD_PKT_Q7_V1_8822B)
+#define BIT_SET_HEAD_PKT_Q7_V1_8822B(x, v)                                     \
+	(BIT_CLEAR_HEAD_PKT_Q7_V1_8822B(x) | BIT_HEAD_PKT_Q7_V1_8822B(v))
+
+/* 2 REG_WMAC_LBK_BUF_HD_V1_8822B */
+
+#define BIT_SHIFT_WMAC_LBK_BUF_HEAD_V1_8822B 0
+#define BIT_MASK_WMAC_LBK_BUF_HEAD_V1_8822B 0xfff
+#define BIT_WMAC_LBK_BUF_HEAD_V1_8822B(x)                                      \
+	(((x) & BIT_MASK_WMAC_LBK_BUF_HEAD_V1_8822B)                           \
+	 << BIT_SHIFT_WMAC_LBK_BUF_HEAD_V1_8822B)
+#define BITS_WMAC_LBK_BUF_HEAD_V1_8822B                                        \
+	(BIT_MASK_WMAC_LBK_BUF_HEAD_V1_8822B                                   \
+	 << BIT_SHIFT_WMAC_LBK_BUF_HEAD_V1_8822B)
+#define BIT_CLEAR_WMAC_LBK_BUF_HEAD_V1_8822B(x)                                \
+	((x) & (~BITS_WMAC_LBK_BUF_HEAD_V1_8822B))
+#define BIT_GET_WMAC_LBK_BUF_HEAD_V1_8822B(x)                                  \
+	(((x) >> BIT_SHIFT_WMAC_LBK_BUF_HEAD_V1_8822B) &                       \
+	 BIT_MASK_WMAC_LBK_BUF_HEAD_V1_8822B)
+#define BIT_SET_WMAC_LBK_BUF_HEAD_V1_8822B(x, v)                               \
+	(BIT_CLEAR_WMAC_LBK_BUF_HEAD_V1_8822B(x) |                             \
+	 BIT_WMAC_LBK_BUF_HEAD_V1_8822B(v))
+
+/* 2 REG_MGQ_BDNY_V1_8822B */
+
+#define BIT_SHIFT_MGQ_PGBNDY_V1_8822B 0
+#define BIT_MASK_MGQ_PGBNDY_V1_8822B 0xfff
+#define BIT_MGQ_PGBNDY_V1_8822B(x)                                             \
+	(((x) & BIT_MASK_MGQ_PGBNDY_V1_8822B) << BIT_SHIFT_MGQ_PGBNDY_V1_8822B)
+#define BITS_MGQ_PGBNDY_V1_8822B                                               \
+	(BIT_MASK_MGQ_PGBNDY_V1_8822B << BIT_SHIFT_MGQ_PGBNDY_V1_8822B)
+#define BIT_CLEAR_MGQ_PGBNDY_V1_8822B(x) ((x) & (~BITS_MGQ_PGBNDY_V1_8822B))
+#define BIT_GET_MGQ_PGBNDY_V1_8822B(x)                                         \
+	(((x) >> BIT_SHIFT_MGQ_PGBNDY_V1_8822B) & BIT_MASK_MGQ_PGBNDY_V1_8822B)
+#define BIT_SET_MGQ_PGBNDY_V1_8822B(x, v)                                      \
+	(BIT_CLEAR_MGQ_PGBNDY_V1_8822B(x) | BIT_MGQ_PGBNDY_V1_8822B(v))
+
+/* 2 REG_TXRPT_CTRL_8822B */
+
+#define BIT_SHIFT_TRXRPT_TIMER_TH_8822B 24
+#define BIT_MASK_TRXRPT_TIMER_TH_8822B 0xff
+#define BIT_TRXRPT_TIMER_TH_8822B(x)                                           \
+	(((x) & BIT_MASK_TRXRPT_TIMER_TH_8822B)                                \
+	 << BIT_SHIFT_TRXRPT_TIMER_TH_8822B)
+#define BITS_TRXRPT_TIMER_TH_8822B                                             \
+	(BIT_MASK_TRXRPT_TIMER_TH_8822B << BIT_SHIFT_TRXRPT_TIMER_TH_8822B)
+#define BIT_CLEAR_TRXRPT_TIMER_TH_8822B(x) ((x) & (~BITS_TRXRPT_TIMER_TH_8822B))
+#define BIT_GET_TRXRPT_TIMER_TH_8822B(x)                                       \
+	(((x) >> BIT_SHIFT_TRXRPT_TIMER_TH_8822B) &                            \
+	 BIT_MASK_TRXRPT_TIMER_TH_8822B)
+#define BIT_SET_TRXRPT_TIMER_TH_8822B(x, v)                                    \
+	(BIT_CLEAR_TRXRPT_TIMER_TH_8822B(x) | BIT_TRXRPT_TIMER_TH_8822B(v))
+
+#define BIT_SHIFT_TRXRPT_LEN_TH_8822B 16
+#define BIT_MASK_TRXRPT_LEN_TH_8822B 0xff
+#define BIT_TRXRPT_LEN_TH_8822B(x)                                             \
+	(((x) & BIT_MASK_TRXRPT_LEN_TH_8822B) << BIT_SHIFT_TRXRPT_LEN_TH_8822B)
+#define BITS_TRXRPT_LEN_TH_8822B                                               \
+	(BIT_MASK_TRXRPT_LEN_TH_8822B << BIT_SHIFT_TRXRPT_LEN_TH_8822B)
+#define BIT_CLEAR_TRXRPT_LEN_TH_8822B(x) ((x) & (~BITS_TRXRPT_LEN_TH_8822B))
+#define BIT_GET_TRXRPT_LEN_TH_8822B(x)                                         \
+	(((x) >> BIT_SHIFT_TRXRPT_LEN_TH_8822B) & BIT_MASK_TRXRPT_LEN_TH_8822B)
+#define BIT_SET_TRXRPT_LEN_TH_8822B(x, v)                                      \
+	(BIT_CLEAR_TRXRPT_LEN_TH_8822B(x) | BIT_TRXRPT_LEN_TH_8822B(v))
+
+#define BIT_SHIFT_TRXRPT_READ_PTR_8822B 8
+#define BIT_MASK_TRXRPT_READ_PTR_8822B 0xff
+#define BIT_TRXRPT_READ_PTR_8822B(x)                                           \
+	(((x) & BIT_MASK_TRXRPT_READ_PTR_8822B)                                \
+	 << BIT_SHIFT_TRXRPT_READ_PTR_8822B)
+#define BITS_TRXRPT_READ_PTR_8822B                                             \
+	(BIT_MASK_TRXRPT_READ_PTR_8822B << BIT_SHIFT_TRXRPT_READ_PTR_8822B)
+#define BIT_CLEAR_TRXRPT_READ_PTR_8822B(x) ((x) & (~BITS_TRXRPT_READ_PTR_8822B))
+#define BIT_GET_TRXRPT_READ_PTR_8822B(x)                                       \
+	(((x) >> BIT_SHIFT_TRXRPT_READ_PTR_8822B) &                            \
+	 BIT_MASK_TRXRPT_READ_PTR_8822B)
+#define BIT_SET_TRXRPT_READ_PTR_8822B(x, v)                                    \
+	(BIT_CLEAR_TRXRPT_READ_PTR_8822B(x) | BIT_TRXRPT_READ_PTR_8822B(v))
+
+#define BIT_SHIFT_TRXRPT_WRITE_PTR_8822B 0
+#define BIT_MASK_TRXRPT_WRITE_PTR_8822B 0xff
+#define BIT_TRXRPT_WRITE_PTR_8822B(x)                                          \
+	(((x) & BIT_MASK_TRXRPT_WRITE_PTR_8822B)                               \
+	 << BIT_SHIFT_TRXRPT_WRITE_PTR_8822B)
+#define BITS_TRXRPT_WRITE_PTR_8822B                                            \
+	(BIT_MASK_TRXRPT_WRITE_PTR_8822B << BIT_SHIFT_TRXRPT_WRITE_PTR_8822B)
+#define BIT_CLEAR_TRXRPT_WRITE_PTR_8822B(x)                                    \
+	((x) & (~BITS_TRXRPT_WRITE_PTR_8822B))
+#define BIT_GET_TRXRPT_WRITE_PTR_8822B(x)                                      \
+	(((x) >> BIT_SHIFT_TRXRPT_WRITE_PTR_8822B) &                           \
+	 BIT_MASK_TRXRPT_WRITE_PTR_8822B)
+#define BIT_SET_TRXRPT_WRITE_PTR_8822B(x, v)                                   \
+	(BIT_CLEAR_TRXRPT_WRITE_PTR_8822B(x) | BIT_TRXRPT_WRITE_PTR_8822B(v))
+
+/* 2 REG_INIRTS_RATE_SEL_8822B */
+#define BIT_LEAG_RTS_BW_DUP_8822B BIT(5)
+
+/* 2 REG_BASIC_CFEND_RATE_8822B */
+
+#define BIT_SHIFT_BASIC_CFEND_RATE_8822B 0
+#define BIT_MASK_BASIC_CFEND_RATE_8822B 0x1f
+#define BIT_BASIC_CFEND_RATE_8822B(x)                                          \
+	(((x) & BIT_MASK_BASIC_CFEND_RATE_8822B)                               \
+	 << BIT_SHIFT_BASIC_CFEND_RATE_8822B)
+#define BITS_BASIC_CFEND_RATE_8822B                                            \
+	(BIT_MASK_BASIC_CFEND_RATE_8822B << BIT_SHIFT_BASIC_CFEND_RATE_8822B)
+#define BIT_CLEAR_BASIC_CFEND_RATE_8822B(x)                                    \
+	((x) & (~BITS_BASIC_CFEND_RATE_8822B))
+#define BIT_GET_BASIC_CFEND_RATE_8822B(x)                                      \
+	(((x) >> BIT_SHIFT_BASIC_CFEND_RATE_8822B) &                           \
+	 BIT_MASK_BASIC_CFEND_RATE_8822B)
+#define BIT_SET_BASIC_CFEND_RATE_8822B(x, v)                                   \
+	(BIT_CLEAR_BASIC_CFEND_RATE_8822B(x) | BIT_BASIC_CFEND_RATE_8822B(v))
+
+/* 2 REG_STBC_CFEND_RATE_8822B */
+
+#define BIT_SHIFT_STBC_CFEND_RATE_8822B 0
+#define BIT_MASK_STBC_CFEND_RATE_8822B 0x1f
+#define BIT_STBC_CFEND_RATE_8822B(x)                                           \
+	(((x) & BIT_MASK_STBC_CFEND_RATE_8822B)                                \
+	 << BIT_SHIFT_STBC_CFEND_RATE_8822B)
+#define BITS_STBC_CFEND_RATE_8822B                                             \
+	(BIT_MASK_STBC_CFEND_RATE_8822B << BIT_SHIFT_STBC_CFEND_RATE_8822B)
+#define BIT_CLEAR_STBC_CFEND_RATE_8822B(x) ((x) & (~BITS_STBC_CFEND_RATE_8822B))
+#define BIT_GET_STBC_CFEND_RATE_8822B(x)                                       \
+	(((x) >> BIT_SHIFT_STBC_CFEND_RATE_8822B) &                            \
+	 BIT_MASK_STBC_CFEND_RATE_8822B)
+#define BIT_SET_STBC_CFEND_RATE_8822B(x, v)                                    \
+	(BIT_CLEAR_STBC_CFEND_RATE_8822B(x) | BIT_STBC_CFEND_RATE_8822B(v))
+
+/* 2 REG_DATA_SC_8822B */
+
+#define BIT_SHIFT_TXSC_40M_8822B 4
+#define BIT_MASK_TXSC_40M_8822B 0xf
+#define BIT_TXSC_40M_8822B(x)                                                  \
+	(((x) & BIT_MASK_TXSC_40M_8822B) << BIT_SHIFT_TXSC_40M_8822B)
+#define BITS_TXSC_40M_8822B                                                    \
+	(BIT_MASK_TXSC_40M_8822B << BIT_SHIFT_TXSC_40M_8822B)
+#define BIT_CLEAR_TXSC_40M_8822B(x) ((x) & (~BITS_TXSC_40M_8822B))
+#define BIT_GET_TXSC_40M_8822B(x)                                              \
+	(((x) >> BIT_SHIFT_TXSC_40M_8822B) & BIT_MASK_TXSC_40M_8822B)
+#define BIT_SET_TXSC_40M_8822B(x, v)                                           \
+	(BIT_CLEAR_TXSC_40M_8822B(x) | BIT_TXSC_40M_8822B(v))
+
+#define BIT_SHIFT_TXSC_20M_8822B 0
+#define BIT_MASK_TXSC_20M_8822B 0xf
+#define BIT_TXSC_20M_8822B(x)                                                  \
+	(((x) & BIT_MASK_TXSC_20M_8822B) << BIT_SHIFT_TXSC_20M_8822B)
+#define BITS_TXSC_20M_8822B                                                    \
+	(BIT_MASK_TXSC_20M_8822B << BIT_SHIFT_TXSC_20M_8822B)
+#define BIT_CLEAR_TXSC_20M_8822B(x) ((x) & (~BITS_TXSC_20M_8822B))
+#define BIT_GET_TXSC_20M_8822B(x)                                              \
+	(((x) >> BIT_SHIFT_TXSC_20M_8822B) & BIT_MASK_TXSC_20M_8822B)
+#define BIT_SET_TXSC_20M_8822B(x, v)                                           \
+	(BIT_CLEAR_TXSC_20M_8822B(x) | BIT_TXSC_20M_8822B(v))
+
+/* 2 REG_MACID_SLEEP3_8822B */
+
+#define BIT_SHIFT_MACID127_96_PKTSLEEP_8822B 0
+#define BIT_MASK_MACID127_96_PKTSLEEP_8822B 0xffffffffL
+#define BIT_MACID127_96_PKTSLEEP_8822B(x)                                      \
+	(((x) & BIT_MASK_MACID127_96_PKTSLEEP_8822B)                           \
+	 << BIT_SHIFT_MACID127_96_PKTSLEEP_8822B)
+#define BITS_MACID127_96_PKTSLEEP_8822B                                        \
+	(BIT_MASK_MACID127_96_PKTSLEEP_8822B                                   \
+	 << BIT_SHIFT_MACID127_96_PKTSLEEP_8822B)
+#define BIT_CLEAR_MACID127_96_PKTSLEEP_8822B(x)                                \
+	((x) & (~BITS_MACID127_96_PKTSLEEP_8822B))
+#define BIT_GET_MACID127_96_PKTSLEEP_8822B(x)                                  \
+	(((x) >> BIT_SHIFT_MACID127_96_PKTSLEEP_8822B) &                       \
+	 BIT_MASK_MACID127_96_PKTSLEEP_8822B)
+#define BIT_SET_MACID127_96_PKTSLEEP_8822B(x, v)                               \
+	(BIT_CLEAR_MACID127_96_PKTSLEEP_8822B(x) |                             \
+	 BIT_MACID127_96_PKTSLEEP_8822B(v))
+
+/* 2 REG_MACID_SLEEP1_8822B */
+
+#define BIT_SHIFT_MACID63_32_PKTSLEEP_8822B 0
+#define BIT_MASK_MACID63_32_PKTSLEEP_8822B 0xffffffffL
+#define BIT_MACID63_32_PKTSLEEP_8822B(x)                                       \
+	(((x) & BIT_MASK_MACID63_32_PKTSLEEP_8822B)                            \
+	 << BIT_SHIFT_MACID63_32_PKTSLEEP_8822B)
+#define BITS_MACID63_32_PKTSLEEP_8822B                                         \
+	(BIT_MASK_MACID63_32_PKTSLEEP_8822B                                    \
+	 << BIT_SHIFT_MACID63_32_PKTSLEEP_8822B)
+#define BIT_CLEAR_MACID63_32_PKTSLEEP_8822B(x)                                 \
+	((x) & (~BITS_MACID63_32_PKTSLEEP_8822B))
+#define BIT_GET_MACID63_32_PKTSLEEP_8822B(x)                                   \
+	(((x) >> BIT_SHIFT_MACID63_32_PKTSLEEP_8822B) &                        \
+	 BIT_MASK_MACID63_32_PKTSLEEP_8822B)
+#define BIT_SET_MACID63_32_PKTSLEEP_8822B(x, v)                                \
+	(BIT_CLEAR_MACID63_32_PKTSLEEP_8822B(x) |                              \
+	 BIT_MACID63_32_PKTSLEEP_8822B(v))
+
+/* 2 REG_ARFR2_V1_8822B */
+
+#define BIT_SHIFT_ARFR2_V1_8822B 0
+#define BIT_MASK_ARFR2_V1_8822B 0xffffffffffffffffL
+#define BIT_ARFR2_V1_8822B(x)                                                  \
+	(((x) & BIT_MASK_ARFR2_V1_8822B) << BIT_SHIFT_ARFR2_V1_8822B)
+#define BITS_ARFR2_V1_8822B                                                    \
+	(BIT_MASK_ARFR2_V1_8822B << BIT_SHIFT_ARFR2_V1_8822B)
+#define BIT_CLEAR_ARFR2_V1_8822B(x) ((x) & (~BITS_ARFR2_V1_8822B))
+#define BIT_GET_ARFR2_V1_8822B(x)                                              \
+	(((x) >> BIT_SHIFT_ARFR2_V1_8822B) & BIT_MASK_ARFR2_V1_8822B)
+#define BIT_SET_ARFR2_V1_8822B(x, v)                                           \
+	(BIT_CLEAR_ARFR2_V1_8822B(x) | BIT_ARFR2_V1_8822B(v))
+
+/* 2 REG_ARFR3_V1_8822B */
+
+#define BIT_SHIFT_ARFR3_V1_8822B 0
+#define BIT_MASK_ARFR3_V1_8822B 0xffffffffffffffffL
+#define BIT_ARFR3_V1_8822B(x)                                                  \
+	(((x) & BIT_MASK_ARFR3_V1_8822B) << BIT_SHIFT_ARFR3_V1_8822B)
+#define BITS_ARFR3_V1_8822B                                                    \
+	(BIT_MASK_ARFR3_V1_8822B << BIT_SHIFT_ARFR3_V1_8822B)
+#define BIT_CLEAR_ARFR3_V1_8822B(x) ((x) & (~BITS_ARFR3_V1_8822B))
+#define BIT_GET_ARFR3_V1_8822B(x)                                              \
+	(((x) >> BIT_SHIFT_ARFR3_V1_8822B) & BIT_MASK_ARFR3_V1_8822B)
+#define BIT_SET_ARFR3_V1_8822B(x, v)                                           \
+	(BIT_CLEAR_ARFR3_V1_8822B(x) | BIT_ARFR3_V1_8822B(v))
+
+/* 2 REG_ARFR4_8822B */
+
+#define BIT_SHIFT_ARFR4_8822B 0
+#define BIT_MASK_ARFR4_8822B 0xffffffffffffffffL
+#define BIT_ARFR4_8822B(x)                                                     \
+	(((x) & BIT_MASK_ARFR4_8822B) << BIT_SHIFT_ARFR4_8822B)
+#define BITS_ARFR4_8822B (BIT_MASK_ARFR4_8822B << BIT_SHIFT_ARFR4_8822B)
+#define BIT_CLEAR_ARFR4_8822B(x) ((x) & (~BITS_ARFR4_8822B))
+#define BIT_GET_ARFR4_8822B(x)                                                 \
+	(((x) >> BIT_SHIFT_ARFR4_8822B) & BIT_MASK_ARFR4_8822B)
+#define BIT_SET_ARFR4_8822B(x, v)                                              \
+	(BIT_CLEAR_ARFR4_8822B(x) | BIT_ARFR4_8822B(v))
+
+/* 2 REG_ARFR5_8822B */
+
+#define BIT_SHIFT_ARFR5_8822B 0
+#define BIT_MASK_ARFR5_8822B 0xffffffffffffffffL
+#define BIT_ARFR5_8822B(x)                                                     \
+	(((x) & BIT_MASK_ARFR5_8822B) << BIT_SHIFT_ARFR5_8822B)
+#define BITS_ARFR5_8822B (BIT_MASK_ARFR5_8822B << BIT_SHIFT_ARFR5_8822B)
+#define BIT_CLEAR_ARFR5_8822B(x) ((x) & (~BITS_ARFR5_8822B))
+#define BIT_GET_ARFR5_8822B(x)                                                 \
+	(((x) >> BIT_SHIFT_ARFR5_8822B) & BIT_MASK_ARFR5_8822B)
+#define BIT_SET_ARFR5_8822B(x, v)                                              \
+	(BIT_CLEAR_ARFR5_8822B(x) | BIT_ARFR5_8822B(v))
+
+/* 2 REG_TXRPT_START_OFFSET_8822B */
+
+#define BIT_SHIFT_MACID_MURATE_OFFSET_8822B 24
+#define BIT_MASK_MACID_MURATE_OFFSET_8822B 0xff
+#define BIT_MACID_MURATE_OFFSET_8822B(x)                                       \
+	(((x) & BIT_MASK_MACID_MURATE_OFFSET_8822B)                            \
+	 << BIT_SHIFT_MACID_MURATE_OFFSET_8822B)
+#define BITS_MACID_MURATE_OFFSET_8822B                                         \
+	(BIT_MASK_MACID_MURATE_OFFSET_8822B                                    \
+	 << BIT_SHIFT_MACID_MURATE_OFFSET_8822B)
+#define BIT_CLEAR_MACID_MURATE_OFFSET_8822B(x)                                 \
+	((x) & (~BITS_MACID_MURATE_OFFSET_8822B))
+#define BIT_GET_MACID_MURATE_OFFSET_8822B(x)                                   \
+	(((x) >> BIT_SHIFT_MACID_MURATE_OFFSET_8822B) &                        \
+	 BIT_MASK_MACID_MURATE_OFFSET_8822B)
+#define BIT_SET_MACID_MURATE_OFFSET_8822B(x, v)                                \
+	(BIT_CLEAR_MACID_MURATE_OFFSET_8822B(x) |                              \
+	 BIT_MACID_MURATE_OFFSET_8822B(v))
+
+#define BIT_RPTFIFO_SIZE_OPT_8822B BIT(16)
+
+#define BIT_SHIFT_MACID_CTRL_OFFSET_8822B 8
+#define BIT_MASK_MACID_CTRL_OFFSET_8822B 0xff
+#define BIT_MACID_CTRL_OFFSET_8822B(x)                                         \
+	(((x) & BIT_MASK_MACID_CTRL_OFFSET_8822B)                              \
+	 << BIT_SHIFT_MACID_CTRL_OFFSET_8822B)
+#define BITS_MACID_CTRL_OFFSET_8822B                                           \
+	(BIT_MASK_MACID_CTRL_OFFSET_8822B << BIT_SHIFT_MACID_CTRL_OFFSET_8822B)
+#define BIT_CLEAR_MACID_CTRL_OFFSET_8822B(x)                                   \
+	((x) & (~BITS_MACID_CTRL_OFFSET_8822B))
+#define BIT_GET_MACID_CTRL_OFFSET_8822B(x)                                     \
+	(((x) >> BIT_SHIFT_MACID_CTRL_OFFSET_8822B) &                          \
+	 BIT_MASK_MACID_CTRL_OFFSET_8822B)
+#define BIT_SET_MACID_CTRL_OFFSET_8822B(x, v)                                  \
+	(BIT_CLEAR_MACID_CTRL_OFFSET_8822B(x) | BIT_MACID_CTRL_OFFSET_8822B(v))
+
+#define BIT_SHIFT_AMPDU_TXRPT_OFFSET_8822B 0
+#define BIT_MASK_AMPDU_TXRPT_OFFSET_8822B 0xff
+#define BIT_AMPDU_TXRPT_OFFSET_8822B(x)                                        \
+	(((x) & BIT_MASK_AMPDU_TXRPT_OFFSET_8822B)                             \
+	 << BIT_SHIFT_AMPDU_TXRPT_OFFSET_8822B)
+#define BITS_AMPDU_TXRPT_OFFSET_8822B                                          \
+	(BIT_MASK_AMPDU_TXRPT_OFFSET_8822B                                     \
+	 << BIT_SHIFT_AMPDU_TXRPT_OFFSET_8822B)
+#define BIT_CLEAR_AMPDU_TXRPT_OFFSET_8822B(x)                                  \
+	((x) & (~BITS_AMPDU_TXRPT_OFFSET_8822B))
+#define BIT_GET_AMPDU_TXRPT_OFFSET_8822B(x)                                    \
+	(((x) >> BIT_SHIFT_AMPDU_TXRPT_OFFSET_8822B) &                         \
+	 BIT_MASK_AMPDU_TXRPT_OFFSET_8822B)
+#define BIT_SET_AMPDU_TXRPT_OFFSET_8822B(x, v)                                 \
+	(BIT_CLEAR_AMPDU_TXRPT_OFFSET_8822B(x) |                               \
+	 BIT_AMPDU_TXRPT_OFFSET_8822B(v))
+
+/* 2 REG_POWER_STAGE1_8822B */
+#define BIT_PTA_WL_PRI_MASK_CPU_MGQ_8822B BIT(31)
+#define BIT_PTA_WL_PRI_MASK_BCNQ_8822B BIT(30)
+#define BIT_PTA_WL_PRI_MASK_HIQ_8822B BIT(29)
+#define BIT_PTA_WL_PRI_MASK_MGQ_8822B BIT(28)
+#define BIT_PTA_WL_PRI_MASK_BK_8822B BIT(27)
+#define BIT_PTA_WL_PRI_MASK_BE_8822B BIT(26)
+#define BIT_PTA_WL_PRI_MASK_VI_8822B BIT(25)
+#define BIT_PTA_WL_PRI_MASK_VO_8822B BIT(24)
+
+#define BIT_SHIFT_POWER_STAGE1_8822B 0
+#define BIT_MASK_POWER_STAGE1_8822B 0xffffff
+#define BIT_POWER_STAGE1_8822B(x)                                              \
+	(((x) & BIT_MASK_POWER_STAGE1_8822B) << BIT_SHIFT_POWER_STAGE1_8822B)
+#define BITS_POWER_STAGE1_8822B                                                \
+	(BIT_MASK_POWER_STAGE1_8822B << BIT_SHIFT_POWER_STAGE1_8822B)
+#define BIT_CLEAR_POWER_STAGE1_8822B(x) ((x) & (~BITS_POWER_STAGE1_8822B))
+#define BIT_GET_POWER_STAGE1_8822B(x)                                          \
+	(((x) >> BIT_SHIFT_POWER_STAGE1_8822B) & BIT_MASK_POWER_STAGE1_8822B)
+#define BIT_SET_POWER_STAGE1_8822B(x, v)                                       \
+	(BIT_CLEAR_POWER_STAGE1_8822B(x) | BIT_POWER_STAGE1_8822B(v))
+
+/* 2 REG_POWER_STAGE2_8822B */
+#define BIT__R_CTRL_PKT_POW_ADJ_8822B BIT(24)
+
+#define BIT_SHIFT_POWER_STAGE2_8822B 0
+#define BIT_MASK_POWER_STAGE2_8822B 0xffffff
+#define BIT_POWER_STAGE2_8822B(x)                                              \
+	(((x) & BIT_MASK_POWER_STAGE2_8822B) << BIT_SHIFT_POWER_STAGE2_8822B)
+#define BITS_POWER_STAGE2_8822B                                                \
+	(BIT_MASK_POWER_STAGE2_8822B << BIT_SHIFT_POWER_STAGE2_8822B)
+#define BIT_CLEAR_POWER_STAGE2_8822B(x) ((x) & (~BITS_POWER_STAGE2_8822B))
+#define BIT_GET_POWER_STAGE2_8822B(x)                                          \
+	(((x) >> BIT_SHIFT_POWER_STAGE2_8822B) & BIT_MASK_POWER_STAGE2_8822B)
+#define BIT_SET_POWER_STAGE2_8822B(x, v)                                       \
+	(BIT_CLEAR_POWER_STAGE2_8822B(x) | BIT_POWER_STAGE2_8822B(v))
+
+/* 2 REG_SW_AMPDU_BURST_MODE_CTRL_8822B */
+
+#define BIT_SHIFT_PAD_NUM_THRES_8822B 24
+#define BIT_MASK_PAD_NUM_THRES_8822B 0x3f
+#define BIT_PAD_NUM_THRES_8822B(x)                                             \
+	(((x) & BIT_MASK_PAD_NUM_THRES_8822B) << BIT_SHIFT_PAD_NUM_THRES_8822B)
+#define BITS_PAD_NUM_THRES_8822B                                               \
+	(BIT_MASK_PAD_NUM_THRES_8822B << BIT_SHIFT_PAD_NUM_THRES_8822B)
+#define BIT_CLEAR_PAD_NUM_THRES_8822B(x) ((x) & (~BITS_PAD_NUM_THRES_8822B))
+#define BIT_GET_PAD_NUM_THRES_8822B(x)                                         \
+	(((x) >> BIT_SHIFT_PAD_NUM_THRES_8822B) & BIT_MASK_PAD_NUM_THRES_8822B)
+#define BIT_SET_PAD_NUM_THRES_8822B(x, v)                                      \
+	(BIT_CLEAR_PAD_NUM_THRES_8822B(x) | BIT_PAD_NUM_THRES_8822B(v))
+
+#define BIT_R_DMA_THIS_QUEUE_BK_8822B BIT(23)
+#define BIT_R_DMA_THIS_QUEUE_BE_8822B BIT(22)
+#define BIT_R_DMA_THIS_QUEUE_VI_8822B BIT(21)
+#define BIT_R_DMA_THIS_QUEUE_VO_8822B BIT(20)
+
+#define BIT_SHIFT_R_TOTAL_LEN_TH_8822B 8
+#define BIT_MASK_R_TOTAL_LEN_TH_8822B 0xfff
+#define BIT_R_TOTAL_LEN_TH_8822B(x)                                            \
+	(((x) & BIT_MASK_R_TOTAL_LEN_TH_8822B)                                 \
+	 << BIT_SHIFT_R_TOTAL_LEN_TH_8822B)
+#define BITS_R_TOTAL_LEN_TH_8822B                                              \
+	(BIT_MASK_R_TOTAL_LEN_TH_8822B << BIT_SHIFT_R_TOTAL_LEN_TH_8822B)
+#define BIT_CLEAR_R_TOTAL_LEN_TH_8822B(x) ((x) & (~BITS_R_TOTAL_LEN_TH_8822B))
+#define BIT_GET_R_TOTAL_LEN_TH_8822B(x)                                        \
+	(((x) >> BIT_SHIFT_R_TOTAL_LEN_TH_8822B) &                             \
+	 BIT_MASK_R_TOTAL_LEN_TH_8822B)
+#define BIT_SET_R_TOTAL_LEN_TH_8822B(x, v)                                     \
+	(BIT_CLEAR_R_TOTAL_LEN_TH_8822B(x) | BIT_R_TOTAL_LEN_TH_8822B(v))
+
+#define BIT_EN_NEW_EARLY_8822B BIT(7)
+#define BIT_PRE_TX_CMD_8822B BIT(6)
+
+#define BIT_SHIFT_NUM_SCL_EN_8822B 4
+#define BIT_MASK_NUM_SCL_EN_8822B 0x3
+#define BIT_NUM_SCL_EN_8822B(x)                                                \
+	(((x) & BIT_MASK_NUM_SCL_EN_8822B) << BIT_SHIFT_NUM_SCL_EN_8822B)
+#define BITS_NUM_SCL_EN_8822B                                                  \
+	(BIT_MASK_NUM_SCL_EN_8822B << BIT_SHIFT_NUM_SCL_EN_8822B)
+#define BIT_CLEAR_NUM_SCL_EN_8822B(x) ((x) & (~BITS_NUM_SCL_EN_8822B))
+#define BIT_GET_NUM_SCL_EN_8822B(x)                                            \
+	(((x) >> BIT_SHIFT_NUM_SCL_EN_8822B) & BIT_MASK_NUM_SCL_EN_8822B)
+#define BIT_SET_NUM_SCL_EN_8822B(x, v)                                         \
+	(BIT_CLEAR_NUM_SCL_EN_8822B(x) | BIT_NUM_SCL_EN_8822B(v))
+
+#define BIT_BK_EN_8822B BIT(3)
+#define BIT_BE_EN_8822B BIT(2)
+#define BIT_VI_EN_8822B BIT(1)
+#define BIT_VO_EN_8822B BIT(0)
+
+/* 2 REG_PKT_LIFE_TIME_8822B */
+
+#define BIT_SHIFT_PKT_LIFTIME_BEBK_8822B 16
+#define BIT_MASK_PKT_LIFTIME_BEBK_8822B 0xffff
+#define BIT_PKT_LIFTIME_BEBK_8822B(x)                                          \
+	(((x) & BIT_MASK_PKT_LIFTIME_BEBK_8822B)                               \
+	 << BIT_SHIFT_PKT_LIFTIME_BEBK_8822B)
+#define BITS_PKT_LIFTIME_BEBK_8822B                                            \
+	(BIT_MASK_PKT_LIFTIME_BEBK_8822B << BIT_SHIFT_PKT_LIFTIME_BEBK_8822B)
+#define BIT_CLEAR_PKT_LIFTIME_BEBK_8822B(x)                                    \
+	((x) & (~BITS_PKT_LIFTIME_BEBK_8822B))
+#define BIT_GET_PKT_LIFTIME_BEBK_8822B(x)                                      \
+	(((x) >> BIT_SHIFT_PKT_LIFTIME_BEBK_8822B) &                           \
+	 BIT_MASK_PKT_LIFTIME_BEBK_8822B)
+#define BIT_SET_PKT_LIFTIME_BEBK_8822B(x, v)                                   \
+	(BIT_CLEAR_PKT_LIFTIME_BEBK_8822B(x) | BIT_PKT_LIFTIME_BEBK_8822B(v))
+
+#define BIT_SHIFT_PKT_LIFTIME_VOVI_8822B 0
+#define BIT_MASK_PKT_LIFTIME_VOVI_8822B 0xffff
+#define BIT_PKT_LIFTIME_VOVI_8822B(x)                                          \
+	(((x) & BIT_MASK_PKT_LIFTIME_VOVI_8822B)                               \
+	 << BIT_SHIFT_PKT_LIFTIME_VOVI_8822B)
+#define BITS_PKT_LIFTIME_VOVI_8822B                                            \
+	(BIT_MASK_PKT_LIFTIME_VOVI_8822B << BIT_SHIFT_PKT_LIFTIME_VOVI_8822B)
+#define BIT_CLEAR_PKT_LIFTIME_VOVI_8822B(x)                                    \
+	((x) & (~BITS_PKT_LIFTIME_VOVI_8822B))
+#define BIT_GET_PKT_LIFTIME_VOVI_8822B(x)                                      \
+	(((x) >> BIT_SHIFT_PKT_LIFTIME_VOVI_8822B) &                           \
+	 BIT_MASK_PKT_LIFTIME_VOVI_8822B)
+#define BIT_SET_PKT_LIFTIME_VOVI_8822B(x, v)                                   \
+	(BIT_CLEAR_PKT_LIFTIME_VOVI_8822B(x) | BIT_PKT_LIFTIME_VOVI_8822B(v))
+
+/* 2 REG_STBC_SETTING_8822B */
+
+#define BIT_SHIFT_CDEND_TXTIME_L_8822B 4
+#define BIT_MASK_CDEND_TXTIME_L_8822B 0xf
+#define BIT_CDEND_TXTIME_L_8822B(x)                                            \
+	(((x) & BIT_MASK_CDEND_TXTIME_L_8822B)                                 \
+	 << BIT_SHIFT_CDEND_TXTIME_L_8822B)
+#define BITS_CDEND_TXTIME_L_8822B                                              \
+	(BIT_MASK_CDEND_TXTIME_L_8822B << BIT_SHIFT_CDEND_TXTIME_L_8822B)
+#define BIT_CLEAR_CDEND_TXTIME_L_8822B(x) ((x) & (~BITS_CDEND_TXTIME_L_8822B))
+#define BIT_GET_CDEND_TXTIME_L_8822B(x)                                        \
+	(((x) >> BIT_SHIFT_CDEND_TXTIME_L_8822B) &                             \
+	 BIT_MASK_CDEND_TXTIME_L_8822B)
+#define BIT_SET_CDEND_TXTIME_L_8822B(x, v)                                     \
+	(BIT_CLEAR_CDEND_TXTIME_L_8822B(x) | BIT_CDEND_TXTIME_L_8822B(v))
+
+#define BIT_SHIFT_NESS_8822B 2
+#define BIT_MASK_NESS_8822B 0x3
+#define BIT_NESS_8822B(x) (((x) & BIT_MASK_NESS_8822B) << BIT_SHIFT_NESS_8822B)
+#define BITS_NESS_8822B (BIT_MASK_NESS_8822B << BIT_SHIFT_NESS_8822B)
+#define BIT_CLEAR_NESS_8822B(x) ((x) & (~BITS_NESS_8822B))
+#define BIT_GET_NESS_8822B(x)                                                  \
+	(((x) >> BIT_SHIFT_NESS_8822B) & BIT_MASK_NESS_8822B)
+#define BIT_SET_NESS_8822B(x, v) (BIT_CLEAR_NESS_8822B(x) | BIT_NESS_8822B(v))
+
+#define BIT_SHIFT_STBC_CFEND_8822B 0
+#define BIT_MASK_STBC_CFEND_8822B 0x3
+#define BIT_STBC_CFEND_8822B(x)                                                \
+	(((x) & BIT_MASK_STBC_CFEND_8822B) << BIT_SHIFT_STBC_CFEND_8822B)
+#define BITS_STBC_CFEND_8822B                                                  \
+	(BIT_MASK_STBC_CFEND_8822B << BIT_SHIFT_STBC_CFEND_8822B)
+#define BIT_CLEAR_STBC_CFEND_8822B(x) ((x) & (~BITS_STBC_CFEND_8822B))
+#define BIT_GET_STBC_CFEND_8822B(x)                                            \
+	(((x) >> BIT_SHIFT_STBC_CFEND_8822B) & BIT_MASK_STBC_CFEND_8822B)
+#define BIT_SET_STBC_CFEND_8822B(x, v)                                         \
+	(BIT_CLEAR_STBC_CFEND_8822B(x) | BIT_STBC_CFEND_8822B(v))
+
+/* 2 REG_STBC_SETTING2_8822B */
+
+#define BIT_SHIFT_CDEND_TXTIME_H_8822B 0
+#define BIT_MASK_CDEND_TXTIME_H_8822B 0x1f
+#define BIT_CDEND_TXTIME_H_8822B(x)                                            \
+	(((x) & BIT_MASK_CDEND_TXTIME_H_8822B)                                 \
+	 << BIT_SHIFT_CDEND_TXTIME_H_8822B)
+#define BITS_CDEND_TXTIME_H_8822B                                              \
+	(BIT_MASK_CDEND_TXTIME_H_8822B << BIT_SHIFT_CDEND_TXTIME_H_8822B)
+#define BIT_CLEAR_CDEND_TXTIME_H_8822B(x) ((x) & (~BITS_CDEND_TXTIME_H_8822B))
+#define BIT_GET_CDEND_TXTIME_H_8822B(x)                                        \
+	(((x) >> BIT_SHIFT_CDEND_TXTIME_H_8822B) &                             \
+	 BIT_MASK_CDEND_TXTIME_H_8822B)
+#define BIT_SET_CDEND_TXTIME_H_8822B(x, v)                                     \
+	(BIT_CLEAR_CDEND_TXTIME_H_8822B(x) | BIT_CDEND_TXTIME_H_8822B(v))
+
+/* 2 REG_QUEUE_CTRL_8822B */
+#define BIT_PTA_EDCCA_EN_8822B BIT(5)
+#define BIT_PTA_WL_TX_EN_8822B BIT(4)
+#define BIT_R_USE_DATA_BW_8822B BIT(3)
+#define BIT_TRI_PKT_INT_MODE1_8822B BIT(2)
+#define BIT_TRI_PKT_INT_MODE0_8822B BIT(1)
+#define BIT_ACQ_MODE_SEL_8822B BIT(0)
+
+/* 2 REG_SINGLE_AMPDU_CTRL_8822B */
+#define BIT_EN_SINGLE_APMDU_8822B BIT(7)
+
+/* 2 REG_PROT_MODE_CTRL_8822B */
+
+#define BIT_SHIFT_RTS_MAX_AGG_NUM_8822B 24
+#define BIT_MASK_RTS_MAX_AGG_NUM_8822B 0x3f
+#define BIT_RTS_MAX_AGG_NUM_8822B(x)                                           \
+	(((x) & BIT_MASK_RTS_MAX_AGG_NUM_8822B)                                \
+	 << BIT_SHIFT_RTS_MAX_AGG_NUM_8822B)
+#define BITS_RTS_MAX_AGG_NUM_8822B                                             \
+	(BIT_MASK_RTS_MAX_AGG_NUM_8822B << BIT_SHIFT_RTS_MAX_AGG_NUM_8822B)
+#define BIT_CLEAR_RTS_MAX_AGG_NUM_8822B(x) ((x) & (~BITS_RTS_MAX_AGG_NUM_8822B))
+#define BIT_GET_RTS_MAX_AGG_NUM_8822B(x)                                       \
+	(((x) >> BIT_SHIFT_RTS_MAX_AGG_NUM_8822B) &                            \
+	 BIT_MASK_RTS_MAX_AGG_NUM_8822B)
+#define BIT_SET_RTS_MAX_AGG_NUM_8822B(x, v)                                    \
+	(BIT_CLEAR_RTS_MAX_AGG_NUM_8822B(x) | BIT_RTS_MAX_AGG_NUM_8822B(v))
+
+#define BIT_SHIFT_MAX_AGG_NUM_8822B 16
+#define BIT_MASK_MAX_AGG_NUM_8822B 0x3f
+#define BIT_MAX_AGG_NUM_8822B(x)                                               \
+	(((x) & BIT_MASK_MAX_AGG_NUM_8822B) << BIT_SHIFT_MAX_AGG_NUM_8822B)
+#define BITS_MAX_AGG_NUM_8822B                                                 \
+	(BIT_MASK_MAX_AGG_NUM_8822B << BIT_SHIFT_MAX_AGG_NUM_8822B)
+#define BIT_CLEAR_MAX_AGG_NUM_8822B(x) ((x) & (~BITS_MAX_AGG_NUM_8822B))
+#define BIT_GET_MAX_AGG_NUM_8822B(x)                                           \
+	(((x) >> BIT_SHIFT_MAX_AGG_NUM_8822B) & BIT_MASK_MAX_AGG_NUM_8822B)
+#define BIT_SET_MAX_AGG_NUM_8822B(x, v)                                        \
+	(BIT_CLEAR_MAX_AGG_NUM_8822B(x) | BIT_MAX_AGG_NUM_8822B(v))
+
+#define BIT_SHIFT_RTS_TXTIME_TH_8822B 8
+#define BIT_MASK_RTS_TXTIME_TH_8822B 0xff
+#define BIT_RTS_TXTIME_TH_8822B(x)                                             \
+	(((x) & BIT_MASK_RTS_TXTIME_TH_8822B) << BIT_SHIFT_RTS_TXTIME_TH_8822B)
+#define BITS_RTS_TXTIME_TH_8822B                                               \
+	(BIT_MASK_RTS_TXTIME_TH_8822B << BIT_SHIFT_RTS_TXTIME_TH_8822B)
+#define BIT_CLEAR_RTS_TXTIME_TH_8822B(x) ((x) & (~BITS_RTS_TXTIME_TH_8822B))
+#define BIT_GET_RTS_TXTIME_TH_8822B(x)                                         \
+	(((x) >> BIT_SHIFT_RTS_TXTIME_TH_8822B) & BIT_MASK_RTS_TXTIME_TH_8822B)
+#define BIT_SET_RTS_TXTIME_TH_8822B(x, v)                                      \
+	(BIT_CLEAR_RTS_TXTIME_TH_8822B(x) | BIT_RTS_TXTIME_TH_8822B(v))
+
+#define BIT_SHIFT_RTS_LEN_TH_8822B 0
+#define BIT_MASK_RTS_LEN_TH_8822B 0xff
+#define BIT_RTS_LEN_TH_8822B(x)                                                \
+	(((x) & BIT_MASK_RTS_LEN_TH_8822B) << BIT_SHIFT_RTS_LEN_TH_8822B)
+#define BITS_RTS_LEN_TH_8822B                                                  \
+	(BIT_MASK_RTS_LEN_TH_8822B << BIT_SHIFT_RTS_LEN_TH_8822B)
+#define BIT_CLEAR_RTS_LEN_TH_8822B(x) ((x) & (~BITS_RTS_LEN_TH_8822B))
+#define BIT_GET_RTS_LEN_TH_8822B(x)                                            \
+	(((x) >> BIT_SHIFT_RTS_LEN_TH_8822B) & BIT_MASK_RTS_LEN_TH_8822B)
+#define BIT_SET_RTS_LEN_TH_8822B(x, v)                                         \
+	(BIT_CLEAR_RTS_LEN_TH_8822B(x) | BIT_RTS_LEN_TH_8822B(v))
+
+/* 2 REG_BAR_MODE_CTRL_8822B */
+
+#define BIT_SHIFT_BAR_RTY_LMT_8822B 16
+#define BIT_MASK_BAR_RTY_LMT_8822B 0x3
+#define BIT_BAR_RTY_LMT_8822B(x)                                               \
+	(((x) & BIT_MASK_BAR_RTY_LMT_8822B) << BIT_SHIFT_BAR_RTY_LMT_8822B)
+#define BITS_BAR_RTY_LMT_8822B                                                 \
+	(BIT_MASK_BAR_RTY_LMT_8822B << BIT_SHIFT_BAR_RTY_LMT_8822B)
+#define BIT_CLEAR_BAR_RTY_LMT_8822B(x) ((x) & (~BITS_BAR_RTY_LMT_8822B))
+#define BIT_GET_BAR_RTY_LMT_8822B(x)                                           \
+	(((x) >> BIT_SHIFT_BAR_RTY_LMT_8822B) & BIT_MASK_BAR_RTY_LMT_8822B)
+#define BIT_SET_BAR_RTY_LMT_8822B(x, v)                                        \
+	(BIT_CLEAR_BAR_RTY_LMT_8822B(x) | BIT_BAR_RTY_LMT_8822B(v))
+
+#define BIT_SHIFT_BAR_PKT_TXTIME_TH_8822B 8
+#define BIT_MASK_BAR_PKT_TXTIME_TH_8822B 0xff
+#define BIT_BAR_PKT_TXTIME_TH_8822B(x)                                         \
+	(((x) & BIT_MASK_BAR_PKT_TXTIME_TH_8822B)                              \
+	 << BIT_SHIFT_BAR_PKT_TXTIME_TH_8822B)
+#define BITS_BAR_PKT_TXTIME_TH_8822B                                           \
+	(BIT_MASK_BAR_PKT_TXTIME_TH_8822B << BIT_SHIFT_BAR_PKT_TXTIME_TH_8822B)
+#define BIT_CLEAR_BAR_PKT_TXTIME_TH_8822B(x)                                   \
+	((x) & (~BITS_BAR_PKT_TXTIME_TH_8822B))
+#define BIT_GET_BAR_PKT_TXTIME_TH_8822B(x)                                     \
+	(((x) >> BIT_SHIFT_BAR_PKT_TXTIME_TH_8822B) &                          \
+	 BIT_MASK_BAR_PKT_TXTIME_TH_8822B)
+#define BIT_SET_BAR_PKT_TXTIME_TH_8822B(x, v)                                  \
+	(BIT_CLEAR_BAR_PKT_TXTIME_TH_8822B(x) | BIT_BAR_PKT_TXTIME_TH_8822B(v))
+
+#define BIT_BAR_EN_V1_8822B BIT(6)
+
+#define BIT_SHIFT_BAR_PKTNUM_TH_V1_8822B 0
+#define BIT_MASK_BAR_PKTNUM_TH_V1_8822B 0x3f
+#define BIT_BAR_PKTNUM_TH_V1_8822B(x)                                          \
+	(((x) & BIT_MASK_BAR_PKTNUM_TH_V1_8822B)                               \
+	 << BIT_SHIFT_BAR_PKTNUM_TH_V1_8822B)
+#define BITS_BAR_PKTNUM_TH_V1_8822B                                            \
+	(BIT_MASK_BAR_PKTNUM_TH_V1_8822B << BIT_SHIFT_BAR_PKTNUM_TH_V1_8822B)
+#define BIT_CLEAR_BAR_PKTNUM_TH_V1_8822B(x)                                    \
+	((x) & (~BITS_BAR_PKTNUM_TH_V1_8822B))
+#define BIT_GET_BAR_PKTNUM_TH_V1_8822B(x)                                      \
+	(((x) >> BIT_SHIFT_BAR_PKTNUM_TH_V1_8822B) &                           \
+	 BIT_MASK_BAR_PKTNUM_TH_V1_8822B)
+#define BIT_SET_BAR_PKTNUM_TH_V1_8822B(x, v)                                   \
+	(BIT_CLEAR_BAR_PKTNUM_TH_V1_8822B(x) | BIT_BAR_PKTNUM_TH_V1_8822B(v))
+
+/* 2 REG_RA_TRY_RATE_AGG_LMT_8822B */
+
+#define BIT_SHIFT_RA_TRY_RATE_AGG_LMT_V1_8822B 0
+#define BIT_MASK_RA_TRY_RATE_AGG_LMT_V1_8822B 0x3f
+#define BIT_RA_TRY_RATE_AGG_LMT_V1_8822B(x)                                    \
+	(((x) & BIT_MASK_RA_TRY_RATE_AGG_LMT_V1_8822B)                         \
+	 << BIT_SHIFT_RA_TRY_RATE_AGG_LMT_V1_8822B)
+#define BITS_RA_TRY_RATE_AGG_LMT_V1_8822B                                      \
+	(BIT_MASK_RA_TRY_RATE_AGG_LMT_V1_8822B                                 \
+	 << BIT_SHIFT_RA_TRY_RATE_AGG_LMT_V1_8822B)
+#define BIT_CLEAR_RA_TRY_RATE_AGG_LMT_V1_8822B(x)                              \
+	((x) & (~BITS_RA_TRY_RATE_AGG_LMT_V1_8822B))
+#define BIT_GET_RA_TRY_RATE_AGG_LMT_V1_8822B(x)                                \
+	(((x) >> BIT_SHIFT_RA_TRY_RATE_AGG_LMT_V1_8822B) &                     \
+	 BIT_MASK_RA_TRY_RATE_AGG_LMT_V1_8822B)
+#define BIT_SET_RA_TRY_RATE_AGG_LMT_V1_8822B(x, v)                             \
+	(BIT_CLEAR_RA_TRY_RATE_AGG_LMT_V1_8822B(x) |                           \
+	 BIT_RA_TRY_RATE_AGG_LMT_V1_8822B(v))
+
+/* 2 REG_MACID_SLEEP2_8822B */
+
+#define BIT_SHIFT_MACID95_64PKTSLEEP_8822B 0
+#define BIT_MASK_MACID95_64PKTSLEEP_8822B 0xffffffffL
+#define BIT_MACID95_64PKTSLEEP_8822B(x)                                        \
+	(((x) & BIT_MASK_MACID95_64PKTSLEEP_8822B)                             \
+	 << BIT_SHIFT_MACID95_64PKTSLEEP_8822B)
+#define BITS_MACID95_64PKTSLEEP_8822B                                          \
+	(BIT_MASK_MACID95_64PKTSLEEP_8822B                                     \
+	 << BIT_SHIFT_MACID95_64PKTSLEEP_8822B)
+#define BIT_CLEAR_MACID95_64PKTSLEEP_8822B(x)                                  \
+	((x) & (~BITS_MACID95_64PKTSLEEP_8822B))
+#define BIT_GET_MACID95_64PKTSLEEP_8822B(x)                                    \
+	(((x) >> BIT_SHIFT_MACID95_64PKTSLEEP_8822B) &                         \
+	 BIT_MASK_MACID95_64PKTSLEEP_8822B)
+#define BIT_SET_MACID95_64PKTSLEEP_8822B(x, v)                                 \
+	(BIT_CLEAR_MACID95_64PKTSLEEP_8822B(x) |                               \
+	 BIT_MACID95_64PKTSLEEP_8822B(v))
+
+/* 2 REG_MACID_SLEEP_8822B */
+
+#define BIT_SHIFT_MACID31_0_PKTSLEEP_8822B 0
+#define BIT_MASK_MACID31_0_PKTSLEEP_8822B 0xffffffffL
+#define BIT_MACID31_0_PKTSLEEP_8822B(x)                                        \
+	(((x) & BIT_MASK_MACID31_0_PKTSLEEP_8822B)                             \
+	 << BIT_SHIFT_MACID31_0_PKTSLEEP_8822B)
+#define BITS_MACID31_0_PKTSLEEP_8822B                                          \
+	(BIT_MASK_MACID31_0_PKTSLEEP_8822B                                     \
+	 << BIT_SHIFT_MACID31_0_PKTSLEEP_8822B)
+#define BIT_CLEAR_MACID31_0_PKTSLEEP_8822B(x)                                  \
+	((x) & (~BITS_MACID31_0_PKTSLEEP_8822B))
+#define BIT_GET_MACID31_0_PKTSLEEP_8822B(x)                                    \
+	(((x) >> BIT_SHIFT_MACID31_0_PKTSLEEP_8822B) &                         \
+	 BIT_MASK_MACID31_0_PKTSLEEP_8822B)
+#define BIT_SET_MACID31_0_PKTSLEEP_8822B(x, v)                                 \
+	(BIT_CLEAR_MACID31_0_PKTSLEEP_8822B(x) |                               \
+	 BIT_MACID31_0_PKTSLEEP_8822B(v))
+
+/* 2 REG_HW_SEQ0_8822B */
+
+#define BIT_SHIFT_HW_SSN_SEQ0_8822B 0
+#define BIT_MASK_HW_SSN_SEQ0_8822B 0xfff
+#define BIT_HW_SSN_SEQ0_8822B(x)                                               \
+	(((x) & BIT_MASK_HW_SSN_SEQ0_8822B) << BIT_SHIFT_HW_SSN_SEQ0_8822B)
+#define BITS_HW_SSN_SEQ0_8822B                                                 \
+	(BIT_MASK_HW_SSN_SEQ0_8822B << BIT_SHIFT_HW_SSN_SEQ0_8822B)
+#define BIT_CLEAR_HW_SSN_SEQ0_8822B(x) ((x) & (~BITS_HW_SSN_SEQ0_8822B))
+#define BIT_GET_HW_SSN_SEQ0_8822B(x)                                           \
+	(((x) >> BIT_SHIFT_HW_SSN_SEQ0_8822B) & BIT_MASK_HW_SSN_SEQ0_8822B)
+#define BIT_SET_HW_SSN_SEQ0_8822B(x, v)                                        \
+	(BIT_CLEAR_HW_SSN_SEQ0_8822B(x) | BIT_HW_SSN_SEQ0_8822B(v))
+
+/* 2 REG_HW_SEQ1_8822B */
+
+#define BIT_SHIFT_HW_SSN_SEQ1_8822B 0
+#define BIT_MASK_HW_SSN_SEQ1_8822B 0xfff
+#define BIT_HW_SSN_SEQ1_8822B(x)                                               \
+	(((x) & BIT_MASK_HW_SSN_SEQ1_8822B) << BIT_SHIFT_HW_SSN_SEQ1_8822B)
+#define BITS_HW_SSN_SEQ1_8822B                                                 \
+	(BIT_MASK_HW_SSN_SEQ1_8822B << BIT_SHIFT_HW_SSN_SEQ1_8822B)
+#define BIT_CLEAR_HW_SSN_SEQ1_8822B(x) ((x) & (~BITS_HW_SSN_SEQ1_8822B))
+#define BIT_GET_HW_SSN_SEQ1_8822B(x)                                           \
+	(((x) >> BIT_SHIFT_HW_SSN_SEQ1_8822B) & BIT_MASK_HW_SSN_SEQ1_8822B)
+#define BIT_SET_HW_SSN_SEQ1_8822B(x, v)                                        \
+	(BIT_CLEAR_HW_SSN_SEQ1_8822B(x) | BIT_HW_SSN_SEQ1_8822B(v))
+
+/* 2 REG_HW_SEQ2_8822B */
+
+#define BIT_SHIFT_HW_SSN_SEQ2_8822B 0
+#define BIT_MASK_HW_SSN_SEQ2_8822B 0xfff
+#define BIT_HW_SSN_SEQ2_8822B(x)                                               \
+	(((x) & BIT_MASK_HW_SSN_SEQ2_8822B) << BIT_SHIFT_HW_SSN_SEQ2_8822B)
+#define BITS_HW_SSN_SEQ2_8822B                                                 \
+	(BIT_MASK_HW_SSN_SEQ2_8822B << BIT_SHIFT_HW_SSN_SEQ2_8822B)
+#define BIT_CLEAR_HW_SSN_SEQ2_8822B(x) ((x) & (~BITS_HW_SSN_SEQ2_8822B))
+#define BIT_GET_HW_SSN_SEQ2_8822B(x)                                           \
+	(((x) >> BIT_SHIFT_HW_SSN_SEQ2_8822B) & BIT_MASK_HW_SSN_SEQ2_8822B)
+#define BIT_SET_HW_SSN_SEQ2_8822B(x, v)                                        \
+	(BIT_CLEAR_HW_SSN_SEQ2_8822B(x) | BIT_HW_SSN_SEQ2_8822B(v))
+
+/* 2 REG_HW_SEQ3_8822B */
+
+#define BIT_SHIFT_HW_SSN_SEQ3_8822B 0
+#define BIT_MASK_HW_SSN_SEQ3_8822B 0xfff
+#define BIT_HW_SSN_SEQ3_8822B(x)                                               \
+	(((x) & BIT_MASK_HW_SSN_SEQ3_8822B) << BIT_SHIFT_HW_SSN_SEQ3_8822B)
+#define BITS_HW_SSN_SEQ3_8822B                                                 \
+	(BIT_MASK_HW_SSN_SEQ3_8822B << BIT_SHIFT_HW_SSN_SEQ3_8822B)
+#define BIT_CLEAR_HW_SSN_SEQ3_8822B(x) ((x) & (~BITS_HW_SSN_SEQ3_8822B))
+#define BIT_GET_HW_SSN_SEQ3_8822B(x)                                           \
+	(((x) >> BIT_SHIFT_HW_SSN_SEQ3_8822B) & BIT_MASK_HW_SSN_SEQ3_8822B)
+#define BIT_SET_HW_SSN_SEQ3_8822B(x, v)                                        \
+	(BIT_CLEAR_HW_SSN_SEQ3_8822B(x) | BIT_HW_SSN_SEQ3_8822B(v))
+
+/* 2 REG_NULL_PKT_STATUS_V1_8822B */
+
+#define BIT_SHIFT_PTCL_TOTAL_PG_V2_8822B 2
+#define BIT_MASK_PTCL_TOTAL_PG_V2_8822B 0x3fff
+#define BIT_PTCL_TOTAL_PG_V2_8822B(x)                                          \
+	(((x) & BIT_MASK_PTCL_TOTAL_PG_V2_8822B)                               \
+	 << BIT_SHIFT_PTCL_TOTAL_PG_V2_8822B)
+#define BITS_PTCL_TOTAL_PG_V2_8822B                                            \
+	(BIT_MASK_PTCL_TOTAL_PG_V2_8822B << BIT_SHIFT_PTCL_TOTAL_PG_V2_8822B)
+#define BIT_CLEAR_PTCL_TOTAL_PG_V2_8822B(x)                                    \
+	((x) & (~BITS_PTCL_TOTAL_PG_V2_8822B))
+#define BIT_GET_PTCL_TOTAL_PG_V2_8822B(x)                                      \
+	(((x) >> BIT_SHIFT_PTCL_TOTAL_PG_V2_8822B) &                           \
+	 BIT_MASK_PTCL_TOTAL_PG_V2_8822B)
+#define BIT_SET_PTCL_TOTAL_PG_V2_8822B(x, v)                                   \
+	(BIT_CLEAR_PTCL_TOTAL_PG_V2_8822B(x) | BIT_PTCL_TOTAL_PG_V2_8822B(v))
+
+#define BIT_TX_NULL_1_8822B BIT(1)
+#define BIT_TX_NULL_0_8822B BIT(0)
+
+/* 2 REG_PTCL_ERR_STATUS_8822B */
+#define BIT_PTCL_RATE_TABLE_INVALID_8822B BIT(7)
+#define BIT_FTM_T2R_ERROR_8822B BIT(6)
+#define BIT_PTCL_ERR0_8822B BIT(5)
+#define BIT_PTCL_ERR1_8822B BIT(4)
+#define BIT_PTCL_ERR2_8822B BIT(3)
+#define BIT_PTCL_ERR3_8822B BIT(2)
+#define BIT_PTCL_ERR4_8822B BIT(1)
+#define BIT_PTCL_ERR5_8822B BIT(0)
+
+/* 2 REG_NULL_PKT_STATUS_EXTEND_8822B */
+#define BIT_CLI3_TX_NULL_1_8822B BIT(7)
+#define BIT_CLI3_TX_NULL_0_8822B BIT(6)
+#define BIT_CLI2_TX_NULL_1_8822B BIT(5)
+#define BIT_CLI2_TX_NULL_0_8822B BIT(4)
+#define BIT_CLI1_TX_NULL_1_8822B BIT(3)
+#define BIT_CLI1_TX_NULL_0_8822B BIT(2)
+#define BIT_CLI0_TX_NULL_1_8822B BIT(1)
+#define BIT_CLI0_TX_NULL_0_8822B BIT(0)
+
+/* 2 REG_VIDEO_ENHANCEMENT_FUN_8822B */
+#define BIT_VIDEO_JUST_DROP_8822B BIT(1)
+#define BIT_VIDEO_ENHANCEMENT_FUN_EN_8822B BIT(0)
+
+/* 2 REG_BT_POLLUTE_PKT_CNT_8822B */
+
+#define BIT_SHIFT_BT_POLLUTE_PKT_CNT_8822B 0
+#define BIT_MASK_BT_POLLUTE_PKT_CNT_8822B 0xffff
+#define BIT_BT_POLLUTE_PKT_CNT_8822B(x)                                        \
+	(((x) & BIT_MASK_BT_POLLUTE_PKT_CNT_8822B)                             \
+	 << BIT_SHIFT_BT_POLLUTE_PKT_CNT_8822B)
+#define BITS_BT_POLLUTE_PKT_CNT_8822B                                          \
+	(BIT_MASK_BT_POLLUTE_PKT_CNT_8822B                                     \
+	 << BIT_SHIFT_BT_POLLUTE_PKT_CNT_8822B)
+#define BIT_CLEAR_BT_POLLUTE_PKT_CNT_8822B(x)                                  \
+	((x) & (~BITS_BT_POLLUTE_PKT_CNT_8822B))
+#define BIT_GET_BT_POLLUTE_PKT_CNT_8822B(x)                                    \
+	(((x) >> BIT_SHIFT_BT_POLLUTE_PKT_CNT_8822B) &                         \
+	 BIT_MASK_BT_POLLUTE_PKT_CNT_8822B)
+#define BIT_SET_BT_POLLUTE_PKT_CNT_8822B(x, v)                                 \
+	(BIT_CLEAR_BT_POLLUTE_PKT_CNT_8822B(x) |                               \
+	 BIT_BT_POLLUTE_PKT_CNT_8822B(v))
+
+/* 2 REG_NOT_VALID_8822B */
+
+/* 2 REG_PTCL_DBG_8822B */
+
+#define BIT_SHIFT_PTCL_DBG_8822B 0
+#define BIT_MASK_PTCL_DBG_8822B 0xffffffffL
+#define BIT_PTCL_DBG_8822B(x)                                                  \
+	(((x) & BIT_MASK_PTCL_DBG_8822B) << BIT_SHIFT_PTCL_DBG_8822B)
+#define BITS_PTCL_DBG_8822B                                                    \
+	(BIT_MASK_PTCL_DBG_8822B << BIT_SHIFT_PTCL_DBG_8822B)
+#define BIT_CLEAR_PTCL_DBG_8822B(x) ((x) & (~BITS_PTCL_DBG_8822B))
+#define BIT_GET_PTCL_DBG_8822B(x)                                              \
+	(((x) >> BIT_SHIFT_PTCL_DBG_8822B) & BIT_MASK_PTCL_DBG_8822B)
+#define BIT_SET_PTCL_DBG_8822B(x, v)                                           \
+	(BIT_CLEAR_PTCL_DBG_8822B(x) | BIT_PTCL_DBG_8822B(v))
+
+/* 2 REG_NOT_VALID_8822B */
+
+/* 2 REG_CPUMGQ_TIMER_CTRL2_8822B */
+
+#define BIT_SHIFT_TRI_HEAD_ADDR_8822B 16
+#define BIT_MASK_TRI_HEAD_ADDR_8822B 0xfff
+#define BIT_TRI_HEAD_ADDR_8822B(x)                                             \
+	(((x) & BIT_MASK_TRI_HEAD_ADDR_8822B) << BIT_SHIFT_TRI_HEAD_ADDR_8822B)
+#define BITS_TRI_HEAD_ADDR_8822B                                               \
+	(BIT_MASK_TRI_HEAD_ADDR_8822B << BIT_SHIFT_TRI_HEAD_ADDR_8822B)
+#define BIT_CLEAR_TRI_HEAD_ADDR_8822B(x) ((x) & (~BITS_TRI_HEAD_ADDR_8822B))
+#define BIT_GET_TRI_HEAD_ADDR_8822B(x)                                         \
+	(((x) >> BIT_SHIFT_TRI_HEAD_ADDR_8822B) & BIT_MASK_TRI_HEAD_ADDR_8822B)
+#define BIT_SET_TRI_HEAD_ADDR_8822B(x, v)                                      \
+	(BIT_CLEAR_TRI_HEAD_ADDR_8822B(x) | BIT_TRI_HEAD_ADDR_8822B(v))
+
+#define BIT_DROP_TH_EN_8822B BIT(8)
+
+#define BIT_SHIFT_DROP_TH_8822B 0
+#define BIT_MASK_DROP_TH_8822B 0xff
+#define BIT_DROP_TH_8822B(x)                                                   \
+	(((x) & BIT_MASK_DROP_TH_8822B) << BIT_SHIFT_DROP_TH_8822B)
+#define BITS_DROP_TH_8822B (BIT_MASK_DROP_TH_8822B << BIT_SHIFT_DROP_TH_8822B)
+#define BIT_CLEAR_DROP_TH_8822B(x) ((x) & (~BITS_DROP_TH_8822B))
+#define BIT_GET_DROP_TH_8822B(x)                                               \
+	(((x) >> BIT_SHIFT_DROP_TH_8822B) & BIT_MASK_DROP_TH_8822B)
+#define BIT_SET_DROP_TH_8822B(x, v)                                            \
+	(BIT_CLEAR_DROP_TH_8822B(x) | BIT_DROP_TH_8822B(v))
+
+/* 2 REG_NOT_VALID_8822B */
+
+/* 2 REG_DUMMY_PAGE4_V1_8822B */
+#define BIT_BCN_EN_EXTHWSEQ_8822B BIT(1)
+#define BIT_BCN_EN_HWSEQ_8822B BIT(0)
+
+/* 2 REG_MOREDATA_8822B */
+#define BIT_MOREDATA_CTRL2_EN_V1_8822B BIT(3)
+#define BIT_MOREDATA_CTRL1_EN_V1_8822B BIT(2)
+#define BIT_PKTIN_MOREDATA_REPLACE_ENABLE_V1_8822B BIT(0)
+
+/* 2 REG_NOT_VALID_8822B */
+
+/* 2 REG_Q0_Q1_INFO_8822B */
+#define BIT_QUEUE_MACID_AC_NOT_THE_SAME_8822B BIT(31)
+
+#define BIT_SHIFT_GTAB_ID_8822B 28
+#define BIT_MASK_GTAB_ID_8822B 0x7
+#define BIT_GTAB_ID_8822B(x)                                                   \
+	(((x) & BIT_MASK_GTAB_ID_8822B) << BIT_SHIFT_GTAB_ID_8822B)
+#define BITS_GTAB_ID_8822B (BIT_MASK_GTAB_ID_8822B << BIT_SHIFT_GTAB_ID_8822B)
+#define BIT_CLEAR_GTAB_ID_8822B(x) ((x) & (~BITS_GTAB_ID_8822B))
+#define BIT_GET_GTAB_ID_8822B(x)                                               \
+	(((x) >> BIT_SHIFT_GTAB_ID_8822B) & BIT_MASK_GTAB_ID_8822B)
+#define BIT_SET_GTAB_ID_8822B(x, v)                                            \
+	(BIT_CLEAR_GTAB_ID_8822B(x) | BIT_GTAB_ID_8822B(v))
+
+#define BIT_SHIFT_AC1_PKT_INFO_8822B 16
+#define BIT_MASK_AC1_PKT_INFO_8822B 0xfff
+#define BIT_AC1_PKT_INFO_8822B(x)                                              \
+	(((x) & BIT_MASK_AC1_PKT_INFO_8822B) << BIT_SHIFT_AC1_PKT_INFO_8822B)
+#define BITS_AC1_PKT_INFO_8822B                                                \
+	(BIT_MASK_AC1_PKT_INFO_8822B << BIT_SHIFT_AC1_PKT_INFO_8822B)
+#define BIT_CLEAR_AC1_PKT_INFO_8822B(x) ((x) & (~BITS_AC1_PKT_INFO_8822B))
+#define BIT_GET_AC1_PKT_INFO_8822B(x)                                          \
+	(((x) >> BIT_SHIFT_AC1_PKT_INFO_8822B) & BIT_MASK_AC1_PKT_INFO_8822B)
+#define BIT_SET_AC1_PKT_INFO_8822B(x, v)                                       \
+	(BIT_CLEAR_AC1_PKT_INFO_8822B(x) | BIT_AC1_PKT_INFO_8822B(v))
+
+#define BIT_QUEUE_MACID_AC_NOT_THE_SAME_V1_8822B BIT(15)
+
+#define BIT_SHIFT_GTAB_ID_V1_8822B 12
+#define BIT_MASK_GTAB_ID_V1_8822B 0x7
+#define BIT_GTAB_ID_V1_8822B(x)                                                \
+	(((x) & BIT_MASK_GTAB_ID_V1_8822B) << BIT_SHIFT_GTAB_ID_V1_8822B)
+#define BITS_GTAB_ID_V1_8822B                                                  \
+	(BIT_MASK_GTAB_ID_V1_8822B << BIT_SHIFT_GTAB_ID_V1_8822B)
+#define BIT_CLEAR_GTAB_ID_V1_8822B(x) ((x) & (~BITS_GTAB_ID_V1_8822B))
+#define BIT_GET_GTAB_ID_V1_8822B(x)                                            \
+	(((x) >> BIT_SHIFT_GTAB_ID_V1_8822B) & BIT_MASK_GTAB_ID_V1_8822B)
+#define BIT_SET_GTAB_ID_V1_8822B(x, v)                                         \
+	(BIT_CLEAR_GTAB_ID_V1_8822B(x) | BIT_GTAB_ID_V1_8822B(v))
+
+#define BIT_SHIFT_AC0_PKT_INFO_8822B 0
+#define BIT_MASK_AC0_PKT_INFO_8822B 0xfff
+#define BIT_AC0_PKT_INFO_8822B(x)                                              \
+	(((x) & BIT_MASK_AC0_PKT_INFO_8822B) << BIT_SHIFT_AC0_PKT_INFO_8822B)
+#define BITS_AC0_PKT_INFO_8822B                                                \
+	(BIT_MASK_AC0_PKT_INFO_8822B << BIT_SHIFT_AC0_PKT_INFO_8822B)
+#define BIT_CLEAR_AC0_PKT_INFO_8822B(x) ((x) & (~BITS_AC0_PKT_INFO_8822B))
+#define BIT_GET_AC0_PKT_INFO_8822B(x)                                          \
+	(((x) >> BIT_SHIFT_AC0_PKT_INFO_8822B) & BIT_MASK_AC0_PKT_INFO_8822B)
+#define BIT_SET_AC0_PKT_INFO_8822B(x, v)                                       \
+	(BIT_CLEAR_AC0_PKT_INFO_8822B(x) | BIT_AC0_PKT_INFO_8822B(v))
+
+/* 2 REG_Q2_Q3_INFO_8822B */
+#define BIT_QUEUE_MACID_AC_NOT_THE_SAME_8822B BIT(31)
+
+#define BIT_SHIFT_GTAB_ID_8822B 28
+#define BIT_MASK_GTAB_ID_8822B 0x7
+#define BIT_GTAB_ID_8822B(x)                                                   \
+	(((x) & BIT_MASK_GTAB_ID_8822B) << BIT_SHIFT_GTAB_ID_8822B)
+#define BITS_GTAB_ID_8822B (BIT_MASK_GTAB_ID_8822B << BIT_SHIFT_GTAB_ID_8822B)
+#define BIT_CLEAR_GTAB_ID_8822B(x) ((x) & (~BITS_GTAB_ID_8822B))
+#define BIT_GET_GTAB_ID_8822B(x)                                               \
+	(((x) >> BIT_SHIFT_GTAB_ID_8822B) & BIT_MASK_GTAB_ID_8822B)
+#define BIT_SET_GTAB_ID_8822B(x, v)                                            \
+	(BIT_CLEAR_GTAB_ID_8822B(x) | BIT_GTAB_ID_8822B(v))
+
+#define BIT_SHIFT_AC3_PKT_INFO_8822B 16
+#define BIT_MASK_AC3_PKT_INFO_8822B 0xfff
+#define BIT_AC3_PKT_INFO_8822B(x)                                              \
+	(((x) & BIT_MASK_AC3_PKT_INFO_8822B) << BIT_SHIFT_AC3_PKT_INFO_8822B)
+#define BITS_AC3_PKT_INFO_8822B                                                \
+	(BIT_MASK_AC3_PKT_INFO_8822B << BIT_SHIFT_AC3_PKT_INFO_8822B)
+#define BIT_CLEAR_AC3_PKT_INFO_8822B(x) ((x) & (~BITS_AC3_PKT_INFO_8822B))
+#define BIT_GET_AC3_PKT_INFO_8822B(x)                                          \
+	(((x) >> BIT_SHIFT_AC3_PKT_INFO_8822B) & BIT_MASK_AC3_PKT_INFO_8822B)
+#define BIT_SET_AC3_PKT_INFO_8822B(x, v)                                       \
+	(BIT_CLEAR_AC3_PKT_INFO_8822B(x) | BIT_AC3_PKT_INFO_8822B(v))
+
+#define BIT_QUEUE_MACID_AC_NOT_THE_SAME_V1_8822B BIT(15)
+
+#define BIT_SHIFT_GTAB_ID_V1_8822B 12
+#define BIT_MASK_GTAB_ID_V1_8822B 0x7
+#define BIT_GTAB_ID_V1_8822B(x)                                                \
+	(((x) & BIT_MASK_GTAB_ID_V1_8822B) << BIT_SHIFT_GTAB_ID_V1_8822B)
+#define BITS_GTAB_ID_V1_8822B                                                  \
+	(BIT_MASK_GTAB_ID_V1_8822B << BIT_SHIFT_GTAB_ID_V1_8822B)
+#define BIT_CLEAR_GTAB_ID_V1_8822B(x) ((x) & (~BITS_GTAB_ID_V1_8822B))
+#define BIT_GET_GTAB_ID_V1_8822B(x)                                            \
+	(((x) >> BIT_SHIFT_GTAB_ID_V1_8822B) & BIT_MASK_GTAB_ID_V1_8822B)
+#define BIT_SET_GTAB_ID_V1_8822B(x, v)                                         \
+	(BIT_CLEAR_GTAB_ID_V1_8822B(x) | BIT_GTAB_ID_V1_8822B(v))
+
+#define BIT_SHIFT_AC2_PKT_INFO_8822B 0
+#define BIT_MASK_AC2_PKT_INFO_8822B 0xfff
+#define BIT_AC2_PKT_INFO_8822B(x)                                              \
+	(((x) & BIT_MASK_AC2_PKT_INFO_8822B) << BIT_SHIFT_AC2_PKT_INFO_8822B)
+#define BITS_AC2_PKT_INFO_8822B                                                \
+	(BIT_MASK_AC2_PKT_INFO_8822B << BIT_SHIFT_AC2_PKT_INFO_8822B)
+#define BIT_CLEAR_AC2_PKT_INFO_8822B(x) ((x) & (~BITS_AC2_PKT_INFO_8822B))
+#define BIT_GET_AC2_PKT_INFO_8822B(x)                                          \
+	(((x) >> BIT_SHIFT_AC2_PKT_INFO_8822B) & BIT_MASK_AC2_PKT_INFO_8822B)
+#define BIT_SET_AC2_PKT_INFO_8822B(x, v)                                       \
+	(BIT_CLEAR_AC2_PKT_INFO_8822B(x) | BIT_AC2_PKT_INFO_8822B(v))
+
+/* 2 REG_Q4_Q5_INFO_8822B */
+#define BIT_QUEUE_MACID_AC_NOT_THE_SAME_8822B BIT(31)
+
+#define BIT_SHIFT_GTAB_ID_8822B 28
+#define BIT_MASK_GTAB_ID_8822B 0x7
+#define BIT_GTAB_ID_8822B(x)                                                   \
+	(((x) & BIT_MASK_GTAB_ID_8822B) << BIT_SHIFT_GTAB_ID_8822B)
+#define BITS_GTAB_ID_8822B (BIT_MASK_GTAB_ID_8822B << BIT_SHIFT_GTAB_ID_8822B)
+#define BIT_CLEAR_GTAB_ID_8822B(x) ((x) & (~BITS_GTAB_ID_8822B))
+#define BIT_GET_GTAB_ID_8822B(x)                                               \
+	(((x) >> BIT_SHIFT_GTAB_ID_8822B) & BIT_MASK_GTAB_ID_8822B)
+#define BIT_SET_GTAB_ID_8822B(x, v)                                            \
+	(BIT_CLEAR_GTAB_ID_8822B(x) | BIT_GTAB_ID_8822B(v))
+
+#define BIT_SHIFT_AC5_PKT_INFO_8822B 16
+#define BIT_MASK_AC5_PKT_INFO_8822B 0xfff
+#define BIT_AC5_PKT_INFO_8822B(x)                                              \
+	(((x) & BIT_MASK_AC5_PKT_INFO_8822B) << BIT_SHIFT_AC5_PKT_INFO_8822B)
+#define BITS_AC5_PKT_INFO_8822B                                                \
+	(BIT_MASK_AC5_PKT_INFO_8822B << BIT_SHIFT_AC5_PKT_INFO_8822B)
+#define BIT_CLEAR_AC5_PKT_INFO_8822B(x) ((x) & (~BITS_AC5_PKT_INFO_8822B))
+#define BIT_GET_AC5_PKT_INFO_8822B(x)                                          \
+	(((x) >> BIT_SHIFT_AC5_PKT_INFO_8822B) & BIT_MASK_AC5_PKT_INFO_8822B)
+#define BIT_SET_AC5_PKT_INFO_8822B(x, v)                                       \
+	(BIT_CLEAR_AC5_PKT_INFO_8822B(x) | BIT_AC5_PKT_INFO_8822B(v))
+
+#define BIT_QUEUE_MACID_AC_NOT_THE_SAME_V1_8822B BIT(15)
+
+#define BIT_SHIFT_GTAB_ID_V1_8822B 12
+#define BIT_MASK_GTAB_ID_V1_8822B 0x7
+#define BIT_GTAB_ID_V1_8822B(x)                                                \
+	(((x) & BIT_MASK_GTAB_ID_V1_8822B) << BIT_SHIFT_GTAB_ID_V1_8822B)
+#define BITS_GTAB_ID_V1_8822B                                                  \
+	(BIT_MASK_GTAB_ID_V1_8822B << BIT_SHIFT_GTAB_ID_V1_8822B)
+#define BIT_CLEAR_GTAB_ID_V1_8822B(x) ((x) & (~BITS_GTAB_ID_V1_8822B))
+#define BIT_GET_GTAB_ID_V1_8822B(x)                                            \
+	(((x) >> BIT_SHIFT_GTAB_ID_V1_8822B) & BIT_MASK_GTAB_ID_V1_8822B)
+#define BIT_SET_GTAB_ID_V1_8822B(x, v)                                         \
+	(BIT_CLEAR_GTAB_ID_V1_8822B(x) | BIT_GTAB_ID_V1_8822B(v))
+
+#define BIT_SHIFT_AC4_PKT_INFO_8822B 0
+#define BIT_MASK_AC4_PKT_INFO_8822B 0xfff
+#define BIT_AC4_PKT_INFO_8822B(x)                                              \
+	(((x) & BIT_MASK_AC4_PKT_INFO_8822B) << BIT_SHIFT_AC4_PKT_INFO_8822B)
+#define BITS_AC4_PKT_INFO_8822B                                                \
+	(BIT_MASK_AC4_PKT_INFO_8822B << BIT_SHIFT_AC4_PKT_INFO_8822B)
+#define BIT_CLEAR_AC4_PKT_INFO_8822B(x) ((x) & (~BITS_AC4_PKT_INFO_8822B))
+#define BIT_GET_AC4_PKT_INFO_8822B(x)                                          \
+	(((x) >> BIT_SHIFT_AC4_PKT_INFO_8822B) & BIT_MASK_AC4_PKT_INFO_8822B)
+#define BIT_SET_AC4_PKT_INFO_8822B(x, v)                                       \
+	(BIT_CLEAR_AC4_PKT_INFO_8822B(x) | BIT_AC4_PKT_INFO_8822B(v))
+
+/* 2 REG_Q6_Q7_INFO_8822B */
+#define BIT_QUEUE_MACID_AC_NOT_THE_SAME_8822B BIT(31)
+
+#define BIT_SHIFT_GTAB_ID_8822B 28
+#define BIT_MASK_GTAB_ID_8822B 0x7
+#define BIT_GTAB_ID_8822B(x)                                                   \
+	(((x) & BIT_MASK_GTAB_ID_8822B) << BIT_SHIFT_GTAB_ID_8822B)
+#define BITS_GTAB_ID_8822B (BIT_MASK_GTAB_ID_8822B << BIT_SHIFT_GTAB_ID_8822B)
+#define BIT_CLEAR_GTAB_ID_8822B(x) ((x) & (~BITS_GTAB_ID_8822B))
+#define BIT_GET_GTAB_ID_8822B(x)                                               \
+	(((x) >> BIT_SHIFT_GTAB_ID_8822B) & BIT_MASK_GTAB_ID_8822B)
+#define BIT_SET_GTAB_ID_8822B(x, v)                                            \
+	(BIT_CLEAR_GTAB_ID_8822B(x) | BIT_GTAB_ID_8822B(v))
+
+#define BIT_SHIFT_AC7_PKT_INFO_8822B 16
+#define BIT_MASK_AC7_PKT_INFO_8822B 0xfff
+#define BIT_AC7_PKT_INFO_8822B(x)                                              \
+	(((x) & BIT_MASK_AC7_PKT_INFO_8822B) << BIT_SHIFT_AC7_PKT_INFO_8822B)
+#define BITS_AC7_PKT_INFO_8822B                                                \
+	(BIT_MASK_AC7_PKT_INFO_8822B << BIT_SHIFT_AC7_PKT_INFO_8822B)
+#define BIT_CLEAR_AC7_PKT_INFO_8822B(x) ((x) & (~BITS_AC7_PKT_INFO_8822B))
+#define BIT_GET_AC7_PKT_INFO_8822B(x)                                          \
+	(((x) >> BIT_SHIFT_AC7_PKT_INFO_8822B) & BIT_MASK_AC7_PKT_INFO_8822B)
+#define BIT_SET_AC7_PKT_INFO_8822B(x, v)                                       \
+	(BIT_CLEAR_AC7_PKT_INFO_8822B(x) | BIT_AC7_PKT_INFO_8822B(v))
+
+#define BIT_QUEUE_MACID_AC_NOT_THE_SAME_V1_8822B BIT(15)
+
+#define BIT_SHIFT_GTAB_ID_V1_8822B 12
+#define BIT_MASK_GTAB_ID_V1_8822B 0x7
+#define BIT_GTAB_ID_V1_8822B(x)                                                \
+	(((x) & BIT_MASK_GTAB_ID_V1_8822B) << BIT_SHIFT_GTAB_ID_V1_8822B)
+#define BITS_GTAB_ID_V1_8822B                                                  \
+	(BIT_MASK_GTAB_ID_V1_8822B << BIT_SHIFT_GTAB_ID_V1_8822B)
+#define BIT_CLEAR_GTAB_ID_V1_8822B(x) ((x) & (~BITS_GTAB_ID_V1_8822B))
+#define BIT_GET_GTAB_ID_V1_8822B(x)                                            \
+	(((x) >> BIT_SHIFT_GTAB_ID_V1_8822B) & BIT_MASK_GTAB_ID_V1_8822B)
+#define BIT_SET_GTAB_ID_V1_8822B(x, v)                                         \
+	(BIT_CLEAR_GTAB_ID_V1_8822B(x) | BIT_GTAB_ID_V1_8822B(v))
+
+#define BIT_SHIFT_AC6_PKT_INFO_8822B 0
+#define BIT_MASK_AC6_PKT_INFO_8822B 0xfff
+#define BIT_AC6_PKT_INFO_8822B(x)                                              \
+	(((x) & BIT_MASK_AC6_PKT_INFO_8822B) << BIT_SHIFT_AC6_PKT_INFO_8822B)
+#define BITS_AC6_PKT_INFO_8822B                                                \
+	(BIT_MASK_AC6_PKT_INFO_8822B << BIT_SHIFT_AC6_PKT_INFO_8822B)
+#define BIT_CLEAR_AC6_PKT_INFO_8822B(x) ((x) & (~BITS_AC6_PKT_INFO_8822B))
+#define BIT_GET_AC6_PKT_INFO_8822B(x)                                          \
+	(((x) >> BIT_SHIFT_AC6_PKT_INFO_8822B) & BIT_MASK_AC6_PKT_INFO_8822B)
+#define BIT_SET_AC6_PKT_INFO_8822B(x, v)                                       \
+	(BIT_CLEAR_AC6_PKT_INFO_8822B(x) | BIT_AC6_PKT_INFO_8822B(v))
+
+/* 2 REG_MGQ_HIQ_INFO_8822B */
+
+#define BIT_SHIFT_HIQ_PKT_INFO_8822B 16
+#define BIT_MASK_HIQ_PKT_INFO_8822B 0xfff
+#define BIT_HIQ_PKT_INFO_8822B(x)                                              \
+	(((x) & BIT_MASK_HIQ_PKT_INFO_8822B) << BIT_SHIFT_HIQ_PKT_INFO_8822B)
+#define BITS_HIQ_PKT_INFO_8822B                                                \
+	(BIT_MASK_HIQ_PKT_INFO_8822B << BIT_SHIFT_HIQ_PKT_INFO_8822B)
+#define BIT_CLEAR_HIQ_PKT_INFO_8822B(x) ((x) & (~BITS_HIQ_PKT_INFO_8822B))
+#define BIT_GET_HIQ_PKT_INFO_8822B(x)                                          \
+	(((x) >> BIT_SHIFT_HIQ_PKT_INFO_8822B) & BIT_MASK_HIQ_PKT_INFO_8822B)
+#define BIT_SET_HIQ_PKT_INFO_8822B(x, v)                                       \
+	(BIT_CLEAR_HIQ_PKT_INFO_8822B(x) | BIT_HIQ_PKT_INFO_8822B(v))
+
+#define BIT_SHIFT_MGQ_PKT_INFO_8822B 0
+#define BIT_MASK_MGQ_PKT_INFO_8822B 0xfff
+#define BIT_MGQ_PKT_INFO_8822B(x)                                              \
+	(((x) & BIT_MASK_MGQ_PKT_INFO_8822B) << BIT_SHIFT_MGQ_PKT_INFO_8822B)
+#define BITS_MGQ_PKT_INFO_8822B                                                \
+	(BIT_MASK_MGQ_PKT_INFO_8822B << BIT_SHIFT_MGQ_PKT_INFO_8822B)
+#define BIT_CLEAR_MGQ_PKT_INFO_8822B(x) ((x) & (~BITS_MGQ_PKT_INFO_8822B))
+#define BIT_GET_MGQ_PKT_INFO_8822B(x)                                          \
+	(((x) >> BIT_SHIFT_MGQ_PKT_INFO_8822B) & BIT_MASK_MGQ_PKT_INFO_8822B)
+#define BIT_SET_MGQ_PKT_INFO_8822B(x, v)                                       \
+	(BIT_CLEAR_MGQ_PKT_INFO_8822B(x) | BIT_MGQ_PKT_INFO_8822B(v))
+
+/* 2 REG_CMDQ_BCNQ_INFO_8822B */
+
+#define BIT_SHIFT_CMDQ_PKT_INFO_8822B 16
+#define BIT_MASK_CMDQ_PKT_INFO_8822B 0xfff
+#define BIT_CMDQ_PKT_INFO_8822B(x)                                             \
+	(((x) & BIT_MASK_CMDQ_PKT_INFO_8822B) << BIT_SHIFT_CMDQ_PKT_INFO_8822B)
+#define BITS_CMDQ_PKT_INFO_8822B                                               \
+	(BIT_MASK_CMDQ_PKT_INFO_8822B << BIT_SHIFT_CMDQ_PKT_INFO_8822B)
+#define BIT_CLEAR_CMDQ_PKT_INFO_8822B(x) ((x) & (~BITS_CMDQ_PKT_INFO_8822B))
+#define BIT_GET_CMDQ_PKT_INFO_8822B(x)                                         \
+	(((x) >> BIT_SHIFT_CMDQ_PKT_INFO_8822B) & BIT_MASK_CMDQ_PKT_INFO_8822B)
+#define BIT_SET_CMDQ_PKT_INFO_8822B(x, v)                                      \
+	(BIT_CLEAR_CMDQ_PKT_INFO_8822B(x) | BIT_CMDQ_PKT_INFO_8822B(v))
+
+#define BIT_SHIFT_BCNQ_PKT_INFO_8822B 0
+#define BIT_MASK_BCNQ_PKT_INFO_8822B 0xfff
+#define BIT_BCNQ_PKT_INFO_8822B(x)                                             \
+	(((x) & BIT_MASK_BCNQ_PKT_INFO_8822B) << BIT_SHIFT_BCNQ_PKT_INFO_8822B)
+#define BITS_BCNQ_PKT_INFO_8822B                                               \
+	(BIT_MASK_BCNQ_PKT_INFO_8822B << BIT_SHIFT_BCNQ_PKT_INFO_8822B)
+#define BIT_CLEAR_BCNQ_PKT_INFO_8822B(x) ((x) & (~BITS_BCNQ_PKT_INFO_8822B))
+#define BIT_GET_BCNQ_PKT_INFO_8822B(x)                                         \
+	(((x) >> BIT_SHIFT_BCNQ_PKT_INFO_8822B) & BIT_MASK_BCNQ_PKT_INFO_8822B)
+#define BIT_SET_BCNQ_PKT_INFO_8822B(x, v)                                      \
+	(BIT_CLEAR_BCNQ_PKT_INFO_8822B(x) | BIT_BCNQ_PKT_INFO_8822B(v))
+
+/* 2 REG_USEREG_SETTING_8822B */
+#define BIT_NDPA_USEREG_8822B BIT(21)
+
+#define BIT_SHIFT_RETRY_USEREG_8822B 19
+#define BIT_MASK_RETRY_USEREG_8822B 0x3
+#define BIT_RETRY_USEREG_8822B(x)                                              \
+	(((x) & BIT_MASK_RETRY_USEREG_8822B) << BIT_SHIFT_RETRY_USEREG_8822B)
+#define BITS_RETRY_USEREG_8822B                                                \
+	(BIT_MASK_RETRY_USEREG_8822B << BIT_SHIFT_RETRY_USEREG_8822B)
+#define BIT_CLEAR_RETRY_USEREG_8822B(x) ((x) & (~BITS_RETRY_USEREG_8822B))
+#define BIT_GET_RETRY_USEREG_8822B(x)                                          \
+	(((x) >> BIT_SHIFT_RETRY_USEREG_8822B) & BIT_MASK_RETRY_USEREG_8822B)
+#define BIT_SET_RETRY_USEREG_8822B(x, v)                                       \
+	(BIT_CLEAR_RETRY_USEREG_8822B(x) | BIT_RETRY_USEREG_8822B(v))
+
+#define BIT_SHIFT_TRYPKT_USEREG_8822B 17
+#define BIT_MASK_TRYPKT_USEREG_8822B 0x3
+#define BIT_TRYPKT_USEREG_8822B(x)                                             \
+	(((x) & BIT_MASK_TRYPKT_USEREG_8822B) << BIT_SHIFT_TRYPKT_USEREG_8822B)
+#define BITS_TRYPKT_USEREG_8822B                                               \
+	(BIT_MASK_TRYPKT_USEREG_8822B << BIT_SHIFT_TRYPKT_USEREG_8822B)
+#define BIT_CLEAR_TRYPKT_USEREG_8822B(x) ((x) & (~BITS_TRYPKT_USEREG_8822B))
+#define BIT_GET_TRYPKT_USEREG_8822B(x)                                         \
+	(((x) >> BIT_SHIFT_TRYPKT_USEREG_8822B) & BIT_MASK_TRYPKT_USEREG_8822B)
+#define BIT_SET_TRYPKT_USEREG_8822B(x, v)                                      \
+	(BIT_CLEAR_TRYPKT_USEREG_8822B(x) | BIT_TRYPKT_USEREG_8822B(v))
+
+#define BIT_CTLPKT_USEREG_8822B BIT(16)
+
+/* 2 REG_AESIV_SETTING_8822B */
+
+#define BIT_SHIFT_AESIV_OFFSET_8822B 0
+#define BIT_MASK_AESIV_OFFSET_8822B 0xfff
+#define BIT_AESIV_OFFSET_8822B(x)                                              \
+	(((x) & BIT_MASK_AESIV_OFFSET_8822B) << BIT_SHIFT_AESIV_OFFSET_8822B)
+#define BITS_AESIV_OFFSET_8822B                                                \
+	(BIT_MASK_AESIV_OFFSET_8822B << BIT_SHIFT_AESIV_OFFSET_8822B)
+#define BIT_CLEAR_AESIV_OFFSET_8822B(x) ((x) & (~BITS_AESIV_OFFSET_8822B))
+#define BIT_GET_AESIV_OFFSET_8822B(x)                                          \
+	(((x) >> BIT_SHIFT_AESIV_OFFSET_8822B) & BIT_MASK_AESIV_OFFSET_8822B)
+#define BIT_SET_AESIV_OFFSET_8822B(x, v)                                       \
+	(BIT_CLEAR_AESIV_OFFSET_8822B(x) | BIT_AESIV_OFFSET_8822B(v))
+
+/* 2 REG_BF0_TIME_SETTING_8822B */
+#define BIT_BF0_TIMER_SET_8822B BIT(31)
+#define BIT_BF0_TIMER_CLR_8822B BIT(30)
+#define BIT_BF0_UPDATE_EN_8822B BIT(29)
+#define BIT_BF0_TIMER_EN_8822B BIT(28)
+
+#define BIT_SHIFT_BF0_PRETIME_OVER_8822B 16
+#define BIT_MASK_BF0_PRETIME_OVER_8822B 0xfff
+#define BIT_BF0_PRETIME_OVER_8822B(x)                                          \
+	(((x) & BIT_MASK_BF0_PRETIME_OVER_8822B)                               \
+	 << BIT_SHIFT_BF0_PRETIME_OVER_8822B)
+#define BITS_BF0_PRETIME_OVER_8822B                                            \
+	(BIT_MASK_BF0_PRETIME_OVER_8822B << BIT_SHIFT_BF0_PRETIME_OVER_8822B)
+#define BIT_CLEAR_BF0_PRETIME_OVER_8822B(x)                                    \
+	((x) & (~BITS_BF0_PRETIME_OVER_8822B))
+#define BIT_GET_BF0_PRETIME_OVER_8822B(x)                                      \
+	(((x) >> BIT_SHIFT_BF0_PRETIME_OVER_8822B) &                           \
+	 BIT_MASK_BF0_PRETIME_OVER_8822B)
+#define BIT_SET_BF0_PRETIME_OVER_8822B(x, v)                                   \
+	(BIT_CLEAR_BF0_PRETIME_OVER_8822B(x) | BIT_BF0_PRETIME_OVER_8822B(v))
+
+#define BIT_SHIFT_BF0_LIFETIME_8822B 0
+#define BIT_MASK_BF0_LIFETIME_8822B 0xffff
+#define BIT_BF0_LIFETIME_8822B(x)                                              \
+	(((x) & BIT_MASK_BF0_LIFETIME_8822B) << BIT_SHIFT_BF0_LIFETIME_8822B)
+#define BITS_BF0_LIFETIME_8822B                                                \
+	(BIT_MASK_BF0_LIFETIME_8822B << BIT_SHIFT_BF0_LIFETIME_8822B)
+#define BIT_CLEAR_BF0_LIFETIME_8822B(x) ((x) & (~BITS_BF0_LIFETIME_8822B))
+#define BIT_GET_BF0_LIFETIME_8822B(x)                                          \
+	(((x) >> BIT_SHIFT_BF0_LIFETIME_8822B) & BIT_MASK_BF0_LIFETIME_8822B)
+#define BIT_SET_BF0_LIFETIME_8822B(x, v)                                       \
+	(BIT_CLEAR_BF0_LIFETIME_8822B(x) | BIT_BF0_LIFETIME_8822B(v))
+
+/* 2 REG_BF1_TIME_SETTING_8822B */
+#define BIT_BF1_TIMER_SET_8822B BIT(31)
+#define BIT_BF1_TIMER_CLR_8822B BIT(30)
+#define BIT_BF1_UPDATE_EN_8822B BIT(29)
+#define BIT_BF1_TIMER_EN_8822B BIT(28)
+
+#define BIT_SHIFT_BF1_PRETIME_OVER_8822B 16
+#define BIT_MASK_BF1_PRETIME_OVER_8822B 0xfff
+#define BIT_BF1_PRETIME_OVER_8822B(x)                                          \
+	(((x) & BIT_MASK_BF1_PRETIME_OVER_8822B)                               \
+	 << BIT_SHIFT_BF1_PRETIME_OVER_8822B)
+#define BITS_BF1_PRETIME_OVER_8822B                                            \
+	(BIT_MASK_BF1_PRETIME_OVER_8822B << BIT_SHIFT_BF1_PRETIME_OVER_8822B)
+#define BIT_CLEAR_BF1_PRETIME_OVER_8822B(x)                                    \
+	((x) & (~BITS_BF1_PRETIME_OVER_8822B))
+#define BIT_GET_BF1_PRETIME_OVER_8822B(x)                                      \
+	(((x) >> BIT_SHIFT_BF1_PRETIME_OVER_8822B) &                           \
+	 BIT_MASK_BF1_PRETIME_OVER_8822B)
+#define BIT_SET_BF1_PRETIME_OVER_8822B(x, v)                                   \
+	(BIT_CLEAR_BF1_PRETIME_OVER_8822B(x) | BIT_BF1_PRETIME_OVER_8822B(v))
+
+#define BIT_SHIFT_BF1_LIFETIME_8822B 0
+#define BIT_MASK_BF1_LIFETIME_8822B 0xffff
+#define BIT_BF1_LIFETIME_8822B(x)                                              \
+	(((x) & BIT_MASK_BF1_LIFETIME_8822B) << BIT_SHIFT_BF1_LIFETIME_8822B)
+#define BITS_BF1_LIFETIME_8822B                                                \
+	(BIT_MASK_BF1_LIFETIME_8822B << BIT_SHIFT_BF1_LIFETIME_8822B)
+#define BIT_CLEAR_BF1_LIFETIME_8822B(x) ((x) & (~BITS_BF1_LIFETIME_8822B))
+#define BIT_GET_BF1_LIFETIME_8822B(x)                                          \
+	(((x) >> BIT_SHIFT_BF1_LIFETIME_8822B) & BIT_MASK_BF1_LIFETIME_8822B)
+#define BIT_SET_BF1_LIFETIME_8822B(x, v)                                       \
+	(BIT_CLEAR_BF1_LIFETIME_8822B(x) | BIT_BF1_LIFETIME_8822B(v))
+
+/* 2 REG_BF_TIMEOUT_EN_8822B */
+#define BIT_EN_VHT_LDPC_8822B BIT(9)
+#define BIT_EN_HT_LDPC_8822B BIT(8)
+#define BIT_BF1_TIMEOUT_EN_8822B BIT(1)
+#define BIT_BF0_TIMEOUT_EN_8822B BIT(0)
+
+/* 2 REG_MACID_RELEASE0_8822B */
+
+#define BIT_SHIFT_MACID31_0_RELEASE_8822B 0
+#define BIT_MASK_MACID31_0_RELEASE_8822B 0xffffffffL
+#define BIT_MACID31_0_RELEASE_8822B(x)                                         \
+	(((x) & BIT_MASK_MACID31_0_RELEASE_8822B)                              \
+	 << BIT_SHIFT_MACID31_0_RELEASE_8822B)
+#define BITS_MACID31_0_RELEASE_8822B                                           \
+	(BIT_MASK_MACID31_0_RELEASE_8822B << BIT_SHIFT_MACID31_0_RELEASE_8822B)
+#define BIT_CLEAR_MACID31_0_RELEASE_8822B(x)                                   \
+	((x) & (~BITS_MACID31_0_RELEASE_8822B))
+#define BIT_GET_MACID31_0_RELEASE_8822B(x)                                     \
+	(((x) >> BIT_SHIFT_MACID31_0_RELEASE_8822B) &                          \
+	 BIT_MASK_MACID31_0_RELEASE_8822B)
+#define BIT_SET_MACID31_0_RELEASE_8822B(x, v)                                  \
+	(BIT_CLEAR_MACID31_0_RELEASE_8822B(x) | BIT_MACID31_0_RELEASE_8822B(v))
+
+/* 2 REG_MACID_RELEASE1_8822B */
+
+#define BIT_SHIFT_MACID63_32_RELEASE_8822B 0
+#define BIT_MASK_MACID63_32_RELEASE_8822B 0xffffffffL
+#define BIT_MACID63_32_RELEASE_8822B(x)                                        \
+	(((x) & BIT_MASK_MACID63_32_RELEASE_8822B)                             \
+	 << BIT_SHIFT_MACID63_32_RELEASE_8822B)
+#define BITS_MACID63_32_RELEASE_8822B                                          \
+	(BIT_MASK_MACID63_32_RELEASE_8822B                                     \
+	 << BIT_SHIFT_MACID63_32_RELEASE_8822B)
+#define BIT_CLEAR_MACID63_32_RELEASE_8822B(x)                                  \
+	((x) & (~BITS_MACID63_32_RELEASE_8822B))
+#define BIT_GET_MACID63_32_RELEASE_8822B(x)                                    \
+	(((x) >> BIT_SHIFT_MACID63_32_RELEASE_8822B) &                         \
+	 BIT_MASK_MACID63_32_RELEASE_8822B)
+#define BIT_SET_MACID63_32_RELEASE_8822B(x, v)                                 \
+	(BIT_CLEAR_MACID63_32_RELEASE_8822B(x) |                               \
+	 BIT_MACID63_32_RELEASE_8822B(v))
+
+/* 2 REG_MACID_RELEASE2_8822B */
+
+#define BIT_SHIFT_MACID95_64_RELEASE_8822B 0
+#define BIT_MASK_MACID95_64_RELEASE_8822B 0xffffffffL
+#define BIT_MACID95_64_RELEASE_8822B(x)                                        \
+	(((x) & BIT_MASK_MACID95_64_RELEASE_8822B)                             \
+	 << BIT_SHIFT_MACID95_64_RELEASE_8822B)
+#define BITS_MACID95_64_RELEASE_8822B                                          \
+	(BIT_MASK_MACID95_64_RELEASE_8822B                                     \
+	 << BIT_SHIFT_MACID95_64_RELEASE_8822B)
+#define BIT_CLEAR_MACID95_64_RELEASE_8822B(x)                                  \
+	((x) & (~BITS_MACID95_64_RELEASE_8822B))
+#define BIT_GET_MACID95_64_RELEASE_8822B(x)                                    \
+	(((x) >> BIT_SHIFT_MACID95_64_RELEASE_8822B) &                         \
+	 BIT_MASK_MACID95_64_RELEASE_8822B)
+#define BIT_SET_MACID95_64_RELEASE_8822B(x, v)                                 \
+	(BIT_CLEAR_MACID95_64_RELEASE_8822B(x) |                               \
+	 BIT_MACID95_64_RELEASE_8822B(v))
+
+/* 2 REG_MACID_RELEASE3_8822B */
+
+#define BIT_SHIFT_MACID127_96_RELEASE_8822B 0
+#define BIT_MASK_MACID127_96_RELEASE_8822B 0xffffffffL
+#define BIT_MACID127_96_RELEASE_8822B(x)                                       \
+	(((x) & BIT_MASK_MACID127_96_RELEASE_8822B)                            \
+	 << BIT_SHIFT_MACID127_96_RELEASE_8822B)
+#define BITS_MACID127_96_RELEASE_8822B                                         \
+	(BIT_MASK_MACID127_96_RELEASE_8822B                                    \
+	 << BIT_SHIFT_MACID127_96_RELEASE_8822B)
+#define BIT_CLEAR_MACID127_96_RELEASE_8822B(x)                                 \
+	((x) & (~BITS_MACID127_96_RELEASE_8822B))
+#define BIT_GET_MACID127_96_RELEASE_8822B(x)                                   \
+	(((x) >> BIT_SHIFT_MACID127_96_RELEASE_8822B) &                        \
+	 BIT_MASK_MACID127_96_RELEASE_8822B)
+#define BIT_SET_MACID127_96_RELEASE_8822B(x, v)                                \
+	(BIT_CLEAR_MACID127_96_RELEASE_8822B(x) |                              \
+	 BIT_MACID127_96_RELEASE_8822B(v))
+
+/* 2 REG_MACID_RELEASE_SETTING_8822B */
+#define BIT_MACID_VALUE_8822B BIT(7)
+
+#define BIT_SHIFT_MACID_OFFSET_8822B 0
+#define BIT_MASK_MACID_OFFSET_8822B 0x7f
+#define BIT_MACID_OFFSET_8822B(x)                                              \
+	(((x) & BIT_MASK_MACID_OFFSET_8822B) << BIT_SHIFT_MACID_OFFSET_8822B)
+#define BITS_MACID_OFFSET_8822B                                                \
+	(BIT_MASK_MACID_OFFSET_8822B << BIT_SHIFT_MACID_OFFSET_8822B)
+#define BIT_CLEAR_MACID_OFFSET_8822B(x) ((x) & (~BITS_MACID_OFFSET_8822B))
+#define BIT_GET_MACID_OFFSET_8822B(x)                                          \
+	(((x) >> BIT_SHIFT_MACID_OFFSET_8822B) & BIT_MASK_MACID_OFFSET_8822B)
+#define BIT_SET_MACID_OFFSET_8822B(x, v)                                       \
+	(BIT_CLEAR_MACID_OFFSET_8822B(x) | BIT_MACID_OFFSET_8822B(v))
+
+/* 2 REG_FAST_EDCA_VOVI_SETTING_8822B */
+
+#define BIT_SHIFT_VI_FAST_EDCA_TO_8822B 24
+#define BIT_MASK_VI_FAST_EDCA_TO_8822B 0xff
+#define BIT_VI_FAST_EDCA_TO_8822B(x)                                           \
+	(((x) & BIT_MASK_VI_FAST_EDCA_TO_8822B)                                \
+	 << BIT_SHIFT_VI_FAST_EDCA_TO_8822B)
+#define BITS_VI_FAST_EDCA_TO_8822B                                             \
+	(BIT_MASK_VI_FAST_EDCA_TO_8822B << BIT_SHIFT_VI_FAST_EDCA_TO_8822B)
+#define BIT_CLEAR_VI_FAST_EDCA_TO_8822B(x) ((x) & (~BITS_VI_FAST_EDCA_TO_8822B))
+#define BIT_GET_VI_FAST_EDCA_TO_8822B(x)                                       \
+	(((x) >> BIT_SHIFT_VI_FAST_EDCA_TO_8822B) &                            \
+	 BIT_MASK_VI_FAST_EDCA_TO_8822B)
+#define BIT_SET_VI_FAST_EDCA_TO_8822B(x, v)                                    \
+	(BIT_CLEAR_VI_FAST_EDCA_TO_8822B(x) | BIT_VI_FAST_EDCA_TO_8822B(v))
+
+#define BIT_VI_THRESHOLD_SEL_8822B BIT(23)
+
+#define BIT_SHIFT_VI_FAST_EDCA_PKT_TH_8822B 16
+#define BIT_MASK_VI_FAST_EDCA_PKT_TH_8822B 0x7f
+#define BIT_VI_FAST_EDCA_PKT_TH_8822B(x)                                       \
+	(((x) & BIT_MASK_VI_FAST_EDCA_PKT_TH_8822B)                            \
+	 << BIT_SHIFT_VI_FAST_EDCA_PKT_TH_8822B)
+#define BITS_VI_FAST_EDCA_PKT_TH_8822B                                         \
+	(BIT_MASK_VI_FAST_EDCA_PKT_TH_8822B                                    \
+	 << BIT_SHIFT_VI_FAST_EDCA_PKT_TH_8822B)
+#define BIT_CLEAR_VI_FAST_EDCA_PKT_TH_8822B(x)                                 \
+	((x) & (~BITS_VI_FAST_EDCA_PKT_TH_8822B))
+#define BIT_GET_VI_FAST_EDCA_PKT_TH_8822B(x)                                   \
+	(((x) >> BIT_SHIFT_VI_FAST_EDCA_PKT_TH_8822B) &                        \
+	 BIT_MASK_VI_FAST_EDCA_PKT_TH_8822B)
+#define BIT_SET_VI_FAST_EDCA_PKT_TH_8822B(x, v)                                \
+	(BIT_CLEAR_VI_FAST_EDCA_PKT_TH_8822B(x) |                              \
+	 BIT_VI_FAST_EDCA_PKT_TH_8822B(v))
+
+#define BIT_SHIFT_VO_FAST_EDCA_TO_8822B 8
+#define BIT_MASK_VO_FAST_EDCA_TO_8822B 0xff
+#define BIT_VO_FAST_EDCA_TO_8822B(x)                                           \
+	(((x) & BIT_MASK_VO_FAST_EDCA_TO_8822B)                                \
+	 << BIT_SHIFT_VO_FAST_EDCA_TO_8822B)
+#define BITS_VO_FAST_EDCA_TO_8822B                                             \
+	(BIT_MASK_VO_FAST_EDCA_TO_8822B << BIT_SHIFT_VO_FAST_EDCA_TO_8822B)
+#define BIT_CLEAR_VO_FAST_EDCA_TO_8822B(x) ((x) & (~BITS_VO_FAST_EDCA_TO_8822B))
+#define BIT_GET_VO_FAST_EDCA_TO_8822B(x)                                       \
+	(((x) >> BIT_SHIFT_VO_FAST_EDCA_TO_8822B) &                            \
+	 BIT_MASK_VO_FAST_EDCA_TO_8822B)
+#define BIT_SET_VO_FAST_EDCA_TO_8822B(x, v)                                    \
+	(BIT_CLEAR_VO_FAST_EDCA_TO_8822B(x) | BIT_VO_FAST_EDCA_TO_8822B(v))
+
+#define BIT_VO_THRESHOLD_SEL_8822B BIT(7)
+
+#define BIT_SHIFT_VO_FAST_EDCA_PKT_TH_8822B 0
+#define BIT_MASK_VO_FAST_EDCA_PKT_TH_8822B 0x7f
+#define BIT_VO_FAST_EDCA_PKT_TH_8822B(x)                                       \
+	(((x) & BIT_MASK_VO_FAST_EDCA_PKT_TH_8822B)                            \
+	 << BIT_SHIFT_VO_FAST_EDCA_PKT_TH_8822B)
+#define BITS_VO_FAST_EDCA_PKT_TH_8822B                                         \
+	(BIT_MASK_VO_FAST_EDCA_PKT_TH_8822B                                    \
+	 << BIT_SHIFT_VO_FAST_EDCA_PKT_TH_8822B)
+#define BIT_CLEAR_VO_FAST_EDCA_PKT_TH_8822B(x)                                 \
+	((x) & (~BITS_VO_FAST_EDCA_PKT_TH_8822B))
+#define BIT_GET_VO_FAST_EDCA_PKT_TH_8822B(x)                                   \
+	(((x) >> BIT_SHIFT_VO_FAST_EDCA_PKT_TH_8822B) &                        \
+	 BIT_MASK_VO_FAST_EDCA_PKT_TH_8822B)
+#define BIT_SET_VO_FAST_EDCA_PKT_TH_8822B(x, v)                                \
+	(BIT_CLEAR_VO_FAST_EDCA_PKT_TH_8822B(x) |                              \
+	 BIT_VO_FAST_EDCA_PKT_TH_8822B(v))
+
+/* 2 REG_FAST_EDCA_BEBK_SETTING_8822B */
+
+#define BIT_SHIFT_BK_FAST_EDCA_TO_8822B 24
+#define BIT_MASK_BK_FAST_EDCA_TO_8822B 0xff
+#define BIT_BK_FAST_EDCA_TO_8822B(x)                                           \
+	(((x) & BIT_MASK_BK_FAST_EDCA_TO_8822B)                                \
+	 << BIT_SHIFT_BK_FAST_EDCA_TO_8822B)
+#define BITS_BK_FAST_EDCA_TO_8822B                                             \
+	(BIT_MASK_BK_FAST_EDCA_TO_8822B << BIT_SHIFT_BK_FAST_EDCA_TO_8822B)
+#define BIT_CLEAR_BK_FAST_EDCA_TO_8822B(x) ((x) & (~BITS_BK_FAST_EDCA_TO_8822B))
+#define BIT_GET_BK_FAST_EDCA_TO_8822B(x)                                       \
+	(((x) >> BIT_SHIFT_BK_FAST_EDCA_TO_8822B) &                            \
+	 BIT_MASK_BK_FAST_EDCA_TO_8822B)
+#define BIT_SET_BK_FAST_EDCA_TO_8822B(x, v)                                    \
+	(BIT_CLEAR_BK_FAST_EDCA_TO_8822B(x) | BIT_BK_FAST_EDCA_TO_8822B(v))
+
+#define BIT_BK_THRESHOLD_SEL_8822B BIT(23)
+
+#define BIT_SHIFT_BK_FAST_EDCA_PKT_TH_8822B 16
+#define BIT_MASK_BK_FAST_EDCA_PKT_TH_8822B 0x7f
+#define BIT_BK_FAST_EDCA_PKT_TH_8822B(x)                                       \
+	(((x) & BIT_MASK_BK_FAST_EDCA_PKT_TH_8822B)                            \
+	 << BIT_SHIFT_BK_FAST_EDCA_PKT_TH_8822B)
+#define BITS_BK_FAST_EDCA_PKT_TH_8822B                                         \
+	(BIT_MASK_BK_FAST_EDCA_PKT_TH_8822B                                    \
+	 << BIT_SHIFT_BK_FAST_EDCA_PKT_TH_8822B)
+#define BIT_CLEAR_BK_FAST_EDCA_PKT_TH_8822B(x)                                 \
+	((x) & (~BITS_BK_FAST_EDCA_PKT_TH_8822B))
+#define BIT_GET_BK_FAST_EDCA_PKT_TH_8822B(x)                                   \
+	(((x) >> BIT_SHIFT_BK_FAST_EDCA_PKT_TH_8822B) &                        \
+	 BIT_MASK_BK_FAST_EDCA_PKT_TH_8822B)
+#define BIT_SET_BK_FAST_EDCA_PKT_TH_8822B(x, v)                                \
+	(BIT_CLEAR_BK_FAST_EDCA_PKT_TH_8822B(x) |                              \
+	 BIT_BK_FAST_EDCA_PKT_TH_8822B(v))
+
+#define BIT_SHIFT_BE_FAST_EDCA_TO_8822B 8
+#define BIT_MASK_BE_FAST_EDCA_TO_8822B 0xff
+#define BIT_BE_FAST_EDCA_TO_8822B(x)                                           \
+	(((x) & BIT_MASK_BE_FAST_EDCA_TO_8822B)                                \
+	 << BIT_SHIFT_BE_FAST_EDCA_TO_8822B)
+#define BITS_BE_FAST_EDCA_TO_8822B                                             \
+	(BIT_MASK_BE_FAST_EDCA_TO_8822B << BIT_SHIFT_BE_FAST_EDCA_TO_8822B)
+#define BIT_CLEAR_BE_FAST_EDCA_TO_8822B(x) ((x) & (~BITS_BE_FAST_EDCA_TO_8822B))
+#define BIT_GET_BE_FAST_EDCA_TO_8822B(x)                                       \
+	(((x) >> BIT_SHIFT_BE_FAST_EDCA_TO_8822B) &                            \
+	 BIT_MASK_BE_FAST_EDCA_TO_8822B)
+#define BIT_SET_BE_FAST_EDCA_TO_8822B(x, v)                                    \
+	(BIT_CLEAR_BE_FAST_EDCA_TO_8822B(x) | BIT_BE_FAST_EDCA_TO_8822B(v))
+
+#define BIT_BE_THRESHOLD_SEL_8822B BIT(7)
+
+#define BIT_SHIFT_BE_FAST_EDCA_PKT_TH_8822B 0
+#define BIT_MASK_BE_FAST_EDCA_PKT_TH_8822B 0x7f
+#define BIT_BE_FAST_EDCA_PKT_TH_8822B(x)                                       \
+	(((x) & BIT_MASK_BE_FAST_EDCA_PKT_TH_8822B)                            \
+	 << BIT_SHIFT_BE_FAST_EDCA_PKT_TH_8822B)
+#define BITS_BE_FAST_EDCA_PKT_TH_8822B                                         \
+	(BIT_MASK_BE_FAST_EDCA_PKT_TH_8822B                                    \
+	 << BIT_SHIFT_BE_FAST_EDCA_PKT_TH_8822B)
+#define BIT_CLEAR_BE_FAST_EDCA_PKT_TH_8822B(x)                                 \
+	((x) & (~BITS_BE_FAST_EDCA_PKT_TH_8822B))
+#define BIT_GET_BE_FAST_EDCA_PKT_TH_8822B(x)                                   \
+	(((x) >> BIT_SHIFT_BE_FAST_EDCA_PKT_TH_8822B) &                        \
+	 BIT_MASK_BE_FAST_EDCA_PKT_TH_8822B)
+#define BIT_SET_BE_FAST_EDCA_PKT_TH_8822B(x, v)                                \
+	(BIT_CLEAR_BE_FAST_EDCA_PKT_TH_8822B(x) |                              \
+	 BIT_BE_FAST_EDCA_PKT_TH_8822B(v))
+
+/* 2 REG_MACID_DROP0_8822B */
+
+#define BIT_SHIFT_MACID31_0_DROP_8822B 0
+#define BIT_MASK_MACID31_0_DROP_8822B 0xffffffffL
+#define BIT_MACID31_0_DROP_8822B(x)                                            \
+	(((x) & BIT_MASK_MACID31_0_DROP_8822B)                                 \
+	 << BIT_SHIFT_MACID31_0_DROP_8822B)
+#define BITS_MACID31_0_DROP_8822B                                              \
+	(BIT_MASK_MACID31_0_DROP_8822B << BIT_SHIFT_MACID31_0_DROP_8822B)
+#define BIT_CLEAR_MACID31_0_DROP_8822B(x) ((x) & (~BITS_MACID31_0_DROP_8822B))
+#define BIT_GET_MACID31_0_DROP_8822B(x)                                        \
+	(((x) >> BIT_SHIFT_MACID31_0_DROP_8822B) &                             \
+	 BIT_MASK_MACID31_0_DROP_8822B)
+#define BIT_SET_MACID31_0_DROP_8822B(x, v)                                     \
+	(BIT_CLEAR_MACID31_0_DROP_8822B(x) | BIT_MACID31_0_DROP_8822B(v))
+
+/* 2 REG_MACID_DROP1_8822B */
+
+#define BIT_SHIFT_MACID63_32_DROP_8822B 0
+#define BIT_MASK_MACID63_32_DROP_8822B 0xffffffffL
+#define BIT_MACID63_32_DROP_8822B(x)                                           \
+	(((x) & BIT_MASK_MACID63_32_DROP_8822B)                                \
+	 << BIT_SHIFT_MACID63_32_DROP_8822B)
+#define BITS_MACID63_32_DROP_8822B                                             \
+	(BIT_MASK_MACID63_32_DROP_8822B << BIT_SHIFT_MACID63_32_DROP_8822B)
+#define BIT_CLEAR_MACID63_32_DROP_8822B(x) ((x) & (~BITS_MACID63_32_DROP_8822B))
+#define BIT_GET_MACID63_32_DROP_8822B(x)                                       \
+	(((x) >> BIT_SHIFT_MACID63_32_DROP_8822B) &                            \
+	 BIT_MASK_MACID63_32_DROP_8822B)
+#define BIT_SET_MACID63_32_DROP_8822B(x, v)                                    \
+	(BIT_CLEAR_MACID63_32_DROP_8822B(x) | BIT_MACID63_32_DROP_8822B(v))
+
+/* 2 REG_MACID_DROP2_8822B */
+
+#define BIT_SHIFT_MACID95_64_DROP_8822B 0
+#define BIT_MASK_MACID95_64_DROP_8822B 0xffffffffL
+#define BIT_MACID95_64_DROP_8822B(x)                                           \
+	(((x) & BIT_MASK_MACID95_64_DROP_8822B)                                \
+	 << BIT_SHIFT_MACID95_64_DROP_8822B)
+#define BITS_MACID95_64_DROP_8822B                                             \
+	(BIT_MASK_MACID95_64_DROP_8822B << BIT_SHIFT_MACID95_64_DROP_8822B)
+#define BIT_CLEAR_MACID95_64_DROP_8822B(x) ((x) & (~BITS_MACID95_64_DROP_8822B))
+#define BIT_GET_MACID95_64_DROP_8822B(x)                                       \
+	(((x) >> BIT_SHIFT_MACID95_64_DROP_8822B) &                            \
+	 BIT_MASK_MACID95_64_DROP_8822B)
+#define BIT_SET_MACID95_64_DROP_8822B(x, v)                                    \
+	(BIT_CLEAR_MACID95_64_DROP_8822B(x) | BIT_MACID95_64_DROP_8822B(v))
+
+/* 2 REG_MACID_DROP3_8822B */
+
+#define BIT_SHIFT_MACID127_96_DROP_8822B 0
+#define BIT_MASK_MACID127_96_DROP_8822B 0xffffffffL
+#define BIT_MACID127_96_DROP_8822B(x)                                          \
+	(((x) & BIT_MASK_MACID127_96_DROP_8822B)                               \
+	 << BIT_SHIFT_MACID127_96_DROP_8822B)
+#define BITS_MACID127_96_DROP_8822B                                            \
+	(BIT_MASK_MACID127_96_DROP_8822B << BIT_SHIFT_MACID127_96_DROP_8822B)
+#define BIT_CLEAR_MACID127_96_DROP_8822B(x)                                    \
+	((x) & (~BITS_MACID127_96_DROP_8822B))
+#define BIT_GET_MACID127_96_DROP_8822B(x)                                      \
+	(((x) >> BIT_SHIFT_MACID127_96_DROP_8822B) &                           \
+	 BIT_MASK_MACID127_96_DROP_8822B)
+#define BIT_SET_MACID127_96_DROP_8822B(x, v)                                   \
+	(BIT_CLEAR_MACID127_96_DROP_8822B(x) | BIT_MACID127_96_DROP_8822B(v))
+
+/* 2 REG_R_MACID_RELEASE_SUCCESS_0_8822B */
+
+#define BIT_SHIFT_R_MACID_RELEASE_SUCCESS_0_8822B 0
+#define BIT_MASK_R_MACID_RELEASE_SUCCESS_0_8822B 0xffffffffL
+#define BIT_R_MACID_RELEASE_SUCCESS_0_8822B(x)                                 \
+	(((x) & BIT_MASK_R_MACID_RELEASE_SUCCESS_0_8822B)                      \
+	 << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_0_8822B)
+#define BITS_R_MACID_RELEASE_SUCCESS_0_8822B                                   \
+	(BIT_MASK_R_MACID_RELEASE_SUCCESS_0_8822B                              \
+	 << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_0_8822B)
+#define BIT_CLEAR_R_MACID_RELEASE_SUCCESS_0_8822B(x)                           \
+	((x) & (~BITS_R_MACID_RELEASE_SUCCESS_0_8822B))
+#define BIT_GET_R_MACID_RELEASE_SUCCESS_0_8822B(x)                             \
+	(((x) >> BIT_SHIFT_R_MACID_RELEASE_SUCCESS_0_8822B) &                  \
+	 BIT_MASK_R_MACID_RELEASE_SUCCESS_0_8822B)
+#define BIT_SET_R_MACID_RELEASE_SUCCESS_0_8822B(x, v)                          \
+	(BIT_CLEAR_R_MACID_RELEASE_SUCCESS_0_8822B(x) |                        \
+	 BIT_R_MACID_RELEASE_SUCCESS_0_8822B(v))
+
+/* 2 REG_R_MACID_RELEASE_SUCCESS_1_8822B */
+
+#define BIT_SHIFT_R_MACID_RELEASE_SUCCESS_1_8822B 0
+#define BIT_MASK_R_MACID_RELEASE_SUCCESS_1_8822B 0xffffffffL
+#define BIT_R_MACID_RELEASE_SUCCESS_1_8822B(x)                                 \
+	(((x) & BIT_MASK_R_MACID_RELEASE_SUCCESS_1_8822B)                      \
+	 << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_1_8822B)
+#define BITS_R_MACID_RELEASE_SUCCESS_1_8822B                                   \
+	(BIT_MASK_R_MACID_RELEASE_SUCCESS_1_8822B                              \
+	 << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_1_8822B)
+#define BIT_CLEAR_R_MACID_RELEASE_SUCCESS_1_8822B(x)                           \
+	((x) & (~BITS_R_MACID_RELEASE_SUCCESS_1_8822B))
+#define BIT_GET_R_MACID_RELEASE_SUCCESS_1_8822B(x)                             \
+	(((x) >> BIT_SHIFT_R_MACID_RELEASE_SUCCESS_1_8822B) &                  \
+	 BIT_MASK_R_MACID_RELEASE_SUCCESS_1_8822B)
+#define BIT_SET_R_MACID_RELEASE_SUCCESS_1_8822B(x, v)                          \
+	(BIT_CLEAR_R_MACID_RELEASE_SUCCESS_1_8822B(x) |                        \
+	 BIT_R_MACID_RELEASE_SUCCESS_1_8822B(v))
+
+/* 2 REG_R_MACID_RELEASE_SUCCESS_2_8822B */
+
+#define BIT_SHIFT_R_MACID_RELEASE_SUCCESS_2_8822B 0
+#define BIT_MASK_R_MACID_RELEASE_SUCCESS_2_8822B 0xffffffffL
+#define BIT_R_MACID_RELEASE_SUCCESS_2_8822B(x)                                 \
+	(((x) & BIT_MASK_R_MACID_RELEASE_SUCCESS_2_8822B)                      \
+	 << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_2_8822B)
+#define BITS_R_MACID_RELEASE_SUCCESS_2_8822B                                   \
+	(BIT_MASK_R_MACID_RELEASE_SUCCESS_2_8822B                              \
+	 << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_2_8822B)
+#define BIT_CLEAR_R_MACID_RELEASE_SUCCESS_2_8822B(x)                           \
+	((x) & (~BITS_R_MACID_RELEASE_SUCCESS_2_8822B))
+#define BIT_GET_R_MACID_RELEASE_SUCCESS_2_8822B(x)                             \
+	(((x) >> BIT_SHIFT_R_MACID_RELEASE_SUCCESS_2_8822B) &                  \
+	 BIT_MASK_R_MACID_RELEASE_SUCCESS_2_8822B)
+#define BIT_SET_R_MACID_RELEASE_SUCCESS_2_8822B(x, v)                          \
+	(BIT_CLEAR_R_MACID_RELEASE_SUCCESS_2_8822B(x) |                        \
+	 BIT_R_MACID_RELEASE_SUCCESS_2_8822B(v))
+
+/* 2 REG_R_MACID_RELEASE_SUCCESS_3_8822B */
+
+#define BIT_SHIFT_R_MACID_RELEASE_SUCCESS_3_8822B 0
+#define BIT_MASK_R_MACID_RELEASE_SUCCESS_3_8822B 0xffffffffL
+#define BIT_R_MACID_RELEASE_SUCCESS_3_8822B(x)                                 \
+	(((x) & BIT_MASK_R_MACID_RELEASE_SUCCESS_3_8822B)                      \
+	 << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_3_8822B)
+#define BITS_R_MACID_RELEASE_SUCCESS_3_8822B                                   \
+	(BIT_MASK_R_MACID_RELEASE_SUCCESS_3_8822B                              \
+	 << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_3_8822B)
+#define BIT_CLEAR_R_MACID_RELEASE_SUCCESS_3_8822B(x)                           \
+	((x) & (~BITS_R_MACID_RELEASE_SUCCESS_3_8822B))
+#define BIT_GET_R_MACID_RELEASE_SUCCESS_3_8822B(x)                             \
+	(((x) >> BIT_SHIFT_R_MACID_RELEASE_SUCCESS_3_8822B) &                  \
+	 BIT_MASK_R_MACID_RELEASE_SUCCESS_3_8822B)
+#define BIT_SET_R_MACID_RELEASE_SUCCESS_3_8822B(x, v)                          \
+	(BIT_CLEAR_R_MACID_RELEASE_SUCCESS_3_8822B(x) |                        \
+	 BIT_R_MACID_RELEASE_SUCCESS_3_8822B(v))
+
+/* 2 REG_MGG_FIFO_CRTL_8822B */
+#define BIT_R_MGG_FIFO_EN_8822B BIT(31)
+
+#define BIT_SHIFT_R_MGG_FIFO_PG_SIZE_8822B 28
+#define BIT_MASK_R_MGG_FIFO_PG_SIZE_8822B 0x7
+#define BIT_R_MGG_FIFO_PG_SIZE_8822B(x)                                        \
+	(((x) & BIT_MASK_R_MGG_FIFO_PG_SIZE_8822B)                             \
+	 << BIT_SHIFT_R_MGG_FIFO_PG_SIZE_8822B)
+#define BITS_R_MGG_FIFO_PG_SIZE_8822B                                          \
+	(BIT_MASK_R_MGG_FIFO_PG_SIZE_8822B                                     \
+	 << BIT_SHIFT_R_MGG_FIFO_PG_SIZE_8822B)
+#define BIT_CLEAR_R_MGG_FIFO_PG_SIZE_8822B(x)                                  \
+	((x) & (~BITS_R_MGG_FIFO_PG_SIZE_8822B))
+#define BIT_GET_R_MGG_FIFO_PG_SIZE_8822B(x)                                    \
+	(((x) >> BIT_SHIFT_R_MGG_FIFO_PG_SIZE_8822B) &                         \
+	 BIT_MASK_R_MGG_FIFO_PG_SIZE_8822B)
+#define BIT_SET_R_MGG_FIFO_PG_SIZE_8822B(x, v)                                 \
+	(BIT_CLEAR_R_MGG_FIFO_PG_SIZE_8822B(x) |                               \
+	 BIT_R_MGG_FIFO_PG_SIZE_8822B(v))
+
+#define BIT_SHIFT_R_MGG_FIFO_START_PG_8822B 16
+#define BIT_MASK_R_MGG_FIFO_START_PG_8822B 0xfff
+#define BIT_R_MGG_FIFO_START_PG_8822B(x)                                       \
+	(((x) & BIT_MASK_R_MGG_FIFO_START_PG_8822B)                            \
+	 << BIT_SHIFT_R_MGG_FIFO_START_PG_8822B)
+#define BITS_R_MGG_FIFO_START_PG_8822B                                         \
+	(BIT_MASK_R_MGG_FIFO_START_PG_8822B                                    \
+	 << BIT_SHIFT_R_MGG_FIFO_START_PG_8822B)
+#define BIT_CLEAR_R_MGG_FIFO_START_PG_8822B(x)                                 \
+	((x) & (~BITS_R_MGG_FIFO_START_PG_8822B))
+#define BIT_GET_R_MGG_FIFO_START_PG_8822B(x)                                   \
+	(((x) >> BIT_SHIFT_R_MGG_FIFO_START_PG_8822B) &                        \
+	 BIT_MASK_R_MGG_FIFO_START_PG_8822B)
+#define BIT_SET_R_MGG_FIFO_START_PG_8822B(x, v)                                \
+	(BIT_CLEAR_R_MGG_FIFO_START_PG_8822B(x) |                              \
+	 BIT_R_MGG_FIFO_START_PG_8822B(v))
+
+#define BIT_SHIFT_R_MGG_FIFO_SIZE_8822B 14
+#define BIT_MASK_R_MGG_FIFO_SIZE_8822B 0x3
+#define BIT_R_MGG_FIFO_SIZE_8822B(x)                                           \
+	(((x) & BIT_MASK_R_MGG_FIFO_SIZE_8822B)                                \
+	 << BIT_SHIFT_R_MGG_FIFO_SIZE_8822B)
+#define BITS_R_MGG_FIFO_SIZE_8822B                                             \
+	(BIT_MASK_R_MGG_FIFO_SIZE_8822B << BIT_SHIFT_R_MGG_FIFO_SIZE_8822B)
+#define BIT_CLEAR_R_MGG_FIFO_SIZE_8822B(x) ((x) & (~BITS_R_MGG_FIFO_SIZE_8822B))
+#define BIT_GET_R_MGG_FIFO_SIZE_8822B(x)                                       \
+	(((x) >> BIT_SHIFT_R_MGG_FIFO_SIZE_8822B) &                            \
+	 BIT_MASK_R_MGG_FIFO_SIZE_8822B)
+#define BIT_SET_R_MGG_FIFO_SIZE_8822B(x, v)                                    \
+	(BIT_CLEAR_R_MGG_FIFO_SIZE_8822B(x) | BIT_R_MGG_FIFO_SIZE_8822B(v))
+
+#define BIT_R_MGG_FIFO_PAUSE_8822B BIT(13)
+
+#define BIT_SHIFT_R_MGG_FIFO_RPTR_8822B 8
+#define BIT_MASK_R_MGG_FIFO_RPTR_8822B 0x1f
+#define BIT_R_MGG_FIFO_RPTR_8822B(x)                                           \
+	(((x) & BIT_MASK_R_MGG_FIFO_RPTR_8822B)                                \
+	 << BIT_SHIFT_R_MGG_FIFO_RPTR_8822B)
+#define BITS_R_MGG_FIFO_RPTR_8822B                                             \
+	(BIT_MASK_R_MGG_FIFO_RPTR_8822B << BIT_SHIFT_R_MGG_FIFO_RPTR_8822B)
+#define BIT_CLEAR_R_MGG_FIFO_RPTR_8822B(x) ((x) & (~BITS_R_MGG_FIFO_RPTR_8822B))
+#define BIT_GET_R_MGG_FIFO_RPTR_8822B(x)                                       \
+	(((x) >> BIT_SHIFT_R_MGG_FIFO_RPTR_8822B) &                            \
+	 BIT_MASK_R_MGG_FIFO_RPTR_8822B)
+#define BIT_SET_R_MGG_FIFO_RPTR_8822B(x, v)                                    \
+	(BIT_CLEAR_R_MGG_FIFO_RPTR_8822B(x) | BIT_R_MGG_FIFO_RPTR_8822B(v))
+
+#define BIT_R_MGG_FIFO_OV_8822B BIT(7)
+#define BIT_R_MGG_FIFO_WPTR_ERROR_8822B BIT(6)
+#define BIT_R_EN_CPU_LIFETIME_8822B BIT(5)
+
+#define BIT_SHIFT_R_MGG_FIFO_WPTR_8822B 0
+#define BIT_MASK_R_MGG_FIFO_WPTR_8822B 0x1f
+#define BIT_R_MGG_FIFO_WPTR_8822B(x)                                           \
+	(((x) & BIT_MASK_R_MGG_FIFO_WPTR_8822B)                                \
+	 << BIT_SHIFT_R_MGG_FIFO_WPTR_8822B)
+#define BITS_R_MGG_FIFO_WPTR_8822B                                             \
+	(BIT_MASK_R_MGG_FIFO_WPTR_8822B << BIT_SHIFT_R_MGG_FIFO_WPTR_8822B)
+#define BIT_CLEAR_R_MGG_FIFO_WPTR_8822B(x) ((x) & (~BITS_R_MGG_FIFO_WPTR_8822B))
+#define BIT_GET_R_MGG_FIFO_WPTR_8822B(x)                                       \
+	(((x) >> BIT_SHIFT_R_MGG_FIFO_WPTR_8822B) &                            \
+	 BIT_MASK_R_MGG_FIFO_WPTR_8822B)
+#define BIT_SET_R_MGG_FIFO_WPTR_8822B(x, v)                                    \
+	(BIT_CLEAR_R_MGG_FIFO_WPTR_8822B(x) | BIT_R_MGG_FIFO_WPTR_8822B(v))
+
+/* 2 REG_MGG_FIFO_INT_8822B */
+
+#define BIT_SHIFT_R_MGG_FIFO_INT_FLAG_8822B 16
+#define BIT_MASK_R_MGG_FIFO_INT_FLAG_8822B 0xffff
+#define BIT_R_MGG_FIFO_INT_FLAG_8822B(x)                                       \
+	(((x) & BIT_MASK_R_MGG_FIFO_INT_FLAG_8822B)                            \
+	 << BIT_SHIFT_R_MGG_FIFO_INT_FLAG_8822B)
+#define BITS_R_MGG_FIFO_INT_FLAG_8822B                                         \
+	(BIT_MASK_R_MGG_FIFO_INT_FLAG_8822B                                    \
+	 << BIT_SHIFT_R_MGG_FIFO_INT_FLAG_8822B)
+#define BIT_CLEAR_R_MGG_FIFO_INT_FLAG_8822B(x)                                 \
+	((x) & (~BITS_R_MGG_FIFO_INT_FLAG_8822B))
+#define BIT_GET_R_MGG_FIFO_INT_FLAG_8822B(x)                                   \
+	(((x) >> BIT_SHIFT_R_MGG_FIFO_INT_FLAG_8822B) &                        \
+	 BIT_MASK_R_MGG_FIFO_INT_FLAG_8822B)
+#define BIT_SET_R_MGG_FIFO_INT_FLAG_8822B(x, v)                                \
+	(BIT_CLEAR_R_MGG_FIFO_INT_FLAG_8822B(x) |                              \
+	 BIT_R_MGG_FIFO_INT_FLAG_8822B(v))
+
+#define BIT_SHIFT_R_MGG_FIFO_INT_MASK_8822B 0
+#define BIT_MASK_R_MGG_FIFO_INT_MASK_8822B 0xffff
+#define BIT_R_MGG_FIFO_INT_MASK_8822B(x)                                       \
+	(((x) & BIT_MASK_R_MGG_FIFO_INT_MASK_8822B)                            \
+	 << BIT_SHIFT_R_MGG_FIFO_INT_MASK_8822B)
+#define BITS_R_MGG_FIFO_INT_MASK_8822B                                         \
+	(BIT_MASK_R_MGG_FIFO_INT_MASK_8822B                                    \
+	 << BIT_SHIFT_R_MGG_FIFO_INT_MASK_8822B)
+#define BIT_CLEAR_R_MGG_FIFO_INT_MASK_8822B(x)                                 \
+	((x) & (~BITS_R_MGG_FIFO_INT_MASK_8822B))
+#define BIT_GET_R_MGG_FIFO_INT_MASK_8822B(x)                                   \
+	(((x) >> BIT_SHIFT_R_MGG_FIFO_INT_MASK_8822B) &                        \
+	 BIT_MASK_R_MGG_FIFO_INT_MASK_8822B)
+#define BIT_SET_R_MGG_FIFO_INT_MASK_8822B(x, v)                                \
+	(BIT_CLEAR_R_MGG_FIFO_INT_MASK_8822B(x) |                              \
+	 BIT_R_MGG_FIFO_INT_MASK_8822B(v))
+
+/* 2 REG_MGG_FIFO_LIFETIME_8822B */
+
+#define BIT_SHIFT_R_MGG_FIFO_LIFETIME_8822B 16
+#define BIT_MASK_R_MGG_FIFO_LIFETIME_8822B 0xffff
+#define BIT_R_MGG_FIFO_LIFETIME_8822B(x)                                       \
+	(((x) & BIT_MASK_R_MGG_FIFO_LIFETIME_8822B)                            \
+	 << BIT_SHIFT_R_MGG_FIFO_LIFETIME_8822B)
+#define BITS_R_MGG_FIFO_LIFETIME_8822B                                         \
+	(BIT_MASK_R_MGG_FIFO_LIFETIME_8822B                                    \
+	 << BIT_SHIFT_R_MGG_FIFO_LIFETIME_8822B)
+#define BIT_CLEAR_R_MGG_FIFO_LIFETIME_8822B(x)                                 \
+	((x) & (~BITS_R_MGG_FIFO_LIFETIME_8822B))
+#define BIT_GET_R_MGG_FIFO_LIFETIME_8822B(x)                                   \
+	(((x) >> BIT_SHIFT_R_MGG_FIFO_LIFETIME_8822B) &                        \
+	 BIT_MASK_R_MGG_FIFO_LIFETIME_8822B)
+#define BIT_SET_R_MGG_FIFO_LIFETIME_8822B(x, v)                                \
+	(BIT_CLEAR_R_MGG_FIFO_LIFETIME_8822B(x) |                              \
+	 BIT_R_MGG_FIFO_LIFETIME_8822B(v))
+
+#define BIT_SHIFT_R_MGG_FIFO_VALID_MAP_8822B 0
+#define BIT_MASK_R_MGG_FIFO_VALID_MAP_8822B 0xffff
+#define BIT_R_MGG_FIFO_VALID_MAP_8822B(x)                                      \
+	(((x) & BIT_MASK_R_MGG_FIFO_VALID_MAP_8822B)                           \
+	 << BIT_SHIFT_R_MGG_FIFO_VALID_MAP_8822B)
+#define BITS_R_MGG_FIFO_VALID_MAP_8822B                                        \
+	(BIT_MASK_R_MGG_FIFO_VALID_MAP_8822B                                   \
+	 << BIT_SHIFT_R_MGG_FIFO_VALID_MAP_8822B)
+#define BIT_CLEAR_R_MGG_FIFO_VALID_MAP_8822B(x)                                \
+	((x) & (~BITS_R_MGG_FIFO_VALID_MAP_8822B))
+#define BIT_GET_R_MGG_FIFO_VALID_MAP_8822B(x)                                  \
+	(((x) >> BIT_SHIFT_R_MGG_FIFO_VALID_MAP_8822B) &                       \
+	 BIT_MASK_R_MGG_FIFO_VALID_MAP_8822B)
+#define BIT_SET_R_MGG_FIFO_VALID_MAP_8822B(x, v)                               \
+	(BIT_CLEAR_R_MGG_FIFO_VALID_MAP_8822B(x) |                             \
+	 BIT_R_MGG_FIFO_VALID_MAP_8822B(v))
+
+/* 2 REG_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8822B */
+
+#define BIT_SHIFT_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8822B 0
+#define BIT_MASK_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8822B 0x7f
+#define BIT_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8822B(x)                      \
+	(((x) & BIT_MASK_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8822B)           \
+	 << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8822B)
+#define BITS_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8822B                        \
+	(BIT_MASK_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8822B                   \
+	 << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8822B)
+#define BIT_CLEAR_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8822B(x)                \
+	((x) & (~BITS_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8822B))
+#define BIT_GET_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8822B(x)                  \
+	(((x) >> BIT_SHIFT_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8822B) &       \
+	 BIT_MASK_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8822B)
+#define BIT_SET_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8822B(x, v)               \
+	(BIT_CLEAR_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8822B(x) |             \
+	 BIT_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8822B(v))
+
+/* 2 REG_SHCUT_SETTING_8822B */
+
+/* 2 REG_NOT_VALID_8822B */
+
+/* 2 REG_NOT_VALID_8822B */
+
+/* 2 REG_NOT_VALID_8822B */
+
+/* 2 REG_NOT_VALID_8822B */
+
+/* 2 REG_NOT_VALID_8822B */
+
+/* 2 REG_NOT_VALID_8822B */
+
+/* 2 REG_SHCUT_LLC_ETH_TYPE0_8822B */
+
+/* 2 REG_NOT_VALID_8822B */
+
+/* 2 REG_NOT_VALID_8822B */
+
+/* 2 REG_SHCUT_LLC_ETH_TYPE1_8822B */
+
+/* 2 REG_NOT_VALID_8822B */
+
+/* 2 REG_NOT_VALID_8822B */
+
+/* 2 REG_SHCUT_LLC_OUI0_8822B */
+
+/* 2 REG_NOT_VALID_8822B */
+
+/* 2 REG_NOT_VALID_8822B */
+
+/* 2 REG_NOT_VALID_8822B */
+
+/* 2 REG_SHCUT_LLC_OUI1_8822B */
+
+/* 2 REG_NOT_VALID_8822B */
+
+/* 2 REG_NOT_VALID_8822B */
+
+/* 2 REG_NOT_VALID_8822B */
+
+/* 2 REG_SHCUT_LLC_OUI2_8822B */
+
+/* 2 REG_NOT_VALID_8822B */
+
+/* 2 REG_NOT_VALID_8822B */
+
+/* 2 REG_NOT_VALID_8822B */
+
+/* 2 REG_SHCUT_LLC_OUI3_8822B */
+
+/* 2 REG_NOT_VALID_8822B */
+
+/* 2 REG_NOT_VALID_8822B */
+
+/* 2 REG_NOT_VALID_8822B */
+
+/* 2 REG_MU_TX_CTL_8822B */
+#define BIT_R_EN_REVERS_GTAB_8822B BIT(6)
+
+#define BIT_SHIFT_R_MU_TABLE_VALID_8822B 0
+#define BIT_MASK_R_MU_TABLE_VALID_8822B 0x3f
+#define BIT_R_MU_TABLE_VALID_8822B(x)                                          \
+	(((x) & BIT_MASK_R_MU_TABLE_VALID_8822B)                               \
+	 << BIT_SHIFT_R_MU_TABLE_VALID_8822B)
+#define BITS_R_MU_TABLE_VALID_8822B                                            \
+	(BIT_MASK_R_MU_TABLE_VALID_8822B << BIT_SHIFT_R_MU_TABLE_VALID_8822B)
+#define BIT_CLEAR_R_MU_TABLE_VALID_8822B(x)                                    \
+	((x) & (~BITS_R_MU_TABLE_VALID_8822B))
+#define BIT_GET_R_MU_TABLE_VALID_8822B(x)                                      \
+	(((x) >> BIT_SHIFT_R_MU_TABLE_VALID_8822B) &                           \
+	 BIT_MASK_R_MU_TABLE_VALID_8822B)
+#define BIT_SET_R_MU_TABLE_VALID_8822B(x, v)                                   \
+	(BIT_CLEAR_R_MU_TABLE_VALID_8822B(x) | BIT_R_MU_TABLE_VALID_8822B(v))
+
+/* 2 REG_MU_STA_GID_VLD_8822B */
+
+/* 2 REG_NOT_VALID_8822B */
+
+#define BIT_SHIFT_R_MU_STA_GTAB_VALID_8822B 0
+#define BIT_MASK_R_MU_STA_GTAB_VALID_8822B 0xffffffffL
+#define BIT_R_MU_STA_GTAB_VALID_8822B(x)                                       \
+	(((x) & BIT_MASK_R_MU_STA_GTAB_VALID_8822B)                            \
+	 << BIT_SHIFT_R_MU_STA_GTAB_VALID_8822B)
+#define BITS_R_MU_STA_GTAB_VALID_8822B                                         \
+	(BIT_MASK_R_MU_STA_GTAB_VALID_8822B                                    \
+	 << BIT_SHIFT_R_MU_STA_GTAB_VALID_8822B)
+#define BIT_CLEAR_R_MU_STA_GTAB_VALID_8822B(x)                                 \
+	((x) & (~BITS_R_MU_STA_GTAB_VALID_8822B))
+#define BIT_GET_R_MU_STA_GTAB_VALID_8822B(x)                                   \
+	(((x) >> BIT_SHIFT_R_MU_STA_GTAB_VALID_8822B) &                        \
+	 BIT_MASK_R_MU_STA_GTAB_VALID_8822B)
+#define BIT_SET_R_MU_STA_GTAB_VALID_8822B(x, v)                                \
+	(BIT_CLEAR_R_MU_STA_GTAB_VALID_8822B(x) |                              \
+	 BIT_R_MU_STA_GTAB_VALID_8822B(v))
+
+#define BIT_SHIFT_R_MU_STA_GTAB_VALID_8822B 0
+#define BIT_MASK_R_MU_STA_GTAB_VALID_8822B 0xffffffffL
+#define BIT_R_MU_STA_GTAB_VALID_8822B(x)                                       \
+	(((x) & BIT_MASK_R_MU_STA_GTAB_VALID_8822B)                            \
+	 << BIT_SHIFT_R_MU_STA_GTAB_VALID_8822B)
+#define BITS_R_MU_STA_GTAB_VALID_8822B                                         \
+	(BIT_MASK_R_MU_STA_GTAB_VALID_8822B                                    \
+	 << BIT_SHIFT_R_MU_STA_GTAB_VALID_8822B)
+#define BIT_CLEAR_R_MU_STA_GTAB_VALID_8822B(x)                                 \
+	((x) & (~BITS_R_MU_STA_GTAB_VALID_8822B))
+#define BIT_GET_R_MU_STA_GTAB_VALID_8822B(x)                                   \
+	(((x) >> BIT_SHIFT_R_MU_STA_GTAB_VALID_8822B) &                        \
+	 BIT_MASK_R_MU_STA_GTAB_VALID_8822B)
+#define BIT_SET_R_MU_STA_GTAB_VALID_8822B(x, v)                                \
+	(BIT_CLEAR_R_MU_STA_GTAB_VALID_8822B(x) |                              \
+	 BIT_R_MU_STA_GTAB_VALID_8822B(v))
+
+/* 2 REG_MU_STA_USER_POS_INFO_8822B */
+
+/* 2 REG_NOT_VALID_8822B */
+
+#define BIT_SHIFT_R_MU_STA_GTAB_POSITION_8822B 0
+#define BIT_MASK_R_MU_STA_GTAB_POSITION_8822B 0xffffffffffffffffL
+#define BIT_R_MU_STA_GTAB_POSITION_8822B(x)                                    \
+	(((x) & BIT_MASK_R_MU_STA_GTAB_POSITION_8822B)                         \
+	 << BIT_SHIFT_R_MU_STA_GTAB_POSITION_8822B)
+#define BITS_R_MU_STA_GTAB_POSITION_8822B                                      \
+	(BIT_MASK_R_MU_STA_GTAB_POSITION_8822B                                 \
+	 << BIT_SHIFT_R_MU_STA_GTAB_POSITION_8822B)
+#define BIT_CLEAR_R_MU_STA_GTAB_POSITION_8822B(x)                              \
+	((x) & (~BITS_R_MU_STA_GTAB_POSITION_8822B))
+#define BIT_GET_R_MU_STA_GTAB_POSITION_8822B(x)                                \
+	(((x) >> BIT_SHIFT_R_MU_STA_GTAB_POSITION_8822B) &                     \
+	 BIT_MASK_R_MU_STA_GTAB_POSITION_8822B)
+#define BIT_SET_R_MU_STA_GTAB_POSITION_8822B(x, v)                             \
+	(BIT_CLEAR_R_MU_STA_GTAB_POSITION_8822B(x) |                           \
+	 BIT_R_MU_STA_GTAB_POSITION_8822B(v))
+
+#define BIT_SHIFT_R_MU_STA_GTAB_POSITION_8822B 0
+#define BIT_MASK_R_MU_STA_GTAB_POSITION_8822B 0xffffffffffffffffL
+#define BIT_R_MU_STA_GTAB_POSITION_8822B(x)                                    \
+	(((x) & BIT_MASK_R_MU_STA_GTAB_POSITION_8822B)                         \
+	 << BIT_SHIFT_R_MU_STA_GTAB_POSITION_8822B)
+#define BITS_R_MU_STA_GTAB_POSITION_8822B                                      \
+	(BIT_MASK_R_MU_STA_GTAB_POSITION_8822B                                 \
+	 << BIT_SHIFT_R_MU_STA_GTAB_POSITION_8822B)
+#define BIT_CLEAR_R_MU_STA_GTAB_POSITION_8822B(x)                              \
+	((x) & (~BITS_R_MU_STA_GTAB_POSITION_8822B))
+#define BIT_GET_R_MU_STA_GTAB_POSITION_8822B(x)                                \
+	(((x) >> BIT_SHIFT_R_MU_STA_GTAB_POSITION_8822B) &                     \
+	 BIT_MASK_R_MU_STA_GTAB_POSITION_8822B)
+#define BIT_SET_R_MU_STA_GTAB_POSITION_8822B(x, v)                             \
+	(BIT_CLEAR_R_MU_STA_GTAB_POSITION_8822B(x) |                           \
+	 BIT_R_MU_STA_GTAB_POSITION_8822B(v))
+
+/* 2 REG_MU_TRX_DBG_CNT_8822B */
+#define BIT_MU_DNGCNT_RST_8822B BIT(20)
+
+#define BIT_SHIFT_MU_DBGCNT_SEL_8822B 16
+#define BIT_MASK_MU_DBGCNT_SEL_8822B 0xf
+#define BIT_MU_DBGCNT_SEL_8822B(x)                                             \
+	(((x) & BIT_MASK_MU_DBGCNT_SEL_8822B) << BIT_SHIFT_MU_DBGCNT_SEL_8822B)
+#define BITS_MU_DBGCNT_SEL_8822B                                               \
+	(BIT_MASK_MU_DBGCNT_SEL_8822B << BIT_SHIFT_MU_DBGCNT_SEL_8822B)
+#define BIT_CLEAR_MU_DBGCNT_SEL_8822B(x) ((x) & (~BITS_MU_DBGCNT_SEL_8822B))
+#define BIT_GET_MU_DBGCNT_SEL_8822B(x)                                         \
+	(((x) >> BIT_SHIFT_MU_DBGCNT_SEL_8822B) & BIT_MASK_MU_DBGCNT_SEL_8822B)
+#define BIT_SET_MU_DBGCNT_SEL_8822B(x, v)                                      \
+	(BIT_CLEAR_MU_DBGCNT_SEL_8822B(x) | BIT_MU_DBGCNT_SEL_8822B(v))
+
+#define BIT_SHIFT_MU_DNGCNT_8822B 0
+#define BIT_MASK_MU_DNGCNT_8822B 0xffff
+#define BIT_MU_DNGCNT_8822B(x)                                                 \
+	(((x) & BIT_MASK_MU_DNGCNT_8822B) << BIT_SHIFT_MU_DNGCNT_8822B)
+#define BITS_MU_DNGCNT_8822B                                                   \
+	(BIT_MASK_MU_DNGCNT_8822B << BIT_SHIFT_MU_DNGCNT_8822B)
+#define BIT_CLEAR_MU_DNGCNT_8822B(x) ((x) & (~BITS_MU_DNGCNT_8822B))
+#define BIT_GET_MU_DNGCNT_8822B(x)                                             \
+	(((x) >> BIT_SHIFT_MU_DNGCNT_8822B) & BIT_MASK_MU_DNGCNT_8822B)
+#define BIT_SET_MU_DNGCNT_8822B(x, v)                                          \
+	(BIT_CLEAR_MU_DNGCNT_8822B(x) | BIT_MU_DNGCNT_8822B(v))
+
+/* 2 REG_MU_TX_CTL_8822B */
+#define BIT_R_EN_REVERS_GTAB_8822B BIT(6)
+
+#define BIT_SHIFT_R_MU_TABLE_VALID_8822B 0
+#define BIT_MASK_R_MU_TABLE_VALID_8822B 0x3f
+#define BIT_R_MU_TABLE_VALID_8822B(x)                                          \
+	(((x) & BIT_MASK_R_MU_TABLE_VALID_8822B)                               \
+	 << BIT_SHIFT_R_MU_TABLE_VALID_8822B)
+#define BITS_R_MU_TABLE_VALID_8822B                                            \
+	(BIT_MASK_R_MU_TABLE_VALID_8822B << BIT_SHIFT_R_MU_TABLE_VALID_8822B)
+#define BIT_CLEAR_R_MU_TABLE_VALID_8822B(x)                                    \
+	((x) & (~BITS_R_MU_TABLE_VALID_8822B))
+#define BIT_GET_R_MU_TABLE_VALID_8822B(x)                                      \
+	(((x) >> BIT_SHIFT_R_MU_TABLE_VALID_8822B) &                           \
+	 BIT_MASK_R_MU_TABLE_VALID_8822B)
+#define BIT_SET_R_MU_TABLE_VALID_8822B(x, v)                                   \
+	(BIT_CLEAR_R_MU_TABLE_VALID_8822B(x) | BIT_R_MU_TABLE_VALID_8822B(v))
+
+/* 2 REG_MU_STA_GID_VLD_8822B */
+
+/* 2 REG_NOT_VALID_8822B */
+
+#define BIT_SHIFT_R_MU_STA_GTAB_VALID_8822B 0
+#define BIT_MASK_R_MU_STA_GTAB_VALID_8822B 0xffffffffL
+#define BIT_R_MU_STA_GTAB_VALID_8822B(x)                                       \
+	(((x) & BIT_MASK_R_MU_STA_GTAB_VALID_8822B)                            \
+	 << BIT_SHIFT_R_MU_STA_GTAB_VALID_8822B)
+#define BITS_R_MU_STA_GTAB_VALID_8822B                                         \
+	(BIT_MASK_R_MU_STA_GTAB_VALID_8822B                                    \
+	 << BIT_SHIFT_R_MU_STA_GTAB_VALID_8822B)
+#define BIT_CLEAR_R_MU_STA_GTAB_VALID_8822B(x)                                 \
+	((x) & (~BITS_R_MU_STA_GTAB_VALID_8822B))
+#define BIT_GET_R_MU_STA_GTAB_VALID_8822B(x)                                   \
+	(((x) >> BIT_SHIFT_R_MU_STA_GTAB_VALID_8822B) &                        \
+	 BIT_MASK_R_MU_STA_GTAB_VALID_8822B)
+#define BIT_SET_R_MU_STA_GTAB_VALID_8822B(x, v)                                \
+	(BIT_CLEAR_R_MU_STA_GTAB_VALID_8822B(x) |                              \
+	 BIT_R_MU_STA_GTAB_VALID_8822B(v))
+
+#define BIT_SHIFT_R_MU_STA_GTAB_VALID_8822B 0
+#define BIT_MASK_R_MU_STA_GTAB_VALID_8822B 0xffffffffL
+#define BIT_R_MU_STA_GTAB_VALID_8822B(x)                                       \
+	(((x) & BIT_MASK_R_MU_STA_GTAB_VALID_8822B)                            \
+	 << BIT_SHIFT_R_MU_STA_GTAB_VALID_8822B)
+#define BITS_R_MU_STA_GTAB_VALID_8822B                                         \
+	(BIT_MASK_R_MU_STA_GTAB_VALID_8822B                                    \
+	 << BIT_SHIFT_R_MU_STA_GTAB_VALID_8822B)
+#define BIT_CLEAR_R_MU_STA_GTAB_VALID_8822B(x)                                 \
+	((x) & (~BITS_R_MU_STA_GTAB_VALID_8822B))
+#define BIT_GET_R_MU_STA_GTAB_VALID_8822B(x)                                   \
+	(((x) >> BIT_SHIFT_R_MU_STA_GTAB_VALID_8822B) &                        \
+	 BIT_MASK_R_MU_STA_GTAB_VALID_8822B)
+#define BIT_SET_R_MU_STA_GTAB_VALID_8822B(x, v)                                \
+	(BIT_CLEAR_R_MU_STA_GTAB_VALID_8822B(x) |                              \
+	 BIT_R_MU_STA_GTAB_VALID_8822B(v))
+
+/* 2 REG_MU_STA_USER_POS_INFO_8822B */
+
+/* 2 REG_NOT_VALID_8822B */
+
+#define BIT_SHIFT_R_MU_STA_GTAB_POSITION_8822B 0
+#define BIT_MASK_R_MU_STA_GTAB_POSITION_8822B 0xffffffffffffffffL
+#define BIT_R_MU_STA_GTAB_POSITION_8822B(x)                                    \
+	(((x) & BIT_MASK_R_MU_STA_GTAB_POSITION_8822B)                         \
+	 << BIT_SHIFT_R_MU_STA_GTAB_POSITION_8822B)
+#define BITS_R_MU_STA_GTAB_POSITION_8822B                                      \
+	(BIT_MASK_R_MU_STA_GTAB_POSITION_8822B                                 \
+	 << BIT_SHIFT_R_MU_STA_GTAB_POSITION_8822B)
+#define BIT_CLEAR_R_MU_STA_GTAB_POSITION_8822B(x)                              \
+	((x) & (~BITS_R_MU_STA_GTAB_POSITION_8822B))
+#define BIT_GET_R_MU_STA_GTAB_POSITION_8822B(x)                                \
+	(((x) >> BIT_SHIFT_R_MU_STA_GTAB_POSITION_8822B) &                     \
+	 BIT_MASK_R_MU_STA_GTAB_POSITION_8822B)
+#define BIT_SET_R_MU_STA_GTAB_POSITION_8822B(x, v)                             \
+	(BIT_CLEAR_R_MU_STA_GTAB_POSITION_8822B(x) |                           \
+	 BIT_R_MU_STA_GTAB_POSITION_8822B(v))
+
+#define BIT_SHIFT_R_MU_STA_GTAB_POSITION_8822B 0
+#define BIT_MASK_R_MU_STA_GTAB_POSITION_8822B 0xffffffffffffffffL
+#define BIT_R_MU_STA_GTAB_POSITION_8822B(x)                                    \
+	(((x) & BIT_MASK_R_MU_STA_GTAB_POSITION_8822B)                         \
+	 << BIT_SHIFT_R_MU_STA_GTAB_POSITION_8822B)
+#define BITS_R_MU_STA_GTAB_POSITION_8822B                                      \
+	(BIT_MASK_R_MU_STA_GTAB_POSITION_8822B                                 \
+	 << BIT_SHIFT_R_MU_STA_GTAB_POSITION_8822B)
+#define BIT_CLEAR_R_MU_STA_GTAB_POSITION_8822B(x)                              \
+	((x) & (~BITS_R_MU_STA_GTAB_POSITION_8822B))
+#define BIT_GET_R_MU_STA_GTAB_POSITION_8822B(x)                                \
+	(((x) >> BIT_SHIFT_R_MU_STA_GTAB_POSITION_8822B) &                     \
+	 BIT_MASK_R_MU_STA_GTAB_POSITION_8822B)
+#define BIT_SET_R_MU_STA_GTAB_POSITION_8822B(x, v)                             \
+	(BIT_CLEAR_R_MU_STA_GTAB_POSITION_8822B(x) |                           \
+	 BIT_R_MU_STA_GTAB_POSITION_8822B(v))
+
+/* 2 REG_MU_TRX_DBG_CNT_8822B */
+#define BIT_MU_DNGCNT_RST_8822B BIT(20)
+
+#define BIT_SHIFT_MU_DBGCNT_SEL_8822B 16
+#define BIT_MASK_MU_DBGCNT_SEL_8822B 0xf
+#define BIT_MU_DBGCNT_SEL_8822B(x)                                             \
+	(((x) & BIT_MASK_MU_DBGCNT_SEL_8822B) << BIT_SHIFT_MU_DBGCNT_SEL_8822B)
+#define BITS_MU_DBGCNT_SEL_8822B                                               \
+	(BIT_MASK_MU_DBGCNT_SEL_8822B << BIT_SHIFT_MU_DBGCNT_SEL_8822B)
+#define BIT_CLEAR_MU_DBGCNT_SEL_8822B(x) ((x) & (~BITS_MU_DBGCNT_SEL_8822B))
+#define BIT_GET_MU_DBGCNT_SEL_8822B(x)                                         \
+	(((x) >> BIT_SHIFT_MU_DBGCNT_SEL_8822B) & BIT_MASK_MU_DBGCNT_SEL_8822B)
+#define BIT_SET_MU_DBGCNT_SEL_8822B(x, v)                                      \
+	(BIT_CLEAR_MU_DBGCNT_SEL_8822B(x) | BIT_MU_DBGCNT_SEL_8822B(v))
+
+#define BIT_SHIFT_MU_DNGCNT_8822B 0
+#define BIT_MASK_MU_DNGCNT_8822B 0xffff
+#define BIT_MU_DNGCNT_8822B(x)                                                 \
+	(((x) & BIT_MASK_MU_DNGCNT_8822B) << BIT_SHIFT_MU_DNGCNT_8822B)
+#define BITS_MU_DNGCNT_8822B                                                   \
+	(BIT_MASK_MU_DNGCNT_8822B << BIT_SHIFT_MU_DNGCNT_8822B)
+#define BIT_CLEAR_MU_DNGCNT_8822B(x) ((x) & (~BITS_MU_DNGCNT_8822B))
+#define BIT_GET_MU_DNGCNT_8822B(x)                                             \
+	(((x) >> BIT_SHIFT_MU_DNGCNT_8822B) & BIT_MASK_MU_DNGCNT_8822B)
+#define BIT_SET_MU_DNGCNT_8822B(x, v)                                          \
+	(BIT_CLEAR_MU_DNGCNT_8822B(x) | BIT_MU_DNGCNT_8822B(v))
+
+/* 2 REG_NOT_VALID_8822B */
+
+/* 2 REG_EDCA_VO_PARAM_8822B */
+
+#define BIT_SHIFT_TXOPLIMIT_8822B 16
+#define BIT_MASK_TXOPLIMIT_8822B 0x7ff
+#define BIT_TXOPLIMIT_8822B(x)                                                 \
+	(((x) & BIT_MASK_TXOPLIMIT_8822B) << BIT_SHIFT_TXOPLIMIT_8822B)
+#define BITS_TXOPLIMIT_8822B                                                   \
+	(BIT_MASK_TXOPLIMIT_8822B << BIT_SHIFT_TXOPLIMIT_8822B)
+#define BIT_CLEAR_TXOPLIMIT_8822B(x) ((x) & (~BITS_TXOPLIMIT_8822B))
+#define BIT_GET_TXOPLIMIT_8822B(x)                                             \
+	(((x) >> BIT_SHIFT_TXOPLIMIT_8822B) & BIT_MASK_TXOPLIMIT_8822B)
+#define BIT_SET_TXOPLIMIT_8822B(x, v)                                          \
+	(BIT_CLEAR_TXOPLIMIT_8822B(x) | BIT_TXOPLIMIT_8822B(v))
+
+#define BIT_SHIFT_CW_8822B 8
+#define BIT_MASK_CW_8822B 0xff
+#define BIT_CW_8822B(x) (((x) & BIT_MASK_CW_8822B) << BIT_SHIFT_CW_8822B)
+#define BITS_CW_8822B (BIT_MASK_CW_8822B << BIT_SHIFT_CW_8822B)
+#define BIT_CLEAR_CW_8822B(x) ((x) & (~BITS_CW_8822B))
+#define BIT_GET_CW_8822B(x) (((x) >> BIT_SHIFT_CW_8822B) & BIT_MASK_CW_8822B)
+#define BIT_SET_CW_8822B(x, v) (BIT_CLEAR_CW_8822B(x) | BIT_CW_8822B(v))
+
+#define BIT_SHIFT_AIFS_8822B 0
+#define BIT_MASK_AIFS_8822B 0xff
+#define BIT_AIFS_8822B(x) (((x) & BIT_MASK_AIFS_8822B) << BIT_SHIFT_AIFS_8822B)
+#define BITS_AIFS_8822B (BIT_MASK_AIFS_8822B << BIT_SHIFT_AIFS_8822B)
+#define BIT_CLEAR_AIFS_8822B(x) ((x) & (~BITS_AIFS_8822B))
+#define BIT_GET_AIFS_8822B(x)                                                  \
+	(((x) >> BIT_SHIFT_AIFS_8822B) & BIT_MASK_AIFS_8822B)
+#define BIT_SET_AIFS_8822B(x, v) (BIT_CLEAR_AIFS_8822B(x) | BIT_AIFS_8822B(v))
+
+/* 2 REG_EDCA_VI_PARAM_8822B */
+
+/* 2 REG_NOT_VALID_8822B */
+
+#define BIT_SHIFT_TXOPLIMIT_8822B 16
+#define BIT_MASK_TXOPLIMIT_8822B 0x7ff
+#define BIT_TXOPLIMIT_8822B(x)                                                 \
+	(((x) & BIT_MASK_TXOPLIMIT_8822B) << BIT_SHIFT_TXOPLIMIT_8822B)
+#define BITS_TXOPLIMIT_8822B                                                   \
+	(BIT_MASK_TXOPLIMIT_8822B << BIT_SHIFT_TXOPLIMIT_8822B)
+#define BIT_CLEAR_TXOPLIMIT_8822B(x) ((x) & (~BITS_TXOPLIMIT_8822B))
+#define BIT_GET_TXOPLIMIT_8822B(x)                                             \
+	(((x) >> BIT_SHIFT_TXOPLIMIT_8822B) & BIT_MASK_TXOPLIMIT_8822B)
+#define BIT_SET_TXOPLIMIT_8822B(x, v)                                          \
+	(BIT_CLEAR_TXOPLIMIT_8822B(x) | BIT_TXOPLIMIT_8822B(v))
+
+#define BIT_SHIFT_CW_8822B 8
+#define BIT_MASK_CW_8822B 0xff
+#define BIT_CW_8822B(x) (((x) & BIT_MASK_CW_8822B) << BIT_SHIFT_CW_8822B)
+#define BITS_CW_8822B (BIT_MASK_CW_8822B << BIT_SHIFT_CW_8822B)
+#define BIT_CLEAR_CW_8822B(x) ((x) & (~BITS_CW_8822B))
+#define BIT_GET_CW_8822B(x) (((x) >> BIT_SHIFT_CW_8822B) & BIT_MASK_CW_8822B)
+#define BIT_SET_CW_8822B(x, v) (BIT_CLEAR_CW_8822B(x) | BIT_CW_8822B(v))
+
+#define BIT_SHIFT_AIFS_8822B 0
+#define BIT_MASK_AIFS_8822B 0xff
+#define BIT_AIFS_8822B(x) (((x) & BIT_MASK_AIFS_8822B) << BIT_SHIFT_AIFS_8822B)
+#define BITS_AIFS_8822B (BIT_MASK_AIFS_8822B << BIT_SHIFT_AIFS_8822B)
+#define BIT_CLEAR_AIFS_8822B(x) ((x) & (~BITS_AIFS_8822B))
+#define BIT_GET_AIFS_8822B(x)                                                  \
+	(((x) >> BIT_SHIFT_AIFS_8822B) & BIT_MASK_AIFS_8822B)
+#define BIT_SET_AIFS_8822B(x, v) (BIT_CLEAR_AIFS_8822B(x) | BIT_AIFS_8822B(v))
+
+/* 2 REG_EDCA_BE_PARAM_8822B */
+
+/* 2 REG_NOT_VALID_8822B */
+
+#define BIT_SHIFT_TXOPLIMIT_8822B 16
+#define BIT_MASK_TXOPLIMIT_8822B 0x7ff
+#define BIT_TXOPLIMIT_8822B(x)                                                 \
+	(((x) & BIT_MASK_TXOPLIMIT_8822B) << BIT_SHIFT_TXOPLIMIT_8822B)
+#define BITS_TXOPLIMIT_8822B                                                   \
+	(BIT_MASK_TXOPLIMIT_8822B << BIT_SHIFT_TXOPLIMIT_8822B)
+#define BIT_CLEAR_TXOPLIMIT_8822B(x) ((x) & (~BITS_TXOPLIMIT_8822B))
+#define BIT_GET_TXOPLIMIT_8822B(x)                                             \
+	(((x) >> BIT_SHIFT_TXOPLIMIT_8822B) & BIT_MASK_TXOPLIMIT_8822B)
+#define BIT_SET_TXOPLIMIT_8822B(x, v)                                          \
+	(BIT_CLEAR_TXOPLIMIT_8822B(x) | BIT_TXOPLIMIT_8822B(v))
+
+#define BIT_SHIFT_CW_8822B 8
+#define BIT_MASK_CW_8822B 0xff
+#define BIT_CW_8822B(x) (((x) & BIT_MASK_CW_8822B) << BIT_SHIFT_CW_8822B)
+#define BITS_CW_8822B (BIT_MASK_CW_8822B << BIT_SHIFT_CW_8822B)
+#define BIT_CLEAR_CW_8822B(x) ((x) & (~BITS_CW_8822B))
+#define BIT_GET_CW_8822B(x) (((x) >> BIT_SHIFT_CW_8822B) & BIT_MASK_CW_8822B)
+#define BIT_SET_CW_8822B(x, v) (BIT_CLEAR_CW_8822B(x) | BIT_CW_8822B(v))
+
+#define BIT_SHIFT_AIFS_8822B 0
+#define BIT_MASK_AIFS_8822B 0xff
+#define BIT_AIFS_8822B(x) (((x) & BIT_MASK_AIFS_8822B) << BIT_SHIFT_AIFS_8822B)
+#define BITS_AIFS_8822B (BIT_MASK_AIFS_8822B << BIT_SHIFT_AIFS_8822B)
+#define BIT_CLEAR_AIFS_8822B(x) ((x) & (~BITS_AIFS_8822B))
+#define BIT_GET_AIFS_8822B(x)                                                  \
+	(((x) >> BIT_SHIFT_AIFS_8822B) & BIT_MASK_AIFS_8822B)
+#define BIT_SET_AIFS_8822B(x, v) (BIT_CLEAR_AIFS_8822B(x) | BIT_AIFS_8822B(v))
+
+/* 2 REG_EDCA_BK_PARAM_8822B */
+
+/* 2 REG_NOT_VALID_8822B */
+
+#define BIT_SHIFT_TXOPLIMIT_8822B 16
+#define BIT_MASK_TXOPLIMIT_8822B 0x7ff
+#define BIT_TXOPLIMIT_8822B(x)                                                 \
+	(((x) & BIT_MASK_TXOPLIMIT_8822B) << BIT_SHIFT_TXOPLIMIT_8822B)
+#define BITS_TXOPLIMIT_8822B                                                   \
+	(BIT_MASK_TXOPLIMIT_8822B << BIT_SHIFT_TXOPLIMIT_8822B)
+#define BIT_CLEAR_TXOPLIMIT_8822B(x) ((x) & (~BITS_TXOPLIMIT_8822B))
+#define BIT_GET_TXOPLIMIT_8822B(x)                                             \
+	(((x) >> BIT_SHIFT_TXOPLIMIT_8822B) & BIT_MASK_TXOPLIMIT_8822B)
+#define BIT_SET_TXOPLIMIT_8822B(x, v)                                          \
+	(BIT_CLEAR_TXOPLIMIT_8822B(x) | BIT_TXOPLIMIT_8822B(v))
+
+#define BIT_SHIFT_CW_8822B 8
+#define BIT_MASK_CW_8822B 0xff
+#define BIT_CW_8822B(x) (((x) & BIT_MASK_CW_8822B) << BIT_SHIFT_CW_8822B)
+#define BITS_CW_8822B (BIT_MASK_CW_8822B << BIT_SHIFT_CW_8822B)
+#define BIT_CLEAR_CW_8822B(x) ((x) & (~BITS_CW_8822B))
+#define BIT_GET_CW_8822B(x) (((x) >> BIT_SHIFT_CW_8822B) & BIT_MASK_CW_8822B)
+#define BIT_SET_CW_8822B(x, v) (BIT_CLEAR_CW_8822B(x) | BIT_CW_8822B(v))
+
+#define BIT_SHIFT_AIFS_8822B 0
+#define BIT_MASK_AIFS_8822B 0xff
+#define BIT_AIFS_8822B(x) (((x) & BIT_MASK_AIFS_8822B) << BIT_SHIFT_AIFS_8822B)
+#define BITS_AIFS_8822B (BIT_MASK_AIFS_8822B << BIT_SHIFT_AIFS_8822B)
+#define BIT_CLEAR_AIFS_8822B(x) ((x) & (~BITS_AIFS_8822B))
+#define BIT_GET_AIFS_8822B(x)                                                  \
+	(((x) >> BIT_SHIFT_AIFS_8822B) & BIT_MASK_AIFS_8822B)
+#define BIT_SET_AIFS_8822B(x, v) (BIT_CLEAR_AIFS_8822B(x) | BIT_AIFS_8822B(v))
+
+/* 2 REG_BCNTCFG_8822B */
+
+#define BIT_SHIFT_BCNCW_MAX_8822B 12
+#define BIT_MASK_BCNCW_MAX_8822B 0xf
+#define BIT_BCNCW_MAX_8822B(x)                                                 \
+	(((x) & BIT_MASK_BCNCW_MAX_8822B) << BIT_SHIFT_BCNCW_MAX_8822B)
+#define BITS_BCNCW_MAX_8822B                                                   \
+	(BIT_MASK_BCNCW_MAX_8822B << BIT_SHIFT_BCNCW_MAX_8822B)
+#define BIT_CLEAR_BCNCW_MAX_8822B(x) ((x) & (~BITS_BCNCW_MAX_8822B))
+#define BIT_GET_BCNCW_MAX_8822B(x)                                             \
+	(((x) >> BIT_SHIFT_BCNCW_MAX_8822B) & BIT_MASK_BCNCW_MAX_8822B)
+#define BIT_SET_BCNCW_MAX_8822B(x, v)                                          \
+	(BIT_CLEAR_BCNCW_MAX_8822B(x) | BIT_BCNCW_MAX_8822B(v))
+
+#define BIT_SHIFT_BCNCW_MIN_8822B 8
+#define BIT_MASK_BCNCW_MIN_8822B 0xf
+#define BIT_BCNCW_MIN_8822B(x)                                                 \
+	(((x) & BIT_MASK_BCNCW_MIN_8822B) << BIT_SHIFT_BCNCW_MIN_8822B)
+#define BITS_BCNCW_MIN_8822B                                                   \
+	(BIT_MASK_BCNCW_MIN_8822B << BIT_SHIFT_BCNCW_MIN_8822B)
+#define BIT_CLEAR_BCNCW_MIN_8822B(x) ((x) & (~BITS_BCNCW_MIN_8822B))
+#define BIT_GET_BCNCW_MIN_8822B(x)                                             \
+	(((x) >> BIT_SHIFT_BCNCW_MIN_8822B) & BIT_MASK_BCNCW_MIN_8822B)
+#define BIT_SET_BCNCW_MIN_8822B(x, v)                                          \
+	(BIT_CLEAR_BCNCW_MIN_8822B(x) | BIT_BCNCW_MIN_8822B(v))
+
+#define BIT_SHIFT_BCNIFS_8822B 0
+#define BIT_MASK_BCNIFS_8822B 0xff
+#define BIT_BCNIFS_8822B(x)                                                    \
+	(((x) & BIT_MASK_BCNIFS_8822B) << BIT_SHIFT_BCNIFS_8822B)
+#define BITS_BCNIFS_8822B (BIT_MASK_BCNIFS_8822B << BIT_SHIFT_BCNIFS_8822B)
+#define BIT_CLEAR_BCNIFS_8822B(x) ((x) & (~BITS_BCNIFS_8822B))
+#define BIT_GET_BCNIFS_8822B(x)                                                \
+	(((x) >> BIT_SHIFT_BCNIFS_8822B) & BIT_MASK_BCNIFS_8822B)
+#define BIT_SET_BCNIFS_8822B(x, v)                                             \
+	(BIT_CLEAR_BCNIFS_8822B(x) | BIT_BCNIFS_8822B(v))
+
+/* 2 REG_PIFS_8822B */
+
+#define BIT_SHIFT_PIFS_8822B 0
+#define BIT_MASK_PIFS_8822B 0xff
+#define BIT_PIFS_8822B(x) (((x) & BIT_MASK_PIFS_8822B) << BIT_SHIFT_PIFS_8822B)
+#define BITS_PIFS_8822B (BIT_MASK_PIFS_8822B << BIT_SHIFT_PIFS_8822B)
+#define BIT_CLEAR_PIFS_8822B(x) ((x) & (~BITS_PIFS_8822B))
+#define BIT_GET_PIFS_8822B(x)                                                  \
+	(((x) >> BIT_SHIFT_PIFS_8822B) & BIT_MASK_PIFS_8822B)
+#define BIT_SET_PIFS_8822B(x, v) (BIT_CLEAR_PIFS_8822B(x) | BIT_PIFS_8822B(v))
+
+/* 2 REG_RDG_PIFS_8822B */
+
+#define BIT_SHIFT_RDG_PIFS_8822B 0
+#define BIT_MASK_RDG_PIFS_8822B 0xff
+#define BIT_RDG_PIFS_8822B(x)                                                  \
+	(((x) & BIT_MASK_RDG_PIFS_8822B) << BIT_SHIFT_RDG_PIFS_8822B)
+#define BITS_RDG_PIFS_8822B                                                    \
+	(BIT_MASK_RDG_PIFS_8822B << BIT_SHIFT_RDG_PIFS_8822B)
+#define BIT_CLEAR_RDG_PIFS_8822B(x) ((x) & (~BITS_RDG_PIFS_8822B))
+#define BIT_GET_RDG_PIFS_8822B(x)                                              \
+	(((x) >> BIT_SHIFT_RDG_PIFS_8822B) & BIT_MASK_RDG_PIFS_8822B)
+#define BIT_SET_RDG_PIFS_8822B(x, v)                                           \
+	(BIT_CLEAR_RDG_PIFS_8822B(x) | BIT_RDG_PIFS_8822B(v))
+
+/* 2 REG_SIFS_8822B */
+
+#define BIT_SHIFT_SIFS_OFDM_TRX_8822B 24
+#define BIT_MASK_SIFS_OFDM_TRX_8822B 0xff
+#define BIT_SIFS_OFDM_TRX_8822B(x)                                             \
+	(((x) & BIT_MASK_SIFS_OFDM_TRX_8822B) << BIT_SHIFT_SIFS_OFDM_TRX_8822B)
+#define BITS_SIFS_OFDM_TRX_8822B                                               \
+	(BIT_MASK_SIFS_OFDM_TRX_8822B << BIT_SHIFT_SIFS_OFDM_TRX_8822B)
+#define BIT_CLEAR_SIFS_OFDM_TRX_8822B(x) ((x) & (~BITS_SIFS_OFDM_TRX_8822B))
+#define BIT_GET_SIFS_OFDM_TRX_8822B(x)                                         \
+	(((x) >> BIT_SHIFT_SIFS_OFDM_TRX_8822B) & BIT_MASK_SIFS_OFDM_TRX_8822B)
+#define BIT_SET_SIFS_OFDM_TRX_8822B(x, v)                                      \
+	(BIT_CLEAR_SIFS_OFDM_TRX_8822B(x) | BIT_SIFS_OFDM_TRX_8822B(v))
+
+#define BIT_SHIFT_SIFS_CCK_TRX_8822B 16
+#define BIT_MASK_SIFS_CCK_TRX_8822B 0xff
+#define BIT_SIFS_CCK_TRX_8822B(x)                                              \
+	(((x) & BIT_MASK_SIFS_CCK_TRX_8822B) << BIT_SHIFT_SIFS_CCK_TRX_8822B)
+#define BITS_SIFS_CCK_TRX_8822B                                                \
+	(BIT_MASK_SIFS_CCK_TRX_8822B << BIT_SHIFT_SIFS_CCK_TRX_8822B)
+#define BIT_CLEAR_SIFS_CCK_TRX_8822B(x) ((x) & (~BITS_SIFS_CCK_TRX_8822B))
+#define BIT_GET_SIFS_CCK_TRX_8822B(x)                                          \
+	(((x) >> BIT_SHIFT_SIFS_CCK_TRX_8822B) & BIT_MASK_SIFS_CCK_TRX_8822B)
+#define BIT_SET_SIFS_CCK_TRX_8822B(x, v)                                       \
+	(BIT_CLEAR_SIFS_CCK_TRX_8822B(x) | BIT_SIFS_CCK_TRX_8822B(v))
+
+#define BIT_SHIFT_SIFS_OFDM_CTX_8822B 8
+#define BIT_MASK_SIFS_OFDM_CTX_8822B 0xff
+#define BIT_SIFS_OFDM_CTX_8822B(x)                                             \
+	(((x) & BIT_MASK_SIFS_OFDM_CTX_8822B) << BIT_SHIFT_SIFS_OFDM_CTX_8822B)
+#define BITS_SIFS_OFDM_CTX_8822B                                               \
+	(BIT_MASK_SIFS_OFDM_CTX_8822B << BIT_SHIFT_SIFS_OFDM_CTX_8822B)
+#define BIT_CLEAR_SIFS_OFDM_CTX_8822B(x) ((x) & (~BITS_SIFS_OFDM_CTX_8822B))
+#define BIT_GET_SIFS_OFDM_CTX_8822B(x)                                         \
+	(((x) >> BIT_SHIFT_SIFS_OFDM_CTX_8822B) & BIT_MASK_SIFS_OFDM_CTX_8822B)
+#define BIT_SET_SIFS_OFDM_CTX_8822B(x, v)                                      \
+	(BIT_CLEAR_SIFS_OFDM_CTX_8822B(x) | BIT_SIFS_OFDM_CTX_8822B(v))
+
+#define BIT_SHIFT_SIFS_CCK_CTX_8822B 0
+#define BIT_MASK_SIFS_CCK_CTX_8822B 0xff
+#define BIT_SIFS_CCK_CTX_8822B(x)                                              \
+	(((x) & BIT_MASK_SIFS_CCK_CTX_8822B) << BIT_SHIFT_SIFS_CCK_CTX_8822B)
+#define BITS_SIFS_CCK_CTX_8822B                                                \
+	(BIT_MASK_SIFS_CCK_CTX_8822B << BIT_SHIFT_SIFS_CCK_CTX_8822B)
+#define BIT_CLEAR_SIFS_CCK_CTX_8822B(x) ((x) & (~BITS_SIFS_CCK_CTX_8822B))
+#define BIT_GET_SIFS_CCK_CTX_8822B(x)                                          \
+	(((x) >> BIT_SHIFT_SIFS_CCK_CTX_8822B) & BIT_MASK_SIFS_CCK_CTX_8822B)
+#define BIT_SET_SIFS_CCK_CTX_8822B(x, v)                                       \
+	(BIT_CLEAR_SIFS_CCK_CTX_8822B(x) | BIT_SIFS_CCK_CTX_8822B(v))
+
+/* 2 REG_TSFTR_SYN_OFFSET_8822B */
+
+#define BIT_SHIFT_TSFTR_SNC_OFFSET_8822B 0
+#define BIT_MASK_TSFTR_SNC_OFFSET_8822B 0xffff
+#define BIT_TSFTR_SNC_OFFSET_8822B(x)                                          \
+	(((x) & BIT_MASK_TSFTR_SNC_OFFSET_8822B)                               \
+	 << BIT_SHIFT_TSFTR_SNC_OFFSET_8822B)
+#define BITS_TSFTR_SNC_OFFSET_8822B                                            \
+	(BIT_MASK_TSFTR_SNC_OFFSET_8822B << BIT_SHIFT_TSFTR_SNC_OFFSET_8822B)
+#define BIT_CLEAR_TSFTR_SNC_OFFSET_8822B(x)                                    \
+	((x) & (~BITS_TSFTR_SNC_OFFSET_8822B))
+#define BIT_GET_TSFTR_SNC_OFFSET_8822B(x)                                      \
+	(((x) >> BIT_SHIFT_TSFTR_SNC_OFFSET_8822B) &                           \
+	 BIT_MASK_TSFTR_SNC_OFFSET_8822B)
+#define BIT_SET_TSFTR_SNC_OFFSET_8822B(x, v)                                   \
+	(BIT_CLEAR_TSFTR_SNC_OFFSET_8822B(x) | BIT_TSFTR_SNC_OFFSET_8822B(v))
+
+/* 2 REG_AGGR_BREAK_TIME_8822B */
+
+#define BIT_SHIFT_AGGR_BK_TIME_8822B 0
+#define BIT_MASK_AGGR_BK_TIME_8822B 0xff
+#define BIT_AGGR_BK_TIME_8822B(x)                                              \
+	(((x) & BIT_MASK_AGGR_BK_TIME_8822B) << BIT_SHIFT_AGGR_BK_TIME_8822B)
+#define BITS_AGGR_BK_TIME_8822B                                                \
+	(BIT_MASK_AGGR_BK_TIME_8822B << BIT_SHIFT_AGGR_BK_TIME_8822B)
+#define BIT_CLEAR_AGGR_BK_TIME_8822B(x) ((x) & (~BITS_AGGR_BK_TIME_8822B))
+#define BIT_GET_AGGR_BK_TIME_8822B(x)                                          \
+	(((x) >> BIT_SHIFT_AGGR_BK_TIME_8822B) & BIT_MASK_AGGR_BK_TIME_8822B)
+#define BIT_SET_AGGR_BK_TIME_8822B(x, v)                                       \
+	(BIT_CLEAR_AGGR_BK_TIME_8822B(x) | BIT_AGGR_BK_TIME_8822B(v))
+
+/* 2 REG_SLOT_8822B */
+
+#define BIT_SHIFT_SLOT_8822B 0
+#define BIT_MASK_SLOT_8822B 0xff
+#define BIT_SLOT_8822B(x) (((x) & BIT_MASK_SLOT_8822B) << BIT_SHIFT_SLOT_8822B)
+#define BITS_SLOT_8822B (BIT_MASK_SLOT_8822B << BIT_SHIFT_SLOT_8822B)
+#define BIT_CLEAR_SLOT_8822B(x) ((x) & (~BITS_SLOT_8822B))
+#define BIT_GET_SLOT_8822B(x)                                                  \
+	(((x) >> BIT_SHIFT_SLOT_8822B) & BIT_MASK_SLOT_8822B)
+#define BIT_SET_SLOT_8822B(x, v) (BIT_CLEAR_SLOT_8822B(x) | BIT_SLOT_8822B(v))
+
+/* 2 REG_TX_PTCL_CTRL_8822B */
+#define BIT_DIS_EDCCA_8822B BIT(15)
+#define BIT_DIS_CCA_8822B BIT(14)
+#define BIT_LSIG_TXOP_TXCMD_NAV_8822B BIT(13)
+#define BIT_SIFS_BK_EN_8822B BIT(12)
+
+#define BIT_SHIFT_TXQ_NAV_MSK_8822B 8
+#define BIT_MASK_TXQ_NAV_MSK_8822B 0xf
+#define BIT_TXQ_NAV_MSK_8822B(x)                                               \
+	(((x) & BIT_MASK_TXQ_NAV_MSK_8822B) << BIT_SHIFT_TXQ_NAV_MSK_8822B)
+#define BITS_TXQ_NAV_MSK_8822B                                                 \
+	(BIT_MASK_TXQ_NAV_MSK_8822B << BIT_SHIFT_TXQ_NAV_MSK_8822B)
+#define BIT_CLEAR_TXQ_NAV_MSK_8822B(x) ((x) & (~BITS_TXQ_NAV_MSK_8822B))
+#define BIT_GET_TXQ_NAV_MSK_8822B(x)                                           \
+	(((x) >> BIT_SHIFT_TXQ_NAV_MSK_8822B) & BIT_MASK_TXQ_NAV_MSK_8822B)
+#define BIT_SET_TXQ_NAV_MSK_8822B(x, v)                                        \
+	(BIT_CLEAR_TXQ_NAV_MSK_8822B(x) | BIT_TXQ_NAV_MSK_8822B(v))
+
+#define BIT_DIS_CW_8822B BIT(7)
+#define BIT_NAV_END_TXOP_8822B BIT(6)
+#define BIT_RDG_END_TXOP_8822B BIT(5)
+#define BIT_AC_INBCN_HOLD_8822B BIT(4)
+#define BIT_MGTQ_TXOP_EN_8822B BIT(3)
+#define BIT_MGTQ_RTSMF_EN_8822B BIT(2)
+#define BIT_HIQ_RTSMF_EN_8822B BIT(1)
+#define BIT_BCN_RTSMF_EN_8822B BIT(0)
+
+/* 2 REG_TXPAUSE_8822B */
+#define BIT_STOP_BCN_HI_MGT_8822B BIT(7)
+#define BIT_MAC_STOPBCNQ_8822B BIT(6)
+#define BIT_MAC_STOPHIQ_8822B BIT(5)
+#define BIT_MAC_STOPMGQ_8822B BIT(4)
+#define BIT_MAC_STOPBK_8822B BIT(3)
+#define BIT_MAC_STOPBE_8822B BIT(2)
+#define BIT_MAC_STOPVI_8822B BIT(1)
+#define BIT_MAC_STOPVO_8822B BIT(0)
+
+/* 2 REG_DIS_TXREQ_CLR_8822B */
+#define BIT_DIS_BT_CCA_8822B BIT(7)
+#define BIT_DIS_TXREQ_CLR_HI_8822B BIT(5)
+#define BIT_DIS_TXREQ_CLR_MGQ_8822B BIT(4)
+#define BIT_DIS_TXREQ_CLR_VO_8822B BIT(3)
+#define BIT_DIS_TXREQ_CLR_VI_8822B BIT(2)
+#define BIT_DIS_TXREQ_CLR_BE_8822B BIT(1)
+#define BIT_DIS_TXREQ_CLR_BK_8822B BIT(0)
+
+/* 2 REG_RD_CTRL_8822B */
+#define BIT_EN_CLR_TXREQ_INCCA_8822B BIT(15)
+#define BIT_DIS_TX_OVER_BCNQ_8822B BIT(14)
+#define BIT_EN_BCNERR_INCCCA_8822B BIT(13)
+#define BIT_EDCCA_MSK_CNTDOWN_EN_8822B BIT(11)
+#define BIT_DIS_TXOP_CFE_8822B BIT(10)
+#define BIT_DIS_LSIG_CFE_8822B BIT(9)
+#define BIT_DIS_STBC_CFE_8822B BIT(8)
+#define BIT_BKQ_RD_INIT_EN_8822B BIT(7)
+#define BIT_BEQ_RD_INIT_EN_8822B BIT(6)
+#define BIT_VIQ_RD_INIT_EN_8822B BIT(5)
+#define BIT_VOQ_RD_INIT_EN_8822B BIT(4)
+#define BIT_BKQ_RD_RESP_EN_8822B BIT(3)
+#define BIT_BEQ_RD_RESP_EN_8822B BIT(2)
+#define BIT_VIQ_RD_RESP_EN_8822B BIT(1)
+#define BIT_VOQ_RD_RESP_EN_8822B BIT(0)
+
+/* 2 REG_MBSSID_CTRL_8822B */
+#define BIT_MBID_BCNQ7_EN_8822B BIT(7)
+#define BIT_MBID_BCNQ6_EN_8822B BIT(6)
+#define BIT_MBID_BCNQ5_EN_8822B BIT(5)
+#define BIT_MBID_BCNQ4_EN_8822B BIT(4)
+#define BIT_MBID_BCNQ3_EN_8822B BIT(3)
+#define BIT_MBID_BCNQ2_EN_8822B BIT(2)
+#define BIT_MBID_BCNQ1_EN_8822B BIT(1)
+#define BIT_MBID_BCNQ0_EN_8822B BIT(0)
+
+/* 2 REG_P2PPS_CTRL_8822B */
+#define BIT_P2P_CTW_ALLSTASLEEP_8822B BIT(7)
+#define BIT_P2P_OFF_DISTX_EN_8822B BIT(6)
+#define BIT_PWR_MGT_EN_8822B BIT(5)
+#define BIT_P2P_NOA1_EN_8822B BIT(2)
+#define BIT_P2P_NOA0_EN_8822B BIT(1)
+
+/* 2 REG_PKT_LIFETIME_CTRL_8822B */
+#define BIT_EN_P2P_CTWND1_8822B BIT(23)
+#define BIT_EN_BKF_CLR_TXREQ_8822B BIT(22)
+#define BIT_EN_TSFBIT32_RST_P2P_8822B BIT(21)
+#define BIT_EN_BCN_TX_BTCCA_8822B BIT(20)
+#define BIT_DIS_PKT_TX_ATIM_8822B BIT(19)
+#define BIT_DIS_BCN_DIS_CTN_8822B BIT(18)
+#define BIT_EN_NAVEND_RST_TXOP_8822B BIT(17)
+#define BIT_EN_FILTER_CCA_8822B BIT(16)
+
+#define BIT_SHIFT_CCA_FILTER_THRS_8822B 8
+#define BIT_MASK_CCA_FILTER_THRS_8822B 0xff
+#define BIT_CCA_FILTER_THRS_8822B(x)                                           \
+	(((x) & BIT_MASK_CCA_FILTER_THRS_8822B)                                \
+	 << BIT_SHIFT_CCA_FILTER_THRS_8822B)
+#define BITS_CCA_FILTER_THRS_8822B                                             \
+	(BIT_MASK_CCA_FILTER_THRS_8822B << BIT_SHIFT_CCA_FILTER_THRS_8822B)
+#define BIT_CLEAR_CCA_FILTER_THRS_8822B(x) ((x) & (~BITS_CCA_FILTER_THRS_8822B))
+#define BIT_GET_CCA_FILTER_THRS_8822B(x)                                       \
+	(((x) >> BIT_SHIFT_CCA_FILTER_THRS_8822B) &                            \
+	 BIT_MASK_CCA_FILTER_THRS_8822B)
+#define BIT_SET_CCA_FILTER_THRS_8822B(x, v)                                    \
+	(BIT_CLEAR_CCA_FILTER_THRS_8822B(x) | BIT_CCA_FILTER_THRS_8822B(v))
+
+#define BIT_SHIFT_EDCCA_THRS_8822B 0
+#define BIT_MASK_EDCCA_THRS_8822B 0xff
+#define BIT_EDCCA_THRS_8822B(x)                                                \
+	(((x) & BIT_MASK_EDCCA_THRS_8822B) << BIT_SHIFT_EDCCA_THRS_8822B)
+#define BITS_EDCCA_THRS_8822B                                                  \
+	(BIT_MASK_EDCCA_THRS_8822B << BIT_SHIFT_EDCCA_THRS_8822B)
+#define BIT_CLEAR_EDCCA_THRS_8822B(x) ((x) & (~BITS_EDCCA_THRS_8822B))
+#define BIT_GET_EDCCA_THRS_8822B(x)                                            \
+	(((x) >> BIT_SHIFT_EDCCA_THRS_8822B) & BIT_MASK_EDCCA_THRS_8822B)
+#define BIT_SET_EDCCA_THRS_8822B(x, v)                                         \
+	(BIT_CLEAR_EDCCA_THRS_8822B(x) | BIT_EDCCA_THRS_8822B(v))
+
+/* 2 REG_P2PPS_SPEC_STATE_8822B */
+#define BIT_SPEC_POWER_STATE_8822B BIT(7)
+#define BIT_SPEC_CTWINDOW_ON_8822B BIT(6)
+#define BIT_SPEC_BEACON_AREA_ON_8822B BIT(5)
+#define BIT_SPEC_CTWIN_EARLY_DISTX_8822B BIT(4)
+#define BIT_SPEC_NOA1_OFF_PERIOD_8822B BIT(3)
+#define BIT_SPEC_FORCE_DOZE1_8822B BIT(2)
+#define BIT_SPEC_NOA0_OFF_PERIOD_8822B BIT(1)
+#define BIT_SPEC_FORCE_DOZE0_8822B BIT(0)
+
+/* 2 REG_TXOP_LIMIT_CTRL_8822B */
+
+#define BIT_SHIFT_TXOP_TBTT_CNT_8822B 24
+#define BIT_MASK_TXOP_TBTT_CNT_8822B 0xff
+#define BIT_TXOP_TBTT_CNT_8822B(x)                                             \
+	(((x) & BIT_MASK_TXOP_TBTT_CNT_8822B) << BIT_SHIFT_TXOP_TBTT_CNT_8822B)
+#define BITS_TXOP_TBTT_CNT_8822B                                               \
+	(BIT_MASK_TXOP_TBTT_CNT_8822B << BIT_SHIFT_TXOP_TBTT_CNT_8822B)
+#define BIT_CLEAR_TXOP_TBTT_CNT_8822B(x) ((x) & (~BITS_TXOP_TBTT_CNT_8822B))
+#define BIT_GET_TXOP_TBTT_CNT_8822B(x)                                         \
+	(((x) >> BIT_SHIFT_TXOP_TBTT_CNT_8822B) & BIT_MASK_TXOP_TBTT_CNT_8822B)
+#define BIT_SET_TXOP_TBTT_CNT_8822B(x, v)                                      \
+	(BIT_CLEAR_TXOP_TBTT_CNT_8822B(x) | BIT_TXOP_TBTT_CNT_8822B(v))
+
+#define BIT_SHIFT_TXOP_TBTT_CNT_SEL_8822B 20
+#define BIT_MASK_TXOP_TBTT_CNT_SEL_8822B 0xf
+#define BIT_TXOP_TBTT_CNT_SEL_8822B(x)                                         \
+	(((x) & BIT_MASK_TXOP_TBTT_CNT_SEL_8822B)                              \
+	 << BIT_SHIFT_TXOP_TBTT_CNT_SEL_8822B)
+#define BITS_TXOP_TBTT_CNT_SEL_8822B                                           \
+	(BIT_MASK_TXOP_TBTT_CNT_SEL_8822B << BIT_SHIFT_TXOP_TBTT_CNT_SEL_8822B)
+#define BIT_CLEAR_TXOP_TBTT_CNT_SEL_8822B(x)                                   \
+	((x) & (~BITS_TXOP_TBTT_CNT_SEL_8822B))
+#define BIT_GET_TXOP_TBTT_CNT_SEL_8822B(x)                                     \
+	(((x) >> BIT_SHIFT_TXOP_TBTT_CNT_SEL_8822B) &                          \
+	 BIT_MASK_TXOP_TBTT_CNT_SEL_8822B)
+#define BIT_SET_TXOP_TBTT_CNT_SEL_8822B(x, v)                                  \
+	(BIT_CLEAR_TXOP_TBTT_CNT_SEL_8822B(x) | BIT_TXOP_TBTT_CNT_SEL_8822B(v))
+
+#define BIT_SHIFT_TXOP_LMT_EN_8822B 16
+#define BIT_MASK_TXOP_LMT_EN_8822B 0xf
+#define BIT_TXOP_LMT_EN_8822B(x)                                               \
+	(((x) & BIT_MASK_TXOP_LMT_EN_8822B) << BIT_SHIFT_TXOP_LMT_EN_8822B)
+#define BITS_TXOP_LMT_EN_8822B                                                 \
+	(BIT_MASK_TXOP_LMT_EN_8822B << BIT_SHIFT_TXOP_LMT_EN_8822B)
+#define BIT_CLEAR_TXOP_LMT_EN_8822B(x) ((x) & (~BITS_TXOP_LMT_EN_8822B))
+#define BIT_GET_TXOP_LMT_EN_8822B(x)                                           \
+	(((x) >> BIT_SHIFT_TXOP_LMT_EN_8822B) & BIT_MASK_TXOP_LMT_EN_8822B)
+#define BIT_SET_TXOP_LMT_EN_8822B(x, v)                                        \
+	(BIT_CLEAR_TXOP_LMT_EN_8822B(x) | BIT_TXOP_LMT_EN_8822B(v))
+
+#define BIT_SHIFT_TXOP_LMT_TX_TIME_8822B 8
+#define BIT_MASK_TXOP_LMT_TX_TIME_8822B 0xff
+#define BIT_TXOP_LMT_TX_TIME_8822B(x)                                          \
+	(((x) & BIT_MASK_TXOP_LMT_TX_TIME_8822B)                               \
+	 << BIT_SHIFT_TXOP_LMT_TX_TIME_8822B)
+#define BITS_TXOP_LMT_TX_TIME_8822B                                            \
+	(BIT_MASK_TXOP_LMT_TX_TIME_8822B << BIT_SHIFT_TXOP_LMT_TX_TIME_8822B)
+#define BIT_CLEAR_TXOP_LMT_TX_TIME_8822B(x)                                    \
+	((x) & (~BITS_TXOP_LMT_TX_TIME_8822B))
+#define BIT_GET_TXOP_LMT_TX_TIME_8822B(x)                                      \
+	(((x) >> BIT_SHIFT_TXOP_LMT_TX_TIME_8822B) &                           \
+	 BIT_MASK_TXOP_LMT_TX_TIME_8822B)
+#define BIT_SET_TXOP_LMT_TX_TIME_8822B(x, v)                                   \
+	(BIT_CLEAR_TXOP_LMT_TX_TIME_8822B(x) | BIT_TXOP_LMT_TX_TIME_8822B(v))
+
+#define BIT_TXOP_CNT_TRIGGER_RESET_8822B BIT(7)
+
+#define BIT_SHIFT_TXOP_LMT_PKT_NUM_8822B 0
+#define BIT_MASK_TXOP_LMT_PKT_NUM_8822B 0x3f
+#define BIT_TXOP_LMT_PKT_NUM_8822B(x)                                          \
+	(((x) & BIT_MASK_TXOP_LMT_PKT_NUM_8822B)                               \
+	 << BIT_SHIFT_TXOP_LMT_PKT_NUM_8822B)
+#define BITS_TXOP_LMT_PKT_NUM_8822B                                            \
+	(BIT_MASK_TXOP_LMT_PKT_NUM_8822B << BIT_SHIFT_TXOP_LMT_PKT_NUM_8822B)
+#define BIT_CLEAR_TXOP_LMT_PKT_NUM_8822B(x)                                    \
+	((x) & (~BITS_TXOP_LMT_PKT_NUM_8822B))
+#define BIT_GET_TXOP_LMT_PKT_NUM_8822B(x)                                      \
+	(((x) >> BIT_SHIFT_TXOP_LMT_PKT_NUM_8822B) &                           \
+	 BIT_MASK_TXOP_LMT_PKT_NUM_8822B)
+#define BIT_SET_TXOP_LMT_PKT_NUM_8822B(x, v)                                   \
+	(BIT_CLEAR_TXOP_LMT_PKT_NUM_8822B(x) | BIT_TXOP_LMT_PKT_NUM_8822B(v))
+
+/* 2 REG_BAR_TX_CTRL_8822B */
+
+/* 2 REG_P2PON_DIS_TXTIME_8822B */
+
+#define BIT_SHIFT_P2PON_DIS_TXTIME_8822B 0
+#define BIT_MASK_P2PON_DIS_TXTIME_8822B 0xff
+#define BIT_P2PON_DIS_TXTIME_8822B(x)                                          \
+	(((x) & BIT_MASK_P2PON_DIS_TXTIME_8822B)                               \
+	 << BIT_SHIFT_P2PON_DIS_TXTIME_8822B)
+#define BITS_P2PON_DIS_TXTIME_8822B                                            \
+	(BIT_MASK_P2PON_DIS_TXTIME_8822B << BIT_SHIFT_P2PON_DIS_TXTIME_8822B)
+#define BIT_CLEAR_P2PON_DIS_TXTIME_8822B(x)                                    \
+	((x) & (~BITS_P2PON_DIS_TXTIME_8822B))
+#define BIT_GET_P2PON_DIS_TXTIME_8822B(x)                                      \
+	(((x) >> BIT_SHIFT_P2PON_DIS_TXTIME_8822B) &                           \
+	 BIT_MASK_P2PON_DIS_TXTIME_8822B)
+#define BIT_SET_P2PON_DIS_TXTIME_8822B(x, v)                                   \
+	(BIT_CLEAR_P2PON_DIS_TXTIME_8822B(x) | BIT_P2PON_DIS_TXTIME_8822B(v))
+
+/* 2 REG_QUEUE_INCOL_THR_8822B */
+
+#define BIT_SHIFT_BK_QUEUE_THR_8822B 24
+#define BIT_MASK_BK_QUEUE_THR_8822B 0xff
+#define BIT_BK_QUEUE_THR_8822B(x)                                              \
+	(((x) & BIT_MASK_BK_QUEUE_THR_8822B) << BIT_SHIFT_BK_QUEUE_THR_8822B)
+#define BITS_BK_QUEUE_THR_8822B                                                \
+	(BIT_MASK_BK_QUEUE_THR_8822B << BIT_SHIFT_BK_QUEUE_THR_8822B)
+#define BIT_CLEAR_BK_QUEUE_THR_8822B(x) ((x) & (~BITS_BK_QUEUE_THR_8822B))
+#define BIT_GET_BK_QUEUE_THR_8822B(x)                                          \
+	(((x) >> BIT_SHIFT_BK_QUEUE_THR_8822B) & BIT_MASK_BK_QUEUE_THR_8822B)
+#define BIT_SET_BK_QUEUE_THR_8822B(x, v)                                       \
+	(BIT_CLEAR_BK_QUEUE_THR_8822B(x) | BIT_BK_QUEUE_THR_8822B(v))
+
+#define BIT_SHIFT_BE_QUEUE_THR_8822B 16
+#define BIT_MASK_BE_QUEUE_THR_8822B 0xff
+#define BIT_BE_QUEUE_THR_8822B(x)                                              \
+	(((x) & BIT_MASK_BE_QUEUE_THR_8822B) << BIT_SHIFT_BE_QUEUE_THR_8822B)
+#define BITS_BE_QUEUE_THR_8822B                                                \
+	(BIT_MASK_BE_QUEUE_THR_8822B << BIT_SHIFT_BE_QUEUE_THR_8822B)
+#define BIT_CLEAR_BE_QUEUE_THR_8822B(x) ((x) & (~BITS_BE_QUEUE_THR_8822B))
+#define BIT_GET_BE_QUEUE_THR_8822B(x)                                          \
+	(((x) >> BIT_SHIFT_BE_QUEUE_THR_8822B) & BIT_MASK_BE_QUEUE_THR_8822B)
+#define BIT_SET_BE_QUEUE_THR_8822B(x, v)                                       \
+	(BIT_CLEAR_BE_QUEUE_THR_8822B(x) | BIT_BE_QUEUE_THR_8822B(v))
+
+#define BIT_SHIFT_VI_QUEUE_THR_8822B 8
+#define BIT_MASK_VI_QUEUE_THR_8822B 0xff
+#define BIT_VI_QUEUE_THR_8822B(x)                                              \
+	(((x) & BIT_MASK_VI_QUEUE_THR_8822B) << BIT_SHIFT_VI_QUEUE_THR_8822B)
+#define BITS_VI_QUEUE_THR_8822B                                                \
+	(BIT_MASK_VI_QUEUE_THR_8822B << BIT_SHIFT_VI_QUEUE_THR_8822B)
+#define BIT_CLEAR_VI_QUEUE_THR_8822B(x) ((x) & (~BITS_VI_QUEUE_THR_8822B))
+#define BIT_GET_VI_QUEUE_THR_8822B(x)                                          \
+	(((x) >> BIT_SHIFT_VI_QUEUE_THR_8822B) & BIT_MASK_VI_QUEUE_THR_8822B)
+#define BIT_SET_VI_QUEUE_THR_8822B(x, v)                                       \
+	(BIT_CLEAR_VI_QUEUE_THR_8822B(x) | BIT_VI_QUEUE_THR_8822B(v))
+
+#define BIT_SHIFT_VO_QUEUE_THR_8822B 0
+#define BIT_MASK_VO_QUEUE_THR_8822B 0xff
+#define BIT_VO_QUEUE_THR_8822B(x)                                              \
+	(((x) & BIT_MASK_VO_QUEUE_THR_8822B) << BIT_SHIFT_VO_QUEUE_THR_8822B)
+#define BITS_VO_QUEUE_THR_8822B                                                \
+	(BIT_MASK_VO_QUEUE_THR_8822B << BIT_SHIFT_VO_QUEUE_THR_8822B)
+#define BIT_CLEAR_VO_QUEUE_THR_8822B(x) ((x) & (~BITS_VO_QUEUE_THR_8822B))
+#define BIT_GET_VO_QUEUE_THR_8822B(x)                                          \
+	(((x) >> BIT_SHIFT_VO_QUEUE_THR_8822B) & BIT_MASK_VO_QUEUE_THR_8822B)
+#define BIT_SET_VO_QUEUE_THR_8822B(x, v)                                       \
+	(BIT_CLEAR_VO_QUEUE_THR_8822B(x) | BIT_VO_QUEUE_THR_8822B(v))
+
+/* 2 REG_QUEUE_INCOL_EN_8822B */
+#define BIT_QUEUE_INCOL_EN_8822B BIT(16)
+
+#define BIT_SHIFT_BE_TRIGGER_NUM_8822B 12
+#define BIT_MASK_BE_TRIGGER_NUM_8822B 0xf
+#define BIT_BE_TRIGGER_NUM_8822B(x)                                            \
+	(((x) & BIT_MASK_BE_TRIGGER_NUM_8822B)                                 \
+	 << BIT_SHIFT_BE_TRIGGER_NUM_8822B)
+#define BITS_BE_TRIGGER_NUM_8822B                                              \
+	(BIT_MASK_BE_TRIGGER_NUM_8822B << BIT_SHIFT_BE_TRIGGER_NUM_8822B)
+#define BIT_CLEAR_BE_TRIGGER_NUM_8822B(x) ((x) & (~BITS_BE_TRIGGER_NUM_8822B))
+#define BIT_GET_BE_TRIGGER_NUM_8822B(x)                                        \
+	(((x) >> BIT_SHIFT_BE_TRIGGER_NUM_8822B) &                             \
+	 BIT_MASK_BE_TRIGGER_NUM_8822B)
+#define BIT_SET_BE_TRIGGER_NUM_8822B(x, v)                                     \
+	(BIT_CLEAR_BE_TRIGGER_NUM_8822B(x) | BIT_BE_TRIGGER_NUM_8822B(v))
+
+#define BIT_SHIFT_BK_TRIGGER_NUM_8822B 8
+#define BIT_MASK_BK_TRIGGER_NUM_8822B 0xf
+#define BIT_BK_TRIGGER_NUM_8822B(x)                                            \
+	(((x) & BIT_MASK_BK_TRIGGER_NUM_8822B)                                 \
+	 << BIT_SHIFT_BK_TRIGGER_NUM_8822B)
+#define BITS_BK_TRIGGER_NUM_8822B                                              \
+	(BIT_MASK_BK_TRIGGER_NUM_8822B << BIT_SHIFT_BK_TRIGGER_NUM_8822B)
+#define BIT_CLEAR_BK_TRIGGER_NUM_8822B(x) ((x) & (~BITS_BK_TRIGGER_NUM_8822B))
+#define BIT_GET_BK_TRIGGER_NUM_8822B(x)                                        \
+	(((x) >> BIT_SHIFT_BK_TRIGGER_NUM_8822B) &                             \
+	 BIT_MASK_BK_TRIGGER_NUM_8822B)
+#define BIT_SET_BK_TRIGGER_NUM_8822B(x, v)                                     \
+	(BIT_CLEAR_BK_TRIGGER_NUM_8822B(x) | BIT_BK_TRIGGER_NUM_8822B(v))
+
+#define BIT_SHIFT_VI_TRIGGER_NUM_8822B 4
+#define BIT_MASK_VI_TRIGGER_NUM_8822B 0xf
+#define BIT_VI_TRIGGER_NUM_8822B(x)                                            \
+	(((x) & BIT_MASK_VI_TRIGGER_NUM_8822B)                                 \
+	 << BIT_SHIFT_VI_TRIGGER_NUM_8822B)
+#define BITS_VI_TRIGGER_NUM_8822B                                              \
+	(BIT_MASK_VI_TRIGGER_NUM_8822B << BIT_SHIFT_VI_TRIGGER_NUM_8822B)
+#define BIT_CLEAR_VI_TRIGGER_NUM_8822B(x) ((x) & (~BITS_VI_TRIGGER_NUM_8822B))
+#define BIT_GET_VI_TRIGGER_NUM_8822B(x)                                        \
+	(((x) >> BIT_SHIFT_VI_TRIGGER_NUM_8822B) &                             \
+	 BIT_MASK_VI_TRIGGER_NUM_8822B)
+#define BIT_SET_VI_TRIGGER_NUM_8822B(x, v)                                     \
+	(BIT_CLEAR_VI_TRIGGER_NUM_8822B(x) | BIT_VI_TRIGGER_NUM_8822B(v))
+
+#define BIT_SHIFT_VO_TRIGGER_NUM_8822B 0
+#define BIT_MASK_VO_TRIGGER_NUM_8822B 0xf
+#define BIT_VO_TRIGGER_NUM_8822B(x)                                            \
+	(((x) & BIT_MASK_VO_TRIGGER_NUM_8822B)                                 \
+	 << BIT_SHIFT_VO_TRIGGER_NUM_8822B)
+#define BITS_VO_TRIGGER_NUM_8822B                                              \
+	(BIT_MASK_VO_TRIGGER_NUM_8822B << BIT_SHIFT_VO_TRIGGER_NUM_8822B)
+#define BIT_CLEAR_VO_TRIGGER_NUM_8822B(x) ((x) & (~BITS_VO_TRIGGER_NUM_8822B))
+#define BIT_GET_VO_TRIGGER_NUM_8822B(x)                                        \
+	(((x) >> BIT_SHIFT_VO_TRIGGER_NUM_8822B) &                             \
+	 BIT_MASK_VO_TRIGGER_NUM_8822B)
+#define BIT_SET_VO_TRIGGER_NUM_8822B(x, v)                                     \
+	(BIT_CLEAR_VO_TRIGGER_NUM_8822B(x) | BIT_VO_TRIGGER_NUM_8822B(v))
+
+/* 2 REG_TBTT_PROHIBIT_8822B */
+
+#define BIT_SHIFT_TBTT_HOLD_TIME_AP_8822B 8
+#define BIT_MASK_TBTT_HOLD_TIME_AP_8822B 0xfff
+#define BIT_TBTT_HOLD_TIME_AP_8822B(x)                                         \
+	(((x) & BIT_MASK_TBTT_HOLD_TIME_AP_8822B)                              \
+	 << BIT_SHIFT_TBTT_HOLD_TIME_AP_8822B)
+#define BITS_TBTT_HOLD_TIME_AP_8822B                                           \
+	(BIT_MASK_TBTT_HOLD_TIME_AP_8822B << BIT_SHIFT_TBTT_HOLD_TIME_AP_8822B)
+#define BIT_CLEAR_TBTT_HOLD_TIME_AP_8822B(x)                                   \
+	((x) & (~BITS_TBTT_HOLD_TIME_AP_8822B))
+#define BIT_GET_TBTT_HOLD_TIME_AP_8822B(x)                                     \
+	(((x) >> BIT_SHIFT_TBTT_HOLD_TIME_AP_8822B) &                          \
+	 BIT_MASK_TBTT_HOLD_TIME_AP_8822B)
+#define BIT_SET_TBTT_HOLD_TIME_AP_8822B(x, v)                                  \
+	(BIT_CLEAR_TBTT_HOLD_TIME_AP_8822B(x) | BIT_TBTT_HOLD_TIME_AP_8822B(v))
+
+#define BIT_SHIFT_TBTT_PROHIBIT_SETUP_8822B 0
+#define BIT_MASK_TBTT_PROHIBIT_SETUP_8822B 0xf
+#define BIT_TBTT_PROHIBIT_SETUP_8822B(x)                                       \
+	(((x) & BIT_MASK_TBTT_PROHIBIT_SETUP_8822B)                            \
+	 << BIT_SHIFT_TBTT_PROHIBIT_SETUP_8822B)
+#define BITS_TBTT_PROHIBIT_SETUP_8822B                                         \
+	(BIT_MASK_TBTT_PROHIBIT_SETUP_8822B                                    \
+	 << BIT_SHIFT_TBTT_PROHIBIT_SETUP_8822B)
+#define BIT_CLEAR_TBTT_PROHIBIT_SETUP_8822B(x)                                 \
+	((x) & (~BITS_TBTT_PROHIBIT_SETUP_8822B))
+#define BIT_GET_TBTT_PROHIBIT_SETUP_8822B(x)                                   \
+	(((x) >> BIT_SHIFT_TBTT_PROHIBIT_SETUP_8822B) &                        \
+	 BIT_MASK_TBTT_PROHIBIT_SETUP_8822B)
+#define BIT_SET_TBTT_PROHIBIT_SETUP_8822B(x, v)                                \
+	(BIT_CLEAR_TBTT_PROHIBIT_SETUP_8822B(x) |                              \
+	 BIT_TBTT_PROHIBIT_SETUP_8822B(v))
+
+/* 2 REG_P2PPS_STATE_8822B */
+#define BIT_POWER_STATE_8822B BIT(7)
+#define BIT_CTWINDOW_ON_8822B BIT(6)
+#define BIT_BEACON_AREA_ON_8822B BIT(5)
+#define BIT_CTWIN_EARLY_DISTX_8822B BIT(4)
+#define BIT_NOA1_OFF_PERIOD_8822B BIT(3)
+#define BIT_FORCE_DOZE1_8822B BIT(2)
+#define BIT_NOA0_OFF_PERIOD_8822B BIT(1)
+#define BIT_FORCE_DOZE0_8822B BIT(0)
+
+/* 2 REG_RD_NAV_NXT_8822B */
+
+#define BIT_SHIFT_RD_NAV_PROT_NXT_8822B 0
+#define BIT_MASK_RD_NAV_PROT_NXT_8822B 0xffff
+#define BIT_RD_NAV_PROT_NXT_8822B(x)                                           \
+	(((x) & BIT_MASK_RD_NAV_PROT_NXT_8822B)                                \
+	 << BIT_SHIFT_RD_NAV_PROT_NXT_8822B)
+#define BITS_RD_NAV_PROT_NXT_8822B                                             \
+	(BIT_MASK_RD_NAV_PROT_NXT_8822B << BIT_SHIFT_RD_NAV_PROT_NXT_8822B)
+#define BIT_CLEAR_RD_NAV_PROT_NXT_8822B(x) ((x) & (~BITS_RD_NAV_PROT_NXT_8822B))
+#define BIT_GET_RD_NAV_PROT_NXT_8822B(x)                                       \
+	(((x) >> BIT_SHIFT_RD_NAV_PROT_NXT_8822B) &                            \
+	 BIT_MASK_RD_NAV_PROT_NXT_8822B)
+#define BIT_SET_RD_NAV_PROT_NXT_8822B(x, v)                                    \
+	(BIT_CLEAR_RD_NAV_PROT_NXT_8822B(x) | BIT_RD_NAV_PROT_NXT_8822B(v))
+
+/* 2 REG_NAV_PROT_LEN_8822B */
+
+#define BIT_SHIFT_NAV_PROT_LEN_8822B 0
+#define BIT_MASK_NAV_PROT_LEN_8822B 0xffff
+#define BIT_NAV_PROT_LEN_8822B(x)                                              \
+	(((x) & BIT_MASK_NAV_PROT_LEN_8822B) << BIT_SHIFT_NAV_PROT_LEN_8822B)
+#define BITS_NAV_PROT_LEN_8822B                                                \
+	(BIT_MASK_NAV_PROT_LEN_8822B << BIT_SHIFT_NAV_PROT_LEN_8822B)
+#define BIT_CLEAR_NAV_PROT_LEN_8822B(x) ((x) & (~BITS_NAV_PROT_LEN_8822B))
+#define BIT_GET_NAV_PROT_LEN_8822B(x)                                          \
+	(((x) >> BIT_SHIFT_NAV_PROT_LEN_8822B) & BIT_MASK_NAV_PROT_LEN_8822B)
+#define BIT_SET_NAV_PROT_LEN_8822B(x, v)                                       \
+	(BIT_CLEAR_NAV_PROT_LEN_8822B(x) | BIT_NAV_PROT_LEN_8822B(v))
+
+/* 2 REG_BCN_CTRL_8822B */
+#define BIT_DIS_RX_BSSID_FIT_8822B BIT(6)
+#define BIT_P0_EN_TXBCN_RPT_8822B BIT(5)
+#define BIT_DIS_TSF_UDT_8822B BIT(4)
+#define BIT_EN_BCN_FUNCTION_8822B BIT(3)
+#define BIT_P0_EN_RXBCN_RPT_8822B BIT(2)
+#define BIT_EN_P2P_CTWINDOW_8822B BIT(1)
+#define BIT_EN_P2P_BCNQ_AREA_8822B BIT(0)
+
+/* 2 REG_BCN_CTRL_CLINT0_8822B */
+#define BIT_CLI0_DIS_RX_BSSID_FIT_8822B BIT(6)
+#define BIT_CLI0_DIS_TSF_UDT_8822B BIT(4)
+#define BIT_CLI0_EN_BCN_FUNCTION_8822B BIT(3)
+#define BIT_CLI0_EN_RXBCN_RPT_8822B BIT(2)
+#define BIT_CLI0_ENP2P_CTWINDOW_8822B BIT(1)
+#define BIT_CLI0_ENP2P_BCNQ_AREA_8822B BIT(0)
+
+/* 2 REG_MBID_NUM_8822B */
+#define BIT_EN_PRE_DL_BEACON_8822B BIT(3)
+
+#define BIT_SHIFT_MBID_BCN_NUM_8822B 0
+#define BIT_MASK_MBID_BCN_NUM_8822B 0x7
+#define BIT_MBID_BCN_NUM_8822B(x)                                              \
+	(((x) & BIT_MASK_MBID_BCN_NUM_8822B) << BIT_SHIFT_MBID_BCN_NUM_8822B)
+#define BITS_MBID_BCN_NUM_8822B                                                \
+	(BIT_MASK_MBID_BCN_NUM_8822B << BIT_SHIFT_MBID_BCN_NUM_8822B)
+#define BIT_CLEAR_MBID_BCN_NUM_8822B(x) ((x) & (~BITS_MBID_BCN_NUM_8822B))
+#define BIT_GET_MBID_BCN_NUM_8822B(x)                                          \
+	(((x) >> BIT_SHIFT_MBID_BCN_NUM_8822B) & BIT_MASK_MBID_BCN_NUM_8822B)
+#define BIT_SET_MBID_BCN_NUM_8822B(x, v)                                       \
+	(BIT_CLEAR_MBID_BCN_NUM_8822B(x) | BIT_MBID_BCN_NUM_8822B(v))
+
+/* 2 REG_DUAL_TSF_RST_8822B */
+#define BIT_FREECNT_RST_8822B BIT(5)
+#define BIT_TSFTR_CLI3_RST_8822B BIT(4)
+#define BIT_TSFTR_CLI2_RST_8822B BIT(3)
+#define BIT_TSFTR_CLI1_RST_8822B BIT(2)
+#define BIT_TSFTR_CLI0_RST_8822B BIT(1)
+#define BIT_TSFTR_RST_8822B BIT(0)
+
+/* 2 REG_MBSSID_BCN_SPACE_8822B */
+
+#define BIT_SHIFT_BCN_TIMER_SEL_FWRD_8822B 28
+#define BIT_MASK_BCN_TIMER_SEL_FWRD_8822B 0x7
+#define BIT_BCN_TIMER_SEL_FWRD_8822B(x)                                        \
+	(((x) & BIT_MASK_BCN_TIMER_SEL_FWRD_8822B)                             \
+	 << BIT_SHIFT_BCN_TIMER_SEL_FWRD_8822B)
+#define BITS_BCN_TIMER_SEL_FWRD_8822B                                          \
+	(BIT_MASK_BCN_TIMER_SEL_FWRD_8822B                                     \
+	 << BIT_SHIFT_BCN_TIMER_SEL_FWRD_8822B)
+#define BIT_CLEAR_BCN_TIMER_SEL_FWRD_8822B(x)                                  \
+	((x) & (~BITS_BCN_TIMER_SEL_FWRD_8822B))
+#define BIT_GET_BCN_TIMER_SEL_FWRD_8822B(x)                                    \
+	(((x) >> BIT_SHIFT_BCN_TIMER_SEL_FWRD_8822B) &                         \
+	 BIT_MASK_BCN_TIMER_SEL_FWRD_8822B)
+#define BIT_SET_BCN_TIMER_SEL_FWRD_8822B(x, v)                                 \
+	(BIT_CLEAR_BCN_TIMER_SEL_FWRD_8822B(x) |                               \
+	 BIT_BCN_TIMER_SEL_FWRD_8822B(v))
+
+#define BIT_SHIFT_BCN_SPACE_CLINT0_8822B 16
+#define BIT_MASK_BCN_SPACE_CLINT0_8822B 0xfff
+#define BIT_BCN_SPACE_CLINT0_8822B(x)                                          \
+	(((x) & BIT_MASK_BCN_SPACE_CLINT0_8822B)                               \
+	 << BIT_SHIFT_BCN_SPACE_CLINT0_8822B)
+#define BITS_BCN_SPACE_CLINT0_8822B                                            \
+	(BIT_MASK_BCN_SPACE_CLINT0_8822B << BIT_SHIFT_BCN_SPACE_CLINT0_8822B)
+#define BIT_CLEAR_BCN_SPACE_CLINT0_8822B(x)                                    \
+	((x) & (~BITS_BCN_SPACE_CLINT0_8822B))
+#define BIT_GET_BCN_SPACE_CLINT0_8822B(x)                                      \
+	(((x) >> BIT_SHIFT_BCN_SPACE_CLINT0_8822B) &                           \
+	 BIT_MASK_BCN_SPACE_CLINT0_8822B)
+#define BIT_SET_BCN_SPACE_CLINT0_8822B(x, v)                                   \
+	(BIT_CLEAR_BCN_SPACE_CLINT0_8822B(x) | BIT_BCN_SPACE_CLINT0_8822B(v))
+
+#define BIT_SHIFT_BCN_SPACE0_8822B 0
+#define BIT_MASK_BCN_SPACE0_8822B 0xffff
+#define BIT_BCN_SPACE0_8822B(x)                                                \
+	(((x) & BIT_MASK_BCN_SPACE0_8822B) << BIT_SHIFT_BCN_SPACE0_8822B)
+#define BITS_BCN_SPACE0_8822B                                                  \
+	(BIT_MASK_BCN_SPACE0_8822B << BIT_SHIFT_BCN_SPACE0_8822B)
+#define BIT_CLEAR_BCN_SPACE0_8822B(x) ((x) & (~BITS_BCN_SPACE0_8822B))
+#define BIT_GET_BCN_SPACE0_8822B(x)                                            \
+	(((x) >> BIT_SHIFT_BCN_SPACE0_8822B) & BIT_MASK_BCN_SPACE0_8822B)
+#define BIT_SET_BCN_SPACE0_8822B(x, v)                                         \
+	(BIT_CLEAR_BCN_SPACE0_8822B(x) | BIT_BCN_SPACE0_8822B(v))
+
+/* 2 REG_DRVERLYINT_8822B */
+
+#define BIT_SHIFT_DRVERLYITV_8822B 0
+#define BIT_MASK_DRVERLYITV_8822B 0xff
+#define BIT_DRVERLYITV_8822B(x)                                                \
+	(((x) & BIT_MASK_DRVERLYITV_8822B) << BIT_SHIFT_DRVERLYITV_8822B)
+#define BITS_DRVERLYITV_8822B                                                  \
+	(BIT_MASK_DRVERLYITV_8822B << BIT_SHIFT_DRVERLYITV_8822B)
+#define BIT_CLEAR_DRVERLYITV_8822B(x) ((x) & (~BITS_DRVERLYITV_8822B))
+#define BIT_GET_DRVERLYITV_8822B(x)                                            \
+	(((x) >> BIT_SHIFT_DRVERLYITV_8822B) & BIT_MASK_DRVERLYITV_8822B)
+#define BIT_SET_DRVERLYITV_8822B(x, v)                                         \
+	(BIT_CLEAR_DRVERLYITV_8822B(x) | BIT_DRVERLYITV_8822B(v))
+
+/* 2 REG_BCNDMATIM_8822B */
+
+#define BIT_SHIFT_BCNDMATIM_8822B 0
+#define BIT_MASK_BCNDMATIM_8822B 0xff
+#define BIT_BCNDMATIM_8822B(x)                                                 \
+	(((x) & BIT_MASK_BCNDMATIM_8822B) << BIT_SHIFT_BCNDMATIM_8822B)
+#define BITS_BCNDMATIM_8822B                                                   \
+	(BIT_MASK_BCNDMATIM_8822B << BIT_SHIFT_BCNDMATIM_8822B)
+#define BIT_CLEAR_BCNDMATIM_8822B(x) ((x) & (~BITS_BCNDMATIM_8822B))
+#define BIT_GET_BCNDMATIM_8822B(x)                                             \
+	(((x) >> BIT_SHIFT_BCNDMATIM_8822B) & BIT_MASK_BCNDMATIM_8822B)
+#define BIT_SET_BCNDMATIM_8822B(x, v)                                          \
+	(BIT_CLEAR_BCNDMATIM_8822B(x) | BIT_BCNDMATIM_8822B(v))
+
+/* 2 REG_ATIMWND_8822B */
+
+#define BIT_SHIFT_ATIMWND0_8822B 0
+#define BIT_MASK_ATIMWND0_8822B 0xffff
+#define BIT_ATIMWND0_8822B(x)                                                  \
+	(((x) & BIT_MASK_ATIMWND0_8822B) << BIT_SHIFT_ATIMWND0_8822B)
+#define BITS_ATIMWND0_8822B                                                    \
+	(BIT_MASK_ATIMWND0_8822B << BIT_SHIFT_ATIMWND0_8822B)
+#define BIT_CLEAR_ATIMWND0_8822B(x) ((x) & (~BITS_ATIMWND0_8822B))
+#define BIT_GET_ATIMWND0_8822B(x)                                              \
+	(((x) >> BIT_SHIFT_ATIMWND0_8822B) & BIT_MASK_ATIMWND0_8822B)
+#define BIT_SET_ATIMWND0_8822B(x, v)                                           \
+	(BIT_CLEAR_ATIMWND0_8822B(x) | BIT_ATIMWND0_8822B(v))
+
+/* 2 REG_USTIME_TSF_8822B */
+
+#define BIT_SHIFT_USTIME_TSF_V1_8822B 0
+#define BIT_MASK_USTIME_TSF_V1_8822B 0xff
+#define BIT_USTIME_TSF_V1_8822B(x)                                             \
+	(((x) & BIT_MASK_USTIME_TSF_V1_8822B) << BIT_SHIFT_USTIME_TSF_V1_8822B)
+#define BITS_USTIME_TSF_V1_8822B                                               \
+	(BIT_MASK_USTIME_TSF_V1_8822B << BIT_SHIFT_USTIME_TSF_V1_8822B)
+#define BIT_CLEAR_USTIME_TSF_V1_8822B(x) ((x) & (~BITS_USTIME_TSF_V1_8822B))
+#define BIT_GET_USTIME_TSF_V1_8822B(x)                                         \
+	(((x) >> BIT_SHIFT_USTIME_TSF_V1_8822B) & BIT_MASK_USTIME_TSF_V1_8822B)
+#define BIT_SET_USTIME_TSF_V1_8822B(x, v)                                      \
+	(BIT_CLEAR_USTIME_TSF_V1_8822B(x) | BIT_USTIME_TSF_V1_8822B(v))
+
+/* 2 REG_BCN_MAX_ERR_8822B */
+
+#define BIT_SHIFT_BCN_MAX_ERR_8822B 0
+#define BIT_MASK_BCN_MAX_ERR_8822B 0xff
+#define BIT_BCN_MAX_ERR_8822B(x)                                               \
+	(((x) & BIT_MASK_BCN_MAX_ERR_8822B) << BIT_SHIFT_BCN_MAX_ERR_8822B)
+#define BITS_BCN_MAX_ERR_8822B                                                 \
+	(BIT_MASK_BCN_MAX_ERR_8822B << BIT_SHIFT_BCN_MAX_ERR_8822B)
+#define BIT_CLEAR_BCN_MAX_ERR_8822B(x) ((x) & (~BITS_BCN_MAX_ERR_8822B))
+#define BIT_GET_BCN_MAX_ERR_8822B(x)                                           \
+	(((x) >> BIT_SHIFT_BCN_MAX_ERR_8822B) & BIT_MASK_BCN_MAX_ERR_8822B)
+#define BIT_SET_BCN_MAX_ERR_8822B(x, v)                                        \
+	(BIT_CLEAR_BCN_MAX_ERR_8822B(x) | BIT_BCN_MAX_ERR_8822B(v))
+
+/* 2 REG_RXTSF_OFFSET_CCK_8822B */
+
+#define BIT_SHIFT_CCK_RXTSF_OFFSET_8822B 0
+#define BIT_MASK_CCK_RXTSF_OFFSET_8822B 0xff
+#define BIT_CCK_RXTSF_OFFSET_8822B(x)                                          \
+	(((x) & BIT_MASK_CCK_RXTSF_OFFSET_8822B)                               \
+	 << BIT_SHIFT_CCK_RXTSF_OFFSET_8822B)
+#define BITS_CCK_RXTSF_OFFSET_8822B                                            \
+	(BIT_MASK_CCK_RXTSF_OFFSET_8822B << BIT_SHIFT_CCK_RXTSF_OFFSET_8822B)
+#define BIT_CLEAR_CCK_RXTSF_OFFSET_8822B(x)                                    \
+	((x) & (~BITS_CCK_RXTSF_OFFSET_8822B))
+#define BIT_GET_CCK_RXTSF_OFFSET_8822B(x)                                      \
+	(((x) >> BIT_SHIFT_CCK_RXTSF_OFFSET_8822B) &                           \
+	 BIT_MASK_CCK_RXTSF_OFFSET_8822B)
+#define BIT_SET_CCK_RXTSF_OFFSET_8822B(x, v)                                   \
+	(BIT_CLEAR_CCK_RXTSF_OFFSET_8822B(x) | BIT_CCK_RXTSF_OFFSET_8822B(v))
+
+/* 2 REG_RXTSF_OFFSET_OFDM_8822B */
+
+#define BIT_SHIFT_OFDM_RXTSF_OFFSET_8822B 0
+#define BIT_MASK_OFDM_RXTSF_OFFSET_8822B 0xff
+#define BIT_OFDM_RXTSF_OFFSET_8822B(x)                                         \
+	(((x) & BIT_MASK_OFDM_RXTSF_OFFSET_8822B)                              \
+	 << BIT_SHIFT_OFDM_RXTSF_OFFSET_8822B)
+#define BITS_OFDM_RXTSF_OFFSET_8822B                                           \
+	(BIT_MASK_OFDM_RXTSF_OFFSET_8822B << BIT_SHIFT_OFDM_RXTSF_OFFSET_8822B)
+#define BIT_CLEAR_OFDM_RXTSF_OFFSET_8822B(x)                                   \
+	((x) & (~BITS_OFDM_RXTSF_OFFSET_8822B))
+#define BIT_GET_OFDM_RXTSF_OFFSET_8822B(x)                                     \
+	(((x) >> BIT_SHIFT_OFDM_RXTSF_OFFSET_8822B) &                          \
+	 BIT_MASK_OFDM_RXTSF_OFFSET_8822B)
+#define BIT_SET_OFDM_RXTSF_OFFSET_8822B(x, v)                                  \
+	(BIT_CLEAR_OFDM_RXTSF_OFFSET_8822B(x) | BIT_OFDM_RXTSF_OFFSET_8822B(v))
+
+/* 2 REG_TSFTR_8822B */
+
+#define BIT_SHIFT_TSF_TIMER_8822B 0
+#define BIT_MASK_TSF_TIMER_8822B 0xffffffffffffffffL
+#define BIT_TSF_TIMER_8822B(x)                                                 \
+	(((x) & BIT_MASK_TSF_TIMER_8822B) << BIT_SHIFT_TSF_TIMER_8822B)
+#define BITS_TSF_TIMER_8822B                                                   \
+	(BIT_MASK_TSF_TIMER_8822B << BIT_SHIFT_TSF_TIMER_8822B)
+#define BIT_CLEAR_TSF_TIMER_8822B(x) ((x) & (~BITS_TSF_TIMER_8822B))
+#define BIT_GET_TSF_TIMER_8822B(x)                                             \
+	(((x) >> BIT_SHIFT_TSF_TIMER_8822B) & BIT_MASK_TSF_TIMER_8822B)
+#define BIT_SET_TSF_TIMER_8822B(x, v)                                          \
+	(BIT_CLEAR_TSF_TIMER_8822B(x) | BIT_TSF_TIMER_8822B(v))
+
+/* 2 REG_FREERUN_CNT_8822B */
+
+#define BIT_SHIFT_FREERUN_CNT_8822B 0
+#define BIT_MASK_FREERUN_CNT_8822B 0xffffffffffffffffL
+#define BIT_FREERUN_CNT_8822B(x)                                               \
+	(((x) & BIT_MASK_FREERUN_CNT_8822B) << BIT_SHIFT_FREERUN_CNT_8822B)
+#define BITS_FREERUN_CNT_8822B                                                 \
+	(BIT_MASK_FREERUN_CNT_8822B << BIT_SHIFT_FREERUN_CNT_8822B)
+#define BIT_CLEAR_FREERUN_CNT_8822B(x) ((x) & (~BITS_FREERUN_CNT_8822B))
+#define BIT_GET_FREERUN_CNT_8822B(x)                                           \
+	(((x) >> BIT_SHIFT_FREERUN_CNT_8822B) & BIT_MASK_FREERUN_CNT_8822B)
+#define BIT_SET_FREERUN_CNT_8822B(x, v)                                        \
+	(BIT_CLEAR_FREERUN_CNT_8822B(x) | BIT_FREERUN_CNT_8822B(v))
+
+/* 2 REG_ATIMWND1_V1_8822B */
+
+#define BIT_SHIFT_ATIMWND1_V1_8822B 0
+#define BIT_MASK_ATIMWND1_V1_8822B 0xff
+#define BIT_ATIMWND1_V1_8822B(x)                                               \
+	(((x) & BIT_MASK_ATIMWND1_V1_8822B) << BIT_SHIFT_ATIMWND1_V1_8822B)
+#define BITS_ATIMWND1_V1_8822B                                                 \
+	(BIT_MASK_ATIMWND1_V1_8822B << BIT_SHIFT_ATIMWND1_V1_8822B)
+#define BIT_CLEAR_ATIMWND1_V1_8822B(x) ((x) & (~BITS_ATIMWND1_V1_8822B))
+#define BIT_GET_ATIMWND1_V1_8822B(x)                                           \
+	(((x) >> BIT_SHIFT_ATIMWND1_V1_8822B) & BIT_MASK_ATIMWND1_V1_8822B)
+#define BIT_SET_ATIMWND1_V1_8822B(x, v)                                        \
+	(BIT_CLEAR_ATIMWND1_V1_8822B(x) | BIT_ATIMWND1_V1_8822B(v))
+
+/* 2 REG_TBTT_PROHIBIT_INFRA_8822B */
+
+#define BIT_SHIFT_TBTT_PROHIBIT_INFRA_8822B 0
+#define BIT_MASK_TBTT_PROHIBIT_INFRA_8822B 0xff
+#define BIT_TBTT_PROHIBIT_INFRA_8822B(x)                                       \
+	(((x) & BIT_MASK_TBTT_PROHIBIT_INFRA_8822B)                            \
+	 << BIT_SHIFT_TBTT_PROHIBIT_INFRA_8822B)
+#define BITS_TBTT_PROHIBIT_INFRA_8822B                                         \
+	(BIT_MASK_TBTT_PROHIBIT_INFRA_8822B                                    \
+	 << BIT_SHIFT_TBTT_PROHIBIT_INFRA_8822B)
+#define BIT_CLEAR_TBTT_PROHIBIT_INFRA_8822B(x)                                 \
+	((x) & (~BITS_TBTT_PROHIBIT_INFRA_8822B))
+#define BIT_GET_TBTT_PROHIBIT_INFRA_8822B(x)                                   \
+	(((x) >> BIT_SHIFT_TBTT_PROHIBIT_INFRA_8822B) &                        \
+	 BIT_MASK_TBTT_PROHIBIT_INFRA_8822B)
+#define BIT_SET_TBTT_PROHIBIT_INFRA_8822B(x, v)                                \
+	(BIT_CLEAR_TBTT_PROHIBIT_INFRA_8822B(x) |                              \
+	 BIT_TBTT_PROHIBIT_INFRA_8822B(v))
+
+/* 2 REG_CTWND_8822B */
+
+#define BIT_SHIFT_CTWND_8822B 0
+#define BIT_MASK_CTWND_8822B 0xff
+#define BIT_CTWND_8822B(x)                                                     \
+	(((x) & BIT_MASK_CTWND_8822B) << BIT_SHIFT_CTWND_8822B)
+#define BITS_CTWND_8822B (BIT_MASK_CTWND_8822B << BIT_SHIFT_CTWND_8822B)
+#define BIT_CLEAR_CTWND_8822B(x) ((x) & (~BITS_CTWND_8822B))
+#define BIT_GET_CTWND_8822B(x)                                                 \
+	(((x) >> BIT_SHIFT_CTWND_8822B) & BIT_MASK_CTWND_8822B)
+#define BIT_SET_CTWND_8822B(x, v)                                              \
+	(BIT_CLEAR_CTWND_8822B(x) | BIT_CTWND_8822B(v))
+
+/* 2 REG_BCNIVLCUNT_8822B */
+
+#define BIT_SHIFT_BCNIVLCUNT_8822B 0
+#define BIT_MASK_BCNIVLCUNT_8822B 0x7f
+#define BIT_BCNIVLCUNT_8822B(x)                                                \
+	(((x) & BIT_MASK_BCNIVLCUNT_8822B) << BIT_SHIFT_BCNIVLCUNT_8822B)
+#define BITS_BCNIVLCUNT_8822B                                                  \
+	(BIT_MASK_BCNIVLCUNT_8822B << BIT_SHIFT_BCNIVLCUNT_8822B)
+#define BIT_CLEAR_BCNIVLCUNT_8822B(x) ((x) & (~BITS_BCNIVLCUNT_8822B))
+#define BIT_GET_BCNIVLCUNT_8822B(x)                                            \
+	(((x) >> BIT_SHIFT_BCNIVLCUNT_8822B) & BIT_MASK_BCNIVLCUNT_8822B)
+#define BIT_SET_BCNIVLCUNT_8822B(x, v)                                         \
+	(BIT_CLEAR_BCNIVLCUNT_8822B(x) | BIT_BCNIVLCUNT_8822B(v))
+
+/* 2 REG_BCNDROPCTRL_8822B */
+#define BIT_BEACON_DROP_EN_8822B BIT(7)
+
+#define BIT_SHIFT_BEACON_DROP_IVL_8822B 0
+#define BIT_MASK_BEACON_DROP_IVL_8822B 0x7f
+#define BIT_BEACON_DROP_IVL_8822B(x)                                           \
+	(((x) & BIT_MASK_BEACON_DROP_IVL_8822B)                                \
+	 << BIT_SHIFT_BEACON_DROP_IVL_8822B)
+#define BITS_BEACON_DROP_IVL_8822B                                             \
+	(BIT_MASK_BEACON_DROP_IVL_8822B << BIT_SHIFT_BEACON_DROP_IVL_8822B)
+#define BIT_CLEAR_BEACON_DROP_IVL_8822B(x) ((x) & (~BITS_BEACON_DROP_IVL_8822B))
+#define BIT_GET_BEACON_DROP_IVL_8822B(x)                                       \
+	(((x) >> BIT_SHIFT_BEACON_DROP_IVL_8822B) &                            \
+	 BIT_MASK_BEACON_DROP_IVL_8822B)
+#define BIT_SET_BEACON_DROP_IVL_8822B(x, v)                                    \
+	(BIT_CLEAR_BEACON_DROP_IVL_8822B(x) | BIT_BEACON_DROP_IVL_8822B(v))
+
+/* 2 REG_HGQ_TIMEOUT_PERIOD_8822B */
+
+#define BIT_SHIFT_HGQ_TIMEOUT_PERIOD_8822B 0
+#define BIT_MASK_HGQ_TIMEOUT_PERIOD_8822B 0xff
+#define BIT_HGQ_TIMEOUT_PERIOD_8822B(x)                                        \
+	(((x) & BIT_MASK_HGQ_TIMEOUT_PERIOD_8822B)                             \
+	 << BIT_SHIFT_HGQ_TIMEOUT_PERIOD_8822B)
+#define BITS_HGQ_TIMEOUT_PERIOD_8822B                                          \
+	(BIT_MASK_HGQ_TIMEOUT_PERIOD_8822B                                     \
+	 << BIT_SHIFT_HGQ_TIMEOUT_PERIOD_8822B)
+#define BIT_CLEAR_HGQ_TIMEOUT_PERIOD_8822B(x)                                  \
+	((x) & (~BITS_HGQ_TIMEOUT_PERIOD_8822B))
+#define BIT_GET_HGQ_TIMEOUT_PERIOD_8822B(x)                                    \
+	(((x) >> BIT_SHIFT_HGQ_TIMEOUT_PERIOD_8822B) &                         \
+	 BIT_MASK_HGQ_TIMEOUT_PERIOD_8822B)
+#define BIT_SET_HGQ_TIMEOUT_PERIOD_8822B(x, v)                                 \
+	(BIT_CLEAR_HGQ_TIMEOUT_PERIOD_8822B(x) |                               \
+	 BIT_HGQ_TIMEOUT_PERIOD_8822B(v))
+
+/* 2 REG_TXCMD_TIMEOUT_PERIOD_8822B */
+
+#define BIT_SHIFT_TXCMD_TIMEOUT_PERIOD_8822B 0
+#define BIT_MASK_TXCMD_TIMEOUT_PERIOD_8822B 0xff
+#define BIT_TXCMD_TIMEOUT_PERIOD_8822B(x)                                      \
+	(((x) & BIT_MASK_TXCMD_TIMEOUT_PERIOD_8822B)                           \
+	 << BIT_SHIFT_TXCMD_TIMEOUT_PERIOD_8822B)
+#define BITS_TXCMD_TIMEOUT_PERIOD_8822B                                        \
+	(BIT_MASK_TXCMD_TIMEOUT_PERIOD_8822B                                   \
+	 << BIT_SHIFT_TXCMD_TIMEOUT_PERIOD_8822B)
+#define BIT_CLEAR_TXCMD_TIMEOUT_PERIOD_8822B(x)                                \
+	((x) & (~BITS_TXCMD_TIMEOUT_PERIOD_8822B))
+#define BIT_GET_TXCMD_TIMEOUT_PERIOD_8822B(x)                                  \
+	(((x) >> BIT_SHIFT_TXCMD_TIMEOUT_PERIOD_8822B) &                       \
+	 BIT_MASK_TXCMD_TIMEOUT_PERIOD_8822B)
+#define BIT_SET_TXCMD_TIMEOUT_PERIOD_8822B(x, v)                               \
+	(BIT_CLEAR_TXCMD_TIMEOUT_PERIOD_8822B(x) |                             \
+	 BIT_TXCMD_TIMEOUT_PERIOD_8822B(v))
+
+/* 2 REG_MISC_CTRL_8822B */
+#define BIT_AUTO_SYNC_BY_TBTT_8822B BIT(6)
+#define BIT_DIS_TRX_CAL_BCN_8822B BIT(5)
+#define BIT_DIS_TX_CAL_TBTT_8822B BIT(4)
+#define BIT_EN_FREECNT_8822B BIT(3)
+#define BIT_BCN_AGGRESSION_8822B BIT(2)
+
+#define BIT_SHIFT_DIS_SECONDARY_CCA_8822B 0
+#define BIT_MASK_DIS_SECONDARY_CCA_8822B 0x3
+#define BIT_DIS_SECONDARY_CCA_8822B(x)                                         \
+	(((x) & BIT_MASK_DIS_SECONDARY_CCA_8822B)                              \
+	 << BIT_SHIFT_DIS_SECONDARY_CCA_8822B)
+#define BITS_DIS_SECONDARY_CCA_8822B                                           \
+	(BIT_MASK_DIS_SECONDARY_CCA_8822B << BIT_SHIFT_DIS_SECONDARY_CCA_8822B)
+#define BIT_CLEAR_DIS_SECONDARY_CCA_8822B(x)                                   \
+	((x) & (~BITS_DIS_SECONDARY_CCA_8822B))
+#define BIT_GET_DIS_SECONDARY_CCA_8822B(x)                                     \
+	(((x) >> BIT_SHIFT_DIS_SECONDARY_CCA_8822B) &                          \
+	 BIT_MASK_DIS_SECONDARY_CCA_8822B)
+#define BIT_SET_DIS_SECONDARY_CCA_8822B(x, v)                                  \
+	(BIT_CLEAR_DIS_SECONDARY_CCA_8822B(x) | BIT_DIS_SECONDARY_CCA_8822B(v))
+
+/* 2 REG_BCN_CTRL_CLINT1_8822B */
+#define BIT_CLI1_DIS_RX_BSSID_FIT_8822B BIT(6)
+#define BIT_CLI1_DIS_TSF_UDT_8822B BIT(4)
+#define BIT_CLI1_EN_BCN_FUNCTION_8822B BIT(3)
+#define BIT_CLI1_EN_RXBCN_RPT_8822B BIT(2)
+#define BIT_CLI1_ENP2P_CTWINDOW_8822B BIT(1)
+#define BIT_CLI1_ENP2P_BCNQ_AREA_8822B BIT(0)
+
+/* 2 REG_BCN_CTRL_CLINT2_8822B */
+#define BIT_CLI2_DIS_RX_BSSID_FIT_8822B BIT(6)
+#define BIT_CLI2_DIS_TSF_UDT_8822B BIT(4)
+#define BIT_CLI2_EN_BCN_FUNCTION_8822B BIT(3)
+#define BIT_CLI2_EN_RXBCN_RPT_8822B BIT(2)
+#define BIT_CLI2_ENP2P_CTWINDOW_8822B BIT(1)
+#define BIT_CLI2_ENP2P_BCNQ_AREA_8822B BIT(0)
+
+/* 2 REG_BCN_CTRL_CLINT3_8822B */
+#define BIT_CLI3_DIS_RX_BSSID_FIT_8822B BIT(6)
+#define BIT_CLI3_DIS_TSF_UDT_8822B BIT(4)
+#define BIT_CLI3_EN_BCN_FUNCTION_8822B BIT(3)
+#define BIT_CLI3_EN_RXBCN_RPT_8822B BIT(2)
+#define BIT_CLI3_ENP2P_CTWINDOW_8822B BIT(1)
+#define BIT_CLI3_ENP2P_BCNQ_AREA_8822B BIT(0)
+
+/* 2 REG_EXTEND_CTRL_8822B */
+#define BIT_EN_TSFBIT32_RST_P2P2_8822B BIT(5)
+#define BIT_EN_TSFBIT32_RST_P2P1_8822B BIT(4)
+
+#define BIT_SHIFT_PORT_SEL_8822B 0
+#define BIT_MASK_PORT_SEL_8822B 0x7
+#define BIT_PORT_SEL_8822B(x)                                                  \
+	(((x) & BIT_MASK_PORT_SEL_8822B) << BIT_SHIFT_PORT_SEL_8822B)
+#define BITS_PORT_SEL_8822B                                                    \
+	(BIT_MASK_PORT_SEL_8822B << BIT_SHIFT_PORT_SEL_8822B)
+#define BIT_CLEAR_PORT_SEL_8822B(x) ((x) & (~BITS_PORT_SEL_8822B))
+#define BIT_GET_PORT_SEL_8822B(x)                                              \
+	(((x) >> BIT_SHIFT_PORT_SEL_8822B) & BIT_MASK_PORT_SEL_8822B)
+#define BIT_SET_PORT_SEL_8822B(x, v)                                           \
+	(BIT_CLEAR_PORT_SEL_8822B(x) | BIT_PORT_SEL_8822B(v))
+
+/* 2 REG_P2PPS1_SPEC_STATE_8822B */
+#define BIT_P2P1_SPEC_POWER_STATE_8822B BIT(7)
+#define BIT_P2P1_SPEC_CTWINDOW_ON_8822B BIT(6)
+#define BIT_P2P1_SPEC_BCN_AREA_ON_8822B BIT(5)
+#define BIT_P2P1_SPEC_CTWIN_EARLY_DISTX_8822B BIT(4)
+#define BIT_P2P1_SPEC_NOA1_OFF_PERIOD_8822B BIT(3)
+#define BIT_P2P1_SPEC_FORCE_DOZE1_8822B BIT(2)
+#define BIT_P2P1_SPEC_NOA0_OFF_PERIOD_8822B BIT(1)
+#define BIT_P2P1_SPEC_FORCE_DOZE0_8822B BIT(0)
+
+/* 2 REG_P2PPS1_STATE_8822B */
+#define BIT_P2P1_POWER_STATE_8822B BIT(7)
+#define BIT_P2P1_CTWINDOW_ON_8822B BIT(6)
+#define BIT_P2P1_BEACON_AREA_ON_8822B BIT(5)
+#define BIT_P2P1_CTWIN_EARLY_DISTX_8822B BIT(4)
+#define BIT_P2P1_NOA1_OFF_PERIOD_8822B BIT(3)
+#define BIT_P2P1_FORCE_DOZE1_8822B BIT(2)
+#define BIT_P2P1_NOA0_OFF_PERIOD_8822B BIT(1)
+#define BIT_P2P1_FORCE_DOZE0_8822B BIT(0)
+
+/* 2 REG_P2PPS2_SPEC_STATE_8822B */
+#define BIT_P2P2_SPEC_POWER_STATE_8822B BIT(7)
+#define BIT_P2P2_SPEC_CTWINDOW_ON_8822B BIT(6)
+#define BIT_P2P2_SPEC_BCN_AREA_ON_8822B BIT(5)
+#define BIT_P2P2_SPEC_CTWIN_EARLY_DISTX_8822B BIT(4)
+#define BIT_P2P2_SPEC_NOA1_OFF_PERIOD_8822B BIT(3)
+#define BIT_P2P2_SPEC_FORCE_DOZE1_8822B BIT(2)
+#define BIT_P2P2_SPEC_NOA0_OFF_PERIOD_8822B BIT(1)
+#define BIT_P2P2_SPEC_FORCE_DOZE0_8822B BIT(0)
+
+/* 2 REG_P2PPS2_STATE_8822B */
+#define BIT_P2P2_POWER_STATE_8822B BIT(7)
+#define BIT_P2P2_CTWINDOW_ON_8822B BIT(6)
+#define BIT_P2P2_BEACON_AREA_ON_8822B BIT(5)
+#define BIT_P2P2_CTWIN_EARLY_DISTX_8822B BIT(4)
+#define BIT_P2P2_NOA1_OFF_PERIOD_8822B BIT(3)
+#define BIT_P2P2_FORCE_DOZE1_8822B BIT(2)
+#define BIT_P2P2_NOA0_OFF_PERIOD_8822B BIT(1)
+#define BIT_P2P2_FORCE_DOZE0_8822B BIT(0)
+
+/* 2 REG_PS_TIMER0_8822B */
+
+#define BIT_SHIFT_PSTIMER0_INT_8822B 5
+#define BIT_MASK_PSTIMER0_INT_8822B 0x7ffffff
+#define BIT_PSTIMER0_INT_8822B(x)                                              \
+	(((x) & BIT_MASK_PSTIMER0_INT_8822B) << BIT_SHIFT_PSTIMER0_INT_8822B)
+#define BITS_PSTIMER0_INT_8822B                                                \
+	(BIT_MASK_PSTIMER0_INT_8822B << BIT_SHIFT_PSTIMER0_INT_8822B)
+#define BIT_CLEAR_PSTIMER0_INT_8822B(x) ((x) & (~BITS_PSTIMER0_INT_8822B))
+#define BIT_GET_PSTIMER0_INT_8822B(x)                                          \
+	(((x) >> BIT_SHIFT_PSTIMER0_INT_8822B) & BIT_MASK_PSTIMER0_INT_8822B)
+#define BIT_SET_PSTIMER0_INT_8822B(x, v)                                       \
+	(BIT_CLEAR_PSTIMER0_INT_8822B(x) | BIT_PSTIMER0_INT_8822B(v))
+
+/* 2 REG_PS_TIMER1_8822B */
+
+#define BIT_SHIFT_PSTIMER1_INT_8822B 5
+#define BIT_MASK_PSTIMER1_INT_8822B 0x7ffffff
+#define BIT_PSTIMER1_INT_8822B(x)                                              \
+	(((x) & BIT_MASK_PSTIMER1_INT_8822B) << BIT_SHIFT_PSTIMER1_INT_8822B)
+#define BITS_PSTIMER1_INT_8822B                                                \
+	(BIT_MASK_PSTIMER1_INT_8822B << BIT_SHIFT_PSTIMER1_INT_8822B)
+#define BIT_CLEAR_PSTIMER1_INT_8822B(x) ((x) & (~BITS_PSTIMER1_INT_8822B))
+#define BIT_GET_PSTIMER1_INT_8822B(x)                                          \
+	(((x) >> BIT_SHIFT_PSTIMER1_INT_8822B) & BIT_MASK_PSTIMER1_INT_8822B)
+#define BIT_SET_PSTIMER1_INT_8822B(x, v)                                       \
+	(BIT_CLEAR_PSTIMER1_INT_8822B(x) | BIT_PSTIMER1_INT_8822B(v))
+
+/* 2 REG_PS_TIMER2_8822B */
+
+#define BIT_SHIFT_PSTIMER2_INT_8822B 5
+#define BIT_MASK_PSTIMER2_INT_8822B 0x7ffffff
+#define BIT_PSTIMER2_INT_8822B(x)                                              \
+	(((x) & BIT_MASK_PSTIMER2_INT_8822B) << BIT_SHIFT_PSTIMER2_INT_8822B)
+#define BITS_PSTIMER2_INT_8822B                                                \
+	(BIT_MASK_PSTIMER2_INT_8822B << BIT_SHIFT_PSTIMER2_INT_8822B)
+#define BIT_CLEAR_PSTIMER2_INT_8822B(x) ((x) & (~BITS_PSTIMER2_INT_8822B))
+#define BIT_GET_PSTIMER2_INT_8822B(x)                                          \
+	(((x) >> BIT_SHIFT_PSTIMER2_INT_8822B) & BIT_MASK_PSTIMER2_INT_8822B)
+#define BIT_SET_PSTIMER2_INT_8822B(x, v)                                       \
+	(BIT_CLEAR_PSTIMER2_INT_8822B(x) | BIT_PSTIMER2_INT_8822B(v))
+
+/* 2 REG_TBTT_CTN_AREA_8822B */
+
+#define BIT_SHIFT_TBTT_CTN_AREA_8822B 0
+#define BIT_MASK_TBTT_CTN_AREA_8822B 0xff
+#define BIT_TBTT_CTN_AREA_8822B(x)                                             \
+	(((x) & BIT_MASK_TBTT_CTN_AREA_8822B) << BIT_SHIFT_TBTT_CTN_AREA_8822B)
+#define BITS_TBTT_CTN_AREA_8822B                                               \
+	(BIT_MASK_TBTT_CTN_AREA_8822B << BIT_SHIFT_TBTT_CTN_AREA_8822B)
+#define BIT_CLEAR_TBTT_CTN_AREA_8822B(x) ((x) & (~BITS_TBTT_CTN_AREA_8822B))
+#define BIT_GET_TBTT_CTN_AREA_8822B(x)                                         \
+	(((x) >> BIT_SHIFT_TBTT_CTN_AREA_8822B) & BIT_MASK_TBTT_CTN_AREA_8822B)
+#define BIT_SET_TBTT_CTN_AREA_8822B(x, v)                                      \
+	(BIT_CLEAR_TBTT_CTN_AREA_8822B(x) | BIT_TBTT_CTN_AREA_8822B(v))
+
+/* 2 REG_FORCE_BCN_IFS_8822B */
+
+#define BIT_SHIFT_FORCE_BCN_IFS_8822B 0
+#define BIT_MASK_FORCE_BCN_IFS_8822B 0xff
+#define BIT_FORCE_BCN_IFS_8822B(x)                                             \
+	(((x) & BIT_MASK_FORCE_BCN_IFS_8822B) << BIT_SHIFT_FORCE_BCN_IFS_8822B)
+#define BITS_FORCE_BCN_IFS_8822B                                               \
+	(BIT_MASK_FORCE_BCN_IFS_8822B << BIT_SHIFT_FORCE_BCN_IFS_8822B)
+#define BIT_CLEAR_FORCE_BCN_IFS_8822B(x) ((x) & (~BITS_FORCE_BCN_IFS_8822B))
+#define BIT_GET_FORCE_BCN_IFS_8822B(x)                                         \
+	(((x) >> BIT_SHIFT_FORCE_BCN_IFS_8822B) & BIT_MASK_FORCE_BCN_IFS_8822B)
+#define BIT_SET_FORCE_BCN_IFS_8822B(x, v)                                      \
+	(BIT_CLEAR_FORCE_BCN_IFS_8822B(x) | BIT_FORCE_BCN_IFS_8822B(v))
+
+/* 2 REG_TXOP_MIN_8822B */
+
+#define BIT_SHIFT_TXOP_MIN_8822B 0
+#define BIT_MASK_TXOP_MIN_8822B 0x3fff
+#define BIT_TXOP_MIN_8822B(x)                                                  \
+	(((x) & BIT_MASK_TXOP_MIN_8822B) << BIT_SHIFT_TXOP_MIN_8822B)
+#define BITS_TXOP_MIN_8822B                                                    \
+	(BIT_MASK_TXOP_MIN_8822B << BIT_SHIFT_TXOP_MIN_8822B)
+#define BIT_CLEAR_TXOP_MIN_8822B(x) ((x) & (~BITS_TXOP_MIN_8822B))
+#define BIT_GET_TXOP_MIN_8822B(x)                                              \
+	(((x) >> BIT_SHIFT_TXOP_MIN_8822B) & BIT_MASK_TXOP_MIN_8822B)
+#define BIT_SET_TXOP_MIN_8822B(x, v)                                           \
+	(BIT_CLEAR_TXOP_MIN_8822B(x) | BIT_TXOP_MIN_8822B(v))
+
+/* 2 REG_PRE_BKF_TIME_8822B */
+
+#define BIT_SHIFT_PRE_BKF_TIME_8822B 0
+#define BIT_MASK_PRE_BKF_TIME_8822B 0xff
+#define BIT_PRE_BKF_TIME_8822B(x)                                              \
+	(((x) & BIT_MASK_PRE_BKF_TIME_8822B) << BIT_SHIFT_PRE_BKF_TIME_8822B)
+#define BITS_PRE_BKF_TIME_8822B                                                \
+	(BIT_MASK_PRE_BKF_TIME_8822B << BIT_SHIFT_PRE_BKF_TIME_8822B)
+#define BIT_CLEAR_PRE_BKF_TIME_8822B(x) ((x) & (~BITS_PRE_BKF_TIME_8822B))
+#define BIT_GET_PRE_BKF_TIME_8822B(x)                                          \
+	(((x) >> BIT_SHIFT_PRE_BKF_TIME_8822B) & BIT_MASK_PRE_BKF_TIME_8822B)
+#define BIT_SET_PRE_BKF_TIME_8822B(x, v)                                       \
+	(BIT_CLEAR_PRE_BKF_TIME_8822B(x) | BIT_PRE_BKF_TIME_8822B(v))
+
+/* 2 REG_CROSS_TXOP_CTRL_8822B */
+#define BIT_DTIM_BYPASS_8822B BIT(2)
+#define BIT_RTS_NAV_TXOP_8822B BIT(1)
+#define BIT_NOT_CROSS_TXOP_8822B BIT(0)
+
+/* 2 REG_ATIMWND2_8822B */
+
+#define BIT_SHIFT_ATIMWND2_8822B 0
+#define BIT_MASK_ATIMWND2_8822B 0xff
+#define BIT_ATIMWND2_8822B(x)                                                  \
+	(((x) & BIT_MASK_ATIMWND2_8822B) << BIT_SHIFT_ATIMWND2_8822B)
+#define BITS_ATIMWND2_8822B                                                    \
+	(BIT_MASK_ATIMWND2_8822B << BIT_SHIFT_ATIMWND2_8822B)
+#define BIT_CLEAR_ATIMWND2_8822B(x) ((x) & (~BITS_ATIMWND2_8822B))
+#define BIT_GET_ATIMWND2_8822B(x)                                              \
+	(((x) >> BIT_SHIFT_ATIMWND2_8822B) & BIT_MASK_ATIMWND2_8822B)
+#define BIT_SET_ATIMWND2_8822B(x, v)                                           \
+	(BIT_CLEAR_ATIMWND2_8822B(x) | BIT_ATIMWND2_8822B(v))
+
+/* 2 REG_ATIMWND3_8822B */
+
+#define BIT_SHIFT_ATIMWND3_8822B 0
+#define BIT_MASK_ATIMWND3_8822B 0xff
+#define BIT_ATIMWND3_8822B(x)                                                  \
+	(((x) & BIT_MASK_ATIMWND3_8822B) << BIT_SHIFT_ATIMWND3_8822B)
+#define BITS_ATIMWND3_8822B                                                    \
+	(BIT_MASK_ATIMWND3_8822B << BIT_SHIFT_ATIMWND3_8822B)
+#define BIT_CLEAR_ATIMWND3_8822B(x) ((x) & (~BITS_ATIMWND3_8822B))
+#define BIT_GET_ATIMWND3_8822B(x)                                              \
+	(((x) >> BIT_SHIFT_ATIMWND3_8822B) & BIT_MASK_ATIMWND3_8822B)
+#define BIT_SET_ATIMWND3_8822B(x, v)                                           \
+	(BIT_CLEAR_ATIMWND3_8822B(x) | BIT_ATIMWND3_8822B(v))
+
+/* 2 REG_ATIMWND4_8822B */
+
+#define BIT_SHIFT_ATIMWND4_8822B 0
+#define BIT_MASK_ATIMWND4_8822B 0xff
+#define BIT_ATIMWND4_8822B(x)                                                  \
+	(((x) & BIT_MASK_ATIMWND4_8822B) << BIT_SHIFT_ATIMWND4_8822B)
+#define BITS_ATIMWND4_8822B                                                    \
+	(BIT_MASK_ATIMWND4_8822B << BIT_SHIFT_ATIMWND4_8822B)
+#define BIT_CLEAR_ATIMWND4_8822B(x) ((x) & (~BITS_ATIMWND4_8822B))
+#define BIT_GET_ATIMWND4_8822B(x)                                              \
+	(((x) >> BIT_SHIFT_ATIMWND4_8822B) & BIT_MASK_ATIMWND4_8822B)
+#define BIT_SET_ATIMWND4_8822B(x, v)                                           \
+	(BIT_CLEAR_ATIMWND4_8822B(x) | BIT_ATIMWND4_8822B(v))
+
+/* 2 REG_ATIMWND5_8822B */
+
+#define BIT_SHIFT_ATIMWND5_8822B 0
+#define BIT_MASK_ATIMWND5_8822B 0xff
+#define BIT_ATIMWND5_8822B(x)                                                  \
+	(((x) & BIT_MASK_ATIMWND5_8822B) << BIT_SHIFT_ATIMWND5_8822B)
+#define BITS_ATIMWND5_8822B                                                    \
+	(BIT_MASK_ATIMWND5_8822B << BIT_SHIFT_ATIMWND5_8822B)
+#define BIT_CLEAR_ATIMWND5_8822B(x) ((x) & (~BITS_ATIMWND5_8822B))
+#define BIT_GET_ATIMWND5_8822B(x)                                              \
+	(((x) >> BIT_SHIFT_ATIMWND5_8822B) & BIT_MASK_ATIMWND5_8822B)
+#define BIT_SET_ATIMWND5_8822B(x, v)                                           \
+	(BIT_CLEAR_ATIMWND5_8822B(x) | BIT_ATIMWND5_8822B(v))
+
+/* 2 REG_ATIMWND6_8822B */
+
+#define BIT_SHIFT_ATIMWND6_8822B 0
+#define BIT_MASK_ATIMWND6_8822B 0xff
+#define BIT_ATIMWND6_8822B(x)                                                  \
+	(((x) & BIT_MASK_ATIMWND6_8822B) << BIT_SHIFT_ATIMWND6_8822B)
+#define BITS_ATIMWND6_8822B                                                    \
+	(BIT_MASK_ATIMWND6_8822B << BIT_SHIFT_ATIMWND6_8822B)
+#define BIT_CLEAR_ATIMWND6_8822B(x) ((x) & (~BITS_ATIMWND6_8822B))
+#define BIT_GET_ATIMWND6_8822B(x)                                              \
+	(((x) >> BIT_SHIFT_ATIMWND6_8822B) & BIT_MASK_ATIMWND6_8822B)
+#define BIT_SET_ATIMWND6_8822B(x, v)                                           \
+	(BIT_CLEAR_ATIMWND6_8822B(x) | BIT_ATIMWND6_8822B(v))
+
+/* 2 REG_ATIMWND7_8822B */
+
+#define BIT_SHIFT_ATIMWND7_8822B 0
+#define BIT_MASK_ATIMWND7_8822B 0xff
+#define BIT_ATIMWND7_8822B(x)                                                  \
+	(((x) & BIT_MASK_ATIMWND7_8822B) << BIT_SHIFT_ATIMWND7_8822B)
+#define BITS_ATIMWND7_8822B                                                    \
+	(BIT_MASK_ATIMWND7_8822B << BIT_SHIFT_ATIMWND7_8822B)
+#define BIT_CLEAR_ATIMWND7_8822B(x) ((x) & (~BITS_ATIMWND7_8822B))
+#define BIT_GET_ATIMWND7_8822B(x)                                              \
+	(((x) >> BIT_SHIFT_ATIMWND7_8822B) & BIT_MASK_ATIMWND7_8822B)
+#define BIT_SET_ATIMWND7_8822B(x, v)                                           \
+	(BIT_CLEAR_ATIMWND7_8822B(x) | BIT_ATIMWND7_8822B(v))
+
+/* 2 REG_ATIMUGT_8822B */
+
+#define BIT_SHIFT_ATIM_URGENT_8822B 0
+#define BIT_MASK_ATIM_URGENT_8822B 0xff
+#define BIT_ATIM_URGENT_8822B(x)                                               \
+	(((x) & BIT_MASK_ATIM_URGENT_8822B) << BIT_SHIFT_ATIM_URGENT_8822B)
+#define BITS_ATIM_URGENT_8822B                                                 \
+	(BIT_MASK_ATIM_URGENT_8822B << BIT_SHIFT_ATIM_URGENT_8822B)
+#define BIT_CLEAR_ATIM_URGENT_8822B(x) ((x) & (~BITS_ATIM_URGENT_8822B))
+#define BIT_GET_ATIM_URGENT_8822B(x)                                           \
+	(((x) >> BIT_SHIFT_ATIM_URGENT_8822B) & BIT_MASK_ATIM_URGENT_8822B)
+#define BIT_SET_ATIM_URGENT_8822B(x, v)                                        \
+	(BIT_CLEAR_ATIM_URGENT_8822B(x) | BIT_ATIM_URGENT_8822B(v))
+
+/* 2 REG_HIQ_NO_LMT_EN_8822B */
+#define BIT_HIQ_NO_LMT_EN_VAP7_8822B BIT(7)
+#define BIT_HIQ_NO_LMT_EN_VAP6_8822B BIT(6)
+#define BIT_HIQ_NO_LMT_EN_VAP5_8822B BIT(5)
+#define BIT_HIQ_NO_LMT_EN_VAP4_8822B BIT(4)
+#define BIT_HIQ_NO_LMT_EN_VAP3_8822B BIT(3)
+#define BIT_HIQ_NO_LMT_EN_VAP2_8822B BIT(2)
+#define BIT_HIQ_NO_LMT_EN_VAP1_8822B BIT(1)
+#define BIT_HIQ_NO_LMT_EN_ROOT_8822B BIT(0)
+
+/* 2 REG_DTIM_COUNTER_ROOT_8822B */
+
+#define BIT_SHIFT_DTIM_COUNT_ROOT_8822B 0
+#define BIT_MASK_DTIM_COUNT_ROOT_8822B 0xff
+#define BIT_DTIM_COUNT_ROOT_8822B(x)                                           \
+	(((x) & BIT_MASK_DTIM_COUNT_ROOT_8822B)                                \
+	 << BIT_SHIFT_DTIM_COUNT_ROOT_8822B)
+#define BITS_DTIM_COUNT_ROOT_8822B                                             \
+	(BIT_MASK_DTIM_COUNT_ROOT_8822B << BIT_SHIFT_DTIM_COUNT_ROOT_8822B)
+#define BIT_CLEAR_DTIM_COUNT_ROOT_8822B(x) ((x) & (~BITS_DTIM_COUNT_ROOT_8822B))
+#define BIT_GET_DTIM_COUNT_ROOT_8822B(x)                                       \
+	(((x) >> BIT_SHIFT_DTIM_COUNT_ROOT_8822B) &                            \
+	 BIT_MASK_DTIM_COUNT_ROOT_8822B)
+#define BIT_SET_DTIM_COUNT_ROOT_8822B(x, v)                                    \
+	(BIT_CLEAR_DTIM_COUNT_ROOT_8822B(x) | BIT_DTIM_COUNT_ROOT_8822B(v))
+
+/* 2 REG_DTIM_COUNTER_VAP1_8822B */
+
+#define BIT_SHIFT_DTIM_COUNT_VAP1_8822B 0
+#define BIT_MASK_DTIM_COUNT_VAP1_8822B 0xff
+#define BIT_DTIM_COUNT_VAP1_8822B(x)                                           \
+	(((x) & BIT_MASK_DTIM_COUNT_VAP1_8822B)                                \
+	 << BIT_SHIFT_DTIM_COUNT_VAP1_8822B)
+#define BITS_DTIM_COUNT_VAP1_8822B                                             \
+	(BIT_MASK_DTIM_COUNT_VAP1_8822B << BIT_SHIFT_DTIM_COUNT_VAP1_8822B)
+#define BIT_CLEAR_DTIM_COUNT_VAP1_8822B(x) ((x) & (~BITS_DTIM_COUNT_VAP1_8822B))
+#define BIT_GET_DTIM_COUNT_VAP1_8822B(x)                                       \
+	(((x) >> BIT_SHIFT_DTIM_COUNT_VAP1_8822B) &                            \
+	 BIT_MASK_DTIM_COUNT_VAP1_8822B)
+#define BIT_SET_DTIM_COUNT_VAP1_8822B(x, v)                                    \
+	(BIT_CLEAR_DTIM_COUNT_VAP1_8822B(x) | BIT_DTIM_COUNT_VAP1_8822B(v))
+
+/* 2 REG_DTIM_COUNTER_VAP2_8822B */
+
+#define BIT_SHIFT_DTIM_COUNT_VAP2_8822B 0
+#define BIT_MASK_DTIM_COUNT_VAP2_8822B 0xff
+#define BIT_DTIM_COUNT_VAP2_8822B(x)                                           \
+	(((x) & BIT_MASK_DTIM_COUNT_VAP2_8822B)                                \
+	 << BIT_SHIFT_DTIM_COUNT_VAP2_8822B)
+#define BITS_DTIM_COUNT_VAP2_8822B                                             \
+	(BIT_MASK_DTIM_COUNT_VAP2_8822B << BIT_SHIFT_DTIM_COUNT_VAP2_8822B)
+#define BIT_CLEAR_DTIM_COUNT_VAP2_8822B(x) ((x) & (~BITS_DTIM_COUNT_VAP2_8822B))
+#define BIT_GET_DTIM_COUNT_VAP2_8822B(x)                                       \
+	(((x) >> BIT_SHIFT_DTIM_COUNT_VAP2_8822B) &                            \
+	 BIT_MASK_DTIM_COUNT_VAP2_8822B)
+#define BIT_SET_DTIM_COUNT_VAP2_8822B(x, v)                                    \
+	(BIT_CLEAR_DTIM_COUNT_VAP2_8822B(x) | BIT_DTIM_COUNT_VAP2_8822B(v))
+
+/* 2 REG_DTIM_COUNTER_VAP3_8822B */
+
+#define BIT_SHIFT_DTIM_COUNT_VAP3_8822B 0
+#define BIT_MASK_DTIM_COUNT_VAP3_8822B 0xff
+#define BIT_DTIM_COUNT_VAP3_8822B(x)                                           \
+	(((x) & BIT_MASK_DTIM_COUNT_VAP3_8822B)                                \
+	 << BIT_SHIFT_DTIM_COUNT_VAP3_8822B)
+#define BITS_DTIM_COUNT_VAP3_8822B                                             \
+	(BIT_MASK_DTIM_COUNT_VAP3_8822B << BIT_SHIFT_DTIM_COUNT_VAP3_8822B)
+#define BIT_CLEAR_DTIM_COUNT_VAP3_8822B(x) ((x) & (~BITS_DTIM_COUNT_VAP3_8822B))
+#define BIT_GET_DTIM_COUNT_VAP3_8822B(x)                                       \
+	(((x) >> BIT_SHIFT_DTIM_COUNT_VAP3_8822B) &                            \
+	 BIT_MASK_DTIM_COUNT_VAP3_8822B)
+#define BIT_SET_DTIM_COUNT_VAP3_8822B(x, v)                                    \
+	(BIT_CLEAR_DTIM_COUNT_VAP3_8822B(x) | BIT_DTIM_COUNT_VAP3_8822B(v))
+
+/* 2 REG_DTIM_COUNTER_VAP4_8822B */
+
+#define BIT_SHIFT_DTIM_COUNT_VAP4_8822B 0
+#define BIT_MASK_DTIM_COUNT_VAP4_8822B 0xff
+#define BIT_DTIM_COUNT_VAP4_8822B(x)                                           \
+	(((x) & BIT_MASK_DTIM_COUNT_VAP4_8822B)                                \
+	 << BIT_SHIFT_DTIM_COUNT_VAP4_8822B)
+#define BITS_DTIM_COUNT_VAP4_8822B                                             \
+	(BIT_MASK_DTIM_COUNT_VAP4_8822B << BIT_SHIFT_DTIM_COUNT_VAP4_8822B)
+#define BIT_CLEAR_DTIM_COUNT_VAP4_8822B(x) ((x) & (~BITS_DTIM_COUNT_VAP4_8822B))
+#define BIT_GET_DTIM_COUNT_VAP4_8822B(x)                                       \
+	(((x) >> BIT_SHIFT_DTIM_COUNT_VAP4_8822B) &                            \
+	 BIT_MASK_DTIM_COUNT_VAP4_8822B)
+#define BIT_SET_DTIM_COUNT_VAP4_8822B(x, v)                                    \
+	(BIT_CLEAR_DTIM_COUNT_VAP4_8822B(x) | BIT_DTIM_COUNT_VAP4_8822B(v))
+
+/* 2 REG_DTIM_COUNTER_VAP5_8822B */
+
+#define BIT_SHIFT_DTIM_COUNT_VAP5_8822B 0
+#define BIT_MASK_DTIM_COUNT_VAP5_8822B 0xff
+#define BIT_DTIM_COUNT_VAP5_8822B(x)                                           \
+	(((x) & BIT_MASK_DTIM_COUNT_VAP5_8822B)                                \
+	 << BIT_SHIFT_DTIM_COUNT_VAP5_8822B)
+#define BITS_DTIM_COUNT_VAP5_8822B                                             \
+	(BIT_MASK_DTIM_COUNT_VAP5_8822B << BIT_SHIFT_DTIM_COUNT_VAP5_8822B)
+#define BIT_CLEAR_DTIM_COUNT_VAP5_8822B(x) ((x) & (~BITS_DTIM_COUNT_VAP5_8822B))
+#define BIT_GET_DTIM_COUNT_VAP5_8822B(x)                                       \
+	(((x) >> BIT_SHIFT_DTIM_COUNT_VAP5_8822B) &                            \
+	 BIT_MASK_DTIM_COUNT_VAP5_8822B)
+#define BIT_SET_DTIM_COUNT_VAP5_8822B(x, v)                                    \
+	(BIT_CLEAR_DTIM_COUNT_VAP5_8822B(x) | BIT_DTIM_COUNT_VAP5_8822B(v))
+
+/* 2 REG_DTIM_COUNTER_VAP6_8822B */
+
+#define BIT_SHIFT_DTIM_COUNT_VAP6_8822B 0
+#define BIT_MASK_DTIM_COUNT_VAP6_8822B 0xff
+#define BIT_DTIM_COUNT_VAP6_8822B(x)                                           \
+	(((x) & BIT_MASK_DTIM_COUNT_VAP6_8822B)                                \
+	 << BIT_SHIFT_DTIM_COUNT_VAP6_8822B)
+#define BITS_DTIM_COUNT_VAP6_8822B                                             \
+	(BIT_MASK_DTIM_COUNT_VAP6_8822B << BIT_SHIFT_DTIM_COUNT_VAP6_8822B)
+#define BIT_CLEAR_DTIM_COUNT_VAP6_8822B(x) ((x) & (~BITS_DTIM_COUNT_VAP6_8822B))
+#define BIT_GET_DTIM_COUNT_VAP6_8822B(x)                                       \
+	(((x) >> BIT_SHIFT_DTIM_COUNT_VAP6_8822B) &                            \
+	 BIT_MASK_DTIM_COUNT_VAP6_8822B)
+#define BIT_SET_DTIM_COUNT_VAP6_8822B(x, v)                                    \
+	(BIT_CLEAR_DTIM_COUNT_VAP6_8822B(x) | BIT_DTIM_COUNT_VAP6_8822B(v))
+
+/* 2 REG_DTIM_COUNTER_VAP7_8822B */
+
+#define BIT_SHIFT_DTIM_COUNT_VAP7_8822B 0
+#define BIT_MASK_DTIM_COUNT_VAP7_8822B 0xff
+#define BIT_DTIM_COUNT_VAP7_8822B(x)                                           \
+	(((x) & BIT_MASK_DTIM_COUNT_VAP7_8822B)                                \
+	 << BIT_SHIFT_DTIM_COUNT_VAP7_8822B)
+#define BITS_DTIM_COUNT_VAP7_8822B                                             \
+	(BIT_MASK_DTIM_COUNT_VAP7_8822B << BIT_SHIFT_DTIM_COUNT_VAP7_8822B)
+#define BIT_CLEAR_DTIM_COUNT_VAP7_8822B(x) ((x) & (~BITS_DTIM_COUNT_VAP7_8822B))
+#define BIT_GET_DTIM_COUNT_VAP7_8822B(x)                                       \
+	(((x) >> BIT_SHIFT_DTIM_COUNT_VAP7_8822B) &                            \
+	 BIT_MASK_DTIM_COUNT_VAP7_8822B)
+#define BIT_SET_DTIM_COUNT_VAP7_8822B(x, v)                                    \
+	(BIT_CLEAR_DTIM_COUNT_VAP7_8822B(x) | BIT_DTIM_COUNT_VAP7_8822B(v))
+
+/* 2 REG_DIS_ATIM_8822B */
+#define BIT_DIS_ATIM_VAP7_8822B BIT(7)
+#define BIT_DIS_ATIM_VAP6_8822B BIT(6)
+#define BIT_DIS_ATIM_VAP5_8822B BIT(5)
+#define BIT_DIS_ATIM_VAP4_8822B BIT(4)
+#define BIT_DIS_ATIM_VAP3_8822B BIT(3)
+#define BIT_DIS_ATIM_VAP2_8822B BIT(2)
+#define BIT_DIS_ATIM_VAP1_8822B BIT(1)
+#define BIT_DIS_ATIM_ROOT_8822B BIT(0)
+
+/* 2 REG_EARLY_128US_8822B */
+
+#define BIT_SHIFT_TSFT_SEL_TIMER1_8822B 3
+#define BIT_MASK_TSFT_SEL_TIMER1_8822B 0x7
+#define BIT_TSFT_SEL_TIMER1_8822B(x)                                           \
+	(((x) & BIT_MASK_TSFT_SEL_TIMER1_8822B)                                \
+	 << BIT_SHIFT_TSFT_SEL_TIMER1_8822B)
+#define BITS_TSFT_SEL_TIMER1_8822B                                             \
+	(BIT_MASK_TSFT_SEL_TIMER1_8822B << BIT_SHIFT_TSFT_SEL_TIMER1_8822B)
+#define BIT_CLEAR_TSFT_SEL_TIMER1_8822B(x) ((x) & (~BITS_TSFT_SEL_TIMER1_8822B))
+#define BIT_GET_TSFT_SEL_TIMER1_8822B(x)                                       \
+	(((x) >> BIT_SHIFT_TSFT_SEL_TIMER1_8822B) &                            \
+	 BIT_MASK_TSFT_SEL_TIMER1_8822B)
+#define BIT_SET_TSFT_SEL_TIMER1_8822B(x, v)                                    \
+	(BIT_CLEAR_TSFT_SEL_TIMER1_8822B(x) | BIT_TSFT_SEL_TIMER1_8822B(v))
+
+#define BIT_SHIFT_EARLY_128US_8822B 0
+#define BIT_MASK_EARLY_128US_8822B 0x7
+#define BIT_EARLY_128US_8822B(x)                                               \
+	(((x) & BIT_MASK_EARLY_128US_8822B) << BIT_SHIFT_EARLY_128US_8822B)
+#define BITS_EARLY_128US_8822B                                                 \
+	(BIT_MASK_EARLY_128US_8822B << BIT_SHIFT_EARLY_128US_8822B)
+#define BIT_CLEAR_EARLY_128US_8822B(x) ((x) & (~BITS_EARLY_128US_8822B))
+#define BIT_GET_EARLY_128US_8822B(x)                                           \
+	(((x) >> BIT_SHIFT_EARLY_128US_8822B) & BIT_MASK_EARLY_128US_8822B)
+#define BIT_SET_EARLY_128US_8822B(x, v)                                        \
+	(BIT_CLEAR_EARLY_128US_8822B(x) | BIT_EARLY_128US_8822B(v))
+
+/* 2 REG_P2PPS1_CTRL_8822B */
+#define BIT_P2P1_CTW_ALLSTASLEEP_8822B BIT(7)
+#define BIT_P2P1_OFF_DISTX_EN_8822B BIT(6)
+#define BIT_P2P1_PWR_MGT_EN_8822B BIT(5)
+#define BIT_P2P1_NOA1_EN_8822B BIT(2)
+#define BIT_P2P1_NOA0_EN_8822B BIT(1)
+
+/* 2 REG_P2PPS2_CTRL_8822B */
+#define BIT_P2P2_CTW_ALLSTASLEEP_8822B BIT(7)
+#define BIT_P2P2_OFF_DISTX_EN_8822B BIT(6)
+#define BIT_P2P2_PWR_MGT_EN_8822B BIT(5)
+#define BIT_P2P2_NOA1_EN_8822B BIT(2)
+#define BIT_P2P2_NOA0_EN_8822B BIT(1)
+
+/* 2 REG_TIMER0_SRC_SEL_8822B */
+
+#define BIT_SHIFT_SYNC_CLI_SEL_8822B 4
+#define BIT_MASK_SYNC_CLI_SEL_8822B 0x7
+#define BIT_SYNC_CLI_SEL_8822B(x)                                              \
+	(((x) & BIT_MASK_SYNC_CLI_SEL_8822B) << BIT_SHIFT_SYNC_CLI_SEL_8822B)
+#define BITS_SYNC_CLI_SEL_8822B                                                \
+	(BIT_MASK_SYNC_CLI_SEL_8822B << BIT_SHIFT_SYNC_CLI_SEL_8822B)
+#define BIT_CLEAR_SYNC_CLI_SEL_8822B(x) ((x) & (~BITS_SYNC_CLI_SEL_8822B))
+#define BIT_GET_SYNC_CLI_SEL_8822B(x)                                          \
+	(((x) >> BIT_SHIFT_SYNC_CLI_SEL_8822B) & BIT_MASK_SYNC_CLI_SEL_8822B)
+#define BIT_SET_SYNC_CLI_SEL_8822B(x, v)                                       \
+	(BIT_CLEAR_SYNC_CLI_SEL_8822B(x) | BIT_SYNC_CLI_SEL_8822B(v))
+
+#define BIT_SHIFT_TSFT_SEL_TIMER0_8822B 0
+#define BIT_MASK_TSFT_SEL_TIMER0_8822B 0x7
+#define BIT_TSFT_SEL_TIMER0_8822B(x)                                           \
+	(((x) & BIT_MASK_TSFT_SEL_TIMER0_8822B)                                \
+	 << BIT_SHIFT_TSFT_SEL_TIMER0_8822B)
+#define BITS_TSFT_SEL_TIMER0_8822B                                             \
+	(BIT_MASK_TSFT_SEL_TIMER0_8822B << BIT_SHIFT_TSFT_SEL_TIMER0_8822B)
+#define BIT_CLEAR_TSFT_SEL_TIMER0_8822B(x) ((x) & (~BITS_TSFT_SEL_TIMER0_8822B))
+#define BIT_GET_TSFT_SEL_TIMER0_8822B(x)                                       \
+	(((x) >> BIT_SHIFT_TSFT_SEL_TIMER0_8822B) &                            \
+	 BIT_MASK_TSFT_SEL_TIMER0_8822B)
+#define BIT_SET_TSFT_SEL_TIMER0_8822B(x, v)                                    \
+	(BIT_CLEAR_TSFT_SEL_TIMER0_8822B(x) | BIT_TSFT_SEL_TIMER0_8822B(v))
+
+/* 2 REG_NOA_UNIT_SEL_8822B */
+
+#define BIT_SHIFT_NOA_UNIT2_SEL_8822B 8
+#define BIT_MASK_NOA_UNIT2_SEL_8822B 0x7
+#define BIT_NOA_UNIT2_SEL_8822B(x)                                             \
+	(((x) & BIT_MASK_NOA_UNIT2_SEL_8822B) << BIT_SHIFT_NOA_UNIT2_SEL_8822B)
+#define BITS_NOA_UNIT2_SEL_8822B                                               \
+	(BIT_MASK_NOA_UNIT2_SEL_8822B << BIT_SHIFT_NOA_UNIT2_SEL_8822B)
+#define BIT_CLEAR_NOA_UNIT2_SEL_8822B(x) ((x) & (~BITS_NOA_UNIT2_SEL_8822B))
+#define BIT_GET_NOA_UNIT2_SEL_8822B(x)                                         \
+	(((x) >> BIT_SHIFT_NOA_UNIT2_SEL_8822B) & BIT_MASK_NOA_UNIT2_SEL_8822B)
+#define BIT_SET_NOA_UNIT2_SEL_8822B(x, v)                                      \
+	(BIT_CLEAR_NOA_UNIT2_SEL_8822B(x) | BIT_NOA_UNIT2_SEL_8822B(v))
+
+#define BIT_SHIFT_NOA_UNIT1_SEL_8822B 4
+#define BIT_MASK_NOA_UNIT1_SEL_8822B 0x7
+#define BIT_NOA_UNIT1_SEL_8822B(x)                                             \
+	(((x) & BIT_MASK_NOA_UNIT1_SEL_8822B) << BIT_SHIFT_NOA_UNIT1_SEL_8822B)
+#define BITS_NOA_UNIT1_SEL_8822B                                               \
+	(BIT_MASK_NOA_UNIT1_SEL_8822B << BIT_SHIFT_NOA_UNIT1_SEL_8822B)
+#define BIT_CLEAR_NOA_UNIT1_SEL_8822B(x) ((x) & (~BITS_NOA_UNIT1_SEL_8822B))
+#define BIT_GET_NOA_UNIT1_SEL_8822B(x)                                         \
+	(((x) >> BIT_SHIFT_NOA_UNIT1_SEL_8822B) & BIT_MASK_NOA_UNIT1_SEL_8822B)
+#define BIT_SET_NOA_UNIT1_SEL_8822B(x, v)                                      \
+	(BIT_CLEAR_NOA_UNIT1_SEL_8822B(x) | BIT_NOA_UNIT1_SEL_8822B(v))
+
+#define BIT_SHIFT_NOA_UNIT0_SEL_8822B 0
+#define BIT_MASK_NOA_UNIT0_SEL_8822B 0x7
+#define BIT_NOA_UNIT0_SEL_8822B(x)                                             \
+	(((x) & BIT_MASK_NOA_UNIT0_SEL_8822B) << BIT_SHIFT_NOA_UNIT0_SEL_8822B)
+#define BITS_NOA_UNIT0_SEL_8822B                                               \
+	(BIT_MASK_NOA_UNIT0_SEL_8822B << BIT_SHIFT_NOA_UNIT0_SEL_8822B)
+#define BIT_CLEAR_NOA_UNIT0_SEL_8822B(x) ((x) & (~BITS_NOA_UNIT0_SEL_8822B))
+#define BIT_GET_NOA_UNIT0_SEL_8822B(x)                                         \
+	(((x) >> BIT_SHIFT_NOA_UNIT0_SEL_8822B) & BIT_MASK_NOA_UNIT0_SEL_8822B)
+#define BIT_SET_NOA_UNIT0_SEL_8822B(x, v)                                      \
+	(BIT_CLEAR_NOA_UNIT0_SEL_8822B(x) | BIT_NOA_UNIT0_SEL_8822B(v))
+
+/* 2 REG_P2POFF_DIS_TXTIME_8822B */
+
+#define BIT_SHIFT_P2POFF_DIS_TXTIME_8822B 0
+#define BIT_MASK_P2POFF_DIS_TXTIME_8822B 0xff
+#define BIT_P2POFF_DIS_TXTIME_8822B(x)                                         \
+	(((x) & BIT_MASK_P2POFF_DIS_TXTIME_8822B)                              \
+	 << BIT_SHIFT_P2POFF_DIS_TXTIME_8822B)
+#define BITS_P2POFF_DIS_TXTIME_8822B                                           \
+	(BIT_MASK_P2POFF_DIS_TXTIME_8822B << BIT_SHIFT_P2POFF_DIS_TXTIME_8822B)
+#define BIT_CLEAR_P2POFF_DIS_TXTIME_8822B(x)                                   \
+	((x) & (~BITS_P2POFF_DIS_TXTIME_8822B))
+#define BIT_GET_P2POFF_DIS_TXTIME_8822B(x)                                     \
+	(((x) >> BIT_SHIFT_P2POFF_DIS_TXTIME_8822B) &                          \
+	 BIT_MASK_P2POFF_DIS_TXTIME_8822B)
+#define BIT_SET_P2POFF_DIS_TXTIME_8822B(x, v)                                  \
+	(BIT_CLEAR_P2POFF_DIS_TXTIME_8822B(x) | BIT_P2POFF_DIS_TXTIME_8822B(v))
+
+/* 2 REG_MBSSID_BCN_SPACE2_8822B */
+
+#define BIT_SHIFT_BCN_SPACE_CLINT2_8822B 16
+#define BIT_MASK_BCN_SPACE_CLINT2_8822B 0xfff
+#define BIT_BCN_SPACE_CLINT2_8822B(x)                                          \
+	(((x) & BIT_MASK_BCN_SPACE_CLINT2_8822B)                               \
+	 << BIT_SHIFT_BCN_SPACE_CLINT2_8822B)
+#define BITS_BCN_SPACE_CLINT2_8822B                                            \
+	(BIT_MASK_BCN_SPACE_CLINT2_8822B << BIT_SHIFT_BCN_SPACE_CLINT2_8822B)
+#define BIT_CLEAR_BCN_SPACE_CLINT2_8822B(x)                                    \
+	((x) & (~BITS_BCN_SPACE_CLINT2_8822B))
+#define BIT_GET_BCN_SPACE_CLINT2_8822B(x)                                      \
+	(((x) >> BIT_SHIFT_BCN_SPACE_CLINT2_8822B) &                           \
+	 BIT_MASK_BCN_SPACE_CLINT2_8822B)
+#define BIT_SET_BCN_SPACE_CLINT2_8822B(x, v)                                   \
+	(BIT_CLEAR_BCN_SPACE_CLINT2_8822B(x) | BIT_BCN_SPACE_CLINT2_8822B(v))
+
+#define BIT_SHIFT_BCN_SPACE_CLINT1_8822B 0
+#define BIT_MASK_BCN_SPACE_CLINT1_8822B 0xfff
+#define BIT_BCN_SPACE_CLINT1_8822B(x)                                          \
+	(((x) & BIT_MASK_BCN_SPACE_CLINT1_8822B)                               \
+	 << BIT_SHIFT_BCN_SPACE_CLINT1_8822B)
+#define BITS_BCN_SPACE_CLINT1_8822B                                            \
+	(BIT_MASK_BCN_SPACE_CLINT1_8822B << BIT_SHIFT_BCN_SPACE_CLINT1_8822B)
+#define BIT_CLEAR_BCN_SPACE_CLINT1_8822B(x)                                    \
+	((x) & (~BITS_BCN_SPACE_CLINT1_8822B))
+#define BIT_GET_BCN_SPACE_CLINT1_8822B(x)                                      \
+	(((x) >> BIT_SHIFT_BCN_SPACE_CLINT1_8822B) &                           \
+	 BIT_MASK_BCN_SPACE_CLINT1_8822B)
+#define BIT_SET_BCN_SPACE_CLINT1_8822B(x, v)                                   \
+	(BIT_CLEAR_BCN_SPACE_CLINT1_8822B(x) | BIT_BCN_SPACE_CLINT1_8822B(v))
+
+/* 2 REG_MBSSID_BCN_SPACE3_8822B */
+
+#define BIT_SHIFT_SUB_BCN_SPACE_8822B 16
+#define BIT_MASK_SUB_BCN_SPACE_8822B 0xff
+#define BIT_SUB_BCN_SPACE_8822B(x)                                             \
+	(((x) & BIT_MASK_SUB_BCN_SPACE_8822B) << BIT_SHIFT_SUB_BCN_SPACE_8822B)
+#define BITS_SUB_BCN_SPACE_8822B                                               \
+	(BIT_MASK_SUB_BCN_SPACE_8822B << BIT_SHIFT_SUB_BCN_SPACE_8822B)
+#define BIT_CLEAR_SUB_BCN_SPACE_8822B(x) ((x) & (~BITS_SUB_BCN_SPACE_8822B))
+#define BIT_GET_SUB_BCN_SPACE_8822B(x)                                         \
+	(((x) >> BIT_SHIFT_SUB_BCN_SPACE_8822B) & BIT_MASK_SUB_BCN_SPACE_8822B)
+#define BIT_SET_SUB_BCN_SPACE_8822B(x, v)                                      \
+	(BIT_CLEAR_SUB_BCN_SPACE_8822B(x) | BIT_SUB_BCN_SPACE_8822B(v))
+
+#define BIT_SHIFT_BCN_SPACE_CLINT3_8822B 0
+#define BIT_MASK_BCN_SPACE_CLINT3_8822B 0xfff
+#define BIT_BCN_SPACE_CLINT3_8822B(x)                                          \
+	(((x) & BIT_MASK_BCN_SPACE_CLINT3_8822B)                               \
+	 << BIT_SHIFT_BCN_SPACE_CLINT3_8822B)
+#define BITS_BCN_SPACE_CLINT3_8822B                                            \
+	(BIT_MASK_BCN_SPACE_CLINT3_8822B << BIT_SHIFT_BCN_SPACE_CLINT3_8822B)
+#define BIT_CLEAR_BCN_SPACE_CLINT3_8822B(x)                                    \
+	((x) & (~BITS_BCN_SPACE_CLINT3_8822B))
+#define BIT_GET_BCN_SPACE_CLINT3_8822B(x)                                      \
+	(((x) >> BIT_SHIFT_BCN_SPACE_CLINT3_8822B) &                           \
+	 BIT_MASK_BCN_SPACE_CLINT3_8822B)
+#define BIT_SET_BCN_SPACE_CLINT3_8822B(x, v)                                   \
+	(BIT_CLEAR_BCN_SPACE_CLINT3_8822B(x) | BIT_BCN_SPACE_CLINT3_8822B(v))
+
+/* 2 REG_ACMHWCTRL_8822B */
+#define BIT_BEQ_ACM_STATUS_8822B BIT(7)
+#define BIT_VIQ_ACM_STATUS_8822B BIT(6)
+#define BIT_VOQ_ACM_STATUS_8822B BIT(5)
+#define BIT_BEQ_ACM_EN_8822B BIT(3)
+#define BIT_VIQ_ACM_EN_8822B BIT(2)
+#define BIT_VOQ_ACM_EN_8822B BIT(1)
+#define BIT_ACMHWEN_8822B BIT(0)
+
+/* 2 REG_ACMRSTCTRL_8822B */
+#define BIT_BE_ACM_RESET_USED_TIME_8822B BIT(2)
+#define BIT_VI_ACM_RESET_USED_TIME_8822B BIT(1)
+#define BIT_VO_ACM_RESET_USED_TIME_8822B BIT(0)
+
+/* 2 REG_ACMAVG_8822B */
+
+#define BIT_SHIFT_AVGPERIOD_8822B 0
+#define BIT_MASK_AVGPERIOD_8822B 0xffff
+#define BIT_AVGPERIOD_8822B(x)                                                 \
+	(((x) & BIT_MASK_AVGPERIOD_8822B) << BIT_SHIFT_AVGPERIOD_8822B)
+#define BITS_AVGPERIOD_8822B                                                   \
+	(BIT_MASK_AVGPERIOD_8822B << BIT_SHIFT_AVGPERIOD_8822B)
+#define BIT_CLEAR_AVGPERIOD_8822B(x) ((x) & (~BITS_AVGPERIOD_8822B))
+#define BIT_GET_AVGPERIOD_8822B(x)                                             \
+	(((x) >> BIT_SHIFT_AVGPERIOD_8822B) & BIT_MASK_AVGPERIOD_8822B)
+#define BIT_SET_AVGPERIOD_8822B(x, v)                                          \
+	(BIT_CLEAR_AVGPERIOD_8822B(x) | BIT_AVGPERIOD_8822B(v))
+
+/* 2 REG_VO_ADMTIME_8822B */
+
+#define BIT_SHIFT_VO_ADMITTED_TIME_8822B 0
+#define BIT_MASK_VO_ADMITTED_TIME_8822B 0xffff
+#define BIT_VO_ADMITTED_TIME_8822B(x)                                          \
+	(((x) & BIT_MASK_VO_ADMITTED_TIME_8822B)                               \
+	 << BIT_SHIFT_VO_ADMITTED_TIME_8822B)
+#define BITS_VO_ADMITTED_TIME_8822B                                            \
+	(BIT_MASK_VO_ADMITTED_TIME_8822B << BIT_SHIFT_VO_ADMITTED_TIME_8822B)
+#define BIT_CLEAR_VO_ADMITTED_TIME_8822B(x)                                    \
+	((x) & (~BITS_VO_ADMITTED_TIME_8822B))
+#define BIT_GET_VO_ADMITTED_TIME_8822B(x)                                      \
+	(((x) >> BIT_SHIFT_VO_ADMITTED_TIME_8822B) &                           \
+	 BIT_MASK_VO_ADMITTED_TIME_8822B)
+#define BIT_SET_VO_ADMITTED_TIME_8822B(x, v)                                   \
+	(BIT_CLEAR_VO_ADMITTED_TIME_8822B(x) | BIT_VO_ADMITTED_TIME_8822B(v))
+
+/* 2 REG_VI_ADMTIME_8822B */
+
+#define BIT_SHIFT_VI_ADMITTED_TIME_8822B 0
+#define BIT_MASK_VI_ADMITTED_TIME_8822B 0xffff
+#define BIT_VI_ADMITTED_TIME_8822B(x)                                          \
+	(((x) & BIT_MASK_VI_ADMITTED_TIME_8822B)                               \
+	 << BIT_SHIFT_VI_ADMITTED_TIME_8822B)
+#define BITS_VI_ADMITTED_TIME_8822B                                            \
+	(BIT_MASK_VI_ADMITTED_TIME_8822B << BIT_SHIFT_VI_ADMITTED_TIME_8822B)
+#define BIT_CLEAR_VI_ADMITTED_TIME_8822B(x)                                    \
+	((x) & (~BITS_VI_ADMITTED_TIME_8822B))
+#define BIT_GET_VI_ADMITTED_TIME_8822B(x)                                      \
+	(((x) >> BIT_SHIFT_VI_ADMITTED_TIME_8822B) &                           \
+	 BIT_MASK_VI_ADMITTED_TIME_8822B)
+#define BIT_SET_VI_ADMITTED_TIME_8822B(x, v)                                   \
+	(BIT_CLEAR_VI_ADMITTED_TIME_8822B(x) | BIT_VI_ADMITTED_TIME_8822B(v))
+
+/* 2 REG_BE_ADMTIME_8822B */
+
+#define BIT_SHIFT_BE_ADMITTED_TIME_8822B 0
+#define BIT_MASK_BE_ADMITTED_TIME_8822B 0xffff
+#define BIT_BE_ADMITTED_TIME_8822B(x)                                          \
+	(((x) & BIT_MASK_BE_ADMITTED_TIME_8822B)                               \
+	 << BIT_SHIFT_BE_ADMITTED_TIME_8822B)
+#define BITS_BE_ADMITTED_TIME_8822B                                            \
+	(BIT_MASK_BE_ADMITTED_TIME_8822B << BIT_SHIFT_BE_ADMITTED_TIME_8822B)
+#define BIT_CLEAR_BE_ADMITTED_TIME_8822B(x)                                    \
+	((x) & (~BITS_BE_ADMITTED_TIME_8822B))
+#define BIT_GET_BE_ADMITTED_TIME_8822B(x)                                      \
+	(((x) >> BIT_SHIFT_BE_ADMITTED_TIME_8822B) &                           \
+	 BIT_MASK_BE_ADMITTED_TIME_8822B)
+#define BIT_SET_BE_ADMITTED_TIME_8822B(x, v)                                   \
+	(BIT_CLEAR_BE_ADMITTED_TIME_8822B(x) | BIT_BE_ADMITTED_TIME_8822B(v))
+
+/* 2 REG_EDCA_RANDOM_GEN_8822B */
+
+#define BIT_SHIFT_RANDOM_GEN_8822B 0
+#define BIT_MASK_RANDOM_GEN_8822B 0xffffff
+#define BIT_RANDOM_GEN_8822B(x)                                                \
+	(((x) & BIT_MASK_RANDOM_GEN_8822B) << BIT_SHIFT_RANDOM_GEN_8822B)
+#define BITS_RANDOM_GEN_8822B                                                  \
+	(BIT_MASK_RANDOM_GEN_8822B << BIT_SHIFT_RANDOM_GEN_8822B)
+#define BIT_CLEAR_RANDOM_GEN_8822B(x) ((x) & (~BITS_RANDOM_GEN_8822B))
+#define BIT_GET_RANDOM_GEN_8822B(x)                                            \
+	(((x) >> BIT_SHIFT_RANDOM_GEN_8822B) & BIT_MASK_RANDOM_GEN_8822B)
+#define BIT_SET_RANDOM_GEN_8822B(x, v)                                         \
+	(BIT_CLEAR_RANDOM_GEN_8822B(x) | BIT_RANDOM_GEN_8822B(v))
+
+/* 2 REG_TXCMD_NOA_SEL_8822B */
+
+#define BIT_SHIFT_NOA_SEL_V2_8822B 4
+#define BIT_MASK_NOA_SEL_V2_8822B 0x7
+#define BIT_NOA_SEL_V2_8822B(x)                                                \
+	(((x) & BIT_MASK_NOA_SEL_V2_8822B) << BIT_SHIFT_NOA_SEL_V2_8822B)
+#define BITS_NOA_SEL_V2_8822B                                                  \
+	(BIT_MASK_NOA_SEL_V2_8822B << BIT_SHIFT_NOA_SEL_V2_8822B)
+#define BIT_CLEAR_NOA_SEL_V2_8822B(x) ((x) & (~BITS_NOA_SEL_V2_8822B))
+#define BIT_GET_NOA_SEL_V2_8822B(x)                                            \
+	(((x) >> BIT_SHIFT_NOA_SEL_V2_8822B) & BIT_MASK_NOA_SEL_V2_8822B)
+#define BIT_SET_NOA_SEL_V2_8822B(x, v)                                         \
+	(BIT_CLEAR_NOA_SEL_V2_8822B(x) | BIT_NOA_SEL_V2_8822B(v))
+
+#define BIT_SHIFT_TXCMD_SEG_SEL_8822B 0
+#define BIT_MASK_TXCMD_SEG_SEL_8822B 0xf
+#define BIT_TXCMD_SEG_SEL_8822B(x)                                             \
+	(((x) & BIT_MASK_TXCMD_SEG_SEL_8822B) << BIT_SHIFT_TXCMD_SEG_SEL_8822B)
+#define BITS_TXCMD_SEG_SEL_8822B                                               \
+	(BIT_MASK_TXCMD_SEG_SEL_8822B << BIT_SHIFT_TXCMD_SEG_SEL_8822B)
+#define BIT_CLEAR_TXCMD_SEG_SEL_8822B(x) ((x) & (~BITS_TXCMD_SEG_SEL_8822B))
+#define BIT_GET_TXCMD_SEG_SEL_8822B(x)                                         \
+	(((x) >> BIT_SHIFT_TXCMD_SEG_SEL_8822B) & BIT_MASK_TXCMD_SEG_SEL_8822B)
+#define BIT_SET_TXCMD_SEG_SEL_8822B(x, v)                                      \
+	(BIT_CLEAR_TXCMD_SEG_SEL_8822B(x) | BIT_TXCMD_SEG_SEL_8822B(v))
+
+/* 2 REG_NOA_PARAM_8822B */
+
+#define BIT_SHIFT_NOA_COUNT_8822B (96 & CPU_OPT_WIDTH)
+#define BIT_MASK_NOA_COUNT_8822B 0xff
+#define BIT_NOA_COUNT_8822B(x)                                                 \
+	(((x) & BIT_MASK_NOA_COUNT_8822B) << BIT_SHIFT_NOA_COUNT_8822B)
+#define BITS_NOA_COUNT_8822B                                                   \
+	(BIT_MASK_NOA_COUNT_8822B << BIT_SHIFT_NOA_COUNT_8822B)
+#define BIT_CLEAR_NOA_COUNT_8822B(x) ((x) & (~BITS_NOA_COUNT_8822B))
+#define BIT_GET_NOA_COUNT_8822B(x)                                             \
+	(((x) >> BIT_SHIFT_NOA_COUNT_8822B) & BIT_MASK_NOA_COUNT_8822B)
+#define BIT_SET_NOA_COUNT_8822B(x, v)                                          \
+	(BIT_CLEAR_NOA_COUNT_8822B(x) | BIT_NOA_COUNT_8822B(v))
+
+#define BIT_SHIFT_NOA_START_TIME_8822B (64 & CPU_OPT_WIDTH)
+#define BIT_MASK_NOA_START_TIME_8822B 0xffffffffL
+#define BIT_NOA_START_TIME_8822B(x)                                            \
+	(((x) & BIT_MASK_NOA_START_TIME_8822B)                                 \
+	 << BIT_SHIFT_NOA_START_TIME_8822B)
+#define BITS_NOA_START_TIME_8822B                                              \
+	(BIT_MASK_NOA_START_TIME_8822B << BIT_SHIFT_NOA_START_TIME_8822B)
+#define BIT_CLEAR_NOA_START_TIME_8822B(x) ((x) & (~BITS_NOA_START_TIME_8822B))
+#define BIT_GET_NOA_START_TIME_8822B(x)                                        \
+	(((x) >> BIT_SHIFT_NOA_START_TIME_8822B) &                             \
+	 BIT_MASK_NOA_START_TIME_8822B)
+#define BIT_SET_NOA_START_TIME_8822B(x, v)                                     \
+	(BIT_CLEAR_NOA_START_TIME_8822B(x) | BIT_NOA_START_TIME_8822B(v))
+
+#define BIT_SHIFT_NOA_INTERVAL_8822B (32 & CPU_OPT_WIDTH)
+#define BIT_MASK_NOA_INTERVAL_8822B 0xffffffffL
+#define BIT_NOA_INTERVAL_8822B(x)                                              \
+	(((x) & BIT_MASK_NOA_INTERVAL_8822B) << BIT_SHIFT_NOA_INTERVAL_8822B)
+#define BITS_NOA_INTERVAL_8822B                                                \
+	(BIT_MASK_NOA_INTERVAL_8822B << BIT_SHIFT_NOA_INTERVAL_8822B)
+#define BIT_CLEAR_NOA_INTERVAL_8822B(x) ((x) & (~BITS_NOA_INTERVAL_8822B))
+#define BIT_GET_NOA_INTERVAL_8822B(x)                                          \
+	(((x) >> BIT_SHIFT_NOA_INTERVAL_8822B) & BIT_MASK_NOA_INTERVAL_8822B)
+#define BIT_SET_NOA_INTERVAL_8822B(x, v)                                       \
+	(BIT_CLEAR_NOA_INTERVAL_8822B(x) | BIT_NOA_INTERVAL_8822B(v))
+
+#define BIT_SHIFT_NOA_DURATION_8822B 0
+#define BIT_MASK_NOA_DURATION_8822B 0xffffffffL
+#define BIT_NOA_DURATION_8822B(x)                                              \
+	(((x) & BIT_MASK_NOA_DURATION_8822B) << BIT_SHIFT_NOA_DURATION_8822B)
+#define BITS_NOA_DURATION_8822B                                                \
+	(BIT_MASK_NOA_DURATION_8822B << BIT_SHIFT_NOA_DURATION_8822B)
+#define BIT_CLEAR_NOA_DURATION_8822B(x) ((x) & (~BITS_NOA_DURATION_8822B))
+#define BIT_GET_NOA_DURATION_8822B(x)                                          \
+	(((x) >> BIT_SHIFT_NOA_DURATION_8822B) & BIT_MASK_NOA_DURATION_8822B)
+#define BIT_SET_NOA_DURATION_8822B(x, v)                                       \
+	(BIT_CLEAR_NOA_DURATION_8822B(x) | BIT_NOA_DURATION_8822B(v))
+
+/* 2 REG_P2P_RST_8822B */
+#define BIT_P2P2_PWR_RST1_8822B BIT(5)
+#define BIT_P2P2_PWR_RST0_8822B BIT(4)
+#define BIT_P2P1_PWR_RST1_8822B BIT(3)
+#define BIT_P2P1_PWR_RST0_8822B BIT(2)
+#define BIT_P2P_PWR_RST1_V1_8822B BIT(1)
+#define BIT_P2P_PWR_RST0_V1_8822B BIT(0)
+
+/* 2 REG_SCHEDULER_RST_8822B */
+#define BIT_SYNC_CLI_ONCE_RIGHT_NOW_8822B BIT(2)
+#define BIT_SYNC_CLI_ONCE_BY_TBTT_8822B BIT(1)
+#define BIT_SCHEDULER_RST_V1_8822B BIT(0)
+
+/* 2 REG_SCH_TXCMD_8822B */
+
+#define BIT_SHIFT_SCH_TXCMD_8822B 0
+#define BIT_MASK_SCH_TXCMD_8822B 0xffffffffL
+#define BIT_SCH_TXCMD_8822B(x)                                                 \
+	(((x) & BIT_MASK_SCH_TXCMD_8822B) << BIT_SHIFT_SCH_TXCMD_8822B)
+#define BITS_SCH_TXCMD_8822B                                                   \
+	(BIT_MASK_SCH_TXCMD_8822B << BIT_SHIFT_SCH_TXCMD_8822B)
+#define BIT_CLEAR_SCH_TXCMD_8822B(x) ((x) & (~BITS_SCH_TXCMD_8822B))
+#define BIT_GET_SCH_TXCMD_8822B(x)                                             \
+	(((x) >> BIT_SHIFT_SCH_TXCMD_8822B) & BIT_MASK_SCH_TXCMD_8822B)
+#define BIT_SET_SCH_TXCMD_8822B(x, v)                                          \
+	(BIT_CLEAR_SCH_TXCMD_8822B(x) | BIT_SCH_TXCMD_8822B(v))
+
+/* 2 REG_PAGE5_DUMMY_8822B */
+
+/* 2 REG_CPUMGQ_TX_TIMER_8822B */
+
+#define BIT_SHIFT_CPUMGQ_TX_TIMER_V1_8822B 0
+#define BIT_MASK_CPUMGQ_TX_TIMER_V1_8822B 0xffffffffL
+#define BIT_CPUMGQ_TX_TIMER_V1_8822B(x)                                        \
+	(((x) & BIT_MASK_CPUMGQ_TX_TIMER_V1_8822B)                             \
+	 << BIT_SHIFT_CPUMGQ_TX_TIMER_V1_8822B)
+#define BITS_CPUMGQ_TX_TIMER_V1_8822B                                          \
+	(BIT_MASK_CPUMGQ_TX_TIMER_V1_8822B                                     \
+	 << BIT_SHIFT_CPUMGQ_TX_TIMER_V1_8822B)
+#define BIT_CLEAR_CPUMGQ_TX_TIMER_V1_8822B(x)                                  \
+	((x) & (~BITS_CPUMGQ_TX_TIMER_V1_8822B))
+#define BIT_GET_CPUMGQ_TX_TIMER_V1_8822B(x)                                    \
+	(((x) >> BIT_SHIFT_CPUMGQ_TX_TIMER_V1_8822B) &                         \
+	 BIT_MASK_CPUMGQ_TX_TIMER_V1_8822B)
+#define BIT_SET_CPUMGQ_TX_TIMER_V1_8822B(x, v)                                 \
+	(BIT_CLEAR_CPUMGQ_TX_TIMER_V1_8822B(x) |                               \
+	 BIT_CPUMGQ_TX_TIMER_V1_8822B(v))
+
+/* 2 REG_PS_TIMER_A_8822B */
+
+#define BIT_SHIFT_PS_TIMER_A_V1_8822B 0
+#define BIT_MASK_PS_TIMER_A_V1_8822B 0xffffffffL
+#define BIT_PS_TIMER_A_V1_8822B(x)                                             \
+	(((x) & BIT_MASK_PS_TIMER_A_V1_8822B) << BIT_SHIFT_PS_TIMER_A_V1_8822B)
+#define BITS_PS_TIMER_A_V1_8822B                                               \
+	(BIT_MASK_PS_TIMER_A_V1_8822B << BIT_SHIFT_PS_TIMER_A_V1_8822B)
+#define BIT_CLEAR_PS_TIMER_A_V1_8822B(x) ((x) & (~BITS_PS_TIMER_A_V1_8822B))
+#define BIT_GET_PS_TIMER_A_V1_8822B(x)                                         \
+	(((x) >> BIT_SHIFT_PS_TIMER_A_V1_8822B) & BIT_MASK_PS_TIMER_A_V1_8822B)
+#define BIT_SET_PS_TIMER_A_V1_8822B(x, v)                                      \
+	(BIT_CLEAR_PS_TIMER_A_V1_8822B(x) | BIT_PS_TIMER_A_V1_8822B(v))
+
+/* 2 REG_PS_TIMER_B_8822B */
+
+#define BIT_SHIFT_PS_TIMER_B_V1_8822B 0
+#define BIT_MASK_PS_TIMER_B_V1_8822B 0xffffffffL
+#define BIT_PS_TIMER_B_V1_8822B(x)                                             \
+	(((x) & BIT_MASK_PS_TIMER_B_V1_8822B) << BIT_SHIFT_PS_TIMER_B_V1_8822B)
+#define BITS_PS_TIMER_B_V1_8822B                                               \
+	(BIT_MASK_PS_TIMER_B_V1_8822B << BIT_SHIFT_PS_TIMER_B_V1_8822B)
+#define BIT_CLEAR_PS_TIMER_B_V1_8822B(x) ((x) & (~BITS_PS_TIMER_B_V1_8822B))
+#define BIT_GET_PS_TIMER_B_V1_8822B(x)                                         \
+	(((x) >> BIT_SHIFT_PS_TIMER_B_V1_8822B) & BIT_MASK_PS_TIMER_B_V1_8822B)
+#define BIT_SET_PS_TIMER_B_V1_8822B(x, v)                                      \
+	(BIT_CLEAR_PS_TIMER_B_V1_8822B(x) | BIT_PS_TIMER_B_V1_8822B(v))
+
+/* 2 REG_PS_TIMER_C_8822B */
+
+#define BIT_SHIFT_PS_TIMER_C_V1_8822B 0
+#define BIT_MASK_PS_TIMER_C_V1_8822B 0xffffffffL
+#define BIT_PS_TIMER_C_V1_8822B(x)                                             \
+	(((x) & BIT_MASK_PS_TIMER_C_V1_8822B) << BIT_SHIFT_PS_TIMER_C_V1_8822B)
+#define BITS_PS_TIMER_C_V1_8822B                                               \
+	(BIT_MASK_PS_TIMER_C_V1_8822B << BIT_SHIFT_PS_TIMER_C_V1_8822B)
+#define BIT_CLEAR_PS_TIMER_C_V1_8822B(x) ((x) & (~BITS_PS_TIMER_C_V1_8822B))
+#define BIT_GET_PS_TIMER_C_V1_8822B(x)                                         \
+	(((x) >> BIT_SHIFT_PS_TIMER_C_V1_8822B) & BIT_MASK_PS_TIMER_C_V1_8822B)
+#define BIT_SET_PS_TIMER_C_V1_8822B(x, v)                                      \
+	(BIT_CLEAR_PS_TIMER_C_V1_8822B(x) | BIT_PS_TIMER_C_V1_8822B(v))
+
+/* 2 REG_PS_TIMER_ABC_CPUMGQ_TIMER_CRTL_8822B */
+#define BIT_CPUMGQ_TIMER_EN_8822B BIT(31)
+#define BIT_CPUMGQ_TX_EN_8822B BIT(28)
+
+#define BIT_SHIFT_CPUMGQ_TIMER_TSF_SEL_8822B 24
+#define BIT_MASK_CPUMGQ_TIMER_TSF_SEL_8822B 0x7
+#define BIT_CPUMGQ_TIMER_TSF_SEL_8822B(x)                                      \
+	(((x) & BIT_MASK_CPUMGQ_TIMER_TSF_SEL_8822B)                           \
+	 << BIT_SHIFT_CPUMGQ_TIMER_TSF_SEL_8822B)
+#define BITS_CPUMGQ_TIMER_TSF_SEL_8822B                                        \
+	(BIT_MASK_CPUMGQ_TIMER_TSF_SEL_8822B                                   \
+	 << BIT_SHIFT_CPUMGQ_TIMER_TSF_SEL_8822B)
+#define BIT_CLEAR_CPUMGQ_TIMER_TSF_SEL_8822B(x)                                \
+	((x) & (~BITS_CPUMGQ_TIMER_TSF_SEL_8822B))
+#define BIT_GET_CPUMGQ_TIMER_TSF_SEL_8822B(x)                                  \
+	(((x) >> BIT_SHIFT_CPUMGQ_TIMER_TSF_SEL_8822B) &                       \
+	 BIT_MASK_CPUMGQ_TIMER_TSF_SEL_8822B)
+#define BIT_SET_CPUMGQ_TIMER_TSF_SEL_8822B(x, v)                               \
+	(BIT_CLEAR_CPUMGQ_TIMER_TSF_SEL_8822B(x) |                             \
+	 BIT_CPUMGQ_TIMER_TSF_SEL_8822B(v))
+
+#define BIT_PS_TIMER_C_EN_8822B BIT(23)
+
+#define BIT_SHIFT_PS_TIMER_C_TSF_SEL_8822B 16
+#define BIT_MASK_PS_TIMER_C_TSF_SEL_8822B 0x7
+#define BIT_PS_TIMER_C_TSF_SEL_8822B(x)                                        \
+	(((x) & BIT_MASK_PS_TIMER_C_TSF_SEL_8822B)                             \
+	 << BIT_SHIFT_PS_TIMER_C_TSF_SEL_8822B)
+#define BITS_PS_TIMER_C_TSF_SEL_8822B                                          \
+	(BIT_MASK_PS_TIMER_C_TSF_SEL_8822B                                     \
+	 << BIT_SHIFT_PS_TIMER_C_TSF_SEL_8822B)
+#define BIT_CLEAR_PS_TIMER_C_TSF_SEL_8822B(x)                                  \
+	((x) & (~BITS_PS_TIMER_C_TSF_SEL_8822B))
+#define BIT_GET_PS_TIMER_C_TSF_SEL_8822B(x)                                    \
+	(((x) >> BIT_SHIFT_PS_TIMER_C_TSF_SEL_8822B) &                         \
+	 BIT_MASK_PS_TIMER_C_TSF_SEL_8822B)
+#define BIT_SET_PS_TIMER_C_TSF_SEL_8822B(x, v)                                 \
+	(BIT_CLEAR_PS_TIMER_C_TSF_SEL_8822B(x) |                               \
+	 BIT_PS_TIMER_C_TSF_SEL_8822B(v))
+
+#define BIT_PS_TIMER_B_EN_8822B BIT(15)
+
+#define BIT_SHIFT_PS_TIMER_B_TSF_SEL_8822B 8
+#define BIT_MASK_PS_TIMER_B_TSF_SEL_8822B 0x7
+#define BIT_PS_TIMER_B_TSF_SEL_8822B(x)                                        \
+	(((x) & BIT_MASK_PS_TIMER_B_TSF_SEL_8822B)                             \
+	 << BIT_SHIFT_PS_TIMER_B_TSF_SEL_8822B)
+#define BITS_PS_TIMER_B_TSF_SEL_8822B                                          \
+	(BIT_MASK_PS_TIMER_B_TSF_SEL_8822B                                     \
+	 << BIT_SHIFT_PS_TIMER_B_TSF_SEL_8822B)
+#define BIT_CLEAR_PS_TIMER_B_TSF_SEL_8822B(x)                                  \
+	((x) & (~BITS_PS_TIMER_B_TSF_SEL_8822B))
+#define BIT_GET_PS_TIMER_B_TSF_SEL_8822B(x)                                    \
+	(((x) >> BIT_SHIFT_PS_TIMER_B_TSF_SEL_8822B) &                         \
+	 BIT_MASK_PS_TIMER_B_TSF_SEL_8822B)
+#define BIT_SET_PS_TIMER_B_TSF_SEL_8822B(x, v)                                 \
+	(BIT_CLEAR_PS_TIMER_B_TSF_SEL_8822B(x) |                               \
+	 BIT_PS_TIMER_B_TSF_SEL_8822B(v))
+
+#define BIT_PS_TIMER_A_EN_8822B BIT(7)
+
+#define BIT_SHIFT_PS_TIMER_A_TSF_SEL_8822B 0
+#define BIT_MASK_PS_TIMER_A_TSF_SEL_8822B 0x7
+#define BIT_PS_TIMER_A_TSF_SEL_8822B(x)                                        \
+	(((x) & BIT_MASK_PS_TIMER_A_TSF_SEL_8822B)                             \
+	 << BIT_SHIFT_PS_TIMER_A_TSF_SEL_8822B)
+#define BITS_PS_TIMER_A_TSF_SEL_8822B                                          \
+	(BIT_MASK_PS_TIMER_A_TSF_SEL_8822B                                     \
+	 << BIT_SHIFT_PS_TIMER_A_TSF_SEL_8822B)
+#define BIT_CLEAR_PS_TIMER_A_TSF_SEL_8822B(x)                                  \
+	((x) & (~BITS_PS_TIMER_A_TSF_SEL_8822B))
+#define BIT_GET_PS_TIMER_A_TSF_SEL_8822B(x)                                    \
+	(((x) >> BIT_SHIFT_PS_TIMER_A_TSF_SEL_8822B) &                         \
+	 BIT_MASK_PS_TIMER_A_TSF_SEL_8822B)
+#define BIT_SET_PS_TIMER_A_TSF_SEL_8822B(x, v)                                 \
+	(BIT_CLEAR_PS_TIMER_A_TSF_SEL_8822B(x) |                               \
+	 BIT_PS_TIMER_A_TSF_SEL_8822B(v))
+
+/* 2 REG_CPUMGQ_TX_TIMER_EARLY_8822B */
+
+#define BIT_SHIFT_CPUMGQ_TX_TIMER_EARLY_8822B 0
+#define BIT_MASK_CPUMGQ_TX_TIMER_EARLY_8822B 0xff
+#define BIT_CPUMGQ_TX_TIMER_EARLY_8822B(x)                                     \
+	(((x) & BIT_MASK_CPUMGQ_TX_TIMER_EARLY_8822B)                          \
+	 << BIT_SHIFT_CPUMGQ_TX_TIMER_EARLY_8822B)
+#define BITS_CPUMGQ_TX_TIMER_EARLY_8822B                                       \
+	(BIT_MASK_CPUMGQ_TX_TIMER_EARLY_8822B                                  \
+	 << BIT_SHIFT_CPUMGQ_TX_TIMER_EARLY_8822B)
+#define BIT_CLEAR_CPUMGQ_TX_TIMER_EARLY_8822B(x)                               \
+	((x) & (~BITS_CPUMGQ_TX_TIMER_EARLY_8822B))
+#define BIT_GET_CPUMGQ_TX_TIMER_EARLY_8822B(x)                                 \
+	(((x) >> BIT_SHIFT_CPUMGQ_TX_TIMER_EARLY_8822B) &                      \
+	 BIT_MASK_CPUMGQ_TX_TIMER_EARLY_8822B)
+#define BIT_SET_CPUMGQ_TX_TIMER_EARLY_8822B(x, v)                              \
+	(BIT_CLEAR_CPUMGQ_TX_TIMER_EARLY_8822B(x) |                            \
+	 BIT_CPUMGQ_TX_TIMER_EARLY_8822B(v))
+
+/* 2 REG_PS_TIMER_A_EARLY_8822B */
+
+#define BIT_SHIFT_PS_TIMER_A_EARLY_8822B 0
+#define BIT_MASK_PS_TIMER_A_EARLY_8822B 0xff
+#define BIT_PS_TIMER_A_EARLY_8822B(x)                                          \
+	(((x) & BIT_MASK_PS_TIMER_A_EARLY_8822B)                               \
+	 << BIT_SHIFT_PS_TIMER_A_EARLY_8822B)
+#define BITS_PS_TIMER_A_EARLY_8822B                                            \
+	(BIT_MASK_PS_TIMER_A_EARLY_8822B << BIT_SHIFT_PS_TIMER_A_EARLY_8822B)
+#define BIT_CLEAR_PS_TIMER_A_EARLY_8822B(x)                                    \
+	((x) & (~BITS_PS_TIMER_A_EARLY_8822B))
+#define BIT_GET_PS_TIMER_A_EARLY_8822B(x)                                      \
+	(((x) >> BIT_SHIFT_PS_TIMER_A_EARLY_8822B) &                           \
+	 BIT_MASK_PS_TIMER_A_EARLY_8822B)
+#define BIT_SET_PS_TIMER_A_EARLY_8822B(x, v)                                   \
+	(BIT_CLEAR_PS_TIMER_A_EARLY_8822B(x) | BIT_PS_TIMER_A_EARLY_8822B(v))
+
+/* 2 REG_PS_TIMER_B_EARLY_8822B */
+
+#define BIT_SHIFT_PS_TIMER_B_EARLY_8822B 0
+#define BIT_MASK_PS_TIMER_B_EARLY_8822B 0xff
+#define BIT_PS_TIMER_B_EARLY_8822B(x)                                          \
+	(((x) & BIT_MASK_PS_TIMER_B_EARLY_8822B)                               \
+	 << BIT_SHIFT_PS_TIMER_B_EARLY_8822B)
+#define BITS_PS_TIMER_B_EARLY_8822B                                            \
+	(BIT_MASK_PS_TIMER_B_EARLY_8822B << BIT_SHIFT_PS_TIMER_B_EARLY_8822B)
+#define BIT_CLEAR_PS_TIMER_B_EARLY_8822B(x)                                    \
+	((x) & (~BITS_PS_TIMER_B_EARLY_8822B))
+#define BIT_GET_PS_TIMER_B_EARLY_8822B(x)                                      \
+	(((x) >> BIT_SHIFT_PS_TIMER_B_EARLY_8822B) &                           \
+	 BIT_MASK_PS_TIMER_B_EARLY_8822B)
+#define BIT_SET_PS_TIMER_B_EARLY_8822B(x, v)                                   \
+	(BIT_CLEAR_PS_TIMER_B_EARLY_8822B(x) | BIT_PS_TIMER_B_EARLY_8822B(v))
+
+/* 2 REG_PS_TIMER_C_EARLY_8822B */
+
+#define BIT_SHIFT_PS_TIMER_C_EARLY_8822B 0
+#define BIT_MASK_PS_TIMER_C_EARLY_8822B 0xff
+#define BIT_PS_TIMER_C_EARLY_8822B(x)                                          \
+	(((x) & BIT_MASK_PS_TIMER_C_EARLY_8822B)                               \
+	 << BIT_SHIFT_PS_TIMER_C_EARLY_8822B)
+#define BITS_PS_TIMER_C_EARLY_8822B                                            \
+	(BIT_MASK_PS_TIMER_C_EARLY_8822B << BIT_SHIFT_PS_TIMER_C_EARLY_8822B)
+#define BIT_CLEAR_PS_TIMER_C_EARLY_8822B(x)                                    \
+	((x) & (~BITS_PS_TIMER_C_EARLY_8822B))
+#define BIT_GET_PS_TIMER_C_EARLY_8822B(x)                                      \
+	(((x) >> BIT_SHIFT_PS_TIMER_C_EARLY_8822B) &                           \
+	 BIT_MASK_PS_TIMER_C_EARLY_8822B)
+#define BIT_SET_PS_TIMER_C_EARLY_8822B(x, v)                                   \
+	(BIT_CLEAR_PS_TIMER_C_EARLY_8822B(x) | BIT_PS_TIMER_C_EARLY_8822B(v))
+
+/* 2 REG_CPUMGQ_PARAMETER_8822B */
+
+/* 2 REG_NOT_VALID_8822B */
+#define BIT_MAC_STOP_CPUMGQ_8822B BIT(16)
+
+#define BIT_SHIFT_CW_8822B 8
+#define BIT_MASK_CW_8822B 0xff
+#define BIT_CW_8822B(x) (((x) & BIT_MASK_CW_8822B) << BIT_SHIFT_CW_8822B)
+#define BITS_CW_8822B (BIT_MASK_CW_8822B << BIT_SHIFT_CW_8822B)
+#define BIT_CLEAR_CW_8822B(x) ((x) & (~BITS_CW_8822B))
+#define BIT_GET_CW_8822B(x) (((x) >> BIT_SHIFT_CW_8822B) & BIT_MASK_CW_8822B)
+#define BIT_SET_CW_8822B(x, v) (BIT_CLEAR_CW_8822B(x) | BIT_CW_8822B(v))
+
+#define BIT_SHIFT_AIFS_8822B 0
+#define BIT_MASK_AIFS_8822B 0xff
+#define BIT_AIFS_8822B(x) (((x) & BIT_MASK_AIFS_8822B) << BIT_SHIFT_AIFS_8822B)
+#define BITS_AIFS_8822B (BIT_MASK_AIFS_8822B << BIT_SHIFT_AIFS_8822B)
+#define BIT_CLEAR_AIFS_8822B(x) ((x) & (~BITS_AIFS_8822B))
+#define BIT_GET_AIFS_8822B(x)                                                  \
+	(((x) >> BIT_SHIFT_AIFS_8822B) & BIT_MASK_AIFS_8822B)
+#define BIT_SET_AIFS_8822B(x, v) (BIT_CLEAR_AIFS_8822B(x) | BIT_AIFS_8822B(v))
+
+/* 2 REG_NOT_VALID_8822B */
+
+/* 2 REG_BWOPMODE_8822B (BW OPERATION MODE REGISTER) */
+
+/* 2 REG_WMAC_FWPKT_CR_8822B */
+#define BIT_FWEN_8822B BIT(7)
+#define BIT_PHYSTS_PKT_CTRL_8822B BIT(6)
+#define BIT_APPHDR_MIDSRCH_FAIL_8822B BIT(4)
+#define BIT_FWPARSING_EN_8822B BIT(3)
+
+#define BIT_SHIFT_APPEND_MHDR_LEN_8822B 0
+#define BIT_MASK_APPEND_MHDR_LEN_8822B 0x7
+#define BIT_APPEND_MHDR_LEN_8822B(x)                                           \
+	(((x) & BIT_MASK_APPEND_MHDR_LEN_8822B)                                \
+	 << BIT_SHIFT_APPEND_MHDR_LEN_8822B)
+#define BITS_APPEND_MHDR_LEN_8822B                                             \
+	(BIT_MASK_APPEND_MHDR_LEN_8822B << BIT_SHIFT_APPEND_MHDR_LEN_8822B)
+#define BIT_CLEAR_APPEND_MHDR_LEN_8822B(x) ((x) & (~BITS_APPEND_MHDR_LEN_8822B))
+#define BIT_GET_APPEND_MHDR_LEN_8822B(x)                                       \
+	(((x) >> BIT_SHIFT_APPEND_MHDR_LEN_8822B) &                            \
+	 BIT_MASK_APPEND_MHDR_LEN_8822B)
+#define BIT_SET_APPEND_MHDR_LEN_8822B(x, v)                                    \
+	(BIT_CLEAR_APPEND_MHDR_LEN_8822B(x) | BIT_APPEND_MHDR_LEN_8822B(v))
+
+/* 2 REG_WMAC_CR_8822B (WMAC CR AND APSD CONTROL REGISTER) */
+#define BIT_IC_MACPHY_M_8822B BIT(0)
+
+/* 2 REG_TCR_8822B (TRANSMISSION CONFIGURATION REGISTER) */
+#define BIT_WMAC_EN_RTS_ADDR_8822B BIT(31)
+#define BIT_WMAC_DISABLE_CCK_8822B BIT(30)
+#define BIT_WMAC_RAW_LEN_8822B BIT(29)
+#define BIT_WMAC_NOTX_IN_RXNDP_8822B BIT(28)
+#define BIT_WMAC_EN_EOF_8822B BIT(27)
+#define BIT_WMAC_BF_SEL_8822B BIT(26)
+#define BIT_WMAC_ANTMODE_SEL_8822B BIT(25)
+#define BIT_WMAC_TCRPWRMGT_HWCTL_8822B BIT(24)
+#define BIT_WMAC_SMOOTH_VAL_8822B BIT(23)
+#define BIT_FETCH_MPDU_AFTER_WSEC_RDY_8822B BIT(20)
+#define BIT_WMAC_TCR_EN_20MST_8822B BIT(19)
+#define BIT_WMAC_DIS_SIGTA_8822B BIT(18)
+#define BIT_WMAC_DIS_A2B0_8822B BIT(17)
+#define BIT_WMAC_MSK_SIGBCRC_8822B BIT(16)
+#define BIT_WMAC_TCR_ERRSTEN_3_8822B BIT(15)
+#define BIT_WMAC_TCR_ERRSTEN_2_8822B BIT(14)
+#define BIT_WMAC_TCR_ERRSTEN_1_8822B BIT(13)
+#define BIT_WMAC_TCR_ERRSTEN_0_8822B BIT(12)
+#define BIT_WMAC_TCR_TXSK_PERPKT_8822B BIT(11)
+#define BIT_ICV_8822B BIT(10)
+#define BIT_CFEND_FORMAT_8822B BIT(9)
+#define BIT_CRC_8822B BIT(8)
+#define BIT_PWRBIT_OW_EN_8822B BIT(7)
+#define BIT_PWR_ST_8822B BIT(6)
+#define BIT_WMAC_TCR_UPD_TIMIE_8822B BIT(5)
+#define BIT_WMAC_TCR_UPD_HGQMD_8822B BIT(4)
+#define BIT_VHTSIGA1_TXPS_8822B BIT(3)
+#define BIT_PAD_SEL_8822B BIT(2)
+#define BIT_DIS_GCLK_8822B BIT(1)
+
+/* 2 REG_RCR_8822B (RECEIVE CONFIGURATION REGISTER) */
+#define BIT_APP_FCS_8822B BIT(31)
+#define BIT_APP_MIC_8822B BIT(30)
+#define BIT_APP_ICV_8822B BIT(29)
+#define BIT_APP_PHYSTS_8822B BIT(28)
+#define BIT_APP_BASSN_8822B BIT(27)
+#define BIT_VHT_DACK_8822B BIT(26)
+#define BIT_TCPOFLD_EN_8822B BIT(25)
+#define BIT_ENMBID_8822B BIT(24)
+#define BIT_LSIGEN_8822B BIT(23)
+#define BIT_MFBEN_8822B BIT(22)
+#define BIT_DISCHKPPDLLEN_8822B BIT(21)
+#define BIT_PKTCTL_DLEN_8822B BIT(20)
+#define BIT_TIM_PARSER_EN_8822B BIT(18)
+#define BIT_BC_MD_EN_8822B BIT(17)
+#define BIT_UC_MD_EN_8822B BIT(16)
+#define BIT_RXSK_PERPKT_8822B BIT(15)
+#define BIT_HTC_LOC_CTRL_8822B BIT(14)
+#define BIT_RPFM_CAM_ENABLE_8822B BIT(12)
+#define BIT_TA_BCN_8822B BIT(11)
+#define BIT_DISDECMYPKT_8822B BIT(10)
+#define BIT_AICV_8822B BIT(9)
+#define BIT_ACRC32_8822B BIT(8)
+#define BIT_CBSSID_BCN_8822B BIT(7)
+#define BIT_CBSSID_DATA_8822B BIT(6)
+#define BIT_APWRMGT_8822B BIT(5)
+#define BIT_ADD3_8822B BIT(4)
+#define BIT_AB_8822B BIT(3)
+#define BIT_AM_8822B BIT(2)
+#define BIT_APM_8822B BIT(1)
+#define BIT_AAP_8822B BIT(0)
+
+/* 2 REG_RX_DRVINFO_SZ_8822B (RX DRIVER INFO SIZE REGISTER) */
+#define BIT_PHYSTS_PER_PKT_MODE_8822B BIT(7)
+
+#define BIT_SHIFT_DRVINFO_SZ_V1_8822B 0
+#define BIT_MASK_DRVINFO_SZ_V1_8822B 0xf
+#define BIT_DRVINFO_SZ_V1_8822B(x)                                             \
+	(((x) & BIT_MASK_DRVINFO_SZ_V1_8822B) << BIT_SHIFT_DRVINFO_SZ_V1_8822B)
+#define BITS_DRVINFO_SZ_V1_8822B                                               \
+	(BIT_MASK_DRVINFO_SZ_V1_8822B << BIT_SHIFT_DRVINFO_SZ_V1_8822B)
+#define BIT_CLEAR_DRVINFO_SZ_V1_8822B(x) ((x) & (~BITS_DRVINFO_SZ_V1_8822B))
+#define BIT_GET_DRVINFO_SZ_V1_8822B(x)                                         \
+	(((x) >> BIT_SHIFT_DRVINFO_SZ_V1_8822B) & BIT_MASK_DRVINFO_SZ_V1_8822B)
+#define BIT_SET_DRVINFO_SZ_V1_8822B(x, v)                                      \
+	(BIT_CLEAR_DRVINFO_SZ_V1_8822B(x) | BIT_DRVINFO_SZ_V1_8822B(v))
+
+/* 2 REG_RX_DLK_TIME_8822B (RX DEADLOCK TIME REGISTER) */
+
+#define BIT_SHIFT_RX_DLK_TIME_8822B 0
+#define BIT_MASK_RX_DLK_TIME_8822B 0xff
+#define BIT_RX_DLK_TIME_8822B(x)                                               \
+	(((x) & BIT_MASK_RX_DLK_TIME_8822B) << BIT_SHIFT_RX_DLK_TIME_8822B)
+#define BITS_RX_DLK_TIME_8822B                                                 \
+	(BIT_MASK_RX_DLK_TIME_8822B << BIT_SHIFT_RX_DLK_TIME_8822B)
+#define BIT_CLEAR_RX_DLK_TIME_8822B(x) ((x) & (~BITS_RX_DLK_TIME_8822B))
+#define BIT_GET_RX_DLK_TIME_8822B(x)                                           \
+	(((x) >> BIT_SHIFT_RX_DLK_TIME_8822B) & BIT_MASK_RX_DLK_TIME_8822B)
+#define BIT_SET_RX_DLK_TIME_8822B(x, v)                                        \
+	(BIT_CLEAR_RX_DLK_TIME_8822B(x) | BIT_RX_DLK_TIME_8822B(v))
+
+/* 2 REG_RX_PKT_LIMIT_8822B (RX PACKET LENGTH LIMIT REGISTER) */
+
+#define BIT_SHIFT_RXPKTLMT_8822B 0
+#define BIT_MASK_RXPKTLMT_8822B 0x3f
+#define BIT_RXPKTLMT_8822B(x)                                                  \
+	(((x) & BIT_MASK_RXPKTLMT_8822B) << BIT_SHIFT_RXPKTLMT_8822B)
+#define BITS_RXPKTLMT_8822B                                                    \
+	(BIT_MASK_RXPKTLMT_8822B << BIT_SHIFT_RXPKTLMT_8822B)
+#define BIT_CLEAR_RXPKTLMT_8822B(x) ((x) & (~BITS_RXPKTLMT_8822B))
+#define BIT_GET_RXPKTLMT_8822B(x)                                              \
+	(((x) >> BIT_SHIFT_RXPKTLMT_8822B) & BIT_MASK_RXPKTLMT_8822B)
+#define BIT_SET_RXPKTLMT_8822B(x, v)                                           \
+	(BIT_CLEAR_RXPKTLMT_8822B(x) | BIT_RXPKTLMT_8822B(v))
+
+/* 2 REG_MACID_8822B (MAC ID REGISTER) */
+
+#define BIT_SHIFT_MACID_8822B 0
+#define BIT_MASK_MACID_8822B 0xffffffffffffL
+#define BIT_MACID_8822B(x)                                                     \
+	(((x) & BIT_MASK_MACID_8822B) << BIT_SHIFT_MACID_8822B)
+#define BITS_MACID_8822B (BIT_MASK_MACID_8822B << BIT_SHIFT_MACID_8822B)
+#define BIT_CLEAR_MACID_8822B(x) ((x) & (~BITS_MACID_8822B))
+#define BIT_GET_MACID_8822B(x)                                                 \
+	(((x) >> BIT_SHIFT_MACID_8822B) & BIT_MASK_MACID_8822B)
+#define BIT_SET_MACID_8822B(x, v)                                              \
+	(BIT_CLEAR_MACID_8822B(x) | BIT_MACID_8822B(v))
+
+/* 2 REG_BSSID_8822B (BSSID REGISTER) */
+
+#define BIT_SHIFT_BSSID_8822B 0
+#define BIT_MASK_BSSID_8822B 0xffffffffffffL
+#define BIT_BSSID_8822B(x)                                                     \
+	(((x) & BIT_MASK_BSSID_8822B) << BIT_SHIFT_BSSID_8822B)
+#define BITS_BSSID_8822B (BIT_MASK_BSSID_8822B << BIT_SHIFT_BSSID_8822B)
+#define BIT_CLEAR_BSSID_8822B(x) ((x) & (~BITS_BSSID_8822B))
+#define BIT_GET_BSSID_8822B(x)                                                 \
+	(((x) >> BIT_SHIFT_BSSID_8822B) & BIT_MASK_BSSID_8822B)
+#define BIT_SET_BSSID_8822B(x, v)                                              \
+	(BIT_CLEAR_BSSID_8822B(x) | BIT_BSSID_8822B(v))
+
+/* 2 REG_MAR_8822B (MULTICAST ADDRESS REGISTER) */
+
+#define BIT_SHIFT_MAR_8822B 0
+#define BIT_MASK_MAR_8822B 0xffffffffffffffffL
+#define BIT_MAR_8822B(x) (((x) & BIT_MASK_MAR_8822B) << BIT_SHIFT_MAR_8822B)
+#define BITS_MAR_8822B (BIT_MASK_MAR_8822B << BIT_SHIFT_MAR_8822B)
+#define BIT_CLEAR_MAR_8822B(x) ((x) & (~BITS_MAR_8822B))
+#define BIT_GET_MAR_8822B(x) (((x) >> BIT_SHIFT_MAR_8822B) & BIT_MASK_MAR_8822B)
+#define BIT_SET_MAR_8822B(x, v) (BIT_CLEAR_MAR_8822B(x) | BIT_MAR_8822B(v))
+
+/* 2 REG_MBIDCAMCFG_1_8822B (MBSSID CAM CONFIGURATION REGISTER) */
+
+#define BIT_SHIFT_MBIDCAM_RWDATA_L_8822B 0
+#define BIT_MASK_MBIDCAM_RWDATA_L_8822B 0xffffffffL
+#define BIT_MBIDCAM_RWDATA_L_8822B(x)                                          \
+	(((x) & BIT_MASK_MBIDCAM_RWDATA_L_8822B)                               \
+	 << BIT_SHIFT_MBIDCAM_RWDATA_L_8822B)
+#define BITS_MBIDCAM_RWDATA_L_8822B                                            \
+	(BIT_MASK_MBIDCAM_RWDATA_L_8822B << BIT_SHIFT_MBIDCAM_RWDATA_L_8822B)
+#define BIT_CLEAR_MBIDCAM_RWDATA_L_8822B(x)                                    \
+	((x) & (~BITS_MBIDCAM_RWDATA_L_8822B))
+#define BIT_GET_MBIDCAM_RWDATA_L_8822B(x)                                      \
+	(((x) >> BIT_SHIFT_MBIDCAM_RWDATA_L_8822B) &                           \
+	 BIT_MASK_MBIDCAM_RWDATA_L_8822B)
+#define BIT_SET_MBIDCAM_RWDATA_L_8822B(x, v)                                   \
+	(BIT_CLEAR_MBIDCAM_RWDATA_L_8822B(x) | BIT_MBIDCAM_RWDATA_L_8822B(v))
+
+/* 2 REG_MBIDCAMCFG_2_8822B (MBSSID CAM CONFIGURATION REGISTER) */
+#define BIT_MBIDCAM_POLL_8822B BIT(31)
+#define BIT_MBIDCAM_WT_EN_8822B BIT(30)
+
+#define BIT_SHIFT_MBIDCAM_ADDR_8822B 24
+#define BIT_MASK_MBIDCAM_ADDR_8822B 0x1f
+#define BIT_MBIDCAM_ADDR_8822B(x)                                              \
+	(((x) & BIT_MASK_MBIDCAM_ADDR_8822B) << BIT_SHIFT_MBIDCAM_ADDR_8822B)
+#define BITS_MBIDCAM_ADDR_8822B                                                \
+	(BIT_MASK_MBIDCAM_ADDR_8822B << BIT_SHIFT_MBIDCAM_ADDR_8822B)
+#define BIT_CLEAR_MBIDCAM_ADDR_8822B(x) ((x) & (~BITS_MBIDCAM_ADDR_8822B))
+#define BIT_GET_MBIDCAM_ADDR_8822B(x)                                          \
+	(((x) >> BIT_SHIFT_MBIDCAM_ADDR_8822B) & BIT_MASK_MBIDCAM_ADDR_8822B)
+#define BIT_SET_MBIDCAM_ADDR_8822B(x, v)                                       \
+	(BIT_CLEAR_MBIDCAM_ADDR_8822B(x) | BIT_MBIDCAM_ADDR_8822B(v))
+
+#define BIT_MBIDCAM_VALID_8822B BIT(23)
+#define BIT_LSIC_TXOP_EN_8822B BIT(17)
+#define BIT_CTS_EN_8822B BIT(16)
+
+#define BIT_SHIFT_MBIDCAM_RWDATA_H_8822B 0
+#define BIT_MASK_MBIDCAM_RWDATA_H_8822B 0xffff
+#define BIT_MBIDCAM_RWDATA_H_8822B(x)                                          \
+	(((x) & BIT_MASK_MBIDCAM_RWDATA_H_8822B)                               \
+	 << BIT_SHIFT_MBIDCAM_RWDATA_H_8822B)
+#define BITS_MBIDCAM_RWDATA_H_8822B                                            \
+	(BIT_MASK_MBIDCAM_RWDATA_H_8822B << BIT_SHIFT_MBIDCAM_RWDATA_H_8822B)
+#define BIT_CLEAR_MBIDCAM_RWDATA_H_8822B(x)                                    \
+	((x) & (~BITS_MBIDCAM_RWDATA_H_8822B))
+#define BIT_GET_MBIDCAM_RWDATA_H_8822B(x)                                      \
+	(((x) >> BIT_SHIFT_MBIDCAM_RWDATA_H_8822B) &                           \
+	 BIT_MASK_MBIDCAM_RWDATA_H_8822B)
+#define BIT_SET_MBIDCAM_RWDATA_H_8822B(x, v)                                   \
+	(BIT_CLEAR_MBIDCAM_RWDATA_H_8822B(x) | BIT_MBIDCAM_RWDATA_H_8822B(v))
+
+/* 2 REG_ZLD_NUM_8822B */
+
+#define BIT_SHIFT_ZLD_NUM_8822B 0
+#define BIT_MASK_ZLD_NUM_8822B 0xff
+#define BIT_ZLD_NUM_8822B(x)                                                   \
+	(((x) & BIT_MASK_ZLD_NUM_8822B) << BIT_SHIFT_ZLD_NUM_8822B)
+#define BITS_ZLD_NUM_8822B (BIT_MASK_ZLD_NUM_8822B << BIT_SHIFT_ZLD_NUM_8822B)
+#define BIT_CLEAR_ZLD_NUM_8822B(x) ((x) & (~BITS_ZLD_NUM_8822B))
+#define BIT_GET_ZLD_NUM_8822B(x)                                               \
+	(((x) >> BIT_SHIFT_ZLD_NUM_8822B) & BIT_MASK_ZLD_NUM_8822B)
+#define BIT_SET_ZLD_NUM_8822B(x, v)                                            \
+	(BIT_CLEAR_ZLD_NUM_8822B(x) | BIT_ZLD_NUM_8822B(v))
+
+/* 2 REG_UDF_THSD_8822B */
+
+#define BIT_SHIFT_UDF_THSD_8822B 0
+#define BIT_MASK_UDF_THSD_8822B 0xff
+#define BIT_UDF_THSD_8822B(x)                                                  \
+	(((x) & BIT_MASK_UDF_THSD_8822B) << BIT_SHIFT_UDF_THSD_8822B)
+#define BITS_UDF_THSD_8822B                                                    \
+	(BIT_MASK_UDF_THSD_8822B << BIT_SHIFT_UDF_THSD_8822B)
+#define BIT_CLEAR_UDF_THSD_8822B(x) ((x) & (~BITS_UDF_THSD_8822B))
+#define BIT_GET_UDF_THSD_8822B(x)                                              \
+	(((x) >> BIT_SHIFT_UDF_THSD_8822B) & BIT_MASK_UDF_THSD_8822B)
+#define BIT_SET_UDF_THSD_8822B(x, v)                                           \
+	(BIT_CLEAR_UDF_THSD_8822B(x) | BIT_UDF_THSD_8822B(v))
+
+/* 2 REG_WMAC_TCR_TSFT_OFS_8822B */
+
+#define BIT_SHIFT_WMAC_TCR_TSFT_OFS_8822B 0
+#define BIT_MASK_WMAC_TCR_TSFT_OFS_8822B 0xffff
+#define BIT_WMAC_TCR_TSFT_OFS_8822B(x)                                         \
+	(((x) & BIT_MASK_WMAC_TCR_TSFT_OFS_8822B)                              \
+	 << BIT_SHIFT_WMAC_TCR_TSFT_OFS_8822B)
+#define BITS_WMAC_TCR_TSFT_OFS_8822B                                           \
+	(BIT_MASK_WMAC_TCR_TSFT_OFS_8822B << BIT_SHIFT_WMAC_TCR_TSFT_OFS_8822B)
+#define BIT_CLEAR_WMAC_TCR_TSFT_OFS_8822B(x)                                   \
+	((x) & (~BITS_WMAC_TCR_TSFT_OFS_8822B))
+#define BIT_GET_WMAC_TCR_TSFT_OFS_8822B(x)                                     \
+	(((x) >> BIT_SHIFT_WMAC_TCR_TSFT_OFS_8822B) &                          \
+	 BIT_MASK_WMAC_TCR_TSFT_OFS_8822B)
+#define BIT_SET_WMAC_TCR_TSFT_OFS_8822B(x, v)                                  \
+	(BIT_CLEAR_WMAC_TCR_TSFT_OFS_8822B(x) | BIT_WMAC_TCR_TSFT_OFS_8822B(v))
+
+/* 2 REG_MCU_TEST_2_V1_8822B */
+
+#define BIT_SHIFT_MCU_RSVD_2_V1_8822B 0
+#define BIT_MASK_MCU_RSVD_2_V1_8822B 0xffff
+#define BIT_MCU_RSVD_2_V1_8822B(x)                                             \
+	(((x) & BIT_MASK_MCU_RSVD_2_V1_8822B) << BIT_SHIFT_MCU_RSVD_2_V1_8822B)
+#define BITS_MCU_RSVD_2_V1_8822B                                               \
+	(BIT_MASK_MCU_RSVD_2_V1_8822B << BIT_SHIFT_MCU_RSVD_2_V1_8822B)
+#define BIT_CLEAR_MCU_RSVD_2_V1_8822B(x) ((x) & (~BITS_MCU_RSVD_2_V1_8822B))
+#define BIT_GET_MCU_RSVD_2_V1_8822B(x)                                         \
+	(((x) >> BIT_SHIFT_MCU_RSVD_2_V1_8822B) & BIT_MASK_MCU_RSVD_2_V1_8822B)
+#define BIT_SET_MCU_RSVD_2_V1_8822B(x, v)                                      \
+	(BIT_CLEAR_MCU_RSVD_2_V1_8822B(x) | BIT_MCU_RSVD_2_V1_8822B(v))
+
+/* 2 REG_WMAC_TXTIMEOUT_8822B */
+
+#define BIT_SHIFT_WMAC_TXTIMEOUT_8822B 0
+#define BIT_MASK_WMAC_TXTIMEOUT_8822B 0xff
+#define BIT_WMAC_TXTIMEOUT_8822B(x)                                            \
+	(((x) & BIT_MASK_WMAC_TXTIMEOUT_8822B)                                 \
+	 << BIT_SHIFT_WMAC_TXTIMEOUT_8822B)
+#define BITS_WMAC_TXTIMEOUT_8822B                                              \
+	(BIT_MASK_WMAC_TXTIMEOUT_8822B << BIT_SHIFT_WMAC_TXTIMEOUT_8822B)
+#define BIT_CLEAR_WMAC_TXTIMEOUT_8822B(x) ((x) & (~BITS_WMAC_TXTIMEOUT_8822B))
+#define BIT_GET_WMAC_TXTIMEOUT_8822B(x)                                        \
+	(((x) >> BIT_SHIFT_WMAC_TXTIMEOUT_8822B) &                             \
+	 BIT_MASK_WMAC_TXTIMEOUT_8822B)
+#define BIT_SET_WMAC_TXTIMEOUT_8822B(x, v)                                     \
+	(BIT_CLEAR_WMAC_TXTIMEOUT_8822B(x) | BIT_WMAC_TXTIMEOUT_8822B(v))
+
+/* 2 REG_STMP_THSD_8822B */
+
+#define BIT_SHIFT_STMP_THSD_8822B 0
+#define BIT_MASK_STMP_THSD_8822B 0xff
+#define BIT_STMP_THSD_8822B(x)                                                 \
+	(((x) & BIT_MASK_STMP_THSD_8822B) << BIT_SHIFT_STMP_THSD_8822B)
+#define BITS_STMP_THSD_8822B                                                   \
+	(BIT_MASK_STMP_THSD_8822B << BIT_SHIFT_STMP_THSD_8822B)
+#define BIT_CLEAR_STMP_THSD_8822B(x) ((x) & (~BITS_STMP_THSD_8822B))
+#define BIT_GET_STMP_THSD_8822B(x)                                             \
+	(((x) >> BIT_SHIFT_STMP_THSD_8822B) & BIT_MASK_STMP_THSD_8822B)
+#define BIT_SET_STMP_THSD_8822B(x, v)                                          \
+	(BIT_CLEAR_STMP_THSD_8822B(x) | BIT_STMP_THSD_8822B(v))
+
+/* 2 REG_MAC_SPEC_SIFS_8822B (SPECIFICATION SIFS REGISTER) */
+
+#define BIT_SHIFT_SPEC_SIFS_OFDM_8822B 8
+#define BIT_MASK_SPEC_SIFS_OFDM_8822B 0xff
+#define BIT_SPEC_SIFS_OFDM_8822B(x)                                            \
+	(((x) & BIT_MASK_SPEC_SIFS_OFDM_8822B)                                 \
+	 << BIT_SHIFT_SPEC_SIFS_OFDM_8822B)
+#define BITS_SPEC_SIFS_OFDM_8822B                                              \
+	(BIT_MASK_SPEC_SIFS_OFDM_8822B << BIT_SHIFT_SPEC_SIFS_OFDM_8822B)
+#define BIT_CLEAR_SPEC_SIFS_OFDM_8822B(x) ((x) & (~BITS_SPEC_SIFS_OFDM_8822B))
+#define BIT_GET_SPEC_SIFS_OFDM_8822B(x)                                        \
+	(((x) >> BIT_SHIFT_SPEC_SIFS_OFDM_8822B) &                             \
+	 BIT_MASK_SPEC_SIFS_OFDM_8822B)
+#define BIT_SET_SPEC_SIFS_OFDM_8822B(x, v)                                     \
+	(BIT_CLEAR_SPEC_SIFS_OFDM_8822B(x) | BIT_SPEC_SIFS_OFDM_8822B(v))
+
+#define BIT_SHIFT_SPEC_SIFS_CCK_8822B 0
+#define BIT_MASK_SPEC_SIFS_CCK_8822B 0xff
+#define BIT_SPEC_SIFS_CCK_8822B(x)                                             \
+	(((x) & BIT_MASK_SPEC_SIFS_CCK_8822B) << BIT_SHIFT_SPEC_SIFS_CCK_8822B)
+#define BITS_SPEC_SIFS_CCK_8822B                                               \
+	(BIT_MASK_SPEC_SIFS_CCK_8822B << BIT_SHIFT_SPEC_SIFS_CCK_8822B)
+#define BIT_CLEAR_SPEC_SIFS_CCK_8822B(x) ((x) & (~BITS_SPEC_SIFS_CCK_8822B))
+#define BIT_GET_SPEC_SIFS_CCK_8822B(x)                                         \
+	(((x) >> BIT_SHIFT_SPEC_SIFS_CCK_8822B) & BIT_MASK_SPEC_SIFS_CCK_8822B)
+#define BIT_SET_SPEC_SIFS_CCK_8822B(x, v)                                      \
+	(BIT_CLEAR_SPEC_SIFS_CCK_8822B(x) | BIT_SPEC_SIFS_CCK_8822B(v))
+
+/* 2 REG_USTIME_EDCA_8822B (US TIME TUNING FOR EDCA REGISTER) */
+
+#define BIT_SHIFT_USTIME_EDCA_V1_8822B 0
+#define BIT_MASK_USTIME_EDCA_V1_8822B 0x1ff
+#define BIT_USTIME_EDCA_V1_8822B(x)                                            \
+	(((x) & BIT_MASK_USTIME_EDCA_V1_8822B)                                 \
+	 << BIT_SHIFT_USTIME_EDCA_V1_8822B)
+#define BITS_USTIME_EDCA_V1_8822B                                              \
+	(BIT_MASK_USTIME_EDCA_V1_8822B << BIT_SHIFT_USTIME_EDCA_V1_8822B)
+#define BIT_CLEAR_USTIME_EDCA_V1_8822B(x) ((x) & (~BITS_USTIME_EDCA_V1_8822B))
+#define BIT_GET_USTIME_EDCA_V1_8822B(x)                                        \
+	(((x) >> BIT_SHIFT_USTIME_EDCA_V1_8822B) &                             \
+	 BIT_MASK_USTIME_EDCA_V1_8822B)
+#define BIT_SET_USTIME_EDCA_V1_8822B(x, v)                                     \
+	(BIT_CLEAR_USTIME_EDCA_V1_8822B(x) | BIT_USTIME_EDCA_V1_8822B(v))
+
+/* 2 REG_RESP_SIFS_OFDM_8822B (RESPONSE SIFS FOR OFDM REGISTER) */
+
+#define BIT_SHIFT_SIFS_R2T_OFDM_8822B 8
+#define BIT_MASK_SIFS_R2T_OFDM_8822B 0xff
+#define BIT_SIFS_R2T_OFDM_8822B(x)                                             \
+	(((x) & BIT_MASK_SIFS_R2T_OFDM_8822B) << BIT_SHIFT_SIFS_R2T_OFDM_8822B)
+#define BITS_SIFS_R2T_OFDM_8822B                                               \
+	(BIT_MASK_SIFS_R2T_OFDM_8822B << BIT_SHIFT_SIFS_R2T_OFDM_8822B)
+#define BIT_CLEAR_SIFS_R2T_OFDM_8822B(x) ((x) & (~BITS_SIFS_R2T_OFDM_8822B))
+#define BIT_GET_SIFS_R2T_OFDM_8822B(x)                                         \
+	(((x) >> BIT_SHIFT_SIFS_R2T_OFDM_8822B) & BIT_MASK_SIFS_R2T_OFDM_8822B)
+#define BIT_SET_SIFS_R2T_OFDM_8822B(x, v)                                      \
+	(BIT_CLEAR_SIFS_R2T_OFDM_8822B(x) | BIT_SIFS_R2T_OFDM_8822B(v))
+
+#define BIT_SHIFT_SIFS_T2T_OFDM_8822B 0
+#define BIT_MASK_SIFS_T2T_OFDM_8822B 0xff
+#define BIT_SIFS_T2T_OFDM_8822B(x)                                             \
+	(((x) & BIT_MASK_SIFS_T2T_OFDM_8822B) << BIT_SHIFT_SIFS_T2T_OFDM_8822B)
+#define BITS_SIFS_T2T_OFDM_8822B                                               \
+	(BIT_MASK_SIFS_T2T_OFDM_8822B << BIT_SHIFT_SIFS_T2T_OFDM_8822B)
+#define BIT_CLEAR_SIFS_T2T_OFDM_8822B(x) ((x) & (~BITS_SIFS_T2T_OFDM_8822B))
+#define BIT_GET_SIFS_T2T_OFDM_8822B(x)                                         \
+	(((x) >> BIT_SHIFT_SIFS_T2T_OFDM_8822B) & BIT_MASK_SIFS_T2T_OFDM_8822B)
+#define BIT_SET_SIFS_T2T_OFDM_8822B(x, v)                                      \
+	(BIT_CLEAR_SIFS_T2T_OFDM_8822B(x) | BIT_SIFS_T2T_OFDM_8822B(v))
+
+/* 2 REG_RESP_SIFS_CCK_8822B (RESPONSE SIFS FOR CCK REGISTER) */
+
+#define BIT_SHIFT_SIFS_R2T_CCK_8822B 8
+#define BIT_MASK_SIFS_R2T_CCK_8822B 0xff
+#define BIT_SIFS_R2T_CCK_8822B(x)                                              \
+	(((x) & BIT_MASK_SIFS_R2T_CCK_8822B) << BIT_SHIFT_SIFS_R2T_CCK_8822B)
+#define BITS_SIFS_R2T_CCK_8822B                                                \
+	(BIT_MASK_SIFS_R2T_CCK_8822B << BIT_SHIFT_SIFS_R2T_CCK_8822B)
+#define BIT_CLEAR_SIFS_R2T_CCK_8822B(x) ((x) & (~BITS_SIFS_R2T_CCK_8822B))
+#define BIT_GET_SIFS_R2T_CCK_8822B(x)                                          \
+	(((x) >> BIT_SHIFT_SIFS_R2T_CCK_8822B) & BIT_MASK_SIFS_R2T_CCK_8822B)
+#define BIT_SET_SIFS_R2T_CCK_8822B(x, v)                                       \
+	(BIT_CLEAR_SIFS_R2T_CCK_8822B(x) | BIT_SIFS_R2T_CCK_8822B(v))
+
+#define BIT_SHIFT_SIFS_T2T_CCK_8822B 0
+#define BIT_MASK_SIFS_T2T_CCK_8822B 0xff
+#define BIT_SIFS_T2T_CCK_8822B(x)                                              \
+	(((x) & BIT_MASK_SIFS_T2T_CCK_8822B) << BIT_SHIFT_SIFS_T2T_CCK_8822B)
+#define BITS_SIFS_T2T_CCK_8822B                                                \
+	(BIT_MASK_SIFS_T2T_CCK_8822B << BIT_SHIFT_SIFS_T2T_CCK_8822B)
+#define BIT_CLEAR_SIFS_T2T_CCK_8822B(x) ((x) & (~BITS_SIFS_T2T_CCK_8822B))
+#define BIT_GET_SIFS_T2T_CCK_8822B(x)                                          \
+	(((x) >> BIT_SHIFT_SIFS_T2T_CCK_8822B) & BIT_MASK_SIFS_T2T_CCK_8822B)
+#define BIT_SET_SIFS_T2T_CCK_8822B(x, v)                                       \
+	(BIT_CLEAR_SIFS_T2T_CCK_8822B(x) | BIT_SIFS_T2T_CCK_8822B(v))
+
+/* 2 REG_EIFS_8822B (EIFS REGISTER) */
+
+#define BIT_SHIFT_EIFS_8822B 0
+#define BIT_MASK_EIFS_8822B 0xffff
+#define BIT_EIFS_8822B(x) (((x) & BIT_MASK_EIFS_8822B) << BIT_SHIFT_EIFS_8822B)
+#define BITS_EIFS_8822B (BIT_MASK_EIFS_8822B << BIT_SHIFT_EIFS_8822B)
+#define BIT_CLEAR_EIFS_8822B(x) ((x) & (~BITS_EIFS_8822B))
+#define BIT_GET_EIFS_8822B(x)                                                  \
+	(((x) >> BIT_SHIFT_EIFS_8822B) & BIT_MASK_EIFS_8822B)
+#define BIT_SET_EIFS_8822B(x, v) (BIT_CLEAR_EIFS_8822B(x) | BIT_EIFS_8822B(v))
+
+/* 2 REG_CTS2TO_8822B (CTS2 TIMEOUT REGISTER) */
+
+#define BIT_SHIFT_CTS2TO_8822B 0
+#define BIT_MASK_CTS2TO_8822B 0xff
+#define BIT_CTS2TO_8822B(x)                                                    \
+	(((x) & BIT_MASK_CTS2TO_8822B) << BIT_SHIFT_CTS2TO_8822B)
+#define BITS_CTS2TO_8822B (BIT_MASK_CTS2TO_8822B << BIT_SHIFT_CTS2TO_8822B)
+#define BIT_CLEAR_CTS2TO_8822B(x) ((x) & (~BITS_CTS2TO_8822B))
+#define BIT_GET_CTS2TO_8822B(x)                                                \
+	(((x) >> BIT_SHIFT_CTS2TO_8822B) & BIT_MASK_CTS2TO_8822B)
+#define BIT_SET_CTS2TO_8822B(x, v)                                             \
+	(BIT_CLEAR_CTS2TO_8822B(x) | BIT_CTS2TO_8822B(v))
+
+/* 2 REG_ACKTO_8822B (ACK TIMEOUT REGISTER) */
+
+#define BIT_SHIFT_ACKTO_8822B 0
+#define BIT_MASK_ACKTO_8822B 0xff
+#define BIT_ACKTO_8822B(x)                                                     \
+	(((x) & BIT_MASK_ACKTO_8822B) << BIT_SHIFT_ACKTO_8822B)
+#define BITS_ACKTO_8822B (BIT_MASK_ACKTO_8822B << BIT_SHIFT_ACKTO_8822B)
+#define BIT_CLEAR_ACKTO_8822B(x) ((x) & (~BITS_ACKTO_8822B))
+#define BIT_GET_ACKTO_8822B(x)                                                 \
+	(((x) >> BIT_SHIFT_ACKTO_8822B) & BIT_MASK_ACKTO_8822B)
+#define BIT_SET_ACKTO_8822B(x, v)                                              \
+	(BIT_CLEAR_ACKTO_8822B(x) | BIT_ACKTO_8822B(v))
+
+/* 2 REG_NAV_CTRL_8822B (NAV CONTROL REGISTER) */
+
+#define BIT_SHIFT_NAV_UPPER_8822B 16
+#define BIT_MASK_NAV_UPPER_8822B 0xff
+#define BIT_NAV_UPPER_8822B(x)                                                 \
+	(((x) & BIT_MASK_NAV_UPPER_8822B) << BIT_SHIFT_NAV_UPPER_8822B)
+#define BITS_NAV_UPPER_8822B                                                   \
+	(BIT_MASK_NAV_UPPER_8822B << BIT_SHIFT_NAV_UPPER_8822B)
+#define BIT_CLEAR_NAV_UPPER_8822B(x) ((x) & (~BITS_NAV_UPPER_8822B))
+#define BIT_GET_NAV_UPPER_8822B(x)                                             \
+	(((x) >> BIT_SHIFT_NAV_UPPER_8822B) & BIT_MASK_NAV_UPPER_8822B)
+#define BIT_SET_NAV_UPPER_8822B(x, v)                                          \
+	(BIT_CLEAR_NAV_UPPER_8822B(x) | BIT_NAV_UPPER_8822B(v))
+
+#define BIT_SHIFT_RXMYRTS_NAV_8822B 8
+#define BIT_MASK_RXMYRTS_NAV_8822B 0xf
+#define BIT_RXMYRTS_NAV_8822B(x)                                               \
+	(((x) & BIT_MASK_RXMYRTS_NAV_8822B) << BIT_SHIFT_RXMYRTS_NAV_8822B)
+#define BITS_RXMYRTS_NAV_8822B                                                 \
+	(BIT_MASK_RXMYRTS_NAV_8822B << BIT_SHIFT_RXMYRTS_NAV_8822B)
+#define BIT_CLEAR_RXMYRTS_NAV_8822B(x) ((x) & (~BITS_RXMYRTS_NAV_8822B))
+#define BIT_GET_RXMYRTS_NAV_8822B(x)                                           \
+	(((x) >> BIT_SHIFT_RXMYRTS_NAV_8822B) & BIT_MASK_RXMYRTS_NAV_8822B)
+#define BIT_SET_RXMYRTS_NAV_8822B(x, v)                                        \
+	(BIT_CLEAR_RXMYRTS_NAV_8822B(x) | BIT_RXMYRTS_NAV_8822B(v))
+
+#define BIT_SHIFT_RTSRST_8822B 0
+#define BIT_MASK_RTSRST_8822B 0xff
+#define BIT_RTSRST_8822B(x)                                                    \
+	(((x) & BIT_MASK_RTSRST_8822B) << BIT_SHIFT_RTSRST_8822B)
+#define BITS_RTSRST_8822B (BIT_MASK_RTSRST_8822B << BIT_SHIFT_RTSRST_8822B)
+#define BIT_CLEAR_RTSRST_8822B(x) ((x) & (~BITS_RTSRST_8822B))
+#define BIT_GET_RTSRST_8822B(x)                                                \
+	(((x) >> BIT_SHIFT_RTSRST_8822B) & BIT_MASK_RTSRST_8822B)
+#define BIT_SET_RTSRST_8822B(x, v)                                             \
+	(BIT_CLEAR_RTSRST_8822B(x) | BIT_RTSRST_8822B(v))
+
+/* 2 REG_BACAMCMD_8822B (BLOCK ACK CAM COMMAND REGISTER) */
+#define BIT_BACAM_POLL_8822B BIT(31)
+#define BIT_BACAM_RST_8822B BIT(17)
+#define BIT_BACAM_RW_8822B BIT(16)
+
+#define BIT_SHIFT_TXSBM_8822B 14
+#define BIT_MASK_TXSBM_8822B 0x3
+#define BIT_TXSBM_8822B(x)                                                     \
+	(((x) & BIT_MASK_TXSBM_8822B) << BIT_SHIFT_TXSBM_8822B)
+#define BITS_TXSBM_8822B (BIT_MASK_TXSBM_8822B << BIT_SHIFT_TXSBM_8822B)
+#define BIT_CLEAR_TXSBM_8822B(x) ((x) & (~BITS_TXSBM_8822B))
+#define BIT_GET_TXSBM_8822B(x)                                                 \
+	(((x) >> BIT_SHIFT_TXSBM_8822B) & BIT_MASK_TXSBM_8822B)
+#define BIT_SET_TXSBM_8822B(x, v)                                              \
+	(BIT_CLEAR_TXSBM_8822B(x) | BIT_TXSBM_8822B(v))
+
+#define BIT_SHIFT_BACAM_ADDR_8822B 0
+#define BIT_MASK_BACAM_ADDR_8822B 0x3f
+#define BIT_BACAM_ADDR_8822B(x)                                                \
+	(((x) & BIT_MASK_BACAM_ADDR_8822B) << BIT_SHIFT_BACAM_ADDR_8822B)
+#define BITS_BACAM_ADDR_8822B                                                  \
+	(BIT_MASK_BACAM_ADDR_8822B << BIT_SHIFT_BACAM_ADDR_8822B)
+#define BIT_CLEAR_BACAM_ADDR_8822B(x) ((x) & (~BITS_BACAM_ADDR_8822B))
+#define BIT_GET_BACAM_ADDR_8822B(x)                                            \
+	(((x) >> BIT_SHIFT_BACAM_ADDR_8822B) & BIT_MASK_BACAM_ADDR_8822B)
+#define BIT_SET_BACAM_ADDR_8822B(x, v)                                         \
+	(BIT_CLEAR_BACAM_ADDR_8822B(x) | BIT_BACAM_ADDR_8822B(v))
+
+/* 2 REG_BACAMCONTENT_8822B (BLOCK ACK CAM CONTENT REGISTER) */
+
+#define BIT_SHIFT_BA_CONTENT_H_8822B (32 & CPU_OPT_WIDTH)
+#define BIT_MASK_BA_CONTENT_H_8822B 0xffffffffL
+#define BIT_BA_CONTENT_H_8822B(x)                                              \
+	(((x) & BIT_MASK_BA_CONTENT_H_8822B) << BIT_SHIFT_BA_CONTENT_H_8822B)
+#define BITS_BA_CONTENT_H_8822B                                                \
+	(BIT_MASK_BA_CONTENT_H_8822B << BIT_SHIFT_BA_CONTENT_H_8822B)
+#define BIT_CLEAR_BA_CONTENT_H_8822B(x) ((x) & (~BITS_BA_CONTENT_H_8822B))
+#define BIT_GET_BA_CONTENT_H_8822B(x)                                          \
+	(((x) >> BIT_SHIFT_BA_CONTENT_H_8822B) & BIT_MASK_BA_CONTENT_H_8822B)
+#define BIT_SET_BA_CONTENT_H_8822B(x, v)                                       \
+	(BIT_CLEAR_BA_CONTENT_H_8822B(x) | BIT_BA_CONTENT_H_8822B(v))
+
+#define BIT_SHIFT_BA_CONTENT_L_8822B 0
+#define BIT_MASK_BA_CONTENT_L_8822B 0xffffffffL
+#define BIT_BA_CONTENT_L_8822B(x)                                              \
+	(((x) & BIT_MASK_BA_CONTENT_L_8822B) << BIT_SHIFT_BA_CONTENT_L_8822B)
+#define BITS_BA_CONTENT_L_8822B                                                \
+	(BIT_MASK_BA_CONTENT_L_8822B << BIT_SHIFT_BA_CONTENT_L_8822B)
+#define BIT_CLEAR_BA_CONTENT_L_8822B(x) ((x) & (~BITS_BA_CONTENT_L_8822B))
+#define BIT_GET_BA_CONTENT_L_8822B(x)                                          \
+	(((x) >> BIT_SHIFT_BA_CONTENT_L_8822B) & BIT_MASK_BA_CONTENT_L_8822B)
+#define BIT_SET_BA_CONTENT_L_8822B(x, v)                                       \
+	(BIT_CLEAR_BA_CONTENT_L_8822B(x) | BIT_BA_CONTENT_L_8822B(v))
+
+/* 2 REG_WMAC_BITMAP_CTL_8822B */
+#define BIT_BITMAP_VO_8822B BIT(7)
+#define BIT_BITMAP_VI_8822B BIT(6)
+#define BIT_BITMAP_BE_8822B BIT(5)
+#define BIT_BITMAP_BK_8822B BIT(4)
+
+#define BIT_SHIFT_BITMAP_CONDITION_8822B 2
+#define BIT_MASK_BITMAP_CONDITION_8822B 0x3
+#define BIT_BITMAP_CONDITION_8822B(x)                                          \
+	(((x) & BIT_MASK_BITMAP_CONDITION_8822B)                               \
+	 << BIT_SHIFT_BITMAP_CONDITION_8822B)
+#define BITS_BITMAP_CONDITION_8822B                                            \
+	(BIT_MASK_BITMAP_CONDITION_8822B << BIT_SHIFT_BITMAP_CONDITION_8822B)
+#define BIT_CLEAR_BITMAP_CONDITION_8822B(x)                                    \
+	((x) & (~BITS_BITMAP_CONDITION_8822B))
+#define BIT_GET_BITMAP_CONDITION_8822B(x)                                      \
+	(((x) >> BIT_SHIFT_BITMAP_CONDITION_8822B) &                           \
+	 BIT_MASK_BITMAP_CONDITION_8822B)
+#define BIT_SET_BITMAP_CONDITION_8822B(x, v)                                   \
+	(BIT_CLEAR_BITMAP_CONDITION_8822B(x) | BIT_BITMAP_CONDITION_8822B(v))
+
+#define BIT_BITMAP_SSNBK_COUNTER_CLR_8822B BIT(1)
+#define BIT_BITMAP_FORCE_8822B BIT(0)
+
+/* 2 REG_TX_RX_8822B STATUS */
+
+#define BIT_SHIFT_RXPKT_TYPE_8822B 2
+#define BIT_MASK_RXPKT_TYPE_8822B 0x3f
+#define BIT_RXPKT_TYPE_8822B(x)                                                \
+	(((x) & BIT_MASK_RXPKT_TYPE_8822B) << BIT_SHIFT_RXPKT_TYPE_8822B)
+#define BITS_RXPKT_TYPE_8822B                                                  \
+	(BIT_MASK_RXPKT_TYPE_8822B << BIT_SHIFT_RXPKT_TYPE_8822B)
+#define BIT_CLEAR_RXPKT_TYPE_8822B(x) ((x) & (~BITS_RXPKT_TYPE_8822B))
+#define BIT_GET_RXPKT_TYPE_8822B(x)                                            \
+	(((x) >> BIT_SHIFT_RXPKT_TYPE_8822B) & BIT_MASK_RXPKT_TYPE_8822B)
+#define BIT_SET_RXPKT_TYPE_8822B(x, v)                                         \
+	(BIT_CLEAR_RXPKT_TYPE_8822B(x) | BIT_RXPKT_TYPE_8822B(v))
+
+#define BIT_TXACT_IND_8822B BIT(1)
+#define BIT_RXACT_IND_8822B BIT(0)
+
+/* 2 REG_WMAC_BACAM_RPMEN_8822B */
+
+#define BIT_SHIFT_BITMAP_SSNBK_COUNTER_8822B 2
+#define BIT_MASK_BITMAP_SSNBK_COUNTER_8822B 0x3f
+#define BIT_BITMAP_SSNBK_COUNTER_8822B(x)                                      \
+	(((x) & BIT_MASK_BITMAP_SSNBK_COUNTER_8822B)                           \
+	 << BIT_SHIFT_BITMAP_SSNBK_COUNTER_8822B)
+#define BITS_BITMAP_SSNBK_COUNTER_8822B                                        \
+	(BIT_MASK_BITMAP_SSNBK_COUNTER_8822B                                   \
+	 << BIT_SHIFT_BITMAP_SSNBK_COUNTER_8822B)
+#define BIT_CLEAR_BITMAP_SSNBK_COUNTER_8822B(x)                                \
+	((x) & (~BITS_BITMAP_SSNBK_COUNTER_8822B))
+#define BIT_GET_BITMAP_SSNBK_COUNTER_8822B(x)                                  \
+	(((x) >> BIT_SHIFT_BITMAP_SSNBK_COUNTER_8822B) &                       \
+	 BIT_MASK_BITMAP_SSNBK_COUNTER_8822B)
+#define BIT_SET_BITMAP_SSNBK_COUNTER_8822B(x, v)                               \
+	(BIT_CLEAR_BITMAP_SSNBK_COUNTER_8822B(x) |                             \
+	 BIT_BITMAP_SSNBK_COUNTER_8822B(v))
+
+#define BIT_BITMAP_EN_8822B BIT(1)
+#define BIT_WMAC_BACAM_RPMEN_8822B BIT(0)
+
+/* 2 REG_LBDLY_8822B (LOOPBACK DELAY REGISTER) */
+
+#define BIT_SHIFT_LBDLY_8822B 0
+#define BIT_MASK_LBDLY_8822B 0x1f
+#define BIT_LBDLY_8822B(x)                                                     \
+	(((x) & BIT_MASK_LBDLY_8822B) << BIT_SHIFT_LBDLY_8822B)
+#define BITS_LBDLY_8822B (BIT_MASK_LBDLY_8822B << BIT_SHIFT_LBDLY_8822B)
+#define BIT_CLEAR_LBDLY_8822B(x) ((x) & (~BITS_LBDLY_8822B))
+#define BIT_GET_LBDLY_8822B(x)                                                 \
+	(((x) >> BIT_SHIFT_LBDLY_8822B) & BIT_MASK_LBDLY_8822B)
+#define BIT_SET_LBDLY_8822B(x, v)                                              \
+	(BIT_CLEAR_LBDLY_8822B(x) | BIT_LBDLY_8822B(v))
+
+/* 2 REG_RXERR_RPT_8822B (RX ERROR REPORT REGISTER) */
+
+#define BIT_SHIFT_RXERR_RPT_SEL_V1_3_0_8822B 28
+#define BIT_MASK_RXERR_RPT_SEL_V1_3_0_8822B 0xf
+#define BIT_RXERR_RPT_SEL_V1_3_0_8822B(x)                                      \
+	(((x) & BIT_MASK_RXERR_RPT_SEL_V1_3_0_8822B)                           \
+	 << BIT_SHIFT_RXERR_RPT_SEL_V1_3_0_8822B)
+#define BITS_RXERR_RPT_SEL_V1_3_0_8822B                                        \
+	(BIT_MASK_RXERR_RPT_SEL_V1_3_0_8822B                                   \
+	 << BIT_SHIFT_RXERR_RPT_SEL_V1_3_0_8822B)
+#define BIT_CLEAR_RXERR_RPT_SEL_V1_3_0_8822B(x)                                \
+	((x) & (~BITS_RXERR_RPT_SEL_V1_3_0_8822B))
+#define BIT_GET_RXERR_RPT_SEL_V1_3_0_8822B(x)                                  \
+	(((x) >> BIT_SHIFT_RXERR_RPT_SEL_V1_3_0_8822B) &                       \
+	 BIT_MASK_RXERR_RPT_SEL_V1_3_0_8822B)
+#define BIT_SET_RXERR_RPT_SEL_V1_3_0_8822B(x, v)                               \
+	(BIT_CLEAR_RXERR_RPT_SEL_V1_3_0_8822B(x) |                             \
+	 BIT_RXERR_RPT_SEL_V1_3_0_8822B(v))
+
+#define BIT_RXERR_RPT_RST_8822B BIT(27)
+#define BIT_RXERR_RPT_SEL_V1_4_8822B BIT(26)
+#define BIT_W1S_8822B BIT(23)
+#define BIT_UD_SELECT_BSSID_8822B BIT(22)
+
+#define BIT_SHIFT_UD_SUB_TYPE_8822B 18
+#define BIT_MASK_UD_SUB_TYPE_8822B 0xf
+#define BIT_UD_SUB_TYPE_8822B(x)                                               \
+	(((x) & BIT_MASK_UD_SUB_TYPE_8822B) << BIT_SHIFT_UD_SUB_TYPE_8822B)
+#define BITS_UD_SUB_TYPE_8822B                                                 \
+	(BIT_MASK_UD_SUB_TYPE_8822B << BIT_SHIFT_UD_SUB_TYPE_8822B)
+#define BIT_CLEAR_UD_SUB_TYPE_8822B(x) ((x) & (~BITS_UD_SUB_TYPE_8822B))
+#define BIT_GET_UD_SUB_TYPE_8822B(x)                                           \
+	(((x) >> BIT_SHIFT_UD_SUB_TYPE_8822B) & BIT_MASK_UD_SUB_TYPE_8822B)
+#define BIT_SET_UD_SUB_TYPE_8822B(x, v)                                        \
+	(BIT_CLEAR_UD_SUB_TYPE_8822B(x) | BIT_UD_SUB_TYPE_8822B(v))
+
+#define BIT_SHIFT_UD_TYPE_8822B 16
+#define BIT_MASK_UD_TYPE_8822B 0x3
+#define BIT_UD_TYPE_8822B(x)                                                   \
+	(((x) & BIT_MASK_UD_TYPE_8822B) << BIT_SHIFT_UD_TYPE_8822B)
+#define BITS_UD_TYPE_8822B (BIT_MASK_UD_TYPE_8822B << BIT_SHIFT_UD_TYPE_8822B)
+#define BIT_CLEAR_UD_TYPE_8822B(x) ((x) & (~BITS_UD_TYPE_8822B))
+#define BIT_GET_UD_TYPE_8822B(x)                                               \
+	(((x) >> BIT_SHIFT_UD_TYPE_8822B) & BIT_MASK_UD_TYPE_8822B)
+#define BIT_SET_UD_TYPE_8822B(x, v)                                            \
+	(BIT_CLEAR_UD_TYPE_8822B(x) | BIT_UD_TYPE_8822B(v))
+
+#define BIT_SHIFT_RPT_COUNTER_8822B 0
+#define BIT_MASK_RPT_COUNTER_8822B 0xffff
+#define BIT_RPT_COUNTER_8822B(x)                                               \
+	(((x) & BIT_MASK_RPT_COUNTER_8822B) << BIT_SHIFT_RPT_COUNTER_8822B)
+#define BITS_RPT_COUNTER_8822B                                                 \
+	(BIT_MASK_RPT_COUNTER_8822B << BIT_SHIFT_RPT_COUNTER_8822B)
+#define BIT_CLEAR_RPT_COUNTER_8822B(x) ((x) & (~BITS_RPT_COUNTER_8822B))
+#define BIT_GET_RPT_COUNTER_8822B(x)                                           \
+	(((x) >> BIT_SHIFT_RPT_COUNTER_8822B) & BIT_MASK_RPT_COUNTER_8822B)
+#define BIT_SET_RPT_COUNTER_8822B(x, v)                                        \
+	(BIT_CLEAR_RPT_COUNTER_8822B(x) | BIT_RPT_COUNTER_8822B(v))
+
+/* 2 REG_WMAC_TRXPTCL_CTL_8822B (WMAC TX/RX PROTOCOL CONTROL REGISTER) */
+
+#define BIT_SHIFT_ACKBA_TYPSEL_8822B (60 & CPU_OPT_WIDTH)
+#define BIT_MASK_ACKBA_TYPSEL_8822B 0xf
+#define BIT_ACKBA_TYPSEL_8822B(x)                                              \
+	(((x) & BIT_MASK_ACKBA_TYPSEL_8822B) << BIT_SHIFT_ACKBA_TYPSEL_8822B)
+#define BITS_ACKBA_TYPSEL_8822B                                                \
+	(BIT_MASK_ACKBA_TYPSEL_8822B << BIT_SHIFT_ACKBA_TYPSEL_8822B)
+#define BIT_CLEAR_ACKBA_TYPSEL_8822B(x) ((x) & (~BITS_ACKBA_TYPSEL_8822B))
+#define BIT_GET_ACKBA_TYPSEL_8822B(x)                                          \
+	(((x) >> BIT_SHIFT_ACKBA_TYPSEL_8822B) & BIT_MASK_ACKBA_TYPSEL_8822B)
+#define BIT_SET_ACKBA_TYPSEL_8822B(x, v)                                       \
+	(BIT_CLEAR_ACKBA_TYPSEL_8822B(x) | BIT_ACKBA_TYPSEL_8822B(v))
+
+#define BIT_SHIFT_ACKBA_ACKPCHK_8822B (56 & CPU_OPT_WIDTH)
+#define BIT_MASK_ACKBA_ACKPCHK_8822B 0xf
+#define BIT_ACKBA_ACKPCHK_8822B(x)                                             \
+	(((x) & BIT_MASK_ACKBA_ACKPCHK_8822B) << BIT_SHIFT_ACKBA_ACKPCHK_8822B)
+#define BITS_ACKBA_ACKPCHK_8822B                                               \
+	(BIT_MASK_ACKBA_ACKPCHK_8822B << BIT_SHIFT_ACKBA_ACKPCHK_8822B)
+#define BIT_CLEAR_ACKBA_ACKPCHK_8822B(x) ((x) & (~BITS_ACKBA_ACKPCHK_8822B))
+#define BIT_GET_ACKBA_ACKPCHK_8822B(x)                                         \
+	(((x) >> BIT_SHIFT_ACKBA_ACKPCHK_8822B) & BIT_MASK_ACKBA_ACKPCHK_8822B)
+#define BIT_SET_ACKBA_ACKPCHK_8822B(x, v)                                      \
+	(BIT_CLEAR_ACKBA_ACKPCHK_8822B(x) | BIT_ACKBA_ACKPCHK_8822B(v))
+
+#define BIT_SHIFT_ACKBAR_TYPESEL_8822B (48 & CPU_OPT_WIDTH)
+#define BIT_MASK_ACKBAR_TYPESEL_8822B 0xff
+#define BIT_ACKBAR_TYPESEL_8822B(x)                                            \
+	(((x) & BIT_MASK_ACKBAR_TYPESEL_8822B)                                 \
+	 << BIT_SHIFT_ACKBAR_TYPESEL_8822B)
+#define BITS_ACKBAR_TYPESEL_8822B                                              \
+	(BIT_MASK_ACKBAR_TYPESEL_8822B << BIT_SHIFT_ACKBAR_TYPESEL_8822B)
+#define BIT_CLEAR_ACKBAR_TYPESEL_8822B(x) ((x) & (~BITS_ACKBAR_TYPESEL_8822B))
+#define BIT_GET_ACKBAR_TYPESEL_8822B(x)                                        \
+	(((x) >> BIT_SHIFT_ACKBAR_TYPESEL_8822B) &                             \
+	 BIT_MASK_ACKBAR_TYPESEL_8822B)
+#define BIT_SET_ACKBAR_TYPESEL_8822B(x, v)                                     \
+	(BIT_CLEAR_ACKBAR_TYPESEL_8822B(x) | BIT_ACKBAR_TYPESEL_8822B(v))
+
+#define BIT_SHIFT_ACKBAR_ACKPCHK_8822B (44 & CPU_OPT_WIDTH)
+#define BIT_MASK_ACKBAR_ACKPCHK_8822B 0xf
+#define BIT_ACKBAR_ACKPCHK_8822B(x)                                            \
+	(((x) & BIT_MASK_ACKBAR_ACKPCHK_8822B)                                 \
+	 << BIT_SHIFT_ACKBAR_ACKPCHK_8822B)
+#define BITS_ACKBAR_ACKPCHK_8822B                                              \
+	(BIT_MASK_ACKBAR_ACKPCHK_8822B << BIT_SHIFT_ACKBAR_ACKPCHK_8822B)
+#define BIT_CLEAR_ACKBAR_ACKPCHK_8822B(x) ((x) & (~BITS_ACKBAR_ACKPCHK_8822B))
+#define BIT_GET_ACKBAR_ACKPCHK_8822B(x)                                        \
+	(((x) >> BIT_SHIFT_ACKBAR_ACKPCHK_8822B) &                             \
+	 BIT_MASK_ACKBAR_ACKPCHK_8822B)
+#define BIT_SET_ACKBAR_ACKPCHK_8822B(x, v)                                     \
+	(BIT_CLEAR_ACKBAR_ACKPCHK_8822B(x) | BIT_ACKBAR_ACKPCHK_8822B(v))
+
+#define BIT_RXBA_IGNOREA2_8822B BIT(42)
+#define BIT_EN_SAVE_ALL_TXOPADDR_8822B BIT(41)
+#define BIT_EN_TXCTS_TO_TXOPOWNER_INRXNAV_8822B BIT(40)
+#define BIT_DIS_TXBA_AMPDUFCSERR_8822B BIT(39)
+#define BIT_DIS_TXBA_RXBARINFULL_8822B BIT(38)
+#define BIT_DIS_TXCFE_INFULL_8822B BIT(37)
+#define BIT_DIS_TXCTS_INFULL_8822B BIT(36)
+#define BIT_EN_TXACKBA_IN_TX_RDG_8822B BIT(35)
+#define BIT_EN_TXACKBA_IN_TXOP_8822B BIT(34)
+#define BIT_EN_TXCTS_IN_RXNAV_8822B BIT(33)
+#define BIT_EN_TXCTS_INTXOP_8822B BIT(32)
+#define BIT_BLK_EDCA_BBSLP_8822B BIT(31)
+#define BIT_BLK_EDCA_BBSBY_8822B BIT(30)
+#define BIT_ACKTO_BLOCK_SCH_EN_8822B BIT(27)
+#define BIT_EIFS_BLOCK_SCH_EN_8822B BIT(26)
+#define BIT_PLCPCHK_RST_EIFS_8822B BIT(25)
+#define BIT_CCA_RST_EIFS_8822B BIT(24)
+#define BIT_DIS_UPD_MYRXPKTNAV_8822B BIT(23)
+#define BIT_EARLY_TXBA_8822B BIT(22)
+
+#define BIT_SHIFT_RESP_CHNBUSY_8822B 20
+#define BIT_MASK_RESP_CHNBUSY_8822B 0x3
+#define BIT_RESP_CHNBUSY_8822B(x)                                              \
+	(((x) & BIT_MASK_RESP_CHNBUSY_8822B) << BIT_SHIFT_RESP_CHNBUSY_8822B)
+#define BITS_RESP_CHNBUSY_8822B                                                \
+	(BIT_MASK_RESP_CHNBUSY_8822B << BIT_SHIFT_RESP_CHNBUSY_8822B)
+#define BIT_CLEAR_RESP_CHNBUSY_8822B(x) ((x) & (~BITS_RESP_CHNBUSY_8822B))
+#define BIT_GET_RESP_CHNBUSY_8822B(x)                                          \
+	(((x) >> BIT_SHIFT_RESP_CHNBUSY_8822B) & BIT_MASK_RESP_CHNBUSY_8822B)
+#define BIT_SET_RESP_CHNBUSY_8822B(x, v)                                       \
+	(BIT_CLEAR_RESP_CHNBUSY_8822B(x) | BIT_RESP_CHNBUSY_8822B(v))
+
+#define BIT_RESP_DCTS_EN_8822B BIT(19)
+#define BIT_RESP_DCFE_EN_8822B BIT(18)
+#define BIT_RESP_SPLCPEN_8822B BIT(17)
+#define BIT_RESP_SGIEN_8822B BIT(16)
+#define BIT_RESP_LDPC_EN_8822B BIT(15)
+#define BIT_DIS_RESP_ACKINCCA_8822B BIT(14)
+#define BIT_DIS_RESP_CTSINCCA_8822B BIT(13)
+
+#define BIT_SHIFT_R_WMAC_SECOND_CCA_TIMER_8822B 10
+#define BIT_MASK_R_WMAC_SECOND_CCA_TIMER_8822B 0x7
+#define BIT_R_WMAC_SECOND_CCA_TIMER_8822B(x)                                   \
+	(((x) & BIT_MASK_R_WMAC_SECOND_CCA_TIMER_8822B)                        \
+	 << BIT_SHIFT_R_WMAC_SECOND_CCA_TIMER_8822B)
+#define BITS_R_WMAC_SECOND_CCA_TIMER_8822B                                     \
+	(BIT_MASK_R_WMAC_SECOND_CCA_TIMER_8822B                                \
+	 << BIT_SHIFT_R_WMAC_SECOND_CCA_TIMER_8822B)
+#define BIT_CLEAR_R_WMAC_SECOND_CCA_TIMER_8822B(x)                             \
+	((x) & (~BITS_R_WMAC_SECOND_CCA_TIMER_8822B))
+#define BIT_GET_R_WMAC_SECOND_CCA_TIMER_8822B(x)                               \
+	(((x) >> BIT_SHIFT_R_WMAC_SECOND_CCA_TIMER_8822B) &                    \
+	 BIT_MASK_R_WMAC_SECOND_CCA_TIMER_8822B)
+#define BIT_SET_R_WMAC_SECOND_CCA_TIMER_8822B(x, v)                            \
+	(BIT_CLEAR_R_WMAC_SECOND_CCA_TIMER_8822B(x) |                          \
+	 BIT_R_WMAC_SECOND_CCA_TIMER_8822B(v))
+
+#define BIT_SHIFT_RFMOD_8822B 7
+#define BIT_MASK_RFMOD_8822B 0x3
+#define BIT_RFMOD_8822B(x)                                                     \
+	(((x) & BIT_MASK_RFMOD_8822B) << BIT_SHIFT_RFMOD_8822B)
+#define BITS_RFMOD_8822B (BIT_MASK_RFMOD_8822B << BIT_SHIFT_RFMOD_8822B)
+#define BIT_CLEAR_RFMOD_8822B(x) ((x) & (~BITS_RFMOD_8822B))
+#define BIT_GET_RFMOD_8822B(x)                                                 \
+	(((x) >> BIT_SHIFT_RFMOD_8822B) & BIT_MASK_RFMOD_8822B)
+#define BIT_SET_RFMOD_8822B(x, v)                                              \
+	(BIT_CLEAR_RFMOD_8822B(x) | BIT_RFMOD_8822B(v))
+
+#define BIT_SHIFT_RESP_CTS_DYNBW_SEL_8822B 5
+#define BIT_MASK_RESP_CTS_DYNBW_SEL_8822B 0x3
+#define BIT_RESP_CTS_DYNBW_SEL_8822B(x)                                        \
+	(((x) & BIT_MASK_RESP_CTS_DYNBW_SEL_8822B)                             \
+	 << BIT_SHIFT_RESP_CTS_DYNBW_SEL_8822B)
+#define BITS_RESP_CTS_DYNBW_SEL_8822B                                          \
+	(BIT_MASK_RESP_CTS_DYNBW_SEL_8822B                                     \
+	 << BIT_SHIFT_RESP_CTS_DYNBW_SEL_8822B)
+#define BIT_CLEAR_RESP_CTS_DYNBW_SEL_8822B(x)                                  \
+	((x) & (~BITS_RESP_CTS_DYNBW_SEL_8822B))
+#define BIT_GET_RESP_CTS_DYNBW_SEL_8822B(x)                                    \
+	(((x) >> BIT_SHIFT_RESP_CTS_DYNBW_SEL_8822B) &                         \
+	 BIT_MASK_RESP_CTS_DYNBW_SEL_8822B)
+#define BIT_SET_RESP_CTS_DYNBW_SEL_8822B(x, v)                                 \
+	(BIT_CLEAR_RESP_CTS_DYNBW_SEL_8822B(x) |                               \
+	 BIT_RESP_CTS_DYNBW_SEL_8822B(v))
+
+#define BIT_DLY_TX_WAIT_RXANTSEL_8822B BIT(4)
+#define BIT_TXRESP_BY_RXANTSEL_8822B BIT(3)
+
+#define BIT_SHIFT_ORIG_DCTS_CHK_8822B 0
+#define BIT_MASK_ORIG_DCTS_CHK_8822B 0x3
+#define BIT_ORIG_DCTS_CHK_8822B(x)                                             \
+	(((x) & BIT_MASK_ORIG_DCTS_CHK_8822B) << BIT_SHIFT_ORIG_DCTS_CHK_8822B)
+#define BITS_ORIG_DCTS_CHK_8822B                                               \
+	(BIT_MASK_ORIG_DCTS_CHK_8822B << BIT_SHIFT_ORIG_DCTS_CHK_8822B)
+#define BIT_CLEAR_ORIG_DCTS_CHK_8822B(x) ((x) & (~BITS_ORIG_DCTS_CHK_8822B))
+#define BIT_GET_ORIG_DCTS_CHK_8822B(x)                                         \
+	(((x) >> BIT_SHIFT_ORIG_DCTS_CHK_8822B) & BIT_MASK_ORIG_DCTS_CHK_8822B)
+#define BIT_SET_ORIG_DCTS_CHK_8822B(x, v)                                      \
+	(BIT_CLEAR_ORIG_DCTS_CHK_8822B(x) | BIT_ORIG_DCTS_CHK_8822B(v))
+
+/* 2 REG_CAMCMD_8822B (CAM COMMAND REGISTER) */
+#define BIT_SECCAM_POLLING_8822B BIT(31)
+#define BIT_SECCAM_CLR_8822B BIT(30)
+#define BIT_MFBCAM_CLR_8822B BIT(29)
+#define BIT_SECCAM_WE_8822B BIT(16)
+
+#define BIT_SHIFT_SECCAM_ADDR_V2_8822B 0
+#define BIT_MASK_SECCAM_ADDR_V2_8822B 0x3ff
+#define BIT_SECCAM_ADDR_V2_8822B(x)                                            \
+	(((x) & BIT_MASK_SECCAM_ADDR_V2_8822B)                                 \
+	 << BIT_SHIFT_SECCAM_ADDR_V2_8822B)
+#define BITS_SECCAM_ADDR_V2_8822B                                              \
+	(BIT_MASK_SECCAM_ADDR_V2_8822B << BIT_SHIFT_SECCAM_ADDR_V2_8822B)
+#define BIT_CLEAR_SECCAM_ADDR_V2_8822B(x) ((x) & (~BITS_SECCAM_ADDR_V2_8822B))
+#define BIT_GET_SECCAM_ADDR_V2_8822B(x)                                        \
+	(((x) >> BIT_SHIFT_SECCAM_ADDR_V2_8822B) &                             \
+	 BIT_MASK_SECCAM_ADDR_V2_8822B)
+#define BIT_SET_SECCAM_ADDR_V2_8822B(x, v)                                     \
+	(BIT_CLEAR_SECCAM_ADDR_V2_8822B(x) | BIT_SECCAM_ADDR_V2_8822B(v))
+
+/* 2 REG_CAMWRITE_8822B (CAM WRITE REGISTER) */
+
+#define BIT_SHIFT_CAMW_DATA_8822B 0
+#define BIT_MASK_CAMW_DATA_8822B 0xffffffffL
+#define BIT_CAMW_DATA_8822B(x)                                                 \
+	(((x) & BIT_MASK_CAMW_DATA_8822B) << BIT_SHIFT_CAMW_DATA_8822B)
+#define BITS_CAMW_DATA_8822B                                                   \
+	(BIT_MASK_CAMW_DATA_8822B << BIT_SHIFT_CAMW_DATA_8822B)
+#define BIT_CLEAR_CAMW_DATA_8822B(x) ((x) & (~BITS_CAMW_DATA_8822B))
+#define BIT_GET_CAMW_DATA_8822B(x)                                             \
+	(((x) >> BIT_SHIFT_CAMW_DATA_8822B) & BIT_MASK_CAMW_DATA_8822B)
+#define BIT_SET_CAMW_DATA_8822B(x, v)                                          \
+	(BIT_CLEAR_CAMW_DATA_8822B(x) | BIT_CAMW_DATA_8822B(v))
+
+/* 2 REG_CAMREAD_8822B (CAM READ REGISTER) */
+
+#define BIT_SHIFT_CAMR_DATA_8822B 0
+#define BIT_MASK_CAMR_DATA_8822B 0xffffffffL
+#define BIT_CAMR_DATA_8822B(x)                                                 \
+	(((x) & BIT_MASK_CAMR_DATA_8822B) << BIT_SHIFT_CAMR_DATA_8822B)
+#define BITS_CAMR_DATA_8822B                                                   \
+	(BIT_MASK_CAMR_DATA_8822B << BIT_SHIFT_CAMR_DATA_8822B)
+#define BIT_CLEAR_CAMR_DATA_8822B(x) ((x) & (~BITS_CAMR_DATA_8822B))
+#define BIT_GET_CAMR_DATA_8822B(x)                                             \
+	(((x) >> BIT_SHIFT_CAMR_DATA_8822B) & BIT_MASK_CAMR_DATA_8822B)
+#define BIT_SET_CAMR_DATA_8822B(x, v)                                          \
+	(BIT_CLEAR_CAMR_DATA_8822B(x) | BIT_CAMR_DATA_8822B(v))
+
+/* 2 REG_CAMDBG_8822B (CAM DEBUG REGISTER) */
+#define BIT_SECCAM_INFO_8822B BIT(31)
+#define BIT_SEC_KEYFOUND_8822B BIT(15)
+
+#define BIT_SHIFT_CAMDBG_SEC_TYPE_8822B 12
+#define BIT_MASK_CAMDBG_SEC_TYPE_8822B 0x7
+#define BIT_CAMDBG_SEC_TYPE_8822B(x)                                           \
+	(((x) & BIT_MASK_CAMDBG_SEC_TYPE_8822B)                                \
+	 << BIT_SHIFT_CAMDBG_SEC_TYPE_8822B)
+#define BITS_CAMDBG_SEC_TYPE_8822B                                             \
+	(BIT_MASK_CAMDBG_SEC_TYPE_8822B << BIT_SHIFT_CAMDBG_SEC_TYPE_8822B)
+#define BIT_CLEAR_CAMDBG_SEC_TYPE_8822B(x) ((x) & (~BITS_CAMDBG_SEC_TYPE_8822B))
+#define BIT_GET_CAMDBG_SEC_TYPE_8822B(x)                                       \
+	(((x) >> BIT_SHIFT_CAMDBG_SEC_TYPE_8822B) &                            \
+	 BIT_MASK_CAMDBG_SEC_TYPE_8822B)
+#define BIT_SET_CAMDBG_SEC_TYPE_8822B(x, v)                                    \
+	(BIT_CLEAR_CAMDBG_SEC_TYPE_8822B(x) | BIT_CAMDBG_SEC_TYPE_8822B(v))
+
+#define BIT_CAMDBG_EXT_SECTYPE_8822B BIT(11)
+
+#define BIT_SHIFT_CAMDBG_MIC_KEY_IDX_8822B 5
+#define BIT_MASK_CAMDBG_MIC_KEY_IDX_8822B 0x1f
+#define BIT_CAMDBG_MIC_KEY_IDX_8822B(x)                                        \
+	(((x) & BIT_MASK_CAMDBG_MIC_KEY_IDX_8822B)                             \
+	 << BIT_SHIFT_CAMDBG_MIC_KEY_IDX_8822B)
+#define BITS_CAMDBG_MIC_KEY_IDX_8822B                                          \
+	(BIT_MASK_CAMDBG_MIC_KEY_IDX_8822B                                     \
+	 << BIT_SHIFT_CAMDBG_MIC_KEY_IDX_8822B)
+#define BIT_CLEAR_CAMDBG_MIC_KEY_IDX_8822B(x)                                  \
+	((x) & (~BITS_CAMDBG_MIC_KEY_IDX_8822B))
+#define BIT_GET_CAMDBG_MIC_KEY_IDX_8822B(x)                                    \
+	(((x) >> BIT_SHIFT_CAMDBG_MIC_KEY_IDX_8822B) &                         \
+	 BIT_MASK_CAMDBG_MIC_KEY_IDX_8822B)
+#define BIT_SET_CAMDBG_MIC_KEY_IDX_8822B(x, v)                                 \
+	(BIT_CLEAR_CAMDBG_MIC_KEY_IDX_8822B(x) |                               \
+	 BIT_CAMDBG_MIC_KEY_IDX_8822B(v))
+
+#define BIT_SHIFT_CAMDBG_SEC_KEY_IDX_8822B 0
+#define BIT_MASK_CAMDBG_SEC_KEY_IDX_8822B 0x1f
+#define BIT_CAMDBG_SEC_KEY_IDX_8822B(x)                                        \
+	(((x) & BIT_MASK_CAMDBG_SEC_KEY_IDX_8822B)                             \
+	 << BIT_SHIFT_CAMDBG_SEC_KEY_IDX_8822B)
+#define BITS_CAMDBG_SEC_KEY_IDX_8822B                                          \
+	(BIT_MASK_CAMDBG_SEC_KEY_IDX_8822B                                     \
+	 << BIT_SHIFT_CAMDBG_SEC_KEY_IDX_8822B)
+#define BIT_CLEAR_CAMDBG_SEC_KEY_IDX_8822B(x)                                  \
+	((x) & (~BITS_CAMDBG_SEC_KEY_IDX_8822B))
+#define BIT_GET_CAMDBG_SEC_KEY_IDX_8822B(x)                                    \
+	(((x) >> BIT_SHIFT_CAMDBG_SEC_KEY_IDX_8822B) &                         \
+	 BIT_MASK_CAMDBG_SEC_KEY_IDX_8822B)
+#define BIT_SET_CAMDBG_SEC_KEY_IDX_8822B(x, v)                                 \
+	(BIT_CLEAR_CAMDBG_SEC_KEY_IDX_8822B(x) |                               \
+	 BIT_CAMDBG_SEC_KEY_IDX_8822B(v))
+
+/* 2 REG_RXFILTER_ACTION_1_8822B */
+
+#define BIT_SHIFT_RXFILTER_ACTION_1_8822B 0
+#define BIT_MASK_RXFILTER_ACTION_1_8822B 0xff
+#define BIT_RXFILTER_ACTION_1_8822B(x)                                         \
+	(((x) & BIT_MASK_RXFILTER_ACTION_1_8822B)                              \
+	 << BIT_SHIFT_RXFILTER_ACTION_1_8822B)
+#define BITS_RXFILTER_ACTION_1_8822B                                           \
+	(BIT_MASK_RXFILTER_ACTION_1_8822B << BIT_SHIFT_RXFILTER_ACTION_1_8822B)
+#define BIT_CLEAR_RXFILTER_ACTION_1_8822B(x)                                   \
+	((x) & (~BITS_RXFILTER_ACTION_1_8822B))
+#define BIT_GET_RXFILTER_ACTION_1_8822B(x)                                     \
+	(((x) >> BIT_SHIFT_RXFILTER_ACTION_1_8822B) &                          \
+	 BIT_MASK_RXFILTER_ACTION_1_8822B)
+#define BIT_SET_RXFILTER_ACTION_1_8822B(x, v)                                  \
+	(BIT_CLEAR_RXFILTER_ACTION_1_8822B(x) | BIT_RXFILTER_ACTION_1_8822B(v))
+
+/* 2 REG_RXFILTER_CATEGORY_1_8822B */
+
+#define BIT_SHIFT_RXFILTER_CATEGORY_1_8822B 0
+#define BIT_MASK_RXFILTER_CATEGORY_1_8822B 0xff
+#define BIT_RXFILTER_CATEGORY_1_8822B(x)                                       \
+	(((x) & BIT_MASK_RXFILTER_CATEGORY_1_8822B)                            \
+	 << BIT_SHIFT_RXFILTER_CATEGORY_1_8822B)
+#define BITS_RXFILTER_CATEGORY_1_8822B                                         \
+	(BIT_MASK_RXFILTER_CATEGORY_1_8822B                                    \
+	 << BIT_SHIFT_RXFILTER_CATEGORY_1_8822B)
+#define BIT_CLEAR_RXFILTER_CATEGORY_1_8822B(x)                                 \
+	((x) & (~BITS_RXFILTER_CATEGORY_1_8822B))
+#define BIT_GET_RXFILTER_CATEGORY_1_8822B(x)                                   \
+	(((x) >> BIT_SHIFT_RXFILTER_CATEGORY_1_8822B) &                        \
+	 BIT_MASK_RXFILTER_CATEGORY_1_8822B)
+#define BIT_SET_RXFILTER_CATEGORY_1_8822B(x, v)                                \
+	(BIT_CLEAR_RXFILTER_CATEGORY_1_8822B(x) |                              \
+	 BIT_RXFILTER_CATEGORY_1_8822B(v))
+
+/* 2 REG_SECCFG_8822B (SECURITY CONFIGURATION REGISTER) */
+#define BIT_DIS_GCLK_WAPI_8822B BIT(15)
+#define BIT_DIS_GCLK_AES_8822B BIT(14)
+#define BIT_DIS_GCLK_TKIP_8822B BIT(13)
+#define BIT_AES_SEL_QC_1_8822B BIT(12)
+#define BIT_AES_SEL_QC_0_8822B BIT(11)
+#define BIT_CHK_BMC_8822B BIT(9)
+#define BIT_CHK_KEYID_8822B BIT(8)
+#define BIT_RXBCUSEDK_8822B BIT(7)
+#define BIT_TXBCUSEDK_8822B BIT(6)
+#define BIT_NOSKMC_8822B BIT(5)
+#define BIT_SKBYA2_8822B BIT(4)
+#define BIT_RXDEC_8822B BIT(3)
+#define BIT_TXENC_8822B BIT(2)
+#define BIT_RXUHUSEDK_8822B BIT(1)
+#define BIT_TXUHUSEDK_8822B BIT(0)
+
+/* 2 REG_RXFILTER_ACTION_3_8822B */
+
+#define BIT_SHIFT_RXFILTER_ACTION_3_8822B 0
+#define BIT_MASK_RXFILTER_ACTION_3_8822B 0xff
+#define BIT_RXFILTER_ACTION_3_8822B(x)                                         \
+	(((x) & BIT_MASK_RXFILTER_ACTION_3_8822B)                              \
+	 << BIT_SHIFT_RXFILTER_ACTION_3_8822B)
+#define BITS_RXFILTER_ACTION_3_8822B                                           \
+	(BIT_MASK_RXFILTER_ACTION_3_8822B << BIT_SHIFT_RXFILTER_ACTION_3_8822B)
+#define BIT_CLEAR_RXFILTER_ACTION_3_8822B(x)                                   \
+	((x) & (~BITS_RXFILTER_ACTION_3_8822B))
+#define BIT_GET_RXFILTER_ACTION_3_8822B(x)                                     \
+	(((x) >> BIT_SHIFT_RXFILTER_ACTION_3_8822B) &                          \
+	 BIT_MASK_RXFILTER_ACTION_3_8822B)
+#define BIT_SET_RXFILTER_ACTION_3_8822B(x, v)                                  \
+	(BIT_CLEAR_RXFILTER_ACTION_3_8822B(x) | BIT_RXFILTER_ACTION_3_8822B(v))
+
+/* 2 REG_RXFILTER_CATEGORY_3_8822B */
+
+#define BIT_SHIFT_RXFILTER_CATEGORY_3_8822B 0
+#define BIT_MASK_RXFILTER_CATEGORY_3_8822B 0xff
+#define BIT_RXFILTER_CATEGORY_3_8822B(x)                                       \
+	(((x) & BIT_MASK_RXFILTER_CATEGORY_3_8822B)                            \
+	 << BIT_SHIFT_RXFILTER_CATEGORY_3_8822B)
+#define BITS_RXFILTER_CATEGORY_3_8822B                                         \
+	(BIT_MASK_RXFILTER_CATEGORY_3_8822B                                    \
+	 << BIT_SHIFT_RXFILTER_CATEGORY_3_8822B)
+#define BIT_CLEAR_RXFILTER_CATEGORY_3_8822B(x)                                 \
+	((x) & (~BITS_RXFILTER_CATEGORY_3_8822B))
+#define BIT_GET_RXFILTER_CATEGORY_3_8822B(x)                                   \
+	(((x) >> BIT_SHIFT_RXFILTER_CATEGORY_3_8822B) &                        \
+	 BIT_MASK_RXFILTER_CATEGORY_3_8822B)
+#define BIT_SET_RXFILTER_CATEGORY_3_8822B(x, v)                                \
+	(BIT_CLEAR_RXFILTER_CATEGORY_3_8822B(x) |                              \
+	 BIT_RXFILTER_CATEGORY_3_8822B(v))
+
+/* 2 REG_RXFILTER_ACTION_2_8822B */
+
+#define BIT_SHIFT_RXFILTER_ACTION_2_8822B 0
+#define BIT_MASK_RXFILTER_ACTION_2_8822B 0xff
+#define BIT_RXFILTER_ACTION_2_8822B(x)                                         \
+	(((x) & BIT_MASK_RXFILTER_ACTION_2_8822B)                              \
+	 << BIT_SHIFT_RXFILTER_ACTION_2_8822B)
+#define BITS_RXFILTER_ACTION_2_8822B                                           \
+	(BIT_MASK_RXFILTER_ACTION_2_8822B << BIT_SHIFT_RXFILTER_ACTION_2_8822B)
+#define BIT_CLEAR_RXFILTER_ACTION_2_8822B(x)                                   \
+	((x) & (~BITS_RXFILTER_ACTION_2_8822B))
+#define BIT_GET_RXFILTER_ACTION_2_8822B(x)                                     \
+	(((x) >> BIT_SHIFT_RXFILTER_ACTION_2_8822B) &                          \
+	 BIT_MASK_RXFILTER_ACTION_2_8822B)
+#define BIT_SET_RXFILTER_ACTION_2_8822B(x, v)                                  \
+	(BIT_CLEAR_RXFILTER_ACTION_2_8822B(x) | BIT_RXFILTER_ACTION_2_8822B(v))
+
+/* 2 REG_RXFILTER_CATEGORY_2_8822B */
+
+#define BIT_SHIFT_RXFILTER_CATEGORY_2_8822B 0
+#define BIT_MASK_RXFILTER_CATEGORY_2_8822B 0xff
+#define BIT_RXFILTER_CATEGORY_2_8822B(x)                                       \
+	(((x) & BIT_MASK_RXFILTER_CATEGORY_2_8822B)                            \
+	 << BIT_SHIFT_RXFILTER_CATEGORY_2_8822B)
+#define BITS_RXFILTER_CATEGORY_2_8822B                                         \
+	(BIT_MASK_RXFILTER_CATEGORY_2_8822B                                    \
+	 << BIT_SHIFT_RXFILTER_CATEGORY_2_8822B)
+#define BIT_CLEAR_RXFILTER_CATEGORY_2_8822B(x)                                 \
+	((x) & (~BITS_RXFILTER_CATEGORY_2_8822B))
+#define BIT_GET_RXFILTER_CATEGORY_2_8822B(x)                                   \
+	(((x) >> BIT_SHIFT_RXFILTER_CATEGORY_2_8822B) &                        \
+	 BIT_MASK_RXFILTER_CATEGORY_2_8822B)
+#define BIT_SET_RXFILTER_CATEGORY_2_8822B(x, v)                                \
+	(BIT_CLEAR_RXFILTER_CATEGORY_2_8822B(x) |                              \
+	 BIT_RXFILTER_CATEGORY_2_8822B(v))
+
+/* 2 REG_RXFLTMAP4_8822B (RX FILTER MAP GROUP 4) */
+#define BIT_CTRLFLT15EN_FW_8822B BIT(15)
+#define BIT_CTRLFLT14EN_FW_8822B BIT(14)
+#define BIT_CTRLFLT13EN_FW_8822B BIT(13)
+#define BIT_CTRLFLT12EN_FW_8822B BIT(12)
+#define BIT_CTRLFLT11EN_FW_8822B BIT(11)
+#define BIT_CTRLFLT10EN_FW_8822B BIT(10)
+#define BIT_CTRLFLT9EN_FW_8822B BIT(9)
+#define BIT_CTRLFLT8EN_FW_8822B BIT(8)
+#define BIT_CTRLFLT7EN_FW_8822B BIT(7)
+#define BIT_CTRLFLT6EN_FW_8822B BIT(6)
+#define BIT_CTRLFLT5EN_FW_8822B BIT(5)
+#define BIT_CTRLFLT4EN_FW_8822B BIT(4)
+#define BIT_CTRLFLT3EN_FW_8822B BIT(3)
+#define BIT_CTRLFLT2EN_FW_8822B BIT(2)
+#define BIT_CTRLFLT1EN_FW_8822B BIT(1)
+#define BIT_CTRLFLT0EN_FW_8822B BIT(0)
+
+/* 2 REG_RXFLTMAP3_8822B (RX FILTER MAP GROUP 3) */
+#define BIT_MGTFLT15EN_FW_8822B BIT(15)
+#define BIT_MGTFLT14EN_FW_8822B BIT(14)
+#define BIT_MGTFLT13EN_FW_8822B BIT(13)
+#define BIT_MGTFLT12EN_FW_8822B BIT(12)
+#define BIT_MGTFLT11EN_FW_8822B BIT(11)
+#define BIT_MGTFLT10EN_FW_8822B BIT(10)
+#define BIT_MGTFLT9EN_FW_8822B BIT(9)
+#define BIT_MGTFLT8EN_FW_8822B BIT(8)
+#define BIT_MGTFLT7EN_FW_8822B BIT(7)
+#define BIT_MGTFLT6EN_FW_8822B BIT(6)
+#define BIT_MGTFLT5EN_FW_8822B BIT(5)
+#define BIT_MGTFLT4EN_FW_8822B BIT(4)
+#define BIT_MGTFLT3EN_FW_8822B BIT(3)
+#define BIT_MGTFLT2EN_FW_8822B BIT(2)
+#define BIT_MGTFLT1EN_FW_8822B BIT(1)
+#define BIT_MGTFLT0EN_FW_8822B BIT(0)
+
+/* 2 REG_RXFLTMAP6_8822B (RX FILTER MAP GROUP 6) */
+#define BIT_ACTIONFLT15EN_FW_8822B BIT(15)
+#define BIT_ACTIONFLT14EN_FW_8822B BIT(14)
+#define BIT_ACTIONFLT13EN_FW_8822B BIT(13)
+#define BIT_ACTIONFLT12EN_FW_8822B BIT(12)
+#define BIT_ACTIONFLT11EN_FW_8822B BIT(11)
+#define BIT_ACTIONFLT10EN_FW_8822B BIT(10)
+#define BIT_ACTIONFLT9EN_FW_8822B BIT(9)
+#define BIT_ACTIONFLT8EN_FW_8822B BIT(8)
+#define BIT_ACTIONFLT7EN_FW_8822B BIT(7)
+#define BIT_ACTIONFLT6EN_FW_8822B BIT(6)
+#define BIT_ACTIONFLT5EN_FW_8822B BIT(5)
+#define BIT_ACTIONFLT4EN_FW_8822B BIT(4)
+#define BIT_ACTIONFLT3EN_FW_8822B BIT(3)
+#define BIT_ACTIONFLT2EN_FW_8822B BIT(2)
+#define BIT_ACTIONFLT1EN_FW_8822B BIT(1)
+#define BIT_ACTIONFLT0EN_FW_8822B BIT(0)
+
+/* 2 REG_RXFLTMAP5_8822B (RX FILTER MAP GROUP 5) */
+#define BIT_DATAFLT15EN_FW_8822B BIT(15)
+#define BIT_DATAFLT14EN_FW_8822B BIT(14)
+#define BIT_DATAFLT13EN_FW_8822B BIT(13)
+#define BIT_DATAFLT12EN_FW_8822B BIT(12)
+#define BIT_DATAFLT11EN_FW_8822B BIT(11)
+#define BIT_DATAFLT10EN_FW_8822B BIT(10)
+#define BIT_DATAFLT9EN_FW_8822B BIT(9)
+#define BIT_DATAFLT8EN_FW_8822B BIT(8)
+#define BIT_DATAFLT7EN_FW_8822B BIT(7)
+#define BIT_DATAFLT6EN_FW_8822B BIT(6)
+#define BIT_DATAFLT5EN_FW_8822B BIT(5)
+#define BIT_DATAFLT4EN_FW_8822B BIT(4)
+#define BIT_DATAFLT3EN_FW_8822B BIT(3)
+#define BIT_DATAFLT2EN_FW_8822B BIT(2)
+#define BIT_DATAFLT1EN_FW_8822B BIT(1)
+#define BIT_DATAFLT0EN_FW_8822B BIT(0)
+
+/* 2 REG_WMMPS_UAPSD_TID_8822B (WMM POWER SAVE UAPSD TID REGISTER) */
+#define BIT_WMMPS_UAPSD_TID7_8822B BIT(7)
+#define BIT_WMMPS_UAPSD_TID6_8822B BIT(6)
+#define BIT_WMMPS_UAPSD_TID5_8822B BIT(5)
+#define BIT_WMMPS_UAPSD_TID4_8822B BIT(4)
+#define BIT_WMMPS_UAPSD_TID3_8822B BIT(3)
+#define BIT_WMMPS_UAPSD_TID2_8822B BIT(2)
+#define BIT_WMMPS_UAPSD_TID1_8822B BIT(1)
+#define BIT_WMMPS_UAPSD_TID0_8822B BIT(0)
+
+/* 2 REG_PS_RX_INFO_8822B (POWER SAVE RX INFORMATION REGISTER) */
+
+#define BIT_SHIFT_PORTSEL__PS_RX_INFO_8822B 5
+#define BIT_MASK_PORTSEL__PS_RX_INFO_8822B 0x7
+#define BIT_PORTSEL__PS_RX_INFO_8822B(x)                                       \
+	(((x) & BIT_MASK_PORTSEL__PS_RX_INFO_8822B)                            \
+	 << BIT_SHIFT_PORTSEL__PS_RX_INFO_8822B)
+#define BITS_PORTSEL__PS_RX_INFO_8822B                                         \
+	(BIT_MASK_PORTSEL__PS_RX_INFO_8822B                                    \
+	 << BIT_SHIFT_PORTSEL__PS_RX_INFO_8822B)
+#define BIT_CLEAR_PORTSEL__PS_RX_INFO_8822B(x)                                 \
+	((x) & (~BITS_PORTSEL__PS_RX_INFO_8822B))
+#define BIT_GET_PORTSEL__PS_RX_INFO_8822B(x)                                   \
+	(((x) >> BIT_SHIFT_PORTSEL__PS_RX_INFO_8822B) &                        \
+	 BIT_MASK_PORTSEL__PS_RX_INFO_8822B)
+#define BIT_SET_PORTSEL__PS_RX_INFO_8822B(x, v)                                \
+	(BIT_CLEAR_PORTSEL__PS_RX_INFO_8822B(x) |                              \
+	 BIT_PORTSEL__PS_RX_INFO_8822B(v))
+
+#define BIT_RXCTRLIN0_8822B BIT(4)
+#define BIT_RXMGTIN0_8822B BIT(3)
+#define BIT_RXDATAIN2_8822B BIT(2)
+#define BIT_RXDATAIN1_8822B BIT(1)
+#define BIT_RXDATAIN0_8822B BIT(0)
+
+/* 2 REG_NAN_RX_TSF_FILTER_8822B(NAN_RX_TSF_ADDRESS_FILTER) */
+#define BIT_CHK_TSF_TA_8822B BIT(2)
+#define BIT_CHK_TSF_CBSSID_8822B BIT(1)
+#define BIT_CHK_TSF_EN_8822B BIT(0)
+
+/* 2 REG_WOW_CTRL_8822B (WAKE ON WLAN CONTROL REGISTER) */
+
+#define BIT_SHIFT_PSF_BSSIDSEL_B2B1_8822B 6
+#define BIT_MASK_PSF_BSSIDSEL_B2B1_8822B 0x3
+#define BIT_PSF_BSSIDSEL_B2B1_8822B(x)                                         \
+	(((x) & BIT_MASK_PSF_BSSIDSEL_B2B1_8822B)                              \
+	 << BIT_SHIFT_PSF_BSSIDSEL_B2B1_8822B)
+#define BITS_PSF_BSSIDSEL_B2B1_8822B                                           \
+	(BIT_MASK_PSF_BSSIDSEL_B2B1_8822B << BIT_SHIFT_PSF_BSSIDSEL_B2B1_8822B)
+#define BIT_CLEAR_PSF_BSSIDSEL_B2B1_8822B(x)                                   \
+	((x) & (~BITS_PSF_BSSIDSEL_B2B1_8822B))
+#define BIT_GET_PSF_BSSIDSEL_B2B1_8822B(x)                                     \
+	(((x) >> BIT_SHIFT_PSF_BSSIDSEL_B2B1_8822B) &                          \
+	 BIT_MASK_PSF_BSSIDSEL_B2B1_8822B)
+#define BIT_SET_PSF_BSSIDSEL_B2B1_8822B(x, v)                                  \
+	(BIT_CLEAR_PSF_BSSIDSEL_B2B1_8822B(x) | BIT_PSF_BSSIDSEL_B2B1_8822B(v))
+
+#define BIT_WOWHCI_8822B BIT(5)
+#define BIT_PSF_BSSIDSEL_B0_8822B BIT(4)
+#define BIT_UWF_8822B BIT(3)
+#define BIT_MAGIC_8822B BIT(2)
+#define BIT_WOWEN_8822B BIT(1)
+#define BIT_FORCE_WAKEUP_8822B BIT(0)
+
+/* 2 REG_LPNAV_CTRL_8822B (LOW POWER NAV CONTROL REGISTER) */
+#define BIT_LPNAV_EN_8822B BIT(31)
+
+#define BIT_SHIFT_LPNAV_EARLY_8822B 16
+#define BIT_MASK_LPNAV_EARLY_8822B 0x7fff
+#define BIT_LPNAV_EARLY_8822B(x)                                               \
+	(((x) & BIT_MASK_LPNAV_EARLY_8822B) << BIT_SHIFT_LPNAV_EARLY_8822B)
+#define BITS_LPNAV_EARLY_8822B                                                 \
+	(BIT_MASK_LPNAV_EARLY_8822B << BIT_SHIFT_LPNAV_EARLY_8822B)
+#define BIT_CLEAR_LPNAV_EARLY_8822B(x) ((x) & (~BITS_LPNAV_EARLY_8822B))
+#define BIT_GET_LPNAV_EARLY_8822B(x)                                           \
+	(((x) >> BIT_SHIFT_LPNAV_EARLY_8822B) & BIT_MASK_LPNAV_EARLY_8822B)
+#define BIT_SET_LPNAV_EARLY_8822B(x, v)                                        \
+	(BIT_CLEAR_LPNAV_EARLY_8822B(x) | BIT_LPNAV_EARLY_8822B(v))
+
+#define BIT_SHIFT_LPNAV_TH_8822B 0
+#define BIT_MASK_LPNAV_TH_8822B 0xffff
+#define BIT_LPNAV_TH_8822B(x)                                                  \
+	(((x) & BIT_MASK_LPNAV_TH_8822B) << BIT_SHIFT_LPNAV_TH_8822B)
+#define BITS_LPNAV_TH_8822B                                                    \
+	(BIT_MASK_LPNAV_TH_8822B << BIT_SHIFT_LPNAV_TH_8822B)
+#define BIT_CLEAR_LPNAV_TH_8822B(x) ((x) & (~BITS_LPNAV_TH_8822B))
+#define BIT_GET_LPNAV_TH_8822B(x)                                              \
+	(((x) >> BIT_SHIFT_LPNAV_TH_8822B) & BIT_MASK_LPNAV_TH_8822B)
+#define BIT_SET_LPNAV_TH_8822B(x, v)                                           \
+	(BIT_CLEAR_LPNAV_TH_8822B(x) | BIT_LPNAV_TH_8822B(v))
+
+/* 2 REG_WKFMCAM_CMD_8822B (WAKEUP FRAME CAM COMMAND REGISTER) */
+#define BIT_WKFCAM_POLLING_V1_8822B BIT(31)
+#define BIT_WKFCAM_CLR_V1_8822B BIT(30)
+#define BIT_WKFCAM_WE_8822B BIT(16)
+
+#define BIT_SHIFT_WKFCAM_ADDR_V2_8822B 8
+#define BIT_MASK_WKFCAM_ADDR_V2_8822B 0xff
+#define BIT_WKFCAM_ADDR_V2_8822B(x)                                            \
+	(((x) & BIT_MASK_WKFCAM_ADDR_V2_8822B)                                 \
+	 << BIT_SHIFT_WKFCAM_ADDR_V2_8822B)
+#define BITS_WKFCAM_ADDR_V2_8822B                                              \
+	(BIT_MASK_WKFCAM_ADDR_V2_8822B << BIT_SHIFT_WKFCAM_ADDR_V2_8822B)
+#define BIT_CLEAR_WKFCAM_ADDR_V2_8822B(x) ((x) & (~BITS_WKFCAM_ADDR_V2_8822B))
+#define BIT_GET_WKFCAM_ADDR_V2_8822B(x)                                        \
+	(((x) >> BIT_SHIFT_WKFCAM_ADDR_V2_8822B) &                             \
+	 BIT_MASK_WKFCAM_ADDR_V2_8822B)
+#define BIT_SET_WKFCAM_ADDR_V2_8822B(x, v)                                     \
+	(BIT_CLEAR_WKFCAM_ADDR_V2_8822B(x) | BIT_WKFCAM_ADDR_V2_8822B(v))
+
+#define BIT_SHIFT_WKFCAM_CAM_NUM_V1_8822B 0
+#define BIT_MASK_WKFCAM_CAM_NUM_V1_8822B 0xff
+#define BIT_WKFCAM_CAM_NUM_V1_8822B(x)                                         \
+	(((x) & BIT_MASK_WKFCAM_CAM_NUM_V1_8822B)                              \
+	 << BIT_SHIFT_WKFCAM_CAM_NUM_V1_8822B)
+#define BITS_WKFCAM_CAM_NUM_V1_8822B                                           \
+	(BIT_MASK_WKFCAM_CAM_NUM_V1_8822B << BIT_SHIFT_WKFCAM_CAM_NUM_V1_8822B)
+#define BIT_CLEAR_WKFCAM_CAM_NUM_V1_8822B(x)                                   \
+	((x) & (~BITS_WKFCAM_CAM_NUM_V1_8822B))
+#define BIT_GET_WKFCAM_CAM_NUM_V1_8822B(x)                                     \
+	(((x) >> BIT_SHIFT_WKFCAM_CAM_NUM_V1_8822B) &                          \
+	 BIT_MASK_WKFCAM_CAM_NUM_V1_8822B)
+#define BIT_SET_WKFCAM_CAM_NUM_V1_8822B(x, v)                                  \
+	(BIT_CLEAR_WKFCAM_CAM_NUM_V1_8822B(x) | BIT_WKFCAM_CAM_NUM_V1_8822B(v))
+
+/* 2 REG_WKFMCAM_RWD_8822B (WAKEUP FRAME READ/WRITE DATA) */
+
+#define BIT_SHIFT_WKFMCAM_RWD_8822B 0
+#define BIT_MASK_WKFMCAM_RWD_8822B 0xffffffffL
+#define BIT_WKFMCAM_RWD_8822B(x)                                               \
+	(((x) & BIT_MASK_WKFMCAM_RWD_8822B) << BIT_SHIFT_WKFMCAM_RWD_8822B)
+#define BITS_WKFMCAM_RWD_8822B                                                 \
+	(BIT_MASK_WKFMCAM_RWD_8822B << BIT_SHIFT_WKFMCAM_RWD_8822B)
+#define BIT_CLEAR_WKFMCAM_RWD_8822B(x) ((x) & (~BITS_WKFMCAM_RWD_8822B))
+#define BIT_GET_WKFMCAM_RWD_8822B(x)                                           \
+	(((x) >> BIT_SHIFT_WKFMCAM_RWD_8822B) & BIT_MASK_WKFMCAM_RWD_8822B)
+#define BIT_SET_WKFMCAM_RWD_8822B(x, v)                                        \
+	(BIT_CLEAR_WKFMCAM_RWD_8822B(x) | BIT_WKFMCAM_RWD_8822B(v))
+
+/* 2 REG_RXFLTMAP1_8822B (RX FILTER MAP GROUP 1) */
+#define BIT_CTRLFLT15EN_8822B BIT(15)
+#define BIT_CTRLFLT14EN_8822B BIT(14)
+#define BIT_CTRLFLT13EN_8822B BIT(13)
+#define BIT_CTRLFLT12EN_8822B BIT(12)
+#define BIT_CTRLFLT11EN_8822B BIT(11)
+#define BIT_CTRLFLT10EN_8822B BIT(10)
+#define BIT_CTRLFLT9EN_8822B BIT(9)
+#define BIT_CTRLFLT8EN_8822B BIT(8)
+#define BIT_CTRLFLT7EN_8822B BIT(7)
+#define BIT_CTRLFLT6EN_8822B BIT(6)
+#define BIT_CTRLFLT5EN_8822B BIT(5)
+#define BIT_CTRLFLT4EN_8822B BIT(4)
+#define BIT_CTRLFLT3EN_8822B BIT(3)
+#define BIT_CTRLFLT2EN_8822B BIT(2)
+#define BIT_CTRLFLT1EN_8822B BIT(1)
+#define BIT_CTRLFLT0EN_8822B BIT(0)
+
+/* 2 REG_RXFLTMAP0_8822B (RX FILTER MAP GROUP 0) */
+#define BIT_MGTFLT15EN_8822B BIT(15)
+#define BIT_MGTFLT14EN_8822B BIT(14)
+#define BIT_MGTFLT13EN_8822B BIT(13)
+#define BIT_MGTFLT12EN_8822B BIT(12)
+#define BIT_MGTFLT11EN_8822B BIT(11)
+#define BIT_MGTFLT10EN_8822B BIT(10)
+#define BIT_MGTFLT9EN_8822B BIT(9)
+#define BIT_MGTFLT8EN_8822B BIT(8)
+#define BIT_MGTFLT7EN_8822B BIT(7)
+#define BIT_MGTFLT6EN_8822B BIT(6)
+#define BIT_MGTFLT5EN_8822B BIT(5)
+#define BIT_MGTFLT4EN_8822B BIT(4)
+#define BIT_MGTFLT3EN_8822B BIT(3)
+#define BIT_MGTFLT2EN_8822B BIT(2)
+#define BIT_MGTFLT1EN_8822B BIT(1)
+#define BIT_MGTFLT0EN_8822B BIT(0)
+
+/* 2 REG_NOT_VALID_8822B */
+
+/* 2 REG_RXFLTMAP2_8822B (RX FILTER MAP GROUP 2) */
+#define BIT_DATAFLT15EN_8822B BIT(15)
+#define BIT_DATAFLT14EN_8822B BIT(14)
+#define BIT_DATAFLT13EN_8822B BIT(13)
+#define BIT_DATAFLT12EN_8822B BIT(12)
+#define BIT_DATAFLT11EN_8822B BIT(11)
+#define BIT_DATAFLT10EN_8822B BIT(10)
+#define BIT_DATAFLT9EN_8822B BIT(9)
+#define BIT_DATAFLT8EN_8822B BIT(8)
+#define BIT_DATAFLT7EN_8822B BIT(7)
+#define BIT_DATAFLT6EN_8822B BIT(6)
+#define BIT_DATAFLT5EN_8822B BIT(5)
+#define BIT_DATAFLT4EN_8822B BIT(4)
+#define BIT_DATAFLT3EN_8822B BIT(3)
+#define BIT_DATAFLT2EN_8822B BIT(2)
+#define BIT_DATAFLT1EN_8822B BIT(1)
+#define BIT_DATAFLT0EN_8822B BIT(0)
+
+/* 2 REG_BCN_PSR_RPT_8822B (BEACON PARSER REPORT REGISTER) */
+
+#define BIT_SHIFT_DTIM_CNT_8822B 24
+#define BIT_MASK_DTIM_CNT_8822B 0xff
+#define BIT_DTIM_CNT_8822B(x)                                                  \
+	(((x) & BIT_MASK_DTIM_CNT_8822B) << BIT_SHIFT_DTIM_CNT_8822B)
+#define BITS_DTIM_CNT_8822B                                                    \
+	(BIT_MASK_DTIM_CNT_8822B << BIT_SHIFT_DTIM_CNT_8822B)
+#define BIT_CLEAR_DTIM_CNT_8822B(x) ((x) & (~BITS_DTIM_CNT_8822B))
+#define BIT_GET_DTIM_CNT_8822B(x)                                              \
+	(((x) >> BIT_SHIFT_DTIM_CNT_8822B) & BIT_MASK_DTIM_CNT_8822B)
+#define BIT_SET_DTIM_CNT_8822B(x, v)                                           \
+	(BIT_CLEAR_DTIM_CNT_8822B(x) | BIT_DTIM_CNT_8822B(v))
+
+#define BIT_SHIFT_DTIM_PERIOD_8822B 16
+#define BIT_MASK_DTIM_PERIOD_8822B 0xff
+#define BIT_DTIM_PERIOD_8822B(x)                                               \
+	(((x) & BIT_MASK_DTIM_PERIOD_8822B) << BIT_SHIFT_DTIM_PERIOD_8822B)
+#define BITS_DTIM_PERIOD_8822B                                                 \
+	(BIT_MASK_DTIM_PERIOD_8822B << BIT_SHIFT_DTIM_PERIOD_8822B)
+#define BIT_CLEAR_DTIM_PERIOD_8822B(x) ((x) & (~BITS_DTIM_PERIOD_8822B))
+#define BIT_GET_DTIM_PERIOD_8822B(x)                                           \
+	(((x) >> BIT_SHIFT_DTIM_PERIOD_8822B) & BIT_MASK_DTIM_PERIOD_8822B)
+#define BIT_SET_DTIM_PERIOD_8822B(x, v)                                        \
+	(BIT_CLEAR_DTIM_PERIOD_8822B(x) | BIT_DTIM_PERIOD_8822B(v))
+
+#define BIT_DTIM_8822B BIT(15)
+#define BIT_TIM_8822B BIT(14)
+
+#define BIT_SHIFT_PS_AID_0_8822B 0
+#define BIT_MASK_PS_AID_0_8822B 0x7ff
+#define BIT_PS_AID_0_8822B(x)                                                  \
+	(((x) & BIT_MASK_PS_AID_0_8822B) << BIT_SHIFT_PS_AID_0_8822B)
+#define BITS_PS_AID_0_8822B                                                    \
+	(BIT_MASK_PS_AID_0_8822B << BIT_SHIFT_PS_AID_0_8822B)
+#define BIT_CLEAR_PS_AID_0_8822B(x) ((x) & (~BITS_PS_AID_0_8822B))
+#define BIT_GET_PS_AID_0_8822B(x)                                              \
+	(((x) >> BIT_SHIFT_PS_AID_0_8822B) & BIT_MASK_PS_AID_0_8822B)
+#define BIT_SET_PS_AID_0_8822B(x, v)                                           \
+	(BIT_CLEAR_PS_AID_0_8822B(x) | BIT_PS_AID_0_8822B(v))
+
+/* 2 REG_FLC_TRPC_8822B (TIMER OF FLC_RPC) */
+#define BIT_FLC_RPCT_V1_8822B BIT(7)
+#define BIT_MODE_8822B BIT(6)
+
+#define BIT_SHIFT_TRPCD_8822B 0
+#define BIT_MASK_TRPCD_8822B 0x3f
+#define BIT_TRPCD_8822B(x)                                                     \
+	(((x) & BIT_MASK_TRPCD_8822B) << BIT_SHIFT_TRPCD_8822B)
+#define BITS_TRPCD_8822B (BIT_MASK_TRPCD_8822B << BIT_SHIFT_TRPCD_8822B)
+#define BIT_CLEAR_TRPCD_8822B(x) ((x) & (~BITS_TRPCD_8822B))
+#define BIT_GET_TRPCD_8822B(x)                                                 \
+	(((x) >> BIT_SHIFT_TRPCD_8822B) & BIT_MASK_TRPCD_8822B)
+#define BIT_SET_TRPCD_8822B(x, v)                                              \
+	(BIT_CLEAR_TRPCD_8822B(x) | BIT_TRPCD_8822B(v))
+
+/* 2 REG_FLC_PTS_8822B (PKT TYPE SELECTION OF FLC_RPC T) */
+#define BIT_CMF_8822B BIT(2)
+#define BIT_CCF_8822B BIT(1)
+#define BIT_CDF_8822B BIT(0)
+
+/* 2 REG_FLC_RPCT_8822B (FLC_RPC THRESHOLD) */
+
+#define BIT_SHIFT_FLC_RPCT_8822B 0
+#define BIT_MASK_FLC_RPCT_8822B 0xff
+#define BIT_FLC_RPCT_8822B(x)                                                  \
+	(((x) & BIT_MASK_FLC_RPCT_8822B) << BIT_SHIFT_FLC_RPCT_8822B)
+#define BITS_FLC_RPCT_8822B                                                    \
+	(BIT_MASK_FLC_RPCT_8822B << BIT_SHIFT_FLC_RPCT_8822B)
+#define BIT_CLEAR_FLC_RPCT_8822B(x) ((x) & (~BITS_FLC_RPCT_8822B))
+#define BIT_GET_FLC_RPCT_8822B(x)                                              \
+	(((x) >> BIT_SHIFT_FLC_RPCT_8822B) & BIT_MASK_FLC_RPCT_8822B)
+#define BIT_SET_FLC_RPCT_8822B(x, v)                                           \
+	(BIT_CLEAR_FLC_RPCT_8822B(x) | BIT_FLC_RPCT_8822B(v))
+
+/* 2 REG_FLC_RPC_8822B (FW LPS CONDITION -- RX PKT COUNTER) */
+
+#define BIT_SHIFT_FLC_RPC_8822B 0
+#define BIT_MASK_FLC_RPC_8822B 0xff
+#define BIT_FLC_RPC_8822B(x)                                                   \
+	(((x) & BIT_MASK_FLC_RPC_8822B) << BIT_SHIFT_FLC_RPC_8822B)
+#define BITS_FLC_RPC_8822B (BIT_MASK_FLC_RPC_8822B << BIT_SHIFT_FLC_RPC_8822B)
+#define BIT_CLEAR_FLC_RPC_8822B(x) ((x) & (~BITS_FLC_RPC_8822B))
+#define BIT_GET_FLC_RPC_8822B(x)                                               \
+	(((x) >> BIT_SHIFT_FLC_RPC_8822B) & BIT_MASK_FLC_RPC_8822B)
+#define BIT_SET_FLC_RPC_8822B(x, v)                                            \
+	(BIT_CLEAR_FLC_RPC_8822B(x) | BIT_FLC_RPC_8822B(v))
+
+/* 2 REG_RXPKTMON_CTRL_8822B */
+
+#define BIT_SHIFT_RXBKQPKT_SEQ_8822B 20
+#define BIT_MASK_RXBKQPKT_SEQ_8822B 0xf
+#define BIT_RXBKQPKT_SEQ_8822B(x)                                              \
+	(((x) & BIT_MASK_RXBKQPKT_SEQ_8822B) << BIT_SHIFT_RXBKQPKT_SEQ_8822B)
+#define BITS_RXBKQPKT_SEQ_8822B                                                \
+	(BIT_MASK_RXBKQPKT_SEQ_8822B << BIT_SHIFT_RXBKQPKT_SEQ_8822B)
+#define BIT_CLEAR_RXBKQPKT_SEQ_8822B(x) ((x) & (~BITS_RXBKQPKT_SEQ_8822B))
+#define BIT_GET_RXBKQPKT_SEQ_8822B(x)                                          \
+	(((x) >> BIT_SHIFT_RXBKQPKT_SEQ_8822B) & BIT_MASK_RXBKQPKT_SEQ_8822B)
+#define BIT_SET_RXBKQPKT_SEQ_8822B(x, v)                                       \
+	(BIT_CLEAR_RXBKQPKT_SEQ_8822B(x) | BIT_RXBKQPKT_SEQ_8822B(v))
+
+#define BIT_SHIFT_RXBEQPKT_SEQ_8822B 16
+#define BIT_MASK_RXBEQPKT_SEQ_8822B 0xf
+#define BIT_RXBEQPKT_SEQ_8822B(x)                                              \
+	(((x) & BIT_MASK_RXBEQPKT_SEQ_8822B) << BIT_SHIFT_RXBEQPKT_SEQ_8822B)
+#define BITS_RXBEQPKT_SEQ_8822B                                                \
+	(BIT_MASK_RXBEQPKT_SEQ_8822B << BIT_SHIFT_RXBEQPKT_SEQ_8822B)
+#define BIT_CLEAR_RXBEQPKT_SEQ_8822B(x) ((x) & (~BITS_RXBEQPKT_SEQ_8822B))
+#define BIT_GET_RXBEQPKT_SEQ_8822B(x)                                          \
+	(((x) >> BIT_SHIFT_RXBEQPKT_SEQ_8822B) & BIT_MASK_RXBEQPKT_SEQ_8822B)
+#define BIT_SET_RXBEQPKT_SEQ_8822B(x, v)                                       \
+	(BIT_CLEAR_RXBEQPKT_SEQ_8822B(x) | BIT_RXBEQPKT_SEQ_8822B(v))
+
+#define BIT_SHIFT_RXVIQPKT_SEQ_8822B 12
+#define BIT_MASK_RXVIQPKT_SEQ_8822B 0xf
+#define BIT_RXVIQPKT_SEQ_8822B(x)                                              \
+	(((x) & BIT_MASK_RXVIQPKT_SEQ_8822B) << BIT_SHIFT_RXVIQPKT_SEQ_8822B)
+#define BITS_RXVIQPKT_SEQ_8822B                                                \
+	(BIT_MASK_RXVIQPKT_SEQ_8822B << BIT_SHIFT_RXVIQPKT_SEQ_8822B)
+#define BIT_CLEAR_RXVIQPKT_SEQ_8822B(x) ((x) & (~BITS_RXVIQPKT_SEQ_8822B))
+#define BIT_GET_RXVIQPKT_SEQ_8822B(x)                                          \
+	(((x) >> BIT_SHIFT_RXVIQPKT_SEQ_8822B) & BIT_MASK_RXVIQPKT_SEQ_8822B)
+#define BIT_SET_RXVIQPKT_SEQ_8822B(x, v)                                       \
+	(BIT_CLEAR_RXVIQPKT_SEQ_8822B(x) | BIT_RXVIQPKT_SEQ_8822B(v))
+
+#define BIT_SHIFT_RXVOQPKT_SEQ_8822B 8
+#define BIT_MASK_RXVOQPKT_SEQ_8822B 0xf
+#define BIT_RXVOQPKT_SEQ_8822B(x)                                              \
+	(((x) & BIT_MASK_RXVOQPKT_SEQ_8822B) << BIT_SHIFT_RXVOQPKT_SEQ_8822B)
+#define BITS_RXVOQPKT_SEQ_8822B                                                \
+	(BIT_MASK_RXVOQPKT_SEQ_8822B << BIT_SHIFT_RXVOQPKT_SEQ_8822B)
+#define BIT_CLEAR_RXVOQPKT_SEQ_8822B(x) ((x) & (~BITS_RXVOQPKT_SEQ_8822B))
+#define BIT_GET_RXVOQPKT_SEQ_8822B(x)                                          \
+	(((x) >> BIT_SHIFT_RXVOQPKT_SEQ_8822B) & BIT_MASK_RXVOQPKT_SEQ_8822B)
+#define BIT_SET_RXVOQPKT_SEQ_8822B(x, v)                                       \
+	(BIT_CLEAR_RXVOQPKT_SEQ_8822B(x) | BIT_RXVOQPKT_SEQ_8822B(v))
+
+#define BIT_RXBKQPKT_ERR_8822B BIT(7)
+#define BIT_RXBEQPKT_ERR_8822B BIT(6)
+#define BIT_RXVIQPKT_ERR_8822B BIT(5)
+#define BIT_RXVOQPKT_ERR_8822B BIT(4)
+#define BIT_RXDMA_MON_EN_8822B BIT(2)
+#define BIT_RXPKT_MON_RST_8822B BIT(1)
+#define BIT_RXPKT_MON_EN_8822B BIT(0)
+
+/* 2 REG_STATE_MON_8822B */
+
+#define BIT_SHIFT_STATE_SEL_8822B 24
+#define BIT_MASK_STATE_SEL_8822B 0x1f
+#define BIT_STATE_SEL_8822B(x)                                                 \
+	(((x) & BIT_MASK_STATE_SEL_8822B) << BIT_SHIFT_STATE_SEL_8822B)
+#define BITS_STATE_SEL_8822B                                                   \
+	(BIT_MASK_STATE_SEL_8822B << BIT_SHIFT_STATE_SEL_8822B)
+#define BIT_CLEAR_STATE_SEL_8822B(x) ((x) & (~BITS_STATE_SEL_8822B))
+#define BIT_GET_STATE_SEL_8822B(x)                                             \
+	(((x) >> BIT_SHIFT_STATE_SEL_8822B) & BIT_MASK_STATE_SEL_8822B)
+#define BIT_SET_STATE_SEL_8822B(x, v)                                          \
+	(BIT_CLEAR_STATE_SEL_8822B(x) | BIT_STATE_SEL_8822B(v))
+
+#define BIT_SHIFT_STATE_INFO_8822B 8
+#define BIT_MASK_STATE_INFO_8822B 0xff
+#define BIT_STATE_INFO_8822B(x)                                                \
+	(((x) & BIT_MASK_STATE_INFO_8822B) << BIT_SHIFT_STATE_INFO_8822B)
+#define BITS_STATE_INFO_8822B                                                  \
+	(BIT_MASK_STATE_INFO_8822B << BIT_SHIFT_STATE_INFO_8822B)
+#define BIT_CLEAR_STATE_INFO_8822B(x) ((x) & (~BITS_STATE_INFO_8822B))
+#define BIT_GET_STATE_INFO_8822B(x)                                            \
+	(((x) >> BIT_SHIFT_STATE_INFO_8822B) & BIT_MASK_STATE_INFO_8822B)
+#define BIT_SET_STATE_INFO_8822B(x, v)                                         \
+	(BIT_CLEAR_STATE_INFO_8822B(x) | BIT_STATE_INFO_8822B(v))
+
+#define BIT_UPD_NXT_STATE_8822B BIT(7)
+
+#define BIT_SHIFT_CUR_STATE_8822B 0
+#define BIT_MASK_CUR_STATE_8822B 0x7f
+#define BIT_CUR_STATE_8822B(x)                                                 \
+	(((x) & BIT_MASK_CUR_STATE_8822B) << BIT_SHIFT_CUR_STATE_8822B)
+#define BITS_CUR_STATE_8822B                                                   \
+	(BIT_MASK_CUR_STATE_8822B << BIT_SHIFT_CUR_STATE_8822B)
+#define BIT_CLEAR_CUR_STATE_8822B(x) ((x) & (~BITS_CUR_STATE_8822B))
+#define BIT_GET_CUR_STATE_8822B(x)                                             \
+	(((x) >> BIT_SHIFT_CUR_STATE_8822B) & BIT_MASK_CUR_STATE_8822B)
+#define BIT_SET_CUR_STATE_8822B(x, v)                                          \
+	(BIT_CLEAR_CUR_STATE_8822B(x) | BIT_CUR_STATE_8822B(v))
+
+/* 2 REG_ERROR_MON_8822B */
+#define BIT_MACRX_ERR_1_8822B BIT(17)
+#define BIT_MACRX_ERR_0_8822B BIT(16)
+#define BIT_MACTX_ERR_3_8822B BIT(3)
+#define BIT_MACTX_ERR_2_8822B BIT(2)
+#define BIT_MACTX_ERR_1_8822B BIT(1)
+#define BIT_MACTX_ERR_0_8822B BIT(0)
+
+/* 2 REG_SEARCH_MACID_8822B */
+#define BIT_EN_TXRPTBUF_CLK_8822B BIT(31)
+
+#define BIT_SHIFT_INFO_INDEX_OFFSET_8822B 16
+#define BIT_MASK_INFO_INDEX_OFFSET_8822B 0x1fff
+#define BIT_INFO_INDEX_OFFSET_8822B(x)                                         \
+	(((x) & BIT_MASK_INFO_INDEX_OFFSET_8822B)                              \
+	 << BIT_SHIFT_INFO_INDEX_OFFSET_8822B)
+#define BITS_INFO_INDEX_OFFSET_8822B                                           \
+	(BIT_MASK_INFO_INDEX_OFFSET_8822B << BIT_SHIFT_INFO_INDEX_OFFSET_8822B)
+#define BIT_CLEAR_INFO_INDEX_OFFSET_8822B(x)                                   \
+	((x) & (~BITS_INFO_INDEX_OFFSET_8822B))
+#define BIT_GET_INFO_INDEX_OFFSET_8822B(x)                                     \
+	(((x) >> BIT_SHIFT_INFO_INDEX_OFFSET_8822B) &                          \
+	 BIT_MASK_INFO_INDEX_OFFSET_8822B)
+#define BIT_SET_INFO_INDEX_OFFSET_8822B(x, v)                                  \
+	(BIT_CLEAR_INFO_INDEX_OFFSET_8822B(x) | BIT_INFO_INDEX_OFFSET_8822B(v))
+
+#define BIT_WMAC_SRCH_FIFOFULL_8822B BIT(15)
+#define BIT_DIS_INFOSRCH_8822B BIT(14)
+#define BIT_DISABLE_B0_8822B BIT(13)
+
+#define BIT_SHIFT_INFO_ADDR_OFFSET_8822B 0
+#define BIT_MASK_INFO_ADDR_OFFSET_8822B 0x1fff
+#define BIT_INFO_ADDR_OFFSET_8822B(x)                                          \
+	(((x) & BIT_MASK_INFO_ADDR_OFFSET_8822B)                               \
+	 << BIT_SHIFT_INFO_ADDR_OFFSET_8822B)
+#define BITS_INFO_ADDR_OFFSET_8822B                                            \
+	(BIT_MASK_INFO_ADDR_OFFSET_8822B << BIT_SHIFT_INFO_ADDR_OFFSET_8822B)
+#define BIT_CLEAR_INFO_ADDR_OFFSET_8822B(x)                                    \
+	((x) & (~BITS_INFO_ADDR_OFFSET_8822B))
+#define BIT_GET_INFO_ADDR_OFFSET_8822B(x)                                      \
+	(((x) >> BIT_SHIFT_INFO_ADDR_OFFSET_8822B) &                           \
+	 BIT_MASK_INFO_ADDR_OFFSET_8822B)
+#define BIT_SET_INFO_ADDR_OFFSET_8822B(x, v)                                   \
+	(BIT_CLEAR_INFO_ADDR_OFFSET_8822B(x) | BIT_INFO_ADDR_OFFSET_8822B(v))
+
+/* 2 REG_BT_COEX_TABLE_8822B (BT-COEXISTENCE CONTROL REGISTER) */
+#define BIT_PRI_MASK_RX_RESP_8822B BIT(126)
+#define BIT_PRI_MASK_RXOFDM_8822B BIT(125)
+#define BIT_PRI_MASK_RXCCK_8822B BIT(124)
+
+#define BIT_SHIFT_PRI_MASK_TXAC_8822B (117 & CPU_OPT_WIDTH)
+#define BIT_MASK_PRI_MASK_TXAC_8822B 0x7f
+#define BIT_PRI_MASK_TXAC_8822B(x)                                             \
+	(((x) & BIT_MASK_PRI_MASK_TXAC_8822B) << BIT_SHIFT_PRI_MASK_TXAC_8822B)
+#define BITS_PRI_MASK_TXAC_8822B                                               \
+	(BIT_MASK_PRI_MASK_TXAC_8822B << BIT_SHIFT_PRI_MASK_TXAC_8822B)
+#define BIT_CLEAR_PRI_MASK_TXAC_8822B(x) ((x) & (~BITS_PRI_MASK_TXAC_8822B))
+#define BIT_GET_PRI_MASK_TXAC_8822B(x)                                         \
+	(((x) >> BIT_SHIFT_PRI_MASK_TXAC_8822B) & BIT_MASK_PRI_MASK_TXAC_8822B)
+#define BIT_SET_PRI_MASK_TXAC_8822B(x, v)                                      \
+	(BIT_CLEAR_PRI_MASK_TXAC_8822B(x) | BIT_PRI_MASK_TXAC_8822B(v))
+
+#define BIT_SHIFT_PRI_MASK_NAV_8822B (109 & CPU_OPT_WIDTH)
+#define BIT_MASK_PRI_MASK_NAV_8822B 0xff
+#define BIT_PRI_MASK_NAV_8822B(x)                                              \
+	(((x) & BIT_MASK_PRI_MASK_NAV_8822B) << BIT_SHIFT_PRI_MASK_NAV_8822B)
+#define BITS_PRI_MASK_NAV_8822B                                                \
+	(BIT_MASK_PRI_MASK_NAV_8822B << BIT_SHIFT_PRI_MASK_NAV_8822B)
+#define BIT_CLEAR_PRI_MASK_NAV_8822B(x) ((x) & (~BITS_PRI_MASK_NAV_8822B))
+#define BIT_GET_PRI_MASK_NAV_8822B(x)                                          \
+	(((x) >> BIT_SHIFT_PRI_MASK_NAV_8822B) & BIT_MASK_PRI_MASK_NAV_8822B)
+#define BIT_SET_PRI_MASK_NAV_8822B(x, v)                                       \
+	(BIT_CLEAR_PRI_MASK_NAV_8822B(x) | BIT_PRI_MASK_NAV_8822B(v))
+
+#define BIT_PRI_MASK_CCK_8822B BIT(108)
+#define BIT_PRI_MASK_OFDM_8822B BIT(107)
+#define BIT_PRI_MASK_RTY_8822B BIT(106)
+
+#define BIT_SHIFT_PRI_MASK_NUM_8822B (102 & CPU_OPT_WIDTH)
+#define BIT_MASK_PRI_MASK_NUM_8822B 0xf
+#define BIT_PRI_MASK_NUM_8822B(x)                                              \
+	(((x) & BIT_MASK_PRI_MASK_NUM_8822B) << BIT_SHIFT_PRI_MASK_NUM_8822B)
+#define BITS_PRI_MASK_NUM_8822B                                                \
+	(BIT_MASK_PRI_MASK_NUM_8822B << BIT_SHIFT_PRI_MASK_NUM_8822B)
+#define BIT_CLEAR_PRI_MASK_NUM_8822B(x) ((x) & (~BITS_PRI_MASK_NUM_8822B))
+#define BIT_GET_PRI_MASK_NUM_8822B(x)                                          \
+	(((x) >> BIT_SHIFT_PRI_MASK_NUM_8822B) & BIT_MASK_PRI_MASK_NUM_8822B)
+#define BIT_SET_PRI_MASK_NUM_8822B(x, v)                                       \
+	(BIT_CLEAR_PRI_MASK_NUM_8822B(x) | BIT_PRI_MASK_NUM_8822B(v))
+
+#define BIT_SHIFT_PRI_MASK_TYPE_8822B (98 & CPU_OPT_WIDTH)
+#define BIT_MASK_PRI_MASK_TYPE_8822B 0xf
+#define BIT_PRI_MASK_TYPE_8822B(x)                                             \
+	(((x) & BIT_MASK_PRI_MASK_TYPE_8822B) << BIT_SHIFT_PRI_MASK_TYPE_8822B)
+#define BITS_PRI_MASK_TYPE_8822B                                               \
+	(BIT_MASK_PRI_MASK_TYPE_8822B << BIT_SHIFT_PRI_MASK_TYPE_8822B)
+#define BIT_CLEAR_PRI_MASK_TYPE_8822B(x) ((x) & (~BITS_PRI_MASK_TYPE_8822B))
+#define BIT_GET_PRI_MASK_TYPE_8822B(x)                                         \
+	(((x) >> BIT_SHIFT_PRI_MASK_TYPE_8822B) & BIT_MASK_PRI_MASK_TYPE_8822B)
+#define BIT_SET_PRI_MASK_TYPE_8822B(x, v)                                      \
+	(BIT_CLEAR_PRI_MASK_TYPE_8822B(x) | BIT_PRI_MASK_TYPE_8822B(v))
+
+#define BIT_OOB_8822B BIT(97)
+#define BIT_ANT_SEL_8822B BIT(96)
+
+#define BIT_SHIFT_BREAK_TABLE_2_8822B (80 & CPU_OPT_WIDTH)
+#define BIT_MASK_BREAK_TABLE_2_8822B 0xffff
+#define BIT_BREAK_TABLE_2_8822B(x)                                             \
+	(((x) & BIT_MASK_BREAK_TABLE_2_8822B) << BIT_SHIFT_BREAK_TABLE_2_8822B)
+#define BITS_BREAK_TABLE_2_8822B                                               \
+	(BIT_MASK_BREAK_TABLE_2_8822B << BIT_SHIFT_BREAK_TABLE_2_8822B)
+#define BIT_CLEAR_BREAK_TABLE_2_8822B(x) ((x) & (~BITS_BREAK_TABLE_2_8822B))
+#define BIT_GET_BREAK_TABLE_2_8822B(x)                                         \
+	(((x) >> BIT_SHIFT_BREAK_TABLE_2_8822B) & BIT_MASK_BREAK_TABLE_2_8822B)
+#define BIT_SET_BREAK_TABLE_2_8822B(x, v)                                      \
+	(BIT_CLEAR_BREAK_TABLE_2_8822B(x) | BIT_BREAK_TABLE_2_8822B(v))
+
+#define BIT_SHIFT_BREAK_TABLE_1_8822B (64 & CPU_OPT_WIDTH)
+#define BIT_MASK_BREAK_TABLE_1_8822B 0xffff
+#define BIT_BREAK_TABLE_1_8822B(x)                                             \
+	(((x) & BIT_MASK_BREAK_TABLE_1_8822B) << BIT_SHIFT_BREAK_TABLE_1_8822B)
+#define BITS_BREAK_TABLE_1_8822B                                               \
+	(BIT_MASK_BREAK_TABLE_1_8822B << BIT_SHIFT_BREAK_TABLE_1_8822B)
+#define BIT_CLEAR_BREAK_TABLE_1_8822B(x) ((x) & (~BITS_BREAK_TABLE_1_8822B))
+#define BIT_GET_BREAK_TABLE_1_8822B(x)                                         \
+	(((x) >> BIT_SHIFT_BREAK_TABLE_1_8822B) & BIT_MASK_BREAK_TABLE_1_8822B)
+#define BIT_SET_BREAK_TABLE_1_8822B(x, v)                                      \
+	(BIT_CLEAR_BREAK_TABLE_1_8822B(x) | BIT_BREAK_TABLE_1_8822B(v))
+
+#define BIT_SHIFT_COEX_TABLE_2_8822B (32 & CPU_OPT_WIDTH)
+#define BIT_MASK_COEX_TABLE_2_8822B 0xffffffffL
+#define BIT_COEX_TABLE_2_8822B(x)                                              \
+	(((x) & BIT_MASK_COEX_TABLE_2_8822B) << BIT_SHIFT_COEX_TABLE_2_8822B)
+#define BITS_COEX_TABLE_2_8822B                                                \
+	(BIT_MASK_COEX_TABLE_2_8822B << BIT_SHIFT_COEX_TABLE_2_8822B)
+#define BIT_CLEAR_COEX_TABLE_2_8822B(x) ((x) & (~BITS_COEX_TABLE_2_8822B))
+#define BIT_GET_COEX_TABLE_2_8822B(x)                                          \
+	(((x) >> BIT_SHIFT_COEX_TABLE_2_8822B) & BIT_MASK_COEX_TABLE_2_8822B)
+#define BIT_SET_COEX_TABLE_2_8822B(x, v)                                       \
+	(BIT_CLEAR_COEX_TABLE_2_8822B(x) | BIT_COEX_TABLE_2_8822B(v))
+
+#define BIT_SHIFT_COEX_TABLE_1_8822B 0
+#define BIT_MASK_COEX_TABLE_1_8822B 0xffffffffL
+#define BIT_COEX_TABLE_1_8822B(x)                                              \
+	(((x) & BIT_MASK_COEX_TABLE_1_8822B) << BIT_SHIFT_COEX_TABLE_1_8822B)
+#define BITS_COEX_TABLE_1_8822B                                                \
+	(BIT_MASK_COEX_TABLE_1_8822B << BIT_SHIFT_COEX_TABLE_1_8822B)
+#define BIT_CLEAR_COEX_TABLE_1_8822B(x) ((x) & (~BITS_COEX_TABLE_1_8822B))
+#define BIT_GET_COEX_TABLE_1_8822B(x)                                          \
+	(((x) >> BIT_SHIFT_COEX_TABLE_1_8822B) & BIT_MASK_COEX_TABLE_1_8822B)
+#define BIT_SET_COEX_TABLE_1_8822B(x, v)                                       \
+	(BIT_CLEAR_COEX_TABLE_1_8822B(x) | BIT_COEX_TABLE_1_8822B(v))
+
+/* 2 REG_RXCMD_0_8822B */
+#define BIT_RXCMD_EN_8822B BIT(31)
+
+#define BIT_SHIFT_RXCMD_INFO_8822B 0
+#define BIT_MASK_RXCMD_INFO_8822B 0x7fffffffL
+#define BIT_RXCMD_INFO_8822B(x)                                                \
+	(((x) & BIT_MASK_RXCMD_INFO_8822B) << BIT_SHIFT_RXCMD_INFO_8822B)
+#define BITS_RXCMD_INFO_8822B                                                  \
+	(BIT_MASK_RXCMD_INFO_8822B << BIT_SHIFT_RXCMD_INFO_8822B)
+#define BIT_CLEAR_RXCMD_INFO_8822B(x) ((x) & (~BITS_RXCMD_INFO_8822B))
+#define BIT_GET_RXCMD_INFO_8822B(x)                                            \
+	(((x) >> BIT_SHIFT_RXCMD_INFO_8822B) & BIT_MASK_RXCMD_INFO_8822B)
+#define BIT_SET_RXCMD_INFO_8822B(x, v)                                         \
+	(BIT_CLEAR_RXCMD_INFO_8822B(x) | BIT_RXCMD_INFO_8822B(v))
+
+/* 2 REG_RXCMD_1_8822B */
+
+#define BIT_SHIFT_RXCMD_PRD_8822B 0
+#define BIT_MASK_RXCMD_PRD_8822B 0xffff
+#define BIT_RXCMD_PRD_8822B(x)                                                 \
+	(((x) & BIT_MASK_RXCMD_PRD_8822B) << BIT_SHIFT_RXCMD_PRD_8822B)
+#define BITS_RXCMD_PRD_8822B                                                   \
+	(BIT_MASK_RXCMD_PRD_8822B << BIT_SHIFT_RXCMD_PRD_8822B)
+#define BIT_CLEAR_RXCMD_PRD_8822B(x) ((x) & (~BITS_RXCMD_PRD_8822B))
+#define BIT_GET_RXCMD_PRD_8822B(x)                                             \
+	(((x) >> BIT_SHIFT_RXCMD_PRD_8822B) & BIT_MASK_RXCMD_PRD_8822B)
+#define BIT_SET_RXCMD_PRD_8822B(x, v)                                          \
+	(BIT_CLEAR_RXCMD_PRD_8822B(x) | BIT_RXCMD_PRD_8822B(v))
+
+/* 2 REG_NOT_VALID_8822B */
+
+/* 2 REG_WMAC_RESP_TXINFO_8822B (RESPONSE TXINFO REGISTER) */
+
+#define BIT_SHIFT_WMAC_RESP_MFB_8822B 25
+#define BIT_MASK_WMAC_RESP_MFB_8822B 0x7f
+#define BIT_WMAC_RESP_MFB_8822B(x)                                             \
+	(((x) & BIT_MASK_WMAC_RESP_MFB_8822B) << BIT_SHIFT_WMAC_RESP_MFB_8822B)
+#define BITS_WMAC_RESP_MFB_8822B                                               \
+	(BIT_MASK_WMAC_RESP_MFB_8822B << BIT_SHIFT_WMAC_RESP_MFB_8822B)
+#define BIT_CLEAR_WMAC_RESP_MFB_8822B(x) ((x) & (~BITS_WMAC_RESP_MFB_8822B))
+#define BIT_GET_WMAC_RESP_MFB_8822B(x)                                         \
+	(((x) >> BIT_SHIFT_WMAC_RESP_MFB_8822B) & BIT_MASK_WMAC_RESP_MFB_8822B)
+#define BIT_SET_WMAC_RESP_MFB_8822B(x, v)                                      \
+	(BIT_CLEAR_WMAC_RESP_MFB_8822B(x) | BIT_WMAC_RESP_MFB_8822B(v))
+
+#define BIT_SHIFT_WMAC_ANTINF_SEL_8822B 23
+#define BIT_MASK_WMAC_ANTINF_SEL_8822B 0x3
+#define BIT_WMAC_ANTINF_SEL_8822B(x)                                           \
+	(((x) & BIT_MASK_WMAC_ANTINF_SEL_8822B)                                \
+	 << BIT_SHIFT_WMAC_ANTINF_SEL_8822B)
+#define BITS_WMAC_ANTINF_SEL_8822B                                             \
+	(BIT_MASK_WMAC_ANTINF_SEL_8822B << BIT_SHIFT_WMAC_ANTINF_SEL_8822B)
+#define BIT_CLEAR_WMAC_ANTINF_SEL_8822B(x) ((x) & (~BITS_WMAC_ANTINF_SEL_8822B))
+#define BIT_GET_WMAC_ANTINF_SEL_8822B(x)                                       \
+	(((x) >> BIT_SHIFT_WMAC_ANTINF_SEL_8822B) &                            \
+	 BIT_MASK_WMAC_ANTINF_SEL_8822B)
+#define BIT_SET_WMAC_ANTINF_SEL_8822B(x, v)                                    \
+	(BIT_CLEAR_WMAC_ANTINF_SEL_8822B(x) | BIT_WMAC_ANTINF_SEL_8822B(v))
+
+#define BIT_SHIFT_WMAC_ANTSEL_SEL_8822B 21
+#define BIT_MASK_WMAC_ANTSEL_SEL_8822B 0x3
+#define BIT_WMAC_ANTSEL_SEL_8822B(x)                                           \
+	(((x) & BIT_MASK_WMAC_ANTSEL_SEL_8822B)                                \
+	 << BIT_SHIFT_WMAC_ANTSEL_SEL_8822B)
+#define BITS_WMAC_ANTSEL_SEL_8822B                                             \
+	(BIT_MASK_WMAC_ANTSEL_SEL_8822B << BIT_SHIFT_WMAC_ANTSEL_SEL_8822B)
+#define BIT_CLEAR_WMAC_ANTSEL_SEL_8822B(x) ((x) & (~BITS_WMAC_ANTSEL_SEL_8822B))
+#define BIT_GET_WMAC_ANTSEL_SEL_8822B(x)                                       \
+	(((x) >> BIT_SHIFT_WMAC_ANTSEL_SEL_8822B) &                            \
+	 BIT_MASK_WMAC_ANTSEL_SEL_8822B)
+#define BIT_SET_WMAC_ANTSEL_SEL_8822B(x, v)                                    \
+	(BIT_CLEAR_WMAC_ANTSEL_SEL_8822B(x) | BIT_WMAC_ANTSEL_SEL_8822B(v))
+
+#define BIT_SHIFT_R_WMAC_RESP_TXPOWER_8822B 18
+#define BIT_MASK_R_WMAC_RESP_TXPOWER_8822B 0x7
+#define BIT_R_WMAC_RESP_TXPOWER_8822B(x)                                       \
+	(((x) & BIT_MASK_R_WMAC_RESP_TXPOWER_8822B)                            \
+	 << BIT_SHIFT_R_WMAC_RESP_TXPOWER_8822B)
+#define BITS_R_WMAC_RESP_TXPOWER_8822B                                         \
+	(BIT_MASK_R_WMAC_RESP_TXPOWER_8822B                                    \
+	 << BIT_SHIFT_R_WMAC_RESP_TXPOWER_8822B)
+#define BIT_CLEAR_R_WMAC_RESP_TXPOWER_8822B(x)                                 \
+	((x) & (~BITS_R_WMAC_RESP_TXPOWER_8822B))
+#define BIT_GET_R_WMAC_RESP_TXPOWER_8822B(x)                                   \
+	(((x) >> BIT_SHIFT_R_WMAC_RESP_TXPOWER_8822B) &                        \
+	 BIT_MASK_R_WMAC_RESP_TXPOWER_8822B)
+#define BIT_SET_R_WMAC_RESP_TXPOWER_8822B(x, v)                                \
+	(BIT_CLEAR_R_WMAC_RESP_TXPOWER_8822B(x) |                              \
+	 BIT_R_WMAC_RESP_TXPOWER_8822B(v))
+
+#define BIT_SHIFT_WMAC_RESP_TXANT_8822B 0
+#define BIT_MASK_WMAC_RESP_TXANT_8822B 0x3ffff
+#define BIT_WMAC_RESP_TXANT_8822B(x)                                           \
+	(((x) & BIT_MASK_WMAC_RESP_TXANT_8822B)                                \
+	 << BIT_SHIFT_WMAC_RESP_TXANT_8822B)
+#define BITS_WMAC_RESP_TXANT_8822B                                             \
+	(BIT_MASK_WMAC_RESP_TXANT_8822B << BIT_SHIFT_WMAC_RESP_TXANT_8822B)
+#define BIT_CLEAR_WMAC_RESP_TXANT_8822B(x) ((x) & (~BITS_WMAC_RESP_TXANT_8822B))
+#define BIT_GET_WMAC_RESP_TXANT_8822B(x)                                       \
+	(((x) >> BIT_SHIFT_WMAC_RESP_TXANT_8822B) &                            \
+	 BIT_MASK_WMAC_RESP_TXANT_8822B)
+#define BIT_SET_WMAC_RESP_TXANT_8822B(x, v)                                    \
+	(BIT_CLEAR_WMAC_RESP_TXANT_8822B(x) | BIT_WMAC_RESP_TXANT_8822B(v))
+
+/* 2 REG_BBPSF_CTRL_8822B */
+#define BIT_CTL_IDLE_CLR_CSI_RPT_8822B BIT(31)
+#define BIT_WMAC_USE_NDPARATE_8822B BIT(30)
+
+#define BIT_SHIFT_WMAC_CSI_RATE_8822B 24
+#define BIT_MASK_WMAC_CSI_RATE_8822B 0x3f
+#define BIT_WMAC_CSI_RATE_8822B(x)                                             \
+	(((x) & BIT_MASK_WMAC_CSI_RATE_8822B) << BIT_SHIFT_WMAC_CSI_RATE_8822B)
+#define BITS_WMAC_CSI_RATE_8822B                                               \
+	(BIT_MASK_WMAC_CSI_RATE_8822B << BIT_SHIFT_WMAC_CSI_RATE_8822B)
+#define BIT_CLEAR_WMAC_CSI_RATE_8822B(x) ((x) & (~BITS_WMAC_CSI_RATE_8822B))
+#define BIT_GET_WMAC_CSI_RATE_8822B(x)                                         \
+	(((x) >> BIT_SHIFT_WMAC_CSI_RATE_8822B) & BIT_MASK_WMAC_CSI_RATE_8822B)
+#define BIT_SET_WMAC_CSI_RATE_8822B(x, v)                                      \
+	(BIT_CLEAR_WMAC_CSI_RATE_8822B(x) | BIT_WMAC_CSI_RATE_8822B(v))
+
+#define BIT_SHIFT_WMAC_RESP_TXRATE_8822B 16
+#define BIT_MASK_WMAC_RESP_TXRATE_8822B 0xff
+#define BIT_WMAC_RESP_TXRATE_8822B(x)                                          \
+	(((x) & BIT_MASK_WMAC_RESP_TXRATE_8822B)                               \
+	 << BIT_SHIFT_WMAC_RESP_TXRATE_8822B)
+#define BITS_WMAC_RESP_TXRATE_8822B                                            \
+	(BIT_MASK_WMAC_RESP_TXRATE_8822B << BIT_SHIFT_WMAC_RESP_TXRATE_8822B)
+#define BIT_CLEAR_WMAC_RESP_TXRATE_8822B(x)                                    \
+	((x) & (~BITS_WMAC_RESP_TXRATE_8822B))
+#define BIT_GET_WMAC_RESP_TXRATE_8822B(x)                                      \
+	(((x) >> BIT_SHIFT_WMAC_RESP_TXRATE_8822B) &                           \
+	 BIT_MASK_WMAC_RESP_TXRATE_8822B)
+#define BIT_SET_WMAC_RESP_TXRATE_8822B(x, v)                                   \
+	(BIT_CLEAR_WMAC_RESP_TXRATE_8822B(x) | BIT_WMAC_RESP_TXRATE_8822B(v))
+
+#define BIT_BBPSF_MPDUCHKEN_8822B BIT(5)
+#define BIT_BBPSF_MHCHKEN_8822B BIT(4)
+#define BIT_BBPSF_ERRCHKEN_8822B BIT(3)
+
+#define BIT_SHIFT_BBPSF_ERRTHR_8822B 0
+#define BIT_MASK_BBPSF_ERRTHR_8822B 0x7
+#define BIT_BBPSF_ERRTHR_8822B(x)                                              \
+	(((x) & BIT_MASK_BBPSF_ERRTHR_8822B) << BIT_SHIFT_BBPSF_ERRTHR_8822B)
+#define BITS_BBPSF_ERRTHR_8822B                                                \
+	(BIT_MASK_BBPSF_ERRTHR_8822B << BIT_SHIFT_BBPSF_ERRTHR_8822B)
+#define BIT_CLEAR_BBPSF_ERRTHR_8822B(x) ((x) & (~BITS_BBPSF_ERRTHR_8822B))
+#define BIT_GET_BBPSF_ERRTHR_8822B(x)                                          \
+	(((x) >> BIT_SHIFT_BBPSF_ERRTHR_8822B) & BIT_MASK_BBPSF_ERRTHR_8822B)
+#define BIT_SET_BBPSF_ERRTHR_8822B(x, v)                                       \
+	(BIT_CLEAR_BBPSF_ERRTHR_8822B(x) | BIT_BBPSF_ERRTHR_8822B(v))
+
+/* 2 REG_NOT_VALID_8822B */
+
+/* 2 REG_P2P_RX_BCN_NOA_8822B (P2P RX BEACON NOA REGISTER) */
+#define BIT_NOA_PARSER_EN_8822B BIT(15)
+#define BIT_BSSID_SEL_8822B BIT(14)
+
+#define BIT_SHIFT_P2P_OUI_TYPE_8822B 0
+#define BIT_MASK_P2P_OUI_TYPE_8822B 0xff
+#define BIT_P2P_OUI_TYPE_8822B(x)                                              \
+	(((x) & BIT_MASK_P2P_OUI_TYPE_8822B) << BIT_SHIFT_P2P_OUI_TYPE_8822B)
+#define BITS_P2P_OUI_TYPE_8822B                                                \
+	(BIT_MASK_P2P_OUI_TYPE_8822B << BIT_SHIFT_P2P_OUI_TYPE_8822B)
+#define BIT_CLEAR_P2P_OUI_TYPE_8822B(x) ((x) & (~BITS_P2P_OUI_TYPE_8822B))
+#define BIT_GET_P2P_OUI_TYPE_8822B(x)                                          \
+	(((x) >> BIT_SHIFT_P2P_OUI_TYPE_8822B) & BIT_MASK_P2P_OUI_TYPE_8822B)
+#define BIT_SET_P2P_OUI_TYPE_8822B(x, v)                                       \
+	(BIT_CLEAR_P2P_OUI_TYPE_8822B(x) | BIT_P2P_OUI_TYPE_8822B(v))
+
+/* 2 REG_ASSOCIATED_BFMER0_INFO_8822B (ASSOCIATED BEAMFORMER0 INFO REGISTER) */
+
+#define BIT_SHIFT_R_WMAC_TXCSI_AID0_8822B (48 & CPU_OPT_WIDTH)
+#define BIT_MASK_R_WMAC_TXCSI_AID0_8822B 0x1ff
+#define BIT_R_WMAC_TXCSI_AID0_8822B(x)                                         \
+	(((x) & BIT_MASK_R_WMAC_TXCSI_AID0_8822B)                              \
+	 << BIT_SHIFT_R_WMAC_TXCSI_AID0_8822B)
+#define BITS_R_WMAC_TXCSI_AID0_8822B                                           \
+	(BIT_MASK_R_WMAC_TXCSI_AID0_8822B << BIT_SHIFT_R_WMAC_TXCSI_AID0_8822B)
+#define BIT_CLEAR_R_WMAC_TXCSI_AID0_8822B(x)                                   \
+	((x) & (~BITS_R_WMAC_TXCSI_AID0_8822B))
+#define BIT_GET_R_WMAC_TXCSI_AID0_8822B(x)                                     \
+	(((x) >> BIT_SHIFT_R_WMAC_TXCSI_AID0_8822B) &                          \
+	 BIT_MASK_R_WMAC_TXCSI_AID0_8822B)
+#define BIT_SET_R_WMAC_TXCSI_AID0_8822B(x, v)                                  \
+	(BIT_CLEAR_R_WMAC_TXCSI_AID0_8822B(x) | BIT_R_WMAC_TXCSI_AID0_8822B(v))
+
+#define BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0_8822B 0
+#define BIT_MASK_R_WMAC_SOUNDING_RXADD_R0_8822B 0xffffffffffffL
+#define BIT_R_WMAC_SOUNDING_RXADD_R0_8822B(x)                                  \
+	(((x) & BIT_MASK_R_WMAC_SOUNDING_RXADD_R0_8822B)                       \
+	 << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0_8822B)
+#define BITS_R_WMAC_SOUNDING_RXADD_R0_8822B                                    \
+	(BIT_MASK_R_WMAC_SOUNDING_RXADD_R0_8822B                               \
+	 << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0_8822B)
+#define BIT_CLEAR_R_WMAC_SOUNDING_RXADD_R0_8822B(x)                            \
+	((x) & (~BITS_R_WMAC_SOUNDING_RXADD_R0_8822B))
+#define BIT_GET_R_WMAC_SOUNDING_RXADD_R0_8822B(x)                              \
+	(((x) >> BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0_8822B) &                   \
+	 BIT_MASK_R_WMAC_SOUNDING_RXADD_R0_8822B)
+#define BIT_SET_R_WMAC_SOUNDING_RXADD_R0_8822B(x, v)                           \
+	(BIT_CLEAR_R_WMAC_SOUNDING_RXADD_R0_8822B(x) |                         \
+	 BIT_R_WMAC_SOUNDING_RXADD_R0_8822B(v))
+
+/* 2 REG_ASSOCIATED_BFMER1_INFO_8822B (ASSOCIATED BEAMFORMER1 INFO REGISTER) */
+
+#define BIT_SHIFT_R_WMAC_TXCSI_AID1_8822B (48 & CPU_OPT_WIDTH)
+#define BIT_MASK_R_WMAC_TXCSI_AID1_8822B 0x1ff
+#define BIT_R_WMAC_TXCSI_AID1_8822B(x)                                         \
+	(((x) & BIT_MASK_R_WMAC_TXCSI_AID1_8822B)                              \
+	 << BIT_SHIFT_R_WMAC_TXCSI_AID1_8822B)
+#define BITS_R_WMAC_TXCSI_AID1_8822B                                           \
+	(BIT_MASK_R_WMAC_TXCSI_AID1_8822B << BIT_SHIFT_R_WMAC_TXCSI_AID1_8822B)
+#define BIT_CLEAR_R_WMAC_TXCSI_AID1_8822B(x)                                   \
+	((x) & (~BITS_R_WMAC_TXCSI_AID1_8822B))
+#define BIT_GET_R_WMAC_TXCSI_AID1_8822B(x)                                     \
+	(((x) >> BIT_SHIFT_R_WMAC_TXCSI_AID1_8822B) &                          \
+	 BIT_MASK_R_WMAC_TXCSI_AID1_8822B)
+#define BIT_SET_R_WMAC_TXCSI_AID1_8822B(x, v)                                  \
+	(BIT_CLEAR_R_WMAC_TXCSI_AID1_8822B(x) | BIT_R_WMAC_TXCSI_AID1_8822B(v))
+
+#define BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1_8822B 0
+#define BIT_MASK_R_WMAC_SOUNDING_RXADD_R1_8822B 0xffffffffffffL
+#define BIT_R_WMAC_SOUNDING_RXADD_R1_8822B(x)                                  \
+	(((x) & BIT_MASK_R_WMAC_SOUNDING_RXADD_R1_8822B)                       \
+	 << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1_8822B)
+#define BITS_R_WMAC_SOUNDING_RXADD_R1_8822B                                    \
+	(BIT_MASK_R_WMAC_SOUNDING_RXADD_R1_8822B                               \
+	 << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1_8822B)
+#define BIT_CLEAR_R_WMAC_SOUNDING_RXADD_R1_8822B(x)                            \
+	((x) & (~BITS_R_WMAC_SOUNDING_RXADD_R1_8822B))
+#define BIT_GET_R_WMAC_SOUNDING_RXADD_R1_8822B(x)                              \
+	(((x) >> BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1_8822B) &                   \
+	 BIT_MASK_R_WMAC_SOUNDING_RXADD_R1_8822B)
+#define BIT_SET_R_WMAC_SOUNDING_RXADD_R1_8822B(x, v)                           \
+	(BIT_CLEAR_R_WMAC_SOUNDING_RXADD_R1_8822B(x) |                         \
+	 BIT_R_WMAC_SOUNDING_RXADD_R1_8822B(v))
+
+/* 2 REG_TX_CSI_RPT_PARAM_BW20_8822B (TX CSI REPORT PARAMETER REGISTER) */
+
+#define BIT_SHIFT_R_WMAC_BFINFO_20M_1_8822B 16
+#define BIT_MASK_R_WMAC_BFINFO_20M_1_8822B 0xfff
+#define BIT_R_WMAC_BFINFO_20M_1_8822B(x)                                       \
+	(((x) & BIT_MASK_R_WMAC_BFINFO_20M_1_8822B)                            \
+	 << BIT_SHIFT_R_WMAC_BFINFO_20M_1_8822B)
+#define BITS_R_WMAC_BFINFO_20M_1_8822B                                         \
+	(BIT_MASK_R_WMAC_BFINFO_20M_1_8822B                                    \
+	 << BIT_SHIFT_R_WMAC_BFINFO_20M_1_8822B)
+#define BIT_CLEAR_R_WMAC_BFINFO_20M_1_8822B(x)                                 \
+	((x) & (~BITS_R_WMAC_BFINFO_20M_1_8822B))
+#define BIT_GET_R_WMAC_BFINFO_20M_1_8822B(x)                                   \
+	(((x) >> BIT_SHIFT_R_WMAC_BFINFO_20M_1_8822B) &                        \
+	 BIT_MASK_R_WMAC_BFINFO_20M_1_8822B)
+#define BIT_SET_R_WMAC_BFINFO_20M_1_8822B(x, v)                                \
+	(BIT_CLEAR_R_WMAC_BFINFO_20M_1_8822B(x) |                              \
+	 BIT_R_WMAC_BFINFO_20M_1_8822B(v))
+
+#define BIT_SHIFT_R_WMAC_BFINFO_20M_0_8822B 0
+#define BIT_MASK_R_WMAC_BFINFO_20M_0_8822B 0xfff
+#define BIT_R_WMAC_BFINFO_20M_0_8822B(x)                                       \
+	(((x) & BIT_MASK_R_WMAC_BFINFO_20M_0_8822B)                            \
+	 << BIT_SHIFT_R_WMAC_BFINFO_20M_0_8822B)
+#define BITS_R_WMAC_BFINFO_20M_0_8822B                                         \
+	(BIT_MASK_R_WMAC_BFINFO_20M_0_8822B                                    \
+	 << BIT_SHIFT_R_WMAC_BFINFO_20M_0_8822B)
+#define BIT_CLEAR_R_WMAC_BFINFO_20M_0_8822B(x)                                 \
+	((x) & (~BITS_R_WMAC_BFINFO_20M_0_8822B))
+#define BIT_GET_R_WMAC_BFINFO_20M_0_8822B(x)                                   \
+	(((x) >> BIT_SHIFT_R_WMAC_BFINFO_20M_0_8822B) &                        \
+	 BIT_MASK_R_WMAC_BFINFO_20M_0_8822B)
+#define BIT_SET_R_WMAC_BFINFO_20M_0_8822B(x, v)                                \
+	(BIT_CLEAR_R_WMAC_BFINFO_20M_0_8822B(x) |                              \
+	 BIT_R_WMAC_BFINFO_20M_0_8822B(v))
+
+/* 2 REG_TX_CSI_RPT_PARAM_BW40_8822B (TX CSI REPORT PARAMETER_BW40 REGISTER) */
+
+#define BIT_SHIFT_WMAC_RESP_ANTCD_8822B 0
+#define BIT_MASK_WMAC_RESP_ANTCD_8822B 0xf
+#define BIT_WMAC_RESP_ANTCD_8822B(x)                                           \
+	(((x) & BIT_MASK_WMAC_RESP_ANTCD_8822B)                                \
+	 << BIT_SHIFT_WMAC_RESP_ANTCD_8822B)
+#define BITS_WMAC_RESP_ANTCD_8822B                                             \
+	(BIT_MASK_WMAC_RESP_ANTCD_8822B << BIT_SHIFT_WMAC_RESP_ANTCD_8822B)
+#define BIT_CLEAR_WMAC_RESP_ANTCD_8822B(x) ((x) & (~BITS_WMAC_RESP_ANTCD_8822B))
+#define BIT_GET_WMAC_RESP_ANTCD_8822B(x)                                       \
+	(((x) >> BIT_SHIFT_WMAC_RESP_ANTCD_8822B) &                            \
+	 BIT_MASK_WMAC_RESP_ANTCD_8822B)
+#define BIT_SET_WMAC_RESP_ANTCD_8822B(x, v)                                    \
+	(BIT_CLEAR_WMAC_RESP_ANTCD_8822B(x) | BIT_WMAC_RESP_ANTCD_8822B(v))
+
+/* 2 REG_TX_CSI_RPT_PARAM_BW80_8822B (TX CSI REPORT PARAMETER_BW80 REGISTER) */
+
+/* 2 REG_BCN_PSR_RPT2_8822B (BEACON PARSER REPORT REGISTER2) */
+
+#define BIT_SHIFT_DTIM_CNT2_8822B 24
+#define BIT_MASK_DTIM_CNT2_8822B 0xff
+#define BIT_DTIM_CNT2_8822B(x)                                                 \
+	(((x) & BIT_MASK_DTIM_CNT2_8822B) << BIT_SHIFT_DTIM_CNT2_8822B)
+#define BITS_DTIM_CNT2_8822B                                                   \
+	(BIT_MASK_DTIM_CNT2_8822B << BIT_SHIFT_DTIM_CNT2_8822B)
+#define BIT_CLEAR_DTIM_CNT2_8822B(x) ((x) & (~BITS_DTIM_CNT2_8822B))
+#define BIT_GET_DTIM_CNT2_8822B(x)                                             \
+	(((x) >> BIT_SHIFT_DTIM_CNT2_8822B) & BIT_MASK_DTIM_CNT2_8822B)
+#define BIT_SET_DTIM_CNT2_8822B(x, v)                                          \
+	(BIT_CLEAR_DTIM_CNT2_8822B(x) | BIT_DTIM_CNT2_8822B(v))
+
+#define BIT_SHIFT_DTIM_PERIOD2_8822B 16
+#define BIT_MASK_DTIM_PERIOD2_8822B 0xff
+#define BIT_DTIM_PERIOD2_8822B(x)                                              \
+	(((x) & BIT_MASK_DTIM_PERIOD2_8822B) << BIT_SHIFT_DTIM_PERIOD2_8822B)
+#define BITS_DTIM_PERIOD2_8822B                                                \
+	(BIT_MASK_DTIM_PERIOD2_8822B << BIT_SHIFT_DTIM_PERIOD2_8822B)
+#define BIT_CLEAR_DTIM_PERIOD2_8822B(x) ((x) & (~BITS_DTIM_PERIOD2_8822B))
+#define BIT_GET_DTIM_PERIOD2_8822B(x)                                          \
+	(((x) >> BIT_SHIFT_DTIM_PERIOD2_8822B) & BIT_MASK_DTIM_PERIOD2_8822B)
+#define BIT_SET_DTIM_PERIOD2_8822B(x, v)                                       \
+	(BIT_CLEAR_DTIM_PERIOD2_8822B(x) | BIT_DTIM_PERIOD2_8822B(v))
+
+#define BIT_DTIM2_8822B BIT(15)
+#define BIT_TIM2_8822B BIT(14)
+
+#define BIT_SHIFT_PS_AID_2_8822B 0
+#define BIT_MASK_PS_AID_2_8822B 0x7ff
+#define BIT_PS_AID_2_8822B(x)                                                  \
+	(((x) & BIT_MASK_PS_AID_2_8822B) << BIT_SHIFT_PS_AID_2_8822B)
+#define BITS_PS_AID_2_8822B                                                    \
+	(BIT_MASK_PS_AID_2_8822B << BIT_SHIFT_PS_AID_2_8822B)
+#define BIT_CLEAR_PS_AID_2_8822B(x) ((x) & (~BITS_PS_AID_2_8822B))
+#define BIT_GET_PS_AID_2_8822B(x)                                              \
+	(((x) >> BIT_SHIFT_PS_AID_2_8822B) & BIT_MASK_PS_AID_2_8822B)
+#define BIT_SET_PS_AID_2_8822B(x, v)                                           \
+	(BIT_CLEAR_PS_AID_2_8822B(x) | BIT_PS_AID_2_8822B(v))
+
+/* 2 REG_BCN_PSR_RPT3_8822B (BEACON PARSER REPORT REGISTER3) */
+
+#define BIT_SHIFT_DTIM_CNT3_8822B 24
+#define BIT_MASK_DTIM_CNT3_8822B 0xff
+#define BIT_DTIM_CNT3_8822B(x)                                                 \
+	(((x) & BIT_MASK_DTIM_CNT3_8822B) << BIT_SHIFT_DTIM_CNT3_8822B)
+#define BITS_DTIM_CNT3_8822B                                                   \
+	(BIT_MASK_DTIM_CNT3_8822B << BIT_SHIFT_DTIM_CNT3_8822B)
+#define BIT_CLEAR_DTIM_CNT3_8822B(x) ((x) & (~BITS_DTIM_CNT3_8822B))
+#define BIT_GET_DTIM_CNT3_8822B(x)                                             \
+	(((x) >> BIT_SHIFT_DTIM_CNT3_8822B) & BIT_MASK_DTIM_CNT3_8822B)
+#define BIT_SET_DTIM_CNT3_8822B(x, v)                                          \
+	(BIT_CLEAR_DTIM_CNT3_8822B(x) | BIT_DTIM_CNT3_8822B(v))
+
+#define BIT_SHIFT_DTIM_PERIOD3_8822B 16
+#define BIT_MASK_DTIM_PERIOD3_8822B 0xff
+#define BIT_DTIM_PERIOD3_8822B(x)                                              \
+	(((x) & BIT_MASK_DTIM_PERIOD3_8822B) << BIT_SHIFT_DTIM_PERIOD3_8822B)
+#define BITS_DTIM_PERIOD3_8822B                                                \
+	(BIT_MASK_DTIM_PERIOD3_8822B << BIT_SHIFT_DTIM_PERIOD3_8822B)
+#define BIT_CLEAR_DTIM_PERIOD3_8822B(x) ((x) & (~BITS_DTIM_PERIOD3_8822B))
+#define BIT_GET_DTIM_PERIOD3_8822B(x)                                          \
+	(((x) >> BIT_SHIFT_DTIM_PERIOD3_8822B) & BIT_MASK_DTIM_PERIOD3_8822B)
+#define BIT_SET_DTIM_PERIOD3_8822B(x, v)                                       \
+	(BIT_CLEAR_DTIM_PERIOD3_8822B(x) | BIT_DTIM_PERIOD3_8822B(v))
+
+#define BIT_DTIM3_8822B BIT(15)
+#define BIT_TIM3_8822B BIT(14)
+
+#define BIT_SHIFT_PS_AID_3_8822B 0
+#define BIT_MASK_PS_AID_3_8822B 0x7ff
+#define BIT_PS_AID_3_8822B(x)                                                  \
+	(((x) & BIT_MASK_PS_AID_3_8822B) << BIT_SHIFT_PS_AID_3_8822B)
+#define BITS_PS_AID_3_8822B                                                    \
+	(BIT_MASK_PS_AID_3_8822B << BIT_SHIFT_PS_AID_3_8822B)
+#define BIT_CLEAR_PS_AID_3_8822B(x) ((x) & (~BITS_PS_AID_3_8822B))
+#define BIT_GET_PS_AID_3_8822B(x)                                              \
+	(((x) >> BIT_SHIFT_PS_AID_3_8822B) & BIT_MASK_PS_AID_3_8822B)
+#define BIT_SET_PS_AID_3_8822B(x, v)                                           \
+	(BIT_CLEAR_PS_AID_3_8822B(x) | BIT_PS_AID_3_8822B(v))
+
+/* 2 REG_BCN_PSR_RPT4_8822B (BEACON PARSER REPORT REGISTER4) */
+
+#define BIT_SHIFT_DTIM_CNT4_8822B 24
+#define BIT_MASK_DTIM_CNT4_8822B 0xff
+#define BIT_DTIM_CNT4_8822B(x)                                                 \
+	(((x) & BIT_MASK_DTIM_CNT4_8822B) << BIT_SHIFT_DTIM_CNT4_8822B)
+#define BITS_DTIM_CNT4_8822B                                                   \
+	(BIT_MASK_DTIM_CNT4_8822B << BIT_SHIFT_DTIM_CNT4_8822B)
+#define BIT_CLEAR_DTIM_CNT4_8822B(x) ((x) & (~BITS_DTIM_CNT4_8822B))
+#define BIT_GET_DTIM_CNT4_8822B(x)                                             \
+	(((x) >> BIT_SHIFT_DTIM_CNT4_8822B) & BIT_MASK_DTIM_CNT4_8822B)
+#define BIT_SET_DTIM_CNT4_8822B(x, v)                                          \
+	(BIT_CLEAR_DTIM_CNT4_8822B(x) | BIT_DTIM_CNT4_8822B(v))
+
+#define BIT_SHIFT_DTIM_PERIOD4_8822B 16
+#define BIT_MASK_DTIM_PERIOD4_8822B 0xff
+#define BIT_DTIM_PERIOD4_8822B(x)                                              \
+	(((x) & BIT_MASK_DTIM_PERIOD4_8822B) << BIT_SHIFT_DTIM_PERIOD4_8822B)
+#define BITS_DTIM_PERIOD4_8822B                                                \
+	(BIT_MASK_DTIM_PERIOD4_8822B << BIT_SHIFT_DTIM_PERIOD4_8822B)
+#define BIT_CLEAR_DTIM_PERIOD4_8822B(x) ((x) & (~BITS_DTIM_PERIOD4_8822B))
+#define BIT_GET_DTIM_PERIOD4_8822B(x)                                          \
+	(((x) >> BIT_SHIFT_DTIM_PERIOD4_8822B) & BIT_MASK_DTIM_PERIOD4_8822B)
+#define BIT_SET_DTIM_PERIOD4_8822B(x, v)                                       \
+	(BIT_CLEAR_DTIM_PERIOD4_8822B(x) | BIT_DTIM_PERIOD4_8822B(v))
+
+#define BIT_DTIM4_8822B BIT(15)
+#define BIT_TIM4_8822B BIT(14)
+
+#define BIT_SHIFT_PS_AID_4_8822B 0
+#define BIT_MASK_PS_AID_4_8822B 0x7ff
+#define BIT_PS_AID_4_8822B(x)                                                  \
+	(((x) & BIT_MASK_PS_AID_4_8822B) << BIT_SHIFT_PS_AID_4_8822B)
+#define BITS_PS_AID_4_8822B                                                    \
+	(BIT_MASK_PS_AID_4_8822B << BIT_SHIFT_PS_AID_4_8822B)
+#define BIT_CLEAR_PS_AID_4_8822B(x) ((x) & (~BITS_PS_AID_4_8822B))
+#define BIT_GET_PS_AID_4_8822B(x)                                              \
+	(((x) >> BIT_SHIFT_PS_AID_4_8822B) & BIT_MASK_PS_AID_4_8822B)
+#define BIT_SET_PS_AID_4_8822B(x, v)                                           \
+	(BIT_CLEAR_PS_AID_4_8822B(x) | BIT_PS_AID_4_8822B(v))
+
+/* 2 REG_A1_ADDR_MASK_8822B (A1 ADDR MASK REGISTER) */
+
+#define BIT_SHIFT_A1_ADDR_MASK_8822B 0
+#define BIT_MASK_A1_ADDR_MASK_8822B 0xffffffffL
+#define BIT_A1_ADDR_MASK_8822B(x)                                              \
+	(((x) & BIT_MASK_A1_ADDR_MASK_8822B) << BIT_SHIFT_A1_ADDR_MASK_8822B)
+#define BITS_A1_ADDR_MASK_8822B                                                \
+	(BIT_MASK_A1_ADDR_MASK_8822B << BIT_SHIFT_A1_ADDR_MASK_8822B)
+#define BIT_CLEAR_A1_ADDR_MASK_8822B(x) ((x) & (~BITS_A1_ADDR_MASK_8822B))
+#define BIT_GET_A1_ADDR_MASK_8822B(x)                                          \
+	(((x) >> BIT_SHIFT_A1_ADDR_MASK_8822B) & BIT_MASK_A1_ADDR_MASK_8822B)
+#define BIT_SET_A1_ADDR_MASK_8822B(x, v)                                       \
+	(BIT_CLEAR_A1_ADDR_MASK_8822B(x) | BIT_A1_ADDR_MASK_8822B(v))
+
+/* 2 REG_MACID2_8822B (MAC ID2 REGISTER) */
+
+#define BIT_SHIFT_MACID2_8822B 0
+#define BIT_MASK_MACID2_8822B 0xffffffffffffL
+#define BIT_MACID2_8822B(x)                                                    \
+	(((x) & BIT_MASK_MACID2_8822B) << BIT_SHIFT_MACID2_8822B)
+#define BITS_MACID2_8822B (BIT_MASK_MACID2_8822B << BIT_SHIFT_MACID2_8822B)
+#define BIT_CLEAR_MACID2_8822B(x) ((x) & (~BITS_MACID2_8822B))
+#define BIT_GET_MACID2_8822B(x)                                                \
+	(((x) >> BIT_SHIFT_MACID2_8822B) & BIT_MASK_MACID2_8822B)
+#define BIT_SET_MACID2_8822B(x, v)                                             \
+	(BIT_CLEAR_MACID2_8822B(x) | BIT_MACID2_8822B(v))
+
+/* 2 REG_BSSID2_8822B (BSSID2 REGISTER) */
+
+#define BIT_SHIFT_BSSID2_8822B 0
+#define BIT_MASK_BSSID2_8822B 0xffffffffffffL
+#define BIT_BSSID2_8822B(x)                                                    \
+	(((x) & BIT_MASK_BSSID2_8822B) << BIT_SHIFT_BSSID2_8822B)
+#define BITS_BSSID2_8822B (BIT_MASK_BSSID2_8822B << BIT_SHIFT_BSSID2_8822B)
+#define BIT_CLEAR_BSSID2_8822B(x) ((x) & (~BITS_BSSID2_8822B))
+#define BIT_GET_BSSID2_8822B(x)                                                \
+	(((x) >> BIT_SHIFT_BSSID2_8822B) & BIT_MASK_BSSID2_8822B)
+#define BIT_SET_BSSID2_8822B(x, v)                                             \
+	(BIT_CLEAR_BSSID2_8822B(x) | BIT_BSSID2_8822B(v))
+
+/* 2 REG_MACID3_8822B (MAC ID3 REGISTER) */
+
+#define BIT_SHIFT_MACID3_8822B 0
+#define BIT_MASK_MACID3_8822B 0xffffffffffffL
+#define BIT_MACID3_8822B(x)                                                    \
+	(((x) & BIT_MASK_MACID3_8822B) << BIT_SHIFT_MACID3_8822B)
+#define BITS_MACID3_8822B (BIT_MASK_MACID3_8822B << BIT_SHIFT_MACID3_8822B)
+#define BIT_CLEAR_MACID3_8822B(x) ((x) & (~BITS_MACID3_8822B))
+#define BIT_GET_MACID3_8822B(x)                                                \
+	(((x) >> BIT_SHIFT_MACID3_8822B) & BIT_MASK_MACID3_8822B)
+#define BIT_SET_MACID3_8822B(x, v)                                             \
+	(BIT_CLEAR_MACID3_8822B(x) | BIT_MACID3_8822B(v))
+
+/* 2 REG_BSSID3_8822B (BSSID3 REGISTER) */
+
+#define BIT_SHIFT_BSSID3_8822B 0
+#define BIT_MASK_BSSID3_8822B 0xffffffffffffL
+#define BIT_BSSID3_8822B(x)                                                    \
+	(((x) & BIT_MASK_BSSID3_8822B) << BIT_SHIFT_BSSID3_8822B)
+#define BITS_BSSID3_8822B (BIT_MASK_BSSID3_8822B << BIT_SHIFT_BSSID3_8822B)
+#define BIT_CLEAR_BSSID3_8822B(x) ((x) & (~BITS_BSSID3_8822B))
+#define BIT_GET_BSSID3_8822B(x)                                                \
+	(((x) >> BIT_SHIFT_BSSID3_8822B) & BIT_MASK_BSSID3_8822B)
+#define BIT_SET_BSSID3_8822B(x, v)                                             \
+	(BIT_CLEAR_BSSID3_8822B(x) | BIT_BSSID3_8822B(v))
+
+/* 2 REG_MACID4_8822B (MAC ID4 REGISTER) */
+
+#define BIT_SHIFT_MACID4_8822B 0
+#define BIT_MASK_MACID4_8822B 0xffffffffffffL
+#define BIT_MACID4_8822B(x)                                                    \
+	(((x) & BIT_MASK_MACID4_8822B) << BIT_SHIFT_MACID4_8822B)
+#define BITS_MACID4_8822B (BIT_MASK_MACID4_8822B << BIT_SHIFT_MACID4_8822B)
+#define BIT_CLEAR_MACID4_8822B(x) ((x) & (~BITS_MACID4_8822B))
+#define BIT_GET_MACID4_8822B(x)                                                \
+	(((x) >> BIT_SHIFT_MACID4_8822B) & BIT_MASK_MACID4_8822B)
+#define BIT_SET_MACID4_8822B(x, v)                                             \
+	(BIT_CLEAR_MACID4_8822B(x) | BIT_MACID4_8822B(v))
+
+/* 2 REG_BSSID4_8822B (BSSID4 REGISTER) */
+
+#define BIT_SHIFT_BSSID4_8822B 0
+#define BIT_MASK_BSSID4_8822B 0xffffffffffffL
+#define BIT_BSSID4_8822B(x)                                                    \
+	(((x) & BIT_MASK_BSSID4_8822B) << BIT_SHIFT_BSSID4_8822B)
+#define BITS_BSSID4_8822B (BIT_MASK_BSSID4_8822B << BIT_SHIFT_BSSID4_8822B)
+#define BIT_CLEAR_BSSID4_8822B(x) ((x) & (~BITS_BSSID4_8822B))
+#define BIT_GET_BSSID4_8822B(x)                                                \
+	(((x) >> BIT_SHIFT_BSSID4_8822B) & BIT_MASK_BSSID4_8822B)
+#define BIT_SET_BSSID4_8822B(x, v)                                             \
+	(BIT_CLEAR_BSSID4_8822B(x) | BIT_BSSID4_8822B(v))
+
+/* 2 REG_NOA_REPORT_8822B */
+
+/* 2 REG_PWRBIT_SETTING_8822B */
+#define BIT_CLI3_PWRBIT_OW_EN_8822B BIT(7)
+#define BIT_CLI3_PWR_ST_8822B BIT(6)
+#define BIT_CLI2_PWRBIT_OW_EN_8822B BIT(5)
+#define BIT_CLI2_PWR_ST_8822B BIT(4)
+#define BIT_CLI1_PWRBIT_OW_EN_8822B BIT(3)
+#define BIT_CLI1_PWR_ST_8822B BIT(2)
+#define BIT_CLI0_PWRBIT_OW_EN_8822B BIT(1)
+#define BIT_CLI0_PWR_ST_8822B BIT(0)
+
+/* 2 REG_WMAC_MU_BF_OPTION_8822B */
+#define BIT_WMAC_RESP_NONSTA1_DIS_8822B BIT(7)
+#define BIT_BIT_WMAC_TXMU_ACKPOLICY_EN_8822B BIT(6)
+
+#define BIT_SHIFT_WMAC_TXMU_ACKPOLICY_8822B 4
+#define BIT_MASK_WMAC_TXMU_ACKPOLICY_8822B 0x3
+#define BIT_WMAC_TXMU_ACKPOLICY_8822B(x)                                       \
+	(((x) & BIT_MASK_WMAC_TXMU_ACKPOLICY_8822B)                            \
+	 << BIT_SHIFT_WMAC_TXMU_ACKPOLICY_8822B)
+#define BITS_WMAC_TXMU_ACKPOLICY_8822B                                         \
+	(BIT_MASK_WMAC_TXMU_ACKPOLICY_8822B                                    \
+	 << BIT_SHIFT_WMAC_TXMU_ACKPOLICY_8822B)
+#define BIT_CLEAR_WMAC_TXMU_ACKPOLICY_8822B(x)                                 \
+	((x) & (~BITS_WMAC_TXMU_ACKPOLICY_8822B))
+#define BIT_GET_WMAC_TXMU_ACKPOLICY_8822B(x)                                   \
+	(((x) >> BIT_SHIFT_WMAC_TXMU_ACKPOLICY_8822B) &                        \
+	 BIT_MASK_WMAC_TXMU_ACKPOLICY_8822B)
+#define BIT_SET_WMAC_TXMU_ACKPOLICY_8822B(x, v)                                \
+	(BIT_CLEAR_WMAC_TXMU_ACKPOLICY_8822B(x) |                              \
+	 BIT_WMAC_TXMU_ACKPOLICY_8822B(v))
+
+#define BIT_SHIFT_WMAC_MU_BFEE_PORT_SEL_8822B 1
+#define BIT_MASK_WMAC_MU_BFEE_PORT_SEL_8822B 0x7
+#define BIT_WMAC_MU_BFEE_PORT_SEL_8822B(x)                                     \
+	(((x) & BIT_MASK_WMAC_MU_BFEE_PORT_SEL_8822B)                          \
+	 << BIT_SHIFT_WMAC_MU_BFEE_PORT_SEL_8822B)
+#define BITS_WMAC_MU_BFEE_PORT_SEL_8822B                                       \
+	(BIT_MASK_WMAC_MU_BFEE_PORT_SEL_8822B                                  \
+	 << BIT_SHIFT_WMAC_MU_BFEE_PORT_SEL_8822B)
+#define BIT_CLEAR_WMAC_MU_BFEE_PORT_SEL_8822B(x)                               \
+	((x) & (~BITS_WMAC_MU_BFEE_PORT_SEL_8822B))
+#define BIT_GET_WMAC_MU_BFEE_PORT_SEL_8822B(x)                                 \
+	(((x) >> BIT_SHIFT_WMAC_MU_BFEE_PORT_SEL_8822B) &                      \
+	 BIT_MASK_WMAC_MU_BFEE_PORT_SEL_8822B)
+#define BIT_SET_WMAC_MU_BFEE_PORT_SEL_8822B(x, v)                              \
+	(BIT_CLEAR_WMAC_MU_BFEE_PORT_SEL_8822B(x) |                            \
+	 BIT_WMAC_MU_BFEE_PORT_SEL_8822B(v))
+
+#define BIT_WMAC_MU_BFEE_DIS_8822B BIT(0)
+
+/* 2 REG_NOT_VALID_8822B */
+
+#define BIT_SHIFT_WMAC_PAUSE_BB_CLR_TH_8822B 0
+#define BIT_MASK_WMAC_PAUSE_BB_CLR_TH_8822B 0xff
+#define BIT_WMAC_PAUSE_BB_CLR_TH_8822B(x)                                      \
+	(((x) & BIT_MASK_WMAC_PAUSE_BB_CLR_TH_8822B)                           \
+	 << BIT_SHIFT_WMAC_PAUSE_BB_CLR_TH_8822B)
+#define BITS_WMAC_PAUSE_BB_CLR_TH_8822B                                        \
+	(BIT_MASK_WMAC_PAUSE_BB_CLR_TH_8822B                                   \
+	 << BIT_SHIFT_WMAC_PAUSE_BB_CLR_TH_8822B)
+#define BIT_CLEAR_WMAC_PAUSE_BB_CLR_TH_8822B(x)                                \
+	((x) & (~BITS_WMAC_PAUSE_BB_CLR_TH_8822B))
+#define BIT_GET_WMAC_PAUSE_BB_CLR_TH_8822B(x)                                  \
+	(((x) >> BIT_SHIFT_WMAC_PAUSE_BB_CLR_TH_8822B) &                       \
+	 BIT_MASK_WMAC_PAUSE_BB_CLR_TH_8822B)
+#define BIT_SET_WMAC_PAUSE_BB_CLR_TH_8822B(x, v)                               \
+	(BIT_CLEAR_WMAC_PAUSE_BB_CLR_TH_8822B(x) |                             \
+	 BIT_WMAC_PAUSE_BB_CLR_TH_8822B(v))
+
+/* 2 REG_WMAC_MU_ARB_8822B */
+#define BIT_WMAC_ARB_HW_ADAPT_EN_8822B BIT(7)
+#define BIT_WMAC_ARB_SW_EN_8822B BIT(6)
+
+#define BIT_SHIFT_WMAC_ARB_SW_STATE_8822B 0
+#define BIT_MASK_WMAC_ARB_SW_STATE_8822B 0x3f
+#define BIT_WMAC_ARB_SW_STATE_8822B(x)                                         \
+	(((x) & BIT_MASK_WMAC_ARB_SW_STATE_8822B)                              \
+	 << BIT_SHIFT_WMAC_ARB_SW_STATE_8822B)
+#define BITS_WMAC_ARB_SW_STATE_8822B                                           \
+	(BIT_MASK_WMAC_ARB_SW_STATE_8822B << BIT_SHIFT_WMAC_ARB_SW_STATE_8822B)
+#define BIT_CLEAR_WMAC_ARB_SW_STATE_8822B(x)                                   \
+	((x) & (~BITS_WMAC_ARB_SW_STATE_8822B))
+#define BIT_GET_WMAC_ARB_SW_STATE_8822B(x)                                     \
+	(((x) >> BIT_SHIFT_WMAC_ARB_SW_STATE_8822B) &                          \
+	 BIT_MASK_WMAC_ARB_SW_STATE_8822B)
+#define BIT_SET_WMAC_ARB_SW_STATE_8822B(x, v)                                  \
+	(BIT_CLEAR_WMAC_ARB_SW_STATE_8822B(x) | BIT_WMAC_ARB_SW_STATE_8822B(v))
+
+/* 2 REG_WMAC_MU_OPTION_8822B */
+
+#define BIT_SHIFT_WMAC_MU_DBGSEL_8822B 5
+#define BIT_MASK_WMAC_MU_DBGSEL_8822B 0x3
+#define BIT_WMAC_MU_DBGSEL_8822B(x)                                            \
+	(((x) & BIT_MASK_WMAC_MU_DBGSEL_8822B)                                 \
+	 << BIT_SHIFT_WMAC_MU_DBGSEL_8822B)
+#define BITS_WMAC_MU_DBGSEL_8822B                                              \
+	(BIT_MASK_WMAC_MU_DBGSEL_8822B << BIT_SHIFT_WMAC_MU_DBGSEL_8822B)
+#define BIT_CLEAR_WMAC_MU_DBGSEL_8822B(x) ((x) & (~BITS_WMAC_MU_DBGSEL_8822B))
+#define BIT_GET_WMAC_MU_DBGSEL_8822B(x)                                        \
+	(((x) >> BIT_SHIFT_WMAC_MU_DBGSEL_8822B) &                             \
+	 BIT_MASK_WMAC_MU_DBGSEL_8822B)
+#define BIT_SET_WMAC_MU_DBGSEL_8822B(x, v)                                     \
+	(BIT_CLEAR_WMAC_MU_DBGSEL_8822B(x) | BIT_WMAC_MU_DBGSEL_8822B(v))
+
+#define BIT_SHIFT_WMAC_MU_CPRD_TIMEOUT_8822B 0
+#define BIT_MASK_WMAC_MU_CPRD_TIMEOUT_8822B 0x1f
+#define BIT_WMAC_MU_CPRD_TIMEOUT_8822B(x)                                      \
+	(((x) & BIT_MASK_WMAC_MU_CPRD_TIMEOUT_8822B)                           \
+	 << BIT_SHIFT_WMAC_MU_CPRD_TIMEOUT_8822B)
+#define BITS_WMAC_MU_CPRD_TIMEOUT_8822B                                        \
+	(BIT_MASK_WMAC_MU_CPRD_TIMEOUT_8822B                                   \
+	 << BIT_SHIFT_WMAC_MU_CPRD_TIMEOUT_8822B)
+#define BIT_CLEAR_WMAC_MU_CPRD_TIMEOUT_8822B(x)                                \
+	((x) & (~BITS_WMAC_MU_CPRD_TIMEOUT_8822B))
+#define BIT_GET_WMAC_MU_CPRD_TIMEOUT_8822B(x)                                  \
+	(((x) >> BIT_SHIFT_WMAC_MU_CPRD_TIMEOUT_8822B) &                       \
+	 BIT_MASK_WMAC_MU_CPRD_TIMEOUT_8822B)
+#define BIT_SET_WMAC_MU_CPRD_TIMEOUT_8822B(x, v)                               \
+	(BIT_CLEAR_WMAC_MU_CPRD_TIMEOUT_8822B(x) |                             \
+	 BIT_WMAC_MU_CPRD_TIMEOUT_8822B(v))
+
+/* 2 REG_WMAC_MU_BF_CTL_8822B */
+#define BIT_WMAC_INVLD_BFPRT_CHK_8822B BIT(15)
+#define BIT_WMAC_RETXBFRPTSEQ_UPD_8822B BIT(14)
+
+#define BIT_SHIFT_WMAC_MU_BFRPTSEG_SEL_8822B 12
+#define BIT_MASK_WMAC_MU_BFRPTSEG_SEL_8822B 0x3
+#define BIT_WMAC_MU_BFRPTSEG_SEL_8822B(x)                                      \
+	(((x) & BIT_MASK_WMAC_MU_BFRPTSEG_SEL_8822B)                           \
+	 << BIT_SHIFT_WMAC_MU_BFRPTSEG_SEL_8822B)
+#define BITS_WMAC_MU_BFRPTSEG_SEL_8822B                                        \
+	(BIT_MASK_WMAC_MU_BFRPTSEG_SEL_8822B                                   \
+	 << BIT_SHIFT_WMAC_MU_BFRPTSEG_SEL_8822B)
+#define BIT_CLEAR_WMAC_MU_BFRPTSEG_SEL_8822B(x)                                \
+	((x) & (~BITS_WMAC_MU_BFRPTSEG_SEL_8822B))
+#define BIT_GET_WMAC_MU_BFRPTSEG_SEL_8822B(x)                                  \
+	(((x) >> BIT_SHIFT_WMAC_MU_BFRPTSEG_SEL_8822B) &                       \
+	 BIT_MASK_WMAC_MU_BFRPTSEG_SEL_8822B)
+#define BIT_SET_WMAC_MU_BFRPTSEG_SEL_8822B(x, v)                               \
+	(BIT_CLEAR_WMAC_MU_BFRPTSEG_SEL_8822B(x) |                             \
+	 BIT_WMAC_MU_BFRPTSEG_SEL_8822B(v))
+
+#define BIT_SHIFT_WMAC_MU_BF_MYAID_8822B 0
+#define BIT_MASK_WMAC_MU_BF_MYAID_8822B 0xfff
+#define BIT_WMAC_MU_BF_MYAID_8822B(x)                                          \
+	(((x) & BIT_MASK_WMAC_MU_BF_MYAID_8822B)                               \
+	 << BIT_SHIFT_WMAC_MU_BF_MYAID_8822B)
+#define BITS_WMAC_MU_BF_MYAID_8822B                                            \
+	(BIT_MASK_WMAC_MU_BF_MYAID_8822B << BIT_SHIFT_WMAC_MU_BF_MYAID_8822B)
+#define BIT_CLEAR_WMAC_MU_BF_MYAID_8822B(x)                                    \
+	((x) & (~BITS_WMAC_MU_BF_MYAID_8822B))
+#define BIT_GET_WMAC_MU_BF_MYAID_8822B(x)                                      \
+	(((x) >> BIT_SHIFT_WMAC_MU_BF_MYAID_8822B) &                           \
+	 BIT_MASK_WMAC_MU_BF_MYAID_8822B)
+#define BIT_SET_WMAC_MU_BF_MYAID_8822B(x, v)                                   \
+	(BIT_CLEAR_WMAC_MU_BF_MYAID_8822B(x) | BIT_WMAC_MU_BF_MYAID_8822B(v))
+
+/* 2 REG_WMAC_MU_BFRPT_PARA_8822B */
+
+#define BIT_SHIFT_BIT_BFRPT_PARA_USERID_SEL_8822B 12
+#define BIT_MASK_BIT_BFRPT_PARA_USERID_SEL_8822B 0x7
+#define BIT_BIT_BFRPT_PARA_USERID_SEL_8822B(x)                                 \
+	(((x) & BIT_MASK_BIT_BFRPT_PARA_USERID_SEL_8822B)                      \
+	 << BIT_SHIFT_BIT_BFRPT_PARA_USERID_SEL_8822B)
+#define BITS_BIT_BFRPT_PARA_USERID_SEL_8822B                                   \
+	(BIT_MASK_BIT_BFRPT_PARA_USERID_SEL_8822B                              \
+	 << BIT_SHIFT_BIT_BFRPT_PARA_USERID_SEL_8822B)
+#define BIT_CLEAR_BIT_BFRPT_PARA_USERID_SEL_8822B(x)                           \
+	((x) & (~BITS_BIT_BFRPT_PARA_USERID_SEL_8822B))
+#define BIT_GET_BIT_BFRPT_PARA_USERID_SEL_8822B(x)                             \
+	(((x) >> BIT_SHIFT_BIT_BFRPT_PARA_USERID_SEL_8822B) &                  \
+	 BIT_MASK_BIT_BFRPT_PARA_USERID_SEL_8822B)
+#define BIT_SET_BIT_BFRPT_PARA_USERID_SEL_8822B(x, v)                          \
+	(BIT_CLEAR_BIT_BFRPT_PARA_USERID_SEL_8822B(x) |                        \
+	 BIT_BIT_BFRPT_PARA_USERID_SEL_8822B(v))
+
+#define BIT_SHIFT_BFRPT_PARA_8822B 0
+#define BIT_MASK_BFRPT_PARA_8822B 0xfff
+#define BIT_BFRPT_PARA_8822B(x)                                                \
+	(((x) & BIT_MASK_BFRPT_PARA_8822B) << BIT_SHIFT_BFRPT_PARA_8822B)
+#define BITS_BFRPT_PARA_8822B                                                  \
+	(BIT_MASK_BFRPT_PARA_8822B << BIT_SHIFT_BFRPT_PARA_8822B)
+#define BIT_CLEAR_BFRPT_PARA_8822B(x) ((x) & (~BITS_BFRPT_PARA_8822B))
+#define BIT_GET_BFRPT_PARA_8822B(x)                                            \
+	(((x) >> BIT_SHIFT_BFRPT_PARA_8822B) & BIT_MASK_BFRPT_PARA_8822B)
+#define BIT_SET_BFRPT_PARA_8822B(x, v)                                         \
+	(BIT_CLEAR_BFRPT_PARA_8822B(x) | BIT_BFRPT_PARA_8822B(v))
+
+/* 2 REG_WMAC_ASSOCIATED_MU_BFMEE2_8822B */
+#define BIT_STATUS_BFEE2_8822B BIT(10)
+#define BIT_WMAC_MU_BFEE2_EN_8822B BIT(9)
+
+#define BIT_SHIFT_WMAC_MU_BFEE2_AID_8822B 0
+#define BIT_MASK_WMAC_MU_BFEE2_AID_8822B 0x1ff
+#define BIT_WMAC_MU_BFEE2_AID_8822B(x)                                         \
+	(((x) & BIT_MASK_WMAC_MU_BFEE2_AID_8822B)                              \
+	 << BIT_SHIFT_WMAC_MU_BFEE2_AID_8822B)
+#define BITS_WMAC_MU_BFEE2_AID_8822B                                           \
+	(BIT_MASK_WMAC_MU_BFEE2_AID_8822B << BIT_SHIFT_WMAC_MU_BFEE2_AID_8822B)
+#define BIT_CLEAR_WMAC_MU_BFEE2_AID_8822B(x)                                   \
+	((x) & (~BITS_WMAC_MU_BFEE2_AID_8822B))
+#define BIT_GET_WMAC_MU_BFEE2_AID_8822B(x)                                     \
+	(((x) >> BIT_SHIFT_WMAC_MU_BFEE2_AID_8822B) &                          \
+	 BIT_MASK_WMAC_MU_BFEE2_AID_8822B)
+#define BIT_SET_WMAC_MU_BFEE2_AID_8822B(x, v)                                  \
+	(BIT_CLEAR_WMAC_MU_BFEE2_AID_8822B(x) | BIT_WMAC_MU_BFEE2_AID_8822B(v))
+
+/* 2 REG_WMAC_ASSOCIATED_MU_BFMEE3_8822B */
+#define BIT_STATUS_BFEE3_8822B BIT(10)
+#define BIT_WMAC_MU_BFEE3_EN_8822B BIT(9)
+
+#define BIT_SHIFT_WMAC_MU_BFEE3_AID_8822B 0
+#define BIT_MASK_WMAC_MU_BFEE3_AID_8822B 0x1ff
+#define BIT_WMAC_MU_BFEE3_AID_8822B(x)                                         \
+	(((x) & BIT_MASK_WMAC_MU_BFEE3_AID_8822B)                              \
+	 << BIT_SHIFT_WMAC_MU_BFEE3_AID_8822B)
+#define BITS_WMAC_MU_BFEE3_AID_8822B                                           \
+	(BIT_MASK_WMAC_MU_BFEE3_AID_8822B << BIT_SHIFT_WMAC_MU_BFEE3_AID_8822B)
+#define BIT_CLEAR_WMAC_MU_BFEE3_AID_8822B(x)                                   \
+	((x) & (~BITS_WMAC_MU_BFEE3_AID_8822B))
+#define BIT_GET_WMAC_MU_BFEE3_AID_8822B(x)                                     \
+	(((x) >> BIT_SHIFT_WMAC_MU_BFEE3_AID_8822B) &                          \
+	 BIT_MASK_WMAC_MU_BFEE3_AID_8822B)
+#define BIT_SET_WMAC_MU_BFEE3_AID_8822B(x, v)                                  \
+	(BIT_CLEAR_WMAC_MU_BFEE3_AID_8822B(x) | BIT_WMAC_MU_BFEE3_AID_8822B(v))
+
+/* 2 REG_WMAC_ASSOCIATED_MU_BFMEE4_8822B */
+#define BIT_STATUS_BFEE4_8822B BIT(10)
+#define BIT_WMAC_MU_BFEE4_EN_8822B BIT(9)
+
+#define BIT_SHIFT_WMAC_MU_BFEE4_AID_8822B 0
+#define BIT_MASK_WMAC_MU_BFEE4_AID_8822B 0x1ff
+#define BIT_WMAC_MU_BFEE4_AID_8822B(x)                                         \
+	(((x) & BIT_MASK_WMAC_MU_BFEE4_AID_8822B)                              \
+	 << BIT_SHIFT_WMAC_MU_BFEE4_AID_8822B)
+#define BITS_WMAC_MU_BFEE4_AID_8822B                                           \
+	(BIT_MASK_WMAC_MU_BFEE4_AID_8822B << BIT_SHIFT_WMAC_MU_BFEE4_AID_8822B)
+#define BIT_CLEAR_WMAC_MU_BFEE4_AID_8822B(x)                                   \
+	((x) & (~BITS_WMAC_MU_BFEE4_AID_8822B))
+#define BIT_GET_WMAC_MU_BFEE4_AID_8822B(x)                                     \
+	(((x) >> BIT_SHIFT_WMAC_MU_BFEE4_AID_8822B) &                          \
+	 BIT_MASK_WMAC_MU_BFEE4_AID_8822B)
+#define BIT_SET_WMAC_MU_BFEE4_AID_8822B(x, v)                                  \
+	(BIT_CLEAR_WMAC_MU_BFEE4_AID_8822B(x) | BIT_WMAC_MU_BFEE4_AID_8822B(v))
+
+/* 2 REG_WMAC_ASSOCIATED_MU_BFMEE5_8822B */
+#define BIT_STATUS_BFEE5_8822B BIT(10)
+#define BIT_WMAC_MU_BFEE5_EN_8822B BIT(9)
+
+#define BIT_SHIFT_WMAC_MU_BFEE5_AID_8822B 0
+#define BIT_MASK_WMAC_MU_BFEE5_AID_8822B 0x1ff
+#define BIT_WMAC_MU_BFEE5_AID_8822B(x)                                         \
+	(((x) & BIT_MASK_WMAC_MU_BFEE5_AID_8822B)                              \
+	 << BIT_SHIFT_WMAC_MU_BFEE5_AID_8822B)
+#define BITS_WMAC_MU_BFEE5_AID_8822B                                           \
+	(BIT_MASK_WMAC_MU_BFEE5_AID_8822B << BIT_SHIFT_WMAC_MU_BFEE5_AID_8822B)
+#define BIT_CLEAR_WMAC_MU_BFEE5_AID_8822B(x)                                   \
+	((x) & (~BITS_WMAC_MU_BFEE5_AID_8822B))
+#define BIT_GET_WMAC_MU_BFEE5_AID_8822B(x)                                     \
+	(((x) >> BIT_SHIFT_WMAC_MU_BFEE5_AID_8822B) &                          \
+	 BIT_MASK_WMAC_MU_BFEE5_AID_8822B)
+#define BIT_SET_WMAC_MU_BFEE5_AID_8822B(x, v)                                  \
+	(BIT_CLEAR_WMAC_MU_BFEE5_AID_8822B(x) | BIT_WMAC_MU_BFEE5_AID_8822B(v))
+
+/* 2 REG_WMAC_ASSOCIATED_MU_BFMEE6_8822B */
+#define BIT_STATUS_BFEE6_8822B BIT(10)
+#define BIT_WMAC_MU_BFEE6_EN_8822B BIT(9)
+
+#define BIT_SHIFT_WMAC_MU_BFEE6_AID_8822B 0
+#define BIT_MASK_WMAC_MU_BFEE6_AID_8822B 0x1ff
+#define BIT_WMAC_MU_BFEE6_AID_8822B(x)                                         \
+	(((x) & BIT_MASK_WMAC_MU_BFEE6_AID_8822B)                              \
+	 << BIT_SHIFT_WMAC_MU_BFEE6_AID_8822B)
+#define BITS_WMAC_MU_BFEE6_AID_8822B                                           \
+	(BIT_MASK_WMAC_MU_BFEE6_AID_8822B << BIT_SHIFT_WMAC_MU_BFEE6_AID_8822B)
+#define BIT_CLEAR_WMAC_MU_BFEE6_AID_8822B(x)                                   \
+	((x) & (~BITS_WMAC_MU_BFEE6_AID_8822B))
+#define BIT_GET_WMAC_MU_BFEE6_AID_8822B(x)                                     \
+	(((x) >> BIT_SHIFT_WMAC_MU_BFEE6_AID_8822B) &                          \
+	 BIT_MASK_WMAC_MU_BFEE6_AID_8822B)
+#define BIT_SET_WMAC_MU_BFEE6_AID_8822B(x, v)                                  \
+	(BIT_CLEAR_WMAC_MU_BFEE6_AID_8822B(x) | BIT_WMAC_MU_BFEE6_AID_8822B(v))
+
+/* 2 REG_WMAC_ASSOCIATED_MU_BFMEE7_8822B */
+#define BIT_STATUS_BFEE7_8822B BIT(10)
+#define BIT_WMAC_MU_BFEE7_EN_8822B BIT(9)
+
+#define BIT_SHIFT_WMAC_MU_BFEE7_AID_8822B 0
+#define BIT_MASK_WMAC_MU_BFEE7_AID_8822B 0x1ff
+#define BIT_WMAC_MU_BFEE7_AID_8822B(x)                                         \
+	(((x) & BIT_MASK_WMAC_MU_BFEE7_AID_8822B)                              \
+	 << BIT_SHIFT_WMAC_MU_BFEE7_AID_8822B)
+#define BITS_WMAC_MU_BFEE7_AID_8822B                                           \
+	(BIT_MASK_WMAC_MU_BFEE7_AID_8822B << BIT_SHIFT_WMAC_MU_BFEE7_AID_8822B)
+#define BIT_CLEAR_WMAC_MU_BFEE7_AID_8822B(x)                                   \
+	((x) & (~BITS_WMAC_MU_BFEE7_AID_8822B))
+#define BIT_GET_WMAC_MU_BFEE7_AID_8822B(x)                                     \
+	(((x) >> BIT_SHIFT_WMAC_MU_BFEE7_AID_8822B) &                          \
+	 BIT_MASK_WMAC_MU_BFEE7_AID_8822B)
+#define BIT_SET_WMAC_MU_BFEE7_AID_8822B(x, v)                                  \
+	(BIT_CLEAR_WMAC_MU_BFEE7_AID_8822B(x) | BIT_WMAC_MU_BFEE7_AID_8822B(v))
+
+/* 2 REG_NOT_VALID_8822B */
+#define BIT_RST_ALL_COUNTER_8822B BIT(31)
+
+#define BIT_SHIFT_ABORT_RX_VBON_COUNTER_8822B 16
+#define BIT_MASK_ABORT_RX_VBON_COUNTER_8822B 0xff
+#define BIT_ABORT_RX_VBON_COUNTER_8822B(x)                                     \
+	(((x) & BIT_MASK_ABORT_RX_VBON_COUNTER_8822B)                          \
+	 << BIT_SHIFT_ABORT_RX_VBON_COUNTER_8822B)
+#define BITS_ABORT_RX_VBON_COUNTER_8822B                                       \
+	(BIT_MASK_ABORT_RX_VBON_COUNTER_8822B                                  \
+	 << BIT_SHIFT_ABORT_RX_VBON_COUNTER_8822B)
+#define BIT_CLEAR_ABORT_RX_VBON_COUNTER_8822B(x)                               \
+	((x) & (~BITS_ABORT_RX_VBON_COUNTER_8822B))
+#define BIT_GET_ABORT_RX_VBON_COUNTER_8822B(x)                                 \
+	(((x) >> BIT_SHIFT_ABORT_RX_VBON_COUNTER_8822B) &                      \
+	 BIT_MASK_ABORT_RX_VBON_COUNTER_8822B)
+#define BIT_SET_ABORT_RX_VBON_COUNTER_8822B(x, v)                              \
+	(BIT_CLEAR_ABORT_RX_VBON_COUNTER_8822B(x) |                            \
+	 BIT_ABORT_RX_VBON_COUNTER_8822B(v))
+
+#define BIT_SHIFT_ABORT_RX_RDRDY_COUNTER_8822B 8
+#define BIT_MASK_ABORT_RX_RDRDY_COUNTER_8822B 0xff
+#define BIT_ABORT_RX_RDRDY_COUNTER_8822B(x)                                    \
+	(((x) & BIT_MASK_ABORT_RX_RDRDY_COUNTER_8822B)                         \
+	 << BIT_SHIFT_ABORT_RX_RDRDY_COUNTER_8822B)
+#define BITS_ABORT_RX_RDRDY_COUNTER_8822B                                      \
+	(BIT_MASK_ABORT_RX_RDRDY_COUNTER_8822B                                 \
+	 << BIT_SHIFT_ABORT_RX_RDRDY_COUNTER_8822B)
+#define BIT_CLEAR_ABORT_RX_RDRDY_COUNTER_8822B(x)                              \
+	((x) & (~BITS_ABORT_RX_RDRDY_COUNTER_8822B))
+#define BIT_GET_ABORT_RX_RDRDY_COUNTER_8822B(x)                                \
+	(((x) >> BIT_SHIFT_ABORT_RX_RDRDY_COUNTER_8822B) &                     \
+	 BIT_MASK_ABORT_RX_RDRDY_COUNTER_8822B)
+#define BIT_SET_ABORT_RX_RDRDY_COUNTER_8822B(x, v)                             \
+	(BIT_CLEAR_ABORT_RX_RDRDY_COUNTER_8822B(x) |                           \
+	 BIT_ABORT_RX_RDRDY_COUNTER_8822B(v))
+
+#define BIT_SHIFT_VBON_EARLY_FALLING_COUNTER_8822B 0
+#define BIT_MASK_VBON_EARLY_FALLING_COUNTER_8822B 0xff
+#define BIT_VBON_EARLY_FALLING_COUNTER_8822B(x)                                \
+	(((x) & BIT_MASK_VBON_EARLY_FALLING_COUNTER_8822B)                     \
+	 << BIT_SHIFT_VBON_EARLY_FALLING_COUNTER_8822B)
+#define BITS_VBON_EARLY_FALLING_COUNTER_8822B                                  \
+	(BIT_MASK_VBON_EARLY_FALLING_COUNTER_8822B                             \
+	 << BIT_SHIFT_VBON_EARLY_FALLING_COUNTER_8822B)
+#define BIT_CLEAR_VBON_EARLY_FALLING_COUNTER_8822B(x)                          \
+	((x) & (~BITS_VBON_EARLY_FALLING_COUNTER_8822B))
+#define BIT_GET_VBON_EARLY_FALLING_COUNTER_8822B(x)                            \
+	(((x) >> BIT_SHIFT_VBON_EARLY_FALLING_COUNTER_8822B) &                 \
+	 BIT_MASK_VBON_EARLY_FALLING_COUNTER_8822B)
+#define BIT_SET_VBON_EARLY_FALLING_COUNTER_8822B(x, v)                         \
+	(BIT_CLEAR_VBON_EARLY_FALLING_COUNTER_8822B(x) |                       \
+	 BIT_VBON_EARLY_FALLING_COUNTER_8822B(v))
+
+/* 2 REG_NOT_VALID_8822B */
+#define BIT_WMAC_PLCP_TRX_SEL_8822B BIT(31)
+
+#define BIT_SHIFT_WMAC_PLCP_RDSIG_SEL_8822B 28
+#define BIT_MASK_WMAC_PLCP_RDSIG_SEL_8822B 0x7
+#define BIT_WMAC_PLCP_RDSIG_SEL_8822B(x)                                       \
+	(((x) & BIT_MASK_WMAC_PLCP_RDSIG_SEL_8822B)                            \
+	 << BIT_SHIFT_WMAC_PLCP_RDSIG_SEL_8822B)
+#define BITS_WMAC_PLCP_RDSIG_SEL_8822B                                         \
+	(BIT_MASK_WMAC_PLCP_RDSIG_SEL_8822B                                    \
+	 << BIT_SHIFT_WMAC_PLCP_RDSIG_SEL_8822B)
+#define BIT_CLEAR_WMAC_PLCP_RDSIG_SEL_8822B(x)                                 \
+	((x) & (~BITS_WMAC_PLCP_RDSIG_SEL_8822B))
+#define BIT_GET_WMAC_PLCP_RDSIG_SEL_8822B(x)                                   \
+	(((x) >> BIT_SHIFT_WMAC_PLCP_RDSIG_SEL_8822B) &                        \
+	 BIT_MASK_WMAC_PLCP_RDSIG_SEL_8822B)
+#define BIT_SET_WMAC_PLCP_RDSIG_SEL_8822B(x, v)                                \
+	(BIT_CLEAR_WMAC_PLCP_RDSIG_SEL_8822B(x) |                              \
+	 BIT_WMAC_PLCP_RDSIG_SEL_8822B(v))
+
+#define BIT_SHIFT_WMAC_RATE_IDX_8822B 24
+#define BIT_MASK_WMAC_RATE_IDX_8822B 0xf
+#define BIT_WMAC_RATE_IDX_8822B(x)                                             \
+	(((x) & BIT_MASK_WMAC_RATE_IDX_8822B) << BIT_SHIFT_WMAC_RATE_IDX_8822B)
+#define BITS_WMAC_RATE_IDX_8822B                                               \
+	(BIT_MASK_WMAC_RATE_IDX_8822B << BIT_SHIFT_WMAC_RATE_IDX_8822B)
+#define BIT_CLEAR_WMAC_RATE_IDX_8822B(x) ((x) & (~BITS_WMAC_RATE_IDX_8822B))
+#define BIT_GET_WMAC_RATE_IDX_8822B(x)                                         \
+	(((x) >> BIT_SHIFT_WMAC_RATE_IDX_8822B) & BIT_MASK_WMAC_RATE_IDX_8822B)
+#define BIT_SET_WMAC_RATE_IDX_8822B(x, v)                                      \
+	(BIT_CLEAR_WMAC_RATE_IDX_8822B(x) | BIT_WMAC_RATE_IDX_8822B(v))
+
+#define BIT_SHIFT_WMAC_PLCP_RDSIG_8822B 0
+#define BIT_MASK_WMAC_PLCP_RDSIG_8822B 0xffffff
+#define BIT_WMAC_PLCP_RDSIG_8822B(x)                                           \
+	(((x) & BIT_MASK_WMAC_PLCP_RDSIG_8822B)                                \
+	 << BIT_SHIFT_WMAC_PLCP_RDSIG_8822B)
+#define BITS_WMAC_PLCP_RDSIG_8822B                                             \
+	(BIT_MASK_WMAC_PLCP_RDSIG_8822B << BIT_SHIFT_WMAC_PLCP_RDSIG_8822B)
+#define BIT_CLEAR_WMAC_PLCP_RDSIG_8822B(x) ((x) & (~BITS_WMAC_PLCP_RDSIG_8822B))
+#define BIT_GET_WMAC_PLCP_RDSIG_8822B(x)                                       \
+	(((x) >> BIT_SHIFT_WMAC_PLCP_RDSIG_8822B) &                            \
+	 BIT_MASK_WMAC_PLCP_RDSIG_8822B)
+#define BIT_SET_WMAC_PLCP_RDSIG_8822B(x, v)                                    \
+	(BIT_CLEAR_WMAC_PLCP_RDSIG_8822B(x) | BIT_WMAC_PLCP_RDSIG_8822B(v))
+
+/* 2 REG_NOT_VALID_8822B */
+#define BIT_WMAC_MUTX_IDX_8822B BIT(24)
+
+#define BIT_SHIFT_WMAC_PLCP_RDSIG_8822B 0
+#define BIT_MASK_WMAC_PLCP_RDSIG_8822B 0xffffff
+#define BIT_WMAC_PLCP_RDSIG_8822B(x)                                           \
+	(((x) & BIT_MASK_WMAC_PLCP_RDSIG_8822B)                                \
+	 << BIT_SHIFT_WMAC_PLCP_RDSIG_8822B)
+#define BITS_WMAC_PLCP_RDSIG_8822B                                             \
+	(BIT_MASK_WMAC_PLCP_RDSIG_8822B << BIT_SHIFT_WMAC_PLCP_RDSIG_8822B)
+#define BIT_CLEAR_WMAC_PLCP_RDSIG_8822B(x) ((x) & (~BITS_WMAC_PLCP_RDSIG_8822B))
+#define BIT_GET_WMAC_PLCP_RDSIG_8822B(x)                                       \
+	(((x) >> BIT_SHIFT_WMAC_PLCP_RDSIG_8822B) &                            \
+	 BIT_MASK_WMAC_PLCP_RDSIG_8822B)
+#define BIT_SET_WMAC_PLCP_RDSIG_8822B(x, v)                                    \
+	(BIT_CLEAR_WMAC_PLCP_RDSIG_8822B(x) | BIT_WMAC_PLCP_RDSIG_8822B(v))
+
+/* 2 REG_TRANSMIT_ADDRSS_0_8822B (TA0 REGISTER) */
+
+#define BIT_SHIFT_TA0_8822B 0
+#define BIT_MASK_TA0_8822B 0xffffffffffffL
+#define BIT_TA0_8822B(x) (((x) & BIT_MASK_TA0_8822B) << BIT_SHIFT_TA0_8822B)
+#define BITS_TA0_8822B (BIT_MASK_TA0_8822B << BIT_SHIFT_TA0_8822B)
+#define BIT_CLEAR_TA0_8822B(x) ((x) & (~BITS_TA0_8822B))
+#define BIT_GET_TA0_8822B(x) (((x) >> BIT_SHIFT_TA0_8822B) & BIT_MASK_TA0_8822B)
+#define BIT_SET_TA0_8822B(x, v) (BIT_CLEAR_TA0_8822B(x) | BIT_TA0_8822B(v))
+
+/* 2 REG_TRANSMIT_ADDRSS_1_8822B (TA1 REGISTER) */
+
+#define BIT_SHIFT_TA1_8822B 0
+#define BIT_MASK_TA1_8822B 0xffffffffffffL
+#define BIT_TA1_8822B(x) (((x) & BIT_MASK_TA1_8822B) << BIT_SHIFT_TA1_8822B)
+#define BITS_TA1_8822B (BIT_MASK_TA1_8822B << BIT_SHIFT_TA1_8822B)
+#define BIT_CLEAR_TA1_8822B(x) ((x) & (~BITS_TA1_8822B))
+#define BIT_GET_TA1_8822B(x) (((x) >> BIT_SHIFT_TA1_8822B) & BIT_MASK_TA1_8822B)
+#define BIT_SET_TA1_8822B(x, v) (BIT_CLEAR_TA1_8822B(x) | BIT_TA1_8822B(v))
+
+/* 2 REG_TRANSMIT_ADDRSS_2_8822B (TA2 REGISTER) */
+
+#define BIT_SHIFT_TA2_8822B 0
+#define BIT_MASK_TA2_8822B 0xffffffffffffL
+#define BIT_TA2_8822B(x) (((x) & BIT_MASK_TA2_8822B) << BIT_SHIFT_TA2_8822B)
+#define BITS_TA2_8822B (BIT_MASK_TA2_8822B << BIT_SHIFT_TA2_8822B)
+#define BIT_CLEAR_TA2_8822B(x) ((x) & (~BITS_TA2_8822B))
+#define BIT_GET_TA2_8822B(x) (((x) >> BIT_SHIFT_TA2_8822B) & BIT_MASK_TA2_8822B)
+#define BIT_SET_TA2_8822B(x, v) (BIT_CLEAR_TA2_8822B(x) | BIT_TA2_8822B(v))
+
+/* 2 REG_TRANSMIT_ADDRSS_3_8822B (TA3 REGISTER) */
+
+#define BIT_SHIFT_TA3_8822B 0
+#define BIT_MASK_TA3_8822B 0xffffffffffffL
+#define BIT_TA3_8822B(x) (((x) & BIT_MASK_TA3_8822B) << BIT_SHIFT_TA3_8822B)
+#define BITS_TA3_8822B (BIT_MASK_TA3_8822B << BIT_SHIFT_TA3_8822B)
+#define BIT_CLEAR_TA3_8822B(x) ((x) & (~BITS_TA3_8822B))
+#define BIT_GET_TA3_8822B(x) (((x) >> BIT_SHIFT_TA3_8822B) & BIT_MASK_TA3_8822B)
+#define BIT_SET_TA3_8822B(x, v) (BIT_CLEAR_TA3_8822B(x) | BIT_TA3_8822B(v))
+
+/* 2 REG_TRANSMIT_ADDRSS_4_8822B (TA4 REGISTER) */
+
+#define BIT_SHIFT_TA4_8822B 0
+#define BIT_MASK_TA4_8822B 0xffffffffffffL
+#define BIT_TA4_8822B(x) (((x) & BIT_MASK_TA4_8822B) << BIT_SHIFT_TA4_8822B)
+#define BITS_TA4_8822B (BIT_MASK_TA4_8822B << BIT_SHIFT_TA4_8822B)
+#define BIT_CLEAR_TA4_8822B(x) ((x) & (~BITS_TA4_8822B))
+#define BIT_GET_TA4_8822B(x) (((x) >> BIT_SHIFT_TA4_8822B) & BIT_MASK_TA4_8822B)
+#define BIT_SET_TA4_8822B(x, v) (BIT_CLEAR_TA4_8822B(x) | BIT_TA4_8822B(v))
+
+/* 2 REG_NOT_VALID_8822B */
+
+/* 2 REG_MACID1_8822B */
+
+#define BIT_SHIFT_MACID1_8822B 0
+#define BIT_MASK_MACID1_8822B 0xffffffffffffL
+#define BIT_MACID1_8822B(x)                                                    \
+	(((x) & BIT_MASK_MACID1_8822B) << BIT_SHIFT_MACID1_8822B)
+#define BITS_MACID1_8822B (BIT_MASK_MACID1_8822B << BIT_SHIFT_MACID1_8822B)
+#define BIT_CLEAR_MACID1_8822B(x) ((x) & (~BITS_MACID1_8822B))
+#define BIT_GET_MACID1_8822B(x)                                                \
+	(((x) >> BIT_SHIFT_MACID1_8822B) & BIT_MASK_MACID1_8822B)
+#define BIT_SET_MACID1_8822B(x, v)                                             \
+	(BIT_CLEAR_MACID1_8822B(x) | BIT_MACID1_8822B(v))
+
+/* 2 REG_BSSID1_8822B */
+
+#define BIT_SHIFT_BSSID1_8822B 0
+#define BIT_MASK_BSSID1_8822B 0xffffffffffffL
+#define BIT_BSSID1_8822B(x)                                                    \
+	(((x) & BIT_MASK_BSSID1_8822B) << BIT_SHIFT_BSSID1_8822B)
+#define BITS_BSSID1_8822B (BIT_MASK_BSSID1_8822B << BIT_SHIFT_BSSID1_8822B)
+#define BIT_CLEAR_BSSID1_8822B(x) ((x) & (~BITS_BSSID1_8822B))
+#define BIT_GET_BSSID1_8822B(x)                                                \
+	(((x) >> BIT_SHIFT_BSSID1_8822B) & BIT_MASK_BSSID1_8822B)
+#define BIT_SET_BSSID1_8822B(x, v)                                             \
+	(BIT_CLEAR_BSSID1_8822B(x) | BIT_BSSID1_8822B(v))
+
+/* 2 REG_BCN_PSR_RPT1_8822B */
+
+#define BIT_SHIFT_DTIM_CNT1_8822B 24
+#define BIT_MASK_DTIM_CNT1_8822B 0xff
+#define BIT_DTIM_CNT1_8822B(x)                                                 \
+	(((x) & BIT_MASK_DTIM_CNT1_8822B) << BIT_SHIFT_DTIM_CNT1_8822B)
+#define BITS_DTIM_CNT1_8822B                                                   \
+	(BIT_MASK_DTIM_CNT1_8822B << BIT_SHIFT_DTIM_CNT1_8822B)
+#define BIT_CLEAR_DTIM_CNT1_8822B(x) ((x) & (~BITS_DTIM_CNT1_8822B))
+#define BIT_GET_DTIM_CNT1_8822B(x)                                             \
+	(((x) >> BIT_SHIFT_DTIM_CNT1_8822B) & BIT_MASK_DTIM_CNT1_8822B)
+#define BIT_SET_DTIM_CNT1_8822B(x, v)                                          \
+	(BIT_CLEAR_DTIM_CNT1_8822B(x) | BIT_DTIM_CNT1_8822B(v))
+
+#define BIT_SHIFT_DTIM_PERIOD1_8822B 16
+#define BIT_MASK_DTIM_PERIOD1_8822B 0xff
+#define BIT_DTIM_PERIOD1_8822B(x)                                              \
+	(((x) & BIT_MASK_DTIM_PERIOD1_8822B) << BIT_SHIFT_DTIM_PERIOD1_8822B)
+#define BITS_DTIM_PERIOD1_8822B                                                \
+	(BIT_MASK_DTIM_PERIOD1_8822B << BIT_SHIFT_DTIM_PERIOD1_8822B)
+#define BIT_CLEAR_DTIM_PERIOD1_8822B(x) ((x) & (~BITS_DTIM_PERIOD1_8822B))
+#define BIT_GET_DTIM_PERIOD1_8822B(x)                                          \
+	(((x) >> BIT_SHIFT_DTIM_PERIOD1_8822B) & BIT_MASK_DTIM_PERIOD1_8822B)
+#define BIT_SET_DTIM_PERIOD1_8822B(x, v)                                       \
+	(BIT_CLEAR_DTIM_PERIOD1_8822B(x) | BIT_DTIM_PERIOD1_8822B(v))
+
+#define BIT_DTIM1_8822B BIT(15)
+#define BIT_TIM1_8822B BIT(14)
+
+#define BIT_SHIFT_PS_AID_1_8822B 0
+#define BIT_MASK_PS_AID_1_8822B 0x7ff
+#define BIT_PS_AID_1_8822B(x)                                                  \
+	(((x) & BIT_MASK_PS_AID_1_8822B) << BIT_SHIFT_PS_AID_1_8822B)
+#define BITS_PS_AID_1_8822B                                                    \
+	(BIT_MASK_PS_AID_1_8822B << BIT_SHIFT_PS_AID_1_8822B)
+#define BIT_CLEAR_PS_AID_1_8822B(x) ((x) & (~BITS_PS_AID_1_8822B))
+#define BIT_GET_PS_AID_1_8822B(x)                                              \
+	(((x) >> BIT_SHIFT_PS_AID_1_8822B) & BIT_MASK_PS_AID_1_8822B)
+#define BIT_SET_PS_AID_1_8822B(x, v)                                           \
+	(BIT_CLEAR_PS_AID_1_8822B(x) | BIT_PS_AID_1_8822B(v))
+
+/* 2 REG_ASSOCIATED_BFMEE_SEL_8822B */
+#define BIT_TXUSER_ID1_8822B BIT(25)
+
+#define BIT_SHIFT_AID1_8822B 16
+#define BIT_MASK_AID1_8822B 0x1ff
+#define BIT_AID1_8822B(x) (((x) & BIT_MASK_AID1_8822B) << BIT_SHIFT_AID1_8822B)
+#define BITS_AID1_8822B (BIT_MASK_AID1_8822B << BIT_SHIFT_AID1_8822B)
+#define BIT_CLEAR_AID1_8822B(x) ((x) & (~BITS_AID1_8822B))
+#define BIT_GET_AID1_8822B(x)                                                  \
+	(((x) >> BIT_SHIFT_AID1_8822B) & BIT_MASK_AID1_8822B)
+#define BIT_SET_AID1_8822B(x, v) (BIT_CLEAR_AID1_8822B(x) | BIT_AID1_8822B(v))
+
+#define BIT_TXUSER_ID0_8822B BIT(9)
+
+#define BIT_SHIFT_AID0_8822B 0
+#define BIT_MASK_AID0_8822B 0x1ff
+#define BIT_AID0_8822B(x) (((x) & BIT_MASK_AID0_8822B) << BIT_SHIFT_AID0_8822B)
+#define BITS_AID0_8822B (BIT_MASK_AID0_8822B << BIT_SHIFT_AID0_8822B)
+#define BIT_CLEAR_AID0_8822B(x) ((x) & (~BITS_AID0_8822B))
+#define BIT_GET_AID0_8822B(x)                                                  \
+	(((x) >> BIT_SHIFT_AID0_8822B) & BIT_MASK_AID0_8822B)
+#define BIT_SET_AID0_8822B(x, v) (BIT_CLEAR_AID0_8822B(x) | BIT_AID0_8822B(v))
+
+/* 2 REG_SND_PTCL_CTRL_8822B */
+
+#define BIT_SHIFT_NDP_RX_STANDBY_TIMER_8822B 24
+#define BIT_MASK_NDP_RX_STANDBY_TIMER_8822B 0xff
+#define BIT_NDP_RX_STANDBY_TIMER_8822B(x)                                      \
+	(((x) & BIT_MASK_NDP_RX_STANDBY_TIMER_8822B)                           \
+	 << BIT_SHIFT_NDP_RX_STANDBY_TIMER_8822B)
+#define BITS_NDP_RX_STANDBY_TIMER_8822B                                        \
+	(BIT_MASK_NDP_RX_STANDBY_TIMER_8822B                                   \
+	 << BIT_SHIFT_NDP_RX_STANDBY_TIMER_8822B)
+#define BIT_CLEAR_NDP_RX_STANDBY_TIMER_8822B(x)                                \
+	((x) & (~BITS_NDP_RX_STANDBY_TIMER_8822B))
+#define BIT_GET_NDP_RX_STANDBY_TIMER_8822B(x)                                  \
+	(((x) >> BIT_SHIFT_NDP_RX_STANDBY_TIMER_8822B) &                       \
+	 BIT_MASK_NDP_RX_STANDBY_TIMER_8822B)
+#define BIT_SET_NDP_RX_STANDBY_TIMER_8822B(x, v)                               \
+	(BIT_CLEAR_NDP_RX_STANDBY_TIMER_8822B(x) |                             \
+	 BIT_NDP_RX_STANDBY_TIMER_8822B(v))
+
+#define BIT_SHIFT_CSI_RPT_OFFSET_HT_V1_8822B 16
+#define BIT_MASK_CSI_RPT_OFFSET_HT_V1_8822B 0x3f
+#define BIT_CSI_RPT_OFFSET_HT_V1_8822B(x)                                      \
+	(((x) & BIT_MASK_CSI_RPT_OFFSET_HT_V1_8822B)                           \
+	 << BIT_SHIFT_CSI_RPT_OFFSET_HT_V1_8822B)
+#define BITS_CSI_RPT_OFFSET_HT_V1_8822B                                        \
+	(BIT_MASK_CSI_RPT_OFFSET_HT_V1_8822B                                   \
+	 << BIT_SHIFT_CSI_RPT_OFFSET_HT_V1_8822B)
+#define BIT_CLEAR_CSI_RPT_OFFSET_HT_V1_8822B(x)                                \
+	((x) & (~BITS_CSI_RPT_OFFSET_HT_V1_8822B))
+#define BIT_GET_CSI_RPT_OFFSET_HT_V1_8822B(x)                                  \
+	(((x) >> BIT_SHIFT_CSI_RPT_OFFSET_HT_V1_8822B) &                       \
+	 BIT_MASK_CSI_RPT_OFFSET_HT_V1_8822B)
+#define BIT_SET_CSI_RPT_OFFSET_HT_V1_8822B(x, v)                               \
+	(BIT_CLEAR_CSI_RPT_OFFSET_HT_V1_8822B(x) |                             \
+	 BIT_CSI_RPT_OFFSET_HT_V1_8822B(v))
+
+#define BIT_VHTNDP_RPTPOLL_CSI_STR_OFFSET_SEL_8822B BIT(15)
+#define BIT_NDPVLD_POS_RST_FFPTR_DIS_8822B BIT(14)
+
+#define BIT_SHIFT_R_CSI_RPT_OFFSET_VHT_V1_8822B 8
+#define BIT_MASK_R_CSI_RPT_OFFSET_VHT_V1_8822B 0x3f
+#define BIT_R_CSI_RPT_OFFSET_VHT_V1_8822B(x)                                   \
+	(((x) & BIT_MASK_R_CSI_RPT_OFFSET_VHT_V1_8822B)                        \
+	 << BIT_SHIFT_R_CSI_RPT_OFFSET_VHT_V1_8822B)
+#define BITS_R_CSI_RPT_OFFSET_VHT_V1_8822B                                     \
+	(BIT_MASK_R_CSI_RPT_OFFSET_VHT_V1_8822B                                \
+	 << BIT_SHIFT_R_CSI_RPT_OFFSET_VHT_V1_8822B)
+#define BIT_CLEAR_R_CSI_RPT_OFFSET_VHT_V1_8822B(x)                             \
+	((x) & (~BITS_R_CSI_RPT_OFFSET_VHT_V1_8822B))
+#define BIT_GET_R_CSI_RPT_OFFSET_VHT_V1_8822B(x)                               \
+	(((x) >> BIT_SHIFT_R_CSI_RPT_OFFSET_VHT_V1_8822B) &                    \
+	 BIT_MASK_R_CSI_RPT_OFFSET_VHT_V1_8822B)
+#define BIT_SET_R_CSI_RPT_OFFSET_VHT_V1_8822B(x, v)                            \
+	(BIT_CLEAR_R_CSI_RPT_OFFSET_VHT_V1_8822B(x) |                          \
+	 BIT_R_CSI_RPT_OFFSET_VHT_V1_8822B(v))
+
+#define BIT_R_WMAC_USE_NSTS_8822B BIT(7)
+#define BIT_R_DISABLE_CHECK_VHTSIGB_CRC_8822B BIT(6)
+#define BIT_R_DISABLE_CHECK_VHTSIGA_CRC_8822B BIT(5)
+#define BIT_R_WMAC_BFPARAM_SEL_8822B BIT(4)
+#define BIT_R_WMAC_CSISEQ_SEL_8822B BIT(3)
+#define BIT_R_WMAC_CSI_WITHHTC_EN_8822B BIT(2)
+#define BIT_R_WMAC_HT_NDPA_EN_8822B BIT(1)
+#define BIT_R_WMAC_VHT_NDPA_EN_8822B BIT(0)
+
+/* 2 REG_RX_CSI_RPT_INFO_8822B */
+
+/* 2 REG_NS_ARP_CTRL_8822B */
+#define BIT_R_WMAC_NSARP_RSPEN_8822B BIT(15)
+#define BIT_R_WMAC_NSARP_RARP_8822B BIT(9)
+#define BIT_R_WMAC_NSARP_RIPV6_8822B BIT(8)
+
+#define BIT_SHIFT_R_WMAC_NSARP_MODEN_8822B 6
+#define BIT_MASK_R_WMAC_NSARP_MODEN_8822B 0x3
+#define BIT_R_WMAC_NSARP_MODEN_8822B(x)                                        \
+	(((x) & BIT_MASK_R_WMAC_NSARP_MODEN_8822B)                             \
+	 << BIT_SHIFT_R_WMAC_NSARP_MODEN_8822B)
+#define BITS_R_WMAC_NSARP_MODEN_8822B                                          \
+	(BIT_MASK_R_WMAC_NSARP_MODEN_8822B                                     \
+	 << BIT_SHIFT_R_WMAC_NSARP_MODEN_8822B)
+#define BIT_CLEAR_R_WMAC_NSARP_MODEN_8822B(x)                                  \
+	((x) & (~BITS_R_WMAC_NSARP_MODEN_8822B))
+#define BIT_GET_R_WMAC_NSARP_MODEN_8822B(x)                                    \
+	(((x) >> BIT_SHIFT_R_WMAC_NSARP_MODEN_8822B) &                         \
+	 BIT_MASK_R_WMAC_NSARP_MODEN_8822B)
+#define BIT_SET_R_WMAC_NSARP_MODEN_8822B(x, v)                                 \
+	(BIT_CLEAR_R_WMAC_NSARP_MODEN_8822B(x) |                               \
+	 BIT_R_WMAC_NSARP_MODEN_8822B(v))
+
+#define BIT_SHIFT_R_WMAC_NSARP_RSPFTP_8822B 4
+#define BIT_MASK_R_WMAC_NSARP_RSPFTP_8822B 0x3
+#define BIT_R_WMAC_NSARP_RSPFTP_8822B(x)                                       \
+	(((x) & BIT_MASK_R_WMAC_NSARP_RSPFTP_8822B)                            \
+	 << BIT_SHIFT_R_WMAC_NSARP_RSPFTP_8822B)
+#define BITS_R_WMAC_NSARP_RSPFTP_8822B                                         \
+	(BIT_MASK_R_WMAC_NSARP_RSPFTP_8822B                                    \
+	 << BIT_SHIFT_R_WMAC_NSARP_RSPFTP_8822B)
+#define BIT_CLEAR_R_WMAC_NSARP_RSPFTP_8822B(x)                                 \
+	((x) & (~BITS_R_WMAC_NSARP_RSPFTP_8822B))
+#define BIT_GET_R_WMAC_NSARP_RSPFTP_8822B(x)                                   \
+	(((x) >> BIT_SHIFT_R_WMAC_NSARP_RSPFTP_8822B) &                        \
+	 BIT_MASK_R_WMAC_NSARP_RSPFTP_8822B)
+#define BIT_SET_R_WMAC_NSARP_RSPFTP_8822B(x, v)                                \
+	(BIT_CLEAR_R_WMAC_NSARP_RSPFTP_8822B(x) |                              \
+	 BIT_R_WMAC_NSARP_RSPFTP_8822B(v))
+
+#define BIT_SHIFT_R_WMAC_NSARP_RSPSEC_8822B 0
+#define BIT_MASK_R_WMAC_NSARP_RSPSEC_8822B 0xf
+#define BIT_R_WMAC_NSARP_RSPSEC_8822B(x)                                       \
+	(((x) & BIT_MASK_R_WMAC_NSARP_RSPSEC_8822B)                            \
+	 << BIT_SHIFT_R_WMAC_NSARP_RSPSEC_8822B)
+#define BITS_R_WMAC_NSARP_RSPSEC_8822B                                         \
+	(BIT_MASK_R_WMAC_NSARP_RSPSEC_8822B                                    \
+	 << BIT_SHIFT_R_WMAC_NSARP_RSPSEC_8822B)
+#define BIT_CLEAR_R_WMAC_NSARP_RSPSEC_8822B(x)                                 \
+	((x) & (~BITS_R_WMAC_NSARP_RSPSEC_8822B))
+#define BIT_GET_R_WMAC_NSARP_RSPSEC_8822B(x)                                   \
+	(((x) >> BIT_SHIFT_R_WMAC_NSARP_RSPSEC_8822B) &                        \
+	 BIT_MASK_R_WMAC_NSARP_RSPSEC_8822B)
+#define BIT_SET_R_WMAC_NSARP_RSPSEC_8822B(x, v)                                \
+	(BIT_CLEAR_R_WMAC_NSARP_RSPSEC_8822B(x) |                              \
+	 BIT_R_WMAC_NSARP_RSPSEC_8822B(v))
+
+/* 2 REG_NS_ARP_INFO_8822B */
+#define BIT_REQ_IS_MCNS_8822B BIT(23)
+#define BIT_REQ_IS_UCNS_8822B BIT(22)
+#define BIT_REQ_IS_USNS_8822B BIT(21)
+#define BIT_REQ_IS_ARP_8822B BIT(20)
+#define BIT_EXPRSP_MH_WITHQC_8822B BIT(19)
+
+#define BIT_SHIFT_EXPRSP_SECTYPE_8822B 16
+#define BIT_MASK_EXPRSP_SECTYPE_8822B 0x7
+#define BIT_EXPRSP_SECTYPE_8822B(x)                                            \
+	(((x) & BIT_MASK_EXPRSP_SECTYPE_8822B)                                 \
+	 << BIT_SHIFT_EXPRSP_SECTYPE_8822B)
+#define BITS_EXPRSP_SECTYPE_8822B                                              \
+	(BIT_MASK_EXPRSP_SECTYPE_8822B << BIT_SHIFT_EXPRSP_SECTYPE_8822B)
+#define BIT_CLEAR_EXPRSP_SECTYPE_8822B(x) ((x) & (~BITS_EXPRSP_SECTYPE_8822B))
+#define BIT_GET_EXPRSP_SECTYPE_8822B(x)                                        \
+	(((x) >> BIT_SHIFT_EXPRSP_SECTYPE_8822B) &                             \
+	 BIT_MASK_EXPRSP_SECTYPE_8822B)
+#define BIT_SET_EXPRSP_SECTYPE_8822B(x, v)                                     \
+	(BIT_CLEAR_EXPRSP_SECTYPE_8822B(x) | BIT_EXPRSP_SECTYPE_8822B(v))
+
+#define BIT_SHIFT_EXPRSP_CHKSM_7_TO_0_8822B 8
+#define BIT_MASK_EXPRSP_CHKSM_7_TO_0_8822B 0xff
+#define BIT_EXPRSP_CHKSM_7_TO_0_8822B(x)                                       \
+	(((x) & BIT_MASK_EXPRSP_CHKSM_7_TO_0_8822B)                            \
+	 << BIT_SHIFT_EXPRSP_CHKSM_7_TO_0_8822B)
+#define BITS_EXPRSP_CHKSM_7_TO_0_8822B                                         \
+	(BIT_MASK_EXPRSP_CHKSM_7_TO_0_8822B                                    \
+	 << BIT_SHIFT_EXPRSP_CHKSM_7_TO_0_8822B)
+#define BIT_CLEAR_EXPRSP_CHKSM_7_TO_0_8822B(x)                                 \
+	((x) & (~BITS_EXPRSP_CHKSM_7_TO_0_8822B))
+#define BIT_GET_EXPRSP_CHKSM_7_TO_0_8822B(x)                                   \
+	(((x) >> BIT_SHIFT_EXPRSP_CHKSM_7_TO_0_8822B) &                        \
+	 BIT_MASK_EXPRSP_CHKSM_7_TO_0_8822B)
+#define BIT_SET_EXPRSP_CHKSM_7_TO_0_8822B(x, v)                                \
+	(BIT_CLEAR_EXPRSP_CHKSM_7_TO_0_8822B(x) |                              \
+	 BIT_EXPRSP_CHKSM_7_TO_0_8822B(v))
+
+#define BIT_SHIFT_EXPRSP_CHKSM_15_TO_8_8822B 0
+#define BIT_MASK_EXPRSP_CHKSM_15_TO_8_8822B 0xff
+#define BIT_EXPRSP_CHKSM_15_TO_8_8822B(x)                                      \
+	(((x) & BIT_MASK_EXPRSP_CHKSM_15_TO_8_8822B)                           \
+	 << BIT_SHIFT_EXPRSP_CHKSM_15_TO_8_8822B)
+#define BITS_EXPRSP_CHKSM_15_TO_8_8822B                                        \
+	(BIT_MASK_EXPRSP_CHKSM_15_TO_8_8822B                                   \
+	 << BIT_SHIFT_EXPRSP_CHKSM_15_TO_8_8822B)
+#define BIT_CLEAR_EXPRSP_CHKSM_15_TO_8_8822B(x)                                \
+	((x) & (~BITS_EXPRSP_CHKSM_15_TO_8_8822B))
+#define BIT_GET_EXPRSP_CHKSM_15_TO_8_8822B(x)                                  \
+	(((x) >> BIT_SHIFT_EXPRSP_CHKSM_15_TO_8_8822B) &                       \
+	 BIT_MASK_EXPRSP_CHKSM_15_TO_8_8822B)
+#define BIT_SET_EXPRSP_CHKSM_15_TO_8_8822B(x, v)                               \
+	(BIT_CLEAR_EXPRSP_CHKSM_15_TO_8_8822B(x) |                             \
+	 BIT_EXPRSP_CHKSM_15_TO_8_8822B(v))
+
+/* 2 REG_BEAMFORMING_INFO_NSARP_V1_8822B */
+
+#define BIT_SHIFT_WMAC_ARPIP_8822B 0
+#define BIT_MASK_WMAC_ARPIP_8822B 0xffffffffL
+#define BIT_WMAC_ARPIP_8822B(x)                                                \
+	(((x) & BIT_MASK_WMAC_ARPIP_8822B) << BIT_SHIFT_WMAC_ARPIP_8822B)
+#define BITS_WMAC_ARPIP_8822B                                                  \
+	(BIT_MASK_WMAC_ARPIP_8822B << BIT_SHIFT_WMAC_ARPIP_8822B)
+#define BIT_CLEAR_WMAC_ARPIP_8822B(x) ((x) & (~BITS_WMAC_ARPIP_8822B))
+#define BIT_GET_WMAC_ARPIP_8822B(x)                                            \
+	(((x) >> BIT_SHIFT_WMAC_ARPIP_8822B) & BIT_MASK_WMAC_ARPIP_8822B)
+#define BIT_SET_WMAC_ARPIP_8822B(x, v)                                         \
+	(BIT_CLEAR_WMAC_ARPIP_8822B(x) | BIT_WMAC_ARPIP_8822B(v))
+
+/* 2 REG_BEAMFORMING_INFO_NSARP_8822B */
+
+#define BIT_SHIFT_BEAMFORMING_INFO_8822B 0
+#define BIT_MASK_BEAMFORMING_INFO_8822B 0xffffffffL
+#define BIT_BEAMFORMING_INFO_8822B(x)                                          \
+	(((x) & BIT_MASK_BEAMFORMING_INFO_8822B)                               \
+	 << BIT_SHIFT_BEAMFORMING_INFO_8822B)
+#define BITS_BEAMFORMING_INFO_8822B                                            \
+	(BIT_MASK_BEAMFORMING_INFO_8822B << BIT_SHIFT_BEAMFORMING_INFO_8822B)
+#define BIT_CLEAR_BEAMFORMING_INFO_8822B(x)                                    \
+	((x) & (~BITS_BEAMFORMING_INFO_8822B))
+#define BIT_GET_BEAMFORMING_INFO_8822B(x)                                      \
+	(((x) >> BIT_SHIFT_BEAMFORMING_INFO_8822B) &                           \
+	 BIT_MASK_BEAMFORMING_INFO_8822B)
+#define BIT_SET_BEAMFORMING_INFO_8822B(x, v)                                   \
+	(BIT_CLEAR_BEAMFORMING_INFO_8822B(x) | BIT_BEAMFORMING_INFO_8822B(v))
+
+/* 2 REG_NOT_VALID_8822B */
+
+#define BIT_SHIFT_R_WMAC_IPV6_MYIPAD_8822B 0
+#define BIT_MASK_R_WMAC_IPV6_MYIPAD_8822B 0xffffffffffffffffffffffffffffffffL
+#define BIT_R_WMAC_IPV6_MYIPAD_8822B(x)                                        \
+	(((x) & BIT_MASK_R_WMAC_IPV6_MYIPAD_8822B)                             \
+	 << BIT_SHIFT_R_WMAC_IPV6_MYIPAD_8822B)
+#define BITS_R_WMAC_IPV6_MYIPAD_8822B                                          \
+	(BIT_MASK_R_WMAC_IPV6_MYIPAD_8822B                                     \
+	 << BIT_SHIFT_R_WMAC_IPV6_MYIPAD_8822B)
+#define BIT_CLEAR_R_WMAC_IPV6_MYIPAD_8822B(x)                                  \
+	((x) & (~BITS_R_WMAC_IPV6_MYIPAD_8822B))
+#define BIT_GET_R_WMAC_IPV6_MYIPAD_8822B(x)                                    \
+	(((x) >> BIT_SHIFT_R_WMAC_IPV6_MYIPAD_8822B) &                         \
+	 BIT_MASK_R_WMAC_IPV6_MYIPAD_8822B)
+#define BIT_SET_R_WMAC_IPV6_MYIPAD_8822B(x, v)                                 \
+	(BIT_CLEAR_R_WMAC_IPV6_MYIPAD_8822B(x) |                               \
+	 BIT_R_WMAC_IPV6_MYIPAD_8822B(v))
+
+/* 2 REG_RSVD_0X740_8822B */
+
+/* 2 REG_WMAC_RTX_CTX_SUBTYPE_CFG_8822B */
+
+#define BIT_SHIFT_R_WMAC_CTX_SUBTYPE_8822B 4
+#define BIT_MASK_R_WMAC_CTX_SUBTYPE_8822B 0xf
+#define BIT_R_WMAC_CTX_SUBTYPE_8822B(x)                                        \
+	(((x) & BIT_MASK_R_WMAC_CTX_SUBTYPE_8822B)                             \
+	 << BIT_SHIFT_R_WMAC_CTX_SUBTYPE_8822B)
+#define BITS_R_WMAC_CTX_SUBTYPE_8822B                                          \
+	(BIT_MASK_R_WMAC_CTX_SUBTYPE_8822B                                     \
+	 << BIT_SHIFT_R_WMAC_CTX_SUBTYPE_8822B)
+#define BIT_CLEAR_R_WMAC_CTX_SUBTYPE_8822B(x)                                  \
+	((x) & (~BITS_R_WMAC_CTX_SUBTYPE_8822B))
+#define BIT_GET_R_WMAC_CTX_SUBTYPE_8822B(x)                                    \
+	(((x) >> BIT_SHIFT_R_WMAC_CTX_SUBTYPE_8822B) &                         \
+	 BIT_MASK_R_WMAC_CTX_SUBTYPE_8822B)
+#define BIT_SET_R_WMAC_CTX_SUBTYPE_8822B(x, v)                                 \
+	(BIT_CLEAR_R_WMAC_CTX_SUBTYPE_8822B(x) |                               \
+	 BIT_R_WMAC_CTX_SUBTYPE_8822B(v))
+
+#define BIT_SHIFT_R_WMAC_RTX_SUBTYPE_8822B 0
+#define BIT_MASK_R_WMAC_RTX_SUBTYPE_8822B 0xf
+#define BIT_R_WMAC_RTX_SUBTYPE_8822B(x)                                        \
+	(((x) & BIT_MASK_R_WMAC_RTX_SUBTYPE_8822B)                             \
+	 << BIT_SHIFT_R_WMAC_RTX_SUBTYPE_8822B)
+#define BITS_R_WMAC_RTX_SUBTYPE_8822B                                          \
+	(BIT_MASK_R_WMAC_RTX_SUBTYPE_8822B                                     \
+	 << BIT_SHIFT_R_WMAC_RTX_SUBTYPE_8822B)
+#define BIT_CLEAR_R_WMAC_RTX_SUBTYPE_8822B(x)                                  \
+	((x) & (~BITS_R_WMAC_RTX_SUBTYPE_8822B))
+#define BIT_GET_R_WMAC_RTX_SUBTYPE_8822B(x)                                    \
+	(((x) >> BIT_SHIFT_R_WMAC_RTX_SUBTYPE_8822B) &                         \
+	 BIT_MASK_R_WMAC_RTX_SUBTYPE_8822B)
+#define BIT_SET_R_WMAC_RTX_SUBTYPE_8822B(x, v)                                 \
+	(BIT_CLEAR_R_WMAC_RTX_SUBTYPE_8822B(x) |                               \
+	 BIT_R_WMAC_RTX_SUBTYPE_8822B(v))
+
+/* 2 REG_WMAC_SWAES_CFG_8822B */
+
+/* 2 REG_BT_COEX_V2_8822B */
+#define BIT_GNT_BT_POLARITY_8822B BIT(12)
+#define BIT_GNT_BT_BYPASS_PRIORITY_8822B BIT(8)
+
+#define BIT_SHIFT_TIMER_8822B 0
+#define BIT_MASK_TIMER_8822B 0xff
+#define BIT_TIMER_8822B(x)                                                     \
+	(((x) & BIT_MASK_TIMER_8822B) << BIT_SHIFT_TIMER_8822B)
+#define BITS_TIMER_8822B (BIT_MASK_TIMER_8822B << BIT_SHIFT_TIMER_8822B)
+#define BIT_CLEAR_TIMER_8822B(x) ((x) & (~BITS_TIMER_8822B))
+#define BIT_GET_TIMER_8822B(x)                                                 \
+	(((x) >> BIT_SHIFT_TIMER_8822B) & BIT_MASK_TIMER_8822B)
+#define BIT_SET_TIMER_8822B(x, v)                                              \
+	(BIT_CLEAR_TIMER_8822B(x) | BIT_TIMER_8822B(v))
+
+/* 2 REG_BT_COEX_8822B */
+#define BIT_R_GNT_BT_RFC_SW_8822B BIT(12)
+#define BIT_R_GNT_BT_RFC_SW_EN_8822B BIT(11)
+#define BIT_R_GNT_BT_BB_SW_8822B BIT(10)
+#define BIT_R_GNT_BT_BB_SW_EN_8822B BIT(9)
+#define BIT_R_BT_CNT_THREN_8822B BIT(8)
+
+#define BIT_SHIFT_R_BT_CNT_THR_8822B 0
+#define BIT_MASK_R_BT_CNT_THR_8822B 0xff
+#define BIT_R_BT_CNT_THR_8822B(x)                                              \
+	(((x) & BIT_MASK_R_BT_CNT_THR_8822B) << BIT_SHIFT_R_BT_CNT_THR_8822B)
+#define BITS_R_BT_CNT_THR_8822B                                                \
+	(BIT_MASK_R_BT_CNT_THR_8822B << BIT_SHIFT_R_BT_CNT_THR_8822B)
+#define BIT_CLEAR_R_BT_CNT_THR_8822B(x) ((x) & (~BITS_R_BT_CNT_THR_8822B))
+#define BIT_GET_R_BT_CNT_THR_8822B(x)                                          \
+	(((x) >> BIT_SHIFT_R_BT_CNT_THR_8822B) & BIT_MASK_R_BT_CNT_THR_8822B)
+#define BIT_SET_R_BT_CNT_THR_8822B(x, v)                                       \
+	(BIT_CLEAR_R_BT_CNT_THR_8822B(x) | BIT_R_BT_CNT_THR_8822B(v))
+
+/* 2 REG_WLAN_ACT_MASK_CTRL_8822B */
+#define BIT_WLRX_TER_BY_CTL_8822B BIT(43)
+#define BIT_WLRX_TER_BY_AD_8822B BIT(42)
+#define BIT_ANT_DIVERSITY_SEL_8822B BIT(41)
+#define BIT_ANTSEL_FOR_BT_CTRL_EN_8822B BIT(40)
+#define BIT_WLACT_LOW_GNTWL_EN_8822B BIT(34)
+#define BIT_WLACT_HIGH_GNTBT_EN_8822B BIT(33)
+#define BIT_NAV_UPPER_V1_8822B BIT(32)
+
+#define BIT_SHIFT_RXMYRTS_NAV_V1_8822B 8
+#define BIT_MASK_RXMYRTS_NAV_V1_8822B 0xff
+#define BIT_RXMYRTS_NAV_V1_8822B(x)                                            \
+	(((x) & BIT_MASK_RXMYRTS_NAV_V1_8822B)                                 \
+	 << BIT_SHIFT_RXMYRTS_NAV_V1_8822B)
+#define BITS_RXMYRTS_NAV_V1_8822B                                              \
+	(BIT_MASK_RXMYRTS_NAV_V1_8822B << BIT_SHIFT_RXMYRTS_NAV_V1_8822B)
+#define BIT_CLEAR_RXMYRTS_NAV_V1_8822B(x) ((x) & (~BITS_RXMYRTS_NAV_V1_8822B))
+#define BIT_GET_RXMYRTS_NAV_V1_8822B(x)                                        \
+	(((x) >> BIT_SHIFT_RXMYRTS_NAV_V1_8822B) &                             \
+	 BIT_MASK_RXMYRTS_NAV_V1_8822B)
+#define BIT_SET_RXMYRTS_NAV_V1_8822B(x, v)                                     \
+	(BIT_CLEAR_RXMYRTS_NAV_V1_8822B(x) | BIT_RXMYRTS_NAV_V1_8822B(v))
+
+#define BIT_SHIFT_RTSRST_V1_8822B 0
+#define BIT_MASK_RTSRST_V1_8822B 0xff
+#define BIT_RTSRST_V1_8822B(x)                                                 \
+	(((x) & BIT_MASK_RTSRST_V1_8822B) << BIT_SHIFT_RTSRST_V1_8822B)
+#define BITS_RTSRST_V1_8822B                                                   \
+	(BIT_MASK_RTSRST_V1_8822B << BIT_SHIFT_RTSRST_V1_8822B)
+#define BIT_CLEAR_RTSRST_V1_8822B(x) ((x) & (~BITS_RTSRST_V1_8822B))
+#define BIT_GET_RTSRST_V1_8822B(x)                                             \
+	(((x) >> BIT_SHIFT_RTSRST_V1_8822B) & BIT_MASK_RTSRST_V1_8822B)
+#define BIT_SET_RTSRST_V1_8822B(x, v)                                          \
+	(BIT_CLEAR_RTSRST_V1_8822B(x) | BIT_RTSRST_V1_8822B(v))
+
+/* 2 REG_BT_COEX_ENHANCED_INTR_CTRL_8822B */
+
+#define BIT_SHIFT_BT_STAT_DELAY_8822B 12
+#define BIT_MASK_BT_STAT_DELAY_8822B 0xf
+#define BIT_BT_STAT_DELAY_8822B(x)                                             \
+	(((x) & BIT_MASK_BT_STAT_DELAY_8822B) << BIT_SHIFT_BT_STAT_DELAY_8822B)
+#define BITS_BT_STAT_DELAY_8822B                                               \
+	(BIT_MASK_BT_STAT_DELAY_8822B << BIT_SHIFT_BT_STAT_DELAY_8822B)
+#define BIT_CLEAR_BT_STAT_DELAY_8822B(x) ((x) & (~BITS_BT_STAT_DELAY_8822B))
+#define BIT_GET_BT_STAT_DELAY_8822B(x)                                         \
+	(((x) >> BIT_SHIFT_BT_STAT_DELAY_8822B) & BIT_MASK_BT_STAT_DELAY_8822B)
+#define BIT_SET_BT_STAT_DELAY_8822B(x, v)                                      \
+	(BIT_CLEAR_BT_STAT_DELAY_8822B(x) | BIT_BT_STAT_DELAY_8822B(v))
+
+#define BIT_SHIFT_BT_TRX_INIT_DETECT_8822B 8
+#define BIT_MASK_BT_TRX_INIT_DETECT_8822B 0xf
+#define BIT_BT_TRX_INIT_DETECT_8822B(x)                                        \
+	(((x) & BIT_MASK_BT_TRX_INIT_DETECT_8822B)                             \
+	 << BIT_SHIFT_BT_TRX_INIT_DETECT_8822B)
+#define BITS_BT_TRX_INIT_DETECT_8822B                                          \
+	(BIT_MASK_BT_TRX_INIT_DETECT_8822B                                     \
+	 << BIT_SHIFT_BT_TRX_INIT_DETECT_8822B)
+#define BIT_CLEAR_BT_TRX_INIT_DETECT_8822B(x)                                  \
+	((x) & (~BITS_BT_TRX_INIT_DETECT_8822B))
+#define BIT_GET_BT_TRX_INIT_DETECT_8822B(x)                                    \
+	(((x) >> BIT_SHIFT_BT_TRX_INIT_DETECT_8822B) &                         \
+	 BIT_MASK_BT_TRX_INIT_DETECT_8822B)
+#define BIT_SET_BT_TRX_INIT_DETECT_8822B(x, v)                                 \
+	(BIT_CLEAR_BT_TRX_INIT_DETECT_8822B(x) |                               \
+	 BIT_BT_TRX_INIT_DETECT_8822B(v))
+
+#define BIT_SHIFT_BT_PRI_DETECT_TO_8822B 4
+#define BIT_MASK_BT_PRI_DETECT_TO_8822B 0xf
+#define BIT_BT_PRI_DETECT_TO_8822B(x)                                          \
+	(((x) & BIT_MASK_BT_PRI_DETECT_TO_8822B)                               \
+	 << BIT_SHIFT_BT_PRI_DETECT_TO_8822B)
+#define BITS_BT_PRI_DETECT_TO_8822B                                            \
+	(BIT_MASK_BT_PRI_DETECT_TO_8822B << BIT_SHIFT_BT_PRI_DETECT_TO_8822B)
+#define BIT_CLEAR_BT_PRI_DETECT_TO_8822B(x)                                    \
+	((x) & (~BITS_BT_PRI_DETECT_TO_8822B))
+#define BIT_GET_BT_PRI_DETECT_TO_8822B(x)                                      \
+	(((x) >> BIT_SHIFT_BT_PRI_DETECT_TO_8822B) &                           \
+	 BIT_MASK_BT_PRI_DETECT_TO_8822B)
+#define BIT_SET_BT_PRI_DETECT_TO_8822B(x, v)                                   \
+	(BIT_CLEAR_BT_PRI_DETECT_TO_8822B(x) | BIT_BT_PRI_DETECT_TO_8822B(v))
+
+#define BIT_R_GRANTALL_WLMASK_8822B BIT(3)
+#define BIT_STATIS_BT_EN_8822B BIT(2)
+#define BIT_WL_ACT_MASK_ENABLE_8822B BIT(1)
+#define BIT_ENHANCED_BT_8822B BIT(0)
+
+/* 2 REG_BT_ACT_STATISTICS_8822B */
+
+#define BIT_SHIFT_STATIS_BT_LO_RX_8822B (48 & CPU_OPT_WIDTH)
+#define BIT_MASK_STATIS_BT_LO_RX_8822B 0xffff
+#define BIT_STATIS_BT_LO_RX_8822B(x)                                           \
+	(((x) & BIT_MASK_STATIS_BT_LO_RX_8822B)                                \
+	 << BIT_SHIFT_STATIS_BT_LO_RX_8822B)
+#define BITS_STATIS_BT_LO_RX_8822B                                             \
+	(BIT_MASK_STATIS_BT_LO_RX_8822B << BIT_SHIFT_STATIS_BT_LO_RX_8822B)
+#define BIT_CLEAR_STATIS_BT_LO_RX_8822B(x) ((x) & (~BITS_STATIS_BT_LO_RX_8822B))
+#define BIT_GET_STATIS_BT_LO_RX_8822B(x)                                       \
+	(((x) >> BIT_SHIFT_STATIS_BT_LO_RX_8822B) &                            \
+	 BIT_MASK_STATIS_BT_LO_RX_8822B)
+#define BIT_SET_STATIS_BT_LO_RX_8822B(x, v)                                    \
+	(BIT_CLEAR_STATIS_BT_LO_RX_8822B(x) | BIT_STATIS_BT_LO_RX_8822B(v))
+
+#define BIT_SHIFT_STATIS_BT_LO_TX_8822B (32 & CPU_OPT_WIDTH)
+#define BIT_MASK_STATIS_BT_LO_TX_8822B 0xffff
+#define BIT_STATIS_BT_LO_TX_8822B(x)                                           \
+	(((x) & BIT_MASK_STATIS_BT_LO_TX_8822B)                                \
+	 << BIT_SHIFT_STATIS_BT_LO_TX_8822B)
+#define BITS_STATIS_BT_LO_TX_8822B                                             \
+	(BIT_MASK_STATIS_BT_LO_TX_8822B << BIT_SHIFT_STATIS_BT_LO_TX_8822B)
+#define BIT_CLEAR_STATIS_BT_LO_TX_8822B(x) ((x) & (~BITS_STATIS_BT_LO_TX_8822B))
+#define BIT_GET_STATIS_BT_LO_TX_8822B(x)                                       \
+	(((x) >> BIT_SHIFT_STATIS_BT_LO_TX_8822B) &                            \
+	 BIT_MASK_STATIS_BT_LO_TX_8822B)
+#define BIT_SET_STATIS_BT_LO_TX_8822B(x, v)                                    \
+	(BIT_CLEAR_STATIS_BT_LO_TX_8822B(x) | BIT_STATIS_BT_LO_TX_8822B(v))
+
+#define BIT_SHIFT_STATIS_BT_HI_RX_8822B 16
+#define BIT_MASK_STATIS_BT_HI_RX_8822B 0xffff
+#define BIT_STATIS_BT_HI_RX_8822B(x)                                           \
+	(((x) & BIT_MASK_STATIS_BT_HI_RX_8822B)                                \
+	 << BIT_SHIFT_STATIS_BT_HI_RX_8822B)
+#define BITS_STATIS_BT_HI_RX_8822B                                             \
+	(BIT_MASK_STATIS_BT_HI_RX_8822B << BIT_SHIFT_STATIS_BT_HI_RX_8822B)
+#define BIT_CLEAR_STATIS_BT_HI_RX_8822B(x) ((x) & (~BITS_STATIS_BT_HI_RX_8822B))
+#define BIT_GET_STATIS_BT_HI_RX_8822B(x)                                       \
+	(((x) >> BIT_SHIFT_STATIS_BT_HI_RX_8822B) &                            \
+	 BIT_MASK_STATIS_BT_HI_RX_8822B)
+#define BIT_SET_STATIS_BT_HI_RX_8822B(x, v)                                    \
+	(BIT_CLEAR_STATIS_BT_HI_RX_8822B(x) | BIT_STATIS_BT_HI_RX_8822B(v))
+
+#define BIT_SHIFT_STATIS_BT_HI_TX_8822B 0
+#define BIT_MASK_STATIS_BT_HI_TX_8822B 0xffff
+#define BIT_STATIS_BT_HI_TX_8822B(x)                                           \
+	(((x) & BIT_MASK_STATIS_BT_HI_TX_8822B)                                \
+	 << BIT_SHIFT_STATIS_BT_HI_TX_8822B)
+#define BITS_STATIS_BT_HI_TX_8822B                                             \
+	(BIT_MASK_STATIS_BT_HI_TX_8822B << BIT_SHIFT_STATIS_BT_HI_TX_8822B)
+#define BIT_CLEAR_STATIS_BT_HI_TX_8822B(x) ((x) & (~BITS_STATIS_BT_HI_TX_8822B))
+#define BIT_GET_STATIS_BT_HI_TX_8822B(x)                                       \
+	(((x) >> BIT_SHIFT_STATIS_BT_HI_TX_8822B) &                            \
+	 BIT_MASK_STATIS_BT_HI_TX_8822B)
+#define BIT_SET_STATIS_BT_HI_TX_8822B(x, v)                                    \
+	(BIT_CLEAR_STATIS_BT_HI_TX_8822B(x) | BIT_STATIS_BT_HI_TX_8822B(v))
+
+/* 2 REG_BT_STATISTICS_CONTROL_REGISTER_8822B */
+
+#define BIT_SHIFT_R_BT_CMD_RPT_8822B 16
+#define BIT_MASK_R_BT_CMD_RPT_8822B 0xffff
+#define BIT_R_BT_CMD_RPT_8822B(x)                                              \
+	(((x) & BIT_MASK_R_BT_CMD_RPT_8822B) << BIT_SHIFT_R_BT_CMD_RPT_8822B)
+#define BITS_R_BT_CMD_RPT_8822B                                                \
+	(BIT_MASK_R_BT_CMD_RPT_8822B << BIT_SHIFT_R_BT_CMD_RPT_8822B)
+#define BIT_CLEAR_R_BT_CMD_RPT_8822B(x) ((x) & (~BITS_R_BT_CMD_RPT_8822B))
+#define BIT_GET_R_BT_CMD_RPT_8822B(x)                                          \
+	(((x) >> BIT_SHIFT_R_BT_CMD_RPT_8822B) & BIT_MASK_R_BT_CMD_RPT_8822B)
+#define BIT_SET_R_BT_CMD_RPT_8822B(x, v)                                       \
+	(BIT_CLEAR_R_BT_CMD_RPT_8822B(x) | BIT_R_BT_CMD_RPT_8822B(v))
+
+#define BIT_SHIFT_R_RPT_FROM_BT_8822B 8
+#define BIT_MASK_R_RPT_FROM_BT_8822B 0xff
+#define BIT_R_RPT_FROM_BT_8822B(x)                                             \
+	(((x) & BIT_MASK_R_RPT_FROM_BT_8822B) << BIT_SHIFT_R_RPT_FROM_BT_8822B)
+#define BITS_R_RPT_FROM_BT_8822B                                               \
+	(BIT_MASK_R_RPT_FROM_BT_8822B << BIT_SHIFT_R_RPT_FROM_BT_8822B)
+#define BIT_CLEAR_R_RPT_FROM_BT_8822B(x) ((x) & (~BITS_R_RPT_FROM_BT_8822B))
+#define BIT_GET_R_RPT_FROM_BT_8822B(x)                                         \
+	(((x) >> BIT_SHIFT_R_RPT_FROM_BT_8822B) & BIT_MASK_R_RPT_FROM_BT_8822B)
+#define BIT_SET_R_RPT_FROM_BT_8822B(x, v)                                      \
+	(BIT_CLEAR_R_RPT_FROM_BT_8822B(x) | BIT_R_RPT_FROM_BT_8822B(v))
+
+#define BIT_SHIFT_BT_HID_ISR_SET_8822B 6
+#define BIT_MASK_BT_HID_ISR_SET_8822B 0x3
+#define BIT_BT_HID_ISR_SET_8822B(x)                                            \
+	(((x) & BIT_MASK_BT_HID_ISR_SET_8822B)                                 \
+	 << BIT_SHIFT_BT_HID_ISR_SET_8822B)
+#define BITS_BT_HID_ISR_SET_8822B                                              \
+	(BIT_MASK_BT_HID_ISR_SET_8822B << BIT_SHIFT_BT_HID_ISR_SET_8822B)
+#define BIT_CLEAR_BT_HID_ISR_SET_8822B(x) ((x) & (~BITS_BT_HID_ISR_SET_8822B))
+#define BIT_GET_BT_HID_ISR_SET_8822B(x)                                        \
+	(((x) >> BIT_SHIFT_BT_HID_ISR_SET_8822B) &                             \
+	 BIT_MASK_BT_HID_ISR_SET_8822B)
+#define BIT_SET_BT_HID_ISR_SET_8822B(x, v)                                     \
+	(BIT_CLEAR_BT_HID_ISR_SET_8822B(x) | BIT_BT_HID_ISR_SET_8822B(v))
+
+#define BIT_TDMA_BT_START_NOTIFY_8822B BIT(5)
+#define BIT_ENABLE_TDMA_FW_MODE_8822B BIT(4)
+#define BIT_ENABLE_PTA_TDMA_MODE_8822B BIT(3)
+#define BIT_ENABLE_COEXIST_TAB_IN_TDMA_8822B BIT(2)
+#define BIT_GPIO2_GPIO3_EXANGE_OR_NO_BT_CCA_8822B BIT(1)
+#define BIT_RTK_BT_ENABLE_8822B BIT(0)
+
+/* 2 REG_BT_STATUS_REPORT_REGISTER_8822B */
+
+#define BIT_SHIFT_BT_PROFILE_8822B 24
+#define BIT_MASK_BT_PROFILE_8822B 0xff
+#define BIT_BT_PROFILE_8822B(x)                                                \
+	(((x) & BIT_MASK_BT_PROFILE_8822B) << BIT_SHIFT_BT_PROFILE_8822B)
+#define BITS_BT_PROFILE_8822B                                                  \
+	(BIT_MASK_BT_PROFILE_8822B << BIT_SHIFT_BT_PROFILE_8822B)
+#define BIT_CLEAR_BT_PROFILE_8822B(x) ((x) & (~BITS_BT_PROFILE_8822B))
+#define BIT_GET_BT_PROFILE_8822B(x)                                            \
+	(((x) >> BIT_SHIFT_BT_PROFILE_8822B) & BIT_MASK_BT_PROFILE_8822B)
+#define BIT_SET_BT_PROFILE_8822B(x, v)                                         \
+	(BIT_CLEAR_BT_PROFILE_8822B(x) | BIT_BT_PROFILE_8822B(v))
+
+#define BIT_SHIFT_BT_POWER_8822B 16
+#define BIT_MASK_BT_POWER_8822B 0xff
+#define BIT_BT_POWER_8822B(x)                                                  \
+	(((x) & BIT_MASK_BT_POWER_8822B) << BIT_SHIFT_BT_POWER_8822B)
+#define BITS_BT_POWER_8822B                                                    \
+	(BIT_MASK_BT_POWER_8822B << BIT_SHIFT_BT_POWER_8822B)
+#define BIT_CLEAR_BT_POWER_8822B(x) ((x) & (~BITS_BT_POWER_8822B))
+#define BIT_GET_BT_POWER_8822B(x)                                              \
+	(((x) >> BIT_SHIFT_BT_POWER_8822B) & BIT_MASK_BT_POWER_8822B)
+#define BIT_SET_BT_POWER_8822B(x, v)                                           \
+	(BIT_CLEAR_BT_POWER_8822B(x) | BIT_BT_POWER_8822B(v))
+
+#define BIT_SHIFT_BT_PREDECT_STATUS_8822B 8
+#define BIT_MASK_BT_PREDECT_STATUS_8822B 0xff
+#define BIT_BT_PREDECT_STATUS_8822B(x)                                         \
+	(((x) & BIT_MASK_BT_PREDECT_STATUS_8822B)                              \
+	 << BIT_SHIFT_BT_PREDECT_STATUS_8822B)
+#define BITS_BT_PREDECT_STATUS_8822B                                           \
+	(BIT_MASK_BT_PREDECT_STATUS_8822B << BIT_SHIFT_BT_PREDECT_STATUS_8822B)
+#define BIT_CLEAR_BT_PREDECT_STATUS_8822B(x)                                   \
+	((x) & (~BITS_BT_PREDECT_STATUS_8822B))
+#define BIT_GET_BT_PREDECT_STATUS_8822B(x)                                     \
+	(((x) >> BIT_SHIFT_BT_PREDECT_STATUS_8822B) &                          \
+	 BIT_MASK_BT_PREDECT_STATUS_8822B)
+#define BIT_SET_BT_PREDECT_STATUS_8822B(x, v)                                  \
+	(BIT_CLEAR_BT_PREDECT_STATUS_8822B(x) | BIT_BT_PREDECT_STATUS_8822B(v))
+
+#define BIT_SHIFT_BT_CMD_INFO_8822B 0
+#define BIT_MASK_BT_CMD_INFO_8822B 0xff
+#define BIT_BT_CMD_INFO_8822B(x)                                               \
+	(((x) & BIT_MASK_BT_CMD_INFO_8822B) << BIT_SHIFT_BT_CMD_INFO_8822B)
+#define BITS_BT_CMD_INFO_8822B                                                 \
+	(BIT_MASK_BT_CMD_INFO_8822B << BIT_SHIFT_BT_CMD_INFO_8822B)
+#define BIT_CLEAR_BT_CMD_INFO_8822B(x) ((x) & (~BITS_BT_CMD_INFO_8822B))
+#define BIT_GET_BT_CMD_INFO_8822B(x)                                           \
+	(((x) >> BIT_SHIFT_BT_CMD_INFO_8822B) & BIT_MASK_BT_CMD_INFO_8822B)
+#define BIT_SET_BT_CMD_INFO_8822B(x, v)                                        \
+	(BIT_CLEAR_BT_CMD_INFO_8822B(x) | BIT_BT_CMD_INFO_8822B(v))
+
+/* 2 REG_BT_INTERRUPT_CONTROL_REGISTER_8822B */
+#define BIT_EN_MAC_NULL_PKT_NOTIFY_8822B BIT(31)
+#define BIT_EN_WLAN_RPT_AND_BT_QUERY_8822B BIT(30)
+#define BIT_EN_BT_STSTUS_RPT_8822B BIT(29)
+#define BIT_EN_BT_POWER_8822B BIT(28)
+#define BIT_EN_BT_CHANNEL_8822B BIT(27)
+#define BIT_EN_BT_SLOT_CHANGE_8822B BIT(26)
+#define BIT_EN_BT_PROFILE_OR_HID_8822B BIT(25)
+#define BIT_WLAN_RPT_NOTIFY_8822B BIT(24)
+
+#define BIT_SHIFT_WLAN_RPT_DATA_8822B 16
+#define BIT_MASK_WLAN_RPT_DATA_8822B 0xff
+#define BIT_WLAN_RPT_DATA_8822B(x)                                             \
+	(((x) & BIT_MASK_WLAN_RPT_DATA_8822B) << BIT_SHIFT_WLAN_RPT_DATA_8822B)
+#define BITS_WLAN_RPT_DATA_8822B                                               \
+	(BIT_MASK_WLAN_RPT_DATA_8822B << BIT_SHIFT_WLAN_RPT_DATA_8822B)
+#define BIT_CLEAR_WLAN_RPT_DATA_8822B(x) ((x) & (~BITS_WLAN_RPT_DATA_8822B))
+#define BIT_GET_WLAN_RPT_DATA_8822B(x)                                         \
+	(((x) >> BIT_SHIFT_WLAN_RPT_DATA_8822B) & BIT_MASK_WLAN_RPT_DATA_8822B)
+#define BIT_SET_WLAN_RPT_DATA_8822B(x, v)                                      \
+	(BIT_CLEAR_WLAN_RPT_DATA_8822B(x) | BIT_WLAN_RPT_DATA_8822B(v))
+
+#define BIT_SHIFT_CMD_ID_8822B 8
+#define BIT_MASK_CMD_ID_8822B 0xff
+#define BIT_CMD_ID_8822B(x)                                                    \
+	(((x) & BIT_MASK_CMD_ID_8822B) << BIT_SHIFT_CMD_ID_8822B)
+#define BITS_CMD_ID_8822B (BIT_MASK_CMD_ID_8822B << BIT_SHIFT_CMD_ID_8822B)
+#define BIT_CLEAR_CMD_ID_8822B(x) ((x) & (~BITS_CMD_ID_8822B))
+#define BIT_GET_CMD_ID_8822B(x)                                                \
+	(((x) >> BIT_SHIFT_CMD_ID_8822B) & BIT_MASK_CMD_ID_8822B)
+#define BIT_SET_CMD_ID_8822B(x, v)                                             \
+	(BIT_CLEAR_CMD_ID_8822B(x) | BIT_CMD_ID_8822B(v))
+
+#define BIT_SHIFT_BT_DATA_8822B 0
+#define BIT_MASK_BT_DATA_8822B 0xff
+#define BIT_BT_DATA_8822B(x)                                                   \
+	(((x) & BIT_MASK_BT_DATA_8822B) << BIT_SHIFT_BT_DATA_8822B)
+#define BITS_BT_DATA_8822B (BIT_MASK_BT_DATA_8822B << BIT_SHIFT_BT_DATA_8822B)
+#define BIT_CLEAR_BT_DATA_8822B(x) ((x) & (~BITS_BT_DATA_8822B))
+#define BIT_GET_BT_DATA_8822B(x)                                               \
+	(((x) >> BIT_SHIFT_BT_DATA_8822B) & BIT_MASK_BT_DATA_8822B)
+#define BIT_SET_BT_DATA_8822B(x, v)                                            \
+	(BIT_CLEAR_BT_DATA_8822B(x) | BIT_BT_DATA_8822B(v))
+
+/* 2 REG_WLAN_REPORT_TIME_OUT_CONTROL_REGISTER_8822B */
+
+#define BIT_SHIFT_WLAN_RPT_TO_8822B 0
+#define BIT_MASK_WLAN_RPT_TO_8822B 0xff
+#define BIT_WLAN_RPT_TO_8822B(x)                                               \
+	(((x) & BIT_MASK_WLAN_RPT_TO_8822B) << BIT_SHIFT_WLAN_RPT_TO_8822B)
+#define BITS_WLAN_RPT_TO_8822B                                                 \
+	(BIT_MASK_WLAN_RPT_TO_8822B << BIT_SHIFT_WLAN_RPT_TO_8822B)
+#define BIT_CLEAR_WLAN_RPT_TO_8822B(x) ((x) & (~BITS_WLAN_RPT_TO_8822B))
+#define BIT_GET_WLAN_RPT_TO_8822B(x)                                           \
+	(((x) >> BIT_SHIFT_WLAN_RPT_TO_8822B) & BIT_MASK_WLAN_RPT_TO_8822B)
+#define BIT_SET_WLAN_RPT_TO_8822B(x, v)                                        \
+	(BIT_CLEAR_WLAN_RPT_TO_8822B(x) | BIT_WLAN_RPT_TO_8822B(v))
+
+/* 2 REG_BT_ISOLATION_TABLE_REGISTER_REGISTER_8822B */
+
+#define BIT_SHIFT_ISOLATION_CHK_8822B 1
+#define BIT_MASK_ISOLATION_CHK_8822B 0x7fffffffffffffffffffL
+#define BIT_ISOLATION_CHK_8822B(x)                                             \
+	(((x) & BIT_MASK_ISOLATION_CHK_8822B) << BIT_SHIFT_ISOLATION_CHK_8822B)
+#define BITS_ISOLATION_CHK_8822B                                               \
+	(BIT_MASK_ISOLATION_CHK_8822B << BIT_SHIFT_ISOLATION_CHK_8822B)
+#define BIT_CLEAR_ISOLATION_CHK_8822B(x) ((x) & (~BITS_ISOLATION_CHK_8822B))
+#define BIT_GET_ISOLATION_CHK_8822B(x)                                         \
+	(((x) >> BIT_SHIFT_ISOLATION_CHK_8822B) & BIT_MASK_ISOLATION_CHK_8822B)
+#define BIT_SET_ISOLATION_CHK_8822B(x, v)                                      \
+	(BIT_CLEAR_ISOLATION_CHK_8822B(x) | BIT_ISOLATION_CHK_8822B(v))
+
+#define BIT_ISOLATION_EN_8822B BIT(0)
+
+/* 2 REG_BT_INTERRUPT_STATUS_REGISTER_8822B */
+#define BIT_BT_HID_ISR_8822B BIT(7)
+#define BIT_BT_QUERY_ISR_8822B BIT(6)
+#define BIT_MAC_NULL_PKT_NOTIFY_ISR_8822B BIT(5)
+#define BIT_WLAN_RPT_ISR_8822B BIT(4)
+#define BIT_BT_POWER_ISR_8822B BIT(3)
+#define BIT_BT_CHANNEL_ISR_8822B BIT(2)
+#define BIT_BT_SLOT_CHANGE_ISR_8822B BIT(1)
+#define BIT_BT_PROFILE_ISR_8822B BIT(0)
+
+/* 2 REG_BT_TDMA_TIME_REGISTER_8822B */
+
+#define BIT_SHIFT_BT_TIME_8822B 6
+#define BIT_MASK_BT_TIME_8822B 0x3ffffff
+#define BIT_BT_TIME_8822B(x)                                                   \
+	(((x) & BIT_MASK_BT_TIME_8822B) << BIT_SHIFT_BT_TIME_8822B)
+#define BITS_BT_TIME_8822B (BIT_MASK_BT_TIME_8822B << BIT_SHIFT_BT_TIME_8822B)
+#define BIT_CLEAR_BT_TIME_8822B(x) ((x) & (~BITS_BT_TIME_8822B))
+#define BIT_GET_BT_TIME_8822B(x)                                               \
+	(((x) >> BIT_SHIFT_BT_TIME_8822B) & BIT_MASK_BT_TIME_8822B)
+#define BIT_SET_BT_TIME_8822B(x, v)                                            \
+	(BIT_CLEAR_BT_TIME_8822B(x) | BIT_BT_TIME_8822B(v))
+
+#define BIT_SHIFT_BT_RPT_SAMPLE_RATE_8822B 0
+#define BIT_MASK_BT_RPT_SAMPLE_RATE_8822B 0x3f
+#define BIT_BT_RPT_SAMPLE_RATE_8822B(x)                                        \
+	(((x) & BIT_MASK_BT_RPT_SAMPLE_RATE_8822B)                             \
+	 << BIT_SHIFT_BT_RPT_SAMPLE_RATE_8822B)
+#define BITS_BT_RPT_SAMPLE_RATE_8822B                                          \
+	(BIT_MASK_BT_RPT_SAMPLE_RATE_8822B                                     \
+	 << BIT_SHIFT_BT_RPT_SAMPLE_RATE_8822B)
+#define BIT_CLEAR_BT_RPT_SAMPLE_RATE_8822B(x)                                  \
+	((x) & (~BITS_BT_RPT_SAMPLE_RATE_8822B))
+#define BIT_GET_BT_RPT_SAMPLE_RATE_8822B(x)                                    \
+	(((x) >> BIT_SHIFT_BT_RPT_SAMPLE_RATE_8822B) &                         \
+	 BIT_MASK_BT_RPT_SAMPLE_RATE_8822B)
+#define BIT_SET_BT_RPT_SAMPLE_RATE_8822B(x, v)                                 \
+	(BIT_CLEAR_BT_RPT_SAMPLE_RATE_8822B(x) |                               \
+	 BIT_BT_RPT_SAMPLE_RATE_8822B(v))
+
+/* 2 REG_BT_ACT_REGISTER_8822B */
+
+#define BIT_SHIFT_BT_EISR_EN_8822B 16
+#define BIT_MASK_BT_EISR_EN_8822B 0xff
+#define BIT_BT_EISR_EN_8822B(x)                                                \
+	(((x) & BIT_MASK_BT_EISR_EN_8822B) << BIT_SHIFT_BT_EISR_EN_8822B)
+#define BITS_BT_EISR_EN_8822B                                                  \
+	(BIT_MASK_BT_EISR_EN_8822B << BIT_SHIFT_BT_EISR_EN_8822B)
+#define BIT_CLEAR_BT_EISR_EN_8822B(x) ((x) & (~BITS_BT_EISR_EN_8822B))
+#define BIT_GET_BT_EISR_EN_8822B(x)                                            \
+	(((x) >> BIT_SHIFT_BT_EISR_EN_8822B) & BIT_MASK_BT_EISR_EN_8822B)
+#define BIT_SET_BT_EISR_EN_8822B(x, v)                                         \
+	(BIT_CLEAR_BT_EISR_EN_8822B(x) | BIT_BT_EISR_EN_8822B(v))
+
+#define BIT_BT_ACT_FALLING_ISR_8822B BIT(10)
+#define BIT_BT_ACT_RISING_ISR_8822B BIT(9)
+#define BIT_TDMA_TO_ISR_8822B BIT(8)
+
+#define BIT_SHIFT_BT_CH_8822B 0
+#define BIT_MASK_BT_CH_8822B 0xff
+#define BIT_BT_CH_8822B(x)                                                     \
+	(((x) & BIT_MASK_BT_CH_8822B) << BIT_SHIFT_BT_CH_8822B)
+#define BITS_BT_CH_8822B (BIT_MASK_BT_CH_8822B << BIT_SHIFT_BT_CH_8822B)
+#define BIT_CLEAR_BT_CH_8822B(x) ((x) & (~BITS_BT_CH_8822B))
+#define BIT_GET_BT_CH_8822B(x)                                                 \
+	(((x) >> BIT_SHIFT_BT_CH_8822B) & BIT_MASK_BT_CH_8822B)
+#define BIT_SET_BT_CH_8822B(x, v)                                              \
+	(BIT_CLEAR_BT_CH_8822B(x) | BIT_BT_CH_8822B(v))
+
+/* 2 REG_OBFF_CTRL_BASIC_8822B */
+#define BIT_OBFF_EN_V1_8822B BIT(31)
+
+#define BIT_SHIFT_OBFF_STATE_V1_8822B 28
+#define BIT_MASK_OBFF_STATE_V1_8822B 0x3
+#define BIT_OBFF_STATE_V1_8822B(x)                                             \
+	(((x) & BIT_MASK_OBFF_STATE_V1_8822B) << BIT_SHIFT_OBFF_STATE_V1_8822B)
+#define BITS_OBFF_STATE_V1_8822B                                               \
+	(BIT_MASK_OBFF_STATE_V1_8822B << BIT_SHIFT_OBFF_STATE_V1_8822B)
+#define BIT_CLEAR_OBFF_STATE_V1_8822B(x) ((x) & (~BITS_OBFF_STATE_V1_8822B))
+#define BIT_GET_OBFF_STATE_V1_8822B(x)                                         \
+	(((x) >> BIT_SHIFT_OBFF_STATE_V1_8822B) & BIT_MASK_OBFF_STATE_V1_8822B)
+#define BIT_SET_OBFF_STATE_V1_8822B(x, v)                                      \
+	(BIT_CLEAR_OBFF_STATE_V1_8822B(x) | BIT_OBFF_STATE_V1_8822B(v))
+
+#define BIT_OBFF_ACT_RXDMA_EN_8822B BIT(27)
+#define BIT_OBFF_BLOCK_INT_EN_8822B BIT(26)
+#define BIT_OBFF_AUTOACT_EN_8822B BIT(25)
+#define BIT_OBFF_AUTOIDLE_EN_8822B BIT(24)
+
+#define BIT_SHIFT_WAKE_MAX_PLS_8822B 20
+#define BIT_MASK_WAKE_MAX_PLS_8822B 0x7
+#define BIT_WAKE_MAX_PLS_8822B(x)                                              \
+	(((x) & BIT_MASK_WAKE_MAX_PLS_8822B) << BIT_SHIFT_WAKE_MAX_PLS_8822B)
+#define BITS_WAKE_MAX_PLS_8822B                                                \
+	(BIT_MASK_WAKE_MAX_PLS_8822B << BIT_SHIFT_WAKE_MAX_PLS_8822B)
+#define BIT_CLEAR_WAKE_MAX_PLS_8822B(x) ((x) & (~BITS_WAKE_MAX_PLS_8822B))
+#define BIT_GET_WAKE_MAX_PLS_8822B(x)                                          \
+	(((x) >> BIT_SHIFT_WAKE_MAX_PLS_8822B) & BIT_MASK_WAKE_MAX_PLS_8822B)
+#define BIT_SET_WAKE_MAX_PLS_8822B(x, v)                                       \
+	(BIT_CLEAR_WAKE_MAX_PLS_8822B(x) | BIT_WAKE_MAX_PLS_8822B(v))
+
+#define BIT_SHIFT_WAKE_MIN_PLS_8822B 16
+#define BIT_MASK_WAKE_MIN_PLS_8822B 0x7
+#define BIT_WAKE_MIN_PLS_8822B(x)                                              \
+	(((x) & BIT_MASK_WAKE_MIN_PLS_8822B) << BIT_SHIFT_WAKE_MIN_PLS_8822B)
+#define BITS_WAKE_MIN_PLS_8822B                                                \
+	(BIT_MASK_WAKE_MIN_PLS_8822B << BIT_SHIFT_WAKE_MIN_PLS_8822B)
+#define BIT_CLEAR_WAKE_MIN_PLS_8822B(x) ((x) & (~BITS_WAKE_MIN_PLS_8822B))
+#define BIT_GET_WAKE_MIN_PLS_8822B(x)                                          \
+	(((x) >> BIT_SHIFT_WAKE_MIN_PLS_8822B) & BIT_MASK_WAKE_MIN_PLS_8822B)
+#define BIT_SET_WAKE_MIN_PLS_8822B(x, v)                                       \
+	(BIT_CLEAR_WAKE_MIN_PLS_8822B(x) | BIT_WAKE_MIN_PLS_8822B(v))
+
+#define BIT_SHIFT_WAKE_MAX_F2F_8822B 12
+#define BIT_MASK_WAKE_MAX_F2F_8822B 0x7
+#define BIT_WAKE_MAX_F2F_8822B(x)                                              \
+	(((x) & BIT_MASK_WAKE_MAX_F2F_8822B) << BIT_SHIFT_WAKE_MAX_F2F_8822B)
+#define BITS_WAKE_MAX_F2F_8822B                                                \
+	(BIT_MASK_WAKE_MAX_F2F_8822B << BIT_SHIFT_WAKE_MAX_F2F_8822B)
+#define BIT_CLEAR_WAKE_MAX_F2F_8822B(x) ((x) & (~BITS_WAKE_MAX_F2F_8822B))
+#define BIT_GET_WAKE_MAX_F2F_8822B(x)                                          \
+	(((x) >> BIT_SHIFT_WAKE_MAX_F2F_8822B) & BIT_MASK_WAKE_MAX_F2F_8822B)
+#define BIT_SET_WAKE_MAX_F2F_8822B(x, v)                                       \
+	(BIT_CLEAR_WAKE_MAX_F2F_8822B(x) | BIT_WAKE_MAX_F2F_8822B(v))
+
+#define BIT_SHIFT_WAKE_MIN_F2F_8822B 8
+#define BIT_MASK_WAKE_MIN_F2F_8822B 0x7
+#define BIT_WAKE_MIN_F2F_8822B(x)                                              \
+	(((x) & BIT_MASK_WAKE_MIN_F2F_8822B) << BIT_SHIFT_WAKE_MIN_F2F_8822B)
+#define BITS_WAKE_MIN_F2F_8822B                                                \
+	(BIT_MASK_WAKE_MIN_F2F_8822B << BIT_SHIFT_WAKE_MIN_F2F_8822B)
+#define BIT_CLEAR_WAKE_MIN_F2F_8822B(x) ((x) & (~BITS_WAKE_MIN_F2F_8822B))
+#define BIT_GET_WAKE_MIN_F2F_8822B(x)                                          \
+	(((x) >> BIT_SHIFT_WAKE_MIN_F2F_8822B) & BIT_MASK_WAKE_MIN_F2F_8822B)
+#define BIT_SET_WAKE_MIN_F2F_8822B(x, v)                                       \
+	(BIT_CLEAR_WAKE_MIN_F2F_8822B(x) | BIT_WAKE_MIN_F2F_8822B(v))
+
+#define BIT_APP_CPU_ACT_V1_8822B BIT(3)
+#define BIT_APP_OBFF_V1_8822B BIT(2)
+#define BIT_APP_IDLE_V1_8822B BIT(1)
+#define BIT_APP_INIT_V1_8822B BIT(0)
+
+/* 2 REG_OBFF_CTRL2_TIMER_8822B */
+
+#define BIT_SHIFT_RX_HIGH_TIMER_IDX_8822B 24
+#define BIT_MASK_RX_HIGH_TIMER_IDX_8822B 0x7
+#define BIT_RX_HIGH_TIMER_IDX_8822B(x)                                         \
+	(((x) & BIT_MASK_RX_HIGH_TIMER_IDX_8822B)                              \
+	 << BIT_SHIFT_RX_HIGH_TIMER_IDX_8822B)
+#define BITS_RX_HIGH_TIMER_IDX_8822B                                           \
+	(BIT_MASK_RX_HIGH_TIMER_IDX_8822B << BIT_SHIFT_RX_HIGH_TIMER_IDX_8822B)
+#define BIT_CLEAR_RX_HIGH_TIMER_IDX_8822B(x)                                   \
+	((x) & (~BITS_RX_HIGH_TIMER_IDX_8822B))
+#define BIT_GET_RX_HIGH_TIMER_IDX_8822B(x)                                     \
+	(((x) >> BIT_SHIFT_RX_HIGH_TIMER_IDX_8822B) &                          \
+	 BIT_MASK_RX_HIGH_TIMER_IDX_8822B)
+#define BIT_SET_RX_HIGH_TIMER_IDX_8822B(x, v)                                  \
+	(BIT_CLEAR_RX_HIGH_TIMER_IDX_8822B(x) | BIT_RX_HIGH_TIMER_IDX_8822B(v))
+
+#define BIT_SHIFT_RX_MED_TIMER_IDX_8822B 16
+#define BIT_MASK_RX_MED_TIMER_IDX_8822B 0x7
+#define BIT_RX_MED_TIMER_IDX_8822B(x)                                          \
+	(((x) & BIT_MASK_RX_MED_TIMER_IDX_8822B)                               \
+	 << BIT_SHIFT_RX_MED_TIMER_IDX_8822B)
+#define BITS_RX_MED_TIMER_IDX_8822B                                            \
+	(BIT_MASK_RX_MED_TIMER_IDX_8822B << BIT_SHIFT_RX_MED_TIMER_IDX_8822B)
+#define BIT_CLEAR_RX_MED_TIMER_IDX_8822B(x)                                    \
+	((x) & (~BITS_RX_MED_TIMER_IDX_8822B))
+#define BIT_GET_RX_MED_TIMER_IDX_8822B(x)                                      \
+	(((x) >> BIT_SHIFT_RX_MED_TIMER_IDX_8822B) &                           \
+	 BIT_MASK_RX_MED_TIMER_IDX_8822B)
+#define BIT_SET_RX_MED_TIMER_IDX_8822B(x, v)                                   \
+	(BIT_CLEAR_RX_MED_TIMER_IDX_8822B(x) | BIT_RX_MED_TIMER_IDX_8822B(v))
+
+#define BIT_SHIFT_RX_LOW_TIMER_IDX_8822B 8
+#define BIT_MASK_RX_LOW_TIMER_IDX_8822B 0x7
+#define BIT_RX_LOW_TIMER_IDX_8822B(x)                                          \
+	(((x) & BIT_MASK_RX_LOW_TIMER_IDX_8822B)                               \
+	 << BIT_SHIFT_RX_LOW_TIMER_IDX_8822B)
+#define BITS_RX_LOW_TIMER_IDX_8822B                                            \
+	(BIT_MASK_RX_LOW_TIMER_IDX_8822B << BIT_SHIFT_RX_LOW_TIMER_IDX_8822B)
+#define BIT_CLEAR_RX_LOW_TIMER_IDX_8822B(x)                                    \
+	((x) & (~BITS_RX_LOW_TIMER_IDX_8822B))
+#define BIT_GET_RX_LOW_TIMER_IDX_8822B(x)                                      \
+	(((x) >> BIT_SHIFT_RX_LOW_TIMER_IDX_8822B) &                           \
+	 BIT_MASK_RX_LOW_TIMER_IDX_8822B)
+#define BIT_SET_RX_LOW_TIMER_IDX_8822B(x, v)                                   \
+	(BIT_CLEAR_RX_LOW_TIMER_IDX_8822B(x) | BIT_RX_LOW_TIMER_IDX_8822B(v))
+
+#define BIT_SHIFT_OBFF_INT_TIMER_IDX_8822B 0
+#define BIT_MASK_OBFF_INT_TIMER_IDX_8822B 0x7
+#define BIT_OBFF_INT_TIMER_IDX_8822B(x)                                        \
+	(((x) & BIT_MASK_OBFF_INT_TIMER_IDX_8822B)                             \
+	 << BIT_SHIFT_OBFF_INT_TIMER_IDX_8822B)
+#define BITS_OBFF_INT_TIMER_IDX_8822B                                          \
+	(BIT_MASK_OBFF_INT_TIMER_IDX_8822B                                     \
+	 << BIT_SHIFT_OBFF_INT_TIMER_IDX_8822B)
+#define BIT_CLEAR_OBFF_INT_TIMER_IDX_8822B(x)                                  \
+	((x) & (~BITS_OBFF_INT_TIMER_IDX_8822B))
+#define BIT_GET_OBFF_INT_TIMER_IDX_8822B(x)                                    \
+	(((x) >> BIT_SHIFT_OBFF_INT_TIMER_IDX_8822B) &                         \
+	 BIT_MASK_OBFF_INT_TIMER_IDX_8822B)
+#define BIT_SET_OBFF_INT_TIMER_IDX_8822B(x, v)                                 \
+	(BIT_CLEAR_OBFF_INT_TIMER_IDX_8822B(x) |                               \
+	 BIT_OBFF_INT_TIMER_IDX_8822B(v))
+
+/* 2 REG_LTR_CTRL_BASIC_8822B */
+#define BIT_LTR_EN_V1_8822B BIT(31)
+#define BIT_LTR_HW_EN_V1_8822B BIT(30)
+#define BIT_LRT_ACT_CTS_EN_8822B BIT(29)
+#define BIT_LTR_ACT_RXPKT_EN_8822B BIT(28)
+#define BIT_LTR_ACT_RXDMA_EN_8822B BIT(27)
+#define BIT_LTR_IDLE_NO_SNOOP_8822B BIT(26)
+#define BIT_SPDUP_MGTPKT_8822B BIT(25)
+#define BIT_RX_AGG_EN_8822B BIT(24)
+#define BIT_APP_LTR_ACT_8822B BIT(23)
+#define BIT_APP_LTR_IDLE_8822B BIT(22)
+
+#define BIT_SHIFT_HIGH_RATE_TRIG_SEL_8822B 20
+#define BIT_MASK_HIGH_RATE_TRIG_SEL_8822B 0x3
+#define BIT_HIGH_RATE_TRIG_SEL_8822B(x)                                        \
+	(((x) & BIT_MASK_HIGH_RATE_TRIG_SEL_8822B)                             \
+	 << BIT_SHIFT_HIGH_RATE_TRIG_SEL_8822B)
+#define BITS_HIGH_RATE_TRIG_SEL_8822B                                          \
+	(BIT_MASK_HIGH_RATE_TRIG_SEL_8822B                                     \
+	 << BIT_SHIFT_HIGH_RATE_TRIG_SEL_8822B)
+#define BIT_CLEAR_HIGH_RATE_TRIG_SEL_8822B(x)                                  \
+	((x) & (~BITS_HIGH_RATE_TRIG_SEL_8822B))
+#define BIT_GET_HIGH_RATE_TRIG_SEL_8822B(x)                                    \
+	(((x) >> BIT_SHIFT_HIGH_RATE_TRIG_SEL_8822B) &                         \
+	 BIT_MASK_HIGH_RATE_TRIG_SEL_8822B)
+#define BIT_SET_HIGH_RATE_TRIG_SEL_8822B(x, v)                                 \
+	(BIT_CLEAR_HIGH_RATE_TRIG_SEL_8822B(x) |                               \
+	 BIT_HIGH_RATE_TRIG_SEL_8822B(v))
+
+#define BIT_SHIFT_MED_RATE_TRIG_SEL_8822B 18
+#define BIT_MASK_MED_RATE_TRIG_SEL_8822B 0x3
+#define BIT_MED_RATE_TRIG_SEL_8822B(x)                                         \
+	(((x) & BIT_MASK_MED_RATE_TRIG_SEL_8822B)                              \
+	 << BIT_SHIFT_MED_RATE_TRIG_SEL_8822B)
+#define BITS_MED_RATE_TRIG_SEL_8822B                                           \
+	(BIT_MASK_MED_RATE_TRIG_SEL_8822B << BIT_SHIFT_MED_RATE_TRIG_SEL_8822B)
+#define BIT_CLEAR_MED_RATE_TRIG_SEL_8822B(x)                                   \
+	((x) & (~BITS_MED_RATE_TRIG_SEL_8822B))
+#define BIT_GET_MED_RATE_TRIG_SEL_8822B(x)                                     \
+	(((x) >> BIT_SHIFT_MED_RATE_TRIG_SEL_8822B) &                          \
+	 BIT_MASK_MED_RATE_TRIG_SEL_8822B)
+#define BIT_SET_MED_RATE_TRIG_SEL_8822B(x, v)                                  \
+	(BIT_CLEAR_MED_RATE_TRIG_SEL_8822B(x) | BIT_MED_RATE_TRIG_SEL_8822B(v))
+
+#define BIT_SHIFT_LOW_RATE_TRIG_SEL_8822B 16
+#define BIT_MASK_LOW_RATE_TRIG_SEL_8822B 0x3
+#define BIT_LOW_RATE_TRIG_SEL_8822B(x)                                         \
+	(((x) & BIT_MASK_LOW_RATE_TRIG_SEL_8822B)                              \
+	 << BIT_SHIFT_LOW_RATE_TRIG_SEL_8822B)
+#define BITS_LOW_RATE_TRIG_SEL_8822B                                           \
+	(BIT_MASK_LOW_RATE_TRIG_SEL_8822B << BIT_SHIFT_LOW_RATE_TRIG_SEL_8822B)
+#define BIT_CLEAR_LOW_RATE_TRIG_SEL_8822B(x)                                   \
+	((x) & (~BITS_LOW_RATE_TRIG_SEL_8822B))
+#define BIT_GET_LOW_RATE_TRIG_SEL_8822B(x)                                     \
+	(((x) >> BIT_SHIFT_LOW_RATE_TRIG_SEL_8822B) &                          \
+	 BIT_MASK_LOW_RATE_TRIG_SEL_8822B)
+#define BIT_SET_LOW_RATE_TRIG_SEL_8822B(x, v)                                  \
+	(BIT_CLEAR_LOW_RATE_TRIG_SEL_8822B(x) | BIT_LOW_RATE_TRIG_SEL_8822B(v))
+
+#define BIT_SHIFT_HIGH_RATE_BD_IDX_8822B 8
+#define BIT_MASK_HIGH_RATE_BD_IDX_8822B 0x7f
+#define BIT_HIGH_RATE_BD_IDX_8822B(x)                                          \
+	(((x) & BIT_MASK_HIGH_RATE_BD_IDX_8822B)                               \
+	 << BIT_SHIFT_HIGH_RATE_BD_IDX_8822B)
+#define BITS_HIGH_RATE_BD_IDX_8822B                                            \
+	(BIT_MASK_HIGH_RATE_BD_IDX_8822B << BIT_SHIFT_HIGH_RATE_BD_IDX_8822B)
+#define BIT_CLEAR_HIGH_RATE_BD_IDX_8822B(x)                                    \
+	((x) & (~BITS_HIGH_RATE_BD_IDX_8822B))
+#define BIT_GET_HIGH_RATE_BD_IDX_8822B(x)                                      \
+	(((x) >> BIT_SHIFT_HIGH_RATE_BD_IDX_8822B) &                           \
+	 BIT_MASK_HIGH_RATE_BD_IDX_8822B)
+#define BIT_SET_HIGH_RATE_BD_IDX_8822B(x, v)                                   \
+	(BIT_CLEAR_HIGH_RATE_BD_IDX_8822B(x) | BIT_HIGH_RATE_BD_IDX_8822B(v))
+
+#define BIT_SHIFT_LOW_RATE_BD_IDX_8822B 0
+#define BIT_MASK_LOW_RATE_BD_IDX_8822B 0x7f
+#define BIT_LOW_RATE_BD_IDX_8822B(x)                                           \
+	(((x) & BIT_MASK_LOW_RATE_BD_IDX_8822B)                                \
+	 << BIT_SHIFT_LOW_RATE_BD_IDX_8822B)
+#define BITS_LOW_RATE_BD_IDX_8822B                                             \
+	(BIT_MASK_LOW_RATE_BD_IDX_8822B << BIT_SHIFT_LOW_RATE_BD_IDX_8822B)
+#define BIT_CLEAR_LOW_RATE_BD_IDX_8822B(x) ((x) & (~BITS_LOW_RATE_BD_IDX_8822B))
+#define BIT_GET_LOW_RATE_BD_IDX_8822B(x)                                       \
+	(((x) >> BIT_SHIFT_LOW_RATE_BD_IDX_8822B) &                            \
+	 BIT_MASK_LOW_RATE_BD_IDX_8822B)
+#define BIT_SET_LOW_RATE_BD_IDX_8822B(x, v)                                    \
+	(BIT_CLEAR_LOW_RATE_BD_IDX_8822B(x) | BIT_LOW_RATE_BD_IDX_8822B(v))
+
+/* 2 REG_LTR_CTRL2_TIMER_THRESHOLD_8822B */
+
+#define BIT_SHIFT_RX_EMPTY_TIMER_IDX_8822B 24
+#define BIT_MASK_RX_EMPTY_TIMER_IDX_8822B 0x7
+#define BIT_RX_EMPTY_TIMER_IDX_8822B(x)                                        \
+	(((x) & BIT_MASK_RX_EMPTY_TIMER_IDX_8822B)                             \
+	 << BIT_SHIFT_RX_EMPTY_TIMER_IDX_8822B)
+#define BITS_RX_EMPTY_TIMER_IDX_8822B                                          \
+	(BIT_MASK_RX_EMPTY_TIMER_IDX_8822B                                     \
+	 << BIT_SHIFT_RX_EMPTY_TIMER_IDX_8822B)
+#define BIT_CLEAR_RX_EMPTY_TIMER_IDX_8822B(x)                                  \
+	((x) & (~BITS_RX_EMPTY_TIMER_IDX_8822B))
+#define BIT_GET_RX_EMPTY_TIMER_IDX_8822B(x)                                    \
+	(((x) >> BIT_SHIFT_RX_EMPTY_TIMER_IDX_8822B) &                         \
+	 BIT_MASK_RX_EMPTY_TIMER_IDX_8822B)
+#define BIT_SET_RX_EMPTY_TIMER_IDX_8822B(x, v)                                 \
+	(BIT_CLEAR_RX_EMPTY_TIMER_IDX_8822B(x) |                               \
+	 BIT_RX_EMPTY_TIMER_IDX_8822B(v))
+
+#define BIT_SHIFT_RX_AFULL_TH_IDX_8822B 20
+#define BIT_MASK_RX_AFULL_TH_IDX_8822B 0x7
+#define BIT_RX_AFULL_TH_IDX_8822B(x)                                           \
+	(((x) & BIT_MASK_RX_AFULL_TH_IDX_8822B)                                \
+	 << BIT_SHIFT_RX_AFULL_TH_IDX_8822B)
+#define BITS_RX_AFULL_TH_IDX_8822B                                             \
+	(BIT_MASK_RX_AFULL_TH_IDX_8822B << BIT_SHIFT_RX_AFULL_TH_IDX_8822B)
+#define BIT_CLEAR_RX_AFULL_TH_IDX_8822B(x) ((x) & (~BITS_RX_AFULL_TH_IDX_8822B))
+#define BIT_GET_RX_AFULL_TH_IDX_8822B(x)                                       \
+	(((x) >> BIT_SHIFT_RX_AFULL_TH_IDX_8822B) &                            \
+	 BIT_MASK_RX_AFULL_TH_IDX_8822B)
+#define BIT_SET_RX_AFULL_TH_IDX_8822B(x, v)                                    \
+	(BIT_CLEAR_RX_AFULL_TH_IDX_8822B(x) | BIT_RX_AFULL_TH_IDX_8822B(v))
+
+#define BIT_SHIFT_RX_HIGH_TH_IDX_8822B 16
+#define BIT_MASK_RX_HIGH_TH_IDX_8822B 0x7
+#define BIT_RX_HIGH_TH_IDX_8822B(x)                                            \
+	(((x) & BIT_MASK_RX_HIGH_TH_IDX_8822B)                                 \
+	 << BIT_SHIFT_RX_HIGH_TH_IDX_8822B)
+#define BITS_RX_HIGH_TH_IDX_8822B                                              \
+	(BIT_MASK_RX_HIGH_TH_IDX_8822B << BIT_SHIFT_RX_HIGH_TH_IDX_8822B)
+#define BIT_CLEAR_RX_HIGH_TH_IDX_8822B(x) ((x) & (~BITS_RX_HIGH_TH_IDX_8822B))
+#define BIT_GET_RX_HIGH_TH_IDX_8822B(x)                                        \
+	(((x) >> BIT_SHIFT_RX_HIGH_TH_IDX_8822B) &                             \
+	 BIT_MASK_RX_HIGH_TH_IDX_8822B)
+#define BIT_SET_RX_HIGH_TH_IDX_8822B(x, v)                                     \
+	(BIT_CLEAR_RX_HIGH_TH_IDX_8822B(x) | BIT_RX_HIGH_TH_IDX_8822B(v))
+
+#define BIT_SHIFT_RX_MED_TH_IDX_8822B 12
+#define BIT_MASK_RX_MED_TH_IDX_8822B 0x7
+#define BIT_RX_MED_TH_IDX_8822B(x)                                             \
+	(((x) & BIT_MASK_RX_MED_TH_IDX_8822B) << BIT_SHIFT_RX_MED_TH_IDX_8822B)
+#define BITS_RX_MED_TH_IDX_8822B                                               \
+	(BIT_MASK_RX_MED_TH_IDX_8822B << BIT_SHIFT_RX_MED_TH_IDX_8822B)
+#define BIT_CLEAR_RX_MED_TH_IDX_8822B(x) ((x) & (~BITS_RX_MED_TH_IDX_8822B))
+#define BIT_GET_RX_MED_TH_IDX_8822B(x)                                         \
+	(((x) >> BIT_SHIFT_RX_MED_TH_IDX_8822B) & BIT_MASK_RX_MED_TH_IDX_8822B)
+#define BIT_SET_RX_MED_TH_IDX_8822B(x, v)                                      \
+	(BIT_CLEAR_RX_MED_TH_IDX_8822B(x) | BIT_RX_MED_TH_IDX_8822B(v))
+
+#define BIT_SHIFT_RX_LOW_TH_IDX_8822B 8
+#define BIT_MASK_RX_LOW_TH_IDX_8822B 0x7
+#define BIT_RX_LOW_TH_IDX_8822B(x)                                             \
+	(((x) & BIT_MASK_RX_LOW_TH_IDX_8822B) << BIT_SHIFT_RX_LOW_TH_IDX_8822B)
+#define BITS_RX_LOW_TH_IDX_8822B                                               \
+	(BIT_MASK_RX_LOW_TH_IDX_8822B << BIT_SHIFT_RX_LOW_TH_IDX_8822B)
+#define BIT_CLEAR_RX_LOW_TH_IDX_8822B(x) ((x) & (~BITS_RX_LOW_TH_IDX_8822B))
+#define BIT_GET_RX_LOW_TH_IDX_8822B(x)                                         \
+	(((x) >> BIT_SHIFT_RX_LOW_TH_IDX_8822B) & BIT_MASK_RX_LOW_TH_IDX_8822B)
+#define BIT_SET_RX_LOW_TH_IDX_8822B(x, v)                                      \
+	(BIT_CLEAR_RX_LOW_TH_IDX_8822B(x) | BIT_RX_LOW_TH_IDX_8822B(v))
+
+#define BIT_SHIFT_LTR_SPACE_IDX_8822B 4
+#define BIT_MASK_LTR_SPACE_IDX_8822B 0x3
+#define BIT_LTR_SPACE_IDX_8822B(x)                                             \
+	(((x) & BIT_MASK_LTR_SPACE_IDX_8822B) << BIT_SHIFT_LTR_SPACE_IDX_8822B)
+#define BITS_LTR_SPACE_IDX_8822B                                               \
+	(BIT_MASK_LTR_SPACE_IDX_8822B << BIT_SHIFT_LTR_SPACE_IDX_8822B)
+#define BIT_CLEAR_LTR_SPACE_IDX_8822B(x) ((x) & (~BITS_LTR_SPACE_IDX_8822B))
+#define BIT_GET_LTR_SPACE_IDX_8822B(x)                                         \
+	(((x) >> BIT_SHIFT_LTR_SPACE_IDX_8822B) & BIT_MASK_LTR_SPACE_IDX_8822B)
+#define BIT_SET_LTR_SPACE_IDX_8822B(x, v)                                      \
+	(BIT_CLEAR_LTR_SPACE_IDX_8822B(x) | BIT_LTR_SPACE_IDX_8822B(v))
+
+#define BIT_SHIFT_LTR_IDLE_TIMER_IDX_8822B 0
+#define BIT_MASK_LTR_IDLE_TIMER_IDX_8822B 0x7
+#define BIT_LTR_IDLE_TIMER_IDX_8822B(x)                                        \
+	(((x) & BIT_MASK_LTR_IDLE_TIMER_IDX_8822B)                             \
+	 << BIT_SHIFT_LTR_IDLE_TIMER_IDX_8822B)
+#define BITS_LTR_IDLE_TIMER_IDX_8822B                                          \
+	(BIT_MASK_LTR_IDLE_TIMER_IDX_8822B                                     \
+	 << BIT_SHIFT_LTR_IDLE_TIMER_IDX_8822B)
+#define BIT_CLEAR_LTR_IDLE_TIMER_IDX_8822B(x)                                  \
+	((x) & (~BITS_LTR_IDLE_TIMER_IDX_8822B))
+#define BIT_GET_LTR_IDLE_TIMER_IDX_8822B(x)                                    \
+	(((x) >> BIT_SHIFT_LTR_IDLE_TIMER_IDX_8822B) &                         \
+	 BIT_MASK_LTR_IDLE_TIMER_IDX_8822B)
+#define BIT_SET_LTR_IDLE_TIMER_IDX_8822B(x, v)                                 \
+	(BIT_CLEAR_LTR_IDLE_TIMER_IDX_8822B(x) |                               \
+	 BIT_LTR_IDLE_TIMER_IDX_8822B(v))
+
+/* 2 REG_LTR_IDLE_LATENCY_V1_8822B */
+
+#define BIT_SHIFT_LTR_IDLE_L_8822B 0
+#define BIT_MASK_LTR_IDLE_L_8822B 0xffffffffL
+#define BIT_LTR_IDLE_L_8822B(x)                                                \
+	(((x) & BIT_MASK_LTR_IDLE_L_8822B) << BIT_SHIFT_LTR_IDLE_L_8822B)
+#define BITS_LTR_IDLE_L_8822B                                                  \
+	(BIT_MASK_LTR_IDLE_L_8822B << BIT_SHIFT_LTR_IDLE_L_8822B)
+#define BIT_CLEAR_LTR_IDLE_L_8822B(x) ((x) & (~BITS_LTR_IDLE_L_8822B))
+#define BIT_GET_LTR_IDLE_L_8822B(x)                                            \
+	(((x) >> BIT_SHIFT_LTR_IDLE_L_8822B) & BIT_MASK_LTR_IDLE_L_8822B)
+#define BIT_SET_LTR_IDLE_L_8822B(x, v)                                         \
+	(BIT_CLEAR_LTR_IDLE_L_8822B(x) | BIT_LTR_IDLE_L_8822B(v))
+
+/* 2 REG_LTR_ACTIVE_LATENCY_V1_8822B */
+
+#define BIT_SHIFT_LTR_ACT_L_8822B 0
+#define BIT_MASK_LTR_ACT_L_8822B 0xffffffffL
+#define BIT_LTR_ACT_L_8822B(x)                                                 \
+	(((x) & BIT_MASK_LTR_ACT_L_8822B) << BIT_SHIFT_LTR_ACT_L_8822B)
+#define BITS_LTR_ACT_L_8822B                                                   \
+	(BIT_MASK_LTR_ACT_L_8822B << BIT_SHIFT_LTR_ACT_L_8822B)
+#define BIT_CLEAR_LTR_ACT_L_8822B(x) ((x) & (~BITS_LTR_ACT_L_8822B))
+#define BIT_GET_LTR_ACT_L_8822B(x)                                             \
+	(((x) >> BIT_SHIFT_LTR_ACT_L_8822B) & BIT_MASK_LTR_ACT_L_8822B)
+#define BIT_SET_LTR_ACT_L_8822B(x, v)                                          \
+	(BIT_CLEAR_LTR_ACT_L_8822B(x) | BIT_LTR_ACT_L_8822B(v))
+
+/* 2 REG_ANTENNA_TRAINING_CONTROL_REGISTER_8822B */
+#define BIT_APPEND_MACID_IN_RESP_EN_8822B BIT(50)
+#define BIT_ADDR2_MATCH_EN_8822B BIT(49)
+#define BIT_ANTTRN_EN_8822B BIT(48)
+
+#define BIT_SHIFT_TRAIN_STA_ADDR_8822B 0
+#define BIT_MASK_TRAIN_STA_ADDR_8822B 0xffffffffffffL
+#define BIT_TRAIN_STA_ADDR_8822B(x)                                            \
+	(((x) & BIT_MASK_TRAIN_STA_ADDR_8822B)                                 \
+	 << BIT_SHIFT_TRAIN_STA_ADDR_8822B)
+#define BITS_TRAIN_STA_ADDR_8822B                                              \
+	(BIT_MASK_TRAIN_STA_ADDR_8822B << BIT_SHIFT_TRAIN_STA_ADDR_8822B)
+#define BIT_CLEAR_TRAIN_STA_ADDR_8822B(x) ((x) & (~BITS_TRAIN_STA_ADDR_8822B))
+#define BIT_GET_TRAIN_STA_ADDR_8822B(x)                                        \
+	(((x) >> BIT_SHIFT_TRAIN_STA_ADDR_8822B) &                             \
+	 BIT_MASK_TRAIN_STA_ADDR_8822B)
+#define BIT_SET_TRAIN_STA_ADDR_8822B(x, v)                                     \
+	(BIT_CLEAR_TRAIN_STA_ADDR_8822B(x) | BIT_TRAIN_STA_ADDR_8822B(v))
+
+/* 2 REG_RSVD_0X7B4_8822B */
+
+/* 2 REG_WMAC_PKTCNT_RWD_8822B */
+
+#define BIT_SHIFT_PKTCNT_BSSIDMAP_8822B 4
+#define BIT_MASK_PKTCNT_BSSIDMAP_8822B 0xf
+#define BIT_PKTCNT_BSSIDMAP_8822B(x)                                           \
+	(((x) & BIT_MASK_PKTCNT_BSSIDMAP_8822B)                                \
+	 << BIT_SHIFT_PKTCNT_BSSIDMAP_8822B)
+#define BITS_PKTCNT_BSSIDMAP_8822B                                             \
+	(BIT_MASK_PKTCNT_BSSIDMAP_8822B << BIT_SHIFT_PKTCNT_BSSIDMAP_8822B)
+#define BIT_CLEAR_PKTCNT_BSSIDMAP_8822B(x) ((x) & (~BITS_PKTCNT_BSSIDMAP_8822B))
+#define BIT_GET_PKTCNT_BSSIDMAP_8822B(x)                                       \
+	(((x) >> BIT_SHIFT_PKTCNT_BSSIDMAP_8822B) &                            \
+	 BIT_MASK_PKTCNT_BSSIDMAP_8822B)
+#define BIT_SET_PKTCNT_BSSIDMAP_8822B(x, v)                                    \
+	(BIT_CLEAR_PKTCNT_BSSIDMAP_8822B(x) | BIT_PKTCNT_BSSIDMAP_8822B(v))
+
+#define BIT_PKTCNT_CNTRST_8822B BIT(1)
+#define BIT_PKTCNT_CNTEN_8822B BIT(0)
+
+/* 2 REG_WMAC_PKTCNT_CTRL_8822B */
+#define BIT_WMAC_PKTCNT_TRST_8822B BIT(9)
+#define BIT_WMAC_PKTCNT_FEN_8822B BIT(8)
+
+#define BIT_SHIFT_WMAC_PKTCNT_CFGAD_8822B 0
+#define BIT_MASK_WMAC_PKTCNT_CFGAD_8822B 0xff
+#define BIT_WMAC_PKTCNT_CFGAD_8822B(x)                                         \
+	(((x) & BIT_MASK_WMAC_PKTCNT_CFGAD_8822B)                              \
+	 << BIT_SHIFT_WMAC_PKTCNT_CFGAD_8822B)
+#define BITS_WMAC_PKTCNT_CFGAD_8822B                                           \
+	(BIT_MASK_WMAC_PKTCNT_CFGAD_8822B << BIT_SHIFT_WMAC_PKTCNT_CFGAD_8822B)
+#define BIT_CLEAR_WMAC_PKTCNT_CFGAD_8822B(x)                                   \
+	((x) & (~BITS_WMAC_PKTCNT_CFGAD_8822B))
+#define BIT_GET_WMAC_PKTCNT_CFGAD_8822B(x)                                     \
+	(((x) >> BIT_SHIFT_WMAC_PKTCNT_CFGAD_8822B) &                          \
+	 BIT_MASK_WMAC_PKTCNT_CFGAD_8822B)
+#define BIT_SET_WMAC_PKTCNT_CFGAD_8822B(x, v)                                  \
+	(BIT_CLEAR_WMAC_PKTCNT_CFGAD_8822B(x) | BIT_WMAC_PKTCNT_CFGAD_8822B(v))
+
+/* 2 REG_IQ_DUMP_8822B */
+
+#define BIT_SHIFT_R_WMAC_MATCH_REF_MAC_8822B (64 & CPU_OPT_WIDTH)
+#define BIT_MASK_R_WMAC_MATCH_REF_MAC_8822B 0xffffffffL
+#define BIT_R_WMAC_MATCH_REF_MAC_8822B(x)                                      \
+	(((x) & BIT_MASK_R_WMAC_MATCH_REF_MAC_8822B)                           \
+	 << BIT_SHIFT_R_WMAC_MATCH_REF_MAC_8822B)
+#define BITS_R_WMAC_MATCH_REF_MAC_8822B                                        \
+	(BIT_MASK_R_WMAC_MATCH_REF_MAC_8822B                                   \
+	 << BIT_SHIFT_R_WMAC_MATCH_REF_MAC_8822B)
+#define BIT_CLEAR_R_WMAC_MATCH_REF_MAC_8822B(x)                                \
+	((x) & (~BITS_R_WMAC_MATCH_REF_MAC_8822B))
+#define BIT_GET_R_WMAC_MATCH_REF_MAC_8822B(x)                                  \
+	(((x) >> BIT_SHIFT_R_WMAC_MATCH_REF_MAC_8822B) &                       \
+	 BIT_MASK_R_WMAC_MATCH_REF_MAC_8822B)
+#define BIT_SET_R_WMAC_MATCH_REF_MAC_8822B(x, v)                               \
+	(BIT_CLEAR_R_WMAC_MATCH_REF_MAC_8822B(x) |                             \
+	 BIT_R_WMAC_MATCH_REF_MAC_8822B(v))
+
+#define BIT_SHIFT_R_WMAC_MASK_LA_MAC_8822B (32 & CPU_OPT_WIDTH)
+#define BIT_MASK_R_WMAC_MASK_LA_MAC_8822B 0xffffffffL
+#define BIT_R_WMAC_MASK_LA_MAC_8822B(x)                                        \
+	(((x) & BIT_MASK_R_WMAC_MASK_LA_MAC_8822B)                             \
+	 << BIT_SHIFT_R_WMAC_MASK_LA_MAC_8822B)
+#define BITS_R_WMAC_MASK_LA_MAC_8822B                                          \
+	(BIT_MASK_R_WMAC_MASK_LA_MAC_8822B                                     \
+	 << BIT_SHIFT_R_WMAC_MASK_LA_MAC_8822B)
+#define BIT_CLEAR_R_WMAC_MASK_LA_MAC_8822B(x)                                  \
+	((x) & (~BITS_R_WMAC_MASK_LA_MAC_8822B))
+#define BIT_GET_R_WMAC_MASK_LA_MAC_8822B(x)                                    \
+	(((x) >> BIT_SHIFT_R_WMAC_MASK_LA_MAC_8822B) &                         \
+	 BIT_MASK_R_WMAC_MASK_LA_MAC_8822B)
+#define BIT_SET_R_WMAC_MASK_LA_MAC_8822B(x, v)                                 \
+	(BIT_CLEAR_R_WMAC_MASK_LA_MAC_8822B(x) |                               \
+	 BIT_R_WMAC_MASK_LA_MAC_8822B(v))
+
+#define BIT_SHIFT_DUMP_OK_ADDR_8822B 16
+#define BIT_MASK_DUMP_OK_ADDR_8822B 0xffff
+#define BIT_DUMP_OK_ADDR_8822B(x)                                              \
+	(((x) & BIT_MASK_DUMP_OK_ADDR_8822B) << BIT_SHIFT_DUMP_OK_ADDR_8822B)
+#define BITS_DUMP_OK_ADDR_8822B                                                \
+	(BIT_MASK_DUMP_OK_ADDR_8822B << BIT_SHIFT_DUMP_OK_ADDR_8822B)
+#define BIT_CLEAR_DUMP_OK_ADDR_8822B(x) ((x) & (~BITS_DUMP_OK_ADDR_8822B))
+#define BIT_GET_DUMP_OK_ADDR_8822B(x)                                          \
+	(((x) >> BIT_SHIFT_DUMP_OK_ADDR_8822B) & BIT_MASK_DUMP_OK_ADDR_8822B)
+#define BIT_SET_DUMP_OK_ADDR_8822B(x, v)                                       \
+	(BIT_CLEAR_DUMP_OK_ADDR_8822B(x) | BIT_DUMP_OK_ADDR_8822B(v))
+
+#define BIT_SHIFT_R_TRIG_TIME_SEL_8822B 8
+#define BIT_MASK_R_TRIG_TIME_SEL_8822B 0x7f
+#define BIT_R_TRIG_TIME_SEL_8822B(x)                                           \
+	(((x) & BIT_MASK_R_TRIG_TIME_SEL_8822B)                                \
+	 << BIT_SHIFT_R_TRIG_TIME_SEL_8822B)
+#define BITS_R_TRIG_TIME_SEL_8822B                                             \
+	(BIT_MASK_R_TRIG_TIME_SEL_8822B << BIT_SHIFT_R_TRIG_TIME_SEL_8822B)
+#define BIT_CLEAR_R_TRIG_TIME_SEL_8822B(x) ((x) & (~BITS_R_TRIG_TIME_SEL_8822B))
+#define BIT_GET_R_TRIG_TIME_SEL_8822B(x)                                       \
+	(((x) >> BIT_SHIFT_R_TRIG_TIME_SEL_8822B) &                            \
+	 BIT_MASK_R_TRIG_TIME_SEL_8822B)
+#define BIT_SET_R_TRIG_TIME_SEL_8822B(x, v)                                    \
+	(BIT_CLEAR_R_TRIG_TIME_SEL_8822B(x) | BIT_R_TRIG_TIME_SEL_8822B(v))
+
+#define BIT_SHIFT_R_MAC_TRIG_SEL_8822B 6
+#define BIT_MASK_R_MAC_TRIG_SEL_8822B 0x3
+#define BIT_R_MAC_TRIG_SEL_8822B(x)                                            \
+	(((x) & BIT_MASK_R_MAC_TRIG_SEL_8822B)                                 \
+	 << BIT_SHIFT_R_MAC_TRIG_SEL_8822B)
+#define BITS_R_MAC_TRIG_SEL_8822B                                              \
+	(BIT_MASK_R_MAC_TRIG_SEL_8822B << BIT_SHIFT_R_MAC_TRIG_SEL_8822B)
+#define BIT_CLEAR_R_MAC_TRIG_SEL_8822B(x) ((x) & (~BITS_R_MAC_TRIG_SEL_8822B))
+#define BIT_GET_R_MAC_TRIG_SEL_8822B(x)                                        \
+	(((x) >> BIT_SHIFT_R_MAC_TRIG_SEL_8822B) &                             \
+	 BIT_MASK_R_MAC_TRIG_SEL_8822B)
+#define BIT_SET_R_MAC_TRIG_SEL_8822B(x, v)                                     \
+	(BIT_CLEAR_R_MAC_TRIG_SEL_8822B(x) | BIT_R_MAC_TRIG_SEL_8822B(v))
+
+#define BIT_MAC_TRIG_REG_8822B BIT(5)
+
+#define BIT_SHIFT_R_LEVEL_PULSE_SEL_8822B 3
+#define BIT_MASK_R_LEVEL_PULSE_SEL_8822B 0x3
+#define BIT_R_LEVEL_PULSE_SEL_8822B(x)                                         \
+	(((x) & BIT_MASK_R_LEVEL_PULSE_SEL_8822B)                              \
+	 << BIT_SHIFT_R_LEVEL_PULSE_SEL_8822B)
+#define BITS_R_LEVEL_PULSE_SEL_8822B                                           \
+	(BIT_MASK_R_LEVEL_PULSE_SEL_8822B << BIT_SHIFT_R_LEVEL_PULSE_SEL_8822B)
+#define BIT_CLEAR_R_LEVEL_PULSE_SEL_8822B(x)                                   \
+	((x) & (~BITS_R_LEVEL_PULSE_SEL_8822B))
+#define BIT_GET_R_LEVEL_PULSE_SEL_8822B(x)                                     \
+	(((x) >> BIT_SHIFT_R_LEVEL_PULSE_SEL_8822B) &                          \
+	 BIT_MASK_R_LEVEL_PULSE_SEL_8822B)
+#define BIT_SET_R_LEVEL_PULSE_SEL_8822B(x, v)                                  \
+	(BIT_CLEAR_R_LEVEL_PULSE_SEL_8822B(x) | BIT_R_LEVEL_PULSE_SEL_8822B(v))
+
+#define BIT_EN_LA_MAC_8822B BIT(2)
+#define BIT_R_EN_IQDUMP_8822B BIT(1)
+#define BIT_R_IQDATA_DUMP_8822B BIT(0)
+
+/* 2 REG_WMAC_FTM_CTL_8822B */
+#define BIT_RXFTM_TXACK_SC_8822B BIT(6)
+#define BIT_RXFTM_TXACK_BW_8822B BIT(5)
+#define BIT_RXFTM_EN_8822B BIT(3)
+#define BIT_RXFTMREQ_BYDRV_8822B BIT(2)
+#define BIT_RXFTMREQ_EN_8822B BIT(1)
+#define BIT_FTM_EN_8822B BIT(0)
+
+/* 2 REG_WMAC_IQ_MDPK_FUNC_8822B */
+
+/* 2 REG_WMAC_OPTION_FUNCTION_8822B */
+
+#define BIT_SHIFT_R_WMAC_RX_FIL_LEN_8822B (64 & CPU_OPT_WIDTH)
+#define BIT_MASK_R_WMAC_RX_FIL_LEN_8822B 0xffff
+#define BIT_R_WMAC_RX_FIL_LEN_8822B(x)                                         \
+	(((x) & BIT_MASK_R_WMAC_RX_FIL_LEN_8822B)                              \
+	 << BIT_SHIFT_R_WMAC_RX_FIL_LEN_8822B)
+#define BITS_R_WMAC_RX_FIL_LEN_8822B                                           \
+	(BIT_MASK_R_WMAC_RX_FIL_LEN_8822B << BIT_SHIFT_R_WMAC_RX_FIL_LEN_8822B)
+#define BIT_CLEAR_R_WMAC_RX_FIL_LEN_8822B(x)                                   \
+	((x) & (~BITS_R_WMAC_RX_FIL_LEN_8822B))
+#define BIT_GET_R_WMAC_RX_FIL_LEN_8822B(x)                                     \
+	(((x) >> BIT_SHIFT_R_WMAC_RX_FIL_LEN_8822B) &                          \
+	 BIT_MASK_R_WMAC_RX_FIL_LEN_8822B)
+#define BIT_SET_R_WMAC_RX_FIL_LEN_8822B(x, v)                                  \
+	(BIT_CLEAR_R_WMAC_RX_FIL_LEN_8822B(x) | BIT_R_WMAC_RX_FIL_LEN_8822B(v))
+
+#define BIT_SHIFT_R_WMAC_RXFIFO_FULL_TH_8822B (56 & CPU_OPT_WIDTH)
+#define BIT_MASK_R_WMAC_RXFIFO_FULL_TH_8822B 0xff
+#define BIT_R_WMAC_RXFIFO_FULL_TH_8822B(x)                                     \
+	(((x) & BIT_MASK_R_WMAC_RXFIFO_FULL_TH_8822B)                          \
+	 << BIT_SHIFT_R_WMAC_RXFIFO_FULL_TH_8822B)
+#define BITS_R_WMAC_RXFIFO_FULL_TH_8822B                                       \
+	(BIT_MASK_R_WMAC_RXFIFO_FULL_TH_8822B                                  \
+	 << BIT_SHIFT_R_WMAC_RXFIFO_FULL_TH_8822B)
+#define BIT_CLEAR_R_WMAC_RXFIFO_FULL_TH_8822B(x)                               \
+	((x) & (~BITS_R_WMAC_RXFIFO_FULL_TH_8822B))
+#define BIT_GET_R_WMAC_RXFIFO_FULL_TH_8822B(x)                                 \
+	(((x) >> BIT_SHIFT_R_WMAC_RXFIFO_FULL_TH_8822B) &                      \
+	 BIT_MASK_R_WMAC_RXFIFO_FULL_TH_8822B)
+#define BIT_SET_R_WMAC_RXFIFO_FULL_TH_8822B(x, v)                              \
+	(BIT_CLEAR_R_WMAC_RXFIFO_FULL_TH_8822B(x) |                            \
+	 BIT_R_WMAC_RXFIFO_FULL_TH_8822B(v))
+
+#define BIT_R_WMAC_RX_SYNCFIFO_SYNC_8822B BIT(55)
+#define BIT_R_WMAC_RXRST_DLY_8822B BIT(54)
+#define BIT_R_WMAC_SRCH_TXRPT_REF_DROP_8822B BIT(53)
+#define BIT_R_WMAC_SRCH_TXRPT_UA1_8822B BIT(52)
+#define BIT_R_WMAC_SRCH_TXRPT_TYPE_8822B BIT(51)
+#define BIT_R_WMAC_NDP_RST_8822B BIT(50)
+#define BIT_R_WMAC_POWINT_EN_8822B BIT(49)
+#define BIT_R_WMAC_SRCH_TXRPT_PERPKT_8822B BIT(48)
+#define BIT_R_WMAC_SRCH_TXRPT_MID_8822B BIT(47)
+#define BIT_R_WMAC_PFIN_TOEN_8822B BIT(46)
+#define BIT_R_WMAC_FIL_SECERR_8822B BIT(45)
+#define BIT_R_WMAC_FIL_CTLPKTLEN_8822B BIT(44)
+#define BIT_R_WMAC_FIL_FCTYPE_8822B BIT(43)
+#define BIT_R_WMAC_FIL_FCPROVER_8822B BIT(42)
+#define BIT_R_WMAC_PHYSTS_SNIF_8822B BIT(41)
+#define BIT_R_WMAC_PHYSTS_PLCP_8822B BIT(40)
+#define BIT_R_MAC_TCR_VBONF_RD_8822B BIT(39)
+#define BIT_R_WMAC_TCR_MPAR_NDP_8822B BIT(38)
+#define BIT_R_WMAC_NDP_FILTER_8822B BIT(37)
+#define BIT_R_WMAC_RXLEN_SEL_8822B BIT(36)
+#define BIT_R_WMAC_RXLEN_SEL1_8822B BIT(35)
+#define BIT_R_OFDM_FILTER_8822B BIT(34)
+#define BIT_R_WMAC_CHK_OFDM_LEN_8822B BIT(33)
+#define BIT_R_WMAC_CHK_CCK_LEN_8822B BIT(32)
+
+#define BIT_SHIFT_R_OFDM_LEN_8822B 26
+#define BIT_MASK_R_OFDM_LEN_8822B 0x3f
+#define BIT_R_OFDM_LEN_8822B(x)                                                \
+	(((x) & BIT_MASK_R_OFDM_LEN_8822B) << BIT_SHIFT_R_OFDM_LEN_8822B)
+#define BITS_R_OFDM_LEN_8822B                                                  \
+	(BIT_MASK_R_OFDM_LEN_8822B << BIT_SHIFT_R_OFDM_LEN_8822B)
+#define BIT_CLEAR_R_OFDM_LEN_8822B(x) ((x) & (~BITS_R_OFDM_LEN_8822B))
+#define BIT_GET_R_OFDM_LEN_8822B(x)                                            \
+	(((x) >> BIT_SHIFT_R_OFDM_LEN_8822B) & BIT_MASK_R_OFDM_LEN_8822B)
+#define BIT_SET_R_OFDM_LEN_8822B(x, v)                                         \
+	(BIT_CLEAR_R_OFDM_LEN_8822B(x) | BIT_R_OFDM_LEN_8822B(v))
+
+#define BIT_SHIFT_R_CCK_LEN_8822B 0
+#define BIT_MASK_R_CCK_LEN_8822B 0xffff
+#define BIT_R_CCK_LEN_8822B(x)                                                 \
+	(((x) & BIT_MASK_R_CCK_LEN_8822B) << BIT_SHIFT_R_CCK_LEN_8822B)
+#define BITS_R_CCK_LEN_8822B                                                   \
+	(BIT_MASK_R_CCK_LEN_8822B << BIT_SHIFT_R_CCK_LEN_8822B)
+#define BIT_CLEAR_R_CCK_LEN_8822B(x) ((x) & (~BITS_R_CCK_LEN_8822B))
+#define BIT_GET_R_CCK_LEN_8822B(x)                                             \
+	(((x) >> BIT_SHIFT_R_CCK_LEN_8822B) & BIT_MASK_R_CCK_LEN_8822B)
+#define BIT_SET_R_CCK_LEN_8822B(x, v)                                          \
+	(BIT_CLEAR_R_CCK_LEN_8822B(x) | BIT_R_CCK_LEN_8822B(v))
+
+/* 2 REG_RX_FILTER_FUNCTION_8822B */
+#define BIT_R_WMAC_MHRDDY_LATCH_8822B BIT(14)
+#define BIT_R_WMAC_MHRDDY_CLR_8822B BIT(13)
+#define BIT_R_RXPKTCTL_FSM_BASED_MPDURDY1_8822B BIT(12)
+#define BIT_WMAC_DIS_VHT_PLCP_CHK_MU_8822B BIT(11)
+#define BIT_R_CHK_DELIMIT_LEN_8822B BIT(10)
+#define BIT_R_REAPTER_ADDR_MATCH_8822B BIT(9)
+#define BIT_R_RXPKTCTL_FSM_BASED_MPDURDY_8822B BIT(8)
+#define BIT_R_LATCH_MACHRDY_8822B BIT(7)
+#define BIT_R_WMAC_RXFIL_REND_8822B BIT(6)
+#define BIT_R_WMAC_MPDURDY_CLR_8822B BIT(5)
+#define BIT_R_WMAC_CLRRXSEC_8822B BIT(4)
+#define BIT_R_WMAC_RXFIL_RDEL_8822B BIT(3)
+#define BIT_R_WMAC_RXFIL_FCSE_8822B BIT(2)
+#define BIT_R_WMAC_RXFIL_MESH_DEL_8822B BIT(1)
+#define BIT_R_WMAC_RXFIL_MASKM_8822B BIT(0)
+
+/* 2 REG_NDP_SIG_8822B */
+
+#define BIT_SHIFT_R_WMAC_TXNDP_SIGB_8822B 0
+#define BIT_MASK_R_WMAC_TXNDP_SIGB_8822B 0x1fffff
+#define BIT_R_WMAC_TXNDP_SIGB_8822B(x)                                         \
+	(((x) & BIT_MASK_R_WMAC_TXNDP_SIGB_8822B)                              \
+	 << BIT_SHIFT_R_WMAC_TXNDP_SIGB_8822B)
+#define BITS_R_WMAC_TXNDP_SIGB_8822B                                           \
+	(BIT_MASK_R_WMAC_TXNDP_SIGB_8822B << BIT_SHIFT_R_WMAC_TXNDP_SIGB_8822B)
+#define BIT_CLEAR_R_WMAC_TXNDP_SIGB_8822B(x)                                   \
+	((x) & (~BITS_R_WMAC_TXNDP_SIGB_8822B))
+#define BIT_GET_R_WMAC_TXNDP_SIGB_8822B(x)                                     \
+	(((x) >> BIT_SHIFT_R_WMAC_TXNDP_SIGB_8822B) &                          \
+	 BIT_MASK_R_WMAC_TXNDP_SIGB_8822B)
+#define BIT_SET_R_WMAC_TXNDP_SIGB_8822B(x, v)                                  \
+	(BIT_CLEAR_R_WMAC_TXNDP_SIGB_8822B(x) | BIT_R_WMAC_TXNDP_SIGB_8822B(v))
+
+/* 2 REG_TXCMD_INFO_FOR_RSP_PKT_8822B */
+
+#define BIT_SHIFT_R_MAC_DEBUG_8822B (32 & CPU_OPT_WIDTH)
+#define BIT_MASK_R_MAC_DEBUG_8822B 0xffffffffL
+#define BIT_R_MAC_DEBUG_8822B(x)                                               \
+	(((x) & BIT_MASK_R_MAC_DEBUG_8822B) << BIT_SHIFT_R_MAC_DEBUG_8822B)
+#define BITS_R_MAC_DEBUG_8822B                                                 \
+	(BIT_MASK_R_MAC_DEBUG_8822B << BIT_SHIFT_R_MAC_DEBUG_8822B)
+#define BIT_CLEAR_R_MAC_DEBUG_8822B(x) ((x) & (~BITS_R_MAC_DEBUG_8822B))
+#define BIT_GET_R_MAC_DEBUG_8822B(x)                                           \
+	(((x) >> BIT_SHIFT_R_MAC_DEBUG_8822B) & BIT_MASK_R_MAC_DEBUG_8822B)
+#define BIT_SET_R_MAC_DEBUG_8822B(x, v)                                        \
+	(BIT_CLEAR_R_MAC_DEBUG_8822B(x) | BIT_R_MAC_DEBUG_8822B(v))
+
+#define BIT_SHIFT_R_MAC_DBG_SHIFT_8822B 8
+#define BIT_MASK_R_MAC_DBG_SHIFT_8822B 0x7
+#define BIT_R_MAC_DBG_SHIFT_8822B(x)                                           \
+	(((x) & BIT_MASK_R_MAC_DBG_SHIFT_8822B)                                \
+	 << BIT_SHIFT_R_MAC_DBG_SHIFT_8822B)
+#define BITS_R_MAC_DBG_SHIFT_8822B                                             \
+	(BIT_MASK_R_MAC_DBG_SHIFT_8822B << BIT_SHIFT_R_MAC_DBG_SHIFT_8822B)
+#define BIT_CLEAR_R_MAC_DBG_SHIFT_8822B(x) ((x) & (~BITS_R_MAC_DBG_SHIFT_8822B))
+#define BIT_GET_R_MAC_DBG_SHIFT_8822B(x)                                       \
+	(((x) >> BIT_SHIFT_R_MAC_DBG_SHIFT_8822B) &                            \
+	 BIT_MASK_R_MAC_DBG_SHIFT_8822B)
+#define BIT_SET_R_MAC_DBG_SHIFT_8822B(x, v)                                    \
+	(BIT_CLEAR_R_MAC_DBG_SHIFT_8822B(x) | BIT_R_MAC_DBG_SHIFT_8822B(v))
+
+#define BIT_SHIFT_R_MAC_DBG_SEL_8822B 0
+#define BIT_MASK_R_MAC_DBG_SEL_8822B 0x3
+#define BIT_R_MAC_DBG_SEL_8822B(x)                                             \
+	(((x) & BIT_MASK_R_MAC_DBG_SEL_8822B) << BIT_SHIFT_R_MAC_DBG_SEL_8822B)
+#define BITS_R_MAC_DBG_SEL_8822B                                               \
+	(BIT_MASK_R_MAC_DBG_SEL_8822B << BIT_SHIFT_R_MAC_DBG_SEL_8822B)
+#define BIT_CLEAR_R_MAC_DBG_SEL_8822B(x) ((x) & (~BITS_R_MAC_DBG_SEL_8822B))
+#define BIT_GET_R_MAC_DBG_SEL_8822B(x)                                         \
+	(((x) >> BIT_SHIFT_R_MAC_DBG_SEL_8822B) & BIT_MASK_R_MAC_DBG_SEL_8822B)
+#define BIT_SET_R_MAC_DBG_SEL_8822B(x, v)                                      \
+	(BIT_CLEAR_R_MAC_DBG_SEL_8822B(x) | BIT_R_MAC_DBG_SEL_8822B(v))
+
+/* 2 REG_RTS_ADDRESS_0_8822B */
+
+/* 2 REG_RTS_ADDRESS_1_8822B */
+
+/* 2 REG_RPFM_MAP1_8822B */
+#define BIT_DATA_RPFM15EN_8822B BIT(15)
+#define BIT_DATA_RPFM14EN_8822B BIT(14)
+#define BIT_DATA_RPFM13EN_8822B BIT(13)
+#define BIT_DATA_RPFM12EN_8822B BIT(12)
+#define BIT_DATA_RPFM11EN_8822B BIT(11)
+#define BIT_DATA_RPFM10EN_8822B BIT(10)
+#define BIT_DATA_RPFM9EN_8822B BIT(9)
+#define BIT_DATA_RPFM8EN_8822B BIT(8)
+#define BIT_DATA_RPFM7EN_8822B BIT(7)
+#define BIT_DATA_RPFM6EN_8822B BIT(6)
+#define BIT_DATA_RPFM5EN_8822B BIT(5)
+#define BIT_DATA_RPFM4EN_8822B BIT(4)
+#define BIT_DATA_RPFM3EN_8822B BIT(3)
+#define BIT_DATA_RPFM2EN_8822B BIT(2)
+#define BIT_DATA_RPFM1EN_8822B BIT(1)
+#define BIT_DATA_RPFM0EN_8822B BIT(0)
+
+/* 2 REG_WL2LTECOEX_INDIRECT_ACCESS_CTRL_V1_8822B */
+#define BIT_LTECOEX_ACCESS_START_V1_8822B BIT(31)
+#define BIT_LTECOEX_WRITE_MODE_V1_8822B BIT(30)
+#define BIT_LTECOEX_READY_BIT_V1_8822B BIT(29)
+
+#define BIT_SHIFT_WRITE_BYTE_EN_V1_8822B 16
+#define BIT_MASK_WRITE_BYTE_EN_V1_8822B 0xf
+#define BIT_WRITE_BYTE_EN_V1_8822B(x)                                          \
+	(((x) & BIT_MASK_WRITE_BYTE_EN_V1_8822B)                               \
+	 << BIT_SHIFT_WRITE_BYTE_EN_V1_8822B)
+#define BITS_WRITE_BYTE_EN_V1_8822B                                            \
+	(BIT_MASK_WRITE_BYTE_EN_V1_8822B << BIT_SHIFT_WRITE_BYTE_EN_V1_8822B)
+#define BIT_CLEAR_WRITE_BYTE_EN_V1_8822B(x)                                    \
+	((x) & (~BITS_WRITE_BYTE_EN_V1_8822B))
+#define BIT_GET_WRITE_BYTE_EN_V1_8822B(x)                                      \
+	(((x) >> BIT_SHIFT_WRITE_BYTE_EN_V1_8822B) &                           \
+	 BIT_MASK_WRITE_BYTE_EN_V1_8822B)
+#define BIT_SET_WRITE_BYTE_EN_V1_8822B(x, v)                                   \
+	(BIT_CLEAR_WRITE_BYTE_EN_V1_8822B(x) | BIT_WRITE_BYTE_EN_V1_8822B(v))
+
+#define BIT_SHIFT_LTECOEX_REG_ADDR_V1_8822B 0
+#define BIT_MASK_LTECOEX_REG_ADDR_V1_8822B 0xffff
+#define BIT_LTECOEX_REG_ADDR_V1_8822B(x)                                       \
+	(((x) & BIT_MASK_LTECOEX_REG_ADDR_V1_8822B)                            \
+	 << BIT_SHIFT_LTECOEX_REG_ADDR_V1_8822B)
+#define BITS_LTECOEX_REG_ADDR_V1_8822B                                         \
+	(BIT_MASK_LTECOEX_REG_ADDR_V1_8822B                                    \
+	 << BIT_SHIFT_LTECOEX_REG_ADDR_V1_8822B)
+#define BIT_CLEAR_LTECOEX_REG_ADDR_V1_8822B(x)                                 \
+	((x) & (~BITS_LTECOEX_REG_ADDR_V1_8822B))
+#define BIT_GET_LTECOEX_REG_ADDR_V1_8822B(x)                                   \
+	(((x) >> BIT_SHIFT_LTECOEX_REG_ADDR_V1_8822B) &                        \
+	 BIT_MASK_LTECOEX_REG_ADDR_V1_8822B)
+#define BIT_SET_LTECOEX_REG_ADDR_V1_8822B(x, v)                                \
+	(BIT_CLEAR_LTECOEX_REG_ADDR_V1_8822B(x) |                              \
+	 BIT_LTECOEX_REG_ADDR_V1_8822B(v))
+
+/* 2 REG_WL2LTECOEX_INDIRECT_ACCESS_WRITE_DATA_V1_8822B */
+
+#define BIT_SHIFT_LTECOEX_W_DATA_V1_8822B 0
+#define BIT_MASK_LTECOEX_W_DATA_V1_8822B 0xffffffffL
+#define BIT_LTECOEX_W_DATA_V1_8822B(x)                                         \
+	(((x) & BIT_MASK_LTECOEX_W_DATA_V1_8822B)                              \
+	 << BIT_SHIFT_LTECOEX_W_DATA_V1_8822B)
+#define BITS_LTECOEX_W_DATA_V1_8822B                                           \
+	(BIT_MASK_LTECOEX_W_DATA_V1_8822B << BIT_SHIFT_LTECOEX_W_DATA_V1_8822B)
+#define BIT_CLEAR_LTECOEX_W_DATA_V1_8822B(x)                                   \
+	((x) & (~BITS_LTECOEX_W_DATA_V1_8822B))
+#define BIT_GET_LTECOEX_W_DATA_V1_8822B(x)                                     \
+	(((x) >> BIT_SHIFT_LTECOEX_W_DATA_V1_8822B) &                          \
+	 BIT_MASK_LTECOEX_W_DATA_V1_8822B)
+#define BIT_SET_LTECOEX_W_DATA_V1_8822B(x, v)                                  \
+	(BIT_CLEAR_LTECOEX_W_DATA_V1_8822B(x) | BIT_LTECOEX_W_DATA_V1_8822B(v))
+
+/* 2 REG_WL2LTECOEX_INDIRECT_ACCESS_READ_DATA_V1_8822B */
+
+#define BIT_SHIFT_LTECOEX_R_DATA_V1_8822B 0
+#define BIT_MASK_LTECOEX_R_DATA_V1_8822B 0xffffffffL
+#define BIT_LTECOEX_R_DATA_V1_8822B(x)                                         \
+	(((x) & BIT_MASK_LTECOEX_R_DATA_V1_8822B)                              \
+	 << BIT_SHIFT_LTECOEX_R_DATA_V1_8822B)
+#define BITS_LTECOEX_R_DATA_V1_8822B                                           \
+	(BIT_MASK_LTECOEX_R_DATA_V1_8822B << BIT_SHIFT_LTECOEX_R_DATA_V1_8822B)
+#define BIT_CLEAR_LTECOEX_R_DATA_V1_8822B(x)                                   \
+	((x) & (~BITS_LTECOEX_R_DATA_V1_8822B))
+#define BIT_GET_LTECOEX_R_DATA_V1_8822B(x)                                     \
+	(((x) >> BIT_SHIFT_LTECOEX_R_DATA_V1_8822B) &                          \
+	 BIT_MASK_LTECOEX_R_DATA_V1_8822B)
+#define BIT_SET_LTECOEX_R_DATA_V1_8822B(x, v)                                  \
+	(BIT_CLEAR_LTECOEX_R_DATA_V1_8822B(x) | BIT_LTECOEX_R_DATA_V1_8822B(v))
+
+/* 2 REG_NOT_VALID_8822B */
+
+/* 2 REG_SDIO_TX_CTRL_8822B */
+
+#define BIT_SHIFT_SDIO_INT_TIMEOUT_8822B 16
+#define BIT_MASK_SDIO_INT_TIMEOUT_8822B 0xffff
+#define BIT_SDIO_INT_TIMEOUT_8822B(x)                                          \
+	(((x) & BIT_MASK_SDIO_INT_TIMEOUT_8822B)                               \
+	 << BIT_SHIFT_SDIO_INT_TIMEOUT_8822B)
+#define BITS_SDIO_INT_TIMEOUT_8822B                                            \
+	(BIT_MASK_SDIO_INT_TIMEOUT_8822B << BIT_SHIFT_SDIO_INT_TIMEOUT_8822B)
+#define BIT_CLEAR_SDIO_INT_TIMEOUT_8822B(x)                                    \
+	((x) & (~BITS_SDIO_INT_TIMEOUT_8822B))
+#define BIT_GET_SDIO_INT_TIMEOUT_8822B(x)                                      \
+	(((x) >> BIT_SHIFT_SDIO_INT_TIMEOUT_8822B) &                           \
+	 BIT_MASK_SDIO_INT_TIMEOUT_8822B)
+#define BIT_SET_SDIO_INT_TIMEOUT_8822B(x, v)                                   \
+	(BIT_CLEAR_SDIO_INT_TIMEOUT_8822B(x) | BIT_SDIO_INT_TIMEOUT_8822B(v))
+
+#define BIT_IO_ERR_STATUS_8822B BIT(15)
+#define BIT_REPLY_ERRCRC_IN_DATA_8822B BIT(9)
+#define BIT_EN_CMD53_OVERLAP_8822B BIT(8)
+#define BIT_REPLY_ERR_IN_R5_8822B BIT(7)
+#define BIT_R18A_EN_8822B BIT(6)
+#define BIT_SDIO_CMD_FORCE_VLD_8822B BIT(5)
+#define BIT_INIT_CMD_EN_8822B BIT(4)
+#define BIT_EN_RXDMA_MASK_INT_8822B BIT(2)
+#define BIT_EN_MASK_TIMER_8822B BIT(1)
+#define BIT_CMD_ERR_STOP_INT_EN_8822B BIT(0)
+
+/* 2 REG_SDIO_HIMR_8822B */
+#define BIT_SDIO_CRCERR_MSK_8822B BIT(31)
+#define BIT_SDIO_HSISR3_IND_MSK_8822B BIT(30)
+#define BIT_SDIO_HSISR2_IND_MSK_8822B BIT(29)
+#define BIT_SDIO_HEISR_IND_MSK_8822B BIT(28)
+#define BIT_SDIO_CTWEND_MSK_8822B BIT(27)
+#define BIT_SDIO_ATIMEND_E_MSK_8822B BIT(26)
+#define BIT_SDIIO_ATIMEND_MSK_8822B BIT(25)
+#define BIT_SDIO_OCPINT_MSK_8822B BIT(24)
+#define BIT_SDIO_PSTIMEOUT_MSK_8822B BIT(23)
+#define BIT_SDIO_GTINT4_MSK_8822B BIT(22)
+#define BIT_SDIO_GTINT3_MSK_8822B BIT(21)
+#define BIT_SDIO_HSISR_IND_MSK_8822B BIT(20)
+#define BIT_SDIO_CPWM2_MSK_8822B BIT(19)
+#define BIT_SDIO_CPWM1_MSK_8822B BIT(18)
+#define BIT_SDIO_C2HCMD_INT_MSK_8822B BIT(17)
+#define BIT_SDIO_BCNERLY_INT_MSK_8822B BIT(16)
+#define BIT_SDIO_TXBCNERR_MSK_8822B BIT(7)
+#define BIT_SDIO_TXBCNOK_MSK_8822B BIT(6)
+#define BIT_SDIO_RXFOVW_MSK_8822B BIT(5)
+#define BIT_SDIO_TXFOVW_MSK_8822B BIT(4)
+#define BIT_SDIO_RXERR_MSK_8822B BIT(3)
+#define BIT_SDIO_TXERR_MSK_8822B BIT(2)
+#define BIT_SDIO_AVAL_MSK_8822B BIT(1)
+#define BIT_RX_REQUEST_MSK_8822B BIT(0)
+
+/* 2 REG_SDIO_HISR_8822B */
+#define BIT_SDIO_CRCERR_8822B BIT(31)
+#define BIT_SDIO_HSISR3_IND_8822B BIT(30)
+#define BIT_SDIO_HSISR2_IND_8822B BIT(29)
+#define BIT_SDIO_HEISR_IND_8822B BIT(28)
+#define BIT_SDIO_CTWEND_8822B BIT(27)
+#define BIT_SDIO_ATIMEND_E_8822B BIT(26)
+#define BIT_SDIO_ATIMEND_8822B BIT(25)
+#define BIT_SDIO_OCPINT_8822B BIT(24)
+#define BIT_SDIO_PSTIMEOUT_8822B BIT(23)
+#define BIT_SDIO_GTINT4_8822B BIT(22)
+#define BIT_SDIO_GTINT3_8822B BIT(21)
+#define BIT_SDIO_HSISR_IND_8822B BIT(20)
+#define BIT_SDIO_CPWM2_8822B BIT(19)
+#define BIT_SDIO_CPWM1_8822B BIT(18)
+#define BIT_SDIO_C2HCMD_INT_8822B BIT(17)
+#define BIT_SDIO_BCNERLY_INT_8822B BIT(16)
+#define BIT_SDIO_TXBCNERR_8822B BIT(7)
+#define BIT_SDIO_TXBCNOK_8822B BIT(6)
+#define BIT_SDIO_RXFOVW_8822B BIT(5)
+#define BIT_SDIO_TXFOVW_8822B BIT(4)
+#define BIT_SDIO_RXERR_8822B BIT(3)
+#define BIT_SDIO_TXERR_8822B BIT(2)
+#define BIT_SDIO_AVAL_8822B BIT(1)
+#define BIT_RX_REQUEST_8822B BIT(0)
+
+/* 2 REG_SDIO_RX_REQ_LEN_8822B */
+
+#define BIT_SHIFT_RX_REQ_LEN_V1_8822B 0
+#define BIT_MASK_RX_REQ_LEN_V1_8822B 0x3ffff
+#define BIT_RX_REQ_LEN_V1_8822B(x)                                             \
+	(((x) & BIT_MASK_RX_REQ_LEN_V1_8822B) << BIT_SHIFT_RX_REQ_LEN_V1_8822B)
+#define BITS_RX_REQ_LEN_V1_8822B                                               \
+	(BIT_MASK_RX_REQ_LEN_V1_8822B << BIT_SHIFT_RX_REQ_LEN_V1_8822B)
+#define BIT_CLEAR_RX_REQ_LEN_V1_8822B(x) ((x) & (~BITS_RX_REQ_LEN_V1_8822B))
+#define BIT_GET_RX_REQ_LEN_V1_8822B(x)                                         \
+	(((x) >> BIT_SHIFT_RX_REQ_LEN_V1_8822B) & BIT_MASK_RX_REQ_LEN_V1_8822B)
+#define BIT_SET_RX_REQ_LEN_V1_8822B(x, v)                                      \
+	(BIT_CLEAR_RX_REQ_LEN_V1_8822B(x) | BIT_RX_REQ_LEN_V1_8822B(v))
+
+/* 2 REG_SDIO_FREE_TXPG_SEQ_V1_8822B */
+
+#define BIT_SHIFT_FREE_TXPG_SEQ_8822B 0
+#define BIT_MASK_FREE_TXPG_SEQ_8822B 0xff
+#define BIT_FREE_TXPG_SEQ_8822B(x)                                             \
+	(((x) & BIT_MASK_FREE_TXPG_SEQ_8822B) << BIT_SHIFT_FREE_TXPG_SEQ_8822B)
+#define BITS_FREE_TXPG_SEQ_8822B                                               \
+	(BIT_MASK_FREE_TXPG_SEQ_8822B << BIT_SHIFT_FREE_TXPG_SEQ_8822B)
+#define BIT_CLEAR_FREE_TXPG_SEQ_8822B(x) ((x) & (~BITS_FREE_TXPG_SEQ_8822B))
+#define BIT_GET_FREE_TXPG_SEQ_8822B(x)                                         \
+	(((x) >> BIT_SHIFT_FREE_TXPG_SEQ_8822B) & BIT_MASK_FREE_TXPG_SEQ_8822B)
+#define BIT_SET_FREE_TXPG_SEQ_8822B(x, v)                                      \
+	(BIT_CLEAR_FREE_TXPG_SEQ_8822B(x) | BIT_FREE_TXPG_SEQ_8822B(v))
+
+/* 2 REG_SDIO_FREE_TXPG_8822B */
+
+#define BIT_SHIFT_MID_FREEPG_V1_8822B 16
+#define BIT_MASK_MID_FREEPG_V1_8822B 0xfff
+#define BIT_MID_FREEPG_V1_8822B(x)                                             \
+	(((x) & BIT_MASK_MID_FREEPG_V1_8822B) << BIT_SHIFT_MID_FREEPG_V1_8822B)
+#define BITS_MID_FREEPG_V1_8822B                                               \
+	(BIT_MASK_MID_FREEPG_V1_8822B << BIT_SHIFT_MID_FREEPG_V1_8822B)
+#define BIT_CLEAR_MID_FREEPG_V1_8822B(x) ((x) & (~BITS_MID_FREEPG_V1_8822B))
+#define BIT_GET_MID_FREEPG_V1_8822B(x)                                         \
+	(((x) >> BIT_SHIFT_MID_FREEPG_V1_8822B) & BIT_MASK_MID_FREEPG_V1_8822B)
+#define BIT_SET_MID_FREEPG_V1_8822B(x, v)                                      \
+	(BIT_CLEAR_MID_FREEPG_V1_8822B(x) | BIT_MID_FREEPG_V1_8822B(v))
+
+#define BIT_SHIFT_HIQ_FREEPG_V1_8822B 0
+#define BIT_MASK_HIQ_FREEPG_V1_8822B 0xfff
+#define BIT_HIQ_FREEPG_V1_8822B(x)                                             \
+	(((x) & BIT_MASK_HIQ_FREEPG_V1_8822B) << BIT_SHIFT_HIQ_FREEPG_V1_8822B)
+#define BITS_HIQ_FREEPG_V1_8822B                                               \
+	(BIT_MASK_HIQ_FREEPG_V1_8822B << BIT_SHIFT_HIQ_FREEPG_V1_8822B)
+#define BIT_CLEAR_HIQ_FREEPG_V1_8822B(x) ((x) & (~BITS_HIQ_FREEPG_V1_8822B))
+#define BIT_GET_HIQ_FREEPG_V1_8822B(x)                                         \
+	(((x) >> BIT_SHIFT_HIQ_FREEPG_V1_8822B) & BIT_MASK_HIQ_FREEPG_V1_8822B)
+#define BIT_SET_HIQ_FREEPG_V1_8822B(x, v)                                      \
+	(BIT_CLEAR_HIQ_FREEPG_V1_8822B(x) | BIT_HIQ_FREEPG_V1_8822B(v))
+
+/* 2 REG_SDIO_FREE_TXPG2_8822B */
+
+#define BIT_SHIFT_PUB_FREEPG_V1_8822B 16
+#define BIT_MASK_PUB_FREEPG_V1_8822B 0xfff
+#define BIT_PUB_FREEPG_V1_8822B(x)                                             \
+	(((x) & BIT_MASK_PUB_FREEPG_V1_8822B) << BIT_SHIFT_PUB_FREEPG_V1_8822B)
+#define BITS_PUB_FREEPG_V1_8822B                                               \
+	(BIT_MASK_PUB_FREEPG_V1_8822B << BIT_SHIFT_PUB_FREEPG_V1_8822B)
+#define BIT_CLEAR_PUB_FREEPG_V1_8822B(x) ((x) & (~BITS_PUB_FREEPG_V1_8822B))
+#define BIT_GET_PUB_FREEPG_V1_8822B(x)                                         \
+	(((x) >> BIT_SHIFT_PUB_FREEPG_V1_8822B) & BIT_MASK_PUB_FREEPG_V1_8822B)
+#define BIT_SET_PUB_FREEPG_V1_8822B(x, v)                                      \
+	(BIT_CLEAR_PUB_FREEPG_V1_8822B(x) | BIT_PUB_FREEPG_V1_8822B(v))
+
+#define BIT_SHIFT_LOW_FREEPG_V1_8822B 0
+#define BIT_MASK_LOW_FREEPG_V1_8822B 0xfff
+#define BIT_LOW_FREEPG_V1_8822B(x)                                             \
+	(((x) & BIT_MASK_LOW_FREEPG_V1_8822B) << BIT_SHIFT_LOW_FREEPG_V1_8822B)
+#define BITS_LOW_FREEPG_V1_8822B                                               \
+	(BIT_MASK_LOW_FREEPG_V1_8822B << BIT_SHIFT_LOW_FREEPG_V1_8822B)
+#define BIT_CLEAR_LOW_FREEPG_V1_8822B(x) ((x) & (~BITS_LOW_FREEPG_V1_8822B))
+#define BIT_GET_LOW_FREEPG_V1_8822B(x)                                         \
+	(((x) >> BIT_SHIFT_LOW_FREEPG_V1_8822B) & BIT_MASK_LOW_FREEPG_V1_8822B)
+#define BIT_SET_LOW_FREEPG_V1_8822B(x, v)                                      \
+	(BIT_CLEAR_LOW_FREEPG_V1_8822B(x) | BIT_LOW_FREEPG_V1_8822B(v))
+
+/* 2 REG_SDIO_OQT_FREE_TXPG_V1_8822B */
+
+#define BIT_SHIFT_NOAC_OQT_FREEPG_V1_8822B 24
+#define BIT_MASK_NOAC_OQT_FREEPG_V1_8822B 0xff
+#define BIT_NOAC_OQT_FREEPG_V1_8822B(x)                                        \
+	(((x) & BIT_MASK_NOAC_OQT_FREEPG_V1_8822B)                             \
+	 << BIT_SHIFT_NOAC_OQT_FREEPG_V1_8822B)
+#define BITS_NOAC_OQT_FREEPG_V1_8822B                                          \
+	(BIT_MASK_NOAC_OQT_FREEPG_V1_8822B                                     \
+	 << BIT_SHIFT_NOAC_OQT_FREEPG_V1_8822B)
+#define BIT_CLEAR_NOAC_OQT_FREEPG_V1_8822B(x)                                  \
+	((x) & (~BITS_NOAC_OQT_FREEPG_V1_8822B))
+#define BIT_GET_NOAC_OQT_FREEPG_V1_8822B(x)                                    \
+	(((x) >> BIT_SHIFT_NOAC_OQT_FREEPG_V1_8822B) &                         \
+	 BIT_MASK_NOAC_OQT_FREEPG_V1_8822B)
+#define BIT_SET_NOAC_OQT_FREEPG_V1_8822B(x, v)                                 \
+	(BIT_CLEAR_NOAC_OQT_FREEPG_V1_8822B(x) |                               \
+	 BIT_NOAC_OQT_FREEPG_V1_8822B(v))
+
+#define BIT_SHIFT_AC_OQT_FREEPG_V1_8822B 16
+#define BIT_MASK_AC_OQT_FREEPG_V1_8822B 0xff
+#define BIT_AC_OQT_FREEPG_V1_8822B(x)                                          \
+	(((x) & BIT_MASK_AC_OQT_FREEPG_V1_8822B)                               \
+	 << BIT_SHIFT_AC_OQT_FREEPG_V1_8822B)
+#define BITS_AC_OQT_FREEPG_V1_8822B                                            \
+	(BIT_MASK_AC_OQT_FREEPG_V1_8822B << BIT_SHIFT_AC_OQT_FREEPG_V1_8822B)
+#define BIT_CLEAR_AC_OQT_FREEPG_V1_8822B(x)                                    \
+	((x) & (~BITS_AC_OQT_FREEPG_V1_8822B))
+#define BIT_GET_AC_OQT_FREEPG_V1_8822B(x)                                      \
+	(((x) >> BIT_SHIFT_AC_OQT_FREEPG_V1_8822B) &                           \
+	 BIT_MASK_AC_OQT_FREEPG_V1_8822B)
+#define BIT_SET_AC_OQT_FREEPG_V1_8822B(x, v)                                   \
+	(BIT_CLEAR_AC_OQT_FREEPG_V1_8822B(x) | BIT_AC_OQT_FREEPG_V1_8822B(v))
+
+#define BIT_SHIFT_EXQ_FREEPG_V1_8822B 0
+#define BIT_MASK_EXQ_FREEPG_V1_8822B 0xfff
+#define BIT_EXQ_FREEPG_V1_8822B(x)                                             \
+	(((x) & BIT_MASK_EXQ_FREEPG_V1_8822B) << BIT_SHIFT_EXQ_FREEPG_V1_8822B)
+#define BITS_EXQ_FREEPG_V1_8822B                                               \
+	(BIT_MASK_EXQ_FREEPG_V1_8822B << BIT_SHIFT_EXQ_FREEPG_V1_8822B)
+#define BIT_CLEAR_EXQ_FREEPG_V1_8822B(x) ((x) & (~BITS_EXQ_FREEPG_V1_8822B))
+#define BIT_GET_EXQ_FREEPG_V1_8822B(x)                                         \
+	(((x) >> BIT_SHIFT_EXQ_FREEPG_V1_8822B) & BIT_MASK_EXQ_FREEPG_V1_8822B)
+#define BIT_SET_EXQ_FREEPG_V1_8822B(x, v)                                      \
+	(BIT_CLEAR_EXQ_FREEPG_V1_8822B(x) | BIT_EXQ_FREEPG_V1_8822B(v))
+
+/* 2 REG_SDIO_HTSFR_INFO_8822B */
+
+#define BIT_SHIFT_HTSFR1_8822B 16
+#define BIT_MASK_HTSFR1_8822B 0xffff
+#define BIT_HTSFR1_8822B(x)                                                    \
+	(((x) & BIT_MASK_HTSFR1_8822B) << BIT_SHIFT_HTSFR1_8822B)
+#define BITS_HTSFR1_8822B (BIT_MASK_HTSFR1_8822B << BIT_SHIFT_HTSFR1_8822B)
+#define BIT_CLEAR_HTSFR1_8822B(x) ((x) & (~BITS_HTSFR1_8822B))
+#define BIT_GET_HTSFR1_8822B(x)                                                \
+	(((x) >> BIT_SHIFT_HTSFR1_8822B) & BIT_MASK_HTSFR1_8822B)
+#define BIT_SET_HTSFR1_8822B(x, v)                                             \
+	(BIT_CLEAR_HTSFR1_8822B(x) | BIT_HTSFR1_8822B(v))
+
+#define BIT_SHIFT_HTSFR0_8822B 0
+#define BIT_MASK_HTSFR0_8822B 0xffff
+#define BIT_HTSFR0_8822B(x)                                                    \
+	(((x) & BIT_MASK_HTSFR0_8822B) << BIT_SHIFT_HTSFR0_8822B)
+#define BITS_HTSFR0_8822B (BIT_MASK_HTSFR0_8822B << BIT_SHIFT_HTSFR0_8822B)
+#define BIT_CLEAR_HTSFR0_8822B(x) ((x) & (~BITS_HTSFR0_8822B))
+#define BIT_GET_HTSFR0_8822B(x)                                                \
+	(((x) >> BIT_SHIFT_HTSFR0_8822B) & BIT_MASK_HTSFR0_8822B)
+#define BIT_SET_HTSFR0_8822B(x, v)                                             \
+	(BIT_CLEAR_HTSFR0_8822B(x) | BIT_HTSFR0_8822B(v))
+
+/* 2 REG_SDIO_HCPWM1_V2_8822B */
+#define BIT_TOGGLE_8822B BIT(7)
+#define BIT_CUR_PS_8822B BIT(0)
+
+/* 2 REG_SDIO_HCPWM2_V2_8822B */
+
+/* 2 REG_SDIO_INDIRECT_REG_CFG_8822B */
+#define BIT_INDIRECT_REG_RDY_8822B BIT(20)
+#define BIT_INDIRECT_REG_R_8822B BIT(19)
+#define BIT_INDIRECT_REG_W_8822B BIT(18)
+
+#define BIT_SHIFT_INDIRECT_REG_SIZE_8822B 16
+#define BIT_MASK_INDIRECT_REG_SIZE_8822B 0x3
+#define BIT_INDIRECT_REG_SIZE_8822B(x)                                         \
+	(((x) & BIT_MASK_INDIRECT_REG_SIZE_8822B)                              \
+	 << BIT_SHIFT_INDIRECT_REG_SIZE_8822B)
+#define BITS_INDIRECT_REG_SIZE_8822B                                           \
+	(BIT_MASK_INDIRECT_REG_SIZE_8822B << BIT_SHIFT_INDIRECT_REG_SIZE_8822B)
+#define BIT_CLEAR_INDIRECT_REG_SIZE_8822B(x)                                   \
+	((x) & (~BITS_INDIRECT_REG_SIZE_8822B))
+#define BIT_GET_INDIRECT_REG_SIZE_8822B(x)                                     \
+	(((x) >> BIT_SHIFT_INDIRECT_REG_SIZE_8822B) &                          \
+	 BIT_MASK_INDIRECT_REG_SIZE_8822B)
+#define BIT_SET_INDIRECT_REG_SIZE_8822B(x, v)                                  \
+	(BIT_CLEAR_INDIRECT_REG_SIZE_8822B(x) | BIT_INDIRECT_REG_SIZE_8822B(v))
+
+#define BIT_SHIFT_INDIRECT_REG_ADDR_8822B 0
+#define BIT_MASK_INDIRECT_REG_ADDR_8822B 0xffff
+#define BIT_INDIRECT_REG_ADDR_8822B(x)                                         \
+	(((x) & BIT_MASK_INDIRECT_REG_ADDR_8822B)                              \
+	 << BIT_SHIFT_INDIRECT_REG_ADDR_8822B)
+#define BITS_INDIRECT_REG_ADDR_8822B                                           \
+	(BIT_MASK_INDIRECT_REG_ADDR_8822B << BIT_SHIFT_INDIRECT_REG_ADDR_8822B)
+#define BIT_CLEAR_INDIRECT_REG_ADDR_8822B(x)                                   \
+	((x) & (~BITS_INDIRECT_REG_ADDR_8822B))
+#define BIT_GET_INDIRECT_REG_ADDR_8822B(x)                                     \
+	(((x) >> BIT_SHIFT_INDIRECT_REG_ADDR_8822B) &                          \
+	 BIT_MASK_INDIRECT_REG_ADDR_8822B)
+#define BIT_SET_INDIRECT_REG_ADDR_8822B(x, v)                                  \
+	(BIT_CLEAR_INDIRECT_REG_ADDR_8822B(x) | BIT_INDIRECT_REG_ADDR_8822B(v))
+
+/* 2 REG_SDIO_INDIRECT_REG_DATA_8822B */
+
+#define BIT_SHIFT_INDIRECT_REG_DATA_8822B 0
+#define BIT_MASK_INDIRECT_REG_DATA_8822B 0xffffffffL
+#define BIT_INDIRECT_REG_DATA_8822B(x)                                         \
+	(((x) & BIT_MASK_INDIRECT_REG_DATA_8822B)                              \
+	 << BIT_SHIFT_INDIRECT_REG_DATA_8822B)
+#define BITS_INDIRECT_REG_DATA_8822B                                           \
+	(BIT_MASK_INDIRECT_REG_DATA_8822B << BIT_SHIFT_INDIRECT_REG_DATA_8822B)
+#define BIT_CLEAR_INDIRECT_REG_DATA_8822B(x)                                   \
+	((x) & (~BITS_INDIRECT_REG_DATA_8822B))
+#define BIT_GET_INDIRECT_REG_DATA_8822B(x)                                     \
+	(((x) >> BIT_SHIFT_INDIRECT_REG_DATA_8822B) &                          \
+	 BIT_MASK_INDIRECT_REG_DATA_8822B)
+#define BIT_SET_INDIRECT_REG_DATA_8822B(x, v)                                  \
+	(BIT_CLEAR_INDIRECT_REG_DATA_8822B(x) | BIT_INDIRECT_REG_DATA_8822B(v))
+
+/* 2 REG_SDIO_H2C_8822B */
+
+#define BIT_SHIFT_SDIO_H2C_MSG_8822B 0
+#define BIT_MASK_SDIO_H2C_MSG_8822B 0xffffffffL
+#define BIT_SDIO_H2C_MSG_8822B(x)                                              \
+	(((x) & BIT_MASK_SDIO_H2C_MSG_8822B) << BIT_SHIFT_SDIO_H2C_MSG_8822B)
+#define BITS_SDIO_H2C_MSG_8822B                                                \
+	(BIT_MASK_SDIO_H2C_MSG_8822B << BIT_SHIFT_SDIO_H2C_MSG_8822B)
+#define BIT_CLEAR_SDIO_H2C_MSG_8822B(x) ((x) & (~BITS_SDIO_H2C_MSG_8822B))
+#define BIT_GET_SDIO_H2C_MSG_8822B(x)                                          \
+	(((x) >> BIT_SHIFT_SDIO_H2C_MSG_8822B) & BIT_MASK_SDIO_H2C_MSG_8822B)
+#define BIT_SET_SDIO_H2C_MSG_8822B(x, v)                                       \
+	(BIT_CLEAR_SDIO_H2C_MSG_8822B(x) | BIT_SDIO_H2C_MSG_8822B(v))
+
+/* 2 REG_SDIO_C2H_8822B */
+
+#define BIT_SHIFT_SDIO_C2H_MSG_8822B 0
+#define BIT_MASK_SDIO_C2H_MSG_8822B 0xffffffffL
+#define BIT_SDIO_C2H_MSG_8822B(x)                                              \
+	(((x) & BIT_MASK_SDIO_C2H_MSG_8822B) << BIT_SHIFT_SDIO_C2H_MSG_8822B)
+#define BITS_SDIO_C2H_MSG_8822B                                                \
+	(BIT_MASK_SDIO_C2H_MSG_8822B << BIT_SHIFT_SDIO_C2H_MSG_8822B)
+#define BIT_CLEAR_SDIO_C2H_MSG_8822B(x) ((x) & (~BITS_SDIO_C2H_MSG_8822B))
+#define BIT_GET_SDIO_C2H_MSG_8822B(x)                                          \
+	(((x) >> BIT_SHIFT_SDIO_C2H_MSG_8822B) & BIT_MASK_SDIO_C2H_MSG_8822B)
+#define BIT_SET_SDIO_C2H_MSG_8822B(x, v)                                       \
+	(BIT_CLEAR_SDIO_C2H_MSG_8822B(x) | BIT_SDIO_C2H_MSG_8822B(v))
+
+/* 2 REG_SDIO_HRPWM1_8822B */
+#define BIT_TOGGLE_8822B BIT(7)
+#define BIT_ACK_8822B BIT(6)
+#define BIT_REQ_PS_8822B BIT(0)
+
+/* 2 REG_SDIO_HRPWM2_8822B */
+
+/* 2 REG_SDIO_HPS_CLKR_8822B */
+
+/* 2 REG_SDIO_BUS_CTRL_8822B */
+#define BIT_PAD_CLK_XHGE_EN_8822B BIT(3)
+#define BIT_INTER_CLK_EN_8822B BIT(2)
+#define BIT_EN_RPT_TXCRC_8822B BIT(1)
+#define BIT_DIS_RXDMA_STS_8822B BIT(0)
+
+/* 2 REG_SDIO_HSUS_CTRL_8822B */
+#define BIT_INTR_CTRL_8822B BIT(4)
+#define BIT_SDIO_VOLTAGE_8822B BIT(3)
+#define BIT_BYPASS_INIT_8822B BIT(2)
+#define BIT_HCI_RESUME_RDY_8822B BIT(1)
+#define BIT_HCI_SUS_REQ_8822B BIT(0)
+
+/* 2 REG_SDIO_RESPONSE_TIMER_8822B */
+
+#define BIT_SHIFT_CMDIN_2RESP_TIMER_8822B 0
+#define BIT_MASK_CMDIN_2RESP_TIMER_8822B 0xffff
+#define BIT_CMDIN_2RESP_TIMER_8822B(x)                                         \
+	(((x) & BIT_MASK_CMDIN_2RESP_TIMER_8822B)                              \
+	 << BIT_SHIFT_CMDIN_2RESP_TIMER_8822B)
+#define BITS_CMDIN_2RESP_TIMER_8822B                                           \
+	(BIT_MASK_CMDIN_2RESP_TIMER_8822B << BIT_SHIFT_CMDIN_2RESP_TIMER_8822B)
+#define BIT_CLEAR_CMDIN_2RESP_TIMER_8822B(x)                                   \
+	((x) & (~BITS_CMDIN_2RESP_TIMER_8822B))
+#define BIT_GET_CMDIN_2RESP_TIMER_8822B(x)                                     \
+	(((x) >> BIT_SHIFT_CMDIN_2RESP_TIMER_8822B) &                          \
+	 BIT_MASK_CMDIN_2RESP_TIMER_8822B)
+#define BIT_SET_CMDIN_2RESP_TIMER_8822B(x, v)                                  \
+	(BIT_CLEAR_CMDIN_2RESP_TIMER_8822B(x) | BIT_CMDIN_2RESP_TIMER_8822B(v))
+
+/* 2 REG_SDIO_CMD_CRC_8822B */
+
+#define BIT_SHIFT_SDIO_CMD_CRC_V1_8822B 0
+#define BIT_MASK_SDIO_CMD_CRC_V1_8822B 0xff
+#define BIT_SDIO_CMD_CRC_V1_8822B(x)                                           \
+	(((x) & BIT_MASK_SDIO_CMD_CRC_V1_8822B)                                \
+	 << BIT_SHIFT_SDIO_CMD_CRC_V1_8822B)
+#define BITS_SDIO_CMD_CRC_V1_8822B                                             \
+	(BIT_MASK_SDIO_CMD_CRC_V1_8822B << BIT_SHIFT_SDIO_CMD_CRC_V1_8822B)
+#define BIT_CLEAR_SDIO_CMD_CRC_V1_8822B(x) ((x) & (~BITS_SDIO_CMD_CRC_V1_8822B))
+#define BIT_GET_SDIO_CMD_CRC_V1_8822B(x)                                       \
+	(((x) >> BIT_SHIFT_SDIO_CMD_CRC_V1_8822B) &                            \
+	 BIT_MASK_SDIO_CMD_CRC_V1_8822B)
+#define BIT_SET_SDIO_CMD_CRC_V1_8822B(x, v)                                    \
+	(BIT_CLEAR_SDIO_CMD_CRC_V1_8822B(x) | BIT_SDIO_CMD_CRC_V1_8822B(v))
+
+/* 2 REG_SDIO_HSISR_8822B */
+#define BIT_DRV_WLAN_INT_CLR_8822B BIT(1)
+#define BIT_DRV_WLAN_INT_8822B BIT(0)
+
+/* 2 REG_SDIO_ERR_RPT_8822B */
+#define BIT_HR_FF_OVF_8822B BIT(6)
+#define BIT_HR_FF_UDN_8822B BIT(5)
+#define BIT_TXDMA_BUSY_ERR_8822B BIT(4)
+#define BIT_TXDMA_VLD_ERR_8822B BIT(3)
+#define BIT_QSEL_UNKNOWN_ERR_8822B BIT(2)
+#define BIT_QSEL_MIS_ERR_8822B BIT(1)
+#define BIT_SDIO_OVERRD_ERR_8822B BIT(0)
+
+/* 2 REG_SDIO_CMD_ERRCNT_8822B */
+
+#define BIT_SHIFT_CMD_CRC_ERR_CNT_8822B 0
+#define BIT_MASK_CMD_CRC_ERR_CNT_8822B 0xff
+#define BIT_CMD_CRC_ERR_CNT_8822B(x)                                           \
+	(((x) & BIT_MASK_CMD_CRC_ERR_CNT_8822B)                                \
+	 << BIT_SHIFT_CMD_CRC_ERR_CNT_8822B)
+#define BITS_CMD_CRC_ERR_CNT_8822B                                             \
+	(BIT_MASK_CMD_CRC_ERR_CNT_8822B << BIT_SHIFT_CMD_CRC_ERR_CNT_8822B)
+#define BIT_CLEAR_CMD_CRC_ERR_CNT_8822B(x) ((x) & (~BITS_CMD_CRC_ERR_CNT_8822B))
+#define BIT_GET_CMD_CRC_ERR_CNT_8822B(x)                                       \
+	(((x) >> BIT_SHIFT_CMD_CRC_ERR_CNT_8822B) &                            \
+	 BIT_MASK_CMD_CRC_ERR_CNT_8822B)
+#define BIT_SET_CMD_CRC_ERR_CNT_8822B(x, v)                                    \
+	(BIT_CLEAR_CMD_CRC_ERR_CNT_8822B(x) | BIT_CMD_CRC_ERR_CNT_8822B(v))
+
+/* 2 REG_SDIO_DATA_ERRCNT_8822B */
+
+#define BIT_SHIFT_DATA_CRC_ERR_CNT_8822B 0
+#define BIT_MASK_DATA_CRC_ERR_CNT_8822B 0xff
+#define BIT_DATA_CRC_ERR_CNT_8822B(x)                                          \
+	(((x) & BIT_MASK_DATA_CRC_ERR_CNT_8822B)                               \
+	 << BIT_SHIFT_DATA_CRC_ERR_CNT_8822B)
+#define BITS_DATA_CRC_ERR_CNT_8822B                                            \
+	(BIT_MASK_DATA_CRC_ERR_CNT_8822B << BIT_SHIFT_DATA_CRC_ERR_CNT_8822B)
+#define BIT_CLEAR_DATA_CRC_ERR_CNT_8822B(x)                                    \
+	((x) & (~BITS_DATA_CRC_ERR_CNT_8822B))
+#define BIT_GET_DATA_CRC_ERR_CNT_8822B(x)                                      \
+	(((x) >> BIT_SHIFT_DATA_CRC_ERR_CNT_8822B) &                           \
+	 BIT_MASK_DATA_CRC_ERR_CNT_8822B)
+#define BIT_SET_DATA_CRC_ERR_CNT_8822B(x, v)                                   \
+	(BIT_CLEAR_DATA_CRC_ERR_CNT_8822B(x) | BIT_DATA_CRC_ERR_CNT_8822B(v))
+
+/* 2 REG_SDIO_CMD_ERR_CONTENT_8822B */
+
+#define BIT_SHIFT_SDIO_CMD_ERR_CONTENT_8822B 0
+#define BIT_MASK_SDIO_CMD_ERR_CONTENT_8822B 0xffffffffffL
+#define BIT_SDIO_CMD_ERR_CONTENT_8822B(x)                                      \
+	(((x) & BIT_MASK_SDIO_CMD_ERR_CONTENT_8822B)                           \
+	 << BIT_SHIFT_SDIO_CMD_ERR_CONTENT_8822B)
+#define BITS_SDIO_CMD_ERR_CONTENT_8822B                                        \
+	(BIT_MASK_SDIO_CMD_ERR_CONTENT_8822B                                   \
+	 << BIT_SHIFT_SDIO_CMD_ERR_CONTENT_8822B)
+#define BIT_CLEAR_SDIO_CMD_ERR_CONTENT_8822B(x)                                \
+	((x) & (~BITS_SDIO_CMD_ERR_CONTENT_8822B))
+#define BIT_GET_SDIO_CMD_ERR_CONTENT_8822B(x)                                  \
+	(((x) >> BIT_SHIFT_SDIO_CMD_ERR_CONTENT_8822B) &                       \
+	 BIT_MASK_SDIO_CMD_ERR_CONTENT_8822B)
+#define BIT_SET_SDIO_CMD_ERR_CONTENT_8822B(x, v)                               \
+	(BIT_CLEAR_SDIO_CMD_ERR_CONTENT_8822B(x) |                             \
+	 BIT_SDIO_CMD_ERR_CONTENT_8822B(v))
+
+/* 2 REG_SDIO_CRC_ERR_IDX_8822B */
+#define BIT_D3_CRC_ERR_8822B BIT(4)
+#define BIT_D2_CRC_ERR_8822B BIT(3)
+#define BIT_D1_CRC_ERR_8822B BIT(2)
+#define BIT_D0_CRC_ERR_8822B BIT(1)
+#define BIT_CMD_CRC_ERR_8822B BIT(0)
+
+/* 2 REG_SDIO_DATA_CRC_8822B */
+
+#define BIT_SHIFT_SDIO_DATA_CRC_8822B 0
+#define BIT_MASK_SDIO_DATA_CRC_8822B 0xffff
+#define BIT_SDIO_DATA_CRC_8822B(x)                                             \
+	(((x) & BIT_MASK_SDIO_DATA_CRC_8822B) << BIT_SHIFT_SDIO_DATA_CRC_8822B)
+#define BITS_SDIO_DATA_CRC_8822B                                               \
+	(BIT_MASK_SDIO_DATA_CRC_8822B << BIT_SHIFT_SDIO_DATA_CRC_8822B)
+#define BIT_CLEAR_SDIO_DATA_CRC_8822B(x) ((x) & (~BITS_SDIO_DATA_CRC_8822B))
+#define BIT_GET_SDIO_DATA_CRC_8822B(x)                                         \
+	(((x) >> BIT_SHIFT_SDIO_DATA_CRC_8822B) & BIT_MASK_SDIO_DATA_CRC_8822B)
+#define BIT_SET_SDIO_DATA_CRC_8822B(x, v)                                      \
+	(BIT_CLEAR_SDIO_DATA_CRC_8822B(x) | BIT_SDIO_DATA_CRC_8822B(v))
+
+/* 2 REG_SDIO_DATA_REPLY_TIME_8822B */
+
+#define BIT_SHIFT_SDIO_DATA_REPLY_TIME_8822B 0
+#define BIT_MASK_SDIO_DATA_REPLY_TIME_8822B 0x7
+#define BIT_SDIO_DATA_REPLY_TIME_8822B(x)                                      \
+	(((x) & BIT_MASK_SDIO_DATA_REPLY_TIME_8822B)                           \
+	 << BIT_SHIFT_SDIO_DATA_REPLY_TIME_8822B)
+#define BITS_SDIO_DATA_REPLY_TIME_8822B                                        \
+	(BIT_MASK_SDIO_DATA_REPLY_TIME_8822B                                   \
+	 << BIT_SHIFT_SDIO_DATA_REPLY_TIME_8822B)
+#define BIT_CLEAR_SDIO_DATA_REPLY_TIME_8822B(x)                                \
+	((x) & (~BITS_SDIO_DATA_REPLY_TIME_8822B))
+#define BIT_GET_SDIO_DATA_REPLY_TIME_8822B(x)                                  \
+	(((x) >> BIT_SHIFT_SDIO_DATA_REPLY_TIME_8822B) &                       \
+	 BIT_MASK_SDIO_DATA_REPLY_TIME_8822B)
+#define BIT_SET_SDIO_DATA_REPLY_TIME_8822B(x, v)                               \
+	(BIT_CLEAR_SDIO_DATA_REPLY_TIME_8822B(x) |                             \
+	 BIT_SDIO_DATA_REPLY_TIME_8822B(v))
+
+#endif
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/halmac/halmac_bit_8822c.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/halmac/halmac_bit_8822c.h
--- linux-5.6.3/3rdparty/rtl8821ce/hal/halmac/halmac_bit_8822c.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/halmac/halmac_bit_8822c.h	2020-04-10 16:35:06.811659835 +0300
@@ -0,0 +1,21838 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2017 - 2018 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ ******************************************************************************/
+
+#ifndef __INC_HALMAC_BIT_8822C_H
+#define __INC_HALMAC_BIT_8822C_H
+
+#define CPU_OPT_WIDTH 0x1F
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_SYS_ISO_CTRL_8822C */
+#define BIT_PWC_EV12V_8822C BIT(15)
+
+/* 2 REG_NOT_VALID_8822C */
+#define BIT_PA33V_EN_8822C BIT(13)
+#define BIT_PA12V_EN_8822C BIT(12)
+#define BIT_UA33V_EN_8822C BIT(11)
+#define BIT_UA12V_EN_8822C BIT(10)
+#define BIT_ISO_RFDIO_8822C BIT(9)
+#define BIT_ISO_EB2CORE_8822C BIT(8)
+#define BIT_ISO_DIOE_8822C BIT(7)
+#define BIT_ISO_WLPON2PP_8822C BIT(6)
+#define BIT_ISO_IP2MAC_WA2PP_8822C BIT(5)
+#define BIT_ISO_PD2CORE_8822C BIT(4)
+#define BIT_ISO_PA2PCIE_8822C BIT(3)
+#define BIT_ISO_UD2CORE_8822C BIT(2)
+#define BIT_ISO_UA2USB_8822C BIT(1)
+#define BIT_ISO_WD2PP_8822C BIT(0)
+
+/* 2 REG_SYS_FUNC_EN_8822C */
+#define BIT_FEN_MREGEN_8822C BIT(15)
+#define BIT_FEN_HWPDN_8822C BIT(14)
+
+/* 2 REG_NOT_VALID_8822C */
+#define BIT_FEN_ELDR_8822C BIT(12)
+#define BIT_FEN_DCORE_8822C BIT(11)
+#define BIT_FEN_CPUEN_8822C BIT(10)
+#define BIT_FEN_DIOE_8822C BIT(9)
+#define BIT_FEN_PCIED_8822C BIT(8)
+#define BIT_FEN_PPLL_8822C BIT(7)
+#define BIT_FEN_PCIEA_8822C BIT(6)
+#define BIT_FEN_DIO_PCIE_8822C BIT(5)
+#define BIT_FEN_USBD_8822C BIT(4)
+#define BIT_FEN_UPLL_8822C BIT(3)
+#define BIT_FEN_USBA_8822C BIT(2)
+#define BIT_FEN_BB_GLB_RSTN_8822C BIT(1)
+#define BIT_FEN_BBRSTB_8822C BIT(0)
+
+/* 2 REG_SYS_PW_CTRL_8822C */
+#define BIT_SOP_EABM_8822C BIT(31)
+#define BIT_SOP_ACKF_8822C BIT(30)
+#define BIT_SOP_ERCK_8822C BIT(29)
+#define BIT_SOP_ESWR_8822C BIT(28)
+#define BIT_SOP_PWMM_8822C BIT(27)
+#define BIT_SOP_EECK_8822C BIT(26)
+#define BIT_SOP_ANA_CLK_DIVISION_2_8822C BIT(25)
+#define BIT_SOP_EXTL_8822C BIT(24)
+#define BIT_SYM_OP_RING_12M_8822C BIT(22)
+#define BIT_ROP_SWPR_8822C BIT(21)
+#define BIT_DIS_HW_LPLDM_8822C BIT(20)
+#define BIT_OPT_SWRST_WLMCU_8822C BIT(19)
+#define BIT_RDY_SYSPWR_8822C BIT(17)
+#define BIT_EN_WLON_8822C BIT(16)
+#define BIT_APDM_HPDN_8822C BIT(15)
+#define BIT_AFSM_PCIE_SUS_EN_8822C BIT(12)
+#define BIT_AFSM_WLSUS_EN_8822C BIT(11)
+#define BIT_APFM_SWLPS_8822C BIT(10)
+#define BIT_APFM_OFFMAC_8822C BIT(9)
+#define BIT_APFN_ONMAC_8822C BIT(8)
+#define BIT_CHIP_PDN_EN_8822C BIT(7)
+#define BIT_RDY_MACDIS_8822C BIT(6)
+
+/* 2 REG_NOT_VALID_8822C */
+#define BIT_PFM_WOWL_8822C BIT(3)
+#define BIT_PFM_LDKP_8822C BIT(2)
+#define BIT_WL_HCI_ALD_8822C BIT(1)
+#define BIT_PFM_LDALL_8822C BIT(0)
+
+/* 2 REG_SYS_CLK_CTRL_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+#define BIT_CPU_CLK_EN_8822C BIT(14)
+#define BIT_SYMREG_CLK_EN_8822C BIT(13)
+#define BIT_HCI_CLK_EN_8822C BIT(12)
+#define BIT_MAC_CLK_EN_8822C BIT(11)
+#define BIT_SEC_CLK_EN_8822C BIT(10)
+#define BIT_PHY_SSC_RSTB_8822C BIT(9)
+#define BIT_EXT_32K_EN_8822C BIT(8)
+#define BIT_WL_CLK_TEST_8822C BIT(7)
+#define BIT_OP_SPS_PWM_EN_8822C BIT(6)
+#define BIT_LOADER_CLK_EN_8822C BIT(5)
+#define BIT_MACSLP_8822C BIT(4)
+#define BIT_WAKEPAD_EN_8822C BIT(3)
+#define BIT_ROMD16V_EN_8822C BIT(2)
+#define BIT_ANA_CLK_DIVISION_2_8822C BIT(1)
+#define BIT_CNTD16V_EN_8822C BIT(0)
+
+/* 2 REG_SYS_EEPROM_CTRL_8822C */
+
+#define BIT_SHIFT_VPDIDX_8822C 8
+#define BIT_MASK_VPDIDX_8822C 0xff
+#define BIT_VPDIDX_8822C(x)                                                    \
+	(((x) & BIT_MASK_VPDIDX_8822C) << BIT_SHIFT_VPDIDX_8822C)
+#define BITS_VPDIDX_8822C (BIT_MASK_VPDIDX_8822C << BIT_SHIFT_VPDIDX_8822C)
+#define BIT_CLEAR_VPDIDX_8822C(x) ((x) & (~BITS_VPDIDX_8822C))
+#define BIT_GET_VPDIDX_8822C(x)                                                \
+	(((x) >> BIT_SHIFT_VPDIDX_8822C) & BIT_MASK_VPDIDX_8822C)
+#define BIT_SET_VPDIDX_8822C(x, v)                                             \
+	(BIT_CLEAR_VPDIDX_8822C(x) | BIT_VPDIDX_8822C(v))
+
+#define BIT_SHIFT_EEM1_0_8822C 6
+#define BIT_MASK_EEM1_0_8822C 0x3
+#define BIT_EEM1_0_8822C(x)                                                    \
+	(((x) & BIT_MASK_EEM1_0_8822C) << BIT_SHIFT_EEM1_0_8822C)
+#define BITS_EEM1_0_8822C (BIT_MASK_EEM1_0_8822C << BIT_SHIFT_EEM1_0_8822C)
+#define BIT_CLEAR_EEM1_0_8822C(x) ((x) & (~BITS_EEM1_0_8822C))
+#define BIT_GET_EEM1_0_8822C(x)                                                \
+	(((x) >> BIT_SHIFT_EEM1_0_8822C) & BIT_MASK_EEM1_0_8822C)
+#define BIT_SET_EEM1_0_8822C(x, v)                                             \
+	(BIT_CLEAR_EEM1_0_8822C(x) | BIT_EEM1_0_8822C(v))
+
+#define BIT_AUTOLOAD_SUS_8822C BIT(5)
+#define BIT_EERPOMSEL_8822C BIT(4)
+#define BIT_EECS_V1_8822C BIT(3)
+#define BIT_EESK_V1_8822C BIT(2)
+#define BIT_EEDI_V1_8822C BIT(1)
+#define BIT_EEDO_V1_8822C BIT(0)
+
+/* 2 REG_EE_VPD_8822C */
+
+#define BIT_SHIFT_VPD_DATA_8822C 0
+#define BIT_MASK_VPD_DATA_8822C 0xffffffffL
+#define BIT_VPD_DATA_8822C(x)                                                  \
+	(((x) & BIT_MASK_VPD_DATA_8822C) << BIT_SHIFT_VPD_DATA_8822C)
+#define BITS_VPD_DATA_8822C                                                    \
+	(BIT_MASK_VPD_DATA_8822C << BIT_SHIFT_VPD_DATA_8822C)
+#define BIT_CLEAR_VPD_DATA_8822C(x) ((x) & (~BITS_VPD_DATA_8822C))
+#define BIT_GET_VPD_DATA_8822C(x)                                              \
+	(((x) >> BIT_SHIFT_VPD_DATA_8822C) & BIT_MASK_VPD_DATA_8822C)
+#define BIT_SET_VPD_DATA_8822C(x, v)                                           \
+	(BIT_CLEAR_VPD_DATA_8822C(x) | BIT_VPD_DATA_8822C(v))
+
+/* 2 REG_SYS_SWR_CTRL1_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+#define BIT_HW_AUTO_CTRL_EXT_SWR_8822C BIT(9)
+#define BIT_USE_INTERNAL_SWR_AND_LDO_8822C BIT(8)
+#define BIT_MAC_ID_EN_8822C BIT(7)
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_SYS_SWR_CTRL2_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+#define BIT_SW18_SEL_8822C BIT(13)
+
+/* 2 REG_NOT_VALID_8822C */
+#define BIT_SW18_SD_8822C BIT(10)
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_SYS_SWR_CTRL3_8822C */
+#define BIT_SPS18_OCP_DIS_8822C BIT(31)
+
+#define BIT_SHIFT_SPS18_OCP_TH_8822C 16
+#define BIT_MASK_SPS18_OCP_TH_8822C 0x7fff
+#define BIT_SPS18_OCP_TH_8822C(x)                                              \
+	(((x) & BIT_MASK_SPS18_OCP_TH_8822C) << BIT_SHIFT_SPS18_OCP_TH_8822C)
+#define BITS_SPS18_OCP_TH_8822C                                                \
+	(BIT_MASK_SPS18_OCP_TH_8822C << BIT_SHIFT_SPS18_OCP_TH_8822C)
+#define BIT_CLEAR_SPS18_OCP_TH_8822C(x) ((x) & (~BITS_SPS18_OCP_TH_8822C))
+#define BIT_GET_SPS18_OCP_TH_8822C(x)                                          \
+	(((x) >> BIT_SHIFT_SPS18_OCP_TH_8822C) & BIT_MASK_SPS18_OCP_TH_8822C)
+#define BIT_SET_SPS18_OCP_TH_8822C(x, v)                                       \
+	(BIT_CLEAR_SPS18_OCP_TH_8822C(x) | BIT_SPS18_OCP_TH_8822C(v))
+
+#define BIT_SHIFT_OCP_WINDOW_8822C 0
+#define BIT_MASK_OCP_WINDOW_8822C 0xffff
+#define BIT_OCP_WINDOW_8822C(x)                                                \
+	(((x) & BIT_MASK_OCP_WINDOW_8822C) << BIT_SHIFT_OCP_WINDOW_8822C)
+#define BITS_OCP_WINDOW_8822C                                                  \
+	(BIT_MASK_OCP_WINDOW_8822C << BIT_SHIFT_OCP_WINDOW_8822C)
+#define BIT_CLEAR_OCP_WINDOW_8822C(x) ((x) & (~BITS_OCP_WINDOW_8822C))
+#define BIT_GET_OCP_WINDOW_8822C(x)                                            \
+	(((x) >> BIT_SHIFT_OCP_WINDOW_8822C) & BIT_MASK_OCP_WINDOW_8822C)
+#define BIT_SET_OCP_WINDOW_8822C(x, v)                                         \
+	(BIT_CLEAR_OCP_WINDOW_8822C(x) | BIT_OCP_WINDOW_8822C(v))
+
+/* 2 REG_RSV_CTRL_8822C */
+#define BIT_HREG_DBG_8822C BIT(23)
+#define BIT_WLMCUIOIF_8822C BIT(8)
+#define BIT_LOCK_ALL_EN_8822C BIT(7)
+#define BIT_R_DIS_PRST_8822C BIT(6)
+#define BIT_WLOCK_1C_B6_8822C BIT(5)
+#define BIT_WLOCK_40_8822C BIT(4)
+#define BIT_WLOCK_08_8822C BIT(3)
+#define BIT_WLOCK_04_8822C BIT(2)
+#define BIT_WLOCK_00_8822C BIT(1)
+#define BIT_WLOCK_ALL_8822C BIT(0)
+
+/* 2 REG_RF_CTRL_8822C */
+#define BIT_RF_SDMRSTB_8822C BIT(2)
+#define BIT_RF_RSTB_8822C BIT(1)
+#define BIT_RF_EN_8822C BIT(0)
+
+/* 2 REG_AFE_LDO_CTRL_8822C */
+#define BIT_R_SYM_WLBBOFF1_P4_EN_8822C BIT(9)
+#define BIT_R_SYM_WLBBOFF1_P3_EN_8822C BIT(8)
+#define BIT_R_SYM_WLBBOFF1_P2_EN_8822C BIT(7)
+#define BIT_R_SYM_WLBBOFF1_P1_EN_8822C BIT(6)
+#define BIT_R_SYM_WLBBOFF_P4_EN_8822C BIT(4)
+#define BIT_R_SYM_WLBBOFF_P3_EN_8822C BIT(3)
+#define BIT_R_SYM_WLBBOFF_P2_EN_8822C BIT(2)
+#define BIT_R_SYM_WLBBOFF_P1_EN_8822C BIT(1)
+#define BIT_R_SYM_WLBBOFF_EN_8822C BIT(0)
+
+/* 2 REG_AFE_CTRL1_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+#define BIT_SHIFT_MAC_CLK_SEL_8822C 20
+#define BIT_MASK_MAC_CLK_SEL_8822C 0x3
+#define BIT_MAC_CLK_SEL_8822C(x)                                               \
+	(((x) & BIT_MASK_MAC_CLK_SEL_8822C) << BIT_SHIFT_MAC_CLK_SEL_8822C)
+#define BITS_MAC_CLK_SEL_8822C                                                 \
+	(BIT_MASK_MAC_CLK_SEL_8822C << BIT_SHIFT_MAC_CLK_SEL_8822C)
+#define BIT_CLEAR_MAC_CLK_SEL_8822C(x) ((x) & (~BITS_MAC_CLK_SEL_8822C))
+#define BIT_GET_MAC_CLK_SEL_8822C(x)                                           \
+	(((x) >> BIT_SHIFT_MAC_CLK_SEL_8822C) & BIT_MASK_MAC_CLK_SEL_8822C)
+#define BIT_SET_MAC_CLK_SEL_8822C(x, v)                                        \
+	(BIT_CLEAR_MAC_CLK_SEL_8822C(x) | BIT_MAC_CLK_SEL_8822C(v))
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_ANAPARSW_POW_MAC_8822C */
+#define BIT_POW_LDO15_8822C BIT(2)
+#define BIT_POW_SW_8822C BIT(1)
+#define BIT_POW_LDO14_8822C BIT(0)
+
+/* 2 REG_ANAPARLDO_POW_MAC_8822C */
+#define BIT_LDOE25_POW_L_8822C BIT(0)
+
+/* 2 REG_ANAPAR_POW_MAC_8822C */
+#define BIT_DUMMY_V4_8822C BIT(7)
+#define BIT_DUMMY_V3_8822C BIT(6)
+#define BIT_DUMMY_V2_8822C BIT(5)
+#define BIT_DUMMY_V1_8822C BIT(4)
+#define BIT_POW_PC_LDO_PORT1_8822C BIT(3)
+#define BIT_POW_PC_LDO_PORT0_8822C BIT(2)
+#define BIT_POW_PLL_V1_8822C BIT(1)
+#define BIT_POW_POWER_CUT_POW_LDO_8822C BIT(0)
+
+/* 2 REG_ANAPAR_POW_XTAL_8822C */
+#define BIT_POW_XTAL_8822C BIT(1)
+#define BIT_POW_BG_8822C BIT(0)
+
+/* 2 REG_ANAPARLDO_MAC_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+#define BIT_REG_STANDBY_L_8822C BIT(19)
+#define BIT_PD_REGU_L_8822C BIT(18)
+#define BIT_EN_PC_BT_L_8822C BIT(17)
+
+#define BIT_SHIFT_REG_LDOADJ_L_8822C 13
+#define BIT_MASK_REG_LDOADJ_L_8822C 0xf
+#define BIT_REG_LDOADJ_L_8822C(x)                                              \
+	(((x) & BIT_MASK_REG_LDOADJ_L_8822C) << BIT_SHIFT_REG_LDOADJ_L_8822C)
+#define BITS_REG_LDOADJ_L_8822C                                                \
+	(BIT_MASK_REG_LDOADJ_L_8822C << BIT_SHIFT_REG_LDOADJ_L_8822C)
+#define BIT_CLEAR_REG_LDOADJ_L_8822C(x) ((x) & (~BITS_REG_LDOADJ_L_8822C))
+#define BIT_GET_REG_LDOADJ_L_8822C(x)                                          \
+	(((x) >> BIT_SHIFT_REG_LDOADJ_L_8822C) & BIT_MASK_REG_LDOADJ_L_8822C)
+#define BIT_SET_REG_LDOADJ_L_8822C(x, v)                                       \
+	(BIT_CLEAR_REG_LDOADJ_L_8822C(x) | BIT_REG_LDOADJ_L_8822C(v))
+
+#define BIT_CK12M_EN_8822C BIT(11)
+#define BIT_CK12M_SEL_8822C BIT(10)
+#define BIT_EN_25_L_8822C BIT(9)
+#define BIT_EN_SLEEP_8822C BIT(8)
+
+#define BIT_SHIFT_LDOH12_V12ADJ_L_8822C 4
+#define BIT_MASK_LDOH12_V12ADJ_L_8822C 0xf
+#define BIT_LDOH12_V12ADJ_L_8822C(x)                                           \
+	(((x) & BIT_MASK_LDOH12_V12ADJ_L_8822C)                                \
+	 << BIT_SHIFT_LDOH12_V12ADJ_L_8822C)
+#define BITS_LDOH12_V12ADJ_L_8822C                                             \
+	(BIT_MASK_LDOH12_V12ADJ_L_8822C << BIT_SHIFT_LDOH12_V12ADJ_L_8822C)
+#define BIT_CLEAR_LDOH12_V12ADJ_L_8822C(x) ((x) & (~BITS_LDOH12_V12ADJ_L_8822C))
+#define BIT_GET_LDOH12_V12ADJ_L_8822C(x)                                       \
+	(((x) >> BIT_SHIFT_LDOH12_V12ADJ_L_8822C) &                            \
+	 BIT_MASK_LDOH12_V12ADJ_L_8822C)
+#define BIT_SET_LDOH12_V12ADJ_L_8822C(x, v)                                    \
+	(BIT_CLEAR_LDOH12_V12ADJ_L_8822C(x) | BIT_LDOH12_V12ADJ_L_8822C(v))
+
+#define BIT_SHIFT_LDOE25_V12ADJ_L_V1_8822C 0
+#define BIT_MASK_LDOE25_V12ADJ_L_V1_8822C 0xf
+#define BIT_LDOE25_V12ADJ_L_V1_8822C(x)                                        \
+	(((x) & BIT_MASK_LDOE25_V12ADJ_L_V1_8822C)                             \
+	 << BIT_SHIFT_LDOE25_V12ADJ_L_V1_8822C)
+#define BITS_LDOE25_V12ADJ_L_V1_8822C                                          \
+	(BIT_MASK_LDOE25_V12ADJ_L_V1_8822C                                     \
+	 << BIT_SHIFT_LDOE25_V12ADJ_L_V1_8822C)
+#define BIT_CLEAR_LDOE25_V12ADJ_L_V1_8822C(x)                                  \
+	((x) & (~BITS_LDOE25_V12ADJ_L_V1_8822C))
+#define BIT_GET_LDOE25_V12ADJ_L_V1_8822C(x)                                    \
+	(((x) >> BIT_SHIFT_LDOE25_V12ADJ_L_V1_8822C) &                         \
+	 BIT_MASK_LDOE25_V12ADJ_L_V1_8822C)
+#define BIT_SET_LDOE25_V12ADJ_L_V1_8822C(x, v)                                 \
+	(BIT_CLEAR_LDOE25_V12ADJ_L_V1_8822C(x) |                               \
+	 BIT_LDOE25_V12ADJ_L_V1_8822C(v))
+
+/* 2 REG_EFUSE_CTRL_8822C */
+#define BIT_EF_FLAG_8822C BIT(31)
+
+#define BIT_SHIFT_EF_PGPD_8822C 28
+#define BIT_MASK_EF_PGPD_8822C 0x7
+#define BIT_EF_PGPD_8822C(x)                                                   \
+	(((x) & BIT_MASK_EF_PGPD_8822C) << BIT_SHIFT_EF_PGPD_8822C)
+#define BITS_EF_PGPD_8822C (BIT_MASK_EF_PGPD_8822C << BIT_SHIFT_EF_PGPD_8822C)
+#define BIT_CLEAR_EF_PGPD_8822C(x) ((x) & (~BITS_EF_PGPD_8822C))
+#define BIT_GET_EF_PGPD_8822C(x)                                               \
+	(((x) >> BIT_SHIFT_EF_PGPD_8822C) & BIT_MASK_EF_PGPD_8822C)
+#define BIT_SET_EF_PGPD_8822C(x, v)                                            \
+	(BIT_CLEAR_EF_PGPD_8822C(x) | BIT_EF_PGPD_8822C(v))
+
+#define BIT_SHIFT_EF_RDT_8822C 24
+#define BIT_MASK_EF_RDT_8822C 0xf
+#define BIT_EF_RDT_8822C(x)                                                    \
+	(((x) & BIT_MASK_EF_RDT_8822C) << BIT_SHIFT_EF_RDT_8822C)
+#define BITS_EF_RDT_8822C (BIT_MASK_EF_RDT_8822C << BIT_SHIFT_EF_RDT_8822C)
+#define BIT_CLEAR_EF_RDT_8822C(x) ((x) & (~BITS_EF_RDT_8822C))
+#define BIT_GET_EF_RDT_8822C(x)                                                \
+	(((x) >> BIT_SHIFT_EF_RDT_8822C) & BIT_MASK_EF_RDT_8822C)
+#define BIT_SET_EF_RDT_8822C(x, v)                                             \
+	(BIT_CLEAR_EF_RDT_8822C(x) | BIT_EF_RDT_8822C(v))
+
+#define BIT_SHIFT_EF_PGTS_8822C 20
+#define BIT_MASK_EF_PGTS_8822C 0xf
+#define BIT_EF_PGTS_8822C(x)                                                   \
+	(((x) & BIT_MASK_EF_PGTS_8822C) << BIT_SHIFT_EF_PGTS_8822C)
+#define BITS_EF_PGTS_8822C (BIT_MASK_EF_PGTS_8822C << BIT_SHIFT_EF_PGTS_8822C)
+#define BIT_CLEAR_EF_PGTS_8822C(x) ((x) & (~BITS_EF_PGTS_8822C))
+#define BIT_GET_EF_PGTS_8822C(x)                                               \
+	(((x) >> BIT_SHIFT_EF_PGTS_8822C) & BIT_MASK_EF_PGTS_8822C)
+#define BIT_SET_EF_PGTS_8822C(x, v)                                            \
+	(BIT_CLEAR_EF_PGTS_8822C(x) | BIT_EF_PGTS_8822C(v))
+
+#define BIT_EF_PDWN_8822C BIT(19)
+#define BIT_EF_ALDEN_8822C BIT(18)
+
+#define BIT_SHIFT_EF_ADDR_8822C 8
+#define BIT_MASK_EF_ADDR_8822C 0x3ff
+#define BIT_EF_ADDR_8822C(x)                                                   \
+	(((x) & BIT_MASK_EF_ADDR_8822C) << BIT_SHIFT_EF_ADDR_8822C)
+#define BITS_EF_ADDR_8822C (BIT_MASK_EF_ADDR_8822C << BIT_SHIFT_EF_ADDR_8822C)
+#define BIT_CLEAR_EF_ADDR_8822C(x) ((x) & (~BITS_EF_ADDR_8822C))
+#define BIT_GET_EF_ADDR_8822C(x)                                               \
+	(((x) >> BIT_SHIFT_EF_ADDR_8822C) & BIT_MASK_EF_ADDR_8822C)
+#define BIT_SET_EF_ADDR_8822C(x, v)                                            \
+	(BIT_CLEAR_EF_ADDR_8822C(x) | BIT_EF_ADDR_8822C(v))
+
+#define BIT_SHIFT_EF_DATA_8822C 0
+#define BIT_MASK_EF_DATA_8822C 0xff
+#define BIT_EF_DATA_8822C(x)                                                   \
+	(((x) & BIT_MASK_EF_DATA_8822C) << BIT_SHIFT_EF_DATA_8822C)
+#define BITS_EF_DATA_8822C (BIT_MASK_EF_DATA_8822C << BIT_SHIFT_EF_DATA_8822C)
+#define BIT_CLEAR_EF_DATA_8822C(x) ((x) & (~BITS_EF_DATA_8822C))
+#define BIT_GET_EF_DATA_8822C(x)                                               \
+	(((x) >> BIT_SHIFT_EF_DATA_8822C) & BIT_MASK_EF_DATA_8822C)
+#define BIT_SET_EF_DATA_8822C(x, v)                                            \
+	(BIT_CLEAR_EF_DATA_8822C(x) | BIT_EF_DATA_8822C(v))
+
+/* 2 REG_LDO_EFUSE_CTRL_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+#define BIT_EF_CRES_SEL_8822C BIT(26)
+
+#define BIT_SHIFT_EF_SCAN_START_V1_8822C 16
+#define BIT_MASK_EF_SCAN_START_V1_8822C 0x3ff
+#define BIT_EF_SCAN_START_V1_8822C(x)                                          \
+	(((x) & BIT_MASK_EF_SCAN_START_V1_8822C)                               \
+	 << BIT_SHIFT_EF_SCAN_START_V1_8822C)
+#define BITS_EF_SCAN_START_V1_8822C                                            \
+	(BIT_MASK_EF_SCAN_START_V1_8822C << BIT_SHIFT_EF_SCAN_START_V1_8822C)
+#define BIT_CLEAR_EF_SCAN_START_V1_8822C(x)                                    \
+	((x) & (~BITS_EF_SCAN_START_V1_8822C))
+#define BIT_GET_EF_SCAN_START_V1_8822C(x)                                      \
+	(((x) >> BIT_SHIFT_EF_SCAN_START_V1_8822C) &                           \
+	 BIT_MASK_EF_SCAN_START_V1_8822C)
+#define BIT_SET_EF_SCAN_START_V1_8822C(x, v)                                   \
+	(BIT_CLEAR_EF_SCAN_START_V1_8822C(x) | BIT_EF_SCAN_START_V1_8822C(v))
+
+#define BIT_SHIFT_EF_SCAN_END_8822C 12
+#define BIT_MASK_EF_SCAN_END_8822C 0xf
+#define BIT_EF_SCAN_END_8822C(x)                                               \
+	(((x) & BIT_MASK_EF_SCAN_END_8822C) << BIT_SHIFT_EF_SCAN_END_8822C)
+#define BITS_EF_SCAN_END_8822C                                                 \
+	(BIT_MASK_EF_SCAN_END_8822C << BIT_SHIFT_EF_SCAN_END_8822C)
+#define BIT_CLEAR_EF_SCAN_END_8822C(x) ((x) & (~BITS_EF_SCAN_END_8822C))
+#define BIT_GET_EF_SCAN_END_8822C(x)                                           \
+	(((x) >> BIT_SHIFT_EF_SCAN_END_8822C) & BIT_MASK_EF_SCAN_END_8822C)
+#define BIT_SET_EF_SCAN_END_8822C(x, v)                                        \
+	(BIT_CLEAR_EF_SCAN_END_8822C(x) | BIT_EF_SCAN_END_8822C(v))
+
+#define BIT_EF_PD_DIS_8822C BIT(11)
+
+#define BIT_SHIFT_EF_CELL_SEL_8822C 8
+#define BIT_MASK_EF_CELL_SEL_8822C 0x3
+#define BIT_EF_CELL_SEL_8822C(x)                                               \
+	(((x) & BIT_MASK_EF_CELL_SEL_8822C) << BIT_SHIFT_EF_CELL_SEL_8822C)
+#define BITS_EF_CELL_SEL_8822C                                                 \
+	(BIT_MASK_EF_CELL_SEL_8822C << BIT_SHIFT_EF_CELL_SEL_8822C)
+#define BIT_CLEAR_EF_CELL_SEL_8822C(x) ((x) & (~BITS_EF_CELL_SEL_8822C))
+#define BIT_GET_EF_CELL_SEL_8822C(x)                                           \
+	(((x) >> BIT_SHIFT_EF_CELL_SEL_8822C) & BIT_MASK_EF_CELL_SEL_8822C)
+#define BIT_SET_EF_CELL_SEL_8822C(x, v)                                        \
+	(BIT_CLEAR_EF_CELL_SEL_8822C(x) | BIT_EF_CELL_SEL_8822C(v))
+
+#define BIT_EF_TRPT_8822C BIT(7)
+
+#define BIT_SHIFT_EF_TTHD_8822C 0
+#define BIT_MASK_EF_TTHD_8822C 0x7f
+#define BIT_EF_TTHD_8822C(x)                                                   \
+	(((x) & BIT_MASK_EF_TTHD_8822C) << BIT_SHIFT_EF_TTHD_8822C)
+#define BITS_EF_TTHD_8822C (BIT_MASK_EF_TTHD_8822C << BIT_SHIFT_EF_TTHD_8822C)
+#define BIT_CLEAR_EF_TTHD_8822C(x) ((x) & (~BITS_EF_TTHD_8822C))
+#define BIT_GET_EF_TTHD_8822C(x)                                               \
+	(((x) >> BIT_SHIFT_EF_TTHD_8822C) & BIT_MASK_EF_TTHD_8822C)
+#define BIT_SET_EF_TTHD_8822C(x, v)                                            \
+	(BIT_CLEAR_EF_TTHD_8822C(x) | BIT_EF_TTHD_8822C(v))
+
+/* 2 REG_PWR_OPTION_CTRL_8822C */
+
+#define BIT_SHIFT_DBG_SEL_V1_8822C 16
+#define BIT_MASK_DBG_SEL_V1_8822C 0xff
+#define BIT_DBG_SEL_V1_8822C(x)                                                \
+	(((x) & BIT_MASK_DBG_SEL_V1_8822C) << BIT_SHIFT_DBG_SEL_V1_8822C)
+#define BITS_DBG_SEL_V1_8822C                                                  \
+	(BIT_MASK_DBG_SEL_V1_8822C << BIT_SHIFT_DBG_SEL_V1_8822C)
+#define BIT_CLEAR_DBG_SEL_V1_8822C(x) ((x) & (~BITS_DBG_SEL_V1_8822C))
+#define BIT_GET_DBG_SEL_V1_8822C(x)                                            \
+	(((x) >> BIT_SHIFT_DBG_SEL_V1_8822C) & BIT_MASK_DBG_SEL_V1_8822C)
+#define BIT_SET_DBG_SEL_V1_8822C(x, v)                                         \
+	(BIT_CLEAR_DBG_SEL_V1_8822C(x) | BIT_DBG_SEL_V1_8822C(v))
+
+#define BIT_SHIFT_DBG_SEL_BYTE_8822C 14
+#define BIT_MASK_DBG_SEL_BYTE_8822C 0x3
+#define BIT_DBG_SEL_BYTE_8822C(x)                                              \
+	(((x) & BIT_MASK_DBG_SEL_BYTE_8822C) << BIT_SHIFT_DBG_SEL_BYTE_8822C)
+#define BITS_DBG_SEL_BYTE_8822C                                                \
+	(BIT_MASK_DBG_SEL_BYTE_8822C << BIT_SHIFT_DBG_SEL_BYTE_8822C)
+#define BIT_CLEAR_DBG_SEL_BYTE_8822C(x) ((x) & (~BITS_DBG_SEL_BYTE_8822C))
+#define BIT_GET_DBG_SEL_BYTE_8822C(x)                                          \
+	(((x) >> BIT_SHIFT_DBG_SEL_BYTE_8822C) & BIT_MASK_DBG_SEL_BYTE_8822C)
+#define BIT_SET_DBG_SEL_BYTE_8822C(x, v)                                       \
+	(BIT_CLEAR_DBG_SEL_BYTE_8822C(x) | BIT_DBG_SEL_BYTE_8822C(v))
+
+/* 2 REG_NOT_VALID_8822C */
+#define BIT_SYSON_DBG_PAD_E2_8822C BIT(11)
+#define BIT_SYSON_LED_PAD_E2_8822C BIT(10)
+#define BIT_SYSON_GPEE_PAD_E2_8822C BIT(9)
+#define BIT_SYSON_PCI_PAD_E2_8822C BIT(8)
+#define BIT_AUTO_SW_LDO_VOL_EN_8822C BIT(7)
+
+#define BIT_SHIFT_SYSON_SPS0WWV_WT_8822C 4
+#define BIT_MASK_SYSON_SPS0WWV_WT_8822C 0x3
+#define BIT_SYSON_SPS0WWV_WT_8822C(x)                                          \
+	(((x) & BIT_MASK_SYSON_SPS0WWV_WT_8822C)                               \
+	 << BIT_SHIFT_SYSON_SPS0WWV_WT_8822C)
+#define BITS_SYSON_SPS0WWV_WT_8822C                                            \
+	(BIT_MASK_SYSON_SPS0WWV_WT_8822C << BIT_SHIFT_SYSON_SPS0WWV_WT_8822C)
+#define BIT_CLEAR_SYSON_SPS0WWV_WT_8822C(x)                                    \
+	((x) & (~BITS_SYSON_SPS0WWV_WT_8822C))
+#define BIT_GET_SYSON_SPS0WWV_WT_8822C(x)                                      \
+	(((x) >> BIT_SHIFT_SYSON_SPS0WWV_WT_8822C) &                           \
+	 BIT_MASK_SYSON_SPS0WWV_WT_8822C)
+#define BIT_SET_SYSON_SPS0WWV_WT_8822C(x, v)                                   \
+	(BIT_CLEAR_SYSON_SPS0WWV_WT_8822C(x) | BIT_SYSON_SPS0WWV_WT_8822C(v))
+
+#define BIT_SHIFT_SYSON_SPS0LDO_WT_8822C 2
+#define BIT_MASK_SYSON_SPS0LDO_WT_8822C 0x3
+#define BIT_SYSON_SPS0LDO_WT_8822C(x)                                          \
+	(((x) & BIT_MASK_SYSON_SPS0LDO_WT_8822C)                               \
+	 << BIT_SHIFT_SYSON_SPS0LDO_WT_8822C)
+#define BITS_SYSON_SPS0LDO_WT_8822C                                            \
+	(BIT_MASK_SYSON_SPS0LDO_WT_8822C << BIT_SHIFT_SYSON_SPS0LDO_WT_8822C)
+#define BIT_CLEAR_SYSON_SPS0LDO_WT_8822C(x)                                    \
+	((x) & (~BITS_SYSON_SPS0LDO_WT_8822C))
+#define BIT_GET_SYSON_SPS0LDO_WT_8822C(x)                                      \
+	(((x) >> BIT_SHIFT_SYSON_SPS0LDO_WT_8822C) &                           \
+	 BIT_MASK_SYSON_SPS0LDO_WT_8822C)
+#define BIT_SET_SYSON_SPS0LDO_WT_8822C(x, v)                                   \
+	(BIT_CLEAR_SYSON_SPS0LDO_WT_8822C(x) | BIT_SYSON_SPS0LDO_WT_8822C(v))
+
+#define BIT_SHIFT_SYSON_RCLK_SCALE_8822C 0
+#define BIT_MASK_SYSON_RCLK_SCALE_8822C 0x3
+#define BIT_SYSON_RCLK_SCALE_8822C(x)                                          \
+	(((x) & BIT_MASK_SYSON_RCLK_SCALE_8822C)                               \
+	 << BIT_SHIFT_SYSON_RCLK_SCALE_8822C)
+#define BITS_SYSON_RCLK_SCALE_8822C                                            \
+	(BIT_MASK_SYSON_RCLK_SCALE_8822C << BIT_SHIFT_SYSON_RCLK_SCALE_8822C)
+#define BIT_CLEAR_SYSON_RCLK_SCALE_8822C(x)                                    \
+	((x) & (~BITS_SYSON_RCLK_SCALE_8822C))
+#define BIT_GET_SYSON_RCLK_SCALE_8822C(x)                                      \
+	(((x) >> BIT_SHIFT_SYSON_RCLK_SCALE_8822C) &                           \
+	 BIT_MASK_SYSON_RCLK_SCALE_8822C)
+#define BIT_SET_SYSON_RCLK_SCALE_8822C(x, v)                                   \
+	(BIT_CLEAR_SYSON_RCLK_SCALE_8822C(x) | BIT_SYSON_RCLK_SCALE_8822C(v))
+
+/* 2 REG_CAL_TIMER_8822C */
+
+#define BIT_SHIFT_MATCH_CNT_8822C 8
+#define BIT_MASK_MATCH_CNT_8822C 0xff
+#define BIT_MATCH_CNT_8822C(x)                                                 \
+	(((x) & BIT_MASK_MATCH_CNT_8822C) << BIT_SHIFT_MATCH_CNT_8822C)
+#define BITS_MATCH_CNT_8822C                                                   \
+	(BIT_MASK_MATCH_CNT_8822C << BIT_SHIFT_MATCH_CNT_8822C)
+#define BIT_CLEAR_MATCH_CNT_8822C(x) ((x) & (~BITS_MATCH_CNT_8822C))
+#define BIT_GET_MATCH_CNT_8822C(x)                                             \
+	(((x) >> BIT_SHIFT_MATCH_CNT_8822C) & BIT_MASK_MATCH_CNT_8822C)
+#define BIT_SET_MATCH_CNT_8822C(x, v)                                          \
+	(BIT_CLEAR_MATCH_CNT_8822C(x) | BIT_MATCH_CNT_8822C(v))
+
+#define BIT_SHIFT_CAL_SCAL_8822C 0
+#define BIT_MASK_CAL_SCAL_8822C 0xff
+#define BIT_CAL_SCAL_8822C(x)                                                  \
+	(((x) & BIT_MASK_CAL_SCAL_8822C) << BIT_SHIFT_CAL_SCAL_8822C)
+#define BITS_CAL_SCAL_8822C                                                    \
+	(BIT_MASK_CAL_SCAL_8822C << BIT_SHIFT_CAL_SCAL_8822C)
+#define BIT_CLEAR_CAL_SCAL_8822C(x) ((x) & (~BITS_CAL_SCAL_8822C))
+#define BIT_GET_CAL_SCAL_8822C(x)                                              \
+	(((x) >> BIT_SHIFT_CAL_SCAL_8822C) & BIT_MASK_CAL_SCAL_8822C)
+#define BIT_SET_CAL_SCAL_8822C(x, v)                                           \
+	(BIT_CLEAR_CAL_SCAL_8822C(x) | BIT_CAL_SCAL_8822C(v))
+
+/* 2 REG_ACLK_MON_8822C */
+
+#define BIT_SHIFT_RCLK_MON_8822C 5
+#define BIT_MASK_RCLK_MON_8822C 0x7ff
+#define BIT_RCLK_MON_8822C(x)                                                  \
+	(((x) & BIT_MASK_RCLK_MON_8822C) << BIT_SHIFT_RCLK_MON_8822C)
+#define BITS_RCLK_MON_8822C                                                    \
+	(BIT_MASK_RCLK_MON_8822C << BIT_SHIFT_RCLK_MON_8822C)
+#define BIT_CLEAR_RCLK_MON_8822C(x) ((x) & (~BITS_RCLK_MON_8822C))
+#define BIT_GET_RCLK_MON_8822C(x)                                              \
+	(((x) >> BIT_SHIFT_RCLK_MON_8822C) & BIT_MASK_RCLK_MON_8822C)
+#define BIT_SET_RCLK_MON_8822C(x, v)                                           \
+	(BIT_CLEAR_RCLK_MON_8822C(x) | BIT_RCLK_MON_8822C(v))
+
+#define BIT_CAL_EN_8822C BIT(4)
+
+#define BIT_SHIFT_DPSTU_8822C 2
+#define BIT_MASK_DPSTU_8822C 0x3
+#define BIT_DPSTU_8822C(x)                                                     \
+	(((x) & BIT_MASK_DPSTU_8822C) << BIT_SHIFT_DPSTU_8822C)
+#define BITS_DPSTU_8822C (BIT_MASK_DPSTU_8822C << BIT_SHIFT_DPSTU_8822C)
+#define BIT_CLEAR_DPSTU_8822C(x) ((x) & (~BITS_DPSTU_8822C))
+#define BIT_GET_DPSTU_8822C(x)                                                 \
+	(((x) >> BIT_SHIFT_DPSTU_8822C) & BIT_MASK_DPSTU_8822C)
+#define BIT_SET_DPSTU_8822C(x, v)                                              \
+	(BIT_CLEAR_DPSTU_8822C(x) | BIT_DPSTU_8822C(v))
+
+#define BIT_SUS_16X_8822C BIT(1)
+
+/* 2 REG_GPIO_MUXCFG_2_8822C */
+#define BIT_SOUT_GPIO8_8822C BIT(7)
+#define BIT_SOUT_GPIO5_8822C BIT(6)
+#define BIT_RFE_CTRL_5_GPIO14_V1_8822C BIT(5)
+#define BIT_RFE_CTRL_10_GPIO13_V1_8822C BIT(4)
+#define BIT_RFE_CTRL_11_GPIO4_V1_8822C BIT(3)
+#define BIT_RFE_CTRL_5_GPIO14_8822C BIT(2)
+#define BIT_RFE_CTRL_10_GPIO13_8822C BIT(1)
+#define BIT_RFE_CTRL_11_GPIO4_8822C BIT(0)
+
+/* 2 REG_GPIO_MUXCFG_8822C */
+#define BIT_RFE_CTRL_3_GPIO12_8822C BIT(31)
+#define BIT_BT_RFE_CTRL_5_GPIO12_8822C BIT(30)
+#define BIT_S0_TRSW_GPIO12_8822C BIT(29)
+#define BIT_RFE_CTRL_9_GPIO13_8822C BIT(28)
+#define BIT_RFE_CTRL_9_GPIO12_8822C BIT(27)
+#define BIT_RFE_CTRL_8_GPIO4_8822C BIT(26)
+#define BIT_BT_RFE_CTRL_1_GPIO13_8822C BIT(25)
+#define BIT_BT_RFE_CTRL_1_GPIO12_8822C BIT(24)
+#define BIT_BT_RFE_CTRL_0_GPIO4_8822C BIT(23)
+#define BIT_ANTSW_GPIO13_8822C BIT(22)
+#define BIT_ANTSW_GPIO12_8822C BIT(21)
+#define BIT_ANTSWB_GPIO4_8822C BIT(20)
+#define BIT_FSPI_EN_8822C BIT(19)
+#define BIT_WL_RTS_EXT_32K_SEL_8822C BIT(18)
+#define BIT_WLBT_DPDT_SEL_EN_8822C BIT(17)
+#define BIT_WLBT_LNAON_SEL_EN_8822C BIT(16)
+#define BIT_SIC_LBK_8822C BIT(15)
+#define BIT_ENHTP_8822C BIT(14)
+#define BIT_BT_AOD_GPIO3_8822C BIT(13)
+#define BIT_ENSIC_8822C BIT(12)
+#define BIT_SIC_SWRST_8822C BIT(11)
+#define BIT_PO_WIFI_PTA_PINS_8822C BIT(10)
+#define BIT_PO_BT_PTA_PINS_8822C BIT(9)
+#define BIT_ENUART_8822C BIT(8)
+
+#define BIT_SHIFT_BTMODE_8822C 6
+#define BIT_MASK_BTMODE_8822C 0x3
+#define BIT_BTMODE_8822C(x)                                                    \
+	(((x) & BIT_MASK_BTMODE_8822C) << BIT_SHIFT_BTMODE_8822C)
+#define BITS_BTMODE_8822C (BIT_MASK_BTMODE_8822C << BIT_SHIFT_BTMODE_8822C)
+#define BIT_CLEAR_BTMODE_8822C(x) ((x) & (~BITS_BTMODE_8822C))
+#define BIT_GET_BTMODE_8822C(x)                                                \
+	(((x) >> BIT_SHIFT_BTMODE_8822C) & BIT_MASK_BTMODE_8822C)
+#define BIT_SET_BTMODE_8822C(x, v)                                             \
+	(BIT_CLEAR_BTMODE_8822C(x) | BIT_BTMODE_8822C(v))
+
+#define BIT_ENBT_8822C BIT(5)
+#define BIT_EROM_EN_8822C BIT(4)
+#define BIT_WLRFE_6_7_EN_8822C BIT(3)
+#define BIT_WLRFE_4_5_EN_8822C BIT(2)
+
+#define BIT_SHIFT_GPIOSEL_8822C 0
+#define BIT_MASK_GPIOSEL_8822C 0x3
+#define BIT_GPIOSEL_8822C(x)                                                   \
+	(((x) & BIT_MASK_GPIOSEL_8822C) << BIT_SHIFT_GPIOSEL_8822C)
+#define BITS_GPIOSEL_8822C (BIT_MASK_GPIOSEL_8822C << BIT_SHIFT_GPIOSEL_8822C)
+#define BIT_CLEAR_GPIOSEL_8822C(x) ((x) & (~BITS_GPIOSEL_8822C))
+#define BIT_GET_GPIOSEL_8822C(x)                                               \
+	(((x) >> BIT_SHIFT_GPIOSEL_8822C) & BIT_MASK_GPIOSEL_8822C)
+#define BIT_SET_GPIOSEL_8822C(x, v)                                            \
+	(BIT_CLEAR_GPIOSEL_8822C(x) | BIT_GPIOSEL_8822C(v))
+
+/* 2 REG_GPIO_PIN_CTRL_8822C */
+
+#define BIT_SHIFT_GPIO_MOD_7_TO_0_8822C 24
+#define BIT_MASK_GPIO_MOD_7_TO_0_8822C 0xff
+#define BIT_GPIO_MOD_7_TO_0_8822C(x)                                           \
+	(((x) & BIT_MASK_GPIO_MOD_7_TO_0_8822C)                                \
+	 << BIT_SHIFT_GPIO_MOD_7_TO_0_8822C)
+#define BITS_GPIO_MOD_7_TO_0_8822C                                             \
+	(BIT_MASK_GPIO_MOD_7_TO_0_8822C << BIT_SHIFT_GPIO_MOD_7_TO_0_8822C)
+#define BIT_CLEAR_GPIO_MOD_7_TO_0_8822C(x) ((x) & (~BITS_GPIO_MOD_7_TO_0_8822C))
+#define BIT_GET_GPIO_MOD_7_TO_0_8822C(x)                                       \
+	(((x) >> BIT_SHIFT_GPIO_MOD_7_TO_0_8822C) &                            \
+	 BIT_MASK_GPIO_MOD_7_TO_0_8822C)
+#define BIT_SET_GPIO_MOD_7_TO_0_8822C(x, v)                                    \
+	(BIT_CLEAR_GPIO_MOD_7_TO_0_8822C(x) | BIT_GPIO_MOD_7_TO_0_8822C(v))
+
+#define BIT_SHIFT_GPIO_IO_SEL_7_TO_0_8822C 16
+#define BIT_MASK_GPIO_IO_SEL_7_TO_0_8822C 0xff
+#define BIT_GPIO_IO_SEL_7_TO_0_8822C(x)                                        \
+	(((x) & BIT_MASK_GPIO_IO_SEL_7_TO_0_8822C)                             \
+	 << BIT_SHIFT_GPIO_IO_SEL_7_TO_0_8822C)
+#define BITS_GPIO_IO_SEL_7_TO_0_8822C                                          \
+	(BIT_MASK_GPIO_IO_SEL_7_TO_0_8822C                                     \
+	 << BIT_SHIFT_GPIO_IO_SEL_7_TO_0_8822C)
+#define BIT_CLEAR_GPIO_IO_SEL_7_TO_0_8822C(x)                                  \
+	((x) & (~BITS_GPIO_IO_SEL_7_TO_0_8822C))
+#define BIT_GET_GPIO_IO_SEL_7_TO_0_8822C(x)                                    \
+	(((x) >> BIT_SHIFT_GPIO_IO_SEL_7_TO_0_8822C) &                         \
+	 BIT_MASK_GPIO_IO_SEL_7_TO_0_8822C)
+#define BIT_SET_GPIO_IO_SEL_7_TO_0_8822C(x, v)                                 \
+	(BIT_CLEAR_GPIO_IO_SEL_7_TO_0_8822C(x) |                               \
+	 BIT_GPIO_IO_SEL_7_TO_0_8822C(v))
+
+#define BIT_SHIFT_GPIO_OUT_7_TO_0_8822C 8
+#define BIT_MASK_GPIO_OUT_7_TO_0_8822C 0xff
+#define BIT_GPIO_OUT_7_TO_0_8822C(x)                                           \
+	(((x) & BIT_MASK_GPIO_OUT_7_TO_0_8822C)                                \
+	 << BIT_SHIFT_GPIO_OUT_7_TO_0_8822C)
+#define BITS_GPIO_OUT_7_TO_0_8822C                                             \
+	(BIT_MASK_GPIO_OUT_7_TO_0_8822C << BIT_SHIFT_GPIO_OUT_7_TO_0_8822C)
+#define BIT_CLEAR_GPIO_OUT_7_TO_0_8822C(x) ((x) & (~BITS_GPIO_OUT_7_TO_0_8822C))
+#define BIT_GET_GPIO_OUT_7_TO_0_8822C(x)                                       \
+	(((x) >> BIT_SHIFT_GPIO_OUT_7_TO_0_8822C) &                            \
+	 BIT_MASK_GPIO_OUT_7_TO_0_8822C)
+#define BIT_SET_GPIO_OUT_7_TO_0_8822C(x, v)                                    \
+	(BIT_CLEAR_GPIO_OUT_7_TO_0_8822C(x) | BIT_GPIO_OUT_7_TO_0_8822C(v))
+
+#define BIT_SHIFT_GPIO_IN_7_TO_0_8822C 0
+#define BIT_MASK_GPIO_IN_7_TO_0_8822C 0xff
+#define BIT_GPIO_IN_7_TO_0_8822C(x)                                            \
+	(((x) & BIT_MASK_GPIO_IN_7_TO_0_8822C)                                 \
+	 << BIT_SHIFT_GPIO_IN_7_TO_0_8822C)
+#define BITS_GPIO_IN_7_TO_0_8822C                                              \
+	(BIT_MASK_GPIO_IN_7_TO_0_8822C << BIT_SHIFT_GPIO_IN_7_TO_0_8822C)
+#define BIT_CLEAR_GPIO_IN_7_TO_0_8822C(x) ((x) & (~BITS_GPIO_IN_7_TO_0_8822C))
+#define BIT_GET_GPIO_IN_7_TO_0_8822C(x)                                        \
+	(((x) >> BIT_SHIFT_GPIO_IN_7_TO_0_8822C) &                             \
+	 BIT_MASK_GPIO_IN_7_TO_0_8822C)
+#define BIT_SET_GPIO_IN_7_TO_0_8822C(x, v)                                     \
+	(BIT_CLEAR_GPIO_IN_7_TO_0_8822C(x) | BIT_GPIO_IN_7_TO_0_8822C(v))
+
+/* 2 REG_GPIO_INTM_8822C */
+
+#define BIT_SHIFT_MUXDBG_SEL_8822C 30
+#define BIT_MASK_MUXDBG_SEL_8822C 0x3
+#define BIT_MUXDBG_SEL_8822C(x)                                                \
+	(((x) & BIT_MASK_MUXDBG_SEL_8822C) << BIT_SHIFT_MUXDBG_SEL_8822C)
+#define BITS_MUXDBG_SEL_8822C                                                  \
+	(BIT_MASK_MUXDBG_SEL_8822C << BIT_SHIFT_MUXDBG_SEL_8822C)
+#define BIT_CLEAR_MUXDBG_SEL_8822C(x) ((x) & (~BITS_MUXDBG_SEL_8822C))
+#define BIT_GET_MUXDBG_SEL_8822C(x)                                            \
+	(((x) >> BIT_SHIFT_MUXDBG_SEL_8822C) & BIT_MASK_MUXDBG_SEL_8822C)
+#define BIT_SET_MUXDBG_SEL_8822C(x, v)                                         \
+	(BIT_CLEAR_MUXDBG_SEL_8822C(x) | BIT_MUXDBG_SEL_8822C(v))
+
+#define BIT_EXTWOL_SEL_8822C BIT(17)
+#define BIT_EXTWOL_EN_8822C BIT(16)
+#define BIT_GPIOF_INT_MD_8822C BIT(15)
+#define BIT_GPIOE_INT_MD_8822C BIT(14)
+#define BIT_GPIOD_INT_MD_8822C BIT(13)
+#define BIT_GPIOF_INT_MD_8822C BIT(15)
+#define BIT_GPIOE_INT_MD_8822C BIT(14)
+#define BIT_GPIOD_INT_MD_8822C BIT(13)
+#define BIT_GPIOC_INT_MD_8822C BIT(12)
+#define BIT_GPIOB_INT_MD_8822C BIT(11)
+#define BIT_GPIOA_INT_MD_8822C BIT(10)
+#define BIT_GPIO9_INT_MD_8822C BIT(9)
+#define BIT_GPIO8_INT_MD_8822C BIT(8)
+#define BIT_GPIO7_INT_MD_8822C BIT(7)
+#define BIT_GPIO6_INT_MD_8822C BIT(6)
+#define BIT_GPIO5_INT_MD_8822C BIT(5)
+#define BIT_GPIO4_INT_MD_8822C BIT(4)
+#define BIT_GPIO3_INT_MD_8822C BIT(3)
+#define BIT_GPIO2_INT_MD_8822C BIT(2)
+#define BIT_GPIO1_INT_MD_8822C BIT(1)
+#define BIT_GPIO0_INT_MD_8822C BIT(0)
+
+/* 2 REG_LED_CFG_8822C */
+#define BIT_MAILBOX_1WIRE_GPIO_CFG_8822C BIT(31)
+#define BIT_BT_RF_GPIO_CFG_8822C BIT(30)
+#define BIT_BT_SDIO_INT_GPIO_CFG_8822C BIT(29)
+#define BIT_MAILBOX_3WIRE_GPIO_CFG_8822C BIT(28)
+#define BIT_WLBT_PAPE_SEL_EN_8822C BIT(27)
+#define BIT_LNAON_SEL_EN_8822C BIT(26)
+#define BIT_PAPE_SEL_EN_8822C BIT(25)
+#define BIT_DPDT_WLBT_SEL_8822C BIT(24)
+#define BIT_DPDT_SEL_EN_8822C BIT(23)
+#define BIT_GPIO13_14_WL_CTRL_EN_8822C BIT(22)
+#define BIT_LED2DIS_8822C BIT(21)
+#define BIT_LED2PL_8822C BIT(20)
+#define BIT_LED2SV_8822C BIT(19)
+
+#define BIT_SHIFT_LED2CM_8822C 16
+#define BIT_MASK_LED2CM_8822C 0x7
+#define BIT_LED2CM_8822C(x)                                                    \
+	(((x) & BIT_MASK_LED2CM_8822C) << BIT_SHIFT_LED2CM_8822C)
+#define BITS_LED2CM_8822C (BIT_MASK_LED2CM_8822C << BIT_SHIFT_LED2CM_8822C)
+#define BIT_CLEAR_LED2CM_8822C(x) ((x) & (~BITS_LED2CM_8822C))
+#define BIT_GET_LED2CM_8822C(x)                                                \
+	(((x) >> BIT_SHIFT_LED2CM_8822C) & BIT_MASK_LED2CM_8822C)
+#define BIT_SET_LED2CM_8822C(x, v)                                             \
+	(BIT_CLEAR_LED2CM_8822C(x) | BIT_LED2CM_8822C(v))
+
+#define BIT_LED1DIS_8822C BIT(15)
+#define BIT_LED1PL_8822C BIT(12)
+#define BIT_LED1SV_8822C BIT(11)
+
+#define BIT_SHIFT_LED1CM_8822C 8
+#define BIT_MASK_LED1CM_8822C 0x7
+#define BIT_LED1CM_8822C(x)                                                    \
+	(((x) & BIT_MASK_LED1CM_8822C) << BIT_SHIFT_LED1CM_8822C)
+#define BITS_LED1CM_8822C (BIT_MASK_LED1CM_8822C << BIT_SHIFT_LED1CM_8822C)
+#define BIT_CLEAR_LED1CM_8822C(x) ((x) & (~BITS_LED1CM_8822C))
+#define BIT_GET_LED1CM_8822C(x)                                                \
+	(((x) >> BIT_SHIFT_LED1CM_8822C) & BIT_MASK_LED1CM_8822C)
+#define BIT_SET_LED1CM_8822C(x, v)                                             \
+	(BIT_CLEAR_LED1CM_8822C(x) | BIT_LED1CM_8822C(v))
+
+#define BIT_LED0DIS_8822C BIT(7)
+
+#define BIT_SHIFT_AFE_LDO_SWR_CHECK_8822C 5
+#define BIT_MASK_AFE_LDO_SWR_CHECK_8822C 0x3
+#define BIT_AFE_LDO_SWR_CHECK_8822C(x)                                         \
+	(((x) & BIT_MASK_AFE_LDO_SWR_CHECK_8822C)                              \
+	 << BIT_SHIFT_AFE_LDO_SWR_CHECK_8822C)
+#define BITS_AFE_LDO_SWR_CHECK_8822C                                           \
+	(BIT_MASK_AFE_LDO_SWR_CHECK_8822C << BIT_SHIFT_AFE_LDO_SWR_CHECK_8822C)
+#define BIT_CLEAR_AFE_LDO_SWR_CHECK_8822C(x)                                   \
+	((x) & (~BITS_AFE_LDO_SWR_CHECK_8822C))
+#define BIT_GET_AFE_LDO_SWR_CHECK_8822C(x)                                     \
+	(((x) >> BIT_SHIFT_AFE_LDO_SWR_CHECK_8822C) &                          \
+	 BIT_MASK_AFE_LDO_SWR_CHECK_8822C)
+#define BIT_SET_AFE_LDO_SWR_CHECK_8822C(x, v)                                  \
+	(BIT_CLEAR_AFE_LDO_SWR_CHECK_8822C(x) | BIT_AFE_LDO_SWR_CHECK_8822C(v))
+
+#define BIT_LED0PL_8822C BIT(4)
+#define BIT_LED0SV_8822C BIT(3)
+
+#define BIT_SHIFT_LED0CM_8822C 0
+#define BIT_MASK_LED0CM_8822C 0x7
+#define BIT_LED0CM_8822C(x)                                                    \
+	(((x) & BIT_MASK_LED0CM_8822C) << BIT_SHIFT_LED0CM_8822C)
+#define BITS_LED0CM_8822C (BIT_MASK_LED0CM_8822C << BIT_SHIFT_LED0CM_8822C)
+#define BIT_CLEAR_LED0CM_8822C(x) ((x) & (~BITS_LED0CM_8822C))
+#define BIT_GET_LED0CM_8822C(x)                                                \
+	(((x) >> BIT_SHIFT_LED0CM_8822C) & BIT_MASK_LED0CM_8822C)
+#define BIT_SET_LED0CM_8822C(x, v)                                             \
+	(BIT_CLEAR_LED0CM_8822C(x) | BIT_LED0CM_8822C(v))
+
+/* 2 REG_FSIMR_8822C */
+#define BIT_FS_PDNINT_EN_8822C BIT(31)
+#define BIT_FS_SPS_OCP_INT_EN_8822C BIT(29)
+#define BIT_FS_PWMERR_INT_EN_8822C BIT(28)
+#define BIT_FS_GPIOF_INT_EN_8822C BIT(27)
+#define BIT_FS_GPIOE_INT_EN_8822C BIT(26)
+#define BIT_FS_GPIOD_INT_EN_8822C BIT(25)
+#define BIT_FS_GPIOC_INT_EN_8822C BIT(24)
+#define BIT_FS_GPIOB_INT_EN_8822C BIT(23)
+#define BIT_FS_GPIOA_INT_EN_8822C BIT(22)
+#define BIT_FS_GPIO9_INT_EN_8822C BIT(21)
+#define BIT_FS_GPIO8_INT_EN_8822C BIT(20)
+#define BIT_FS_GPIO7_INT_EN_8822C BIT(19)
+#define BIT_FS_GPIO6_INT_EN_8822C BIT(18)
+#define BIT_FS_GPIO5_INT_EN_8822C BIT(17)
+#define BIT_FS_GPIO4_INT_EN_8822C BIT(16)
+#define BIT_FS_GPIO3_INT_EN_8822C BIT(15)
+#define BIT_FS_GPIO2_INT_EN_8822C BIT(14)
+#define BIT_FS_GPIO1_INT_EN_8822C BIT(13)
+#define BIT_FS_GPIO0_INT_EN_8822C BIT(12)
+#define BIT_FS_HCI_SUS_EN_8822C BIT(11)
+#define BIT_FS_HCI_RES_EN_8822C BIT(10)
+#define BIT_FS_HCI_RESET_EN_8822C BIT(9)
+#define BIT_USB_SCSI_CMD_EN_8822C BIT(8)
+#define BIT_FS_BTON_STS_UPDATE_MSK_EN_8822C BIT(7)
+#define BIT_ACT2RECOVERY_INT_EN_V1_8822C BIT(6)
+#define BIT_GEN1GEN2_SWITCH_8822C BIT(5)
+#define BIT_HCI_TXDMA_REQ_HIMR_8822C BIT(4)
+#define BIT_FS_32K_LEAVE_SETTING_MAK_8822C BIT(3)
+#define BIT_FS_32K_ENTER_SETTING_MAK_8822C BIT(2)
+#define BIT_FS_USB_LPMRSM_MSK_8822C BIT(1)
+#define BIT_FS_USB_LPMINT_MSK_8822C BIT(0)
+
+/* 2 REG_FSISR_8822C */
+#define BIT_FS_PDNINT_8822C BIT(31)
+#define BIT_FS_SPS_OCP_INT_8822C BIT(29)
+#define BIT_FS_PWMERR_INT_8822C BIT(28)
+#define BIT_FS_GPIOF_INT_8822C BIT(27)
+#define BIT_FS_GPIOE_INT_8822C BIT(26)
+#define BIT_FS_GPIOD_INT_8822C BIT(25)
+#define BIT_FS_GPIOC_INT_8822C BIT(24)
+#define BIT_FS_GPIOB_INT_8822C BIT(23)
+#define BIT_FS_GPIOA_INT_8822C BIT(22)
+#define BIT_FS_GPIO9_INT_8822C BIT(21)
+#define BIT_FS_GPIO8_INT_8822C BIT(20)
+#define BIT_FS_GPIO7_INT_8822C BIT(19)
+#define BIT_FS_GPIO6_INT_8822C BIT(18)
+#define BIT_FS_GPIO5_INT_8822C BIT(17)
+#define BIT_FS_GPIO4_INT_8822C BIT(16)
+#define BIT_FS_GPIO3_INT_8822C BIT(15)
+#define BIT_FS_GPIO2_INT_8822C BIT(14)
+#define BIT_FS_GPIO1_INT_8822C BIT(13)
+#define BIT_FS_GPIO0_INT_8822C BIT(12)
+#define BIT_FS_HCI_SUS_INT_8822C BIT(11)
+#define BIT_FS_HCI_RES_INT_8822C BIT(10)
+#define BIT_FS_HCI_RESET_INT_8822C BIT(9)
+#define BIT_USB_SCSI_CMD_INT_8822C BIT(8)
+#define BIT_ACT2RECOVERY_8822C BIT(6)
+#define BIT_GEN1GEN2_SWITCH_8822C BIT(5)
+#define BIT_HCI_TXDMA_REQ_HISR_8822C BIT(4)
+#define BIT_FS_32K_LEAVE_SETTING_INT_8822C BIT(3)
+#define BIT_FS_32K_ENTER_SETTING_INT_8822C BIT(2)
+#define BIT_FS_USB_LPMRSM_INT_8822C BIT(1)
+#define BIT_FS_USB_LPMINT_INT_8822C BIT(0)
+
+/* 2 REG_HSIMR_8822C */
+#define BIT_GPIOF_INT_EN_8822C BIT(31)
+#define BIT_GPIOE_INT_EN_8822C BIT(30)
+#define BIT_GPIOD_INT_EN_8822C BIT(29)
+#define BIT_GPIOC_INT_EN_8822C BIT(28)
+#define BIT_GPIOB_INT_EN_8822C BIT(27)
+#define BIT_GPIOA_INT_EN_8822C BIT(26)
+#define BIT_GPIO9_INT_EN_8822C BIT(25)
+#define BIT_GPIO8_INT_EN_8822C BIT(24)
+#define BIT_GPIO7_INT_EN_8822C BIT(23)
+#define BIT_GPIO6_INT_EN_8822C BIT(22)
+#define BIT_GPIO5_INT_EN_8822C BIT(21)
+#define BIT_GPIO4_INT_EN_8822C BIT(20)
+#define BIT_GPIO3_INT_EN_8822C BIT(19)
+#define BIT_GPIO2_INT_EN_V1_8822C BIT(18)
+#define BIT_GPIO1_INT_EN_8822C BIT(17)
+#define BIT_GPIO0_INT_EN_8822C BIT(16)
+#define BIT_PDNINT_EN_8822C BIT(7)
+#define BIT_RON_INT_EN_8822C BIT(6)
+#define BIT_SPS_OCP_INT_EN_8822C BIT(5)
+#define BIT_GPIO15_0_INT_EN_8822C BIT(0)
+
+/* 2 REG_HSISR_8822C */
+#define BIT_GPIOF_INT_8822C BIT(31)
+#define BIT_GPIOE_INT_8822C BIT(30)
+#define BIT_GPIOD_INT_8822C BIT(29)
+#define BIT_GPIOC_INT_8822C BIT(28)
+#define BIT_GPIOB_INT_8822C BIT(27)
+#define BIT_GPIOA_INT_8822C BIT(26)
+#define BIT_GPIO9_INT_8822C BIT(25)
+#define BIT_GPIO8_INT_8822C BIT(24)
+#define BIT_GPIO7_INT_8822C BIT(23)
+#define BIT_GPIO6_INT_8822C BIT(22)
+#define BIT_GPIO5_INT_8822C BIT(21)
+#define BIT_GPIO4_INT_8822C BIT(20)
+#define BIT_GPIO3_INT_8822C BIT(19)
+#define BIT_GPIO2_INT_V1_8822C BIT(18)
+#define BIT_GPIO1_INT_8822C BIT(17)
+#define BIT_GPIO0_INT_8822C BIT(16)
+#define BIT_PDNINT_8822C BIT(7)
+#define BIT_RON_INT_8822C BIT(6)
+#define BIT_SPS_OCP_INT_8822C BIT(5)
+#define BIT_GPIO15_0_INT_8822C BIT(0)
+
+/* 2 REG_GPIO_EXT_CTRL_8822C */
+
+#define BIT_SHIFT_GPIO_MOD_15_TO_8_8822C 24
+#define BIT_MASK_GPIO_MOD_15_TO_8_8822C 0xff
+#define BIT_GPIO_MOD_15_TO_8_8822C(x)                                          \
+	(((x) & BIT_MASK_GPIO_MOD_15_TO_8_8822C)                               \
+	 << BIT_SHIFT_GPIO_MOD_15_TO_8_8822C)
+#define BITS_GPIO_MOD_15_TO_8_8822C                                            \
+	(BIT_MASK_GPIO_MOD_15_TO_8_8822C << BIT_SHIFT_GPIO_MOD_15_TO_8_8822C)
+#define BIT_CLEAR_GPIO_MOD_15_TO_8_8822C(x)                                    \
+	((x) & (~BITS_GPIO_MOD_15_TO_8_8822C))
+#define BIT_GET_GPIO_MOD_15_TO_8_8822C(x)                                      \
+	(((x) >> BIT_SHIFT_GPIO_MOD_15_TO_8_8822C) &                           \
+	 BIT_MASK_GPIO_MOD_15_TO_8_8822C)
+#define BIT_SET_GPIO_MOD_15_TO_8_8822C(x, v)                                   \
+	(BIT_CLEAR_GPIO_MOD_15_TO_8_8822C(x) | BIT_GPIO_MOD_15_TO_8_8822C(v))
+
+#define BIT_SHIFT_GPIO_IO_SEL_15_TO_8_8822C 16
+#define BIT_MASK_GPIO_IO_SEL_15_TO_8_8822C 0xff
+#define BIT_GPIO_IO_SEL_15_TO_8_8822C(x)                                       \
+	(((x) & BIT_MASK_GPIO_IO_SEL_15_TO_8_8822C)                            \
+	 << BIT_SHIFT_GPIO_IO_SEL_15_TO_8_8822C)
+#define BITS_GPIO_IO_SEL_15_TO_8_8822C                                         \
+	(BIT_MASK_GPIO_IO_SEL_15_TO_8_8822C                                    \
+	 << BIT_SHIFT_GPIO_IO_SEL_15_TO_8_8822C)
+#define BIT_CLEAR_GPIO_IO_SEL_15_TO_8_8822C(x)                                 \
+	((x) & (~BITS_GPIO_IO_SEL_15_TO_8_8822C))
+#define BIT_GET_GPIO_IO_SEL_15_TO_8_8822C(x)                                   \
+	(((x) >> BIT_SHIFT_GPIO_IO_SEL_15_TO_8_8822C) &                        \
+	 BIT_MASK_GPIO_IO_SEL_15_TO_8_8822C)
+#define BIT_SET_GPIO_IO_SEL_15_TO_8_8822C(x, v)                                \
+	(BIT_CLEAR_GPIO_IO_SEL_15_TO_8_8822C(x) |                              \
+	 BIT_GPIO_IO_SEL_15_TO_8_8822C(v))
+
+#define BIT_SHIFT_GPIO_OUT_15_TO_8_8822C 8
+#define BIT_MASK_GPIO_OUT_15_TO_8_8822C 0xff
+#define BIT_GPIO_OUT_15_TO_8_8822C(x)                                          \
+	(((x) & BIT_MASK_GPIO_OUT_15_TO_8_8822C)                               \
+	 << BIT_SHIFT_GPIO_OUT_15_TO_8_8822C)
+#define BITS_GPIO_OUT_15_TO_8_8822C                                            \
+	(BIT_MASK_GPIO_OUT_15_TO_8_8822C << BIT_SHIFT_GPIO_OUT_15_TO_8_8822C)
+#define BIT_CLEAR_GPIO_OUT_15_TO_8_8822C(x)                                    \
+	((x) & (~BITS_GPIO_OUT_15_TO_8_8822C))
+#define BIT_GET_GPIO_OUT_15_TO_8_8822C(x)                                      \
+	(((x) >> BIT_SHIFT_GPIO_OUT_15_TO_8_8822C) &                           \
+	 BIT_MASK_GPIO_OUT_15_TO_8_8822C)
+#define BIT_SET_GPIO_OUT_15_TO_8_8822C(x, v)                                   \
+	(BIT_CLEAR_GPIO_OUT_15_TO_8_8822C(x) | BIT_GPIO_OUT_15_TO_8_8822C(v))
+
+#define BIT_SHIFT_GPIO_IN_15_TO_8_8822C 0
+#define BIT_MASK_GPIO_IN_15_TO_8_8822C 0xff
+#define BIT_GPIO_IN_15_TO_8_8822C(x)                                           \
+	(((x) & BIT_MASK_GPIO_IN_15_TO_8_8822C)                                \
+	 << BIT_SHIFT_GPIO_IN_15_TO_8_8822C)
+#define BITS_GPIO_IN_15_TO_8_8822C                                             \
+	(BIT_MASK_GPIO_IN_15_TO_8_8822C << BIT_SHIFT_GPIO_IN_15_TO_8_8822C)
+#define BIT_CLEAR_GPIO_IN_15_TO_8_8822C(x) ((x) & (~BITS_GPIO_IN_15_TO_8_8822C))
+#define BIT_GET_GPIO_IN_15_TO_8_8822C(x)                                       \
+	(((x) >> BIT_SHIFT_GPIO_IN_15_TO_8_8822C) &                            \
+	 BIT_MASK_GPIO_IN_15_TO_8_8822C)
+#define BIT_SET_GPIO_IN_15_TO_8_8822C(x, v)                                    \
+	(BIT_CLEAR_GPIO_IN_15_TO_8_8822C(x) | BIT_GPIO_IN_15_TO_8_8822C(v))
+
+/* 2 REG_PAD_CTRL1_8822C */
+#define BIT_PAPE_WLBT_SEL_8822C BIT(29)
+#define BIT_LNAON_WLBT_SEL_8822C BIT(28)
+#define BIT_BT_BQB_GPIO_SEL_8822C BIT(27)
+#define BIT_BTGP_GPG3_FEN_8822C BIT(26)
+#define BIT_BTGP_GPG2_FEN_8822C BIT(25)
+#define BIT_BTGP_JTAG_EN_8822C BIT(24)
+#define BIT_XTAL_CLK_EXTARNAL_EN_8822C BIT(23)
+#define BIT_BTGP_UART0_EN_8822C BIT(22)
+#define BIT_BTGP_UART1_EN_8822C BIT(21)
+#define BIT_BTGP_SPI_EN_8822C BIT(20)
+#define BIT_BTGP_GPIO_E2_8822C BIT(19)
+#define BIT_BTGP_GPIO_EN_8822C BIT(18)
+
+#define BIT_SHIFT_BTGP_GPIO_SL_8822C 16
+#define BIT_MASK_BTGP_GPIO_SL_8822C 0x3
+#define BIT_BTGP_GPIO_SL_8822C(x)                                              \
+	(((x) & BIT_MASK_BTGP_GPIO_SL_8822C) << BIT_SHIFT_BTGP_GPIO_SL_8822C)
+#define BITS_BTGP_GPIO_SL_8822C                                                \
+	(BIT_MASK_BTGP_GPIO_SL_8822C << BIT_SHIFT_BTGP_GPIO_SL_8822C)
+#define BIT_CLEAR_BTGP_GPIO_SL_8822C(x) ((x) & (~BITS_BTGP_GPIO_SL_8822C))
+#define BIT_GET_BTGP_GPIO_SL_8822C(x)                                          \
+	(((x) >> BIT_SHIFT_BTGP_GPIO_SL_8822C) & BIT_MASK_BTGP_GPIO_SL_8822C)
+#define BIT_SET_BTGP_GPIO_SL_8822C(x, v)                                       \
+	(BIT_CLEAR_BTGP_GPIO_SL_8822C(x) | BIT_BTGP_GPIO_SL_8822C(v))
+
+#define BIT_PAD_SDIO_SR_8822C BIT(14)
+#define BIT_GPIO14_OUTPUT_PL_8822C BIT(13)
+#define BIT_HOST_WAKE_PAD_PULL_EN_8822C BIT(12)
+#define BIT_HOST_WAKE_PAD_SL_8822C BIT(11)
+#define BIT_PAD_LNAON_SR_8822C BIT(10)
+#define BIT_PAD_LNAON_E2_8822C BIT(9)
+#define BIT_SW_LNAON_G_SEL_DATA_8822C BIT(8)
+#define BIT_SW_LNAON_A_SEL_DATA_8822C BIT(7)
+#define BIT_PAD_PAPE_SR_8822C BIT(6)
+#define BIT_PAD_PAPE_E2_8822C BIT(5)
+#define BIT_SW_PAPE_G_SEL_DATA_8822C BIT(4)
+#define BIT_SW_PAPE_A_SEL_DATA_8822C BIT(3)
+#define BIT_PAD_DPDT_SR_8822C BIT(2)
+#define BIT_PAD_DPDT_PAD_E2_8822C BIT(1)
+#define BIT_SW_DPDT_SEL_DATA_8822C BIT(0)
+
+/* 2 REG_WL_BT_PWR_CTRL_8822C */
+#define BIT_ISO_BD2PP_8822C BIT(31)
+#define BIT_LDOV12B_EN_8822C BIT(30)
+#define BIT_CKEN_BTGPS_8822C BIT(29)
+#define BIT_FEN_BTGPS_8822C BIT(28)
+#define BIT_BTCPU_BOOTSEL_8822C BIT(27)
+#define BIT_SPI_SPEEDUP_8822C BIT(26)
+#define BIT_BT_LDO_MODE_8822C BIT(25)
+#define BIT_DEVWAKE_PAD_TYPE_SEL_8822C BIT(24)
+#define BIT_CLKREQ_PAD_TYPE_SEL_8822C BIT(23)
+#define BIT_ISO_BTPON2PP_8822C BIT(22)
+#define BIT_BT_HWROF_EN_8822C BIT(19)
+#define BIT_BT_FUNC_EN_8822C BIT(18)
+#define BIT_BT_HWPDN_SL_8822C BIT(17)
+#define BIT_BT_DISN_EN_8822C BIT(16)
+#define BIT_BT_PDN_PULL_EN_8822C BIT(15)
+#define BIT_WL_PDN_PULL_EN_8822C BIT(14)
+#define BIT_EXTERNAL_REQUEST_PL_8822C BIT(13)
+#define BIT_GPIO0_2_3_PULL_LOW_EN_8822C BIT(12)
+#define BIT_ISO_BA2PP_8822C BIT(11)
+#define BIT_BT_AFE_LDO_EN_8822C BIT(10)
+#define BIT_BT_AFE_PLL_EN_8822C BIT(9)
+#define BIT_BT_DIG_CLK_EN_8822C BIT(8)
+#define BIT_WLAN_32K_SEL_8822C BIT(6)
+#define BIT_WL_DRV_EXIST_IDX_8822C BIT(5)
+#define BIT_DOP_EHPAD_8822C BIT(4)
+#define BIT_WL_HWROF_EN_8822C BIT(3)
+#define BIT_WL_FUNC_EN_8822C BIT(2)
+#define BIT_WL_HWPDN_SL_8822C BIT(1)
+#define BIT_WL_HWPDN_EN_8822C BIT(0)
+
+/* 2 REG_SDM_DEBUG_8822C */
+#define BIT_GPIO_IE_V18_8822C BIT(10)
+#define BIT_PCIE_IE_V18_8822C BIT(9)
+#define BIT_UART_IE_V18_8822C BIT(8)
+
+/* 2 REG_NOT_VALID_8822C */
+
+#define BIT_SHIFT_WLCLK_PHASE_8822C 0
+#define BIT_MASK_WLCLK_PHASE_8822C 0x1f
+#define BIT_WLCLK_PHASE_8822C(x)                                               \
+	(((x) & BIT_MASK_WLCLK_PHASE_8822C) << BIT_SHIFT_WLCLK_PHASE_8822C)
+#define BITS_WLCLK_PHASE_8822C                                                 \
+	(BIT_MASK_WLCLK_PHASE_8822C << BIT_SHIFT_WLCLK_PHASE_8822C)
+#define BIT_CLEAR_WLCLK_PHASE_8822C(x) ((x) & (~BITS_WLCLK_PHASE_8822C))
+#define BIT_GET_WLCLK_PHASE_8822C(x)                                           \
+	(((x) >> BIT_SHIFT_WLCLK_PHASE_8822C) & BIT_MASK_WLCLK_PHASE_8822C)
+#define BIT_SET_WLCLK_PHASE_8822C(x, v)                                        \
+	(BIT_CLEAR_WLCLK_PHASE_8822C(x) | BIT_WLCLK_PHASE_8822C(v))
+
+/* 2 REG_SYS_SDIO_CTRL_8822C */
+#define BIT_DBG_GNT_WL_BT_8822C BIT(27)
+#define BIT_LTE_MUX_CTRL_PATH_8822C BIT(26)
+#define BIT_LTE_COEX_UART_8822C BIT(25)
+#define BIT_3W_LTE_WL_GPIO_8822C BIT(24)
+#define BIT_SDIO_INT_POLARITY_8822C BIT(19)
+#define BIT_SDIO_INT_8822C BIT(18)
+#define BIT_SDIO_OFF_EN_8822C BIT(17)
+#define BIT_SDIO_ON_EN_8822C BIT(16)
+#define BIT_PCIE_FORCE_PWR_NGAT_8822C BIT(13)
+#define BIT_PCIE_CALIB_EN_V1_8822C BIT(12)
+#define BIT_PAGE3_AUXCLK_GATE_8822C BIT(11)
+#define BIT_PCIE_WAIT_TIMEOUT_EVENT_8822C BIT(10)
+#define BIT_PCIE_WAIT_TIME_8822C BIT(9)
+#define BIT_MPCIE_REFCLK_XTAL_SEL_8822C BIT(8)
+#define BIT_BT_CTRL_USB_PWR_BACKDOOR_8822C BIT(5)
+#define BIT_USB_D_STATE_HOLD_8822C BIT(4)
+#define BIT_REG_FORCE_DP_8822C BIT(3)
+#define BIT_REG_DP_MODE_8822C BIT(2)
+#define BIT_RES_USB_MASS_STORAGE_DESC_8822C BIT(1)
+#define BIT_USB_WAIT_TIME_8822C BIT(0)
+
+/* 2 REG_HCI_OPT_CTRL_8822C */
+
+#define BIT_SHIFT_TSFT_SEL_8822C 29
+#define BIT_MASK_TSFT_SEL_8822C 0x7
+#define BIT_TSFT_SEL_8822C(x)                                                  \
+	(((x) & BIT_MASK_TSFT_SEL_8822C) << BIT_SHIFT_TSFT_SEL_8822C)
+#define BITS_TSFT_SEL_8822C                                                    \
+	(BIT_MASK_TSFT_SEL_8822C << BIT_SHIFT_TSFT_SEL_8822C)
+#define BIT_CLEAR_TSFT_SEL_8822C(x) ((x) & (~BITS_TSFT_SEL_8822C))
+#define BIT_GET_TSFT_SEL_8822C(x)                                              \
+	(((x) >> BIT_SHIFT_TSFT_SEL_8822C) & BIT_MASK_TSFT_SEL_8822C)
+#define BIT_SET_TSFT_SEL_8822C(x, v)                                           \
+	(BIT_CLEAR_TSFT_SEL_8822C(x) | BIT_TSFT_SEL_8822C(v))
+
+#define BIT_SDIO_PAD_E5_8822C BIT(18)
+#define BIT_USB_HOST_PWR_OFF_EN_8822C BIT(12)
+#define BIT_SYM_LPS_BLOCK_EN_8822C BIT(11)
+#define BIT_USB_LPM_ACT_EN_8822C BIT(10)
+#define BIT_USB_LPM_NY_8822C BIT(9)
+#define BIT_USB_SUS_DIS_8822C BIT(8)
+
+#define BIT_SHIFT_SDIO_PAD_E_8822C 5
+#define BIT_MASK_SDIO_PAD_E_8822C 0x7
+#define BIT_SDIO_PAD_E_8822C(x)                                                \
+	(((x) & BIT_MASK_SDIO_PAD_E_8822C) << BIT_SHIFT_SDIO_PAD_E_8822C)
+#define BITS_SDIO_PAD_E_8822C                                                  \
+	(BIT_MASK_SDIO_PAD_E_8822C << BIT_SHIFT_SDIO_PAD_E_8822C)
+#define BIT_CLEAR_SDIO_PAD_E_8822C(x) ((x) & (~BITS_SDIO_PAD_E_8822C))
+#define BIT_GET_SDIO_PAD_E_8822C(x)                                            \
+	(((x) >> BIT_SHIFT_SDIO_PAD_E_8822C) & BIT_MASK_SDIO_PAD_E_8822C)
+#define BIT_SET_SDIO_PAD_E_8822C(x, v)                                         \
+	(BIT_CLEAR_SDIO_PAD_E_8822C(x) | BIT_SDIO_PAD_E_8822C(v))
+
+#define BIT_USB_LPPLL_EN_8822C BIT(4)
+#define BIT_USB1_1_USB2_0_DECISION_8822C BIT(3)
+#define BIT_ROP_SW15_8822C BIT(2)
+#define BIT_PCI_CKRDY_OPT_8822C BIT(1)
+#define BIT_PCI_VAUX_EN_8822C BIT(0)
+
+/* 2 REG_HCI_BG_CTRL_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+#define BIT_IBX_EN_VALUE_8822C BIT(9)
+#define BIT_IB_EN_VALUE_8822C BIT(8)
+
+/* 2 REG_NOT_VALID_8822C */
+#define BIT_FORCED_IB_EN_8822C BIT(4)
+#define BIT_EN_REGBG_8822C BIT(3)
+#define BIT_REG_BG_LPF_8822C BIT(2)
+
+#define BIT_SHIFT_REG_BG_8822C 0
+#define BIT_MASK_REG_BG_8822C 0x3
+#define BIT_REG_BG_8822C(x)                                                    \
+	(((x) & BIT_MASK_REG_BG_8822C) << BIT_SHIFT_REG_BG_8822C)
+#define BITS_REG_BG_8822C (BIT_MASK_REG_BG_8822C << BIT_SHIFT_REG_BG_8822C)
+#define BIT_CLEAR_REG_BG_8822C(x) ((x) & (~BITS_REG_BG_8822C))
+#define BIT_GET_REG_BG_8822C(x)                                                \
+	(((x) >> BIT_SHIFT_REG_BG_8822C) & BIT_MASK_REG_BG_8822C)
+#define BIT_SET_REG_BG_8822C(x, v)                                             \
+	(BIT_CLEAR_REG_BG_8822C(x) | BIT_REG_BG_8822C(v))
+
+/* 2 REG_HCI_LDO_CTRL_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+#define BIT_EN_LW_PWR_8822C BIT(6)
+#define BIT_EN_REGU_8822C BIT(5)
+#define BIT_EN_PC_8822C BIT(4)
+
+#define BIT_SHIFT_REG_VADJ_8822C 0
+#define BIT_MASK_REG_VADJ_8822C 0xf
+#define BIT_REG_VADJ_8822C(x)                                                  \
+	(((x) & BIT_MASK_REG_VADJ_8822C) << BIT_SHIFT_REG_VADJ_8822C)
+#define BITS_REG_VADJ_8822C                                                    \
+	(BIT_MASK_REG_VADJ_8822C << BIT_SHIFT_REG_VADJ_8822C)
+#define BIT_CLEAR_REG_VADJ_8822C(x) ((x) & (~BITS_REG_VADJ_8822C))
+#define BIT_GET_REG_VADJ_8822C(x)                                              \
+	(((x) >> BIT_SHIFT_REG_VADJ_8822C) & BIT_MASK_REG_VADJ_8822C)
+#define BIT_SET_REG_VADJ_8822C(x, v)                                           \
+	(BIT_CLEAR_REG_VADJ_8822C(x) | BIT_REG_VADJ_8822C(v))
+
+/* 2 REG_LDO_SWR_CTRL_8822C */
+#define BIT_EXT_SWR_CTRL_EN_8822C BIT(31)
+#define BIT_ZCD_HW_AUTO_EN_8822C BIT(27)
+#define BIT_ZCD_REGSEL_8822C BIT(26)
+
+#define BIT_SHIFT_AUTO_ZCD_IN_CODE_8822C 21
+#define BIT_MASK_AUTO_ZCD_IN_CODE_8822C 0x1f
+#define BIT_AUTO_ZCD_IN_CODE_8822C(x)                                          \
+	(((x) & BIT_MASK_AUTO_ZCD_IN_CODE_8822C)                               \
+	 << BIT_SHIFT_AUTO_ZCD_IN_CODE_8822C)
+#define BITS_AUTO_ZCD_IN_CODE_8822C                                            \
+	(BIT_MASK_AUTO_ZCD_IN_CODE_8822C << BIT_SHIFT_AUTO_ZCD_IN_CODE_8822C)
+#define BIT_CLEAR_AUTO_ZCD_IN_CODE_8822C(x)                                    \
+	((x) & (~BITS_AUTO_ZCD_IN_CODE_8822C))
+#define BIT_GET_AUTO_ZCD_IN_CODE_8822C(x)                                      \
+	(((x) >> BIT_SHIFT_AUTO_ZCD_IN_CODE_8822C) &                           \
+	 BIT_MASK_AUTO_ZCD_IN_CODE_8822C)
+#define BIT_SET_AUTO_ZCD_IN_CODE_8822C(x, v)                                   \
+	(BIT_CLEAR_AUTO_ZCD_IN_CODE_8822C(x) | BIT_AUTO_ZCD_IN_CODE_8822C(v))
+
+#define BIT_SHIFT_ZCD_CODE_IN_L_8822C 16
+#define BIT_MASK_ZCD_CODE_IN_L_8822C 0x1f
+#define BIT_ZCD_CODE_IN_L_8822C(x)                                             \
+	(((x) & BIT_MASK_ZCD_CODE_IN_L_8822C) << BIT_SHIFT_ZCD_CODE_IN_L_8822C)
+#define BITS_ZCD_CODE_IN_L_8822C                                               \
+	(BIT_MASK_ZCD_CODE_IN_L_8822C << BIT_SHIFT_ZCD_CODE_IN_L_8822C)
+#define BIT_CLEAR_ZCD_CODE_IN_L_8822C(x) ((x) & (~BITS_ZCD_CODE_IN_L_8822C))
+#define BIT_GET_ZCD_CODE_IN_L_8822C(x)                                         \
+	(((x) >> BIT_SHIFT_ZCD_CODE_IN_L_8822C) & BIT_MASK_ZCD_CODE_IN_L_8822C)
+#define BIT_SET_ZCD_CODE_IN_L_8822C(x, v)                                      \
+	(BIT_CLEAR_ZCD_CODE_IN_L_8822C(x) | BIT_ZCD_CODE_IN_L_8822C(v))
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_MCUFW_CTRL_8822C */
+
+#define BIT_SHIFT_RPWM_8822C 24
+#define BIT_MASK_RPWM_8822C 0xff
+#define BIT_RPWM_8822C(x) (((x) & BIT_MASK_RPWM_8822C) << BIT_SHIFT_RPWM_8822C)
+#define BITS_RPWM_8822C (BIT_MASK_RPWM_8822C << BIT_SHIFT_RPWM_8822C)
+#define BIT_CLEAR_RPWM_8822C(x) ((x) & (~BITS_RPWM_8822C))
+#define BIT_GET_RPWM_8822C(x)                                                  \
+	(((x) >> BIT_SHIFT_RPWM_8822C) & BIT_MASK_RPWM_8822C)
+#define BIT_SET_RPWM_8822C(x, v) (BIT_CLEAR_RPWM_8822C(x) | BIT_RPWM_8822C(v))
+
+#define BIT_ANA_PORT_EN_8822C BIT(22)
+#define BIT_MAC_PORT_EN_8822C BIT(21)
+#define BIT_BOOT_FSPI_EN_8822C BIT(20)
+#define BIT_ROM_DLEN_8822C BIT(19)
+
+#define BIT_SHIFT_ROM_PGE_8822C 16
+#define BIT_MASK_ROM_PGE_8822C 0x7
+#define BIT_ROM_PGE_8822C(x)                                                   \
+	(((x) & BIT_MASK_ROM_PGE_8822C) << BIT_SHIFT_ROM_PGE_8822C)
+#define BITS_ROM_PGE_8822C (BIT_MASK_ROM_PGE_8822C << BIT_SHIFT_ROM_PGE_8822C)
+#define BIT_CLEAR_ROM_PGE_8822C(x) ((x) & (~BITS_ROM_PGE_8822C))
+#define BIT_GET_ROM_PGE_8822C(x)                                               \
+	(((x) >> BIT_SHIFT_ROM_PGE_8822C) & BIT_MASK_ROM_PGE_8822C)
+#define BIT_SET_ROM_PGE_8822C(x, v)                                            \
+	(BIT_CLEAR_ROM_PGE_8822C(x) | BIT_ROM_PGE_8822C(v))
+
+#define BIT_FW_INIT_RDY_8822C BIT(15)
+#define BIT_FW_DW_RDY_8822C BIT(14)
+
+#define BIT_SHIFT_CPU_CLK_SEL_8822C 12
+#define BIT_MASK_CPU_CLK_SEL_8822C 0x3
+#define BIT_CPU_CLK_SEL_8822C(x)                                               \
+	(((x) & BIT_MASK_CPU_CLK_SEL_8822C) << BIT_SHIFT_CPU_CLK_SEL_8822C)
+#define BITS_CPU_CLK_SEL_8822C                                                 \
+	(BIT_MASK_CPU_CLK_SEL_8822C << BIT_SHIFT_CPU_CLK_SEL_8822C)
+#define BIT_CLEAR_CPU_CLK_SEL_8822C(x) ((x) & (~BITS_CPU_CLK_SEL_8822C))
+#define BIT_GET_CPU_CLK_SEL_8822C(x)                                           \
+	(((x) >> BIT_SHIFT_CPU_CLK_SEL_8822C) & BIT_MASK_CPU_CLK_SEL_8822C)
+#define BIT_SET_CPU_CLK_SEL_8822C(x, v)                                        \
+	(BIT_CLEAR_CPU_CLK_SEL_8822C(x) | BIT_CPU_CLK_SEL_8822C(v))
+
+#define BIT_CCLK_CHG_MASK_8822C BIT(11)
+#define BIT_EMEM__TXBUF_CHKSUM_OK_8822C BIT(10)
+#define BIT_EMEM_TXBUF_DW_RDY_8822C BIT(9)
+#define BIT_EMEM_CHKSUM_OK_8822C BIT(8)
+#define BIT_EMEM_DW_OK_8822C BIT(7)
+#define BIT_DMEM_CHKSUM_OK_8822C BIT(6)
+#define BIT_DMEM_DW_OK_8822C BIT(5)
+#define BIT_IMEM_CHKSUM_OK_8822C BIT(4)
+#define BIT_IMEM_DW_OK_8822C BIT(3)
+#define BIT_IMEM_BOOT_LOAD_CHKSUM_OK_8822C BIT(2)
+#define BIT_IMEM_BOOT_LOAD_DW_OK_8822C BIT(1)
+#define BIT_MCUFWDL_EN_8822C BIT(0)
+
+/* 2 REG_MCU_TST_CFG_8822C */
+
+#define BIT_SHIFT_LBKTST_8822C 0
+#define BIT_MASK_LBKTST_8822C 0xffff
+#define BIT_LBKTST_8822C(x)                                                    \
+	(((x) & BIT_MASK_LBKTST_8822C) << BIT_SHIFT_LBKTST_8822C)
+#define BITS_LBKTST_8822C (BIT_MASK_LBKTST_8822C << BIT_SHIFT_LBKTST_8822C)
+#define BIT_CLEAR_LBKTST_8822C(x) ((x) & (~BITS_LBKTST_8822C))
+#define BIT_GET_LBKTST_8822C(x)                                                \
+	(((x) >> BIT_SHIFT_LBKTST_8822C) & BIT_MASK_LBKTST_8822C)
+#define BIT_SET_LBKTST_8822C(x, v)                                             \
+	(BIT_CLEAR_LBKTST_8822C(x) | BIT_LBKTST_8822C(v))
+
+/* 2 REG_HMEBOX_E0_E1_8822C */
+
+#define BIT_SHIFT_HOST_MSG_E1_8822C 16
+#define BIT_MASK_HOST_MSG_E1_8822C 0xffff
+#define BIT_HOST_MSG_E1_8822C(x)                                               \
+	(((x) & BIT_MASK_HOST_MSG_E1_8822C) << BIT_SHIFT_HOST_MSG_E1_8822C)
+#define BITS_HOST_MSG_E1_8822C                                                 \
+	(BIT_MASK_HOST_MSG_E1_8822C << BIT_SHIFT_HOST_MSG_E1_8822C)
+#define BIT_CLEAR_HOST_MSG_E1_8822C(x) ((x) & (~BITS_HOST_MSG_E1_8822C))
+#define BIT_GET_HOST_MSG_E1_8822C(x)                                           \
+	(((x) >> BIT_SHIFT_HOST_MSG_E1_8822C) & BIT_MASK_HOST_MSG_E1_8822C)
+#define BIT_SET_HOST_MSG_E1_8822C(x, v)                                        \
+	(BIT_CLEAR_HOST_MSG_E1_8822C(x) | BIT_HOST_MSG_E1_8822C(v))
+
+#define BIT_SHIFT_HOST_MSG_E0_8822C 0
+#define BIT_MASK_HOST_MSG_E0_8822C 0xffff
+#define BIT_HOST_MSG_E0_8822C(x)                                               \
+	(((x) & BIT_MASK_HOST_MSG_E0_8822C) << BIT_SHIFT_HOST_MSG_E0_8822C)
+#define BITS_HOST_MSG_E0_8822C                                                 \
+	(BIT_MASK_HOST_MSG_E0_8822C << BIT_SHIFT_HOST_MSG_E0_8822C)
+#define BIT_CLEAR_HOST_MSG_E0_8822C(x) ((x) & (~BITS_HOST_MSG_E0_8822C))
+#define BIT_GET_HOST_MSG_E0_8822C(x)                                           \
+	(((x) >> BIT_SHIFT_HOST_MSG_E0_8822C) & BIT_MASK_HOST_MSG_E0_8822C)
+#define BIT_SET_HOST_MSG_E0_8822C(x, v)                                        \
+	(BIT_CLEAR_HOST_MSG_E0_8822C(x) | BIT_HOST_MSG_E0_8822C(v))
+
+/* 2 REG_HMEBOX_E2_E3_8822C */
+
+#define BIT_SHIFT_HOST_MSG_E3_8822C 16
+#define BIT_MASK_HOST_MSG_E3_8822C 0xffff
+#define BIT_HOST_MSG_E3_8822C(x)                                               \
+	(((x) & BIT_MASK_HOST_MSG_E3_8822C) << BIT_SHIFT_HOST_MSG_E3_8822C)
+#define BITS_HOST_MSG_E3_8822C                                                 \
+	(BIT_MASK_HOST_MSG_E3_8822C << BIT_SHIFT_HOST_MSG_E3_8822C)
+#define BIT_CLEAR_HOST_MSG_E3_8822C(x) ((x) & (~BITS_HOST_MSG_E3_8822C))
+#define BIT_GET_HOST_MSG_E3_8822C(x)                                           \
+	(((x) >> BIT_SHIFT_HOST_MSG_E3_8822C) & BIT_MASK_HOST_MSG_E3_8822C)
+#define BIT_SET_HOST_MSG_E3_8822C(x, v)                                        \
+	(BIT_CLEAR_HOST_MSG_E3_8822C(x) | BIT_HOST_MSG_E3_8822C(v))
+
+#define BIT_SHIFT_HOST_MSG_E2_8822C 0
+#define BIT_MASK_HOST_MSG_E2_8822C 0xffff
+#define BIT_HOST_MSG_E2_8822C(x)                                               \
+	(((x) & BIT_MASK_HOST_MSG_E2_8822C) << BIT_SHIFT_HOST_MSG_E2_8822C)
+#define BITS_HOST_MSG_E2_8822C                                                 \
+	(BIT_MASK_HOST_MSG_E2_8822C << BIT_SHIFT_HOST_MSG_E2_8822C)
+#define BIT_CLEAR_HOST_MSG_E2_8822C(x) ((x) & (~BITS_HOST_MSG_E2_8822C))
+#define BIT_GET_HOST_MSG_E2_8822C(x)                                           \
+	(((x) >> BIT_SHIFT_HOST_MSG_E2_8822C) & BIT_MASK_HOST_MSG_E2_8822C)
+#define BIT_SET_HOST_MSG_E2_8822C(x, v)                                        \
+	(BIT_CLEAR_HOST_MSG_E2_8822C(x) | BIT_HOST_MSG_E2_8822C(v))
+
+/* 2 REG_WLLPS_CTRL_8822C */
+#define BIT_WLLPSOP_EABM_8822C BIT(31)
+#define BIT_WLLPSOP_ACKF_8822C BIT(30)
+#define BIT_WLLPSOP_DLDM_8822C BIT(29)
+#define BIT_WLLPSOP_ESWR_8822C BIT(28)
+#define BIT_WLLPSOP_PWMM_8822C BIT(27)
+#define BIT_WLLPSOP_EECK_8822C BIT(26)
+#define BIT_WLLPSOP_WLMACOFF_8822C BIT(25)
+#define BIT_WLLPSOP_EXTAL_8822C BIT(24)
+#define BIT_WL_SYNPON_VOLTSPDN_8822C BIT(23)
+#define BIT_WLLPSOP_WLBBOFF_8822C BIT(22)
+#define BIT_WLLPSOP_WLMEM_DS_8822C BIT(21)
+#define BIT_WLLPSOP_LDO_WAIT_TIME_8822C BIT(20)
+#define BIT_WLLPSOP_ANA_CLK_DIVISION_2_8822C BIT(19)
+#define BIT_AFE_BCN_8822C BIT(18)
+
+#define BIT_SHIFT_LPLDH12_VADJ_STEP_DN_8822C 12
+#define BIT_MASK_LPLDH12_VADJ_STEP_DN_8822C 0xf
+#define BIT_LPLDH12_VADJ_STEP_DN_8822C(x)                                      \
+	(((x) & BIT_MASK_LPLDH12_VADJ_STEP_DN_8822C)                           \
+	 << BIT_SHIFT_LPLDH12_VADJ_STEP_DN_8822C)
+#define BITS_LPLDH12_VADJ_STEP_DN_8822C                                        \
+	(BIT_MASK_LPLDH12_VADJ_STEP_DN_8822C                                   \
+	 << BIT_SHIFT_LPLDH12_VADJ_STEP_DN_8822C)
+#define BIT_CLEAR_LPLDH12_VADJ_STEP_DN_8822C(x)                                \
+	((x) & (~BITS_LPLDH12_VADJ_STEP_DN_8822C))
+#define BIT_GET_LPLDH12_VADJ_STEP_DN_8822C(x)                                  \
+	(((x) >> BIT_SHIFT_LPLDH12_VADJ_STEP_DN_8822C) &                       \
+	 BIT_MASK_LPLDH12_VADJ_STEP_DN_8822C)
+#define BIT_SET_LPLDH12_VADJ_STEP_DN_8822C(x, v)                               \
+	(BIT_CLEAR_LPLDH12_VADJ_STEP_DN_8822C(x) |                             \
+	 BIT_LPLDH12_VADJ_STEP_DN_8822C(v))
+
+#define BIT_SHIFT_V15ADJ_L1_STEP_DN_V1_8822C 8
+#define BIT_MASK_V15ADJ_L1_STEP_DN_V1_8822C 0xf
+#define BIT_V15ADJ_L1_STEP_DN_V1_8822C(x)                                      \
+	(((x) & BIT_MASK_V15ADJ_L1_STEP_DN_V1_8822C)                           \
+	 << BIT_SHIFT_V15ADJ_L1_STEP_DN_V1_8822C)
+#define BITS_V15ADJ_L1_STEP_DN_V1_8822C                                        \
+	(BIT_MASK_V15ADJ_L1_STEP_DN_V1_8822C                                   \
+	 << BIT_SHIFT_V15ADJ_L1_STEP_DN_V1_8822C)
+#define BIT_CLEAR_V15ADJ_L1_STEP_DN_V1_8822C(x)                                \
+	((x) & (~BITS_V15ADJ_L1_STEP_DN_V1_8822C))
+#define BIT_GET_V15ADJ_L1_STEP_DN_V1_8822C(x)                                  \
+	(((x) >> BIT_SHIFT_V15ADJ_L1_STEP_DN_V1_8822C) &                       \
+	 BIT_MASK_V15ADJ_L1_STEP_DN_V1_8822C)
+#define BIT_SET_V15ADJ_L1_STEP_DN_V1_8822C(x, v)                               \
+	(BIT_CLEAR_V15ADJ_L1_STEP_DN_V1_8822C(x) |                             \
+	 BIT_V15ADJ_L1_STEP_DN_V1_8822C(v))
+
+#define BIT_FORCE_LEAVE_LPS_8822C BIT(3)
+#define BIT_SW_AFE_MODE_8822C BIT(2)
+#define BIT_REGU_32K_CLK_EN_8822C BIT(1)
+#define BIT_WL_LPS_EN_8822C BIT(0)
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_GPIO_DEBOUNCE_CTRL_8822C */
+#define BIT_WLGP_DBC1EN_8822C BIT(15)
+
+#define BIT_SHIFT_WLGP_DBC1_8822C 8
+#define BIT_MASK_WLGP_DBC1_8822C 0xf
+#define BIT_WLGP_DBC1_8822C(x)                                                 \
+	(((x) & BIT_MASK_WLGP_DBC1_8822C) << BIT_SHIFT_WLGP_DBC1_8822C)
+#define BITS_WLGP_DBC1_8822C                                                   \
+	(BIT_MASK_WLGP_DBC1_8822C << BIT_SHIFT_WLGP_DBC1_8822C)
+#define BIT_CLEAR_WLGP_DBC1_8822C(x) ((x) & (~BITS_WLGP_DBC1_8822C))
+#define BIT_GET_WLGP_DBC1_8822C(x)                                             \
+	(((x) >> BIT_SHIFT_WLGP_DBC1_8822C) & BIT_MASK_WLGP_DBC1_8822C)
+#define BIT_SET_WLGP_DBC1_8822C(x, v)                                          \
+	(BIT_CLEAR_WLGP_DBC1_8822C(x) | BIT_WLGP_DBC1_8822C(v))
+
+#define BIT_WLGP_DBC0EN_8822C BIT(7)
+
+#define BIT_SHIFT_WLGP_DBC0_8822C 0
+#define BIT_MASK_WLGP_DBC0_8822C 0xf
+#define BIT_WLGP_DBC0_8822C(x)                                                 \
+	(((x) & BIT_MASK_WLGP_DBC0_8822C) << BIT_SHIFT_WLGP_DBC0_8822C)
+#define BITS_WLGP_DBC0_8822C                                                   \
+	(BIT_MASK_WLGP_DBC0_8822C << BIT_SHIFT_WLGP_DBC0_8822C)
+#define BIT_CLEAR_WLGP_DBC0_8822C(x) ((x) & (~BITS_WLGP_DBC0_8822C))
+#define BIT_GET_WLGP_DBC0_8822C(x)                                             \
+	(((x) >> BIT_SHIFT_WLGP_DBC0_8822C) & BIT_MASK_WLGP_DBC0_8822C)
+#define BIT_SET_WLGP_DBC0_8822C(x, v)                                          \
+	(BIT_CLEAR_WLGP_DBC0_8822C(x) | BIT_WLGP_DBC0_8822C(v))
+
+/* 2 REG_RPWM2_8822C */
+
+#define BIT_SHIFT_RPWM2_8822C 16
+#define BIT_MASK_RPWM2_8822C 0xffff
+#define BIT_RPWM2_8822C(x)                                                     \
+	(((x) & BIT_MASK_RPWM2_8822C) << BIT_SHIFT_RPWM2_8822C)
+#define BITS_RPWM2_8822C (BIT_MASK_RPWM2_8822C << BIT_SHIFT_RPWM2_8822C)
+#define BIT_CLEAR_RPWM2_8822C(x) ((x) & (~BITS_RPWM2_8822C))
+#define BIT_GET_RPWM2_8822C(x)                                                 \
+	(((x) >> BIT_SHIFT_RPWM2_8822C) & BIT_MASK_RPWM2_8822C)
+#define BIT_SET_RPWM2_8822C(x, v)                                              \
+	(BIT_CLEAR_RPWM2_8822C(x) | BIT_RPWM2_8822C(v))
+
+/* 2 REG_SYSON_FSM_MON_8822C */
+
+#define BIT_SHIFT_FSM_MON_SEL_8822C 24
+#define BIT_MASK_FSM_MON_SEL_8822C 0x7
+#define BIT_FSM_MON_SEL_8822C(x)                                               \
+	(((x) & BIT_MASK_FSM_MON_SEL_8822C) << BIT_SHIFT_FSM_MON_SEL_8822C)
+#define BITS_FSM_MON_SEL_8822C                                                 \
+	(BIT_MASK_FSM_MON_SEL_8822C << BIT_SHIFT_FSM_MON_SEL_8822C)
+#define BIT_CLEAR_FSM_MON_SEL_8822C(x) ((x) & (~BITS_FSM_MON_SEL_8822C))
+#define BIT_GET_FSM_MON_SEL_8822C(x)                                           \
+	(((x) >> BIT_SHIFT_FSM_MON_SEL_8822C) & BIT_MASK_FSM_MON_SEL_8822C)
+#define BIT_SET_FSM_MON_SEL_8822C(x, v)                                        \
+	(BIT_CLEAR_FSM_MON_SEL_8822C(x) | BIT_FSM_MON_SEL_8822C(v))
+
+#define BIT_DOP_ELDO_8822C BIT(23)
+#define BIT_FSM_MON_UPD_8822C BIT(15)
+
+#define BIT_SHIFT_FSM_PAR_8822C 0
+#define BIT_MASK_FSM_PAR_8822C 0x7fff
+#define BIT_FSM_PAR_8822C(x)                                                   \
+	(((x) & BIT_MASK_FSM_PAR_8822C) << BIT_SHIFT_FSM_PAR_8822C)
+#define BITS_FSM_PAR_8822C (BIT_MASK_FSM_PAR_8822C << BIT_SHIFT_FSM_PAR_8822C)
+#define BIT_CLEAR_FSM_PAR_8822C(x) ((x) & (~BITS_FSM_PAR_8822C))
+#define BIT_GET_FSM_PAR_8822C(x)                                               \
+	(((x) >> BIT_SHIFT_FSM_PAR_8822C) & BIT_MASK_FSM_PAR_8822C)
+#define BIT_SET_FSM_PAR_8822C(x, v)                                            \
+	(BIT_CLEAR_FSM_PAR_8822C(x) | BIT_FSM_PAR_8822C(v))
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_PMC_DBG_CTRL1_8822C */
+#define BIT_BT_INT_EN_8822C BIT(31)
+
+#define BIT_SHIFT_RD_WR_WIFI_BT_INFO_8822C 16
+#define BIT_MASK_RD_WR_WIFI_BT_INFO_8822C 0x7fff
+#define BIT_RD_WR_WIFI_BT_INFO_8822C(x)                                        \
+	(((x) & BIT_MASK_RD_WR_WIFI_BT_INFO_8822C)                             \
+	 << BIT_SHIFT_RD_WR_WIFI_BT_INFO_8822C)
+#define BITS_RD_WR_WIFI_BT_INFO_8822C                                          \
+	(BIT_MASK_RD_WR_WIFI_BT_INFO_8822C                                     \
+	 << BIT_SHIFT_RD_WR_WIFI_BT_INFO_8822C)
+#define BIT_CLEAR_RD_WR_WIFI_BT_INFO_8822C(x)                                  \
+	((x) & (~BITS_RD_WR_WIFI_BT_INFO_8822C))
+#define BIT_GET_RD_WR_WIFI_BT_INFO_8822C(x)                                    \
+	(((x) >> BIT_SHIFT_RD_WR_WIFI_BT_INFO_8822C) &                         \
+	 BIT_MASK_RD_WR_WIFI_BT_INFO_8822C)
+#define BIT_SET_RD_WR_WIFI_BT_INFO_8822C(x, v)                                 \
+	(BIT_CLEAR_RD_WR_WIFI_BT_INFO_8822C(x) |                               \
+	 BIT_RD_WR_WIFI_BT_INFO_8822C(v))
+
+#define BIT_PMC_WR_OVF_8822C BIT(8)
+
+#define BIT_SHIFT_WLPMC_ERRINT_8822C 0
+#define BIT_MASK_WLPMC_ERRINT_8822C 0xff
+#define BIT_WLPMC_ERRINT_8822C(x)                                              \
+	(((x) & BIT_MASK_WLPMC_ERRINT_8822C) << BIT_SHIFT_WLPMC_ERRINT_8822C)
+#define BITS_WLPMC_ERRINT_8822C                                                \
+	(BIT_MASK_WLPMC_ERRINT_8822C << BIT_SHIFT_WLPMC_ERRINT_8822C)
+#define BIT_CLEAR_WLPMC_ERRINT_8822C(x) ((x) & (~BITS_WLPMC_ERRINT_8822C))
+#define BIT_GET_WLPMC_ERRINT_8822C(x)                                          \
+	(((x) >> BIT_SHIFT_WLPMC_ERRINT_8822C) & BIT_MASK_WLPMC_ERRINT_8822C)
+#define BIT_SET_WLPMC_ERRINT_8822C(x, v)                                       \
+	(BIT_CLEAR_WLPMC_ERRINT_8822C(x) | BIT_WLPMC_ERRINT_8822C(v))
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_HIMR0_8822C */
+#define BIT_TIMEOUT_INTERRUPT2_MASK_8822C BIT(31)
+#define BIT_TIMEOUT_INTERRUTP1_MASK_8822C BIT(30)
+#define BIT_PSTIMEOUT_MSK_8822C BIT(29)
+#define BIT_GTINT4_MSK_8822C BIT(28)
+#define BIT_GTINT3_MSK_8822C BIT(27)
+#define BIT_TXBCN0ERR_MSK_8822C BIT(26)
+#define BIT_TXBCN0OK_MSK_8822C BIT(25)
+#define BIT_TSF_BIT32_TOGGLE_MSK_8822C BIT(24)
+#define BIT_BCNDMAINT0_MSK_8822C BIT(20)
+#define BIT_BCNDERR0_MSK_8822C BIT(16)
+#define BIT_HSISR_IND_ON_INT_MSK_8822C BIT(15)
+#define BIT_BCNDMAINT_E_MSK_8822C BIT(14)
+#define BIT_CTWEND_MSK_8822C BIT(12)
+#define BIT_HISR1_IND_MSK_8822C BIT(11)
+#define BIT_C2HCMD_MSK_8822C BIT(10)
+#define BIT_CPWM2_MSK_8822C BIT(9)
+#define BIT_CPWM_MSK_8822C BIT(8)
+#define BIT_HIGHDOK_MSK_8822C BIT(7)
+#define BIT_MGTDOK_MSK_8822C BIT(6)
+#define BIT_BKDOK_MSK_8822C BIT(5)
+#define BIT_BEDOK_MSK_8822C BIT(4)
+#define BIT_VIDOK_MSK_8822C BIT(3)
+#define BIT_VODOK_MSK_8822C BIT(2)
+#define BIT_RDU_MSK_8822C BIT(1)
+#define BIT_RXOK_MSK_8822C BIT(0)
+
+/* 2 REG_HISR0_8822C */
+#define BIT_PSTIMEOUT2_8822C BIT(31)
+#define BIT_PSTIMEOUT1_8822C BIT(30)
+#define BIT_PSTIMEOUT_8822C BIT(29)
+#define BIT_GTINT4_8822C BIT(28)
+#define BIT_GTINT3_8822C BIT(27)
+#define BIT_TXBCN0ERR_8822C BIT(26)
+#define BIT_TXBCN0OK_8822C BIT(25)
+#define BIT_TSF_BIT32_TOGGLE_8822C BIT(24)
+#define BIT_BCNDMAINT0_8822C BIT(20)
+#define BIT_BCNDERR0_8822C BIT(16)
+#define BIT_HSISR_IND_ON_INT_8822C BIT(15)
+#define BIT_BCNDMAINT_E_8822C BIT(14)
+#define BIT_CTWEND_8822C BIT(12)
+#define BIT_HISR1_IND_INT_8822C BIT(11)
+#define BIT_C2HCMD_8822C BIT(10)
+#define BIT_CPWM2_8822C BIT(9)
+#define BIT_CPWM_8822C BIT(8)
+#define BIT_HIGHDOK_8822C BIT(7)
+#define BIT_MGTDOK_8822C BIT(6)
+#define BIT_BKDOK_8822C BIT(5)
+#define BIT_BEDOK_8822C BIT(4)
+#define BIT_VIDOK_8822C BIT(3)
+#define BIT_VODOK_8822C BIT(2)
+#define BIT_RDU_8822C BIT(1)
+#define BIT_RXOK_8822C BIT(0)
+
+/* 2 REG_HIMR1_8822C */
+#define BIT_TXFIFO_TH_INT_8822C BIT(30)
+#define BIT_BTON_STS_UPDATE_MASK_8822C BIT(29)
+#define BIT_MCU_ERR_MASK_8822C BIT(28)
+#define BIT_BCNDMAINT7__MSK_8822C BIT(27)
+#define BIT_BCNDMAINT6__MSK_8822C BIT(26)
+#define BIT_BCNDMAINT5__MSK_8822C BIT(25)
+#define BIT_BCNDMAINT4__MSK_8822C BIT(24)
+#define BIT_BCNDMAINT3_MSK_8822C BIT(23)
+#define BIT_BCNDMAINT2_MSK_8822C BIT(22)
+#define BIT_BCNDMAINT1_MSK_8822C BIT(21)
+#define BIT_BCNDERR7_MSK_8822C BIT(20)
+#define BIT_BCNDERR6_MSK_8822C BIT(19)
+#define BIT_BCNDERR5_MSK_8822C BIT(18)
+#define BIT_BCNDERR4_MSK_8822C BIT(17)
+#define BIT_BCNDERR3_MSK_8822C BIT(16)
+#define BIT_BCNDERR2_MSK_8822C BIT(15)
+#define BIT_BCNDERR1_MSK_8822C BIT(14)
+#define BIT_ATIMEND_E_MSK_8822C BIT(13)
+#define BIT_ATIMEND__MSK_8822C BIT(12)
+#define BIT_TXERR_MSK_8822C BIT(11)
+#define BIT_RXERR_MSK_8822C BIT(10)
+#define BIT_TXFOVW_MSK_8822C BIT(9)
+#define BIT_FOVW_MSK_8822C BIT(8)
+#define BIT_CPU_MGQ_TXDONE_MSK_8822C BIT(5)
+#define BIT_PS_TIMER_C_MSK_8822C BIT(4)
+#define BIT_PS_TIMER_B_MSK_8822C BIT(3)
+#define BIT_PS_TIMER_A_MSK_8822C BIT(2)
+#define BIT_CPUMGQ_TX_TIMER_MSK_8822C BIT(1)
+
+/* 2 REG_HISR1_8822C */
+#define BIT_TXFIFO_TH_INT_8822C BIT(30)
+#define BIT_BTON_STS_UPDATE_INT_8822C BIT(29)
+#define BIT_MCU_ERR_8822C BIT(28)
+#define BIT_BCNDMAINT7_8822C BIT(27)
+#define BIT_BCNDMAINT6_8822C BIT(26)
+#define BIT_BCNDMAINT5_8822C BIT(25)
+#define BIT_BCNDMAINT4_8822C BIT(24)
+#define BIT_BCNDMAINT3_8822C BIT(23)
+#define BIT_BCNDMAINT2_8822C BIT(22)
+#define BIT_BCNDMAINT1_8822C BIT(21)
+#define BIT_BCNDERR7_8822C BIT(20)
+#define BIT_BCNDERR6_8822C BIT(19)
+#define BIT_BCNDERR5_8822C BIT(18)
+#define BIT_BCNDERR4_8822C BIT(17)
+#define BIT_BCNDERR3_8822C BIT(16)
+#define BIT_BCNDERR2_8822C BIT(15)
+#define BIT_BCNDERR1_8822C BIT(14)
+#define BIT_ATIMEND_E_8822C BIT(13)
+#define BIT_ATIMEND_8822C BIT(12)
+#define BIT_TXERR_INT_8822C BIT(11)
+#define BIT_RXERR_INT_8822C BIT(10)
+#define BIT_TXFOVW_8822C BIT(9)
+#define BIT_FOVW_8822C BIT(8)
+
+/* 2 REG_NOT_VALID_8822C */
+#define BIT_CPU_MGQ_TXDONE_8822C BIT(5)
+#define BIT_PS_TIMER_C_8822C BIT(4)
+#define BIT_PS_TIMER_B_8822C BIT(3)
+#define BIT_PS_TIMER_A_8822C BIT(2)
+#define BIT_CPUMGQ_TX_TIMER_8822C BIT(1)
+
+/* 2 REG_DBG_PORT_SEL_8822C */
+
+#define BIT_SHIFT_DEBUG_ST_8822C 0
+#define BIT_MASK_DEBUG_ST_8822C 0xffffffffL
+#define BIT_DEBUG_ST_8822C(x)                                                  \
+	(((x) & BIT_MASK_DEBUG_ST_8822C) << BIT_SHIFT_DEBUG_ST_8822C)
+#define BITS_DEBUG_ST_8822C                                                    \
+	(BIT_MASK_DEBUG_ST_8822C << BIT_SHIFT_DEBUG_ST_8822C)
+#define BIT_CLEAR_DEBUG_ST_8822C(x) ((x) & (~BITS_DEBUG_ST_8822C))
+#define BIT_GET_DEBUG_ST_8822C(x)                                              \
+	(((x) >> BIT_SHIFT_DEBUG_ST_8822C) & BIT_MASK_DEBUG_ST_8822C)
+#define BIT_SET_DEBUG_ST_8822C(x, v)                                           \
+	(BIT_CLEAR_DEBUG_ST_8822C(x) | BIT_DEBUG_ST_8822C(v))
+
+/* 2 REG_PAD_CTRL2_8822C */
+#define BIT_USB3_USB2_TRANSITION_8822C BIT(20)
+
+#define BIT_SHIFT_USB23_SW_MODE_V1_8822C 18
+#define BIT_MASK_USB23_SW_MODE_V1_8822C 0x3
+#define BIT_USB23_SW_MODE_V1_8822C(x)                                          \
+	(((x) & BIT_MASK_USB23_SW_MODE_V1_8822C)                               \
+	 << BIT_SHIFT_USB23_SW_MODE_V1_8822C)
+#define BITS_USB23_SW_MODE_V1_8822C                                            \
+	(BIT_MASK_USB23_SW_MODE_V1_8822C << BIT_SHIFT_USB23_SW_MODE_V1_8822C)
+#define BIT_CLEAR_USB23_SW_MODE_V1_8822C(x)                                    \
+	((x) & (~BITS_USB23_SW_MODE_V1_8822C))
+#define BIT_GET_USB23_SW_MODE_V1_8822C(x)                                      \
+	(((x) >> BIT_SHIFT_USB23_SW_MODE_V1_8822C) &                           \
+	 BIT_MASK_USB23_SW_MODE_V1_8822C)
+#define BIT_SET_USB23_SW_MODE_V1_8822C(x, v)                                   \
+	(BIT_CLEAR_USB23_SW_MODE_V1_8822C(x) | BIT_USB23_SW_MODE_V1_8822C(v))
+
+#define BIT_NO_PDN_CHIPOFF_V1_8822C BIT(17)
+#define BIT_RSM_EN_V1_8822C BIT(16)
+
+#define BIT_SHIFT_MATCH_CNT_8822C 8
+#define BIT_MASK_MATCH_CNT_8822C 0xff
+#define BIT_MATCH_CNT_8822C(x)                                                 \
+	(((x) & BIT_MASK_MATCH_CNT_8822C) << BIT_SHIFT_MATCH_CNT_8822C)
+#define BITS_MATCH_CNT_8822C                                                   \
+	(BIT_MASK_MATCH_CNT_8822C << BIT_SHIFT_MATCH_CNT_8822C)
+#define BIT_CLEAR_MATCH_CNT_8822C(x) ((x) & (~BITS_MATCH_CNT_8822C))
+#define BIT_GET_MATCH_CNT_8822C(x)                                             \
+	(((x) >> BIT_SHIFT_MATCH_CNT_8822C) & BIT_MASK_MATCH_CNT_8822C)
+#define BIT_SET_MATCH_CNT_8822C(x, v)                                          \
+	(BIT_CLEAR_MATCH_CNT_8822C(x) | BIT_MATCH_CNT_8822C(v))
+
+#define BIT_LD_B12V_EN_8822C BIT(7)
+#define BIT_EECS_IOSEL_V1_8822C BIT(6)
+#define BIT_EECS_DATA_O_V1_8822C BIT(5)
+#define BIT_EECS_DATA_I_V1_8822C BIT(4)
+#define BIT_EESK_IOSEL_V1_8822C BIT(2)
+#define BIT_EESK_DATA_O_V1_8822C BIT(1)
+#define BIT_EESK_DATA_I_V1_8822C BIT(0)
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_PMC_DBG_CTRL2_8822C */
+
+#define BIT_SHIFT_EFUSE_BURN_GNT_8822C 24
+#define BIT_MASK_EFUSE_BURN_GNT_8822C 0xff
+#define BIT_EFUSE_BURN_GNT_8822C(x)                                            \
+	(((x) & BIT_MASK_EFUSE_BURN_GNT_8822C)                                 \
+	 << BIT_SHIFT_EFUSE_BURN_GNT_8822C)
+#define BITS_EFUSE_BURN_GNT_8822C                                              \
+	(BIT_MASK_EFUSE_BURN_GNT_8822C << BIT_SHIFT_EFUSE_BURN_GNT_8822C)
+#define BIT_CLEAR_EFUSE_BURN_GNT_8822C(x) ((x) & (~BITS_EFUSE_BURN_GNT_8822C))
+#define BIT_GET_EFUSE_BURN_GNT_8822C(x)                                        \
+	(((x) >> BIT_SHIFT_EFUSE_BURN_GNT_8822C) &                             \
+	 BIT_MASK_EFUSE_BURN_GNT_8822C)
+#define BIT_SET_EFUSE_BURN_GNT_8822C(x, v)                                     \
+	(BIT_CLEAR_EFUSE_BURN_GNT_8822C(x) | BIT_EFUSE_BURN_GNT_8822C(v))
+
+#define BIT_STOP_WL_PMC_8822C BIT(9)
+#define BIT_STOP_SYM_PMC_8822C BIT(8)
+#define BIT_BT_ACCESS_WL_PAGE0_8822C BIT(6)
+#define BIT_REG_RST_WLPMC_8822C BIT(5)
+#define BIT_REG_RST_PD12N_8822C BIT(4)
+#define BIT_SYSON_DIS_WLREG_WRMSK_8822C BIT(3)
+#define BIT_SYSON_DIS_PMCREG_WRMSK_8822C BIT(2)
+
+#define BIT_SHIFT_SYSON_REG_ARB_8822C 0
+#define BIT_MASK_SYSON_REG_ARB_8822C 0x3
+#define BIT_SYSON_REG_ARB_8822C(x)                                             \
+	(((x) & BIT_MASK_SYSON_REG_ARB_8822C) << BIT_SHIFT_SYSON_REG_ARB_8822C)
+#define BITS_SYSON_REG_ARB_8822C                                               \
+	(BIT_MASK_SYSON_REG_ARB_8822C << BIT_SHIFT_SYSON_REG_ARB_8822C)
+#define BIT_CLEAR_SYSON_REG_ARB_8822C(x) ((x) & (~BITS_SYSON_REG_ARB_8822C))
+#define BIT_GET_SYSON_REG_ARB_8822C(x)                                         \
+	(((x) >> BIT_SHIFT_SYSON_REG_ARB_8822C) & BIT_MASK_SYSON_REG_ARB_8822C)
+#define BIT_SET_SYSON_REG_ARB_8822C(x, v)                                      \
+	(BIT_CLEAR_SYSON_REG_ARB_8822C(x) | BIT_SYSON_REG_ARB_8822C(v))
+
+/* 2 REG_BIST_CTRL_8822C */
+#define BIT_BIST_USB_DIS_8822C BIT(27)
+#define BIT_BIST_PCI_DIS_8822C BIT(26)
+#define BIT_BIST_BT_DIS_8822C BIT(25)
+#define BIT_BIST_WL_DIS_8822C BIT(24)
+
+#define BIT_SHIFT_BIST_RPT_SEL_8822C 16
+#define BIT_MASK_BIST_RPT_SEL_8822C 0xf
+#define BIT_BIST_RPT_SEL_8822C(x)                                              \
+	(((x) & BIT_MASK_BIST_RPT_SEL_8822C) << BIT_SHIFT_BIST_RPT_SEL_8822C)
+#define BITS_BIST_RPT_SEL_8822C                                                \
+	(BIT_MASK_BIST_RPT_SEL_8822C << BIT_SHIFT_BIST_RPT_SEL_8822C)
+#define BIT_CLEAR_BIST_RPT_SEL_8822C(x) ((x) & (~BITS_BIST_RPT_SEL_8822C))
+#define BIT_GET_BIST_RPT_SEL_8822C(x)                                          \
+	(((x) >> BIT_SHIFT_BIST_RPT_SEL_8822C) & BIT_MASK_BIST_RPT_SEL_8822C)
+#define BIT_SET_BIST_RPT_SEL_8822C(x, v)                                       \
+	(BIT_CLEAR_BIST_RPT_SEL_8822C(x) | BIT_BIST_RPT_SEL_8822C(v))
+
+#define BIT_BIST_RESUME_PS_8822C BIT(4)
+#define BIT_BIST_RESUME_8822C BIT(3)
+#define BIT_BIST_NORMAL_8822C BIT(2)
+#define BIT_BIST_RSTN_8822C BIT(1)
+#define BIT_BIST_CLK_EN_8822C BIT(0)
+
+/* 2 REG_BIST_RPT_8822C */
+
+#define BIT_SHIFT_MBIST_REPORT_8822C 0
+#define BIT_MASK_MBIST_REPORT_8822C 0xffffffffL
+#define BIT_MBIST_REPORT_8822C(x)                                              \
+	(((x) & BIT_MASK_MBIST_REPORT_8822C) << BIT_SHIFT_MBIST_REPORT_8822C)
+#define BITS_MBIST_REPORT_8822C                                                \
+	(BIT_MASK_MBIST_REPORT_8822C << BIT_SHIFT_MBIST_REPORT_8822C)
+#define BIT_CLEAR_MBIST_REPORT_8822C(x) ((x) & (~BITS_MBIST_REPORT_8822C))
+#define BIT_GET_MBIST_REPORT_8822C(x)                                          \
+	(((x) >> BIT_SHIFT_MBIST_REPORT_8822C) & BIT_MASK_MBIST_REPORT_8822C)
+#define BIT_SET_MBIST_REPORT_8822C(x, v)                                       \
+	(BIT_CLEAR_MBIST_REPORT_8822C(x) | BIT_MBIST_REPORT_8822C(v))
+
+/* 2 REG_MEM_CTRL_8822C */
+#define BIT_UMEM_RME_8822C BIT(31)
+
+#define BIT_SHIFT_BT_SPRAM_8822C 28
+#define BIT_MASK_BT_SPRAM_8822C 0x3
+#define BIT_BT_SPRAM_8822C(x)                                                  \
+	(((x) & BIT_MASK_BT_SPRAM_8822C) << BIT_SHIFT_BT_SPRAM_8822C)
+#define BITS_BT_SPRAM_8822C                                                    \
+	(BIT_MASK_BT_SPRAM_8822C << BIT_SHIFT_BT_SPRAM_8822C)
+#define BIT_CLEAR_BT_SPRAM_8822C(x) ((x) & (~BITS_BT_SPRAM_8822C))
+#define BIT_GET_BT_SPRAM_8822C(x)                                              \
+	(((x) >> BIT_SHIFT_BT_SPRAM_8822C) & BIT_MASK_BT_SPRAM_8822C)
+#define BIT_SET_BT_SPRAM_8822C(x, v)                                           \
+	(BIT_CLEAR_BT_SPRAM_8822C(x) | BIT_BT_SPRAM_8822C(v))
+
+#define BIT_SHIFT_BT_ROM_8822C 24
+#define BIT_MASK_BT_ROM_8822C 0xf
+#define BIT_BT_ROM_8822C(x)                                                    \
+	(((x) & BIT_MASK_BT_ROM_8822C) << BIT_SHIFT_BT_ROM_8822C)
+#define BITS_BT_ROM_8822C (BIT_MASK_BT_ROM_8822C << BIT_SHIFT_BT_ROM_8822C)
+#define BIT_CLEAR_BT_ROM_8822C(x) ((x) & (~BITS_BT_ROM_8822C))
+#define BIT_GET_BT_ROM_8822C(x)                                                \
+	(((x) >> BIT_SHIFT_BT_ROM_8822C) & BIT_MASK_BT_ROM_8822C)
+#define BIT_SET_BT_ROM_8822C(x, v)                                             \
+	(BIT_CLEAR_BT_ROM_8822C(x) | BIT_BT_ROM_8822C(v))
+
+#define BIT_SHIFT_PCI_DPRAM_8822C 10
+#define BIT_MASK_PCI_DPRAM_8822C 0x3
+#define BIT_PCI_DPRAM_8822C(x)                                                 \
+	(((x) & BIT_MASK_PCI_DPRAM_8822C) << BIT_SHIFT_PCI_DPRAM_8822C)
+#define BITS_PCI_DPRAM_8822C                                                   \
+	(BIT_MASK_PCI_DPRAM_8822C << BIT_SHIFT_PCI_DPRAM_8822C)
+#define BIT_CLEAR_PCI_DPRAM_8822C(x) ((x) & (~BITS_PCI_DPRAM_8822C))
+#define BIT_GET_PCI_DPRAM_8822C(x)                                             \
+	(((x) >> BIT_SHIFT_PCI_DPRAM_8822C) & BIT_MASK_PCI_DPRAM_8822C)
+#define BIT_SET_PCI_DPRAM_8822C(x, v)                                          \
+	(BIT_CLEAR_PCI_DPRAM_8822C(x) | BIT_PCI_DPRAM_8822C(v))
+
+#define BIT_SHIFT_PCI_SPRAM_8822C 8
+#define BIT_MASK_PCI_SPRAM_8822C 0x3
+#define BIT_PCI_SPRAM_8822C(x)                                                 \
+	(((x) & BIT_MASK_PCI_SPRAM_8822C) << BIT_SHIFT_PCI_SPRAM_8822C)
+#define BITS_PCI_SPRAM_8822C                                                   \
+	(BIT_MASK_PCI_SPRAM_8822C << BIT_SHIFT_PCI_SPRAM_8822C)
+#define BIT_CLEAR_PCI_SPRAM_8822C(x) ((x) & (~BITS_PCI_SPRAM_8822C))
+#define BIT_GET_PCI_SPRAM_8822C(x)                                             \
+	(((x) >> BIT_SHIFT_PCI_SPRAM_8822C) & BIT_MASK_PCI_SPRAM_8822C)
+#define BIT_SET_PCI_SPRAM_8822C(x, v)                                          \
+	(BIT_CLEAR_PCI_SPRAM_8822C(x) | BIT_PCI_SPRAM_8822C(v))
+
+#define BIT_SHIFT_USB_SPRAM_8822C 6
+#define BIT_MASK_USB_SPRAM_8822C 0x3
+#define BIT_USB_SPRAM_8822C(x)                                                 \
+	(((x) & BIT_MASK_USB_SPRAM_8822C) << BIT_SHIFT_USB_SPRAM_8822C)
+#define BITS_USB_SPRAM_8822C                                                   \
+	(BIT_MASK_USB_SPRAM_8822C << BIT_SHIFT_USB_SPRAM_8822C)
+#define BIT_CLEAR_USB_SPRAM_8822C(x) ((x) & (~BITS_USB_SPRAM_8822C))
+#define BIT_GET_USB_SPRAM_8822C(x)                                             \
+	(((x) >> BIT_SHIFT_USB_SPRAM_8822C) & BIT_MASK_USB_SPRAM_8822C)
+#define BIT_SET_USB_SPRAM_8822C(x, v)                                          \
+	(BIT_CLEAR_USB_SPRAM_8822C(x) | BIT_USB_SPRAM_8822C(v))
+
+#define BIT_SHIFT_USB_SPRF_8822C 4
+#define BIT_MASK_USB_SPRF_8822C 0x3
+#define BIT_USB_SPRF_8822C(x)                                                  \
+	(((x) & BIT_MASK_USB_SPRF_8822C) << BIT_SHIFT_USB_SPRF_8822C)
+#define BITS_USB_SPRF_8822C                                                    \
+	(BIT_MASK_USB_SPRF_8822C << BIT_SHIFT_USB_SPRF_8822C)
+#define BIT_CLEAR_USB_SPRF_8822C(x) ((x) & (~BITS_USB_SPRF_8822C))
+#define BIT_GET_USB_SPRF_8822C(x)                                              \
+	(((x) >> BIT_SHIFT_USB_SPRF_8822C) & BIT_MASK_USB_SPRF_8822C)
+#define BIT_SET_USB_SPRF_8822C(x, v)                                           \
+	(BIT_CLEAR_USB_SPRF_8822C(x) | BIT_USB_SPRF_8822C(v))
+
+#define BIT_SHIFT_MCU_ROM_8822C 0
+#define BIT_MASK_MCU_ROM_8822C 0xf
+#define BIT_MCU_ROM_8822C(x)                                                   \
+	(((x) & BIT_MASK_MCU_ROM_8822C) << BIT_SHIFT_MCU_ROM_8822C)
+#define BITS_MCU_ROM_8822C (BIT_MASK_MCU_ROM_8822C << BIT_SHIFT_MCU_ROM_8822C)
+#define BIT_CLEAR_MCU_ROM_8822C(x) ((x) & (~BITS_MCU_ROM_8822C))
+#define BIT_GET_MCU_ROM_8822C(x)                                               \
+	(((x) >> BIT_SHIFT_MCU_ROM_8822C) & BIT_MASK_MCU_ROM_8822C)
+#define BIT_SET_MCU_ROM_8822C(x, v)                                            \
+	(BIT_CLEAR_MCU_ROM_8822C(x) | BIT_MCU_ROM_8822C(v))
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_USB_SIE_INTF_8822C */
+#define BIT_RD_SEL_8822C BIT(31)
+#define BIT_USB_SIE_INTF_WE_V1_8822C BIT(30)
+#define BIT_USB_SIE_INTF_BYIOREG_V1_8822C BIT(29)
+#define BIT_USB_SIE_SELECT_8822C BIT(28)
+
+#define BIT_SHIFT_USB_SIE_INTF_ADDR_V1_8822C 16
+#define BIT_MASK_USB_SIE_INTF_ADDR_V1_8822C 0x1ff
+#define BIT_USB_SIE_INTF_ADDR_V1_8822C(x)                                      \
+	(((x) & BIT_MASK_USB_SIE_INTF_ADDR_V1_8822C)                           \
+	 << BIT_SHIFT_USB_SIE_INTF_ADDR_V1_8822C)
+#define BITS_USB_SIE_INTF_ADDR_V1_8822C                                        \
+	(BIT_MASK_USB_SIE_INTF_ADDR_V1_8822C                                   \
+	 << BIT_SHIFT_USB_SIE_INTF_ADDR_V1_8822C)
+#define BIT_CLEAR_USB_SIE_INTF_ADDR_V1_8822C(x)                                \
+	((x) & (~BITS_USB_SIE_INTF_ADDR_V1_8822C))
+#define BIT_GET_USB_SIE_INTF_ADDR_V1_8822C(x)                                  \
+	(((x) >> BIT_SHIFT_USB_SIE_INTF_ADDR_V1_8822C) &                       \
+	 BIT_MASK_USB_SIE_INTF_ADDR_V1_8822C)
+#define BIT_SET_USB_SIE_INTF_ADDR_V1_8822C(x, v)                               \
+	(BIT_CLEAR_USB_SIE_INTF_ADDR_V1_8822C(x) |                             \
+	 BIT_USB_SIE_INTF_ADDR_V1_8822C(v))
+
+#define BIT_SHIFT_USB_SIE_INTF_RD_8822C 8
+#define BIT_MASK_USB_SIE_INTF_RD_8822C 0xff
+#define BIT_USB_SIE_INTF_RD_8822C(x)                                           \
+	(((x) & BIT_MASK_USB_SIE_INTF_RD_8822C)                                \
+	 << BIT_SHIFT_USB_SIE_INTF_RD_8822C)
+#define BITS_USB_SIE_INTF_RD_8822C                                             \
+	(BIT_MASK_USB_SIE_INTF_RD_8822C << BIT_SHIFT_USB_SIE_INTF_RD_8822C)
+#define BIT_CLEAR_USB_SIE_INTF_RD_8822C(x) ((x) & (~BITS_USB_SIE_INTF_RD_8822C))
+#define BIT_GET_USB_SIE_INTF_RD_8822C(x)                                       \
+	(((x) >> BIT_SHIFT_USB_SIE_INTF_RD_8822C) &                            \
+	 BIT_MASK_USB_SIE_INTF_RD_8822C)
+#define BIT_SET_USB_SIE_INTF_RD_8822C(x, v)                                    \
+	(BIT_CLEAR_USB_SIE_INTF_RD_8822C(x) | BIT_USB_SIE_INTF_RD_8822C(v))
+
+#define BIT_SHIFT_USB_SIE_INTF_WD_8822C 0
+#define BIT_MASK_USB_SIE_INTF_WD_8822C 0xff
+#define BIT_USB_SIE_INTF_WD_8822C(x)                                           \
+	(((x) & BIT_MASK_USB_SIE_INTF_WD_8822C)                                \
+	 << BIT_SHIFT_USB_SIE_INTF_WD_8822C)
+#define BITS_USB_SIE_INTF_WD_8822C                                             \
+	(BIT_MASK_USB_SIE_INTF_WD_8822C << BIT_SHIFT_USB_SIE_INTF_WD_8822C)
+#define BIT_CLEAR_USB_SIE_INTF_WD_8822C(x) ((x) & (~BITS_USB_SIE_INTF_WD_8822C))
+#define BIT_GET_USB_SIE_INTF_WD_8822C(x)                                       \
+	(((x) >> BIT_SHIFT_USB_SIE_INTF_WD_8822C) &                            \
+	 BIT_MASK_USB_SIE_INTF_WD_8822C)
+#define BIT_SET_USB_SIE_INTF_WD_8822C(x, v)                                    \
+	(BIT_CLEAR_USB_SIE_INTF_WD_8822C(x) | BIT_USB_SIE_INTF_WD_8822C(v))
+
+/* 2 REG_PCIE_MIO_INTF_8822C */
+
+#define BIT_SHIFT_PCIE_MIO_ADDR_PAGE_8822C 16
+#define BIT_MASK_PCIE_MIO_ADDR_PAGE_8822C 0x3
+#define BIT_PCIE_MIO_ADDR_PAGE_8822C(x)                                        \
+	(((x) & BIT_MASK_PCIE_MIO_ADDR_PAGE_8822C)                             \
+	 << BIT_SHIFT_PCIE_MIO_ADDR_PAGE_8822C)
+#define BITS_PCIE_MIO_ADDR_PAGE_8822C                                          \
+	(BIT_MASK_PCIE_MIO_ADDR_PAGE_8822C                                     \
+	 << BIT_SHIFT_PCIE_MIO_ADDR_PAGE_8822C)
+#define BIT_CLEAR_PCIE_MIO_ADDR_PAGE_8822C(x)                                  \
+	((x) & (~BITS_PCIE_MIO_ADDR_PAGE_8822C))
+#define BIT_GET_PCIE_MIO_ADDR_PAGE_8822C(x)                                    \
+	(((x) >> BIT_SHIFT_PCIE_MIO_ADDR_PAGE_8822C) &                         \
+	 BIT_MASK_PCIE_MIO_ADDR_PAGE_8822C)
+#define BIT_SET_PCIE_MIO_ADDR_PAGE_8822C(x, v)                                 \
+	(BIT_CLEAR_PCIE_MIO_ADDR_PAGE_8822C(x) |                               \
+	 BIT_PCIE_MIO_ADDR_PAGE_8822C(v))
+
+#define BIT_PCIE_MIO_BYIOREG_8822C BIT(13)
+#define BIT_PCIE_MIO_RE_8822C BIT(12)
+
+#define BIT_SHIFT_PCIE_MIO_WE_8822C 8
+#define BIT_MASK_PCIE_MIO_WE_8822C 0xf
+#define BIT_PCIE_MIO_WE_8822C(x)                                               \
+	(((x) & BIT_MASK_PCIE_MIO_WE_8822C) << BIT_SHIFT_PCIE_MIO_WE_8822C)
+#define BITS_PCIE_MIO_WE_8822C                                                 \
+	(BIT_MASK_PCIE_MIO_WE_8822C << BIT_SHIFT_PCIE_MIO_WE_8822C)
+#define BIT_CLEAR_PCIE_MIO_WE_8822C(x) ((x) & (~BITS_PCIE_MIO_WE_8822C))
+#define BIT_GET_PCIE_MIO_WE_8822C(x)                                           \
+	(((x) >> BIT_SHIFT_PCIE_MIO_WE_8822C) & BIT_MASK_PCIE_MIO_WE_8822C)
+#define BIT_SET_PCIE_MIO_WE_8822C(x, v)                                        \
+	(BIT_CLEAR_PCIE_MIO_WE_8822C(x) | BIT_PCIE_MIO_WE_8822C(v))
+
+#define BIT_SHIFT_PCIE_MIO_ADDR_8822C 0
+#define BIT_MASK_PCIE_MIO_ADDR_8822C 0xff
+#define BIT_PCIE_MIO_ADDR_8822C(x)                                             \
+	(((x) & BIT_MASK_PCIE_MIO_ADDR_8822C) << BIT_SHIFT_PCIE_MIO_ADDR_8822C)
+#define BITS_PCIE_MIO_ADDR_8822C                                               \
+	(BIT_MASK_PCIE_MIO_ADDR_8822C << BIT_SHIFT_PCIE_MIO_ADDR_8822C)
+#define BIT_CLEAR_PCIE_MIO_ADDR_8822C(x) ((x) & (~BITS_PCIE_MIO_ADDR_8822C))
+#define BIT_GET_PCIE_MIO_ADDR_8822C(x)                                         \
+	(((x) >> BIT_SHIFT_PCIE_MIO_ADDR_8822C) & BIT_MASK_PCIE_MIO_ADDR_8822C)
+#define BIT_SET_PCIE_MIO_ADDR_8822C(x, v)                                      \
+	(BIT_CLEAR_PCIE_MIO_ADDR_8822C(x) | BIT_PCIE_MIO_ADDR_8822C(v))
+
+/* 2 REG_PCIE_MIO_INTD_8822C */
+
+#define BIT_SHIFT_PCIE_MIO_DATA_8822C 0
+#define BIT_MASK_PCIE_MIO_DATA_8822C 0xffffffffL
+#define BIT_PCIE_MIO_DATA_8822C(x)                                             \
+	(((x) & BIT_MASK_PCIE_MIO_DATA_8822C) << BIT_SHIFT_PCIE_MIO_DATA_8822C)
+#define BITS_PCIE_MIO_DATA_8822C                                               \
+	(BIT_MASK_PCIE_MIO_DATA_8822C << BIT_SHIFT_PCIE_MIO_DATA_8822C)
+#define BIT_CLEAR_PCIE_MIO_DATA_8822C(x) ((x) & (~BITS_PCIE_MIO_DATA_8822C))
+#define BIT_GET_PCIE_MIO_DATA_8822C(x)                                         \
+	(((x) >> BIT_SHIFT_PCIE_MIO_DATA_8822C) & BIT_MASK_PCIE_MIO_DATA_8822C)
+#define BIT_SET_PCIE_MIO_DATA_8822C(x, v)                                      \
+	(BIT_CLEAR_PCIE_MIO_DATA_8822C(x) | BIT_PCIE_MIO_DATA_8822C(v))
+
+/* 2 REG_WLRF1_8822C */
+
+#define BIT_SHIFT_WLRF1_CTRL_8822C 24
+#define BIT_MASK_WLRF1_CTRL_8822C 0xff
+#define BIT_WLRF1_CTRL_8822C(x)                                                \
+	(((x) & BIT_MASK_WLRF1_CTRL_8822C) << BIT_SHIFT_WLRF1_CTRL_8822C)
+#define BITS_WLRF1_CTRL_8822C                                                  \
+	(BIT_MASK_WLRF1_CTRL_8822C << BIT_SHIFT_WLRF1_CTRL_8822C)
+#define BIT_CLEAR_WLRF1_CTRL_8822C(x) ((x) & (~BITS_WLRF1_CTRL_8822C))
+#define BIT_GET_WLRF1_CTRL_8822C(x)                                            \
+	(((x) >> BIT_SHIFT_WLRF1_CTRL_8822C) & BIT_MASK_WLRF1_CTRL_8822C)
+#define BIT_SET_WLRF1_CTRL_8822C(x, v)                                         \
+	(BIT_CLEAR_WLRF1_CTRL_8822C(x) | BIT_WLRF1_CTRL_8822C(v))
+
+/* 2 REG_SYS_CFG1_8822C */
+
+#define BIT_SHIFT_TRP_ICFG_8822C 28
+#define BIT_MASK_TRP_ICFG_8822C 0xf
+#define BIT_TRP_ICFG_8822C(x)                                                  \
+	(((x) & BIT_MASK_TRP_ICFG_8822C) << BIT_SHIFT_TRP_ICFG_8822C)
+#define BITS_TRP_ICFG_8822C                                                    \
+	(BIT_MASK_TRP_ICFG_8822C << BIT_SHIFT_TRP_ICFG_8822C)
+#define BIT_CLEAR_TRP_ICFG_8822C(x) ((x) & (~BITS_TRP_ICFG_8822C))
+#define BIT_GET_TRP_ICFG_8822C(x)                                              \
+	(((x) >> BIT_SHIFT_TRP_ICFG_8822C) & BIT_MASK_TRP_ICFG_8822C)
+#define BIT_SET_TRP_ICFG_8822C(x, v)                                           \
+	(BIT_CLEAR_TRP_ICFG_8822C(x) | BIT_TRP_ICFG_8822C(v))
+
+#define BIT_RF_TYPE_ID_8822C BIT(27)
+#define BIT_BD_HCI_SEL_8822C BIT(26)
+#define BIT_BD_PKG_SEL_8822C BIT(25)
+#define BIT_INTERNAL_EXTERNAL_SWR_8822C BIT(24)
+#define BIT_RTL_ID_8822C BIT(23)
+#define BIT_PAD_HWPD_IDN_8822C BIT(22)
+#define BIT_TESTMODE_8822C BIT(20)
+
+#define BIT_SHIFT_VENDOR_ID_8822C 16
+#define BIT_MASK_VENDOR_ID_8822C 0xf
+#define BIT_VENDOR_ID_8822C(x)                                                 \
+	(((x) & BIT_MASK_VENDOR_ID_8822C) << BIT_SHIFT_VENDOR_ID_8822C)
+#define BITS_VENDOR_ID_8822C                                                   \
+	(BIT_MASK_VENDOR_ID_8822C << BIT_SHIFT_VENDOR_ID_8822C)
+#define BIT_CLEAR_VENDOR_ID_8822C(x) ((x) & (~BITS_VENDOR_ID_8822C))
+#define BIT_GET_VENDOR_ID_8822C(x)                                             \
+	(((x) >> BIT_SHIFT_VENDOR_ID_8822C) & BIT_MASK_VENDOR_ID_8822C)
+#define BIT_SET_VENDOR_ID_8822C(x, v)                                          \
+	(BIT_CLEAR_VENDOR_ID_8822C(x) | BIT_VENDOR_ID_8822C(v))
+
+#define BIT_SHIFT_CHIP_VER_8822C 12
+#define BIT_MASK_CHIP_VER_8822C 0xf
+#define BIT_CHIP_VER_8822C(x)                                                  \
+	(((x) & BIT_MASK_CHIP_VER_8822C) << BIT_SHIFT_CHIP_VER_8822C)
+#define BITS_CHIP_VER_8822C                                                    \
+	(BIT_MASK_CHIP_VER_8822C << BIT_SHIFT_CHIP_VER_8822C)
+#define BIT_CLEAR_CHIP_VER_8822C(x) ((x) & (~BITS_CHIP_VER_8822C))
+#define BIT_GET_CHIP_VER_8822C(x)                                              \
+	(((x) >> BIT_SHIFT_CHIP_VER_8822C) & BIT_MASK_CHIP_VER_8822C)
+#define BIT_SET_CHIP_VER_8822C(x, v)                                           \
+	(BIT_CLEAR_CHIP_VER_8822C(x) | BIT_CHIP_VER_8822C(v))
+
+#define BIT_BD_MAC3_8822C BIT(11)
+#define BIT_BD_MAC1_8822C BIT(10)
+#define BIT_BD_MAC2_8822C BIT(9)
+#define BIT_SIC_IDLE_8822C BIT(8)
+#define BIT_SW_OFFLOAD_EN_8822C BIT(7)
+#define BIT_OCP_SHUTDN_8822C BIT(6)
+#define BIT_V15_VLD_8822C BIT(5)
+#define BIT_PCIRSTB_8822C BIT(4)
+#define BIT_PCLK_VLD_8822C BIT(3)
+#define BIT_UCLK_VLD_8822C BIT(2)
+#define BIT_ACLK_VLD_8822C BIT(1)
+#define BIT_XCLK_VLD_8822C BIT(0)
+
+/* 2 REG_SYS_STATUS1_8822C */
+
+#define BIT_SHIFT_RF_RL_ID_8822C 28
+#define BIT_MASK_RF_RL_ID_8822C 0xf
+#define BIT_RF_RL_ID_8822C(x)                                                  \
+	(((x) & BIT_MASK_RF_RL_ID_8822C) << BIT_SHIFT_RF_RL_ID_8822C)
+#define BITS_RF_RL_ID_8822C                                                    \
+	(BIT_MASK_RF_RL_ID_8822C << BIT_SHIFT_RF_RL_ID_8822C)
+#define BIT_CLEAR_RF_RL_ID_8822C(x) ((x) & (~BITS_RF_RL_ID_8822C))
+#define BIT_GET_RF_RL_ID_8822C(x)                                              \
+	(((x) >> BIT_SHIFT_RF_RL_ID_8822C) & BIT_MASK_RF_RL_ID_8822C)
+#define BIT_SET_RF_RL_ID_8822C(x, v)                                           \
+	(BIT_CLEAR_RF_RL_ID_8822C(x) | BIT_RF_RL_ID_8822C(v))
+
+#define BIT_HPHY_ICFG_8822C BIT(19)
+
+#define BIT_SHIFT_SEL_0XC0_8822C 16
+#define BIT_MASK_SEL_0XC0_8822C 0x3
+#define BIT_SEL_0XC0_8822C(x)                                                  \
+	(((x) & BIT_MASK_SEL_0XC0_8822C) << BIT_SHIFT_SEL_0XC0_8822C)
+#define BITS_SEL_0XC0_8822C                                                    \
+	(BIT_MASK_SEL_0XC0_8822C << BIT_SHIFT_SEL_0XC0_8822C)
+#define BIT_CLEAR_SEL_0XC0_8822C(x) ((x) & (~BITS_SEL_0XC0_8822C))
+#define BIT_GET_SEL_0XC0_8822C(x)                                              \
+	(((x) >> BIT_SHIFT_SEL_0XC0_8822C) & BIT_MASK_SEL_0XC0_8822C)
+#define BIT_SET_SEL_0XC0_8822C(x, v)                                           \
+	(BIT_CLEAR_SEL_0XC0_8822C(x) | BIT_SEL_0XC0_8822C(v))
+
+#define BIT_SHIFT_HCI_SEL_V4_8822C 12
+#define BIT_MASK_HCI_SEL_V4_8822C 0x3
+#define BIT_HCI_SEL_V4_8822C(x)                                                \
+	(((x) & BIT_MASK_HCI_SEL_V4_8822C) << BIT_SHIFT_HCI_SEL_V4_8822C)
+#define BITS_HCI_SEL_V4_8822C                                                  \
+	(BIT_MASK_HCI_SEL_V4_8822C << BIT_SHIFT_HCI_SEL_V4_8822C)
+#define BIT_CLEAR_HCI_SEL_V4_8822C(x) ((x) & (~BITS_HCI_SEL_V4_8822C))
+#define BIT_GET_HCI_SEL_V4_8822C(x)                                            \
+	(((x) >> BIT_SHIFT_HCI_SEL_V4_8822C) & BIT_MASK_HCI_SEL_V4_8822C)
+#define BIT_SET_HCI_SEL_V4_8822C(x, v)                                         \
+	(BIT_CLEAR_HCI_SEL_V4_8822C(x) | BIT_HCI_SEL_V4_8822C(v))
+
+#define BIT_USB_OPERATION_MODE_8822C BIT(10)
+#define BIT_BT_PDN_8822C BIT(9)
+#define BIT_AUTO_WLPON_8822C BIT(8)
+#define BIT_WL_MODE_8822C BIT(7)
+#define BIT_PKG_SEL_HCI_8822C BIT(6)
+
+#define BIT_SHIFT_PAD_HCI_SEL_V2_8822C 3
+#define BIT_MASK_PAD_HCI_SEL_V2_8822C 0x3
+#define BIT_PAD_HCI_SEL_V2_8822C(x)                                            \
+	(((x) & BIT_MASK_PAD_HCI_SEL_V2_8822C)                                 \
+	 << BIT_SHIFT_PAD_HCI_SEL_V2_8822C)
+#define BITS_PAD_HCI_SEL_V2_8822C                                              \
+	(BIT_MASK_PAD_HCI_SEL_V2_8822C << BIT_SHIFT_PAD_HCI_SEL_V2_8822C)
+#define BIT_CLEAR_PAD_HCI_SEL_V2_8822C(x) ((x) & (~BITS_PAD_HCI_SEL_V2_8822C))
+#define BIT_GET_PAD_HCI_SEL_V2_8822C(x)                                        \
+	(((x) >> BIT_SHIFT_PAD_HCI_SEL_V2_8822C) &                             \
+	 BIT_MASK_PAD_HCI_SEL_V2_8822C)
+#define BIT_SET_PAD_HCI_SEL_V2_8822C(x, v)                                     \
+	(BIT_CLEAR_PAD_HCI_SEL_V2_8822C(x) | BIT_PAD_HCI_SEL_V2_8822C(v))
+
+#define BIT_SHIFT_EFS_HCI_SEL_V1_8822C 0
+#define BIT_MASK_EFS_HCI_SEL_V1_8822C 0x7
+#define BIT_EFS_HCI_SEL_V1_8822C(x)                                            \
+	(((x) & BIT_MASK_EFS_HCI_SEL_V1_8822C)                                 \
+	 << BIT_SHIFT_EFS_HCI_SEL_V1_8822C)
+#define BITS_EFS_HCI_SEL_V1_8822C                                              \
+	(BIT_MASK_EFS_HCI_SEL_V1_8822C << BIT_SHIFT_EFS_HCI_SEL_V1_8822C)
+#define BIT_CLEAR_EFS_HCI_SEL_V1_8822C(x) ((x) & (~BITS_EFS_HCI_SEL_V1_8822C))
+#define BIT_GET_EFS_HCI_SEL_V1_8822C(x)                                        \
+	(((x) >> BIT_SHIFT_EFS_HCI_SEL_V1_8822C) &                             \
+	 BIT_MASK_EFS_HCI_SEL_V1_8822C)
+#define BIT_SET_EFS_HCI_SEL_V1_8822C(x, v)                                     \
+	(BIT_CLEAR_EFS_HCI_SEL_V1_8822C(x) | BIT_EFS_HCI_SEL_V1_8822C(v))
+
+/* 2 REG_SYS_STATUS2_8822C */
+#define BIT_HIOE_ON_TIMEOUT_8822C BIT(23)
+#define BIT_SIC_ON_TIMEOUT_8822C BIT(22)
+#define BIT_CPU_ON_TIMEOUT_8822C BIT(21)
+#define BIT_HCI_ON_TIMEOUT_8822C BIT(20)
+#define BIT_SIO_ALDN_8822C BIT(19)
+#define BIT_USB_ALDN_8822C BIT(18)
+#define BIT_PCI_ALDN_8822C BIT(17)
+#define BIT_SYS_ALDN_8822C BIT(16)
+
+#define BIT_SHIFT_EPVID1_8822C 8
+#define BIT_MASK_EPVID1_8822C 0xff
+#define BIT_EPVID1_8822C(x)                                                    \
+	(((x) & BIT_MASK_EPVID1_8822C) << BIT_SHIFT_EPVID1_8822C)
+#define BITS_EPVID1_8822C (BIT_MASK_EPVID1_8822C << BIT_SHIFT_EPVID1_8822C)
+#define BIT_CLEAR_EPVID1_8822C(x) ((x) & (~BITS_EPVID1_8822C))
+#define BIT_GET_EPVID1_8822C(x)                                                \
+	(((x) >> BIT_SHIFT_EPVID1_8822C) & BIT_MASK_EPVID1_8822C)
+#define BIT_SET_EPVID1_8822C(x, v)                                             \
+	(BIT_CLEAR_EPVID1_8822C(x) | BIT_EPVID1_8822C(v))
+
+#define BIT_SHIFT_EPVID0_8822C 0
+#define BIT_MASK_EPVID0_8822C 0xff
+#define BIT_EPVID0_8822C(x)                                                    \
+	(((x) & BIT_MASK_EPVID0_8822C) << BIT_SHIFT_EPVID0_8822C)
+#define BITS_EPVID0_8822C (BIT_MASK_EPVID0_8822C << BIT_SHIFT_EPVID0_8822C)
+#define BIT_CLEAR_EPVID0_8822C(x) ((x) & (~BITS_EPVID0_8822C))
+#define BIT_GET_EPVID0_8822C(x)                                                \
+	(((x) >> BIT_SHIFT_EPVID0_8822C) & BIT_MASK_EPVID0_8822C)
+#define BIT_SET_EPVID0_8822C(x, v)                                             \
+	(BIT_CLEAR_EPVID0_8822C(x) | BIT_EPVID0_8822C(v))
+
+/* 2 REG_SYS_CFG2_8822C */
+#define BIT_HCI_SEL_EMBEDDED_8822C BIT(8)
+
+#define BIT_SHIFT_HW_ID_8822C 0
+#define BIT_MASK_HW_ID_8822C 0xff
+#define BIT_HW_ID_8822C(x)                                                     \
+	(((x) & BIT_MASK_HW_ID_8822C) << BIT_SHIFT_HW_ID_8822C)
+#define BITS_HW_ID_8822C (BIT_MASK_HW_ID_8822C << BIT_SHIFT_HW_ID_8822C)
+#define BIT_CLEAR_HW_ID_8822C(x) ((x) & (~BITS_HW_ID_8822C))
+#define BIT_GET_HW_ID_8822C(x)                                                 \
+	(((x) >> BIT_SHIFT_HW_ID_8822C) & BIT_MASK_HW_ID_8822C)
+#define BIT_SET_HW_ID_8822C(x, v)                                              \
+	(BIT_CLEAR_HW_ID_8822C(x) | BIT_HW_ID_8822C(v))
+
+/* 2 REG_SYS_CFG3_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_ANAPARSW_MAC_0_8822C */
+#define BIT_OCP_L_8822C BIT(31)
+#define BIT_POWOCP_L_8822C BIT(30)
+
+#define BIT_SHIFT_CF_L_V2_8822C 28
+#define BIT_MASK_CF_L_V2_8822C 0x3
+#define BIT_CF_L_V2_8822C(x)                                                   \
+	(((x) & BIT_MASK_CF_L_V2_8822C) << BIT_SHIFT_CF_L_V2_8822C)
+#define BITS_CF_L_V2_8822C (BIT_MASK_CF_L_V2_8822C << BIT_SHIFT_CF_L_V2_8822C)
+#define BIT_CLEAR_CF_L_V2_8822C(x) ((x) & (~BITS_CF_L_V2_8822C))
+#define BIT_GET_CF_L_V2_8822C(x)                                               \
+	(((x) >> BIT_SHIFT_CF_L_V2_8822C) & BIT_MASK_CF_L_V2_8822C)
+#define BIT_SET_CF_L_V2_8822C(x, v)                                            \
+	(BIT_CLEAR_CF_L_V2_8822C(x) | BIT_CF_L_V2_8822C(v))
+
+#define BIT_SHIFT_CFC_L_V2_8822C 26
+#define BIT_MASK_CFC_L_V2_8822C 0x3
+#define BIT_CFC_L_V2_8822C(x)                                                  \
+	(((x) & BIT_MASK_CFC_L_V2_8822C) << BIT_SHIFT_CFC_L_V2_8822C)
+#define BITS_CFC_L_V2_8822C                                                    \
+	(BIT_MASK_CFC_L_V2_8822C << BIT_SHIFT_CFC_L_V2_8822C)
+#define BIT_CLEAR_CFC_L_V2_8822C(x) ((x) & (~BITS_CFC_L_V2_8822C))
+#define BIT_GET_CFC_L_V2_8822C(x)                                              \
+	(((x) >> BIT_SHIFT_CFC_L_V2_8822C) & BIT_MASK_CFC_L_V2_8822C)
+#define BIT_SET_CFC_L_V2_8822C(x, v)                                           \
+	(BIT_CLEAR_CFC_L_V2_8822C(x) | BIT_CFC_L_V2_8822C(v))
+
+#define BIT_SHIFT_R3_L_V2_8822C 24
+#define BIT_MASK_R3_L_V2_8822C 0x3
+#define BIT_R3_L_V2_8822C(x)                                                   \
+	(((x) & BIT_MASK_R3_L_V2_8822C) << BIT_SHIFT_R3_L_V2_8822C)
+#define BITS_R3_L_V2_8822C (BIT_MASK_R3_L_V2_8822C << BIT_SHIFT_R3_L_V2_8822C)
+#define BIT_CLEAR_R3_L_V2_8822C(x) ((x) & (~BITS_R3_L_V2_8822C))
+#define BIT_GET_R3_L_V2_8822C(x)                                               \
+	(((x) >> BIT_SHIFT_R3_L_V2_8822C) & BIT_MASK_R3_L_V2_8822C)
+#define BIT_SET_R3_L_V2_8822C(x, v)                                            \
+	(BIT_CLEAR_R3_L_V2_8822C(x) | BIT_R3_L_V2_8822C(v))
+
+#define BIT_SHIFT_R2_L_8822C 22
+#define BIT_MASK_R2_L_8822C 0x3
+#define BIT_R2_L_8822C(x) (((x) & BIT_MASK_R2_L_8822C) << BIT_SHIFT_R2_L_8822C)
+#define BITS_R2_L_8822C (BIT_MASK_R2_L_8822C << BIT_SHIFT_R2_L_8822C)
+#define BIT_CLEAR_R2_L_8822C(x) ((x) & (~BITS_R2_L_8822C))
+#define BIT_GET_R2_L_8822C(x)                                                  \
+	(((x) >> BIT_SHIFT_R2_L_8822C) & BIT_MASK_R2_L_8822C)
+#define BIT_SET_R2_L_8822C(x, v) (BIT_CLEAR_R2_L_8822C(x) | BIT_R2_L_8822C(v))
+
+#define BIT_SHIFT_R1_L_8822C 20
+#define BIT_MASK_R1_L_8822C 0x3
+#define BIT_R1_L_8822C(x) (((x) & BIT_MASK_R1_L_8822C) << BIT_SHIFT_R1_L_8822C)
+#define BITS_R1_L_8822C (BIT_MASK_R1_L_8822C << BIT_SHIFT_R1_L_8822C)
+#define BIT_CLEAR_R1_L_8822C(x) ((x) & (~BITS_R1_L_8822C))
+#define BIT_GET_R1_L_8822C(x)                                                  \
+	(((x) >> BIT_SHIFT_R1_L_8822C) & BIT_MASK_R1_L_8822C)
+#define BIT_SET_R1_L_8822C(x, v) (BIT_CLEAR_R1_L_8822C(x) | BIT_R1_L_8822C(v))
+
+#define BIT_SHIFT_C3_L_8822C 18
+#define BIT_MASK_C3_L_8822C 0x3
+#define BIT_C3_L_8822C(x) (((x) & BIT_MASK_C3_L_8822C) << BIT_SHIFT_C3_L_8822C)
+#define BITS_C3_L_8822C (BIT_MASK_C3_L_8822C << BIT_SHIFT_C3_L_8822C)
+#define BIT_CLEAR_C3_L_8822C(x) ((x) & (~BITS_C3_L_8822C))
+#define BIT_GET_C3_L_8822C(x)                                                  \
+	(((x) >> BIT_SHIFT_C3_L_8822C) & BIT_MASK_C3_L_8822C)
+#define BIT_SET_C3_L_8822C(x, v) (BIT_CLEAR_C3_L_8822C(x) | BIT_C3_L_8822C(v))
+
+#define BIT_SHIFT_C2_L_8822C 16
+#define BIT_MASK_C2_L_8822C 0x3
+#define BIT_C2_L_8822C(x) (((x) & BIT_MASK_C2_L_8822C) << BIT_SHIFT_C2_L_8822C)
+#define BITS_C2_L_8822C (BIT_MASK_C2_L_8822C << BIT_SHIFT_C2_L_8822C)
+#define BIT_CLEAR_C2_L_8822C(x) ((x) & (~BITS_C2_L_8822C))
+#define BIT_GET_C2_L_8822C(x)                                                  \
+	(((x) >> BIT_SHIFT_C2_L_8822C) & BIT_MASK_C2_L_8822C)
+#define BIT_SET_C2_L_8822C(x, v) (BIT_CLEAR_C2_L_8822C(x) | BIT_C2_L_8822C(v))
+
+#define BIT_SHIFT_C1_L_V2_8822C 14
+#define BIT_MASK_C1_L_V2_8822C 0x3
+#define BIT_C1_L_V2_8822C(x)                                                   \
+	(((x) & BIT_MASK_C1_L_V2_8822C) << BIT_SHIFT_C1_L_V2_8822C)
+#define BITS_C1_L_V2_8822C (BIT_MASK_C1_L_V2_8822C << BIT_SHIFT_C1_L_V2_8822C)
+#define BIT_CLEAR_C1_L_V2_8822C(x) ((x) & (~BITS_C1_L_V2_8822C))
+#define BIT_GET_C1_L_V2_8822C(x)                                               \
+	(((x) >> BIT_SHIFT_C1_L_V2_8822C) & BIT_MASK_C1_L_V2_8822C)
+#define BIT_SET_C1_L_V2_8822C(x, v)                                            \
+	(BIT_CLEAR_C1_L_V2_8822C(x) | BIT_C1_L_V2_8822C(v))
+
+#define BIT_REG_OCPS_L_V2_8822C BIT(13)
+#define BIT_REG_PWM_L_8822C BIT(12)
+
+#define BIT_SHIFT_V15ADJ_L_8822C 9
+#define BIT_MASK_V15ADJ_L_8822C 0x7
+#define BIT_V15ADJ_L_8822C(x)                                                  \
+	(((x) & BIT_MASK_V15ADJ_L_8822C) << BIT_SHIFT_V15ADJ_L_8822C)
+#define BITS_V15ADJ_L_8822C                                                    \
+	(BIT_MASK_V15ADJ_L_8822C << BIT_SHIFT_V15ADJ_L_8822C)
+#define BIT_CLEAR_V15ADJ_L_8822C(x) ((x) & (~BITS_V15ADJ_L_8822C))
+#define BIT_GET_V15ADJ_L_8822C(x)                                              \
+	(((x) >> BIT_SHIFT_V15ADJ_L_8822C) & BIT_MASK_V15ADJ_L_8822C)
+#define BIT_SET_V15ADJ_L_8822C(x, v)                                           \
+	(BIT_CLEAR_V15ADJ_L_8822C(x) | BIT_V15ADJ_L_8822C(v))
+
+#define BIT_SHIFT_IN_L_8822C 6
+#define BIT_MASK_IN_L_8822C 0x7
+#define BIT_IN_L_8822C(x) (((x) & BIT_MASK_IN_L_8822C) << BIT_SHIFT_IN_L_8822C)
+#define BITS_IN_L_8822C (BIT_MASK_IN_L_8822C << BIT_SHIFT_IN_L_8822C)
+#define BIT_CLEAR_IN_L_8822C(x) ((x) & (~BITS_IN_L_8822C))
+#define BIT_GET_IN_L_8822C(x)                                                  \
+	(((x) >> BIT_SHIFT_IN_L_8822C) & BIT_MASK_IN_L_8822C)
+#define BIT_SET_IN_L_8822C(x, v) (BIT_CLEAR_IN_L_8822C(x) | BIT_IN_L_8822C(v))
+
+#define BIT_SHIFT_STD_L_8822C 4
+#define BIT_MASK_STD_L_8822C 0x3
+#define BIT_STD_L_8822C(x)                                                     \
+	(((x) & BIT_MASK_STD_L_8822C) << BIT_SHIFT_STD_L_8822C)
+#define BITS_STD_L_8822C (BIT_MASK_STD_L_8822C << BIT_SHIFT_STD_L_8822C)
+#define BIT_CLEAR_STD_L_8822C(x) ((x) & (~BITS_STD_L_8822C))
+#define BIT_GET_STD_L_8822C(x)                                                 \
+	(((x) >> BIT_SHIFT_STD_L_8822C) & BIT_MASK_STD_L_8822C)
+#define BIT_SET_STD_L_8822C(x, v)                                              \
+	(BIT_CLEAR_STD_L_8822C(x) | BIT_STD_L_8822C(v))
+
+#define BIT_SHIFT_VOL_L_8822C 0
+#define BIT_MASK_VOL_L_8822C 0xf
+#define BIT_VOL_L_8822C(x)                                                     \
+	(((x) & BIT_MASK_VOL_L_8822C) << BIT_SHIFT_VOL_L_8822C)
+#define BITS_VOL_L_8822C (BIT_MASK_VOL_L_8822C << BIT_SHIFT_VOL_L_8822C)
+#define BIT_CLEAR_VOL_L_8822C(x) ((x) & (~BITS_VOL_L_8822C))
+#define BIT_GET_VOL_L_8822C(x)                                                 \
+	(((x) >> BIT_SHIFT_VOL_L_8822C) & BIT_MASK_VOL_L_8822C)
+#define BIT_SET_VOL_L_8822C(x, v)                                              \
+	(BIT_CLEAR_VOL_L_8822C(x) | BIT_VOL_L_8822C(v))
+
+/* 2 REG_ANAPARSW_MAC_1_8822C */
+
+#define BIT_SHIFT_OCP_L_PFM_8822C 29
+#define BIT_MASK_OCP_L_PFM_8822C 0x7
+#define BIT_OCP_L_PFM_8822C(x)                                                 \
+	(((x) & BIT_MASK_OCP_L_PFM_8822C) << BIT_SHIFT_OCP_L_PFM_8822C)
+#define BITS_OCP_L_PFM_8822C                                                   \
+	(BIT_MASK_OCP_L_PFM_8822C << BIT_SHIFT_OCP_L_PFM_8822C)
+#define BIT_CLEAR_OCP_L_PFM_8822C(x) ((x) & (~BITS_OCP_L_PFM_8822C))
+#define BIT_GET_OCP_L_PFM_8822C(x)                                             \
+	(((x) >> BIT_SHIFT_OCP_L_PFM_8822C) & BIT_MASK_OCP_L_PFM_8822C)
+#define BIT_SET_OCP_L_PFM_8822C(x, v)                                          \
+	(BIT_CLEAR_OCP_L_PFM_8822C(x) | BIT_OCP_L_PFM_8822C(v))
+
+#define BIT_SHIFT_CFC_L_PFM_8822C 27
+#define BIT_MASK_CFC_L_PFM_8822C 0x3
+#define BIT_CFC_L_PFM_8822C(x)                                                 \
+	(((x) & BIT_MASK_CFC_L_PFM_8822C) << BIT_SHIFT_CFC_L_PFM_8822C)
+#define BITS_CFC_L_PFM_8822C                                                   \
+	(BIT_MASK_CFC_L_PFM_8822C << BIT_SHIFT_CFC_L_PFM_8822C)
+#define BIT_CLEAR_CFC_L_PFM_8822C(x) ((x) & (~BITS_CFC_L_PFM_8822C))
+#define BIT_GET_CFC_L_PFM_8822C(x)                                             \
+	(((x) >> BIT_SHIFT_CFC_L_PFM_8822C) & BIT_MASK_CFC_L_PFM_8822C)
+#define BIT_SET_CFC_L_PFM_8822C(x, v)                                          \
+	(BIT_CLEAR_CFC_L_PFM_8822C(x) | BIT_CFC_L_PFM_8822C(v))
+
+/* 2 REG_NOT_VALID_8822C */
+
+#define BIT_SHIFT_REG_FREQ_L_V1_8822C 20
+#define BIT_MASK_REG_FREQ_L_V1_8822C 0x7
+#define BIT_REG_FREQ_L_V1_8822C(x)                                             \
+	(((x) & BIT_MASK_REG_FREQ_L_V1_8822C) << BIT_SHIFT_REG_FREQ_L_V1_8822C)
+#define BITS_REG_FREQ_L_V1_8822C                                               \
+	(BIT_MASK_REG_FREQ_L_V1_8822C << BIT_SHIFT_REG_FREQ_L_V1_8822C)
+#define BIT_CLEAR_REG_FREQ_L_V1_8822C(x) ((x) & (~BITS_REG_FREQ_L_V1_8822C))
+#define BIT_GET_REG_FREQ_L_V1_8822C(x)                                         \
+	(((x) >> BIT_SHIFT_REG_FREQ_L_V1_8822C) & BIT_MASK_REG_FREQ_L_V1_8822C)
+#define BIT_SET_REG_FREQ_L_V1_8822C(x, v)                                      \
+	(BIT_CLEAR_REG_FREQ_L_V1_8822C(x) | BIT_REG_FREQ_L_V1_8822C(v))
+
+#define BIT_EN_DUTY_8822C BIT(19)
+
+#define BIT_SHIFT_REG_MODE_V2_8822C 17
+#define BIT_MASK_REG_MODE_V2_8822C 0x3
+#define BIT_REG_MODE_V2_8822C(x)                                               \
+	(((x) & BIT_MASK_REG_MODE_V2_8822C) << BIT_SHIFT_REG_MODE_V2_8822C)
+#define BITS_REG_MODE_V2_8822C                                                 \
+	(BIT_MASK_REG_MODE_V2_8822C << BIT_SHIFT_REG_MODE_V2_8822C)
+#define BIT_CLEAR_REG_MODE_V2_8822C(x) ((x) & (~BITS_REG_MODE_V2_8822C))
+#define BIT_GET_REG_MODE_V2_8822C(x)                                           \
+	(((x) >> BIT_SHIFT_REG_MODE_V2_8822C) & BIT_MASK_REG_MODE_V2_8822C)
+#define BIT_SET_REG_MODE_V2_8822C(x, v)                                        \
+	(BIT_CLEAR_REG_MODE_V2_8822C(x) | BIT_REG_MODE_V2_8822C(v))
+
+#define BIT_EN_SP_8822C BIT(16)
+#define BIT_REG_AUTO_L_V2_8822C BIT(15)
+#define BIT_REG_LDOF_L_V2_8822C BIT(14)
+#define BIT_REG_TYPE_L_V2_8822C BIT(13)
+#define BIT_VO15_V1P05_H_8822C BIT(12)
+#define BIT_ARENB_L_V2_8822C BIT(11)
+
+#define BIT_SHIFT_TBOX_L1_V2_8822C 9
+#define BIT_MASK_TBOX_L1_V2_8822C 0x3
+#define BIT_TBOX_L1_V2_8822C(x)                                                \
+	(((x) & BIT_MASK_TBOX_L1_V2_8822C) << BIT_SHIFT_TBOX_L1_V2_8822C)
+#define BITS_TBOX_L1_V2_8822C                                                  \
+	(BIT_MASK_TBOX_L1_V2_8822C << BIT_SHIFT_TBOX_L1_V2_8822C)
+#define BIT_CLEAR_TBOX_L1_V2_8822C(x) ((x) & (~BITS_TBOX_L1_V2_8822C))
+#define BIT_GET_TBOX_L1_V2_8822C(x)                                            \
+	(((x) >> BIT_SHIFT_TBOX_L1_V2_8822C) & BIT_MASK_TBOX_L1_V2_8822C)
+#define BIT_SET_TBOX_L1_V2_8822C(x, v)                                         \
+	(BIT_CLEAR_TBOX_L1_V2_8822C(x) | BIT_TBOX_L1_V2_8822C(v))
+
+#define BIT_SHIFT_REG_DELAY_L_8822C 7
+#define BIT_MASK_REG_DELAY_L_8822C 0x3
+#define BIT_REG_DELAY_L_8822C(x)                                               \
+	(((x) & BIT_MASK_REG_DELAY_L_8822C) << BIT_SHIFT_REG_DELAY_L_8822C)
+#define BITS_REG_DELAY_L_8822C                                                 \
+	(BIT_MASK_REG_DELAY_L_8822C << BIT_SHIFT_REG_DELAY_L_8822C)
+#define BIT_CLEAR_REG_DELAY_L_8822C(x) ((x) & (~BITS_REG_DELAY_L_8822C))
+#define BIT_GET_REG_DELAY_L_8822C(x)                                           \
+	(((x) >> BIT_SHIFT_REG_DELAY_L_8822C) & BIT_MASK_REG_DELAY_L_8822C)
+#define BIT_SET_REG_DELAY_L_8822C(x, v)                                        \
+	(BIT_CLEAR_REG_DELAY_L_8822C(x) | BIT_REG_DELAY_L_8822C(v))
+
+#define BIT_REG_CLAMP_D_L_8822C BIT(6)
+#define BIT_REG_BYPASS_L_V2_8822C BIT(5)
+#define BIT_REG_AUTOZCD_L_8822C BIT(4)
+#define BIT_POW_ZCD_L_V2_8822C BIT(3)
+#define BIT_REG_HALF_L_8822C BIT(2)
+
+#define BIT_SHIFT_OCP_L_V2_8822C 0
+#define BIT_MASK_OCP_L_V2_8822C 0x3
+#define BIT_OCP_L_V2_8822C(x)                                                  \
+	(((x) & BIT_MASK_OCP_L_V2_8822C) << BIT_SHIFT_OCP_L_V2_8822C)
+#define BITS_OCP_L_V2_8822C                                                    \
+	(BIT_MASK_OCP_L_V2_8822C << BIT_SHIFT_OCP_L_V2_8822C)
+#define BIT_CLEAR_OCP_L_V2_8822C(x) ((x) & (~BITS_OCP_L_V2_8822C))
+#define BIT_GET_OCP_L_V2_8822C(x)                                              \
+	(((x) >> BIT_SHIFT_OCP_L_V2_8822C) & BIT_MASK_OCP_L_V2_8822C)
+#define BIT_SET_OCP_L_V2_8822C(x, v)                                           \
+	(BIT_CLEAR_OCP_L_V2_8822C(x) | BIT_OCP_L_V2_8822C(v))
+
+/* 2 REG_ANAPAR_MAC_0_8822C */
+
+#define BIT_SHIFT_REG_LPF_R3_8822C 29
+#define BIT_MASK_REG_LPF_R3_8822C 0x7
+#define BIT_REG_LPF_R3_8822C(x)                                                \
+	(((x) & BIT_MASK_REG_LPF_R3_8822C) << BIT_SHIFT_REG_LPF_R3_8822C)
+#define BITS_REG_LPF_R3_8822C                                                  \
+	(BIT_MASK_REG_LPF_R3_8822C << BIT_SHIFT_REG_LPF_R3_8822C)
+#define BIT_CLEAR_REG_LPF_R3_8822C(x) ((x) & (~BITS_REG_LPF_R3_8822C))
+#define BIT_GET_REG_LPF_R3_8822C(x)                                            \
+	(((x) >> BIT_SHIFT_REG_LPF_R3_8822C) & BIT_MASK_REG_LPF_R3_8822C)
+#define BIT_SET_REG_LPF_R3_8822C(x, v)                                         \
+	(BIT_CLEAR_REG_LPF_R3_8822C(x) | BIT_REG_LPF_R3_8822C(v))
+
+#define BIT_SHIFT_REG_LPF_R2_8822C 24
+#define BIT_MASK_REG_LPF_R2_8822C 0x1f
+#define BIT_REG_LPF_R2_8822C(x)                                                \
+	(((x) & BIT_MASK_REG_LPF_R2_8822C) << BIT_SHIFT_REG_LPF_R2_8822C)
+#define BITS_REG_LPF_R2_8822C                                                  \
+	(BIT_MASK_REG_LPF_R2_8822C << BIT_SHIFT_REG_LPF_R2_8822C)
+#define BIT_CLEAR_REG_LPF_R2_8822C(x) ((x) & (~BITS_REG_LPF_R2_8822C))
+#define BIT_GET_REG_LPF_R2_8822C(x)                                            \
+	(((x) >> BIT_SHIFT_REG_LPF_R2_8822C) & BIT_MASK_REG_LPF_R2_8822C)
+#define BIT_SET_REG_LPF_R2_8822C(x, v)                                         \
+	(BIT_CLEAR_REG_LPF_R2_8822C(x) | BIT_REG_LPF_R2_8822C(v))
+
+#define BIT_SHIFT_REG_LPF_C3_8822C 21
+#define BIT_MASK_REG_LPF_C3_8822C 0x7
+#define BIT_REG_LPF_C3_8822C(x)                                                \
+	(((x) & BIT_MASK_REG_LPF_C3_8822C) << BIT_SHIFT_REG_LPF_C3_8822C)
+#define BITS_REG_LPF_C3_8822C                                                  \
+	(BIT_MASK_REG_LPF_C3_8822C << BIT_SHIFT_REG_LPF_C3_8822C)
+#define BIT_CLEAR_REG_LPF_C3_8822C(x) ((x) & (~BITS_REG_LPF_C3_8822C))
+#define BIT_GET_REG_LPF_C3_8822C(x)                                            \
+	(((x) >> BIT_SHIFT_REG_LPF_C3_8822C) & BIT_MASK_REG_LPF_C3_8822C)
+#define BIT_SET_REG_LPF_C3_8822C(x, v)                                         \
+	(BIT_CLEAR_REG_LPF_C3_8822C(x) | BIT_REG_LPF_C3_8822C(v))
+
+#define BIT_SHIFT_REG_LPF_C2_8822C 18
+#define BIT_MASK_REG_LPF_C2_8822C 0x7
+#define BIT_REG_LPF_C2_8822C(x)                                                \
+	(((x) & BIT_MASK_REG_LPF_C2_8822C) << BIT_SHIFT_REG_LPF_C2_8822C)
+#define BITS_REG_LPF_C2_8822C                                                  \
+	(BIT_MASK_REG_LPF_C2_8822C << BIT_SHIFT_REG_LPF_C2_8822C)
+#define BIT_CLEAR_REG_LPF_C2_8822C(x) ((x) & (~BITS_REG_LPF_C2_8822C))
+#define BIT_GET_REG_LPF_C2_8822C(x)                                            \
+	(((x) >> BIT_SHIFT_REG_LPF_C2_8822C) & BIT_MASK_REG_LPF_C2_8822C)
+#define BIT_SET_REG_LPF_C2_8822C(x, v)                                         \
+	(BIT_CLEAR_REG_LPF_C2_8822C(x) | BIT_REG_LPF_C2_8822C(v))
+
+#define BIT_SHIFT_REG_LPF_C1_8822C 15
+#define BIT_MASK_REG_LPF_C1_8822C 0x7
+#define BIT_REG_LPF_C1_8822C(x)                                                \
+	(((x) & BIT_MASK_REG_LPF_C1_8822C) << BIT_SHIFT_REG_LPF_C1_8822C)
+#define BITS_REG_LPF_C1_8822C                                                  \
+	(BIT_MASK_REG_LPF_C1_8822C << BIT_SHIFT_REG_LPF_C1_8822C)
+#define BIT_CLEAR_REG_LPF_C1_8822C(x) ((x) & (~BITS_REG_LPF_C1_8822C))
+#define BIT_GET_REG_LPF_C1_8822C(x)                                            \
+	(((x) >> BIT_SHIFT_REG_LPF_C1_8822C) & BIT_MASK_REG_LPF_C1_8822C)
+#define BIT_SET_REG_LPF_C1_8822C(x, v)                                         \
+	(BIT_CLEAR_REG_LPF_C1_8822C(x) | BIT_REG_LPF_C1_8822C(v))
+
+#define BIT_SHIFT_REG_LDO_SEL_V1_8822C 13
+#define BIT_MASK_REG_LDO_SEL_V1_8822C 0x3
+#define BIT_REG_LDO_SEL_V1_8822C(x)                                            \
+	(((x) & BIT_MASK_REG_LDO_SEL_V1_8822C)                                 \
+	 << BIT_SHIFT_REG_LDO_SEL_V1_8822C)
+#define BITS_REG_LDO_SEL_V1_8822C                                              \
+	(BIT_MASK_REG_LDO_SEL_V1_8822C << BIT_SHIFT_REG_LDO_SEL_V1_8822C)
+#define BIT_CLEAR_REG_LDO_SEL_V1_8822C(x) ((x) & (~BITS_REG_LDO_SEL_V1_8822C))
+#define BIT_GET_REG_LDO_SEL_V1_8822C(x)                                        \
+	(((x) >> BIT_SHIFT_REG_LDO_SEL_V1_8822C) &                             \
+	 BIT_MASK_REG_LDO_SEL_V1_8822C)
+#define BIT_SET_REG_LDO_SEL_V1_8822C(x, v)                                     \
+	(BIT_CLEAR_REG_LDO_SEL_V1_8822C(x) | BIT_REG_LDO_SEL_V1_8822C(v))
+
+#define BIT_REG_CP_ICPX2_8822C BIT(12)
+
+#define BIT_SHIFT_REG_CP_ICP_SEL_FAST_8822C 9
+#define BIT_MASK_REG_CP_ICP_SEL_FAST_8822C 0x7
+#define BIT_REG_CP_ICP_SEL_FAST_8822C(x)                                       \
+	(((x) & BIT_MASK_REG_CP_ICP_SEL_FAST_8822C)                            \
+	 << BIT_SHIFT_REG_CP_ICP_SEL_FAST_8822C)
+#define BITS_REG_CP_ICP_SEL_FAST_8822C                                         \
+	(BIT_MASK_REG_CP_ICP_SEL_FAST_8822C                                    \
+	 << BIT_SHIFT_REG_CP_ICP_SEL_FAST_8822C)
+#define BIT_CLEAR_REG_CP_ICP_SEL_FAST_8822C(x)                                 \
+	((x) & (~BITS_REG_CP_ICP_SEL_FAST_8822C))
+#define BIT_GET_REG_CP_ICP_SEL_FAST_8822C(x)                                   \
+	(((x) >> BIT_SHIFT_REG_CP_ICP_SEL_FAST_8822C) &                        \
+	 BIT_MASK_REG_CP_ICP_SEL_FAST_8822C)
+#define BIT_SET_REG_CP_ICP_SEL_FAST_8822C(x, v)                                \
+	(BIT_CLEAR_REG_CP_ICP_SEL_FAST_8822C(x) |                              \
+	 BIT_REG_CP_ICP_SEL_FAST_8822C(v))
+
+#define BIT_SHIFT_REG_CP_ICP_SEL_8822C 6
+#define BIT_MASK_REG_CP_ICP_SEL_8822C 0x7
+#define BIT_REG_CP_ICP_SEL_8822C(x)                                            \
+	(((x) & BIT_MASK_REG_CP_ICP_SEL_8822C)                                 \
+	 << BIT_SHIFT_REG_CP_ICP_SEL_8822C)
+#define BITS_REG_CP_ICP_SEL_8822C                                              \
+	(BIT_MASK_REG_CP_ICP_SEL_8822C << BIT_SHIFT_REG_CP_ICP_SEL_8822C)
+#define BIT_CLEAR_REG_CP_ICP_SEL_8822C(x) ((x) & (~BITS_REG_CP_ICP_SEL_8822C))
+#define BIT_GET_REG_CP_ICP_SEL_8822C(x)                                        \
+	(((x) >> BIT_SHIFT_REG_CP_ICP_SEL_8822C) &                             \
+	 BIT_MASK_REG_CP_ICP_SEL_8822C)
+#define BIT_SET_REG_CP_ICP_SEL_8822C(x, v)                                     \
+	(BIT_CLEAR_REG_CP_ICP_SEL_8822C(x) | BIT_REG_CP_ICP_SEL_8822C(v))
+
+#define BIT_SHIFT_REG_IB_PI_8822C 4
+#define BIT_MASK_REG_IB_PI_8822C 0x3
+#define BIT_REG_IB_PI_8822C(x)                                                 \
+	(((x) & BIT_MASK_REG_IB_PI_8822C) << BIT_SHIFT_REG_IB_PI_8822C)
+#define BITS_REG_IB_PI_8822C                                                   \
+	(BIT_MASK_REG_IB_PI_8822C << BIT_SHIFT_REG_IB_PI_8822C)
+#define BIT_CLEAR_REG_IB_PI_8822C(x) ((x) & (~BITS_REG_IB_PI_8822C))
+#define BIT_GET_REG_IB_PI_8822C(x)                                             \
+	(((x) >> BIT_SHIFT_REG_IB_PI_8822C) & BIT_MASK_REG_IB_PI_8822C)
+#define BIT_SET_REG_IB_PI_8822C(x, v)                                          \
+	(BIT_CLEAR_REG_IB_PI_8822C(x) | BIT_REG_IB_PI_8822C(v))
+
+#define BIT_LDO2PWRCUT_8822C BIT(3)
+#define BIT_VPULSE_LDO_8822C BIT(2)
+
+#define BIT_SHIFT_LDO_VSEL_8822C 0
+#define BIT_MASK_LDO_VSEL_8822C 0x3
+#define BIT_LDO_VSEL_8822C(x)                                                  \
+	(((x) & BIT_MASK_LDO_VSEL_8822C) << BIT_SHIFT_LDO_VSEL_8822C)
+#define BITS_LDO_VSEL_8822C                                                    \
+	(BIT_MASK_LDO_VSEL_8822C << BIT_SHIFT_LDO_VSEL_8822C)
+#define BIT_CLEAR_LDO_VSEL_8822C(x) ((x) & (~BITS_LDO_VSEL_8822C))
+#define BIT_GET_LDO_VSEL_8822C(x)                                              \
+	(((x) >> BIT_SHIFT_LDO_VSEL_8822C) & BIT_MASK_LDO_VSEL_8822C)
+#define BIT_SET_LDO_VSEL_8822C(x, v)                                           \
+	(BIT_CLEAR_LDO_VSEL_8822C(x) | BIT_LDO_VSEL_8822C(v))
+
+/* 2 REG_ANAPAR_MAC_1_8822C */
+
+#define BIT_SHIFT_REG_CK_MON_SEL_8822C 29
+#define BIT_MASK_REG_CK_MON_SEL_8822C 0x7
+#define BIT_REG_CK_MON_SEL_8822C(x)                                            \
+	(((x) & BIT_MASK_REG_CK_MON_SEL_8822C)                                 \
+	 << BIT_SHIFT_REG_CK_MON_SEL_8822C)
+#define BITS_REG_CK_MON_SEL_8822C                                              \
+	(BIT_MASK_REG_CK_MON_SEL_8822C << BIT_SHIFT_REG_CK_MON_SEL_8822C)
+#define BIT_CLEAR_REG_CK_MON_SEL_8822C(x) ((x) & (~BITS_REG_CK_MON_SEL_8822C))
+#define BIT_GET_REG_CK_MON_SEL_8822C(x)                                        \
+	(((x) >> BIT_SHIFT_REG_CK_MON_SEL_8822C) &                             \
+	 BIT_MASK_REG_CK_MON_SEL_8822C)
+#define BIT_SET_REG_CK_MON_SEL_8822C(x, v)                                     \
+	(BIT_CLEAR_REG_CK_MON_SEL_8822C(x) | BIT_REG_CK_MON_SEL_8822C(v))
+
+#define BIT_REG_CK_MON_EN_8822C BIT(28)
+#define BIT_REG_XTAL_FREQ_SEL_8822C BIT(27)
+#define BIT_REG_XTAL_EDGE_SEL_8822C BIT(26)
+#define BIT_REG_VCO_KVCO_8822C BIT(25)
+#define BIT_REG_SDM_EDGE_SEL_8822C BIT(24)
+#define BIT_REG_SDM_CK_SEL_8822C BIT(23)
+#define BIT_REG_SDM_CK_GATED_8822C BIT(22)
+#define BIT_REG_PFD_RESET_GATED_8822C BIT(21)
+
+#define BIT_SHIFT_REG_LPF_R3_FAST_8822C 16
+#define BIT_MASK_REG_LPF_R3_FAST_8822C 0x1f
+#define BIT_REG_LPF_R3_FAST_8822C(x)                                           \
+	(((x) & BIT_MASK_REG_LPF_R3_FAST_8822C)                                \
+	 << BIT_SHIFT_REG_LPF_R3_FAST_8822C)
+#define BITS_REG_LPF_R3_FAST_8822C                                             \
+	(BIT_MASK_REG_LPF_R3_FAST_8822C << BIT_SHIFT_REG_LPF_R3_FAST_8822C)
+#define BIT_CLEAR_REG_LPF_R3_FAST_8822C(x) ((x) & (~BITS_REG_LPF_R3_FAST_8822C))
+#define BIT_GET_REG_LPF_R3_FAST_8822C(x)                                       \
+	(((x) >> BIT_SHIFT_REG_LPF_R3_FAST_8822C) &                            \
+	 BIT_MASK_REG_LPF_R3_FAST_8822C)
+#define BIT_SET_REG_LPF_R3_FAST_8822C(x, v)                                    \
+	(BIT_CLEAR_REG_LPF_R3_FAST_8822C(x) | BIT_REG_LPF_R3_FAST_8822C(v))
+
+#define BIT_SHIFT_REG_LPF_R2_FAST_8822C 11
+#define BIT_MASK_REG_LPF_R2_FAST_8822C 0x1f
+#define BIT_REG_LPF_R2_FAST_8822C(x)                                           \
+	(((x) & BIT_MASK_REG_LPF_R2_FAST_8822C)                                \
+	 << BIT_SHIFT_REG_LPF_R2_FAST_8822C)
+#define BITS_REG_LPF_R2_FAST_8822C                                             \
+	(BIT_MASK_REG_LPF_R2_FAST_8822C << BIT_SHIFT_REG_LPF_R2_FAST_8822C)
+#define BIT_CLEAR_REG_LPF_R2_FAST_8822C(x) ((x) & (~BITS_REG_LPF_R2_FAST_8822C))
+#define BIT_GET_REG_LPF_R2_FAST_8822C(x)                                       \
+	(((x) >> BIT_SHIFT_REG_LPF_R2_FAST_8822C) &                            \
+	 BIT_MASK_REG_LPF_R2_FAST_8822C)
+#define BIT_SET_REG_LPF_R2_FAST_8822C(x, v)                                    \
+	(BIT_CLEAR_REG_LPF_R2_FAST_8822C(x) | BIT_REG_LPF_R2_FAST_8822C(v))
+
+#define BIT_SHIFT_REG_LPF_C3_FAST_8822C 8
+#define BIT_MASK_REG_LPF_C3_FAST_8822C 0x7
+#define BIT_REG_LPF_C3_FAST_8822C(x)                                           \
+	(((x) & BIT_MASK_REG_LPF_C3_FAST_8822C)                                \
+	 << BIT_SHIFT_REG_LPF_C3_FAST_8822C)
+#define BITS_REG_LPF_C3_FAST_8822C                                             \
+	(BIT_MASK_REG_LPF_C3_FAST_8822C << BIT_SHIFT_REG_LPF_C3_FAST_8822C)
+#define BIT_CLEAR_REG_LPF_C3_FAST_8822C(x) ((x) & (~BITS_REG_LPF_C3_FAST_8822C))
+#define BIT_GET_REG_LPF_C3_FAST_8822C(x)                                       \
+	(((x) >> BIT_SHIFT_REG_LPF_C3_FAST_8822C) &                            \
+	 BIT_MASK_REG_LPF_C3_FAST_8822C)
+#define BIT_SET_REG_LPF_C3_FAST_8822C(x, v)                                    \
+	(BIT_CLEAR_REG_LPF_C3_FAST_8822C(x) | BIT_REG_LPF_C3_FAST_8822C(v))
+
+#define BIT_SHIFT_REG_LPF_C2_FAST_8822C 5
+#define BIT_MASK_REG_LPF_C2_FAST_8822C 0x7
+#define BIT_REG_LPF_C2_FAST_8822C(x)                                           \
+	(((x) & BIT_MASK_REG_LPF_C2_FAST_8822C)                                \
+	 << BIT_SHIFT_REG_LPF_C2_FAST_8822C)
+#define BITS_REG_LPF_C2_FAST_8822C                                             \
+	(BIT_MASK_REG_LPF_C2_FAST_8822C << BIT_SHIFT_REG_LPF_C2_FAST_8822C)
+#define BIT_CLEAR_REG_LPF_C2_FAST_8822C(x) ((x) & (~BITS_REG_LPF_C2_FAST_8822C))
+#define BIT_GET_REG_LPF_C2_FAST_8822C(x)                                       \
+	(((x) >> BIT_SHIFT_REG_LPF_C2_FAST_8822C) &                            \
+	 BIT_MASK_REG_LPF_C2_FAST_8822C)
+#define BIT_SET_REG_LPF_C2_FAST_8822C(x, v)                                    \
+	(BIT_CLEAR_REG_LPF_C2_FAST_8822C(x) | BIT_REG_LPF_C2_FAST_8822C(v))
+
+#define BIT_SHIFT_REG_LPF_C1_FAST_8822C 2
+#define BIT_MASK_REG_LPF_C1_FAST_8822C 0x7
+#define BIT_REG_LPF_C1_FAST_8822C(x)                                           \
+	(((x) & BIT_MASK_REG_LPF_C1_FAST_8822C)                                \
+	 << BIT_SHIFT_REG_LPF_C1_FAST_8822C)
+#define BITS_REG_LPF_C1_FAST_8822C                                             \
+	(BIT_MASK_REG_LPF_C1_FAST_8822C << BIT_SHIFT_REG_LPF_C1_FAST_8822C)
+#define BIT_CLEAR_REG_LPF_C1_FAST_8822C(x) ((x) & (~BITS_REG_LPF_C1_FAST_8822C))
+#define BIT_GET_REG_LPF_C1_FAST_8822C(x)                                       \
+	(((x) >> BIT_SHIFT_REG_LPF_C1_FAST_8822C) &                            \
+	 BIT_MASK_REG_LPF_C1_FAST_8822C)
+#define BIT_SET_REG_LPF_C1_FAST_8822C(x, v)                                    \
+	(BIT_CLEAR_REG_LPF_C1_FAST_8822C(x) | BIT_REG_LPF_C1_FAST_8822C(v))
+
+#define BIT_SHIFT_REG_LPF_R3_V1_8822C 0
+#define BIT_MASK_REG_LPF_R3_V1_8822C 0x3
+#define BIT_REG_LPF_R3_V1_8822C(x)                                             \
+	(((x) & BIT_MASK_REG_LPF_R3_V1_8822C) << BIT_SHIFT_REG_LPF_R3_V1_8822C)
+#define BITS_REG_LPF_R3_V1_8822C                                               \
+	(BIT_MASK_REG_LPF_R3_V1_8822C << BIT_SHIFT_REG_LPF_R3_V1_8822C)
+#define BIT_CLEAR_REG_LPF_R3_V1_8822C(x) ((x) & (~BITS_REG_LPF_R3_V1_8822C))
+#define BIT_GET_REG_LPF_R3_V1_8822C(x)                                         \
+	(((x) >> BIT_SHIFT_REG_LPF_R3_V1_8822C) & BIT_MASK_REG_LPF_R3_V1_8822C)
+#define BIT_SET_REG_LPF_R3_V1_8822C(x, v)                                      \
+	(BIT_CLEAR_REG_LPF_R3_V1_8822C(x) | BIT_REG_LPF_R3_V1_8822C(v))
+
+/* 2 REG_ANAPAR_MAC_2_8822C */
+
+#define BIT_SHIFT_AGPIO_DRV_V1_8822C 30
+#define BIT_MASK_AGPIO_DRV_V1_8822C 0x3
+#define BIT_AGPIO_DRV_V1_8822C(x)                                              \
+	(((x) & BIT_MASK_AGPIO_DRV_V1_8822C) << BIT_SHIFT_AGPIO_DRV_V1_8822C)
+#define BITS_AGPIO_DRV_V1_8822C                                                \
+	(BIT_MASK_AGPIO_DRV_V1_8822C << BIT_SHIFT_AGPIO_DRV_V1_8822C)
+#define BIT_CLEAR_AGPIO_DRV_V1_8822C(x) ((x) & (~BITS_AGPIO_DRV_V1_8822C))
+#define BIT_GET_AGPIO_DRV_V1_8822C(x)                                          \
+	(((x) >> BIT_SHIFT_AGPIO_DRV_V1_8822C) & BIT_MASK_AGPIO_DRV_V1_8822C)
+#define BIT_SET_AGPIO_DRV_V1_8822C(x, v)                                       \
+	(BIT_CLEAR_AGPIO_DRV_V1_8822C(x) | BIT_AGPIO_DRV_V1_8822C(v))
+
+#define BIT_AGPIO_GPO_V1_8822C BIT(29)
+#define BIT_AGPIO_GPE_V1_8822C BIT(28)
+#define BIT_SEL_CLK_8822C BIT(27)
+
+#define BIT_SHIFT_LS_XTAL_SEL_8822C 23
+#define BIT_MASK_LS_XTAL_SEL_8822C 0xf
+#define BIT_LS_XTAL_SEL_8822C(x)                                               \
+	(((x) & BIT_MASK_LS_XTAL_SEL_8822C) << BIT_SHIFT_LS_XTAL_SEL_8822C)
+#define BITS_LS_XTAL_SEL_8822C                                                 \
+	(BIT_MASK_LS_XTAL_SEL_8822C << BIT_SHIFT_LS_XTAL_SEL_8822C)
+#define BIT_CLEAR_LS_XTAL_SEL_8822C(x) ((x) & (~BITS_LS_XTAL_SEL_8822C))
+#define BIT_GET_LS_XTAL_SEL_8822C(x)                                           \
+	(((x) >> BIT_SHIFT_LS_XTAL_SEL_8822C) & BIT_MASK_LS_XTAL_SEL_8822C)
+#define BIT_SET_LS_XTAL_SEL_8822C(x, v)                                        \
+	(BIT_CLEAR_LS_XTAL_SEL_8822C(x) | BIT_LS_XTAL_SEL_8822C(v))
+
+#define BIT_LS_SDM_ORDER_V1_8822C BIT(22)
+#define BIT_LS_DELAY_PH_8822C BIT(21)
+#define BIT_DIVIDER_SEL_8822C BIT(20)
+
+#define BIT_SHIFT_PCODE_8822C 15
+#define BIT_MASK_PCODE_8822C 0x1f
+#define BIT_PCODE_8822C(x)                                                     \
+	(((x) & BIT_MASK_PCODE_8822C) << BIT_SHIFT_PCODE_8822C)
+#define BITS_PCODE_8822C (BIT_MASK_PCODE_8822C << BIT_SHIFT_PCODE_8822C)
+#define BIT_CLEAR_PCODE_8822C(x) ((x) & (~BITS_PCODE_8822C))
+#define BIT_GET_PCODE_8822C(x)                                                 \
+	(((x) >> BIT_SHIFT_PCODE_8822C) & BIT_MASK_PCODE_8822C)
+#define BIT_SET_PCODE_8822C(x, v)                                              \
+	(BIT_CLEAR_PCODE_8822C(x) | BIT_PCODE_8822C(v))
+
+#define BIT_SHIFT_NCODE_8822C 7
+#define BIT_MASK_NCODE_8822C 0xff
+#define BIT_NCODE_8822C(x)                                                     \
+	(((x) & BIT_MASK_NCODE_8822C) << BIT_SHIFT_NCODE_8822C)
+#define BITS_NCODE_8822C (BIT_MASK_NCODE_8822C << BIT_SHIFT_NCODE_8822C)
+#define BIT_CLEAR_NCODE_8822C(x) ((x) & (~BITS_NCODE_8822C))
+#define BIT_GET_NCODE_8822C(x)                                                 \
+	(((x) >> BIT_SHIFT_NCODE_8822C) & BIT_MASK_NCODE_8822C)
+#define BIT_SET_NCODE_8822C(x, v)                                              \
+	(BIT_CLEAR_NCODE_8822C(x) | BIT_NCODE_8822C(v))
+
+#define BIT_REG_BEACON_8822C BIT(6)
+#define BIT_REG_MBIASE_8822C BIT(5)
+
+#define BIT_SHIFT_REG_FAST_SEL_8822C 3
+#define BIT_MASK_REG_FAST_SEL_8822C 0x3
+#define BIT_REG_FAST_SEL_8822C(x)                                              \
+	(((x) & BIT_MASK_REG_FAST_SEL_8822C) << BIT_SHIFT_REG_FAST_SEL_8822C)
+#define BITS_REG_FAST_SEL_8822C                                                \
+	(BIT_MASK_REG_FAST_SEL_8822C << BIT_SHIFT_REG_FAST_SEL_8822C)
+#define BIT_CLEAR_REG_FAST_SEL_8822C(x) ((x) & (~BITS_REG_FAST_SEL_8822C))
+#define BIT_GET_REG_FAST_SEL_8822C(x)                                          \
+	(((x) >> BIT_SHIFT_REG_FAST_SEL_8822C) & BIT_MASK_REG_FAST_SEL_8822C)
+#define BIT_SET_REG_FAST_SEL_8822C(x, v)                                       \
+	(BIT_CLEAR_REG_FAST_SEL_8822C(x) | BIT_REG_FAST_SEL_8822C(v))
+
+#define BIT_REG_CK960M_EN_8822C BIT(2)
+#define BIT_REG_CK320M_EN_8822C BIT(1)
+#define BIT_REG_CK_5M_EN_8822C BIT(0)
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_ANAPAR_XTAL_0_8822C */
+#define BIT_XTAL_SC_LPS_8822C BIT(31)
+
+#define BIT_SHIFT_XTAL_SC_INIT_8822C 24
+#define BIT_MASK_XTAL_SC_INIT_8822C 0x7f
+#define BIT_XTAL_SC_INIT_8822C(x)                                              \
+	(((x) & BIT_MASK_XTAL_SC_INIT_8822C) << BIT_SHIFT_XTAL_SC_INIT_8822C)
+#define BITS_XTAL_SC_INIT_8822C                                                \
+	(BIT_MASK_XTAL_SC_INIT_8822C << BIT_SHIFT_XTAL_SC_INIT_8822C)
+#define BIT_CLEAR_XTAL_SC_INIT_8822C(x) ((x) & (~BITS_XTAL_SC_INIT_8822C))
+#define BIT_GET_XTAL_SC_INIT_8822C(x)                                          \
+	(((x) >> BIT_SHIFT_XTAL_SC_INIT_8822C) & BIT_MASK_XTAL_SC_INIT_8822C)
+#define BIT_SET_XTAL_SC_INIT_8822C(x, v)                                       \
+	(BIT_CLEAR_XTAL_SC_INIT_8822C(x) | BIT_XTAL_SC_INIT_8822C(v))
+
+#define BIT_SHIFT_XTAL_SC_XO_8822C 17
+#define BIT_MASK_XTAL_SC_XO_8822C 0x7f
+#define BIT_XTAL_SC_XO_8822C(x)                                                \
+	(((x) & BIT_MASK_XTAL_SC_XO_8822C) << BIT_SHIFT_XTAL_SC_XO_8822C)
+#define BITS_XTAL_SC_XO_8822C                                                  \
+	(BIT_MASK_XTAL_SC_XO_8822C << BIT_SHIFT_XTAL_SC_XO_8822C)
+#define BIT_CLEAR_XTAL_SC_XO_8822C(x) ((x) & (~BITS_XTAL_SC_XO_8822C))
+#define BIT_GET_XTAL_SC_XO_8822C(x)                                            \
+	(((x) >> BIT_SHIFT_XTAL_SC_XO_8822C) & BIT_MASK_XTAL_SC_XO_8822C)
+#define BIT_SET_XTAL_SC_XO_8822C(x, v)                                         \
+	(BIT_CLEAR_XTAL_SC_XO_8822C(x) | BIT_XTAL_SC_XO_8822C(v))
+
+#define BIT_SHIFT_XTAL_SC_XI_8822C 10
+#define BIT_MASK_XTAL_SC_XI_8822C 0x7f
+#define BIT_XTAL_SC_XI_8822C(x)                                                \
+	(((x) & BIT_MASK_XTAL_SC_XI_8822C) << BIT_SHIFT_XTAL_SC_XI_8822C)
+#define BITS_XTAL_SC_XI_8822C                                                  \
+	(BIT_MASK_XTAL_SC_XI_8822C << BIT_SHIFT_XTAL_SC_XI_8822C)
+#define BIT_CLEAR_XTAL_SC_XI_8822C(x) ((x) & (~BITS_XTAL_SC_XI_8822C))
+#define BIT_GET_XTAL_SC_XI_8822C(x)                                            \
+	(((x) >> BIT_SHIFT_XTAL_SC_XI_8822C) & BIT_MASK_XTAL_SC_XI_8822C)
+#define BIT_SET_XTAL_SC_XI_8822C(x, v)                                         \
+	(BIT_CLEAR_XTAL_SC_XI_8822C(x) | BIT_XTAL_SC_XI_8822C(v))
+
+#define BIT_SHIFT_XTAL_GMN_V3_8822C 5
+#define BIT_MASK_XTAL_GMN_V3_8822C 0x1f
+#define BIT_XTAL_GMN_V3_8822C(x)                                               \
+	(((x) & BIT_MASK_XTAL_GMN_V3_8822C) << BIT_SHIFT_XTAL_GMN_V3_8822C)
+#define BITS_XTAL_GMN_V3_8822C                                                 \
+	(BIT_MASK_XTAL_GMN_V3_8822C << BIT_SHIFT_XTAL_GMN_V3_8822C)
+#define BIT_CLEAR_XTAL_GMN_V3_8822C(x) ((x) & (~BITS_XTAL_GMN_V3_8822C))
+#define BIT_GET_XTAL_GMN_V3_8822C(x)                                           \
+	(((x) >> BIT_SHIFT_XTAL_GMN_V3_8822C) & BIT_MASK_XTAL_GMN_V3_8822C)
+#define BIT_SET_XTAL_GMN_V3_8822C(x, v)                                        \
+	(BIT_CLEAR_XTAL_GMN_V3_8822C(x) | BIT_XTAL_GMN_V3_8822C(v))
+
+#define BIT_SHIFT_XTAL_GMP_V3_8822C 0
+#define BIT_MASK_XTAL_GMP_V3_8822C 0x1f
+#define BIT_XTAL_GMP_V3_8822C(x)                                               \
+	(((x) & BIT_MASK_XTAL_GMP_V3_8822C) << BIT_SHIFT_XTAL_GMP_V3_8822C)
+#define BITS_XTAL_GMP_V3_8822C                                                 \
+	(BIT_MASK_XTAL_GMP_V3_8822C << BIT_SHIFT_XTAL_GMP_V3_8822C)
+#define BIT_CLEAR_XTAL_GMP_V3_8822C(x) ((x) & (~BITS_XTAL_GMP_V3_8822C))
+#define BIT_GET_XTAL_GMP_V3_8822C(x)                                           \
+	(((x) >> BIT_SHIFT_XTAL_GMP_V3_8822C) & BIT_MASK_XTAL_GMP_V3_8822C)
+#define BIT_SET_XTAL_GMP_V3_8822C(x, v)                                        \
+	(BIT_CLEAR_XTAL_GMP_V3_8822C(x) | BIT_XTAL_GMP_V3_8822C(v))
+
+/* 2 REG_ANAPAR_XTAL_1_8822C */
+#define BIT_XTAL_SEL_TOK_V1_8822C BIT(31)
+#define BIT_XTAL_DELAY_DIGI_V2_8822C BIT(30)
+#define BIT_XTAL_DELAY_USB_V2_8822C BIT(29)
+#define BIT_XTAL_DELAY_AFE_V2_8822C BIT(28)
+
+#define BIT_SHIFT_XTAL_DRV_DIGI_V2_8822C 26
+#define BIT_MASK_XTAL_DRV_DIGI_V2_8822C 0x3
+#define BIT_XTAL_DRV_DIGI_V2_8822C(x)                                          \
+	(((x) & BIT_MASK_XTAL_DRV_DIGI_V2_8822C)                               \
+	 << BIT_SHIFT_XTAL_DRV_DIGI_V2_8822C)
+#define BITS_XTAL_DRV_DIGI_V2_8822C                                            \
+	(BIT_MASK_XTAL_DRV_DIGI_V2_8822C << BIT_SHIFT_XTAL_DRV_DIGI_V2_8822C)
+#define BIT_CLEAR_XTAL_DRV_DIGI_V2_8822C(x)                                    \
+	((x) & (~BITS_XTAL_DRV_DIGI_V2_8822C))
+#define BIT_GET_XTAL_DRV_DIGI_V2_8822C(x)                                      \
+	(((x) >> BIT_SHIFT_XTAL_DRV_DIGI_V2_8822C) &                           \
+	 BIT_MASK_XTAL_DRV_DIGI_V2_8822C)
+#define BIT_SET_XTAL_DRV_DIGI_V2_8822C(x, v)                                   \
+	(BIT_CLEAR_XTAL_DRV_DIGI_V2_8822C(x) | BIT_XTAL_DRV_DIGI_V2_8822C(v))
+
+#define BIT_EN_XTAL_DRV_LPS_8822C BIT(25)
+#define BIT_EN_XTAL_DRV_DIGI_V2_8822C BIT(24)
+
+#define BIT_SHIFT_XTAL_DRV_USB_8822C 22
+#define BIT_MASK_XTAL_DRV_USB_8822C 0x3
+#define BIT_XTAL_DRV_USB_8822C(x)                                              \
+	(((x) & BIT_MASK_XTAL_DRV_USB_8822C) << BIT_SHIFT_XTAL_DRV_USB_8822C)
+#define BITS_XTAL_DRV_USB_8822C                                                \
+	(BIT_MASK_XTAL_DRV_USB_8822C << BIT_SHIFT_XTAL_DRV_USB_8822C)
+#define BIT_CLEAR_XTAL_DRV_USB_8822C(x) ((x) & (~BITS_XTAL_DRV_USB_8822C))
+#define BIT_GET_XTAL_DRV_USB_8822C(x)                                          \
+	(((x) >> BIT_SHIFT_XTAL_DRV_USB_8822C) & BIT_MASK_XTAL_DRV_USB_8822C)
+#define BIT_SET_XTAL_DRV_USB_8822C(x, v)                                       \
+	(BIT_CLEAR_XTAL_DRV_USB_8822C(x) | BIT_XTAL_DRV_USB_8822C(v))
+
+#define BIT_EN_XTAL_DRV_USB_8822C BIT(21)
+
+#define BIT_SHIFT_XTAL_DRV_AFE_V2_8822C 19
+#define BIT_MASK_XTAL_DRV_AFE_V2_8822C 0x3
+#define BIT_XTAL_DRV_AFE_V2_8822C(x)                                           \
+	(((x) & BIT_MASK_XTAL_DRV_AFE_V2_8822C)                                \
+	 << BIT_SHIFT_XTAL_DRV_AFE_V2_8822C)
+#define BITS_XTAL_DRV_AFE_V2_8822C                                             \
+	(BIT_MASK_XTAL_DRV_AFE_V2_8822C << BIT_SHIFT_XTAL_DRV_AFE_V2_8822C)
+#define BIT_CLEAR_XTAL_DRV_AFE_V2_8822C(x) ((x) & (~BITS_XTAL_DRV_AFE_V2_8822C))
+#define BIT_GET_XTAL_DRV_AFE_V2_8822C(x)                                       \
+	(((x) >> BIT_SHIFT_XTAL_DRV_AFE_V2_8822C) &                            \
+	 BIT_MASK_XTAL_DRV_AFE_V2_8822C)
+#define BIT_SET_XTAL_DRV_AFE_V2_8822C(x, v)                                    \
+	(BIT_CLEAR_XTAL_DRV_AFE_V2_8822C(x) | BIT_XTAL_DRV_AFE_V2_8822C(v))
+
+#define BIT_EN_XTAL_DRV_AFE_8822C BIT(18)
+
+#define BIT_SHIFT_XTAL_DRV_RF2_V2_8822C 16
+#define BIT_MASK_XTAL_DRV_RF2_V2_8822C 0x3
+#define BIT_XTAL_DRV_RF2_V2_8822C(x)                                           \
+	(((x) & BIT_MASK_XTAL_DRV_RF2_V2_8822C)                                \
+	 << BIT_SHIFT_XTAL_DRV_RF2_V2_8822C)
+#define BITS_XTAL_DRV_RF2_V2_8822C                                             \
+	(BIT_MASK_XTAL_DRV_RF2_V2_8822C << BIT_SHIFT_XTAL_DRV_RF2_V2_8822C)
+#define BIT_CLEAR_XTAL_DRV_RF2_V2_8822C(x) ((x) & (~BITS_XTAL_DRV_RF2_V2_8822C))
+#define BIT_GET_XTAL_DRV_RF2_V2_8822C(x)                                       \
+	(((x) >> BIT_SHIFT_XTAL_DRV_RF2_V2_8822C) &                            \
+	 BIT_MASK_XTAL_DRV_RF2_V2_8822C)
+#define BIT_SET_XTAL_DRV_RF2_V2_8822C(x, v)                                    \
+	(BIT_CLEAR_XTAL_DRV_RF2_V2_8822C(x) | BIT_XTAL_DRV_RF2_V2_8822C(v))
+
+#define BIT_EN_XTAL_DRV_RF2_8822C BIT(15)
+
+#define BIT_SHIFT_XTAL_DRV_RF1_8822C 13
+#define BIT_MASK_XTAL_DRV_RF1_8822C 0x3
+#define BIT_XTAL_DRV_RF1_8822C(x)                                              \
+	(((x) & BIT_MASK_XTAL_DRV_RF1_8822C) << BIT_SHIFT_XTAL_DRV_RF1_8822C)
+#define BITS_XTAL_DRV_RF1_8822C                                                \
+	(BIT_MASK_XTAL_DRV_RF1_8822C << BIT_SHIFT_XTAL_DRV_RF1_8822C)
+#define BIT_CLEAR_XTAL_DRV_RF1_8822C(x) ((x) & (~BITS_XTAL_DRV_RF1_8822C))
+#define BIT_GET_XTAL_DRV_RF1_8822C(x)                                          \
+	(((x) >> BIT_SHIFT_XTAL_DRV_RF1_8822C) & BIT_MASK_XTAL_DRV_RF1_8822C)
+#define BIT_SET_XTAL_DRV_RF1_8822C(x, v)                                       \
+	(BIT_CLEAR_XTAL_DRV_RF1_8822C(x) | BIT_XTAL_DRV_RF1_8822C(v))
+
+#define BIT_EN_XTAL_DRV_RF1_8822C BIT(12)
+#define BIT_XTAL_DRV_RF_LATCH_V4_8822C BIT(11)
+#define BIT_XTAL_GM_SEP_V3_8822C BIT(10)
+#define BIT_XQSEL_RF_AWAKE_V3_8822C BIT(9)
+#define BIT_XQSEL_RF_INITIAL_V3_8822C BIT(8)
+#define BIT_XQSEL_V2_8822C BIT(7)
+#define BIT_GATED_XTAL_OK0_V2_8822C BIT(6)
+
+#define BIT_SHIFT_XTAL_SC_LPS_V2_8822C 0
+#define BIT_MASK_XTAL_SC_LPS_V2_8822C 0x3f
+#define BIT_XTAL_SC_LPS_V2_8822C(x)                                            \
+	(((x) & BIT_MASK_XTAL_SC_LPS_V2_8822C)                                 \
+	 << BIT_SHIFT_XTAL_SC_LPS_V2_8822C)
+#define BITS_XTAL_SC_LPS_V2_8822C                                              \
+	(BIT_MASK_XTAL_SC_LPS_V2_8822C << BIT_SHIFT_XTAL_SC_LPS_V2_8822C)
+#define BIT_CLEAR_XTAL_SC_LPS_V2_8822C(x) ((x) & (~BITS_XTAL_SC_LPS_V2_8822C))
+#define BIT_GET_XTAL_SC_LPS_V2_8822C(x)                                        \
+	(((x) >> BIT_SHIFT_XTAL_SC_LPS_V2_8822C) &                             \
+	 BIT_MASK_XTAL_SC_LPS_V2_8822C)
+#define BIT_SET_XTAL_SC_LPS_V2_8822C(x, v)                                     \
+	(BIT_CLEAR_XTAL_SC_LPS_V2_8822C(x) | BIT_XTAL_SC_LPS_V2_8822C(v))
+
+/* 2 REG_ANAPAR_XTAL_2_8822C */
+#define BIT_XTAL_AAC_CAP_8822C BIT(31)
+
+#define BIT_SHIFT_XTAL_PDSW_8822C 29
+#define BIT_MASK_XTAL_PDSW_8822C 0x3
+#define BIT_XTAL_PDSW_8822C(x)                                                 \
+	(((x) & BIT_MASK_XTAL_PDSW_8822C) << BIT_SHIFT_XTAL_PDSW_8822C)
+#define BITS_XTAL_PDSW_8822C                                                   \
+	(BIT_MASK_XTAL_PDSW_8822C << BIT_SHIFT_XTAL_PDSW_8822C)
+#define BIT_CLEAR_XTAL_PDSW_8822C(x) ((x) & (~BITS_XTAL_PDSW_8822C))
+#define BIT_GET_XTAL_PDSW_8822C(x)                                             \
+	(((x) >> BIT_SHIFT_XTAL_PDSW_8822C) & BIT_MASK_XTAL_PDSW_8822C)
+#define BIT_SET_XTAL_PDSW_8822C(x, v)                                          \
+	(BIT_CLEAR_XTAL_PDSW_8822C(x) | BIT_XTAL_PDSW_8822C(v))
+
+#define BIT_SHIFT_XTAL_LPS_BUF_VB_8822C 27
+#define BIT_MASK_XTAL_LPS_BUF_VB_8822C 0x3
+#define BIT_XTAL_LPS_BUF_VB_8822C(x)                                           \
+	(((x) & BIT_MASK_XTAL_LPS_BUF_VB_8822C)                                \
+	 << BIT_SHIFT_XTAL_LPS_BUF_VB_8822C)
+#define BITS_XTAL_LPS_BUF_VB_8822C                                             \
+	(BIT_MASK_XTAL_LPS_BUF_VB_8822C << BIT_SHIFT_XTAL_LPS_BUF_VB_8822C)
+#define BIT_CLEAR_XTAL_LPS_BUF_VB_8822C(x) ((x) & (~BITS_XTAL_LPS_BUF_VB_8822C))
+#define BIT_GET_XTAL_LPS_BUF_VB_8822C(x)                                       \
+	(((x) >> BIT_SHIFT_XTAL_LPS_BUF_VB_8822C) &                            \
+	 BIT_MASK_XTAL_LPS_BUF_VB_8822C)
+#define BIT_SET_XTAL_LPS_BUF_VB_8822C(x, v)                                    \
+	(BIT_CLEAR_XTAL_LPS_BUF_VB_8822C(x) | BIT_XTAL_LPS_BUF_VB_8822C(v))
+
+#define BIT_XTAL_PDCK_MANU_8822C BIT(26)
+#define BIT_XTAL_PDCK_OK_MANU_8822C BIT(25)
+
+#define BIT_SHIFT_XTAL_VREF_SEL_8822C 20
+#define BIT_MASK_XTAL_VREF_SEL_8822C 0x1f
+#define BIT_XTAL_VREF_SEL_8822C(x)                                             \
+	(((x) & BIT_MASK_XTAL_VREF_SEL_8822C) << BIT_SHIFT_XTAL_VREF_SEL_8822C)
+#define BITS_XTAL_VREF_SEL_8822C                                               \
+	(BIT_MASK_XTAL_VREF_SEL_8822C << BIT_SHIFT_XTAL_VREF_SEL_8822C)
+#define BIT_CLEAR_XTAL_VREF_SEL_8822C(x) ((x) & (~BITS_XTAL_VREF_SEL_8822C))
+#define BIT_GET_XTAL_VREF_SEL_8822C(x)                                         \
+	(((x) >> BIT_SHIFT_XTAL_VREF_SEL_8822C) & BIT_MASK_XTAL_VREF_SEL_8822C)
+#define BIT_SET_XTAL_VREF_SEL_8822C(x, v)                                      \
+	(BIT_CLEAR_XTAL_VREF_SEL_8822C(x) | BIT_XTAL_VREF_SEL_8822C(v))
+
+#define BIT_EN_XTAL_PDCK_VREF_8822C BIT(19)
+#define BIT_XTAL_SEL_PWR_V1_8822C BIT(18)
+#define BIT_XTAL_LPS_DIVISOR_8822C BIT(17)
+#define BIT_XTAL_CKDIGI_SEL_8822C BIT(16)
+#define BIT_EN_XTAL_LPS_CLK_8822C BIT(15)
+#define BIT_EN_XTAL_SCHMITT_8822C BIT(14)
+#define BIT_XTAL_PK_SEL_OFFSET_8822C BIT(13)
+
+#define BIT_SHIFT_XTAL_MANU_PK_SEL_8822C 11
+#define BIT_MASK_XTAL_MANU_PK_SEL_8822C 0x3
+#define BIT_XTAL_MANU_PK_SEL_8822C(x)                                          \
+	(((x) & BIT_MASK_XTAL_MANU_PK_SEL_8822C)                               \
+	 << BIT_SHIFT_XTAL_MANU_PK_SEL_8822C)
+#define BITS_XTAL_MANU_PK_SEL_8822C                                            \
+	(BIT_MASK_XTAL_MANU_PK_SEL_8822C << BIT_SHIFT_XTAL_MANU_PK_SEL_8822C)
+#define BIT_CLEAR_XTAL_MANU_PK_SEL_8822C(x)                                    \
+	((x) & (~BITS_XTAL_MANU_PK_SEL_8822C))
+#define BIT_GET_XTAL_MANU_PK_SEL_8822C(x)                                      \
+	(((x) >> BIT_SHIFT_XTAL_MANU_PK_SEL_8822C) &                           \
+	 BIT_MASK_XTAL_MANU_PK_SEL_8822C)
+#define BIT_SET_XTAL_MANU_PK_SEL_8822C(x, v)                                   \
+	(BIT_CLEAR_XTAL_MANU_PK_SEL_8822C(x) | BIT_XTAL_MANU_PK_SEL_8822C(v))
+
+#define BIT_XTAL_AACK_PK_MANU_8822C BIT(10)
+#define BIT_EN_XTAL_AAC_PKDET_V1_8822C BIT(9)
+#define BIT_EN_XTAL_AAC_GM_V1_8822C BIT(8)
+#define BIT_XTAL_LDO_OPVB_SEL_8822C BIT(7)
+#define BIT_XTAL_LDO_NC_8822C BIT(6)
+
+#define BIT_SHIFT_XTAL_LDO_VREF_V2_8822C 3
+#define BIT_MASK_XTAL_LDO_VREF_V2_8822C 0x7
+#define BIT_XTAL_LDO_VREF_V2_8822C(x)                                          \
+	(((x) & BIT_MASK_XTAL_LDO_VREF_V2_8822C)                               \
+	 << BIT_SHIFT_XTAL_LDO_VREF_V2_8822C)
+#define BITS_XTAL_LDO_VREF_V2_8822C                                            \
+	(BIT_MASK_XTAL_LDO_VREF_V2_8822C << BIT_SHIFT_XTAL_LDO_VREF_V2_8822C)
+#define BIT_CLEAR_XTAL_LDO_VREF_V2_8822C(x)                                    \
+	((x) & (~BITS_XTAL_LDO_VREF_V2_8822C))
+#define BIT_GET_XTAL_LDO_VREF_V2_8822C(x)                                      \
+	(((x) >> BIT_SHIFT_XTAL_LDO_VREF_V2_8822C) &                           \
+	 BIT_MASK_XTAL_LDO_VREF_V2_8822C)
+#define BIT_SET_XTAL_LDO_VREF_V2_8822C(x, v)                                   \
+	(BIT_CLEAR_XTAL_LDO_VREF_V2_8822C(x) | BIT_XTAL_LDO_VREF_V2_8822C(v))
+
+#define BIT_XTAL_LPMODE_V1_8822C BIT(2)
+
+#define BIT_SHIFT_XTAL_SEL_TOK_V3_8822C 0
+#define BIT_MASK_XTAL_SEL_TOK_V3_8822C 0x3
+#define BIT_XTAL_SEL_TOK_V3_8822C(x)                                           \
+	(((x) & BIT_MASK_XTAL_SEL_TOK_V3_8822C)                                \
+	 << BIT_SHIFT_XTAL_SEL_TOK_V3_8822C)
+#define BITS_XTAL_SEL_TOK_V3_8822C                                             \
+	(BIT_MASK_XTAL_SEL_TOK_V3_8822C << BIT_SHIFT_XTAL_SEL_TOK_V3_8822C)
+#define BIT_CLEAR_XTAL_SEL_TOK_V3_8822C(x) ((x) & (~BITS_XTAL_SEL_TOK_V3_8822C))
+#define BIT_GET_XTAL_SEL_TOK_V3_8822C(x)                                       \
+	(((x) >> BIT_SHIFT_XTAL_SEL_TOK_V3_8822C) &                            \
+	 BIT_MASK_XTAL_SEL_TOK_V3_8822C)
+#define BIT_SET_XTAL_SEL_TOK_V3_8822C(x, v)                                    \
+	(BIT_CLEAR_XTAL_SEL_TOK_V3_8822C(x) | BIT_XTAL_SEL_TOK_V3_8822C(v))
+
+/* 2 REG_ANAPAR_XTAL_3_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+#define BIT_SHIFT_XTAL_DUMMY_V1_8822C 7
+#define BIT_MASK_XTAL_DUMMY_V1_8822C 0x3f
+#define BIT_XTAL_DUMMY_V1_8822C(x)                                             \
+	(((x) & BIT_MASK_XTAL_DUMMY_V1_8822C) << BIT_SHIFT_XTAL_DUMMY_V1_8822C)
+#define BITS_XTAL_DUMMY_V1_8822C                                               \
+	(BIT_MASK_XTAL_DUMMY_V1_8822C << BIT_SHIFT_XTAL_DUMMY_V1_8822C)
+#define BIT_CLEAR_XTAL_DUMMY_V1_8822C(x) ((x) & (~BITS_XTAL_DUMMY_V1_8822C))
+#define BIT_GET_XTAL_DUMMY_V1_8822C(x)                                         \
+	(((x) >> BIT_SHIFT_XTAL_DUMMY_V1_8822C) & BIT_MASK_XTAL_DUMMY_V1_8822C)
+#define BIT_SET_XTAL_DUMMY_V1_8822C(x, v)                                      \
+	(BIT_CLEAR_XTAL_DUMMY_V1_8822C(x) | BIT_XTAL_DUMMY_V1_8822C(v))
+
+#define BIT_XTAL_EN_LNBUF_8822C BIT(6)
+#define BIT_XTAL__AAC_TIE_MID_8822C BIT(5)
+
+#define BIT_SHIFT_XTAL_AAC_OPCUR_8822C 3
+#define BIT_MASK_XTAL_AAC_OPCUR_8822C 0x3
+#define BIT_XTAL_AAC_OPCUR_8822C(x)                                            \
+	(((x) & BIT_MASK_XTAL_AAC_OPCUR_8822C)                                 \
+	 << BIT_SHIFT_XTAL_AAC_OPCUR_8822C)
+#define BITS_XTAL_AAC_OPCUR_8822C                                              \
+	(BIT_MASK_XTAL_AAC_OPCUR_8822C << BIT_SHIFT_XTAL_AAC_OPCUR_8822C)
+#define BIT_CLEAR_XTAL_AAC_OPCUR_8822C(x) ((x) & (~BITS_XTAL_AAC_OPCUR_8822C))
+#define BIT_GET_XTAL_AAC_OPCUR_8822C(x)                                        \
+	(((x) >> BIT_SHIFT_XTAL_AAC_OPCUR_8822C) &                             \
+	 BIT_MASK_XTAL_AAC_OPCUR_8822C)
+#define BIT_SET_XTAL_AAC_OPCUR_8822C(x, v)                                     \
+	(BIT_CLEAR_XTAL_AAC_OPCUR_8822C(x) | BIT_XTAL_AAC_OPCUR_8822C(v))
+
+#define BIT_SHIFT_XTAL_AAC_IOFFSET_8822C 1
+#define BIT_MASK_XTAL_AAC_IOFFSET_8822C 0x3
+#define BIT_XTAL_AAC_IOFFSET_8822C(x)                                          \
+	(((x) & BIT_MASK_XTAL_AAC_IOFFSET_8822C)                               \
+	 << BIT_SHIFT_XTAL_AAC_IOFFSET_8822C)
+#define BITS_XTAL_AAC_IOFFSET_8822C                                            \
+	(BIT_MASK_XTAL_AAC_IOFFSET_8822C << BIT_SHIFT_XTAL_AAC_IOFFSET_8822C)
+#define BIT_CLEAR_XTAL_AAC_IOFFSET_8822C(x)                                    \
+	((x) & (~BITS_XTAL_AAC_IOFFSET_8822C))
+#define BIT_GET_XTAL_AAC_IOFFSET_8822C(x)                                      \
+	(((x) >> BIT_SHIFT_XTAL_AAC_IOFFSET_8822C) &                           \
+	 BIT_MASK_XTAL_AAC_IOFFSET_8822C)
+#define BIT_SET_XTAL_AAC_IOFFSET_8822C(x, v)                                   \
+	(BIT_CLEAR_XTAL_AAC_IOFFSET_8822C(x) | BIT_XTAL_AAC_IOFFSET_8822C(v))
+
+#define BIT_XTAL_AAC_CAP_V1_8822C BIT(0)
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_ANAPAR_XTAL_AACK_0_8822C */
+#define BIT_XAAC_LPOW_8822C BIT(31)
+
+#define BIT_SHIFT_AAC_MODE_8822C 29
+#define BIT_MASK_AAC_MODE_8822C 0x3
+#define BIT_AAC_MODE_8822C(x)                                                  \
+	(((x) & BIT_MASK_AAC_MODE_8822C) << BIT_SHIFT_AAC_MODE_8822C)
+#define BITS_AAC_MODE_8822C                                                    \
+	(BIT_MASK_AAC_MODE_8822C << BIT_SHIFT_AAC_MODE_8822C)
+#define BIT_CLEAR_AAC_MODE_8822C(x) ((x) & (~BITS_AAC_MODE_8822C))
+#define BIT_GET_AAC_MODE_8822C(x)                                              \
+	(((x) >> BIT_SHIFT_AAC_MODE_8822C) & BIT_MASK_AAC_MODE_8822C)
+#define BIT_SET_AAC_MODE_8822C(x, v)                                           \
+	(BIT_CLEAR_AAC_MODE_8822C(x) | BIT_AAC_MODE_8822C(v))
+
+#define BIT_EN_XTAL_AAC_TRIG_8822C BIT(28)
+#define BIT_EN_XTAL_AAC_8822C BIT(27)
+#define BIT_EN_XTAL_AAC_DIGI_8822C BIT(26)
+
+#define BIT_SHIFT_GM_MANUAL_8822C 21
+#define BIT_MASK_GM_MANUAL_8822C 0x1f
+#define BIT_GM_MANUAL_8822C(x)                                                 \
+	(((x) & BIT_MASK_GM_MANUAL_8822C) << BIT_SHIFT_GM_MANUAL_8822C)
+#define BITS_GM_MANUAL_8822C                                                   \
+	(BIT_MASK_GM_MANUAL_8822C << BIT_SHIFT_GM_MANUAL_8822C)
+#define BIT_CLEAR_GM_MANUAL_8822C(x) ((x) & (~BITS_GM_MANUAL_8822C))
+#define BIT_GET_GM_MANUAL_8822C(x)                                             \
+	(((x) >> BIT_SHIFT_GM_MANUAL_8822C) & BIT_MASK_GM_MANUAL_8822C)
+#define BIT_SET_GM_MANUAL_8822C(x, v)                                          \
+	(BIT_CLEAR_GM_MANUAL_8822C(x) | BIT_GM_MANUAL_8822C(v))
+
+#define BIT_SHIFT_GM_STUP_8822C 16
+#define BIT_MASK_GM_STUP_8822C 0x1f
+#define BIT_GM_STUP_8822C(x)                                                   \
+	(((x) & BIT_MASK_GM_STUP_8822C) << BIT_SHIFT_GM_STUP_8822C)
+#define BITS_GM_STUP_8822C (BIT_MASK_GM_STUP_8822C << BIT_SHIFT_GM_STUP_8822C)
+#define BIT_CLEAR_GM_STUP_8822C(x) ((x) & (~BITS_GM_STUP_8822C))
+#define BIT_GET_GM_STUP_8822C(x)                                               \
+	(((x) >> BIT_SHIFT_GM_STUP_8822C) & BIT_MASK_GM_STUP_8822C)
+#define BIT_SET_GM_STUP_8822C(x, v)                                            \
+	(BIT_CLEAR_GM_STUP_8822C(x) | BIT_GM_STUP_8822C(v))
+
+#define BIT_SHIFT_XTAL_CK_SET_8822C 13
+#define BIT_MASK_XTAL_CK_SET_8822C 0x7
+#define BIT_XTAL_CK_SET_8822C(x)                                               \
+	(((x) & BIT_MASK_XTAL_CK_SET_8822C) << BIT_SHIFT_XTAL_CK_SET_8822C)
+#define BITS_XTAL_CK_SET_8822C                                                 \
+	(BIT_MASK_XTAL_CK_SET_8822C << BIT_SHIFT_XTAL_CK_SET_8822C)
+#define BIT_CLEAR_XTAL_CK_SET_8822C(x) ((x) & (~BITS_XTAL_CK_SET_8822C))
+#define BIT_GET_XTAL_CK_SET_8822C(x)                                           \
+	(((x) >> BIT_SHIFT_XTAL_CK_SET_8822C) & BIT_MASK_XTAL_CK_SET_8822C)
+#define BIT_SET_XTAL_CK_SET_8822C(x, v)                                        \
+	(BIT_CLEAR_XTAL_CK_SET_8822C(x) | BIT_XTAL_CK_SET_8822C(v))
+
+#define BIT_SHIFT_GM_INIT_8822C 8
+#define BIT_MASK_GM_INIT_8822C 0x1f
+#define BIT_GM_INIT_8822C(x)                                                   \
+	(((x) & BIT_MASK_GM_INIT_8822C) << BIT_SHIFT_GM_INIT_8822C)
+#define BITS_GM_INIT_8822C (BIT_MASK_GM_INIT_8822C << BIT_SHIFT_GM_INIT_8822C)
+#define BIT_CLEAR_GM_INIT_8822C(x) ((x) & (~BITS_GM_INIT_8822C))
+#define BIT_GET_GM_INIT_8822C(x)                                               \
+	(((x) >> BIT_SHIFT_GM_INIT_8822C) & BIT_MASK_GM_INIT_8822C)
+#define BIT_SET_GM_INIT_8822C(x, v)                                            \
+	(BIT_CLEAR_GM_INIT_8822C(x) | BIT_GM_INIT_8822C(v))
+
+#define BIT_GM_STEP_8822C BIT(7)
+
+#define BIT_SHIFT_XAAC_GM_OFFSET_8822C 2
+#define BIT_MASK_XAAC_GM_OFFSET_8822C 0x1f
+#define BIT_XAAC_GM_OFFSET_8822C(x)                                            \
+	(((x) & BIT_MASK_XAAC_GM_OFFSET_8822C)                                 \
+	 << BIT_SHIFT_XAAC_GM_OFFSET_8822C)
+#define BITS_XAAC_GM_OFFSET_8822C                                              \
+	(BIT_MASK_XAAC_GM_OFFSET_8822C << BIT_SHIFT_XAAC_GM_OFFSET_8822C)
+#define BIT_CLEAR_XAAC_GM_OFFSET_8822C(x) ((x) & (~BITS_XAAC_GM_OFFSET_8822C))
+#define BIT_GET_XAAC_GM_OFFSET_8822C(x)                                        \
+	(((x) >> BIT_SHIFT_XAAC_GM_OFFSET_8822C) &                             \
+	 BIT_MASK_XAAC_GM_OFFSET_8822C)
+#define BIT_SET_XAAC_GM_OFFSET_8822C(x, v)                                     \
+	(BIT_CLEAR_XAAC_GM_OFFSET_8822C(x) | BIT_XAAC_GM_OFFSET_8822C(v))
+
+#define BIT_OFFSET_PLUS_8822C BIT(1)
+#define BIT_RESET_N_8822C BIT(0)
+
+/* 2 REG_ANAPAR_XTAL_AACK_1_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+#define BIT_SHIFT_PK_END_AR_8822C 3
+#define BIT_MASK_PK_END_AR_8822C 0x3
+#define BIT_PK_END_AR_8822C(x)                                                 \
+	(((x) & BIT_MASK_PK_END_AR_8822C) << BIT_SHIFT_PK_END_AR_8822C)
+#define BITS_PK_END_AR_8822C                                                   \
+	(BIT_MASK_PK_END_AR_8822C << BIT_SHIFT_PK_END_AR_8822C)
+#define BIT_CLEAR_PK_END_AR_8822C(x) ((x) & (~BITS_PK_END_AR_8822C))
+#define BIT_GET_PK_END_AR_8822C(x)                                             \
+	(((x) >> BIT_SHIFT_PK_END_AR_8822C) & BIT_MASK_PK_END_AR_8822C)
+#define BIT_SET_PK_END_AR_8822C(x, v)                                          \
+	(BIT_CLEAR_PK_END_AR_8822C(x) | BIT_PK_END_AR_8822C(v))
+
+#define BIT_SHIFT_PK_START_AR_8822C 1
+#define BIT_MASK_PK_START_AR_8822C 0x3
+#define BIT_PK_START_AR_8822C(x)                                               \
+	(((x) & BIT_MASK_PK_START_AR_8822C) << BIT_SHIFT_PK_START_AR_8822C)
+#define BITS_PK_START_AR_8822C                                                 \
+	(BIT_MASK_PK_START_AR_8822C << BIT_SHIFT_PK_START_AR_8822C)
+#define BIT_CLEAR_PK_START_AR_8822C(x) ((x) & (~BITS_PK_START_AR_8822C))
+#define BIT_GET_PK_START_AR_8822C(x)                                           \
+	(((x) >> BIT_SHIFT_PK_START_AR_8822C) & BIT_MASK_PK_START_AR_8822C)
+#define BIT_SET_PK_START_AR_8822C(x, v)                                        \
+	(BIT_CLEAR_PK_START_AR_8822C(x) | BIT_PK_START_AR_8822C(v))
+
+#define BIT_XAAC_LUT_MANUAL_EN_8822C BIT(0)
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_ANAPAR_XTAL_MODE_DECODER_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+#define BIT_SHIFT_XTAL_LDO_LPS_8822C 21
+#define BIT_MASK_XTAL_LDO_LPS_8822C 0x7
+#define BIT_XTAL_LDO_LPS_8822C(x)                                              \
+	(((x) & BIT_MASK_XTAL_LDO_LPS_8822C) << BIT_SHIFT_XTAL_LDO_LPS_8822C)
+#define BITS_XTAL_LDO_LPS_8822C                                                \
+	(BIT_MASK_XTAL_LDO_LPS_8822C << BIT_SHIFT_XTAL_LDO_LPS_8822C)
+#define BIT_CLEAR_XTAL_LDO_LPS_8822C(x) ((x) & (~BITS_XTAL_LDO_LPS_8822C))
+#define BIT_GET_XTAL_LDO_LPS_8822C(x)                                          \
+	(((x) >> BIT_SHIFT_XTAL_LDO_LPS_8822C) & BIT_MASK_XTAL_LDO_LPS_8822C)
+#define BIT_SET_XTAL_LDO_LPS_8822C(x, v)                                       \
+	(BIT_CLEAR_XTAL_LDO_LPS_8822C(x) | BIT_XTAL_LDO_LPS_8822C(v))
+
+#define BIT_SHIFT_XTAL_WAIT_CYC_8822C 15
+#define BIT_MASK_XTAL_WAIT_CYC_8822C 0x3f
+#define BIT_XTAL_WAIT_CYC_8822C(x)                                             \
+	(((x) & BIT_MASK_XTAL_WAIT_CYC_8822C) << BIT_SHIFT_XTAL_WAIT_CYC_8822C)
+#define BITS_XTAL_WAIT_CYC_8822C                                               \
+	(BIT_MASK_XTAL_WAIT_CYC_8822C << BIT_SHIFT_XTAL_WAIT_CYC_8822C)
+#define BIT_CLEAR_XTAL_WAIT_CYC_8822C(x) ((x) & (~BITS_XTAL_WAIT_CYC_8822C))
+#define BIT_GET_XTAL_WAIT_CYC_8822C(x)                                         \
+	(((x) >> BIT_SHIFT_XTAL_WAIT_CYC_8822C) & BIT_MASK_XTAL_WAIT_CYC_8822C)
+#define BIT_SET_XTAL_WAIT_CYC_8822C(x, v)                                      \
+	(BIT_CLEAR_XTAL_WAIT_CYC_8822C(x) | BIT_XTAL_WAIT_CYC_8822C(v))
+
+#define BIT_SHIFT_XTAL_LDO_OK_8822C 12
+#define BIT_MASK_XTAL_LDO_OK_8822C 0x7
+#define BIT_XTAL_LDO_OK_8822C(x)                                               \
+	(((x) & BIT_MASK_XTAL_LDO_OK_8822C) << BIT_SHIFT_XTAL_LDO_OK_8822C)
+#define BITS_XTAL_LDO_OK_8822C                                                 \
+	(BIT_MASK_XTAL_LDO_OK_8822C << BIT_SHIFT_XTAL_LDO_OK_8822C)
+#define BIT_CLEAR_XTAL_LDO_OK_8822C(x) ((x) & (~BITS_XTAL_LDO_OK_8822C))
+#define BIT_GET_XTAL_LDO_OK_8822C(x)                                           \
+	(((x) >> BIT_SHIFT_XTAL_LDO_OK_8822C) & BIT_MASK_XTAL_LDO_OK_8822C)
+#define BIT_SET_XTAL_LDO_OK_8822C(x, v)                                        \
+	(BIT_CLEAR_XTAL_LDO_OK_8822C(x) | BIT_XTAL_LDO_OK_8822C(v))
+
+#define BIT_XTAL_MD_LPOW_8822C BIT(11)
+
+#define BIT_SHIFT_XTAL_OV_RATIO_8822C 9
+#define BIT_MASK_XTAL_OV_RATIO_8822C 0x3
+#define BIT_XTAL_OV_RATIO_8822C(x)                                             \
+	(((x) & BIT_MASK_XTAL_OV_RATIO_8822C) << BIT_SHIFT_XTAL_OV_RATIO_8822C)
+#define BITS_XTAL_OV_RATIO_8822C                                               \
+	(BIT_MASK_XTAL_OV_RATIO_8822C << BIT_SHIFT_XTAL_OV_RATIO_8822C)
+#define BIT_CLEAR_XTAL_OV_RATIO_8822C(x) ((x) & (~BITS_XTAL_OV_RATIO_8822C))
+#define BIT_GET_XTAL_OV_RATIO_8822C(x)                                         \
+	(((x) >> BIT_SHIFT_XTAL_OV_RATIO_8822C) & BIT_MASK_XTAL_OV_RATIO_8822C)
+#define BIT_SET_XTAL_OV_RATIO_8822C(x, v)                                      \
+	(BIT_CLEAR_XTAL_OV_RATIO_8822C(x) | BIT_XTAL_OV_RATIO_8822C(v))
+
+#define BIT_SHIFT_XTAL_OV_UNIT_8822C 6
+#define BIT_MASK_XTAL_OV_UNIT_8822C 0x7
+#define BIT_XTAL_OV_UNIT_8822C(x)                                              \
+	(((x) & BIT_MASK_XTAL_OV_UNIT_8822C) << BIT_SHIFT_XTAL_OV_UNIT_8822C)
+#define BITS_XTAL_OV_UNIT_8822C                                                \
+	(BIT_MASK_XTAL_OV_UNIT_8822C << BIT_SHIFT_XTAL_OV_UNIT_8822C)
+#define BIT_CLEAR_XTAL_OV_UNIT_8822C(x) ((x) & (~BITS_XTAL_OV_UNIT_8822C))
+#define BIT_GET_XTAL_OV_UNIT_8822C(x)                                          \
+	(((x) >> BIT_SHIFT_XTAL_OV_UNIT_8822C) & BIT_MASK_XTAL_OV_UNIT_8822C)
+#define BIT_SET_XTAL_OV_UNIT_8822C(x, v)                                       \
+	(BIT_CLEAR_XTAL_OV_UNIT_8822C(x) | BIT_XTAL_OV_UNIT_8822C(v))
+
+#define BIT_SHIFT_XTAL_MODE_MANUAL_8822C 4
+#define BIT_MASK_XTAL_MODE_MANUAL_8822C 0x3
+#define BIT_XTAL_MODE_MANUAL_8822C(x)                                          \
+	(((x) & BIT_MASK_XTAL_MODE_MANUAL_8822C)                               \
+	 << BIT_SHIFT_XTAL_MODE_MANUAL_8822C)
+#define BITS_XTAL_MODE_MANUAL_8822C                                            \
+	(BIT_MASK_XTAL_MODE_MANUAL_8822C << BIT_SHIFT_XTAL_MODE_MANUAL_8822C)
+#define BIT_CLEAR_XTAL_MODE_MANUAL_8822C(x)                                    \
+	((x) & (~BITS_XTAL_MODE_MANUAL_8822C))
+#define BIT_GET_XTAL_MODE_MANUAL_8822C(x)                                      \
+	(((x) >> BIT_SHIFT_XTAL_MODE_MANUAL_8822C) &                           \
+	 BIT_MASK_XTAL_MODE_MANUAL_8822C)
+#define BIT_SET_XTAL_MODE_MANUAL_8822C(x, v)                                   \
+	(BIT_CLEAR_XTAL_MODE_MANUAL_8822C(x) | BIT_XTAL_MODE_MANUAL_8822C(v))
+
+#define BIT_XTAL_MANU_SEL_8822C BIT(3)
+
+/* 2 REG_NOT_VALID_8822C */
+#define BIT_XTAL_MODE_8822C BIT(1)
+#define BIT_RESET_N_DECODER_8822C BIT(0)
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_SYS_CFG5_8822C */
+#define BIT_LPS_STATUS_8822C BIT(3)
+#define BIT_HCI_TXDMA_BUSY_8822C BIT(2)
+#define BIT_HCI_TXDMA_ALLOW_8822C BIT(1)
+#define BIT_FW_CTRL_HCI_TXDMA_EN_8822C BIT(0)
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_CPU_DMEM_CON_8822C */
+#define BIT_WDT_AUTO_MODE_8822C BIT(22)
+#define BIT_WDT_PLATFORM_EN_8822C BIT(21)
+#define BIT_WDT_CPU_EN_8822C BIT(20)
+#define BIT_WDT_OPT_IOWRAPPER_8822C BIT(19)
+#define BIT_ANA_PORT_IDLE_8822C BIT(18)
+#define BIT_MAC_PORT_IDLE_8822C BIT(17)
+#define BIT_WL_PLATFORM_RST_8822C BIT(16)
+#define BIT_WL_SECURITY_CLK_8822C BIT(15)
+#define BIT_DDMA_EN_8822C BIT(8)
+
+#define BIT_SHIFT_CPU_DMEM_CON_8822C 0
+#define BIT_MASK_CPU_DMEM_CON_8822C 0xff
+#define BIT_CPU_DMEM_CON_8822C(x)                                              \
+	(((x) & BIT_MASK_CPU_DMEM_CON_8822C) << BIT_SHIFT_CPU_DMEM_CON_8822C)
+#define BITS_CPU_DMEM_CON_8822C                                                \
+	(BIT_MASK_CPU_DMEM_CON_8822C << BIT_SHIFT_CPU_DMEM_CON_8822C)
+#define BIT_CLEAR_CPU_DMEM_CON_8822C(x) ((x) & (~BITS_CPU_DMEM_CON_8822C))
+#define BIT_GET_CPU_DMEM_CON_8822C(x)                                          \
+	(((x) >> BIT_SHIFT_CPU_DMEM_CON_8822C) & BIT_MASK_CPU_DMEM_CON_8822C)
+#define BIT_SET_CPU_DMEM_CON_8822C(x, v)                                       \
+	(BIT_CLEAR_CPU_DMEM_CON_8822C(x) | BIT_CPU_DMEM_CON_8822C(v))
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_BOOT_REASON_8822C */
+
+#define BIT_SHIFT_BOOT_REASON_V1_8822C 0
+#define BIT_MASK_BOOT_REASON_V1_8822C 0x7
+#define BIT_BOOT_REASON_V1_8822C(x)                                            \
+	(((x) & BIT_MASK_BOOT_REASON_V1_8822C)                                 \
+	 << BIT_SHIFT_BOOT_REASON_V1_8822C)
+#define BITS_BOOT_REASON_V1_8822C                                              \
+	(BIT_MASK_BOOT_REASON_V1_8822C << BIT_SHIFT_BOOT_REASON_V1_8822C)
+#define BIT_CLEAR_BOOT_REASON_V1_8822C(x) ((x) & (~BITS_BOOT_REASON_V1_8822C))
+#define BIT_GET_BOOT_REASON_V1_8822C(x)                                        \
+	(((x) >> BIT_SHIFT_BOOT_REASON_V1_8822C) &                             \
+	 BIT_MASK_BOOT_REASON_V1_8822C)
+#define BIT_SET_BOOT_REASON_V1_8822C(x, v)                                     \
+	(BIT_CLEAR_BOOT_REASON_V1_8822C(x) | BIT_BOOT_REASON_V1_8822C(v))
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_HIMR2_8822C */
+#define BIT_BCNDMAINT_P4_MSK_8822C BIT(31)
+#define BIT_BCNDMAINT_P3_MSK_8822C BIT(30)
+#define BIT_BCNDMAINT_P2_MSK_8822C BIT(29)
+#define BIT_BCNDMAINT_P1_MSK_8822C BIT(28)
+#define BIT_ATIMEND7_MSK_8822C BIT(22)
+#define BIT_ATIMEND6_MSK_8822C BIT(21)
+#define BIT_ATIMEND5_MSK_8822C BIT(20)
+#define BIT_ATIMEND4_MSK_8822C BIT(19)
+#define BIT_ATIMEND3_MSK_8822C BIT(18)
+#define BIT_ATIMEND2_MSK_8822C BIT(17)
+#define BIT_ATIMEND1_MSK_8822C BIT(16)
+#define BIT_TXBCN7OK_MSK_8822C BIT(14)
+#define BIT_TXBCN6OK_MSK_8822C BIT(13)
+#define BIT_TXBCN5OK_MSK_8822C BIT(12)
+#define BIT_TXBCN4OK_MSK_8822C BIT(11)
+#define BIT_TXBCN3OK_MSK_8822C BIT(10)
+#define BIT_TXBCN2OK_MSK_8822C BIT(9)
+#define BIT_TXBCN1OK_MSK_V1_8822C BIT(8)
+#define BIT_TXBCN7ERR_MSK_8822C BIT(6)
+#define BIT_TXBCN6ERR_MSK_8822C BIT(5)
+#define BIT_TXBCN5ERR_MSK_8822C BIT(4)
+#define BIT_TXBCN4ERR_MSK_8822C BIT(3)
+#define BIT_TXBCN3ERR_MSK_8822C BIT(2)
+#define BIT_TXBCN2ERR_MSK_8822C BIT(1)
+#define BIT_TXBCN1ERR_MSK_V1_8822C BIT(0)
+
+/* 2 REG_HISR2_8822C */
+#define BIT_BCNDMAINT_P4_8822C BIT(31)
+#define BIT_BCNDMAINT_P3_8822C BIT(30)
+#define BIT_BCNDMAINT_P2_8822C BIT(29)
+#define BIT_BCNDMAINT_P1_8822C BIT(28)
+#define BIT_ATIMEND7_8822C BIT(22)
+#define BIT_ATIMEND6_8822C BIT(21)
+#define BIT_ATIMEND5_8822C BIT(20)
+#define BIT_ATIMEND4_8822C BIT(19)
+#define BIT_ATIMEND3_8822C BIT(18)
+#define BIT_ATIMEND2_8822C BIT(17)
+#define BIT_ATIMEND1_8822C BIT(16)
+#define BIT_TXBCN7OK_8822C BIT(14)
+#define BIT_TXBCN6OK_8822C BIT(13)
+#define BIT_TXBCN5OK_8822C BIT(12)
+#define BIT_TXBCN4OK_8822C BIT(11)
+#define BIT_TXBCN3OK_8822C BIT(10)
+#define BIT_TXBCN2OK_8822C BIT(9)
+#define BIT_TXBCN1OK_8822C BIT(8)
+#define BIT_TXBCN7ERR_8822C BIT(6)
+#define BIT_TXBCN6ERR_8822C BIT(5)
+#define BIT_TXBCN5ERR_8822C BIT(4)
+#define BIT_TXBCN4ERR_8822C BIT(3)
+#define BIT_TXBCN3ERR_8822C BIT(2)
+#define BIT_TXBCN2ERR_8822C BIT(1)
+#define BIT_TXBCN1ERR_8822C BIT(0)
+
+/* 2 REG_HIMR3_8822C */
+#define BIT_WDT_PLATFORM_INT_MSK_8822C BIT(18)
+#define BIT_WDT_CPU_INT_MSK_8822C BIT(17)
+#define BIT_SETH2CDOK_MASK_8822C BIT(16)
+#define BIT_H2C_CMD_FULL_MASK_8822C BIT(15)
+#define BIT_PWR_INT_127_MASK_8822C BIT(14)
+#define BIT_TXSHORTCUT_TXDESUPDATEOK_MASK_8822C BIT(13)
+#define BIT_TXSHORTCUT_BKUPDATEOK_MASK_8822C BIT(12)
+#define BIT_TXSHORTCUT_BEUPDATEOK_MASK_8822C BIT(11)
+#define BIT_TXSHORTCUT_VIUPDATEOK_MAS_8822C BIT(10)
+#define BIT_TXSHORTCUT_VOUPDATEOK_MASK_8822C BIT(9)
+#define BIT_PWR_INT_127_MASK_V1_8822C BIT(8)
+#define BIT_PWR_INT_126TO96_MASK_8822C BIT(7)
+#define BIT_PWR_INT_95TO64_MASK_8822C BIT(6)
+#define BIT_PWR_INT_63TO32_MASK_8822C BIT(5)
+#define BIT_PWR_INT_31TO0_MASK_8822C BIT(4)
+#define BIT_RX_DMA_STUCK_MSK_8822C BIT(3)
+#define BIT_TX_DMA_STUCK_MSK_8822C BIT(2)
+#define BIT_DDMA0_LP_INT_MSK_8822C BIT(1)
+#define BIT_DDMA0_HP_INT_MSK_8822C BIT(0)
+
+/* 2 REG_HISR3_8822C */
+#define BIT_WDT_PLATFORM_INT_8822C BIT(18)
+#define BIT_WDT_CPU_INT_8822C BIT(17)
+#define BIT_SETH2CDOK_8822C BIT(16)
+#define BIT_H2C_CMD_FULL_8822C BIT(15)
+#define BIT_PWR_INT_127_8822C BIT(14)
+#define BIT_TXSHORTCUT_TXDESUPDATEOK_8822C BIT(13)
+#define BIT_TXSHORTCUT_BKUPDATEOK_8822C BIT(12)
+#define BIT_TXSHORTCUT_BEUPDATEOK_8822C BIT(11)
+#define BIT_TXSHORTCUT_VIUPDATEOK_8822C BIT(10)
+#define BIT_TXSHORTCUT_VOUPDATEOK_8822C BIT(9)
+#define BIT_PWR_INT_127_V1_8822C BIT(8)
+#define BIT_PWR_INT_126TO96_8822C BIT(7)
+#define BIT_PWR_INT_95TO64_8822C BIT(6)
+#define BIT_PWR_INT_63TO32_8822C BIT(5)
+#define BIT_PWR_INT_31TO0_8822C BIT(4)
+#define BIT_RX_DMA_STUCK_8822C BIT(3)
+#define BIT_TX_DMA_STUCK_8822C BIT(2)
+#define BIT_DDMA0_LP_INT_8822C BIT(1)
+#define BIT_DDMA0_HP_INT_8822C BIT(0)
+
+/* 2 REG_SW_MDIO_8822C */
+#define BIT_DIS_TIMEOUT_IO_8822C BIT(24)
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_H2C_PKT_READADDR_8822C */
+
+#define BIT_SHIFT_H2C_PKT_READADDR_8822C 0
+#define BIT_MASK_H2C_PKT_READADDR_8822C 0x3ffff
+#define BIT_H2C_PKT_READADDR_8822C(x)                                          \
+	(((x) & BIT_MASK_H2C_PKT_READADDR_8822C)                               \
+	 << BIT_SHIFT_H2C_PKT_READADDR_8822C)
+#define BITS_H2C_PKT_READADDR_8822C                                            \
+	(BIT_MASK_H2C_PKT_READADDR_8822C << BIT_SHIFT_H2C_PKT_READADDR_8822C)
+#define BIT_CLEAR_H2C_PKT_READADDR_8822C(x)                                    \
+	((x) & (~BITS_H2C_PKT_READADDR_8822C))
+#define BIT_GET_H2C_PKT_READADDR_8822C(x)                                      \
+	(((x) >> BIT_SHIFT_H2C_PKT_READADDR_8822C) &                           \
+	 BIT_MASK_H2C_PKT_READADDR_8822C)
+#define BIT_SET_H2C_PKT_READADDR_8822C(x, v)                                   \
+	(BIT_CLEAR_H2C_PKT_READADDR_8822C(x) | BIT_H2C_PKT_READADDR_8822C(v))
+
+/* 2 REG_H2C_PKT_WRITEADDR_8822C */
+
+#define BIT_SHIFT_H2C_PKT_WRITEADDR_8822C 0
+#define BIT_MASK_H2C_PKT_WRITEADDR_8822C 0x3ffff
+#define BIT_H2C_PKT_WRITEADDR_8822C(x)                                         \
+	(((x) & BIT_MASK_H2C_PKT_WRITEADDR_8822C)                              \
+	 << BIT_SHIFT_H2C_PKT_WRITEADDR_8822C)
+#define BITS_H2C_PKT_WRITEADDR_8822C                                           \
+	(BIT_MASK_H2C_PKT_WRITEADDR_8822C << BIT_SHIFT_H2C_PKT_WRITEADDR_8822C)
+#define BIT_CLEAR_H2C_PKT_WRITEADDR_8822C(x)                                   \
+	((x) & (~BITS_H2C_PKT_WRITEADDR_8822C))
+#define BIT_GET_H2C_PKT_WRITEADDR_8822C(x)                                     \
+	(((x) >> BIT_SHIFT_H2C_PKT_WRITEADDR_8822C) &                          \
+	 BIT_MASK_H2C_PKT_WRITEADDR_8822C)
+#define BIT_SET_H2C_PKT_WRITEADDR_8822C(x, v)                                  \
+	(BIT_CLEAR_H2C_PKT_WRITEADDR_8822C(x) | BIT_H2C_PKT_WRITEADDR_8822C(v))
+
+/* 2 REG_MEM_PWR_CRTL_8822C */
+#define BIT_MEM_BB_SD_8822C BIT(17)
+#define BIT_MEM_BB_DS_8822C BIT(16)
+#define BIT_MEM_BT_DS_8822C BIT(10)
+#define BIT_MEM_SDIO_LS_8822C BIT(9)
+#define BIT_MEM_SDIO_DS_8822C BIT(8)
+#define BIT_MEM_USB_LS_8822C BIT(7)
+#define BIT_MEM_USB_DS_8822C BIT(6)
+#define BIT_MEM_PCI_LS_8822C BIT(5)
+#define BIT_MEM_PCI_DS_8822C BIT(4)
+#define BIT_MEM_WLMAC_LS_8822C BIT(3)
+#define BIT_MEM_WLMAC_DS_8822C BIT(2)
+#define BIT_MEM_WLMCU_LS_8822C BIT(1)
+#define BIT_MEM_WLMCU_DS_8822C BIT(0)
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_FW_DBG6_8822C */
+
+#define BIT_SHIFT_FW_DBG6_8822C 0
+#define BIT_MASK_FW_DBG6_8822C 0xffffffffL
+#define BIT_FW_DBG6_8822C(x)                                                   \
+	(((x) & BIT_MASK_FW_DBG6_8822C) << BIT_SHIFT_FW_DBG6_8822C)
+#define BITS_FW_DBG6_8822C (BIT_MASK_FW_DBG6_8822C << BIT_SHIFT_FW_DBG6_8822C)
+#define BIT_CLEAR_FW_DBG6_8822C(x) ((x) & (~BITS_FW_DBG6_8822C))
+#define BIT_GET_FW_DBG6_8822C(x)                                               \
+	(((x) >> BIT_SHIFT_FW_DBG6_8822C) & BIT_MASK_FW_DBG6_8822C)
+#define BIT_SET_FW_DBG6_8822C(x, v)                                            \
+	(BIT_CLEAR_FW_DBG6_8822C(x) | BIT_FW_DBG6_8822C(v))
+
+/* 2 REG_FW_DBG7_8822C */
+
+#define BIT_SHIFT_FW_DBG7_8822C 0
+#define BIT_MASK_FW_DBG7_8822C 0xffffffffL
+#define BIT_FW_DBG7_8822C(x)                                                   \
+	(((x) & BIT_MASK_FW_DBG7_8822C) << BIT_SHIFT_FW_DBG7_8822C)
+#define BITS_FW_DBG7_8822C (BIT_MASK_FW_DBG7_8822C << BIT_SHIFT_FW_DBG7_8822C)
+#define BIT_CLEAR_FW_DBG7_8822C(x) ((x) & (~BITS_FW_DBG7_8822C))
+#define BIT_GET_FW_DBG7_8822C(x)                                               \
+	(((x) >> BIT_SHIFT_FW_DBG7_8822C) & BIT_MASK_FW_DBG7_8822C)
+#define BIT_SET_FW_DBG7_8822C(x, v)                                            \
+	(BIT_CLEAR_FW_DBG7_8822C(x) | BIT_FW_DBG7_8822C(v))
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_CR_8822C */
+
+#define BIT_SHIFT_LBMODE_8822C 24
+#define BIT_MASK_LBMODE_8822C 0x1f
+#define BIT_LBMODE_8822C(x)                                                    \
+	(((x) & BIT_MASK_LBMODE_8822C) << BIT_SHIFT_LBMODE_8822C)
+#define BITS_LBMODE_8822C (BIT_MASK_LBMODE_8822C << BIT_SHIFT_LBMODE_8822C)
+#define BIT_CLEAR_LBMODE_8822C(x) ((x) & (~BITS_LBMODE_8822C))
+#define BIT_GET_LBMODE_8822C(x)                                                \
+	(((x) >> BIT_SHIFT_LBMODE_8822C) & BIT_MASK_LBMODE_8822C)
+#define BIT_SET_LBMODE_8822C(x, v)                                             \
+	(BIT_CLEAR_LBMODE_8822C(x) | BIT_LBMODE_8822C(v))
+
+#define BIT_SHIFT_NETYPE1_8822C 18
+#define BIT_MASK_NETYPE1_8822C 0x3
+#define BIT_NETYPE1_8822C(x)                                                   \
+	(((x) & BIT_MASK_NETYPE1_8822C) << BIT_SHIFT_NETYPE1_8822C)
+#define BITS_NETYPE1_8822C (BIT_MASK_NETYPE1_8822C << BIT_SHIFT_NETYPE1_8822C)
+#define BIT_CLEAR_NETYPE1_8822C(x) ((x) & (~BITS_NETYPE1_8822C))
+#define BIT_GET_NETYPE1_8822C(x)                                               \
+	(((x) >> BIT_SHIFT_NETYPE1_8822C) & BIT_MASK_NETYPE1_8822C)
+#define BIT_SET_NETYPE1_8822C(x, v)                                            \
+	(BIT_CLEAR_NETYPE1_8822C(x) | BIT_NETYPE1_8822C(v))
+
+#define BIT_SHIFT_NETYPE0_8822C 16
+#define BIT_MASK_NETYPE0_8822C 0x3
+#define BIT_NETYPE0_8822C(x)                                                   \
+	(((x) & BIT_MASK_NETYPE0_8822C) << BIT_SHIFT_NETYPE0_8822C)
+#define BITS_NETYPE0_8822C (BIT_MASK_NETYPE0_8822C << BIT_SHIFT_NETYPE0_8822C)
+#define BIT_CLEAR_NETYPE0_8822C(x) ((x) & (~BITS_NETYPE0_8822C))
+#define BIT_GET_NETYPE0_8822C(x)                                               \
+	(((x) >> BIT_SHIFT_NETYPE0_8822C) & BIT_MASK_NETYPE0_8822C)
+#define BIT_SET_NETYPE0_8822C(x, v)                                            \
+	(BIT_CLEAR_NETYPE0_8822C(x) | BIT_NETYPE0_8822C(v))
+
+#define BIT_COUNTER_STS_EN_8822C BIT(13)
+#define BIT_I2C_MAILBOX_EN_8822C BIT(12)
+#define BIT_SHCUT_EN_8822C BIT(11)
+#define BIT_32K_CAL_TMR_EN_8822C BIT(10)
+#define BIT_MAC_SEC_EN_8822C BIT(9)
+#define BIT_ENSWBCN_8822C BIT(8)
+#define BIT_MACRXEN_8822C BIT(7)
+#define BIT_MACTXEN_8822C BIT(6)
+#define BIT_SCHEDULE_EN_8822C BIT(5)
+#define BIT_PROTOCOL_EN_8822C BIT(4)
+#define BIT_RXDMA_EN_8822C BIT(3)
+#define BIT_TXDMA_EN_8822C BIT(2)
+#define BIT_HCI_RXDMA_EN_8822C BIT(1)
+#define BIT_HCI_TXDMA_EN_8822C BIT(0)
+
+/* 2 REG_PG_SIZE_8822C */
+
+#define BIT_SHIFT_DBG_FIFO_SEL_8822C 16
+#define BIT_MASK_DBG_FIFO_SEL_8822C 0xff
+#define BIT_DBG_FIFO_SEL_8822C(x)                                              \
+	(((x) & BIT_MASK_DBG_FIFO_SEL_8822C) << BIT_SHIFT_DBG_FIFO_SEL_8822C)
+#define BITS_DBG_FIFO_SEL_8822C                                                \
+	(BIT_MASK_DBG_FIFO_SEL_8822C << BIT_SHIFT_DBG_FIFO_SEL_8822C)
+#define BIT_CLEAR_DBG_FIFO_SEL_8822C(x) ((x) & (~BITS_DBG_FIFO_SEL_8822C))
+#define BIT_GET_DBG_FIFO_SEL_8822C(x)                                          \
+	(((x) >> BIT_SHIFT_DBG_FIFO_SEL_8822C) & BIT_MASK_DBG_FIFO_SEL_8822C)
+#define BIT_SET_DBG_FIFO_SEL_8822C(x, v)                                       \
+	(BIT_CLEAR_DBG_FIFO_SEL_8822C(x) | BIT_DBG_FIFO_SEL_8822C(v))
+
+/* 2 REG_PKT_BUFF_ACCESS_CTRL_8822C */
+
+#define BIT_SHIFT_PKT_BUFF_ACCESS_CTRL_8822C 0
+#define BIT_MASK_PKT_BUFF_ACCESS_CTRL_8822C 0xff
+#define BIT_PKT_BUFF_ACCESS_CTRL_8822C(x)                                      \
+	(((x) & BIT_MASK_PKT_BUFF_ACCESS_CTRL_8822C)                           \
+	 << BIT_SHIFT_PKT_BUFF_ACCESS_CTRL_8822C)
+#define BITS_PKT_BUFF_ACCESS_CTRL_8822C                                        \
+	(BIT_MASK_PKT_BUFF_ACCESS_CTRL_8822C                                   \
+	 << BIT_SHIFT_PKT_BUFF_ACCESS_CTRL_8822C)
+#define BIT_CLEAR_PKT_BUFF_ACCESS_CTRL_8822C(x)                                \
+	((x) & (~BITS_PKT_BUFF_ACCESS_CTRL_8822C))
+#define BIT_GET_PKT_BUFF_ACCESS_CTRL_8822C(x)                                  \
+	(((x) >> BIT_SHIFT_PKT_BUFF_ACCESS_CTRL_8822C) &                       \
+	 BIT_MASK_PKT_BUFF_ACCESS_CTRL_8822C)
+#define BIT_SET_PKT_BUFF_ACCESS_CTRL_8822C(x, v)                               \
+	(BIT_CLEAR_PKT_BUFF_ACCESS_CTRL_8822C(x) |                             \
+	 BIT_PKT_BUFF_ACCESS_CTRL_8822C(v))
+
+/* 2 REG_TSF_CLK_STATE_8822C */
+#define BIT_TSF_CLK_STABLE_8822C BIT(15)
+
+/* 2 REG_TXDMA_PQ_MAP_8822C */
+#define BIT_CSI_BW_EN_8822C BIT(31)
+
+#define BIT_SHIFT_TXDMA_H2C_MAP_8822C 16
+#define BIT_MASK_TXDMA_H2C_MAP_8822C 0x3
+#define BIT_TXDMA_H2C_MAP_8822C(x)                                             \
+	(((x) & BIT_MASK_TXDMA_H2C_MAP_8822C) << BIT_SHIFT_TXDMA_H2C_MAP_8822C)
+#define BITS_TXDMA_H2C_MAP_8822C                                               \
+	(BIT_MASK_TXDMA_H2C_MAP_8822C << BIT_SHIFT_TXDMA_H2C_MAP_8822C)
+#define BIT_CLEAR_TXDMA_H2C_MAP_8822C(x) ((x) & (~BITS_TXDMA_H2C_MAP_8822C))
+#define BIT_GET_TXDMA_H2C_MAP_8822C(x)                                         \
+	(((x) >> BIT_SHIFT_TXDMA_H2C_MAP_8822C) & BIT_MASK_TXDMA_H2C_MAP_8822C)
+#define BIT_SET_TXDMA_H2C_MAP_8822C(x, v)                                      \
+	(BIT_CLEAR_TXDMA_H2C_MAP_8822C(x) | BIT_TXDMA_H2C_MAP_8822C(v))
+
+#define BIT_SHIFT_TXDMA_HIQ_MAP_8822C 14
+#define BIT_MASK_TXDMA_HIQ_MAP_8822C 0x3
+#define BIT_TXDMA_HIQ_MAP_8822C(x)                                             \
+	(((x) & BIT_MASK_TXDMA_HIQ_MAP_8822C) << BIT_SHIFT_TXDMA_HIQ_MAP_8822C)
+#define BITS_TXDMA_HIQ_MAP_8822C                                               \
+	(BIT_MASK_TXDMA_HIQ_MAP_8822C << BIT_SHIFT_TXDMA_HIQ_MAP_8822C)
+#define BIT_CLEAR_TXDMA_HIQ_MAP_8822C(x) ((x) & (~BITS_TXDMA_HIQ_MAP_8822C))
+#define BIT_GET_TXDMA_HIQ_MAP_8822C(x)                                         \
+	(((x) >> BIT_SHIFT_TXDMA_HIQ_MAP_8822C) & BIT_MASK_TXDMA_HIQ_MAP_8822C)
+#define BIT_SET_TXDMA_HIQ_MAP_8822C(x, v)                                      \
+	(BIT_CLEAR_TXDMA_HIQ_MAP_8822C(x) | BIT_TXDMA_HIQ_MAP_8822C(v))
+
+#define BIT_SHIFT_TXDMA_MGQ_MAP_8822C 12
+#define BIT_MASK_TXDMA_MGQ_MAP_8822C 0x3
+#define BIT_TXDMA_MGQ_MAP_8822C(x)                                             \
+	(((x) & BIT_MASK_TXDMA_MGQ_MAP_8822C) << BIT_SHIFT_TXDMA_MGQ_MAP_8822C)
+#define BITS_TXDMA_MGQ_MAP_8822C                                               \
+	(BIT_MASK_TXDMA_MGQ_MAP_8822C << BIT_SHIFT_TXDMA_MGQ_MAP_8822C)
+#define BIT_CLEAR_TXDMA_MGQ_MAP_8822C(x) ((x) & (~BITS_TXDMA_MGQ_MAP_8822C))
+#define BIT_GET_TXDMA_MGQ_MAP_8822C(x)                                         \
+	(((x) >> BIT_SHIFT_TXDMA_MGQ_MAP_8822C) & BIT_MASK_TXDMA_MGQ_MAP_8822C)
+#define BIT_SET_TXDMA_MGQ_MAP_8822C(x, v)                                      \
+	(BIT_CLEAR_TXDMA_MGQ_MAP_8822C(x) | BIT_TXDMA_MGQ_MAP_8822C(v))
+
+#define BIT_SHIFT_TXDMA_BKQ_MAP_8822C 10
+#define BIT_MASK_TXDMA_BKQ_MAP_8822C 0x3
+#define BIT_TXDMA_BKQ_MAP_8822C(x)                                             \
+	(((x) & BIT_MASK_TXDMA_BKQ_MAP_8822C) << BIT_SHIFT_TXDMA_BKQ_MAP_8822C)
+#define BITS_TXDMA_BKQ_MAP_8822C                                               \
+	(BIT_MASK_TXDMA_BKQ_MAP_8822C << BIT_SHIFT_TXDMA_BKQ_MAP_8822C)
+#define BIT_CLEAR_TXDMA_BKQ_MAP_8822C(x) ((x) & (~BITS_TXDMA_BKQ_MAP_8822C))
+#define BIT_GET_TXDMA_BKQ_MAP_8822C(x)                                         \
+	(((x) >> BIT_SHIFT_TXDMA_BKQ_MAP_8822C) & BIT_MASK_TXDMA_BKQ_MAP_8822C)
+#define BIT_SET_TXDMA_BKQ_MAP_8822C(x, v)                                      \
+	(BIT_CLEAR_TXDMA_BKQ_MAP_8822C(x) | BIT_TXDMA_BKQ_MAP_8822C(v))
+
+#define BIT_SHIFT_TXDMA_BEQ_MAP_8822C 8
+#define BIT_MASK_TXDMA_BEQ_MAP_8822C 0x3
+#define BIT_TXDMA_BEQ_MAP_8822C(x)                                             \
+	(((x) & BIT_MASK_TXDMA_BEQ_MAP_8822C) << BIT_SHIFT_TXDMA_BEQ_MAP_8822C)
+#define BITS_TXDMA_BEQ_MAP_8822C                                               \
+	(BIT_MASK_TXDMA_BEQ_MAP_8822C << BIT_SHIFT_TXDMA_BEQ_MAP_8822C)
+#define BIT_CLEAR_TXDMA_BEQ_MAP_8822C(x) ((x) & (~BITS_TXDMA_BEQ_MAP_8822C))
+#define BIT_GET_TXDMA_BEQ_MAP_8822C(x)                                         \
+	(((x) >> BIT_SHIFT_TXDMA_BEQ_MAP_8822C) & BIT_MASK_TXDMA_BEQ_MAP_8822C)
+#define BIT_SET_TXDMA_BEQ_MAP_8822C(x, v)                                      \
+	(BIT_CLEAR_TXDMA_BEQ_MAP_8822C(x) | BIT_TXDMA_BEQ_MAP_8822C(v))
+
+#define BIT_SHIFT_TXDMA_VIQ_MAP_8822C 6
+#define BIT_MASK_TXDMA_VIQ_MAP_8822C 0x3
+#define BIT_TXDMA_VIQ_MAP_8822C(x)                                             \
+	(((x) & BIT_MASK_TXDMA_VIQ_MAP_8822C) << BIT_SHIFT_TXDMA_VIQ_MAP_8822C)
+#define BITS_TXDMA_VIQ_MAP_8822C                                               \
+	(BIT_MASK_TXDMA_VIQ_MAP_8822C << BIT_SHIFT_TXDMA_VIQ_MAP_8822C)
+#define BIT_CLEAR_TXDMA_VIQ_MAP_8822C(x) ((x) & (~BITS_TXDMA_VIQ_MAP_8822C))
+#define BIT_GET_TXDMA_VIQ_MAP_8822C(x)                                         \
+	(((x) >> BIT_SHIFT_TXDMA_VIQ_MAP_8822C) & BIT_MASK_TXDMA_VIQ_MAP_8822C)
+#define BIT_SET_TXDMA_VIQ_MAP_8822C(x, v)                                      \
+	(BIT_CLEAR_TXDMA_VIQ_MAP_8822C(x) | BIT_TXDMA_VIQ_MAP_8822C(v))
+
+#define BIT_SHIFT_TXDMA_VOQ_MAP_8822C 4
+#define BIT_MASK_TXDMA_VOQ_MAP_8822C 0x3
+#define BIT_TXDMA_VOQ_MAP_8822C(x)                                             \
+	(((x) & BIT_MASK_TXDMA_VOQ_MAP_8822C) << BIT_SHIFT_TXDMA_VOQ_MAP_8822C)
+#define BITS_TXDMA_VOQ_MAP_8822C                                               \
+	(BIT_MASK_TXDMA_VOQ_MAP_8822C << BIT_SHIFT_TXDMA_VOQ_MAP_8822C)
+#define BIT_CLEAR_TXDMA_VOQ_MAP_8822C(x) ((x) & (~BITS_TXDMA_VOQ_MAP_8822C))
+#define BIT_GET_TXDMA_VOQ_MAP_8822C(x)                                         \
+	(((x) >> BIT_SHIFT_TXDMA_VOQ_MAP_8822C) & BIT_MASK_TXDMA_VOQ_MAP_8822C)
+#define BIT_SET_TXDMA_VOQ_MAP_8822C(x, v)                                      \
+	(BIT_CLEAR_TXDMA_VOQ_MAP_8822C(x) | BIT_TXDMA_VOQ_MAP_8822C(v))
+
+#define BIT_TXDMA_BW_EN_8822C BIT(3)
+#define BIT_RXDMA_AGG_EN_8822C BIT(2)
+#define BIT_RXSHFT_EN_8822C BIT(1)
+#define BIT_RXDMA_ARBBW_EN_8822C BIT(0)
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_TRXFF_BNDY_8822C */
+
+#define BIT_SHIFT_FWFFOVFL_RSV_8822C 16
+#define BIT_MASK_FWFFOVFL_RSV_8822C 0xf
+#define BIT_FWFFOVFL_RSV_8822C(x)                                              \
+	(((x) & BIT_MASK_FWFFOVFL_RSV_8822C) << BIT_SHIFT_FWFFOVFL_RSV_8822C)
+#define BITS_FWFFOVFL_RSV_8822C                                                \
+	(BIT_MASK_FWFFOVFL_RSV_8822C << BIT_SHIFT_FWFFOVFL_RSV_8822C)
+#define BIT_CLEAR_FWFFOVFL_RSV_8822C(x) ((x) & (~BITS_FWFFOVFL_RSV_8822C))
+#define BIT_GET_FWFFOVFL_RSV_8822C(x)                                          \
+	(((x) >> BIT_SHIFT_FWFFOVFL_RSV_8822C) & BIT_MASK_FWFFOVFL_RSV_8822C)
+#define BIT_SET_FWFFOVFL_RSV_8822C(x, v)                                       \
+	(BIT_CLEAR_FWFFOVFL_RSV_8822C(x) | BIT_FWFFOVFL_RSV_8822C(v))
+
+#define BIT_SHIFT_RXFFOVFL_RSV_V2_8822C 8
+#define BIT_MASK_RXFFOVFL_RSV_V2_8822C 0xf
+#define BIT_RXFFOVFL_RSV_V2_8822C(x)                                           \
+	(((x) & BIT_MASK_RXFFOVFL_RSV_V2_8822C)                                \
+	 << BIT_SHIFT_RXFFOVFL_RSV_V2_8822C)
+#define BITS_RXFFOVFL_RSV_V2_8822C                                             \
+	(BIT_MASK_RXFFOVFL_RSV_V2_8822C << BIT_SHIFT_RXFFOVFL_RSV_V2_8822C)
+#define BIT_CLEAR_RXFFOVFL_RSV_V2_8822C(x) ((x) & (~BITS_RXFFOVFL_RSV_V2_8822C))
+#define BIT_GET_RXFFOVFL_RSV_V2_8822C(x)                                       \
+	(((x) >> BIT_SHIFT_RXFFOVFL_RSV_V2_8822C) &                            \
+	 BIT_MASK_RXFFOVFL_RSV_V2_8822C)
+#define BIT_SET_RXFFOVFL_RSV_V2_8822C(x, v)                                    \
+	(BIT_CLEAR_RXFFOVFL_RSV_V2_8822C(x) | BIT_RXFFOVFL_RSV_V2_8822C(v))
+
+/* 2 REG_PTA_I2C_MBOX_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+#define BIT_SHIFT_I2C_M_STATUS_8822C 8
+#define BIT_MASK_I2C_M_STATUS_8822C 0xf
+#define BIT_I2C_M_STATUS_8822C(x)                                              \
+	(((x) & BIT_MASK_I2C_M_STATUS_8822C) << BIT_SHIFT_I2C_M_STATUS_8822C)
+#define BITS_I2C_M_STATUS_8822C                                                \
+	(BIT_MASK_I2C_M_STATUS_8822C << BIT_SHIFT_I2C_M_STATUS_8822C)
+#define BIT_CLEAR_I2C_M_STATUS_8822C(x) ((x) & (~BITS_I2C_M_STATUS_8822C))
+#define BIT_GET_I2C_M_STATUS_8822C(x)                                          \
+	(((x) >> BIT_SHIFT_I2C_M_STATUS_8822C) & BIT_MASK_I2C_M_STATUS_8822C)
+#define BIT_SET_I2C_M_STATUS_8822C(x, v)                                       \
+	(BIT_CLEAR_I2C_M_STATUS_8822C(x) | BIT_I2C_M_STATUS_8822C(v))
+
+#define BIT_SHIFT_I2C_M_BUS_GNT_FW_8822C 4
+#define BIT_MASK_I2C_M_BUS_GNT_FW_8822C 0x7
+#define BIT_I2C_M_BUS_GNT_FW_8822C(x)                                          \
+	(((x) & BIT_MASK_I2C_M_BUS_GNT_FW_8822C)                               \
+	 << BIT_SHIFT_I2C_M_BUS_GNT_FW_8822C)
+#define BITS_I2C_M_BUS_GNT_FW_8822C                                            \
+	(BIT_MASK_I2C_M_BUS_GNT_FW_8822C << BIT_SHIFT_I2C_M_BUS_GNT_FW_8822C)
+#define BIT_CLEAR_I2C_M_BUS_GNT_FW_8822C(x)                                    \
+	((x) & (~BITS_I2C_M_BUS_GNT_FW_8822C))
+#define BIT_GET_I2C_M_BUS_GNT_FW_8822C(x)                                      \
+	(((x) >> BIT_SHIFT_I2C_M_BUS_GNT_FW_8822C) &                           \
+	 BIT_MASK_I2C_M_BUS_GNT_FW_8822C)
+#define BIT_SET_I2C_M_BUS_GNT_FW_8822C(x, v)                                   \
+	(BIT_CLEAR_I2C_M_BUS_GNT_FW_8822C(x) | BIT_I2C_M_BUS_GNT_FW_8822C(v))
+
+#define BIT_I2C_M_GNT_FW_8822C BIT(3)
+
+#define BIT_SHIFT_I2C_M_SPEED_8822C 1
+#define BIT_MASK_I2C_M_SPEED_8822C 0x3
+#define BIT_I2C_M_SPEED_8822C(x)                                               \
+	(((x) & BIT_MASK_I2C_M_SPEED_8822C) << BIT_SHIFT_I2C_M_SPEED_8822C)
+#define BITS_I2C_M_SPEED_8822C                                                 \
+	(BIT_MASK_I2C_M_SPEED_8822C << BIT_SHIFT_I2C_M_SPEED_8822C)
+#define BIT_CLEAR_I2C_M_SPEED_8822C(x) ((x) & (~BITS_I2C_M_SPEED_8822C))
+#define BIT_GET_I2C_M_SPEED_8822C(x)                                           \
+	(((x) >> BIT_SHIFT_I2C_M_SPEED_8822C) & BIT_MASK_I2C_M_SPEED_8822C)
+#define BIT_SET_I2C_M_SPEED_8822C(x, v)                                        \
+	(BIT_CLEAR_I2C_M_SPEED_8822C(x) | BIT_I2C_M_SPEED_8822C(v))
+
+#define BIT_I2C_M_UNLOCK_8822C BIT(0)
+
+/* 2 REG_RXFF_BNDY_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+#define BIT_SHIFT_RXFF0_BNDY_V2_8822C 0
+#define BIT_MASK_RXFF0_BNDY_V2_8822C 0x3ffff
+#define BIT_RXFF0_BNDY_V2_8822C(x)                                             \
+	(((x) & BIT_MASK_RXFF0_BNDY_V2_8822C) << BIT_SHIFT_RXFF0_BNDY_V2_8822C)
+#define BITS_RXFF0_BNDY_V2_8822C                                               \
+	(BIT_MASK_RXFF0_BNDY_V2_8822C << BIT_SHIFT_RXFF0_BNDY_V2_8822C)
+#define BIT_CLEAR_RXFF0_BNDY_V2_8822C(x) ((x) & (~BITS_RXFF0_BNDY_V2_8822C))
+#define BIT_GET_RXFF0_BNDY_V2_8822C(x)                                         \
+	(((x) >> BIT_SHIFT_RXFF0_BNDY_V2_8822C) & BIT_MASK_RXFF0_BNDY_V2_8822C)
+#define BIT_SET_RXFF0_BNDY_V2_8822C(x, v)                                      \
+	(BIT_CLEAR_RXFF0_BNDY_V2_8822C(x) | BIT_RXFF0_BNDY_V2_8822C(v))
+
+/* 2 REG_FE1IMR_8822C */
+#define BIT_FS_SW_PLL_LEAVE_32K_INT_EN_8822C BIT(31)
+#define BIT_FS_FWFF_FULL_INT_EN_8822C BIT(30)
+#define BIT_FS_BB_STOP_RX_INT_EN_8822C BIT(29)
+#define BIT_FS_RXDMA2_DONE_INT_EN_8822C BIT(28)
+#define BIT_FS_RXDONE2_INT_EN_8822C BIT(26)
+#define BIT_FS_RX_BCN_P4_INT_EN_8822C BIT(25)
+#define BIT_FS_RX_BCN_P3_INT_EN_8822C BIT(24)
+#define BIT_FS_RX_BCN_P2_INT_EN_8822C BIT(23)
+#define BIT_FS_RX_BCN_P1_INT_EN_8822C BIT(22)
+#define BIT_FS_RX_BCN_P0_INT_EN_8822C BIT(21)
+#define BIT_FS_RX_UMD0_INT_EN_8822C BIT(20)
+#define BIT_FS_RX_UMD1_INT_EN_8822C BIT(19)
+#define BIT_FS_RX_BMD0_INT_EN_8822C BIT(18)
+#define BIT_FS_RX_BMD1_INT_EN_8822C BIT(17)
+#define BIT_FS_RXDONE_INT_EN_8822C BIT(16)
+#define BIT_FS_WWLAN_INT_EN_8822C BIT(15)
+#define BIT_FS_SOUND_DONE_INT_EN_8822C BIT(14)
+#define BIT_FS_BF1_PRETO_INT_EN_8822C BIT(11)
+#define BIT_FS_BF0_PRETO_INT_EN_8822C BIT(10)
+#define BIT_FS_PTCL_RELEASE_MACID_INT_EN_8822C BIT(9)
+#define BIT_FS_PRETX_ERRHLD_INT_EN_8822C BIT(8)
+#define BIT_FS_LTE_COEX_EN_8822C BIT(6)
+#define BIT_FS_WLACTOFF_INT_EN_8822C BIT(5)
+#define BIT_FS_WLACTON_INT_EN_8822C BIT(4)
+#define BIT_FS_BTCMD_INT_EN_8822C BIT(3)
+#define BIT_FS_REG_MAILBOX_TO_I2C_INT_EN_8822C BIT(2)
+#define BIT_FS_TRPC_TO_INT_EN_V1_8822C BIT(1)
+#define BIT_FS_RPC_O_T_INT_EN_V1_8822C BIT(0)
+
+/* 2 REG_FE1ISR_8822C */
+#define BIT_FS_SW_PLL_LEAVE_32K_INT_8822C BIT(31)
+#define BIT_FS_FS_FWFF_FULL_INT_8822C BIT(30)
+#define BIT_FS_BB_STOP_RX_INT_8822C BIT(29)
+#define BIT_FS_RXDMA2_DONE_INT_8822C BIT(28)
+#define BIT_FS_RXDONE2_INT_8822C BIT(26)
+#define BIT_FS_RX_BCN_P4_INT_8822C BIT(25)
+#define BIT_FS_RX_BCN_P3_INT_8822C BIT(24)
+#define BIT_FS_RX_BCN_P2_INT_8822C BIT(23)
+#define BIT_FS_RX_BCN_P1_INT_8822C BIT(22)
+#define BIT_FS_RX_BCN_P0_INT_8822C BIT(21)
+#define BIT_FS_RX_UMD0_INT_8822C BIT(20)
+#define BIT_FS_RX_UMD1_INT_8822C BIT(19)
+#define BIT_FS_RX_BMD0_INT_8822C BIT(18)
+#define BIT_FS_RX_BMD1_INT_8822C BIT(17)
+#define BIT_FS_RXDONE_INT_8822C BIT(16)
+#define BIT_FS_WWLAN_INT_8822C BIT(15)
+#define BIT_FS_SOUND_DONE_INT_8822C BIT(14)
+#define BIT_FS_BF1_PRETO_INT_8822C BIT(11)
+#define BIT_FS_BF0_PRETO_INT_8822C BIT(10)
+#define BIT_FS_PTCL_RELEASE_MACID_INT_8822C BIT(9)
+#define BIT_FS_PRETX_ERRHLD_INT_8822C BIT(8)
+#define BIT_FS_LTE_COEX_INT_8822C BIT(6)
+#define BIT_FS_WLACTOFF_INT_8822C BIT(5)
+#define BIT_FS_WLACTON_INT_8822C BIT(4)
+#define BIT_FS_BCN_RX_INT_INT_8822C BIT(3)
+#define BIT_FS_MAILBOX_TO_I2C_INT_8822C BIT(2)
+#define BIT_FS_TRPC_TO_INT_8822C BIT(1)
+#define BIT_FS_RPC_O_T_INT_8822C BIT(0)
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_CPWM_8822C */
+#define BIT_CPWM_TOGGLING_8822C BIT(31)
+
+#define BIT_SHIFT_CPWM_MOD_8822C 24
+#define BIT_MASK_CPWM_MOD_8822C 0x7f
+#define BIT_CPWM_MOD_8822C(x)                                                  \
+	(((x) & BIT_MASK_CPWM_MOD_8822C) << BIT_SHIFT_CPWM_MOD_8822C)
+#define BITS_CPWM_MOD_8822C                                                    \
+	(BIT_MASK_CPWM_MOD_8822C << BIT_SHIFT_CPWM_MOD_8822C)
+#define BIT_CLEAR_CPWM_MOD_8822C(x) ((x) & (~BITS_CPWM_MOD_8822C))
+#define BIT_GET_CPWM_MOD_8822C(x)                                              \
+	(((x) >> BIT_SHIFT_CPWM_MOD_8822C) & BIT_MASK_CPWM_MOD_8822C)
+#define BIT_SET_CPWM_MOD_8822C(x, v)                                           \
+	(BIT_CLEAR_CPWM_MOD_8822C(x) | BIT_CPWM_MOD_8822C(v))
+
+/* 2 REG_FWIMR_8822C */
+#define BIT_FS_TXBCNOK_MB7_INT_EN_8822C BIT(31)
+#define BIT_FS_TXBCNOK_MB6_INT_EN_8822C BIT(30)
+#define BIT_FS_TXBCNOK_MB5_INT_EN_8822C BIT(29)
+#define BIT_FS_TXBCNOK_MB4_INT_EN_8822C BIT(28)
+#define BIT_FS_TXBCNOK_MB3_INT_EN_8822C BIT(27)
+#define BIT_FS_TXBCNOK_MB2_INT_EN_8822C BIT(26)
+#define BIT_FS_TXBCNOK_MB1_INT_EN_8822C BIT(25)
+#define BIT_FS_TXBCNOK_MB0_INT_EN_8822C BIT(24)
+#define BIT_FS_TXBCNERR_MB7_INT_EN_8822C BIT(23)
+#define BIT_FS_TXBCNERR_MB6_INT_EN_8822C BIT(22)
+#define BIT_FS_TXBCNERR_MB5_INT_EN_8822C BIT(21)
+#define BIT_FS_TXBCNERR_MB4_INT_EN_8822C BIT(20)
+#define BIT_FS_TXBCNERR_MB3_INT_EN_8822C BIT(19)
+#define BIT_FS_TXBCNERR_MB2_INT_EN_8822C BIT(18)
+#define BIT_FS_TXBCNERR_MB1_INT_EN_8822C BIT(17)
+#define BIT_FS_TXBCNERR_MB0_INT_EN_8822C BIT(16)
+#define BIT_CPU_MGQ_TXDONE_INT_EN_8822C BIT(15)
+#define BIT_SIFS_OVERSPEC_INT_EN_8822C BIT(14)
+#define BIT_FS_MGNTQ_RPTR_RELEASE_INT_EN_8822C BIT(13)
+#define BIT_FS_MGNTQFF_TO_INT_EN_8822C BIT(12)
+#define BIT_FS_CPUMGQ_ERR_INT_EN_8822C BIT(11)
+#define BIT_FS_DDMA0_LP_INT_EN_8822C BIT(9)
+#define BIT_FS_DDMA0_HP_INT_EN_8822C BIT(8)
+#define BIT_FS_TRXRPT_INT_EN_8822C BIT(7)
+#define BIT_FS_C2H_W_READY_INT_EN_8822C BIT(6)
+#define BIT_FS_HRCV_INT_EN_8822C BIT(5)
+#define BIT_FS_H2CCMD_INT_EN_8822C BIT(4)
+#define BIT_FS_TXPKTIN_INT_EN_8822C BIT(3)
+#define BIT_FS_ERRORHDL_INT_EN_8822C BIT(2)
+#define BIT_FS_TXCCX_INT_EN_8822C BIT(1)
+#define BIT_FS_TXCLOSE_INT_EN_8822C BIT(0)
+
+/* 2 REG_FWISR_8822C */
+#define BIT_FS_TXBCNOK_MB7_INT_8822C BIT(31)
+#define BIT_FS_TXBCNOK_MB6_INT_8822C BIT(30)
+#define BIT_FS_TXBCNOK_MB5_INT_8822C BIT(29)
+#define BIT_FS_TXBCNOK_MB4_INT_8822C BIT(28)
+#define BIT_FS_TXBCNOK_MB3_INT_8822C BIT(27)
+#define BIT_FS_TXBCNOK_MB2_INT_8822C BIT(26)
+#define BIT_FS_TXBCNOK_MB1_INT_8822C BIT(25)
+#define BIT_FS_TXBCNOK_MB0_INT_8822C BIT(24)
+#define BIT_FS_TXBCNERR_MB7_INT_8822C BIT(23)
+#define BIT_FS_TXBCNERR_MB6_INT_8822C BIT(22)
+#define BIT_FS_TXBCNERR_MB5_INT_8822C BIT(21)
+#define BIT_FS_TXBCNERR_MB4_INT_8822C BIT(20)
+#define BIT_FS_TXBCNERR_MB3_INT_8822C BIT(19)
+#define BIT_FS_TXBCNERR_MB2_INT_8822C BIT(18)
+#define BIT_FS_TXBCNERR_MB1_INT_8822C BIT(17)
+#define BIT_FS_TXBCNERR_MB0_INT_8822C BIT(16)
+#define BIT_CPU_MGQ_TXDONE_INT_8822C BIT(15)
+#define BIT_SIFS_OVERSPEC_INT_8822C BIT(14)
+#define BIT_FS_MGNTQ_RPTR_RELEASE_INT_8822C BIT(13)
+#define BIT_FS_MGNTQFF_TO_INT_8822C BIT(12)
+#define BIT_FS_CPUMGQ_ERR_INT_8822C BIT(11)
+#define BIT_FS_DDMA0_LP_INT_8822C BIT(9)
+#define BIT_FS_DDMA0_HP_INT_8822C BIT(8)
+#define BIT_FS_TRXRPT_INT_8822C BIT(7)
+#define BIT_FS_C2H_W_READY_INT_8822C BIT(6)
+#define BIT_FS_HRCV_INT_8822C BIT(5)
+#define BIT_FS_H2CCMD_INT_8822C BIT(4)
+#define BIT_FS_TXPKTIN_INT_8822C BIT(3)
+#define BIT_FS_ERRORHDL_INT_8822C BIT(2)
+#define BIT_FS_TXCCX_INT_8822C BIT(1)
+#define BIT_FS_TXCLOSE_INT_8822C BIT(0)
+
+/* 2 REG_FTIMR_8822C */
+#define BIT_PS_TIMER_C_EARLY_INT_EN_8822C BIT(23)
+#define BIT_PS_TIMER_B_EARLY_INT_EN_8822C BIT(22)
+#define BIT_PS_TIMER_A_EARLY_INT_EN_8822C BIT(21)
+#define BIT_CPUMGQ_TX_TIMER_EARLY_INT_EN_8822C BIT(20)
+#define BIT_PS_TIMER_C_INT_EN_8822C BIT(19)
+#define BIT_PS_TIMER_B_INT_EN_8822C BIT(18)
+#define BIT_PS_TIMER_A_INT_EN_8822C BIT(17)
+#define BIT_CPUMGQ_TX_TIMER_INT_EN_8822C BIT(16)
+#define BIT_FS_PS_TIMEOUT2_EN_8822C BIT(15)
+#define BIT_FS_PS_TIMEOUT1_EN_8822C BIT(14)
+#define BIT_FS_PS_TIMEOUT0_EN_8822C BIT(13)
+#define BIT_FS_GTINT8_EN_8822C BIT(8)
+#define BIT_FS_GTINT7_EN_8822C BIT(7)
+#define BIT_FS_GTINT6_EN_8822C BIT(6)
+#define BIT_FS_GTINT5_EN_8822C BIT(5)
+#define BIT_FS_GTINT4_EN_8822C BIT(4)
+#define BIT_FS_GTINT3_EN_8822C BIT(3)
+#define BIT_FS_GTINT2_EN_8822C BIT(2)
+#define BIT_FS_GTINT1_EN_8822C BIT(1)
+#define BIT_FS_GTINT0_EN_8822C BIT(0)
+
+/* 2 REG_FTISR_8822C */
+#define BIT_PS_TIMER_C_EARLY__INT_8822C BIT(23)
+#define BIT_PS_TIMER_B_EARLY__INT_8822C BIT(22)
+#define BIT_PS_TIMER_A_EARLY__INT_8822C BIT(21)
+#define BIT_CPUMGQ_TX_TIMER_EARLY_INT_8822C BIT(20)
+#define BIT_PS_TIMER_C_INT_8822C BIT(19)
+#define BIT_PS_TIMER_B_INT_8822C BIT(18)
+#define BIT_PS_TIMER_A_INT_8822C BIT(17)
+#define BIT_CPUMGQ_TX_TIMER_INT_8822C BIT(16)
+#define BIT_FS_PS_TIMEOUT2_INT_8822C BIT(15)
+#define BIT_FS_PS_TIMEOUT1_INT_8822C BIT(14)
+#define BIT_FS_PS_TIMEOUT0_INT_8822C BIT(13)
+#define BIT_FS_GTINT8_INT_8822C BIT(8)
+#define BIT_FS_GTINT7_INT_8822C BIT(7)
+#define BIT_FS_GTINT6_INT_8822C BIT(6)
+#define BIT_FS_GTINT5_INT_8822C BIT(5)
+#define BIT_FS_GTINT4_INT_8822C BIT(4)
+#define BIT_FS_GTINT3_INT_8822C BIT(3)
+#define BIT_FS_GTINT2_INT_8822C BIT(2)
+#define BIT_FS_GTINT1_INT_8822C BIT(1)
+#define BIT_FS_GTINT0_INT_8822C BIT(0)
+
+/* 2 REG_PKTBUF_DBG_CTRL_8822C */
+
+#define BIT_SHIFT_PKTBUF_WRITE_EN_8822C 24
+#define BIT_MASK_PKTBUF_WRITE_EN_8822C 0xff
+#define BIT_PKTBUF_WRITE_EN_8822C(x)                                           \
+	(((x) & BIT_MASK_PKTBUF_WRITE_EN_8822C)                                \
+	 << BIT_SHIFT_PKTBUF_WRITE_EN_8822C)
+#define BITS_PKTBUF_WRITE_EN_8822C                                             \
+	(BIT_MASK_PKTBUF_WRITE_EN_8822C << BIT_SHIFT_PKTBUF_WRITE_EN_8822C)
+#define BIT_CLEAR_PKTBUF_WRITE_EN_8822C(x) ((x) & (~BITS_PKTBUF_WRITE_EN_8822C))
+#define BIT_GET_PKTBUF_WRITE_EN_8822C(x)                                       \
+	(((x) >> BIT_SHIFT_PKTBUF_WRITE_EN_8822C) &                            \
+	 BIT_MASK_PKTBUF_WRITE_EN_8822C)
+#define BIT_SET_PKTBUF_WRITE_EN_8822C(x, v)                                    \
+	(BIT_CLEAR_PKTBUF_WRITE_EN_8822C(x) | BIT_PKTBUF_WRITE_EN_8822C(v))
+
+#define BIT_TXRPTBUF_DBG_8822C BIT(23)
+
+/* 2 REG_NOT_VALID_8822C */
+#define BIT_TXPKTBUF_DBG_V2_8822C BIT(20)
+#define BIT_RXPKTBUF_DBG_8822C BIT(16)
+
+#define BIT_SHIFT_PKTBUF_DBG_ADDR_8822C 0
+#define BIT_MASK_PKTBUF_DBG_ADDR_8822C 0x1fff
+#define BIT_PKTBUF_DBG_ADDR_8822C(x)                                           \
+	(((x) & BIT_MASK_PKTBUF_DBG_ADDR_8822C)                                \
+	 << BIT_SHIFT_PKTBUF_DBG_ADDR_8822C)
+#define BITS_PKTBUF_DBG_ADDR_8822C                                             \
+	(BIT_MASK_PKTBUF_DBG_ADDR_8822C << BIT_SHIFT_PKTBUF_DBG_ADDR_8822C)
+#define BIT_CLEAR_PKTBUF_DBG_ADDR_8822C(x) ((x) & (~BITS_PKTBUF_DBG_ADDR_8822C))
+#define BIT_GET_PKTBUF_DBG_ADDR_8822C(x)                                       \
+	(((x) >> BIT_SHIFT_PKTBUF_DBG_ADDR_8822C) &                            \
+	 BIT_MASK_PKTBUF_DBG_ADDR_8822C)
+#define BIT_SET_PKTBUF_DBG_ADDR_8822C(x, v)                                    \
+	(BIT_CLEAR_PKTBUF_DBG_ADDR_8822C(x) | BIT_PKTBUF_DBG_ADDR_8822C(v))
+
+/* 2 REG_PKTBUF_DBG_DATA_L_8822C */
+
+#define BIT_SHIFT_PKTBUF_DBG_DATA_L_8822C 0
+#define BIT_MASK_PKTBUF_DBG_DATA_L_8822C 0xffffffffL
+#define BIT_PKTBUF_DBG_DATA_L_8822C(x)                                         \
+	(((x) & BIT_MASK_PKTBUF_DBG_DATA_L_8822C)                              \
+	 << BIT_SHIFT_PKTBUF_DBG_DATA_L_8822C)
+#define BITS_PKTBUF_DBG_DATA_L_8822C                                           \
+	(BIT_MASK_PKTBUF_DBG_DATA_L_8822C << BIT_SHIFT_PKTBUF_DBG_DATA_L_8822C)
+#define BIT_CLEAR_PKTBUF_DBG_DATA_L_8822C(x)                                   \
+	((x) & (~BITS_PKTBUF_DBG_DATA_L_8822C))
+#define BIT_GET_PKTBUF_DBG_DATA_L_8822C(x)                                     \
+	(((x) >> BIT_SHIFT_PKTBUF_DBG_DATA_L_8822C) &                          \
+	 BIT_MASK_PKTBUF_DBG_DATA_L_8822C)
+#define BIT_SET_PKTBUF_DBG_DATA_L_8822C(x, v)                                  \
+	(BIT_CLEAR_PKTBUF_DBG_DATA_L_8822C(x) | BIT_PKTBUF_DBG_DATA_L_8822C(v))
+
+/* 2 REG_PKTBUF_DBG_DATA_H_8822C */
+
+#define BIT_SHIFT_PKTBUF_DBG_DATA_H_8822C 0
+#define BIT_MASK_PKTBUF_DBG_DATA_H_8822C 0xffffffffL
+#define BIT_PKTBUF_DBG_DATA_H_8822C(x)                                         \
+	(((x) & BIT_MASK_PKTBUF_DBG_DATA_H_8822C)                              \
+	 << BIT_SHIFT_PKTBUF_DBG_DATA_H_8822C)
+#define BITS_PKTBUF_DBG_DATA_H_8822C                                           \
+	(BIT_MASK_PKTBUF_DBG_DATA_H_8822C << BIT_SHIFT_PKTBUF_DBG_DATA_H_8822C)
+#define BIT_CLEAR_PKTBUF_DBG_DATA_H_8822C(x)                                   \
+	((x) & (~BITS_PKTBUF_DBG_DATA_H_8822C))
+#define BIT_GET_PKTBUF_DBG_DATA_H_8822C(x)                                     \
+	(((x) >> BIT_SHIFT_PKTBUF_DBG_DATA_H_8822C) &                          \
+	 BIT_MASK_PKTBUF_DBG_DATA_H_8822C)
+#define BIT_SET_PKTBUF_DBG_DATA_H_8822C(x, v)                                  \
+	(BIT_CLEAR_PKTBUF_DBG_DATA_H_8822C(x) | BIT_PKTBUF_DBG_DATA_H_8822C(v))
+
+/* 2 REG_CPWM2_8822C */
+
+#define BIT_SHIFT_L0S_TO_RCVY_NUM_8822C 16
+#define BIT_MASK_L0S_TO_RCVY_NUM_8822C 0xff
+#define BIT_L0S_TO_RCVY_NUM_8822C(x)                                           \
+	(((x) & BIT_MASK_L0S_TO_RCVY_NUM_8822C)                                \
+	 << BIT_SHIFT_L0S_TO_RCVY_NUM_8822C)
+#define BITS_L0S_TO_RCVY_NUM_8822C                                             \
+	(BIT_MASK_L0S_TO_RCVY_NUM_8822C << BIT_SHIFT_L0S_TO_RCVY_NUM_8822C)
+#define BIT_CLEAR_L0S_TO_RCVY_NUM_8822C(x) ((x) & (~BITS_L0S_TO_RCVY_NUM_8822C))
+#define BIT_GET_L0S_TO_RCVY_NUM_8822C(x)                                       \
+	(((x) >> BIT_SHIFT_L0S_TO_RCVY_NUM_8822C) &                            \
+	 BIT_MASK_L0S_TO_RCVY_NUM_8822C)
+#define BIT_SET_L0S_TO_RCVY_NUM_8822C(x, v)                                    \
+	(BIT_CLEAR_L0S_TO_RCVY_NUM_8822C(x) | BIT_L0S_TO_RCVY_NUM_8822C(v))
+
+#define BIT_CPWM2_TOGGLING_8822C BIT(15)
+
+#define BIT_SHIFT_CPWM2_MOD_8822C 0
+#define BIT_MASK_CPWM2_MOD_8822C 0x7fff
+#define BIT_CPWM2_MOD_8822C(x)                                                 \
+	(((x) & BIT_MASK_CPWM2_MOD_8822C) << BIT_SHIFT_CPWM2_MOD_8822C)
+#define BITS_CPWM2_MOD_8822C                                                   \
+	(BIT_MASK_CPWM2_MOD_8822C << BIT_SHIFT_CPWM2_MOD_8822C)
+#define BIT_CLEAR_CPWM2_MOD_8822C(x) ((x) & (~BITS_CPWM2_MOD_8822C))
+#define BIT_GET_CPWM2_MOD_8822C(x)                                             \
+	(((x) >> BIT_SHIFT_CPWM2_MOD_8822C) & BIT_MASK_CPWM2_MOD_8822C)
+#define BIT_SET_CPWM2_MOD_8822C(x, v)                                          \
+	(BIT_CLEAR_CPWM2_MOD_8822C(x) | BIT_CPWM2_MOD_8822C(v))
+
+/* 2 REG_TC0_CTRL_8822C */
+#define BIT_TC0INT_EN_8822C BIT(26)
+#define BIT_TC0MODE_8822C BIT(25)
+#define BIT_TC0EN_8822C BIT(24)
+
+#define BIT_SHIFT_TC0DATA_8822C 0
+#define BIT_MASK_TC0DATA_8822C 0xffffff
+#define BIT_TC0DATA_8822C(x)                                                   \
+	(((x) & BIT_MASK_TC0DATA_8822C) << BIT_SHIFT_TC0DATA_8822C)
+#define BITS_TC0DATA_8822C (BIT_MASK_TC0DATA_8822C << BIT_SHIFT_TC0DATA_8822C)
+#define BIT_CLEAR_TC0DATA_8822C(x) ((x) & (~BITS_TC0DATA_8822C))
+#define BIT_GET_TC0DATA_8822C(x)                                               \
+	(((x) >> BIT_SHIFT_TC0DATA_8822C) & BIT_MASK_TC0DATA_8822C)
+#define BIT_SET_TC0DATA_8822C(x, v)                                            \
+	(BIT_CLEAR_TC0DATA_8822C(x) | BIT_TC0DATA_8822C(v))
+
+/* 2 REG_TC1_CTRL_8822C */
+#define BIT_TC1INT_EN_8822C BIT(26)
+#define BIT_TC1MODE_8822C BIT(25)
+#define BIT_TC1EN_8822C BIT(24)
+
+#define BIT_SHIFT_TC1DATA_8822C 0
+#define BIT_MASK_TC1DATA_8822C 0xffffff
+#define BIT_TC1DATA_8822C(x)                                                   \
+	(((x) & BIT_MASK_TC1DATA_8822C) << BIT_SHIFT_TC1DATA_8822C)
+#define BITS_TC1DATA_8822C (BIT_MASK_TC1DATA_8822C << BIT_SHIFT_TC1DATA_8822C)
+#define BIT_CLEAR_TC1DATA_8822C(x) ((x) & (~BITS_TC1DATA_8822C))
+#define BIT_GET_TC1DATA_8822C(x)                                               \
+	(((x) >> BIT_SHIFT_TC1DATA_8822C) & BIT_MASK_TC1DATA_8822C)
+#define BIT_SET_TC1DATA_8822C(x, v)                                            \
+	(BIT_CLEAR_TC1DATA_8822C(x) | BIT_TC1DATA_8822C(v))
+
+/* 2 REG_TC2_CTRL_8822C */
+#define BIT_TC2INT_EN_8822C BIT(26)
+#define BIT_TC2MODE_8822C BIT(25)
+#define BIT_TC2EN_8822C BIT(24)
+
+#define BIT_SHIFT_TC2DATA_8822C 0
+#define BIT_MASK_TC2DATA_8822C 0xffffff
+#define BIT_TC2DATA_8822C(x)                                                   \
+	(((x) & BIT_MASK_TC2DATA_8822C) << BIT_SHIFT_TC2DATA_8822C)
+#define BITS_TC2DATA_8822C (BIT_MASK_TC2DATA_8822C << BIT_SHIFT_TC2DATA_8822C)
+#define BIT_CLEAR_TC2DATA_8822C(x) ((x) & (~BITS_TC2DATA_8822C))
+#define BIT_GET_TC2DATA_8822C(x)                                               \
+	(((x) >> BIT_SHIFT_TC2DATA_8822C) & BIT_MASK_TC2DATA_8822C)
+#define BIT_SET_TC2DATA_8822C(x, v)                                            \
+	(BIT_CLEAR_TC2DATA_8822C(x) | BIT_TC2DATA_8822C(v))
+
+/* 2 REG_TC3_CTRL_8822C */
+#define BIT_TC3INT_EN_8822C BIT(26)
+#define BIT_TC3MODE_8822C BIT(25)
+#define BIT_TC3EN_8822C BIT(24)
+
+#define BIT_SHIFT_TC3DATA_8822C 0
+#define BIT_MASK_TC3DATA_8822C 0xffffff
+#define BIT_TC3DATA_8822C(x)                                                   \
+	(((x) & BIT_MASK_TC3DATA_8822C) << BIT_SHIFT_TC3DATA_8822C)
+#define BITS_TC3DATA_8822C (BIT_MASK_TC3DATA_8822C << BIT_SHIFT_TC3DATA_8822C)
+#define BIT_CLEAR_TC3DATA_8822C(x) ((x) & (~BITS_TC3DATA_8822C))
+#define BIT_GET_TC3DATA_8822C(x)                                               \
+	(((x) >> BIT_SHIFT_TC3DATA_8822C) & BIT_MASK_TC3DATA_8822C)
+#define BIT_SET_TC3DATA_8822C(x, v)                                            \
+	(BIT_CLEAR_TC3DATA_8822C(x) | BIT_TC3DATA_8822C(v))
+
+/* 2 REG_TC4_CTRL_8822C */
+#define BIT_TC4INT_EN_8822C BIT(26)
+#define BIT_TC4MODE_8822C BIT(25)
+#define BIT_TC4EN_8822C BIT(24)
+
+#define BIT_SHIFT_TC4DATA_8822C 0
+#define BIT_MASK_TC4DATA_8822C 0xffffff
+#define BIT_TC4DATA_8822C(x)                                                   \
+	(((x) & BIT_MASK_TC4DATA_8822C) << BIT_SHIFT_TC4DATA_8822C)
+#define BITS_TC4DATA_8822C (BIT_MASK_TC4DATA_8822C << BIT_SHIFT_TC4DATA_8822C)
+#define BIT_CLEAR_TC4DATA_8822C(x) ((x) & (~BITS_TC4DATA_8822C))
+#define BIT_GET_TC4DATA_8822C(x)                                               \
+	(((x) >> BIT_SHIFT_TC4DATA_8822C) & BIT_MASK_TC4DATA_8822C)
+#define BIT_SET_TC4DATA_8822C(x, v)                                            \
+	(BIT_CLEAR_TC4DATA_8822C(x) | BIT_TC4DATA_8822C(v))
+
+/* 2 REG_TCUNIT_BASE_8822C */
+
+#define BIT_SHIFT_TCUNIT_BASE_8822C 0
+#define BIT_MASK_TCUNIT_BASE_8822C 0x3fff
+#define BIT_TCUNIT_BASE_8822C(x)                                               \
+	(((x) & BIT_MASK_TCUNIT_BASE_8822C) << BIT_SHIFT_TCUNIT_BASE_8822C)
+#define BITS_TCUNIT_BASE_8822C                                                 \
+	(BIT_MASK_TCUNIT_BASE_8822C << BIT_SHIFT_TCUNIT_BASE_8822C)
+#define BIT_CLEAR_TCUNIT_BASE_8822C(x) ((x) & (~BITS_TCUNIT_BASE_8822C))
+#define BIT_GET_TCUNIT_BASE_8822C(x)                                           \
+	(((x) >> BIT_SHIFT_TCUNIT_BASE_8822C) & BIT_MASK_TCUNIT_BASE_8822C)
+#define BIT_SET_TCUNIT_BASE_8822C(x, v)                                        \
+	(BIT_CLEAR_TCUNIT_BASE_8822C(x) | BIT_TCUNIT_BASE_8822C(v))
+
+/* 2 REG_TC5_CTRL_8822C */
+#define BIT_TC5INT_EN_8822C BIT(26)
+#define BIT_TC5MODE_8822C BIT(25)
+#define BIT_TC5EN_8822C BIT(24)
+
+#define BIT_SHIFT_TC5DATA_8822C 0
+#define BIT_MASK_TC5DATA_8822C 0xffffff
+#define BIT_TC5DATA_8822C(x)                                                   \
+	(((x) & BIT_MASK_TC5DATA_8822C) << BIT_SHIFT_TC5DATA_8822C)
+#define BITS_TC5DATA_8822C (BIT_MASK_TC5DATA_8822C << BIT_SHIFT_TC5DATA_8822C)
+#define BIT_CLEAR_TC5DATA_8822C(x) ((x) & (~BITS_TC5DATA_8822C))
+#define BIT_GET_TC5DATA_8822C(x)                                               \
+	(((x) >> BIT_SHIFT_TC5DATA_8822C) & BIT_MASK_TC5DATA_8822C)
+#define BIT_SET_TC5DATA_8822C(x, v)                                            \
+	(BIT_CLEAR_TC5DATA_8822C(x) | BIT_TC5DATA_8822C(v))
+
+/* 2 REG_TC6_CTRL_8822C */
+#define BIT_TC6INT_EN_8822C BIT(26)
+#define BIT_TC6MODE_8822C BIT(25)
+#define BIT_TC6EN_8822C BIT(24)
+
+#define BIT_SHIFT_TC6DATA_8822C 0
+#define BIT_MASK_TC6DATA_8822C 0xffffff
+#define BIT_TC6DATA_8822C(x)                                                   \
+	(((x) & BIT_MASK_TC6DATA_8822C) << BIT_SHIFT_TC6DATA_8822C)
+#define BITS_TC6DATA_8822C (BIT_MASK_TC6DATA_8822C << BIT_SHIFT_TC6DATA_8822C)
+#define BIT_CLEAR_TC6DATA_8822C(x) ((x) & (~BITS_TC6DATA_8822C))
+#define BIT_GET_TC6DATA_8822C(x)                                               \
+	(((x) >> BIT_SHIFT_TC6DATA_8822C) & BIT_MASK_TC6DATA_8822C)
+#define BIT_SET_TC6DATA_8822C(x, v)                                            \
+	(BIT_CLEAR_TC6DATA_8822C(x) | BIT_TC6DATA_8822C(v))
+
+/* 2 REG_MBIST_DRF_FAIL_8822C */
+
+#define BIT_SHIFT_8051_MBIST_DRF_FAIL_8822C 26
+#define BIT_MASK_8051_MBIST_DRF_FAIL_8822C 0x3f
+#define BIT_8051_MBIST_DRF_FAIL_8822C(x)                                       \
+	(((x) & BIT_MASK_8051_MBIST_DRF_FAIL_8822C)                            \
+	 << BIT_SHIFT_8051_MBIST_DRF_FAIL_8822C)
+#define BITS_8051_MBIST_DRF_FAIL_8822C                                         \
+	(BIT_MASK_8051_MBIST_DRF_FAIL_8822C                                    \
+	 << BIT_SHIFT_8051_MBIST_DRF_FAIL_8822C)
+#define BIT_CLEAR_8051_MBIST_DRF_FAIL_8822C(x)                                 \
+	((x) & (~BITS_8051_MBIST_DRF_FAIL_8822C))
+#define BIT_GET_8051_MBIST_DRF_FAIL_8822C(x)                                   \
+	(((x) >> BIT_SHIFT_8051_MBIST_DRF_FAIL_8822C) &                        \
+	 BIT_MASK_8051_MBIST_DRF_FAIL_8822C)
+#define BIT_SET_8051_MBIST_DRF_FAIL_8822C(x, v)                                \
+	(BIT_CLEAR_8051_MBIST_DRF_FAIL_8822C(x) |                              \
+	 BIT_8051_MBIST_DRF_FAIL_8822C(v))
+
+#define BIT_SHIFT_USB_MBIST_DRF_FAIL_8822C 24
+#define BIT_MASK_USB_MBIST_DRF_FAIL_8822C 0x3
+#define BIT_USB_MBIST_DRF_FAIL_8822C(x)                                        \
+	(((x) & BIT_MASK_USB_MBIST_DRF_FAIL_8822C)                             \
+	 << BIT_SHIFT_USB_MBIST_DRF_FAIL_8822C)
+#define BITS_USB_MBIST_DRF_FAIL_8822C                                          \
+	(BIT_MASK_USB_MBIST_DRF_FAIL_8822C                                     \
+	 << BIT_SHIFT_USB_MBIST_DRF_FAIL_8822C)
+#define BIT_CLEAR_USB_MBIST_DRF_FAIL_8822C(x)                                  \
+	((x) & (~BITS_USB_MBIST_DRF_FAIL_8822C))
+#define BIT_GET_USB_MBIST_DRF_FAIL_8822C(x)                                    \
+	(((x) >> BIT_SHIFT_USB_MBIST_DRF_FAIL_8822C) &                         \
+	 BIT_MASK_USB_MBIST_DRF_FAIL_8822C)
+#define BIT_SET_USB_MBIST_DRF_FAIL_8822C(x, v)                                 \
+	(BIT_CLEAR_USB_MBIST_DRF_FAIL_8822C(x) |                               \
+	 BIT_USB_MBIST_DRF_FAIL_8822C(v))
+
+#define BIT_SHIFT_PCIE_MBIST_DRF_FAIL_8822C 18
+#define BIT_MASK_PCIE_MBIST_DRF_FAIL_8822C 0x3f
+#define BIT_PCIE_MBIST_DRF_FAIL_8822C(x)                                       \
+	(((x) & BIT_MASK_PCIE_MBIST_DRF_FAIL_8822C)                            \
+	 << BIT_SHIFT_PCIE_MBIST_DRF_FAIL_8822C)
+#define BITS_PCIE_MBIST_DRF_FAIL_8822C                                         \
+	(BIT_MASK_PCIE_MBIST_DRF_FAIL_8822C                                    \
+	 << BIT_SHIFT_PCIE_MBIST_DRF_FAIL_8822C)
+#define BIT_CLEAR_PCIE_MBIST_DRF_FAIL_8822C(x)                                 \
+	((x) & (~BITS_PCIE_MBIST_DRF_FAIL_8822C))
+#define BIT_GET_PCIE_MBIST_DRF_FAIL_8822C(x)                                   \
+	(((x) >> BIT_SHIFT_PCIE_MBIST_DRF_FAIL_8822C) &                        \
+	 BIT_MASK_PCIE_MBIST_DRF_FAIL_8822C)
+#define BIT_SET_PCIE_MBIST_DRF_FAIL_8822C(x, v)                                \
+	(BIT_CLEAR_PCIE_MBIST_DRF_FAIL_8822C(x) |                              \
+	 BIT_PCIE_MBIST_DRF_FAIL_8822C(v))
+
+#define BIT_SHIFT_MAC_MBIST_DRF_FAIL_8822C 0
+#define BIT_MASK_MAC_MBIST_DRF_FAIL_8822C 0x3ffff
+#define BIT_MAC_MBIST_DRF_FAIL_8822C(x)                                        \
+	(((x) & BIT_MASK_MAC_MBIST_DRF_FAIL_8822C)                             \
+	 << BIT_SHIFT_MAC_MBIST_DRF_FAIL_8822C)
+#define BITS_MAC_MBIST_DRF_FAIL_8822C                                          \
+	(BIT_MASK_MAC_MBIST_DRF_FAIL_8822C                                     \
+	 << BIT_SHIFT_MAC_MBIST_DRF_FAIL_8822C)
+#define BIT_CLEAR_MAC_MBIST_DRF_FAIL_8822C(x)                                  \
+	((x) & (~BITS_MAC_MBIST_DRF_FAIL_8822C))
+#define BIT_GET_MAC_MBIST_DRF_FAIL_8822C(x)                                    \
+	(((x) >> BIT_SHIFT_MAC_MBIST_DRF_FAIL_8822C) &                         \
+	 BIT_MASK_MAC_MBIST_DRF_FAIL_8822C)
+#define BIT_SET_MAC_MBIST_DRF_FAIL_8822C(x, v)                                 \
+	(BIT_CLEAR_MAC_MBIST_DRF_FAIL_8822C(x) |                               \
+	 BIT_MAC_MBIST_DRF_FAIL_8822C(v))
+
+/* 2 REG_MBIST_START_PAUSE_8822C */
+
+#define BIT_SHIFT_8051_MBIST_START_PAUSE_V1_8822C 26
+#define BIT_MASK_8051_MBIST_START_PAUSE_V1_8822C 0x3f
+#define BIT_8051_MBIST_START_PAUSE_V1_8822C(x)                                 \
+	(((x) & BIT_MASK_8051_MBIST_START_PAUSE_V1_8822C)                      \
+	 << BIT_SHIFT_8051_MBIST_START_PAUSE_V1_8822C)
+#define BITS_8051_MBIST_START_PAUSE_V1_8822C                                   \
+	(BIT_MASK_8051_MBIST_START_PAUSE_V1_8822C                              \
+	 << BIT_SHIFT_8051_MBIST_START_PAUSE_V1_8822C)
+#define BIT_CLEAR_8051_MBIST_START_PAUSE_V1_8822C(x)                           \
+	((x) & (~BITS_8051_MBIST_START_PAUSE_V1_8822C))
+#define BIT_GET_8051_MBIST_START_PAUSE_V1_8822C(x)                             \
+	(((x) >> BIT_SHIFT_8051_MBIST_START_PAUSE_V1_8822C) &                  \
+	 BIT_MASK_8051_MBIST_START_PAUSE_V1_8822C)
+#define BIT_SET_8051_MBIST_START_PAUSE_V1_8822C(x, v)                          \
+	(BIT_CLEAR_8051_MBIST_START_PAUSE_V1_8822C(x) |                        \
+	 BIT_8051_MBIST_START_PAUSE_V1_8822C(v))
+
+#define BIT_SHIFT_USB_MBIST_START_PAUSE_V1_8822C 24
+#define BIT_MASK_USB_MBIST_START_PAUSE_V1_8822C 0x3
+#define BIT_USB_MBIST_START_PAUSE_V1_8822C(x)                                  \
+	(((x) & BIT_MASK_USB_MBIST_START_PAUSE_V1_8822C)                       \
+	 << BIT_SHIFT_USB_MBIST_START_PAUSE_V1_8822C)
+#define BITS_USB_MBIST_START_PAUSE_V1_8822C                                    \
+	(BIT_MASK_USB_MBIST_START_PAUSE_V1_8822C                               \
+	 << BIT_SHIFT_USB_MBIST_START_PAUSE_V1_8822C)
+#define BIT_CLEAR_USB_MBIST_START_PAUSE_V1_8822C(x)                            \
+	((x) & (~BITS_USB_MBIST_START_PAUSE_V1_8822C))
+#define BIT_GET_USB_MBIST_START_PAUSE_V1_8822C(x)                              \
+	(((x) >> BIT_SHIFT_USB_MBIST_START_PAUSE_V1_8822C) &                   \
+	 BIT_MASK_USB_MBIST_START_PAUSE_V1_8822C)
+#define BIT_SET_USB_MBIST_START_PAUSE_V1_8822C(x, v)                           \
+	(BIT_CLEAR_USB_MBIST_START_PAUSE_V1_8822C(x) |                         \
+	 BIT_USB_MBIST_START_PAUSE_V1_8822C(v))
+
+#define BIT_SHIFT_PCIE_MBIST_START_PAUSE_V1_8822C 18
+#define BIT_MASK_PCIE_MBIST_START_PAUSE_V1_8822C 0x3f
+#define BIT_PCIE_MBIST_START_PAUSE_V1_8822C(x)                                 \
+	(((x) & BIT_MASK_PCIE_MBIST_START_PAUSE_V1_8822C)                      \
+	 << BIT_SHIFT_PCIE_MBIST_START_PAUSE_V1_8822C)
+#define BITS_PCIE_MBIST_START_PAUSE_V1_8822C                                   \
+	(BIT_MASK_PCIE_MBIST_START_PAUSE_V1_8822C                              \
+	 << BIT_SHIFT_PCIE_MBIST_START_PAUSE_V1_8822C)
+#define BIT_CLEAR_PCIE_MBIST_START_PAUSE_V1_8822C(x)                           \
+	((x) & (~BITS_PCIE_MBIST_START_PAUSE_V1_8822C))
+#define BIT_GET_PCIE_MBIST_START_PAUSE_V1_8822C(x)                             \
+	(((x) >> BIT_SHIFT_PCIE_MBIST_START_PAUSE_V1_8822C) &                  \
+	 BIT_MASK_PCIE_MBIST_START_PAUSE_V1_8822C)
+#define BIT_SET_PCIE_MBIST_START_PAUSE_V1_8822C(x, v)                          \
+	(BIT_CLEAR_PCIE_MBIST_START_PAUSE_V1_8822C(x) |                        \
+	 BIT_PCIE_MBIST_START_PAUSE_V1_8822C(v))
+
+#define BIT_SHIFT_MAC_MBIST_START_PAUSE_V1_8822C 0
+#define BIT_MASK_MAC_MBIST_START_PAUSE_V1_8822C 0x3ffff
+#define BIT_MAC_MBIST_START_PAUSE_V1_8822C(x)                                  \
+	(((x) & BIT_MASK_MAC_MBIST_START_PAUSE_V1_8822C)                       \
+	 << BIT_SHIFT_MAC_MBIST_START_PAUSE_V1_8822C)
+#define BITS_MAC_MBIST_START_PAUSE_V1_8822C                                    \
+	(BIT_MASK_MAC_MBIST_START_PAUSE_V1_8822C                               \
+	 << BIT_SHIFT_MAC_MBIST_START_PAUSE_V1_8822C)
+#define BIT_CLEAR_MAC_MBIST_START_PAUSE_V1_8822C(x)                            \
+	((x) & (~BITS_MAC_MBIST_START_PAUSE_V1_8822C))
+#define BIT_GET_MAC_MBIST_START_PAUSE_V1_8822C(x)                              \
+	(((x) >> BIT_SHIFT_MAC_MBIST_START_PAUSE_V1_8822C) &                   \
+	 BIT_MASK_MAC_MBIST_START_PAUSE_V1_8822C)
+#define BIT_SET_MAC_MBIST_START_PAUSE_V1_8822C(x, v)                           \
+	(BIT_CLEAR_MAC_MBIST_START_PAUSE_V1_8822C(x) |                         \
+	 BIT_MAC_MBIST_START_PAUSE_V1_8822C(v))
+
+/* 2 REG_MBIST_DONE_8822C */
+
+#define BIT_SHIFT_8051_MBIST_DONE_V1_8822C 26
+#define BIT_MASK_8051_MBIST_DONE_V1_8822C 0x3f
+#define BIT_8051_MBIST_DONE_V1_8822C(x)                                        \
+	(((x) & BIT_MASK_8051_MBIST_DONE_V1_8822C)                             \
+	 << BIT_SHIFT_8051_MBIST_DONE_V1_8822C)
+#define BITS_8051_MBIST_DONE_V1_8822C                                          \
+	(BIT_MASK_8051_MBIST_DONE_V1_8822C                                     \
+	 << BIT_SHIFT_8051_MBIST_DONE_V1_8822C)
+#define BIT_CLEAR_8051_MBIST_DONE_V1_8822C(x)                                  \
+	((x) & (~BITS_8051_MBIST_DONE_V1_8822C))
+#define BIT_GET_8051_MBIST_DONE_V1_8822C(x)                                    \
+	(((x) >> BIT_SHIFT_8051_MBIST_DONE_V1_8822C) &                         \
+	 BIT_MASK_8051_MBIST_DONE_V1_8822C)
+#define BIT_SET_8051_MBIST_DONE_V1_8822C(x, v)                                 \
+	(BIT_CLEAR_8051_MBIST_DONE_V1_8822C(x) |                               \
+	 BIT_8051_MBIST_DONE_V1_8822C(v))
+
+#define BIT_SHIFT_USB_MBIST_DONE_V1_8822C 24
+#define BIT_MASK_USB_MBIST_DONE_V1_8822C 0x3
+#define BIT_USB_MBIST_DONE_V1_8822C(x)                                         \
+	(((x) & BIT_MASK_USB_MBIST_DONE_V1_8822C)                              \
+	 << BIT_SHIFT_USB_MBIST_DONE_V1_8822C)
+#define BITS_USB_MBIST_DONE_V1_8822C                                           \
+	(BIT_MASK_USB_MBIST_DONE_V1_8822C << BIT_SHIFT_USB_MBIST_DONE_V1_8822C)
+#define BIT_CLEAR_USB_MBIST_DONE_V1_8822C(x)                                   \
+	((x) & (~BITS_USB_MBIST_DONE_V1_8822C))
+#define BIT_GET_USB_MBIST_DONE_V1_8822C(x)                                     \
+	(((x) >> BIT_SHIFT_USB_MBIST_DONE_V1_8822C) &                          \
+	 BIT_MASK_USB_MBIST_DONE_V1_8822C)
+#define BIT_SET_USB_MBIST_DONE_V1_8822C(x, v)                                  \
+	(BIT_CLEAR_USB_MBIST_DONE_V1_8822C(x) | BIT_USB_MBIST_DONE_V1_8822C(v))
+
+#define BIT_SHIFT_PCIE_MBIST_DONE_V1_8822C 18
+#define BIT_MASK_PCIE_MBIST_DONE_V1_8822C 0x3f
+#define BIT_PCIE_MBIST_DONE_V1_8822C(x)                                        \
+	(((x) & BIT_MASK_PCIE_MBIST_DONE_V1_8822C)                             \
+	 << BIT_SHIFT_PCIE_MBIST_DONE_V1_8822C)
+#define BITS_PCIE_MBIST_DONE_V1_8822C                                          \
+	(BIT_MASK_PCIE_MBIST_DONE_V1_8822C                                     \
+	 << BIT_SHIFT_PCIE_MBIST_DONE_V1_8822C)
+#define BIT_CLEAR_PCIE_MBIST_DONE_V1_8822C(x)                                  \
+	((x) & (~BITS_PCIE_MBIST_DONE_V1_8822C))
+#define BIT_GET_PCIE_MBIST_DONE_V1_8822C(x)                                    \
+	(((x) >> BIT_SHIFT_PCIE_MBIST_DONE_V1_8822C) &                         \
+	 BIT_MASK_PCIE_MBIST_DONE_V1_8822C)
+#define BIT_SET_PCIE_MBIST_DONE_V1_8822C(x, v)                                 \
+	(BIT_CLEAR_PCIE_MBIST_DONE_V1_8822C(x) |                               \
+	 BIT_PCIE_MBIST_DONE_V1_8822C(v))
+
+#define BIT_SHIFT_MAC_MBIST_DONE_V1_8822C 0
+#define BIT_MASK_MAC_MBIST_DONE_V1_8822C 0x3ffff
+#define BIT_MAC_MBIST_DONE_V1_8822C(x)                                         \
+	(((x) & BIT_MASK_MAC_MBIST_DONE_V1_8822C)                              \
+	 << BIT_SHIFT_MAC_MBIST_DONE_V1_8822C)
+#define BITS_MAC_MBIST_DONE_V1_8822C                                           \
+	(BIT_MASK_MAC_MBIST_DONE_V1_8822C << BIT_SHIFT_MAC_MBIST_DONE_V1_8822C)
+#define BIT_CLEAR_MAC_MBIST_DONE_V1_8822C(x)                                   \
+	((x) & (~BITS_MAC_MBIST_DONE_V1_8822C))
+#define BIT_GET_MAC_MBIST_DONE_V1_8822C(x)                                     \
+	(((x) >> BIT_SHIFT_MAC_MBIST_DONE_V1_8822C) &                          \
+	 BIT_MASK_MAC_MBIST_DONE_V1_8822C)
+#define BIT_SET_MAC_MBIST_DONE_V1_8822C(x, v)                                  \
+	(BIT_CLEAR_MAC_MBIST_DONE_V1_8822C(x) | BIT_MAC_MBIST_DONE_V1_8822C(v))
+
+/* 2 REG_MBIST_READ_BIST_RPT_8822C */
+
+#define BIT_SHIFT_MBIST_READ_BIST_RPT_8822C 0
+#define BIT_MASK_MBIST_READ_BIST_RPT_8822C 0xffffffffL
+#define BIT_MBIST_READ_BIST_RPT_8822C(x)                                       \
+	(((x) & BIT_MASK_MBIST_READ_BIST_RPT_8822C)                            \
+	 << BIT_SHIFT_MBIST_READ_BIST_RPT_8822C)
+#define BITS_MBIST_READ_BIST_RPT_8822C                                         \
+	(BIT_MASK_MBIST_READ_BIST_RPT_8822C                                    \
+	 << BIT_SHIFT_MBIST_READ_BIST_RPT_8822C)
+#define BIT_CLEAR_MBIST_READ_BIST_RPT_8822C(x)                                 \
+	((x) & (~BITS_MBIST_READ_BIST_RPT_8822C))
+#define BIT_GET_MBIST_READ_BIST_RPT_8822C(x)                                   \
+	(((x) >> BIT_SHIFT_MBIST_READ_BIST_RPT_8822C) &                        \
+	 BIT_MASK_MBIST_READ_BIST_RPT_8822C)
+#define BIT_SET_MBIST_READ_BIST_RPT_8822C(x, v)                                \
+	(BIT_CLEAR_MBIST_READ_BIST_RPT_8822C(x) |                              \
+	 BIT_MBIST_READ_BIST_RPT_8822C(v))
+
+/* 2 REG_AES_DECRPT_DATA_8822C */
+
+#define BIT_SHIFT_IPS_CFG_ADDR_8822C 0
+#define BIT_MASK_IPS_CFG_ADDR_8822C 0xff
+#define BIT_IPS_CFG_ADDR_8822C(x)                                              \
+	(((x) & BIT_MASK_IPS_CFG_ADDR_8822C) << BIT_SHIFT_IPS_CFG_ADDR_8822C)
+#define BITS_IPS_CFG_ADDR_8822C                                                \
+	(BIT_MASK_IPS_CFG_ADDR_8822C << BIT_SHIFT_IPS_CFG_ADDR_8822C)
+#define BIT_CLEAR_IPS_CFG_ADDR_8822C(x) ((x) & (~BITS_IPS_CFG_ADDR_8822C))
+#define BIT_GET_IPS_CFG_ADDR_8822C(x)                                          \
+	(((x) >> BIT_SHIFT_IPS_CFG_ADDR_8822C) & BIT_MASK_IPS_CFG_ADDR_8822C)
+#define BIT_SET_IPS_CFG_ADDR_8822C(x, v)                                       \
+	(BIT_CLEAR_IPS_CFG_ADDR_8822C(x) | BIT_IPS_CFG_ADDR_8822C(v))
+
+/* 2 REG_AES_DECRPT_CFG_8822C */
+
+#define BIT_SHIFT_IPS_CFG_DATA_8822C 0
+#define BIT_MASK_IPS_CFG_DATA_8822C 0xffffffffL
+#define BIT_IPS_CFG_DATA_8822C(x)                                              \
+	(((x) & BIT_MASK_IPS_CFG_DATA_8822C) << BIT_SHIFT_IPS_CFG_DATA_8822C)
+#define BITS_IPS_CFG_DATA_8822C                                                \
+	(BIT_MASK_IPS_CFG_DATA_8822C << BIT_SHIFT_IPS_CFG_DATA_8822C)
+#define BIT_CLEAR_IPS_CFG_DATA_8822C(x) ((x) & (~BITS_IPS_CFG_DATA_8822C))
+#define BIT_GET_IPS_CFG_DATA_8822C(x)                                          \
+	(((x) >> BIT_SHIFT_IPS_CFG_DATA_8822C) & BIT_MASK_IPS_CFG_DATA_8822C)
+#define BIT_SET_IPS_CFG_DATA_8822C(x, v)                                       \
+	(BIT_CLEAR_IPS_CFG_DATA_8822C(x) | BIT_IPS_CFG_DATA_8822C(v))
+
+/* 2 REG_HIOE_CTRL_8822C */
+#define BIT_HIOE_CFG_FILE_LOC_SEL_8822C BIT(31)
+#define BIT_HIOE_WRITE_REQ_8822C BIT(30)
+#define BIT_HIOE_READ_REQ_8822C BIT(29)
+#define BIT_INST_FORMAT_ERR_8822C BIT(25)
+#define BIT_OP_TIMEOUT_ERR_8822C BIT(24)
+
+#define BIT_SHIFT_HIOE_OP_TIMEOUT_8822C 16
+#define BIT_MASK_HIOE_OP_TIMEOUT_8822C 0xff
+#define BIT_HIOE_OP_TIMEOUT_8822C(x)                                           \
+	(((x) & BIT_MASK_HIOE_OP_TIMEOUT_8822C)                                \
+	 << BIT_SHIFT_HIOE_OP_TIMEOUT_8822C)
+#define BITS_HIOE_OP_TIMEOUT_8822C                                             \
+	(BIT_MASK_HIOE_OP_TIMEOUT_8822C << BIT_SHIFT_HIOE_OP_TIMEOUT_8822C)
+#define BIT_CLEAR_HIOE_OP_TIMEOUT_8822C(x) ((x) & (~BITS_HIOE_OP_TIMEOUT_8822C))
+#define BIT_GET_HIOE_OP_TIMEOUT_8822C(x)                                       \
+	(((x) >> BIT_SHIFT_HIOE_OP_TIMEOUT_8822C) &                            \
+	 BIT_MASK_HIOE_OP_TIMEOUT_8822C)
+#define BIT_SET_HIOE_OP_TIMEOUT_8822C(x, v)                                    \
+	(BIT_CLEAR_HIOE_OP_TIMEOUT_8822C(x) | BIT_HIOE_OP_TIMEOUT_8822C(v))
+
+#define BIT_SHIFT_BITDATA_CHECKSUM_8822C 0
+#define BIT_MASK_BITDATA_CHECKSUM_8822C 0xffff
+#define BIT_BITDATA_CHECKSUM_8822C(x)                                          \
+	(((x) & BIT_MASK_BITDATA_CHECKSUM_8822C)                               \
+	 << BIT_SHIFT_BITDATA_CHECKSUM_8822C)
+#define BITS_BITDATA_CHECKSUM_8822C                                            \
+	(BIT_MASK_BITDATA_CHECKSUM_8822C << BIT_SHIFT_BITDATA_CHECKSUM_8822C)
+#define BIT_CLEAR_BITDATA_CHECKSUM_8822C(x)                                    \
+	((x) & (~BITS_BITDATA_CHECKSUM_8822C))
+#define BIT_GET_BITDATA_CHECKSUM_8822C(x)                                      \
+	(((x) >> BIT_SHIFT_BITDATA_CHECKSUM_8822C) &                           \
+	 BIT_MASK_BITDATA_CHECKSUM_8822C)
+#define BIT_SET_BITDATA_CHECKSUM_8822C(x, v)                                   \
+	(BIT_CLEAR_BITDATA_CHECKSUM_8822C(x) | BIT_BITDATA_CHECKSUM_8822C(v))
+
+/* 2 REG_HIOE_CFG_FILE_8822C */
+
+#define BIT_SHIFT_TXBF_END_ADDR_8822C 16
+#define BIT_MASK_TXBF_END_ADDR_8822C 0xffff
+#define BIT_TXBF_END_ADDR_8822C(x)                                             \
+	(((x) & BIT_MASK_TXBF_END_ADDR_8822C) << BIT_SHIFT_TXBF_END_ADDR_8822C)
+#define BITS_TXBF_END_ADDR_8822C                                               \
+	(BIT_MASK_TXBF_END_ADDR_8822C << BIT_SHIFT_TXBF_END_ADDR_8822C)
+#define BIT_CLEAR_TXBF_END_ADDR_8822C(x) ((x) & (~BITS_TXBF_END_ADDR_8822C))
+#define BIT_GET_TXBF_END_ADDR_8822C(x)                                         \
+	(((x) >> BIT_SHIFT_TXBF_END_ADDR_8822C) & BIT_MASK_TXBF_END_ADDR_8822C)
+#define BIT_SET_TXBF_END_ADDR_8822C(x, v)                                      \
+	(BIT_CLEAR_TXBF_END_ADDR_8822C(x) | BIT_TXBF_END_ADDR_8822C(v))
+
+#define BIT_SHIFT_TXBF_STR_ADDR_8822C 0
+#define BIT_MASK_TXBF_STR_ADDR_8822C 0xffff
+#define BIT_TXBF_STR_ADDR_8822C(x)                                             \
+	(((x) & BIT_MASK_TXBF_STR_ADDR_8822C) << BIT_SHIFT_TXBF_STR_ADDR_8822C)
+#define BITS_TXBF_STR_ADDR_8822C                                               \
+	(BIT_MASK_TXBF_STR_ADDR_8822C << BIT_SHIFT_TXBF_STR_ADDR_8822C)
+#define BIT_CLEAR_TXBF_STR_ADDR_8822C(x) ((x) & (~BITS_TXBF_STR_ADDR_8822C))
+#define BIT_GET_TXBF_STR_ADDR_8822C(x)                                         \
+	(((x) >> BIT_SHIFT_TXBF_STR_ADDR_8822C) & BIT_MASK_TXBF_STR_ADDR_8822C)
+#define BIT_SET_TXBF_STR_ADDR_8822C(x, v)                                      \
+	(BIT_CLEAR_TXBF_STR_ADDR_8822C(x) | BIT_TXBF_STR_ADDR_8822C(v))
+
+/* 2 REG_TMETER_8822C */
+#define BIT_TEMP_VALID_8822C BIT(31)
+
+#define BIT_SHIFT_TEMP_VALUE_8822C 24
+#define BIT_MASK_TEMP_VALUE_8822C 0x3f
+#define BIT_TEMP_VALUE_8822C(x)                                                \
+	(((x) & BIT_MASK_TEMP_VALUE_8822C) << BIT_SHIFT_TEMP_VALUE_8822C)
+#define BITS_TEMP_VALUE_8822C                                                  \
+	(BIT_MASK_TEMP_VALUE_8822C << BIT_SHIFT_TEMP_VALUE_8822C)
+#define BIT_CLEAR_TEMP_VALUE_8822C(x) ((x) & (~BITS_TEMP_VALUE_8822C))
+#define BIT_GET_TEMP_VALUE_8822C(x)                                            \
+	(((x) >> BIT_SHIFT_TEMP_VALUE_8822C) & BIT_MASK_TEMP_VALUE_8822C)
+#define BIT_SET_TEMP_VALUE_8822C(x, v)                                         \
+	(BIT_CLEAR_TEMP_VALUE_8822C(x) | BIT_TEMP_VALUE_8822C(v))
+
+#define BIT_SHIFT_REG_TMETER_TIMER_8822C 8
+#define BIT_MASK_REG_TMETER_TIMER_8822C 0xfff
+#define BIT_REG_TMETER_TIMER_8822C(x)                                          \
+	(((x) & BIT_MASK_REG_TMETER_TIMER_8822C)                               \
+	 << BIT_SHIFT_REG_TMETER_TIMER_8822C)
+#define BITS_REG_TMETER_TIMER_8822C                                            \
+	(BIT_MASK_REG_TMETER_TIMER_8822C << BIT_SHIFT_REG_TMETER_TIMER_8822C)
+#define BIT_CLEAR_REG_TMETER_TIMER_8822C(x)                                    \
+	((x) & (~BITS_REG_TMETER_TIMER_8822C))
+#define BIT_GET_REG_TMETER_TIMER_8822C(x)                                      \
+	(((x) >> BIT_SHIFT_REG_TMETER_TIMER_8822C) &                           \
+	 BIT_MASK_REG_TMETER_TIMER_8822C)
+#define BIT_SET_REG_TMETER_TIMER_8822C(x, v)                                   \
+	(BIT_CLEAR_REG_TMETER_TIMER_8822C(x) | BIT_REG_TMETER_TIMER_8822C(v))
+
+#define BIT_SHIFT_REG_TEMP_DELTA_8822C 2
+#define BIT_MASK_REG_TEMP_DELTA_8822C 0x3f
+#define BIT_REG_TEMP_DELTA_8822C(x)                                            \
+	(((x) & BIT_MASK_REG_TEMP_DELTA_8822C)                                 \
+	 << BIT_SHIFT_REG_TEMP_DELTA_8822C)
+#define BITS_REG_TEMP_DELTA_8822C                                              \
+	(BIT_MASK_REG_TEMP_DELTA_8822C << BIT_SHIFT_REG_TEMP_DELTA_8822C)
+#define BIT_CLEAR_REG_TEMP_DELTA_8822C(x) ((x) & (~BITS_REG_TEMP_DELTA_8822C))
+#define BIT_GET_REG_TEMP_DELTA_8822C(x)                                        \
+	(((x) >> BIT_SHIFT_REG_TEMP_DELTA_8822C) &                             \
+	 BIT_MASK_REG_TEMP_DELTA_8822C)
+#define BIT_SET_REG_TEMP_DELTA_8822C(x, v)                                     \
+	(BIT_CLEAR_REG_TEMP_DELTA_8822C(x) | BIT_REG_TEMP_DELTA_8822C(v))
+
+#define BIT_REG_TMETER_EN_8822C BIT(0)
+
+/* 2 REG_OSC_32K_CTRL_8822C */
+
+#define BIT_SHIFT_OSC_32K_CLKGEN_0_8822C 16
+#define BIT_MASK_OSC_32K_CLKGEN_0_8822C 0xffff
+#define BIT_OSC_32K_CLKGEN_0_8822C(x)                                          \
+	(((x) & BIT_MASK_OSC_32K_CLKGEN_0_8822C)                               \
+	 << BIT_SHIFT_OSC_32K_CLKGEN_0_8822C)
+#define BITS_OSC_32K_CLKGEN_0_8822C                                            \
+	(BIT_MASK_OSC_32K_CLKGEN_0_8822C << BIT_SHIFT_OSC_32K_CLKGEN_0_8822C)
+#define BIT_CLEAR_OSC_32K_CLKGEN_0_8822C(x)                                    \
+	((x) & (~BITS_OSC_32K_CLKGEN_0_8822C))
+#define BIT_GET_OSC_32K_CLKGEN_0_8822C(x)                                      \
+	(((x) >> BIT_SHIFT_OSC_32K_CLKGEN_0_8822C) &                           \
+	 BIT_MASK_OSC_32K_CLKGEN_0_8822C)
+#define BIT_SET_OSC_32K_CLKGEN_0_8822C(x, v)                                   \
+	(BIT_CLEAR_OSC_32K_CLKGEN_0_8822C(x) | BIT_OSC_32K_CLKGEN_0_8822C(v))
+
+#define BIT_SHIFT_OSC_32K_RES_COMP_8822C 4
+#define BIT_MASK_OSC_32K_RES_COMP_8822C 0x3
+#define BIT_OSC_32K_RES_COMP_8822C(x)                                          \
+	(((x) & BIT_MASK_OSC_32K_RES_COMP_8822C)                               \
+	 << BIT_SHIFT_OSC_32K_RES_COMP_8822C)
+#define BITS_OSC_32K_RES_COMP_8822C                                            \
+	(BIT_MASK_OSC_32K_RES_COMP_8822C << BIT_SHIFT_OSC_32K_RES_COMP_8822C)
+#define BIT_CLEAR_OSC_32K_RES_COMP_8822C(x)                                    \
+	((x) & (~BITS_OSC_32K_RES_COMP_8822C))
+#define BIT_GET_OSC_32K_RES_COMP_8822C(x)                                      \
+	(((x) >> BIT_SHIFT_OSC_32K_RES_COMP_8822C) &                           \
+	 BIT_MASK_OSC_32K_RES_COMP_8822C)
+#define BIT_SET_OSC_32K_RES_COMP_8822C(x, v)                                   \
+	(BIT_CLEAR_OSC_32K_RES_COMP_8822C(x) | BIT_OSC_32K_RES_COMP_8822C(v))
+
+#define BIT_OSC_32K_OUT_SEL_8822C BIT(3)
+#define BIT_ISO_WL_2_OSC_32K_8822C BIT(1)
+#define BIT_POW_CKGEN_8822C BIT(0)
+
+/* 2 REG_32K_CAL_REG1_8822C */
+#define BIT_CAL_32K_REG_WR_8822C BIT(31)
+#define BIT_CAL_32K_DBG_SEL_8822C BIT(22)
+
+#define BIT_SHIFT_CAL_32K_REG_ADDR_8822C 16
+#define BIT_MASK_CAL_32K_REG_ADDR_8822C 0x3f
+#define BIT_CAL_32K_REG_ADDR_8822C(x)                                          \
+	(((x) & BIT_MASK_CAL_32K_REG_ADDR_8822C)                               \
+	 << BIT_SHIFT_CAL_32K_REG_ADDR_8822C)
+#define BITS_CAL_32K_REG_ADDR_8822C                                            \
+	(BIT_MASK_CAL_32K_REG_ADDR_8822C << BIT_SHIFT_CAL_32K_REG_ADDR_8822C)
+#define BIT_CLEAR_CAL_32K_REG_ADDR_8822C(x)                                    \
+	((x) & (~BITS_CAL_32K_REG_ADDR_8822C))
+#define BIT_GET_CAL_32K_REG_ADDR_8822C(x)                                      \
+	(((x) >> BIT_SHIFT_CAL_32K_REG_ADDR_8822C) &                           \
+	 BIT_MASK_CAL_32K_REG_ADDR_8822C)
+#define BIT_SET_CAL_32K_REG_ADDR_8822C(x, v)                                   \
+	(BIT_CLEAR_CAL_32K_REG_ADDR_8822C(x) | BIT_CAL_32K_REG_ADDR_8822C(v))
+
+#define BIT_SHIFT_CAL_32K_REG_DATA_8822C 0
+#define BIT_MASK_CAL_32K_REG_DATA_8822C 0xffff
+#define BIT_CAL_32K_REG_DATA_8822C(x)                                          \
+	(((x) & BIT_MASK_CAL_32K_REG_DATA_8822C)                               \
+	 << BIT_SHIFT_CAL_32K_REG_DATA_8822C)
+#define BITS_CAL_32K_REG_DATA_8822C                                            \
+	(BIT_MASK_CAL_32K_REG_DATA_8822C << BIT_SHIFT_CAL_32K_REG_DATA_8822C)
+#define BIT_CLEAR_CAL_32K_REG_DATA_8822C(x)                                    \
+	((x) & (~BITS_CAL_32K_REG_DATA_8822C))
+#define BIT_GET_CAL_32K_REG_DATA_8822C(x)                                      \
+	(((x) >> BIT_SHIFT_CAL_32K_REG_DATA_8822C) &                           \
+	 BIT_MASK_CAL_32K_REG_DATA_8822C)
+#define BIT_SET_CAL_32K_REG_DATA_8822C(x, v)                                   \
+	(BIT_CLEAR_CAL_32K_REG_DATA_8822C(x) | BIT_CAL_32K_REG_DATA_8822C(v))
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_C2HEVT_8822C */
+
+#define BIT_SHIFT_C2HEVT_MSG_V1_8822C 0
+#define BIT_MASK_C2HEVT_MSG_V1_8822C 0xffffffffL
+#define BIT_C2HEVT_MSG_V1_8822C(x)                                             \
+	(((x) & BIT_MASK_C2HEVT_MSG_V1_8822C) << BIT_SHIFT_C2HEVT_MSG_V1_8822C)
+#define BITS_C2HEVT_MSG_V1_8822C                                               \
+	(BIT_MASK_C2HEVT_MSG_V1_8822C << BIT_SHIFT_C2HEVT_MSG_V1_8822C)
+#define BIT_CLEAR_C2HEVT_MSG_V1_8822C(x) ((x) & (~BITS_C2HEVT_MSG_V1_8822C))
+#define BIT_GET_C2HEVT_MSG_V1_8822C(x)                                         \
+	(((x) >> BIT_SHIFT_C2HEVT_MSG_V1_8822C) & BIT_MASK_C2HEVT_MSG_V1_8822C)
+#define BIT_SET_C2HEVT_MSG_V1_8822C(x, v)                                      \
+	(BIT_CLEAR_C2HEVT_MSG_V1_8822C(x) | BIT_C2HEVT_MSG_V1_8822C(v))
+
+/* 2 REG_C2HEVT_1_8822C */
+
+#define BIT_SHIFT_C2HEVT_MSG_1_8822C 0
+#define BIT_MASK_C2HEVT_MSG_1_8822C 0xffffffffL
+#define BIT_C2HEVT_MSG_1_8822C(x)                                              \
+	(((x) & BIT_MASK_C2HEVT_MSG_1_8822C) << BIT_SHIFT_C2HEVT_MSG_1_8822C)
+#define BITS_C2HEVT_MSG_1_8822C                                                \
+	(BIT_MASK_C2HEVT_MSG_1_8822C << BIT_SHIFT_C2HEVT_MSG_1_8822C)
+#define BIT_CLEAR_C2HEVT_MSG_1_8822C(x) ((x) & (~BITS_C2HEVT_MSG_1_8822C))
+#define BIT_GET_C2HEVT_MSG_1_8822C(x)                                          \
+	(((x) >> BIT_SHIFT_C2HEVT_MSG_1_8822C) & BIT_MASK_C2HEVT_MSG_1_8822C)
+#define BIT_SET_C2HEVT_MSG_1_8822C(x, v)                                       \
+	(BIT_CLEAR_C2HEVT_MSG_1_8822C(x) | BIT_C2HEVT_MSG_1_8822C(v))
+
+/* 2 REG_C2HEVT_2_8822C */
+
+#define BIT_SHIFT_C2HEVT_MSG_2_8822C 0
+#define BIT_MASK_C2HEVT_MSG_2_8822C 0xffffffffL
+#define BIT_C2HEVT_MSG_2_8822C(x)                                              \
+	(((x) & BIT_MASK_C2HEVT_MSG_2_8822C) << BIT_SHIFT_C2HEVT_MSG_2_8822C)
+#define BITS_C2HEVT_MSG_2_8822C                                                \
+	(BIT_MASK_C2HEVT_MSG_2_8822C << BIT_SHIFT_C2HEVT_MSG_2_8822C)
+#define BIT_CLEAR_C2HEVT_MSG_2_8822C(x) ((x) & (~BITS_C2HEVT_MSG_2_8822C))
+#define BIT_GET_C2HEVT_MSG_2_8822C(x)                                          \
+	(((x) >> BIT_SHIFT_C2HEVT_MSG_2_8822C) & BIT_MASK_C2HEVT_MSG_2_8822C)
+#define BIT_SET_C2HEVT_MSG_2_8822C(x, v)                                       \
+	(BIT_CLEAR_C2HEVT_MSG_2_8822C(x) | BIT_C2HEVT_MSG_2_8822C(v))
+
+/* 2 REG_C2HEVT_3_8822C */
+
+#define BIT_SHIFT_C2HEVT_MSG_3_8822C 0
+#define BIT_MASK_C2HEVT_MSG_3_8822C 0xffffffffL
+#define BIT_C2HEVT_MSG_3_8822C(x)                                              \
+	(((x) & BIT_MASK_C2HEVT_MSG_3_8822C) << BIT_SHIFT_C2HEVT_MSG_3_8822C)
+#define BITS_C2HEVT_MSG_3_8822C                                                \
+	(BIT_MASK_C2HEVT_MSG_3_8822C << BIT_SHIFT_C2HEVT_MSG_3_8822C)
+#define BIT_CLEAR_C2HEVT_MSG_3_8822C(x) ((x) & (~BITS_C2HEVT_MSG_3_8822C))
+#define BIT_GET_C2HEVT_MSG_3_8822C(x)                                          \
+	(((x) >> BIT_SHIFT_C2HEVT_MSG_3_8822C) & BIT_MASK_C2HEVT_MSG_3_8822C)
+#define BIT_SET_C2HEVT_MSG_3_8822C(x, v)                                       \
+	(BIT_CLEAR_C2HEVT_MSG_3_8822C(x) | BIT_C2HEVT_MSG_3_8822C(v))
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_SW_DEFINED_PAGE1_8822C */
+
+#define BIT_SHIFT_SW_DEFINED_PAGE1_V1_8822C 0
+#define BIT_MASK_SW_DEFINED_PAGE1_V1_8822C 0xffffffffL
+#define BIT_SW_DEFINED_PAGE1_V1_8822C(x)                                       \
+	(((x) & BIT_MASK_SW_DEFINED_PAGE1_V1_8822C)                            \
+	 << BIT_SHIFT_SW_DEFINED_PAGE1_V1_8822C)
+#define BITS_SW_DEFINED_PAGE1_V1_8822C                                         \
+	(BIT_MASK_SW_DEFINED_PAGE1_V1_8822C                                    \
+	 << BIT_SHIFT_SW_DEFINED_PAGE1_V1_8822C)
+#define BIT_CLEAR_SW_DEFINED_PAGE1_V1_8822C(x)                                 \
+	((x) & (~BITS_SW_DEFINED_PAGE1_V1_8822C))
+#define BIT_GET_SW_DEFINED_PAGE1_V1_8822C(x)                                   \
+	(((x) >> BIT_SHIFT_SW_DEFINED_PAGE1_V1_8822C) &                        \
+	 BIT_MASK_SW_DEFINED_PAGE1_V1_8822C)
+#define BIT_SET_SW_DEFINED_PAGE1_V1_8822C(x, v)                                \
+	(BIT_CLEAR_SW_DEFINED_PAGE1_V1_8822C(x) |                              \
+	 BIT_SW_DEFINED_PAGE1_V1_8822C(v))
+
+/* 2 REG_SW_DEFINED_PAGE2_8822C */
+
+#define BIT_SHIFT_SW_DEFINED_PAGE2_8822C 0
+#define BIT_MASK_SW_DEFINED_PAGE2_8822C 0xffffffffL
+#define BIT_SW_DEFINED_PAGE2_8822C(x)                                          \
+	(((x) & BIT_MASK_SW_DEFINED_PAGE2_8822C)                               \
+	 << BIT_SHIFT_SW_DEFINED_PAGE2_8822C)
+#define BITS_SW_DEFINED_PAGE2_8822C                                            \
+	(BIT_MASK_SW_DEFINED_PAGE2_8822C << BIT_SHIFT_SW_DEFINED_PAGE2_8822C)
+#define BIT_CLEAR_SW_DEFINED_PAGE2_8822C(x)                                    \
+	((x) & (~BITS_SW_DEFINED_PAGE2_8822C))
+#define BIT_GET_SW_DEFINED_PAGE2_8822C(x)                                      \
+	(((x) >> BIT_SHIFT_SW_DEFINED_PAGE2_8822C) &                           \
+	 BIT_MASK_SW_DEFINED_PAGE2_8822C)
+#define BIT_SET_SW_DEFINED_PAGE2_8822C(x, v)                                   \
+	(BIT_CLEAR_SW_DEFINED_PAGE2_8822C(x) | BIT_SW_DEFINED_PAGE2_8822C(v))
+
+/* 2 REG_MCUTST_I_8822C */
+
+#define BIT_SHIFT_MCUDMSG_I_8822C 0
+#define BIT_MASK_MCUDMSG_I_8822C 0xffffffffL
+#define BIT_MCUDMSG_I_8822C(x)                                                 \
+	(((x) & BIT_MASK_MCUDMSG_I_8822C) << BIT_SHIFT_MCUDMSG_I_8822C)
+#define BITS_MCUDMSG_I_8822C                                                   \
+	(BIT_MASK_MCUDMSG_I_8822C << BIT_SHIFT_MCUDMSG_I_8822C)
+#define BIT_CLEAR_MCUDMSG_I_8822C(x) ((x) & (~BITS_MCUDMSG_I_8822C))
+#define BIT_GET_MCUDMSG_I_8822C(x)                                             \
+	(((x) >> BIT_SHIFT_MCUDMSG_I_8822C) & BIT_MASK_MCUDMSG_I_8822C)
+#define BIT_SET_MCUDMSG_I_8822C(x, v)                                          \
+	(BIT_CLEAR_MCUDMSG_I_8822C(x) | BIT_MCUDMSG_I_8822C(v))
+
+/* 2 REG_MCUTST_II_8822C */
+
+#define BIT_SHIFT_MCUDMSG_II_8822C 0
+#define BIT_MASK_MCUDMSG_II_8822C 0xffffffffL
+#define BIT_MCUDMSG_II_8822C(x)                                                \
+	(((x) & BIT_MASK_MCUDMSG_II_8822C) << BIT_SHIFT_MCUDMSG_II_8822C)
+#define BITS_MCUDMSG_II_8822C                                                  \
+	(BIT_MASK_MCUDMSG_II_8822C << BIT_SHIFT_MCUDMSG_II_8822C)
+#define BIT_CLEAR_MCUDMSG_II_8822C(x) ((x) & (~BITS_MCUDMSG_II_8822C))
+#define BIT_GET_MCUDMSG_II_8822C(x)                                            \
+	(((x) >> BIT_SHIFT_MCUDMSG_II_8822C) & BIT_MASK_MCUDMSG_II_8822C)
+#define BIT_SET_MCUDMSG_II_8822C(x, v)                                         \
+	(BIT_CLEAR_MCUDMSG_II_8822C(x) | BIT_MCUDMSG_II_8822C(v))
+
+/* 2 REG_FMETHR_8822C */
+#define BIT_FMSG_INT_8822C BIT(31)
+
+#define BIT_SHIFT_FW_MSG_8822C 0
+#define BIT_MASK_FW_MSG_8822C 0xffffffffL
+#define BIT_FW_MSG_8822C(x)                                                    \
+	(((x) & BIT_MASK_FW_MSG_8822C) << BIT_SHIFT_FW_MSG_8822C)
+#define BITS_FW_MSG_8822C (BIT_MASK_FW_MSG_8822C << BIT_SHIFT_FW_MSG_8822C)
+#define BIT_CLEAR_FW_MSG_8822C(x) ((x) & (~BITS_FW_MSG_8822C))
+#define BIT_GET_FW_MSG_8822C(x)                                                \
+	(((x) >> BIT_SHIFT_FW_MSG_8822C) & BIT_MASK_FW_MSG_8822C)
+#define BIT_SET_FW_MSG_8822C(x, v)                                             \
+	(BIT_CLEAR_FW_MSG_8822C(x) | BIT_FW_MSG_8822C(v))
+
+/* 2 REG_HMETFR_8822C */
+
+#define BIT_SHIFT_HRCV_MSG_8822C 24
+#define BIT_MASK_HRCV_MSG_8822C 0xff
+#define BIT_HRCV_MSG_8822C(x)                                                  \
+	(((x) & BIT_MASK_HRCV_MSG_8822C) << BIT_SHIFT_HRCV_MSG_8822C)
+#define BITS_HRCV_MSG_8822C                                                    \
+	(BIT_MASK_HRCV_MSG_8822C << BIT_SHIFT_HRCV_MSG_8822C)
+#define BIT_CLEAR_HRCV_MSG_8822C(x) ((x) & (~BITS_HRCV_MSG_8822C))
+#define BIT_GET_HRCV_MSG_8822C(x)                                              \
+	(((x) >> BIT_SHIFT_HRCV_MSG_8822C) & BIT_MASK_HRCV_MSG_8822C)
+#define BIT_SET_HRCV_MSG_8822C(x, v)                                           \
+	(BIT_CLEAR_HRCV_MSG_8822C(x) | BIT_HRCV_MSG_8822C(v))
+
+#define BIT_INT_BOX3_8822C BIT(3)
+#define BIT_INT_BOX2_8822C BIT(2)
+#define BIT_INT_BOX1_8822C BIT(1)
+#define BIT_INT_BOX0_8822C BIT(0)
+
+/* 2 REG_HMEBOX0_8822C */
+
+#define BIT_SHIFT_HOST_MSG_0_8822C 0
+#define BIT_MASK_HOST_MSG_0_8822C 0xffffffffL
+#define BIT_HOST_MSG_0_8822C(x)                                                \
+	(((x) & BIT_MASK_HOST_MSG_0_8822C) << BIT_SHIFT_HOST_MSG_0_8822C)
+#define BITS_HOST_MSG_0_8822C                                                  \
+	(BIT_MASK_HOST_MSG_0_8822C << BIT_SHIFT_HOST_MSG_0_8822C)
+#define BIT_CLEAR_HOST_MSG_0_8822C(x) ((x) & (~BITS_HOST_MSG_0_8822C))
+#define BIT_GET_HOST_MSG_0_8822C(x)                                            \
+	(((x) >> BIT_SHIFT_HOST_MSG_0_8822C) & BIT_MASK_HOST_MSG_0_8822C)
+#define BIT_SET_HOST_MSG_0_8822C(x, v)                                         \
+	(BIT_CLEAR_HOST_MSG_0_8822C(x) | BIT_HOST_MSG_0_8822C(v))
+
+/* 2 REG_HMEBOX1_8822C */
+
+#define BIT_SHIFT_HOST_MSG_1_8822C 0
+#define BIT_MASK_HOST_MSG_1_8822C 0xffffffffL
+#define BIT_HOST_MSG_1_8822C(x)                                                \
+	(((x) & BIT_MASK_HOST_MSG_1_8822C) << BIT_SHIFT_HOST_MSG_1_8822C)
+#define BITS_HOST_MSG_1_8822C                                                  \
+	(BIT_MASK_HOST_MSG_1_8822C << BIT_SHIFT_HOST_MSG_1_8822C)
+#define BIT_CLEAR_HOST_MSG_1_8822C(x) ((x) & (~BITS_HOST_MSG_1_8822C))
+#define BIT_GET_HOST_MSG_1_8822C(x)                                            \
+	(((x) >> BIT_SHIFT_HOST_MSG_1_8822C) & BIT_MASK_HOST_MSG_1_8822C)
+#define BIT_SET_HOST_MSG_1_8822C(x, v)                                         \
+	(BIT_CLEAR_HOST_MSG_1_8822C(x) | BIT_HOST_MSG_1_8822C(v))
+
+/* 2 REG_HMEBOX2_8822C */
+
+#define BIT_SHIFT_HOST_MSG_2_8822C 0
+#define BIT_MASK_HOST_MSG_2_8822C 0xffffffffL
+#define BIT_HOST_MSG_2_8822C(x)                                                \
+	(((x) & BIT_MASK_HOST_MSG_2_8822C) << BIT_SHIFT_HOST_MSG_2_8822C)
+#define BITS_HOST_MSG_2_8822C                                                  \
+	(BIT_MASK_HOST_MSG_2_8822C << BIT_SHIFT_HOST_MSG_2_8822C)
+#define BIT_CLEAR_HOST_MSG_2_8822C(x) ((x) & (~BITS_HOST_MSG_2_8822C))
+#define BIT_GET_HOST_MSG_2_8822C(x)                                            \
+	(((x) >> BIT_SHIFT_HOST_MSG_2_8822C) & BIT_MASK_HOST_MSG_2_8822C)
+#define BIT_SET_HOST_MSG_2_8822C(x, v)                                         \
+	(BIT_CLEAR_HOST_MSG_2_8822C(x) | BIT_HOST_MSG_2_8822C(v))
+
+/* 2 REG_HMEBOX3_8822C */
+
+#define BIT_SHIFT_HOST_MSG_3_8822C 0
+#define BIT_MASK_HOST_MSG_3_8822C 0xffffffffL
+#define BIT_HOST_MSG_3_8822C(x)                                                \
+	(((x) & BIT_MASK_HOST_MSG_3_8822C) << BIT_SHIFT_HOST_MSG_3_8822C)
+#define BITS_HOST_MSG_3_8822C                                                  \
+	(BIT_MASK_HOST_MSG_3_8822C << BIT_SHIFT_HOST_MSG_3_8822C)
+#define BIT_CLEAR_HOST_MSG_3_8822C(x) ((x) & (~BITS_HOST_MSG_3_8822C))
+#define BIT_GET_HOST_MSG_3_8822C(x)                                            \
+	(((x) >> BIT_SHIFT_HOST_MSG_3_8822C) & BIT_MASK_HOST_MSG_3_8822C)
+#define BIT_SET_HOST_MSG_3_8822C(x, v)                                         \
+	(BIT_CLEAR_HOST_MSG_3_8822C(x) | BIT_HOST_MSG_3_8822C(v))
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_BB_ACCESS_CTRL_8822C */
+
+#define BIT_SHIFT_BB_WRITE_READ_8822C 30
+#define BIT_MASK_BB_WRITE_READ_8822C 0x3
+#define BIT_BB_WRITE_READ_8822C(x)                                             \
+	(((x) & BIT_MASK_BB_WRITE_READ_8822C) << BIT_SHIFT_BB_WRITE_READ_8822C)
+#define BITS_BB_WRITE_READ_8822C                                               \
+	(BIT_MASK_BB_WRITE_READ_8822C << BIT_SHIFT_BB_WRITE_READ_8822C)
+#define BIT_CLEAR_BB_WRITE_READ_8822C(x) ((x) & (~BITS_BB_WRITE_READ_8822C))
+#define BIT_GET_BB_WRITE_READ_8822C(x)                                         \
+	(((x) >> BIT_SHIFT_BB_WRITE_READ_8822C) & BIT_MASK_BB_WRITE_READ_8822C)
+#define BIT_SET_BB_WRITE_READ_8822C(x, v)                                      \
+	(BIT_CLEAR_BB_WRITE_READ_8822C(x) | BIT_BB_WRITE_READ_8822C(v))
+
+#define BIT_SHIFT_BB_WRITE_EN_8822C 12
+#define BIT_MASK_BB_WRITE_EN_8822C 0xf
+#define BIT_BB_WRITE_EN_8822C(x)                                               \
+	(((x) & BIT_MASK_BB_WRITE_EN_8822C) << BIT_SHIFT_BB_WRITE_EN_8822C)
+#define BITS_BB_WRITE_EN_8822C                                                 \
+	(BIT_MASK_BB_WRITE_EN_8822C << BIT_SHIFT_BB_WRITE_EN_8822C)
+#define BIT_CLEAR_BB_WRITE_EN_8822C(x) ((x) & (~BITS_BB_WRITE_EN_8822C))
+#define BIT_GET_BB_WRITE_EN_8822C(x)                                           \
+	(((x) >> BIT_SHIFT_BB_WRITE_EN_8822C) & BIT_MASK_BB_WRITE_EN_8822C)
+#define BIT_SET_BB_WRITE_EN_8822C(x, v)                                        \
+	(BIT_CLEAR_BB_WRITE_EN_8822C(x) | BIT_BB_WRITE_EN_8822C(v))
+
+#define BIT_SHIFT_BB_ADDR_8822C 2
+#define BIT_MASK_BB_ADDR_8822C 0x1ff
+#define BIT_BB_ADDR_8822C(x)                                                   \
+	(((x) & BIT_MASK_BB_ADDR_8822C) << BIT_SHIFT_BB_ADDR_8822C)
+#define BITS_BB_ADDR_8822C (BIT_MASK_BB_ADDR_8822C << BIT_SHIFT_BB_ADDR_8822C)
+#define BIT_CLEAR_BB_ADDR_8822C(x) ((x) & (~BITS_BB_ADDR_8822C))
+#define BIT_GET_BB_ADDR_8822C(x)                                               \
+	(((x) >> BIT_SHIFT_BB_ADDR_8822C) & BIT_MASK_BB_ADDR_8822C)
+#define BIT_SET_BB_ADDR_8822C(x, v)                                            \
+	(BIT_CLEAR_BB_ADDR_8822C(x) | BIT_BB_ADDR_8822C(v))
+
+#define BIT_BB_ERRACC_8822C BIT(0)
+
+/* 2 REG_BB_ACCESS_DATA_8822C */
+
+#define BIT_SHIFT_BB_DATA_8822C 0
+#define BIT_MASK_BB_DATA_8822C 0xffffffffL
+#define BIT_BB_DATA_8822C(x)                                                   \
+	(((x) & BIT_MASK_BB_DATA_8822C) << BIT_SHIFT_BB_DATA_8822C)
+#define BITS_BB_DATA_8822C (BIT_MASK_BB_DATA_8822C << BIT_SHIFT_BB_DATA_8822C)
+#define BIT_CLEAR_BB_DATA_8822C(x) ((x) & (~BITS_BB_DATA_8822C))
+#define BIT_GET_BB_DATA_8822C(x)                                               \
+	(((x) >> BIT_SHIFT_BB_DATA_8822C) & BIT_MASK_BB_DATA_8822C)
+#define BIT_SET_BB_DATA_8822C(x, v)                                            \
+	(BIT_CLEAR_BB_DATA_8822C(x) | BIT_BB_DATA_8822C(v))
+
+/* 2 REG_HMEBOX_E0_8822C */
+
+#define BIT_SHIFT_HMEBOX_E0_8822C 0
+#define BIT_MASK_HMEBOX_E0_8822C 0xffffffffL
+#define BIT_HMEBOX_E0_8822C(x)                                                 \
+	(((x) & BIT_MASK_HMEBOX_E0_8822C) << BIT_SHIFT_HMEBOX_E0_8822C)
+#define BITS_HMEBOX_E0_8822C                                                   \
+	(BIT_MASK_HMEBOX_E0_8822C << BIT_SHIFT_HMEBOX_E0_8822C)
+#define BIT_CLEAR_HMEBOX_E0_8822C(x) ((x) & (~BITS_HMEBOX_E0_8822C))
+#define BIT_GET_HMEBOX_E0_8822C(x)                                             \
+	(((x) >> BIT_SHIFT_HMEBOX_E0_8822C) & BIT_MASK_HMEBOX_E0_8822C)
+#define BIT_SET_HMEBOX_E0_8822C(x, v)                                          \
+	(BIT_CLEAR_HMEBOX_E0_8822C(x) | BIT_HMEBOX_E0_8822C(v))
+
+/* 2 REG_HMEBOX_E1_8822C */
+
+#define BIT_SHIFT_HMEBOX_E1_8822C 0
+#define BIT_MASK_HMEBOX_E1_8822C 0xffffffffL
+#define BIT_HMEBOX_E1_8822C(x)                                                 \
+	(((x) & BIT_MASK_HMEBOX_E1_8822C) << BIT_SHIFT_HMEBOX_E1_8822C)
+#define BITS_HMEBOX_E1_8822C                                                   \
+	(BIT_MASK_HMEBOX_E1_8822C << BIT_SHIFT_HMEBOX_E1_8822C)
+#define BIT_CLEAR_HMEBOX_E1_8822C(x) ((x) & (~BITS_HMEBOX_E1_8822C))
+#define BIT_GET_HMEBOX_E1_8822C(x)                                             \
+	(((x) >> BIT_SHIFT_HMEBOX_E1_8822C) & BIT_MASK_HMEBOX_E1_8822C)
+#define BIT_SET_HMEBOX_E1_8822C(x, v)                                          \
+	(BIT_CLEAR_HMEBOX_E1_8822C(x) | BIT_HMEBOX_E1_8822C(v))
+
+/* 2 REG_HMEBOX_E2_8822C */
+
+#define BIT_SHIFT_HMEBOX_E2_8822C 0
+#define BIT_MASK_HMEBOX_E2_8822C 0xffffffffL
+#define BIT_HMEBOX_E2_8822C(x)                                                 \
+	(((x) & BIT_MASK_HMEBOX_E2_8822C) << BIT_SHIFT_HMEBOX_E2_8822C)
+#define BITS_HMEBOX_E2_8822C                                                   \
+	(BIT_MASK_HMEBOX_E2_8822C << BIT_SHIFT_HMEBOX_E2_8822C)
+#define BIT_CLEAR_HMEBOX_E2_8822C(x) ((x) & (~BITS_HMEBOX_E2_8822C))
+#define BIT_GET_HMEBOX_E2_8822C(x)                                             \
+	(((x) >> BIT_SHIFT_HMEBOX_E2_8822C) & BIT_MASK_HMEBOX_E2_8822C)
+#define BIT_SET_HMEBOX_E2_8822C(x, v)                                          \
+	(BIT_CLEAR_HMEBOX_E2_8822C(x) | BIT_HMEBOX_E2_8822C(v))
+
+/* 2 REG_HMEBOX_E3_8822C */
+
+#define BIT_SHIFT_HMEBOX_E3_8822C 0
+#define BIT_MASK_HMEBOX_E3_8822C 0xffffffffL
+#define BIT_HMEBOX_E3_8822C(x)                                                 \
+	(((x) & BIT_MASK_HMEBOX_E3_8822C) << BIT_SHIFT_HMEBOX_E3_8822C)
+#define BITS_HMEBOX_E3_8822C                                                   \
+	(BIT_MASK_HMEBOX_E3_8822C << BIT_SHIFT_HMEBOX_E3_8822C)
+#define BIT_CLEAR_HMEBOX_E3_8822C(x) ((x) & (~BITS_HMEBOX_E3_8822C))
+#define BIT_GET_HMEBOX_E3_8822C(x)                                             \
+	(((x) >> BIT_SHIFT_HMEBOX_E3_8822C) & BIT_MASK_HMEBOX_E3_8822C)
+#define BIT_SET_HMEBOX_E3_8822C(x, v)                                          \
+	(BIT_CLEAR_HMEBOX_E3_8822C(x) | BIT_HMEBOX_E3_8822C(v))
+
+/* 2 REG_CR_EXT_8822C */
+
+#define BIT_SHIFT_PHY_REQ_DELAY_8822C 24
+#define BIT_MASK_PHY_REQ_DELAY_8822C 0xf
+#define BIT_PHY_REQ_DELAY_8822C(x)                                             \
+	(((x) & BIT_MASK_PHY_REQ_DELAY_8822C) << BIT_SHIFT_PHY_REQ_DELAY_8822C)
+#define BITS_PHY_REQ_DELAY_8822C                                               \
+	(BIT_MASK_PHY_REQ_DELAY_8822C << BIT_SHIFT_PHY_REQ_DELAY_8822C)
+#define BIT_CLEAR_PHY_REQ_DELAY_8822C(x) ((x) & (~BITS_PHY_REQ_DELAY_8822C))
+#define BIT_GET_PHY_REQ_DELAY_8822C(x)                                         \
+	(((x) >> BIT_SHIFT_PHY_REQ_DELAY_8822C) & BIT_MASK_PHY_REQ_DELAY_8822C)
+#define BIT_SET_PHY_REQ_DELAY_8822C(x, v)                                      \
+	(BIT_CLEAR_PHY_REQ_DELAY_8822C(x) | BIT_PHY_REQ_DELAY_8822C(v))
+
+/* 2 REG_NOT_VALID_8822C */
+#define BIT_SPD_DOWN_8822C BIT(16)
+
+/* 2 REG_NOT_VALID_8822C */
+
+#define BIT_SHIFT_NETYPE4_8822C 4
+#define BIT_MASK_NETYPE4_8822C 0x3
+#define BIT_NETYPE4_8822C(x)                                                   \
+	(((x) & BIT_MASK_NETYPE4_8822C) << BIT_SHIFT_NETYPE4_8822C)
+#define BITS_NETYPE4_8822C (BIT_MASK_NETYPE4_8822C << BIT_SHIFT_NETYPE4_8822C)
+#define BIT_CLEAR_NETYPE4_8822C(x) ((x) & (~BITS_NETYPE4_8822C))
+#define BIT_GET_NETYPE4_8822C(x)                                               \
+	(((x) >> BIT_SHIFT_NETYPE4_8822C) & BIT_MASK_NETYPE4_8822C)
+#define BIT_SET_NETYPE4_8822C(x, v)                                            \
+	(BIT_CLEAR_NETYPE4_8822C(x) | BIT_NETYPE4_8822C(v))
+
+#define BIT_SHIFT_NETYPE3_8822C 2
+#define BIT_MASK_NETYPE3_8822C 0x3
+#define BIT_NETYPE3_8822C(x)                                                   \
+	(((x) & BIT_MASK_NETYPE3_8822C) << BIT_SHIFT_NETYPE3_8822C)
+#define BITS_NETYPE3_8822C (BIT_MASK_NETYPE3_8822C << BIT_SHIFT_NETYPE3_8822C)
+#define BIT_CLEAR_NETYPE3_8822C(x) ((x) & (~BITS_NETYPE3_8822C))
+#define BIT_GET_NETYPE3_8822C(x)                                               \
+	(((x) >> BIT_SHIFT_NETYPE3_8822C) & BIT_MASK_NETYPE3_8822C)
+#define BIT_SET_NETYPE3_8822C(x, v)                                            \
+	(BIT_CLEAR_NETYPE3_8822C(x) | BIT_NETYPE3_8822C(v))
+
+#define BIT_SHIFT_NETYPE2_8822C 0
+#define BIT_MASK_NETYPE2_8822C 0x3
+#define BIT_NETYPE2_8822C(x)                                                   \
+	(((x) & BIT_MASK_NETYPE2_8822C) << BIT_SHIFT_NETYPE2_8822C)
+#define BITS_NETYPE2_8822C (BIT_MASK_NETYPE2_8822C << BIT_SHIFT_NETYPE2_8822C)
+#define BIT_CLEAR_NETYPE2_8822C(x) ((x) & (~BITS_NETYPE2_8822C))
+#define BIT_GET_NETYPE2_8822C(x)                                               \
+	(((x) >> BIT_SHIFT_NETYPE2_8822C) & BIT_MASK_NETYPE2_8822C)
+#define BIT_SET_NETYPE2_8822C(x, v)                                            \
+	(BIT_CLEAR_NETYPE2_8822C(x) | BIT_NETYPE2_8822C(v))
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_FWFF_8822C */
+
+#define BIT_SHIFT_PKTNUM_TH_V1_8822C 24
+#define BIT_MASK_PKTNUM_TH_V1_8822C 0xff
+#define BIT_PKTNUM_TH_V1_8822C(x)                                              \
+	(((x) & BIT_MASK_PKTNUM_TH_V1_8822C) << BIT_SHIFT_PKTNUM_TH_V1_8822C)
+#define BITS_PKTNUM_TH_V1_8822C                                                \
+	(BIT_MASK_PKTNUM_TH_V1_8822C << BIT_SHIFT_PKTNUM_TH_V1_8822C)
+#define BIT_CLEAR_PKTNUM_TH_V1_8822C(x) ((x) & (~BITS_PKTNUM_TH_V1_8822C))
+#define BIT_GET_PKTNUM_TH_V1_8822C(x)                                          \
+	(((x) >> BIT_SHIFT_PKTNUM_TH_V1_8822C) & BIT_MASK_PKTNUM_TH_V1_8822C)
+#define BIT_SET_PKTNUM_TH_V1_8822C(x, v)                                       \
+	(BIT_CLEAR_PKTNUM_TH_V1_8822C(x) | BIT_PKTNUM_TH_V1_8822C(v))
+
+#define BIT_SHIFT_TIMER_TH_8822C 16
+#define BIT_MASK_TIMER_TH_8822C 0xff
+#define BIT_TIMER_TH_8822C(x)                                                  \
+	(((x) & BIT_MASK_TIMER_TH_8822C) << BIT_SHIFT_TIMER_TH_8822C)
+#define BITS_TIMER_TH_8822C                                                    \
+	(BIT_MASK_TIMER_TH_8822C << BIT_SHIFT_TIMER_TH_8822C)
+#define BIT_CLEAR_TIMER_TH_8822C(x) ((x) & (~BITS_TIMER_TH_8822C))
+#define BIT_GET_TIMER_TH_8822C(x)                                              \
+	(((x) >> BIT_SHIFT_TIMER_TH_8822C) & BIT_MASK_TIMER_TH_8822C)
+#define BIT_SET_TIMER_TH_8822C(x, v)                                           \
+	(BIT_CLEAR_TIMER_TH_8822C(x) | BIT_TIMER_TH_8822C(v))
+
+#define BIT_SHIFT_RXPKT1ENADDR_8822C 0
+#define BIT_MASK_RXPKT1ENADDR_8822C 0xffff
+#define BIT_RXPKT1ENADDR_8822C(x)                                              \
+	(((x) & BIT_MASK_RXPKT1ENADDR_8822C) << BIT_SHIFT_RXPKT1ENADDR_8822C)
+#define BITS_RXPKT1ENADDR_8822C                                                \
+	(BIT_MASK_RXPKT1ENADDR_8822C << BIT_SHIFT_RXPKT1ENADDR_8822C)
+#define BIT_CLEAR_RXPKT1ENADDR_8822C(x) ((x) & (~BITS_RXPKT1ENADDR_8822C))
+#define BIT_GET_RXPKT1ENADDR_8822C(x)                                          \
+	(((x) >> BIT_SHIFT_RXPKT1ENADDR_8822C) & BIT_MASK_RXPKT1ENADDR_8822C)
+#define BIT_SET_RXPKT1ENADDR_8822C(x, v)                                       \
+	(BIT_CLEAR_RXPKT1ENADDR_8822C(x) | BIT_RXPKT1ENADDR_8822C(v))
+
+/* 2 REG_RXFF_PTR_V1_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+#define BIT_SHIFT_RXFF0_RDPTR_V2_8822C 0
+#define BIT_MASK_RXFF0_RDPTR_V2_8822C 0x3ffff
+#define BIT_RXFF0_RDPTR_V2_8822C(x)                                            \
+	(((x) & BIT_MASK_RXFF0_RDPTR_V2_8822C)                                 \
+	 << BIT_SHIFT_RXFF0_RDPTR_V2_8822C)
+#define BITS_RXFF0_RDPTR_V2_8822C                                              \
+	(BIT_MASK_RXFF0_RDPTR_V2_8822C << BIT_SHIFT_RXFF0_RDPTR_V2_8822C)
+#define BIT_CLEAR_RXFF0_RDPTR_V2_8822C(x) ((x) & (~BITS_RXFF0_RDPTR_V2_8822C))
+#define BIT_GET_RXFF0_RDPTR_V2_8822C(x)                                        \
+	(((x) >> BIT_SHIFT_RXFF0_RDPTR_V2_8822C) &                             \
+	 BIT_MASK_RXFF0_RDPTR_V2_8822C)
+#define BIT_SET_RXFF0_RDPTR_V2_8822C(x, v)                                     \
+	(BIT_CLEAR_RXFF0_RDPTR_V2_8822C(x) | BIT_RXFF0_RDPTR_V2_8822C(v))
+
+/* 2 REG_RXFF_WTR_V1_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+#define BIT_SHIFT_RXFF0_WTPTR_V2_8822C 0
+#define BIT_MASK_RXFF0_WTPTR_V2_8822C 0x3ffff
+#define BIT_RXFF0_WTPTR_V2_8822C(x)                                            \
+	(((x) & BIT_MASK_RXFF0_WTPTR_V2_8822C)                                 \
+	 << BIT_SHIFT_RXFF0_WTPTR_V2_8822C)
+#define BITS_RXFF0_WTPTR_V2_8822C                                              \
+	(BIT_MASK_RXFF0_WTPTR_V2_8822C << BIT_SHIFT_RXFF0_WTPTR_V2_8822C)
+#define BIT_CLEAR_RXFF0_WTPTR_V2_8822C(x) ((x) & (~BITS_RXFF0_WTPTR_V2_8822C))
+#define BIT_GET_RXFF0_WTPTR_V2_8822C(x)                                        \
+	(((x) >> BIT_SHIFT_RXFF0_WTPTR_V2_8822C) &                             \
+	 BIT_MASK_RXFF0_WTPTR_V2_8822C)
+#define BIT_SET_RXFF0_WTPTR_V2_8822C(x, v)                                     \
+	(BIT_CLEAR_RXFF0_WTPTR_V2_8822C(x) | BIT_RXFF0_WTPTR_V2_8822C(v))
+
+/* 2 REG_FE2IMR_8822C */
+#define BIT__FE4ISR__IND_MSK_8822C BIT(29)
+#define BIT_FS_TXSC_DESC_DONE_INT_EN_8822C BIT(28)
+#define BIT_FS_TXSC_BKDONE_INT_EN_8822C BIT(27)
+#define BIT_FS_TXSC_BEDONE_INT_EN_8822C BIT(26)
+#define BIT_FS_TXSC_VIDONE_INT_EN_8822C BIT(25)
+#define BIT_FS_TXSC_VODONE_INT_EN_8822C BIT(24)
+#define BIT_FS_ATIM_MB7_INT_EN_8822C BIT(23)
+#define BIT_FS_ATIM_MB6_INT_EN_8822C BIT(22)
+#define BIT_FS_ATIM_MB5_INT_EN_8822C BIT(21)
+#define BIT_FS_ATIM_MB4_INT_EN_8822C BIT(20)
+#define BIT_FS_ATIM_MB3_INT_EN_8822C BIT(19)
+#define BIT_FS_ATIM_MB2_INT_EN_8822C BIT(18)
+#define BIT_FS_ATIM_MB1_INT_EN_8822C BIT(17)
+#define BIT_FS_ATIM_MB0_INT_EN_8822C BIT(16)
+#define BIT_FS_TBTT4INT_EN_8822C BIT(11)
+#define BIT_FS_TBTT3INT_EN_8822C BIT(10)
+#define BIT_FS_TBTT2INT_EN_8822C BIT(9)
+#define BIT_FS_TBTT1INT_EN_8822C BIT(8)
+#define BIT_FS_TBTT0_MB7INT_EN_8822C BIT(7)
+#define BIT_FS_TBTT0_MB6INT_EN_8822C BIT(6)
+#define BIT_FS_TBTT0_MB5INT_EN_8822C BIT(5)
+#define BIT_FS_TBTT0_MB4INT_EN_8822C BIT(4)
+#define BIT_FS_TBTT0_MB3INT_EN_8822C BIT(3)
+#define BIT_FS_TBTT0_MB2INT_EN_8822C BIT(2)
+#define BIT_FS_TBTT0_MB1INT_EN_8822C BIT(1)
+#define BIT_FS_TBTT0_INT_EN_8822C BIT(0)
+
+/* 2 REG_FE2ISR_8822C */
+#define BIT__FE4ISR__IND_INT_8822C BIT(29)
+#define BIT_FS_TXSC_DESC_DONE_INT_8822C BIT(28)
+#define BIT_FS_TXSC_BKDONE_INT_8822C BIT(27)
+#define BIT_FS_TXSC_BEDONE_INT_8822C BIT(26)
+#define BIT_FS_TXSC_VIDONE_INT_8822C BIT(25)
+#define BIT_FS_TXSC_VODONE_INT_8822C BIT(24)
+#define BIT_FS_ATIM_MB7_INT_8822C BIT(23)
+#define BIT_FS_ATIM_MB6_INT_8822C BIT(22)
+#define BIT_FS_ATIM_MB5_INT_8822C BIT(21)
+#define BIT_FS_ATIM_MB4_INT_8822C BIT(20)
+#define BIT_FS_ATIM_MB3_INT_8822C BIT(19)
+#define BIT_FS_ATIM_MB2_INT_8822C BIT(18)
+#define BIT_FS_ATIM_MB1_INT_8822C BIT(17)
+#define BIT_FS_ATIM_MB0_INT_8822C BIT(16)
+#define BIT_FS_TBTT4INT_8822C BIT(11)
+#define BIT_FS_TBTT3INT_8822C BIT(10)
+#define BIT_FS_TBTT2INT_8822C BIT(9)
+#define BIT_FS_TBTT1INT_8822C BIT(8)
+#define BIT_FS_TBTT0_MB7INT_8822C BIT(7)
+#define BIT_FS_TBTT0_MB6INT_8822C BIT(6)
+#define BIT_FS_TBTT0_MB5INT_8822C BIT(5)
+#define BIT_FS_TBTT0_MB4INT_8822C BIT(4)
+#define BIT_FS_TBTT0_MB3INT_8822C BIT(3)
+#define BIT_FS_TBTT0_MB2INT_8822C BIT(2)
+#define BIT_FS_TBTT0_MB1INT_8822C BIT(1)
+#define BIT_FS_TBTT0_INT_8822C BIT(0)
+
+/* 2 REG_FE3IMR_8822C */
+#define BIT_FS_CLI3_MTI_BCNIVLEAR_INT__EN_8822C BIT(31)
+#define BIT_FS_CLI2_MTI_BCNIVLEAR_INT__EN_8822C BIT(30)
+#define BIT_FS_CLI1_MTI_BCNIVLEAR_INT__EN_8822C BIT(29)
+#define BIT_FS_CLI0_MTI_BCNIVLEAR_INT__EN_8822C BIT(28)
+#define BIT_FS_BCNDMA4_INT_EN_8822C BIT(27)
+#define BIT_FS_BCNDMA3_INT_EN_8822C BIT(26)
+#define BIT_FS_BCNDMA2_INT_EN_8822C BIT(25)
+#define BIT_FS_BCNDMA1_INT_EN_8822C BIT(24)
+#define BIT_FS_BCNDMA0_MB7_INT_EN_8822C BIT(23)
+#define BIT_FS_BCNDMA0_MB6_INT_EN_8822C BIT(22)
+#define BIT_FS_BCNDMA0_MB5_INT_EN_8822C BIT(21)
+#define BIT_FS_BCNDMA0_MB4_INT_EN_8822C BIT(20)
+#define BIT_FS_BCNDMA0_MB3_INT_EN_8822C BIT(19)
+#define BIT_FS_BCNDMA0_MB2_INT_EN_8822C BIT(18)
+#define BIT_FS_BCNDMA0_MB1_INT_EN_8822C BIT(17)
+#define BIT_FS_BCNDMA0_INT_EN_8822C BIT(16)
+#define BIT_FS_MTI_BCNIVLEAR_INT__EN_8822C BIT(15)
+#define BIT_FS_BCNERLY4_INT_EN_8822C BIT(11)
+#define BIT_FS_BCNERLY3_INT_EN_8822C BIT(10)
+#define BIT_FS_BCNERLY2_INT_EN_8822C BIT(9)
+#define BIT_FS_BCNERLY1_INT_EN_8822C BIT(8)
+#define BIT_FS_BCNERLY0_MB7INT_EN_8822C BIT(7)
+#define BIT_FS_BCNERLY0_MB6INT_EN_8822C BIT(6)
+#define BIT_FS_BCNERLY0_MB5INT_EN_8822C BIT(5)
+#define BIT_FS_BCNERLY0_MB4INT_EN_8822C BIT(4)
+#define BIT_FS_BCNERLY0_MB3INT_EN_8822C BIT(3)
+#define BIT_FS_BCNERLY0_MB2INT_EN_8822C BIT(2)
+#define BIT_FS_BCNERLY0_MB1INT_EN_8822C BIT(1)
+#define BIT_FS_BCNERLY0_INT_EN_8822C BIT(0)
+
+/* 2 REG_FE3ISR_8822C */
+#define BIT_FS_CLI3_MTI_BCNIVLEAR_INT_8822C BIT(31)
+#define BIT_FS_CLI2_MTI_BCNIVLEAR_INT_8822C BIT(30)
+#define BIT_FS_CLI1_MTI_BCNIVLEAR_INT_8822C BIT(29)
+#define BIT_FS_CLI0_MTI_BCNIVLEAR_INT_8822C BIT(28)
+#define BIT_FS_BCNDMA4_INT_8822C BIT(27)
+#define BIT_FS_BCNDMA3_INT_8822C BIT(26)
+#define BIT_FS_BCNDMA2_INT_8822C BIT(25)
+#define BIT_FS_BCNDMA1_INT_8822C BIT(24)
+#define BIT_FS_BCNDMA0_MB7_INT_8822C BIT(23)
+#define BIT_FS_BCNDMA0_MB6_INT_8822C BIT(22)
+#define BIT_FS_BCNDMA0_MB5_INT_8822C BIT(21)
+#define BIT_FS_BCNDMA0_MB4_INT_8822C BIT(20)
+#define BIT_FS_BCNDMA0_MB3_INT_8822C BIT(19)
+#define BIT_FS_BCNDMA0_MB2_INT_8822C BIT(18)
+#define BIT_FS_BCNDMA0_MB1_INT_8822C BIT(17)
+#define BIT_FS_BCNDMA0_INT_8822C BIT(16)
+#define BIT_FS_MTI_BCNIVLEAR_INT_8822C BIT(15)
+#define BIT_FS_BCNERLY4_INT_8822C BIT(11)
+#define BIT_FS_BCNERLY3_INT_8822C BIT(10)
+#define BIT_FS_BCNERLY2_INT_8822C BIT(9)
+#define BIT_FS_BCNERLY1_INT_8822C BIT(8)
+#define BIT_FS_BCNERLY0_MB7INT_8822C BIT(7)
+#define BIT_FS_BCNERLY0_MB6INT_8822C BIT(6)
+#define BIT_FS_BCNERLY0_MB5INT_8822C BIT(5)
+#define BIT_FS_BCNERLY0_MB4INT_8822C BIT(4)
+#define BIT_FS_BCNERLY0_MB3INT_8822C BIT(3)
+#define BIT_FS_BCNERLY0_MB2INT_8822C BIT(2)
+#define BIT_FS_BCNERLY0_MB1INT_8822C BIT(1)
+#define BIT_FS_BCNERLY0_INT_8822C BIT(0)
+
+/* 2 REG_FE4IMR_8822C */
+#define BIT_FS_CLI3_TXPKTIN_INT_EN_8822C BIT(19)
+#define BIT_FS_CLI2_TXPKTIN_INT_EN_8822C BIT(18)
+#define BIT_FS_CLI1_TXPKTIN_INT_EN_8822C BIT(17)
+#define BIT_FS_CLI0_TXPKTIN_INT_EN_8822C BIT(16)
+#define BIT_FS_CLI3_RX_UMD0_INT_EN_8822C BIT(15)
+#define BIT_FS_CLI3_RX_UMD1_INT_EN_8822C BIT(14)
+#define BIT_FS_CLI3_RX_BMD0_INT_EN_8822C BIT(13)
+#define BIT_FS_CLI3_RX_BMD1_INT_EN_8822C BIT(12)
+#define BIT_FS_CLI2_RX_UMD0_INT_EN_8822C BIT(11)
+#define BIT_FS_CLI2_RX_UMD1_INT_EN_8822C BIT(10)
+#define BIT_FS_CLI2_RX_BMD0_INT_EN_8822C BIT(9)
+#define BIT_FS_CLI2_RX_BMD1_INT_EN_8822C BIT(8)
+#define BIT_FS_CLI1_RX_UMD0_INT_EN_8822C BIT(7)
+#define BIT_FS_CLI1_RX_UMD1_INT_EN_8822C BIT(6)
+#define BIT_FS_CLI1_RX_BMD0_INT_EN_8822C BIT(5)
+#define BIT_FS_CLI1_RX_BMD1_INT_EN_8822C BIT(4)
+#define BIT_FS_CLI0_RX_UMD0_INT_EN_8822C BIT(3)
+#define BIT_FS_CLI0_RX_UMD1_INT_EN_8822C BIT(2)
+#define BIT_FS_CLI0_RX_BMD0_INT_EN_8822C BIT(1)
+#define BIT_FS_CLI0_RX_BMD1_INT_EN_8822C BIT(0)
+
+/* 2 REG_FE4ISR_8822C */
+#define BIT_FS_CLI3_TXPKTIN_INT_8822C BIT(19)
+#define BIT_FS_CLI2_TXPKTIN_INT_8822C BIT(18)
+#define BIT_FS_CLI1_TXPKTIN_INT_8822C BIT(17)
+#define BIT_FS_CLI0_TXPKTIN_INT_8822C BIT(16)
+#define BIT_FS_CLI3_RX_UMD0_INT_8822C BIT(15)
+#define BIT_FS_CLI3_RX_UMD1_INT_8822C BIT(14)
+#define BIT_FS_CLI3_RX_BMD0_INT_8822C BIT(13)
+#define BIT_FS_CLI3_RX_BMD1_INT_8822C BIT(12)
+#define BIT_FS_CLI2_RX_UMD0_INT_8822C BIT(11)
+#define BIT_FS_CLI2_RX_UMD1_INT_8822C BIT(10)
+#define BIT_FS_CLI2_RX_BMD0_INT_8822C BIT(9)
+#define BIT_FS_CLI2_RX_BMD1_INT_8822C BIT(8)
+#define BIT_FS_CLI1_RX_UMD0_INT_8822C BIT(7)
+#define BIT_FS_CLI1_RX_UMD1_INT_8822C BIT(6)
+#define BIT_FS_CLI1_RX_BMD0_INT_8822C BIT(5)
+#define BIT_FS_CLI1_RX_BMD1_INT_8822C BIT(4)
+#define BIT_FS_CLI0_RX_UMD0_INT_8822C BIT(3)
+#define BIT_FS_CLI0_RX_UMD1_INT_8822C BIT(2)
+#define BIT_FS_CLI0_RX_BMD0_INT_8822C BIT(1)
+#define BIT_FS_CLI0_RX_BMD1_INT_8822C BIT(0)
+
+/* 2 REG_FT1IMR_8822C */
+#define BIT__FT2ISR__IND_MSK_8822C BIT(30)
+#define BIT_FTM_PTT_INT_EN_8822C BIT(29)
+#define BIT_RXFTMREQ_INT_EN_8822C BIT(28)
+#define BIT_RXFTM_INT_EN_8822C BIT(27)
+#define BIT_TXFTM_INT_EN_8822C BIT(26)
+#define BIT_FS_H2C_CMD_OK_INT_EN_8822C BIT(25)
+#define BIT_FS_H2C_CMD_FULL_INT_EN_8822C BIT(24)
+#define BIT_FS_MACID_PWRCHANGE5_INT_EN_8822C BIT(23)
+#define BIT_FS_MACID_PWRCHANGE4_INT_EN_8822C BIT(22)
+#define BIT_FS_MACID_PWRCHANGE3_INT_EN_8822C BIT(21)
+#define BIT_FS_MACID_PWRCHANGE2_INT_EN_8822C BIT(20)
+#define BIT_FS_MACID_PWRCHANGE1_INT_EN_8822C BIT(19)
+#define BIT_FS_MACID_PWRCHANGE0_INT_EN_8822C BIT(18)
+#define BIT_FS_CTWEND2_INT_EN_8822C BIT(17)
+#define BIT_FS_CTWEND1_INT_EN_8822C BIT(16)
+#define BIT_FS_CTWEND0_INT_EN_8822C BIT(15)
+#define BIT_FS_TX_NULL1_INT_EN_8822C BIT(14)
+#define BIT_FS_TX_NULL0_INT_EN_8822C BIT(13)
+#define BIT_FS_TSF_BIT32_TOGGLE_EN_8822C BIT(12)
+#define BIT_FS_P2P_RFON2_INT_EN_8822C BIT(11)
+#define BIT_FS_P2P_RFOFF2_INT_EN_8822C BIT(10)
+#define BIT_FS_P2P_RFON1_INT_EN_8822C BIT(9)
+#define BIT_FS_P2P_RFOFF1_INT_EN_8822C BIT(8)
+#define BIT_FS_P2P_RFON0_INT_EN_8822C BIT(7)
+#define BIT_FS_P2P_RFOFF0_INT_EN_8822C BIT(6)
+#define BIT_FS_RX_UAPSDMD1_EN_8822C BIT(5)
+#define BIT_FS_RX_UAPSDMD0_EN_8822C BIT(4)
+#define BIT_FS_TRIGGER_PKT_EN_8822C BIT(3)
+#define BIT_FS_EOSP_INT_EN_8822C BIT(2)
+#define BIT_FS_RPWM2_INT_EN_8822C BIT(1)
+#define BIT_FS_RPWM_INT_EN_8822C BIT(0)
+
+/* 2 REG_FT1ISR_8822C */
+#define BIT__FT2ISR__IND_INT_8822C BIT(30)
+#define BIT_FTM_PTT_INT_8822C BIT(29)
+#define BIT_RXFTMREQ_INT_8822C BIT(28)
+#define BIT_RXFTM_INT_8822C BIT(27)
+#define BIT_TXFTM_INT_8822C BIT(26)
+#define BIT_FS_H2C_CMD_OK_INT_8822C BIT(25)
+#define BIT_FS_H2C_CMD_FULL_INT_8822C BIT(24)
+#define BIT_FS_MACID_PWRCHANGE5_INT_8822C BIT(23)
+#define BIT_FS_MACID_PWRCHANGE4_INT_8822C BIT(22)
+#define BIT_FS_MACID_PWRCHANGE3_INT_8822C BIT(21)
+#define BIT_FS_MACID_PWRCHANGE2_INT_8822C BIT(20)
+#define BIT_FS_MACID_PWRCHANGE1_INT_8822C BIT(19)
+#define BIT_FS_MACID_PWRCHANGE0_INT_8822C BIT(18)
+#define BIT_FS_CTWEND2_INT_8822C BIT(17)
+#define BIT_FS_CTWEND1_INT_8822C BIT(16)
+#define BIT_FS_CTWEND0_INT_8822C BIT(15)
+#define BIT_FS_TX_NULL1_INT_8822C BIT(14)
+#define BIT_FS_TX_NULL0_INT_8822C BIT(13)
+#define BIT_FS_TSF_BIT32_TOGGLE_INT_8822C BIT(12)
+#define BIT_FS_P2P_RFON2_INT_8822C BIT(11)
+#define BIT_FS_P2P_RFOFF2_INT_8822C BIT(10)
+#define BIT_FS_P2P_RFON1_INT_8822C BIT(9)
+#define BIT_FS_P2P_RFOFF1_INT_8822C BIT(8)
+#define BIT_FS_P2P_RFON0_INT_8822C BIT(7)
+#define BIT_FS_P2P_RFOFF0_INT_8822C BIT(6)
+#define BIT_FS_RX_UAPSDMD1_INT_8822C BIT(5)
+#define BIT_FS_RX_UAPSDMD0_INT_8822C BIT(4)
+#define BIT_FS_TRIGGER_PKT_INT_8822C BIT(3)
+#define BIT_FS_EOSP_INT_8822C BIT(2)
+#define BIT_FS_RPWM2_INT_8822C BIT(1)
+#define BIT_FS_RPWM_INT_8822C BIT(0)
+
+/* 2 REG_SPWR0_8822C */
+
+#define BIT_SHIFT_MID_31TO0_8822C 0
+#define BIT_MASK_MID_31TO0_8822C 0xffffffffL
+#define BIT_MID_31TO0_8822C(x)                                                 \
+	(((x) & BIT_MASK_MID_31TO0_8822C) << BIT_SHIFT_MID_31TO0_8822C)
+#define BITS_MID_31TO0_8822C                                                   \
+	(BIT_MASK_MID_31TO0_8822C << BIT_SHIFT_MID_31TO0_8822C)
+#define BIT_CLEAR_MID_31TO0_8822C(x) ((x) & (~BITS_MID_31TO0_8822C))
+#define BIT_GET_MID_31TO0_8822C(x)                                             \
+	(((x) >> BIT_SHIFT_MID_31TO0_8822C) & BIT_MASK_MID_31TO0_8822C)
+#define BIT_SET_MID_31TO0_8822C(x, v)                                          \
+	(BIT_CLEAR_MID_31TO0_8822C(x) | BIT_MID_31TO0_8822C(v))
+
+/* 2 REG_SPWR1_8822C */
+
+#define BIT_SHIFT_MID_63TO32_8822C 0
+#define BIT_MASK_MID_63TO32_8822C 0xffffffffL
+#define BIT_MID_63TO32_8822C(x)                                                \
+	(((x) & BIT_MASK_MID_63TO32_8822C) << BIT_SHIFT_MID_63TO32_8822C)
+#define BITS_MID_63TO32_8822C                                                  \
+	(BIT_MASK_MID_63TO32_8822C << BIT_SHIFT_MID_63TO32_8822C)
+#define BIT_CLEAR_MID_63TO32_8822C(x) ((x) & (~BITS_MID_63TO32_8822C))
+#define BIT_GET_MID_63TO32_8822C(x)                                            \
+	(((x) >> BIT_SHIFT_MID_63TO32_8822C) & BIT_MASK_MID_63TO32_8822C)
+#define BIT_SET_MID_63TO32_8822C(x, v)                                         \
+	(BIT_CLEAR_MID_63TO32_8822C(x) | BIT_MID_63TO32_8822C(v))
+
+/* 2 REG_SPWR2_8822C */
+
+#define BIT_SHIFT_MID_95O64_8822C 0
+#define BIT_MASK_MID_95O64_8822C 0xffffffffL
+#define BIT_MID_95O64_8822C(x)                                                 \
+	(((x) & BIT_MASK_MID_95O64_8822C) << BIT_SHIFT_MID_95O64_8822C)
+#define BITS_MID_95O64_8822C                                                   \
+	(BIT_MASK_MID_95O64_8822C << BIT_SHIFT_MID_95O64_8822C)
+#define BIT_CLEAR_MID_95O64_8822C(x) ((x) & (~BITS_MID_95O64_8822C))
+#define BIT_GET_MID_95O64_8822C(x)                                             \
+	(((x) >> BIT_SHIFT_MID_95O64_8822C) & BIT_MASK_MID_95O64_8822C)
+#define BIT_SET_MID_95O64_8822C(x, v)                                          \
+	(BIT_CLEAR_MID_95O64_8822C(x) | BIT_MID_95O64_8822C(v))
+
+/* 2 REG_SPWR3_8822C */
+
+#define BIT_SHIFT_MID_127TO96_8822C 0
+#define BIT_MASK_MID_127TO96_8822C 0xffffffffL
+#define BIT_MID_127TO96_8822C(x)                                               \
+	(((x) & BIT_MASK_MID_127TO96_8822C) << BIT_SHIFT_MID_127TO96_8822C)
+#define BITS_MID_127TO96_8822C                                                 \
+	(BIT_MASK_MID_127TO96_8822C << BIT_SHIFT_MID_127TO96_8822C)
+#define BIT_CLEAR_MID_127TO96_8822C(x) ((x) & (~BITS_MID_127TO96_8822C))
+#define BIT_GET_MID_127TO96_8822C(x)                                           \
+	(((x) >> BIT_SHIFT_MID_127TO96_8822C) & BIT_MASK_MID_127TO96_8822C)
+#define BIT_SET_MID_127TO96_8822C(x, v)                                        \
+	(BIT_CLEAR_MID_127TO96_8822C(x) | BIT_MID_127TO96_8822C(v))
+
+/* 2 REG_POWSEQ_8822C */
+
+#define BIT_SHIFT_SEQNUM_MID_8822C 16
+#define BIT_MASK_SEQNUM_MID_8822C 0xffff
+#define BIT_SEQNUM_MID_8822C(x)                                                \
+	(((x) & BIT_MASK_SEQNUM_MID_8822C) << BIT_SHIFT_SEQNUM_MID_8822C)
+#define BITS_SEQNUM_MID_8822C                                                  \
+	(BIT_MASK_SEQNUM_MID_8822C << BIT_SHIFT_SEQNUM_MID_8822C)
+#define BIT_CLEAR_SEQNUM_MID_8822C(x) ((x) & (~BITS_SEQNUM_MID_8822C))
+#define BIT_GET_SEQNUM_MID_8822C(x)                                            \
+	(((x) >> BIT_SHIFT_SEQNUM_MID_8822C) & BIT_MASK_SEQNUM_MID_8822C)
+#define BIT_SET_SEQNUM_MID_8822C(x, v)                                         \
+	(BIT_CLEAR_SEQNUM_MID_8822C(x) | BIT_SEQNUM_MID_8822C(v))
+
+#define BIT_SHIFT_REF_MID_8822C 0
+#define BIT_MASK_REF_MID_8822C 0x7f
+#define BIT_REF_MID_8822C(x)                                                   \
+	(((x) & BIT_MASK_REF_MID_8822C) << BIT_SHIFT_REF_MID_8822C)
+#define BITS_REF_MID_8822C (BIT_MASK_REF_MID_8822C << BIT_SHIFT_REF_MID_8822C)
+#define BIT_CLEAR_REF_MID_8822C(x) ((x) & (~BITS_REF_MID_8822C))
+#define BIT_GET_REF_MID_8822C(x)                                               \
+	(((x) >> BIT_SHIFT_REF_MID_8822C) & BIT_MASK_REF_MID_8822C)
+#define BIT_SET_REF_MID_8822C(x, v)                                            \
+	(BIT_CLEAR_REF_MID_8822C(x) | BIT_REF_MID_8822C(v))
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_TC7_CTRL_V1_8822C */
+#define BIT_TC7INT_EN_8822C BIT(26)
+#define BIT_TC7MODE_8822C BIT(25)
+#define BIT_TC7EN_8822C BIT(24)
+
+#define BIT_SHIFT_TC7DATA_8822C 0
+#define BIT_MASK_TC7DATA_8822C 0xffffff
+#define BIT_TC7DATA_8822C(x)                                                   \
+	(((x) & BIT_MASK_TC7DATA_8822C) << BIT_SHIFT_TC7DATA_8822C)
+#define BITS_TC7DATA_8822C (BIT_MASK_TC7DATA_8822C << BIT_SHIFT_TC7DATA_8822C)
+#define BIT_CLEAR_TC7DATA_8822C(x) ((x) & (~BITS_TC7DATA_8822C))
+#define BIT_GET_TC7DATA_8822C(x)                                               \
+	(((x) >> BIT_SHIFT_TC7DATA_8822C) & BIT_MASK_TC7DATA_8822C)
+#define BIT_SET_TC7DATA_8822C(x, v)                                            \
+	(BIT_CLEAR_TC7DATA_8822C(x) | BIT_TC7DATA_8822C(v))
+
+/* 2 REG_TC8_CTRL_V1_8822C */
+#define BIT_TC8INT_EN_8822C BIT(26)
+#define BIT_TC8MODE_8822C BIT(25)
+#define BIT_TC8EN_8822C BIT(24)
+
+#define BIT_SHIFT_TC8DATA_8822C 0
+#define BIT_MASK_TC8DATA_8822C 0xffffff
+#define BIT_TC8DATA_8822C(x)                                                   \
+	(((x) & BIT_MASK_TC8DATA_8822C) << BIT_SHIFT_TC8DATA_8822C)
+#define BITS_TC8DATA_8822C (BIT_MASK_TC8DATA_8822C << BIT_SHIFT_TC8DATA_8822C)
+#define BIT_CLEAR_TC8DATA_8822C(x) ((x) & (~BITS_TC8DATA_8822C))
+#define BIT_GET_TC8DATA_8822C(x)                                               \
+	(((x) >> BIT_SHIFT_TC8DATA_8822C) & BIT_MASK_TC8DATA_8822C)
+#define BIT_SET_TC8DATA_8822C(x, v)                                            \
+	(BIT_CLEAR_TC8DATA_8822C(x) | BIT_TC8DATA_8822C(v))
+
+/* 2 REG_RX_BCN_TBTT_ITVL0_8822C */
+
+#define BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT2_8822C 24
+#define BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT2_8822C 0xff
+#define BIT_RX_BCN_TBTT_ITVL_CLIENT2_8822C(x)                                  \
+	(((x) & BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT2_8822C)                       \
+	 << BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT2_8822C)
+#define BITS_RX_BCN_TBTT_ITVL_CLIENT2_8822C                                    \
+	(BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT2_8822C                               \
+	 << BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT2_8822C)
+#define BIT_CLEAR_RX_BCN_TBTT_ITVL_CLIENT2_8822C(x)                            \
+	((x) & (~BITS_RX_BCN_TBTT_ITVL_CLIENT2_8822C))
+#define BIT_GET_RX_BCN_TBTT_ITVL_CLIENT2_8822C(x)                              \
+	(((x) >> BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT2_8822C) &                   \
+	 BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT2_8822C)
+#define BIT_SET_RX_BCN_TBTT_ITVL_CLIENT2_8822C(x, v)                           \
+	(BIT_CLEAR_RX_BCN_TBTT_ITVL_CLIENT2_8822C(x) |                         \
+	 BIT_RX_BCN_TBTT_ITVL_CLIENT2_8822C(v))
+
+#define BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT1_8822C 16
+#define BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT1_8822C 0xff
+#define BIT_RX_BCN_TBTT_ITVL_CLIENT1_8822C(x)                                  \
+	(((x) & BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT1_8822C)                       \
+	 << BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT1_8822C)
+#define BITS_RX_BCN_TBTT_ITVL_CLIENT1_8822C                                    \
+	(BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT1_8822C                               \
+	 << BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT1_8822C)
+#define BIT_CLEAR_RX_BCN_TBTT_ITVL_CLIENT1_8822C(x)                            \
+	((x) & (~BITS_RX_BCN_TBTT_ITVL_CLIENT1_8822C))
+#define BIT_GET_RX_BCN_TBTT_ITVL_CLIENT1_8822C(x)                              \
+	(((x) >> BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT1_8822C) &                   \
+	 BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT1_8822C)
+#define BIT_SET_RX_BCN_TBTT_ITVL_CLIENT1_8822C(x, v)                           \
+	(BIT_CLEAR_RX_BCN_TBTT_ITVL_CLIENT1_8822C(x) |                         \
+	 BIT_RX_BCN_TBTT_ITVL_CLIENT1_8822C(v))
+
+#define BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT0_8822C 8
+#define BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT0_8822C 0xff
+#define BIT_RX_BCN_TBTT_ITVL_CLIENT0_8822C(x)                                  \
+	(((x) & BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT0_8822C)                       \
+	 << BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT0_8822C)
+#define BITS_RX_BCN_TBTT_ITVL_CLIENT0_8822C                                    \
+	(BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT0_8822C                               \
+	 << BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT0_8822C)
+#define BIT_CLEAR_RX_BCN_TBTT_ITVL_CLIENT0_8822C(x)                            \
+	((x) & (~BITS_RX_BCN_TBTT_ITVL_CLIENT0_8822C))
+#define BIT_GET_RX_BCN_TBTT_ITVL_CLIENT0_8822C(x)                              \
+	(((x) >> BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT0_8822C) &                   \
+	 BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT0_8822C)
+#define BIT_SET_RX_BCN_TBTT_ITVL_CLIENT0_8822C(x, v)                           \
+	(BIT_CLEAR_RX_BCN_TBTT_ITVL_CLIENT0_8822C(x) |                         \
+	 BIT_RX_BCN_TBTT_ITVL_CLIENT0_8822C(v))
+
+#define BIT_SHIFT_RX_BCN_TBTT_ITVL_PORT0_8822C 0
+#define BIT_MASK_RX_BCN_TBTT_ITVL_PORT0_8822C 0xff
+#define BIT_RX_BCN_TBTT_ITVL_PORT0_8822C(x)                                    \
+	(((x) & BIT_MASK_RX_BCN_TBTT_ITVL_PORT0_8822C)                         \
+	 << BIT_SHIFT_RX_BCN_TBTT_ITVL_PORT0_8822C)
+#define BITS_RX_BCN_TBTT_ITVL_PORT0_8822C                                      \
+	(BIT_MASK_RX_BCN_TBTT_ITVL_PORT0_8822C                                 \
+	 << BIT_SHIFT_RX_BCN_TBTT_ITVL_PORT0_8822C)
+#define BIT_CLEAR_RX_BCN_TBTT_ITVL_PORT0_8822C(x)                              \
+	((x) & (~BITS_RX_BCN_TBTT_ITVL_PORT0_8822C))
+#define BIT_GET_RX_BCN_TBTT_ITVL_PORT0_8822C(x)                                \
+	(((x) >> BIT_SHIFT_RX_BCN_TBTT_ITVL_PORT0_8822C) &                     \
+	 BIT_MASK_RX_BCN_TBTT_ITVL_PORT0_8822C)
+#define BIT_SET_RX_BCN_TBTT_ITVL_PORT0_8822C(x, v)                             \
+	(BIT_CLEAR_RX_BCN_TBTT_ITVL_PORT0_8822C(x) |                           \
+	 BIT_RX_BCN_TBTT_ITVL_PORT0_8822C(v))
+
+/* 2 REG_RX_BCN_TBTT_ITVL1_8822C */
+
+#define BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT3_8822C 0
+#define BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT3_8822C 0xff
+#define BIT_RX_BCN_TBTT_ITVL_CLIENT3_8822C(x)                                  \
+	(((x) & BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT3_8822C)                       \
+	 << BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT3_8822C)
+#define BITS_RX_BCN_TBTT_ITVL_CLIENT3_8822C                                    \
+	(BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT3_8822C                               \
+	 << BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT3_8822C)
+#define BIT_CLEAR_RX_BCN_TBTT_ITVL_CLIENT3_8822C(x)                            \
+	((x) & (~BITS_RX_BCN_TBTT_ITVL_CLIENT3_8822C))
+#define BIT_GET_RX_BCN_TBTT_ITVL_CLIENT3_8822C(x)                              \
+	(((x) >> BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT3_8822C) &                   \
+	 BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT3_8822C)
+#define BIT_SET_RX_BCN_TBTT_ITVL_CLIENT3_8822C(x, v)                           \
+	(BIT_CLEAR_RX_BCN_TBTT_ITVL_CLIENT3_8822C(x) |                         \
+	 BIT_RX_BCN_TBTT_ITVL_CLIENT3_8822C(v))
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_IO_WRAP_ERR_FLAG_8822C */
+#define BIT_IO_WRAP_ERR_8822C BIT(0)
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_SPEED_SENSOR_8822C */
+#define BIT_DSS_1_RST_N_8822C BIT(31)
+#define BIT_DSS_1_SPEED_EN_8822C BIT(30)
+#define BIT_DSS_1_WIRE_SEL_8822C BIT(29)
+#define BIT_DSS_ENCLK_8822C BIT(28)
+
+#define BIT_SHIFT_DSS_1_RO_SEL_8822C 24
+#define BIT_MASK_DSS_1_RO_SEL_8822C 0x7
+#define BIT_DSS_1_RO_SEL_8822C(x)                                              \
+	(((x) & BIT_MASK_DSS_1_RO_SEL_8822C) << BIT_SHIFT_DSS_1_RO_SEL_8822C)
+#define BITS_DSS_1_RO_SEL_8822C                                                \
+	(BIT_MASK_DSS_1_RO_SEL_8822C << BIT_SHIFT_DSS_1_RO_SEL_8822C)
+#define BIT_CLEAR_DSS_1_RO_SEL_8822C(x) ((x) & (~BITS_DSS_1_RO_SEL_8822C))
+#define BIT_GET_DSS_1_RO_SEL_8822C(x)                                          \
+	(((x) >> BIT_SHIFT_DSS_1_RO_SEL_8822C) & BIT_MASK_DSS_1_RO_SEL_8822C)
+#define BIT_SET_DSS_1_RO_SEL_8822C(x, v)                                       \
+	(BIT_CLEAR_DSS_1_RO_SEL_8822C(x) | BIT_DSS_1_RO_SEL_8822C(v))
+
+#define BIT_SHIFT_DSS_1_DATA_IN_8822C 0
+#define BIT_MASK_DSS_1_DATA_IN_8822C 0xfffff
+#define BIT_DSS_1_DATA_IN_8822C(x)                                             \
+	(((x) & BIT_MASK_DSS_1_DATA_IN_8822C) << BIT_SHIFT_DSS_1_DATA_IN_8822C)
+#define BITS_DSS_1_DATA_IN_8822C                                               \
+	(BIT_MASK_DSS_1_DATA_IN_8822C << BIT_SHIFT_DSS_1_DATA_IN_8822C)
+#define BIT_CLEAR_DSS_1_DATA_IN_8822C(x) ((x) & (~BITS_DSS_1_DATA_IN_8822C))
+#define BIT_GET_DSS_1_DATA_IN_8822C(x)                                         \
+	(((x) >> BIT_SHIFT_DSS_1_DATA_IN_8822C) & BIT_MASK_DSS_1_DATA_IN_8822C)
+#define BIT_SET_DSS_1_DATA_IN_8822C(x, v)                                      \
+	(BIT_CLEAR_DSS_1_DATA_IN_8822C(x) | BIT_DSS_1_DATA_IN_8822C(v))
+
+/* 2 REG_SPEED_SENSOR1_8822C */
+#define BIT_DSS_1_READY_8822C BIT(31)
+#define BIT_DSS_1_WSORT_GO_8822C BIT(30)
+
+#define BIT_SHIFT_DSS_1_COUNT_OUT_8822C 0
+#define BIT_MASK_DSS_1_COUNT_OUT_8822C 0xfffff
+#define BIT_DSS_1_COUNT_OUT_8822C(x)                                           \
+	(((x) & BIT_MASK_DSS_1_COUNT_OUT_8822C)                                \
+	 << BIT_SHIFT_DSS_1_COUNT_OUT_8822C)
+#define BITS_DSS_1_COUNT_OUT_8822C                                             \
+	(BIT_MASK_DSS_1_COUNT_OUT_8822C << BIT_SHIFT_DSS_1_COUNT_OUT_8822C)
+#define BIT_CLEAR_DSS_1_COUNT_OUT_8822C(x) ((x) & (~BITS_DSS_1_COUNT_OUT_8822C))
+#define BIT_GET_DSS_1_COUNT_OUT_8822C(x)                                       \
+	(((x) >> BIT_SHIFT_DSS_1_COUNT_OUT_8822C) &                            \
+	 BIT_MASK_DSS_1_COUNT_OUT_8822C)
+#define BIT_SET_DSS_1_COUNT_OUT_8822C(x, v)                                    \
+	(BIT_CLEAR_DSS_1_COUNT_OUT_8822C(x) | BIT_DSS_1_COUNT_OUT_8822C(v))
+
+/* 2 REG_SPEED_SENSOR2_8822C */
+#define BIT_DSS_2_RST_N_8822C BIT(31)
+#define BIT_DSS_2_SPEED_EN_8822C BIT(30)
+#define BIT_DSS_2_WIRE_SEL_8822C BIT(29)
+#define BIT_DSS_ENCLK_8822C BIT(28)
+
+#define BIT_SHIFT_DSS_2_RO_SEL_8822C 24
+#define BIT_MASK_DSS_2_RO_SEL_8822C 0x7
+#define BIT_DSS_2_RO_SEL_8822C(x)                                              \
+	(((x) & BIT_MASK_DSS_2_RO_SEL_8822C) << BIT_SHIFT_DSS_2_RO_SEL_8822C)
+#define BITS_DSS_2_RO_SEL_8822C                                                \
+	(BIT_MASK_DSS_2_RO_SEL_8822C << BIT_SHIFT_DSS_2_RO_SEL_8822C)
+#define BIT_CLEAR_DSS_2_RO_SEL_8822C(x) ((x) & (~BITS_DSS_2_RO_SEL_8822C))
+#define BIT_GET_DSS_2_RO_SEL_8822C(x)                                          \
+	(((x) >> BIT_SHIFT_DSS_2_RO_SEL_8822C) & BIT_MASK_DSS_2_RO_SEL_8822C)
+#define BIT_SET_DSS_2_RO_SEL_8822C(x, v)                                       \
+	(BIT_CLEAR_DSS_2_RO_SEL_8822C(x) | BIT_DSS_2_RO_SEL_8822C(v))
+
+#define BIT_SHIFT_DSS_2_DATA_IN_8822C 0
+#define BIT_MASK_DSS_2_DATA_IN_8822C 0xfffff
+#define BIT_DSS_2_DATA_IN_8822C(x)                                             \
+	(((x) & BIT_MASK_DSS_2_DATA_IN_8822C) << BIT_SHIFT_DSS_2_DATA_IN_8822C)
+#define BITS_DSS_2_DATA_IN_8822C                                               \
+	(BIT_MASK_DSS_2_DATA_IN_8822C << BIT_SHIFT_DSS_2_DATA_IN_8822C)
+#define BIT_CLEAR_DSS_2_DATA_IN_8822C(x) ((x) & (~BITS_DSS_2_DATA_IN_8822C))
+#define BIT_GET_DSS_2_DATA_IN_8822C(x)                                         \
+	(((x) >> BIT_SHIFT_DSS_2_DATA_IN_8822C) & BIT_MASK_DSS_2_DATA_IN_8822C)
+#define BIT_SET_DSS_2_DATA_IN_8822C(x, v)                                      \
+	(BIT_CLEAR_DSS_2_DATA_IN_8822C(x) | BIT_DSS_2_DATA_IN_8822C(v))
+
+/* 2 REG_SPEED_SENSOR3_8822C */
+#define BIT_DSS_2_READY_8822C BIT(31)
+#define BIT_DSS_2_WSORT_GO_8822C BIT(30)
+
+#define BIT_SHIFT_DSS_2_COUNT_OUT_8822C 0
+#define BIT_MASK_DSS_2_COUNT_OUT_8822C 0xfffff
+#define BIT_DSS_2_COUNT_OUT_8822C(x)                                           \
+	(((x) & BIT_MASK_DSS_2_COUNT_OUT_8822C)                                \
+	 << BIT_SHIFT_DSS_2_COUNT_OUT_8822C)
+#define BITS_DSS_2_COUNT_OUT_8822C                                             \
+	(BIT_MASK_DSS_2_COUNT_OUT_8822C << BIT_SHIFT_DSS_2_COUNT_OUT_8822C)
+#define BIT_CLEAR_DSS_2_COUNT_OUT_8822C(x) ((x) & (~BITS_DSS_2_COUNT_OUT_8822C))
+#define BIT_GET_DSS_2_COUNT_OUT_8822C(x)                                       \
+	(((x) >> BIT_SHIFT_DSS_2_COUNT_OUT_8822C) &                            \
+	 BIT_MASK_DSS_2_COUNT_OUT_8822C)
+#define BIT_SET_DSS_2_COUNT_OUT_8822C(x, v)                                    \
+	(BIT_CLEAR_DSS_2_COUNT_OUT_8822C(x) | BIT_DSS_2_COUNT_OUT_8822C(v))
+
+/* 2 REG_SPEED_SENSOR4_8822C */
+#define BIT_DSS_3_RST_N_8822C BIT(31)
+#define BIT_DSS_3_SPEED_EN_8822C BIT(30)
+#define BIT_DSS_3_WIRE_SEL_8822C BIT(29)
+#define BIT_DSS_ENCLK_8822C BIT(28)
+
+#define BIT_SHIFT_DSS_3_RO_SEL_8822C 24
+#define BIT_MASK_DSS_3_RO_SEL_8822C 0x7
+#define BIT_DSS_3_RO_SEL_8822C(x)                                              \
+	(((x) & BIT_MASK_DSS_3_RO_SEL_8822C) << BIT_SHIFT_DSS_3_RO_SEL_8822C)
+#define BITS_DSS_3_RO_SEL_8822C                                                \
+	(BIT_MASK_DSS_3_RO_SEL_8822C << BIT_SHIFT_DSS_3_RO_SEL_8822C)
+#define BIT_CLEAR_DSS_3_RO_SEL_8822C(x) ((x) & (~BITS_DSS_3_RO_SEL_8822C))
+#define BIT_GET_DSS_3_RO_SEL_8822C(x)                                          \
+	(((x) >> BIT_SHIFT_DSS_3_RO_SEL_8822C) & BIT_MASK_DSS_3_RO_SEL_8822C)
+#define BIT_SET_DSS_3_RO_SEL_8822C(x, v)                                       \
+	(BIT_CLEAR_DSS_3_RO_SEL_8822C(x) | BIT_DSS_3_RO_SEL_8822C(v))
+
+#define BIT_SHIFT_DSS_3_DATA_IN_8822C 0
+#define BIT_MASK_DSS_3_DATA_IN_8822C 0xfffff
+#define BIT_DSS_3_DATA_IN_8822C(x)                                             \
+	(((x) & BIT_MASK_DSS_3_DATA_IN_8822C) << BIT_SHIFT_DSS_3_DATA_IN_8822C)
+#define BITS_DSS_3_DATA_IN_8822C                                               \
+	(BIT_MASK_DSS_3_DATA_IN_8822C << BIT_SHIFT_DSS_3_DATA_IN_8822C)
+#define BIT_CLEAR_DSS_3_DATA_IN_8822C(x) ((x) & (~BITS_DSS_3_DATA_IN_8822C))
+#define BIT_GET_DSS_3_DATA_IN_8822C(x)                                         \
+	(((x) >> BIT_SHIFT_DSS_3_DATA_IN_8822C) & BIT_MASK_DSS_3_DATA_IN_8822C)
+#define BIT_SET_DSS_3_DATA_IN_8822C(x, v)                                      \
+	(BIT_CLEAR_DSS_3_DATA_IN_8822C(x) | BIT_DSS_3_DATA_IN_8822C(v))
+
+/* 2 REG_SPEED_SENSOR5_8822C */
+#define BIT_DSS_3_READY_8822C BIT(31)
+#define BIT_DSS_3_WSORT_GO_8822C BIT(30)
+
+#define BIT_SHIFT_DSS_3_COUNT_OUT_8822C 0
+#define BIT_MASK_DSS_3_COUNT_OUT_8822C 0xfffff
+#define BIT_DSS_3_COUNT_OUT_8822C(x)                                           \
+	(((x) & BIT_MASK_DSS_3_COUNT_OUT_8822C)                                \
+	 << BIT_SHIFT_DSS_3_COUNT_OUT_8822C)
+#define BITS_DSS_3_COUNT_OUT_8822C                                             \
+	(BIT_MASK_DSS_3_COUNT_OUT_8822C << BIT_SHIFT_DSS_3_COUNT_OUT_8822C)
+#define BIT_CLEAR_DSS_3_COUNT_OUT_8822C(x) ((x) & (~BITS_DSS_3_COUNT_OUT_8822C))
+#define BIT_GET_DSS_3_COUNT_OUT_8822C(x)                                       \
+	(((x) >> BIT_SHIFT_DSS_3_COUNT_OUT_8822C) &                            \
+	 BIT_MASK_DSS_3_COUNT_OUT_8822C)
+#define BIT_SET_DSS_3_COUNT_OUT_8822C(x, v)                                    \
+	(BIT_CLEAR_DSS_3_COUNT_OUT_8822C(x) | BIT_DSS_3_COUNT_OUT_8822C(v))
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_COUNTER_CTRL_8822C */
+
+#define BIT_SHIFT_COUNTER_BASE_8822C 16
+#define BIT_MASK_COUNTER_BASE_8822C 0x1fff
+#define BIT_COUNTER_BASE_8822C(x)                                              \
+	(((x) & BIT_MASK_COUNTER_BASE_8822C) << BIT_SHIFT_COUNTER_BASE_8822C)
+#define BITS_COUNTER_BASE_8822C                                                \
+	(BIT_MASK_COUNTER_BASE_8822C << BIT_SHIFT_COUNTER_BASE_8822C)
+#define BIT_CLEAR_COUNTER_BASE_8822C(x) ((x) & (~BITS_COUNTER_BASE_8822C))
+#define BIT_GET_COUNTER_BASE_8822C(x)                                          \
+	(((x) >> BIT_SHIFT_COUNTER_BASE_8822C) & BIT_MASK_COUNTER_BASE_8822C)
+#define BIT_SET_COUNTER_BASE_8822C(x, v)                                       \
+	(BIT_CLEAR_COUNTER_BASE_8822C(x) | BIT_COUNTER_BASE_8822C(v))
+
+#define BIT_EN_RTS_REQ_8822C BIT(9)
+#define BIT_EN_EDCA_REQ_8822C BIT(8)
+#define BIT_EN_PTCL_REQ_8822C BIT(7)
+#define BIT_EN_SCH_REQ_8822C BIT(6)
+#define BIT_USB_COUNT_EN_8822C BIT(5)
+#define BIT_PCIE_COUNT_EN_8822C BIT(4)
+#define BIT_RQPN_COUNT_EN_8822C BIT(3)
+#define BIT_RDE_COUNT_EN_8822C BIT(2)
+#define BIT_TDE_COUNT_EN_8822C BIT(1)
+#define BIT_DISABLE_COUNTER_8822C BIT(0)
+
+/* 2 REG_COUNTER_THRESHOLD_8822C */
+#define BIT_SEL_ALL_MACID_8822C BIT(31)
+
+#define BIT_SHIFT_COUNTER_MACID_8822C 24
+#define BIT_MASK_COUNTER_MACID_8822C 0x7f
+#define BIT_COUNTER_MACID_8822C(x)                                             \
+	(((x) & BIT_MASK_COUNTER_MACID_8822C) << BIT_SHIFT_COUNTER_MACID_8822C)
+#define BITS_COUNTER_MACID_8822C                                               \
+	(BIT_MASK_COUNTER_MACID_8822C << BIT_SHIFT_COUNTER_MACID_8822C)
+#define BIT_CLEAR_COUNTER_MACID_8822C(x) ((x) & (~BITS_COUNTER_MACID_8822C))
+#define BIT_GET_COUNTER_MACID_8822C(x)                                         \
+	(((x) >> BIT_SHIFT_COUNTER_MACID_8822C) & BIT_MASK_COUNTER_MACID_8822C)
+#define BIT_SET_COUNTER_MACID_8822C(x, v)                                      \
+	(BIT_CLEAR_COUNTER_MACID_8822C(x) | BIT_COUNTER_MACID_8822C(v))
+
+#define BIT_SHIFT_AGG_VALUE2_8822C 16
+#define BIT_MASK_AGG_VALUE2_8822C 0x7f
+#define BIT_AGG_VALUE2_8822C(x)                                                \
+	(((x) & BIT_MASK_AGG_VALUE2_8822C) << BIT_SHIFT_AGG_VALUE2_8822C)
+#define BITS_AGG_VALUE2_8822C                                                  \
+	(BIT_MASK_AGG_VALUE2_8822C << BIT_SHIFT_AGG_VALUE2_8822C)
+#define BIT_CLEAR_AGG_VALUE2_8822C(x) ((x) & (~BITS_AGG_VALUE2_8822C))
+#define BIT_GET_AGG_VALUE2_8822C(x)                                            \
+	(((x) >> BIT_SHIFT_AGG_VALUE2_8822C) & BIT_MASK_AGG_VALUE2_8822C)
+#define BIT_SET_AGG_VALUE2_8822C(x, v)                                         \
+	(BIT_CLEAR_AGG_VALUE2_8822C(x) | BIT_AGG_VALUE2_8822C(v))
+
+#define BIT_SHIFT_AGG_VALUE1_8822C 8
+#define BIT_MASK_AGG_VALUE1_8822C 0x7f
+#define BIT_AGG_VALUE1_8822C(x)                                                \
+	(((x) & BIT_MASK_AGG_VALUE1_8822C) << BIT_SHIFT_AGG_VALUE1_8822C)
+#define BITS_AGG_VALUE1_8822C                                                  \
+	(BIT_MASK_AGG_VALUE1_8822C << BIT_SHIFT_AGG_VALUE1_8822C)
+#define BIT_CLEAR_AGG_VALUE1_8822C(x) ((x) & (~BITS_AGG_VALUE1_8822C))
+#define BIT_GET_AGG_VALUE1_8822C(x)                                            \
+	(((x) >> BIT_SHIFT_AGG_VALUE1_8822C) & BIT_MASK_AGG_VALUE1_8822C)
+#define BIT_SET_AGG_VALUE1_8822C(x, v)                                         \
+	(BIT_CLEAR_AGG_VALUE1_8822C(x) | BIT_AGG_VALUE1_8822C(v))
+
+#define BIT_SHIFT_AGG_VALUE0_8822C 0
+#define BIT_MASK_AGG_VALUE0_8822C 0x7f
+#define BIT_AGG_VALUE0_8822C(x)                                                \
+	(((x) & BIT_MASK_AGG_VALUE0_8822C) << BIT_SHIFT_AGG_VALUE0_8822C)
+#define BITS_AGG_VALUE0_8822C                                                  \
+	(BIT_MASK_AGG_VALUE0_8822C << BIT_SHIFT_AGG_VALUE0_8822C)
+#define BIT_CLEAR_AGG_VALUE0_8822C(x) ((x) & (~BITS_AGG_VALUE0_8822C))
+#define BIT_GET_AGG_VALUE0_8822C(x)                                            \
+	(((x) >> BIT_SHIFT_AGG_VALUE0_8822C) & BIT_MASK_AGG_VALUE0_8822C)
+#define BIT_SET_AGG_VALUE0_8822C(x, v)                                         \
+	(BIT_CLEAR_AGG_VALUE0_8822C(x) | BIT_AGG_VALUE0_8822C(v))
+
+/* 2 REG_COUNTER_SET_8822C */
+
+#define BIT_SHIFT_REQUEST_RESET_8822C 16
+#define BIT_MASK_REQUEST_RESET_8822C 0xffff
+#define BIT_REQUEST_RESET_8822C(x)                                             \
+	(((x) & BIT_MASK_REQUEST_RESET_8822C) << BIT_SHIFT_REQUEST_RESET_8822C)
+#define BITS_REQUEST_RESET_8822C                                               \
+	(BIT_MASK_REQUEST_RESET_8822C << BIT_SHIFT_REQUEST_RESET_8822C)
+#define BIT_CLEAR_REQUEST_RESET_8822C(x) ((x) & (~BITS_REQUEST_RESET_8822C))
+#define BIT_GET_REQUEST_RESET_8822C(x)                                         \
+	(((x) >> BIT_SHIFT_REQUEST_RESET_8822C) & BIT_MASK_REQUEST_RESET_8822C)
+#define BIT_SET_REQUEST_RESET_8822C(x, v)                                      \
+	(BIT_CLEAR_REQUEST_RESET_8822C(x) | BIT_REQUEST_RESET_8822C(v))
+
+#define BIT_SHIFT_REQUEST_START_8822C 0
+#define BIT_MASK_REQUEST_START_8822C 0xffff
+#define BIT_REQUEST_START_8822C(x)                                             \
+	(((x) & BIT_MASK_REQUEST_START_8822C) << BIT_SHIFT_REQUEST_START_8822C)
+#define BITS_REQUEST_START_8822C                                               \
+	(BIT_MASK_REQUEST_START_8822C << BIT_SHIFT_REQUEST_START_8822C)
+#define BIT_CLEAR_REQUEST_START_8822C(x) ((x) & (~BITS_REQUEST_START_8822C))
+#define BIT_GET_REQUEST_START_8822C(x)                                         \
+	(((x) >> BIT_SHIFT_REQUEST_START_8822C) & BIT_MASK_REQUEST_START_8822C)
+#define BIT_SET_REQUEST_START_8822C(x, v)                                      \
+	(BIT_CLEAR_REQUEST_START_8822C(x) | BIT_REQUEST_START_8822C(v))
+
+/* 2 REG_COUNTER_OVERFLOW_8822C */
+
+#define BIT_SHIFT_CNT_OVF_REG_8822C 0
+#define BIT_MASK_CNT_OVF_REG_8822C 0xffff
+#define BIT_CNT_OVF_REG_8822C(x)                                               \
+	(((x) & BIT_MASK_CNT_OVF_REG_8822C) << BIT_SHIFT_CNT_OVF_REG_8822C)
+#define BITS_CNT_OVF_REG_8822C                                                 \
+	(BIT_MASK_CNT_OVF_REG_8822C << BIT_SHIFT_CNT_OVF_REG_8822C)
+#define BIT_CLEAR_CNT_OVF_REG_8822C(x) ((x) & (~BITS_CNT_OVF_REG_8822C))
+#define BIT_GET_CNT_OVF_REG_8822C(x)                                           \
+	(((x) >> BIT_SHIFT_CNT_OVF_REG_8822C) & BIT_MASK_CNT_OVF_REG_8822C)
+#define BIT_SET_CNT_OVF_REG_8822C(x, v)                                        \
+	(BIT_CLEAR_CNT_OVF_REG_8822C(x) | BIT_CNT_OVF_REG_8822C(v))
+
+/* 2 REG_TXDMA_LEN_THRESHOLD_8822C */
+
+#define BIT_SHIFT_TDE_LEN_TH1_8822C 16
+#define BIT_MASK_TDE_LEN_TH1_8822C 0xffff
+#define BIT_TDE_LEN_TH1_8822C(x)                                               \
+	(((x) & BIT_MASK_TDE_LEN_TH1_8822C) << BIT_SHIFT_TDE_LEN_TH1_8822C)
+#define BITS_TDE_LEN_TH1_8822C                                                 \
+	(BIT_MASK_TDE_LEN_TH1_8822C << BIT_SHIFT_TDE_LEN_TH1_8822C)
+#define BIT_CLEAR_TDE_LEN_TH1_8822C(x) ((x) & (~BITS_TDE_LEN_TH1_8822C))
+#define BIT_GET_TDE_LEN_TH1_8822C(x)                                           \
+	(((x) >> BIT_SHIFT_TDE_LEN_TH1_8822C) & BIT_MASK_TDE_LEN_TH1_8822C)
+#define BIT_SET_TDE_LEN_TH1_8822C(x, v)                                        \
+	(BIT_CLEAR_TDE_LEN_TH1_8822C(x) | BIT_TDE_LEN_TH1_8822C(v))
+
+#define BIT_SHIFT_TDE_LEN_TH0_8822C 0
+#define BIT_MASK_TDE_LEN_TH0_8822C 0xffff
+#define BIT_TDE_LEN_TH0_8822C(x)                                               \
+	(((x) & BIT_MASK_TDE_LEN_TH0_8822C) << BIT_SHIFT_TDE_LEN_TH0_8822C)
+#define BITS_TDE_LEN_TH0_8822C                                                 \
+	(BIT_MASK_TDE_LEN_TH0_8822C << BIT_SHIFT_TDE_LEN_TH0_8822C)
+#define BIT_CLEAR_TDE_LEN_TH0_8822C(x) ((x) & (~BITS_TDE_LEN_TH0_8822C))
+#define BIT_GET_TDE_LEN_TH0_8822C(x)                                           \
+	(((x) >> BIT_SHIFT_TDE_LEN_TH0_8822C) & BIT_MASK_TDE_LEN_TH0_8822C)
+#define BIT_SET_TDE_LEN_TH0_8822C(x, v)                                        \
+	(BIT_CLEAR_TDE_LEN_TH0_8822C(x) | BIT_TDE_LEN_TH0_8822C(v))
+
+/* 2 REG_RXDMA_LEN_THRESHOLD_8822C */
+
+#define BIT_SHIFT_RDE_LEN_TH1_8822C 16
+#define BIT_MASK_RDE_LEN_TH1_8822C 0xffff
+#define BIT_RDE_LEN_TH1_8822C(x)                                               \
+	(((x) & BIT_MASK_RDE_LEN_TH1_8822C) << BIT_SHIFT_RDE_LEN_TH1_8822C)
+#define BITS_RDE_LEN_TH1_8822C                                                 \
+	(BIT_MASK_RDE_LEN_TH1_8822C << BIT_SHIFT_RDE_LEN_TH1_8822C)
+#define BIT_CLEAR_RDE_LEN_TH1_8822C(x) ((x) & (~BITS_RDE_LEN_TH1_8822C))
+#define BIT_GET_RDE_LEN_TH1_8822C(x)                                           \
+	(((x) >> BIT_SHIFT_RDE_LEN_TH1_8822C) & BIT_MASK_RDE_LEN_TH1_8822C)
+#define BIT_SET_RDE_LEN_TH1_8822C(x, v)                                        \
+	(BIT_CLEAR_RDE_LEN_TH1_8822C(x) | BIT_RDE_LEN_TH1_8822C(v))
+
+#define BIT_SHIFT_RDE_LEN_TH0_8822C 0
+#define BIT_MASK_RDE_LEN_TH0_8822C 0xffff
+#define BIT_RDE_LEN_TH0_8822C(x)                                               \
+	(((x) & BIT_MASK_RDE_LEN_TH0_8822C) << BIT_SHIFT_RDE_LEN_TH0_8822C)
+#define BITS_RDE_LEN_TH0_8822C                                                 \
+	(BIT_MASK_RDE_LEN_TH0_8822C << BIT_SHIFT_RDE_LEN_TH0_8822C)
+#define BIT_CLEAR_RDE_LEN_TH0_8822C(x) ((x) & (~BITS_RDE_LEN_TH0_8822C))
+#define BIT_GET_RDE_LEN_TH0_8822C(x)                                           \
+	(((x) >> BIT_SHIFT_RDE_LEN_TH0_8822C) & BIT_MASK_RDE_LEN_TH0_8822C)
+#define BIT_SET_RDE_LEN_TH0_8822C(x, v)                                        \
+	(BIT_CLEAR_RDE_LEN_TH0_8822C(x) | BIT_RDE_LEN_TH0_8822C(v))
+
+/* 2 REG_PCIE_EXEC_TIME_THRESHOLD_8822C */
+
+#define BIT_SHIFT_COUNT_INT_SEL_8822C 16
+#define BIT_MASK_COUNT_INT_SEL_8822C 0x3
+#define BIT_COUNT_INT_SEL_8822C(x)                                             \
+	(((x) & BIT_MASK_COUNT_INT_SEL_8822C) << BIT_SHIFT_COUNT_INT_SEL_8822C)
+#define BITS_COUNT_INT_SEL_8822C                                               \
+	(BIT_MASK_COUNT_INT_SEL_8822C << BIT_SHIFT_COUNT_INT_SEL_8822C)
+#define BIT_CLEAR_COUNT_INT_SEL_8822C(x) ((x) & (~BITS_COUNT_INT_SEL_8822C))
+#define BIT_GET_COUNT_INT_SEL_8822C(x)                                         \
+	(((x) >> BIT_SHIFT_COUNT_INT_SEL_8822C) & BIT_MASK_COUNT_INT_SEL_8822C)
+#define BIT_SET_COUNT_INT_SEL_8822C(x, v)                                      \
+	(BIT_CLEAR_COUNT_INT_SEL_8822C(x) | BIT_COUNT_INT_SEL_8822C(v))
+
+#define BIT_SHIFT_EXEC_TIME_TH_8822C 0
+#define BIT_MASK_EXEC_TIME_TH_8822C 0xffff
+#define BIT_EXEC_TIME_TH_8822C(x)                                              \
+	(((x) & BIT_MASK_EXEC_TIME_TH_8822C) << BIT_SHIFT_EXEC_TIME_TH_8822C)
+#define BITS_EXEC_TIME_TH_8822C                                                \
+	(BIT_MASK_EXEC_TIME_TH_8822C << BIT_SHIFT_EXEC_TIME_TH_8822C)
+#define BIT_CLEAR_EXEC_TIME_TH_8822C(x) ((x) & (~BITS_EXEC_TIME_TH_8822C))
+#define BIT_GET_EXEC_TIME_TH_8822C(x)                                          \
+	(((x) >> BIT_SHIFT_EXEC_TIME_TH_8822C) & BIT_MASK_EXEC_TIME_TH_8822C)
+#define BIT_SET_EXEC_TIME_TH_8822C(x, v)                                       \
+	(BIT_CLEAR_EXEC_TIME_TH_8822C(x) | BIT_EXEC_TIME_TH_8822C(v))
+
+/* 2 REG_FT2IMR_8822C */
+#define BIT_FS_CLI3_RX_UAPSDMD1_EN_8822C BIT(31)
+#define BIT_FS_CLI3_RX_UAPSDMD0_EN_8822C BIT(30)
+#define BIT_FS_CLI3_TRIGGER_PKT_EN_8822C BIT(29)
+#define BIT_FS_CLI3_EOSP_INT_EN_8822C BIT(28)
+#define BIT_FS_CLI2_RX_UAPSDMD1_EN_8822C BIT(27)
+#define BIT_FS_CLI2_RX_UAPSDMD0_EN_8822C BIT(26)
+#define BIT_FS_CLI2_TRIGGER_PKT_EN_8822C BIT(25)
+#define BIT_FS_CLI2_EOSP_INT_EN_8822C BIT(24)
+#define BIT_FS_CLI1_RX_UAPSDMD1_EN_8822C BIT(23)
+#define BIT_FS_CLI1_RX_UAPSDMD0_EN_8822C BIT(22)
+#define BIT_FS_CLI1_TRIGGER_PKT_EN_8822C BIT(21)
+#define BIT_FS_CLI1_EOSP_INT_EN_8822C BIT(20)
+#define BIT_FS_CLI0_RX_UAPSDMD1_EN_8822C BIT(19)
+#define BIT_FS_CLI0_RX_UAPSDMD0_EN_8822C BIT(18)
+#define BIT_FS_CLI0_TRIGGER_PKT_EN_8822C BIT(17)
+#define BIT_FS_CLI0_EOSP_INT_EN_8822C BIT(16)
+#define BIT_FS_TSF_BIT32_TOGGLE_P2P2_EN_8822C BIT(9)
+#define BIT_FS_TSF_BIT32_TOGGLE_P2P1_EN_8822C BIT(8)
+#define BIT_FS_CLI3_TX_NULL1_INT_EN_8822C BIT(7)
+#define BIT_FS_CLI3_TX_NULL0_INT_EN_8822C BIT(6)
+#define BIT_FS_CLI2_TX_NULL1_INT_EN_8822C BIT(5)
+#define BIT_FS_CLI2_TX_NULL0_INT_EN_8822C BIT(4)
+#define BIT_FS_CLI1_TX_NULL1_INT_EN_8822C BIT(3)
+#define BIT_FS_CLI1_TX_NULL0_INT_EN_8822C BIT(2)
+#define BIT_FS_CLI0_TX_NULL1_INT_EN_8822C BIT(1)
+#define BIT_FS_CLI0_TX_NULL0_INT_EN_8822C BIT(0)
+
+/* 2 REG_FT2ISR_8822C */
+#define BIT_FS_CLI3_RX_UAPSDMD1_INT_8822C BIT(31)
+#define BIT_FS_CLI3_RX_UAPSDMD0_INT_8822C BIT(30)
+#define BIT_FS_CLI3_TRIGGER_PKT_INT_8822C BIT(29)
+#define BIT_FS_CLI3_EOSP_INT_8822C BIT(28)
+#define BIT_FS_CLI2_RX_UAPSDMD1_INT_8822C BIT(27)
+#define BIT_FS_CLI2_RX_UAPSDMD0_INT_8822C BIT(26)
+#define BIT_FS_CLI2_TRIGGER_PKT_INT_8822C BIT(25)
+#define BIT_FS_CLI2_EOSP_INT_8822C BIT(24)
+#define BIT_FS_CLI1_RX_UAPSDMD1_INT_8822C BIT(23)
+#define BIT_FS_CLI1_RX_UAPSDMD0_INT_8822C BIT(22)
+#define BIT_FS_CLI1_TRIGGER_PKT_INT_8822C BIT(21)
+#define BIT_FS_CLI1_EOSP_INT_8822C BIT(20)
+#define BIT_FS_CLI0_RX_UAPSDMD1_INT_8822C BIT(19)
+#define BIT_FS_CLI0_RX_UAPSDMD0_INT_8822C BIT(18)
+#define BIT_FS_CLI0_TRIGGER_PKT_INT_8822C BIT(17)
+#define BIT_FS_CLI0_EOSP_INT_8822C BIT(16)
+#define BIT_FS_TSF_BIT32_TOGGLE_P2P2_INT_8822C BIT(9)
+#define BIT_FS_TSF_BIT32_TOGGLE_P2P1_INT_8822C BIT(8)
+#define BIT_FS_CLI3_TX_NULL1_INT_8822C BIT(7)
+#define BIT_FS_CLI3_TX_NULL0_INT_8822C BIT(6)
+#define BIT_FS_CLI2_TX_NULL1_INT_8822C BIT(5)
+#define BIT_FS_CLI2_TX_NULL0_INT_8822C BIT(4)
+#define BIT_FS_CLI1_TX_NULL1_INT_8822C BIT(3)
+#define BIT_FS_CLI1_TX_NULL0_INT_8822C BIT(2)
+#define BIT_FS_CLI0_TX_NULL1_INT_8822C BIT(1)
+#define BIT_FS_CLI0_TX_NULL0_INT_8822C BIT(0)
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_MSG2_8822C */
+
+#define BIT_SHIFT_FW_MSG2_8822C 0
+#define BIT_MASK_FW_MSG2_8822C 0xffffffffL
+#define BIT_FW_MSG2_8822C(x)                                                   \
+	(((x) & BIT_MASK_FW_MSG2_8822C) << BIT_SHIFT_FW_MSG2_8822C)
+#define BITS_FW_MSG2_8822C (BIT_MASK_FW_MSG2_8822C << BIT_SHIFT_FW_MSG2_8822C)
+#define BIT_CLEAR_FW_MSG2_8822C(x) ((x) & (~BITS_FW_MSG2_8822C))
+#define BIT_GET_FW_MSG2_8822C(x)                                               \
+	(((x) >> BIT_SHIFT_FW_MSG2_8822C) & BIT_MASK_FW_MSG2_8822C)
+#define BIT_SET_FW_MSG2_8822C(x, v)                                            \
+	(BIT_CLEAR_FW_MSG2_8822C(x) | BIT_FW_MSG2_8822C(v))
+
+/* 2 REG_MSG3_8822C */
+
+#define BIT_SHIFT_FW_MSG3_8822C 0
+#define BIT_MASK_FW_MSG3_8822C 0xffffffffL
+#define BIT_FW_MSG3_8822C(x)                                                   \
+	(((x) & BIT_MASK_FW_MSG3_8822C) << BIT_SHIFT_FW_MSG3_8822C)
+#define BITS_FW_MSG3_8822C (BIT_MASK_FW_MSG3_8822C << BIT_SHIFT_FW_MSG3_8822C)
+#define BIT_CLEAR_FW_MSG3_8822C(x) ((x) & (~BITS_FW_MSG3_8822C))
+#define BIT_GET_FW_MSG3_8822C(x)                                               \
+	(((x) >> BIT_SHIFT_FW_MSG3_8822C) & BIT_MASK_FW_MSG3_8822C)
+#define BIT_SET_FW_MSG3_8822C(x, v)                                            \
+	(BIT_CLEAR_FW_MSG3_8822C(x) | BIT_FW_MSG3_8822C(v))
+
+/* 2 REG_MSG4_8822C */
+
+#define BIT_SHIFT_FW_MSG4_8822C 0
+#define BIT_MASK_FW_MSG4_8822C 0xffffffffL
+#define BIT_FW_MSG4_8822C(x)                                                   \
+	(((x) & BIT_MASK_FW_MSG4_8822C) << BIT_SHIFT_FW_MSG4_8822C)
+#define BITS_FW_MSG4_8822C (BIT_MASK_FW_MSG4_8822C << BIT_SHIFT_FW_MSG4_8822C)
+#define BIT_CLEAR_FW_MSG4_8822C(x) ((x) & (~BITS_FW_MSG4_8822C))
+#define BIT_GET_FW_MSG4_8822C(x)                                               \
+	(((x) >> BIT_SHIFT_FW_MSG4_8822C) & BIT_MASK_FW_MSG4_8822C)
+#define BIT_SET_FW_MSG4_8822C(x, v)                                            \
+	(BIT_CLEAR_FW_MSG4_8822C(x) | BIT_FW_MSG4_8822C(v))
+
+/* 2 REG_MSG5_8822C */
+
+#define BIT_SHIFT_FW_MSG5_8822C 0
+#define BIT_MASK_FW_MSG5_8822C 0xffffffffL
+#define BIT_FW_MSG5_8822C(x)                                                   \
+	(((x) & BIT_MASK_FW_MSG5_8822C) << BIT_SHIFT_FW_MSG5_8822C)
+#define BITS_FW_MSG5_8822C (BIT_MASK_FW_MSG5_8822C << BIT_SHIFT_FW_MSG5_8822C)
+#define BIT_CLEAR_FW_MSG5_8822C(x) ((x) & (~BITS_FW_MSG5_8822C))
+#define BIT_GET_FW_MSG5_8822C(x)                                               \
+	(((x) >> BIT_SHIFT_FW_MSG5_8822C) & BIT_MASK_FW_MSG5_8822C)
+#define BIT_SET_FW_MSG5_8822C(x, v)                                            \
+	(BIT_CLEAR_FW_MSG5_8822C(x) | BIT_FW_MSG5_8822C(v))
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_FIFOPAGE_CTRL_1_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+#define BIT_SHIFT_TX_OQT_HE_FREE_SPACE_V1_8822C 16
+#define BIT_MASK_TX_OQT_HE_FREE_SPACE_V1_8822C 0xff
+#define BIT_TX_OQT_HE_FREE_SPACE_V1_8822C(x)                                   \
+	(((x) & BIT_MASK_TX_OQT_HE_FREE_SPACE_V1_8822C)                        \
+	 << BIT_SHIFT_TX_OQT_HE_FREE_SPACE_V1_8822C)
+#define BITS_TX_OQT_HE_FREE_SPACE_V1_8822C                                     \
+	(BIT_MASK_TX_OQT_HE_FREE_SPACE_V1_8822C                                \
+	 << BIT_SHIFT_TX_OQT_HE_FREE_SPACE_V1_8822C)
+#define BIT_CLEAR_TX_OQT_HE_FREE_SPACE_V1_8822C(x)                             \
+	((x) & (~BITS_TX_OQT_HE_FREE_SPACE_V1_8822C))
+#define BIT_GET_TX_OQT_HE_FREE_SPACE_V1_8822C(x)                               \
+	(((x) >> BIT_SHIFT_TX_OQT_HE_FREE_SPACE_V1_8822C) &                    \
+	 BIT_MASK_TX_OQT_HE_FREE_SPACE_V1_8822C)
+#define BIT_SET_TX_OQT_HE_FREE_SPACE_V1_8822C(x, v)                            \
+	(BIT_CLEAR_TX_OQT_HE_FREE_SPACE_V1_8822C(x) |                          \
+	 BIT_TX_OQT_HE_FREE_SPACE_V1_8822C(v))
+
+/* 2 REG_NOT_VALID_8822C */
+
+#define BIT_SHIFT_TX_OQT_NL_FREE_SPACE_V1_8822C 0
+#define BIT_MASK_TX_OQT_NL_FREE_SPACE_V1_8822C 0xff
+#define BIT_TX_OQT_NL_FREE_SPACE_V1_8822C(x)                                   \
+	(((x) & BIT_MASK_TX_OQT_NL_FREE_SPACE_V1_8822C)                        \
+	 << BIT_SHIFT_TX_OQT_NL_FREE_SPACE_V1_8822C)
+#define BITS_TX_OQT_NL_FREE_SPACE_V1_8822C                                     \
+	(BIT_MASK_TX_OQT_NL_FREE_SPACE_V1_8822C                                \
+	 << BIT_SHIFT_TX_OQT_NL_FREE_SPACE_V1_8822C)
+#define BIT_CLEAR_TX_OQT_NL_FREE_SPACE_V1_8822C(x)                             \
+	((x) & (~BITS_TX_OQT_NL_FREE_SPACE_V1_8822C))
+#define BIT_GET_TX_OQT_NL_FREE_SPACE_V1_8822C(x)                               \
+	(((x) >> BIT_SHIFT_TX_OQT_NL_FREE_SPACE_V1_8822C) &                    \
+	 BIT_MASK_TX_OQT_NL_FREE_SPACE_V1_8822C)
+#define BIT_SET_TX_OQT_NL_FREE_SPACE_V1_8822C(x, v)                            \
+	(BIT_CLEAR_TX_OQT_NL_FREE_SPACE_V1_8822C(x) |                          \
+	 BIT_TX_OQT_NL_FREE_SPACE_V1_8822C(v))
+
+/* 2 REG_FIFOPAGE_CTRL_2_8822C */
+#define BIT_BCN_VALID_1_V1_8822C BIT(31)
+
+/* 2 REG_NOT_VALID_8822C */
+
+#define BIT_SHIFT_BCN_HEAD_1_V1_8822C 16
+#define BIT_MASK_BCN_HEAD_1_V1_8822C 0xfff
+#define BIT_BCN_HEAD_1_V1_8822C(x)                                             \
+	(((x) & BIT_MASK_BCN_HEAD_1_V1_8822C) << BIT_SHIFT_BCN_HEAD_1_V1_8822C)
+#define BITS_BCN_HEAD_1_V1_8822C                                               \
+	(BIT_MASK_BCN_HEAD_1_V1_8822C << BIT_SHIFT_BCN_HEAD_1_V1_8822C)
+#define BIT_CLEAR_BCN_HEAD_1_V1_8822C(x) ((x) & (~BITS_BCN_HEAD_1_V1_8822C))
+#define BIT_GET_BCN_HEAD_1_V1_8822C(x)                                         \
+	(((x) >> BIT_SHIFT_BCN_HEAD_1_V1_8822C) & BIT_MASK_BCN_HEAD_1_V1_8822C)
+#define BIT_SET_BCN_HEAD_1_V1_8822C(x, v)                                      \
+	(BIT_CLEAR_BCN_HEAD_1_V1_8822C(x) | BIT_BCN_HEAD_1_V1_8822C(v))
+
+#define BIT_BCN_VALID_V1_8822C BIT(15)
+
+/* 2 REG_NOT_VALID_8822C */
+
+#define BIT_SHIFT_BCN_HEAD_V1_8822C 0
+#define BIT_MASK_BCN_HEAD_V1_8822C 0xfff
+#define BIT_BCN_HEAD_V1_8822C(x)                                               \
+	(((x) & BIT_MASK_BCN_HEAD_V1_8822C) << BIT_SHIFT_BCN_HEAD_V1_8822C)
+#define BITS_BCN_HEAD_V1_8822C                                                 \
+	(BIT_MASK_BCN_HEAD_V1_8822C << BIT_SHIFT_BCN_HEAD_V1_8822C)
+#define BIT_CLEAR_BCN_HEAD_V1_8822C(x) ((x) & (~BITS_BCN_HEAD_V1_8822C))
+#define BIT_GET_BCN_HEAD_V1_8822C(x)                                           \
+	(((x) >> BIT_SHIFT_BCN_HEAD_V1_8822C) & BIT_MASK_BCN_HEAD_V1_8822C)
+#define BIT_SET_BCN_HEAD_V1_8822C(x, v)                                        \
+	(BIT_CLEAR_BCN_HEAD_V1_8822C(x) | BIT_BCN_HEAD_V1_8822C(v))
+
+/* 2 REG_AUTO_LLT_V1_8822C */
+
+#define BIT_SHIFT_MAX_TX_PKT_V1_8822C 24
+#define BIT_MASK_MAX_TX_PKT_V1_8822C 0xff
+#define BIT_MAX_TX_PKT_V1_8822C(x)                                             \
+	(((x) & BIT_MASK_MAX_TX_PKT_V1_8822C) << BIT_SHIFT_MAX_TX_PKT_V1_8822C)
+#define BITS_MAX_TX_PKT_V1_8822C                                               \
+	(BIT_MASK_MAX_TX_PKT_V1_8822C << BIT_SHIFT_MAX_TX_PKT_V1_8822C)
+#define BIT_CLEAR_MAX_TX_PKT_V1_8822C(x) ((x) & (~BITS_MAX_TX_PKT_V1_8822C))
+#define BIT_GET_MAX_TX_PKT_V1_8822C(x)                                         \
+	(((x) >> BIT_SHIFT_MAX_TX_PKT_V1_8822C) & BIT_MASK_MAX_TX_PKT_V1_8822C)
+#define BIT_SET_MAX_TX_PKT_V1_8822C(x, v)                                      \
+	(BIT_CLEAR_MAX_TX_PKT_V1_8822C(x) | BIT_MAX_TX_PKT_V1_8822C(v))
+
+#define BIT_TDE_ERROR_STOP_V1_8822C BIT(23)
+
+/* 2 REG_NOT_VALID_8822C */
+
+#define BIT_SHIFT_LLT_FREE_PAGE_V2_8822C 8
+#define BIT_MASK_LLT_FREE_PAGE_V2_8822C 0xfff
+#define BIT_LLT_FREE_PAGE_V2_8822C(x)                                          \
+	(((x) & BIT_MASK_LLT_FREE_PAGE_V2_8822C)                               \
+	 << BIT_SHIFT_LLT_FREE_PAGE_V2_8822C)
+#define BITS_LLT_FREE_PAGE_V2_8822C                                            \
+	(BIT_MASK_LLT_FREE_PAGE_V2_8822C << BIT_SHIFT_LLT_FREE_PAGE_V2_8822C)
+#define BIT_CLEAR_LLT_FREE_PAGE_V2_8822C(x)                                    \
+	((x) & (~BITS_LLT_FREE_PAGE_V2_8822C))
+#define BIT_GET_LLT_FREE_PAGE_V2_8822C(x)                                      \
+	(((x) >> BIT_SHIFT_LLT_FREE_PAGE_V2_8822C) &                           \
+	 BIT_MASK_LLT_FREE_PAGE_V2_8822C)
+#define BIT_SET_LLT_FREE_PAGE_V2_8822C(x, v)                                   \
+	(BIT_CLEAR_LLT_FREE_PAGE_V2_8822C(x) | BIT_LLT_FREE_PAGE_V2_8822C(v))
+
+#define BIT_SHIFT_BLK_DESC_NUM_8822C 4
+#define BIT_MASK_BLK_DESC_NUM_8822C 0xf
+#define BIT_BLK_DESC_NUM_8822C(x)                                              \
+	(((x) & BIT_MASK_BLK_DESC_NUM_8822C) << BIT_SHIFT_BLK_DESC_NUM_8822C)
+#define BITS_BLK_DESC_NUM_8822C                                                \
+	(BIT_MASK_BLK_DESC_NUM_8822C << BIT_SHIFT_BLK_DESC_NUM_8822C)
+#define BIT_CLEAR_BLK_DESC_NUM_8822C(x) ((x) & (~BITS_BLK_DESC_NUM_8822C))
+#define BIT_GET_BLK_DESC_NUM_8822C(x)                                          \
+	(((x) >> BIT_SHIFT_BLK_DESC_NUM_8822C) & BIT_MASK_BLK_DESC_NUM_8822C)
+#define BIT_SET_BLK_DESC_NUM_8822C(x, v)                                       \
+	(BIT_CLEAR_BLK_DESC_NUM_8822C(x) | BIT_BLK_DESC_NUM_8822C(v))
+
+#define BIT_R_BCN_HEAD_SEL_8822C BIT(3)
+#define BIT_R_EN_BCN_SW_HEAD_SEL_8822C BIT(2)
+#define BIT_LLT_DBG_SEL_8822C BIT(1)
+#define BIT_AUTO_INIT_LLT_V1_8822C BIT(0)
+
+/* 2 REG_TXDMA_OFFSET_CHK_8822C */
+#define BIT_EM_CHKSUM_FIN_8822C BIT(31)
+#define BIT_EMN_PCIE_DMA_MOD_8822C BIT(30)
+#define BIT_EN_TXQUE_CLR_8822C BIT(29)
+#define BIT_EN_PCIE_FIFO_MODE_8822C BIT(28)
+
+#define BIT_SHIFT_PG_UNDER_TH_V1_8822C 16
+#define BIT_MASK_PG_UNDER_TH_V1_8822C 0xfff
+#define BIT_PG_UNDER_TH_V1_8822C(x)                                            \
+	(((x) & BIT_MASK_PG_UNDER_TH_V1_8822C)                                 \
+	 << BIT_SHIFT_PG_UNDER_TH_V1_8822C)
+#define BITS_PG_UNDER_TH_V1_8822C                                              \
+	(BIT_MASK_PG_UNDER_TH_V1_8822C << BIT_SHIFT_PG_UNDER_TH_V1_8822C)
+#define BIT_CLEAR_PG_UNDER_TH_V1_8822C(x) ((x) & (~BITS_PG_UNDER_TH_V1_8822C))
+#define BIT_GET_PG_UNDER_TH_V1_8822C(x)                                        \
+	(((x) >> BIT_SHIFT_PG_UNDER_TH_V1_8822C) &                             \
+	 BIT_MASK_PG_UNDER_TH_V1_8822C)
+#define BIT_SET_PG_UNDER_TH_V1_8822C(x, v)                                     \
+	(BIT_CLEAR_PG_UNDER_TH_V1_8822C(x) | BIT_PG_UNDER_TH_V1_8822C(v))
+
+#define BIT_R_EN_RESET_RESTORE_H2C_8822C BIT(15)
+#define BIT_SDIO_TDE_FINISH_8822C BIT(14)
+#define BIT_SDIO_TXDESC_CHKSUM_EN_8822C BIT(13)
+#define BIT_RST_RDPTR_8822C BIT(12)
+#define BIT_RST_WRPTR_8822C BIT(11)
+#define BIT_CHK_PG_TH_EN_8822C BIT(10)
+#define BIT_DROP_DATA_EN_8822C BIT(9)
+#define BIT_CHECK_OFFSET_EN_8822C BIT(8)
+
+#define BIT_SHIFT_CHECK_OFFSET_8822C 0
+#define BIT_MASK_CHECK_OFFSET_8822C 0xff
+#define BIT_CHECK_OFFSET_8822C(x)                                              \
+	(((x) & BIT_MASK_CHECK_OFFSET_8822C) << BIT_SHIFT_CHECK_OFFSET_8822C)
+#define BITS_CHECK_OFFSET_8822C                                                \
+	(BIT_MASK_CHECK_OFFSET_8822C << BIT_SHIFT_CHECK_OFFSET_8822C)
+#define BIT_CLEAR_CHECK_OFFSET_8822C(x) ((x) & (~BITS_CHECK_OFFSET_8822C))
+#define BIT_GET_CHECK_OFFSET_8822C(x)                                          \
+	(((x) >> BIT_SHIFT_CHECK_OFFSET_8822C) & BIT_MASK_CHECK_OFFSET_8822C)
+#define BIT_SET_CHECK_OFFSET_8822C(x, v)                                       \
+	(BIT_CLEAR_CHECK_OFFSET_8822C(x) | BIT_CHECK_OFFSET_8822C(v))
+
+/* 2 REG_TXDMA_STATUS_8822C */
+#define BIT_TXPKTBUF_REQ_ERR_8822C BIT(18)
+#define BIT_HI_OQT_UDN_8822C BIT(17)
+#define BIT_HI_OQT_OVF_8822C BIT(16)
+#define BIT_PAYLOAD_CHKSUM_ERR_8822C BIT(15)
+#define BIT_PAYLOAD_UDN_8822C BIT(14)
+#define BIT_PAYLOAD_OVF_8822C BIT(13)
+#define BIT_DSC_CHKSUM_FAIL_8822C BIT(12)
+#define BIT_UNKNOWN_QSEL_8822C BIT(11)
+#define BIT_EP_QSEL_DIFF_8822C BIT(10)
+#define BIT_TX_OFFS_UNMATCH_8822C BIT(9)
+#define BIT_TXOQT_UDN_8822C BIT(8)
+#define BIT_TXOQT_OVF_8822C BIT(7)
+#define BIT_TXDMA_SFF_UDN_8822C BIT(6)
+#define BIT_TXDMA_SFF_OVF_8822C BIT(5)
+#define BIT_LLT_NULL_PG_8822C BIT(4)
+#define BIT_PAGE_UDN_8822C BIT(3)
+#define BIT_PAGE_OVF_8822C BIT(2)
+#define BIT_TXFF_PG_UDN_8822C BIT(1)
+#define BIT_TXFF_PG_OVF_8822C BIT(0)
+
+/* 2 REG_TX_DMA_DBG_8822C */
+
+/* 2 REG_TQPNT1_8822C */
+#define BIT_HPQ_INT_EN_8822C BIT(31)
+
+#define BIT_SHIFT_HPQ_HIGH_TH_V1_8822C 16
+#define BIT_MASK_HPQ_HIGH_TH_V1_8822C 0xfff
+#define BIT_HPQ_HIGH_TH_V1_8822C(x)                                            \
+	(((x) & BIT_MASK_HPQ_HIGH_TH_V1_8822C)                                 \
+	 << BIT_SHIFT_HPQ_HIGH_TH_V1_8822C)
+#define BITS_HPQ_HIGH_TH_V1_8822C                                              \
+	(BIT_MASK_HPQ_HIGH_TH_V1_8822C << BIT_SHIFT_HPQ_HIGH_TH_V1_8822C)
+#define BIT_CLEAR_HPQ_HIGH_TH_V1_8822C(x) ((x) & (~BITS_HPQ_HIGH_TH_V1_8822C))
+#define BIT_GET_HPQ_HIGH_TH_V1_8822C(x)                                        \
+	(((x) >> BIT_SHIFT_HPQ_HIGH_TH_V1_8822C) &                             \
+	 BIT_MASK_HPQ_HIGH_TH_V1_8822C)
+#define BIT_SET_HPQ_HIGH_TH_V1_8822C(x, v)                                     \
+	(BIT_CLEAR_HPQ_HIGH_TH_V1_8822C(x) | BIT_HPQ_HIGH_TH_V1_8822C(v))
+
+#define BIT_SHIFT_HPQ_LOW_TH_V1_8822C 0
+#define BIT_MASK_HPQ_LOW_TH_V1_8822C 0xfff
+#define BIT_HPQ_LOW_TH_V1_8822C(x)                                             \
+	(((x) & BIT_MASK_HPQ_LOW_TH_V1_8822C) << BIT_SHIFT_HPQ_LOW_TH_V1_8822C)
+#define BITS_HPQ_LOW_TH_V1_8822C                                               \
+	(BIT_MASK_HPQ_LOW_TH_V1_8822C << BIT_SHIFT_HPQ_LOW_TH_V1_8822C)
+#define BIT_CLEAR_HPQ_LOW_TH_V1_8822C(x) ((x) & (~BITS_HPQ_LOW_TH_V1_8822C))
+#define BIT_GET_HPQ_LOW_TH_V1_8822C(x)                                         \
+	(((x) >> BIT_SHIFT_HPQ_LOW_TH_V1_8822C) & BIT_MASK_HPQ_LOW_TH_V1_8822C)
+#define BIT_SET_HPQ_LOW_TH_V1_8822C(x, v)                                      \
+	(BIT_CLEAR_HPQ_LOW_TH_V1_8822C(x) | BIT_HPQ_LOW_TH_V1_8822C(v))
+
+/* 2 REG_TQPNT2_8822C */
+#define BIT_NPQ_INT_EN_8822C BIT(31)
+
+#define BIT_SHIFT_NPQ_HIGH_TH_V1_8822C 16
+#define BIT_MASK_NPQ_HIGH_TH_V1_8822C 0xfff
+#define BIT_NPQ_HIGH_TH_V1_8822C(x)                                            \
+	(((x) & BIT_MASK_NPQ_HIGH_TH_V1_8822C)                                 \
+	 << BIT_SHIFT_NPQ_HIGH_TH_V1_8822C)
+#define BITS_NPQ_HIGH_TH_V1_8822C                                              \
+	(BIT_MASK_NPQ_HIGH_TH_V1_8822C << BIT_SHIFT_NPQ_HIGH_TH_V1_8822C)
+#define BIT_CLEAR_NPQ_HIGH_TH_V1_8822C(x) ((x) & (~BITS_NPQ_HIGH_TH_V1_8822C))
+#define BIT_GET_NPQ_HIGH_TH_V1_8822C(x)                                        \
+	(((x) >> BIT_SHIFT_NPQ_HIGH_TH_V1_8822C) &                             \
+	 BIT_MASK_NPQ_HIGH_TH_V1_8822C)
+#define BIT_SET_NPQ_HIGH_TH_V1_8822C(x, v)                                     \
+	(BIT_CLEAR_NPQ_HIGH_TH_V1_8822C(x) | BIT_NPQ_HIGH_TH_V1_8822C(v))
+
+#define BIT_SHIFT_NPQ_LOW_TH_V1_8822C 0
+#define BIT_MASK_NPQ_LOW_TH_V1_8822C 0xfff
+#define BIT_NPQ_LOW_TH_V1_8822C(x)                                             \
+	(((x) & BIT_MASK_NPQ_LOW_TH_V1_8822C) << BIT_SHIFT_NPQ_LOW_TH_V1_8822C)
+#define BITS_NPQ_LOW_TH_V1_8822C                                               \
+	(BIT_MASK_NPQ_LOW_TH_V1_8822C << BIT_SHIFT_NPQ_LOW_TH_V1_8822C)
+#define BIT_CLEAR_NPQ_LOW_TH_V1_8822C(x) ((x) & (~BITS_NPQ_LOW_TH_V1_8822C))
+#define BIT_GET_NPQ_LOW_TH_V1_8822C(x)                                         \
+	(((x) >> BIT_SHIFT_NPQ_LOW_TH_V1_8822C) & BIT_MASK_NPQ_LOW_TH_V1_8822C)
+#define BIT_SET_NPQ_LOW_TH_V1_8822C(x, v)                                      \
+	(BIT_CLEAR_NPQ_LOW_TH_V1_8822C(x) | BIT_NPQ_LOW_TH_V1_8822C(v))
+
+/* 2 REG_TQPNT3_8822C */
+#define BIT_LPQ_INT_EN_8822C BIT(31)
+
+#define BIT_SHIFT_LPQ_HIGH_TH_V1_8822C 16
+#define BIT_MASK_LPQ_HIGH_TH_V1_8822C 0xfff
+#define BIT_LPQ_HIGH_TH_V1_8822C(x)                                            \
+	(((x) & BIT_MASK_LPQ_HIGH_TH_V1_8822C)                                 \
+	 << BIT_SHIFT_LPQ_HIGH_TH_V1_8822C)
+#define BITS_LPQ_HIGH_TH_V1_8822C                                              \
+	(BIT_MASK_LPQ_HIGH_TH_V1_8822C << BIT_SHIFT_LPQ_HIGH_TH_V1_8822C)
+#define BIT_CLEAR_LPQ_HIGH_TH_V1_8822C(x) ((x) & (~BITS_LPQ_HIGH_TH_V1_8822C))
+#define BIT_GET_LPQ_HIGH_TH_V1_8822C(x)                                        \
+	(((x) >> BIT_SHIFT_LPQ_HIGH_TH_V1_8822C) &                             \
+	 BIT_MASK_LPQ_HIGH_TH_V1_8822C)
+#define BIT_SET_LPQ_HIGH_TH_V1_8822C(x, v)                                     \
+	(BIT_CLEAR_LPQ_HIGH_TH_V1_8822C(x) | BIT_LPQ_HIGH_TH_V1_8822C(v))
+
+#define BIT_SHIFT_LPQ_LOW_TH_V1_8822C 0
+#define BIT_MASK_LPQ_LOW_TH_V1_8822C 0xfff
+#define BIT_LPQ_LOW_TH_V1_8822C(x)                                             \
+	(((x) & BIT_MASK_LPQ_LOW_TH_V1_8822C) << BIT_SHIFT_LPQ_LOW_TH_V1_8822C)
+#define BITS_LPQ_LOW_TH_V1_8822C                                               \
+	(BIT_MASK_LPQ_LOW_TH_V1_8822C << BIT_SHIFT_LPQ_LOW_TH_V1_8822C)
+#define BIT_CLEAR_LPQ_LOW_TH_V1_8822C(x) ((x) & (~BITS_LPQ_LOW_TH_V1_8822C))
+#define BIT_GET_LPQ_LOW_TH_V1_8822C(x)                                         \
+	(((x) >> BIT_SHIFT_LPQ_LOW_TH_V1_8822C) & BIT_MASK_LPQ_LOW_TH_V1_8822C)
+#define BIT_SET_LPQ_LOW_TH_V1_8822C(x, v)                                      \
+	(BIT_CLEAR_LPQ_LOW_TH_V1_8822C(x) | BIT_LPQ_LOW_TH_V1_8822C(v))
+
+/* 2 REG_TQPNT4_8822C */
+#define BIT_EXQ_INT_EN_8822C BIT(31)
+
+#define BIT_SHIFT_EXQ_HIGH_TH_V1_8822C 16
+#define BIT_MASK_EXQ_HIGH_TH_V1_8822C 0xfff
+#define BIT_EXQ_HIGH_TH_V1_8822C(x)                                            \
+	(((x) & BIT_MASK_EXQ_HIGH_TH_V1_8822C)                                 \
+	 << BIT_SHIFT_EXQ_HIGH_TH_V1_8822C)
+#define BITS_EXQ_HIGH_TH_V1_8822C                                              \
+	(BIT_MASK_EXQ_HIGH_TH_V1_8822C << BIT_SHIFT_EXQ_HIGH_TH_V1_8822C)
+#define BIT_CLEAR_EXQ_HIGH_TH_V1_8822C(x) ((x) & (~BITS_EXQ_HIGH_TH_V1_8822C))
+#define BIT_GET_EXQ_HIGH_TH_V1_8822C(x)                                        \
+	(((x) >> BIT_SHIFT_EXQ_HIGH_TH_V1_8822C) &                             \
+	 BIT_MASK_EXQ_HIGH_TH_V1_8822C)
+#define BIT_SET_EXQ_HIGH_TH_V1_8822C(x, v)                                     \
+	(BIT_CLEAR_EXQ_HIGH_TH_V1_8822C(x) | BIT_EXQ_HIGH_TH_V1_8822C(v))
+
+#define BIT_SHIFT_EXQ_LOW_TH_V1_8822C 0
+#define BIT_MASK_EXQ_LOW_TH_V1_8822C 0xfff
+#define BIT_EXQ_LOW_TH_V1_8822C(x)                                             \
+	(((x) & BIT_MASK_EXQ_LOW_TH_V1_8822C) << BIT_SHIFT_EXQ_LOW_TH_V1_8822C)
+#define BITS_EXQ_LOW_TH_V1_8822C                                               \
+	(BIT_MASK_EXQ_LOW_TH_V1_8822C << BIT_SHIFT_EXQ_LOW_TH_V1_8822C)
+#define BIT_CLEAR_EXQ_LOW_TH_V1_8822C(x) ((x) & (~BITS_EXQ_LOW_TH_V1_8822C))
+#define BIT_GET_EXQ_LOW_TH_V1_8822C(x)                                         \
+	(((x) >> BIT_SHIFT_EXQ_LOW_TH_V1_8822C) & BIT_MASK_EXQ_LOW_TH_V1_8822C)
+#define BIT_SET_EXQ_LOW_TH_V1_8822C(x, v)                                      \
+	(BIT_CLEAR_EXQ_LOW_TH_V1_8822C(x) | BIT_EXQ_LOW_TH_V1_8822C(v))
+
+/* 2 REG_RQPN_CTRL_1_8822C */
+
+#define BIT_SHIFT_TXPKTNUM_H_V2_8822C 16
+#define BIT_MASK_TXPKTNUM_H_V2_8822C 0xfff
+#define BIT_TXPKTNUM_H_V2_8822C(x)                                             \
+	(((x) & BIT_MASK_TXPKTNUM_H_V2_8822C) << BIT_SHIFT_TXPKTNUM_H_V2_8822C)
+#define BITS_TXPKTNUM_H_V2_8822C                                               \
+	(BIT_MASK_TXPKTNUM_H_V2_8822C << BIT_SHIFT_TXPKTNUM_H_V2_8822C)
+#define BIT_CLEAR_TXPKTNUM_H_V2_8822C(x) ((x) & (~BITS_TXPKTNUM_H_V2_8822C))
+#define BIT_GET_TXPKTNUM_H_V2_8822C(x)                                         \
+	(((x) >> BIT_SHIFT_TXPKTNUM_H_V2_8822C) & BIT_MASK_TXPKTNUM_H_V2_8822C)
+#define BIT_SET_TXPKTNUM_H_V2_8822C(x, v)                                      \
+	(BIT_CLEAR_TXPKTNUM_H_V2_8822C(x) | BIT_TXPKTNUM_H_V2_8822C(v))
+
+#define BIT_SHIFT_TXPKTNUM_V3_8822C 0
+#define BIT_MASK_TXPKTNUM_V3_8822C 0xfff
+#define BIT_TXPKTNUM_V3_8822C(x)                                               \
+	(((x) & BIT_MASK_TXPKTNUM_V3_8822C) << BIT_SHIFT_TXPKTNUM_V3_8822C)
+#define BITS_TXPKTNUM_V3_8822C                                                 \
+	(BIT_MASK_TXPKTNUM_V3_8822C << BIT_SHIFT_TXPKTNUM_V3_8822C)
+#define BIT_CLEAR_TXPKTNUM_V3_8822C(x) ((x) & (~BITS_TXPKTNUM_V3_8822C))
+#define BIT_GET_TXPKTNUM_V3_8822C(x)                                           \
+	(((x) >> BIT_SHIFT_TXPKTNUM_V3_8822C) & BIT_MASK_TXPKTNUM_V3_8822C)
+#define BIT_SET_TXPKTNUM_V3_8822C(x, v)                                        \
+	(BIT_CLEAR_TXPKTNUM_V3_8822C(x) | BIT_TXPKTNUM_V3_8822C(v))
+
+/* 2 REG_RQPN_CTRL_2_8822C */
+#define BIT_LD_RQPN_8822C BIT(31)
+#define BIT_EXQ_PUBLIC_DIS_V1_8822C BIT(19)
+#define BIT_NPQ_PUBLIC_DIS_V1_8822C BIT(18)
+#define BIT_LPQ_PUBLIC_DIS_V1_8822C BIT(17)
+#define BIT_HPQ_PUBLIC_DIS_V1_8822C BIT(16)
+#define BIT_SDIO_TXAGG_ALIGN_ADJUST_EN_8822C BIT(15)
+
+#define BIT_SHIFT_SDIO_TXAGG_ALIGN_SIZE_8822C 0
+#define BIT_MASK_SDIO_TXAGG_ALIGN_SIZE_8822C 0xfff
+#define BIT_SDIO_TXAGG_ALIGN_SIZE_8822C(x)                                     \
+	(((x) & BIT_MASK_SDIO_TXAGG_ALIGN_SIZE_8822C)                          \
+	 << BIT_SHIFT_SDIO_TXAGG_ALIGN_SIZE_8822C)
+#define BITS_SDIO_TXAGG_ALIGN_SIZE_8822C                                       \
+	(BIT_MASK_SDIO_TXAGG_ALIGN_SIZE_8822C                                  \
+	 << BIT_SHIFT_SDIO_TXAGG_ALIGN_SIZE_8822C)
+#define BIT_CLEAR_SDIO_TXAGG_ALIGN_SIZE_8822C(x)                               \
+	((x) & (~BITS_SDIO_TXAGG_ALIGN_SIZE_8822C))
+#define BIT_GET_SDIO_TXAGG_ALIGN_SIZE_8822C(x)                                 \
+	(((x) >> BIT_SHIFT_SDIO_TXAGG_ALIGN_SIZE_8822C) &                      \
+	 BIT_MASK_SDIO_TXAGG_ALIGN_SIZE_8822C)
+#define BIT_SET_SDIO_TXAGG_ALIGN_SIZE_8822C(x, v)                              \
+	(BIT_CLEAR_SDIO_TXAGG_ALIGN_SIZE_8822C(x) |                            \
+	 BIT_SDIO_TXAGG_ALIGN_SIZE_8822C(v))
+
+/* 2 REG_FIFOPAGE_INFO_1_8822C */
+
+#define BIT_SHIFT_HPQ_AVAL_PG_V1_8822C 16
+#define BIT_MASK_HPQ_AVAL_PG_V1_8822C 0xfff
+#define BIT_HPQ_AVAL_PG_V1_8822C(x)                                            \
+	(((x) & BIT_MASK_HPQ_AVAL_PG_V1_8822C)                                 \
+	 << BIT_SHIFT_HPQ_AVAL_PG_V1_8822C)
+#define BITS_HPQ_AVAL_PG_V1_8822C                                              \
+	(BIT_MASK_HPQ_AVAL_PG_V1_8822C << BIT_SHIFT_HPQ_AVAL_PG_V1_8822C)
+#define BIT_CLEAR_HPQ_AVAL_PG_V1_8822C(x) ((x) & (~BITS_HPQ_AVAL_PG_V1_8822C))
+#define BIT_GET_HPQ_AVAL_PG_V1_8822C(x)                                        \
+	(((x) >> BIT_SHIFT_HPQ_AVAL_PG_V1_8822C) &                             \
+	 BIT_MASK_HPQ_AVAL_PG_V1_8822C)
+#define BIT_SET_HPQ_AVAL_PG_V1_8822C(x, v)                                     \
+	(BIT_CLEAR_HPQ_AVAL_PG_V1_8822C(x) | BIT_HPQ_AVAL_PG_V1_8822C(v))
+
+#define BIT_SHIFT_HPQ_V1_8822C 0
+#define BIT_MASK_HPQ_V1_8822C 0xfff
+#define BIT_HPQ_V1_8822C(x)                                                    \
+	(((x) & BIT_MASK_HPQ_V1_8822C) << BIT_SHIFT_HPQ_V1_8822C)
+#define BITS_HPQ_V1_8822C (BIT_MASK_HPQ_V1_8822C << BIT_SHIFT_HPQ_V1_8822C)
+#define BIT_CLEAR_HPQ_V1_8822C(x) ((x) & (~BITS_HPQ_V1_8822C))
+#define BIT_GET_HPQ_V1_8822C(x)                                                \
+	(((x) >> BIT_SHIFT_HPQ_V1_8822C) & BIT_MASK_HPQ_V1_8822C)
+#define BIT_SET_HPQ_V1_8822C(x, v)                                             \
+	(BIT_CLEAR_HPQ_V1_8822C(x) | BIT_HPQ_V1_8822C(v))
+
+/* 2 REG_FIFOPAGE_INFO_2_8822C */
+
+#define BIT_SHIFT_LPQ_AVAL_PG_V1_8822C 16
+#define BIT_MASK_LPQ_AVAL_PG_V1_8822C 0xfff
+#define BIT_LPQ_AVAL_PG_V1_8822C(x)                                            \
+	(((x) & BIT_MASK_LPQ_AVAL_PG_V1_8822C)                                 \
+	 << BIT_SHIFT_LPQ_AVAL_PG_V1_8822C)
+#define BITS_LPQ_AVAL_PG_V1_8822C                                              \
+	(BIT_MASK_LPQ_AVAL_PG_V1_8822C << BIT_SHIFT_LPQ_AVAL_PG_V1_8822C)
+#define BIT_CLEAR_LPQ_AVAL_PG_V1_8822C(x) ((x) & (~BITS_LPQ_AVAL_PG_V1_8822C))
+#define BIT_GET_LPQ_AVAL_PG_V1_8822C(x)                                        \
+	(((x) >> BIT_SHIFT_LPQ_AVAL_PG_V1_8822C) &                             \
+	 BIT_MASK_LPQ_AVAL_PG_V1_8822C)
+#define BIT_SET_LPQ_AVAL_PG_V1_8822C(x, v)                                     \
+	(BIT_CLEAR_LPQ_AVAL_PG_V1_8822C(x) | BIT_LPQ_AVAL_PG_V1_8822C(v))
+
+#define BIT_SHIFT_LPQ_V1_8822C 0
+#define BIT_MASK_LPQ_V1_8822C 0xfff
+#define BIT_LPQ_V1_8822C(x)                                                    \
+	(((x) & BIT_MASK_LPQ_V1_8822C) << BIT_SHIFT_LPQ_V1_8822C)
+#define BITS_LPQ_V1_8822C (BIT_MASK_LPQ_V1_8822C << BIT_SHIFT_LPQ_V1_8822C)
+#define BIT_CLEAR_LPQ_V1_8822C(x) ((x) & (~BITS_LPQ_V1_8822C))
+#define BIT_GET_LPQ_V1_8822C(x)                                                \
+	(((x) >> BIT_SHIFT_LPQ_V1_8822C) & BIT_MASK_LPQ_V1_8822C)
+#define BIT_SET_LPQ_V1_8822C(x, v)                                             \
+	(BIT_CLEAR_LPQ_V1_8822C(x) | BIT_LPQ_V1_8822C(v))
+
+/* 2 REG_FIFOPAGE_INFO_3_8822C */
+
+#define BIT_SHIFT_NPQ_AVAL_PG_V1_8822C 16
+#define BIT_MASK_NPQ_AVAL_PG_V1_8822C 0xfff
+#define BIT_NPQ_AVAL_PG_V1_8822C(x)                                            \
+	(((x) & BIT_MASK_NPQ_AVAL_PG_V1_8822C)                                 \
+	 << BIT_SHIFT_NPQ_AVAL_PG_V1_8822C)
+#define BITS_NPQ_AVAL_PG_V1_8822C                                              \
+	(BIT_MASK_NPQ_AVAL_PG_V1_8822C << BIT_SHIFT_NPQ_AVAL_PG_V1_8822C)
+#define BIT_CLEAR_NPQ_AVAL_PG_V1_8822C(x) ((x) & (~BITS_NPQ_AVAL_PG_V1_8822C))
+#define BIT_GET_NPQ_AVAL_PG_V1_8822C(x)                                        \
+	(((x) >> BIT_SHIFT_NPQ_AVAL_PG_V1_8822C) &                             \
+	 BIT_MASK_NPQ_AVAL_PG_V1_8822C)
+#define BIT_SET_NPQ_AVAL_PG_V1_8822C(x, v)                                     \
+	(BIT_CLEAR_NPQ_AVAL_PG_V1_8822C(x) | BIT_NPQ_AVAL_PG_V1_8822C(v))
+
+#define BIT_SHIFT_NPQ_V1_8822C 0
+#define BIT_MASK_NPQ_V1_8822C 0xfff
+#define BIT_NPQ_V1_8822C(x)                                                    \
+	(((x) & BIT_MASK_NPQ_V1_8822C) << BIT_SHIFT_NPQ_V1_8822C)
+#define BITS_NPQ_V1_8822C (BIT_MASK_NPQ_V1_8822C << BIT_SHIFT_NPQ_V1_8822C)
+#define BIT_CLEAR_NPQ_V1_8822C(x) ((x) & (~BITS_NPQ_V1_8822C))
+#define BIT_GET_NPQ_V1_8822C(x)                                                \
+	(((x) >> BIT_SHIFT_NPQ_V1_8822C) & BIT_MASK_NPQ_V1_8822C)
+#define BIT_SET_NPQ_V1_8822C(x, v)                                             \
+	(BIT_CLEAR_NPQ_V1_8822C(x) | BIT_NPQ_V1_8822C(v))
+
+/* 2 REG_FIFOPAGE_INFO_4_8822C */
+
+#define BIT_SHIFT_EXQ_AVAL_PG_V1_8822C 16
+#define BIT_MASK_EXQ_AVAL_PG_V1_8822C 0xfff
+#define BIT_EXQ_AVAL_PG_V1_8822C(x)                                            \
+	(((x) & BIT_MASK_EXQ_AVAL_PG_V1_8822C)                                 \
+	 << BIT_SHIFT_EXQ_AVAL_PG_V1_8822C)
+#define BITS_EXQ_AVAL_PG_V1_8822C                                              \
+	(BIT_MASK_EXQ_AVAL_PG_V1_8822C << BIT_SHIFT_EXQ_AVAL_PG_V1_8822C)
+#define BIT_CLEAR_EXQ_AVAL_PG_V1_8822C(x) ((x) & (~BITS_EXQ_AVAL_PG_V1_8822C))
+#define BIT_GET_EXQ_AVAL_PG_V1_8822C(x)                                        \
+	(((x) >> BIT_SHIFT_EXQ_AVAL_PG_V1_8822C) &                             \
+	 BIT_MASK_EXQ_AVAL_PG_V1_8822C)
+#define BIT_SET_EXQ_AVAL_PG_V1_8822C(x, v)                                     \
+	(BIT_CLEAR_EXQ_AVAL_PG_V1_8822C(x) | BIT_EXQ_AVAL_PG_V1_8822C(v))
+
+#define BIT_SHIFT_EXQ_V1_8822C 0
+#define BIT_MASK_EXQ_V1_8822C 0xfff
+#define BIT_EXQ_V1_8822C(x)                                                    \
+	(((x) & BIT_MASK_EXQ_V1_8822C) << BIT_SHIFT_EXQ_V1_8822C)
+#define BITS_EXQ_V1_8822C (BIT_MASK_EXQ_V1_8822C << BIT_SHIFT_EXQ_V1_8822C)
+#define BIT_CLEAR_EXQ_V1_8822C(x) ((x) & (~BITS_EXQ_V1_8822C))
+#define BIT_GET_EXQ_V1_8822C(x)                                                \
+	(((x) >> BIT_SHIFT_EXQ_V1_8822C) & BIT_MASK_EXQ_V1_8822C)
+#define BIT_SET_EXQ_V1_8822C(x, v)                                             \
+	(BIT_CLEAR_EXQ_V1_8822C(x) | BIT_EXQ_V1_8822C(v))
+
+/* 2 REG_FIFOPAGE_INFO_5_8822C */
+
+#define BIT_SHIFT_PUBQ_AVAL_PG_V1_8822C 16
+#define BIT_MASK_PUBQ_AVAL_PG_V1_8822C 0xfff
+#define BIT_PUBQ_AVAL_PG_V1_8822C(x)                                           \
+	(((x) & BIT_MASK_PUBQ_AVAL_PG_V1_8822C)                                \
+	 << BIT_SHIFT_PUBQ_AVAL_PG_V1_8822C)
+#define BITS_PUBQ_AVAL_PG_V1_8822C                                             \
+	(BIT_MASK_PUBQ_AVAL_PG_V1_8822C << BIT_SHIFT_PUBQ_AVAL_PG_V1_8822C)
+#define BIT_CLEAR_PUBQ_AVAL_PG_V1_8822C(x) ((x) & (~BITS_PUBQ_AVAL_PG_V1_8822C))
+#define BIT_GET_PUBQ_AVAL_PG_V1_8822C(x)                                       \
+	(((x) >> BIT_SHIFT_PUBQ_AVAL_PG_V1_8822C) &                            \
+	 BIT_MASK_PUBQ_AVAL_PG_V1_8822C)
+#define BIT_SET_PUBQ_AVAL_PG_V1_8822C(x, v)                                    \
+	(BIT_CLEAR_PUBQ_AVAL_PG_V1_8822C(x) | BIT_PUBQ_AVAL_PG_V1_8822C(v))
+
+#define BIT_SHIFT_PUBQ_V1_8822C 0
+#define BIT_MASK_PUBQ_V1_8822C 0xfff
+#define BIT_PUBQ_V1_8822C(x)                                                   \
+	(((x) & BIT_MASK_PUBQ_V1_8822C) << BIT_SHIFT_PUBQ_V1_8822C)
+#define BITS_PUBQ_V1_8822C (BIT_MASK_PUBQ_V1_8822C << BIT_SHIFT_PUBQ_V1_8822C)
+#define BIT_CLEAR_PUBQ_V1_8822C(x) ((x) & (~BITS_PUBQ_V1_8822C))
+#define BIT_GET_PUBQ_V1_8822C(x)                                               \
+	(((x) >> BIT_SHIFT_PUBQ_V1_8822C) & BIT_MASK_PUBQ_V1_8822C)
+#define BIT_SET_PUBQ_V1_8822C(x, v)                                            \
+	(BIT_CLEAR_PUBQ_V1_8822C(x) | BIT_PUBQ_V1_8822C(v))
+
+/* 2 REG_H2C_HEAD_8822C */
+
+#define BIT_SHIFT_H2C_HEAD_8822C 0
+#define BIT_MASK_H2C_HEAD_8822C 0x3ffff
+#define BIT_H2C_HEAD_8822C(x)                                                  \
+	(((x) & BIT_MASK_H2C_HEAD_8822C) << BIT_SHIFT_H2C_HEAD_8822C)
+#define BITS_H2C_HEAD_8822C                                                    \
+	(BIT_MASK_H2C_HEAD_8822C << BIT_SHIFT_H2C_HEAD_8822C)
+#define BIT_CLEAR_H2C_HEAD_8822C(x) ((x) & (~BITS_H2C_HEAD_8822C))
+#define BIT_GET_H2C_HEAD_8822C(x)                                              \
+	(((x) >> BIT_SHIFT_H2C_HEAD_8822C) & BIT_MASK_H2C_HEAD_8822C)
+#define BIT_SET_H2C_HEAD_8822C(x, v)                                           \
+	(BIT_CLEAR_H2C_HEAD_8822C(x) | BIT_H2C_HEAD_8822C(v))
+
+/* 2 REG_H2C_TAIL_8822C */
+
+#define BIT_SHIFT_H2C_TAIL_8822C 0
+#define BIT_MASK_H2C_TAIL_8822C 0x3ffff
+#define BIT_H2C_TAIL_8822C(x)                                                  \
+	(((x) & BIT_MASK_H2C_TAIL_8822C) << BIT_SHIFT_H2C_TAIL_8822C)
+#define BITS_H2C_TAIL_8822C                                                    \
+	(BIT_MASK_H2C_TAIL_8822C << BIT_SHIFT_H2C_TAIL_8822C)
+#define BIT_CLEAR_H2C_TAIL_8822C(x) ((x) & (~BITS_H2C_TAIL_8822C))
+#define BIT_GET_H2C_TAIL_8822C(x)                                              \
+	(((x) >> BIT_SHIFT_H2C_TAIL_8822C) & BIT_MASK_H2C_TAIL_8822C)
+#define BIT_SET_H2C_TAIL_8822C(x, v)                                           \
+	(BIT_CLEAR_H2C_TAIL_8822C(x) | BIT_H2C_TAIL_8822C(v))
+
+/* 2 REG_H2C_READ_ADDR_8822C */
+
+#define BIT_SHIFT_H2C_READ_ADDR_8822C 0
+#define BIT_MASK_H2C_READ_ADDR_8822C 0x3ffff
+#define BIT_H2C_READ_ADDR_8822C(x)                                             \
+	(((x) & BIT_MASK_H2C_READ_ADDR_8822C) << BIT_SHIFT_H2C_READ_ADDR_8822C)
+#define BITS_H2C_READ_ADDR_8822C                                               \
+	(BIT_MASK_H2C_READ_ADDR_8822C << BIT_SHIFT_H2C_READ_ADDR_8822C)
+#define BIT_CLEAR_H2C_READ_ADDR_8822C(x) ((x) & (~BITS_H2C_READ_ADDR_8822C))
+#define BIT_GET_H2C_READ_ADDR_8822C(x)                                         \
+	(((x) >> BIT_SHIFT_H2C_READ_ADDR_8822C) & BIT_MASK_H2C_READ_ADDR_8822C)
+#define BIT_SET_H2C_READ_ADDR_8822C(x, v)                                      \
+	(BIT_CLEAR_H2C_READ_ADDR_8822C(x) | BIT_H2C_READ_ADDR_8822C(v))
+
+/* 2 REG_H2C_WR_ADDR_8822C */
+
+#define BIT_SHIFT_H2C_WR_ADDR_8822C 0
+#define BIT_MASK_H2C_WR_ADDR_8822C 0x3ffff
+#define BIT_H2C_WR_ADDR_8822C(x)                                               \
+	(((x) & BIT_MASK_H2C_WR_ADDR_8822C) << BIT_SHIFT_H2C_WR_ADDR_8822C)
+#define BITS_H2C_WR_ADDR_8822C                                                 \
+	(BIT_MASK_H2C_WR_ADDR_8822C << BIT_SHIFT_H2C_WR_ADDR_8822C)
+#define BIT_CLEAR_H2C_WR_ADDR_8822C(x) ((x) & (~BITS_H2C_WR_ADDR_8822C))
+#define BIT_GET_H2C_WR_ADDR_8822C(x)                                           \
+	(((x) >> BIT_SHIFT_H2C_WR_ADDR_8822C) & BIT_MASK_H2C_WR_ADDR_8822C)
+#define BIT_SET_H2C_WR_ADDR_8822C(x, v)                                        \
+	(BIT_CLEAR_H2C_WR_ADDR_8822C(x) | BIT_H2C_WR_ADDR_8822C(v))
+
+/* 2 REG_H2C_INFO_8822C */
+#define BIT_H2C_SPACE_VLD_8822C BIT(3)
+#define BIT_H2C_WR_ADDR_RST_8822C BIT(2)
+
+#define BIT_SHIFT_H2C_LEN_SEL_8822C 0
+#define BIT_MASK_H2C_LEN_SEL_8822C 0x3
+#define BIT_H2C_LEN_SEL_8822C(x)                                               \
+	(((x) & BIT_MASK_H2C_LEN_SEL_8822C) << BIT_SHIFT_H2C_LEN_SEL_8822C)
+#define BITS_H2C_LEN_SEL_8822C                                                 \
+	(BIT_MASK_H2C_LEN_SEL_8822C << BIT_SHIFT_H2C_LEN_SEL_8822C)
+#define BIT_CLEAR_H2C_LEN_SEL_8822C(x) ((x) & (~BITS_H2C_LEN_SEL_8822C))
+#define BIT_GET_H2C_LEN_SEL_8822C(x)                                           \
+	(((x) >> BIT_SHIFT_H2C_LEN_SEL_8822C) & BIT_MASK_H2C_LEN_SEL_8822C)
+#define BIT_SET_H2C_LEN_SEL_8822C(x, v)                                        \
+	(BIT_CLEAR_H2C_LEN_SEL_8822C(x) | BIT_H2C_LEN_SEL_8822C(v))
+
+/* 2 REG_PGSUB_CNT_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+#define BIT_RST_PGSUB_CNT_8822C BIT(1)
+#define BIT_PGSUB_CNT_EN_8822C BIT(0)
+
+/* 2 REG_PGSUB_H_8822C */
+
+#define BIT_SHIFT_HPQ_PGSUB_CNT_8822C 0
+#define BIT_MASK_HPQ_PGSUB_CNT_8822C 0xffffffffL
+#define BIT_HPQ_PGSUB_CNT_8822C(x)                                             \
+	(((x) & BIT_MASK_HPQ_PGSUB_CNT_8822C) << BIT_SHIFT_HPQ_PGSUB_CNT_8822C)
+#define BITS_HPQ_PGSUB_CNT_8822C                                               \
+	(BIT_MASK_HPQ_PGSUB_CNT_8822C << BIT_SHIFT_HPQ_PGSUB_CNT_8822C)
+#define BIT_CLEAR_HPQ_PGSUB_CNT_8822C(x) ((x) & (~BITS_HPQ_PGSUB_CNT_8822C))
+#define BIT_GET_HPQ_PGSUB_CNT_8822C(x)                                         \
+	(((x) >> BIT_SHIFT_HPQ_PGSUB_CNT_8822C) & BIT_MASK_HPQ_PGSUB_CNT_8822C)
+#define BIT_SET_HPQ_PGSUB_CNT_8822C(x, v)                                      \
+	(BIT_CLEAR_HPQ_PGSUB_CNT_8822C(x) | BIT_HPQ_PGSUB_CNT_8822C(v))
+
+/* 2 REG_PGSUB_N_8822C */
+
+#define BIT_SHIFT_NPQ_PGSUB_CNT_8822C 0
+#define BIT_MASK_NPQ_PGSUB_CNT_8822C 0xffffffffL
+#define BIT_NPQ_PGSUB_CNT_8822C(x)                                             \
+	(((x) & BIT_MASK_NPQ_PGSUB_CNT_8822C) << BIT_SHIFT_NPQ_PGSUB_CNT_8822C)
+#define BITS_NPQ_PGSUB_CNT_8822C                                               \
+	(BIT_MASK_NPQ_PGSUB_CNT_8822C << BIT_SHIFT_NPQ_PGSUB_CNT_8822C)
+#define BIT_CLEAR_NPQ_PGSUB_CNT_8822C(x) ((x) & (~BITS_NPQ_PGSUB_CNT_8822C))
+#define BIT_GET_NPQ_PGSUB_CNT_8822C(x)                                         \
+	(((x) >> BIT_SHIFT_NPQ_PGSUB_CNT_8822C) & BIT_MASK_NPQ_PGSUB_CNT_8822C)
+#define BIT_SET_NPQ_PGSUB_CNT_8822C(x, v)                                      \
+	(BIT_CLEAR_NPQ_PGSUB_CNT_8822C(x) | BIT_NPQ_PGSUB_CNT_8822C(v))
+
+/* 2 REG_PGSUB_L_8822C */
+
+#define BIT_SHIFT_LPQ_PGSUB_CNT_8822C 0
+#define BIT_MASK_LPQ_PGSUB_CNT_8822C 0xffffffffL
+#define BIT_LPQ_PGSUB_CNT_8822C(x)                                             \
+	(((x) & BIT_MASK_LPQ_PGSUB_CNT_8822C) << BIT_SHIFT_LPQ_PGSUB_CNT_8822C)
+#define BITS_LPQ_PGSUB_CNT_8822C                                               \
+	(BIT_MASK_LPQ_PGSUB_CNT_8822C << BIT_SHIFT_LPQ_PGSUB_CNT_8822C)
+#define BIT_CLEAR_LPQ_PGSUB_CNT_8822C(x) ((x) & (~BITS_LPQ_PGSUB_CNT_8822C))
+#define BIT_GET_LPQ_PGSUB_CNT_8822C(x)                                         \
+	(((x) >> BIT_SHIFT_LPQ_PGSUB_CNT_8822C) & BIT_MASK_LPQ_PGSUB_CNT_8822C)
+#define BIT_SET_LPQ_PGSUB_CNT_8822C(x, v)                                      \
+	(BIT_CLEAR_LPQ_PGSUB_CNT_8822C(x) | BIT_LPQ_PGSUB_CNT_8822C(v))
+
+/* 2 REG_PGSUB_E_8822C */
+
+#define BIT_SHIFT_EPQ_PGSUB_CNT_8822C 0
+#define BIT_MASK_EPQ_PGSUB_CNT_8822C 0xffffffffL
+#define BIT_EPQ_PGSUB_CNT_8822C(x)                                             \
+	(((x) & BIT_MASK_EPQ_PGSUB_CNT_8822C) << BIT_SHIFT_EPQ_PGSUB_CNT_8822C)
+#define BITS_EPQ_PGSUB_CNT_8822C                                               \
+	(BIT_MASK_EPQ_PGSUB_CNT_8822C << BIT_SHIFT_EPQ_PGSUB_CNT_8822C)
+#define BIT_CLEAR_EPQ_PGSUB_CNT_8822C(x) ((x) & (~BITS_EPQ_PGSUB_CNT_8822C))
+#define BIT_GET_EPQ_PGSUB_CNT_8822C(x)                                         \
+	(((x) >> BIT_SHIFT_EPQ_PGSUB_CNT_8822C) & BIT_MASK_EPQ_PGSUB_CNT_8822C)
+#define BIT_SET_EPQ_PGSUB_CNT_8822C(x, v)                                      \
+	(BIT_CLEAR_EPQ_PGSUB_CNT_8822C(x) | BIT_EPQ_PGSUB_CNT_8822C(v))
+
+/* 2 REG_RXDMA_AGG_PG_TH_8822C */
+#define BIT_USB_RXDMA_AGG_EN_8822C BIT(31)
+#define BIT_EN_FW_ADD_8822C BIT(30)
+#define BIT_EN_PRE_CALC_8822C BIT(29)
+#define BIT_RXAGG_SW_EN_8822C BIT(28)
+#define BIT_RXAGG_SW_TRIG_8822C BIT(27)
+
+/* 2 REG_NOT_VALID_8822C */
+
+#define BIT_SHIFT_DMA_AGG_TO_V1_8822C 8
+#define BIT_MASK_DMA_AGG_TO_V1_8822C 0xff
+#define BIT_DMA_AGG_TO_V1_8822C(x)                                             \
+	(((x) & BIT_MASK_DMA_AGG_TO_V1_8822C) << BIT_SHIFT_DMA_AGG_TO_V1_8822C)
+#define BITS_DMA_AGG_TO_V1_8822C                                               \
+	(BIT_MASK_DMA_AGG_TO_V1_8822C << BIT_SHIFT_DMA_AGG_TO_V1_8822C)
+#define BIT_CLEAR_DMA_AGG_TO_V1_8822C(x) ((x) & (~BITS_DMA_AGG_TO_V1_8822C))
+#define BIT_GET_DMA_AGG_TO_V1_8822C(x)                                         \
+	(((x) >> BIT_SHIFT_DMA_AGG_TO_V1_8822C) & BIT_MASK_DMA_AGG_TO_V1_8822C)
+#define BIT_SET_DMA_AGG_TO_V1_8822C(x, v)                                      \
+	(BIT_CLEAR_DMA_AGG_TO_V1_8822C(x) | BIT_DMA_AGG_TO_V1_8822C(v))
+
+#define BIT_SHIFT_RXDMA_AGG_PG_TH_8822C 0
+#define BIT_MASK_RXDMA_AGG_PG_TH_8822C 0xff
+#define BIT_RXDMA_AGG_PG_TH_8822C(x)                                           \
+	(((x) & BIT_MASK_RXDMA_AGG_PG_TH_8822C)                                \
+	 << BIT_SHIFT_RXDMA_AGG_PG_TH_8822C)
+#define BITS_RXDMA_AGG_PG_TH_8822C                                             \
+	(BIT_MASK_RXDMA_AGG_PG_TH_8822C << BIT_SHIFT_RXDMA_AGG_PG_TH_8822C)
+#define BIT_CLEAR_RXDMA_AGG_PG_TH_8822C(x) ((x) & (~BITS_RXDMA_AGG_PG_TH_8822C))
+#define BIT_GET_RXDMA_AGG_PG_TH_8822C(x)                                       \
+	(((x) >> BIT_SHIFT_RXDMA_AGG_PG_TH_8822C) &                            \
+	 BIT_MASK_RXDMA_AGG_PG_TH_8822C)
+#define BIT_SET_RXDMA_AGG_PG_TH_8822C(x, v)                                    \
+	(BIT_CLEAR_RXDMA_AGG_PG_TH_8822C(x) | BIT_RXDMA_AGG_PG_TH_8822C(v))
+
+/* 2 REG_RXPKT_NUM_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+#define BIT_SHIFT_FW_UPD_RDPTR19_TO_16_8822C 20
+#define BIT_MASK_FW_UPD_RDPTR19_TO_16_8822C 0xf
+#define BIT_FW_UPD_RDPTR19_TO_16_8822C(x)                                      \
+	(((x) & BIT_MASK_FW_UPD_RDPTR19_TO_16_8822C)                           \
+	 << BIT_SHIFT_FW_UPD_RDPTR19_TO_16_8822C)
+#define BITS_FW_UPD_RDPTR19_TO_16_8822C                                        \
+	(BIT_MASK_FW_UPD_RDPTR19_TO_16_8822C                                   \
+	 << BIT_SHIFT_FW_UPD_RDPTR19_TO_16_8822C)
+#define BIT_CLEAR_FW_UPD_RDPTR19_TO_16_8822C(x)                                \
+	((x) & (~BITS_FW_UPD_RDPTR19_TO_16_8822C))
+#define BIT_GET_FW_UPD_RDPTR19_TO_16_8822C(x)                                  \
+	(((x) >> BIT_SHIFT_FW_UPD_RDPTR19_TO_16_8822C) &                       \
+	 BIT_MASK_FW_UPD_RDPTR19_TO_16_8822C)
+#define BIT_SET_FW_UPD_RDPTR19_TO_16_8822C(x, v)                               \
+	(BIT_CLEAR_FW_UPD_RDPTR19_TO_16_8822C(x) |                             \
+	 BIT_FW_UPD_RDPTR19_TO_16_8822C(v))
+
+#define BIT_RXDMA_REQ_8822C BIT(19)
+#define BIT_RW_RELEASE_EN_8822C BIT(18)
+#define BIT_RXDMA_IDLE_8822C BIT(17)
+#define BIT_RXPKT_RELEASE_POLL_8822C BIT(16)
+
+#define BIT_SHIFT_FW_UPD_RDPTR_8822C 0
+#define BIT_MASK_FW_UPD_RDPTR_8822C 0xffff
+#define BIT_FW_UPD_RDPTR_8822C(x)                                              \
+	(((x) & BIT_MASK_FW_UPD_RDPTR_8822C) << BIT_SHIFT_FW_UPD_RDPTR_8822C)
+#define BITS_FW_UPD_RDPTR_8822C                                                \
+	(BIT_MASK_FW_UPD_RDPTR_8822C << BIT_SHIFT_FW_UPD_RDPTR_8822C)
+#define BIT_CLEAR_FW_UPD_RDPTR_8822C(x) ((x) & (~BITS_FW_UPD_RDPTR_8822C))
+#define BIT_GET_FW_UPD_RDPTR_8822C(x)                                          \
+	(((x) >> BIT_SHIFT_FW_UPD_RDPTR_8822C) & BIT_MASK_FW_UPD_RDPTR_8822C)
+#define BIT_SET_FW_UPD_RDPTR_8822C(x, v)                                       \
+	(BIT_CLEAR_FW_UPD_RDPTR_8822C(x) | BIT_FW_UPD_RDPTR_8822C(v))
+
+/* 2 REG_RXDMA_STATUS_8822C */
+#define BIT_C2H_PKT_OVF_8822C BIT(7)
+#define BIT_AGG_CONFGI_ISSUE_8822C BIT(6)
+#define BIT_FW_POLL_ISSUE_8822C BIT(5)
+#define BIT_RX_DATA_UDN_8822C BIT(4)
+#define BIT_RX_SFF_UDN_8822C BIT(3)
+#define BIT_RX_SFF_OVF_8822C BIT(2)
+#define BIT_RXPKT_OVF_8822C BIT(0)
+
+/* 2 REG_RXDMA_DPR_8822C */
+
+#define BIT_SHIFT_RDE_DEBUG_8822C 0
+#define BIT_MASK_RDE_DEBUG_8822C 0xffffffffL
+#define BIT_RDE_DEBUG_8822C(x)                                                 \
+	(((x) & BIT_MASK_RDE_DEBUG_8822C) << BIT_SHIFT_RDE_DEBUG_8822C)
+#define BITS_RDE_DEBUG_8822C                                                   \
+	(BIT_MASK_RDE_DEBUG_8822C << BIT_SHIFT_RDE_DEBUG_8822C)
+#define BIT_CLEAR_RDE_DEBUG_8822C(x) ((x) & (~BITS_RDE_DEBUG_8822C))
+#define BIT_GET_RDE_DEBUG_8822C(x)                                             \
+	(((x) >> BIT_SHIFT_RDE_DEBUG_8822C) & BIT_MASK_RDE_DEBUG_8822C)
+#define BIT_SET_RDE_DEBUG_8822C(x, v)                                          \
+	(BIT_CLEAR_RDE_DEBUG_8822C(x) | BIT_RDE_DEBUG_8822C(v))
+
+/* 2 REG_RXDMA_MODE_8822C */
+
+#define BIT_SHIFT_PKTNUM_TH_V2_8822C 24
+#define BIT_MASK_PKTNUM_TH_V2_8822C 0x1f
+#define BIT_PKTNUM_TH_V2_8822C(x)                                              \
+	(((x) & BIT_MASK_PKTNUM_TH_V2_8822C) << BIT_SHIFT_PKTNUM_TH_V2_8822C)
+#define BITS_PKTNUM_TH_V2_8822C                                                \
+	(BIT_MASK_PKTNUM_TH_V2_8822C << BIT_SHIFT_PKTNUM_TH_V2_8822C)
+#define BIT_CLEAR_PKTNUM_TH_V2_8822C(x) ((x) & (~BITS_PKTNUM_TH_V2_8822C))
+#define BIT_GET_PKTNUM_TH_V2_8822C(x)                                          \
+	(((x) >> BIT_SHIFT_PKTNUM_TH_V2_8822C) & BIT_MASK_PKTNUM_TH_V2_8822C)
+#define BIT_SET_PKTNUM_TH_V2_8822C(x, v)                                       \
+	(BIT_CLEAR_PKTNUM_TH_V2_8822C(x) | BIT_PKTNUM_TH_V2_8822C(v))
+
+#define BIT_TXBA_BREAK_USBAGG_8822C BIT(23)
+
+#define BIT_SHIFT_PKTLEN_PARA_8822C 16
+#define BIT_MASK_PKTLEN_PARA_8822C 0x7
+#define BIT_PKTLEN_PARA_8822C(x)                                               \
+	(((x) & BIT_MASK_PKTLEN_PARA_8822C) << BIT_SHIFT_PKTLEN_PARA_8822C)
+#define BITS_PKTLEN_PARA_8822C                                                 \
+	(BIT_MASK_PKTLEN_PARA_8822C << BIT_SHIFT_PKTLEN_PARA_8822C)
+#define BIT_CLEAR_PKTLEN_PARA_8822C(x) ((x) & (~BITS_PKTLEN_PARA_8822C))
+#define BIT_GET_PKTLEN_PARA_8822C(x)                                           \
+	(((x) >> BIT_SHIFT_PKTLEN_PARA_8822C) & BIT_MASK_PKTLEN_PARA_8822C)
+#define BIT_SET_PKTLEN_PARA_8822C(x, v)                                        \
+	(BIT_CLEAR_PKTLEN_PARA_8822C(x) | BIT_PKTLEN_PARA_8822C(v))
+
+#define BIT_RX_DBG_SEL_8822C BIT(7)
+#define BIT_EN_SPD_8822C BIT(6)
+
+#define BIT_SHIFT_BURST_SIZE_8822C 4
+#define BIT_MASK_BURST_SIZE_8822C 0x3
+#define BIT_BURST_SIZE_8822C(x)                                                \
+	(((x) & BIT_MASK_BURST_SIZE_8822C) << BIT_SHIFT_BURST_SIZE_8822C)
+#define BITS_BURST_SIZE_8822C                                                  \
+	(BIT_MASK_BURST_SIZE_8822C << BIT_SHIFT_BURST_SIZE_8822C)
+#define BIT_CLEAR_BURST_SIZE_8822C(x) ((x) & (~BITS_BURST_SIZE_8822C))
+#define BIT_GET_BURST_SIZE_8822C(x)                                            \
+	(((x) >> BIT_SHIFT_BURST_SIZE_8822C) & BIT_MASK_BURST_SIZE_8822C)
+#define BIT_SET_BURST_SIZE_8822C(x, v)                                         \
+	(BIT_CLEAR_BURST_SIZE_8822C(x) | BIT_BURST_SIZE_8822C(v))
+
+#define BIT_SHIFT_BURST_CNT_8822C 2
+#define BIT_MASK_BURST_CNT_8822C 0x3
+#define BIT_BURST_CNT_8822C(x)                                                 \
+	(((x) & BIT_MASK_BURST_CNT_8822C) << BIT_SHIFT_BURST_CNT_8822C)
+#define BITS_BURST_CNT_8822C                                                   \
+	(BIT_MASK_BURST_CNT_8822C << BIT_SHIFT_BURST_CNT_8822C)
+#define BIT_CLEAR_BURST_CNT_8822C(x) ((x) & (~BITS_BURST_CNT_8822C))
+#define BIT_GET_BURST_CNT_8822C(x)                                             \
+	(((x) >> BIT_SHIFT_BURST_CNT_8822C) & BIT_MASK_BURST_CNT_8822C)
+#define BIT_SET_BURST_CNT_8822C(x, v)                                          \
+	(BIT_CLEAR_BURST_CNT_8822C(x) | BIT_BURST_CNT_8822C(v))
+
+#define BIT_DMA_MODE_8822C BIT(1)
+
+/* 2 REG_C2H_PKT_8822C */
+
+#define BIT_SHIFT_R_C2H_STR_ADDR_16_TO_19_8822C 24
+#define BIT_MASK_R_C2H_STR_ADDR_16_TO_19_8822C 0xf
+#define BIT_R_C2H_STR_ADDR_16_TO_19_8822C(x)                                   \
+	(((x) & BIT_MASK_R_C2H_STR_ADDR_16_TO_19_8822C)                        \
+	 << BIT_SHIFT_R_C2H_STR_ADDR_16_TO_19_8822C)
+#define BITS_R_C2H_STR_ADDR_16_TO_19_8822C                                     \
+	(BIT_MASK_R_C2H_STR_ADDR_16_TO_19_8822C                                \
+	 << BIT_SHIFT_R_C2H_STR_ADDR_16_TO_19_8822C)
+#define BIT_CLEAR_R_C2H_STR_ADDR_16_TO_19_8822C(x)                             \
+	((x) & (~BITS_R_C2H_STR_ADDR_16_TO_19_8822C))
+#define BIT_GET_R_C2H_STR_ADDR_16_TO_19_8822C(x)                               \
+	(((x) >> BIT_SHIFT_R_C2H_STR_ADDR_16_TO_19_8822C) &                    \
+	 BIT_MASK_R_C2H_STR_ADDR_16_TO_19_8822C)
+#define BIT_SET_R_C2H_STR_ADDR_16_TO_19_8822C(x, v)                            \
+	(BIT_CLEAR_R_C2H_STR_ADDR_16_TO_19_8822C(x) |                          \
+	 BIT_R_C2H_STR_ADDR_16_TO_19_8822C(v))
+
+#define BIT_R_C2H_PKT_REQ_8822C BIT(16)
+
+#define BIT_SHIFT_R_C2H_STR_ADDR_8822C 0
+#define BIT_MASK_R_C2H_STR_ADDR_8822C 0xffff
+#define BIT_R_C2H_STR_ADDR_8822C(x)                                            \
+	(((x) & BIT_MASK_R_C2H_STR_ADDR_8822C)                                 \
+	 << BIT_SHIFT_R_C2H_STR_ADDR_8822C)
+#define BITS_R_C2H_STR_ADDR_8822C                                              \
+	(BIT_MASK_R_C2H_STR_ADDR_8822C << BIT_SHIFT_R_C2H_STR_ADDR_8822C)
+#define BIT_CLEAR_R_C2H_STR_ADDR_8822C(x) ((x) & (~BITS_R_C2H_STR_ADDR_8822C))
+#define BIT_GET_R_C2H_STR_ADDR_8822C(x)                                        \
+	(((x) >> BIT_SHIFT_R_C2H_STR_ADDR_8822C) &                             \
+	 BIT_MASK_R_C2H_STR_ADDR_8822C)
+#define BIT_SET_R_C2H_STR_ADDR_8822C(x, v)                                     \
+	(BIT_CLEAR_R_C2H_STR_ADDR_8822C(x) | BIT_R_C2H_STR_ADDR_8822C(v))
+
+/* 2 REG_FWFF_C2H_8822C */
+
+#define BIT_SHIFT_C2H_DMA_ADDR_8822C 0
+#define BIT_MASK_C2H_DMA_ADDR_8822C 0x3ffff
+#define BIT_C2H_DMA_ADDR_8822C(x)                                              \
+	(((x) & BIT_MASK_C2H_DMA_ADDR_8822C) << BIT_SHIFT_C2H_DMA_ADDR_8822C)
+#define BITS_C2H_DMA_ADDR_8822C                                                \
+	(BIT_MASK_C2H_DMA_ADDR_8822C << BIT_SHIFT_C2H_DMA_ADDR_8822C)
+#define BIT_CLEAR_C2H_DMA_ADDR_8822C(x) ((x) & (~BITS_C2H_DMA_ADDR_8822C))
+#define BIT_GET_C2H_DMA_ADDR_8822C(x)                                          \
+	(((x) >> BIT_SHIFT_C2H_DMA_ADDR_8822C) & BIT_MASK_C2H_DMA_ADDR_8822C)
+#define BIT_SET_C2H_DMA_ADDR_8822C(x, v)                                       \
+	(BIT_CLEAR_C2H_DMA_ADDR_8822C(x) | BIT_C2H_DMA_ADDR_8822C(v))
+
+/* 2 REG_FWFF_CTRL_8822C */
+#define BIT_FWFF_DMAPKT_REQ_8822C BIT(31)
+
+#define BIT_SHIFT_FWFF_DMA_PKT_NUM_8822C 16
+#define BIT_MASK_FWFF_DMA_PKT_NUM_8822C 0xff
+#define BIT_FWFF_DMA_PKT_NUM_8822C(x)                                          \
+	(((x) & BIT_MASK_FWFF_DMA_PKT_NUM_8822C)                               \
+	 << BIT_SHIFT_FWFF_DMA_PKT_NUM_8822C)
+#define BITS_FWFF_DMA_PKT_NUM_8822C                                            \
+	(BIT_MASK_FWFF_DMA_PKT_NUM_8822C << BIT_SHIFT_FWFF_DMA_PKT_NUM_8822C)
+#define BIT_CLEAR_FWFF_DMA_PKT_NUM_8822C(x)                                    \
+	((x) & (~BITS_FWFF_DMA_PKT_NUM_8822C))
+#define BIT_GET_FWFF_DMA_PKT_NUM_8822C(x)                                      \
+	(((x) >> BIT_SHIFT_FWFF_DMA_PKT_NUM_8822C) &                           \
+	 BIT_MASK_FWFF_DMA_PKT_NUM_8822C)
+#define BIT_SET_FWFF_DMA_PKT_NUM_8822C(x, v)                                   \
+	(BIT_CLEAR_FWFF_DMA_PKT_NUM_8822C(x) | BIT_FWFF_DMA_PKT_NUM_8822C(v))
+
+#define BIT_SHIFT_FWFF_STR_ADDR_8822C 0
+#define BIT_MASK_FWFF_STR_ADDR_8822C 0xffff
+#define BIT_FWFF_STR_ADDR_8822C(x)                                             \
+	(((x) & BIT_MASK_FWFF_STR_ADDR_8822C) << BIT_SHIFT_FWFF_STR_ADDR_8822C)
+#define BITS_FWFF_STR_ADDR_8822C                                               \
+	(BIT_MASK_FWFF_STR_ADDR_8822C << BIT_SHIFT_FWFF_STR_ADDR_8822C)
+#define BIT_CLEAR_FWFF_STR_ADDR_8822C(x) ((x) & (~BITS_FWFF_STR_ADDR_8822C))
+#define BIT_GET_FWFF_STR_ADDR_8822C(x)                                         \
+	(((x) >> BIT_SHIFT_FWFF_STR_ADDR_8822C) & BIT_MASK_FWFF_STR_ADDR_8822C)
+#define BIT_SET_FWFF_STR_ADDR_8822C(x, v)                                      \
+	(BIT_CLEAR_FWFF_STR_ADDR_8822C(x) | BIT_FWFF_STR_ADDR_8822C(v))
+
+/* 2 REG_FWFF_PKT_INFO_8822C */
+
+#define BIT_SHIFT_FWFF_PKT_QUEUED_8822C 16
+#define BIT_MASK_FWFF_PKT_QUEUED_8822C 0xff
+#define BIT_FWFF_PKT_QUEUED_8822C(x)                                           \
+	(((x) & BIT_MASK_FWFF_PKT_QUEUED_8822C)                                \
+	 << BIT_SHIFT_FWFF_PKT_QUEUED_8822C)
+#define BITS_FWFF_PKT_QUEUED_8822C                                             \
+	(BIT_MASK_FWFF_PKT_QUEUED_8822C << BIT_SHIFT_FWFF_PKT_QUEUED_8822C)
+#define BIT_CLEAR_FWFF_PKT_QUEUED_8822C(x) ((x) & (~BITS_FWFF_PKT_QUEUED_8822C))
+#define BIT_GET_FWFF_PKT_QUEUED_8822C(x)                                       \
+	(((x) >> BIT_SHIFT_FWFF_PKT_QUEUED_8822C) &                            \
+	 BIT_MASK_FWFF_PKT_QUEUED_8822C)
+#define BIT_SET_FWFF_PKT_QUEUED_8822C(x, v)                                    \
+	(BIT_CLEAR_FWFF_PKT_QUEUED_8822C(x) | BIT_FWFF_PKT_QUEUED_8822C(v))
+
+/* 2 REG_NOT_VALID_8822C */
+
+#define BIT_SHIFT_FWFF_PKT_STR_ADDR_V2_8822C 0
+#define BIT_MASK_FWFF_PKT_STR_ADDR_V2_8822C 0x3fff
+#define BIT_FWFF_PKT_STR_ADDR_V2_8822C(x)                                      \
+	(((x) & BIT_MASK_FWFF_PKT_STR_ADDR_V2_8822C)                           \
+	 << BIT_SHIFT_FWFF_PKT_STR_ADDR_V2_8822C)
+#define BITS_FWFF_PKT_STR_ADDR_V2_8822C                                        \
+	(BIT_MASK_FWFF_PKT_STR_ADDR_V2_8822C                                   \
+	 << BIT_SHIFT_FWFF_PKT_STR_ADDR_V2_8822C)
+#define BIT_CLEAR_FWFF_PKT_STR_ADDR_V2_8822C(x)                                \
+	((x) & (~BITS_FWFF_PKT_STR_ADDR_V2_8822C))
+#define BIT_GET_FWFF_PKT_STR_ADDR_V2_8822C(x)                                  \
+	(((x) >> BIT_SHIFT_FWFF_PKT_STR_ADDR_V2_8822C) &                       \
+	 BIT_MASK_FWFF_PKT_STR_ADDR_V2_8822C)
+#define BIT_SET_FWFF_PKT_STR_ADDR_V2_8822C(x, v)                               \
+	(BIT_CLEAR_FWFF_PKT_STR_ADDR_V2_8822C(x) |                             \
+	 BIT_FWFF_PKT_STR_ADDR_V2_8822C(v))
+
+/* 2 REG_RXPKTNUM_8822C */
+
+#define BIT_SHIFT_PKT_NUM_WOL_V1_8822C 16
+#define BIT_MASK_PKT_NUM_WOL_V1_8822C 0xffff
+#define BIT_PKT_NUM_WOL_V1_8822C(x)                                            \
+	(((x) & BIT_MASK_PKT_NUM_WOL_V1_8822C)                                 \
+	 << BIT_SHIFT_PKT_NUM_WOL_V1_8822C)
+#define BITS_PKT_NUM_WOL_V1_8822C                                              \
+	(BIT_MASK_PKT_NUM_WOL_V1_8822C << BIT_SHIFT_PKT_NUM_WOL_V1_8822C)
+#define BIT_CLEAR_PKT_NUM_WOL_V1_8822C(x) ((x) & (~BITS_PKT_NUM_WOL_V1_8822C))
+#define BIT_GET_PKT_NUM_WOL_V1_8822C(x)                                        \
+	(((x) >> BIT_SHIFT_PKT_NUM_WOL_V1_8822C) &                             \
+	 BIT_MASK_PKT_NUM_WOL_V1_8822C)
+#define BIT_SET_PKT_NUM_WOL_V1_8822C(x, v)                                     \
+	(BIT_CLEAR_PKT_NUM_WOL_V1_8822C(x) | BIT_PKT_NUM_WOL_V1_8822C(v))
+
+#define BIT_SHIFT_RXPKT_NUM_V1_8822C 0
+#define BIT_MASK_RXPKT_NUM_V1_8822C 0xffff
+#define BIT_RXPKT_NUM_V1_8822C(x)                                              \
+	(((x) & BIT_MASK_RXPKT_NUM_V1_8822C) << BIT_SHIFT_RXPKT_NUM_V1_8822C)
+#define BITS_RXPKT_NUM_V1_8822C                                                \
+	(BIT_MASK_RXPKT_NUM_V1_8822C << BIT_SHIFT_RXPKT_NUM_V1_8822C)
+#define BIT_CLEAR_RXPKT_NUM_V1_8822C(x) ((x) & (~BITS_RXPKT_NUM_V1_8822C))
+#define BIT_GET_RXPKT_NUM_V1_8822C(x)                                          \
+	(((x) >> BIT_SHIFT_RXPKT_NUM_V1_8822C) & BIT_MASK_RXPKT_NUM_V1_8822C)
+#define BIT_SET_RXPKT_NUM_V1_8822C(x, v)                                       \
+	(BIT_CLEAR_RXPKT_NUM_V1_8822C(x) | BIT_RXPKT_NUM_V1_8822C(v))
+
+/* 2 REG_RXPKTNUM_TH_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+#define BIT_SHIFT_RXPKT_NUM_TH_8822C 0
+#define BIT_MASK_RXPKT_NUM_TH_8822C 0xff
+#define BIT_RXPKT_NUM_TH_8822C(x)                                              \
+	(((x) & BIT_MASK_RXPKT_NUM_TH_8822C) << BIT_SHIFT_RXPKT_NUM_TH_8822C)
+#define BITS_RXPKT_NUM_TH_8822C                                                \
+	(BIT_MASK_RXPKT_NUM_TH_8822C << BIT_SHIFT_RXPKT_NUM_TH_8822C)
+#define BIT_CLEAR_RXPKT_NUM_TH_8822C(x) ((x) & (~BITS_RXPKT_NUM_TH_8822C))
+#define BIT_GET_RXPKT_NUM_TH_8822C(x)                                          \
+	(((x) >> BIT_SHIFT_RXPKT_NUM_TH_8822C) & BIT_MASK_RXPKT_NUM_TH_8822C)
+#define BIT_SET_RXPKT_NUM_TH_8822C(x, v)                                       \
+	(BIT_CLEAR_RXPKT_NUM_TH_8822C(x) | BIT_RXPKT_NUM_TH_8822C(v))
+
+/* 2 REG_FW_MSG1_8822C */
+
+#define BIT_SHIFT_FW_MSG_REG1_8822C 0
+#define BIT_MASK_FW_MSG_REG1_8822C 0xffffffffL
+#define BIT_FW_MSG_REG1_8822C(x)                                               \
+	(((x) & BIT_MASK_FW_MSG_REG1_8822C) << BIT_SHIFT_FW_MSG_REG1_8822C)
+#define BITS_FW_MSG_REG1_8822C                                                 \
+	(BIT_MASK_FW_MSG_REG1_8822C << BIT_SHIFT_FW_MSG_REG1_8822C)
+#define BIT_CLEAR_FW_MSG_REG1_8822C(x) ((x) & (~BITS_FW_MSG_REG1_8822C))
+#define BIT_GET_FW_MSG_REG1_8822C(x)                                           \
+	(((x) >> BIT_SHIFT_FW_MSG_REG1_8822C) & BIT_MASK_FW_MSG_REG1_8822C)
+#define BIT_SET_FW_MSG_REG1_8822C(x, v)                                        \
+	(BIT_CLEAR_FW_MSG_REG1_8822C(x) | BIT_FW_MSG_REG1_8822C(v))
+
+/* 2 REG_FW_MSG2_8822C */
+
+#define BIT_SHIFT_FW_MSG_REG2_8822C 0
+#define BIT_MASK_FW_MSG_REG2_8822C 0xffffffffL
+#define BIT_FW_MSG_REG2_8822C(x)                                               \
+	(((x) & BIT_MASK_FW_MSG_REG2_8822C) << BIT_SHIFT_FW_MSG_REG2_8822C)
+#define BITS_FW_MSG_REG2_8822C                                                 \
+	(BIT_MASK_FW_MSG_REG2_8822C << BIT_SHIFT_FW_MSG_REG2_8822C)
+#define BIT_CLEAR_FW_MSG_REG2_8822C(x) ((x) & (~BITS_FW_MSG_REG2_8822C))
+#define BIT_GET_FW_MSG_REG2_8822C(x)                                           \
+	(((x) >> BIT_SHIFT_FW_MSG_REG2_8822C) & BIT_MASK_FW_MSG_REG2_8822C)
+#define BIT_SET_FW_MSG_REG2_8822C(x, v)                                        \
+	(BIT_CLEAR_FW_MSG_REG2_8822C(x) | BIT_FW_MSG_REG2_8822C(v))
+
+/* 2 REG_FW_MSG3_8822C */
+
+#define BIT_SHIFT_FW_MSG_REG3_8822C 0
+#define BIT_MASK_FW_MSG_REG3_8822C 0xffffffffL
+#define BIT_FW_MSG_REG3_8822C(x)                                               \
+	(((x) & BIT_MASK_FW_MSG_REG3_8822C) << BIT_SHIFT_FW_MSG_REG3_8822C)
+#define BITS_FW_MSG_REG3_8822C                                                 \
+	(BIT_MASK_FW_MSG_REG3_8822C << BIT_SHIFT_FW_MSG_REG3_8822C)
+#define BIT_CLEAR_FW_MSG_REG3_8822C(x) ((x) & (~BITS_FW_MSG_REG3_8822C))
+#define BIT_GET_FW_MSG_REG3_8822C(x)                                           \
+	(((x) >> BIT_SHIFT_FW_MSG_REG3_8822C) & BIT_MASK_FW_MSG_REG3_8822C)
+#define BIT_SET_FW_MSG_REG3_8822C(x, v)                                        \
+	(BIT_CLEAR_FW_MSG_REG3_8822C(x) | BIT_FW_MSG_REG3_8822C(v))
+
+/* 2 REG_FW_MSG4_8822C */
+
+#define BIT_SHIFT_FW_MSG_REG4_8822C 0
+#define BIT_MASK_FW_MSG_REG4_8822C 0xffffffffL
+#define BIT_FW_MSG_REG4_8822C(x)                                               \
+	(((x) & BIT_MASK_FW_MSG_REG4_8822C) << BIT_SHIFT_FW_MSG_REG4_8822C)
+#define BITS_FW_MSG_REG4_8822C                                                 \
+	(BIT_MASK_FW_MSG_REG4_8822C << BIT_SHIFT_FW_MSG_REG4_8822C)
+#define BIT_CLEAR_FW_MSG_REG4_8822C(x) ((x) & (~BITS_FW_MSG_REG4_8822C))
+#define BIT_GET_FW_MSG_REG4_8822C(x)                                           \
+	(((x) >> BIT_SHIFT_FW_MSG_REG4_8822C) & BIT_MASK_FW_MSG_REG4_8822C)
+#define BIT_SET_FW_MSG_REG4_8822C(x, v)                                        \
+	(BIT_CLEAR_FW_MSG_REG4_8822C(x) | BIT_FW_MSG_REG4_8822C(v))
+
+/* 2 REG_DDMA_CH0SA_8822C */
+
+#define BIT_SHIFT_DDMACH0_SA_8822C 0
+#define BIT_MASK_DDMACH0_SA_8822C 0xffffffffL
+#define BIT_DDMACH0_SA_8822C(x)                                                \
+	(((x) & BIT_MASK_DDMACH0_SA_8822C) << BIT_SHIFT_DDMACH0_SA_8822C)
+#define BITS_DDMACH0_SA_8822C                                                  \
+	(BIT_MASK_DDMACH0_SA_8822C << BIT_SHIFT_DDMACH0_SA_8822C)
+#define BIT_CLEAR_DDMACH0_SA_8822C(x) ((x) & (~BITS_DDMACH0_SA_8822C))
+#define BIT_GET_DDMACH0_SA_8822C(x)                                            \
+	(((x) >> BIT_SHIFT_DDMACH0_SA_8822C) & BIT_MASK_DDMACH0_SA_8822C)
+#define BIT_SET_DDMACH0_SA_8822C(x, v)                                         \
+	(BIT_CLEAR_DDMACH0_SA_8822C(x) | BIT_DDMACH0_SA_8822C(v))
+
+/* 2 REG_DDMA_CH0DA_8822C */
+
+#define BIT_SHIFT_DDMACH0_DA_8822C 0
+#define BIT_MASK_DDMACH0_DA_8822C 0xffffffffL
+#define BIT_DDMACH0_DA_8822C(x)                                                \
+	(((x) & BIT_MASK_DDMACH0_DA_8822C) << BIT_SHIFT_DDMACH0_DA_8822C)
+#define BITS_DDMACH0_DA_8822C                                                  \
+	(BIT_MASK_DDMACH0_DA_8822C << BIT_SHIFT_DDMACH0_DA_8822C)
+#define BIT_CLEAR_DDMACH0_DA_8822C(x) ((x) & (~BITS_DDMACH0_DA_8822C))
+#define BIT_GET_DDMACH0_DA_8822C(x)                                            \
+	(((x) >> BIT_SHIFT_DDMACH0_DA_8822C) & BIT_MASK_DDMACH0_DA_8822C)
+#define BIT_SET_DDMACH0_DA_8822C(x, v)                                         \
+	(BIT_CLEAR_DDMACH0_DA_8822C(x) | BIT_DDMACH0_DA_8822C(v))
+
+/* 2 REG_DDMA_CH0CTRL_8822C */
+#define BIT_DDMACH0_OWN_8822C BIT(31)
+#define BIT_DDMACH0_IDMEM_ERR_8822C BIT(30)
+#define BIT_DDMACH0_CHKSUM_EN_8822C BIT(29)
+#define BIT_DDMACH0_DA_W_DISABLE_8822C BIT(28)
+#define BIT_DDMACH0_CHKSUM_STS_8822C BIT(27)
+#define BIT_DDMACH0_DDMA_MODE_8822C BIT(26)
+#define BIT_DDMACH0_RESET_CHKSUM_STS_8822C BIT(25)
+#define BIT_DDMACH0_CHKSUM_CONT_8822C BIT(24)
+
+#define BIT_SHIFT_DDMACH0_DLEN_8822C 0
+#define BIT_MASK_DDMACH0_DLEN_8822C 0x3ffff
+#define BIT_DDMACH0_DLEN_8822C(x)                                              \
+	(((x) & BIT_MASK_DDMACH0_DLEN_8822C) << BIT_SHIFT_DDMACH0_DLEN_8822C)
+#define BITS_DDMACH0_DLEN_8822C                                                \
+	(BIT_MASK_DDMACH0_DLEN_8822C << BIT_SHIFT_DDMACH0_DLEN_8822C)
+#define BIT_CLEAR_DDMACH0_DLEN_8822C(x) ((x) & (~BITS_DDMACH0_DLEN_8822C))
+#define BIT_GET_DDMACH0_DLEN_8822C(x)                                          \
+	(((x) >> BIT_SHIFT_DDMACH0_DLEN_8822C) & BIT_MASK_DDMACH0_DLEN_8822C)
+#define BIT_SET_DDMACH0_DLEN_8822C(x, v)                                       \
+	(BIT_CLEAR_DDMACH0_DLEN_8822C(x) | BIT_DDMACH0_DLEN_8822C(v))
+
+/* 2 REG_DDMA_CH1SA_8822C */
+
+#define BIT_SHIFT_DDMACH1_SA_8822C 0
+#define BIT_MASK_DDMACH1_SA_8822C 0xffffffffL
+#define BIT_DDMACH1_SA_8822C(x)                                                \
+	(((x) & BIT_MASK_DDMACH1_SA_8822C) << BIT_SHIFT_DDMACH1_SA_8822C)
+#define BITS_DDMACH1_SA_8822C                                                  \
+	(BIT_MASK_DDMACH1_SA_8822C << BIT_SHIFT_DDMACH1_SA_8822C)
+#define BIT_CLEAR_DDMACH1_SA_8822C(x) ((x) & (~BITS_DDMACH1_SA_8822C))
+#define BIT_GET_DDMACH1_SA_8822C(x)                                            \
+	(((x) >> BIT_SHIFT_DDMACH1_SA_8822C) & BIT_MASK_DDMACH1_SA_8822C)
+#define BIT_SET_DDMACH1_SA_8822C(x, v)                                         \
+	(BIT_CLEAR_DDMACH1_SA_8822C(x) | BIT_DDMACH1_SA_8822C(v))
+
+/* 2 REG_DDMA_CH1DA_8822C */
+
+#define BIT_SHIFT_DDMACH1_DA_8822C 0
+#define BIT_MASK_DDMACH1_DA_8822C 0xffffffffL
+#define BIT_DDMACH1_DA_8822C(x)                                                \
+	(((x) & BIT_MASK_DDMACH1_DA_8822C) << BIT_SHIFT_DDMACH1_DA_8822C)
+#define BITS_DDMACH1_DA_8822C                                                  \
+	(BIT_MASK_DDMACH1_DA_8822C << BIT_SHIFT_DDMACH1_DA_8822C)
+#define BIT_CLEAR_DDMACH1_DA_8822C(x) ((x) & (~BITS_DDMACH1_DA_8822C))
+#define BIT_GET_DDMACH1_DA_8822C(x)                                            \
+	(((x) >> BIT_SHIFT_DDMACH1_DA_8822C) & BIT_MASK_DDMACH1_DA_8822C)
+#define BIT_SET_DDMACH1_DA_8822C(x, v)                                         \
+	(BIT_CLEAR_DDMACH1_DA_8822C(x) | BIT_DDMACH1_DA_8822C(v))
+
+/* 2 REG_DDMA_CH1CTRL_8822C */
+#define BIT_DDMACH1_OWN_8822C BIT(31)
+#define BIT_DDMACH1_IDMEM_ERR_8822C BIT(30)
+#define BIT_DDMACH1_CHKSUM_EN_8822C BIT(29)
+#define BIT_DDMACH1_DA_W_DISABLE_8822C BIT(28)
+#define BIT_DDMACH1_CHKSUM_STS_8822C BIT(27)
+#define BIT_DDMACH1_DDMA_MODE_8822C BIT(26)
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+#define BIT_SHIFT_DDMACH1_DLEN_8822C 0
+#define BIT_MASK_DDMACH1_DLEN_8822C 0x3ffff
+#define BIT_DDMACH1_DLEN_8822C(x)                                              \
+	(((x) & BIT_MASK_DDMACH1_DLEN_8822C) << BIT_SHIFT_DDMACH1_DLEN_8822C)
+#define BITS_DDMACH1_DLEN_8822C                                                \
+	(BIT_MASK_DDMACH1_DLEN_8822C << BIT_SHIFT_DDMACH1_DLEN_8822C)
+#define BIT_CLEAR_DDMACH1_DLEN_8822C(x) ((x) & (~BITS_DDMACH1_DLEN_8822C))
+#define BIT_GET_DDMACH1_DLEN_8822C(x)                                          \
+	(((x) >> BIT_SHIFT_DDMACH1_DLEN_8822C) & BIT_MASK_DDMACH1_DLEN_8822C)
+#define BIT_SET_DDMACH1_DLEN_8822C(x, v)                                       \
+	(BIT_CLEAR_DDMACH1_DLEN_8822C(x) | BIT_DDMACH1_DLEN_8822C(v))
+
+/* 2 REG_DDMA_CH2SA_8822C */
+
+#define BIT_SHIFT_DDMACH2_SA_8822C 0
+#define BIT_MASK_DDMACH2_SA_8822C 0xffffffffL
+#define BIT_DDMACH2_SA_8822C(x)                                                \
+	(((x) & BIT_MASK_DDMACH2_SA_8822C) << BIT_SHIFT_DDMACH2_SA_8822C)
+#define BITS_DDMACH2_SA_8822C                                                  \
+	(BIT_MASK_DDMACH2_SA_8822C << BIT_SHIFT_DDMACH2_SA_8822C)
+#define BIT_CLEAR_DDMACH2_SA_8822C(x) ((x) & (~BITS_DDMACH2_SA_8822C))
+#define BIT_GET_DDMACH2_SA_8822C(x)                                            \
+	(((x) >> BIT_SHIFT_DDMACH2_SA_8822C) & BIT_MASK_DDMACH2_SA_8822C)
+#define BIT_SET_DDMACH2_SA_8822C(x, v)                                         \
+	(BIT_CLEAR_DDMACH2_SA_8822C(x) | BIT_DDMACH2_SA_8822C(v))
+
+/* 2 REG_DDMA_CH2DA_8822C */
+
+#define BIT_SHIFT_DDMACH2_DA_8822C 0
+#define BIT_MASK_DDMACH2_DA_8822C 0xffffffffL
+#define BIT_DDMACH2_DA_8822C(x)                                                \
+	(((x) & BIT_MASK_DDMACH2_DA_8822C) << BIT_SHIFT_DDMACH2_DA_8822C)
+#define BITS_DDMACH2_DA_8822C                                                  \
+	(BIT_MASK_DDMACH2_DA_8822C << BIT_SHIFT_DDMACH2_DA_8822C)
+#define BIT_CLEAR_DDMACH2_DA_8822C(x) ((x) & (~BITS_DDMACH2_DA_8822C))
+#define BIT_GET_DDMACH2_DA_8822C(x)                                            \
+	(((x) >> BIT_SHIFT_DDMACH2_DA_8822C) & BIT_MASK_DDMACH2_DA_8822C)
+#define BIT_SET_DDMACH2_DA_8822C(x, v)                                         \
+	(BIT_CLEAR_DDMACH2_DA_8822C(x) | BIT_DDMACH2_DA_8822C(v))
+
+/* 2 REG_DDMA_CH2CTRL_8822C */
+#define BIT_DDMACH2_OWN_8822C BIT(31)
+#define BIT_DDMACH2_IDMEM_ERR_8822C BIT(30)
+#define BIT_DDMACH2_CHKSUM_EN_8822C BIT(29)
+#define BIT_DDMACH2_DA_W_DISABLE_8822C BIT(28)
+#define BIT_DDMACH2_CHKSUM_STS_8822C BIT(27)
+#define BIT_DDMACH2_DDMA_MODE_8822C BIT(26)
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+#define BIT_SHIFT_DDMACH2_DLEN_8822C 0
+#define BIT_MASK_DDMACH2_DLEN_8822C 0x3ffff
+#define BIT_DDMACH2_DLEN_8822C(x)                                              \
+	(((x) & BIT_MASK_DDMACH2_DLEN_8822C) << BIT_SHIFT_DDMACH2_DLEN_8822C)
+#define BITS_DDMACH2_DLEN_8822C                                                \
+	(BIT_MASK_DDMACH2_DLEN_8822C << BIT_SHIFT_DDMACH2_DLEN_8822C)
+#define BIT_CLEAR_DDMACH2_DLEN_8822C(x) ((x) & (~BITS_DDMACH2_DLEN_8822C))
+#define BIT_GET_DDMACH2_DLEN_8822C(x)                                          \
+	(((x) >> BIT_SHIFT_DDMACH2_DLEN_8822C) & BIT_MASK_DDMACH2_DLEN_8822C)
+#define BIT_SET_DDMACH2_DLEN_8822C(x, v)                                       \
+	(BIT_CLEAR_DDMACH2_DLEN_8822C(x) | BIT_DDMACH2_DLEN_8822C(v))
+
+/* 2 REG_DDMA_CH3SA_8822C */
+
+#define BIT_SHIFT_DDMACH3_SA_8822C 0
+#define BIT_MASK_DDMACH3_SA_8822C 0xffffffffL
+#define BIT_DDMACH3_SA_8822C(x)                                                \
+	(((x) & BIT_MASK_DDMACH3_SA_8822C) << BIT_SHIFT_DDMACH3_SA_8822C)
+#define BITS_DDMACH3_SA_8822C                                                  \
+	(BIT_MASK_DDMACH3_SA_8822C << BIT_SHIFT_DDMACH3_SA_8822C)
+#define BIT_CLEAR_DDMACH3_SA_8822C(x) ((x) & (~BITS_DDMACH3_SA_8822C))
+#define BIT_GET_DDMACH3_SA_8822C(x)                                            \
+	(((x) >> BIT_SHIFT_DDMACH3_SA_8822C) & BIT_MASK_DDMACH3_SA_8822C)
+#define BIT_SET_DDMACH3_SA_8822C(x, v)                                         \
+	(BIT_CLEAR_DDMACH3_SA_8822C(x) | BIT_DDMACH3_SA_8822C(v))
+
+/* 2 REG_DDMA_CH3DA_8822C */
+
+#define BIT_SHIFT_DDMACH3_DA_8822C 0
+#define BIT_MASK_DDMACH3_DA_8822C 0xffffffffL
+#define BIT_DDMACH3_DA_8822C(x)                                                \
+	(((x) & BIT_MASK_DDMACH3_DA_8822C) << BIT_SHIFT_DDMACH3_DA_8822C)
+#define BITS_DDMACH3_DA_8822C                                                  \
+	(BIT_MASK_DDMACH3_DA_8822C << BIT_SHIFT_DDMACH3_DA_8822C)
+#define BIT_CLEAR_DDMACH3_DA_8822C(x) ((x) & (~BITS_DDMACH3_DA_8822C))
+#define BIT_GET_DDMACH3_DA_8822C(x)                                            \
+	(((x) >> BIT_SHIFT_DDMACH3_DA_8822C) & BIT_MASK_DDMACH3_DA_8822C)
+#define BIT_SET_DDMACH3_DA_8822C(x, v)                                         \
+	(BIT_CLEAR_DDMACH3_DA_8822C(x) | BIT_DDMACH3_DA_8822C(v))
+
+/* 2 REG_DDMA_CH3CTRL_8822C */
+#define BIT_DDMACH3_OWN_8822C BIT(31)
+#define BIT_DDMACH3_IDMEM_ERR_8822C BIT(30)
+#define BIT_DDMACH3_CHKSUM_EN_8822C BIT(29)
+#define BIT_DDMACH3_DA_W_DISABLE_8822C BIT(28)
+#define BIT_DDMACH3_CHKSUM_STS_8822C BIT(27)
+#define BIT_DDMACH3_DDMA_MODE_8822C BIT(26)
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+#define BIT_SHIFT_DDMACH3_DLEN_8822C 0
+#define BIT_MASK_DDMACH3_DLEN_8822C 0x3ffff
+#define BIT_DDMACH3_DLEN_8822C(x)                                              \
+	(((x) & BIT_MASK_DDMACH3_DLEN_8822C) << BIT_SHIFT_DDMACH3_DLEN_8822C)
+#define BITS_DDMACH3_DLEN_8822C                                                \
+	(BIT_MASK_DDMACH3_DLEN_8822C << BIT_SHIFT_DDMACH3_DLEN_8822C)
+#define BIT_CLEAR_DDMACH3_DLEN_8822C(x) ((x) & (~BITS_DDMACH3_DLEN_8822C))
+#define BIT_GET_DDMACH3_DLEN_8822C(x)                                          \
+	(((x) >> BIT_SHIFT_DDMACH3_DLEN_8822C) & BIT_MASK_DDMACH3_DLEN_8822C)
+#define BIT_SET_DDMACH3_DLEN_8822C(x, v)                                       \
+	(BIT_CLEAR_DDMACH3_DLEN_8822C(x) | BIT_DDMACH3_DLEN_8822C(v))
+
+/* 2 REG_DDMA_CH4SA_8822C */
+
+#define BIT_SHIFT_DDMACH4_SA_8822C 0
+#define BIT_MASK_DDMACH4_SA_8822C 0xffffffffL
+#define BIT_DDMACH4_SA_8822C(x)                                                \
+	(((x) & BIT_MASK_DDMACH4_SA_8822C) << BIT_SHIFT_DDMACH4_SA_8822C)
+#define BITS_DDMACH4_SA_8822C                                                  \
+	(BIT_MASK_DDMACH4_SA_8822C << BIT_SHIFT_DDMACH4_SA_8822C)
+#define BIT_CLEAR_DDMACH4_SA_8822C(x) ((x) & (~BITS_DDMACH4_SA_8822C))
+#define BIT_GET_DDMACH4_SA_8822C(x)                                            \
+	(((x) >> BIT_SHIFT_DDMACH4_SA_8822C) & BIT_MASK_DDMACH4_SA_8822C)
+#define BIT_SET_DDMACH4_SA_8822C(x, v)                                         \
+	(BIT_CLEAR_DDMACH4_SA_8822C(x) | BIT_DDMACH4_SA_8822C(v))
+
+/* 2 REG_DDMA_CH4DA_8822C */
+
+#define BIT_SHIFT_DDMACH4_DA_8822C 0
+#define BIT_MASK_DDMACH4_DA_8822C 0xffffffffL
+#define BIT_DDMACH4_DA_8822C(x)                                                \
+	(((x) & BIT_MASK_DDMACH4_DA_8822C) << BIT_SHIFT_DDMACH4_DA_8822C)
+#define BITS_DDMACH4_DA_8822C                                                  \
+	(BIT_MASK_DDMACH4_DA_8822C << BIT_SHIFT_DDMACH4_DA_8822C)
+#define BIT_CLEAR_DDMACH4_DA_8822C(x) ((x) & (~BITS_DDMACH4_DA_8822C))
+#define BIT_GET_DDMACH4_DA_8822C(x)                                            \
+	(((x) >> BIT_SHIFT_DDMACH4_DA_8822C) & BIT_MASK_DDMACH4_DA_8822C)
+#define BIT_SET_DDMACH4_DA_8822C(x, v)                                         \
+	(BIT_CLEAR_DDMACH4_DA_8822C(x) | BIT_DDMACH4_DA_8822C(v))
+
+/* 2 REG_DDMA_CH4CTRL_8822C */
+#define BIT_DDMACH4_OWN_8822C BIT(31)
+#define BIT_DDMACH4_IDMEM_ERR_8822C BIT(30)
+#define BIT_DDMACH4_CHKSUM_EN_8822C BIT(29)
+#define BIT_DDMACH4_DA_W_DISABLE_8822C BIT(28)
+#define BIT_DDMACH4_CHKSUM_STS_8822C BIT(27)
+#define BIT_DDMACH4_DDMA_MODE_8822C BIT(26)
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+#define BIT_SHIFT_DDMACH4_DLEN_8822C 0
+#define BIT_MASK_DDMACH4_DLEN_8822C 0x3ffff
+#define BIT_DDMACH4_DLEN_8822C(x)                                              \
+	(((x) & BIT_MASK_DDMACH4_DLEN_8822C) << BIT_SHIFT_DDMACH4_DLEN_8822C)
+#define BITS_DDMACH4_DLEN_8822C                                                \
+	(BIT_MASK_DDMACH4_DLEN_8822C << BIT_SHIFT_DDMACH4_DLEN_8822C)
+#define BIT_CLEAR_DDMACH4_DLEN_8822C(x) ((x) & (~BITS_DDMACH4_DLEN_8822C))
+#define BIT_GET_DDMACH4_DLEN_8822C(x)                                          \
+	(((x) >> BIT_SHIFT_DDMACH4_DLEN_8822C) & BIT_MASK_DDMACH4_DLEN_8822C)
+#define BIT_SET_DDMACH4_DLEN_8822C(x, v)                                       \
+	(BIT_CLEAR_DDMACH4_DLEN_8822C(x) | BIT_DDMACH4_DLEN_8822C(v))
+
+/* 2 REG_DDMA_CH5SA_8822C */
+
+#define BIT_SHIFT_DDMACH5_SA_8822C 0
+#define BIT_MASK_DDMACH5_SA_8822C 0xffffffffL
+#define BIT_DDMACH5_SA_8822C(x)                                                \
+	(((x) & BIT_MASK_DDMACH5_SA_8822C) << BIT_SHIFT_DDMACH5_SA_8822C)
+#define BITS_DDMACH5_SA_8822C                                                  \
+	(BIT_MASK_DDMACH5_SA_8822C << BIT_SHIFT_DDMACH5_SA_8822C)
+#define BIT_CLEAR_DDMACH5_SA_8822C(x) ((x) & (~BITS_DDMACH5_SA_8822C))
+#define BIT_GET_DDMACH5_SA_8822C(x)                                            \
+	(((x) >> BIT_SHIFT_DDMACH5_SA_8822C) & BIT_MASK_DDMACH5_SA_8822C)
+#define BIT_SET_DDMACH5_SA_8822C(x, v)                                         \
+	(BIT_CLEAR_DDMACH5_SA_8822C(x) | BIT_DDMACH5_SA_8822C(v))
+
+/* 2 REG_DDMA_CH5DA_8822C */
+
+#define BIT_SHIFT_DDMACH5_DA_8822C 0
+#define BIT_MASK_DDMACH5_DA_8822C 0xffffffffL
+#define BIT_DDMACH5_DA_8822C(x)                                                \
+	(((x) & BIT_MASK_DDMACH5_DA_8822C) << BIT_SHIFT_DDMACH5_DA_8822C)
+#define BITS_DDMACH5_DA_8822C                                                  \
+	(BIT_MASK_DDMACH5_DA_8822C << BIT_SHIFT_DDMACH5_DA_8822C)
+#define BIT_CLEAR_DDMACH5_DA_8822C(x) ((x) & (~BITS_DDMACH5_DA_8822C))
+#define BIT_GET_DDMACH5_DA_8822C(x)                                            \
+	(((x) >> BIT_SHIFT_DDMACH5_DA_8822C) & BIT_MASK_DDMACH5_DA_8822C)
+#define BIT_SET_DDMACH5_DA_8822C(x, v)                                         \
+	(BIT_CLEAR_DDMACH5_DA_8822C(x) | BIT_DDMACH5_DA_8822C(v))
+
+/* 2 REG_DDMA_CH5CTRL_8822C */
+#define BIT_DDMACH5_OWN_8822C BIT(31)
+#define BIT_DDMACH5_IDMEM_ERR_8822C BIT(30)
+#define BIT_DDMACH5_CHKSUM_EN_8822C BIT(29)
+#define BIT_DDMACH5_DA_W_DISABLE_8822C BIT(28)
+#define BIT_DDMACH5_CHKSUM_STS_8822C BIT(27)
+#define BIT_DDMACH5_DDMA_MODE_8822C BIT(26)
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+#define BIT_SHIFT_DDMACH5_DLEN_8822C 0
+#define BIT_MASK_DDMACH5_DLEN_8822C 0x3ffff
+#define BIT_DDMACH5_DLEN_8822C(x)                                              \
+	(((x) & BIT_MASK_DDMACH5_DLEN_8822C) << BIT_SHIFT_DDMACH5_DLEN_8822C)
+#define BITS_DDMACH5_DLEN_8822C                                                \
+	(BIT_MASK_DDMACH5_DLEN_8822C << BIT_SHIFT_DDMACH5_DLEN_8822C)
+#define BIT_CLEAR_DDMACH5_DLEN_8822C(x) ((x) & (~BITS_DDMACH5_DLEN_8822C))
+#define BIT_GET_DDMACH5_DLEN_8822C(x)                                          \
+	(((x) >> BIT_SHIFT_DDMACH5_DLEN_8822C) & BIT_MASK_DDMACH5_DLEN_8822C)
+#define BIT_SET_DDMACH5_DLEN_8822C(x, v)                                       \
+	(BIT_CLEAR_DDMACH5_DLEN_8822C(x) | BIT_DDMACH5_DLEN_8822C(v))
+
+/* 2 REG_DDMA_INT_MSK_8822C */
+#define BIT_DDMACH5_MSK_8822C BIT(5)
+#define BIT_DDMACH4_MSK_8822C BIT(4)
+#define BIT_DDMACH3_MSK_8822C BIT(3)
+#define BIT_DDMACH2_MSK_8822C BIT(2)
+#define BIT_DDMACH1_MSK_8822C BIT(1)
+#define BIT_DDMACH0_MSK_8822C BIT(0)
+
+/* 2 REG_DDMA_CHSTATUS_8822C */
+#define BIT_DDMACH5_BUSY_8822C BIT(5)
+#define BIT_DDMACH4_BUSY_8822C BIT(4)
+#define BIT_DDMACH3_BUSY_8822C BIT(3)
+#define BIT_DDMACH2_BUSY_8822C BIT(2)
+#define BIT_DDMACH1_BUSY_8822C BIT(1)
+#define BIT_DDMACH0_BUSY_8822C BIT(0)
+
+/* 2 REG_DDMA_CHKSUM_8822C */
+
+#define BIT_SHIFT_IDDMA0_CHKSUM_8822C 0
+#define BIT_MASK_IDDMA0_CHKSUM_8822C 0xffff
+#define BIT_IDDMA0_CHKSUM_8822C(x)                                             \
+	(((x) & BIT_MASK_IDDMA0_CHKSUM_8822C) << BIT_SHIFT_IDDMA0_CHKSUM_8822C)
+#define BITS_IDDMA0_CHKSUM_8822C                                               \
+	(BIT_MASK_IDDMA0_CHKSUM_8822C << BIT_SHIFT_IDDMA0_CHKSUM_8822C)
+#define BIT_CLEAR_IDDMA0_CHKSUM_8822C(x) ((x) & (~BITS_IDDMA0_CHKSUM_8822C))
+#define BIT_GET_IDDMA0_CHKSUM_8822C(x)                                         \
+	(((x) >> BIT_SHIFT_IDDMA0_CHKSUM_8822C) & BIT_MASK_IDDMA0_CHKSUM_8822C)
+#define BIT_SET_IDDMA0_CHKSUM_8822C(x, v)                                      \
+	(BIT_CLEAR_IDDMA0_CHKSUM_8822C(x) | BIT_IDDMA0_CHKSUM_8822C(v))
+
+/* 2 REG_DDMA_MONITOR_8822C */
+#define BIT_IDDMA0_PERMU_UNDERFLOW_8822C BIT(14)
+#define BIT_IDDMA0_FIFO_UNDERFLOW_8822C BIT(13)
+#define BIT_IDDMA0_FIFO_OVERFLOW_8822C BIT(12)
+#define BIT_CH5_ERR_8822C BIT(5)
+#define BIT_CH4_ERR_8822C BIT(4)
+#define BIT_CH3_ERR_8822C BIT(3)
+#define BIT_CH2_ERR_8822C BIT(2)
+#define BIT_CH1_ERR_8822C BIT(1)
+#define BIT_CH0_ERR_8822C BIT(0)
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_PCIE_CTRL_8822C */
+#define BIT_PCIEIO_PERSTB_SEL_8822C BIT(31)
+
+#define BIT_SHIFT_PCIE_MAX_RXDMA_8822C 28
+#define BIT_MASK_PCIE_MAX_RXDMA_8822C 0x7
+#define BIT_PCIE_MAX_RXDMA_8822C(x)                                            \
+	(((x) & BIT_MASK_PCIE_MAX_RXDMA_8822C)                                 \
+	 << BIT_SHIFT_PCIE_MAX_RXDMA_8822C)
+#define BITS_PCIE_MAX_RXDMA_8822C                                              \
+	(BIT_MASK_PCIE_MAX_RXDMA_8822C << BIT_SHIFT_PCIE_MAX_RXDMA_8822C)
+#define BIT_CLEAR_PCIE_MAX_RXDMA_8822C(x) ((x) & (~BITS_PCIE_MAX_RXDMA_8822C))
+#define BIT_GET_PCIE_MAX_RXDMA_8822C(x)                                        \
+	(((x) >> BIT_SHIFT_PCIE_MAX_RXDMA_8822C) &                             \
+	 BIT_MASK_PCIE_MAX_RXDMA_8822C)
+#define BIT_SET_PCIE_MAX_RXDMA_8822C(x, v)                                     \
+	(BIT_CLEAR_PCIE_MAX_RXDMA_8822C(x) | BIT_PCIE_MAX_RXDMA_8822C(v))
+
+#define BIT_SHIFT_PCIE_MAX_TXDMA_8822C 24
+#define BIT_MASK_PCIE_MAX_TXDMA_8822C 0x7
+#define BIT_PCIE_MAX_TXDMA_8822C(x)                                            \
+	(((x) & BIT_MASK_PCIE_MAX_TXDMA_8822C)                                 \
+	 << BIT_SHIFT_PCIE_MAX_TXDMA_8822C)
+#define BITS_PCIE_MAX_TXDMA_8822C                                              \
+	(BIT_MASK_PCIE_MAX_TXDMA_8822C << BIT_SHIFT_PCIE_MAX_TXDMA_8822C)
+#define BIT_CLEAR_PCIE_MAX_TXDMA_8822C(x) ((x) & (~BITS_PCIE_MAX_TXDMA_8822C))
+#define BIT_GET_PCIE_MAX_TXDMA_8822C(x)                                        \
+	(((x) >> BIT_SHIFT_PCIE_MAX_TXDMA_8822C) &                             \
+	 BIT_MASK_PCIE_MAX_TXDMA_8822C)
+#define BIT_SET_PCIE_MAX_TXDMA_8822C(x, v)                                     \
+	(BIT_CLEAR_PCIE_MAX_TXDMA_8822C(x) | BIT_PCIE_MAX_TXDMA_8822C(v))
+
+#define BIT_EN_CPL_TIMEOUT_PS_8822C BIT(22)
+#define BIT_REG_TXDMA_FAIL_PS_8822C BIT(21)
+#define BIT_PCIE_RST_TRXDMA_INTF_8822C BIT(20)
+#define BIT_EN_HWENTR_L1_8822C BIT(19)
+#define BIT_EN_ADV_CLKGATE_8822C BIT(18)
+#define BIT_PCIE_EN_SWENT_L23_8822C BIT(17)
+#define BIT_PCIE_EN_HWEXT_L1_8822C BIT(16)
+#define BIT_RX_CLOSE_EN_8822C BIT(15)
+#define BIT_STOP_BCNQ_8822C BIT(14)
+#define BIT_STOP_MGQ_8822C BIT(13)
+#define BIT_STOP_VOQ_8822C BIT(12)
+#define BIT_STOP_VIQ_8822C BIT(11)
+#define BIT_STOP_BEQ_8822C BIT(10)
+#define BIT_STOP_BKQ_8822C BIT(9)
+#define BIT_STOP_RXQ_8822C BIT(8)
+#define BIT_STOP_HI7Q_8822C BIT(7)
+#define BIT_STOP_HI6Q_8822C BIT(6)
+#define BIT_STOP_HI5Q_8822C BIT(5)
+#define BIT_STOP_HI4Q_8822C BIT(4)
+#define BIT_STOP_HI3Q_8822C BIT(3)
+#define BIT_STOP_HI2Q_8822C BIT(2)
+#define BIT_STOP_HI1Q_8822C BIT(1)
+#define BIT_STOP_HI0Q_8822C BIT(0)
+
+/* 2 REG_INT_MIG_8822C */
+
+#define BIT_SHIFT_TRXCOUNTER_MATCH_8822C 24
+#define BIT_MASK_TRXCOUNTER_MATCH_8822C 0xff
+#define BIT_TRXCOUNTER_MATCH_8822C(x)                                          \
+	(((x) & BIT_MASK_TRXCOUNTER_MATCH_8822C)                               \
+	 << BIT_SHIFT_TRXCOUNTER_MATCH_8822C)
+#define BITS_TRXCOUNTER_MATCH_8822C                                            \
+	(BIT_MASK_TRXCOUNTER_MATCH_8822C << BIT_SHIFT_TRXCOUNTER_MATCH_8822C)
+#define BIT_CLEAR_TRXCOUNTER_MATCH_8822C(x)                                    \
+	((x) & (~BITS_TRXCOUNTER_MATCH_8822C))
+#define BIT_GET_TRXCOUNTER_MATCH_8822C(x)                                      \
+	(((x) >> BIT_SHIFT_TRXCOUNTER_MATCH_8822C) &                           \
+	 BIT_MASK_TRXCOUNTER_MATCH_8822C)
+#define BIT_SET_TRXCOUNTER_MATCH_8822C(x, v)                                   \
+	(BIT_CLEAR_TRXCOUNTER_MATCH_8822C(x) | BIT_TRXCOUNTER_MATCH_8822C(v))
+
+#define BIT_SHIFT_TRXTIMER_MATCH_8822C 16
+#define BIT_MASK_TRXTIMER_MATCH_8822C 0xff
+#define BIT_TRXTIMER_MATCH_8822C(x)                                            \
+	(((x) & BIT_MASK_TRXTIMER_MATCH_8822C)                                 \
+	 << BIT_SHIFT_TRXTIMER_MATCH_8822C)
+#define BITS_TRXTIMER_MATCH_8822C                                              \
+	(BIT_MASK_TRXTIMER_MATCH_8822C << BIT_SHIFT_TRXTIMER_MATCH_8822C)
+#define BIT_CLEAR_TRXTIMER_MATCH_8822C(x) ((x) & (~BITS_TRXTIMER_MATCH_8822C))
+#define BIT_GET_TRXTIMER_MATCH_8822C(x)                                        \
+	(((x) >> BIT_SHIFT_TRXTIMER_MATCH_8822C) &                             \
+	 BIT_MASK_TRXTIMER_MATCH_8822C)
+#define BIT_SET_TRXTIMER_MATCH_8822C(x, v)                                     \
+	(BIT_CLEAR_TRXTIMER_MATCH_8822C(x) | BIT_TRXTIMER_MATCH_8822C(v))
+
+#define BIT_SHIFT_TRXTIMER_UNIT_8822C 0
+#define BIT_MASK_TRXTIMER_UNIT_8822C 0x3
+#define BIT_TRXTIMER_UNIT_8822C(x)                                             \
+	(((x) & BIT_MASK_TRXTIMER_UNIT_8822C) << BIT_SHIFT_TRXTIMER_UNIT_8822C)
+#define BITS_TRXTIMER_UNIT_8822C                                               \
+	(BIT_MASK_TRXTIMER_UNIT_8822C << BIT_SHIFT_TRXTIMER_UNIT_8822C)
+#define BIT_CLEAR_TRXTIMER_UNIT_8822C(x) ((x) & (~BITS_TRXTIMER_UNIT_8822C))
+#define BIT_GET_TRXTIMER_UNIT_8822C(x)                                         \
+	(((x) >> BIT_SHIFT_TRXTIMER_UNIT_8822C) & BIT_MASK_TRXTIMER_UNIT_8822C)
+#define BIT_SET_TRXTIMER_UNIT_8822C(x, v)                                      \
+	(BIT_CLEAR_TRXTIMER_UNIT_8822C(x) | BIT_TRXTIMER_UNIT_8822C(v))
+
+/* 2 REG_BCNQ_TXBD_DESA_8822C */
+
+#define BIT_SHIFT_BCNQ_TXBD_DESA_8822C 0
+#define BIT_MASK_BCNQ_TXBD_DESA_8822C 0xffffffffffffffffL
+#define BIT_BCNQ_TXBD_DESA_8822C(x)                                            \
+	(((x) & BIT_MASK_BCNQ_TXBD_DESA_8822C)                                 \
+	 << BIT_SHIFT_BCNQ_TXBD_DESA_8822C)
+#define BITS_BCNQ_TXBD_DESA_8822C                                              \
+	(BIT_MASK_BCNQ_TXBD_DESA_8822C << BIT_SHIFT_BCNQ_TXBD_DESA_8822C)
+#define BIT_CLEAR_BCNQ_TXBD_DESA_8822C(x) ((x) & (~BITS_BCNQ_TXBD_DESA_8822C))
+#define BIT_GET_BCNQ_TXBD_DESA_8822C(x)                                        \
+	(((x) >> BIT_SHIFT_BCNQ_TXBD_DESA_8822C) &                             \
+	 BIT_MASK_BCNQ_TXBD_DESA_8822C)
+#define BIT_SET_BCNQ_TXBD_DESA_8822C(x, v)                                     \
+	(BIT_CLEAR_BCNQ_TXBD_DESA_8822C(x) | BIT_BCNQ_TXBD_DESA_8822C(v))
+
+/* 2 REG_MGQ_TXBD_DESA_8822C */
+
+#define BIT_SHIFT_MGQ_TXBD_DESA_8822C 0
+#define BIT_MASK_MGQ_TXBD_DESA_8822C 0xffffffffffffffffL
+#define BIT_MGQ_TXBD_DESA_8822C(x)                                             \
+	(((x) & BIT_MASK_MGQ_TXBD_DESA_8822C) << BIT_SHIFT_MGQ_TXBD_DESA_8822C)
+#define BITS_MGQ_TXBD_DESA_8822C                                               \
+	(BIT_MASK_MGQ_TXBD_DESA_8822C << BIT_SHIFT_MGQ_TXBD_DESA_8822C)
+#define BIT_CLEAR_MGQ_TXBD_DESA_8822C(x) ((x) & (~BITS_MGQ_TXBD_DESA_8822C))
+#define BIT_GET_MGQ_TXBD_DESA_8822C(x)                                         \
+	(((x) >> BIT_SHIFT_MGQ_TXBD_DESA_8822C) & BIT_MASK_MGQ_TXBD_DESA_8822C)
+#define BIT_SET_MGQ_TXBD_DESA_8822C(x, v)                                      \
+	(BIT_CLEAR_MGQ_TXBD_DESA_8822C(x) | BIT_MGQ_TXBD_DESA_8822C(v))
+
+/* 2 REG_VOQ_TXBD_DESA_8822C */
+
+#define BIT_SHIFT_VOQ_TXBD_DESA_8822C 0
+#define BIT_MASK_VOQ_TXBD_DESA_8822C 0xffffffffffffffffL
+#define BIT_VOQ_TXBD_DESA_8822C(x)                                             \
+	(((x) & BIT_MASK_VOQ_TXBD_DESA_8822C) << BIT_SHIFT_VOQ_TXBD_DESA_8822C)
+#define BITS_VOQ_TXBD_DESA_8822C                                               \
+	(BIT_MASK_VOQ_TXBD_DESA_8822C << BIT_SHIFT_VOQ_TXBD_DESA_8822C)
+#define BIT_CLEAR_VOQ_TXBD_DESA_8822C(x) ((x) & (~BITS_VOQ_TXBD_DESA_8822C))
+#define BIT_GET_VOQ_TXBD_DESA_8822C(x)                                         \
+	(((x) >> BIT_SHIFT_VOQ_TXBD_DESA_8822C) & BIT_MASK_VOQ_TXBD_DESA_8822C)
+#define BIT_SET_VOQ_TXBD_DESA_8822C(x, v)                                      \
+	(BIT_CLEAR_VOQ_TXBD_DESA_8822C(x) | BIT_VOQ_TXBD_DESA_8822C(v))
+
+/* 2 REG_VIQ_TXBD_DESA_8822C */
+
+#define BIT_SHIFT_VIQ_TXBD_DESA_8822C 0
+#define BIT_MASK_VIQ_TXBD_DESA_8822C 0xffffffffffffffffL
+#define BIT_VIQ_TXBD_DESA_8822C(x)                                             \
+	(((x) & BIT_MASK_VIQ_TXBD_DESA_8822C) << BIT_SHIFT_VIQ_TXBD_DESA_8822C)
+#define BITS_VIQ_TXBD_DESA_8822C                                               \
+	(BIT_MASK_VIQ_TXBD_DESA_8822C << BIT_SHIFT_VIQ_TXBD_DESA_8822C)
+#define BIT_CLEAR_VIQ_TXBD_DESA_8822C(x) ((x) & (~BITS_VIQ_TXBD_DESA_8822C))
+#define BIT_GET_VIQ_TXBD_DESA_8822C(x)                                         \
+	(((x) >> BIT_SHIFT_VIQ_TXBD_DESA_8822C) & BIT_MASK_VIQ_TXBD_DESA_8822C)
+#define BIT_SET_VIQ_TXBD_DESA_8822C(x, v)                                      \
+	(BIT_CLEAR_VIQ_TXBD_DESA_8822C(x) | BIT_VIQ_TXBD_DESA_8822C(v))
+
+/* 2 REG_BEQ_TXBD_DESA_8822C */
+
+#define BIT_SHIFT_BEQ_TXBD_DESA_8822C 0
+#define BIT_MASK_BEQ_TXBD_DESA_8822C 0xffffffffffffffffL
+#define BIT_BEQ_TXBD_DESA_8822C(x)                                             \
+	(((x) & BIT_MASK_BEQ_TXBD_DESA_8822C) << BIT_SHIFT_BEQ_TXBD_DESA_8822C)
+#define BITS_BEQ_TXBD_DESA_8822C                                               \
+	(BIT_MASK_BEQ_TXBD_DESA_8822C << BIT_SHIFT_BEQ_TXBD_DESA_8822C)
+#define BIT_CLEAR_BEQ_TXBD_DESA_8822C(x) ((x) & (~BITS_BEQ_TXBD_DESA_8822C))
+#define BIT_GET_BEQ_TXBD_DESA_8822C(x)                                         \
+	(((x) >> BIT_SHIFT_BEQ_TXBD_DESA_8822C) & BIT_MASK_BEQ_TXBD_DESA_8822C)
+#define BIT_SET_BEQ_TXBD_DESA_8822C(x, v)                                      \
+	(BIT_CLEAR_BEQ_TXBD_DESA_8822C(x) | BIT_BEQ_TXBD_DESA_8822C(v))
+
+/* 2 REG_BKQ_TXBD_DESA_8822C */
+
+#define BIT_SHIFT_BKQ_TXBD_DESA_8822C 0
+#define BIT_MASK_BKQ_TXBD_DESA_8822C 0xffffffffffffffffL
+#define BIT_BKQ_TXBD_DESA_8822C(x)                                             \
+	(((x) & BIT_MASK_BKQ_TXBD_DESA_8822C) << BIT_SHIFT_BKQ_TXBD_DESA_8822C)
+#define BITS_BKQ_TXBD_DESA_8822C                                               \
+	(BIT_MASK_BKQ_TXBD_DESA_8822C << BIT_SHIFT_BKQ_TXBD_DESA_8822C)
+#define BIT_CLEAR_BKQ_TXBD_DESA_8822C(x) ((x) & (~BITS_BKQ_TXBD_DESA_8822C))
+#define BIT_GET_BKQ_TXBD_DESA_8822C(x)                                         \
+	(((x) >> BIT_SHIFT_BKQ_TXBD_DESA_8822C) & BIT_MASK_BKQ_TXBD_DESA_8822C)
+#define BIT_SET_BKQ_TXBD_DESA_8822C(x, v)                                      \
+	(BIT_CLEAR_BKQ_TXBD_DESA_8822C(x) | BIT_BKQ_TXBD_DESA_8822C(v))
+
+/* 2 REG_RXQ_RXBD_DESA_8822C */
+
+#define BIT_SHIFT_RXQ_RXBD_DESA_8822C 0
+#define BIT_MASK_RXQ_RXBD_DESA_8822C 0xffffffffffffffffL
+#define BIT_RXQ_RXBD_DESA_8822C(x)                                             \
+	(((x) & BIT_MASK_RXQ_RXBD_DESA_8822C) << BIT_SHIFT_RXQ_RXBD_DESA_8822C)
+#define BITS_RXQ_RXBD_DESA_8822C                                               \
+	(BIT_MASK_RXQ_RXBD_DESA_8822C << BIT_SHIFT_RXQ_RXBD_DESA_8822C)
+#define BIT_CLEAR_RXQ_RXBD_DESA_8822C(x) ((x) & (~BITS_RXQ_RXBD_DESA_8822C))
+#define BIT_GET_RXQ_RXBD_DESA_8822C(x)                                         \
+	(((x) >> BIT_SHIFT_RXQ_RXBD_DESA_8822C) & BIT_MASK_RXQ_RXBD_DESA_8822C)
+#define BIT_SET_RXQ_RXBD_DESA_8822C(x, v)                                      \
+	(BIT_CLEAR_RXQ_RXBD_DESA_8822C(x) | BIT_RXQ_RXBD_DESA_8822C(v))
+
+/* 2 REG_HI0Q_TXBD_DESA_8822C */
+
+#define BIT_SHIFT_HI0Q_TXBD_DESA_8822C 0
+#define BIT_MASK_HI0Q_TXBD_DESA_8822C 0xffffffffffffffffL
+#define BIT_HI0Q_TXBD_DESA_8822C(x)                                            \
+	(((x) & BIT_MASK_HI0Q_TXBD_DESA_8822C)                                 \
+	 << BIT_SHIFT_HI0Q_TXBD_DESA_8822C)
+#define BITS_HI0Q_TXBD_DESA_8822C                                              \
+	(BIT_MASK_HI0Q_TXBD_DESA_8822C << BIT_SHIFT_HI0Q_TXBD_DESA_8822C)
+#define BIT_CLEAR_HI0Q_TXBD_DESA_8822C(x) ((x) & (~BITS_HI0Q_TXBD_DESA_8822C))
+#define BIT_GET_HI0Q_TXBD_DESA_8822C(x)                                        \
+	(((x) >> BIT_SHIFT_HI0Q_TXBD_DESA_8822C) &                             \
+	 BIT_MASK_HI0Q_TXBD_DESA_8822C)
+#define BIT_SET_HI0Q_TXBD_DESA_8822C(x, v)                                     \
+	(BIT_CLEAR_HI0Q_TXBD_DESA_8822C(x) | BIT_HI0Q_TXBD_DESA_8822C(v))
+
+/* 2 REG_HI1Q_TXBD_DESA_8822C */
+
+#define BIT_SHIFT_HI1Q_TXBD_DESA_8822C 0
+#define BIT_MASK_HI1Q_TXBD_DESA_8822C 0xffffffffffffffffL
+#define BIT_HI1Q_TXBD_DESA_8822C(x)                                            \
+	(((x) & BIT_MASK_HI1Q_TXBD_DESA_8822C)                                 \
+	 << BIT_SHIFT_HI1Q_TXBD_DESA_8822C)
+#define BITS_HI1Q_TXBD_DESA_8822C                                              \
+	(BIT_MASK_HI1Q_TXBD_DESA_8822C << BIT_SHIFT_HI1Q_TXBD_DESA_8822C)
+#define BIT_CLEAR_HI1Q_TXBD_DESA_8822C(x) ((x) & (~BITS_HI1Q_TXBD_DESA_8822C))
+#define BIT_GET_HI1Q_TXBD_DESA_8822C(x)                                        \
+	(((x) >> BIT_SHIFT_HI1Q_TXBD_DESA_8822C) &                             \
+	 BIT_MASK_HI1Q_TXBD_DESA_8822C)
+#define BIT_SET_HI1Q_TXBD_DESA_8822C(x, v)                                     \
+	(BIT_CLEAR_HI1Q_TXBD_DESA_8822C(x) | BIT_HI1Q_TXBD_DESA_8822C(v))
+
+/* 2 REG_HI2Q_TXBD_DESA_8822C */
+
+#define BIT_SHIFT_HI2Q_TXBD_DESA_8822C 0
+#define BIT_MASK_HI2Q_TXBD_DESA_8822C 0xffffffffffffffffL
+#define BIT_HI2Q_TXBD_DESA_8822C(x)                                            \
+	(((x) & BIT_MASK_HI2Q_TXBD_DESA_8822C)                                 \
+	 << BIT_SHIFT_HI2Q_TXBD_DESA_8822C)
+#define BITS_HI2Q_TXBD_DESA_8822C                                              \
+	(BIT_MASK_HI2Q_TXBD_DESA_8822C << BIT_SHIFT_HI2Q_TXBD_DESA_8822C)
+#define BIT_CLEAR_HI2Q_TXBD_DESA_8822C(x) ((x) & (~BITS_HI2Q_TXBD_DESA_8822C))
+#define BIT_GET_HI2Q_TXBD_DESA_8822C(x)                                        \
+	(((x) >> BIT_SHIFT_HI2Q_TXBD_DESA_8822C) &                             \
+	 BIT_MASK_HI2Q_TXBD_DESA_8822C)
+#define BIT_SET_HI2Q_TXBD_DESA_8822C(x, v)                                     \
+	(BIT_CLEAR_HI2Q_TXBD_DESA_8822C(x) | BIT_HI2Q_TXBD_DESA_8822C(v))
+
+/* 2 REG_HI3Q_TXBD_DESA_8822C */
+
+#define BIT_SHIFT_HI3Q_TXBD_DESA_8822C 0
+#define BIT_MASK_HI3Q_TXBD_DESA_8822C 0xffffffffffffffffL
+#define BIT_HI3Q_TXBD_DESA_8822C(x)                                            \
+	(((x) & BIT_MASK_HI3Q_TXBD_DESA_8822C)                                 \
+	 << BIT_SHIFT_HI3Q_TXBD_DESA_8822C)
+#define BITS_HI3Q_TXBD_DESA_8822C                                              \
+	(BIT_MASK_HI3Q_TXBD_DESA_8822C << BIT_SHIFT_HI3Q_TXBD_DESA_8822C)
+#define BIT_CLEAR_HI3Q_TXBD_DESA_8822C(x) ((x) & (~BITS_HI3Q_TXBD_DESA_8822C))
+#define BIT_GET_HI3Q_TXBD_DESA_8822C(x)                                        \
+	(((x) >> BIT_SHIFT_HI3Q_TXBD_DESA_8822C) &                             \
+	 BIT_MASK_HI3Q_TXBD_DESA_8822C)
+#define BIT_SET_HI3Q_TXBD_DESA_8822C(x, v)                                     \
+	(BIT_CLEAR_HI3Q_TXBD_DESA_8822C(x) | BIT_HI3Q_TXBD_DESA_8822C(v))
+
+/* 2 REG_HI4Q_TXBD_DESA_8822C */
+
+#define BIT_SHIFT_HI4Q_TXBD_DESA_8822C 0
+#define BIT_MASK_HI4Q_TXBD_DESA_8822C 0xffffffffffffffffL
+#define BIT_HI4Q_TXBD_DESA_8822C(x)                                            \
+	(((x) & BIT_MASK_HI4Q_TXBD_DESA_8822C)                                 \
+	 << BIT_SHIFT_HI4Q_TXBD_DESA_8822C)
+#define BITS_HI4Q_TXBD_DESA_8822C                                              \
+	(BIT_MASK_HI4Q_TXBD_DESA_8822C << BIT_SHIFT_HI4Q_TXBD_DESA_8822C)
+#define BIT_CLEAR_HI4Q_TXBD_DESA_8822C(x) ((x) & (~BITS_HI4Q_TXBD_DESA_8822C))
+#define BIT_GET_HI4Q_TXBD_DESA_8822C(x)                                        \
+	(((x) >> BIT_SHIFT_HI4Q_TXBD_DESA_8822C) &                             \
+	 BIT_MASK_HI4Q_TXBD_DESA_8822C)
+#define BIT_SET_HI4Q_TXBD_DESA_8822C(x, v)                                     \
+	(BIT_CLEAR_HI4Q_TXBD_DESA_8822C(x) | BIT_HI4Q_TXBD_DESA_8822C(v))
+
+/* 2 REG_HI5Q_TXBD_DESA_8822C */
+
+#define BIT_SHIFT_HI5Q_TXBD_DESA_8822C 0
+#define BIT_MASK_HI5Q_TXBD_DESA_8822C 0xffffffffffffffffL
+#define BIT_HI5Q_TXBD_DESA_8822C(x)                                            \
+	(((x) & BIT_MASK_HI5Q_TXBD_DESA_8822C)                                 \
+	 << BIT_SHIFT_HI5Q_TXBD_DESA_8822C)
+#define BITS_HI5Q_TXBD_DESA_8822C                                              \
+	(BIT_MASK_HI5Q_TXBD_DESA_8822C << BIT_SHIFT_HI5Q_TXBD_DESA_8822C)
+#define BIT_CLEAR_HI5Q_TXBD_DESA_8822C(x) ((x) & (~BITS_HI5Q_TXBD_DESA_8822C))
+#define BIT_GET_HI5Q_TXBD_DESA_8822C(x)                                        \
+	(((x) >> BIT_SHIFT_HI5Q_TXBD_DESA_8822C) &                             \
+	 BIT_MASK_HI5Q_TXBD_DESA_8822C)
+#define BIT_SET_HI5Q_TXBD_DESA_8822C(x, v)                                     \
+	(BIT_CLEAR_HI5Q_TXBD_DESA_8822C(x) | BIT_HI5Q_TXBD_DESA_8822C(v))
+
+/* 2 REG_HI6Q_TXBD_DESA_8822C */
+
+#define BIT_SHIFT_HI6Q_TXBD_DESA_8822C 0
+#define BIT_MASK_HI6Q_TXBD_DESA_8822C 0xffffffffffffffffL
+#define BIT_HI6Q_TXBD_DESA_8822C(x)                                            \
+	(((x) & BIT_MASK_HI6Q_TXBD_DESA_8822C)                                 \
+	 << BIT_SHIFT_HI6Q_TXBD_DESA_8822C)
+#define BITS_HI6Q_TXBD_DESA_8822C                                              \
+	(BIT_MASK_HI6Q_TXBD_DESA_8822C << BIT_SHIFT_HI6Q_TXBD_DESA_8822C)
+#define BIT_CLEAR_HI6Q_TXBD_DESA_8822C(x) ((x) & (~BITS_HI6Q_TXBD_DESA_8822C))
+#define BIT_GET_HI6Q_TXBD_DESA_8822C(x)                                        \
+	(((x) >> BIT_SHIFT_HI6Q_TXBD_DESA_8822C) &                             \
+	 BIT_MASK_HI6Q_TXBD_DESA_8822C)
+#define BIT_SET_HI6Q_TXBD_DESA_8822C(x, v)                                     \
+	(BIT_CLEAR_HI6Q_TXBD_DESA_8822C(x) | BIT_HI6Q_TXBD_DESA_8822C(v))
+
+/* 2 REG_HI7Q_TXBD_DESA_8822C */
+
+#define BIT_SHIFT_HI7Q_TXBD_DESA_8822C 0
+#define BIT_MASK_HI7Q_TXBD_DESA_8822C 0xffffffffffffffffL
+#define BIT_HI7Q_TXBD_DESA_8822C(x)                                            \
+	(((x) & BIT_MASK_HI7Q_TXBD_DESA_8822C)                                 \
+	 << BIT_SHIFT_HI7Q_TXBD_DESA_8822C)
+#define BITS_HI7Q_TXBD_DESA_8822C                                              \
+	(BIT_MASK_HI7Q_TXBD_DESA_8822C << BIT_SHIFT_HI7Q_TXBD_DESA_8822C)
+#define BIT_CLEAR_HI7Q_TXBD_DESA_8822C(x) ((x) & (~BITS_HI7Q_TXBD_DESA_8822C))
+#define BIT_GET_HI7Q_TXBD_DESA_8822C(x)                                        \
+	(((x) >> BIT_SHIFT_HI7Q_TXBD_DESA_8822C) &                             \
+	 BIT_MASK_HI7Q_TXBD_DESA_8822C)
+#define BIT_SET_HI7Q_TXBD_DESA_8822C(x, v)                                     \
+	(BIT_CLEAR_HI7Q_TXBD_DESA_8822C(x) | BIT_HI7Q_TXBD_DESA_8822C(v))
+
+/* 2 REG_MGQ_TXBD_NUM_8822C */
+#define BIT_PCIE_MGQ_FLAG_8822C BIT(14)
+
+#define BIT_SHIFT_MGQ_DESC_MODE_8822C 12
+#define BIT_MASK_MGQ_DESC_MODE_8822C 0x3
+#define BIT_MGQ_DESC_MODE_8822C(x)                                             \
+	(((x) & BIT_MASK_MGQ_DESC_MODE_8822C) << BIT_SHIFT_MGQ_DESC_MODE_8822C)
+#define BITS_MGQ_DESC_MODE_8822C                                               \
+	(BIT_MASK_MGQ_DESC_MODE_8822C << BIT_SHIFT_MGQ_DESC_MODE_8822C)
+#define BIT_CLEAR_MGQ_DESC_MODE_8822C(x) ((x) & (~BITS_MGQ_DESC_MODE_8822C))
+#define BIT_GET_MGQ_DESC_MODE_8822C(x)                                         \
+	(((x) >> BIT_SHIFT_MGQ_DESC_MODE_8822C) & BIT_MASK_MGQ_DESC_MODE_8822C)
+#define BIT_SET_MGQ_DESC_MODE_8822C(x, v)                                      \
+	(BIT_CLEAR_MGQ_DESC_MODE_8822C(x) | BIT_MGQ_DESC_MODE_8822C(v))
+
+#define BIT_SHIFT_MGQ_DESC_NUM_8822C 0
+#define BIT_MASK_MGQ_DESC_NUM_8822C 0xfff
+#define BIT_MGQ_DESC_NUM_8822C(x)                                              \
+	(((x) & BIT_MASK_MGQ_DESC_NUM_8822C) << BIT_SHIFT_MGQ_DESC_NUM_8822C)
+#define BITS_MGQ_DESC_NUM_8822C                                                \
+	(BIT_MASK_MGQ_DESC_NUM_8822C << BIT_SHIFT_MGQ_DESC_NUM_8822C)
+#define BIT_CLEAR_MGQ_DESC_NUM_8822C(x) ((x) & (~BITS_MGQ_DESC_NUM_8822C))
+#define BIT_GET_MGQ_DESC_NUM_8822C(x)                                          \
+	(((x) >> BIT_SHIFT_MGQ_DESC_NUM_8822C) & BIT_MASK_MGQ_DESC_NUM_8822C)
+#define BIT_SET_MGQ_DESC_NUM_8822C(x, v)                                       \
+	(BIT_CLEAR_MGQ_DESC_NUM_8822C(x) | BIT_MGQ_DESC_NUM_8822C(v))
+
+/* 2 REG_RX_RXBD_NUM_8822C */
+#define BIT_SYS_32_64_8822C BIT(15)
+
+#define BIT_SHIFT_BCNQ_DESC_MODE_8822C 13
+#define BIT_MASK_BCNQ_DESC_MODE_8822C 0x3
+#define BIT_BCNQ_DESC_MODE_8822C(x)                                            \
+	(((x) & BIT_MASK_BCNQ_DESC_MODE_8822C)                                 \
+	 << BIT_SHIFT_BCNQ_DESC_MODE_8822C)
+#define BITS_BCNQ_DESC_MODE_8822C                                              \
+	(BIT_MASK_BCNQ_DESC_MODE_8822C << BIT_SHIFT_BCNQ_DESC_MODE_8822C)
+#define BIT_CLEAR_BCNQ_DESC_MODE_8822C(x) ((x) & (~BITS_BCNQ_DESC_MODE_8822C))
+#define BIT_GET_BCNQ_DESC_MODE_8822C(x)                                        \
+	(((x) >> BIT_SHIFT_BCNQ_DESC_MODE_8822C) &                             \
+	 BIT_MASK_BCNQ_DESC_MODE_8822C)
+#define BIT_SET_BCNQ_DESC_MODE_8822C(x, v)                                     \
+	(BIT_CLEAR_BCNQ_DESC_MODE_8822C(x) | BIT_BCNQ_DESC_MODE_8822C(v))
+
+#define BIT_PCIE_BCNQ_FLAG_8822C BIT(12)
+
+#define BIT_SHIFT_RXQ_DESC_NUM_8822C 0
+#define BIT_MASK_RXQ_DESC_NUM_8822C 0xfff
+#define BIT_RXQ_DESC_NUM_8822C(x)                                              \
+	(((x) & BIT_MASK_RXQ_DESC_NUM_8822C) << BIT_SHIFT_RXQ_DESC_NUM_8822C)
+#define BITS_RXQ_DESC_NUM_8822C                                                \
+	(BIT_MASK_RXQ_DESC_NUM_8822C << BIT_SHIFT_RXQ_DESC_NUM_8822C)
+#define BIT_CLEAR_RXQ_DESC_NUM_8822C(x) ((x) & (~BITS_RXQ_DESC_NUM_8822C))
+#define BIT_GET_RXQ_DESC_NUM_8822C(x)                                          \
+	(((x) >> BIT_SHIFT_RXQ_DESC_NUM_8822C) & BIT_MASK_RXQ_DESC_NUM_8822C)
+#define BIT_SET_RXQ_DESC_NUM_8822C(x, v)                                       \
+	(BIT_CLEAR_RXQ_DESC_NUM_8822C(x) | BIT_RXQ_DESC_NUM_8822C(v))
+
+/* 2 REG_VOQ_TXBD_NUM_8822C */
+#define BIT_PCIE_VOQ_FLAG_8822C BIT(14)
+
+#define BIT_SHIFT_VOQ_DESC_MODE_8822C 12
+#define BIT_MASK_VOQ_DESC_MODE_8822C 0x3
+#define BIT_VOQ_DESC_MODE_8822C(x)                                             \
+	(((x) & BIT_MASK_VOQ_DESC_MODE_8822C) << BIT_SHIFT_VOQ_DESC_MODE_8822C)
+#define BITS_VOQ_DESC_MODE_8822C                                               \
+	(BIT_MASK_VOQ_DESC_MODE_8822C << BIT_SHIFT_VOQ_DESC_MODE_8822C)
+#define BIT_CLEAR_VOQ_DESC_MODE_8822C(x) ((x) & (~BITS_VOQ_DESC_MODE_8822C))
+#define BIT_GET_VOQ_DESC_MODE_8822C(x)                                         \
+	(((x) >> BIT_SHIFT_VOQ_DESC_MODE_8822C) & BIT_MASK_VOQ_DESC_MODE_8822C)
+#define BIT_SET_VOQ_DESC_MODE_8822C(x, v)                                      \
+	(BIT_CLEAR_VOQ_DESC_MODE_8822C(x) | BIT_VOQ_DESC_MODE_8822C(v))
+
+#define BIT_SHIFT_VOQ_DESC_NUM_8822C 0
+#define BIT_MASK_VOQ_DESC_NUM_8822C 0xfff
+#define BIT_VOQ_DESC_NUM_8822C(x)                                              \
+	(((x) & BIT_MASK_VOQ_DESC_NUM_8822C) << BIT_SHIFT_VOQ_DESC_NUM_8822C)
+#define BITS_VOQ_DESC_NUM_8822C                                                \
+	(BIT_MASK_VOQ_DESC_NUM_8822C << BIT_SHIFT_VOQ_DESC_NUM_8822C)
+#define BIT_CLEAR_VOQ_DESC_NUM_8822C(x) ((x) & (~BITS_VOQ_DESC_NUM_8822C))
+#define BIT_GET_VOQ_DESC_NUM_8822C(x)                                          \
+	(((x) >> BIT_SHIFT_VOQ_DESC_NUM_8822C) & BIT_MASK_VOQ_DESC_NUM_8822C)
+#define BIT_SET_VOQ_DESC_NUM_8822C(x, v)                                       \
+	(BIT_CLEAR_VOQ_DESC_NUM_8822C(x) | BIT_VOQ_DESC_NUM_8822C(v))
+
+/* 2 REG_VIQ_TXBD_NUM_8822C */
+#define BIT_PCIE_VIQ_FLAG_8822C BIT(14)
+
+#define BIT_SHIFT_VIQ_DESC_MODE_8822C 12
+#define BIT_MASK_VIQ_DESC_MODE_8822C 0x3
+#define BIT_VIQ_DESC_MODE_8822C(x)                                             \
+	(((x) & BIT_MASK_VIQ_DESC_MODE_8822C) << BIT_SHIFT_VIQ_DESC_MODE_8822C)
+#define BITS_VIQ_DESC_MODE_8822C                                               \
+	(BIT_MASK_VIQ_DESC_MODE_8822C << BIT_SHIFT_VIQ_DESC_MODE_8822C)
+#define BIT_CLEAR_VIQ_DESC_MODE_8822C(x) ((x) & (~BITS_VIQ_DESC_MODE_8822C))
+#define BIT_GET_VIQ_DESC_MODE_8822C(x)                                         \
+	(((x) >> BIT_SHIFT_VIQ_DESC_MODE_8822C) & BIT_MASK_VIQ_DESC_MODE_8822C)
+#define BIT_SET_VIQ_DESC_MODE_8822C(x, v)                                      \
+	(BIT_CLEAR_VIQ_DESC_MODE_8822C(x) | BIT_VIQ_DESC_MODE_8822C(v))
+
+#define BIT_SHIFT_VIQ_DESC_NUM_8822C 0
+#define BIT_MASK_VIQ_DESC_NUM_8822C 0xfff
+#define BIT_VIQ_DESC_NUM_8822C(x)                                              \
+	(((x) & BIT_MASK_VIQ_DESC_NUM_8822C) << BIT_SHIFT_VIQ_DESC_NUM_8822C)
+#define BITS_VIQ_DESC_NUM_8822C                                                \
+	(BIT_MASK_VIQ_DESC_NUM_8822C << BIT_SHIFT_VIQ_DESC_NUM_8822C)
+#define BIT_CLEAR_VIQ_DESC_NUM_8822C(x) ((x) & (~BITS_VIQ_DESC_NUM_8822C))
+#define BIT_GET_VIQ_DESC_NUM_8822C(x)                                          \
+	(((x) >> BIT_SHIFT_VIQ_DESC_NUM_8822C) & BIT_MASK_VIQ_DESC_NUM_8822C)
+#define BIT_SET_VIQ_DESC_NUM_8822C(x, v)                                       \
+	(BIT_CLEAR_VIQ_DESC_NUM_8822C(x) | BIT_VIQ_DESC_NUM_8822C(v))
+
+/* 2 REG_BEQ_TXBD_NUM_8822C */
+#define BIT_PCIE_BEQ_FLAG_8822C BIT(14)
+
+#define BIT_SHIFT_BEQ_DESC_MODE_8822C 12
+#define BIT_MASK_BEQ_DESC_MODE_8822C 0x3
+#define BIT_BEQ_DESC_MODE_8822C(x)                                             \
+	(((x) & BIT_MASK_BEQ_DESC_MODE_8822C) << BIT_SHIFT_BEQ_DESC_MODE_8822C)
+#define BITS_BEQ_DESC_MODE_8822C                                               \
+	(BIT_MASK_BEQ_DESC_MODE_8822C << BIT_SHIFT_BEQ_DESC_MODE_8822C)
+#define BIT_CLEAR_BEQ_DESC_MODE_8822C(x) ((x) & (~BITS_BEQ_DESC_MODE_8822C))
+#define BIT_GET_BEQ_DESC_MODE_8822C(x)                                         \
+	(((x) >> BIT_SHIFT_BEQ_DESC_MODE_8822C) & BIT_MASK_BEQ_DESC_MODE_8822C)
+#define BIT_SET_BEQ_DESC_MODE_8822C(x, v)                                      \
+	(BIT_CLEAR_BEQ_DESC_MODE_8822C(x) | BIT_BEQ_DESC_MODE_8822C(v))
+
+#define BIT_SHIFT_BEQ_DESC_NUM_8822C 0
+#define BIT_MASK_BEQ_DESC_NUM_8822C 0xfff
+#define BIT_BEQ_DESC_NUM_8822C(x)                                              \
+	(((x) & BIT_MASK_BEQ_DESC_NUM_8822C) << BIT_SHIFT_BEQ_DESC_NUM_8822C)
+#define BITS_BEQ_DESC_NUM_8822C                                                \
+	(BIT_MASK_BEQ_DESC_NUM_8822C << BIT_SHIFT_BEQ_DESC_NUM_8822C)
+#define BIT_CLEAR_BEQ_DESC_NUM_8822C(x) ((x) & (~BITS_BEQ_DESC_NUM_8822C))
+#define BIT_GET_BEQ_DESC_NUM_8822C(x)                                          \
+	(((x) >> BIT_SHIFT_BEQ_DESC_NUM_8822C) & BIT_MASK_BEQ_DESC_NUM_8822C)
+#define BIT_SET_BEQ_DESC_NUM_8822C(x, v)                                       \
+	(BIT_CLEAR_BEQ_DESC_NUM_8822C(x) | BIT_BEQ_DESC_NUM_8822C(v))
+
+/* 2 REG_BKQ_TXBD_NUM_8822C */
+#define BIT_PCIE_BKQ_FLAG_8822C BIT(14)
+
+#define BIT_SHIFT_BKQ_DESC_MODE_8822C 12
+#define BIT_MASK_BKQ_DESC_MODE_8822C 0x3
+#define BIT_BKQ_DESC_MODE_8822C(x)                                             \
+	(((x) & BIT_MASK_BKQ_DESC_MODE_8822C) << BIT_SHIFT_BKQ_DESC_MODE_8822C)
+#define BITS_BKQ_DESC_MODE_8822C                                               \
+	(BIT_MASK_BKQ_DESC_MODE_8822C << BIT_SHIFT_BKQ_DESC_MODE_8822C)
+#define BIT_CLEAR_BKQ_DESC_MODE_8822C(x) ((x) & (~BITS_BKQ_DESC_MODE_8822C))
+#define BIT_GET_BKQ_DESC_MODE_8822C(x)                                         \
+	(((x) >> BIT_SHIFT_BKQ_DESC_MODE_8822C) & BIT_MASK_BKQ_DESC_MODE_8822C)
+#define BIT_SET_BKQ_DESC_MODE_8822C(x, v)                                      \
+	(BIT_CLEAR_BKQ_DESC_MODE_8822C(x) | BIT_BKQ_DESC_MODE_8822C(v))
+
+#define BIT_SHIFT_BKQ_DESC_NUM_8822C 0
+#define BIT_MASK_BKQ_DESC_NUM_8822C 0xfff
+#define BIT_BKQ_DESC_NUM_8822C(x)                                              \
+	(((x) & BIT_MASK_BKQ_DESC_NUM_8822C) << BIT_SHIFT_BKQ_DESC_NUM_8822C)
+#define BITS_BKQ_DESC_NUM_8822C                                                \
+	(BIT_MASK_BKQ_DESC_NUM_8822C << BIT_SHIFT_BKQ_DESC_NUM_8822C)
+#define BIT_CLEAR_BKQ_DESC_NUM_8822C(x) ((x) & (~BITS_BKQ_DESC_NUM_8822C))
+#define BIT_GET_BKQ_DESC_NUM_8822C(x)                                          \
+	(((x) >> BIT_SHIFT_BKQ_DESC_NUM_8822C) & BIT_MASK_BKQ_DESC_NUM_8822C)
+#define BIT_SET_BKQ_DESC_NUM_8822C(x, v)                                       \
+	(BIT_CLEAR_BKQ_DESC_NUM_8822C(x) | BIT_BKQ_DESC_NUM_8822C(v))
+
+/* 2 REG_HI0Q_TXBD_NUM_8822C */
+#define BIT_HI0Q_FLAG_8822C BIT(14)
+
+#define BIT_SHIFT_HI0Q_DESC_MODE_8822C 12
+#define BIT_MASK_HI0Q_DESC_MODE_8822C 0x3
+#define BIT_HI0Q_DESC_MODE_8822C(x)                                            \
+	(((x) & BIT_MASK_HI0Q_DESC_MODE_8822C)                                 \
+	 << BIT_SHIFT_HI0Q_DESC_MODE_8822C)
+#define BITS_HI0Q_DESC_MODE_8822C                                              \
+	(BIT_MASK_HI0Q_DESC_MODE_8822C << BIT_SHIFT_HI0Q_DESC_MODE_8822C)
+#define BIT_CLEAR_HI0Q_DESC_MODE_8822C(x) ((x) & (~BITS_HI0Q_DESC_MODE_8822C))
+#define BIT_GET_HI0Q_DESC_MODE_8822C(x)                                        \
+	(((x) >> BIT_SHIFT_HI0Q_DESC_MODE_8822C) &                             \
+	 BIT_MASK_HI0Q_DESC_MODE_8822C)
+#define BIT_SET_HI0Q_DESC_MODE_8822C(x, v)                                     \
+	(BIT_CLEAR_HI0Q_DESC_MODE_8822C(x) | BIT_HI0Q_DESC_MODE_8822C(v))
+
+#define BIT_SHIFT_HI0Q_DESC_NUM_8822C 0
+#define BIT_MASK_HI0Q_DESC_NUM_8822C 0xfff
+#define BIT_HI0Q_DESC_NUM_8822C(x)                                             \
+	(((x) & BIT_MASK_HI0Q_DESC_NUM_8822C) << BIT_SHIFT_HI0Q_DESC_NUM_8822C)
+#define BITS_HI0Q_DESC_NUM_8822C                                               \
+	(BIT_MASK_HI0Q_DESC_NUM_8822C << BIT_SHIFT_HI0Q_DESC_NUM_8822C)
+#define BIT_CLEAR_HI0Q_DESC_NUM_8822C(x) ((x) & (~BITS_HI0Q_DESC_NUM_8822C))
+#define BIT_GET_HI0Q_DESC_NUM_8822C(x)                                         \
+	(((x) >> BIT_SHIFT_HI0Q_DESC_NUM_8822C) & BIT_MASK_HI0Q_DESC_NUM_8822C)
+#define BIT_SET_HI0Q_DESC_NUM_8822C(x, v)                                      \
+	(BIT_CLEAR_HI0Q_DESC_NUM_8822C(x) | BIT_HI0Q_DESC_NUM_8822C(v))
+
+/* 2 REG_HI1Q_TXBD_NUM_8822C */
+#define BIT_HI1Q_FLAG_8822C BIT(14)
+
+#define BIT_SHIFT_HI1Q_DESC_MODE_8822C 12
+#define BIT_MASK_HI1Q_DESC_MODE_8822C 0x3
+#define BIT_HI1Q_DESC_MODE_8822C(x)                                            \
+	(((x) & BIT_MASK_HI1Q_DESC_MODE_8822C)                                 \
+	 << BIT_SHIFT_HI1Q_DESC_MODE_8822C)
+#define BITS_HI1Q_DESC_MODE_8822C                                              \
+	(BIT_MASK_HI1Q_DESC_MODE_8822C << BIT_SHIFT_HI1Q_DESC_MODE_8822C)
+#define BIT_CLEAR_HI1Q_DESC_MODE_8822C(x) ((x) & (~BITS_HI1Q_DESC_MODE_8822C))
+#define BIT_GET_HI1Q_DESC_MODE_8822C(x)                                        \
+	(((x) >> BIT_SHIFT_HI1Q_DESC_MODE_8822C) &                             \
+	 BIT_MASK_HI1Q_DESC_MODE_8822C)
+#define BIT_SET_HI1Q_DESC_MODE_8822C(x, v)                                     \
+	(BIT_CLEAR_HI1Q_DESC_MODE_8822C(x) | BIT_HI1Q_DESC_MODE_8822C(v))
+
+#define BIT_SHIFT_HI1Q_DESC_NUM_8822C 0
+#define BIT_MASK_HI1Q_DESC_NUM_8822C 0xfff
+#define BIT_HI1Q_DESC_NUM_8822C(x)                                             \
+	(((x) & BIT_MASK_HI1Q_DESC_NUM_8822C) << BIT_SHIFT_HI1Q_DESC_NUM_8822C)
+#define BITS_HI1Q_DESC_NUM_8822C                                               \
+	(BIT_MASK_HI1Q_DESC_NUM_8822C << BIT_SHIFT_HI1Q_DESC_NUM_8822C)
+#define BIT_CLEAR_HI1Q_DESC_NUM_8822C(x) ((x) & (~BITS_HI1Q_DESC_NUM_8822C))
+#define BIT_GET_HI1Q_DESC_NUM_8822C(x)                                         \
+	(((x) >> BIT_SHIFT_HI1Q_DESC_NUM_8822C) & BIT_MASK_HI1Q_DESC_NUM_8822C)
+#define BIT_SET_HI1Q_DESC_NUM_8822C(x, v)                                      \
+	(BIT_CLEAR_HI1Q_DESC_NUM_8822C(x) | BIT_HI1Q_DESC_NUM_8822C(v))
+
+/* 2 REG_HI2Q_TXBD_NUM_8822C */
+#define BIT_HI2Q_FLAG_8822C BIT(14)
+
+#define BIT_SHIFT_HI2Q_DESC_MODE_8822C 12
+#define BIT_MASK_HI2Q_DESC_MODE_8822C 0x3
+#define BIT_HI2Q_DESC_MODE_8822C(x)                                            \
+	(((x) & BIT_MASK_HI2Q_DESC_MODE_8822C)                                 \
+	 << BIT_SHIFT_HI2Q_DESC_MODE_8822C)
+#define BITS_HI2Q_DESC_MODE_8822C                                              \
+	(BIT_MASK_HI2Q_DESC_MODE_8822C << BIT_SHIFT_HI2Q_DESC_MODE_8822C)
+#define BIT_CLEAR_HI2Q_DESC_MODE_8822C(x) ((x) & (~BITS_HI2Q_DESC_MODE_8822C))
+#define BIT_GET_HI2Q_DESC_MODE_8822C(x)                                        \
+	(((x) >> BIT_SHIFT_HI2Q_DESC_MODE_8822C) &                             \
+	 BIT_MASK_HI2Q_DESC_MODE_8822C)
+#define BIT_SET_HI2Q_DESC_MODE_8822C(x, v)                                     \
+	(BIT_CLEAR_HI2Q_DESC_MODE_8822C(x) | BIT_HI2Q_DESC_MODE_8822C(v))
+
+#define BIT_SHIFT_HI2Q_DESC_NUM_8822C 0
+#define BIT_MASK_HI2Q_DESC_NUM_8822C 0xfff
+#define BIT_HI2Q_DESC_NUM_8822C(x)                                             \
+	(((x) & BIT_MASK_HI2Q_DESC_NUM_8822C) << BIT_SHIFT_HI2Q_DESC_NUM_8822C)
+#define BITS_HI2Q_DESC_NUM_8822C                                               \
+	(BIT_MASK_HI2Q_DESC_NUM_8822C << BIT_SHIFT_HI2Q_DESC_NUM_8822C)
+#define BIT_CLEAR_HI2Q_DESC_NUM_8822C(x) ((x) & (~BITS_HI2Q_DESC_NUM_8822C))
+#define BIT_GET_HI2Q_DESC_NUM_8822C(x)                                         \
+	(((x) >> BIT_SHIFT_HI2Q_DESC_NUM_8822C) & BIT_MASK_HI2Q_DESC_NUM_8822C)
+#define BIT_SET_HI2Q_DESC_NUM_8822C(x, v)                                      \
+	(BIT_CLEAR_HI2Q_DESC_NUM_8822C(x) | BIT_HI2Q_DESC_NUM_8822C(v))
+
+/* 2 REG_HI3Q_TXBD_NUM_8822C */
+#define BIT_HI3Q_FLAG_8822C BIT(14)
+
+#define BIT_SHIFT_HI3Q_DESC_MODE_8822C 12
+#define BIT_MASK_HI3Q_DESC_MODE_8822C 0x3
+#define BIT_HI3Q_DESC_MODE_8822C(x)                                            \
+	(((x) & BIT_MASK_HI3Q_DESC_MODE_8822C)                                 \
+	 << BIT_SHIFT_HI3Q_DESC_MODE_8822C)
+#define BITS_HI3Q_DESC_MODE_8822C                                              \
+	(BIT_MASK_HI3Q_DESC_MODE_8822C << BIT_SHIFT_HI3Q_DESC_MODE_8822C)
+#define BIT_CLEAR_HI3Q_DESC_MODE_8822C(x) ((x) & (~BITS_HI3Q_DESC_MODE_8822C))
+#define BIT_GET_HI3Q_DESC_MODE_8822C(x)                                        \
+	(((x) >> BIT_SHIFT_HI3Q_DESC_MODE_8822C) &                             \
+	 BIT_MASK_HI3Q_DESC_MODE_8822C)
+#define BIT_SET_HI3Q_DESC_MODE_8822C(x, v)                                     \
+	(BIT_CLEAR_HI3Q_DESC_MODE_8822C(x) | BIT_HI3Q_DESC_MODE_8822C(v))
+
+#define BIT_SHIFT_HI3Q_DESC_NUM_8822C 0
+#define BIT_MASK_HI3Q_DESC_NUM_8822C 0xfff
+#define BIT_HI3Q_DESC_NUM_8822C(x)                                             \
+	(((x) & BIT_MASK_HI3Q_DESC_NUM_8822C) << BIT_SHIFT_HI3Q_DESC_NUM_8822C)
+#define BITS_HI3Q_DESC_NUM_8822C                                               \
+	(BIT_MASK_HI3Q_DESC_NUM_8822C << BIT_SHIFT_HI3Q_DESC_NUM_8822C)
+#define BIT_CLEAR_HI3Q_DESC_NUM_8822C(x) ((x) & (~BITS_HI3Q_DESC_NUM_8822C))
+#define BIT_GET_HI3Q_DESC_NUM_8822C(x)                                         \
+	(((x) >> BIT_SHIFT_HI3Q_DESC_NUM_8822C) & BIT_MASK_HI3Q_DESC_NUM_8822C)
+#define BIT_SET_HI3Q_DESC_NUM_8822C(x, v)                                      \
+	(BIT_CLEAR_HI3Q_DESC_NUM_8822C(x) | BIT_HI3Q_DESC_NUM_8822C(v))
+
+/* 2 REG_HI4Q_TXBD_NUM_8822C */
+#define BIT_HI4Q_FLAG_8822C BIT(14)
+
+#define BIT_SHIFT_HI4Q_DESC_MODE_8822C 12
+#define BIT_MASK_HI4Q_DESC_MODE_8822C 0x3
+#define BIT_HI4Q_DESC_MODE_8822C(x)                                            \
+	(((x) & BIT_MASK_HI4Q_DESC_MODE_8822C)                                 \
+	 << BIT_SHIFT_HI4Q_DESC_MODE_8822C)
+#define BITS_HI4Q_DESC_MODE_8822C                                              \
+	(BIT_MASK_HI4Q_DESC_MODE_8822C << BIT_SHIFT_HI4Q_DESC_MODE_8822C)
+#define BIT_CLEAR_HI4Q_DESC_MODE_8822C(x) ((x) & (~BITS_HI4Q_DESC_MODE_8822C))
+#define BIT_GET_HI4Q_DESC_MODE_8822C(x)                                        \
+	(((x) >> BIT_SHIFT_HI4Q_DESC_MODE_8822C) &                             \
+	 BIT_MASK_HI4Q_DESC_MODE_8822C)
+#define BIT_SET_HI4Q_DESC_MODE_8822C(x, v)                                     \
+	(BIT_CLEAR_HI4Q_DESC_MODE_8822C(x) | BIT_HI4Q_DESC_MODE_8822C(v))
+
+#define BIT_SHIFT_HI4Q_DESC_NUM_8822C 0
+#define BIT_MASK_HI4Q_DESC_NUM_8822C 0xfff
+#define BIT_HI4Q_DESC_NUM_8822C(x)                                             \
+	(((x) & BIT_MASK_HI4Q_DESC_NUM_8822C) << BIT_SHIFT_HI4Q_DESC_NUM_8822C)
+#define BITS_HI4Q_DESC_NUM_8822C                                               \
+	(BIT_MASK_HI4Q_DESC_NUM_8822C << BIT_SHIFT_HI4Q_DESC_NUM_8822C)
+#define BIT_CLEAR_HI4Q_DESC_NUM_8822C(x) ((x) & (~BITS_HI4Q_DESC_NUM_8822C))
+#define BIT_GET_HI4Q_DESC_NUM_8822C(x)                                         \
+	(((x) >> BIT_SHIFT_HI4Q_DESC_NUM_8822C) & BIT_MASK_HI4Q_DESC_NUM_8822C)
+#define BIT_SET_HI4Q_DESC_NUM_8822C(x, v)                                      \
+	(BIT_CLEAR_HI4Q_DESC_NUM_8822C(x) | BIT_HI4Q_DESC_NUM_8822C(v))
+
+/* 2 REG_HI5Q_TXBD_NUM_8822C */
+#define BIT_HI5Q_FLAG_8822C BIT(14)
+
+#define BIT_SHIFT_HI5Q_DESC_MODE_8822C 12
+#define BIT_MASK_HI5Q_DESC_MODE_8822C 0x3
+#define BIT_HI5Q_DESC_MODE_8822C(x)                                            \
+	(((x) & BIT_MASK_HI5Q_DESC_MODE_8822C)                                 \
+	 << BIT_SHIFT_HI5Q_DESC_MODE_8822C)
+#define BITS_HI5Q_DESC_MODE_8822C                                              \
+	(BIT_MASK_HI5Q_DESC_MODE_8822C << BIT_SHIFT_HI5Q_DESC_MODE_8822C)
+#define BIT_CLEAR_HI5Q_DESC_MODE_8822C(x) ((x) & (~BITS_HI5Q_DESC_MODE_8822C))
+#define BIT_GET_HI5Q_DESC_MODE_8822C(x)                                        \
+	(((x) >> BIT_SHIFT_HI5Q_DESC_MODE_8822C) &                             \
+	 BIT_MASK_HI5Q_DESC_MODE_8822C)
+#define BIT_SET_HI5Q_DESC_MODE_8822C(x, v)                                     \
+	(BIT_CLEAR_HI5Q_DESC_MODE_8822C(x) | BIT_HI5Q_DESC_MODE_8822C(v))
+
+#define BIT_SHIFT_HI5Q_DESC_NUM_8822C 0
+#define BIT_MASK_HI5Q_DESC_NUM_8822C 0xfff
+#define BIT_HI5Q_DESC_NUM_8822C(x)                                             \
+	(((x) & BIT_MASK_HI5Q_DESC_NUM_8822C) << BIT_SHIFT_HI5Q_DESC_NUM_8822C)
+#define BITS_HI5Q_DESC_NUM_8822C                                               \
+	(BIT_MASK_HI5Q_DESC_NUM_8822C << BIT_SHIFT_HI5Q_DESC_NUM_8822C)
+#define BIT_CLEAR_HI5Q_DESC_NUM_8822C(x) ((x) & (~BITS_HI5Q_DESC_NUM_8822C))
+#define BIT_GET_HI5Q_DESC_NUM_8822C(x)                                         \
+	(((x) >> BIT_SHIFT_HI5Q_DESC_NUM_8822C) & BIT_MASK_HI5Q_DESC_NUM_8822C)
+#define BIT_SET_HI5Q_DESC_NUM_8822C(x, v)                                      \
+	(BIT_CLEAR_HI5Q_DESC_NUM_8822C(x) | BIT_HI5Q_DESC_NUM_8822C(v))
+
+/* 2 REG_HI6Q_TXBD_NUM_8822C */
+#define BIT_HI6Q_FLAG_8822C BIT(14)
+
+#define BIT_SHIFT_HI6Q_DESC_MODE_8822C 12
+#define BIT_MASK_HI6Q_DESC_MODE_8822C 0x3
+#define BIT_HI6Q_DESC_MODE_8822C(x)                                            \
+	(((x) & BIT_MASK_HI6Q_DESC_MODE_8822C)                                 \
+	 << BIT_SHIFT_HI6Q_DESC_MODE_8822C)
+#define BITS_HI6Q_DESC_MODE_8822C                                              \
+	(BIT_MASK_HI6Q_DESC_MODE_8822C << BIT_SHIFT_HI6Q_DESC_MODE_8822C)
+#define BIT_CLEAR_HI6Q_DESC_MODE_8822C(x) ((x) & (~BITS_HI6Q_DESC_MODE_8822C))
+#define BIT_GET_HI6Q_DESC_MODE_8822C(x)                                        \
+	(((x) >> BIT_SHIFT_HI6Q_DESC_MODE_8822C) &                             \
+	 BIT_MASK_HI6Q_DESC_MODE_8822C)
+#define BIT_SET_HI6Q_DESC_MODE_8822C(x, v)                                     \
+	(BIT_CLEAR_HI6Q_DESC_MODE_8822C(x) | BIT_HI6Q_DESC_MODE_8822C(v))
+
+#define BIT_SHIFT_HI6Q_DESC_NUM_8822C 0
+#define BIT_MASK_HI6Q_DESC_NUM_8822C 0xfff
+#define BIT_HI6Q_DESC_NUM_8822C(x)                                             \
+	(((x) & BIT_MASK_HI6Q_DESC_NUM_8822C) << BIT_SHIFT_HI6Q_DESC_NUM_8822C)
+#define BITS_HI6Q_DESC_NUM_8822C                                               \
+	(BIT_MASK_HI6Q_DESC_NUM_8822C << BIT_SHIFT_HI6Q_DESC_NUM_8822C)
+#define BIT_CLEAR_HI6Q_DESC_NUM_8822C(x) ((x) & (~BITS_HI6Q_DESC_NUM_8822C))
+#define BIT_GET_HI6Q_DESC_NUM_8822C(x)                                         \
+	(((x) >> BIT_SHIFT_HI6Q_DESC_NUM_8822C) & BIT_MASK_HI6Q_DESC_NUM_8822C)
+#define BIT_SET_HI6Q_DESC_NUM_8822C(x, v)                                      \
+	(BIT_CLEAR_HI6Q_DESC_NUM_8822C(x) | BIT_HI6Q_DESC_NUM_8822C(v))
+
+/* 2 REG_HI7Q_TXBD_NUM_8822C */
+#define BIT_HI7Q_FLAG_8822C BIT(14)
+
+#define BIT_SHIFT_HI7Q_DESC_MODE_8822C 12
+#define BIT_MASK_HI7Q_DESC_MODE_8822C 0x3
+#define BIT_HI7Q_DESC_MODE_8822C(x)                                            \
+	(((x) & BIT_MASK_HI7Q_DESC_MODE_8822C)                                 \
+	 << BIT_SHIFT_HI7Q_DESC_MODE_8822C)
+#define BITS_HI7Q_DESC_MODE_8822C                                              \
+	(BIT_MASK_HI7Q_DESC_MODE_8822C << BIT_SHIFT_HI7Q_DESC_MODE_8822C)
+#define BIT_CLEAR_HI7Q_DESC_MODE_8822C(x) ((x) & (~BITS_HI7Q_DESC_MODE_8822C))
+#define BIT_GET_HI7Q_DESC_MODE_8822C(x)                                        \
+	(((x) >> BIT_SHIFT_HI7Q_DESC_MODE_8822C) &                             \
+	 BIT_MASK_HI7Q_DESC_MODE_8822C)
+#define BIT_SET_HI7Q_DESC_MODE_8822C(x, v)                                     \
+	(BIT_CLEAR_HI7Q_DESC_MODE_8822C(x) | BIT_HI7Q_DESC_MODE_8822C(v))
+
+#define BIT_SHIFT_HI7Q_DESC_NUM_8822C 0
+#define BIT_MASK_HI7Q_DESC_NUM_8822C 0xfff
+#define BIT_HI7Q_DESC_NUM_8822C(x)                                             \
+	(((x) & BIT_MASK_HI7Q_DESC_NUM_8822C) << BIT_SHIFT_HI7Q_DESC_NUM_8822C)
+#define BITS_HI7Q_DESC_NUM_8822C                                               \
+	(BIT_MASK_HI7Q_DESC_NUM_8822C << BIT_SHIFT_HI7Q_DESC_NUM_8822C)
+#define BIT_CLEAR_HI7Q_DESC_NUM_8822C(x) ((x) & (~BITS_HI7Q_DESC_NUM_8822C))
+#define BIT_GET_HI7Q_DESC_NUM_8822C(x)                                         \
+	(((x) >> BIT_SHIFT_HI7Q_DESC_NUM_8822C) & BIT_MASK_HI7Q_DESC_NUM_8822C)
+#define BIT_SET_HI7Q_DESC_NUM_8822C(x, v)                                      \
+	(BIT_CLEAR_HI7Q_DESC_NUM_8822C(x) | BIT_HI7Q_DESC_NUM_8822C(v))
+
+/* 2 REG_TSFTIMER_HCI_8822C */
+
+#define BIT_SHIFT_TSFT2_HCI_8822C 16
+#define BIT_MASK_TSFT2_HCI_8822C 0xffff
+#define BIT_TSFT2_HCI_8822C(x)                                                 \
+	(((x) & BIT_MASK_TSFT2_HCI_8822C) << BIT_SHIFT_TSFT2_HCI_8822C)
+#define BITS_TSFT2_HCI_8822C                                                   \
+	(BIT_MASK_TSFT2_HCI_8822C << BIT_SHIFT_TSFT2_HCI_8822C)
+#define BIT_CLEAR_TSFT2_HCI_8822C(x) ((x) & (~BITS_TSFT2_HCI_8822C))
+#define BIT_GET_TSFT2_HCI_8822C(x)                                             \
+	(((x) >> BIT_SHIFT_TSFT2_HCI_8822C) & BIT_MASK_TSFT2_HCI_8822C)
+#define BIT_SET_TSFT2_HCI_8822C(x, v)                                          \
+	(BIT_CLEAR_TSFT2_HCI_8822C(x) | BIT_TSFT2_HCI_8822C(v))
+
+#define BIT_SHIFT_TSFT1_HCI_8822C 0
+#define BIT_MASK_TSFT1_HCI_8822C 0xffff
+#define BIT_TSFT1_HCI_8822C(x)                                                 \
+	(((x) & BIT_MASK_TSFT1_HCI_8822C) << BIT_SHIFT_TSFT1_HCI_8822C)
+#define BITS_TSFT1_HCI_8822C                                                   \
+	(BIT_MASK_TSFT1_HCI_8822C << BIT_SHIFT_TSFT1_HCI_8822C)
+#define BIT_CLEAR_TSFT1_HCI_8822C(x) ((x) & (~BITS_TSFT1_HCI_8822C))
+#define BIT_GET_TSFT1_HCI_8822C(x)                                             \
+	(((x) >> BIT_SHIFT_TSFT1_HCI_8822C) & BIT_MASK_TSFT1_HCI_8822C)
+#define BIT_SET_TSFT1_HCI_8822C(x, v)                                          \
+	(BIT_CLEAR_TSFT1_HCI_8822C(x) | BIT_TSFT1_HCI_8822C(v))
+
+/* 2 REG_BD_RWPTR_CLR_8822C */
+#define BIT_CLR_HI7Q_HW_IDX_8822C BIT(29)
+#define BIT_CLR_HI6Q_HW_IDX_8822C BIT(28)
+#define BIT_CLR_HI5Q_HW_IDX_8822C BIT(27)
+#define BIT_CLR_HI4Q_HW_IDX_8822C BIT(26)
+#define BIT_CLR_HI3Q_HW_IDX_8822C BIT(25)
+#define BIT_CLR_HI2Q_HW_IDX_8822C BIT(24)
+#define BIT_CLR_HI1Q_HW_IDX_8822C BIT(23)
+#define BIT_CLR_HI0Q_HW_IDX_8822C BIT(22)
+#define BIT_CLR_BKQ_HW_IDX_8822C BIT(21)
+#define BIT_CLR_BEQ_HW_IDX_8822C BIT(20)
+#define BIT_CLR_VIQ_HW_IDX_8822C BIT(19)
+#define BIT_CLR_VOQ_HW_IDX_8822C BIT(18)
+#define BIT_CLR_MGQ_HW_IDX_8822C BIT(17)
+#define BIT_CLR_RXQ_HW_IDX_8822C BIT(16)
+#define BIT_CLR_HI7Q_HOST_IDX_8822C BIT(13)
+#define BIT_CLR_HI6Q_HOST_IDX_8822C BIT(12)
+#define BIT_CLR_HI5Q_HOST_IDX_8822C BIT(11)
+#define BIT_CLR_HI4Q_HOST_IDX_8822C BIT(10)
+#define BIT_CLR_HI3Q_HOST_IDX_8822C BIT(9)
+#define BIT_CLR_HI2Q_HOST_IDX_8822C BIT(8)
+#define BIT_CLR_HI1Q_HOST_IDX_8822C BIT(7)
+#define BIT_CLR_HI0Q_HOST_IDX_8822C BIT(6)
+#define BIT_CLR_BKQ_HOST_IDX_8822C BIT(5)
+#define BIT_CLR_BEQ_HOST_IDX_8822C BIT(4)
+#define BIT_CLR_VIQ_HOST_IDX_8822C BIT(3)
+#define BIT_CLR_VOQ_HOST_IDX_8822C BIT(2)
+#define BIT_CLR_MGQ_HOST_IDX_8822C BIT(1)
+#define BIT_CLR_RXQ_HOST_IDX_8822C BIT(0)
+
+/* 2 REG_VOQ_TXBD_IDX_8822C */
+
+#define BIT_SHIFT_VOQ_HW_IDX_8822C 16
+#define BIT_MASK_VOQ_HW_IDX_8822C 0xfff
+#define BIT_VOQ_HW_IDX_8822C(x)                                                \
+	(((x) & BIT_MASK_VOQ_HW_IDX_8822C) << BIT_SHIFT_VOQ_HW_IDX_8822C)
+#define BITS_VOQ_HW_IDX_8822C                                                  \
+	(BIT_MASK_VOQ_HW_IDX_8822C << BIT_SHIFT_VOQ_HW_IDX_8822C)
+#define BIT_CLEAR_VOQ_HW_IDX_8822C(x) ((x) & (~BITS_VOQ_HW_IDX_8822C))
+#define BIT_GET_VOQ_HW_IDX_8822C(x)                                            \
+	(((x) >> BIT_SHIFT_VOQ_HW_IDX_8822C) & BIT_MASK_VOQ_HW_IDX_8822C)
+#define BIT_SET_VOQ_HW_IDX_8822C(x, v)                                         \
+	(BIT_CLEAR_VOQ_HW_IDX_8822C(x) | BIT_VOQ_HW_IDX_8822C(v))
+
+#define BIT_SHIFT_VOQ_HOST_IDX_8822C 0
+#define BIT_MASK_VOQ_HOST_IDX_8822C 0xfff
+#define BIT_VOQ_HOST_IDX_8822C(x)                                              \
+	(((x) & BIT_MASK_VOQ_HOST_IDX_8822C) << BIT_SHIFT_VOQ_HOST_IDX_8822C)
+#define BITS_VOQ_HOST_IDX_8822C                                                \
+	(BIT_MASK_VOQ_HOST_IDX_8822C << BIT_SHIFT_VOQ_HOST_IDX_8822C)
+#define BIT_CLEAR_VOQ_HOST_IDX_8822C(x) ((x) & (~BITS_VOQ_HOST_IDX_8822C))
+#define BIT_GET_VOQ_HOST_IDX_8822C(x)                                          \
+	(((x) >> BIT_SHIFT_VOQ_HOST_IDX_8822C) & BIT_MASK_VOQ_HOST_IDX_8822C)
+#define BIT_SET_VOQ_HOST_IDX_8822C(x, v)                                       \
+	(BIT_CLEAR_VOQ_HOST_IDX_8822C(x) | BIT_VOQ_HOST_IDX_8822C(v))
+
+/* 2 REG_VIQ_TXBD_IDX_8822C */
+
+#define BIT_SHIFT_VIQ_HW_IDX_8822C 16
+#define BIT_MASK_VIQ_HW_IDX_8822C 0xfff
+#define BIT_VIQ_HW_IDX_8822C(x)                                                \
+	(((x) & BIT_MASK_VIQ_HW_IDX_8822C) << BIT_SHIFT_VIQ_HW_IDX_8822C)
+#define BITS_VIQ_HW_IDX_8822C                                                  \
+	(BIT_MASK_VIQ_HW_IDX_8822C << BIT_SHIFT_VIQ_HW_IDX_8822C)
+#define BIT_CLEAR_VIQ_HW_IDX_8822C(x) ((x) & (~BITS_VIQ_HW_IDX_8822C))
+#define BIT_GET_VIQ_HW_IDX_8822C(x)                                            \
+	(((x) >> BIT_SHIFT_VIQ_HW_IDX_8822C) & BIT_MASK_VIQ_HW_IDX_8822C)
+#define BIT_SET_VIQ_HW_IDX_8822C(x, v)                                         \
+	(BIT_CLEAR_VIQ_HW_IDX_8822C(x) | BIT_VIQ_HW_IDX_8822C(v))
+
+#define BIT_SHIFT_VIQ_HOST_IDX_8822C 0
+#define BIT_MASK_VIQ_HOST_IDX_8822C 0xfff
+#define BIT_VIQ_HOST_IDX_8822C(x)                                              \
+	(((x) & BIT_MASK_VIQ_HOST_IDX_8822C) << BIT_SHIFT_VIQ_HOST_IDX_8822C)
+#define BITS_VIQ_HOST_IDX_8822C                                                \
+	(BIT_MASK_VIQ_HOST_IDX_8822C << BIT_SHIFT_VIQ_HOST_IDX_8822C)
+#define BIT_CLEAR_VIQ_HOST_IDX_8822C(x) ((x) & (~BITS_VIQ_HOST_IDX_8822C))
+#define BIT_GET_VIQ_HOST_IDX_8822C(x)                                          \
+	(((x) >> BIT_SHIFT_VIQ_HOST_IDX_8822C) & BIT_MASK_VIQ_HOST_IDX_8822C)
+#define BIT_SET_VIQ_HOST_IDX_8822C(x, v)                                       \
+	(BIT_CLEAR_VIQ_HOST_IDX_8822C(x) | BIT_VIQ_HOST_IDX_8822C(v))
+
+/* 2 REG_BEQ_TXBD_IDX_8822C */
+
+#define BIT_SHIFT_BEQ_HW_IDX_8822C 16
+#define BIT_MASK_BEQ_HW_IDX_8822C 0xfff
+#define BIT_BEQ_HW_IDX_8822C(x)                                                \
+	(((x) & BIT_MASK_BEQ_HW_IDX_8822C) << BIT_SHIFT_BEQ_HW_IDX_8822C)
+#define BITS_BEQ_HW_IDX_8822C                                                  \
+	(BIT_MASK_BEQ_HW_IDX_8822C << BIT_SHIFT_BEQ_HW_IDX_8822C)
+#define BIT_CLEAR_BEQ_HW_IDX_8822C(x) ((x) & (~BITS_BEQ_HW_IDX_8822C))
+#define BIT_GET_BEQ_HW_IDX_8822C(x)                                            \
+	(((x) >> BIT_SHIFT_BEQ_HW_IDX_8822C) & BIT_MASK_BEQ_HW_IDX_8822C)
+#define BIT_SET_BEQ_HW_IDX_8822C(x, v)                                         \
+	(BIT_CLEAR_BEQ_HW_IDX_8822C(x) | BIT_BEQ_HW_IDX_8822C(v))
+
+#define BIT_SHIFT_BEQ_HOST_IDX_8822C 0
+#define BIT_MASK_BEQ_HOST_IDX_8822C 0xfff
+#define BIT_BEQ_HOST_IDX_8822C(x)                                              \
+	(((x) & BIT_MASK_BEQ_HOST_IDX_8822C) << BIT_SHIFT_BEQ_HOST_IDX_8822C)
+#define BITS_BEQ_HOST_IDX_8822C                                                \
+	(BIT_MASK_BEQ_HOST_IDX_8822C << BIT_SHIFT_BEQ_HOST_IDX_8822C)
+#define BIT_CLEAR_BEQ_HOST_IDX_8822C(x) ((x) & (~BITS_BEQ_HOST_IDX_8822C))
+#define BIT_GET_BEQ_HOST_IDX_8822C(x)                                          \
+	(((x) >> BIT_SHIFT_BEQ_HOST_IDX_8822C) & BIT_MASK_BEQ_HOST_IDX_8822C)
+#define BIT_SET_BEQ_HOST_IDX_8822C(x, v)                                       \
+	(BIT_CLEAR_BEQ_HOST_IDX_8822C(x) | BIT_BEQ_HOST_IDX_8822C(v))
+
+/* 2 REG_BKQ_TXBD_IDX_8822C */
+
+#define BIT_SHIFT_BKQ_HW_IDX_8822C 16
+#define BIT_MASK_BKQ_HW_IDX_8822C 0xfff
+#define BIT_BKQ_HW_IDX_8822C(x)                                                \
+	(((x) & BIT_MASK_BKQ_HW_IDX_8822C) << BIT_SHIFT_BKQ_HW_IDX_8822C)
+#define BITS_BKQ_HW_IDX_8822C                                                  \
+	(BIT_MASK_BKQ_HW_IDX_8822C << BIT_SHIFT_BKQ_HW_IDX_8822C)
+#define BIT_CLEAR_BKQ_HW_IDX_8822C(x) ((x) & (~BITS_BKQ_HW_IDX_8822C))
+#define BIT_GET_BKQ_HW_IDX_8822C(x)                                            \
+	(((x) >> BIT_SHIFT_BKQ_HW_IDX_8822C) & BIT_MASK_BKQ_HW_IDX_8822C)
+#define BIT_SET_BKQ_HW_IDX_8822C(x, v)                                         \
+	(BIT_CLEAR_BKQ_HW_IDX_8822C(x) | BIT_BKQ_HW_IDX_8822C(v))
+
+#define BIT_SHIFT_BKQ_HOST_IDX_8822C 0
+#define BIT_MASK_BKQ_HOST_IDX_8822C 0xfff
+#define BIT_BKQ_HOST_IDX_8822C(x)                                              \
+	(((x) & BIT_MASK_BKQ_HOST_IDX_8822C) << BIT_SHIFT_BKQ_HOST_IDX_8822C)
+#define BITS_BKQ_HOST_IDX_8822C                                                \
+	(BIT_MASK_BKQ_HOST_IDX_8822C << BIT_SHIFT_BKQ_HOST_IDX_8822C)
+#define BIT_CLEAR_BKQ_HOST_IDX_8822C(x) ((x) & (~BITS_BKQ_HOST_IDX_8822C))
+#define BIT_GET_BKQ_HOST_IDX_8822C(x)                                          \
+	(((x) >> BIT_SHIFT_BKQ_HOST_IDX_8822C) & BIT_MASK_BKQ_HOST_IDX_8822C)
+#define BIT_SET_BKQ_HOST_IDX_8822C(x, v)                                       \
+	(BIT_CLEAR_BKQ_HOST_IDX_8822C(x) | BIT_BKQ_HOST_IDX_8822C(v))
+
+/* 2 REG_MGQ_TXBD_IDX_8822C */
+
+#define BIT_SHIFT_MGQ_HW_IDX_8822C 16
+#define BIT_MASK_MGQ_HW_IDX_8822C 0xfff
+#define BIT_MGQ_HW_IDX_8822C(x)                                                \
+	(((x) & BIT_MASK_MGQ_HW_IDX_8822C) << BIT_SHIFT_MGQ_HW_IDX_8822C)
+#define BITS_MGQ_HW_IDX_8822C                                                  \
+	(BIT_MASK_MGQ_HW_IDX_8822C << BIT_SHIFT_MGQ_HW_IDX_8822C)
+#define BIT_CLEAR_MGQ_HW_IDX_8822C(x) ((x) & (~BITS_MGQ_HW_IDX_8822C))
+#define BIT_GET_MGQ_HW_IDX_8822C(x)                                            \
+	(((x) >> BIT_SHIFT_MGQ_HW_IDX_8822C) & BIT_MASK_MGQ_HW_IDX_8822C)
+#define BIT_SET_MGQ_HW_IDX_8822C(x, v)                                         \
+	(BIT_CLEAR_MGQ_HW_IDX_8822C(x) | BIT_MGQ_HW_IDX_8822C(v))
+
+#define BIT_SHIFT_MGQ_HOST_IDX_8822C 0
+#define BIT_MASK_MGQ_HOST_IDX_8822C 0xfff
+#define BIT_MGQ_HOST_IDX_8822C(x)                                              \
+	(((x) & BIT_MASK_MGQ_HOST_IDX_8822C) << BIT_SHIFT_MGQ_HOST_IDX_8822C)
+#define BITS_MGQ_HOST_IDX_8822C                                                \
+	(BIT_MASK_MGQ_HOST_IDX_8822C << BIT_SHIFT_MGQ_HOST_IDX_8822C)
+#define BIT_CLEAR_MGQ_HOST_IDX_8822C(x) ((x) & (~BITS_MGQ_HOST_IDX_8822C))
+#define BIT_GET_MGQ_HOST_IDX_8822C(x)                                          \
+	(((x) >> BIT_SHIFT_MGQ_HOST_IDX_8822C) & BIT_MASK_MGQ_HOST_IDX_8822C)
+#define BIT_SET_MGQ_HOST_IDX_8822C(x, v)                                       \
+	(BIT_CLEAR_MGQ_HOST_IDX_8822C(x) | BIT_MGQ_HOST_IDX_8822C(v))
+
+/* 2 REG_RXQ_RXBD_IDX_8822C */
+
+#define BIT_SHIFT_RXQ_HW_IDX_8822C 16
+#define BIT_MASK_RXQ_HW_IDX_8822C 0xfff
+#define BIT_RXQ_HW_IDX_8822C(x)                                                \
+	(((x) & BIT_MASK_RXQ_HW_IDX_8822C) << BIT_SHIFT_RXQ_HW_IDX_8822C)
+#define BITS_RXQ_HW_IDX_8822C                                                  \
+	(BIT_MASK_RXQ_HW_IDX_8822C << BIT_SHIFT_RXQ_HW_IDX_8822C)
+#define BIT_CLEAR_RXQ_HW_IDX_8822C(x) ((x) & (~BITS_RXQ_HW_IDX_8822C))
+#define BIT_GET_RXQ_HW_IDX_8822C(x)                                            \
+	(((x) >> BIT_SHIFT_RXQ_HW_IDX_8822C) & BIT_MASK_RXQ_HW_IDX_8822C)
+#define BIT_SET_RXQ_HW_IDX_8822C(x, v)                                         \
+	(BIT_CLEAR_RXQ_HW_IDX_8822C(x) | BIT_RXQ_HW_IDX_8822C(v))
+
+#define BIT_SHIFT_RXQ_HOST_IDX_8822C 0
+#define BIT_MASK_RXQ_HOST_IDX_8822C 0xfff
+#define BIT_RXQ_HOST_IDX_8822C(x)                                              \
+	(((x) & BIT_MASK_RXQ_HOST_IDX_8822C) << BIT_SHIFT_RXQ_HOST_IDX_8822C)
+#define BITS_RXQ_HOST_IDX_8822C                                                \
+	(BIT_MASK_RXQ_HOST_IDX_8822C << BIT_SHIFT_RXQ_HOST_IDX_8822C)
+#define BIT_CLEAR_RXQ_HOST_IDX_8822C(x) ((x) & (~BITS_RXQ_HOST_IDX_8822C))
+#define BIT_GET_RXQ_HOST_IDX_8822C(x)                                          \
+	(((x) >> BIT_SHIFT_RXQ_HOST_IDX_8822C) & BIT_MASK_RXQ_HOST_IDX_8822C)
+#define BIT_SET_RXQ_HOST_IDX_8822C(x, v)                                       \
+	(BIT_CLEAR_RXQ_HOST_IDX_8822C(x) | BIT_RXQ_HOST_IDX_8822C(v))
+
+/* 2 REG_HI0Q_TXBD_IDX_8822C */
+
+#define BIT_SHIFT_HI0Q_HW_IDX_8822C 16
+#define BIT_MASK_HI0Q_HW_IDX_8822C 0xfff
+#define BIT_HI0Q_HW_IDX_8822C(x)                                               \
+	(((x) & BIT_MASK_HI0Q_HW_IDX_8822C) << BIT_SHIFT_HI0Q_HW_IDX_8822C)
+#define BITS_HI0Q_HW_IDX_8822C                                                 \
+	(BIT_MASK_HI0Q_HW_IDX_8822C << BIT_SHIFT_HI0Q_HW_IDX_8822C)
+#define BIT_CLEAR_HI0Q_HW_IDX_8822C(x) ((x) & (~BITS_HI0Q_HW_IDX_8822C))
+#define BIT_GET_HI0Q_HW_IDX_8822C(x)                                           \
+	(((x) >> BIT_SHIFT_HI0Q_HW_IDX_8822C) & BIT_MASK_HI0Q_HW_IDX_8822C)
+#define BIT_SET_HI0Q_HW_IDX_8822C(x, v)                                        \
+	(BIT_CLEAR_HI0Q_HW_IDX_8822C(x) | BIT_HI0Q_HW_IDX_8822C(v))
+
+#define BIT_SHIFT_HI0Q_HOST_IDX_8822C 0
+#define BIT_MASK_HI0Q_HOST_IDX_8822C 0xfff
+#define BIT_HI0Q_HOST_IDX_8822C(x)                                             \
+	(((x) & BIT_MASK_HI0Q_HOST_IDX_8822C) << BIT_SHIFT_HI0Q_HOST_IDX_8822C)
+#define BITS_HI0Q_HOST_IDX_8822C                                               \
+	(BIT_MASK_HI0Q_HOST_IDX_8822C << BIT_SHIFT_HI0Q_HOST_IDX_8822C)
+#define BIT_CLEAR_HI0Q_HOST_IDX_8822C(x) ((x) & (~BITS_HI0Q_HOST_IDX_8822C))
+#define BIT_GET_HI0Q_HOST_IDX_8822C(x)                                         \
+	(((x) >> BIT_SHIFT_HI0Q_HOST_IDX_8822C) & BIT_MASK_HI0Q_HOST_IDX_8822C)
+#define BIT_SET_HI0Q_HOST_IDX_8822C(x, v)                                      \
+	(BIT_CLEAR_HI0Q_HOST_IDX_8822C(x) | BIT_HI0Q_HOST_IDX_8822C(v))
+
+/* 2 REG_HI1Q_TXBD_IDX_8822C */
+
+#define BIT_SHIFT_HI1Q_HW_IDX_8822C 16
+#define BIT_MASK_HI1Q_HW_IDX_8822C 0xfff
+#define BIT_HI1Q_HW_IDX_8822C(x)                                               \
+	(((x) & BIT_MASK_HI1Q_HW_IDX_8822C) << BIT_SHIFT_HI1Q_HW_IDX_8822C)
+#define BITS_HI1Q_HW_IDX_8822C                                                 \
+	(BIT_MASK_HI1Q_HW_IDX_8822C << BIT_SHIFT_HI1Q_HW_IDX_8822C)
+#define BIT_CLEAR_HI1Q_HW_IDX_8822C(x) ((x) & (~BITS_HI1Q_HW_IDX_8822C))
+#define BIT_GET_HI1Q_HW_IDX_8822C(x)                                           \
+	(((x) >> BIT_SHIFT_HI1Q_HW_IDX_8822C) & BIT_MASK_HI1Q_HW_IDX_8822C)
+#define BIT_SET_HI1Q_HW_IDX_8822C(x, v)                                        \
+	(BIT_CLEAR_HI1Q_HW_IDX_8822C(x) | BIT_HI1Q_HW_IDX_8822C(v))
+
+#define BIT_SHIFT_HI1Q_HOST_IDX_8822C 0
+#define BIT_MASK_HI1Q_HOST_IDX_8822C 0xfff
+#define BIT_HI1Q_HOST_IDX_8822C(x)                                             \
+	(((x) & BIT_MASK_HI1Q_HOST_IDX_8822C) << BIT_SHIFT_HI1Q_HOST_IDX_8822C)
+#define BITS_HI1Q_HOST_IDX_8822C                                               \
+	(BIT_MASK_HI1Q_HOST_IDX_8822C << BIT_SHIFT_HI1Q_HOST_IDX_8822C)
+#define BIT_CLEAR_HI1Q_HOST_IDX_8822C(x) ((x) & (~BITS_HI1Q_HOST_IDX_8822C))
+#define BIT_GET_HI1Q_HOST_IDX_8822C(x)                                         \
+	(((x) >> BIT_SHIFT_HI1Q_HOST_IDX_8822C) & BIT_MASK_HI1Q_HOST_IDX_8822C)
+#define BIT_SET_HI1Q_HOST_IDX_8822C(x, v)                                      \
+	(BIT_CLEAR_HI1Q_HOST_IDX_8822C(x) | BIT_HI1Q_HOST_IDX_8822C(v))
+
+/* 2 REG_HI2Q_TXBD_IDX_8822C */
+
+#define BIT_SHIFT_HI2Q_HW_IDX_8822C 16
+#define BIT_MASK_HI2Q_HW_IDX_8822C 0xfff
+#define BIT_HI2Q_HW_IDX_8822C(x)                                               \
+	(((x) & BIT_MASK_HI2Q_HW_IDX_8822C) << BIT_SHIFT_HI2Q_HW_IDX_8822C)
+#define BITS_HI2Q_HW_IDX_8822C                                                 \
+	(BIT_MASK_HI2Q_HW_IDX_8822C << BIT_SHIFT_HI2Q_HW_IDX_8822C)
+#define BIT_CLEAR_HI2Q_HW_IDX_8822C(x) ((x) & (~BITS_HI2Q_HW_IDX_8822C))
+#define BIT_GET_HI2Q_HW_IDX_8822C(x)                                           \
+	(((x) >> BIT_SHIFT_HI2Q_HW_IDX_8822C) & BIT_MASK_HI2Q_HW_IDX_8822C)
+#define BIT_SET_HI2Q_HW_IDX_8822C(x, v)                                        \
+	(BIT_CLEAR_HI2Q_HW_IDX_8822C(x) | BIT_HI2Q_HW_IDX_8822C(v))
+
+#define BIT_SHIFT_HI2Q_HOST_IDX_8822C 0
+#define BIT_MASK_HI2Q_HOST_IDX_8822C 0xfff
+#define BIT_HI2Q_HOST_IDX_8822C(x)                                             \
+	(((x) & BIT_MASK_HI2Q_HOST_IDX_8822C) << BIT_SHIFT_HI2Q_HOST_IDX_8822C)
+#define BITS_HI2Q_HOST_IDX_8822C                                               \
+	(BIT_MASK_HI2Q_HOST_IDX_8822C << BIT_SHIFT_HI2Q_HOST_IDX_8822C)
+#define BIT_CLEAR_HI2Q_HOST_IDX_8822C(x) ((x) & (~BITS_HI2Q_HOST_IDX_8822C))
+#define BIT_GET_HI2Q_HOST_IDX_8822C(x)                                         \
+	(((x) >> BIT_SHIFT_HI2Q_HOST_IDX_8822C) & BIT_MASK_HI2Q_HOST_IDX_8822C)
+#define BIT_SET_HI2Q_HOST_IDX_8822C(x, v)                                      \
+	(BIT_CLEAR_HI2Q_HOST_IDX_8822C(x) | BIT_HI2Q_HOST_IDX_8822C(v))
+
+/* 2 REG_HI3Q_TXBD_IDX_8822C */
+
+#define BIT_SHIFT_HI3Q_HW_IDX_8822C 16
+#define BIT_MASK_HI3Q_HW_IDX_8822C 0xfff
+#define BIT_HI3Q_HW_IDX_8822C(x)                                               \
+	(((x) & BIT_MASK_HI3Q_HW_IDX_8822C) << BIT_SHIFT_HI3Q_HW_IDX_8822C)
+#define BITS_HI3Q_HW_IDX_8822C                                                 \
+	(BIT_MASK_HI3Q_HW_IDX_8822C << BIT_SHIFT_HI3Q_HW_IDX_8822C)
+#define BIT_CLEAR_HI3Q_HW_IDX_8822C(x) ((x) & (~BITS_HI3Q_HW_IDX_8822C))
+#define BIT_GET_HI3Q_HW_IDX_8822C(x)                                           \
+	(((x) >> BIT_SHIFT_HI3Q_HW_IDX_8822C) & BIT_MASK_HI3Q_HW_IDX_8822C)
+#define BIT_SET_HI3Q_HW_IDX_8822C(x, v)                                        \
+	(BIT_CLEAR_HI3Q_HW_IDX_8822C(x) | BIT_HI3Q_HW_IDX_8822C(v))
+
+#define BIT_SHIFT_HI3Q_HOST_IDX_8822C 0
+#define BIT_MASK_HI3Q_HOST_IDX_8822C 0xfff
+#define BIT_HI3Q_HOST_IDX_8822C(x)                                             \
+	(((x) & BIT_MASK_HI3Q_HOST_IDX_8822C) << BIT_SHIFT_HI3Q_HOST_IDX_8822C)
+#define BITS_HI3Q_HOST_IDX_8822C                                               \
+	(BIT_MASK_HI3Q_HOST_IDX_8822C << BIT_SHIFT_HI3Q_HOST_IDX_8822C)
+#define BIT_CLEAR_HI3Q_HOST_IDX_8822C(x) ((x) & (~BITS_HI3Q_HOST_IDX_8822C))
+#define BIT_GET_HI3Q_HOST_IDX_8822C(x)                                         \
+	(((x) >> BIT_SHIFT_HI3Q_HOST_IDX_8822C) & BIT_MASK_HI3Q_HOST_IDX_8822C)
+#define BIT_SET_HI3Q_HOST_IDX_8822C(x, v)                                      \
+	(BIT_CLEAR_HI3Q_HOST_IDX_8822C(x) | BIT_HI3Q_HOST_IDX_8822C(v))
+
+/* 2 REG_HI4Q_TXBD_IDX_8822C */
+
+#define BIT_SHIFT_HI4Q_HW_IDX_8822C 16
+#define BIT_MASK_HI4Q_HW_IDX_8822C 0xfff
+#define BIT_HI4Q_HW_IDX_8822C(x)                                               \
+	(((x) & BIT_MASK_HI4Q_HW_IDX_8822C) << BIT_SHIFT_HI4Q_HW_IDX_8822C)
+#define BITS_HI4Q_HW_IDX_8822C                                                 \
+	(BIT_MASK_HI4Q_HW_IDX_8822C << BIT_SHIFT_HI4Q_HW_IDX_8822C)
+#define BIT_CLEAR_HI4Q_HW_IDX_8822C(x) ((x) & (~BITS_HI4Q_HW_IDX_8822C))
+#define BIT_GET_HI4Q_HW_IDX_8822C(x)                                           \
+	(((x) >> BIT_SHIFT_HI4Q_HW_IDX_8822C) & BIT_MASK_HI4Q_HW_IDX_8822C)
+#define BIT_SET_HI4Q_HW_IDX_8822C(x, v)                                        \
+	(BIT_CLEAR_HI4Q_HW_IDX_8822C(x) | BIT_HI4Q_HW_IDX_8822C(v))
+
+#define BIT_SHIFT_HI4Q_HOST_IDX_8822C 0
+#define BIT_MASK_HI4Q_HOST_IDX_8822C 0xfff
+#define BIT_HI4Q_HOST_IDX_8822C(x)                                             \
+	(((x) & BIT_MASK_HI4Q_HOST_IDX_8822C) << BIT_SHIFT_HI4Q_HOST_IDX_8822C)
+#define BITS_HI4Q_HOST_IDX_8822C                                               \
+	(BIT_MASK_HI4Q_HOST_IDX_8822C << BIT_SHIFT_HI4Q_HOST_IDX_8822C)
+#define BIT_CLEAR_HI4Q_HOST_IDX_8822C(x) ((x) & (~BITS_HI4Q_HOST_IDX_8822C))
+#define BIT_GET_HI4Q_HOST_IDX_8822C(x)                                         \
+	(((x) >> BIT_SHIFT_HI4Q_HOST_IDX_8822C) & BIT_MASK_HI4Q_HOST_IDX_8822C)
+#define BIT_SET_HI4Q_HOST_IDX_8822C(x, v)                                      \
+	(BIT_CLEAR_HI4Q_HOST_IDX_8822C(x) | BIT_HI4Q_HOST_IDX_8822C(v))
+
+/* 2 REG_HI5Q_TXBD_IDX_8822C */
+
+#define BIT_SHIFT_HI5Q_HW_IDX_8822C 16
+#define BIT_MASK_HI5Q_HW_IDX_8822C 0xfff
+#define BIT_HI5Q_HW_IDX_8822C(x)                                               \
+	(((x) & BIT_MASK_HI5Q_HW_IDX_8822C) << BIT_SHIFT_HI5Q_HW_IDX_8822C)
+#define BITS_HI5Q_HW_IDX_8822C                                                 \
+	(BIT_MASK_HI5Q_HW_IDX_8822C << BIT_SHIFT_HI5Q_HW_IDX_8822C)
+#define BIT_CLEAR_HI5Q_HW_IDX_8822C(x) ((x) & (~BITS_HI5Q_HW_IDX_8822C))
+#define BIT_GET_HI5Q_HW_IDX_8822C(x)                                           \
+	(((x) >> BIT_SHIFT_HI5Q_HW_IDX_8822C) & BIT_MASK_HI5Q_HW_IDX_8822C)
+#define BIT_SET_HI5Q_HW_IDX_8822C(x, v)                                        \
+	(BIT_CLEAR_HI5Q_HW_IDX_8822C(x) | BIT_HI5Q_HW_IDX_8822C(v))
+
+#define BIT_SHIFT_HI5Q_HOST_IDX_8822C 0
+#define BIT_MASK_HI5Q_HOST_IDX_8822C 0xfff
+#define BIT_HI5Q_HOST_IDX_8822C(x)                                             \
+	(((x) & BIT_MASK_HI5Q_HOST_IDX_8822C) << BIT_SHIFT_HI5Q_HOST_IDX_8822C)
+#define BITS_HI5Q_HOST_IDX_8822C                                               \
+	(BIT_MASK_HI5Q_HOST_IDX_8822C << BIT_SHIFT_HI5Q_HOST_IDX_8822C)
+#define BIT_CLEAR_HI5Q_HOST_IDX_8822C(x) ((x) & (~BITS_HI5Q_HOST_IDX_8822C))
+#define BIT_GET_HI5Q_HOST_IDX_8822C(x)                                         \
+	(((x) >> BIT_SHIFT_HI5Q_HOST_IDX_8822C) & BIT_MASK_HI5Q_HOST_IDX_8822C)
+#define BIT_SET_HI5Q_HOST_IDX_8822C(x, v)                                      \
+	(BIT_CLEAR_HI5Q_HOST_IDX_8822C(x) | BIT_HI5Q_HOST_IDX_8822C(v))
+
+/* 2 REG_HI6Q_TXBD_IDX_8822C */
+
+#define BIT_SHIFT_HI6Q_HW_IDX_8822C 16
+#define BIT_MASK_HI6Q_HW_IDX_8822C 0xfff
+#define BIT_HI6Q_HW_IDX_8822C(x)                                               \
+	(((x) & BIT_MASK_HI6Q_HW_IDX_8822C) << BIT_SHIFT_HI6Q_HW_IDX_8822C)
+#define BITS_HI6Q_HW_IDX_8822C                                                 \
+	(BIT_MASK_HI6Q_HW_IDX_8822C << BIT_SHIFT_HI6Q_HW_IDX_8822C)
+#define BIT_CLEAR_HI6Q_HW_IDX_8822C(x) ((x) & (~BITS_HI6Q_HW_IDX_8822C))
+#define BIT_GET_HI6Q_HW_IDX_8822C(x)                                           \
+	(((x) >> BIT_SHIFT_HI6Q_HW_IDX_8822C) & BIT_MASK_HI6Q_HW_IDX_8822C)
+#define BIT_SET_HI6Q_HW_IDX_8822C(x, v)                                        \
+	(BIT_CLEAR_HI6Q_HW_IDX_8822C(x) | BIT_HI6Q_HW_IDX_8822C(v))
+
+#define BIT_SHIFT_HI6Q_HOST_IDX_8822C 0
+#define BIT_MASK_HI6Q_HOST_IDX_8822C 0xfff
+#define BIT_HI6Q_HOST_IDX_8822C(x)                                             \
+	(((x) & BIT_MASK_HI6Q_HOST_IDX_8822C) << BIT_SHIFT_HI6Q_HOST_IDX_8822C)
+#define BITS_HI6Q_HOST_IDX_8822C                                               \
+	(BIT_MASK_HI6Q_HOST_IDX_8822C << BIT_SHIFT_HI6Q_HOST_IDX_8822C)
+#define BIT_CLEAR_HI6Q_HOST_IDX_8822C(x) ((x) & (~BITS_HI6Q_HOST_IDX_8822C))
+#define BIT_GET_HI6Q_HOST_IDX_8822C(x)                                         \
+	(((x) >> BIT_SHIFT_HI6Q_HOST_IDX_8822C) & BIT_MASK_HI6Q_HOST_IDX_8822C)
+#define BIT_SET_HI6Q_HOST_IDX_8822C(x, v)                                      \
+	(BIT_CLEAR_HI6Q_HOST_IDX_8822C(x) | BIT_HI6Q_HOST_IDX_8822C(v))
+
+/* 2 REG_HI7Q_TXBD_IDX_8822C */
+
+#define BIT_SHIFT_HI7Q_HW_IDX_8822C 16
+#define BIT_MASK_HI7Q_HW_IDX_8822C 0xfff
+#define BIT_HI7Q_HW_IDX_8822C(x)                                               \
+	(((x) & BIT_MASK_HI7Q_HW_IDX_8822C) << BIT_SHIFT_HI7Q_HW_IDX_8822C)
+#define BITS_HI7Q_HW_IDX_8822C                                                 \
+	(BIT_MASK_HI7Q_HW_IDX_8822C << BIT_SHIFT_HI7Q_HW_IDX_8822C)
+#define BIT_CLEAR_HI7Q_HW_IDX_8822C(x) ((x) & (~BITS_HI7Q_HW_IDX_8822C))
+#define BIT_GET_HI7Q_HW_IDX_8822C(x)                                           \
+	(((x) >> BIT_SHIFT_HI7Q_HW_IDX_8822C) & BIT_MASK_HI7Q_HW_IDX_8822C)
+#define BIT_SET_HI7Q_HW_IDX_8822C(x, v)                                        \
+	(BIT_CLEAR_HI7Q_HW_IDX_8822C(x) | BIT_HI7Q_HW_IDX_8822C(v))
+
+#define BIT_SHIFT_HI7Q_HOST_IDX_8822C 0
+#define BIT_MASK_HI7Q_HOST_IDX_8822C 0xfff
+#define BIT_HI7Q_HOST_IDX_8822C(x)                                             \
+	(((x) & BIT_MASK_HI7Q_HOST_IDX_8822C) << BIT_SHIFT_HI7Q_HOST_IDX_8822C)
+#define BITS_HI7Q_HOST_IDX_8822C                                               \
+	(BIT_MASK_HI7Q_HOST_IDX_8822C << BIT_SHIFT_HI7Q_HOST_IDX_8822C)
+#define BIT_CLEAR_HI7Q_HOST_IDX_8822C(x) ((x) & (~BITS_HI7Q_HOST_IDX_8822C))
+#define BIT_GET_HI7Q_HOST_IDX_8822C(x)                                         \
+	(((x) >> BIT_SHIFT_HI7Q_HOST_IDX_8822C) & BIT_MASK_HI7Q_HOST_IDX_8822C)
+#define BIT_SET_HI7Q_HOST_IDX_8822C(x, v)                                      \
+	(BIT_CLEAR_HI7Q_HOST_IDX_8822C(x) | BIT_HI7Q_HOST_IDX_8822C(v))
+
+/* 2 REG_DBG_SEL_V1_8822C */
+
+#define BIT_SHIFT_DBG_SEL_8822C 0
+#define BIT_MASK_DBG_SEL_8822C 0xff
+#define BIT_DBG_SEL_8822C(x)                                                   \
+	(((x) & BIT_MASK_DBG_SEL_8822C) << BIT_SHIFT_DBG_SEL_8822C)
+#define BITS_DBG_SEL_8822C (BIT_MASK_DBG_SEL_8822C << BIT_SHIFT_DBG_SEL_8822C)
+#define BIT_CLEAR_DBG_SEL_8822C(x) ((x) & (~BITS_DBG_SEL_8822C))
+#define BIT_GET_DBG_SEL_8822C(x)                                               \
+	(((x) >> BIT_SHIFT_DBG_SEL_8822C) & BIT_MASK_DBG_SEL_8822C)
+#define BIT_SET_DBG_SEL_8822C(x, v)                                            \
+	(BIT_CLEAR_DBG_SEL_8822C(x) | BIT_DBG_SEL_8822C(v))
+
+/* 2 REG_PCIE_HRPWM1_V1_8822C */
+
+#define BIT_SHIFT_PCIE_HRPWM_8822C 0
+#define BIT_MASK_PCIE_HRPWM_8822C 0xff
+#define BIT_PCIE_HRPWM_8822C(x)                                                \
+	(((x) & BIT_MASK_PCIE_HRPWM_8822C) << BIT_SHIFT_PCIE_HRPWM_8822C)
+#define BITS_PCIE_HRPWM_8822C                                                  \
+	(BIT_MASK_PCIE_HRPWM_8822C << BIT_SHIFT_PCIE_HRPWM_8822C)
+#define BIT_CLEAR_PCIE_HRPWM_8822C(x) ((x) & (~BITS_PCIE_HRPWM_8822C))
+#define BIT_GET_PCIE_HRPWM_8822C(x)                                            \
+	(((x) >> BIT_SHIFT_PCIE_HRPWM_8822C) & BIT_MASK_PCIE_HRPWM_8822C)
+#define BIT_SET_PCIE_HRPWM_8822C(x, v)                                         \
+	(BIT_CLEAR_PCIE_HRPWM_8822C(x) | BIT_PCIE_HRPWM_8822C(v))
+
+/* 2 REG_PCIE_HCPWM1_V1_8822C */
+
+#define BIT_SHIFT_PCIE_HCPWM_8822C 0
+#define BIT_MASK_PCIE_HCPWM_8822C 0xff
+#define BIT_PCIE_HCPWM_8822C(x)                                                \
+	(((x) & BIT_MASK_PCIE_HCPWM_8822C) << BIT_SHIFT_PCIE_HCPWM_8822C)
+#define BITS_PCIE_HCPWM_8822C                                                  \
+	(BIT_MASK_PCIE_HCPWM_8822C << BIT_SHIFT_PCIE_HCPWM_8822C)
+#define BIT_CLEAR_PCIE_HCPWM_8822C(x) ((x) & (~BITS_PCIE_HCPWM_8822C))
+#define BIT_GET_PCIE_HCPWM_8822C(x)                                            \
+	(((x) >> BIT_SHIFT_PCIE_HCPWM_8822C) & BIT_MASK_PCIE_HCPWM_8822C)
+#define BIT_SET_PCIE_HCPWM_8822C(x, v)                                         \
+	(BIT_CLEAR_PCIE_HCPWM_8822C(x) | BIT_PCIE_HCPWM_8822C(v))
+
+/* 2 REG_PCIE_CTRL2_8822C */
+#define BIT_DIS_TXDMA_PRE_8822C BIT(7)
+#define BIT_DIS_RXDMA_PRE_8822C BIT(6)
+
+#define BIT_SHIFT_HPS_CLKR_PCIE_8822C 4
+#define BIT_MASK_HPS_CLKR_PCIE_8822C 0x3
+#define BIT_HPS_CLKR_PCIE_8822C(x)                                             \
+	(((x) & BIT_MASK_HPS_CLKR_PCIE_8822C) << BIT_SHIFT_HPS_CLKR_PCIE_8822C)
+#define BITS_HPS_CLKR_PCIE_8822C                                               \
+	(BIT_MASK_HPS_CLKR_PCIE_8822C << BIT_SHIFT_HPS_CLKR_PCIE_8822C)
+#define BIT_CLEAR_HPS_CLKR_PCIE_8822C(x) ((x) & (~BITS_HPS_CLKR_PCIE_8822C))
+#define BIT_GET_HPS_CLKR_PCIE_8822C(x)                                         \
+	(((x) >> BIT_SHIFT_HPS_CLKR_PCIE_8822C) & BIT_MASK_HPS_CLKR_PCIE_8822C)
+#define BIT_SET_HPS_CLKR_PCIE_8822C(x, v)                                      \
+	(BIT_CLEAR_HPS_CLKR_PCIE_8822C(x) | BIT_HPS_CLKR_PCIE_8822C(v))
+
+#define BIT_PCIE_INT_8822C BIT(3)
+#define BIT_TXFLAG_EXIT_L1_EN_8822C BIT(2)
+#define BIT_EN_RXDMA_ALIGN_8822C BIT(1)
+#define BIT_EN_TXDMA_ALIGN_8822C BIT(0)
+
+/* 2 REG_PCIE_HRPWM2_V1_8822C */
+
+#define BIT_SHIFT_PCIE_HRPWM2_8822C 0
+#define BIT_MASK_PCIE_HRPWM2_8822C 0xffff
+#define BIT_PCIE_HRPWM2_8822C(x)                                               \
+	(((x) & BIT_MASK_PCIE_HRPWM2_8822C) << BIT_SHIFT_PCIE_HRPWM2_8822C)
+#define BITS_PCIE_HRPWM2_8822C                                                 \
+	(BIT_MASK_PCIE_HRPWM2_8822C << BIT_SHIFT_PCIE_HRPWM2_8822C)
+#define BIT_CLEAR_PCIE_HRPWM2_8822C(x) ((x) & (~BITS_PCIE_HRPWM2_8822C))
+#define BIT_GET_PCIE_HRPWM2_8822C(x)                                           \
+	(((x) >> BIT_SHIFT_PCIE_HRPWM2_8822C) & BIT_MASK_PCIE_HRPWM2_8822C)
+#define BIT_SET_PCIE_HRPWM2_8822C(x, v)                                        \
+	(BIT_CLEAR_PCIE_HRPWM2_8822C(x) | BIT_PCIE_HRPWM2_8822C(v))
+
+/* 2 REG_PCIE_HCPWM2_V1_8822C */
+
+#define BIT_SHIFT_PCIE_HCPWM2_8822C 0
+#define BIT_MASK_PCIE_HCPWM2_8822C 0xffff
+#define BIT_PCIE_HCPWM2_8822C(x)                                               \
+	(((x) & BIT_MASK_PCIE_HCPWM2_8822C) << BIT_SHIFT_PCIE_HCPWM2_8822C)
+#define BITS_PCIE_HCPWM2_8822C                                                 \
+	(BIT_MASK_PCIE_HCPWM2_8822C << BIT_SHIFT_PCIE_HCPWM2_8822C)
+#define BIT_CLEAR_PCIE_HCPWM2_8822C(x) ((x) & (~BITS_PCIE_HCPWM2_8822C))
+#define BIT_GET_PCIE_HCPWM2_8822C(x)                                           \
+	(((x) >> BIT_SHIFT_PCIE_HCPWM2_8822C) & BIT_MASK_PCIE_HCPWM2_8822C)
+#define BIT_SET_PCIE_HCPWM2_8822C(x, v)                                        \
+	(BIT_CLEAR_PCIE_HCPWM2_8822C(x) | BIT_PCIE_HCPWM2_8822C(v))
+
+/* 2 REG_PCIE_H2C_MSG_V1_8822C */
+
+#define BIT_SHIFT_DRV2FW_INFO_8822C 0
+#define BIT_MASK_DRV2FW_INFO_8822C 0xffffffffL
+#define BIT_DRV2FW_INFO_8822C(x)                                               \
+	(((x) & BIT_MASK_DRV2FW_INFO_8822C) << BIT_SHIFT_DRV2FW_INFO_8822C)
+#define BITS_DRV2FW_INFO_8822C                                                 \
+	(BIT_MASK_DRV2FW_INFO_8822C << BIT_SHIFT_DRV2FW_INFO_8822C)
+#define BIT_CLEAR_DRV2FW_INFO_8822C(x) ((x) & (~BITS_DRV2FW_INFO_8822C))
+#define BIT_GET_DRV2FW_INFO_8822C(x)                                           \
+	(((x) >> BIT_SHIFT_DRV2FW_INFO_8822C) & BIT_MASK_DRV2FW_INFO_8822C)
+#define BIT_SET_DRV2FW_INFO_8822C(x, v)                                        \
+	(BIT_CLEAR_DRV2FW_INFO_8822C(x) | BIT_DRV2FW_INFO_8822C(v))
+
+/* 2 REG_PCIE_C2H_MSG_V1_8822C */
+
+#define BIT_SHIFT_HCI_PCIE_C2H_MSG_8822C 0
+#define BIT_MASK_HCI_PCIE_C2H_MSG_8822C 0xffffffffL
+#define BIT_HCI_PCIE_C2H_MSG_8822C(x)                                          \
+	(((x) & BIT_MASK_HCI_PCIE_C2H_MSG_8822C)                               \
+	 << BIT_SHIFT_HCI_PCIE_C2H_MSG_8822C)
+#define BITS_HCI_PCIE_C2H_MSG_8822C                                            \
+	(BIT_MASK_HCI_PCIE_C2H_MSG_8822C << BIT_SHIFT_HCI_PCIE_C2H_MSG_8822C)
+#define BIT_CLEAR_HCI_PCIE_C2H_MSG_8822C(x)                                    \
+	((x) & (~BITS_HCI_PCIE_C2H_MSG_8822C))
+#define BIT_GET_HCI_PCIE_C2H_MSG_8822C(x)                                      \
+	(((x) >> BIT_SHIFT_HCI_PCIE_C2H_MSG_8822C) &                           \
+	 BIT_MASK_HCI_PCIE_C2H_MSG_8822C)
+#define BIT_SET_HCI_PCIE_C2H_MSG_8822C(x, v)                                   \
+	(BIT_CLEAR_HCI_PCIE_C2H_MSG_8822C(x) | BIT_HCI_PCIE_C2H_MSG_8822C(v))
+
+/* 2 REG_DBI_WDATA_V1_8822C */
+
+#define BIT_SHIFT_DBI_WDATA_8822C 0
+#define BIT_MASK_DBI_WDATA_8822C 0xffffffffL
+#define BIT_DBI_WDATA_8822C(x)                                                 \
+	(((x) & BIT_MASK_DBI_WDATA_8822C) << BIT_SHIFT_DBI_WDATA_8822C)
+#define BITS_DBI_WDATA_8822C                                                   \
+	(BIT_MASK_DBI_WDATA_8822C << BIT_SHIFT_DBI_WDATA_8822C)
+#define BIT_CLEAR_DBI_WDATA_8822C(x) ((x) & (~BITS_DBI_WDATA_8822C))
+#define BIT_GET_DBI_WDATA_8822C(x)                                             \
+	(((x) >> BIT_SHIFT_DBI_WDATA_8822C) & BIT_MASK_DBI_WDATA_8822C)
+#define BIT_SET_DBI_WDATA_8822C(x, v)                                          \
+	(BIT_CLEAR_DBI_WDATA_8822C(x) | BIT_DBI_WDATA_8822C(v))
+
+/* 2 REG_DBI_RDATA_V1_8822C */
+
+#define BIT_SHIFT_DBI_RDATA_8822C 0
+#define BIT_MASK_DBI_RDATA_8822C 0xffffffffL
+#define BIT_DBI_RDATA_8822C(x)                                                 \
+	(((x) & BIT_MASK_DBI_RDATA_8822C) << BIT_SHIFT_DBI_RDATA_8822C)
+#define BITS_DBI_RDATA_8822C                                                   \
+	(BIT_MASK_DBI_RDATA_8822C << BIT_SHIFT_DBI_RDATA_8822C)
+#define BIT_CLEAR_DBI_RDATA_8822C(x) ((x) & (~BITS_DBI_RDATA_8822C))
+#define BIT_GET_DBI_RDATA_8822C(x)                                             \
+	(((x) >> BIT_SHIFT_DBI_RDATA_8822C) & BIT_MASK_DBI_RDATA_8822C)
+#define BIT_SET_DBI_RDATA_8822C(x, v)                                          \
+	(BIT_CLEAR_DBI_RDATA_8822C(x) | BIT_DBI_RDATA_8822C(v))
+
+/* 2 REG_DBI_FLAG_V1_8822C */
+#define BIT_EN_STUCK_DBG_8822C BIT(26)
+#define BIT_RX_STUCK_8822C BIT(25)
+#define BIT_TX_STUCK_8822C BIT(24)
+#define BIT_DBI_RFLAG_8822C BIT(17)
+#define BIT_DBI_WFLAG_8822C BIT(16)
+
+#define BIT_SHIFT_DBI_WREN_8822C 12
+#define BIT_MASK_DBI_WREN_8822C 0xf
+#define BIT_DBI_WREN_8822C(x)                                                  \
+	(((x) & BIT_MASK_DBI_WREN_8822C) << BIT_SHIFT_DBI_WREN_8822C)
+#define BITS_DBI_WREN_8822C                                                    \
+	(BIT_MASK_DBI_WREN_8822C << BIT_SHIFT_DBI_WREN_8822C)
+#define BIT_CLEAR_DBI_WREN_8822C(x) ((x) & (~BITS_DBI_WREN_8822C))
+#define BIT_GET_DBI_WREN_8822C(x)                                              \
+	(((x) >> BIT_SHIFT_DBI_WREN_8822C) & BIT_MASK_DBI_WREN_8822C)
+#define BIT_SET_DBI_WREN_8822C(x, v)                                           \
+	(BIT_CLEAR_DBI_WREN_8822C(x) | BIT_DBI_WREN_8822C(v))
+
+#define BIT_SHIFT_DBI_ADDR_8822C 0
+#define BIT_MASK_DBI_ADDR_8822C 0xfff
+#define BIT_DBI_ADDR_8822C(x)                                                  \
+	(((x) & BIT_MASK_DBI_ADDR_8822C) << BIT_SHIFT_DBI_ADDR_8822C)
+#define BITS_DBI_ADDR_8822C                                                    \
+	(BIT_MASK_DBI_ADDR_8822C << BIT_SHIFT_DBI_ADDR_8822C)
+#define BIT_CLEAR_DBI_ADDR_8822C(x) ((x) & (~BITS_DBI_ADDR_8822C))
+#define BIT_GET_DBI_ADDR_8822C(x)                                              \
+	(((x) >> BIT_SHIFT_DBI_ADDR_8822C) & BIT_MASK_DBI_ADDR_8822C)
+#define BIT_SET_DBI_ADDR_8822C(x, v)                                           \
+	(BIT_CLEAR_DBI_ADDR_8822C(x) | BIT_DBI_ADDR_8822C(v))
+
+/* 2 REG_MDIO_V1_8822C */
+
+#define BIT_SHIFT_MDIO_RDATA_8822C 16
+#define BIT_MASK_MDIO_RDATA_8822C 0xffff
+#define BIT_MDIO_RDATA_8822C(x)                                                \
+	(((x) & BIT_MASK_MDIO_RDATA_8822C) << BIT_SHIFT_MDIO_RDATA_8822C)
+#define BITS_MDIO_RDATA_8822C                                                  \
+	(BIT_MASK_MDIO_RDATA_8822C << BIT_SHIFT_MDIO_RDATA_8822C)
+#define BIT_CLEAR_MDIO_RDATA_8822C(x) ((x) & (~BITS_MDIO_RDATA_8822C))
+#define BIT_GET_MDIO_RDATA_8822C(x)                                            \
+	(((x) >> BIT_SHIFT_MDIO_RDATA_8822C) & BIT_MASK_MDIO_RDATA_8822C)
+#define BIT_SET_MDIO_RDATA_8822C(x, v)                                         \
+	(BIT_CLEAR_MDIO_RDATA_8822C(x) | BIT_MDIO_RDATA_8822C(v))
+
+#define BIT_SHIFT_MDIO_WDATA_8822C 0
+#define BIT_MASK_MDIO_WDATA_8822C 0xffff
+#define BIT_MDIO_WDATA_8822C(x)                                                \
+	(((x) & BIT_MASK_MDIO_WDATA_8822C) << BIT_SHIFT_MDIO_WDATA_8822C)
+#define BITS_MDIO_WDATA_8822C                                                  \
+	(BIT_MASK_MDIO_WDATA_8822C << BIT_SHIFT_MDIO_WDATA_8822C)
+#define BIT_CLEAR_MDIO_WDATA_8822C(x) ((x) & (~BITS_MDIO_WDATA_8822C))
+#define BIT_GET_MDIO_WDATA_8822C(x)                                            \
+	(((x) >> BIT_SHIFT_MDIO_WDATA_8822C) & BIT_MASK_MDIO_WDATA_8822C)
+#define BIT_SET_MDIO_WDATA_8822C(x, v)                                         \
+	(BIT_CLEAR_MDIO_WDATA_8822C(x) | BIT_MDIO_WDATA_8822C(v))
+
+/* 2 REG_PCIE_MIX_CFG_8822C */
+
+#define BIT_SHIFT_MDIO_PHY_ADDR_8822C 24
+#define BIT_MASK_MDIO_PHY_ADDR_8822C 0x1f
+#define BIT_MDIO_PHY_ADDR_8822C(x)                                             \
+	(((x) & BIT_MASK_MDIO_PHY_ADDR_8822C) << BIT_SHIFT_MDIO_PHY_ADDR_8822C)
+#define BITS_MDIO_PHY_ADDR_8822C                                               \
+	(BIT_MASK_MDIO_PHY_ADDR_8822C << BIT_SHIFT_MDIO_PHY_ADDR_8822C)
+#define BIT_CLEAR_MDIO_PHY_ADDR_8822C(x) ((x) & (~BITS_MDIO_PHY_ADDR_8822C))
+#define BIT_GET_MDIO_PHY_ADDR_8822C(x)                                         \
+	(((x) >> BIT_SHIFT_MDIO_PHY_ADDR_8822C) & BIT_MASK_MDIO_PHY_ADDR_8822C)
+#define BIT_SET_MDIO_PHY_ADDR_8822C(x, v)                                      \
+	(BIT_CLEAR_MDIO_PHY_ADDR_8822C(x) | BIT_MDIO_PHY_ADDR_8822C(v))
+
+#define BIT_SHIFT_WATCH_DOG_RECORD_V1_8822C 10
+#define BIT_MASK_WATCH_DOG_RECORD_V1_8822C 0x3fff
+#define BIT_WATCH_DOG_RECORD_V1_8822C(x)                                       \
+	(((x) & BIT_MASK_WATCH_DOG_RECORD_V1_8822C)                            \
+	 << BIT_SHIFT_WATCH_DOG_RECORD_V1_8822C)
+#define BITS_WATCH_DOG_RECORD_V1_8822C                                         \
+	(BIT_MASK_WATCH_DOG_RECORD_V1_8822C                                    \
+	 << BIT_SHIFT_WATCH_DOG_RECORD_V1_8822C)
+#define BIT_CLEAR_WATCH_DOG_RECORD_V1_8822C(x)                                 \
+	((x) & (~BITS_WATCH_DOG_RECORD_V1_8822C))
+#define BIT_GET_WATCH_DOG_RECORD_V1_8822C(x)                                   \
+	(((x) >> BIT_SHIFT_WATCH_DOG_RECORD_V1_8822C) &                        \
+	 BIT_MASK_WATCH_DOG_RECORD_V1_8822C)
+#define BIT_SET_WATCH_DOG_RECORD_V1_8822C(x, v)                                \
+	(BIT_CLEAR_WATCH_DOG_RECORD_V1_8822C(x) |                              \
+	 BIT_WATCH_DOG_RECORD_V1_8822C(v))
+
+#define BIT_R_IO_TIMEOUT_FLAG_V1_8822C BIT(9)
+#define BIT_EN_WATCH_DOG_8822C BIT(8)
+#define BIT_ECRC_EN_V1_8822C BIT(7)
+#define BIT_MDIO_RFLAG_V1_8822C BIT(6)
+#define BIT_MDIO_WFLAG_V1_8822C BIT(5)
+
+#define BIT_SHIFT_MDIO_REG_ADDR_V1_8822C 0
+#define BIT_MASK_MDIO_REG_ADDR_V1_8822C 0x1f
+#define BIT_MDIO_REG_ADDR_V1_8822C(x)                                          \
+	(((x) & BIT_MASK_MDIO_REG_ADDR_V1_8822C)                               \
+	 << BIT_SHIFT_MDIO_REG_ADDR_V1_8822C)
+#define BITS_MDIO_REG_ADDR_V1_8822C                                            \
+	(BIT_MASK_MDIO_REG_ADDR_V1_8822C << BIT_SHIFT_MDIO_REG_ADDR_V1_8822C)
+#define BIT_CLEAR_MDIO_REG_ADDR_V1_8822C(x)                                    \
+	((x) & (~BITS_MDIO_REG_ADDR_V1_8822C))
+#define BIT_GET_MDIO_REG_ADDR_V1_8822C(x)                                      \
+	(((x) >> BIT_SHIFT_MDIO_REG_ADDR_V1_8822C) &                           \
+	 BIT_MASK_MDIO_REG_ADDR_V1_8822C)
+#define BIT_SET_MDIO_REG_ADDR_V1_8822C(x, v)                                   \
+	(BIT_CLEAR_MDIO_REG_ADDR_V1_8822C(x) | BIT_MDIO_REG_ADDR_V1_8822C(v))
+
+/* 2 REG_HCI_MIX_CFG_8822C */
+
+#define BIT_SHIFT_WATCH_DOG_TIMER_8822C 28
+#define BIT_MASK_WATCH_DOG_TIMER_8822C 0xf
+#define BIT_WATCH_DOG_TIMER_8822C(x)                                           \
+	(((x) & BIT_MASK_WATCH_DOG_TIMER_8822C)                                \
+	 << BIT_SHIFT_WATCH_DOG_TIMER_8822C)
+#define BITS_WATCH_DOG_TIMER_8822C                                             \
+	(BIT_MASK_WATCH_DOG_TIMER_8822C << BIT_SHIFT_WATCH_DOG_TIMER_8822C)
+#define BIT_CLEAR_WATCH_DOG_TIMER_8822C(x) ((x) & (~BITS_WATCH_DOG_TIMER_8822C))
+#define BIT_GET_WATCH_DOG_TIMER_8822C(x)                                       \
+	(((x) >> BIT_SHIFT_WATCH_DOG_TIMER_8822C) &                            \
+	 BIT_MASK_WATCH_DOG_TIMER_8822C)
+#define BIT_SET_WATCH_DOG_TIMER_8822C(x, v)                                    \
+	(BIT_CLEAR_WATCH_DOG_TIMER_8822C(x) | BIT_WATCH_DOG_TIMER_8822C(v))
+
+#define BIT_EN_ALIGN_MTU_8822C BIT(23)
+
+#define BIT_SHIFT_LATENCY_CONTROL_8822C 21
+#define BIT_MASK_LATENCY_CONTROL_8822C 0x3
+#define BIT_LATENCY_CONTROL_8822C(x)                                           \
+	(((x) & BIT_MASK_LATENCY_CONTROL_8822C)                                \
+	 << BIT_SHIFT_LATENCY_CONTROL_8822C)
+#define BITS_LATENCY_CONTROL_8822C                                             \
+	(BIT_MASK_LATENCY_CONTROL_8822C << BIT_SHIFT_LATENCY_CONTROL_8822C)
+#define BIT_CLEAR_LATENCY_CONTROL_8822C(x) ((x) & (~BITS_LATENCY_CONTROL_8822C))
+#define BIT_GET_LATENCY_CONTROL_8822C(x)                                       \
+	(((x) >> BIT_SHIFT_LATENCY_CONTROL_8822C) &                            \
+	 BIT_MASK_LATENCY_CONTROL_8822C)
+#define BIT_SET_LATENCY_CONTROL_8822C(x, v)                                    \
+	(BIT_CLEAR_LATENCY_CONTROL_8822C(x) | BIT_LATENCY_CONTROL_8822C(v))
+
+#define BIT_HOST_GEN2_SUPPORT_8822C BIT(20)
+
+#define BIT_SHIFT_TXDMA_ERR_FLAG_V1_8822C 15
+#define BIT_MASK_TXDMA_ERR_FLAG_V1_8822C 0x1f
+#define BIT_TXDMA_ERR_FLAG_V1_8822C(x)                                         \
+	(((x) & BIT_MASK_TXDMA_ERR_FLAG_V1_8822C)                              \
+	 << BIT_SHIFT_TXDMA_ERR_FLAG_V1_8822C)
+#define BITS_TXDMA_ERR_FLAG_V1_8822C                                           \
+	(BIT_MASK_TXDMA_ERR_FLAG_V1_8822C << BIT_SHIFT_TXDMA_ERR_FLAG_V1_8822C)
+#define BIT_CLEAR_TXDMA_ERR_FLAG_V1_8822C(x)                                   \
+	((x) & (~BITS_TXDMA_ERR_FLAG_V1_8822C))
+#define BIT_GET_TXDMA_ERR_FLAG_V1_8822C(x)                                     \
+	(((x) >> BIT_SHIFT_TXDMA_ERR_FLAG_V1_8822C) &                          \
+	 BIT_MASK_TXDMA_ERR_FLAG_V1_8822C)
+#define BIT_SET_TXDMA_ERR_FLAG_V1_8822C(x, v)                                  \
+	(BIT_CLEAR_TXDMA_ERR_FLAG_V1_8822C(x) | BIT_TXDMA_ERR_FLAG_V1_8822C(v))
+
+#define BIT_EPHY_RX50_EN_8822C BIT(11)
+
+#define BIT_SHIFT_MSI_TIMEOUT_ID_V1_8822C 8
+#define BIT_MASK_MSI_TIMEOUT_ID_V1_8822C 0x7
+#define BIT_MSI_TIMEOUT_ID_V1_8822C(x)                                         \
+	(((x) & BIT_MASK_MSI_TIMEOUT_ID_V1_8822C)                              \
+	 << BIT_SHIFT_MSI_TIMEOUT_ID_V1_8822C)
+#define BITS_MSI_TIMEOUT_ID_V1_8822C                                           \
+	(BIT_MASK_MSI_TIMEOUT_ID_V1_8822C << BIT_SHIFT_MSI_TIMEOUT_ID_V1_8822C)
+#define BIT_CLEAR_MSI_TIMEOUT_ID_V1_8822C(x)                                   \
+	((x) & (~BITS_MSI_TIMEOUT_ID_V1_8822C))
+#define BIT_GET_MSI_TIMEOUT_ID_V1_8822C(x)                                     \
+	(((x) >> BIT_SHIFT_MSI_TIMEOUT_ID_V1_8822C) &                          \
+	 BIT_MASK_MSI_TIMEOUT_ID_V1_8822C)
+#define BIT_SET_MSI_TIMEOUT_ID_V1_8822C(x, v)                                  \
+	(BIT_CLEAR_MSI_TIMEOUT_ID_V1_8822C(x) | BIT_MSI_TIMEOUT_ID_V1_8822C(v))
+
+#define BIT_RADDR_RD_8822C BIT(7)
+#define BIT_L1OFF_PWR_OFF_EN_8822C BIT(6)
+#define BIT_L0S_LINK_OFF_8822C BIT(4)
+#define BIT_ACT_LINK_OFF_8822C BIT(3)
+#define BIT_EN_SLOW_MAC_TX_8822C BIT(2)
+#define BIT_EN_SLOW_MAC_RX_8822C BIT(1)
+#define BIT_EN_SLOW_MAC_HW_8822C BIT(0)
+
+/* 2 REG_STC_INT_CS_8822C(PCIE STATE CHANGE INTERRUPT CONTROL AND STATUS) */
+#define BIT_STC_INT_EN_8822C BIT(31)
+
+#define BIT_SHIFT_STC_INT_FLAG_8822C 16
+#define BIT_MASK_STC_INT_FLAG_8822C 0xff
+#define BIT_STC_INT_FLAG_8822C(x)                                              \
+	(((x) & BIT_MASK_STC_INT_FLAG_8822C) << BIT_SHIFT_STC_INT_FLAG_8822C)
+#define BITS_STC_INT_FLAG_8822C                                                \
+	(BIT_MASK_STC_INT_FLAG_8822C << BIT_SHIFT_STC_INT_FLAG_8822C)
+#define BIT_CLEAR_STC_INT_FLAG_8822C(x) ((x) & (~BITS_STC_INT_FLAG_8822C))
+#define BIT_GET_STC_INT_FLAG_8822C(x)                                          \
+	(((x) >> BIT_SHIFT_STC_INT_FLAG_8822C) & BIT_MASK_STC_INT_FLAG_8822C)
+#define BIT_SET_STC_INT_FLAG_8822C(x, v)                                       \
+	(BIT_CLEAR_STC_INT_FLAG_8822C(x) | BIT_STC_INT_FLAG_8822C(v))
+
+#define BIT_SHIFT_STC_INT_IDX_8822C 8
+#define BIT_MASK_STC_INT_IDX_8822C 0x7
+#define BIT_STC_INT_IDX_8822C(x)                                               \
+	(((x) & BIT_MASK_STC_INT_IDX_8822C) << BIT_SHIFT_STC_INT_IDX_8822C)
+#define BITS_STC_INT_IDX_8822C                                                 \
+	(BIT_MASK_STC_INT_IDX_8822C << BIT_SHIFT_STC_INT_IDX_8822C)
+#define BIT_CLEAR_STC_INT_IDX_8822C(x) ((x) & (~BITS_STC_INT_IDX_8822C))
+#define BIT_GET_STC_INT_IDX_8822C(x)                                           \
+	(((x) >> BIT_SHIFT_STC_INT_IDX_8822C) & BIT_MASK_STC_INT_IDX_8822C)
+#define BIT_SET_STC_INT_IDX_8822C(x, v)                                        \
+	(BIT_CLEAR_STC_INT_IDX_8822C(x) | BIT_STC_INT_IDX_8822C(v))
+
+#define BIT_SHIFT_STC_INT_REALTIME_CS_8822C 0
+#define BIT_MASK_STC_INT_REALTIME_CS_8822C 0x3f
+#define BIT_STC_INT_REALTIME_CS_8822C(x)                                       \
+	(((x) & BIT_MASK_STC_INT_REALTIME_CS_8822C)                            \
+	 << BIT_SHIFT_STC_INT_REALTIME_CS_8822C)
+#define BITS_STC_INT_REALTIME_CS_8822C                                         \
+	(BIT_MASK_STC_INT_REALTIME_CS_8822C                                    \
+	 << BIT_SHIFT_STC_INT_REALTIME_CS_8822C)
+#define BIT_CLEAR_STC_INT_REALTIME_CS_8822C(x)                                 \
+	((x) & (~BITS_STC_INT_REALTIME_CS_8822C))
+#define BIT_GET_STC_INT_REALTIME_CS_8822C(x)                                   \
+	(((x) >> BIT_SHIFT_STC_INT_REALTIME_CS_8822C) &                        \
+	 BIT_MASK_STC_INT_REALTIME_CS_8822C)
+#define BIT_SET_STC_INT_REALTIME_CS_8822C(x, v)                                \
+	(BIT_CLEAR_STC_INT_REALTIME_CS_8822C(x) |                              \
+	 BIT_STC_INT_REALTIME_CS_8822C(v))
+
+#define BIT_STC_INT_GRP_EN_8822C BIT(31)
+
+#define BIT_SHIFT_STC_INT_EXPECT_LS_8822C 8
+#define BIT_MASK_STC_INT_EXPECT_LS_8822C 0x3f
+#define BIT_STC_INT_EXPECT_LS_8822C(x)                                         \
+	(((x) & BIT_MASK_STC_INT_EXPECT_LS_8822C)                              \
+	 << BIT_SHIFT_STC_INT_EXPECT_LS_8822C)
+#define BITS_STC_INT_EXPECT_LS_8822C                                           \
+	(BIT_MASK_STC_INT_EXPECT_LS_8822C << BIT_SHIFT_STC_INT_EXPECT_LS_8822C)
+#define BIT_CLEAR_STC_INT_EXPECT_LS_8822C(x)                                   \
+	((x) & (~BITS_STC_INT_EXPECT_LS_8822C))
+#define BIT_GET_STC_INT_EXPECT_LS_8822C(x)                                     \
+	(((x) >> BIT_SHIFT_STC_INT_EXPECT_LS_8822C) &                          \
+	 BIT_MASK_STC_INT_EXPECT_LS_8822C)
+#define BIT_SET_STC_INT_EXPECT_LS_8822C(x, v)                                  \
+	(BIT_CLEAR_STC_INT_EXPECT_LS_8822C(x) | BIT_STC_INT_EXPECT_LS_8822C(v))
+
+#define BIT_SHIFT_STC_INT_EXPECT_CS_8822C 0
+#define BIT_MASK_STC_INT_EXPECT_CS_8822C 0x3f
+#define BIT_STC_INT_EXPECT_CS_8822C(x)                                         \
+	(((x) & BIT_MASK_STC_INT_EXPECT_CS_8822C)                              \
+	 << BIT_SHIFT_STC_INT_EXPECT_CS_8822C)
+#define BITS_STC_INT_EXPECT_CS_8822C                                           \
+	(BIT_MASK_STC_INT_EXPECT_CS_8822C << BIT_SHIFT_STC_INT_EXPECT_CS_8822C)
+#define BIT_CLEAR_STC_INT_EXPECT_CS_8822C(x)                                   \
+	((x) & (~BITS_STC_INT_EXPECT_CS_8822C))
+#define BIT_GET_STC_INT_EXPECT_CS_8822C(x)                                     \
+	(((x) >> BIT_SHIFT_STC_INT_EXPECT_CS_8822C) &                          \
+	 BIT_MASK_STC_INT_EXPECT_CS_8822C)
+#define BIT_SET_STC_INT_EXPECT_CS_8822C(x, v)                                  \
+	(BIT_CLEAR_STC_INT_EXPECT_CS_8822C(x) | BIT_STC_INT_EXPECT_CS_8822C(v))
+
+/* 2 REG_H2CQ_TXBD_DESA_8822C */
+
+#define BIT_SHIFT_H2CQ_TXBD_DESA_8822C 0
+#define BIT_MASK_H2CQ_TXBD_DESA_8822C 0xffffffffffffffffL
+#define BIT_H2CQ_TXBD_DESA_8822C(x)                                            \
+	(((x) & BIT_MASK_H2CQ_TXBD_DESA_8822C)                                 \
+	 << BIT_SHIFT_H2CQ_TXBD_DESA_8822C)
+#define BITS_H2CQ_TXBD_DESA_8822C                                              \
+	(BIT_MASK_H2CQ_TXBD_DESA_8822C << BIT_SHIFT_H2CQ_TXBD_DESA_8822C)
+#define BIT_CLEAR_H2CQ_TXBD_DESA_8822C(x) ((x) & (~BITS_H2CQ_TXBD_DESA_8822C))
+#define BIT_GET_H2CQ_TXBD_DESA_8822C(x)                                        \
+	(((x) >> BIT_SHIFT_H2CQ_TXBD_DESA_8822C) &                             \
+	 BIT_MASK_H2CQ_TXBD_DESA_8822C)
+#define BIT_SET_H2CQ_TXBD_DESA_8822C(x, v)                                     \
+	(BIT_CLEAR_H2CQ_TXBD_DESA_8822C(x) | BIT_H2CQ_TXBD_DESA_8822C(v))
+
+/* 2 REG_H2CQ_TXBD_NUM_8822C */
+#define BIT_PCIE_H2CQ_FLAG_8822C BIT(14)
+
+#define BIT_SHIFT_H2CQ_DESC_MODE_8822C 12
+#define BIT_MASK_H2CQ_DESC_MODE_8822C 0x3
+#define BIT_H2CQ_DESC_MODE_8822C(x)                                            \
+	(((x) & BIT_MASK_H2CQ_DESC_MODE_8822C)                                 \
+	 << BIT_SHIFT_H2CQ_DESC_MODE_8822C)
+#define BITS_H2CQ_DESC_MODE_8822C                                              \
+	(BIT_MASK_H2CQ_DESC_MODE_8822C << BIT_SHIFT_H2CQ_DESC_MODE_8822C)
+#define BIT_CLEAR_H2CQ_DESC_MODE_8822C(x) ((x) & (~BITS_H2CQ_DESC_MODE_8822C))
+#define BIT_GET_H2CQ_DESC_MODE_8822C(x)                                        \
+	(((x) >> BIT_SHIFT_H2CQ_DESC_MODE_8822C) &                             \
+	 BIT_MASK_H2CQ_DESC_MODE_8822C)
+#define BIT_SET_H2CQ_DESC_MODE_8822C(x, v)                                     \
+	(BIT_CLEAR_H2CQ_DESC_MODE_8822C(x) | BIT_H2CQ_DESC_MODE_8822C(v))
+
+#define BIT_SHIFT_H2CQ_DESC_NUM_8822C 0
+#define BIT_MASK_H2CQ_DESC_NUM_8822C 0xfff
+#define BIT_H2CQ_DESC_NUM_8822C(x)                                             \
+	(((x) & BIT_MASK_H2CQ_DESC_NUM_8822C) << BIT_SHIFT_H2CQ_DESC_NUM_8822C)
+#define BITS_H2CQ_DESC_NUM_8822C                                               \
+	(BIT_MASK_H2CQ_DESC_NUM_8822C << BIT_SHIFT_H2CQ_DESC_NUM_8822C)
+#define BIT_CLEAR_H2CQ_DESC_NUM_8822C(x) ((x) & (~BITS_H2CQ_DESC_NUM_8822C))
+#define BIT_GET_H2CQ_DESC_NUM_8822C(x)                                         \
+	(((x) >> BIT_SHIFT_H2CQ_DESC_NUM_8822C) & BIT_MASK_H2CQ_DESC_NUM_8822C)
+#define BIT_SET_H2CQ_DESC_NUM_8822C(x, v)                                      \
+	(BIT_CLEAR_H2CQ_DESC_NUM_8822C(x) | BIT_H2CQ_DESC_NUM_8822C(v))
+
+/* 2 REG_H2CQ_TXBD_IDX_8822C */
+
+#define BIT_SHIFT_H2CQ_HW_IDX_8822C 16
+#define BIT_MASK_H2CQ_HW_IDX_8822C 0xfff
+#define BIT_H2CQ_HW_IDX_8822C(x)                                               \
+	(((x) & BIT_MASK_H2CQ_HW_IDX_8822C) << BIT_SHIFT_H2CQ_HW_IDX_8822C)
+#define BITS_H2CQ_HW_IDX_8822C                                                 \
+	(BIT_MASK_H2CQ_HW_IDX_8822C << BIT_SHIFT_H2CQ_HW_IDX_8822C)
+#define BIT_CLEAR_H2CQ_HW_IDX_8822C(x) ((x) & (~BITS_H2CQ_HW_IDX_8822C))
+#define BIT_GET_H2CQ_HW_IDX_8822C(x)                                           \
+	(((x) >> BIT_SHIFT_H2CQ_HW_IDX_8822C) & BIT_MASK_H2CQ_HW_IDX_8822C)
+#define BIT_SET_H2CQ_HW_IDX_8822C(x, v)                                        \
+	(BIT_CLEAR_H2CQ_HW_IDX_8822C(x) | BIT_H2CQ_HW_IDX_8822C(v))
+
+#define BIT_SHIFT_H2CQ_HOST_IDX_8822C 0
+#define BIT_MASK_H2CQ_HOST_IDX_8822C 0xfff
+#define BIT_H2CQ_HOST_IDX_8822C(x)                                             \
+	(((x) & BIT_MASK_H2CQ_HOST_IDX_8822C) << BIT_SHIFT_H2CQ_HOST_IDX_8822C)
+#define BITS_H2CQ_HOST_IDX_8822C                                               \
+	(BIT_MASK_H2CQ_HOST_IDX_8822C << BIT_SHIFT_H2CQ_HOST_IDX_8822C)
+#define BIT_CLEAR_H2CQ_HOST_IDX_8822C(x) ((x) & (~BITS_H2CQ_HOST_IDX_8822C))
+#define BIT_GET_H2CQ_HOST_IDX_8822C(x)                                         \
+	(((x) >> BIT_SHIFT_H2CQ_HOST_IDX_8822C) & BIT_MASK_H2CQ_HOST_IDX_8822C)
+#define BIT_SET_H2CQ_HOST_IDX_8822C(x, v)                                      \
+	(BIT_CLEAR_H2CQ_HOST_IDX_8822C(x) | BIT_H2CQ_HOST_IDX_8822C(v))
+
+/* 2 REG_H2CQ_CSR_8822C[31:0] (H2CQ CONTROL AND STATUS) */
+#define BIT_H2CQ_FULL_8822C BIT(31)
+#define BIT_CLR_H2CQ_HOST_IDX_8822C BIT(16)
+#define BIT_CLR_H2CQ_HW_IDX_8822C BIT(8)
+#define BIT_STOP_H2CQ_8822C BIT(0)
+
+/* 2 REG_CHANGE_PCIE_SPEED_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+#define BIT_SHIFT_RXDMA_ERR_CNT_8822C 8
+#define BIT_MASK_RXDMA_ERR_CNT_8822C 0xff
+#define BIT_RXDMA_ERR_CNT_8822C(x)                                             \
+	(((x) & BIT_MASK_RXDMA_ERR_CNT_8822C) << BIT_SHIFT_RXDMA_ERR_CNT_8822C)
+#define BITS_RXDMA_ERR_CNT_8822C                                               \
+	(BIT_MASK_RXDMA_ERR_CNT_8822C << BIT_SHIFT_RXDMA_ERR_CNT_8822C)
+#define BIT_CLEAR_RXDMA_ERR_CNT_8822C(x) ((x) & (~BITS_RXDMA_ERR_CNT_8822C))
+#define BIT_GET_RXDMA_ERR_CNT_8822C(x)                                         \
+	(((x) >> BIT_SHIFT_RXDMA_ERR_CNT_8822C) & BIT_MASK_RXDMA_ERR_CNT_8822C)
+#define BIT_SET_RXDMA_ERR_CNT_8822C(x, v)                                      \
+	(BIT_CLEAR_RXDMA_ERR_CNT_8822C(x) | BIT_RXDMA_ERR_CNT_8822C(v))
+
+#define BIT_TXDMA_ERR_HANDLE_REQ_8822C BIT(7)
+#define BIT_TXDMA_ERROR_PS_8822C BIT(6)
+#define BIT_EN_TXDMA_STUCK_ERR_HANDLE_8822C BIT(5)
+#define BIT_EN_TXDMA_RTN_ERR_HANDLE_8822C BIT(4)
+#define BIT_RXDMA_ERR_HANDLE_REQ_8822C BIT(3)
+#define BIT_RXDMA_ERROR_PS_8822C BIT(2)
+#define BIT_EN_RXDMA_STUCK_ERR_HANDLE_8822C BIT(1)
+#define BIT_EN_RXDMA_RTN_ERR_HANDLE_8822C BIT(0)
+
+/* 2 REG_DEBUG_STATE1_8822C */
+
+#define BIT_SHIFT_DEBUG_STATE1_8822C 0
+#define BIT_MASK_DEBUG_STATE1_8822C 0xffffffffL
+#define BIT_DEBUG_STATE1_8822C(x)                                              \
+	(((x) & BIT_MASK_DEBUG_STATE1_8822C) << BIT_SHIFT_DEBUG_STATE1_8822C)
+#define BITS_DEBUG_STATE1_8822C                                                \
+	(BIT_MASK_DEBUG_STATE1_8822C << BIT_SHIFT_DEBUG_STATE1_8822C)
+#define BIT_CLEAR_DEBUG_STATE1_8822C(x) ((x) & (~BITS_DEBUG_STATE1_8822C))
+#define BIT_GET_DEBUG_STATE1_8822C(x)                                          \
+	(((x) >> BIT_SHIFT_DEBUG_STATE1_8822C) & BIT_MASK_DEBUG_STATE1_8822C)
+#define BIT_SET_DEBUG_STATE1_8822C(x, v)                                       \
+	(BIT_CLEAR_DEBUG_STATE1_8822C(x) | BIT_DEBUG_STATE1_8822C(v))
+
+/* 2 REG_DEBUG_STATE2_8822C */
+
+#define BIT_SHIFT_DEBUG_STATE2_8822C 0
+#define BIT_MASK_DEBUG_STATE2_8822C 0xffffffffL
+#define BIT_DEBUG_STATE2_8822C(x)                                              \
+	(((x) & BIT_MASK_DEBUG_STATE2_8822C) << BIT_SHIFT_DEBUG_STATE2_8822C)
+#define BITS_DEBUG_STATE2_8822C                                                \
+	(BIT_MASK_DEBUG_STATE2_8822C << BIT_SHIFT_DEBUG_STATE2_8822C)
+#define BIT_CLEAR_DEBUG_STATE2_8822C(x) ((x) & (~BITS_DEBUG_STATE2_8822C))
+#define BIT_GET_DEBUG_STATE2_8822C(x)                                          \
+	(((x) >> BIT_SHIFT_DEBUG_STATE2_8822C) & BIT_MASK_DEBUG_STATE2_8822C)
+#define BIT_SET_DEBUG_STATE2_8822C(x, v)                                       \
+	(BIT_CLEAR_DEBUG_STATE2_8822C(x) | BIT_DEBUG_STATE2_8822C(v))
+
+/* 2 REG_DEBUG_STATE3_8822C */
+
+#define BIT_SHIFT_DEBUG_STATE3_8822C 0
+#define BIT_MASK_DEBUG_STATE3_8822C 0xffffffffL
+#define BIT_DEBUG_STATE3_8822C(x)                                              \
+	(((x) & BIT_MASK_DEBUG_STATE3_8822C) << BIT_SHIFT_DEBUG_STATE3_8822C)
+#define BITS_DEBUG_STATE3_8822C                                                \
+	(BIT_MASK_DEBUG_STATE3_8822C << BIT_SHIFT_DEBUG_STATE3_8822C)
+#define BIT_CLEAR_DEBUG_STATE3_8822C(x) ((x) & (~BITS_DEBUG_STATE3_8822C))
+#define BIT_GET_DEBUG_STATE3_8822C(x)                                          \
+	(((x) >> BIT_SHIFT_DEBUG_STATE3_8822C) & BIT_MASK_DEBUG_STATE3_8822C)
+#define BIT_SET_DEBUG_STATE3_8822C(x, v)                                       \
+	(BIT_CLEAR_DEBUG_STATE3_8822C(x) | BIT_DEBUG_STATE3_8822C(v))
+
+/* 2 REG_CHNL_DMA_CFG_V1_8822C */
+#define BIT_TXHCI_EN_V1_8822C BIT(26)
+#define BIT_TXHCI_IDLE_V1_8822C BIT(25)
+#define BIT_DMA_PRI_EN_V1_8822C BIT(24)
+
+/* 2 REG_PCIE_HISR0_V1_8822C */
+#define BIT_PSTIMER_2_8822C BIT(31)
+#define BIT_PSTIMER_1_8822C BIT(30)
+#define BIT_PSTIMER_0_8822C BIT(29)
+#define BIT_GTINT4_8822C BIT(28)
+#define BIT_GTINT3_8822C BIT(27)
+#define BIT_TXBCN0ERR_8822C BIT(26)
+#define BIT_TXBCN0OK_8822C BIT(25)
+#define BIT_TSF_BIT32_TOGGLE_8822C BIT(24)
+#define BIT_TXDMA_START_INT_8822C BIT(23)
+#define BIT_TXDMA_STOP_INT_8822C BIT(22)
+#define BIT_HISR7_IND_8822C BIT(21)
+#define BIT_BCNDMAINT0_8822C BIT(20)
+#define BIT_HISR6_IND_8822C BIT(19)
+#define BIT_HISR5_IND_8822C BIT(18)
+#define BIT_HISR4_IND_8822C BIT(17)
+#define BIT_BCNDERR0_8822C BIT(16)
+#define BIT_HSISR_IND_ON_INT_8822C BIT(15)
+#define BIT_HISR3_IND_8822C BIT(14)
+#define BIT_HISR2_IND_8822C BIT(13)
+#define BIT_HISR1_IND_8822C BIT(11)
+#define BIT_C2HCMD_8822C BIT(10)
+#define BIT_CPWM2_8822C BIT(9)
+#define BIT_CPWM_8822C BIT(8)
+#define BIT_TXDMAOK_CHANNEL15_8822C BIT(7)
+#define BIT_TXDMAOK_CHANNEL14_8822C BIT(6)
+#define BIT_TXDMAOK_CHANNEL3_8822C BIT(5)
+#define BIT_TXDMAOK_CHANNEL2_8822C BIT(4)
+#define BIT_TXDMAOK_CHANNEL1_8822C BIT(3)
+#define BIT_TXDMAOK_CHANNEL0_8822C BIT(2)
+#define BIT_RDU_8822C BIT(1)
+#define BIT_RXOK_8822C BIT(0)
+
+/* 2 REG_PCIE_HISR1_V1_8822C */
+#define BIT_PRE_TX_ERR_INT_8822C BIT(31)
+#define BIT_TXFIFO_TH_INT_8822C BIT(30)
+#define BIT_BTON_STS_UPDATE_INT_8822C BIT(29)
+#define BIT_BCNDMAINT7_8822C BIT(27)
+#define BIT_BCNDMAINT6_8822C BIT(26)
+#define BIT_BCNDMAINT5_8822C BIT(25)
+#define BIT_BCNDMAINT4_8822C BIT(24)
+#define BIT_BCNDMAINT3_8822C BIT(23)
+#define BIT_BCNDMAINT2_8822C BIT(22)
+#define BIT_BCNDMAINT1_8822C BIT(21)
+#define BIT_BCNDERR7_8822C BIT(20)
+#define BIT_BCNDERR6_8822C BIT(19)
+#define BIT_BCNDERR5_8822C BIT(18)
+#define BIT_BCNDERR4_8822C BIT(17)
+#define BIT_BCNDERR3_8822C BIT(16)
+#define BIT_BCNDERR2_8822C BIT(15)
+#define BIT_BCNDERR1_8822C BIT(14)
+#define BIT_ATIMEND_8822C BIT(12)
+#define BIT_TXERR_INT_8822C BIT(11)
+#define BIT_RXERR_INT_8822C BIT(10)
+#define BIT_TXFOVW_8822C BIT(9)
+#define BIT_FOVW_8822C BIT(8)
+#define BIT_CPU_MGQ_EARLY_INT_8822C BIT(6)
+#define BIT_CPU_MGQ_TXDONE_8822C BIT(5)
+#define BIT_PSTIMER_5_8822C BIT(4)
+#define BIT_PSTIMER_4_8822C BIT(3)
+#define BIT_PSTIMER_3_8822C BIT(2)
+#define BIT_CPUMGQ_TX_TIMER_8822C BIT(1)
+#define BIT_BB_STOPRX_INT_8822C BIT(0)
+
+/* 2 REG_PCIE_HISR2_V1_8822C */
+#define BIT_BCNDMAINT_P4_8822C BIT(31)
+#define BIT_BCNDMAINT_P3_8822C BIT(30)
+#define BIT_BCNDMAINT_P2_8822C BIT(29)
+#define BIT_BCNDMAINT_P1_8822C BIT(28)
+#define BIT_SCH_PHY_TXOP_SIFS_INT_8822C BIT(23)
+#define BIT_ATIMEND7_8822C BIT(22)
+#define BIT_ATIMEND6_8822C BIT(21)
+#define BIT_ATIMEND5_8822C BIT(20)
+#define BIT_ATIMEND4_8822C BIT(19)
+#define BIT_ATIMEND3_8822C BIT(18)
+#define BIT_ATIMEND2_8822C BIT(17)
+#define BIT_ATIMEND1_8822C BIT(16)
+#define BIT_TXBCN7OK_8822C BIT(14)
+#define BIT_TXBCN6OK_8822C BIT(13)
+#define BIT_TXBCN5OK_8822C BIT(12)
+#define BIT_TXBCN4OK_8822C BIT(11)
+#define BIT_TXBCN3OK_8822C BIT(10)
+#define BIT_TXBCN2OK_8822C BIT(9)
+#define BIT_TXBCN1OK_8822C BIT(8)
+#define BIT_TXBCN7ERR_8822C BIT(6)
+#define BIT_TXBCN6ERR_8822C BIT(5)
+#define BIT_TXBCN5ERR_8822C BIT(4)
+#define BIT_TXBCN4ERR_8822C BIT(3)
+#define BIT_TXBCN3ERR_8822C BIT(2)
+#define BIT_TXBCN2ERR_8822C BIT(1)
+#define BIT_TXBCN1ERR_8822C BIT(0)
+
+/* 2 REG_PCIE_HISR3_V1_8822C */
+#define BIT_GTINT12_8822C BIT(24)
+#define BIT_GTINT11_8822C BIT(23)
+#define BIT_GTINT10_8822C BIT(22)
+#define BIT_GTINT9_8822C BIT(21)
+#define BIT_RX_DESC_BUF_FULL_8822C BIT(20)
+#define BIT_CPHY_LDO_OCP_DET_INT_8822C BIT(19)
+#define BIT_WDT_PLATFORM_INT_8822C BIT(18)
+#define BIT_WDT_CPU_INT_8822C BIT(17)
+#define BIT_SETH2CDOK_8822C BIT(16)
+#define BIT_H2C_CMD_FULL_8822C BIT(15)
+#define BIT_PKT_TRANS_ERR_8822C BIT(14)
+#define BIT_TXSHORTCUT_TXDESUPDATEOK_8822C BIT(13)
+#define BIT_TXSHORTCUT_BKUPDATEOK_8822C BIT(12)
+#define BIT_TXSHORTCUT_BEUPDATEOK_8822C BIT(11)
+#define BIT_TXSHORTCUT_VIUPDATEOK_8822C BIT(10)
+#define BIT_TXSHORTCUT_VOUPDATEOK_8822C BIT(9)
+#define BIT_SEARCH_FAIL_8822C BIT(8)
+#define BIT_PWR_INT_127TO96_8822C BIT(7)
+#define BIT_PWR_INT_95TO64_8822C BIT(6)
+#define BIT_PWR_INT_63TO32_8822C BIT(5)
+#define BIT_PWR_INT_31TO0_8822C BIT(4)
+#define BIT_RX_DMA_STUCK_8822C BIT(3)
+#define BIT_TX_DMA_STUCK_8822C BIT(2)
+#define BIT_DDMA0_LP_INT_8822C BIT(1)
+#define BIT_DDMA0_HP_INT_8822C BIT(0)
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_Q0_INFO_8822C */
+
+#define BIT_SHIFT_QUEUEMACID_Q0_V1_8822C 25
+#define BIT_MASK_QUEUEMACID_Q0_V1_8822C 0x7f
+#define BIT_QUEUEMACID_Q0_V1_8822C(x)                                          \
+	(((x) & BIT_MASK_QUEUEMACID_Q0_V1_8822C)                               \
+	 << BIT_SHIFT_QUEUEMACID_Q0_V1_8822C)
+#define BITS_QUEUEMACID_Q0_V1_8822C                                            \
+	(BIT_MASK_QUEUEMACID_Q0_V1_8822C << BIT_SHIFT_QUEUEMACID_Q0_V1_8822C)
+#define BIT_CLEAR_QUEUEMACID_Q0_V1_8822C(x)                                    \
+	((x) & (~BITS_QUEUEMACID_Q0_V1_8822C))
+#define BIT_GET_QUEUEMACID_Q0_V1_8822C(x)                                      \
+	(((x) >> BIT_SHIFT_QUEUEMACID_Q0_V1_8822C) &                           \
+	 BIT_MASK_QUEUEMACID_Q0_V1_8822C)
+#define BIT_SET_QUEUEMACID_Q0_V1_8822C(x, v)                                   \
+	(BIT_CLEAR_QUEUEMACID_Q0_V1_8822C(x) | BIT_QUEUEMACID_Q0_V1_8822C(v))
+
+#define BIT_SHIFT_QUEUEAC_Q0_V1_8822C 23
+#define BIT_MASK_QUEUEAC_Q0_V1_8822C 0x3
+#define BIT_QUEUEAC_Q0_V1_8822C(x)                                             \
+	(((x) & BIT_MASK_QUEUEAC_Q0_V1_8822C) << BIT_SHIFT_QUEUEAC_Q0_V1_8822C)
+#define BITS_QUEUEAC_Q0_V1_8822C                                               \
+	(BIT_MASK_QUEUEAC_Q0_V1_8822C << BIT_SHIFT_QUEUEAC_Q0_V1_8822C)
+#define BIT_CLEAR_QUEUEAC_Q0_V1_8822C(x) ((x) & (~BITS_QUEUEAC_Q0_V1_8822C))
+#define BIT_GET_QUEUEAC_Q0_V1_8822C(x)                                         \
+	(((x) >> BIT_SHIFT_QUEUEAC_Q0_V1_8822C) & BIT_MASK_QUEUEAC_Q0_V1_8822C)
+#define BIT_SET_QUEUEAC_Q0_V1_8822C(x, v)                                      \
+	(BIT_CLEAR_QUEUEAC_Q0_V1_8822C(x) | BIT_QUEUEAC_Q0_V1_8822C(v))
+
+#define BIT_TIDEMPTY_Q0_V1_8822C BIT(22)
+
+#define BIT_SHIFT_TAIL_PKT_Q0_V2_8822C 11
+#define BIT_MASK_TAIL_PKT_Q0_V2_8822C 0x7ff
+#define BIT_TAIL_PKT_Q0_V2_8822C(x)                                            \
+	(((x) & BIT_MASK_TAIL_PKT_Q0_V2_8822C)                                 \
+	 << BIT_SHIFT_TAIL_PKT_Q0_V2_8822C)
+#define BITS_TAIL_PKT_Q0_V2_8822C                                              \
+	(BIT_MASK_TAIL_PKT_Q0_V2_8822C << BIT_SHIFT_TAIL_PKT_Q0_V2_8822C)
+#define BIT_CLEAR_TAIL_PKT_Q0_V2_8822C(x) ((x) & (~BITS_TAIL_PKT_Q0_V2_8822C))
+#define BIT_GET_TAIL_PKT_Q0_V2_8822C(x)                                        \
+	(((x) >> BIT_SHIFT_TAIL_PKT_Q0_V2_8822C) &                             \
+	 BIT_MASK_TAIL_PKT_Q0_V2_8822C)
+#define BIT_SET_TAIL_PKT_Q0_V2_8822C(x, v)                                     \
+	(BIT_CLEAR_TAIL_PKT_Q0_V2_8822C(x) | BIT_TAIL_PKT_Q0_V2_8822C(v))
+
+#define BIT_SHIFT_HEAD_PKT_Q0_V1_8822C 0
+#define BIT_MASK_HEAD_PKT_Q0_V1_8822C 0x7ff
+#define BIT_HEAD_PKT_Q0_V1_8822C(x)                                            \
+	(((x) & BIT_MASK_HEAD_PKT_Q0_V1_8822C)                                 \
+	 << BIT_SHIFT_HEAD_PKT_Q0_V1_8822C)
+#define BITS_HEAD_PKT_Q0_V1_8822C                                              \
+	(BIT_MASK_HEAD_PKT_Q0_V1_8822C << BIT_SHIFT_HEAD_PKT_Q0_V1_8822C)
+#define BIT_CLEAR_HEAD_PKT_Q0_V1_8822C(x) ((x) & (~BITS_HEAD_PKT_Q0_V1_8822C))
+#define BIT_GET_HEAD_PKT_Q0_V1_8822C(x)                                        \
+	(((x) >> BIT_SHIFT_HEAD_PKT_Q0_V1_8822C) &                             \
+	 BIT_MASK_HEAD_PKT_Q0_V1_8822C)
+#define BIT_SET_HEAD_PKT_Q0_V1_8822C(x, v)                                     \
+	(BIT_CLEAR_HEAD_PKT_Q0_V1_8822C(x) | BIT_HEAD_PKT_Q0_V1_8822C(v))
+
+/* 2 REG_Q1_INFO_8822C */
+
+#define BIT_SHIFT_QUEUEMACID_Q1_V1_8822C 25
+#define BIT_MASK_QUEUEMACID_Q1_V1_8822C 0x7f
+#define BIT_QUEUEMACID_Q1_V1_8822C(x)                                          \
+	(((x) & BIT_MASK_QUEUEMACID_Q1_V1_8822C)                               \
+	 << BIT_SHIFT_QUEUEMACID_Q1_V1_8822C)
+#define BITS_QUEUEMACID_Q1_V1_8822C                                            \
+	(BIT_MASK_QUEUEMACID_Q1_V1_8822C << BIT_SHIFT_QUEUEMACID_Q1_V1_8822C)
+#define BIT_CLEAR_QUEUEMACID_Q1_V1_8822C(x)                                    \
+	((x) & (~BITS_QUEUEMACID_Q1_V1_8822C))
+#define BIT_GET_QUEUEMACID_Q1_V1_8822C(x)                                      \
+	(((x) >> BIT_SHIFT_QUEUEMACID_Q1_V1_8822C) &                           \
+	 BIT_MASK_QUEUEMACID_Q1_V1_8822C)
+#define BIT_SET_QUEUEMACID_Q1_V1_8822C(x, v)                                   \
+	(BIT_CLEAR_QUEUEMACID_Q1_V1_8822C(x) | BIT_QUEUEMACID_Q1_V1_8822C(v))
+
+#define BIT_SHIFT_QUEUEAC_Q1_V1_8822C 23
+#define BIT_MASK_QUEUEAC_Q1_V1_8822C 0x3
+#define BIT_QUEUEAC_Q1_V1_8822C(x)                                             \
+	(((x) & BIT_MASK_QUEUEAC_Q1_V1_8822C) << BIT_SHIFT_QUEUEAC_Q1_V1_8822C)
+#define BITS_QUEUEAC_Q1_V1_8822C                                               \
+	(BIT_MASK_QUEUEAC_Q1_V1_8822C << BIT_SHIFT_QUEUEAC_Q1_V1_8822C)
+#define BIT_CLEAR_QUEUEAC_Q1_V1_8822C(x) ((x) & (~BITS_QUEUEAC_Q1_V1_8822C))
+#define BIT_GET_QUEUEAC_Q1_V1_8822C(x)                                         \
+	(((x) >> BIT_SHIFT_QUEUEAC_Q1_V1_8822C) & BIT_MASK_QUEUEAC_Q1_V1_8822C)
+#define BIT_SET_QUEUEAC_Q1_V1_8822C(x, v)                                      \
+	(BIT_CLEAR_QUEUEAC_Q1_V1_8822C(x) | BIT_QUEUEAC_Q1_V1_8822C(v))
+
+#define BIT_TIDEMPTY_Q1_V1_8822C BIT(22)
+
+#define BIT_SHIFT_TAIL_PKT_Q1_V2_8822C 11
+#define BIT_MASK_TAIL_PKT_Q1_V2_8822C 0x7ff
+#define BIT_TAIL_PKT_Q1_V2_8822C(x)                                            \
+	(((x) & BIT_MASK_TAIL_PKT_Q1_V2_8822C)                                 \
+	 << BIT_SHIFT_TAIL_PKT_Q1_V2_8822C)
+#define BITS_TAIL_PKT_Q1_V2_8822C                                              \
+	(BIT_MASK_TAIL_PKT_Q1_V2_8822C << BIT_SHIFT_TAIL_PKT_Q1_V2_8822C)
+#define BIT_CLEAR_TAIL_PKT_Q1_V2_8822C(x) ((x) & (~BITS_TAIL_PKT_Q1_V2_8822C))
+#define BIT_GET_TAIL_PKT_Q1_V2_8822C(x)                                        \
+	(((x) >> BIT_SHIFT_TAIL_PKT_Q1_V2_8822C) &                             \
+	 BIT_MASK_TAIL_PKT_Q1_V2_8822C)
+#define BIT_SET_TAIL_PKT_Q1_V2_8822C(x, v)                                     \
+	(BIT_CLEAR_TAIL_PKT_Q1_V2_8822C(x) | BIT_TAIL_PKT_Q1_V2_8822C(v))
+
+#define BIT_SHIFT_HEAD_PKT_Q1_V1_8822C 0
+#define BIT_MASK_HEAD_PKT_Q1_V1_8822C 0x7ff
+#define BIT_HEAD_PKT_Q1_V1_8822C(x)                                            \
+	(((x) & BIT_MASK_HEAD_PKT_Q1_V1_8822C)                                 \
+	 << BIT_SHIFT_HEAD_PKT_Q1_V1_8822C)
+#define BITS_HEAD_PKT_Q1_V1_8822C                                              \
+	(BIT_MASK_HEAD_PKT_Q1_V1_8822C << BIT_SHIFT_HEAD_PKT_Q1_V1_8822C)
+#define BIT_CLEAR_HEAD_PKT_Q1_V1_8822C(x) ((x) & (~BITS_HEAD_PKT_Q1_V1_8822C))
+#define BIT_GET_HEAD_PKT_Q1_V1_8822C(x)                                        \
+	(((x) >> BIT_SHIFT_HEAD_PKT_Q1_V1_8822C) &                             \
+	 BIT_MASK_HEAD_PKT_Q1_V1_8822C)
+#define BIT_SET_HEAD_PKT_Q1_V1_8822C(x, v)                                     \
+	(BIT_CLEAR_HEAD_PKT_Q1_V1_8822C(x) | BIT_HEAD_PKT_Q1_V1_8822C(v))
+
+/* 2 REG_Q2_INFO_8822C */
+
+#define BIT_SHIFT_QUEUEMACID_Q2_V1_8822C 25
+#define BIT_MASK_QUEUEMACID_Q2_V1_8822C 0x7f
+#define BIT_QUEUEMACID_Q2_V1_8822C(x)                                          \
+	(((x) & BIT_MASK_QUEUEMACID_Q2_V1_8822C)                               \
+	 << BIT_SHIFT_QUEUEMACID_Q2_V1_8822C)
+#define BITS_QUEUEMACID_Q2_V1_8822C                                            \
+	(BIT_MASK_QUEUEMACID_Q2_V1_8822C << BIT_SHIFT_QUEUEMACID_Q2_V1_8822C)
+#define BIT_CLEAR_QUEUEMACID_Q2_V1_8822C(x)                                    \
+	((x) & (~BITS_QUEUEMACID_Q2_V1_8822C))
+#define BIT_GET_QUEUEMACID_Q2_V1_8822C(x)                                      \
+	(((x) >> BIT_SHIFT_QUEUEMACID_Q2_V1_8822C) &                           \
+	 BIT_MASK_QUEUEMACID_Q2_V1_8822C)
+#define BIT_SET_QUEUEMACID_Q2_V1_8822C(x, v)                                   \
+	(BIT_CLEAR_QUEUEMACID_Q2_V1_8822C(x) | BIT_QUEUEMACID_Q2_V1_8822C(v))
+
+#define BIT_SHIFT_QUEUEAC_Q2_V1_8822C 23
+#define BIT_MASK_QUEUEAC_Q2_V1_8822C 0x3
+#define BIT_QUEUEAC_Q2_V1_8822C(x)                                             \
+	(((x) & BIT_MASK_QUEUEAC_Q2_V1_8822C) << BIT_SHIFT_QUEUEAC_Q2_V1_8822C)
+#define BITS_QUEUEAC_Q2_V1_8822C                                               \
+	(BIT_MASK_QUEUEAC_Q2_V1_8822C << BIT_SHIFT_QUEUEAC_Q2_V1_8822C)
+#define BIT_CLEAR_QUEUEAC_Q2_V1_8822C(x) ((x) & (~BITS_QUEUEAC_Q2_V1_8822C))
+#define BIT_GET_QUEUEAC_Q2_V1_8822C(x)                                         \
+	(((x) >> BIT_SHIFT_QUEUEAC_Q2_V1_8822C) & BIT_MASK_QUEUEAC_Q2_V1_8822C)
+#define BIT_SET_QUEUEAC_Q2_V1_8822C(x, v)                                      \
+	(BIT_CLEAR_QUEUEAC_Q2_V1_8822C(x) | BIT_QUEUEAC_Q2_V1_8822C(v))
+
+#define BIT_TIDEMPTY_Q2_V1_8822C BIT(22)
+
+#define BIT_SHIFT_TAIL_PKT_Q2_V2_8822C 11
+#define BIT_MASK_TAIL_PKT_Q2_V2_8822C 0x7ff
+#define BIT_TAIL_PKT_Q2_V2_8822C(x)                                            \
+	(((x) & BIT_MASK_TAIL_PKT_Q2_V2_8822C)                                 \
+	 << BIT_SHIFT_TAIL_PKT_Q2_V2_8822C)
+#define BITS_TAIL_PKT_Q2_V2_8822C                                              \
+	(BIT_MASK_TAIL_PKT_Q2_V2_8822C << BIT_SHIFT_TAIL_PKT_Q2_V2_8822C)
+#define BIT_CLEAR_TAIL_PKT_Q2_V2_8822C(x) ((x) & (~BITS_TAIL_PKT_Q2_V2_8822C))
+#define BIT_GET_TAIL_PKT_Q2_V2_8822C(x)                                        \
+	(((x) >> BIT_SHIFT_TAIL_PKT_Q2_V2_8822C) &                             \
+	 BIT_MASK_TAIL_PKT_Q2_V2_8822C)
+#define BIT_SET_TAIL_PKT_Q2_V2_8822C(x, v)                                     \
+	(BIT_CLEAR_TAIL_PKT_Q2_V2_8822C(x) | BIT_TAIL_PKT_Q2_V2_8822C(v))
+
+#define BIT_SHIFT_HEAD_PKT_Q2_V1_8822C 0
+#define BIT_MASK_HEAD_PKT_Q2_V1_8822C 0x7ff
+#define BIT_HEAD_PKT_Q2_V1_8822C(x)                                            \
+	(((x) & BIT_MASK_HEAD_PKT_Q2_V1_8822C)                                 \
+	 << BIT_SHIFT_HEAD_PKT_Q2_V1_8822C)
+#define BITS_HEAD_PKT_Q2_V1_8822C                                              \
+	(BIT_MASK_HEAD_PKT_Q2_V1_8822C << BIT_SHIFT_HEAD_PKT_Q2_V1_8822C)
+#define BIT_CLEAR_HEAD_PKT_Q2_V1_8822C(x) ((x) & (~BITS_HEAD_PKT_Q2_V1_8822C))
+#define BIT_GET_HEAD_PKT_Q2_V1_8822C(x)                                        \
+	(((x) >> BIT_SHIFT_HEAD_PKT_Q2_V1_8822C) &                             \
+	 BIT_MASK_HEAD_PKT_Q2_V1_8822C)
+#define BIT_SET_HEAD_PKT_Q2_V1_8822C(x, v)                                     \
+	(BIT_CLEAR_HEAD_PKT_Q2_V1_8822C(x) | BIT_HEAD_PKT_Q2_V1_8822C(v))
+
+/* 2 REG_Q3_INFO_8822C */
+
+#define BIT_SHIFT_QUEUEMACID_Q3_V1_8822C 25
+#define BIT_MASK_QUEUEMACID_Q3_V1_8822C 0x7f
+#define BIT_QUEUEMACID_Q3_V1_8822C(x)                                          \
+	(((x) & BIT_MASK_QUEUEMACID_Q3_V1_8822C)                               \
+	 << BIT_SHIFT_QUEUEMACID_Q3_V1_8822C)
+#define BITS_QUEUEMACID_Q3_V1_8822C                                            \
+	(BIT_MASK_QUEUEMACID_Q3_V1_8822C << BIT_SHIFT_QUEUEMACID_Q3_V1_8822C)
+#define BIT_CLEAR_QUEUEMACID_Q3_V1_8822C(x)                                    \
+	((x) & (~BITS_QUEUEMACID_Q3_V1_8822C))
+#define BIT_GET_QUEUEMACID_Q3_V1_8822C(x)                                      \
+	(((x) >> BIT_SHIFT_QUEUEMACID_Q3_V1_8822C) &                           \
+	 BIT_MASK_QUEUEMACID_Q3_V1_8822C)
+#define BIT_SET_QUEUEMACID_Q3_V1_8822C(x, v)                                   \
+	(BIT_CLEAR_QUEUEMACID_Q3_V1_8822C(x) | BIT_QUEUEMACID_Q3_V1_8822C(v))
+
+#define BIT_SHIFT_QUEUEAC_Q3_V1_8822C 23
+#define BIT_MASK_QUEUEAC_Q3_V1_8822C 0x3
+#define BIT_QUEUEAC_Q3_V1_8822C(x)                                             \
+	(((x) & BIT_MASK_QUEUEAC_Q3_V1_8822C) << BIT_SHIFT_QUEUEAC_Q3_V1_8822C)
+#define BITS_QUEUEAC_Q3_V1_8822C                                               \
+	(BIT_MASK_QUEUEAC_Q3_V1_8822C << BIT_SHIFT_QUEUEAC_Q3_V1_8822C)
+#define BIT_CLEAR_QUEUEAC_Q3_V1_8822C(x) ((x) & (~BITS_QUEUEAC_Q3_V1_8822C))
+#define BIT_GET_QUEUEAC_Q3_V1_8822C(x)                                         \
+	(((x) >> BIT_SHIFT_QUEUEAC_Q3_V1_8822C) & BIT_MASK_QUEUEAC_Q3_V1_8822C)
+#define BIT_SET_QUEUEAC_Q3_V1_8822C(x, v)                                      \
+	(BIT_CLEAR_QUEUEAC_Q3_V1_8822C(x) | BIT_QUEUEAC_Q3_V1_8822C(v))
+
+#define BIT_TIDEMPTY_Q3_V1_8822C BIT(22)
+
+#define BIT_SHIFT_TAIL_PKT_Q3_V2_8822C 11
+#define BIT_MASK_TAIL_PKT_Q3_V2_8822C 0x7ff
+#define BIT_TAIL_PKT_Q3_V2_8822C(x)                                            \
+	(((x) & BIT_MASK_TAIL_PKT_Q3_V2_8822C)                                 \
+	 << BIT_SHIFT_TAIL_PKT_Q3_V2_8822C)
+#define BITS_TAIL_PKT_Q3_V2_8822C                                              \
+	(BIT_MASK_TAIL_PKT_Q3_V2_8822C << BIT_SHIFT_TAIL_PKT_Q3_V2_8822C)
+#define BIT_CLEAR_TAIL_PKT_Q3_V2_8822C(x) ((x) & (~BITS_TAIL_PKT_Q3_V2_8822C))
+#define BIT_GET_TAIL_PKT_Q3_V2_8822C(x)                                        \
+	(((x) >> BIT_SHIFT_TAIL_PKT_Q3_V2_8822C) &                             \
+	 BIT_MASK_TAIL_PKT_Q3_V2_8822C)
+#define BIT_SET_TAIL_PKT_Q3_V2_8822C(x, v)                                     \
+	(BIT_CLEAR_TAIL_PKT_Q3_V2_8822C(x) | BIT_TAIL_PKT_Q3_V2_8822C(v))
+
+#define BIT_SHIFT_HEAD_PKT_Q3_V1_8822C 0
+#define BIT_MASK_HEAD_PKT_Q3_V1_8822C 0x7ff
+#define BIT_HEAD_PKT_Q3_V1_8822C(x)                                            \
+	(((x) & BIT_MASK_HEAD_PKT_Q3_V1_8822C)                                 \
+	 << BIT_SHIFT_HEAD_PKT_Q3_V1_8822C)
+#define BITS_HEAD_PKT_Q3_V1_8822C                                              \
+	(BIT_MASK_HEAD_PKT_Q3_V1_8822C << BIT_SHIFT_HEAD_PKT_Q3_V1_8822C)
+#define BIT_CLEAR_HEAD_PKT_Q3_V1_8822C(x) ((x) & (~BITS_HEAD_PKT_Q3_V1_8822C))
+#define BIT_GET_HEAD_PKT_Q3_V1_8822C(x)                                        \
+	(((x) >> BIT_SHIFT_HEAD_PKT_Q3_V1_8822C) &                             \
+	 BIT_MASK_HEAD_PKT_Q3_V1_8822C)
+#define BIT_SET_HEAD_PKT_Q3_V1_8822C(x, v)                                     \
+	(BIT_CLEAR_HEAD_PKT_Q3_V1_8822C(x) | BIT_HEAD_PKT_Q3_V1_8822C(v))
+
+/* 2 REG_MGQ_INFO_8822C */
+
+#define BIT_SHIFT_QUEUEMACID_MGQ_V1_8822C 25
+#define BIT_MASK_QUEUEMACID_MGQ_V1_8822C 0x7f
+#define BIT_QUEUEMACID_MGQ_V1_8822C(x)                                         \
+	(((x) & BIT_MASK_QUEUEMACID_MGQ_V1_8822C)                              \
+	 << BIT_SHIFT_QUEUEMACID_MGQ_V1_8822C)
+#define BITS_QUEUEMACID_MGQ_V1_8822C                                           \
+	(BIT_MASK_QUEUEMACID_MGQ_V1_8822C << BIT_SHIFT_QUEUEMACID_MGQ_V1_8822C)
+#define BIT_CLEAR_QUEUEMACID_MGQ_V1_8822C(x)                                   \
+	((x) & (~BITS_QUEUEMACID_MGQ_V1_8822C))
+#define BIT_GET_QUEUEMACID_MGQ_V1_8822C(x)                                     \
+	(((x) >> BIT_SHIFT_QUEUEMACID_MGQ_V1_8822C) &                          \
+	 BIT_MASK_QUEUEMACID_MGQ_V1_8822C)
+#define BIT_SET_QUEUEMACID_MGQ_V1_8822C(x, v)                                  \
+	(BIT_CLEAR_QUEUEMACID_MGQ_V1_8822C(x) | BIT_QUEUEMACID_MGQ_V1_8822C(v))
+
+#define BIT_SHIFT_QUEUEAC_MGQ_V1_8822C 23
+#define BIT_MASK_QUEUEAC_MGQ_V1_8822C 0x3
+#define BIT_QUEUEAC_MGQ_V1_8822C(x)                                            \
+	(((x) & BIT_MASK_QUEUEAC_MGQ_V1_8822C)                                 \
+	 << BIT_SHIFT_QUEUEAC_MGQ_V1_8822C)
+#define BITS_QUEUEAC_MGQ_V1_8822C                                              \
+	(BIT_MASK_QUEUEAC_MGQ_V1_8822C << BIT_SHIFT_QUEUEAC_MGQ_V1_8822C)
+#define BIT_CLEAR_QUEUEAC_MGQ_V1_8822C(x) ((x) & (~BITS_QUEUEAC_MGQ_V1_8822C))
+#define BIT_GET_QUEUEAC_MGQ_V1_8822C(x)                                        \
+	(((x) >> BIT_SHIFT_QUEUEAC_MGQ_V1_8822C) &                             \
+	 BIT_MASK_QUEUEAC_MGQ_V1_8822C)
+#define BIT_SET_QUEUEAC_MGQ_V1_8822C(x, v)                                     \
+	(BIT_CLEAR_QUEUEAC_MGQ_V1_8822C(x) | BIT_QUEUEAC_MGQ_V1_8822C(v))
+
+#define BIT_TIDEMPTY_MGQ_V1_8822C BIT(22)
+
+#define BIT_SHIFT_TAIL_PKT_MGQ_V2_8822C 11
+#define BIT_MASK_TAIL_PKT_MGQ_V2_8822C 0x7ff
+#define BIT_TAIL_PKT_MGQ_V2_8822C(x)                                           \
+	(((x) & BIT_MASK_TAIL_PKT_MGQ_V2_8822C)                                \
+	 << BIT_SHIFT_TAIL_PKT_MGQ_V2_8822C)
+#define BITS_TAIL_PKT_MGQ_V2_8822C                                             \
+	(BIT_MASK_TAIL_PKT_MGQ_V2_8822C << BIT_SHIFT_TAIL_PKT_MGQ_V2_8822C)
+#define BIT_CLEAR_TAIL_PKT_MGQ_V2_8822C(x) ((x) & (~BITS_TAIL_PKT_MGQ_V2_8822C))
+#define BIT_GET_TAIL_PKT_MGQ_V2_8822C(x)                                       \
+	(((x) >> BIT_SHIFT_TAIL_PKT_MGQ_V2_8822C) &                            \
+	 BIT_MASK_TAIL_PKT_MGQ_V2_8822C)
+#define BIT_SET_TAIL_PKT_MGQ_V2_8822C(x, v)                                    \
+	(BIT_CLEAR_TAIL_PKT_MGQ_V2_8822C(x) | BIT_TAIL_PKT_MGQ_V2_8822C(v))
+
+#define BIT_SHIFT_HEAD_PKT_MGQ_V1_8822C 0
+#define BIT_MASK_HEAD_PKT_MGQ_V1_8822C 0x7ff
+#define BIT_HEAD_PKT_MGQ_V1_8822C(x)                                           \
+	(((x) & BIT_MASK_HEAD_PKT_MGQ_V1_8822C)                                \
+	 << BIT_SHIFT_HEAD_PKT_MGQ_V1_8822C)
+#define BITS_HEAD_PKT_MGQ_V1_8822C                                             \
+	(BIT_MASK_HEAD_PKT_MGQ_V1_8822C << BIT_SHIFT_HEAD_PKT_MGQ_V1_8822C)
+#define BIT_CLEAR_HEAD_PKT_MGQ_V1_8822C(x) ((x) & (~BITS_HEAD_PKT_MGQ_V1_8822C))
+#define BIT_GET_HEAD_PKT_MGQ_V1_8822C(x)                                       \
+	(((x) >> BIT_SHIFT_HEAD_PKT_MGQ_V1_8822C) &                            \
+	 BIT_MASK_HEAD_PKT_MGQ_V1_8822C)
+#define BIT_SET_HEAD_PKT_MGQ_V1_8822C(x, v)                                    \
+	(BIT_CLEAR_HEAD_PKT_MGQ_V1_8822C(x) | BIT_HEAD_PKT_MGQ_V1_8822C(v))
+
+/* 2 REG_HIQ_INFO_8822C */
+
+#define BIT_SHIFT_QUEUEMACID_HIQ_V1_8822C 25
+#define BIT_MASK_QUEUEMACID_HIQ_V1_8822C 0x7f
+#define BIT_QUEUEMACID_HIQ_V1_8822C(x)                                         \
+	(((x) & BIT_MASK_QUEUEMACID_HIQ_V1_8822C)                              \
+	 << BIT_SHIFT_QUEUEMACID_HIQ_V1_8822C)
+#define BITS_QUEUEMACID_HIQ_V1_8822C                                           \
+	(BIT_MASK_QUEUEMACID_HIQ_V1_8822C << BIT_SHIFT_QUEUEMACID_HIQ_V1_8822C)
+#define BIT_CLEAR_QUEUEMACID_HIQ_V1_8822C(x)                                   \
+	((x) & (~BITS_QUEUEMACID_HIQ_V1_8822C))
+#define BIT_GET_QUEUEMACID_HIQ_V1_8822C(x)                                     \
+	(((x) >> BIT_SHIFT_QUEUEMACID_HIQ_V1_8822C) &                          \
+	 BIT_MASK_QUEUEMACID_HIQ_V1_8822C)
+#define BIT_SET_QUEUEMACID_HIQ_V1_8822C(x, v)                                  \
+	(BIT_CLEAR_QUEUEMACID_HIQ_V1_8822C(x) | BIT_QUEUEMACID_HIQ_V1_8822C(v))
+
+#define BIT_SHIFT_QUEUEAC_HIQ_V1_8822C 23
+#define BIT_MASK_QUEUEAC_HIQ_V1_8822C 0x3
+#define BIT_QUEUEAC_HIQ_V1_8822C(x)                                            \
+	(((x) & BIT_MASK_QUEUEAC_HIQ_V1_8822C)                                 \
+	 << BIT_SHIFT_QUEUEAC_HIQ_V1_8822C)
+#define BITS_QUEUEAC_HIQ_V1_8822C                                              \
+	(BIT_MASK_QUEUEAC_HIQ_V1_8822C << BIT_SHIFT_QUEUEAC_HIQ_V1_8822C)
+#define BIT_CLEAR_QUEUEAC_HIQ_V1_8822C(x) ((x) & (~BITS_QUEUEAC_HIQ_V1_8822C))
+#define BIT_GET_QUEUEAC_HIQ_V1_8822C(x)                                        \
+	(((x) >> BIT_SHIFT_QUEUEAC_HIQ_V1_8822C) &                             \
+	 BIT_MASK_QUEUEAC_HIQ_V1_8822C)
+#define BIT_SET_QUEUEAC_HIQ_V1_8822C(x, v)                                     \
+	(BIT_CLEAR_QUEUEAC_HIQ_V1_8822C(x) | BIT_QUEUEAC_HIQ_V1_8822C(v))
+
+#define BIT_TIDEMPTY_HIQ_V1_8822C BIT(22)
+
+#define BIT_SHIFT_TAIL_PKT_HIQ_V2_8822C 11
+#define BIT_MASK_TAIL_PKT_HIQ_V2_8822C 0x7ff
+#define BIT_TAIL_PKT_HIQ_V2_8822C(x)                                           \
+	(((x) & BIT_MASK_TAIL_PKT_HIQ_V2_8822C)                                \
+	 << BIT_SHIFT_TAIL_PKT_HIQ_V2_8822C)
+#define BITS_TAIL_PKT_HIQ_V2_8822C                                             \
+	(BIT_MASK_TAIL_PKT_HIQ_V2_8822C << BIT_SHIFT_TAIL_PKT_HIQ_V2_8822C)
+#define BIT_CLEAR_TAIL_PKT_HIQ_V2_8822C(x) ((x) & (~BITS_TAIL_PKT_HIQ_V2_8822C))
+#define BIT_GET_TAIL_PKT_HIQ_V2_8822C(x)                                       \
+	(((x) >> BIT_SHIFT_TAIL_PKT_HIQ_V2_8822C) &                            \
+	 BIT_MASK_TAIL_PKT_HIQ_V2_8822C)
+#define BIT_SET_TAIL_PKT_HIQ_V2_8822C(x, v)                                    \
+	(BIT_CLEAR_TAIL_PKT_HIQ_V2_8822C(x) | BIT_TAIL_PKT_HIQ_V2_8822C(v))
+
+#define BIT_SHIFT_HEAD_PKT_HIQ_V1_8822C 0
+#define BIT_MASK_HEAD_PKT_HIQ_V1_8822C 0x7ff
+#define BIT_HEAD_PKT_HIQ_V1_8822C(x)                                           \
+	(((x) & BIT_MASK_HEAD_PKT_HIQ_V1_8822C)                                \
+	 << BIT_SHIFT_HEAD_PKT_HIQ_V1_8822C)
+#define BITS_HEAD_PKT_HIQ_V1_8822C                                             \
+	(BIT_MASK_HEAD_PKT_HIQ_V1_8822C << BIT_SHIFT_HEAD_PKT_HIQ_V1_8822C)
+#define BIT_CLEAR_HEAD_PKT_HIQ_V1_8822C(x) ((x) & (~BITS_HEAD_PKT_HIQ_V1_8822C))
+#define BIT_GET_HEAD_PKT_HIQ_V1_8822C(x)                                       \
+	(((x) >> BIT_SHIFT_HEAD_PKT_HIQ_V1_8822C) &                            \
+	 BIT_MASK_HEAD_PKT_HIQ_V1_8822C)
+#define BIT_SET_HEAD_PKT_HIQ_V1_8822C(x, v)                                    \
+	(BIT_CLEAR_HEAD_PKT_HIQ_V1_8822C(x) | BIT_HEAD_PKT_HIQ_V1_8822C(v))
+
+/* 2 REG_BCNQ_INFO_8822C */
+
+#define BIT_SHIFT_BCNQ_HEAD_PG_V1_8822C 0
+#define BIT_MASK_BCNQ_HEAD_PG_V1_8822C 0xfff
+#define BIT_BCNQ_HEAD_PG_V1_8822C(x)                                           \
+	(((x) & BIT_MASK_BCNQ_HEAD_PG_V1_8822C)                                \
+	 << BIT_SHIFT_BCNQ_HEAD_PG_V1_8822C)
+#define BITS_BCNQ_HEAD_PG_V1_8822C                                             \
+	(BIT_MASK_BCNQ_HEAD_PG_V1_8822C << BIT_SHIFT_BCNQ_HEAD_PG_V1_8822C)
+#define BIT_CLEAR_BCNQ_HEAD_PG_V1_8822C(x) ((x) & (~BITS_BCNQ_HEAD_PG_V1_8822C))
+#define BIT_GET_BCNQ_HEAD_PG_V1_8822C(x)                                       \
+	(((x) >> BIT_SHIFT_BCNQ_HEAD_PG_V1_8822C) &                            \
+	 BIT_MASK_BCNQ_HEAD_PG_V1_8822C)
+#define BIT_SET_BCNQ_HEAD_PG_V1_8822C(x, v)                                    \
+	(BIT_CLEAR_BCNQ_HEAD_PG_V1_8822C(x) | BIT_BCNQ_HEAD_PG_V1_8822C(v))
+
+/* 2 REG_TXPKT_EMPTY_8822C */
+#define BIT_BCNQ_EMPTY_8822C BIT(11)
+#define BIT_HQQ_EMPTY_8822C BIT(10)
+#define BIT_MQQ_EMPTY_8822C BIT(9)
+#define BIT_MGQ_CPU_EMPTY_8822C BIT(8)
+#define BIT_AC7Q_EMPTY_8822C BIT(7)
+#define BIT_AC6Q_EMPTY_8822C BIT(6)
+#define BIT_AC5Q_EMPTY_8822C BIT(5)
+#define BIT_AC4Q_EMPTY_8822C BIT(4)
+#define BIT_AC3Q_EMPTY_8822C BIT(3)
+#define BIT_AC2Q_EMPTY_8822C BIT(2)
+#define BIT_AC1Q_EMPTY_8822C BIT(1)
+#define BIT_AC0Q_EMPTY_8822C BIT(0)
+
+/* 2 REG_CPU_MGQ_INFO_8822C */
+#define BIT_BCN1_POLL_8822C BIT(30)
+#define BIT_CPUMGT_POLL_8822C BIT(29)
+#define BIT_BCN_POLL_8822C BIT(28)
+#define BIT_CPUMGQ_FW_NUM_V1_8822C BIT(12)
+
+#define BIT_SHIFT_FW_FREE_TAIL_V1_8822C 0
+#define BIT_MASK_FW_FREE_TAIL_V1_8822C 0xfff
+#define BIT_FW_FREE_TAIL_V1_8822C(x)                                           \
+	(((x) & BIT_MASK_FW_FREE_TAIL_V1_8822C)                                \
+	 << BIT_SHIFT_FW_FREE_TAIL_V1_8822C)
+#define BITS_FW_FREE_TAIL_V1_8822C                                             \
+	(BIT_MASK_FW_FREE_TAIL_V1_8822C << BIT_SHIFT_FW_FREE_TAIL_V1_8822C)
+#define BIT_CLEAR_FW_FREE_TAIL_V1_8822C(x) ((x) & (~BITS_FW_FREE_TAIL_V1_8822C))
+#define BIT_GET_FW_FREE_TAIL_V1_8822C(x)                                       \
+	(((x) >> BIT_SHIFT_FW_FREE_TAIL_V1_8822C) &                            \
+	 BIT_MASK_FW_FREE_TAIL_V1_8822C)
+#define BIT_SET_FW_FREE_TAIL_V1_8822C(x, v)                                    \
+	(BIT_CLEAR_FW_FREE_TAIL_V1_8822C(x) | BIT_FW_FREE_TAIL_V1_8822C(v))
+
+/* 2 REG_FWHW_TXQ_CTRL_8822C */
+#define BIT_RTS_LIMIT_IN_OFDM_8822C BIT(23)
+#define BIT_EN_BCNQ_DL_8822C BIT(22)
+#define BIT_EN_RD_RESP_NAV_BK_8822C BIT(21)
+#define BIT_EN_WR_FREE_TAIL_8822C BIT(20)
+#define BIT_NOTXRPT_USERATE_EN_8822C BIT(19)
+#define BIT_DIS_TXFAIL_RPT_8822C BIT(18)
+#define BIT_FTM_TIMEOUT_BYPASS_8822C BIT(16)
+
+#define BIT_SHIFT_EN_QUEUE_RPT_8822C 8
+#define BIT_MASK_EN_QUEUE_RPT_8822C 0xff
+#define BIT_EN_QUEUE_RPT_8822C(x)                                              \
+	(((x) & BIT_MASK_EN_QUEUE_RPT_8822C) << BIT_SHIFT_EN_QUEUE_RPT_8822C)
+#define BITS_EN_QUEUE_RPT_8822C                                                \
+	(BIT_MASK_EN_QUEUE_RPT_8822C << BIT_SHIFT_EN_QUEUE_RPT_8822C)
+#define BIT_CLEAR_EN_QUEUE_RPT_8822C(x) ((x) & (~BITS_EN_QUEUE_RPT_8822C))
+#define BIT_GET_EN_QUEUE_RPT_8822C(x)                                          \
+	(((x) >> BIT_SHIFT_EN_QUEUE_RPT_8822C) & BIT_MASK_EN_QUEUE_RPT_8822C)
+#define BIT_SET_EN_QUEUE_RPT_8822C(x, v)                                       \
+	(BIT_CLEAR_EN_QUEUE_RPT_8822C(x) | BIT_EN_QUEUE_RPT_8822C(v))
+
+#define BIT_EN_RTY_BK_8822C BIT(7)
+#define BIT_EN_USE_INI_RAT_8822C BIT(6)
+#define BIT_EN_RTS_NAV_BK_8822C BIT(5)
+#define BIT_DIS_SSN_CHECK_8822C BIT(4)
+#define BIT_MACID_MATCH_RTS_8822C BIT(3)
+#define BIT_EN_BCN_TRXRPT_V1_8822C BIT(2)
+#define BIT_R_EN_FTMRPT_V1_8822C BIT(1)
+#define BIT_R_BMC_NAV_PROTECT_8822C BIT(0)
+
+/* 2 REG_DATAFB_SEL_8822C */
+#define BIT_BROADCAST_RTY_EN_8822C BIT(3)
+#define BIT_EN_RTY_BK_COD_8822C BIT(2)
+
+#define BIT_SHIFT__R_DATA_FALLBACK_SEL_8822C 0
+#define BIT_MASK__R_DATA_FALLBACK_SEL_8822C 0x3
+#define BIT__R_DATA_FALLBACK_SEL_8822C(x)                                      \
+	(((x) & BIT_MASK__R_DATA_FALLBACK_SEL_8822C)                           \
+	 << BIT_SHIFT__R_DATA_FALLBACK_SEL_8822C)
+#define BITS__R_DATA_FALLBACK_SEL_8822C                                        \
+	(BIT_MASK__R_DATA_FALLBACK_SEL_8822C                                   \
+	 << BIT_SHIFT__R_DATA_FALLBACK_SEL_8822C)
+#define BIT_CLEAR__R_DATA_FALLBACK_SEL_8822C(x)                                \
+	((x) & (~BITS__R_DATA_FALLBACK_SEL_8822C))
+#define BIT_GET__R_DATA_FALLBACK_SEL_8822C(x)                                  \
+	(((x) >> BIT_SHIFT__R_DATA_FALLBACK_SEL_8822C) &                       \
+	 BIT_MASK__R_DATA_FALLBACK_SEL_8822C)
+#define BIT_SET__R_DATA_FALLBACK_SEL_8822C(x, v)                               \
+	(BIT_CLEAR__R_DATA_FALLBACK_SEL_8822C(x) |                             \
+	 BIT__R_DATA_FALLBACK_SEL_8822C(v))
+
+/* 2 REG_BCNQ_BDNY_V1_8822C */
+
+#define BIT_SHIFT_BCNQ_PGBNDY_V1_8822C 0
+#define BIT_MASK_BCNQ_PGBNDY_V1_8822C 0xfff
+#define BIT_BCNQ_PGBNDY_V1_8822C(x)                                            \
+	(((x) & BIT_MASK_BCNQ_PGBNDY_V1_8822C)                                 \
+	 << BIT_SHIFT_BCNQ_PGBNDY_V1_8822C)
+#define BITS_BCNQ_PGBNDY_V1_8822C                                              \
+	(BIT_MASK_BCNQ_PGBNDY_V1_8822C << BIT_SHIFT_BCNQ_PGBNDY_V1_8822C)
+#define BIT_CLEAR_BCNQ_PGBNDY_V1_8822C(x) ((x) & (~BITS_BCNQ_PGBNDY_V1_8822C))
+#define BIT_GET_BCNQ_PGBNDY_V1_8822C(x)                                        \
+	(((x) >> BIT_SHIFT_BCNQ_PGBNDY_V1_8822C) &                             \
+	 BIT_MASK_BCNQ_PGBNDY_V1_8822C)
+#define BIT_SET_BCNQ_PGBNDY_V1_8822C(x, v)                                     \
+	(BIT_CLEAR_BCNQ_PGBNDY_V1_8822C(x) | BIT_BCNQ_PGBNDY_V1_8822C(v))
+
+/* 2 REG_LIFETIME_EN_8822C */
+#define BIT_BT_INT_CPU_8822C BIT(7)
+#define BIT_BT_INT_PTA_8822C BIT(6)
+#define BIT_EN_CTRL_RTYBIT_8822C BIT(4)
+#define BIT_LIFETIME_BK_EN_8822C BIT(3)
+#define BIT_LIFETIME_BE_EN_8822C BIT(2)
+#define BIT_LIFETIME_VI_EN_8822C BIT(1)
+#define BIT_LIFETIME_VO_EN_8822C BIT(0)
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_SPEC_SIFS_8822C */
+
+#define BIT_SHIFT_SPEC_SIFS_OFDM_PTCL_8822C 8
+#define BIT_MASK_SPEC_SIFS_OFDM_PTCL_8822C 0xff
+#define BIT_SPEC_SIFS_OFDM_PTCL_8822C(x)                                       \
+	(((x) & BIT_MASK_SPEC_SIFS_OFDM_PTCL_8822C)                            \
+	 << BIT_SHIFT_SPEC_SIFS_OFDM_PTCL_8822C)
+#define BITS_SPEC_SIFS_OFDM_PTCL_8822C                                         \
+	(BIT_MASK_SPEC_SIFS_OFDM_PTCL_8822C                                    \
+	 << BIT_SHIFT_SPEC_SIFS_OFDM_PTCL_8822C)
+#define BIT_CLEAR_SPEC_SIFS_OFDM_PTCL_8822C(x)                                 \
+	((x) & (~BITS_SPEC_SIFS_OFDM_PTCL_8822C))
+#define BIT_GET_SPEC_SIFS_OFDM_PTCL_8822C(x)                                   \
+	(((x) >> BIT_SHIFT_SPEC_SIFS_OFDM_PTCL_8822C) &                        \
+	 BIT_MASK_SPEC_SIFS_OFDM_PTCL_8822C)
+#define BIT_SET_SPEC_SIFS_OFDM_PTCL_8822C(x, v)                                \
+	(BIT_CLEAR_SPEC_SIFS_OFDM_PTCL_8822C(x) |                              \
+	 BIT_SPEC_SIFS_OFDM_PTCL_8822C(v))
+
+#define BIT_SHIFT_SPEC_SIFS_CCK_PTCL_8822C 0
+#define BIT_MASK_SPEC_SIFS_CCK_PTCL_8822C 0xff
+#define BIT_SPEC_SIFS_CCK_PTCL_8822C(x)                                        \
+	(((x) & BIT_MASK_SPEC_SIFS_CCK_PTCL_8822C)                             \
+	 << BIT_SHIFT_SPEC_SIFS_CCK_PTCL_8822C)
+#define BITS_SPEC_SIFS_CCK_PTCL_8822C                                          \
+	(BIT_MASK_SPEC_SIFS_CCK_PTCL_8822C                                     \
+	 << BIT_SHIFT_SPEC_SIFS_CCK_PTCL_8822C)
+#define BIT_CLEAR_SPEC_SIFS_CCK_PTCL_8822C(x)                                  \
+	((x) & (~BITS_SPEC_SIFS_CCK_PTCL_8822C))
+#define BIT_GET_SPEC_SIFS_CCK_PTCL_8822C(x)                                    \
+	(((x) >> BIT_SHIFT_SPEC_SIFS_CCK_PTCL_8822C) &                         \
+	 BIT_MASK_SPEC_SIFS_CCK_PTCL_8822C)
+#define BIT_SET_SPEC_SIFS_CCK_PTCL_8822C(x, v)                                 \
+	(BIT_CLEAR_SPEC_SIFS_CCK_PTCL_8822C(x) |                               \
+	 BIT_SPEC_SIFS_CCK_PTCL_8822C(v))
+
+/* 2 REG_RETRY_LIMIT_8822C */
+
+#define BIT_SHIFT_SRL_8822C 8
+#define BIT_MASK_SRL_8822C 0x3f
+#define BIT_SRL_8822C(x) (((x) & BIT_MASK_SRL_8822C) << BIT_SHIFT_SRL_8822C)
+#define BITS_SRL_8822C (BIT_MASK_SRL_8822C << BIT_SHIFT_SRL_8822C)
+#define BIT_CLEAR_SRL_8822C(x) ((x) & (~BITS_SRL_8822C))
+#define BIT_GET_SRL_8822C(x) (((x) >> BIT_SHIFT_SRL_8822C) & BIT_MASK_SRL_8822C)
+#define BIT_SET_SRL_8822C(x, v) (BIT_CLEAR_SRL_8822C(x) | BIT_SRL_8822C(v))
+
+#define BIT_SHIFT_LRL_8822C 0
+#define BIT_MASK_LRL_8822C 0x3f
+#define BIT_LRL_8822C(x) (((x) & BIT_MASK_LRL_8822C) << BIT_SHIFT_LRL_8822C)
+#define BITS_LRL_8822C (BIT_MASK_LRL_8822C << BIT_SHIFT_LRL_8822C)
+#define BIT_CLEAR_LRL_8822C(x) ((x) & (~BITS_LRL_8822C))
+#define BIT_GET_LRL_8822C(x) (((x) >> BIT_SHIFT_LRL_8822C) & BIT_MASK_LRL_8822C)
+#define BIT_SET_LRL_8822C(x, v) (BIT_CLEAR_LRL_8822C(x) | BIT_LRL_8822C(v))
+
+/* 2 REG_TXBF_CTRL_8822C */
+#define BIT_R_ENABLE_NDPA_8822C BIT(31)
+#define BIT_USE_NDPA_PARAMETER_8822C BIT(30)
+#define BIT_R_PROP_TXBF_8822C BIT(29)
+#define BIT_R_EN_NDPA_INT_8822C BIT(28)
+#define BIT_R_TXBF1_80M_8822C BIT(27)
+#define BIT_R_TXBF1_40M_8822C BIT(26)
+#define BIT_R_TXBF1_20M_8822C BIT(25)
+
+#define BIT_SHIFT_R_TXBF1_AID_8822C 16
+#define BIT_MASK_R_TXBF1_AID_8822C 0x1ff
+#define BIT_R_TXBF1_AID_8822C(x)                                               \
+	(((x) & BIT_MASK_R_TXBF1_AID_8822C) << BIT_SHIFT_R_TXBF1_AID_8822C)
+#define BITS_R_TXBF1_AID_8822C                                                 \
+	(BIT_MASK_R_TXBF1_AID_8822C << BIT_SHIFT_R_TXBF1_AID_8822C)
+#define BIT_CLEAR_R_TXBF1_AID_8822C(x) ((x) & (~BITS_R_TXBF1_AID_8822C))
+#define BIT_GET_R_TXBF1_AID_8822C(x)                                           \
+	(((x) >> BIT_SHIFT_R_TXBF1_AID_8822C) & BIT_MASK_R_TXBF1_AID_8822C)
+#define BIT_SET_R_TXBF1_AID_8822C(x, v)                                        \
+	(BIT_CLEAR_R_TXBF1_AID_8822C(x) | BIT_R_TXBF1_AID_8822C(v))
+
+#define BIT_DIS_NDP_BFEN_8822C BIT(15)
+#define BIT_R_TXBCN_NOBLOCK_NDP_8822C BIT(14)
+#define BIT_R_TXBF0_80M_8822C BIT(11)
+#define BIT_R_TXBF0_40M_8822C BIT(10)
+#define BIT_R_TXBF0_20M_8822C BIT(9)
+
+#define BIT_SHIFT_R_TXBF0_AID_8822C 0
+#define BIT_MASK_R_TXBF0_AID_8822C 0x1ff
+#define BIT_R_TXBF0_AID_8822C(x)                                               \
+	(((x) & BIT_MASK_R_TXBF0_AID_8822C) << BIT_SHIFT_R_TXBF0_AID_8822C)
+#define BITS_R_TXBF0_AID_8822C                                                 \
+	(BIT_MASK_R_TXBF0_AID_8822C << BIT_SHIFT_R_TXBF0_AID_8822C)
+#define BIT_CLEAR_R_TXBF0_AID_8822C(x) ((x) & (~BITS_R_TXBF0_AID_8822C))
+#define BIT_GET_R_TXBF0_AID_8822C(x)                                           \
+	(((x) >> BIT_SHIFT_R_TXBF0_AID_8822C) & BIT_MASK_R_TXBF0_AID_8822C)
+#define BIT_SET_R_TXBF0_AID_8822C(x, v)                                        \
+	(BIT_CLEAR_R_TXBF0_AID_8822C(x) | BIT_R_TXBF0_AID_8822C(v))
+
+/* 2 REG_DARFRC_8822C */
+
+#define BIT_SHIFT_DARF_RC4_8822C 24
+#define BIT_MASK_DARF_RC4_8822C 0x1f
+#define BIT_DARF_RC4_8822C(x)                                                  \
+	(((x) & BIT_MASK_DARF_RC4_8822C) << BIT_SHIFT_DARF_RC4_8822C)
+#define BITS_DARF_RC4_8822C                                                    \
+	(BIT_MASK_DARF_RC4_8822C << BIT_SHIFT_DARF_RC4_8822C)
+#define BIT_CLEAR_DARF_RC4_8822C(x) ((x) & (~BITS_DARF_RC4_8822C))
+#define BIT_GET_DARF_RC4_8822C(x)                                              \
+	(((x) >> BIT_SHIFT_DARF_RC4_8822C) & BIT_MASK_DARF_RC4_8822C)
+#define BIT_SET_DARF_RC4_8822C(x, v)                                           \
+	(BIT_CLEAR_DARF_RC4_8822C(x) | BIT_DARF_RC4_8822C(v))
+
+#define BIT_SHIFT_DARF_RC3_8822C 16
+#define BIT_MASK_DARF_RC3_8822C 0x1f
+#define BIT_DARF_RC3_8822C(x)                                                  \
+	(((x) & BIT_MASK_DARF_RC3_8822C) << BIT_SHIFT_DARF_RC3_8822C)
+#define BITS_DARF_RC3_8822C                                                    \
+	(BIT_MASK_DARF_RC3_8822C << BIT_SHIFT_DARF_RC3_8822C)
+#define BIT_CLEAR_DARF_RC3_8822C(x) ((x) & (~BITS_DARF_RC3_8822C))
+#define BIT_GET_DARF_RC3_8822C(x)                                              \
+	(((x) >> BIT_SHIFT_DARF_RC3_8822C) & BIT_MASK_DARF_RC3_8822C)
+#define BIT_SET_DARF_RC3_8822C(x, v)                                           \
+	(BIT_CLEAR_DARF_RC3_8822C(x) | BIT_DARF_RC3_8822C(v))
+
+#define BIT_SHIFT_DARF_RC2_8822C 8
+#define BIT_MASK_DARF_RC2_8822C 0x1f
+#define BIT_DARF_RC2_8822C(x)                                                  \
+	(((x) & BIT_MASK_DARF_RC2_8822C) << BIT_SHIFT_DARF_RC2_8822C)
+#define BITS_DARF_RC2_8822C                                                    \
+	(BIT_MASK_DARF_RC2_8822C << BIT_SHIFT_DARF_RC2_8822C)
+#define BIT_CLEAR_DARF_RC2_8822C(x) ((x) & (~BITS_DARF_RC2_8822C))
+#define BIT_GET_DARF_RC2_8822C(x)                                              \
+	(((x) >> BIT_SHIFT_DARF_RC2_8822C) & BIT_MASK_DARF_RC2_8822C)
+#define BIT_SET_DARF_RC2_8822C(x, v)                                           \
+	(BIT_CLEAR_DARF_RC2_8822C(x) | BIT_DARF_RC2_8822C(v))
+
+#define BIT_SHIFT_DARF_RC1_8822C 0
+#define BIT_MASK_DARF_RC1_8822C 0x1f
+#define BIT_DARF_RC1_8822C(x)                                                  \
+	(((x) & BIT_MASK_DARF_RC1_8822C) << BIT_SHIFT_DARF_RC1_8822C)
+#define BITS_DARF_RC1_8822C                                                    \
+	(BIT_MASK_DARF_RC1_8822C << BIT_SHIFT_DARF_RC1_8822C)
+#define BIT_CLEAR_DARF_RC1_8822C(x) ((x) & (~BITS_DARF_RC1_8822C))
+#define BIT_GET_DARF_RC1_8822C(x)                                              \
+	(((x) >> BIT_SHIFT_DARF_RC1_8822C) & BIT_MASK_DARF_RC1_8822C)
+#define BIT_SET_DARF_RC1_8822C(x, v)                                           \
+	(BIT_CLEAR_DARF_RC1_8822C(x) | BIT_DARF_RC1_8822C(v))
+
+/* 2 REG_DARFRCH_8822C */
+
+#define BIT_SHIFT_DARF_RC8_V1_8822C 24
+#define BIT_MASK_DARF_RC8_V1_8822C 0x1f
+#define BIT_DARF_RC8_V1_8822C(x)                                               \
+	(((x) & BIT_MASK_DARF_RC8_V1_8822C) << BIT_SHIFT_DARF_RC8_V1_8822C)
+#define BITS_DARF_RC8_V1_8822C                                                 \
+	(BIT_MASK_DARF_RC8_V1_8822C << BIT_SHIFT_DARF_RC8_V1_8822C)
+#define BIT_CLEAR_DARF_RC8_V1_8822C(x) ((x) & (~BITS_DARF_RC8_V1_8822C))
+#define BIT_GET_DARF_RC8_V1_8822C(x)                                           \
+	(((x) >> BIT_SHIFT_DARF_RC8_V1_8822C) & BIT_MASK_DARF_RC8_V1_8822C)
+#define BIT_SET_DARF_RC8_V1_8822C(x, v)                                        \
+	(BIT_CLEAR_DARF_RC8_V1_8822C(x) | BIT_DARF_RC8_V1_8822C(v))
+
+#define BIT_SHIFT_DARF_RC7_V1_8822C 16
+#define BIT_MASK_DARF_RC7_V1_8822C 0x1f
+#define BIT_DARF_RC7_V1_8822C(x)                                               \
+	(((x) & BIT_MASK_DARF_RC7_V1_8822C) << BIT_SHIFT_DARF_RC7_V1_8822C)
+#define BITS_DARF_RC7_V1_8822C                                                 \
+	(BIT_MASK_DARF_RC7_V1_8822C << BIT_SHIFT_DARF_RC7_V1_8822C)
+#define BIT_CLEAR_DARF_RC7_V1_8822C(x) ((x) & (~BITS_DARF_RC7_V1_8822C))
+#define BIT_GET_DARF_RC7_V1_8822C(x)                                           \
+	(((x) >> BIT_SHIFT_DARF_RC7_V1_8822C) & BIT_MASK_DARF_RC7_V1_8822C)
+#define BIT_SET_DARF_RC7_V1_8822C(x, v)                                        \
+	(BIT_CLEAR_DARF_RC7_V1_8822C(x) | BIT_DARF_RC7_V1_8822C(v))
+
+#define BIT_SHIFT_DARF_RC6_V1_8822C 8
+#define BIT_MASK_DARF_RC6_V1_8822C 0x1f
+#define BIT_DARF_RC6_V1_8822C(x)                                               \
+	(((x) & BIT_MASK_DARF_RC6_V1_8822C) << BIT_SHIFT_DARF_RC6_V1_8822C)
+#define BITS_DARF_RC6_V1_8822C                                                 \
+	(BIT_MASK_DARF_RC6_V1_8822C << BIT_SHIFT_DARF_RC6_V1_8822C)
+#define BIT_CLEAR_DARF_RC6_V1_8822C(x) ((x) & (~BITS_DARF_RC6_V1_8822C))
+#define BIT_GET_DARF_RC6_V1_8822C(x)                                           \
+	(((x) >> BIT_SHIFT_DARF_RC6_V1_8822C) & BIT_MASK_DARF_RC6_V1_8822C)
+#define BIT_SET_DARF_RC6_V1_8822C(x, v)                                        \
+	(BIT_CLEAR_DARF_RC6_V1_8822C(x) | BIT_DARF_RC6_V1_8822C(v))
+
+#define BIT_SHIFT_DARF_RC5_V1_8822C 0
+#define BIT_MASK_DARF_RC5_V1_8822C 0x1f
+#define BIT_DARF_RC5_V1_8822C(x)                                               \
+	(((x) & BIT_MASK_DARF_RC5_V1_8822C) << BIT_SHIFT_DARF_RC5_V1_8822C)
+#define BITS_DARF_RC5_V1_8822C                                                 \
+	(BIT_MASK_DARF_RC5_V1_8822C << BIT_SHIFT_DARF_RC5_V1_8822C)
+#define BIT_CLEAR_DARF_RC5_V1_8822C(x) ((x) & (~BITS_DARF_RC5_V1_8822C))
+#define BIT_GET_DARF_RC5_V1_8822C(x)                                           \
+	(((x) >> BIT_SHIFT_DARF_RC5_V1_8822C) & BIT_MASK_DARF_RC5_V1_8822C)
+#define BIT_SET_DARF_RC5_V1_8822C(x, v)                                        \
+	(BIT_CLEAR_DARF_RC5_V1_8822C(x) | BIT_DARF_RC5_V1_8822C(v))
+
+/* 2 REG_RARFRC_8822C */
+
+#define BIT_SHIFT_RARF_RC4_8822C 24
+#define BIT_MASK_RARF_RC4_8822C 0x1f
+#define BIT_RARF_RC4_8822C(x)                                                  \
+	(((x) & BIT_MASK_RARF_RC4_8822C) << BIT_SHIFT_RARF_RC4_8822C)
+#define BITS_RARF_RC4_8822C                                                    \
+	(BIT_MASK_RARF_RC4_8822C << BIT_SHIFT_RARF_RC4_8822C)
+#define BIT_CLEAR_RARF_RC4_8822C(x) ((x) & (~BITS_RARF_RC4_8822C))
+#define BIT_GET_RARF_RC4_8822C(x)                                              \
+	(((x) >> BIT_SHIFT_RARF_RC4_8822C) & BIT_MASK_RARF_RC4_8822C)
+#define BIT_SET_RARF_RC4_8822C(x, v)                                           \
+	(BIT_CLEAR_RARF_RC4_8822C(x) | BIT_RARF_RC4_8822C(v))
+
+#define BIT_SHIFT_RARF_RC3_8822C 16
+#define BIT_MASK_RARF_RC3_8822C 0x1f
+#define BIT_RARF_RC3_8822C(x)                                                  \
+	(((x) & BIT_MASK_RARF_RC3_8822C) << BIT_SHIFT_RARF_RC3_8822C)
+#define BITS_RARF_RC3_8822C                                                    \
+	(BIT_MASK_RARF_RC3_8822C << BIT_SHIFT_RARF_RC3_8822C)
+#define BIT_CLEAR_RARF_RC3_8822C(x) ((x) & (~BITS_RARF_RC3_8822C))
+#define BIT_GET_RARF_RC3_8822C(x)                                              \
+	(((x) >> BIT_SHIFT_RARF_RC3_8822C) & BIT_MASK_RARF_RC3_8822C)
+#define BIT_SET_RARF_RC3_8822C(x, v)                                           \
+	(BIT_CLEAR_RARF_RC3_8822C(x) | BIT_RARF_RC3_8822C(v))
+
+#define BIT_SHIFT_RARF_RC2_8822C 8
+#define BIT_MASK_RARF_RC2_8822C 0x1f
+#define BIT_RARF_RC2_8822C(x)                                                  \
+	(((x) & BIT_MASK_RARF_RC2_8822C) << BIT_SHIFT_RARF_RC2_8822C)
+#define BITS_RARF_RC2_8822C                                                    \
+	(BIT_MASK_RARF_RC2_8822C << BIT_SHIFT_RARF_RC2_8822C)
+#define BIT_CLEAR_RARF_RC2_8822C(x) ((x) & (~BITS_RARF_RC2_8822C))
+#define BIT_GET_RARF_RC2_8822C(x)                                              \
+	(((x) >> BIT_SHIFT_RARF_RC2_8822C) & BIT_MASK_RARF_RC2_8822C)
+#define BIT_SET_RARF_RC2_8822C(x, v)                                           \
+	(BIT_CLEAR_RARF_RC2_8822C(x) | BIT_RARF_RC2_8822C(v))
+
+#define BIT_SHIFT_RARF_RC1_8822C 0
+#define BIT_MASK_RARF_RC1_8822C 0x1f
+#define BIT_RARF_RC1_8822C(x)                                                  \
+	(((x) & BIT_MASK_RARF_RC1_8822C) << BIT_SHIFT_RARF_RC1_8822C)
+#define BITS_RARF_RC1_8822C                                                    \
+	(BIT_MASK_RARF_RC1_8822C << BIT_SHIFT_RARF_RC1_8822C)
+#define BIT_CLEAR_RARF_RC1_8822C(x) ((x) & (~BITS_RARF_RC1_8822C))
+#define BIT_GET_RARF_RC1_8822C(x)                                              \
+	(((x) >> BIT_SHIFT_RARF_RC1_8822C) & BIT_MASK_RARF_RC1_8822C)
+#define BIT_SET_RARF_RC1_8822C(x, v)                                           \
+	(BIT_CLEAR_RARF_RC1_8822C(x) | BIT_RARF_RC1_8822C(v))
+
+/* 2 REG_RARFRCH_8822C */
+
+#define BIT_SHIFT_RARF_RC8_V1_8822C 24
+#define BIT_MASK_RARF_RC8_V1_8822C 0x1f
+#define BIT_RARF_RC8_V1_8822C(x)                                               \
+	(((x) & BIT_MASK_RARF_RC8_V1_8822C) << BIT_SHIFT_RARF_RC8_V1_8822C)
+#define BITS_RARF_RC8_V1_8822C                                                 \
+	(BIT_MASK_RARF_RC8_V1_8822C << BIT_SHIFT_RARF_RC8_V1_8822C)
+#define BIT_CLEAR_RARF_RC8_V1_8822C(x) ((x) & (~BITS_RARF_RC8_V1_8822C))
+#define BIT_GET_RARF_RC8_V1_8822C(x)                                           \
+	(((x) >> BIT_SHIFT_RARF_RC8_V1_8822C) & BIT_MASK_RARF_RC8_V1_8822C)
+#define BIT_SET_RARF_RC8_V1_8822C(x, v)                                        \
+	(BIT_CLEAR_RARF_RC8_V1_8822C(x) | BIT_RARF_RC8_V1_8822C(v))
+
+#define BIT_SHIFT_RARF_RC7_V1_8822C 16
+#define BIT_MASK_RARF_RC7_V1_8822C 0x1f
+#define BIT_RARF_RC7_V1_8822C(x)                                               \
+	(((x) & BIT_MASK_RARF_RC7_V1_8822C) << BIT_SHIFT_RARF_RC7_V1_8822C)
+#define BITS_RARF_RC7_V1_8822C                                                 \
+	(BIT_MASK_RARF_RC7_V1_8822C << BIT_SHIFT_RARF_RC7_V1_8822C)
+#define BIT_CLEAR_RARF_RC7_V1_8822C(x) ((x) & (~BITS_RARF_RC7_V1_8822C))
+#define BIT_GET_RARF_RC7_V1_8822C(x)                                           \
+	(((x) >> BIT_SHIFT_RARF_RC7_V1_8822C) & BIT_MASK_RARF_RC7_V1_8822C)
+#define BIT_SET_RARF_RC7_V1_8822C(x, v)                                        \
+	(BIT_CLEAR_RARF_RC7_V1_8822C(x) | BIT_RARF_RC7_V1_8822C(v))
+
+#define BIT_SHIFT_RARF_RC6_V1_8822C 8
+#define BIT_MASK_RARF_RC6_V1_8822C 0x1f
+#define BIT_RARF_RC6_V1_8822C(x)                                               \
+	(((x) & BIT_MASK_RARF_RC6_V1_8822C) << BIT_SHIFT_RARF_RC6_V1_8822C)
+#define BITS_RARF_RC6_V1_8822C                                                 \
+	(BIT_MASK_RARF_RC6_V1_8822C << BIT_SHIFT_RARF_RC6_V1_8822C)
+#define BIT_CLEAR_RARF_RC6_V1_8822C(x) ((x) & (~BITS_RARF_RC6_V1_8822C))
+#define BIT_GET_RARF_RC6_V1_8822C(x)                                           \
+	(((x) >> BIT_SHIFT_RARF_RC6_V1_8822C) & BIT_MASK_RARF_RC6_V1_8822C)
+#define BIT_SET_RARF_RC6_V1_8822C(x, v)                                        \
+	(BIT_CLEAR_RARF_RC6_V1_8822C(x) | BIT_RARF_RC6_V1_8822C(v))
+
+#define BIT_SHIFT_RARF_RC5_V1_8822C 0
+#define BIT_MASK_RARF_RC5_V1_8822C 0x1f
+#define BIT_RARF_RC5_V1_8822C(x)                                               \
+	(((x) & BIT_MASK_RARF_RC5_V1_8822C) << BIT_SHIFT_RARF_RC5_V1_8822C)
+#define BITS_RARF_RC5_V1_8822C                                                 \
+	(BIT_MASK_RARF_RC5_V1_8822C << BIT_SHIFT_RARF_RC5_V1_8822C)
+#define BIT_CLEAR_RARF_RC5_V1_8822C(x) ((x) & (~BITS_RARF_RC5_V1_8822C))
+#define BIT_GET_RARF_RC5_V1_8822C(x)                                           \
+	(((x) >> BIT_SHIFT_RARF_RC5_V1_8822C) & BIT_MASK_RARF_RC5_V1_8822C)
+#define BIT_SET_RARF_RC5_V1_8822C(x, v)                                        \
+	(BIT_CLEAR_RARF_RC5_V1_8822C(x) | BIT_RARF_RC5_V1_8822C(v))
+
+/* 2 REG_RRSR_8822C */
+
+#define BIT_SHIFT_RRSR_RSC_8822C 21
+#define BIT_MASK_RRSR_RSC_8822C 0x3
+#define BIT_RRSR_RSC_8822C(x)                                                  \
+	(((x) & BIT_MASK_RRSR_RSC_8822C) << BIT_SHIFT_RRSR_RSC_8822C)
+#define BITS_RRSR_RSC_8822C                                                    \
+	(BIT_MASK_RRSR_RSC_8822C << BIT_SHIFT_RRSR_RSC_8822C)
+#define BIT_CLEAR_RRSR_RSC_8822C(x) ((x) & (~BITS_RRSR_RSC_8822C))
+#define BIT_GET_RRSR_RSC_8822C(x)                                              \
+	(((x) >> BIT_SHIFT_RRSR_RSC_8822C) & BIT_MASK_RRSR_RSC_8822C)
+#define BIT_SET_RRSR_RSC_8822C(x, v)                                           \
+	(BIT_CLEAR_RRSR_RSC_8822C(x) | BIT_RRSR_RSC_8822C(v))
+
+#define BIT_SHIFT_RRSC_BITMAP_8822C 0
+#define BIT_MASK_RRSC_BITMAP_8822C 0xfffff
+#define BIT_RRSC_BITMAP_8822C(x)                                               \
+	(((x) & BIT_MASK_RRSC_BITMAP_8822C) << BIT_SHIFT_RRSC_BITMAP_8822C)
+#define BITS_RRSC_BITMAP_8822C                                                 \
+	(BIT_MASK_RRSC_BITMAP_8822C << BIT_SHIFT_RRSC_BITMAP_8822C)
+#define BIT_CLEAR_RRSC_BITMAP_8822C(x) ((x) & (~BITS_RRSC_BITMAP_8822C))
+#define BIT_GET_RRSC_BITMAP_8822C(x)                                           \
+	(((x) >> BIT_SHIFT_RRSC_BITMAP_8822C) & BIT_MASK_RRSC_BITMAP_8822C)
+#define BIT_SET_RRSC_BITMAP_8822C(x, v)                                        \
+	(BIT_CLEAR_RRSC_BITMAP_8822C(x) | BIT_RRSC_BITMAP_8822C(v))
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_ARFR0_8822C */
+
+#define BIT_SHIFT_ARFRL0_8822C 0
+#define BIT_MASK_ARFRL0_8822C 0xffffffffL
+#define BIT_ARFRL0_8822C(x)                                                    \
+	(((x) & BIT_MASK_ARFRL0_8822C) << BIT_SHIFT_ARFRL0_8822C)
+#define BITS_ARFRL0_8822C (BIT_MASK_ARFRL0_8822C << BIT_SHIFT_ARFRL0_8822C)
+#define BIT_CLEAR_ARFRL0_8822C(x) ((x) & (~BITS_ARFRL0_8822C))
+#define BIT_GET_ARFRL0_8822C(x)                                                \
+	(((x) >> BIT_SHIFT_ARFRL0_8822C) & BIT_MASK_ARFRL0_8822C)
+#define BIT_SET_ARFRL0_8822C(x, v)                                             \
+	(BIT_CLEAR_ARFRL0_8822C(x) | BIT_ARFRL0_8822C(v))
+
+/* 2 REG_ARFRH0_8822C */
+
+#define BIT_SHIFT_ARFRH0_8822C 0
+#define BIT_MASK_ARFRH0_8822C 0xffffffffL
+#define BIT_ARFRH0_8822C(x)                                                    \
+	(((x) & BIT_MASK_ARFRH0_8822C) << BIT_SHIFT_ARFRH0_8822C)
+#define BITS_ARFRH0_8822C (BIT_MASK_ARFRH0_8822C << BIT_SHIFT_ARFRH0_8822C)
+#define BIT_CLEAR_ARFRH0_8822C(x) ((x) & (~BITS_ARFRH0_8822C))
+#define BIT_GET_ARFRH0_8822C(x)                                                \
+	(((x) >> BIT_SHIFT_ARFRH0_8822C) & BIT_MASK_ARFRH0_8822C)
+#define BIT_SET_ARFRH0_8822C(x, v)                                             \
+	(BIT_CLEAR_ARFRH0_8822C(x) | BIT_ARFRH0_8822C(v))
+
+/* 2 REG_ARFR1_V1_8822C */
+
+#define BIT_SHIFT_ARFRL1_8822C 0
+#define BIT_MASK_ARFRL1_8822C 0xffffffffL
+#define BIT_ARFRL1_8822C(x)                                                    \
+	(((x) & BIT_MASK_ARFRL1_8822C) << BIT_SHIFT_ARFRL1_8822C)
+#define BITS_ARFRL1_8822C (BIT_MASK_ARFRL1_8822C << BIT_SHIFT_ARFRL1_8822C)
+#define BIT_CLEAR_ARFRL1_8822C(x) ((x) & (~BITS_ARFRL1_8822C))
+#define BIT_GET_ARFRL1_8822C(x)                                                \
+	(((x) >> BIT_SHIFT_ARFRL1_8822C) & BIT_MASK_ARFRL1_8822C)
+#define BIT_SET_ARFRL1_8822C(x, v)                                             \
+	(BIT_CLEAR_ARFRL1_8822C(x) | BIT_ARFRL1_8822C(v))
+
+/* 2 REG_ARFRH1_V1_8822C */
+
+#define BIT_SHIFT_ARFRH1_8822C 0
+#define BIT_MASK_ARFRH1_8822C 0xffffffffL
+#define BIT_ARFRH1_8822C(x)                                                    \
+	(((x) & BIT_MASK_ARFRH1_8822C) << BIT_SHIFT_ARFRH1_8822C)
+#define BITS_ARFRH1_8822C (BIT_MASK_ARFRH1_8822C << BIT_SHIFT_ARFRH1_8822C)
+#define BIT_CLEAR_ARFRH1_8822C(x) ((x) & (~BITS_ARFRH1_8822C))
+#define BIT_GET_ARFRH1_8822C(x)                                                \
+	(((x) >> BIT_SHIFT_ARFRH1_8822C) & BIT_MASK_ARFRH1_8822C)
+#define BIT_SET_ARFRH1_8822C(x, v)                                             \
+	(BIT_CLEAR_ARFRH1_8822C(x) | BIT_ARFRH1_8822C(v))
+
+/* 2 REG_CCK_CHECK_8822C */
+#define BIT_CHECK_CCK_EN_8822C BIT(7)
+#define BIT_EN_BCN_PKT_REL_8822C BIT(6)
+#define BIT_BCN_PORT_SEL_8822C BIT(5)
+#define BIT_MOREDATA_BYPASS_8822C BIT(4)
+#define BIT_EN_CLR_CMD_REL_BCN_PKT_8822C BIT(3)
+#define BIT_R_EN_SET_MOREDATA_8822C BIT(2)
+#define BIT__R_DIS_CLEAR_MACID_RELEASE_8822C BIT(1)
+#define BIT__R_MACID_RELEASE_EN_8822C BIT(0)
+
+/* 2 REG_AMPDU_MAX_TIME_V1_8822C */
+
+#define BIT_SHIFT_AMPDU_MAX_TIME_8822C 0
+#define BIT_MASK_AMPDU_MAX_TIME_8822C 0xff
+#define BIT_AMPDU_MAX_TIME_8822C(x)                                            \
+	(((x) & BIT_MASK_AMPDU_MAX_TIME_8822C)                                 \
+	 << BIT_SHIFT_AMPDU_MAX_TIME_8822C)
+#define BITS_AMPDU_MAX_TIME_8822C                                              \
+	(BIT_MASK_AMPDU_MAX_TIME_8822C << BIT_SHIFT_AMPDU_MAX_TIME_8822C)
+#define BIT_CLEAR_AMPDU_MAX_TIME_8822C(x) ((x) & (~BITS_AMPDU_MAX_TIME_8822C))
+#define BIT_GET_AMPDU_MAX_TIME_8822C(x)                                        \
+	(((x) >> BIT_SHIFT_AMPDU_MAX_TIME_8822C) &                             \
+	 BIT_MASK_AMPDU_MAX_TIME_8822C)
+#define BIT_SET_AMPDU_MAX_TIME_8822C(x, v)                                     \
+	(BIT_CLEAR_AMPDU_MAX_TIME_8822C(x) | BIT_AMPDU_MAX_TIME_8822C(v))
+
+/* 2 REG_BCNQ1_BDNY_V1_8822C */
+
+#define BIT_SHIFT_BCNQ1_PGBNDY_V1_8822C 0
+#define BIT_MASK_BCNQ1_PGBNDY_V1_8822C 0xfff
+#define BIT_BCNQ1_PGBNDY_V1_8822C(x)                                           \
+	(((x) & BIT_MASK_BCNQ1_PGBNDY_V1_8822C)                                \
+	 << BIT_SHIFT_BCNQ1_PGBNDY_V1_8822C)
+#define BITS_BCNQ1_PGBNDY_V1_8822C                                             \
+	(BIT_MASK_BCNQ1_PGBNDY_V1_8822C << BIT_SHIFT_BCNQ1_PGBNDY_V1_8822C)
+#define BIT_CLEAR_BCNQ1_PGBNDY_V1_8822C(x) ((x) & (~BITS_BCNQ1_PGBNDY_V1_8822C))
+#define BIT_GET_BCNQ1_PGBNDY_V1_8822C(x)                                       \
+	(((x) >> BIT_SHIFT_BCNQ1_PGBNDY_V1_8822C) &                            \
+	 BIT_MASK_BCNQ1_PGBNDY_V1_8822C)
+#define BIT_SET_BCNQ1_PGBNDY_V1_8822C(x, v)                                    \
+	(BIT_CLEAR_BCNQ1_PGBNDY_V1_8822C(x) | BIT_BCNQ1_PGBNDY_V1_8822C(v))
+
+/* 2 REG_AMPDU_MAX_LENGTH_HT_8822C */
+
+#define BIT_SHIFT_AMPDU_MAX_LENGTH_HT_8822C 0
+#define BIT_MASK_AMPDU_MAX_LENGTH_HT_8822C 0xffff
+#define BIT_AMPDU_MAX_LENGTH_HT_8822C(x)                                       \
+	(((x) & BIT_MASK_AMPDU_MAX_LENGTH_HT_8822C)                            \
+	 << BIT_SHIFT_AMPDU_MAX_LENGTH_HT_8822C)
+#define BITS_AMPDU_MAX_LENGTH_HT_8822C                                         \
+	(BIT_MASK_AMPDU_MAX_LENGTH_HT_8822C                                    \
+	 << BIT_SHIFT_AMPDU_MAX_LENGTH_HT_8822C)
+#define BIT_CLEAR_AMPDU_MAX_LENGTH_HT_8822C(x)                                 \
+	((x) & (~BITS_AMPDU_MAX_LENGTH_HT_8822C))
+#define BIT_GET_AMPDU_MAX_LENGTH_HT_8822C(x)                                   \
+	(((x) >> BIT_SHIFT_AMPDU_MAX_LENGTH_HT_8822C) &                        \
+	 BIT_MASK_AMPDU_MAX_LENGTH_HT_8822C)
+#define BIT_SET_AMPDU_MAX_LENGTH_HT_8822C(x, v)                                \
+	(BIT_CLEAR_AMPDU_MAX_LENGTH_HT_8822C(x) |                              \
+	 BIT_AMPDU_MAX_LENGTH_HT_8822C(v))
+
+/* 2 REG_ACQ_STOP_8822C */
+#define BIT_AC7Q_STOP_8822C BIT(7)
+#define BIT_AC6Q_STOP_8822C BIT(6)
+#define BIT_AC5Q_STOP_8822C BIT(5)
+#define BIT_AC4Q_STOP_8822C BIT(4)
+#define BIT_AC3Q_STOP_8822C BIT(3)
+#define BIT_AC2Q_STOP_8822C BIT(2)
+#define BIT_AC1Q_STOP_8822C BIT(1)
+#define BIT_AC0Q_STOP_8822C BIT(0)
+
+/* 2 REG_NDPA_RATE_8822C */
+
+#define BIT_SHIFT_R_NDPA_RATE_V1_8822C 0
+#define BIT_MASK_R_NDPA_RATE_V1_8822C 0xff
+#define BIT_R_NDPA_RATE_V1_8822C(x)                                            \
+	(((x) & BIT_MASK_R_NDPA_RATE_V1_8822C)                                 \
+	 << BIT_SHIFT_R_NDPA_RATE_V1_8822C)
+#define BITS_R_NDPA_RATE_V1_8822C                                              \
+	(BIT_MASK_R_NDPA_RATE_V1_8822C << BIT_SHIFT_R_NDPA_RATE_V1_8822C)
+#define BIT_CLEAR_R_NDPA_RATE_V1_8822C(x) ((x) & (~BITS_R_NDPA_RATE_V1_8822C))
+#define BIT_GET_R_NDPA_RATE_V1_8822C(x)                                        \
+	(((x) >> BIT_SHIFT_R_NDPA_RATE_V1_8822C) &                             \
+	 BIT_MASK_R_NDPA_RATE_V1_8822C)
+#define BIT_SET_R_NDPA_RATE_V1_8822C(x, v)                                     \
+	(BIT_CLEAR_R_NDPA_RATE_V1_8822C(x) | BIT_R_NDPA_RATE_V1_8822C(v))
+
+/* 2 REG_TX_HANG_CTRL_8822C */
+#define BIT_R_EN_GNT_BT_AWAKE_8822C BIT(3)
+#define BIT_EN_EOF_V1_8822C BIT(2)
+#define BIT_DIS_OQT_BLOCK_8822C BIT(1)
+#define BIT_SEARCH_QUEUE_EN_8822C BIT(0)
+
+/* 2 REG_NDPA_OPT_CTRL_8822C */
+#define BIT_R_DIS_MACID_RELEASE_RTY_8822C BIT(5)
+
+#define BIT_SHIFT_BW_SIGTA_8822C 3
+#define BIT_MASK_BW_SIGTA_8822C 0x3
+#define BIT_BW_SIGTA_8822C(x)                                                  \
+	(((x) & BIT_MASK_BW_SIGTA_8822C) << BIT_SHIFT_BW_SIGTA_8822C)
+#define BITS_BW_SIGTA_8822C                                                    \
+	(BIT_MASK_BW_SIGTA_8822C << BIT_SHIFT_BW_SIGTA_8822C)
+#define BIT_CLEAR_BW_SIGTA_8822C(x) ((x) & (~BITS_BW_SIGTA_8822C))
+#define BIT_GET_BW_SIGTA_8822C(x)                                              \
+	(((x) >> BIT_SHIFT_BW_SIGTA_8822C) & BIT_MASK_BW_SIGTA_8822C)
+#define BIT_SET_BW_SIGTA_8822C(x, v)                                           \
+	(BIT_CLEAR_BW_SIGTA_8822C(x) | BIT_BW_SIGTA_8822C(v))
+
+#define BIT_EN_BAR_SIGTA_8822C BIT(2)
+
+#define BIT_SHIFT_R_NDPA_BW_8822C 0
+#define BIT_MASK_R_NDPA_BW_8822C 0x3
+#define BIT_R_NDPA_BW_8822C(x)                                                 \
+	(((x) & BIT_MASK_R_NDPA_BW_8822C) << BIT_SHIFT_R_NDPA_BW_8822C)
+#define BITS_R_NDPA_BW_8822C                                                   \
+	(BIT_MASK_R_NDPA_BW_8822C << BIT_SHIFT_R_NDPA_BW_8822C)
+#define BIT_CLEAR_R_NDPA_BW_8822C(x) ((x) & (~BITS_R_NDPA_BW_8822C))
+#define BIT_GET_R_NDPA_BW_8822C(x)                                             \
+	(((x) >> BIT_SHIFT_R_NDPA_BW_8822C) & BIT_MASK_R_NDPA_BW_8822C)
+#define BIT_SET_R_NDPA_BW_8822C(x, v)                                          \
+	(BIT_CLEAR_R_NDPA_BW_8822C(x) | BIT_R_NDPA_BW_8822C(v))
+
+/* 2 REG_AMPDU_MAX_LENGTH_VHT_8822C */
+
+#define BIT_SHIFT_AMPDU_MAX_LENGTH_VHT_V1_8822C 0
+#define BIT_MASK_AMPDU_MAX_LENGTH_VHT_V1_8822C 0xfffff
+#define BIT_AMPDU_MAX_LENGTH_VHT_V1_8822C(x)                                   \
+	(((x) & BIT_MASK_AMPDU_MAX_LENGTH_VHT_V1_8822C)                        \
+	 << BIT_SHIFT_AMPDU_MAX_LENGTH_VHT_V1_8822C)
+#define BITS_AMPDU_MAX_LENGTH_VHT_V1_8822C                                     \
+	(BIT_MASK_AMPDU_MAX_LENGTH_VHT_V1_8822C                                \
+	 << BIT_SHIFT_AMPDU_MAX_LENGTH_VHT_V1_8822C)
+#define BIT_CLEAR_AMPDU_MAX_LENGTH_VHT_V1_8822C(x)                             \
+	((x) & (~BITS_AMPDU_MAX_LENGTH_VHT_V1_8822C))
+#define BIT_GET_AMPDU_MAX_LENGTH_VHT_V1_8822C(x)                               \
+	(((x) >> BIT_SHIFT_AMPDU_MAX_LENGTH_VHT_V1_8822C) &                    \
+	 BIT_MASK_AMPDU_MAX_LENGTH_VHT_V1_8822C)
+#define BIT_SET_AMPDU_MAX_LENGTH_VHT_V1_8822C(x, v)                            \
+	(BIT_CLEAR_AMPDU_MAX_LENGTH_VHT_V1_8822C(x) |                          \
+	 BIT_AMPDU_MAX_LENGTH_VHT_V1_8822C(v))
+
+/* 2 REG_RD_RESP_PKT_TH_8822C */
+
+#define BIT_SHIFT_RD_RESP_PKT_TH_V1_8822C 0
+#define BIT_MASK_RD_RESP_PKT_TH_V1_8822C 0x3f
+#define BIT_RD_RESP_PKT_TH_V1_8822C(x)                                         \
+	(((x) & BIT_MASK_RD_RESP_PKT_TH_V1_8822C)                              \
+	 << BIT_SHIFT_RD_RESP_PKT_TH_V1_8822C)
+#define BITS_RD_RESP_PKT_TH_V1_8822C                                           \
+	(BIT_MASK_RD_RESP_PKT_TH_V1_8822C << BIT_SHIFT_RD_RESP_PKT_TH_V1_8822C)
+#define BIT_CLEAR_RD_RESP_PKT_TH_V1_8822C(x)                                   \
+	((x) & (~BITS_RD_RESP_PKT_TH_V1_8822C))
+#define BIT_GET_RD_RESP_PKT_TH_V1_8822C(x)                                     \
+	(((x) >> BIT_SHIFT_RD_RESP_PKT_TH_V1_8822C) &                          \
+	 BIT_MASK_RD_RESP_PKT_TH_V1_8822C)
+#define BIT_SET_RD_RESP_PKT_TH_V1_8822C(x, v)                                  \
+	(BIT_CLEAR_RD_RESP_PKT_TH_V1_8822C(x) | BIT_RD_RESP_PKT_TH_V1_8822C(v))
+
+/* 2 REG_CMDQ_INFO_8822C */
+
+#define BIT_SHIFT_QUEUEMACID_CMDQ_V1_8822C 25
+#define BIT_MASK_QUEUEMACID_CMDQ_V1_8822C 0x7f
+#define BIT_QUEUEMACID_CMDQ_V1_8822C(x)                                        \
+	(((x) & BIT_MASK_QUEUEMACID_CMDQ_V1_8822C)                             \
+	 << BIT_SHIFT_QUEUEMACID_CMDQ_V1_8822C)
+#define BITS_QUEUEMACID_CMDQ_V1_8822C                                          \
+	(BIT_MASK_QUEUEMACID_CMDQ_V1_8822C                                     \
+	 << BIT_SHIFT_QUEUEMACID_CMDQ_V1_8822C)
+#define BIT_CLEAR_QUEUEMACID_CMDQ_V1_8822C(x)                                  \
+	((x) & (~BITS_QUEUEMACID_CMDQ_V1_8822C))
+#define BIT_GET_QUEUEMACID_CMDQ_V1_8822C(x)                                    \
+	(((x) >> BIT_SHIFT_QUEUEMACID_CMDQ_V1_8822C) &                         \
+	 BIT_MASK_QUEUEMACID_CMDQ_V1_8822C)
+#define BIT_SET_QUEUEMACID_CMDQ_V1_8822C(x, v)                                 \
+	(BIT_CLEAR_QUEUEMACID_CMDQ_V1_8822C(x) |                               \
+	 BIT_QUEUEMACID_CMDQ_V1_8822C(v))
+
+#define BIT_SHIFT_QUEUEAC_CMDQ_V1_8822C 23
+#define BIT_MASK_QUEUEAC_CMDQ_V1_8822C 0x3
+#define BIT_QUEUEAC_CMDQ_V1_8822C(x)                                           \
+	(((x) & BIT_MASK_QUEUEAC_CMDQ_V1_8822C)                                \
+	 << BIT_SHIFT_QUEUEAC_CMDQ_V1_8822C)
+#define BITS_QUEUEAC_CMDQ_V1_8822C                                             \
+	(BIT_MASK_QUEUEAC_CMDQ_V1_8822C << BIT_SHIFT_QUEUEAC_CMDQ_V1_8822C)
+#define BIT_CLEAR_QUEUEAC_CMDQ_V1_8822C(x) ((x) & (~BITS_QUEUEAC_CMDQ_V1_8822C))
+#define BIT_GET_QUEUEAC_CMDQ_V1_8822C(x)                                       \
+	(((x) >> BIT_SHIFT_QUEUEAC_CMDQ_V1_8822C) &                            \
+	 BIT_MASK_QUEUEAC_CMDQ_V1_8822C)
+#define BIT_SET_QUEUEAC_CMDQ_V1_8822C(x, v)                                    \
+	(BIT_CLEAR_QUEUEAC_CMDQ_V1_8822C(x) | BIT_QUEUEAC_CMDQ_V1_8822C(v))
+
+#define BIT_TIDEMPTY_CMDQ_V1_8822C BIT(22)
+
+#define BIT_SHIFT_TAIL_PKT_Q4_V2_8822C 11
+#define BIT_MASK_TAIL_PKT_Q4_V2_8822C 0x7ff
+#define BIT_TAIL_PKT_Q4_V2_8822C(x)                                            \
+	(((x) & BIT_MASK_TAIL_PKT_Q4_V2_8822C)                                 \
+	 << BIT_SHIFT_TAIL_PKT_Q4_V2_8822C)
+#define BITS_TAIL_PKT_Q4_V2_8822C                                              \
+	(BIT_MASK_TAIL_PKT_Q4_V2_8822C << BIT_SHIFT_TAIL_PKT_Q4_V2_8822C)
+#define BIT_CLEAR_TAIL_PKT_Q4_V2_8822C(x) ((x) & (~BITS_TAIL_PKT_Q4_V2_8822C))
+#define BIT_GET_TAIL_PKT_Q4_V2_8822C(x)                                        \
+	(((x) >> BIT_SHIFT_TAIL_PKT_Q4_V2_8822C) &                             \
+	 BIT_MASK_TAIL_PKT_Q4_V2_8822C)
+#define BIT_SET_TAIL_PKT_Q4_V2_8822C(x, v)                                     \
+	(BIT_CLEAR_TAIL_PKT_Q4_V2_8822C(x) | BIT_TAIL_PKT_Q4_V2_8822C(v))
+
+#define BIT_SHIFT_HEAD_PKT_CMDQ_V1_8822C 0
+#define BIT_MASK_HEAD_PKT_CMDQ_V1_8822C 0x7ff
+#define BIT_HEAD_PKT_CMDQ_V1_8822C(x)                                          \
+	(((x) & BIT_MASK_HEAD_PKT_CMDQ_V1_8822C)                               \
+	 << BIT_SHIFT_HEAD_PKT_CMDQ_V1_8822C)
+#define BITS_HEAD_PKT_CMDQ_V1_8822C                                            \
+	(BIT_MASK_HEAD_PKT_CMDQ_V1_8822C << BIT_SHIFT_HEAD_PKT_CMDQ_V1_8822C)
+#define BIT_CLEAR_HEAD_PKT_CMDQ_V1_8822C(x)                                    \
+	((x) & (~BITS_HEAD_PKT_CMDQ_V1_8822C))
+#define BIT_GET_HEAD_PKT_CMDQ_V1_8822C(x)                                      \
+	(((x) >> BIT_SHIFT_HEAD_PKT_CMDQ_V1_8822C) &                           \
+	 BIT_MASK_HEAD_PKT_CMDQ_V1_8822C)
+#define BIT_SET_HEAD_PKT_CMDQ_V1_8822C(x, v)                                   \
+	(BIT_CLEAR_HEAD_PKT_CMDQ_V1_8822C(x) | BIT_HEAD_PKT_CMDQ_V1_8822C(v))
+
+/* 2 REG_Q4_INFO_8822C */
+
+#define BIT_SHIFT_QUEUEMACID_Q4_V1_8822C 25
+#define BIT_MASK_QUEUEMACID_Q4_V1_8822C 0x7f
+#define BIT_QUEUEMACID_Q4_V1_8822C(x)                                          \
+	(((x) & BIT_MASK_QUEUEMACID_Q4_V1_8822C)                               \
+	 << BIT_SHIFT_QUEUEMACID_Q4_V1_8822C)
+#define BITS_QUEUEMACID_Q4_V1_8822C                                            \
+	(BIT_MASK_QUEUEMACID_Q4_V1_8822C << BIT_SHIFT_QUEUEMACID_Q4_V1_8822C)
+#define BIT_CLEAR_QUEUEMACID_Q4_V1_8822C(x)                                    \
+	((x) & (~BITS_QUEUEMACID_Q4_V1_8822C))
+#define BIT_GET_QUEUEMACID_Q4_V1_8822C(x)                                      \
+	(((x) >> BIT_SHIFT_QUEUEMACID_Q4_V1_8822C) &                           \
+	 BIT_MASK_QUEUEMACID_Q4_V1_8822C)
+#define BIT_SET_QUEUEMACID_Q4_V1_8822C(x, v)                                   \
+	(BIT_CLEAR_QUEUEMACID_Q4_V1_8822C(x) | BIT_QUEUEMACID_Q4_V1_8822C(v))
+
+#define BIT_SHIFT_QUEUEAC_Q4_V1_8822C 23
+#define BIT_MASK_QUEUEAC_Q4_V1_8822C 0x3
+#define BIT_QUEUEAC_Q4_V1_8822C(x)                                             \
+	(((x) & BIT_MASK_QUEUEAC_Q4_V1_8822C) << BIT_SHIFT_QUEUEAC_Q4_V1_8822C)
+#define BITS_QUEUEAC_Q4_V1_8822C                                               \
+	(BIT_MASK_QUEUEAC_Q4_V1_8822C << BIT_SHIFT_QUEUEAC_Q4_V1_8822C)
+#define BIT_CLEAR_QUEUEAC_Q4_V1_8822C(x) ((x) & (~BITS_QUEUEAC_Q4_V1_8822C))
+#define BIT_GET_QUEUEAC_Q4_V1_8822C(x)                                         \
+	(((x) >> BIT_SHIFT_QUEUEAC_Q4_V1_8822C) & BIT_MASK_QUEUEAC_Q4_V1_8822C)
+#define BIT_SET_QUEUEAC_Q4_V1_8822C(x, v)                                      \
+	(BIT_CLEAR_QUEUEAC_Q4_V1_8822C(x) | BIT_QUEUEAC_Q4_V1_8822C(v))
+
+#define BIT_TIDEMPTY_Q4_V1_8822C BIT(22)
+
+#define BIT_SHIFT_TAIL_PKT_Q4_V2_8822C 11
+#define BIT_MASK_TAIL_PKT_Q4_V2_8822C 0x7ff
+#define BIT_TAIL_PKT_Q4_V2_8822C(x)                                            \
+	(((x) & BIT_MASK_TAIL_PKT_Q4_V2_8822C)                                 \
+	 << BIT_SHIFT_TAIL_PKT_Q4_V2_8822C)
+#define BITS_TAIL_PKT_Q4_V2_8822C                                              \
+	(BIT_MASK_TAIL_PKT_Q4_V2_8822C << BIT_SHIFT_TAIL_PKT_Q4_V2_8822C)
+#define BIT_CLEAR_TAIL_PKT_Q4_V2_8822C(x) ((x) & (~BITS_TAIL_PKT_Q4_V2_8822C))
+#define BIT_GET_TAIL_PKT_Q4_V2_8822C(x)                                        \
+	(((x) >> BIT_SHIFT_TAIL_PKT_Q4_V2_8822C) &                             \
+	 BIT_MASK_TAIL_PKT_Q4_V2_8822C)
+#define BIT_SET_TAIL_PKT_Q4_V2_8822C(x, v)                                     \
+	(BIT_CLEAR_TAIL_PKT_Q4_V2_8822C(x) | BIT_TAIL_PKT_Q4_V2_8822C(v))
+
+#define BIT_SHIFT_HEAD_PKT_Q4_V1_8822C 0
+#define BIT_MASK_HEAD_PKT_Q4_V1_8822C 0x7ff
+#define BIT_HEAD_PKT_Q4_V1_8822C(x)                                            \
+	(((x) & BIT_MASK_HEAD_PKT_Q4_V1_8822C)                                 \
+	 << BIT_SHIFT_HEAD_PKT_Q4_V1_8822C)
+#define BITS_HEAD_PKT_Q4_V1_8822C                                              \
+	(BIT_MASK_HEAD_PKT_Q4_V1_8822C << BIT_SHIFT_HEAD_PKT_Q4_V1_8822C)
+#define BIT_CLEAR_HEAD_PKT_Q4_V1_8822C(x) ((x) & (~BITS_HEAD_PKT_Q4_V1_8822C))
+#define BIT_GET_HEAD_PKT_Q4_V1_8822C(x)                                        \
+	(((x) >> BIT_SHIFT_HEAD_PKT_Q4_V1_8822C) &                             \
+	 BIT_MASK_HEAD_PKT_Q4_V1_8822C)
+#define BIT_SET_HEAD_PKT_Q4_V1_8822C(x, v)                                     \
+	(BIT_CLEAR_HEAD_PKT_Q4_V1_8822C(x) | BIT_HEAD_PKT_Q4_V1_8822C(v))
+
+/* 2 REG_Q5_INFO_8822C */
+
+#define BIT_SHIFT_QUEUEMACID_Q5_V1_8822C 25
+#define BIT_MASK_QUEUEMACID_Q5_V1_8822C 0x7f
+#define BIT_QUEUEMACID_Q5_V1_8822C(x)                                          \
+	(((x) & BIT_MASK_QUEUEMACID_Q5_V1_8822C)                               \
+	 << BIT_SHIFT_QUEUEMACID_Q5_V1_8822C)
+#define BITS_QUEUEMACID_Q5_V1_8822C                                            \
+	(BIT_MASK_QUEUEMACID_Q5_V1_8822C << BIT_SHIFT_QUEUEMACID_Q5_V1_8822C)
+#define BIT_CLEAR_QUEUEMACID_Q5_V1_8822C(x)                                    \
+	((x) & (~BITS_QUEUEMACID_Q5_V1_8822C))
+#define BIT_GET_QUEUEMACID_Q5_V1_8822C(x)                                      \
+	(((x) >> BIT_SHIFT_QUEUEMACID_Q5_V1_8822C) &                           \
+	 BIT_MASK_QUEUEMACID_Q5_V1_8822C)
+#define BIT_SET_QUEUEMACID_Q5_V1_8822C(x, v)                                   \
+	(BIT_CLEAR_QUEUEMACID_Q5_V1_8822C(x) | BIT_QUEUEMACID_Q5_V1_8822C(v))
+
+#define BIT_SHIFT_QUEUEAC_Q5_V1_8822C 23
+#define BIT_MASK_QUEUEAC_Q5_V1_8822C 0x3
+#define BIT_QUEUEAC_Q5_V1_8822C(x)                                             \
+	(((x) & BIT_MASK_QUEUEAC_Q5_V1_8822C) << BIT_SHIFT_QUEUEAC_Q5_V1_8822C)
+#define BITS_QUEUEAC_Q5_V1_8822C                                               \
+	(BIT_MASK_QUEUEAC_Q5_V1_8822C << BIT_SHIFT_QUEUEAC_Q5_V1_8822C)
+#define BIT_CLEAR_QUEUEAC_Q5_V1_8822C(x) ((x) & (~BITS_QUEUEAC_Q5_V1_8822C))
+#define BIT_GET_QUEUEAC_Q5_V1_8822C(x)                                         \
+	(((x) >> BIT_SHIFT_QUEUEAC_Q5_V1_8822C) & BIT_MASK_QUEUEAC_Q5_V1_8822C)
+#define BIT_SET_QUEUEAC_Q5_V1_8822C(x, v)                                      \
+	(BIT_CLEAR_QUEUEAC_Q5_V1_8822C(x) | BIT_QUEUEAC_Q5_V1_8822C(v))
+
+#define BIT_TIDEMPTY_Q5_V1_8822C BIT(22)
+
+#define BIT_SHIFT_TAIL_PKT_Q5_V2_8822C 11
+#define BIT_MASK_TAIL_PKT_Q5_V2_8822C 0x7ff
+#define BIT_TAIL_PKT_Q5_V2_8822C(x)                                            \
+	(((x) & BIT_MASK_TAIL_PKT_Q5_V2_8822C)                                 \
+	 << BIT_SHIFT_TAIL_PKT_Q5_V2_8822C)
+#define BITS_TAIL_PKT_Q5_V2_8822C                                              \
+	(BIT_MASK_TAIL_PKT_Q5_V2_8822C << BIT_SHIFT_TAIL_PKT_Q5_V2_8822C)
+#define BIT_CLEAR_TAIL_PKT_Q5_V2_8822C(x) ((x) & (~BITS_TAIL_PKT_Q5_V2_8822C))
+#define BIT_GET_TAIL_PKT_Q5_V2_8822C(x)                                        \
+	(((x) >> BIT_SHIFT_TAIL_PKT_Q5_V2_8822C) &                             \
+	 BIT_MASK_TAIL_PKT_Q5_V2_8822C)
+#define BIT_SET_TAIL_PKT_Q5_V2_8822C(x, v)                                     \
+	(BIT_CLEAR_TAIL_PKT_Q5_V2_8822C(x) | BIT_TAIL_PKT_Q5_V2_8822C(v))
+
+#define BIT_SHIFT_HEAD_PKT_Q5_V1_8822C 0
+#define BIT_MASK_HEAD_PKT_Q5_V1_8822C 0x7ff
+#define BIT_HEAD_PKT_Q5_V1_8822C(x)                                            \
+	(((x) & BIT_MASK_HEAD_PKT_Q5_V1_8822C)                                 \
+	 << BIT_SHIFT_HEAD_PKT_Q5_V1_8822C)
+#define BITS_HEAD_PKT_Q5_V1_8822C                                              \
+	(BIT_MASK_HEAD_PKT_Q5_V1_8822C << BIT_SHIFT_HEAD_PKT_Q5_V1_8822C)
+#define BIT_CLEAR_HEAD_PKT_Q5_V1_8822C(x) ((x) & (~BITS_HEAD_PKT_Q5_V1_8822C))
+#define BIT_GET_HEAD_PKT_Q5_V1_8822C(x)                                        \
+	(((x) >> BIT_SHIFT_HEAD_PKT_Q5_V1_8822C) &                             \
+	 BIT_MASK_HEAD_PKT_Q5_V1_8822C)
+#define BIT_SET_HEAD_PKT_Q5_V1_8822C(x, v)                                     \
+	(BIT_CLEAR_HEAD_PKT_Q5_V1_8822C(x) | BIT_HEAD_PKT_Q5_V1_8822C(v))
+
+/* 2 REG_Q6_INFO_8822C */
+
+#define BIT_SHIFT_QUEUEMACID_Q6_V1_8822C 25
+#define BIT_MASK_QUEUEMACID_Q6_V1_8822C 0x7f
+#define BIT_QUEUEMACID_Q6_V1_8822C(x)                                          \
+	(((x) & BIT_MASK_QUEUEMACID_Q6_V1_8822C)                               \
+	 << BIT_SHIFT_QUEUEMACID_Q6_V1_8822C)
+#define BITS_QUEUEMACID_Q6_V1_8822C                                            \
+	(BIT_MASK_QUEUEMACID_Q6_V1_8822C << BIT_SHIFT_QUEUEMACID_Q6_V1_8822C)
+#define BIT_CLEAR_QUEUEMACID_Q6_V1_8822C(x)                                    \
+	((x) & (~BITS_QUEUEMACID_Q6_V1_8822C))
+#define BIT_GET_QUEUEMACID_Q6_V1_8822C(x)                                      \
+	(((x) >> BIT_SHIFT_QUEUEMACID_Q6_V1_8822C) &                           \
+	 BIT_MASK_QUEUEMACID_Q6_V1_8822C)
+#define BIT_SET_QUEUEMACID_Q6_V1_8822C(x, v)                                   \
+	(BIT_CLEAR_QUEUEMACID_Q6_V1_8822C(x) | BIT_QUEUEMACID_Q6_V1_8822C(v))
+
+#define BIT_SHIFT_QUEUEAC_Q6_V1_8822C 23
+#define BIT_MASK_QUEUEAC_Q6_V1_8822C 0x3
+#define BIT_QUEUEAC_Q6_V1_8822C(x)                                             \
+	(((x) & BIT_MASK_QUEUEAC_Q6_V1_8822C) << BIT_SHIFT_QUEUEAC_Q6_V1_8822C)
+#define BITS_QUEUEAC_Q6_V1_8822C                                               \
+	(BIT_MASK_QUEUEAC_Q6_V1_8822C << BIT_SHIFT_QUEUEAC_Q6_V1_8822C)
+#define BIT_CLEAR_QUEUEAC_Q6_V1_8822C(x) ((x) & (~BITS_QUEUEAC_Q6_V1_8822C))
+#define BIT_GET_QUEUEAC_Q6_V1_8822C(x)                                         \
+	(((x) >> BIT_SHIFT_QUEUEAC_Q6_V1_8822C) & BIT_MASK_QUEUEAC_Q6_V1_8822C)
+#define BIT_SET_QUEUEAC_Q6_V1_8822C(x, v)                                      \
+	(BIT_CLEAR_QUEUEAC_Q6_V1_8822C(x) | BIT_QUEUEAC_Q6_V1_8822C(v))
+
+#define BIT_TIDEMPTY_Q6_V1_8822C BIT(22)
+
+#define BIT_SHIFT_TAIL_PKT_Q6_V2_8822C 11
+#define BIT_MASK_TAIL_PKT_Q6_V2_8822C 0x7ff
+#define BIT_TAIL_PKT_Q6_V2_8822C(x)                                            \
+	(((x) & BIT_MASK_TAIL_PKT_Q6_V2_8822C)                                 \
+	 << BIT_SHIFT_TAIL_PKT_Q6_V2_8822C)
+#define BITS_TAIL_PKT_Q6_V2_8822C                                              \
+	(BIT_MASK_TAIL_PKT_Q6_V2_8822C << BIT_SHIFT_TAIL_PKT_Q6_V2_8822C)
+#define BIT_CLEAR_TAIL_PKT_Q6_V2_8822C(x) ((x) & (~BITS_TAIL_PKT_Q6_V2_8822C))
+#define BIT_GET_TAIL_PKT_Q6_V2_8822C(x)                                        \
+	(((x) >> BIT_SHIFT_TAIL_PKT_Q6_V2_8822C) &                             \
+	 BIT_MASK_TAIL_PKT_Q6_V2_8822C)
+#define BIT_SET_TAIL_PKT_Q6_V2_8822C(x, v)                                     \
+	(BIT_CLEAR_TAIL_PKT_Q6_V2_8822C(x) | BIT_TAIL_PKT_Q6_V2_8822C(v))
+
+#define BIT_SHIFT_HEAD_PKT_Q6_V1_8822C 0
+#define BIT_MASK_HEAD_PKT_Q6_V1_8822C 0x7ff
+#define BIT_HEAD_PKT_Q6_V1_8822C(x)                                            \
+	(((x) & BIT_MASK_HEAD_PKT_Q6_V1_8822C)                                 \
+	 << BIT_SHIFT_HEAD_PKT_Q6_V1_8822C)
+#define BITS_HEAD_PKT_Q6_V1_8822C                                              \
+	(BIT_MASK_HEAD_PKT_Q6_V1_8822C << BIT_SHIFT_HEAD_PKT_Q6_V1_8822C)
+#define BIT_CLEAR_HEAD_PKT_Q6_V1_8822C(x) ((x) & (~BITS_HEAD_PKT_Q6_V1_8822C))
+#define BIT_GET_HEAD_PKT_Q6_V1_8822C(x)                                        \
+	(((x) >> BIT_SHIFT_HEAD_PKT_Q6_V1_8822C) &                             \
+	 BIT_MASK_HEAD_PKT_Q6_V1_8822C)
+#define BIT_SET_HEAD_PKT_Q6_V1_8822C(x, v)                                     \
+	(BIT_CLEAR_HEAD_PKT_Q6_V1_8822C(x) | BIT_HEAD_PKT_Q6_V1_8822C(v))
+
+/* 2 REG_Q7_INFO_8822C */
+
+#define BIT_SHIFT_QUEUEMACID_Q7_V1_8822C 25
+#define BIT_MASK_QUEUEMACID_Q7_V1_8822C 0x7f
+#define BIT_QUEUEMACID_Q7_V1_8822C(x)                                          \
+	(((x) & BIT_MASK_QUEUEMACID_Q7_V1_8822C)                               \
+	 << BIT_SHIFT_QUEUEMACID_Q7_V1_8822C)
+#define BITS_QUEUEMACID_Q7_V1_8822C                                            \
+	(BIT_MASK_QUEUEMACID_Q7_V1_8822C << BIT_SHIFT_QUEUEMACID_Q7_V1_8822C)
+#define BIT_CLEAR_QUEUEMACID_Q7_V1_8822C(x)                                    \
+	((x) & (~BITS_QUEUEMACID_Q7_V1_8822C))
+#define BIT_GET_QUEUEMACID_Q7_V1_8822C(x)                                      \
+	(((x) >> BIT_SHIFT_QUEUEMACID_Q7_V1_8822C) &                           \
+	 BIT_MASK_QUEUEMACID_Q7_V1_8822C)
+#define BIT_SET_QUEUEMACID_Q7_V1_8822C(x, v)                                   \
+	(BIT_CLEAR_QUEUEMACID_Q7_V1_8822C(x) | BIT_QUEUEMACID_Q7_V1_8822C(v))
+
+#define BIT_SHIFT_QUEUEAC_Q7_V1_8822C 23
+#define BIT_MASK_QUEUEAC_Q7_V1_8822C 0x3
+#define BIT_QUEUEAC_Q7_V1_8822C(x)                                             \
+	(((x) & BIT_MASK_QUEUEAC_Q7_V1_8822C) << BIT_SHIFT_QUEUEAC_Q7_V1_8822C)
+#define BITS_QUEUEAC_Q7_V1_8822C                                               \
+	(BIT_MASK_QUEUEAC_Q7_V1_8822C << BIT_SHIFT_QUEUEAC_Q7_V1_8822C)
+#define BIT_CLEAR_QUEUEAC_Q7_V1_8822C(x) ((x) & (~BITS_QUEUEAC_Q7_V1_8822C))
+#define BIT_GET_QUEUEAC_Q7_V1_8822C(x)                                         \
+	(((x) >> BIT_SHIFT_QUEUEAC_Q7_V1_8822C) & BIT_MASK_QUEUEAC_Q7_V1_8822C)
+#define BIT_SET_QUEUEAC_Q7_V1_8822C(x, v)                                      \
+	(BIT_CLEAR_QUEUEAC_Q7_V1_8822C(x) | BIT_QUEUEAC_Q7_V1_8822C(v))
+
+#define BIT_TIDEMPTY_Q7_V1_8822C BIT(22)
+
+#define BIT_SHIFT_TAIL_PKT_Q7_V2_8822C 11
+#define BIT_MASK_TAIL_PKT_Q7_V2_8822C 0x7ff
+#define BIT_TAIL_PKT_Q7_V2_8822C(x)                                            \
+	(((x) & BIT_MASK_TAIL_PKT_Q7_V2_8822C)                                 \
+	 << BIT_SHIFT_TAIL_PKT_Q7_V2_8822C)
+#define BITS_TAIL_PKT_Q7_V2_8822C                                              \
+	(BIT_MASK_TAIL_PKT_Q7_V2_8822C << BIT_SHIFT_TAIL_PKT_Q7_V2_8822C)
+#define BIT_CLEAR_TAIL_PKT_Q7_V2_8822C(x) ((x) & (~BITS_TAIL_PKT_Q7_V2_8822C))
+#define BIT_GET_TAIL_PKT_Q7_V2_8822C(x)                                        \
+	(((x) >> BIT_SHIFT_TAIL_PKT_Q7_V2_8822C) &                             \
+	 BIT_MASK_TAIL_PKT_Q7_V2_8822C)
+#define BIT_SET_TAIL_PKT_Q7_V2_8822C(x, v)                                     \
+	(BIT_CLEAR_TAIL_PKT_Q7_V2_8822C(x) | BIT_TAIL_PKT_Q7_V2_8822C(v))
+
+#define BIT_SHIFT_HEAD_PKT_Q7_V1_8822C 0
+#define BIT_MASK_HEAD_PKT_Q7_V1_8822C 0x7ff
+#define BIT_HEAD_PKT_Q7_V1_8822C(x)                                            \
+	(((x) & BIT_MASK_HEAD_PKT_Q7_V1_8822C)                                 \
+	 << BIT_SHIFT_HEAD_PKT_Q7_V1_8822C)
+#define BITS_HEAD_PKT_Q7_V1_8822C                                              \
+	(BIT_MASK_HEAD_PKT_Q7_V1_8822C << BIT_SHIFT_HEAD_PKT_Q7_V1_8822C)
+#define BIT_CLEAR_HEAD_PKT_Q7_V1_8822C(x) ((x) & (~BITS_HEAD_PKT_Q7_V1_8822C))
+#define BIT_GET_HEAD_PKT_Q7_V1_8822C(x)                                        \
+	(((x) >> BIT_SHIFT_HEAD_PKT_Q7_V1_8822C) &                             \
+	 BIT_MASK_HEAD_PKT_Q7_V1_8822C)
+#define BIT_SET_HEAD_PKT_Q7_V1_8822C(x, v)                                     \
+	(BIT_CLEAR_HEAD_PKT_Q7_V1_8822C(x) | BIT_HEAD_PKT_Q7_V1_8822C(v))
+
+/* 2 REG_WMAC_LBK_BUF_HD_V1_8822C */
+
+#define BIT_SHIFT_WMAC_LBK_BUF_HEAD_V1_8822C 0
+#define BIT_MASK_WMAC_LBK_BUF_HEAD_V1_8822C 0xfff
+#define BIT_WMAC_LBK_BUF_HEAD_V1_8822C(x)                                      \
+	(((x) & BIT_MASK_WMAC_LBK_BUF_HEAD_V1_8822C)                           \
+	 << BIT_SHIFT_WMAC_LBK_BUF_HEAD_V1_8822C)
+#define BITS_WMAC_LBK_BUF_HEAD_V1_8822C                                        \
+	(BIT_MASK_WMAC_LBK_BUF_HEAD_V1_8822C                                   \
+	 << BIT_SHIFT_WMAC_LBK_BUF_HEAD_V1_8822C)
+#define BIT_CLEAR_WMAC_LBK_BUF_HEAD_V1_8822C(x)                                \
+	((x) & (~BITS_WMAC_LBK_BUF_HEAD_V1_8822C))
+#define BIT_GET_WMAC_LBK_BUF_HEAD_V1_8822C(x)                                  \
+	(((x) >> BIT_SHIFT_WMAC_LBK_BUF_HEAD_V1_8822C) &                       \
+	 BIT_MASK_WMAC_LBK_BUF_HEAD_V1_8822C)
+#define BIT_SET_WMAC_LBK_BUF_HEAD_V1_8822C(x, v)                               \
+	(BIT_CLEAR_WMAC_LBK_BUF_HEAD_V1_8822C(x) |                             \
+	 BIT_WMAC_LBK_BUF_HEAD_V1_8822C(v))
+
+/* 2 REG_MGQ_BDNY_V1_8822C */
+
+#define BIT_SHIFT_MGQ_PGBNDY_V1_8822C 0
+#define BIT_MASK_MGQ_PGBNDY_V1_8822C 0xfff
+#define BIT_MGQ_PGBNDY_V1_8822C(x)                                             \
+	(((x) & BIT_MASK_MGQ_PGBNDY_V1_8822C) << BIT_SHIFT_MGQ_PGBNDY_V1_8822C)
+#define BITS_MGQ_PGBNDY_V1_8822C                                               \
+	(BIT_MASK_MGQ_PGBNDY_V1_8822C << BIT_SHIFT_MGQ_PGBNDY_V1_8822C)
+#define BIT_CLEAR_MGQ_PGBNDY_V1_8822C(x) ((x) & (~BITS_MGQ_PGBNDY_V1_8822C))
+#define BIT_GET_MGQ_PGBNDY_V1_8822C(x)                                         \
+	(((x) >> BIT_SHIFT_MGQ_PGBNDY_V1_8822C) & BIT_MASK_MGQ_PGBNDY_V1_8822C)
+#define BIT_SET_MGQ_PGBNDY_V1_8822C(x, v)                                      \
+	(BIT_CLEAR_MGQ_PGBNDY_V1_8822C(x) | BIT_MGQ_PGBNDY_V1_8822C(v))
+
+/* 2 REG_TXRPT_CTRL_8822C */
+
+#define BIT_SHIFT_TRXRPT_TIMER_TH_8822C 24
+#define BIT_MASK_TRXRPT_TIMER_TH_8822C 0xff
+#define BIT_TRXRPT_TIMER_TH_8822C(x)                                           \
+	(((x) & BIT_MASK_TRXRPT_TIMER_TH_8822C)                                \
+	 << BIT_SHIFT_TRXRPT_TIMER_TH_8822C)
+#define BITS_TRXRPT_TIMER_TH_8822C                                             \
+	(BIT_MASK_TRXRPT_TIMER_TH_8822C << BIT_SHIFT_TRXRPT_TIMER_TH_8822C)
+#define BIT_CLEAR_TRXRPT_TIMER_TH_8822C(x) ((x) & (~BITS_TRXRPT_TIMER_TH_8822C))
+#define BIT_GET_TRXRPT_TIMER_TH_8822C(x)                                       \
+	(((x) >> BIT_SHIFT_TRXRPT_TIMER_TH_8822C) &                            \
+	 BIT_MASK_TRXRPT_TIMER_TH_8822C)
+#define BIT_SET_TRXRPT_TIMER_TH_8822C(x, v)                                    \
+	(BIT_CLEAR_TRXRPT_TIMER_TH_8822C(x) | BIT_TRXRPT_TIMER_TH_8822C(v))
+
+#define BIT_SHIFT_TRXRPT_LEN_TH_8822C 16
+#define BIT_MASK_TRXRPT_LEN_TH_8822C 0xff
+#define BIT_TRXRPT_LEN_TH_8822C(x)                                             \
+	(((x) & BIT_MASK_TRXRPT_LEN_TH_8822C) << BIT_SHIFT_TRXRPT_LEN_TH_8822C)
+#define BITS_TRXRPT_LEN_TH_8822C                                               \
+	(BIT_MASK_TRXRPT_LEN_TH_8822C << BIT_SHIFT_TRXRPT_LEN_TH_8822C)
+#define BIT_CLEAR_TRXRPT_LEN_TH_8822C(x) ((x) & (~BITS_TRXRPT_LEN_TH_8822C))
+#define BIT_GET_TRXRPT_LEN_TH_8822C(x)                                         \
+	(((x) >> BIT_SHIFT_TRXRPT_LEN_TH_8822C) & BIT_MASK_TRXRPT_LEN_TH_8822C)
+#define BIT_SET_TRXRPT_LEN_TH_8822C(x, v)                                      \
+	(BIT_CLEAR_TRXRPT_LEN_TH_8822C(x) | BIT_TRXRPT_LEN_TH_8822C(v))
+
+#define BIT_SHIFT_TRXRPT_READ_PTR_8822C 8
+#define BIT_MASK_TRXRPT_READ_PTR_8822C 0xff
+#define BIT_TRXRPT_READ_PTR_8822C(x)                                           \
+	(((x) & BIT_MASK_TRXRPT_READ_PTR_8822C)                                \
+	 << BIT_SHIFT_TRXRPT_READ_PTR_8822C)
+#define BITS_TRXRPT_READ_PTR_8822C                                             \
+	(BIT_MASK_TRXRPT_READ_PTR_8822C << BIT_SHIFT_TRXRPT_READ_PTR_8822C)
+#define BIT_CLEAR_TRXRPT_READ_PTR_8822C(x) ((x) & (~BITS_TRXRPT_READ_PTR_8822C))
+#define BIT_GET_TRXRPT_READ_PTR_8822C(x)                                       \
+	(((x) >> BIT_SHIFT_TRXRPT_READ_PTR_8822C) &                            \
+	 BIT_MASK_TRXRPT_READ_PTR_8822C)
+#define BIT_SET_TRXRPT_READ_PTR_8822C(x, v)                                    \
+	(BIT_CLEAR_TRXRPT_READ_PTR_8822C(x) | BIT_TRXRPT_READ_PTR_8822C(v))
+
+#define BIT_SHIFT_TRXRPT_WRITE_PTR_8822C 0
+#define BIT_MASK_TRXRPT_WRITE_PTR_8822C 0xff
+#define BIT_TRXRPT_WRITE_PTR_8822C(x)                                          \
+	(((x) & BIT_MASK_TRXRPT_WRITE_PTR_8822C)                               \
+	 << BIT_SHIFT_TRXRPT_WRITE_PTR_8822C)
+#define BITS_TRXRPT_WRITE_PTR_8822C                                            \
+	(BIT_MASK_TRXRPT_WRITE_PTR_8822C << BIT_SHIFT_TRXRPT_WRITE_PTR_8822C)
+#define BIT_CLEAR_TRXRPT_WRITE_PTR_8822C(x)                                    \
+	((x) & (~BITS_TRXRPT_WRITE_PTR_8822C))
+#define BIT_GET_TRXRPT_WRITE_PTR_8822C(x)                                      \
+	(((x) >> BIT_SHIFT_TRXRPT_WRITE_PTR_8822C) &                           \
+	 BIT_MASK_TRXRPT_WRITE_PTR_8822C)
+#define BIT_SET_TRXRPT_WRITE_PTR_8822C(x, v)                                   \
+	(BIT_CLEAR_TRXRPT_WRITE_PTR_8822C(x) | BIT_TRXRPT_WRITE_PTR_8822C(v))
+
+/* 2 REG_INIRTS_RATE_SEL_8822C */
+#define BIT_LEAG_RTS_BW_DUP_8822C BIT(5)
+
+/* 2 REG_BASIC_CFEND_RATE_8822C */
+
+#define BIT_SHIFT_BASIC_CFEND_RATE_8822C 0
+#define BIT_MASK_BASIC_CFEND_RATE_8822C 0x1f
+#define BIT_BASIC_CFEND_RATE_8822C(x)                                          \
+	(((x) & BIT_MASK_BASIC_CFEND_RATE_8822C)                               \
+	 << BIT_SHIFT_BASIC_CFEND_RATE_8822C)
+#define BITS_BASIC_CFEND_RATE_8822C                                            \
+	(BIT_MASK_BASIC_CFEND_RATE_8822C << BIT_SHIFT_BASIC_CFEND_RATE_8822C)
+#define BIT_CLEAR_BASIC_CFEND_RATE_8822C(x)                                    \
+	((x) & (~BITS_BASIC_CFEND_RATE_8822C))
+#define BIT_GET_BASIC_CFEND_RATE_8822C(x)                                      \
+	(((x) >> BIT_SHIFT_BASIC_CFEND_RATE_8822C) &                           \
+	 BIT_MASK_BASIC_CFEND_RATE_8822C)
+#define BIT_SET_BASIC_CFEND_RATE_8822C(x, v)                                   \
+	(BIT_CLEAR_BASIC_CFEND_RATE_8822C(x) | BIT_BASIC_CFEND_RATE_8822C(v))
+
+/* 2 REG_STBC_CFEND_RATE_8822C */
+
+#define BIT_SHIFT_STBC_CFEND_RATE_8822C 0
+#define BIT_MASK_STBC_CFEND_RATE_8822C 0x1f
+#define BIT_STBC_CFEND_RATE_8822C(x)                                           \
+	(((x) & BIT_MASK_STBC_CFEND_RATE_8822C)                                \
+	 << BIT_SHIFT_STBC_CFEND_RATE_8822C)
+#define BITS_STBC_CFEND_RATE_8822C                                             \
+	(BIT_MASK_STBC_CFEND_RATE_8822C << BIT_SHIFT_STBC_CFEND_RATE_8822C)
+#define BIT_CLEAR_STBC_CFEND_RATE_8822C(x) ((x) & (~BITS_STBC_CFEND_RATE_8822C))
+#define BIT_GET_STBC_CFEND_RATE_8822C(x)                                       \
+	(((x) >> BIT_SHIFT_STBC_CFEND_RATE_8822C) &                            \
+	 BIT_MASK_STBC_CFEND_RATE_8822C)
+#define BIT_SET_STBC_CFEND_RATE_8822C(x, v)                                    \
+	(BIT_CLEAR_STBC_CFEND_RATE_8822C(x) | BIT_STBC_CFEND_RATE_8822C(v))
+
+/* 2 REG_DATA_SC_8822C */
+
+#define BIT_SHIFT_TXSC_40M_8822C 4
+#define BIT_MASK_TXSC_40M_8822C 0xf
+#define BIT_TXSC_40M_8822C(x)                                                  \
+	(((x) & BIT_MASK_TXSC_40M_8822C) << BIT_SHIFT_TXSC_40M_8822C)
+#define BITS_TXSC_40M_8822C                                                    \
+	(BIT_MASK_TXSC_40M_8822C << BIT_SHIFT_TXSC_40M_8822C)
+#define BIT_CLEAR_TXSC_40M_8822C(x) ((x) & (~BITS_TXSC_40M_8822C))
+#define BIT_GET_TXSC_40M_8822C(x)                                              \
+	(((x) >> BIT_SHIFT_TXSC_40M_8822C) & BIT_MASK_TXSC_40M_8822C)
+#define BIT_SET_TXSC_40M_8822C(x, v)                                           \
+	(BIT_CLEAR_TXSC_40M_8822C(x) | BIT_TXSC_40M_8822C(v))
+
+#define BIT_SHIFT_TXSC_20M_8822C 0
+#define BIT_MASK_TXSC_20M_8822C 0xf
+#define BIT_TXSC_20M_8822C(x)                                                  \
+	(((x) & BIT_MASK_TXSC_20M_8822C) << BIT_SHIFT_TXSC_20M_8822C)
+#define BITS_TXSC_20M_8822C                                                    \
+	(BIT_MASK_TXSC_20M_8822C << BIT_SHIFT_TXSC_20M_8822C)
+#define BIT_CLEAR_TXSC_20M_8822C(x) ((x) & (~BITS_TXSC_20M_8822C))
+#define BIT_GET_TXSC_20M_8822C(x)                                              \
+	(((x) >> BIT_SHIFT_TXSC_20M_8822C) & BIT_MASK_TXSC_20M_8822C)
+#define BIT_SET_TXSC_20M_8822C(x, v)                                           \
+	(BIT_CLEAR_TXSC_20M_8822C(x) | BIT_TXSC_20M_8822C(v))
+
+/* 2 REG_MACID_SLEEP3_8822C */
+
+#define BIT_SHIFT_MACID127_96_PKTSLEEP_8822C 0
+#define BIT_MASK_MACID127_96_PKTSLEEP_8822C 0xffffffffL
+#define BIT_MACID127_96_PKTSLEEP_8822C(x)                                      \
+	(((x) & BIT_MASK_MACID127_96_PKTSLEEP_8822C)                           \
+	 << BIT_SHIFT_MACID127_96_PKTSLEEP_8822C)
+#define BITS_MACID127_96_PKTSLEEP_8822C                                        \
+	(BIT_MASK_MACID127_96_PKTSLEEP_8822C                                   \
+	 << BIT_SHIFT_MACID127_96_PKTSLEEP_8822C)
+#define BIT_CLEAR_MACID127_96_PKTSLEEP_8822C(x)                                \
+	((x) & (~BITS_MACID127_96_PKTSLEEP_8822C))
+#define BIT_GET_MACID127_96_PKTSLEEP_8822C(x)                                  \
+	(((x) >> BIT_SHIFT_MACID127_96_PKTSLEEP_8822C) &                       \
+	 BIT_MASK_MACID127_96_PKTSLEEP_8822C)
+#define BIT_SET_MACID127_96_PKTSLEEP_8822C(x, v)                               \
+	(BIT_CLEAR_MACID127_96_PKTSLEEP_8822C(x) |                             \
+	 BIT_MACID127_96_PKTSLEEP_8822C(v))
+
+/* 2 REG_MACID_SLEEP1_8822C */
+
+#define BIT_SHIFT_MACID63_32_PKTSLEEP_8822C 0
+#define BIT_MASK_MACID63_32_PKTSLEEP_8822C 0xffffffffL
+#define BIT_MACID63_32_PKTSLEEP_8822C(x)                                       \
+	(((x) & BIT_MASK_MACID63_32_PKTSLEEP_8822C)                            \
+	 << BIT_SHIFT_MACID63_32_PKTSLEEP_8822C)
+#define BITS_MACID63_32_PKTSLEEP_8822C                                         \
+	(BIT_MASK_MACID63_32_PKTSLEEP_8822C                                    \
+	 << BIT_SHIFT_MACID63_32_PKTSLEEP_8822C)
+#define BIT_CLEAR_MACID63_32_PKTSLEEP_8822C(x)                                 \
+	((x) & (~BITS_MACID63_32_PKTSLEEP_8822C))
+#define BIT_GET_MACID63_32_PKTSLEEP_8822C(x)                                   \
+	(((x) >> BIT_SHIFT_MACID63_32_PKTSLEEP_8822C) &                        \
+	 BIT_MASK_MACID63_32_PKTSLEEP_8822C)
+#define BIT_SET_MACID63_32_PKTSLEEP_8822C(x, v)                                \
+	(BIT_CLEAR_MACID63_32_PKTSLEEP_8822C(x) |                              \
+	 BIT_MACID63_32_PKTSLEEP_8822C(v))
+
+/* 2 REG_ARFR2_V1_8822C */
+
+#define BIT_SHIFT_ARFRL2_8822C 0
+#define BIT_MASK_ARFRL2_8822C 0xffffffffL
+#define BIT_ARFRL2_8822C(x)                                                    \
+	(((x) & BIT_MASK_ARFRL2_8822C) << BIT_SHIFT_ARFRL2_8822C)
+#define BITS_ARFRL2_8822C (BIT_MASK_ARFRL2_8822C << BIT_SHIFT_ARFRL2_8822C)
+#define BIT_CLEAR_ARFRL2_8822C(x) ((x) & (~BITS_ARFRL2_8822C))
+#define BIT_GET_ARFRL2_8822C(x)                                                \
+	(((x) >> BIT_SHIFT_ARFRL2_8822C) & BIT_MASK_ARFRL2_8822C)
+#define BIT_SET_ARFRL2_8822C(x, v)                                             \
+	(BIT_CLEAR_ARFRL2_8822C(x) | BIT_ARFRL2_8822C(v))
+
+/* 2 REG_ARFRH2_V1_8822C */
+
+#define BIT_SHIFT_ARFRH2_8822C 0
+#define BIT_MASK_ARFRH2_8822C 0xffffffffL
+#define BIT_ARFRH2_8822C(x)                                                    \
+	(((x) & BIT_MASK_ARFRH2_8822C) << BIT_SHIFT_ARFRH2_8822C)
+#define BITS_ARFRH2_8822C (BIT_MASK_ARFRH2_8822C << BIT_SHIFT_ARFRH2_8822C)
+#define BIT_CLEAR_ARFRH2_8822C(x) ((x) & (~BITS_ARFRH2_8822C))
+#define BIT_GET_ARFRH2_8822C(x)                                                \
+	(((x) >> BIT_SHIFT_ARFRH2_8822C) & BIT_MASK_ARFRH2_8822C)
+#define BIT_SET_ARFRH2_8822C(x, v)                                             \
+	(BIT_CLEAR_ARFRH2_8822C(x) | BIT_ARFRH2_8822C(v))
+
+/* 2 REG_ARFR3_V1_8822C */
+
+#define BIT_SHIFT_ARFRL3_8822C 0
+#define BIT_MASK_ARFRL3_8822C 0xffffffffL
+#define BIT_ARFRL3_8822C(x)                                                    \
+	(((x) & BIT_MASK_ARFRL3_8822C) << BIT_SHIFT_ARFRL3_8822C)
+#define BITS_ARFRL3_8822C (BIT_MASK_ARFRL3_8822C << BIT_SHIFT_ARFRL3_8822C)
+#define BIT_CLEAR_ARFRL3_8822C(x) ((x) & (~BITS_ARFRL3_8822C))
+#define BIT_GET_ARFRL3_8822C(x)                                                \
+	(((x) >> BIT_SHIFT_ARFRL3_8822C) & BIT_MASK_ARFRL3_8822C)
+#define BIT_SET_ARFRL3_8822C(x, v)                                             \
+	(BIT_CLEAR_ARFRL3_8822C(x) | BIT_ARFRL3_8822C(v))
+
+/* 2 REG_ARFRH3_V1_8822C */
+
+#define BIT_SHIFT_ARFRH3_8822C 0
+#define BIT_MASK_ARFRH3_8822C 0xffffffffL
+#define BIT_ARFRH3_8822C(x)                                                    \
+	(((x) & BIT_MASK_ARFRH3_8822C) << BIT_SHIFT_ARFRH3_8822C)
+#define BITS_ARFRH3_8822C (BIT_MASK_ARFRH3_8822C << BIT_SHIFT_ARFRH3_8822C)
+#define BIT_CLEAR_ARFRH3_8822C(x) ((x) & (~BITS_ARFRH3_8822C))
+#define BIT_GET_ARFRH3_8822C(x)                                                \
+	(((x) >> BIT_SHIFT_ARFRH3_8822C) & BIT_MASK_ARFRH3_8822C)
+#define BIT_SET_ARFRH3_8822C(x, v)                                             \
+	(BIT_CLEAR_ARFRH3_8822C(x) | BIT_ARFRH3_8822C(v))
+
+/* 2 REG_ARFR4_8822C */
+
+#define BIT_SHIFT_ARFRL4_8822C 0
+#define BIT_MASK_ARFRL4_8822C 0xffffffffL
+#define BIT_ARFRL4_8822C(x)                                                    \
+	(((x) & BIT_MASK_ARFRL4_8822C) << BIT_SHIFT_ARFRL4_8822C)
+#define BITS_ARFRL4_8822C (BIT_MASK_ARFRL4_8822C << BIT_SHIFT_ARFRL4_8822C)
+#define BIT_CLEAR_ARFRL4_8822C(x) ((x) & (~BITS_ARFRL4_8822C))
+#define BIT_GET_ARFRL4_8822C(x)                                                \
+	(((x) >> BIT_SHIFT_ARFRL4_8822C) & BIT_MASK_ARFRL4_8822C)
+#define BIT_SET_ARFRL4_8822C(x, v)                                             \
+	(BIT_CLEAR_ARFRL4_8822C(x) | BIT_ARFRL4_8822C(v))
+
+/* 2 REG_ARFRH4_8822C */
+
+#define BIT_SHIFT_ARFRH4_8822C 0
+#define BIT_MASK_ARFRH4_8822C 0xffffffffL
+#define BIT_ARFRH4_8822C(x)                                                    \
+	(((x) & BIT_MASK_ARFRH4_8822C) << BIT_SHIFT_ARFRH4_8822C)
+#define BITS_ARFRH4_8822C (BIT_MASK_ARFRH4_8822C << BIT_SHIFT_ARFRH4_8822C)
+#define BIT_CLEAR_ARFRH4_8822C(x) ((x) & (~BITS_ARFRH4_8822C))
+#define BIT_GET_ARFRH4_8822C(x)                                                \
+	(((x) >> BIT_SHIFT_ARFRH4_8822C) & BIT_MASK_ARFRH4_8822C)
+#define BIT_SET_ARFRH4_8822C(x, v)                                             \
+	(BIT_CLEAR_ARFRH4_8822C(x) | BIT_ARFRH4_8822C(v))
+
+/* 2 REG_ARFR5_8822C */
+
+#define BIT_SHIFT_ARFRL5_8822C 0
+#define BIT_MASK_ARFRL5_8822C 0xffffffffL
+#define BIT_ARFRL5_8822C(x)                                                    \
+	(((x) & BIT_MASK_ARFRL5_8822C) << BIT_SHIFT_ARFRL5_8822C)
+#define BITS_ARFRL5_8822C (BIT_MASK_ARFRL5_8822C << BIT_SHIFT_ARFRL5_8822C)
+#define BIT_CLEAR_ARFRL5_8822C(x) ((x) & (~BITS_ARFRL5_8822C))
+#define BIT_GET_ARFRL5_8822C(x)                                                \
+	(((x) >> BIT_SHIFT_ARFRL5_8822C) & BIT_MASK_ARFRL5_8822C)
+#define BIT_SET_ARFRL5_8822C(x, v)                                             \
+	(BIT_CLEAR_ARFRL5_8822C(x) | BIT_ARFRL5_8822C(v))
+
+/* 2 REG_ARFRH5_8822C */
+
+#define BIT_SHIFT_ARFRH5_8822C 0
+#define BIT_MASK_ARFRH5_8822C 0xffffffffL
+#define BIT_ARFRH5_8822C(x)                                                    \
+	(((x) & BIT_MASK_ARFRH5_8822C) << BIT_SHIFT_ARFRH5_8822C)
+#define BITS_ARFRH5_8822C (BIT_MASK_ARFRH5_8822C << BIT_SHIFT_ARFRH5_8822C)
+#define BIT_CLEAR_ARFRH5_8822C(x) ((x) & (~BITS_ARFRH5_8822C))
+#define BIT_GET_ARFRH5_8822C(x)                                                \
+	(((x) >> BIT_SHIFT_ARFRH5_8822C) & BIT_MASK_ARFRH5_8822C)
+#define BIT_SET_ARFRH5_8822C(x, v)                                             \
+	(BIT_CLEAR_ARFRH5_8822C(x) | BIT_ARFRH5_8822C(v))
+
+/* 2 REG_TXRPT_START_OFFSET_8822C */
+
+#define BIT_SHIFT_MACID_MURATE_OFFSET_8822C 24
+#define BIT_MASK_MACID_MURATE_OFFSET_8822C 0xff
+#define BIT_MACID_MURATE_OFFSET_8822C(x)                                       \
+	(((x) & BIT_MASK_MACID_MURATE_OFFSET_8822C)                            \
+	 << BIT_SHIFT_MACID_MURATE_OFFSET_8822C)
+#define BITS_MACID_MURATE_OFFSET_8822C                                         \
+	(BIT_MASK_MACID_MURATE_OFFSET_8822C                                    \
+	 << BIT_SHIFT_MACID_MURATE_OFFSET_8822C)
+#define BIT_CLEAR_MACID_MURATE_OFFSET_8822C(x)                                 \
+	((x) & (~BITS_MACID_MURATE_OFFSET_8822C))
+#define BIT_GET_MACID_MURATE_OFFSET_8822C(x)                                   \
+	(((x) >> BIT_SHIFT_MACID_MURATE_OFFSET_8822C) &                        \
+	 BIT_MASK_MACID_MURATE_OFFSET_8822C)
+#define BIT_SET_MACID_MURATE_OFFSET_8822C(x, v)                                \
+	(BIT_CLEAR_MACID_MURATE_OFFSET_8822C(x) |                              \
+	 BIT_MACID_MURATE_OFFSET_8822C(v))
+
+#define BIT_SHIFT_TXRPT_MISS_COUNT_8822C 17
+#define BIT_MASK_TXRPT_MISS_COUNT_8822C 0x7
+#define BIT_TXRPT_MISS_COUNT_8822C(x)                                          \
+	(((x) & BIT_MASK_TXRPT_MISS_COUNT_8822C)                               \
+	 << BIT_SHIFT_TXRPT_MISS_COUNT_8822C)
+#define BITS_TXRPT_MISS_COUNT_8822C                                            \
+	(BIT_MASK_TXRPT_MISS_COUNT_8822C << BIT_SHIFT_TXRPT_MISS_COUNT_8822C)
+#define BIT_CLEAR_TXRPT_MISS_COUNT_8822C(x)                                    \
+	((x) & (~BITS_TXRPT_MISS_COUNT_8822C))
+#define BIT_GET_TXRPT_MISS_COUNT_8822C(x)                                      \
+	(((x) >> BIT_SHIFT_TXRPT_MISS_COUNT_8822C) &                           \
+	 BIT_MASK_TXRPT_MISS_COUNT_8822C)
+#define BIT_SET_TXRPT_MISS_COUNT_8822C(x, v)                                   \
+	(BIT_CLEAR_TXRPT_MISS_COUNT_8822C(x) | BIT_TXRPT_MISS_COUNT_8822C(v))
+
+#define BIT_RPTFIFO_SIZE_OPT_8822C BIT(16)
+
+#define BIT_SHIFT_MACID_CTRL_OFFSET_8822C 8
+#define BIT_MASK_MACID_CTRL_OFFSET_8822C 0xff
+#define BIT_MACID_CTRL_OFFSET_8822C(x)                                         \
+	(((x) & BIT_MASK_MACID_CTRL_OFFSET_8822C)                              \
+	 << BIT_SHIFT_MACID_CTRL_OFFSET_8822C)
+#define BITS_MACID_CTRL_OFFSET_8822C                                           \
+	(BIT_MASK_MACID_CTRL_OFFSET_8822C << BIT_SHIFT_MACID_CTRL_OFFSET_8822C)
+#define BIT_CLEAR_MACID_CTRL_OFFSET_8822C(x)                                   \
+	((x) & (~BITS_MACID_CTRL_OFFSET_8822C))
+#define BIT_GET_MACID_CTRL_OFFSET_8822C(x)                                     \
+	(((x) >> BIT_SHIFT_MACID_CTRL_OFFSET_8822C) &                          \
+	 BIT_MASK_MACID_CTRL_OFFSET_8822C)
+#define BIT_SET_MACID_CTRL_OFFSET_8822C(x, v)                                  \
+	(BIT_CLEAR_MACID_CTRL_OFFSET_8822C(x) | BIT_MACID_CTRL_OFFSET_8822C(v))
+
+#define BIT_SHIFT_AMPDU_TXRPT_OFFSET_8822C 0
+#define BIT_MASK_AMPDU_TXRPT_OFFSET_8822C 0xff
+#define BIT_AMPDU_TXRPT_OFFSET_8822C(x)                                        \
+	(((x) & BIT_MASK_AMPDU_TXRPT_OFFSET_8822C)                             \
+	 << BIT_SHIFT_AMPDU_TXRPT_OFFSET_8822C)
+#define BITS_AMPDU_TXRPT_OFFSET_8822C                                          \
+	(BIT_MASK_AMPDU_TXRPT_OFFSET_8822C                                     \
+	 << BIT_SHIFT_AMPDU_TXRPT_OFFSET_8822C)
+#define BIT_CLEAR_AMPDU_TXRPT_OFFSET_8822C(x)                                  \
+	((x) & (~BITS_AMPDU_TXRPT_OFFSET_8822C))
+#define BIT_GET_AMPDU_TXRPT_OFFSET_8822C(x)                                    \
+	(((x) >> BIT_SHIFT_AMPDU_TXRPT_OFFSET_8822C) &                         \
+	 BIT_MASK_AMPDU_TXRPT_OFFSET_8822C)
+#define BIT_SET_AMPDU_TXRPT_OFFSET_8822C(x, v)                                 \
+	(BIT_CLEAR_AMPDU_TXRPT_OFFSET_8822C(x) |                               \
+	 BIT_AMPDU_TXRPT_OFFSET_8822C(v))
+
+/* 2 REG_POWER_STAGE1_8822C */
+#define BIT_PTA_WL_PRI_MASK_CPU_MGQ_8822C BIT(31)
+#define BIT_PTA_WL_PRI_MASK_BCNQ_8822C BIT(30)
+#define BIT_PTA_WL_PRI_MASK_HIQ_8822C BIT(29)
+#define BIT_PTA_WL_PRI_MASK_MGQ_8822C BIT(28)
+#define BIT_PTA_WL_PRI_MASK_BK_8822C BIT(27)
+#define BIT_PTA_WL_PRI_MASK_BE_8822C BIT(26)
+#define BIT_PTA_WL_PRI_MASK_VI_8822C BIT(25)
+#define BIT_PTA_WL_PRI_MASK_VO_8822C BIT(24)
+
+#define BIT_SHIFT_POWER_STAGE1_8822C 0
+#define BIT_MASK_POWER_STAGE1_8822C 0xffffff
+#define BIT_POWER_STAGE1_8822C(x)                                              \
+	(((x) & BIT_MASK_POWER_STAGE1_8822C) << BIT_SHIFT_POWER_STAGE1_8822C)
+#define BITS_POWER_STAGE1_8822C                                                \
+	(BIT_MASK_POWER_STAGE1_8822C << BIT_SHIFT_POWER_STAGE1_8822C)
+#define BIT_CLEAR_POWER_STAGE1_8822C(x) ((x) & (~BITS_POWER_STAGE1_8822C))
+#define BIT_GET_POWER_STAGE1_8822C(x)                                          \
+	(((x) >> BIT_SHIFT_POWER_STAGE1_8822C) & BIT_MASK_POWER_STAGE1_8822C)
+#define BIT_SET_POWER_STAGE1_8822C(x, v)                                       \
+	(BIT_CLEAR_POWER_STAGE1_8822C(x) | BIT_POWER_STAGE1_8822C(v))
+
+/* 2 REG_POWER_STAGE2_8822C */
+#define BIT__R_CTRL_PKT_POW_ADJ_8822C BIT(24)
+
+#define BIT_SHIFT_POWER_STAGE2_8822C 0
+#define BIT_MASK_POWER_STAGE2_8822C 0xffffff
+#define BIT_POWER_STAGE2_8822C(x)                                              \
+	(((x) & BIT_MASK_POWER_STAGE2_8822C) << BIT_SHIFT_POWER_STAGE2_8822C)
+#define BITS_POWER_STAGE2_8822C                                                \
+	(BIT_MASK_POWER_STAGE2_8822C << BIT_SHIFT_POWER_STAGE2_8822C)
+#define BIT_CLEAR_POWER_STAGE2_8822C(x) ((x) & (~BITS_POWER_STAGE2_8822C))
+#define BIT_GET_POWER_STAGE2_8822C(x)                                          \
+	(((x) >> BIT_SHIFT_POWER_STAGE2_8822C) & BIT_MASK_POWER_STAGE2_8822C)
+#define BIT_SET_POWER_STAGE2_8822C(x, v)                                       \
+	(BIT_CLEAR_POWER_STAGE2_8822C(x) | BIT_POWER_STAGE2_8822C(v))
+
+/* 2 REG_SW_AMPDU_BURST_MODE_CTRL_8822C */
+
+#define BIT_SHIFT_PAD_NUM_THRES_8822C 24
+#define BIT_MASK_PAD_NUM_THRES_8822C 0x3f
+#define BIT_PAD_NUM_THRES_8822C(x)                                             \
+	(((x) & BIT_MASK_PAD_NUM_THRES_8822C) << BIT_SHIFT_PAD_NUM_THRES_8822C)
+#define BITS_PAD_NUM_THRES_8822C                                               \
+	(BIT_MASK_PAD_NUM_THRES_8822C << BIT_SHIFT_PAD_NUM_THRES_8822C)
+#define BIT_CLEAR_PAD_NUM_THRES_8822C(x) ((x) & (~BITS_PAD_NUM_THRES_8822C))
+#define BIT_GET_PAD_NUM_THRES_8822C(x)                                         \
+	(((x) >> BIT_SHIFT_PAD_NUM_THRES_8822C) & BIT_MASK_PAD_NUM_THRES_8822C)
+#define BIT_SET_PAD_NUM_THRES_8822C(x, v)                                      \
+	(BIT_CLEAR_PAD_NUM_THRES_8822C(x) | BIT_PAD_NUM_THRES_8822C(v))
+
+#define BIT_R_DMA_THIS_QUEUE_BK_8822C BIT(23)
+#define BIT_R_DMA_THIS_QUEUE_BE_8822C BIT(22)
+#define BIT_R_DMA_THIS_QUEUE_VI_8822C BIT(21)
+#define BIT_R_DMA_THIS_QUEUE_VO_8822C BIT(20)
+
+#define BIT_SHIFT_R_TOTAL_LEN_TH_8822C 8
+#define BIT_MASK_R_TOTAL_LEN_TH_8822C 0xfff
+#define BIT_R_TOTAL_LEN_TH_8822C(x)                                            \
+	(((x) & BIT_MASK_R_TOTAL_LEN_TH_8822C)                                 \
+	 << BIT_SHIFT_R_TOTAL_LEN_TH_8822C)
+#define BITS_R_TOTAL_LEN_TH_8822C                                              \
+	(BIT_MASK_R_TOTAL_LEN_TH_8822C << BIT_SHIFT_R_TOTAL_LEN_TH_8822C)
+#define BIT_CLEAR_R_TOTAL_LEN_TH_8822C(x) ((x) & (~BITS_R_TOTAL_LEN_TH_8822C))
+#define BIT_GET_R_TOTAL_LEN_TH_8822C(x)                                        \
+	(((x) >> BIT_SHIFT_R_TOTAL_LEN_TH_8822C) &                             \
+	 BIT_MASK_R_TOTAL_LEN_TH_8822C)
+#define BIT_SET_R_TOTAL_LEN_TH_8822C(x, v)                                     \
+	(BIT_CLEAR_R_TOTAL_LEN_TH_8822C(x) | BIT_R_TOTAL_LEN_TH_8822C(v))
+
+#define BIT_EN_NEW_EARLY_8822C BIT(7)
+#define BIT_PRE_TX_CMD_8822C BIT(6)
+
+#define BIT_SHIFT_NUM_SCL_EN_8822C 4
+#define BIT_MASK_NUM_SCL_EN_8822C 0x3
+#define BIT_NUM_SCL_EN_8822C(x)                                                \
+	(((x) & BIT_MASK_NUM_SCL_EN_8822C) << BIT_SHIFT_NUM_SCL_EN_8822C)
+#define BITS_NUM_SCL_EN_8822C                                                  \
+	(BIT_MASK_NUM_SCL_EN_8822C << BIT_SHIFT_NUM_SCL_EN_8822C)
+#define BIT_CLEAR_NUM_SCL_EN_8822C(x) ((x) & (~BITS_NUM_SCL_EN_8822C))
+#define BIT_GET_NUM_SCL_EN_8822C(x)                                            \
+	(((x) >> BIT_SHIFT_NUM_SCL_EN_8822C) & BIT_MASK_NUM_SCL_EN_8822C)
+#define BIT_SET_NUM_SCL_EN_8822C(x, v)                                         \
+	(BIT_CLEAR_NUM_SCL_EN_8822C(x) | BIT_NUM_SCL_EN_8822C(v))
+
+#define BIT_BK_EN_8822C BIT(3)
+#define BIT_BE_EN_8822C BIT(2)
+#define BIT_VI_EN_8822C BIT(1)
+#define BIT_VO_EN_8822C BIT(0)
+
+/* 2 REG_PKT_LIFE_TIME_8822C */
+
+#define BIT_SHIFT_PKT_LIFTIME_BEBK_8822C 16
+#define BIT_MASK_PKT_LIFTIME_BEBK_8822C 0xffff
+#define BIT_PKT_LIFTIME_BEBK_8822C(x)                                          \
+	(((x) & BIT_MASK_PKT_LIFTIME_BEBK_8822C)                               \
+	 << BIT_SHIFT_PKT_LIFTIME_BEBK_8822C)
+#define BITS_PKT_LIFTIME_BEBK_8822C                                            \
+	(BIT_MASK_PKT_LIFTIME_BEBK_8822C << BIT_SHIFT_PKT_LIFTIME_BEBK_8822C)
+#define BIT_CLEAR_PKT_LIFTIME_BEBK_8822C(x)                                    \
+	((x) & (~BITS_PKT_LIFTIME_BEBK_8822C))
+#define BIT_GET_PKT_LIFTIME_BEBK_8822C(x)                                      \
+	(((x) >> BIT_SHIFT_PKT_LIFTIME_BEBK_8822C) &                           \
+	 BIT_MASK_PKT_LIFTIME_BEBK_8822C)
+#define BIT_SET_PKT_LIFTIME_BEBK_8822C(x, v)                                   \
+	(BIT_CLEAR_PKT_LIFTIME_BEBK_8822C(x) | BIT_PKT_LIFTIME_BEBK_8822C(v))
+
+#define BIT_SHIFT_PKT_LIFTIME_VOVI_8822C 0
+#define BIT_MASK_PKT_LIFTIME_VOVI_8822C 0xffff
+#define BIT_PKT_LIFTIME_VOVI_8822C(x)                                          \
+	(((x) & BIT_MASK_PKT_LIFTIME_VOVI_8822C)                               \
+	 << BIT_SHIFT_PKT_LIFTIME_VOVI_8822C)
+#define BITS_PKT_LIFTIME_VOVI_8822C                                            \
+	(BIT_MASK_PKT_LIFTIME_VOVI_8822C << BIT_SHIFT_PKT_LIFTIME_VOVI_8822C)
+#define BIT_CLEAR_PKT_LIFTIME_VOVI_8822C(x)                                    \
+	((x) & (~BITS_PKT_LIFTIME_VOVI_8822C))
+#define BIT_GET_PKT_LIFTIME_VOVI_8822C(x)                                      \
+	(((x) >> BIT_SHIFT_PKT_LIFTIME_VOVI_8822C) &                           \
+	 BIT_MASK_PKT_LIFTIME_VOVI_8822C)
+#define BIT_SET_PKT_LIFTIME_VOVI_8822C(x, v)                                   \
+	(BIT_CLEAR_PKT_LIFTIME_VOVI_8822C(x) | BIT_PKT_LIFTIME_VOVI_8822C(v))
+
+/* 2 REG_STBC_SETTING_8822C */
+
+#define BIT_SHIFT_CDEND_TXTIME_L_8822C 4
+#define BIT_MASK_CDEND_TXTIME_L_8822C 0xf
+#define BIT_CDEND_TXTIME_L_8822C(x)                                            \
+	(((x) & BIT_MASK_CDEND_TXTIME_L_8822C)                                 \
+	 << BIT_SHIFT_CDEND_TXTIME_L_8822C)
+#define BITS_CDEND_TXTIME_L_8822C                                              \
+	(BIT_MASK_CDEND_TXTIME_L_8822C << BIT_SHIFT_CDEND_TXTIME_L_8822C)
+#define BIT_CLEAR_CDEND_TXTIME_L_8822C(x) ((x) & (~BITS_CDEND_TXTIME_L_8822C))
+#define BIT_GET_CDEND_TXTIME_L_8822C(x)                                        \
+	(((x) >> BIT_SHIFT_CDEND_TXTIME_L_8822C) &                             \
+	 BIT_MASK_CDEND_TXTIME_L_8822C)
+#define BIT_SET_CDEND_TXTIME_L_8822C(x, v)                                     \
+	(BIT_CLEAR_CDEND_TXTIME_L_8822C(x) | BIT_CDEND_TXTIME_L_8822C(v))
+
+#define BIT_SHIFT_NESS_8822C 2
+#define BIT_MASK_NESS_8822C 0x3
+#define BIT_NESS_8822C(x) (((x) & BIT_MASK_NESS_8822C) << BIT_SHIFT_NESS_8822C)
+#define BITS_NESS_8822C (BIT_MASK_NESS_8822C << BIT_SHIFT_NESS_8822C)
+#define BIT_CLEAR_NESS_8822C(x) ((x) & (~BITS_NESS_8822C))
+#define BIT_GET_NESS_8822C(x)                                                  \
+	(((x) >> BIT_SHIFT_NESS_8822C) & BIT_MASK_NESS_8822C)
+#define BIT_SET_NESS_8822C(x, v) (BIT_CLEAR_NESS_8822C(x) | BIT_NESS_8822C(v))
+
+#define BIT_SHIFT_STBC_CFEND_8822C 0
+#define BIT_MASK_STBC_CFEND_8822C 0x3
+#define BIT_STBC_CFEND_8822C(x)                                                \
+	(((x) & BIT_MASK_STBC_CFEND_8822C) << BIT_SHIFT_STBC_CFEND_8822C)
+#define BITS_STBC_CFEND_8822C                                                  \
+	(BIT_MASK_STBC_CFEND_8822C << BIT_SHIFT_STBC_CFEND_8822C)
+#define BIT_CLEAR_STBC_CFEND_8822C(x) ((x) & (~BITS_STBC_CFEND_8822C))
+#define BIT_GET_STBC_CFEND_8822C(x)                                            \
+	(((x) >> BIT_SHIFT_STBC_CFEND_8822C) & BIT_MASK_STBC_CFEND_8822C)
+#define BIT_SET_STBC_CFEND_8822C(x, v)                                         \
+	(BIT_CLEAR_STBC_CFEND_8822C(x) | BIT_STBC_CFEND_8822C(v))
+
+/* 2 REG_STBC_SETTING2_8822C */
+
+#define BIT_SHIFT_CDEND_TXTIME_H_8822C 0
+#define BIT_MASK_CDEND_TXTIME_H_8822C 0x1f
+#define BIT_CDEND_TXTIME_H_8822C(x)                                            \
+	(((x) & BIT_MASK_CDEND_TXTIME_H_8822C)                                 \
+	 << BIT_SHIFT_CDEND_TXTIME_H_8822C)
+#define BITS_CDEND_TXTIME_H_8822C                                              \
+	(BIT_MASK_CDEND_TXTIME_H_8822C << BIT_SHIFT_CDEND_TXTIME_H_8822C)
+#define BIT_CLEAR_CDEND_TXTIME_H_8822C(x) ((x) & (~BITS_CDEND_TXTIME_H_8822C))
+#define BIT_GET_CDEND_TXTIME_H_8822C(x)                                        \
+	(((x) >> BIT_SHIFT_CDEND_TXTIME_H_8822C) &                             \
+	 BIT_MASK_CDEND_TXTIME_H_8822C)
+#define BIT_SET_CDEND_TXTIME_H_8822C(x, v)                                     \
+	(BIT_CLEAR_CDEND_TXTIME_H_8822C(x) | BIT_CDEND_TXTIME_H_8822C(v))
+
+/* 2 REG_QUEUE_CTRL_8822C */
+#define BIT_FORCE_RND_PRI_8822C BIT(6)
+#define BIT_PTA_EDCCA_EN_8822C BIT(5)
+#define BIT_PTA_WL_TX_EN_8822C BIT(4)
+#define BIT_R_USE_DATA_BW_8822C BIT(3)
+#define BIT_TRI_PKT_INT_MODE1_8822C BIT(2)
+#define BIT_TRI_PKT_INT_MODE0_8822C BIT(1)
+#define BIT_ACQ_MODE_SEL_8822C BIT(0)
+
+/* 2 REG_SINGLE_AMPDU_CTRL_8822C */
+#define BIT_EN_SINGLE_APMDU_8822C BIT(7)
+
+#define BIT_SHIFT_SNDTX_MAXTIME_8822C 0
+#define BIT_MASK_SNDTX_MAXTIME_8822C 0x7f
+#define BIT_SNDTX_MAXTIME_8822C(x)                                             \
+	(((x) & BIT_MASK_SNDTX_MAXTIME_8822C) << BIT_SHIFT_SNDTX_MAXTIME_8822C)
+#define BITS_SNDTX_MAXTIME_8822C                                               \
+	(BIT_MASK_SNDTX_MAXTIME_8822C << BIT_SHIFT_SNDTX_MAXTIME_8822C)
+#define BIT_CLEAR_SNDTX_MAXTIME_8822C(x) ((x) & (~BITS_SNDTX_MAXTIME_8822C))
+#define BIT_GET_SNDTX_MAXTIME_8822C(x)                                         \
+	(((x) >> BIT_SHIFT_SNDTX_MAXTIME_8822C) & BIT_MASK_SNDTX_MAXTIME_8822C)
+#define BIT_SET_SNDTX_MAXTIME_8822C(x, v)                                      \
+	(BIT_CLEAR_SNDTX_MAXTIME_8822C(x) | BIT_SNDTX_MAXTIME_8822C(v))
+
+/* 2 REG_PROT_MODE_CTRL_8822C */
+#define BIT_SND_SIFS_TXDATA_8822C BIT(31)
+#define BIT_TX_SND_MATCH_MACID_8822C BIT(30)
+
+#define BIT_SHIFT_RTS_MAX_AGG_NUM_8822C 24
+#define BIT_MASK_RTS_MAX_AGG_NUM_8822C 0x3f
+#define BIT_RTS_MAX_AGG_NUM_8822C(x)                                           \
+	(((x) & BIT_MASK_RTS_MAX_AGG_NUM_8822C)                                \
+	 << BIT_SHIFT_RTS_MAX_AGG_NUM_8822C)
+#define BITS_RTS_MAX_AGG_NUM_8822C                                             \
+	(BIT_MASK_RTS_MAX_AGG_NUM_8822C << BIT_SHIFT_RTS_MAX_AGG_NUM_8822C)
+#define BIT_CLEAR_RTS_MAX_AGG_NUM_8822C(x) ((x) & (~BITS_RTS_MAX_AGG_NUM_8822C))
+#define BIT_GET_RTS_MAX_AGG_NUM_8822C(x)                                       \
+	(((x) >> BIT_SHIFT_RTS_MAX_AGG_NUM_8822C) &                            \
+	 BIT_MASK_RTS_MAX_AGG_NUM_8822C)
+#define BIT_SET_RTS_MAX_AGG_NUM_8822C(x, v)                                    \
+	(BIT_CLEAR_RTS_MAX_AGG_NUM_8822C(x) | BIT_RTS_MAX_AGG_NUM_8822C(v))
+
+#define BIT_SHIFT_MAX_AGG_NUM_8822C 16
+#define BIT_MASK_MAX_AGG_NUM_8822C 0x3f
+#define BIT_MAX_AGG_NUM_8822C(x)                                               \
+	(((x) & BIT_MASK_MAX_AGG_NUM_8822C) << BIT_SHIFT_MAX_AGG_NUM_8822C)
+#define BITS_MAX_AGG_NUM_8822C                                                 \
+	(BIT_MASK_MAX_AGG_NUM_8822C << BIT_SHIFT_MAX_AGG_NUM_8822C)
+#define BIT_CLEAR_MAX_AGG_NUM_8822C(x) ((x) & (~BITS_MAX_AGG_NUM_8822C))
+#define BIT_GET_MAX_AGG_NUM_8822C(x)                                           \
+	(((x) >> BIT_SHIFT_MAX_AGG_NUM_8822C) & BIT_MASK_MAX_AGG_NUM_8822C)
+#define BIT_SET_MAX_AGG_NUM_8822C(x, v)                                        \
+	(BIT_CLEAR_MAX_AGG_NUM_8822C(x) | BIT_MAX_AGG_NUM_8822C(v))
+
+#define BIT_SHIFT_RTS_TXTIME_TH_8822C 8
+#define BIT_MASK_RTS_TXTIME_TH_8822C 0xff
+#define BIT_RTS_TXTIME_TH_8822C(x)                                             \
+	(((x) & BIT_MASK_RTS_TXTIME_TH_8822C) << BIT_SHIFT_RTS_TXTIME_TH_8822C)
+#define BITS_RTS_TXTIME_TH_8822C                                               \
+	(BIT_MASK_RTS_TXTIME_TH_8822C << BIT_SHIFT_RTS_TXTIME_TH_8822C)
+#define BIT_CLEAR_RTS_TXTIME_TH_8822C(x) ((x) & (~BITS_RTS_TXTIME_TH_8822C))
+#define BIT_GET_RTS_TXTIME_TH_8822C(x)                                         \
+	(((x) >> BIT_SHIFT_RTS_TXTIME_TH_8822C) & BIT_MASK_RTS_TXTIME_TH_8822C)
+#define BIT_SET_RTS_TXTIME_TH_8822C(x, v)                                      \
+	(BIT_CLEAR_RTS_TXTIME_TH_8822C(x) | BIT_RTS_TXTIME_TH_8822C(v))
+
+#define BIT_SHIFT_RTS_LEN_TH_8822C 0
+#define BIT_MASK_RTS_LEN_TH_8822C 0xff
+#define BIT_RTS_LEN_TH_8822C(x)                                                \
+	(((x) & BIT_MASK_RTS_LEN_TH_8822C) << BIT_SHIFT_RTS_LEN_TH_8822C)
+#define BITS_RTS_LEN_TH_8822C                                                  \
+	(BIT_MASK_RTS_LEN_TH_8822C << BIT_SHIFT_RTS_LEN_TH_8822C)
+#define BIT_CLEAR_RTS_LEN_TH_8822C(x) ((x) & (~BITS_RTS_LEN_TH_8822C))
+#define BIT_GET_RTS_LEN_TH_8822C(x)                                            \
+	(((x) >> BIT_SHIFT_RTS_LEN_TH_8822C) & BIT_MASK_RTS_LEN_TH_8822C)
+#define BIT_SET_RTS_LEN_TH_8822C(x, v)                                         \
+	(BIT_CLEAR_RTS_LEN_TH_8822C(x) | BIT_RTS_LEN_TH_8822C(v))
+
+/* 2 REG_BAR_MODE_CTRL_8822C */
+
+#define BIT_SHIFT_BAR_RTY_LMT_8822C 16
+#define BIT_MASK_BAR_RTY_LMT_8822C 0x3
+#define BIT_BAR_RTY_LMT_8822C(x)                                               \
+	(((x) & BIT_MASK_BAR_RTY_LMT_8822C) << BIT_SHIFT_BAR_RTY_LMT_8822C)
+#define BITS_BAR_RTY_LMT_8822C                                                 \
+	(BIT_MASK_BAR_RTY_LMT_8822C << BIT_SHIFT_BAR_RTY_LMT_8822C)
+#define BIT_CLEAR_BAR_RTY_LMT_8822C(x) ((x) & (~BITS_BAR_RTY_LMT_8822C))
+#define BIT_GET_BAR_RTY_LMT_8822C(x)                                           \
+	(((x) >> BIT_SHIFT_BAR_RTY_LMT_8822C) & BIT_MASK_BAR_RTY_LMT_8822C)
+#define BIT_SET_BAR_RTY_LMT_8822C(x, v)                                        \
+	(BIT_CLEAR_BAR_RTY_LMT_8822C(x) | BIT_BAR_RTY_LMT_8822C(v))
+
+#define BIT_SHIFT_BAR_PKT_TXTIME_TH_8822C 8
+#define BIT_MASK_BAR_PKT_TXTIME_TH_8822C 0xff
+#define BIT_BAR_PKT_TXTIME_TH_8822C(x)                                         \
+	(((x) & BIT_MASK_BAR_PKT_TXTIME_TH_8822C)                              \
+	 << BIT_SHIFT_BAR_PKT_TXTIME_TH_8822C)
+#define BITS_BAR_PKT_TXTIME_TH_8822C                                           \
+	(BIT_MASK_BAR_PKT_TXTIME_TH_8822C << BIT_SHIFT_BAR_PKT_TXTIME_TH_8822C)
+#define BIT_CLEAR_BAR_PKT_TXTIME_TH_8822C(x)                                   \
+	((x) & (~BITS_BAR_PKT_TXTIME_TH_8822C))
+#define BIT_GET_BAR_PKT_TXTIME_TH_8822C(x)                                     \
+	(((x) >> BIT_SHIFT_BAR_PKT_TXTIME_TH_8822C) &                          \
+	 BIT_MASK_BAR_PKT_TXTIME_TH_8822C)
+#define BIT_SET_BAR_PKT_TXTIME_TH_8822C(x, v)                                  \
+	(BIT_CLEAR_BAR_PKT_TXTIME_TH_8822C(x) | BIT_BAR_PKT_TXTIME_TH_8822C(v))
+
+#define BIT_BAR_EN_V1_8822C BIT(6)
+
+#define BIT_SHIFT_BAR_PKTNUM_TH_V1_8822C 0
+#define BIT_MASK_BAR_PKTNUM_TH_V1_8822C 0x3f
+#define BIT_BAR_PKTNUM_TH_V1_8822C(x)                                          \
+	(((x) & BIT_MASK_BAR_PKTNUM_TH_V1_8822C)                               \
+	 << BIT_SHIFT_BAR_PKTNUM_TH_V1_8822C)
+#define BITS_BAR_PKTNUM_TH_V1_8822C                                            \
+	(BIT_MASK_BAR_PKTNUM_TH_V1_8822C << BIT_SHIFT_BAR_PKTNUM_TH_V1_8822C)
+#define BIT_CLEAR_BAR_PKTNUM_TH_V1_8822C(x)                                    \
+	((x) & (~BITS_BAR_PKTNUM_TH_V1_8822C))
+#define BIT_GET_BAR_PKTNUM_TH_V1_8822C(x)                                      \
+	(((x) >> BIT_SHIFT_BAR_PKTNUM_TH_V1_8822C) &                           \
+	 BIT_MASK_BAR_PKTNUM_TH_V1_8822C)
+#define BIT_SET_BAR_PKTNUM_TH_V1_8822C(x, v)                                   \
+	(BIT_CLEAR_BAR_PKTNUM_TH_V1_8822C(x) | BIT_BAR_PKTNUM_TH_V1_8822C(v))
+
+/* 2 REG_RA_TRY_RATE_AGG_LMT_8822C */
+
+#define BIT_SHIFT_RA_TRY_RATE_AGG_LMT_V1_8822C 0
+#define BIT_MASK_RA_TRY_RATE_AGG_LMT_V1_8822C 0x3f
+#define BIT_RA_TRY_RATE_AGG_LMT_V1_8822C(x)                                    \
+	(((x) & BIT_MASK_RA_TRY_RATE_AGG_LMT_V1_8822C)                         \
+	 << BIT_SHIFT_RA_TRY_RATE_AGG_LMT_V1_8822C)
+#define BITS_RA_TRY_RATE_AGG_LMT_V1_8822C                                      \
+	(BIT_MASK_RA_TRY_RATE_AGG_LMT_V1_8822C                                 \
+	 << BIT_SHIFT_RA_TRY_RATE_AGG_LMT_V1_8822C)
+#define BIT_CLEAR_RA_TRY_RATE_AGG_LMT_V1_8822C(x)                              \
+	((x) & (~BITS_RA_TRY_RATE_AGG_LMT_V1_8822C))
+#define BIT_GET_RA_TRY_RATE_AGG_LMT_V1_8822C(x)                                \
+	(((x) >> BIT_SHIFT_RA_TRY_RATE_AGG_LMT_V1_8822C) &                     \
+	 BIT_MASK_RA_TRY_RATE_AGG_LMT_V1_8822C)
+#define BIT_SET_RA_TRY_RATE_AGG_LMT_V1_8822C(x, v)                             \
+	(BIT_CLEAR_RA_TRY_RATE_AGG_LMT_V1_8822C(x) |                           \
+	 BIT_RA_TRY_RATE_AGG_LMT_V1_8822C(v))
+
+/* 2 REG_MACID_SLEEP2_8822C */
+
+#define BIT_SHIFT_MACID95_64PKTSLEEP_8822C 0
+#define BIT_MASK_MACID95_64PKTSLEEP_8822C 0xffffffffL
+#define BIT_MACID95_64PKTSLEEP_8822C(x)                                        \
+	(((x) & BIT_MASK_MACID95_64PKTSLEEP_8822C)                             \
+	 << BIT_SHIFT_MACID95_64PKTSLEEP_8822C)
+#define BITS_MACID95_64PKTSLEEP_8822C                                          \
+	(BIT_MASK_MACID95_64PKTSLEEP_8822C                                     \
+	 << BIT_SHIFT_MACID95_64PKTSLEEP_8822C)
+#define BIT_CLEAR_MACID95_64PKTSLEEP_8822C(x)                                  \
+	((x) & (~BITS_MACID95_64PKTSLEEP_8822C))
+#define BIT_GET_MACID95_64PKTSLEEP_8822C(x)                                    \
+	(((x) >> BIT_SHIFT_MACID95_64PKTSLEEP_8822C) &                         \
+	 BIT_MASK_MACID95_64PKTSLEEP_8822C)
+#define BIT_SET_MACID95_64PKTSLEEP_8822C(x, v)                                 \
+	(BIT_CLEAR_MACID95_64PKTSLEEP_8822C(x) |                               \
+	 BIT_MACID95_64PKTSLEEP_8822C(v))
+
+/* 2 REG_MACID_SLEEP_8822C */
+
+#define BIT_SHIFT_MACID31_0_PKTSLEEP_8822C 0
+#define BIT_MASK_MACID31_0_PKTSLEEP_8822C 0xffffffffL
+#define BIT_MACID31_0_PKTSLEEP_8822C(x)                                        \
+	(((x) & BIT_MASK_MACID31_0_PKTSLEEP_8822C)                             \
+	 << BIT_SHIFT_MACID31_0_PKTSLEEP_8822C)
+#define BITS_MACID31_0_PKTSLEEP_8822C                                          \
+	(BIT_MASK_MACID31_0_PKTSLEEP_8822C                                     \
+	 << BIT_SHIFT_MACID31_0_PKTSLEEP_8822C)
+#define BIT_CLEAR_MACID31_0_PKTSLEEP_8822C(x)                                  \
+	((x) & (~BITS_MACID31_0_PKTSLEEP_8822C))
+#define BIT_GET_MACID31_0_PKTSLEEP_8822C(x)                                    \
+	(((x) >> BIT_SHIFT_MACID31_0_PKTSLEEP_8822C) &                         \
+	 BIT_MASK_MACID31_0_PKTSLEEP_8822C)
+#define BIT_SET_MACID31_0_PKTSLEEP_8822C(x, v)                                 \
+	(BIT_CLEAR_MACID31_0_PKTSLEEP_8822C(x) |                               \
+	 BIT_MACID31_0_PKTSLEEP_8822C(v))
+
+/* 2 REG_HW_SEQ0_8822C */
+
+#define BIT_SHIFT_HW_SSN_SEQ0_8822C 0
+#define BIT_MASK_HW_SSN_SEQ0_8822C 0xfff
+#define BIT_HW_SSN_SEQ0_8822C(x)                                               \
+	(((x) & BIT_MASK_HW_SSN_SEQ0_8822C) << BIT_SHIFT_HW_SSN_SEQ0_8822C)
+#define BITS_HW_SSN_SEQ0_8822C                                                 \
+	(BIT_MASK_HW_SSN_SEQ0_8822C << BIT_SHIFT_HW_SSN_SEQ0_8822C)
+#define BIT_CLEAR_HW_SSN_SEQ0_8822C(x) ((x) & (~BITS_HW_SSN_SEQ0_8822C))
+#define BIT_GET_HW_SSN_SEQ0_8822C(x)                                           \
+	(((x) >> BIT_SHIFT_HW_SSN_SEQ0_8822C) & BIT_MASK_HW_SSN_SEQ0_8822C)
+#define BIT_SET_HW_SSN_SEQ0_8822C(x, v)                                        \
+	(BIT_CLEAR_HW_SSN_SEQ0_8822C(x) | BIT_HW_SSN_SEQ0_8822C(v))
+
+/* 2 REG_HW_SEQ1_8822C */
+
+#define BIT_SHIFT_HW_SSN_SEQ1_8822C 0
+#define BIT_MASK_HW_SSN_SEQ1_8822C 0xfff
+#define BIT_HW_SSN_SEQ1_8822C(x)                                               \
+	(((x) & BIT_MASK_HW_SSN_SEQ1_8822C) << BIT_SHIFT_HW_SSN_SEQ1_8822C)
+#define BITS_HW_SSN_SEQ1_8822C                                                 \
+	(BIT_MASK_HW_SSN_SEQ1_8822C << BIT_SHIFT_HW_SSN_SEQ1_8822C)
+#define BIT_CLEAR_HW_SSN_SEQ1_8822C(x) ((x) & (~BITS_HW_SSN_SEQ1_8822C))
+#define BIT_GET_HW_SSN_SEQ1_8822C(x)                                           \
+	(((x) >> BIT_SHIFT_HW_SSN_SEQ1_8822C) & BIT_MASK_HW_SSN_SEQ1_8822C)
+#define BIT_SET_HW_SSN_SEQ1_8822C(x, v)                                        \
+	(BIT_CLEAR_HW_SSN_SEQ1_8822C(x) | BIT_HW_SSN_SEQ1_8822C(v))
+
+/* 2 REG_HW_SEQ2_8822C */
+
+#define BIT_SHIFT_HW_SSN_SEQ2_8822C 0
+#define BIT_MASK_HW_SSN_SEQ2_8822C 0xfff
+#define BIT_HW_SSN_SEQ2_8822C(x)                                               \
+	(((x) & BIT_MASK_HW_SSN_SEQ2_8822C) << BIT_SHIFT_HW_SSN_SEQ2_8822C)
+#define BITS_HW_SSN_SEQ2_8822C                                                 \
+	(BIT_MASK_HW_SSN_SEQ2_8822C << BIT_SHIFT_HW_SSN_SEQ2_8822C)
+#define BIT_CLEAR_HW_SSN_SEQ2_8822C(x) ((x) & (~BITS_HW_SSN_SEQ2_8822C))
+#define BIT_GET_HW_SSN_SEQ2_8822C(x)                                           \
+	(((x) >> BIT_SHIFT_HW_SSN_SEQ2_8822C) & BIT_MASK_HW_SSN_SEQ2_8822C)
+#define BIT_SET_HW_SSN_SEQ2_8822C(x, v)                                        \
+	(BIT_CLEAR_HW_SSN_SEQ2_8822C(x) | BIT_HW_SSN_SEQ2_8822C(v))
+
+/* 2 REG_HW_SEQ3_8822C */
+
+#define BIT_SHIFT_CSI_HWSEQ_SEL_8822C 12
+#define BIT_MASK_CSI_HWSEQ_SEL_8822C 0x3
+#define BIT_CSI_HWSEQ_SEL_8822C(x)                                             \
+	(((x) & BIT_MASK_CSI_HWSEQ_SEL_8822C) << BIT_SHIFT_CSI_HWSEQ_SEL_8822C)
+#define BITS_CSI_HWSEQ_SEL_8822C                                               \
+	(BIT_MASK_CSI_HWSEQ_SEL_8822C << BIT_SHIFT_CSI_HWSEQ_SEL_8822C)
+#define BIT_CLEAR_CSI_HWSEQ_SEL_8822C(x) ((x) & (~BITS_CSI_HWSEQ_SEL_8822C))
+#define BIT_GET_CSI_HWSEQ_SEL_8822C(x)                                         \
+	(((x) >> BIT_SHIFT_CSI_HWSEQ_SEL_8822C) & BIT_MASK_CSI_HWSEQ_SEL_8822C)
+#define BIT_SET_CSI_HWSEQ_SEL_8822C(x, v)                                      \
+	(BIT_CLEAR_CSI_HWSEQ_SEL_8822C(x) | BIT_CSI_HWSEQ_SEL_8822C(v))
+
+#define BIT_SHIFT_HW_SSN_SEQ3_8822C 0
+#define BIT_MASK_HW_SSN_SEQ3_8822C 0xfff
+#define BIT_HW_SSN_SEQ3_8822C(x)                                               \
+	(((x) & BIT_MASK_HW_SSN_SEQ3_8822C) << BIT_SHIFT_HW_SSN_SEQ3_8822C)
+#define BITS_HW_SSN_SEQ3_8822C                                                 \
+	(BIT_MASK_HW_SSN_SEQ3_8822C << BIT_SHIFT_HW_SSN_SEQ3_8822C)
+#define BIT_CLEAR_HW_SSN_SEQ3_8822C(x) ((x) & (~BITS_HW_SSN_SEQ3_8822C))
+#define BIT_GET_HW_SSN_SEQ3_8822C(x)                                           \
+	(((x) >> BIT_SHIFT_HW_SSN_SEQ3_8822C) & BIT_MASK_HW_SSN_SEQ3_8822C)
+#define BIT_SET_HW_SSN_SEQ3_8822C(x, v)                                        \
+	(BIT_CLEAR_HW_SSN_SEQ3_8822C(x) | BIT_HW_SSN_SEQ3_8822C(v))
+
+/* 2 REG_NULL_PKT_STATUS_V1_8822C */
+
+#define BIT_SHIFT_PTCL_TOTAL_PG_V2_8822C 2
+#define BIT_MASK_PTCL_TOTAL_PG_V2_8822C 0x3fff
+#define BIT_PTCL_TOTAL_PG_V2_8822C(x)                                          \
+	(((x) & BIT_MASK_PTCL_TOTAL_PG_V2_8822C)                               \
+	 << BIT_SHIFT_PTCL_TOTAL_PG_V2_8822C)
+#define BITS_PTCL_TOTAL_PG_V2_8822C                                            \
+	(BIT_MASK_PTCL_TOTAL_PG_V2_8822C << BIT_SHIFT_PTCL_TOTAL_PG_V2_8822C)
+#define BIT_CLEAR_PTCL_TOTAL_PG_V2_8822C(x)                                    \
+	((x) & (~BITS_PTCL_TOTAL_PG_V2_8822C))
+#define BIT_GET_PTCL_TOTAL_PG_V2_8822C(x)                                      \
+	(((x) >> BIT_SHIFT_PTCL_TOTAL_PG_V2_8822C) &                           \
+	 BIT_MASK_PTCL_TOTAL_PG_V2_8822C)
+#define BIT_SET_PTCL_TOTAL_PG_V2_8822C(x, v)                                   \
+	(BIT_CLEAR_PTCL_TOTAL_PG_V2_8822C(x) | BIT_PTCL_TOTAL_PG_V2_8822C(v))
+
+#define BIT_TX_NULL_1_8822C BIT(1)
+#define BIT_TX_NULL_0_8822C BIT(0)
+
+/* 2 REG_PTCL_ERR_STATUS_8822C */
+#define BIT_PTCL_RATE_TABLE_INVALID_8822C BIT(7)
+#define BIT_FTM_T2R_ERROR_8822C BIT(6)
+#define BIT_PTCL_ERR0_8822C BIT(5)
+#define BIT_PTCL_ERR1_8822C BIT(4)
+#define BIT_PTCL_ERR2_8822C BIT(3)
+#define BIT_PTCL_ERR3_8822C BIT(2)
+#define BIT_PTCL_ERR4_8822C BIT(1)
+#define BIT_PTCL_ERR5_8822C BIT(0)
+
+/* 2 REG_NULL_PKT_STATUS_EXTEND_8822C */
+#define BIT_CLI3_TX_NULL_1_8822C BIT(7)
+#define BIT_CLI3_TX_NULL_0_8822C BIT(6)
+#define BIT_CLI2_TX_NULL_1_8822C BIT(5)
+#define BIT_CLI2_TX_NULL_0_8822C BIT(4)
+#define BIT_CLI1_TX_NULL_1_8822C BIT(3)
+#define BIT_CLI1_TX_NULL_0_8822C BIT(2)
+#define BIT_CLI0_TX_NULL_1_8822C BIT(1)
+#define BIT_CLI0_TX_NULL_0_8822C BIT(0)
+
+/* 2 REG_HQMGQ_DROP_8822C */
+#define BIT_HIQ_DROP_8822C BIT(7)
+#define BIT_MGQ_DROP_8822C BIT(6)
+#define BIT_CLR_HGQ_REQ_BLOCK_8822C BIT(5)
+
+/* 2 REG_PRECNT_CTRL_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+#define BIT_EN_PRECNT_8822C BIT(11)
+
+#define BIT_SHIFT_PRECNT_TH_8822C 0
+#define BIT_MASK_PRECNT_TH_8822C 0x7ff
+#define BIT_PRECNT_TH_8822C(x)                                                 \
+	(((x) & BIT_MASK_PRECNT_TH_8822C) << BIT_SHIFT_PRECNT_TH_8822C)
+#define BITS_PRECNT_TH_8822C                                                   \
+	(BIT_MASK_PRECNT_TH_8822C << BIT_SHIFT_PRECNT_TH_8822C)
+#define BIT_CLEAR_PRECNT_TH_8822C(x) ((x) & (~BITS_PRECNT_TH_8822C))
+#define BIT_GET_PRECNT_TH_8822C(x)                                             \
+	(((x) >> BIT_SHIFT_PRECNT_TH_8822C) & BIT_MASK_PRECNT_TH_8822C)
+#define BIT_SET_PRECNT_TH_8822C(x, v)                                          \
+	(BIT_CLEAR_PRECNT_TH_8822C(x) | BIT_PRECNT_TH_8822C(v))
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_BT_POLLUTE_PKT_CNT_8822C */
+
+#define BIT_SHIFT_BT_POLLUTE_PKT_CNT_8822C 0
+#define BIT_MASK_BT_POLLUTE_PKT_CNT_8822C 0xffff
+#define BIT_BT_POLLUTE_PKT_CNT_8822C(x)                                        \
+	(((x) & BIT_MASK_BT_POLLUTE_PKT_CNT_8822C)                             \
+	 << BIT_SHIFT_BT_POLLUTE_PKT_CNT_8822C)
+#define BITS_BT_POLLUTE_PKT_CNT_8822C                                          \
+	(BIT_MASK_BT_POLLUTE_PKT_CNT_8822C                                     \
+	 << BIT_SHIFT_BT_POLLUTE_PKT_CNT_8822C)
+#define BIT_CLEAR_BT_POLLUTE_PKT_CNT_8822C(x)                                  \
+	((x) & (~BITS_BT_POLLUTE_PKT_CNT_8822C))
+#define BIT_GET_BT_POLLUTE_PKT_CNT_8822C(x)                                    \
+	(((x) >> BIT_SHIFT_BT_POLLUTE_PKT_CNT_8822C) &                         \
+	 BIT_MASK_BT_POLLUTE_PKT_CNT_8822C)
+#define BIT_SET_BT_POLLUTE_PKT_CNT_8822C(x, v)                                 \
+	(BIT_CLEAR_BT_POLLUTE_PKT_CNT_8822C(x) |                               \
+	 BIT_BT_POLLUTE_PKT_CNT_8822C(v))
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_PTCL_DBG_8822C */
+
+#define BIT_SHIFT_PTCL_DBG_8822C 0
+#define BIT_MASK_PTCL_DBG_8822C 0xffffffffL
+#define BIT_PTCL_DBG_8822C(x)                                                  \
+	(((x) & BIT_MASK_PTCL_DBG_8822C) << BIT_SHIFT_PTCL_DBG_8822C)
+#define BITS_PTCL_DBG_8822C                                                    \
+	(BIT_MASK_PTCL_DBG_8822C << BIT_SHIFT_PTCL_DBG_8822C)
+#define BIT_CLEAR_PTCL_DBG_8822C(x) ((x) & (~BITS_PTCL_DBG_8822C))
+#define BIT_GET_PTCL_DBG_8822C(x)                                              \
+	(((x) >> BIT_SHIFT_PTCL_DBG_8822C) & BIT_MASK_PTCL_DBG_8822C)
+#define BIT_SET_PTCL_DBG_8822C(x, v)                                           \
+	(BIT_CLEAR_PTCL_DBG_8822C(x) | BIT_PTCL_DBG_8822C(v))
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_CPUMGQ_TIMER_CTRL2_8822C */
+
+#define BIT_SHIFT_TRI_HEAD_ADDR_8822C 16
+#define BIT_MASK_TRI_HEAD_ADDR_8822C 0xfff
+#define BIT_TRI_HEAD_ADDR_8822C(x)                                             \
+	(((x) & BIT_MASK_TRI_HEAD_ADDR_8822C) << BIT_SHIFT_TRI_HEAD_ADDR_8822C)
+#define BITS_TRI_HEAD_ADDR_8822C                                               \
+	(BIT_MASK_TRI_HEAD_ADDR_8822C << BIT_SHIFT_TRI_HEAD_ADDR_8822C)
+#define BIT_CLEAR_TRI_HEAD_ADDR_8822C(x) ((x) & (~BITS_TRI_HEAD_ADDR_8822C))
+#define BIT_GET_TRI_HEAD_ADDR_8822C(x)                                         \
+	(((x) >> BIT_SHIFT_TRI_HEAD_ADDR_8822C) & BIT_MASK_TRI_HEAD_ADDR_8822C)
+#define BIT_SET_TRI_HEAD_ADDR_8822C(x, v)                                      \
+	(BIT_CLEAR_TRI_HEAD_ADDR_8822C(x) | BIT_TRI_HEAD_ADDR_8822C(v))
+
+#define BIT_DROP_TH_EN_8822C BIT(8)
+
+#define BIT_SHIFT_DROP_TH_8822C 0
+#define BIT_MASK_DROP_TH_8822C 0xff
+#define BIT_DROP_TH_8822C(x)                                                   \
+	(((x) & BIT_MASK_DROP_TH_8822C) << BIT_SHIFT_DROP_TH_8822C)
+#define BITS_DROP_TH_8822C (BIT_MASK_DROP_TH_8822C << BIT_SHIFT_DROP_TH_8822C)
+#define BIT_CLEAR_DROP_TH_8822C(x) ((x) & (~BITS_DROP_TH_8822C))
+#define BIT_GET_DROP_TH_8822C(x)                                               \
+	(((x) >> BIT_SHIFT_DROP_TH_8822C) & BIT_MASK_DROP_TH_8822C)
+#define BIT_SET_DROP_TH_8822C(x, v)                                            \
+	(BIT_CLEAR_DROP_TH_8822C(x) | BIT_DROP_TH_8822C(v))
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_DUMMY_PAGE4_V1_8822C */
+
+/* 2 REG_MOREDATA_8822C */
+#define BIT_MOREDATA_CTRL2_EN_V1_8822C BIT(3)
+#define BIT_MOREDATA_CTRL1_EN_V1_8822C BIT(2)
+#define BIT_PKTIN_MOREDATA_REPLACE_ENABLE_V1_8822C BIT(0)
+
+/* 2 REG_Q0_Q1_INFO_8822C */
+#define BIT_QUEUE_MACID_AC_NOT_THE_SAME_8822C BIT(31)
+
+#define BIT_SHIFT_GTAB_ID_8822C 28
+#define BIT_MASK_GTAB_ID_8822C 0x7
+#define BIT_GTAB_ID_8822C(x)                                                   \
+	(((x) & BIT_MASK_GTAB_ID_8822C) << BIT_SHIFT_GTAB_ID_8822C)
+#define BITS_GTAB_ID_8822C (BIT_MASK_GTAB_ID_8822C << BIT_SHIFT_GTAB_ID_8822C)
+#define BIT_CLEAR_GTAB_ID_8822C(x) ((x) & (~BITS_GTAB_ID_8822C))
+#define BIT_GET_GTAB_ID_8822C(x)                                               \
+	(((x) >> BIT_SHIFT_GTAB_ID_8822C) & BIT_MASK_GTAB_ID_8822C)
+#define BIT_SET_GTAB_ID_8822C(x, v)                                            \
+	(BIT_CLEAR_GTAB_ID_8822C(x) | BIT_GTAB_ID_8822C(v))
+
+#define BIT_SHIFT_AC1_PKT_INFO_8822C 16
+#define BIT_MASK_AC1_PKT_INFO_8822C 0xfff
+#define BIT_AC1_PKT_INFO_8822C(x)                                              \
+	(((x) & BIT_MASK_AC1_PKT_INFO_8822C) << BIT_SHIFT_AC1_PKT_INFO_8822C)
+#define BITS_AC1_PKT_INFO_8822C                                                \
+	(BIT_MASK_AC1_PKT_INFO_8822C << BIT_SHIFT_AC1_PKT_INFO_8822C)
+#define BIT_CLEAR_AC1_PKT_INFO_8822C(x) ((x) & (~BITS_AC1_PKT_INFO_8822C))
+#define BIT_GET_AC1_PKT_INFO_8822C(x)                                          \
+	(((x) >> BIT_SHIFT_AC1_PKT_INFO_8822C) & BIT_MASK_AC1_PKT_INFO_8822C)
+#define BIT_SET_AC1_PKT_INFO_8822C(x, v)                                       \
+	(BIT_CLEAR_AC1_PKT_INFO_8822C(x) | BIT_AC1_PKT_INFO_8822C(v))
+
+#define BIT_QUEUE_MACID_AC_NOT_THE_SAME_V1_8822C BIT(15)
+
+#define BIT_SHIFT_GTAB_ID_V1_8822C 12
+#define BIT_MASK_GTAB_ID_V1_8822C 0x7
+#define BIT_GTAB_ID_V1_8822C(x)                                                \
+	(((x) & BIT_MASK_GTAB_ID_V1_8822C) << BIT_SHIFT_GTAB_ID_V1_8822C)
+#define BITS_GTAB_ID_V1_8822C                                                  \
+	(BIT_MASK_GTAB_ID_V1_8822C << BIT_SHIFT_GTAB_ID_V1_8822C)
+#define BIT_CLEAR_GTAB_ID_V1_8822C(x) ((x) & (~BITS_GTAB_ID_V1_8822C))
+#define BIT_GET_GTAB_ID_V1_8822C(x)                                            \
+	(((x) >> BIT_SHIFT_GTAB_ID_V1_8822C) & BIT_MASK_GTAB_ID_V1_8822C)
+#define BIT_SET_GTAB_ID_V1_8822C(x, v)                                         \
+	(BIT_CLEAR_GTAB_ID_V1_8822C(x) | BIT_GTAB_ID_V1_8822C(v))
+
+#define BIT_SHIFT_AC0_PKT_INFO_8822C 0
+#define BIT_MASK_AC0_PKT_INFO_8822C 0xfff
+#define BIT_AC0_PKT_INFO_8822C(x)                                              \
+	(((x) & BIT_MASK_AC0_PKT_INFO_8822C) << BIT_SHIFT_AC0_PKT_INFO_8822C)
+#define BITS_AC0_PKT_INFO_8822C                                                \
+	(BIT_MASK_AC0_PKT_INFO_8822C << BIT_SHIFT_AC0_PKT_INFO_8822C)
+#define BIT_CLEAR_AC0_PKT_INFO_8822C(x) ((x) & (~BITS_AC0_PKT_INFO_8822C))
+#define BIT_GET_AC0_PKT_INFO_8822C(x)                                          \
+	(((x) >> BIT_SHIFT_AC0_PKT_INFO_8822C) & BIT_MASK_AC0_PKT_INFO_8822C)
+#define BIT_SET_AC0_PKT_INFO_8822C(x, v)                                       \
+	(BIT_CLEAR_AC0_PKT_INFO_8822C(x) | BIT_AC0_PKT_INFO_8822C(v))
+
+/* 2 REG_Q2_Q3_INFO_8822C */
+#define BIT_QUEUE_MACID_AC_NOT_THE_SAME_8822C BIT(31)
+
+#define BIT_SHIFT_GTAB_ID_8822C 28
+#define BIT_MASK_GTAB_ID_8822C 0x7
+#define BIT_GTAB_ID_8822C(x)                                                   \
+	(((x) & BIT_MASK_GTAB_ID_8822C) << BIT_SHIFT_GTAB_ID_8822C)
+#define BITS_GTAB_ID_8822C (BIT_MASK_GTAB_ID_8822C << BIT_SHIFT_GTAB_ID_8822C)
+#define BIT_CLEAR_GTAB_ID_8822C(x) ((x) & (~BITS_GTAB_ID_8822C))
+#define BIT_GET_GTAB_ID_8822C(x)                                               \
+	(((x) >> BIT_SHIFT_GTAB_ID_8822C) & BIT_MASK_GTAB_ID_8822C)
+#define BIT_SET_GTAB_ID_8822C(x, v)                                            \
+	(BIT_CLEAR_GTAB_ID_8822C(x) | BIT_GTAB_ID_8822C(v))
+
+#define BIT_SHIFT_AC3_PKT_INFO_8822C 16
+#define BIT_MASK_AC3_PKT_INFO_8822C 0xfff
+#define BIT_AC3_PKT_INFO_8822C(x)                                              \
+	(((x) & BIT_MASK_AC3_PKT_INFO_8822C) << BIT_SHIFT_AC3_PKT_INFO_8822C)
+#define BITS_AC3_PKT_INFO_8822C                                                \
+	(BIT_MASK_AC3_PKT_INFO_8822C << BIT_SHIFT_AC3_PKT_INFO_8822C)
+#define BIT_CLEAR_AC3_PKT_INFO_8822C(x) ((x) & (~BITS_AC3_PKT_INFO_8822C))
+#define BIT_GET_AC3_PKT_INFO_8822C(x)                                          \
+	(((x) >> BIT_SHIFT_AC3_PKT_INFO_8822C) & BIT_MASK_AC3_PKT_INFO_8822C)
+#define BIT_SET_AC3_PKT_INFO_8822C(x, v)                                       \
+	(BIT_CLEAR_AC3_PKT_INFO_8822C(x) | BIT_AC3_PKT_INFO_8822C(v))
+
+#define BIT_QUEUE_MACID_AC_NOT_THE_SAME_V1_8822C BIT(15)
+
+#define BIT_SHIFT_GTAB_ID_V1_8822C 12
+#define BIT_MASK_GTAB_ID_V1_8822C 0x7
+#define BIT_GTAB_ID_V1_8822C(x)                                                \
+	(((x) & BIT_MASK_GTAB_ID_V1_8822C) << BIT_SHIFT_GTAB_ID_V1_8822C)
+#define BITS_GTAB_ID_V1_8822C                                                  \
+	(BIT_MASK_GTAB_ID_V1_8822C << BIT_SHIFT_GTAB_ID_V1_8822C)
+#define BIT_CLEAR_GTAB_ID_V1_8822C(x) ((x) & (~BITS_GTAB_ID_V1_8822C))
+#define BIT_GET_GTAB_ID_V1_8822C(x)                                            \
+	(((x) >> BIT_SHIFT_GTAB_ID_V1_8822C) & BIT_MASK_GTAB_ID_V1_8822C)
+#define BIT_SET_GTAB_ID_V1_8822C(x, v)                                         \
+	(BIT_CLEAR_GTAB_ID_V1_8822C(x) | BIT_GTAB_ID_V1_8822C(v))
+
+#define BIT_SHIFT_AC2_PKT_INFO_8822C 0
+#define BIT_MASK_AC2_PKT_INFO_8822C 0xfff
+#define BIT_AC2_PKT_INFO_8822C(x)                                              \
+	(((x) & BIT_MASK_AC2_PKT_INFO_8822C) << BIT_SHIFT_AC2_PKT_INFO_8822C)
+#define BITS_AC2_PKT_INFO_8822C                                                \
+	(BIT_MASK_AC2_PKT_INFO_8822C << BIT_SHIFT_AC2_PKT_INFO_8822C)
+#define BIT_CLEAR_AC2_PKT_INFO_8822C(x) ((x) & (~BITS_AC2_PKT_INFO_8822C))
+#define BIT_GET_AC2_PKT_INFO_8822C(x)                                          \
+	(((x) >> BIT_SHIFT_AC2_PKT_INFO_8822C) & BIT_MASK_AC2_PKT_INFO_8822C)
+#define BIT_SET_AC2_PKT_INFO_8822C(x, v)                                       \
+	(BIT_CLEAR_AC2_PKT_INFO_8822C(x) | BIT_AC2_PKT_INFO_8822C(v))
+
+/* 2 REG_Q4_Q5_INFO_8822C */
+#define BIT_QUEUE_MACID_AC_NOT_THE_SAME_8822C BIT(31)
+
+#define BIT_SHIFT_GTAB_ID_8822C 28
+#define BIT_MASK_GTAB_ID_8822C 0x7
+#define BIT_GTAB_ID_8822C(x)                                                   \
+	(((x) & BIT_MASK_GTAB_ID_8822C) << BIT_SHIFT_GTAB_ID_8822C)
+#define BITS_GTAB_ID_8822C (BIT_MASK_GTAB_ID_8822C << BIT_SHIFT_GTAB_ID_8822C)
+#define BIT_CLEAR_GTAB_ID_8822C(x) ((x) & (~BITS_GTAB_ID_8822C))
+#define BIT_GET_GTAB_ID_8822C(x)                                               \
+	(((x) >> BIT_SHIFT_GTAB_ID_8822C) & BIT_MASK_GTAB_ID_8822C)
+#define BIT_SET_GTAB_ID_8822C(x, v)                                            \
+	(BIT_CLEAR_GTAB_ID_8822C(x) | BIT_GTAB_ID_8822C(v))
+
+#define BIT_SHIFT_AC5_PKT_INFO_8822C 16
+#define BIT_MASK_AC5_PKT_INFO_8822C 0xfff
+#define BIT_AC5_PKT_INFO_8822C(x)                                              \
+	(((x) & BIT_MASK_AC5_PKT_INFO_8822C) << BIT_SHIFT_AC5_PKT_INFO_8822C)
+#define BITS_AC5_PKT_INFO_8822C                                                \
+	(BIT_MASK_AC5_PKT_INFO_8822C << BIT_SHIFT_AC5_PKT_INFO_8822C)
+#define BIT_CLEAR_AC5_PKT_INFO_8822C(x) ((x) & (~BITS_AC5_PKT_INFO_8822C))
+#define BIT_GET_AC5_PKT_INFO_8822C(x)                                          \
+	(((x) >> BIT_SHIFT_AC5_PKT_INFO_8822C) & BIT_MASK_AC5_PKT_INFO_8822C)
+#define BIT_SET_AC5_PKT_INFO_8822C(x, v)                                       \
+	(BIT_CLEAR_AC5_PKT_INFO_8822C(x) | BIT_AC5_PKT_INFO_8822C(v))
+
+#define BIT_QUEUE_MACID_AC_NOT_THE_SAME_V1_8822C BIT(15)
+
+#define BIT_SHIFT_GTAB_ID_V1_8822C 12
+#define BIT_MASK_GTAB_ID_V1_8822C 0x7
+#define BIT_GTAB_ID_V1_8822C(x)                                                \
+	(((x) & BIT_MASK_GTAB_ID_V1_8822C) << BIT_SHIFT_GTAB_ID_V1_8822C)
+#define BITS_GTAB_ID_V1_8822C                                                  \
+	(BIT_MASK_GTAB_ID_V1_8822C << BIT_SHIFT_GTAB_ID_V1_8822C)
+#define BIT_CLEAR_GTAB_ID_V1_8822C(x) ((x) & (~BITS_GTAB_ID_V1_8822C))
+#define BIT_GET_GTAB_ID_V1_8822C(x)                                            \
+	(((x) >> BIT_SHIFT_GTAB_ID_V1_8822C) & BIT_MASK_GTAB_ID_V1_8822C)
+#define BIT_SET_GTAB_ID_V1_8822C(x, v)                                         \
+	(BIT_CLEAR_GTAB_ID_V1_8822C(x) | BIT_GTAB_ID_V1_8822C(v))
+
+#define BIT_SHIFT_AC4_PKT_INFO_8822C 0
+#define BIT_MASK_AC4_PKT_INFO_8822C 0xfff
+#define BIT_AC4_PKT_INFO_8822C(x)                                              \
+	(((x) & BIT_MASK_AC4_PKT_INFO_8822C) << BIT_SHIFT_AC4_PKT_INFO_8822C)
+#define BITS_AC4_PKT_INFO_8822C                                                \
+	(BIT_MASK_AC4_PKT_INFO_8822C << BIT_SHIFT_AC4_PKT_INFO_8822C)
+#define BIT_CLEAR_AC4_PKT_INFO_8822C(x) ((x) & (~BITS_AC4_PKT_INFO_8822C))
+#define BIT_GET_AC4_PKT_INFO_8822C(x)                                          \
+	(((x) >> BIT_SHIFT_AC4_PKT_INFO_8822C) & BIT_MASK_AC4_PKT_INFO_8822C)
+#define BIT_SET_AC4_PKT_INFO_8822C(x, v)                                       \
+	(BIT_CLEAR_AC4_PKT_INFO_8822C(x) | BIT_AC4_PKT_INFO_8822C(v))
+
+/* 2 REG_Q6_Q7_INFO_8822C */
+#define BIT_QUEUE_MACID_AC_NOT_THE_SAME_8822C BIT(31)
+
+#define BIT_SHIFT_GTAB_ID_8822C 28
+#define BIT_MASK_GTAB_ID_8822C 0x7
+#define BIT_GTAB_ID_8822C(x)                                                   \
+	(((x) & BIT_MASK_GTAB_ID_8822C) << BIT_SHIFT_GTAB_ID_8822C)
+#define BITS_GTAB_ID_8822C (BIT_MASK_GTAB_ID_8822C << BIT_SHIFT_GTAB_ID_8822C)
+#define BIT_CLEAR_GTAB_ID_8822C(x) ((x) & (~BITS_GTAB_ID_8822C))
+#define BIT_GET_GTAB_ID_8822C(x)                                               \
+	(((x) >> BIT_SHIFT_GTAB_ID_8822C) & BIT_MASK_GTAB_ID_8822C)
+#define BIT_SET_GTAB_ID_8822C(x, v)                                            \
+	(BIT_CLEAR_GTAB_ID_8822C(x) | BIT_GTAB_ID_8822C(v))
+
+#define BIT_SHIFT_AC7_PKT_INFO_8822C 16
+#define BIT_MASK_AC7_PKT_INFO_8822C 0xfff
+#define BIT_AC7_PKT_INFO_8822C(x)                                              \
+	(((x) & BIT_MASK_AC7_PKT_INFO_8822C) << BIT_SHIFT_AC7_PKT_INFO_8822C)
+#define BITS_AC7_PKT_INFO_8822C                                                \
+	(BIT_MASK_AC7_PKT_INFO_8822C << BIT_SHIFT_AC7_PKT_INFO_8822C)
+#define BIT_CLEAR_AC7_PKT_INFO_8822C(x) ((x) & (~BITS_AC7_PKT_INFO_8822C))
+#define BIT_GET_AC7_PKT_INFO_8822C(x)                                          \
+	(((x) >> BIT_SHIFT_AC7_PKT_INFO_8822C) & BIT_MASK_AC7_PKT_INFO_8822C)
+#define BIT_SET_AC7_PKT_INFO_8822C(x, v)                                       \
+	(BIT_CLEAR_AC7_PKT_INFO_8822C(x) | BIT_AC7_PKT_INFO_8822C(v))
+
+#define BIT_QUEUE_MACID_AC_NOT_THE_SAME_V1_8822C BIT(15)
+
+#define BIT_SHIFT_GTAB_ID_V1_8822C 12
+#define BIT_MASK_GTAB_ID_V1_8822C 0x7
+#define BIT_GTAB_ID_V1_8822C(x)                                                \
+	(((x) & BIT_MASK_GTAB_ID_V1_8822C) << BIT_SHIFT_GTAB_ID_V1_8822C)
+#define BITS_GTAB_ID_V1_8822C                                                  \
+	(BIT_MASK_GTAB_ID_V1_8822C << BIT_SHIFT_GTAB_ID_V1_8822C)
+#define BIT_CLEAR_GTAB_ID_V1_8822C(x) ((x) & (~BITS_GTAB_ID_V1_8822C))
+#define BIT_GET_GTAB_ID_V1_8822C(x)                                            \
+	(((x) >> BIT_SHIFT_GTAB_ID_V1_8822C) & BIT_MASK_GTAB_ID_V1_8822C)
+#define BIT_SET_GTAB_ID_V1_8822C(x, v)                                         \
+	(BIT_CLEAR_GTAB_ID_V1_8822C(x) | BIT_GTAB_ID_V1_8822C(v))
+
+#define BIT_SHIFT_AC6_PKT_INFO_8822C 0
+#define BIT_MASK_AC6_PKT_INFO_8822C 0xfff
+#define BIT_AC6_PKT_INFO_8822C(x)                                              \
+	(((x) & BIT_MASK_AC6_PKT_INFO_8822C) << BIT_SHIFT_AC6_PKT_INFO_8822C)
+#define BITS_AC6_PKT_INFO_8822C                                                \
+	(BIT_MASK_AC6_PKT_INFO_8822C << BIT_SHIFT_AC6_PKT_INFO_8822C)
+#define BIT_CLEAR_AC6_PKT_INFO_8822C(x) ((x) & (~BITS_AC6_PKT_INFO_8822C))
+#define BIT_GET_AC6_PKT_INFO_8822C(x)                                          \
+	(((x) >> BIT_SHIFT_AC6_PKT_INFO_8822C) & BIT_MASK_AC6_PKT_INFO_8822C)
+#define BIT_SET_AC6_PKT_INFO_8822C(x, v)                                       \
+	(BIT_CLEAR_AC6_PKT_INFO_8822C(x) | BIT_AC6_PKT_INFO_8822C(v))
+
+/* 2 REG_MGQ_HIQ_INFO_8822C */
+
+#define BIT_SHIFT_HIQ_PKT_INFO_8822C 16
+#define BIT_MASK_HIQ_PKT_INFO_8822C 0xfff
+#define BIT_HIQ_PKT_INFO_8822C(x)                                              \
+	(((x) & BIT_MASK_HIQ_PKT_INFO_8822C) << BIT_SHIFT_HIQ_PKT_INFO_8822C)
+#define BITS_HIQ_PKT_INFO_8822C                                                \
+	(BIT_MASK_HIQ_PKT_INFO_8822C << BIT_SHIFT_HIQ_PKT_INFO_8822C)
+#define BIT_CLEAR_HIQ_PKT_INFO_8822C(x) ((x) & (~BITS_HIQ_PKT_INFO_8822C))
+#define BIT_GET_HIQ_PKT_INFO_8822C(x)                                          \
+	(((x) >> BIT_SHIFT_HIQ_PKT_INFO_8822C) & BIT_MASK_HIQ_PKT_INFO_8822C)
+#define BIT_SET_HIQ_PKT_INFO_8822C(x, v)                                       \
+	(BIT_CLEAR_HIQ_PKT_INFO_8822C(x) | BIT_HIQ_PKT_INFO_8822C(v))
+
+#define BIT_SHIFT_MGQ_PKT_INFO_8822C 0
+#define BIT_MASK_MGQ_PKT_INFO_8822C 0xfff
+#define BIT_MGQ_PKT_INFO_8822C(x)                                              \
+	(((x) & BIT_MASK_MGQ_PKT_INFO_8822C) << BIT_SHIFT_MGQ_PKT_INFO_8822C)
+#define BITS_MGQ_PKT_INFO_8822C                                                \
+	(BIT_MASK_MGQ_PKT_INFO_8822C << BIT_SHIFT_MGQ_PKT_INFO_8822C)
+#define BIT_CLEAR_MGQ_PKT_INFO_8822C(x) ((x) & (~BITS_MGQ_PKT_INFO_8822C))
+#define BIT_GET_MGQ_PKT_INFO_8822C(x)                                          \
+	(((x) >> BIT_SHIFT_MGQ_PKT_INFO_8822C) & BIT_MASK_MGQ_PKT_INFO_8822C)
+#define BIT_SET_MGQ_PKT_INFO_8822C(x, v)                                       \
+	(BIT_CLEAR_MGQ_PKT_INFO_8822C(x) | BIT_MGQ_PKT_INFO_8822C(v))
+
+/* 2 REG_CMDQ_BCNQ_INFO_8822C */
+
+#define BIT_SHIFT_CMDQ_PKT_INFO_8822C 16
+#define BIT_MASK_CMDQ_PKT_INFO_8822C 0xfff
+#define BIT_CMDQ_PKT_INFO_8822C(x)                                             \
+	(((x) & BIT_MASK_CMDQ_PKT_INFO_8822C) << BIT_SHIFT_CMDQ_PKT_INFO_8822C)
+#define BITS_CMDQ_PKT_INFO_8822C                                               \
+	(BIT_MASK_CMDQ_PKT_INFO_8822C << BIT_SHIFT_CMDQ_PKT_INFO_8822C)
+#define BIT_CLEAR_CMDQ_PKT_INFO_8822C(x) ((x) & (~BITS_CMDQ_PKT_INFO_8822C))
+#define BIT_GET_CMDQ_PKT_INFO_8822C(x)                                         \
+	(((x) >> BIT_SHIFT_CMDQ_PKT_INFO_8822C) & BIT_MASK_CMDQ_PKT_INFO_8822C)
+#define BIT_SET_CMDQ_PKT_INFO_8822C(x, v)                                      \
+	(BIT_CLEAR_CMDQ_PKT_INFO_8822C(x) | BIT_CMDQ_PKT_INFO_8822C(v))
+
+#define BIT_SHIFT_BCNQ_PKT_INFO_8822C 0
+#define BIT_MASK_BCNQ_PKT_INFO_8822C 0xfff
+#define BIT_BCNQ_PKT_INFO_8822C(x)                                             \
+	(((x) & BIT_MASK_BCNQ_PKT_INFO_8822C) << BIT_SHIFT_BCNQ_PKT_INFO_8822C)
+#define BITS_BCNQ_PKT_INFO_8822C                                               \
+	(BIT_MASK_BCNQ_PKT_INFO_8822C << BIT_SHIFT_BCNQ_PKT_INFO_8822C)
+#define BIT_CLEAR_BCNQ_PKT_INFO_8822C(x) ((x) & (~BITS_BCNQ_PKT_INFO_8822C))
+#define BIT_GET_BCNQ_PKT_INFO_8822C(x)                                         \
+	(((x) >> BIT_SHIFT_BCNQ_PKT_INFO_8822C) & BIT_MASK_BCNQ_PKT_INFO_8822C)
+#define BIT_SET_BCNQ_PKT_INFO_8822C(x, v)                                      \
+	(BIT_CLEAR_BCNQ_PKT_INFO_8822C(x) | BIT_BCNQ_PKT_INFO_8822C(v))
+
+/* 2 REG_LOOPBACK_OPTION_8822C */
+#define BIT_LOOPACK_FAST_EDCA_EN_8822C BIT(24)
+
+/* 2 REG_AESIV_SETTING_8822C */
+
+#define BIT_SHIFT_AESIV_OFFSET_8822C 0
+#define BIT_MASK_AESIV_OFFSET_8822C 0xfff
+#define BIT_AESIV_OFFSET_8822C(x)                                              \
+	(((x) & BIT_MASK_AESIV_OFFSET_8822C) << BIT_SHIFT_AESIV_OFFSET_8822C)
+#define BITS_AESIV_OFFSET_8822C                                                \
+	(BIT_MASK_AESIV_OFFSET_8822C << BIT_SHIFT_AESIV_OFFSET_8822C)
+#define BIT_CLEAR_AESIV_OFFSET_8822C(x) ((x) & (~BITS_AESIV_OFFSET_8822C))
+#define BIT_GET_AESIV_OFFSET_8822C(x)                                          \
+	(((x) >> BIT_SHIFT_AESIV_OFFSET_8822C) & BIT_MASK_AESIV_OFFSET_8822C)
+#define BIT_SET_AESIV_OFFSET_8822C(x, v)                                       \
+	(BIT_CLEAR_AESIV_OFFSET_8822C(x) | BIT_AESIV_OFFSET_8822C(v))
+
+/* 2 REG_BF0_TIME_SETTING_8822C */
+#define BIT_BF0_TIMER_SET_8822C BIT(31)
+#define BIT_BF0_TIMER_CLR_8822C BIT(30)
+#define BIT_BF0_UPDATE_EN_8822C BIT(29)
+#define BIT_BF0_TIMER_EN_8822C BIT(28)
+
+#define BIT_SHIFT_BF0_PRETIME_OVER_8822C 16
+#define BIT_MASK_BF0_PRETIME_OVER_8822C 0xfff
+#define BIT_BF0_PRETIME_OVER_8822C(x)                                          \
+	(((x) & BIT_MASK_BF0_PRETIME_OVER_8822C)                               \
+	 << BIT_SHIFT_BF0_PRETIME_OVER_8822C)
+#define BITS_BF0_PRETIME_OVER_8822C                                            \
+	(BIT_MASK_BF0_PRETIME_OVER_8822C << BIT_SHIFT_BF0_PRETIME_OVER_8822C)
+#define BIT_CLEAR_BF0_PRETIME_OVER_8822C(x)                                    \
+	((x) & (~BITS_BF0_PRETIME_OVER_8822C))
+#define BIT_GET_BF0_PRETIME_OVER_8822C(x)                                      \
+	(((x) >> BIT_SHIFT_BF0_PRETIME_OVER_8822C) &                           \
+	 BIT_MASK_BF0_PRETIME_OVER_8822C)
+#define BIT_SET_BF0_PRETIME_OVER_8822C(x, v)                                   \
+	(BIT_CLEAR_BF0_PRETIME_OVER_8822C(x) | BIT_BF0_PRETIME_OVER_8822C(v))
+
+#define BIT_SHIFT_BF0_LIFETIME_8822C 0
+#define BIT_MASK_BF0_LIFETIME_8822C 0xffff
+#define BIT_BF0_LIFETIME_8822C(x)                                              \
+	(((x) & BIT_MASK_BF0_LIFETIME_8822C) << BIT_SHIFT_BF0_LIFETIME_8822C)
+#define BITS_BF0_LIFETIME_8822C                                                \
+	(BIT_MASK_BF0_LIFETIME_8822C << BIT_SHIFT_BF0_LIFETIME_8822C)
+#define BIT_CLEAR_BF0_LIFETIME_8822C(x) ((x) & (~BITS_BF0_LIFETIME_8822C))
+#define BIT_GET_BF0_LIFETIME_8822C(x)                                          \
+	(((x) >> BIT_SHIFT_BF0_LIFETIME_8822C) & BIT_MASK_BF0_LIFETIME_8822C)
+#define BIT_SET_BF0_LIFETIME_8822C(x, v)                                       \
+	(BIT_CLEAR_BF0_LIFETIME_8822C(x) | BIT_BF0_LIFETIME_8822C(v))
+
+/* 2 REG_BF1_TIME_SETTING_8822C */
+#define BIT_BF1_TIMER_SET_8822C BIT(31)
+#define BIT_BF1_TIMER_CLR_8822C BIT(30)
+#define BIT_BF1_UPDATE_EN_8822C BIT(29)
+#define BIT_BF1_TIMER_EN_8822C BIT(28)
+
+#define BIT_SHIFT_BF1_PRETIME_OVER_8822C 16
+#define BIT_MASK_BF1_PRETIME_OVER_8822C 0xfff
+#define BIT_BF1_PRETIME_OVER_8822C(x)                                          \
+	(((x) & BIT_MASK_BF1_PRETIME_OVER_8822C)                               \
+	 << BIT_SHIFT_BF1_PRETIME_OVER_8822C)
+#define BITS_BF1_PRETIME_OVER_8822C                                            \
+	(BIT_MASK_BF1_PRETIME_OVER_8822C << BIT_SHIFT_BF1_PRETIME_OVER_8822C)
+#define BIT_CLEAR_BF1_PRETIME_OVER_8822C(x)                                    \
+	((x) & (~BITS_BF1_PRETIME_OVER_8822C))
+#define BIT_GET_BF1_PRETIME_OVER_8822C(x)                                      \
+	(((x) >> BIT_SHIFT_BF1_PRETIME_OVER_8822C) &                           \
+	 BIT_MASK_BF1_PRETIME_OVER_8822C)
+#define BIT_SET_BF1_PRETIME_OVER_8822C(x, v)                                   \
+	(BIT_CLEAR_BF1_PRETIME_OVER_8822C(x) | BIT_BF1_PRETIME_OVER_8822C(v))
+
+#define BIT_SHIFT_BF1_LIFETIME_8822C 0
+#define BIT_MASK_BF1_LIFETIME_8822C 0xffff
+#define BIT_BF1_LIFETIME_8822C(x)                                              \
+	(((x) & BIT_MASK_BF1_LIFETIME_8822C) << BIT_SHIFT_BF1_LIFETIME_8822C)
+#define BITS_BF1_LIFETIME_8822C                                                \
+	(BIT_MASK_BF1_LIFETIME_8822C << BIT_SHIFT_BF1_LIFETIME_8822C)
+#define BIT_CLEAR_BF1_LIFETIME_8822C(x) ((x) & (~BITS_BF1_LIFETIME_8822C))
+#define BIT_GET_BF1_LIFETIME_8822C(x)                                          \
+	(((x) >> BIT_SHIFT_BF1_LIFETIME_8822C) & BIT_MASK_BF1_LIFETIME_8822C)
+#define BIT_SET_BF1_LIFETIME_8822C(x, v)                                       \
+	(BIT_CLEAR_BF1_LIFETIME_8822C(x) | BIT_BF1_LIFETIME_8822C(v))
+
+/* 2 REG_BF_TIMEOUT_EN_8822C */
+#define BIT_EN_VHT_LDPC_8822C BIT(9)
+#define BIT_EN_HT_LDPC_8822C BIT(8)
+#define BIT_BF1_TIMEOUT_EN_8822C BIT(1)
+#define BIT_BF0_TIMEOUT_EN_8822C BIT(0)
+
+/* 2 REG_MACID_RELEASE0_8822C */
+
+#define BIT_SHIFT_MACID31_0_RELEASE_8822C 0
+#define BIT_MASK_MACID31_0_RELEASE_8822C 0xffffffffL
+#define BIT_MACID31_0_RELEASE_8822C(x)                                         \
+	(((x) & BIT_MASK_MACID31_0_RELEASE_8822C)                              \
+	 << BIT_SHIFT_MACID31_0_RELEASE_8822C)
+#define BITS_MACID31_0_RELEASE_8822C                                           \
+	(BIT_MASK_MACID31_0_RELEASE_8822C << BIT_SHIFT_MACID31_0_RELEASE_8822C)
+#define BIT_CLEAR_MACID31_0_RELEASE_8822C(x)                                   \
+	((x) & (~BITS_MACID31_0_RELEASE_8822C))
+#define BIT_GET_MACID31_0_RELEASE_8822C(x)                                     \
+	(((x) >> BIT_SHIFT_MACID31_0_RELEASE_8822C) &                          \
+	 BIT_MASK_MACID31_0_RELEASE_8822C)
+#define BIT_SET_MACID31_0_RELEASE_8822C(x, v)                                  \
+	(BIT_CLEAR_MACID31_0_RELEASE_8822C(x) | BIT_MACID31_0_RELEASE_8822C(v))
+
+/* 2 REG_MACID_RELEASE1_8822C */
+
+#define BIT_SHIFT_MACID63_32_RELEASE_8822C 0
+#define BIT_MASK_MACID63_32_RELEASE_8822C 0xffffffffL
+#define BIT_MACID63_32_RELEASE_8822C(x)                                        \
+	(((x) & BIT_MASK_MACID63_32_RELEASE_8822C)                             \
+	 << BIT_SHIFT_MACID63_32_RELEASE_8822C)
+#define BITS_MACID63_32_RELEASE_8822C                                          \
+	(BIT_MASK_MACID63_32_RELEASE_8822C                                     \
+	 << BIT_SHIFT_MACID63_32_RELEASE_8822C)
+#define BIT_CLEAR_MACID63_32_RELEASE_8822C(x)                                  \
+	((x) & (~BITS_MACID63_32_RELEASE_8822C))
+#define BIT_GET_MACID63_32_RELEASE_8822C(x)                                    \
+	(((x) >> BIT_SHIFT_MACID63_32_RELEASE_8822C) &                         \
+	 BIT_MASK_MACID63_32_RELEASE_8822C)
+#define BIT_SET_MACID63_32_RELEASE_8822C(x, v)                                 \
+	(BIT_CLEAR_MACID63_32_RELEASE_8822C(x) |                               \
+	 BIT_MACID63_32_RELEASE_8822C(v))
+
+/* 2 REG_MACID_RELEASE2_8822C */
+
+#define BIT_SHIFT_MACID95_64_RELEASE_8822C 0
+#define BIT_MASK_MACID95_64_RELEASE_8822C 0xffffffffL
+#define BIT_MACID95_64_RELEASE_8822C(x)                                        \
+	(((x) & BIT_MASK_MACID95_64_RELEASE_8822C)                             \
+	 << BIT_SHIFT_MACID95_64_RELEASE_8822C)
+#define BITS_MACID95_64_RELEASE_8822C                                          \
+	(BIT_MASK_MACID95_64_RELEASE_8822C                                     \
+	 << BIT_SHIFT_MACID95_64_RELEASE_8822C)
+#define BIT_CLEAR_MACID95_64_RELEASE_8822C(x)                                  \
+	((x) & (~BITS_MACID95_64_RELEASE_8822C))
+#define BIT_GET_MACID95_64_RELEASE_8822C(x)                                    \
+	(((x) >> BIT_SHIFT_MACID95_64_RELEASE_8822C) &                         \
+	 BIT_MASK_MACID95_64_RELEASE_8822C)
+#define BIT_SET_MACID95_64_RELEASE_8822C(x, v)                                 \
+	(BIT_CLEAR_MACID95_64_RELEASE_8822C(x) |                               \
+	 BIT_MACID95_64_RELEASE_8822C(v))
+
+/* 2 REG_MACID_RELEASE3_8822C */
+
+#define BIT_SHIFT_MACID127_96_RELEASE_8822C 0
+#define BIT_MASK_MACID127_96_RELEASE_8822C 0xffffffffL
+#define BIT_MACID127_96_RELEASE_8822C(x)                                       \
+	(((x) & BIT_MASK_MACID127_96_RELEASE_8822C)                            \
+	 << BIT_SHIFT_MACID127_96_RELEASE_8822C)
+#define BITS_MACID127_96_RELEASE_8822C                                         \
+	(BIT_MASK_MACID127_96_RELEASE_8822C                                    \
+	 << BIT_SHIFT_MACID127_96_RELEASE_8822C)
+#define BIT_CLEAR_MACID127_96_RELEASE_8822C(x)                                 \
+	((x) & (~BITS_MACID127_96_RELEASE_8822C))
+#define BIT_GET_MACID127_96_RELEASE_8822C(x)                                   \
+	(((x) >> BIT_SHIFT_MACID127_96_RELEASE_8822C) &                        \
+	 BIT_MASK_MACID127_96_RELEASE_8822C)
+#define BIT_SET_MACID127_96_RELEASE_8822C(x, v)                                \
+	(BIT_CLEAR_MACID127_96_RELEASE_8822C(x) |                              \
+	 BIT_MACID127_96_RELEASE_8822C(v))
+
+/* 2 REG_MACID_RELEASE_SETTING_8822C */
+#define BIT_MACID_VALUE_8822C BIT(7)
+
+#define BIT_SHIFT_MACID_OFFSET_8822C 0
+#define BIT_MASK_MACID_OFFSET_8822C 0x7f
+#define BIT_MACID_OFFSET_8822C(x)                                              \
+	(((x) & BIT_MASK_MACID_OFFSET_8822C) << BIT_SHIFT_MACID_OFFSET_8822C)
+#define BITS_MACID_OFFSET_8822C                                                \
+	(BIT_MASK_MACID_OFFSET_8822C << BIT_SHIFT_MACID_OFFSET_8822C)
+#define BIT_CLEAR_MACID_OFFSET_8822C(x) ((x) & (~BITS_MACID_OFFSET_8822C))
+#define BIT_GET_MACID_OFFSET_8822C(x)                                          \
+	(((x) >> BIT_SHIFT_MACID_OFFSET_8822C) & BIT_MASK_MACID_OFFSET_8822C)
+#define BIT_SET_MACID_OFFSET_8822C(x, v)                                       \
+	(BIT_CLEAR_MACID_OFFSET_8822C(x) | BIT_MACID_OFFSET_8822C(v))
+
+/* 2 REG_FAST_EDCA_VOVI_SETTING_8822C */
+
+#define BIT_SHIFT_VI_FAST_EDCA_TO_8822C 24
+#define BIT_MASK_VI_FAST_EDCA_TO_8822C 0xff
+#define BIT_VI_FAST_EDCA_TO_8822C(x)                                           \
+	(((x) & BIT_MASK_VI_FAST_EDCA_TO_8822C)                                \
+	 << BIT_SHIFT_VI_FAST_EDCA_TO_8822C)
+#define BITS_VI_FAST_EDCA_TO_8822C                                             \
+	(BIT_MASK_VI_FAST_EDCA_TO_8822C << BIT_SHIFT_VI_FAST_EDCA_TO_8822C)
+#define BIT_CLEAR_VI_FAST_EDCA_TO_8822C(x) ((x) & (~BITS_VI_FAST_EDCA_TO_8822C))
+#define BIT_GET_VI_FAST_EDCA_TO_8822C(x)                                       \
+	(((x) >> BIT_SHIFT_VI_FAST_EDCA_TO_8822C) &                            \
+	 BIT_MASK_VI_FAST_EDCA_TO_8822C)
+#define BIT_SET_VI_FAST_EDCA_TO_8822C(x, v)                                    \
+	(BIT_CLEAR_VI_FAST_EDCA_TO_8822C(x) | BIT_VI_FAST_EDCA_TO_8822C(v))
+
+#define BIT_VI_THRESHOLD_SEL_8822C BIT(23)
+
+#define BIT_SHIFT_VI_FAST_EDCA_PKT_TH_8822C 16
+#define BIT_MASK_VI_FAST_EDCA_PKT_TH_8822C 0x7f
+#define BIT_VI_FAST_EDCA_PKT_TH_8822C(x)                                       \
+	(((x) & BIT_MASK_VI_FAST_EDCA_PKT_TH_8822C)                            \
+	 << BIT_SHIFT_VI_FAST_EDCA_PKT_TH_8822C)
+#define BITS_VI_FAST_EDCA_PKT_TH_8822C                                         \
+	(BIT_MASK_VI_FAST_EDCA_PKT_TH_8822C                                    \
+	 << BIT_SHIFT_VI_FAST_EDCA_PKT_TH_8822C)
+#define BIT_CLEAR_VI_FAST_EDCA_PKT_TH_8822C(x)                                 \
+	((x) & (~BITS_VI_FAST_EDCA_PKT_TH_8822C))
+#define BIT_GET_VI_FAST_EDCA_PKT_TH_8822C(x)                                   \
+	(((x) >> BIT_SHIFT_VI_FAST_EDCA_PKT_TH_8822C) &                        \
+	 BIT_MASK_VI_FAST_EDCA_PKT_TH_8822C)
+#define BIT_SET_VI_FAST_EDCA_PKT_TH_8822C(x, v)                                \
+	(BIT_CLEAR_VI_FAST_EDCA_PKT_TH_8822C(x) |                              \
+	 BIT_VI_FAST_EDCA_PKT_TH_8822C(v))
+
+#define BIT_SHIFT_VO_FAST_EDCA_TO_8822C 8
+#define BIT_MASK_VO_FAST_EDCA_TO_8822C 0xff
+#define BIT_VO_FAST_EDCA_TO_8822C(x)                                           \
+	(((x) & BIT_MASK_VO_FAST_EDCA_TO_8822C)                                \
+	 << BIT_SHIFT_VO_FAST_EDCA_TO_8822C)
+#define BITS_VO_FAST_EDCA_TO_8822C                                             \
+	(BIT_MASK_VO_FAST_EDCA_TO_8822C << BIT_SHIFT_VO_FAST_EDCA_TO_8822C)
+#define BIT_CLEAR_VO_FAST_EDCA_TO_8822C(x) ((x) & (~BITS_VO_FAST_EDCA_TO_8822C))
+#define BIT_GET_VO_FAST_EDCA_TO_8822C(x)                                       \
+	(((x) >> BIT_SHIFT_VO_FAST_EDCA_TO_8822C) &                            \
+	 BIT_MASK_VO_FAST_EDCA_TO_8822C)
+#define BIT_SET_VO_FAST_EDCA_TO_8822C(x, v)                                    \
+	(BIT_CLEAR_VO_FAST_EDCA_TO_8822C(x) | BIT_VO_FAST_EDCA_TO_8822C(v))
+
+#define BIT_VO_THRESHOLD_SEL_8822C BIT(7)
+
+#define BIT_SHIFT_VO_FAST_EDCA_PKT_TH_8822C 0
+#define BIT_MASK_VO_FAST_EDCA_PKT_TH_8822C 0x7f
+#define BIT_VO_FAST_EDCA_PKT_TH_8822C(x)                                       \
+	(((x) & BIT_MASK_VO_FAST_EDCA_PKT_TH_8822C)                            \
+	 << BIT_SHIFT_VO_FAST_EDCA_PKT_TH_8822C)
+#define BITS_VO_FAST_EDCA_PKT_TH_8822C                                         \
+	(BIT_MASK_VO_FAST_EDCA_PKT_TH_8822C                                    \
+	 << BIT_SHIFT_VO_FAST_EDCA_PKT_TH_8822C)
+#define BIT_CLEAR_VO_FAST_EDCA_PKT_TH_8822C(x)                                 \
+	((x) & (~BITS_VO_FAST_EDCA_PKT_TH_8822C))
+#define BIT_GET_VO_FAST_EDCA_PKT_TH_8822C(x)                                   \
+	(((x) >> BIT_SHIFT_VO_FAST_EDCA_PKT_TH_8822C) &                        \
+	 BIT_MASK_VO_FAST_EDCA_PKT_TH_8822C)
+#define BIT_SET_VO_FAST_EDCA_PKT_TH_8822C(x, v)                                \
+	(BIT_CLEAR_VO_FAST_EDCA_PKT_TH_8822C(x) |                              \
+	 BIT_VO_FAST_EDCA_PKT_TH_8822C(v))
+
+/* 2 REG_FAST_EDCA_BEBK_SETTING_8822C */
+
+#define BIT_SHIFT_BK_FAST_EDCA_TO_8822C 24
+#define BIT_MASK_BK_FAST_EDCA_TO_8822C 0xff
+#define BIT_BK_FAST_EDCA_TO_8822C(x)                                           \
+	(((x) & BIT_MASK_BK_FAST_EDCA_TO_8822C)                                \
+	 << BIT_SHIFT_BK_FAST_EDCA_TO_8822C)
+#define BITS_BK_FAST_EDCA_TO_8822C                                             \
+	(BIT_MASK_BK_FAST_EDCA_TO_8822C << BIT_SHIFT_BK_FAST_EDCA_TO_8822C)
+#define BIT_CLEAR_BK_FAST_EDCA_TO_8822C(x) ((x) & (~BITS_BK_FAST_EDCA_TO_8822C))
+#define BIT_GET_BK_FAST_EDCA_TO_8822C(x)                                       \
+	(((x) >> BIT_SHIFT_BK_FAST_EDCA_TO_8822C) &                            \
+	 BIT_MASK_BK_FAST_EDCA_TO_8822C)
+#define BIT_SET_BK_FAST_EDCA_TO_8822C(x, v)                                    \
+	(BIT_CLEAR_BK_FAST_EDCA_TO_8822C(x) | BIT_BK_FAST_EDCA_TO_8822C(v))
+
+#define BIT_BK_THRESHOLD_SEL_8822C BIT(23)
+
+#define BIT_SHIFT_BK_FAST_EDCA_PKT_TH_8822C 16
+#define BIT_MASK_BK_FAST_EDCA_PKT_TH_8822C 0x7f
+#define BIT_BK_FAST_EDCA_PKT_TH_8822C(x)                                       \
+	(((x) & BIT_MASK_BK_FAST_EDCA_PKT_TH_8822C)                            \
+	 << BIT_SHIFT_BK_FAST_EDCA_PKT_TH_8822C)
+#define BITS_BK_FAST_EDCA_PKT_TH_8822C                                         \
+	(BIT_MASK_BK_FAST_EDCA_PKT_TH_8822C                                    \
+	 << BIT_SHIFT_BK_FAST_EDCA_PKT_TH_8822C)
+#define BIT_CLEAR_BK_FAST_EDCA_PKT_TH_8822C(x)                                 \
+	((x) & (~BITS_BK_FAST_EDCA_PKT_TH_8822C))
+#define BIT_GET_BK_FAST_EDCA_PKT_TH_8822C(x)                                   \
+	(((x) >> BIT_SHIFT_BK_FAST_EDCA_PKT_TH_8822C) &                        \
+	 BIT_MASK_BK_FAST_EDCA_PKT_TH_8822C)
+#define BIT_SET_BK_FAST_EDCA_PKT_TH_8822C(x, v)                                \
+	(BIT_CLEAR_BK_FAST_EDCA_PKT_TH_8822C(x) |                              \
+	 BIT_BK_FAST_EDCA_PKT_TH_8822C(v))
+
+#define BIT_SHIFT_BE_FAST_EDCA_TO_8822C 8
+#define BIT_MASK_BE_FAST_EDCA_TO_8822C 0xff
+#define BIT_BE_FAST_EDCA_TO_8822C(x)                                           \
+	(((x) & BIT_MASK_BE_FAST_EDCA_TO_8822C)                                \
+	 << BIT_SHIFT_BE_FAST_EDCA_TO_8822C)
+#define BITS_BE_FAST_EDCA_TO_8822C                                             \
+	(BIT_MASK_BE_FAST_EDCA_TO_8822C << BIT_SHIFT_BE_FAST_EDCA_TO_8822C)
+#define BIT_CLEAR_BE_FAST_EDCA_TO_8822C(x) ((x) & (~BITS_BE_FAST_EDCA_TO_8822C))
+#define BIT_GET_BE_FAST_EDCA_TO_8822C(x)                                       \
+	(((x) >> BIT_SHIFT_BE_FAST_EDCA_TO_8822C) &                            \
+	 BIT_MASK_BE_FAST_EDCA_TO_8822C)
+#define BIT_SET_BE_FAST_EDCA_TO_8822C(x, v)                                    \
+	(BIT_CLEAR_BE_FAST_EDCA_TO_8822C(x) | BIT_BE_FAST_EDCA_TO_8822C(v))
+
+#define BIT_BE_THRESHOLD_SEL_8822C BIT(7)
+
+#define BIT_SHIFT_BE_FAST_EDCA_PKT_TH_8822C 0
+#define BIT_MASK_BE_FAST_EDCA_PKT_TH_8822C 0x7f
+#define BIT_BE_FAST_EDCA_PKT_TH_8822C(x)                                       \
+	(((x) & BIT_MASK_BE_FAST_EDCA_PKT_TH_8822C)                            \
+	 << BIT_SHIFT_BE_FAST_EDCA_PKT_TH_8822C)
+#define BITS_BE_FAST_EDCA_PKT_TH_8822C                                         \
+	(BIT_MASK_BE_FAST_EDCA_PKT_TH_8822C                                    \
+	 << BIT_SHIFT_BE_FAST_EDCA_PKT_TH_8822C)
+#define BIT_CLEAR_BE_FAST_EDCA_PKT_TH_8822C(x)                                 \
+	((x) & (~BITS_BE_FAST_EDCA_PKT_TH_8822C))
+#define BIT_GET_BE_FAST_EDCA_PKT_TH_8822C(x)                                   \
+	(((x) >> BIT_SHIFT_BE_FAST_EDCA_PKT_TH_8822C) &                        \
+	 BIT_MASK_BE_FAST_EDCA_PKT_TH_8822C)
+#define BIT_SET_BE_FAST_EDCA_PKT_TH_8822C(x, v)                                \
+	(BIT_CLEAR_BE_FAST_EDCA_PKT_TH_8822C(x) |                              \
+	 BIT_BE_FAST_EDCA_PKT_TH_8822C(v))
+
+/* 2 REG_MACID_DROP0_8822C */
+
+#define BIT_SHIFT_MACID31_0_DROP_8822C 0
+#define BIT_MASK_MACID31_0_DROP_8822C 0xffffffffL
+#define BIT_MACID31_0_DROP_8822C(x)                                            \
+	(((x) & BIT_MASK_MACID31_0_DROP_8822C)                                 \
+	 << BIT_SHIFT_MACID31_0_DROP_8822C)
+#define BITS_MACID31_0_DROP_8822C                                              \
+	(BIT_MASK_MACID31_0_DROP_8822C << BIT_SHIFT_MACID31_0_DROP_8822C)
+#define BIT_CLEAR_MACID31_0_DROP_8822C(x) ((x) & (~BITS_MACID31_0_DROP_8822C))
+#define BIT_GET_MACID31_0_DROP_8822C(x)                                        \
+	(((x) >> BIT_SHIFT_MACID31_0_DROP_8822C) &                             \
+	 BIT_MASK_MACID31_0_DROP_8822C)
+#define BIT_SET_MACID31_0_DROP_8822C(x, v)                                     \
+	(BIT_CLEAR_MACID31_0_DROP_8822C(x) | BIT_MACID31_0_DROP_8822C(v))
+
+/* 2 REG_MACID_DROP1_8822C */
+
+#define BIT_SHIFT_MACID63_32_DROP_8822C 0
+#define BIT_MASK_MACID63_32_DROP_8822C 0xffffffffL
+#define BIT_MACID63_32_DROP_8822C(x)                                           \
+	(((x) & BIT_MASK_MACID63_32_DROP_8822C)                                \
+	 << BIT_SHIFT_MACID63_32_DROP_8822C)
+#define BITS_MACID63_32_DROP_8822C                                             \
+	(BIT_MASK_MACID63_32_DROP_8822C << BIT_SHIFT_MACID63_32_DROP_8822C)
+#define BIT_CLEAR_MACID63_32_DROP_8822C(x) ((x) & (~BITS_MACID63_32_DROP_8822C))
+#define BIT_GET_MACID63_32_DROP_8822C(x)                                       \
+	(((x) >> BIT_SHIFT_MACID63_32_DROP_8822C) &                            \
+	 BIT_MASK_MACID63_32_DROP_8822C)
+#define BIT_SET_MACID63_32_DROP_8822C(x, v)                                    \
+	(BIT_CLEAR_MACID63_32_DROP_8822C(x) | BIT_MACID63_32_DROP_8822C(v))
+
+/* 2 REG_MACID_DROP2_8822C */
+
+#define BIT_SHIFT_MACID95_64_DROP_8822C 0
+#define BIT_MASK_MACID95_64_DROP_8822C 0xffffffffL
+#define BIT_MACID95_64_DROP_8822C(x)                                           \
+	(((x) & BIT_MASK_MACID95_64_DROP_8822C)                                \
+	 << BIT_SHIFT_MACID95_64_DROP_8822C)
+#define BITS_MACID95_64_DROP_8822C                                             \
+	(BIT_MASK_MACID95_64_DROP_8822C << BIT_SHIFT_MACID95_64_DROP_8822C)
+#define BIT_CLEAR_MACID95_64_DROP_8822C(x) ((x) & (~BITS_MACID95_64_DROP_8822C))
+#define BIT_GET_MACID95_64_DROP_8822C(x)                                       \
+	(((x) >> BIT_SHIFT_MACID95_64_DROP_8822C) &                            \
+	 BIT_MASK_MACID95_64_DROP_8822C)
+#define BIT_SET_MACID95_64_DROP_8822C(x, v)                                    \
+	(BIT_CLEAR_MACID95_64_DROP_8822C(x) | BIT_MACID95_64_DROP_8822C(v))
+
+/* 2 REG_MACID_DROP3_8822C */
+
+#define BIT_SHIFT_MACID127_96_DROP_8822C 0
+#define BIT_MASK_MACID127_96_DROP_8822C 0xffffffffL
+#define BIT_MACID127_96_DROP_8822C(x)                                          \
+	(((x) & BIT_MASK_MACID127_96_DROP_8822C)                               \
+	 << BIT_SHIFT_MACID127_96_DROP_8822C)
+#define BITS_MACID127_96_DROP_8822C                                            \
+	(BIT_MASK_MACID127_96_DROP_8822C << BIT_SHIFT_MACID127_96_DROP_8822C)
+#define BIT_CLEAR_MACID127_96_DROP_8822C(x)                                    \
+	((x) & (~BITS_MACID127_96_DROP_8822C))
+#define BIT_GET_MACID127_96_DROP_8822C(x)                                      \
+	(((x) >> BIT_SHIFT_MACID127_96_DROP_8822C) &                           \
+	 BIT_MASK_MACID127_96_DROP_8822C)
+#define BIT_SET_MACID127_96_DROP_8822C(x, v)                                   \
+	(BIT_CLEAR_MACID127_96_DROP_8822C(x) | BIT_MACID127_96_DROP_8822C(v))
+
+/* 2 REG_R_MACID_RELEASE_SUCCESS_0_8822C */
+
+#define BIT_SHIFT_R_MACID_RELEASE_SUCCESS_0_8822C 0
+#define BIT_MASK_R_MACID_RELEASE_SUCCESS_0_8822C 0xffffffffL
+#define BIT_R_MACID_RELEASE_SUCCESS_0_8822C(x)                                 \
+	(((x) & BIT_MASK_R_MACID_RELEASE_SUCCESS_0_8822C)                      \
+	 << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_0_8822C)
+#define BITS_R_MACID_RELEASE_SUCCESS_0_8822C                                   \
+	(BIT_MASK_R_MACID_RELEASE_SUCCESS_0_8822C                              \
+	 << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_0_8822C)
+#define BIT_CLEAR_R_MACID_RELEASE_SUCCESS_0_8822C(x)                           \
+	((x) & (~BITS_R_MACID_RELEASE_SUCCESS_0_8822C))
+#define BIT_GET_R_MACID_RELEASE_SUCCESS_0_8822C(x)                             \
+	(((x) >> BIT_SHIFT_R_MACID_RELEASE_SUCCESS_0_8822C) &                  \
+	 BIT_MASK_R_MACID_RELEASE_SUCCESS_0_8822C)
+#define BIT_SET_R_MACID_RELEASE_SUCCESS_0_8822C(x, v)                          \
+	(BIT_CLEAR_R_MACID_RELEASE_SUCCESS_0_8822C(x) |                        \
+	 BIT_R_MACID_RELEASE_SUCCESS_0_8822C(v))
+
+/* 2 REG_R_MACID_RELEASE_SUCCESS_1_8822C */
+
+#define BIT_SHIFT_R_MACID_RELEASE_SUCCESS_1_8822C 0
+#define BIT_MASK_R_MACID_RELEASE_SUCCESS_1_8822C 0xffffffffL
+#define BIT_R_MACID_RELEASE_SUCCESS_1_8822C(x)                                 \
+	(((x) & BIT_MASK_R_MACID_RELEASE_SUCCESS_1_8822C)                      \
+	 << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_1_8822C)
+#define BITS_R_MACID_RELEASE_SUCCESS_1_8822C                                   \
+	(BIT_MASK_R_MACID_RELEASE_SUCCESS_1_8822C                              \
+	 << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_1_8822C)
+#define BIT_CLEAR_R_MACID_RELEASE_SUCCESS_1_8822C(x)                           \
+	((x) & (~BITS_R_MACID_RELEASE_SUCCESS_1_8822C))
+#define BIT_GET_R_MACID_RELEASE_SUCCESS_1_8822C(x)                             \
+	(((x) >> BIT_SHIFT_R_MACID_RELEASE_SUCCESS_1_8822C) &                  \
+	 BIT_MASK_R_MACID_RELEASE_SUCCESS_1_8822C)
+#define BIT_SET_R_MACID_RELEASE_SUCCESS_1_8822C(x, v)                          \
+	(BIT_CLEAR_R_MACID_RELEASE_SUCCESS_1_8822C(x) |                        \
+	 BIT_R_MACID_RELEASE_SUCCESS_1_8822C(v))
+
+/* 2 REG_R_MACID_RELEASE_SUCCESS_2_8822C */
+
+#define BIT_SHIFT_R_MACID_RELEASE_SUCCESS_2_8822C 0
+#define BIT_MASK_R_MACID_RELEASE_SUCCESS_2_8822C 0xffffffffL
+#define BIT_R_MACID_RELEASE_SUCCESS_2_8822C(x)                                 \
+	(((x) & BIT_MASK_R_MACID_RELEASE_SUCCESS_2_8822C)                      \
+	 << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_2_8822C)
+#define BITS_R_MACID_RELEASE_SUCCESS_2_8822C                                   \
+	(BIT_MASK_R_MACID_RELEASE_SUCCESS_2_8822C                              \
+	 << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_2_8822C)
+#define BIT_CLEAR_R_MACID_RELEASE_SUCCESS_2_8822C(x)                           \
+	((x) & (~BITS_R_MACID_RELEASE_SUCCESS_2_8822C))
+#define BIT_GET_R_MACID_RELEASE_SUCCESS_2_8822C(x)                             \
+	(((x) >> BIT_SHIFT_R_MACID_RELEASE_SUCCESS_2_8822C) &                  \
+	 BIT_MASK_R_MACID_RELEASE_SUCCESS_2_8822C)
+#define BIT_SET_R_MACID_RELEASE_SUCCESS_2_8822C(x, v)                          \
+	(BIT_CLEAR_R_MACID_RELEASE_SUCCESS_2_8822C(x) |                        \
+	 BIT_R_MACID_RELEASE_SUCCESS_2_8822C(v))
+
+/* 2 REG_R_MACID_RELEASE_SUCCESS_3_8822C */
+
+#define BIT_SHIFT_R_MACID_RELEASE_SUCCESS_3_8822C 0
+#define BIT_MASK_R_MACID_RELEASE_SUCCESS_3_8822C 0xffffffffL
+#define BIT_R_MACID_RELEASE_SUCCESS_3_8822C(x)                                 \
+	(((x) & BIT_MASK_R_MACID_RELEASE_SUCCESS_3_8822C)                      \
+	 << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_3_8822C)
+#define BITS_R_MACID_RELEASE_SUCCESS_3_8822C                                   \
+	(BIT_MASK_R_MACID_RELEASE_SUCCESS_3_8822C                              \
+	 << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_3_8822C)
+#define BIT_CLEAR_R_MACID_RELEASE_SUCCESS_3_8822C(x)                           \
+	((x) & (~BITS_R_MACID_RELEASE_SUCCESS_3_8822C))
+#define BIT_GET_R_MACID_RELEASE_SUCCESS_3_8822C(x)                             \
+	(((x) >> BIT_SHIFT_R_MACID_RELEASE_SUCCESS_3_8822C) &                  \
+	 BIT_MASK_R_MACID_RELEASE_SUCCESS_3_8822C)
+#define BIT_SET_R_MACID_RELEASE_SUCCESS_3_8822C(x, v)                          \
+	(BIT_CLEAR_R_MACID_RELEASE_SUCCESS_3_8822C(x) |                        \
+	 BIT_R_MACID_RELEASE_SUCCESS_3_8822C(v))
+
+/* 2 REG_MGQ_FIFO_WRITE_POINTER_8822C */
+#define BIT_MGQ_FIFO_OV_8822C BIT(7)
+#define BIT_MGQ_FIFO_WPTR_ERROR_8822C BIT(6)
+#define BIT_EN_MGQ_FIFO_LIFETIME_8822C BIT(5)
+
+#define BIT_SHIFT_MGQ_FIFO_WPTR_8822C 0
+#define BIT_MASK_MGQ_FIFO_WPTR_8822C 0x1f
+#define BIT_MGQ_FIFO_WPTR_8822C(x)                                             \
+	(((x) & BIT_MASK_MGQ_FIFO_WPTR_8822C) << BIT_SHIFT_MGQ_FIFO_WPTR_8822C)
+#define BITS_MGQ_FIFO_WPTR_8822C                                               \
+	(BIT_MASK_MGQ_FIFO_WPTR_8822C << BIT_SHIFT_MGQ_FIFO_WPTR_8822C)
+#define BIT_CLEAR_MGQ_FIFO_WPTR_8822C(x) ((x) & (~BITS_MGQ_FIFO_WPTR_8822C))
+#define BIT_GET_MGQ_FIFO_WPTR_8822C(x)                                         \
+	(((x) >> BIT_SHIFT_MGQ_FIFO_WPTR_8822C) & BIT_MASK_MGQ_FIFO_WPTR_8822C)
+#define BIT_SET_MGQ_FIFO_WPTR_8822C(x, v)                                      \
+	(BIT_CLEAR_MGQ_FIFO_WPTR_8822C(x) | BIT_MGQ_FIFO_WPTR_8822C(v))
+
+/* 2 REG_MGQ_FIFO_READ_POINTER_8822C */
+
+#define BIT_SHIFT_MGQ_FIFO_SIZE_8822C 14
+#define BIT_MASK_MGQ_FIFO_SIZE_8822C 0x3
+#define BIT_MGQ_FIFO_SIZE_8822C(x)                                             \
+	(((x) & BIT_MASK_MGQ_FIFO_SIZE_8822C) << BIT_SHIFT_MGQ_FIFO_SIZE_8822C)
+#define BITS_MGQ_FIFO_SIZE_8822C                                               \
+	(BIT_MASK_MGQ_FIFO_SIZE_8822C << BIT_SHIFT_MGQ_FIFO_SIZE_8822C)
+#define BIT_CLEAR_MGQ_FIFO_SIZE_8822C(x) ((x) & (~BITS_MGQ_FIFO_SIZE_8822C))
+#define BIT_GET_MGQ_FIFO_SIZE_8822C(x)                                         \
+	(((x) >> BIT_SHIFT_MGQ_FIFO_SIZE_8822C) & BIT_MASK_MGQ_FIFO_SIZE_8822C)
+#define BIT_SET_MGQ_FIFO_SIZE_8822C(x, v)                                      \
+	(BIT_CLEAR_MGQ_FIFO_SIZE_8822C(x) | BIT_MGQ_FIFO_SIZE_8822C(v))
+
+#define BIT_MGQ_FIFO_PAUSE_8822C BIT(13)
+
+#define BIT_SHIFT_MGQ_FIFO_RPTR_8822C 8
+#define BIT_MASK_MGQ_FIFO_RPTR_8822C 0x1f
+#define BIT_MGQ_FIFO_RPTR_8822C(x)                                             \
+	(((x) & BIT_MASK_MGQ_FIFO_RPTR_8822C) << BIT_SHIFT_MGQ_FIFO_RPTR_8822C)
+#define BITS_MGQ_FIFO_RPTR_8822C                                               \
+	(BIT_MASK_MGQ_FIFO_RPTR_8822C << BIT_SHIFT_MGQ_FIFO_RPTR_8822C)
+#define BIT_CLEAR_MGQ_FIFO_RPTR_8822C(x) ((x) & (~BITS_MGQ_FIFO_RPTR_8822C))
+#define BIT_GET_MGQ_FIFO_RPTR_8822C(x)                                         \
+	(((x) >> BIT_SHIFT_MGQ_FIFO_RPTR_8822C) & BIT_MASK_MGQ_FIFO_RPTR_8822C)
+#define BIT_SET_MGQ_FIFO_RPTR_8822C(x, v)                                      \
+	(BIT_CLEAR_MGQ_FIFO_RPTR_8822C(x) | BIT_MGQ_FIFO_RPTR_8822C(v))
+
+/* 2 REG_MGQ_FIFO_ENABLE_8822C */
+#define BIT_MGQ_FIFO_EN_8822C BIT(15)
+
+#define BIT_SHIFT_MGQ_FIFO_PG_SIZE_8822C 12
+#define BIT_MASK_MGQ_FIFO_PG_SIZE_8822C 0x7
+#define BIT_MGQ_FIFO_PG_SIZE_8822C(x)                                          \
+	(((x) & BIT_MASK_MGQ_FIFO_PG_SIZE_8822C)                               \
+	 << BIT_SHIFT_MGQ_FIFO_PG_SIZE_8822C)
+#define BITS_MGQ_FIFO_PG_SIZE_8822C                                            \
+	(BIT_MASK_MGQ_FIFO_PG_SIZE_8822C << BIT_SHIFT_MGQ_FIFO_PG_SIZE_8822C)
+#define BIT_CLEAR_MGQ_FIFO_PG_SIZE_8822C(x)                                    \
+	((x) & (~BITS_MGQ_FIFO_PG_SIZE_8822C))
+#define BIT_GET_MGQ_FIFO_PG_SIZE_8822C(x)                                      \
+	(((x) >> BIT_SHIFT_MGQ_FIFO_PG_SIZE_8822C) &                           \
+	 BIT_MASK_MGQ_FIFO_PG_SIZE_8822C)
+#define BIT_SET_MGQ_FIFO_PG_SIZE_8822C(x, v)                                   \
+	(BIT_CLEAR_MGQ_FIFO_PG_SIZE_8822C(x) | BIT_MGQ_FIFO_PG_SIZE_8822C(v))
+
+#define BIT_SHIFT_MGQ_FIFO_START_PG_8822C 0
+#define BIT_MASK_MGQ_FIFO_START_PG_8822C 0xfff
+#define BIT_MGQ_FIFO_START_PG_8822C(x)                                         \
+	(((x) & BIT_MASK_MGQ_FIFO_START_PG_8822C)                              \
+	 << BIT_SHIFT_MGQ_FIFO_START_PG_8822C)
+#define BITS_MGQ_FIFO_START_PG_8822C                                           \
+	(BIT_MASK_MGQ_FIFO_START_PG_8822C << BIT_SHIFT_MGQ_FIFO_START_PG_8822C)
+#define BIT_CLEAR_MGQ_FIFO_START_PG_8822C(x)                                   \
+	((x) & (~BITS_MGQ_FIFO_START_PG_8822C))
+#define BIT_GET_MGQ_FIFO_START_PG_8822C(x)                                     \
+	(((x) >> BIT_SHIFT_MGQ_FIFO_START_PG_8822C) &                          \
+	 BIT_MASK_MGQ_FIFO_START_PG_8822C)
+#define BIT_SET_MGQ_FIFO_START_PG_8822C(x, v)                                  \
+	(BIT_CLEAR_MGQ_FIFO_START_PG_8822C(x) | BIT_MGQ_FIFO_START_PG_8822C(v))
+
+/* 2 REG_MGQ_FIFO_RELEASE_INT_MASK_8822C */
+
+#define BIT_SHIFT_MGQ_FIFO_REL_INT_MASK_8822C 0
+#define BIT_MASK_MGQ_FIFO_REL_INT_MASK_8822C 0xffff
+#define BIT_MGQ_FIFO_REL_INT_MASK_8822C(x)                                     \
+	(((x) & BIT_MASK_MGQ_FIFO_REL_INT_MASK_8822C)                          \
+	 << BIT_SHIFT_MGQ_FIFO_REL_INT_MASK_8822C)
+#define BITS_MGQ_FIFO_REL_INT_MASK_8822C                                       \
+	(BIT_MASK_MGQ_FIFO_REL_INT_MASK_8822C                                  \
+	 << BIT_SHIFT_MGQ_FIFO_REL_INT_MASK_8822C)
+#define BIT_CLEAR_MGQ_FIFO_REL_INT_MASK_8822C(x)                               \
+	((x) & (~BITS_MGQ_FIFO_REL_INT_MASK_8822C))
+#define BIT_GET_MGQ_FIFO_REL_INT_MASK_8822C(x)                                 \
+	(((x) >> BIT_SHIFT_MGQ_FIFO_REL_INT_MASK_8822C) &                      \
+	 BIT_MASK_MGQ_FIFO_REL_INT_MASK_8822C)
+#define BIT_SET_MGQ_FIFO_REL_INT_MASK_8822C(x, v)                              \
+	(BIT_CLEAR_MGQ_FIFO_REL_INT_MASK_8822C(x) |                            \
+	 BIT_MGQ_FIFO_REL_INT_MASK_8822C(v))
+
+/* 2 REG_MGQ_FIFO_RELEASE_INT_FLAG_8822C */
+
+#define BIT_SHIFT_MGQ_FIFO_REL_INT_FLAG_8822C 0
+#define BIT_MASK_MGQ_FIFO_REL_INT_FLAG_8822C 0xffff
+#define BIT_MGQ_FIFO_REL_INT_FLAG_8822C(x)                                     \
+	(((x) & BIT_MASK_MGQ_FIFO_REL_INT_FLAG_8822C)                          \
+	 << BIT_SHIFT_MGQ_FIFO_REL_INT_FLAG_8822C)
+#define BITS_MGQ_FIFO_REL_INT_FLAG_8822C                                       \
+	(BIT_MASK_MGQ_FIFO_REL_INT_FLAG_8822C                                  \
+	 << BIT_SHIFT_MGQ_FIFO_REL_INT_FLAG_8822C)
+#define BIT_CLEAR_MGQ_FIFO_REL_INT_FLAG_8822C(x)                               \
+	((x) & (~BITS_MGQ_FIFO_REL_INT_FLAG_8822C))
+#define BIT_GET_MGQ_FIFO_REL_INT_FLAG_8822C(x)                                 \
+	(((x) >> BIT_SHIFT_MGQ_FIFO_REL_INT_FLAG_8822C) &                      \
+	 BIT_MASK_MGQ_FIFO_REL_INT_FLAG_8822C)
+#define BIT_SET_MGQ_FIFO_REL_INT_FLAG_8822C(x, v)                              \
+	(BIT_CLEAR_MGQ_FIFO_REL_INT_FLAG_8822C(x) |                            \
+	 BIT_MGQ_FIFO_REL_INT_FLAG_8822C(v))
+
+/* 2 REG_MGQ_FIFO_VALID_MAP_8822C */
+
+#define BIT_SHIFT_MGQ_FIFO_PKT_VALID_MAP_8822C 0
+#define BIT_MASK_MGQ_FIFO_PKT_VALID_MAP_8822C 0xffff
+#define BIT_MGQ_FIFO_PKT_VALID_MAP_8822C(x)                                    \
+	(((x) & BIT_MASK_MGQ_FIFO_PKT_VALID_MAP_8822C)                         \
+	 << BIT_SHIFT_MGQ_FIFO_PKT_VALID_MAP_8822C)
+#define BITS_MGQ_FIFO_PKT_VALID_MAP_8822C                                      \
+	(BIT_MASK_MGQ_FIFO_PKT_VALID_MAP_8822C                                 \
+	 << BIT_SHIFT_MGQ_FIFO_PKT_VALID_MAP_8822C)
+#define BIT_CLEAR_MGQ_FIFO_PKT_VALID_MAP_8822C(x)                              \
+	((x) & (~BITS_MGQ_FIFO_PKT_VALID_MAP_8822C))
+#define BIT_GET_MGQ_FIFO_PKT_VALID_MAP_8822C(x)                                \
+	(((x) >> BIT_SHIFT_MGQ_FIFO_PKT_VALID_MAP_8822C) &                     \
+	 BIT_MASK_MGQ_FIFO_PKT_VALID_MAP_8822C)
+#define BIT_SET_MGQ_FIFO_PKT_VALID_MAP_8822C(x, v)                             \
+	(BIT_CLEAR_MGQ_FIFO_PKT_VALID_MAP_8822C(x) |                           \
+	 BIT_MGQ_FIFO_PKT_VALID_MAP_8822C(v))
+
+/* 2 REG_MGQ_FIFO_LIFETIME_8822C */
+
+#define BIT_SHIFT_MGQ_FIFO_LIFETIME_8822C 0
+#define BIT_MASK_MGQ_FIFO_LIFETIME_8822C 0xffff
+#define BIT_MGQ_FIFO_LIFETIME_8822C(x)                                         \
+	(((x) & BIT_MASK_MGQ_FIFO_LIFETIME_8822C)                              \
+	 << BIT_SHIFT_MGQ_FIFO_LIFETIME_8822C)
+#define BITS_MGQ_FIFO_LIFETIME_8822C                                           \
+	(BIT_MASK_MGQ_FIFO_LIFETIME_8822C << BIT_SHIFT_MGQ_FIFO_LIFETIME_8822C)
+#define BIT_CLEAR_MGQ_FIFO_LIFETIME_8822C(x)                                   \
+	((x) & (~BITS_MGQ_FIFO_LIFETIME_8822C))
+#define BIT_GET_MGQ_FIFO_LIFETIME_8822C(x)                                     \
+	(((x) >> BIT_SHIFT_MGQ_FIFO_LIFETIME_8822C) &                          \
+	 BIT_MASK_MGQ_FIFO_LIFETIME_8822C)
+#define BIT_SET_MGQ_FIFO_LIFETIME_8822C(x, v)                                  \
+	(BIT_CLEAR_MGQ_FIFO_LIFETIME_8822C(x) | BIT_MGQ_FIFO_LIFETIME_8822C(v))
+
+/* 2 REG_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8822C */
+
+#define BIT_SHIFT_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8822C 0
+#define BIT_MASK_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8822C 0x7f
+#define BIT_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8822C(x)                      \
+	(((x) & BIT_MASK_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8822C)           \
+	 << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8822C)
+#define BITS_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8822C                        \
+	(BIT_MASK_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8822C                   \
+	 << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8822C)
+#define BIT_CLEAR_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8822C(x)                \
+	((x) & (~BITS_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8822C))
+#define BIT_GET_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8822C(x)                  \
+	(((x) >> BIT_SHIFT_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8822C) &       \
+	 BIT_MASK_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8822C)
+#define BIT_SET_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8822C(x, v)               \
+	(BIT_CLEAR_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8822C(x) |             \
+	 BIT_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8822C(v))
+
+/* 2 REG_SHCUT_SETTING_8822C */
+
+/* 2 REG_SHCUT_LLC_ETH_TYPE0_8822C */
+
+/* 2 REG_SHCUT_LLC_ETH_TYPE1_8822C */
+
+/* 2 REG_SHCUT_LLC_OUI0_8822C */
+
+/* 2 REG_SHCUT_LLC_OUI1_8822C */
+
+/* 2 REG_SHCUT_LLC_OUI2_8822C */
+
+/* 2 REG_MU_TX_CTL_8822C */
+#define BIT_R_MU_P1_WAIT_STATE_EN_8822C BIT(16)
+
+#define BIT_SHIFT_R_MU_RL_8822C 12
+#define BIT_MASK_R_MU_RL_8822C 0xf
+#define BIT_R_MU_RL_8822C(x)                                                   \
+	(((x) & BIT_MASK_R_MU_RL_8822C) << BIT_SHIFT_R_MU_RL_8822C)
+#define BITS_R_MU_RL_8822C (BIT_MASK_R_MU_RL_8822C << BIT_SHIFT_R_MU_RL_8822C)
+#define BIT_CLEAR_R_MU_RL_8822C(x) ((x) & (~BITS_R_MU_RL_8822C))
+#define BIT_GET_R_MU_RL_8822C(x)                                               \
+	(((x) >> BIT_SHIFT_R_MU_RL_8822C) & BIT_MASK_R_MU_RL_8822C)
+#define BIT_SET_R_MU_RL_8822C(x, v)                                            \
+	(BIT_CLEAR_R_MU_RL_8822C(x) | BIT_R_MU_RL_8822C(v))
+
+#define BIT_R_FORCE_P1_RATEDOWN_8822C BIT(11)
+
+#define BIT_SHIFT_R_MU_TAB_SEL_8822C 8
+#define BIT_MASK_R_MU_TAB_SEL_8822C 0x7
+#define BIT_R_MU_TAB_SEL_8822C(x)                                              \
+	(((x) & BIT_MASK_R_MU_TAB_SEL_8822C) << BIT_SHIFT_R_MU_TAB_SEL_8822C)
+#define BITS_R_MU_TAB_SEL_8822C                                                \
+	(BIT_MASK_R_MU_TAB_SEL_8822C << BIT_SHIFT_R_MU_TAB_SEL_8822C)
+#define BIT_CLEAR_R_MU_TAB_SEL_8822C(x) ((x) & (~BITS_R_MU_TAB_SEL_8822C))
+#define BIT_GET_R_MU_TAB_SEL_8822C(x)                                          \
+	(((x) >> BIT_SHIFT_R_MU_TAB_SEL_8822C) & BIT_MASK_R_MU_TAB_SEL_8822C)
+#define BIT_SET_R_MU_TAB_SEL_8822C(x, v)                                       \
+	(BIT_CLEAR_R_MU_TAB_SEL_8822C(x) | BIT_R_MU_TAB_SEL_8822C(v))
+
+#define BIT_R_EN_MU_MIMO_8822C BIT(7)
+#define BIT_R_EN_REVERS_GTAB_8822C BIT(6)
+
+#define BIT_SHIFT_R_MU_TABLE_VALID_8822C 0
+#define BIT_MASK_R_MU_TABLE_VALID_8822C 0x3f
+#define BIT_R_MU_TABLE_VALID_8822C(x)                                          \
+	(((x) & BIT_MASK_R_MU_TABLE_VALID_8822C)                               \
+	 << BIT_SHIFT_R_MU_TABLE_VALID_8822C)
+#define BITS_R_MU_TABLE_VALID_8822C                                            \
+	(BIT_MASK_R_MU_TABLE_VALID_8822C << BIT_SHIFT_R_MU_TABLE_VALID_8822C)
+#define BIT_CLEAR_R_MU_TABLE_VALID_8822C(x)                                    \
+	((x) & (~BITS_R_MU_TABLE_VALID_8822C))
+#define BIT_GET_R_MU_TABLE_VALID_8822C(x)                                      \
+	(((x) >> BIT_SHIFT_R_MU_TABLE_VALID_8822C) &                           \
+	 BIT_MASK_R_MU_TABLE_VALID_8822C)
+#define BIT_SET_R_MU_TABLE_VALID_8822C(x, v)                                   \
+	(BIT_CLEAR_R_MU_TABLE_VALID_8822C(x) | BIT_R_MU_TABLE_VALID_8822C(v))
+
+/* 2 REG_MU_STA_GID_VLD_8822C */
+
+#define BIT_SHIFT_R_MU_STA_GTAB_VALID_8822C 0
+#define BIT_MASK_R_MU_STA_GTAB_VALID_8822C 0xffffffffL
+#define BIT_R_MU_STA_GTAB_VALID_8822C(x)                                       \
+	(((x) & BIT_MASK_R_MU_STA_GTAB_VALID_8822C)                            \
+	 << BIT_SHIFT_R_MU_STA_GTAB_VALID_8822C)
+#define BITS_R_MU_STA_GTAB_VALID_8822C                                         \
+	(BIT_MASK_R_MU_STA_GTAB_VALID_8822C                                    \
+	 << BIT_SHIFT_R_MU_STA_GTAB_VALID_8822C)
+#define BIT_CLEAR_R_MU_STA_GTAB_VALID_8822C(x)                                 \
+	((x) & (~BITS_R_MU_STA_GTAB_VALID_8822C))
+#define BIT_GET_R_MU_STA_GTAB_VALID_8822C(x)                                   \
+	(((x) >> BIT_SHIFT_R_MU_STA_GTAB_VALID_8822C) &                        \
+	 BIT_MASK_R_MU_STA_GTAB_VALID_8822C)
+#define BIT_SET_R_MU_STA_GTAB_VALID_8822C(x, v)                                \
+	(BIT_CLEAR_R_MU_STA_GTAB_VALID_8822C(x) |                              \
+	 BIT_R_MU_STA_GTAB_VALID_8822C(v))
+
+/* 2 REG_MU_STA_USER_POS_INFO_8822C */
+
+#define BIT_SHIFT_R_MU_STA_GTAB_POSITION_L_8822C 0
+#define BIT_MASK_R_MU_STA_GTAB_POSITION_L_8822C 0xffffffffL
+#define BIT_R_MU_STA_GTAB_POSITION_L_8822C(x)                                  \
+	(((x) & BIT_MASK_R_MU_STA_GTAB_POSITION_L_8822C)                       \
+	 << BIT_SHIFT_R_MU_STA_GTAB_POSITION_L_8822C)
+#define BITS_R_MU_STA_GTAB_POSITION_L_8822C                                    \
+	(BIT_MASK_R_MU_STA_GTAB_POSITION_L_8822C                               \
+	 << BIT_SHIFT_R_MU_STA_GTAB_POSITION_L_8822C)
+#define BIT_CLEAR_R_MU_STA_GTAB_POSITION_L_8822C(x)                            \
+	((x) & (~BITS_R_MU_STA_GTAB_POSITION_L_8822C))
+#define BIT_GET_R_MU_STA_GTAB_POSITION_L_8822C(x)                              \
+	(((x) >> BIT_SHIFT_R_MU_STA_GTAB_POSITION_L_8822C) &                   \
+	 BIT_MASK_R_MU_STA_GTAB_POSITION_L_8822C)
+#define BIT_SET_R_MU_STA_GTAB_POSITION_L_8822C(x, v)                           \
+	(BIT_CLEAR_R_MU_STA_GTAB_POSITION_L_8822C(x) |                         \
+	 BIT_R_MU_STA_GTAB_POSITION_L_8822C(v))
+
+/* 2 REG_MU_STA_USER_POS_INFO_H_8822C */
+
+#define BIT_SHIFT_R_MU_STA_GTAB_POSITION_H_8822C 0
+#define BIT_MASK_R_MU_STA_GTAB_POSITION_H_8822C 0xffffffffL
+#define BIT_R_MU_STA_GTAB_POSITION_H_8822C(x)                                  \
+	(((x) & BIT_MASK_R_MU_STA_GTAB_POSITION_H_8822C)                       \
+	 << BIT_SHIFT_R_MU_STA_GTAB_POSITION_H_8822C)
+#define BITS_R_MU_STA_GTAB_POSITION_H_8822C                                    \
+	(BIT_MASK_R_MU_STA_GTAB_POSITION_H_8822C                               \
+	 << BIT_SHIFT_R_MU_STA_GTAB_POSITION_H_8822C)
+#define BIT_CLEAR_R_MU_STA_GTAB_POSITION_H_8822C(x)                            \
+	((x) & (~BITS_R_MU_STA_GTAB_POSITION_H_8822C))
+#define BIT_GET_R_MU_STA_GTAB_POSITION_H_8822C(x)                              \
+	(((x) >> BIT_SHIFT_R_MU_STA_GTAB_POSITION_H_8822C) &                   \
+	 BIT_MASK_R_MU_STA_GTAB_POSITION_H_8822C)
+#define BIT_SET_R_MU_STA_GTAB_POSITION_H_8822C(x, v)                           \
+	(BIT_CLEAR_R_MU_STA_GTAB_POSITION_H_8822C(x) |                         \
+	 BIT_R_MU_STA_GTAB_POSITION_H_8822C(v))
+
+/* 2 REG_CHNL_INFO_CTRL_8822C */
+#define BIT_CHNL_REF_RXNAV_8822C BIT(7)
+#define BIT_CHNL_REF_VBON_8822C BIT(6)
+#define BIT_CHNL_REF_EDCA_8822C BIT(5)
+#define BIT_CHNL_REF_CCA_8822C BIT(4)
+#define BIT_RST_CHNL_BUSY_8822C BIT(3)
+#define BIT_RST_CHNL_IDLE_8822C BIT(2)
+#define BIT_CHNL_INFO_RST_8822C BIT(1)
+#define BIT_ATM_AIRTIME_EN_8822C BIT(0)
+
+/* 2 REG_CHNL_IDLE_TIME_8822C */
+
+#define BIT_SHIFT_CHNL_IDLE_TIME_8822C 0
+#define BIT_MASK_CHNL_IDLE_TIME_8822C 0xffffffffL
+#define BIT_CHNL_IDLE_TIME_8822C(x)                                            \
+	(((x) & BIT_MASK_CHNL_IDLE_TIME_8822C)                                 \
+	 << BIT_SHIFT_CHNL_IDLE_TIME_8822C)
+#define BITS_CHNL_IDLE_TIME_8822C                                              \
+	(BIT_MASK_CHNL_IDLE_TIME_8822C << BIT_SHIFT_CHNL_IDLE_TIME_8822C)
+#define BIT_CLEAR_CHNL_IDLE_TIME_8822C(x) ((x) & (~BITS_CHNL_IDLE_TIME_8822C))
+#define BIT_GET_CHNL_IDLE_TIME_8822C(x)                                        \
+	(((x) >> BIT_SHIFT_CHNL_IDLE_TIME_8822C) &                             \
+	 BIT_MASK_CHNL_IDLE_TIME_8822C)
+#define BIT_SET_CHNL_IDLE_TIME_8822C(x, v)                                     \
+	(BIT_CLEAR_CHNL_IDLE_TIME_8822C(x) | BIT_CHNL_IDLE_TIME_8822C(v))
+
+/* 2 REG_CHNL_BUSY_TIME_8822C */
+
+#define BIT_SHIFT_CHNL_BUSY_TIME_8822C 0
+#define BIT_MASK_CHNL_BUSY_TIME_8822C 0xffffffffL
+#define BIT_CHNL_BUSY_TIME_8822C(x)                                            \
+	(((x) & BIT_MASK_CHNL_BUSY_TIME_8822C)                                 \
+	 << BIT_SHIFT_CHNL_BUSY_TIME_8822C)
+#define BITS_CHNL_BUSY_TIME_8822C                                              \
+	(BIT_MASK_CHNL_BUSY_TIME_8822C << BIT_SHIFT_CHNL_BUSY_TIME_8822C)
+#define BIT_CLEAR_CHNL_BUSY_TIME_8822C(x) ((x) & (~BITS_CHNL_BUSY_TIME_8822C))
+#define BIT_GET_CHNL_BUSY_TIME_8822C(x)                                        \
+	(((x) >> BIT_SHIFT_CHNL_BUSY_TIME_8822C) &                             \
+	 BIT_MASK_CHNL_BUSY_TIME_8822C)
+#define BIT_SET_CHNL_BUSY_TIME_8822C(x, v)                                     \
+	(BIT_CLEAR_CHNL_BUSY_TIME_8822C(x) | BIT_CHNL_BUSY_TIME_8822C(v))
+
+/* 2 REG_MU_TRX_DBG_CNT_V1_8822C */
+#define BIT_MU_DNGCNT_RST_8822C BIT(20)
+
+#define BIT_SHIFT_MU_DNGCNT_SEL_8822C 16
+#define BIT_MASK_MU_DNGCNT_SEL_8822C 0xf
+#define BIT_MU_DNGCNT_SEL_8822C(x)                                             \
+	(((x) & BIT_MASK_MU_DNGCNT_SEL_8822C) << BIT_SHIFT_MU_DNGCNT_SEL_8822C)
+#define BITS_MU_DNGCNT_SEL_8822C                                               \
+	(BIT_MASK_MU_DNGCNT_SEL_8822C << BIT_SHIFT_MU_DNGCNT_SEL_8822C)
+#define BIT_CLEAR_MU_DNGCNT_SEL_8822C(x) ((x) & (~BITS_MU_DNGCNT_SEL_8822C))
+#define BIT_GET_MU_DNGCNT_SEL_8822C(x)                                         \
+	(((x) >> BIT_SHIFT_MU_DNGCNT_SEL_8822C) & BIT_MASK_MU_DNGCNT_SEL_8822C)
+#define BIT_SET_MU_DNGCNT_SEL_8822C(x, v)                                      \
+	(BIT_CLEAR_MU_DNGCNT_SEL_8822C(x) | BIT_MU_DNGCNT_SEL_8822C(v))
+
+#define BIT_SHIFT_MU_DNGCNT_8822C 0
+#define BIT_MASK_MU_DNGCNT_8822C 0xffff
+#define BIT_MU_DNGCNT_8822C(x)                                                 \
+	(((x) & BIT_MASK_MU_DNGCNT_8822C) << BIT_SHIFT_MU_DNGCNT_8822C)
+#define BITS_MU_DNGCNT_8822C                                                   \
+	(BIT_MASK_MU_DNGCNT_8822C << BIT_SHIFT_MU_DNGCNT_8822C)
+#define BIT_CLEAR_MU_DNGCNT_8822C(x) ((x) & (~BITS_MU_DNGCNT_8822C))
+#define BIT_GET_MU_DNGCNT_8822C(x)                                             \
+	(((x) >> BIT_SHIFT_MU_DNGCNT_8822C) & BIT_MASK_MU_DNGCNT_8822C)
+#define BIT_SET_MU_DNGCNT_8822C(x, v)                                          \
+	(BIT_CLEAR_MU_DNGCNT_8822C(x) | BIT_MU_DNGCNT_8822C(v))
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_EDCA_VO_PARAM_8822C */
+
+#define BIT_SHIFT_TXOPLIMIT_8822C 16
+#define BIT_MASK_TXOPLIMIT_8822C 0x7ff
+#define BIT_TXOPLIMIT_8822C(x)                                                 \
+	(((x) & BIT_MASK_TXOPLIMIT_8822C) << BIT_SHIFT_TXOPLIMIT_8822C)
+#define BITS_TXOPLIMIT_8822C                                                   \
+	(BIT_MASK_TXOPLIMIT_8822C << BIT_SHIFT_TXOPLIMIT_8822C)
+#define BIT_CLEAR_TXOPLIMIT_8822C(x) ((x) & (~BITS_TXOPLIMIT_8822C))
+#define BIT_GET_TXOPLIMIT_8822C(x)                                             \
+	(((x) >> BIT_SHIFT_TXOPLIMIT_8822C) & BIT_MASK_TXOPLIMIT_8822C)
+#define BIT_SET_TXOPLIMIT_8822C(x, v)                                          \
+	(BIT_CLEAR_TXOPLIMIT_8822C(x) | BIT_TXOPLIMIT_8822C(v))
+
+#define BIT_SHIFT_CW_8822C 8
+#define BIT_MASK_CW_8822C 0xff
+#define BIT_CW_8822C(x) (((x) & BIT_MASK_CW_8822C) << BIT_SHIFT_CW_8822C)
+#define BITS_CW_8822C (BIT_MASK_CW_8822C << BIT_SHIFT_CW_8822C)
+#define BIT_CLEAR_CW_8822C(x) ((x) & (~BITS_CW_8822C))
+#define BIT_GET_CW_8822C(x) (((x) >> BIT_SHIFT_CW_8822C) & BIT_MASK_CW_8822C)
+#define BIT_SET_CW_8822C(x, v) (BIT_CLEAR_CW_8822C(x) | BIT_CW_8822C(v))
+
+#define BIT_SHIFT_AIFS_8822C 0
+#define BIT_MASK_AIFS_8822C 0xff
+#define BIT_AIFS_8822C(x) (((x) & BIT_MASK_AIFS_8822C) << BIT_SHIFT_AIFS_8822C)
+#define BITS_AIFS_8822C (BIT_MASK_AIFS_8822C << BIT_SHIFT_AIFS_8822C)
+#define BIT_CLEAR_AIFS_8822C(x) ((x) & (~BITS_AIFS_8822C))
+#define BIT_GET_AIFS_8822C(x)                                                  \
+	(((x) >> BIT_SHIFT_AIFS_8822C) & BIT_MASK_AIFS_8822C)
+#define BIT_SET_AIFS_8822C(x, v) (BIT_CLEAR_AIFS_8822C(x) | BIT_AIFS_8822C(v))
+
+/* 2 REG_EDCA_VI_PARAM_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+#define BIT_SHIFT_TXOPLIMIT_8822C 16
+#define BIT_MASK_TXOPLIMIT_8822C 0x7ff
+#define BIT_TXOPLIMIT_8822C(x)                                                 \
+	(((x) & BIT_MASK_TXOPLIMIT_8822C) << BIT_SHIFT_TXOPLIMIT_8822C)
+#define BITS_TXOPLIMIT_8822C                                                   \
+	(BIT_MASK_TXOPLIMIT_8822C << BIT_SHIFT_TXOPLIMIT_8822C)
+#define BIT_CLEAR_TXOPLIMIT_8822C(x) ((x) & (~BITS_TXOPLIMIT_8822C))
+#define BIT_GET_TXOPLIMIT_8822C(x)                                             \
+	(((x) >> BIT_SHIFT_TXOPLIMIT_8822C) & BIT_MASK_TXOPLIMIT_8822C)
+#define BIT_SET_TXOPLIMIT_8822C(x, v)                                          \
+	(BIT_CLEAR_TXOPLIMIT_8822C(x) | BIT_TXOPLIMIT_8822C(v))
+
+#define BIT_SHIFT_CW_8822C 8
+#define BIT_MASK_CW_8822C 0xff
+#define BIT_CW_8822C(x) (((x) & BIT_MASK_CW_8822C) << BIT_SHIFT_CW_8822C)
+#define BITS_CW_8822C (BIT_MASK_CW_8822C << BIT_SHIFT_CW_8822C)
+#define BIT_CLEAR_CW_8822C(x) ((x) & (~BITS_CW_8822C))
+#define BIT_GET_CW_8822C(x) (((x) >> BIT_SHIFT_CW_8822C) & BIT_MASK_CW_8822C)
+#define BIT_SET_CW_8822C(x, v) (BIT_CLEAR_CW_8822C(x) | BIT_CW_8822C(v))
+
+#define BIT_SHIFT_AIFS_8822C 0
+#define BIT_MASK_AIFS_8822C 0xff
+#define BIT_AIFS_8822C(x) (((x) & BIT_MASK_AIFS_8822C) << BIT_SHIFT_AIFS_8822C)
+#define BITS_AIFS_8822C (BIT_MASK_AIFS_8822C << BIT_SHIFT_AIFS_8822C)
+#define BIT_CLEAR_AIFS_8822C(x) ((x) & (~BITS_AIFS_8822C))
+#define BIT_GET_AIFS_8822C(x)                                                  \
+	(((x) >> BIT_SHIFT_AIFS_8822C) & BIT_MASK_AIFS_8822C)
+#define BIT_SET_AIFS_8822C(x, v) (BIT_CLEAR_AIFS_8822C(x) | BIT_AIFS_8822C(v))
+
+/* 2 REG_EDCA_BE_PARAM_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+#define BIT_SHIFT_TXOPLIMIT_8822C 16
+#define BIT_MASK_TXOPLIMIT_8822C 0x7ff
+#define BIT_TXOPLIMIT_8822C(x)                                                 \
+	(((x) & BIT_MASK_TXOPLIMIT_8822C) << BIT_SHIFT_TXOPLIMIT_8822C)
+#define BITS_TXOPLIMIT_8822C                                                   \
+	(BIT_MASK_TXOPLIMIT_8822C << BIT_SHIFT_TXOPLIMIT_8822C)
+#define BIT_CLEAR_TXOPLIMIT_8822C(x) ((x) & (~BITS_TXOPLIMIT_8822C))
+#define BIT_GET_TXOPLIMIT_8822C(x)                                             \
+	(((x) >> BIT_SHIFT_TXOPLIMIT_8822C) & BIT_MASK_TXOPLIMIT_8822C)
+#define BIT_SET_TXOPLIMIT_8822C(x, v)                                          \
+	(BIT_CLEAR_TXOPLIMIT_8822C(x) | BIT_TXOPLIMIT_8822C(v))
+
+#define BIT_SHIFT_CW_8822C 8
+#define BIT_MASK_CW_8822C 0xff
+#define BIT_CW_8822C(x) (((x) & BIT_MASK_CW_8822C) << BIT_SHIFT_CW_8822C)
+#define BITS_CW_8822C (BIT_MASK_CW_8822C << BIT_SHIFT_CW_8822C)
+#define BIT_CLEAR_CW_8822C(x) ((x) & (~BITS_CW_8822C))
+#define BIT_GET_CW_8822C(x) (((x) >> BIT_SHIFT_CW_8822C) & BIT_MASK_CW_8822C)
+#define BIT_SET_CW_8822C(x, v) (BIT_CLEAR_CW_8822C(x) | BIT_CW_8822C(v))
+
+#define BIT_SHIFT_AIFS_8822C 0
+#define BIT_MASK_AIFS_8822C 0xff
+#define BIT_AIFS_8822C(x) (((x) & BIT_MASK_AIFS_8822C) << BIT_SHIFT_AIFS_8822C)
+#define BITS_AIFS_8822C (BIT_MASK_AIFS_8822C << BIT_SHIFT_AIFS_8822C)
+#define BIT_CLEAR_AIFS_8822C(x) ((x) & (~BITS_AIFS_8822C))
+#define BIT_GET_AIFS_8822C(x)                                                  \
+	(((x) >> BIT_SHIFT_AIFS_8822C) & BIT_MASK_AIFS_8822C)
+#define BIT_SET_AIFS_8822C(x, v) (BIT_CLEAR_AIFS_8822C(x) | BIT_AIFS_8822C(v))
+
+/* 2 REG_EDCA_BK_PARAM_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+#define BIT_SHIFT_TXOPLIMIT_8822C 16
+#define BIT_MASK_TXOPLIMIT_8822C 0x7ff
+#define BIT_TXOPLIMIT_8822C(x)                                                 \
+	(((x) & BIT_MASK_TXOPLIMIT_8822C) << BIT_SHIFT_TXOPLIMIT_8822C)
+#define BITS_TXOPLIMIT_8822C                                                   \
+	(BIT_MASK_TXOPLIMIT_8822C << BIT_SHIFT_TXOPLIMIT_8822C)
+#define BIT_CLEAR_TXOPLIMIT_8822C(x) ((x) & (~BITS_TXOPLIMIT_8822C))
+#define BIT_GET_TXOPLIMIT_8822C(x)                                             \
+	(((x) >> BIT_SHIFT_TXOPLIMIT_8822C) & BIT_MASK_TXOPLIMIT_8822C)
+#define BIT_SET_TXOPLIMIT_8822C(x, v)                                          \
+	(BIT_CLEAR_TXOPLIMIT_8822C(x) | BIT_TXOPLIMIT_8822C(v))
+
+#define BIT_SHIFT_CW_8822C 8
+#define BIT_MASK_CW_8822C 0xff
+#define BIT_CW_8822C(x) (((x) & BIT_MASK_CW_8822C) << BIT_SHIFT_CW_8822C)
+#define BITS_CW_8822C (BIT_MASK_CW_8822C << BIT_SHIFT_CW_8822C)
+#define BIT_CLEAR_CW_8822C(x) ((x) & (~BITS_CW_8822C))
+#define BIT_GET_CW_8822C(x) (((x) >> BIT_SHIFT_CW_8822C) & BIT_MASK_CW_8822C)
+#define BIT_SET_CW_8822C(x, v) (BIT_CLEAR_CW_8822C(x) | BIT_CW_8822C(v))
+
+#define BIT_SHIFT_AIFS_8822C 0
+#define BIT_MASK_AIFS_8822C 0xff
+#define BIT_AIFS_8822C(x) (((x) & BIT_MASK_AIFS_8822C) << BIT_SHIFT_AIFS_8822C)
+#define BITS_AIFS_8822C (BIT_MASK_AIFS_8822C << BIT_SHIFT_AIFS_8822C)
+#define BIT_CLEAR_AIFS_8822C(x) ((x) & (~BITS_AIFS_8822C))
+#define BIT_GET_AIFS_8822C(x)                                                  \
+	(((x) >> BIT_SHIFT_AIFS_8822C) & BIT_MASK_AIFS_8822C)
+#define BIT_SET_AIFS_8822C(x, v) (BIT_CLEAR_AIFS_8822C(x) | BIT_AIFS_8822C(v))
+
+/* 2 REG_BCNTCFG_8822C */
+
+#define BIT_SHIFT_BCNCW_MAX_8822C 12
+#define BIT_MASK_BCNCW_MAX_8822C 0xf
+#define BIT_BCNCW_MAX_8822C(x)                                                 \
+	(((x) & BIT_MASK_BCNCW_MAX_8822C) << BIT_SHIFT_BCNCW_MAX_8822C)
+#define BITS_BCNCW_MAX_8822C                                                   \
+	(BIT_MASK_BCNCW_MAX_8822C << BIT_SHIFT_BCNCW_MAX_8822C)
+#define BIT_CLEAR_BCNCW_MAX_8822C(x) ((x) & (~BITS_BCNCW_MAX_8822C))
+#define BIT_GET_BCNCW_MAX_8822C(x)                                             \
+	(((x) >> BIT_SHIFT_BCNCW_MAX_8822C) & BIT_MASK_BCNCW_MAX_8822C)
+#define BIT_SET_BCNCW_MAX_8822C(x, v)                                          \
+	(BIT_CLEAR_BCNCW_MAX_8822C(x) | BIT_BCNCW_MAX_8822C(v))
+
+#define BIT_SHIFT_BCNCW_MIN_8822C 8
+#define BIT_MASK_BCNCW_MIN_8822C 0xf
+#define BIT_BCNCW_MIN_8822C(x)                                                 \
+	(((x) & BIT_MASK_BCNCW_MIN_8822C) << BIT_SHIFT_BCNCW_MIN_8822C)
+#define BITS_BCNCW_MIN_8822C                                                   \
+	(BIT_MASK_BCNCW_MIN_8822C << BIT_SHIFT_BCNCW_MIN_8822C)
+#define BIT_CLEAR_BCNCW_MIN_8822C(x) ((x) & (~BITS_BCNCW_MIN_8822C))
+#define BIT_GET_BCNCW_MIN_8822C(x)                                             \
+	(((x) >> BIT_SHIFT_BCNCW_MIN_8822C) & BIT_MASK_BCNCW_MIN_8822C)
+#define BIT_SET_BCNCW_MIN_8822C(x, v)                                          \
+	(BIT_CLEAR_BCNCW_MIN_8822C(x) | BIT_BCNCW_MIN_8822C(v))
+
+#define BIT_SHIFT_BCNIFS_8822C 0
+#define BIT_MASK_BCNIFS_8822C 0xff
+#define BIT_BCNIFS_8822C(x)                                                    \
+	(((x) & BIT_MASK_BCNIFS_8822C) << BIT_SHIFT_BCNIFS_8822C)
+#define BITS_BCNIFS_8822C (BIT_MASK_BCNIFS_8822C << BIT_SHIFT_BCNIFS_8822C)
+#define BIT_CLEAR_BCNIFS_8822C(x) ((x) & (~BITS_BCNIFS_8822C))
+#define BIT_GET_BCNIFS_8822C(x)                                                \
+	(((x) >> BIT_SHIFT_BCNIFS_8822C) & BIT_MASK_BCNIFS_8822C)
+#define BIT_SET_BCNIFS_8822C(x, v)                                             \
+	(BIT_CLEAR_BCNIFS_8822C(x) | BIT_BCNIFS_8822C(v))
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_PIFS_8822C */
+
+#define BIT_SHIFT_PIFS_8822C 0
+#define BIT_MASK_PIFS_8822C 0xff
+#define BIT_PIFS_8822C(x) (((x) & BIT_MASK_PIFS_8822C) << BIT_SHIFT_PIFS_8822C)
+#define BITS_PIFS_8822C (BIT_MASK_PIFS_8822C << BIT_SHIFT_PIFS_8822C)
+#define BIT_CLEAR_PIFS_8822C(x) ((x) & (~BITS_PIFS_8822C))
+#define BIT_GET_PIFS_8822C(x)                                                  \
+	(((x) >> BIT_SHIFT_PIFS_8822C) & BIT_MASK_PIFS_8822C)
+#define BIT_SET_PIFS_8822C(x, v) (BIT_CLEAR_PIFS_8822C(x) | BIT_PIFS_8822C(v))
+
+/* 2 REG_RDG_PIFS_8822C */
+
+#define BIT_SHIFT_RDG_PIFS_8822C 0
+#define BIT_MASK_RDG_PIFS_8822C 0xff
+#define BIT_RDG_PIFS_8822C(x)                                                  \
+	(((x) & BIT_MASK_RDG_PIFS_8822C) << BIT_SHIFT_RDG_PIFS_8822C)
+#define BITS_RDG_PIFS_8822C                                                    \
+	(BIT_MASK_RDG_PIFS_8822C << BIT_SHIFT_RDG_PIFS_8822C)
+#define BIT_CLEAR_RDG_PIFS_8822C(x) ((x) & (~BITS_RDG_PIFS_8822C))
+#define BIT_GET_RDG_PIFS_8822C(x)                                              \
+	(((x) >> BIT_SHIFT_RDG_PIFS_8822C) & BIT_MASK_RDG_PIFS_8822C)
+#define BIT_SET_RDG_PIFS_8822C(x, v)                                           \
+	(BIT_CLEAR_RDG_PIFS_8822C(x) | BIT_RDG_PIFS_8822C(v))
+
+/* 2 REG_SIFS_8822C */
+
+#define BIT_SHIFT_SIFS_OFDM_TRX_8822C 24
+#define BIT_MASK_SIFS_OFDM_TRX_8822C 0xff
+#define BIT_SIFS_OFDM_TRX_8822C(x)                                             \
+	(((x) & BIT_MASK_SIFS_OFDM_TRX_8822C) << BIT_SHIFT_SIFS_OFDM_TRX_8822C)
+#define BITS_SIFS_OFDM_TRX_8822C                                               \
+	(BIT_MASK_SIFS_OFDM_TRX_8822C << BIT_SHIFT_SIFS_OFDM_TRX_8822C)
+#define BIT_CLEAR_SIFS_OFDM_TRX_8822C(x) ((x) & (~BITS_SIFS_OFDM_TRX_8822C))
+#define BIT_GET_SIFS_OFDM_TRX_8822C(x)                                         \
+	(((x) >> BIT_SHIFT_SIFS_OFDM_TRX_8822C) & BIT_MASK_SIFS_OFDM_TRX_8822C)
+#define BIT_SET_SIFS_OFDM_TRX_8822C(x, v)                                      \
+	(BIT_CLEAR_SIFS_OFDM_TRX_8822C(x) | BIT_SIFS_OFDM_TRX_8822C(v))
+
+#define BIT_SHIFT_SIFS_CCK_TRX_8822C 16
+#define BIT_MASK_SIFS_CCK_TRX_8822C 0xff
+#define BIT_SIFS_CCK_TRX_8822C(x)                                              \
+	(((x) & BIT_MASK_SIFS_CCK_TRX_8822C) << BIT_SHIFT_SIFS_CCK_TRX_8822C)
+#define BITS_SIFS_CCK_TRX_8822C                                                \
+	(BIT_MASK_SIFS_CCK_TRX_8822C << BIT_SHIFT_SIFS_CCK_TRX_8822C)
+#define BIT_CLEAR_SIFS_CCK_TRX_8822C(x) ((x) & (~BITS_SIFS_CCK_TRX_8822C))
+#define BIT_GET_SIFS_CCK_TRX_8822C(x)                                          \
+	(((x) >> BIT_SHIFT_SIFS_CCK_TRX_8822C) & BIT_MASK_SIFS_CCK_TRX_8822C)
+#define BIT_SET_SIFS_CCK_TRX_8822C(x, v)                                       \
+	(BIT_CLEAR_SIFS_CCK_TRX_8822C(x) | BIT_SIFS_CCK_TRX_8822C(v))
+
+#define BIT_SHIFT_SIFS_OFDM_CTX_8822C 8
+#define BIT_MASK_SIFS_OFDM_CTX_8822C 0xff
+#define BIT_SIFS_OFDM_CTX_8822C(x)                                             \
+	(((x) & BIT_MASK_SIFS_OFDM_CTX_8822C) << BIT_SHIFT_SIFS_OFDM_CTX_8822C)
+#define BITS_SIFS_OFDM_CTX_8822C                                               \
+	(BIT_MASK_SIFS_OFDM_CTX_8822C << BIT_SHIFT_SIFS_OFDM_CTX_8822C)
+#define BIT_CLEAR_SIFS_OFDM_CTX_8822C(x) ((x) & (~BITS_SIFS_OFDM_CTX_8822C))
+#define BIT_GET_SIFS_OFDM_CTX_8822C(x)                                         \
+	(((x) >> BIT_SHIFT_SIFS_OFDM_CTX_8822C) & BIT_MASK_SIFS_OFDM_CTX_8822C)
+#define BIT_SET_SIFS_OFDM_CTX_8822C(x, v)                                      \
+	(BIT_CLEAR_SIFS_OFDM_CTX_8822C(x) | BIT_SIFS_OFDM_CTX_8822C(v))
+
+#define BIT_SHIFT_SIFS_CCK_CTX_8822C 0
+#define BIT_MASK_SIFS_CCK_CTX_8822C 0xff
+#define BIT_SIFS_CCK_CTX_8822C(x)                                              \
+	(((x) & BIT_MASK_SIFS_CCK_CTX_8822C) << BIT_SHIFT_SIFS_CCK_CTX_8822C)
+#define BITS_SIFS_CCK_CTX_8822C                                                \
+	(BIT_MASK_SIFS_CCK_CTX_8822C << BIT_SHIFT_SIFS_CCK_CTX_8822C)
+#define BIT_CLEAR_SIFS_CCK_CTX_8822C(x) ((x) & (~BITS_SIFS_CCK_CTX_8822C))
+#define BIT_GET_SIFS_CCK_CTX_8822C(x)                                          \
+	(((x) >> BIT_SHIFT_SIFS_CCK_CTX_8822C) & BIT_MASK_SIFS_CCK_CTX_8822C)
+#define BIT_SET_SIFS_CCK_CTX_8822C(x, v)                                       \
+	(BIT_CLEAR_SIFS_CCK_CTX_8822C(x) | BIT_SIFS_CCK_CTX_8822C(v))
+
+/* 2 REG_TSFTR_SYN_OFFSET_8822C */
+
+#define BIT_SHIFT_TSFTR_SNC_OFFSET_8822C 0
+#define BIT_MASK_TSFTR_SNC_OFFSET_8822C 0xffff
+#define BIT_TSFTR_SNC_OFFSET_8822C(x)                                          \
+	(((x) & BIT_MASK_TSFTR_SNC_OFFSET_8822C)                               \
+	 << BIT_SHIFT_TSFTR_SNC_OFFSET_8822C)
+#define BITS_TSFTR_SNC_OFFSET_8822C                                            \
+	(BIT_MASK_TSFTR_SNC_OFFSET_8822C << BIT_SHIFT_TSFTR_SNC_OFFSET_8822C)
+#define BIT_CLEAR_TSFTR_SNC_OFFSET_8822C(x)                                    \
+	((x) & (~BITS_TSFTR_SNC_OFFSET_8822C))
+#define BIT_GET_TSFTR_SNC_OFFSET_8822C(x)                                      \
+	(((x) >> BIT_SHIFT_TSFTR_SNC_OFFSET_8822C) &                           \
+	 BIT_MASK_TSFTR_SNC_OFFSET_8822C)
+#define BIT_SET_TSFTR_SNC_OFFSET_8822C(x, v)                                   \
+	(BIT_CLEAR_TSFTR_SNC_OFFSET_8822C(x) | BIT_TSFTR_SNC_OFFSET_8822C(v))
+
+/* 2 REG_AGGR_BREAK_TIME_8822C */
+
+#define BIT_SHIFT_AGGR_BK_TIME_8822C 0
+#define BIT_MASK_AGGR_BK_TIME_8822C 0xff
+#define BIT_AGGR_BK_TIME_8822C(x)                                              \
+	(((x) & BIT_MASK_AGGR_BK_TIME_8822C) << BIT_SHIFT_AGGR_BK_TIME_8822C)
+#define BITS_AGGR_BK_TIME_8822C                                                \
+	(BIT_MASK_AGGR_BK_TIME_8822C << BIT_SHIFT_AGGR_BK_TIME_8822C)
+#define BIT_CLEAR_AGGR_BK_TIME_8822C(x) ((x) & (~BITS_AGGR_BK_TIME_8822C))
+#define BIT_GET_AGGR_BK_TIME_8822C(x)                                          \
+	(((x) >> BIT_SHIFT_AGGR_BK_TIME_8822C) & BIT_MASK_AGGR_BK_TIME_8822C)
+#define BIT_SET_AGGR_BK_TIME_8822C(x, v)                                       \
+	(BIT_CLEAR_AGGR_BK_TIME_8822C(x) | BIT_AGGR_BK_TIME_8822C(v))
+
+/* 2 REG_SLOT_8822C */
+
+#define BIT_SHIFT_SLOT_8822C 0
+#define BIT_MASK_SLOT_8822C 0xff
+#define BIT_SLOT_8822C(x) (((x) & BIT_MASK_SLOT_8822C) << BIT_SHIFT_SLOT_8822C)
+#define BITS_SLOT_8822C (BIT_MASK_SLOT_8822C << BIT_SHIFT_SLOT_8822C)
+#define BIT_CLEAR_SLOT_8822C(x) ((x) & (~BITS_SLOT_8822C))
+#define BIT_GET_SLOT_8822C(x)                                                  \
+	(((x) >> BIT_SHIFT_SLOT_8822C) & BIT_MASK_SLOT_8822C)
+#define BIT_SET_SLOT_8822C(x, v) (BIT_CLEAR_SLOT_8822C(x) | BIT_SLOT_8822C(v))
+
+/* 2 REG_NOA_ON_ERLY_TIME_8822C */
+
+#define BIT_SHIFT__NOA_ON_ERLY_TIME_8822C 0
+#define BIT_MASK__NOA_ON_ERLY_TIME_8822C 0xff
+#define BIT__NOA_ON_ERLY_TIME_8822C(x)                                         \
+	(((x) & BIT_MASK__NOA_ON_ERLY_TIME_8822C)                              \
+	 << BIT_SHIFT__NOA_ON_ERLY_TIME_8822C)
+#define BITS__NOA_ON_ERLY_TIME_8822C                                           \
+	(BIT_MASK__NOA_ON_ERLY_TIME_8822C << BIT_SHIFT__NOA_ON_ERLY_TIME_8822C)
+#define BIT_CLEAR__NOA_ON_ERLY_TIME_8822C(x)                                   \
+	((x) & (~BITS__NOA_ON_ERLY_TIME_8822C))
+#define BIT_GET__NOA_ON_ERLY_TIME_8822C(x)                                     \
+	(((x) >> BIT_SHIFT__NOA_ON_ERLY_TIME_8822C) &                          \
+	 BIT_MASK__NOA_ON_ERLY_TIME_8822C)
+#define BIT_SET__NOA_ON_ERLY_TIME_8822C(x, v)                                  \
+	(BIT_CLEAR__NOA_ON_ERLY_TIME_8822C(x) | BIT__NOA_ON_ERLY_TIME_8822C(v))
+
+/* 2 REG_NOA_OFF_ERLY_TIME_8822C */
+
+#define BIT_SHIFT__NOA_OFF_ERLY_TIME_8822C 0
+#define BIT_MASK__NOA_OFF_ERLY_TIME_8822C 0xff
+#define BIT__NOA_OFF_ERLY_TIME_8822C(x)                                        \
+	(((x) & BIT_MASK__NOA_OFF_ERLY_TIME_8822C)                             \
+	 << BIT_SHIFT__NOA_OFF_ERLY_TIME_8822C)
+#define BITS__NOA_OFF_ERLY_TIME_8822C                                          \
+	(BIT_MASK__NOA_OFF_ERLY_TIME_8822C                                     \
+	 << BIT_SHIFT__NOA_OFF_ERLY_TIME_8822C)
+#define BIT_CLEAR__NOA_OFF_ERLY_TIME_8822C(x)                                  \
+	((x) & (~BITS__NOA_OFF_ERLY_TIME_8822C))
+#define BIT_GET__NOA_OFF_ERLY_TIME_8822C(x)                                    \
+	(((x) >> BIT_SHIFT__NOA_OFF_ERLY_TIME_8822C) &                         \
+	 BIT_MASK__NOA_OFF_ERLY_TIME_8822C)
+#define BIT_SET__NOA_OFF_ERLY_TIME_8822C(x, v)                                 \
+	(BIT_CLEAR__NOA_OFF_ERLY_TIME_8822C(x) |                               \
+	 BIT__NOA_OFF_ERLY_TIME_8822C(v))
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_TX_PTCL_CTRL_8822C */
+#define BIT_DIS_EDCCA_8822C BIT(15)
+#define BIT_DIS_CCA_8822C BIT(14)
+#define BIT_LSIG_TXOP_TXCMD_NAV_8822C BIT(13)
+#define BIT_SIFS_BK_EN_8822C BIT(12)
+
+#define BIT_SHIFT_TXQ_NAV_MSK_8822C 8
+#define BIT_MASK_TXQ_NAV_MSK_8822C 0xf
+#define BIT_TXQ_NAV_MSK_8822C(x)                                               \
+	(((x) & BIT_MASK_TXQ_NAV_MSK_8822C) << BIT_SHIFT_TXQ_NAV_MSK_8822C)
+#define BITS_TXQ_NAV_MSK_8822C                                                 \
+	(BIT_MASK_TXQ_NAV_MSK_8822C << BIT_SHIFT_TXQ_NAV_MSK_8822C)
+#define BIT_CLEAR_TXQ_NAV_MSK_8822C(x) ((x) & (~BITS_TXQ_NAV_MSK_8822C))
+#define BIT_GET_TXQ_NAV_MSK_8822C(x)                                           \
+	(((x) >> BIT_SHIFT_TXQ_NAV_MSK_8822C) & BIT_MASK_TXQ_NAV_MSK_8822C)
+#define BIT_SET_TXQ_NAV_MSK_8822C(x, v)                                        \
+	(BIT_CLEAR_TXQ_NAV_MSK_8822C(x) | BIT_TXQ_NAV_MSK_8822C(v))
+
+#define BIT_DIS_CW_8822C BIT(7)
+#define BIT_NAV_END_TXOP_8822C BIT(6)
+#define BIT_RDG_END_TXOP_8822C BIT(5)
+#define BIT_AC_INBCN_HOLD_8822C BIT(4)
+#define BIT_MGTQ_TXOP_EN_8822C BIT(3)
+#define BIT_MGTQ_RTSMF_EN_8822C BIT(2)
+#define BIT_HIQ_RTSMF_EN_8822C BIT(1)
+#define BIT_BCN_RTSMF_EN_8822C BIT(0)
+
+/* 2 REG_TXPAUSE_8822C */
+#define BIT_STOP_BCN_HI_MGT_8822C BIT(7)
+#define BIT_MAC_STOPBCNQ_8822C BIT(6)
+#define BIT_MAC_STOPHIQ_8822C BIT(5)
+#define BIT_MAC_STOPMGQ_8822C BIT(4)
+#define BIT_MAC_STOPBK_8822C BIT(3)
+#define BIT_MAC_STOPBE_8822C BIT(2)
+#define BIT_MAC_STOPVI_8822C BIT(1)
+#define BIT_MAC_STOPVO_8822C BIT(0)
+
+/* 2 REG_DIS_TXREQ_CLR_8822C */
+#define BIT_DIS_BT_CCA_8822C BIT(7)
+#define BIT_DIS_TXREQ_CLR_HI_8822C BIT(5)
+#define BIT_DIS_TXREQ_CLR_MGQ_8822C BIT(4)
+#define BIT_DIS_TXREQ_CLR_VO_8822C BIT(3)
+#define BIT_DIS_TXREQ_CLR_VI_8822C BIT(2)
+#define BIT_DIS_TXREQ_CLR_BE_8822C BIT(1)
+#define BIT_DIS_TXREQ_CLR_BK_8822C BIT(0)
+
+/* 2 REG_RD_CTRL_8822C */
+#define BIT_EN_CLR_TXREQ_INCCA_8822C BIT(15)
+#define BIT_DIS_TX_OVER_BCNQ_8822C BIT(14)
+#define BIT_EN_BCNERR_INCCCA_8822C BIT(13)
+#define BIT_EDCCA_MSK_CNTDOWN_EN_8822C BIT(11)
+#define BIT_DIS_TXOP_CFE_8822C BIT(10)
+#define BIT_DIS_LSIG_CFE_8822C BIT(9)
+#define BIT_DIS_STBC_CFE_8822C BIT(8)
+#define BIT_BKQ_RD_INIT_EN_8822C BIT(7)
+#define BIT_BEQ_RD_INIT_EN_8822C BIT(6)
+#define BIT_VIQ_RD_INIT_EN_8822C BIT(5)
+#define BIT_VOQ_RD_INIT_EN_8822C BIT(4)
+#define BIT_BKQ_RD_RESP_EN_8822C BIT(3)
+#define BIT_BEQ_RD_RESP_EN_8822C BIT(2)
+#define BIT_VIQ_RD_RESP_EN_8822C BIT(1)
+#define BIT_VOQ_RD_RESP_EN_8822C BIT(0)
+
+/* 2 REG_MBSSID_CTRL_8822C */
+#define BIT_MBID_BCNQ7_EN_8822C BIT(7)
+#define BIT_MBID_BCNQ6_EN_8822C BIT(6)
+#define BIT_MBID_BCNQ5_EN_8822C BIT(5)
+#define BIT_MBID_BCNQ4_EN_8822C BIT(4)
+#define BIT_MBID_BCNQ3_EN_8822C BIT(3)
+#define BIT_MBID_BCNQ2_EN_8822C BIT(2)
+#define BIT_MBID_BCNQ1_EN_8822C BIT(1)
+#define BIT_MBID_BCNQ0_EN_8822C BIT(0)
+
+/* 2 REG_P2PPS_CTRL_8822C */
+#define BIT_P2P_CTW_ALLSTASLEEP_8822C BIT(7)
+#define BIT_P2P_OFF_DISTX_EN_8822C BIT(6)
+#define BIT_PWR_MGT_EN_8822C BIT(5)
+#define BIT_P2P_NOA1_EN_8822C BIT(2)
+#define BIT_P2P_NOA0_EN_8822C BIT(1)
+
+/* 2 REG_PKT_LIFETIME_CTRL_8822C */
+#define BIT_EN_P2P_CTWND1_8822C BIT(23)
+#define BIT_EN_BKF_CLR_TXREQ_8822C BIT(22)
+#define BIT_EN_TSFBIT32_RST_P2P_8822C BIT(21)
+#define BIT_EN_BCN_TX_BTCCA_8822C BIT(20)
+#define BIT_DIS_PKT_TX_ATIM_8822C BIT(19)
+#define BIT_DIS_BCN_DIS_CTN_8822C BIT(18)
+#define BIT_EN_NAVEND_RST_TXOP_8822C BIT(17)
+#define BIT_EN_FILTER_CCA_8822C BIT(16)
+
+#define BIT_SHIFT_CCA_FILTER_THRS_8822C 8
+#define BIT_MASK_CCA_FILTER_THRS_8822C 0xff
+#define BIT_CCA_FILTER_THRS_8822C(x)                                           \
+	(((x) & BIT_MASK_CCA_FILTER_THRS_8822C)                                \
+	 << BIT_SHIFT_CCA_FILTER_THRS_8822C)
+#define BITS_CCA_FILTER_THRS_8822C                                             \
+	(BIT_MASK_CCA_FILTER_THRS_8822C << BIT_SHIFT_CCA_FILTER_THRS_8822C)
+#define BIT_CLEAR_CCA_FILTER_THRS_8822C(x) ((x) & (~BITS_CCA_FILTER_THRS_8822C))
+#define BIT_GET_CCA_FILTER_THRS_8822C(x)                                       \
+	(((x) >> BIT_SHIFT_CCA_FILTER_THRS_8822C) &                            \
+	 BIT_MASK_CCA_FILTER_THRS_8822C)
+#define BIT_SET_CCA_FILTER_THRS_8822C(x, v)                                    \
+	(BIT_CLEAR_CCA_FILTER_THRS_8822C(x) | BIT_CCA_FILTER_THRS_8822C(v))
+
+#define BIT_SHIFT_EDCCA_THRS_8822C 0
+#define BIT_MASK_EDCCA_THRS_8822C 0xff
+#define BIT_EDCCA_THRS_8822C(x)                                                \
+	(((x) & BIT_MASK_EDCCA_THRS_8822C) << BIT_SHIFT_EDCCA_THRS_8822C)
+#define BITS_EDCCA_THRS_8822C                                                  \
+	(BIT_MASK_EDCCA_THRS_8822C << BIT_SHIFT_EDCCA_THRS_8822C)
+#define BIT_CLEAR_EDCCA_THRS_8822C(x) ((x) & (~BITS_EDCCA_THRS_8822C))
+#define BIT_GET_EDCCA_THRS_8822C(x)                                            \
+	(((x) >> BIT_SHIFT_EDCCA_THRS_8822C) & BIT_MASK_EDCCA_THRS_8822C)
+#define BIT_SET_EDCCA_THRS_8822C(x, v)                                         \
+	(BIT_CLEAR_EDCCA_THRS_8822C(x) | BIT_EDCCA_THRS_8822C(v))
+
+/* 2 REG_P2PPS_SPEC_STATE_8822C */
+#define BIT_SPEC_POWER_STATE_8822C BIT(7)
+#define BIT_SPEC_CTWINDOW_ON_8822C BIT(6)
+#define BIT_SPEC_BEACON_AREA_ON_8822C BIT(5)
+#define BIT_SPEC_CTWIN_EARLY_DISTX_8822C BIT(4)
+#define BIT_SPEC_NOA1_OFF_PERIOD_8822C BIT(3)
+#define BIT_SPEC_FORCE_DOZE1_8822C BIT(2)
+#define BIT_SPEC_NOA0_OFF_PERIOD_8822C BIT(1)
+#define BIT_SPEC_FORCE_DOZE0_8822C BIT(0)
+
+/* 2 REG_TXOP_LIMIT_CTRL_8822C */
+
+#define BIT_SHIFT_TXOP_TBTT_CNT_8822C 24
+#define BIT_MASK_TXOP_TBTT_CNT_8822C 0xff
+#define BIT_TXOP_TBTT_CNT_8822C(x)                                             \
+	(((x) & BIT_MASK_TXOP_TBTT_CNT_8822C) << BIT_SHIFT_TXOP_TBTT_CNT_8822C)
+#define BITS_TXOP_TBTT_CNT_8822C                                               \
+	(BIT_MASK_TXOP_TBTT_CNT_8822C << BIT_SHIFT_TXOP_TBTT_CNT_8822C)
+#define BIT_CLEAR_TXOP_TBTT_CNT_8822C(x) ((x) & (~BITS_TXOP_TBTT_CNT_8822C))
+#define BIT_GET_TXOP_TBTT_CNT_8822C(x)                                         \
+	(((x) >> BIT_SHIFT_TXOP_TBTT_CNT_8822C) & BIT_MASK_TXOP_TBTT_CNT_8822C)
+#define BIT_SET_TXOP_TBTT_CNT_8822C(x, v)                                      \
+	(BIT_CLEAR_TXOP_TBTT_CNT_8822C(x) | BIT_TXOP_TBTT_CNT_8822C(v))
+
+#define BIT_SHIFT_TXOP_TBTT_CNT_SEL_8822C 20
+#define BIT_MASK_TXOP_TBTT_CNT_SEL_8822C 0xf
+#define BIT_TXOP_TBTT_CNT_SEL_8822C(x)                                         \
+	(((x) & BIT_MASK_TXOP_TBTT_CNT_SEL_8822C)                              \
+	 << BIT_SHIFT_TXOP_TBTT_CNT_SEL_8822C)
+#define BITS_TXOP_TBTT_CNT_SEL_8822C                                           \
+	(BIT_MASK_TXOP_TBTT_CNT_SEL_8822C << BIT_SHIFT_TXOP_TBTT_CNT_SEL_8822C)
+#define BIT_CLEAR_TXOP_TBTT_CNT_SEL_8822C(x)                                   \
+	((x) & (~BITS_TXOP_TBTT_CNT_SEL_8822C))
+#define BIT_GET_TXOP_TBTT_CNT_SEL_8822C(x)                                     \
+	(((x) >> BIT_SHIFT_TXOP_TBTT_CNT_SEL_8822C) &                          \
+	 BIT_MASK_TXOP_TBTT_CNT_SEL_8822C)
+#define BIT_SET_TXOP_TBTT_CNT_SEL_8822C(x, v)                                  \
+	(BIT_CLEAR_TXOP_TBTT_CNT_SEL_8822C(x) | BIT_TXOP_TBTT_CNT_SEL_8822C(v))
+
+#define BIT_SHIFT_TXOP_LMT_EN_8822C 16
+#define BIT_MASK_TXOP_LMT_EN_8822C 0xf
+#define BIT_TXOP_LMT_EN_8822C(x)                                               \
+	(((x) & BIT_MASK_TXOP_LMT_EN_8822C) << BIT_SHIFT_TXOP_LMT_EN_8822C)
+#define BITS_TXOP_LMT_EN_8822C                                                 \
+	(BIT_MASK_TXOP_LMT_EN_8822C << BIT_SHIFT_TXOP_LMT_EN_8822C)
+#define BIT_CLEAR_TXOP_LMT_EN_8822C(x) ((x) & (~BITS_TXOP_LMT_EN_8822C))
+#define BIT_GET_TXOP_LMT_EN_8822C(x)                                           \
+	(((x) >> BIT_SHIFT_TXOP_LMT_EN_8822C) & BIT_MASK_TXOP_LMT_EN_8822C)
+#define BIT_SET_TXOP_LMT_EN_8822C(x, v)                                        \
+	(BIT_CLEAR_TXOP_LMT_EN_8822C(x) | BIT_TXOP_LMT_EN_8822C(v))
+
+#define BIT_SHIFT_TXOP_LMT_TX_TIME_8822C 8
+#define BIT_MASK_TXOP_LMT_TX_TIME_8822C 0xff
+#define BIT_TXOP_LMT_TX_TIME_8822C(x)                                          \
+	(((x) & BIT_MASK_TXOP_LMT_TX_TIME_8822C)                               \
+	 << BIT_SHIFT_TXOP_LMT_TX_TIME_8822C)
+#define BITS_TXOP_LMT_TX_TIME_8822C                                            \
+	(BIT_MASK_TXOP_LMT_TX_TIME_8822C << BIT_SHIFT_TXOP_LMT_TX_TIME_8822C)
+#define BIT_CLEAR_TXOP_LMT_TX_TIME_8822C(x)                                    \
+	((x) & (~BITS_TXOP_LMT_TX_TIME_8822C))
+#define BIT_GET_TXOP_LMT_TX_TIME_8822C(x)                                      \
+	(((x) >> BIT_SHIFT_TXOP_LMT_TX_TIME_8822C) &                           \
+	 BIT_MASK_TXOP_LMT_TX_TIME_8822C)
+#define BIT_SET_TXOP_LMT_TX_TIME_8822C(x, v)                                   \
+	(BIT_CLEAR_TXOP_LMT_TX_TIME_8822C(x) | BIT_TXOP_LMT_TX_TIME_8822C(v))
+
+#define BIT_TXOP_CNT_TRIGGER_RESET_8822C BIT(7)
+
+#define BIT_SHIFT_TXOP_LMT_PKT_NUM_8822C 0
+#define BIT_MASK_TXOP_LMT_PKT_NUM_8822C 0x3f
+#define BIT_TXOP_LMT_PKT_NUM_8822C(x)                                          \
+	(((x) & BIT_MASK_TXOP_LMT_PKT_NUM_8822C)                               \
+	 << BIT_SHIFT_TXOP_LMT_PKT_NUM_8822C)
+#define BITS_TXOP_LMT_PKT_NUM_8822C                                            \
+	(BIT_MASK_TXOP_LMT_PKT_NUM_8822C << BIT_SHIFT_TXOP_LMT_PKT_NUM_8822C)
+#define BIT_CLEAR_TXOP_LMT_PKT_NUM_8822C(x)                                    \
+	((x) & (~BITS_TXOP_LMT_PKT_NUM_8822C))
+#define BIT_GET_TXOP_LMT_PKT_NUM_8822C(x)                                      \
+	(((x) >> BIT_SHIFT_TXOP_LMT_PKT_NUM_8822C) &                           \
+	 BIT_MASK_TXOP_LMT_PKT_NUM_8822C)
+#define BIT_SET_TXOP_LMT_PKT_NUM_8822C(x, v)                                   \
+	(BIT_CLEAR_TXOP_LMT_PKT_NUM_8822C(x) | BIT_TXOP_LMT_PKT_NUM_8822C(v))
+
+/* 2 REG_BAR_TX_CTRL_8822C */
+
+/* 2 REG_P2PON_DIS_TXTIME_8822C */
+
+#define BIT_SHIFT_P2PON_DIS_TXTIME_8822C 0
+#define BIT_MASK_P2PON_DIS_TXTIME_8822C 0xff
+#define BIT_P2PON_DIS_TXTIME_8822C(x)                                          \
+	(((x) & BIT_MASK_P2PON_DIS_TXTIME_8822C)                               \
+	 << BIT_SHIFT_P2PON_DIS_TXTIME_8822C)
+#define BITS_P2PON_DIS_TXTIME_8822C                                            \
+	(BIT_MASK_P2PON_DIS_TXTIME_8822C << BIT_SHIFT_P2PON_DIS_TXTIME_8822C)
+#define BIT_CLEAR_P2PON_DIS_TXTIME_8822C(x)                                    \
+	((x) & (~BITS_P2PON_DIS_TXTIME_8822C))
+#define BIT_GET_P2PON_DIS_TXTIME_8822C(x)                                      \
+	(((x) >> BIT_SHIFT_P2PON_DIS_TXTIME_8822C) &                           \
+	 BIT_MASK_P2PON_DIS_TXTIME_8822C)
+#define BIT_SET_P2PON_DIS_TXTIME_8822C(x, v)                                   \
+	(BIT_CLEAR_P2PON_DIS_TXTIME_8822C(x) | BIT_P2PON_DIS_TXTIME_8822C(v))
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_CCA_TXEN_CNT_8822C */
+#define BIT_ENABLE_STOP_UPDATE_NAV_8822C BIT(21)
+#define BIT_ENABLE_GEN_RANDON_SLOT_TX_8822C BIT(20)
+#define BIT_ENABLE_RANDOM_SHIFT_TX_8822C BIT(19)
+#define BIT_ENABLE_EDCA_REF_FUNCTION_8822C BIT(18)
+#define BIT_CCA_TXEN_CNT_SWITCH_8822C BIT(17)
+#define BIT_CCA_TXEN_CNT_EN_8822C BIT(16)
+
+#define BIT_SHIFT_CCA_TXEN_BIG_CNT_8822C 8
+#define BIT_MASK_CCA_TXEN_BIG_CNT_8822C 0xff
+#define BIT_CCA_TXEN_BIG_CNT_8822C(x)                                          \
+	(((x) & BIT_MASK_CCA_TXEN_BIG_CNT_8822C)                               \
+	 << BIT_SHIFT_CCA_TXEN_BIG_CNT_8822C)
+#define BITS_CCA_TXEN_BIG_CNT_8822C                                            \
+	(BIT_MASK_CCA_TXEN_BIG_CNT_8822C << BIT_SHIFT_CCA_TXEN_BIG_CNT_8822C)
+#define BIT_CLEAR_CCA_TXEN_BIG_CNT_8822C(x)                                    \
+	((x) & (~BITS_CCA_TXEN_BIG_CNT_8822C))
+#define BIT_GET_CCA_TXEN_BIG_CNT_8822C(x)                                      \
+	(((x) >> BIT_SHIFT_CCA_TXEN_BIG_CNT_8822C) &                           \
+	 BIT_MASK_CCA_TXEN_BIG_CNT_8822C)
+#define BIT_SET_CCA_TXEN_BIG_CNT_8822C(x, v)                                   \
+	(BIT_CLEAR_CCA_TXEN_BIG_CNT_8822C(x) | BIT_CCA_TXEN_BIG_CNT_8822C(v))
+
+#define BIT_SHIFT_CCA_TXEN_SMALL_CNT_8822C 0
+#define BIT_MASK_CCA_TXEN_SMALL_CNT_8822C 0xff
+#define BIT_CCA_TXEN_SMALL_CNT_8822C(x)                                        \
+	(((x) & BIT_MASK_CCA_TXEN_SMALL_CNT_8822C)                             \
+	 << BIT_SHIFT_CCA_TXEN_SMALL_CNT_8822C)
+#define BITS_CCA_TXEN_SMALL_CNT_8822C                                          \
+	(BIT_MASK_CCA_TXEN_SMALL_CNT_8822C                                     \
+	 << BIT_SHIFT_CCA_TXEN_SMALL_CNT_8822C)
+#define BIT_CLEAR_CCA_TXEN_SMALL_CNT_8822C(x)                                  \
+	((x) & (~BITS_CCA_TXEN_SMALL_CNT_8822C))
+#define BIT_GET_CCA_TXEN_SMALL_CNT_8822C(x)                                    \
+	(((x) >> BIT_SHIFT_CCA_TXEN_SMALL_CNT_8822C) &                         \
+	 BIT_MASK_CCA_TXEN_SMALL_CNT_8822C)
+#define BIT_SET_CCA_TXEN_SMALL_CNT_8822C(x, v)                                 \
+	(BIT_CLEAR_CCA_TXEN_SMALL_CNT_8822C(x) |                               \
+	 BIT_CCA_TXEN_SMALL_CNT_8822C(v))
+
+/* 2 REG_MAX_INTER_COLLISION_8822C */
+
+#define BIT_SHIFT_MAX_INTER_COLLISION_BK_8822C 24
+#define BIT_MASK_MAX_INTER_COLLISION_BK_8822C 0xff
+#define BIT_MAX_INTER_COLLISION_BK_8822C(x)                                    \
+	(((x) & BIT_MASK_MAX_INTER_COLLISION_BK_8822C)                         \
+	 << BIT_SHIFT_MAX_INTER_COLLISION_BK_8822C)
+#define BITS_MAX_INTER_COLLISION_BK_8822C                                      \
+	(BIT_MASK_MAX_INTER_COLLISION_BK_8822C                                 \
+	 << BIT_SHIFT_MAX_INTER_COLLISION_BK_8822C)
+#define BIT_CLEAR_MAX_INTER_COLLISION_BK_8822C(x)                              \
+	((x) & (~BITS_MAX_INTER_COLLISION_BK_8822C))
+#define BIT_GET_MAX_INTER_COLLISION_BK_8822C(x)                                \
+	(((x) >> BIT_SHIFT_MAX_INTER_COLLISION_BK_8822C) &                     \
+	 BIT_MASK_MAX_INTER_COLLISION_BK_8822C)
+#define BIT_SET_MAX_INTER_COLLISION_BK_8822C(x, v)                             \
+	(BIT_CLEAR_MAX_INTER_COLLISION_BK_8822C(x) |                           \
+	 BIT_MAX_INTER_COLLISION_BK_8822C(v))
+
+#define BIT_SHIFT_MAX_INTER_COLLISION_BE_8822C 16
+#define BIT_MASK_MAX_INTER_COLLISION_BE_8822C 0xff
+#define BIT_MAX_INTER_COLLISION_BE_8822C(x)                                    \
+	(((x) & BIT_MASK_MAX_INTER_COLLISION_BE_8822C)                         \
+	 << BIT_SHIFT_MAX_INTER_COLLISION_BE_8822C)
+#define BITS_MAX_INTER_COLLISION_BE_8822C                                      \
+	(BIT_MASK_MAX_INTER_COLLISION_BE_8822C                                 \
+	 << BIT_SHIFT_MAX_INTER_COLLISION_BE_8822C)
+#define BIT_CLEAR_MAX_INTER_COLLISION_BE_8822C(x)                              \
+	((x) & (~BITS_MAX_INTER_COLLISION_BE_8822C))
+#define BIT_GET_MAX_INTER_COLLISION_BE_8822C(x)                                \
+	(((x) >> BIT_SHIFT_MAX_INTER_COLLISION_BE_8822C) &                     \
+	 BIT_MASK_MAX_INTER_COLLISION_BE_8822C)
+#define BIT_SET_MAX_INTER_COLLISION_BE_8822C(x, v)                             \
+	(BIT_CLEAR_MAX_INTER_COLLISION_BE_8822C(x) |                           \
+	 BIT_MAX_INTER_COLLISION_BE_8822C(v))
+
+#define BIT_SHIFT_MAX_INTER_COLLISION_VI_8822C 8
+#define BIT_MASK_MAX_INTER_COLLISION_VI_8822C 0xff
+#define BIT_MAX_INTER_COLLISION_VI_8822C(x)                                    \
+	(((x) & BIT_MASK_MAX_INTER_COLLISION_VI_8822C)                         \
+	 << BIT_SHIFT_MAX_INTER_COLLISION_VI_8822C)
+#define BITS_MAX_INTER_COLLISION_VI_8822C                                      \
+	(BIT_MASK_MAX_INTER_COLLISION_VI_8822C                                 \
+	 << BIT_SHIFT_MAX_INTER_COLLISION_VI_8822C)
+#define BIT_CLEAR_MAX_INTER_COLLISION_VI_8822C(x)                              \
+	((x) & (~BITS_MAX_INTER_COLLISION_VI_8822C))
+#define BIT_GET_MAX_INTER_COLLISION_VI_8822C(x)                                \
+	(((x) >> BIT_SHIFT_MAX_INTER_COLLISION_VI_8822C) &                     \
+	 BIT_MASK_MAX_INTER_COLLISION_VI_8822C)
+#define BIT_SET_MAX_INTER_COLLISION_VI_8822C(x, v)                             \
+	(BIT_CLEAR_MAX_INTER_COLLISION_VI_8822C(x) |                           \
+	 BIT_MAX_INTER_COLLISION_VI_8822C(v))
+
+#define BIT_SHIFT_MAX_INTER_COLLISION_VO_8822C 0
+#define BIT_MASK_MAX_INTER_COLLISION_VO_8822C 0xff
+#define BIT_MAX_INTER_COLLISION_VO_8822C(x)                                    \
+	(((x) & BIT_MASK_MAX_INTER_COLLISION_VO_8822C)                         \
+	 << BIT_SHIFT_MAX_INTER_COLLISION_VO_8822C)
+#define BITS_MAX_INTER_COLLISION_VO_8822C                                      \
+	(BIT_MASK_MAX_INTER_COLLISION_VO_8822C                                 \
+	 << BIT_SHIFT_MAX_INTER_COLLISION_VO_8822C)
+#define BIT_CLEAR_MAX_INTER_COLLISION_VO_8822C(x)                              \
+	((x) & (~BITS_MAX_INTER_COLLISION_VO_8822C))
+#define BIT_GET_MAX_INTER_COLLISION_VO_8822C(x)                                \
+	(((x) >> BIT_SHIFT_MAX_INTER_COLLISION_VO_8822C) &                     \
+	 BIT_MASK_MAX_INTER_COLLISION_VO_8822C)
+#define BIT_SET_MAX_INTER_COLLISION_VO_8822C(x, v)                             \
+	(BIT_CLEAR_MAX_INTER_COLLISION_VO_8822C(x) |                           \
+	 BIT_MAX_INTER_COLLISION_VO_8822C(v))
+
+/* 2 REG_MAX_INTER_COLLISION_CNT_8822C */
+#define BIT_MAX_INTER_COLLISION_EN_8822C BIT(16)
+
+#define BIT_SHIFT_MAX_INTER_COLLISION_CNT_BK_8822C 12
+#define BIT_MASK_MAX_INTER_COLLISION_CNT_BK_8822C 0xf
+#define BIT_MAX_INTER_COLLISION_CNT_BK_8822C(x)                                \
+	(((x) & BIT_MASK_MAX_INTER_COLLISION_CNT_BK_8822C)                     \
+	 << BIT_SHIFT_MAX_INTER_COLLISION_CNT_BK_8822C)
+#define BITS_MAX_INTER_COLLISION_CNT_BK_8822C                                  \
+	(BIT_MASK_MAX_INTER_COLLISION_CNT_BK_8822C                             \
+	 << BIT_SHIFT_MAX_INTER_COLLISION_CNT_BK_8822C)
+#define BIT_CLEAR_MAX_INTER_COLLISION_CNT_BK_8822C(x)                          \
+	((x) & (~BITS_MAX_INTER_COLLISION_CNT_BK_8822C))
+#define BIT_GET_MAX_INTER_COLLISION_CNT_BK_8822C(x)                            \
+	(((x) >> BIT_SHIFT_MAX_INTER_COLLISION_CNT_BK_8822C) &                 \
+	 BIT_MASK_MAX_INTER_COLLISION_CNT_BK_8822C)
+#define BIT_SET_MAX_INTER_COLLISION_CNT_BK_8822C(x, v)                         \
+	(BIT_CLEAR_MAX_INTER_COLLISION_CNT_BK_8822C(x) |                       \
+	 BIT_MAX_INTER_COLLISION_CNT_BK_8822C(v))
+
+#define BIT_SHIFT_MAX_INTER_COLLISION_CNT_BE_8822C 8
+#define BIT_MASK_MAX_INTER_COLLISION_CNT_BE_8822C 0xf
+#define BIT_MAX_INTER_COLLISION_CNT_BE_8822C(x)                                \
+	(((x) & BIT_MASK_MAX_INTER_COLLISION_CNT_BE_8822C)                     \
+	 << BIT_SHIFT_MAX_INTER_COLLISION_CNT_BE_8822C)
+#define BITS_MAX_INTER_COLLISION_CNT_BE_8822C                                  \
+	(BIT_MASK_MAX_INTER_COLLISION_CNT_BE_8822C                             \
+	 << BIT_SHIFT_MAX_INTER_COLLISION_CNT_BE_8822C)
+#define BIT_CLEAR_MAX_INTER_COLLISION_CNT_BE_8822C(x)                          \
+	((x) & (~BITS_MAX_INTER_COLLISION_CNT_BE_8822C))
+#define BIT_GET_MAX_INTER_COLLISION_CNT_BE_8822C(x)                            \
+	(((x) >> BIT_SHIFT_MAX_INTER_COLLISION_CNT_BE_8822C) &                 \
+	 BIT_MASK_MAX_INTER_COLLISION_CNT_BE_8822C)
+#define BIT_SET_MAX_INTER_COLLISION_CNT_BE_8822C(x, v)                         \
+	(BIT_CLEAR_MAX_INTER_COLLISION_CNT_BE_8822C(x) |                       \
+	 BIT_MAX_INTER_COLLISION_CNT_BE_8822C(v))
+
+#define BIT_SHIFT_MAX_INTER_COLLISION_CNT_VI_8822C 4
+#define BIT_MASK_MAX_INTER_COLLISION_CNT_VI_8822C 0xf
+#define BIT_MAX_INTER_COLLISION_CNT_VI_8822C(x)                                \
+	(((x) & BIT_MASK_MAX_INTER_COLLISION_CNT_VI_8822C)                     \
+	 << BIT_SHIFT_MAX_INTER_COLLISION_CNT_VI_8822C)
+#define BITS_MAX_INTER_COLLISION_CNT_VI_8822C                                  \
+	(BIT_MASK_MAX_INTER_COLLISION_CNT_VI_8822C                             \
+	 << BIT_SHIFT_MAX_INTER_COLLISION_CNT_VI_8822C)
+#define BIT_CLEAR_MAX_INTER_COLLISION_CNT_VI_8822C(x)                          \
+	((x) & (~BITS_MAX_INTER_COLLISION_CNT_VI_8822C))
+#define BIT_GET_MAX_INTER_COLLISION_CNT_VI_8822C(x)                            \
+	(((x) >> BIT_SHIFT_MAX_INTER_COLLISION_CNT_VI_8822C) &                 \
+	 BIT_MASK_MAX_INTER_COLLISION_CNT_VI_8822C)
+#define BIT_SET_MAX_INTER_COLLISION_CNT_VI_8822C(x, v)                         \
+	(BIT_CLEAR_MAX_INTER_COLLISION_CNT_VI_8822C(x) |                       \
+	 BIT_MAX_INTER_COLLISION_CNT_VI_8822C(v))
+
+#define BIT_SHIFT_MAX_INTER_COLLISION_CNT_VO_8822C 0
+#define BIT_MASK_MAX_INTER_COLLISION_CNT_VO_8822C 0xf
+#define BIT_MAX_INTER_COLLISION_CNT_VO_8822C(x)                                \
+	(((x) & BIT_MASK_MAX_INTER_COLLISION_CNT_VO_8822C)                     \
+	 << BIT_SHIFT_MAX_INTER_COLLISION_CNT_VO_8822C)
+#define BITS_MAX_INTER_COLLISION_CNT_VO_8822C                                  \
+	(BIT_MASK_MAX_INTER_COLLISION_CNT_VO_8822C                             \
+	 << BIT_SHIFT_MAX_INTER_COLLISION_CNT_VO_8822C)
+#define BIT_CLEAR_MAX_INTER_COLLISION_CNT_VO_8822C(x)                          \
+	((x) & (~BITS_MAX_INTER_COLLISION_CNT_VO_8822C))
+#define BIT_GET_MAX_INTER_COLLISION_CNT_VO_8822C(x)                            \
+	(((x) >> BIT_SHIFT_MAX_INTER_COLLISION_CNT_VO_8822C) &                 \
+	 BIT_MASK_MAX_INTER_COLLISION_CNT_VO_8822C)
+#define BIT_SET_MAX_INTER_COLLISION_CNT_VO_8822C(x, v)                         \
+	(BIT_CLEAR_MAX_INTER_COLLISION_CNT_VO_8822C(x) |                       \
+	 BIT_MAX_INTER_COLLISION_CNT_VO_8822C(v))
+
+/* 2 REG_TBTT_PROHIBIT_8822C */
+
+#define BIT_SHIFT_TBTT_HOLD_TIME_AP_8822C 8
+#define BIT_MASK_TBTT_HOLD_TIME_AP_8822C 0xfff
+#define BIT_TBTT_HOLD_TIME_AP_8822C(x)                                         \
+	(((x) & BIT_MASK_TBTT_HOLD_TIME_AP_8822C)                              \
+	 << BIT_SHIFT_TBTT_HOLD_TIME_AP_8822C)
+#define BITS_TBTT_HOLD_TIME_AP_8822C                                           \
+	(BIT_MASK_TBTT_HOLD_TIME_AP_8822C << BIT_SHIFT_TBTT_HOLD_TIME_AP_8822C)
+#define BIT_CLEAR_TBTT_HOLD_TIME_AP_8822C(x)                                   \
+	((x) & (~BITS_TBTT_HOLD_TIME_AP_8822C))
+#define BIT_GET_TBTT_HOLD_TIME_AP_8822C(x)                                     \
+	(((x) >> BIT_SHIFT_TBTT_HOLD_TIME_AP_8822C) &                          \
+	 BIT_MASK_TBTT_HOLD_TIME_AP_8822C)
+#define BIT_SET_TBTT_HOLD_TIME_AP_8822C(x, v)                                  \
+	(BIT_CLEAR_TBTT_HOLD_TIME_AP_8822C(x) | BIT_TBTT_HOLD_TIME_AP_8822C(v))
+
+#define BIT_SHIFT_TBTT_PROHIBIT_SETUP_8822C 0
+#define BIT_MASK_TBTT_PROHIBIT_SETUP_8822C 0xf
+#define BIT_TBTT_PROHIBIT_SETUP_8822C(x)                                       \
+	(((x) & BIT_MASK_TBTT_PROHIBIT_SETUP_8822C)                            \
+	 << BIT_SHIFT_TBTT_PROHIBIT_SETUP_8822C)
+#define BITS_TBTT_PROHIBIT_SETUP_8822C                                         \
+	(BIT_MASK_TBTT_PROHIBIT_SETUP_8822C                                    \
+	 << BIT_SHIFT_TBTT_PROHIBIT_SETUP_8822C)
+#define BIT_CLEAR_TBTT_PROHIBIT_SETUP_8822C(x)                                 \
+	((x) & (~BITS_TBTT_PROHIBIT_SETUP_8822C))
+#define BIT_GET_TBTT_PROHIBIT_SETUP_8822C(x)                                   \
+	(((x) >> BIT_SHIFT_TBTT_PROHIBIT_SETUP_8822C) &                        \
+	 BIT_MASK_TBTT_PROHIBIT_SETUP_8822C)
+#define BIT_SET_TBTT_PROHIBIT_SETUP_8822C(x, v)                                \
+	(BIT_CLEAR_TBTT_PROHIBIT_SETUP_8822C(x) |                              \
+	 BIT_TBTT_PROHIBIT_SETUP_8822C(v))
+
+/* 2 REG_P2PPS_STATE_8822C */
+#define BIT_POWER_STATE_8822C BIT(7)
+#define BIT_CTWINDOW_ON_8822C BIT(6)
+#define BIT_BEACON_AREA_ON_8822C BIT(5)
+#define BIT_CTWIN_EARLY_DISTX_8822C BIT(4)
+#define BIT_NOA1_OFF_PERIOD_8822C BIT(3)
+#define BIT_FORCE_DOZE1_8822C BIT(2)
+#define BIT_NOA0_OFF_PERIOD_8822C BIT(1)
+#define BIT_FORCE_DOZE0_8822C BIT(0)
+
+/* 2 REG_RD_NAV_NXT_8822C */
+
+#define BIT_SHIFT_RD_NAV_PROT_NXT_8822C 0
+#define BIT_MASK_RD_NAV_PROT_NXT_8822C 0xffff
+#define BIT_RD_NAV_PROT_NXT_8822C(x)                                           \
+	(((x) & BIT_MASK_RD_NAV_PROT_NXT_8822C)                                \
+	 << BIT_SHIFT_RD_NAV_PROT_NXT_8822C)
+#define BITS_RD_NAV_PROT_NXT_8822C                                             \
+	(BIT_MASK_RD_NAV_PROT_NXT_8822C << BIT_SHIFT_RD_NAV_PROT_NXT_8822C)
+#define BIT_CLEAR_RD_NAV_PROT_NXT_8822C(x) ((x) & (~BITS_RD_NAV_PROT_NXT_8822C))
+#define BIT_GET_RD_NAV_PROT_NXT_8822C(x)                                       \
+	(((x) >> BIT_SHIFT_RD_NAV_PROT_NXT_8822C) &                            \
+	 BIT_MASK_RD_NAV_PROT_NXT_8822C)
+#define BIT_SET_RD_NAV_PROT_NXT_8822C(x, v)                                    \
+	(BIT_CLEAR_RD_NAV_PROT_NXT_8822C(x) | BIT_RD_NAV_PROT_NXT_8822C(v))
+
+/* 2 REG_NAV_PROT_LEN_8822C */
+
+#define BIT_SHIFT_NAV_PROT_LEN_8822C 0
+#define BIT_MASK_NAV_PROT_LEN_8822C 0xffff
+#define BIT_NAV_PROT_LEN_8822C(x)                                              \
+	(((x) & BIT_MASK_NAV_PROT_LEN_8822C) << BIT_SHIFT_NAV_PROT_LEN_8822C)
+#define BITS_NAV_PROT_LEN_8822C                                                \
+	(BIT_MASK_NAV_PROT_LEN_8822C << BIT_SHIFT_NAV_PROT_LEN_8822C)
+#define BIT_CLEAR_NAV_PROT_LEN_8822C(x) ((x) & (~BITS_NAV_PROT_LEN_8822C))
+#define BIT_GET_NAV_PROT_LEN_8822C(x)                                          \
+	(((x) >> BIT_SHIFT_NAV_PROT_LEN_8822C) & BIT_MASK_NAV_PROT_LEN_8822C)
+#define BIT_SET_NAV_PROT_LEN_8822C(x, v)                                       \
+	(BIT_CLEAR_NAV_PROT_LEN_8822C(x) | BIT_NAV_PROT_LEN_8822C(v))
+
+/* 2 REG_FTM_PTT_8822C */
+
+#define BIT_SHIFT_FTM_PTT_TSF_R2T_SEL_8822C 22
+#define BIT_MASK_FTM_PTT_TSF_R2T_SEL_8822C 0x7
+#define BIT_FTM_PTT_TSF_R2T_SEL_8822C(x)                                       \
+	(((x) & BIT_MASK_FTM_PTT_TSF_R2T_SEL_8822C)                            \
+	 << BIT_SHIFT_FTM_PTT_TSF_R2T_SEL_8822C)
+#define BITS_FTM_PTT_TSF_R2T_SEL_8822C                                         \
+	(BIT_MASK_FTM_PTT_TSF_R2T_SEL_8822C                                    \
+	 << BIT_SHIFT_FTM_PTT_TSF_R2T_SEL_8822C)
+#define BIT_CLEAR_FTM_PTT_TSF_R2T_SEL_8822C(x)                                 \
+	((x) & (~BITS_FTM_PTT_TSF_R2T_SEL_8822C))
+#define BIT_GET_FTM_PTT_TSF_R2T_SEL_8822C(x)                                   \
+	(((x) >> BIT_SHIFT_FTM_PTT_TSF_R2T_SEL_8822C) &                        \
+	 BIT_MASK_FTM_PTT_TSF_R2T_SEL_8822C)
+#define BIT_SET_FTM_PTT_TSF_R2T_SEL_8822C(x, v)                                \
+	(BIT_CLEAR_FTM_PTT_TSF_R2T_SEL_8822C(x) |                              \
+	 BIT_FTM_PTT_TSF_R2T_SEL_8822C(v))
+
+#define BIT_SHIFT_FTM_PTT_TSF_T2R_SEL_8822C 19
+#define BIT_MASK_FTM_PTT_TSF_T2R_SEL_8822C 0x7
+#define BIT_FTM_PTT_TSF_T2R_SEL_8822C(x)                                       \
+	(((x) & BIT_MASK_FTM_PTT_TSF_T2R_SEL_8822C)                            \
+	 << BIT_SHIFT_FTM_PTT_TSF_T2R_SEL_8822C)
+#define BITS_FTM_PTT_TSF_T2R_SEL_8822C                                         \
+	(BIT_MASK_FTM_PTT_TSF_T2R_SEL_8822C                                    \
+	 << BIT_SHIFT_FTM_PTT_TSF_T2R_SEL_8822C)
+#define BIT_CLEAR_FTM_PTT_TSF_T2R_SEL_8822C(x)                                 \
+	((x) & (~BITS_FTM_PTT_TSF_T2R_SEL_8822C))
+#define BIT_GET_FTM_PTT_TSF_T2R_SEL_8822C(x)                                   \
+	(((x) >> BIT_SHIFT_FTM_PTT_TSF_T2R_SEL_8822C) &                        \
+	 BIT_MASK_FTM_PTT_TSF_T2R_SEL_8822C)
+#define BIT_SET_FTM_PTT_TSF_T2R_SEL_8822C(x, v)                                \
+	(BIT_CLEAR_FTM_PTT_TSF_T2R_SEL_8822C(x) |                              \
+	 BIT_FTM_PTT_TSF_T2R_SEL_8822C(v))
+
+#define BIT_SHIFT_FTM_PTT_TSF_SEL_8822C 16
+#define BIT_MASK_FTM_PTT_TSF_SEL_8822C 0x7
+#define BIT_FTM_PTT_TSF_SEL_8822C(x)                                           \
+	(((x) & BIT_MASK_FTM_PTT_TSF_SEL_8822C)                                \
+	 << BIT_SHIFT_FTM_PTT_TSF_SEL_8822C)
+#define BITS_FTM_PTT_TSF_SEL_8822C                                             \
+	(BIT_MASK_FTM_PTT_TSF_SEL_8822C << BIT_SHIFT_FTM_PTT_TSF_SEL_8822C)
+#define BIT_CLEAR_FTM_PTT_TSF_SEL_8822C(x) ((x) & (~BITS_FTM_PTT_TSF_SEL_8822C))
+#define BIT_GET_FTM_PTT_TSF_SEL_8822C(x)                                       \
+	(((x) >> BIT_SHIFT_FTM_PTT_TSF_SEL_8822C) &                            \
+	 BIT_MASK_FTM_PTT_TSF_SEL_8822C)
+#define BIT_SET_FTM_PTT_TSF_SEL_8822C(x, v)                                    \
+	(BIT_CLEAR_FTM_PTT_TSF_SEL_8822C(x) | BIT_FTM_PTT_TSF_SEL_8822C(v))
+
+#define BIT_SHIFT_FTM_PTT_VALUE_8822C 0
+#define BIT_MASK_FTM_PTT_VALUE_8822C 0xffff
+#define BIT_FTM_PTT_VALUE_8822C(x)                                             \
+	(((x) & BIT_MASK_FTM_PTT_VALUE_8822C) << BIT_SHIFT_FTM_PTT_VALUE_8822C)
+#define BITS_FTM_PTT_VALUE_8822C                                               \
+	(BIT_MASK_FTM_PTT_VALUE_8822C << BIT_SHIFT_FTM_PTT_VALUE_8822C)
+#define BIT_CLEAR_FTM_PTT_VALUE_8822C(x) ((x) & (~BITS_FTM_PTT_VALUE_8822C))
+#define BIT_GET_FTM_PTT_VALUE_8822C(x)                                         \
+	(((x) >> BIT_SHIFT_FTM_PTT_VALUE_8822C) & BIT_MASK_FTM_PTT_VALUE_8822C)
+#define BIT_SET_FTM_PTT_VALUE_8822C(x, v)                                      \
+	(BIT_CLEAR_FTM_PTT_VALUE_8822C(x) | BIT_FTM_PTT_VALUE_8822C(v))
+
+/* 2 REG_FTM_TSF_8822C */
+
+#define BIT_SHIFT_FTM_T2_TSF_8822C 16
+#define BIT_MASK_FTM_T2_TSF_8822C 0xffff
+#define BIT_FTM_T2_TSF_8822C(x)                                                \
+	(((x) & BIT_MASK_FTM_T2_TSF_8822C) << BIT_SHIFT_FTM_T2_TSF_8822C)
+#define BITS_FTM_T2_TSF_8822C                                                  \
+	(BIT_MASK_FTM_T2_TSF_8822C << BIT_SHIFT_FTM_T2_TSF_8822C)
+#define BIT_CLEAR_FTM_T2_TSF_8822C(x) ((x) & (~BITS_FTM_T2_TSF_8822C))
+#define BIT_GET_FTM_T2_TSF_8822C(x)                                            \
+	(((x) >> BIT_SHIFT_FTM_T2_TSF_8822C) & BIT_MASK_FTM_T2_TSF_8822C)
+#define BIT_SET_FTM_T2_TSF_8822C(x, v)                                         \
+	(BIT_CLEAR_FTM_T2_TSF_8822C(x) | BIT_FTM_T2_TSF_8822C(v))
+
+#define BIT_SHIFT_FTM_T1_TSF_8822C 0
+#define BIT_MASK_FTM_T1_TSF_8822C 0xffff
+#define BIT_FTM_T1_TSF_8822C(x)                                                \
+	(((x) & BIT_MASK_FTM_T1_TSF_8822C) << BIT_SHIFT_FTM_T1_TSF_8822C)
+#define BITS_FTM_T1_TSF_8822C                                                  \
+	(BIT_MASK_FTM_T1_TSF_8822C << BIT_SHIFT_FTM_T1_TSF_8822C)
+#define BIT_CLEAR_FTM_T1_TSF_8822C(x) ((x) & (~BITS_FTM_T1_TSF_8822C))
+#define BIT_GET_FTM_T1_TSF_8822C(x)                                            \
+	(((x) >> BIT_SHIFT_FTM_T1_TSF_8822C) & BIT_MASK_FTM_T1_TSF_8822C)
+#define BIT_SET_FTM_T1_TSF_8822C(x, v)                                         \
+	(BIT_CLEAR_FTM_T1_TSF_8822C(x) | BIT_FTM_T1_TSF_8822C(v))
+
+/* 2 REG_BCN_CTRL_8822C */
+#define BIT_DIS_RX_BSSID_FIT_8822C BIT(6)
+#define BIT_P0_EN_TXBCN_RPT_8822C BIT(5)
+#define BIT_DIS_TSF_UDT_8822C BIT(4)
+#define BIT_EN_BCN_FUNCTION_8822C BIT(3)
+#define BIT_P0_EN_RXBCN_RPT_8822C BIT(2)
+#define BIT_EN_P2P_CTWINDOW_8822C BIT(1)
+#define BIT_EN_P2P_BCNQ_AREA_8822C BIT(0)
+
+/* 2 REG_BCN_CTRL_CLINT0_8822C */
+#define BIT_CLI0_DIS_RX_BSSID_FIT_8822C BIT(6)
+#define BIT_CLI0_DIS_TSF_UDT_8822C BIT(4)
+#define BIT_CLI0_EN_BCN_FUNCTION_8822C BIT(3)
+#define BIT_CLI0_EN_RXBCN_RPT_8822C BIT(2)
+#define BIT_CLI0_ENP2P_CTWINDOW_8822C BIT(1)
+#define BIT_CLI0_ENP2P_BCNQ_AREA_8822C BIT(0)
+
+/* 2 REG_MBID_NUM_8822C */
+#define BIT_EN_PRE_DL_BEACON_8822C BIT(3)
+
+#define BIT_SHIFT_MBID_BCN_NUM_8822C 0
+#define BIT_MASK_MBID_BCN_NUM_8822C 0x7
+#define BIT_MBID_BCN_NUM_8822C(x)                                              \
+	(((x) & BIT_MASK_MBID_BCN_NUM_8822C) << BIT_SHIFT_MBID_BCN_NUM_8822C)
+#define BITS_MBID_BCN_NUM_8822C                                                \
+	(BIT_MASK_MBID_BCN_NUM_8822C << BIT_SHIFT_MBID_BCN_NUM_8822C)
+#define BIT_CLEAR_MBID_BCN_NUM_8822C(x) ((x) & (~BITS_MBID_BCN_NUM_8822C))
+#define BIT_GET_MBID_BCN_NUM_8822C(x)                                          \
+	(((x) >> BIT_SHIFT_MBID_BCN_NUM_8822C) & BIT_MASK_MBID_BCN_NUM_8822C)
+#define BIT_SET_MBID_BCN_NUM_8822C(x, v)                                       \
+	(BIT_CLEAR_MBID_BCN_NUM_8822C(x) | BIT_MBID_BCN_NUM_8822C(v))
+
+/* 2 REG_DUAL_TSF_RST_8822C */
+#define BIT_FREECNT_RST_8822C BIT(5)
+#define BIT_TSFTR_CLI3_RST_8822C BIT(4)
+#define BIT_TSFTR_CLI2_RST_8822C BIT(3)
+#define BIT_TSFTR_CLI1_RST_8822C BIT(2)
+#define BIT_TSFTR_CLI0_RST_8822C BIT(1)
+#define BIT_TSFTR_RST_8822C BIT(0)
+
+/* 2 REG_MBSSID_BCN_SPACE_8822C */
+
+#define BIT_SHIFT_BCN_TIMER_SEL_FWRD_8822C 28
+#define BIT_MASK_BCN_TIMER_SEL_FWRD_8822C 0x7
+#define BIT_BCN_TIMER_SEL_FWRD_8822C(x)                                        \
+	(((x) & BIT_MASK_BCN_TIMER_SEL_FWRD_8822C)                             \
+	 << BIT_SHIFT_BCN_TIMER_SEL_FWRD_8822C)
+#define BITS_BCN_TIMER_SEL_FWRD_8822C                                          \
+	(BIT_MASK_BCN_TIMER_SEL_FWRD_8822C                                     \
+	 << BIT_SHIFT_BCN_TIMER_SEL_FWRD_8822C)
+#define BIT_CLEAR_BCN_TIMER_SEL_FWRD_8822C(x)                                  \
+	((x) & (~BITS_BCN_TIMER_SEL_FWRD_8822C))
+#define BIT_GET_BCN_TIMER_SEL_FWRD_8822C(x)                                    \
+	(((x) >> BIT_SHIFT_BCN_TIMER_SEL_FWRD_8822C) &                         \
+	 BIT_MASK_BCN_TIMER_SEL_FWRD_8822C)
+#define BIT_SET_BCN_TIMER_SEL_FWRD_8822C(x, v)                                 \
+	(BIT_CLEAR_BCN_TIMER_SEL_FWRD_8822C(x) |                               \
+	 BIT_BCN_TIMER_SEL_FWRD_8822C(v))
+
+#define BIT_SHIFT_BCN_SPACE_CLINT0_8822C 16
+#define BIT_MASK_BCN_SPACE_CLINT0_8822C 0xfff
+#define BIT_BCN_SPACE_CLINT0_8822C(x)                                          \
+	(((x) & BIT_MASK_BCN_SPACE_CLINT0_8822C)                               \
+	 << BIT_SHIFT_BCN_SPACE_CLINT0_8822C)
+#define BITS_BCN_SPACE_CLINT0_8822C                                            \
+	(BIT_MASK_BCN_SPACE_CLINT0_8822C << BIT_SHIFT_BCN_SPACE_CLINT0_8822C)
+#define BIT_CLEAR_BCN_SPACE_CLINT0_8822C(x)                                    \
+	((x) & (~BITS_BCN_SPACE_CLINT0_8822C))
+#define BIT_GET_BCN_SPACE_CLINT0_8822C(x)                                      \
+	(((x) >> BIT_SHIFT_BCN_SPACE_CLINT0_8822C) &                           \
+	 BIT_MASK_BCN_SPACE_CLINT0_8822C)
+#define BIT_SET_BCN_SPACE_CLINT0_8822C(x, v)                                   \
+	(BIT_CLEAR_BCN_SPACE_CLINT0_8822C(x) | BIT_BCN_SPACE_CLINT0_8822C(v))
+
+#define BIT_SHIFT_BCN_SPACE0_8822C 0
+#define BIT_MASK_BCN_SPACE0_8822C 0xffff
+#define BIT_BCN_SPACE0_8822C(x)                                                \
+	(((x) & BIT_MASK_BCN_SPACE0_8822C) << BIT_SHIFT_BCN_SPACE0_8822C)
+#define BITS_BCN_SPACE0_8822C                                                  \
+	(BIT_MASK_BCN_SPACE0_8822C << BIT_SHIFT_BCN_SPACE0_8822C)
+#define BIT_CLEAR_BCN_SPACE0_8822C(x) ((x) & (~BITS_BCN_SPACE0_8822C))
+#define BIT_GET_BCN_SPACE0_8822C(x)                                            \
+	(((x) >> BIT_SHIFT_BCN_SPACE0_8822C) & BIT_MASK_BCN_SPACE0_8822C)
+#define BIT_SET_BCN_SPACE0_8822C(x, v)                                         \
+	(BIT_CLEAR_BCN_SPACE0_8822C(x) | BIT_BCN_SPACE0_8822C(v))
+
+/* 2 REG_DRVERLYINT_8822C */
+
+#define BIT_SHIFT_DRVERLYITV_8822C 0
+#define BIT_MASK_DRVERLYITV_8822C 0xff
+#define BIT_DRVERLYITV_8822C(x)                                                \
+	(((x) & BIT_MASK_DRVERLYITV_8822C) << BIT_SHIFT_DRVERLYITV_8822C)
+#define BITS_DRVERLYITV_8822C                                                  \
+	(BIT_MASK_DRVERLYITV_8822C << BIT_SHIFT_DRVERLYITV_8822C)
+#define BIT_CLEAR_DRVERLYITV_8822C(x) ((x) & (~BITS_DRVERLYITV_8822C))
+#define BIT_GET_DRVERLYITV_8822C(x)                                            \
+	(((x) >> BIT_SHIFT_DRVERLYITV_8822C) & BIT_MASK_DRVERLYITV_8822C)
+#define BIT_SET_DRVERLYITV_8822C(x, v)                                         \
+	(BIT_CLEAR_DRVERLYITV_8822C(x) | BIT_DRVERLYITV_8822C(v))
+
+/* 2 REG_BCNDMATIM_8822C */
+
+#define BIT_SHIFT_BCNDMATIM_8822C 0
+#define BIT_MASK_BCNDMATIM_8822C 0xff
+#define BIT_BCNDMATIM_8822C(x)                                                 \
+	(((x) & BIT_MASK_BCNDMATIM_8822C) << BIT_SHIFT_BCNDMATIM_8822C)
+#define BITS_BCNDMATIM_8822C                                                   \
+	(BIT_MASK_BCNDMATIM_8822C << BIT_SHIFT_BCNDMATIM_8822C)
+#define BIT_CLEAR_BCNDMATIM_8822C(x) ((x) & (~BITS_BCNDMATIM_8822C))
+#define BIT_GET_BCNDMATIM_8822C(x)                                             \
+	(((x) >> BIT_SHIFT_BCNDMATIM_8822C) & BIT_MASK_BCNDMATIM_8822C)
+#define BIT_SET_BCNDMATIM_8822C(x, v)                                          \
+	(BIT_CLEAR_BCNDMATIM_8822C(x) | BIT_BCNDMATIM_8822C(v))
+
+/* 2 REG_ATIMWND_8822C */
+
+#define BIT_SHIFT_ATIMWND0_8822C 0
+#define BIT_MASK_ATIMWND0_8822C 0xffff
+#define BIT_ATIMWND0_8822C(x)                                                  \
+	(((x) & BIT_MASK_ATIMWND0_8822C) << BIT_SHIFT_ATIMWND0_8822C)
+#define BITS_ATIMWND0_8822C                                                    \
+	(BIT_MASK_ATIMWND0_8822C << BIT_SHIFT_ATIMWND0_8822C)
+#define BIT_CLEAR_ATIMWND0_8822C(x) ((x) & (~BITS_ATIMWND0_8822C))
+#define BIT_GET_ATIMWND0_8822C(x)                                              \
+	(((x) >> BIT_SHIFT_ATIMWND0_8822C) & BIT_MASK_ATIMWND0_8822C)
+#define BIT_SET_ATIMWND0_8822C(x, v)                                           \
+	(BIT_CLEAR_ATIMWND0_8822C(x) | BIT_ATIMWND0_8822C(v))
+
+/* 2 REG_USTIME_TSF_8822C */
+
+#define BIT_SHIFT_USTIME_TSF_V1_8822C 0
+#define BIT_MASK_USTIME_TSF_V1_8822C 0xff
+#define BIT_USTIME_TSF_V1_8822C(x)                                             \
+	(((x) & BIT_MASK_USTIME_TSF_V1_8822C) << BIT_SHIFT_USTIME_TSF_V1_8822C)
+#define BITS_USTIME_TSF_V1_8822C                                               \
+	(BIT_MASK_USTIME_TSF_V1_8822C << BIT_SHIFT_USTIME_TSF_V1_8822C)
+#define BIT_CLEAR_USTIME_TSF_V1_8822C(x) ((x) & (~BITS_USTIME_TSF_V1_8822C))
+#define BIT_GET_USTIME_TSF_V1_8822C(x)                                         \
+	(((x) >> BIT_SHIFT_USTIME_TSF_V1_8822C) & BIT_MASK_USTIME_TSF_V1_8822C)
+#define BIT_SET_USTIME_TSF_V1_8822C(x, v)                                      \
+	(BIT_CLEAR_USTIME_TSF_V1_8822C(x) | BIT_USTIME_TSF_V1_8822C(v))
+
+/* 2 REG_BCN_MAX_ERR_8822C */
+
+#define BIT_SHIFT_BCN_MAX_ERR_8822C 0
+#define BIT_MASK_BCN_MAX_ERR_8822C 0xff
+#define BIT_BCN_MAX_ERR_8822C(x)                                               \
+	(((x) & BIT_MASK_BCN_MAX_ERR_8822C) << BIT_SHIFT_BCN_MAX_ERR_8822C)
+#define BITS_BCN_MAX_ERR_8822C                                                 \
+	(BIT_MASK_BCN_MAX_ERR_8822C << BIT_SHIFT_BCN_MAX_ERR_8822C)
+#define BIT_CLEAR_BCN_MAX_ERR_8822C(x) ((x) & (~BITS_BCN_MAX_ERR_8822C))
+#define BIT_GET_BCN_MAX_ERR_8822C(x)                                           \
+	(((x) >> BIT_SHIFT_BCN_MAX_ERR_8822C) & BIT_MASK_BCN_MAX_ERR_8822C)
+#define BIT_SET_BCN_MAX_ERR_8822C(x, v)                                        \
+	(BIT_CLEAR_BCN_MAX_ERR_8822C(x) | BIT_BCN_MAX_ERR_8822C(v))
+
+/* 2 REG_RXTSF_OFFSET_CCK_8822C */
+
+#define BIT_SHIFT_CCK_RXTSF_OFFSET_8822C 0
+#define BIT_MASK_CCK_RXTSF_OFFSET_8822C 0xff
+#define BIT_CCK_RXTSF_OFFSET_8822C(x)                                          \
+	(((x) & BIT_MASK_CCK_RXTSF_OFFSET_8822C)                               \
+	 << BIT_SHIFT_CCK_RXTSF_OFFSET_8822C)
+#define BITS_CCK_RXTSF_OFFSET_8822C                                            \
+	(BIT_MASK_CCK_RXTSF_OFFSET_8822C << BIT_SHIFT_CCK_RXTSF_OFFSET_8822C)
+#define BIT_CLEAR_CCK_RXTSF_OFFSET_8822C(x)                                    \
+	((x) & (~BITS_CCK_RXTSF_OFFSET_8822C))
+#define BIT_GET_CCK_RXTSF_OFFSET_8822C(x)                                      \
+	(((x) >> BIT_SHIFT_CCK_RXTSF_OFFSET_8822C) &                           \
+	 BIT_MASK_CCK_RXTSF_OFFSET_8822C)
+#define BIT_SET_CCK_RXTSF_OFFSET_8822C(x, v)                                   \
+	(BIT_CLEAR_CCK_RXTSF_OFFSET_8822C(x) | BIT_CCK_RXTSF_OFFSET_8822C(v))
+
+/* 2 REG_RXTSF_OFFSET_OFDM_8822C */
+
+#define BIT_SHIFT_OFDM_RXTSF_OFFSET_8822C 0
+#define BIT_MASK_OFDM_RXTSF_OFFSET_8822C 0xff
+#define BIT_OFDM_RXTSF_OFFSET_8822C(x)                                         \
+	(((x) & BIT_MASK_OFDM_RXTSF_OFFSET_8822C)                              \
+	 << BIT_SHIFT_OFDM_RXTSF_OFFSET_8822C)
+#define BITS_OFDM_RXTSF_OFFSET_8822C                                           \
+	(BIT_MASK_OFDM_RXTSF_OFFSET_8822C << BIT_SHIFT_OFDM_RXTSF_OFFSET_8822C)
+#define BIT_CLEAR_OFDM_RXTSF_OFFSET_8822C(x)                                   \
+	((x) & (~BITS_OFDM_RXTSF_OFFSET_8822C))
+#define BIT_GET_OFDM_RXTSF_OFFSET_8822C(x)                                     \
+	(((x) >> BIT_SHIFT_OFDM_RXTSF_OFFSET_8822C) &                          \
+	 BIT_MASK_OFDM_RXTSF_OFFSET_8822C)
+#define BIT_SET_OFDM_RXTSF_OFFSET_8822C(x, v)                                  \
+	(BIT_CLEAR_OFDM_RXTSF_OFFSET_8822C(x) | BIT_OFDM_RXTSF_OFFSET_8822C(v))
+
+/* 2 REG_TSFTR_8822C */
+
+#define BIT_SHIFT_TSF_TIMER_V1_8822C 0
+#define BIT_MASK_TSF_TIMER_V1_8822C 0xffffffffL
+#define BIT_TSF_TIMER_V1_8822C(x)                                              \
+	(((x) & BIT_MASK_TSF_TIMER_V1_8822C) << BIT_SHIFT_TSF_TIMER_V1_8822C)
+#define BITS_TSF_TIMER_V1_8822C                                                \
+	(BIT_MASK_TSF_TIMER_V1_8822C << BIT_SHIFT_TSF_TIMER_V1_8822C)
+#define BIT_CLEAR_TSF_TIMER_V1_8822C(x) ((x) & (~BITS_TSF_TIMER_V1_8822C))
+#define BIT_GET_TSF_TIMER_V1_8822C(x)                                          \
+	(((x) >> BIT_SHIFT_TSF_TIMER_V1_8822C) & BIT_MASK_TSF_TIMER_V1_8822C)
+#define BIT_SET_TSF_TIMER_V1_8822C(x, v)                                       \
+	(BIT_CLEAR_TSF_TIMER_V1_8822C(x) | BIT_TSF_TIMER_V1_8822C(v))
+
+/* 2 REG_TSFTR_1_8822C */
+
+#define BIT_SHIFT_TSF_TIMER_V2_8822C 0
+#define BIT_MASK_TSF_TIMER_V2_8822C 0xffffffffL
+#define BIT_TSF_TIMER_V2_8822C(x)                                              \
+	(((x) & BIT_MASK_TSF_TIMER_V2_8822C) << BIT_SHIFT_TSF_TIMER_V2_8822C)
+#define BITS_TSF_TIMER_V2_8822C                                                \
+	(BIT_MASK_TSF_TIMER_V2_8822C << BIT_SHIFT_TSF_TIMER_V2_8822C)
+#define BIT_CLEAR_TSF_TIMER_V2_8822C(x) ((x) & (~BITS_TSF_TIMER_V2_8822C))
+#define BIT_GET_TSF_TIMER_V2_8822C(x)                                          \
+	(((x) >> BIT_SHIFT_TSF_TIMER_V2_8822C) & BIT_MASK_TSF_TIMER_V2_8822C)
+#define BIT_SET_TSF_TIMER_V2_8822C(x, v)                                       \
+	(BIT_CLEAR_TSF_TIMER_V2_8822C(x) | BIT_TSF_TIMER_V2_8822C(v))
+
+/* 2 REG_FREERUN_CNT_8822C */
+
+#define BIT_SHIFT_FREERUN_CNT_V1_8822C 0
+#define BIT_MASK_FREERUN_CNT_V1_8822C 0xffffffffL
+#define BIT_FREERUN_CNT_V1_8822C(x)                                            \
+	(((x) & BIT_MASK_FREERUN_CNT_V1_8822C)                                 \
+	 << BIT_SHIFT_FREERUN_CNT_V1_8822C)
+#define BITS_FREERUN_CNT_V1_8822C                                              \
+	(BIT_MASK_FREERUN_CNT_V1_8822C << BIT_SHIFT_FREERUN_CNT_V1_8822C)
+#define BIT_CLEAR_FREERUN_CNT_V1_8822C(x) ((x) & (~BITS_FREERUN_CNT_V1_8822C))
+#define BIT_GET_FREERUN_CNT_V1_8822C(x)                                        \
+	(((x) >> BIT_SHIFT_FREERUN_CNT_V1_8822C) &                             \
+	 BIT_MASK_FREERUN_CNT_V1_8822C)
+#define BIT_SET_FREERUN_CNT_V1_8822C(x, v)                                     \
+	(BIT_CLEAR_FREERUN_CNT_V1_8822C(x) | BIT_FREERUN_CNT_V1_8822C(v))
+
+/* 2 REG_FREERUN_CNT_1_8822C */
+
+#define BIT_SHIFT_FREERUN_CNT_V2_8822C 0
+#define BIT_MASK_FREERUN_CNT_V2_8822C 0xffffffffL
+#define BIT_FREERUN_CNT_V2_8822C(x)                                            \
+	(((x) & BIT_MASK_FREERUN_CNT_V2_8822C)                                 \
+	 << BIT_SHIFT_FREERUN_CNT_V2_8822C)
+#define BITS_FREERUN_CNT_V2_8822C                                              \
+	(BIT_MASK_FREERUN_CNT_V2_8822C << BIT_SHIFT_FREERUN_CNT_V2_8822C)
+#define BIT_CLEAR_FREERUN_CNT_V2_8822C(x) ((x) & (~BITS_FREERUN_CNT_V2_8822C))
+#define BIT_GET_FREERUN_CNT_V2_8822C(x)                                        \
+	(((x) >> BIT_SHIFT_FREERUN_CNT_V2_8822C) &                             \
+	 BIT_MASK_FREERUN_CNT_V2_8822C)
+#define BIT_SET_FREERUN_CNT_V2_8822C(x, v)                                     \
+	(BIT_CLEAR_FREERUN_CNT_V2_8822C(x) | BIT_FREERUN_CNT_V2_8822C(v))
+
+/* 2 REG_ATIMWND1_V1_8822C */
+
+#define BIT_SHIFT_ATIMWND1_V1_8822C 0
+#define BIT_MASK_ATIMWND1_V1_8822C 0xff
+#define BIT_ATIMWND1_V1_8822C(x)                                               \
+	(((x) & BIT_MASK_ATIMWND1_V1_8822C) << BIT_SHIFT_ATIMWND1_V1_8822C)
+#define BITS_ATIMWND1_V1_8822C                                                 \
+	(BIT_MASK_ATIMWND1_V1_8822C << BIT_SHIFT_ATIMWND1_V1_8822C)
+#define BIT_CLEAR_ATIMWND1_V1_8822C(x) ((x) & (~BITS_ATIMWND1_V1_8822C))
+#define BIT_GET_ATIMWND1_V1_8822C(x)                                           \
+	(((x) >> BIT_SHIFT_ATIMWND1_V1_8822C) & BIT_MASK_ATIMWND1_V1_8822C)
+#define BIT_SET_ATIMWND1_V1_8822C(x, v)                                        \
+	(BIT_CLEAR_ATIMWND1_V1_8822C(x) | BIT_ATIMWND1_V1_8822C(v))
+
+/* 2 REG_TBTT_PROHIBIT_INFRA_8822C */
+
+#define BIT_SHIFT_TBTT_PROHIBIT_INFRA_8822C 0
+#define BIT_MASK_TBTT_PROHIBIT_INFRA_8822C 0xff
+#define BIT_TBTT_PROHIBIT_INFRA_8822C(x)                                       \
+	(((x) & BIT_MASK_TBTT_PROHIBIT_INFRA_8822C)                            \
+	 << BIT_SHIFT_TBTT_PROHIBIT_INFRA_8822C)
+#define BITS_TBTT_PROHIBIT_INFRA_8822C                                         \
+	(BIT_MASK_TBTT_PROHIBIT_INFRA_8822C                                    \
+	 << BIT_SHIFT_TBTT_PROHIBIT_INFRA_8822C)
+#define BIT_CLEAR_TBTT_PROHIBIT_INFRA_8822C(x)                                 \
+	((x) & (~BITS_TBTT_PROHIBIT_INFRA_8822C))
+#define BIT_GET_TBTT_PROHIBIT_INFRA_8822C(x)                                   \
+	(((x) >> BIT_SHIFT_TBTT_PROHIBIT_INFRA_8822C) &                        \
+	 BIT_MASK_TBTT_PROHIBIT_INFRA_8822C)
+#define BIT_SET_TBTT_PROHIBIT_INFRA_8822C(x, v)                                \
+	(BIT_CLEAR_TBTT_PROHIBIT_INFRA_8822C(x) |                              \
+	 BIT_TBTT_PROHIBIT_INFRA_8822C(v))
+
+/* 2 REG_CTWND_8822C */
+
+#define BIT_SHIFT_CTWND_8822C 0
+#define BIT_MASK_CTWND_8822C 0xff
+#define BIT_CTWND_8822C(x)                                                     \
+	(((x) & BIT_MASK_CTWND_8822C) << BIT_SHIFT_CTWND_8822C)
+#define BITS_CTWND_8822C (BIT_MASK_CTWND_8822C << BIT_SHIFT_CTWND_8822C)
+#define BIT_CLEAR_CTWND_8822C(x) ((x) & (~BITS_CTWND_8822C))
+#define BIT_GET_CTWND_8822C(x)                                                 \
+	(((x) >> BIT_SHIFT_CTWND_8822C) & BIT_MASK_CTWND_8822C)
+#define BIT_SET_CTWND_8822C(x, v)                                              \
+	(BIT_CLEAR_CTWND_8822C(x) | BIT_CTWND_8822C(v))
+
+/* 2 REG_BCNIVLCUNT_8822C */
+
+#define BIT_SHIFT_BCNIVLCUNT_8822C 0
+#define BIT_MASK_BCNIVLCUNT_8822C 0x7f
+#define BIT_BCNIVLCUNT_8822C(x)                                                \
+	(((x) & BIT_MASK_BCNIVLCUNT_8822C) << BIT_SHIFT_BCNIVLCUNT_8822C)
+#define BITS_BCNIVLCUNT_8822C                                                  \
+	(BIT_MASK_BCNIVLCUNT_8822C << BIT_SHIFT_BCNIVLCUNT_8822C)
+#define BIT_CLEAR_BCNIVLCUNT_8822C(x) ((x) & (~BITS_BCNIVLCUNT_8822C))
+#define BIT_GET_BCNIVLCUNT_8822C(x)                                            \
+	(((x) >> BIT_SHIFT_BCNIVLCUNT_8822C) & BIT_MASK_BCNIVLCUNT_8822C)
+#define BIT_SET_BCNIVLCUNT_8822C(x, v)                                         \
+	(BIT_CLEAR_BCNIVLCUNT_8822C(x) | BIT_BCNIVLCUNT_8822C(v))
+
+/* 2 REG_BCNDROPCTRL_8822C */
+#define BIT_BEACON_DROP_EN_8822C BIT(7)
+
+#define BIT_SHIFT_BEACON_DROP_IVL_8822C 0
+#define BIT_MASK_BEACON_DROP_IVL_8822C 0x7f
+#define BIT_BEACON_DROP_IVL_8822C(x)                                           \
+	(((x) & BIT_MASK_BEACON_DROP_IVL_8822C)                                \
+	 << BIT_SHIFT_BEACON_DROP_IVL_8822C)
+#define BITS_BEACON_DROP_IVL_8822C                                             \
+	(BIT_MASK_BEACON_DROP_IVL_8822C << BIT_SHIFT_BEACON_DROP_IVL_8822C)
+#define BIT_CLEAR_BEACON_DROP_IVL_8822C(x) ((x) & (~BITS_BEACON_DROP_IVL_8822C))
+#define BIT_GET_BEACON_DROP_IVL_8822C(x)                                       \
+	(((x) >> BIT_SHIFT_BEACON_DROP_IVL_8822C) &                            \
+	 BIT_MASK_BEACON_DROP_IVL_8822C)
+#define BIT_SET_BEACON_DROP_IVL_8822C(x, v)                                    \
+	(BIT_CLEAR_BEACON_DROP_IVL_8822C(x) | BIT_BEACON_DROP_IVL_8822C(v))
+
+/* 2 REG_HGQ_TIMEOUT_PERIOD_8822C */
+
+#define BIT_SHIFT_HGQ_TIMEOUT_PERIOD_8822C 0
+#define BIT_MASK_HGQ_TIMEOUT_PERIOD_8822C 0xff
+#define BIT_HGQ_TIMEOUT_PERIOD_8822C(x)                                        \
+	(((x) & BIT_MASK_HGQ_TIMEOUT_PERIOD_8822C)                             \
+	 << BIT_SHIFT_HGQ_TIMEOUT_PERIOD_8822C)
+#define BITS_HGQ_TIMEOUT_PERIOD_8822C                                          \
+	(BIT_MASK_HGQ_TIMEOUT_PERIOD_8822C                                     \
+	 << BIT_SHIFT_HGQ_TIMEOUT_PERIOD_8822C)
+#define BIT_CLEAR_HGQ_TIMEOUT_PERIOD_8822C(x)                                  \
+	((x) & (~BITS_HGQ_TIMEOUT_PERIOD_8822C))
+#define BIT_GET_HGQ_TIMEOUT_PERIOD_8822C(x)                                    \
+	(((x) >> BIT_SHIFT_HGQ_TIMEOUT_PERIOD_8822C) &                         \
+	 BIT_MASK_HGQ_TIMEOUT_PERIOD_8822C)
+#define BIT_SET_HGQ_TIMEOUT_PERIOD_8822C(x, v)                                 \
+	(BIT_CLEAR_HGQ_TIMEOUT_PERIOD_8822C(x) |                               \
+	 BIT_HGQ_TIMEOUT_PERIOD_8822C(v))
+
+/* 2 REG_TXCMD_TIMEOUT_PERIOD_8822C */
+
+#define BIT_SHIFT_TXCMD_TIMEOUT_PERIOD_8822C 0
+#define BIT_MASK_TXCMD_TIMEOUT_PERIOD_8822C 0xff
+#define BIT_TXCMD_TIMEOUT_PERIOD_8822C(x)                                      \
+	(((x) & BIT_MASK_TXCMD_TIMEOUT_PERIOD_8822C)                           \
+	 << BIT_SHIFT_TXCMD_TIMEOUT_PERIOD_8822C)
+#define BITS_TXCMD_TIMEOUT_PERIOD_8822C                                        \
+	(BIT_MASK_TXCMD_TIMEOUT_PERIOD_8822C                                   \
+	 << BIT_SHIFT_TXCMD_TIMEOUT_PERIOD_8822C)
+#define BIT_CLEAR_TXCMD_TIMEOUT_PERIOD_8822C(x)                                \
+	((x) & (~BITS_TXCMD_TIMEOUT_PERIOD_8822C))
+#define BIT_GET_TXCMD_TIMEOUT_PERIOD_8822C(x)                                  \
+	(((x) >> BIT_SHIFT_TXCMD_TIMEOUT_PERIOD_8822C) &                       \
+	 BIT_MASK_TXCMD_TIMEOUT_PERIOD_8822C)
+#define BIT_SET_TXCMD_TIMEOUT_PERIOD_8822C(x, v)                               \
+	(BIT_CLEAR_TXCMD_TIMEOUT_PERIOD_8822C(x) |                             \
+	 BIT_TXCMD_TIMEOUT_PERIOD_8822C(v))
+
+/* 2 REG_MISC_CTRL_8822C */
+#define BIT_DIS_MARK_TSF_US_V2_8822C BIT(7)
+#define BIT_AUTO_SYNC_BY_TBTT_8822C BIT(6)
+#define BIT_DIS_TRX_CAL_BCN_8822C BIT(5)
+#define BIT_DIS_TX_CAL_TBTT_8822C BIT(4)
+#define BIT_EN_FREECNT_8822C BIT(3)
+#define BIT_BCN_AGGRESSION_8822C BIT(2)
+
+#define BIT_SHIFT_DIS_SECONDARY_CCA_8822C 0
+#define BIT_MASK_DIS_SECONDARY_CCA_8822C 0x3
+#define BIT_DIS_SECONDARY_CCA_8822C(x)                                         \
+	(((x) & BIT_MASK_DIS_SECONDARY_CCA_8822C)                              \
+	 << BIT_SHIFT_DIS_SECONDARY_CCA_8822C)
+#define BITS_DIS_SECONDARY_CCA_8822C                                           \
+	(BIT_MASK_DIS_SECONDARY_CCA_8822C << BIT_SHIFT_DIS_SECONDARY_CCA_8822C)
+#define BIT_CLEAR_DIS_SECONDARY_CCA_8822C(x)                                   \
+	((x) & (~BITS_DIS_SECONDARY_CCA_8822C))
+#define BIT_GET_DIS_SECONDARY_CCA_8822C(x)                                     \
+	(((x) >> BIT_SHIFT_DIS_SECONDARY_CCA_8822C) &                          \
+	 BIT_MASK_DIS_SECONDARY_CCA_8822C)
+#define BIT_SET_DIS_SECONDARY_CCA_8822C(x, v)                                  \
+	(BIT_CLEAR_DIS_SECONDARY_CCA_8822C(x) | BIT_DIS_SECONDARY_CCA_8822C(v))
+
+/* 2 REG_BCN_CTRL_CLINT1_8822C */
+#define BIT_CLI1_DIS_RX_BSSID_FIT_8822C BIT(6)
+#define BIT_CLI1_DIS_TSF_UDT_8822C BIT(4)
+#define BIT_CLI1_EN_BCN_FUNCTION_8822C BIT(3)
+#define BIT_CLI1_EN_RXBCN_RPT_8822C BIT(2)
+#define BIT_CLI1_ENP2P_CTWINDOW_8822C BIT(1)
+#define BIT_CLI1_ENP2P_BCNQ_AREA_8822C BIT(0)
+
+/* 2 REG_BCN_CTRL_CLINT2_8822C */
+#define BIT_CLI2_DIS_RX_BSSID_FIT_8822C BIT(6)
+#define BIT_CLI2_DIS_TSF_UDT_8822C BIT(4)
+#define BIT_CLI2_EN_BCN_FUNCTION_8822C BIT(3)
+#define BIT_CLI2_EN_RXBCN_RPT_8822C BIT(2)
+#define BIT_CLI2_ENP2P_CTWINDOW_8822C BIT(1)
+#define BIT_CLI2_ENP2P_BCNQ_AREA_8822C BIT(0)
+
+/* 2 REG_BCN_CTRL_CLINT3_8822C */
+#define BIT_CLI3_DIS_RX_BSSID_FIT_8822C BIT(6)
+#define BIT_CLI3_DIS_TSF_UDT_8822C BIT(4)
+#define BIT_CLI3_EN_BCN_FUNCTION_8822C BIT(3)
+#define BIT_CLI3_EN_RXBCN_RPT_8822C BIT(2)
+#define BIT_CLI3_ENP2P_CTWINDOW_8822C BIT(1)
+#define BIT_CLI3_ENP2P_BCNQ_AREA_8822C BIT(0)
+
+/* 2 REG_EXTEND_CTRL_8822C */
+#define BIT_EN_TSFBIT32_RST_P2P2_8822C BIT(5)
+#define BIT_EN_TSFBIT32_RST_P2P1_8822C BIT(4)
+
+#define BIT_SHIFT_PORT_SEL_8822C 0
+#define BIT_MASK_PORT_SEL_8822C 0x7
+#define BIT_PORT_SEL_8822C(x)                                                  \
+	(((x) & BIT_MASK_PORT_SEL_8822C) << BIT_SHIFT_PORT_SEL_8822C)
+#define BITS_PORT_SEL_8822C                                                    \
+	(BIT_MASK_PORT_SEL_8822C << BIT_SHIFT_PORT_SEL_8822C)
+#define BIT_CLEAR_PORT_SEL_8822C(x) ((x) & (~BITS_PORT_SEL_8822C))
+#define BIT_GET_PORT_SEL_8822C(x)                                              \
+	(((x) >> BIT_SHIFT_PORT_SEL_8822C) & BIT_MASK_PORT_SEL_8822C)
+#define BIT_SET_PORT_SEL_8822C(x, v)                                           \
+	(BIT_CLEAR_PORT_SEL_8822C(x) | BIT_PORT_SEL_8822C(v))
+
+/* 2 REG_P2PPS1_SPEC_STATE_8822C */
+#define BIT_P2P1_SPEC_POWER_STATE_8822C BIT(7)
+#define BIT_P2P1_SPEC_CTWINDOW_ON_8822C BIT(6)
+#define BIT_P2P1_SPEC_BCN_AREA_ON_8822C BIT(5)
+#define BIT_P2P1_SPEC_CTWIN_EARLY_DISTX_8822C BIT(4)
+#define BIT_P2P1_SPEC_NOA1_OFF_PERIOD_8822C BIT(3)
+#define BIT_P2P1_SPEC_FORCE_DOZE1_8822C BIT(2)
+#define BIT_P2P1_SPEC_NOA0_OFF_PERIOD_8822C BIT(1)
+#define BIT_P2P1_SPEC_FORCE_DOZE0_8822C BIT(0)
+
+/* 2 REG_P2PPS1_STATE_8822C */
+#define BIT_P2P1_POWER_STATE_8822C BIT(7)
+#define BIT_P2P1_CTWINDOW_ON_8822C BIT(6)
+#define BIT_P2P1_BEACON_AREA_ON_8822C BIT(5)
+#define BIT_P2P1_CTWIN_EARLY_DISTX_8822C BIT(4)
+#define BIT_P2P1_NOA1_OFF_PERIOD_8822C BIT(3)
+#define BIT_P2P1_FORCE_DOZE1_8822C BIT(2)
+#define BIT_P2P1_NOA0_OFF_PERIOD_8822C BIT(1)
+#define BIT_P2P1_FORCE_DOZE0_8822C BIT(0)
+
+/* 2 REG_P2PPS2_SPEC_STATE_8822C */
+#define BIT_P2P2_SPEC_POWER_STATE_8822C BIT(7)
+#define BIT_P2P2_SPEC_CTWINDOW_ON_8822C BIT(6)
+#define BIT_P2P2_SPEC_BCN_AREA_ON_8822C BIT(5)
+#define BIT_P2P2_SPEC_CTWIN_EARLY_DISTX_8822C BIT(4)
+#define BIT_P2P2_SPEC_NOA1_OFF_PERIOD_8822C BIT(3)
+#define BIT_P2P2_SPEC_FORCE_DOZE1_8822C BIT(2)
+#define BIT_P2P2_SPEC_NOA0_OFF_PERIOD_8822C BIT(1)
+#define BIT_P2P2_SPEC_FORCE_DOZE0_8822C BIT(0)
+
+/* 2 REG_P2PPS2_STATE_8822C */
+#define BIT_P2P2_POWER_STATE_8822C BIT(7)
+#define BIT_P2P2_CTWINDOW_ON_8822C BIT(6)
+#define BIT_P2P2_BEACON_AREA_ON_8822C BIT(5)
+#define BIT_P2P2_CTWIN_EARLY_DISTX_8822C BIT(4)
+#define BIT_P2P2_NOA1_OFF_PERIOD_8822C BIT(3)
+#define BIT_P2P2_FORCE_DOZE1_8822C BIT(2)
+#define BIT_P2P2_NOA0_OFF_PERIOD_8822C BIT(1)
+#define BIT_P2P2_FORCE_DOZE0_8822C BIT(0)
+
+/* 2 REG_PS_TIMER0_8822C */
+
+#define BIT_SHIFT_PSTIMER0_INT_8822C 5
+#define BIT_MASK_PSTIMER0_INT_8822C 0x7ffffff
+#define BIT_PSTIMER0_INT_8822C(x)                                              \
+	(((x) & BIT_MASK_PSTIMER0_INT_8822C) << BIT_SHIFT_PSTIMER0_INT_8822C)
+#define BITS_PSTIMER0_INT_8822C                                                \
+	(BIT_MASK_PSTIMER0_INT_8822C << BIT_SHIFT_PSTIMER0_INT_8822C)
+#define BIT_CLEAR_PSTIMER0_INT_8822C(x) ((x) & (~BITS_PSTIMER0_INT_8822C))
+#define BIT_GET_PSTIMER0_INT_8822C(x)                                          \
+	(((x) >> BIT_SHIFT_PSTIMER0_INT_8822C) & BIT_MASK_PSTIMER0_INT_8822C)
+#define BIT_SET_PSTIMER0_INT_8822C(x, v)                                       \
+	(BIT_CLEAR_PSTIMER0_INT_8822C(x) | BIT_PSTIMER0_INT_8822C(v))
+
+/* 2 REG_PS_TIMER1_8822C */
+
+#define BIT_SHIFT_PSTIMER1_INT_8822C 5
+#define BIT_MASK_PSTIMER1_INT_8822C 0x7ffffff
+#define BIT_PSTIMER1_INT_8822C(x)                                              \
+	(((x) & BIT_MASK_PSTIMER1_INT_8822C) << BIT_SHIFT_PSTIMER1_INT_8822C)
+#define BITS_PSTIMER1_INT_8822C                                                \
+	(BIT_MASK_PSTIMER1_INT_8822C << BIT_SHIFT_PSTIMER1_INT_8822C)
+#define BIT_CLEAR_PSTIMER1_INT_8822C(x) ((x) & (~BITS_PSTIMER1_INT_8822C))
+#define BIT_GET_PSTIMER1_INT_8822C(x)                                          \
+	(((x) >> BIT_SHIFT_PSTIMER1_INT_8822C) & BIT_MASK_PSTIMER1_INT_8822C)
+#define BIT_SET_PSTIMER1_INT_8822C(x, v)                                       \
+	(BIT_CLEAR_PSTIMER1_INT_8822C(x) | BIT_PSTIMER1_INT_8822C(v))
+
+/* 2 REG_PS_TIMER2_8822C */
+
+#define BIT_SHIFT_PSTIMER2_INT_8822C 5
+#define BIT_MASK_PSTIMER2_INT_8822C 0x7ffffff
+#define BIT_PSTIMER2_INT_8822C(x)                                              \
+	(((x) & BIT_MASK_PSTIMER2_INT_8822C) << BIT_SHIFT_PSTIMER2_INT_8822C)
+#define BITS_PSTIMER2_INT_8822C                                                \
+	(BIT_MASK_PSTIMER2_INT_8822C << BIT_SHIFT_PSTIMER2_INT_8822C)
+#define BIT_CLEAR_PSTIMER2_INT_8822C(x) ((x) & (~BITS_PSTIMER2_INT_8822C))
+#define BIT_GET_PSTIMER2_INT_8822C(x)                                          \
+	(((x) >> BIT_SHIFT_PSTIMER2_INT_8822C) & BIT_MASK_PSTIMER2_INT_8822C)
+#define BIT_SET_PSTIMER2_INT_8822C(x, v)                                       \
+	(BIT_CLEAR_PSTIMER2_INT_8822C(x) | BIT_PSTIMER2_INT_8822C(v))
+
+/* 2 REG_TBTT_CTN_AREA_8822C */
+
+#define BIT_SHIFT_TBTT_CTN_AREA_8822C 0
+#define BIT_MASK_TBTT_CTN_AREA_8822C 0xff
+#define BIT_TBTT_CTN_AREA_8822C(x)                                             \
+	(((x) & BIT_MASK_TBTT_CTN_AREA_8822C) << BIT_SHIFT_TBTT_CTN_AREA_8822C)
+#define BITS_TBTT_CTN_AREA_8822C                                               \
+	(BIT_MASK_TBTT_CTN_AREA_8822C << BIT_SHIFT_TBTT_CTN_AREA_8822C)
+#define BIT_CLEAR_TBTT_CTN_AREA_8822C(x) ((x) & (~BITS_TBTT_CTN_AREA_8822C))
+#define BIT_GET_TBTT_CTN_AREA_8822C(x)                                         \
+	(((x) >> BIT_SHIFT_TBTT_CTN_AREA_8822C) & BIT_MASK_TBTT_CTN_AREA_8822C)
+#define BIT_SET_TBTT_CTN_AREA_8822C(x, v)                                      \
+	(BIT_CLEAR_TBTT_CTN_AREA_8822C(x) | BIT_TBTT_CTN_AREA_8822C(v))
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_FORCE_BCN_IFS_8822C */
+
+#define BIT_SHIFT_FORCE_BCN_IFS_8822C 0
+#define BIT_MASK_FORCE_BCN_IFS_8822C 0xff
+#define BIT_FORCE_BCN_IFS_8822C(x)                                             \
+	(((x) & BIT_MASK_FORCE_BCN_IFS_8822C) << BIT_SHIFT_FORCE_BCN_IFS_8822C)
+#define BITS_FORCE_BCN_IFS_8822C                                               \
+	(BIT_MASK_FORCE_BCN_IFS_8822C << BIT_SHIFT_FORCE_BCN_IFS_8822C)
+#define BIT_CLEAR_FORCE_BCN_IFS_8822C(x) ((x) & (~BITS_FORCE_BCN_IFS_8822C))
+#define BIT_GET_FORCE_BCN_IFS_8822C(x)                                         \
+	(((x) >> BIT_SHIFT_FORCE_BCN_IFS_8822C) & BIT_MASK_FORCE_BCN_IFS_8822C)
+#define BIT_SET_FORCE_BCN_IFS_8822C(x, v)                                      \
+	(BIT_CLEAR_FORCE_BCN_IFS_8822C(x) | BIT_FORCE_BCN_IFS_8822C(v))
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_TXOP_MIN_8822C */
+#define BIT_HIQ_NAV_BREAK_EN_8822C BIT(15)
+#define BIT_MGQ_NAV_BREAK_EN_8822C BIT(14)
+
+#define BIT_SHIFT_TXOP_MIN_8822C 0
+#define BIT_MASK_TXOP_MIN_8822C 0x3fff
+#define BIT_TXOP_MIN_8822C(x)                                                  \
+	(((x) & BIT_MASK_TXOP_MIN_8822C) << BIT_SHIFT_TXOP_MIN_8822C)
+#define BITS_TXOP_MIN_8822C                                                    \
+	(BIT_MASK_TXOP_MIN_8822C << BIT_SHIFT_TXOP_MIN_8822C)
+#define BIT_CLEAR_TXOP_MIN_8822C(x) ((x) & (~BITS_TXOP_MIN_8822C))
+#define BIT_GET_TXOP_MIN_8822C(x)                                              \
+	(((x) >> BIT_SHIFT_TXOP_MIN_8822C) & BIT_MASK_TXOP_MIN_8822C)
+#define BIT_SET_TXOP_MIN_8822C(x, v)                                           \
+	(BIT_CLEAR_TXOP_MIN_8822C(x) | BIT_TXOP_MIN_8822C(v))
+
+/* 2 REG_PRE_BKF_TIME_8822C */
+
+#define BIT_SHIFT_PRE_BKF_TIME_8822C 0
+#define BIT_MASK_PRE_BKF_TIME_8822C 0xff
+#define BIT_PRE_BKF_TIME_8822C(x)                                              \
+	(((x) & BIT_MASK_PRE_BKF_TIME_8822C) << BIT_SHIFT_PRE_BKF_TIME_8822C)
+#define BITS_PRE_BKF_TIME_8822C                                                \
+	(BIT_MASK_PRE_BKF_TIME_8822C << BIT_SHIFT_PRE_BKF_TIME_8822C)
+#define BIT_CLEAR_PRE_BKF_TIME_8822C(x) ((x) & (~BITS_PRE_BKF_TIME_8822C))
+#define BIT_GET_PRE_BKF_TIME_8822C(x)                                          \
+	(((x) >> BIT_SHIFT_PRE_BKF_TIME_8822C) & BIT_MASK_PRE_BKF_TIME_8822C)
+#define BIT_SET_PRE_BKF_TIME_8822C(x, v)                                       \
+	(BIT_CLEAR_PRE_BKF_TIME_8822C(x) | BIT_PRE_BKF_TIME_8822C(v))
+
+/* 2 REG_CROSS_TXOP_CTRL_8822C */
+#define BIT_TXFAIL_BREACK_TXOP_EN_8822C BIT(3)
+#define BIT_DTIM_BYPASS_8822C BIT(2)
+#define BIT_RTS_NAV_TXOP_8822C BIT(1)
+#define BIT_NOT_CROSS_TXOP_8822C BIT(0)
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_RX_TBTT_SHIFT_V1_8822C */
+#define BIT_RX_TBTT_SHIFT_RW_FLAG_V1_8822C BIT(31)
+
+#define BIT_SHIFT_RX_TBTT_SHIFT_OFFSET_V1_8822C 16
+#define BIT_MASK_RX_TBTT_SHIFT_OFFSET_V1_8822C 0xfff
+#define BIT_RX_TBTT_SHIFT_OFFSET_V1_8822C(x)                                   \
+	(((x) & BIT_MASK_RX_TBTT_SHIFT_OFFSET_V1_8822C)                        \
+	 << BIT_SHIFT_RX_TBTT_SHIFT_OFFSET_V1_8822C)
+#define BITS_RX_TBTT_SHIFT_OFFSET_V1_8822C                                     \
+	(BIT_MASK_RX_TBTT_SHIFT_OFFSET_V1_8822C                                \
+	 << BIT_SHIFT_RX_TBTT_SHIFT_OFFSET_V1_8822C)
+#define BIT_CLEAR_RX_TBTT_SHIFT_OFFSET_V1_8822C(x)                             \
+	((x) & (~BITS_RX_TBTT_SHIFT_OFFSET_V1_8822C))
+#define BIT_GET_RX_TBTT_SHIFT_OFFSET_V1_8822C(x)                               \
+	(((x) >> BIT_SHIFT_RX_TBTT_SHIFT_OFFSET_V1_8822C) &                    \
+	 BIT_MASK_RX_TBTT_SHIFT_OFFSET_V1_8822C)
+#define BIT_SET_RX_TBTT_SHIFT_OFFSET_V1_8822C(x, v)                            \
+	(BIT_CLEAR_RX_TBTT_SHIFT_OFFSET_V1_8822C(x) |                          \
+	 BIT_RX_TBTT_SHIFT_OFFSET_V1_8822C(v))
+
+#define BIT_SHIFT_RX_TBTT_SHIFT_SEL_V1_8822C 8
+#define BIT_MASK_RX_TBTT_SHIFT_SEL_V1_8822C 0x7
+#define BIT_RX_TBTT_SHIFT_SEL_V1_8822C(x)                                      \
+	(((x) & BIT_MASK_RX_TBTT_SHIFT_SEL_V1_8822C)                           \
+	 << BIT_SHIFT_RX_TBTT_SHIFT_SEL_V1_8822C)
+#define BITS_RX_TBTT_SHIFT_SEL_V1_8822C                                        \
+	(BIT_MASK_RX_TBTT_SHIFT_SEL_V1_8822C                                   \
+	 << BIT_SHIFT_RX_TBTT_SHIFT_SEL_V1_8822C)
+#define BIT_CLEAR_RX_TBTT_SHIFT_SEL_V1_8822C(x)                                \
+	((x) & (~BITS_RX_TBTT_SHIFT_SEL_V1_8822C))
+#define BIT_GET_RX_TBTT_SHIFT_SEL_V1_8822C(x)                                  \
+	(((x) >> BIT_SHIFT_RX_TBTT_SHIFT_SEL_V1_8822C) &                       \
+	 BIT_MASK_RX_TBTT_SHIFT_SEL_V1_8822C)
+#define BIT_SET_RX_TBTT_SHIFT_SEL_V1_8822C(x, v)                               \
+	(BIT_CLEAR_RX_TBTT_SHIFT_SEL_V1_8822C(x) |                             \
+	 BIT_RX_TBTT_SHIFT_SEL_V1_8822C(v))
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_ATIMWND2_8822C */
+
+#define BIT_SHIFT_ATIMWND2_8822C 0
+#define BIT_MASK_ATIMWND2_8822C 0xff
+#define BIT_ATIMWND2_8822C(x)                                                  \
+	(((x) & BIT_MASK_ATIMWND2_8822C) << BIT_SHIFT_ATIMWND2_8822C)
+#define BITS_ATIMWND2_8822C                                                    \
+	(BIT_MASK_ATIMWND2_8822C << BIT_SHIFT_ATIMWND2_8822C)
+#define BIT_CLEAR_ATIMWND2_8822C(x) ((x) & (~BITS_ATIMWND2_8822C))
+#define BIT_GET_ATIMWND2_8822C(x)                                              \
+	(((x) >> BIT_SHIFT_ATIMWND2_8822C) & BIT_MASK_ATIMWND2_8822C)
+#define BIT_SET_ATIMWND2_8822C(x, v)                                           \
+	(BIT_CLEAR_ATIMWND2_8822C(x) | BIT_ATIMWND2_8822C(v))
+
+/* 2 REG_ATIMWND3_8822C */
+
+#define BIT_SHIFT_ATIMWND3_8822C 0
+#define BIT_MASK_ATIMWND3_8822C 0xff
+#define BIT_ATIMWND3_8822C(x)                                                  \
+	(((x) & BIT_MASK_ATIMWND3_8822C) << BIT_SHIFT_ATIMWND3_8822C)
+#define BITS_ATIMWND3_8822C                                                    \
+	(BIT_MASK_ATIMWND3_8822C << BIT_SHIFT_ATIMWND3_8822C)
+#define BIT_CLEAR_ATIMWND3_8822C(x) ((x) & (~BITS_ATIMWND3_8822C))
+#define BIT_GET_ATIMWND3_8822C(x)                                              \
+	(((x) >> BIT_SHIFT_ATIMWND3_8822C) & BIT_MASK_ATIMWND3_8822C)
+#define BIT_SET_ATIMWND3_8822C(x, v)                                           \
+	(BIT_CLEAR_ATIMWND3_8822C(x) | BIT_ATIMWND3_8822C(v))
+
+/* 2 REG_ATIMWND4_8822C */
+
+#define BIT_SHIFT_ATIMWND4_8822C 0
+#define BIT_MASK_ATIMWND4_8822C 0xff
+#define BIT_ATIMWND4_8822C(x)                                                  \
+	(((x) & BIT_MASK_ATIMWND4_8822C) << BIT_SHIFT_ATIMWND4_8822C)
+#define BITS_ATIMWND4_8822C                                                    \
+	(BIT_MASK_ATIMWND4_8822C << BIT_SHIFT_ATIMWND4_8822C)
+#define BIT_CLEAR_ATIMWND4_8822C(x) ((x) & (~BITS_ATIMWND4_8822C))
+#define BIT_GET_ATIMWND4_8822C(x)                                              \
+	(((x) >> BIT_SHIFT_ATIMWND4_8822C) & BIT_MASK_ATIMWND4_8822C)
+#define BIT_SET_ATIMWND4_8822C(x, v)                                           \
+	(BIT_CLEAR_ATIMWND4_8822C(x) | BIT_ATIMWND4_8822C(v))
+
+/* 2 REG_ATIMWND5_8822C */
+
+#define BIT_SHIFT_ATIMWND5_8822C 0
+#define BIT_MASK_ATIMWND5_8822C 0xff
+#define BIT_ATIMWND5_8822C(x)                                                  \
+	(((x) & BIT_MASK_ATIMWND5_8822C) << BIT_SHIFT_ATIMWND5_8822C)
+#define BITS_ATIMWND5_8822C                                                    \
+	(BIT_MASK_ATIMWND5_8822C << BIT_SHIFT_ATIMWND5_8822C)
+#define BIT_CLEAR_ATIMWND5_8822C(x) ((x) & (~BITS_ATIMWND5_8822C))
+#define BIT_GET_ATIMWND5_8822C(x)                                              \
+	(((x) >> BIT_SHIFT_ATIMWND5_8822C) & BIT_MASK_ATIMWND5_8822C)
+#define BIT_SET_ATIMWND5_8822C(x, v)                                           \
+	(BIT_CLEAR_ATIMWND5_8822C(x) | BIT_ATIMWND5_8822C(v))
+
+/* 2 REG_ATIMWND6_8822C */
+
+#define BIT_SHIFT_ATIMWND6_8822C 0
+#define BIT_MASK_ATIMWND6_8822C 0xff
+#define BIT_ATIMWND6_8822C(x)                                                  \
+	(((x) & BIT_MASK_ATIMWND6_8822C) << BIT_SHIFT_ATIMWND6_8822C)
+#define BITS_ATIMWND6_8822C                                                    \
+	(BIT_MASK_ATIMWND6_8822C << BIT_SHIFT_ATIMWND6_8822C)
+#define BIT_CLEAR_ATIMWND6_8822C(x) ((x) & (~BITS_ATIMWND6_8822C))
+#define BIT_GET_ATIMWND6_8822C(x)                                              \
+	(((x) >> BIT_SHIFT_ATIMWND6_8822C) & BIT_MASK_ATIMWND6_8822C)
+#define BIT_SET_ATIMWND6_8822C(x, v)                                           \
+	(BIT_CLEAR_ATIMWND6_8822C(x) | BIT_ATIMWND6_8822C(v))
+
+/* 2 REG_ATIMWND7_8822C */
+
+#define BIT_SHIFT_ATIMWND7_8822C 0
+#define BIT_MASK_ATIMWND7_8822C 0xff
+#define BIT_ATIMWND7_8822C(x)                                                  \
+	(((x) & BIT_MASK_ATIMWND7_8822C) << BIT_SHIFT_ATIMWND7_8822C)
+#define BITS_ATIMWND7_8822C                                                    \
+	(BIT_MASK_ATIMWND7_8822C << BIT_SHIFT_ATIMWND7_8822C)
+#define BIT_CLEAR_ATIMWND7_8822C(x) ((x) & (~BITS_ATIMWND7_8822C))
+#define BIT_GET_ATIMWND7_8822C(x)                                              \
+	(((x) >> BIT_SHIFT_ATIMWND7_8822C) & BIT_MASK_ATIMWND7_8822C)
+#define BIT_SET_ATIMWND7_8822C(x, v)                                           \
+	(BIT_CLEAR_ATIMWND7_8822C(x) | BIT_ATIMWND7_8822C(v))
+
+/* 2 REG_ATIMUGT_8822C */
+
+#define BIT_SHIFT_ATIM_URGENT_8822C 0
+#define BIT_MASK_ATIM_URGENT_8822C 0xff
+#define BIT_ATIM_URGENT_8822C(x)                                               \
+	(((x) & BIT_MASK_ATIM_URGENT_8822C) << BIT_SHIFT_ATIM_URGENT_8822C)
+#define BITS_ATIM_URGENT_8822C                                                 \
+	(BIT_MASK_ATIM_URGENT_8822C << BIT_SHIFT_ATIM_URGENT_8822C)
+#define BIT_CLEAR_ATIM_URGENT_8822C(x) ((x) & (~BITS_ATIM_URGENT_8822C))
+#define BIT_GET_ATIM_URGENT_8822C(x)                                           \
+	(((x) >> BIT_SHIFT_ATIM_URGENT_8822C) & BIT_MASK_ATIM_URGENT_8822C)
+#define BIT_SET_ATIM_URGENT_8822C(x, v)                                        \
+	(BIT_CLEAR_ATIM_URGENT_8822C(x) | BIT_ATIM_URGENT_8822C(v))
+
+/* 2 REG_HIQ_NO_LMT_EN_8822C */
+#define BIT_HIQ_NO_LMT_EN_VAP7_8822C BIT(7)
+#define BIT_HIQ_NO_LMT_EN_VAP6_8822C BIT(6)
+#define BIT_HIQ_NO_LMT_EN_VAP5_8822C BIT(5)
+#define BIT_HIQ_NO_LMT_EN_VAP4_8822C BIT(4)
+#define BIT_HIQ_NO_LMT_EN_VAP3_8822C BIT(3)
+#define BIT_HIQ_NO_LMT_EN_VAP2_8822C BIT(2)
+#define BIT_HIQ_NO_LMT_EN_VAP1_8822C BIT(1)
+#define BIT_HIQ_NO_LMT_EN_ROOT_8822C BIT(0)
+
+/* 2 REG_DTIM_COUNTER_ROOT_8822C */
+
+#define BIT_SHIFT_DTIM_COUNT_ROOT_8822C 0
+#define BIT_MASK_DTIM_COUNT_ROOT_8822C 0xff
+#define BIT_DTIM_COUNT_ROOT_8822C(x)                                           \
+	(((x) & BIT_MASK_DTIM_COUNT_ROOT_8822C)                                \
+	 << BIT_SHIFT_DTIM_COUNT_ROOT_8822C)
+#define BITS_DTIM_COUNT_ROOT_8822C                                             \
+	(BIT_MASK_DTIM_COUNT_ROOT_8822C << BIT_SHIFT_DTIM_COUNT_ROOT_8822C)
+#define BIT_CLEAR_DTIM_COUNT_ROOT_8822C(x) ((x) & (~BITS_DTIM_COUNT_ROOT_8822C))
+#define BIT_GET_DTIM_COUNT_ROOT_8822C(x)                                       \
+	(((x) >> BIT_SHIFT_DTIM_COUNT_ROOT_8822C) &                            \
+	 BIT_MASK_DTIM_COUNT_ROOT_8822C)
+#define BIT_SET_DTIM_COUNT_ROOT_8822C(x, v)                                    \
+	(BIT_CLEAR_DTIM_COUNT_ROOT_8822C(x) | BIT_DTIM_COUNT_ROOT_8822C(v))
+
+/* 2 REG_DTIM_COUNTER_VAP1_8822C */
+
+#define BIT_SHIFT_DTIM_COUNT_VAP1_8822C 0
+#define BIT_MASK_DTIM_COUNT_VAP1_8822C 0xff
+#define BIT_DTIM_COUNT_VAP1_8822C(x)                                           \
+	(((x) & BIT_MASK_DTIM_COUNT_VAP1_8822C)                                \
+	 << BIT_SHIFT_DTIM_COUNT_VAP1_8822C)
+#define BITS_DTIM_COUNT_VAP1_8822C                                             \
+	(BIT_MASK_DTIM_COUNT_VAP1_8822C << BIT_SHIFT_DTIM_COUNT_VAP1_8822C)
+#define BIT_CLEAR_DTIM_COUNT_VAP1_8822C(x) ((x) & (~BITS_DTIM_COUNT_VAP1_8822C))
+#define BIT_GET_DTIM_COUNT_VAP1_8822C(x)                                       \
+	(((x) >> BIT_SHIFT_DTIM_COUNT_VAP1_8822C) &                            \
+	 BIT_MASK_DTIM_COUNT_VAP1_8822C)
+#define BIT_SET_DTIM_COUNT_VAP1_8822C(x, v)                                    \
+	(BIT_CLEAR_DTIM_COUNT_VAP1_8822C(x) | BIT_DTIM_COUNT_VAP1_8822C(v))
+
+/* 2 REG_DTIM_COUNTER_VAP2_8822C */
+
+#define BIT_SHIFT_DTIM_COUNT_VAP2_8822C 0
+#define BIT_MASK_DTIM_COUNT_VAP2_8822C 0xff
+#define BIT_DTIM_COUNT_VAP2_8822C(x)                                           \
+	(((x) & BIT_MASK_DTIM_COUNT_VAP2_8822C)                                \
+	 << BIT_SHIFT_DTIM_COUNT_VAP2_8822C)
+#define BITS_DTIM_COUNT_VAP2_8822C                                             \
+	(BIT_MASK_DTIM_COUNT_VAP2_8822C << BIT_SHIFT_DTIM_COUNT_VAP2_8822C)
+#define BIT_CLEAR_DTIM_COUNT_VAP2_8822C(x) ((x) & (~BITS_DTIM_COUNT_VAP2_8822C))
+#define BIT_GET_DTIM_COUNT_VAP2_8822C(x)                                       \
+	(((x) >> BIT_SHIFT_DTIM_COUNT_VAP2_8822C) &                            \
+	 BIT_MASK_DTIM_COUNT_VAP2_8822C)
+#define BIT_SET_DTIM_COUNT_VAP2_8822C(x, v)                                    \
+	(BIT_CLEAR_DTIM_COUNT_VAP2_8822C(x) | BIT_DTIM_COUNT_VAP2_8822C(v))
+
+/* 2 REG_DTIM_COUNTER_VAP3_8822C */
+
+#define BIT_SHIFT_DTIM_COUNT_VAP3_8822C 0
+#define BIT_MASK_DTIM_COUNT_VAP3_8822C 0xff
+#define BIT_DTIM_COUNT_VAP3_8822C(x)                                           \
+	(((x) & BIT_MASK_DTIM_COUNT_VAP3_8822C)                                \
+	 << BIT_SHIFT_DTIM_COUNT_VAP3_8822C)
+#define BITS_DTIM_COUNT_VAP3_8822C                                             \
+	(BIT_MASK_DTIM_COUNT_VAP3_8822C << BIT_SHIFT_DTIM_COUNT_VAP3_8822C)
+#define BIT_CLEAR_DTIM_COUNT_VAP3_8822C(x) ((x) & (~BITS_DTIM_COUNT_VAP3_8822C))
+#define BIT_GET_DTIM_COUNT_VAP3_8822C(x)                                       \
+	(((x) >> BIT_SHIFT_DTIM_COUNT_VAP3_8822C) &                            \
+	 BIT_MASK_DTIM_COUNT_VAP3_8822C)
+#define BIT_SET_DTIM_COUNT_VAP3_8822C(x, v)                                    \
+	(BIT_CLEAR_DTIM_COUNT_VAP3_8822C(x) | BIT_DTIM_COUNT_VAP3_8822C(v))
+
+/* 2 REG_DTIM_COUNTER_VAP4_8822C */
+
+#define BIT_SHIFT_DTIM_COUNT_VAP4_8822C 0
+#define BIT_MASK_DTIM_COUNT_VAP4_8822C 0xff
+#define BIT_DTIM_COUNT_VAP4_8822C(x)                                           \
+	(((x) & BIT_MASK_DTIM_COUNT_VAP4_8822C)                                \
+	 << BIT_SHIFT_DTIM_COUNT_VAP4_8822C)
+#define BITS_DTIM_COUNT_VAP4_8822C                                             \
+	(BIT_MASK_DTIM_COUNT_VAP4_8822C << BIT_SHIFT_DTIM_COUNT_VAP4_8822C)
+#define BIT_CLEAR_DTIM_COUNT_VAP4_8822C(x) ((x) & (~BITS_DTIM_COUNT_VAP4_8822C))
+#define BIT_GET_DTIM_COUNT_VAP4_8822C(x)                                       \
+	(((x) >> BIT_SHIFT_DTIM_COUNT_VAP4_8822C) &                            \
+	 BIT_MASK_DTIM_COUNT_VAP4_8822C)
+#define BIT_SET_DTIM_COUNT_VAP4_8822C(x, v)                                    \
+	(BIT_CLEAR_DTIM_COUNT_VAP4_8822C(x) | BIT_DTIM_COUNT_VAP4_8822C(v))
+
+/* 2 REG_DTIM_COUNTER_VAP5_8822C */
+
+#define BIT_SHIFT_DTIM_COUNT_VAP5_8822C 0
+#define BIT_MASK_DTIM_COUNT_VAP5_8822C 0xff
+#define BIT_DTIM_COUNT_VAP5_8822C(x)                                           \
+	(((x) & BIT_MASK_DTIM_COUNT_VAP5_8822C)                                \
+	 << BIT_SHIFT_DTIM_COUNT_VAP5_8822C)
+#define BITS_DTIM_COUNT_VAP5_8822C                                             \
+	(BIT_MASK_DTIM_COUNT_VAP5_8822C << BIT_SHIFT_DTIM_COUNT_VAP5_8822C)
+#define BIT_CLEAR_DTIM_COUNT_VAP5_8822C(x) ((x) & (~BITS_DTIM_COUNT_VAP5_8822C))
+#define BIT_GET_DTIM_COUNT_VAP5_8822C(x)                                       \
+	(((x) >> BIT_SHIFT_DTIM_COUNT_VAP5_8822C) &                            \
+	 BIT_MASK_DTIM_COUNT_VAP5_8822C)
+#define BIT_SET_DTIM_COUNT_VAP5_8822C(x, v)                                    \
+	(BIT_CLEAR_DTIM_COUNT_VAP5_8822C(x) | BIT_DTIM_COUNT_VAP5_8822C(v))
+
+/* 2 REG_DTIM_COUNTER_VAP6_8822C */
+
+#define BIT_SHIFT_DTIM_COUNT_VAP6_8822C 0
+#define BIT_MASK_DTIM_COUNT_VAP6_8822C 0xff
+#define BIT_DTIM_COUNT_VAP6_8822C(x)                                           \
+	(((x) & BIT_MASK_DTIM_COUNT_VAP6_8822C)                                \
+	 << BIT_SHIFT_DTIM_COUNT_VAP6_8822C)
+#define BITS_DTIM_COUNT_VAP6_8822C                                             \
+	(BIT_MASK_DTIM_COUNT_VAP6_8822C << BIT_SHIFT_DTIM_COUNT_VAP6_8822C)
+#define BIT_CLEAR_DTIM_COUNT_VAP6_8822C(x) ((x) & (~BITS_DTIM_COUNT_VAP6_8822C))
+#define BIT_GET_DTIM_COUNT_VAP6_8822C(x)                                       \
+	(((x) >> BIT_SHIFT_DTIM_COUNT_VAP6_8822C) &                            \
+	 BIT_MASK_DTIM_COUNT_VAP6_8822C)
+#define BIT_SET_DTIM_COUNT_VAP6_8822C(x, v)                                    \
+	(BIT_CLEAR_DTIM_COUNT_VAP6_8822C(x) | BIT_DTIM_COUNT_VAP6_8822C(v))
+
+/* 2 REG_DTIM_COUNTER_VAP7_8822C */
+
+#define BIT_SHIFT_DTIM_COUNT_VAP7_8822C 0
+#define BIT_MASK_DTIM_COUNT_VAP7_8822C 0xff
+#define BIT_DTIM_COUNT_VAP7_8822C(x)                                           \
+	(((x) & BIT_MASK_DTIM_COUNT_VAP7_8822C)                                \
+	 << BIT_SHIFT_DTIM_COUNT_VAP7_8822C)
+#define BITS_DTIM_COUNT_VAP7_8822C                                             \
+	(BIT_MASK_DTIM_COUNT_VAP7_8822C << BIT_SHIFT_DTIM_COUNT_VAP7_8822C)
+#define BIT_CLEAR_DTIM_COUNT_VAP7_8822C(x) ((x) & (~BITS_DTIM_COUNT_VAP7_8822C))
+#define BIT_GET_DTIM_COUNT_VAP7_8822C(x)                                       \
+	(((x) >> BIT_SHIFT_DTIM_COUNT_VAP7_8822C) &                            \
+	 BIT_MASK_DTIM_COUNT_VAP7_8822C)
+#define BIT_SET_DTIM_COUNT_VAP7_8822C(x, v)                                    \
+	(BIT_CLEAR_DTIM_COUNT_VAP7_8822C(x) | BIT_DTIM_COUNT_VAP7_8822C(v))
+
+/* 2 REG_DIS_ATIM_8822C */
+#define BIT_DIS_ATIM_VAP7_8822C BIT(7)
+#define BIT_DIS_ATIM_VAP6_8822C BIT(6)
+#define BIT_DIS_ATIM_VAP5_8822C BIT(5)
+#define BIT_DIS_ATIM_VAP4_8822C BIT(4)
+#define BIT_DIS_ATIM_VAP3_8822C BIT(3)
+#define BIT_DIS_ATIM_VAP2_8822C BIT(2)
+#define BIT_DIS_ATIM_VAP1_8822C BIT(1)
+#define BIT_DIS_ATIM_ROOT_8822C BIT(0)
+
+/* 2 REG_EARLY_128US_8822C */
+
+#define BIT_SHIFT_TSFT_SEL_TIMER1_8822C 3
+#define BIT_MASK_TSFT_SEL_TIMER1_8822C 0x7
+#define BIT_TSFT_SEL_TIMER1_8822C(x)                                           \
+	(((x) & BIT_MASK_TSFT_SEL_TIMER1_8822C)                                \
+	 << BIT_SHIFT_TSFT_SEL_TIMER1_8822C)
+#define BITS_TSFT_SEL_TIMER1_8822C                                             \
+	(BIT_MASK_TSFT_SEL_TIMER1_8822C << BIT_SHIFT_TSFT_SEL_TIMER1_8822C)
+#define BIT_CLEAR_TSFT_SEL_TIMER1_8822C(x) ((x) & (~BITS_TSFT_SEL_TIMER1_8822C))
+#define BIT_GET_TSFT_SEL_TIMER1_8822C(x)                                       \
+	(((x) >> BIT_SHIFT_TSFT_SEL_TIMER1_8822C) &                            \
+	 BIT_MASK_TSFT_SEL_TIMER1_8822C)
+#define BIT_SET_TSFT_SEL_TIMER1_8822C(x, v)                                    \
+	(BIT_CLEAR_TSFT_SEL_TIMER1_8822C(x) | BIT_TSFT_SEL_TIMER1_8822C(v))
+
+#define BIT_SHIFT_EARLY_128US_8822C 0
+#define BIT_MASK_EARLY_128US_8822C 0x7
+#define BIT_EARLY_128US_8822C(x)                                               \
+	(((x) & BIT_MASK_EARLY_128US_8822C) << BIT_SHIFT_EARLY_128US_8822C)
+#define BITS_EARLY_128US_8822C                                                 \
+	(BIT_MASK_EARLY_128US_8822C << BIT_SHIFT_EARLY_128US_8822C)
+#define BIT_CLEAR_EARLY_128US_8822C(x) ((x) & (~BITS_EARLY_128US_8822C))
+#define BIT_GET_EARLY_128US_8822C(x)                                           \
+	(((x) >> BIT_SHIFT_EARLY_128US_8822C) & BIT_MASK_EARLY_128US_8822C)
+#define BIT_SET_EARLY_128US_8822C(x, v)                                        \
+	(BIT_CLEAR_EARLY_128US_8822C(x) | BIT_EARLY_128US_8822C(v))
+
+/* 2 REG_P2PPS1_CTRL_8822C */
+#define BIT_P2P1_CTW_ALLSTASLEEP_8822C BIT(7)
+#define BIT_P2P1_OFF_DISTX_EN_8822C BIT(6)
+#define BIT_P2P1_PWR_MGT_EN_8822C BIT(5)
+#define BIT_P2P1_NOA1_EN_8822C BIT(2)
+#define BIT_P2P1_NOA0_EN_8822C BIT(1)
+
+/* 2 REG_P2PPS2_CTRL_8822C */
+#define BIT_P2P2_CTW_ALLSTASLEEP_8822C BIT(7)
+#define BIT_P2P2_OFF_DISTX_EN_8822C BIT(6)
+#define BIT_P2P2_PWR_MGT_EN_8822C BIT(5)
+#define BIT_P2P2_NOA1_EN_8822C BIT(2)
+#define BIT_P2P2_NOA0_EN_8822C BIT(1)
+
+/* 2 REG_TIMER0_SRC_SEL_8822C */
+
+#define BIT_SHIFT_SYNC_CLI_SEL_8822C 4
+#define BIT_MASK_SYNC_CLI_SEL_8822C 0x7
+#define BIT_SYNC_CLI_SEL_8822C(x)                                              \
+	(((x) & BIT_MASK_SYNC_CLI_SEL_8822C) << BIT_SHIFT_SYNC_CLI_SEL_8822C)
+#define BITS_SYNC_CLI_SEL_8822C                                                \
+	(BIT_MASK_SYNC_CLI_SEL_8822C << BIT_SHIFT_SYNC_CLI_SEL_8822C)
+#define BIT_CLEAR_SYNC_CLI_SEL_8822C(x) ((x) & (~BITS_SYNC_CLI_SEL_8822C))
+#define BIT_GET_SYNC_CLI_SEL_8822C(x)                                          \
+	(((x) >> BIT_SHIFT_SYNC_CLI_SEL_8822C) & BIT_MASK_SYNC_CLI_SEL_8822C)
+#define BIT_SET_SYNC_CLI_SEL_8822C(x, v)                                       \
+	(BIT_CLEAR_SYNC_CLI_SEL_8822C(x) | BIT_SYNC_CLI_SEL_8822C(v))
+
+#define BIT_SHIFT_TSFT_SEL_TIMER0_8822C 0
+#define BIT_MASK_TSFT_SEL_TIMER0_8822C 0x7
+#define BIT_TSFT_SEL_TIMER0_8822C(x)                                           \
+	(((x) & BIT_MASK_TSFT_SEL_TIMER0_8822C)                                \
+	 << BIT_SHIFT_TSFT_SEL_TIMER0_8822C)
+#define BITS_TSFT_SEL_TIMER0_8822C                                             \
+	(BIT_MASK_TSFT_SEL_TIMER0_8822C << BIT_SHIFT_TSFT_SEL_TIMER0_8822C)
+#define BIT_CLEAR_TSFT_SEL_TIMER0_8822C(x) ((x) & (~BITS_TSFT_SEL_TIMER0_8822C))
+#define BIT_GET_TSFT_SEL_TIMER0_8822C(x)                                       \
+	(((x) >> BIT_SHIFT_TSFT_SEL_TIMER0_8822C) &                            \
+	 BIT_MASK_TSFT_SEL_TIMER0_8822C)
+#define BIT_SET_TSFT_SEL_TIMER0_8822C(x, v)                                    \
+	(BIT_CLEAR_TSFT_SEL_TIMER0_8822C(x) | BIT_TSFT_SEL_TIMER0_8822C(v))
+
+/* 2 REG_NOA_UNIT_SEL_8822C */
+
+#define BIT_SHIFT_NOA_UNIT2_SEL_8822C 8
+#define BIT_MASK_NOA_UNIT2_SEL_8822C 0x7
+#define BIT_NOA_UNIT2_SEL_8822C(x)                                             \
+	(((x) & BIT_MASK_NOA_UNIT2_SEL_8822C) << BIT_SHIFT_NOA_UNIT2_SEL_8822C)
+#define BITS_NOA_UNIT2_SEL_8822C                                               \
+	(BIT_MASK_NOA_UNIT2_SEL_8822C << BIT_SHIFT_NOA_UNIT2_SEL_8822C)
+#define BIT_CLEAR_NOA_UNIT2_SEL_8822C(x) ((x) & (~BITS_NOA_UNIT2_SEL_8822C))
+#define BIT_GET_NOA_UNIT2_SEL_8822C(x)                                         \
+	(((x) >> BIT_SHIFT_NOA_UNIT2_SEL_8822C) & BIT_MASK_NOA_UNIT2_SEL_8822C)
+#define BIT_SET_NOA_UNIT2_SEL_8822C(x, v)                                      \
+	(BIT_CLEAR_NOA_UNIT2_SEL_8822C(x) | BIT_NOA_UNIT2_SEL_8822C(v))
+
+#define BIT_SHIFT_NOA_UNIT1_SEL_8822C 4
+#define BIT_MASK_NOA_UNIT1_SEL_8822C 0x7
+#define BIT_NOA_UNIT1_SEL_8822C(x)                                             \
+	(((x) & BIT_MASK_NOA_UNIT1_SEL_8822C) << BIT_SHIFT_NOA_UNIT1_SEL_8822C)
+#define BITS_NOA_UNIT1_SEL_8822C                                               \
+	(BIT_MASK_NOA_UNIT1_SEL_8822C << BIT_SHIFT_NOA_UNIT1_SEL_8822C)
+#define BIT_CLEAR_NOA_UNIT1_SEL_8822C(x) ((x) & (~BITS_NOA_UNIT1_SEL_8822C))
+#define BIT_GET_NOA_UNIT1_SEL_8822C(x)                                         \
+	(((x) >> BIT_SHIFT_NOA_UNIT1_SEL_8822C) & BIT_MASK_NOA_UNIT1_SEL_8822C)
+#define BIT_SET_NOA_UNIT1_SEL_8822C(x, v)                                      \
+	(BIT_CLEAR_NOA_UNIT1_SEL_8822C(x) | BIT_NOA_UNIT1_SEL_8822C(v))
+
+#define BIT_SHIFT_NOA_UNIT0_SEL_8822C 0
+#define BIT_MASK_NOA_UNIT0_SEL_8822C 0x7
+#define BIT_NOA_UNIT0_SEL_8822C(x)                                             \
+	(((x) & BIT_MASK_NOA_UNIT0_SEL_8822C) << BIT_SHIFT_NOA_UNIT0_SEL_8822C)
+#define BITS_NOA_UNIT0_SEL_8822C                                               \
+	(BIT_MASK_NOA_UNIT0_SEL_8822C << BIT_SHIFT_NOA_UNIT0_SEL_8822C)
+#define BIT_CLEAR_NOA_UNIT0_SEL_8822C(x) ((x) & (~BITS_NOA_UNIT0_SEL_8822C))
+#define BIT_GET_NOA_UNIT0_SEL_8822C(x)                                         \
+	(((x) >> BIT_SHIFT_NOA_UNIT0_SEL_8822C) & BIT_MASK_NOA_UNIT0_SEL_8822C)
+#define BIT_SET_NOA_UNIT0_SEL_8822C(x, v)                                      \
+	(BIT_CLEAR_NOA_UNIT0_SEL_8822C(x) | BIT_NOA_UNIT0_SEL_8822C(v))
+
+/* 2 REG_P2POFF_DIS_TXTIME_8822C */
+
+#define BIT_SHIFT_P2POFF_DIS_TXTIME_8822C 0
+#define BIT_MASK_P2POFF_DIS_TXTIME_8822C 0xff
+#define BIT_P2POFF_DIS_TXTIME_8822C(x)                                         \
+	(((x) & BIT_MASK_P2POFF_DIS_TXTIME_8822C)                              \
+	 << BIT_SHIFT_P2POFF_DIS_TXTIME_8822C)
+#define BITS_P2POFF_DIS_TXTIME_8822C                                           \
+	(BIT_MASK_P2POFF_DIS_TXTIME_8822C << BIT_SHIFT_P2POFF_DIS_TXTIME_8822C)
+#define BIT_CLEAR_P2POFF_DIS_TXTIME_8822C(x)                                   \
+	((x) & (~BITS_P2POFF_DIS_TXTIME_8822C))
+#define BIT_GET_P2POFF_DIS_TXTIME_8822C(x)                                     \
+	(((x) >> BIT_SHIFT_P2POFF_DIS_TXTIME_8822C) &                          \
+	 BIT_MASK_P2POFF_DIS_TXTIME_8822C)
+#define BIT_SET_P2POFF_DIS_TXTIME_8822C(x, v)                                  \
+	(BIT_CLEAR_P2POFF_DIS_TXTIME_8822C(x) | BIT_P2POFF_DIS_TXTIME_8822C(v))
+
+/* 2 REG_MBSSID_BCN_SPACE2_8822C */
+
+#define BIT_SHIFT_BCN_SPACE_CLINT2_8822C 16
+#define BIT_MASK_BCN_SPACE_CLINT2_8822C 0xfff
+#define BIT_BCN_SPACE_CLINT2_8822C(x)                                          \
+	(((x) & BIT_MASK_BCN_SPACE_CLINT2_8822C)                               \
+	 << BIT_SHIFT_BCN_SPACE_CLINT2_8822C)
+#define BITS_BCN_SPACE_CLINT2_8822C                                            \
+	(BIT_MASK_BCN_SPACE_CLINT2_8822C << BIT_SHIFT_BCN_SPACE_CLINT2_8822C)
+#define BIT_CLEAR_BCN_SPACE_CLINT2_8822C(x)                                    \
+	((x) & (~BITS_BCN_SPACE_CLINT2_8822C))
+#define BIT_GET_BCN_SPACE_CLINT2_8822C(x)                                      \
+	(((x) >> BIT_SHIFT_BCN_SPACE_CLINT2_8822C) &                           \
+	 BIT_MASK_BCN_SPACE_CLINT2_8822C)
+#define BIT_SET_BCN_SPACE_CLINT2_8822C(x, v)                                   \
+	(BIT_CLEAR_BCN_SPACE_CLINT2_8822C(x) | BIT_BCN_SPACE_CLINT2_8822C(v))
+
+#define BIT_SHIFT_BCN_SPACE_CLINT1_8822C 0
+#define BIT_MASK_BCN_SPACE_CLINT1_8822C 0xfff
+#define BIT_BCN_SPACE_CLINT1_8822C(x)                                          \
+	(((x) & BIT_MASK_BCN_SPACE_CLINT1_8822C)                               \
+	 << BIT_SHIFT_BCN_SPACE_CLINT1_8822C)
+#define BITS_BCN_SPACE_CLINT1_8822C                                            \
+	(BIT_MASK_BCN_SPACE_CLINT1_8822C << BIT_SHIFT_BCN_SPACE_CLINT1_8822C)
+#define BIT_CLEAR_BCN_SPACE_CLINT1_8822C(x)                                    \
+	((x) & (~BITS_BCN_SPACE_CLINT1_8822C))
+#define BIT_GET_BCN_SPACE_CLINT1_8822C(x)                                      \
+	(((x) >> BIT_SHIFT_BCN_SPACE_CLINT1_8822C) &                           \
+	 BIT_MASK_BCN_SPACE_CLINT1_8822C)
+#define BIT_SET_BCN_SPACE_CLINT1_8822C(x, v)                                   \
+	(BIT_CLEAR_BCN_SPACE_CLINT1_8822C(x) | BIT_BCN_SPACE_CLINT1_8822C(v))
+
+/* 2 REG_MBSSID_BCN_SPACE3_8822C */
+
+#define BIT_SHIFT_SUB_BCN_SPACE_8822C 16
+#define BIT_MASK_SUB_BCN_SPACE_8822C 0xff
+#define BIT_SUB_BCN_SPACE_8822C(x)                                             \
+	(((x) & BIT_MASK_SUB_BCN_SPACE_8822C) << BIT_SHIFT_SUB_BCN_SPACE_8822C)
+#define BITS_SUB_BCN_SPACE_8822C                                               \
+	(BIT_MASK_SUB_BCN_SPACE_8822C << BIT_SHIFT_SUB_BCN_SPACE_8822C)
+#define BIT_CLEAR_SUB_BCN_SPACE_8822C(x) ((x) & (~BITS_SUB_BCN_SPACE_8822C))
+#define BIT_GET_SUB_BCN_SPACE_8822C(x)                                         \
+	(((x) >> BIT_SHIFT_SUB_BCN_SPACE_8822C) & BIT_MASK_SUB_BCN_SPACE_8822C)
+#define BIT_SET_SUB_BCN_SPACE_8822C(x, v)                                      \
+	(BIT_CLEAR_SUB_BCN_SPACE_8822C(x) | BIT_SUB_BCN_SPACE_8822C(v))
+
+#define BIT_SHIFT_BCN_SPACE_CLINT3_8822C 0
+#define BIT_MASK_BCN_SPACE_CLINT3_8822C 0xfff
+#define BIT_BCN_SPACE_CLINT3_8822C(x)                                          \
+	(((x) & BIT_MASK_BCN_SPACE_CLINT3_8822C)                               \
+	 << BIT_SHIFT_BCN_SPACE_CLINT3_8822C)
+#define BITS_BCN_SPACE_CLINT3_8822C                                            \
+	(BIT_MASK_BCN_SPACE_CLINT3_8822C << BIT_SHIFT_BCN_SPACE_CLINT3_8822C)
+#define BIT_CLEAR_BCN_SPACE_CLINT3_8822C(x)                                    \
+	((x) & (~BITS_BCN_SPACE_CLINT3_8822C))
+#define BIT_GET_BCN_SPACE_CLINT3_8822C(x)                                      \
+	(((x) >> BIT_SHIFT_BCN_SPACE_CLINT3_8822C) &                           \
+	 BIT_MASK_BCN_SPACE_CLINT3_8822C)
+#define BIT_SET_BCN_SPACE_CLINT3_8822C(x, v)                                   \
+	(BIT_CLEAR_BCN_SPACE_CLINT3_8822C(x) | BIT_BCN_SPACE_CLINT3_8822C(v))
+
+/* 2 REG_ACMHWCTRL_8822C */
+#define BIT_BEQ_ACM_STATUS_8822C BIT(7)
+#define BIT_VIQ_ACM_STATUS_8822C BIT(6)
+#define BIT_VOQ_ACM_STATUS_8822C BIT(5)
+#define BIT_BEQ_ACM_EN_8822C BIT(3)
+#define BIT_VIQ_ACM_EN_8822C BIT(2)
+#define BIT_VOQ_ACM_EN_8822C BIT(1)
+#define BIT_ACMHWEN_8822C BIT(0)
+
+/* 2 REG_ACMRSTCTRL_8822C */
+#define BIT_BE_ACM_RESET_USED_TIME_8822C BIT(2)
+#define BIT_VI_ACM_RESET_USED_TIME_8822C BIT(1)
+#define BIT_VO_ACM_RESET_USED_TIME_8822C BIT(0)
+
+/* 2 REG_ACMAVG_8822C */
+
+#define BIT_SHIFT_AVGPERIOD_8822C 0
+#define BIT_MASK_AVGPERIOD_8822C 0xffff
+#define BIT_AVGPERIOD_8822C(x)                                                 \
+	(((x) & BIT_MASK_AVGPERIOD_8822C) << BIT_SHIFT_AVGPERIOD_8822C)
+#define BITS_AVGPERIOD_8822C                                                   \
+	(BIT_MASK_AVGPERIOD_8822C << BIT_SHIFT_AVGPERIOD_8822C)
+#define BIT_CLEAR_AVGPERIOD_8822C(x) ((x) & (~BITS_AVGPERIOD_8822C))
+#define BIT_GET_AVGPERIOD_8822C(x)                                             \
+	(((x) >> BIT_SHIFT_AVGPERIOD_8822C) & BIT_MASK_AVGPERIOD_8822C)
+#define BIT_SET_AVGPERIOD_8822C(x, v)                                          \
+	(BIT_CLEAR_AVGPERIOD_8822C(x) | BIT_AVGPERIOD_8822C(v))
+
+/* 2 REG_VO_ADMTIME_8822C */
+
+#define BIT_SHIFT_VO_ADMITTED_TIME_8822C 0
+#define BIT_MASK_VO_ADMITTED_TIME_8822C 0xffff
+#define BIT_VO_ADMITTED_TIME_8822C(x)                                          \
+	(((x) & BIT_MASK_VO_ADMITTED_TIME_8822C)                               \
+	 << BIT_SHIFT_VO_ADMITTED_TIME_8822C)
+#define BITS_VO_ADMITTED_TIME_8822C                                            \
+	(BIT_MASK_VO_ADMITTED_TIME_8822C << BIT_SHIFT_VO_ADMITTED_TIME_8822C)
+#define BIT_CLEAR_VO_ADMITTED_TIME_8822C(x)                                    \
+	((x) & (~BITS_VO_ADMITTED_TIME_8822C))
+#define BIT_GET_VO_ADMITTED_TIME_8822C(x)                                      \
+	(((x) >> BIT_SHIFT_VO_ADMITTED_TIME_8822C) &                           \
+	 BIT_MASK_VO_ADMITTED_TIME_8822C)
+#define BIT_SET_VO_ADMITTED_TIME_8822C(x, v)                                   \
+	(BIT_CLEAR_VO_ADMITTED_TIME_8822C(x) | BIT_VO_ADMITTED_TIME_8822C(v))
+
+/* 2 REG_VI_ADMTIME_8822C */
+
+#define BIT_SHIFT_VI_ADMITTED_TIME_8822C 0
+#define BIT_MASK_VI_ADMITTED_TIME_8822C 0xffff
+#define BIT_VI_ADMITTED_TIME_8822C(x)                                          \
+	(((x) & BIT_MASK_VI_ADMITTED_TIME_8822C)                               \
+	 << BIT_SHIFT_VI_ADMITTED_TIME_8822C)
+#define BITS_VI_ADMITTED_TIME_8822C                                            \
+	(BIT_MASK_VI_ADMITTED_TIME_8822C << BIT_SHIFT_VI_ADMITTED_TIME_8822C)
+#define BIT_CLEAR_VI_ADMITTED_TIME_8822C(x)                                    \
+	((x) & (~BITS_VI_ADMITTED_TIME_8822C))
+#define BIT_GET_VI_ADMITTED_TIME_8822C(x)                                      \
+	(((x) >> BIT_SHIFT_VI_ADMITTED_TIME_8822C) &                           \
+	 BIT_MASK_VI_ADMITTED_TIME_8822C)
+#define BIT_SET_VI_ADMITTED_TIME_8822C(x, v)                                   \
+	(BIT_CLEAR_VI_ADMITTED_TIME_8822C(x) | BIT_VI_ADMITTED_TIME_8822C(v))
+
+/* 2 REG_BE_ADMTIME_8822C */
+
+#define BIT_SHIFT_BE_ADMITTED_TIME_8822C 0
+#define BIT_MASK_BE_ADMITTED_TIME_8822C 0xffff
+#define BIT_BE_ADMITTED_TIME_8822C(x)                                          \
+	(((x) & BIT_MASK_BE_ADMITTED_TIME_8822C)                               \
+	 << BIT_SHIFT_BE_ADMITTED_TIME_8822C)
+#define BITS_BE_ADMITTED_TIME_8822C                                            \
+	(BIT_MASK_BE_ADMITTED_TIME_8822C << BIT_SHIFT_BE_ADMITTED_TIME_8822C)
+#define BIT_CLEAR_BE_ADMITTED_TIME_8822C(x)                                    \
+	((x) & (~BITS_BE_ADMITTED_TIME_8822C))
+#define BIT_GET_BE_ADMITTED_TIME_8822C(x)                                      \
+	(((x) >> BIT_SHIFT_BE_ADMITTED_TIME_8822C) &                           \
+	 BIT_MASK_BE_ADMITTED_TIME_8822C)
+#define BIT_SET_BE_ADMITTED_TIME_8822C(x, v)                                   \
+	(BIT_CLEAR_BE_ADMITTED_TIME_8822C(x) | BIT_BE_ADMITTED_TIME_8822C(v))
+
+/* 2 REG_MAC_HEADER_NAV_OFFSET_8822C */
+
+#define BIT_SHIFT_MAC_HEADER_NAV_OFFSET_8822C 0
+#define BIT_MASK_MAC_HEADER_NAV_OFFSET_8822C 0xff
+#define BIT_MAC_HEADER_NAV_OFFSET_8822C(x)                                     \
+	(((x) & BIT_MASK_MAC_HEADER_NAV_OFFSET_8822C)                          \
+	 << BIT_SHIFT_MAC_HEADER_NAV_OFFSET_8822C)
+#define BITS_MAC_HEADER_NAV_OFFSET_8822C                                       \
+	(BIT_MASK_MAC_HEADER_NAV_OFFSET_8822C                                  \
+	 << BIT_SHIFT_MAC_HEADER_NAV_OFFSET_8822C)
+#define BIT_CLEAR_MAC_HEADER_NAV_OFFSET_8822C(x)                               \
+	((x) & (~BITS_MAC_HEADER_NAV_OFFSET_8822C))
+#define BIT_GET_MAC_HEADER_NAV_OFFSET_8822C(x)                                 \
+	(((x) >> BIT_SHIFT_MAC_HEADER_NAV_OFFSET_8822C) &                      \
+	 BIT_MASK_MAC_HEADER_NAV_OFFSET_8822C)
+#define BIT_SET_MAC_HEADER_NAV_OFFSET_8822C(x, v)                              \
+	(BIT_CLEAR_MAC_HEADER_NAV_OFFSET_8822C(x) |                            \
+	 BIT_MAC_HEADER_NAV_OFFSET_8822C(v))
+
+/* 2 REG_DIS_NDPA_NAV_CHECK_8822C */
+#define BIT_CHG_POWER_BCN_AREA_V1_8822C BIT(1)
+#define BIT_DIS_NDPA_NAV_CHECK_8822C BIT(0)
+
+/* 2 REG_EDCA_RANDOM_GEN_8822C */
+
+#define BIT_SHIFT_RANDOM_GEN_8822C 0
+#define BIT_MASK_RANDOM_GEN_8822C 0xffffff
+#define BIT_RANDOM_GEN_8822C(x)                                                \
+	(((x) & BIT_MASK_RANDOM_GEN_8822C) << BIT_SHIFT_RANDOM_GEN_8822C)
+#define BITS_RANDOM_GEN_8822C                                                  \
+	(BIT_MASK_RANDOM_GEN_8822C << BIT_SHIFT_RANDOM_GEN_8822C)
+#define BIT_CLEAR_RANDOM_GEN_8822C(x) ((x) & (~BITS_RANDOM_GEN_8822C))
+#define BIT_GET_RANDOM_GEN_8822C(x)                                            \
+	(((x) >> BIT_SHIFT_RANDOM_GEN_8822C) & BIT_MASK_RANDOM_GEN_8822C)
+#define BIT_SET_RANDOM_GEN_8822C(x, v)                                         \
+	(BIT_CLEAR_RANDOM_GEN_8822C(x) | BIT_RANDOM_GEN_8822C(v))
+
+/* 2 REG_TXCMD_NOA_SEL_8822C */
+
+#define BIT_SHIFT_NOA_SEL_V2_8822C 4
+#define BIT_MASK_NOA_SEL_V2_8822C 0x7
+#define BIT_NOA_SEL_V2_8822C(x)                                                \
+	(((x) & BIT_MASK_NOA_SEL_V2_8822C) << BIT_SHIFT_NOA_SEL_V2_8822C)
+#define BITS_NOA_SEL_V2_8822C                                                  \
+	(BIT_MASK_NOA_SEL_V2_8822C << BIT_SHIFT_NOA_SEL_V2_8822C)
+#define BIT_CLEAR_NOA_SEL_V2_8822C(x) ((x) & (~BITS_NOA_SEL_V2_8822C))
+#define BIT_GET_NOA_SEL_V2_8822C(x)                                            \
+	(((x) >> BIT_SHIFT_NOA_SEL_V2_8822C) & BIT_MASK_NOA_SEL_V2_8822C)
+#define BIT_SET_NOA_SEL_V2_8822C(x, v)                                         \
+	(BIT_CLEAR_NOA_SEL_V2_8822C(x) | BIT_NOA_SEL_V2_8822C(v))
+
+#define BIT_SHIFT_TXCMD_SEG_SEL_8822C 0
+#define BIT_MASK_TXCMD_SEG_SEL_8822C 0xf
+#define BIT_TXCMD_SEG_SEL_8822C(x)                                             \
+	(((x) & BIT_MASK_TXCMD_SEG_SEL_8822C) << BIT_SHIFT_TXCMD_SEG_SEL_8822C)
+#define BITS_TXCMD_SEG_SEL_8822C                                               \
+	(BIT_MASK_TXCMD_SEG_SEL_8822C << BIT_SHIFT_TXCMD_SEG_SEL_8822C)
+#define BIT_CLEAR_TXCMD_SEG_SEL_8822C(x) ((x) & (~BITS_TXCMD_SEG_SEL_8822C))
+#define BIT_GET_TXCMD_SEG_SEL_8822C(x)                                         \
+	(((x) >> BIT_SHIFT_TXCMD_SEG_SEL_8822C) & BIT_MASK_TXCMD_SEG_SEL_8822C)
+#define BIT_SET_TXCMD_SEG_SEL_8822C(x, v)                                      \
+	(BIT_CLEAR_TXCMD_SEG_SEL_8822C(x) | BIT_TXCMD_SEG_SEL_8822C(v))
+
+/* 2 REG_32K_CLK_SEL_8822C */
+#define BIT_R_BCNERR_CNT_EN_8822C BIT(20)
+
+#define BIT_SHIFT_R_BCNERR_PORT_SEL_8822C 16
+#define BIT_MASK_R_BCNERR_PORT_SEL_8822C 0x7
+#define BIT_R_BCNERR_PORT_SEL_8822C(x)                                         \
+	(((x) & BIT_MASK_R_BCNERR_PORT_SEL_8822C)                              \
+	 << BIT_SHIFT_R_BCNERR_PORT_SEL_8822C)
+#define BITS_R_BCNERR_PORT_SEL_8822C                                           \
+	(BIT_MASK_R_BCNERR_PORT_SEL_8822C << BIT_SHIFT_R_BCNERR_PORT_SEL_8822C)
+#define BIT_CLEAR_R_BCNERR_PORT_SEL_8822C(x)                                   \
+	((x) & (~BITS_R_BCNERR_PORT_SEL_8822C))
+#define BIT_GET_R_BCNERR_PORT_SEL_8822C(x)                                     \
+	(((x) >> BIT_SHIFT_R_BCNERR_PORT_SEL_8822C) &                          \
+	 BIT_MASK_R_BCNERR_PORT_SEL_8822C)
+#define BIT_SET_R_BCNERR_PORT_SEL_8822C(x, v)                                  \
+	(BIT_CLEAR_R_BCNERR_PORT_SEL_8822C(x) | BIT_R_BCNERR_PORT_SEL_8822C(v))
+
+#define BIT_SHIFT_R_TXPAUSE1_8822C 8
+#define BIT_MASK_R_TXPAUSE1_8822C 0xff
+#define BIT_R_TXPAUSE1_8822C(x)                                                \
+	(((x) & BIT_MASK_R_TXPAUSE1_8822C) << BIT_SHIFT_R_TXPAUSE1_8822C)
+#define BITS_R_TXPAUSE1_8822C                                                  \
+	(BIT_MASK_R_TXPAUSE1_8822C << BIT_SHIFT_R_TXPAUSE1_8822C)
+#define BIT_CLEAR_R_TXPAUSE1_8822C(x) ((x) & (~BITS_R_TXPAUSE1_8822C))
+#define BIT_GET_R_TXPAUSE1_8822C(x)                                            \
+	(((x) >> BIT_SHIFT_R_TXPAUSE1_8822C) & BIT_MASK_R_TXPAUSE1_8822C)
+#define BIT_SET_R_TXPAUSE1_8822C(x, v)                                         \
+	(BIT_CLEAR_R_TXPAUSE1_8822C(x) | BIT_R_TXPAUSE1_8822C(v))
+
+#define BIT_SLEEP_32K_EN_V1_8822C BIT(2)
+
+#define BIT_SHIFT_BW_CFG_8822C 0
+#define BIT_MASK_BW_CFG_8822C 0x3
+#define BIT_BW_CFG_8822C(x)                                                    \
+	(((x) & BIT_MASK_BW_CFG_8822C) << BIT_SHIFT_BW_CFG_8822C)
+#define BITS_BW_CFG_8822C (BIT_MASK_BW_CFG_8822C << BIT_SHIFT_BW_CFG_8822C)
+#define BIT_CLEAR_BW_CFG_8822C(x) ((x) & (~BITS_BW_CFG_8822C))
+#define BIT_GET_BW_CFG_8822C(x)                                                \
+	(((x) >> BIT_SHIFT_BW_CFG_8822C) & BIT_MASK_BW_CFG_8822C)
+#define BIT_SET_BW_CFG_8822C(x, v)                                             \
+	(BIT_CLEAR_BW_CFG_8822C(x) | BIT_BW_CFG_8822C(v))
+
+/* 2 REG_EARLYINT_ADJUST_8822C */
+
+#define BIT_SHIFT_RXBCN_TIMER_8822C 16
+#define BIT_MASK_RXBCN_TIMER_8822C 0xffff
+#define BIT_RXBCN_TIMER_8822C(x)                                               \
+	(((x) & BIT_MASK_RXBCN_TIMER_8822C) << BIT_SHIFT_RXBCN_TIMER_8822C)
+#define BITS_RXBCN_TIMER_8822C                                                 \
+	(BIT_MASK_RXBCN_TIMER_8822C << BIT_SHIFT_RXBCN_TIMER_8822C)
+#define BIT_CLEAR_RXBCN_TIMER_8822C(x) ((x) & (~BITS_RXBCN_TIMER_8822C))
+#define BIT_GET_RXBCN_TIMER_8822C(x)                                           \
+	(((x) >> BIT_SHIFT_RXBCN_TIMER_8822C) & BIT_MASK_RXBCN_TIMER_8822C)
+#define BIT_SET_RXBCN_TIMER_8822C(x, v)                                        \
+	(BIT_CLEAR_RXBCN_TIMER_8822C(x) | BIT_RXBCN_TIMER_8822C(v))
+
+#define BIT_SHIFT_R_ERLYINTADJ_8822C 0
+#define BIT_MASK_R_ERLYINTADJ_8822C 0xffff
+#define BIT_R_ERLYINTADJ_8822C(x)                                              \
+	(((x) & BIT_MASK_R_ERLYINTADJ_8822C) << BIT_SHIFT_R_ERLYINTADJ_8822C)
+#define BITS_R_ERLYINTADJ_8822C                                                \
+	(BIT_MASK_R_ERLYINTADJ_8822C << BIT_SHIFT_R_ERLYINTADJ_8822C)
+#define BIT_CLEAR_R_ERLYINTADJ_8822C(x) ((x) & (~BITS_R_ERLYINTADJ_8822C))
+#define BIT_GET_R_ERLYINTADJ_8822C(x)                                          \
+	(((x) >> BIT_SHIFT_R_ERLYINTADJ_8822C) & BIT_MASK_R_ERLYINTADJ_8822C)
+#define BIT_SET_R_ERLYINTADJ_8822C(x, v)                                       \
+	(BIT_CLEAR_R_ERLYINTADJ_8822C(x) | BIT_R_ERLYINTADJ_8822C(v))
+
+/* 2 REG_BCNERR_CNT_8822C */
+
+#define BIT_SHIFT_BCNERR_CNT_OTHERS_8822C 24
+#define BIT_MASK_BCNERR_CNT_OTHERS_8822C 0xff
+#define BIT_BCNERR_CNT_OTHERS_8822C(x)                                         \
+	(((x) & BIT_MASK_BCNERR_CNT_OTHERS_8822C)                              \
+	 << BIT_SHIFT_BCNERR_CNT_OTHERS_8822C)
+#define BITS_BCNERR_CNT_OTHERS_8822C                                           \
+	(BIT_MASK_BCNERR_CNT_OTHERS_8822C << BIT_SHIFT_BCNERR_CNT_OTHERS_8822C)
+#define BIT_CLEAR_BCNERR_CNT_OTHERS_8822C(x)                                   \
+	((x) & (~BITS_BCNERR_CNT_OTHERS_8822C))
+#define BIT_GET_BCNERR_CNT_OTHERS_8822C(x)                                     \
+	(((x) >> BIT_SHIFT_BCNERR_CNT_OTHERS_8822C) &                          \
+	 BIT_MASK_BCNERR_CNT_OTHERS_8822C)
+#define BIT_SET_BCNERR_CNT_OTHERS_8822C(x, v)                                  \
+	(BIT_CLEAR_BCNERR_CNT_OTHERS_8822C(x) | BIT_BCNERR_CNT_OTHERS_8822C(v))
+
+#define BIT_SHIFT_BCNERR_CNT_INVALID_8822C 16
+#define BIT_MASK_BCNERR_CNT_INVALID_8822C 0xff
+#define BIT_BCNERR_CNT_INVALID_8822C(x)                                        \
+	(((x) & BIT_MASK_BCNERR_CNT_INVALID_8822C)                             \
+	 << BIT_SHIFT_BCNERR_CNT_INVALID_8822C)
+#define BITS_BCNERR_CNT_INVALID_8822C                                          \
+	(BIT_MASK_BCNERR_CNT_INVALID_8822C                                     \
+	 << BIT_SHIFT_BCNERR_CNT_INVALID_8822C)
+#define BIT_CLEAR_BCNERR_CNT_INVALID_8822C(x)                                  \
+	((x) & (~BITS_BCNERR_CNT_INVALID_8822C))
+#define BIT_GET_BCNERR_CNT_INVALID_8822C(x)                                    \
+	(((x) >> BIT_SHIFT_BCNERR_CNT_INVALID_8822C) &                         \
+	 BIT_MASK_BCNERR_CNT_INVALID_8822C)
+#define BIT_SET_BCNERR_CNT_INVALID_8822C(x, v)                                 \
+	(BIT_CLEAR_BCNERR_CNT_INVALID_8822C(x) |                               \
+	 BIT_BCNERR_CNT_INVALID_8822C(v))
+
+#define BIT_SHIFT_BCNERR_CNT_MAC_8822C 8
+#define BIT_MASK_BCNERR_CNT_MAC_8822C 0xff
+#define BIT_BCNERR_CNT_MAC_8822C(x)                                            \
+	(((x) & BIT_MASK_BCNERR_CNT_MAC_8822C)                                 \
+	 << BIT_SHIFT_BCNERR_CNT_MAC_8822C)
+#define BITS_BCNERR_CNT_MAC_8822C                                              \
+	(BIT_MASK_BCNERR_CNT_MAC_8822C << BIT_SHIFT_BCNERR_CNT_MAC_8822C)
+#define BIT_CLEAR_BCNERR_CNT_MAC_8822C(x) ((x) & (~BITS_BCNERR_CNT_MAC_8822C))
+#define BIT_GET_BCNERR_CNT_MAC_8822C(x)                                        \
+	(((x) >> BIT_SHIFT_BCNERR_CNT_MAC_8822C) &                             \
+	 BIT_MASK_BCNERR_CNT_MAC_8822C)
+#define BIT_SET_BCNERR_CNT_MAC_8822C(x, v)                                     \
+	(BIT_CLEAR_BCNERR_CNT_MAC_8822C(x) | BIT_BCNERR_CNT_MAC_8822C(v))
+
+#define BIT_SHIFT_BCNERR_CNT_CCA_8822C 0
+#define BIT_MASK_BCNERR_CNT_CCA_8822C 0xff
+#define BIT_BCNERR_CNT_CCA_8822C(x)                                            \
+	(((x) & BIT_MASK_BCNERR_CNT_CCA_8822C)                                 \
+	 << BIT_SHIFT_BCNERR_CNT_CCA_8822C)
+#define BITS_BCNERR_CNT_CCA_8822C                                              \
+	(BIT_MASK_BCNERR_CNT_CCA_8822C << BIT_SHIFT_BCNERR_CNT_CCA_8822C)
+#define BIT_CLEAR_BCNERR_CNT_CCA_8822C(x) ((x) & (~BITS_BCNERR_CNT_CCA_8822C))
+#define BIT_GET_BCNERR_CNT_CCA_8822C(x)                                        \
+	(((x) >> BIT_SHIFT_BCNERR_CNT_CCA_8822C) &                             \
+	 BIT_MASK_BCNERR_CNT_CCA_8822C)
+#define BIT_SET_BCNERR_CNT_CCA_8822C(x, v)                                     \
+	(BIT_CLEAR_BCNERR_CNT_CCA_8822C(x) | BIT_BCNERR_CNT_CCA_8822C(v))
+
+/* 2 REG_BCNERR_CNT_2_8822C */
+
+#define BIT_SHIFT_BCNERR_CNT_EDCCA_8822C 0
+#define BIT_MASK_BCNERR_CNT_EDCCA_8822C 0xff
+#define BIT_BCNERR_CNT_EDCCA_8822C(x)                                          \
+	(((x) & BIT_MASK_BCNERR_CNT_EDCCA_8822C)                               \
+	 << BIT_SHIFT_BCNERR_CNT_EDCCA_8822C)
+#define BITS_BCNERR_CNT_EDCCA_8822C                                            \
+	(BIT_MASK_BCNERR_CNT_EDCCA_8822C << BIT_SHIFT_BCNERR_CNT_EDCCA_8822C)
+#define BIT_CLEAR_BCNERR_CNT_EDCCA_8822C(x)                                    \
+	((x) & (~BITS_BCNERR_CNT_EDCCA_8822C))
+#define BIT_GET_BCNERR_CNT_EDCCA_8822C(x)                                      \
+	(((x) >> BIT_SHIFT_BCNERR_CNT_EDCCA_8822C) &                           \
+	 BIT_MASK_BCNERR_CNT_EDCCA_8822C)
+#define BIT_SET_BCNERR_CNT_EDCCA_8822C(x, v)                                   \
+	(BIT_CLEAR_BCNERR_CNT_EDCCA_8822C(x) | BIT_BCNERR_CNT_EDCCA_8822C(v))
+
+/* 2 REG_NOA_PARAM_8822C */
+
+#define BIT_SHIFT_NOA_DURATION_V1_8822C 0
+#define BIT_MASK_NOA_DURATION_V1_8822C 0xffffffffL
+#define BIT_NOA_DURATION_V1_8822C(x)                                           \
+	(((x) & BIT_MASK_NOA_DURATION_V1_8822C)                                \
+	 << BIT_SHIFT_NOA_DURATION_V1_8822C)
+#define BITS_NOA_DURATION_V1_8822C                                             \
+	(BIT_MASK_NOA_DURATION_V1_8822C << BIT_SHIFT_NOA_DURATION_V1_8822C)
+#define BIT_CLEAR_NOA_DURATION_V1_8822C(x) ((x) & (~BITS_NOA_DURATION_V1_8822C))
+#define BIT_GET_NOA_DURATION_V1_8822C(x)                                       \
+	(((x) >> BIT_SHIFT_NOA_DURATION_V1_8822C) &                            \
+	 BIT_MASK_NOA_DURATION_V1_8822C)
+#define BIT_SET_NOA_DURATION_V1_8822C(x, v)                                    \
+	(BIT_CLEAR_NOA_DURATION_V1_8822C(x) | BIT_NOA_DURATION_V1_8822C(v))
+
+/* 2 REG_NOA_PARAM_1_8822C */
+
+#define BIT_SHIFT_NOA_INTERVAL_V1_8822C 0
+#define BIT_MASK_NOA_INTERVAL_V1_8822C 0xffffffffL
+#define BIT_NOA_INTERVAL_V1_8822C(x)                                           \
+	(((x) & BIT_MASK_NOA_INTERVAL_V1_8822C)                                \
+	 << BIT_SHIFT_NOA_INTERVAL_V1_8822C)
+#define BITS_NOA_INTERVAL_V1_8822C                                             \
+	(BIT_MASK_NOA_INTERVAL_V1_8822C << BIT_SHIFT_NOA_INTERVAL_V1_8822C)
+#define BIT_CLEAR_NOA_INTERVAL_V1_8822C(x) ((x) & (~BITS_NOA_INTERVAL_V1_8822C))
+#define BIT_GET_NOA_INTERVAL_V1_8822C(x)                                       \
+	(((x) >> BIT_SHIFT_NOA_INTERVAL_V1_8822C) &                            \
+	 BIT_MASK_NOA_INTERVAL_V1_8822C)
+#define BIT_SET_NOA_INTERVAL_V1_8822C(x, v)                                    \
+	(BIT_CLEAR_NOA_INTERVAL_V1_8822C(x) | BIT_NOA_INTERVAL_V1_8822C(v))
+
+/* 2 REG_NOA_PARAM_2_8822C */
+
+#define BIT_SHIFT_NOA_START_TIME_V1_8822C 0
+#define BIT_MASK_NOA_START_TIME_V1_8822C 0xffffffffL
+#define BIT_NOA_START_TIME_V1_8822C(x)                                         \
+	(((x) & BIT_MASK_NOA_START_TIME_V1_8822C)                              \
+	 << BIT_SHIFT_NOA_START_TIME_V1_8822C)
+#define BITS_NOA_START_TIME_V1_8822C                                           \
+	(BIT_MASK_NOA_START_TIME_V1_8822C << BIT_SHIFT_NOA_START_TIME_V1_8822C)
+#define BIT_CLEAR_NOA_START_TIME_V1_8822C(x)                                   \
+	((x) & (~BITS_NOA_START_TIME_V1_8822C))
+#define BIT_GET_NOA_START_TIME_V1_8822C(x)                                     \
+	(((x) >> BIT_SHIFT_NOA_START_TIME_V1_8822C) &                          \
+	 BIT_MASK_NOA_START_TIME_V1_8822C)
+#define BIT_SET_NOA_START_TIME_V1_8822C(x, v)                                  \
+	(BIT_CLEAR_NOA_START_TIME_V1_8822C(x) | BIT_NOA_START_TIME_V1_8822C(v))
+
+/* 2 REG_NOA_PARAM_3_8822C */
+
+#define BIT_SHIFT_NOA_COUNT_V1_8822C 0
+#define BIT_MASK_NOA_COUNT_V1_8822C 0xffffffffL
+#define BIT_NOA_COUNT_V1_8822C(x)                                              \
+	(((x) & BIT_MASK_NOA_COUNT_V1_8822C) << BIT_SHIFT_NOA_COUNT_V1_8822C)
+#define BITS_NOA_COUNT_V1_8822C                                                \
+	(BIT_MASK_NOA_COUNT_V1_8822C << BIT_SHIFT_NOA_COUNT_V1_8822C)
+#define BIT_CLEAR_NOA_COUNT_V1_8822C(x) ((x) & (~BITS_NOA_COUNT_V1_8822C))
+#define BIT_GET_NOA_COUNT_V1_8822C(x)                                          \
+	(((x) >> BIT_SHIFT_NOA_COUNT_V1_8822C) & BIT_MASK_NOA_COUNT_V1_8822C)
+#define BIT_SET_NOA_COUNT_V1_8822C(x, v)                                       \
+	(BIT_CLEAR_NOA_COUNT_V1_8822C(x) | BIT_NOA_COUNT_V1_8822C(v))
+
+/* 2 REG_P2P_RST_8822C */
+#define BIT_P2P2_PWR_RST1_8822C BIT(5)
+#define BIT_P2P2_PWR_RST0_8822C BIT(4)
+#define BIT_P2P1_PWR_RST1_8822C BIT(3)
+#define BIT_P2P1_PWR_RST0_8822C BIT(2)
+#define BIT_P2P_PWR_RST1_V1_8822C BIT(1)
+#define BIT_P2P_PWR_RST0_V1_8822C BIT(0)
+
+/* 2 REG_SCHEDULER_RST_8822C */
+#define BIT_SYNC_CLI_ONCE_RIGHT_NOW_8822C BIT(2)
+#define BIT_SYNC_CLI_ONCE_BY_TBTT_8822C BIT(1)
+#define BIT_SCHEDULER_RST_V1_8822C BIT(0)
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_SCH_DBG_VALUE_8822C */
+
+#define BIT_SHIFT_SCH_DBG_VALUE_8822C 0
+#define BIT_MASK_SCH_DBG_VALUE_8822C 0xffffffffL
+#define BIT_SCH_DBG_VALUE_8822C(x)                                             \
+	(((x) & BIT_MASK_SCH_DBG_VALUE_8822C) << BIT_SHIFT_SCH_DBG_VALUE_8822C)
+#define BITS_SCH_DBG_VALUE_8822C                                               \
+	(BIT_MASK_SCH_DBG_VALUE_8822C << BIT_SHIFT_SCH_DBG_VALUE_8822C)
+#define BIT_CLEAR_SCH_DBG_VALUE_8822C(x) ((x) & (~BITS_SCH_DBG_VALUE_8822C))
+#define BIT_GET_SCH_DBG_VALUE_8822C(x)                                         \
+	(((x) >> BIT_SHIFT_SCH_DBG_VALUE_8822C) & BIT_MASK_SCH_DBG_VALUE_8822C)
+#define BIT_SET_SCH_DBG_VALUE_8822C(x, v)                                      \
+	(BIT_CLEAR_SCH_DBG_VALUE_8822C(x) | BIT_SCH_DBG_VALUE_8822C(v))
+
+/* 2 REG_SCH_TXCMD_8822C */
+
+#define BIT_SHIFT_SCH_TXCMD_8822C 0
+#define BIT_MASK_SCH_TXCMD_8822C 0xffffffffL
+#define BIT_SCH_TXCMD_8822C(x)                                                 \
+	(((x) & BIT_MASK_SCH_TXCMD_8822C) << BIT_SHIFT_SCH_TXCMD_8822C)
+#define BITS_SCH_TXCMD_8822C                                                   \
+	(BIT_MASK_SCH_TXCMD_8822C << BIT_SHIFT_SCH_TXCMD_8822C)
+#define BIT_CLEAR_SCH_TXCMD_8822C(x) ((x) & (~BITS_SCH_TXCMD_8822C))
+#define BIT_GET_SCH_TXCMD_8822C(x)                                             \
+	(((x) >> BIT_SHIFT_SCH_TXCMD_8822C) & BIT_MASK_SCH_TXCMD_8822C)
+#define BIT_SET_SCH_TXCMD_8822C(x, v)                                          \
+	(BIT_CLEAR_SCH_TXCMD_8822C(x) | BIT_SCH_TXCMD_8822C(v))
+
+/* 2 REG_PAGE5_DUMMY_8822C */
+
+/* 2 REG_CPUMGQ_TX_TIMER_8822C */
+
+#define BIT_SHIFT_CPUMGQ_TX_TIMER_V1_8822C 0
+#define BIT_MASK_CPUMGQ_TX_TIMER_V1_8822C 0xffffffffL
+#define BIT_CPUMGQ_TX_TIMER_V1_8822C(x)                                        \
+	(((x) & BIT_MASK_CPUMGQ_TX_TIMER_V1_8822C)                             \
+	 << BIT_SHIFT_CPUMGQ_TX_TIMER_V1_8822C)
+#define BITS_CPUMGQ_TX_TIMER_V1_8822C                                          \
+	(BIT_MASK_CPUMGQ_TX_TIMER_V1_8822C                                     \
+	 << BIT_SHIFT_CPUMGQ_TX_TIMER_V1_8822C)
+#define BIT_CLEAR_CPUMGQ_TX_TIMER_V1_8822C(x)                                  \
+	((x) & (~BITS_CPUMGQ_TX_TIMER_V1_8822C))
+#define BIT_GET_CPUMGQ_TX_TIMER_V1_8822C(x)                                    \
+	(((x) >> BIT_SHIFT_CPUMGQ_TX_TIMER_V1_8822C) &                         \
+	 BIT_MASK_CPUMGQ_TX_TIMER_V1_8822C)
+#define BIT_SET_CPUMGQ_TX_TIMER_V1_8822C(x, v)                                 \
+	(BIT_CLEAR_CPUMGQ_TX_TIMER_V1_8822C(x) |                               \
+	 BIT_CPUMGQ_TX_TIMER_V1_8822C(v))
+
+/* 2 REG_PS_TIMER_A_8822C */
+
+#define BIT_SHIFT_PS_TIMER_A_V1_8822C 0
+#define BIT_MASK_PS_TIMER_A_V1_8822C 0xffffffffL
+#define BIT_PS_TIMER_A_V1_8822C(x)                                             \
+	(((x) & BIT_MASK_PS_TIMER_A_V1_8822C) << BIT_SHIFT_PS_TIMER_A_V1_8822C)
+#define BITS_PS_TIMER_A_V1_8822C                                               \
+	(BIT_MASK_PS_TIMER_A_V1_8822C << BIT_SHIFT_PS_TIMER_A_V1_8822C)
+#define BIT_CLEAR_PS_TIMER_A_V1_8822C(x) ((x) & (~BITS_PS_TIMER_A_V1_8822C))
+#define BIT_GET_PS_TIMER_A_V1_8822C(x)                                         \
+	(((x) >> BIT_SHIFT_PS_TIMER_A_V1_8822C) & BIT_MASK_PS_TIMER_A_V1_8822C)
+#define BIT_SET_PS_TIMER_A_V1_8822C(x, v)                                      \
+	(BIT_CLEAR_PS_TIMER_A_V1_8822C(x) | BIT_PS_TIMER_A_V1_8822C(v))
+
+/* 2 REG_PS_TIMER_B_8822C */
+
+#define BIT_SHIFT_PS_TIMER_B_V1_8822C 0
+#define BIT_MASK_PS_TIMER_B_V1_8822C 0xffffffffL
+#define BIT_PS_TIMER_B_V1_8822C(x)                                             \
+	(((x) & BIT_MASK_PS_TIMER_B_V1_8822C) << BIT_SHIFT_PS_TIMER_B_V1_8822C)
+#define BITS_PS_TIMER_B_V1_8822C                                               \
+	(BIT_MASK_PS_TIMER_B_V1_8822C << BIT_SHIFT_PS_TIMER_B_V1_8822C)
+#define BIT_CLEAR_PS_TIMER_B_V1_8822C(x) ((x) & (~BITS_PS_TIMER_B_V1_8822C))
+#define BIT_GET_PS_TIMER_B_V1_8822C(x)                                         \
+	(((x) >> BIT_SHIFT_PS_TIMER_B_V1_8822C) & BIT_MASK_PS_TIMER_B_V1_8822C)
+#define BIT_SET_PS_TIMER_B_V1_8822C(x, v)                                      \
+	(BIT_CLEAR_PS_TIMER_B_V1_8822C(x) | BIT_PS_TIMER_B_V1_8822C(v))
+
+/* 2 REG_PS_TIMER_C_8822C */
+
+#define BIT_SHIFT_PS_TIMER_C_V1_8822C 0
+#define BIT_MASK_PS_TIMER_C_V1_8822C 0xffffffffL
+#define BIT_PS_TIMER_C_V1_8822C(x)                                             \
+	(((x) & BIT_MASK_PS_TIMER_C_V1_8822C) << BIT_SHIFT_PS_TIMER_C_V1_8822C)
+#define BITS_PS_TIMER_C_V1_8822C                                               \
+	(BIT_MASK_PS_TIMER_C_V1_8822C << BIT_SHIFT_PS_TIMER_C_V1_8822C)
+#define BIT_CLEAR_PS_TIMER_C_V1_8822C(x) ((x) & (~BITS_PS_TIMER_C_V1_8822C))
+#define BIT_GET_PS_TIMER_C_V1_8822C(x)                                         \
+	(((x) >> BIT_SHIFT_PS_TIMER_C_V1_8822C) & BIT_MASK_PS_TIMER_C_V1_8822C)
+#define BIT_SET_PS_TIMER_C_V1_8822C(x, v)                                      \
+	(BIT_CLEAR_PS_TIMER_C_V1_8822C(x) | BIT_PS_TIMER_C_V1_8822C(v))
+
+/* 2 REG_PS_TIMER_ABC_CPUMGQ_TIMER_CRTL_8822C */
+#define BIT_CPUMGQ_TIMER_EN_8822C BIT(31)
+#define BIT_CPUMGQ_TX_EN_8822C BIT(28)
+
+#define BIT_SHIFT_CPUMGQ_TIMER_TSF_SEL_8822C 24
+#define BIT_MASK_CPUMGQ_TIMER_TSF_SEL_8822C 0x7
+#define BIT_CPUMGQ_TIMER_TSF_SEL_8822C(x)                                      \
+	(((x) & BIT_MASK_CPUMGQ_TIMER_TSF_SEL_8822C)                           \
+	 << BIT_SHIFT_CPUMGQ_TIMER_TSF_SEL_8822C)
+#define BITS_CPUMGQ_TIMER_TSF_SEL_8822C                                        \
+	(BIT_MASK_CPUMGQ_TIMER_TSF_SEL_8822C                                   \
+	 << BIT_SHIFT_CPUMGQ_TIMER_TSF_SEL_8822C)
+#define BIT_CLEAR_CPUMGQ_TIMER_TSF_SEL_8822C(x)                                \
+	((x) & (~BITS_CPUMGQ_TIMER_TSF_SEL_8822C))
+#define BIT_GET_CPUMGQ_TIMER_TSF_SEL_8822C(x)                                  \
+	(((x) >> BIT_SHIFT_CPUMGQ_TIMER_TSF_SEL_8822C) &                       \
+	 BIT_MASK_CPUMGQ_TIMER_TSF_SEL_8822C)
+#define BIT_SET_CPUMGQ_TIMER_TSF_SEL_8822C(x, v)                               \
+	(BIT_CLEAR_CPUMGQ_TIMER_TSF_SEL_8822C(x) |                             \
+	 BIT_CPUMGQ_TIMER_TSF_SEL_8822C(v))
+
+#define BIT_PS_TIMER_C_EN_8822C BIT(23)
+
+#define BIT_SHIFT_PS_TIMER_C_TSF_SEL_8822C 16
+#define BIT_MASK_PS_TIMER_C_TSF_SEL_8822C 0x7
+#define BIT_PS_TIMER_C_TSF_SEL_8822C(x)                                        \
+	(((x) & BIT_MASK_PS_TIMER_C_TSF_SEL_8822C)                             \
+	 << BIT_SHIFT_PS_TIMER_C_TSF_SEL_8822C)
+#define BITS_PS_TIMER_C_TSF_SEL_8822C                                          \
+	(BIT_MASK_PS_TIMER_C_TSF_SEL_8822C                                     \
+	 << BIT_SHIFT_PS_TIMER_C_TSF_SEL_8822C)
+#define BIT_CLEAR_PS_TIMER_C_TSF_SEL_8822C(x)                                  \
+	((x) & (~BITS_PS_TIMER_C_TSF_SEL_8822C))
+#define BIT_GET_PS_TIMER_C_TSF_SEL_8822C(x)                                    \
+	(((x) >> BIT_SHIFT_PS_TIMER_C_TSF_SEL_8822C) &                         \
+	 BIT_MASK_PS_TIMER_C_TSF_SEL_8822C)
+#define BIT_SET_PS_TIMER_C_TSF_SEL_8822C(x, v)                                 \
+	(BIT_CLEAR_PS_TIMER_C_TSF_SEL_8822C(x) |                               \
+	 BIT_PS_TIMER_C_TSF_SEL_8822C(v))
+
+#define BIT_PS_TIMER_B_EN_8822C BIT(15)
+
+#define BIT_SHIFT_PS_TIMER_B_TSF_SEL_8822C 8
+#define BIT_MASK_PS_TIMER_B_TSF_SEL_8822C 0x7
+#define BIT_PS_TIMER_B_TSF_SEL_8822C(x)                                        \
+	(((x) & BIT_MASK_PS_TIMER_B_TSF_SEL_8822C)                             \
+	 << BIT_SHIFT_PS_TIMER_B_TSF_SEL_8822C)
+#define BITS_PS_TIMER_B_TSF_SEL_8822C                                          \
+	(BIT_MASK_PS_TIMER_B_TSF_SEL_8822C                                     \
+	 << BIT_SHIFT_PS_TIMER_B_TSF_SEL_8822C)
+#define BIT_CLEAR_PS_TIMER_B_TSF_SEL_8822C(x)                                  \
+	((x) & (~BITS_PS_TIMER_B_TSF_SEL_8822C))
+#define BIT_GET_PS_TIMER_B_TSF_SEL_8822C(x)                                    \
+	(((x) >> BIT_SHIFT_PS_TIMER_B_TSF_SEL_8822C) &                         \
+	 BIT_MASK_PS_TIMER_B_TSF_SEL_8822C)
+#define BIT_SET_PS_TIMER_B_TSF_SEL_8822C(x, v)                                 \
+	(BIT_CLEAR_PS_TIMER_B_TSF_SEL_8822C(x) |                               \
+	 BIT_PS_TIMER_B_TSF_SEL_8822C(v))
+
+#define BIT_PS_TIMER_A_EN_8822C BIT(7)
+
+#define BIT_SHIFT_PS_TIMER_A_TSF_SEL_8822C 0
+#define BIT_MASK_PS_TIMER_A_TSF_SEL_8822C 0x7
+#define BIT_PS_TIMER_A_TSF_SEL_8822C(x)                                        \
+	(((x) & BIT_MASK_PS_TIMER_A_TSF_SEL_8822C)                             \
+	 << BIT_SHIFT_PS_TIMER_A_TSF_SEL_8822C)
+#define BITS_PS_TIMER_A_TSF_SEL_8822C                                          \
+	(BIT_MASK_PS_TIMER_A_TSF_SEL_8822C                                     \
+	 << BIT_SHIFT_PS_TIMER_A_TSF_SEL_8822C)
+#define BIT_CLEAR_PS_TIMER_A_TSF_SEL_8822C(x)                                  \
+	((x) & (~BITS_PS_TIMER_A_TSF_SEL_8822C))
+#define BIT_GET_PS_TIMER_A_TSF_SEL_8822C(x)                                    \
+	(((x) >> BIT_SHIFT_PS_TIMER_A_TSF_SEL_8822C) &                         \
+	 BIT_MASK_PS_TIMER_A_TSF_SEL_8822C)
+#define BIT_SET_PS_TIMER_A_TSF_SEL_8822C(x, v)                                 \
+	(BIT_CLEAR_PS_TIMER_A_TSF_SEL_8822C(x) |                               \
+	 BIT_PS_TIMER_A_TSF_SEL_8822C(v))
+
+/* 2 REG_CPUMGQ_TX_TIMER_EARLY_8822C */
+
+#define BIT_SHIFT_CPUMGQ_TX_TIMER_EARLY_8822C 0
+#define BIT_MASK_CPUMGQ_TX_TIMER_EARLY_8822C 0xff
+#define BIT_CPUMGQ_TX_TIMER_EARLY_8822C(x)                                     \
+	(((x) & BIT_MASK_CPUMGQ_TX_TIMER_EARLY_8822C)                          \
+	 << BIT_SHIFT_CPUMGQ_TX_TIMER_EARLY_8822C)
+#define BITS_CPUMGQ_TX_TIMER_EARLY_8822C                                       \
+	(BIT_MASK_CPUMGQ_TX_TIMER_EARLY_8822C                                  \
+	 << BIT_SHIFT_CPUMGQ_TX_TIMER_EARLY_8822C)
+#define BIT_CLEAR_CPUMGQ_TX_TIMER_EARLY_8822C(x)                               \
+	((x) & (~BITS_CPUMGQ_TX_TIMER_EARLY_8822C))
+#define BIT_GET_CPUMGQ_TX_TIMER_EARLY_8822C(x)                                 \
+	(((x) >> BIT_SHIFT_CPUMGQ_TX_TIMER_EARLY_8822C) &                      \
+	 BIT_MASK_CPUMGQ_TX_TIMER_EARLY_8822C)
+#define BIT_SET_CPUMGQ_TX_TIMER_EARLY_8822C(x, v)                              \
+	(BIT_CLEAR_CPUMGQ_TX_TIMER_EARLY_8822C(x) |                            \
+	 BIT_CPUMGQ_TX_TIMER_EARLY_8822C(v))
+
+/* 2 REG_PS_TIMER_A_EARLY_8822C */
+
+#define BIT_SHIFT_PS_TIMER_A_EARLY_8822C 0
+#define BIT_MASK_PS_TIMER_A_EARLY_8822C 0xff
+#define BIT_PS_TIMER_A_EARLY_8822C(x)                                          \
+	(((x) & BIT_MASK_PS_TIMER_A_EARLY_8822C)                               \
+	 << BIT_SHIFT_PS_TIMER_A_EARLY_8822C)
+#define BITS_PS_TIMER_A_EARLY_8822C                                            \
+	(BIT_MASK_PS_TIMER_A_EARLY_8822C << BIT_SHIFT_PS_TIMER_A_EARLY_8822C)
+#define BIT_CLEAR_PS_TIMER_A_EARLY_8822C(x)                                    \
+	((x) & (~BITS_PS_TIMER_A_EARLY_8822C))
+#define BIT_GET_PS_TIMER_A_EARLY_8822C(x)                                      \
+	(((x) >> BIT_SHIFT_PS_TIMER_A_EARLY_8822C) &                           \
+	 BIT_MASK_PS_TIMER_A_EARLY_8822C)
+#define BIT_SET_PS_TIMER_A_EARLY_8822C(x, v)                                   \
+	(BIT_CLEAR_PS_TIMER_A_EARLY_8822C(x) | BIT_PS_TIMER_A_EARLY_8822C(v))
+
+/* 2 REG_PS_TIMER_B_EARLY_8822C */
+
+#define BIT_SHIFT_PS_TIMER_B_EARLY_8822C 0
+#define BIT_MASK_PS_TIMER_B_EARLY_8822C 0xff
+#define BIT_PS_TIMER_B_EARLY_8822C(x)                                          \
+	(((x) & BIT_MASK_PS_TIMER_B_EARLY_8822C)                               \
+	 << BIT_SHIFT_PS_TIMER_B_EARLY_8822C)
+#define BITS_PS_TIMER_B_EARLY_8822C                                            \
+	(BIT_MASK_PS_TIMER_B_EARLY_8822C << BIT_SHIFT_PS_TIMER_B_EARLY_8822C)
+#define BIT_CLEAR_PS_TIMER_B_EARLY_8822C(x)                                    \
+	((x) & (~BITS_PS_TIMER_B_EARLY_8822C))
+#define BIT_GET_PS_TIMER_B_EARLY_8822C(x)                                      \
+	(((x) >> BIT_SHIFT_PS_TIMER_B_EARLY_8822C) &                           \
+	 BIT_MASK_PS_TIMER_B_EARLY_8822C)
+#define BIT_SET_PS_TIMER_B_EARLY_8822C(x, v)                                   \
+	(BIT_CLEAR_PS_TIMER_B_EARLY_8822C(x) | BIT_PS_TIMER_B_EARLY_8822C(v))
+
+/* 2 REG_PS_TIMER_C_EARLY_8822C */
+
+#define BIT_SHIFT_PS_TIMER_C_EARLY_8822C 0
+#define BIT_MASK_PS_TIMER_C_EARLY_8822C 0xff
+#define BIT_PS_TIMER_C_EARLY_8822C(x)                                          \
+	(((x) & BIT_MASK_PS_TIMER_C_EARLY_8822C)                               \
+	 << BIT_SHIFT_PS_TIMER_C_EARLY_8822C)
+#define BITS_PS_TIMER_C_EARLY_8822C                                            \
+	(BIT_MASK_PS_TIMER_C_EARLY_8822C << BIT_SHIFT_PS_TIMER_C_EARLY_8822C)
+#define BIT_CLEAR_PS_TIMER_C_EARLY_8822C(x)                                    \
+	((x) & (~BITS_PS_TIMER_C_EARLY_8822C))
+#define BIT_GET_PS_TIMER_C_EARLY_8822C(x)                                      \
+	(((x) >> BIT_SHIFT_PS_TIMER_C_EARLY_8822C) &                           \
+	 BIT_MASK_PS_TIMER_C_EARLY_8822C)
+#define BIT_SET_PS_TIMER_C_EARLY_8822C(x, v)                                   \
+	(BIT_CLEAR_PS_TIMER_C_EARLY_8822C(x) | BIT_PS_TIMER_C_EARLY_8822C(v))
+
+/* 2 REG_CPUMGQ_PARAMETER_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+#define BIT_MAC_STOP_CPUMGQ_8822C BIT(16)
+
+#define BIT_SHIFT_CW_8822C 8
+#define BIT_MASK_CW_8822C 0xff
+#define BIT_CW_8822C(x) (((x) & BIT_MASK_CW_8822C) << BIT_SHIFT_CW_8822C)
+#define BITS_CW_8822C (BIT_MASK_CW_8822C << BIT_SHIFT_CW_8822C)
+#define BIT_CLEAR_CW_8822C(x) ((x) & (~BITS_CW_8822C))
+#define BIT_GET_CW_8822C(x) (((x) >> BIT_SHIFT_CW_8822C) & BIT_MASK_CW_8822C)
+#define BIT_SET_CW_8822C(x, v) (BIT_CLEAR_CW_8822C(x) | BIT_CW_8822C(v))
+
+#define BIT_SHIFT_AIFS_8822C 0
+#define BIT_MASK_AIFS_8822C 0xff
+#define BIT_AIFS_8822C(x) (((x) & BIT_MASK_AIFS_8822C) << BIT_SHIFT_AIFS_8822C)
+#define BITS_AIFS_8822C (BIT_MASK_AIFS_8822C << BIT_SHIFT_AIFS_8822C)
+#define BIT_CLEAR_AIFS_8822C(x) ((x) & (~BITS_AIFS_8822C))
+#define BIT_GET_AIFS_8822C(x)                                                  \
+	(((x) >> BIT_SHIFT_AIFS_8822C) & BIT_MASK_AIFS_8822C)
+#define BIT_SET_AIFS_8822C(x, v) (BIT_CLEAR_AIFS_8822C(x) | BIT_AIFS_8822C(v))
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_TSF_SYNC_ADJ_8822C */
+
+#define BIT_SHIFT_R_P0_TSFT_ADJ_VAL_8822C 16
+#define BIT_MASK_R_P0_TSFT_ADJ_VAL_8822C 0xffff
+#define BIT_R_P0_TSFT_ADJ_VAL_8822C(x)                                         \
+	(((x) & BIT_MASK_R_P0_TSFT_ADJ_VAL_8822C)                              \
+	 << BIT_SHIFT_R_P0_TSFT_ADJ_VAL_8822C)
+#define BITS_R_P0_TSFT_ADJ_VAL_8822C                                           \
+	(BIT_MASK_R_P0_TSFT_ADJ_VAL_8822C << BIT_SHIFT_R_P0_TSFT_ADJ_VAL_8822C)
+#define BIT_CLEAR_R_P0_TSFT_ADJ_VAL_8822C(x)                                   \
+	((x) & (~BITS_R_P0_TSFT_ADJ_VAL_8822C))
+#define BIT_GET_R_P0_TSFT_ADJ_VAL_8822C(x)                                     \
+	(((x) >> BIT_SHIFT_R_P0_TSFT_ADJ_VAL_8822C) &                          \
+	 BIT_MASK_R_P0_TSFT_ADJ_VAL_8822C)
+#define BIT_SET_R_P0_TSFT_ADJ_VAL_8822C(x, v)                                  \
+	(BIT_CLEAR_R_P0_TSFT_ADJ_VAL_8822C(x) | BIT_R_P0_TSFT_ADJ_VAL_8822C(v))
+
+#define BIT_R_X_COMP_Y_OVER_8822C BIT(8)
+
+#define BIT_SHIFT_R_X_SYNC_SEL_8822C 3
+#define BIT_MASK_R_X_SYNC_SEL_8822C 0x7
+#define BIT_R_X_SYNC_SEL_8822C(x)                                              \
+	(((x) & BIT_MASK_R_X_SYNC_SEL_8822C) << BIT_SHIFT_R_X_SYNC_SEL_8822C)
+#define BITS_R_X_SYNC_SEL_8822C                                                \
+	(BIT_MASK_R_X_SYNC_SEL_8822C << BIT_SHIFT_R_X_SYNC_SEL_8822C)
+#define BIT_CLEAR_R_X_SYNC_SEL_8822C(x) ((x) & (~BITS_R_X_SYNC_SEL_8822C))
+#define BIT_GET_R_X_SYNC_SEL_8822C(x)                                          \
+	(((x) >> BIT_SHIFT_R_X_SYNC_SEL_8822C) & BIT_MASK_R_X_SYNC_SEL_8822C)
+#define BIT_SET_R_X_SYNC_SEL_8822C(x, v)                                       \
+	(BIT_CLEAR_R_X_SYNC_SEL_8822C(x) | BIT_R_X_SYNC_SEL_8822C(v))
+
+#define BIT_SHIFT_R_SYNC_Y_SEL_8822C 0
+#define BIT_MASK_R_SYNC_Y_SEL_8822C 0x7
+#define BIT_R_SYNC_Y_SEL_8822C(x)                                              \
+	(((x) & BIT_MASK_R_SYNC_Y_SEL_8822C) << BIT_SHIFT_R_SYNC_Y_SEL_8822C)
+#define BITS_R_SYNC_Y_SEL_8822C                                                \
+	(BIT_MASK_R_SYNC_Y_SEL_8822C << BIT_SHIFT_R_SYNC_Y_SEL_8822C)
+#define BIT_CLEAR_R_SYNC_Y_SEL_8822C(x) ((x) & (~BITS_R_SYNC_Y_SEL_8822C))
+#define BIT_GET_R_SYNC_Y_SEL_8822C(x)                                          \
+	(((x) >> BIT_SHIFT_R_SYNC_Y_SEL_8822C) & BIT_MASK_R_SYNC_Y_SEL_8822C)
+#define BIT_SET_R_SYNC_Y_SEL_8822C(x, v)                                       \
+	(BIT_CLEAR_R_SYNC_Y_SEL_8822C(x) | BIT_R_SYNC_Y_SEL_8822C(v))
+
+/* 2 REG_TSF_ADJ_VLAUE_8822C */
+
+#define BIT_SHIFT_R_CLI1_TSFT_ADJ_VAL_8822C 16
+#define BIT_MASK_R_CLI1_TSFT_ADJ_VAL_8822C 0xffff
+#define BIT_R_CLI1_TSFT_ADJ_VAL_8822C(x)                                       \
+	(((x) & BIT_MASK_R_CLI1_TSFT_ADJ_VAL_8822C)                            \
+	 << BIT_SHIFT_R_CLI1_TSFT_ADJ_VAL_8822C)
+#define BITS_R_CLI1_TSFT_ADJ_VAL_8822C                                         \
+	(BIT_MASK_R_CLI1_TSFT_ADJ_VAL_8822C                                    \
+	 << BIT_SHIFT_R_CLI1_TSFT_ADJ_VAL_8822C)
+#define BIT_CLEAR_R_CLI1_TSFT_ADJ_VAL_8822C(x)                                 \
+	((x) & (~BITS_R_CLI1_TSFT_ADJ_VAL_8822C))
+#define BIT_GET_R_CLI1_TSFT_ADJ_VAL_8822C(x)                                   \
+	(((x) >> BIT_SHIFT_R_CLI1_TSFT_ADJ_VAL_8822C) &                        \
+	 BIT_MASK_R_CLI1_TSFT_ADJ_VAL_8822C)
+#define BIT_SET_R_CLI1_TSFT_ADJ_VAL_8822C(x, v)                                \
+	(BIT_CLEAR_R_CLI1_TSFT_ADJ_VAL_8822C(x) |                              \
+	 BIT_R_CLI1_TSFT_ADJ_VAL_8822C(v))
+
+#define BIT_SHIFT_R_CLI0_TSFT_ADJ_VAL_8822C 0
+#define BIT_MASK_R_CLI0_TSFT_ADJ_VAL_8822C 0xffff
+#define BIT_R_CLI0_TSFT_ADJ_VAL_8822C(x)                                       \
+	(((x) & BIT_MASK_R_CLI0_TSFT_ADJ_VAL_8822C)                            \
+	 << BIT_SHIFT_R_CLI0_TSFT_ADJ_VAL_8822C)
+#define BITS_R_CLI0_TSFT_ADJ_VAL_8822C                                         \
+	(BIT_MASK_R_CLI0_TSFT_ADJ_VAL_8822C                                    \
+	 << BIT_SHIFT_R_CLI0_TSFT_ADJ_VAL_8822C)
+#define BIT_CLEAR_R_CLI0_TSFT_ADJ_VAL_8822C(x)                                 \
+	((x) & (~BITS_R_CLI0_TSFT_ADJ_VAL_8822C))
+#define BIT_GET_R_CLI0_TSFT_ADJ_VAL_8822C(x)                                   \
+	(((x) >> BIT_SHIFT_R_CLI0_TSFT_ADJ_VAL_8822C) &                        \
+	 BIT_MASK_R_CLI0_TSFT_ADJ_VAL_8822C)
+#define BIT_SET_R_CLI0_TSFT_ADJ_VAL_8822C(x, v)                                \
+	(BIT_CLEAR_R_CLI0_TSFT_ADJ_VAL_8822C(x) |                              \
+	 BIT_R_CLI0_TSFT_ADJ_VAL_8822C(v))
+
+/* 2 REG_TSF_ADJ_VLAUE_2_8822C */
+
+#define BIT_SHIFT_R_CLI3_TSFT_ADJ_VAL_8822C 16
+#define BIT_MASK_R_CLI3_TSFT_ADJ_VAL_8822C 0xffff
+#define BIT_R_CLI3_TSFT_ADJ_VAL_8822C(x)                                       \
+	(((x) & BIT_MASK_R_CLI3_TSFT_ADJ_VAL_8822C)                            \
+	 << BIT_SHIFT_R_CLI3_TSFT_ADJ_VAL_8822C)
+#define BITS_R_CLI3_TSFT_ADJ_VAL_8822C                                         \
+	(BIT_MASK_R_CLI3_TSFT_ADJ_VAL_8822C                                    \
+	 << BIT_SHIFT_R_CLI3_TSFT_ADJ_VAL_8822C)
+#define BIT_CLEAR_R_CLI3_TSFT_ADJ_VAL_8822C(x)                                 \
+	((x) & (~BITS_R_CLI3_TSFT_ADJ_VAL_8822C))
+#define BIT_GET_R_CLI3_TSFT_ADJ_VAL_8822C(x)                                   \
+	(((x) >> BIT_SHIFT_R_CLI3_TSFT_ADJ_VAL_8822C) &                        \
+	 BIT_MASK_R_CLI3_TSFT_ADJ_VAL_8822C)
+#define BIT_SET_R_CLI3_TSFT_ADJ_VAL_8822C(x, v)                                \
+	(BIT_CLEAR_R_CLI3_TSFT_ADJ_VAL_8822C(x) |                              \
+	 BIT_R_CLI3_TSFT_ADJ_VAL_8822C(v))
+
+#define BIT_SHIFT_R_CLI2_TSFT_ADJ_VAL_8822C 0
+#define BIT_MASK_R_CLI2_TSFT_ADJ_VAL_8822C 0xffff
+#define BIT_R_CLI2_TSFT_ADJ_VAL_8822C(x)                                       \
+	(((x) & BIT_MASK_R_CLI2_TSFT_ADJ_VAL_8822C)                            \
+	 << BIT_SHIFT_R_CLI2_TSFT_ADJ_VAL_8822C)
+#define BITS_R_CLI2_TSFT_ADJ_VAL_8822C                                         \
+	(BIT_MASK_R_CLI2_TSFT_ADJ_VAL_8822C                                    \
+	 << BIT_SHIFT_R_CLI2_TSFT_ADJ_VAL_8822C)
+#define BIT_CLEAR_R_CLI2_TSFT_ADJ_VAL_8822C(x)                                 \
+	((x) & (~BITS_R_CLI2_TSFT_ADJ_VAL_8822C))
+#define BIT_GET_R_CLI2_TSFT_ADJ_VAL_8822C(x)                                   \
+	(((x) >> BIT_SHIFT_R_CLI2_TSFT_ADJ_VAL_8822C) &                        \
+	 BIT_MASK_R_CLI2_TSFT_ADJ_VAL_8822C)
+#define BIT_SET_R_CLI2_TSFT_ADJ_VAL_8822C(x, v)                                \
+	(BIT_CLEAR_R_CLI2_TSFT_ADJ_VAL_8822C(x) |                              \
+	 BIT_R_CLI2_TSFT_ADJ_VAL_8822C(v))
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_RSVD_8822C */
+
+/* 2 REG_RSVD_8822C */
+
+/* 2 REG_RSVD_8822C */
+
+/* 2 REG_RSVD_8822C */
+
+/* 2 REG_RSVD_8822C */
+
+/* 2 REG_RSVD_8822C */
+
+/* 2 REG_RSVD_8822C */
+
+/* 2 REG_RSVD_8822C */
+
+/* 2 REG_P2PPS_HW_AUTO_PAUSE_CTRL_8822C */
+#define BIT_P2PPS_NOA_STOP_TX_HANG_8822C BIT(31)
+#define BIT_P2PPS_MACID_PAUSE_EN_8822C BIT(11)
+#define BIT_P2PPS__MGQ_PAUSE_8822C BIT(10)
+#define BIT_P2PPS__HIQ_PAUSE_8822C BIT(9)
+#define BIT_P2PPS__BCNQ_PAUSE_8822C BIT(8)
+
+#define BIT_SHIFT_P2PPS_MACID_PAUSE_8822C 0
+#define BIT_MASK_P2PPS_MACID_PAUSE_8822C 0xff
+#define BIT_P2PPS_MACID_PAUSE_8822C(x)                                         \
+	(((x) & BIT_MASK_P2PPS_MACID_PAUSE_8822C)                              \
+	 << BIT_SHIFT_P2PPS_MACID_PAUSE_8822C)
+#define BITS_P2PPS_MACID_PAUSE_8822C                                           \
+	(BIT_MASK_P2PPS_MACID_PAUSE_8822C << BIT_SHIFT_P2PPS_MACID_PAUSE_8822C)
+#define BIT_CLEAR_P2PPS_MACID_PAUSE_8822C(x)                                   \
+	((x) & (~BITS_P2PPS_MACID_PAUSE_8822C))
+#define BIT_GET_P2PPS_MACID_PAUSE_8822C(x)                                     \
+	(((x) >> BIT_SHIFT_P2PPS_MACID_PAUSE_8822C) &                          \
+	 BIT_MASK_P2PPS_MACID_PAUSE_8822C)
+#define BIT_SET_P2PPS_MACID_PAUSE_8822C(x, v)                                  \
+	(BIT_CLEAR_P2PPS_MACID_PAUSE_8822C(x) | BIT_P2PPS_MACID_PAUSE_8822C(v))
+
+/* 2 REG_P2PPS1_HW_AUTO_PAUSE_CTRL_8822C */
+#define BIT_P2PPS1_NOA_STOP_TX_HANG_8822C BIT(31)
+#define BIT_P2PPS1_MACID_PAUSE_EN_8822C BIT(11)
+#define BIT_P2PPS1__MGQ_PAUSE_8822C BIT(10)
+#define BIT_P2PPS1__HIQ_PAUSE_8822C BIT(9)
+#define BIT_P2PPS1__BCNQ_PAUSE_8822C BIT(8)
+
+#define BIT_SHIFT_P2PPS1_MACID_PAUSE_8822C 0
+#define BIT_MASK_P2PPS1_MACID_PAUSE_8822C 0xff
+#define BIT_P2PPS1_MACID_PAUSE_8822C(x)                                        \
+	(((x) & BIT_MASK_P2PPS1_MACID_PAUSE_8822C)                             \
+	 << BIT_SHIFT_P2PPS1_MACID_PAUSE_8822C)
+#define BITS_P2PPS1_MACID_PAUSE_8822C                                          \
+	(BIT_MASK_P2PPS1_MACID_PAUSE_8822C                                     \
+	 << BIT_SHIFT_P2PPS1_MACID_PAUSE_8822C)
+#define BIT_CLEAR_P2PPS1_MACID_PAUSE_8822C(x)                                  \
+	((x) & (~BITS_P2PPS1_MACID_PAUSE_8822C))
+#define BIT_GET_P2PPS1_MACID_PAUSE_8822C(x)                                    \
+	(((x) >> BIT_SHIFT_P2PPS1_MACID_PAUSE_8822C) &                         \
+	 BIT_MASK_P2PPS1_MACID_PAUSE_8822C)
+#define BIT_SET_P2PPS1_MACID_PAUSE_8822C(x, v)                                 \
+	(BIT_CLEAR_P2PPS1_MACID_PAUSE_8822C(x) |                               \
+	 BIT_P2PPS1_MACID_PAUSE_8822C(v))
+
+/* 2 REG_P2PPS2_HW_AUTO_PAUSE_CTRL_8822C */
+#define BIT_P2PPS2_NOA_STOP_TX_HANG_8822C BIT(31)
+#define BIT_P2PPS2_MACID_PAUSE_EN_8822C BIT(11)
+#define BIT_P2PPS2__MGQ_PAUSE_8822C BIT(10)
+#define BIT_P2PPS2__HIQ_PAUSE_8822C BIT(9)
+#define BIT_P2PPS2__BCNQ_PAUSE_8822C BIT(8)
+
+#define BIT_SHIFT_P2PPS2_MACID_PAUSE_8822C 0
+#define BIT_MASK_P2PPS2_MACID_PAUSE_8822C 0xff
+#define BIT_P2PPS2_MACID_PAUSE_8822C(x)                                        \
+	(((x) & BIT_MASK_P2PPS2_MACID_PAUSE_8822C)                             \
+	 << BIT_SHIFT_P2PPS2_MACID_PAUSE_8822C)
+#define BITS_P2PPS2_MACID_PAUSE_8822C                                          \
+	(BIT_MASK_P2PPS2_MACID_PAUSE_8822C                                     \
+	 << BIT_SHIFT_P2PPS2_MACID_PAUSE_8822C)
+#define BIT_CLEAR_P2PPS2_MACID_PAUSE_8822C(x)                                  \
+	((x) & (~BITS_P2PPS2_MACID_PAUSE_8822C))
+#define BIT_GET_P2PPS2_MACID_PAUSE_8822C(x)                                    \
+	(((x) >> BIT_SHIFT_P2PPS2_MACID_PAUSE_8822C) &                         \
+	 BIT_MASK_P2PPS2_MACID_PAUSE_8822C)
+#define BIT_SET_P2PPS2_MACID_PAUSE_8822C(x, v)                                 \
+	(BIT_CLEAR_P2PPS2_MACID_PAUSE_8822C(x) |                               \
+	 BIT_P2PPS2_MACID_PAUSE_8822C(v))
+
+/* 2 REG_RSVD_8822C */
+
+/* 2 REG_RSVD_8822C */
+
+/* 2 REG_RSVD_8822C */
+
+/* 2 REG_RSVD_8822C */
+
+/* 2 REG_RSVD_8822C */
+
+/* 2 REG_RSVD_8822C */
+
+/* 2 REG_RSVD_8822C */
+
+/* 2 REG_RSVD_8822C */
+
+/* 2 REG_RSVD_8822C */
+
+/* 2 REG_RSVD_8822C */
+
+/* 2 REG_RSVD_8822C */
+
+/* 2 REG_RSVD_8822C */
+
+/* 2 REG_RSVD_8822C */
+
+/* 2 REG_RSVD_8822C */
+
+/* 2 REG_RSVD_8822C */
+
+/* 2 REG_RSVD_8822C */
+
+/* 2 REG_RSVD_8822C */
+
+/* 2 REG_RSVD_8822C */
+
+/* 2 REG_RSVD_8822C */
+
+/* 2 REG_RSVD_8822C */
+
+/* 2 REG_RSVD_8822C */
+
+/* 2 REG_RSVD_8822C */
+
+/* 2 REG_SCHEDULER_COUNTER_8822C */
+
+#define BIT_SHIFT__SCHEDULER_COUNTER_8822C 16
+#define BIT_MASK__SCHEDULER_COUNTER_8822C 0xffff
+#define BIT__SCHEDULER_COUNTER_8822C(x)                                        \
+	(((x) & BIT_MASK__SCHEDULER_COUNTER_8822C)                             \
+	 << BIT_SHIFT__SCHEDULER_COUNTER_8822C)
+#define BITS__SCHEDULER_COUNTER_8822C                                          \
+	(BIT_MASK__SCHEDULER_COUNTER_8822C                                     \
+	 << BIT_SHIFT__SCHEDULER_COUNTER_8822C)
+#define BIT_CLEAR__SCHEDULER_COUNTER_8822C(x)                                  \
+	((x) & (~BITS__SCHEDULER_COUNTER_8822C))
+#define BIT_GET__SCHEDULER_COUNTER_8822C(x)                                    \
+	(((x) >> BIT_SHIFT__SCHEDULER_COUNTER_8822C) &                         \
+	 BIT_MASK__SCHEDULER_COUNTER_8822C)
+#define BIT_SET__SCHEDULER_COUNTER_8822C(x, v)                                 \
+	(BIT_CLEAR__SCHEDULER_COUNTER_8822C(x) |                               \
+	 BIT__SCHEDULER_COUNTER_8822C(v))
+
+#define BIT__SCHEDULER_COUNTER_RST_8822C BIT(8)
+
+#define BIT_SHIFT_SCHEDULER_COUNTER_SEL_8822C 0
+#define BIT_MASK_SCHEDULER_COUNTER_SEL_8822C 0xff
+#define BIT_SCHEDULER_COUNTER_SEL_8822C(x)                                     \
+	(((x) & BIT_MASK_SCHEDULER_COUNTER_SEL_8822C)                          \
+	 << BIT_SHIFT_SCHEDULER_COUNTER_SEL_8822C)
+#define BITS_SCHEDULER_COUNTER_SEL_8822C                                       \
+	(BIT_MASK_SCHEDULER_COUNTER_SEL_8822C                                  \
+	 << BIT_SHIFT_SCHEDULER_COUNTER_SEL_8822C)
+#define BIT_CLEAR_SCHEDULER_COUNTER_SEL_8822C(x)                               \
+	((x) & (~BITS_SCHEDULER_COUNTER_SEL_8822C))
+#define BIT_GET_SCHEDULER_COUNTER_SEL_8822C(x)                                 \
+	(((x) >> BIT_SHIFT_SCHEDULER_COUNTER_SEL_8822C) &                      \
+	 BIT_MASK_SCHEDULER_COUNTER_SEL_8822C)
+#define BIT_SET_SCHEDULER_COUNTER_SEL_8822C(x, v)                              \
+	(BIT_CLEAR_SCHEDULER_COUNTER_SEL_8822C(x) |                            \
+	 BIT_SCHEDULER_COUNTER_SEL_8822C(v))
+
+/* 2 REG_RSVD_8822C */
+
+/* 2 REG_RSVD_8822C */
+
+/* 2 REG_RSVD_8822C */
+
+/* 2 REG_RSVD_8822C */
+
+/* 2 REG_RSVD_8822C */
+
+/* 2 REG_RSVD_8822C */
+
+/* 2 REG_RSVD_8822C */
+
+/* 2 REG_RSVD_8822C */
+
+/* 2 REG_RSVD_8822C */
+
+/* 2 REG_RSVD_8822C */
+
+/* 2 REG_RSVD_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_WMAC_CR_8822C (WMAC CR AND APSD CONTROL REGISTER) */
+#define BIT_IC_MACPHY_M_8822C BIT(0)
+
+/* 2 REG_WMAC_FWPKT_CR_8822C */
+#define BIT_FWEN_8822C BIT(7)
+#define BIT_PHYSTS_PKT_CTRL_8822C BIT(6)
+#define BIT_APPHDR_MIDSRCH_FAIL_8822C BIT(4)
+#define BIT_FWPARSING_EN_8822C BIT(3)
+
+#define BIT_SHIFT_APPEND_MHDR_LEN_8822C 0
+#define BIT_MASK_APPEND_MHDR_LEN_8822C 0x7
+#define BIT_APPEND_MHDR_LEN_8822C(x)                                           \
+	(((x) & BIT_MASK_APPEND_MHDR_LEN_8822C)                                \
+	 << BIT_SHIFT_APPEND_MHDR_LEN_8822C)
+#define BITS_APPEND_MHDR_LEN_8822C                                             \
+	(BIT_MASK_APPEND_MHDR_LEN_8822C << BIT_SHIFT_APPEND_MHDR_LEN_8822C)
+#define BIT_CLEAR_APPEND_MHDR_LEN_8822C(x) ((x) & (~BITS_APPEND_MHDR_LEN_8822C))
+#define BIT_GET_APPEND_MHDR_LEN_8822C(x)                                       \
+	(((x) >> BIT_SHIFT_APPEND_MHDR_LEN_8822C) &                            \
+	 BIT_MASK_APPEND_MHDR_LEN_8822C)
+#define BIT_SET_APPEND_MHDR_LEN_8822C(x, v)                                    \
+	(BIT_CLEAR_APPEND_MHDR_LEN_8822C(x) | BIT_APPEND_MHDR_LEN_8822C(v))
+
+/* 2 REG_FW_STS_FILTER_8822C */
+#define BIT_DATA_FW_STS_FILTER_8822C BIT(2)
+#define BIT_CTRL_FW_STS_FILTER_8822C BIT(1)
+#define BIT_MGNT_FW_STS_FILTER_8822C BIT(0)
+
+/* 2 REG_RSVD_8822C */
+
+/* 2 REG_TCR_8822C (TRANSMISSION CONFIGURATION REGISTER) */
+#define BIT_WMAC_EN_RTS_ADDR_8822C BIT(31)
+#define BIT_WMAC_DISABLE_CCK_8822C BIT(30)
+#define BIT_WMAC_RAW_LEN_8822C BIT(29)
+#define BIT_WMAC_NOTX_IN_RXNDP_8822C BIT(28)
+#define BIT_WMAC_EN_EOF_8822C BIT(27)
+#define BIT_WMAC_BF_SEL_8822C BIT(26)
+#define BIT_WMAC_ANTMODE_SEL_8822C BIT(25)
+#define BIT_WMAC_TCRPWRMGT_HWCTL_8822C BIT(24)
+#define BIT_WMAC_SMOOTH_VAL_8822C BIT(23)
+#define BIT_WMAC_EN_SCRAM_INC_8822C BIT(22)
+#define BIT_UNDERFLOWEN_CMPLEN_SEL_8822C BIT(21)
+#define BIT_FETCH_MPDU_AFTER_WSEC_RDY_8822C BIT(20)
+#define BIT_WMAC_TCR_EN_20MST_8822C BIT(19)
+#define BIT_WMAC_DIS_SIGTA_8822C BIT(18)
+#define BIT_WMAC_DIS_A2B0_8822C BIT(17)
+#define BIT_WMAC_MSK_SIGBCRC_8822C BIT(16)
+#define BIT_WMAC_TCR_ERRSTEN_3_8822C BIT(15)
+#define BIT_WMAC_TCR_ERRSTEN_2_8822C BIT(14)
+#define BIT_WMAC_TCR_ERRSTEN_1_8822C BIT(13)
+#define BIT_WMAC_TCR_ERRSTEN_0_8822C BIT(12)
+#define BIT_WMAC_TCR_TXSK_PERPKT_8822C BIT(11)
+#define BIT_ICV_8822C BIT(10)
+#define BIT_CFEND_FORMAT_8822C BIT(9)
+#define BIT_CRC_8822C BIT(8)
+#define BIT_WMAC_TCRPWRMGT_HWDATA_EN_8822C BIT(7)
+#define BIT_PWR_ST_8822C BIT(6)
+#define BIT_WMAC_TCR_UPD_TIMIE_8822C BIT(5)
+#define BIT_WMAC_TCR_UPD_HGQMD_8822C BIT(4)
+#define BIT_VHTSIGA1_TXPS_8822C BIT(3)
+#define BIT_PAD_SEL_8822C BIT(2)
+#define BIT_DIS_GCLK_8822C BIT(1)
+#define BIT_WMAC_TCRPWRMGT_HWACT_EN_8822C BIT(0)
+
+/* 2 REG_RCR_8822C (RECEIVE CONFIGURATION REGISTER) */
+#define BIT_APP_FCS_8822C BIT(31)
+#define BIT_APP_MIC_8822C BIT(30)
+#define BIT_APP_ICV_8822C BIT(29)
+#define BIT_APP_PHYSTS_8822C BIT(28)
+#define BIT_APP_BASSN_8822C BIT(27)
+#define BIT_VHT_DACK_8822C BIT(26)
+#define BIT_TCPOFLD_EN_8822C BIT(25)
+#define BIT_ENMBID_8822C BIT(24)
+#define BIT_LSIGEN_8822C BIT(23)
+#define BIT_MFBEN_8822C BIT(22)
+#define BIT_DISCHKPPDLLEN_8822C BIT(21)
+#define BIT_PKTCTL_DLEN_8822C BIT(20)
+#define BIT_DISGCLK_8822C BIT(19)
+#define BIT_TIM_PARSER_EN_8822C BIT(18)
+#define BIT_BC_MD_EN_8822C BIT(17)
+#define BIT_UC_MD_EN_8822C BIT(16)
+#define BIT_RXSK_PERPKT_8822C BIT(15)
+#define BIT_HTC_LOC_CTRL_8822C BIT(14)
+#define BIT_ACK_WITH_CBSSID_DATA_OPTION_8822C BIT(13)
+#define BIT_RPFM_CAM_ENABLE_8822C BIT(12)
+#define BIT_TA_BCN_8822C BIT(11)
+#define BIT_DISDECMYPKT_8822C BIT(10)
+#define BIT_AICV_8822C BIT(9)
+#define BIT_ACRC32_8822C BIT(8)
+#define BIT_CBSSID_BCN_8822C BIT(7)
+#define BIT_CBSSID_DATA_8822C BIT(6)
+#define BIT_APWRMGT_8822C BIT(5)
+#define BIT_ADD3_8822C BIT(4)
+#define BIT_AB_8822C BIT(3)
+#define BIT_AM_8822C BIT(2)
+#define BIT_APM_8822C BIT(1)
+#define BIT_AAP_8822C BIT(0)
+
+/* 2 REG_RX_PKT_LIMIT_8822C (RX PACKET LENGTH LIMIT REGISTER) */
+
+#define BIT_SHIFT_RXPKTLMT_8822C 0
+#define BIT_MASK_RXPKTLMT_8822C 0x3f
+#define BIT_RXPKTLMT_8822C(x)                                                  \
+	(((x) & BIT_MASK_RXPKTLMT_8822C) << BIT_SHIFT_RXPKTLMT_8822C)
+#define BITS_RXPKTLMT_8822C                                                    \
+	(BIT_MASK_RXPKTLMT_8822C << BIT_SHIFT_RXPKTLMT_8822C)
+#define BIT_CLEAR_RXPKTLMT_8822C(x) ((x) & (~BITS_RXPKTLMT_8822C))
+#define BIT_GET_RXPKTLMT_8822C(x)                                              \
+	(((x) >> BIT_SHIFT_RXPKTLMT_8822C) & BIT_MASK_RXPKTLMT_8822C)
+#define BIT_SET_RXPKTLMT_8822C(x, v)                                           \
+	(BIT_CLEAR_RXPKTLMT_8822C(x) | BIT_RXPKTLMT_8822C(v))
+
+/* 2 REG_RX_DLK_TIME_8822C (RX DEADLOCK TIME REGISTER) */
+
+#define BIT_SHIFT_RX_DLK_TIME_8822C 0
+#define BIT_MASK_RX_DLK_TIME_8822C 0xff
+#define BIT_RX_DLK_TIME_8822C(x)                                               \
+	(((x) & BIT_MASK_RX_DLK_TIME_8822C) << BIT_SHIFT_RX_DLK_TIME_8822C)
+#define BITS_RX_DLK_TIME_8822C                                                 \
+	(BIT_MASK_RX_DLK_TIME_8822C << BIT_SHIFT_RX_DLK_TIME_8822C)
+#define BIT_CLEAR_RX_DLK_TIME_8822C(x) ((x) & (~BITS_RX_DLK_TIME_8822C))
+#define BIT_GET_RX_DLK_TIME_8822C(x)                                           \
+	(((x) >> BIT_SHIFT_RX_DLK_TIME_8822C) & BIT_MASK_RX_DLK_TIME_8822C)
+#define BIT_SET_RX_DLK_TIME_8822C(x, v)                                        \
+	(BIT_CLEAR_RX_DLK_TIME_8822C(x) | BIT_RX_DLK_TIME_8822C(v))
+
+/* 2 REG_RSVD_8822C */
+
+/* 2 REG_RX_DRVINFO_SZ_8822C (RX DRIVER INFO SIZE REGISTER) */
+#define BIT_PHYSTS_PER_PKT_MODE_8822C BIT(7)
+
+#define BIT_SHIFT_DRVINFO_SZ_V1_8822C 0
+#define BIT_MASK_DRVINFO_SZ_V1_8822C 0xf
+#define BIT_DRVINFO_SZ_V1_8822C(x)                                             \
+	(((x) & BIT_MASK_DRVINFO_SZ_V1_8822C) << BIT_SHIFT_DRVINFO_SZ_V1_8822C)
+#define BITS_DRVINFO_SZ_V1_8822C                                               \
+	(BIT_MASK_DRVINFO_SZ_V1_8822C << BIT_SHIFT_DRVINFO_SZ_V1_8822C)
+#define BIT_CLEAR_DRVINFO_SZ_V1_8822C(x) ((x) & (~BITS_DRVINFO_SZ_V1_8822C))
+#define BIT_GET_DRVINFO_SZ_V1_8822C(x)                                         \
+	(((x) >> BIT_SHIFT_DRVINFO_SZ_V1_8822C) & BIT_MASK_DRVINFO_SZ_V1_8822C)
+#define BIT_SET_DRVINFO_SZ_V1_8822C(x, v)                                      \
+	(BIT_CLEAR_DRVINFO_SZ_V1_8822C(x) | BIT_DRVINFO_SZ_V1_8822C(v))
+
+/* 2 REG_MACID_8822C	(MAC ID REGISTER) */
+
+#define BIT_SHIFT_MACID_V1_8822C 0
+#define BIT_MASK_MACID_V1_8822C 0xffffffffL
+#define BIT_MACID_V1_8822C(x)                                                  \
+	(((x) & BIT_MASK_MACID_V1_8822C) << BIT_SHIFT_MACID_V1_8822C)
+#define BITS_MACID_V1_8822C                                                    \
+	(BIT_MASK_MACID_V1_8822C << BIT_SHIFT_MACID_V1_8822C)
+#define BIT_CLEAR_MACID_V1_8822C(x) ((x) & (~BITS_MACID_V1_8822C))
+#define BIT_GET_MACID_V1_8822C(x)                                              \
+	(((x) >> BIT_SHIFT_MACID_V1_8822C) & BIT_MASK_MACID_V1_8822C)
+#define BIT_SET_MACID_V1_8822C(x, v)                                           \
+	(BIT_CLEAR_MACID_V1_8822C(x) | BIT_MACID_V1_8822C(v))
+
+/* 2 REG_MACID_H_8822C	(MAC ID REGISTER) */
+
+#define BIT_SHIFT_MACID_H_V1_8822C 0
+#define BIT_MASK_MACID_H_V1_8822C 0xffff
+#define BIT_MACID_H_V1_8822C(x)                                                \
+	(((x) & BIT_MASK_MACID_H_V1_8822C) << BIT_SHIFT_MACID_H_V1_8822C)
+#define BITS_MACID_H_V1_8822C                                                  \
+	(BIT_MASK_MACID_H_V1_8822C << BIT_SHIFT_MACID_H_V1_8822C)
+#define BIT_CLEAR_MACID_H_V1_8822C(x) ((x) & (~BITS_MACID_H_V1_8822C))
+#define BIT_GET_MACID_H_V1_8822C(x)                                            \
+	(((x) >> BIT_SHIFT_MACID_H_V1_8822C) & BIT_MASK_MACID_H_V1_8822C)
+#define BIT_SET_MACID_H_V1_8822C(x, v)                                         \
+	(BIT_CLEAR_MACID_H_V1_8822C(x) | BIT_MACID_H_V1_8822C(v))
+
+/* 2 REG_BSSID_8822C (BSSID REGISTER) */
+
+#define BIT_SHIFT_BSSID_V1_8822C 0
+#define BIT_MASK_BSSID_V1_8822C 0xffffffffL
+#define BIT_BSSID_V1_8822C(x)                                                  \
+	(((x) & BIT_MASK_BSSID_V1_8822C) << BIT_SHIFT_BSSID_V1_8822C)
+#define BITS_BSSID_V1_8822C                                                    \
+	(BIT_MASK_BSSID_V1_8822C << BIT_SHIFT_BSSID_V1_8822C)
+#define BIT_CLEAR_BSSID_V1_8822C(x) ((x) & (~BITS_BSSID_V1_8822C))
+#define BIT_GET_BSSID_V1_8822C(x)                                              \
+	(((x) >> BIT_SHIFT_BSSID_V1_8822C) & BIT_MASK_BSSID_V1_8822C)
+#define BIT_SET_BSSID_V1_8822C(x, v)                                           \
+	(BIT_CLEAR_BSSID_V1_8822C(x) | BIT_BSSID_V1_8822C(v))
+
+/* 2 REG_BSSID_H_8822C	(BSSID REGISTER) */
+
+/* 2 REG_NOT_VALID_8822C */
+
+#define BIT_SHIFT_BSSID_H_V1_8822C 0
+#define BIT_MASK_BSSID_H_V1_8822C 0xffff
+#define BIT_BSSID_H_V1_8822C(x)                                                \
+	(((x) & BIT_MASK_BSSID_H_V1_8822C) << BIT_SHIFT_BSSID_H_V1_8822C)
+#define BITS_BSSID_H_V1_8822C                                                  \
+	(BIT_MASK_BSSID_H_V1_8822C << BIT_SHIFT_BSSID_H_V1_8822C)
+#define BIT_CLEAR_BSSID_H_V1_8822C(x) ((x) & (~BITS_BSSID_H_V1_8822C))
+#define BIT_GET_BSSID_H_V1_8822C(x)                                            \
+	(((x) >> BIT_SHIFT_BSSID_H_V1_8822C) & BIT_MASK_BSSID_H_V1_8822C)
+#define BIT_SET_BSSID_H_V1_8822C(x, v)                                         \
+	(BIT_CLEAR_BSSID_H_V1_8822C(x) | BIT_BSSID_H_V1_8822C(v))
+
+/* 2 REG_MAR_8822C (MULTICAST ADDRESS REGISTER) */
+
+#define BIT_SHIFT_MAR_V1_8822C 0
+#define BIT_MASK_MAR_V1_8822C 0xffffffffL
+#define BIT_MAR_V1_8822C(x)                                                    \
+	(((x) & BIT_MASK_MAR_V1_8822C) << BIT_SHIFT_MAR_V1_8822C)
+#define BITS_MAR_V1_8822C (BIT_MASK_MAR_V1_8822C << BIT_SHIFT_MAR_V1_8822C)
+#define BIT_CLEAR_MAR_V1_8822C(x) ((x) & (~BITS_MAR_V1_8822C))
+#define BIT_GET_MAR_V1_8822C(x)                                                \
+	(((x) >> BIT_SHIFT_MAR_V1_8822C) & BIT_MASK_MAR_V1_8822C)
+#define BIT_SET_MAR_V1_8822C(x, v)                                             \
+	(BIT_CLEAR_MAR_V1_8822C(x) | BIT_MAR_V1_8822C(v))
+
+/* 2 REG_MAR_H_8822C (MULTICAST ADDRESS REGISTER) */
+
+#define BIT_SHIFT_MAR_H_V1_8822C 0
+#define BIT_MASK_MAR_H_V1_8822C 0xffffffffL
+#define BIT_MAR_H_V1_8822C(x)                                                  \
+	(((x) & BIT_MASK_MAR_H_V1_8822C) << BIT_SHIFT_MAR_H_V1_8822C)
+#define BITS_MAR_H_V1_8822C                                                    \
+	(BIT_MASK_MAR_H_V1_8822C << BIT_SHIFT_MAR_H_V1_8822C)
+#define BIT_CLEAR_MAR_H_V1_8822C(x) ((x) & (~BITS_MAR_H_V1_8822C))
+#define BIT_GET_MAR_H_V1_8822C(x)                                              \
+	(((x) >> BIT_SHIFT_MAR_H_V1_8822C) & BIT_MASK_MAR_H_V1_8822C)
+#define BIT_SET_MAR_H_V1_8822C(x, v)                                           \
+	(BIT_CLEAR_MAR_H_V1_8822C(x) | BIT_MAR_H_V1_8822C(v))
+
+/* 2 REG_MBIDCAMCFG_1_8822C (MBSSID CAM CONFIGURATION REGISTER) */
+
+#define BIT_SHIFT_MBIDCAM_RWDATA_L_8822C 0
+#define BIT_MASK_MBIDCAM_RWDATA_L_8822C 0xffffffffL
+#define BIT_MBIDCAM_RWDATA_L_8822C(x)                                          \
+	(((x) & BIT_MASK_MBIDCAM_RWDATA_L_8822C)                               \
+	 << BIT_SHIFT_MBIDCAM_RWDATA_L_8822C)
+#define BITS_MBIDCAM_RWDATA_L_8822C                                            \
+	(BIT_MASK_MBIDCAM_RWDATA_L_8822C << BIT_SHIFT_MBIDCAM_RWDATA_L_8822C)
+#define BIT_CLEAR_MBIDCAM_RWDATA_L_8822C(x)                                    \
+	((x) & (~BITS_MBIDCAM_RWDATA_L_8822C))
+#define BIT_GET_MBIDCAM_RWDATA_L_8822C(x)                                      \
+	(((x) >> BIT_SHIFT_MBIDCAM_RWDATA_L_8822C) &                           \
+	 BIT_MASK_MBIDCAM_RWDATA_L_8822C)
+#define BIT_SET_MBIDCAM_RWDATA_L_8822C(x, v)                                   \
+	(BIT_CLEAR_MBIDCAM_RWDATA_L_8822C(x) | BIT_MBIDCAM_RWDATA_L_8822C(v))
+
+/* 2 REG_MBIDCAMCFG_2_8822C (MBSSID CAM CONFIGURATION REGISTER) */
+#define BIT_MBIDCAM_POLL_8822C BIT(31)
+#define BIT_MBIDCAM_WT_EN_8822C BIT(30)
+
+#define BIT_SHIFT_MBIDCAM_ADDR_V1_8822C 24
+#define BIT_MASK_MBIDCAM_ADDR_V1_8822C 0x3f
+#define BIT_MBIDCAM_ADDR_V1_8822C(x)                                           \
+	(((x) & BIT_MASK_MBIDCAM_ADDR_V1_8822C)                                \
+	 << BIT_SHIFT_MBIDCAM_ADDR_V1_8822C)
+#define BITS_MBIDCAM_ADDR_V1_8822C                                             \
+	(BIT_MASK_MBIDCAM_ADDR_V1_8822C << BIT_SHIFT_MBIDCAM_ADDR_V1_8822C)
+#define BIT_CLEAR_MBIDCAM_ADDR_V1_8822C(x) ((x) & (~BITS_MBIDCAM_ADDR_V1_8822C))
+#define BIT_GET_MBIDCAM_ADDR_V1_8822C(x)                                       \
+	(((x) >> BIT_SHIFT_MBIDCAM_ADDR_V1_8822C) &                            \
+	 BIT_MASK_MBIDCAM_ADDR_V1_8822C)
+#define BIT_SET_MBIDCAM_ADDR_V1_8822C(x, v)                                    \
+	(BIT_CLEAR_MBIDCAM_ADDR_V1_8822C(x) | BIT_MBIDCAM_ADDR_V1_8822C(v))
+
+#define BIT_MBIDCAM_VALID_8822C BIT(23)
+#define BIT_LSIC_TXOP_EN_8822C BIT(17)
+#define BIT_CTS_EN_8822C BIT(16)
+
+#define BIT_SHIFT_MBIDCAM_RWDATA_H_8822C 0
+#define BIT_MASK_MBIDCAM_RWDATA_H_8822C 0xffff
+#define BIT_MBIDCAM_RWDATA_H_8822C(x)                                          \
+	(((x) & BIT_MASK_MBIDCAM_RWDATA_H_8822C)                               \
+	 << BIT_SHIFT_MBIDCAM_RWDATA_H_8822C)
+#define BITS_MBIDCAM_RWDATA_H_8822C                                            \
+	(BIT_MASK_MBIDCAM_RWDATA_H_8822C << BIT_SHIFT_MBIDCAM_RWDATA_H_8822C)
+#define BIT_CLEAR_MBIDCAM_RWDATA_H_8822C(x)                                    \
+	((x) & (~BITS_MBIDCAM_RWDATA_H_8822C))
+#define BIT_GET_MBIDCAM_RWDATA_H_8822C(x)                                      \
+	(((x) >> BIT_SHIFT_MBIDCAM_RWDATA_H_8822C) &                           \
+	 BIT_MASK_MBIDCAM_RWDATA_H_8822C)
+#define BIT_SET_MBIDCAM_RWDATA_H_8822C(x, v)                                   \
+	(BIT_CLEAR_MBIDCAM_RWDATA_H_8822C(x) | BIT_MBIDCAM_RWDATA_H_8822C(v))
+
+/* 2 REG_WMAC_TCR_TSFT_OFS_8822C */
+
+#define BIT_SHIFT_WMAC_TCR_TSFT_OFS_8822C 0
+#define BIT_MASK_WMAC_TCR_TSFT_OFS_8822C 0xffff
+#define BIT_WMAC_TCR_TSFT_OFS_8822C(x)                                         \
+	(((x) & BIT_MASK_WMAC_TCR_TSFT_OFS_8822C)                              \
+	 << BIT_SHIFT_WMAC_TCR_TSFT_OFS_8822C)
+#define BITS_WMAC_TCR_TSFT_OFS_8822C                                           \
+	(BIT_MASK_WMAC_TCR_TSFT_OFS_8822C << BIT_SHIFT_WMAC_TCR_TSFT_OFS_8822C)
+#define BIT_CLEAR_WMAC_TCR_TSFT_OFS_8822C(x)                                   \
+	((x) & (~BITS_WMAC_TCR_TSFT_OFS_8822C))
+#define BIT_GET_WMAC_TCR_TSFT_OFS_8822C(x)                                     \
+	(((x) >> BIT_SHIFT_WMAC_TCR_TSFT_OFS_8822C) &                          \
+	 BIT_MASK_WMAC_TCR_TSFT_OFS_8822C)
+#define BIT_SET_WMAC_TCR_TSFT_OFS_8822C(x, v)                                  \
+	(BIT_CLEAR_WMAC_TCR_TSFT_OFS_8822C(x) | BIT_WMAC_TCR_TSFT_OFS_8822C(v))
+
+/* 2 REG_UDF_THSD_8822C */
+#define BIT_UDF_THSD_V1_8822C BIT(7)
+
+#define BIT_SHIFT_UDF_THSD_VALUE_8822C 0
+#define BIT_MASK_UDF_THSD_VALUE_8822C 0x7f
+#define BIT_UDF_THSD_VALUE_8822C(x)                                            \
+	(((x) & BIT_MASK_UDF_THSD_VALUE_8822C)                                 \
+	 << BIT_SHIFT_UDF_THSD_VALUE_8822C)
+#define BITS_UDF_THSD_VALUE_8822C                                              \
+	(BIT_MASK_UDF_THSD_VALUE_8822C << BIT_SHIFT_UDF_THSD_VALUE_8822C)
+#define BIT_CLEAR_UDF_THSD_VALUE_8822C(x) ((x) & (~BITS_UDF_THSD_VALUE_8822C))
+#define BIT_GET_UDF_THSD_VALUE_8822C(x)                                        \
+	(((x) >> BIT_SHIFT_UDF_THSD_VALUE_8822C) &                             \
+	 BIT_MASK_UDF_THSD_VALUE_8822C)
+#define BIT_SET_UDF_THSD_VALUE_8822C(x, v)                                     \
+	(BIT_CLEAR_UDF_THSD_VALUE_8822C(x) | BIT_UDF_THSD_VALUE_8822C(v))
+
+/* 2 REG_ZLD_NUM_8822C */
+
+#define BIT_SHIFT_ZLD_NUM_8822C 0
+#define BIT_MASK_ZLD_NUM_8822C 0xff
+#define BIT_ZLD_NUM_8822C(x)                                                   \
+	(((x) & BIT_MASK_ZLD_NUM_8822C) << BIT_SHIFT_ZLD_NUM_8822C)
+#define BITS_ZLD_NUM_8822C (BIT_MASK_ZLD_NUM_8822C << BIT_SHIFT_ZLD_NUM_8822C)
+#define BIT_CLEAR_ZLD_NUM_8822C(x) ((x) & (~BITS_ZLD_NUM_8822C))
+#define BIT_GET_ZLD_NUM_8822C(x)                                               \
+	(((x) >> BIT_SHIFT_ZLD_NUM_8822C) & BIT_MASK_ZLD_NUM_8822C)
+#define BIT_SET_ZLD_NUM_8822C(x, v)                                            \
+	(BIT_CLEAR_ZLD_NUM_8822C(x) | BIT_ZLD_NUM_8822C(v))
+
+/* 2 REG_STMP_THSD_8822C */
+
+#define BIT_SHIFT_STMP_THSD_8822C 0
+#define BIT_MASK_STMP_THSD_8822C 0xff
+#define BIT_STMP_THSD_8822C(x)                                                 \
+	(((x) & BIT_MASK_STMP_THSD_8822C) << BIT_SHIFT_STMP_THSD_8822C)
+#define BITS_STMP_THSD_8822C                                                   \
+	(BIT_MASK_STMP_THSD_8822C << BIT_SHIFT_STMP_THSD_8822C)
+#define BIT_CLEAR_STMP_THSD_8822C(x) ((x) & (~BITS_STMP_THSD_8822C))
+#define BIT_GET_STMP_THSD_8822C(x)                                             \
+	(((x) >> BIT_SHIFT_STMP_THSD_8822C) & BIT_MASK_STMP_THSD_8822C)
+#define BIT_SET_STMP_THSD_8822C(x, v)                                          \
+	(BIT_CLEAR_STMP_THSD_8822C(x) | BIT_STMP_THSD_8822C(v))
+
+/* 2 REG_WMAC_TXTIMEOUT_8822C */
+
+#define BIT_SHIFT_WMAC_TXTIMEOUT_8822C 0
+#define BIT_MASK_WMAC_TXTIMEOUT_8822C 0xff
+#define BIT_WMAC_TXTIMEOUT_8822C(x)                                            \
+	(((x) & BIT_MASK_WMAC_TXTIMEOUT_8822C)                                 \
+	 << BIT_SHIFT_WMAC_TXTIMEOUT_8822C)
+#define BITS_WMAC_TXTIMEOUT_8822C                                              \
+	(BIT_MASK_WMAC_TXTIMEOUT_8822C << BIT_SHIFT_WMAC_TXTIMEOUT_8822C)
+#define BIT_CLEAR_WMAC_TXTIMEOUT_8822C(x) ((x) & (~BITS_WMAC_TXTIMEOUT_8822C))
+#define BIT_GET_WMAC_TXTIMEOUT_8822C(x)                                        \
+	(((x) >> BIT_SHIFT_WMAC_TXTIMEOUT_8822C) &                             \
+	 BIT_MASK_WMAC_TXTIMEOUT_8822C)
+#define BIT_SET_WMAC_TXTIMEOUT_8822C(x, v)                                     \
+	(BIT_CLEAR_WMAC_TXTIMEOUT_8822C(x) | BIT_WMAC_TXTIMEOUT_8822C(v))
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_USTIME_EDCA_8822C (US TIME TUNING FOR EDCA REGISTER) */
+
+#define BIT_SHIFT_USTIME_EDCA_8822C 0
+#define BIT_MASK_USTIME_EDCA_8822C 0xff
+#define BIT_USTIME_EDCA_8822C(x)                                               \
+	(((x) & BIT_MASK_USTIME_EDCA_8822C) << BIT_SHIFT_USTIME_EDCA_8822C)
+#define BITS_USTIME_EDCA_8822C                                                 \
+	(BIT_MASK_USTIME_EDCA_8822C << BIT_SHIFT_USTIME_EDCA_8822C)
+#define BIT_CLEAR_USTIME_EDCA_8822C(x) ((x) & (~BITS_USTIME_EDCA_8822C))
+#define BIT_GET_USTIME_EDCA_8822C(x)                                           \
+	(((x) >> BIT_SHIFT_USTIME_EDCA_8822C) & BIT_MASK_USTIME_EDCA_8822C)
+#define BIT_SET_USTIME_EDCA_8822C(x, v)                                        \
+	(BIT_CLEAR_USTIME_EDCA_8822C(x) | BIT_USTIME_EDCA_8822C(v))
+
+/* 2 REG_ACKTO_CCK_8822C (ACK TIMEOUT REGISTER FOR CCK RATE) */
+
+#define BIT_SHIFT_ACKTO_CCK_8822C 0
+#define BIT_MASK_ACKTO_CCK_8822C 0xff
+#define BIT_ACKTO_CCK_8822C(x)                                                 \
+	(((x) & BIT_MASK_ACKTO_CCK_8822C) << BIT_SHIFT_ACKTO_CCK_8822C)
+#define BITS_ACKTO_CCK_8822C                                                   \
+	(BIT_MASK_ACKTO_CCK_8822C << BIT_SHIFT_ACKTO_CCK_8822C)
+#define BIT_CLEAR_ACKTO_CCK_8822C(x) ((x) & (~BITS_ACKTO_CCK_8822C))
+#define BIT_GET_ACKTO_CCK_8822C(x)                                             \
+	(((x) >> BIT_SHIFT_ACKTO_CCK_8822C) & BIT_MASK_ACKTO_CCK_8822C)
+#define BIT_SET_ACKTO_CCK_8822C(x, v)                                          \
+	(BIT_CLEAR_ACKTO_CCK_8822C(x) | BIT_ACKTO_CCK_8822C(v))
+
+/* 2 REG_MAC_SPEC_SIFS_8822C (SPECIFICATION SIFS REGISTER) */
+
+#define BIT_SHIFT_SPEC_SIFS_OFDM_8822C 8
+#define BIT_MASK_SPEC_SIFS_OFDM_8822C 0xff
+#define BIT_SPEC_SIFS_OFDM_8822C(x)                                            \
+	(((x) & BIT_MASK_SPEC_SIFS_OFDM_8822C)                                 \
+	 << BIT_SHIFT_SPEC_SIFS_OFDM_8822C)
+#define BITS_SPEC_SIFS_OFDM_8822C                                              \
+	(BIT_MASK_SPEC_SIFS_OFDM_8822C << BIT_SHIFT_SPEC_SIFS_OFDM_8822C)
+#define BIT_CLEAR_SPEC_SIFS_OFDM_8822C(x) ((x) & (~BITS_SPEC_SIFS_OFDM_8822C))
+#define BIT_GET_SPEC_SIFS_OFDM_8822C(x)                                        \
+	(((x) >> BIT_SHIFT_SPEC_SIFS_OFDM_8822C) &                             \
+	 BIT_MASK_SPEC_SIFS_OFDM_8822C)
+#define BIT_SET_SPEC_SIFS_OFDM_8822C(x, v)                                     \
+	(BIT_CLEAR_SPEC_SIFS_OFDM_8822C(x) | BIT_SPEC_SIFS_OFDM_8822C(v))
+
+#define BIT_SHIFT_SPEC_SIFS_CCK_8822C 0
+#define BIT_MASK_SPEC_SIFS_CCK_8822C 0xff
+#define BIT_SPEC_SIFS_CCK_8822C(x)                                             \
+	(((x) & BIT_MASK_SPEC_SIFS_CCK_8822C) << BIT_SHIFT_SPEC_SIFS_CCK_8822C)
+#define BITS_SPEC_SIFS_CCK_8822C                                               \
+	(BIT_MASK_SPEC_SIFS_CCK_8822C << BIT_SHIFT_SPEC_SIFS_CCK_8822C)
+#define BIT_CLEAR_SPEC_SIFS_CCK_8822C(x) ((x) & (~BITS_SPEC_SIFS_CCK_8822C))
+#define BIT_GET_SPEC_SIFS_CCK_8822C(x)                                         \
+	(((x) >> BIT_SHIFT_SPEC_SIFS_CCK_8822C) & BIT_MASK_SPEC_SIFS_CCK_8822C)
+#define BIT_SET_SPEC_SIFS_CCK_8822C(x, v)                                      \
+	(BIT_CLEAR_SPEC_SIFS_CCK_8822C(x) | BIT_SPEC_SIFS_CCK_8822C(v))
+
+/* 2 REG_RESP_SIFS_CCK_8822C (RESPONSE SIFS FOR CCK REGISTER) */
+
+#define BIT_SHIFT_SIFS_R2T_CCK_8822C 8
+#define BIT_MASK_SIFS_R2T_CCK_8822C 0xff
+#define BIT_SIFS_R2T_CCK_8822C(x)                                              \
+	(((x) & BIT_MASK_SIFS_R2T_CCK_8822C) << BIT_SHIFT_SIFS_R2T_CCK_8822C)
+#define BITS_SIFS_R2T_CCK_8822C                                                \
+	(BIT_MASK_SIFS_R2T_CCK_8822C << BIT_SHIFT_SIFS_R2T_CCK_8822C)
+#define BIT_CLEAR_SIFS_R2T_CCK_8822C(x) ((x) & (~BITS_SIFS_R2T_CCK_8822C))
+#define BIT_GET_SIFS_R2T_CCK_8822C(x)                                          \
+	(((x) >> BIT_SHIFT_SIFS_R2T_CCK_8822C) & BIT_MASK_SIFS_R2T_CCK_8822C)
+#define BIT_SET_SIFS_R2T_CCK_8822C(x, v)                                       \
+	(BIT_CLEAR_SIFS_R2T_CCK_8822C(x) | BIT_SIFS_R2T_CCK_8822C(v))
+
+#define BIT_SHIFT_SIFS_T2T_CCK_8822C 0
+#define BIT_MASK_SIFS_T2T_CCK_8822C 0xff
+#define BIT_SIFS_T2T_CCK_8822C(x)                                              \
+	(((x) & BIT_MASK_SIFS_T2T_CCK_8822C) << BIT_SHIFT_SIFS_T2T_CCK_8822C)
+#define BITS_SIFS_T2T_CCK_8822C                                                \
+	(BIT_MASK_SIFS_T2T_CCK_8822C << BIT_SHIFT_SIFS_T2T_CCK_8822C)
+#define BIT_CLEAR_SIFS_T2T_CCK_8822C(x) ((x) & (~BITS_SIFS_T2T_CCK_8822C))
+#define BIT_GET_SIFS_T2T_CCK_8822C(x)                                          \
+	(((x) >> BIT_SHIFT_SIFS_T2T_CCK_8822C) & BIT_MASK_SIFS_T2T_CCK_8822C)
+#define BIT_SET_SIFS_T2T_CCK_8822C(x, v)                                       \
+	(BIT_CLEAR_SIFS_T2T_CCK_8822C(x) | BIT_SIFS_T2T_CCK_8822C(v))
+
+/* 2 REG_RESP_SIFS_OFDM_8822C (RESPONSE SIFS FOR OFDM REGISTER) */
+
+#define BIT_SHIFT_SIFS_R2T_OFDM_8822C 8
+#define BIT_MASK_SIFS_R2T_OFDM_8822C 0xff
+#define BIT_SIFS_R2T_OFDM_8822C(x)                                             \
+	(((x) & BIT_MASK_SIFS_R2T_OFDM_8822C) << BIT_SHIFT_SIFS_R2T_OFDM_8822C)
+#define BITS_SIFS_R2T_OFDM_8822C                                               \
+	(BIT_MASK_SIFS_R2T_OFDM_8822C << BIT_SHIFT_SIFS_R2T_OFDM_8822C)
+#define BIT_CLEAR_SIFS_R2T_OFDM_8822C(x) ((x) & (~BITS_SIFS_R2T_OFDM_8822C))
+#define BIT_GET_SIFS_R2T_OFDM_8822C(x)                                         \
+	(((x) >> BIT_SHIFT_SIFS_R2T_OFDM_8822C) & BIT_MASK_SIFS_R2T_OFDM_8822C)
+#define BIT_SET_SIFS_R2T_OFDM_8822C(x, v)                                      \
+	(BIT_CLEAR_SIFS_R2T_OFDM_8822C(x) | BIT_SIFS_R2T_OFDM_8822C(v))
+
+#define BIT_SHIFT_SIFS_T2T_OFDM_8822C 0
+#define BIT_MASK_SIFS_T2T_OFDM_8822C 0xff
+#define BIT_SIFS_T2T_OFDM_8822C(x)                                             \
+	(((x) & BIT_MASK_SIFS_T2T_OFDM_8822C) << BIT_SHIFT_SIFS_T2T_OFDM_8822C)
+#define BITS_SIFS_T2T_OFDM_8822C                                               \
+	(BIT_MASK_SIFS_T2T_OFDM_8822C << BIT_SHIFT_SIFS_T2T_OFDM_8822C)
+#define BIT_CLEAR_SIFS_T2T_OFDM_8822C(x) ((x) & (~BITS_SIFS_T2T_OFDM_8822C))
+#define BIT_GET_SIFS_T2T_OFDM_8822C(x)                                         \
+	(((x) >> BIT_SHIFT_SIFS_T2T_OFDM_8822C) & BIT_MASK_SIFS_T2T_OFDM_8822C)
+#define BIT_SET_SIFS_T2T_OFDM_8822C(x, v)                                      \
+	(BIT_CLEAR_SIFS_T2T_OFDM_8822C(x) | BIT_SIFS_T2T_OFDM_8822C(v))
+
+/* 2 REG_ACKTO_8822C (ACK TIMEOUT REGISTER) */
+
+#define BIT_SHIFT_ACKTO_8822C 0
+#define BIT_MASK_ACKTO_8822C 0xff
+#define BIT_ACKTO_8822C(x)                                                     \
+	(((x) & BIT_MASK_ACKTO_8822C) << BIT_SHIFT_ACKTO_8822C)
+#define BITS_ACKTO_8822C (BIT_MASK_ACKTO_8822C << BIT_SHIFT_ACKTO_8822C)
+#define BIT_CLEAR_ACKTO_8822C(x) ((x) & (~BITS_ACKTO_8822C))
+#define BIT_GET_ACKTO_8822C(x)                                                 \
+	(((x) >> BIT_SHIFT_ACKTO_8822C) & BIT_MASK_ACKTO_8822C)
+#define BIT_SET_ACKTO_8822C(x, v)                                              \
+	(BIT_CLEAR_ACKTO_8822C(x) | BIT_ACKTO_8822C(v))
+
+/* 2 REG_CTS2TO_8822C (CTS2 TIMEOUT REGISTER) */
+
+#define BIT_SHIFT_CTS2TO_8822C 0
+#define BIT_MASK_CTS2TO_8822C 0xff
+#define BIT_CTS2TO_8822C(x)                                                    \
+	(((x) & BIT_MASK_CTS2TO_8822C) << BIT_SHIFT_CTS2TO_8822C)
+#define BITS_CTS2TO_8822C (BIT_MASK_CTS2TO_8822C << BIT_SHIFT_CTS2TO_8822C)
+#define BIT_CLEAR_CTS2TO_8822C(x) ((x) & (~BITS_CTS2TO_8822C))
+#define BIT_GET_CTS2TO_8822C(x)                                                \
+	(((x) >> BIT_SHIFT_CTS2TO_8822C) & BIT_MASK_CTS2TO_8822C)
+#define BIT_SET_CTS2TO_8822C(x, v)                                             \
+	(BIT_CLEAR_CTS2TO_8822C(x) | BIT_CTS2TO_8822C(v))
+
+/* 2 REG_EIFS_8822C (EIFS REGISTER) */
+
+#define BIT_SHIFT_EIFS_8822C 0
+#define BIT_MASK_EIFS_8822C 0xffff
+#define BIT_EIFS_8822C(x) (((x) & BIT_MASK_EIFS_8822C) << BIT_SHIFT_EIFS_8822C)
+#define BITS_EIFS_8822C (BIT_MASK_EIFS_8822C << BIT_SHIFT_EIFS_8822C)
+#define BIT_CLEAR_EIFS_8822C(x) ((x) & (~BITS_EIFS_8822C))
+#define BIT_GET_EIFS_8822C(x)                                                  \
+	(((x) >> BIT_SHIFT_EIFS_8822C) & BIT_MASK_EIFS_8822C)
+#define BIT_SET_EIFS_8822C(x, v) (BIT_CLEAR_EIFS_8822C(x) | BIT_EIFS_8822C(v))
+
+/* 2 REG_RPFM_MAP0_8822C */
+#define BIT_MGT_RPFM15EN_8822C BIT(15)
+#define BIT_MGT_RPFM14EN_8822C BIT(14)
+#define BIT_MGT_RPFM13EN_8822C BIT(13)
+#define BIT_MGT_RPFM12EN_8822C BIT(12)
+#define BIT_MGT_RPFM11EN_8822C BIT(11)
+#define BIT_MGT_RPFM10EN_8822C BIT(10)
+#define BIT_MGT_RPFM9EN_8822C BIT(9)
+#define BIT_MGT_RPFM8EN_8822C BIT(8)
+#define BIT_MGT_RPFM7EN_8822C BIT(7)
+#define BIT_MGT_RPFM6EN_8822C BIT(6)
+#define BIT_MGT_RPFM5EN_8822C BIT(5)
+#define BIT_MGT_RPFM4EN_8822C BIT(4)
+#define BIT_MGT_RPFM3EN_8822C BIT(3)
+#define BIT_MGT_RPFM2EN_8822C BIT(2)
+#define BIT_MGT_RPFM1EN_8822C BIT(1)
+#define BIT_MGT_RPFM0EN_8822C BIT(0)
+
+/* 2 REG_RPFM_MAP1_V1_8822C */
+#define BIT_DATA_RPFM15EN_8822C BIT(15)
+#define BIT_DATA_RPFM14EN_8822C BIT(14)
+#define BIT_DATA_RPFM13EN_8822C BIT(13)
+#define BIT_DATA_RPFM12EN_8822C BIT(12)
+#define BIT_DATA_RPFM11EN_8822C BIT(11)
+#define BIT_DATA_RPFM10EN_8822C BIT(10)
+#define BIT_DATA_RPFM9EN_8822C BIT(9)
+#define BIT_DATA_RPFM8EN_8822C BIT(8)
+#define BIT_DATA_RPFM7EN_8822C BIT(7)
+#define BIT_DATA_RPFM6EN_8822C BIT(6)
+#define BIT_DATA_RPFM5EN_8822C BIT(5)
+#define BIT_DATA_RPFM4EN_8822C BIT(4)
+#define BIT_DATA_RPFM3EN_8822C BIT(3)
+#define BIT_DATA_RPFM2EN_8822C BIT(2)
+#define BIT_DATA_RPFM1EN_8822C BIT(1)
+#define BIT_DATA_RPFM0EN_8822C BIT(0)
+
+/* 2 REG_RPFM_CAM_CMD_8822C (RX PAYLOAD FRAME MASK CAM COMMAND REGISTER) */
+#define BIT_RPFM_CAM_POLLING_8822C BIT(31)
+#define BIT_RPFM_CAM_CLR_8822C BIT(30)
+#define BIT_RPFM_CAM_WE_8822C BIT(16)
+
+#define BIT_SHIFT_RPFM_CAM_ADDR_8822C 0
+#define BIT_MASK_RPFM_CAM_ADDR_8822C 0x7f
+#define BIT_RPFM_CAM_ADDR_8822C(x)                                             \
+	(((x) & BIT_MASK_RPFM_CAM_ADDR_8822C) << BIT_SHIFT_RPFM_CAM_ADDR_8822C)
+#define BITS_RPFM_CAM_ADDR_8822C                                               \
+	(BIT_MASK_RPFM_CAM_ADDR_8822C << BIT_SHIFT_RPFM_CAM_ADDR_8822C)
+#define BIT_CLEAR_RPFM_CAM_ADDR_8822C(x) ((x) & (~BITS_RPFM_CAM_ADDR_8822C))
+#define BIT_GET_RPFM_CAM_ADDR_8822C(x)                                         \
+	(((x) >> BIT_SHIFT_RPFM_CAM_ADDR_8822C) & BIT_MASK_RPFM_CAM_ADDR_8822C)
+#define BIT_SET_RPFM_CAM_ADDR_8822C(x, v)                                      \
+	(BIT_CLEAR_RPFM_CAM_ADDR_8822C(x) | BIT_RPFM_CAM_ADDR_8822C(v))
+
+/* 2 REG_RPFM_CAM_RWD_8822C (ACK TIMEOUT REGISTER) */
+
+#define BIT_SHIFT_RPFM_CAM_RWD_8822C 0
+#define BIT_MASK_RPFM_CAM_RWD_8822C 0xffffffffL
+#define BIT_RPFM_CAM_RWD_8822C(x)                                              \
+	(((x) & BIT_MASK_RPFM_CAM_RWD_8822C) << BIT_SHIFT_RPFM_CAM_RWD_8822C)
+#define BITS_RPFM_CAM_RWD_8822C                                                \
+	(BIT_MASK_RPFM_CAM_RWD_8822C << BIT_SHIFT_RPFM_CAM_RWD_8822C)
+#define BIT_CLEAR_RPFM_CAM_RWD_8822C(x) ((x) & (~BITS_RPFM_CAM_RWD_8822C))
+#define BIT_GET_RPFM_CAM_RWD_8822C(x)                                          \
+	(((x) >> BIT_SHIFT_RPFM_CAM_RWD_8822C) & BIT_MASK_RPFM_CAM_RWD_8822C)
+#define BIT_SET_RPFM_CAM_RWD_8822C(x, v)                                       \
+	(BIT_CLEAR_RPFM_CAM_RWD_8822C(x) | BIT_RPFM_CAM_RWD_8822C(v))
+
+/* 2 REG_NAV_CTRL_8822C (NAV CONTROL REGISTER) */
+
+#define BIT_SHIFT_NAV_UPPER_8822C 16
+#define BIT_MASK_NAV_UPPER_8822C 0xff
+#define BIT_NAV_UPPER_8822C(x)                                                 \
+	(((x) & BIT_MASK_NAV_UPPER_8822C) << BIT_SHIFT_NAV_UPPER_8822C)
+#define BITS_NAV_UPPER_8822C                                                   \
+	(BIT_MASK_NAV_UPPER_8822C << BIT_SHIFT_NAV_UPPER_8822C)
+#define BIT_CLEAR_NAV_UPPER_8822C(x) ((x) & (~BITS_NAV_UPPER_8822C))
+#define BIT_GET_NAV_UPPER_8822C(x)                                             \
+	(((x) >> BIT_SHIFT_NAV_UPPER_8822C) & BIT_MASK_NAV_UPPER_8822C)
+#define BIT_SET_NAV_UPPER_8822C(x, v)                                          \
+	(BIT_CLEAR_NAV_UPPER_8822C(x) | BIT_NAV_UPPER_8822C(v))
+
+#define BIT_SHIFT_RXMYRTS_NAV_8822C 8
+#define BIT_MASK_RXMYRTS_NAV_8822C 0xf
+#define BIT_RXMYRTS_NAV_8822C(x)                                               \
+	(((x) & BIT_MASK_RXMYRTS_NAV_8822C) << BIT_SHIFT_RXMYRTS_NAV_8822C)
+#define BITS_RXMYRTS_NAV_8822C                                                 \
+	(BIT_MASK_RXMYRTS_NAV_8822C << BIT_SHIFT_RXMYRTS_NAV_8822C)
+#define BIT_CLEAR_RXMYRTS_NAV_8822C(x) ((x) & (~BITS_RXMYRTS_NAV_8822C))
+#define BIT_GET_RXMYRTS_NAV_8822C(x)                                           \
+	(((x) >> BIT_SHIFT_RXMYRTS_NAV_8822C) & BIT_MASK_RXMYRTS_NAV_8822C)
+#define BIT_SET_RXMYRTS_NAV_8822C(x, v)                                        \
+	(BIT_CLEAR_RXMYRTS_NAV_8822C(x) | BIT_RXMYRTS_NAV_8822C(v))
+
+#define BIT_SHIFT_RTSRST_8822C 0
+#define BIT_MASK_RTSRST_8822C 0xff
+#define BIT_RTSRST_8822C(x)                                                    \
+	(((x) & BIT_MASK_RTSRST_8822C) << BIT_SHIFT_RTSRST_8822C)
+#define BITS_RTSRST_8822C (BIT_MASK_RTSRST_8822C << BIT_SHIFT_RTSRST_8822C)
+#define BIT_CLEAR_RTSRST_8822C(x) ((x) & (~BITS_RTSRST_8822C))
+#define BIT_GET_RTSRST_8822C(x)                                                \
+	(((x) >> BIT_SHIFT_RTSRST_8822C) & BIT_MASK_RTSRST_8822C)
+#define BIT_SET_RTSRST_8822C(x, v)                                             \
+	(BIT_CLEAR_RTSRST_8822C(x) | BIT_RTSRST_8822C(v))
+
+/* 2 REG_BACAMCMD_8822C (BLOCK ACK CAM COMMAND REGISTER) */
+#define BIT_BACAM_POLL_8822C BIT(31)
+#define BIT_BACAM_RST_8822C BIT(17)
+#define BIT_BACAM_RW_8822C BIT(16)
+
+#define BIT_SHIFT_TXSBM_8822C 14
+#define BIT_MASK_TXSBM_8822C 0x3
+#define BIT_TXSBM_8822C(x)                                                     \
+	(((x) & BIT_MASK_TXSBM_8822C) << BIT_SHIFT_TXSBM_8822C)
+#define BITS_TXSBM_8822C (BIT_MASK_TXSBM_8822C << BIT_SHIFT_TXSBM_8822C)
+#define BIT_CLEAR_TXSBM_8822C(x) ((x) & (~BITS_TXSBM_8822C))
+#define BIT_GET_TXSBM_8822C(x)                                                 \
+	(((x) >> BIT_SHIFT_TXSBM_8822C) & BIT_MASK_TXSBM_8822C)
+#define BIT_SET_TXSBM_8822C(x, v)                                              \
+	(BIT_CLEAR_TXSBM_8822C(x) | BIT_TXSBM_8822C(v))
+
+#define BIT_SHIFT_BACAM_ADDR_8822C 0
+#define BIT_MASK_BACAM_ADDR_8822C 0x3f
+#define BIT_BACAM_ADDR_8822C(x)                                                \
+	(((x) & BIT_MASK_BACAM_ADDR_8822C) << BIT_SHIFT_BACAM_ADDR_8822C)
+#define BITS_BACAM_ADDR_8822C                                                  \
+	(BIT_MASK_BACAM_ADDR_8822C << BIT_SHIFT_BACAM_ADDR_8822C)
+#define BIT_CLEAR_BACAM_ADDR_8822C(x) ((x) & (~BITS_BACAM_ADDR_8822C))
+#define BIT_GET_BACAM_ADDR_8822C(x)                                            \
+	(((x) >> BIT_SHIFT_BACAM_ADDR_8822C) & BIT_MASK_BACAM_ADDR_8822C)
+#define BIT_SET_BACAM_ADDR_8822C(x, v)                                         \
+	(BIT_CLEAR_BACAM_ADDR_8822C(x) | BIT_BACAM_ADDR_8822C(v))
+
+/* 2 REG_BACAMCONTENT_8822C (BLOCK ACK CAM CONTENT REGISTER) */
+
+#define BIT_SHIFT_BA_CONTENT_L_8822C 0
+#define BIT_MASK_BA_CONTENT_L_8822C 0xffffffffL
+#define BIT_BA_CONTENT_L_8822C(x)                                              \
+	(((x) & BIT_MASK_BA_CONTENT_L_8822C) << BIT_SHIFT_BA_CONTENT_L_8822C)
+#define BITS_BA_CONTENT_L_8822C                                                \
+	(BIT_MASK_BA_CONTENT_L_8822C << BIT_SHIFT_BA_CONTENT_L_8822C)
+#define BIT_CLEAR_BA_CONTENT_L_8822C(x) ((x) & (~BITS_BA_CONTENT_L_8822C))
+#define BIT_GET_BA_CONTENT_L_8822C(x)                                          \
+	(((x) >> BIT_SHIFT_BA_CONTENT_L_8822C) & BIT_MASK_BA_CONTENT_L_8822C)
+#define BIT_SET_BA_CONTENT_L_8822C(x, v)                                       \
+	(BIT_CLEAR_BA_CONTENT_L_8822C(x) | BIT_BA_CONTENT_L_8822C(v))
+
+/* 2 REG_BACAMCONTENT_H_8822C (BLOCK ACK CAM CONTENT REGISTER) */
+
+#define BIT_SHIFT_BA_CONTENT_H_8822C 0
+#define BIT_MASK_BA_CONTENT_H_8822C 0xffffffffL
+#define BIT_BA_CONTENT_H_8822C(x)                                              \
+	(((x) & BIT_MASK_BA_CONTENT_H_8822C) << BIT_SHIFT_BA_CONTENT_H_8822C)
+#define BITS_BA_CONTENT_H_8822C                                                \
+	(BIT_MASK_BA_CONTENT_H_8822C << BIT_SHIFT_BA_CONTENT_H_8822C)
+#define BIT_CLEAR_BA_CONTENT_H_8822C(x) ((x) & (~BITS_BA_CONTENT_H_8822C))
+#define BIT_GET_BA_CONTENT_H_8822C(x)                                          \
+	(((x) >> BIT_SHIFT_BA_CONTENT_H_8822C) & BIT_MASK_BA_CONTENT_H_8822C)
+#define BIT_SET_BA_CONTENT_H_8822C(x, v)                                       \
+	(BIT_CLEAR_BA_CONTENT_H_8822C(x) | BIT_BA_CONTENT_H_8822C(v))
+
+/* 2 REG_LBDLY_8822C (LOOPBACK DELAY REGISTER) */
+
+#define BIT_SHIFT_LBDLY_8822C 0
+#define BIT_MASK_LBDLY_8822C 0x1f
+#define BIT_LBDLY_8822C(x)                                                     \
+	(((x) & BIT_MASK_LBDLY_8822C) << BIT_SHIFT_LBDLY_8822C)
+#define BITS_LBDLY_8822C (BIT_MASK_LBDLY_8822C << BIT_SHIFT_LBDLY_8822C)
+#define BIT_CLEAR_LBDLY_8822C(x) ((x) & (~BITS_LBDLY_8822C))
+#define BIT_GET_LBDLY_8822C(x)                                                 \
+	(((x) >> BIT_SHIFT_LBDLY_8822C) & BIT_MASK_LBDLY_8822C)
+#define BIT_SET_LBDLY_8822C(x, v)                                              \
+	(BIT_CLEAR_LBDLY_8822C(x) | BIT_LBDLY_8822C(v))
+
+/* 2 REG_WMAC_BACAM_RPMEN_8822C */
+
+#define BIT_SHIFT_BITMAP_SSNBK_COUNTER_8822C 2
+#define BIT_MASK_BITMAP_SSNBK_COUNTER_8822C 0x3f
+#define BIT_BITMAP_SSNBK_COUNTER_8822C(x)                                      \
+	(((x) & BIT_MASK_BITMAP_SSNBK_COUNTER_8822C)                           \
+	 << BIT_SHIFT_BITMAP_SSNBK_COUNTER_8822C)
+#define BITS_BITMAP_SSNBK_COUNTER_8822C                                        \
+	(BIT_MASK_BITMAP_SSNBK_COUNTER_8822C                                   \
+	 << BIT_SHIFT_BITMAP_SSNBK_COUNTER_8822C)
+#define BIT_CLEAR_BITMAP_SSNBK_COUNTER_8822C(x)                                \
+	((x) & (~BITS_BITMAP_SSNBK_COUNTER_8822C))
+#define BIT_GET_BITMAP_SSNBK_COUNTER_8822C(x)                                  \
+	(((x) >> BIT_SHIFT_BITMAP_SSNBK_COUNTER_8822C) &                       \
+	 BIT_MASK_BITMAP_SSNBK_COUNTER_8822C)
+#define BIT_SET_BITMAP_SSNBK_COUNTER_8822C(x, v)                               \
+	(BIT_CLEAR_BITMAP_SSNBK_COUNTER_8822C(x) |                             \
+	 BIT_BITMAP_SSNBK_COUNTER_8822C(v))
+
+#define BIT_BITMAP_EN_8822C BIT(1)
+#define BIT_WMAC_BACAM_RPMEN_8822C BIT(0)
+
+/* 2 REG_TX_RX_8822C STATUS */
+
+#define BIT_SHIFT_RXPKT_TYPE_8822C 2
+#define BIT_MASK_RXPKT_TYPE_8822C 0x3f
+#define BIT_RXPKT_TYPE_8822C(x)                                                \
+	(((x) & BIT_MASK_RXPKT_TYPE_8822C) << BIT_SHIFT_RXPKT_TYPE_8822C)
+#define BITS_RXPKT_TYPE_8822C                                                  \
+	(BIT_MASK_RXPKT_TYPE_8822C << BIT_SHIFT_RXPKT_TYPE_8822C)
+#define BIT_CLEAR_RXPKT_TYPE_8822C(x) ((x) & (~BITS_RXPKT_TYPE_8822C))
+#define BIT_GET_RXPKT_TYPE_8822C(x)                                            \
+	(((x) >> BIT_SHIFT_RXPKT_TYPE_8822C) & BIT_MASK_RXPKT_TYPE_8822C)
+#define BIT_SET_RXPKT_TYPE_8822C(x, v)                                         \
+	(BIT_CLEAR_RXPKT_TYPE_8822C(x) | BIT_RXPKT_TYPE_8822C(v))
+
+#define BIT_TXACT_IND_8822C BIT(1)
+#define BIT_RXACT_IND_8822C BIT(0)
+
+/* 2 REG_WMAC_BITMAP_CTL_8822C */
+#define BIT_BITMAP_VO_8822C BIT(7)
+#define BIT_BITMAP_VI_8822C BIT(6)
+#define BIT_BITMAP_BE_8822C BIT(5)
+#define BIT_BITMAP_BK_8822C BIT(4)
+
+#define BIT_SHIFT_BITMAP_CONDITION_8822C 2
+#define BIT_MASK_BITMAP_CONDITION_8822C 0x3
+#define BIT_BITMAP_CONDITION_8822C(x)                                          \
+	(((x) & BIT_MASK_BITMAP_CONDITION_8822C)                               \
+	 << BIT_SHIFT_BITMAP_CONDITION_8822C)
+#define BITS_BITMAP_CONDITION_8822C                                            \
+	(BIT_MASK_BITMAP_CONDITION_8822C << BIT_SHIFT_BITMAP_CONDITION_8822C)
+#define BIT_CLEAR_BITMAP_CONDITION_8822C(x)                                    \
+	((x) & (~BITS_BITMAP_CONDITION_8822C))
+#define BIT_GET_BITMAP_CONDITION_8822C(x)                                      \
+	(((x) >> BIT_SHIFT_BITMAP_CONDITION_8822C) &                           \
+	 BIT_MASK_BITMAP_CONDITION_8822C)
+#define BIT_SET_BITMAP_CONDITION_8822C(x, v)                                   \
+	(BIT_CLEAR_BITMAP_CONDITION_8822C(x) | BIT_BITMAP_CONDITION_8822C(v))
+
+#define BIT_BITMAP_SSNBK_COUNTER_CLR_8822C BIT(1)
+#define BIT_BITMAP_FORCE_8822C BIT(0)
+
+/* 2 REG_RXERR_RPT_8822C (RX ERROR REPORT REGISTER) */
+
+#define BIT_SHIFT_RXERR_RPT_SEL_V1_3_0_8822C 28
+#define BIT_MASK_RXERR_RPT_SEL_V1_3_0_8822C 0xf
+#define BIT_RXERR_RPT_SEL_V1_3_0_8822C(x)                                      \
+	(((x) & BIT_MASK_RXERR_RPT_SEL_V1_3_0_8822C)                           \
+	 << BIT_SHIFT_RXERR_RPT_SEL_V1_3_0_8822C)
+#define BITS_RXERR_RPT_SEL_V1_3_0_8822C                                        \
+	(BIT_MASK_RXERR_RPT_SEL_V1_3_0_8822C                                   \
+	 << BIT_SHIFT_RXERR_RPT_SEL_V1_3_0_8822C)
+#define BIT_CLEAR_RXERR_RPT_SEL_V1_3_0_8822C(x)                                \
+	((x) & (~BITS_RXERR_RPT_SEL_V1_3_0_8822C))
+#define BIT_GET_RXERR_RPT_SEL_V1_3_0_8822C(x)                                  \
+	(((x) >> BIT_SHIFT_RXERR_RPT_SEL_V1_3_0_8822C) &                       \
+	 BIT_MASK_RXERR_RPT_SEL_V1_3_0_8822C)
+#define BIT_SET_RXERR_RPT_SEL_V1_3_0_8822C(x, v)                               \
+	(BIT_CLEAR_RXERR_RPT_SEL_V1_3_0_8822C(x) |                             \
+	 BIT_RXERR_RPT_SEL_V1_3_0_8822C(v))
+
+#define BIT_RXERR_RPT_RST_8822C BIT(27)
+#define BIT_RXERR_RPT_SEL_V1_4_8822C BIT(26)
+
+#define BIT_SHIFT_UD_SELECT_BSSID_2_1_8822C 24
+#define BIT_MASK_UD_SELECT_BSSID_2_1_8822C 0x3
+#define BIT_UD_SELECT_BSSID_2_1_8822C(x)                                       \
+	(((x) & BIT_MASK_UD_SELECT_BSSID_2_1_8822C)                            \
+	 << BIT_SHIFT_UD_SELECT_BSSID_2_1_8822C)
+#define BITS_UD_SELECT_BSSID_2_1_8822C                                         \
+	(BIT_MASK_UD_SELECT_BSSID_2_1_8822C                                    \
+	 << BIT_SHIFT_UD_SELECT_BSSID_2_1_8822C)
+#define BIT_CLEAR_UD_SELECT_BSSID_2_1_8822C(x)                                 \
+	((x) & (~BITS_UD_SELECT_BSSID_2_1_8822C))
+#define BIT_GET_UD_SELECT_BSSID_2_1_8822C(x)                                   \
+	(((x) >> BIT_SHIFT_UD_SELECT_BSSID_2_1_8822C) &                        \
+	 BIT_MASK_UD_SELECT_BSSID_2_1_8822C)
+#define BIT_SET_UD_SELECT_BSSID_2_1_8822C(x, v)                                \
+	(BIT_CLEAR_UD_SELECT_BSSID_2_1_8822C(x) |                              \
+	 BIT_UD_SELECT_BSSID_2_1_8822C(v))
+
+#define BIT_W1S_8822C BIT(23)
+#define BIT_UD_SELECT_BSSID_0_8822C BIT(22)
+
+#define BIT_SHIFT_UD_SUB_TYPE_8822C 18
+#define BIT_MASK_UD_SUB_TYPE_8822C 0xf
+#define BIT_UD_SUB_TYPE_8822C(x)                                               \
+	(((x) & BIT_MASK_UD_SUB_TYPE_8822C) << BIT_SHIFT_UD_SUB_TYPE_8822C)
+#define BITS_UD_SUB_TYPE_8822C                                                 \
+	(BIT_MASK_UD_SUB_TYPE_8822C << BIT_SHIFT_UD_SUB_TYPE_8822C)
+#define BIT_CLEAR_UD_SUB_TYPE_8822C(x) ((x) & (~BITS_UD_SUB_TYPE_8822C))
+#define BIT_GET_UD_SUB_TYPE_8822C(x)                                           \
+	(((x) >> BIT_SHIFT_UD_SUB_TYPE_8822C) & BIT_MASK_UD_SUB_TYPE_8822C)
+#define BIT_SET_UD_SUB_TYPE_8822C(x, v)                                        \
+	(BIT_CLEAR_UD_SUB_TYPE_8822C(x) | BIT_UD_SUB_TYPE_8822C(v))
+
+#define BIT_SHIFT_UD_TYPE_8822C 16
+#define BIT_MASK_UD_TYPE_8822C 0x3
+#define BIT_UD_TYPE_8822C(x)                                                   \
+	(((x) & BIT_MASK_UD_TYPE_8822C) << BIT_SHIFT_UD_TYPE_8822C)
+#define BITS_UD_TYPE_8822C (BIT_MASK_UD_TYPE_8822C << BIT_SHIFT_UD_TYPE_8822C)
+#define BIT_CLEAR_UD_TYPE_8822C(x) ((x) & (~BITS_UD_TYPE_8822C))
+#define BIT_GET_UD_TYPE_8822C(x)                                               \
+	(((x) >> BIT_SHIFT_UD_TYPE_8822C) & BIT_MASK_UD_TYPE_8822C)
+#define BIT_SET_UD_TYPE_8822C(x, v)                                            \
+	(BIT_CLEAR_UD_TYPE_8822C(x) | BIT_UD_TYPE_8822C(v))
+
+#define BIT_SHIFT_RPT_COUNTER_8822C 0
+#define BIT_MASK_RPT_COUNTER_8822C 0xffff
+#define BIT_RPT_COUNTER_8822C(x)                                               \
+	(((x) & BIT_MASK_RPT_COUNTER_8822C) << BIT_SHIFT_RPT_COUNTER_8822C)
+#define BITS_RPT_COUNTER_8822C                                                 \
+	(BIT_MASK_RPT_COUNTER_8822C << BIT_SHIFT_RPT_COUNTER_8822C)
+#define BIT_CLEAR_RPT_COUNTER_8822C(x) ((x) & (~BITS_RPT_COUNTER_8822C))
+#define BIT_GET_RPT_COUNTER_8822C(x)                                           \
+	(((x) >> BIT_SHIFT_RPT_COUNTER_8822C) & BIT_MASK_RPT_COUNTER_8822C)
+#define BIT_SET_RPT_COUNTER_8822C(x, v)                                        \
+	(BIT_CLEAR_RPT_COUNTER_8822C(x) | BIT_RPT_COUNTER_8822C(v))
+
+/* 2 REG_WMAC_TRXPTCL_CTL_8822C	(WMAC TX/RX PROTOCOL CONTROL REGISTER) */
+#define BIT_ACKTO_BLOCK_SCH_EN_8822C BIT(27)
+#define BIT_EIFS_BLOCK_SCH_EN_8822C BIT(26)
+#define BIT_PLCPCHK_RST_EIFS_8822C BIT(25)
+#define BIT_CCA_RST_EIFS_8822C BIT(24)
+#define BIT_DIS_UPD_MYRXPKTNAV_8822C BIT(23)
+#define BIT_EARLY_TXBA_8822C BIT(22)
+
+#define BIT_SHIFT_RESP_CHNBUSY_8822C 20
+#define BIT_MASK_RESP_CHNBUSY_8822C 0x3
+#define BIT_RESP_CHNBUSY_8822C(x)                                              \
+	(((x) & BIT_MASK_RESP_CHNBUSY_8822C) << BIT_SHIFT_RESP_CHNBUSY_8822C)
+#define BITS_RESP_CHNBUSY_8822C                                                \
+	(BIT_MASK_RESP_CHNBUSY_8822C << BIT_SHIFT_RESP_CHNBUSY_8822C)
+#define BIT_CLEAR_RESP_CHNBUSY_8822C(x) ((x) & (~BITS_RESP_CHNBUSY_8822C))
+#define BIT_GET_RESP_CHNBUSY_8822C(x)                                          \
+	(((x) >> BIT_SHIFT_RESP_CHNBUSY_8822C) & BIT_MASK_RESP_CHNBUSY_8822C)
+#define BIT_SET_RESP_CHNBUSY_8822C(x, v)                                       \
+	(BIT_CLEAR_RESP_CHNBUSY_8822C(x) | BIT_RESP_CHNBUSY_8822C(v))
+
+#define BIT_RESP_DCTS_EN_8822C BIT(19)
+#define BIT_RESP_DCFE_EN_8822C BIT(18)
+#define BIT_RESP_SPLCPEN_8822C BIT(17)
+#define BIT_RESP_SGIEN_8822C BIT(16)
+#define BIT_RESP_LDPC_EN_8822C BIT(15)
+#define BIT_DIS_RESP_ACKINCCA_8822C BIT(14)
+#define BIT_DIS_RESP_CTSINCCA_8822C BIT(13)
+
+#define BIT_SHIFT_R_WMAC_SECOND_CCA_TIMER_8822C 10
+#define BIT_MASK_R_WMAC_SECOND_CCA_TIMER_8822C 0x7
+#define BIT_R_WMAC_SECOND_CCA_TIMER_8822C(x)                                   \
+	(((x) & BIT_MASK_R_WMAC_SECOND_CCA_TIMER_8822C)                        \
+	 << BIT_SHIFT_R_WMAC_SECOND_CCA_TIMER_8822C)
+#define BITS_R_WMAC_SECOND_CCA_TIMER_8822C                                     \
+	(BIT_MASK_R_WMAC_SECOND_CCA_TIMER_8822C                                \
+	 << BIT_SHIFT_R_WMAC_SECOND_CCA_TIMER_8822C)
+#define BIT_CLEAR_R_WMAC_SECOND_CCA_TIMER_8822C(x)                             \
+	((x) & (~BITS_R_WMAC_SECOND_CCA_TIMER_8822C))
+#define BIT_GET_R_WMAC_SECOND_CCA_TIMER_8822C(x)                               \
+	(((x) >> BIT_SHIFT_R_WMAC_SECOND_CCA_TIMER_8822C) &                    \
+	 BIT_MASK_R_WMAC_SECOND_CCA_TIMER_8822C)
+#define BIT_SET_R_WMAC_SECOND_CCA_TIMER_8822C(x, v)                            \
+	(BIT_CLEAR_R_WMAC_SECOND_CCA_TIMER_8822C(x) |                          \
+	 BIT_R_WMAC_SECOND_CCA_TIMER_8822C(v))
+
+#define BIT_SHIFT_RFMOD_8822C 7
+#define BIT_MASK_RFMOD_8822C 0x3
+#define BIT_RFMOD_8822C(x)                                                     \
+	(((x) & BIT_MASK_RFMOD_8822C) << BIT_SHIFT_RFMOD_8822C)
+#define BITS_RFMOD_8822C (BIT_MASK_RFMOD_8822C << BIT_SHIFT_RFMOD_8822C)
+#define BIT_CLEAR_RFMOD_8822C(x) ((x) & (~BITS_RFMOD_8822C))
+#define BIT_GET_RFMOD_8822C(x)                                                 \
+	(((x) >> BIT_SHIFT_RFMOD_8822C) & BIT_MASK_RFMOD_8822C)
+#define BIT_SET_RFMOD_8822C(x, v)                                              \
+	(BIT_CLEAR_RFMOD_8822C(x) | BIT_RFMOD_8822C(v))
+
+#define BIT_SHIFT_RESP_CTS_DYNBW_SEL_8822C 5
+#define BIT_MASK_RESP_CTS_DYNBW_SEL_8822C 0x3
+#define BIT_RESP_CTS_DYNBW_SEL_8822C(x)                                        \
+	(((x) & BIT_MASK_RESP_CTS_DYNBW_SEL_8822C)                             \
+	 << BIT_SHIFT_RESP_CTS_DYNBW_SEL_8822C)
+#define BITS_RESP_CTS_DYNBW_SEL_8822C                                          \
+	(BIT_MASK_RESP_CTS_DYNBW_SEL_8822C                                     \
+	 << BIT_SHIFT_RESP_CTS_DYNBW_SEL_8822C)
+#define BIT_CLEAR_RESP_CTS_DYNBW_SEL_8822C(x)                                  \
+	((x) & (~BITS_RESP_CTS_DYNBW_SEL_8822C))
+#define BIT_GET_RESP_CTS_DYNBW_SEL_8822C(x)                                    \
+	(((x) >> BIT_SHIFT_RESP_CTS_DYNBW_SEL_8822C) &                         \
+	 BIT_MASK_RESP_CTS_DYNBW_SEL_8822C)
+#define BIT_SET_RESP_CTS_DYNBW_SEL_8822C(x, v)                                 \
+	(BIT_CLEAR_RESP_CTS_DYNBW_SEL_8822C(x) |                               \
+	 BIT_RESP_CTS_DYNBW_SEL_8822C(v))
+
+#define BIT_DLY_TX_WAIT_RXANTSEL_8822C BIT(4)
+#define BIT_TXRESP_BY_RXANTSEL_8822C BIT(3)
+
+#define BIT_SHIFT_ORIG_DCTS_CHK_8822C 0
+#define BIT_MASK_ORIG_DCTS_CHK_8822C 0x3
+#define BIT_ORIG_DCTS_CHK_8822C(x)                                             \
+	(((x) & BIT_MASK_ORIG_DCTS_CHK_8822C) << BIT_SHIFT_ORIG_DCTS_CHK_8822C)
+#define BITS_ORIG_DCTS_CHK_8822C                                               \
+	(BIT_MASK_ORIG_DCTS_CHK_8822C << BIT_SHIFT_ORIG_DCTS_CHK_8822C)
+#define BIT_CLEAR_ORIG_DCTS_CHK_8822C(x) ((x) & (~BITS_ORIG_DCTS_CHK_8822C))
+#define BIT_GET_ORIG_DCTS_CHK_8822C(x)                                         \
+	(((x) >> BIT_SHIFT_ORIG_DCTS_CHK_8822C) & BIT_MASK_ORIG_DCTS_CHK_8822C)
+#define BIT_SET_ORIG_DCTS_CHK_8822C(x, v)                                      \
+	(BIT_CLEAR_ORIG_DCTS_CHK_8822C(x) | BIT_ORIG_DCTS_CHK_8822C(v))
+
+/* 2 REG_WMAC_TRXPTCL_CTL_H_8822C */
+
+#define BIT_SHIFT_ACKBA_TYPSEL_8822C 28
+#define BIT_MASK_ACKBA_TYPSEL_8822C 0xf
+#define BIT_ACKBA_TYPSEL_8822C(x)                                              \
+	(((x) & BIT_MASK_ACKBA_TYPSEL_8822C) << BIT_SHIFT_ACKBA_TYPSEL_8822C)
+#define BITS_ACKBA_TYPSEL_8822C                                                \
+	(BIT_MASK_ACKBA_TYPSEL_8822C << BIT_SHIFT_ACKBA_TYPSEL_8822C)
+#define BIT_CLEAR_ACKBA_TYPSEL_8822C(x) ((x) & (~BITS_ACKBA_TYPSEL_8822C))
+#define BIT_GET_ACKBA_TYPSEL_8822C(x)                                          \
+	(((x) >> BIT_SHIFT_ACKBA_TYPSEL_8822C) & BIT_MASK_ACKBA_TYPSEL_8822C)
+#define BIT_SET_ACKBA_TYPSEL_8822C(x, v)                                       \
+	(BIT_CLEAR_ACKBA_TYPSEL_8822C(x) | BIT_ACKBA_TYPSEL_8822C(v))
+
+#define BIT_SHIFT_ACKBA_ACKPCHK_8822C 24
+#define BIT_MASK_ACKBA_ACKPCHK_8822C 0xf
+#define BIT_ACKBA_ACKPCHK_8822C(x)                                             \
+	(((x) & BIT_MASK_ACKBA_ACKPCHK_8822C) << BIT_SHIFT_ACKBA_ACKPCHK_8822C)
+#define BITS_ACKBA_ACKPCHK_8822C                                               \
+	(BIT_MASK_ACKBA_ACKPCHK_8822C << BIT_SHIFT_ACKBA_ACKPCHK_8822C)
+#define BIT_CLEAR_ACKBA_ACKPCHK_8822C(x) ((x) & (~BITS_ACKBA_ACKPCHK_8822C))
+#define BIT_GET_ACKBA_ACKPCHK_8822C(x)                                         \
+	(((x) >> BIT_SHIFT_ACKBA_ACKPCHK_8822C) & BIT_MASK_ACKBA_ACKPCHK_8822C)
+#define BIT_SET_ACKBA_ACKPCHK_8822C(x, v)                                      \
+	(BIT_CLEAR_ACKBA_ACKPCHK_8822C(x) | BIT_ACKBA_ACKPCHK_8822C(v))
+
+#define BIT_SHIFT_ACKBAR_TYPESEL_8822C 16
+#define BIT_MASK_ACKBAR_TYPESEL_8822C 0xff
+#define BIT_ACKBAR_TYPESEL_8822C(x)                                            \
+	(((x) & BIT_MASK_ACKBAR_TYPESEL_8822C)                                 \
+	 << BIT_SHIFT_ACKBAR_TYPESEL_8822C)
+#define BITS_ACKBAR_TYPESEL_8822C                                              \
+	(BIT_MASK_ACKBAR_TYPESEL_8822C << BIT_SHIFT_ACKBAR_TYPESEL_8822C)
+#define BIT_CLEAR_ACKBAR_TYPESEL_8822C(x) ((x) & (~BITS_ACKBAR_TYPESEL_8822C))
+#define BIT_GET_ACKBAR_TYPESEL_8822C(x)                                        \
+	(((x) >> BIT_SHIFT_ACKBAR_TYPESEL_8822C) &                             \
+	 BIT_MASK_ACKBAR_TYPESEL_8822C)
+#define BIT_SET_ACKBAR_TYPESEL_8822C(x, v)                                     \
+	(BIT_CLEAR_ACKBAR_TYPESEL_8822C(x) | BIT_ACKBAR_TYPESEL_8822C(v))
+
+#define BIT_SHIFT_ACKBAR_ACKPCHK_8822C 12
+#define BIT_MASK_ACKBAR_ACKPCHK_8822C 0xf
+#define BIT_ACKBAR_ACKPCHK_8822C(x)                                            \
+	(((x) & BIT_MASK_ACKBAR_ACKPCHK_8822C)                                 \
+	 << BIT_SHIFT_ACKBAR_ACKPCHK_8822C)
+#define BITS_ACKBAR_ACKPCHK_8822C                                              \
+	(BIT_MASK_ACKBAR_ACKPCHK_8822C << BIT_SHIFT_ACKBAR_ACKPCHK_8822C)
+#define BIT_CLEAR_ACKBAR_ACKPCHK_8822C(x) ((x) & (~BITS_ACKBAR_ACKPCHK_8822C))
+#define BIT_GET_ACKBAR_ACKPCHK_8822C(x)                                        \
+	(((x) >> BIT_SHIFT_ACKBAR_ACKPCHK_8822C) &                             \
+	 BIT_MASK_ACKBAR_ACKPCHK_8822C)
+#define BIT_SET_ACKBAR_ACKPCHK_8822C(x, v)                                     \
+	(BIT_CLEAR_ACKBAR_ACKPCHK_8822C(x) | BIT_ACKBAR_ACKPCHK_8822C(v))
+
+#define BIT_RXBA_IGNOREA2_V1_8822C BIT(10)
+#define BIT_EN_SAVE_ALL_TXOPADDR_V1_8822C BIT(9)
+#define BIT_EN_TXCTS_TO_TXOPOWNER_INRXNAV_V1_8822C BIT(8)
+#define BIT_DIS_TXBA_AMPDUFCSERR_V1_8822C BIT(7)
+#define BIT_DIS_TXBA_RXBARINFULL_V1_8822C BIT(6)
+#define BIT_DIS_TXCFE_INFULL_V1_8822C BIT(5)
+#define BIT_DIS_TXCTS_INFULL_V1_8822C BIT(4)
+#define BIT_EN_TXACKBA_IN_TX_RDG_V1_8822C BIT(3)
+#define BIT_EN_TXACKBA_IN_TXOP_V1_8822C BIT(2)
+#define BIT_EN_TXCTS_IN_RXNAV_V1_8822C BIT(1)
+#define BIT_EN_TXCTS_INTXOP_V1_8822C BIT(0)
+
+/* 2 REG_CAMCMD_8822C (CAM COMMAND REGISTER) */
+#define BIT_SECCAM_POLLING_8822C BIT(31)
+#define BIT_SECCAM_CLR_8822C BIT(30)
+#define BIT_SECCAM_WE_8822C BIT(16)
+
+#define BIT_SHIFT_SECCAM_ADDR_V2_8822C 0
+#define BIT_MASK_SECCAM_ADDR_V2_8822C 0x3ff
+#define BIT_SECCAM_ADDR_V2_8822C(x)                                            \
+	(((x) & BIT_MASK_SECCAM_ADDR_V2_8822C)                                 \
+	 << BIT_SHIFT_SECCAM_ADDR_V2_8822C)
+#define BITS_SECCAM_ADDR_V2_8822C                                              \
+	(BIT_MASK_SECCAM_ADDR_V2_8822C << BIT_SHIFT_SECCAM_ADDR_V2_8822C)
+#define BIT_CLEAR_SECCAM_ADDR_V2_8822C(x) ((x) & (~BITS_SECCAM_ADDR_V2_8822C))
+#define BIT_GET_SECCAM_ADDR_V2_8822C(x)                                        \
+	(((x) >> BIT_SHIFT_SECCAM_ADDR_V2_8822C) &                             \
+	 BIT_MASK_SECCAM_ADDR_V2_8822C)
+#define BIT_SET_SECCAM_ADDR_V2_8822C(x, v)                                     \
+	(BIT_CLEAR_SECCAM_ADDR_V2_8822C(x) | BIT_SECCAM_ADDR_V2_8822C(v))
+
+/* 2 REG_CAMWRITE_8822C (CAM WRITE REGISTER) */
+
+#define BIT_SHIFT_CAMW_DATA_8822C 0
+#define BIT_MASK_CAMW_DATA_8822C 0xffffffffL
+#define BIT_CAMW_DATA_8822C(x)                                                 \
+	(((x) & BIT_MASK_CAMW_DATA_8822C) << BIT_SHIFT_CAMW_DATA_8822C)
+#define BITS_CAMW_DATA_8822C                                                   \
+	(BIT_MASK_CAMW_DATA_8822C << BIT_SHIFT_CAMW_DATA_8822C)
+#define BIT_CLEAR_CAMW_DATA_8822C(x) ((x) & (~BITS_CAMW_DATA_8822C))
+#define BIT_GET_CAMW_DATA_8822C(x)                                             \
+	(((x) >> BIT_SHIFT_CAMW_DATA_8822C) & BIT_MASK_CAMW_DATA_8822C)
+#define BIT_SET_CAMW_DATA_8822C(x, v)                                          \
+	(BIT_CLEAR_CAMW_DATA_8822C(x) | BIT_CAMW_DATA_8822C(v))
+
+/* 2 REG_CAMREAD_8822C (CAM READ REGISTER) */
+
+#define BIT_SHIFT_CAMR_DATA_8822C 0
+#define BIT_MASK_CAMR_DATA_8822C 0xffffffffL
+#define BIT_CAMR_DATA_8822C(x)                                                 \
+	(((x) & BIT_MASK_CAMR_DATA_8822C) << BIT_SHIFT_CAMR_DATA_8822C)
+#define BITS_CAMR_DATA_8822C                                                   \
+	(BIT_MASK_CAMR_DATA_8822C << BIT_SHIFT_CAMR_DATA_8822C)
+#define BIT_CLEAR_CAMR_DATA_8822C(x) ((x) & (~BITS_CAMR_DATA_8822C))
+#define BIT_GET_CAMR_DATA_8822C(x)                                             \
+	(((x) >> BIT_SHIFT_CAMR_DATA_8822C) & BIT_MASK_CAMR_DATA_8822C)
+#define BIT_SET_CAMR_DATA_8822C(x, v)                                          \
+	(BIT_CLEAR_CAMR_DATA_8822C(x) | BIT_CAMR_DATA_8822C(v))
+
+/* 2 REG_CAMDBG_8822C (CAM DEBUG REGISTER) */
+#define BIT_SECCAM_INFO_8822C BIT(31)
+#define BIT_SEC_KEYFOUND_8822C BIT(15)
+
+#define BIT_SHIFT_CAMDBG_SEC_TYPE_8822C 12
+#define BIT_MASK_CAMDBG_SEC_TYPE_8822C 0x7
+#define BIT_CAMDBG_SEC_TYPE_8822C(x)                                           \
+	(((x) & BIT_MASK_CAMDBG_SEC_TYPE_8822C)                                \
+	 << BIT_SHIFT_CAMDBG_SEC_TYPE_8822C)
+#define BITS_CAMDBG_SEC_TYPE_8822C                                             \
+	(BIT_MASK_CAMDBG_SEC_TYPE_8822C << BIT_SHIFT_CAMDBG_SEC_TYPE_8822C)
+#define BIT_CLEAR_CAMDBG_SEC_TYPE_8822C(x) ((x) & (~BITS_CAMDBG_SEC_TYPE_8822C))
+#define BIT_GET_CAMDBG_SEC_TYPE_8822C(x)                                       \
+	(((x) >> BIT_SHIFT_CAMDBG_SEC_TYPE_8822C) &                            \
+	 BIT_MASK_CAMDBG_SEC_TYPE_8822C)
+#define BIT_SET_CAMDBG_SEC_TYPE_8822C(x, v)                                    \
+	(BIT_CLEAR_CAMDBG_SEC_TYPE_8822C(x) | BIT_CAMDBG_SEC_TYPE_8822C(v))
+
+#define BIT_CAMDBG_EXT_SECTYPE_8822C BIT(11)
+
+#define BIT_SHIFT_CAMDBG_MIC_KEY_IDX_8822C 5
+#define BIT_MASK_CAMDBG_MIC_KEY_IDX_8822C 0x1f
+#define BIT_CAMDBG_MIC_KEY_IDX_8822C(x)                                        \
+	(((x) & BIT_MASK_CAMDBG_MIC_KEY_IDX_8822C)                             \
+	 << BIT_SHIFT_CAMDBG_MIC_KEY_IDX_8822C)
+#define BITS_CAMDBG_MIC_KEY_IDX_8822C                                          \
+	(BIT_MASK_CAMDBG_MIC_KEY_IDX_8822C                                     \
+	 << BIT_SHIFT_CAMDBG_MIC_KEY_IDX_8822C)
+#define BIT_CLEAR_CAMDBG_MIC_KEY_IDX_8822C(x)                                  \
+	((x) & (~BITS_CAMDBG_MIC_KEY_IDX_8822C))
+#define BIT_GET_CAMDBG_MIC_KEY_IDX_8822C(x)                                    \
+	(((x) >> BIT_SHIFT_CAMDBG_MIC_KEY_IDX_8822C) &                         \
+	 BIT_MASK_CAMDBG_MIC_KEY_IDX_8822C)
+#define BIT_SET_CAMDBG_MIC_KEY_IDX_8822C(x, v)                                 \
+	(BIT_CLEAR_CAMDBG_MIC_KEY_IDX_8822C(x) |                               \
+	 BIT_CAMDBG_MIC_KEY_IDX_8822C(v))
+
+#define BIT_SHIFT_CAMDBG_SEC_KEY_IDX_8822C 0
+#define BIT_MASK_CAMDBG_SEC_KEY_IDX_8822C 0x1f
+#define BIT_CAMDBG_SEC_KEY_IDX_8822C(x)                                        \
+	(((x) & BIT_MASK_CAMDBG_SEC_KEY_IDX_8822C)                             \
+	 << BIT_SHIFT_CAMDBG_SEC_KEY_IDX_8822C)
+#define BITS_CAMDBG_SEC_KEY_IDX_8822C                                          \
+	(BIT_MASK_CAMDBG_SEC_KEY_IDX_8822C                                     \
+	 << BIT_SHIFT_CAMDBG_SEC_KEY_IDX_8822C)
+#define BIT_CLEAR_CAMDBG_SEC_KEY_IDX_8822C(x)                                  \
+	((x) & (~BITS_CAMDBG_SEC_KEY_IDX_8822C))
+#define BIT_GET_CAMDBG_SEC_KEY_IDX_8822C(x)                                    \
+	(((x) >> BIT_SHIFT_CAMDBG_SEC_KEY_IDX_8822C) &                         \
+	 BIT_MASK_CAMDBG_SEC_KEY_IDX_8822C)
+#define BIT_SET_CAMDBG_SEC_KEY_IDX_8822C(x, v)                                 \
+	(BIT_CLEAR_CAMDBG_SEC_KEY_IDX_8822C(x) |                               \
+	 BIT_CAMDBG_SEC_KEY_IDX_8822C(v))
+
+/* 2 REG_SECCFG_8822C (SECURITY CONFIGURATION REGISTER) */
+#define BIT_DIS_GCLK_WAPI_8822C BIT(15)
+#define BIT_DIS_GCLK_AES_8822C BIT(14)
+#define BIT_DIS_GCLK_TKIP_8822C BIT(13)
+#define BIT_AES_SEL_QC_1_8822C BIT(12)
+#define BIT_AES_SEL_QC_0_8822C BIT(11)
+#define BIT_CHK_BMC_8822C BIT(9)
+#define BIT_CHK_KEYID_8822C BIT(8)
+#define BIT_RXBCUSEDK_8822C BIT(7)
+#define BIT_TXBCUSEDK_8822C BIT(6)
+#define BIT_NOSKMC_8822C BIT(5)
+#define BIT_SKBYA2_8822C BIT(4)
+#define BIT_RXDEC_8822C BIT(3)
+#define BIT_TXENC_8822C BIT(2)
+#define BIT_RXUHUSEDK_8822C BIT(1)
+#define BIT_TXUHUSEDK_8822C BIT(0)
+
+/* 2 REG_RXFILTER_CATEGORY_1_8822C */
+
+#define BIT_SHIFT_RXFILTER_CATEGORY_1_8822C 0
+#define BIT_MASK_RXFILTER_CATEGORY_1_8822C 0xff
+#define BIT_RXFILTER_CATEGORY_1_8822C(x)                                       \
+	(((x) & BIT_MASK_RXFILTER_CATEGORY_1_8822C)                            \
+	 << BIT_SHIFT_RXFILTER_CATEGORY_1_8822C)
+#define BITS_RXFILTER_CATEGORY_1_8822C                                         \
+	(BIT_MASK_RXFILTER_CATEGORY_1_8822C                                    \
+	 << BIT_SHIFT_RXFILTER_CATEGORY_1_8822C)
+#define BIT_CLEAR_RXFILTER_CATEGORY_1_8822C(x)                                 \
+	((x) & (~BITS_RXFILTER_CATEGORY_1_8822C))
+#define BIT_GET_RXFILTER_CATEGORY_1_8822C(x)                                   \
+	(((x) >> BIT_SHIFT_RXFILTER_CATEGORY_1_8822C) &                        \
+	 BIT_MASK_RXFILTER_CATEGORY_1_8822C)
+#define BIT_SET_RXFILTER_CATEGORY_1_8822C(x, v)                                \
+	(BIT_CLEAR_RXFILTER_CATEGORY_1_8822C(x) |                              \
+	 BIT_RXFILTER_CATEGORY_1_8822C(v))
+
+/* 2 REG_RXFILTER_ACTION_1_8822C */
+
+#define BIT_SHIFT_RXFILTER_ACTION_1_8822C 0
+#define BIT_MASK_RXFILTER_ACTION_1_8822C 0xff
+#define BIT_RXFILTER_ACTION_1_8822C(x)                                         \
+	(((x) & BIT_MASK_RXFILTER_ACTION_1_8822C)                              \
+	 << BIT_SHIFT_RXFILTER_ACTION_1_8822C)
+#define BITS_RXFILTER_ACTION_1_8822C                                           \
+	(BIT_MASK_RXFILTER_ACTION_1_8822C << BIT_SHIFT_RXFILTER_ACTION_1_8822C)
+#define BIT_CLEAR_RXFILTER_ACTION_1_8822C(x)                                   \
+	((x) & (~BITS_RXFILTER_ACTION_1_8822C))
+#define BIT_GET_RXFILTER_ACTION_1_8822C(x)                                     \
+	(((x) >> BIT_SHIFT_RXFILTER_ACTION_1_8822C) &                          \
+	 BIT_MASK_RXFILTER_ACTION_1_8822C)
+#define BIT_SET_RXFILTER_ACTION_1_8822C(x, v)                                  \
+	(BIT_CLEAR_RXFILTER_ACTION_1_8822C(x) | BIT_RXFILTER_ACTION_1_8822C(v))
+
+/* 2 REG_RXFILTER_CATEGORY_2_8822C */
+
+#define BIT_SHIFT_RXFILTER_CATEGORY_2_8822C 0
+#define BIT_MASK_RXFILTER_CATEGORY_2_8822C 0xff
+#define BIT_RXFILTER_CATEGORY_2_8822C(x)                                       \
+	(((x) & BIT_MASK_RXFILTER_CATEGORY_2_8822C)                            \
+	 << BIT_SHIFT_RXFILTER_CATEGORY_2_8822C)
+#define BITS_RXFILTER_CATEGORY_2_8822C                                         \
+	(BIT_MASK_RXFILTER_CATEGORY_2_8822C                                    \
+	 << BIT_SHIFT_RXFILTER_CATEGORY_2_8822C)
+#define BIT_CLEAR_RXFILTER_CATEGORY_2_8822C(x)                                 \
+	((x) & (~BITS_RXFILTER_CATEGORY_2_8822C))
+#define BIT_GET_RXFILTER_CATEGORY_2_8822C(x)                                   \
+	(((x) >> BIT_SHIFT_RXFILTER_CATEGORY_2_8822C) &                        \
+	 BIT_MASK_RXFILTER_CATEGORY_2_8822C)
+#define BIT_SET_RXFILTER_CATEGORY_2_8822C(x, v)                                \
+	(BIT_CLEAR_RXFILTER_CATEGORY_2_8822C(x) |                              \
+	 BIT_RXFILTER_CATEGORY_2_8822C(v))
+
+/* 2 REG_RXFILTER_ACTION_2_8822C */
+
+#define BIT_SHIFT_RXFILTER_ACTION_2_8822C 0
+#define BIT_MASK_RXFILTER_ACTION_2_8822C 0xff
+#define BIT_RXFILTER_ACTION_2_8822C(x)                                         \
+	(((x) & BIT_MASK_RXFILTER_ACTION_2_8822C)                              \
+	 << BIT_SHIFT_RXFILTER_ACTION_2_8822C)
+#define BITS_RXFILTER_ACTION_2_8822C                                           \
+	(BIT_MASK_RXFILTER_ACTION_2_8822C << BIT_SHIFT_RXFILTER_ACTION_2_8822C)
+#define BIT_CLEAR_RXFILTER_ACTION_2_8822C(x)                                   \
+	((x) & (~BITS_RXFILTER_ACTION_2_8822C))
+#define BIT_GET_RXFILTER_ACTION_2_8822C(x)                                     \
+	(((x) >> BIT_SHIFT_RXFILTER_ACTION_2_8822C) &                          \
+	 BIT_MASK_RXFILTER_ACTION_2_8822C)
+#define BIT_SET_RXFILTER_ACTION_2_8822C(x, v)                                  \
+	(BIT_CLEAR_RXFILTER_ACTION_2_8822C(x) | BIT_RXFILTER_ACTION_2_8822C(v))
+
+/* 2 REG_RXFILTER_CATEGORY_3_8822C */
+
+#define BIT_SHIFT_RXFILTER_CATEGORY_3_8822C 0
+#define BIT_MASK_RXFILTER_CATEGORY_3_8822C 0xff
+#define BIT_RXFILTER_CATEGORY_3_8822C(x)                                       \
+	(((x) & BIT_MASK_RXFILTER_CATEGORY_3_8822C)                            \
+	 << BIT_SHIFT_RXFILTER_CATEGORY_3_8822C)
+#define BITS_RXFILTER_CATEGORY_3_8822C                                         \
+	(BIT_MASK_RXFILTER_CATEGORY_3_8822C                                    \
+	 << BIT_SHIFT_RXFILTER_CATEGORY_3_8822C)
+#define BIT_CLEAR_RXFILTER_CATEGORY_3_8822C(x)                                 \
+	((x) & (~BITS_RXFILTER_CATEGORY_3_8822C))
+#define BIT_GET_RXFILTER_CATEGORY_3_8822C(x)                                   \
+	(((x) >> BIT_SHIFT_RXFILTER_CATEGORY_3_8822C) &                        \
+	 BIT_MASK_RXFILTER_CATEGORY_3_8822C)
+#define BIT_SET_RXFILTER_CATEGORY_3_8822C(x, v)                                \
+	(BIT_CLEAR_RXFILTER_CATEGORY_3_8822C(x) |                              \
+	 BIT_RXFILTER_CATEGORY_3_8822C(v))
+
+/* 2 REG_RXFILTER_ACTION_3_8822C */
+
+#define BIT_SHIFT_RXFILTER_ACTION_3_8822C 0
+#define BIT_MASK_RXFILTER_ACTION_3_8822C 0xff
+#define BIT_RXFILTER_ACTION_3_8822C(x)                                         \
+	(((x) & BIT_MASK_RXFILTER_ACTION_3_8822C)                              \
+	 << BIT_SHIFT_RXFILTER_ACTION_3_8822C)
+#define BITS_RXFILTER_ACTION_3_8822C                                           \
+	(BIT_MASK_RXFILTER_ACTION_3_8822C << BIT_SHIFT_RXFILTER_ACTION_3_8822C)
+#define BIT_CLEAR_RXFILTER_ACTION_3_8822C(x)                                   \
+	((x) & (~BITS_RXFILTER_ACTION_3_8822C))
+#define BIT_GET_RXFILTER_ACTION_3_8822C(x)                                     \
+	(((x) >> BIT_SHIFT_RXFILTER_ACTION_3_8822C) &                          \
+	 BIT_MASK_RXFILTER_ACTION_3_8822C)
+#define BIT_SET_RXFILTER_ACTION_3_8822C(x, v)                                  \
+	(BIT_CLEAR_RXFILTER_ACTION_3_8822C(x) | BIT_RXFILTER_ACTION_3_8822C(v))
+
+/* 2 REG_RXFLTMAP3_8822C (RX FILTER MAP GROUP 3) */
+#define BIT_MGTFLT15EN_FW_8822C BIT(15)
+#define BIT_MGTFLT14EN_FW_8822C BIT(14)
+#define BIT_MGTFLT13EN_FW_8822C BIT(13)
+#define BIT_MGTFLT12EN_FW_8822C BIT(12)
+#define BIT_MGTFLT11EN_FW_8822C BIT(11)
+#define BIT_MGTFLT10EN_FW_8822C BIT(10)
+#define BIT_MGTFLT9EN_FW_8822C BIT(9)
+#define BIT_MGTFLT8EN_FW_8822C BIT(8)
+#define BIT_MGTFLT7EN_FW_8822C BIT(7)
+#define BIT_MGTFLT6EN_FW_8822C BIT(6)
+#define BIT_MGTFLT5EN_FW_8822C BIT(5)
+#define BIT_MGTFLT4EN_FW_8822C BIT(4)
+#define BIT_MGTFLT3EN_FW_8822C BIT(3)
+#define BIT_MGTFLT2EN_FW_8822C BIT(2)
+#define BIT_MGTFLT1EN_FW_8822C BIT(1)
+#define BIT_MGTFLT0EN_FW_8822C BIT(0)
+
+/* 2 REG_RXFLTMAP4_8822C (RX FILTER MAP GROUP 4) */
+#define BIT_CTRLFLT15EN_FW_8822C BIT(15)
+#define BIT_CTRLFLT14EN_FW_8822C BIT(14)
+#define BIT_CTRLFLT13EN_FW_8822C BIT(13)
+#define BIT_CTRLFLT12EN_FW_8822C BIT(12)
+#define BIT_CTRLFLT11EN_FW_8822C BIT(11)
+#define BIT_CTRLFLT10EN_FW_8822C BIT(10)
+#define BIT_CTRLFLT9EN_FW_8822C BIT(9)
+#define BIT_CTRLFLT8EN_FW_8822C BIT(8)
+#define BIT_CTRLFLT7EN_FW_8822C BIT(7)
+#define BIT_CTRLFLT6EN_FW_8822C BIT(6)
+#define BIT_CTRLFLT5EN_FW_8822C BIT(5)
+#define BIT_CTRLFLT4EN_FW_8822C BIT(4)
+#define BIT_CTRLFLT3EN_FW_8822C BIT(3)
+#define BIT_CTRLFLT2EN_FW_8822C BIT(2)
+#define BIT_CTRLFLT1EN_FW_8822C BIT(1)
+#define BIT_CTRLFLT0EN_FW_8822C BIT(0)
+
+/* 2 REG_RXFLTMAP5_8822C (RX FILTER MAP GROUP 5) */
+#define BIT_DATAFLT15EN_FW_8822C BIT(15)
+#define BIT_DATAFLT14EN_FW_8822C BIT(14)
+#define BIT_DATAFLT13EN_FW_8822C BIT(13)
+#define BIT_DATAFLT12EN_FW_8822C BIT(12)
+#define BIT_DATAFLT11EN_FW_8822C BIT(11)
+#define BIT_DATAFLT10EN_FW_8822C BIT(10)
+#define BIT_DATAFLT9EN_FW_8822C BIT(9)
+#define BIT_DATAFLT8EN_FW_8822C BIT(8)
+#define BIT_DATAFLT7EN_FW_8822C BIT(7)
+#define BIT_DATAFLT6EN_FW_8822C BIT(6)
+#define BIT_DATAFLT5EN_FW_8822C BIT(5)
+#define BIT_DATAFLT4EN_FW_8822C BIT(4)
+#define BIT_DATAFLT3EN_FW_8822C BIT(3)
+#define BIT_DATAFLT2EN_FW_8822C BIT(2)
+#define BIT_DATAFLT1EN_FW_8822C BIT(1)
+#define BIT_DATAFLT0EN_FW_8822C BIT(0)
+
+/* 2 REG_RXFLTMAP6_8822C (RX FILTER MAP GROUP 6) */
+#define BIT_ACTIONFLT15EN_FW_8822C BIT(15)
+#define BIT_ACTIONFLT14EN_FW_8822C BIT(14)
+#define BIT_ACTIONFLT13EN_FW_8822C BIT(13)
+#define BIT_ACTIONFLT12EN_FW_8822C BIT(12)
+#define BIT_ACTIONFLT11EN_FW_8822C BIT(11)
+#define BIT_ACTIONFLT10EN_FW_8822C BIT(10)
+#define BIT_ACTIONFLT9EN_FW_8822C BIT(9)
+#define BIT_ACTIONFLT8EN_FW_8822C BIT(8)
+#define BIT_ACTIONFLT7EN_FW_8822C BIT(7)
+#define BIT_ACTIONFLT6EN_FW_8822C BIT(6)
+#define BIT_ACTIONFLT5EN_FW_8822C BIT(5)
+#define BIT_ACTIONFLT4EN_FW_8822C BIT(4)
+#define BIT_ACTIONFLT3EN_FW_8822C BIT(3)
+#define BIT_ACTIONFLT2EN_FW_8822C BIT(2)
+#define BIT_ACTIONFLT1EN_FW_8822C BIT(1)
+#define BIT_ACTIONFLT0EN_FW_8822C BIT(0)
+
+/* 2 REG_WOW_CTRL_8822C (WAKE ON WLAN CONTROL REGISTER) */
+
+#define BIT_SHIFT_PSF_BSSIDSEL_B2B1_8822C 6
+#define BIT_MASK_PSF_BSSIDSEL_B2B1_8822C 0x3
+#define BIT_PSF_BSSIDSEL_B2B1_8822C(x)                                         \
+	(((x) & BIT_MASK_PSF_BSSIDSEL_B2B1_8822C)                              \
+	 << BIT_SHIFT_PSF_BSSIDSEL_B2B1_8822C)
+#define BITS_PSF_BSSIDSEL_B2B1_8822C                                           \
+	(BIT_MASK_PSF_BSSIDSEL_B2B1_8822C << BIT_SHIFT_PSF_BSSIDSEL_B2B1_8822C)
+#define BIT_CLEAR_PSF_BSSIDSEL_B2B1_8822C(x)                                   \
+	((x) & (~BITS_PSF_BSSIDSEL_B2B1_8822C))
+#define BIT_GET_PSF_BSSIDSEL_B2B1_8822C(x)                                     \
+	(((x) >> BIT_SHIFT_PSF_BSSIDSEL_B2B1_8822C) &                          \
+	 BIT_MASK_PSF_BSSIDSEL_B2B1_8822C)
+#define BIT_SET_PSF_BSSIDSEL_B2B1_8822C(x, v)                                  \
+	(BIT_CLEAR_PSF_BSSIDSEL_B2B1_8822C(x) | BIT_PSF_BSSIDSEL_B2B1_8822C(v))
+
+#define BIT_WOWHCI_8822C BIT(5)
+#define BIT_PSF_BSSIDSEL_B0_8822C BIT(4)
+#define BIT_UWF_8822C BIT(3)
+#define BIT_MAGIC_8822C BIT(2)
+#define BIT_WOWEN_8822C BIT(1)
+#define BIT_FORCE_WAKEUP_8822C BIT(0)
+
+/* 2 REG_NAN_RX_TSF_FILTER_8822C(NAN_RX_TSF_ADDRESS_FILTER) */
+#define BIT_CHK_TSF_TA_8822C BIT(2)
+#define BIT_CHK_TSF_CBSSID_8822C BIT(1)
+#define BIT_CHK_TSF_EN_8822C BIT(0)
+
+/* 2 REG_PS_RX_INFO_8822C (POWER SAVE RX INFORMATION REGISTER) */
+
+#define BIT_SHIFT_PORTSEL__PS_RX_INFO_8822C 5
+#define BIT_MASK_PORTSEL__PS_RX_INFO_8822C 0x7
+#define BIT_PORTSEL__PS_RX_INFO_8822C(x)                                       \
+	(((x) & BIT_MASK_PORTSEL__PS_RX_INFO_8822C)                            \
+	 << BIT_SHIFT_PORTSEL__PS_RX_INFO_8822C)
+#define BITS_PORTSEL__PS_RX_INFO_8822C                                         \
+	(BIT_MASK_PORTSEL__PS_RX_INFO_8822C                                    \
+	 << BIT_SHIFT_PORTSEL__PS_RX_INFO_8822C)
+#define BIT_CLEAR_PORTSEL__PS_RX_INFO_8822C(x)                                 \
+	((x) & (~BITS_PORTSEL__PS_RX_INFO_8822C))
+#define BIT_GET_PORTSEL__PS_RX_INFO_8822C(x)                                   \
+	(((x) >> BIT_SHIFT_PORTSEL__PS_RX_INFO_8822C) &                        \
+	 BIT_MASK_PORTSEL__PS_RX_INFO_8822C)
+#define BIT_SET_PORTSEL__PS_RX_INFO_8822C(x, v)                                \
+	(BIT_CLEAR_PORTSEL__PS_RX_INFO_8822C(x) |                              \
+	 BIT_PORTSEL__PS_RX_INFO_8822C(v))
+
+#define BIT_RXCTRLIN0_8822C BIT(4)
+#define BIT_RXMGTIN0_8822C BIT(3)
+#define BIT_RXDATAIN2_8822C BIT(2)
+#define BIT_RXDATAIN1_8822C BIT(1)
+#define BIT_RXDATAIN0_8822C BIT(0)
+
+/* 2 REG_WMMPS_UAPSD_TID_8822C (WMM POWER SAVE UAPSD TID REGISTER) */
+#define BIT_WMMPS_UAPSD_TID7_8822C BIT(7)
+#define BIT_WMMPS_UAPSD_TID6_8822C BIT(6)
+#define BIT_WMMPS_UAPSD_TID5_8822C BIT(5)
+#define BIT_WMMPS_UAPSD_TID4_8822C BIT(4)
+#define BIT_WMMPS_UAPSD_TID3_8822C BIT(3)
+#define BIT_WMMPS_UAPSD_TID2_8822C BIT(2)
+#define BIT_WMMPS_UAPSD_TID1_8822C BIT(1)
+#define BIT_WMMPS_UAPSD_TID0_8822C BIT(0)
+
+/* 2 REG_LPNAV_CTRL_8822C (LOW POWER NAV CONTROL REGISTER) */
+
+/* 2 REG_WKFMCAM_CMD_8822C (WAKEUP FRAME CAM COMMAND REGISTER) */
+#define BIT_WKFCAM_POLLING_V1_8822C BIT(31)
+#define BIT_WKFCAM_CLR_V1_8822C BIT(30)
+#define BIT_WKFCAM_WE_8822C BIT(16)
+
+#define BIT_SHIFT_WKFCAM_ADDR_V2_8822C 8
+#define BIT_MASK_WKFCAM_ADDR_V2_8822C 0xff
+#define BIT_WKFCAM_ADDR_V2_8822C(x)                                            \
+	(((x) & BIT_MASK_WKFCAM_ADDR_V2_8822C)                                 \
+	 << BIT_SHIFT_WKFCAM_ADDR_V2_8822C)
+#define BITS_WKFCAM_ADDR_V2_8822C                                              \
+	(BIT_MASK_WKFCAM_ADDR_V2_8822C << BIT_SHIFT_WKFCAM_ADDR_V2_8822C)
+#define BIT_CLEAR_WKFCAM_ADDR_V2_8822C(x) ((x) & (~BITS_WKFCAM_ADDR_V2_8822C))
+#define BIT_GET_WKFCAM_ADDR_V2_8822C(x)                                        \
+	(((x) >> BIT_SHIFT_WKFCAM_ADDR_V2_8822C) &                             \
+	 BIT_MASK_WKFCAM_ADDR_V2_8822C)
+#define BIT_SET_WKFCAM_ADDR_V2_8822C(x, v)                                     \
+	(BIT_CLEAR_WKFCAM_ADDR_V2_8822C(x) | BIT_WKFCAM_ADDR_V2_8822C(v))
+
+#define BIT_SHIFT_WKFCAM_CAM_NUM_V1_8822C 0
+#define BIT_MASK_WKFCAM_CAM_NUM_V1_8822C 0xff
+#define BIT_WKFCAM_CAM_NUM_V1_8822C(x)                                         \
+	(((x) & BIT_MASK_WKFCAM_CAM_NUM_V1_8822C)                              \
+	 << BIT_SHIFT_WKFCAM_CAM_NUM_V1_8822C)
+#define BITS_WKFCAM_CAM_NUM_V1_8822C                                           \
+	(BIT_MASK_WKFCAM_CAM_NUM_V1_8822C << BIT_SHIFT_WKFCAM_CAM_NUM_V1_8822C)
+#define BIT_CLEAR_WKFCAM_CAM_NUM_V1_8822C(x)                                   \
+	((x) & (~BITS_WKFCAM_CAM_NUM_V1_8822C))
+#define BIT_GET_WKFCAM_CAM_NUM_V1_8822C(x)                                     \
+	(((x) >> BIT_SHIFT_WKFCAM_CAM_NUM_V1_8822C) &                          \
+	 BIT_MASK_WKFCAM_CAM_NUM_V1_8822C)
+#define BIT_SET_WKFCAM_CAM_NUM_V1_8822C(x, v)                                  \
+	(BIT_CLEAR_WKFCAM_CAM_NUM_V1_8822C(x) | BIT_WKFCAM_CAM_NUM_V1_8822C(v))
+
+/* 2 REG_WKFMCAM_RWD_8822C (WAKEUP FRAME READ/WRITE DATA) */
+
+#define BIT_SHIFT_WKFMCAM_RWD_8822C 0
+#define BIT_MASK_WKFMCAM_RWD_8822C 0xffffffffL
+#define BIT_WKFMCAM_RWD_8822C(x)                                               \
+	(((x) & BIT_MASK_WKFMCAM_RWD_8822C) << BIT_SHIFT_WKFMCAM_RWD_8822C)
+#define BITS_WKFMCAM_RWD_8822C                                                 \
+	(BIT_MASK_WKFMCAM_RWD_8822C << BIT_SHIFT_WKFMCAM_RWD_8822C)
+#define BIT_CLEAR_WKFMCAM_RWD_8822C(x) ((x) & (~BITS_WKFMCAM_RWD_8822C))
+#define BIT_GET_WKFMCAM_RWD_8822C(x)                                           \
+	(((x) >> BIT_SHIFT_WKFMCAM_RWD_8822C) & BIT_MASK_WKFMCAM_RWD_8822C)
+#define BIT_SET_WKFMCAM_RWD_8822C(x, v)                                        \
+	(BIT_CLEAR_WKFMCAM_RWD_8822C(x) | BIT_WKFMCAM_RWD_8822C(v))
+
+/* 2 REG_RXFLTMAP0_8822C (RX FILTER MAP GROUP 0) */
+#define BIT_MGTFLT15EN_8822C BIT(15)
+#define BIT_MGTFLT14EN_8822C BIT(14)
+#define BIT_MGTFLT13EN_8822C BIT(13)
+#define BIT_MGTFLT12EN_8822C BIT(12)
+#define BIT_MGTFLT11EN_8822C BIT(11)
+#define BIT_MGTFLT10EN_8822C BIT(10)
+#define BIT_MGTFLT9EN_8822C BIT(9)
+#define BIT_MGTFLT8EN_8822C BIT(8)
+#define BIT_MGTFLT7EN_8822C BIT(7)
+#define BIT_MGTFLT6EN_8822C BIT(6)
+#define BIT_MGTFLT5EN_8822C BIT(5)
+#define BIT_MGTFLT4EN_8822C BIT(4)
+#define BIT_MGTFLT3EN_8822C BIT(3)
+#define BIT_MGTFLT2EN_8822C BIT(2)
+#define BIT_MGTFLT1EN_8822C BIT(1)
+#define BIT_MGTFLT0EN_8822C BIT(0)
+
+/* 2 REG_RXFLTMAP1_8822C (RX FILTER MAP GROUP 1) */
+#define BIT_CTRLFLT15EN_8822C BIT(15)
+#define BIT_CTRLFLT14EN_8822C BIT(14)
+#define BIT_CTRLFLT13EN_8822C BIT(13)
+#define BIT_CTRLFLT12EN_8822C BIT(12)
+#define BIT_CTRLFLT11EN_8822C BIT(11)
+#define BIT_CTRLFLT10EN_8822C BIT(10)
+#define BIT_CTRLFLT9EN_8822C BIT(9)
+#define BIT_CTRLFLT8EN_8822C BIT(8)
+#define BIT_CTRLFLT7EN_8822C BIT(7)
+#define BIT_CTRLFLT6EN_8822C BIT(6)
+#define BIT_CTRLFLT5EN_8822C BIT(5)
+#define BIT_CTRLFLT4EN_8822C BIT(4)
+#define BIT_CTRLFLT3EN_8822C BIT(3)
+#define BIT_CTRLFLT2EN_8822C BIT(2)
+#define BIT_CTRLFLT1EN_8822C BIT(1)
+#define BIT_CTRLFLT0EN_8822C BIT(0)
+
+/* 2 REG_RXFLTMAP2_8822C (RX FILTER MAP GROUP 2) */
+#define BIT_DATAFLT15EN_8822C BIT(15)
+#define BIT_DATAFLT14EN_8822C BIT(14)
+#define BIT_DATAFLT13EN_8822C BIT(13)
+#define BIT_DATAFLT12EN_8822C BIT(12)
+#define BIT_DATAFLT11EN_8822C BIT(11)
+#define BIT_DATAFLT10EN_8822C BIT(10)
+#define BIT_DATAFLT9EN_8822C BIT(9)
+#define BIT_DATAFLT8EN_8822C BIT(8)
+#define BIT_DATAFLT7EN_8822C BIT(7)
+#define BIT_DATAFLT6EN_8822C BIT(6)
+#define BIT_DATAFLT5EN_8822C BIT(5)
+#define BIT_DATAFLT4EN_8822C BIT(4)
+#define BIT_DATAFLT3EN_8822C BIT(3)
+#define BIT_DATAFLT2EN_8822C BIT(2)
+#define BIT_DATAFLT1EN_8822C BIT(1)
+#define BIT_DATAFLT0EN_8822C BIT(0)
+
+/* 2 REG_RSVD_8822C */
+
+/* 2 REG_BCN_PSR_RPT_8822C (BEACON PARSER REPORT REGISTER) */
+
+#define BIT_SHIFT_DTIM_CNT_8822C 24
+#define BIT_MASK_DTIM_CNT_8822C 0xff
+#define BIT_DTIM_CNT_8822C(x)                                                  \
+	(((x) & BIT_MASK_DTIM_CNT_8822C) << BIT_SHIFT_DTIM_CNT_8822C)
+#define BITS_DTIM_CNT_8822C                                                    \
+	(BIT_MASK_DTIM_CNT_8822C << BIT_SHIFT_DTIM_CNT_8822C)
+#define BIT_CLEAR_DTIM_CNT_8822C(x) ((x) & (~BITS_DTIM_CNT_8822C))
+#define BIT_GET_DTIM_CNT_8822C(x)                                              \
+	(((x) >> BIT_SHIFT_DTIM_CNT_8822C) & BIT_MASK_DTIM_CNT_8822C)
+#define BIT_SET_DTIM_CNT_8822C(x, v)                                           \
+	(BIT_CLEAR_DTIM_CNT_8822C(x) | BIT_DTIM_CNT_8822C(v))
+
+#define BIT_SHIFT_DTIM_PERIOD_8822C 16
+#define BIT_MASK_DTIM_PERIOD_8822C 0xff
+#define BIT_DTIM_PERIOD_8822C(x)                                               \
+	(((x) & BIT_MASK_DTIM_PERIOD_8822C) << BIT_SHIFT_DTIM_PERIOD_8822C)
+#define BITS_DTIM_PERIOD_8822C                                                 \
+	(BIT_MASK_DTIM_PERIOD_8822C << BIT_SHIFT_DTIM_PERIOD_8822C)
+#define BIT_CLEAR_DTIM_PERIOD_8822C(x) ((x) & (~BITS_DTIM_PERIOD_8822C))
+#define BIT_GET_DTIM_PERIOD_8822C(x)                                           \
+	(((x) >> BIT_SHIFT_DTIM_PERIOD_8822C) & BIT_MASK_DTIM_PERIOD_8822C)
+#define BIT_SET_DTIM_PERIOD_8822C(x, v)                                        \
+	(BIT_CLEAR_DTIM_PERIOD_8822C(x) | BIT_DTIM_PERIOD_8822C(v))
+
+#define BIT_DTIM_8822C BIT(15)
+#define BIT_TIM_8822C BIT(14)
+#define BIT_RPT_VALID_8822C BIT(13)
+
+#define BIT_SHIFT_PS_AID_0_8822C 0
+#define BIT_MASK_PS_AID_0_8822C 0x7ff
+#define BIT_PS_AID_0_8822C(x)                                                  \
+	(((x) & BIT_MASK_PS_AID_0_8822C) << BIT_SHIFT_PS_AID_0_8822C)
+#define BITS_PS_AID_0_8822C                                                    \
+	(BIT_MASK_PS_AID_0_8822C << BIT_SHIFT_PS_AID_0_8822C)
+#define BIT_CLEAR_PS_AID_0_8822C(x) ((x) & (~BITS_PS_AID_0_8822C))
+#define BIT_GET_PS_AID_0_8822C(x)                                              \
+	(((x) >> BIT_SHIFT_PS_AID_0_8822C) & BIT_MASK_PS_AID_0_8822C)
+#define BIT_SET_PS_AID_0_8822C(x, v)                                           \
+	(BIT_CLEAR_PS_AID_0_8822C(x) | BIT_PS_AID_0_8822C(v))
+
+/* 2 REG_FLC_RPC_8822C (FW LPS CONDITION -- RX PKT COUNTER) */
+
+#define BIT_SHIFT_FLC_RPC_8822C 0
+#define BIT_MASK_FLC_RPC_8822C 0xff
+#define BIT_FLC_RPC_8822C(x)                                                   \
+	(((x) & BIT_MASK_FLC_RPC_8822C) << BIT_SHIFT_FLC_RPC_8822C)
+#define BITS_FLC_RPC_8822C (BIT_MASK_FLC_RPC_8822C << BIT_SHIFT_FLC_RPC_8822C)
+#define BIT_CLEAR_FLC_RPC_8822C(x) ((x) & (~BITS_FLC_RPC_8822C))
+#define BIT_GET_FLC_RPC_8822C(x)                                               \
+	(((x) >> BIT_SHIFT_FLC_RPC_8822C) & BIT_MASK_FLC_RPC_8822C)
+#define BIT_SET_FLC_RPC_8822C(x, v)                                            \
+	(BIT_CLEAR_FLC_RPC_8822C(x) | BIT_FLC_RPC_8822C(v))
+
+/* 2 REG_FLC_RPCT_8822C (FLC_RPC THRESHOLD) */
+
+#define BIT_SHIFT_FLC_RPCT_8822C 0
+#define BIT_MASK_FLC_RPCT_8822C 0xff
+#define BIT_FLC_RPCT_8822C(x)                                                  \
+	(((x) & BIT_MASK_FLC_RPCT_8822C) << BIT_SHIFT_FLC_RPCT_8822C)
+#define BITS_FLC_RPCT_8822C                                                    \
+	(BIT_MASK_FLC_RPCT_8822C << BIT_SHIFT_FLC_RPCT_8822C)
+#define BIT_CLEAR_FLC_RPCT_8822C(x) ((x) & (~BITS_FLC_RPCT_8822C))
+#define BIT_GET_FLC_RPCT_8822C(x)                                              \
+	(((x) >> BIT_SHIFT_FLC_RPCT_8822C) & BIT_MASK_FLC_RPCT_8822C)
+#define BIT_SET_FLC_RPCT_8822C(x, v)                                           \
+	(BIT_CLEAR_FLC_RPCT_8822C(x) | BIT_FLC_RPCT_8822C(v))
+
+/* 2 REG_FLC_PTS_8822C (PKT TYPE SELECTION OF FLC_RPC T) */
+#define BIT_CMF_8822C BIT(2)
+#define BIT_CCF_8822C BIT(1)
+#define BIT_CDF_8822C BIT(0)
+
+/* 2 REG_FLC_TRPC_8822C (TIMER OF FLC_RPC) */
+#define BIT_FLC_RPCT_V1_8822C BIT(7)
+#define BIT_MODE_8822C BIT(6)
+
+#define BIT_SHIFT_TRPCD_8822C 0
+#define BIT_MASK_TRPCD_8822C 0x3f
+#define BIT_TRPCD_8822C(x)                                                     \
+	(((x) & BIT_MASK_TRPCD_8822C) << BIT_SHIFT_TRPCD_8822C)
+#define BITS_TRPCD_8822C (BIT_MASK_TRPCD_8822C << BIT_SHIFT_TRPCD_8822C)
+#define BIT_CLEAR_TRPCD_8822C(x) ((x) & (~BITS_TRPCD_8822C))
+#define BIT_GET_TRPCD_8822C(x)                                                 \
+	(((x) >> BIT_SHIFT_TRPCD_8822C) & BIT_MASK_TRPCD_8822C)
+#define BIT_SET_TRPCD_8822C(x, v)                                              \
+	(BIT_CLEAR_TRPCD_8822C(x) | BIT_TRPCD_8822C(v))
+
+/* 2 REG_RXPKTMON_CTRL_8822C */
+
+#define BIT_SHIFT_RXBKQPKT_SEQ_8822C 20
+#define BIT_MASK_RXBKQPKT_SEQ_8822C 0xf
+#define BIT_RXBKQPKT_SEQ_8822C(x)                                              \
+	(((x) & BIT_MASK_RXBKQPKT_SEQ_8822C) << BIT_SHIFT_RXBKQPKT_SEQ_8822C)
+#define BITS_RXBKQPKT_SEQ_8822C                                                \
+	(BIT_MASK_RXBKQPKT_SEQ_8822C << BIT_SHIFT_RXBKQPKT_SEQ_8822C)
+#define BIT_CLEAR_RXBKQPKT_SEQ_8822C(x) ((x) & (~BITS_RXBKQPKT_SEQ_8822C))
+#define BIT_GET_RXBKQPKT_SEQ_8822C(x)                                          \
+	(((x) >> BIT_SHIFT_RXBKQPKT_SEQ_8822C) & BIT_MASK_RXBKQPKT_SEQ_8822C)
+#define BIT_SET_RXBKQPKT_SEQ_8822C(x, v)                                       \
+	(BIT_CLEAR_RXBKQPKT_SEQ_8822C(x) | BIT_RXBKQPKT_SEQ_8822C(v))
+
+#define BIT_SHIFT_RXBEQPKT_SEQ_8822C 16
+#define BIT_MASK_RXBEQPKT_SEQ_8822C 0xf
+#define BIT_RXBEQPKT_SEQ_8822C(x)                                              \
+	(((x) & BIT_MASK_RXBEQPKT_SEQ_8822C) << BIT_SHIFT_RXBEQPKT_SEQ_8822C)
+#define BITS_RXBEQPKT_SEQ_8822C                                                \
+	(BIT_MASK_RXBEQPKT_SEQ_8822C << BIT_SHIFT_RXBEQPKT_SEQ_8822C)
+#define BIT_CLEAR_RXBEQPKT_SEQ_8822C(x) ((x) & (~BITS_RXBEQPKT_SEQ_8822C))
+#define BIT_GET_RXBEQPKT_SEQ_8822C(x)                                          \
+	(((x) >> BIT_SHIFT_RXBEQPKT_SEQ_8822C) & BIT_MASK_RXBEQPKT_SEQ_8822C)
+#define BIT_SET_RXBEQPKT_SEQ_8822C(x, v)                                       \
+	(BIT_CLEAR_RXBEQPKT_SEQ_8822C(x) | BIT_RXBEQPKT_SEQ_8822C(v))
+
+#define BIT_SHIFT_RXVIQPKT_SEQ_8822C 12
+#define BIT_MASK_RXVIQPKT_SEQ_8822C 0xf
+#define BIT_RXVIQPKT_SEQ_8822C(x)                                              \
+	(((x) & BIT_MASK_RXVIQPKT_SEQ_8822C) << BIT_SHIFT_RXVIQPKT_SEQ_8822C)
+#define BITS_RXVIQPKT_SEQ_8822C                                                \
+	(BIT_MASK_RXVIQPKT_SEQ_8822C << BIT_SHIFT_RXVIQPKT_SEQ_8822C)
+#define BIT_CLEAR_RXVIQPKT_SEQ_8822C(x) ((x) & (~BITS_RXVIQPKT_SEQ_8822C))
+#define BIT_GET_RXVIQPKT_SEQ_8822C(x)                                          \
+	(((x) >> BIT_SHIFT_RXVIQPKT_SEQ_8822C) & BIT_MASK_RXVIQPKT_SEQ_8822C)
+#define BIT_SET_RXVIQPKT_SEQ_8822C(x, v)                                       \
+	(BIT_CLEAR_RXVIQPKT_SEQ_8822C(x) | BIT_RXVIQPKT_SEQ_8822C(v))
+
+#define BIT_SHIFT_RXVOQPKT_SEQ_8822C 8
+#define BIT_MASK_RXVOQPKT_SEQ_8822C 0xf
+#define BIT_RXVOQPKT_SEQ_8822C(x)                                              \
+	(((x) & BIT_MASK_RXVOQPKT_SEQ_8822C) << BIT_SHIFT_RXVOQPKT_SEQ_8822C)
+#define BITS_RXVOQPKT_SEQ_8822C                                                \
+	(BIT_MASK_RXVOQPKT_SEQ_8822C << BIT_SHIFT_RXVOQPKT_SEQ_8822C)
+#define BIT_CLEAR_RXVOQPKT_SEQ_8822C(x) ((x) & (~BITS_RXVOQPKT_SEQ_8822C))
+#define BIT_GET_RXVOQPKT_SEQ_8822C(x)                                          \
+	(((x) >> BIT_SHIFT_RXVOQPKT_SEQ_8822C) & BIT_MASK_RXVOQPKT_SEQ_8822C)
+#define BIT_SET_RXVOQPKT_SEQ_8822C(x, v)                                       \
+	(BIT_CLEAR_RXVOQPKT_SEQ_8822C(x) | BIT_RXVOQPKT_SEQ_8822C(v))
+
+#define BIT_RXBKQPKT_ERR_8822C BIT(7)
+#define BIT_RXBEQPKT_ERR_8822C BIT(6)
+#define BIT_RXVIQPKT_ERR_8822C BIT(5)
+#define BIT_RXVOQPKT_ERR_8822C BIT(4)
+#define BIT_RXDMA_MON_EN_8822C BIT(2)
+#define BIT_RXPKT_MON_RST_8822C BIT(1)
+#define BIT_RXPKT_MON_EN_8822C BIT(0)
+
+/* 2 REG_STATE_MON_8822C */
+
+#define BIT_SHIFT_STATE_SEL_8822C 24
+#define BIT_MASK_STATE_SEL_8822C 0x1f
+#define BIT_STATE_SEL_8822C(x)                                                 \
+	(((x) & BIT_MASK_STATE_SEL_8822C) << BIT_SHIFT_STATE_SEL_8822C)
+#define BITS_STATE_SEL_8822C                                                   \
+	(BIT_MASK_STATE_SEL_8822C << BIT_SHIFT_STATE_SEL_8822C)
+#define BIT_CLEAR_STATE_SEL_8822C(x) ((x) & (~BITS_STATE_SEL_8822C))
+#define BIT_GET_STATE_SEL_8822C(x)                                             \
+	(((x) >> BIT_SHIFT_STATE_SEL_8822C) & BIT_MASK_STATE_SEL_8822C)
+#define BIT_SET_STATE_SEL_8822C(x, v)                                          \
+	(BIT_CLEAR_STATE_SEL_8822C(x) | BIT_STATE_SEL_8822C(v))
+
+#define BIT_SHIFT_STATE_INFO_8822C 8
+#define BIT_MASK_STATE_INFO_8822C 0xff
+#define BIT_STATE_INFO_8822C(x)                                                \
+	(((x) & BIT_MASK_STATE_INFO_8822C) << BIT_SHIFT_STATE_INFO_8822C)
+#define BITS_STATE_INFO_8822C                                                  \
+	(BIT_MASK_STATE_INFO_8822C << BIT_SHIFT_STATE_INFO_8822C)
+#define BIT_CLEAR_STATE_INFO_8822C(x) ((x) & (~BITS_STATE_INFO_8822C))
+#define BIT_GET_STATE_INFO_8822C(x)                                            \
+	(((x) >> BIT_SHIFT_STATE_INFO_8822C) & BIT_MASK_STATE_INFO_8822C)
+#define BIT_SET_STATE_INFO_8822C(x, v)                                         \
+	(BIT_CLEAR_STATE_INFO_8822C(x) | BIT_STATE_INFO_8822C(v))
+
+#define BIT_UPD_NXT_STATE_8822C BIT(7)
+
+#define BIT_SHIFT_CUR_STATE_8822C 0
+#define BIT_MASK_CUR_STATE_8822C 0x7f
+#define BIT_CUR_STATE_8822C(x)                                                 \
+	(((x) & BIT_MASK_CUR_STATE_8822C) << BIT_SHIFT_CUR_STATE_8822C)
+#define BITS_CUR_STATE_8822C                                                   \
+	(BIT_MASK_CUR_STATE_8822C << BIT_SHIFT_CUR_STATE_8822C)
+#define BIT_CLEAR_CUR_STATE_8822C(x) ((x) & (~BITS_CUR_STATE_8822C))
+#define BIT_GET_CUR_STATE_8822C(x)                                             \
+	(((x) >> BIT_SHIFT_CUR_STATE_8822C) & BIT_MASK_CUR_STATE_8822C)
+#define BIT_SET_CUR_STATE_8822C(x, v)                                          \
+	(BIT_CLEAR_CUR_STATE_8822C(x) | BIT_CUR_STATE_8822C(v))
+
+/* 2 REG_ERROR_MON_8822C */
+#define BIT_CSIRPT_LEN_BB_MORE_THAN_MAC_8822C BIT(23)
+#define BIT_CSI_CHKSUM_ERROR_8822C BIT(22)
+#define BIT_MACRX_ERR_4_8822C BIT(20)
+#define BIT_MACRX_ERR_3_8822C BIT(19)
+#define BIT_MACRX_ERR_2_8822C BIT(18)
+#define BIT_MACRX_ERR_1_8822C BIT(17)
+#define BIT_MACRX_ERR_0_8822C BIT(16)
+#define BIT_WMAC_PRETX_ERRHDL_EN_8822C BIT(15)
+#define BIT_MACTX_ERR_5_8822C BIT(5)
+#define BIT_MACTX_ERR_4_8822C BIT(4)
+#define BIT_MACTX_ERR_3_8822C BIT(3)
+#define BIT_MACTX_ERR_2_8822C BIT(2)
+#define BIT_MACTX_ERR_1_8822C BIT(1)
+#define BIT_MACTX_ERR_0_8822C BIT(0)
+
+/* 2 REG_SEARCH_MACID_8822C */
+#define BIT_EN_TXRPTBUF_CLK_8822C BIT(31)
+
+#define BIT_SHIFT_INFO_INDEX_OFFSET_8822C 16
+#define BIT_MASK_INFO_INDEX_OFFSET_8822C 0x1fff
+#define BIT_INFO_INDEX_OFFSET_8822C(x)                                         \
+	(((x) & BIT_MASK_INFO_INDEX_OFFSET_8822C)                              \
+	 << BIT_SHIFT_INFO_INDEX_OFFSET_8822C)
+#define BITS_INFO_INDEX_OFFSET_8822C                                           \
+	(BIT_MASK_INFO_INDEX_OFFSET_8822C << BIT_SHIFT_INFO_INDEX_OFFSET_8822C)
+#define BIT_CLEAR_INFO_INDEX_OFFSET_8822C(x)                                   \
+	((x) & (~BITS_INFO_INDEX_OFFSET_8822C))
+#define BIT_GET_INFO_INDEX_OFFSET_8822C(x)                                     \
+	(((x) >> BIT_SHIFT_INFO_INDEX_OFFSET_8822C) &                          \
+	 BIT_MASK_INFO_INDEX_OFFSET_8822C)
+#define BIT_SET_INFO_INDEX_OFFSET_8822C(x, v)                                  \
+	(BIT_CLEAR_INFO_INDEX_OFFSET_8822C(x) | BIT_INFO_INDEX_OFFSET_8822C(v))
+
+#define BIT_WMAC_SRCH_FIFOFULL_8822C BIT(15)
+#define BIT_DIS_INFOSRCH_8822C BIT(14)
+
+#define BIT_SHIFT_INFO_ADDR_OFFSET_8822C 0
+#define BIT_MASK_INFO_ADDR_OFFSET_8822C 0x1fff
+#define BIT_INFO_ADDR_OFFSET_8822C(x)                                          \
+	(((x) & BIT_MASK_INFO_ADDR_OFFSET_8822C)                               \
+	 << BIT_SHIFT_INFO_ADDR_OFFSET_8822C)
+#define BITS_INFO_ADDR_OFFSET_8822C                                            \
+	(BIT_MASK_INFO_ADDR_OFFSET_8822C << BIT_SHIFT_INFO_ADDR_OFFSET_8822C)
+#define BIT_CLEAR_INFO_ADDR_OFFSET_8822C(x)                                    \
+	((x) & (~BITS_INFO_ADDR_OFFSET_8822C))
+#define BIT_GET_INFO_ADDR_OFFSET_8822C(x)                                      \
+	(((x) >> BIT_SHIFT_INFO_ADDR_OFFSET_8822C) &                           \
+	 BIT_MASK_INFO_ADDR_OFFSET_8822C)
+#define BIT_SET_INFO_ADDR_OFFSET_8822C(x, v)                                   \
+	(BIT_CLEAR_INFO_ADDR_OFFSET_8822C(x) | BIT_INFO_ADDR_OFFSET_8822C(v))
+
+/* 2 REG_BT_COEX_TABLE_8822C (BT-COEXISTENCE CONTROL REGISTER) */
+
+#define BIT_SHIFT_COEX_TABLE_1_8822C 0
+#define BIT_MASK_COEX_TABLE_1_8822C 0xffffffffL
+#define BIT_COEX_TABLE_1_8822C(x)                                              \
+	(((x) & BIT_MASK_COEX_TABLE_1_8822C) << BIT_SHIFT_COEX_TABLE_1_8822C)
+#define BITS_COEX_TABLE_1_8822C                                                \
+	(BIT_MASK_COEX_TABLE_1_8822C << BIT_SHIFT_COEX_TABLE_1_8822C)
+#define BIT_CLEAR_COEX_TABLE_1_8822C(x) ((x) & (~BITS_COEX_TABLE_1_8822C))
+#define BIT_GET_COEX_TABLE_1_8822C(x)                                          \
+	(((x) >> BIT_SHIFT_COEX_TABLE_1_8822C) & BIT_MASK_COEX_TABLE_1_8822C)
+#define BIT_SET_COEX_TABLE_1_8822C(x, v)                                       \
+	(BIT_CLEAR_COEX_TABLE_1_8822C(x) | BIT_COEX_TABLE_1_8822C(v))
+
+/* 2 REG_BT_COEX_TABLE2_8822C (BT-COEXISTENCE CONTROL REGISTER) */
+
+#define BIT_SHIFT_COEX_TABLE_2_8822C 0
+#define BIT_MASK_COEX_TABLE_2_8822C 0xffffffffL
+#define BIT_COEX_TABLE_2_8822C(x)                                              \
+	(((x) & BIT_MASK_COEX_TABLE_2_8822C) << BIT_SHIFT_COEX_TABLE_2_8822C)
+#define BITS_COEX_TABLE_2_8822C                                                \
+	(BIT_MASK_COEX_TABLE_2_8822C << BIT_SHIFT_COEX_TABLE_2_8822C)
+#define BIT_CLEAR_COEX_TABLE_2_8822C(x) ((x) & (~BITS_COEX_TABLE_2_8822C))
+#define BIT_GET_COEX_TABLE_2_8822C(x)                                          \
+	(((x) >> BIT_SHIFT_COEX_TABLE_2_8822C) & BIT_MASK_COEX_TABLE_2_8822C)
+#define BIT_SET_COEX_TABLE_2_8822C(x, v)                                       \
+	(BIT_CLEAR_COEX_TABLE_2_8822C(x) | BIT_COEX_TABLE_2_8822C(v))
+
+/* 2 REG_BT_COEX_BREAK_TABLE_8822C (BT-COEXISTENCE CONTROL REGISTER) */
+
+#define BIT_SHIFT_BREAK_TABLE_2_8822C 16
+#define BIT_MASK_BREAK_TABLE_2_8822C 0xffff
+#define BIT_BREAK_TABLE_2_8822C(x)                                             \
+	(((x) & BIT_MASK_BREAK_TABLE_2_8822C) << BIT_SHIFT_BREAK_TABLE_2_8822C)
+#define BITS_BREAK_TABLE_2_8822C                                               \
+	(BIT_MASK_BREAK_TABLE_2_8822C << BIT_SHIFT_BREAK_TABLE_2_8822C)
+#define BIT_CLEAR_BREAK_TABLE_2_8822C(x) ((x) & (~BITS_BREAK_TABLE_2_8822C))
+#define BIT_GET_BREAK_TABLE_2_8822C(x)                                         \
+	(((x) >> BIT_SHIFT_BREAK_TABLE_2_8822C) & BIT_MASK_BREAK_TABLE_2_8822C)
+#define BIT_SET_BREAK_TABLE_2_8822C(x, v)                                      \
+	(BIT_CLEAR_BREAK_TABLE_2_8822C(x) | BIT_BREAK_TABLE_2_8822C(v))
+
+#define BIT_SHIFT_BREAK_TABLE_1_8822C 0
+#define BIT_MASK_BREAK_TABLE_1_8822C 0xffff
+#define BIT_BREAK_TABLE_1_8822C(x)                                             \
+	(((x) & BIT_MASK_BREAK_TABLE_1_8822C) << BIT_SHIFT_BREAK_TABLE_1_8822C)
+#define BITS_BREAK_TABLE_1_8822C                                               \
+	(BIT_MASK_BREAK_TABLE_1_8822C << BIT_SHIFT_BREAK_TABLE_1_8822C)
+#define BIT_CLEAR_BREAK_TABLE_1_8822C(x) ((x) & (~BITS_BREAK_TABLE_1_8822C))
+#define BIT_GET_BREAK_TABLE_1_8822C(x)                                         \
+	(((x) >> BIT_SHIFT_BREAK_TABLE_1_8822C) & BIT_MASK_BREAK_TABLE_1_8822C)
+#define BIT_SET_BREAK_TABLE_1_8822C(x, v)                                      \
+	(BIT_CLEAR_BREAK_TABLE_1_8822C(x) | BIT_BREAK_TABLE_1_8822C(v))
+
+/* 2 REG_BT_COEX_TABLE_H_8822C (BT-COEXISTENCE CONTROL REGISTER) */
+#define BIT_PRI_MASK_RX_RESP_V1_8822C BIT(30)
+#define BIT_PRI_MASK_RXOFDM_V1_8822C BIT(29)
+#define BIT_PRI_MASK_RXCCK_V1_8822C BIT(28)
+
+#define BIT_SHIFT_PRI_MASK_TXAC_8822C 21
+#define BIT_MASK_PRI_MASK_TXAC_8822C 0x7f
+#define BIT_PRI_MASK_TXAC_8822C(x)                                             \
+	(((x) & BIT_MASK_PRI_MASK_TXAC_8822C) << BIT_SHIFT_PRI_MASK_TXAC_8822C)
+#define BITS_PRI_MASK_TXAC_8822C                                               \
+	(BIT_MASK_PRI_MASK_TXAC_8822C << BIT_SHIFT_PRI_MASK_TXAC_8822C)
+#define BIT_CLEAR_PRI_MASK_TXAC_8822C(x) ((x) & (~BITS_PRI_MASK_TXAC_8822C))
+#define BIT_GET_PRI_MASK_TXAC_8822C(x)                                         \
+	(((x) >> BIT_SHIFT_PRI_MASK_TXAC_8822C) & BIT_MASK_PRI_MASK_TXAC_8822C)
+#define BIT_SET_PRI_MASK_TXAC_8822C(x, v)                                      \
+	(BIT_CLEAR_PRI_MASK_TXAC_8822C(x) | BIT_PRI_MASK_TXAC_8822C(v))
+
+#define BIT_SHIFT_PRI_MASK_NAV_8822C 13
+#define BIT_MASK_PRI_MASK_NAV_8822C 0xff
+#define BIT_PRI_MASK_NAV_8822C(x)                                              \
+	(((x) & BIT_MASK_PRI_MASK_NAV_8822C) << BIT_SHIFT_PRI_MASK_NAV_8822C)
+#define BITS_PRI_MASK_NAV_8822C                                                \
+	(BIT_MASK_PRI_MASK_NAV_8822C << BIT_SHIFT_PRI_MASK_NAV_8822C)
+#define BIT_CLEAR_PRI_MASK_NAV_8822C(x) ((x) & (~BITS_PRI_MASK_NAV_8822C))
+#define BIT_GET_PRI_MASK_NAV_8822C(x)                                          \
+	(((x) >> BIT_SHIFT_PRI_MASK_NAV_8822C) & BIT_MASK_PRI_MASK_NAV_8822C)
+#define BIT_SET_PRI_MASK_NAV_8822C(x, v)                                       \
+	(BIT_CLEAR_PRI_MASK_NAV_8822C(x) | BIT_PRI_MASK_NAV_8822C(v))
+
+#define BIT_PRI_MASK_CCK_V1_8822C BIT(12)
+#define BIT_PRI_MASK_OFDM_V1_8822C BIT(11)
+#define BIT_PRI_MASK_RTY_V1_8822C BIT(10)
+
+#define BIT_SHIFT_PRI_MASK_NUM_8822C 6
+#define BIT_MASK_PRI_MASK_NUM_8822C 0xf
+#define BIT_PRI_MASK_NUM_8822C(x)                                              \
+	(((x) & BIT_MASK_PRI_MASK_NUM_8822C) << BIT_SHIFT_PRI_MASK_NUM_8822C)
+#define BITS_PRI_MASK_NUM_8822C                                                \
+	(BIT_MASK_PRI_MASK_NUM_8822C << BIT_SHIFT_PRI_MASK_NUM_8822C)
+#define BIT_CLEAR_PRI_MASK_NUM_8822C(x) ((x) & (~BITS_PRI_MASK_NUM_8822C))
+#define BIT_GET_PRI_MASK_NUM_8822C(x)                                          \
+	(((x) >> BIT_SHIFT_PRI_MASK_NUM_8822C) & BIT_MASK_PRI_MASK_NUM_8822C)
+#define BIT_SET_PRI_MASK_NUM_8822C(x, v)                                       \
+	(BIT_CLEAR_PRI_MASK_NUM_8822C(x) | BIT_PRI_MASK_NUM_8822C(v))
+
+#define BIT_SHIFT_PRI_MASK_TYPE_8822C 2
+#define BIT_MASK_PRI_MASK_TYPE_8822C 0xf
+#define BIT_PRI_MASK_TYPE_8822C(x)                                             \
+	(((x) & BIT_MASK_PRI_MASK_TYPE_8822C) << BIT_SHIFT_PRI_MASK_TYPE_8822C)
+#define BITS_PRI_MASK_TYPE_8822C                                               \
+	(BIT_MASK_PRI_MASK_TYPE_8822C << BIT_SHIFT_PRI_MASK_TYPE_8822C)
+#define BIT_CLEAR_PRI_MASK_TYPE_8822C(x) ((x) & (~BITS_PRI_MASK_TYPE_8822C))
+#define BIT_GET_PRI_MASK_TYPE_8822C(x)                                         \
+	(((x) >> BIT_SHIFT_PRI_MASK_TYPE_8822C) & BIT_MASK_PRI_MASK_TYPE_8822C)
+#define BIT_SET_PRI_MASK_TYPE_8822C(x, v)                                      \
+	(BIT_CLEAR_PRI_MASK_TYPE_8822C(x) | BIT_PRI_MASK_TYPE_8822C(v))
+
+#define BIT_OOB_V1_8822C BIT(1)
+#define BIT_ANT_SEL_V1_8822C BIT(0)
+
+/* 2 REG_RXCMD_0_8822C */
+#define BIT_RXCMD_EN_8822C BIT(31)
+
+#define BIT_SHIFT_RXCMD_INFO_8822C 0
+#define BIT_MASK_RXCMD_INFO_8822C 0x7fffffffL
+#define BIT_RXCMD_INFO_8822C(x)                                                \
+	(((x) & BIT_MASK_RXCMD_INFO_8822C) << BIT_SHIFT_RXCMD_INFO_8822C)
+#define BITS_RXCMD_INFO_8822C                                                  \
+	(BIT_MASK_RXCMD_INFO_8822C << BIT_SHIFT_RXCMD_INFO_8822C)
+#define BIT_CLEAR_RXCMD_INFO_8822C(x) ((x) & (~BITS_RXCMD_INFO_8822C))
+#define BIT_GET_RXCMD_INFO_8822C(x)                                            \
+	(((x) >> BIT_SHIFT_RXCMD_INFO_8822C) & BIT_MASK_RXCMD_INFO_8822C)
+#define BIT_SET_RXCMD_INFO_8822C(x, v)                                         \
+	(BIT_CLEAR_RXCMD_INFO_8822C(x) | BIT_RXCMD_INFO_8822C(v))
+
+/* 2 REG_RXCMD_1_8822C */
+
+#define BIT_SHIFT_RXCMD_PRD_8822C 0
+#define BIT_MASK_RXCMD_PRD_8822C 0xffff
+#define BIT_RXCMD_PRD_8822C(x)                                                 \
+	(((x) & BIT_MASK_RXCMD_PRD_8822C) << BIT_SHIFT_RXCMD_PRD_8822C)
+#define BITS_RXCMD_PRD_8822C                                                   \
+	(BIT_MASK_RXCMD_PRD_8822C << BIT_SHIFT_RXCMD_PRD_8822C)
+#define BIT_CLEAR_RXCMD_PRD_8822C(x) ((x) & (~BITS_RXCMD_PRD_8822C))
+#define BIT_GET_RXCMD_PRD_8822C(x)                                             \
+	(((x) >> BIT_SHIFT_RXCMD_PRD_8822C) & BIT_MASK_RXCMD_PRD_8822C)
+#define BIT_SET_RXCMD_PRD_8822C(x, v)                                          \
+	(BIT_CLEAR_RXCMD_PRD_8822C(x) | BIT_RXCMD_PRD_8822C(v))
+
+/* 2 REG_WMAC_RESP_TXINFO_8822C (RESPONSE TXINFO REGISTER) */
+
+#define BIT_SHIFT_WMAC_RESP_MFB_8822C 25
+#define BIT_MASK_WMAC_RESP_MFB_8822C 0x7f
+#define BIT_WMAC_RESP_MFB_8822C(x)                                             \
+	(((x) & BIT_MASK_WMAC_RESP_MFB_8822C) << BIT_SHIFT_WMAC_RESP_MFB_8822C)
+#define BITS_WMAC_RESP_MFB_8822C                                               \
+	(BIT_MASK_WMAC_RESP_MFB_8822C << BIT_SHIFT_WMAC_RESP_MFB_8822C)
+#define BIT_CLEAR_WMAC_RESP_MFB_8822C(x) ((x) & (~BITS_WMAC_RESP_MFB_8822C))
+#define BIT_GET_WMAC_RESP_MFB_8822C(x)                                         \
+	(((x) >> BIT_SHIFT_WMAC_RESP_MFB_8822C) & BIT_MASK_WMAC_RESP_MFB_8822C)
+#define BIT_SET_WMAC_RESP_MFB_8822C(x, v)                                      \
+	(BIT_CLEAR_WMAC_RESP_MFB_8822C(x) | BIT_WMAC_RESP_MFB_8822C(v))
+
+#define BIT_SHIFT_WMAC_ANTINF_SEL_8822C 23
+#define BIT_MASK_WMAC_ANTINF_SEL_8822C 0x3
+#define BIT_WMAC_ANTINF_SEL_8822C(x)                                           \
+	(((x) & BIT_MASK_WMAC_ANTINF_SEL_8822C)                                \
+	 << BIT_SHIFT_WMAC_ANTINF_SEL_8822C)
+#define BITS_WMAC_ANTINF_SEL_8822C                                             \
+	(BIT_MASK_WMAC_ANTINF_SEL_8822C << BIT_SHIFT_WMAC_ANTINF_SEL_8822C)
+#define BIT_CLEAR_WMAC_ANTINF_SEL_8822C(x) ((x) & (~BITS_WMAC_ANTINF_SEL_8822C))
+#define BIT_GET_WMAC_ANTINF_SEL_8822C(x)                                       \
+	(((x) >> BIT_SHIFT_WMAC_ANTINF_SEL_8822C) &                            \
+	 BIT_MASK_WMAC_ANTINF_SEL_8822C)
+#define BIT_SET_WMAC_ANTINF_SEL_8822C(x, v)                                    \
+	(BIT_CLEAR_WMAC_ANTINF_SEL_8822C(x) | BIT_WMAC_ANTINF_SEL_8822C(v))
+
+#define BIT_SHIFT_WMAC_ANTSEL_SEL_8822C 21
+#define BIT_MASK_WMAC_ANTSEL_SEL_8822C 0x3
+#define BIT_WMAC_ANTSEL_SEL_8822C(x)                                           \
+	(((x) & BIT_MASK_WMAC_ANTSEL_SEL_8822C)                                \
+	 << BIT_SHIFT_WMAC_ANTSEL_SEL_8822C)
+#define BITS_WMAC_ANTSEL_SEL_8822C                                             \
+	(BIT_MASK_WMAC_ANTSEL_SEL_8822C << BIT_SHIFT_WMAC_ANTSEL_SEL_8822C)
+#define BIT_CLEAR_WMAC_ANTSEL_SEL_8822C(x) ((x) & (~BITS_WMAC_ANTSEL_SEL_8822C))
+#define BIT_GET_WMAC_ANTSEL_SEL_8822C(x)                                       \
+	(((x) >> BIT_SHIFT_WMAC_ANTSEL_SEL_8822C) &                            \
+	 BIT_MASK_WMAC_ANTSEL_SEL_8822C)
+#define BIT_SET_WMAC_ANTSEL_SEL_8822C(x, v)                                    \
+	(BIT_CLEAR_WMAC_ANTSEL_SEL_8822C(x) | BIT_WMAC_ANTSEL_SEL_8822C(v))
+
+#define BIT_SHIFT_WMAC_RESP_TXPOWER_OFFSET_TYPE_8822C 18
+#define BIT_MASK_WMAC_RESP_TXPOWER_OFFSET_TYPE_8822C 0x3
+#define BIT_WMAC_RESP_TXPOWER_OFFSET_TYPE_8822C(x)                             \
+	(((x) & BIT_MASK_WMAC_RESP_TXPOWER_OFFSET_TYPE_8822C)                  \
+	 << BIT_SHIFT_WMAC_RESP_TXPOWER_OFFSET_TYPE_8822C)
+#define BITS_WMAC_RESP_TXPOWER_OFFSET_TYPE_8822C                               \
+	(BIT_MASK_WMAC_RESP_TXPOWER_OFFSET_TYPE_8822C                          \
+	 << BIT_SHIFT_WMAC_RESP_TXPOWER_OFFSET_TYPE_8822C)
+#define BIT_CLEAR_WMAC_RESP_TXPOWER_OFFSET_TYPE_8822C(x)                       \
+	((x) & (~BITS_WMAC_RESP_TXPOWER_OFFSET_TYPE_8822C))
+#define BIT_GET_WMAC_RESP_TXPOWER_OFFSET_TYPE_8822C(x)                         \
+	(((x) >> BIT_SHIFT_WMAC_RESP_TXPOWER_OFFSET_TYPE_8822C) &              \
+	 BIT_MASK_WMAC_RESP_TXPOWER_OFFSET_TYPE_8822C)
+#define BIT_SET_WMAC_RESP_TXPOWER_OFFSET_TYPE_8822C(x, v)                      \
+	(BIT_CLEAR_WMAC_RESP_TXPOWER_OFFSET_TYPE_8822C(x) |                    \
+	 BIT_WMAC_RESP_TXPOWER_OFFSET_TYPE_8822C(v))
+
+#define BIT_SHIFT_WMAC_RESP_TXANT_V1_8822C 6
+#define BIT_MASK_WMAC_RESP_TXANT_V1_8822C 0xfff
+#define BIT_WMAC_RESP_TXANT_V1_8822C(x)                                        \
+	(((x) & BIT_MASK_WMAC_RESP_TXANT_V1_8822C)                             \
+	 << BIT_SHIFT_WMAC_RESP_TXANT_V1_8822C)
+#define BITS_WMAC_RESP_TXANT_V1_8822C                                          \
+	(BIT_MASK_WMAC_RESP_TXANT_V1_8822C                                     \
+	 << BIT_SHIFT_WMAC_RESP_TXANT_V1_8822C)
+#define BIT_CLEAR_WMAC_RESP_TXANT_V1_8822C(x)                                  \
+	((x) & (~BITS_WMAC_RESP_TXANT_V1_8822C))
+#define BIT_GET_WMAC_RESP_TXANT_V1_8822C(x)                                    \
+	(((x) >> BIT_SHIFT_WMAC_RESP_TXANT_V1_8822C) &                         \
+	 BIT_MASK_WMAC_RESP_TXANT_V1_8822C)
+#define BIT_SET_WMAC_RESP_TXANT_V1_8822C(x, v)                                 \
+	(BIT_CLEAR_WMAC_RESP_TXANT_V1_8822C(x) |                               \
+	 BIT_WMAC_RESP_TXANT_V1_8822C(v))
+
+/* 2 REG_BBPSF_CTRL_8822C */
+#define BIT_CTL_IDLE_CLR_CSI_RPT_8822C BIT(31)
+#define BIT_WMAC_USE_NDPARATE_8822C BIT(30)
+
+#define BIT_SHIFT_WMAC_CSI_RATE_8822C 24
+#define BIT_MASK_WMAC_CSI_RATE_8822C 0x3f
+#define BIT_WMAC_CSI_RATE_8822C(x)                                             \
+	(((x) & BIT_MASK_WMAC_CSI_RATE_8822C) << BIT_SHIFT_WMAC_CSI_RATE_8822C)
+#define BITS_WMAC_CSI_RATE_8822C                                               \
+	(BIT_MASK_WMAC_CSI_RATE_8822C << BIT_SHIFT_WMAC_CSI_RATE_8822C)
+#define BIT_CLEAR_WMAC_CSI_RATE_8822C(x) ((x) & (~BITS_WMAC_CSI_RATE_8822C))
+#define BIT_GET_WMAC_CSI_RATE_8822C(x)                                         \
+	(((x) >> BIT_SHIFT_WMAC_CSI_RATE_8822C) & BIT_MASK_WMAC_CSI_RATE_8822C)
+#define BIT_SET_WMAC_CSI_RATE_8822C(x, v)                                      \
+	(BIT_CLEAR_WMAC_CSI_RATE_8822C(x) | BIT_WMAC_CSI_RATE_8822C(v))
+
+#define BIT_SHIFT_WMAC_RESP_TXRATE_8822C 16
+#define BIT_MASK_WMAC_RESP_TXRATE_8822C 0xff
+#define BIT_WMAC_RESP_TXRATE_8822C(x)                                          \
+	(((x) & BIT_MASK_WMAC_RESP_TXRATE_8822C)                               \
+	 << BIT_SHIFT_WMAC_RESP_TXRATE_8822C)
+#define BITS_WMAC_RESP_TXRATE_8822C                                            \
+	(BIT_MASK_WMAC_RESP_TXRATE_8822C << BIT_SHIFT_WMAC_RESP_TXRATE_8822C)
+#define BIT_CLEAR_WMAC_RESP_TXRATE_8822C(x)                                    \
+	((x) & (~BITS_WMAC_RESP_TXRATE_8822C))
+#define BIT_GET_WMAC_RESP_TXRATE_8822C(x)                                      \
+	(((x) >> BIT_SHIFT_WMAC_RESP_TXRATE_8822C) &                           \
+	 BIT_MASK_WMAC_RESP_TXRATE_8822C)
+#define BIT_SET_WMAC_RESP_TXRATE_8822C(x, v)                                   \
+	(BIT_CLEAR_WMAC_RESP_TXRATE_8822C(x) | BIT_WMAC_RESP_TXRATE_8822C(v))
+
+#define BIT_SHIFT_CSI_RSC_8822C 13
+#define BIT_MASK_CSI_RSC_8822C 0x3
+#define BIT_CSI_RSC_8822C(x)                                                   \
+	(((x) & BIT_MASK_CSI_RSC_8822C) << BIT_SHIFT_CSI_RSC_8822C)
+#define BITS_CSI_RSC_8822C (BIT_MASK_CSI_RSC_8822C << BIT_SHIFT_CSI_RSC_8822C)
+#define BIT_CLEAR_CSI_RSC_8822C(x) ((x) & (~BITS_CSI_RSC_8822C))
+#define BIT_GET_CSI_RSC_8822C(x)                                               \
+	(((x) >> BIT_SHIFT_CSI_RSC_8822C) & BIT_MASK_CSI_RSC_8822C)
+#define BIT_SET_CSI_RSC_8822C(x, v)                                            \
+	(BIT_CLEAR_CSI_RSC_8822C(x) | BIT_CSI_RSC_8822C(v))
+
+#define BIT_CSI_GID_SEL_8822C BIT(12)
+#define BIT_NDPVLD_PROTECT_RDRDY_DIS_8822C BIT(9)
+#define BIT_RDCSI_EMPTY_APPZERO_8822C BIT(8)
+#define BIT_CSI_RATE_FB_EN_8822C BIT(7)
+#define BIT_RXFIFO_WRPTR_WO_CHKSUM_8822C BIT(6)
+
+/* 2 REG_P2P_RX_BCN_NOA_8822C (P2P RX BEACON NOA REGISTER) */
+#define BIT_NOA_PARSER_EN_8822C BIT(15)
+
+#define BIT_SHIFT_BSSID_SEL_V1_8822C 12
+#define BIT_MASK_BSSID_SEL_V1_8822C 0x7
+#define BIT_BSSID_SEL_V1_8822C(x)                                              \
+	(((x) & BIT_MASK_BSSID_SEL_V1_8822C) << BIT_SHIFT_BSSID_SEL_V1_8822C)
+#define BITS_BSSID_SEL_V1_8822C                                                \
+	(BIT_MASK_BSSID_SEL_V1_8822C << BIT_SHIFT_BSSID_SEL_V1_8822C)
+#define BIT_CLEAR_BSSID_SEL_V1_8822C(x) ((x) & (~BITS_BSSID_SEL_V1_8822C))
+#define BIT_GET_BSSID_SEL_V1_8822C(x)                                          \
+	(((x) >> BIT_SHIFT_BSSID_SEL_V1_8822C) & BIT_MASK_BSSID_SEL_V1_8822C)
+#define BIT_SET_BSSID_SEL_V1_8822C(x, v)                                       \
+	(BIT_CLEAR_BSSID_SEL_V1_8822C(x) | BIT_BSSID_SEL_V1_8822C(v))
+
+#define BIT_SHIFT_P2P_OUI_TYPE_8822C 0
+#define BIT_MASK_P2P_OUI_TYPE_8822C 0xff
+#define BIT_P2P_OUI_TYPE_8822C(x)                                              \
+	(((x) & BIT_MASK_P2P_OUI_TYPE_8822C) << BIT_SHIFT_P2P_OUI_TYPE_8822C)
+#define BITS_P2P_OUI_TYPE_8822C                                                \
+	(BIT_MASK_P2P_OUI_TYPE_8822C << BIT_SHIFT_P2P_OUI_TYPE_8822C)
+#define BIT_CLEAR_P2P_OUI_TYPE_8822C(x) ((x) & (~BITS_P2P_OUI_TYPE_8822C))
+#define BIT_GET_P2P_OUI_TYPE_8822C(x)                                          \
+	(((x) >> BIT_SHIFT_P2P_OUI_TYPE_8822C) & BIT_MASK_P2P_OUI_TYPE_8822C)
+#define BIT_SET_P2P_OUI_TYPE_8822C(x, v)                                       \
+	(BIT_CLEAR_P2P_OUI_TYPE_8822C(x) | BIT_P2P_OUI_TYPE_8822C(v))
+
+/* 2 REG_RSVD_8822C */
+
+/* 2 REG_ASSOCIATED_BFMER0_INFO_8822C (ASSOCIATED BEAMFORMER0 INFO REGISTER) */
+
+#define BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0_V1_8822C 0
+#define BIT_MASK_R_WMAC_SOUNDING_RXADD_R0_V1_8822C 0xffffffffL
+#define BIT_R_WMAC_SOUNDING_RXADD_R0_V1_8822C(x)                               \
+	(((x) & BIT_MASK_R_WMAC_SOUNDING_RXADD_R0_V1_8822C)                    \
+	 << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0_V1_8822C)
+#define BITS_R_WMAC_SOUNDING_RXADD_R0_V1_8822C                                 \
+	(BIT_MASK_R_WMAC_SOUNDING_RXADD_R0_V1_8822C                            \
+	 << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0_V1_8822C)
+#define BIT_CLEAR_R_WMAC_SOUNDING_RXADD_R0_V1_8822C(x)                         \
+	((x) & (~BITS_R_WMAC_SOUNDING_RXADD_R0_V1_8822C))
+#define BIT_GET_R_WMAC_SOUNDING_RXADD_R0_V1_8822C(x)                           \
+	(((x) >> BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0_V1_8822C) &                \
+	 BIT_MASK_R_WMAC_SOUNDING_RXADD_R0_V1_8822C)
+#define BIT_SET_R_WMAC_SOUNDING_RXADD_R0_V1_8822C(x, v)                        \
+	(BIT_CLEAR_R_WMAC_SOUNDING_RXADD_R0_V1_8822C(x) |                      \
+	 BIT_R_WMAC_SOUNDING_RXADD_R0_V1_8822C(v))
+
+/* 2 REG_ASSOCIATED_BFMER0_INFO_H_8822C */
+
+#define BIT_SHIFT_R_WMAC_TXCSI_AID0_8822C 16
+#define BIT_MASK_R_WMAC_TXCSI_AID0_8822C 0x1ff
+#define BIT_R_WMAC_TXCSI_AID0_8822C(x)                                         \
+	(((x) & BIT_MASK_R_WMAC_TXCSI_AID0_8822C)                              \
+	 << BIT_SHIFT_R_WMAC_TXCSI_AID0_8822C)
+#define BITS_R_WMAC_TXCSI_AID0_8822C                                           \
+	(BIT_MASK_R_WMAC_TXCSI_AID0_8822C << BIT_SHIFT_R_WMAC_TXCSI_AID0_8822C)
+#define BIT_CLEAR_R_WMAC_TXCSI_AID0_8822C(x)                                   \
+	((x) & (~BITS_R_WMAC_TXCSI_AID0_8822C))
+#define BIT_GET_R_WMAC_TXCSI_AID0_8822C(x)                                     \
+	(((x) >> BIT_SHIFT_R_WMAC_TXCSI_AID0_8822C) &                          \
+	 BIT_MASK_R_WMAC_TXCSI_AID0_8822C)
+#define BIT_SET_R_WMAC_TXCSI_AID0_8822C(x, v)                                  \
+	(BIT_CLEAR_R_WMAC_TXCSI_AID0_8822C(x) | BIT_R_WMAC_TXCSI_AID0_8822C(v))
+
+#define BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0_H_V1_8822C 0
+#define BIT_MASK_R_WMAC_SOUNDING_RXADD_R0_H_V1_8822C 0xffff
+#define BIT_R_WMAC_SOUNDING_RXADD_R0_H_V1_8822C(x)                             \
+	(((x) & BIT_MASK_R_WMAC_SOUNDING_RXADD_R0_H_V1_8822C)                  \
+	 << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0_H_V1_8822C)
+#define BITS_R_WMAC_SOUNDING_RXADD_R0_H_V1_8822C                               \
+	(BIT_MASK_R_WMAC_SOUNDING_RXADD_R0_H_V1_8822C                          \
+	 << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0_H_V1_8822C)
+#define BIT_CLEAR_R_WMAC_SOUNDING_RXADD_R0_H_V1_8822C(x)                       \
+	((x) & (~BITS_R_WMAC_SOUNDING_RXADD_R0_H_V1_8822C))
+#define BIT_GET_R_WMAC_SOUNDING_RXADD_R0_H_V1_8822C(x)                         \
+	(((x) >> BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0_H_V1_8822C) &              \
+	 BIT_MASK_R_WMAC_SOUNDING_RXADD_R0_H_V1_8822C)
+#define BIT_SET_R_WMAC_SOUNDING_RXADD_R0_H_V1_8822C(x, v)                      \
+	(BIT_CLEAR_R_WMAC_SOUNDING_RXADD_R0_H_V1_8822C(x) |                    \
+	 BIT_R_WMAC_SOUNDING_RXADD_R0_H_V1_8822C(v))
+
+/* 2 REG_ASSOCIATED_BFMER1_INFO_8822C (ASSOCIATED BEAMFORMER1 INFO REGISTER) */
+
+#define BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1_V1_8822C 0
+#define BIT_MASK_R_WMAC_SOUNDING_RXADD_R1_V1_8822C 0xffffffffL
+#define BIT_R_WMAC_SOUNDING_RXADD_R1_V1_8822C(x)                               \
+	(((x) & BIT_MASK_R_WMAC_SOUNDING_RXADD_R1_V1_8822C)                    \
+	 << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1_V1_8822C)
+#define BITS_R_WMAC_SOUNDING_RXADD_R1_V1_8822C                                 \
+	(BIT_MASK_R_WMAC_SOUNDING_RXADD_R1_V1_8822C                            \
+	 << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1_V1_8822C)
+#define BIT_CLEAR_R_WMAC_SOUNDING_RXADD_R1_V1_8822C(x)                         \
+	((x) & (~BITS_R_WMAC_SOUNDING_RXADD_R1_V1_8822C))
+#define BIT_GET_R_WMAC_SOUNDING_RXADD_R1_V1_8822C(x)                           \
+	(((x) >> BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1_V1_8822C) &                \
+	 BIT_MASK_R_WMAC_SOUNDING_RXADD_R1_V1_8822C)
+#define BIT_SET_R_WMAC_SOUNDING_RXADD_R1_V1_8822C(x, v)                        \
+	(BIT_CLEAR_R_WMAC_SOUNDING_RXADD_R1_V1_8822C(x) |                      \
+	 BIT_R_WMAC_SOUNDING_RXADD_R1_V1_8822C(v))
+
+/* 2 REG_ASSOCIATED_BFMER1_INFO_H_8822C */
+
+#define BIT_SHIFT_R_WMAC_TXCSI_AID1_8822C 16
+#define BIT_MASK_R_WMAC_TXCSI_AID1_8822C 0x1ff
+#define BIT_R_WMAC_TXCSI_AID1_8822C(x)                                         \
+	(((x) & BIT_MASK_R_WMAC_TXCSI_AID1_8822C)                              \
+	 << BIT_SHIFT_R_WMAC_TXCSI_AID1_8822C)
+#define BITS_R_WMAC_TXCSI_AID1_8822C                                           \
+	(BIT_MASK_R_WMAC_TXCSI_AID1_8822C << BIT_SHIFT_R_WMAC_TXCSI_AID1_8822C)
+#define BIT_CLEAR_R_WMAC_TXCSI_AID1_8822C(x)                                   \
+	((x) & (~BITS_R_WMAC_TXCSI_AID1_8822C))
+#define BIT_GET_R_WMAC_TXCSI_AID1_8822C(x)                                     \
+	(((x) >> BIT_SHIFT_R_WMAC_TXCSI_AID1_8822C) &                          \
+	 BIT_MASK_R_WMAC_TXCSI_AID1_8822C)
+#define BIT_SET_R_WMAC_TXCSI_AID1_8822C(x, v)                                  \
+	(BIT_CLEAR_R_WMAC_TXCSI_AID1_8822C(x) | BIT_R_WMAC_TXCSI_AID1_8822C(v))
+
+#define BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1_H_V1_8822C 0
+#define BIT_MASK_R_WMAC_SOUNDING_RXADD_R1_H_V1_8822C 0xffff
+#define BIT_R_WMAC_SOUNDING_RXADD_R1_H_V1_8822C(x)                             \
+	(((x) & BIT_MASK_R_WMAC_SOUNDING_RXADD_R1_H_V1_8822C)                  \
+	 << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1_H_V1_8822C)
+#define BITS_R_WMAC_SOUNDING_RXADD_R1_H_V1_8822C                               \
+	(BIT_MASK_R_WMAC_SOUNDING_RXADD_R1_H_V1_8822C                          \
+	 << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1_H_V1_8822C)
+#define BIT_CLEAR_R_WMAC_SOUNDING_RXADD_R1_H_V1_8822C(x)                       \
+	((x) & (~BITS_R_WMAC_SOUNDING_RXADD_R1_H_V1_8822C))
+#define BIT_GET_R_WMAC_SOUNDING_RXADD_R1_H_V1_8822C(x)                         \
+	(((x) >> BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1_H_V1_8822C) &              \
+	 BIT_MASK_R_WMAC_SOUNDING_RXADD_R1_H_V1_8822C)
+#define BIT_SET_R_WMAC_SOUNDING_RXADD_R1_H_V1_8822C(x, v)                      \
+	(BIT_CLEAR_R_WMAC_SOUNDING_RXADD_R1_H_V1_8822C(x) |                    \
+	 BIT_R_WMAC_SOUNDING_RXADD_R1_H_V1_8822C(v))
+
+/* 2 REG_TX_CSI_RPT_PARAM_BW20_8822C (TX CSI REPORT PARAMETER REGISTER) */
+
+#define BIT_SHIFT_R_WMAC_BFINFO_20M_1_8822C 16
+#define BIT_MASK_R_WMAC_BFINFO_20M_1_8822C 0xfff
+#define BIT_R_WMAC_BFINFO_20M_1_8822C(x)                                       \
+	(((x) & BIT_MASK_R_WMAC_BFINFO_20M_1_8822C)                            \
+	 << BIT_SHIFT_R_WMAC_BFINFO_20M_1_8822C)
+#define BITS_R_WMAC_BFINFO_20M_1_8822C                                         \
+	(BIT_MASK_R_WMAC_BFINFO_20M_1_8822C                                    \
+	 << BIT_SHIFT_R_WMAC_BFINFO_20M_1_8822C)
+#define BIT_CLEAR_R_WMAC_BFINFO_20M_1_8822C(x)                                 \
+	((x) & (~BITS_R_WMAC_BFINFO_20M_1_8822C))
+#define BIT_GET_R_WMAC_BFINFO_20M_1_8822C(x)                                   \
+	(((x) >> BIT_SHIFT_R_WMAC_BFINFO_20M_1_8822C) &                        \
+	 BIT_MASK_R_WMAC_BFINFO_20M_1_8822C)
+#define BIT_SET_R_WMAC_BFINFO_20M_1_8822C(x, v)                                \
+	(BIT_CLEAR_R_WMAC_BFINFO_20M_1_8822C(x) |                              \
+	 BIT_R_WMAC_BFINFO_20M_1_8822C(v))
+
+#define BIT_SHIFT_R_WMAC_BFINFO_20M_0_8822C 0
+#define BIT_MASK_R_WMAC_BFINFO_20M_0_8822C 0xfff
+#define BIT_R_WMAC_BFINFO_20M_0_8822C(x)                                       \
+	(((x) & BIT_MASK_R_WMAC_BFINFO_20M_0_8822C)                            \
+	 << BIT_SHIFT_R_WMAC_BFINFO_20M_0_8822C)
+#define BITS_R_WMAC_BFINFO_20M_0_8822C                                         \
+	(BIT_MASK_R_WMAC_BFINFO_20M_0_8822C                                    \
+	 << BIT_SHIFT_R_WMAC_BFINFO_20M_0_8822C)
+#define BIT_CLEAR_R_WMAC_BFINFO_20M_0_8822C(x)                                 \
+	((x) & (~BITS_R_WMAC_BFINFO_20M_0_8822C))
+#define BIT_GET_R_WMAC_BFINFO_20M_0_8822C(x)                                   \
+	(((x) >> BIT_SHIFT_R_WMAC_BFINFO_20M_0_8822C) &                        \
+	 BIT_MASK_R_WMAC_BFINFO_20M_0_8822C)
+#define BIT_SET_R_WMAC_BFINFO_20M_0_8822C(x, v)                                \
+	(BIT_CLEAR_R_WMAC_BFINFO_20M_0_8822C(x) |                              \
+	 BIT_R_WMAC_BFINFO_20M_0_8822C(v))
+
+/* 2 REG_TX_CSI_RPT_PARAM_BW40_8822C (TX CSI REPORT PARAMETER_BW40 REGISTER) */
+
+#define BIT_SHIFT_WMAC_RESP_ANTD_8822C 12
+#define BIT_MASK_WMAC_RESP_ANTD_8822C 0xf
+#define BIT_WMAC_RESP_ANTD_8822C(x)                                            \
+	(((x) & BIT_MASK_WMAC_RESP_ANTD_8822C)                                 \
+	 << BIT_SHIFT_WMAC_RESP_ANTD_8822C)
+#define BITS_WMAC_RESP_ANTD_8822C                                              \
+	(BIT_MASK_WMAC_RESP_ANTD_8822C << BIT_SHIFT_WMAC_RESP_ANTD_8822C)
+#define BIT_CLEAR_WMAC_RESP_ANTD_8822C(x) ((x) & (~BITS_WMAC_RESP_ANTD_8822C))
+#define BIT_GET_WMAC_RESP_ANTD_8822C(x)                                        \
+	(((x) >> BIT_SHIFT_WMAC_RESP_ANTD_8822C) &                             \
+	 BIT_MASK_WMAC_RESP_ANTD_8822C)
+#define BIT_SET_WMAC_RESP_ANTD_8822C(x, v)                                     \
+	(BIT_CLEAR_WMAC_RESP_ANTD_8822C(x) | BIT_WMAC_RESP_ANTD_8822C(v))
+
+#define BIT_SHIFT_WMAC_RESP_ANTC_8822C 8
+#define BIT_MASK_WMAC_RESP_ANTC_8822C 0xf
+#define BIT_WMAC_RESP_ANTC_8822C(x)                                            \
+	(((x) & BIT_MASK_WMAC_RESP_ANTC_8822C)                                 \
+	 << BIT_SHIFT_WMAC_RESP_ANTC_8822C)
+#define BITS_WMAC_RESP_ANTC_8822C                                              \
+	(BIT_MASK_WMAC_RESP_ANTC_8822C << BIT_SHIFT_WMAC_RESP_ANTC_8822C)
+#define BIT_CLEAR_WMAC_RESP_ANTC_8822C(x) ((x) & (~BITS_WMAC_RESP_ANTC_8822C))
+#define BIT_GET_WMAC_RESP_ANTC_8822C(x)                                        \
+	(((x) >> BIT_SHIFT_WMAC_RESP_ANTC_8822C) &                             \
+	 BIT_MASK_WMAC_RESP_ANTC_8822C)
+#define BIT_SET_WMAC_RESP_ANTC_8822C(x, v)                                     \
+	(BIT_CLEAR_WMAC_RESP_ANTC_8822C(x) | BIT_WMAC_RESP_ANTC_8822C(v))
+
+#define BIT_SHIFT_WMAC_RESP_ANTB_8822C 4
+#define BIT_MASK_WMAC_RESP_ANTB_8822C 0xf
+#define BIT_WMAC_RESP_ANTB_8822C(x)                                            \
+	(((x) & BIT_MASK_WMAC_RESP_ANTB_8822C)                                 \
+	 << BIT_SHIFT_WMAC_RESP_ANTB_8822C)
+#define BITS_WMAC_RESP_ANTB_8822C                                              \
+	(BIT_MASK_WMAC_RESP_ANTB_8822C << BIT_SHIFT_WMAC_RESP_ANTB_8822C)
+#define BIT_CLEAR_WMAC_RESP_ANTB_8822C(x) ((x) & (~BITS_WMAC_RESP_ANTB_8822C))
+#define BIT_GET_WMAC_RESP_ANTB_8822C(x)                                        \
+	(((x) >> BIT_SHIFT_WMAC_RESP_ANTB_8822C) &                             \
+	 BIT_MASK_WMAC_RESP_ANTB_8822C)
+#define BIT_SET_WMAC_RESP_ANTB_8822C(x, v)                                     \
+	(BIT_CLEAR_WMAC_RESP_ANTB_8822C(x) | BIT_WMAC_RESP_ANTB_8822C(v))
+
+#define BIT_SHIFT_WMAC_RESP_ANTA_8822C 0
+#define BIT_MASK_WMAC_RESP_ANTA_8822C 0xf
+#define BIT_WMAC_RESP_ANTA_8822C(x)                                            \
+	(((x) & BIT_MASK_WMAC_RESP_ANTA_8822C)                                 \
+	 << BIT_SHIFT_WMAC_RESP_ANTA_8822C)
+#define BITS_WMAC_RESP_ANTA_8822C                                              \
+	(BIT_MASK_WMAC_RESP_ANTA_8822C << BIT_SHIFT_WMAC_RESP_ANTA_8822C)
+#define BIT_CLEAR_WMAC_RESP_ANTA_8822C(x) ((x) & (~BITS_WMAC_RESP_ANTA_8822C))
+#define BIT_GET_WMAC_RESP_ANTA_8822C(x)                                        \
+	(((x) >> BIT_SHIFT_WMAC_RESP_ANTA_8822C) &                             \
+	 BIT_MASK_WMAC_RESP_ANTA_8822C)
+#define BIT_SET_WMAC_RESP_ANTA_8822C(x, v)                                     \
+	(BIT_CLEAR_WMAC_RESP_ANTA_8822C(x) | BIT_WMAC_RESP_ANTA_8822C(v))
+
+/* 2 REG_CSI_PTR_8822C */
+
+#define BIT_SHIFT_CSI_RADDR_LATCH_V2_8822C 16
+#define BIT_MASK_CSI_RADDR_LATCH_V2_8822C 0xffff
+#define BIT_CSI_RADDR_LATCH_V2_8822C(x)                                        \
+	(((x) & BIT_MASK_CSI_RADDR_LATCH_V2_8822C)                             \
+	 << BIT_SHIFT_CSI_RADDR_LATCH_V2_8822C)
+#define BITS_CSI_RADDR_LATCH_V2_8822C                                          \
+	(BIT_MASK_CSI_RADDR_LATCH_V2_8822C                                     \
+	 << BIT_SHIFT_CSI_RADDR_LATCH_V2_8822C)
+#define BIT_CLEAR_CSI_RADDR_LATCH_V2_8822C(x)                                  \
+	((x) & (~BITS_CSI_RADDR_LATCH_V2_8822C))
+#define BIT_GET_CSI_RADDR_LATCH_V2_8822C(x)                                    \
+	(((x) >> BIT_SHIFT_CSI_RADDR_LATCH_V2_8822C) &                         \
+	 BIT_MASK_CSI_RADDR_LATCH_V2_8822C)
+#define BIT_SET_CSI_RADDR_LATCH_V2_8822C(x, v)                                 \
+	(BIT_CLEAR_CSI_RADDR_LATCH_V2_8822C(x) |                               \
+	 BIT_CSI_RADDR_LATCH_V2_8822C(v))
+
+#define BIT_SHIFT_CSI_WADDR_LATCH_V2_8822C 0
+#define BIT_MASK_CSI_WADDR_LATCH_V2_8822C 0xffff
+#define BIT_CSI_WADDR_LATCH_V2_8822C(x)                                        \
+	(((x) & BIT_MASK_CSI_WADDR_LATCH_V2_8822C)                             \
+	 << BIT_SHIFT_CSI_WADDR_LATCH_V2_8822C)
+#define BITS_CSI_WADDR_LATCH_V2_8822C                                          \
+	(BIT_MASK_CSI_WADDR_LATCH_V2_8822C                                     \
+	 << BIT_SHIFT_CSI_WADDR_LATCH_V2_8822C)
+#define BIT_CLEAR_CSI_WADDR_LATCH_V2_8822C(x)                                  \
+	((x) & (~BITS_CSI_WADDR_LATCH_V2_8822C))
+#define BIT_GET_CSI_WADDR_LATCH_V2_8822C(x)                                    \
+	(((x) >> BIT_SHIFT_CSI_WADDR_LATCH_V2_8822C) &                         \
+	 BIT_MASK_CSI_WADDR_LATCH_V2_8822C)
+#define BIT_SET_CSI_WADDR_LATCH_V2_8822C(x, v)                                 \
+	(BIT_CLEAR_CSI_WADDR_LATCH_V2_8822C(x) |                               \
+	 BIT_CSI_WADDR_LATCH_V2_8822C(v))
+
+/* 2 REG_BCN_PSR_RPT2_8822C (BEACON PARSER REPORT REGISTER2) */
+
+#define BIT_SHIFT_DTIM_CNT2_8822C 24
+#define BIT_MASK_DTIM_CNT2_8822C 0xff
+#define BIT_DTIM_CNT2_8822C(x)                                                 \
+	(((x) & BIT_MASK_DTIM_CNT2_8822C) << BIT_SHIFT_DTIM_CNT2_8822C)
+#define BITS_DTIM_CNT2_8822C                                                   \
+	(BIT_MASK_DTIM_CNT2_8822C << BIT_SHIFT_DTIM_CNT2_8822C)
+#define BIT_CLEAR_DTIM_CNT2_8822C(x) ((x) & (~BITS_DTIM_CNT2_8822C))
+#define BIT_GET_DTIM_CNT2_8822C(x)                                             \
+	(((x) >> BIT_SHIFT_DTIM_CNT2_8822C) & BIT_MASK_DTIM_CNT2_8822C)
+#define BIT_SET_DTIM_CNT2_8822C(x, v)                                          \
+	(BIT_CLEAR_DTIM_CNT2_8822C(x) | BIT_DTIM_CNT2_8822C(v))
+
+#define BIT_SHIFT_DTIM_PERIOD2_8822C 16
+#define BIT_MASK_DTIM_PERIOD2_8822C 0xff
+#define BIT_DTIM_PERIOD2_8822C(x)                                              \
+	(((x) & BIT_MASK_DTIM_PERIOD2_8822C) << BIT_SHIFT_DTIM_PERIOD2_8822C)
+#define BITS_DTIM_PERIOD2_8822C                                                \
+	(BIT_MASK_DTIM_PERIOD2_8822C << BIT_SHIFT_DTIM_PERIOD2_8822C)
+#define BIT_CLEAR_DTIM_PERIOD2_8822C(x) ((x) & (~BITS_DTIM_PERIOD2_8822C))
+#define BIT_GET_DTIM_PERIOD2_8822C(x)                                          \
+	(((x) >> BIT_SHIFT_DTIM_PERIOD2_8822C) & BIT_MASK_DTIM_PERIOD2_8822C)
+#define BIT_SET_DTIM_PERIOD2_8822C(x, v)                                       \
+	(BIT_CLEAR_DTIM_PERIOD2_8822C(x) | BIT_DTIM_PERIOD2_8822C(v))
+
+#define BIT_DTIM2_8822C BIT(15)
+#define BIT_TIM2_8822C BIT(14)
+#define BIT_RPT_VALID_8822C BIT(13)
+
+#define BIT_SHIFT_PS_AID_2_8822C 0
+#define BIT_MASK_PS_AID_2_8822C 0x7ff
+#define BIT_PS_AID_2_8822C(x)                                                  \
+	(((x) & BIT_MASK_PS_AID_2_8822C) << BIT_SHIFT_PS_AID_2_8822C)
+#define BITS_PS_AID_2_8822C                                                    \
+	(BIT_MASK_PS_AID_2_8822C << BIT_SHIFT_PS_AID_2_8822C)
+#define BIT_CLEAR_PS_AID_2_8822C(x) ((x) & (~BITS_PS_AID_2_8822C))
+#define BIT_GET_PS_AID_2_8822C(x)                                              \
+	(((x) >> BIT_SHIFT_PS_AID_2_8822C) & BIT_MASK_PS_AID_2_8822C)
+#define BIT_SET_PS_AID_2_8822C(x, v)                                           \
+	(BIT_CLEAR_PS_AID_2_8822C(x) | BIT_PS_AID_2_8822C(v))
+
+/* 2 REG_BCN_PSR_RPT3_8822C (BEACON PARSER REPORT REGISTER3) */
+
+#define BIT_SHIFT_DTIM_CNT3_8822C 24
+#define BIT_MASK_DTIM_CNT3_8822C 0xff
+#define BIT_DTIM_CNT3_8822C(x)                                                 \
+	(((x) & BIT_MASK_DTIM_CNT3_8822C) << BIT_SHIFT_DTIM_CNT3_8822C)
+#define BITS_DTIM_CNT3_8822C                                                   \
+	(BIT_MASK_DTIM_CNT3_8822C << BIT_SHIFT_DTIM_CNT3_8822C)
+#define BIT_CLEAR_DTIM_CNT3_8822C(x) ((x) & (~BITS_DTIM_CNT3_8822C))
+#define BIT_GET_DTIM_CNT3_8822C(x)                                             \
+	(((x) >> BIT_SHIFT_DTIM_CNT3_8822C) & BIT_MASK_DTIM_CNT3_8822C)
+#define BIT_SET_DTIM_CNT3_8822C(x, v)                                          \
+	(BIT_CLEAR_DTIM_CNT3_8822C(x) | BIT_DTIM_CNT3_8822C(v))
+
+#define BIT_SHIFT_DTIM_PERIOD3_8822C 16
+#define BIT_MASK_DTIM_PERIOD3_8822C 0xff
+#define BIT_DTIM_PERIOD3_8822C(x)                                              \
+	(((x) & BIT_MASK_DTIM_PERIOD3_8822C) << BIT_SHIFT_DTIM_PERIOD3_8822C)
+#define BITS_DTIM_PERIOD3_8822C                                                \
+	(BIT_MASK_DTIM_PERIOD3_8822C << BIT_SHIFT_DTIM_PERIOD3_8822C)
+#define BIT_CLEAR_DTIM_PERIOD3_8822C(x) ((x) & (~BITS_DTIM_PERIOD3_8822C))
+#define BIT_GET_DTIM_PERIOD3_8822C(x)                                          \
+	(((x) >> BIT_SHIFT_DTIM_PERIOD3_8822C) & BIT_MASK_DTIM_PERIOD3_8822C)
+#define BIT_SET_DTIM_PERIOD3_8822C(x, v)                                       \
+	(BIT_CLEAR_DTIM_PERIOD3_8822C(x) | BIT_DTIM_PERIOD3_8822C(v))
+
+#define BIT_DTIM3_8822C BIT(15)
+#define BIT_TIM3_8822C BIT(14)
+#define BIT_RPT_VALID_8822C BIT(13)
+
+#define BIT_SHIFT_PS_AID_3_8822C 0
+#define BIT_MASK_PS_AID_3_8822C 0x7ff
+#define BIT_PS_AID_3_8822C(x)                                                  \
+	(((x) & BIT_MASK_PS_AID_3_8822C) << BIT_SHIFT_PS_AID_3_8822C)
+#define BITS_PS_AID_3_8822C                                                    \
+	(BIT_MASK_PS_AID_3_8822C << BIT_SHIFT_PS_AID_3_8822C)
+#define BIT_CLEAR_PS_AID_3_8822C(x) ((x) & (~BITS_PS_AID_3_8822C))
+#define BIT_GET_PS_AID_3_8822C(x)                                              \
+	(((x) >> BIT_SHIFT_PS_AID_3_8822C) & BIT_MASK_PS_AID_3_8822C)
+#define BIT_SET_PS_AID_3_8822C(x, v)                                           \
+	(BIT_CLEAR_PS_AID_3_8822C(x) | BIT_PS_AID_3_8822C(v))
+
+/* 2 REG_BCN_PSR_RPT4_8822C (BEACON PARSER REPORT REGISTER4) */
+
+#define BIT_SHIFT_DTIM_CNT4_8822C 24
+#define BIT_MASK_DTIM_CNT4_8822C 0xff
+#define BIT_DTIM_CNT4_8822C(x)                                                 \
+	(((x) & BIT_MASK_DTIM_CNT4_8822C) << BIT_SHIFT_DTIM_CNT4_8822C)
+#define BITS_DTIM_CNT4_8822C                                                   \
+	(BIT_MASK_DTIM_CNT4_8822C << BIT_SHIFT_DTIM_CNT4_8822C)
+#define BIT_CLEAR_DTIM_CNT4_8822C(x) ((x) & (~BITS_DTIM_CNT4_8822C))
+#define BIT_GET_DTIM_CNT4_8822C(x)                                             \
+	(((x) >> BIT_SHIFT_DTIM_CNT4_8822C) & BIT_MASK_DTIM_CNT4_8822C)
+#define BIT_SET_DTIM_CNT4_8822C(x, v)                                          \
+	(BIT_CLEAR_DTIM_CNT4_8822C(x) | BIT_DTIM_CNT4_8822C(v))
+
+#define BIT_SHIFT_DTIM_PERIOD4_8822C 16
+#define BIT_MASK_DTIM_PERIOD4_8822C 0xff
+#define BIT_DTIM_PERIOD4_8822C(x)                                              \
+	(((x) & BIT_MASK_DTIM_PERIOD4_8822C) << BIT_SHIFT_DTIM_PERIOD4_8822C)
+#define BITS_DTIM_PERIOD4_8822C                                                \
+	(BIT_MASK_DTIM_PERIOD4_8822C << BIT_SHIFT_DTIM_PERIOD4_8822C)
+#define BIT_CLEAR_DTIM_PERIOD4_8822C(x) ((x) & (~BITS_DTIM_PERIOD4_8822C))
+#define BIT_GET_DTIM_PERIOD4_8822C(x)                                          \
+	(((x) >> BIT_SHIFT_DTIM_PERIOD4_8822C) & BIT_MASK_DTIM_PERIOD4_8822C)
+#define BIT_SET_DTIM_PERIOD4_8822C(x, v)                                       \
+	(BIT_CLEAR_DTIM_PERIOD4_8822C(x) | BIT_DTIM_PERIOD4_8822C(v))
+
+#define BIT_DTIM4_8822C BIT(15)
+#define BIT_TIM4_8822C BIT(14)
+#define BIT_RPT_VALID_8822C BIT(13)
+
+#define BIT_SHIFT_PS_AID_4_8822C 0
+#define BIT_MASK_PS_AID_4_8822C 0x7ff
+#define BIT_PS_AID_4_8822C(x)                                                  \
+	(((x) & BIT_MASK_PS_AID_4_8822C) << BIT_SHIFT_PS_AID_4_8822C)
+#define BITS_PS_AID_4_8822C                                                    \
+	(BIT_MASK_PS_AID_4_8822C << BIT_SHIFT_PS_AID_4_8822C)
+#define BIT_CLEAR_PS_AID_4_8822C(x) ((x) & (~BITS_PS_AID_4_8822C))
+#define BIT_GET_PS_AID_4_8822C(x)                                              \
+	(((x) >> BIT_SHIFT_PS_AID_4_8822C) & BIT_MASK_PS_AID_4_8822C)
+#define BIT_SET_PS_AID_4_8822C(x, v)                                           \
+	(BIT_CLEAR_PS_AID_4_8822C(x) | BIT_PS_AID_4_8822C(v))
+
+/* 2 REG_A1_ADDR_MASK_8822C (A1 ADDR MASK REGISTER) */
+
+#define BIT_SHIFT_A1_ADDR_MASK_8822C 0
+#define BIT_MASK_A1_ADDR_MASK_8822C 0xffffffffL
+#define BIT_A1_ADDR_MASK_8822C(x)                                              \
+	(((x) & BIT_MASK_A1_ADDR_MASK_8822C) << BIT_SHIFT_A1_ADDR_MASK_8822C)
+#define BITS_A1_ADDR_MASK_8822C                                                \
+	(BIT_MASK_A1_ADDR_MASK_8822C << BIT_SHIFT_A1_ADDR_MASK_8822C)
+#define BIT_CLEAR_A1_ADDR_MASK_8822C(x) ((x) & (~BITS_A1_ADDR_MASK_8822C))
+#define BIT_GET_A1_ADDR_MASK_8822C(x)                                          \
+	(((x) >> BIT_SHIFT_A1_ADDR_MASK_8822C) & BIT_MASK_A1_ADDR_MASK_8822C)
+#define BIT_SET_A1_ADDR_MASK_8822C(x, v)                                       \
+	(BIT_CLEAR_A1_ADDR_MASK_8822C(x) | BIT_A1_ADDR_MASK_8822C(v))
+
+/* 2 REG_RXPSF_CTRL_8822C */
+#define BIT_RXGCK_FIFOTHR_EN_8822C BIT(28)
+
+#define BIT_SHIFT_RXGCK_VHT_FIFOTHR_8822C 26
+#define BIT_MASK_RXGCK_VHT_FIFOTHR_8822C 0x3
+#define BIT_RXGCK_VHT_FIFOTHR_8822C(x)                                         \
+	(((x) & BIT_MASK_RXGCK_VHT_FIFOTHR_8822C)                              \
+	 << BIT_SHIFT_RXGCK_VHT_FIFOTHR_8822C)
+#define BITS_RXGCK_VHT_FIFOTHR_8822C                                           \
+	(BIT_MASK_RXGCK_VHT_FIFOTHR_8822C << BIT_SHIFT_RXGCK_VHT_FIFOTHR_8822C)
+#define BIT_CLEAR_RXGCK_VHT_FIFOTHR_8822C(x)                                   \
+	((x) & (~BITS_RXGCK_VHT_FIFOTHR_8822C))
+#define BIT_GET_RXGCK_VHT_FIFOTHR_8822C(x)                                     \
+	(((x) >> BIT_SHIFT_RXGCK_VHT_FIFOTHR_8822C) &                          \
+	 BIT_MASK_RXGCK_VHT_FIFOTHR_8822C)
+#define BIT_SET_RXGCK_VHT_FIFOTHR_8822C(x, v)                                  \
+	(BIT_CLEAR_RXGCK_VHT_FIFOTHR_8822C(x) | BIT_RXGCK_VHT_FIFOTHR_8822C(v))
+
+#define BIT_SHIFT_RXGCK_HT_FIFOTHR_8822C 24
+#define BIT_MASK_RXGCK_HT_FIFOTHR_8822C 0x3
+#define BIT_RXGCK_HT_FIFOTHR_8822C(x)                                          \
+	(((x) & BIT_MASK_RXGCK_HT_FIFOTHR_8822C)                               \
+	 << BIT_SHIFT_RXGCK_HT_FIFOTHR_8822C)
+#define BITS_RXGCK_HT_FIFOTHR_8822C                                            \
+	(BIT_MASK_RXGCK_HT_FIFOTHR_8822C << BIT_SHIFT_RXGCK_HT_FIFOTHR_8822C)
+#define BIT_CLEAR_RXGCK_HT_FIFOTHR_8822C(x)                                    \
+	((x) & (~BITS_RXGCK_HT_FIFOTHR_8822C))
+#define BIT_GET_RXGCK_HT_FIFOTHR_8822C(x)                                      \
+	(((x) >> BIT_SHIFT_RXGCK_HT_FIFOTHR_8822C) &                           \
+	 BIT_MASK_RXGCK_HT_FIFOTHR_8822C)
+#define BIT_SET_RXGCK_HT_FIFOTHR_8822C(x, v)                                   \
+	(BIT_CLEAR_RXGCK_HT_FIFOTHR_8822C(x) | BIT_RXGCK_HT_FIFOTHR_8822C(v))
+
+#define BIT_SHIFT_RXGCK_OFDM_FIFOTHR_8822C 22
+#define BIT_MASK_RXGCK_OFDM_FIFOTHR_8822C 0x3
+#define BIT_RXGCK_OFDM_FIFOTHR_8822C(x)                                        \
+	(((x) & BIT_MASK_RXGCK_OFDM_FIFOTHR_8822C)                             \
+	 << BIT_SHIFT_RXGCK_OFDM_FIFOTHR_8822C)
+#define BITS_RXGCK_OFDM_FIFOTHR_8822C                                          \
+	(BIT_MASK_RXGCK_OFDM_FIFOTHR_8822C                                     \
+	 << BIT_SHIFT_RXGCK_OFDM_FIFOTHR_8822C)
+#define BIT_CLEAR_RXGCK_OFDM_FIFOTHR_8822C(x)                                  \
+	((x) & (~BITS_RXGCK_OFDM_FIFOTHR_8822C))
+#define BIT_GET_RXGCK_OFDM_FIFOTHR_8822C(x)                                    \
+	(((x) >> BIT_SHIFT_RXGCK_OFDM_FIFOTHR_8822C) &                         \
+	 BIT_MASK_RXGCK_OFDM_FIFOTHR_8822C)
+#define BIT_SET_RXGCK_OFDM_FIFOTHR_8822C(x, v)                                 \
+	(BIT_CLEAR_RXGCK_OFDM_FIFOTHR_8822C(x) |                               \
+	 BIT_RXGCK_OFDM_FIFOTHR_8822C(v))
+
+#define BIT_SHIFT_RXGCK_CCK_FIFOTHR_8822C 20
+#define BIT_MASK_RXGCK_CCK_FIFOTHR_8822C 0x3
+#define BIT_RXGCK_CCK_FIFOTHR_8822C(x)                                         \
+	(((x) & BIT_MASK_RXGCK_CCK_FIFOTHR_8822C)                              \
+	 << BIT_SHIFT_RXGCK_CCK_FIFOTHR_8822C)
+#define BITS_RXGCK_CCK_FIFOTHR_8822C                                           \
+	(BIT_MASK_RXGCK_CCK_FIFOTHR_8822C << BIT_SHIFT_RXGCK_CCK_FIFOTHR_8822C)
+#define BIT_CLEAR_RXGCK_CCK_FIFOTHR_8822C(x)                                   \
+	((x) & (~BITS_RXGCK_CCK_FIFOTHR_8822C))
+#define BIT_GET_RXGCK_CCK_FIFOTHR_8822C(x)                                     \
+	(((x) >> BIT_SHIFT_RXGCK_CCK_FIFOTHR_8822C) &                          \
+	 BIT_MASK_RXGCK_CCK_FIFOTHR_8822C)
+#define BIT_SET_RXGCK_CCK_FIFOTHR_8822C(x, v)                                  \
+	(BIT_CLEAR_RXGCK_CCK_FIFOTHR_8822C(x) | BIT_RXGCK_CCK_FIFOTHR_8822C(v))
+
+#define BIT_SHIFT_RXGCK_ENTRY_DELAY_8822C 17
+#define BIT_MASK_RXGCK_ENTRY_DELAY_8822C 0x7
+#define BIT_RXGCK_ENTRY_DELAY_8822C(x)                                         \
+	(((x) & BIT_MASK_RXGCK_ENTRY_DELAY_8822C)                              \
+	 << BIT_SHIFT_RXGCK_ENTRY_DELAY_8822C)
+#define BITS_RXGCK_ENTRY_DELAY_8822C                                           \
+	(BIT_MASK_RXGCK_ENTRY_DELAY_8822C << BIT_SHIFT_RXGCK_ENTRY_DELAY_8822C)
+#define BIT_CLEAR_RXGCK_ENTRY_DELAY_8822C(x)                                   \
+	((x) & (~BITS_RXGCK_ENTRY_DELAY_8822C))
+#define BIT_GET_RXGCK_ENTRY_DELAY_8822C(x)                                     \
+	(((x) >> BIT_SHIFT_RXGCK_ENTRY_DELAY_8822C) &                          \
+	 BIT_MASK_RXGCK_ENTRY_DELAY_8822C)
+#define BIT_SET_RXGCK_ENTRY_DELAY_8822C(x, v)                                  \
+	(BIT_CLEAR_RXGCK_ENTRY_DELAY_8822C(x) | BIT_RXGCK_ENTRY_DELAY_8822C(v))
+
+#define BIT_RXGCK_OFDMCCA_EN_8822C BIT(16)
+
+#define BIT_SHIFT_RXPSF_PKTLENTHR_8822C 13
+#define BIT_MASK_RXPSF_PKTLENTHR_8822C 0x7
+#define BIT_RXPSF_PKTLENTHR_8822C(x)                                           \
+	(((x) & BIT_MASK_RXPSF_PKTLENTHR_8822C)                                \
+	 << BIT_SHIFT_RXPSF_PKTLENTHR_8822C)
+#define BITS_RXPSF_PKTLENTHR_8822C                                             \
+	(BIT_MASK_RXPSF_PKTLENTHR_8822C << BIT_SHIFT_RXPSF_PKTLENTHR_8822C)
+#define BIT_CLEAR_RXPSF_PKTLENTHR_8822C(x) ((x) & (~BITS_RXPSF_PKTLENTHR_8822C))
+#define BIT_GET_RXPSF_PKTLENTHR_8822C(x)                                       \
+	(((x) >> BIT_SHIFT_RXPSF_PKTLENTHR_8822C) &                            \
+	 BIT_MASK_RXPSF_PKTLENTHR_8822C)
+#define BIT_SET_RXPSF_PKTLENTHR_8822C(x, v)                                    \
+	(BIT_CLEAR_RXPSF_PKTLENTHR_8822C(x) | BIT_RXPSF_PKTLENTHR_8822C(v))
+
+#define BIT_RXPSF_CTRLEN_8822C BIT(12)
+#define BIT_RXPSF_VHTCHKEN_8822C BIT(11)
+#define BIT_RXPSF_HTCHKEN_8822C BIT(10)
+#define BIT_RXPSF_OFDMCHKEN_8822C BIT(9)
+#define BIT_RXPSF_CCKCHKEN_8822C BIT(8)
+#define BIT_RXPSF_OFDMRST_8822C BIT(7)
+#define BIT_RXPSF_CCKRST_8822C BIT(6)
+#define BIT_RXPSF_MHCHKEN_8822C BIT(5)
+#define BIT_RXPSF_CONT_ERRCHKEN_8822C BIT(4)
+#define BIT_RXPSF_ALL_ERRCHKEN_8822C BIT(3)
+
+#define BIT_SHIFT_RXPSF_ERRTHR_8822C 0
+#define BIT_MASK_RXPSF_ERRTHR_8822C 0x7
+#define BIT_RXPSF_ERRTHR_8822C(x)                                              \
+	(((x) & BIT_MASK_RXPSF_ERRTHR_8822C) << BIT_SHIFT_RXPSF_ERRTHR_8822C)
+#define BITS_RXPSF_ERRTHR_8822C                                                \
+	(BIT_MASK_RXPSF_ERRTHR_8822C << BIT_SHIFT_RXPSF_ERRTHR_8822C)
+#define BIT_CLEAR_RXPSF_ERRTHR_8822C(x) ((x) & (~BITS_RXPSF_ERRTHR_8822C))
+#define BIT_GET_RXPSF_ERRTHR_8822C(x)                                          \
+	(((x) >> BIT_SHIFT_RXPSF_ERRTHR_8822C) & BIT_MASK_RXPSF_ERRTHR_8822C)
+#define BIT_SET_RXPSF_ERRTHR_8822C(x, v)                                       \
+	(BIT_CLEAR_RXPSF_ERRTHR_8822C(x) | BIT_RXPSF_ERRTHR_8822C(v))
+
+/* 2 REG_RXPSF_TYPE_CTRL_8822C */
+#define BIT_RXPSF_DATA15EN_8822C BIT(31)
+#define BIT_RXPSF_DATA14EN_8822C BIT(30)
+#define BIT_RXPSF_DATA13EN_8822C BIT(29)
+#define BIT_RXPSF_DATA12EN_8822C BIT(28)
+#define BIT_RXPSF_DATA11EN_8822C BIT(27)
+#define BIT_RXPSF_DATA10EN_8822C BIT(26)
+#define BIT_RXPSF_DATA9EN_8822C BIT(25)
+#define BIT_RXPSF_DATA8EN_8822C BIT(24)
+#define BIT_RXPSF_DATA7EN_8822C BIT(23)
+#define BIT_RXPSF_DATA6EN_8822C BIT(22)
+#define BIT_RXPSF_DATA5EN_8822C BIT(21)
+#define BIT_RXPSF_DATA4EN_8822C BIT(20)
+#define BIT_RXPSF_DATA3EN_8822C BIT(19)
+#define BIT_RXPSF_DATA2EN_8822C BIT(18)
+#define BIT_RXPSF_DATA1EN_8822C BIT(17)
+#define BIT_RXPSF_DATA0EN_8822C BIT(16)
+#define BIT_RXPSF_MGT15EN_8822C BIT(15)
+#define BIT_RXPSF_MGT14EN_8822C BIT(14)
+#define BIT_RXPSF_MGT13EN_8822C BIT(13)
+#define BIT_RXPSF_MGT12EN_8822C BIT(12)
+#define BIT_RXPSF_MGT11EN_8822C BIT(11)
+#define BIT_RXPSF_MGT10EN_8822C BIT(10)
+#define BIT_RXPSF_MGT9EN_8822C BIT(9)
+#define BIT_RXPSF_MGT8EN_8822C BIT(8)
+#define BIT_RXPSF_MGT7EN_8822C BIT(7)
+#define BIT_RXPSF_MGT6EN_8822C BIT(6)
+#define BIT_RXPSF_MGT5EN_8822C BIT(5)
+#define BIT_RXPSF_MGT4EN_8822C BIT(4)
+#define BIT_RXPSF_MGT3EN_8822C BIT(3)
+#define BIT_RXPSF_MGT2EN_8822C BIT(2)
+#define BIT_RXPSF_MGT1EN_8822C BIT(1)
+#define BIT_RXPSF_MGT0EN_8822C BIT(0)
+
+/* 2 REG_CAM_ACCESS_CTRL_8822C */
+#define BIT_INDIRECT_ERR_8822C BIT(6)
+#define BIT_DIRECT_ERR_8822C BIT(5)
+#define BIT_DIR_ACCESS_EN_RX_BA_8822C BIT(4)
+#define BIT_DIR_ACCESS_EN_MBSSIDCAM_8822C BIT(3)
+#define BIT_DIR_ACCESS_EN_KEY_8822C BIT(2)
+#define BIT_DIR_ACCESS_EN_WOWLAN_8822C BIT(1)
+#define BIT_DIR_ACCESS_EN_FW_FILTER_8822C BIT(0)
+
+/* 2 REG_HT_SND_REF_RATE_8822C */
+
+#define BIT_SHIFT_WMAC_HT_CSI_RATE_8822C 0
+#define BIT_MASK_WMAC_HT_CSI_RATE_8822C 0x3f
+#define BIT_WMAC_HT_CSI_RATE_8822C(x)                                          \
+	(((x) & BIT_MASK_WMAC_HT_CSI_RATE_8822C)                               \
+	 << BIT_SHIFT_WMAC_HT_CSI_RATE_8822C)
+#define BITS_WMAC_HT_CSI_RATE_8822C                                            \
+	(BIT_MASK_WMAC_HT_CSI_RATE_8822C << BIT_SHIFT_WMAC_HT_CSI_RATE_8822C)
+#define BIT_CLEAR_WMAC_HT_CSI_RATE_8822C(x)                                    \
+	((x) & (~BITS_WMAC_HT_CSI_RATE_8822C))
+#define BIT_GET_WMAC_HT_CSI_RATE_8822C(x)                                      \
+	(((x) >> BIT_SHIFT_WMAC_HT_CSI_RATE_8822C) &                           \
+	 BIT_MASK_WMAC_HT_CSI_RATE_8822C)
+#define BIT_SET_WMAC_HT_CSI_RATE_8822C(x, v)                                   \
+	(BIT_CLEAR_WMAC_HT_CSI_RATE_8822C(x) | BIT_WMAC_HT_CSI_RATE_8822C(v))
+
+/* 2 REG_RSVD_8822C */
+
+/* 2 REG_MACID2_8822C (MAC ID2 REGISTER) */
+
+#define BIT_SHIFT_MACID2_V1_8822C 0
+#define BIT_MASK_MACID2_V1_8822C 0xffffffffL
+#define BIT_MACID2_V1_8822C(x)                                                 \
+	(((x) & BIT_MASK_MACID2_V1_8822C) << BIT_SHIFT_MACID2_V1_8822C)
+#define BITS_MACID2_V1_8822C                                                   \
+	(BIT_MASK_MACID2_V1_8822C << BIT_SHIFT_MACID2_V1_8822C)
+#define BIT_CLEAR_MACID2_V1_8822C(x) ((x) & (~BITS_MACID2_V1_8822C))
+#define BIT_GET_MACID2_V1_8822C(x)                                             \
+	(((x) >> BIT_SHIFT_MACID2_V1_8822C) & BIT_MASK_MACID2_V1_8822C)
+#define BIT_SET_MACID2_V1_8822C(x, v)                                          \
+	(BIT_CLEAR_MACID2_V1_8822C(x) | BIT_MACID2_V1_8822C(v))
+
+/* 2 REG_MACID2_H_8822C (MAC ID2 REGISTER) */
+
+#define BIT_SHIFT_MACID2_H_V1_8822C 0
+#define BIT_MASK_MACID2_H_V1_8822C 0xffff
+#define BIT_MACID2_H_V1_8822C(x)                                               \
+	(((x) & BIT_MASK_MACID2_H_V1_8822C) << BIT_SHIFT_MACID2_H_V1_8822C)
+#define BITS_MACID2_H_V1_8822C                                                 \
+	(BIT_MASK_MACID2_H_V1_8822C << BIT_SHIFT_MACID2_H_V1_8822C)
+#define BIT_CLEAR_MACID2_H_V1_8822C(x) ((x) & (~BITS_MACID2_H_V1_8822C))
+#define BIT_GET_MACID2_H_V1_8822C(x)                                           \
+	(((x) >> BIT_SHIFT_MACID2_H_V1_8822C) & BIT_MASK_MACID2_H_V1_8822C)
+#define BIT_SET_MACID2_H_V1_8822C(x, v)                                        \
+	(BIT_CLEAR_MACID2_H_V1_8822C(x) | BIT_MACID2_H_V1_8822C(v))
+
+/* 2 REG_BSSID2_8822C (BSSID2 REGISTER) */
+
+#define BIT_SHIFT_BSSID2_V1_8822C 0
+#define BIT_MASK_BSSID2_V1_8822C 0xffffffffL
+#define BIT_BSSID2_V1_8822C(x)                                                 \
+	(((x) & BIT_MASK_BSSID2_V1_8822C) << BIT_SHIFT_BSSID2_V1_8822C)
+#define BITS_BSSID2_V1_8822C                                                   \
+	(BIT_MASK_BSSID2_V1_8822C << BIT_SHIFT_BSSID2_V1_8822C)
+#define BIT_CLEAR_BSSID2_V1_8822C(x) ((x) & (~BITS_BSSID2_V1_8822C))
+#define BIT_GET_BSSID2_V1_8822C(x)                                             \
+	(((x) >> BIT_SHIFT_BSSID2_V1_8822C) & BIT_MASK_BSSID2_V1_8822C)
+#define BIT_SET_BSSID2_V1_8822C(x, v)                                          \
+	(BIT_CLEAR_BSSID2_V1_8822C(x) | BIT_BSSID2_V1_8822C(v))
+
+/* 2 REG_BSSID2_H_8822C (BSSID2 REGISTER) */
+
+#define BIT_SHIFT_BSSID2_H_V1_8822C 0
+#define BIT_MASK_BSSID2_H_V1_8822C 0xffff
+#define BIT_BSSID2_H_V1_8822C(x)                                               \
+	(((x) & BIT_MASK_BSSID2_H_V1_8822C) << BIT_SHIFT_BSSID2_H_V1_8822C)
+#define BITS_BSSID2_H_V1_8822C                                                 \
+	(BIT_MASK_BSSID2_H_V1_8822C << BIT_SHIFT_BSSID2_H_V1_8822C)
+#define BIT_CLEAR_BSSID2_H_V1_8822C(x) ((x) & (~BITS_BSSID2_H_V1_8822C))
+#define BIT_GET_BSSID2_H_V1_8822C(x)                                           \
+	(((x) >> BIT_SHIFT_BSSID2_H_V1_8822C) & BIT_MASK_BSSID2_H_V1_8822C)
+#define BIT_SET_BSSID2_H_V1_8822C(x, v)                                        \
+	(BIT_CLEAR_BSSID2_H_V1_8822C(x) | BIT_BSSID2_H_V1_8822C(v))
+
+/* 2 REG_MACID3_8822C (MAC ID3 REGISTER) */
+
+#define BIT_SHIFT_MACID3_V1_8822C 0
+#define BIT_MASK_MACID3_V1_8822C 0xffffffffL
+#define BIT_MACID3_V1_8822C(x)                                                 \
+	(((x) & BIT_MASK_MACID3_V1_8822C) << BIT_SHIFT_MACID3_V1_8822C)
+#define BITS_MACID3_V1_8822C                                                   \
+	(BIT_MASK_MACID3_V1_8822C << BIT_SHIFT_MACID3_V1_8822C)
+#define BIT_CLEAR_MACID3_V1_8822C(x) ((x) & (~BITS_MACID3_V1_8822C))
+#define BIT_GET_MACID3_V1_8822C(x)                                             \
+	(((x) >> BIT_SHIFT_MACID3_V1_8822C) & BIT_MASK_MACID3_V1_8822C)
+#define BIT_SET_MACID3_V1_8822C(x, v)                                          \
+	(BIT_CLEAR_MACID3_V1_8822C(x) | BIT_MACID3_V1_8822C(v))
+
+/* 2 REG_MACID3_H_8822C (MAC ID3 REGISTER) */
+
+#define BIT_SHIFT_MACID3_H_V1_8822C 0
+#define BIT_MASK_MACID3_H_V1_8822C 0xffff
+#define BIT_MACID3_H_V1_8822C(x)                                               \
+	(((x) & BIT_MASK_MACID3_H_V1_8822C) << BIT_SHIFT_MACID3_H_V1_8822C)
+#define BITS_MACID3_H_V1_8822C                                                 \
+	(BIT_MASK_MACID3_H_V1_8822C << BIT_SHIFT_MACID3_H_V1_8822C)
+#define BIT_CLEAR_MACID3_H_V1_8822C(x) ((x) & (~BITS_MACID3_H_V1_8822C))
+#define BIT_GET_MACID3_H_V1_8822C(x)                                           \
+	(((x) >> BIT_SHIFT_MACID3_H_V1_8822C) & BIT_MASK_MACID3_H_V1_8822C)
+#define BIT_SET_MACID3_H_V1_8822C(x, v)                                        \
+	(BIT_CLEAR_MACID3_H_V1_8822C(x) | BIT_MACID3_H_V1_8822C(v))
+
+/* 2 REG_BSSID3_8822C (BSSID3 REGISTER) */
+
+#define BIT_SHIFT_BSSID3_V1_8822C 0
+#define BIT_MASK_BSSID3_V1_8822C 0xffffffffL
+#define BIT_BSSID3_V1_8822C(x)                                                 \
+	(((x) & BIT_MASK_BSSID3_V1_8822C) << BIT_SHIFT_BSSID3_V1_8822C)
+#define BITS_BSSID3_V1_8822C                                                   \
+	(BIT_MASK_BSSID3_V1_8822C << BIT_SHIFT_BSSID3_V1_8822C)
+#define BIT_CLEAR_BSSID3_V1_8822C(x) ((x) & (~BITS_BSSID3_V1_8822C))
+#define BIT_GET_BSSID3_V1_8822C(x)                                             \
+	(((x) >> BIT_SHIFT_BSSID3_V1_8822C) & BIT_MASK_BSSID3_V1_8822C)
+#define BIT_SET_BSSID3_V1_8822C(x, v)                                          \
+	(BIT_CLEAR_BSSID3_V1_8822C(x) | BIT_BSSID3_V1_8822C(v))
+
+/* 2 REG_BSSID3_H_8822C (BSSID3 REGISTER) */
+
+#define BIT_SHIFT_BSSID3_H_V1_8822C 0
+#define BIT_MASK_BSSID3_H_V1_8822C 0xffff
+#define BIT_BSSID3_H_V1_8822C(x)                                               \
+	(((x) & BIT_MASK_BSSID3_H_V1_8822C) << BIT_SHIFT_BSSID3_H_V1_8822C)
+#define BITS_BSSID3_H_V1_8822C                                                 \
+	(BIT_MASK_BSSID3_H_V1_8822C << BIT_SHIFT_BSSID3_H_V1_8822C)
+#define BIT_CLEAR_BSSID3_H_V1_8822C(x) ((x) & (~BITS_BSSID3_H_V1_8822C))
+#define BIT_GET_BSSID3_H_V1_8822C(x)                                           \
+	(((x) >> BIT_SHIFT_BSSID3_H_V1_8822C) & BIT_MASK_BSSID3_H_V1_8822C)
+#define BIT_SET_BSSID3_H_V1_8822C(x, v)                                        \
+	(BIT_CLEAR_BSSID3_H_V1_8822C(x) | BIT_BSSID3_H_V1_8822C(v))
+
+/* 2 REG_MACID4_8822C (MAC ID4 REGISTER) */
+
+#define BIT_SHIFT_MACID4_V1_8822C 0
+#define BIT_MASK_MACID4_V1_8822C 0xffffffffL
+#define BIT_MACID4_V1_8822C(x)                                                 \
+	(((x) & BIT_MASK_MACID4_V1_8822C) << BIT_SHIFT_MACID4_V1_8822C)
+#define BITS_MACID4_V1_8822C                                                   \
+	(BIT_MASK_MACID4_V1_8822C << BIT_SHIFT_MACID4_V1_8822C)
+#define BIT_CLEAR_MACID4_V1_8822C(x) ((x) & (~BITS_MACID4_V1_8822C))
+#define BIT_GET_MACID4_V1_8822C(x)                                             \
+	(((x) >> BIT_SHIFT_MACID4_V1_8822C) & BIT_MASK_MACID4_V1_8822C)
+#define BIT_SET_MACID4_V1_8822C(x, v)                                          \
+	(BIT_CLEAR_MACID4_V1_8822C(x) | BIT_MACID4_V1_8822C(v))
+
+/* 2 REG_MACID4_H_8822C (MAC ID4 REGISTER) */
+
+#define BIT_SHIFT_MACID4_H_V1_8822C 0
+#define BIT_MASK_MACID4_H_V1_8822C 0xffff
+#define BIT_MACID4_H_V1_8822C(x)                                               \
+	(((x) & BIT_MASK_MACID4_H_V1_8822C) << BIT_SHIFT_MACID4_H_V1_8822C)
+#define BITS_MACID4_H_V1_8822C                                                 \
+	(BIT_MASK_MACID4_H_V1_8822C << BIT_SHIFT_MACID4_H_V1_8822C)
+#define BIT_CLEAR_MACID4_H_V1_8822C(x) ((x) & (~BITS_MACID4_H_V1_8822C))
+#define BIT_GET_MACID4_H_V1_8822C(x)                                           \
+	(((x) >> BIT_SHIFT_MACID4_H_V1_8822C) & BIT_MASK_MACID4_H_V1_8822C)
+#define BIT_SET_MACID4_H_V1_8822C(x, v)                                        \
+	(BIT_CLEAR_MACID4_H_V1_8822C(x) | BIT_MACID4_H_V1_8822C(v))
+
+/* 2 REG_BSSID4_8822C (BSSID4 REGISTER) */
+
+#define BIT_SHIFT_BSSID4_V1_8822C 0
+#define BIT_MASK_BSSID4_V1_8822C 0xffffffffL
+#define BIT_BSSID4_V1_8822C(x)                                                 \
+	(((x) & BIT_MASK_BSSID4_V1_8822C) << BIT_SHIFT_BSSID4_V1_8822C)
+#define BITS_BSSID4_V1_8822C                                                   \
+	(BIT_MASK_BSSID4_V1_8822C << BIT_SHIFT_BSSID4_V1_8822C)
+#define BIT_CLEAR_BSSID4_V1_8822C(x) ((x) & (~BITS_BSSID4_V1_8822C))
+#define BIT_GET_BSSID4_V1_8822C(x)                                             \
+	(((x) >> BIT_SHIFT_BSSID4_V1_8822C) & BIT_MASK_BSSID4_V1_8822C)
+#define BIT_SET_BSSID4_V1_8822C(x, v)                                          \
+	(BIT_CLEAR_BSSID4_V1_8822C(x) | BIT_BSSID4_V1_8822C(v))
+
+/* 2 REG_BSSID4_H_8822C (BSSID4 REGISTER) */
+
+#define BIT_SHIFT_BSSID4_H_V1_8822C 0
+#define BIT_MASK_BSSID4_H_V1_8822C 0xffff
+#define BIT_BSSID4_H_V1_8822C(x)                                               \
+	(((x) & BIT_MASK_BSSID4_H_V1_8822C) << BIT_SHIFT_BSSID4_H_V1_8822C)
+#define BITS_BSSID4_H_V1_8822C                                                 \
+	(BIT_MASK_BSSID4_H_V1_8822C << BIT_SHIFT_BSSID4_H_V1_8822C)
+#define BIT_CLEAR_BSSID4_H_V1_8822C(x) ((x) & (~BITS_BSSID4_H_V1_8822C))
+#define BIT_GET_BSSID4_H_V1_8822C(x)                                           \
+	(((x) >> BIT_SHIFT_BSSID4_H_V1_8822C) & BIT_MASK_BSSID4_H_V1_8822C)
+#define BIT_SET_BSSID4_H_V1_8822C(x, v)                                        \
+	(BIT_CLEAR_BSSID4_H_V1_8822C(x) | BIT_BSSID4_H_V1_8822C(v))
+
+/* 2 REG_NOA_REPORT_8822C */
+
+/* 2 REG_NOA_REPORT_1_8822C */
+
+/* 2 REG_NOA_REPORT_2_8822C */
+
+/* 2 REG_NOA_REPORT_3_8822C */
+
+/* 2 REG_PWRBIT_SETTING_8822C */
+#define BIT_CLI3_WMAC_TCRPWRMGT_HWCTL_EN_8822C BIT(15)
+#define BIT_CLI3_WMAC_TCRPWRMGT_HWDATA_EN_8822C BIT(14)
+#define BIT_CLI3_WMAC_TCRPWRMGT_HWACT_EN_8822C BIT(13)
+#define BIT_CLI3_PWR_ST_V1_8822C BIT(12)
+#define BIT_CLI2_WMAC_TCRPWRMGT_HWCTL_EN_8822C BIT(11)
+#define BIT_CLI2_WMAC_TCRPWRMGT_HWDATA_EN_8822C BIT(10)
+#define BIT_CLI2_WMAC_TCRPWRMGT_HWACT_EN_8822C BIT(9)
+#define BIT_CLI2_PWR_ST_V1_8822C BIT(8)
+#define BIT_CLI1_WMAC_TCRPWRMGT_HWCTL_EN_8822C BIT(7)
+#define BIT_CLI1_WMAC_TCRPWRMGT_HWDATA_EN_8822C BIT(6)
+#define BIT_CLI1_WMAC_TCRPWRMGT_HWACT_EN_8822C BIT(5)
+#define BIT_CLI1_PWR_ST_V1_8822C BIT(4)
+#define BIT_CLI0_WMAC_TCRPWRMGT_HWCTL_EN_8822C BIT(3)
+#define BIT_CLI0_WMAC_TCRPWRMGT_HWDATA_EN_8822C BIT(2)
+#define BIT_CLI0_WMAC_TCRPWRMGT_HWACT_EN_8822C BIT(1)
+#define BIT_CLI0_PWR_ST_V1_8822C BIT(0)
+
+/* 2 REG_GENERAL_OPTION_8822C */
+#define BIT_WMAC_RXRST_NDP_TIMEOUT_8822C BIT(11)
+#define BIT_WMAC_NDP_STANDBY_WAIT_RXEND_8822C BIT(10)
+#define BIT_DUMMY_FCS_READY_MASK_EN_8822C BIT(9)
+#define BIT_RXFIFO_GNT_CUT_8822C BIT(8)
+#define BIT_DUMMY_RXD_FCS_ERROR_MASK_EN_V1_8822C BIT(7)
+#define BIT_WMAC_EXT_DBG_SEL_V1_8822C BIT(6)
+#define BIT_WMAC_FIX_FIRST_MPDU_WITH_PHYSTS_8822C BIT(5)
+#define BIT_RX_DMA_BYPASS_CHECK_DATABYPASS_CHECK_DATA_8822C BIT(4)
+#define BIT_RX_DMA_BYPASS_CHECK_MGTBIT_RX_DMA_BYPASS_CHECK_MGT_8822C BIT(3)
+#define BIT_TXSERV_FIELD_SEL_8822C BIT(2)
+#define BIT_RXVHT_LEN_SEL_8822C BIT(1)
+#define BIT_RXMIC_PROTECT_EN_8822C BIT(0)
+
+/* 2 REG_RSVD_8822C */
+
+/* 2 REG_RSVD_8822C */
+
+/* 2 REG_RSVD_8822C */
+
+/* 2 REG_RSVD_8822C */
+
+/* 2 REG_CSI_RRSR_8822C */
+#define BIT_CSI_LDPC_EN_8822C BIT(29)
+#define BIT_CSI_STBC_EN_8822C BIT(28)
+
+#define BIT_SHIFT_CSI_RRSC_BITMAP_8822C 4
+#define BIT_MASK_CSI_RRSC_BITMAP_8822C 0xffffff
+#define BIT_CSI_RRSC_BITMAP_8822C(x)                                           \
+	(((x) & BIT_MASK_CSI_RRSC_BITMAP_8822C)                                \
+	 << BIT_SHIFT_CSI_RRSC_BITMAP_8822C)
+#define BITS_CSI_RRSC_BITMAP_8822C                                             \
+	(BIT_MASK_CSI_RRSC_BITMAP_8822C << BIT_SHIFT_CSI_RRSC_BITMAP_8822C)
+#define BIT_CLEAR_CSI_RRSC_BITMAP_8822C(x) ((x) & (~BITS_CSI_RRSC_BITMAP_8822C))
+#define BIT_GET_CSI_RRSC_BITMAP_8822C(x)                                       \
+	(((x) >> BIT_SHIFT_CSI_RRSC_BITMAP_8822C) &                            \
+	 BIT_MASK_CSI_RRSC_BITMAP_8822C)
+#define BIT_SET_CSI_RRSC_BITMAP_8822C(x, v)                                    \
+	(BIT_CLEAR_CSI_RRSC_BITMAP_8822C(x) | BIT_CSI_RRSC_BITMAP_8822C(v))
+
+#define BIT_SHIFT_OFDM_LEN_TH_8822C 0
+#define BIT_MASK_OFDM_LEN_TH_8822C 0xf
+#define BIT_OFDM_LEN_TH_8822C(x)                                               \
+	(((x) & BIT_MASK_OFDM_LEN_TH_8822C) << BIT_SHIFT_OFDM_LEN_TH_8822C)
+#define BITS_OFDM_LEN_TH_8822C                                                 \
+	(BIT_MASK_OFDM_LEN_TH_8822C << BIT_SHIFT_OFDM_LEN_TH_8822C)
+#define BIT_CLEAR_OFDM_LEN_TH_8822C(x) ((x) & (~BITS_OFDM_LEN_TH_8822C))
+#define BIT_GET_OFDM_LEN_TH_8822C(x)                                           \
+	(((x) >> BIT_SHIFT_OFDM_LEN_TH_8822C) & BIT_MASK_OFDM_LEN_TH_8822C)
+#define BIT_SET_OFDM_LEN_TH_8822C(x, v)                                        \
+	(BIT_CLEAR_OFDM_LEN_TH_8822C(x) | BIT_OFDM_LEN_TH_8822C(v))
+
+/* 2 REG_MU_BF_OPTION_8822C */
+#define BIT_WMAC_RESP_NONSTA1_DIS_8822C BIT(7)
+#define BIT_WMAC_TXMU_ACKPOLICY_EN_8822C BIT(6)
+
+#define BIT_SHIFT_WMAC_TXMU_ACKPOLICY_8822C 4
+#define BIT_MASK_WMAC_TXMU_ACKPOLICY_8822C 0x3
+#define BIT_WMAC_TXMU_ACKPOLICY_8822C(x)                                       \
+	(((x) & BIT_MASK_WMAC_TXMU_ACKPOLICY_8822C)                            \
+	 << BIT_SHIFT_WMAC_TXMU_ACKPOLICY_8822C)
+#define BITS_WMAC_TXMU_ACKPOLICY_8822C                                         \
+	(BIT_MASK_WMAC_TXMU_ACKPOLICY_8822C                                    \
+	 << BIT_SHIFT_WMAC_TXMU_ACKPOLICY_8822C)
+#define BIT_CLEAR_WMAC_TXMU_ACKPOLICY_8822C(x)                                 \
+	((x) & (~BITS_WMAC_TXMU_ACKPOLICY_8822C))
+#define BIT_GET_WMAC_TXMU_ACKPOLICY_8822C(x)                                   \
+	(((x) >> BIT_SHIFT_WMAC_TXMU_ACKPOLICY_8822C) &                        \
+	 BIT_MASK_WMAC_TXMU_ACKPOLICY_8822C)
+#define BIT_SET_WMAC_TXMU_ACKPOLICY_8822C(x, v)                                \
+	(BIT_CLEAR_WMAC_TXMU_ACKPOLICY_8822C(x) |                              \
+	 BIT_WMAC_TXMU_ACKPOLICY_8822C(v))
+
+#define BIT_SHIFT_WMAC_MU_BFEE_PORT_SEL_8822C 1
+#define BIT_MASK_WMAC_MU_BFEE_PORT_SEL_8822C 0x7
+#define BIT_WMAC_MU_BFEE_PORT_SEL_8822C(x)                                     \
+	(((x) & BIT_MASK_WMAC_MU_BFEE_PORT_SEL_8822C)                          \
+	 << BIT_SHIFT_WMAC_MU_BFEE_PORT_SEL_8822C)
+#define BITS_WMAC_MU_BFEE_PORT_SEL_8822C                                       \
+	(BIT_MASK_WMAC_MU_BFEE_PORT_SEL_8822C                                  \
+	 << BIT_SHIFT_WMAC_MU_BFEE_PORT_SEL_8822C)
+#define BIT_CLEAR_WMAC_MU_BFEE_PORT_SEL_8822C(x)                               \
+	((x) & (~BITS_WMAC_MU_BFEE_PORT_SEL_8822C))
+#define BIT_GET_WMAC_MU_BFEE_PORT_SEL_8822C(x)                                 \
+	(((x) >> BIT_SHIFT_WMAC_MU_BFEE_PORT_SEL_8822C) &                      \
+	 BIT_MASK_WMAC_MU_BFEE_PORT_SEL_8822C)
+#define BIT_SET_WMAC_MU_BFEE_PORT_SEL_8822C(x, v)                              \
+	(BIT_CLEAR_WMAC_MU_BFEE_PORT_SEL_8822C(x) |                            \
+	 BIT_WMAC_MU_BFEE_PORT_SEL_8822C(v))
+
+#define BIT_WMAC_MU_BFEE_DIS_8822C BIT(0)
+
+/* 2 REG_WMAC_PAUSE_BB_CLR_TH_8822C */
+
+#define BIT_SHIFT_WMAC_PAUSE_BB_CLR_TH_8822C 0
+#define BIT_MASK_WMAC_PAUSE_BB_CLR_TH_8822C 0xff
+#define BIT_WMAC_PAUSE_BB_CLR_TH_8822C(x)                                      \
+	(((x) & BIT_MASK_WMAC_PAUSE_BB_CLR_TH_8822C)                           \
+	 << BIT_SHIFT_WMAC_PAUSE_BB_CLR_TH_8822C)
+#define BITS_WMAC_PAUSE_BB_CLR_TH_8822C                                        \
+	(BIT_MASK_WMAC_PAUSE_BB_CLR_TH_8822C                                   \
+	 << BIT_SHIFT_WMAC_PAUSE_BB_CLR_TH_8822C)
+#define BIT_CLEAR_WMAC_PAUSE_BB_CLR_TH_8822C(x)                                \
+	((x) & (~BITS_WMAC_PAUSE_BB_CLR_TH_8822C))
+#define BIT_GET_WMAC_PAUSE_BB_CLR_TH_8822C(x)                                  \
+	(((x) >> BIT_SHIFT_WMAC_PAUSE_BB_CLR_TH_8822C) &                       \
+	 BIT_MASK_WMAC_PAUSE_BB_CLR_TH_8822C)
+#define BIT_SET_WMAC_PAUSE_BB_CLR_TH_8822C(x, v)                               \
+	(BIT_CLEAR_WMAC_PAUSE_BB_CLR_TH_8822C(x) |                             \
+	 BIT_WMAC_PAUSE_BB_CLR_TH_8822C(v))
+
+/* 2 REG__WMAC_MULBK_BUF_8822C */
+
+#define BIT_SHIFT_WMAC_MULBK_PAGE_SIZE_8822C 0
+#define BIT_MASK_WMAC_MULBK_PAGE_SIZE_8822C 0xff
+#define BIT_WMAC_MULBK_PAGE_SIZE_8822C(x)                                      \
+	(((x) & BIT_MASK_WMAC_MULBK_PAGE_SIZE_8822C)                           \
+	 << BIT_SHIFT_WMAC_MULBK_PAGE_SIZE_8822C)
+#define BITS_WMAC_MULBK_PAGE_SIZE_8822C                                        \
+	(BIT_MASK_WMAC_MULBK_PAGE_SIZE_8822C                                   \
+	 << BIT_SHIFT_WMAC_MULBK_PAGE_SIZE_8822C)
+#define BIT_CLEAR_WMAC_MULBK_PAGE_SIZE_8822C(x)                                \
+	((x) & (~BITS_WMAC_MULBK_PAGE_SIZE_8822C))
+#define BIT_GET_WMAC_MULBK_PAGE_SIZE_8822C(x)                                  \
+	(((x) >> BIT_SHIFT_WMAC_MULBK_PAGE_SIZE_8822C) &                       \
+	 BIT_MASK_WMAC_MULBK_PAGE_SIZE_8822C)
+#define BIT_SET_WMAC_MULBK_PAGE_SIZE_8822C(x, v)                               \
+	(BIT_CLEAR_WMAC_MULBK_PAGE_SIZE_8822C(x) |                             \
+	 BIT_WMAC_MULBK_PAGE_SIZE_8822C(v))
+
+/* 2 REG_WMAC_MU_OPTION_8822C */
+
+/* 2 REG_WMAC_MU_BF_CTL_8822C */
+#define BIT_WMAC_INVLD_BFPRT_CHK_8822C BIT(15)
+#define BIT_WMAC_RETXBFRPTSEQ_UPD_8822C BIT(14)
+
+#define BIT_SHIFT_WMAC_MU_BFRPTSEG_SEL_8822C 12
+#define BIT_MASK_WMAC_MU_BFRPTSEG_SEL_8822C 0x3
+#define BIT_WMAC_MU_BFRPTSEG_SEL_8822C(x)                                      \
+	(((x) & BIT_MASK_WMAC_MU_BFRPTSEG_SEL_8822C)                           \
+	 << BIT_SHIFT_WMAC_MU_BFRPTSEG_SEL_8822C)
+#define BITS_WMAC_MU_BFRPTSEG_SEL_8822C                                        \
+	(BIT_MASK_WMAC_MU_BFRPTSEG_SEL_8822C                                   \
+	 << BIT_SHIFT_WMAC_MU_BFRPTSEG_SEL_8822C)
+#define BIT_CLEAR_WMAC_MU_BFRPTSEG_SEL_8822C(x)                                \
+	((x) & (~BITS_WMAC_MU_BFRPTSEG_SEL_8822C))
+#define BIT_GET_WMAC_MU_BFRPTSEG_SEL_8822C(x)                                  \
+	(((x) >> BIT_SHIFT_WMAC_MU_BFRPTSEG_SEL_8822C) &                       \
+	 BIT_MASK_WMAC_MU_BFRPTSEG_SEL_8822C)
+#define BIT_SET_WMAC_MU_BFRPTSEG_SEL_8822C(x, v)                               \
+	(BIT_CLEAR_WMAC_MU_BFRPTSEG_SEL_8822C(x) |                             \
+	 BIT_WMAC_MU_BFRPTSEG_SEL_8822C(v))
+
+#define BIT_SHIFT_WMAC_MU_BF_MYAID_8822C 0
+#define BIT_MASK_WMAC_MU_BF_MYAID_8822C 0xfff
+#define BIT_WMAC_MU_BF_MYAID_8822C(x)                                          \
+	(((x) & BIT_MASK_WMAC_MU_BF_MYAID_8822C)                               \
+	 << BIT_SHIFT_WMAC_MU_BF_MYAID_8822C)
+#define BITS_WMAC_MU_BF_MYAID_8822C                                            \
+	(BIT_MASK_WMAC_MU_BF_MYAID_8822C << BIT_SHIFT_WMAC_MU_BF_MYAID_8822C)
+#define BIT_CLEAR_WMAC_MU_BF_MYAID_8822C(x)                                    \
+	((x) & (~BITS_WMAC_MU_BF_MYAID_8822C))
+#define BIT_GET_WMAC_MU_BF_MYAID_8822C(x)                                      \
+	(((x) >> BIT_SHIFT_WMAC_MU_BF_MYAID_8822C) &                           \
+	 BIT_MASK_WMAC_MU_BF_MYAID_8822C)
+#define BIT_SET_WMAC_MU_BF_MYAID_8822C(x, v)                                   \
+	(BIT_CLEAR_WMAC_MU_BF_MYAID_8822C(x) | BIT_WMAC_MU_BF_MYAID_8822C(v))
+
+/* 2 REG_WMAC_MU_BFRPT_PARA_8822C */
+
+#define BIT_SHIFT_BFRPT_PARA_USERID_SEL_V1_8822C 13
+#define BIT_MASK_BFRPT_PARA_USERID_SEL_V1_8822C 0x7
+#define BIT_BFRPT_PARA_USERID_SEL_V1_8822C(x)                                  \
+	(((x) & BIT_MASK_BFRPT_PARA_USERID_SEL_V1_8822C)                       \
+	 << BIT_SHIFT_BFRPT_PARA_USERID_SEL_V1_8822C)
+#define BITS_BFRPT_PARA_USERID_SEL_V1_8822C                                    \
+	(BIT_MASK_BFRPT_PARA_USERID_SEL_V1_8822C                               \
+	 << BIT_SHIFT_BFRPT_PARA_USERID_SEL_V1_8822C)
+#define BIT_CLEAR_BFRPT_PARA_USERID_SEL_V1_8822C(x)                            \
+	((x) & (~BITS_BFRPT_PARA_USERID_SEL_V1_8822C))
+#define BIT_GET_BFRPT_PARA_USERID_SEL_V1_8822C(x)                              \
+	(((x) >> BIT_SHIFT_BFRPT_PARA_USERID_SEL_V1_8822C) &                   \
+	 BIT_MASK_BFRPT_PARA_USERID_SEL_V1_8822C)
+#define BIT_SET_BFRPT_PARA_USERID_SEL_V1_8822C(x, v)                           \
+	(BIT_CLEAR_BFRPT_PARA_USERID_SEL_V1_8822C(x) |                         \
+	 BIT_BFRPT_PARA_USERID_SEL_V1_8822C(v))
+
+#define BIT_SHIFT_BFRPT_PARA_V1_8822C 0
+#define BIT_MASK_BFRPT_PARA_V1_8822C 0x1fff
+#define BIT_BFRPT_PARA_V1_8822C(x)                                             \
+	(((x) & BIT_MASK_BFRPT_PARA_V1_8822C) << BIT_SHIFT_BFRPT_PARA_V1_8822C)
+#define BITS_BFRPT_PARA_V1_8822C                                               \
+	(BIT_MASK_BFRPT_PARA_V1_8822C << BIT_SHIFT_BFRPT_PARA_V1_8822C)
+#define BIT_CLEAR_BFRPT_PARA_V1_8822C(x) ((x) & (~BITS_BFRPT_PARA_V1_8822C))
+#define BIT_GET_BFRPT_PARA_V1_8822C(x)                                         \
+	(((x) >> BIT_SHIFT_BFRPT_PARA_V1_8822C) & BIT_MASK_BFRPT_PARA_V1_8822C)
+#define BIT_SET_BFRPT_PARA_V1_8822C(x, v)                                      \
+	(BIT_CLEAR_BFRPT_PARA_V1_8822C(x) | BIT_BFRPT_PARA_V1_8822C(v))
+
+/* 2 REG_WMAC_ASSOCIATED_MU_BFMEE2_8822C */
+#define BIT_STATUS_BFEE2_8822C BIT(10)
+#define BIT_WMAC_MU_BFEE2_EN_8822C BIT(9)
+
+#define BIT_SHIFT_WMAC_MU_BFEE2_AID_8822C 0
+#define BIT_MASK_WMAC_MU_BFEE2_AID_8822C 0x1ff
+#define BIT_WMAC_MU_BFEE2_AID_8822C(x)                                         \
+	(((x) & BIT_MASK_WMAC_MU_BFEE2_AID_8822C)                              \
+	 << BIT_SHIFT_WMAC_MU_BFEE2_AID_8822C)
+#define BITS_WMAC_MU_BFEE2_AID_8822C                                           \
+	(BIT_MASK_WMAC_MU_BFEE2_AID_8822C << BIT_SHIFT_WMAC_MU_BFEE2_AID_8822C)
+#define BIT_CLEAR_WMAC_MU_BFEE2_AID_8822C(x)                                   \
+	((x) & (~BITS_WMAC_MU_BFEE2_AID_8822C))
+#define BIT_GET_WMAC_MU_BFEE2_AID_8822C(x)                                     \
+	(((x) >> BIT_SHIFT_WMAC_MU_BFEE2_AID_8822C) &                          \
+	 BIT_MASK_WMAC_MU_BFEE2_AID_8822C)
+#define BIT_SET_WMAC_MU_BFEE2_AID_8822C(x, v)                                  \
+	(BIT_CLEAR_WMAC_MU_BFEE2_AID_8822C(x) | BIT_WMAC_MU_BFEE2_AID_8822C(v))
+
+/* 2 REG_WMAC_ASSOCIATED_MU_BFMEE3_8822C */
+#define BIT_STATUS_BFEE3_8822C BIT(10)
+#define BIT_WMAC_MU_BFEE3_EN_8822C BIT(9)
+
+#define BIT_SHIFT_WMAC_MU_BFEE3_AID_8822C 0
+#define BIT_MASK_WMAC_MU_BFEE3_AID_8822C 0x1ff
+#define BIT_WMAC_MU_BFEE3_AID_8822C(x)                                         \
+	(((x) & BIT_MASK_WMAC_MU_BFEE3_AID_8822C)                              \
+	 << BIT_SHIFT_WMAC_MU_BFEE3_AID_8822C)
+#define BITS_WMAC_MU_BFEE3_AID_8822C                                           \
+	(BIT_MASK_WMAC_MU_BFEE3_AID_8822C << BIT_SHIFT_WMAC_MU_BFEE3_AID_8822C)
+#define BIT_CLEAR_WMAC_MU_BFEE3_AID_8822C(x)                                   \
+	((x) & (~BITS_WMAC_MU_BFEE3_AID_8822C))
+#define BIT_GET_WMAC_MU_BFEE3_AID_8822C(x)                                     \
+	(((x) >> BIT_SHIFT_WMAC_MU_BFEE3_AID_8822C) &                          \
+	 BIT_MASK_WMAC_MU_BFEE3_AID_8822C)
+#define BIT_SET_WMAC_MU_BFEE3_AID_8822C(x, v)                                  \
+	(BIT_CLEAR_WMAC_MU_BFEE3_AID_8822C(x) | BIT_WMAC_MU_BFEE3_AID_8822C(v))
+
+/* 2 REG_WMAC_ASSOCIATED_MU_BFMEE4_8822C */
+#define BIT_STATUS_BFEE4_8822C BIT(10)
+#define BIT_WMAC_MU_BFEE4_EN_8822C BIT(9)
+
+#define BIT_SHIFT_WMAC_MU_BFEE4_AID_8822C 0
+#define BIT_MASK_WMAC_MU_BFEE4_AID_8822C 0x1ff
+#define BIT_WMAC_MU_BFEE4_AID_8822C(x)                                         \
+	(((x) & BIT_MASK_WMAC_MU_BFEE4_AID_8822C)                              \
+	 << BIT_SHIFT_WMAC_MU_BFEE4_AID_8822C)
+#define BITS_WMAC_MU_BFEE4_AID_8822C                                           \
+	(BIT_MASK_WMAC_MU_BFEE4_AID_8822C << BIT_SHIFT_WMAC_MU_BFEE4_AID_8822C)
+#define BIT_CLEAR_WMAC_MU_BFEE4_AID_8822C(x)                                   \
+	((x) & (~BITS_WMAC_MU_BFEE4_AID_8822C))
+#define BIT_GET_WMAC_MU_BFEE4_AID_8822C(x)                                     \
+	(((x) >> BIT_SHIFT_WMAC_MU_BFEE4_AID_8822C) &                          \
+	 BIT_MASK_WMAC_MU_BFEE4_AID_8822C)
+#define BIT_SET_WMAC_MU_BFEE4_AID_8822C(x, v)                                  \
+	(BIT_CLEAR_WMAC_MU_BFEE4_AID_8822C(x) | BIT_WMAC_MU_BFEE4_AID_8822C(v))
+
+/* 2 REG_WMAC_ASSOCIATED_MU_BFMEE5_8822C */
+#define BIT_BIT_STATUS_BFEE5_8822C BIT(10)
+#define BIT_WMAC_MU_BFEE5_EN_8822C BIT(9)
+
+#define BIT_SHIFT_WMAC_MU_BFEE5_AID_8822C 0
+#define BIT_MASK_WMAC_MU_BFEE5_AID_8822C 0x1ff
+#define BIT_WMAC_MU_BFEE5_AID_8822C(x)                                         \
+	(((x) & BIT_MASK_WMAC_MU_BFEE5_AID_8822C)                              \
+	 << BIT_SHIFT_WMAC_MU_BFEE5_AID_8822C)
+#define BITS_WMAC_MU_BFEE5_AID_8822C                                           \
+	(BIT_MASK_WMAC_MU_BFEE5_AID_8822C << BIT_SHIFT_WMAC_MU_BFEE5_AID_8822C)
+#define BIT_CLEAR_WMAC_MU_BFEE5_AID_8822C(x)                                   \
+	((x) & (~BITS_WMAC_MU_BFEE5_AID_8822C))
+#define BIT_GET_WMAC_MU_BFEE5_AID_8822C(x)                                     \
+	(((x) >> BIT_SHIFT_WMAC_MU_BFEE5_AID_8822C) &                          \
+	 BIT_MASK_WMAC_MU_BFEE5_AID_8822C)
+#define BIT_SET_WMAC_MU_BFEE5_AID_8822C(x, v)                                  \
+	(BIT_CLEAR_WMAC_MU_BFEE5_AID_8822C(x) | BIT_WMAC_MU_BFEE5_AID_8822C(v))
+
+/* 2 REG_WMAC_ASSOCIATED_MU_BFMEE6_8822C */
+#define BIT_STATUS_BFEE6_8822C BIT(10)
+#define BIT_WMAC_MU_BFEE6_EN_8822C BIT(9)
+
+#define BIT_SHIFT_WMAC_MU_BFEE6_AID_8822C 0
+#define BIT_MASK_WMAC_MU_BFEE6_AID_8822C 0x1ff
+#define BIT_WMAC_MU_BFEE6_AID_8822C(x)                                         \
+	(((x) & BIT_MASK_WMAC_MU_BFEE6_AID_8822C)                              \
+	 << BIT_SHIFT_WMAC_MU_BFEE6_AID_8822C)
+#define BITS_WMAC_MU_BFEE6_AID_8822C                                           \
+	(BIT_MASK_WMAC_MU_BFEE6_AID_8822C << BIT_SHIFT_WMAC_MU_BFEE6_AID_8822C)
+#define BIT_CLEAR_WMAC_MU_BFEE6_AID_8822C(x)                                   \
+	((x) & (~BITS_WMAC_MU_BFEE6_AID_8822C))
+#define BIT_GET_WMAC_MU_BFEE6_AID_8822C(x)                                     \
+	(((x) >> BIT_SHIFT_WMAC_MU_BFEE6_AID_8822C) &                          \
+	 BIT_MASK_WMAC_MU_BFEE6_AID_8822C)
+#define BIT_SET_WMAC_MU_BFEE6_AID_8822C(x, v)                                  \
+	(BIT_CLEAR_WMAC_MU_BFEE6_AID_8822C(x) | BIT_WMAC_MU_BFEE6_AID_8822C(v))
+
+/* 2 REG_WMAC_ASSOCIATED_MU_BFMEE7_8822C */
+#define BIT_STATUS_BFEE7_8822C BIT(10)
+#define BIT_WMAC_MU_BFEE7_EN_8822C BIT(9)
+
+#define BIT_SHIFT_WMAC_MU_BFEE7_AID_8822C 0
+#define BIT_MASK_WMAC_MU_BFEE7_AID_8822C 0x1ff
+#define BIT_WMAC_MU_BFEE7_AID_8822C(x)                                         \
+	(((x) & BIT_MASK_WMAC_MU_BFEE7_AID_8822C)                              \
+	 << BIT_SHIFT_WMAC_MU_BFEE7_AID_8822C)
+#define BITS_WMAC_MU_BFEE7_AID_8822C                                           \
+	(BIT_MASK_WMAC_MU_BFEE7_AID_8822C << BIT_SHIFT_WMAC_MU_BFEE7_AID_8822C)
+#define BIT_CLEAR_WMAC_MU_BFEE7_AID_8822C(x)                                   \
+	((x) & (~BITS_WMAC_MU_BFEE7_AID_8822C))
+#define BIT_GET_WMAC_MU_BFEE7_AID_8822C(x)                                     \
+	(((x) >> BIT_SHIFT_WMAC_MU_BFEE7_AID_8822C) &                          \
+	 BIT_MASK_WMAC_MU_BFEE7_AID_8822C)
+#define BIT_SET_WMAC_MU_BFEE7_AID_8822C(x, v)                                  \
+	(BIT_CLEAR_WMAC_MU_BFEE7_AID_8822C(x) | BIT_WMAC_MU_BFEE7_AID_8822C(v))
+
+/* 2 REG_WMAC_BB_STOP_RX_COUNTER_8822C */
+#define BIT_RST_ALL_COUNTER_8822C BIT(31)
+
+#define BIT_SHIFT_ABORT_RX_VBON_COUNTER_8822C 16
+#define BIT_MASK_ABORT_RX_VBON_COUNTER_8822C 0xff
+#define BIT_ABORT_RX_VBON_COUNTER_8822C(x)                                     \
+	(((x) & BIT_MASK_ABORT_RX_VBON_COUNTER_8822C)                          \
+	 << BIT_SHIFT_ABORT_RX_VBON_COUNTER_8822C)
+#define BITS_ABORT_RX_VBON_COUNTER_8822C                                       \
+	(BIT_MASK_ABORT_RX_VBON_COUNTER_8822C                                  \
+	 << BIT_SHIFT_ABORT_RX_VBON_COUNTER_8822C)
+#define BIT_CLEAR_ABORT_RX_VBON_COUNTER_8822C(x)                               \
+	((x) & (~BITS_ABORT_RX_VBON_COUNTER_8822C))
+#define BIT_GET_ABORT_RX_VBON_COUNTER_8822C(x)                                 \
+	(((x) >> BIT_SHIFT_ABORT_RX_VBON_COUNTER_8822C) &                      \
+	 BIT_MASK_ABORT_RX_VBON_COUNTER_8822C)
+#define BIT_SET_ABORT_RX_VBON_COUNTER_8822C(x, v)                              \
+	(BIT_CLEAR_ABORT_RX_VBON_COUNTER_8822C(x) |                            \
+	 BIT_ABORT_RX_VBON_COUNTER_8822C(v))
+
+#define BIT_SHIFT_ABORT_RX_RDRDY_COUNTER_8822C 8
+#define BIT_MASK_ABORT_RX_RDRDY_COUNTER_8822C 0xff
+#define BIT_ABORT_RX_RDRDY_COUNTER_8822C(x)                                    \
+	(((x) & BIT_MASK_ABORT_RX_RDRDY_COUNTER_8822C)                         \
+	 << BIT_SHIFT_ABORT_RX_RDRDY_COUNTER_8822C)
+#define BITS_ABORT_RX_RDRDY_COUNTER_8822C                                      \
+	(BIT_MASK_ABORT_RX_RDRDY_COUNTER_8822C                                 \
+	 << BIT_SHIFT_ABORT_RX_RDRDY_COUNTER_8822C)
+#define BIT_CLEAR_ABORT_RX_RDRDY_COUNTER_8822C(x)                              \
+	((x) & (~BITS_ABORT_RX_RDRDY_COUNTER_8822C))
+#define BIT_GET_ABORT_RX_RDRDY_COUNTER_8822C(x)                                \
+	(((x) >> BIT_SHIFT_ABORT_RX_RDRDY_COUNTER_8822C) &                     \
+	 BIT_MASK_ABORT_RX_RDRDY_COUNTER_8822C)
+#define BIT_SET_ABORT_RX_RDRDY_COUNTER_8822C(x, v)                             \
+	(BIT_CLEAR_ABORT_RX_RDRDY_COUNTER_8822C(x) |                           \
+	 BIT_ABORT_RX_RDRDY_COUNTER_8822C(v))
+
+#define BIT_SHIFT_VBON_EARLY_FALLING_COUNTER_8822C 0
+#define BIT_MASK_VBON_EARLY_FALLING_COUNTER_8822C 0xff
+#define BIT_VBON_EARLY_FALLING_COUNTER_8822C(x)                                \
+	(((x) & BIT_MASK_VBON_EARLY_FALLING_COUNTER_8822C)                     \
+	 << BIT_SHIFT_VBON_EARLY_FALLING_COUNTER_8822C)
+#define BITS_VBON_EARLY_FALLING_COUNTER_8822C                                  \
+	(BIT_MASK_VBON_EARLY_FALLING_COUNTER_8822C                             \
+	 << BIT_SHIFT_VBON_EARLY_FALLING_COUNTER_8822C)
+#define BIT_CLEAR_VBON_EARLY_FALLING_COUNTER_8822C(x)                          \
+	((x) & (~BITS_VBON_EARLY_FALLING_COUNTER_8822C))
+#define BIT_GET_VBON_EARLY_FALLING_COUNTER_8822C(x)                            \
+	(((x) >> BIT_SHIFT_VBON_EARLY_FALLING_COUNTER_8822C) &                 \
+	 BIT_MASK_VBON_EARLY_FALLING_COUNTER_8822C)
+#define BIT_SET_VBON_EARLY_FALLING_COUNTER_8822C(x, v)                         \
+	(BIT_CLEAR_VBON_EARLY_FALLING_COUNTER_8822C(x) |                       \
+	 BIT_VBON_EARLY_FALLING_COUNTER_8822C(v))
+
+/* 2 REG_WMAC_PLCP_MONITOR_8822C */
+#define BIT_WMAC_PLCP_TRX_SEL_8822C BIT(31)
+
+#define BIT_SHIFT_WMAC_PLCP_RDSIG_SEL_8822C 28
+#define BIT_MASK_WMAC_PLCP_RDSIG_SEL_8822C 0x7
+#define BIT_WMAC_PLCP_RDSIG_SEL_8822C(x)                                       \
+	(((x) & BIT_MASK_WMAC_PLCP_RDSIG_SEL_8822C)                            \
+	 << BIT_SHIFT_WMAC_PLCP_RDSIG_SEL_8822C)
+#define BITS_WMAC_PLCP_RDSIG_SEL_8822C                                         \
+	(BIT_MASK_WMAC_PLCP_RDSIG_SEL_8822C                                    \
+	 << BIT_SHIFT_WMAC_PLCP_RDSIG_SEL_8822C)
+#define BIT_CLEAR_WMAC_PLCP_RDSIG_SEL_8822C(x)                                 \
+	((x) & (~BITS_WMAC_PLCP_RDSIG_SEL_8822C))
+#define BIT_GET_WMAC_PLCP_RDSIG_SEL_8822C(x)                                   \
+	(((x) >> BIT_SHIFT_WMAC_PLCP_RDSIG_SEL_8822C) &                        \
+	 BIT_MASK_WMAC_PLCP_RDSIG_SEL_8822C)
+#define BIT_SET_WMAC_PLCP_RDSIG_SEL_8822C(x, v)                                \
+	(BIT_CLEAR_WMAC_PLCP_RDSIG_SEL_8822C(x) |                              \
+	 BIT_WMAC_PLCP_RDSIG_SEL_8822C(v))
+
+#define BIT_SHIFT_WMAC_RATE_IDX_8822C 24
+#define BIT_MASK_WMAC_RATE_IDX_8822C 0xf
+#define BIT_WMAC_RATE_IDX_8822C(x)                                             \
+	(((x) & BIT_MASK_WMAC_RATE_IDX_8822C) << BIT_SHIFT_WMAC_RATE_IDX_8822C)
+#define BITS_WMAC_RATE_IDX_8822C                                               \
+	(BIT_MASK_WMAC_RATE_IDX_8822C << BIT_SHIFT_WMAC_RATE_IDX_8822C)
+#define BIT_CLEAR_WMAC_RATE_IDX_8822C(x) ((x) & (~BITS_WMAC_RATE_IDX_8822C))
+#define BIT_GET_WMAC_RATE_IDX_8822C(x)                                         \
+	(((x) >> BIT_SHIFT_WMAC_RATE_IDX_8822C) & BIT_MASK_WMAC_RATE_IDX_8822C)
+#define BIT_SET_WMAC_RATE_IDX_8822C(x, v)                                      \
+	(BIT_CLEAR_WMAC_RATE_IDX_8822C(x) | BIT_WMAC_RATE_IDX_8822C(v))
+
+#define BIT_SHIFT_WMAC_PLCP_RDSIG_8822C 0
+#define BIT_MASK_WMAC_PLCP_RDSIG_8822C 0xffffff
+#define BIT_WMAC_PLCP_RDSIG_8822C(x)                                           \
+	(((x) & BIT_MASK_WMAC_PLCP_RDSIG_8822C)                                \
+	 << BIT_SHIFT_WMAC_PLCP_RDSIG_8822C)
+#define BITS_WMAC_PLCP_RDSIG_8822C                                             \
+	(BIT_MASK_WMAC_PLCP_RDSIG_8822C << BIT_SHIFT_WMAC_PLCP_RDSIG_8822C)
+#define BIT_CLEAR_WMAC_PLCP_RDSIG_8822C(x) ((x) & (~BITS_WMAC_PLCP_RDSIG_8822C))
+#define BIT_GET_WMAC_PLCP_RDSIG_8822C(x)                                       \
+	(((x) >> BIT_SHIFT_WMAC_PLCP_RDSIG_8822C) &                            \
+	 BIT_MASK_WMAC_PLCP_RDSIG_8822C)
+#define BIT_SET_WMAC_PLCP_RDSIG_8822C(x, v)                                    \
+	(BIT_CLEAR_WMAC_PLCP_RDSIG_8822C(x) | BIT_WMAC_PLCP_RDSIG_8822C(v))
+
+/* 2 REG_WMAC_PLCP_MONITOR_MUTX_8822C */
+#define BIT_WMAC_MUTX_IDX_8822C BIT(24)
+
+#define BIT_SHIFT_WMAC_PLCP_RDSIG_8822C 0
+#define BIT_MASK_WMAC_PLCP_RDSIG_8822C 0xffffff
+#define BIT_WMAC_PLCP_RDSIG_8822C(x)                                           \
+	(((x) & BIT_MASK_WMAC_PLCP_RDSIG_8822C)                                \
+	 << BIT_SHIFT_WMAC_PLCP_RDSIG_8822C)
+#define BITS_WMAC_PLCP_RDSIG_8822C                                             \
+	(BIT_MASK_WMAC_PLCP_RDSIG_8822C << BIT_SHIFT_WMAC_PLCP_RDSIG_8822C)
+#define BIT_CLEAR_WMAC_PLCP_RDSIG_8822C(x) ((x) & (~BITS_WMAC_PLCP_RDSIG_8822C))
+#define BIT_GET_WMAC_PLCP_RDSIG_8822C(x)                                       \
+	(((x) >> BIT_SHIFT_WMAC_PLCP_RDSIG_8822C) &                            \
+	 BIT_MASK_WMAC_PLCP_RDSIG_8822C)
+#define BIT_SET_WMAC_PLCP_RDSIG_8822C(x, v)                                    \
+	(BIT_CLEAR_WMAC_PLCP_RDSIG_8822C(x) | BIT_WMAC_PLCP_RDSIG_8822C(v))
+
+/* 2 REG_WMAC_CSIDMA_CFG_8822C */
+
+#define BIT_SHIFT_CSI_SEG_SIZE_8822C 16
+#define BIT_MASK_CSI_SEG_SIZE_8822C 0xfff
+#define BIT_CSI_SEG_SIZE_8822C(x)                                              \
+	(((x) & BIT_MASK_CSI_SEG_SIZE_8822C) << BIT_SHIFT_CSI_SEG_SIZE_8822C)
+#define BITS_CSI_SEG_SIZE_8822C                                                \
+	(BIT_MASK_CSI_SEG_SIZE_8822C << BIT_SHIFT_CSI_SEG_SIZE_8822C)
+#define BIT_CLEAR_CSI_SEG_SIZE_8822C(x) ((x) & (~BITS_CSI_SEG_SIZE_8822C))
+#define BIT_GET_CSI_SEG_SIZE_8822C(x)                                          \
+	(((x) >> BIT_SHIFT_CSI_SEG_SIZE_8822C) & BIT_MASK_CSI_SEG_SIZE_8822C)
+#define BIT_SET_CSI_SEG_SIZE_8822C(x, v)                                       \
+	(BIT_CLEAR_CSI_SEG_SIZE_8822C(x) | BIT_CSI_SEG_SIZE_8822C(v))
+
+#define BIT_SHIFT_CSI_START_PAGE_8822C 0
+#define BIT_MASK_CSI_START_PAGE_8822C 0xfff
+#define BIT_CSI_START_PAGE_8822C(x)                                            \
+	(((x) & BIT_MASK_CSI_START_PAGE_8822C)                                 \
+	 << BIT_SHIFT_CSI_START_PAGE_8822C)
+#define BITS_CSI_START_PAGE_8822C                                              \
+	(BIT_MASK_CSI_START_PAGE_8822C << BIT_SHIFT_CSI_START_PAGE_8822C)
+#define BIT_CLEAR_CSI_START_PAGE_8822C(x) ((x) & (~BITS_CSI_START_PAGE_8822C))
+#define BIT_GET_CSI_START_PAGE_8822C(x)                                        \
+	(((x) >> BIT_SHIFT_CSI_START_PAGE_8822C) &                             \
+	 BIT_MASK_CSI_START_PAGE_8822C)
+#define BIT_SET_CSI_START_PAGE_8822C(x, v)                                     \
+	(BIT_CLEAR_CSI_START_PAGE_8822C(x) | BIT_CSI_START_PAGE_8822C(v))
+
+/* 2 REG_TRANSMIT_ADDRSS_0_8822C (TA0 REGISTER) */
+
+#define BIT_SHIFT_TA0_V1_8822C 0
+#define BIT_MASK_TA0_V1_8822C 0xffffffffL
+#define BIT_TA0_V1_8822C(x)                                                    \
+	(((x) & BIT_MASK_TA0_V1_8822C) << BIT_SHIFT_TA0_V1_8822C)
+#define BITS_TA0_V1_8822C (BIT_MASK_TA0_V1_8822C << BIT_SHIFT_TA0_V1_8822C)
+#define BIT_CLEAR_TA0_V1_8822C(x) ((x) & (~BITS_TA0_V1_8822C))
+#define BIT_GET_TA0_V1_8822C(x)                                                \
+	(((x) >> BIT_SHIFT_TA0_V1_8822C) & BIT_MASK_TA0_V1_8822C)
+#define BIT_SET_TA0_V1_8822C(x, v)                                             \
+	(BIT_CLEAR_TA0_V1_8822C(x) | BIT_TA0_V1_8822C(v))
+
+/* 2 REG_TRANSMIT_ADDRSS_0_H_8822C (TA0 REGISTER) */
+
+#define BIT_SHIFT_TA0_H_V1_8822C 0
+#define BIT_MASK_TA0_H_V1_8822C 0xffff
+#define BIT_TA0_H_V1_8822C(x)                                                  \
+	(((x) & BIT_MASK_TA0_H_V1_8822C) << BIT_SHIFT_TA0_H_V1_8822C)
+#define BITS_TA0_H_V1_8822C                                                    \
+	(BIT_MASK_TA0_H_V1_8822C << BIT_SHIFT_TA0_H_V1_8822C)
+#define BIT_CLEAR_TA0_H_V1_8822C(x) ((x) & (~BITS_TA0_H_V1_8822C))
+#define BIT_GET_TA0_H_V1_8822C(x)                                              \
+	(((x) >> BIT_SHIFT_TA0_H_V1_8822C) & BIT_MASK_TA0_H_V1_8822C)
+#define BIT_SET_TA0_H_V1_8822C(x, v)                                           \
+	(BIT_CLEAR_TA0_H_V1_8822C(x) | BIT_TA0_H_V1_8822C(v))
+
+/* 2 REG_TRANSMIT_ADDRSS_1_8822C (TA1 REGISTER) */
+
+#define BIT_SHIFT_TA1_V1_8822C 0
+#define BIT_MASK_TA1_V1_8822C 0xffffffffL
+#define BIT_TA1_V1_8822C(x)                                                    \
+	(((x) & BIT_MASK_TA1_V1_8822C) << BIT_SHIFT_TA1_V1_8822C)
+#define BITS_TA1_V1_8822C (BIT_MASK_TA1_V1_8822C << BIT_SHIFT_TA1_V1_8822C)
+#define BIT_CLEAR_TA1_V1_8822C(x) ((x) & (~BITS_TA1_V1_8822C))
+#define BIT_GET_TA1_V1_8822C(x)                                                \
+	(((x) >> BIT_SHIFT_TA1_V1_8822C) & BIT_MASK_TA1_V1_8822C)
+#define BIT_SET_TA1_V1_8822C(x, v)                                             \
+	(BIT_CLEAR_TA1_V1_8822C(x) | BIT_TA1_V1_8822C(v))
+
+/* 2 REG_TRANSMIT_ADDRSS_1_H_8822C (TA1 REGISTER) */
+
+#define BIT_SHIFT_TA1_H_V1_8822C 0
+#define BIT_MASK_TA1_H_V1_8822C 0xffff
+#define BIT_TA1_H_V1_8822C(x)                                                  \
+	(((x) & BIT_MASK_TA1_H_V1_8822C) << BIT_SHIFT_TA1_H_V1_8822C)
+#define BITS_TA1_H_V1_8822C                                                    \
+	(BIT_MASK_TA1_H_V1_8822C << BIT_SHIFT_TA1_H_V1_8822C)
+#define BIT_CLEAR_TA1_H_V1_8822C(x) ((x) & (~BITS_TA1_H_V1_8822C))
+#define BIT_GET_TA1_H_V1_8822C(x)                                              \
+	(((x) >> BIT_SHIFT_TA1_H_V1_8822C) & BIT_MASK_TA1_H_V1_8822C)
+#define BIT_SET_TA1_H_V1_8822C(x, v)                                           \
+	(BIT_CLEAR_TA1_H_V1_8822C(x) | BIT_TA1_H_V1_8822C(v))
+
+/* 2 REG_TRANSMIT_ADDRSS_2_8822C (TA2 REGISTER) */
+
+#define BIT_SHIFT_TA2_V1_8822C 0
+#define BIT_MASK_TA2_V1_8822C 0xffffffffL
+#define BIT_TA2_V1_8822C(x)                                                    \
+	(((x) & BIT_MASK_TA2_V1_8822C) << BIT_SHIFT_TA2_V1_8822C)
+#define BITS_TA2_V1_8822C (BIT_MASK_TA2_V1_8822C << BIT_SHIFT_TA2_V1_8822C)
+#define BIT_CLEAR_TA2_V1_8822C(x) ((x) & (~BITS_TA2_V1_8822C))
+#define BIT_GET_TA2_V1_8822C(x)                                                \
+	(((x) >> BIT_SHIFT_TA2_V1_8822C) & BIT_MASK_TA2_V1_8822C)
+#define BIT_SET_TA2_V1_8822C(x, v)                                             \
+	(BIT_CLEAR_TA2_V1_8822C(x) | BIT_TA2_V1_8822C(v))
+
+/* 2 REG_TRANSMIT_ADDRSS_2_H_8822C (TA2 REGISTER) */
+
+#define BIT_SHIFT_TA2_H_V1_8822C 0
+#define BIT_MASK_TA2_H_V1_8822C 0xffff
+#define BIT_TA2_H_V1_8822C(x)                                                  \
+	(((x) & BIT_MASK_TA2_H_V1_8822C) << BIT_SHIFT_TA2_H_V1_8822C)
+#define BITS_TA2_H_V1_8822C                                                    \
+	(BIT_MASK_TA2_H_V1_8822C << BIT_SHIFT_TA2_H_V1_8822C)
+#define BIT_CLEAR_TA2_H_V1_8822C(x) ((x) & (~BITS_TA2_H_V1_8822C))
+#define BIT_GET_TA2_H_V1_8822C(x)                                              \
+	(((x) >> BIT_SHIFT_TA2_H_V1_8822C) & BIT_MASK_TA2_H_V1_8822C)
+#define BIT_SET_TA2_H_V1_8822C(x, v)                                           \
+	(BIT_CLEAR_TA2_H_V1_8822C(x) | BIT_TA2_H_V1_8822C(v))
+
+/* 2 REG_TRANSMIT_ADDRSS_3_8822C (TA3 REGISTER) */
+
+#define BIT_SHIFT_TA2_V1_8822C 0
+#define BIT_MASK_TA2_V1_8822C 0xffffffffL
+#define BIT_TA2_V1_8822C(x)                                                    \
+	(((x) & BIT_MASK_TA2_V1_8822C) << BIT_SHIFT_TA2_V1_8822C)
+#define BITS_TA2_V1_8822C (BIT_MASK_TA2_V1_8822C << BIT_SHIFT_TA2_V1_8822C)
+#define BIT_CLEAR_TA2_V1_8822C(x) ((x) & (~BITS_TA2_V1_8822C))
+#define BIT_GET_TA2_V1_8822C(x)                                                \
+	(((x) >> BIT_SHIFT_TA2_V1_8822C) & BIT_MASK_TA2_V1_8822C)
+#define BIT_SET_TA2_V1_8822C(x, v)                                             \
+	(BIT_CLEAR_TA2_V1_8822C(x) | BIT_TA2_V1_8822C(v))
+
+/* 2 REG_TRANSMIT_ADDRSS_3_H_8822C (TA3 REGISTER) */
+
+#define BIT_SHIFT_TA3_H_V1_8822C 0
+#define BIT_MASK_TA3_H_V1_8822C 0xffff
+#define BIT_TA3_H_V1_8822C(x)                                                  \
+	(((x) & BIT_MASK_TA3_H_V1_8822C) << BIT_SHIFT_TA3_H_V1_8822C)
+#define BITS_TA3_H_V1_8822C                                                    \
+	(BIT_MASK_TA3_H_V1_8822C << BIT_SHIFT_TA3_H_V1_8822C)
+#define BIT_CLEAR_TA3_H_V1_8822C(x) ((x) & (~BITS_TA3_H_V1_8822C))
+#define BIT_GET_TA3_H_V1_8822C(x)                                              \
+	(((x) >> BIT_SHIFT_TA3_H_V1_8822C) & BIT_MASK_TA3_H_V1_8822C)
+#define BIT_SET_TA3_H_V1_8822C(x, v)                                           \
+	(BIT_CLEAR_TA3_H_V1_8822C(x) | BIT_TA3_H_V1_8822C(v))
+
+/* 2 REG_TRANSMIT_ADDRSS_4_8822C (TA4 REGISTER) */
+
+#define BIT_SHIFT_TA4_V1_8822C 0
+#define BIT_MASK_TA4_V1_8822C 0xffffffffL
+#define BIT_TA4_V1_8822C(x)                                                    \
+	(((x) & BIT_MASK_TA4_V1_8822C) << BIT_SHIFT_TA4_V1_8822C)
+#define BITS_TA4_V1_8822C (BIT_MASK_TA4_V1_8822C << BIT_SHIFT_TA4_V1_8822C)
+#define BIT_CLEAR_TA4_V1_8822C(x) ((x) & (~BITS_TA4_V1_8822C))
+#define BIT_GET_TA4_V1_8822C(x)                                                \
+	(((x) >> BIT_SHIFT_TA4_V1_8822C) & BIT_MASK_TA4_V1_8822C)
+#define BIT_SET_TA4_V1_8822C(x, v)                                             \
+	(BIT_CLEAR_TA4_V1_8822C(x) | BIT_TA4_V1_8822C(v))
+
+/* 2 REG_TRANSMIT_ADDRSS_4_H_8822C (TA4 REGISTER) */
+
+#define BIT_SHIFT_TA4_H_V1_8822C 0
+#define BIT_MASK_TA4_H_V1_8822C 0xffff
+#define BIT_TA4_H_V1_8822C(x)                                                  \
+	(((x) & BIT_MASK_TA4_H_V1_8822C) << BIT_SHIFT_TA4_H_V1_8822C)
+#define BITS_TA4_H_V1_8822C                                                    \
+	(BIT_MASK_TA4_H_V1_8822C << BIT_SHIFT_TA4_H_V1_8822C)
+#define BIT_CLEAR_TA4_H_V1_8822C(x) ((x) & (~BITS_TA4_H_V1_8822C))
+#define BIT_GET_TA4_H_V1_8822C(x)                                              \
+	(((x) >> BIT_SHIFT_TA4_H_V1_8822C) & BIT_MASK_TA4_H_V1_8822C)
+#define BIT_SET_TA4_H_V1_8822C(x, v)                                           \
+	(BIT_CLEAR_TA4_H_V1_8822C(x) | BIT_TA4_H_V1_8822C(v))
+
+/* 2 REG_RSVD_8822C */
+
+/* 2 REG_RSVD_8822C */
+
+/* 2 REG_RSVD_8822C */
+
+/* 2 REG_RSVD_8822C */
+
+/* 2 REG_RSVD_8822C */
+
+/* 2 REG_RSVD_8822C */
+
+/* 2 REG_RSVD_8822C */
+
+/* 2 REG_RSVD_8822C */
+
+/* 2 REG_RSVD_8822C */
+
+/* 2 REG_RSVD_8822C */
+
+/* 2 REG_RSVD_8822C */
+
+/* 2 REG_RSVD_8822C */
+
+/* 2 REG_RSVD_8822C */
+
+/* 2 REG_RSVD_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_MACID1_8822C */
+
+#define BIT_SHIFT_MACID1_0_8822C 0
+#define BIT_MASK_MACID1_0_8822C 0xffffffffL
+#define BIT_MACID1_0_8822C(x)                                                  \
+	(((x) & BIT_MASK_MACID1_0_8822C) << BIT_SHIFT_MACID1_0_8822C)
+#define BITS_MACID1_0_8822C                                                    \
+	(BIT_MASK_MACID1_0_8822C << BIT_SHIFT_MACID1_0_8822C)
+#define BIT_CLEAR_MACID1_0_8822C(x) ((x) & (~BITS_MACID1_0_8822C))
+#define BIT_GET_MACID1_0_8822C(x)                                              \
+	(((x) >> BIT_SHIFT_MACID1_0_8822C) & BIT_MASK_MACID1_0_8822C)
+#define BIT_SET_MACID1_0_8822C(x, v)                                           \
+	(BIT_CLEAR_MACID1_0_8822C(x) | BIT_MACID1_0_8822C(v))
+
+/* 2 REG_MACID1_1_8822C */
+
+#define BIT_SHIFT_MACID1_1_8822C 0
+#define BIT_MASK_MACID1_1_8822C 0xffff
+#define BIT_MACID1_1_8822C(x)                                                  \
+	(((x) & BIT_MASK_MACID1_1_8822C) << BIT_SHIFT_MACID1_1_8822C)
+#define BITS_MACID1_1_8822C                                                    \
+	(BIT_MASK_MACID1_1_8822C << BIT_SHIFT_MACID1_1_8822C)
+#define BIT_CLEAR_MACID1_1_8822C(x) ((x) & (~BITS_MACID1_1_8822C))
+#define BIT_GET_MACID1_1_8822C(x)                                              \
+	(((x) >> BIT_SHIFT_MACID1_1_8822C) & BIT_MASK_MACID1_1_8822C)
+#define BIT_SET_MACID1_1_8822C(x, v)                                           \
+	(BIT_CLEAR_MACID1_1_8822C(x) | BIT_MACID1_1_8822C(v))
+
+/* 2 REG_BSSID1_8822C */
+
+#define BIT_SHIFT_BSSID1_0_8822C 0
+#define BIT_MASK_BSSID1_0_8822C 0xffffffffL
+#define BIT_BSSID1_0_8822C(x)                                                  \
+	(((x) & BIT_MASK_BSSID1_0_8822C) << BIT_SHIFT_BSSID1_0_8822C)
+#define BITS_BSSID1_0_8822C                                                    \
+	(BIT_MASK_BSSID1_0_8822C << BIT_SHIFT_BSSID1_0_8822C)
+#define BIT_CLEAR_BSSID1_0_8822C(x) ((x) & (~BITS_BSSID1_0_8822C))
+#define BIT_GET_BSSID1_0_8822C(x)                                              \
+	(((x) >> BIT_SHIFT_BSSID1_0_8822C) & BIT_MASK_BSSID1_0_8822C)
+#define BIT_SET_BSSID1_0_8822C(x, v)                                           \
+	(BIT_CLEAR_BSSID1_0_8822C(x) | BIT_BSSID1_0_8822C(v))
+
+/* 2 REG_BSSID1_1_8822C */
+
+#define BIT_SHIFT_BSSID1_1_8822C 0
+#define BIT_MASK_BSSID1_1_8822C 0xffff
+#define BIT_BSSID1_1_8822C(x)                                                  \
+	(((x) & BIT_MASK_BSSID1_1_8822C) << BIT_SHIFT_BSSID1_1_8822C)
+#define BITS_BSSID1_1_8822C                                                    \
+	(BIT_MASK_BSSID1_1_8822C << BIT_SHIFT_BSSID1_1_8822C)
+#define BIT_CLEAR_BSSID1_1_8822C(x) ((x) & (~BITS_BSSID1_1_8822C))
+#define BIT_GET_BSSID1_1_8822C(x)                                              \
+	(((x) >> BIT_SHIFT_BSSID1_1_8822C) & BIT_MASK_BSSID1_1_8822C)
+#define BIT_SET_BSSID1_1_8822C(x, v)                                           \
+	(BIT_CLEAR_BSSID1_1_8822C(x) | BIT_BSSID1_1_8822C(v))
+
+/* 2 REG_BCN_PSR_RPT1_8822C */
+
+#define BIT_SHIFT_DTIM_CNT1_8822C 24
+#define BIT_MASK_DTIM_CNT1_8822C 0xff
+#define BIT_DTIM_CNT1_8822C(x)                                                 \
+	(((x) & BIT_MASK_DTIM_CNT1_8822C) << BIT_SHIFT_DTIM_CNT1_8822C)
+#define BITS_DTIM_CNT1_8822C                                                   \
+	(BIT_MASK_DTIM_CNT1_8822C << BIT_SHIFT_DTIM_CNT1_8822C)
+#define BIT_CLEAR_DTIM_CNT1_8822C(x) ((x) & (~BITS_DTIM_CNT1_8822C))
+#define BIT_GET_DTIM_CNT1_8822C(x)                                             \
+	(((x) >> BIT_SHIFT_DTIM_CNT1_8822C) & BIT_MASK_DTIM_CNT1_8822C)
+#define BIT_SET_DTIM_CNT1_8822C(x, v)                                          \
+	(BIT_CLEAR_DTIM_CNT1_8822C(x) | BIT_DTIM_CNT1_8822C(v))
+
+#define BIT_SHIFT_DTIM_PERIOD1_8822C 16
+#define BIT_MASK_DTIM_PERIOD1_8822C 0xff
+#define BIT_DTIM_PERIOD1_8822C(x)                                              \
+	(((x) & BIT_MASK_DTIM_PERIOD1_8822C) << BIT_SHIFT_DTIM_PERIOD1_8822C)
+#define BITS_DTIM_PERIOD1_8822C                                                \
+	(BIT_MASK_DTIM_PERIOD1_8822C << BIT_SHIFT_DTIM_PERIOD1_8822C)
+#define BIT_CLEAR_DTIM_PERIOD1_8822C(x) ((x) & (~BITS_DTIM_PERIOD1_8822C))
+#define BIT_GET_DTIM_PERIOD1_8822C(x)                                          \
+	(((x) >> BIT_SHIFT_DTIM_PERIOD1_8822C) & BIT_MASK_DTIM_PERIOD1_8822C)
+#define BIT_SET_DTIM_PERIOD1_8822C(x, v)                                       \
+	(BIT_CLEAR_DTIM_PERIOD1_8822C(x) | BIT_DTIM_PERIOD1_8822C(v))
+
+#define BIT_DTIM1_8822C BIT(15)
+#define BIT_TIM1_8822C BIT(14)
+#define BIT_BCN_VALID_V2_8822C BIT(13)
+
+#define BIT_SHIFT_PS_AID_1_8822C 0
+#define BIT_MASK_PS_AID_1_8822C 0x7ff
+#define BIT_PS_AID_1_8822C(x)                                                  \
+	(((x) & BIT_MASK_PS_AID_1_8822C) << BIT_SHIFT_PS_AID_1_8822C)
+#define BITS_PS_AID_1_8822C                                                    \
+	(BIT_MASK_PS_AID_1_8822C << BIT_SHIFT_PS_AID_1_8822C)
+#define BIT_CLEAR_PS_AID_1_8822C(x) ((x) & (~BITS_PS_AID_1_8822C))
+#define BIT_GET_PS_AID_1_8822C(x)                                              \
+	(((x) >> BIT_SHIFT_PS_AID_1_8822C) & BIT_MASK_PS_AID_1_8822C)
+#define BIT_SET_PS_AID_1_8822C(x, v)                                           \
+	(BIT_CLEAR_PS_AID_1_8822C(x) | BIT_PS_AID_1_8822C(v))
+
+/* 2 REG_ASSOCIATED_BFMEE_SEL_8822C */
+#define BIT_TXUSER_ID1_8822C BIT(25)
+
+#define BIT_SHIFT_AID1_8822C 16
+#define BIT_MASK_AID1_8822C 0x1ff
+#define BIT_AID1_8822C(x) (((x) & BIT_MASK_AID1_8822C) << BIT_SHIFT_AID1_8822C)
+#define BITS_AID1_8822C (BIT_MASK_AID1_8822C << BIT_SHIFT_AID1_8822C)
+#define BIT_CLEAR_AID1_8822C(x) ((x) & (~BITS_AID1_8822C))
+#define BIT_GET_AID1_8822C(x)                                                  \
+	(((x) >> BIT_SHIFT_AID1_8822C) & BIT_MASK_AID1_8822C)
+#define BIT_SET_AID1_8822C(x, v) (BIT_CLEAR_AID1_8822C(x) | BIT_AID1_8822C(v))
+
+#define BIT_TXUSER_ID0_8822C BIT(9)
+
+#define BIT_SHIFT_AID0_8822C 0
+#define BIT_MASK_AID0_8822C 0x1ff
+#define BIT_AID0_8822C(x) (((x) & BIT_MASK_AID0_8822C) << BIT_SHIFT_AID0_8822C)
+#define BITS_AID0_8822C (BIT_MASK_AID0_8822C << BIT_SHIFT_AID0_8822C)
+#define BIT_CLEAR_AID0_8822C(x) ((x) & (~BITS_AID0_8822C))
+#define BIT_GET_AID0_8822C(x)                                                  \
+	(((x) >> BIT_SHIFT_AID0_8822C) & BIT_MASK_AID0_8822C)
+#define BIT_SET_AID0_8822C(x, v) (BIT_CLEAR_AID0_8822C(x) | BIT_AID0_8822C(v))
+
+/* 2 REG_SND_PTCL_CTRL_8822C */
+
+#define BIT_SHIFT_NDP_RX_STANDBY_TIMER_8822C 24
+#define BIT_MASK_NDP_RX_STANDBY_TIMER_8822C 0xff
+#define BIT_NDP_RX_STANDBY_TIMER_8822C(x)                                      \
+	(((x) & BIT_MASK_NDP_RX_STANDBY_TIMER_8822C)                           \
+	 << BIT_SHIFT_NDP_RX_STANDBY_TIMER_8822C)
+#define BITS_NDP_RX_STANDBY_TIMER_8822C                                        \
+	(BIT_MASK_NDP_RX_STANDBY_TIMER_8822C                                   \
+	 << BIT_SHIFT_NDP_RX_STANDBY_TIMER_8822C)
+#define BIT_CLEAR_NDP_RX_STANDBY_TIMER_8822C(x)                                \
+	((x) & (~BITS_NDP_RX_STANDBY_TIMER_8822C))
+#define BIT_GET_NDP_RX_STANDBY_TIMER_8822C(x)                                  \
+	(((x) >> BIT_SHIFT_NDP_RX_STANDBY_TIMER_8822C) &                       \
+	 BIT_MASK_NDP_RX_STANDBY_TIMER_8822C)
+#define BIT_SET_NDP_RX_STANDBY_TIMER_8822C(x, v)                               \
+	(BIT_CLEAR_NDP_RX_STANDBY_TIMER_8822C(x) |                             \
+	 BIT_NDP_RX_STANDBY_TIMER_8822C(v))
+
+#define BIT_R_WMAC_CHK_RPTPOLL_A2_DIS_8822C BIT(23)
+#define BIT_R_WMAC_CHK_UCNDPA_A2_DIS_8822C BIT(22)
+
+#define BIT_SHIFT_CSI_RPT_OFFSET_HT_V1_8822C 16
+#define BIT_MASK_CSI_RPT_OFFSET_HT_V1_8822C 0x3f
+#define BIT_CSI_RPT_OFFSET_HT_V1_8822C(x)                                      \
+	(((x) & BIT_MASK_CSI_RPT_OFFSET_HT_V1_8822C)                           \
+	 << BIT_SHIFT_CSI_RPT_OFFSET_HT_V1_8822C)
+#define BITS_CSI_RPT_OFFSET_HT_V1_8822C                                        \
+	(BIT_MASK_CSI_RPT_OFFSET_HT_V1_8822C                                   \
+	 << BIT_SHIFT_CSI_RPT_OFFSET_HT_V1_8822C)
+#define BIT_CLEAR_CSI_RPT_OFFSET_HT_V1_8822C(x)                                \
+	((x) & (~BITS_CSI_RPT_OFFSET_HT_V1_8822C))
+#define BIT_GET_CSI_RPT_OFFSET_HT_V1_8822C(x)                                  \
+	(((x) >> BIT_SHIFT_CSI_RPT_OFFSET_HT_V1_8822C) &                       \
+	 BIT_MASK_CSI_RPT_OFFSET_HT_V1_8822C)
+#define BIT_SET_CSI_RPT_OFFSET_HT_V1_8822C(x, v)                               \
+	(BIT_CLEAR_CSI_RPT_OFFSET_HT_V1_8822C(x) |                             \
+	 BIT_CSI_RPT_OFFSET_HT_V1_8822C(v))
+
+#define BIT_R_WMAC_OFFSET_RPTPOLL_EN_8822C BIT(15)
+#define BIT_R_WMAC_CSI_CHKSUM_DIS_8822C BIT(14)
+
+#define BIT_SHIFT_R_WMAC_VHT_CATEGORY_V1_8822C 8
+#define BIT_MASK_R_WMAC_VHT_CATEGORY_V1_8822C 0x3f
+#define BIT_R_WMAC_VHT_CATEGORY_V1_8822C(x)                                    \
+	(((x) & BIT_MASK_R_WMAC_VHT_CATEGORY_V1_8822C)                         \
+	 << BIT_SHIFT_R_WMAC_VHT_CATEGORY_V1_8822C)
+#define BITS_R_WMAC_VHT_CATEGORY_V1_8822C                                      \
+	(BIT_MASK_R_WMAC_VHT_CATEGORY_V1_8822C                                 \
+	 << BIT_SHIFT_R_WMAC_VHT_CATEGORY_V1_8822C)
+#define BIT_CLEAR_R_WMAC_VHT_CATEGORY_V1_8822C(x)                              \
+	((x) & (~BITS_R_WMAC_VHT_CATEGORY_V1_8822C))
+#define BIT_GET_R_WMAC_VHT_CATEGORY_V1_8822C(x)                                \
+	(((x) >> BIT_SHIFT_R_WMAC_VHT_CATEGORY_V1_8822C) &                     \
+	 BIT_MASK_R_WMAC_VHT_CATEGORY_V1_8822C)
+#define BIT_SET_R_WMAC_VHT_CATEGORY_V1_8822C(x, v)                             \
+	(BIT_CLEAR_R_WMAC_VHT_CATEGORY_V1_8822C(x) |                           \
+	 BIT_R_WMAC_VHT_CATEGORY_V1_8822C(v))
+
+#define BIT_R_WMAC_USE_NSTS_8822C BIT(7)
+#define BIT_R_DISABLE_CHECK_VHTSIGB_CRC_8822C BIT(6)
+#define BIT_R_DISABLE_CHECK_VHTSIGA_CRC_8822C BIT(5)
+#define BIT_R_WMAC_BFPARAM_SEL_8822C BIT(4)
+#define BIT_R_WMAC_CSISEQ_SEL_8822C BIT(3)
+#define BIT_R_WMAC_CSI_WITHHTC_EN_8822C BIT(2)
+#define BIT_R_WMAC_HT_NDPA_EN_8822C BIT(1)
+#define BIT_R_WMAC_VHT_NDPA_EN_8822C BIT(0)
+
+/* 2 REG_RX_CSI_RPT_INFO_8822C */
+#define BIT_WRITE_ENABLE_8822C BIT(31)
+#define BIT_WMAC_CHECK_SOUNDING_SEQ_8822C BIT(30)
+
+#define BIT_SHIFT_VHTHT_MIMO_CTRL_FIELD_8822C 1
+#define BIT_MASK_VHTHT_MIMO_CTRL_FIELD_8822C 0xffffff
+#define BIT_VHTHT_MIMO_CTRL_FIELD_8822C(x)                                     \
+	(((x) & BIT_MASK_VHTHT_MIMO_CTRL_FIELD_8822C)                          \
+	 << BIT_SHIFT_VHTHT_MIMO_CTRL_FIELD_8822C)
+#define BITS_VHTHT_MIMO_CTRL_FIELD_8822C                                       \
+	(BIT_MASK_VHTHT_MIMO_CTRL_FIELD_8822C                                  \
+	 << BIT_SHIFT_VHTHT_MIMO_CTRL_FIELD_8822C)
+#define BIT_CLEAR_VHTHT_MIMO_CTRL_FIELD_8822C(x)                               \
+	((x) & (~BITS_VHTHT_MIMO_CTRL_FIELD_8822C))
+#define BIT_GET_VHTHT_MIMO_CTRL_FIELD_8822C(x)                                 \
+	(((x) >> BIT_SHIFT_VHTHT_MIMO_CTRL_FIELD_8822C) &                      \
+	 BIT_MASK_VHTHT_MIMO_CTRL_FIELD_8822C)
+#define BIT_SET_VHTHT_MIMO_CTRL_FIELD_8822C(x, v)                              \
+	(BIT_CLEAR_VHTHT_MIMO_CTRL_FIELD_8822C(x) |                            \
+	 BIT_VHTHT_MIMO_CTRL_FIELD_8822C(v))
+
+#define BIT_CSI_INTERRUPT_STATUS_8822C BIT(0)
+
+/* 2 REG_NS_ARP_CTRL_8822C */
+#define BIT_R_WMAC_NSARP_RSPEN_8822C BIT(15)
+#define BIT_R_WMAC_NSARP_RARP_8822C BIT(9)
+#define BIT_R_WMAC_NSARP_RIPV6_8822C BIT(8)
+
+#define BIT_SHIFT_R_WMAC_NSARP_MODEN_8822C 6
+#define BIT_MASK_R_WMAC_NSARP_MODEN_8822C 0x3
+#define BIT_R_WMAC_NSARP_MODEN_8822C(x)                                        \
+	(((x) & BIT_MASK_R_WMAC_NSARP_MODEN_8822C)                             \
+	 << BIT_SHIFT_R_WMAC_NSARP_MODEN_8822C)
+#define BITS_R_WMAC_NSARP_MODEN_8822C                                          \
+	(BIT_MASK_R_WMAC_NSARP_MODEN_8822C                                     \
+	 << BIT_SHIFT_R_WMAC_NSARP_MODEN_8822C)
+#define BIT_CLEAR_R_WMAC_NSARP_MODEN_8822C(x)                                  \
+	((x) & (~BITS_R_WMAC_NSARP_MODEN_8822C))
+#define BIT_GET_R_WMAC_NSARP_MODEN_8822C(x)                                    \
+	(((x) >> BIT_SHIFT_R_WMAC_NSARP_MODEN_8822C) &                         \
+	 BIT_MASK_R_WMAC_NSARP_MODEN_8822C)
+#define BIT_SET_R_WMAC_NSARP_MODEN_8822C(x, v)                                 \
+	(BIT_CLEAR_R_WMAC_NSARP_MODEN_8822C(x) |                               \
+	 BIT_R_WMAC_NSARP_MODEN_8822C(v))
+
+#define BIT_SHIFT_R_WMAC_NSARP_RSPFTP_8822C 4
+#define BIT_MASK_R_WMAC_NSARP_RSPFTP_8822C 0x3
+#define BIT_R_WMAC_NSARP_RSPFTP_8822C(x)                                       \
+	(((x) & BIT_MASK_R_WMAC_NSARP_RSPFTP_8822C)                            \
+	 << BIT_SHIFT_R_WMAC_NSARP_RSPFTP_8822C)
+#define BITS_R_WMAC_NSARP_RSPFTP_8822C                                         \
+	(BIT_MASK_R_WMAC_NSARP_RSPFTP_8822C                                    \
+	 << BIT_SHIFT_R_WMAC_NSARP_RSPFTP_8822C)
+#define BIT_CLEAR_R_WMAC_NSARP_RSPFTP_8822C(x)                                 \
+	((x) & (~BITS_R_WMAC_NSARP_RSPFTP_8822C))
+#define BIT_GET_R_WMAC_NSARP_RSPFTP_8822C(x)                                   \
+	(((x) >> BIT_SHIFT_R_WMAC_NSARP_RSPFTP_8822C) &                        \
+	 BIT_MASK_R_WMAC_NSARP_RSPFTP_8822C)
+#define BIT_SET_R_WMAC_NSARP_RSPFTP_8822C(x, v)                                \
+	(BIT_CLEAR_R_WMAC_NSARP_RSPFTP_8822C(x) |                              \
+	 BIT_R_WMAC_NSARP_RSPFTP_8822C(v))
+
+#define BIT_SHIFT_R_WMAC_NSARP_RSPSEC_8822C 0
+#define BIT_MASK_R_WMAC_NSARP_RSPSEC_8822C 0xf
+#define BIT_R_WMAC_NSARP_RSPSEC_8822C(x)                                       \
+	(((x) & BIT_MASK_R_WMAC_NSARP_RSPSEC_8822C)                            \
+	 << BIT_SHIFT_R_WMAC_NSARP_RSPSEC_8822C)
+#define BITS_R_WMAC_NSARP_RSPSEC_8822C                                         \
+	(BIT_MASK_R_WMAC_NSARP_RSPSEC_8822C                                    \
+	 << BIT_SHIFT_R_WMAC_NSARP_RSPSEC_8822C)
+#define BIT_CLEAR_R_WMAC_NSARP_RSPSEC_8822C(x)                                 \
+	((x) & (~BITS_R_WMAC_NSARP_RSPSEC_8822C))
+#define BIT_GET_R_WMAC_NSARP_RSPSEC_8822C(x)                                   \
+	(((x) >> BIT_SHIFT_R_WMAC_NSARP_RSPSEC_8822C) &                        \
+	 BIT_MASK_R_WMAC_NSARP_RSPSEC_8822C)
+#define BIT_SET_R_WMAC_NSARP_RSPSEC_8822C(x, v)                                \
+	(BIT_CLEAR_R_WMAC_NSARP_RSPSEC_8822C(x) |                              \
+	 BIT_R_WMAC_NSARP_RSPSEC_8822C(v))
+
+/* 2 REG_NS_ARP_INFO_8822C */
+#define BIT_REQ_IS_MCNS_8822C BIT(23)
+#define BIT_REQ_IS_UCNS_8822C BIT(22)
+#define BIT_REQ_IS_USNS_8822C BIT(21)
+#define BIT_REQ_IS_ARP_8822C BIT(20)
+#define BIT_EXPRSP_MH_WITHQC_8822C BIT(19)
+
+#define BIT_SHIFT_EXPRSP_SECTYPE_8822C 16
+#define BIT_MASK_EXPRSP_SECTYPE_8822C 0x7
+#define BIT_EXPRSP_SECTYPE_8822C(x)                                            \
+	(((x) & BIT_MASK_EXPRSP_SECTYPE_8822C)                                 \
+	 << BIT_SHIFT_EXPRSP_SECTYPE_8822C)
+#define BITS_EXPRSP_SECTYPE_8822C                                              \
+	(BIT_MASK_EXPRSP_SECTYPE_8822C << BIT_SHIFT_EXPRSP_SECTYPE_8822C)
+#define BIT_CLEAR_EXPRSP_SECTYPE_8822C(x) ((x) & (~BITS_EXPRSP_SECTYPE_8822C))
+#define BIT_GET_EXPRSP_SECTYPE_8822C(x)                                        \
+	(((x) >> BIT_SHIFT_EXPRSP_SECTYPE_8822C) &                             \
+	 BIT_MASK_EXPRSP_SECTYPE_8822C)
+#define BIT_SET_EXPRSP_SECTYPE_8822C(x, v)                                     \
+	(BIT_CLEAR_EXPRSP_SECTYPE_8822C(x) | BIT_EXPRSP_SECTYPE_8822C(v))
+
+#define BIT_SHIFT_EXPRSP_CHKSM_7_TO_0_8822C 8
+#define BIT_MASK_EXPRSP_CHKSM_7_TO_0_8822C 0xff
+#define BIT_EXPRSP_CHKSM_7_TO_0_8822C(x)                                       \
+	(((x) & BIT_MASK_EXPRSP_CHKSM_7_TO_0_8822C)                            \
+	 << BIT_SHIFT_EXPRSP_CHKSM_7_TO_0_8822C)
+#define BITS_EXPRSP_CHKSM_7_TO_0_8822C                                         \
+	(BIT_MASK_EXPRSP_CHKSM_7_TO_0_8822C                                    \
+	 << BIT_SHIFT_EXPRSP_CHKSM_7_TO_0_8822C)
+#define BIT_CLEAR_EXPRSP_CHKSM_7_TO_0_8822C(x)                                 \
+	((x) & (~BITS_EXPRSP_CHKSM_7_TO_0_8822C))
+#define BIT_GET_EXPRSP_CHKSM_7_TO_0_8822C(x)                                   \
+	(((x) >> BIT_SHIFT_EXPRSP_CHKSM_7_TO_0_8822C) &                        \
+	 BIT_MASK_EXPRSP_CHKSM_7_TO_0_8822C)
+#define BIT_SET_EXPRSP_CHKSM_7_TO_0_8822C(x, v)                                \
+	(BIT_CLEAR_EXPRSP_CHKSM_7_TO_0_8822C(x) |                              \
+	 BIT_EXPRSP_CHKSM_7_TO_0_8822C(v))
+
+#define BIT_SHIFT_EXPRSP_CHKSM_15_TO_8_8822C 0
+#define BIT_MASK_EXPRSP_CHKSM_15_TO_8_8822C 0xff
+#define BIT_EXPRSP_CHKSM_15_TO_8_8822C(x)                                      \
+	(((x) & BIT_MASK_EXPRSP_CHKSM_15_TO_8_8822C)                           \
+	 << BIT_SHIFT_EXPRSP_CHKSM_15_TO_8_8822C)
+#define BITS_EXPRSP_CHKSM_15_TO_8_8822C                                        \
+	(BIT_MASK_EXPRSP_CHKSM_15_TO_8_8822C                                   \
+	 << BIT_SHIFT_EXPRSP_CHKSM_15_TO_8_8822C)
+#define BIT_CLEAR_EXPRSP_CHKSM_15_TO_8_8822C(x)                                \
+	((x) & (~BITS_EXPRSP_CHKSM_15_TO_8_8822C))
+#define BIT_GET_EXPRSP_CHKSM_15_TO_8_8822C(x)                                  \
+	(((x) >> BIT_SHIFT_EXPRSP_CHKSM_15_TO_8_8822C) &                       \
+	 BIT_MASK_EXPRSP_CHKSM_15_TO_8_8822C)
+#define BIT_SET_EXPRSP_CHKSM_15_TO_8_8822C(x, v)                               \
+	(BIT_CLEAR_EXPRSP_CHKSM_15_TO_8_8822C(x) |                             \
+	 BIT_EXPRSP_CHKSM_15_TO_8_8822C(v))
+
+/* 2 REG_BEAMFORMING_INFO_NSARP_V1_8822C */
+
+#define BIT_SHIFT_WMAC_ARPIP_8822C 0
+#define BIT_MASK_WMAC_ARPIP_8822C 0xffffffffL
+#define BIT_WMAC_ARPIP_8822C(x)                                                \
+	(((x) & BIT_MASK_WMAC_ARPIP_8822C) << BIT_SHIFT_WMAC_ARPIP_8822C)
+#define BITS_WMAC_ARPIP_8822C                                                  \
+	(BIT_MASK_WMAC_ARPIP_8822C << BIT_SHIFT_WMAC_ARPIP_8822C)
+#define BIT_CLEAR_WMAC_ARPIP_8822C(x) ((x) & (~BITS_WMAC_ARPIP_8822C))
+#define BIT_GET_WMAC_ARPIP_8822C(x)                                            \
+	(((x) >> BIT_SHIFT_WMAC_ARPIP_8822C) & BIT_MASK_WMAC_ARPIP_8822C)
+#define BIT_SET_WMAC_ARPIP_8822C(x, v)                                         \
+	(BIT_CLEAR_WMAC_ARPIP_8822C(x) | BIT_WMAC_ARPIP_8822C(v))
+
+/* 2 REG_BEAMFORMING_INFO_NSARP_8822C */
+
+#define BIT_SHIFT_UPD_BFMEE_USERID_8822C 13
+#define BIT_MASK_UPD_BFMEE_USERID_8822C 0x7
+#define BIT_UPD_BFMEE_USERID_8822C(x)                                          \
+	(((x) & BIT_MASK_UPD_BFMEE_USERID_8822C)                               \
+	 << BIT_SHIFT_UPD_BFMEE_USERID_8822C)
+#define BITS_UPD_BFMEE_USERID_8822C                                            \
+	(BIT_MASK_UPD_BFMEE_USERID_8822C << BIT_SHIFT_UPD_BFMEE_USERID_8822C)
+#define BIT_CLEAR_UPD_BFMEE_USERID_8822C(x)                                    \
+	((x) & (~BITS_UPD_BFMEE_USERID_8822C))
+#define BIT_GET_UPD_BFMEE_USERID_8822C(x)                                      \
+	(((x) >> BIT_SHIFT_UPD_BFMEE_USERID_8822C) &                           \
+	 BIT_MASK_UPD_BFMEE_USERID_8822C)
+#define BIT_SET_UPD_BFMEE_USERID_8822C(x, v)                                   \
+	(BIT_CLEAR_UPD_BFMEE_USERID_8822C(x) | BIT_UPD_BFMEE_USERID_8822C(v))
+
+#define BIT_UPD_BFMEE_FBTP_8822C BIT(12)
+
+#define BIT_SHIFT_UPD_BFMEE_BW_8822C 0
+#define BIT_MASK_UPD_BFMEE_BW_8822C 0xfff
+#define BIT_UPD_BFMEE_BW_8822C(x)                                              \
+	(((x) & BIT_MASK_UPD_BFMEE_BW_8822C) << BIT_SHIFT_UPD_BFMEE_BW_8822C)
+#define BITS_UPD_BFMEE_BW_8822C                                                \
+	(BIT_MASK_UPD_BFMEE_BW_8822C << BIT_SHIFT_UPD_BFMEE_BW_8822C)
+#define BIT_CLEAR_UPD_BFMEE_BW_8822C(x) ((x) & (~BITS_UPD_BFMEE_BW_8822C))
+#define BIT_GET_UPD_BFMEE_BW_8822C(x)                                          \
+	(((x) >> BIT_SHIFT_UPD_BFMEE_BW_8822C) & BIT_MASK_UPD_BFMEE_BW_8822C)
+#define BIT_SET_UPD_BFMEE_BW_8822C(x, v)                                       \
+	(BIT_CLEAR_UPD_BFMEE_BW_8822C(x) | BIT_UPD_BFMEE_BW_8822C(v))
+
+#define BIT_SHIFT_UPD_BFMEE_CB_8822C 8
+#define BIT_MASK_UPD_BFMEE_CB_8822C 0x3
+#define BIT_UPD_BFMEE_CB_8822C(x)                                              \
+	(((x) & BIT_MASK_UPD_BFMEE_CB_8822C) << BIT_SHIFT_UPD_BFMEE_CB_8822C)
+#define BITS_UPD_BFMEE_CB_8822C                                                \
+	(BIT_MASK_UPD_BFMEE_CB_8822C << BIT_SHIFT_UPD_BFMEE_CB_8822C)
+#define BIT_CLEAR_UPD_BFMEE_CB_8822C(x) ((x) & (~BITS_UPD_BFMEE_CB_8822C))
+#define BIT_GET_UPD_BFMEE_CB_8822C(x)                                          \
+	(((x) >> BIT_SHIFT_UPD_BFMEE_CB_8822C) & BIT_MASK_UPD_BFMEE_CB_8822C)
+#define BIT_SET_UPD_BFMEE_CB_8822C(x, v)                                       \
+	(BIT_CLEAR_UPD_BFMEE_CB_8822C(x) | BIT_UPD_BFMEE_CB_8822C(v))
+
+#define BIT_SHIFT_UPD_BFMEE_NG_8822C 6
+#define BIT_MASK_UPD_BFMEE_NG_8822C 0x3
+#define BIT_UPD_BFMEE_NG_8822C(x)                                              \
+	(((x) & BIT_MASK_UPD_BFMEE_NG_8822C) << BIT_SHIFT_UPD_BFMEE_NG_8822C)
+#define BITS_UPD_BFMEE_NG_8822C                                                \
+	(BIT_MASK_UPD_BFMEE_NG_8822C << BIT_SHIFT_UPD_BFMEE_NG_8822C)
+#define BIT_CLEAR_UPD_BFMEE_NG_8822C(x) ((x) & (~BITS_UPD_BFMEE_NG_8822C))
+#define BIT_GET_UPD_BFMEE_NG_8822C(x)                                          \
+	(((x) >> BIT_SHIFT_UPD_BFMEE_NG_8822C) & BIT_MASK_UPD_BFMEE_NG_8822C)
+#define BIT_SET_UPD_BFMEE_NG_8822C(x, v)                                       \
+	(BIT_CLEAR_UPD_BFMEE_NG_8822C(x) | BIT_UPD_BFMEE_NG_8822C(v))
+
+#define BIT_SHIFT_UPD_BFMEE_NR_8822C 3
+#define BIT_MASK_UPD_BFMEE_NR_8822C 0x7
+#define BIT_UPD_BFMEE_NR_8822C(x)                                              \
+	(((x) & BIT_MASK_UPD_BFMEE_NR_8822C) << BIT_SHIFT_UPD_BFMEE_NR_8822C)
+#define BITS_UPD_BFMEE_NR_8822C                                                \
+	(BIT_MASK_UPD_BFMEE_NR_8822C << BIT_SHIFT_UPD_BFMEE_NR_8822C)
+#define BIT_CLEAR_UPD_BFMEE_NR_8822C(x) ((x) & (~BITS_UPD_BFMEE_NR_8822C))
+#define BIT_GET_UPD_BFMEE_NR_8822C(x)                                          \
+	(((x) >> BIT_SHIFT_UPD_BFMEE_NR_8822C) & BIT_MASK_UPD_BFMEE_NR_8822C)
+#define BIT_SET_UPD_BFMEE_NR_8822C(x, v)                                       \
+	(BIT_CLEAR_UPD_BFMEE_NR_8822C(x) | BIT_UPD_BFMEE_NR_8822C(v))
+
+#define BIT_SHIFT_UPD_BFMEE_NC_8822C 0
+#define BIT_MASK_UPD_BFMEE_NC_8822C 0x7
+#define BIT_UPD_BFMEE_NC_8822C(x)                                              \
+	(((x) & BIT_MASK_UPD_BFMEE_NC_8822C) << BIT_SHIFT_UPD_BFMEE_NC_8822C)
+#define BITS_UPD_BFMEE_NC_8822C                                                \
+	(BIT_MASK_UPD_BFMEE_NC_8822C << BIT_SHIFT_UPD_BFMEE_NC_8822C)
+#define BIT_CLEAR_UPD_BFMEE_NC_8822C(x) ((x) & (~BITS_UPD_BFMEE_NC_8822C))
+#define BIT_GET_UPD_BFMEE_NC_8822C(x)                                          \
+	(((x) >> BIT_SHIFT_UPD_BFMEE_NC_8822C) & BIT_MASK_UPD_BFMEE_NC_8822C)
+#define BIT_SET_UPD_BFMEE_NC_8822C(x, v)                                       \
+	(BIT_CLEAR_UPD_BFMEE_NC_8822C(x) | BIT_UPD_BFMEE_NC_8822C(v))
+
+/* 2 REG_IPV6_8822C */
+
+#define BIT_SHIFT_R_WMAC_IPV6_MYIPAD_0_8822C 0
+#define BIT_MASK_R_WMAC_IPV6_MYIPAD_0_8822C 0xffffffffL
+#define BIT_R_WMAC_IPV6_MYIPAD_0_8822C(x)                                      \
+	(((x) & BIT_MASK_R_WMAC_IPV6_MYIPAD_0_8822C)                           \
+	 << BIT_SHIFT_R_WMAC_IPV6_MYIPAD_0_8822C)
+#define BITS_R_WMAC_IPV6_MYIPAD_0_8822C                                        \
+	(BIT_MASK_R_WMAC_IPV6_MYIPAD_0_8822C                                   \
+	 << BIT_SHIFT_R_WMAC_IPV6_MYIPAD_0_8822C)
+#define BIT_CLEAR_R_WMAC_IPV6_MYIPAD_0_8822C(x)                                \
+	((x) & (~BITS_R_WMAC_IPV6_MYIPAD_0_8822C))
+#define BIT_GET_R_WMAC_IPV6_MYIPAD_0_8822C(x)                                  \
+	(((x) >> BIT_SHIFT_R_WMAC_IPV6_MYIPAD_0_8822C) &                       \
+	 BIT_MASK_R_WMAC_IPV6_MYIPAD_0_8822C)
+#define BIT_SET_R_WMAC_IPV6_MYIPAD_0_8822C(x, v)                               \
+	(BIT_CLEAR_R_WMAC_IPV6_MYIPAD_0_8822C(x) |                             \
+	 BIT_R_WMAC_IPV6_MYIPAD_0_8822C(v))
+
+/* 2 REG_IPV6_1_8822C */
+
+#define BIT_SHIFT_R_WMAC_IPV6_MYIPAD_1_8822C 0
+#define BIT_MASK_R_WMAC_IPV6_MYIPAD_1_8822C 0xffffffffL
+#define BIT_R_WMAC_IPV6_MYIPAD_1_8822C(x)                                      \
+	(((x) & BIT_MASK_R_WMAC_IPV6_MYIPAD_1_8822C)                           \
+	 << BIT_SHIFT_R_WMAC_IPV6_MYIPAD_1_8822C)
+#define BITS_R_WMAC_IPV6_MYIPAD_1_8822C                                        \
+	(BIT_MASK_R_WMAC_IPV6_MYIPAD_1_8822C                                   \
+	 << BIT_SHIFT_R_WMAC_IPV6_MYIPAD_1_8822C)
+#define BIT_CLEAR_R_WMAC_IPV6_MYIPAD_1_8822C(x)                                \
+	((x) & (~BITS_R_WMAC_IPV6_MYIPAD_1_8822C))
+#define BIT_GET_R_WMAC_IPV6_MYIPAD_1_8822C(x)                                  \
+	(((x) >> BIT_SHIFT_R_WMAC_IPV6_MYIPAD_1_8822C) &                       \
+	 BIT_MASK_R_WMAC_IPV6_MYIPAD_1_8822C)
+#define BIT_SET_R_WMAC_IPV6_MYIPAD_1_8822C(x, v)                               \
+	(BIT_CLEAR_R_WMAC_IPV6_MYIPAD_1_8822C(x) |                             \
+	 BIT_R_WMAC_IPV6_MYIPAD_1_8822C(v))
+
+/* 2 REG_IPV6_2_8822C */
+
+#define BIT_SHIFT_R_WMAC_IPV6_MYIPAD_2_8822C 0
+#define BIT_MASK_R_WMAC_IPV6_MYIPAD_2_8822C 0xffffffffL
+#define BIT_R_WMAC_IPV6_MYIPAD_2_8822C(x)                                      \
+	(((x) & BIT_MASK_R_WMAC_IPV6_MYIPAD_2_8822C)                           \
+	 << BIT_SHIFT_R_WMAC_IPV6_MYIPAD_2_8822C)
+#define BITS_R_WMAC_IPV6_MYIPAD_2_8822C                                        \
+	(BIT_MASK_R_WMAC_IPV6_MYIPAD_2_8822C                                   \
+	 << BIT_SHIFT_R_WMAC_IPV6_MYIPAD_2_8822C)
+#define BIT_CLEAR_R_WMAC_IPV6_MYIPAD_2_8822C(x)                                \
+	((x) & (~BITS_R_WMAC_IPV6_MYIPAD_2_8822C))
+#define BIT_GET_R_WMAC_IPV6_MYIPAD_2_8822C(x)                                  \
+	(((x) >> BIT_SHIFT_R_WMAC_IPV6_MYIPAD_2_8822C) &                       \
+	 BIT_MASK_R_WMAC_IPV6_MYIPAD_2_8822C)
+#define BIT_SET_R_WMAC_IPV6_MYIPAD_2_8822C(x, v)                               \
+	(BIT_CLEAR_R_WMAC_IPV6_MYIPAD_2_8822C(x) |                             \
+	 BIT_R_WMAC_IPV6_MYIPAD_2_8822C(v))
+
+/* 2 REG_IPV6_3_8822C */
+
+#define BIT_SHIFT_R_WMAC_IPV6_MYIPAD_3_8822C 0
+#define BIT_MASK_R_WMAC_IPV6_MYIPAD_3_8822C 0xffffffffL
+#define BIT_R_WMAC_IPV6_MYIPAD_3_8822C(x)                                      \
+	(((x) & BIT_MASK_R_WMAC_IPV6_MYIPAD_3_8822C)                           \
+	 << BIT_SHIFT_R_WMAC_IPV6_MYIPAD_3_8822C)
+#define BITS_R_WMAC_IPV6_MYIPAD_3_8822C                                        \
+	(BIT_MASK_R_WMAC_IPV6_MYIPAD_3_8822C                                   \
+	 << BIT_SHIFT_R_WMAC_IPV6_MYIPAD_3_8822C)
+#define BIT_CLEAR_R_WMAC_IPV6_MYIPAD_3_8822C(x)                                \
+	((x) & (~BITS_R_WMAC_IPV6_MYIPAD_3_8822C))
+#define BIT_GET_R_WMAC_IPV6_MYIPAD_3_8822C(x)                                  \
+	(((x) >> BIT_SHIFT_R_WMAC_IPV6_MYIPAD_3_8822C) &                       \
+	 BIT_MASK_R_WMAC_IPV6_MYIPAD_3_8822C)
+#define BIT_SET_R_WMAC_IPV6_MYIPAD_3_8822C(x, v)                               \
+	(BIT_CLEAR_R_WMAC_IPV6_MYIPAD_3_8822C(x) |                             \
+	 BIT_R_WMAC_IPV6_MYIPAD_3_8822C(v))
+
+/* 2 REG_WMAC_RTX_CTX_SUBTYPE_CFG_8822C */
+
+#define BIT_SHIFT_R_WMAC_CTX_SUBTYPE_8822C 4
+#define BIT_MASK_R_WMAC_CTX_SUBTYPE_8822C 0xf
+#define BIT_R_WMAC_CTX_SUBTYPE_8822C(x)                                        \
+	(((x) & BIT_MASK_R_WMAC_CTX_SUBTYPE_8822C)                             \
+	 << BIT_SHIFT_R_WMAC_CTX_SUBTYPE_8822C)
+#define BITS_R_WMAC_CTX_SUBTYPE_8822C                                          \
+	(BIT_MASK_R_WMAC_CTX_SUBTYPE_8822C                                     \
+	 << BIT_SHIFT_R_WMAC_CTX_SUBTYPE_8822C)
+#define BIT_CLEAR_R_WMAC_CTX_SUBTYPE_8822C(x)                                  \
+	((x) & (~BITS_R_WMAC_CTX_SUBTYPE_8822C))
+#define BIT_GET_R_WMAC_CTX_SUBTYPE_8822C(x)                                    \
+	(((x) >> BIT_SHIFT_R_WMAC_CTX_SUBTYPE_8822C) &                         \
+	 BIT_MASK_R_WMAC_CTX_SUBTYPE_8822C)
+#define BIT_SET_R_WMAC_CTX_SUBTYPE_8822C(x, v)                                 \
+	(BIT_CLEAR_R_WMAC_CTX_SUBTYPE_8822C(x) |                               \
+	 BIT_R_WMAC_CTX_SUBTYPE_8822C(v))
+
+#define BIT_SHIFT_R_WMAC_RTX_SUBTYPE_8822C 0
+#define BIT_MASK_R_WMAC_RTX_SUBTYPE_8822C 0xf
+#define BIT_R_WMAC_RTX_SUBTYPE_8822C(x)                                        \
+	(((x) & BIT_MASK_R_WMAC_RTX_SUBTYPE_8822C)                             \
+	 << BIT_SHIFT_R_WMAC_RTX_SUBTYPE_8822C)
+#define BITS_R_WMAC_RTX_SUBTYPE_8822C                                          \
+	(BIT_MASK_R_WMAC_RTX_SUBTYPE_8822C                                     \
+	 << BIT_SHIFT_R_WMAC_RTX_SUBTYPE_8822C)
+#define BIT_CLEAR_R_WMAC_RTX_SUBTYPE_8822C(x)                                  \
+	((x) & (~BITS_R_WMAC_RTX_SUBTYPE_8822C))
+#define BIT_GET_R_WMAC_RTX_SUBTYPE_8822C(x)                                    \
+	(((x) >> BIT_SHIFT_R_WMAC_RTX_SUBTYPE_8822C) &                         \
+	 BIT_MASK_R_WMAC_RTX_SUBTYPE_8822C)
+#define BIT_SET_R_WMAC_RTX_SUBTYPE_8822C(x, v)                                 \
+	(BIT_CLEAR_R_WMAC_RTX_SUBTYPE_8822C(x) |                               \
+	 BIT_R_WMAC_RTX_SUBTYPE_8822C(v))
+
+/* 2 REG_WMAC_SWAES_DIO_B63_B32_8822C */
+
+#define BIT_SHIFT_WMAC_SWAES_DIO_B63_B32_8822C 0
+#define BIT_MASK_WMAC_SWAES_DIO_B63_B32_8822C 0xffffffffL
+#define BIT_WMAC_SWAES_DIO_B63_B32_8822C(x)                                    \
+	(((x) & BIT_MASK_WMAC_SWAES_DIO_B63_B32_8822C)                         \
+	 << BIT_SHIFT_WMAC_SWAES_DIO_B63_B32_8822C)
+#define BITS_WMAC_SWAES_DIO_B63_B32_8822C                                      \
+	(BIT_MASK_WMAC_SWAES_DIO_B63_B32_8822C                                 \
+	 << BIT_SHIFT_WMAC_SWAES_DIO_B63_B32_8822C)
+#define BIT_CLEAR_WMAC_SWAES_DIO_B63_B32_8822C(x)                              \
+	((x) & (~BITS_WMAC_SWAES_DIO_B63_B32_8822C))
+#define BIT_GET_WMAC_SWAES_DIO_B63_B32_8822C(x)                                \
+	(((x) >> BIT_SHIFT_WMAC_SWAES_DIO_B63_B32_8822C) &                     \
+	 BIT_MASK_WMAC_SWAES_DIO_B63_B32_8822C)
+#define BIT_SET_WMAC_SWAES_DIO_B63_B32_8822C(x, v)                             \
+	(BIT_CLEAR_WMAC_SWAES_DIO_B63_B32_8822C(x) |                           \
+	 BIT_WMAC_SWAES_DIO_B63_B32_8822C(v))
+
+/* 2 REG_WMAC_SWAES_DIO_B95_B64_8822C */
+
+#define BIT_SHIFT_WMAC_SWAES_DIO_B95_B64_8822C 0
+#define BIT_MASK_WMAC_SWAES_DIO_B95_B64_8822C 0xffffffffL
+#define BIT_WMAC_SWAES_DIO_B95_B64_8822C(x)                                    \
+	(((x) & BIT_MASK_WMAC_SWAES_DIO_B95_B64_8822C)                         \
+	 << BIT_SHIFT_WMAC_SWAES_DIO_B95_B64_8822C)
+#define BITS_WMAC_SWAES_DIO_B95_B64_8822C                                      \
+	(BIT_MASK_WMAC_SWAES_DIO_B95_B64_8822C                                 \
+	 << BIT_SHIFT_WMAC_SWAES_DIO_B95_B64_8822C)
+#define BIT_CLEAR_WMAC_SWAES_DIO_B95_B64_8822C(x)                              \
+	((x) & (~BITS_WMAC_SWAES_DIO_B95_B64_8822C))
+#define BIT_GET_WMAC_SWAES_DIO_B95_B64_8822C(x)                                \
+	(((x) >> BIT_SHIFT_WMAC_SWAES_DIO_B95_B64_8822C) &                     \
+	 BIT_MASK_WMAC_SWAES_DIO_B95_B64_8822C)
+#define BIT_SET_WMAC_SWAES_DIO_B95_B64_8822C(x, v)                             \
+	(BIT_CLEAR_WMAC_SWAES_DIO_B95_B64_8822C(x) |                           \
+	 BIT_WMAC_SWAES_DIO_B95_B64_8822C(v))
+
+/* 2 REG_WMAC_SWAES_DIO_B127_B96_8822C */
+
+#define BIT_SHIFT_WMAC_SWAES_DIO_B127_B96_8822C 0
+#define BIT_MASK_WMAC_SWAES_DIO_B127_B96_8822C 0xffffffffL
+#define BIT_WMAC_SWAES_DIO_B127_B96_8822C(x)                                   \
+	(((x) & BIT_MASK_WMAC_SWAES_DIO_B127_B96_8822C)                        \
+	 << BIT_SHIFT_WMAC_SWAES_DIO_B127_B96_8822C)
+#define BITS_WMAC_SWAES_DIO_B127_B96_8822C                                     \
+	(BIT_MASK_WMAC_SWAES_DIO_B127_B96_8822C                                \
+	 << BIT_SHIFT_WMAC_SWAES_DIO_B127_B96_8822C)
+#define BIT_CLEAR_WMAC_SWAES_DIO_B127_B96_8822C(x)                             \
+	((x) & (~BITS_WMAC_SWAES_DIO_B127_B96_8822C))
+#define BIT_GET_WMAC_SWAES_DIO_B127_B96_8822C(x)                               \
+	(((x) >> BIT_SHIFT_WMAC_SWAES_DIO_B127_B96_8822C) &                    \
+	 BIT_MASK_WMAC_SWAES_DIO_B127_B96_8822C)
+#define BIT_SET_WMAC_SWAES_DIO_B127_B96_8822C(x, v)                            \
+	(BIT_CLEAR_WMAC_SWAES_DIO_B127_B96_8822C(x) |                          \
+	 BIT_WMAC_SWAES_DIO_B127_B96_8822C(v))
+
+/* 2 REG_WMAC_SWAES_CFG_8822C */
+
+/* 2 REG_BT_COEX_V2_8822C */
+#define BIT_GNT_BT_POLARITY_8822C BIT(12)
+#define BIT_GNT_BT_BYPASS_PRIORITY_8822C BIT(8)
+
+#define BIT_SHIFT_TIMER_8822C 0
+#define BIT_MASK_TIMER_8822C 0xff
+#define BIT_TIMER_8822C(x)                                                     \
+	(((x) & BIT_MASK_TIMER_8822C) << BIT_SHIFT_TIMER_8822C)
+#define BITS_TIMER_8822C (BIT_MASK_TIMER_8822C << BIT_SHIFT_TIMER_8822C)
+#define BIT_CLEAR_TIMER_8822C(x) ((x) & (~BITS_TIMER_8822C))
+#define BIT_GET_TIMER_8822C(x)                                                 \
+	(((x) >> BIT_SHIFT_TIMER_8822C) & BIT_MASK_TIMER_8822C)
+#define BIT_SET_TIMER_8822C(x, v)                                              \
+	(BIT_CLEAR_TIMER_8822C(x) | BIT_TIMER_8822C(v))
+
+/* 2 REG_BT_COEX_8822C */
+#define BIT_R_GNT_BT_RFC_SW_8822C BIT(12)
+#define BIT_R_GNT_BT_RFC_SW_EN_8822C BIT(11)
+#define BIT_R_GNT_BT_BB_SW_8822C BIT(10)
+#define BIT_R_GNT_BT_BB_SW_EN_8822C BIT(9)
+#define BIT_R_BT_CNT_THREN_8822C BIT(8)
+
+#define BIT_SHIFT_R_BT_CNT_THR_8822C 0
+#define BIT_MASK_R_BT_CNT_THR_8822C 0xff
+#define BIT_R_BT_CNT_THR_8822C(x)                                              \
+	(((x) & BIT_MASK_R_BT_CNT_THR_8822C) << BIT_SHIFT_R_BT_CNT_THR_8822C)
+#define BITS_R_BT_CNT_THR_8822C                                                \
+	(BIT_MASK_R_BT_CNT_THR_8822C << BIT_SHIFT_R_BT_CNT_THR_8822C)
+#define BIT_CLEAR_R_BT_CNT_THR_8822C(x) ((x) & (~BITS_R_BT_CNT_THR_8822C))
+#define BIT_GET_R_BT_CNT_THR_8822C(x)                                          \
+	(((x) >> BIT_SHIFT_R_BT_CNT_THR_8822C) & BIT_MASK_R_BT_CNT_THR_8822C)
+#define BIT_SET_R_BT_CNT_THR_8822C(x, v)                                       \
+	(BIT_CLEAR_R_BT_CNT_THR_8822C(x) | BIT_R_BT_CNT_THR_8822C(v))
+
+/* 2 REG_WLAN_ACT_MASK_CTRL_8822C */
+
+#define BIT_SHIFT_RXMYRTS_NAV_V1_8822C 8
+#define BIT_MASK_RXMYRTS_NAV_V1_8822C 0xff
+#define BIT_RXMYRTS_NAV_V1_8822C(x)                                            \
+	(((x) & BIT_MASK_RXMYRTS_NAV_V1_8822C)                                 \
+	 << BIT_SHIFT_RXMYRTS_NAV_V1_8822C)
+#define BITS_RXMYRTS_NAV_V1_8822C                                              \
+	(BIT_MASK_RXMYRTS_NAV_V1_8822C << BIT_SHIFT_RXMYRTS_NAV_V1_8822C)
+#define BIT_CLEAR_RXMYRTS_NAV_V1_8822C(x) ((x) & (~BITS_RXMYRTS_NAV_V1_8822C))
+#define BIT_GET_RXMYRTS_NAV_V1_8822C(x)                                        \
+	(((x) >> BIT_SHIFT_RXMYRTS_NAV_V1_8822C) &                             \
+	 BIT_MASK_RXMYRTS_NAV_V1_8822C)
+#define BIT_SET_RXMYRTS_NAV_V1_8822C(x, v)                                     \
+	(BIT_CLEAR_RXMYRTS_NAV_V1_8822C(x) | BIT_RXMYRTS_NAV_V1_8822C(v))
+
+#define BIT_SHIFT_RTSRST_V1_8822C 0
+#define BIT_MASK_RTSRST_V1_8822C 0xff
+#define BIT_RTSRST_V1_8822C(x)                                                 \
+	(((x) & BIT_MASK_RTSRST_V1_8822C) << BIT_SHIFT_RTSRST_V1_8822C)
+#define BITS_RTSRST_V1_8822C                                                   \
+	(BIT_MASK_RTSRST_V1_8822C << BIT_SHIFT_RTSRST_V1_8822C)
+#define BIT_CLEAR_RTSRST_V1_8822C(x) ((x) & (~BITS_RTSRST_V1_8822C))
+#define BIT_GET_RTSRST_V1_8822C(x)                                             \
+	(((x) >> BIT_SHIFT_RTSRST_V1_8822C) & BIT_MASK_RTSRST_V1_8822C)
+#define BIT_SET_RTSRST_V1_8822C(x, v)                                          \
+	(BIT_CLEAR_RTSRST_V1_8822C(x) | BIT_RTSRST_V1_8822C(v))
+
+/* 2 REG_WLAN_ACT_MASK_CTRL_1_8822C */
+#define BIT_WLRX_TER_BY_CTL_1_8822C BIT(11)
+#define BIT_WLRX_TER_BY_AD_1_8822C BIT(10)
+#define BIT_ANT_DIVERSITY_SEL_1_8822C BIT(9)
+#define BIT_ANTSEL_FOR_BT_CTRL_EN_1_8822C BIT(8)
+#define BIT_WLACT_LOW_GNTWL_EN_1_8822C BIT(2)
+#define BIT_WLACT_HIGH_GNTBT_EN_1_8822C BIT(1)
+#define BIT_NAV_UPPER_1_V1_8822C BIT(0)
+
+/* 2 REG_BT_COEX_ENHANCED_INTR_CTRL_8822C */
+
+#define BIT_SHIFT_BT_STAT_DELAY_8822C 12
+#define BIT_MASK_BT_STAT_DELAY_8822C 0xf
+#define BIT_BT_STAT_DELAY_8822C(x)                                             \
+	(((x) & BIT_MASK_BT_STAT_DELAY_8822C) << BIT_SHIFT_BT_STAT_DELAY_8822C)
+#define BITS_BT_STAT_DELAY_8822C                                               \
+	(BIT_MASK_BT_STAT_DELAY_8822C << BIT_SHIFT_BT_STAT_DELAY_8822C)
+#define BIT_CLEAR_BT_STAT_DELAY_8822C(x) ((x) & (~BITS_BT_STAT_DELAY_8822C))
+#define BIT_GET_BT_STAT_DELAY_8822C(x)                                         \
+	(((x) >> BIT_SHIFT_BT_STAT_DELAY_8822C) & BIT_MASK_BT_STAT_DELAY_8822C)
+#define BIT_SET_BT_STAT_DELAY_8822C(x, v)                                      \
+	(BIT_CLEAR_BT_STAT_DELAY_8822C(x) | BIT_BT_STAT_DELAY_8822C(v))
+
+#define BIT_SHIFT_BT_TRX_INIT_DETECT_8822C 8
+#define BIT_MASK_BT_TRX_INIT_DETECT_8822C 0xf
+#define BIT_BT_TRX_INIT_DETECT_8822C(x)                                        \
+	(((x) & BIT_MASK_BT_TRX_INIT_DETECT_8822C)                             \
+	 << BIT_SHIFT_BT_TRX_INIT_DETECT_8822C)
+#define BITS_BT_TRX_INIT_DETECT_8822C                                          \
+	(BIT_MASK_BT_TRX_INIT_DETECT_8822C                                     \
+	 << BIT_SHIFT_BT_TRX_INIT_DETECT_8822C)
+#define BIT_CLEAR_BT_TRX_INIT_DETECT_8822C(x)                                  \
+	((x) & (~BITS_BT_TRX_INIT_DETECT_8822C))
+#define BIT_GET_BT_TRX_INIT_DETECT_8822C(x)                                    \
+	(((x) >> BIT_SHIFT_BT_TRX_INIT_DETECT_8822C) &                         \
+	 BIT_MASK_BT_TRX_INIT_DETECT_8822C)
+#define BIT_SET_BT_TRX_INIT_DETECT_8822C(x, v)                                 \
+	(BIT_CLEAR_BT_TRX_INIT_DETECT_8822C(x) |                               \
+	 BIT_BT_TRX_INIT_DETECT_8822C(v))
+
+#define BIT_SHIFT_BT_PRI_DETECT_TO_8822C 4
+#define BIT_MASK_BT_PRI_DETECT_TO_8822C 0xf
+#define BIT_BT_PRI_DETECT_TO_8822C(x)                                          \
+	(((x) & BIT_MASK_BT_PRI_DETECT_TO_8822C)                               \
+	 << BIT_SHIFT_BT_PRI_DETECT_TO_8822C)
+#define BITS_BT_PRI_DETECT_TO_8822C                                            \
+	(BIT_MASK_BT_PRI_DETECT_TO_8822C << BIT_SHIFT_BT_PRI_DETECT_TO_8822C)
+#define BIT_CLEAR_BT_PRI_DETECT_TO_8822C(x)                                    \
+	((x) & (~BITS_BT_PRI_DETECT_TO_8822C))
+#define BIT_GET_BT_PRI_DETECT_TO_8822C(x)                                      \
+	(((x) >> BIT_SHIFT_BT_PRI_DETECT_TO_8822C) &                           \
+	 BIT_MASK_BT_PRI_DETECT_TO_8822C)
+#define BIT_SET_BT_PRI_DETECT_TO_8822C(x, v)                                   \
+	(BIT_CLEAR_BT_PRI_DETECT_TO_8822C(x) | BIT_BT_PRI_DETECT_TO_8822C(v))
+
+#define BIT_R_GRANTALL_WLMASK_8822C BIT(3)
+#define BIT_STATIS_BT_EN_8822C BIT(2)
+#define BIT_WL_ACT_MASK_ENABLE_8822C BIT(1)
+#define BIT_ENHANCED_BT_8822C BIT(0)
+
+/* 2 REG_BT_ACT_STATISTICS_8822C */
+
+#define BIT_SHIFT_STATIS_BT_HI_RX_8822C 16
+#define BIT_MASK_STATIS_BT_HI_RX_8822C 0xffff
+#define BIT_STATIS_BT_HI_RX_8822C(x)                                           \
+	(((x) & BIT_MASK_STATIS_BT_HI_RX_8822C)                                \
+	 << BIT_SHIFT_STATIS_BT_HI_RX_8822C)
+#define BITS_STATIS_BT_HI_RX_8822C                                             \
+	(BIT_MASK_STATIS_BT_HI_RX_8822C << BIT_SHIFT_STATIS_BT_HI_RX_8822C)
+#define BIT_CLEAR_STATIS_BT_HI_RX_8822C(x) ((x) & (~BITS_STATIS_BT_HI_RX_8822C))
+#define BIT_GET_STATIS_BT_HI_RX_8822C(x)                                       \
+	(((x) >> BIT_SHIFT_STATIS_BT_HI_RX_8822C) &                            \
+	 BIT_MASK_STATIS_BT_HI_RX_8822C)
+#define BIT_SET_STATIS_BT_HI_RX_8822C(x, v)                                    \
+	(BIT_CLEAR_STATIS_BT_HI_RX_8822C(x) | BIT_STATIS_BT_HI_RX_8822C(v))
+
+#define BIT_SHIFT_STATIS_BT_HI_TX_8822C 0
+#define BIT_MASK_STATIS_BT_HI_TX_8822C 0xffff
+#define BIT_STATIS_BT_HI_TX_8822C(x)                                           \
+	(((x) & BIT_MASK_STATIS_BT_HI_TX_8822C)                                \
+	 << BIT_SHIFT_STATIS_BT_HI_TX_8822C)
+#define BITS_STATIS_BT_HI_TX_8822C                                             \
+	(BIT_MASK_STATIS_BT_HI_TX_8822C << BIT_SHIFT_STATIS_BT_HI_TX_8822C)
+#define BIT_CLEAR_STATIS_BT_HI_TX_8822C(x) ((x) & (~BITS_STATIS_BT_HI_TX_8822C))
+#define BIT_GET_STATIS_BT_HI_TX_8822C(x)                                       \
+	(((x) >> BIT_SHIFT_STATIS_BT_HI_TX_8822C) &                            \
+	 BIT_MASK_STATIS_BT_HI_TX_8822C)
+#define BIT_SET_STATIS_BT_HI_TX_8822C(x, v)                                    \
+	(BIT_CLEAR_STATIS_BT_HI_TX_8822C(x) | BIT_STATIS_BT_HI_TX_8822C(v))
+
+/* 2 REG_BT_ACT_STATISTICS_1_8822C */
+
+#define BIT_SHIFT_STATIS_BT_LO_RX_1_8822C 16
+#define BIT_MASK_STATIS_BT_LO_RX_1_8822C 0xffff
+#define BIT_STATIS_BT_LO_RX_1_8822C(x)                                         \
+	(((x) & BIT_MASK_STATIS_BT_LO_RX_1_8822C)                              \
+	 << BIT_SHIFT_STATIS_BT_LO_RX_1_8822C)
+#define BITS_STATIS_BT_LO_RX_1_8822C                                           \
+	(BIT_MASK_STATIS_BT_LO_RX_1_8822C << BIT_SHIFT_STATIS_BT_LO_RX_1_8822C)
+#define BIT_CLEAR_STATIS_BT_LO_RX_1_8822C(x)                                   \
+	((x) & (~BITS_STATIS_BT_LO_RX_1_8822C))
+#define BIT_GET_STATIS_BT_LO_RX_1_8822C(x)                                     \
+	(((x) >> BIT_SHIFT_STATIS_BT_LO_RX_1_8822C) &                          \
+	 BIT_MASK_STATIS_BT_LO_RX_1_8822C)
+#define BIT_SET_STATIS_BT_LO_RX_1_8822C(x, v)                                  \
+	(BIT_CLEAR_STATIS_BT_LO_RX_1_8822C(x) | BIT_STATIS_BT_LO_RX_1_8822C(v))
+
+#define BIT_SHIFT_STATIS_BT_LO_TX_1_8822C 0
+#define BIT_MASK_STATIS_BT_LO_TX_1_8822C 0xffff
+#define BIT_STATIS_BT_LO_TX_1_8822C(x)                                         \
+	(((x) & BIT_MASK_STATIS_BT_LO_TX_1_8822C)                              \
+	 << BIT_SHIFT_STATIS_BT_LO_TX_1_8822C)
+#define BITS_STATIS_BT_LO_TX_1_8822C                                           \
+	(BIT_MASK_STATIS_BT_LO_TX_1_8822C << BIT_SHIFT_STATIS_BT_LO_TX_1_8822C)
+#define BIT_CLEAR_STATIS_BT_LO_TX_1_8822C(x)                                   \
+	((x) & (~BITS_STATIS_BT_LO_TX_1_8822C))
+#define BIT_GET_STATIS_BT_LO_TX_1_8822C(x)                                     \
+	(((x) >> BIT_SHIFT_STATIS_BT_LO_TX_1_8822C) &                          \
+	 BIT_MASK_STATIS_BT_LO_TX_1_8822C)
+#define BIT_SET_STATIS_BT_LO_TX_1_8822C(x, v)                                  \
+	(BIT_CLEAR_STATIS_BT_LO_TX_1_8822C(x) | BIT_STATIS_BT_LO_TX_1_8822C(v))
+
+/* 2 REG_BT_STATISTICS_CONTROL_REGISTER_8822C */
+
+#define BIT_SHIFT_R_BT_CMD_RPT_8822C 16
+#define BIT_MASK_R_BT_CMD_RPT_8822C 0xffff
+#define BIT_R_BT_CMD_RPT_8822C(x)                                              \
+	(((x) & BIT_MASK_R_BT_CMD_RPT_8822C) << BIT_SHIFT_R_BT_CMD_RPT_8822C)
+#define BITS_R_BT_CMD_RPT_8822C                                                \
+	(BIT_MASK_R_BT_CMD_RPT_8822C << BIT_SHIFT_R_BT_CMD_RPT_8822C)
+#define BIT_CLEAR_R_BT_CMD_RPT_8822C(x) ((x) & (~BITS_R_BT_CMD_RPT_8822C))
+#define BIT_GET_R_BT_CMD_RPT_8822C(x)                                          \
+	(((x) >> BIT_SHIFT_R_BT_CMD_RPT_8822C) & BIT_MASK_R_BT_CMD_RPT_8822C)
+#define BIT_SET_R_BT_CMD_RPT_8822C(x, v)                                       \
+	(BIT_CLEAR_R_BT_CMD_RPT_8822C(x) | BIT_R_BT_CMD_RPT_8822C(v))
+
+#define BIT_SHIFT_R_RPT_FROM_BT_8822C 8
+#define BIT_MASK_R_RPT_FROM_BT_8822C 0xff
+#define BIT_R_RPT_FROM_BT_8822C(x)                                             \
+	(((x) & BIT_MASK_R_RPT_FROM_BT_8822C) << BIT_SHIFT_R_RPT_FROM_BT_8822C)
+#define BITS_R_RPT_FROM_BT_8822C                                               \
+	(BIT_MASK_R_RPT_FROM_BT_8822C << BIT_SHIFT_R_RPT_FROM_BT_8822C)
+#define BIT_CLEAR_R_RPT_FROM_BT_8822C(x) ((x) & (~BITS_R_RPT_FROM_BT_8822C))
+#define BIT_GET_R_RPT_FROM_BT_8822C(x)                                         \
+	(((x) >> BIT_SHIFT_R_RPT_FROM_BT_8822C) & BIT_MASK_R_RPT_FROM_BT_8822C)
+#define BIT_SET_R_RPT_FROM_BT_8822C(x, v)                                      \
+	(BIT_CLEAR_R_RPT_FROM_BT_8822C(x) | BIT_R_RPT_FROM_BT_8822C(v))
+
+#define BIT_SHIFT_BT_HID_ISR_SET_8822C 6
+#define BIT_MASK_BT_HID_ISR_SET_8822C 0x3
+#define BIT_BT_HID_ISR_SET_8822C(x)                                            \
+	(((x) & BIT_MASK_BT_HID_ISR_SET_8822C)                                 \
+	 << BIT_SHIFT_BT_HID_ISR_SET_8822C)
+#define BITS_BT_HID_ISR_SET_8822C                                              \
+	(BIT_MASK_BT_HID_ISR_SET_8822C << BIT_SHIFT_BT_HID_ISR_SET_8822C)
+#define BIT_CLEAR_BT_HID_ISR_SET_8822C(x) ((x) & (~BITS_BT_HID_ISR_SET_8822C))
+#define BIT_GET_BT_HID_ISR_SET_8822C(x)                                        \
+	(((x) >> BIT_SHIFT_BT_HID_ISR_SET_8822C) &                             \
+	 BIT_MASK_BT_HID_ISR_SET_8822C)
+#define BIT_SET_BT_HID_ISR_SET_8822C(x, v)                                     \
+	(BIT_CLEAR_BT_HID_ISR_SET_8822C(x) | BIT_BT_HID_ISR_SET_8822C(v))
+
+#define BIT_TDMA_BT_START_NOTIFY_8822C BIT(5)
+#define BIT_ENABLE_TDMA_FW_MODE_8822C BIT(4)
+#define BIT_ENABLE_PTA_TDMA_MODE_8822C BIT(3)
+#define BIT_ENABLE_COEXIST_TAB_IN_TDMA_8822C BIT(2)
+#define BIT_GPIO2_GPIO3_EXANGE_OR_NO_BT_CCA_8822C BIT(1)
+#define BIT_RTK_BT_ENABLE_8822C BIT(0)
+
+/* 2 REG_BT_STATUS_REPORT_REGISTER_8822C */
+
+#define BIT_SHIFT_BT_PROFILE_8822C 24
+#define BIT_MASK_BT_PROFILE_8822C 0xff
+#define BIT_BT_PROFILE_8822C(x)                                                \
+	(((x) & BIT_MASK_BT_PROFILE_8822C) << BIT_SHIFT_BT_PROFILE_8822C)
+#define BITS_BT_PROFILE_8822C                                                  \
+	(BIT_MASK_BT_PROFILE_8822C << BIT_SHIFT_BT_PROFILE_8822C)
+#define BIT_CLEAR_BT_PROFILE_8822C(x) ((x) & (~BITS_BT_PROFILE_8822C))
+#define BIT_GET_BT_PROFILE_8822C(x)                                            \
+	(((x) >> BIT_SHIFT_BT_PROFILE_8822C) & BIT_MASK_BT_PROFILE_8822C)
+#define BIT_SET_BT_PROFILE_8822C(x, v)                                         \
+	(BIT_CLEAR_BT_PROFILE_8822C(x) | BIT_BT_PROFILE_8822C(v))
+
+#define BIT_SHIFT_BT_POWER_8822C 16
+#define BIT_MASK_BT_POWER_8822C 0xff
+#define BIT_BT_POWER_8822C(x)                                                  \
+	(((x) & BIT_MASK_BT_POWER_8822C) << BIT_SHIFT_BT_POWER_8822C)
+#define BITS_BT_POWER_8822C                                                    \
+	(BIT_MASK_BT_POWER_8822C << BIT_SHIFT_BT_POWER_8822C)
+#define BIT_CLEAR_BT_POWER_8822C(x) ((x) & (~BITS_BT_POWER_8822C))
+#define BIT_GET_BT_POWER_8822C(x)                                              \
+	(((x) >> BIT_SHIFT_BT_POWER_8822C) & BIT_MASK_BT_POWER_8822C)
+#define BIT_SET_BT_POWER_8822C(x, v)                                           \
+	(BIT_CLEAR_BT_POWER_8822C(x) | BIT_BT_POWER_8822C(v))
+
+#define BIT_SHIFT_BT_PREDECT_STATUS_8822C 8
+#define BIT_MASK_BT_PREDECT_STATUS_8822C 0xff
+#define BIT_BT_PREDECT_STATUS_8822C(x)                                         \
+	(((x) & BIT_MASK_BT_PREDECT_STATUS_8822C)                              \
+	 << BIT_SHIFT_BT_PREDECT_STATUS_8822C)
+#define BITS_BT_PREDECT_STATUS_8822C                                           \
+	(BIT_MASK_BT_PREDECT_STATUS_8822C << BIT_SHIFT_BT_PREDECT_STATUS_8822C)
+#define BIT_CLEAR_BT_PREDECT_STATUS_8822C(x)                                   \
+	((x) & (~BITS_BT_PREDECT_STATUS_8822C))
+#define BIT_GET_BT_PREDECT_STATUS_8822C(x)                                     \
+	(((x) >> BIT_SHIFT_BT_PREDECT_STATUS_8822C) &                          \
+	 BIT_MASK_BT_PREDECT_STATUS_8822C)
+#define BIT_SET_BT_PREDECT_STATUS_8822C(x, v)                                  \
+	(BIT_CLEAR_BT_PREDECT_STATUS_8822C(x) | BIT_BT_PREDECT_STATUS_8822C(v))
+
+#define BIT_SHIFT_BT_CMD_INFO_8822C 0
+#define BIT_MASK_BT_CMD_INFO_8822C 0xff
+#define BIT_BT_CMD_INFO_8822C(x)                                               \
+	(((x) & BIT_MASK_BT_CMD_INFO_8822C) << BIT_SHIFT_BT_CMD_INFO_8822C)
+#define BITS_BT_CMD_INFO_8822C                                                 \
+	(BIT_MASK_BT_CMD_INFO_8822C << BIT_SHIFT_BT_CMD_INFO_8822C)
+#define BIT_CLEAR_BT_CMD_INFO_8822C(x) ((x) & (~BITS_BT_CMD_INFO_8822C))
+#define BIT_GET_BT_CMD_INFO_8822C(x)                                           \
+	(((x) >> BIT_SHIFT_BT_CMD_INFO_8822C) & BIT_MASK_BT_CMD_INFO_8822C)
+#define BIT_SET_BT_CMD_INFO_8822C(x, v)                                        \
+	(BIT_CLEAR_BT_CMD_INFO_8822C(x) | BIT_BT_CMD_INFO_8822C(v))
+
+/* 2 REG_BT_INTERRUPT_CONTROL_REGISTER_8822C */
+#define BIT_EN_MAC_NULL_PKT_NOTIFY_8822C BIT(31)
+#define BIT_EN_WLAN_RPT_AND_BT_QUERY_8822C BIT(30)
+#define BIT_EN_BT_STSTUS_RPT_8822C BIT(29)
+#define BIT_EN_BT_POWER_8822C BIT(28)
+#define BIT_EN_BT_CHANNEL_8822C BIT(27)
+#define BIT_EN_BT_SLOT_CHANGE_8822C BIT(26)
+#define BIT_EN_BT_PROFILE_OR_HID_8822C BIT(25)
+#define BIT_WLAN_RPT_NOTIFY_8822C BIT(24)
+
+#define BIT_SHIFT_WLAN_RPT_DATA_8822C 16
+#define BIT_MASK_WLAN_RPT_DATA_8822C 0xff
+#define BIT_WLAN_RPT_DATA_8822C(x)                                             \
+	(((x) & BIT_MASK_WLAN_RPT_DATA_8822C) << BIT_SHIFT_WLAN_RPT_DATA_8822C)
+#define BITS_WLAN_RPT_DATA_8822C                                               \
+	(BIT_MASK_WLAN_RPT_DATA_8822C << BIT_SHIFT_WLAN_RPT_DATA_8822C)
+#define BIT_CLEAR_WLAN_RPT_DATA_8822C(x) ((x) & (~BITS_WLAN_RPT_DATA_8822C))
+#define BIT_GET_WLAN_RPT_DATA_8822C(x)                                         \
+	(((x) >> BIT_SHIFT_WLAN_RPT_DATA_8822C) & BIT_MASK_WLAN_RPT_DATA_8822C)
+#define BIT_SET_WLAN_RPT_DATA_8822C(x, v)                                      \
+	(BIT_CLEAR_WLAN_RPT_DATA_8822C(x) | BIT_WLAN_RPT_DATA_8822C(v))
+
+#define BIT_SHIFT_CMD_ID_8822C 8
+#define BIT_MASK_CMD_ID_8822C 0xff
+#define BIT_CMD_ID_8822C(x)                                                    \
+	(((x) & BIT_MASK_CMD_ID_8822C) << BIT_SHIFT_CMD_ID_8822C)
+#define BITS_CMD_ID_8822C (BIT_MASK_CMD_ID_8822C << BIT_SHIFT_CMD_ID_8822C)
+#define BIT_CLEAR_CMD_ID_8822C(x) ((x) & (~BITS_CMD_ID_8822C))
+#define BIT_GET_CMD_ID_8822C(x)                                                \
+	(((x) >> BIT_SHIFT_CMD_ID_8822C) & BIT_MASK_CMD_ID_8822C)
+#define BIT_SET_CMD_ID_8822C(x, v)                                             \
+	(BIT_CLEAR_CMD_ID_8822C(x) | BIT_CMD_ID_8822C(v))
+
+#define BIT_SHIFT_BT_DATA_8822C 0
+#define BIT_MASK_BT_DATA_8822C 0xff
+#define BIT_BT_DATA_8822C(x)                                                   \
+	(((x) & BIT_MASK_BT_DATA_8822C) << BIT_SHIFT_BT_DATA_8822C)
+#define BITS_BT_DATA_8822C (BIT_MASK_BT_DATA_8822C << BIT_SHIFT_BT_DATA_8822C)
+#define BIT_CLEAR_BT_DATA_8822C(x) ((x) & (~BITS_BT_DATA_8822C))
+#define BIT_GET_BT_DATA_8822C(x)                                               \
+	(((x) >> BIT_SHIFT_BT_DATA_8822C) & BIT_MASK_BT_DATA_8822C)
+#define BIT_SET_BT_DATA_8822C(x, v)                                            \
+	(BIT_CLEAR_BT_DATA_8822C(x) | BIT_BT_DATA_8822C(v))
+
+/* 2 REG_WLAN_REPORT_TIME_OUT_CONTROL_REGISTER_8822C */
+
+#define BIT_SHIFT_WLAN_RPT_TO_8822C 0
+#define BIT_MASK_WLAN_RPT_TO_8822C 0xff
+#define BIT_WLAN_RPT_TO_8822C(x)                                               \
+	(((x) & BIT_MASK_WLAN_RPT_TO_8822C) << BIT_SHIFT_WLAN_RPT_TO_8822C)
+#define BITS_WLAN_RPT_TO_8822C                                                 \
+	(BIT_MASK_WLAN_RPT_TO_8822C << BIT_SHIFT_WLAN_RPT_TO_8822C)
+#define BIT_CLEAR_WLAN_RPT_TO_8822C(x) ((x) & (~BITS_WLAN_RPT_TO_8822C))
+#define BIT_GET_WLAN_RPT_TO_8822C(x)                                           \
+	(((x) >> BIT_SHIFT_WLAN_RPT_TO_8822C) & BIT_MASK_WLAN_RPT_TO_8822C)
+#define BIT_SET_WLAN_RPT_TO_8822C(x, v)                                        \
+	(BIT_CLEAR_WLAN_RPT_TO_8822C(x) | BIT_WLAN_RPT_TO_8822C(v))
+
+/* 2 REG_BT_ISOLATION_TABLE_REGISTER_REGISTER_8822C */
+
+#define BIT_SHIFT_ISOLATION_CHK_0_8822C 1
+#define BIT_MASK_ISOLATION_CHK_0_8822C 0x7fffff
+#define BIT_ISOLATION_CHK_0_8822C(x)                                           \
+	(((x) & BIT_MASK_ISOLATION_CHK_0_8822C)                                \
+	 << BIT_SHIFT_ISOLATION_CHK_0_8822C)
+#define BITS_ISOLATION_CHK_0_8822C                                             \
+	(BIT_MASK_ISOLATION_CHK_0_8822C << BIT_SHIFT_ISOLATION_CHK_0_8822C)
+#define BIT_CLEAR_ISOLATION_CHK_0_8822C(x) ((x) & (~BITS_ISOLATION_CHK_0_8822C))
+#define BIT_GET_ISOLATION_CHK_0_8822C(x)                                       \
+	(((x) >> BIT_SHIFT_ISOLATION_CHK_0_8822C) &                            \
+	 BIT_MASK_ISOLATION_CHK_0_8822C)
+#define BIT_SET_ISOLATION_CHK_0_8822C(x, v)                                    \
+	(BIT_CLEAR_ISOLATION_CHK_0_8822C(x) | BIT_ISOLATION_CHK_0_8822C(v))
+
+#define BIT_ISOLATION_EN_8822C BIT(0)
+
+/* 2 REG_BT_ISOLATION_TABLE_REGISTER_REGISTER_1_8822C */
+
+#define BIT_SHIFT_ISOLATION_CHK_1_8822C 0
+#define BIT_MASK_ISOLATION_CHK_1_8822C 0xffffffffL
+#define BIT_ISOLATION_CHK_1_8822C(x)                                           \
+	(((x) & BIT_MASK_ISOLATION_CHK_1_8822C)                                \
+	 << BIT_SHIFT_ISOLATION_CHK_1_8822C)
+#define BITS_ISOLATION_CHK_1_8822C                                             \
+	(BIT_MASK_ISOLATION_CHK_1_8822C << BIT_SHIFT_ISOLATION_CHK_1_8822C)
+#define BIT_CLEAR_ISOLATION_CHK_1_8822C(x) ((x) & (~BITS_ISOLATION_CHK_1_8822C))
+#define BIT_GET_ISOLATION_CHK_1_8822C(x)                                       \
+	(((x) >> BIT_SHIFT_ISOLATION_CHK_1_8822C) &                            \
+	 BIT_MASK_ISOLATION_CHK_1_8822C)
+#define BIT_SET_ISOLATION_CHK_1_8822C(x, v)                                    \
+	(BIT_CLEAR_ISOLATION_CHK_1_8822C(x) | BIT_ISOLATION_CHK_1_8822C(v))
+
+/* 2 REG_BT_ISOLATION_TABLE_REGISTER_REGISTER_2_8822C */
+
+#define BIT_SHIFT_ISOLATION_CHK_2_8822C 0
+#define BIT_MASK_ISOLATION_CHK_2_8822C 0xffffff
+#define BIT_ISOLATION_CHK_2_8822C(x)                                           \
+	(((x) & BIT_MASK_ISOLATION_CHK_2_8822C)                                \
+	 << BIT_SHIFT_ISOLATION_CHK_2_8822C)
+#define BITS_ISOLATION_CHK_2_8822C                                             \
+	(BIT_MASK_ISOLATION_CHK_2_8822C << BIT_SHIFT_ISOLATION_CHK_2_8822C)
+#define BIT_CLEAR_ISOLATION_CHK_2_8822C(x) ((x) & (~BITS_ISOLATION_CHK_2_8822C))
+#define BIT_GET_ISOLATION_CHK_2_8822C(x)                                       \
+	(((x) >> BIT_SHIFT_ISOLATION_CHK_2_8822C) &                            \
+	 BIT_MASK_ISOLATION_CHK_2_8822C)
+#define BIT_SET_ISOLATION_CHK_2_8822C(x, v)                                    \
+	(BIT_CLEAR_ISOLATION_CHK_2_8822C(x) | BIT_ISOLATION_CHK_2_8822C(v))
+
+/* 2 REG_BT_INTERRUPT_STATUS_REGISTER_8822C */
+#define BIT_BT_HID_ISR_8822C BIT(7)
+#define BIT_BT_QUERY_ISR_8822C BIT(6)
+#define BIT_MAC_NULL_PKT_NOTIFY_ISR_8822C BIT(5)
+#define BIT_WLAN_RPT_ISR_8822C BIT(4)
+#define BIT_BT_POWER_ISR_8822C BIT(3)
+#define BIT_BT_CHANNEL_ISR_8822C BIT(2)
+#define BIT_BT_SLOT_CHANGE_ISR_8822C BIT(1)
+#define BIT_BT_PROFILE_ISR_8822C BIT(0)
+
+/* 2 REG_BT_TDMA_TIME_REGISTER_8822C */
+
+#define BIT_SHIFT_BT_TIME_8822C 6
+#define BIT_MASK_BT_TIME_8822C 0x3ffffff
+#define BIT_BT_TIME_8822C(x)                                                   \
+	(((x) & BIT_MASK_BT_TIME_8822C) << BIT_SHIFT_BT_TIME_8822C)
+#define BITS_BT_TIME_8822C (BIT_MASK_BT_TIME_8822C << BIT_SHIFT_BT_TIME_8822C)
+#define BIT_CLEAR_BT_TIME_8822C(x) ((x) & (~BITS_BT_TIME_8822C))
+#define BIT_GET_BT_TIME_8822C(x)                                               \
+	(((x) >> BIT_SHIFT_BT_TIME_8822C) & BIT_MASK_BT_TIME_8822C)
+#define BIT_SET_BT_TIME_8822C(x, v)                                            \
+	(BIT_CLEAR_BT_TIME_8822C(x) | BIT_BT_TIME_8822C(v))
+
+#define BIT_SHIFT_BT_RPT_SAMPLE_RATE_8822C 0
+#define BIT_MASK_BT_RPT_SAMPLE_RATE_8822C 0x3f
+#define BIT_BT_RPT_SAMPLE_RATE_8822C(x)                                        \
+	(((x) & BIT_MASK_BT_RPT_SAMPLE_RATE_8822C)                             \
+	 << BIT_SHIFT_BT_RPT_SAMPLE_RATE_8822C)
+#define BITS_BT_RPT_SAMPLE_RATE_8822C                                          \
+	(BIT_MASK_BT_RPT_SAMPLE_RATE_8822C                                     \
+	 << BIT_SHIFT_BT_RPT_SAMPLE_RATE_8822C)
+#define BIT_CLEAR_BT_RPT_SAMPLE_RATE_8822C(x)                                  \
+	((x) & (~BITS_BT_RPT_SAMPLE_RATE_8822C))
+#define BIT_GET_BT_RPT_SAMPLE_RATE_8822C(x)                                    \
+	(((x) >> BIT_SHIFT_BT_RPT_SAMPLE_RATE_8822C) &                         \
+	 BIT_MASK_BT_RPT_SAMPLE_RATE_8822C)
+#define BIT_SET_BT_RPT_SAMPLE_RATE_8822C(x, v)                                 \
+	(BIT_CLEAR_BT_RPT_SAMPLE_RATE_8822C(x) |                               \
+	 BIT_BT_RPT_SAMPLE_RATE_8822C(v))
+
+/* 2 REG_BT_ACT_REGISTER_8822C */
+
+#define BIT_SHIFT_BT_EISR_EN_8822C 16
+#define BIT_MASK_BT_EISR_EN_8822C 0xff
+#define BIT_BT_EISR_EN_8822C(x)                                                \
+	(((x) & BIT_MASK_BT_EISR_EN_8822C) << BIT_SHIFT_BT_EISR_EN_8822C)
+#define BITS_BT_EISR_EN_8822C                                                  \
+	(BIT_MASK_BT_EISR_EN_8822C << BIT_SHIFT_BT_EISR_EN_8822C)
+#define BIT_CLEAR_BT_EISR_EN_8822C(x) ((x) & (~BITS_BT_EISR_EN_8822C))
+#define BIT_GET_BT_EISR_EN_8822C(x)                                            \
+	(((x) >> BIT_SHIFT_BT_EISR_EN_8822C) & BIT_MASK_BT_EISR_EN_8822C)
+#define BIT_SET_BT_EISR_EN_8822C(x, v)                                         \
+	(BIT_CLEAR_BT_EISR_EN_8822C(x) | BIT_BT_EISR_EN_8822C(v))
+
+#define BIT_BT_ACT_FALLING_ISR_8822C BIT(10)
+#define BIT_BT_ACT_RISING_ISR_8822C BIT(9)
+#define BIT_TDMA_TO_ISR_8822C BIT(8)
+
+#define BIT_SHIFT_BT_CH_V1_8822C 0
+#define BIT_MASK_BT_CH_V1_8822C 0x7f
+#define BIT_BT_CH_V1_8822C(x)                                                  \
+	(((x) & BIT_MASK_BT_CH_V1_8822C) << BIT_SHIFT_BT_CH_V1_8822C)
+#define BITS_BT_CH_V1_8822C                                                    \
+	(BIT_MASK_BT_CH_V1_8822C << BIT_SHIFT_BT_CH_V1_8822C)
+#define BIT_CLEAR_BT_CH_V1_8822C(x) ((x) & (~BITS_BT_CH_V1_8822C))
+#define BIT_GET_BT_CH_V1_8822C(x)                                              \
+	(((x) >> BIT_SHIFT_BT_CH_V1_8822C) & BIT_MASK_BT_CH_V1_8822C)
+#define BIT_SET_BT_CH_V1_8822C(x, v)                                           \
+	(BIT_CLEAR_BT_CH_V1_8822C(x) | BIT_BT_CH_V1_8822C(v))
+
+/* 2 REG_OBFF_CTRL_BASIC_8822C */
+#define BIT_OBFF_EN_V1_8822C BIT(31)
+
+#define BIT_SHIFT_OBFF_STATE_V1_8822C 28
+#define BIT_MASK_OBFF_STATE_V1_8822C 0x3
+#define BIT_OBFF_STATE_V1_8822C(x)                                             \
+	(((x) & BIT_MASK_OBFF_STATE_V1_8822C) << BIT_SHIFT_OBFF_STATE_V1_8822C)
+#define BITS_OBFF_STATE_V1_8822C                                               \
+	(BIT_MASK_OBFF_STATE_V1_8822C << BIT_SHIFT_OBFF_STATE_V1_8822C)
+#define BIT_CLEAR_OBFF_STATE_V1_8822C(x) ((x) & (~BITS_OBFF_STATE_V1_8822C))
+#define BIT_GET_OBFF_STATE_V1_8822C(x)                                         \
+	(((x) >> BIT_SHIFT_OBFF_STATE_V1_8822C) & BIT_MASK_OBFF_STATE_V1_8822C)
+#define BIT_SET_OBFF_STATE_V1_8822C(x, v)                                      \
+	(BIT_CLEAR_OBFF_STATE_V1_8822C(x) | BIT_OBFF_STATE_V1_8822C(v))
+
+#define BIT_OBFF_ACT_RXDMA_EN_8822C BIT(27)
+#define BIT_OBFF_BLOCK_INT_EN_8822C BIT(26)
+#define BIT_OBFF_AUTOACT_EN_8822C BIT(25)
+#define BIT_OBFF_AUTOIDLE_EN_8822C BIT(24)
+
+#define BIT_SHIFT_WAKE_MAX_PLS_8822C 20
+#define BIT_MASK_WAKE_MAX_PLS_8822C 0x7
+#define BIT_WAKE_MAX_PLS_8822C(x)                                              \
+	(((x) & BIT_MASK_WAKE_MAX_PLS_8822C) << BIT_SHIFT_WAKE_MAX_PLS_8822C)
+#define BITS_WAKE_MAX_PLS_8822C                                                \
+	(BIT_MASK_WAKE_MAX_PLS_8822C << BIT_SHIFT_WAKE_MAX_PLS_8822C)
+#define BIT_CLEAR_WAKE_MAX_PLS_8822C(x) ((x) & (~BITS_WAKE_MAX_PLS_8822C))
+#define BIT_GET_WAKE_MAX_PLS_8822C(x)                                          \
+	(((x) >> BIT_SHIFT_WAKE_MAX_PLS_8822C) & BIT_MASK_WAKE_MAX_PLS_8822C)
+#define BIT_SET_WAKE_MAX_PLS_8822C(x, v)                                       \
+	(BIT_CLEAR_WAKE_MAX_PLS_8822C(x) | BIT_WAKE_MAX_PLS_8822C(v))
+
+#define BIT_SHIFT_WAKE_MIN_PLS_8822C 16
+#define BIT_MASK_WAKE_MIN_PLS_8822C 0x7
+#define BIT_WAKE_MIN_PLS_8822C(x)                                              \
+	(((x) & BIT_MASK_WAKE_MIN_PLS_8822C) << BIT_SHIFT_WAKE_MIN_PLS_8822C)
+#define BITS_WAKE_MIN_PLS_8822C                                                \
+	(BIT_MASK_WAKE_MIN_PLS_8822C << BIT_SHIFT_WAKE_MIN_PLS_8822C)
+#define BIT_CLEAR_WAKE_MIN_PLS_8822C(x) ((x) & (~BITS_WAKE_MIN_PLS_8822C))
+#define BIT_GET_WAKE_MIN_PLS_8822C(x)                                          \
+	(((x) >> BIT_SHIFT_WAKE_MIN_PLS_8822C) & BIT_MASK_WAKE_MIN_PLS_8822C)
+#define BIT_SET_WAKE_MIN_PLS_8822C(x, v)                                       \
+	(BIT_CLEAR_WAKE_MIN_PLS_8822C(x) | BIT_WAKE_MIN_PLS_8822C(v))
+
+#define BIT_SHIFT_WAKE_MAX_F2F_8822C 12
+#define BIT_MASK_WAKE_MAX_F2F_8822C 0x7
+#define BIT_WAKE_MAX_F2F_8822C(x)                                              \
+	(((x) & BIT_MASK_WAKE_MAX_F2F_8822C) << BIT_SHIFT_WAKE_MAX_F2F_8822C)
+#define BITS_WAKE_MAX_F2F_8822C                                                \
+	(BIT_MASK_WAKE_MAX_F2F_8822C << BIT_SHIFT_WAKE_MAX_F2F_8822C)
+#define BIT_CLEAR_WAKE_MAX_F2F_8822C(x) ((x) & (~BITS_WAKE_MAX_F2F_8822C))
+#define BIT_GET_WAKE_MAX_F2F_8822C(x)                                          \
+	(((x) >> BIT_SHIFT_WAKE_MAX_F2F_8822C) & BIT_MASK_WAKE_MAX_F2F_8822C)
+#define BIT_SET_WAKE_MAX_F2F_8822C(x, v)                                       \
+	(BIT_CLEAR_WAKE_MAX_F2F_8822C(x) | BIT_WAKE_MAX_F2F_8822C(v))
+
+#define BIT_SHIFT_WAKE_MIN_F2F_8822C 8
+#define BIT_MASK_WAKE_MIN_F2F_8822C 0x7
+#define BIT_WAKE_MIN_F2F_8822C(x)                                              \
+	(((x) & BIT_MASK_WAKE_MIN_F2F_8822C) << BIT_SHIFT_WAKE_MIN_F2F_8822C)
+#define BITS_WAKE_MIN_F2F_8822C                                                \
+	(BIT_MASK_WAKE_MIN_F2F_8822C << BIT_SHIFT_WAKE_MIN_F2F_8822C)
+#define BIT_CLEAR_WAKE_MIN_F2F_8822C(x) ((x) & (~BITS_WAKE_MIN_F2F_8822C))
+#define BIT_GET_WAKE_MIN_F2F_8822C(x)                                          \
+	(((x) >> BIT_SHIFT_WAKE_MIN_F2F_8822C) & BIT_MASK_WAKE_MIN_F2F_8822C)
+#define BIT_SET_WAKE_MIN_F2F_8822C(x, v)                                       \
+	(BIT_CLEAR_WAKE_MIN_F2F_8822C(x) | BIT_WAKE_MIN_F2F_8822C(v))
+
+#define BIT_APP_CPU_ACT_V1_8822C BIT(3)
+#define BIT_APP_OBFF_V1_8822C BIT(2)
+#define BIT_APP_IDLE_V1_8822C BIT(1)
+#define BIT_APP_INIT_V1_8822C BIT(0)
+
+/* 2 REG_OBFF_CTRL2_TIMER_8822C */
+
+#define BIT_SHIFT_RX_HIGH_TIMER_IDX_8822C 24
+#define BIT_MASK_RX_HIGH_TIMER_IDX_8822C 0x7
+#define BIT_RX_HIGH_TIMER_IDX_8822C(x)                                         \
+	(((x) & BIT_MASK_RX_HIGH_TIMER_IDX_8822C)                              \
+	 << BIT_SHIFT_RX_HIGH_TIMER_IDX_8822C)
+#define BITS_RX_HIGH_TIMER_IDX_8822C                                           \
+	(BIT_MASK_RX_HIGH_TIMER_IDX_8822C << BIT_SHIFT_RX_HIGH_TIMER_IDX_8822C)
+#define BIT_CLEAR_RX_HIGH_TIMER_IDX_8822C(x)                                   \
+	((x) & (~BITS_RX_HIGH_TIMER_IDX_8822C))
+#define BIT_GET_RX_HIGH_TIMER_IDX_8822C(x)                                     \
+	(((x) >> BIT_SHIFT_RX_HIGH_TIMER_IDX_8822C) &                          \
+	 BIT_MASK_RX_HIGH_TIMER_IDX_8822C)
+#define BIT_SET_RX_HIGH_TIMER_IDX_8822C(x, v)                                  \
+	(BIT_CLEAR_RX_HIGH_TIMER_IDX_8822C(x) | BIT_RX_HIGH_TIMER_IDX_8822C(v))
+
+#define BIT_SHIFT_RX_MED_TIMER_IDX_8822C 16
+#define BIT_MASK_RX_MED_TIMER_IDX_8822C 0x7
+#define BIT_RX_MED_TIMER_IDX_8822C(x)                                          \
+	(((x) & BIT_MASK_RX_MED_TIMER_IDX_8822C)                               \
+	 << BIT_SHIFT_RX_MED_TIMER_IDX_8822C)
+#define BITS_RX_MED_TIMER_IDX_8822C                                            \
+	(BIT_MASK_RX_MED_TIMER_IDX_8822C << BIT_SHIFT_RX_MED_TIMER_IDX_8822C)
+#define BIT_CLEAR_RX_MED_TIMER_IDX_8822C(x)                                    \
+	((x) & (~BITS_RX_MED_TIMER_IDX_8822C))
+#define BIT_GET_RX_MED_TIMER_IDX_8822C(x)                                      \
+	(((x) >> BIT_SHIFT_RX_MED_TIMER_IDX_8822C) &                           \
+	 BIT_MASK_RX_MED_TIMER_IDX_8822C)
+#define BIT_SET_RX_MED_TIMER_IDX_8822C(x, v)                                   \
+	(BIT_CLEAR_RX_MED_TIMER_IDX_8822C(x) | BIT_RX_MED_TIMER_IDX_8822C(v))
+
+#define BIT_SHIFT_RX_LOW_TIMER_IDX_8822C 8
+#define BIT_MASK_RX_LOW_TIMER_IDX_8822C 0x7
+#define BIT_RX_LOW_TIMER_IDX_8822C(x)                                          \
+	(((x) & BIT_MASK_RX_LOW_TIMER_IDX_8822C)                               \
+	 << BIT_SHIFT_RX_LOW_TIMER_IDX_8822C)
+#define BITS_RX_LOW_TIMER_IDX_8822C                                            \
+	(BIT_MASK_RX_LOW_TIMER_IDX_8822C << BIT_SHIFT_RX_LOW_TIMER_IDX_8822C)
+#define BIT_CLEAR_RX_LOW_TIMER_IDX_8822C(x)                                    \
+	((x) & (~BITS_RX_LOW_TIMER_IDX_8822C))
+#define BIT_GET_RX_LOW_TIMER_IDX_8822C(x)                                      \
+	(((x) >> BIT_SHIFT_RX_LOW_TIMER_IDX_8822C) &                           \
+	 BIT_MASK_RX_LOW_TIMER_IDX_8822C)
+#define BIT_SET_RX_LOW_TIMER_IDX_8822C(x, v)                                   \
+	(BIT_CLEAR_RX_LOW_TIMER_IDX_8822C(x) | BIT_RX_LOW_TIMER_IDX_8822C(v))
+
+#define BIT_SHIFT_OBFF_INT_TIMER_IDX_8822C 0
+#define BIT_MASK_OBFF_INT_TIMER_IDX_8822C 0x7
+#define BIT_OBFF_INT_TIMER_IDX_8822C(x)                                        \
+	(((x) & BIT_MASK_OBFF_INT_TIMER_IDX_8822C)                             \
+	 << BIT_SHIFT_OBFF_INT_TIMER_IDX_8822C)
+#define BITS_OBFF_INT_TIMER_IDX_8822C                                          \
+	(BIT_MASK_OBFF_INT_TIMER_IDX_8822C                                     \
+	 << BIT_SHIFT_OBFF_INT_TIMER_IDX_8822C)
+#define BIT_CLEAR_OBFF_INT_TIMER_IDX_8822C(x)                                  \
+	((x) & (~BITS_OBFF_INT_TIMER_IDX_8822C))
+#define BIT_GET_OBFF_INT_TIMER_IDX_8822C(x)                                    \
+	(((x) >> BIT_SHIFT_OBFF_INT_TIMER_IDX_8822C) &                         \
+	 BIT_MASK_OBFF_INT_TIMER_IDX_8822C)
+#define BIT_SET_OBFF_INT_TIMER_IDX_8822C(x, v)                                 \
+	(BIT_CLEAR_OBFF_INT_TIMER_IDX_8822C(x) |                               \
+	 BIT_OBFF_INT_TIMER_IDX_8822C(v))
+
+/* 2 REG_LTR_CTRL_BASIC_8822C */
+#define BIT_LTR_EN_V1_8822C BIT(31)
+#define BIT_LTR_HW_EN_V1_8822C BIT(30)
+#define BIT_LRT_ACT_CTS_EN_8822C BIT(29)
+#define BIT_LTR_ACT_RXPKT_EN_8822C BIT(28)
+#define BIT_LTR_ACT_RXDMA_EN_8822C BIT(27)
+#define BIT_LTR_IDLE_NO_SNOOP_8822C BIT(26)
+#define BIT_SPDUP_MGTPKT_8822C BIT(25)
+#define BIT_RX_AGG_EN_8822C BIT(24)
+#define BIT_APP_LTR_ACT_8822C BIT(23)
+#define BIT_APP_LTR_IDLE_8822C BIT(22)
+
+#define BIT_SHIFT_HIGH_RATE_TRIG_SEL_8822C 20
+#define BIT_MASK_HIGH_RATE_TRIG_SEL_8822C 0x3
+#define BIT_HIGH_RATE_TRIG_SEL_8822C(x)                                        \
+	(((x) & BIT_MASK_HIGH_RATE_TRIG_SEL_8822C)                             \
+	 << BIT_SHIFT_HIGH_RATE_TRIG_SEL_8822C)
+#define BITS_HIGH_RATE_TRIG_SEL_8822C                                          \
+	(BIT_MASK_HIGH_RATE_TRIG_SEL_8822C                                     \
+	 << BIT_SHIFT_HIGH_RATE_TRIG_SEL_8822C)
+#define BIT_CLEAR_HIGH_RATE_TRIG_SEL_8822C(x)                                  \
+	((x) & (~BITS_HIGH_RATE_TRIG_SEL_8822C))
+#define BIT_GET_HIGH_RATE_TRIG_SEL_8822C(x)                                    \
+	(((x) >> BIT_SHIFT_HIGH_RATE_TRIG_SEL_8822C) &                         \
+	 BIT_MASK_HIGH_RATE_TRIG_SEL_8822C)
+#define BIT_SET_HIGH_RATE_TRIG_SEL_8822C(x, v)                                 \
+	(BIT_CLEAR_HIGH_RATE_TRIG_SEL_8822C(x) |                               \
+	 BIT_HIGH_RATE_TRIG_SEL_8822C(v))
+
+#define BIT_SHIFT_MED_RATE_TRIG_SEL_8822C 18
+#define BIT_MASK_MED_RATE_TRIG_SEL_8822C 0x3
+#define BIT_MED_RATE_TRIG_SEL_8822C(x)                                         \
+	(((x) & BIT_MASK_MED_RATE_TRIG_SEL_8822C)                              \
+	 << BIT_SHIFT_MED_RATE_TRIG_SEL_8822C)
+#define BITS_MED_RATE_TRIG_SEL_8822C                                           \
+	(BIT_MASK_MED_RATE_TRIG_SEL_8822C << BIT_SHIFT_MED_RATE_TRIG_SEL_8822C)
+#define BIT_CLEAR_MED_RATE_TRIG_SEL_8822C(x)                                   \
+	((x) & (~BITS_MED_RATE_TRIG_SEL_8822C))
+#define BIT_GET_MED_RATE_TRIG_SEL_8822C(x)                                     \
+	(((x) >> BIT_SHIFT_MED_RATE_TRIG_SEL_8822C) &                          \
+	 BIT_MASK_MED_RATE_TRIG_SEL_8822C)
+#define BIT_SET_MED_RATE_TRIG_SEL_8822C(x, v)                                  \
+	(BIT_CLEAR_MED_RATE_TRIG_SEL_8822C(x) | BIT_MED_RATE_TRIG_SEL_8822C(v))
+
+#define BIT_SHIFT_LOW_RATE_TRIG_SEL_8822C 16
+#define BIT_MASK_LOW_RATE_TRIG_SEL_8822C 0x3
+#define BIT_LOW_RATE_TRIG_SEL_8822C(x)                                         \
+	(((x) & BIT_MASK_LOW_RATE_TRIG_SEL_8822C)                              \
+	 << BIT_SHIFT_LOW_RATE_TRIG_SEL_8822C)
+#define BITS_LOW_RATE_TRIG_SEL_8822C                                           \
+	(BIT_MASK_LOW_RATE_TRIG_SEL_8822C << BIT_SHIFT_LOW_RATE_TRIG_SEL_8822C)
+#define BIT_CLEAR_LOW_RATE_TRIG_SEL_8822C(x)                                   \
+	((x) & (~BITS_LOW_RATE_TRIG_SEL_8822C))
+#define BIT_GET_LOW_RATE_TRIG_SEL_8822C(x)                                     \
+	(((x) >> BIT_SHIFT_LOW_RATE_TRIG_SEL_8822C) &                          \
+	 BIT_MASK_LOW_RATE_TRIG_SEL_8822C)
+#define BIT_SET_LOW_RATE_TRIG_SEL_8822C(x, v)                                  \
+	(BIT_CLEAR_LOW_RATE_TRIG_SEL_8822C(x) | BIT_LOW_RATE_TRIG_SEL_8822C(v))
+
+#define BIT_SHIFT_HIGH_RATE_BD_IDX_8822C 8
+#define BIT_MASK_HIGH_RATE_BD_IDX_8822C 0x7f
+#define BIT_HIGH_RATE_BD_IDX_8822C(x)                                          \
+	(((x) & BIT_MASK_HIGH_RATE_BD_IDX_8822C)                               \
+	 << BIT_SHIFT_HIGH_RATE_BD_IDX_8822C)
+#define BITS_HIGH_RATE_BD_IDX_8822C                                            \
+	(BIT_MASK_HIGH_RATE_BD_IDX_8822C << BIT_SHIFT_HIGH_RATE_BD_IDX_8822C)
+#define BIT_CLEAR_HIGH_RATE_BD_IDX_8822C(x)                                    \
+	((x) & (~BITS_HIGH_RATE_BD_IDX_8822C))
+#define BIT_GET_HIGH_RATE_BD_IDX_8822C(x)                                      \
+	(((x) >> BIT_SHIFT_HIGH_RATE_BD_IDX_8822C) &                           \
+	 BIT_MASK_HIGH_RATE_BD_IDX_8822C)
+#define BIT_SET_HIGH_RATE_BD_IDX_8822C(x, v)                                   \
+	(BIT_CLEAR_HIGH_RATE_BD_IDX_8822C(x) | BIT_HIGH_RATE_BD_IDX_8822C(v))
+
+#define BIT_SHIFT_LOW_RATE_BD_IDX_8822C 0
+#define BIT_MASK_LOW_RATE_BD_IDX_8822C 0x7f
+#define BIT_LOW_RATE_BD_IDX_8822C(x)                                           \
+	(((x) & BIT_MASK_LOW_RATE_BD_IDX_8822C)                                \
+	 << BIT_SHIFT_LOW_RATE_BD_IDX_8822C)
+#define BITS_LOW_RATE_BD_IDX_8822C                                             \
+	(BIT_MASK_LOW_RATE_BD_IDX_8822C << BIT_SHIFT_LOW_RATE_BD_IDX_8822C)
+#define BIT_CLEAR_LOW_RATE_BD_IDX_8822C(x) ((x) & (~BITS_LOW_RATE_BD_IDX_8822C))
+#define BIT_GET_LOW_RATE_BD_IDX_8822C(x)                                       \
+	(((x) >> BIT_SHIFT_LOW_RATE_BD_IDX_8822C) &                            \
+	 BIT_MASK_LOW_RATE_BD_IDX_8822C)
+#define BIT_SET_LOW_RATE_BD_IDX_8822C(x, v)                                    \
+	(BIT_CLEAR_LOW_RATE_BD_IDX_8822C(x) | BIT_LOW_RATE_BD_IDX_8822C(v))
+
+/* 2 REG_LTR_CTRL2_TIMER_THRESHOLD_8822C */
+
+#define BIT_SHIFT_RX_EMPTY_TIMER_IDX_8822C 24
+#define BIT_MASK_RX_EMPTY_TIMER_IDX_8822C 0x7
+#define BIT_RX_EMPTY_TIMER_IDX_8822C(x)                                        \
+	(((x) & BIT_MASK_RX_EMPTY_TIMER_IDX_8822C)                             \
+	 << BIT_SHIFT_RX_EMPTY_TIMER_IDX_8822C)
+#define BITS_RX_EMPTY_TIMER_IDX_8822C                                          \
+	(BIT_MASK_RX_EMPTY_TIMER_IDX_8822C                                     \
+	 << BIT_SHIFT_RX_EMPTY_TIMER_IDX_8822C)
+#define BIT_CLEAR_RX_EMPTY_TIMER_IDX_8822C(x)                                  \
+	((x) & (~BITS_RX_EMPTY_TIMER_IDX_8822C))
+#define BIT_GET_RX_EMPTY_TIMER_IDX_8822C(x)                                    \
+	(((x) >> BIT_SHIFT_RX_EMPTY_TIMER_IDX_8822C) &                         \
+	 BIT_MASK_RX_EMPTY_TIMER_IDX_8822C)
+#define BIT_SET_RX_EMPTY_TIMER_IDX_8822C(x, v)                                 \
+	(BIT_CLEAR_RX_EMPTY_TIMER_IDX_8822C(x) |                               \
+	 BIT_RX_EMPTY_TIMER_IDX_8822C(v))
+
+#define BIT_SHIFT_RX_AFULL_TH_IDX_8822C 20
+#define BIT_MASK_RX_AFULL_TH_IDX_8822C 0x7
+#define BIT_RX_AFULL_TH_IDX_8822C(x)                                           \
+	(((x) & BIT_MASK_RX_AFULL_TH_IDX_8822C)                                \
+	 << BIT_SHIFT_RX_AFULL_TH_IDX_8822C)
+#define BITS_RX_AFULL_TH_IDX_8822C                                             \
+	(BIT_MASK_RX_AFULL_TH_IDX_8822C << BIT_SHIFT_RX_AFULL_TH_IDX_8822C)
+#define BIT_CLEAR_RX_AFULL_TH_IDX_8822C(x) ((x) & (~BITS_RX_AFULL_TH_IDX_8822C))
+#define BIT_GET_RX_AFULL_TH_IDX_8822C(x)                                       \
+	(((x) >> BIT_SHIFT_RX_AFULL_TH_IDX_8822C) &                            \
+	 BIT_MASK_RX_AFULL_TH_IDX_8822C)
+#define BIT_SET_RX_AFULL_TH_IDX_8822C(x, v)                                    \
+	(BIT_CLEAR_RX_AFULL_TH_IDX_8822C(x) | BIT_RX_AFULL_TH_IDX_8822C(v))
+
+#define BIT_SHIFT_RX_HIGH_TH_IDX_8822C 16
+#define BIT_MASK_RX_HIGH_TH_IDX_8822C 0x7
+#define BIT_RX_HIGH_TH_IDX_8822C(x)                                            \
+	(((x) & BIT_MASK_RX_HIGH_TH_IDX_8822C)                                 \
+	 << BIT_SHIFT_RX_HIGH_TH_IDX_8822C)
+#define BITS_RX_HIGH_TH_IDX_8822C                                              \
+	(BIT_MASK_RX_HIGH_TH_IDX_8822C << BIT_SHIFT_RX_HIGH_TH_IDX_8822C)
+#define BIT_CLEAR_RX_HIGH_TH_IDX_8822C(x) ((x) & (~BITS_RX_HIGH_TH_IDX_8822C))
+#define BIT_GET_RX_HIGH_TH_IDX_8822C(x)                                        \
+	(((x) >> BIT_SHIFT_RX_HIGH_TH_IDX_8822C) &                             \
+	 BIT_MASK_RX_HIGH_TH_IDX_8822C)
+#define BIT_SET_RX_HIGH_TH_IDX_8822C(x, v)                                     \
+	(BIT_CLEAR_RX_HIGH_TH_IDX_8822C(x) | BIT_RX_HIGH_TH_IDX_8822C(v))
+
+#define BIT_SHIFT_RX_MED_TH_IDX_8822C 12
+#define BIT_MASK_RX_MED_TH_IDX_8822C 0x7
+#define BIT_RX_MED_TH_IDX_8822C(x)                                             \
+	(((x) & BIT_MASK_RX_MED_TH_IDX_8822C) << BIT_SHIFT_RX_MED_TH_IDX_8822C)
+#define BITS_RX_MED_TH_IDX_8822C                                               \
+	(BIT_MASK_RX_MED_TH_IDX_8822C << BIT_SHIFT_RX_MED_TH_IDX_8822C)
+#define BIT_CLEAR_RX_MED_TH_IDX_8822C(x) ((x) & (~BITS_RX_MED_TH_IDX_8822C))
+#define BIT_GET_RX_MED_TH_IDX_8822C(x)                                         \
+	(((x) >> BIT_SHIFT_RX_MED_TH_IDX_8822C) & BIT_MASK_RX_MED_TH_IDX_8822C)
+#define BIT_SET_RX_MED_TH_IDX_8822C(x, v)                                      \
+	(BIT_CLEAR_RX_MED_TH_IDX_8822C(x) | BIT_RX_MED_TH_IDX_8822C(v))
+
+#define BIT_SHIFT_RX_LOW_TH_IDX_8822C 8
+#define BIT_MASK_RX_LOW_TH_IDX_8822C 0x7
+#define BIT_RX_LOW_TH_IDX_8822C(x)                                             \
+	(((x) & BIT_MASK_RX_LOW_TH_IDX_8822C) << BIT_SHIFT_RX_LOW_TH_IDX_8822C)
+#define BITS_RX_LOW_TH_IDX_8822C                                               \
+	(BIT_MASK_RX_LOW_TH_IDX_8822C << BIT_SHIFT_RX_LOW_TH_IDX_8822C)
+#define BIT_CLEAR_RX_LOW_TH_IDX_8822C(x) ((x) & (~BITS_RX_LOW_TH_IDX_8822C))
+#define BIT_GET_RX_LOW_TH_IDX_8822C(x)                                         \
+	(((x) >> BIT_SHIFT_RX_LOW_TH_IDX_8822C) & BIT_MASK_RX_LOW_TH_IDX_8822C)
+#define BIT_SET_RX_LOW_TH_IDX_8822C(x, v)                                      \
+	(BIT_CLEAR_RX_LOW_TH_IDX_8822C(x) | BIT_RX_LOW_TH_IDX_8822C(v))
+
+#define BIT_SHIFT_LTR_SPACE_IDX_8822C 4
+#define BIT_MASK_LTR_SPACE_IDX_8822C 0x3
+#define BIT_LTR_SPACE_IDX_8822C(x)                                             \
+	(((x) & BIT_MASK_LTR_SPACE_IDX_8822C) << BIT_SHIFT_LTR_SPACE_IDX_8822C)
+#define BITS_LTR_SPACE_IDX_8822C                                               \
+	(BIT_MASK_LTR_SPACE_IDX_8822C << BIT_SHIFT_LTR_SPACE_IDX_8822C)
+#define BIT_CLEAR_LTR_SPACE_IDX_8822C(x) ((x) & (~BITS_LTR_SPACE_IDX_8822C))
+#define BIT_GET_LTR_SPACE_IDX_8822C(x)                                         \
+	(((x) >> BIT_SHIFT_LTR_SPACE_IDX_8822C) & BIT_MASK_LTR_SPACE_IDX_8822C)
+#define BIT_SET_LTR_SPACE_IDX_8822C(x, v)                                      \
+	(BIT_CLEAR_LTR_SPACE_IDX_8822C(x) | BIT_LTR_SPACE_IDX_8822C(v))
+
+#define BIT_SHIFT_LTR_IDLE_TIMER_IDX_8822C 0
+#define BIT_MASK_LTR_IDLE_TIMER_IDX_8822C 0x7
+#define BIT_LTR_IDLE_TIMER_IDX_8822C(x)                                        \
+	(((x) & BIT_MASK_LTR_IDLE_TIMER_IDX_8822C)                             \
+	 << BIT_SHIFT_LTR_IDLE_TIMER_IDX_8822C)
+#define BITS_LTR_IDLE_TIMER_IDX_8822C                                          \
+	(BIT_MASK_LTR_IDLE_TIMER_IDX_8822C                                     \
+	 << BIT_SHIFT_LTR_IDLE_TIMER_IDX_8822C)
+#define BIT_CLEAR_LTR_IDLE_TIMER_IDX_8822C(x)                                  \
+	((x) & (~BITS_LTR_IDLE_TIMER_IDX_8822C))
+#define BIT_GET_LTR_IDLE_TIMER_IDX_8822C(x)                                    \
+	(((x) >> BIT_SHIFT_LTR_IDLE_TIMER_IDX_8822C) &                         \
+	 BIT_MASK_LTR_IDLE_TIMER_IDX_8822C)
+#define BIT_SET_LTR_IDLE_TIMER_IDX_8822C(x, v)                                 \
+	(BIT_CLEAR_LTR_IDLE_TIMER_IDX_8822C(x) |                               \
+	 BIT_LTR_IDLE_TIMER_IDX_8822C(v))
+
+/* 2 REG_LTR_IDLE_LATENCY_V1_8822C */
+
+#define BIT_SHIFT_LTR_IDLE_L_8822C 0
+#define BIT_MASK_LTR_IDLE_L_8822C 0xffffffffL
+#define BIT_LTR_IDLE_L_8822C(x)                                                \
+	(((x) & BIT_MASK_LTR_IDLE_L_8822C) << BIT_SHIFT_LTR_IDLE_L_8822C)
+#define BITS_LTR_IDLE_L_8822C                                                  \
+	(BIT_MASK_LTR_IDLE_L_8822C << BIT_SHIFT_LTR_IDLE_L_8822C)
+#define BIT_CLEAR_LTR_IDLE_L_8822C(x) ((x) & (~BITS_LTR_IDLE_L_8822C))
+#define BIT_GET_LTR_IDLE_L_8822C(x)                                            \
+	(((x) >> BIT_SHIFT_LTR_IDLE_L_8822C) & BIT_MASK_LTR_IDLE_L_8822C)
+#define BIT_SET_LTR_IDLE_L_8822C(x, v)                                         \
+	(BIT_CLEAR_LTR_IDLE_L_8822C(x) | BIT_LTR_IDLE_L_8822C(v))
+
+/* 2 REG_LTR_ACTIVE_LATENCY_V1_8822C */
+
+#define BIT_SHIFT_LTR_ACT_L_8822C 0
+#define BIT_MASK_LTR_ACT_L_8822C 0xffffffffL
+#define BIT_LTR_ACT_L_8822C(x)                                                 \
+	(((x) & BIT_MASK_LTR_ACT_L_8822C) << BIT_SHIFT_LTR_ACT_L_8822C)
+#define BITS_LTR_ACT_L_8822C                                                   \
+	(BIT_MASK_LTR_ACT_L_8822C << BIT_SHIFT_LTR_ACT_L_8822C)
+#define BIT_CLEAR_LTR_ACT_L_8822C(x) ((x) & (~BITS_LTR_ACT_L_8822C))
+#define BIT_GET_LTR_ACT_L_8822C(x)                                             \
+	(((x) >> BIT_SHIFT_LTR_ACT_L_8822C) & BIT_MASK_LTR_ACT_L_8822C)
+#define BIT_SET_LTR_ACT_L_8822C(x, v)                                          \
+	(BIT_CLEAR_LTR_ACT_L_8822C(x) | BIT_LTR_ACT_L_8822C(v))
+
+/* 2 REG_ANTENNA_TRAINING_CONTROL_REGISTER_8822C */
+
+#define BIT_SHIFT_TRAIN_STA_ADDR_0_8822C 0
+#define BIT_MASK_TRAIN_STA_ADDR_0_8822C 0xffffffffL
+#define BIT_TRAIN_STA_ADDR_0_8822C(x)                                          \
+	(((x) & BIT_MASK_TRAIN_STA_ADDR_0_8822C)                               \
+	 << BIT_SHIFT_TRAIN_STA_ADDR_0_8822C)
+#define BITS_TRAIN_STA_ADDR_0_8822C                                            \
+	(BIT_MASK_TRAIN_STA_ADDR_0_8822C << BIT_SHIFT_TRAIN_STA_ADDR_0_8822C)
+#define BIT_CLEAR_TRAIN_STA_ADDR_0_8822C(x)                                    \
+	((x) & (~BITS_TRAIN_STA_ADDR_0_8822C))
+#define BIT_GET_TRAIN_STA_ADDR_0_8822C(x)                                      \
+	(((x) >> BIT_SHIFT_TRAIN_STA_ADDR_0_8822C) &                           \
+	 BIT_MASK_TRAIN_STA_ADDR_0_8822C)
+#define BIT_SET_TRAIN_STA_ADDR_0_8822C(x, v)                                   \
+	(BIT_CLEAR_TRAIN_STA_ADDR_0_8822C(x) | BIT_TRAIN_STA_ADDR_0_8822C(v))
+
+/* 2 REG_ANTENNA_TRAINING_CONTROL_REGISTER_1_8822C */
+#define BIT_ANTTRN_SWITCH_8822C BIT(19)
+#define BIT_APPEND_MACID_IN_RESP_EN_1_8822C BIT(18)
+#define BIT_ADDR2_MATCH_EN_1_8822C BIT(17)
+#define BIT_ANTTRN_EN_1_8822C BIT(16)
+
+#define BIT_SHIFT_TRAIN_STA_ADDR_1_8822C 0
+#define BIT_MASK_TRAIN_STA_ADDR_1_8822C 0xffff
+#define BIT_TRAIN_STA_ADDR_1_8822C(x)                                          \
+	(((x) & BIT_MASK_TRAIN_STA_ADDR_1_8822C)                               \
+	 << BIT_SHIFT_TRAIN_STA_ADDR_1_8822C)
+#define BITS_TRAIN_STA_ADDR_1_8822C                                            \
+	(BIT_MASK_TRAIN_STA_ADDR_1_8822C << BIT_SHIFT_TRAIN_STA_ADDR_1_8822C)
+#define BIT_CLEAR_TRAIN_STA_ADDR_1_8822C(x)                                    \
+	((x) & (~BITS_TRAIN_STA_ADDR_1_8822C))
+#define BIT_GET_TRAIN_STA_ADDR_1_8822C(x)                                      \
+	(((x) >> BIT_SHIFT_TRAIN_STA_ADDR_1_8822C) &                           \
+	 BIT_MASK_TRAIN_STA_ADDR_1_8822C)
+#define BIT_SET_TRAIN_STA_ADDR_1_8822C(x, v)                                   \
+	(BIT_CLEAR_TRAIN_STA_ADDR_1_8822C(x) | BIT_TRAIN_STA_ADDR_1_8822C(v))
+
+/* 2 REG_WMAC_PKTCNT_RWD_8822C */
+
+#define BIT_SHIFT_PKTCNT_BSSIDMAP_8822C 4
+#define BIT_MASK_PKTCNT_BSSIDMAP_8822C 0xf
+#define BIT_PKTCNT_BSSIDMAP_8822C(x)                                           \
+	(((x) & BIT_MASK_PKTCNT_BSSIDMAP_8822C)                                \
+	 << BIT_SHIFT_PKTCNT_BSSIDMAP_8822C)
+#define BITS_PKTCNT_BSSIDMAP_8822C                                             \
+	(BIT_MASK_PKTCNT_BSSIDMAP_8822C << BIT_SHIFT_PKTCNT_BSSIDMAP_8822C)
+#define BIT_CLEAR_PKTCNT_BSSIDMAP_8822C(x) ((x) & (~BITS_PKTCNT_BSSIDMAP_8822C))
+#define BIT_GET_PKTCNT_BSSIDMAP_8822C(x)                                       \
+	(((x) >> BIT_SHIFT_PKTCNT_BSSIDMAP_8822C) &                            \
+	 BIT_MASK_PKTCNT_BSSIDMAP_8822C)
+#define BIT_SET_PKTCNT_BSSIDMAP_8822C(x, v)                                    \
+	(BIT_CLEAR_PKTCNT_BSSIDMAP_8822C(x) | BIT_PKTCNT_BSSIDMAP_8822C(v))
+
+#define BIT_PKTCNT_CNTRST_8822C BIT(1)
+#define BIT_PKTCNT_CNTEN_8822C BIT(0)
+
+/* 2 REG_WMAC_PKTCNT_CTRL_8822C */
+#define BIT_WMAC_PKTCNT_TRST_8822C BIT(9)
+#define BIT_WMAC_PKTCNT_FEN_8822C BIT(8)
+
+#define BIT_SHIFT_WMAC_PKTCNT_CFGAD_8822C 0
+#define BIT_MASK_WMAC_PKTCNT_CFGAD_8822C 0xff
+#define BIT_WMAC_PKTCNT_CFGAD_8822C(x)                                         \
+	(((x) & BIT_MASK_WMAC_PKTCNT_CFGAD_8822C)                              \
+	 << BIT_SHIFT_WMAC_PKTCNT_CFGAD_8822C)
+#define BITS_WMAC_PKTCNT_CFGAD_8822C                                           \
+	(BIT_MASK_WMAC_PKTCNT_CFGAD_8822C << BIT_SHIFT_WMAC_PKTCNT_CFGAD_8822C)
+#define BIT_CLEAR_WMAC_PKTCNT_CFGAD_8822C(x)                                   \
+	((x) & (~BITS_WMAC_PKTCNT_CFGAD_8822C))
+#define BIT_GET_WMAC_PKTCNT_CFGAD_8822C(x)                                     \
+	(((x) >> BIT_SHIFT_WMAC_PKTCNT_CFGAD_8822C) &                          \
+	 BIT_MASK_WMAC_PKTCNT_CFGAD_8822C)
+#define BIT_SET_WMAC_PKTCNT_CFGAD_8822C(x, v)                                  \
+	(BIT_CLEAR_WMAC_PKTCNT_CFGAD_8822C(x) | BIT_WMAC_PKTCNT_CFGAD_8822C(v))
+
+/* 2 REG_IQ_DUMP_8822C */
+
+#define BIT_SHIFT_DUMP_OK_ADDR_8822C 16
+#define BIT_MASK_DUMP_OK_ADDR_8822C 0xffff
+#define BIT_DUMP_OK_ADDR_8822C(x)                                              \
+	(((x) & BIT_MASK_DUMP_OK_ADDR_8822C) << BIT_SHIFT_DUMP_OK_ADDR_8822C)
+#define BITS_DUMP_OK_ADDR_8822C                                                \
+	(BIT_MASK_DUMP_OK_ADDR_8822C << BIT_SHIFT_DUMP_OK_ADDR_8822C)
+#define BIT_CLEAR_DUMP_OK_ADDR_8822C(x) ((x) & (~BITS_DUMP_OK_ADDR_8822C))
+#define BIT_GET_DUMP_OK_ADDR_8822C(x)                                          \
+	(((x) >> BIT_SHIFT_DUMP_OK_ADDR_8822C) & BIT_MASK_DUMP_OK_ADDR_8822C)
+#define BIT_SET_DUMP_OK_ADDR_8822C(x, v)                                       \
+	(BIT_CLEAR_DUMP_OK_ADDR_8822C(x) | BIT_DUMP_OK_ADDR_8822C(v))
+
+#define BIT_MACDBG_TRIG_IQDUMP_8822C BIT(15)
+
+#define BIT_SHIFT_R_TRIG_TIME_SEL_8822C 8
+#define BIT_MASK_R_TRIG_TIME_SEL_8822C 0x7f
+#define BIT_R_TRIG_TIME_SEL_8822C(x)                                           \
+	(((x) & BIT_MASK_R_TRIG_TIME_SEL_8822C)                                \
+	 << BIT_SHIFT_R_TRIG_TIME_SEL_8822C)
+#define BITS_R_TRIG_TIME_SEL_8822C                                             \
+	(BIT_MASK_R_TRIG_TIME_SEL_8822C << BIT_SHIFT_R_TRIG_TIME_SEL_8822C)
+#define BIT_CLEAR_R_TRIG_TIME_SEL_8822C(x) ((x) & (~BITS_R_TRIG_TIME_SEL_8822C))
+#define BIT_GET_R_TRIG_TIME_SEL_8822C(x)                                       \
+	(((x) >> BIT_SHIFT_R_TRIG_TIME_SEL_8822C) &                            \
+	 BIT_MASK_R_TRIG_TIME_SEL_8822C)
+#define BIT_SET_R_TRIG_TIME_SEL_8822C(x, v)                                    \
+	(BIT_CLEAR_R_TRIG_TIME_SEL_8822C(x) | BIT_R_TRIG_TIME_SEL_8822C(v))
+
+#define BIT_SHIFT_R_MAC_TRIG_SEL_8822C 6
+#define BIT_MASK_R_MAC_TRIG_SEL_8822C 0x3
+#define BIT_R_MAC_TRIG_SEL_8822C(x)                                            \
+	(((x) & BIT_MASK_R_MAC_TRIG_SEL_8822C)                                 \
+	 << BIT_SHIFT_R_MAC_TRIG_SEL_8822C)
+#define BITS_R_MAC_TRIG_SEL_8822C                                              \
+	(BIT_MASK_R_MAC_TRIG_SEL_8822C << BIT_SHIFT_R_MAC_TRIG_SEL_8822C)
+#define BIT_CLEAR_R_MAC_TRIG_SEL_8822C(x) ((x) & (~BITS_R_MAC_TRIG_SEL_8822C))
+#define BIT_GET_R_MAC_TRIG_SEL_8822C(x)                                        \
+	(((x) >> BIT_SHIFT_R_MAC_TRIG_SEL_8822C) &                             \
+	 BIT_MASK_R_MAC_TRIG_SEL_8822C)
+#define BIT_SET_R_MAC_TRIG_SEL_8822C(x, v)                                     \
+	(BIT_CLEAR_R_MAC_TRIG_SEL_8822C(x) | BIT_R_MAC_TRIG_SEL_8822C(v))
+
+#define BIT_MAC_TRIG_REG_8822C BIT(5)
+
+#define BIT_SHIFT_R_LEVEL_PULSE_SEL_8822C 3
+#define BIT_MASK_R_LEVEL_PULSE_SEL_8822C 0x3
+#define BIT_R_LEVEL_PULSE_SEL_8822C(x)                                         \
+	(((x) & BIT_MASK_R_LEVEL_PULSE_SEL_8822C)                              \
+	 << BIT_SHIFT_R_LEVEL_PULSE_SEL_8822C)
+#define BITS_R_LEVEL_PULSE_SEL_8822C                                           \
+	(BIT_MASK_R_LEVEL_PULSE_SEL_8822C << BIT_SHIFT_R_LEVEL_PULSE_SEL_8822C)
+#define BIT_CLEAR_R_LEVEL_PULSE_SEL_8822C(x)                                   \
+	((x) & (~BITS_R_LEVEL_PULSE_SEL_8822C))
+#define BIT_GET_R_LEVEL_PULSE_SEL_8822C(x)                                     \
+	(((x) >> BIT_SHIFT_R_LEVEL_PULSE_SEL_8822C) &                          \
+	 BIT_MASK_R_LEVEL_PULSE_SEL_8822C)
+#define BIT_SET_R_LEVEL_PULSE_SEL_8822C(x, v)                                  \
+	(BIT_CLEAR_R_LEVEL_PULSE_SEL_8822C(x) | BIT_R_LEVEL_PULSE_SEL_8822C(v))
+
+#define BIT_EN_LA_MAC_8822C BIT(2)
+#define BIT_R_EN_IQDUMP_8822C BIT(1)
+#define BIT_R_IQDATA_DUMP_8822C BIT(0)
+
+/* 2 REG_IQ_DUMP_1_8822C */
+
+#define BIT_SHIFT_R_WMAC_MASK_LA_MAC_1_8822C 0
+#define BIT_MASK_R_WMAC_MASK_LA_MAC_1_8822C 0xffffffffL
+#define BIT_R_WMAC_MASK_LA_MAC_1_8822C(x)                                      \
+	(((x) & BIT_MASK_R_WMAC_MASK_LA_MAC_1_8822C)                           \
+	 << BIT_SHIFT_R_WMAC_MASK_LA_MAC_1_8822C)
+#define BITS_R_WMAC_MASK_LA_MAC_1_8822C                                        \
+	(BIT_MASK_R_WMAC_MASK_LA_MAC_1_8822C                                   \
+	 << BIT_SHIFT_R_WMAC_MASK_LA_MAC_1_8822C)
+#define BIT_CLEAR_R_WMAC_MASK_LA_MAC_1_8822C(x)                                \
+	((x) & (~BITS_R_WMAC_MASK_LA_MAC_1_8822C))
+#define BIT_GET_R_WMAC_MASK_LA_MAC_1_8822C(x)                                  \
+	(((x) >> BIT_SHIFT_R_WMAC_MASK_LA_MAC_1_8822C) &                       \
+	 BIT_MASK_R_WMAC_MASK_LA_MAC_1_8822C)
+#define BIT_SET_R_WMAC_MASK_LA_MAC_1_8822C(x, v)                               \
+	(BIT_CLEAR_R_WMAC_MASK_LA_MAC_1_8822C(x) |                             \
+	 BIT_R_WMAC_MASK_LA_MAC_1_8822C(v))
+
+/* 2 REG_IQ_DUMP_2_8822C */
+
+#define BIT_SHIFT_R_WMAC_MATCH_REF_MAC_2_8822C 0
+#define BIT_MASK_R_WMAC_MATCH_REF_MAC_2_8822C 0xffffffffL
+#define BIT_R_WMAC_MATCH_REF_MAC_2_8822C(x)                                    \
+	(((x) & BIT_MASK_R_WMAC_MATCH_REF_MAC_2_8822C)                         \
+	 << BIT_SHIFT_R_WMAC_MATCH_REF_MAC_2_8822C)
+#define BITS_R_WMAC_MATCH_REF_MAC_2_8822C                                      \
+	(BIT_MASK_R_WMAC_MATCH_REF_MAC_2_8822C                                 \
+	 << BIT_SHIFT_R_WMAC_MATCH_REF_MAC_2_8822C)
+#define BIT_CLEAR_R_WMAC_MATCH_REF_MAC_2_8822C(x)                              \
+	((x) & (~BITS_R_WMAC_MATCH_REF_MAC_2_8822C))
+#define BIT_GET_R_WMAC_MATCH_REF_MAC_2_8822C(x)                                \
+	(((x) >> BIT_SHIFT_R_WMAC_MATCH_REF_MAC_2_8822C) &                     \
+	 BIT_MASK_R_WMAC_MATCH_REF_MAC_2_8822C)
+#define BIT_SET_R_WMAC_MATCH_REF_MAC_2_8822C(x, v)                             \
+	(BIT_CLEAR_R_WMAC_MATCH_REF_MAC_2_8822C(x) |                           \
+	 BIT_R_WMAC_MATCH_REF_MAC_2_8822C(v))
+
+/* 2 REG_WMAC_FTM_CTL_8822C */
+#define BIT_RXFTM_TXACK_SC_8822C BIT(6)
+#define BIT_RXFTM_TXACK_BW_8822C BIT(5)
+#define BIT_RXFTM_EN_8822C BIT(3)
+#define BIT_RXFTMREQ_BYDRV_8822C BIT(2)
+#define BIT_RXFTMREQ_EN_8822C BIT(1)
+#define BIT_FTM_EN_8822C BIT(0)
+
+/* 2 REG_WMAC_IQ_MDPK_FUNC_8822C */
+
+/* 2 REG_WMAC_OPTION_FUNCTION_8822C */
+
+#define BIT_SHIFT_R_OFDM_LEN_V1_8822C 16
+#define BIT_MASK_R_OFDM_LEN_V1_8822C 0xffff
+#define BIT_R_OFDM_LEN_V1_8822C(x)                                             \
+	(((x) & BIT_MASK_R_OFDM_LEN_V1_8822C) << BIT_SHIFT_R_OFDM_LEN_V1_8822C)
+#define BITS_R_OFDM_LEN_V1_8822C                                               \
+	(BIT_MASK_R_OFDM_LEN_V1_8822C << BIT_SHIFT_R_OFDM_LEN_V1_8822C)
+#define BIT_CLEAR_R_OFDM_LEN_V1_8822C(x) ((x) & (~BITS_R_OFDM_LEN_V1_8822C))
+#define BIT_GET_R_OFDM_LEN_V1_8822C(x)                                         \
+	(((x) >> BIT_SHIFT_R_OFDM_LEN_V1_8822C) & BIT_MASK_R_OFDM_LEN_V1_8822C)
+#define BIT_SET_R_OFDM_LEN_V1_8822C(x, v)                                      \
+	(BIT_CLEAR_R_OFDM_LEN_V1_8822C(x) | BIT_R_OFDM_LEN_V1_8822C(v))
+
+#define BIT_SHIFT_R_CCK_LEN_8822C 0
+#define BIT_MASK_R_CCK_LEN_8822C 0xffff
+#define BIT_R_CCK_LEN_8822C(x)                                                 \
+	(((x) & BIT_MASK_R_CCK_LEN_8822C) << BIT_SHIFT_R_CCK_LEN_8822C)
+#define BITS_R_CCK_LEN_8822C                                                   \
+	(BIT_MASK_R_CCK_LEN_8822C << BIT_SHIFT_R_CCK_LEN_8822C)
+#define BIT_CLEAR_R_CCK_LEN_8822C(x) ((x) & (~BITS_R_CCK_LEN_8822C))
+#define BIT_GET_R_CCK_LEN_8822C(x)                                             \
+	(((x) >> BIT_SHIFT_R_CCK_LEN_8822C) & BIT_MASK_R_CCK_LEN_8822C)
+#define BIT_SET_R_CCK_LEN_8822C(x, v)                                          \
+	(BIT_CLEAR_R_CCK_LEN_8822C(x) | BIT_R_CCK_LEN_8822C(v))
+
+/* 2 REG_WMAC_OPTION_FUNCTION_1_8822C */
+
+#define BIT_SHIFT_R_WMAC_RXFIFO_FULL_TH_1_8822C 24
+#define BIT_MASK_R_WMAC_RXFIFO_FULL_TH_1_8822C 0xff
+#define BIT_R_WMAC_RXFIFO_FULL_TH_1_8822C(x)                                   \
+	(((x) & BIT_MASK_R_WMAC_RXFIFO_FULL_TH_1_8822C)                        \
+	 << BIT_SHIFT_R_WMAC_RXFIFO_FULL_TH_1_8822C)
+#define BITS_R_WMAC_RXFIFO_FULL_TH_1_8822C                                     \
+	(BIT_MASK_R_WMAC_RXFIFO_FULL_TH_1_8822C                                \
+	 << BIT_SHIFT_R_WMAC_RXFIFO_FULL_TH_1_8822C)
+#define BIT_CLEAR_R_WMAC_RXFIFO_FULL_TH_1_8822C(x)                             \
+	((x) & (~BITS_R_WMAC_RXFIFO_FULL_TH_1_8822C))
+#define BIT_GET_R_WMAC_RXFIFO_FULL_TH_1_8822C(x)                               \
+	(((x) >> BIT_SHIFT_R_WMAC_RXFIFO_FULL_TH_1_8822C) &                    \
+	 BIT_MASK_R_WMAC_RXFIFO_FULL_TH_1_8822C)
+#define BIT_SET_R_WMAC_RXFIFO_FULL_TH_1_8822C(x, v)                            \
+	(BIT_CLEAR_R_WMAC_RXFIFO_FULL_TH_1_8822C(x) |                          \
+	 BIT_R_WMAC_RXFIFO_FULL_TH_1_8822C(v))
+
+#define BIT_R_WMAC_RX_SYNCFIFO_SYNC_1_8822C BIT(23)
+#define BIT_R_WMAC_RXRST_DLY_1_8822C BIT(22)
+#define BIT_R_WMAC_SRCH_TXRPT_REF_DROP_1_8822C BIT(21)
+#define BIT_R_WMAC_SRCH_TXRPT_UA1_1_8822C BIT(20)
+#define BIT_R_WMAC_SRCH_TXRPT_TYPE_1_8822C BIT(19)
+#define BIT_R_WMAC_NDP_RST_1_8822C BIT(18)
+#define BIT_R_WMAC_POWINT_EN_1_8822C BIT(17)
+#define BIT_R_WMAC_SRCH_TXRPT_PERPKT_1_8822C BIT(16)
+#define BIT_R_WMAC_SRCH_TXRPT_MID_1_8822C BIT(15)
+#define BIT_R_WMAC_PFIN_TOEN_1_8822C BIT(14)
+#define BIT_R_WMAC_FIL_SECERR_1_8822C BIT(13)
+#define BIT_R_WMAC_FIL_CTLPKTLEN_1_8822C BIT(12)
+#define BIT_R_WMAC_FIL_FCTYPE_1_8822C BIT(11)
+#define BIT_R_WMAC_FIL_FCPROVER_1_8822C BIT(10)
+#define BIT_R_WMAC_PHYSTS_SNIF_1_8822C BIT(9)
+#define BIT_R_WMAC_PHYSTS_PLCP_1_8822C BIT(8)
+#define BIT_R_MAC_TCR_VBONF_RD_1_8822C BIT(7)
+#define BIT_R_WMAC_TCR_MPAR_NDP_1_8822C BIT(6)
+#define BIT_R_WMAC_NDP_FILTER_1_8822C BIT(5)
+#define BIT_R_WMAC_RXLEN_SEL_1_8822C BIT(4)
+#define BIT_R_WMAC_RXLEN_SEL1_1_8822C BIT(3)
+#define BIT_R_OFDM_FILTER_1_8822C BIT(2)
+#define BIT_R_WMAC_CHK_OFDM_LEN_1_8822C BIT(1)
+#define BIT_R_WMAC_CHK_CCK_LEN_1_8822C BIT(0)
+
+/* 2 REG_WMAC_OPTION_FUNCTION_2_8822C */
+
+#define BIT_SHIFT_R_WMAC_RX_FIL_LEN_2_8822C 0
+#define BIT_MASK_R_WMAC_RX_FIL_LEN_2_8822C 0xffff
+#define BIT_R_WMAC_RX_FIL_LEN_2_8822C(x)                                       \
+	(((x) & BIT_MASK_R_WMAC_RX_FIL_LEN_2_8822C)                            \
+	 << BIT_SHIFT_R_WMAC_RX_FIL_LEN_2_8822C)
+#define BITS_R_WMAC_RX_FIL_LEN_2_8822C                                         \
+	(BIT_MASK_R_WMAC_RX_FIL_LEN_2_8822C                                    \
+	 << BIT_SHIFT_R_WMAC_RX_FIL_LEN_2_8822C)
+#define BIT_CLEAR_R_WMAC_RX_FIL_LEN_2_8822C(x)                                 \
+	((x) & (~BITS_R_WMAC_RX_FIL_LEN_2_8822C))
+#define BIT_GET_R_WMAC_RX_FIL_LEN_2_8822C(x)                                   \
+	(((x) >> BIT_SHIFT_R_WMAC_RX_FIL_LEN_2_8822C) &                        \
+	 BIT_MASK_R_WMAC_RX_FIL_LEN_2_8822C)
+#define BIT_SET_R_WMAC_RX_FIL_LEN_2_8822C(x, v)                                \
+	(BIT_CLEAR_R_WMAC_RX_FIL_LEN_2_8822C(x) |                              \
+	 BIT_R_WMAC_RX_FIL_LEN_2_8822C(v))
+
+/* 2 REG_RX_FILTER_FUNCTION_8822C */
+#define BIT_RXHANG_EN_8822C BIT(15)
+#define BIT_R_WMAC_MHRDDY_LATCH_8822C BIT(14)
+#define BIT_R_WMAC_MHRDDY_CLR_8822C BIT(13)
+#define BIT_R_RXPKTCTL_FSM_BASED_MPDURDY1_8822C BIT(12)
+#define BIT_WMAC_DIS_VHT_PLCP_CHK_MU_8822C BIT(11)
+#define BIT_R_CHK_DELIMIT_LEN_8822C BIT(10)
+#define BIT_R_REAPTER_ADDR_MATCH_8822C BIT(9)
+#define BIT_R_RXPKTCTL_FSM_BASED_MPDURDY_8822C BIT(8)
+#define BIT_R_LATCH_MACHRDY_8822C BIT(7)
+#define BIT_R_WMAC_RXFIL_REND_8822C BIT(6)
+#define BIT_R_WMAC_MPDURDY_CLR_8822C BIT(5)
+#define BIT_R_WMAC_CLRRXSEC_8822C BIT(4)
+#define BIT_R_WMAC_RXFIL_RDEL_8822C BIT(3)
+#define BIT_R_WMAC_RXFIL_FCSE_8822C BIT(2)
+#define BIT_R_WMAC_RXFIL_MESH_DEL_8822C BIT(1)
+#define BIT_R_WMAC_RXFIL_MASKM_8822C BIT(0)
+
+/* 2 REG_NDP_SIG_8822C */
+
+#define BIT_SHIFT_R_WMAC_TXNDP_SIGB_8822C 0
+#define BIT_MASK_R_WMAC_TXNDP_SIGB_8822C 0x1fffff
+#define BIT_R_WMAC_TXNDP_SIGB_8822C(x)                                         \
+	(((x) & BIT_MASK_R_WMAC_TXNDP_SIGB_8822C)                              \
+	 << BIT_SHIFT_R_WMAC_TXNDP_SIGB_8822C)
+#define BITS_R_WMAC_TXNDP_SIGB_8822C                                           \
+	(BIT_MASK_R_WMAC_TXNDP_SIGB_8822C << BIT_SHIFT_R_WMAC_TXNDP_SIGB_8822C)
+#define BIT_CLEAR_R_WMAC_TXNDP_SIGB_8822C(x)                                   \
+	((x) & (~BITS_R_WMAC_TXNDP_SIGB_8822C))
+#define BIT_GET_R_WMAC_TXNDP_SIGB_8822C(x)                                     \
+	(((x) >> BIT_SHIFT_R_WMAC_TXNDP_SIGB_8822C) &                          \
+	 BIT_MASK_R_WMAC_TXNDP_SIGB_8822C)
+#define BIT_SET_R_WMAC_TXNDP_SIGB_8822C(x, v)                                  \
+	(BIT_CLEAR_R_WMAC_TXNDP_SIGB_8822C(x) | BIT_R_WMAC_TXNDP_SIGB_8822C(v))
+
+/* 2 REG_TXCMD_INFO_FOR_RSP_PKT_8822C */
+
+#define BIT_SHIFT_R_MAC_DBG_SHIFT_8822C 8
+#define BIT_MASK_R_MAC_DBG_SHIFT_8822C 0x7
+#define BIT_R_MAC_DBG_SHIFT_8822C(x)                                           \
+	(((x) & BIT_MASK_R_MAC_DBG_SHIFT_8822C)                                \
+	 << BIT_SHIFT_R_MAC_DBG_SHIFT_8822C)
+#define BITS_R_MAC_DBG_SHIFT_8822C                                             \
+	(BIT_MASK_R_MAC_DBG_SHIFT_8822C << BIT_SHIFT_R_MAC_DBG_SHIFT_8822C)
+#define BIT_CLEAR_R_MAC_DBG_SHIFT_8822C(x) ((x) & (~BITS_R_MAC_DBG_SHIFT_8822C))
+#define BIT_GET_R_MAC_DBG_SHIFT_8822C(x)                                       \
+	(((x) >> BIT_SHIFT_R_MAC_DBG_SHIFT_8822C) &                            \
+	 BIT_MASK_R_MAC_DBG_SHIFT_8822C)
+#define BIT_SET_R_MAC_DBG_SHIFT_8822C(x, v)                                    \
+	(BIT_CLEAR_R_MAC_DBG_SHIFT_8822C(x) | BIT_R_MAC_DBG_SHIFT_8822C(v))
+
+#define BIT_SHIFT_R_MAC_DBG_SEL_8822C 0
+#define BIT_MASK_R_MAC_DBG_SEL_8822C 0x3
+#define BIT_R_MAC_DBG_SEL_8822C(x)                                             \
+	(((x) & BIT_MASK_R_MAC_DBG_SEL_8822C) << BIT_SHIFT_R_MAC_DBG_SEL_8822C)
+#define BITS_R_MAC_DBG_SEL_8822C                                               \
+	(BIT_MASK_R_MAC_DBG_SEL_8822C << BIT_SHIFT_R_MAC_DBG_SEL_8822C)
+#define BIT_CLEAR_R_MAC_DBG_SEL_8822C(x) ((x) & (~BITS_R_MAC_DBG_SEL_8822C))
+#define BIT_GET_R_MAC_DBG_SEL_8822C(x)                                         \
+	(((x) >> BIT_SHIFT_R_MAC_DBG_SEL_8822C) & BIT_MASK_R_MAC_DBG_SEL_8822C)
+#define BIT_SET_R_MAC_DBG_SEL_8822C(x, v)                                      \
+	(BIT_CLEAR_R_MAC_DBG_SEL_8822C(x) | BIT_R_MAC_DBG_SEL_8822C(v))
+
+/* 2 REG_TXCMD_INFO_FOR_RSP_PKT_1_8822C */
+
+#define BIT_SHIFT_R_MAC_DEBUG_1_8822C 0
+#define BIT_MASK_R_MAC_DEBUG_1_8822C 0xffffffffL
+#define BIT_R_MAC_DEBUG_1_8822C(x)                                             \
+	(((x) & BIT_MASK_R_MAC_DEBUG_1_8822C) << BIT_SHIFT_R_MAC_DEBUG_1_8822C)
+#define BITS_R_MAC_DEBUG_1_8822C                                               \
+	(BIT_MASK_R_MAC_DEBUG_1_8822C << BIT_SHIFT_R_MAC_DEBUG_1_8822C)
+#define BIT_CLEAR_R_MAC_DEBUG_1_8822C(x) ((x) & (~BITS_R_MAC_DEBUG_1_8822C))
+#define BIT_GET_R_MAC_DEBUG_1_8822C(x)                                         \
+	(((x) >> BIT_SHIFT_R_MAC_DEBUG_1_8822C) & BIT_MASK_R_MAC_DEBUG_1_8822C)
+#define BIT_SET_R_MAC_DEBUG_1_8822C(x, v)                                      \
+	(BIT_CLEAR_R_MAC_DEBUG_1_8822C(x) | BIT_R_MAC_DEBUG_1_8822C(v))
+
+/* 2 REG_WSEC_OPTION_8822C */
+#define BIT_RXDEC_BM_MGNT_8822C BIT(22)
+#define BIT_TXENC_BM_MGNT_8822C BIT(21)
+#define BIT_RXDEC_UNI_MGNT_8822C BIT(20)
+#define BIT_TXENC_UNI_MGNT_8822C BIT(19)
+#define BIT_WMAC_SEC_MASKIV_8822C BIT(18)
+
+#define BIT_SHIFT_WMAC_SEC_PN_SEL_8822C 16
+#define BIT_MASK_WMAC_SEC_PN_SEL_8822C 0x3
+#define BIT_WMAC_SEC_PN_SEL_8822C(x)                                           \
+	(((x) & BIT_MASK_WMAC_SEC_PN_SEL_8822C)                                \
+	 << BIT_SHIFT_WMAC_SEC_PN_SEL_8822C)
+#define BITS_WMAC_SEC_PN_SEL_8822C                                             \
+	(BIT_MASK_WMAC_SEC_PN_SEL_8822C << BIT_SHIFT_WMAC_SEC_PN_SEL_8822C)
+#define BIT_CLEAR_WMAC_SEC_PN_SEL_8822C(x) ((x) & (~BITS_WMAC_SEC_PN_SEL_8822C))
+#define BIT_GET_WMAC_SEC_PN_SEL_8822C(x)                                       \
+	(((x) >> BIT_SHIFT_WMAC_SEC_PN_SEL_8822C) &                            \
+	 BIT_MASK_WMAC_SEC_PN_SEL_8822C)
+#define BIT_SET_WMAC_SEC_PN_SEL_8822C(x, v)                                    \
+	(BIT_CLEAR_WMAC_SEC_PN_SEL_8822C(x) | BIT_WMAC_SEC_PN_SEL_8822C(v))
+
+#define BIT_SHIFT_BT_TIME_CNT_8822C 0
+#define BIT_MASK_BT_TIME_CNT_8822C 0xff
+#define BIT_BT_TIME_CNT_8822C(x)                                               \
+	(((x) & BIT_MASK_BT_TIME_CNT_8822C) << BIT_SHIFT_BT_TIME_CNT_8822C)
+#define BITS_BT_TIME_CNT_8822C                                                 \
+	(BIT_MASK_BT_TIME_CNT_8822C << BIT_SHIFT_BT_TIME_CNT_8822C)
+#define BIT_CLEAR_BT_TIME_CNT_8822C(x) ((x) & (~BITS_BT_TIME_CNT_8822C))
+#define BIT_GET_BT_TIME_CNT_8822C(x)                                           \
+	(((x) >> BIT_SHIFT_BT_TIME_CNT_8822C) & BIT_MASK_BT_TIME_CNT_8822C)
+#define BIT_SET_BT_TIME_CNT_8822C(x, v)                                        \
+	(BIT_CLEAR_BT_TIME_CNT_8822C(x) | BIT_BT_TIME_CNT_8822C(v))
+
+/* 2 REG_RTS_ADDRESS_0_8822C */
+
+/* 2 REG_RTS_ADDRESS_0_1_8822C */
+
+/* 2 REG_RTS_ADDRESS_1_8822C */
+
+/* 2 REG_RTS_ADDRESS_1_1_8822C */
+
+/* 2 REG_WL2LTECOEX_INDIRECT_ACCESS_CTRL_V1_8822C */
+#define BIT_LTECOEX_ACCESS_START_V1_8822C BIT(31)
+#define BIT_LTECOEX_WRITE_MODE_V1_8822C BIT(30)
+#define BIT_LTECOEX_READY_BIT_V1_8822C BIT(29)
+
+#define BIT_SHIFT_WRITE_BYTE_EN_V1_8822C 16
+#define BIT_MASK_WRITE_BYTE_EN_V1_8822C 0xf
+#define BIT_WRITE_BYTE_EN_V1_8822C(x)                                          \
+	(((x) & BIT_MASK_WRITE_BYTE_EN_V1_8822C)                               \
+	 << BIT_SHIFT_WRITE_BYTE_EN_V1_8822C)
+#define BITS_WRITE_BYTE_EN_V1_8822C                                            \
+	(BIT_MASK_WRITE_BYTE_EN_V1_8822C << BIT_SHIFT_WRITE_BYTE_EN_V1_8822C)
+#define BIT_CLEAR_WRITE_BYTE_EN_V1_8822C(x)                                    \
+	((x) & (~BITS_WRITE_BYTE_EN_V1_8822C))
+#define BIT_GET_WRITE_BYTE_EN_V1_8822C(x)                                      \
+	(((x) >> BIT_SHIFT_WRITE_BYTE_EN_V1_8822C) &                           \
+	 BIT_MASK_WRITE_BYTE_EN_V1_8822C)
+#define BIT_SET_WRITE_BYTE_EN_V1_8822C(x, v)                                   \
+	(BIT_CLEAR_WRITE_BYTE_EN_V1_8822C(x) | BIT_WRITE_BYTE_EN_V1_8822C(v))
+
+#define BIT_SHIFT_LTECOEX_REG_ADDR_V1_8822C 0
+#define BIT_MASK_LTECOEX_REG_ADDR_V1_8822C 0xffff
+#define BIT_LTECOEX_REG_ADDR_V1_8822C(x)                                       \
+	(((x) & BIT_MASK_LTECOEX_REG_ADDR_V1_8822C)                            \
+	 << BIT_SHIFT_LTECOEX_REG_ADDR_V1_8822C)
+#define BITS_LTECOEX_REG_ADDR_V1_8822C                                         \
+	(BIT_MASK_LTECOEX_REG_ADDR_V1_8822C                                    \
+	 << BIT_SHIFT_LTECOEX_REG_ADDR_V1_8822C)
+#define BIT_CLEAR_LTECOEX_REG_ADDR_V1_8822C(x)                                 \
+	((x) & (~BITS_LTECOEX_REG_ADDR_V1_8822C))
+#define BIT_GET_LTECOEX_REG_ADDR_V1_8822C(x)                                   \
+	(((x) >> BIT_SHIFT_LTECOEX_REG_ADDR_V1_8822C) &                        \
+	 BIT_MASK_LTECOEX_REG_ADDR_V1_8822C)
+#define BIT_SET_LTECOEX_REG_ADDR_V1_8822C(x, v)                                \
+	(BIT_CLEAR_LTECOEX_REG_ADDR_V1_8822C(x) |                              \
+	 BIT_LTECOEX_REG_ADDR_V1_8822C(v))
+
+/* 2 REG_WL2LTECOEX_INDIRECT_ACCESS_WRITE_DATA_V1_8822C */
+
+#define BIT_SHIFT_LTECOEX_W_DATA_V1_8822C 0
+#define BIT_MASK_LTECOEX_W_DATA_V1_8822C 0xffffffffL
+#define BIT_LTECOEX_W_DATA_V1_8822C(x)                                         \
+	(((x) & BIT_MASK_LTECOEX_W_DATA_V1_8822C)                              \
+	 << BIT_SHIFT_LTECOEX_W_DATA_V1_8822C)
+#define BITS_LTECOEX_W_DATA_V1_8822C                                           \
+	(BIT_MASK_LTECOEX_W_DATA_V1_8822C << BIT_SHIFT_LTECOEX_W_DATA_V1_8822C)
+#define BIT_CLEAR_LTECOEX_W_DATA_V1_8822C(x)                                   \
+	((x) & (~BITS_LTECOEX_W_DATA_V1_8822C))
+#define BIT_GET_LTECOEX_W_DATA_V1_8822C(x)                                     \
+	(((x) >> BIT_SHIFT_LTECOEX_W_DATA_V1_8822C) &                          \
+	 BIT_MASK_LTECOEX_W_DATA_V1_8822C)
+#define BIT_SET_LTECOEX_W_DATA_V1_8822C(x, v)                                  \
+	(BIT_CLEAR_LTECOEX_W_DATA_V1_8822C(x) | BIT_LTECOEX_W_DATA_V1_8822C(v))
+
+/* 2 REG_WL2LTECOEX_INDIRECT_ACCESS_READ_DATA_V1_8822C */
+
+#define BIT_SHIFT_LTECOEX_R_DATA_V1_8822C 0
+#define BIT_MASK_LTECOEX_R_DATA_V1_8822C 0xffffffffL
+#define BIT_LTECOEX_R_DATA_V1_8822C(x)                                         \
+	(((x) & BIT_MASK_LTECOEX_R_DATA_V1_8822C)                              \
+	 << BIT_SHIFT_LTECOEX_R_DATA_V1_8822C)
+#define BITS_LTECOEX_R_DATA_V1_8822C                                           \
+	(BIT_MASK_LTECOEX_R_DATA_V1_8822C << BIT_SHIFT_LTECOEX_R_DATA_V1_8822C)
+#define BIT_CLEAR_LTECOEX_R_DATA_V1_8822C(x)                                   \
+	((x) & (~BITS_LTECOEX_R_DATA_V1_8822C))
+#define BIT_GET_LTECOEX_R_DATA_V1_8822C(x)                                     \
+	(((x) >> BIT_SHIFT_LTECOEX_R_DATA_V1_8822C) &                          \
+	 BIT_MASK_LTECOEX_R_DATA_V1_8822C)
+#define BIT_SET_LTECOEX_R_DATA_V1_8822C(x, v)                                  \
+	(BIT_CLEAR_LTECOEX_R_DATA_V1_8822C(x) | BIT_LTECOEX_R_DATA_V1_8822C(v))
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_SDIO_TX_CTRL_8822C */
+
+#define BIT_SHIFT_SDIO_INT_TIMEOUT_8822C 16
+#define BIT_MASK_SDIO_INT_TIMEOUT_8822C 0xffff
+#define BIT_SDIO_INT_TIMEOUT_8822C(x)                                          \
+	(((x) & BIT_MASK_SDIO_INT_TIMEOUT_8822C)                               \
+	 << BIT_SHIFT_SDIO_INT_TIMEOUT_8822C)
+#define BITS_SDIO_INT_TIMEOUT_8822C                                            \
+	(BIT_MASK_SDIO_INT_TIMEOUT_8822C << BIT_SHIFT_SDIO_INT_TIMEOUT_8822C)
+#define BIT_CLEAR_SDIO_INT_TIMEOUT_8822C(x)                                    \
+	((x) & (~BITS_SDIO_INT_TIMEOUT_8822C))
+#define BIT_GET_SDIO_INT_TIMEOUT_8822C(x)                                      \
+	(((x) >> BIT_SHIFT_SDIO_INT_TIMEOUT_8822C) &                           \
+	 BIT_MASK_SDIO_INT_TIMEOUT_8822C)
+#define BIT_SET_SDIO_INT_TIMEOUT_8822C(x, v)                                   \
+	(BIT_CLEAR_SDIO_INT_TIMEOUT_8822C(x) | BIT_SDIO_INT_TIMEOUT_8822C(v))
+
+#define BIT_IO_ERR_STATUS_8822C BIT(15)
+#define BIT_CMD53_W_MIX_8822C BIT(14)
+#define BIT_CMD53_TX_FORMAT_8822C BIT(13)
+#define BIT_CMD53_R_TIMEOUT_MASK_8822C BIT(12)
+
+#define BIT_SHIFT_CMD53_R_TIMEOUT_UNIT_8822C 10
+#define BIT_MASK_CMD53_R_TIMEOUT_UNIT_8822C 0x3
+#define BIT_CMD53_R_TIMEOUT_UNIT_8822C(x)                                      \
+	(((x) & BIT_MASK_CMD53_R_TIMEOUT_UNIT_8822C)                           \
+	 << BIT_SHIFT_CMD53_R_TIMEOUT_UNIT_8822C)
+#define BITS_CMD53_R_TIMEOUT_UNIT_8822C                                        \
+	(BIT_MASK_CMD53_R_TIMEOUT_UNIT_8822C                                   \
+	 << BIT_SHIFT_CMD53_R_TIMEOUT_UNIT_8822C)
+#define BIT_CLEAR_CMD53_R_TIMEOUT_UNIT_8822C(x)                                \
+	((x) & (~BITS_CMD53_R_TIMEOUT_UNIT_8822C))
+#define BIT_GET_CMD53_R_TIMEOUT_UNIT_8822C(x)                                  \
+	(((x) >> BIT_SHIFT_CMD53_R_TIMEOUT_UNIT_8822C) &                       \
+	 BIT_MASK_CMD53_R_TIMEOUT_UNIT_8822C)
+#define BIT_SET_CMD53_R_TIMEOUT_UNIT_8822C(x, v)                               \
+	(BIT_CLEAR_CMD53_R_TIMEOUT_UNIT_8822C(x) |                             \
+	 BIT_CMD53_R_TIMEOUT_UNIT_8822C(v))
+
+#define BIT_REPLY_ERRCRC_IN_DATA_8822C BIT(9)
+#define BIT_EN_CMD53_OVERLAP_8822C BIT(8)
+#define BIT_REPLY_ERR_IN_R5_8822C BIT(7)
+#define BIT_R18A_EN_8822C BIT(6)
+#define BIT_SDIO_CMD_FORCE_VLD_8822C BIT(5)
+#define BIT_INIT_CMD_EN_8822C BIT(4)
+#define BIT_RXINT_READ_MASK_DIS_8822C BIT(3)
+#define BIT_EN_RXDMA_MASK_INT_8822C BIT(2)
+#define BIT_EN_MASK_TIMER_8822C BIT(1)
+#define BIT_CMD_ERR_STOP_INT_EN_8822C BIT(0)
+
+/* 2 REG_SDIO_CMD11_VOL_SWITCH_8822C */
+
+#define BIT_SHIFT_CMD11_SEQ_END_DELAY_8822C 4
+#define BIT_MASK_CMD11_SEQ_END_DELAY_8822C 0xf
+#define BIT_CMD11_SEQ_END_DELAY_8822C(x)                                       \
+	(((x) & BIT_MASK_CMD11_SEQ_END_DELAY_8822C)                            \
+	 << BIT_SHIFT_CMD11_SEQ_END_DELAY_8822C)
+#define BITS_CMD11_SEQ_END_DELAY_8822C                                         \
+	(BIT_MASK_CMD11_SEQ_END_DELAY_8822C                                    \
+	 << BIT_SHIFT_CMD11_SEQ_END_DELAY_8822C)
+#define BIT_CLEAR_CMD11_SEQ_END_DELAY_8822C(x)                                 \
+	((x) & (~BITS_CMD11_SEQ_END_DELAY_8822C))
+#define BIT_GET_CMD11_SEQ_END_DELAY_8822C(x)                                   \
+	(((x) >> BIT_SHIFT_CMD11_SEQ_END_DELAY_8822C) &                        \
+	 BIT_MASK_CMD11_SEQ_END_DELAY_8822C)
+#define BIT_SET_CMD11_SEQ_END_DELAY_8822C(x, v)                                \
+	(BIT_CLEAR_CMD11_SEQ_END_DELAY_8822C(x) |                              \
+	 BIT_CMD11_SEQ_END_DELAY_8822C(v))
+
+#define BIT_SHIFT_CMD11_SEQ_SAMPLE_INTERVAL_8822C 1
+#define BIT_MASK_CMD11_SEQ_SAMPLE_INTERVAL_8822C 0x7
+#define BIT_CMD11_SEQ_SAMPLE_INTERVAL_8822C(x)                                 \
+	(((x) & BIT_MASK_CMD11_SEQ_SAMPLE_INTERVAL_8822C)                      \
+	 << BIT_SHIFT_CMD11_SEQ_SAMPLE_INTERVAL_8822C)
+#define BITS_CMD11_SEQ_SAMPLE_INTERVAL_8822C                                   \
+	(BIT_MASK_CMD11_SEQ_SAMPLE_INTERVAL_8822C                              \
+	 << BIT_SHIFT_CMD11_SEQ_SAMPLE_INTERVAL_8822C)
+#define BIT_CLEAR_CMD11_SEQ_SAMPLE_INTERVAL_8822C(x)                           \
+	((x) & (~BITS_CMD11_SEQ_SAMPLE_INTERVAL_8822C))
+#define BIT_GET_CMD11_SEQ_SAMPLE_INTERVAL_8822C(x)                             \
+	(((x) >> BIT_SHIFT_CMD11_SEQ_SAMPLE_INTERVAL_8822C) &                  \
+	 BIT_MASK_CMD11_SEQ_SAMPLE_INTERVAL_8822C)
+#define BIT_SET_CMD11_SEQ_SAMPLE_INTERVAL_8822C(x, v)                          \
+	(BIT_CLEAR_CMD11_SEQ_SAMPLE_INTERVAL_8822C(x) |                        \
+	 BIT_CMD11_SEQ_SAMPLE_INTERVAL_8822C(v))
+
+#define BIT_CMD11_SEQ_EN_8822C BIT(0)
+
+/* 2 REG_SDIO_CTRL_8822C */
+#define BIT_SIG_OUT_PH_8822C BIT(0)
+
+/* 2 REG_SDIO_DRIVING_8822C */
+
+#define BIT_SHIFT_SDIO_DRV_TYPE_D_8822C 12
+#define BIT_MASK_SDIO_DRV_TYPE_D_8822C 0xf
+#define BIT_SDIO_DRV_TYPE_D_8822C(x)                                           \
+	(((x) & BIT_MASK_SDIO_DRV_TYPE_D_8822C)                                \
+	 << BIT_SHIFT_SDIO_DRV_TYPE_D_8822C)
+#define BITS_SDIO_DRV_TYPE_D_8822C                                             \
+	(BIT_MASK_SDIO_DRV_TYPE_D_8822C << BIT_SHIFT_SDIO_DRV_TYPE_D_8822C)
+#define BIT_CLEAR_SDIO_DRV_TYPE_D_8822C(x) ((x) & (~BITS_SDIO_DRV_TYPE_D_8822C))
+#define BIT_GET_SDIO_DRV_TYPE_D_8822C(x)                                       \
+	(((x) >> BIT_SHIFT_SDIO_DRV_TYPE_D_8822C) &                            \
+	 BIT_MASK_SDIO_DRV_TYPE_D_8822C)
+#define BIT_SET_SDIO_DRV_TYPE_D_8822C(x, v)                                    \
+	(BIT_CLEAR_SDIO_DRV_TYPE_D_8822C(x) | BIT_SDIO_DRV_TYPE_D_8822C(v))
+
+#define BIT_SHIFT_SDIO_DRV_TYPE_C_8822C 8
+#define BIT_MASK_SDIO_DRV_TYPE_C_8822C 0xf
+#define BIT_SDIO_DRV_TYPE_C_8822C(x)                                           \
+	(((x) & BIT_MASK_SDIO_DRV_TYPE_C_8822C)                                \
+	 << BIT_SHIFT_SDIO_DRV_TYPE_C_8822C)
+#define BITS_SDIO_DRV_TYPE_C_8822C                                             \
+	(BIT_MASK_SDIO_DRV_TYPE_C_8822C << BIT_SHIFT_SDIO_DRV_TYPE_C_8822C)
+#define BIT_CLEAR_SDIO_DRV_TYPE_C_8822C(x) ((x) & (~BITS_SDIO_DRV_TYPE_C_8822C))
+#define BIT_GET_SDIO_DRV_TYPE_C_8822C(x)                                       \
+	(((x) >> BIT_SHIFT_SDIO_DRV_TYPE_C_8822C) &                            \
+	 BIT_MASK_SDIO_DRV_TYPE_C_8822C)
+#define BIT_SET_SDIO_DRV_TYPE_C_8822C(x, v)                                    \
+	(BIT_CLEAR_SDIO_DRV_TYPE_C_8822C(x) | BIT_SDIO_DRV_TYPE_C_8822C(v))
+
+#define BIT_SHIFT_SDIO_DRV_TYPE_B_8822C 4
+#define BIT_MASK_SDIO_DRV_TYPE_B_8822C 0xf
+#define BIT_SDIO_DRV_TYPE_B_8822C(x)                                           \
+	(((x) & BIT_MASK_SDIO_DRV_TYPE_B_8822C)                                \
+	 << BIT_SHIFT_SDIO_DRV_TYPE_B_8822C)
+#define BITS_SDIO_DRV_TYPE_B_8822C                                             \
+	(BIT_MASK_SDIO_DRV_TYPE_B_8822C << BIT_SHIFT_SDIO_DRV_TYPE_B_8822C)
+#define BIT_CLEAR_SDIO_DRV_TYPE_B_8822C(x) ((x) & (~BITS_SDIO_DRV_TYPE_B_8822C))
+#define BIT_GET_SDIO_DRV_TYPE_B_8822C(x)                                       \
+	(((x) >> BIT_SHIFT_SDIO_DRV_TYPE_B_8822C) &                            \
+	 BIT_MASK_SDIO_DRV_TYPE_B_8822C)
+#define BIT_SET_SDIO_DRV_TYPE_B_8822C(x, v)                                    \
+	(BIT_CLEAR_SDIO_DRV_TYPE_B_8822C(x) | BIT_SDIO_DRV_TYPE_B_8822C(v))
+
+#define BIT_SHIFT_SDIO_DRV_TYPE_A_8822C 0
+#define BIT_MASK_SDIO_DRV_TYPE_A_8822C 0xf
+#define BIT_SDIO_DRV_TYPE_A_8822C(x)                                           \
+	(((x) & BIT_MASK_SDIO_DRV_TYPE_A_8822C)                                \
+	 << BIT_SHIFT_SDIO_DRV_TYPE_A_8822C)
+#define BITS_SDIO_DRV_TYPE_A_8822C                                             \
+	(BIT_MASK_SDIO_DRV_TYPE_A_8822C << BIT_SHIFT_SDIO_DRV_TYPE_A_8822C)
+#define BIT_CLEAR_SDIO_DRV_TYPE_A_8822C(x) ((x) & (~BITS_SDIO_DRV_TYPE_A_8822C))
+#define BIT_GET_SDIO_DRV_TYPE_A_8822C(x)                                       \
+	(((x) >> BIT_SHIFT_SDIO_DRV_TYPE_A_8822C) &                            \
+	 BIT_MASK_SDIO_DRV_TYPE_A_8822C)
+#define BIT_SET_SDIO_DRV_TYPE_A_8822C(x, v)                                    \
+	(BIT_CLEAR_SDIO_DRV_TYPE_A_8822C(x) | BIT_SDIO_DRV_TYPE_A_8822C(v))
+
+/* 2 REG_SDIO_MONITOR_8822C */
+
+#define BIT_SHIFT_SDIO_INT_START_8822C 0
+#define BIT_MASK_SDIO_INT_START_8822C 0xffffffffL
+#define BIT_SDIO_INT_START_8822C(x)                                            \
+	(((x) & BIT_MASK_SDIO_INT_START_8822C)                                 \
+	 << BIT_SHIFT_SDIO_INT_START_8822C)
+#define BITS_SDIO_INT_START_8822C                                              \
+	(BIT_MASK_SDIO_INT_START_8822C << BIT_SHIFT_SDIO_INT_START_8822C)
+#define BIT_CLEAR_SDIO_INT_START_8822C(x) ((x) & (~BITS_SDIO_INT_START_8822C))
+#define BIT_GET_SDIO_INT_START_8822C(x)                                        \
+	(((x) >> BIT_SHIFT_SDIO_INT_START_8822C) &                             \
+	 BIT_MASK_SDIO_INT_START_8822C)
+#define BIT_SET_SDIO_INT_START_8822C(x, v)                                     \
+	(BIT_CLEAR_SDIO_INT_START_8822C(x) | BIT_SDIO_INT_START_8822C(v))
+
+/* 2 REG_SDIO_MONITOR_2_8822C */
+#define BIT_CMD53_WT_EN_8822C BIT(23)
+
+#define BIT_SHIFT_SDIO_CLK_MONITOR_8822C 21
+#define BIT_MASK_SDIO_CLK_MONITOR_8822C 0x3
+#define BIT_SDIO_CLK_MONITOR_8822C(x)                                          \
+	(((x) & BIT_MASK_SDIO_CLK_MONITOR_8822C)                               \
+	 << BIT_SHIFT_SDIO_CLK_MONITOR_8822C)
+#define BITS_SDIO_CLK_MONITOR_8822C                                            \
+	(BIT_MASK_SDIO_CLK_MONITOR_8822C << BIT_SHIFT_SDIO_CLK_MONITOR_8822C)
+#define BIT_CLEAR_SDIO_CLK_MONITOR_8822C(x)                                    \
+	((x) & (~BITS_SDIO_CLK_MONITOR_8822C))
+#define BIT_GET_SDIO_CLK_MONITOR_8822C(x)                                      \
+	(((x) >> BIT_SHIFT_SDIO_CLK_MONITOR_8822C) &                           \
+	 BIT_MASK_SDIO_CLK_MONITOR_8822C)
+#define BIT_SET_SDIO_CLK_MONITOR_8822C(x, v)                                   \
+	(BIT_CLEAR_SDIO_CLK_MONITOR_8822C(x) | BIT_SDIO_CLK_MONITOR_8822C(v))
+
+#define BIT_SHIFT_SDIO_CLK_CNT_8822C 0
+#define BIT_MASK_SDIO_CLK_CNT_8822C 0x1fffff
+#define BIT_SDIO_CLK_CNT_8822C(x)                                              \
+	(((x) & BIT_MASK_SDIO_CLK_CNT_8822C) << BIT_SHIFT_SDIO_CLK_CNT_8822C)
+#define BITS_SDIO_CLK_CNT_8822C                                                \
+	(BIT_MASK_SDIO_CLK_CNT_8822C << BIT_SHIFT_SDIO_CLK_CNT_8822C)
+#define BIT_CLEAR_SDIO_CLK_CNT_8822C(x) ((x) & (~BITS_SDIO_CLK_CNT_8822C))
+#define BIT_GET_SDIO_CLK_CNT_8822C(x)                                          \
+	(((x) >> BIT_SHIFT_SDIO_CLK_CNT_8822C) & BIT_MASK_SDIO_CLK_CNT_8822C)
+#define BIT_SET_SDIO_CLK_CNT_8822C(x, v)                                       \
+	(BIT_CLEAR_SDIO_CLK_CNT_8822C(x) | BIT_SDIO_CLK_CNT_8822C(v))
+
+/* 2 REG_SDIO_HIMR_8822C */
+#define BIT_SDIO_CRCERR_MSK_8822C BIT(31)
+#define BIT_SDIO_HSISR3_IND_MSK_8822C BIT(30)
+#define BIT_SDIO_HSISR2_IND_MSK_8822C BIT(29)
+#define BIT_SDIO_HEISR_IND_MSK_8822C BIT(28)
+#define BIT_SDIO_CTWEND_MSK_8822C BIT(27)
+#define BIT_SDIO_ATIMEND_E_MSK_8822C BIT(26)
+#define BIT_SDIIO_ATIMEND_MSK_8822C BIT(25)
+#define BIT_SDIO_OCPINT_MSK_8822C BIT(24)
+#define BIT_SDIO_PSTIMEOUT_MSK_8822C BIT(23)
+#define BIT_SDIO_GTINT4_MSK_8822C BIT(22)
+#define BIT_SDIO_GTINT3_MSK_8822C BIT(21)
+#define BIT_SDIO_HSISR_IND_MSK_8822C BIT(20)
+#define BIT_SDIO_CPWM2_MSK_8822C BIT(19)
+#define BIT_SDIO_CPWM1_MSK_8822C BIT(18)
+#define BIT_SDIO_C2HCMD_INT_MSK_8822C BIT(17)
+#define BIT_SDIO_BCNERLY_INT_MSK_8822C BIT(16)
+#define BIT_SDIO_TXBCNERR_MSK_8822C BIT(7)
+#define BIT_SDIO_TXBCNOK_MSK_8822C BIT(6)
+#define BIT_SDIO_RXFOVW_MSK_8822C BIT(5)
+#define BIT_SDIO_TXFOVW_MSK_8822C BIT(4)
+#define BIT_SDIO_RXERR_MSK_8822C BIT(3)
+#define BIT_SDIO_TXERR_MSK_8822C BIT(2)
+#define BIT_SDIO_AVAL_MSK_8822C BIT(1)
+#define BIT_RX_REQUEST_MSK_8822C BIT(0)
+
+/* 2 REG_SDIO_HISR_8822C */
+#define BIT_SDIO_CRCERR_8822C BIT(31)
+#define BIT_SDIO_HSISR3_IND_8822C BIT(30)
+#define BIT_SDIO_HSISR2_IND_8822C BIT(29)
+#define BIT_SDIO_HEISR_IND_8822C BIT(28)
+#define BIT_SDIO_CTWEND_8822C BIT(27)
+#define BIT_SDIO_ATIMEND_E_8822C BIT(26)
+#define BIT_SDIO_ATIMEND_8822C BIT(25)
+#define BIT_SDIO_OCPINT_8822C BIT(24)
+#define BIT_SDIO_PSTIMEOUT_8822C BIT(23)
+#define BIT_SDIO_GTINT4_8822C BIT(22)
+#define BIT_SDIO_GTINT3_8822C BIT(21)
+#define BIT_SDIO_HSISR_IND_8822C BIT(20)
+#define BIT_SDIO_CPWM2_8822C BIT(19)
+#define BIT_SDIO_CPWM1_8822C BIT(18)
+#define BIT_SDIO_C2HCMD_INT_8822C BIT(17)
+#define BIT_SDIO_BCNERLY_INT_8822C BIT(16)
+#define BIT_SDIO_TXBCNERR_8822C BIT(7)
+#define BIT_SDIO_TXBCNOK_8822C BIT(6)
+#define BIT_SDIO_RXFOVW_8822C BIT(5)
+#define BIT_SDIO_TXFOVW_8822C BIT(4)
+#define BIT_SDIO_RXERR_8822C BIT(3)
+#define BIT_SDIO_TXERR_8822C BIT(2)
+#define BIT_SDIO_AVAL_8822C BIT(1)
+#define BIT_RX_REQUEST_8822C BIT(0)
+
+/* 2 REG_SDIO_RX_REQ_LEN_8822C */
+
+#define BIT_SHIFT_RX_REQ_LEN_V1_8822C 0
+#define BIT_MASK_RX_REQ_LEN_V1_8822C 0x3ffff
+#define BIT_RX_REQ_LEN_V1_8822C(x)                                             \
+	(((x) & BIT_MASK_RX_REQ_LEN_V1_8822C) << BIT_SHIFT_RX_REQ_LEN_V1_8822C)
+#define BITS_RX_REQ_LEN_V1_8822C                                               \
+	(BIT_MASK_RX_REQ_LEN_V1_8822C << BIT_SHIFT_RX_REQ_LEN_V1_8822C)
+#define BIT_CLEAR_RX_REQ_LEN_V1_8822C(x) ((x) & (~BITS_RX_REQ_LEN_V1_8822C))
+#define BIT_GET_RX_REQ_LEN_V1_8822C(x)                                         \
+	(((x) >> BIT_SHIFT_RX_REQ_LEN_V1_8822C) & BIT_MASK_RX_REQ_LEN_V1_8822C)
+#define BIT_SET_RX_REQ_LEN_V1_8822C(x, v)                                      \
+	(BIT_CLEAR_RX_REQ_LEN_V1_8822C(x) | BIT_RX_REQ_LEN_V1_8822C(v))
+
+/* 2 REG_SDIO_FREE_TXPG_SEQ_V1_8822C */
+
+#define BIT_SHIFT_FREE_TXPG_SEQ_8822C 0
+#define BIT_MASK_FREE_TXPG_SEQ_8822C 0xff
+#define BIT_FREE_TXPG_SEQ_8822C(x)                                             \
+	(((x) & BIT_MASK_FREE_TXPG_SEQ_8822C) << BIT_SHIFT_FREE_TXPG_SEQ_8822C)
+#define BITS_FREE_TXPG_SEQ_8822C                                               \
+	(BIT_MASK_FREE_TXPG_SEQ_8822C << BIT_SHIFT_FREE_TXPG_SEQ_8822C)
+#define BIT_CLEAR_FREE_TXPG_SEQ_8822C(x) ((x) & (~BITS_FREE_TXPG_SEQ_8822C))
+#define BIT_GET_FREE_TXPG_SEQ_8822C(x)                                         \
+	(((x) >> BIT_SHIFT_FREE_TXPG_SEQ_8822C) & BIT_MASK_FREE_TXPG_SEQ_8822C)
+#define BIT_SET_FREE_TXPG_SEQ_8822C(x, v)                                      \
+	(BIT_CLEAR_FREE_TXPG_SEQ_8822C(x) | BIT_FREE_TXPG_SEQ_8822C(v))
+
+/* 2 REG_SDIO_FREE_TXPG_8822C */
+
+#define BIT_SHIFT_MID_FREEPG_V1_8822C 16
+#define BIT_MASK_MID_FREEPG_V1_8822C 0xfff
+#define BIT_MID_FREEPG_V1_8822C(x)                                             \
+	(((x) & BIT_MASK_MID_FREEPG_V1_8822C) << BIT_SHIFT_MID_FREEPG_V1_8822C)
+#define BITS_MID_FREEPG_V1_8822C                                               \
+	(BIT_MASK_MID_FREEPG_V1_8822C << BIT_SHIFT_MID_FREEPG_V1_8822C)
+#define BIT_CLEAR_MID_FREEPG_V1_8822C(x) ((x) & (~BITS_MID_FREEPG_V1_8822C))
+#define BIT_GET_MID_FREEPG_V1_8822C(x)                                         \
+	(((x) >> BIT_SHIFT_MID_FREEPG_V1_8822C) & BIT_MASK_MID_FREEPG_V1_8822C)
+#define BIT_SET_MID_FREEPG_V1_8822C(x, v)                                      \
+	(BIT_CLEAR_MID_FREEPG_V1_8822C(x) | BIT_MID_FREEPG_V1_8822C(v))
+
+#define BIT_SHIFT_HIQ_FREEPG_V1_8822C 0
+#define BIT_MASK_HIQ_FREEPG_V1_8822C 0xfff
+#define BIT_HIQ_FREEPG_V1_8822C(x)                                             \
+	(((x) & BIT_MASK_HIQ_FREEPG_V1_8822C) << BIT_SHIFT_HIQ_FREEPG_V1_8822C)
+#define BITS_HIQ_FREEPG_V1_8822C                                               \
+	(BIT_MASK_HIQ_FREEPG_V1_8822C << BIT_SHIFT_HIQ_FREEPG_V1_8822C)
+#define BIT_CLEAR_HIQ_FREEPG_V1_8822C(x) ((x) & (~BITS_HIQ_FREEPG_V1_8822C))
+#define BIT_GET_HIQ_FREEPG_V1_8822C(x)                                         \
+	(((x) >> BIT_SHIFT_HIQ_FREEPG_V1_8822C) & BIT_MASK_HIQ_FREEPG_V1_8822C)
+#define BIT_SET_HIQ_FREEPG_V1_8822C(x, v)                                      \
+	(BIT_CLEAR_HIQ_FREEPG_V1_8822C(x) | BIT_HIQ_FREEPG_V1_8822C(v))
+
+/* 2 REG_SDIO_FREE_TXPG2_8822C */
+
+#define BIT_SHIFT_PUB_FREEPG_V1_8822C 16
+#define BIT_MASK_PUB_FREEPG_V1_8822C 0xfff
+#define BIT_PUB_FREEPG_V1_8822C(x)                                             \
+	(((x) & BIT_MASK_PUB_FREEPG_V1_8822C) << BIT_SHIFT_PUB_FREEPG_V1_8822C)
+#define BITS_PUB_FREEPG_V1_8822C                                               \
+	(BIT_MASK_PUB_FREEPG_V1_8822C << BIT_SHIFT_PUB_FREEPG_V1_8822C)
+#define BIT_CLEAR_PUB_FREEPG_V1_8822C(x) ((x) & (~BITS_PUB_FREEPG_V1_8822C))
+#define BIT_GET_PUB_FREEPG_V1_8822C(x)                                         \
+	(((x) >> BIT_SHIFT_PUB_FREEPG_V1_8822C) & BIT_MASK_PUB_FREEPG_V1_8822C)
+#define BIT_SET_PUB_FREEPG_V1_8822C(x, v)                                      \
+	(BIT_CLEAR_PUB_FREEPG_V1_8822C(x) | BIT_PUB_FREEPG_V1_8822C(v))
+
+#define BIT_SHIFT_LOW_FREEPG_V1_8822C 0
+#define BIT_MASK_LOW_FREEPG_V1_8822C 0xfff
+#define BIT_LOW_FREEPG_V1_8822C(x)                                             \
+	(((x) & BIT_MASK_LOW_FREEPG_V1_8822C) << BIT_SHIFT_LOW_FREEPG_V1_8822C)
+#define BITS_LOW_FREEPG_V1_8822C                                               \
+	(BIT_MASK_LOW_FREEPG_V1_8822C << BIT_SHIFT_LOW_FREEPG_V1_8822C)
+#define BIT_CLEAR_LOW_FREEPG_V1_8822C(x) ((x) & (~BITS_LOW_FREEPG_V1_8822C))
+#define BIT_GET_LOW_FREEPG_V1_8822C(x)                                         \
+	(((x) >> BIT_SHIFT_LOW_FREEPG_V1_8822C) & BIT_MASK_LOW_FREEPG_V1_8822C)
+#define BIT_SET_LOW_FREEPG_V1_8822C(x, v)                                      \
+	(BIT_CLEAR_LOW_FREEPG_V1_8822C(x) | BIT_LOW_FREEPG_V1_8822C(v))
+
+/* 2 REG_SDIO_OQT_FREE_TXPG_V1_8822C */
+
+#define BIT_SHIFT_NOAC_OQT_FREEPG_V1_8822C 24
+#define BIT_MASK_NOAC_OQT_FREEPG_V1_8822C 0xff
+#define BIT_NOAC_OQT_FREEPG_V1_8822C(x)                                        \
+	(((x) & BIT_MASK_NOAC_OQT_FREEPG_V1_8822C)                             \
+	 << BIT_SHIFT_NOAC_OQT_FREEPG_V1_8822C)
+#define BITS_NOAC_OQT_FREEPG_V1_8822C                                          \
+	(BIT_MASK_NOAC_OQT_FREEPG_V1_8822C                                     \
+	 << BIT_SHIFT_NOAC_OQT_FREEPG_V1_8822C)
+#define BIT_CLEAR_NOAC_OQT_FREEPG_V1_8822C(x)                                  \
+	((x) & (~BITS_NOAC_OQT_FREEPG_V1_8822C))
+#define BIT_GET_NOAC_OQT_FREEPG_V1_8822C(x)                                    \
+	(((x) >> BIT_SHIFT_NOAC_OQT_FREEPG_V1_8822C) &                         \
+	 BIT_MASK_NOAC_OQT_FREEPG_V1_8822C)
+#define BIT_SET_NOAC_OQT_FREEPG_V1_8822C(x, v)                                 \
+	(BIT_CLEAR_NOAC_OQT_FREEPG_V1_8822C(x) |                               \
+	 BIT_NOAC_OQT_FREEPG_V1_8822C(v))
+
+#define BIT_SHIFT_AC_OQT_FREEPG_V1_8822C 16
+#define BIT_MASK_AC_OQT_FREEPG_V1_8822C 0xff
+#define BIT_AC_OQT_FREEPG_V1_8822C(x)                                          \
+	(((x) & BIT_MASK_AC_OQT_FREEPG_V1_8822C)                               \
+	 << BIT_SHIFT_AC_OQT_FREEPG_V1_8822C)
+#define BITS_AC_OQT_FREEPG_V1_8822C                                            \
+	(BIT_MASK_AC_OQT_FREEPG_V1_8822C << BIT_SHIFT_AC_OQT_FREEPG_V1_8822C)
+#define BIT_CLEAR_AC_OQT_FREEPG_V1_8822C(x)                                    \
+	((x) & (~BITS_AC_OQT_FREEPG_V1_8822C))
+#define BIT_GET_AC_OQT_FREEPG_V1_8822C(x)                                      \
+	(((x) >> BIT_SHIFT_AC_OQT_FREEPG_V1_8822C) &                           \
+	 BIT_MASK_AC_OQT_FREEPG_V1_8822C)
+#define BIT_SET_AC_OQT_FREEPG_V1_8822C(x, v)                                   \
+	(BIT_CLEAR_AC_OQT_FREEPG_V1_8822C(x) | BIT_AC_OQT_FREEPG_V1_8822C(v))
+
+#define BIT_SHIFT_EXQ_FREEPG_V1_8822C 0
+#define BIT_MASK_EXQ_FREEPG_V1_8822C 0xfff
+#define BIT_EXQ_FREEPG_V1_8822C(x)                                             \
+	(((x) & BIT_MASK_EXQ_FREEPG_V1_8822C) << BIT_SHIFT_EXQ_FREEPG_V1_8822C)
+#define BITS_EXQ_FREEPG_V1_8822C                                               \
+	(BIT_MASK_EXQ_FREEPG_V1_8822C << BIT_SHIFT_EXQ_FREEPG_V1_8822C)
+#define BIT_CLEAR_EXQ_FREEPG_V1_8822C(x) ((x) & (~BITS_EXQ_FREEPG_V1_8822C))
+#define BIT_GET_EXQ_FREEPG_V1_8822C(x)                                         \
+	(((x) >> BIT_SHIFT_EXQ_FREEPG_V1_8822C) & BIT_MASK_EXQ_FREEPG_V1_8822C)
+#define BIT_SET_EXQ_FREEPG_V1_8822C(x, v)                                      \
+	(BIT_CLEAR_EXQ_FREEPG_V1_8822C(x) | BIT_EXQ_FREEPG_V1_8822C(v))
+
+/* 2 REG_SDIO_TXPKT_EMPTY_8822C */
+#define BIT_SDIO_BCNQ_EMPTY_8822C BIT(11)
+#define BIT_SDIO_HQQ_EMPTY_8822C BIT(10)
+#define BIT_SDIO_MQQ_EMPTY_8822C BIT(9)
+#define BIT_SDIO_MGQ_CPU_EMPTY_8822C BIT(8)
+#define BIT_SDIO_AC7Q_EMPTY_8822C BIT(7)
+#define BIT_SDIO_AC6Q_EMPTY_8822C BIT(6)
+#define BIT_SDIO_AC5Q_EMPTY_8822C BIT(5)
+#define BIT_SDIO_AC4Q_EMPTY_8822C BIT(4)
+#define BIT_SDIO_AC3Q_EMPTY_8822C BIT(3)
+#define BIT_SDIO_AC2Q_EMPTY_8822C BIT(2)
+#define BIT_SDIO_AC1Q_EMPTY_8822C BIT(1)
+#define BIT_SDIO_AC0Q_EMPTY_8822C BIT(0)
+
+/* 2 REG_SDIO_HTSFR_INFO_8822C */
+
+#define BIT_SHIFT_HTSFR1_8822C 16
+#define BIT_MASK_HTSFR1_8822C 0xffff
+#define BIT_HTSFR1_8822C(x)                                                    \
+	(((x) & BIT_MASK_HTSFR1_8822C) << BIT_SHIFT_HTSFR1_8822C)
+#define BITS_HTSFR1_8822C (BIT_MASK_HTSFR1_8822C << BIT_SHIFT_HTSFR1_8822C)
+#define BIT_CLEAR_HTSFR1_8822C(x) ((x) & (~BITS_HTSFR1_8822C))
+#define BIT_GET_HTSFR1_8822C(x)                                                \
+	(((x) >> BIT_SHIFT_HTSFR1_8822C) & BIT_MASK_HTSFR1_8822C)
+#define BIT_SET_HTSFR1_8822C(x, v)                                             \
+	(BIT_CLEAR_HTSFR1_8822C(x) | BIT_HTSFR1_8822C(v))
+
+#define BIT_SHIFT_HTSFR0_8822C 0
+#define BIT_MASK_HTSFR0_8822C 0xffff
+#define BIT_HTSFR0_8822C(x)                                                    \
+	(((x) & BIT_MASK_HTSFR0_8822C) << BIT_SHIFT_HTSFR0_8822C)
+#define BITS_HTSFR0_8822C (BIT_MASK_HTSFR0_8822C << BIT_SHIFT_HTSFR0_8822C)
+#define BIT_CLEAR_HTSFR0_8822C(x) ((x) & (~BITS_HTSFR0_8822C))
+#define BIT_GET_HTSFR0_8822C(x)                                                \
+	(((x) >> BIT_SHIFT_HTSFR0_8822C) & BIT_MASK_HTSFR0_8822C)
+#define BIT_SET_HTSFR0_8822C(x, v)                                             \
+	(BIT_CLEAR_HTSFR0_8822C(x) | BIT_HTSFR0_8822C(v))
+
+/* 2 REG_SDIO_HCPWM1_V2_8822C */
+#define BIT_TOGGLE_8822C BIT(7)
+#define BIT_CUR_PS_8822C BIT(0)
+
+/* 2 REG_SDIO_HCPWM2_V2_8822C */
+
+/* 2 REG_SDIO_INDIRECT_REG_CFG_8822C */
+#define BIT_INDIRECT_REG_RDY_8822C BIT(20)
+#define BIT_INDIRECT_REG_R_8822C BIT(19)
+#define BIT_INDIRECT_REG_W_8822C BIT(18)
+
+#define BIT_SHIFT_INDIRECT_REG_SIZE_8822C 16
+#define BIT_MASK_INDIRECT_REG_SIZE_8822C 0x3
+#define BIT_INDIRECT_REG_SIZE_8822C(x)                                         \
+	(((x) & BIT_MASK_INDIRECT_REG_SIZE_8822C)                              \
+	 << BIT_SHIFT_INDIRECT_REG_SIZE_8822C)
+#define BITS_INDIRECT_REG_SIZE_8822C                                           \
+	(BIT_MASK_INDIRECT_REG_SIZE_8822C << BIT_SHIFT_INDIRECT_REG_SIZE_8822C)
+#define BIT_CLEAR_INDIRECT_REG_SIZE_8822C(x)                                   \
+	((x) & (~BITS_INDIRECT_REG_SIZE_8822C))
+#define BIT_GET_INDIRECT_REG_SIZE_8822C(x)                                     \
+	(((x) >> BIT_SHIFT_INDIRECT_REG_SIZE_8822C) &                          \
+	 BIT_MASK_INDIRECT_REG_SIZE_8822C)
+#define BIT_SET_INDIRECT_REG_SIZE_8822C(x, v)                                  \
+	(BIT_CLEAR_INDIRECT_REG_SIZE_8822C(x) | BIT_INDIRECT_REG_SIZE_8822C(v))
+
+#define BIT_SHIFT_INDIRECT_REG_ADDR_8822C 0
+#define BIT_MASK_INDIRECT_REG_ADDR_8822C 0xffff
+#define BIT_INDIRECT_REG_ADDR_8822C(x)                                         \
+	(((x) & BIT_MASK_INDIRECT_REG_ADDR_8822C)                              \
+	 << BIT_SHIFT_INDIRECT_REG_ADDR_8822C)
+#define BITS_INDIRECT_REG_ADDR_8822C                                           \
+	(BIT_MASK_INDIRECT_REG_ADDR_8822C << BIT_SHIFT_INDIRECT_REG_ADDR_8822C)
+#define BIT_CLEAR_INDIRECT_REG_ADDR_8822C(x)                                   \
+	((x) & (~BITS_INDIRECT_REG_ADDR_8822C))
+#define BIT_GET_INDIRECT_REG_ADDR_8822C(x)                                     \
+	(((x) >> BIT_SHIFT_INDIRECT_REG_ADDR_8822C) &                          \
+	 BIT_MASK_INDIRECT_REG_ADDR_8822C)
+#define BIT_SET_INDIRECT_REG_ADDR_8822C(x, v)                                  \
+	(BIT_CLEAR_INDIRECT_REG_ADDR_8822C(x) | BIT_INDIRECT_REG_ADDR_8822C(v))
+
+/* 2 REG_SDIO_INDIRECT_REG_DATA_8822C */
+
+#define BIT_SHIFT_INDIRECT_REG_DATA_8822C 0
+#define BIT_MASK_INDIRECT_REG_DATA_8822C 0xffffffffL
+#define BIT_INDIRECT_REG_DATA_8822C(x)                                         \
+	(((x) & BIT_MASK_INDIRECT_REG_DATA_8822C)                              \
+	 << BIT_SHIFT_INDIRECT_REG_DATA_8822C)
+#define BITS_INDIRECT_REG_DATA_8822C                                           \
+	(BIT_MASK_INDIRECT_REG_DATA_8822C << BIT_SHIFT_INDIRECT_REG_DATA_8822C)
+#define BIT_CLEAR_INDIRECT_REG_DATA_8822C(x)                                   \
+	((x) & (~BITS_INDIRECT_REG_DATA_8822C))
+#define BIT_GET_INDIRECT_REG_DATA_8822C(x)                                     \
+	(((x) >> BIT_SHIFT_INDIRECT_REG_DATA_8822C) &                          \
+	 BIT_MASK_INDIRECT_REG_DATA_8822C)
+#define BIT_SET_INDIRECT_REG_DATA_8822C(x, v)                                  \
+	(BIT_CLEAR_INDIRECT_REG_DATA_8822C(x) | BIT_INDIRECT_REG_DATA_8822C(v))
+
+/* 2 REG_SDIO_H2C_8822C */
+
+#define BIT_SHIFT_SDIO_H2C_MSG_8822C 0
+#define BIT_MASK_SDIO_H2C_MSG_8822C 0xffffffffL
+#define BIT_SDIO_H2C_MSG_8822C(x)                                              \
+	(((x) & BIT_MASK_SDIO_H2C_MSG_8822C) << BIT_SHIFT_SDIO_H2C_MSG_8822C)
+#define BITS_SDIO_H2C_MSG_8822C                                                \
+	(BIT_MASK_SDIO_H2C_MSG_8822C << BIT_SHIFT_SDIO_H2C_MSG_8822C)
+#define BIT_CLEAR_SDIO_H2C_MSG_8822C(x) ((x) & (~BITS_SDIO_H2C_MSG_8822C))
+#define BIT_GET_SDIO_H2C_MSG_8822C(x)                                          \
+	(((x) >> BIT_SHIFT_SDIO_H2C_MSG_8822C) & BIT_MASK_SDIO_H2C_MSG_8822C)
+#define BIT_SET_SDIO_H2C_MSG_8822C(x, v)                                       \
+	(BIT_CLEAR_SDIO_H2C_MSG_8822C(x) | BIT_SDIO_H2C_MSG_8822C(v))
+
+/* 2 REG_SDIO_C2H_8822C */
+
+#define BIT_SHIFT_SDIO_C2H_MSG_8822C 0
+#define BIT_MASK_SDIO_C2H_MSG_8822C 0xffffffffL
+#define BIT_SDIO_C2H_MSG_8822C(x)                                              \
+	(((x) & BIT_MASK_SDIO_C2H_MSG_8822C) << BIT_SHIFT_SDIO_C2H_MSG_8822C)
+#define BITS_SDIO_C2H_MSG_8822C                                                \
+	(BIT_MASK_SDIO_C2H_MSG_8822C << BIT_SHIFT_SDIO_C2H_MSG_8822C)
+#define BIT_CLEAR_SDIO_C2H_MSG_8822C(x) ((x) & (~BITS_SDIO_C2H_MSG_8822C))
+#define BIT_GET_SDIO_C2H_MSG_8822C(x)                                          \
+	(((x) >> BIT_SHIFT_SDIO_C2H_MSG_8822C) & BIT_MASK_SDIO_C2H_MSG_8822C)
+#define BIT_SET_SDIO_C2H_MSG_8822C(x, v)                                       \
+	(BIT_CLEAR_SDIO_C2H_MSG_8822C(x) | BIT_SDIO_C2H_MSG_8822C(v))
+
+/* 2 REG_SDIO_HRPWM1_8822C */
+#define BIT_TOGGLE_8822C BIT(7)
+#define BIT_ACK_8822C BIT(6)
+#define BIT_REQ_PS_8822C BIT(0)
+
+/* 2 REG_SDIO_HRPWM2_8822C */
+
+/* 2 REG_SDIO_HPS_CLKR_8822C */
+
+/* 2 REG_SDIO_BUS_CTRL_8822C */
+#define BIT_INT_MASK_DIS_8822C BIT(4)
+#define BIT_PAD_CLK_XHGE_EN_8822C BIT(3)
+#define BIT_INTER_CLK_EN_8822C BIT(2)
+#define BIT_EN_RPT_TXCRC_8822C BIT(1)
+#define BIT_DIS_RXDMA_STS_8822C BIT(0)
+
+/* 2 REG_SDIO_HSUS_CTRL_8822C */
+#define BIT_INTR_CTRL_8822C BIT(4)
+#define BIT_SDIO_VOLTAGE_8822C BIT(3)
+#define BIT_BYPASS_INIT_8822C BIT(2)
+#define BIT_HCI_RESUME_RDY_8822C BIT(1)
+#define BIT_HCI_SUS_REQ_8822C BIT(0)
+
+/* 2 REG_SDIO_RESPONSE_TIMER_8822C */
+
+#define BIT_SHIFT_CMDIN_2RESP_TIMER_8822C 0
+#define BIT_MASK_CMDIN_2RESP_TIMER_8822C 0xffff
+#define BIT_CMDIN_2RESP_TIMER_8822C(x)                                         \
+	(((x) & BIT_MASK_CMDIN_2RESP_TIMER_8822C)                              \
+	 << BIT_SHIFT_CMDIN_2RESP_TIMER_8822C)
+#define BITS_CMDIN_2RESP_TIMER_8822C                                           \
+	(BIT_MASK_CMDIN_2RESP_TIMER_8822C << BIT_SHIFT_CMDIN_2RESP_TIMER_8822C)
+#define BIT_CLEAR_CMDIN_2RESP_TIMER_8822C(x)                                   \
+	((x) & (~BITS_CMDIN_2RESP_TIMER_8822C))
+#define BIT_GET_CMDIN_2RESP_TIMER_8822C(x)                                     \
+	(((x) >> BIT_SHIFT_CMDIN_2RESP_TIMER_8822C) &                          \
+	 BIT_MASK_CMDIN_2RESP_TIMER_8822C)
+#define BIT_SET_CMDIN_2RESP_TIMER_8822C(x, v)                                  \
+	(BIT_CLEAR_CMDIN_2RESP_TIMER_8822C(x) | BIT_CMDIN_2RESP_TIMER_8822C(v))
+
+/* 2 REG_SDIO_CMD_CRC_8822C */
+
+#define BIT_SHIFT_SDIO_CMD_CRC_V1_8822C 0
+#define BIT_MASK_SDIO_CMD_CRC_V1_8822C 0xff
+#define BIT_SDIO_CMD_CRC_V1_8822C(x)                                           \
+	(((x) & BIT_MASK_SDIO_CMD_CRC_V1_8822C)                                \
+	 << BIT_SHIFT_SDIO_CMD_CRC_V1_8822C)
+#define BITS_SDIO_CMD_CRC_V1_8822C                                             \
+	(BIT_MASK_SDIO_CMD_CRC_V1_8822C << BIT_SHIFT_SDIO_CMD_CRC_V1_8822C)
+#define BIT_CLEAR_SDIO_CMD_CRC_V1_8822C(x) ((x) & (~BITS_SDIO_CMD_CRC_V1_8822C))
+#define BIT_GET_SDIO_CMD_CRC_V1_8822C(x)                                       \
+	(((x) >> BIT_SHIFT_SDIO_CMD_CRC_V1_8822C) &                            \
+	 BIT_MASK_SDIO_CMD_CRC_V1_8822C)
+#define BIT_SET_SDIO_CMD_CRC_V1_8822C(x, v)                                    \
+	(BIT_CLEAR_SDIO_CMD_CRC_V1_8822C(x) | BIT_SDIO_CMD_CRC_V1_8822C(v))
+
+/* 2 REG_SDIO_HSISR_8822C */
+#define BIT_DRV_WLAN_INT_CLR_8822C BIT(1)
+#define BIT_DRV_WLAN_INT_8822C BIT(0)
+
+/* 2 REG_SDIO_HSIMR_8822C */
+#define BIT_HISR_MASK_8822C BIT(0)
+
+/* 2 REG_SDIO_DIOERR_RPT_8822C */
+#define BIT_SDIO_PAGE_ERR_8822C BIT(0)
+
+/* 2 REG_SDIO_CMD_ERRCNT_8822C */
+
+#define BIT_SHIFT_CMD_CRC_ERR_CNT_8822C 0
+#define BIT_MASK_CMD_CRC_ERR_CNT_8822C 0xff
+#define BIT_CMD_CRC_ERR_CNT_8822C(x)                                           \
+	(((x) & BIT_MASK_CMD_CRC_ERR_CNT_8822C)                                \
+	 << BIT_SHIFT_CMD_CRC_ERR_CNT_8822C)
+#define BITS_CMD_CRC_ERR_CNT_8822C                                             \
+	(BIT_MASK_CMD_CRC_ERR_CNT_8822C << BIT_SHIFT_CMD_CRC_ERR_CNT_8822C)
+#define BIT_CLEAR_CMD_CRC_ERR_CNT_8822C(x) ((x) & (~BITS_CMD_CRC_ERR_CNT_8822C))
+#define BIT_GET_CMD_CRC_ERR_CNT_8822C(x)                                       \
+	(((x) >> BIT_SHIFT_CMD_CRC_ERR_CNT_8822C) &                            \
+	 BIT_MASK_CMD_CRC_ERR_CNT_8822C)
+#define BIT_SET_CMD_CRC_ERR_CNT_8822C(x, v)                                    \
+	(BIT_CLEAR_CMD_CRC_ERR_CNT_8822C(x) | BIT_CMD_CRC_ERR_CNT_8822C(v))
+
+/* 2 REG_SDIO_DATA_ERRCNT_8822C */
+
+#define BIT_SHIFT_DATA_CRC_ERR_CNT_8822C 0
+#define BIT_MASK_DATA_CRC_ERR_CNT_8822C 0xff
+#define BIT_DATA_CRC_ERR_CNT_8822C(x)                                          \
+	(((x) & BIT_MASK_DATA_CRC_ERR_CNT_8822C)                               \
+	 << BIT_SHIFT_DATA_CRC_ERR_CNT_8822C)
+#define BITS_DATA_CRC_ERR_CNT_8822C                                            \
+	(BIT_MASK_DATA_CRC_ERR_CNT_8822C << BIT_SHIFT_DATA_CRC_ERR_CNT_8822C)
+#define BIT_CLEAR_DATA_CRC_ERR_CNT_8822C(x)                                    \
+	((x) & (~BITS_DATA_CRC_ERR_CNT_8822C))
+#define BIT_GET_DATA_CRC_ERR_CNT_8822C(x)                                      \
+	(((x) >> BIT_SHIFT_DATA_CRC_ERR_CNT_8822C) &                           \
+	 BIT_MASK_DATA_CRC_ERR_CNT_8822C)
+#define BIT_SET_DATA_CRC_ERR_CNT_8822C(x, v)                                   \
+	(BIT_CLEAR_DATA_CRC_ERR_CNT_8822C(x) | BIT_DATA_CRC_ERR_CNT_8822C(v))
+
+/* 2 REG_SDIO_CMD_ERR_CONTENT_8822C */
+
+#define BIT_SHIFT_SDIO_CMD_ERR_CONTENT_8822C 0
+#define BIT_MASK_SDIO_CMD_ERR_CONTENT_8822C 0xffffffffffL
+#define BIT_SDIO_CMD_ERR_CONTENT_8822C(x)                                      \
+	(((x) & BIT_MASK_SDIO_CMD_ERR_CONTENT_8822C)                           \
+	 << BIT_SHIFT_SDIO_CMD_ERR_CONTENT_8822C)
+#define BITS_SDIO_CMD_ERR_CONTENT_8822C                                        \
+	(BIT_MASK_SDIO_CMD_ERR_CONTENT_8822C                                   \
+	 << BIT_SHIFT_SDIO_CMD_ERR_CONTENT_8822C)
+#define BIT_CLEAR_SDIO_CMD_ERR_CONTENT_8822C(x)                                \
+	((x) & (~BITS_SDIO_CMD_ERR_CONTENT_8822C))
+#define BIT_GET_SDIO_CMD_ERR_CONTENT_8822C(x)                                  \
+	(((x) >> BIT_SHIFT_SDIO_CMD_ERR_CONTENT_8822C) &                       \
+	 BIT_MASK_SDIO_CMD_ERR_CONTENT_8822C)
+#define BIT_SET_SDIO_CMD_ERR_CONTENT_8822C(x, v)                               \
+	(BIT_CLEAR_SDIO_CMD_ERR_CONTENT_8822C(x) |                             \
+	 BIT_SDIO_CMD_ERR_CONTENT_8822C(v))
+
+/* 2 REG_SDIO_CRC_ERR_IDX_8822C */
+#define BIT_D3_CRC_ERR_8822C BIT(4)
+#define BIT_D2_CRC_ERR_8822C BIT(3)
+#define BIT_D1_CRC_ERR_8822C BIT(2)
+#define BIT_D0_CRC_ERR_8822C BIT(1)
+#define BIT_CMD_CRC_ERR_8822C BIT(0)
+
+/* 2 REG_SDIO_DATA_CRC_8822C */
+
+#define BIT_SHIFT_SDIO_DATA_CRC_8822C 0
+#define BIT_MASK_SDIO_DATA_CRC_8822C 0xffff
+#define BIT_SDIO_DATA_CRC_8822C(x)                                             \
+	(((x) & BIT_MASK_SDIO_DATA_CRC_8822C) << BIT_SHIFT_SDIO_DATA_CRC_8822C)
+#define BITS_SDIO_DATA_CRC_8822C                                               \
+	(BIT_MASK_SDIO_DATA_CRC_8822C << BIT_SHIFT_SDIO_DATA_CRC_8822C)
+#define BIT_CLEAR_SDIO_DATA_CRC_8822C(x) ((x) & (~BITS_SDIO_DATA_CRC_8822C))
+#define BIT_GET_SDIO_DATA_CRC_8822C(x)                                         \
+	(((x) >> BIT_SHIFT_SDIO_DATA_CRC_8822C) & BIT_MASK_SDIO_DATA_CRC_8822C)
+#define BIT_SET_SDIO_DATA_CRC_8822C(x, v)                                      \
+	(BIT_CLEAR_SDIO_DATA_CRC_8822C(x) | BIT_SDIO_DATA_CRC_8822C(v))
+
+/* 2 REG_SDIO_TRANS_FIFO_STATUS_8822C */
+#define BIT_TRANS_FIFO_UNDERFLOW_8822C BIT(1)
+#define BIT_TRANS_FIFO_OVERFLOW_8822C BIT(0)
+
+#endif
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/halmac/halmac_fw_info.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/halmac/halmac_fw_info.h
--- linux-5.6.3/3rdparty/rtl8821ce/hal/halmac/halmac_fw_info.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/halmac/halmac_fw_info.h	2020-04-10 16:35:06.811659835 +0300
@@ -0,0 +1,119 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ ******************************************************************************/
+
+#ifndef _HALMAC_FW_INFO_H_
+#define _HALMAC_FW_INFO_H_
+
+#define H2C_FORMAT_VERSION		11
+
+/* FW bin information */
+#define WLAN_FW_HDR_SIZE		64
+#define WLAN_FW_HDR_CHKSUM_SIZE		8
+
+#define WLAN_FW_HDR_VERSION		4
+#define WLAN_FW_HDR_SUBVERSION		6
+#define WLAN_FW_HDR_SUBINDEX		7
+#define WLAN_FW_HDR_MONTH		16
+#define WLAN_FW_HDR_DATE		17
+#define WLAN_FW_HDR_HOUR		18
+#define WLAN_FW_HDR_MIN			19
+#define WLAN_FW_HDR_YEAR		20
+#define WLAN_FW_HDR_MEM_USAGE		24
+#define WLAN_FW_HDR_H2C_FMT_VER		28
+#define WLAN_FW_HDR_DMEM_ADDR		32
+#define WLAN_FW_HDR_DMEM_SIZE		36
+#define WLAN_FW_HDR_IMEM_SIZE		48
+#define WLAN_FW_HDR_EMEM_SIZE		52
+#define WLAN_FW_HDR_EMEM_ADDR		56
+#define WLAN_FW_HDR_IMEM_ADDR		60
+
+#define H2C_ACK_HDR_CONTENT_LENGTH		8
+#define CFG_PARAMETER_ACK_CONTENT_LENGTH	16
+#define SCAN_STATUS_RPT_CONTENT_LENGTH		4
+#define C2H_DBG_HDR_LEN				4
+#define C2H_DBG_CONTENT_MAX_LENGTH		228
+#define C2H_DBG_CONTENT_SEQ_OFFSET		1
+
+/* Rename from FW SysHalCom_Debug_RAM.h */
+#define FW_REG_H2CPKT_DONE_SEQ		0x1C8
+#define FW_REG_WOW_REASON		0x1C7
+
+enum halmac_data_type {
+	HALMAC_DATA_TYPE_MAC_REG = 0x00,
+	HALMAC_DATA_TYPE_BB_REG = 0x01,
+	HALMAC_DATA_TYPE_RADIO_A = 0x02,
+	HALMAC_DATA_TYPE_RADIO_B = 0x03,
+	HALMAC_DATA_TYPE_RADIO_C = 0x04,
+	HALMAC_DATA_TYPE_RADIO_D = 0x05,
+
+	HALMAC_DATA_TYPE_DRV_DEFINE_0 = 0x80,
+	HALMAC_DATA_TYPE_DRV_DEFINE_1 = 0x81,
+	HALMAC_DATA_TYPE_DRV_DEFINE_2 = 0x82,
+	HALMAC_DATA_TYPE_DRV_DEFINE_3 = 0x83,
+	HALMAC_DATA_TYPE_UNDEFINE = 0x7FFFFFFF,
+};
+
+enum halmac_packet_id {
+	HALMAC_PACKET_PROBE_REQ = 0x00,
+	HALMAC_PACKET_SYNC_BCN = 0x01,
+	HALMAC_PACKET_DISCOVERY_BCN = 0x02,
+	HALMAC_PACKET_UNDEFINE = 0x7FFFFFFF,
+};
+
+enum halmac_cs_action_id {
+	HALMAC_CS_ACTION_NONE = 0x00,
+	HALMAC_CS_ACTIVE_SCAN = 0x01,
+	HALMAC_CS_NAN_NONMASTER_DW = 0x02,
+	HALMAC_CS_NAN_NONMASTER_NONDW = 0x03,
+	HALMAC_CS_NAN_MASTER_NONDW = 0x04,
+	HALMAC_CS_NAN_MASTER_DW = 0x05,
+	HALMAC_CS_ACTION_UNDEFINE = 0x7FFFFFFF,
+};
+
+enum halmac_cs_extra_action_id {
+	HALMAC_CS_EXTRA_ACTION_NONE = 0x00,
+	HALMAC_CS_EXTRA_UPDATE_PROBE = 0x01,
+	HALMAC_CS_EXTRA_UPDATE_BEACON = 0x02,
+	HALMAC_CS_EXTRA_ACTION_UNDEFINE = 0x7FFFFFFF,
+};
+
+enum halmac_h2c_return_code {
+	HALMAC_H2C_RETURN_SUCCESS = 0x00,
+	HALMAC_H2C_RETURN_CFG_ERR_LEN = 0x01,
+	HALMAC_H2C_RETURN_CFG_ERR_CMD = 0x02,
+	HALMAC_H2C_RETURN_EFUSE_ERR_DUMP = 0x03,
+	HALMAC_H2C_RETURN_DATAPACK_ERR_FULL = 0x04,
+	HALMAC_H2C_RETURN_DATAPACK_ERR_ID = 0x05,
+	HALMAC_H2C_RETURN_RUN_ERR_EMPTY = 0x06,
+	HALMAC_H2C_RETURN_RUN_ERR_LEN = 0x07,
+	HALMAC_H2C_RETURN_RUN_ERR_CMD = 0x08,
+	HALMAC_H2C_RETURN_RUN_ERR_ID = 0x09,
+	HALMAC_H2C_RETURN_PACKET_ERR_FULL = 0x0A,
+	HALMAC_H2C_RETURN_PACKET_ERR_ID = 0x0B,
+	HALMAC_H2C_RETURN_SCAN_ERR_FULL = 0x0C,
+	HALMAC_H2C_RETURN_SCAN_ERR_PHYDM = 0x0D,
+	HALMAC_H2C_RETURN_ORIG_ERR_ID = 0x0E,
+	HALMAC_H2C_RETURN_UNDEFINE = 0x7FFFFFFF,
+};
+
+enum halmac_scan_report_code {
+	HALMAC_SCAN_REPORT_DONE	= 0x00,
+	HALMAC_SCAN_REPORT_ERR_PHYDM = 0x01,
+	HALMAC_SCAN_REPORT_ERR_ID = 0x02,
+	HALMAC_SCAN_REPORT_ERR_TX = 0x03,
+	HALMAC_SCAN_REPORT_UNDEFINE = 0x7FFFFFFF,
+};
+
+#endif
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/halmac/halmac_fw_offload_c2h_ap.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/halmac/halmac_fw_offload_c2h_ap.h
--- linux-5.6.3/3rdparty/rtl8821ce/hal/halmac/halmac_fw_offload_c2h_ap.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/halmac/halmac_fw_offload_c2h_ap.h	2020-04-10 16:35:06.811659835 +0300
@@ -0,0 +1,515 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ ******************************************************************************/
+
+#ifndef _HAL_FWOFFLOADC2HFORMAT_H2C_C2H_AP_H_
+#define _HAL_FWOFFLOADC2HFORMAT_H2C_C2H_AP_H_
+#define C2H_SUB_CMD_ID_C2H_DBG 0X00
+#define C2H_SUB_CMD_ID_BT_COEX_INFO 0X02
+#define C2H_SUB_CMD_ID_SCAN_STATUS_RPT 0X03
+#define C2H_SUB_CMD_ID_H2C_ACK_HDR 0X01
+#define C2H_SUB_CMD_ID_CFG_PARAM_ACK 0X01
+#define C2H_SUB_CMD_ID_BT_COEX_ACK 0X01
+#define C2H_SUB_CMD_ID_DUMP_PHYSICAL_EFUSE_ACK 0X01
+#define C2H_SUB_CMD_ID_UPDATE_PKT_ACK 0X01
+#define C2H_SUB_CMD_ID_UPDATE_DATAPACK_ACK 0X01
+#define C2H_SUB_CMD_ID_RUN_DATAPACK_ACK 0X01
+#define C2H_SUB_CMD_ID_CH_SWITCH_ACK 0X01
+#define C2H_SUB_CMD_ID_IQK_ACK 0X01
+#define C2H_SUB_CMD_ID_PWR_TRK_ACK 0X01
+#define C2H_SUB_CMD_ID_PSD_ACK 0X01
+#define C2H_SUB_CMD_ID_FW_MEM_DUMP_ACK 0X01
+#define C2H_SUB_CMD_ID_PSD_DATA 0X04
+#define C2H_SUB_CMD_ID_EFUSE_DATA 0X05
+#define C2H_SUB_CMD_ID_IQK_DATA 0X06
+#define C2H_SUB_CMD_ID_C2H_PKT_FTM_DBG 0X07
+#define C2H_SUB_CMD_ID_C2H_PKT_FTM_2_DBG 0X08
+#define C2H_SUB_CMD_ID_C2H_PKT_FTM_3_DBG 0X09
+#define C2H_SUB_CMD_ID_C2H_PKT_FTM_4_DBG 0X0A
+#define C2H_SUB_CMD_ID_FTMACKRPT_HDL_DBG 0X0B
+#define C2H_SUB_CMD_ID_FTMC2H_RPT 0X0C
+#define C2H_SUB_CMD_ID_DRVFTMC2H_RPT 0X0D
+#define C2H_SUB_CMD_ID_C2H_PKT_FTM_5_DBG 0X0E
+#define C2H_SUB_CMD_ID_CCX_RPT 0X0F
+#define C2H_SUB_CMD_ID_C2H_PKT_NAN_RPT 0X10
+#define C2H_SUB_CMD_ID_C2H_PKT_ATM_RPT 0X11
+#define C2H_SUB_CMD_ID_C2H_PKT_FTMSESSION_END 0X1C
+#define C2H_SUB_CMD_ID_C2H_PKT_DETECT_THERMAL 0X1D
+#define C2H_SUB_CMD_ID_FW_DBG_MSG 0XFF
+#define C2H_SUB_CMD_ID_FW_SNDING_ACK 0X01
+#define C2H_SUB_CMD_ID_FW_FWCTRL_RPT 0X1F
+#define C2H_SUB_CMD_ID_H2C_LOOPBACK_ACK 0X20
+#define C2H_SUB_CMD_ID_FWCMD_LOOPBACK_ACK 0X21
+#define C2H_SUB_CMD_ID_FW_TBTT_RPT 0X23
+#define H2C_SUB_CMD_ID_CFG_PARAM_ACK SUB_CMD_ID_CFG_PARAM
+#define H2C_SUB_CMD_ID_BT_COEX_ACK SUB_CMD_ID_BT_COEX
+#define H2C_SUB_CMD_ID_DUMP_PHYSICAL_EFUSE_ACK SUB_CMD_ID_DUMP_PHYSICAL_EFUSE
+#define H2C_SUB_CMD_ID_UPDATE_PKT_ACK SUB_CMD_ID_UPDATE_PKT
+#define H2C_SUB_CMD_ID_UPDATE_DATAPACK_ACK SUB_CMD_ID_UPDATE_DATAPACK
+#define H2C_SUB_CMD_ID_RUN_DATAPACK_ACK SUB_CMD_ID_RUN_DATAPACK
+#define H2C_SUB_CMD_ID_CH_SWITCH_ACK SUB_CMD_ID_CH_SWITCH
+#define H2C_SUB_CMD_ID_IQK_ACK SUB_CMD_ID_IQK
+#define H2C_SUB_CMD_ID_PWR_TRK_ACK SUB_CMD_ID_PWR_TRK
+#define H2C_SUB_CMD_ID_PSD_ACK SUB_CMD_ID_PSD
+#define H2C_SUB_CMD_ID_FW_MEM_DUMP_ACK SUB_CMD_ID_FW_MEM_DUMP
+#define H2C_SUB_CMD_ID_CCX_RPT SUB_CMD_ID_CCX_RPT
+#define H2C_SUB_CMD_ID_FW_DBG_MSG SUB_CMD_ID_FW_DBG_MSG
+#define H2C_SUB_CMD_ID_FW_SNDING_ACK SUB_CMD_ID_FW_SNDING
+#define H2C_SUB_CMD_ID_FW_FWCTRL_RPT SUB_CMD_ID_FW_FWCTRL_RPT
+#define H2C_SUB_CMD_ID_H2C_LOOPBACK_ACK SUB_CMD_ID_H2C_LOOPBACK
+#define H2C_SUB_CMD_ID_FWCMD_LOOPBACK_ACK SUB_CMD_ID_FWCMD_LOOPBACK
+#define H2C_CMD_ID_CFG_PARAM_ACK 0XFF
+#define H2C_CMD_ID_BT_COEX_ACK 0XFF
+#define H2C_CMD_ID_DUMP_PHYSICAL_EFUSE_ACK 0XFF
+#define H2C_CMD_ID_UPDATE_PKT_ACK 0XFF
+#define H2C_CMD_ID_UPDATE_DATAPACK_ACK 0XFF
+#define H2C_CMD_ID_RUN_DATAPACK_ACK 0XFF
+#define H2C_CMD_ID_CH_SWITCH_ACK 0XFF
+#define H2C_CMD_ID_IQK_ACK 0XFF
+#define H2C_CMD_ID_PWR_TRK_ACK 0XFF
+#define H2C_CMD_ID_PSD_ACK 0XFF
+#define H2C_CMD_ID_FW_MEM_DUMP_ACK 0XFF
+#define H2C_CMD_ID_CCX_RPT 0XFF
+#define H2C_CMD_ID_FW_DBG_MSG 0XFF
+#define H2C_CMD_ID_FW_SNDING_ACK 0XFF
+#define H2C_CMD_ID_FW_FWCTRL_RPT 0XFF
+#define H2C_CMD_ID_H2C_LOOPBACK_ACK 0XFF
+#define H2C_CMD_ID_FWCMD_LOOPBACK_ACK 0XFF
+#define C2H_HDR_GET_CMD_ID(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X00, 0, 8)
+#define C2H_HDR_SET_CMD_ID(c2h_pkt, value)                                     \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 0, 8, value)
+#define C2H_HDR_SET_CMD_ID_NO_CLR(c2h_pkt, value)                              \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 0, 8, value)
+#define C2H_HDR_GET_SEQ(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X00, 8, 8)
+#define C2H_HDR_SET_SEQ(c2h_pkt, value)                                        \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 8, 8, value)
+#define C2H_HDR_SET_SEQ_NO_CLR(c2h_pkt, value)                                 \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 8, 8, value)
+#define C2H_HDR_GET_C2H_SUB_CMD_ID(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X00, 16, 8)
+#define C2H_HDR_SET_C2H_SUB_CMD_ID(c2h_pkt, value)                             \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 16, 8, value)
+#define C2H_HDR_SET_C2H_SUB_CMD_ID_NO_CLR(c2h_pkt, value)                      \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 16, 8, value)
+#define C2H_HDR_GET_LEN(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X00, 24, 8)
+#define C2H_HDR_SET_LEN(c2h_pkt, value)                                        \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 24, 8, value)
+#define C2H_HDR_SET_LEN_NO_CLR(c2h_pkt, value)                                 \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 24, 8, value)
+#define C2H_DBG_GET_DBG_MSG(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X04, 0, 8)
+#define C2H_DBG_SET_DBG_MSG(c2h_pkt, value)                                    \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X04, 0, 8, value)
+#define C2H_DBG_SET_DBG_MSG_NO_CLR(c2h_pkt, value)                             \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 0, 8, value)
+#define BT_COEX_INFO_GET_DATA_START(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X04, 0, 8)
+#define BT_COEX_INFO_SET_DATA_START(c2h_pkt, value)                            \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X04, 0, 8, value)
+#define BT_COEX_INFO_SET_DATA_START_NO_CLR(c2h_pkt, value)                     \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 0, 8, value)
+#define SCAN_STATUS_RPT_GET_H2C_RETURN_CODE(c2h_pkt)                           \
+	GET_C2H_FIELD(c2h_pkt + 0X04, 0, 8)
+#define SCAN_STATUS_RPT_SET_H2C_RETURN_CODE(c2h_pkt, value)                    \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X04, 0, 8, value)
+#define SCAN_STATUS_RPT_SET_H2C_RETURN_CODE_NO_CLR(c2h_pkt, value)             \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 0, 8, value)
+#define SCAN_STATUS_RPT_GET_H2C_SEQ(c2h_pkt)                                   \
+	GET_C2H_FIELD(c2h_pkt + 0X04, 16, 16)
+#define SCAN_STATUS_RPT_SET_H2C_SEQ(c2h_pkt, value)                            \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X04, 16, 16, value)
+#define SCAN_STATUS_RPT_SET_H2C_SEQ_NO_CLR(c2h_pkt, value)                     \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 16, 16, value)
+#define H2C_ACK_HDR_GET_H2C_RETURN_CODE(c2h_pkt)                               \
+	GET_C2H_FIELD(c2h_pkt + 0X04, 0, 8)
+#define H2C_ACK_HDR_SET_H2C_RETURN_CODE(c2h_pkt, value)                        \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X04, 0, 8, value)
+#define H2C_ACK_HDR_SET_H2C_RETURN_CODE_NO_CLR(c2h_pkt, value)                 \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 0, 8, value)
+#define H2C_ACK_HDR_GET_H2C_CMD_ID(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X04, 8, 8)
+#define H2C_ACK_HDR_SET_H2C_CMD_ID(c2h_pkt, value)                             \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X04, 8, 8, value)
+#define H2C_ACK_HDR_SET_H2C_CMD_ID_NO_CLR(c2h_pkt, value)                      \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 8, 8, value)
+#define H2C_ACK_HDR_GET_H2C_SUB_CMD_ID(c2h_pkt)                                \
+	GET_C2H_FIELD(c2h_pkt + 0X04, 16, 16)
+#define H2C_ACK_HDR_SET_H2C_SUB_CMD_ID(c2h_pkt, value)                         \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X04, 16, 16, value)
+#define H2C_ACK_HDR_SET_H2C_SUB_CMD_ID_NO_CLR(c2h_pkt, value)                  \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 16, 16, value)
+#define H2C_ACK_HDR_GET_H2C_SEQ(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X08, 0, 16)
+#define H2C_ACK_HDR_SET_H2C_SEQ(c2h_pkt, value)                                \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X08, 0, 16, value)
+#define H2C_ACK_HDR_SET_H2C_SEQ_NO_CLR(c2h_pkt, value)                         \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X08, 0, 16, value)
+#define CFG_PARAM_ACK_GET_OFFSET_ACCUMULATION(c2h_pkt)                         \
+	GET_C2H_FIELD(c2h_pkt + 0XC, 0, 32)
+#define CFG_PARAM_ACK_SET_OFFSET_ACCUMULATION(c2h_pkt, value)                  \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0XC, 0, 32, value)
+#define CFG_PARAM_ACK_SET_OFFSET_ACCUMULATION_NO_CLR(c2h_pkt, value)           \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0XC, 0, 32, value)
+#define CFG_PARAM_ACK_GET_VALUE_ACCUMULATION(c2h_pkt)                          \
+	GET_C2H_FIELD(c2h_pkt + 0X10, 0, 32)
+#define CFG_PARAM_ACK_SET_VALUE_ACCUMULATION(c2h_pkt, value)                   \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X10, 0, 32, value)
+#define CFG_PARAM_ACK_SET_VALUE_ACCUMULATION_NO_CLR(c2h_pkt, value)            \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X10, 0, 32, value)
+#define BT_COEX_ACK_GET_DATA_START(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0XC, 0, 8)
+#define BT_COEX_ACK_SET_DATA_START(c2h_pkt, value)                             \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0XC, 0, 8, value)
+#define BT_COEX_ACK_SET_DATA_START_NO_CLR(c2h_pkt, value)                      \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0XC, 0, 8, value)
+#define PSD_DATA_GET_SEGMENT_ID(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X04, 0, 7)
+#define PSD_DATA_SET_SEGMENT_ID(c2h_pkt, value)                                \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X04, 0, 7, value)
+#define PSD_DATA_SET_SEGMENT_ID_NO_CLR(c2h_pkt, value)                         \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 0, 7, value)
+#define PSD_DATA_GET_END_SEGMENT(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X04, 7, 1)
+#define PSD_DATA_SET_END_SEGMENT(c2h_pkt, value)                               \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X04, 7, 1, value)
+#define PSD_DATA_SET_END_SEGMENT_NO_CLR(c2h_pkt, value)                        \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 7, 1, value)
+#define PSD_DATA_GET_SEGMENT_SIZE(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X04, 8, 8)
+#define PSD_DATA_SET_SEGMENT_SIZE(c2h_pkt, value)                              \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X04, 8, 8, value)
+#define PSD_DATA_SET_SEGMENT_SIZE_NO_CLR(c2h_pkt, value)                       \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 8, 8, value)
+#define PSD_DATA_GET_TOTAL_SIZE(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X04, 16, 16)
+#define PSD_DATA_SET_TOTAL_SIZE(c2h_pkt, value)                                \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X04, 16, 16, value)
+#define PSD_DATA_SET_TOTAL_SIZE_NO_CLR(c2h_pkt, value)                         \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 16, 16, value)
+#define PSD_DATA_GET_H2C_SEQ(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X8, 0, 16)
+#define PSD_DATA_SET_H2C_SEQ(c2h_pkt, value)                                   \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X8, 0, 16, value)
+#define PSD_DATA_SET_H2C_SEQ_NO_CLR(c2h_pkt, value)                            \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X8, 0, 16, value)
+#define PSD_DATA_GET_DATA_START(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X8, 16, 8)
+#define PSD_DATA_SET_DATA_START(c2h_pkt, value)                                \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X8, 16, 8, value)
+#define PSD_DATA_SET_DATA_START_NO_CLR(c2h_pkt, value)                         \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X8, 16, 8, value)
+#define EFUSE_DATA_GET_SEGMENT_ID(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X04, 0, 7)
+#define EFUSE_DATA_SET_SEGMENT_ID(c2h_pkt, value)                              \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X04, 0, 7, value)
+#define EFUSE_DATA_SET_SEGMENT_ID_NO_CLR(c2h_pkt, value)                       \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 0, 7, value)
+#define EFUSE_DATA_GET_END_SEGMENT(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X04, 7, 1)
+#define EFUSE_DATA_SET_END_SEGMENT(c2h_pkt, value)                             \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X04, 7, 1, value)
+#define EFUSE_DATA_SET_END_SEGMENT_NO_CLR(c2h_pkt, value)                      \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 7, 1, value)
+#define EFUSE_DATA_GET_SEGMENT_SIZE(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X04, 8, 8)
+#define EFUSE_DATA_SET_SEGMENT_SIZE(c2h_pkt, value)                            \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X04, 8, 8, value)
+#define EFUSE_DATA_SET_SEGMENT_SIZE_NO_CLR(c2h_pkt, value)                     \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 8, 8, value)
+#define EFUSE_DATA_GET_TOTAL_SIZE(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X04, 16, 16)
+#define EFUSE_DATA_SET_TOTAL_SIZE(c2h_pkt, value)                              \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X04, 16, 16, value)
+#define EFUSE_DATA_SET_TOTAL_SIZE_NO_CLR(c2h_pkt, value)                       \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 16, 16, value)
+#define EFUSE_DATA_GET_H2C_SEQ(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X8, 0, 16)
+#define EFUSE_DATA_SET_H2C_SEQ(c2h_pkt, value)                                 \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X8, 0, 16, value)
+#define EFUSE_DATA_SET_H2C_SEQ_NO_CLR(c2h_pkt, value)                          \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X8, 0, 16, value)
+#define EFUSE_DATA_GET_DATA_START(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X8, 16, 8)
+#define EFUSE_DATA_SET_DATA_START(c2h_pkt, value)                              \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X8, 16, 8, value)
+#define EFUSE_DATA_SET_DATA_START_NO_CLR(c2h_pkt, value)                       \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X8, 16, 8, value)
+#define IQK_DATA_GET_SEGMENT_ID(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X04, 0, 7)
+#define IQK_DATA_SET_SEGMENT_ID(c2h_pkt, value)                                \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X04, 0, 7, value)
+#define IQK_DATA_SET_SEGMENT_ID_NO_CLR(c2h_pkt, value)                         \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 0, 7, value)
+#define IQK_DATA_GET_END_SEGMENT(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X04, 7, 1)
+#define IQK_DATA_SET_END_SEGMENT(c2h_pkt, value)                               \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X04, 7, 1, value)
+#define IQK_DATA_SET_END_SEGMENT_NO_CLR(c2h_pkt, value)                        \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 7, 1, value)
+#define IQK_DATA_GET_SEGMENT_SIZE(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X04, 8, 8)
+#define IQK_DATA_SET_SEGMENT_SIZE(c2h_pkt, value)                              \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X04, 8, 8, value)
+#define IQK_DATA_SET_SEGMENT_SIZE_NO_CLR(c2h_pkt, value)                       \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 8, 8, value)
+#define IQK_DATA_GET_TOTAL_SIZE(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X04, 16, 16)
+#define IQK_DATA_SET_TOTAL_SIZE(c2h_pkt, value)                                \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X04, 16, 16, value)
+#define IQK_DATA_SET_TOTAL_SIZE_NO_CLR(c2h_pkt, value)                         \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 16, 16, value)
+#define IQK_DATA_GET_H2C_SEQ(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X8, 0, 16)
+#define IQK_DATA_SET_H2C_SEQ(c2h_pkt, value)                                   \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X8, 0, 16, value)
+#define IQK_DATA_SET_H2C_SEQ_NO_CLR(c2h_pkt, value)                            \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X8, 0, 16, value)
+#define IQK_DATA_GET_DATA_START(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X8, 16, 8)
+#define IQK_DATA_SET_DATA_START(c2h_pkt, value)                                \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X8, 16, 8, value)
+#define IQK_DATA_SET_DATA_START_NO_CLR(c2h_pkt, value)                         \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X8, 16, 8, value)
+#define CCX_RPT_GET_POLLUTED(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X4, 0, 1)
+#define CCX_RPT_SET_POLLUTED(c2h_pkt, value)                                   \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X4, 0, 1, value)
+#define CCX_RPT_SET_POLLUTED_NO_CLR(c2h_pkt, value)                            \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X4, 0, 1, value)
+#define CCX_RPT_GET_RPT_SEL(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X4, 5, 3)
+#define CCX_RPT_SET_RPT_SEL(c2h_pkt, value)                                    \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X4, 5, 3, value)
+#define CCX_RPT_SET_RPT_SEL_NO_CLR(c2h_pkt, value)                             \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X4, 5, 3, value)
+#define CCX_RPT_GET_QSEL(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X4, 8, 5)
+#define CCX_RPT_SET_QSEL(c2h_pkt, value)                                       \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X4, 8, 5, value)
+#define CCX_RPT_SET_QSEL_NO_CLR(c2h_pkt, value)                                \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X4, 8, 5, value)
+#define CCX_RPT_GET_MISSED_RPT_NUM(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X4, 13, 3)
+#define CCX_RPT_SET_MISSED_RPT_NUM(c2h_pkt, value)                             \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X4, 13, 3, value)
+#define CCX_RPT_SET_MISSED_RPT_NUM_NO_CLR(c2h_pkt, value)                      \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X4, 13, 3, value)
+#define CCX_RPT_GET_MACID(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X4, 16, 7)
+#define CCX_RPT_SET_MACID(c2h_pkt, value)                                      \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X4, 16, 7, value)
+#define CCX_RPT_SET_MACID_NO_CLR(c2h_pkt, value)                               \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X4, 16, 7, value)
+#define CCX_RPT_GET_INITIAL_DATA_RATE(c2h_pkt)                                 \
+	GET_C2H_FIELD(c2h_pkt + 0X4, 24, 7)
+#define CCX_RPT_SET_INITIAL_DATA_RATE(c2h_pkt, value)                          \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X4, 24, 7, value)
+#define CCX_RPT_SET_INITIAL_DATA_RATE_NO_CLR(c2h_pkt, value)                   \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X4, 24, 7, value)
+#define CCX_RPT_GET_INITIAL_SGI(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X4, 31, 1)
+#define CCX_RPT_SET_INITIAL_SGI(c2h_pkt, value)                                \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X4, 31, 1, value)
+#define CCX_RPT_SET_INITIAL_SGI_NO_CLR(c2h_pkt, value)                         \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X4, 31, 1, value)
+#define CCX_RPT_GET_QUEUE_TIME(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X8, 0, 16)
+#define CCX_RPT_SET_QUEUE_TIME(c2h_pkt, value)                                 \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X8, 0, 16, value)
+#define CCX_RPT_SET_QUEUE_TIME_NO_CLR(c2h_pkt, value)                          \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X8, 0, 16, value)
+#define CCX_RPT_GET_SW_DEFINE_BYTE0(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X8, 16, 8)
+#define CCX_RPT_SET_SW_DEFINE_BYTE0(c2h_pkt, value)                            \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X8, 16, 8, value)
+#define CCX_RPT_SET_SW_DEFINE_BYTE0_NO_CLR(c2h_pkt, value)                     \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X8, 16, 8, value)
+#define CCX_RPT_GET_RTS_RETRY_COUNT(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X8, 24, 4)
+#define CCX_RPT_SET_RTS_RETRY_COUNT(c2h_pkt, value)                            \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X8, 24, 4, value)
+#define CCX_RPT_SET_RTS_RETRY_COUNT_NO_CLR(c2h_pkt, value)                     \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X8, 24, 4, value)
+#define CCX_RPT_GET_BMC(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X8, 29, 1)
+#define CCX_RPT_SET_BMC(c2h_pkt, value)                                        \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X8, 29, 1, value)
+#define CCX_RPT_SET_BMC_NO_CLR(c2h_pkt, value)                                 \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X8, 29, 1, value)
+#define CCX_RPT_GET_TX_STATE(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X8, 30, 2)
+#define CCX_RPT_SET_TX_STATE(c2h_pkt, value)                                   \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X8, 30, 2, value)
+#define CCX_RPT_SET_TX_STATE_NO_CLR(c2h_pkt, value)                            \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X8, 30, 2, value)
+#define CCX_RPT_GET_DATA_RETRY_COUNT(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0XC, 0, 6)
+#define CCX_RPT_SET_DATA_RETRY_COUNT(c2h_pkt, value)                           \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0XC, 0, 6, value)
+#define CCX_RPT_SET_DATA_RETRY_COUNT_NO_CLR(c2h_pkt, value)                    \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0XC, 0, 6, value)
+#define CCX_RPT_GET_FINAL_DATA_RATE(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0XC, 8, 7)
+#define CCX_RPT_SET_FINAL_DATA_RATE(c2h_pkt, value)                            \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0XC, 8, 7, value)
+#define CCX_RPT_SET_FINAL_DATA_RATE_NO_CLR(c2h_pkt, value)                     \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0XC, 8, 7, value)
+#define CCX_RPT_GET_FINAL_SGI(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0XC, 15, 1)
+#define CCX_RPT_SET_FINAL_SGI(c2h_pkt, value)                                  \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0XC, 15, 1, value)
+#define CCX_RPT_SET_FINAL_SGI_NO_CLR(c2h_pkt, value)                           \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0XC, 15, 1, value)
+#define CCX_RPT_GET_RF_CH_NUM(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0XC, 16, 10)
+#define CCX_RPT_SET_RF_CH_NUM(c2h_pkt, value)                                  \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0XC, 16, 10, value)
+#define CCX_RPT_SET_RF_CH_NUM_NO_CLR(c2h_pkt, value)                           \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0XC, 16, 10, value)
+#define CCX_RPT_GET_SC(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0XC, 26, 4)
+#define CCX_RPT_SET_SC(c2h_pkt, value)                                         \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0XC, 26, 4, value)
+#define CCX_RPT_SET_SC_NO_CLR(c2h_pkt, value)                                  \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0XC, 26, 4, value)
+#define CCX_RPT_GET_BW(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0XC, 30, 2)
+#define CCX_RPT_SET_BW(c2h_pkt, value)                                         \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0XC, 30, 2, value)
+#define CCX_RPT_SET_BW_NO_CLR(c2h_pkt, value)                                  \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0XC, 30, 2, value)
+#define FW_DBG_MSG_GET_CMD_ID(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X00, 0, 8)
+#define FW_DBG_MSG_SET_CMD_ID(c2h_pkt, value)                                  \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 0, 8, value)
+#define FW_DBG_MSG_SET_CMD_ID_NO_CLR(c2h_pkt, value)                           \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 0, 8, value)
+#define FW_DBG_MSG_GET_C2H_SUB_CMD_ID(c2h_pkt)                                 \
+	GET_C2H_FIELD(c2h_pkt + 0X00, 16, 8)
+#define FW_DBG_MSG_SET_C2H_SUB_CMD_ID(c2h_pkt, value)                          \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 16, 8, value)
+#define FW_DBG_MSG_SET_C2H_SUB_CMD_ID_NO_CLR(c2h_pkt, value)                   \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 16, 8, value)
+#define FW_DBG_MSG_GET_FULL(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X00, 24, 1)
+#define FW_DBG_MSG_SET_FULL(c2h_pkt, value)                                    \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 24, 1, value)
+#define FW_DBG_MSG_SET_FULL_NO_CLR(c2h_pkt, value)                             \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 24, 1, value)
+#define FW_DBG_MSG_GET_OWN(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X00, 31, 1)
+#define FW_DBG_MSG_SET_OWN(c2h_pkt, value)                                     \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 31, 1, value)
+#define FW_DBG_MSG_SET_OWN_NO_CLR(c2h_pkt, value)                              \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 31, 1, value)
+#define FW_FWCTRL_RPT_GET_EVT_TYPE(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X00, 0, 8)
+#define FW_FWCTRL_RPT_SET_EVT_TYPE(c2h_pkt, value)                             \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 0, 8, value)
+#define FW_FWCTRL_RPT_SET_EVT_TYPE_NO_CLR(c2h_pkt, value)                      \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 0, 8, value)
+#define FW_FWCTRL_RPT_GET_LENGTH(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X00, 8, 8)
+#define FW_FWCTRL_RPT_SET_LENGTH(c2h_pkt, value)                               \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 8, 8, value)
+#define FW_FWCTRL_RPT_SET_LENGTH_NO_CLR(c2h_pkt, value)                        \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 8, 8, value)
+#define FW_FWCTRL_RPT_GET_SEQ_NUM(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X00, 16, 8)
+#define FW_FWCTRL_RPT_SET_SEQ_NUM(c2h_pkt, value)                              \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 16, 8, value)
+#define FW_FWCTRL_RPT_SET_SEQ_NUM_NO_CLR(c2h_pkt, value)                       \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 16, 8, value)
+#define FW_FWCTRL_RPT_GET_IS_ACK(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X00, 24, 1)
+#define FW_FWCTRL_RPT_SET_IS_ACK(c2h_pkt, value)                               \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 24, 1, value)
+#define FW_FWCTRL_RPT_SET_IS_ACK_NO_CLR(c2h_pkt, value)                        \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 24, 1, value)
+#define FW_FWCTRL_RPT_GET_MORE_CONTENT(c2h_pkt)                                \
+	GET_C2H_FIELD(c2h_pkt + 0X00, 25, 1)
+#define FW_FWCTRL_RPT_SET_MORE_CONTENT(c2h_pkt, value)                         \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 25, 1, value)
+#define FW_FWCTRL_RPT_SET_MORE_CONTENT_NO_CLR(c2h_pkt, value)                  \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 25, 1, value)
+#define FW_FWCTRL_RPT_GET_CONTENT_IDX(c2h_pkt)                                 \
+	GET_C2H_FIELD(c2h_pkt + 0X00, 26, 6)
+#define FW_FWCTRL_RPT_SET_CONTENT_IDX(c2h_pkt, value)                          \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 26, 6, value)
+#define FW_FWCTRL_RPT_SET_CONTENT_IDX_NO_CLR(c2h_pkt, value)                   \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 26, 6, value)
+#define FW_FWCTRL_RPT_GET_CLASS_ID(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X04, 0, 8)
+#define FW_FWCTRL_RPT_SET_CLASS_ID(c2h_pkt, value)                             \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X04, 0, 8, value)
+#define FW_FWCTRL_RPT_SET_CLASS_ID_NO_CLR(c2h_pkt, value)                      \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 0, 8, value)
+#define FW_FWCTRL_RPT_GET_CONTENT(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X04, 16, 16)
+#define FW_FWCTRL_RPT_SET_CONTENT(c2h_pkt, value)                              \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X04, 16, 16, value)
+#define FW_FWCTRL_RPT_SET_CONTENT_NO_CLR(c2h_pkt, value)                       \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 16, 16, value)
+#define H2C_LOOPBACK_ACK_GET_H2C_BYTE_0(c2h_pkt)                               \
+	GET_C2H_FIELD(c2h_pkt + 0X04, 0, 8)
+#define H2C_LOOPBACK_ACK_SET_H2C_BYTE_0(c2h_pkt, value)                        \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X04, 0, 8, value)
+#define H2C_LOOPBACK_ACK_SET_H2C_BYTE_0_NO_CLR(c2h_pkt, value)                 \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 0, 8, value)
+#define H2C_LOOPBACK_ACK_GET_H2C_BYTE_1(c2h_pkt)                               \
+	GET_C2H_FIELD(c2h_pkt + 0X04, 8, 8)
+#define H2C_LOOPBACK_ACK_SET_H2C_BYTE_1(c2h_pkt, value)                        \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X04, 8, 8, value)
+#define H2C_LOOPBACK_ACK_SET_H2C_BYTE_1_NO_CLR(c2h_pkt, value)                 \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 8, 8, value)
+#define H2C_LOOPBACK_ACK_GET_H2C_BYTE_2(c2h_pkt)                               \
+	GET_C2H_FIELD(c2h_pkt + 0X04, 16, 8)
+#define H2C_LOOPBACK_ACK_SET_H2C_BYTE_2(c2h_pkt, value)                        \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X04, 16, 8, value)
+#define H2C_LOOPBACK_ACK_SET_H2C_BYTE_2_NO_CLR(c2h_pkt, value)                 \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 16, 8, value)
+#define H2C_LOOPBACK_ACK_GET_H2C_BYTE_3(c2h_pkt)                               \
+	GET_C2H_FIELD(c2h_pkt + 0X04, 24, 8)
+#define H2C_LOOPBACK_ACK_SET_H2C_BYTE_3(c2h_pkt, value)                        \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X04, 24, 8, value)
+#define H2C_LOOPBACK_ACK_SET_H2C_BYTE_3_NO_CLR(c2h_pkt, value)                 \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 24, 8, value)
+#define H2C_LOOPBACK_ACK_GET_H2C_BYTE_4(c2h_pkt)                               \
+	GET_C2H_FIELD(c2h_pkt + 0X8, 0, 8)
+#define H2C_LOOPBACK_ACK_SET_H2C_BYTE_4(c2h_pkt, value)                        \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X8, 0, 8, value)
+#define H2C_LOOPBACK_ACK_SET_H2C_BYTE_4_NO_CLR(c2h_pkt, value)                 \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X8, 0, 8, value)
+#define H2C_LOOPBACK_ACK_GET_H2C_BYTE_5(c2h_pkt)                               \
+	GET_C2H_FIELD(c2h_pkt + 0X8, 8, 8)
+#define H2C_LOOPBACK_ACK_SET_H2C_BYTE_5(c2h_pkt, value)                        \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X8, 8, 8, value)
+#define H2C_LOOPBACK_ACK_SET_H2C_BYTE_5_NO_CLR(c2h_pkt, value)                 \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X8, 8, 8, value)
+#define H2C_LOOPBACK_ACK_GET_H2C_BYTE_6(c2h_pkt)                               \
+	GET_C2H_FIELD(c2h_pkt + 0X8, 16, 8)
+#define H2C_LOOPBACK_ACK_SET_H2C_BYTE_6(c2h_pkt, value)                        \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X8, 16, 8, value)
+#define H2C_LOOPBACK_ACK_SET_H2C_BYTE_6_NO_CLR(c2h_pkt, value)                 \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X8, 16, 8, value)
+#define H2C_LOOPBACK_ACK_GET_H2C_BYTE_7(c2h_pkt)                               \
+	GET_C2H_FIELD(c2h_pkt + 0X8, 24, 8)
+#define H2C_LOOPBACK_ACK_SET_H2C_BYTE_7(c2h_pkt, value)                        \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X8, 24, 8, value)
+#define H2C_LOOPBACK_ACK_SET_H2C_BYTE_7_NO_CLR(c2h_pkt, value)                 \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X8, 24, 8, value)
+#define FWCMD_LOOPBACK_ACK_GET_H2C_BYTE_0(c2h_pkt)                             \
+	GET_C2H_FIELD(c2h_pkt + 0X04, 0, 8)
+#define FWCMD_LOOPBACK_ACK_SET_H2C_BYTE_0(c2h_pkt, value)                      \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X04, 0, 8, value)
+#define FWCMD_LOOPBACK_ACK_SET_H2C_BYTE_0_NO_CLR(c2h_pkt, value)               \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 0, 8, value)
+#define FWCMD_LOOPBACK_ACK_GET_H2C_BYTE_1(c2h_pkt)                             \
+	GET_C2H_FIELD(c2h_pkt + 0X04, 8, 8)
+#define FWCMD_LOOPBACK_ACK_SET_H2C_BYTE_1(c2h_pkt, value)                      \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X04, 8, 8, value)
+#define FWCMD_LOOPBACK_ACK_SET_H2C_BYTE_1_NO_CLR(c2h_pkt, value)               \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 8, 8, value)
+#define FWCMD_LOOPBACK_ACK_GET_H2C_BYTE_2(c2h_pkt)                             \
+	GET_C2H_FIELD(c2h_pkt + 0X04, 16, 8)
+#define FWCMD_LOOPBACK_ACK_SET_H2C_BYTE_2(c2h_pkt, value)                      \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X04, 16, 8, value)
+#define FWCMD_LOOPBACK_ACK_SET_H2C_BYTE_2_NO_CLR(c2h_pkt, value)               \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 16, 8, value)
+#define FWCMD_LOOPBACK_ACK_GET_H2C_BYTE_3(c2h_pkt)                             \
+	GET_C2H_FIELD(c2h_pkt + 0X04, 24, 8)
+#define FWCMD_LOOPBACK_ACK_SET_H2C_BYTE_3(c2h_pkt, value)                      \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X04, 24, 8, value)
+#define FWCMD_LOOPBACK_ACK_SET_H2C_BYTE_3_NO_CLR(c2h_pkt, value)               \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 24, 8, value)
+#define FWCMD_LOOPBACK_ACK_GET_H2C_BYTE_4(c2h_pkt)                             \
+	GET_C2H_FIELD(c2h_pkt + 0X8, 0, 8)
+#define FWCMD_LOOPBACK_ACK_SET_H2C_BYTE_4(c2h_pkt, value)                      \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X8, 0, 8, value)
+#define FWCMD_LOOPBACK_ACK_SET_H2C_BYTE_4_NO_CLR(c2h_pkt, value)               \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X8, 0, 8, value)
+#define FWCMD_LOOPBACK_ACK_GET_H2C_BYTE_5(c2h_pkt)                             \
+	GET_C2H_FIELD(c2h_pkt + 0X8, 8, 8)
+#define FWCMD_LOOPBACK_ACK_SET_H2C_BYTE_5(c2h_pkt, value)                      \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X8, 8, 8, value)
+#define FWCMD_LOOPBACK_ACK_SET_H2C_BYTE_5_NO_CLR(c2h_pkt, value)               \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X8, 8, 8, value)
+#define FWCMD_LOOPBACK_ACK_GET_H2C_BYTE_6(c2h_pkt)                             \
+	GET_C2H_FIELD(c2h_pkt + 0X8, 16, 8)
+#define FWCMD_LOOPBACK_ACK_SET_H2C_BYTE_6(c2h_pkt, value)                      \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X8, 16, 8, value)
+#define FWCMD_LOOPBACK_ACK_SET_H2C_BYTE_6_NO_CLR(c2h_pkt, value)               \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X8, 16, 8, value)
+#define FWCMD_LOOPBACK_ACK_GET_H2C_BYTE_7(c2h_pkt)                             \
+	GET_C2H_FIELD(c2h_pkt + 0X8, 24, 8)
+#define FWCMD_LOOPBACK_ACK_SET_H2C_BYTE_7(c2h_pkt, value)                      \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X8, 24, 8, value)
+#define FWCMD_LOOPBACK_ACK_SET_H2C_BYTE_7_NO_CLR(c2h_pkt, value)               \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X8, 24, 8, value)
+#define FW_TBTT_RPT_GET_PORT_NUMBER(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X04, 0, 8)
+#define FW_TBTT_RPT_SET_PORT_NUMBER(c2h_pkt, value)                            \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X04, 0, 8, value)
+#define FW_TBTT_RPT_SET_PORT_NUMBER_NO_CLR(c2h_pkt, value)                     \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 0, 8, value)
+#endif
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/halmac/halmac_fw_offload_c2h_nic.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/halmac/halmac_fw_offload_c2h_nic.h
--- linux-5.6.3/3rdparty/rtl8821ce/hal/halmac/halmac_fw_offload_c2h_nic.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/halmac/halmac_fw_offload_c2h_nic.h	2020-04-10 16:35:06.811659835 +0300
@@ -0,0 +1,379 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ ******************************************************************************/
+
+#ifndef _HAL_FWOFFLOADC2HFORMAT_H2C_C2H_NIC_H_
+#define _HAL_FWOFFLOADC2HFORMAT_H2C_C2H_NIC_H_
+#define C2H_SUB_CMD_ID_C2H_DBG 0X00
+#define C2H_SUB_CMD_ID_BT_COEX_INFO 0X02
+#define C2H_SUB_CMD_ID_SCAN_STATUS_RPT 0X03
+#define C2H_SUB_CMD_ID_H2C_ACK_HDR 0X01
+#define C2H_SUB_CMD_ID_CFG_PARAM_ACK 0X01
+#define C2H_SUB_CMD_ID_BT_COEX_ACK 0X01
+#define C2H_SUB_CMD_ID_DUMP_PHYSICAL_EFUSE_ACK 0X01
+#define C2H_SUB_CMD_ID_UPDATE_PKT_ACK 0X01
+#define C2H_SUB_CMD_ID_UPDATE_DATAPACK_ACK 0X01
+#define C2H_SUB_CMD_ID_RUN_DATAPACK_ACK 0X01
+#define C2H_SUB_CMD_ID_CH_SWITCH_ACK 0X01
+#define C2H_SUB_CMD_ID_IQK_ACK 0X01
+#define C2H_SUB_CMD_ID_PWR_TRK_ACK 0X01
+#define C2H_SUB_CMD_ID_PSD_ACK 0X01
+#define C2H_SUB_CMD_ID_FW_MEM_DUMP_ACK 0X01
+#define C2H_SUB_CMD_ID_PSD_DATA 0X04
+#define C2H_SUB_CMD_ID_EFUSE_DATA 0X05
+#define C2H_SUB_CMD_ID_IQK_DATA 0X06
+#define C2H_SUB_CMD_ID_C2H_PKT_FTM_DBG 0X07
+#define C2H_SUB_CMD_ID_C2H_PKT_FTM_2_DBG 0X08
+#define C2H_SUB_CMD_ID_C2H_PKT_FTM_3_DBG 0X09
+#define C2H_SUB_CMD_ID_C2H_PKT_FTM_4_DBG 0X0A
+#define C2H_SUB_CMD_ID_FTMACKRPT_HDL_DBG 0X0B
+#define C2H_SUB_CMD_ID_FTMC2H_RPT 0X0C
+#define C2H_SUB_CMD_ID_DRVFTMC2H_RPT 0X0D
+#define C2H_SUB_CMD_ID_C2H_PKT_FTM_5_DBG 0X0E
+#define C2H_SUB_CMD_ID_CCX_RPT 0X0F
+#define C2H_SUB_CMD_ID_C2H_PKT_NAN_RPT 0X10
+#define C2H_SUB_CMD_ID_C2H_PKT_ATM_RPT 0X11
+#define C2H_SUB_CMD_ID_C2H_PKT_FTMSESSION_END 0X1C
+#define C2H_SUB_CMD_ID_C2H_PKT_DETECT_THERMAL 0X1D
+#define C2H_SUB_CMD_ID_FW_DBG_MSG 0XFF
+#define C2H_SUB_CMD_ID_FW_SNDING_ACK 0X01
+#define C2H_SUB_CMD_ID_FW_FWCTRL_RPT 0X1F
+#define C2H_SUB_CMD_ID_H2C_LOOPBACK_ACK 0X20
+#define C2H_SUB_CMD_ID_FWCMD_LOOPBACK_ACK 0X21
+#define C2H_SUB_CMD_ID_FW_TBTT_RPT 0X23
+#define H2C_SUB_CMD_ID_CFG_PARAM_ACK SUB_CMD_ID_CFG_PARAM
+#define H2C_SUB_CMD_ID_BT_COEX_ACK SUB_CMD_ID_BT_COEX
+#define H2C_SUB_CMD_ID_DUMP_PHYSICAL_EFUSE_ACK SUB_CMD_ID_DUMP_PHYSICAL_EFUSE
+#define H2C_SUB_CMD_ID_UPDATE_PKT_ACK SUB_CMD_ID_UPDATE_PKT
+#define H2C_SUB_CMD_ID_UPDATE_DATAPACK_ACK SUB_CMD_ID_UPDATE_DATAPACK
+#define H2C_SUB_CMD_ID_RUN_DATAPACK_ACK SUB_CMD_ID_RUN_DATAPACK
+#define H2C_SUB_CMD_ID_CH_SWITCH_ACK SUB_CMD_ID_CH_SWITCH
+#define H2C_SUB_CMD_ID_IQK_ACK SUB_CMD_ID_IQK
+#define H2C_SUB_CMD_ID_PWR_TRK_ACK SUB_CMD_ID_PWR_TRK
+#define H2C_SUB_CMD_ID_PSD_ACK SUB_CMD_ID_PSD
+#define H2C_SUB_CMD_ID_FW_MEM_DUMP_ACK SUB_CMD_ID_FW_MEM_DUMP
+#define H2C_SUB_CMD_ID_CCX_RPT SUB_CMD_ID_CCX_RPT
+#define H2C_SUB_CMD_ID_FW_DBG_MSG SUB_CMD_ID_FW_DBG_MSG
+#define H2C_SUB_CMD_ID_FW_SNDING_ACK SUB_CMD_ID_FW_SNDING
+#define H2C_SUB_CMD_ID_FW_FWCTRL_RPT SUB_CMD_ID_FW_FWCTRL_RPT
+#define H2C_SUB_CMD_ID_H2C_LOOPBACK_ACK SUB_CMD_ID_H2C_LOOPBACK
+#define H2C_SUB_CMD_ID_FWCMD_LOOPBACK_ACK SUB_CMD_ID_FWCMD_LOOPBACK
+#define H2C_CMD_ID_CFG_PARAM_ACK 0XFF
+#define H2C_CMD_ID_BT_COEX_ACK 0XFF
+#define H2C_CMD_ID_DUMP_PHYSICAL_EFUSE_ACK 0XFF
+#define H2C_CMD_ID_UPDATE_PKT_ACK 0XFF
+#define H2C_CMD_ID_UPDATE_DATAPACK_ACK 0XFF
+#define H2C_CMD_ID_RUN_DATAPACK_ACK 0XFF
+#define H2C_CMD_ID_CH_SWITCH_ACK 0XFF
+#define H2C_CMD_ID_IQK_ACK 0XFF
+#define H2C_CMD_ID_PWR_TRK_ACK 0XFF
+#define H2C_CMD_ID_PSD_ACK 0XFF
+#define H2C_CMD_ID_FW_MEM_DUMP_ACK 0XFF
+#define H2C_CMD_ID_CCX_RPT 0XFF
+#define H2C_CMD_ID_FW_DBG_MSG 0XFF
+#define H2C_CMD_ID_FW_SNDING_ACK 0XFF
+#define H2C_CMD_ID_FW_FWCTRL_RPT 0XFF
+#define H2C_CMD_ID_H2C_LOOPBACK_ACK 0XFF
+#define H2C_CMD_ID_FWCMD_LOOPBACK_ACK 0XFF
+#define C2H_HDR_GET_CMD_ID(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 0, 8)
+#define C2H_HDR_SET_CMD_ID(c2h_pkt, value)                                     \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 0, 8, value)
+#define C2H_HDR_GET_SEQ(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 8, 8)
+#define C2H_HDR_SET_SEQ(c2h_pkt, value)                                        \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 8, 8, value)
+#define C2H_HDR_GET_C2H_SUB_CMD_ID(c2h_pkt)                                    \
+	LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 16, 8)
+#define C2H_HDR_SET_C2H_SUB_CMD_ID(c2h_pkt, value)                             \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 16, 8, value)
+#define C2H_HDR_GET_LEN(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 24, 8)
+#define C2H_HDR_SET_LEN(c2h_pkt, value)                                        \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 24, 8, value)
+#define C2H_DBG_GET_DBG_MSG(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 0, 8)
+#define C2H_DBG_SET_DBG_MSG(c2h_pkt, value)                                    \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 0, 8, value)
+#define BT_COEX_INFO_GET_DATA_START(c2h_pkt)                                   \
+	LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 0, 8)
+#define BT_COEX_INFO_SET_DATA_START(c2h_pkt, value)                            \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 0, 8, value)
+#define SCAN_STATUS_RPT_GET_H2C_RETURN_CODE(c2h_pkt)                           \
+	LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 0, 8)
+#define SCAN_STATUS_RPT_SET_H2C_RETURN_CODE(c2h_pkt, value)                    \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 0, 8, value)
+#define SCAN_STATUS_RPT_GET_H2C_SEQ(c2h_pkt)                                   \
+	LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 16, 16)
+#define SCAN_STATUS_RPT_SET_H2C_SEQ(c2h_pkt, value)                            \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 16, 16, value)
+#define H2C_ACK_HDR_GET_H2C_RETURN_CODE(c2h_pkt)                               \
+	LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 0, 8)
+#define H2C_ACK_HDR_SET_H2C_RETURN_CODE(c2h_pkt, value)                        \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 0, 8, value)
+#define H2C_ACK_HDR_GET_H2C_CMD_ID(c2h_pkt)                                    \
+	LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 8, 8)
+#define H2C_ACK_HDR_SET_H2C_CMD_ID(c2h_pkt, value)                             \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 8, 8, value)
+#define H2C_ACK_HDR_GET_H2C_SUB_CMD_ID(c2h_pkt)                                \
+	LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 16, 16)
+#define H2C_ACK_HDR_SET_H2C_SUB_CMD_ID(c2h_pkt, value)                         \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 16, 16, value)
+#define H2C_ACK_HDR_GET_H2C_SEQ(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X08, 0, 16)
+#define H2C_ACK_HDR_SET_H2C_SEQ(c2h_pkt, value)                                \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X08, 0, 16, value)
+#define CFG_PARAM_ACK_GET_OFFSET_ACCUMULATION(c2h_pkt)                         \
+	LE_BITS_TO_4BYTE(c2h_pkt + 0XC, 0, 32)
+#define CFG_PARAM_ACK_SET_OFFSET_ACCUMULATION(c2h_pkt, value)                  \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0XC, 0, 32, value)
+#define CFG_PARAM_ACK_GET_VALUE_ACCUMULATION(c2h_pkt)                          \
+	LE_BITS_TO_4BYTE(c2h_pkt + 0X10, 0, 32)
+#define CFG_PARAM_ACK_SET_VALUE_ACCUMULATION(c2h_pkt, value)                   \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X10, 0, 32, value)
+#define BT_COEX_ACK_GET_DATA_START(c2h_pkt)                                    \
+	LE_BITS_TO_4BYTE(c2h_pkt + 0XC, 0, 8)
+#define BT_COEX_ACK_SET_DATA_START(c2h_pkt, value)                             \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0XC, 0, 8, value)
+#define PSD_DATA_GET_SEGMENT_ID(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 0, 7)
+#define PSD_DATA_SET_SEGMENT_ID(c2h_pkt, value)                                \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 0, 7, value)
+#define PSD_DATA_GET_END_SEGMENT(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 7, 1)
+#define PSD_DATA_SET_END_SEGMENT(c2h_pkt, value)                               \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 7, 1, value)
+#define PSD_DATA_GET_SEGMENT_SIZE(c2h_pkt)                                     \
+	LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 8, 8)
+#define PSD_DATA_SET_SEGMENT_SIZE(c2h_pkt, value)                              \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 8, 8, value)
+#define PSD_DATA_GET_TOTAL_SIZE(c2h_pkt)                                       \
+	LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 16, 16)
+#define PSD_DATA_SET_TOTAL_SIZE(c2h_pkt, value)                                \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 16, 16, value)
+#define PSD_DATA_GET_H2C_SEQ(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X8, 0, 16)
+#define PSD_DATA_SET_H2C_SEQ(c2h_pkt, value)                                   \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X8, 0, 16, value)
+#define PSD_DATA_GET_DATA_START(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X8, 16, 8)
+#define PSD_DATA_SET_DATA_START(c2h_pkt, value)                                \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X8, 16, 8, value)
+#define EFUSE_DATA_GET_SEGMENT_ID(c2h_pkt)                                     \
+	LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 0, 7)
+#define EFUSE_DATA_SET_SEGMENT_ID(c2h_pkt, value)                              \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 0, 7, value)
+#define EFUSE_DATA_GET_END_SEGMENT(c2h_pkt)                                    \
+	LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 7, 1)
+#define EFUSE_DATA_SET_END_SEGMENT(c2h_pkt, value)                             \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 7, 1, value)
+#define EFUSE_DATA_GET_SEGMENT_SIZE(c2h_pkt)                                   \
+	LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 8, 8)
+#define EFUSE_DATA_SET_SEGMENT_SIZE(c2h_pkt, value)                            \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 8, 8, value)
+#define EFUSE_DATA_GET_TOTAL_SIZE(c2h_pkt)                                     \
+	LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 16, 16)
+#define EFUSE_DATA_SET_TOTAL_SIZE(c2h_pkt, value)                              \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 16, 16, value)
+#define EFUSE_DATA_GET_H2C_SEQ(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X8, 0, 16)
+#define EFUSE_DATA_SET_H2C_SEQ(c2h_pkt, value)                                 \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X8, 0, 16, value)
+#define EFUSE_DATA_GET_DATA_START(c2h_pkt)                                     \
+	LE_BITS_TO_4BYTE(c2h_pkt + 0X8, 16, 8)
+#define EFUSE_DATA_SET_DATA_START(c2h_pkt, value)                              \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X8, 16, 8, value)
+#define IQK_DATA_GET_SEGMENT_ID(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 0, 7)
+#define IQK_DATA_SET_SEGMENT_ID(c2h_pkt, value)                                \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 0, 7, value)
+#define IQK_DATA_GET_END_SEGMENT(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 7, 1)
+#define IQK_DATA_SET_END_SEGMENT(c2h_pkt, value)                               \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 7, 1, value)
+#define IQK_DATA_GET_SEGMENT_SIZE(c2h_pkt)                                     \
+	LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 8, 8)
+#define IQK_DATA_SET_SEGMENT_SIZE(c2h_pkt, value)                              \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 8, 8, value)
+#define IQK_DATA_GET_TOTAL_SIZE(c2h_pkt)                                       \
+	LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 16, 16)
+#define IQK_DATA_SET_TOTAL_SIZE(c2h_pkt, value)                                \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 16, 16, value)
+#define IQK_DATA_GET_H2C_SEQ(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X8, 0, 16)
+#define IQK_DATA_SET_H2C_SEQ(c2h_pkt, value)                                   \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X8, 0, 16, value)
+#define IQK_DATA_GET_DATA_START(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X8, 16, 8)
+#define IQK_DATA_SET_DATA_START(c2h_pkt, value)                                \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X8, 16, 8, value)
+#define CCX_RPT_GET_POLLUTED(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X4, 0, 1)
+#define CCX_RPT_SET_POLLUTED(c2h_pkt, value)                                   \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X4, 0, 1, value)
+#define CCX_RPT_GET_RPT_SEL(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X4, 5, 3)
+#define CCX_RPT_SET_RPT_SEL(c2h_pkt, value)                                    \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X4, 5, 3, value)
+#define CCX_RPT_GET_QSEL(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X4, 8, 5)
+#define CCX_RPT_SET_QSEL(c2h_pkt, value)                                       \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X4, 8, 5, value)
+#define CCX_RPT_GET_MISSED_RPT_NUM(c2h_pkt)                                    \
+	LE_BITS_TO_4BYTE(c2h_pkt + 0X4, 13, 3)
+#define CCX_RPT_SET_MISSED_RPT_NUM(c2h_pkt, value)                             \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X4, 13, 3, value)
+#define CCX_RPT_GET_MACID(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X4, 16, 7)
+#define CCX_RPT_SET_MACID(c2h_pkt, value)                                      \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X4, 16, 7, value)
+#define CCX_RPT_GET_INITIAL_DATA_RATE(c2h_pkt)                                 \
+	LE_BITS_TO_4BYTE(c2h_pkt + 0X4, 24, 7)
+#define CCX_RPT_SET_INITIAL_DATA_RATE(c2h_pkt, value)                          \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X4, 24, 7, value)
+#define CCX_RPT_GET_INITIAL_SGI(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X4, 31, 1)
+#define CCX_RPT_SET_INITIAL_SGI(c2h_pkt, value)                                \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X4, 31, 1, value)
+#define CCX_RPT_GET_QUEUE_TIME(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X8, 0, 16)
+#define CCX_RPT_SET_QUEUE_TIME(c2h_pkt, value)                                 \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X8, 0, 16, value)
+#define CCX_RPT_GET_SW_DEFINE_BYTE0(c2h_pkt)                                   \
+	LE_BITS_TO_4BYTE(c2h_pkt + 0X8, 16, 8)
+#define CCX_RPT_SET_SW_DEFINE_BYTE0(c2h_pkt, value)                            \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X8, 16, 8, value)
+#define CCX_RPT_GET_RTS_RETRY_COUNT(c2h_pkt)                                   \
+	LE_BITS_TO_4BYTE(c2h_pkt + 0X8, 24, 4)
+#define CCX_RPT_SET_RTS_RETRY_COUNT(c2h_pkt, value)                            \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X8, 24, 4, value)
+#define CCX_RPT_GET_BMC(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X8, 29, 1)
+#define CCX_RPT_SET_BMC(c2h_pkt, value)                                        \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X8, 29, 1, value)
+#define CCX_RPT_GET_TX_STATE(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X8, 30, 2)
+#define CCX_RPT_SET_TX_STATE(c2h_pkt, value)                                   \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X8, 30, 2, value)
+#define CCX_RPT_GET_DATA_RETRY_COUNT(c2h_pkt)                                  \
+	LE_BITS_TO_4BYTE(c2h_pkt + 0XC, 0, 6)
+#define CCX_RPT_SET_DATA_RETRY_COUNT(c2h_pkt, value)                           \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0XC, 0, 6, value)
+#define CCX_RPT_GET_FINAL_DATA_RATE(c2h_pkt)                                   \
+	LE_BITS_TO_4BYTE(c2h_pkt + 0XC, 8, 7)
+#define CCX_RPT_SET_FINAL_DATA_RATE(c2h_pkt, value)                            \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0XC, 8, 7, value)
+#define CCX_RPT_GET_FINAL_SGI(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0XC, 15, 1)
+#define CCX_RPT_SET_FINAL_SGI(c2h_pkt, value)                                  \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0XC, 15, 1, value)
+#define CCX_RPT_GET_RF_CH_NUM(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0XC, 16, 10)
+#define CCX_RPT_SET_RF_CH_NUM(c2h_pkt, value)                                  \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0XC, 16, 10, value)
+#define CCX_RPT_GET_SC(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0XC, 26, 4)
+#define CCX_RPT_SET_SC(c2h_pkt, value)                                         \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0XC, 26, 4, value)
+#define CCX_RPT_GET_BW(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0XC, 30, 2)
+#define CCX_RPT_SET_BW(c2h_pkt, value)                                         \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0XC, 30, 2, value)
+#define FW_DBG_MSG_GET_CMD_ID(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 0, 8)
+#define FW_DBG_MSG_SET_CMD_ID(c2h_pkt, value)                                  \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 0, 8, value)
+#define FW_DBG_MSG_GET_C2H_SUB_CMD_ID(c2h_pkt)                                 \
+	LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 16, 8)
+#define FW_DBG_MSG_SET_C2H_SUB_CMD_ID(c2h_pkt, value)                          \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 16, 8, value)
+#define FW_DBG_MSG_GET_FULL(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 24, 1)
+#define FW_DBG_MSG_SET_FULL(c2h_pkt, value)                                    \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 24, 1, value)
+#define FW_DBG_MSG_GET_OWN(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 31, 1)
+#define FW_DBG_MSG_SET_OWN(c2h_pkt, value)                                     \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 31, 1, value)
+#define FW_FWCTRL_RPT_GET_EVT_TYPE(c2h_pkt)                                    \
+	LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 0, 8)
+#define FW_FWCTRL_RPT_SET_EVT_TYPE(c2h_pkt, value)                             \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 0, 8, value)
+#define FW_FWCTRL_RPT_GET_LENGTH(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 8, 8)
+#define FW_FWCTRL_RPT_SET_LENGTH(c2h_pkt, value)                               \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 8, 8, value)
+#define FW_FWCTRL_RPT_GET_SEQ_NUM(c2h_pkt)                                     \
+	LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 16, 8)
+#define FW_FWCTRL_RPT_SET_SEQ_NUM(c2h_pkt, value)                              \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 16, 8, value)
+#define FW_FWCTRL_RPT_GET_IS_ACK(c2h_pkt)                                      \
+	LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 24, 1)
+#define FW_FWCTRL_RPT_SET_IS_ACK(c2h_pkt, value)                               \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 24, 1, value)
+#define FW_FWCTRL_RPT_GET_MORE_CONTENT(c2h_pkt)                                \
+	LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 25, 1)
+#define FW_FWCTRL_RPT_SET_MORE_CONTENT(c2h_pkt, value)                         \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 25, 1, value)
+#define FW_FWCTRL_RPT_GET_CONTENT_IDX(c2h_pkt)                                 \
+	LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 26, 6)
+#define FW_FWCTRL_RPT_SET_CONTENT_IDX(c2h_pkt, value)                          \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 26, 6, value)
+#define FW_FWCTRL_RPT_GET_CLASS_ID(c2h_pkt)                                    \
+	LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 0, 8)
+#define FW_FWCTRL_RPT_SET_CLASS_ID(c2h_pkt, value)                             \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 0, 8, value)
+#define FW_FWCTRL_RPT_GET_CONTENT(c2h_pkt)                                     \
+	LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 16, 16)
+#define FW_FWCTRL_RPT_SET_CONTENT(c2h_pkt, value)                              \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 16, 16, value)
+#define H2C_LOOPBACK_ACK_GET_H2C_BYTE_0(c2h_pkt)                               \
+	LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 0, 8)
+#define H2C_LOOPBACK_ACK_SET_H2C_BYTE_0(c2h_pkt, value)                        \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 0, 8, value)
+#define H2C_LOOPBACK_ACK_GET_H2C_BYTE_1(c2h_pkt)                               \
+	LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 8, 8)
+#define H2C_LOOPBACK_ACK_SET_H2C_BYTE_1(c2h_pkt, value)                        \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 8, 8, value)
+#define H2C_LOOPBACK_ACK_GET_H2C_BYTE_2(c2h_pkt)                               \
+	LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 16, 8)
+#define H2C_LOOPBACK_ACK_SET_H2C_BYTE_2(c2h_pkt, value)                        \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 16, 8, value)
+#define H2C_LOOPBACK_ACK_GET_H2C_BYTE_3(c2h_pkt)                               \
+	LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 24, 8)
+#define H2C_LOOPBACK_ACK_SET_H2C_BYTE_3(c2h_pkt, value)                        \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 24, 8, value)
+#define H2C_LOOPBACK_ACK_GET_H2C_BYTE_4(c2h_pkt)                               \
+	LE_BITS_TO_4BYTE(c2h_pkt + 0X8, 0, 8)
+#define H2C_LOOPBACK_ACK_SET_H2C_BYTE_4(c2h_pkt, value)                        \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X8, 0, 8, value)
+#define H2C_LOOPBACK_ACK_GET_H2C_BYTE_5(c2h_pkt)                               \
+	LE_BITS_TO_4BYTE(c2h_pkt + 0X8, 8, 8)
+#define H2C_LOOPBACK_ACK_SET_H2C_BYTE_5(c2h_pkt, value)                        \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X8, 8, 8, value)
+#define H2C_LOOPBACK_ACK_GET_H2C_BYTE_6(c2h_pkt)                               \
+	LE_BITS_TO_4BYTE(c2h_pkt + 0X8, 16, 8)
+#define H2C_LOOPBACK_ACK_SET_H2C_BYTE_6(c2h_pkt, value)                        \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X8, 16, 8, value)
+#define H2C_LOOPBACK_ACK_GET_H2C_BYTE_7(c2h_pkt)                               \
+	LE_BITS_TO_4BYTE(c2h_pkt + 0X8, 24, 8)
+#define H2C_LOOPBACK_ACK_SET_H2C_BYTE_7(c2h_pkt, value)                        \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X8, 24, 8, value)
+#define FWCMD_LOOPBACK_ACK_GET_H2C_BYTE_0(c2h_pkt)                             \
+	LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 0, 8)
+#define FWCMD_LOOPBACK_ACK_SET_H2C_BYTE_0(c2h_pkt, value)                      \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 0, 8, value)
+#define FWCMD_LOOPBACK_ACK_GET_H2C_BYTE_1(c2h_pkt)                             \
+	LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 8, 8)
+#define FWCMD_LOOPBACK_ACK_SET_H2C_BYTE_1(c2h_pkt, value)                      \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 8, 8, value)
+#define FWCMD_LOOPBACK_ACK_GET_H2C_BYTE_2(c2h_pkt)                             \
+	LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 16, 8)
+#define FWCMD_LOOPBACK_ACK_SET_H2C_BYTE_2(c2h_pkt, value)                      \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 16, 8, value)
+#define FWCMD_LOOPBACK_ACK_GET_H2C_BYTE_3(c2h_pkt)                             \
+	LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 24, 8)
+#define FWCMD_LOOPBACK_ACK_SET_H2C_BYTE_3(c2h_pkt, value)                      \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 24, 8, value)
+#define FWCMD_LOOPBACK_ACK_GET_H2C_BYTE_4(c2h_pkt)                             \
+	LE_BITS_TO_4BYTE(c2h_pkt + 0X8, 0, 8)
+#define FWCMD_LOOPBACK_ACK_SET_H2C_BYTE_4(c2h_pkt, value)                      \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X8, 0, 8, value)
+#define FWCMD_LOOPBACK_ACK_GET_H2C_BYTE_5(c2h_pkt)                             \
+	LE_BITS_TO_4BYTE(c2h_pkt + 0X8, 8, 8)
+#define FWCMD_LOOPBACK_ACK_SET_H2C_BYTE_5(c2h_pkt, value)                      \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X8, 8, 8, value)
+#define FWCMD_LOOPBACK_ACK_GET_H2C_BYTE_6(c2h_pkt)                             \
+	LE_BITS_TO_4BYTE(c2h_pkt + 0X8, 16, 8)
+#define FWCMD_LOOPBACK_ACK_SET_H2C_BYTE_6(c2h_pkt, value)                      \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X8, 16, 8, value)
+#define FWCMD_LOOPBACK_ACK_GET_H2C_BYTE_7(c2h_pkt)                             \
+	LE_BITS_TO_4BYTE(c2h_pkt + 0X8, 24, 8)
+#define FWCMD_LOOPBACK_ACK_SET_H2C_BYTE_7(c2h_pkt, value)                      \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X8, 24, 8, value)
+#define FW_TBTT_RPT_GET_PORT_NUMBER(c2h_pkt)                                   \
+	LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 0, 8)
+#define FW_TBTT_RPT_SET_PORT_NUMBER(c2h_pkt, value)                            \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 0, 8, value)
+#endif
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/halmac/halmac_fw_offload_h2c_ap.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/halmac/halmac_fw_offload_h2c_ap.h
--- linux-5.6.3/3rdparty/rtl8821ce/hal/halmac/halmac_fw_offload_h2c_ap.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/halmac/halmac_fw_offload_h2c_ap.h	2020-04-10 16:35:06.811659835 +0300
@@ -0,0 +1,989 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ ******************************************************************************/
+
+#ifndef _HAL_FWOFFLOADH2CFORMAT_H2C_C2H_AP_H_
+#define _HAL_FWOFFLOADH2CFORMAT_H2C_C2H_AP_H_
+#define CMD_ID_FW_OFFLOAD_H2C 0XFF
+#define CMD_ID_FW_ACCESS_TEST 0XFF
+#define CMD_ID_CH_SWITCH 0XFF
+#define CMD_ID_DUMP_PHYSICAL_EFUSE 0XFF
+#define CMD_ID_UPDATE_BEACON_PARSING_INFO 0XFF
+#define CMD_ID_CFG_PARAM 0XFF
+#define CMD_ID_UPDATE_DATAPACK 0XFF
+#define CMD_ID_RUN_DATAPACK 0XFF
+#define CMD_ID_DOWNLOAD_FLASH 0XFF
+#define CMD_ID_UPDATE_PKT 0XFF
+#define CMD_ID_GENERAL_INFO 0XFF
+#define CMD_ID_IQK 0XFF
+#define CMD_ID_PWR_TRK 0XFF
+#define CMD_ID_PSD 0XFF
+#define CMD_ID_PHYDM_INFO 0XFF
+#define CMD_ID_FW_SNDING 0XFF
+#define CMD_ID_FW_FWCTRL 0XFF
+#define CMD_ID_H2C_LOOPBACK 0XFF
+#define CMD_ID_FWCMD_LOOPBACK 0XFF
+#define CMD_ID_P2PPS 0XFF
+#define CMD_ID_BT_COEX 0XFF
+#define CMD_ID_NAN_CTRL 0XFF
+#define CMD_ID_NAN_CHANNEL_PLAN_0 0XFF
+#define CMD_ID_NAN_CHANNEL_PLAN_1 0XFF
+#define CATEGORY_H2C_CMD_HEADER 0X00
+#define CATEGORY_FW_OFFLOAD_H2C 0X01
+#define CATEGORY_FW_ACCESS_TEST 0X01
+#define CATEGORY_CH_SWITCH 0X01
+#define CATEGORY_DUMP_PHYSICAL_EFUSE 0X01
+#define CATEGORY_UPDATE_BEACON_PARSING_INFO 0X01
+#define CATEGORY_CFG_PARAM 0X01
+#define CATEGORY_UPDATE_DATAPACK 0X01
+#define CATEGORY_RUN_DATAPACK 0X01
+#define CATEGORY_DOWNLOAD_FLASH 0X01
+#define CATEGORY_UPDATE_PKT 0X01
+#define CATEGORY_GENERAL_INFO 0X01
+#define CATEGORY_IQK 0X01
+#define CATEGORY_PWR_TRK 0X01
+#define CATEGORY_PSD 0X01
+#define CATEGORY_PHYDM_INFO 0X01
+#define CATEGORY_FW_SNDING 0X01
+#define CATEGORY_FW_FWCTRL 0X01
+#define CATEGORY_H2C_LOOPBACK 0X01
+#define CATEGORY_FWCMD_LOOPBACK 0X01
+#define CATEGORY_P2PPS 0X01
+#define CATEGORY_BT_COEX 0X01
+#define CATEGORY_NAN_CTRL 0X01
+#define CATEGORY_NAN_CHANNEL_PLAN_0 0X01
+#define CATEGORY_NAN_CHANNEL_PLAN_1 0X01
+#define SUB_CMD_ID_FW_ACCESS_TEST 0X00
+#define SUB_CMD_ID_CH_SWITCH 0X02
+#define SUB_CMD_ID_DUMP_PHYSICAL_EFUSE 0X03
+#define SUB_CMD_ID_UPDATE_BEACON_PARSING_INFO 0X05
+#define SUB_CMD_ID_CFG_PARAM 0X08
+#define SUB_CMD_ID_UPDATE_DATAPACK 0X09
+#define SUB_CMD_ID_RUN_DATAPACK 0X0A
+#define SUB_CMD_ID_DOWNLOAD_FLASH 0X0B
+#define SUB_CMD_ID_UPDATE_PKT 0X0C
+#define SUB_CMD_ID_GENERAL_INFO 0X0D
+#define SUB_CMD_ID_IQK 0X0E
+#define SUB_CMD_ID_PWR_TRK 0X0F
+#define SUB_CMD_ID_PSD 0X10
+#define SUB_CMD_ID_PHYDM_INFO 0X11
+#define SUB_CMD_ID_FW_SNDING 0X12
+#define SUB_CMD_ID_FW_FWCTRL 0X13
+#define SUB_CMD_ID_H2C_LOOPBACK 0X14
+#define SUB_CMD_ID_FWCMD_LOOPBACK 0X15
+#define SUB_CMD_ID_P2PPS 0X24
+#define SUB_CMD_ID_BT_COEX 0X60
+#define SUB_CMD_ID_NAN_CTRL 0XB2
+#define SUB_CMD_ID_NAN_CHANNEL_PLAN_0 0XB4
+#define SUB_CMD_ID_NAN_CHANNEL_PLAN_1 0XB5
+#define H2C_CMD_HEADER_GET_CATEGORY(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 0, 7)
+#define H2C_CMD_HEADER_SET_CATEGORY(h2c_pkt, value)                            \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 0, 7, value)
+#define H2C_CMD_HEADER_SET_CATEGORY_NO_CLR(h2c_pkt, value)                     \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 0, 7, value)
+#define H2C_CMD_HEADER_GET_ACK(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 7, 1)
+#define H2C_CMD_HEADER_SET_ACK(h2c_pkt, value)                                 \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 7, 1, value)
+#define H2C_CMD_HEADER_SET_ACK_NO_CLR(h2c_pkt, value)                          \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 7, 1, value)
+#define H2C_CMD_HEADER_GET_TOTAL_LEN(h2c_pkt)                                  \
+	GET_H2C_FIELD(h2c_pkt + 0X04, 0, 16)
+#define H2C_CMD_HEADER_SET_TOTAL_LEN(h2c_pkt, value)                           \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X04, 0, 16, value)
+#define H2C_CMD_HEADER_SET_TOTAL_LEN_NO_CLR(h2c_pkt, value)                    \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 0, 16, value)
+#define H2C_CMD_HEADER_GET_SEQ_NUM(h2c_pkt)                                    \
+	GET_H2C_FIELD(h2c_pkt + 0X04, 16, 16)
+#define H2C_CMD_HEADER_SET_SEQ_NUM(h2c_pkt, value)                             \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X04, 16, 16, value)
+#define H2C_CMD_HEADER_SET_SEQ_NUM_NO_CLR(h2c_pkt, value)                      \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 16, 16, value)
+#define FW_OFFLOAD_H2C_GET_CATEGORY(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 0, 7)
+#define FW_OFFLOAD_H2C_SET_CATEGORY(h2c_pkt, value)                            \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 0, 7, value)
+#define FW_OFFLOAD_H2C_SET_CATEGORY_NO_CLR(h2c_pkt, value)                     \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 0, 7, value)
+#define FW_OFFLOAD_H2C_GET_ACK(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 7, 1)
+#define FW_OFFLOAD_H2C_SET_ACK(h2c_pkt, value)                                 \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 7, 1, value)
+#define FW_OFFLOAD_H2C_SET_ACK_NO_CLR(h2c_pkt, value)                          \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 7, 1, value)
+#define FW_OFFLOAD_H2C_GET_CMD_ID(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 8, 8)
+#define FW_OFFLOAD_H2C_SET_CMD_ID(h2c_pkt, value)                              \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 8, 8, value)
+#define FW_OFFLOAD_H2C_SET_CMD_ID_NO_CLR(h2c_pkt, value)                       \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 8, 8, value)
+#define FW_OFFLOAD_H2C_GET_SUB_CMD_ID(h2c_pkt)                                 \
+	GET_H2C_FIELD(h2c_pkt + 0X00, 16, 16)
+#define FW_OFFLOAD_H2C_SET_SUB_CMD_ID(h2c_pkt, value)                          \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 16, 16, value)
+#define FW_OFFLOAD_H2C_SET_SUB_CMD_ID_NO_CLR(h2c_pkt, value)                   \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 16, 16, value)
+#define FW_OFFLOAD_H2C_GET_TOTAL_LEN(h2c_pkt)                                  \
+	GET_H2C_FIELD(h2c_pkt + 0X04, 0, 16)
+#define FW_OFFLOAD_H2C_SET_TOTAL_LEN(h2c_pkt, value)                           \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X04, 0, 16, value)
+#define FW_OFFLOAD_H2C_SET_TOTAL_LEN_NO_CLR(h2c_pkt, value)                    \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 0, 16, value)
+#define FW_OFFLOAD_H2C_GET_SEQ_NUM(h2c_pkt)                                    \
+	GET_H2C_FIELD(h2c_pkt + 0X04, 16, 16)
+#define FW_OFFLOAD_H2C_SET_SEQ_NUM(h2c_pkt, value)                             \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X04, 16, 16, value)
+#define FW_OFFLOAD_H2C_SET_SEQ_NUM_NO_CLR(h2c_pkt, value)                      \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 16, 16, value)
+#define FW_ACCESS_TEST_GET_ACCESS_TXFF(h2c_pkt)                                \
+	GET_H2C_FIELD(h2c_pkt + 0X08, 0, 1)
+#define FW_ACCESS_TEST_SET_ACCESS_TXFF(h2c_pkt, value)                         \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 0, 1, value)
+#define FW_ACCESS_TEST_SET_ACCESS_TXFF_NO_CLR(h2c_pkt, value)                  \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 0, 1, value)
+#define FW_ACCESS_TEST_GET_ACCESS_RXFF(h2c_pkt)                                \
+	GET_H2C_FIELD(h2c_pkt + 0X08, 1, 1)
+#define FW_ACCESS_TEST_SET_ACCESS_RXFF(h2c_pkt, value)                         \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 1, 1, value)
+#define FW_ACCESS_TEST_SET_ACCESS_RXFF_NO_CLR(h2c_pkt, value)                  \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 1, 1, value)
+#define FW_ACCESS_TEST_GET_ACCESS_FWFF(h2c_pkt)                                \
+	GET_H2C_FIELD(h2c_pkt + 0X08, 2, 1)
+#define FW_ACCESS_TEST_SET_ACCESS_FWFF(h2c_pkt, value)                         \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 2, 1, value)
+#define FW_ACCESS_TEST_SET_ACCESS_FWFF_NO_CLR(h2c_pkt, value)                  \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 2, 1, value)
+#define FW_ACCESS_TEST_GET_ACCESS_PHYFF(h2c_pkt)                               \
+	GET_H2C_FIELD(h2c_pkt + 0X08, 3, 1)
+#define FW_ACCESS_TEST_SET_ACCESS_PHYFF(h2c_pkt, value)                        \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 3, 1, value)
+#define FW_ACCESS_TEST_SET_ACCESS_PHYFF_NO_CLR(h2c_pkt, value)                 \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 3, 1, value)
+#define FW_ACCESS_TEST_GET_ACCESS_RPT_BUF(h2c_pkt)                             \
+	GET_H2C_FIELD(h2c_pkt + 0X08, 4, 1)
+#define FW_ACCESS_TEST_SET_ACCESS_RPT_BUF(h2c_pkt, value)                      \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 4, 1, value)
+#define FW_ACCESS_TEST_SET_ACCESS_RPT_BUF_NO_CLR(h2c_pkt, value)               \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 4, 1, value)
+#define FW_ACCESS_TEST_GET_ACCESS_CAM(h2c_pkt)                                 \
+	GET_H2C_FIELD(h2c_pkt + 0X08, 5, 1)
+#define FW_ACCESS_TEST_SET_ACCESS_CAM(h2c_pkt, value)                          \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 5, 1, value)
+#define FW_ACCESS_TEST_SET_ACCESS_CAM_NO_CLR(h2c_pkt, value)                   \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 5, 1, value)
+#define FW_ACCESS_TEST_GET_ACCESS_WOW_CAM(h2c_pkt)                             \
+	GET_H2C_FIELD(h2c_pkt + 0X08, 6, 1)
+#define FW_ACCESS_TEST_SET_ACCESS_WOW_CAM(h2c_pkt, value)                      \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 6, 1, value)
+#define FW_ACCESS_TEST_SET_ACCESS_WOW_CAM_NO_CLR(h2c_pkt, value)               \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 6, 1, value)
+#define FW_ACCESS_TEST_GET_ACCESS_RX_CAM(h2c_pkt)                              \
+	GET_H2C_FIELD(h2c_pkt + 0X08, 7, 1)
+#define FW_ACCESS_TEST_SET_ACCESS_RX_CAM(h2c_pkt, value)                       \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 7, 1, value)
+#define FW_ACCESS_TEST_SET_ACCESS_RX_CAM_NO_CLR(h2c_pkt, value)                \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 7, 1, value)
+#define FW_ACCESS_TEST_GET_ACCESS_BA_CAM(h2c_pkt)                              \
+	GET_H2C_FIELD(h2c_pkt + 0X08, 8, 1)
+#define FW_ACCESS_TEST_SET_ACCESS_BA_CAM(h2c_pkt, value)                       \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 8, 1, value)
+#define FW_ACCESS_TEST_SET_ACCESS_BA_CAM_NO_CLR(h2c_pkt, value)                \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 8, 1, value)
+#define FW_ACCESS_TEST_GET_ACCESS_MBSSID_CAM(h2c_pkt)                          \
+	GET_H2C_FIELD(h2c_pkt + 0X08, 9, 1)
+#define FW_ACCESS_TEST_SET_ACCESS_MBSSID_CAM(h2c_pkt, value)                   \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 9, 1, value)
+#define FW_ACCESS_TEST_SET_ACCESS_MBSSID_CAM_NO_CLR(h2c_pkt, value)            \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 9, 1, value)
+#define FW_ACCESS_TEST_GET_ACCESS_PAGE0(h2c_pkt)                               \
+	GET_H2C_FIELD(h2c_pkt + 0X08, 16, 1)
+#define FW_ACCESS_TEST_SET_ACCESS_PAGE0(h2c_pkt, value)                        \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 16, 1, value)
+#define FW_ACCESS_TEST_SET_ACCESS_PAGE0_NO_CLR(h2c_pkt, value)                 \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 16, 1, value)
+#define FW_ACCESS_TEST_GET_ACCESS_PAGE1(h2c_pkt)                               \
+	GET_H2C_FIELD(h2c_pkt + 0X08, 17, 1)
+#define FW_ACCESS_TEST_SET_ACCESS_PAGE1(h2c_pkt, value)                        \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 17, 1, value)
+#define FW_ACCESS_TEST_SET_ACCESS_PAGE1_NO_CLR(h2c_pkt, value)                 \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 17, 1, value)
+#define FW_ACCESS_TEST_GET_ACCESS_PAGE2(h2c_pkt)                               \
+	GET_H2C_FIELD(h2c_pkt + 0X08, 18, 1)
+#define FW_ACCESS_TEST_SET_ACCESS_PAGE2(h2c_pkt, value)                        \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 18, 1, value)
+#define FW_ACCESS_TEST_SET_ACCESS_PAGE2_NO_CLR(h2c_pkt, value)                 \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 18, 1, value)
+#define FW_ACCESS_TEST_GET_ACCESS_PAGE3(h2c_pkt)                               \
+	GET_H2C_FIELD(h2c_pkt + 0X08, 19, 1)
+#define FW_ACCESS_TEST_SET_ACCESS_PAGE3(h2c_pkt, value)                        \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 19, 1, value)
+#define FW_ACCESS_TEST_SET_ACCESS_PAGE3_NO_CLR(h2c_pkt, value)                 \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 19, 1, value)
+#define FW_ACCESS_TEST_GET_ACCESS_PAGE4(h2c_pkt)                               \
+	GET_H2C_FIELD(h2c_pkt + 0X08, 20, 1)
+#define FW_ACCESS_TEST_SET_ACCESS_PAGE4(h2c_pkt, value)                        \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 20, 1, value)
+#define FW_ACCESS_TEST_SET_ACCESS_PAGE4_NO_CLR(h2c_pkt, value)                 \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 20, 1, value)
+#define FW_ACCESS_TEST_GET_ACCESS_PAGE5(h2c_pkt)                               \
+	GET_H2C_FIELD(h2c_pkt + 0X08, 21, 1)
+#define FW_ACCESS_TEST_SET_ACCESS_PAGE5(h2c_pkt, value)                        \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 21, 1, value)
+#define FW_ACCESS_TEST_SET_ACCESS_PAGE5_NO_CLR(h2c_pkt, value)                 \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 21, 1, value)
+#define FW_ACCESS_TEST_GET_ACCESS_PAGE6(h2c_pkt)                               \
+	GET_H2C_FIELD(h2c_pkt + 0X08, 22, 1)
+#define FW_ACCESS_TEST_SET_ACCESS_PAGE6(h2c_pkt, value)                        \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 22, 1, value)
+#define FW_ACCESS_TEST_SET_ACCESS_PAGE6_NO_CLR(h2c_pkt, value)                 \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 22, 1, value)
+#define FW_ACCESS_TEST_GET_ACCESS_PAGE7(h2c_pkt)                               \
+	GET_H2C_FIELD(h2c_pkt + 0X08, 23, 1)
+#define FW_ACCESS_TEST_SET_ACCESS_PAGE7(h2c_pkt, value)                        \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 23, 1, value)
+#define FW_ACCESS_TEST_SET_ACCESS_PAGE7_NO_CLR(h2c_pkt, value)                 \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 23, 1, value)
+#define CH_SWITCH_GET_START(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 0, 1)
+#define CH_SWITCH_SET_START(h2c_pkt, value)                                    \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 0, 1, value)
+#define CH_SWITCH_SET_START_NO_CLR(h2c_pkt, value)                             \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 0, 1, value)
+#define CH_SWITCH_GET_DEST_CH_EN(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 1, 1)
+#define CH_SWITCH_SET_DEST_CH_EN(h2c_pkt, value)                               \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 1, 1, value)
+#define CH_SWITCH_SET_DEST_CH_EN_NO_CLR(h2c_pkt, value)                        \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 1, 1, value)
+#define CH_SWITCH_GET_ABSOLUTE_TIME(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 2, 1)
+#define CH_SWITCH_SET_ABSOLUTE_TIME(h2c_pkt, value)                            \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 2, 1, value)
+#define CH_SWITCH_SET_ABSOLUTE_TIME_NO_CLR(h2c_pkt, value)                     \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 2, 1, value)
+#define CH_SWITCH_GET_PERIODIC_OPT(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 3, 2)
+#define CH_SWITCH_SET_PERIODIC_OPT(h2c_pkt, value)                             \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 3, 2, value)
+#define CH_SWITCH_SET_PERIODIC_OPT_NO_CLR(h2c_pkt, value)                      \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 3, 2, value)
+#define CH_SWITCH_GET_INFO_LOC(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 8, 8)
+#define CH_SWITCH_SET_INFO_LOC(h2c_pkt, value)                                 \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 8, 8, value)
+#define CH_SWITCH_SET_INFO_LOC_NO_CLR(h2c_pkt, value)                          \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 8, 8, value)
+#define CH_SWITCH_GET_CH_NUM(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 16, 8)
+#define CH_SWITCH_SET_CH_NUM(h2c_pkt, value)                                   \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 16, 8, value)
+#define CH_SWITCH_SET_CH_NUM_NO_CLR(h2c_pkt, value)                            \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 16, 8, value)
+#define CH_SWITCH_GET_PRI_CH_IDX(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 24, 4)
+#define CH_SWITCH_SET_PRI_CH_IDX(h2c_pkt, value)                               \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 24, 4, value)
+#define CH_SWITCH_SET_PRI_CH_IDX_NO_CLR(h2c_pkt, value)                        \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 24, 4, value)
+#define CH_SWITCH_GET_DEST_BW(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 28, 4)
+#define CH_SWITCH_SET_DEST_BW(h2c_pkt, value)                                  \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 28, 4, value)
+#define CH_SWITCH_SET_DEST_BW_NO_CLR(h2c_pkt, value)                           \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 28, 4, value)
+#define CH_SWITCH_GET_DEST_CH(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X0C, 0, 8)
+#define CH_SWITCH_SET_DEST_CH(h2c_pkt, value)                                  \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X0C, 0, 8, value)
+#define CH_SWITCH_SET_DEST_CH_NO_CLR(h2c_pkt, value)                           \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X0C, 0, 8, value)
+#define CH_SWITCH_GET_NORMAL_PERIOD(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X0C, 8, 6)
+#define CH_SWITCH_SET_NORMAL_PERIOD(h2c_pkt, value)                            \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X0C, 8, 6, value)
+#define CH_SWITCH_SET_NORMAL_PERIOD_NO_CLR(h2c_pkt, value)                     \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X0C, 8, 6, value)
+#define CH_SWITCH_GET_NORMAL_PERIOD_SEL(h2c_pkt)                               \
+	GET_H2C_FIELD(h2c_pkt + 0X0C, 14, 2)
+#define CH_SWITCH_SET_NORMAL_PERIOD_SEL(h2c_pkt, value)                        \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X0C, 14, 2, value)
+#define CH_SWITCH_SET_NORMAL_PERIOD_SEL_NO_CLR(h2c_pkt, value)                 \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X0C, 14, 2, value)
+#define CH_SWITCH_GET_SLOW_PERIOD(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X0C, 16, 6)
+#define CH_SWITCH_SET_SLOW_PERIOD(h2c_pkt, value)                              \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X0C, 16, 6, value)
+#define CH_SWITCH_SET_SLOW_PERIOD_NO_CLR(h2c_pkt, value)                       \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X0C, 16, 6, value)
+#define CH_SWITCH_GET_SLOW_PERIOD_SEL(h2c_pkt)                                 \
+	GET_H2C_FIELD(h2c_pkt + 0X0C, 22, 2)
+#define CH_SWITCH_SET_SLOW_PERIOD_SEL(h2c_pkt, value)                          \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X0C, 22, 2, value)
+#define CH_SWITCH_SET_SLOW_PERIOD_SEL_NO_CLR(h2c_pkt, value)                   \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X0C, 22, 2, value)
+#define CH_SWITCH_GET_NORMAL_CYCLE(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X0C, 24, 8)
+#define CH_SWITCH_SET_NORMAL_CYCLE(h2c_pkt, value)                             \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X0C, 24, 8, value)
+#define CH_SWITCH_SET_NORMAL_CYCLE_NO_CLR(h2c_pkt, value)                      \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X0C, 24, 8, value)
+#define CH_SWITCH_GET_TSF_HIGH(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X10, 0, 32)
+#define CH_SWITCH_SET_TSF_HIGH(h2c_pkt, value)                                 \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X10, 0, 32, value)
+#define CH_SWITCH_SET_TSF_HIGH_NO_CLR(h2c_pkt, value)                          \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X10, 0, 32, value)
+#define CH_SWITCH_GET_TSF_LOW(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X14, 0, 32)
+#define CH_SWITCH_SET_TSF_LOW(h2c_pkt, value)                                  \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X14, 0, 32, value)
+#define CH_SWITCH_SET_TSF_LOW_NO_CLR(h2c_pkt, value)                           \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X14, 0, 32, value)
+#define CH_SWITCH_GET_INFO_SIZE(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X18, 0, 16)
+#define CH_SWITCH_SET_INFO_SIZE(h2c_pkt, value)                                \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X18, 0, 16, value)
+#define CH_SWITCH_SET_INFO_SIZE_NO_CLR(h2c_pkt, value)                         \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X18, 0, 16, value)
+#define UPDATE_BEACON_PARSING_INFO_GET_FUNC_EN(h2c_pkt)                        \
+	GET_H2C_FIELD(h2c_pkt + 0X08, 0, 1)
+#define UPDATE_BEACON_PARSING_INFO_SET_FUNC_EN(h2c_pkt, value)                 \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 0, 1, value)
+#define UPDATE_BEACON_PARSING_INFO_SET_FUNC_EN_NO_CLR(h2c_pkt, value)          \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 0, 1, value)
+#define UPDATE_BEACON_PARSING_INFO_GET_SIZE_TH(h2c_pkt)                        \
+	GET_H2C_FIELD(h2c_pkt + 0X08, 8, 4)
+#define UPDATE_BEACON_PARSING_INFO_SET_SIZE_TH(h2c_pkt, value)                 \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 8, 4, value)
+#define UPDATE_BEACON_PARSING_INFO_SET_SIZE_TH_NO_CLR(h2c_pkt, value)          \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 8, 4, value)
+#define UPDATE_BEACON_PARSING_INFO_GET_TIMEOUT(h2c_pkt)                        \
+	GET_H2C_FIELD(h2c_pkt + 0X08, 12, 4)
+#define UPDATE_BEACON_PARSING_INFO_SET_TIMEOUT(h2c_pkt, value)                 \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 12, 4, value)
+#define UPDATE_BEACON_PARSING_INFO_SET_TIMEOUT_NO_CLR(h2c_pkt, value)          \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 12, 4, value)
+#define UPDATE_BEACON_PARSING_INFO_GET_IE_ID_BMP_0(h2c_pkt)                    \
+	GET_H2C_FIELD(h2c_pkt + 0X0C, 0, 32)
+#define UPDATE_BEACON_PARSING_INFO_SET_IE_ID_BMP_0(h2c_pkt, value)             \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X0C, 0, 32, value)
+#define UPDATE_BEACON_PARSING_INFO_SET_IE_ID_BMP_0_NO_CLR(h2c_pkt, value)      \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X0C, 0, 32, value)
+#define UPDATE_BEACON_PARSING_INFO_GET_IE_ID_BMP_1(h2c_pkt)                    \
+	GET_H2C_FIELD(h2c_pkt + 0X10, 0, 32)
+#define UPDATE_BEACON_PARSING_INFO_SET_IE_ID_BMP_1(h2c_pkt, value)             \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X10, 0, 32, value)
+#define UPDATE_BEACON_PARSING_INFO_SET_IE_ID_BMP_1_NO_CLR(h2c_pkt, value)      \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X10, 0, 32, value)
+#define UPDATE_BEACON_PARSING_INFO_GET_IE_ID_BMP_2(h2c_pkt)                    \
+	GET_H2C_FIELD(h2c_pkt + 0X14, 0, 32)
+#define UPDATE_BEACON_PARSING_INFO_SET_IE_ID_BMP_2(h2c_pkt, value)             \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X14, 0, 32, value)
+#define UPDATE_BEACON_PARSING_INFO_SET_IE_ID_BMP_2_NO_CLR(h2c_pkt, value)      \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X14, 0, 32, value)
+#define UPDATE_BEACON_PARSING_INFO_GET_IE_ID_BMP_3(h2c_pkt)                    \
+	GET_H2C_FIELD(h2c_pkt + 0X18, 0, 32)
+#define UPDATE_BEACON_PARSING_INFO_SET_IE_ID_BMP_3(h2c_pkt, value)             \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X18, 0, 32, value)
+#define UPDATE_BEACON_PARSING_INFO_SET_IE_ID_BMP_3_NO_CLR(h2c_pkt, value)      \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X18, 0, 32, value)
+#define UPDATE_BEACON_PARSING_INFO_GET_IE_ID_BMP_4(h2c_pkt)                    \
+	GET_H2C_FIELD(h2c_pkt + 0X1C, 0, 32)
+#define UPDATE_BEACON_PARSING_INFO_SET_IE_ID_BMP_4(h2c_pkt, value)             \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X1C, 0, 32, value)
+#define UPDATE_BEACON_PARSING_INFO_SET_IE_ID_BMP_4_NO_CLR(h2c_pkt, value)      \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X1C, 0, 32, value)
+#define CFG_PARAM_GET_NUM(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 0, 16)
+#define CFG_PARAM_SET_NUM(h2c_pkt, value)                                      \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 0, 16, value)
+#define CFG_PARAM_SET_NUM_NO_CLR(h2c_pkt, value)                               \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 0, 16, value)
+#define CFG_PARAM_GET_INIT_CASE(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 16, 1)
+#define CFG_PARAM_SET_INIT_CASE(h2c_pkt, value)                                \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 16, 1, value)
+#define CFG_PARAM_SET_INIT_CASE_NO_CLR(h2c_pkt, value)                         \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 16, 1, value)
+#define CFG_PARAM_GET_LOC(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 24, 8)
+#define CFG_PARAM_SET_LOC(h2c_pkt, value)                                      \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 24, 8, value)
+#define CFG_PARAM_SET_LOC_NO_CLR(h2c_pkt, value)                               \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 24, 8, value)
+#define UPDATE_DATAPACK_GET_SIZE(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 0, 16)
+#define UPDATE_DATAPACK_SET_SIZE(h2c_pkt, value)                               \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 0, 16, value)
+#define UPDATE_DATAPACK_SET_SIZE_NO_CLR(h2c_pkt, value)                        \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 0, 16, value)
+#define UPDATE_DATAPACK_GET_DATAPACK_ID(h2c_pkt)                               \
+	GET_H2C_FIELD(h2c_pkt + 0X08, 16, 8)
+#define UPDATE_DATAPACK_SET_DATAPACK_ID(h2c_pkt, value)                        \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 16, 8, value)
+#define UPDATE_DATAPACK_SET_DATAPACK_ID_NO_CLR(h2c_pkt, value)                 \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 16, 8, value)
+#define UPDATE_DATAPACK_GET_DATAPACK_LOC(h2c_pkt)                              \
+	GET_H2C_FIELD(h2c_pkt + 0X08, 24, 8)
+#define UPDATE_DATAPACK_SET_DATAPACK_LOC(h2c_pkt, value)                       \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 24, 8, value)
+#define UPDATE_DATAPACK_SET_DATAPACK_LOC_NO_CLR(h2c_pkt, value)                \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 24, 8, value)
+#define UPDATE_DATAPACK_GET_DATAPACK_SEGMENT(h2c_pkt)                          \
+	GET_H2C_FIELD(h2c_pkt + 0X0C, 0, 8)
+#define UPDATE_DATAPACK_SET_DATAPACK_SEGMENT(h2c_pkt, value)                   \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X0C, 0, 8, value)
+#define UPDATE_DATAPACK_SET_DATAPACK_SEGMENT_NO_CLR(h2c_pkt, value)            \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X0C, 0, 8, value)
+#define UPDATE_DATAPACK_GET_END_SEGMENT(h2c_pkt)                               \
+	GET_H2C_FIELD(h2c_pkt + 0X0C, 8, 1)
+#define UPDATE_DATAPACK_SET_END_SEGMENT(h2c_pkt, value)                        \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X0C, 8, 1, value)
+#define UPDATE_DATAPACK_SET_END_SEGMENT_NO_CLR(h2c_pkt, value)                 \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X0C, 8, 1, value)
+#define RUN_DATAPACK_GET_DATAPACK_ID(h2c_pkt)                                  \
+	GET_H2C_FIELD(h2c_pkt + 0X08, 0, 8)
+#define RUN_DATAPACK_SET_DATAPACK_ID(h2c_pkt, value)                           \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 0, 8, value)
+#define RUN_DATAPACK_SET_DATAPACK_ID_NO_CLR(h2c_pkt, value)                    \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 0, 8, value)
+#define DOWNLOAD_FLASH_GET_SPI_CMD(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 0, 8)
+#define DOWNLOAD_FLASH_SET_SPI_CMD(h2c_pkt, value)                             \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 0, 8, value)
+#define DOWNLOAD_FLASH_SET_SPI_CMD_NO_CLR(h2c_pkt, value)                      \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 0, 8, value)
+#define DOWNLOAD_FLASH_GET_LOCATION(h2c_pkt)                                   \
+	GET_H2C_FIELD(h2c_pkt + 0X08, 8, 16)
+#define DOWNLOAD_FLASH_SET_LOCATION(h2c_pkt, value)                            \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 8, 16, value)
+#define DOWNLOAD_FLASH_SET_LOCATION_NO_CLR(h2c_pkt, value)                     \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 8, 16, value)
+#define DOWNLOAD_FLASH_GET_SIZE(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X0C, 0, 32)
+#define DOWNLOAD_FLASH_SET_SIZE(h2c_pkt, value)                                \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X0C, 0, 32, value)
+#define DOWNLOAD_FLASH_SET_SIZE_NO_CLR(h2c_pkt, value)                         \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X0C, 0, 32, value)
+#define DOWNLOAD_FLASH_GET_START_ADDR(h2c_pkt)                                 \
+	GET_H2C_FIELD(h2c_pkt + 0X10, 0, 32)
+#define DOWNLOAD_FLASH_SET_START_ADDR(h2c_pkt, value)                          \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X10, 0, 32, value)
+#define DOWNLOAD_FLASH_SET_START_ADDR_NO_CLR(h2c_pkt, value)                   \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X10, 0, 32, value)
+#define UPDATE_PKT_GET_SIZE(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 0, 16)
+#define UPDATE_PKT_SET_SIZE(h2c_pkt, value)                                    \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 0, 16, value)
+#define UPDATE_PKT_SET_SIZE_NO_CLR(h2c_pkt, value)                             \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 0, 16, value)
+#define UPDATE_PKT_GET_ID(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 16, 8)
+#define UPDATE_PKT_SET_ID(h2c_pkt, value)                                      \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 16, 8, value)
+#define UPDATE_PKT_SET_ID_NO_CLR(h2c_pkt, value)                               \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 16, 8, value)
+#define UPDATE_PKT_GET_LOC(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 24, 8)
+#define UPDATE_PKT_SET_LOC(h2c_pkt, value)                                     \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 24, 8, value)
+#define UPDATE_PKT_SET_LOC_NO_CLR(h2c_pkt, value)                              \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 24, 8, value)
+#define GENERAL_INFO_GET_FW_TX_BOUNDARY(h2c_pkt)                               \
+	GET_H2C_FIELD(h2c_pkt + 0X08, 16, 8)
+#define GENERAL_INFO_SET_FW_TX_BOUNDARY(h2c_pkt, value)                        \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 16, 8, value)
+#define GENERAL_INFO_SET_FW_TX_BOUNDARY_NO_CLR(h2c_pkt, value)                 \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 16, 8, value)
+#define IQK_GET_CLEAR(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 0, 1)
+#define IQK_SET_CLEAR(h2c_pkt, value)                                          \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 0, 1, value)
+#define IQK_SET_CLEAR_NO_CLR(h2c_pkt, value)                                   \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 0, 1, value)
+#define IQK_GET_SEGMENT_IQK(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 1, 1)
+#define IQK_SET_SEGMENT_IQK(h2c_pkt, value)                                    \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 1, 1, value)
+#define IQK_SET_SEGMENT_IQK_NO_CLR(h2c_pkt, value)                             \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 1, 1, value)
+#define PWR_TRK_GET_ENABLE_A(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 0, 1)
+#define PWR_TRK_SET_ENABLE_A(h2c_pkt, value)                                   \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 0, 1, value)
+#define PWR_TRK_SET_ENABLE_A_NO_CLR(h2c_pkt, value)                            \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 0, 1, value)
+#define PWR_TRK_GET_ENABLE_B(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 1, 1)
+#define PWR_TRK_SET_ENABLE_B(h2c_pkt, value)                                   \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 1, 1, value)
+#define PWR_TRK_SET_ENABLE_B_NO_CLR(h2c_pkt, value)                            \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 1, 1, value)
+#define PWR_TRK_GET_ENABLE_C(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 2, 1)
+#define PWR_TRK_SET_ENABLE_C(h2c_pkt, value)                                   \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 2, 1, value)
+#define PWR_TRK_SET_ENABLE_C_NO_CLR(h2c_pkt, value)                            \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 2, 1, value)
+#define PWR_TRK_GET_ENABLE_D(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 3, 1)
+#define PWR_TRK_SET_ENABLE_D(h2c_pkt, value)                                   \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 3, 1, value)
+#define PWR_TRK_SET_ENABLE_D_NO_CLR(h2c_pkt, value)                            \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 3, 1, value)
+#define PWR_TRK_GET_TYPE(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 4, 3)
+#define PWR_TRK_SET_TYPE(h2c_pkt, value)                                       \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 4, 3, value)
+#define PWR_TRK_SET_TYPE_NO_CLR(h2c_pkt, value)                                \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 4, 3, value)
+#define PWR_TRK_GET_BBSWING_INDEX(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 8, 8)
+#define PWR_TRK_SET_BBSWING_INDEX(h2c_pkt, value)                              \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 8, 8, value)
+#define PWR_TRK_SET_BBSWING_INDEX_NO_CLR(h2c_pkt, value)                       \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 8, 8, value)
+#define PWR_TRK_GET_TX_PWR_INDEX_A(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X0C, 0, 8)
+#define PWR_TRK_SET_TX_PWR_INDEX_A(h2c_pkt, value)                             \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X0C, 0, 8, value)
+#define PWR_TRK_SET_TX_PWR_INDEX_A_NO_CLR(h2c_pkt, value)                      \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X0C, 0, 8, value)
+#define PWR_TRK_GET_OFFSET_VALUE_A(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X0C, 8, 8)
+#define PWR_TRK_SET_OFFSET_VALUE_A(h2c_pkt, value)                             \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X0C, 8, 8, value)
+#define PWR_TRK_SET_OFFSET_VALUE_A_NO_CLR(h2c_pkt, value)                      \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X0C, 8, 8, value)
+#define PWR_TRK_GET_TSSI_VALUE_A(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X0C, 16, 8)
+#define PWR_TRK_SET_TSSI_VALUE_A(h2c_pkt, value)                               \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X0C, 16, 8, value)
+#define PWR_TRK_SET_TSSI_VALUE_A_NO_CLR(h2c_pkt, value)                        \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X0C, 16, 8, value)
+#define PWR_TRK_GET_TX_PWR_INDEX_B(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X10, 0, 8)
+#define PWR_TRK_SET_TX_PWR_INDEX_B(h2c_pkt, value)                             \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X10, 0, 8, value)
+#define PWR_TRK_SET_TX_PWR_INDEX_B_NO_CLR(h2c_pkt, value)                      \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X10, 0, 8, value)
+#define PWR_TRK_GET_OFFSET_VALUE_B(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X10, 8, 8)
+#define PWR_TRK_SET_OFFSET_VALUE_B(h2c_pkt, value)                             \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X10, 8, 8, value)
+#define PWR_TRK_SET_OFFSET_VALUE_B_NO_CLR(h2c_pkt, value)                      \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X10, 8, 8, value)
+#define PWR_TRK_GET_TSSI_VALUE_B(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X10, 16, 8)
+#define PWR_TRK_SET_TSSI_VALUE_B(h2c_pkt, value)                               \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X10, 16, 8, value)
+#define PWR_TRK_SET_TSSI_VALUE_B_NO_CLR(h2c_pkt, value)                        \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X10, 16, 8, value)
+#define PWR_TRK_GET_TX_PWR_INDEX_C(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X14, 0, 8)
+#define PWR_TRK_SET_TX_PWR_INDEX_C(h2c_pkt, value)                             \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X14, 0, 8, value)
+#define PWR_TRK_SET_TX_PWR_INDEX_C_NO_CLR(h2c_pkt, value)                      \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X14, 0, 8, value)
+#define PWR_TRK_GET_OFFSET_VALUE_C(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X14, 8, 8)
+#define PWR_TRK_SET_OFFSET_VALUE_C(h2c_pkt, value)                             \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X14, 8, 8, value)
+#define PWR_TRK_SET_OFFSET_VALUE_C_NO_CLR(h2c_pkt, value)                      \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X14, 8, 8, value)
+#define PWR_TRK_GET_TSSI_VALUE_C(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X14, 16, 8)
+#define PWR_TRK_SET_TSSI_VALUE_C(h2c_pkt, value)                               \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X14, 16, 8, value)
+#define PWR_TRK_SET_TSSI_VALUE_C_NO_CLR(h2c_pkt, value)                        \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X14, 16, 8, value)
+#define PWR_TRK_GET_TX_PWR_INDEX_D(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X18, 0, 8)
+#define PWR_TRK_SET_TX_PWR_INDEX_D(h2c_pkt, value)                             \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X18, 0, 8, value)
+#define PWR_TRK_SET_TX_PWR_INDEX_D_NO_CLR(h2c_pkt, value)                      \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X18, 0, 8, value)
+#define PWR_TRK_GET_OFFSET_VALUE_D(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X18, 8, 8)
+#define PWR_TRK_SET_OFFSET_VALUE_D(h2c_pkt, value)                             \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X18, 8, 8, value)
+#define PWR_TRK_SET_OFFSET_VALUE_D_NO_CLR(h2c_pkt, value)                      \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X18, 8, 8, value)
+#define PWR_TRK_GET_TSSI_VALUE_D(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X18, 16, 8)
+#define PWR_TRK_SET_TSSI_VALUE_D(h2c_pkt, value)                               \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X18, 16, 8, value)
+#define PWR_TRK_SET_TSSI_VALUE_D_NO_CLR(h2c_pkt, value)                        \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X18, 16, 8, value)
+#define PSD_GET_START_PSD(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 0, 16)
+#define PSD_SET_START_PSD(h2c_pkt, value)                                      \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 0, 16, value)
+#define PSD_SET_START_PSD_NO_CLR(h2c_pkt, value)                               \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 0, 16, value)
+#define PSD_GET_END_PSD(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 16, 16)
+#define PSD_SET_END_PSD(h2c_pkt, value)                                        \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 16, 16, value)
+#define PSD_SET_END_PSD_NO_CLR(h2c_pkt, value)                                 \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 16, 16, value)
+#define PHYDM_INFO_GET_REF_TYPE(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 0, 8)
+#define PHYDM_INFO_SET_REF_TYPE(h2c_pkt, value)                                \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 0, 8, value)
+#define PHYDM_INFO_SET_REF_TYPE_NO_CLR(h2c_pkt, value)                         \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 0, 8, value)
+#define PHYDM_INFO_GET_RF_TYPE(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 8, 8)
+#define PHYDM_INFO_SET_RF_TYPE(h2c_pkt, value)                                 \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 8, 8, value)
+#define PHYDM_INFO_SET_RF_TYPE_NO_CLR(h2c_pkt, value)                          \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 8, 8, value)
+#define PHYDM_INFO_GET_CUT_VER(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 16, 8)
+#define PHYDM_INFO_SET_CUT_VER(h2c_pkt, value)                                 \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 16, 8, value)
+#define PHYDM_INFO_SET_CUT_VER_NO_CLR(h2c_pkt, value)                          \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 16, 8, value)
+#define PHYDM_INFO_GET_RX_ANT_STATUS(h2c_pkt)                                  \
+	GET_H2C_FIELD(h2c_pkt + 0X08, 24, 4)
+#define PHYDM_INFO_SET_RX_ANT_STATUS(h2c_pkt, value)                           \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 24, 4, value)
+#define PHYDM_INFO_SET_RX_ANT_STATUS_NO_CLR(h2c_pkt, value)                    \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 24, 4, value)
+#define PHYDM_INFO_GET_TX_ANT_STATUS(h2c_pkt)                                  \
+	GET_H2C_FIELD(h2c_pkt + 0X08, 28, 4)
+#define PHYDM_INFO_SET_TX_ANT_STATUS(h2c_pkt, value)                           \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 28, 4, value)
+#define PHYDM_INFO_SET_TX_ANT_STATUS_NO_CLR(h2c_pkt, value)                    \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 28, 4, value)
+#define FW_SNDING_GET_SU0(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 0, 1)
+#define FW_SNDING_SET_SU0(h2c_pkt, value)                                      \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 0, 1, value)
+#define FW_SNDING_SET_SU0_NO_CLR(h2c_pkt, value)                               \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 0, 1, value)
+#define FW_SNDING_GET_SU1(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 1, 1)
+#define FW_SNDING_SET_SU1(h2c_pkt, value)                                      \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 1, 1, value)
+#define FW_SNDING_SET_SU1_NO_CLR(h2c_pkt, value)                               \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 1, 1, value)
+#define FW_SNDING_GET_MU(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 2, 1)
+#define FW_SNDING_SET_MU(h2c_pkt, value)                                       \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 2, 1, value)
+#define FW_SNDING_SET_MU_NO_CLR(h2c_pkt, value)                                \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 2, 1, value)
+#define FW_SNDING_GET_PERIOD(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 8, 8)
+#define FW_SNDING_SET_PERIOD(h2c_pkt, value)                                   \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 8, 8, value)
+#define FW_SNDING_SET_PERIOD_NO_CLR(h2c_pkt, value)                            \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 8, 8, value)
+#define FW_SNDING_GET_NDPA0_HEAD_PG(h2c_pkt)                                   \
+	GET_H2C_FIELD(h2c_pkt + 0X08, 16, 8)
+#define FW_SNDING_SET_NDPA0_HEAD_PG(h2c_pkt, value)                            \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 16, 8, value)
+#define FW_SNDING_SET_NDPA0_HEAD_PG_NO_CLR(h2c_pkt, value)                     \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 16, 8, value)
+#define FW_SNDING_GET_NDPA1_HEAD_PG(h2c_pkt)                                   \
+	GET_H2C_FIELD(h2c_pkt + 0X08, 24, 8)
+#define FW_SNDING_SET_NDPA1_HEAD_PG(h2c_pkt, value)                            \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 24, 8, value)
+#define FW_SNDING_SET_NDPA1_HEAD_PG_NO_CLR(h2c_pkt, value)                     \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 24, 8, value)
+#define FW_SNDING_GET_MU_NDPA_HEAD_PG(h2c_pkt)                                 \
+	GET_H2C_FIELD(h2c_pkt + 0XC, 0, 8)
+#define FW_SNDING_SET_MU_NDPA_HEAD_PG(h2c_pkt, value)                          \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0XC, 0, 8, value)
+#define FW_SNDING_SET_MU_NDPA_HEAD_PG_NO_CLR(h2c_pkt, value)                   \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0XC, 0, 8, value)
+#define FW_SNDING_GET_RPT0_HEAD_PG(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0XC, 8, 8)
+#define FW_SNDING_SET_RPT0_HEAD_PG(h2c_pkt, value)                             \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0XC, 8, 8, value)
+#define FW_SNDING_SET_RPT0_HEAD_PG_NO_CLR(h2c_pkt, value)                      \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0XC, 8, 8, value)
+#define FW_SNDING_GET_RPT1_HEAD_PG(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0XC, 16, 8)
+#define FW_SNDING_SET_RPT1_HEAD_PG(h2c_pkt, value)                             \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0XC, 16, 8, value)
+#define FW_SNDING_SET_RPT1_HEAD_PG_NO_CLR(h2c_pkt, value)                      \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0XC, 16, 8, value)
+#define FW_SNDING_GET_RPT2_HEAD_PG(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0XC, 24, 8)
+#define FW_SNDING_SET_RPT2_HEAD_PG(h2c_pkt, value)                             \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0XC, 24, 8, value)
+#define FW_SNDING_SET_RPT2_HEAD_PG_NO_CLR(h2c_pkt, value)                      \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0XC, 24, 8, value)
+#define FW_FWCTRL_GET_SEQ_NUM(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 0, 8)
+#define FW_FWCTRL_SET_SEQ_NUM(h2c_pkt, value)                                  \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 0, 8, value)
+#define FW_FWCTRL_SET_SEQ_NUM_NO_CLR(h2c_pkt, value)                           \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 0, 8, value)
+#define FW_FWCTRL_GET_MORE_CONTENT(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 8, 1)
+#define FW_FWCTRL_SET_MORE_CONTENT(h2c_pkt, value)                             \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 8, 1, value)
+#define FW_FWCTRL_SET_MORE_CONTENT_NO_CLR(h2c_pkt, value)                      \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 8, 1, value)
+#define FW_FWCTRL_GET_CONTENT_IDX(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 9, 7)
+#define FW_FWCTRL_SET_CONTENT_IDX(h2c_pkt, value)                              \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 9, 7, value)
+#define FW_FWCTRL_SET_CONTENT_IDX_NO_CLR(h2c_pkt, value)                       \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 9, 7, value)
+#define FW_FWCTRL_GET_CLASS_ID(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 16, 8)
+#define FW_FWCTRL_SET_CLASS_ID(h2c_pkt, value)                                 \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 16, 8, value)
+#define FW_FWCTRL_SET_CLASS_ID_NO_CLR(h2c_pkt, value)                          \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 16, 8, value)
+#define FW_FWCTRL_GET_LENGTH(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 24, 8)
+#define FW_FWCTRL_SET_LENGTH(h2c_pkt, value)                                   \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 24, 8, value)
+#define FW_FWCTRL_SET_LENGTH_NO_CLR(h2c_pkt, value)                            \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 24, 8, value)
+#define FW_FWCTRL_GET_CONTENT(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X0C, 0, 32)
+#define FW_FWCTRL_SET_CONTENT(h2c_pkt, value)                                  \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X0C, 0, 32, value)
+#define FW_FWCTRL_SET_CONTENT_NO_CLR(h2c_pkt, value)                           \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X0C, 0, 32, value)
+#define P2PPS_GET_OFFLOAD_EN(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 0, 1)
+#define P2PPS_SET_OFFLOAD_EN(h2c_pkt, value)                                   \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 0, 1, value)
+#define P2PPS_SET_OFFLOAD_EN_NO_CLR(h2c_pkt, value)                            \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 0, 1, value)
+#define P2PPS_GET_ROLE(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 1, 1)
+#define P2PPS_SET_ROLE(h2c_pkt, value)                                         \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 1, 1, value)
+#define P2PPS_SET_ROLE_NO_CLR(h2c_pkt, value)                                  \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 1, 1, value)
+#define P2PPS_GET_CTWINDOW_EN(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 2, 1)
+#define P2PPS_SET_CTWINDOW_EN(h2c_pkt, value)                                  \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 2, 1, value)
+#define P2PPS_SET_CTWINDOW_EN_NO_CLR(h2c_pkt, value)                           \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 2, 1, value)
+#define P2PPS_GET_NOA_EN(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 3, 1)
+#define P2PPS_SET_NOA_EN(h2c_pkt, value)                                       \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 3, 1, value)
+#define P2PPS_SET_NOA_EN_NO_CLR(h2c_pkt, value)                                \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 3, 1, value)
+#define P2PPS_GET_NOA_SEL(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 4, 1)
+#define P2PPS_SET_NOA_SEL(h2c_pkt, value)                                      \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 4, 1, value)
+#define P2PPS_SET_NOA_SEL_NO_CLR(h2c_pkt, value)                               \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 4, 1, value)
+#define P2PPS_GET_ALLSTASLEEP(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 5, 1)
+#define P2PPS_SET_ALLSTASLEEP(h2c_pkt, value)                                  \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 5, 1, value)
+#define P2PPS_SET_ALLSTASLEEP_NO_CLR(h2c_pkt, value)                           \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 5, 1, value)
+#define P2PPS_GET_DISCOVERY(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 6, 1)
+#define P2PPS_SET_DISCOVERY(h2c_pkt, value)                                    \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 6, 1, value)
+#define P2PPS_SET_DISCOVERY_NO_CLR(h2c_pkt, value)                             \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 6, 1, value)
+#define P2PPS_GET_DISABLE_CLOSERF(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 7, 1)
+#define P2PPS_SET_DISABLE_CLOSERF(h2c_pkt, value)                              \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 7, 1, value)
+#define P2PPS_SET_DISABLE_CLOSERF_NO_CLR(h2c_pkt, value)                       \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 7, 1, value)
+#define P2PPS_GET_P2P_PORT_ID(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 8, 8)
+#define P2PPS_SET_P2P_PORT_ID(h2c_pkt, value)                                  \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 8, 8, value)
+#define P2PPS_SET_P2P_PORT_ID_NO_CLR(h2c_pkt, value)                           \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 8, 8, value)
+#define P2PPS_GET_P2P_GROUP(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 16, 8)
+#define P2PPS_SET_P2P_GROUP(h2c_pkt, value)                                    \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 16, 8, value)
+#define P2PPS_SET_P2P_GROUP_NO_CLR(h2c_pkt, value)                             \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 16, 8, value)
+#define P2PPS_GET_P2P_MACID(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 24, 8)
+#define P2PPS_SET_P2P_MACID(h2c_pkt, value)                                    \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 24, 8, value)
+#define P2PPS_SET_P2P_MACID_NO_CLR(h2c_pkt, value)                             \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 24, 8, value)
+#define P2PPS_GET_CTWINDOW_LENGTH(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X0C, 0, 8)
+#define P2PPS_SET_CTWINDOW_LENGTH(h2c_pkt, value)                              \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X0C, 0, 8, value)
+#define P2PPS_SET_CTWINDOW_LENGTH_NO_CLR(h2c_pkt, value)                       \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X0C, 0, 8, value)
+#define P2PPS_GET_NOA_DURATION_PARA(h2c_pkt)                                   \
+	GET_H2C_FIELD(h2c_pkt + 0X10, 0, 32)
+#define P2PPS_SET_NOA_DURATION_PARA(h2c_pkt, value)                            \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X10, 0, 32, value)
+#define P2PPS_SET_NOA_DURATION_PARA_NO_CLR(h2c_pkt, value)                     \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X10, 0, 32, value)
+#define P2PPS_GET_NOA_INTERVAL_PARA(h2c_pkt)                                   \
+	GET_H2C_FIELD(h2c_pkt + 0X14, 0, 32)
+#define P2PPS_SET_NOA_INTERVAL_PARA(h2c_pkt, value)                            \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X14, 0, 32, value)
+#define P2PPS_SET_NOA_INTERVAL_PARA_NO_CLR(h2c_pkt, value)                     \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X14, 0, 32, value)
+#define P2PPS_GET_NOA_START_TIME_PARA(h2c_pkt)                                 \
+	GET_H2C_FIELD(h2c_pkt + 0X18, 0, 32)
+#define P2PPS_SET_NOA_START_TIME_PARA(h2c_pkt, value)                          \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X18, 0, 32, value)
+#define P2PPS_SET_NOA_START_TIME_PARA_NO_CLR(h2c_pkt, value)                   \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X18, 0, 32, value)
+#define P2PPS_GET_NOA_COUNT_PARA(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X1C, 0, 32)
+#define P2PPS_SET_NOA_COUNT_PARA(h2c_pkt, value)                               \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X1C, 0, 32, value)
+#define P2PPS_SET_NOA_COUNT_PARA_NO_CLR(h2c_pkt, value)                        \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X1C, 0, 32, value)
+#define BT_COEX_GET_DATA_START(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 0, 8)
+#define BT_COEX_SET_DATA_START(h2c_pkt, value)                                 \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 0, 8, value)
+#define BT_COEX_SET_DATA_START_NO_CLR(h2c_pkt, value)                          \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 0, 8, value)
+#define NAN_CTRL_GET_NAN_EN(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 0, 2)
+#define NAN_CTRL_SET_NAN_EN(h2c_pkt, value)                                    \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 0, 2, value)
+#define NAN_CTRL_SET_NAN_EN_NO_CLR(h2c_pkt, value)                             \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 0, 2, value)
+#define NAN_CTRL_GET_WARMUP_TIMER_FLAG(h2c_pkt)                                \
+	GET_H2C_FIELD(h2c_pkt + 0X08, 2, 1)
+#define NAN_CTRL_SET_WARMUP_TIMER_FLAG(h2c_pkt, value)                         \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 2, 1, value)
+#define NAN_CTRL_SET_WARMUP_TIMER_FLAG_NO_CLR(h2c_pkt, value)                  \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 2, 1, value)
+#define NAN_CTRL_GET_SUPPORT_BAND(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 8, 2)
+#define NAN_CTRL_SET_SUPPORT_BAND(h2c_pkt, value)                              \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 8, 2, value)
+#define NAN_CTRL_SET_SUPPORT_BAND_NO_CLR(h2c_pkt, value)                       \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 8, 2, value)
+#define NAN_CTRL_GET_DISABLE_2G_DISC_BCN(h2c_pkt)                              \
+	GET_H2C_FIELD(h2c_pkt + 0X08, 10, 1)
+#define NAN_CTRL_SET_DISABLE_2G_DISC_BCN(h2c_pkt, value)                       \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 10, 1, value)
+#define NAN_CTRL_SET_DISABLE_2G_DISC_BCN_NO_CLR(h2c_pkt, value)                \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 10, 1, value)
+#define NAN_CTRL_GET_DISABLE_5G_DISC_BCN(h2c_pkt)                              \
+	GET_H2C_FIELD(h2c_pkt + 0X08, 11, 1)
+#define NAN_CTRL_SET_DISABLE_5G_DISC_BCN(h2c_pkt, value)                       \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 11, 1, value)
+#define NAN_CTRL_SET_DISABLE_5G_DISC_BCN_NO_CLR(h2c_pkt, value)                \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 11, 1, value)
+#define NAN_CTRL_GET_BCN_RSVD_PAGE_OFFSET(h2c_pkt)                             \
+	GET_H2C_FIELD(h2c_pkt + 0X08, 16, 8)
+#define NAN_CTRL_SET_BCN_RSVD_PAGE_OFFSET(h2c_pkt, value)                      \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 16, 8, value)
+#define NAN_CTRL_SET_BCN_RSVD_PAGE_OFFSET_NO_CLR(h2c_pkt, value)               \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 16, 8, value)
+#define NAN_CTRL_GET_CHANNEL_2G(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 24, 8)
+#define NAN_CTRL_SET_CHANNEL_2G(h2c_pkt, value)                                \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 24, 8, value)
+#define NAN_CTRL_SET_CHANNEL_2G_NO_CLR(h2c_pkt, value)                         \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 24, 8, value)
+#define NAN_CTRL_GET_CHANNEL_5G(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X0C, 0, 8)
+#define NAN_CTRL_SET_CHANNEL_5G(h2c_pkt, value)                                \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X0C, 0, 8, value)
+#define NAN_CTRL_SET_CHANNEL_5G_NO_CLR(h2c_pkt, value)                         \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X0C, 0, 8, value)
+#define NAN_CTRL_GET_MASTERPREFERENCE_VALUE(h2c_pkt)                           \
+	GET_H2C_FIELD(h2c_pkt + 0X0C, 8, 8)
+#define NAN_CTRL_SET_MASTERPREFERENCE_VALUE(h2c_pkt, value)                    \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X0C, 8, 8, value)
+#define NAN_CTRL_SET_MASTERPREFERENCE_VALUE_NO_CLR(h2c_pkt, value)             \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X0C, 8, 8, value)
+#define NAN_CTRL_GET_RANDOMFACTOR_VALUE(h2c_pkt)                               \
+	GET_H2C_FIELD(h2c_pkt + 0X0C, 16, 8)
+#define NAN_CTRL_SET_RANDOMFACTOR_VALUE(h2c_pkt, value)                        \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X0C, 16, 8, value)
+#define NAN_CTRL_SET_RANDOMFACTOR_VALUE_NO_CLR(h2c_pkt, value)                 \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X0C, 16, 8, value)
+#define NAN_CHANNEL_PLAN_0_GET_CHANNEL_NUMBER_0(h2c_pkt)                       \
+	GET_H2C_FIELD(h2c_pkt + 0X08, 0, 8)
+#define NAN_CHANNEL_PLAN_0_SET_CHANNEL_NUMBER_0(h2c_pkt, value)                \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 0, 8, value)
+#define NAN_CHANNEL_PLAN_0_SET_CHANNEL_NUMBER_0_NO_CLR(h2c_pkt, value)         \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 0, 8, value)
+#define NAN_CHANNEL_PLAN_0_GET_UNPAUSE_MACID_0(h2c_pkt)                        \
+	GET_H2C_FIELD(h2c_pkt + 0X08, 8, 8)
+#define NAN_CHANNEL_PLAN_0_SET_UNPAUSE_MACID_0(h2c_pkt, value)                 \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 8, 8, value)
+#define NAN_CHANNEL_PLAN_0_SET_UNPAUSE_MACID_0_NO_CLR(h2c_pkt, value)          \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 8, 8, value)
+#define NAN_CHANNEL_PLAN_0_GET_START_TIME_SLOT_0(h2c_pkt)                      \
+	GET_H2C_FIELD(h2c_pkt + 0X0C, 0, 16)
+#define NAN_CHANNEL_PLAN_0_SET_START_TIME_SLOT_0(h2c_pkt, value)               \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X0C, 0, 16, value)
+#define NAN_CHANNEL_PLAN_0_SET_START_TIME_SLOT_0_NO_CLR(h2c_pkt, value)        \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X0C, 0, 16, value)
+#define NAN_CHANNEL_PLAN_0_GET_DURATION_0(h2c_pkt)                             \
+	GET_H2C_FIELD(h2c_pkt + 0X0C, 16, 16)
+#define NAN_CHANNEL_PLAN_0_SET_DURATION_0(h2c_pkt, value)                      \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X0C, 16, 16, value)
+#define NAN_CHANNEL_PLAN_0_SET_DURATION_0_NO_CLR(h2c_pkt, value)               \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X0C, 16, 16, value)
+#define NAN_CHANNEL_PLAN_0_GET_CHANNEL_NUMBER_1(h2c_pkt)                       \
+	GET_H2C_FIELD(h2c_pkt + 0X10, 0, 8)
+#define NAN_CHANNEL_PLAN_0_SET_CHANNEL_NUMBER_1(h2c_pkt, value)                \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X10, 0, 8, value)
+#define NAN_CHANNEL_PLAN_0_SET_CHANNEL_NUMBER_1_NO_CLR(h2c_pkt, value)         \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X10, 0, 8, value)
+#define NAN_CHANNEL_PLAN_0_GET_UNPAUSE_MACID_1(h2c_pkt)                        \
+	GET_H2C_FIELD(h2c_pkt + 0X10, 8, 8)
+#define NAN_CHANNEL_PLAN_0_SET_UNPAUSE_MACID_1(h2c_pkt, value)                 \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X10, 8, 8, value)
+#define NAN_CHANNEL_PLAN_0_SET_UNPAUSE_MACID_1_NO_CLR(h2c_pkt, value)          \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X10, 8, 8, value)
+#define NAN_CHANNEL_PLAN_0_GET_START_TIME_SLOT_1(h2c_pkt)                      \
+	GET_H2C_FIELD(h2c_pkt + 0X14, 0, 16)
+#define NAN_CHANNEL_PLAN_0_SET_START_TIME_SLOT_1(h2c_pkt, value)               \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X14, 0, 16, value)
+#define NAN_CHANNEL_PLAN_0_SET_START_TIME_SLOT_1_NO_CLR(h2c_pkt, value)        \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X14, 0, 16, value)
+#define NAN_CHANNEL_PLAN_0_GET_DURATION_1(h2c_pkt)                             \
+	GET_H2C_FIELD(h2c_pkt + 0X14, 16, 16)
+#define NAN_CHANNEL_PLAN_0_SET_DURATION_1(h2c_pkt, value)                      \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X14, 16, 16, value)
+#define NAN_CHANNEL_PLAN_0_SET_DURATION_1_NO_CLR(h2c_pkt, value)               \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X14, 16, 16, value)
+#define NAN_CHANNEL_PLAN_0_GET_CHANNEL_NUMBER_2(h2c_pkt)                       \
+	GET_H2C_FIELD(h2c_pkt + 0X18, 0, 8)
+#define NAN_CHANNEL_PLAN_0_SET_CHANNEL_NUMBER_2(h2c_pkt, value)                \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X18, 0, 8, value)
+#define NAN_CHANNEL_PLAN_0_SET_CHANNEL_NUMBER_2_NO_CLR(h2c_pkt, value)         \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X18, 0, 8, value)
+#define NAN_CHANNEL_PLAN_0_GET_UNPAUSE_MACID_2(h2c_pkt)                        \
+	GET_H2C_FIELD(h2c_pkt + 0X18, 8, 8)
+#define NAN_CHANNEL_PLAN_0_SET_UNPAUSE_MACID_2(h2c_pkt, value)                 \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X18, 8, 8, value)
+#define NAN_CHANNEL_PLAN_0_SET_UNPAUSE_MACID_2_NO_CLR(h2c_pkt, value)          \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X18, 8, 8, value)
+#define NAN_CHANNEL_PLAN_0_GET_START_TIME_SLOT_2(h2c_pkt)                      \
+	GET_H2C_FIELD(h2c_pkt + 0X1C, 0, 16)
+#define NAN_CHANNEL_PLAN_0_SET_START_TIME_SLOT_2(h2c_pkt, value)               \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X1C, 0, 16, value)
+#define NAN_CHANNEL_PLAN_0_SET_START_TIME_SLOT_2_NO_CLR(h2c_pkt, value)        \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X1C, 0, 16, value)
+#define NAN_CHANNEL_PLAN_0_GET_DURATION_2(h2c_pkt)                             \
+	GET_H2C_FIELD(h2c_pkt + 0X1C, 16, 16)
+#define NAN_CHANNEL_PLAN_0_SET_DURATION_2(h2c_pkt, value)                      \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X1C, 16, 16, value)
+#define NAN_CHANNEL_PLAN_0_SET_DURATION_2_NO_CLR(h2c_pkt, value)               \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X1C, 16, 16, value)
+#define NAN_CHANNEL_PLAN_1_GET_CHANNEL_NUMBER_3(h2c_pkt)                       \
+	GET_H2C_FIELD(h2c_pkt + 0X08, 0, 8)
+#define NAN_CHANNEL_PLAN_1_SET_CHANNEL_NUMBER_3(h2c_pkt, value)                \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 0, 8, value)
+#define NAN_CHANNEL_PLAN_1_SET_CHANNEL_NUMBER_3_NO_CLR(h2c_pkt, value)         \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 0, 8, value)
+#define NAN_CHANNEL_PLAN_1_GET_UNPAUSE_MACID_3(h2c_pkt)                        \
+	GET_H2C_FIELD(h2c_pkt + 0X08, 8, 8)
+#define NAN_CHANNEL_PLAN_1_SET_UNPAUSE_MACID_3(h2c_pkt, value)                 \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 8, 8, value)
+#define NAN_CHANNEL_PLAN_1_SET_UNPAUSE_MACID_3_NO_CLR(h2c_pkt, value)          \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 8, 8, value)
+#define NAN_CHANNEL_PLAN_1_GET_START_TIME_SLOT_3(h2c_pkt)                      \
+	GET_H2C_FIELD(h2c_pkt + 0X0C, 0, 16)
+#define NAN_CHANNEL_PLAN_1_SET_START_TIME_SLOT_3(h2c_pkt, value)               \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X0C, 0, 16, value)
+#define NAN_CHANNEL_PLAN_1_SET_START_TIME_SLOT_3_NO_CLR(h2c_pkt, value)        \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X0C, 0, 16, value)
+#define NAN_CHANNEL_PLAN_1_GET_DURATION_3(h2c_pkt)                             \
+	GET_H2C_FIELD(h2c_pkt + 0X0C, 16, 16)
+#define NAN_CHANNEL_PLAN_1_SET_DURATION_3(h2c_pkt, value)                      \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X0C, 16, 16, value)
+#define NAN_CHANNEL_PLAN_1_SET_DURATION_3_NO_CLR(h2c_pkt, value)               \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X0C, 16, 16, value)
+#define NAN_CHANNEL_PLAN_1_GET_CHANNEL_NUMBER_4(h2c_pkt)                       \
+	GET_H2C_FIELD(h2c_pkt + 0X10, 0, 8)
+#define NAN_CHANNEL_PLAN_1_SET_CHANNEL_NUMBER_4(h2c_pkt, value)                \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X10, 0, 8, value)
+#define NAN_CHANNEL_PLAN_1_SET_CHANNEL_NUMBER_4_NO_CLR(h2c_pkt, value)         \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X10, 0, 8, value)
+#define NAN_CHANNEL_PLAN_1_GET_UNPAUSE_MACID_4(h2c_pkt)                        \
+	GET_H2C_FIELD(h2c_pkt + 0X10, 8, 8)
+#define NAN_CHANNEL_PLAN_1_SET_UNPAUSE_MACID_4(h2c_pkt, value)                 \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X10, 8, 8, value)
+#define NAN_CHANNEL_PLAN_1_SET_UNPAUSE_MACID_4_NO_CLR(h2c_pkt, value)          \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X10, 8, 8, value)
+#define NAN_CHANNEL_PLAN_1_GET_START_TIME_SLOT_4(h2c_pkt)                      \
+	GET_H2C_FIELD(h2c_pkt + 0X14, 0, 16)
+#define NAN_CHANNEL_PLAN_1_SET_START_TIME_SLOT_4(h2c_pkt, value)               \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X14, 0, 16, value)
+#define NAN_CHANNEL_PLAN_1_SET_START_TIME_SLOT_4_NO_CLR(h2c_pkt, value)        \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X14, 0, 16, value)
+#define NAN_CHANNEL_PLAN_1_GET_DURATION_4(h2c_pkt)                             \
+	GET_H2C_FIELD(h2c_pkt + 0X14, 16, 16)
+#define NAN_CHANNEL_PLAN_1_SET_DURATION_4(h2c_pkt, value)                      \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X14, 16, 16, value)
+#define NAN_CHANNEL_PLAN_1_SET_DURATION_4_NO_CLR(h2c_pkt, value)               \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X14, 16, 16, value)
+#define NAN_CHANNEL_PLAN_1_GET_CHANNEL_NUMBER_5(h2c_pkt)                       \
+	GET_H2C_FIELD(h2c_pkt + 0X18, 0, 8)
+#define NAN_CHANNEL_PLAN_1_SET_CHANNEL_NUMBER_5(h2c_pkt, value)                \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X18, 0, 8, value)
+#define NAN_CHANNEL_PLAN_1_SET_CHANNEL_NUMBER_5_NO_CLR(h2c_pkt, value)         \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X18, 0, 8, value)
+#define NAN_CHANNEL_PLAN_1_GET_UNPAUSE_MACID_5(h2c_pkt)                        \
+	GET_H2C_FIELD(h2c_pkt + 0X18, 8, 8)
+#define NAN_CHANNEL_PLAN_1_SET_UNPAUSE_MACID_5(h2c_pkt, value)                 \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X18, 8, 8, value)
+#define NAN_CHANNEL_PLAN_1_SET_UNPAUSE_MACID_5_NO_CLR(h2c_pkt, value)          \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X18, 8, 8, value)
+#define NAN_CHANNEL_PLAN_1_GET_START_TIME_SLOT_5(h2c_pkt)                      \
+	GET_H2C_FIELD(h2c_pkt + 0X1C, 0, 16)
+#define NAN_CHANNEL_PLAN_1_SET_START_TIME_SLOT_5(h2c_pkt, value)               \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X1C, 0, 16, value)
+#define NAN_CHANNEL_PLAN_1_SET_START_TIME_SLOT_5_NO_CLR(h2c_pkt, value)        \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X1C, 0, 16, value)
+#define NAN_CHANNEL_PLAN_1_GET_DURATION_5(h2c_pkt)                             \
+	GET_H2C_FIELD(h2c_pkt + 0X1C, 16, 16)
+#define NAN_CHANNEL_PLAN_1_SET_DURATION_5(h2c_pkt, value)                      \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X1C, 16, 16, value)
+#define NAN_CHANNEL_PLAN_1_SET_DURATION_5_NO_CLR(h2c_pkt, value)               \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X1C, 16, 16, value)
+#endif
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/halmac/halmac_fw_offload_h2c_nic.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/halmac/halmac_fw_offload_h2c_nic.h
--- linux-5.6.3/3rdparty/rtl8821ce/hal/halmac/halmac_fw_offload_h2c_nic.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/halmac/halmac_fw_offload_h2c_nic.h	2020-04-10 16:35:06.811659835 +0300
@@ -0,0 +1,694 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ ******************************************************************************/
+
+#ifndef _HAL_FWOFFLOADH2CFORMAT_H2C_C2H_NIC_H_
+#define _HAL_FWOFFLOADH2CFORMAT_H2C_C2H_NIC_H_
+#define CMD_ID_FW_OFFLOAD_H2C 0XFF
+#define CMD_ID_FW_ACCESS_TEST 0XFF
+#define CMD_ID_CH_SWITCH 0XFF
+#define CMD_ID_DUMP_PHYSICAL_EFUSE 0XFF
+#define CMD_ID_UPDATE_BEACON_PARSING_INFO 0XFF
+#define CMD_ID_CFG_PARAM 0XFF
+#define CMD_ID_UPDATE_DATAPACK 0XFF
+#define CMD_ID_RUN_DATAPACK 0XFF
+#define CMD_ID_DOWNLOAD_FLASH 0XFF
+#define CMD_ID_UPDATE_PKT 0XFF
+#define CMD_ID_GENERAL_INFO 0XFF
+#define CMD_ID_IQK 0XFF
+#define CMD_ID_PWR_TRK 0XFF
+#define CMD_ID_PSD 0XFF
+#define CMD_ID_PHYDM_INFO 0XFF
+#define CMD_ID_FW_SNDING 0XFF
+#define CMD_ID_FW_FWCTRL 0XFF
+#define CMD_ID_H2C_LOOPBACK 0XFF
+#define CMD_ID_FWCMD_LOOPBACK 0XFF
+#define CMD_ID_P2PPS 0XFF
+#define CMD_ID_BT_COEX 0XFF
+#define CMD_ID_NAN_CTRL 0XFF
+#define CMD_ID_NAN_CHANNEL_PLAN_0 0XFF
+#define CMD_ID_NAN_CHANNEL_PLAN_1 0XFF
+#define CATEGORY_H2C_CMD_HEADER 0X00
+#define CATEGORY_FW_OFFLOAD_H2C 0X01
+#define CATEGORY_FW_ACCESS_TEST 0X01
+#define CATEGORY_CH_SWITCH 0X01
+#define CATEGORY_DUMP_PHYSICAL_EFUSE 0X01
+#define CATEGORY_UPDATE_BEACON_PARSING_INFO 0X01
+#define CATEGORY_CFG_PARAM 0X01
+#define CATEGORY_UPDATE_DATAPACK 0X01
+#define CATEGORY_RUN_DATAPACK 0X01
+#define CATEGORY_DOWNLOAD_FLASH 0X01
+#define CATEGORY_UPDATE_PKT 0X01
+#define CATEGORY_GENERAL_INFO 0X01
+#define CATEGORY_IQK 0X01
+#define CATEGORY_PWR_TRK 0X01
+#define CATEGORY_PSD 0X01
+#define CATEGORY_PHYDM_INFO 0X01
+#define CATEGORY_FW_SNDING 0X01
+#define CATEGORY_FW_FWCTRL 0X01
+#define CATEGORY_H2C_LOOPBACK 0X01
+#define CATEGORY_FWCMD_LOOPBACK 0X01
+#define CATEGORY_P2PPS 0X01
+#define CATEGORY_BT_COEX 0X01
+#define CATEGORY_NAN_CTRL 0X01
+#define CATEGORY_NAN_CHANNEL_PLAN_0 0X01
+#define CATEGORY_NAN_CHANNEL_PLAN_1 0X01
+#define SUB_CMD_ID_FW_ACCESS_TEST 0X00
+#define SUB_CMD_ID_CH_SWITCH 0X02
+#define SUB_CMD_ID_DUMP_PHYSICAL_EFUSE 0X03
+#define SUB_CMD_ID_UPDATE_BEACON_PARSING_INFO 0X05
+#define SUB_CMD_ID_CFG_PARAM 0X08
+#define SUB_CMD_ID_UPDATE_DATAPACK 0X09
+#define SUB_CMD_ID_RUN_DATAPACK 0X0A
+#define SUB_CMD_ID_DOWNLOAD_FLASH 0X0B
+#define SUB_CMD_ID_UPDATE_PKT 0X0C
+#define SUB_CMD_ID_GENERAL_INFO 0X0D
+#define SUB_CMD_ID_IQK 0X0E
+#define SUB_CMD_ID_PWR_TRK 0X0F
+#define SUB_CMD_ID_PSD 0X10
+#define SUB_CMD_ID_PHYDM_INFO 0X11
+#define SUB_CMD_ID_FW_SNDING 0X12
+#define SUB_CMD_ID_FW_FWCTRL 0X13
+#define SUB_CMD_ID_H2C_LOOPBACK 0X14
+#define SUB_CMD_ID_FWCMD_LOOPBACK 0X15
+#define SUB_CMD_ID_P2PPS 0X24
+#define SUB_CMD_ID_BT_COEX 0X60
+#define SUB_CMD_ID_NAN_CTRL 0XB2
+#define SUB_CMD_ID_NAN_CHANNEL_PLAN_0 0XB4
+#define SUB_CMD_ID_NAN_CHANNEL_PLAN_1 0XB5
+#define H2C_CMD_HEADER_GET_CATEGORY(h2c_pkt)                                   \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 0, 7)
+#define H2C_CMD_HEADER_SET_CATEGORY(h2c_pkt, value)                            \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 0, 7, value)
+#define H2C_CMD_HEADER_GET_ACK(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 7, 1)
+#define H2C_CMD_HEADER_SET_ACK(h2c_pkt, value)                                 \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 7, 1, value)
+#define H2C_CMD_HEADER_GET_TOTAL_LEN(h2c_pkt)                                  \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X04, 0, 16)
+#define H2C_CMD_HEADER_SET_TOTAL_LEN(h2c_pkt, value)                           \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 0, 16, value)
+#define H2C_CMD_HEADER_GET_SEQ_NUM(h2c_pkt)                                    \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X04, 16, 16)
+#define H2C_CMD_HEADER_SET_SEQ_NUM(h2c_pkt, value)                             \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 16, 16, value)
+#define FW_OFFLOAD_H2C_GET_CATEGORY(h2c_pkt)                                   \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 0, 7)
+#define FW_OFFLOAD_H2C_SET_CATEGORY(h2c_pkt, value)                            \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 0, 7, value)
+#define FW_OFFLOAD_H2C_GET_ACK(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 7, 1)
+#define FW_OFFLOAD_H2C_SET_ACK(h2c_pkt, value)                                 \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 7, 1, value)
+#define FW_OFFLOAD_H2C_GET_CMD_ID(h2c_pkt)                                     \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 8, 8)
+#define FW_OFFLOAD_H2C_SET_CMD_ID(h2c_pkt, value)                              \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 8, 8, value)
+#define FW_OFFLOAD_H2C_GET_SUB_CMD_ID(h2c_pkt)                                 \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 16, 16)
+#define FW_OFFLOAD_H2C_SET_SUB_CMD_ID(h2c_pkt, value)                          \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 16, 16, value)
+#define FW_OFFLOAD_H2C_GET_TOTAL_LEN(h2c_pkt)                                  \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X04, 0, 16)
+#define FW_OFFLOAD_H2C_SET_TOTAL_LEN(h2c_pkt, value)                           \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 0, 16, value)
+#define FW_OFFLOAD_H2C_GET_SEQ_NUM(h2c_pkt)                                    \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X04, 16, 16)
+#define FW_OFFLOAD_H2C_SET_SEQ_NUM(h2c_pkt, value)                             \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 16, 16, value)
+#define FW_ACCESS_TEST_GET_ACCESS_TXFF(h2c_pkt)                                \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 0, 1)
+#define FW_ACCESS_TEST_SET_ACCESS_TXFF(h2c_pkt, value)                         \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 0, 1, value)
+#define FW_ACCESS_TEST_GET_ACCESS_RXFF(h2c_pkt)                                \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 1, 1)
+#define FW_ACCESS_TEST_SET_ACCESS_RXFF(h2c_pkt, value)                         \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 1, 1, value)
+#define FW_ACCESS_TEST_GET_ACCESS_FWFF(h2c_pkt)                                \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 2, 1)
+#define FW_ACCESS_TEST_SET_ACCESS_FWFF(h2c_pkt, value)                         \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 2, 1, value)
+#define FW_ACCESS_TEST_GET_ACCESS_PHYFF(h2c_pkt)                               \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 3, 1)
+#define FW_ACCESS_TEST_SET_ACCESS_PHYFF(h2c_pkt, value)                        \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 3, 1, value)
+#define FW_ACCESS_TEST_GET_ACCESS_RPT_BUF(h2c_pkt)                             \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 4, 1)
+#define FW_ACCESS_TEST_SET_ACCESS_RPT_BUF(h2c_pkt, value)                      \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 4, 1, value)
+#define FW_ACCESS_TEST_GET_ACCESS_CAM(h2c_pkt)                                 \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 5, 1)
+#define FW_ACCESS_TEST_SET_ACCESS_CAM(h2c_pkt, value)                          \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 5, 1, value)
+#define FW_ACCESS_TEST_GET_ACCESS_WOW_CAM(h2c_pkt)                             \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 6, 1)
+#define FW_ACCESS_TEST_SET_ACCESS_WOW_CAM(h2c_pkt, value)                      \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 6, 1, value)
+#define FW_ACCESS_TEST_GET_ACCESS_RX_CAM(h2c_pkt)                              \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 7, 1)
+#define FW_ACCESS_TEST_SET_ACCESS_RX_CAM(h2c_pkt, value)                       \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 7, 1, value)
+#define FW_ACCESS_TEST_GET_ACCESS_BA_CAM(h2c_pkt)                              \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 8, 1)
+#define FW_ACCESS_TEST_SET_ACCESS_BA_CAM(h2c_pkt, value)                       \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 8, 1, value)
+#define FW_ACCESS_TEST_GET_ACCESS_MBSSID_CAM(h2c_pkt)                          \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 9, 1)
+#define FW_ACCESS_TEST_SET_ACCESS_MBSSID_CAM(h2c_pkt, value)                   \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 9, 1, value)
+#define FW_ACCESS_TEST_GET_ACCESS_PAGE0(h2c_pkt)                               \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 16, 1)
+#define FW_ACCESS_TEST_SET_ACCESS_PAGE0(h2c_pkt, value)                        \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 16, 1, value)
+#define FW_ACCESS_TEST_GET_ACCESS_PAGE1(h2c_pkt)                               \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 17, 1)
+#define FW_ACCESS_TEST_SET_ACCESS_PAGE1(h2c_pkt, value)                        \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 17, 1, value)
+#define FW_ACCESS_TEST_GET_ACCESS_PAGE2(h2c_pkt)                               \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 18, 1)
+#define FW_ACCESS_TEST_SET_ACCESS_PAGE2(h2c_pkt, value)                        \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 18, 1, value)
+#define FW_ACCESS_TEST_GET_ACCESS_PAGE3(h2c_pkt)                               \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 19, 1)
+#define FW_ACCESS_TEST_SET_ACCESS_PAGE3(h2c_pkt, value)                        \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 19, 1, value)
+#define FW_ACCESS_TEST_GET_ACCESS_PAGE4(h2c_pkt)                               \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 20, 1)
+#define FW_ACCESS_TEST_SET_ACCESS_PAGE4(h2c_pkt, value)                        \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 20, 1, value)
+#define FW_ACCESS_TEST_GET_ACCESS_PAGE5(h2c_pkt)                               \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 21, 1)
+#define FW_ACCESS_TEST_SET_ACCESS_PAGE5(h2c_pkt, value)                        \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 21, 1, value)
+#define FW_ACCESS_TEST_GET_ACCESS_PAGE6(h2c_pkt)                               \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 22, 1)
+#define FW_ACCESS_TEST_SET_ACCESS_PAGE6(h2c_pkt, value)                        \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 22, 1, value)
+#define FW_ACCESS_TEST_GET_ACCESS_PAGE7(h2c_pkt)                               \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 23, 1)
+#define FW_ACCESS_TEST_SET_ACCESS_PAGE7(h2c_pkt, value)                        \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 23, 1, value)
+#define CH_SWITCH_GET_START(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 0, 1)
+#define CH_SWITCH_SET_START(h2c_pkt, value)                                    \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 0, 1, value)
+#define CH_SWITCH_GET_DEST_CH_EN(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 1, 1)
+#define CH_SWITCH_SET_DEST_CH_EN(h2c_pkt, value)                               \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 1, 1, value)
+#define CH_SWITCH_GET_ABSOLUTE_TIME(h2c_pkt)                                   \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 2, 1)
+#define CH_SWITCH_SET_ABSOLUTE_TIME(h2c_pkt, value)                            \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 2, 1, value)
+#define CH_SWITCH_GET_PERIODIC_OPT(h2c_pkt)                                    \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 3, 2)
+#define CH_SWITCH_SET_PERIODIC_OPT(h2c_pkt, value)                             \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 3, 2, value)
+#define CH_SWITCH_GET_INFO_LOC(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 8, 8)
+#define CH_SWITCH_SET_INFO_LOC(h2c_pkt, value)                                 \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 8, 8, value)
+#define CH_SWITCH_GET_CH_NUM(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 16, 8)
+#define CH_SWITCH_SET_CH_NUM(h2c_pkt, value)                                   \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 16, 8, value)
+#define CH_SWITCH_GET_PRI_CH_IDX(h2c_pkt)                                      \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 24, 4)
+#define CH_SWITCH_SET_PRI_CH_IDX(h2c_pkt, value)                               \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 24, 4, value)
+#define CH_SWITCH_GET_DEST_BW(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 28, 4)
+#define CH_SWITCH_SET_DEST_BW(h2c_pkt, value)                                  \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 28, 4, value)
+#define CH_SWITCH_GET_DEST_CH(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X0C, 0, 8)
+#define CH_SWITCH_SET_DEST_CH(h2c_pkt, value)                                  \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X0C, 0, 8, value)
+#define CH_SWITCH_GET_NORMAL_PERIOD(h2c_pkt)                                   \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X0C, 8, 6)
+#define CH_SWITCH_SET_NORMAL_PERIOD(h2c_pkt, value)                            \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X0C, 8, 6, value)
+#define CH_SWITCH_GET_NORMAL_PERIOD_SEL(h2c_pkt)                               \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X0C, 14, 2)
+#define CH_SWITCH_SET_NORMAL_PERIOD_SEL(h2c_pkt, value)                        \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X0C, 14, 2, value)
+#define CH_SWITCH_GET_SLOW_PERIOD(h2c_pkt)                                     \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X0C, 16, 6)
+#define CH_SWITCH_SET_SLOW_PERIOD(h2c_pkt, value)                              \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X0C, 16, 6, value)
+#define CH_SWITCH_GET_SLOW_PERIOD_SEL(h2c_pkt)                                 \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X0C, 22, 2)
+#define CH_SWITCH_SET_SLOW_PERIOD_SEL(h2c_pkt, value)                          \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X0C, 22, 2, value)
+#define CH_SWITCH_GET_NORMAL_CYCLE(h2c_pkt)                                    \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X0C, 24, 8)
+#define CH_SWITCH_SET_NORMAL_CYCLE(h2c_pkt, value)                             \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X0C, 24, 8, value)
+#define CH_SWITCH_GET_TSF_HIGH(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X10, 0, 32)
+#define CH_SWITCH_SET_TSF_HIGH(h2c_pkt, value)                                 \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X10, 0, 32, value)
+#define CH_SWITCH_GET_TSF_LOW(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X14, 0, 32)
+#define CH_SWITCH_SET_TSF_LOW(h2c_pkt, value)                                  \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X14, 0, 32, value)
+#define CH_SWITCH_GET_INFO_SIZE(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X18, 0, 16)
+#define CH_SWITCH_SET_INFO_SIZE(h2c_pkt, value)                                \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X18, 0, 16, value)
+#define UPDATE_BEACON_PARSING_INFO_GET_FUNC_EN(h2c_pkt)                        \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 0, 1)
+#define UPDATE_BEACON_PARSING_INFO_SET_FUNC_EN(h2c_pkt, value)                 \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 0, 1, value)
+#define UPDATE_BEACON_PARSING_INFO_GET_SIZE_TH(h2c_pkt)                        \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 8, 4)
+#define UPDATE_BEACON_PARSING_INFO_SET_SIZE_TH(h2c_pkt, value)                 \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 8, 4, value)
+#define UPDATE_BEACON_PARSING_INFO_GET_TIMEOUT(h2c_pkt)                        \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 12, 4)
+#define UPDATE_BEACON_PARSING_INFO_SET_TIMEOUT(h2c_pkt, value)                 \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 12, 4, value)
+#define UPDATE_BEACON_PARSING_INFO_GET_IE_ID_BMP_0(h2c_pkt)                    \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X0C, 0, 32)
+#define UPDATE_BEACON_PARSING_INFO_SET_IE_ID_BMP_0(h2c_pkt, value)             \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X0C, 0, 32, value)
+#define UPDATE_BEACON_PARSING_INFO_GET_IE_ID_BMP_1(h2c_pkt)                    \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X10, 0, 32)
+#define UPDATE_BEACON_PARSING_INFO_SET_IE_ID_BMP_1(h2c_pkt, value)             \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X10, 0, 32, value)
+#define UPDATE_BEACON_PARSING_INFO_GET_IE_ID_BMP_2(h2c_pkt)                    \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X14, 0, 32)
+#define UPDATE_BEACON_PARSING_INFO_SET_IE_ID_BMP_2(h2c_pkt, value)             \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X14, 0, 32, value)
+#define UPDATE_BEACON_PARSING_INFO_GET_IE_ID_BMP_3(h2c_pkt)                    \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X18, 0, 32)
+#define UPDATE_BEACON_PARSING_INFO_SET_IE_ID_BMP_3(h2c_pkt, value)             \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X18, 0, 32, value)
+#define UPDATE_BEACON_PARSING_INFO_GET_IE_ID_BMP_4(h2c_pkt)                    \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X1C, 0, 32)
+#define UPDATE_BEACON_PARSING_INFO_SET_IE_ID_BMP_4(h2c_pkt, value)             \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X1C, 0, 32, value)
+#define CFG_PARAM_GET_NUM(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 0, 16)
+#define CFG_PARAM_SET_NUM(h2c_pkt, value)                                      \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 0, 16, value)
+#define CFG_PARAM_GET_INIT_CASE(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 16, 1)
+#define CFG_PARAM_SET_INIT_CASE(h2c_pkt, value)                                \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 16, 1, value)
+#define CFG_PARAM_GET_LOC(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 24, 8)
+#define CFG_PARAM_SET_LOC(h2c_pkt, value)                                      \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 24, 8, value)
+#define UPDATE_DATAPACK_GET_SIZE(h2c_pkt)                                      \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 0, 16)
+#define UPDATE_DATAPACK_SET_SIZE(h2c_pkt, value)                               \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 0, 16, value)
+#define UPDATE_DATAPACK_GET_DATAPACK_ID(h2c_pkt)                               \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 16, 8)
+#define UPDATE_DATAPACK_SET_DATAPACK_ID(h2c_pkt, value)                        \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 16, 8, value)
+#define UPDATE_DATAPACK_GET_DATAPACK_LOC(h2c_pkt)                              \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 24, 8)
+#define UPDATE_DATAPACK_SET_DATAPACK_LOC(h2c_pkt, value)                       \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 24, 8, value)
+#define UPDATE_DATAPACK_GET_DATAPACK_SEGMENT(h2c_pkt)                          \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X0C, 0, 8)
+#define UPDATE_DATAPACK_SET_DATAPACK_SEGMENT(h2c_pkt, value)                   \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X0C, 0, 8, value)
+#define UPDATE_DATAPACK_GET_END_SEGMENT(h2c_pkt)                               \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X0C, 8, 1)
+#define UPDATE_DATAPACK_SET_END_SEGMENT(h2c_pkt, value)                        \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X0C, 8, 1, value)
+#define RUN_DATAPACK_GET_DATAPACK_ID(h2c_pkt)                                  \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 0, 8)
+#define RUN_DATAPACK_SET_DATAPACK_ID(h2c_pkt, value)                           \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 0, 8, value)
+#define DOWNLOAD_FLASH_GET_SPI_CMD(h2c_pkt)                                    \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 0, 8)
+#define DOWNLOAD_FLASH_SET_SPI_CMD(h2c_pkt, value)                             \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 0, 8, value)
+#define DOWNLOAD_FLASH_GET_LOCATION(h2c_pkt)                                   \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 8, 16)
+#define DOWNLOAD_FLASH_SET_LOCATION(h2c_pkt, value)                            \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 8, 16, value)
+#define DOWNLOAD_FLASH_GET_SIZE(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X0C, 0, 32)
+#define DOWNLOAD_FLASH_SET_SIZE(h2c_pkt, value)                                \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X0C, 0, 32, value)
+#define DOWNLOAD_FLASH_GET_START_ADDR(h2c_pkt)                                 \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X10, 0, 32)
+#define DOWNLOAD_FLASH_SET_START_ADDR(h2c_pkt, value)                          \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X10, 0, 32, value)
+#define UPDATE_PKT_GET_SIZE(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 0, 16)
+#define UPDATE_PKT_SET_SIZE(h2c_pkt, value)                                    \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 0, 16, value)
+#define UPDATE_PKT_GET_ID(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 16, 8)
+#define UPDATE_PKT_SET_ID(h2c_pkt, value)                                      \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 16, 8, value)
+#define UPDATE_PKT_GET_LOC(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 24, 8)
+#define UPDATE_PKT_SET_LOC(h2c_pkt, value)                                     \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 24, 8, value)
+#define GENERAL_INFO_GET_FW_TX_BOUNDARY(h2c_pkt)                               \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 16, 8)
+#define GENERAL_INFO_SET_FW_TX_BOUNDARY(h2c_pkt, value)                        \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 16, 8, value)
+#define IQK_GET_CLEAR(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 0, 1)
+#define IQK_SET_CLEAR(h2c_pkt, value)                                          \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 0, 1, value)
+#define IQK_GET_SEGMENT_IQK(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 1, 1)
+#define IQK_SET_SEGMENT_IQK(h2c_pkt, value)                                    \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 1, 1, value)
+#define PWR_TRK_GET_ENABLE_A(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 0, 1)
+#define PWR_TRK_SET_ENABLE_A(h2c_pkt, value)                                   \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 0, 1, value)
+#define PWR_TRK_GET_ENABLE_B(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 1, 1)
+#define PWR_TRK_SET_ENABLE_B(h2c_pkt, value)                                   \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 1, 1, value)
+#define PWR_TRK_GET_ENABLE_C(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 2, 1)
+#define PWR_TRK_SET_ENABLE_C(h2c_pkt, value)                                   \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 2, 1, value)
+#define PWR_TRK_GET_ENABLE_D(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 3, 1)
+#define PWR_TRK_SET_ENABLE_D(h2c_pkt, value)                                   \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 3, 1, value)
+#define PWR_TRK_GET_TYPE(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 4, 3)
+#define PWR_TRK_SET_TYPE(h2c_pkt, value)                                       \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 4, 3, value)
+#define PWR_TRK_GET_BBSWING_INDEX(h2c_pkt)                                     \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 8, 8)
+#define PWR_TRK_SET_BBSWING_INDEX(h2c_pkt, value)                              \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 8, 8, value)
+#define PWR_TRK_GET_TX_PWR_INDEX_A(h2c_pkt)                                    \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X0C, 0, 8)
+#define PWR_TRK_SET_TX_PWR_INDEX_A(h2c_pkt, value)                             \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X0C, 0, 8, value)
+#define PWR_TRK_GET_OFFSET_VALUE_A(h2c_pkt)                                    \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X0C, 8, 8)
+#define PWR_TRK_SET_OFFSET_VALUE_A(h2c_pkt, value)                             \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X0C, 8, 8, value)
+#define PWR_TRK_GET_TSSI_VALUE_A(h2c_pkt)                                      \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X0C, 16, 8)
+#define PWR_TRK_SET_TSSI_VALUE_A(h2c_pkt, value)                               \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X0C, 16, 8, value)
+#define PWR_TRK_GET_TX_PWR_INDEX_B(h2c_pkt)                                    \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X10, 0, 8)
+#define PWR_TRK_SET_TX_PWR_INDEX_B(h2c_pkt, value)                             \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X10, 0, 8, value)
+#define PWR_TRK_GET_OFFSET_VALUE_B(h2c_pkt)                                    \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X10, 8, 8)
+#define PWR_TRK_SET_OFFSET_VALUE_B(h2c_pkt, value)                             \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X10, 8, 8, value)
+#define PWR_TRK_GET_TSSI_VALUE_B(h2c_pkt)                                      \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X10, 16, 8)
+#define PWR_TRK_SET_TSSI_VALUE_B(h2c_pkt, value)                               \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X10, 16, 8, value)
+#define PWR_TRK_GET_TX_PWR_INDEX_C(h2c_pkt)                                    \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X14, 0, 8)
+#define PWR_TRK_SET_TX_PWR_INDEX_C(h2c_pkt, value)                             \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X14, 0, 8, value)
+#define PWR_TRK_GET_OFFSET_VALUE_C(h2c_pkt)                                    \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X14, 8, 8)
+#define PWR_TRK_SET_OFFSET_VALUE_C(h2c_pkt, value)                             \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X14, 8, 8, value)
+#define PWR_TRK_GET_TSSI_VALUE_C(h2c_pkt)                                      \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X14, 16, 8)
+#define PWR_TRK_SET_TSSI_VALUE_C(h2c_pkt, value)                               \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X14, 16, 8, value)
+#define PWR_TRK_GET_TX_PWR_INDEX_D(h2c_pkt)                                    \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X18, 0, 8)
+#define PWR_TRK_SET_TX_PWR_INDEX_D(h2c_pkt, value)                             \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X18, 0, 8, value)
+#define PWR_TRK_GET_OFFSET_VALUE_D(h2c_pkt)                                    \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X18, 8, 8)
+#define PWR_TRK_SET_OFFSET_VALUE_D(h2c_pkt, value)                             \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X18, 8, 8, value)
+#define PWR_TRK_GET_TSSI_VALUE_D(h2c_pkt)                                      \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X18, 16, 8)
+#define PWR_TRK_SET_TSSI_VALUE_D(h2c_pkt, value)                               \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X18, 16, 8, value)
+#define PSD_GET_START_PSD(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 0, 16)
+#define PSD_SET_START_PSD(h2c_pkt, value)                                      \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 0, 16, value)
+#define PSD_GET_END_PSD(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 16, 16)
+#define PSD_SET_END_PSD(h2c_pkt, value)                                        \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 16, 16, value)
+#define PHYDM_INFO_GET_REF_TYPE(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 0, 8)
+#define PHYDM_INFO_SET_REF_TYPE(h2c_pkt, value)                                \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 0, 8, value)
+#define PHYDM_INFO_GET_RF_TYPE(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 8, 8)
+#define PHYDM_INFO_SET_RF_TYPE(h2c_pkt, value)                                 \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 8, 8, value)
+#define PHYDM_INFO_GET_CUT_VER(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 16, 8)
+#define PHYDM_INFO_SET_CUT_VER(h2c_pkt, value)                                 \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 16, 8, value)
+#define PHYDM_INFO_GET_RX_ANT_STATUS(h2c_pkt)                                  \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 24, 4)
+#define PHYDM_INFO_SET_RX_ANT_STATUS(h2c_pkt, value)                           \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 24, 4, value)
+#define PHYDM_INFO_GET_TX_ANT_STATUS(h2c_pkt)                                  \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 28, 4)
+#define PHYDM_INFO_SET_TX_ANT_STATUS(h2c_pkt, value)                           \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 28, 4, value)
+#define FW_SNDING_GET_SU0(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 0, 1)
+#define FW_SNDING_SET_SU0(h2c_pkt, value)                                      \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 0, 1, value)
+#define FW_SNDING_GET_SU1(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 1, 1)
+#define FW_SNDING_SET_SU1(h2c_pkt, value)                                      \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 1, 1, value)
+#define FW_SNDING_GET_MU(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 2, 1)
+#define FW_SNDING_SET_MU(h2c_pkt, value)                                       \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 2, 1, value)
+#define FW_SNDING_GET_PERIOD(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 8, 8)
+#define FW_SNDING_SET_PERIOD(h2c_pkt, value)                                   \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 8, 8, value)
+#define FW_SNDING_GET_NDPA0_HEAD_PG(h2c_pkt)                                   \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 16, 8)
+#define FW_SNDING_SET_NDPA0_HEAD_PG(h2c_pkt, value)                            \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 16, 8, value)
+#define FW_SNDING_GET_NDPA1_HEAD_PG(h2c_pkt)                                   \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 24, 8)
+#define FW_SNDING_SET_NDPA1_HEAD_PG(h2c_pkt, value)                            \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 24, 8, value)
+#define FW_SNDING_GET_MU_NDPA_HEAD_PG(h2c_pkt)                                 \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0XC, 0, 8)
+#define FW_SNDING_SET_MU_NDPA_HEAD_PG(h2c_pkt, value)                          \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0XC, 0, 8, value)
+#define FW_SNDING_GET_RPT0_HEAD_PG(h2c_pkt)                                    \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0XC, 8, 8)
+#define FW_SNDING_SET_RPT0_HEAD_PG(h2c_pkt, value)                             \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0XC, 8, 8, value)
+#define FW_SNDING_GET_RPT1_HEAD_PG(h2c_pkt)                                    \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0XC, 16, 8)
+#define FW_SNDING_SET_RPT1_HEAD_PG(h2c_pkt, value)                             \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0XC, 16, 8, value)
+#define FW_SNDING_GET_RPT2_HEAD_PG(h2c_pkt)                                    \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0XC, 24, 8)
+#define FW_SNDING_SET_RPT2_HEAD_PG(h2c_pkt, value)                             \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0XC, 24, 8, value)
+#define FW_FWCTRL_GET_SEQ_NUM(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 0, 8)
+#define FW_FWCTRL_SET_SEQ_NUM(h2c_pkt, value)                                  \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 0, 8, value)
+#define FW_FWCTRL_GET_MORE_CONTENT(h2c_pkt)                                    \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 8, 1)
+#define FW_FWCTRL_SET_MORE_CONTENT(h2c_pkt, value)                             \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 8, 1, value)
+#define FW_FWCTRL_GET_CONTENT_IDX(h2c_pkt)                                     \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 9, 7)
+#define FW_FWCTRL_SET_CONTENT_IDX(h2c_pkt, value)                              \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 9, 7, value)
+#define FW_FWCTRL_GET_CLASS_ID(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 16, 8)
+#define FW_FWCTRL_SET_CLASS_ID(h2c_pkt, value)                                 \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 16, 8, value)
+#define FW_FWCTRL_GET_LENGTH(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 24, 8)
+#define FW_FWCTRL_SET_LENGTH(h2c_pkt, value)                                   \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 24, 8, value)
+#define FW_FWCTRL_GET_CONTENT(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X0C, 0, 32)
+#define FW_FWCTRL_SET_CONTENT(h2c_pkt, value)                                  \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X0C, 0, 32, value)
+#define P2PPS_GET_OFFLOAD_EN(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 0, 1)
+#define P2PPS_SET_OFFLOAD_EN(h2c_pkt, value)                                   \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 0, 1, value)
+#define P2PPS_GET_ROLE(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 1, 1)
+#define P2PPS_SET_ROLE(h2c_pkt, value)                                         \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 1, 1, value)
+#define P2PPS_GET_CTWINDOW_EN(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 2, 1)
+#define P2PPS_SET_CTWINDOW_EN(h2c_pkt, value)                                  \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 2, 1, value)
+#define P2PPS_GET_NOA_EN(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 3, 1)
+#define P2PPS_SET_NOA_EN(h2c_pkt, value)                                       \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 3, 1, value)
+#define P2PPS_GET_NOA_SEL(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 4, 1)
+#define P2PPS_SET_NOA_SEL(h2c_pkt, value)                                      \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 4, 1, value)
+#define P2PPS_GET_ALLSTASLEEP(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 5, 1)
+#define P2PPS_SET_ALLSTASLEEP(h2c_pkt, value)                                  \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 5, 1, value)
+#define P2PPS_GET_DISCOVERY(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 6, 1)
+#define P2PPS_SET_DISCOVERY(h2c_pkt, value)                                    \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 6, 1, value)
+#define P2PPS_GET_DISABLE_CLOSERF(h2c_pkt)                                     \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 7, 1)
+#define P2PPS_SET_DISABLE_CLOSERF(h2c_pkt, value)                              \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 7, 1, value)
+#define P2PPS_GET_P2P_PORT_ID(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 8, 8)
+#define P2PPS_SET_P2P_PORT_ID(h2c_pkt, value)                                  \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 8, 8, value)
+#define P2PPS_GET_P2P_GROUP(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 16, 8)
+#define P2PPS_SET_P2P_GROUP(h2c_pkt, value)                                    \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 16, 8, value)
+#define P2PPS_GET_P2P_MACID(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 24, 8)
+#define P2PPS_SET_P2P_MACID(h2c_pkt, value)                                    \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 24, 8, value)
+#define P2PPS_GET_CTWINDOW_LENGTH(h2c_pkt)                                     \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X0C, 0, 8)
+#define P2PPS_SET_CTWINDOW_LENGTH(h2c_pkt, value)                              \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X0C, 0, 8, value)
+#define P2PPS_GET_NOA_DURATION_PARA(h2c_pkt)                                   \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X10, 0, 32)
+#define P2PPS_SET_NOA_DURATION_PARA(h2c_pkt, value)                            \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X10, 0, 32, value)
+#define P2PPS_GET_NOA_INTERVAL_PARA(h2c_pkt)                                   \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X14, 0, 32)
+#define P2PPS_SET_NOA_INTERVAL_PARA(h2c_pkt, value)                            \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X14, 0, 32, value)
+#define P2PPS_GET_NOA_START_TIME_PARA(h2c_pkt)                                 \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X18, 0, 32)
+#define P2PPS_SET_NOA_START_TIME_PARA(h2c_pkt, value)                          \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X18, 0, 32, value)
+#define P2PPS_GET_NOA_COUNT_PARA(h2c_pkt)                                      \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X1C, 0, 32)
+#define P2PPS_SET_NOA_COUNT_PARA(h2c_pkt, value)                               \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X1C, 0, 32, value)
+#define BT_COEX_GET_DATA_START(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 0, 8)
+#define BT_COEX_SET_DATA_START(h2c_pkt, value)                                 \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 0, 8, value)
+#define NAN_CTRL_GET_NAN_EN(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 0, 2)
+#define NAN_CTRL_SET_NAN_EN(h2c_pkt, value)                                    \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 0, 2, value)
+#define NAN_CTRL_GET_WARMUP_TIMER_FLAG(h2c_pkt)                                \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 2, 1)
+#define NAN_CTRL_SET_WARMUP_TIMER_FLAG(h2c_pkt, value)                         \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 2, 1, value)
+#define NAN_CTRL_GET_SUPPORT_BAND(h2c_pkt)                                     \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 8, 2)
+#define NAN_CTRL_SET_SUPPORT_BAND(h2c_pkt, value)                              \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 8, 2, value)
+#define NAN_CTRL_GET_DISABLE_2G_DISC_BCN(h2c_pkt)                              \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 10, 1)
+#define NAN_CTRL_SET_DISABLE_2G_DISC_BCN(h2c_pkt, value)                       \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 10, 1, value)
+#define NAN_CTRL_GET_DISABLE_5G_DISC_BCN(h2c_pkt)                              \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 11, 1)
+#define NAN_CTRL_SET_DISABLE_5G_DISC_BCN(h2c_pkt, value)                       \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 11, 1, value)
+#define NAN_CTRL_GET_BCN_RSVD_PAGE_OFFSET(h2c_pkt)                             \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 16, 8)
+#define NAN_CTRL_SET_BCN_RSVD_PAGE_OFFSET(h2c_pkt, value)                      \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 16, 8, value)
+#define NAN_CTRL_GET_CHANNEL_2G(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 24, 8)
+#define NAN_CTRL_SET_CHANNEL_2G(h2c_pkt, value)                                \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 24, 8, value)
+#define NAN_CTRL_GET_CHANNEL_5G(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X0C, 0, 8)
+#define NAN_CTRL_SET_CHANNEL_5G(h2c_pkt, value)                                \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X0C, 0, 8, value)
+#define NAN_CTRL_GET_MASTERPREFERENCE_VALUE(h2c_pkt)                           \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X0C, 8, 8)
+#define NAN_CTRL_SET_MASTERPREFERENCE_VALUE(h2c_pkt, value)                    \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X0C, 8, 8, value)
+#define NAN_CTRL_GET_RANDOMFACTOR_VALUE(h2c_pkt)                               \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X0C, 16, 8)
+#define NAN_CTRL_SET_RANDOMFACTOR_VALUE(h2c_pkt, value)                        \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X0C, 16, 8, value)
+#define NAN_CHANNEL_PLAN_0_GET_CHANNEL_NUMBER_0(h2c_pkt)                       \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 0, 8)
+#define NAN_CHANNEL_PLAN_0_SET_CHANNEL_NUMBER_0(h2c_pkt, value)                \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 0, 8, value)
+#define NAN_CHANNEL_PLAN_0_GET_UNPAUSE_MACID_0(h2c_pkt)                        \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 8, 8)
+#define NAN_CHANNEL_PLAN_0_SET_UNPAUSE_MACID_0(h2c_pkt, value)                 \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 8, 8, value)
+#define NAN_CHANNEL_PLAN_0_GET_START_TIME_SLOT_0(h2c_pkt)                      \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X0C, 0, 16)
+#define NAN_CHANNEL_PLAN_0_SET_START_TIME_SLOT_0(h2c_pkt, value)               \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X0C, 0, 16, value)
+#define NAN_CHANNEL_PLAN_0_GET_DURATION_0(h2c_pkt)                             \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X0C, 16, 16)
+#define NAN_CHANNEL_PLAN_0_SET_DURATION_0(h2c_pkt, value)                      \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X0C, 16, 16, value)
+#define NAN_CHANNEL_PLAN_0_GET_CHANNEL_NUMBER_1(h2c_pkt)                       \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X10, 0, 8)
+#define NAN_CHANNEL_PLAN_0_SET_CHANNEL_NUMBER_1(h2c_pkt, value)                \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X10, 0, 8, value)
+#define NAN_CHANNEL_PLAN_0_GET_UNPAUSE_MACID_1(h2c_pkt)                        \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X10, 8, 8)
+#define NAN_CHANNEL_PLAN_0_SET_UNPAUSE_MACID_1(h2c_pkt, value)                 \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X10, 8, 8, value)
+#define NAN_CHANNEL_PLAN_0_GET_START_TIME_SLOT_1(h2c_pkt)                      \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X14, 0, 16)
+#define NAN_CHANNEL_PLAN_0_SET_START_TIME_SLOT_1(h2c_pkt, value)               \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X14, 0, 16, value)
+#define NAN_CHANNEL_PLAN_0_GET_DURATION_1(h2c_pkt)                             \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X14, 16, 16)
+#define NAN_CHANNEL_PLAN_0_SET_DURATION_1(h2c_pkt, value)                      \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X14, 16, 16, value)
+#define NAN_CHANNEL_PLAN_0_GET_CHANNEL_NUMBER_2(h2c_pkt)                       \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X18, 0, 8)
+#define NAN_CHANNEL_PLAN_0_SET_CHANNEL_NUMBER_2(h2c_pkt, value)                \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X18, 0, 8, value)
+#define NAN_CHANNEL_PLAN_0_GET_UNPAUSE_MACID_2(h2c_pkt)                        \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X18, 8, 8)
+#define NAN_CHANNEL_PLAN_0_SET_UNPAUSE_MACID_2(h2c_pkt, value)                 \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X18, 8, 8, value)
+#define NAN_CHANNEL_PLAN_0_GET_START_TIME_SLOT_2(h2c_pkt)                      \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X1C, 0, 16)
+#define NAN_CHANNEL_PLAN_0_SET_START_TIME_SLOT_2(h2c_pkt, value)               \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X1C, 0, 16, value)
+#define NAN_CHANNEL_PLAN_0_GET_DURATION_2(h2c_pkt)                             \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X1C, 16, 16)
+#define NAN_CHANNEL_PLAN_0_SET_DURATION_2(h2c_pkt, value)                      \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X1C, 16, 16, value)
+#define NAN_CHANNEL_PLAN_1_GET_CHANNEL_NUMBER_3(h2c_pkt)                       \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 0, 8)
+#define NAN_CHANNEL_PLAN_1_SET_CHANNEL_NUMBER_3(h2c_pkt, value)                \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 0, 8, value)
+#define NAN_CHANNEL_PLAN_1_GET_UNPAUSE_MACID_3(h2c_pkt)                        \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 8, 8)
+#define NAN_CHANNEL_PLAN_1_SET_UNPAUSE_MACID_3(h2c_pkt, value)                 \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 8, 8, value)
+#define NAN_CHANNEL_PLAN_1_GET_START_TIME_SLOT_3(h2c_pkt)                      \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X0C, 0, 16)
+#define NAN_CHANNEL_PLAN_1_SET_START_TIME_SLOT_3(h2c_pkt, value)               \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X0C, 0, 16, value)
+#define NAN_CHANNEL_PLAN_1_GET_DURATION_3(h2c_pkt)                             \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X0C, 16, 16)
+#define NAN_CHANNEL_PLAN_1_SET_DURATION_3(h2c_pkt, value)                      \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X0C, 16, 16, value)
+#define NAN_CHANNEL_PLAN_1_GET_CHANNEL_NUMBER_4(h2c_pkt)                       \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X10, 0, 8)
+#define NAN_CHANNEL_PLAN_1_SET_CHANNEL_NUMBER_4(h2c_pkt, value)                \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X10, 0, 8, value)
+#define NAN_CHANNEL_PLAN_1_GET_UNPAUSE_MACID_4(h2c_pkt)                        \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X10, 8, 8)
+#define NAN_CHANNEL_PLAN_1_SET_UNPAUSE_MACID_4(h2c_pkt, value)                 \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X10, 8, 8, value)
+#define NAN_CHANNEL_PLAN_1_GET_START_TIME_SLOT_4(h2c_pkt)                      \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X14, 0, 16)
+#define NAN_CHANNEL_PLAN_1_SET_START_TIME_SLOT_4(h2c_pkt, value)               \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X14, 0, 16, value)
+#define NAN_CHANNEL_PLAN_1_GET_DURATION_4(h2c_pkt)                             \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X14, 16, 16)
+#define NAN_CHANNEL_PLAN_1_SET_DURATION_4(h2c_pkt, value)                      \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X14, 16, 16, value)
+#define NAN_CHANNEL_PLAN_1_GET_CHANNEL_NUMBER_5(h2c_pkt)                       \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X18, 0, 8)
+#define NAN_CHANNEL_PLAN_1_SET_CHANNEL_NUMBER_5(h2c_pkt, value)                \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X18, 0, 8, value)
+#define NAN_CHANNEL_PLAN_1_GET_UNPAUSE_MACID_5(h2c_pkt)                        \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X18, 8, 8)
+#define NAN_CHANNEL_PLAN_1_SET_UNPAUSE_MACID_5(h2c_pkt, value)                 \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X18, 8, 8, value)
+#define NAN_CHANNEL_PLAN_1_GET_START_TIME_SLOT_5(h2c_pkt)                      \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X1C, 0, 16)
+#define NAN_CHANNEL_PLAN_1_SET_START_TIME_SLOT_5(h2c_pkt, value)               \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X1C, 0, 16, value)
+#define NAN_CHANNEL_PLAN_1_GET_DURATION_5(h2c_pkt)                             \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X1C, 16, 16)
+#define NAN_CHANNEL_PLAN_1_SET_DURATION_5(h2c_pkt, value)                      \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X1C, 16, 16, value)
+#endif
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/halmac/halmac_gpio_cmd.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/halmac/halmac_gpio_cmd.h
--- linux-5.6.3/3rdparty/rtl8821ce/hal/halmac/halmac_gpio_cmd.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/halmac/halmac_gpio_cmd.h	2020-04-10 16:35:06.811659835 +0300
@@ -0,0 +1,101 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ ******************************************************************************/
+
+#ifndef HALMAC_GPIO_CMD
+#define HALMAC_GPIO_CMD
+
+#include "halmac_2_platform.h"
+
+/* GPIO ID */
+#define HALMAC_GPIO0		0
+#define HALMAC_GPIO1		1
+#define HALMAC_GPIO2		2
+#define HALMAC_GPIO3		3
+#define HALMAC_GPIO4		4
+#define HALMAC_GPIO5		5
+#define HALMAC_GPIO6		6
+#define HALMAC_GPIO7		7
+#define HALMAC_GPIO8		8
+#define HALMAC_GPIO9		9
+#define HALMAC_GPIO10		10
+#define HALMAC_GPIO11		11
+#define HALMAC_GPIO12		12
+#define HALMAC_GPIO13		13
+#define HALMAC_GPIO14		14
+#define HALMAC_GPIO15		15
+#define HALMAC_GPIO_NUM		16
+
+/* GPIO type */
+#define HALMAC_GPIO_IN		0
+#define HALMAC_GPIO_OUT		1
+#define HALMAC_GPIO_IN_OUT	2
+
+/* Function name */
+#define HALMAC_WL_HWPDN			0
+#define HALMAC_BT_HWPDN			1
+#define HALMAC_BT_GPIO			2
+#define HALMAC_WL_HW_EXTWOL		3
+#define HALMAC_BT_HW_EXTWOL		4
+#define HALMAC_BT_SFLASH		5
+#define HALMAC_WL_SFLASH		6
+#define HALMAC_WL_LED			7
+#define HALMAC_SDIO_INT			8
+#define HALMAC_UART0			9
+#define HALMAC_EEPROM			10
+#define HALMAC_JTAG			11
+#define HALMAC_LTE_COEX_UART		12
+#define HALMAC_3W_LTE_WL_GPIO		13
+#define HALMAC_GPIO2_3_WL_CTRL_EN	14
+#define HALMAC_GPIO13_14_WL_CTRL_EN	15
+#define HALMAC_DBG_GNT_WL_BT		16
+#define HALMAC_BT_3DDLS_A		17
+#define HALMAC_BT_3DDLS_B		18
+#define HALMAC_BT_PTA			19
+#define HALMAC_WL_PTA			20
+#define HALMAC_WL_UART			21
+#define HALMAC_WLMAC_DBG		22
+#define HALMAC_WLPHY_DBG		23
+#define HALMAC_BT_DBG			24
+#define HALMAC_WLPHY_RFE_CTRL2GPIO	25
+#define HALMAC_EXT_XTAL			26
+#define HALMAC_SW_IO			27
+#define HALMAC_BT_SDIO_INT		28
+#define HALMAC_BT_JTAG			29
+#define HALMAC_WL_JTAG			30
+#define HALMAC_BT_RF			31
+#define HALMAC_WLPHY_RFE_CTRL2GPIO_2	32
+#define HALMAC_MAILBOX_3W		33
+#define HALMAC_MAILBOX_1W		34
+#define HALMAC_SW_DPDT_SEL		35
+#define HALMAC_BT_DPDT_SEL		36
+#define HALMAC_WL_DPDT_SEL		37
+#define HALMAC_BT_PAPE_SEL		38
+#define HALMAC_SW_PAPE_SEL		39
+#define HALMAC_WLBT_PAPE_SEL		40
+#define HALMAC_SW_LNAON_SET		41
+#define HALMAC_BT_LNAON_SEL		42
+#define HALMAC_WLBT_LNAON_SEL		43
+#define HALMAC_SWR_CTRL_EN		44
+
+struct halmac_gpio_pimux_list {
+	u16 func;
+	u8 id;
+	u8 type;
+	u16 offset;
+	u8 msk;
+	u8 value;
+};
+
+#endif
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/halmac/halmac_h2c_extra_info_ap.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/halmac/halmac_h2c_extra_info_ap.h
--- linux-5.6.3/3rdparty/rtl8821ce/hal/halmac/halmac_h2c_extra_info_ap.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/halmac/halmac_h2c_extra_info_ap.h	2020-04-10 16:35:06.812659881 +0300
@@ -0,0 +1,220 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ ******************************************************************************/
+
+#ifndef _HAL_H2CEXTRAINFO_H2C_C2H_AP_H_
+#define _HAL_H2CEXTRAINFO_H2C_C2H_AP_H_
+#define PARAM_INFO_GET_LEN(extra_info) GET_C2H_FIELD(extra_info + 0X00, 0, 8)
+#define PARAM_INFO_SET_LEN(extra_info, value)                                  \
+	SET_C2H_FIELD_CLR(extra_info + 0X00, 0, 8, value)
+#define PARAM_INFO_SET_LEN_NO_CLR(extra_info, value)                           \
+	SET_C2H_FIELD_NO_CLR(extra_info + 0X00, 0, 8, value)
+#define PARAM_INFO_GET_IO_CMD(extra_info) GET_C2H_FIELD(extra_info + 0X00, 8, 7)
+#define PARAM_INFO_SET_IO_CMD(extra_info, value)                               \
+	SET_C2H_FIELD_CLR(extra_info + 0X00, 8, 7, value)
+#define PARAM_INFO_SET_IO_CMD_NO_CLR(extra_info, value)                        \
+	SET_C2H_FIELD_NO_CLR(extra_info + 0X00, 8, 7, value)
+#define PARAM_INFO_GET_MSK_EN(extra_info)                                      \
+	GET_C2H_FIELD(extra_info + 0X00, 15, 1)
+#define PARAM_INFO_SET_MSK_EN(extra_info, value)                               \
+	SET_C2H_FIELD_CLR(extra_info + 0X00, 15, 1, value)
+#define PARAM_INFO_SET_MSK_EN_NO_CLR(extra_info, value)                        \
+	SET_C2H_FIELD_NO_CLR(extra_info + 0X00, 15, 1, value)
+#define PARAM_INFO_GET_LLT_PG_BNDY(extra_info)                                 \
+	GET_C2H_FIELD(extra_info + 0X00, 16, 8)
+#define PARAM_INFO_SET_LLT_PG_BNDY(extra_info, value)                          \
+	SET_C2H_FIELD_CLR(extra_info + 0X00, 16, 8, value)
+#define PARAM_INFO_SET_LLT_PG_BNDY_NO_CLR(extra_info, value)                   \
+	SET_C2H_FIELD_NO_CLR(extra_info + 0X00, 16, 8, value)
+#define PARAM_INFO_GET_EFUSE_RSVDPAGE_LOC(extra_info)                          \
+	GET_C2H_FIELD(extra_info + 0X00, 16, 8)
+#define PARAM_INFO_SET_EFUSE_RSVDPAGE_LOC(extra_info, value)                   \
+	SET_C2H_FIELD_CLR(extra_info + 0X00, 16, 8, value)
+#define PARAM_INFO_SET_EFUSE_RSVDPAGE_LOC_NO_CLR(extra_info, value)            \
+	SET_C2H_FIELD_NO_CLR(extra_info + 0X00, 16, 8, value)
+#define PARAM_INFO_GET_EFUSE_PATCH_EN(extra_info)                              \
+	GET_C2H_FIELD(extra_info + 0X00, 16, 8)
+#define PARAM_INFO_SET_EFUSE_PATCH_EN(extra_info, value)                       \
+	SET_C2H_FIELD_CLR(extra_info + 0X00, 16, 8, value)
+#define PARAM_INFO_SET_EFUSE_PATCH_EN_NO_CLR(extra_info, value)                \
+	SET_C2H_FIELD_NO_CLR(extra_info + 0X00, 16, 8, value)
+#define PARAM_INFO_GET_RF_ADDR(extra_info)                                     \
+	GET_C2H_FIELD(extra_info + 0X00, 16, 8)
+#define PARAM_INFO_SET_RF_ADDR(extra_info, value)                              \
+	SET_C2H_FIELD_CLR(extra_info + 0X00, 16, 8, value)
+#define PARAM_INFO_SET_RF_ADDR_NO_CLR(extra_info, value)                       \
+	SET_C2H_FIELD_NO_CLR(extra_info + 0X00, 16, 8, value)
+#define PARAM_INFO_GET_IO_ADDR(extra_info)                                     \
+	GET_C2H_FIELD(extra_info + 0X00, 16, 16)
+#define PARAM_INFO_SET_IO_ADDR(extra_info, value)                              \
+	SET_C2H_FIELD_CLR(extra_info + 0X00, 16, 16, value)
+#define PARAM_INFO_SET_IO_ADDR_NO_CLR(extra_info, value)                       \
+	SET_C2H_FIELD_NO_CLR(extra_info + 0X00, 16, 16, value)
+#define PARAM_INFO_GET_DELAY_VAL(extra_info)                                   \
+	GET_C2H_FIELD(extra_info + 0X00, 16, 16)
+#define PARAM_INFO_SET_DELAY_VAL(extra_info, value)                            \
+	SET_C2H_FIELD_CLR(extra_info + 0X00, 16, 16, value)
+#define PARAM_INFO_SET_DELAY_VAL_NO_CLR(extra_info, value)                     \
+	SET_C2H_FIELD_NO_CLR(extra_info + 0X00, 16, 16, value)
+#define PARAM_INFO_GET_RF_PATH(extra_info)                                     \
+	GET_C2H_FIELD(extra_info + 0X00, 24, 8)
+#define PARAM_INFO_SET_RF_PATH(extra_info, value)                              \
+	SET_C2H_FIELD_CLR(extra_info + 0X00, 24, 8, value)
+#define PARAM_INFO_SET_RF_PATH_NO_CLR(extra_info, value)                       \
+	SET_C2H_FIELD_NO_CLR(extra_info + 0X00, 24, 8, value)
+#define PARAM_INFO_GET_DATA(extra_info) GET_C2H_FIELD(extra_info + 0X04, 0, 32)
+#define PARAM_INFO_SET_DATA(extra_info, value)                                 \
+	SET_C2H_FIELD_CLR(extra_info + 0X04, 0, 32, value)
+#define PARAM_INFO_SET_DATA_NO_CLR(extra_info, value)                          \
+	SET_C2H_FIELD_NO_CLR(extra_info + 0X04, 0, 32, value)
+#define PARAM_INFO_GET_MASK(extra_info) GET_C2H_FIELD(extra_info + 0X08, 0, 32)
+#define PARAM_INFO_SET_MASK(extra_info, value)                                 \
+	SET_C2H_FIELD_CLR(extra_info + 0X08, 0, 32, value)
+#define PARAM_INFO_SET_MASK_NO_CLR(extra_info, value)                          \
+	SET_C2H_FIELD_NO_CLR(extra_info + 0X08, 0, 32, value)
+#define CH_INFO_GET_CH(extra_info) GET_C2H_FIELD(extra_info + 0X00, 0, 8)
+#define CH_INFO_SET_CH(extra_info, value)                                      \
+	SET_C2H_FIELD_CLR(extra_info + 0X00, 0, 8, value)
+#define CH_INFO_SET_CH_NO_CLR(extra_info, value)                               \
+	SET_C2H_FIELD_NO_CLR(extra_info + 0X00, 0, 8, value)
+#define CH_INFO_GET_PRI_CH_IDX(extra_info)                                     \
+	GET_C2H_FIELD(extra_info + 0X00, 8, 4)
+#define CH_INFO_SET_PRI_CH_IDX(extra_info, value)                              \
+	SET_C2H_FIELD_CLR(extra_info + 0X00, 8, 4, value)
+#define CH_INFO_SET_PRI_CH_IDX_NO_CLR(extra_info, value)                       \
+	SET_C2H_FIELD_NO_CLR(extra_info + 0X00, 8, 4, value)
+#define CH_INFO_GET_BW(extra_info) GET_C2H_FIELD(extra_info + 0X00, 12, 4)
+#define CH_INFO_SET_BW(extra_info, value)                                      \
+	SET_C2H_FIELD_CLR(extra_info + 0X00, 12, 4, value)
+#define CH_INFO_SET_BW_NO_CLR(extra_info, value)                               \
+	SET_C2H_FIELD_NO_CLR(extra_info + 0X00, 12, 4, value)
+#define CH_INFO_GET_TIMEOUT(extra_info) GET_C2H_FIELD(extra_info + 0X00, 16, 8)
+#define CH_INFO_SET_TIMEOUT(extra_info, value)                                 \
+	SET_C2H_FIELD_CLR(extra_info + 0X00, 16, 8, value)
+#define CH_INFO_SET_TIMEOUT_NO_CLR(extra_info, value)                          \
+	SET_C2H_FIELD_NO_CLR(extra_info + 0X00, 16, 8, value)
+#define CH_INFO_GET_ACTION_ID(extra_info)                                      \
+	GET_C2H_FIELD(extra_info + 0X00, 24, 7)
+#define CH_INFO_SET_ACTION_ID(extra_info, value)                               \
+	SET_C2H_FIELD_CLR(extra_info + 0X00, 24, 7, value)
+#define CH_INFO_SET_ACTION_ID_NO_CLR(extra_info, value)                        \
+	SET_C2H_FIELD_NO_CLR(extra_info + 0X00, 24, 7, value)
+#define CH_INFO_GET_EXTRA_INFO(extra_info)                                     \
+	GET_C2H_FIELD(extra_info + 0X00, 31, 1)
+#define CH_INFO_SET_EXTRA_INFO(extra_info, value)                              \
+	SET_C2H_FIELD_CLR(extra_info + 0X00, 31, 1, value)
+#define CH_INFO_SET_EXTRA_INFO_NO_CLR(extra_info, value)                       \
+	SET_C2H_FIELD_NO_CLR(extra_info + 0X00, 31, 1, value)
+#define CH_EXTRA_INFO_GET_ID(extra_info) GET_C2H_FIELD(extra_info + 0X00, 0, 7)
+#define CH_EXTRA_INFO_SET_ID(extra_info, value)                                \
+	SET_C2H_FIELD_CLR(extra_info + 0X00, 0, 7, value)
+#define CH_EXTRA_INFO_SET_ID_NO_CLR(extra_info, value)                         \
+	SET_C2H_FIELD_NO_CLR(extra_info + 0X00, 0, 7, value)
+#define CH_EXTRA_INFO_GET_INFO(extra_info)                                     \
+	GET_C2H_FIELD(extra_info + 0X00, 7, 1)
+#define CH_EXTRA_INFO_SET_INFO(extra_info, value)                              \
+	SET_C2H_FIELD_CLR(extra_info + 0X00, 7, 1, value)
+#define CH_EXTRA_INFO_SET_INFO_NO_CLR(extra_info, value)                       \
+	SET_C2H_FIELD_NO_CLR(extra_info + 0X00, 7, 1, value)
+#define CH_EXTRA_INFO_GET_SIZE(extra_info)                                     \
+	GET_C2H_FIELD(extra_info + 0X00, 8, 8)
+#define CH_EXTRA_INFO_SET_SIZE(extra_info, value)                              \
+	SET_C2H_FIELD_CLR(extra_info + 0X00, 8, 8, value)
+#define CH_EXTRA_INFO_SET_SIZE_NO_CLR(extra_info, value)                       \
+	SET_C2H_FIELD_NO_CLR(extra_info + 0X00, 8, 8, value)
+#define CH_EXTRA_INFO_GET_DATA(extra_info)                                     \
+	GET_C2H_FIELD(extra_info + 0X00, 16, 1)
+#define CH_EXTRA_INFO_SET_DATA(extra_info, value)                              \
+	SET_C2H_FIELD_CLR(extra_info + 0X00, 16, 1, value)
+#define CH_EXTRA_INFO_SET_DATA_NO_CLR(extra_info, value)                       \
+	SET_C2H_FIELD_NO_CLR(extra_info + 0X00, 16, 1, value)
+#define HIOE_INSTRUCTION_INFO_GET_BYTEDATA_L(extra_info)                       \
+	GET_C2H_FIELD(extra_info + 0X00, 0, 16)
+#define HIOE_INSTRUCTION_INFO_SET_BYTEDATA_L(extra_info, value)                \
+	SET_C2H_FIELD_CLR(extra_info + 0X00, 0, 16, value)
+#define HIOE_INSTRUCTION_INFO_SET_BYTEDATA_L_NO_CLR(extra_info, value)         \
+	SET_C2H_FIELD_NO_CLR(extra_info + 0X00, 0, 16, value)
+#define HIOE_INSTRUCTION_INFO_GET_BITDATA(extra_info)                          \
+	GET_C2H_FIELD(extra_info + 0X00, 0, 16)
+#define HIOE_INSTRUCTION_INFO_SET_BITDATA(extra_info, value)                   \
+	SET_C2H_FIELD_CLR(extra_info + 0X00, 0, 16, value)
+#define HIOE_INSTRUCTION_INFO_SET_BITDATA_NO_CLR(extra_info, value)            \
+	SET_C2H_FIELD_NO_CLR(extra_info + 0X00, 0, 16, value)
+#define HIOE_INSTRUCTION_INFO_GET_BYTEDATA_H(extra_info)                       \
+	GET_C2H_FIELD(extra_info + 0X00, 16, 16)
+#define HIOE_INSTRUCTION_INFO_SET_BYTEDATA_H(extra_info, value)                \
+	SET_C2H_FIELD_CLR(extra_info + 0X00, 16, 16, value)
+#define HIOE_INSTRUCTION_INFO_SET_BYTEDATA_H_NO_CLR(extra_info, value)         \
+	SET_C2H_FIELD_NO_CLR(extra_info + 0X00, 16, 16, value)
+#define HIOE_INSTRUCTION_INFO_GET_BITMASK(extra_info)                          \
+	GET_C2H_FIELD(extra_info + 0X00, 16, 16)
+#define HIOE_INSTRUCTION_INFO_SET_BITMASK(extra_info, value)                   \
+	SET_C2H_FIELD_CLR(extra_info + 0X00, 16, 16, value)
+#define HIOE_INSTRUCTION_INFO_SET_BITMASK_NO_CLR(extra_info, value)            \
+	SET_C2H_FIELD_NO_CLR(extra_info + 0X00, 16, 16, value)
+#define HIOE_INSTRUCTION_INFO_GET_REG_ADDR(extra_info)                         \
+	GET_C2H_FIELD(extra_info + 0X04, 0, 22)
+#define HIOE_INSTRUCTION_INFO_SET_REG_ADDR(extra_info, value)                  \
+	SET_C2H_FIELD_CLR(extra_info + 0X04, 0, 22, value)
+#define HIOE_INSTRUCTION_INFO_SET_REG_ADDR_NO_CLR(extra_info, value)           \
+	SET_C2H_FIELD_NO_CLR(extra_info + 0X04, 0, 22, value)
+#define HIOE_INSTRUCTION_INFO_GET_DELAY_VALUE(extra_info)                      \
+	GET_C2H_FIELD(extra_info + 0X04, 0, 22)
+#define HIOE_INSTRUCTION_INFO_SET_DELAY_VALUE(extra_info, value)               \
+	SET_C2H_FIELD_CLR(extra_info + 0X04, 0, 22, value)
+#define HIOE_INSTRUCTION_INFO_SET_DELAY_VALUE_NO_CLR(extra_info, value)        \
+	SET_C2H_FIELD_NO_CLR(extra_info + 0X04, 0, 22, value)
+#define HIOE_INSTRUCTION_INFO_GET_MODE_SELECT(extra_info)                      \
+	GET_C2H_FIELD(extra_info + 0X04, 22, 1)
+#define HIOE_INSTRUCTION_INFO_SET_MODE_SELECT(extra_info, value)               \
+	SET_C2H_FIELD_CLR(extra_info + 0X04, 22, 1, value)
+#define HIOE_INSTRUCTION_INFO_SET_MODE_SELECT_NO_CLR(extra_info, value)        \
+	SET_C2H_FIELD_NO_CLR(extra_info + 0X04, 22, 1, value)
+#define HIOE_INSTRUCTION_INFO_GET_IO_DELAY(extra_info)                         \
+	GET_C2H_FIELD(extra_info + 0X04, 23, 1)
+#define HIOE_INSTRUCTION_INFO_SET_IO_DELAY(extra_info, value)                  \
+	SET_C2H_FIELD_CLR(extra_info + 0X04, 23, 1, value)
+#define HIOE_INSTRUCTION_INFO_SET_IO_DELAY_NO_CLR(extra_info, value)           \
+	SET_C2H_FIELD_NO_CLR(extra_info + 0X04, 23, 1, value)
+#define HIOE_INSTRUCTION_INFO_GET_BYTEMASK(extra_info)                         \
+	GET_C2H_FIELD(extra_info + 0X04, 24, 4)
+#define HIOE_INSTRUCTION_INFO_SET_BYTEMASK(extra_info, value)                  \
+	SET_C2H_FIELD_CLR(extra_info + 0X04, 24, 4, value)
+#define HIOE_INSTRUCTION_INFO_SET_BYTEMASK_NO_CLR(extra_info, value)           \
+	SET_C2H_FIELD_NO_CLR(extra_info + 0X04, 24, 4, value)
+#define HIOE_INSTRUCTION_INFO_GET_RD_EN(extra_info)                            \
+	GET_C2H_FIELD(extra_info + 0X04, 28, 1)
+#define HIOE_INSTRUCTION_INFO_SET_RD_EN(extra_info, value)                     \
+	SET_C2H_FIELD_CLR(extra_info + 0X04, 28, 1, value)
+#define HIOE_INSTRUCTION_INFO_SET_RD_EN_NO_CLR(extra_info, value)              \
+	SET_C2H_FIELD_NO_CLR(extra_info + 0X04, 28, 1, value)
+#define HIOE_INSTRUCTION_INFO_GET_WR_EN(extra_info)                            \
+	GET_C2H_FIELD(extra_info + 0X04, 29, 1)
+#define HIOE_INSTRUCTION_INFO_SET_WR_EN(extra_info, value)                     \
+	SET_C2H_FIELD_CLR(extra_info + 0X04, 29, 1, value)
+#define HIOE_INSTRUCTION_INFO_SET_WR_EN_NO_CLR(extra_info, value)              \
+	SET_C2H_FIELD_NO_CLR(extra_info + 0X04, 29, 1, value)
+#define HIOE_INSTRUCTION_INFO_GET_RAW_R(extra_info)                            \
+	GET_C2H_FIELD(extra_info + 0X04, 30, 1)
+#define HIOE_INSTRUCTION_INFO_SET_RAW_R(extra_info, value)                     \
+	SET_C2H_FIELD_CLR(extra_info + 0X04, 30, 1, value)
+#define HIOE_INSTRUCTION_INFO_SET_RAW_R_NO_CLR(extra_info, value)              \
+	SET_C2H_FIELD_NO_CLR(extra_info + 0X04, 30, 1, value)
+#define HIOE_INSTRUCTION_INFO_GET_RAW(extra_info)                              \
+	GET_C2H_FIELD(extra_info + 0X04, 31, 1)
+#define HIOE_INSTRUCTION_INFO_SET_RAW(extra_info, value)                       \
+	SET_C2H_FIELD_CLR(extra_info + 0X04, 31, 1, value)
+#define HIOE_INSTRUCTION_INFO_SET_RAW_NO_CLR(extra_info, value)                \
+	SET_C2H_FIELD_NO_CLR(extra_info + 0X04, 31, 1, value)
+#endif
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/halmac/halmac_h2c_extra_info_nic.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/halmac/halmac_h2c_extra_info_nic.h
--- linux-5.6.3/3rdparty/rtl8821ce/hal/halmac/halmac_h2c_extra_info_nic.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/halmac/halmac_h2c_extra_info_nic.h	2020-04-10 16:35:06.812659881 +0300
@@ -0,0 +1,171 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ ******************************************************************************/
+
+#ifndef _HAL_H2CEXTRAINFO_H2C_C2H_NIC_H_
+#define _HAL_H2CEXTRAINFO_H2C_C2H_NIC_H_
+
+/* H2C extra info (rsvd page) usage, unit : page (128byte)*/
+/* dlfw : not include txdesc size*/
+/* update pkt : not include txdesc size*/
+/* cfg param : not include txdesc size*/
+/* scan info : not include txdesc size*/
+/* dl flash : not include txdesc size*/
+#define DLFW_RSVDPG_SIZE 2048
+#define UPDATE_PKT_RSVDPG_SIZE 2048
+#define CFG_PARAM_RSVDPG_SIZE 2048
+#define SCAN_INFO_RSVDPG_SIZE 256
+#define DL_FLASH_RSVDPG_SIZE 2048
+/* su0 snding pkt : include txdesc size */
+#define SU0_SNDING_PKT_OFFSET 0
+#define SU0_SNDING_PKT_RSVDPG_SIZE 128
+
+#define PARAM_INFO_GET_LEN(extra_info) LE_BITS_TO_4BYTE(extra_info + 0X00, 0, 8)
+#define PARAM_INFO_SET_LEN(extra_info, value)                                  \
+	SET_BITS_TO_LE_4BYTE(extra_info + 0X00, 0, 8, value)
+#define PARAM_INFO_GET_IO_CMD(extra_info)                                      \
+	LE_BITS_TO_4BYTE(extra_info + 0X00, 8, 7)
+#define PARAM_INFO_SET_IO_CMD(extra_info, value)                               \
+	SET_BITS_TO_LE_4BYTE(extra_info + 0X00, 8, 7, value)
+#define PARAM_INFO_GET_MSK_EN(extra_info)                                      \
+	LE_BITS_TO_4BYTE(extra_info + 0X00, 15, 1)
+#define PARAM_INFO_SET_MSK_EN(extra_info, value)                               \
+	SET_BITS_TO_LE_4BYTE(extra_info + 0X00, 15, 1, value)
+#define PARAM_INFO_GET_LLT_PG_BNDY(extra_info)                                 \
+	LE_BITS_TO_4BYTE(extra_info + 0X00, 16, 8)
+#define PARAM_INFO_SET_LLT_PG_BNDY(extra_info, value)                          \
+	SET_BITS_TO_LE_4BYTE(extra_info + 0X00, 16, 8, value)
+#define PARAM_INFO_GET_EFUSE_RSVDPAGE_LOC(extra_info)                          \
+	LE_BITS_TO_4BYTE(extra_info + 0X00, 16, 8)
+#define PARAM_INFO_SET_EFUSE_RSVDPAGE_LOC(extra_info, value)                   \
+	SET_BITS_TO_LE_4BYTE(extra_info + 0X00, 16, 8, value)
+#define PARAM_INFO_GET_EFUSE_PATCH_EN(extra_info)                              \
+	LE_BITS_TO_4BYTE(extra_info + 0X00, 16, 8)
+#define PARAM_INFO_SET_EFUSE_PATCH_EN(extra_info, value)                       \
+	SET_BITS_TO_LE_4BYTE(extra_info + 0X00, 16, 8, value)
+#define PARAM_INFO_GET_RF_ADDR(extra_info)                                     \
+	LE_BITS_TO_4BYTE(extra_info + 0X00, 16, 8)
+#define PARAM_INFO_SET_RF_ADDR(extra_info, value)                              \
+	SET_BITS_TO_LE_4BYTE(extra_info + 0X00, 16, 8, value)
+#define PARAM_INFO_GET_IO_ADDR(extra_info)                                     \
+	LE_BITS_TO_4BYTE(extra_info + 0X00, 16, 16)
+#define PARAM_INFO_SET_IO_ADDR(extra_info, value)                              \
+	SET_BITS_TO_LE_4BYTE(extra_info + 0X00, 16, 16, value)
+#define PARAM_INFO_GET_DELAY_VAL(extra_info)                                   \
+	LE_BITS_TO_4BYTE(extra_info + 0X00, 16, 16)
+#define PARAM_INFO_SET_DELAY_VAL(extra_info, value)                            \
+	SET_BITS_TO_LE_4BYTE(extra_info + 0X00, 16, 16, value)
+#define PARAM_INFO_GET_RF_PATH(extra_info)                                     \
+	LE_BITS_TO_4BYTE(extra_info + 0X00, 24, 8)
+#define PARAM_INFO_SET_RF_PATH(extra_info, value)                              \
+	SET_BITS_TO_LE_4BYTE(extra_info + 0X00, 24, 8, value)
+#define PARAM_INFO_GET_DATA(extra_info)                                        \
+	LE_BITS_TO_4BYTE(extra_info + 0X04, 0, 32)
+#define PARAM_INFO_SET_DATA(extra_info, value)                                 \
+	SET_BITS_TO_LE_4BYTE(extra_info + 0X04, 0, 32, value)
+#define PARAM_INFO_GET_MASK(extra_info)                                        \
+	LE_BITS_TO_4BYTE(extra_info + 0X08, 0, 32)
+#define PARAM_INFO_SET_MASK(extra_info, value)                                 \
+	SET_BITS_TO_LE_4BYTE(extra_info + 0X08, 0, 32, value)
+#define CH_INFO_GET_CH(extra_info) LE_BITS_TO_4BYTE(extra_info + 0X00, 0, 8)
+#define CH_INFO_SET_CH(extra_info, value)                                      \
+	SET_BITS_TO_LE_4BYTE(extra_info + 0X00, 0, 8, value)
+#define CH_INFO_GET_PRI_CH_IDX(extra_info)                                     \
+	LE_BITS_TO_4BYTE(extra_info + 0X00, 8, 4)
+#define CH_INFO_SET_PRI_CH_IDX(extra_info, value)                              \
+	SET_BITS_TO_LE_4BYTE(extra_info + 0X00, 8, 4, value)
+#define CH_INFO_GET_BW(extra_info) LE_BITS_TO_4BYTE(extra_info + 0X00, 12, 4)
+#define CH_INFO_SET_BW(extra_info, value)                                      \
+	SET_BITS_TO_LE_4BYTE(extra_info + 0X00, 12, 4, value)
+#define CH_INFO_GET_TIMEOUT(extra_info)                                        \
+	LE_BITS_TO_4BYTE(extra_info + 0X00, 16, 8)
+#define CH_INFO_SET_TIMEOUT(extra_info, value)                                 \
+	SET_BITS_TO_LE_4BYTE(extra_info + 0X00, 16, 8, value)
+#define CH_INFO_GET_ACTION_ID(extra_info)                                      \
+	LE_BITS_TO_4BYTE(extra_info + 0X00, 24, 7)
+#define CH_INFO_SET_ACTION_ID(extra_info, value)                               \
+	SET_BITS_TO_LE_4BYTE(extra_info + 0X00, 24, 7, value)
+#define CH_INFO_GET_EXTRA_INFO(extra_info)                                     \
+	LE_BITS_TO_4BYTE(extra_info + 0X00, 31, 1)
+#define CH_INFO_SET_EXTRA_INFO(extra_info, value)                              \
+	SET_BITS_TO_LE_4BYTE(extra_info + 0X00, 31, 1, value)
+#define CH_EXTRA_INFO_GET_ID(extra_info)                                       \
+	LE_BITS_TO_4BYTE(extra_info + 0X00, 0, 7)
+#define CH_EXTRA_INFO_SET_ID(extra_info, value)                                \
+	SET_BITS_TO_LE_4BYTE(extra_info + 0X00, 0, 7, value)
+#define CH_EXTRA_INFO_GET_INFO(extra_info)                                     \
+	LE_BITS_TO_4BYTE(extra_info + 0X00, 7, 1)
+#define CH_EXTRA_INFO_SET_INFO(extra_info, value)                              \
+	SET_BITS_TO_LE_4BYTE(extra_info + 0X00, 7, 1, value)
+#define CH_EXTRA_INFO_GET_SIZE(extra_info)                                     \
+	LE_BITS_TO_4BYTE(extra_info + 0X00, 8, 8)
+#define CH_EXTRA_INFO_SET_SIZE(extra_info, value)                              \
+	SET_BITS_TO_LE_4BYTE(extra_info + 0X00, 8, 8, value)
+#define CH_EXTRA_INFO_GET_DATA(extra_info)                                     \
+	LE_BITS_TO_4BYTE(extra_info + 0X00, 16, 1)
+#define CH_EXTRA_INFO_SET_DATA(extra_info, value)                              \
+	SET_BITS_TO_LE_4BYTE(extra_info + 0X00, 16, 1, value)
+#define HIOE_INSTRUCTION_INFO_GET_BYTEDATA_L(extra_info)                       \
+	LE_BITS_TO_4BYTE(extra_info + 0X00, 0, 16)
+#define HIOE_INSTRUCTION_INFO_SET_BYTEDATA_L(extra_info, value)                \
+	SET_BITS_TO_LE_4BYTE(extra_info + 0X00, 0, 16, value)
+#define HIOE_INSTRUCTION_INFO_GET_BITDATA(extra_info)                          \
+	LE_BITS_TO_4BYTE(extra_info + 0X00, 0, 16)
+#define HIOE_INSTRUCTION_INFO_SET_BITDATA(extra_info, value)                   \
+	SET_BITS_TO_LE_4BYTE(extra_info + 0X00, 0, 16, value)
+#define HIOE_INSTRUCTION_INFO_GET_BYTEDATA_H(extra_info)                       \
+	LE_BITS_TO_4BYTE(extra_info + 0X00, 16, 16)
+#define HIOE_INSTRUCTION_INFO_SET_BYTEDATA_H(extra_info, value)                \
+	SET_BITS_TO_LE_4BYTE(extra_info + 0X00, 16, 16, value)
+#define HIOE_INSTRUCTION_INFO_GET_BITMASK(extra_info)                          \
+	LE_BITS_TO_4BYTE(extra_info + 0X00, 16, 16)
+#define HIOE_INSTRUCTION_INFO_SET_BITMASK(extra_info, value)                   \
+	SET_BITS_TO_LE_4BYTE(extra_info + 0X00, 16, 16, value)
+#define HIOE_INSTRUCTION_INFO_GET_REG_ADDR(extra_info)                         \
+	LE_BITS_TO_4BYTE(extra_info + 0X04, 0, 22)
+#define HIOE_INSTRUCTION_INFO_SET_REG_ADDR(extra_info, value)                  \
+	SET_BITS_TO_LE_4BYTE(extra_info + 0X04, 0, 22, value)
+#define HIOE_INSTRUCTION_INFO_GET_DELAY_VALUE(extra_info)                      \
+	LE_BITS_TO_4BYTE(extra_info + 0X04, 0, 22)
+#define HIOE_INSTRUCTION_INFO_SET_DELAY_VALUE(extra_info, value)               \
+	SET_BITS_TO_LE_4BYTE(extra_info + 0X04, 0, 22, value)
+#define HIOE_INSTRUCTION_INFO_GET_MODE_SELECT(extra_info)                      \
+	LE_BITS_TO_4BYTE(extra_info + 0X04, 22, 1)
+#define HIOE_INSTRUCTION_INFO_SET_MODE_SELECT(extra_info, value)               \
+	SET_BITS_TO_LE_4BYTE(extra_info + 0X04, 22, 1, value)
+#define HIOE_INSTRUCTION_INFO_GET_IO_DELAY(extra_info)                         \
+	LE_BITS_TO_4BYTE(extra_info + 0X04, 23, 1)
+#define HIOE_INSTRUCTION_INFO_SET_IO_DELAY(extra_info, value)                  \
+	SET_BITS_TO_LE_4BYTE(extra_info + 0X04, 23, 1, value)
+#define HIOE_INSTRUCTION_INFO_GET_BYTEMASK(extra_info)                         \
+	LE_BITS_TO_4BYTE(extra_info + 0X04, 24, 4)
+#define HIOE_INSTRUCTION_INFO_SET_BYTEMASK(extra_info, value)                  \
+	SET_BITS_TO_LE_4BYTE(extra_info + 0X04, 24, 4, value)
+#define HIOE_INSTRUCTION_INFO_GET_RD_EN(extra_info)                            \
+	LE_BITS_TO_4BYTE(extra_info + 0X04, 28, 1)
+#define HIOE_INSTRUCTION_INFO_SET_RD_EN(extra_info, value)                     \
+	SET_BITS_TO_LE_4BYTE(extra_info + 0X04, 28, 1, value)
+#define HIOE_INSTRUCTION_INFO_GET_WR_EN(extra_info)                            \
+	LE_BITS_TO_4BYTE(extra_info + 0X04, 29, 1)
+#define HIOE_INSTRUCTION_INFO_SET_WR_EN(extra_info, value)                     \
+	SET_BITS_TO_LE_4BYTE(extra_info + 0X04, 29, 1, value)
+#define HIOE_INSTRUCTION_INFO_GET_RAW_R(extra_info)                            \
+	LE_BITS_TO_4BYTE(extra_info + 0X04, 30, 1)
+#define HIOE_INSTRUCTION_INFO_SET_RAW_R(extra_info, value)                     \
+	SET_BITS_TO_LE_4BYTE(extra_info + 0X04, 30, 1, value)
+#define HIOE_INSTRUCTION_INFO_GET_RAW(extra_info)                              \
+	LE_BITS_TO_4BYTE(extra_info + 0X04, 31, 1)
+#define HIOE_INSTRUCTION_INFO_SET_RAW(extra_info, value)                       \
+	SET_BITS_TO_LE_4BYTE(extra_info + 0X04, 31, 1, value)
+#endif
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/halmac/halmac_hw_cfg.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/halmac/halmac_hw_cfg.h
--- linux-5.6.3/3rdparty/rtl8821ce/hal/halmac/halmac_hw_cfg.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/halmac/halmac_hw_cfg.h	2020-04-10 16:35:06.812659881 +0300
@@ -0,0 +1,200 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ ******************************************************************************/
+
+#ifndef __HALMAC__HW_CFG_H__
+#define __HALMAC__HW_CFG_H__
+
+#include <drv_conf.h>	/* CONFIG_[IC], CONFIG_[INTF]_HCI */
+
+#ifdef CONFIG_RTL8723A
+#define HALMAC_8723A_SUPPORT	1
+#else
+#define HALMAC_8723A_SUPPORT	0
+#endif
+
+#ifdef CONFIG_RTL8188E
+#define HALMAC_8188E_SUPPORT	1
+#else
+#define HALMAC_8188E_SUPPORT	0
+#endif
+
+#ifdef CONFIG_RTL8821A
+#define HALMAC_8821A_SUPPORT	1
+#else
+#define HALMAC_8821A_SUPPORT	0
+#endif
+
+#ifdef CONFIG_RTL8723B
+#define HALMAC_8723B_SUPPORT	1
+#else
+#define HALMAC_8723B_SUPPORT	0
+#endif
+
+#ifdef CONFIG_RTL8812A
+#define HALMAC_8812A_SUPPORT	1
+#else
+#define HALMAC_8812A_SUPPORT	0
+#endif
+
+#ifdef CONFIG_RTL8192E
+#define HALMAC_8192E_SUPPORT	1
+#else
+#define HALMAC_8192E_SUPPORT	0
+#endif
+
+#ifdef CONFIG_RTL8881A
+#define HALMAC_8881A_SUPPORT	1
+#else
+#define HALMAC_8881A_SUPPORT	0
+#endif
+
+#ifdef CONFIG_RTL8821B
+#define HALMAC_8821B_SUPPORT	1
+#else
+#define HALMAC_8821B_SUPPORT	0
+#endif
+
+#ifdef CONFIG_RTL8814A
+#define HALMAC_8814A_SUPPORT	1
+#else
+#define HALMAC_8814A_SUPPORT	0
+#endif
+
+#ifdef CONFIG_RTL8881A
+#define HALMAC_8881A_SUPPORT	1
+#else
+#define HALMAC_8881A_SUPPORT	0
+#endif
+
+#ifdef CONFIG_RTL8703B
+#define HALMAC_8703B_SUPPORT	1
+#else
+#define HALMAC_8703B_SUPPORT	0
+#endif
+
+#ifdef CONFIG_RTL8723D
+#define HALMAC_8723D_SUPPORT	1
+#else
+#define HALMAC_8723D_SUPPORT	0
+#endif
+
+#ifdef CONFIG_RTL8188F
+#define HALMAC_8188F_SUPPORT	1
+#else
+#define HALMAC_8188F_SUPPORT	0
+#endif
+
+#ifdef CONFIG_RTL8821BMP
+#define HALMAC_8821BMP_SUPPORT	1
+#else
+#define HALMAC_8821BMP_SUPPORT	0
+#endif
+
+#ifdef CONFIG_RTL8814AMP
+#define HALMAC_8814AMP_SUPPORT	1
+#else
+#define HALMAC_8814AMP_SUPPORT	0
+#endif
+
+#ifdef CONFIG_RTL8195A
+#define HALMAC_8195A_SUPPORT	1
+#else
+#define HALMAC_8195A_SUPPORT	0
+#endif
+
+#ifdef CONFIG_RTL8821B
+#define HALMAC_8821B_SUPPORT	1
+#else
+#define HALMAC_8821B_SUPPORT	0
+#endif
+
+#ifdef CONFIG_RTL8196F
+#define HALMAC_8196F_SUPPORT	1
+#else
+#define HALMAC_8196F_SUPPORT	0
+#endif
+
+#ifdef CONFIG_RTL8197F
+#define HALMAC_8197F_SUPPORT	1
+#else
+#define HALMAC_8197F_SUPPORT	0
+#endif
+
+#ifdef CONFIG_RTL8198F
+#define HALMAC_8198F_SUPPORT	1
+#else
+#define HALMAC_8198F_SUPPORT	0
+#endif
+
+#ifdef CONFIG_RTL8192F
+#define HALMAC_8192F_SUPPORT	1
+#else
+#define HALMAC_8192F_SUPPORT	0
+#endif
+
+#ifdef CONFIG_RTL8812F
+#define HALMAC_8812F_SUPPORT	1
+#else
+#define HALMAC_8812F_SUPPORT	0
+#endif
+
+
+/* Halmac support IC version */
+
+#ifdef CONFIG_RTL8814B
+#define HALMAC_8814B_SUPPORT	1
+#else
+#define HALMAC_8814B_SUPPORT	0
+#endif
+
+#ifdef CONFIG_RTL8821C
+#define HALMAC_8821C_SUPPORT	1
+#else
+#define HALMAC_8821C_SUPPORT	0
+#endif
+
+#ifdef CONFIG_RTL8822B
+#define HALMAC_8822B_SUPPORT	1
+#else
+#define HALMAC_8822B_SUPPORT	0
+#endif
+
+#ifdef CONFIG_RTL8822C
+#define HALMAC_8822C_SUPPORT	1
+#else
+#define HALMAC_8822C_SUPPORT	0
+#endif
+
+
+/* Interface support */
+#ifdef CONFIG_SDIO_HCI
+#define HALMAC_SDIO_SUPPORT	1
+#else
+#define HALMAC_SDIO_SUPPORT	0
+#endif
+#ifdef CONFIG_USB_HCI
+#define HALMAC_USB_SUPPORT	1
+#else
+#define HALMAC_USB_SUPPORT	0
+#endif
+#ifdef CONFIG_PCI_HCI
+#define HALMAC_PCIE_SUPPORT	1
+#else
+#define HALMAC_PCIE_SUPPORT	0
+#endif
+
+#endif /* __HALMAC__HW_CFG_H__ */
+
+
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/halmac/halmac_intf_phy_cmd.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/halmac/halmac_intf_phy_cmd.h
--- linux-5.6.3/3rdparty/rtl8821ce/hal/halmac/halmac_intf_phy_cmd.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/halmac/halmac_intf_phy_cmd.h	2020-04-10 16:35:06.812659881 +0300
@@ -0,0 +1,45 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ ******************************************************************************/
+
+#ifndef HALMAC_INTF_PHY_CMD
+#define HALMAC_INTF_PHY_CMD
+
+/* Cut mask */
+enum halmac_intf_phy_cut {
+	HALMAC_INTF_PHY_CUT_TESTCHIP = BIT(0),
+	HALMAC_INTF_PHY_CUT_A = BIT(1),
+	HALMAC_INTF_PHY_CUT_B = BIT(2),
+	HALMAC_INTF_PHY_CUT_C = BIT(3),
+	HALMAC_INTF_PHY_CUT_D = BIT(4),
+	HALMAC_INTF_PHY_CUT_E = BIT(5),
+	HALMAC_INTF_PHY_CUT_F = BIT(6),
+	HALMAC_INTF_PHY_CUT_G = BIT(7),
+	HALMAC_INTF_PHY_CUT_ALL = 0x7FFF,
+};
+
+/* IP selection */
+enum halmac_ip_sel {
+	HALMAC_IP_INTF_PHY = 0,
+	HALMAC_IP_SEL_MAC = 1,
+	HALMAC_IP_PCIE_DBI = 2,
+	HALMAC_IP_SEL_UNDEFINE = 0x7FFF,
+};
+
+/* Platform mask */
+enum halmac_intf_phy_platform {
+	HALMAC_INTF_PHY_PLATFORM_ALL = 0x7FFF,
+};
+
+#endif
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/halmac/halmac_module.c linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/halmac/halmac_module.c
--- linux-5.6.3/3rdparty/rtl8821ce/hal/halmac/halmac_module.c	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/halmac/halmac_module.c	2020-04-10 16:35:06.812659881 +0300
@@ -0,0 +1,719 @@
+#include "halmac_api.h"
+#include "halmac_module.h"
+
+HALMAC_API_ARG api_arg_table[HALMAC_API_MAX] = {
+#if (HALMAC_VERSION(1, 2, 0) <= HALMAC_CURRENT_VERSION)
+		{HALMAC_API_INIT_OBJ, 3, {TLP_TYPE_PVOID, TLP_TYPE_POS_API_ENTRY, TLP_TYPE_PHALMAC_INTERFACE} },
+		{HALMAC_API_DEINIT_OBJ, 0, {TLP_TYPE_NONE} },
+		{HALMAC_API_MAC_POWER_SWITCH, 1, {TLP_TYPE_PHALMAC_MAC_POWER} },
+		{HALMAC_API_DOWNLOAD_FIRMWARE, 1, {TLP_TYPE_PU8_BUFFER} },
+		{HALMAC_API_CFG_MAC_ADDR, 2, {TLP_TYPE_PU8, TLP_TYPE_PHALMAC_WLAN_ADDR} },
+		{HALMAC_API_CFG_BSSID, 2, {TLP_TYPE_PU8, TLP_TYPE_PHALMAC_WLAN_ADDR} },
+		{HALMAC_API_CFG_MULTICAST_ADDR, 1, {TLP_TYPE_PHALMAC_WLAN_ADDR} },
+		{HALMAC_API_PRE_INIT_SYSTEM_CFG, 0, {TLP_TYPE_NONE} },
+		{HALMAC_API_INIT_SYSTEM_CFG, 0, {TLP_TYPE_NONE} },
+		{HALMAC_API_INIT_TRX_CFG, 1, {TLP_TYPE_PHALMAC_TRX_MODE} },
+		{HALMAC_API_CFG_RX_AGGREGATION, 1, {TLP_TYPE_PHALMAC_RXAGG_CFG} },
+		{HALMAC_API_CFG_OPERATION_MODE, 1, {TLP_TYPE_PHALMAC_WIRELESS_MODE} },
+		{HALMAC_API_CFG_BW, 1, {TLP_TYPE_PHALMAC_BW} },
+		{HALMAC_API_INIT_MAC_CFG, 1, {TLP_TYPE_PHALMAC_TRX_MODE} },
+		{HALMAC_API_INIT_SDIO_CFG, 0, {TLP_TYPE_NONE} },
+		{HALMAC_API_INIT_USB_CFG, 0, {TLP_TYPE_NONE} },
+		{HALMAC_API_INIT_PCIE_CFG, 0, {TLP_TYPE_NONE} },
+		{HALMAC_API_DEINIT_SDIO_CFG, 0, {TLP_TYPE_NONE} },
+		{HALMAC_API_DEINIT_USB_CFG, 0, {TLP_TYPE_NONE} },
+		{HALMAC_API_DEINIT_PCIE_CFG, 0, {TLP_TYPE_NONE} },
+		{HALMAC_API_GET_EFUSE_SIZE, 1, {TLP_TYPE_PU32} },
+		{HALMAC_API_DUMP_EFUSE_MAP, 1, {TLP_TYPE_PHALMAC_EFUSE_READ_CFG} },
+		{HALMAC_API_WRITE_EFUSE, 2, {TLP_TYPE_PU32, TLP_TYPE_PU8} },
+		{HALMAC_API_READ_EFUSE, 2, {TLP_TYPE_PU32, TLP_TYPE_PU8} },
+		{HALMAC_API_GET_LOGICAL_EFUSE_SIZE,	1, {TLP_TYPE_PU32} },
+		{HALMAC_API_DUMP_LOGICAL_EFUSE_MAP,	1, {TLP_TYPE_PHALMAC_EFUSE_READ_CFG} },
+		{HALMAC_API_WRITE_LOGICAL_EFUSE, 2, {TLP_TYPE_PU32, TLP_TYPE_PU8} },
+		{HALMAC_API_READ_LOGICAL_EFUSE, 2, {TLP_TYPE_PU32, TLP_TYPE_PU8} },
+		{HALMAC_API_GET_C2H_INFO, 1, {TLP_TYPE_PU8_BUFFER} },
+		{HALMAC_API_H2C_LB, 0, {TLP_TYPE_NONE} },
+		{HALMAC_API_CFG_PARAMETER, 2, {TLP_TYPE_PHALMAC_PHY_PARAMETER_INFO, TLP_TYPE_PU8} },
+		{HALMAC_API_UPDATE_PACKET, 2, {TLP_TYPE_PHALMAC_PACKET_ID, TLP_TYPE_PU8_BUFFER} },
+		{HALMAC_API_TX_ALLOWED_SDIO, 1, {TLP_TYPE_PU8_BUFFER} },
+		{HALMAC_API_SET_BULKOUT_NUM, 1, {TLP_TYPE_PU8} },
+		{HALMAC_API_GET_SDIO_TX_ADDR, 2, {TLP_TYPE_PU8_BUFFER, TLP_TYPE_PU32} },
+		{HALMAC_API_GET_USB_BULKOUT_ID, 2, {TLP_TYPE_PU8_BUFFER, TLP_TYPE_PU8} },
+		{HALMAC_API_TIMER_2S, 0, {TLP_TYPE_NONE} },
+		{HALMAC_API_CFG_DRV_INFO, 1, {TLP_TYPE_PHALMAC_DRV_INFO} },
+		{HALMAC_API_SEND_BT_COEX, 1, {TLP_TYPE_PU8_BUFFER, TLP_TYPE_PU8} },
+		{HALMAC_API_VERIFY_PLATFORM_API, 0, {TLP_TYPE_NONE} },
+		{HALMAC_API_CFG_TXBF, 3, {TLP_TYPE_PU8,	TLP_TYPE_PHALMAC_BW, TLP_TYPE_PU8_1} },
+		{HALMAC_API_CFG_MUMIMO, 1, {TLP_TYPE_PHALMAC_CFG_MUMIMO_PARA} },
+		{HALMAC_API_CFG_SOUNDING, 2, {TLP_TYPE_PHALMAC_SND_ROLE, TLP_TYPE_PHALMAC_DATA_RATE} },
+		{HALMAC_API_DEL_SOUNDING, 1, {TLP_TYPE_PHALMAC_SND_ROLE} },
+		{HALMAC_API_SU_BFER_ENTRY_INIT, 1, {TLP_TYPE_PHALMAC_SU_BFER_INIT_PARA} },
+		{HALMAC_API_SU_BFEE_ENTRY_INIT, 2, {TLP_TYPE_PU8, TLP_TYPE_PU16} },
+		{HALMAC_API_MU_BFER_ENTRY_INIT, 1, {TLP_TYPE_PHALMAC_MU_BFER_INIT_PARA} },
+		{HALMAC_API_MU_BFEE_ENTRY_INIT, 1, {TLP_TYPE_PHALMAC_MU_BFEE_INIT_PARA} },
+		{HALMAC_API_SU_BFER_ENTRY_DEL, 1, {TLP_TYPE_PU8} },
+		{HALMAC_API_SU_BFEE_ENTRY_DEL, 1, {TLP_TYPE_PU8} },
+		{HALMAC_API_MU_BFER_ENTRY_DEL, 0, {TLP_TYPE_NONE} },
+		{HALMAC_API_MU_BFEE_ENTRY_DEL, 1, {TLP_TYPE_PU8} },
+		{HALMAC_API_ADD_CH_INFO, 1, {TLP_TYPE_PHALMAC_CH_INFO} },
+		{HALMAC_API_CTRL_CH_SWITCH, 1, {TLP_TYPE_PHALMAC_CH_SWITCH_OPTION} },
+		{HALMAC_API_CLEAR_CH_INFO, 0, {TLP_TYPE_NONE} },
+		{HALMAC_API_SEND_GENERAL_INFO, 1, {TLP_TYPE_PHALMAC_GENERAL_INFO} },
+		{HALMAC_API_QUERY_STATE, 4, {TLP_TYPE_PHALMAC_FEATURE_ID, TLP_TYPE_PHALMAC_CMD_PROCESS_STATUS, TLP_TYPE_PU8_BUFFER, TLP_TYPE_PU32} },
+		{HALMAC_API_CHECK_FW_STATUS, 1, {TLP_TYPE_PU8} },
+		{HALMAC_API_DUMP_FW_DMEM, 2, {TLP_TYPE_PU8_BUFFER, TLP_TYPE_PU32} },
+		{HALMAC_API_RESET_FEATURE, 1, {TLP_TYPE_PHALMAC_FEATURE_ID} },
+		{HALMAC_API_START_IQK, 1, {TLP_TYPE_PHALMAC_IQK} },
+		{HALMAC_API_CTRL_PWR_TRACKING, 1, {TLP_TYPE_PHALMAC_PWR_TRACKING} },
+		{HALMAC_API_CFG_LA_MODE, 1, {TLP_TYPE_PHALMAC_LA_MODE} },
+		{HALMAC_API_GET_HW_VALUE, 2, {TLP_TYPE_PHALMAC_HW_ID, TLP_TYPE_PVOID} },
+		{HALMAC_API_SET_HW_VALUE, 2, {TLP_TYPE_PHALMAC_HW_ID, TLP_TYPE_PVOID} },
+		{HALMAC_API_CFG_DRV_RSVD_PG_NUM, 1, {TLP_TYPE_PHALMAC_DRV_RSVD_PG_NUM} },
+		{HALMAC_API_DUMP_EFUSE_MAP_BT, 2, {TLP_TYPE_PHALMAC_EFUSE_BANK, TLP_TYPE_PU8_BUFFER} },
+		{HALMAC_API_SWITCH_EFUSE_BANK, 1, {TLP_TYPE_PHALMAC_EFUSE_BANK} },
+		{HALMAC_API_WRITE_EFUSE_BT, 3, {TLP_TYPE_PU32, TLP_TYPE_PU8, TLP_TYPE_PHALMAC_EFUSE_BANK} },
+		{HALMAC_API_PG_EFUSE_BY_MAP, 2, {TLP_TYPE_PHALMAC_PG_EFUSE_INFO, TLP_TYPE_PHALMAC_EFUSE_READ_CFG} },
+		{HALMAC_API_CFG_CSI_RATE, 4, {TLP_TYPE_PU8, TLP_TYPE_PU8_1, TLP_TYPE_PU8_2, TLP_TYPE_PU8_BUFFER} },
+		{HALMAC_API_DL_DRV_RSVD_PG, 2, {TLP_TYPE_PU8, TLP_TYPE_PU8_BUFFER} },
+#endif
+#if (HALMAC_VERSION(1, 3, 0) <= HALMAC_CURRENT_VERSION)
+		{HALMAC_API_PHY_CFG, 1, {TLP_TYPE_PHALMAC_INTF_PHY_PLATFORM} },
+		{HALMAC_API_REGISTER_API, 1, {TLP_TYPE_PHALMAC_API_REGISTRY} },
+		{HALMAC_API_FREE_DOWNLOAD_FIRMWARE, 2, {TLP_TYPE_PHALMAC_DLFW_MEM, TLP_TYPE_PU8_BUFFER} },
+		{HALMAC_API_GET_FW_VERSION, 1, {TLP_TYPE_PHALMAC_FW_VERSION} },
+		{HALMAC_API_DEBUG, 0, {TLP_TYPE_NONE} },
+		{HALMAC_API_GET_EFUSE_AVAL_SIZE, 1, {TLP_TYPE_PU32} },
+		{HALMAC_API_FILL_TXDESC_CHECKSUM, 1, {TLP_TYPE_PU8} },
+		{HALMAC_API_GET_FIFO_SIZE, 1, {TLP_TYPE_PHALMAC_FIFO_SEL} },
+		{HALMAC_API_DUMP_FIFO, 3, {TLP_TYPE_PHALMAC_FIFO_SEL, TLP_TYPE_PU32, TLP_TYPE_PU8_BUFFER} },
+		{HALMAC_API_P2PPS, 1, {TLP_TYPE_PHALMAC_P2PPS} },
+		{HALMAC_API_CFG_TX_AGG_ALIGN, 2, {TLP_TYPE_PU8, TLP_TYPE_PU16} },
+		{HALMAC_API_CFG_MAX_DL_SIZE, 1, {TLP_TYPE_PU32} },
+		{HALMAC_API_CFG_RX_FIFO_EXPANDING_MODE, 1, {TLP_TYPE_PHALMAC_RX_EXPAND_MODE} },
+		{HALMAC_API_CHK_TXDESC, 1, {TLP_TYPE_PU8_BUFFER} },
+		{HALMAC_API_PCIE_SWITCH, 1, {TLP_TYPE_PHALMAC_PCIE_CFG} },
+		{HALMAC_API_SDIO_CMD53_4BYTE, 1, {TLP_TYPE_PHALMAC_SDIO_CMD53_4BYTE_MODE} },
+		{HALMAC_API_CFG_TRANS_ADDR, 2, {TLP_TYPE_PU8, TLP_TYPE_PHALMAC_WLAN_ADDR} },
+		{HALMAC_API_CFG_NET_TYPE, 2, {TLP_TYPE_PU8, TLP_TYPE_PHALMAC_NETWORK_TYPE_SELECT} },
+		{HALMAC_API_CFG_TSF_RESET, 1, {TLP_TYPE_PU8} },
+		{HALMAC_API_CFG_BCN_SPACE, 1, {TLP_TYPE_PU8, TLP_TYPE_PU32} },
+		{HALMAC_API_CFG_BCN_CTRL, 3, {TLP_TYPE_PU8, TLP_TYPE_PU8_1, TLP_TYPE_PHALMAC_BCN_CTRL} },
+		{HALMAC_API_INTF_INTEGRA_TUNING, 0, {TLP_TYPE_NONE} },
+		{HALMAC_API_TXFIFO_IS_EMPTY, 1, {TLP_TYPE_PU32} },
+		{HALMAC_API_SDIO_HW_INFO, 1, {TLP_TYPE_PHALMAC_SDIO_HW_INFO} },
+#endif
+#if (HALMAC_VERSION(1, 4, 0) <= HALMAC_CURRENT_VERSION)
+		{HALMAC_API_CFG_SIDEBAND_INT, 1, {TLP_TYPE_PHALMAC_SIDEBAND_INT_CFG} },
+#endif
+		{HALMAC_API_MAX, 0, {TLP_TYPE_NONE} }
+};
+
+static VOID
+halmac_obj_init(
+	IN struct _HALMAC_OBJ *halmac_obj,
+	IN u8 init
+)
+{
+	halmac_obj->init = init;
+}
+
+static u8
+is_halmac_initialized(
+	IN struct _HALMAC_OBJ *halmac_obj
+)
+{
+	return halmac_obj->init;
+}
+
+static u8
+parse_halmac_api_arg_list(
+	IN HALMAC_API_ID api_id,
+	OUT PHALMAC_TLP_STRUCT parg,
+	IN PHALMAC_TLP_STRUCT ptlp,
+	IN u32 *arg_count
+)
+{
+	u32 i, j;
+	u32 idx = 0;
+	u32	match_count;
+
+	for (i = 0; i < HALMAC_API_MAX; i++) {
+		if (api_arg_table[i].api_id == api_id) {
+			idx = i;
+			break;
+		}
+	}
+
+	if (*arg_count < api_arg_table[idx].arg_count)
+		return _FALSE;
+
+	for (i = 0; i < api_arg_table[idx].arg_count; i++) {
+		match_count = 0;
+		for (j = 0; j < *arg_count; j++) {
+			if (api_arg_table[idx].arg_type_seq[i] == ptlp[j].type) {
+
+				if (match_count >= 1)
+					return _FALSE; /* argument types should be different to each other for the same API */
+
+				parg[i].type = ptlp[j].type;
+				parg[i].length = ptlp[j].length;
+				parg[i].ptr = ptlp[j].ptr;
+				match_count++;
+			}
+		}
+	}
+
+	for (i = 0; i < api_arg_table[idx].arg_count; i++) {
+		if (parg[i].type != api_arg_table[idx].arg_type_seq[i])
+			return _FALSE;
+	}
+
+	return _TRUE;
+}
+
+HALMAC_RET_STATUS
+halmac_initialize_obj(
+	IN struct _HALMAC_OBJ *halmac_obj,
+	INOUT PHALMAC_TLP_STRUCT ptlp,
+	IN	u32 tlpCount
+)
+{
+	VOID *pDriver_adapter = NULL;
+	u32 arg_count = tlpCount;
+	HALMAC_RET_STATUS result = HALMAC_RET_SUCCESS;
+	HALMAC_TLP_STRUCT arg_list[MAX_ARG_NUM] = {0};
+	HALMAC_VER chip_version;
+	PHALMAC_ADAPTER pHalmac_adapter;
+
+	if (is_halmac_initialized(halmac_obj))
+		return HALMAC_RET_SUCCESS;
+
+	if (!parse_halmac_api_arg_list(HALMAC_API_INIT_OBJ, &arg_list[0], ptlp, &arg_count))
+		return HALMAC_RET_WRONG_ARGUMENT;
+
+	halmac_obj->halmac_api_entry = (PHALMAC_API)0;
+	halmac_obj->halmac_adapter = (PHALMAC_ADAPTER)0;
+
+	result = halmac_init_adapter(arg_list[0].ptr, (PHALMAC_PLATFORM_API)arg_list[1].ptr,
+						*((HALMAC_INTERFACE *)arg_list[2].ptr), &(halmac_obj->halmac_adapter), &(halmac_obj->halmac_api_entry));
+
+	if (result != HALMAC_RET_SUCCESS)
+		return result;
+
+	halmac_obj_init(halmac_obj, _TRUE);
+
+	result = halmac_obj->halmac_api_entry->halmac_get_chip_version(halmac_obj->halmac_adapter, &chip_version);
+
+	halmac_obj->version = HALMAC_VERSION(chip_version.major_ver, chip_version.prototype_ver, chip_version.minor_ver);
+
+	pDriver_adapter = halmac_obj->halmac_adapter->pDriver_adapter;
+	pHalmac_adapter = halmac_obj->halmac_adapter;
+
+	PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_init, current ver = 0x%x!!\n", HALMAC_CURRENT_VERSION);
+	PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_init, 88xx ver = 0x%x!!\n", halmac_obj->version);
+
+	return result;
+}
+
+HALMAC_RET_STATUS
+halmac_deinitialize_obj(
+	IN struct _HALMAC_OBJ *halmac_obj,
+	INOUT PHALMAC_TLP_STRUCT ptlp,
+	IN	u32 tlpCount
+)
+{
+	u32 arg_count = tlpCount;
+	HALMAC_RET_STATUS result = HALMAC_RET_SUCCESS;
+	HALMAC_TLP_STRUCT arg_list[MAX_ARG_NUM] = {0};
+
+	if (!is_halmac_initialized(halmac_obj))
+		return HALMAC_RET_NOT_SUPPORT;
+
+	if (!parse_halmac_api_arg_list(HALMAC_API_DEINIT_OBJ, &arg_list[0], ptlp, &arg_count))
+		return HALMAC_RET_WRONG_ARGUMENT;
+
+	halmac_obj_init(halmac_obj, _FALSE);
+	result = halmac_deinit_adapter(halmac_obj->halmac_adapter);
+
+	halmac_obj->halmac_api_entry = (PHALMAC_API)0;
+	halmac_obj->halmac_adapter = (PHALMAC_ADAPTER)0;
+
+	return result;
+}
+
+HALMAC_RET_STATUS
+halmac_set_information(
+	IN struct _HALMAC_OBJ *halmac_obj,
+	IN HALMAC_API_ID api_id,
+	INOUT PHALMAC_TLP_STRUCT ptlp,
+	IN u32 tlpCount
+)
+{
+	u32 arg_count = tlpCount;
+	HALMAC_RET_STATUS state = HALMAC_RET_SUCCESS;
+	HALMAC_TLP_STRUCT arg_list[MAX_ARG_NUM] = {0};
+	PHALMAC_ADAPTER pHalmac_adapter = halmac_obj->halmac_adapter;
+	VOID *pDriver_adapter = halmac_obj->halmac_adapter->pDriver_adapter;
+
+	if (!is_halmac_initialized(halmac_obj))
+		return HALMAC_RET_NOT_SUPPORT;
+
+	if (!parse_halmac_api_arg_list(api_id, &arg_list[0], ptlp, &arg_count))
+		return HALMAC_RET_WRONG_ARGUMENT;
+
+	state = HALMAC_RET_NOT_SUPPORT;
+
+	switch (api_id) {
+#if (HALMAC_VERSION(1, 2, 0) <= HALMAC_CURRENT_VERSION)
+	case HALMAC_API_MAC_POWER_SWITCH:
+		if (halmac_obj->version >= HALMAC_VERSION(1, 2, 0))
+			state = halmac_obj->halmac_api_entry->halmac_mac_power_switch(halmac_obj->halmac_adapter, *((HALMAC_MAC_POWER *)arg_list[0].ptr));
+		break;
+	case HALMAC_API_DOWNLOAD_FIRMWARE:
+		if (halmac_obj->version >= HALMAC_VERSION(1, 2, 0))
+			state = halmac_obj->halmac_api_entry->halmac_download_firmware(halmac_obj->halmac_adapter, (u8 *)arg_list[0].ptr, arg_list[0].length);
+		break;
+	case HALMAC_API_CFG_MAC_ADDR:
+		if (halmac_obj->version >= HALMAC_VERSION(1, 2, 0))
+			state = halmac_obj->halmac_api_entry->halmac_cfg_mac_addr(halmac_obj->halmac_adapter, *((u8 *)arg_list[0].ptr), (PHALMAC_WLAN_ADDR)arg_list[1].ptr);
+		break;
+	case HALMAC_API_CFG_BSSID:
+		if (halmac_obj->version >= HALMAC_VERSION(1, 2, 0))
+			state = halmac_obj->halmac_api_entry->halmac_cfg_bssid(halmac_obj->halmac_adapter, *((u8 *)arg_list[0].ptr), (PHALMAC_WLAN_ADDR)arg_list[1].ptr);
+		break;
+	case HALMAC_API_CFG_MULTICAST_ADDR:
+		if (halmac_obj->version >= HALMAC_VERSION(1, 2, 0))
+			state = halmac_obj->halmac_api_entry->halmac_cfg_multicast_addr(halmac_obj->halmac_adapter, (PHALMAC_WLAN_ADDR)arg_list[0].ptr);
+		break;
+	case HALMAC_API_PRE_INIT_SYSTEM_CFG:
+		if (halmac_obj->version >= HALMAC_VERSION(1, 2, 0))
+			state = halmac_obj->halmac_api_entry->halmac_pre_init_system_cfg(halmac_obj->halmac_adapter);
+		break;
+	case HALMAC_API_INIT_SYSTEM_CFG:
+		if (halmac_obj->version >= HALMAC_VERSION(1, 2, 0))
+			state = halmac_obj->halmac_api_entry->halmac_init_system_cfg(halmac_obj->halmac_adapter);
+		break;
+	case HALMAC_API_INIT_TRX_CFG:
+		if (halmac_obj->version >= HALMAC_VERSION(1, 2, 0))
+			state = halmac_obj->halmac_api_entry->halmac_init_trx_cfg(halmac_obj->halmac_adapter, *((HALMAC_TRX_MODE *)arg_list[0].ptr));
+		break;
+	case HALMAC_API_CFG_RX_AGGREGATION:
+		if (halmac_obj->version >= HALMAC_VERSION(1, 2, 0))
+			state = halmac_obj->halmac_api_entry->halmac_cfg_rx_aggregation(halmac_obj->halmac_adapter, (HALMAC_RXAGG_CFG *)arg_list[0].ptr);
+		break;
+	case HALMAC_API_CFG_OPERATION_MODE:
+		if (halmac_obj->version >= HALMAC_VERSION(1, 2, 0))
+			state = halmac_obj->halmac_api_entry->halmac_cfg_operation_mode(halmac_obj->halmac_adapter, *((HALMAC_WIRELESS_MODE *)arg_list[0].ptr));
+		break;
+	case HALMAC_API_CFG_BW:
+		if (halmac_obj->version >= HALMAC_VERSION(1, 2, 0))
+			state = halmac_obj->halmac_api_entry->halmac_cfg_bw(halmac_obj->halmac_adapter, *((HALMAC_BW *)arg_list[0].ptr));
+		break;
+	case HALMAC_API_INIT_MAC_CFG:
+		if (halmac_obj->version >= HALMAC_VERSION(1, 2, 0))
+			state = halmac_obj->halmac_api_entry->halmac_init_mac_cfg(halmac_obj->halmac_adapter, *((HALMAC_TRX_MODE *)arg_list[0].ptr));
+		break;
+	case HALMAC_API_INIT_SDIO_CFG:
+		if (halmac_obj->version >= HALMAC_VERSION(1, 3, 0))
+			state = halmac_obj->halmac_api_entry->halmac_init_interface_cfg(halmac_obj->halmac_adapter);
+		else if (halmac_obj->version >= HALMAC_VERSION(1, 2, 0))
+			state = halmac_obj->halmac_api_entry->halmac_init_sdio_cfg(halmac_obj->halmac_adapter);
+		break;
+	case HALMAC_API_INIT_USB_CFG:
+		if (halmac_obj->version >= HALMAC_VERSION(1, 3, 0))
+			state = halmac_obj->halmac_api_entry->halmac_init_interface_cfg(halmac_obj->halmac_adapter);
+		else if (halmac_obj->version >= HALMAC_VERSION(1, 2, 0))
+			state = halmac_obj->halmac_api_entry->halmac_init_usb_cfg(halmac_obj->halmac_adapter);
+		break;
+	case HALMAC_API_INIT_PCIE_CFG:
+		if (halmac_obj->version >= HALMAC_VERSION(1, 3, 0))
+			state = halmac_obj->halmac_api_entry->halmac_init_interface_cfg(halmac_obj->halmac_adapter);
+		else if (halmac_obj->version >= HALMAC_VERSION(1, 2, 0))
+			state = halmac_obj->halmac_api_entry->halmac_init_pcie_cfg(halmac_obj->halmac_adapter);
+		break;
+	case HALMAC_API_DEINIT_SDIO_CFG:
+		if (halmac_obj->version >= HALMAC_VERSION(1, 3, 0))
+			state = halmac_obj->halmac_api_entry->halmac_deinit_interface_cfg(halmac_obj->halmac_adapter);
+		else if (halmac_obj->version >= HALMAC_VERSION(1, 2, 0))
+			state = halmac_obj->halmac_api_entry->halmac_deinit_sdio_cfg(halmac_obj->halmac_adapter);
+		break;
+	case HALMAC_API_DEINIT_USB_CFG:
+		if (halmac_obj->version >= HALMAC_VERSION(1, 3, 0))
+			state = halmac_obj->halmac_api_entry->halmac_deinit_interface_cfg(halmac_obj->halmac_adapter);
+		else if (halmac_obj->version >= HALMAC_VERSION(1, 2, 0))
+			state = halmac_obj->halmac_api_entry->halmac_deinit_usb_cfg(halmac_obj->halmac_adapter);
+		break;
+	case HALMAC_API_DEINIT_PCIE_CFG:
+		if (halmac_obj->version >= HALMAC_VERSION(1, 3, 0))
+			state = halmac_obj->halmac_api_entry->halmac_deinit_interface_cfg(halmac_obj->halmac_adapter);
+		else if (halmac_obj->version >= HALMAC_VERSION(1, 2, 0))
+			state = halmac_obj->halmac_api_entry->halmac_deinit_pcie_cfg(halmac_obj->halmac_adapter);
+		break;
+	case HALMAC_API_WRITE_EFUSE:
+		if (halmac_obj->version >= HALMAC_VERSION(1, 2, 0))
+			state = halmac_obj->halmac_api_entry->halmac_write_efuse(halmac_obj->halmac_adapter, *((u32 *)arg_list[0].ptr), *((u8 *)arg_list[1].ptr));
+		break;
+	case HALMAC_API_PG_EFUSE_BY_MAP:
+		if (halmac_obj->version >= HALMAC_VERSION(1, 2, 0))
+			state = halmac_obj->halmac_api_entry->halmac_pg_efuse_by_map(halmac_obj->halmac_adapter, (PHALMAC_PG_EFUSE_INFO)arg_list[0].ptr, *((HALMAC_EFUSE_READ_CFG *)arg_list[1].ptr));
+		break;
+	case HALMAC_API_GET_C2H_INFO:
+		if (halmac_obj->version >= HALMAC_VERSION(1, 2, 0))
+			state = halmac_obj->halmac_api_entry->halmac_get_c2h_info(halmac_obj->halmac_adapter, (u8 *)arg_list[0].ptr, arg_list[0].length);
+		break;
+	case HALMAC_API_H2C_LB:
+		if (halmac_obj->version >= HALMAC_VERSION(1, 2, 0))
+			state = halmac_obj->halmac_api_entry->halmac_h2c_lb(halmac_obj->halmac_adapter);
+		break;
+	case HALMAC_API_CFG_PARAMETER:
+		if (halmac_obj->version >= HALMAC_VERSION(1, 2, 0))
+			state = halmac_obj->halmac_api_entry->halmac_cfg_parameter(halmac_obj->halmac_adapter, (PHALMAC_PHY_PARAMETER_INFO)(arg_list[0].ptr), *((u8 *)arg_list[1].ptr));
+		break;
+	case HALMAC_API_UPDATE_PACKET:
+		if (halmac_obj->version >= HALMAC_VERSION(1, 2, 0))
+			state = halmac_obj->halmac_api_entry->halmac_update_packet(halmac_obj->halmac_adapter, *((HALMAC_PACKET_ID *)arg_list[0].ptr), (u8 *)arg_list[1].ptr, arg_list[1].length);
+		break;
+	case HALMAC_API_SET_BULKOUT_NUM:
+		if (halmac_obj->version >= HALMAC_VERSION(1, 2, 0))
+			state = halmac_obj->halmac_api_entry->halmac_set_bulkout_num(halmac_obj->halmac_adapter, *((u8 *)arg_list[0].ptr));
+		break;
+	case HALMAC_API_CFG_DRV_INFO:
+		if (halmac_obj->version >= HALMAC_VERSION(1, 2, 0))
+			state = halmac_obj->halmac_api_entry->halmac_cfg_drv_info(halmac_obj->halmac_adapter, *((HALMAC_DRV_INFO *)arg_list[0].ptr));
+		break;
+	case HALMAC_API_SEND_BT_COEX:
+		if (halmac_obj->version >= HALMAC_VERSION(1, 2, 0))
+			state = halmac_obj->halmac_api_entry->halmac_send_bt_coex(halmac_obj->halmac_adapter, (u8 *)arg_list[0].ptr, arg_list[0].length, *((u8 *)arg_list[1].ptr));
+		break;
+	case HALMAC_API_VERIFY_PLATFORM_API:
+		if (halmac_obj->version >= HALMAC_VERSION(1, 2, 0))
+			state = halmac_obj->halmac_api_entry->halmac_verify_platform_api(halmac_obj->halmac_adapter);
+		break;
+	case HALMAC_API_CFG_TXBF:
+		if (halmac_obj->version >= HALMAC_VERSION(1, 2, 0))
+			state = halmac_obj->halmac_api_entry->halmac_cfg_txbf(halmac_obj->halmac_adapter, *((u8 *)arg_list[0].ptr), *((HALMAC_BW *)arg_list[1].ptr), *((u8 *)arg_list[2].ptr));
+		break;
+	case HALMAC_API_CFG_MUMIMO:
+		if (halmac_obj->version >= HALMAC_VERSION(1, 2, 0))
+			state = halmac_obj->halmac_api_entry->halmac_cfg_mumimo(halmac_obj->halmac_adapter, (PHALMAC_CFG_MUMIMO_PARA)arg_list[0].ptr);
+		break;
+	case HALMAC_API_CFG_SOUNDING:
+		if (halmac_obj->version >= HALMAC_VERSION(1, 2, 0))
+			state = halmac_obj->halmac_api_entry->halmac_cfg_sounding(halmac_obj->halmac_adapter, *((HALMAC_SND_ROLE *)arg_list[0].ptr), *((HALMAC_DATA_RATE *)arg_list[1].ptr));
+		break;
+	case HALMAC_API_DEL_SOUNDING:
+		if (halmac_obj->version >= HALMAC_VERSION(1, 2, 0))
+			state = halmac_obj->halmac_api_entry->halmac_del_sounding(halmac_obj->halmac_adapter, *((HALMAC_SND_ROLE *)arg_list[0].ptr));
+		break;
+	case HALMAC_API_SU_BFER_ENTRY_INIT:
+		if (halmac_obj->version >= HALMAC_VERSION(1, 2, 0))
+			state = halmac_obj->halmac_api_entry->halmac_su_bfer_entry_init(halmac_obj->halmac_adapter, (PHALMAC_SU_BFER_INIT_PARA)arg_list[0].ptr);
+		break;
+	case HALMAC_API_SU_BFEE_ENTRY_INIT:
+		if (halmac_obj->version >= HALMAC_VERSION(1, 2, 0))
+			state = halmac_obj->halmac_api_entry->halmac_su_bfee_entry_init(halmac_obj->halmac_adapter, *((u8 *)arg_list[0].ptr), *((u16 *)arg_list[1].ptr));
+		break;
+	case HALMAC_API_MU_BFER_ENTRY_INIT:
+		if (halmac_obj->version >= HALMAC_VERSION(1, 2, 0))
+			state = halmac_obj->halmac_api_entry->halmac_mu_bfer_entry_init(halmac_obj->halmac_adapter, (PHALMAC_MU_BFER_INIT_PARA)arg_list[0].ptr);
+		break;
+	case HALMAC_API_MU_BFEE_ENTRY_INIT:
+		if (halmac_obj->version >= HALMAC_VERSION(1, 2, 0))
+			state = halmac_obj->halmac_api_entry->halmac_mu_bfee_entry_init(halmac_obj->halmac_adapter, (PHALMAC_MU_BFEE_INIT_PARA)arg_list[0].ptr);
+		break;
+	case HALMAC_API_SU_BFER_ENTRY_DEL:
+		if (halmac_obj->version >= HALMAC_VERSION(1, 2, 0))
+			state = halmac_obj->halmac_api_entry->halmac_su_bfer_entry_del(halmac_obj->halmac_adapter, *((u8 *)arg_list[0].ptr));
+		break;
+	case HALMAC_API_SU_BFEE_ENTRY_DEL:
+		if (halmac_obj->version >= HALMAC_VERSION(1, 2, 0))
+			state = halmac_obj->halmac_api_entry->halmac_su_bfee_entry_del(halmac_obj->halmac_adapter, *((u8 *)arg_list[0].ptr));
+		break;
+	case HALMAC_API_MU_BFER_ENTRY_DEL:
+		if (halmac_obj->version >= HALMAC_VERSION(1, 2, 0))
+			state = halmac_obj->halmac_api_entry->halmac_mu_bfer_entry_del(halmac_obj->halmac_adapter);
+		break;
+	case HALMAC_API_MU_BFEE_ENTRY_DEL:
+		if (halmac_obj->version >= HALMAC_VERSION(1, 2, 0))
+			state = halmac_obj->halmac_api_entry->halmac_mu_bfee_entry_del(halmac_obj->halmac_adapter, *((u8 *)arg_list[0].ptr));
+		break;
+	case HALMAC_API_ADD_CH_INFO:
+		if (halmac_obj->version >= HALMAC_VERSION(1, 2, 0))
+			state = halmac_obj->halmac_api_entry->halmac_add_ch_info(halmac_obj->halmac_adapter, (PHALMAC_CH_INFO)arg_list[0].ptr);
+		break;
+	case HALMAC_API_CTRL_CH_SWITCH:
+		if (halmac_obj->version >= HALMAC_VERSION(1, 2, 0))
+			state = halmac_obj->halmac_api_entry->halmac_ctrl_ch_switch(halmac_obj->halmac_adapter, (PHALMAC_CH_SWITCH_OPTION)arg_list[0].ptr);
+		break;
+	case HALMAC_API_CLEAR_CH_INFO:
+		if (halmac_obj->version >= HALMAC_VERSION(1, 2, 0))
+			state = halmac_obj->halmac_api_entry->halmac_clear_ch_info(halmac_obj->halmac_adapter);
+		break;
+	case HALMAC_API_SEND_GENERAL_INFO:
+		if (halmac_obj->version >= HALMAC_VERSION(1, 2, 0))
+			state = halmac_obj->halmac_api_entry->halmac_send_general_info(halmac_obj->halmac_adapter, (PHALMAC_GENERAL_INFO)arg_list[0].ptr);
+		break;
+	case HALMAC_API_RESET_FEATURE:
+		if (halmac_obj->version >= HALMAC_VERSION(1, 2, 0))
+			state = halmac_obj->halmac_api_entry->halmac_reset_feature(halmac_obj->halmac_adapter, *((HALMAC_FEATURE_ID *)arg_list[0].ptr));
+		break;
+	case HALMAC_API_WRITE_LOGICAL_EFUSE:
+		if (halmac_obj->version >= HALMAC_VERSION(1, 2, 0))
+			state = halmac_obj->halmac_api_entry->halmac_write_logical_efuse(halmac_obj->halmac_adapter, *((u32 *)arg_list[0].ptr), *((u8 *)arg_list[1].ptr));
+		break;
+	case HALMAC_API_CTRL_PWR_TRACKING:
+		if (halmac_obj->version >= HALMAC_VERSION(1, 2, 0))
+			state = halmac_obj->halmac_api_entry->halmac_ctrl_pwr_tracking(halmac_obj->halmac_adapter, (PHALMAC_PWR_TRACKING_OPTION)arg_list[0].ptr);
+		break;
+	case HALMAC_API_START_IQK:
+		if (halmac_obj->version >= HALMAC_VERSION(1, 2, 0))
+			state = halmac_obj->halmac_api_entry->halmac_start_iqk(halmac_obj->halmac_adapter, (PHALMAC_IQK_PARA)arg_list[0].ptr);
+		break;
+	case HALMAC_API_CFG_LA_MODE:
+		if (halmac_obj->version >= HALMAC_VERSION(1, 2, 0))
+			state = halmac_obj->halmac_api_entry->halmac_cfg_la_mode(halmac_obj->halmac_adapter, *((HALMAC_LA_MODE *)arg_list[0].ptr));
+		break;
+	case HALMAC_API_SET_HW_VALUE:
+		if (halmac_obj->version >= HALMAC_VERSION(1, 2, 0))
+			state = halmac_obj->halmac_api_entry->halmac_set_hw_value(halmac_obj->halmac_adapter, *((HALMAC_HW_ID *)arg_list[0].ptr), (VOID *)arg_list[1].ptr);
+		break;
+	case HALMAC_API_CFG_DRV_RSVD_PG_NUM:
+		if (halmac_obj->version >= HALMAC_VERSION(1, 2, 0))
+			state = halmac_obj->halmac_api_entry->halmac_cfg_drv_rsvd_pg_num(halmac_obj->halmac_adapter, *((HALMAC_DRV_RSVD_PG_NUM *)arg_list[0].ptr));
+		break;
+	case HALMAC_API_SWITCH_EFUSE_BANK:
+		if (halmac_obj->version >= HALMAC_VERSION(1, 2, 0))
+			state = halmac_obj->halmac_api_entry->halmac_switch_efuse_bank(halmac_obj->halmac_adapter, (HALMAC_EFUSE_BANK)*((u16 *)arg_list[0].ptr));
+		break;
+	case HALMAC_API_WRITE_EFUSE_BT:
+		if (halmac_obj->version >= HALMAC_VERSION(1, 2, 0))
+			state = halmac_obj->halmac_api_entry->halmac_write_efuse_bt(halmac_obj->halmac_adapter, *((u32 *)arg_list[0].ptr), *((u8 *)arg_list[1].ptr), (HALMAC_EFUSE_BANK)*((u16 *)arg_list[2].ptr));
+		break;
+	case HALMAC_API_CFG_CSI_RATE:
+		if (halmac_obj->version >= HALMAC_VERSION(1, 2, 0))
+			state = halmac_obj->halmac_api_entry->halmac_cfg_csi_rate(halmac_obj->halmac_adapter, *((u8 *)arg_list[0].ptr), *((u8 *)arg_list[1].ptr), *((u8 *)arg_list[2].ptr), (u8 *)arg_list[3].ptr);
+		break;
+	case HALMAC_API_DL_DRV_RSVD_PG:
+		if (halmac_obj->version >= HALMAC_VERSION(1, 2, 0))
+			state = halmac_obj->halmac_api_entry->halmac_dl_drv_rsvd_page(halmac_obj->halmac_adapter, *((u8 *)arg_list[0].ptr), (u8 *)arg_list[1].ptr, arg_list[1].length);
+		break;
+#endif
+#if (HALMAC_VERSION(1, 3, 0) <= HALMAC_CURRENT_VERSION)
+	case HALMAC_API_PHY_CFG:
+		if (halmac_obj->version >= HALMAC_VERSION(1, 3, 0))
+			state = halmac_obj->halmac_api_entry->halmac_phy_cfg(halmac_obj->halmac_adapter, *((HALMAC_INTF_PHY_PLATFORM *)arg_list[0].ptr));
+		break;
+	case HALMAC_API_DEBUG:
+		if (halmac_obj->version >= HALMAC_VERSION(1, 3, 0))
+			state = halmac_obj->halmac_api_entry->halmac_debug(halmac_obj->halmac_adapter);
+		break;
+	case HALMAC_API_CFG_TX_AGG_ALIGN:
+		if (halmac_obj->version >= HALMAC_VERSION(1, 3, 0))
+			state = halmac_obj->halmac_api_entry->halmac_cfg_tx_agg_align(halmac_obj->halmac_adapter, *((u8 *)arg_list[0].ptr), *((u16 *)arg_list[1].ptr));
+		break;
+	case HALMAC_API_CFG_MAX_DL_SIZE:
+		if (halmac_obj->version >= HALMAC_VERSION(1, 3, 0))
+			state = halmac_obj->halmac_api_entry->halmac_cfg_max_dl_size(halmac_obj->halmac_adapter, *((u32 *)arg_list[0].ptr));
+		break;
+	case HALMAC_API_CFG_RX_FIFO_EXPANDING_MODE:
+		if (halmac_obj->version >= HALMAC_VERSION(1, 3, 0))
+			state = halmac_obj->halmac_api_entry->halmac_cfg_rx_fifo_expanding_mode(halmac_obj->halmac_adapter, *((HALMAC_RX_FIFO_EXPANDING_MODE *)arg_list[0].ptr));
+		break;
+	case HALMAC_API_CHK_TXDESC:
+		if (halmac_obj->version >= HALMAC_VERSION(1, 3, 0))
+			state = halmac_obj->halmac_api_entry->halmac_chk_txdesc(halmac_obj->halmac_adapter, (u8 *)arg_list[0].ptr, arg_list[0].length);
+		break;
+	case HALMAC_API_PCIE_SWITCH:
+		if (halmac_obj->version >= HALMAC_VERSION(1, 3, 0))
+			state = halmac_obj->halmac_api_entry->halmac_pcie_switch(halmac_obj->halmac_adapter, *((HALMAC_PCIE_CFG *)arg_list[0].ptr));
+		break;
+	case HALMAC_API_SDIO_CMD53_4BYTE:
+		if (halmac_obj->version >= HALMAC_VERSION(1, 3, 0))
+			state = halmac_obj->halmac_api_entry->halmac_sdio_cmd53_4byte(halmac_obj->halmac_adapter, *((HALMAC_SDIO_CMD53_4BYTE_MODE *)arg_list[0].ptr));
+		break;
+	case HALMAC_API_INTF_INTEGRA_TUNING:
+		if (halmac_obj->version >= HALMAC_VERSION(1, 3, 0))
+			state = halmac_obj->halmac_api_entry->halmac_interface_integration_tuning(halmac_obj->halmac_adapter);
+		break;
+	case HALMAC_API_TXFIFO_IS_EMPTY:
+		if (halmac_obj->version >= HALMAC_VERSION(1, 3, 3))
+			state = halmac_obj->halmac_api_entry->halmac_txfifo_is_empty(halmac_obj->halmac_adapter, *((u32 *)arg_list[0].ptr));
+		break;
+	case HALMAC_API_P2PPS:
+		if (halmac_obj->version >= HALMAC_VERSION(1, 3, 3))
+			state = halmac_obj->halmac_api_entry->halmac_p2pps(halmac_obj->halmac_adapter, (PHALMAC_P2PPS)arg_list[0].ptr);
+		break;
+	case HALMAC_API_FREE_DOWNLOAD_FIRMWARE:
+		if (halmac_obj->version >= HALMAC_VERSION(1, 3, 5))
+			state = halmac_obj->halmac_api_entry->halmac_free_download_firmware(halmac_obj->halmac_adapter, *((HALMAC_DLFW_MEM *)arg_list[0].ptr), (u8 *)arg_list[1].ptr, arg_list[1].length);
+		break;
+	case HALMAC_API_SDIO_HW_INFO:
+		if (halmac_obj->version >= HALMAC_VERSION(1, 3, 6))
+			state = halmac_obj->halmac_api_entry->halmac_sdio_hw_info(halmac_obj->halmac_adapter, (PHALMAC_SDIO_HW_INFO)arg_list[0].ptr);
+		break;
+#endif
+#if (HALMAC_VERSION(1, 4, 0) <= HALMAC_CURRENT_VERSION)
+	case HALMAC_API_REGISTER_API:
+		if (halmac_obj->version >= HALMAC_VERSION(1, 4, 0))
+			state = halmac_obj->halmac_api_entry->halmac_register_api(halmac_obj->halmac_adapter, (PHALMAC_API_REGISTRY)arg_list[0].ptr);
+		break;
+	case HALMAC_API_CFG_TRANS_ADDR:
+		if (halmac_obj->version >= HALMAC_VERSION(1, 4, 0))
+			state = halmac_obj->halmac_api_entry->halmac_cfg_transmitter_addr(halmac_obj->halmac_adapter, *((u8 *)arg_list[0].ptr), (PHALMAC_WLAN_ADDR)arg_list[1].ptr);
+		break;
+	case HALMAC_API_CFG_NET_TYPE:
+		if (halmac_obj->version >= HALMAC_VERSION(1, 4, 0))
+			state = halmac_obj->halmac_api_entry->halmac_cfg_net_type(halmac_obj->halmac_adapter, *((u8 *)arg_list[0].ptr), *((HALMAC_NETWORK_TYPE_SELECT *)arg_list[1].ptr));
+		break;
+	case HALMAC_API_CFG_TSF_RESET:
+		if (halmac_obj->version >= HALMAC_VERSION(1, 4, 0))
+			state = halmac_obj->halmac_api_entry->halmac_cfg_tsf_rst(halmac_obj->halmac_adapter, *((u8 *)arg_list[0].ptr));
+		break;
+	case HALMAC_API_CFG_BCN_SPACE:
+		if (halmac_obj->version >= HALMAC_VERSION(1, 4, 0))
+			state = halmac_obj->halmac_api_entry->halmac_cfg_bcn_space(halmac_obj->halmac_adapter, *((u8 *)arg_list[0].ptr), *((u32 *)arg_list[1].ptr));
+		break;
+	case HALMAC_API_CFG_BCN_CTRL:
+		if (halmac_obj->version >= HALMAC_VERSION(1, 4, 0))
+			state = halmac_obj->halmac_api_entry->halmac_rw_bcn_ctrl(halmac_obj->halmac_adapter, *((u8 *)arg_list[0].ptr), *((u8 *)arg_list[1].ptr), (PHALMAC_BCN_CTRL)arg_list[2].ptr);
+		break;
+	case HALMAC_API_CFG_SIDEBAND_INT:
+		if (halmac_obj->version >= HALMAC_VERSION(1, 4, 0))
+			state = halmac_obj->halmac_api_entry->halmac_cfg_sideband_int(halmac_obj->halmac_adapter, *((HALMAC_SIDEBAND_INT_CFG *)arg_list[0].ptr));
+		break;
+#endif
+	default:
+		state = HALMAC_RET_NOT_SUPPORT;
+		PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_WARN, "halmac_set_information, HALMAC ver = %x, api_id = %x,HALMAC_RET_NOT_SUPPORT !!\n", halmac_obj->version, api_id, state);
+		break;
+	}
+
+	if (state != HALMAC_RET_SUCCESS)
+		PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_WARN, "halmac_setinformation, HALMAC ver = %x, api_id = %x, state = %x!!\n", halmac_obj->version, api_id, state);
+	else
+		PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "[TRACE] halmac_setinformation, api_id = %x, state = %x!!\n", api_id, state);
+
+	return state;
+}
+
+HALMAC_RET_STATUS
+halmac_get_information(
+	IN struct _HALMAC_OBJ *halmac_obj,
+	IN HALMAC_API_ID api_id,
+	INOUT PHALMAC_TLP_STRUCT ptlp,
+	IN u32 tlpCount
+)
+{
+	u32 arg_count = tlpCount;
+	HALMAC_RET_STATUS state = HALMAC_RET_SUCCESS;
+	HALMAC_TLP_STRUCT arg_list[MAX_ARG_NUM] = {0};
+	PHALMAC_ADAPTER pHalmac_adapter = halmac_obj->halmac_adapter;
+	VOID *pDriver_adapter = halmac_obj->halmac_adapter->pDriver_adapter;
+
+	if (!is_halmac_initialized(halmac_obj))
+		return HALMAC_RET_NOT_SUPPORT;
+
+	if (!parse_halmac_api_arg_list(api_id, &arg_list[0], ptlp, &arg_count))
+		return HALMAC_RET_WRONG_ARGUMENT;
+
+	state = HALMAC_RET_NOT_SUPPORT;
+
+	switch (api_id) {
+#if (HALMAC_VERSION(1, 2, 0) <= HALMAC_CURRENT_VERSION)
+	case HALMAC_API_GET_EFUSE_SIZE:
+		if (halmac_obj->version >= HALMAC_VERSION(1, 2, 0))
+			state = halmac_obj->halmac_api_entry->halmac_get_efuse_size(halmac_obj->halmac_adapter, (u32 *)arg_list[0].ptr);
+		break;
+	case HALMAC_API_DUMP_EFUSE_MAP:
+		if (halmac_obj->version >= HALMAC_VERSION(1, 2, 0))
+			state = halmac_obj->halmac_api_entry->halmac_dump_efuse_map(halmac_obj->halmac_adapter, *((HALMAC_EFUSE_READ_CFG *)arg_list[0].ptr));
+		break;
+	case HALMAC_API_READ_EFUSE:
+		if (halmac_obj->version >= HALMAC_VERSION(1, 2, 0))
+			state = halmac_obj->halmac_api_entry->halmac_read_efuse(halmac_obj->halmac_adapter, *((u32 *)arg_list[0].ptr), (u8 *)arg_list[1].ptr);
+		break;
+	case HALMAC_API_GET_LOGICAL_EFUSE_SIZE:
+		if (halmac_obj->version >= HALMAC_VERSION(1, 2, 0))
+			state = halmac_obj->halmac_api_entry->halmac_get_logical_efuse_size(halmac_obj->halmac_adapter, (u32 *)arg_list[0].ptr);
+		break;
+	case HALMAC_API_DUMP_LOGICAL_EFUSE_MAP:
+		if (halmac_obj->version >= HALMAC_VERSION(1, 2, 0))
+			state = halmac_obj->halmac_api_entry->halmac_dump_logical_efuse_map(halmac_obj->halmac_adapter, *((HALMAC_EFUSE_READ_CFG *)arg_list[0].ptr));
+		break;
+	case HALMAC_API_READ_LOGICAL_EFUSE:
+		if (halmac_obj->version >= HALMAC_VERSION(1, 2, 0))
+			state = halmac_obj->halmac_api_entry->halmac_read_logical_efuse(halmac_obj->halmac_adapter, *((u32 *)arg_list[0].ptr), (u8 *)arg_list[1].ptr);
+		break;
+	case HALMAC_API_TX_ALLOWED_SDIO:
+		if (halmac_obj->version >= HALMAC_VERSION(1, 2, 0))
+			state = halmac_obj->halmac_api_entry->halmac_tx_allowed_sdio(halmac_obj->halmac_adapter, (u8 *)arg_list[0].ptr, arg_list[0].length);
+		break;
+	case HALMAC_API_GET_SDIO_TX_ADDR:
+		if (halmac_obj->version >= HALMAC_VERSION(1, 2, 0))
+			state = halmac_obj->halmac_api_entry->halmac_get_sdio_tx_addr(halmac_obj->halmac_adapter, (u8 *)arg_list[0].ptr, arg_list[0].length, (u32 *)arg_list[1].ptr);
+		break;
+	case HALMAC_API_GET_USB_BULKOUT_ID:
+		if (halmac_obj->version >= HALMAC_VERSION(1, 2, 0))
+			state = halmac_obj->halmac_api_entry->halmac_get_usb_bulkout_id(halmac_obj->halmac_adapter, (u8 *)arg_list[0].ptr, arg_list[0].length, (u8 *)arg_list[1].ptr);
+		break;
+
+	case HALMAC_API_QUERY_STATE:
+		if (halmac_obj->version >= HALMAC_VERSION(1, 2, 0))
+			state = halmac_obj->halmac_api_entry->halmac_query_status(halmac_obj->halmac_adapter, *((HALMAC_FEATURE_ID *)arg_list[0].ptr), (HALMAC_CMD_PROCESS_STATUS *)arg_list[1].ptr, (u8 *)arg_list[2].ptr, (u32 *)arg_list[3].ptr);
+		break;
+	case HALMAC_API_CHECK_FW_STATUS:
+		if (halmac_obj->version >= HALMAC_VERSION(1, 2, 0))
+			state = halmac_obj->halmac_api_entry->halmac_check_fw_status(halmac_obj->halmac_adapter, (u8 *)arg_list[0].ptr);
+		break;
+	case HALMAC_API_DUMP_FW_DMEM:
+		if (halmac_obj->version >= HALMAC_VERSION(1, 2, 0))
+			state = halmac_obj->halmac_api_entry->halmac_dump_fw_dmem(halmac_obj->halmac_adapter, (u8 *)arg_list[0].ptr, (u32 *)arg_list[1].ptr);
+		break;
+	case HALMAC_API_GET_HW_VALUE:
+		if (halmac_obj->version >= HALMAC_VERSION(1, 2, 0))
+			state = halmac_obj->halmac_api_entry->halmac_get_hw_value(halmac_obj->halmac_adapter, *((HALMAC_HW_ID *)arg_list[0].ptr), (VOID *)arg_list[1].ptr);
+		break;
+	case HALMAC_API_DUMP_EFUSE_MAP_BT:
+		if (halmac_obj->version >= HALMAC_VERSION(1, 2, 0))
+			state = halmac_obj->halmac_api_entry->halmac_dump_efuse_map_bt(halmac_obj->halmac_adapter, (HALMAC_EFUSE_BANK)*((u16 *)arg_list[0].ptr), arg_list[1].length, (u8 *)arg_list[1].ptr);
+		break;
+#endif
+#if (HALMAC_VERSION(1, 3, 0) <= HALMAC_CURRENT_VERSION)
+	case HALMAC_API_GET_FW_VERSION:
+		if (halmac_obj->version >= HALMAC_VERSION(1, 3, 0))
+			state = halmac_obj->halmac_api_entry->halmac_get_fw_version(halmac_obj->halmac_adapter, (PHALMAC_FW_VERSION)arg_list[0].ptr);
+		break;
+	case HALMAC_API_GET_EFUSE_AVAL_SIZE:
+		if (halmac_obj->version >= HALMAC_VERSION(1, 3, 0))
+			state = halmac_obj->halmac_api_entry->halmac_get_efuse_available_size(halmac_obj->halmac_adapter, (u32 *)arg_list[0].ptr);
+		break;
+	case HALMAC_API_FILL_TXDESC_CHECKSUM:
+		if (halmac_obj->version >= HALMAC_VERSION(1, 3, 0))
+			state = halmac_obj->halmac_api_entry->halmac_fill_txdesc_checksum(halmac_obj->halmac_adapter, (u8 *)arg_list[0].ptr);
+		break;
+	case HALMAC_API_GET_FIFO_SIZE:
+		if (halmac_obj->version >= HALMAC_VERSION(1, 3, 0)) {
+			*((u32 *)arg_list[0].ptr) = halmac_obj->halmac_api_entry->halmac_get_fifo_size(halmac_obj->halmac_adapter, *((HAL_FIFO_SEL *)arg_list[0].ptr));
+			state = HALMAC_RET_SUCCESS;
+		}
+		break;
+	case HALMAC_API_DUMP_FIFO:
+		if (halmac_obj->version >= HALMAC_VERSION(1, 3, 0))
+			state = halmac_obj->halmac_api_entry->halmac_dump_fifo(halmac_obj->halmac_adapter, *((HAL_FIFO_SEL *)arg_list[0].ptr), *((u32 *)arg_list[1].ptr), arg_list[2].length, (u8 *)arg_list[2].ptr);
+		break;
+#endif
+	default:
+		PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_WARN, "halmac_get_information, HALMAC ver = %x, api_id = %x,HALMAC_RET_NOT_SUPPORT !!\n", halmac_obj->version, api_id, state);
+		state = HALMAC_RET_NOT_SUPPORT;
+		break;
+	}
+
+	if (state != HALMAC_RET_SUCCESS)
+		PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_WARN, "halmac_get_information, HALMAC ver = %x, api_id = %x, state = %x!!\n", halmac_obj->version, api_id, state);
+	else
+		PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "[TRACE] halmac_getinformation, api_id = %x, state = %x!!\n", api_id, state);
+
+	return state;
+}
+
+
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/halmac/halmac_module.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/halmac/halmac_module.h
--- linux-5.6.3/3rdparty/rtl8821ce/hal/halmac/halmac_module.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/halmac/halmac_module.h	2020-04-10 16:35:06.812659881 +0300
@@ -0,0 +1,115 @@
+#ifndef _HALMAC_MODULE_H_
+#define _HALMAC_MODULE_H_
+
+#define HALMAC_VERSION(a, b, c)		(((a) << 16) + ((b) << 8) + (c))
+#define	HALMAC_CURRENT_VERSION		HALMAC_VERSION(HALMAC_MAJOR_VER, HALMAC_PROTOTYPE_VER, HALMAC_MINOR_VER)
+
+#define MAX_ARG_NUM	10
+
+#define		TLP_TYPE_NONE							0x00000000
+#define		TLP_TYPE_PU8							0x00000001
+#define		TLP_TYPE_PU16							0x00000002
+#define		TLP_TYPE_PU32							0x00000003
+#define		TLP_TYPE_PU64							0x00000004
+#define		TLP_TYPE_PS8							0x00000005
+#define		TLP_TYPE_PS16							0x00000006
+#define		TLP_TYPE_PS32							0x00000007
+#define		TLP_TYPE_PS64							0x00000008
+#define		TLP_TYPE_PVOID							0x00000009
+#define		TLP_TYPE_PU8_BUFFER						0x0000000A
+#define		TLP_TYPE_POS_API_ENTRY					0x0000000B
+#define		TLP_TYPE_PHALMAC_WLAN_ADDR				0x0000000C
+#define		TLP_TYPE_PHALMAC_PHY_PARAMETER_INFO		0x0000000D
+#define		TLP_TYPE_PHALMAC_CH_INFO				0x0000000E
+#define		TLP_TYPE_PHALMAC_CH_SWITCH_OPTION		0x0000000F
+#define		TLP_TYPE_PHALMAC_GENERAL_INFO			0x00000010
+#define		TLP_TYPE_PHALMAC_CMD_PROCESS_STATUS		0x00000011
+#define		TLP_TYPE_PHALMAC_INTERFACE				0x00000012
+#define		TLP_TYPE_PHALMAC_MAC_POWER				0x00000013
+#define		TLP_TYPE_PHALMAC_RXAGG_CFG				0x00000014
+#define		TLP_TYPE_PHALMAC_WIRELESS_MODE			0x00000015
+#define		TLP_TYPE_PHALMAC_BW						0x00000016
+#define		TLP_TYPE_PHALMAC_TRX_MODE				0x00000017
+#define		TLP_TYPE_PHALMAC_EFUSE_READ_CFG			0x00000018
+#define		TLP_TYPE_PHALMAC_PACKET_ID				0x00000019
+#define		TLP_TYPE_PHALMAC_DRV_INFO				0x0000001A
+#define		TLP_TYPE_PHALMAC_FEATURE_ID				0x0000001B
+#define		TLP_TYPE_PHALMAC_HW_ID					0x0000001C
+#define		TLP_TYPE_PHALMAC_DRV_RSVD_PG_NUM		0x0000001D
+#define		TLP_TYPE_PHALMAC_LA_MODE				0x0000001E
+#define		TLP_TYPE_PHALMAC_PWR_TRACKING			0x0000001F
+#define		TLP_TYPE_PHALMAC_EFUSE_BANK				0x00000020
+#define		TLP_TYPE_PHALMAC_IQK					0x00000021
+#define		TLP_TYPE_PHALMAC_MU_BFER_INIT_PARA		0x00000022
+#define		TLP_TYPE_PHALMAC_MU_BFEE_INIT_PARA		0x00000023
+#define		TLP_TYPE_PHALMAC_SU_BFER_INIT_PARA		0x00000024
+#define		TLP_TYPE_PHALMAC_SND_ROLE				0x00000025
+#define		TLP_TYPE_PHALMAC_DATA_RATE				0x00000026
+#define		TLP_TYPE_PHALMAC_CFG_MUMIMO_PARA		0x00000027
+#define		TLP_TYPE_PU8_1							0x00000028
+#define		TLP_TYPE_PHALMAC_PG_EFUSE_INFO			0x00000029
+#define		TLP_TYPE_PU8_2							0x0000002A
+#define		TLP_TYPE_PHALMAC_INTF_PHY_PLATFORM		0x0000002B
+#define		TLP_TYPE_PHALMAC_API_REGISTRY			0x0000002C
+#define		TLP_TYPE_PHALMAC_DLFW_MEM				0x0000002D
+#define		TLP_TYPE_PHALMAC_FW_VERSION				0x0000002E
+#define		TLP_TYPE_PHALMAC_SIDEBAND_INT_CFG		0x0000002F
+#define		TLP_TYPE_PHALMAC_FIFO_SEL				0x00000030
+#define		TLP_TYPE_PHALMAC_P2PPS					0x00000031
+#define		TLP_TYPE_PHALMAC_RX_EXPAND_MODE			0x00000032
+#define		TLP_TYPE_PHALMAC_PCIE_CFG				0x00000033
+#define		TLP_TYPE_PHALMAC_SDIO_CMD53_4BYTE_MODE	0x00000034
+#define		TLP_TYPE_PHALMAC_NETWORK_TYPE_SELECT	0x00000035
+#define		TLP_TYPE_PHALMAC_BCN_CTRL				0x00000036
+#define		TLP_TYPE_PHALMAC_SDIO_HW_INFO			0x00000037
+
+typedef struct _HALMAC_TLP_STRUCT {
+	u32 type;
+	u32 length;
+	VOID *ptr;
+} HALMAC_TLP_STRUCT, *PHALMAC_TLP_STRUCT;
+
+typedef struct _HALMAC_API_ARG {
+	HALMAC_API_ID api_id;
+	u32 arg_count;
+	u32	arg_type_seq[MAX_ARG_NUM];
+} HALMAC_API_ARG, *PHALMAC_API_ARG;
+
+typedef struct _HALMAC_OBJ {
+	u8 init;
+	u32 version;
+	PHALMAC_ADAPTER	halmac_adapter;
+	PHALMAC_API	halmac_api_entry;
+} HALMAC_OBJ, *PHALMAC_OBJ;
+
+HALMAC_RET_STATUS
+halmac_initialize_obj(
+	IN struct _HALMAC_OBJ *halmac_obj,
+	INOUT PHALMAC_TLP_STRUCT ptlp,
+	IN	u32 tlpCount
+);
+
+HALMAC_RET_STATUS
+halmac_deinitialize_obj(
+	IN struct _HALMAC_OBJ *halmac_obj,
+	INOUT PHALMAC_TLP_STRUCT ptlp,
+	IN u32 tlpCount
+);
+
+HALMAC_RET_STATUS
+halmac_set_information(
+	IN struct _HALMAC_OBJ *halmac_obj,
+	IN HALMAC_API_ID	api_id,
+	INOUT PHALMAC_TLP_STRUCT ptlp,
+	IN u32 tlpCount
+);
+
+HALMAC_RET_STATUS
+halmac_get_information(
+	IN struct _HALMAC_OBJ *halmac_obj,
+	IN	HALMAC_API_ID	api_id,
+	INOUT PHALMAC_TLP_STRUCT ptlp,
+	IN	u32 tlpCount
+);
+
+#endif
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/halmac/halmac_original_c2h_ap.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/halmac/halmac_original_c2h_ap.h
--- linux-5.6.3/3rdparty/rtl8821ce/hal/halmac/halmac_original_c2h_ap.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/halmac/halmac_original_c2h_ap.h	2020-04-10 16:35:06.812659881 +0300
@@ -0,0 +1,650 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ ******************************************************************************/
+
+#ifndef _HAL_ORIGINALC2HFORMAT_H2C_C2H_AP_H_
+#define _HAL_ORIGINALC2HFORMAT_H2C_C2H_AP_H_
+#define CMD_ID_C2H 0X00
+#define CMD_ID_DBG 0X00
+#define CMD_ID_C2H_LB 0X01
+#define CMD_ID_C2H_SND_TXBF 0X02
+#define CMD_ID_C2H_CCX_RPT 0X03
+#define CMD_ID_C2H_AP_REQ_TXRPT 0X04
+#define CMD_ID_C2H_INITIAL_RATE_COLLECTION 0X05
+#define CMD_ID_C2H_RA_RPT 0X0C
+#define CMD_ID_C2H_SPECIAL_STATISTICS 0X0D
+#define CMD_ID_C2H_RA_PARA_RPT 0X0E
+#define CMD_ID_C2H_CUR_CHANNEL 0X10
+#define CMD_ID_C2H_GPIO_WAKEUP 0X14
+#define CMD_ID_C2H_DROPID_RPT 0X2D
+#define C2H_GET_CMD_ID(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X00, 0, 8)
+#define C2H_SET_CMD_ID(c2h_pkt, value)                                         \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 0, 8, value)
+#define C2H_SET_CMD_ID_NO_CLR(c2h_pkt, value)                                  \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 0, 8, value)
+#define C2H_GET_SEQ(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X00, 8, 8)
+#define C2H_SET_SEQ(c2h_pkt, value)                                            \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 8, 8, value)
+#define C2H_SET_SEQ_NO_CLR(c2h_pkt, value)                                     \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 8, 8, value)
+#define DBG_GET_CMD_ID(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X00, 0, 8)
+#define DBG_SET_CMD_ID(c2h_pkt, value)                                         \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 0, 8, value)
+#define DBG_SET_CMD_ID_NO_CLR(c2h_pkt, value)                                  \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 0, 8, value)
+#define DBG_GET_SEQ(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X00, 8, 8)
+#define DBG_SET_SEQ(c2h_pkt, value)                                            \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 8, 8, value)
+#define DBG_SET_SEQ_NO_CLR(c2h_pkt, value)                                     \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 8, 8, value)
+#define DBG_GET_DBG_STR1(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X00, 16, 8)
+#define DBG_SET_DBG_STR1(c2h_pkt, value)                                       \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 16, 8, value)
+#define DBG_SET_DBG_STR1_NO_CLR(c2h_pkt, value)                                \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 16, 8, value)
+#define DBG_GET_DBG_STR2(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X00, 24, 8)
+#define DBG_SET_DBG_STR2(c2h_pkt, value)                                       \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 24, 8, value)
+#define DBG_SET_DBG_STR2_NO_CLR(c2h_pkt, value)                                \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 24, 8, value)
+#define DBG_GET_DBG_STR3(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X04, 0, 8)
+#define DBG_SET_DBG_STR3(c2h_pkt, value)                                       \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X04, 0, 8, value)
+#define DBG_SET_DBG_STR3_NO_CLR(c2h_pkt, value)                                \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 0, 8, value)
+#define DBG_GET_DBG_STR4(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X04, 8, 8)
+#define DBG_SET_DBG_STR4(c2h_pkt, value)                                       \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X04, 8, 8, value)
+#define DBG_SET_DBG_STR4_NO_CLR(c2h_pkt, value)                                \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 8, 8, value)
+#define DBG_GET_DBG_STR5(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X04, 16, 8)
+#define DBG_SET_DBG_STR5(c2h_pkt, value)                                       \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X04, 16, 8, value)
+#define DBG_SET_DBG_STR5_NO_CLR(c2h_pkt, value)                                \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 16, 8, value)
+#define DBG_GET_DBG_STR6(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X04, 24, 8)
+#define DBG_SET_DBG_STR6(c2h_pkt, value)                                       \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X04, 24, 8, value)
+#define DBG_SET_DBG_STR6_NO_CLR(c2h_pkt, value)                                \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 24, 8, value)
+#define DBG_GET_DBG_STR7(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X08, 0, 8)
+#define DBG_SET_DBG_STR7(c2h_pkt, value)                                       \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X08, 0, 8, value)
+#define DBG_SET_DBG_STR7_NO_CLR(c2h_pkt, value)                                \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X08, 0, 8, value)
+#define DBG_GET_DBG_STR8(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X08, 8, 8)
+#define DBG_SET_DBG_STR8(c2h_pkt, value)                                       \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X08, 8, 8, value)
+#define DBG_SET_DBG_STR8_NO_CLR(c2h_pkt, value)                                \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X08, 8, 8, value)
+#define DBG_GET_DBG_STR9(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X08, 16, 8)
+#define DBG_SET_DBG_STR9(c2h_pkt, value)                                       \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X08, 16, 8, value)
+#define DBG_SET_DBG_STR9_NO_CLR(c2h_pkt, value)                                \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X08, 16, 8, value)
+#define DBG_GET_DBG_STR10(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X08, 24, 8)
+#define DBG_SET_DBG_STR10(c2h_pkt, value)                                      \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X08, 24, 8, value)
+#define DBG_SET_DBG_STR10_NO_CLR(c2h_pkt, value)                               \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X08, 24, 8, value)
+#define DBG_GET_DBG_STR11(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X0C, 0, 8)
+#define DBG_SET_DBG_STR11(c2h_pkt, value)                                      \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X0C, 0, 8, value)
+#define DBG_SET_DBG_STR11_NO_CLR(c2h_pkt, value)                               \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X0C, 0, 8, value)
+#define DBG_GET_DBG_STR12(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X0C, 8, 8)
+#define DBG_SET_DBG_STR12(c2h_pkt, value)                                      \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X0C, 8, 8, value)
+#define DBG_SET_DBG_STR12_NO_CLR(c2h_pkt, value)                               \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X0C, 8, 8, value)
+#define DBG_GET_LEN(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X0C, 16, 8)
+#define DBG_SET_LEN(c2h_pkt, value)                                            \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X0C, 16, 8, value)
+#define DBG_SET_LEN_NO_CLR(c2h_pkt, value)                                     \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X0C, 16, 8, value)
+#define DBG_GET_TRIGGER(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X0C, 24, 8)
+#define DBG_SET_TRIGGER(c2h_pkt, value)                                        \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X0C, 24, 8, value)
+#define DBG_SET_TRIGGER_NO_CLR(c2h_pkt, value)                                 \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X0C, 24, 8, value)
+#define C2H_LB_GET_CMD_ID(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X00, 0, 8)
+#define C2H_LB_SET_CMD_ID(c2h_pkt, value)                                      \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 0, 8, value)
+#define C2H_LB_SET_CMD_ID_NO_CLR(c2h_pkt, value)                               \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 0, 8, value)
+#define C2H_LB_GET_SEQ(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X00, 8, 8)
+#define C2H_LB_SET_SEQ(c2h_pkt, value)                                         \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 8, 8, value)
+#define C2H_LB_SET_SEQ_NO_CLR(c2h_pkt, value)                                  \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 8, 8, value)
+#define C2H_LB_GET_PAYLOAD1(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X00, 16, 16)
+#define C2H_LB_SET_PAYLOAD1(c2h_pkt, value)                                    \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 16, 16, value)
+#define C2H_LB_SET_PAYLOAD1_NO_CLR(c2h_pkt, value)                             \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 16, 16, value)
+#define C2H_LB_GET_PAYLOAD2(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X04, 0, 32)
+#define C2H_LB_SET_PAYLOAD2(c2h_pkt, value)                                    \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X04, 0, 32, value)
+#define C2H_LB_SET_PAYLOAD2_NO_CLR(c2h_pkt, value)                             \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 0, 32, value)
+#define C2H_LB_GET_LEN(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X0C, 16, 8)
+#define C2H_LB_SET_LEN(c2h_pkt, value)                                         \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X0C, 16, 8, value)
+#define C2H_LB_SET_LEN_NO_CLR(c2h_pkt, value)                                  \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X0C, 16, 8, value)
+#define C2H_LB_GET_TRIGGER(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X0C, 24, 8)
+#define C2H_LB_SET_TRIGGER(c2h_pkt, value)                                     \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X0C, 24, 8, value)
+#define C2H_LB_SET_TRIGGER_NO_CLR(c2h_pkt, value)                              \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X0C, 24, 8, value)
+#define C2H_SND_TXBF_GET_CMD_ID(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X00, 0, 8)
+#define C2H_SND_TXBF_SET_CMD_ID(c2h_pkt, value)                                \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 0, 8, value)
+#define C2H_SND_TXBF_SET_CMD_ID_NO_CLR(c2h_pkt, value)                         \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 0, 8, value)
+#define C2H_SND_TXBF_GET_SEQ(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X00, 8, 8)
+#define C2H_SND_TXBF_SET_SEQ(c2h_pkt, value)                                   \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 8, 8, value)
+#define C2H_SND_TXBF_SET_SEQ_NO_CLR(c2h_pkt, value)                            \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 8, 8, value)
+#define C2H_SND_TXBF_GET_SND_RESULT(c2h_pkt)                                   \
+	GET_C2H_FIELD(c2h_pkt + 0X00, 16, 1)
+#define C2H_SND_TXBF_SET_SND_RESULT(c2h_pkt, value)                            \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 16, 1, value)
+#define C2H_SND_TXBF_SET_SND_RESULT_NO_CLR(c2h_pkt, value)                     \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 16, 1, value)
+#define C2H_SND_TXBF_GET_LEN(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X0C, 16, 8)
+#define C2H_SND_TXBF_SET_LEN(c2h_pkt, value)                                   \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X0C, 16, 8, value)
+#define C2H_SND_TXBF_SET_LEN_NO_CLR(c2h_pkt, value)                            \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X0C, 16, 8, value)
+#define C2H_SND_TXBF_GET_TRIGGER(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X0C, 24, 8)
+#define C2H_SND_TXBF_SET_TRIGGER(c2h_pkt, value)                               \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X0C, 24, 8, value)
+#define C2H_SND_TXBF_SET_TRIGGER_NO_CLR(c2h_pkt, value)                        \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X0C, 24, 8, value)
+#define C2H_CCX_RPT_GET_CMD_ID(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X00, 0, 8)
+#define C2H_CCX_RPT_SET_CMD_ID(c2h_pkt, value)                                 \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 0, 8, value)
+#define C2H_CCX_RPT_SET_CMD_ID_NO_CLR(c2h_pkt, value)                          \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 0, 8, value)
+#define C2H_CCX_RPT_GET_SEQ(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X00, 8, 8)
+#define C2H_CCX_RPT_SET_SEQ(c2h_pkt, value)                                    \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 8, 8, value)
+#define C2H_CCX_RPT_SET_SEQ_NO_CLR(c2h_pkt, value)                             \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 8, 8, value)
+#define C2H_CCX_RPT_GET_QSEL(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X00, 16, 5)
+#define C2H_CCX_RPT_SET_QSEL(c2h_pkt, value)                                   \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 16, 5, value)
+#define C2H_CCX_RPT_SET_QSEL_NO_CLR(c2h_pkt, value)                            \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 16, 5, value)
+#define C2H_CCX_RPT_GET_BMC(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X00, 21, 1)
+#define C2H_CCX_RPT_SET_BMC(c2h_pkt, value)                                    \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 21, 1, value)
+#define C2H_CCX_RPT_SET_BMC_NO_CLR(c2h_pkt, value)                             \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 21, 1, value)
+#define C2H_CCX_RPT_GET_LIFE_TIME_OVER(c2h_pkt)                                \
+	GET_C2H_FIELD(c2h_pkt + 0X00, 22, 1)
+#define C2H_CCX_RPT_SET_LIFE_TIME_OVER(c2h_pkt, value)                         \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 22, 1, value)
+#define C2H_CCX_RPT_SET_LIFE_TIME_OVER_NO_CLR(c2h_pkt, value)                  \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 22, 1, value)
+#define C2H_CCX_RPT_GET_RETRY_OVER(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X00, 23, 1)
+#define C2H_CCX_RPT_SET_RETRY_OVER(c2h_pkt, value)                             \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 23, 1, value)
+#define C2H_CCX_RPT_SET_RETRY_OVER_NO_CLR(c2h_pkt, value)                      \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 23, 1, value)
+#define C2H_CCX_RPT_GET_MACID(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X00, 24, 8)
+#define C2H_CCX_RPT_SET_MACID(c2h_pkt, value)                                  \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 24, 8, value)
+#define C2H_CCX_RPT_SET_MACID_NO_CLR(c2h_pkt, value)                           \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 24, 8, value)
+#define C2H_CCX_RPT_GET_DATA_RETRY_CNT(c2h_pkt)                                \
+	GET_C2H_FIELD(c2h_pkt + 0X04, 0, 6)
+#define C2H_CCX_RPT_SET_DATA_RETRY_CNT(c2h_pkt, value)                         \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X04, 0, 6, value)
+#define C2H_CCX_RPT_SET_DATA_RETRY_CNT_NO_CLR(c2h_pkt, value)                  \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 0, 6, value)
+#define C2H_CCX_RPT_GET_QUEUE7_0(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X04, 8, 8)
+#define C2H_CCX_RPT_SET_QUEUE7_0(c2h_pkt, value)                               \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X04, 8, 8, value)
+#define C2H_CCX_RPT_SET_QUEUE7_0_NO_CLR(c2h_pkt, value)                        \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 8, 8, value)
+#define C2H_CCX_RPT_GET_QUEUE15_8(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X04, 16, 8)
+#define C2H_CCX_RPT_SET_QUEUE15_8(c2h_pkt, value)                              \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X04, 16, 8, value)
+#define C2H_CCX_RPT_SET_QUEUE15_8_NO_CLR(c2h_pkt, value)                       \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 16, 8, value)
+#define C2H_CCX_RPT_GET_FINAL_DATA_RATE(c2h_pkt)                               \
+	GET_C2H_FIELD(c2h_pkt + 0X04, 24, 8)
+#define C2H_CCX_RPT_SET_FINAL_DATA_RATE(c2h_pkt, value)                        \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X04, 24, 8, value)
+#define C2H_CCX_RPT_SET_FINAL_DATA_RATE_NO_CLR(c2h_pkt, value)                 \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 24, 8, value)
+#define C2H_CCX_RPT_GET_SW_DEFINE_0(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X08, 0, 8)
+#define C2H_CCX_RPT_SET_SW_DEFINE_0(c2h_pkt, value)                            \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X08, 0, 8, value)
+#define C2H_CCX_RPT_SET_SW_DEFINE_0_NO_CLR(c2h_pkt, value)                     \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X08, 0, 8, value)
+#define C2H_CCX_RPT_GET_SW_DEFINE_1(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X08, 8, 4)
+#define C2H_CCX_RPT_SET_SW_DEFINE_1(c2h_pkt, value)                            \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X08, 8, 4, value)
+#define C2H_CCX_RPT_SET_SW_DEFINE_1_NO_CLR(c2h_pkt, value)                     \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X08, 8, 4, value)
+#define C2H_CCX_RPT_GET_LEN(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X0C, 16, 8)
+#define C2H_CCX_RPT_SET_LEN(c2h_pkt, value)                                    \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X0C, 16, 8, value)
+#define C2H_CCX_RPT_SET_LEN_NO_CLR(c2h_pkt, value)                             \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X0C, 16, 8, value)
+#define C2H_CCX_RPT_GET_TRIGGER(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X0C, 24, 8)
+#define C2H_CCX_RPT_SET_TRIGGER(c2h_pkt, value)                                \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X0C, 24, 8, value)
+#define C2H_CCX_RPT_SET_TRIGGER_NO_CLR(c2h_pkt, value)                         \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X0C, 24, 8, value)
+#define C2H_AP_REQ_TXRPT_GET_CMD_ID(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X00, 0, 8)
+#define C2H_AP_REQ_TXRPT_SET_CMD_ID(c2h_pkt, value)                            \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 0, 8, value)
+#define C2H_AP_REQ_TXRPT_SET_CMD_ID_NO_CLR(c2h_pkt, value)                     \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 0, 8, value)
+#define C2H_AP_REQ_TXRPT_GET_SEQ(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X00, 8, 8)
+#define C2H_AP_REQ_TXRPT_SET_SEQ(c2h_pkt, value)                               \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 8, 8, value)
+#define C2H_AP_REQ_TXRPT_SET_SEQ_NO_CLR(c2h_pkt, value)                        \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 8, 8, value)
+#define C2H_AP_REQ_TXRPT_GET_STA1_MACID(c2h_pkt)                               \
+	GET_C2H_FIELD(c2h_pkt + 0X00, 16, 8)
+#define C2H_AP_REQ_TXRPT_SET_STA1_MACID(c2h_pkt, value)                        \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 16, 8, value)
+#define C2H_AP_REQ_TXRPT_SET_STA1_MACID_NO_CLR(c2h_pkt, value)                 \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 16, 8, value)
+#define C2H_AP_REQ_TXRPT_GET_TX_OK1_0(c2h_pkt)                                 \
+	GET_C2H_FIELD(c2h_pkt + 0X00, 24, 8)
+#define C2H_AP_REQ_TXRPT_SET_TX_OK1_0(c2h_pkt, value)                          \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 24, 8, value)
+#define C2H_AP_REQ_TXRPT_SET_TX_OK1_0_NO_CLR(c2h_pkt, value)                   \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 24, 8, value)
+#define C2H_AP_REQ_TXRPT_GET_TX_OK1_1(c2h_pkt)                                 \
+	GET_C2H_FIELD(c2h_pkt + 0X04, 0, 8)
+#define C2H_AP_REQ_TXRPT_SET_TX_OK1_1(c2h_pkt, value)                          \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X04, 0, 8, value)
+#define C2H_AP_REQ_TXRPT_SET_TX_OK1_1_NO_CLR(c2h_pkt, value)                   \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 0, 8, value)
+#define C2H_AP_REQ_TXRPT_GET_TX_FAIL1_0(c2h_pkt)                               \
+	GET_C2H_FIELD(c2h_pkt + 0X04, 8, 8)
+#define C2H_AP_REQ_TXRPT_SET_TX_FAIL1_0(c2h_pkt, value)                        \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X04, 8, 8, value)
+#define C2H_AP_REQ_TXRPT_SET_TX_FAIL1_0_NO_CLR(c2h_pkt, value)                 \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 8, 8, value)
+#define C2H_AP_REQ_TXRPT_GET_TX_FAIL1_1(c2h_pkt)                               \
+	GET_C2H_FIELD(c2h_pkt + 0X04, 16, 8)
+#define C2H_AP_REQ_TXRPT_SET_TX_FAIL1_1(c2h_pkt, value)                        \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X04, 16, 8, value)
+#define C2H_AP_REQ_TXRPT_SET_TX_FAIL1_1_NO_CLR(c2h_pkt, value)                 \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 16, 8, value)
+#define C2H_AP_REQ_TXRPT_GET_INITIAL_RATE1(c2h_pkt)                            \
+	GET_C2H_FIELD(c2h_pkt + 0X04, 24, 8)
+#define C2H_AP_REQ_TXRPT_SET_INITIAL_RATE1(c2h_pkt, value)                     \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X04, 24, 8, value)
+#define C2H_AP_REQ_TXRPT_SET_INITIAL_RATE1_NO_CLR(c2h_pkt, value)              \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 24, 8, value)
+#define C2H_AP_REQ_TXRPT_GET_STA2_MACID(c2h_pkt)                               \
+	GET_C2H_FIELD(c2h_pkt + 0X08, 0, 8)
+#define C2H_AP_REQ_TXRPT_SET_STA2_MACID(c2h_pkt, value)                        \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X08, 0, 8, value)
+#define C2H_AP_REQ_TXRPT_SET_STA2_MACID_NO_CLR(c2h_pkt, value)                 \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X08, 0, 8, value)
+#define C2H_AP_REQ_TXRPT_GET_TX_OK2_0(c2h_pkt)                                 \
+	GET_C2H_FIELD(c2h_pkt + 0X08, 8, 8)
+#define C2H_AP_REQ_TXRPT_SET_TX_OK2_0(c2h_pkt, value)                          \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X08, 8, 8, value)
+#define C2H_AP_REQ_TXRPT_SET_TX_OK2_0_NO_CLR(c2h_pkt, value)                   \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X08, 8, 8, value)
+#define C2H_AP_REQ_TXRPT_GET_TX_OK2_1(c2h_pkt)                                 \
+	GET_C2H_FIELD(c2h_pkt + 0X08, 16, 8)
+#define C2H_AP_REQ_TXRPT_SET_TX_OK2_1(c2h_pkt, value)                          \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X08, 16, 8, value)
+#define C2H_AP_REQ_TXRPT_SET_TX_OK2_1_NO_CLR(c2h_pkt, value)                   \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X08, 16, 8, value)
+#define C2H_AP_REQ_TXRPT_GET_TX_FAIL2_0(c2h_pkt)                               \
+	GET_C2H_FIELD(c2h_pkt + 0X08, 24, 8)
+#define C2H_AP_REQ_TXRPT_SET_TX_FAIL2_0(c2h_pkt, value)                        \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X08, 24, 8, value)
+#define C2H_AP_REQ_TXRPT_SET_TX_FAIL2_0_NO_CLR(c2h_pkt, value)                 \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X08, 24, 8, value)
+#define C2H_AP_REQ_TXRPT_GET_TX_FAIL2_1(c2h_pkt)                               \
+	GET_C2H_FIELD(c2h_pkt + 0X0C, 0, 8)
+#define C2H_AP_REQ_TXRPT_SET_TX_FAIL2_1(c2h_pkt, value)                        \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X0C, 0, 8, value)
+#define C2H_AP_REQ_TXRPT_SET_TX_FAIL2_1_NO_CLR(c2h_pkt, value)                 \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X0C, 0, 8, value)
+#define C2H_AP_REQ_TXRPT_GET_INITIAL_RATE2(c2h_pkt)                            \
+	GET_C2H_FIELD(c2h_pkt + 0X0C, 8, 8)
+#define C2H_AP_REQ_TXRPT_SET_INITIAL_RATE2(c2h_pkt, value)                     \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X0C, 8, 8, value)
+#define C2H_AP_REQ_TXRPT_SET_INITIAL_RATE2_NO_CLR(c2h_pkt, value)              \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X0C, 8, 8, value)
+#define C2H_AP_REQ_TXRPT_GET_LEN(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X0C, 16, 8)
+#define C2H_AP_REQ_TXRPT_SET_LEN(c2h_pkt, value)                               \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X0C, 16, 8, value)
+#define C2H_AP_REQ_TXRPT_SET_LEN_NO_CLR(c2h_pkt, value)                        \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X0C, 16, 8, value)
+#define C2H_AP_REQ_TXRPT_GET_TRIGGER(c2h_pkt)                                  \
+	GET_C2H_FIELD(c2h_pkt + 0X0C, 24, 8)
+#define C2H_AP_REQ_TXRPT_SET_TRIGGER(c2h_pkt, value)                           \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X0C, 24, 8, value)
+#define C2H_AP_REQ_TXRPT_SET_TRIGGER_NO_CLR(c2h_pkt, value)                    \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X0C, 24, 8, value)
+#define C2H_INITIAL_RATE_COLLECTION_GET_CMD_ID(c2h_pkt)                        \
+	GET_C2H_FIELD(c2h_pkt + 0X00, 0, 8)
+#define C2H_INITIAL_RATE_COLLECTION_SET_CMD_ID(c2h_pkt, value)                 \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 0, 8, value)
+#define C2H_INITIAL_RATE_COLLECTION_SET_CMD_ID_NO_CLR(c2h_pkt, value)          \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 0, 8, value)
+#define C2H_INITIAL_RATE_COLLECTION_GET_SEQ(c2h_pkt)                           \
+	GET_C2H_FIELD(c2h_pkt + 0X00, 8, 8)
+#define C2H_INITIAL_RATE_COLLECTION_SET_SEQ(c2h_pkt, value)                    \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 8, 8, value)
+#define C2H_INITIAL_RATE_COLLECTION_SET_SEQ_NO_CLR(c2h_pkt, value)             \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 8, 8, value)
+#define C2H_INITIAL_RATE_COLLECTION_GET_TRYING_BITMAP(c2h_pkt)                 \
+	GET_C2H_FIELD(c2h_pkt + 0X00, 16, 7)
+#define C2H_INITIAL_RATE_COLLECTION_SET_TRYING_BITMAP(c2h_pkt, value)          \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 16, 7, value)
+#define C2H_INITIAL_RATE_COLLECTION_SET_TRYING_BITMAP_NO_CLR(c2h_pkt, value)   \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 16, 7, value)
+#define C2H_INITIAL_RATE_COLLECTION_GET_INITIAL_RATE1(c2h_pkt)                 \
+	GET_C2H_FIELD(c2h_pkt + 0X00, 24, 8)
+#define C2H_INITIAL_RATE_COLLECTION_SET_INITIAL_RATE1(c2h_pkt, value)          \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 24, 8, value)
+#define C2H_INITIAL_RATE_COLLECTION_SET_INITIAL_RATE1_NO_CLR(c2h_pkt, value)   \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 24, 8, value)
+#define C2H_INITIAL_RATE_COLLECTION_GET_INITIAL_RATE2(c2h_pkt)                 \
+	GET_C2H_FIELD(c2h_pkt + 0X04, 0, 8)
+#define C2H_INITIAL_RATE_COLLECTION_SET_INITIAL_RATE2(c2h_pkt, value)          \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X04, 0, 8, value)
+#define C2H_INITIAL_RATE_COLLECTION_SET_INITIAL_RATE2_NO_CLR(c2h_pkt, value)   \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 0, 8, value)
+#define C2H_INITIAL_RATE_COLLECTION_GET_INITIAL_RATE3(c2h_pkt)                 \
+	GET_C2H_FIELD(c2h_pkt + 0X04, 8, 8)
+#define C2H_INITIAL_RATE_COLLECTION_SET_INITIAL_RATE3(c2h_pkt, value)          \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X04, 8, 8, value)
+#define C2H_INITIAL_RATE_COLLECTION_SET_INITIAL_RATE3_NO_CLR(c2h_pkt, value)   \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 8, 8, value)
+#define C2H_INITIAL_RATE_COLLECTION_GET_INITIAL_RATE4(c2h_pkt)                 \
+	GET_C2H_FIELD(c2h_pkt + 0X04, 16, 8)
+#define C2H_INITIAL_RATE_COLLECTION_SET_INITIAL_RATE4(c2h_pkt, value)          \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X04, 16, 8, value)
+#define C2H_INITIAL_RATE_COLLECTION_SET_INITIAL_RATE4_NO_CLR(c2h_pkt, value)   \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 16, 8, value)
+#define C2H_INITIAL_RATE_COLLECTION_GET_INITIAL_RATE5(c2h_pkt)                 \
+	GET_C2H_FIELD(c2h_pkt + 0X04, 24, 8)
+#define C2H_INITIAL_RATE_COLLECTION_SET_INITIAL_RATE5(c2h_pkt, value)          \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X04, 24, 8, value)
+#define C2H_INITIAL_RATE_COLLECTION_SET_INITIAL_RATE5_NO_CLR(c2h_pkt, value)   \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 24, 8, value)
+#define C2H_INITIAL_RATE_COLLECTION_GET_INITIAL_RATE6(c2h_pkt)                 \
+	GET_C2H_FIELD(c2h_pkt + 0X08, 0, 8)
+#define C2H_INITIAL_RATE_COLLECTION_SET_INITIAL_RATE6(c2h_pkt, value)          \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X08, 0, 8, value)
+#define C2H_INITIAL_RATE_COLLECTION_SET_INITIAL_RATE6_NO_CLR(c2h_pkt, value)   \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X08, 0, 8, value)
+#define C2H_INITIAL_RATE_COLLECTION_GET_INITIAL_RATE7(c2h_pkt)                 \
+	GET_C2H_FIELD(c2h_pkt + 0X08, 8, 8)
+#define C2H_INITIAL_RATE_COLLECTION_SET_INITIAL_RATE7(c2h_pkt, value)          \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X08, 8, 8, value)
+#define C2H_INITIAL_RATE_COLLECTION_SET_INITIAL_RATE7_NO_CLR(c2h_pkt, value)   \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X08, 8, 8, value)
+#define C2H_INITIAL_RATE_COLLECTION_GET_LEN(c2h_pkt)                           \
+	GET_C2H_FIELD(c2h_pkt + 0X0C, 16, 8)
+#define C2H_INITIAL_RATE_COLLECTION_SET_LEN(c2h_pkt, value)                    \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X0C, 16, 8, value)
+#define C2H_INITIAL_RATE_COLLECTION_SET_LEN_NO_CLR(c2h_pkt, value)             \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X0C, 16, 8, value)
+#define C2H_INITIAL_RATE_COLLECTION_GET_TRIGGER(c2h_pkt)                       \
+	GET_C2H_FIELD(c2h_pkt + 0X0C, 24, 8)
+#define C2H_INITIAL_RATE_COLLECTION_SET_TRIGGER(c2h_pkt, value)                \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X0C, 24, 8, value)
+#define C2H_INITIAL_RATE_COLLECTION_SET_TRIGGER_NO_CLR(c2h_pkt, value)         \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X0C, 24, 8, value)
+#define C2H_RA_RPT_GET_CMD_ID(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X00, 0, 8)
+#define C2H_RA_RPT_SET_CMD_ID(c2h_pkt, value)                                  \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 0, 8, value)
+#define C2H_RA_RPT_SET_CMD_ID_NO_CLR(c2h_pkt, value)                           \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 0, 8, value)
+#define C2H_RA_RPT_GET_SEQ(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X00, 8, 8)
+#define C2H_RA_RPT_SET_SEQ(c2h_pkt, value)                                     \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 8, 8, value)
+#define C2H_RA_RPT_SET_SEQ_NO_CLR(c2h_pkt, value)                              \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 8, 8, value)
+#define C2H_RA_RPT_GET_RATE(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X00, 16, 8)
+#define C2H_RA_RPT_SET_RATE(c2h_pkt, value)                                    \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 16, 8, value)
+#define C2H_RA_RPT_SET_RATE_NO_CLR(c2h_pkt, value)                             \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 16, 8, value)
+#define C2H_RA_RPT_GET_MACID(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X00, 24, 8)
+#define C2H_RA_RPT_SET_MACID(c2h_pkt, value)                                   \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 24, 8, value)
+#define C2H_RA_RPT_SET_MACID_NO_CLR(c2h_pkt, value)                            \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 24, 8, value)
+#define C2H_RA_RPT_GET_USE_LDPC(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X04, 0, 1)
+#define C2H_RA_RPT_SET_USE_LDPC(c2h_pkt, value)                                \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X04, 0, 1, value)
+#define C2H_RA_RPT_SET_USE_LDPC_NO_CLR(c2h_pkt, value)                         \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 0, 1, value)
+#define C2H_RA_RPT_GET_USE_TXBF(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X04, 1, 1)
+#define C2H_RA_RPT_SET_USE_TXBF(c2h_pkt, value)                                \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X04, 1, 1, value)
+#define C2H_RA_RPT_SET_USE_TXBF_NO_CLR(c2h_pkt, value)                         \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 1, 1, value)
+#define C2H_RA_RPT_GET_COLLISION_STATE(c2h_pkt)                                \
+	GET_C2H_FIELD(c2h_pkt + 0X04, 8, 8)
+#define C2H_RA_RPT_SET_COLLISION_STATE(c2h_pkt, value)                         \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X04, 8, 8, value)
+#define C2H_RA_RPT_SET_COLLISION_STATE_NO_CLR(c2h_pkt, value)                  \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 8, 8, value)
+#define C2H_RA_RPT_GET_LEN(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X0C, 16, 8)
+#define C2H_RA_RPT_SET_LEN(c2h_pkt, value)                                     \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X0C, 16, 8, value)
+#define C2H_RA_RPT_SET_LEN_NO_CLR(c2h_pkt, value)                              \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X0C, 16, 8, value)
+#define C2H_RA_RPT_GET_TRIGGER(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X0C, 24, 8)
+#define C2H_RA_RPT_SET_TRIGGER(c2h_pkt, value)                                 \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X0C, 24, 8, value)
+#define C2H_RA_RPT_SET_TRIGGER_NO_CLR(c2h_pkt, value)                          \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X0C, 24, 8, value)
+#define C2H_SPECIAL_STATISTICS_GET_CMD_ID(c2h_pkt)                             \
+	GET_C2H_FIELD(c2h_pkt + 0X00, 0, 8)
+#define C2H_SPECIAL_STATISTICS_SET_CMD_ID(c2h_pkt, value)                      \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 0, 8, value)
+#define C2H_SPECIAL_STATISTICS_SET_CMD_ID_NO_CLR(c2h_pkt, value)               \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 0, 8, value)
+#define C2H_SPECIAL_STATISTICS_GET_SEQ(c2h_pkt)                                \
+	GET_C2H_FIELD(c2h_pkt + 0X00, 8, 8)
+#define C2H_SPECIAL_STATISTICS_SET_SEQ(c2h_pkt, value)                         \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 8, 8, value)
+#define C2H_SPECIAL_STATISTICS_SET_SEQ_NO_CLR(c2h_pkt, value)                  \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 8, 8, value)
+#define C2H_SPECIAL_STATISTICS_GET_STATISTICS_IDX(c2h_pkt)                     \
+	GET_C2H_FIELD(c2h_pkt + 0X00, 16, 8)
+#define C2H_SPECIAL_STATISTICS_SET_STATISTICS_IDX(c2h_pkt, value)              \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 16, 8, value)
+#define C2H_SPECIAL_STATISTICS_SET_STATISTICS_IDX_NO_CLR(c2h_pkt, value)       \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 16, 8, value)
+#define C2H_SPECIAL_STATISTICS_GET_DATA0(c2h_pkt)                              \
+	GET_C2H_FIELD(c2h_pkt + 0X00, 24, 8)
+#define C2H_SPECIAL_STATISTICS_SET_DATA0(c2h_pkt, value)                       \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 24, 8, value)
+#define C2H_SPECIAL_STATISTICS_SET_DATA0_NO_CLR(c2h_pkt, value)                \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 24, 8, value)
+#define C2H_SPECIAL_STATISTICS_GET_DATA1(c2h_pkt)                              \
+	GET_C2H_FIELD(c2h_pkt + 0X04, 0, 8)
+#define C2H_SPECIAL_STATISTICS_SET_DATA1(c2h_pkt, value)                       \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X04, 0, 8, value)
+#define C2H_SPECIAL_STATISTICS_SET_DATA1_NO_CLR(c2h_pkt, value)                \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 0, 8, value)
+#define C2H_SPECIAL_STATISTICS_GET_DATA2(c2h_pkt)                              \
+	GET_C2H_FIELD(c2h_pkt + 0X04, 8, 8)
+#define C2H_SPECIAL_STATISTICS_SET_DATA2(c2h_pkt, value)                       \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X04, 8, 8, value)
+#define C2H_SPECIAL_STATISTICS_SET_DATA2_NO_CLR(c2h_pkt, value)                \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 8, 8, value)
+#define C2H_SPECIAL_STATISTICS_GET_DATA3(c2h_pkt)                              \
+	GET_C2H_FIELD(c2h_pkt + 0X04, 16, 8)
+#define C2H_SPECIAL_STATISTICS_SET_DATA3(c2h_pkt, value)                       \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X04, 16, 8, value)
+#define C2H_SPECIAL_STATISTICS_SET_DATA3_NO_CLR(c2h_pkt, value)                \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 16, 8, value)
+#define C2H_SPECIAL_STATISTICS_GET_DATA4(c2h_pkt)                              \
+	GET_C2H_FIELD(c2h_pkt + 0X04, 24, 8)
+#define C2H_SPECIAL_STATISTICS_SET_DATA4(c2h_pkt, value)                       \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X04, 24, 8, value)
+#define C2H_SPECIAL_STATISTICS_SET_DATA4_NO_CLR(c2h_pkt, value)                \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 24, 8, value)
+#define C2H_SPECIAL_STATISTICS_GET_DATA5(c2h_pkt)                              \
+	GET_C2H_FIELD(c2h_pkt + 0X08, 0, 8)
+#define C2H_SPECIAL_STATISTICS_SET_DATA5(c2h_pkt, value)                       \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X08, 0, 8, value)
+#define C2H_SPECIAL_STATISTICS_SET_DATA5_NO_CLR(c2h_pkt, value)                \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X08, 0, 8, value)
+#define C2H_SPECIAL_STATISTICS_GET_DATA6(c2h_pkt)                              \
+	GET_C2H_FIELD(c2h_pkt + 0X08, 8, 8)
+#define C2H_SPECIAL_STATISTICS_SET_DATA6(c2h_pkt, value)                       \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X08, 8, 8, value)
+#define C2H_SPECIAL_STATISTICS_SET_DATA6_NO_CLR(c2h_pkt, value)                \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X08, 8, 8, value)
+#define C2H_SPECIAL_STATISTICS_GET_DATA7(c2h_pkt)                              \
+	GET_C2H_FIELD(c2h_pkt + 0X08, 16, 8)
+#define C2H_SPECIAL_STATISTICS_SET_DATA7(c2h_pkt, value)                       \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X08, 16, 8, value)
+#define C2H_SPECIAL_STATISTICS_SET_DATA7_NO_CLR(c2h_pkt, value)                \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X08, 16, 8, value)
+#define C2H_SPECIAL_STATISTICS_GET_LEN(c2h_pkt)                                \
+	GET_C2H_FIELD(c2h_pkt + 0X0C, 16, 8)
+#define C2H_SPECIAL_STATISTICS_SET_LEN(c2h_pkt, value)                         \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X0C, 16, 8, value)
+#define C2H_SPECIAL_STATISTICS_SET_LEN_NO_CLR(c2h_pkt, value)                  \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X0C, 16, 8, value)
+#define C2H_SPECIAL_STATISTICS_GET_TRIGGER(c2h_pkt)                            \
+	GET_C2H_FIELD(c2h_pkt + 0X0C, 24, 8)
+#define C2H_SPECIAL_STATISTICS_SET_TRIGGER(c2h_pkt, value)                     \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X0C, 24, 8, value)
+#define C2H_SPECIAL_STATISTICS_SET_TRIGGER_NO_CLR(c2h_pkt, value)              \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X0C, 24, 8, value)
+#define C2H_RA_PARA_RPT_GET_CMD_ID(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X00, 0, 8)
+#define C2H_RA_PARA_RPT_SET_CMD_ID(c2h_pkt, value)                             \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 0, 8, value)
+#define C2H_RA_PARA_RPT_SET_CMD_ID_NO_CLR(c2h_pkt, value)                      \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 0, 8, value)
+#define C2H_RA_PARA_RPT_GET_SEQ(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X00, 8, 8)
+#define C2H_RA_PARA_RPT_SET_SEQ(c2h_pkt, value)                                \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 8, 8, value)
+#define C2H_RA_PARA_RPT_SET_SEQ_NO_CLR(c2h_pkt, value)                         \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 8, 8, value)
+#define C2H_RA_PARA_RPT_GET_LEN(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X0C, 16, 8)
+#define C2H_RA_PARA_RPT_SET_LEN(c2h_pkt, value)                                \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X0C, 16, 8, value)
+#define C2H_RA_PARA_RPT_SET_LEN_NO_CLR(c2h_pkt, value)                         \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X0C, 16, 8, value)
+#define C2H_RA_PARA_RPT_GET_TRIGGER(c2h_pkt)                                   \
+	GET_C2H_FIELD(c2h_pkt + 0X0C, 24, 8)
+#define C2H_RA_PARA_RPT_SET_TRIGGER(c2h_pkt, value)                            \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X0C, 24, 8, value)
+#define C2H_RA_PARA_RPT_SET_TRIGGER_NO_CLR(c2h_pkt, value)                     \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X0C, 24, 8, value)
+#define C2H_CUR_CHANNEL_GET_CMD_ID(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X00, 0, 8)
+#define C2H_CUR_CHANNEL_SET_CMD_ID(c2h_pkt, value)                             \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 0, 8, value)
+#define C2H_CUR_CHANNEL_SET_CMD_ID_NO_CLR(c2h_pkt, value)                      \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 0, 8, value)
+#define C2H_CUR_CHANNEL_GET_SEQ(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X00, 8, 8)
+#define C2H_CUR_CHANNEL_SET_SEQ(c2h_pkt, value)                                \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 8, 8, value)
+#define C2H_CUR_CHANNEL_SET_SEQ_NO_CLR(c2h_pkt, value)                         \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 8, 8, value)
+#define C2H_CUR_CHANNEL_GET_CHANNEL_NUM(c2h_pkt)                               \
+	GET_C2H_FIELD(c2h_pkt + 0X00, 16, 8)
+#define C2H_CUR_CHANNEL_SET_CHANNEL_NUM(c2h_pkt, value)                        \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 16, 8, value)
+#define C2H_CUR_CHANNEL_SET_CHANNEL_NUM_NO_CLR(c2h_pkt, value)                 \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 16, 8, value)
+#define C2H_CUR_CHANNEL_GET_LEN(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X0C, 16, 8)
+#define C2H_CUR_CHANNEL_SET_LEN(c2h_pkt, value)                                \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X0C, 16, 8, value)
+#define C2H_CUR_CHANNEL_SET_LEN_NO_CLR(c2h_pkt, value)                         \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X0C, 16, 8, value)
+#define C2H_CUR_CHANNEL_GET_TRIGGER(c2h_pkt)                                   \
+	GET_C2H_FIELD(c2h_pkt + 0X0C, 24, 8)
+#define C2H_CUR_CHANNEL_SET_TRIGGER(c2h_pkt, value)                            \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X0C, 24, 8, value)
+#define C2H_CUR_CHANNEL_SET_TRIGGER_NO_CLR(c2h_pkt, value)                     \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X0C, 24, 8, value)
+#define C2H_GPIO_WAKEUP_GET_CMD_ID(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X00, 0, 8)
+#define C2H_GPIO_WAKEUP_SET_CMD_ID(c2h_pkt, value)                             \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 0, 8, value)
+#define C2H_GPIO_WAKEUP_SET_CMD_ID_NO_CLR(c2h_pkt, value)                      \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 0, 8, value)
+#define C2H_GPIO_WAKEUP_GET_SEQ(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X00, 8, 8)
+#define C2H_GPIO_WAKEUP_SET_SEQ(c2h_pkt, value)                                \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 8, 8, value)
+#define C2H_GPIO_WAKEUP_SET_SEQ_NO_CLR(c2h_pkt, value)                         \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 8, 8, value)
+#define C2H_GPIO_WAKEUP_GET_LEN(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X0C, 16, 8)
+#define C2H_GPIO_WAKEUP_SET_LEN(c2h_pkt, value)                                \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X0C, 16, 8, value)
+#define C2H_GPIO_WAKEUP_SET_LEN_NO_CLR(c2h_pkt, value)                         \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X0C, 16, 8, value)
+#define C2H_GPIO_WAKEUP_GET_TRIGGER(c2h_pkt)                                   \
+	GET_C2H_FIELD(c2h_pkt + 0X0C, 24, 8)
+#define C2H_GPIO_WAKEUP_SET_TRIGGER(c2h_pkt, value)                            \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X0C, 24, 8, value)
+#define C2H_GPIO_WAKEUP_SET_TRIGGER_NO_CLR(c2h_pkt, value)                     \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X0C, 24, 8, value)
+#define C2H_DROPID_RPT_GET_CMD_ID(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X00, 0, 8)
+#define C2H_DROPID_RPT_SET_CMD_ID(c2h_pkt, value)                              \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 0, 8, value)
+#define C2H_DROPID_RPT_SET_CMD_ID_NO_CLR(c2h_pkt, value)                       \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 0, 8, value)
+#define C2H_DROPID_RPT_GET_SEQ(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X00, 8, 8)
+#define C2H_DROPID_RPT_SET_SEQ(c2h_pkt, value)                                 \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 8, 8, value)
+#define C2H_DROPID_RPT_SET_SEQ_NO_CLR(c2h_pkt, value)                          \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 8, 8, value)
+#define C2H_DROPID_RPT_GET_DROPIDBIT(c2h_pkt)                                  \
+	GET_C2H_FIELD(c2h_pkt + 0X00, 16, 4)
+#define C2H_DROPID_RPT_SET_DROPIDBIT(c2h_pkt, value)                           \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 16, 4, value)
+#define C2H_DROPID_RPT_SET_DROPIDBIT_NO_CLR(c2h_pkt, value)                    \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 16, 4, value)
+#define C2H_DROPID_RPT_GET_CURDROPID(c2h_pkt)                                  \
+	GET_C2H_FIELD(c2h_pkt + 0X00, 20, 2)
+#define C2H_DROPID_RPT_SET_CURDROPID(c2h_pkt, value)                           \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 20, 2, value)
+#define C2H_DROPID_RPT_SET_CURDROPID_NO_CLR(c2h_pkt, value)                    \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 20, 2, value)
+#define C2H_DROPID_RPT_GET_MACID(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X04, 0, 8)
+#define C2H_DROPID_RPT_SET_MACID(c2h_pkt, value)                               \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X04, 0, 8, value)
+#define C2H_DROPID_RPT_SET_MACID_NO_CLR(c2h_pkt, value)                        \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 0, 8, value)
+#define C2H_DROPID_RPT_GET_LEN(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X0C, 16, 8)
+#define C2H_DROPID_RPT_SET_LEN(c2h_pkt, value)                                 \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X0C, 16, 8, value)
+#define C2H_DROPID_RPT_SET_LEN_NO_CLR(c2h_pkt, value)                          \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X0C, 16, 8, value)
+#define C2H_DROPID_RPT_GET_TRIGGER(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X0C, 24, 8)
+#define C2H_DROPID_RPT_SET_TRIGGER(c2h_pkt, value)                             \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X0C, 24, 8, value)
+#define C2H_DROPID_RPT_SET_TRIGGER_NO_CLR(c2h_pkt, value)                      \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X0C, 24, 8, value)
+#endif
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/halmac/halmac_original_c2h_nic.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/halmac/halmac_original_c2h_nic.h
--- linux-5.6.3/3rdparty/rtl8821ce/hal/halmac/halmac_original_c2h_nic.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/halmac/halmac_original_c2h_nic.h	2020-04-10 16:35:06.812659881 +0300
@@ -0,0 +1,434 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ ******************************************************************************/
+
+#ifndef _HAL_ORIGINALC2HFORMAT_H2C_C2H_NIC_H_
+#define _HAL_ORIGINALC2HFORMAT_H2C_C2H_NIC_H_
+#define CMD_ID_C2H 0X00
+#define CMD_ID_DBG 0X00
+#define CMD_ID_C2H_LB 0X01
+#define CMD_ID_C2H_SND_TXBF 0X02
+#define CMD_ID_C2H_CCX_RPT 0X03
+#define CMD_ID_C2H_AP_REQ_TXRPT 0X04
+#define CMD_ID_C2H_INITIAL_RATE_COLLECTION 0X05
+#define CMD_ID_C2H_RA_RPT 0X0C
+#define CMD_ID_C2H_SPECIAL_STATISTICS 0X0D
+#define CMD_ID_C2H_RA_PARA_RPT 0X0E
+#define CMD_ID_C2H_CUR_CHANNEL 0X10
+#define CMD_ID_C2H_GPIO_WAKEUP 0X14
+#define CMD_ID_C2H_DROPID_RPT 0X2D
+#define C2H_GET_CMD_ID(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 0, 8)
+#define C2H_SET_CMD_ID(c2h_pkt, value)                                         \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 0, 8, value)
+#define C2H_GET_SEQ(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 8, 8)
+#define C2H_SET_SEQ(c2h_pkt, value)                                            \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 8, 8, value)
+#define DBG_GET_CMD_ID(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 0, 8)
+#define DBG_SET_CMD_ID(c2h_pkt, value)                                         \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 0, 8, value)
+#define DBG_GET_SEQ(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 8, 8)
+#define DBG_SET_SEQ(c2h_pkt, value)                                            \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 8, 8, value)
+#define DBG_GET_DBG_STR1(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 16, 8)
+#define DBG_SET_DBG_STR1(c2h_pkt, value)                                       \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 16, 8, value)
+#define DBG_GET_DBG_STR2(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 24, 8)
+#define DBG_SET_DBG_STR2(c2h_pkt, value)                                       \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 24, 8, value)
+#define DBG_GET_DBG_STR3(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 0, 8)
+#define DBG_SET_DBG_STR3(c2h_pkt, value)                                       \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 0, 8, value)
+#define DBG_GET_DBG_STR4(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 8, 8)
+#define DBG_SET_DBG_STR4(c2h_pkt, value)                                       \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 8, 8, value)
+#define DBG_GET_DBG_STR5(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 16, 8)
+#define DBG_SET_DBG_STR5(c2h_pkt, value)                                       \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 16, 8, value)
+#define DBG_GET_DBG_STR6(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 24, 8)
+#define DBG_SET_DBG_STR6(c2h_pkt, value)                                       \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 24, 8, value)
+#define DBG_GET_DBG_STR7(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X08, 0, 8)
+#define DBG_SET_DBG_STR7(c2h_pkt, value)                                       \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X08, 0, 8, value)
+#define DBG_GET_DBG_STR8(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X08, 8, 8)
+#define DBG_SET_DBG_STR8(c2h_pkt, value)                                       \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X08, 8, 8, value)
+#define DBG_GET_DBG_STR9(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X08, 16, 8)
+#define DBG_SET_DBG_STR9(c2h_pkt, value)                                       \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X08, 16, 8, value)
+#define DBG_GET_DBG_STR10(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X08, 24, 8)
+#define DBG_SET_DBG_STR10(c2h_pkt, value)                                      \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X08, 24, 8, value)
+#define DBG_GET_DBG_STR11(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X0C, 0, 8)
+#define DBG_SET_DBG_STR11(c2h_pkt, value)                                      \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X0C, 0, 8, value)
+#define DBG_GET_DBG_STR12(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X0C, 8, 8)
+#define DBG_SET_DBG_STR12(c2h_pkt, value)                                      \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X0C, 8, 8, value)
+#define DBG_GET_LEN(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X0C, 16, 8)
+#define DBG_SET_LEN(c2h_pkt, value)                                            \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X0C, 16, 8, value)
+#define DBG_GET_TRIGGER(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X0C, 24, 8)
+#define DBG_SET_TRIGGER(c2h_pkt, value)                                        \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X0C, 24, 8, value)
+#define C2H_LB_GET_CMD_ID(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 0, 8)
+#define C2H_LB_SET_CMD_ID(c2h_pkt, value)                                      \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 0, 8, value)
+#define C2H_LB_GET_SEQ(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 8, 8)
+#define C2H_LB_SET_SEQ(c2h_pkt, value)                                         \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 8, 8, value)
+#define C2H_LB_GET_PAYLOAD1(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 16, 16)
+#define C2H_LB_SET_PAYLOAD1(c2h_pkt, value)                                    \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 16, 16, value)
+#define C2H_LB_GET_PAYLOAD2(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 0, 32)
+#define C2H_LB_SET_PAYLOAD2(c2h_pkt, value)                                    \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 0, 32, value)
+#define C2H_LB_GET_LEN(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X0C, 16, 8)
+#define C2H_LB_SET_LEN(c2h_pkt, value)                                         \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X0C, 16, 8, value)
+#define C2H_LB_GET_TRIGGER(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X0C, 24, 8)
+#define C2H_LB_SET_TRIGGER(c2h_pkt, value)                                     \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X0C, 24, 8, value)
+#define C2H_SND_TXBF_GET_CMD_ID(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 0, 8)
+#define C2H_SND_TXBF_SET_CMD_ID(c2h_pkt, value)                                \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 0, 8, value)
+#define C2H_SND_TXBF_GET_SEQ(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 8, 8)
+#define C2H_SND_TXBF_SET_SEQ(c2h_pkt, value)                                   \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 8, 8, value)
+#define C2H_SND_TXBF_GET_SND_RESULT(c2h_pkt)                                   \
+	LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 16, 1)
+#define C2H_SND_TXBF_SET_SND_RESULT(c2h_pkt, value)                            \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 16, 1, value)
+#define C2H_SND_TXBF_GET_LEN(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X0C, 16, 8)
+#define C2H_SND_TXBF_SET_LEN(c2h_pkt, value)                                   \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X0C, 16, 8, value)
+#define C2H_SND_TXBF_GET_TRIGGER(c2h_pkt)                                      \
+	LE_BITS_TO_4BYTE(c2h_pkt + 0X0C, 24, 8)
+#define C2H_SND_TXBF_SET_TRIGGER(c2h_pkt, value)                               \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X0C, 24, 8, value)
+#define C2H_CCX_RPT_GET_CMD_ID(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 0, 8)
+#define C2H_CCX_RPT_SET_CMD_ID(c2h_pkt, value)                                 \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 0, 8, value)
+#define C2H_CCX_RPT_GET_SEQ(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 8, 8)
+#define C2H_CCX_RPT_SET_SEQ(c2h_pkt, value)                                    \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 8, 8, value)
+#define C2H_CCX_RPT_GET_QSEL(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 16, 5)
+#define C2H_CCX_RPT_SET_QSEL(c2h_pkt, value)                                   \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 16, 5, value)
+#define C2H_CCX_RPT_GET_BMC(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 21, 1)
+#define C2H_CCX_RPT_SET_BMC(c2h_pkt, value)                                    \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 21, 1, value)
+#define C2H_CCX_RPT_GET_LIFE_TIME_OVER(c2h_pkt)                                \
+	LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 22, 1)
+#define C2H_CCX_RPT_SET_LIFE_TIME_OVER(c2h_pkt, value)                         \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 22, 1, value)
+#define C2H_CCX_RPT_GET_RETRY_OVER(c2h_pkt)                                    \
+	LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 23, 1)
+#define C2H_CCX_RPT_SET_RETRY_OVER(c2h_pkt, value)                             \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 23, 1, value)
+#define C2H_CCX_RPT_GET_MACID(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 24, 8)
+#define C2H_CCX_RPT_SET_MACID(c2h_pkt, value)                                  \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 24, 8, value)
+#define C2H_CCX_RPT_GET_DATA_RETRY_CNT(c2h_pkt)                                \
+	LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 0, 6)
+#define C2H_CCX_RPT_SET_DATA_RETRY_CNT(c2h_pkt, value)                         \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 0, 6, value)
+#define C2H_CCX_RPT_GET_QUEUE7_0(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 8, 8)
+#define C2H_CCX_RPT_SET_QUEUE7_0(c2h_pkt, value)                               \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 8, 8, value)
+#define C2H_CCX_RPT_GET_QUEUE15_8(c2h_pkt)                                     \
+	LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 16, 8)
+#define C2H_CCX_RPT_SET_QUEUE15_8(c2h_pkt, value)                              \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 16, 8, value)
+#define C2H_CCX_RPT_GET_FINAL_DATA_RATE(c2h_pkt)                               \
+	LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 24, 8)
+#define C2H_CCX_RPT_SET_FINAL_DATA_RATE(c2h_pkt, value)                        \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 24, 8, value)
+#define C2H_CCX_RPT_GET_SW_DEFINE_0(c2h_pkt)                                   \
+	LE_BITS_TO_4BYTE(c2h_pkt + 0X08, 0, 8)
+#define C2H_CCX_RPT_SET_SW_DEFINE_0(c2h_pkt, value)                            \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X08, 0, 8, value)
+#define C2H_CCX_RPT_GET_SW_DEFINE_1(c2h_pkt)                                   \
+	LE_BITS_TO_4BYTE(c2h_pkt + 0X08, 8, 4)
+#define C2H_CCX_RPT_SET_SW_DEFINE_1(c2h_pkt, value)                            \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X08, 8, 4, value)
+#define C2H_CCX_RPT_GET_LEN(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X0C, 16, 8)
+#define C2H_CCX_RPT_SET_LEN(c2h_pkt, value)                                    \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X0C, 16, 8, value)
+#define C2H_CCX_RPT_GET_TRIGGER(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X0C, 24, 8)
+#define C2H_CCX_RPT_SET_TRIGGER(c2h_pkt, value)                                \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X0C, 24, 8, value)
+#define C2H_AP_REQ_TXRPT_GET_CMD_ID(c2h_pkt)                                   \
+	LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 0, 8)
+#define C2H_AP_REQ_TXRPT_SET_CMD_ID(c2h_pkt, value)                            \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 0, 8, value)
+#define C2H_AP_REQ_TXRPT_GET_SEQ(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 8, 8)
+#define C2H_AP_REQ_TXRPT_SET_SEQ(c2h_pkt, value)                               \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 8, 8, value)
+#define C2H_AP_REQ_TXRPT_GET_STA1_MACID(c2h_pkt)                               \
+	LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 16, 8)
+#define C2H_AP_REQ_TXRPT_SET_STA1_MACID(c2h_pkt, value)                        \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 16, 8, value)
+#define C2H_AP_REQ_TXRPT_GET_TX_OK1_0(c2h_pkt)                                 \
+	LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 24, 8)
+#define C2H_AP_REQ_TXRPT_SET_TX_OK1_0(c2h_pkt, value)                          \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 24, 8, value)
+#define C2H_AP_REQ_TXRPT_GET_TX_OK1_1(c2h_pkt)                                 \
+	LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 0, 8)
+#define C2H_AP_REQ_TXRPT_SET_TX_OK1_1(c2h_pkt, value)                          \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 0, 8, value)
+#define C2H_AP_REQ_TXRPT_GET_TX_FAIL1_0(c2h_pkt)                               \
+	LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 8, 8)
+#define C2H_AP_REQ_TXRPT_SET_TX_FAIL1_0(c2h_pkt, value)                        \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 8, 8, value)
+#define C2H_AP_REQ_TXRPT_GET_TX_FAIL1_1(c2h_pkt)                               \
+	LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 16, 8)
+#define C2H_AP_REQ_TXRPT_SET_TX_FAIL1_1(c2h_pkt, value)                        \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 16, 8, value)
+#define C2H_AP_REQ_TXRPT_GET_INITIAL_RATE1(c2h_pkt)                            \
+	LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 24, 8)
+#define C2H_AP_REQ_TXRPT_SET_INITIAL_RATE1(c2h_pkt, value)                     \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 24, 8, value)
+#define C2H_AP_REQ_TXRPT_GET_STA2_MACID(c2h_pkt)                               \
+	LE_BITS_TO_4BYTE(c2h_pkt + 0X08, 0, 8)
+#define C2H_AP_REQ_TXRPT_SET_STA2_MACID(c2h_pkt, value)                        \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X08, 0, 8, value)
+#define C2H_AP_REQ_TXRPT_GET_TX_OK2_0(c2h_pkt)                                 \
+	LE_BITS_TO_4BYTE(c2h_pkt + 0X08, 8, 8)
+#define C2H_AP_REQ_TXRPT_SET_TX_OK2_0(c2h_pkt, value)                          \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X08, 8, 8, value)
+#define C2H_AP_REQ_TXRPT_GET_TX_OK2_1(c2h_pkt)                                 \
+	LE_BITS_TO_4BYTE(c2h_pkt + 0X08, 16, 8)
+#define C2H_AP_REQ_TXRPT_SET_TX_OK2_1(c2h_pkt, value)                          \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X08, 16, 8, value)
+#define C2H_AP_REQ_TXRPT_GET_TX_FAIL2_0(c2h_pkt)                               \
+	LE_BITS_TO_4BYTE(c2h_pkt + 0X08, 24, 8)
+#define C2H_AP_REQ_TXRPT_SET_TX_FAIL2_0(c2h_pkt, value)                        \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X08, 24, 8, value)
+#define C2H_AP_REQ_TXRPT_GET_TX_FAIL2_1(c2h_pkt)                               \
+	LE_BITS_TO_4BYTE(c2h_pkt + 0X0C, 0, 8)
+#define C2H_AP_REQ_TXRPT_SET_TX_FAIL2_1(c2h_pkt, value)                        \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X0C, 0, 8, value)
+#define C2H_AP_REQ_TXRPT_GET_INITIAL_RATE2(c2h_pkt)                            \
+	LE_BITS_TO_4BYTE(c2h_pkt + 0X0C, 8, 8)
+#define C2H_AP_REQ_TXRPT_SET_INITIAL_RATE2(c2h_pkt, value)                     \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X0C, 8, 8, value)
+#define C2H_AP_REQ_TXRPT_GET_LEN(c2h_pkt)                                      \
+	LE_BITS_TO_4BYTE(c2h_pkt + 0X0C, 16, 8)
+#define C2H_AP_REQ_TXRPT_SET_LEN(c2h_pkt, value)                               \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X0C, 16, 8, value)
+#define C2H_AP_REQ_TXRPT_GET_TRIGGER(c2h_pkt)                                  \
+	LE_BITS_TO_4BYTE(c2h_pkt + 0X0C, 24, 8)
+#define C2H_AP_REQ_TXRPT_SET_TRIGGER(c2h_pkt, value)                           \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X0C, 24, 8, value)
+#define C2H_INITIAL_RATE_COLLECTION_GET_CMD_ID(c2h_pkt)                        \
+	LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 0, 8)
+#define C2H_INITIAL_RATE_COLLECTION_SET_CMD_ID(c2h_pkt, value)                 \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 0, 8, value)
+#define C2H_INITIAL_RATE_COLLECTION_GET_SEQ(c2h_pkt)                           \
+	LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 8, 8)
+#define C2H_INITIAL_RATE_COLLECTION_SET_SEQ(c2h_pkt, value)                    \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 8, 8, value)
+#define C2H_INITIAL_RATE_COLLECTION_GET_TRYING_BITMAP(c2h_pkt)                 \
+	LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 16, 7)
+#define C2H_INITIAL_RATE_COLLECTION_SET_TRYING_BITMAP(c2h_pkt, value)          \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 16, 7, value)
+#define C2H_INITIAL_RATE_COLLECTION_GET_INITIAL_RATE1(c2h_pkt)                 \
+	LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 24, 8)
+#define C2H_INITIAL_RATE_COLLECTION_SET_INITIAL_RATE1(c2h_pkt, value)          \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 24, 8, value)
+#define C2H_INITIAL_RATE_COLLECTION_GET_INITIAL_RATE2(c2h_pkt)                 \
+	LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 0, 8)
+#define C2H_INITIAL_RATE_COLLECTION_SET_INITIAL_RATE2(c2h_pkt, value)          \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 0, 8, value)
+#define C2H_INITIAL_RATE_COLLECTION_GET_INITIAL_RATE3(c2h_pkt)                 \
+	LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 8, 8)
+#define C2H_INITIAL_RATE_COLLECTION_SET_INITIAL_RATE3(c2h_pkt, value)          \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 8, 8, value)
+#define C2H_INITIAL_RATE_COLLECTION_GET_INITIAL_RATE4(c2h_pkt)                 \
+	LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 16, 8)
+#define C2H_INITIAL_RATE_COLLECTION_SET_INITIAL_RATE4(c2h_pkt, value)          \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 16, 8, value)
+#define C2H_INITIAL_RATE_COLLECTION_GET_INITIAL_RATE5(c2h_pkt)                 \
+	LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 24, 8)
+#define C2H_INITIAL_RATE_COLLECTION_SET_INITIAL_RATE5(c2h_pkt, value)          \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 24, 8, value)
+#define C2H_INITIAL_RATE_COLLECTION_GET_INITIAL_RATE6(c2h_pkt)                 \
+	LE_BITS_TO_4BYTE(c2h_pkt + 0X08, 0, 8)
+#define C2H_INITIAL_RATE_COLLECTION_SET_INITIAL_RATE6(c2h_pkt, value)          \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X08, 0, 8, value)
+#define C2H_INITIAL_RATE_COLLECTION_GET_INITIAL_RATE7(c2h_pkt)                 \
+	LE_BITS_TO_4BYTE(c2h_pkt + 0X08, 8, 8)
+#define C2H_INITIAL_RATE_COLLECTION_SET_INITIAL_RATE7(c2h_pkt, value)          \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X08, 8, 8, value)
+#define C2H_INITIAL_RATE_COLLECTION_GET_LEN(c2h_pkt)                           \
+	LE_BITS_TO_4BYTE(c2h_pkt + 0X0C, 16, 8)
+#define C2H_INITIAL_RATE_COLLECTION_SET_LEN(c2h_pkt, value)                    \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X0C, 16, 8, value)
+#define C2H_INITIAL_RATE_COLLECTION_GET_TRIGGER(c2h_pkt)                       \
+	LE_BITS_TO_4BYTE(c2h_pkt + 0X0C, 24, 8)
+#define C2H_INITIAL_RATE_COLLECTION_SET_TRIGGER(c2h_pkt, value)                \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X0C, 24, 8, value)
+#define C2H_RA_RPT_GET_CMD_ID(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 0, 8)
+#define C2H_RA_RPT_SET_CMD_ID(c2h_pkt, value)                                  \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 0, 8, value)
+#define C2H_RA_RPT_GET_SEQ(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 8, 8)
+#define C2H_RA_RPT_SET_SEQ(c2h_pkt, value)                                     \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 8, 8, value)
+#define C2H_RA_RPT_GET_RATE(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 16, 8)
+#define C2H_RA_RPT_SET_RATE(c2h_pkt, value)                                    \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 16, 8, value)
+#define C2H_RA_RPT_GET_MACID(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 24, 8)
+#define C2H_RA_RPT_SET_MACID(c2h_pkt, value)                                   \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 24, 8, value)
+#define C2H_RA_RPT_GET_USE_LDPC(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 0, 1)
+#define C2H_RA_RPT_SET_USE_LDPC(c2h_pkt, value)                                \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 0, 1, value)
+#define C2H_RA_RPT_GET_USE_TXBF(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 1, 1)
+#define C2H_RA_RPT_SET_USE_TXBF(c2h_pkt, value)                                \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 1, 1, value)
+#define C2H_RA_RPT_GET_COLLISION_STATE(c2h_pkt)                                \
+	LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 8, 8)
+#define C2H_RA_RPT_SET_COLLISION_STATE(c2h_pkt, value)                         \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 8, 8, value)
+#define C2H_RA_RPT_GET_LEN(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X0C, 16, 8)
+#define C2H_RA_RPT_SET_LEN(c2h_pkt, value)                                     \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X0C, 16, 8, value)
+#define C2H_RA_RPT_GET_TRIGGER(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X0C, 24, 8)
+#define C2H_RA_RPT_SET_TRIGGER(c2h_pkt, value)                                 \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X0C, 24, 8, value)
+#define C2H_SPECIAL_STATISTICS_GET_CMD_ID(c2h_pkt)                             \
+	LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 0, 8)
+#define C2H_SPECIAL_STATISTICS_SET_CMD_ID(c2h_pkt, value)                      \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 0, 8, value)
+#define C2H_SPECIAL_STATISTICS_GET_SEQ(c2h_pkt)                                \
+	LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 8, 8)
+#define C2H_SPECIAL_STATISTICS_SET_SEQ(c2h_pkt, value)                         \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 8, 8, value)
+#define C2H_SPECIAL_STATISTICS_GET_STATISTICS_IDX(c2h_pkt)                     \
+	LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 16, 8)
+#define C2H_SPECIAL_STATISTICS_SET_STATISTICS_IDX(c2h_pkt, value)              \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 16, 8, value)
+#define C2H_SPECIAL_STATISTICS_GET_DATA0(c2h_pkt)                              \
+	LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 24, 8)
+#define C2H_SPECIAL_STATISTICS_SET_DATA0(c2h_pkt, value)                       \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 24, 8, value)
+#define C2H_SPECIAL_STATISTICS_GET_DATA1(c2h_pkt)                              \
+	LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 0, 8)
+#define C2H_SPECIAL_STATISTICS_SET_DATA1(c2h_pkt, value)                       \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 0, 8, value)
+#define C2H_SPECIAL_STATISTICS_GET_DATA2(c2h_pkt)                              \
+	LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 8, 8)
+#define C2H_SPECIAL_STATISTICS_SET_DATA2(c2h_pkt, value)                       \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 8, 8, value)
+#define C2H_SPECIAL_STATISTICS_GET_DATA3(c2h_pkt)                              \
+	LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 16, 8)
+#define C2H_SPECIAL_STATISTICS_SET_DATA3(c2h_pkt, value)                       \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 16, 8, value)
+#define C2H_SPECIAL_STATISTICS_GET_DATA4(c2h_pkt)                              \
+	LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 24, 8)
+#define C2H_SPECIAL_STATISTICS_SET_DATA4(c2h_pkt, value)                       \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 24, 8, value)
+#define C2H_SPECIAL_STATISTICS_GET_DATA5(c2h_pkt)                              \
+	LE_BITS_TO_4BYTE(c2h_pkt + 0X08, 0, 8)
+#define C2H_SPECIAL_STATISTICS_SET_DATA5(c2h_pkt, value)                       \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X08, 0, 8, value)
+#define C2H_SPECIAL_STATISTICS_GET_DATA6(c2h_pkt)                              \
+	LE_BITS_TO_4BYTE(c2h_pkt + 0X08, 8, 8)
+#define C2H_SPECIAL_STATISTICS_SET_DATA6(c2h_pkt, value)                       \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X08, 8, 8, value)
+#define C2H_SPECIAL_STATISTICS_GET_DATA7(c2h_pkt)                              \
+	LE_BITS_TO_4BYTE(c2h_pkt + 0X08, 16, 8)
+#define C2H_SPECIAL_STATISTICS_SET_DATA7(c2h_pkt, value)                       \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X08, 16, 8, value)
+#define C2H_SPECIAL_STATISTICS_GET_LEN(c2h_pkt)                                \
+	LE_BITS_TO_4BYTE(c2h_pkt + 0X0C, 16, 8)
+#define C2H_SPECIAL_STATISTICS_SET_LEN(c2h_pkt, value)                         \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X0C, 16, 8, value)
+#define C2H_SPECIAL_STATISTICS_GET_TRIGGER(c2h_pkt)                            \
+	LE_BITS_TO_4BYTE(c2h_pkt + 0X0C, 24, 8)
+#define C2H_SPECIAL_STATISTICS_SET_TRIGGER(c2h_pkt, value)                     \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X0C, 24, 8, value)
+#define C2H_RA_PARA_RPT_GET_CMD_ID(c2h_pkt)                                    \
+	LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 0, 8)
+#define C2H_RA_PARA_RPT_SET_CMD_ID(c2h_pkt, value)                             \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 0, 8, value)
+#define C2H_RA_PARA_RPT_GET_SEQ(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 8, 8)
+#define C2H_RA_PARA_RPT_SET_SEQ(c2h_pkt, value)                                \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 8, 8, value)
+#define C2H_RA_PARA_RPT_GET_LEN(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X0C, 16, 8)
+#define C2H_RA_PARA_RPT_SET_LEN(c2h_pkt, value)                                \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X0C, 16, 8, value)
+#define C2H_RA_PARA_RPT_GET_TRIGGER(c2h_pkt)                                   \
+	LE_BITS_TO_4BYTE(c2h_pkt + 0X0C, 24, 8)
+#define C2H_RA_PARA_RPT_SET_TRIGGER(c2h_pkt, value)                            \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X0C, 24, 8, value)
+#define C2H_CUR_CHANNEL_GET_CMD_ID(c2h_pkt)                                    \
+	LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 0, 8)
+#define C2H_CUR_CHANNEL_SET_CMD_ID(c2h_pkt, value)                             \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 0, 8, value)
+#define C2H_CUR_CHANNEL_GET_SEQ(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 8, 8)
+#define C2H_CUR_CHANNEL_SET_SEQ(c2h_pkt, value)                                \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 8, 8, value)
+#define C2H_CUR_CHANNEL_GET_CHANNEL_NUM(c2h_pkt)                               \
+	LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 16, 8)
+#define C2H_CUR_CHANNEL_SET_CHANNEL_NUM(c2h_pkt, value)                        \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 16, 8, value)
+#define C2H_CUR_CHANNEL_GET_LEN(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X0C, 16, 8)
+#define C2H_CUR_CHANNEL_SET_LEN(c2h_pkt, value)                                \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X0C, 16, 8, value)
+#define C2H_CUR_CHANNEL_GET_TRIGGER(c2h_pkt)                                   \
+	LE_BITS_TO_4BYTE(c2h_pkt + 0X0C, 24, 8)
+#define C2H_CUR_CHANNEL_SET_TRIGGER(c2h_pkt, value)                            \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X0C, 24, 8, value)
+#define C2H_GPIO_WAKEUP_GET_CMD_ID(c2h_pkt)                                    \
+	LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 0, 8)
+#define C2H_GPIO_WAKEUP_SET_CMD_ID(c2h_pkt, value)                             \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 0, 8, value)
+#define C2H_GPIO_WAKEUP_GET_SEQ(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 8, 8)
+#define C2H_GPIO_WAKEUP_SET_SEQ(c2h_pkt, value)                                \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 8, 8, value)
+#define C2H_GPIO_WAKEUP_GET_LEN(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X0C, 16, 8)
+#define C2H_GPIO_WAKEUP_SET_LEN(c2h_pkt, value)                                \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X0C, 16, 8, value)
+#define C2H_GPIO_WAKEUP_GET_TRIGGER(c2h_pkt)                                   \
+	LE_BITS_TO_4BYTE(c2h_pkt + 0X0C, 24, 8)
+#define C2H_GPIO_WAKEUP_SET_TRIGGER(c2h_pkt, value)                            \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X0C, 24, 8, value)
+#define C2H_DROPID_RPT_GET_CMD_ID(c2h_pkt)                                     \
+	LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 0, 8)
+#define C2H_DROPID_RPT_SET_CMD_ID(c2h_pkt, value)                              \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 0, 8, value)
+#define C2H_DROPID_RPT_GET_SEQ(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 8, 8)
+#define C2H_DROPID_RPT_SET_SEQ(c2h_pkt, value)                                 \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 8, 8, value)
+#define C2H_DROPID_RPT_GET_DROPIDBIT(c2h_pkt)                                  \
+	LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 16, 4)
+#define C2H_DROPID_RPT_SET_DROPIDBIT(c2h_pkt, value)                           \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 16, 4, value)
+#define C2H_DROPID_RPT_GET_CURDROPID(c2h_pkt)                                  \
+	LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 20, 2)
+#define C2H_DROPID_RPT_SET_CURDROPID(c2h_pkt, value)                           \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 20, 2, value)
+#define C2H_DROPID_RPT_GET_MACID(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 0, 8)
+#define C2H_DROPID_RPT_SET_MACID(c2h_pkt, value)                               \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 0, 8, value)
+#define C2H_DROPID_RPT_GET_LEN(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X0C, 16, 8)
+#define C2H_DROPID_RPT_SET_LEN(c2h_pkt, value)                                 \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X0C, 16, 8, value)
+#define C2H_DROPID_RPT_GET_TRIGGER(c2h_pkt)                                    \
+	LE_BITS_TO_4BYTE(c2h_pkt + 0X0C, 24, 8)
+#define C2H_DROPID_RPT_SET_TRIGGER(c2h_pkt, value)                             \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X0C, 24, 8, value)
+#endif
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/halmac/halmac_original_h2c_ap.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/halmac/halmac_original_h2c_ap.h
--- linux-5.6.3/3rdparty/rtl8821ce/hal/halmac/halmac_original_h2c_ap.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/halmac/halmac_original_h2c_ap.h	2020-04-10 16:35:06.812659881 +0300
@@ -0,0 +1,1661 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ ******************************************************************************/
+
+#ifndef _HAL_ORIGINALH2CFORMAT_H2C_C2H_AP_H_
+#define _HAL_ORIGINALH2CFORMAT_H2C_C2H_AP_H_
+#define CMD_ID_ORIGINAL_H2C 0X00
+#define CMD_ID_H2C2H_LB 0X0
+#define CMD_ID_D0_SCAN_OFFLOAD_CTRL 0X06
+#define CMD_ID_RSVD_PAGE 0X0
+#define CMD_ID_MEDIA_STATUS_RPT 0X01
+#define CMD_ID_KEEP_ALIVE 0X03
+#define CMD_ID_DISCONNECT_DECISION 0X04
+#define CMD_ID_AP_OFFLOAD 0X08
+#define CMD_ID_BCN_RSVDPAGE 0X09
+#define CMD_ID_PROBE_RSP_RSVDPAGE 0X0A
+#define CMD_ID_SINGLE_CHANNELSWITCH 0X1C
+#define CMD_ID_SINGLE_CHANNELSWITCH_V2 0X1D
+#define CMD_ID_SET_PWR_MODE 0X00
+#define CMD_ID_PS_TUNING_PARA 0X01
+#define CMD_ID_PS_TUNING_PARA_II 0X02
+#define CMD_ID_PS_LPS_PARA 0X03
+#define CMD_ID_P2P_PS_OFFLOAD 0X04
+#define CMD_ID_PS_SCAN_EN 0X05
+#define CMD_ID_SAP_PS 0X06
+#define CMD_ID_INACTIVE_PS 0X07
+#define CMD_ID_MACID_CFG 0X00
+#define CMD_ID_TXBF 0X01
+#define CMD_ID_RSSI_SETTING 0X02
+#define CMD_ID_AP_REQ_TXRPT 0X03
+#define CMD_ID_INIT_RATE_COLLECTION 0X04
+#define CMD_ID_IQK_OFFLOAD 0X05
+#define CMD_ID_MACID_CFG_3SS 0X06
+#define CMD_ID_RA_PARA_ADJUST 0X07
+#define CMD_ID_WWLAN 0X00
+#define CMD_ID_REMOTE_WAKE_CTRL 0X01
+#define CMD_ID_AOAC_GLOBAL_INFO 0X02
+#define CMD_ID_AOAC_RSVD_PAGE 0X03
+#define CMD_ID_AOAC_RSVD_PAGE2 0X04
+#define CMD_ID_D0_SCAN_OFFLOAD_INFO 0X05
+#define CMD_ID_CHANNEL_SWITCH_OFFLOAD 0X07
+#define CMD_ID_AOAC_RSVD_PAGE3 0X08
+#define CMD_ID_DBG_MSG_CTRL 0X1E
+#define CLASS_ORIGINAL_H2C 0X00
+#define CLASS_H2C2H_LB 0X07
+#define CLASS_D0_SCAN_OFFLOAD_CTRL 0X04
+#define CLASS_RSVD_PAGE 0X0
+#define CLASS_MEDIA_STATUS_RPT 0X0
+#define CLASS_KEEP_ALIVE 0X0
+#define CLASS_DISCONNECT_DECISION 0X0
+#define CLASS_AP_OFFLOAD 0X0
+#define CLASS_BCN_RSVDPAGE 0X0
+#define CLASS_PROBE_RSP_RSVDPAGE 0X0
+#define CLASS_SINGLE_CHANNELSWITCH 0X0
+#define CLASS_SINGLE_CHANNELSWITCH_V2 0X0
+#define CLASS_SET_PWR_MODE 0X01
+#define CLASS_PS_TUNING_PARA 0X01
+#define CLASS_PS_TUNING_PARA_II 0X01
+#define CLASS_PS_LPS_PARA 0X01
+#define CLASS_P2P_PS_OFFLOAD 0X01
+#define CLASS_PS_SCAN_EN 0X1
+#define CLASS_SAP_PS 0X1
+#define CLASS_INACTIVE_PS 0X1
+#define CLASS_MACID_CFG 0X2
+#define CLASS_TXBF 0X2
+#define CLASS_RSSI_SETTING 0X2
+#define CLASS_AP_REQ_TXRPT 0X2
+#define CLASS_INIT_RATE_COLLECTION 0X2
+#define CLASS_IQK_OFFLOAD 0X2
+#define CLASS_MACID_CFG_3SS 0X2
+#define CLASS_RA_PARA_ADJUST 0X02
+#define CLASS_WWLAN 0X4
+#define CLASS_REMOTE_WAKE_CTRL 0X4
+#define CLASS_AOAC_GLOBAL_INFO 0X04
+#define CLASS_AOAC_RSVD_PAGE 0X04
+#define CLASS_AOAC_RSVD_PAGE2 0X04
+#define CLASS_D0_SCAN_OFFLOAD_INFO 0X04
+#define CLASS_CHANNEL_SWITCH_OFFLOAD 0X04
+#define CLASS_AOAC_RSVD_PAGE3 0X04
+#define CLASS_DBG_MSG_CTRL 0X07
+#define ORIGINAL_H2C_GET_CMD_ID(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 0, 5)
+#define ORIGINAL_H2C_SET_CMD_ID(h2c_pkt, value)                                \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 0, 5, value)
+#define ORIGINAL_H2C_SET_CMD_ID_NO_CLR(h2c_pkt, value)                         \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 0, 5, value)
+#define ORIGINAL_H2C_GET_CLASS(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 5, 3)
+#define ORIGINAL_H2C_SET_CLASS(h2c_pkt, value)                                 \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 5, 3, value)
+#define ORIGINAL_H2C_SET_CLASS_NO_CLR(h2c_pkt, value)                          \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 5, 3, value)
+#define H2C2H_LB_GET_CMD_ID(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 0, 5)
+#define H2C2H_LB_SET_CMD_ID(h2c_pkt, value)                                    \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 0, 5, value)
+#define H2C2H_LB_SET_CMD_ID_NO_CLR(h2c_pkt, value)                             \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 0, 5, value)
+#define H2C2H_LB_GET_CLASS(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 5, 3)
+#define H2C2H_LB_SET_CLASS(h2c_pkt, value)                                     \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 5, 3, value)
+#define H2C2H_LB_SET_CLASS_NO_CLR(h2c_pkt, value)                              \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 5, 3, value)
+#define H2C2H_LB_GET_SEQ(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 8, 8)
+#define H2C2H_LB_SET_SEQ(h2c_pkt, value)                                       \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 8, 8, value)
+#define H2C2H_LB_SET_SEQ_NO_CLR(h2c_pkt, value)                                \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 8, 8, value)
+#define H2C2H_LB_GET_PAYLOAD1(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 16, 16)
+#define H2C2H_LB_SET_PAYLOAD1(h2c_pkt, value)                                  \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 16, 16, value)
+#define H2C2H_LB_SET_PAYLOAD1_NO_CLR(h2c_pkt, value)                           \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 16, 16, value)
+#define H2C2H_LB_GET_PAYLOAD2(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X04, 0, 32)
+#define H2C2H_LB_SET_PAYLOAD2(h2c_pkt, value)                                  \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X04, 0, 32, value)
+#define H2C2H_LB_SET_PAYLOAD2_NO_CLR(h2c_pkt, value)                           \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 0, 32, value)
+#define D0_SCAN_OFFLOAD_CTRL_GET_CMD_ID(h2c_pkt)                               \
+	GET_H2C_FIELD(h2c_pkt + 0X00, 0, 5)
+#define D0_SCAN_OFFLOAD_CTRL_SET_CMD_ID(h2c_pkt, value)                        \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 0, 5, value)
+#define D0_SCAN_OFFLOAD_CTRL_SET_CMD_ID_NO_CLR(h2c_pkt, value)                 \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 0, 5, value)
+#define D0_SCAN_OFFLOAD_CTRL_GET_CLASS(h2c_pkt)                                \
+	GET_H2C_FIELD(h2c_pkt + 0X00, 5, 3)
+#define D0_SCAN_OFFLOAD_CTRL_SET_CLASS(h2c_pkt, value)                         \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 5, 3, value)
+#define D0_SCAN_OFFLOAD_CTRL_SET_CLASS_NO_CLR(h2c_pkt, value)                  \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 5, 3, value)
+#define D0_SCAN_OFFLOAD_CTRL_GET_D0_SCAN_FUN_EN(h2c_pkt)                       \
+	GET_H2C_FIELD(h2c_pkt + 0X00, 8, 1)
+#define D0_SCAN_OFFLOAD_CTRL_SET_D0_SCAN_FUN_EN(h2c_pkt, value)                \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 8, 1, value)
+#define D0_SCAN_OFFLOAD_CTRL_SET_D0_SCAN_FUN_EN_NO_CLR(h2c_pkt, value)         \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 8, 1, value)
+#define D0_SCAN_OFFLOAD_CTRL_GET_RTD3FUN_EN(h2c_pkt)                           \
+	GET_H2C_FIELD(h2c_pkt + 0X00, 9, 1)
+#define D0_SCAN_OFFLOAD_CTRL_SET_RTD3FUN_EN(h2c_pkt, value)                    \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 9, 1, value)
+#define D0_SCAN_OFFLOAD_CTRL_SET_RTD3FUN_EN_NO_CLR(h2c_pkt, value)             \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 9, 1, value)
+#define D0_SCAN_OFFLOAD_CTRL_GET_U3_SCAN_FUN_EN(h2c_pkt)                       \
+	GET_H2C_FIELD(h2c_pkt + 0X00, 10, 1)
+#define D0_SCAN_OFFLOAD_CTRL_SET_U3_SCAN_FUN_EN(h2c_pkt, value)                \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 10, 1, value)
+#define D0_SCAN_OFFLOAD_CTRL_SET_U3_SCAN_FUN_EN_NO_CLR(h2c_pkt, value)         \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 10, 1, value)
+#define D0_SCAN_OFFLOAD_CTRL_GET_NLO_FUN_EN(h2c_pkt)                           \
+	GET_H2C_FIELD(h2c_pkt + 0X00, 11, 1)
+#define D0_SCAN_OFFLOAD_CTRL_SET_NLO_FUN_EN(h2c_pkt, value)                    \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 11, 1, value)
+#define D0_SCAN_OFFLOAD_CTRL_SET_NLO_FUN_EN_NO_CLR(h2c_pkt, value)             \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 11, 1, value)
+#define D0_SCAN_OFFLOAD_CTRL_GET_IPS_DEPENDENT(h2c_pkt)                        \
+	GET_H2C_FIELD(h2c_pkt + 0X00, 12, 1)
+#define D0_SCAN_OFFLOAD_CTRL_SET_IPS_DEPENDENT(h2c_pkt, value)                 \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 12, 1, value)
+#define D0_SCAN_OFFLOAD_CTRL_SET_IPS_DEPENDENT_NO_CLR(h2c_pkt, value)          \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 12, 1, value)
+#define D0_SCAN_OFFLOAD_CTRL_GET_LOC_PROBE_PACKET(h2c_pkt)                     \
+	GET_H2C_FIELD(h2c_pkt + 0X00, 16, 17)
+#define D0_SCAN_OFFLOAD_CTRL_SET_LOC_PROBE_PACKET(h2c_pkt, value)              \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 16, 17, value)
+#define D0_SCAN_OFFLOAD_CTRL_SET_LOC_PROBE_PACKET_NO_CLR(h2c_pkt, value)       \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 16, 17, value)
+#define D0_SCAN_OFFLOAD_CTRL_GET_LOC_SCAN_INFO(h2c_pkt)                        \
+	GET_H2C_FIELD(h2c_pkt + 0X00, 24, 8)
+#define D0_SCAN_OFFLOAD_CTRL_SET_LOC_SCAN_INFO(h2c_pkt, value)                 \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 24, 8, value)
+#define D0_SCAN_OFFLOAD_CTRL_SET_LOC_SCAN_INFO_NO_CLR(h2c_pkt, value)          \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 24, 8, value)
+#define D0_SCAN_OFFLOAD_CTRL_GET_LOC_SSID_INFO(h2c_pkt)                        \
+	GET_H2C_FIELD(h2c_pkt + 0X04, 0, 8)
+#define D0_SCAN_OFFLOAD_CTRL_SET_LOC_SSID_INFO(h2c_pkt, value)                 \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X04, 0, 8, value)
+#define D0_SCAN_OFFLOAD_CTRL_SET_LOC_SSID_INFO_NO_CLR(h2c_pkt, value)          \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 0, 8, value)
+#define RSVD_PAGE_GET_CMD_ID(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 0, 5)
+#define RSVD_PAGE_SET_CMD_ID(h2c_pkt, value)                                   \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 0, 5, value)
+#define RSVD_PAGE_SET_CMD_ID_NO_CLR(h2c_pkt, value)                            \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 0, 5, value)
+#define RSVD_PAGE_GET_CLASS(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 5, 3)
+#define RSVD_PAGE_SET_CLASS(h2c_pkt, value)                                    \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 5, 3, value)
+#define RSVD_PAGE_SET_CLASS_NO_CLR(h2c_pkt, value)                             \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 5, 3, value)
+#define RSVD_PAGE_GET_LOC_PROBE_RSP(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 8, 8)
+#define RSVD_PAGE_SET_LOC_PROBE_RSP(h2c_pkt, value)                            \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 8, 8, value)
+#define RSVD_PAGE_SET_LOC_PROBE_RSP_NO_CLR(h2c_pkt, value)                     \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 8, 8, value)
+#define RSVD_PAGE_GET_LOC_PS_POLL(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 16, 8)
+#define RSVD_PAGE_SET_LOC_PS_POLL(h2c_pkt, value)                              \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 16, 8, value)
+#define RSVD_PAGE_SET_LOC_PS_POLL_NO_CLR(h2c_pkt, value)                       \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 16, 8, value)
+#define RSVD_PAGE_GET_LOC_NULL_DATA(h2c_pkt)                                   \
+	GET_H2C_FIELD(h2c_pkt + 0X00, 24, 8)
+#define RSVD_PAGE_SET_LOC_NULL_DATA(h2c_pkt, value)                            \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 24, 8, value)
+#define RSVD_PAGE_SET_LOC_NULL_DATA_NO_CLR(h2c_pkt, value)                     \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 24, 8, value)
+#define RSVD_PAGE_GET_LOC_QOS_NULL(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X04, 0, 8)
+#define RSVD_PAGE_SET_LOC_QOS_NULL(h2c_pkt, value)                             \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X04, 0, 8, value)
+#define RSVD_PAGE_SET_LOC_QOS_NULL_NO_CLR(h2c_pkt, value)                      \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 0, 8, value)
+#define RSVD_PAGE_GET_LOC_BT_QOS_NULL(h2c_pkt)                                 \
+	GET_H2C_FIELD(h2c_pkt + 0X04, 8, 8)
+#define RSVD_PAGE_SET_LOC_BT_QOS_NULL(h2c_pkt, value)                          \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X04, 8, 8, value)
+#define RSVD_PAGE_SET_LOC_BT_QOS_NULL_NO_CLR(h2c_pkt, value)                   \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 8, 8, value)
+#define RSVD_PAGE_GET_LOC_CTS2SELF(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X04, 16, 8)
+#define RSVD_PAGE_SET_LOC_CTS2SELF(h2c_pkt, value)                             \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X04, 16, 8, value)
+#define RSVD_PAGE_SET_LOC_CTS2SELF_NO_CLR(h2c_pkt, value)                      \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 16, 8, value)
+#define RSVD_PAGE_GET_LOC_LTECOEX_QOSNULL(h2c_pkt)                             \
+	GET_H2C_FIELD(h2c_pkt + 0X04, 24, 8)
+#define RSVD_PAGE_SET_LOC_LTECOEX_QOSNULL(h2c_pkt, value)                      \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X04, 24, 8, value)
+#define RSVD_PAGE_SET_LOC_LTECOEX_QOSNULL_NO_CLR(h2c_pkt, value)               \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 24, 8, value)
+#define MEDIA_STATUS_RPT_GET_CMD_ID(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 0, 5)
+#define MEDIA_STATUS_RPT_SET_CMD_ID(h2c_pkt, value)                            \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 0, 5, value)
+#define MEDIA_STATUS_RPT_SET_CMD_ID_NO_CLR(h2c_pkt, value)                     \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 0, 5, value)
+#define MEDIA_STATUS_RPT_GET_CLASS(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 5, 3)
+#define MEDIA_STATUS_RPT_SET_CLASS(h2c_pkt, value)                             \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 5, 3, value)
+#define MEDIA_STATUS_RPT_SET_CLASS_NO_CLR(h2c_pkt, value)                      \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 5, 3, value)
+#define MEDIA_STATUS_RPT_GET_OP_MODE(h2c_pkt)                                  \
+	GET_H2C_FIELD(h2c_pkt + 0X00, 8, 1)
+#define MEDIA_STATUS_RPT_SET_OP_MODE(h2c_pkt, value)                           \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 8, 1, value)
+#define MEDIA_STATUS_RPT_SET_OP_MODE_NO_CLR(h2c_pkt, value)                    \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 8, 1, value)
+#define MEDIA_STATUS_RPT_GET_MACID_IN(h2c_pkt)                                 \
+	GET_H2C_FIELD(h2c_pkt + 0X00, 9, 1)
+#define MEDIA_STATUS_RPT_SET_MACID_IN(h2c_pkt, value)                          \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 9, 1, value)
+#define MEDIA_STATUS_RPT_SET_MACID_IN_NO_CLR(h2c_pkt, value)                   \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 9, 1, value)
+#define MEDIA_STATUS_RPT_GET_MACID(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 16, 8)
+#define MEDIA_STATUS_RPT_SET_MACID(h2c_pkt, value)                             \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 16, 8, value)
+#define MEDIA_STATUS_RPT_SET_MACID_NO_CLR(h2c_pkt, value)                      \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 16, 8, value)
+#define MEDIA_STATUS_RPT_GET_MACID_END(h2c_pkt)                                \
+	GET_H2C_FIELD(h2c_pkt + 0X00, 24, 8)
+#define MEDIA_STATUS_RPT_SET_MACID_END(h2c_pkt, value)                         \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 24, 8, value)
+#define MEDIA_STATUS_RPT_SET_MACID_END_NO_CLR(h2c_pkt, value)                  \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 24, 8, value)
+#define KEEP_ALIVE_GET_CMD_ID(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 0, 5)
+#define KEEP_ALIVE_SET_CMD_ID(h2c_pkt, value)                                  \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 0, 5, value)
+#define KEEP_ALIVE_SET_CMD_ID_NO_CLR(h2c_pkt, value)                           \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 0, 5, value)
+#define KEEP_ALIVE_GET_CLASS(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 5, 3)
+#define KEEP_ALIVE_SET_CLASS(h2c_pkt, value)                                   \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 5, 3, value)
+#define KEEP_ALIVE_SET_CLASS_NO_CLR(h2c_pkt, value)                            \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 5, 3, value)
+#define KEEP_ALIVE_GET_ENABLE(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 8, 1)
+#define KEEP_ALIVE_SET_ENABLE(h2c_pkt, value)                                  \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 8, 1, value)
+#define KEEP_ALIVE_SET_ENABLE_NO_CLR(h2c_pkt, value)                           \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 8, 1, value)
+#define KEEP_ALIVE_GET_ADOPT_USER_SETTING(h2c_pkt)                             \
+	GET_H2C_FIELD(h2c_pkt + 0X00, 9, 1)
+#define KEEP_ALIVE_SET_ADOPT_USER_SETTING(h2c_pkt, value)                      \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 9, 1, value)
+#define KEEP_ALIVE_SET_ADOPT_USER_SETTING_NO_CLR(h2c_pkt, value)               \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 9, 1, value)
+#define KEEP_ALIVE_GET_PKT_TYPE(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 10, 1)
+#define KEEP_ALIVE_SET_PKT_TYPE(h2c_pkt, value)                                \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 10, 1, value)
+#define KEEP_ALIVE_SET_PKT_TYPE_NO_CLR(h2c_pkt, value)                         \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 10, 1, value)
+#define KEEP_ALIVE_GET_KEEP_ALIVE_CHECK_PERIOD(h2c_pkt)                        \
+	GET_H2C_FIELD(h2c_pkt + 0X00, 16, 8)
+#define KEEP_ALIVE_SET_KEEP_ALIVE_CHECK_PERIOD(h2c_pkt, value)                 \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 16, 8, value)
+#define KEEP_ALIVE_SET_KEEP_ALIVE_CHECK_PERIOD_NO_CLR(h2c_pkt, value)          \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 16, 8, value)
+#define DISCONNECT_DECISION_GET_CMD_ID(h2c_pkt)                                \
+	GET_H2C_FIELD(h2c_pkt + 0X00, 0, 5)
+#define DISCONNECT_DECISION_SET_CMD_ID(h2c_pkt, value)                         \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 0, 5, value)
+#define DISCONNECT_DECISION_SET_CMD_ID_NO_CLR(h2c_pkt, value)                  \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 0, 5, value)
+#define DISCONNECT_DECISION_GET_CLASS(h2c_pkt)                                 \
+	GET_H2C_FIELD(h2c_pkt + 0X00, 5, 3)
+#define DISCONNECT_DECISION_SET_CLASS(h2c_pkt, value)                          \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 5, 3, value)
+#define DISCONNECT_DECISION_SET_CLASS_NO_CLR(h2c_pkt, value)                   \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 5, 3, value)
+#define DISCONNECT_DECISION_GET_ENABLE(h2c_pkt)                                \
+	GET_H2C_FIELD(h2c_pkt + 0X00, 8, 1)
+#define DISCONNECT_DECISION_SET_ENABLE(h2c_pkt, value)                         \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 8, 1, value)
+#define DISCONNECT_DECISION_SET_ENABLE_NO_CLR(h2c_pkt, value)                  \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 8, 1, value)
+#define DISCONNECT_DECISION_GET_ADOPT_USER_SETTING(h2c_pkt)                    \
+	GET_H2C_FIELD(h2c_pkt + 0X00, 9, 1)
+#define DISCONNECT_DECISION_SET_ADOPT_USER_SETTING(h2c_pkt, value)             \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 9, 1, value)
+#define DISCONNECT_DECISION_SET_ADOPT_USER_SETTING_NO_CLR(h2c_pkt, value)      \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 9, 1, value)
+#define DISCONNECT_DECISION_GET_TRY_OK_BCN_FAIL_COUNT_EN(h2c_pkt)              \
+	GET_H2C_FIELD(h2c_pkt + 0X00, 10, 1)
+#define DISCONNECT_DECISION_SET_TRY_OK_BCN_FAIL_COUNT_EN(h2c_pkt, value)       \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 10, 1, value)
+#define DISCONNECT_DECISION_SET_TRY_OK_BCN_FAIL_COUNT_EN_NO_CLR(h2c_pkt,       \
+								value)         \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 10, 1, value)
+#define DISCONNECT_DECISION_GET_DISCONNECT_EN(h2c_pkt)                         \
+	GET_H2C_FIELD(h2c_pkt + 0X00, 11, 1)
+#define DISCONNECT_DECISION_SET_DISCONNECT_EN(h2c_pkt, value)                  \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 11, 1, value)
+#define DISCONNECT_DECISION_SET_DISCONNECT_EN_NO_CLR(h2c_pkt, value)           \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 11, 1, value)
+#define DISCONNECT_DECISION_GET_DISCON_DECISION_CHECK_PERIOD(h2c_pkt)          \
+	GET_H2C_FIELD(h2c_pkt + 0X00, 16, 8)
+#define DISCONNECT_DECISION_SET_DISCON_DECISION_CHECK_PERIOD(h2c_pkt, value)   \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 16, 8, value)
+#define DISCONNECT_DECISION_SET_DISCON_DECISION_CHECK_PERIOD_NO_CLR(h2c_pkt,   \
+								    value)     \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 16, 8, value)
+#define DISCONNECT_DECISION_GET_TRY_PKT_NUM(h2c_pkt)                           \
+	GET_H2C_FIELD(h2c_pkt + 0X00, 24, 8)
+#define DISCONNECT_DECISION_SET_TRY_PKT_NUM(h2c_pkt, value)                    \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 24, 8, value)
+#define DISCONNECT_DECISION_SET_TRY_PKT_NUM_NO_CLR(h2c_pkt, value)             \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 24, 8, value)
+#define DISCONNECT_DECISION_GET_TRY_OK_BCN_FAIL_COUNT_LIMIT(h2c_pkt)           \
+	GET_H2C_FIELD(h2c_pkt + 0X04, 0, 8)
+#define DISCONNECT_DECISION_SET_TRY_OK_BCN_FAIL_COUNT_LIMIT(h2c_pkt, value)    \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X04, 0, 8, value)
+#define DISCONNECT_DECISION_SET_TRY_OK_BCN_FAIL_COUNT_LIMIT_NO_CLR(h2c_pkt,    \
+								   value)      \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 0, 8, value)
+#define AP_OFFLOAD_GET_CMD_ID(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 0, 5)
+#define AP_OFFLOAD_SET_CMD_ID(h2c_pkt, value)                                  \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 0, 5, value)
+#define AP_OFFLOAD_SET_CMD_ID_NO_CLR(h2c_pkt, value)                           \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 0, 5, value)
+#define AP_OFFLOAD_GET_CLASS(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 5, 3)
+#define AP_OFFLOAD_SET_CLASS(h2c_pkt, value)                                   \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 5, 3, value)
+#define AP_OFFLOAD_SET_CLASS_NO_CLR(h2c_pkt, value)                            \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 5, 3, value)
+#define AP_OFFLOAD_GET_ON(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 8, 1)
+#define AP_OFFLOAD_SET_ON(h2c_pkt, value)                                      \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 8, 1, value)
+#define AP_OFFLOAD_SET_ON_NO_CLR(h2c_pkt, value)                               \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 8, 1, value)
+#define AP_OFFLOAD_GET_CFG_MIFI_PLATFORM(h2c_pkt)                              \
+	GET_H2C_FIELD(h2c_pkt + 0X00, 9, 1)
+#define AP_OFFLOAD_SET_CFG_MIFI_PLATFORM(h2c_pkt, value)                       \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 9, 1, value)
+#define AP_OFFLOAD_SET_CFG_MIFI_PLATFORM_NO_CLR(h2c_pkt, value)                \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 9, 1, value)
+#define AP_OFFLOAD_GET_LINKED(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 10, 1)
+#define AP_OFFLOAD_SET_LINKED(h2c_pkt, value)                                  \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 10, 1, value)
+#define AP_OFFLOAD_SET_LINKED_NO_CLR(h2c_pkt, value)                           \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 10, 1, value)
+#define AP_OFFLOAD_GET_EN_AUTO_WAKE(h2c_pkt)                                   \
+	GET_H2C_FIELD(h2c_pkt + 0X00, 11, 1)
+#define AP_OFFLOAD_SET_EN_AUTO_WAKE(h2c_pkt, value)                            \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 11, 1, value)
+#define AP_OFFLOAD_SET_EN_AUTO_WAKE_NO_CLR(h2c_pkt, value)                     \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 11, 1, value)
+#define AP_OFFLOAD_GET_WAKE_FLAG(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 12, 1)
+#define AP_OFFLOAD_SET_WAKE_FLAG(h2c_pkt, value)                               \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 12, 1, value)
+#define AP_OFFLOAD_SET_WAKE_FLAG_NO_CLR(h2c_pkt, value)                        \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 12, 1, value)
+#define AP_OFFLOAD_GET_HIDDEN_ROOT(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 16, 1)
+#define AP_OFFLOAD_SET_HIDDEN_ROOT(h2c_pkt, value)                             \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 16, 1, value)
+#define AP_OFFLOAD_SET_HIDDEN_ROOT_NO_CLR(h2c_pkt, value)                      \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 16, 1, value)
+#define AP_OFFLOAD_GET_HIDDEN_VAP1(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 17, 1)
+#define AP_OFFLOAD_SET_HIDDEN_VAP1(h2c_pkt, value)                             \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 17, 1, value)
+#define AP_OFFLOAD_SET_HIDDEN_VAP1_NO_CLR(h2c_pkt, value)                      \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 17, 1, value)
+#define AP_OFFLOAD_GET_HIDDEN_VAP2(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 18, 1)
+#define AP_OFFLOAD_SET_HIDDEN_VAP2(h2c_pkt, value)                             \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 18, 1, value)
+#define AP_OFFLOAD_SET_HIDDEN_VAP2_NO_CLR(h2c_pkt, value)                      \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 18, 1, value)
+#define AP_OFFLOAD_GET_HIDDEN_VAP3(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 19, 1)
+#define AP_OFFLOAD_SET_HIDDEN_VAP3(h2c_pkt, value)                             \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 19, 1, value)
+#define AP_OFFLOAD_SET_HIDDEN_VAP3_NO_CLR(h2c_pkt, value)                      \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 19, 1, value)
+#define AP_OFFLOAD_GET_HIDDEN_VAP4(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 20, 1)
+#define AP_OFFLOAD_SET_HIDDEN_VAP4(h2c_pkt, value)                             \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 20, 1, value)
+#define AP_OFFLOAD_SET_HIDDEN_VAP4_NO_CLR(h2c_pkt, value)                      \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 20, 1, value)
+#define AP_OFFLOAD_GET_DENYANY_ROOT(h2c_pkt)                                   \
+	GET_H2C_FIELD(h2c_pkt + 0X00, 24, 1)
+#define AP_OFFLOAD_SET_DENYANY_ROOT(h2c_pkt, value)                            \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 24, 1, value)
+#define AP_OFFLOAD_SET_DENYANY_ROOT_NO_CLR(h2c_pkt, value)                     \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 24, 1, value)
+#define AP_OFFLOAD_GET_DENYANY_VAP1(h2c_pkt)                                   \
+	GET_H2C_FIELD(h2c_pkt + 0X00, 25, 1)
+#define AP_OFFLOAD_SET_DENYANY_VAP1(h2c_pkt, value)                            \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 25, 1, value)
+#define AP_OFFLOAD_SET_DENYANY_VAP1_NO_CLR(h2c_pkt, value)                     \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 25, 1, value)
+#define AP_OFFLOAD_GET_DENYANY_VAP2(h2c_pkt)                                   \
+	GET_H2C_FIELD(h2c_pkt + 0X00, 26, 1)
+#define AP_OFFLOAD_SET_DENYANY_VAP2(h2c_pkt, value)                            \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 26, 1, value)
+#define AP_OFFLOAD_SET_DENYANY_VAP2_NO_CLR(h2c_pkt, value)                     \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 26, 1, value)
+#define AP_OFFLOAD_GET_DENYANY_VAP3(h2c_pkt)                                   \
+	GET_H2C_FIELD(h2c_pkt + 0X00, 27, 1)
+#define AP_OFFLOAD_SET_DENYANY_VAP3(h2c_pkt, value)                            \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 27, 1, value)
+#define AP_OFFLOAD_SET_DENYANY_VAP3_NO_CLR(h2c_pkt, value)                     \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 27, 1, value)
+#define AP_OFFLOAD_GET_DENYANY_VAP4(h2c_pkt)                                   \
+	GET_H2C_FIELD(h2c_pkt + 0X00, 28, 1)
+#define AP_OFFLOAD_SET_DENYANY_VAP4(h2c_pkt, value)                            \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 28, 1, value)
+#define AP_OFFLOAD_SET_DENYANY_VAP4_NO_CLR(h2c_pkt, value)                     \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 28, 1, value)
+#define AP_OFFLOAD_GET_WAIT_TBTT_CNT(h2c_pkt)                                  \
+	GET_H2C_FIELD(h2c_pkt + 0X04, 0, 8)
+#define AP_OFFLOAD_SET_WAIT_TBTT_CNT(h2c_pkt, value)                           \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X04, 0, 8, value)
+#define AP_OFFLOAD_SET_WAIT_TBTT_CNT_NO_CLR(h2c_pkt, value)                    \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 0, 8, value)
+#define AP_OFFLOAD_GET_WAKE_TIMEOUT(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X04, 8, 8)
+#define AP_OFFLOAD_SET_WAKE_TIMEOUT(h2c_pkt, value)                            \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X04, 8, 8, value)
+#define AP_OFFLOAD_SET_WAKE_TIMEOUT_NO_CLR(h2c_pkt, value)                     \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 8, 8, value)
+#define AP_OFFLOAD_GET_LEN_IV_PAIR(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X04, 16, 8)
+#define AP_OFFLOAD_SET_LEN_IV_PAIR(h2c_pkt, value)                             \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X04, 16, 8, value)
+#define AP_OFFLOAD_SET_LEN_IV_PAIR_NO_CLR(h2c_pkt, value)                      \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 16, 8, value)
+#define AP_OFFLOAD_GET_LEN_IV_GRP(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X04, 24, 8)
+#define AP_OFFLOAD_SET_LEN_IV_GRP(h2c_pkt, value)                              \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X04, 24, 8, value)
+#define AP_OFFLOAD_SET_LEN_IV_GRP_NO_CLR(h2c_pkt, value)                       \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 24, 8, value)
+#define BCN_RSVDPAGE_GET_CMD_ID(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 0, 5)
+#define BCN_RSVDPAGE_SET_CMD_ID(h2c_pkt, value)                                \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 0, 5, value)
+#define BCN_RSVDPAGE_SET_CMD_ID_NO_CLR(h2c_pkt, value)                         \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 0, 5, value)
+#define BCN_RSVDPAGE_GET_CLASS(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 5, 3)
+#define BCN_RSVDPAGE_SET_CLASS(h2c_pkt, value)                                 \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 5, 3, value)
+#define BCN_RSVDPAGE_SET_CLASS_NO_CLR(h2c_pkt, value)                          \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 5, 3, value)
+#define BCN_RSVDPAGE_GET_LOC_ROOT(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 8, 8)
+#define BCN_RSVDPAGE_SET_LOC_ROOT(h2c_pkt, value)                              \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 8, 8, value)
+#define BCN_RSVDPAGE_SET_LOC_ROOT_NO_CLR(h2c_pkt, value)                       \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 8, 8, value)
+#define BCN_RSVDPAGE_GET_LOC_VAP1(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 16, 8)
+#define BCN_RSVDPAGE_SET_LOC_VAP1(h2c_pkt, value)                              \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 16, 8, value)
+#define BCN_RSVDPAGE_SET_LOC_VAP1_NO_CLR(h2c_pkt, value)                       \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 16, 8, value)
+#define BCN_RSVDPAGE_GET_LOC_VAP2(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 24, 8)
+#define BCN_RSVDPAGE_SET_LOC_VAP2(h2c_pkt, value)                              \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 24, 8, value)
+#define BCN_RSVDPAGE_SET_LOC_VAP2_NO_CLR(h2c_pkt, value)                       \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 24, 8, value)
+#define BCN_RSVDPAGE_GET_LOC_VAP3(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X04, 0, 8)
+#define BCN_RSVDPAGE_SET_LOC_VAP3(h2c_pkt, value)                              \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X04, 0, 8, value)
+#define BCN_RSVDPAGE_SET_LOC_VAP3_NO_CLR(h2c_pkt, value)                       \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 0, 8, value)
+#define BCN_RSVDPAGE_GET_LOC_VAP4(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X04, 8, 8)
+#define BCN_RSVDPAGE_SET_LOC_VAP4(h2c_pkt, value)                              \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X04, 8, 8, value)
+#define BCN_RSVDPAGE_SET_LOC_VAP4_NO_CLR(h2c_pkt, value)                       \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 8, 8, value)
+#define PROBE_RSP_RSVDPAGE_GET_CMD_ID(h2c_pkt)                                 \
+	GET_H2C_FIELD(h2c_pkt + 0X00, 0, 5)
+#define PROBE_RSP_RSVDPAGE_SET_CMD_ID(h2c_pkt, value)                          \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 0, 5, value)
+#define PROBE_RSP_RSVDPAGE_SET_CMD_ID_NO_CLR(h2c_pkt, value)                   \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 0, 5, value)
+#define PROBE_RSP_RSVDPAGE_GET_CLASS(h2c_pkt)                                  \
+	GET_H2C_FIELD(h2c_pkt + 0X00, 5, 3)
+#define PROBE_RSP_RSVDPAGE_SET_CLASS(h2c_pkt, value)                           \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 5, 3, value)
+#define PROBE_RSP_RSVDPAGE_SET_CLASS_NO_CLR(h2c_pkt, value)                    \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 5, 3, value)
+#define PROBE_RSP_RSVDPAGE_GET_LOC_ROOT(h2c_pkt)                               \
+	GET_H2C_FIELD(h2c_pkt + 0X00, 8, 8)
+#define PROBE_RSP_RSVDPAGE_SET_LOC_ROOT(h2c_pkt, value)                        \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 8, 8, value)
+#define PROBE_RSP_RSVDPAGE_SET_LOC_ROOT_NO_CLR(h2c_pkt, value)                 \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 8, 8, value)
+#define PROBE_RSP_RSVDPAGE_GET_LOC_VAP1(h2c_pkt)                               \
+	GET_H2C_FIELD(h2c_pkt + 0X00, 16, 8)
+#define PROBE_RSP_RSVDPAGE_SET_LOC_VAP1(h2c_pkt, value)                        \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 16, 8, value)
+#define PROBE_RSP_RSVDPAGE_SET_LOC_VAP1_NO_CLR(h2c_pkt, value)                 \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 16, 8, value)
+#define PROBE_RSP_RSVDPAGE_GET_LOC_VAP2(h2c_pkt)                               \
+	GET_H2C_FIELD(h2c_pkt + 0X00, 24, 8)
+#define PROBE_RSP_RSVDPAGE_SET_LOC_VAP2(h2c_pkt, value)                        \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 24, 8, value)
+#define PROBE_RSP_RSVDPAGE_SET_LOC_VAP2_NO_CLR(h2c_pkt, value)                 \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 24, 8, value)
+#define PROBE_RSP_RSVDPAGE_GET_LOC_VAP3(h2c_pkt)                               \
+	GET_H2C_FIELD(h2c_pkt + 0X04, 0, 8)
+#define PROBE_RSP_RSVDPAGE_SET_LOC_VAP3(h2c_pkt, value)                        \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X04, 0, 8, value)
+#define PROBE_RSP_RSVDPAGE_SET_LOC_VAP3_NO_CLR(h2c_pkt, value)                 \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 0, 8, value)
+#define PROBE_RSP_RSVDPAGE_GET_LOC_VAP4(h2c_pkt)                               \
+	GET_H2C_FIELD(h2c_pkt + 0X04, 8, 8)
+#define PROBE_RSP_RSVDPAGE_SET_LOC_VAP4(h2c_pkt, value)                        \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X04, 8, 8, value)
+#define PROBE_RSP_RSVDPAGE_SET_LOC_VAP4_NO_CLR(h2c_pkt, value)                 \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 8, 8, value)
+#define SINGLE_CHANNELSWITCH_GET_CMD_ID(h2c_pkt)                               \
+	GET_H2C_FIELD(h2c_pkt + 0X00, 0, 5)
+#define SINGLE_CHANNELSWITCH_SET_CMD_ID(h2c_pkt, value)                        \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 0, 5, value)
+#define SINGLE_CHANNELSWITCH_SET_CMD_ID_NO_CLR(h2c_pkt, value)                 \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 0, 5, value)
+#define SINGLE_CHANNELSWITCH_GET_CLASS(h2c_pkt)                                \
+	GET_H2C_FIELD(h2c_pkt + 0X00, 5, 3)
+#define SINGLE_CHANNELSWITCH_SET_CLASS(h2c_pkt, value)                         \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 5, 3, value)
+#define SINGLE_CHANNELSWITCH_SET_CLASS_NO_CLR(h2c_pkt, value)                  \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 5, 3, value)
+#define SINGLE_CHANNELSWITCH_GET_CHANNEL_NUM(h2c_pkt)                          \
+	GET_H2C_FIELD(h2c_pkt + 0X00, 8, 8)
+#define SINGLE_CHANNELSWITCH_SET_CHANNEL_NUM(h2c_pkt, value)                   \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 8, 8, value)
+#define SINGLE_CHANNELSWITCH_SET_CHANNEL_NUM_NO_CLR(h2c_pkt, value)            \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 8, 8, value)
+#define SINGLE_CHANNELSWITCH_GET_BW(h2c_pkt)                                   \
+	GET_H2C_FIELD(h2c_pkt + 0X00, 16, 2)
+#define SINGLE_CHANNELSWITCH_SET_BW(h2c_pkt, value)                            \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 16, 2, value)
+#define SINGLE_CHANNELSWITCH_SET_BW_NO_CLR(h2c_pkt, value)                     \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 16, 2, value)
+#define SINGLE_CHANNELSWITCH_GET_BW40SC(h2c_pkt)                               \
+	GET_H2C_FIELD(h2c_pkt + 0X00, 18, 3)
+#define SINGLE_CHANNELSWITCH_SET_BW40SC(h2c_pkt, value)                        \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 18, 3, value)
+#define SINGLE_CHANNELSWITCH_SET_BW40SC_NO_CLR(h2c_pkt, value)                 \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 18, 3, value)
+#define SINGLE_CHANNELSWITCH_GET_BW80SC(h2c_pkt)                               \
+	GET_H2C_FIELD(h2c_pkt + 0X00, 21, 3)
+#define SINGLE_CHANNELSWITCH_SET_BW80SC(h2c_pkt, value)                        \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 21, 3, value)
+#define SINGLE_CHANNELSWITCH_SET_BW80SC_NO_CLR(h2c_pkt, value)                 \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 21, 3, value)
+#define SINGLE_CHANNELSWITCH_GET_RFE_TYPE(h2c_pkt)                             \
+	GET_H2C_FIELD(h2c_pkt + 0X00, 24, 4)
+#define SINGLE_CHANNELSWITCH_SET_RFE_TYPE(h2c_pkt, value)                      \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 24, 4, value)
+#define SINGLE_CHANNELSWITCH_SET_RFE_TYPE_NO_CLR(h2c_pkt, value)               \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 24, 4, value)
+#define SINGLE_CHANNELSWITCH_V2_GET_CMD_ID(h2c_pkt)                            \
+	GET_H2C_FIELD(h2c_pkt + 0X00, 0, 5)
+#define SINGLE_CHANNELSWITCH_V2_SET_CMD_ID(h2c_pkt, value)                     \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 0, 5, value)
+#define SINGLE_CHANNELSWITCH_V2_SET_CMD_ID_NO_CLR(h2c_pkt, value)              \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 0, 5, value)
+#define SINGLE_CHANNELSWITCH_V2_GET_CLASS(h2c_pkt)                             \
+	GET_H2C_FIELD(h2c_pkt + 0X00, 5, 3)
+#define SINGLE_CHANNELSWITCH_V2_SET_CLASS(h2c_pkt, value)                      \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 5, 3, value)
+#define SINGLE_CHANNELSWITCH_V2_SET_CLASS_NO_CLR(h2c_pkt, value)               \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 5, 3, value)
+#define SINGLE_CHANNELSWITCH_V2_GET_CENTRAL_CH(h2c_pkt)                        \
+	GET_H2C_FIELD(h2c_pkt + 0X00, 8, 8)
+#define SINGLE_CHANNELSWITCH_V2_SET_CENTRAL_CH(h2c_pkt, value)                 \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 8, 8, value)
+#define SINGLE_CHANNELSWITCH_V2_SET_CENTRAL_CH_NO_CLR(h2c_pkt, value)          \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 8, 8, value)
+#define SINGLE_CHANNELSWITCH_V2_GET_PRIMARY_CH_IDX(h2c_pkt)                    \
+	GET_H2C_FIELD(h2c_pkt + 0X00, 16, 4)
+#define SINGLE_CHANNELSWITCH_V2_SET_PRIMARY_CH_IDX(h2c_pkt, value)             \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 16, 4, value)
+#define SINGLE_CHANNELSWITCH_V2_SET_PRIMARY_CH_IDX_NO_CLR(h2c_pkt, value)      \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 16, 4, value)
+#define SINGLE_CHANNELSWITCH_V2_GET_BW(h2c_pkt)                                \
+	GET_H2C_FIELD(h2c_pkt + 0X00, 20, 4)
+#define SINGLE_CHANNELSWITCH_V2_SET_BW(h2c_pkt, value)                         \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 20, 4, value)
+#define SINGLE_CHANNELSWITCH_V2_SET_BW_NO_CLR(h2c_pkt, value)                  \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 20, 4, value)
+#define SET_PWR_MODE_GET_CMD_ID(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 0, 5)
+#define SET_PWR_MODE_SET_CMD_ID(h2c_pkt, value)                                \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 0, 5, value)
+#define SET_PWR_MODE_SET_CMD_ID_NO_CLR(h2c_pkt, value)                         \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 0, 5, value)
+#define SET_PWR_MODE_GET_CLASS(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 5, 3)
+#define SET_PWR_MODE_SET_CLASS(h2c_pkt, value)                                 \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 5, 3, value)
+#define SET_PWR_MODE_SET_CLASS_NO_CLR(h2c_pkt, value)                          \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 5, 3, value)
+#define SET_PWR_MODE_GET_MODE(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 8, 7)
+#define SET_PWR_MODE_SET_MODE(h2c_pkt, value)                                  \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 8, 7, value)
+#define SET_PWR_MODE_SET_MODE_NO_CLR(h2c_pkt, value)                           \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 8, 7, value)
+#define SET_PWR_MODE_GET_CLK_REQUEST(h2c_pkt)                                  \
+	GET_H2C_FIELD(h2c_pkt + 0X00, 15, 1)
+#define SET_PWR_MODE_SET_CLK_REQUEST(h2c_pkt, value)                           \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 15, 1, value)
+#define SET_PWR_MODE_SET_CLK_REQUEST_NO_CLR(h2c_pkt, value)                    \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 15, 1, value)
+#define SET_PWR_MODE_GET_RLBM(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 16, 4)
+#define SET_PWR_MODE_SET_RLBM(h2c_pkt, value)                                  \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 16, 4, value)
+#define SET_PWR_MODE_SET_RLBM_NO_CLR(h2c_pkt, value)                           \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 16, 4, value)
+#define SET_PWR_MODE_GET_SMART_PS(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 20, 4)
+#define SET_PWR_MODE_SET_SMART_PS(h2c_pkt, value)                              \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 20, 4, value)
+#define SET_PWR_MODE_SET_SMART_PS_NO_CLR(h2c_pkt, value)                       \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 20, 4, value)
+#define SET_PWR_MODE_GET_AWAKE_INTERVAL(h2c_pkt)                               \
+	GET_H2C_FIELD(h2c_pkt + 0X00, 24, 8)
+#define SET_PWR_MODE_SET_AWAKE_INTERVAL(h2c_pkt, value)                        \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 24, 8, value)
+#define SET_PWR_MODE_SET_AWAKE_INTERVAL_NO_CLR(h2c_pkt, value)                 \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 24, 8, value)
+#define SET_PWR_MODE_GET_B_ALL_QUEUE_UAPSD(h2c_pkt)                            \
+	GET_H2C_FIELD(h2c_pkt + 0X04, 0, 1)
+#define SET_PWR_MODE_SET_B_ALL_QUEUE_UAPSD(h2c_pkt, value)                     \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X04, 0, 1, value)
+#define SET_PWR_MODE_SET_B_ALL_QUEUE_UAPSD_NO_CLR(h2c_pkt, value)              \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 0, 1, value)
+#define SET_PWR_MODE_GET_BCN_EARLY_RPT(h2c_pkt)                                \
+	GET_H2C_FIELD(h2c_pkt + 0X04, 2, 1)
+#define SET_PWR_MODE_SET_BCN_EARLY_RPT(h2c_pkt, value)                         \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X04, 2, 1, value)
+#define SET_PWR_MODE_SET_BCN_EARLY_RPT_NO_CLR(h2c_pkt, value)                  \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 2, 1, value)
+#define SET_PWR_MODE_GET_PORT_ID(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X04, 5, 3)
+#define SET_PWR_MODE_SET_PORT_ID(h2c_pkt, value)                               \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X04, 5, 3, value)
+#define SET_PWR_MODE_SET_PORT_ID_NO_CLR(h2c_pkt, value)                        \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 5, 3, value)
+#define SET_PWR_MODE_GET_PWR_STATE(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X04, 8, 8)
+#define SET_PWR_MODE_SET_PWR_STATE(h2c_pkt, value)                             \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X04, 8, 8, value)
+#define SET_PWR_MODE_SET_PWR_STATE_NO_CLR(h2c_pkt, value)                      \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 8, 8, value)
+#define SET_PWR_MODE_GET_LOW_POWER_RX_BCN(h2c_pkt)                             \
+	GET_H2C_FIELD(h2c_pkt + 0X04, 16, 1)
+#define SET_PWR_MODE_SET_LOW_POWER_RX_BCN(h2c_pkt, value)                      \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X04, 16, 1, value)
+#define SET_PWR_MODE_SET_LOW_POWER_RX_BCN_NO_CLR(h2c_pkt, value)               \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 16, 1, value)
+#define SET_PWR_MODE_GET_ANT_AUTO_SWITCH(h2c_pkt)                              \
+	GET_H2C_FIELD(h2c_pkt + 0X04, 17, 1)
+#define SET_PWR_MODE_SET_ANT_AUTO_SWITCH(h2c_pkt, value)                       \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X04, 17, 1, value)
+#define SET_PWR_MODE_SET_ANT_AUTO_SWITCH_NO_CLR(h2c_pkt, value)                \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 17, 1, value)
+#define SET_PWR_MODE_GET_PS_ALLOW_BT_HIGH_PRIORITY(h2c_pkt)                    \
+	GET_H2C_FIELD(h2c_pkt + 0X04, 18, 1)
+#define SET_PWR_MODE_SET_PS_ALLOW_BT_HIGH_PRIORITY(h2c_pkt, value)             \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X04, 18, 1, value)
+#define SET_PWR_MODE_SET_PS_ALLOW_BT_HIGH_PRIORITY_NO_CLR(h2c_pkt, value)      \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 18, 1, value)
+#define SET_PWR_MODE_GET_PROTECT_BCN(h2c_pkt)                                  \
+	GET_H2C_FIELD(h2c_pkt + 0X04, 19, 1)
+#define SET_PWR_MODE_SET_PROTECT_BCN(h2c_pkt, value)                           \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X04, 19, 1, value)
+#define SET_PWR_MODE_SET_PROTECT_BCN_NO_CLR(h2c_pkt, value)                    \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 19, 1, value)
+#define SET_PWR_MODE_GET_SILENCE_PERIOD(h2c_pkt)                               \
+	GET_H2C_FIELD(h2c_pkt + 0X04, 20, 1)
+#define SET_PWR_MODE_SET_SILENCE_PERIOD(h2c_pkt, value)                        \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X04, 20, 1, value)
+#define SET_PWR_MODE_SET_SILENCE_PERIOD_NO_CLR(h2c_pkt, value)                 \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 20, 1, value)
+#define SET_PWR_MODE_GET_FAST_BT_CONNECT(h2c_pkt)                              \
+	GET_H2C_FIELD(h2c_pkt + 0X04, 21, 1)
+#define SET_PWR_MODE_SET_FAST_BT_CONNECT(h2c_pkt, value)                       \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X04, 21, 1, value)
+#define SET_PWR_MODE_SET_FAST_BT_CONNECT_NO_CLR(h2c_pkt, value)                \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 21, 1, value)
+#define SET_PWR_MODE_GET_TWO_ANTENNA_EN(h2c_pkt)                               \
+	GET_H2C_FIELD(h2c_pkt + 0X04, 22, 1)
+#define SET_PWR_MODE_SET_TWO_ANTENNA_EN(h2c_pkt, value)                        \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X04, 22, 1, value)
+#define SET_PWR_MODE_SET_TWO_ANTENNA_EN_NO_CLR(h2c_pkt, value)                 \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 22, 1, value)
+#define SET_PWR_MODE_GET_ADOPT_USER_SETTING(h2c_pkt)                           \
+	GET_H2C_FIELD(h2c_pkt + 0X04, 24, 1)
+#define SET_PWR_MODE_SET_ADOPT_USER_SETTING(h2c_pkt, value)                    \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X04, 24, 1, value)
+#define SET_PWR_MODE_SET_ADOPT_USER_SETTING_NO_CLR(h2c_pkt, value)             \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 24, 1, value)
+#define SET_PWR_MODE_GET_DRV_BCN_EARLY_SHIFT(h2c_pkt)                          \
+	GET_H2C_FIELD(h2c_pkt + 0X04, 25, 3)
+#define SET_PWR_MODE_SET_DRV_BCN_EARLY_SHIFT(h2c_pkt, value)                   \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X04, 25, 3, value)
+#define SET_PWR_MODE_SET_DRV_BCN_EARLY_SHIFT_NO_CLR(h2c_pkt, value)            \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 25, 3, value)
+#define SET_PWR_MODE_GET_DRV_BCN_EARLY_SHIFT2(h2c_pkt)                         \
+	GET_H2C_FIELD(h2c_pkt + 0X04, 28, 4)
+#define SET_PWR_MODE_SET_DRV_BCN_EARLY_SHIFT2(h2c_pkt, value)                  \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X04, 28, 4, value)
+#define SET_PWR_MODE_SET_DRV_BCN_EARLY_SHIFT2_NO_CLR(h2c_pkt, value)           \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 28, 4, value)
+#define PS_TUNING_PARA_GET_CMD_ID(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 0, 5)
+#define PS_TUNING_PARA_SET_CMD_ID(h2c_pkt, value)                              \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 0, 5, value)
+#define PS_TUNING_PARA_SET_CMD_ID_NO_CLR(h2c_pkt, value)                       \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 0, 5, value)
+#define PS_TUNING_PARA_GET_CLASS(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 5, 3)
+#define PS_TUNING_PARA_SET_CLASS(h2c_pkt, value)                               \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 5, 3, value)
+#define PS_TUNING_PARA_SET_CLASS_NO_CLR(h2c_pkt, value)                        \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 5, 3, value)
+#define PS_TUNING_PARA_GET_BCN_TO_LIMIT(h2c_pkt)                               \
+	GET_H2C_FIELD(h2c_pkt + 0X00, 8, 7)
+#define PS_TUNING_PARA_SET_BCN_TO_LIMIT(h2c_pkt, value)                        \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 8, 7, value)
+#define PS_TUNING_PARA_SET_BCN_TO_LIMIT_NO_CLR(h2c_pkt, value)                 \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 8, 7, value)
+#define PS_TUNING_PARA_GET_DTIM_TIME_OUT(h2c_pkt)                              \
+	GET_H2C_FIELD(h2c_pkt + 0X00, 15, 1)
+#define PS_TUNING_PARA_SET_DTIM_TIME_OUT(h2c_pkt, value)                       \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 15, 1, value)
+#define PS_TUNING_PARA_SET_DTIM_TIME_OUT_NO_CLR(h2c_pkt, value)                \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 15, 1, value)
+#define PS_TUNING_PARA_GET_PS_TIME_OUT(h2c_pkt)                                \
+	GET_H2C_FIELD(h2c_pkt + 0X00, 16, 4)
+#define PS_TUNING_PARA_SET_PS_TIME_OUT(h2c_pkt, value)                         \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 16, 4, value)
+#define PS_TUNING_PARA_SET_PS_TIME_OUT_NO_CLR(h2c_pkt, value)                  \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 16, 4, value)
+#define PS_TUNING_PARA_GET_ADOPT(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 24, 8)
+#define PS_TUNING_PARA_SET_ADOPT(h2c_pkt, value)                               \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 24, 8, value)
+#define PS_TUNING_PARA_SET_ADOPT_NO_CLR(h2c_pkt, value)                        \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 24, 8, value)
+#define PS_TUNING_PARA_II_GET_CMD_ID(h2c_pkt)                                  \
+	GET_H2C_FIELD(h2c_pkt + 0X00, 0, 5)
+#define PS_TUNING_PARA_II_SET_CMD_ID(h2c_pkt, value)                           \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 0, 5, value)
+#define PS_TUNING_PARA_II_SET_CMD_ID_NO_CLR(h2c_pkt, value)                    \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 0, 5, value)
+#define PS_TUNING_PARA_II_GET_CLASS(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 5, 3)
+#define PS_TUNING_PARA_II_SET_CLASS(h2c_pkt, value)                            \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 5, 3, value)
+#define PS_TUNING_PARA_II_SET_CLASS_NO_CLR(h2c_pkt, value)                     \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 5, 3, value)
+#define PS_TUNING_PARA_II_GET_BCN_TO_PERIOD(h2c_pkt)                           \
+	GET_H2C_FIELD(h2c_pkt + 0X00, 8, 7)
+#define PS_TUNING_PARA_II_SET_BCN_TO_PERIOD(h2c_pkt, value)                    \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 8, 7, value)
+#define PS_TUNING_PARA_II_SET_BCN_TO_PERIOD_NO_CLR(h2c_pkt, value)             \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 8, 7, value)
+#define PS_TUNING_PARA_II_GET_ADOPT(h2c_pkt)                                   \
+	GET_H2C_FIELD(h2c_pkt + 0X00, 15, 1)
+#define PS_TUNING_PARA_II_SET_ADOPT(h2c_pkt, value)                            \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 15, 1, value)
+#define PS_TUNING_PARA_II_SET_ADOPT_NO_CLR(h2c_pkt, value)                     \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 15, 1, value)
+#define PS_TUNING_PARA_II_GET_DRV_EARLY_IVL(h2c_pkt)                           \
+	GET_H2C_FIELD(h2c_pkt + 0X00, 16, 8)
+#define PS_TUNING_PARA_II_SET_DRV_EARLY_IVL(h2c_pkt, value)                    \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 16, 8, value)
+#define PS_TUNING_PARA_II_SET_DRV_EARLY_IVL_NO_CLR(h2c_pkt, value)             \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 16, 8, value)
+#define PS_LPS_PARA_GET_CMD_ID(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 0, 5)
+#define PS_LPS_PARA_SET_CMD_ID(h2c_pkt, value)                                 \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 0, 5, value)
+#define PS_LPS_PARA_SET_CMD_ID_NO_CLR(h2c_pkt, value)                          \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 0, 5, value)
+#define PS_LPS_PARA_GET_CLASS(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 5, 3)
+#define PS_LPS_PARA_SET_CLASS(h2c_pkt, value)                                  \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 5, 3, value)
+#define PS_LPS_PARA_SET_CLASS_NO_CLR(h2c_pkt, value)                           \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 5, 3, value)
+#define PS_LPS_PARA_GET_LPS_CONTROL(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 8, 8)
+#define PS_LPS_PARA_SET_LPS_CONTROL(h2c_pkt, value)                            \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 8, 8, value)
+#define PS_LPS_PARA_SET_LPS_CONTROL_NO_CLR(h2c_pkt, value)                     \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 8, 8, value)
+#define P2P_PS_OFFLOAD_GET_CMD_ID(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 0, 5)
+#define P2P_PS_OFFLOAD_SET_CMD_ID(h2c_pkt, value)                              \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 0, 5, value)
+#define P2P_PS_OFFLOAD_SET_CMD_ID_NO_CLR(h2c_pkt, value)                       \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 0, 5, value)
+#define P2P_PS_OFFLOAD_GET_CLASS(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 5, 3)
+#define P2P_PS_OFFLOAD_SET_CLASS(h2c_pkt, value)                               \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 5, 3, value)
+#define P2P_PS_OFFLOAD_SET_CLASS_NO_CLR(h2c_pkt, value)                        \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 5, 3, value)
+#define P2P_PS_OFFLOAD_GET_OFFLOAD_EN(h2c_pkt)                                 \
+	GET_H2C_FIELD(h2c_pkt + 0X00, 8, 1)
+#define P2P_PS_OFFLOAD_SET_OFFLOAD_EN(h2c_pkt, value)                          \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 8, 1, value)
+#define P2P_PS_OFFLOAD_SET_OFFLOAD_EN_NO_CLR(h2c_pkt, value)                   \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 8, 1, value)
+#define P2P_PS_OFFLOAD_GET_ROLE(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 9, 1)
+#define P2P_PS_OFFLOAD_SET_ROLE(h2c_pkt, value)                                \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 9, 1, value)
+#define P2P_PS_OFFLOAD_SET_ROLE_NO_CLR(h2c_pkt, value)                         \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 9, 1, value)
+#define P2P_PS_OFFLOAD_GET_CTWINDOW_EN(h2c_pkt)                                \
+	GET_H2C_FIELD(h2c_pkt + 0X00, 10, 1)
+#define P2P_PS_OFFLOAD_SET_CTWINDOW_EN(h2c_pkt, value)                         \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 10, 1, value)
+#define P2P_PS_OFFLOAD_SET_CTWINDOW_EN_NO_CLR(h2c_pkt, value)                  \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 10, 1, value)
+#define P2P_PS_OFFLOAD_GET_NOA0_EN(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 11, 1)
+#define P2P_PS_OFFLOAD_SET_NOA0_EN(h2c_pkt, value)                             \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 11, 1, value)
+#define P2P_PS_OFFLOAD_SET_NOA0_EN_NO_CLR(h2c_pkt, value)                      \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 11, 1, value)
+#define P2P_PS_OFFLOAD_GET_NOA1_EN(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 12, 1)
+#define P2P_PS_OFFLOAD_SET_NOA1_EN(h2c_pkt, value)                             \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 12, 1, value)
+#define P2P_PS_OFFLOAD_SET_NOA1_EN_NO_CLR(h2c_pkt, value)                      \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 12, 1, value)
+#define P2P_PS_OFFLOAD_GET_ALL_STA_SLEEP(h2c_pkt)                              \
+	GET_H2C_FIELD(h2c_pkt + 0X00, 13, 1)
+#define P2P_PS_OFFLOAD_SET_ALL_STA_SLEEP(h2c_pkt, value)                       \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 13, 1, value)
+#define P2P_PS_OFFLOAD_SET_ALL_STA_SLEEP_NO_CLR(h2c_pkt, value)                \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 13, 1, value)
+#define P2P_PS_OFFLOAD_GET_DISCOVERY(h2c_pkt)                                  \
+	GET_H2C_FIELD(h2c_pkt + 0X00, 14, 1)
+#define P2P_PS_OFFLOAD_SET_DISCOVERY(h2c_pkt, value)                           \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 14, 1, value)
+#define P2P_PS_OFFLOAD_SET_DISCOVERY_NO_CLR(h2c_pkt, value)                    \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 14, 1, value)
+#define PS_SCAN_EN_GET_CMD_ID(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 0, 5)
+#define PS_SCAN_EN_SET_CMD_ID(h2c_pkt, value)                                  \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 0, 5, value)
+#define PS_SCAN_EN_SET_CMD_ID_NO_CLR(h2c_pkt, value)                           \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 0, 5, value)
+#define PS_SCAN_EN_GET_CLASS(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 5, 3)
+#define PS_SCAN_EN_SET_CLASS(h2c_pkt, value)                                   \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 5, 3, value)
+#define PS_SCAN_EN_SET_CLASS_NO_CLR(h2c_pkt, value)                            \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 5, 3, value)
+#define PS_SCAN_EN_GET_ENABLE(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 8, 1)
+#define PS_SCAN_EN_SET_ENABLE(h2c_pkt, value)                                  \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 8, 1, value)
+#define PS_SCAN_EN_SET_ENABLE_NO_CLR(h2c_pkt, value)                           \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 8, 1, value)
+#define SAP_PS_GET_CMD_ID(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 0, 5)
+#define SAP_PS_SET_CMD_ID(h2c_pkt, value)                                      \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 0, 5, value)
+#define SAP_PS_SET_CMD_ID_NO_CLR(h2c_pkt, value)                               \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 0, 5, value)
+#define SAP_PS_GET_CLASS(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 5, 3)
+#define SAP_PS_SET_CLASS(h2c_pkt, value)                                       \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 5, 3, value)
+#define SAP_PS_SET_CLASS_NO_CLR(h2c_pkt, value)                                \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 5, 3, value)
+#define SAP_PS_GET_ENABLE(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 8, 1)
+#define SAP_PS_SET_ENABLE(h2c_pkt, value)                                      \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 8, 1, value)
+#define SAP_PS_SET_ENABLE_NO_CLR(h2c_pkt, value)                               \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 8, 1, value)
+#define SAP_PS_GET_EN_PS(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 9, 1)
+#define SAP_PS_SET_EN_PS(h2c_pkt, value)                                       \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 9, 1, value)
+#define SAP_PS_SET_EN_PS_NO_CLR(h2c_pkt, value)                                \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 9, 1, value)
+#define SAP_PS_GET_EN_LP_RX(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 10, 1)
+#define SAP_PS_SET_EN_LP_RX(h2c_pkt, value)                                    \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 10, 1, value)
+#define SAP_PS_SET_EN_LP_RX_NO_CLR(h2c_pkt, value)                             \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 10, 1, value)
+#define SAP_PS_GET_MANUAL_32K(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 11, 1)
+#define SAP_PS_SET_MANUAL_32K(h2c_pkt, value)                                  \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 11, 1, value)
+#define SAP_PS_SET_MANUAL_32K_NO_CLR(h2c_pkt, value)                           \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 11, 1, value)
+#define SAP_PS_GET_DURATION(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 16, 8)
+#define SAP_PS_SET_DURATION(h2c_pkt, value)                                    \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 16, 8, value)
+#define SAP_PS_SET_DURATION_NO_CLR(h2c_pkt, value)                             \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 16, 8, value)
+#define INACTIVE_PS_GET_CMD_ID(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 0, 5)
+#define INACTIVE_PS_SET_CMD_ID(h2c_pkt, value)                                 \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 0, 5, value)
+#define INACTIVE_PS_SET_CMD_ID_NO_CLR(h2c_pkt, value)                          \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 0, 5, value)
+#define INACTIVE_PS_GET_CLASS(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 5, 3)
+#define INACTIVE_PS_SET_CLASS(h2c_pkt, value)                                  \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 5, 3, value)
+#define INACTIVE_PS_SET_CLASS_NO_CLR(h2c_pkt, value)                           \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 5, 3, value)
+#define INACTIVE_PS_GET_ENABLE(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 8, 1)
+#define INACTIVE_PS_SET_ENABLE(h2c_pkt, value)                                 \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 8, 1, value)
+#define INACTIVE_PS_SET_ENABLE_NO_CLR(h2c_pkt, value)                          \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 8, 1, value)
+#define INACTIVE_PS_GET_IGNORE_PS_CONDITION(h2c_pkt)                           \
+	GET_H2C_FIELD(h2c_pkt + 0X00, 9, 1)
+#define INACTIVE_PS_SET_IGNORE_PS_CONDITION(h2c_pkt, value)                    \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 9, 1, value)
+#define INACTIVE_PS_SET_IGNORE_PS_CONDITION_NO_CLR(h2c_pkt, value)             \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 9, 1, value)
+#define INACTIVE_PS_GET_FREQUENCY(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 16, 8)
+#define INACTIVE_PS_SET_FREQUENCY(h2c_pkt, value)                              \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 16, 8, value)
+#define INACTIVE_PS_SET_FREQUENCY_NO_CLR(h2c_pkt, value)                       \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 16, 8, value)
+#define INACTIVE_PS_GET_DURATION(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 24, 8)
+#define INACTIVE_PS_SET_DURATION(h2c_pkt, value)                               \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 24, 8, value)
+#define INACTIVE_PS_SET_DURATION_NO_CLR(h2c_pkt, value)                        \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 24, 8, value)
+#define MACID_CFG_GET_CMD_ID(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 0, 5)
+#define MACID_CFG_SET_CMD_ID(h2c_pkt, value)                                   \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 0, 5, value)
+#define MACID_CFG_SET_CMD_ID_NO_CLR(h2c_pkt, value)                            \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 0, 5, value)
+#define MACID_CFG_GET_CLASS(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 5, 3)
+#define MACID_CFG_SET_CLASS(h2c_pkt, value)                                    \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 5, 3, value)
+#define MACID_CFG_SET_CLASS_NO_CLR(h2c_pkt, value)                             \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 5, 3, value)
+#define MACID_CFG_GET_MAC_ID(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 8, 8)
+#define MACID_CFG_SET_MAC_ID(h2c_pkt, value)                                   \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 8, 8, value)
+#define MACID_CFG_SET_MAC_ID_NO_CLR(h2c_pkt, value)                            \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 8, 8, value)
+#define MACID_CFG_GET_RATE_ID(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 16, 5)
+#define MACID_CFG_SET_RATE_ID(h2c_pkt, value)                                  \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 16, 5, value)
+#define MACID_CFG_SET_RATE_ID_NO_CLR(h2c_pkt, value)                           \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 16, 5, value)
+#define MACID_CFG_GET_INIT_RATE_LV(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 21, 2)
+#define MACID_CFG_SET_INIT_RATE_LV(h2c_pkt, value)                             \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 21, 2, value)
+#define MACID_CFG_SET_INIT_RATE_LV_NO_CLR(h2c_pkt, value)                      \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 21, 2, value)
+#define MACID_CFG_GET_SGI(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 23, 1)
+#define MACID_CFG_SET_SGI(h2c_pkt, value)                                      \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 23, 1, value)
+#define MACID_CFG_SET_SGI_NO_CLR(h2c_pkt, value)                               \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 23, 1, value)
+#define MACID_CFG_GET_BW(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 24, 2)
+#define MACID_CFG_SET_BW(h2c_pkt, value)                                       \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 24, 2, value)
+#define MACID_CFG_SET_BW_NO_CLR(h2c_pkt, value)                                \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 24, 2, value)
+#define MACID_CFG_GET_LDPC_CAP(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 26, 1)
+#define MACID_CFG_SET_LDPC_CAP(h2c_pkt, value)                                 \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 26, 1, value)
+#define MACID_CFG_SET_LDPC_CAP_NO_CLR(h2c_pkt, value)                          \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 26, 1, value)
+#define MACID_CFG_GET_NO_UPDATE(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 27, 1)
+#define MACID_CFG_SET_NO_UPDATE(h2c_pkt, value)                                \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 27, 1, value)
+#define MACID_CFG_SET_NO_UPDATE_NO_CLR(h2c_pkt, value)                         \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 27, 1, value)
+#define MACID_CFG_GET_WHT_EN(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 28, 2)
+#define MACID_CFG_SET_WHT_EN(h2c_pkt, value)                                   \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 28, 2, value)
+#define MACID_CFG_SET_WHT_EN_NO_CLR(h2c_pkt, value)                            \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 28, 2, value)
+#define MACID_CFG_GET_DISPT(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 30, 1)
+#define MACID_CFG_SET_DISPT(h2c_pkt, value)                                    \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 30, 1, value)
+#define MACID_CFG_SET_DISPT_NO_CLR(h2c_pkt, value)                             \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 30, 1, value)
+#define MACID_CFG_GET_DISRA(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 31, 1)
+#define MACID_CFG_SET_DISRA(h2c_pkt, value)                                    \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 31, 1, value)
+#define MACID_CFG_SET_DISRA_NO_CLR(h2c_pkt, value)                             \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 31, 1, value)
+#define MACID_CFG_GET_RATE_MASK7_0(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X04, 0, 8)
+#define MACID_CFG_SET_RATE_MASK7_0(h2c_pkt, value)                             \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X04, 0, 8, value)
+#define MACID_CFG_SET_RATE_MASK7_0_NO_CLR(h2c_pkt, value)                      \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 0, 8, value)
+#define MACID_CFG_GET_RATE_MASK15_8(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X04, 8, 8)
+#define MACID_CFG_SET_RATE_MASK15_8(h2c_pkt, value)                            \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X04, 8, 8, value)
+#define MACID_CFG_SET_RATE_MASK15_8_NO_CLR(h2c_pkt, value)                     \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 8, 8, value)
+#define MACID_CFG_GET_RATE_MASK23_16(h2c_pkt)                                  \
+	GET_H2C_FIELD(h2c_pkt + 0X04, 16, 8)
+#define MACID_CFG_SET_RATE_MASK23_16(h2c_pkt, value)                           \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X04, 16, 8, value)
+#define MACID_CFG_SET_RATE_MASK23_16_NO_CLR(h2c_pkt, value)                    \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 16, 8, value)
+#define MACID_CFG_GET_RATE_MASK31_24(h2c_pkt)                                  \
+	GET_H2C_FIELD(h2c_pkt + 0X04, 24, 8)
+#define MACID_CFG_SET_RATE_MASK31_24(h2c_pkt, value)                           \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X04, 24, 8, value)
+#define MACID_CFG_SET_RATE_MASK31_24_NO_CLR(h2c_pkt, value)                    \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 24, 8, value)
+#define TXBF_GET_CMD_ID(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 0, 5)
+#define TXBF_SET_CMD_ID(h2c_pkt, value)                                        \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 0, 5, value)
+#define TXBF_SET_CMD_ID_NO_CLR(h2c_pkt, value)                                 \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 0, 5, value)
+#define TXBF_GET_CLASS(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 5, 3)
+#define TXBF_SET_CLASS(h2c_pkt, value)                                         \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 5, 3, value)
+#define TXBF_SET_CLASS_NO_CLR(h2c_pkt, value)                                  \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 5, 3, value)
+#define TXBF_GET_NDPA0_HEAD_PAGE(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 8, 8)
+#define TXBF_SET_NDPA0_HEAD_PAGE(h2c_pkt, value)                               \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 8, 8, value)
+#define TXBF_SET_NDPA0_HEAD_PAGE_NO_CLR(h2c_pkt, value)                        \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 8, 8, value)
+#define TXBF_GET_NDPA1_HEAD_PAGE(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 16, 8)
+#define TXBF_SET_NDPA1_HEAD_PAGE(h2c_pkt, value)                               \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 16, 8, value)
+#define TXBF_SET_NDPA1_HEAD_PAGE_NO_CLR(h2c_pkt, value)                        \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 16, 8, value)
+#define TXBF_GET_PERIOD_0(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 24, 8)
+#define TXBF_SET_PERIOD_0(h2c_pkt, value)                                      \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 24, 8, value)
+#define TXBF_SET_PERIOD_0_NO_CLR(h2c_pkt, value)                               \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 24, 8, value)
+#define RSSI_SETTING_GET_CMD_ID(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 0, 5)
+#define RSSI_SETTING_SET_CMD_ID(h2c_pkt, value)                                \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 0, 5, value)
+#define RSSI_SETTING_SET_CMD_ID_NO_CLR(h2c_pkt, value)                         \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 0, 5, value)
+#define RSSI_SETTING_GET_CLASS(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 5, 3)
+#define RSSI_SETTING_SET_CLASS(h2c_pkt, value)                                 \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 5, 3, value)
+#define RSSI_SETTING_SET_CLASS_NO_CLR(h2c_pkt, value)                          \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 5, 3, value)
+#define RSSI_SETTING_GET_MAC_ID(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 8, 8)
+#define RSSI_SETTING_SET_MAC_ID(h2c_pkt, value)                                \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 8, 8, value)
+#define RSSI_SETTING_SET_MAC_ID_NO_CLR(h2c_pkt, value)                         \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 8, 8, value)
+#define RSSI_SETTING_GET_RSSI(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 24, 7)
+#define RSSI_SETTING_SET_RSSI(h2c_pkt, value)                                  \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 24, 7, value)
+#define RSSI_SETTING_SET_RSSI_NO_CLR(h2c_pkt, value)                           \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 24, 7, value)
+#define RSSI_SETTING_GET_RA_INFO(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X04, 0, 8)
+#define RSSI_SETTING_SET_RA_INFO(h2c_pkt, value)                               \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X04, 0, 8, value)
+#define RSSI_SETTING_SET_RA_INFO_NO_CLR(h2c_pkt, value)                        \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 0, 8, value)
+#define AP_REQ_TXRPT_GET_CMD_ID(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 0, 5)
+#define AP_REQ_TXRPT_SET_CMD_ID(h2c_pkt, value)                                \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 0, 5, value)
+#define AP_REQ_TXRPT_SET_CMD_ID_NO_CLR(h2c_pkt, value)                         \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 0, 5, value)
+#define AP_REQ_TXRPT_GET_CLASS(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 5, 3)
+#define AP_REQ_TXRPT_SET_CLASS(h2c_pkt, value)                                 \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 5, 3, value)
+#define AP_REQ_TXRPT_SET_CLASS_NO_CLR(h2c_pkt, value)                          \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 5, 3, value)
+#define AP_REQ_TXRPT_GET_STA1_MACID(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 8, 8)
+#define AP_REQ_TXRPT_SET_STA1_MACID(h2c_pkt, value)                            \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 8, 8, value)
+#define AP_REQ_TXRPT_SET_STA1_MACID_NO_CLR(h2c_pkt, value)                     \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 8, 8, value)
+#define AP_REQ_TXRPT_GET_STA2_MACID(h2c_pkt)                                   \
+	GET_H2C_FIELD(h2c_pkt + 0X00, 16, 8)
+#define AP_REQ_TXRPT_SET_STA2_MACID(h2c_pkt, value)                            \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 16, 8, value)
+#define AP_REQ_TXRPT_SET_STA2_MACID_NO_CLR(h2c_pkt, value)                     \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 16, 8, value)
+#define AP_REQ_TXRPT_GET_RTY_OK_TOTAL(h2c_pkt)                                 \
+	GET_H2C_FIELD(h2c_pkt + 0X00, 24, 1)
+#define AP_REQ_TXRPT_SET_RTY_OK_TOTAL(h2c_pkt, value)                          \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 24, 1, value)
+#define AP_REQ_TXRPT_SET_RTY_OK_TOTAL_NO_CLR(h2c_pkt, value)                   \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 24, 1, value)
+#define AP_REQ_TXRPT_GET_RTY_CNT_MACID(h2c_pkt)                                \
+	GET_H2C_FIELD(h2c_pkt + 0X00, 25, 1)
+#define AP_REQ_TXRPT_SET_RTY_CNT_MACID(h2c_pkt, value)                         \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 25, 1, value)
+#define AP_REQ_TXRPT_SET_RTY_CNT_MACID_NO_CLR(h2c_pkt, value)                  \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 25, 1, value)
+#define INIT_RATE_COLLECTION_GET_CMD_ID(h2c_pkt)                               \
+	GET_H2C_FIELD(h2c_pkt + 0X00, 0, 5)
+#define INIT_RATE_COLLECTION_SET_CMD_ID(h2c_pkt, value)                        \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 0, 5, value)
+#define INIT_RATE_COLLECTION_SET_CMD_ID_NO_CLR(h2c_pkt, value)                 \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 0, 5, value)
+#define INIT_RATE_COLLECTION_GET_CLASS(h2c_pkt)                                \
+	GET_H2C_FIELD(h2c_pkt + 0X00, 5, 3)
+#define INIT_RATE_COLLECTION_SET_CLASS(h2c_pkt, value)                         \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 5, 3, value)
+#define INIT_RATE_COLLECTION_SET_CLASS_NO_CLR(h2c_pkt, value)                  \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 5, 3, value)
+#define INIT_RATE_COLLECTION_GET_STA1_MACID(h2c_pkt)                           \
+	GET_H2C_FIELD(h2c_pkt + 0X00, 8, 8)
+#define INIT_RATE_COLLECTION_SET_STA1_MACID(h2c_pkt, value)                    \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 8, 8, value)
+#define INIT_RATE_COLLECTION_SET_STA1_MACID_NO_CLR(h2c_pkt, value)             \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 8, 8, value)
+#define INIT_RATE_COLLECTION_GET_STA2_MACID(h2c_pkt)                           \
+	GET_H2C_FIELD(h2c_pkt + 0X00, 16, 8)
+#define INIT_RATE_COLLECTION_SET_STA2_MACID(h2c_pkt, value)                    \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 16, 8, value)
+#define INIT_RATE_COLLECTION_SET_STA2_MACID_NO_CLR(h2c_pkt, value)             \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 16, 8, value)
+#define INIT_RATE_COLLECTION_GET_STA3_MACID(h2c_pkt)                           \
+	GET_H2C_FIELD(h2c_pkt + 0X00, 24, 8)
+#define INIT_RATE_COLLECTION_SET_STA3_MACID(h2c_pkt, value)                    \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 24, 8, value)
+#define INIT_RATE_COLLECTION_SET_STA3_MACID_NO_CLR(h2c_pkt, value)             \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 24, 8, value)
+#define INIT_RATE_COLLECTION_GET_STA4_MACID(h2c_pkt)                           \
+	GET_H2C_FIELD(h2c_pkt + 0X04, 0, 8)
+#define INIT_RATE_COLLECTION_SET_STA4_MACID(h2c_pkt, value)                    \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X04, 0, 8, value)
+#define INIT_RATE_COLLECTION_SET_STA4_MACID_NO_CLR(h2c_pkt, value)             \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 0, 8, value)
+#define INIT_RATE_COLLECTION_GET_STA5_MACID(h2c_pkt)                           \
+	GET_H2C_FIELD(h2c_pkt + 0X04, 8, 8)
+#define INIT_RATE_COLLECTION_SET_STA5_MACID(h2c_pkt, value)                    \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X04, 8, 8, value)
+#define INIT_RATE_COLLECTION_SET_STA5_MACID_NO_CLR(h2c_pkt, value)             \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 8, 8, value)
+#define INIT_RATE_COLLECTION_GET_STA6_MACID(h2c_pkt)                           \
+	GET_H2C_FIELD(h2c_pkt + 0X04, 16, 8)
+#define INIT_RATE_COLLECTION_SET_STA6_MACID(h2c_pkt, value)                    \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X04, 16, 8, value)
+#define INIT_RATE_COLLECTION_SET_STA6_MACID_NO_CLR(h2c_pkt, value)             \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 16, 8, value)
+#define INIT_RATE_COLLECTION_GET_STA7_MACID(h2c_pkt)                           \
+	GET_H2C_FIELD(h2c_pkt + 0X04, 24, 8)
+#define INIT_RATE_COLLECTION_SET_STA7_MACID(h2c_pkt, value)                    \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X04, 24, 8, value)
+#define INIT_RATE_COLLECTION_SET_STA7_MACID_NO_CLR(h2c_pkt, value)             \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 24, 8, value)
+#define IQK_OFFLOAD_GET_CMD_ID(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 0, 5)
+#define IQK_OFFLOAD_SET_CMD_ID(h2c_pkt, value)                                 \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 0, 5, value)
+#define IQK_OFFLOAD_SET_CMD_ID_NO_CLR(h2c_pkt, value)                          \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 0, 5, value)
+#define IQK_OFFLOAD_GET_CLASS(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 5, 3)
+#define IQK_OFFLOAD_SET_CLASS(h2c_pkt, value)                                  \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 5, 3, value)
+#define IQK_OFFLOAD_SET_CLASS_NO_CLR(h2c_pkt, value)                           \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 5, 3, value)
+#define IQK_OFFLOAD_GET_CHANNEL(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 8, 8)
+#define IQK_OFFLOAD_SET_CHANNEL(h2c_pkt, value)                                \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 8, 8, value)
+#define IQK_OFFLOAD_SET_CHANNEL_NO_CLR(h2c_pkt, value)                         \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 8, 8, value)
+#define IQK_OFFLOAD_GET_BWBAND(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 16, 8)
+#define IQK_OFFLOAD_SET_BWBAND(h2c_pkt, value)                                 \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 16, 8, value)
+#define IQK_OFFLOAD_SET_BWBAND_NO_CLR(h2c_pkt, value)                          \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 16, 8, value)
+#define IQK_OFFLOAD_GET_EXTPALNA(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 24, 8)
+#define IQK_OFFLOAD_SET_EXTPALNA(h2c_pkt, value)                               \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 24, 8, value)
+#define IQK_OFFLOAD_SET_EXTPALNA_NO_CLR(h2c_pkt, value)                        \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 24, 8, value)
+#define MACID_CFG_3SS_GET_CMD_ID(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 0, 5)
+#define MACID_CFG_3SS_SET_CMD_ID(h2c_pkt, value)                               \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 0, 5, value)
+#define MACID_CFG_3SS_SET_CMD_ID_NO_CLR(h2c_pkt, value)                        \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 0, 5, value)
+#define MACID_CFG_3SS_GET_CLASS(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 5, 3)
+#define MACID_CFG_3SS_SET_CLASS(h2c_pkt, value)                                \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 5, 3, value)
+#define MACID_CFG_3SS_SET_CLASS_NO_CLR(h2c_pkt, value)                         \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 5, 3, value)
+#define MACID_CFG_3SS_GET_MACID(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 8, 8)
+#define MACID_CFG_3SS_SET_MACID(h2c_pkt, value)                                \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 8, 8, value)
+#define MACID_CFG_3SS_SET_MACID_NO_CLR(h2c_pkt, value)                         \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 8, 8, value)
+#define MACID_CFG_3SS_GET_RATE_MASK_39_32(h2c_pkt)                             \
+	GET_H2C_FIELD(h2c_pkt + 0X04, 0, 8)
+#define MACID_CFG_3SS_SET_RATE_MASK_39_32(h2c_pkt, value)                      \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X04, 0, 8, value)
+#define MACID_CFG_3SS_SET_RATE_MASK_39_32_NO_CLR(h2c_pkt, value)               \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 0, 8, value)
+#define MACID_CFG_3SS_GET_RATE_MASK_47_40(h2c_pkt)                             \
+	GET_H2C_FIELD(h2c_pkt + 0X04, 8, 8)
+#define MACID_CFG_3SS_SET_RATE_MASK_47_40(h2c_pkt, value)                      \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X04, 8, 8, value)
+#define MACID_CFG_3SS_SET_RATE_MASK_47_40_NO_CLR(h2c_pkt, value)               \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 8, 8, value)
+#define RA_PARA_ADJUST_GET_CMD_ID(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 0, 5)
+#define RA_PARA_ADJUST_SET_CMD_ID(h2c_pkt, value)                              \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 0, 5, value)
+#define RA_PARA_ADJUST_SET_CMD_ID_NO_CLR(h2c_pkt, value)                       \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 0, 5, value)
+#define RA_PARA_ADJUST_GET_CLASS(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 5, 3)
+#define RA_PARA_ADJUST_SET_CLASS(h2c_pkt, value)                               \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 5, 3, value)
+#define RA_PARA_ADJUST_SET_CLASS_NO_CLR(h2c_pkt, value)                        \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 5, 3, value)
+#define RA_PARA_ADJUST_GET_MAC_ID(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 8, 8)
+#define RA_PARA_ADJUST_SET_MAC_ID(h2c_pkt, value)                              \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 8, 8, value)
+#define RA_PARA_ADJUST_SET_MAC_ID_NO_CLR(h2c_pkt, value)                       \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 8, 8, value)
+#define RA_PARA_ADJUST_GET_PARAMETER_INDEX(h2c_pkt)                            \
+	GET_H2C_FIELD(h2c_pkt + 0X00, 16, 8)
+#define RA_PARA_ADJUST_SET_PARAMETER_INDEX(h2c_pkt, value)                     \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 16, 8, value)
+#define RA_PARA_ADJUST_SET_PARAMETER_INDEX_NO_CLR(h2c_pkt, value)              \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 16, 8, value)
+#define RA_PARA_ADJUST_GET_RATE_ID(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 24, 8)
+#define RA_PARA_ADJUST_SET_RATE_ID(h2c_pkt, value)                             \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 24, 8, value)
+#define RA_PARA_ADJUST_SET_RATE_ID_NO_CLR(h2c_pkt, value)                      \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 24, 8, value)
+#define RA_PARA_ADJUST_GET_VALUE_BYTE0(h2c_pkt)                                \
+	GET_H2C_FIELD(h2c_pkt + 0X04, 0, 8)
+#define RA_PARA_ADJUST_SET_VALUE_BYTE0(h2c_pkt, value)                         \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X04, 0, 8, value)
+#define RA_PARA_ADJUST_SET_VALUE_BYTE0_NO_CLR(h2c_pkt, value)                  \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 0, 8, value)
+#define RA_PARA_ADJUST_GET_VALUE_BYTE1(h2c_pkt)                                \
+	GET_H2C_FIELD(h2c_pkt + 0X04, 8, 8)
+#define RA_PARA_ADJUST_SET_VALUE_BYTE1(h2c_pkt, value)                         \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X04, 8, 8, value)
+#define RA_PARA_ADJUST_SET_VALUE_BYTE1_NO_CLR(h2c_pkt, value)                  \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 8, 8, value)
+#define RA_PARA_ADJUST_GET_ASK_FW_FOR_FW_PARA(h2c_pkt)                         \
+	GET_H2C_FIELD(h2c_pkt + 0X04, 16, 8)
+#define RA_PARA_ADJUST_SET_ASK_FW_FOR_FW_PARA(h2c_pkt, value)                  \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X04, 16, 8, value)
+#define RA_PARA_ADJUST_SET_ASK_FW_FOR_FW_PARA_NO_CLR(h2c_pkt, value)           \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 16, 8, value)
+#define WWLAN_GET_CMD_ID(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 0, 5)
+#define WWLAN_SET_CMD_ID(h2c_pkt, value)                                       \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 0, 5, value)
+#define WWLAN_SET_CMD_ID_NO_CLR(h2c_pkt, value)                                \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 0, 5, value)
+#define WWLAN_GET_CLASS(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 5, 3)
+#define WWLAN_SET_CLASS(h2c_pkt, value)                                        \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 5, 3, value)
+#define WWLAN_SET_CLASS_NO_CLR(h2c_pkt, value)                                 \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 5, 3, value)
+#define WWLAN_GET_FUNC_EN(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 8, 1)
+#define WWLAN_SET_FUNC_EN(h2c_pkt, value)                                      \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 8, 1, value)
+#define WWLAN_SET_FUNC_EN_NO_CLR(h2c_pkt, value)                               \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 8, 1, value)
+#define WWLAN_GET_PATTERM_MAT_EN(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 9, 1)
+#define WWLAN_SET_PATTERM_MAT_EN(h2c_pkt, value)                               \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 9, 1, value)
+#define WWLAN_SET_PATTERM_MAT_EN_NO_CLR(h2c_pkt, value)                        \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 9, 1, value)
+#define WWLAN_GET_MAGIC_PKT_EN(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 10, 1)
+#define WWLAN_SET_MAGIC_PKT_EN(h2c_pkt, value)                                 \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 10, 1, value)
+#define WWLAN_SET_MAGIC_PKT_EN_NO_CLR(h2c_pkt, value)                          \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 10, 1, value)
+#define WWLAN_GET_UNICAST_WAKEUP_EN(h2c_pkt)                                   \
+	GET_H2C_FIELD(h2c_pkt + 0X00, 11, 1)
+#define WWLAN_SET_UNICAST_WAKEUP_EN(h2c_pkt, value)                            \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 11, 1, value)
+#define WWLAN_SET_UNICAST_WAKEUP_EN_NO_CLR(h2c_pkt, value)                     \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 11, 1, value)
+#define WWLAN_GET_ALL_PKT_DROP(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 12, 1)
+#define WWLAN_SET_ALL_PKT_DROP(h2c_pkt, value)                                 \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 12, 1, value)
+#define WWLAN_SET_ALL_PKT_DROP_NO_CLR(h2c_pkt, value)                          \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 12, 1, value)
+#define WWLAN_GET_GPIO_ACTIVE(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 13, 1)
+#define WWLAN_SET_GPIO_ACTIVE(h2c_pkt, value)                                  \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 13, 1, value)
+#define WWLAN_SET_GPIO_ACTIVE_NO_CLR(h2c_pkt, value)                           \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 13, 1, value)
+#define WWLAN_GET_REKEY_WAKEUP_EN(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 14, 1)
+#define WWLAN_SET_REKEY_WAKEUP_EN(h2c_pkt, value)                              \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 14, 1, value)
+#define WWLAN_SET_REKEY_WAKEUP_EN_NO_CLR(h2c_pkt, value)                       \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 14, 1, value)
+#define WWLAN_GET_DEAUTH_WAKEUP_EN(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 15, 1)
+#define WWLAN_SET_DEAUTH_WAKEUP_EN(h2c_pkt, value)                             \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 15, 1, value)
+#define WWLAN_SET_DEAUTH_WAKEUP_EN_NO_CLR(h2c_pkt, value)                      \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 15, 1, value)
+#define WWLAN_GET_GPIO_NUM(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 16, 7)
+#define WWLAN_SET_GPIO_NUM(h2c_pkt, value)                                     \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 16, 7, value)
+#define WWLAN_SET_GPIO_NUM_NO_CLR(h2c_pkt, value)                              \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 16, 7, value)
+#define WWLAN_GET_DATAPIN_WAKEUP_EN(h2c_pkt)                                   \
+	GET_H2C_FIELD(h2c_pkt + 0X00, 23, 1)
+#define WWLAN_SET_DATAPIN_WAKEUP_EN(h2c_pkt, value)                            \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 23, 1, value)
+#define WWLAN_SET_DATAPIN_WAKEUP_EN_NO_CLR(h2c_pkt, value)                     \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 23, 1, value)
+#define WWLAN_GET_GPIO_DURATION(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 24, 8)
+#define WWLAN_SET_GPIO_DURATION(h2c_pkt, value)                                \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 24, 8, value)
+#define WWLAN_SET_GPIO_DURATION_NO_CLR(h2c_pkt, value)                         \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 24, 8, value)
+#define WWLAN_GET_GPIO_PLUS_EN(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X04, 0, 1)
+#define WWLAN_SET_GPIO_PLUS_EN(h2c_pkt, value)                                 \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X04, 0, 1, value)
+#define WWLAN_SET_GPIO_PLUS_EN_NO_CLR(h2c_pkt, value)                          \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 0, 1, value)
+#define WWLAN_GET_GPIO_PULSE_COUNT(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X04, 1, 7)
+#define WWLAN_SET_GPIO_PULSE_COUNT(h2c_pkt, value)                             \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X04, 1, 7, value)
+#define WWLAN_SET_GPIO_PULSE_COUNT_NO_CLR(h2c_pkt, value)                      \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 1, 7, value)
+#define WWLAN_GET_DISABLE_UPHY(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X04, 8, 1)
+#define WWLAN_SET_DISABLE_UPHY(h2c_pkt, value)                                 \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X04, 8, 1, value)
+#define WWLAN_SET_DISABLE_UPHY_NO_CLR(h2c_pkt, value)                          \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 8, 1, value)
+#define WWLAN_GET_HST2DEV_EN(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X04, 9, 1)
+#define WWLAN_SET_HST2DEV_EN(h2c_pkt, value)                                   \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X04, 9, 1, value)
+#define WWLAN_SET_HST2DEV_EN_NO_CLR(h2c_pkt, value)                            \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 9, 1, value)
+#define WWLAN_GET_GPIO_DURATION_MS(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X04, 10, 1)
+#define WWLAN_SET_GPIO_DURATION_MS(h2c_pkt, value)                             \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X04, 10, 1, value)
+#define WWLAN_SET_GPIO_DURATION_MS_NO_CLR(h2c_pkt, value)                      \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 10, 1, value)
+#define REMOTE_WAKE_CTRL_GET_CMD_ID(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 0, 5)
+#define REMOTE_WAKE_CTRL_SET_CMD_ID(h2c_pkt, value)                            \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 0, 5, value)
+#define REMOTE_WAKE_CTRL_SET_CMD_ID_NO_CLR(h2c_pkt, value)                     \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 0, 5, value)
+#define REMOTE_WAKE_CTRL_GET_CLASS(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 5, 3)
+#define REMOTE_WAKE_CTRL_SET_CLASS(h2c_pkt, value)                             \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 5, 3, value)
+#define REMOTE_WAKE_CTRL_SET_CLASS_NO_CLR(h2c_pkt, value)                      \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 5, 3, value)
+#define REMOTE_WAKE_CTRL_GET_REMOTE_WAKE_CTRL_EN(h2c_pkt)                      \
+	GET_H2C_FIELD(h2c_pkt + 0X00, 8, 1)
+#define REMOTE_WAKE_CTRL_SET_REMOTE_WAKE_CTRL_EN(h2c_pkt, value)               \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 8, 1, value)
+#define REMOTE_WAKE_CTRL_SET_REMOTE_WAKE_CTRL_EN_NO_CLR(h2c_pkt, value)        \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 8, 1, value)
+#define REMOTE_WAKE_CTRL_GET_ARP_EN(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 9, 1)
+#define REMOTE_WAKE_CTRL_SET_ARP_EN(h2c_pkt, value)                            \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 9, 1, value)
+#define REMOTE_WAKE_CTRL_SET_ARP_EN_NO_CLR(h2c_pkt, value)                     \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 9, 1, value)
+#define REMOTE_WAKE_CTRL_GET_NDP_EN(h2c_pkt)                                   \
+	GET_H2C_FIELD(h2c_pkt + 0X00, 10, 1)
+#define REMOTE_WAKE_CTRL_SET_NDP_EN(h2c_pkt, value)                            \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 10, 1, value)
+#define REMOTE_WAKE_CTRL_SET_NDP_EN_NO_CLR(h2c_pkt, value)                     \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 10, 1, value)
+#define REMOTE_WAKE_CTRL_GET_GTK_EN(h2c_pkt)                                   \
+	GET_H2C_FIELD(h2c_pkt + 0X00, 11, 1)
+#define REMOTE_WAKE_CTRL_SET_GTK_EN(h2c_pkt, value)                            \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 11, 1, value)
+#define REMOTE_WAKE_CTRL_SET_GTK_EN_NO_CLR(h2c_pkt, value)                     \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 11, 1, value)
+#define REMOTE_WAKE_CTRL_GET_NLO_OFFLOAD_EN(h2c_pkt)                           \
+	GET_H2C_FIELD(h2c_pkt + 0X00, 12, 1)
+#define REMOTE_WAKE_CTRL_SET_NLO_OFFLOAD_EN(h2c_pkt, value)                    \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 12, 1, value)
+#define REMOTE_WAKE_CTRL_SET_NLO_OFFLOAD_EN_NO_CLR(h2c_pkt, value)             \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 12, 1, value)
+#define REMOTE_WAKE_CTRL_GET_REAL_WOW_V1_EN(h2c_pkt)                           \
+	GET_H2C_FIELD(h2c_pkt + 0X00, 13, 1)
+#define REMOTE_WAKE_CTRL_SET_REAL_WOW_V1_EN(h2c_pkt, value)                    \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 13, 1, value)
+#define REMOTE_WAKE_CTRL_SET_REAL_WOW_V1_EN_NO_CLR(h2c_pkt, value)             \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 13, 1, value)
+#define REMOTE_WAKE_CTRL_GET_REAL_WOW_V2_EN(h2c_pkt)                           \
+	GET_H2C_FIELD(h2c_pkt + 0X00, 14, 1)
+#define REMOTE_WAKE_CTRL_SET_REAL_WOW_V2_EN(h2c_pkt, value)                    \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 14, 1, value)
+#define REMOTE_WAKE_CTRL_SET_REAL_WOW_V2_EN_NO_CLR(h2c_pkt, value)             \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 14, 1, value)
+#define REMOTE_WAKE_CTRL_GET_FW_UNICAST(h2c_pkt)                               \
+	GET_H2C_FIELD(h2c_pkt + 0X00, 15, 1)
+#define REMOTE_WAKE_CTRL_SET_FW_UNICAST(h2c_pkt, value)                        \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 15, 1, value)
+#define REMOTE_WAKE_CTRL_SET_FW_UNICAST_NO_CLR(h2c_pkt, value)                 \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 15, 1, value)
+#define REMOTE_WAKE_CTRL_GET_P2P_OFFLOAD_EN(h2c_pkt)                           \
+	GET_H2C_FIELD(h2c_pkt + 0X00, 16, 1)
+#define REMOTE_WAKE_CTRL_SET_P2P_OFFLOAD_EN(h2c_pkt, value)                    \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 16, 1, value)
+#define REMOTE_WAKE_CTRL_SET_P2P_OFFLOAD_EN_NO_CLR(h2c_pkt, value)             \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 16, 1, value)
+#define REMOTE_WAKE_CTRL_GET_RUNTIME_PM_EN(h2c_pkt)                            \
+	GET_H2C_FIELD(h2c_pkt + 0X00, 17, 1)
+#define REMOTE_WAKE_CTRL_SET_RUNTIME_PM_EN(h2c_pkt, value)                     \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 17, 1, value)
+#define REMOTE_WAKE_CTRL_SET_RUNTIME_PM_EN_NO_CLR(h2c_pkt, value)              \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 17, 1, value)
+#define REMOTE_WAKE_CTRL_GET_NET_BIOS_DROP_EN(h2c_pkt)                         \
+	GET_H2C_FIELD(h2c_pkt + 0X00, 18, 1)
+#define REMOTE_WAKE_CTRL_SET_NET_BIOS_DROP_EN(h2c_pkt, value)                  \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 18, 1, value)
+#define REMOTE_WAKE_CTRL_SET_NET_BIOS_DROP_EN_NO_CLR(h2c_pkt, value)           \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 18, 1, value)
+#define REMOTE_WAKE_CTRL_GET_ARP_ACTION(h2c_pkt)                               \
+	GET_H2C_FIELD(h2c_pkt + 0X00, 24, 1)
+#define REMOTE_WAKE_CTRL_SET_ARP_ACTION(h2c_pkt, value)                        \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 24, 1, value)
+#define REMOTE_WAKE_CTRL_SET_ARP_ACTION_NO_CLR(h2c_pkt, value)                 \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 24, 1, value)
+#define REMOTE_WAKE_CTRL_GET_FW_PARSING_UNTIL_WAKEUP(h2c_pkt)                  \
+	GET_H2C_FIELD(h2c_pkt + 0X00, 28, 1)
+#define REMOTE_WAKE_CTRL_SET_FW_PARSING_UNTIL_WAKEUP(h2c_pkt, value)           \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 28, 1, value)
+#define REMOTE_WAKE_CTRL_SET_FW_PARSING_UNTIL_WAKEUP_NO_CLR(h2c_pkt, value)    \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 28, 1, value)
+#define REMOTE_WAKE_CTRL_GET_FW_PARSING_AFTER_WAKEUP(h2c_pkt)                  \
+	GET_H2C_FIELD(h2c_pkt + 0X00, 29, 1)
+#define REMOTE_WAKE_CTRL_SET_FW_PARSING_AFTER_WAKEUP(h2c_pkt, value)           \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 29, 1, value)
+#define REMOTE_WAKE_CTRL_SET_FW_PARSING_AFTER_WAKEUP_NO_CLR(h2c_pkt, value)    \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 29, 1, value)
+#define AOAC_GLOBAL_INFO_GET_CMD_ID(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 0, 5)
+#define AOAC_GLOBAL_INFO_SET_CMD_ID(h2c_pkt, value)                            \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 0, 5, value)
+#define AOAC_GLOBAL_INFO_SET_CMD_ID_NO_CLR(h2c_pkt, value)                     \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 0, 5, value)
+#define AOAC_GLOBAL_INFO_GET_CLASS(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 5, 3)
+#define AOAC_GLOBAL_INFO_SET_CLASS(h2c_pkt, value)                             \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 5, 3, value)
+#define AOAC_GLOBAL_INFO_SET_CLASS_NO_CLR(h2c_pkt, value)                      \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 5, 3, value)
+#define AOAC_GLOBAL_INFO_GET_PAIR_WISE_ENC_ALG(h2c_pkt)                        \
+	GET_H2C_FIELD(h2c_pkt + 0X00, 8, 8)
+#define AOAC_GLOBAL_INFO_SET_PAIR_WISE_ENC_ALG(h2c_pkt, value)                 \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 8, 8, value)
+#define AOAC_GLOBAL_INFO_SET_PAIR_WISE_ENC_ALG_NO_CLR(h2c_pkt, value)          \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 8, 8, value)
+#define AOAC_GLOBAL_INFO_GET_GROUP_ENC_ALG(h2c_pkt)                            \
+	GET_H2C_FIELD(h2c_pkt + 0X00, 16, 8)
+#define AOAC_GLOBAL_INFO_SET_GROUP_ENC_ALG(h2c_pkt, value)                     \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 16, 8, value)
+#define AOAC_GLOBAL_INFO_SET_GROUP_ENC_ALG_NO_CLR(h2c_pkt, value)              \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 16, 8, value)
+#define AOAC_RSVD_PAGE_GET_CMD_ID(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 0, 5)
+#define AOAC_RSVD_PAGE_SET_CMD_ID(h2c_pkt, value)                              \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 0, 5, value)
+#define AOAC_RSVD_PAGE_SET_CMD_ID_NO_CLR(h2c_pkt, value)                       \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 0, 5, value)
+#define AOAC_RSVD_PAGE_GET_CLASS(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 5, 3)
+#define AOAC_RSVD_PAGE_SET_CLASS(h2c_pkt, value)                               \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 5, 3, value)
+#define AOAC_RSVD_PAGE_SET_CLASS_NO_CLR(h2c_pkt, value)                        \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 5, 3, value)
+#define AOAC_RSVD_PAGE_GET_LOC_REMOTE_CTRL_INFO(h2c_pkt)                       \
+	GET_H2C_FIELD(h2c_pkt + 0X00, 8, 8)
+#define AOAC_RSVD_PAGE_SET_LOC_REMOTE_CTRL_INFO(h2c_pkt, value)                \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 8, 8, value)
+#define AOAC_RSVD_PAGE_SET_LOC_REMOTE_CTRL_INFO_NO_CLR(h2c_pkt, value)         \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 8, 8, value)
+#define AOAC_RSVD_PAGE_GET_LOC_ARP_RESPONSE(h2c_pkt)                           \
+	GET_H2C_FIELD(h2c_pkt + 0X00, 16, 8)
+#define AOAC_RSVD_PAGE_SET_LOC_ARP_RESPONSE(h2c_pkt, value)                    \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 16, 8, value)
+#define AOAC_RSVD_PAGE_SET_LOC_ARP_RESPONSE_NO_CLR(h2c_pkt, value)             \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 16, 8, value)
+#define AOAC_RSVD_PAGE_GET_LOC_NEIGHBOR_ADVERTISEMENT(h2c_pkt)                 \
+	GET_H2C_FIELD(h2c_pkt + 0X00, 24, 8)
+#define AOAC_RSVD_PAGE_SET_LOC_NEIGHBOR_ADVERTISEMENT(h2c_pkt, value)          \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 24, 8, value)
+#define AOAC_RSVD_PAGE_SET_LOC_NEIGHBOR_ADVERTISEMENT_NO_CLR(h2c_pkt, value)   \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 24, 8, value)
+#define AOAC_RSVD_PAGE_GET_LOC_GTK_RSP(h2c_pkt)                                \
+	GET_H2C_FIELD(h2c_pkt + 0X04, 0, 8)
+#define AOAC_RSVD_PAGE_SET_LOC_GTK_RSP(h2c_pkt, value)                         \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X04, 0, 8, value)
+#define AOAC_RSVD_PAGE_SET_LOC_GTK_RSP_NO_CLR(h2c_pkt, value)                  \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 0, 8, value)
+#define AOAC_RSVD_PAGE_GET_LOC_GTK_INFO(h2c_pkt)                               \
+	GET_H2C_FIELD(h2c_pkt + 0X04, 8, 8)
+#define AOAC_RSVD_PAGE_SET_LOC_GTK_INFO(h2c_pkt, value)                        \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X04, 8, 8, value)
+#define AOAC_RSVD_PAGE_SET_LOC_GTK_INFO_NO_CLR(h2c_pkt, value)                 \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 8, 8, value)
+#define AOAC_RSVD_PAGE_GET_LOC_GTK_EXT_MEM(h2c_pkt)                            \
+	GET_H2C_FIELD(h2c_pkt + 0X04, 16, 8)
+#define AOAC_RSVD_PAGE_SET_LOC_GTK_EXT_MEM(h2c_pkt, value)                     \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X04, 16, 8, value)
+#define AOAC_RSVD_PAGE_SET_LOC_GTK_EXT_MEM_NO_CLR(h2c_pkt, value)              \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 16, 8, value)
+#define AOAC_RSVD_PAGE_GET_LOC_NDP_INFO(h2c_pkt)                               \
+	GET_H2C_FIELD(h2c_pkt + 0X04, 24, 8)
+#define AOAC_RSVD_PAGE_SET_LOC_NDP_INFO(h2c_pkt, value)                        \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X04, 24, 8, value)
+#define AOAC_RSVD_PAGE_SET_LOC_NDP_INFO_NO_CLR(h2c_pkt, value)                 \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 24, 8, value)
+#define AOAC_RSVD_PAGE2_GET_CMD_ID(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 0, 5)
+#define AOAC_RSVD_PAGE2_SET_CMD_ID(h2c_pkt, value)                             \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 0, 5, value)
+#define AOAC_RSVD_PAGE2_SET_CMD_ID_NO_CLR(h2c_pkt, value)                      \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 0, 5, value)
+#define AOAC_RSVD_PAGE2_GET_CLASS(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 5, 3)
+#define AOAC_RSVD_PAGE2_SET_CLASS(h2c_pkt, value)                              \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 5, 3, value)
+#define AOAC_RSVD_PAGE2_SET_CLASS_NO_CLR(h2c_pkt, value)                       \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 5, 3, value)
+#define AOAC_RSVD_PAGE2_GET_LOC_ROUTER_SOLICATION(h2c_pkt)                     \
+	GET_H2C_FIELD(h2c_pkt + 0X00, 8, 8)
+#define AOAC_RSVD_PAGE2_SET_LOC_ROUTER_SOLICATION(h2c_pkt, value)              \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 8, 8, value)
+#define AOAC_RSVD_PAGE2_SET_LOC_ROUTER_SOLICATION_NO_CLR(h2c_pkt, value)       \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 8, 8, value)
+#define AOAC_RSVD_PAGE2_GET_LOC_BUBBLE_PACKET(h2c_pkt)                         \
+	GET_H2C_FIELD(h2c_pkt + 0X00, 16, 8)
+#define AOAC_RSVD_PAGE2_SET_LOC_BUBBLE_PACKET(h2c_pkt, value)                  \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 16, 8, value)
+#define AOAC_RSVD_PAGE2_SET_LOC_BUBBLE_PACKET_NO_CLR(h2c_pkt, value)           \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 16, 8, value)
+#define AOAC_RSVD_PAGE2_GET_LOC_TEREDO_INFO(h2c_pkt)                           \
+	GET_H2C_FIELD(h2c_pkt + 0X00, 24, 8)
+#define AOAC_RSVD_PAGE2_SET_LOC_TEREDO_INFO(h2c_pkt, value)                    \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 24, 8, value)
+#define AOAC_RSVD_PAGE2_SET_LOC_TEREDO_INFO_NO_CLR(h2c_pkt, value)             \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 24, 8, value)
+#define AOAC_RSVD_PAGE2_GET_LOC_REALWOW_INFO(h2c_pkt)                          \
+	GET_H2C_FIELD(h2c_pkt + 0X04, 0, 8)
+#define AOAC_RSVD_PAGE2_SET_LOC_REALWOW_INFO(h2c_pkt, value)                   \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X04, 0, 8, value)
+#define AOAC_RSVD_PAGE2_SET_LOC_REALWOW_INFO_NO_CLR(h2c_pkt, value)            \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 0, 8, value)
+#define AOAC_RSVD_PAGE2_GET_LOC_KEEP_ALIVE_PKT(h2c_pkt)                        \
+	GET_H2C_FIELD(h2c_pkt + 0X04, 8, 8)
+#define AOAC_RSVD_PAGE2_SET_LOC_KEEP_ALIVE_PKT(h2c_pkt, value)                 \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X04, 8, 8, value)
+#define AOAC_RSVD_PAGE2_SET_LOC_KEEP_ALIVE_PKT_NO_CLR(h2c_pkt, value)          \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 8, 8, value)
+#define AOAC_RSVD_PAGE2_GET_LOC_ACK_PATTERN(h2c_pkt)                           \
+	GET_H2C_FIELD(h2c_pkt + 0X04, 16, 8)
+#define AOAC_RSVD_PAGE2_SET_LOC_ACK_PATTERN(h2c_pkt, value)                    \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X04, 16, 8, value)
+#define AOAC_RSVD_PAGE2_SET_LOC_ACK_PATTERN_NO_CLR(h2c_pkt, value)             \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 16, 8, value)
+#define AOAC_RSVD_PAGE2_GET_LOC_WAKEUP_PATTERN(h2c_pkt)                        \
+	GET_H2C_FIELD(h2c_pkt + 0X04, 24, 8)
+#define AOAC_RSVD_PAGE2_SET_LOC_WAKEUP_PATTERN(h2c_pkt, value)                 \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X04, 24, 8, value)
+#define AOAC_RSVD_PAGE2_SET_LOC_WAKEUP_PATTERN_NO_CLR(h2c_pkt, value)          \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 24, 8, value)
+#define D0_SCAN_OFFLOAD_INFO_GET_CMD_ID(h2c_pkt)                               \
+	GET_H2C_FIELD(h2c_pkt + 0X00, 0, 5)
+#define D0_SCAN_OFFLOAD_INFO_SET_CMD_ID(h2c_pkt, value)                        \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 0, 5, value)
+#define D0_SCAN_OFFLOAD_INFO_SET_CMD_ID_NO_CLR(h2c_pkt, value)                 \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 0, 5, value)
+#define D0_SCAN_OFFLOAD_INFO_GET_CLASS(h2c_pkt)                                \
+	GET_H2C_FIELD(h2c_pkt + 0X00, 5, 3)
+#define D0_SCAN_OFFLOAD_INFO_SET_CLASS(h2c_pkt, value)                         \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 5, 3, value)
+#define D0_SCAN_OFFLOAD_INFO_SET_CLASS_NO_CLR(h2c_pkt, value)                  \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 5, 3, value)
+#define D0_SCAN_OFFLOAD_INFO_GET_LOC_CHANNEL_INFO(h2c_pkt)                     \
+	GET_H2C_FIELD(h2c_pkt + 0X00, 8, 8)
+#define D0_SCAN_OFFLOAD_INFO_SET_LOC_CHANNEL_INFO(h2c_pkt, value)              \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 8, 8, value)
+#define D0_SCAN_OFFLOAD_INFO_SET_LOC_CHANNEL_INFO_NO_CLR(h2c_pkt, value)       \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 8, 8, value)
+#define CHANNEL_SWITCH_OFFLOAD_GET_CMD_ID(h2c_pkt)                             \
+	GET_H2C_FIELD(h2c_pkt + 0X00, 0, 5)
+#define CHANNEL_SWITCH_OFFLOAD_SET_CMD_ID(h2c_pkt, value)                      \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 0, 5, value)
+#define CHANNEL_SWITCH_OFFLOAD_SET_CMD_ID_NO_CLR(h2c_pkt, value)               \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 0, 5, value)
+#define CHANNEL_SWITCH_OFFLOAD_GET_CLASS(h2c_pkt)                              \
+	GET_H2C_FIELD(h2c_pkt + 0X00, 5, 3)
+#define CHANNEL_SWITCH_OFFLOAD_SET_CLASS(h2c_pkt, value)                       \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 5, 3, value)
+#define CHANNEL_SWITCH_OFFLOAD_SET_CLASS_NO_CLR(h2c_pkt, value)                \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 5, 3, value)
+#define CHANNEL_SWITCH_OFFLOAD_GET_CHANNEL_NUM(h2c_pkt)                        \
+	GET_H2C_FIELD(h2c_pkt + 0X00, 8, 8)
+#define CHANNEL_SWITCH_OFFLOAD_SET_CHANNEL_NUM(h2c_pkt, value)                 \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 8, 8, value)
+#define CHANNEL_SWITCH_OFFLOAD_SET_CHANNEL_NUM_NO_CLR(h2c_pkt, value)          \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 8, 8, value)
+#define CHANNEL_SWITCH_OFFLOAD_GET_EN_RFE(h2c_pkt)                             \
+	GET_H2C_FIELD(h2c_pkt + 0X00, 16, 8)
+#define CHANNEL_SWITCH_OFFLOAD_SET_EN_RFE(h2c_pkt, value)                      \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 16, 8, value)
+#define CHANNEL_SWITCH_OFFLOAD_SET_EN_RFE_NO_CLR(h2c_pkt, value)               \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 16, 8, value)
+#define CHANNEL_SWITCH_OFFLOAD_GET_RFE_TYPE(h2c_pkt)                           \
+	GET_H2C_FIELD(h2c_pkt + 0X00, 24, 8)
+#define CHANNEL_SWITCH_OFFLOAD_SET_RFE_TYPE(h2c_pkt, value)                    \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 24, 8, value)
+#define CHANNEL_SWITCH_OFFLOAD_SET_RFE_TYPE_NO_CLR(h2c_pkt, value)             \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 24, 8, value)
+#define AOAC_RSVD_PAGE3_GET_CMD_ID(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 0, 5)
+#define AOAC_RSVD_PAGE3_SET_CMD_ID(h2c_pkt, value)                             \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 0, 5, value)
+#define AOAC_RSVD_PAGE3_SET_CMD_ID_NO_CLR(h2c_pkt, value)                      \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 0, 5, value)
+#define AOAC_RSVD_PAGE3_GET_CLASS(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 5, 3)
+#define AOAC_RSVD_PAGE3_SET_CLASS(h2c_pkt, value)                              \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 5, 3, value)
+#define AOAC_RSVD_PAGE3_SET_CLASS_NO_CLR(h2c_pkt, value)                       \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 5, 3, value)
+#define AOAC_RSVD_PAGE3_GET_LOC_NLO_INFO(h2c_pkt)                              \
+	GET_H2C_FIELD(h2c_pkt + 0X00, 8, 8)
+#define AOAC_RSVD_PAGE3_SET_LOC_NLO_INFO(h2c_pkt, value)                       \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 8, 8, value)
+#define AOAC_RSVD_PAGE3_SET_LOC_NLO_INFO_NO_CLR(h2c_pkt, value)                \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 8, 8, value)
+#define AOAC_RSVD_PAGE3_GET_LOC_AOAC_REPORT(h2c_pkt)                           \
+	GET_H2C_FIELD(h2c_pkt + 0X00, 16, 8)
+#define AOAC_RSVD_PAGE3_SET_LOC_AOAC_REPORT(h2c_pkt, value)                    \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 16, 8, value)
+#define AOAC_RSVD_PAGE3_SET_LOC_AOAC_REPORT_NO_CLR(h2c_pkt, value)             \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 16, 8, value)
+#define DBG_MSG_CTRL_GET_CMD_ID(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 0, 5)
+#define DBG_MSG_CTRL_SET_CMD_ID(h2c_pkt, value)                                \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 0, 5, value)
+#define DBG_MSG_CTRL_SET_CMD_ID_NO_CLR(h2c_pkt, value)                         \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 0, 5, value)
+#define DBG_MSG_CTRL_GET_CLASS(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 5, 3)
+#define DBG_MSG_CTRL_SET_CLASS(h2c_pkt, value)                                 \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 5, 3, value)
+#define DBG_MSG_CTRL_SET_CLASS_NO_CLR(h2c_pkt, value)                          \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 5, 3, value)
+#define DBG_MSG_CTRL_GET_FUN_EN(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 8, 1)
+#define DBG_MSG_CTRL_SET_FUN_EN(h2c_pkt, value)                                \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 8, 1, value)
+#define DBG_MSG_CTRL_SET_FUN_EN_NO_CLR(h2c_pkt, value)                         \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 8, 1, value)
+#define DBG_MSG_CTRL_GET_MODE(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 12, 4)
+#define DBG_MSG_CTRL_SET_MODE(h2c_pkt, value)                                  \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 12, 4, value)
+#define DBG_MSG_CTRL_SET_MODE_NO_CLR(h2c_pkt, value)                           \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 12, 4, value)
+#endif
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/halmac/halmac_original_h2c_nic.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/halmac/halmac_original_h2c_nic.h
--- linux-5.6.3/3rdparty/rtl8821ce/hal/halmac/halmac_original_h2c_nic.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/halmac/halmac_original_h2c_nic.h	2020-04-10 16:35:06.812659881 +0300
@@ -0,0 +1,1143 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ ******************************************************************************/
+
+#ifndef _HAL_ORIGINALH2CFORMAT_H2C_C2H_NIC_H_
+#define _HAL_ORIGINALH2CFORMAT_H2C_C2H_NIC_H_
+#define CMD_ID_ORIGINAL_H2C 0X00
+#define CMD_ID_H2C2H_LB 0X0
+#define CMD_ID_D0_SCAN_OFFLOAD_CTRL 0X06
+#define CMD_ID_RSVD_PAGE 0X0
+#define CMD_ID_MEDIA_STATUS_RPT 0X01
+#define CMD_ID_KEEP_ALIVE 0X03
+#define CMD_ID_DISCONNECT_DECISION 0X04
+#define CMD_ID_AP_OFFLOAD 0X08
+#define CMD_ID_BCN_RSVDPAGE 0X09
+#define CMD_ID_PROBE_RSP_RSVDPAGE 0X0A
+#define CMD_ID_SINGLE_CHANNELSWITCH 0X1C
+#define CMD_ID_SINGLE_CHANNELSWITCH_V2 0X1D
+#define CMD_ID_SET_PWR_MODE 0X00
+#define CMD_ID_PS_TUNING_PARA 0X01
+#define CMD_ID_PS_TUNING_PARA_II 0X02
+#define CMD_ID_PS_LPS_PARA 0X03
+#define CMD_ID_P2P_PS_OFFLOAD 0X04
+#define CMD_ID_PS_SCAN_EN 0X05
+#define CMD_ID_SAP_PS 0X06
+#define CMD_ID_INACTIVE_PS 0X07
+#define CMD_ID_MACID_CFG 0X00
+#define CMD_ID_TXBF 0X01
+#define CMD_ID_RSSI_SETTING 0X02
+#define CMD_ID_AP_REQ_TXRPT 0X03
+#define CMD_ID_INIT_RATE_COLLECTION 0X04
+#define CMD_ID_IQK_OFFLOAD 0X05
+#define CMD_ID_MACID_CFG_3SS 0X06
+#define CMD_ID_RA_PARA_ADJUST 0X07
+#define CMD_ID_WWLAN 0X00
+#define CMD_ID_REMOTE_WAKE_CTRL 0X01
+#define CMD_ID_AOAC_GLOBAL_INFO 0X02
+#define CMD_ID_AOAC_RSVD_PAGE 0X03
+#define CMD_ID_AOAC_RSVD_PAGE2 0X04
+#define CMD_ID_D0_SCAN_OFFLOAD_INFO 0X05
+#define CMD_ID_CHANNEL_SWITCH_OFFLOAD 0X07
+#define CMD_ID_AOAC_RSVD_PAGE3 0X08
+#define CMD_ID_DBG_MSG_CTRL 0X1E
+#define CLASS_ORIGINAL_H2C 0X00
+#define CLASS_H2C2H_LB 0X07
+#define CLASS_D0_SCAN_OFFLOAD_CTRL 0X04
+#define CLASS_RSVD_PAGE 0X0
+#define CLASS_MEDIA_STATUS_RPT 0X0
+#define CLASS_KEEP_ALIVE 0X0
+#define CLASS_DISCONNECT_DECISION 0X0
+#define CLASS_AP_OFFLOAD 0X0
+#define CLASS_BCN_RSVDPAGE 0X0
+#define CLASS_PROBE_RSP_RSVDPAGE 0X0
+#define CLASS_SINGLE_CHANNELSWITCH 0X0
+#define CLASS_SINGLE_CHANNELSWITCH_V2 0X0
+#define CLASS_SET_PWR_MODE 0X01
+#define CLASS_PS_TUNING_PARA 0X01
+#define CLASS_PS_TUNING_PARA_II 0X01
+#define CLASS_PS_LPS_PARA 0X01
+#define CLASS_P2P_PS_OFFLOAD 0X01
+#define CLASS_PS_SCAN_EN 0X1
+#define CLASS_SAP_PS 0X1
+#define CLASS_INACTIVE_PS 0X1
+#define CLASS_MACID_CFG 0X2
+#define CLASS_TXBF 0X2
+#define CLASS_RSSI_SETTING 0X2
+#define CLASS_AP_REQ_TXRPT 0X2
+#define CLASS_INIT_RATE_COLLECTION 0X2
+#define CLASS_IQK_OFFLOAD 0X2
+#define CLASS_MACID_CFG_3SS 0X2
+#define CLASS_RA_PARA_ADJUST 0X02
+#define CLASS_WWLAN 0X4
+#define CLASS_REMOTE_WAKE_CTRL 0X4
+#define CLASS_AOAC_GLOBAL_INFO 0X04
+#define CLASS_AOAC_RSVD_PAGE 0X04
+#define CLASS_AOAC_RSVD_PAGE2 0X04
+#define CLASS_D0_SCAN_OFFLOAD_INFO 0X04
+#define CLASS_CHANNEL_SWITCH_OFFLOAD 0X04
+#define CLASS_AOAC_RSVD_PAGE3 0X04
+#define CLASS_DBG_MSG_CTRL 0X07
+#define ORIGINAL_H2C_GET_CMD_ID(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 0, 5)
+#define ORIGINAL_H2C_SET_CMD_ID(h2c_pkt, value)                                \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 0, 5, value)
+#define ORIGINAL_H2C_GET_CLASS(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 5, 3)
+#define ORIGINAL_H2C_SET_CLASS(h2c_pkt, value)                                 \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 5, 3, value)
+#define H2C2H_LB_GET_CMD_ID(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 0, 5)
+#define H2C2H_LB_SET_CMD_ID(h2c_pkt, value)                                    \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 0, 5, value)
+#define H2C2H_LB_GET_CLASS(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 5, 3)
+#define H2C2H_LB_SET_CLASS(h2c_pkt, value)                                     \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 5, 3, value)
+#define H2C2H_LB_GET_SEQ(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 8, 8)
+#define H2C2H_LB_SET_SEQ(h2c_pkt, value)                                       \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 8, 8, value)
+#define H2C2H_LB_GET_PAYLOAD1(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 16, 16)
+#define H2C2H_LB_SET_PAYLOAD1(h2c_pkt, value)                                  \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 16, 16, value)
+#define H2C2H_LB_GET_PAYLOAD2(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X04, 0, 32)
+#define H2C2H_LB_SET_PAYLOAD2(h2c_pkt, value)                                  \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 0, 32, value)
+#define D0_SCAN_OFFLOAD_CTRL_GET_CMD_ID(h2c_pkt)                               \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 0, 5)
+#define D0_SCAN_OFFLOAD_CTRL_SET_CMD_ID(h2c_pkt, value)                        \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 0, 5, value)
+#define D0_SCAN_OFFLOAD_CTRL_GET_CLASS(h2c_pkt)                                \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 5, 3)
+#define D0_SCAN_OFFLOAD_CTRL_SET_CLASS(h2c_pkt, value)                         \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 5, 3, value)
+#define D0_SCAN_OFFLOAD_CTRL_GET_D0_SCAN_FUN_EN(h2c_pkt)                       \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 8, 1)
+#define D0_SCAN_OFFLOAD_CTRL_SET_D0_SCAN_FUN_EN(h2c_pkt, value)                \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 8, 1, value)
+#define D0_SCAN_OFFLOAD_CTRL_GET_RTD3FUN_EN(h2c_pkt)                           \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 9, 1)
+#define D0_SCAN_OFFLOAD_CTRL_SET_RTD3FUN_EN(h2c_pkt, value)                    \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 9, 1, value)
+#define D0_SCAN_OFFLOAD_CTRL_GET_U3_SCAN_FUN_EN(h2c_pkt)                       \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 10, 1)
+#define D0_SCAN_OFFLOAD_CTRL_SET_U3_SCAN_FUN_EN(h2c_pkt, value)                \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 10, 1, value)
+#define D0_SCAN_OFFLOAD_CTRL_GET_NLO_FUN_EN(h2c_pkt)                           \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 11, 1)
+#define D0_SCAN_OFFLOAD_CTRL_SET_NLO_FUN_EN(h2c_pkt, value)                    \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 11, 1, value)
+#define D0_SCAN_OFFLOAD_CTRL_GET_IPS_DEPENDENT(h2c_pkt)                        \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 12, 1)
+#define D0_SCAN_OFFLOAD_CTRL_SET_IPS_DEPENDENT(h2c_pkt, value)                 \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 12, 1, value)
+#define D0_SCAN_OFFLOAD_CTRL_GET_LOC_PROBE_PACKET(h2c_pkt)                     \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 16, 17)
+#define D0_SCAN_OFFLOAD_CTRL_SET_LOC_PROBE_PACKET(h2c_pkt, value)              \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 16, 17, value)
+#define D0_SCAN_OFFLOAD_CTRL_GET_LOC_SCAN_INFO(h2c_pkt)                        \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 24, 8)
+#define D0_SCAN_OFFLOAD_CTRL_SET_LOC_SCAN_INFO(h2c_pkt, value)                 \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 24, 8, value)
+#define D0_SCAN_OFFLOAD_CTRL_GET_LOC_SSID_INFO(h2c_pkt)                        \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X04, 0, 8)
+#define D0_SCAN_OFFLOAD_CTRL_SET_LOC_SSID_INFO(h2c_pkt, value)                 \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 0, 8, value)
+#define RSVD_PAGE_GET_CMD_ID(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 0, 5)
+#define RSVD_PAGE_SET_CMD_ID(h2c_pkt, value)                                   \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 0, 5, value)
+#define RSVD_PAGE_GET_CLASS(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 5, 3)
+#define RSVD_PAGE_SET_CLASS(h2c_pkt, value)                                    \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 5, 3, value)
+#define RSVD_PAGE_GET_LOC_PROBE_RSP(h2c_pkt)                                   \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 8, 8)
+#define RSVD_PAGE_SET_LOC_PROBE_RSP(h2c_pkt, value)                            \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 8, 8, value)
+#define RSVD_PAGE_GET_LOC_PS_POLL(h2c_pkt)                                     \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 16, 8)
+#define RSVD_PAGE_SET_LOC_PS_POLL(h2c_pkt, value)                              \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 16, 8, value)
+#define RSVD_PAGE_GET_LOC_NULL_DATA(h2c_pkt)                                   \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 24, 8)
+#define RSVD_PAGE_SET_LOC_NULL_DATA(h2c_pkt, value)                            \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 24, 8, value)
+#define RSVD_PAGE_GET_LOC_QOS_NULL(h2c_pkt)                                    \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X04, 0, 8)
+#define RSVD_PAGE_SET_LOC_QOS_NULL(h2c_pkt, value)                             \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 0, 8, value)
+#define RSVD_PAGE_GET_LOC_BT_QOS_NULL(h2c_pkt)                                 \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X04, 8, 8)
+#define RSVD_PAGE_SET_LOC_BT_QOS_NULL(h2c_pkt, value)                          \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 8, 8, value)
+#define RSVD_PAGE_GET_LOC_CTS2SELF(h2c_pkt)                                    \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X04, 16, 8)
+#define RSVD_PAGE_SET_LOC_CTS2SELF(h2c_pkt, value)                             \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 16, 8, value)
+#define RSVD_PAGE_GET_LOC_LTECOEX_QOSNULL(h2c_pkt)                             \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X04, 24, 8)
+#define RSVD_PAGE_SET_LOC_LTECOEX_QOSNULL(h2c_pkt, value)                      \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 24, 8, value)
+#define MEDIA_STATUS_RPT_GET_CMD_ID(h2c_pkt)                                   \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 0, 5)
+#define MEDIA_STATUS_RPT_SET_CMD_ID(h2c_pkt, value)                            \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 0, 5, value)
+#define MEDIA_STATUS_RPT_GET_CLASS(h2c_pkt)                                    \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 5, 3)
+#define MEDIA_STATUS_RPT_SET_CLASS(h2c_pkt, value)                             \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 5, 3, value)
+#define MEDIA_STATUS_RPT_GET_OP_MODE(h2c_pkt)                                  \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 8, 1)
+#define MEDIA_STATUS_RPT_SET_OP_MODE(h2c_pkt, value)                           \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 8, 1, value)
+#define MEDIA_STATUS_RPT_GET_MACID_IN(h2c_pkt)                                 \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 9, 1)
+#define MEDIA_STATUS_RPT_SET_MACID_IN(h2c_pkt, value)                          \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 9, 1, value)
+#define MEDIA_STATUS_RPT_GET_MACID(h2c_pkt)                                    \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 16, 8)
+#define MEDIA_STATUS_RPT_SET_MACID(h2c_pkt, value)                             \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 16, 8, value)
+#define MEDIA_STATUS_RPT_GET_MACID_END(h2c_pkt)                                \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 24, 8)
+#define MEDIA_STATUS_RPT_SET_MACID_END(h2c_pkt, value)                         \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 24, 8, value)
+#define KEEP_ALIVE_GET_CMD_ID(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 0, 5)
+#define KEEP_ALIVE_SET_CMD_ID(h2c_pkt, value)                                  \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 0, 5, value)
+#define KEEP_ALIVE_GET_CLASS(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 5, 3)
+#define KEEP_ALIVE_SET_CLASS(h2c_pkt, value)                                   \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 5, 3, value)
+#define KEEP_ALIVE_GET_ENABLE(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 8, 1)
+#define KEEP_ALIVE_SET_ENABLE(h2c_pkt, value)                                  \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 8, 1, value)
+#define KEEP_ALIVE_GET_ADOPT_USER_SETTING(h2c_pkt)                             \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 9, 1)
+#define KEEP_ALIVE_SET_ADOPT_USER_SETTING(h2c_pkt, value)                      \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 9, 1, value)
+#define KEEP_ALIVE_GET_PKT_TYPE(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 10, 1)
+#define KEEP_ALIVE_SET_PKT_TYPE(h2c_pkt, value)                                \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 10, 1, value)
+#define KEEP_ALIVE_GET_KEEP_ALIVE_CHECK_PERIOD(h2c_pkt)                        \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 16, 8)
+#define KEEP_ALIVE_SET_KEEP_ALIVE_CHECK_PERIOD(h2c_pkt, value)                 \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 16, 8, value)
+#define DISCONNECT_DECISION_GET_CMD_ID(h2c_pkt)                                \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 0, 5)
+#define DISCONNECT_DECISION_SET_CMD_ID(h2c_pkt, value)                         \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 0, 5, value)
+#define DISCONNECT_DECISION_GET_CLASS(h2c_pkt)                                 \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 5, 3)
+#define DISCONNECT_DECISION_SET_CLASS(h2c_pkt, value)                          \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 5, 3, value)
+#define DISCONNECT_DECISION_GET_ENABLE(h2c_pkt)                                \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 8, 1)
+#define DISCONNECT_DECISION_SET_ENABLE(h2c_pkt, value)                         \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 8, 1, value)
+#define DISCONNECT_DECISION_GET_ADOPT_USER_SETTING(h2c_pkt)                    \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 9, 1)
+#define DISCONNECT_DECISION_SET_ADOPT_USER_SETTING(h2c_pkt, value)             \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 9, 1, value)
+#define DISCONNECT_DECISION_GET_TRY_OK_BCN_FAIL_COUNT_EN(h2c_pkt)              \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 10, 1)
+#define DISCONNECT_DECISION_SET_TRY_OK_BCN_FAIL_COUNT_EN(h2c_pkt, value)       \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 10, 1, value)
+#define DISCONNECT_DECISION_GET_DISCONNECT_EN(h2c_pkt)                         \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 11, 1)
+#define DISCONNECT_DECISION_SET_DISCONNECT_EN(h2c_pkt, value)                  \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 11, 1, value)
+#define DISCONNECT_DECISION_GET_DISCON_DECISION_CHECK_PERIOD(h2c_pkt)          \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 16, 8)
+#define DISCONNECT_DECISION_SET_DISCON_DECISION_CHECK_PERIOD(h2c_pkt, value)   \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 16, 8, value)
+#define DISCONNECT_DECISION_GET_TRY_PKT_NUM(h2c_pkt)                           \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 24, 8)
+#define DISCONNECT_DECISION_SET_TRY_PKT_NUM(h2c_pkt, value)                    \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 24, 8, value)
+#define DISCONNECT_DECISION_GET_TRY_OK_BCN_FAIL_COUNT_LIMIT(h2c_pkt)           \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X04, 0, 8)
+#define DISCONNECT_DECISION_SET_TRY_OK_BCN_FAIL_COUNT_LIMIT(h2c_pkt, value)    \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 0, 8, value)
+#define AP_OFFLOAD_GET_CMD_ID(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 0, 5)
+#define AP_OFFLOAD_SET_CMD_ID(h2c_pkt, value)                                  \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 0, 5, value)
+#define AP_OFFLOAD_GET_CLASS(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 5, 3)
+#define AP_OFFLOAD_SET_CLASS(h2c_pkt, value)                                   \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 5, 3, value)
+#define AP_OFFLOAD_GET_ON(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 8, 1)
+#define AP_OFFLOAD_SET_ON(h2c_pkt, value)                                      \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 8, 1, value)
+#define AP_OFFLOAD_GET_CFG_MIFI_PLATFORM(h2c_pkt)                              \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 9, 1)
+#define AP_OFFLOAD_SET_CFG_MIFI_PLATFORM(h2c_pkt, value)                       \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 9, 1, value)
+#define AP_OFFLOAD_GET_LINKED(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 10, 1)
+#define AP_OFFLOAD_SET_LINKED(h2c_pkt, value)                                  \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 10, 1, value)
+#define AP_OFFLOAD_GET_EN_AUTO_WAKE(h2c_pkt)                                   \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 11, 1)
+#define AP_OFFLOAD_SET_EN_AUTO_WAKE(h2c_pkt, value)                            \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 11, 1, value)
+#define AP_OFFLOAD_GET_WAKE_FLAG(h2c_pkt)                                      \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 12, 1)
+#define AP_OFFLOAD_SET_WAKE_FLAG(h2c_pkt, value)                               \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 12, 1, value)
+#define AP_OFFLOAD_GET_HIDDEN_ROOT(h2c_pkt)                                    \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 16, 1)
+#define AP_OFFLOAD_SET_HIDDEN_ROOT(h2c_pkt, value)                             \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 16, 1, value)
+#define AP_OFFLOAD_GET_HIDDEN_VAP1(h2c_pkt)                                    \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 17, 1)
+#define AP_OFFLOAD_SET_HIDDEN_VAP1(h2c_pkt, value)                             \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 17, 1, value)
+#define AP_OFFLOAD_GET_HIDDEN_VAP2(h2c_pkt)                                    \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 18, 1)
+#define AP_OFFLOAD_SET_HIDDEN_VAP2(h2c_pkt, value)                             \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 18, 1, value)
+#define AP_OFFLOAD_GET_HIDDEN_VAP3(h2c_pkt)                                    \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 19, 1)
+#define AP_OFFLOAD_SET_HIDDEN_VAP3(h2c_pkt, value)                             \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 19, 1, value)
+#define AP_OFFLOAD_GET_HIDDEN_VAP4(h2c_pkt)                                    \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 20, 1)
+#define AP_OFFLOAD_SET_HIDDEN_VAP4(h2c_pkt, value)                             \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 20, 1, value)
+#define AP_OFFLOAD_GET_DENYANY_ROOT(h2c_pkt)                                   \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 24, 1)
+#define AP_OFFLOAD_SET_DENYANY_ROOT(h2c_pkt, value)                            \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 24, 1, value)
+#define AP_OFFLOAD_GET_DENYANY_VAP1(h2c_pkt)                                   \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 25, 1)
+#define AP_OFFLOAD_SET_DENYANY_VAP1(h2c_pkt, value)                            \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 25, 1, value)
+#define AP_OFFLOAD_GET_DENYANY_VAP2(h2c_pkt)                                   \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 26, 1)
+#define AP_OFFLOAD_SET_DENYANY_VAP2(h2c_pkt, value)                            \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 26, 1, value)
+#define AP_OFFLOAD_GET_DENYANY_VAP3(h2c_pkt)                                   \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 27, 1)
+#define AP_OFFLOAD_SET_DENYANY_VAP3(h2c_pkt, value)                            \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 27, 1, value)
+#define AP_OFFLOAD_GET_DENYANY_VAP4(h2c_pkt)                                   \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 28, 1)
+#define AP_OFFLOAD_SET_DENYANY_VAP4(h2c_pkt, value)                            \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 28, 1, value)
+#define AP_OFFLOAD_GET_WAIT_TBTT_CNT(h2c_pkt)                                  \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X04, 0, 8)
+#define AP_OFFLOAD_SET_WAIT_TBTT_CNT(h2c_pkt, value)                           \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 0, 8, value)
+#define AP_OFFLOAD_GET_WAKE_TIMEOUT(h2c_pkt)                                   \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X04, 8, 8)
+#define AP_OFFLOAD_SET_WAKE_TIMEOUT(h2c_pkt, value)                            \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 8, 8, value)
+#define AP_OFFLOAD_GET_LEN_IV_PAIR(h2c_pkt)                                    \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X04, 16, 8)
+#define AP_OFFLOAD_SET_LEN_IV_PAIR(h2c_pkt, value)                             \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 16, 8, value)
+#define AP_OFFLOAD_GET_LEN_IV_GRP(h2c_pkt)                                     \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X04, 24, 8)
+#define AP_OFFLOAD_SET_LEN_IV_GRP(h2c_pkt, value)                              \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 24, 8, value)
+#define BCN_RSVDPAGE_GET_CMD_ID(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 0, 5)
+#define BCN_RSVDPAGE_SET_CMD_ID(h2c_pkt, value)                                \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 0, 5, value)
+#define BCN_RSVDPAGE_GET_CLASS(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 5, 3)
+#define BCN_RSVDPAGE_SET_CLASS(h2c_pkt, value)                                 \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 5, 3, value)
+#define BCN_RSVDPAGE_GET_LOC_ROOT(h2c_pkt)                                     \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 8, 8)
+#define BCN_RSVDPAGE_SET_LOC_ROOT(h2c_pkt, value)                              \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 8, 8, value)
+#define BCN_RSVDPAGE_GET_LOC_VAP1(h2c_pkt)                                     \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 16, 8)
+#define BCN_RSVDPAGE_SET_LOC_VAP1(h2c_pkt, value)                              \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 16, 8, value)
+#define BCN_RSVDPAGE_GET_LOC_VAP2(h2c_pkt)                                     \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 24, 8)
+#define BCN_RSVDPAGE_SET_LOC_VAP2(h2c_pkt, value)                              \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 24, 8, value)
+#define BCN_RSVDPAGE_GET_LOC_VAP3(h2c_pkt)                                     \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X04, 0, 8)
+#define BCN_RSVDPAGE_SET_LOC_VAP3(h2c_pkt, value)                              \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 0, 8, value)
+#define BCN_RSVDPAGE_GET_LOC_VAP4(h2c_pkt)                                     \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X04, 8, 8)
+#define BCN_RSVDPAGE_SET_LOC_VAP4(h2c_pkt, value)                              \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 8, 8, value)
+#define PROBE_RSP_RSVDPAGE_GET_CMD_ID(h2c_pkt)                                 \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 0, 5)
+#define PROBE_RSP_RSVDPAGE_SET_CMD_ID(h2c_pkt, value)                          \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 0, 5, value)
+#define PROBE_RSP_RSVDPAGE_GET_CLASS(h2c_pkt)                                  \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 5, 3)
+#define PROBE_RSP_RSVDPAGE_SET_CLASS(h2c_pkt, value)                           \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 5, 3, value)
+#define PROBE_RSP_RSVDPAGE_GET_LOC_ROOT(h2c_pkt)                               \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 8, 8)
+#define PROBE_RSP_RSVDPAGE_SET_LOC_ROOT(h2c_pkt, value)                        \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 8, 8, value)
+#define PROBE_RSP_RSVDPAGE_GET_LOC_VAP1(h2c_pkt)                               \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 16, 8)
+#define PROBE_RSP_RSVDPAGE_SET_LOC_VAP1(h2c_pkt, value)                        \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 16, 8, value)
+#define PROBE_RSP_RSVDPAGE_GET_LOC_VAP2(h2c_pkt)                               \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 24, 8)
+#define PROBE_RSP_RSVDPAGE_SET_LOC_VAP2(h2c_pkt, value)                        \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 24, 8, value)
+#define PROBE_RSP_RSVDPAGE_GET_LOC_VAP3(h2c_pkt)                               \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X04, 0, 8)
+#define PROBE_RSP_RSVDPAGE_SET_LOC_VAP3(h2c_pkt, value)                        \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 0, 8, value)
+#define PROBE_RSP_RSVDPAGE_GET_LOC_VAP4(h2c_pkt)                               \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X04, 8, 8)
+#define PROBE_RSP_RSVDPAGE_SET_LOC_VAP4(h2c_pkt, value)                        \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 8, 8, value)
+#define SINGLE_CHANNELSWITCH_GET_CMD_ID(h2c_pkt)                               \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 0, 5)
+#define SINGLE_CHANNELSWITCH_SET_CMD_ID(h2c_pkt, value)                        \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 0, 5, value)
+#define SINGLE_CHANNELSWITCH_GET_CLASS(h2c_pkt)                                \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 5, 3)
+#define SINGLE_CHANNELSWITCH_SET_CLASS(h2c_pkt, value)                         \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 5, 3, value)
+#define SINGLE_CHANNELSWITCH_GET_CHANNEL_NUM(h2c_pkt)                          \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 8, 8)
+#define SINGLE_CHANNELSWITCH_SET_CHANNEL_NUM(h2c_pkt, value)                   \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 8, 8, value)
+#define SINGLE_CHANNELSWITCH_GET_BW(h2c_pkt)                                   \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 16, 2)
+#define SINGLE_CHANNELSWITCH_SET_BW(h2c_pkt, value)                            \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 16, 2, value)
+#define SINGLE_CHANNELSWITCH_GET_BW40SC(h2c_pkt)                               \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 18, 3)
+#define SINGLE_CHANNELSWITCH_SET_BW40SC(h2c_pkt, value)                        \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 18, 3, value)
+#define SINGLE_CHANNELSWITCH_GET_BW80SC(h2c_pkt)                               \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 21, 3)
+#define SINGLE_CHANNELSWITCH_SET_BW80SC(h2c_pkt, value)                        \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 21, 3, value)
+#define SINGLE_CHANNELSWITCH_GET_RFE_TYPE(h2c_pkt)                             \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 24, 4)
+#define SINGLE_CHANNELSWITCH_SET_RFE_TYPE(h2c_pkt, value)                      \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 24, 4, value)
+#define SINGLE_CHANNELSWITCH_V2_GET_CMD_ID(h2c_pkt)                            \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 0, 5)
+#define SINGLE_CHANNELSWITCH_V2_SET_CMD_ID(h2c_pkt, value)                     \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 0, 5, value)
+#define SINGLE_CHANNELSWITCH_V2_GET_CLASS(h2c_pkt)                             \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 5, 3)
+#define SINGLE_CHANNELSWITCH_V2_SET_CLASS(h2c_pkt, value)                      \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 5, 3, value)
+#define SINGLE_CHANNELSWITCH_V2_GET_CENTRAL_CH(h2c_pkt)                        \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 8, 8)
+#define SINGLE_CHANNELSWITCH_V2_SET_CENTRAL_CH(h2c_pkt, value)                 \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 8, 8, value)
+#define SINGLE_CHANNELSWITCH_V2_GET_PRIMARY_CH_IDX(h2c_pkt)                    \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 16, 4)
+#define SINGLE_CHANNELSWITCH_V2_SET_PRIMARY_CH_IDX(h2c_pkt, value)             \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 16, 4, value)
+#define SINGLE_CHANNELSWITCH_V2_GET_BW(h2c_pkt)                                \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 20, 4)
+#define SINGLE_CHANNELSWITCH_V2_SET_BW(h2c_pkt, value)                         \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 20, 4, value)
+#define SET_PWR_MODE_GET_CMD_ID(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 0, 5)
+#define SET_PWR_MODE_SET_CMD_ID(h2c_pkt, value)                                \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 0, 5, value)
+#define SET_PWR_MODE_GET_CLASS(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 5, 3)
+#define SET_PWR_MODE_SET_CLASS(h2c_pkt, value)                                 \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 5, 3, value)
+#define SET_PWR_MODE_GET_MODE(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 8, 7)
+#define SET_PWR_MODE_SET_MODE(h2c_pkt, value)                                  \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 8, 7, value)
+#define SET_PWR_MODE_GET_CLK_REQUEST(h2c_pkt)                                  \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 15, 1)
+#define SET_PWR_MODE_SET_CLK_REQUEST(h2c_pkt, value)                           \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 15, 1, value)
+#define SET_PWR_MODE_GET_RLBM(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 16, 4)
+#define SET_PWR_MODE_SET_RLBM(h2c_pkt, value)                                  \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 16, 4, value)
+#define SET_PWR_MODE_GET_SMART_PS(h2c_pkt)                                     \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 20, 4)
+#define SET_PWR_MODE_SET_SMART_PS(h2c_pkt, value)                              \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 20, 4, value)
+#define SET_PWR_MODE_GET_AWAKE_INTERVAL(h2c_pkt)                               \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 24, 8)
+#define SET_PWR_MODE_SET_AWAKE_INTERVAL(h2c_pkt, value)                        \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 24, 8, value)
+#define SET_PWR_MODE_GET_B_ALL_QUEUE_UAPSD(h2c_pkt)                            \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X04, 0, 1)
+#define SET_PWR_MODE_SET_B_ALL_QUEUE_UAPSD(h2c_pkt, value)                     \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 0, 1, value)
+#define SET_PWR_MODE_GET_BCN_EARLY_RPT(h2c_pkt)                                \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X04, 2, 1)
+#define SET_PWR_MODE_SET_BCN_EARLY_RPT(h2c_pkt, value)                         \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 2, 1, value)
+#define SET_PWR_MODE_GET_PORT_ID(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X04, 5, 3)
+#define SET_PWR_MODE_SET_PORT_ID(h2c_pkt, value)                               \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 5, 3, value)
+#define SET_PWR_MODE_GET_PWR_STATE(h2c_pkt)                                    \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X04, 8, 8)
+#define SET_PWR_MODE_SET_PWR_STATE(h2c_pkt, value)                             \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 8, 8, value)
+#define SET_PWR_MODE_GET_LOW_POWER_RX_BCN(h2c_pkt)                             \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X04, 16, 1)
+#define SET_PWR_MODE_SET_LOW_POWER_RX_BCN(h2c_pkt, value)                      \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 16, 1, value)
+#define SET_PWR_MODE_GET_ANT_AUTO_SWITCH(h2c_pkt)                              \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X04, 17, 1)
+#define SET_PWR_MODE_SET_ANT_AUTO_SWITCH(h2c_pkt, value)                       \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 17, 1, value)
+#define SET_PWR_MODE_GET_PS_ALLOW_BT_HIGH_PRIORITY(h2c_pkt)                    \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X04, 18, 1)
+#define SET_PWR_MODE_SET_PS_ALLOW_BT_HIGH_PRIORITY(h2c_pkt, value)             \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 18, 1, value)
+#define SET_PWR_MODE_GET_PROTECT_BCN(h2c_pkt)                                  \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X04, 19, 1)
+#define SET_PWR_MODE_SET_PROTECT_BCN(h2c_pkt, value)                           \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 19, 1, value)
+#define SET_PWR_MODE_GET_SILENCE_PERIOD(h2c_pkt)                               \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X04, 20, 1)
+#define SET_PWR_MODE_SET_SILENCE_PERIOD(h2c_pkt, value)                        \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 20, 1, value)
+#define SET_PWR_MODE_GET_FAST_BT_CONNECT(h2c_pkt)                              \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X04, 21, 1)
+#define SET_PWR_MODE_SET_FAST_BT_CONNECT(h2c_pkt, value)                       \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 21, 1, value)
+#define SET_PWR_MODE_GET_TWO_ANTENNA_EN(h2c_pkt)                               \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X04, 22, 1)
+#define SET_PWR_MODE_SET_TWO_ANTENNA_EN(h2c_pkt, value)                        \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 22, 1, value)
+#define SET_PWR_MODE_GET_ADOPT_USER_SETTING(h2c_pkt)                           \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X04, 24, 1)
+#define SET_PWR_MODE_SET_ADOPT_USER_SETTING(h2c_pkt, value)                    \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 24, 1, value)
+#define SET_PWR_MODE_GET_DRV_BCN_EARLY_SHIFT(h2c_pkt)                          \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X04, 25, 3)
+#define SET_PWR_MODE_SET_DRV_BCN_EARLY_SHIFT(h2c_pkt, value)                   \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 25, 3, value)
+#define SET_PWR_MODE_GET_DRV_BCN_EARLY_SHIFT2(h2c_pkt)                         \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X04, 28, 4)
+#define SET_PWR_MODE_SET_DRV_BCN_EARLY_SHIFT2(h2c_pkt, value)                  \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 28, 4, value)
+#define PS_TUNING_PARA_GET_CMD_ID(h2c_pkt)                                     \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 0, 5)
+#define PS_TUNING_PARA_SET_CMD_ID(h2c_pkt, value)                              \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 0, 5, value)
+#define PS_TUNING_PARA_GET_CLASS(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 5, 3)
+#define PS_TUNING_PARA_SET_CLASS(h2c_pkt, value)                               \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 5, 3, value)
+#define PS_TUNING_PARA_GET_BCN_TO_LIMIT(h2c_pkt)                               \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 8, 7)
+#define PS_TUNING_PARA_SET_BCN_TO_LIMIT(h2c_pkt, value)                        \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 8, 7, value)
+#define PS_TUNING_PARA_GET_DTIM_TIME_OUT(h2c_pkt)                              \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 15, 1)
+#define PS_TUNING_PARA_SET_DTIM_TIME_OUT(h2c_pkt, value)                       \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 15, 1, value)
+#define PS_TUNING_PARA_GET_PS_TIME_OUT(h2c_pkt)                                \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 16, 4)
+#define PS_TUNING_PARA_SET_PS_TIME_OUT(h2c_pkt, value)                         \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 16, 4, value)
+#define PS_TUNING_PARA_GET_ADOPT(h2c_pkt)                                      \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 24, 8)
+#define PS_TUNING_PARA_SET_ADOPT(h2c_pkt, value)                               \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 24, 8, value)
+#define PS_TUNING_PARA_II_GET_CMD_ID(h2c_pkt)                                  \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 0, 5)
+#define PS_TUNING_PARA_II_SET_CMD_ID(h2c_pkt, value)                           \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 0, 5, value)
+#define PS_TUNING_PARA_II_GET_CLASS(h2c_pkt)                                   \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 5, 3)
+#define PS_TUNING_PARA_II_SET_CLASS(h2c_pkt, value)                            \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 5, 3, value)
+#define PS_TUNING_PARA_II_GET_BCN_TO_PERIOD(h2c_pkt)                           \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 8, 7)
+#define PS_TUNING_PARA_II_SET_BCN_TO_PERIOD(h2c_pkt, value)                    \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 8, 7, value)
+#define PS_TUNING_PARA_II_GET_ADOPT(h2c_pkt)                                   \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 15, 1)
+#define PS_TUNING_PARA_II_SET_ADOPT(h2c_pkt, value)                            \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 15, 1, value)
+#define PS_TUNING_PARA_II_GET_DRV_EARLY_IVL(h2c_pkt)                           \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 16, 8)
+#define PS_TUNING_PARA_II_SET_DRV_EARLY_IVL(h2c_pkt, value)                    \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 16, 8, value)
+#define PS_LPS_PARA_GET_CMD_ID(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 0, 5)
+#define PS_LPS_PARA_SET_CMD_ID(h2c_pkt, value)                                 \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 0, 5, value)
+#define PS_LPS_PARA_GET_CLASS(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 5, 3)
+#define PS_LPS_PARA_SET_CLASS(h2c_pkt, value)                                  \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 5, 3, value)
+#define PS_LPS_PARA_GET_LPS_CONTROL(h2c_pkt)                                   \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 8, 8)
+#define PS_LPS_PARA_SET_LPS_CONTROL(h2c_pkt, value)                            \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 8, 8, value)
+#define P2P_PS_OFFLOAD_GET_CMD_ID(h2c_pkt)                                     \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 0, 5)
+#define P2P_PS_OFFLOAD_SET_CMD_ID(h2c_pkt, value)                              \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 0, 5, value)
+#define P2P_PS_OFFLOAD_GET_CLASS(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 5, 3)
+#define P2P_PS_OFFLOAD_SET_CLASS(h2c_pkt, value)                               \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 5, 3, value)
+#define P2P_PS_OFFLOAD_GET_OFFLOAD_EN(h2c_pkt)                                 \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 8, 1)
+#define P2P_PS_OFFLOAD_SET_OFFLOAD_EN(h2c_pkt, value)                          \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 8, 1, value)
+#define P2P_PS_OFFLOAD_GET_ROLE(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 9, 1)
+#define P2P_PS_OFFLOAD_SET_ROLE(h2c_pkt, value)                                \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 9, 1, value)
+#define P2P_PS_OFFLOAD_GET_CTWINDOW_EN(h2c_pkt)                                \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 10, 1)
+#define P2P_PS_OFFLOAD_SET_CTWINDOW_EN(h2c_pkt, value)                         \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 10, 1, value)
+#define P2P_PS_OFFLOAD_GET_NOA0_EN(h2c_pkt)                                    \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 11, 1)
+#define P2P_PS_OFFLOAD_SET_NOA0_EN(h2c_pkt, value)                             \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 11, 1, value)
+#define P2P_PS_OFFLOAD_GET_NOA1_EN(h2c_pkt)                                    \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 12, 1)
+#define P2P_PS_OFFLOAD_SET_NOA1_EN(h2c_pkt, value)                             \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 12, 1, value)
+#define P2P_PS_OFFLOAD_GET_ALL_STA_SLEEP(h2c_pkt)                              \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 13, 1)
+#define P2P_PS_OFFLOAD_SET_ALL_STA_SLEEP(h2c_pkt, value)                       \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 13, 1, value)
+#define P2P_PS_OFFLOAD_GET_DISCOVERY(h2c_pkt)                                  \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 14, 1)
+#define P2P_PS_OFFLOAD_SET_DISCOVERY(h2c_pkt, value)                           \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 14, 1, value)
+#define PS_SCAN_EN_GET_CMD_ID(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 0, 5)
+#define PS_SCAN_EN_SET_CMD_ID(h2c_pkt, value)                                  \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 0, 5, value)
+#define PS_SCAN_EN_GET_CLASS(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 5, 3)
+#define PS_SCAN_EN_SET_CLASS(h2c_pkt, value)                                   \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 5, 3, value)
+#define PS_SCAN_EN_GET_ENABLE(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 8, 1)
+#define PS_SCAN_EN_SET_ENABLE(h2c_pkt, value)                                  \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 8, 1, value)
+#define SAP_PS_GET_CMD_ID(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 0, 5)
+#define SAP_PS_SET_CMD_ID(h2c_pkt, value)                                      \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 0, 5, value)
+#define SAP_PS_GET_CLASS(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 5, 3)
+#define SAP_PS_SET_CLASS(h2c_pkt, value)                                       \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 5, 3, value)
+#define SAP_PS_GET_ENABLE(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 8, 1)
+#define SAP_PS_SET_ENABLE(h2c_pkt, value)                                      \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 8, 1, value)
+#define SAP_PS_GET_EN_PS(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 9, 1)
+#define SAP_PS_SET_EN_PS(h2c_pkt, value)                                       \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 9, 1, value)
+#define SAP_PS_GET_EN_LP_RX(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 10, 1)
+#define SAP_PS_SET_EN_LP_RX(h2c_pkt, value)                                    \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 10, 1, value)
+#define SAP_PS_GET_MANUAL_32K(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 11, 1)
+#define SAP_PS_SET_MANUAL_32K(h2c_pkt, value)                                  \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 11, 1, value)
+#define SAP_PS_GET_DURATION(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 16, 8)
+#define SAP_PS_SET_DURATION(h2c_pkt, value)                                    \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 16, 8, value)
+#define INACTIVE_PS_GET_CMD_ID(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 0, 5)
+#define INACTIVE_PS_SET_CMD_ID(h2c_pkt, value)                                 \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 0, 5, value)
+#define INACTIVE_PS_GET_CLASS(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 5, 3)
+#define INACTIVE_PS_SET_CLASS(h2c_pkt, value)                                  \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 5, 3, value)
+#define INACTIVE_PS_GET_ENABLE(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 8, 1)
+#define INACTIVE_PS_SET_ENABLE(h2c_pkt, value)                                 \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 8, 1, value)
+#define INACTIVE_PS_GET_IGNORE_PS_CONDITION(h2c_pkt)                           \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 9, 1)
+#define INACTIVE_PS_SET_IGNORE_PS_CONDITION(h2c_pkt, value)                    \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 9, 1, value)
+#define INACTIVE_PS_GET_FREQUENCY(h2c_pkt)                                     \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 16, 8)
+#define INACTIVE_PS_SET_FREQUENCY(h2c_pkt, value)                              \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 16, 8, value)
+#define INACTIVE_PS_GET_DURATION(h2c_pkt)                                      \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 24, 8)
+#define INACTIVE_PS_SET_DURATION(h2c_pkt, value)                               \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 24, 8, value)
+#define MACID_CFG_GET_CMD_ID(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 0, 5)
+#define MACID_CFG_SET_CMD_ID(h2c_pkt, value)                                   \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 0, 5, value)
+#define MACID_CFG_GET_CLASS(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 5, 3)
+#define MACID_CFG_SET_CLASS(h2c_pkt, value)                                    \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 5, 3, value)
+#define MACID_CFG_GET_MAC_ID(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 8, 8)
+#define MACID_CFG_SET_MAC_ID(h2c_pkt, value)                                   \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 8, 8, value)
+#define MACID_CFG_GET_RATE_ID(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 16, 5)
+#define MACID_CFG_SET_RATE_ID(h2c_pkt, value)                                  \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 16, 5, value)
+#define MACID_CFG_GET_INIT_RATE_LV(h2c_pkt)                                    \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 21, 2)
+#define MACID_CFG_SET_INIT_RATE_LV(h2c_pkt, value)                             \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 21, 2, value)
+#define MACID_CFG_GET_SGI(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 23, 1)
+#define MACID_CFG_SET_SGI(h2c_pkt, value)                                      \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 23, 1, value)
+#define MACID_CFG_GET_BW(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 24, 2)
+#define MACID_CFG_SET_BW(h2c_pkt, value)                                       \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 24, 2, value)
+#define MACID_CFG_GET_LDPC_CAP(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 26, 1)
+#define MACID_CFG_SET_LDPC_CAP(h2c_pkt, value)                                 \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 26, 1, value)
+#define MACID_CFG_GET_NO_UPDATE(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 27, 1)
+#define MACID_CFG_SET_NO_UPDATE(h2c_pkt, value)                                \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 27, 1, value)
+#define MACID_CFG_GET_WHT_EN(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 28, 2)
+#define MACID_CFG_SET_WHT_EN(h2c_pkt, value)                                   \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 28, 2, value)
+#define MACID_CFG_GET_DISPT(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 30, 1)
+#define MACID_CFG_SET_DISPT(h2c_pkt, value)                                    \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 30, 1, value)
+#define MACID_CFG_GET_DISRA(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 31, 1)
+#define MACID_CFG_SET_DISRA(h2c_pkt, value)                                    \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 31, 1, value)
+#define MACID_CFG_GET_RATE_MASK7_0(h2c_pkt)                                    \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X04, 0, 8)
+#define MACID_CFG_SET_RATE_MASK7_0(h2c_pkt, value)                             \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 0, 8, value)
+#define MACID_CFG_GET_RATE_MASK15_8(h2c_pkt)                                   \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X04, 8, 8)
+#define MACID_CFG_SET_RATE_MASK15_8(h2c_pkt, value)                            \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 8, 8, value)
+#define MACID_CFG_GET_RATE_MASK23_16(h2c_pkt)                                  \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X04, 16, 8)
+#define MACID_CFG_SET_RATE_MASK23_16(h2c_pkt, value)                           \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 16, 8, value)
+#define MACID_CFG_GET_RATE_MASK31_24(h2c_pkt)                                  \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X04, 24, 8)
+#define MACID_CFG_SET_RATE_MASK31_24(h2c_pkt, value)                           \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 24, 8, value)
+#define TXBF_GET_CMD_ID(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 0, 5)
+#define TXBF_SET_CMD_ID(h2c_pkt, value)                                        \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 0, 5, value)
+#define TXBF_GET_CLASS(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 5, 3)
+#define TXBF_SET_CLASS(h2c_pkt, value)                                         \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 5, 3, value)
+#define TXBF_GET_NDPA0_HEAD_PAGE(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 8, 8)
+#define TXBF_SET_NDPA0_HEAD_PAGE(h2c_pkt, value)                               \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 8, 8, value)
+#define TXBF_GET_NDPA1_HEAD_PAGE(h2c_pkt)                                      \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 16, 8)
+#define TXBF_SET_NDPA1_HEAD_PAGE(h2c_pkt, value)                               \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 16, 8, value)
+#define TXBF_GET_PERIOD_0(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 24, 8)
+#define TXBF_SET_PERIOD_0(h2c_pkt, value)                                      \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 24, 8, value)
+#define RSSI_SETTING_GET_CMD_ID(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 0, 5)
+#define RSSI_SETTING_SET_CMD_ID(h2c_pkt, value)                                \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 0, 5, value)
+#define RSSI_SETTING_GET_CLASS(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 5, 3)
+#define RSSI_SETTING_SET_CLASS(h2c_pkt, value)                                 \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 5, 3, value)
+#define RSSI_SETTING_GET_MAC_ID(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 8, 8)
+#define RSSI_SETTING_SET_MAC_ID(h2c_pkt, value)                                \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 8, 8, value)
+#define RSSI_SETTING_GET_RSSI(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 24, 7)
+#define RSSI_SETTING_SET_RSSI(h2c_pkt, value)                                  \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 24, 7, value)
+#define RSSI_SETTING_GET_RA_INFO(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X04, 0, 8)
+#define RSSI_SETTING_SET_RA_INFO(h2c_pkt, value)                               \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 0, 8, value)
+#define AP_REQ_TXRPT_GET_CMD_ID(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 0, 5)
+#define AP_REQ_TXRPT_SET_CMD_ID(h2c_pkt, value)                                \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 0, 5, value)
+#define AP_REQ_TXRPT_GET_CLASS(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 5, 3)
+#define AP_REQ_TXRPT_SET_CLASS(h2c_pkt, value)                                 \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 5, 3, value)
+#define AP_REQ_TXRPT_GET_STA1_MACID(h2c_pkt)                                   \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 8, 8)
+#define AP_REQ_TXRPT_SET_STA1_MACID(h2c_pkt, value)                            \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 8, 8, value)
+#define AP_REQ_TXRPT_GET_STA2_MACID(h2c_pkt)                                   \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 16, 8)
+#define AP_REQ_TXRPT_SET_STA2_MACID(h2c_pkt, value)                            \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 16, 8, value)
+#define AP_REQ_TXRPT_GET_RTY_OK_TOTAL(h2c_pkt)                                 \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 24, 1)
+#define AP_REQ_TXRPT_SET_RTY_OK_TOTAL(h2c_pkt, value)                          \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 24, 1, value)
+#define AP_REQ_TXRPT_GET_RTY_CNT_MACID(h2c_pkt)                                \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 25, 1)
+#define AP_REQ_TXRPT_SET_RTY_CNT_MACID(h2c_pkt, value)                         \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 25, 1, value)
+#define INIT_RATE_COLLECTION_GET_CMD_ID(h2c_pkt)                               \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 0, 5)
+#define INIT_RATE_COLLECTION_SET_CMD_ID(h2c_pkt, value)                        \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 0, 5, value)
+#define INIT_RATE_COLLECTION_GET_CLASS(h2c_pkt)                                \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 5, 3)
+#define INIT_RATE_COLLECTION_SET_CLASS(h2c_pkt, value)                         \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 5, 3, value)
+#define INIT_RATE_COLLECTION_GET_STA1_MACID(h2c_pkt)                           \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 8, 8)
+#define INIT_RATE_COLLECTION_SET_STA1_MACID(h2c_pkt, value)                    \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 8, 8, value)
+#define INIT_RATE_COLLECTION_GET_STA2_MACID(h2c_pkt)                           \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 16, 8)
+#define INIT_RATE_COLLECTION_SET_STA2_MACID(h2c_pkt, value)                    \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 16, 8, value)
+#define INIT_RATE_COLLECTION_GET_STA3_MACID(h2c_pkt)                           \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 24, 8)
+#define INIT_RATE_COLLECTION_SET_STA3_MACID(h2c_pkt, value)                    \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 24, 8, value)
+#define INIT_RATE_COLLECTION_GET_STA4_MACID(h2c_pkt)                           \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X04, 0, 8)
+#define INIT_RATE_COLLECTION_SET_STA4_MACID(h2c_pkt, value)                    \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 0, 8, value)
+#define INIT_RATE_COLLECTION_GET_STA5_MACID(h2c_pkt)                           \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X04, 8, 8)
+#define INIT_RATE_COLLECTION_SET_STA5_MACID(h2c_pkt, value)                    \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 8, 8, value)
+#define INIT_RATE_COLLECTION_GET_STA6_MACID(h2c_pkt)                           \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X04, 16, 8)
+#define INIT_RATE_COLLECTION_SET_STA6_MACID(h2c_pkt, value)                    \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 16, 8, value)
+#define INIT_RATE_COLLECTION_GET_STA7_MACID(h2c_pkt)                           \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X04, 24, 8)
+#define INIT_RATE_COLLECTION_SET_STA7_MACID(h2c_pkt, value)                    \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 24, 8, value)
+#define IQK_OFFLOAD_GET_CMD_ID(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 0, 5)
+#define IQK_OFFLOAD_SET_CMD_ID(h2c_pkt, value)                                 \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 0, 5, value)
+#define IQK_OFFLOAD_GET_CLASS(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 5, 3)
+#define IQK_OFFLOAD_SET_CLASS(h2c_pkt, value)                                  \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 5, 3, value)
+#define IQK_OFFLOAD_GET_CHANNEL(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 8, 8)
+#define IQK_OFFLOAD_SET_CHANNEL(h2c_pkt, value)                                \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 8, 8, value)
+#define IQK_OFFLOAD_GET_BWBAND(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 16, 8)
+#define IQK_OFFLOAD_SET_BWBAND(h2c_pkt, value)                                 \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 16, 8, value)
+#define IQK_OFFLOAD_GET_EXTPALNA(h2c_pkt)                                      \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 24, 8)
+#define IQK_OFFLOAD_SET_EXTPALNA(h2c_pkt, value)                               \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 24, 8, value)
+#define MACID_CFG_3SS_GET_CMD_ID(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 0, 5)
+#define MACID_CFG_3SS_SET_CMD_ID(h2c_pkt, value)                               \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 0, 5, value)
+#define MACID_CFG_3SS_GET_CLASS(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 5, 3)
+#define MACID_CFG_3SS_SET_CLASS(h2c_pkt, value)                                \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 5, 3, value)
+#define MACID_CFG_3SS_GET_MACID(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 8, 8)
+#define MACID_CFG_3SS_SET_MACID(h2c_pkt, value)                                \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 8, 8, value)
+#define MACID_CFG_3SS_GET_RATE_MASK_39_32(h2c_pkt)                             \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X04, 0, 8)
+#define MACID_CFG_3SS_SET_RATE_MASK_39_32(h2c_pkt, value)                      \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 0, 8, value)
+#define MACID_CFG_3SS_GET_RATE_MASK_47_40(h2c_pkt)                             \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X04, 8, 8)
+#define MACID_CFG_3SS_SET_RATE_MASK_47_40(h2c_pkt, value)                      \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 8, 8, value)
+#define RA_PARA_ADJUST_GET_CMD_ID(h2c_pkt)                                     \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 0, 5)
+#define RA_PARA_ADJUST_SET_CMD_ID(h2c_pkt, value)                              \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 0, 5, value)
+#define RA_PARA_ADJUST_GET_CLASS(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 5, 3)
+#define RA_PARA_ADJUST_SET_CLASS(h2c_pkt, value)                               \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 5, 3, value)
+#define RA_PARA_ADJUST_GET_MAC_ID(h2c_pkt)                                     \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 8, 8)
+#define RA_PARA_ADJUST_SET_MAC_ID(h2c_pkt, value)                              \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 8, 8, value)
+#define RA_PARA_ADJUST_GET_PARAMETER_INDEX(h2c_pkt)                            \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 16, 8)
+#define RA_PARA_ADJUST_SET_PARAMETER_INDEX(h2c_pkt, value)                     \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 16, 8, value)
+#define RA_PARA_ADJUST_GET_RATE_ID(h2c_pkt)                                    \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 24, 8)
+#define RA_PARA_ADJUST_SET_RATE_ID(h2c_pkt, value)                             \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 24, 8, value)
+#define RA_PARA_ADJUST_GET_VALUE_BYTE0(h2c_pkt)                                \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X04, 0, 8)
+#define RA_PARA_ADJUST_SET_VALUE_BYTE0(h2c_pkt, value)                         \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 0, 8, value)
+#define RA_PARA_ADJUST_GET_VALUE_BYTE1(h2c_pkt)                                \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X04, 8, 8)
+#define RA_PARA_ADJUST_SET_VALUE_BYTE1(h2c_pkt, value)                         \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 8, 8, value)
+#define RA_PARA_ADJUST_GET_ASK_FW_FOR_FW_PARA(h2c_pkt)                         \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X04, 16, 8)
+#define RA_PARA_ADJUST_SET_ASK_FW_FOR_FW_PARA(h2c_pkt, value)                  \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 16, 8, value)
+#define WWLAN_GET_CMD_ID(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 0, 5)
+#define WWLAN_SET_CMD_ID(h2c_pkt, value)                                       \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 0, 5, value)
+#define WWLAN_GET_CLASS(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 5, 3)
+#define WWLAN_SET_CLASS(h2c_pkt, value)                                        \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 5, 3, value)
+#define WWLAN_GET_FUNC_EN(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 8, 1)
+#define WWLAN_SET_FUNC_EN(h2c_pkt, value)                                      \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 8, 1, value)
+#define WWLAN_GET_PATTERM_MAT_EN(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 9, 1)
+#define WWLAN_SET_PATTERM_MAT_EN(h2c_pkt, value)                               \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 9, 1, value)
+#define WWLAN_GET_MAGIC_PKT_EN(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 10, 1)
+#define WWLAN_SET_MAGIC_PKT_EN(h2c_pkt, value)                                 \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 10, 1, value)
+#define WWLAN_GET_UNICAST_WAKEUP_EN(h2c_pkt)                                   \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 11, 1)
+#define WWLAN_SET_UNICAST_WAKEUP_EN(h2c_pkt, value)                            \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 11, 1, value)
+#define WWLAN_GET_ALL_PKT_DROP(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 12, 1)
+#define WWLAN_SET_ALL_PKT_DROP(h2c_pkt, value)                                 \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 12, 1, value)
+#define WWLAN_GET_GPIO_ACTIVE(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 13, 1)
+#define WWLAN_SET_GPIO_ACTIVE(h2c_pkt, value)                                  \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 13, 1, value)
+#define WWLAN_GET_REKEY_WAKEUP_EN(h2c_pkt)                                     \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 14, 1)
+#define WWLAN_SET_REKEY_WAKEUP_EN(h2c_pkt, value)                              \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 14, 1, value)
+#define WWLAN_GET_DEAUTH_WAKEUP_EN(h2c_pkt)                                    \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 15, 1)
+#define WWLAN_SET_DEAUTH_WAKEUP_EN(h2c_pkt, value)                             \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 15, 1, value)
+#define WWLAN_GET_GPIO_NUM(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 16, 7)
+#define WWLAN_SET_GPIO_NUM(h2c_pkt, value)                                     \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 16, 7, value)
+#define WWLAN_GET_DATAPIN_WAKEUP_EN(h2c_pkt)                                   \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 23, 1)
+#define WWLAN_SET_DATAPIN_WAKEUP_EN(h2c_pkt, value)                            \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 23, 1, value)
+#define WWLAN_GET_GPIO_DURATION(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 24, 8)
+#define WWLAN_SET_GPIO_DURATION(h2c_pkt, value)                                \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 24, 8, value)
+#define WWLAN_GET_GPIO_PLUS_EN(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X04, 0, 1)
+#define WWLAN_SET_GPIO_PLUS_EN(h2c_pkt, value)                                 \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 0, 1, value)
+#define WWLAN_GET_GPIO_PULSE_COUNT(h2c_pkt)                                    \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X04, 1, 7)
+#define WWLAN_SET_GPIO_PULSE_COUNT(h2c_pkt, value)                             \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 1, 7, value)
+#define WWLAN_GET_DISABLE_UPHY(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X04, 8, 1)
+#define WWLAN_SET_DISABLE_UPHY(h2c_pkt, value)                                 \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 8, 1, value)
+#define WWLAN_GET_HST2DEV_EN(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X04, 9, 1)
+#define WWLAN_SET_HST2DEV_EN(h2c_pkt, value)                                   \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 9, 1, value)
+#define WWLAN_GET_GPIO_DURATION_MS(h2c_pkt)                                    \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X04, 10, 1)
+#define WWLAN_SET_GPIO_DURATION_MS(h2c_pkt, value)                             \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 10, 1, value)
+#define REMOTE_WAKE_CTRL_GET_CMD_ID(h2c_pkt)                                   \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 0, 5)
+#define REMOTE_WAKE_CTRL_SET_CMD_ID(h2c_pkt, value)                            \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 0, 5, value)
+#define REMOTE_WAKE_CTRL_GET_CLASS(h2c_pkt)                                    \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 5, 3)
+#define REMOTE_WAKE_CTRL_SET_CLASS(h2c_pkt, value)                             \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 5, 3, value)
+#define REMOTE_WAKE_CTRL_GET_REMOTE_WAKE_CTRL_EN(h2c_pkt)                      \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 8, 1)
+#define REMOTE_WAKE_CTRL_SET_REMOTE_WAKE_CTRL_EN(h2c_pkt, value)               \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 8, 1, value)
+#define REMOTE_WAKE_CTRL_GET_ARP_EN(h2c_pkt)                                   \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 9, 1)
+#define REMOTE_WAKE_CTRL_SET_ARP_EN(h2c_pkt, value)                            \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 9, 1, value)
+#define REMOTE_WAKE_CTRL_GET_NDP_EN(h2c_pkt)                                   \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 10, 1)
+#define REMOTE_WAKE_CTRL_SET_NDP_EN(h2c_pkt, value)                            \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 10, 1, value)
+#define REMOTE_WAKE_CTRL_GET_GTK_EN(h2c_pkt)                                   \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 11, 1)
+#define REMOTE_WAKE_CTRL_SET_GTK_EN(h2c_pkt, value)                            \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 11, 1, value)
+#define REMOTE_WAKE_CTRL_GET_NLO_OFFLOAD_EN(h2c_pkt)                           \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 12, 1)
+#define REMOTE_WAKE_CTRL_SET_NLO_OFFLOAD_EN(h2c_pkt, value)                    \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 12, 1, value)
+#define REMOTE_WAKE_CTRL_GET_REAL_WOW_V1_EN(h2c_pkt)                           \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 13, 1)
+#define REMOTE_WAKE_CTRL_SET_REAL_WOW_V1_EN(h2c_pkt, value)                    \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 13, 1, value)
+#define REMOTE_WAKE_CTRL_GET_REAL_WOW_V2_EN(h2c_pkt)                           \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 14, 1)
+#define REMOTE_WAKE_CTRL_SET_REAL_WOW_V2_EN(h2c_pkt, value)                    \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 14, 1, value)
+#define REMOTE_WAKE_CTRL_GET_FW_UNICAST(h2c_pkt)                               \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 15, 1)
+#define REMOTE_WAKE_CTRL_SET_FW_UNICAST(h2c_pkt, value)                        \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 15, 1, value)
+#define REMOTE_WAKE_CTRL_GET_P2P_OFFLOAD_EN(h2c_pkt)                           \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 16, 1)
+#define REMOTE_WAKE_CTRL_SET_P2P_OFFLOAD_EN(h2c_pkt, value)                    \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 16, 1, value)
+#define REMOTE_WAKE_CTRL_GET_RUNTIME_PM_EN(h2c_pkt)                            \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 17, 1)
+#define REMOTE_WAKE_CTRL_SET_RUNTIME_PM_EN(h2c_pkt, value)                     \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 17, 1, value)
+#define REMOTE_WAKE_CTRL_GET_NET_BIOS_DROP_EN(h2c_pkt)                         \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 18, 1)
+#define REMOTE_WAKE_CTRL_SET_NET_BIOS_DROP_EN(h2c_pkt, value)                  \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 18, 1, value)
+#define REMOTE_WAKE_CTRL_GET_ARP_ACTION(h2c_pkt)                               \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 24, 1)
+#define REMOTE_WAKE_CTRL_SET_ARP_ACTION(h2c_pkt, value)                        \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 24, 1, value)
+#define REMOTE_WAKE_CTRL_GET_FW_PARSING_UNTIL_WAKEUP(h2c_pkt)                  \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 28, 1)
+#define REMOTE_WAKE_CTRL_SET_FW_PARSING_UNTIL_WAKEUP(h2c_pkt, value)           \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 28, 1, value)
+#define REMOTE_WAKE_CTRL_GET_FW_PARSING_AFTER_WAKEUP(h2c_pkt)                  \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 29, 1)
+#define REMOTE_WAKE_CTRL_SET_FW_PARSING_AFTER_WAKEUP(h2c_pkt, value)           \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 29, 1, value)
+#define AOAC_GLOBAL_INFO_GET_CMD_ID(h2c_pkt)                                   \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 0, 5)
+#define AOAC_GLOBAL_INFO_SET_CMD_ID(h2c_pkt, value)                            \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 0, 5, value)
+#define AOAC_GLOBAL_INFO_GET_CLASS(h2c_pkt)                                    \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 5, 3)
+#define AOAC_GLOBAL_INFO_SET_CLASS(h2c_pkt, value)                             \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 5, 3, value)
+#define AOAC_GLOBAL_INFO_GET_PAIR_WISE_ENC_ALG(h2c_pkt)                        \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 8, 8)
+#define AOAC_GLOBAL_INFO_SET_PAIR_WISE_ENC_ALG(h2c_pkt, value)                 \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 8, 8, value)
+#define AOAC_GLOBAL_INFO_GET_GROUP_ENC_ALG(h2c_pkt)                            \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 16, 8)
+#define AOAC_GLOBAL_INFO_SET_GROUP_ENC_ALG(h2c_pkt, value)                     \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 16, 8, value)
+#define AOAC_RSVD_PAGE_GET_CMD_ID(h2c_pkt)                                     \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 0, 5)
+#define AOAC_RSVD_PAGE_SET_CMD_ID(h2c_pkt, value)                              \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 0, 5, value)
+#define AOAC_RSVD_PAGE_GET_CLASS(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 5, 3)
+#define AOAC_RSVD_PAGE_SET_CLASS(h2c_pkt, value)                               \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 5, 3, value)
+#define AOAC_RSVD_PAGE_GET_LOC_REMOTE_CTRL_INFO(h2c_pkt)                       \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 8, 8)
+#define AOAC_RSVD_PAGE_SET_LOC_REMOTE_CTRL_INFO(h2c_pkt, value)                \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 8, 8, value)
+#define AOAC_RSVD_PAGE_GET_LOC_ARP_RESPONSE(h2c_pkt)                           \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 16, 8)
+#define AOAC_RSVD_PAGE_SET_LOC_ARP_RESPONSE(h2c_pkt, value)                    \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 16, 8, value)
+#define AOAC_RSVD_PAGE_GET_LOC_NEIGHBOR_ADVERTISEMENT(h2c_pkt)                 \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 24, 8)
+#define AOAC_RSVD_PAGE_SET_LOC_NEIGHBOR_ADVERTISEMENT(h2c_pkt, value)          \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 24, 8, value)
+#define AOAC_RSVD_PAGE_GET_LOC_GTK_RSP(h2c_pkt)                                \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X04, 0, 8)
+#define AOAC_RSVD_PAGE_SET_LOC_GTK_RSP(h2c_pkt, value)                         \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 0, 8, value)
+#define AOAC_RSVD_PAGE_GET_LOC_GTK_INFO(h2c_pkt)                               \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X04, 8, 8)
+#define AOAC_RSVD_PAGE_SET_LOC_GTK_INFO(h2c_pkt, value)                        \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 8, 8, value)
+#define AOAC_RSVD_PAGE_GET_LOC_GTK_EXT_MEM(h2c_pkt)                            \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X04, 16, 8)
+#define AOAC_RSVD_PAGE_SET_LOC_GTK_EXT_MEM(h2c_pkt, value)                     \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 16, 8, value)
+#define AOAC_RSVD_PAGE_GET_LOC_NDP_INFO(h2c_pkt)                               \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X04, 24, 8)
+#define AOAC_RSVD_PAGE_SET_LOC_NDP_INFO(h2c_pkt, value)                        \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 24, 8, value)
+#define AOAC_RSVD_PAGE2_GET_CMD_ID(h2c_pkt)                                    \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 0, 5)
+#define AOAC_RSVD_PAGE2_SET_CMD_ID(h2c_pkt, value)                             \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 0, 5, value)
+#define AOAC_RSVD_PAGE2_GET_CLASS(h2c_pkt)                                     \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 5, 3)
+#define AOAC_RSVD_PAGE2_SET_CLASS(h2c_pkt, value)                              \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 5, 3, value)
+#define AOAC_RSVD_PAGE2_GET_LOC_ROUTER_SOLICATION(h2c_pkt)                     \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 8, 8)
+#define AOAC_RSVD_PAGE2_SET_LOC_ROUTER_SOLICATION(h2c_pkt, value)              \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 8, 8, value)
+#define AOAC_RSVD_PAGE2_GET_LOC_BUBBLE_PACKET(h2c_pkt)                         \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 16, 8)
+#define AOAC_RSVD_PAGE2_SET_LOC_BUBBLE_PACKET(h2c_pkt, value)                  \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 16, 8, value)
+#define AOAC_RSVD_PAGE2_GET_LOC_TEREDO_INFO(h2c_pkt)                           \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 24, 8)
+#define AOAC_RSVD_PAGE2_SET_LOC_TEREDO_INFO(h2c_pkt, value)                    \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 24, 8, value)
+#define AOAC_RSVD_PAGE2_GET_LOC_REALWOW_INFO(h2c_pkt)                          \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X04, 0, 8)
+#define AOAC_RSVD_PAGE2_SET_LOC_REALWOW_INFO(h2c_pkt, value)                   \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 0, 8, value)
+#define AOAC_RSVD_PAGE2_GET_LOC_KEEP_ALIVE_PKT(h2c_pkt)                        \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X04, 8, 8)
+#define AOAC_RSVD_PAGE2_SET_LOC_KEEP_ALIVE_PKT(h2c_pkt, value)                 \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 8, 8, value)
+#define AOAC_RSVD_PAGE2_GET_LOC_ACK_PATTERN(h2c_pkt)                           \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X04, 16, 8)
+#define AOAC_RSVD_PAGE2_SET_LOC_ACK_PATTERN(h2c_pkt, value)                    \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 16, 8, value)
+#define AOAC_RSVD_PAGE2_GET_LOC_WAKEUP_PATTERN(h2c_pkt)                        \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X04, 24, 8)
+#define AOAC_RSVD_PAGE2_SET_LOC_WAKEUP_PATTERN(h2c_pkt, value)                 \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 24, 8, value)
+#define D0_SCAN_OFFLOAD_INFO_GET_CMD_ID(h2c_pkt)                               \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 0, 5)
+#define D0_SCAN_OFFLOAD_INFO_SET_CMD_ID(h2c_pkt, value)                        \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 0, 5, value)
+#define D0_SCAN_OFFLOAD_INFO_GET_CLASS(h2c_pkt)                                \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 5, 3)
+#define D0_SCAN_OFFLOAD_INFO_SET_CLASS(h2c_pkt, value)                         \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 5, 3, value)
+#define D0_SCAN_OFFLOAD_INFO_GET_LOC_CHANNEL_INFO(h2c_pkt)                     \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 8, 8)
+#define D0_SCAN_OFFLOAD_INFO_SET_LOC_CHANNEL_INFO(h2c_pkt, value)              \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 8, 8, value)
+#define CHANNEL_SWITCH_OFFLOAD_GET_CMD_ID(h2c_pkt)                             \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 0, 5)
+#define CHANNEL_SWITCH_OFFLOAD_SET_CMD_ID(h2c_pkt, value)                      \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 0, 5, value)
+#define CHANNEL_SWITCH_OFFLOAD_GET_CLASS(h2c_pkt)                              \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 5, 3)
+#define CHANNEL_SWITCH_OFFLOAD_SET_CLASS(h2c_pkt, value)                       \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 5, 3, value)
+#define CHANNEL_SWITCH_OFFLOAD_GET_CHANNEL_NUM(h2c_pkt)                        \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 8, 8)
+#define CHANNEL_SWITCH_OFFLOAD_SET_CHANNEL_NUM(h2c_pkt, value)                 \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 8, 8, value)
+#define CHANNEL_SWITCH_OFFLOAD_GET_EN_RFE(h2c_pkt)                             \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 16, 8)
+#define CHANNEL_SWITCH_OFFLOAD_SET_EN_RFE(h2c_pkt, value)                      \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 16, 8, value)
+#define CHANNEL_SWITCH_OFFLOAD_GET_RFE_TYPE(h2c_pkt)                           \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 24, 8)
+#define CHANNEL_SWITCH_OFFLOAD_SET_RFE_TYPE(h2c_pkt, value)                    \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 24, 8, value)
+#define AOAC_RSVD_PAGE3_GET_CMD_ID(h2c_pkt)                                    \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 0, 5)
+#define AOAC_RSVD_PAGE3_SET_CMD_ID(h2c_pkt, value)                             \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 0, 5, value)
+#define AOAC_RSVD_PAGE3_GET_CLASS(h2c_pkt)                                     \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 5, 3)
+#define AOAC_RSVD_PAGE3_SET_CLASS(h2c_pkt, value)                              \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 5, 3, value)
+#define AOAC_RSVD_PAGE3_GET_LOC_NLO_INFO(h2c_pkt)                              \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 8, 8)
+#define AOAC_RSVD_PAGE3_SET_LOC_NLO_INFO(h2c_pkt, value)                       \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 8, 8, value)
+#define AOAC_RSVD_PAGE3_GET_LOC_AOAC_REPORT(h2c_pkt)                           \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 16, 8)
+#define AOAC_RSVD_PAGE3_SET_LOC_AOAC_REPORT(h2c_pkt, value)                    \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 16, 8, value)
+#define DBG_MSG_CTRL_GET_CMD_ID(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 0, 5)
+#define DBG_MSG_CTRL_SET_CMD_ID(h2c_pkt, value)                                \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 0, 5, value)
+#define DBG_MSG_CTRL_GET_CLASS(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 5, 3)
+#define DBG_MSG_CTRL_SET_CLASS(h2c_pkt, value)                                 \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 5, 3, value)
+#define DBG_MSG_CTRL_GET_FUN_EN(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 8, 1)
+#define DBG_MSG_CTRL_SET_FUN_EN(h2c_pkt, value)                                \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 8, 1, value)
+#define DBG_MSG_CTRL_GET_MODE(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 12, 4)
+#define DBG_MSG_CTRL_SET_MODE(h2c_pkt, value)                                  \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 12, 4, value)
+#endif
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/halmac/halmac_pcie_reg.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/halmac/halmac_pcie_reg.h
--- linux-5.6.3/3rdparty/rtl8821ce/hal/halmac/halmac_pcie_reg.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/halmac/halmac_pcie_reg.h	2020-04-10 16:35:06.812659881 +0300
@@ -0,0 +1,36 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ ******************************************************************************/
+
+#ifndef __HALMAC_PCIE_REG_H__
+#define __HALMAC_PCIE_REG_H__
+
+/* PCIE PHY register */
+#define RAC_CTRL_PPR		0x00
+#define RAC_SET_PPR		0x20
+#define RAC_TRG_PPR		0x21
+
+/* PCIE CFG register */
+#define PCIE_L1_BACKDOOR		0x719
+#define PCIE_ASPM_CTRL			0x70F
+
+/* PCIE MAC register */
+#define LINK_CTRL2_REG_OFFSET		0xA0
+#define GEN2_CTRL_OFFSET		0x80C
+#define LINK_STATUS_REG_OFFSET		0x82
+
+#define PCIE_GEN1_SPEED			0x01
+#define PCIE_GEN2_SPEED			0x02
+
+#endif/* __HALMAC_PCIE_REG_H__ */
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/halmac/halmac_pwr_seq_cmd.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/halmac/halmac_pwr_seq_cmd.h
--- linux-5.6.3/3rdparty/rtl8821ce/hal/halmac/halmac_pwr_seq_cmd.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/halmac/halmac_pwr_seq_cmd.h	2020-04-10 16:35:06.812659881 +0300
@@ -0,0 +1,98 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ ******************************************************************************/
+
+#ifndef HALMAC_POWER_SEQUENCE_CMD
+#define HALMAC_POWER_SEQUENCE_CMD
+
+#include "halmac_2_platform.h"
+
+#define HALMAC_PWR_POLLING_CNT 20000
+
+/* The value of cmd : 4 bits */
+
+/* offset : the read register offset
+ * msk : the mask of the read value
+ * value : N/A, left by 0
+ * Note : dirver shall implement this function by read & msk
+ */
+#define	HALMAC_PWR_CMD_READ		0x00
+/* offset: the read register offset
+ * msk: the mask of the write bits
+ * value: write value
+ * Note: driver shall implement this cmd by read & msk after write
+ */
+#define	HALMAC_PWR_CMD_WRITE	0x01
+/* offset: the read register offset
+ * msk: the mask of the polled value
+ * value: the value to be polled, masked by the msd field.
+ * Note: driver shall implement this cmd by
+ * do{
+ * if( (Read(offset) & msk) == (value & msk) )
+ * break;
+ * } while(not timeout);
+ */
+#define	HALMAC_PWR_CMD_POLLING	0x02
+/* offset: the value to delay
+ * msk: N/A
+ * value: the unit of delay, 0: us, 1: ms
+ */
+#define	HALMAC_PWR_CMD_DELAY	0x03
+/* offset: N/A
+ * msk: N/A
+ * value: N/A
+ */
+#define	HALMAC_PWR_CMD_END	0x04
+
+/* The value of base : 4 bits */
+
+/* define the base address of each block */
+#define   HALMAC_PWR_ADDR_MAC	0x00
+#define   HALMAC_PWR_ADDR_USB	0x01
+#define   HALMAC_PWR_ADDR_PCIE	0x02
+#define   HALMAC_PWR_ADDR_SDIO	0x03
+
+/* The value of interface_msk : 4 bits */
+#define	HALMAC_PWR_INTF_SDIO_MSK	BIT(0)
+#define	HALMAC_PWR_INTF_USB_MSK		BIT(1)
+#define	HALMAC_PWR_INTF_PCI_MSK		BIT(2)
+#define	HALMAC_PWR_INTF_ALL_MSK		(BIT(0) | BIT(1) | BIT(2) | BIT(3))
+
+/* The value of cut_msk : 8 bits */
+#define	HALMAC_PWR_CUT_TESTCHIP_MSK		BIT(0)
+#define	HALMAC_PWR_CUT_A_MSK			BIT(1)
+#define	HALMAC_PWR_CUT_B_MSK			BIT(2)
+#define	HALMAC_PWR_CUT_C_MSK			BIT(3)
+#define	HALMAC_PWR_CUT_D_MSK			BIT(4)
+#define	HALMAC_PWR_CUT_E_MSK			BIT(5)
+#define	HALMAC_PWR_CUT_F_MSK			BIT(6)
+#define	HALMAC_PWR_CUT_G_MSK			BIT(7)
+#define	HALMAC_PWR_CUT_ALL_MSK			0xFF
+
+enum halmac_pwrseq_cmd_delay_unit {
+	HALMAC_PWR_DELAY_US,
+	HALMAC_PWR_DELAY_MS,
+};
+
+struct halmac_wlan_pwr_cfg {
+	u16 offset;
+	u8 cut_msk;
+	u8 interface_msk;
+	u8 base:4;
+	u8 cmd:4;
+	u8 msk;
+	u8 value;
+};
+
+#endif
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/halmac/halmac_reg2.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/halmac/halmac_reg2.h
--- linux-5.6.3/3rdparty/rtl8821ce/hal/halmac/halmac_reg2.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/halmac/halmac_reg2.h	2020-04-10 16:35:06.816660067 +0300
@@ -0,0 +1,8184 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ ******************************************************************************/
+
+#ifndef __HALMAC_COM_REG_H__
+#define __HALMAC_COM_REG_H__
+
+#include "halmac_hw_cfg.h"
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_SYS_ISO_CTRL 0x0000
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+#define REG_SDIO_TX_CTRL 0x10250000
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_SYS_FUNC_EN 0x0002
+#define REG_SYS_PW_CTRL 0x0004
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_SDIO_CMD11_VOL_SWITCH 0x10250004
+#define REG_SDIO_CTRL 0x10250005
+#define REG_SDIO_DRIVING 0x10250006
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_SYS_CLK_CTRL 0x0008
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_SDIO_MONITOR 0x10250008
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_SYS_EEPROM_CTRL 0x000A
+#define REG_EE_VPD 0x000C
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_SDIO_MONITOR_2 0x1025000C
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_SYS_SWR_CTRL1 0x0010
+#define REG_SYS_SWR_CTRL2 0x0014
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+#define REG_SDIO_HIMR 0x10250014
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_SYS_SWR_CTRL3 0x0018
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+#define REG_SDIO_HISR 0x10250018
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_RSV_CTRL 0x001C
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+#define REG_SDIO_RX_REQ_LEN 0x1025001C
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8881A_SUPPORT)
+
+#define REG_RF_CTRL 0x001F
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+#define REG_RF0_CTRL 0x001F
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+#define REG_SDIO_FREE_TXPG_SEQ_V1 0x1025001F
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_AFE_LDO_CTRL 0x0020
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+#define REG_SDIO_FREE_TXPG 0x10250020
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_AFE_CTRL1 0x0024
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+#define REG_SDIO_FREE_TXPG2 0x10250024
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_AFE_CTRL2 0x0028
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+#define REG_SDIO_OQT_FREE_TXPG_V1 0x10250028
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_ANAPARSW_POW_MAC 0x0028
+#define REG_ANAPARLDO_POW_MAC 0x0029
+#define REG_ANAPAR_POW_MAC 0x002A
+#define REG_ANAPAR_POW_XTAL 0x002B
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_AFE_CTRL3 0x002C
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_ANAPARLDO_MAC 0x002C
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_SDIO_TXPKT_EMPTY 0x1025002C
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_EFUSE_CTRL 0x0030
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+#define REG_SDIO_HTSFR_INFO 0x10250030
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_LDO_EFUSE_CTRL 0x0034
+#define REG_PWR_OPTION_CTRL 0x0038
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+#define REG_SDIO_HCPWM1_V2 0x10250038
+#define REG_SDIO_HCPWM2_V2 0x1025003A
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_CAL_TIMER 0x003C
+#define REG_ACLK_MON 0x003E
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_GPIO_MUXCFG_2 0x003F
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_GPIO_MUXCFG 0x0040
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+#define REG_SDIO_INDIRECT_REG_CFG 0x10250040
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_GPIO_PIN_CTRL 0x0044
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+#define REG_SDIO_INDIRECT_REG_DATA 0x10250044
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_GPIO_INTM 0x0048
+#define REG_LED_CFG 0x004C
+#define REG_FSIMR 0x0050
+#define REG_FSISR 0x0054
+#define REG_HSIMR 0x0058
+#define REG_HSISR 0x005C
+#define REG_GPIO_EXT_CTRL 0x0060
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+#define REG_SDIO_H2C 0x10250060
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_PAD_CTRL1 0x0064
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+#define REG_SDIO_C2H 0x10250064
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_WL_BT_PWR_CTRL 0x0068
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8881A_SUPPORT)
+
+#define REG_SDM_DEBUG 0x006C
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+#define REG_GSSR 0x006C
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8881A_SUPPORT)
+
+#define REG_SYS_SDIO_CTRL 0x0070
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+#define REG_SYS_CLKR 0x0070
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_HCI_OPT_CTRL 0x0074
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_AFE_CTRL4 0x0078
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_HCI_BG_CTRL 0x0078
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+#define REG_AFE_XTAL_CTRL_EXT 0x0078
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_HCI_LDO_CTRL 0x007A
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_LDO_SWR_CTRL 0x007C
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_8051FW_CTRL 0x0080
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+#define REG_MCUFW_CTRL 0x0080
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+#define REG_SDIO_HRPWM1 0x10250080
+#define REG_SDIO_HRPWM2 0x10250082
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_MCU_TST_CFG 0x0084
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_SDIO_HPS_CLKR 0x10250084
+#define REG_SDIO_BUS_CTRL 0x10250085
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+#define REG_SDIO_HSUS_CTRL 0x10250086
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_HMEBOX_E0_E1 0x0088
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_SDIO_RESPONSE_TIMER 0x10250088
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+#define REG_SDIO_CMD_CRC 0x1025008A
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_HMEBOX_E2_E3 0x008C
+#define REG_WLLPS_CTRL 0x0090
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_SDIO_HSISR 0x10250090
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_SDIO_HSIMR 0x10250091
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+
+#define REG_AFE_CTRL5 0x0094
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_GPIO_DEBOUNCE_CTRL 0x0098
+#define REG_RPWM2 0x009C
+#define REG_SYSON_FSM_MON 0x00A0
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+
+#define REG_AFE_CTRL6 0x00A4
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_PMC_DBG_CTRL1 0x00A8
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+
+#define REG_AFE_CTRL7 0x00AC
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_HIMR0 0x00B0
+#define REG_HISR0 0x00B4
+#define REG_HIMR1 0x00B8
+#define REG_HISR1 0x00BC
+#define REG_DBG_PORT_SEL 0x00C0
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_SDIO_DIOERR_RPT 0x102500C0
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+
+#define REG_SDIO_ERR_RPT 0x102500C0
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+#define REG_SDIO_CMD_ERRCNT 0x102500C2
+#define REG_SDIO_DATA_ERRCNT 0x102500C3
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_PAD_CTRL2 0x00C4
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+#define REG_SDIO_CMD_ERR_CONTENT 0x102500C4
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+#define REG_MEM_RMC 0x00C8
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+#define REG_SDIO_CRC_ERR_IDX 0x102500C9
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_SDIO_DATA_CRC 0x102500CA
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+
+#define REG_SDIO_DATA_REPLY_TIME 0x102500CB
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_PMC_DBG_CTRL2 0x00CC
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_SDIO_TRANS_FIFO_STATUS 0x102500CC
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_BIST_CTRL 0x00D0
+#define REG_BIST_RPT 0x00D4
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_MEM_CTRL 0x00D8
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+
+#define REG_AFE_CTRL8 0x00DC
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+#define REG_WLAN_DBG 0x00DC
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define REG_SYN_RFC_CTRL 0x00DC
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_USB_SIE_INTF 0x00E0
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+#define REG_SYS_PINMUX 0x00E0
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_PCIE_MIO_INTF 0x00E4
+#define REG_PCIE_MIO_INTD 0x00E8
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_WLRF1 0x00EC
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+#define REG_HPON_FSM 0x00EC
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_SYS_CFG1 0x00F0
+#define REG_SYS_STATUS1 0x00F4
+#define REG_SYS_STATUS2 0x00F8
+#define REG_SYS_CFG2 0x00FC
+#define REG_CR 0x0100
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_PG_SIZE 0x0104
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_PKT_BUFF_ACCESS_CTRL 0x0106
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_TSF_CLK_STATE 0x0108
+#define REG_TXDMA_PQ_MAP 0x010C
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_TRXFF_BNDY 0x0114
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+#define REG_RXFF_BNDY_V1 0x0114
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_PTA_I2C_MBOX 0x0118
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT)
+
+#define REG_FF_STATUS 0x0118
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8881A_SUPPORT)
+
+#define REG_RXFF_PTR 0x011C
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_RXFF_BNDY 0x011C
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_FEIMR 0x0120
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_FE1IMR 0x0120
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_FEISR 0x0124
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_FE1ISR 0x0124
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_CPWM 0x012C
+#define REG_FWIMR 0x0130
+#define REG_FWISR 0x0134
+#define REG_FTIMR 0x0138
+#define REG_FTISR 0x013C
+#define REG_PKTBUF_DBG_CTRL 0x0140
+#define REG_PKTBUF_DBG_DATA_L 0x0144
+#define REG_PKTBUF_DBG_DATA_H 0x0148
+#define REG_CPWM2 0x014C
+#define REG_TC0_CTRL 0x0150
+#define REG_TC1_CTRL 0x0154
+#define REG_TC2_CTRL 0x0158
+#define REG_TC3_CTRL 0x015C
+#define REG_TC4_CTRL 0x0160
+#define REG_TCUNIT_BASE 0x0164
+#define REG_TC5_CTRL 0x0168
+#define REG_TC6_CTRL 0x016C
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT || \
+     HALMAC_8881A_SUPPORT)
+
+#define REG_MBIST_FAIL 0x0170
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+#define REG_MBIST_DRF_FAIL 0x0170
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_MBIST_START_PAUSE 0x0174
+#define REG_MBIST_DONE 0x0178
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_MBIST_ROM_CRC_DATA 0x017C
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+#define REG_MBIST_NRML_FAIL 0x017C
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT)
+
+#define REG_MBIST_FAIL_NRML 0x017C
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_MBIST_READ_BIST_RPT 0x017C
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_AES_DECRPT_DATA 0x0180
+#define REG_AES_DECRPT_CFG 0x0184
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+#define REG_MBIST_READ_BIST_RPT_V1 0x0188
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_HIOE_CTRL 0x0188
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+#define REG_MACCLKFRQ 0x018C
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_HIOE_CFG_FILE 0x018C
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_TMETER 0x0190
+#define REG_OSC_32K_CTRL 0x0194
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_32K_CAL_REG1 0x0198
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+#define REG_32K_CAL_REG0 0x0198
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_C2HEVT 0x01A0
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_C2HEVT_1 0x01A4
+#define REG_C2HEVT_2 0x01A8
+#define REG_C2HEVT_3 0x01AC
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+#define REG_MISC_CTRL_V1 0x01B0
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT)
+
+#define REG_TC7_CTRL 0x01B0
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define REG_RXDESC_BUFF_RPTR 0x01B0
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT)
+
+#define REG_TC8_CTRL 0x01B4
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define REG_RXDESC_BUFF_WPTR 0x01B4
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_SW_DEFINED_PAGE1 0x01B8
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_SW_DEFINED_PAGE2 0x01BC
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_MCUTST_I 0x01C0
+#define REG_MCUTST_II 0x01C4
+#define REG_FMETHR 0x01C8
+#define REG_HMETFR 0x01CC
+#define REG_HMEBOX0 0x01D0
+#define REG_HMEBOX1 0x01D4
+#define REG_HMEBOX2 0x01D8
+#define REG_HMEBOX3 0x01DC
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT || \
+     HALMAC_8881A_SUPPORT)
+
+#define REG_LLT_INIT 0x01E0
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+#define REG_LLT_IND_ACCESS 0x01E0
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define REG_RXDESC_BUFF_BNDY 0x01E0
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_GENTST 0x01E4
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT)
+
+#define REG_LLT_INIT_ADDR 0x01E4
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_BB_ACCESS_CTRL 0x01E8
+#define REG_BB_ACCESS_DATA 0x01EC
+#define REG_HMEBOX_E0 0x01F0
+#define REG_HMEBOX_E1 0x01F4
+#define REG_HMEBOX_E2 0x01F8
+#define REG_HMEBOX_E3 0x01FC
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_RQPN_CTRL_HLPQ 0x0200
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_FIFOPAGE_CTRL_1 0x0200
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define REG_BCN_CTRL_0 0x0200
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_FIFOPAGE_INFO 0x0204
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_FIFOPAGE_CTRL_2 0x0204
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define REG_BCN_CTRL_1 0x0204
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_DWBCN0_CTRL 0x0208
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_AUTO_LLT_V1 0x0208
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_TXDMA_OFFSET_CHK 0x020C
+#define REG_TXDMA_STATUS 0x0210
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_RQPN_NPQ 0x0214
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_TX_DMA_DBG 0x0214
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_TQPNT1 0x0218
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define REG_DMA_RQPN_INFO_PUB 0x0218
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_TQPNT2 0x021C
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define REG_RQPN_CTRL_2_V1 0x021C
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_TDE_DEBUG 0x0220
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_TQPNT3 0x0220
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define REG_BCN_CTRL_2 0x0220
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_AUTO_LLT 0x0224
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_TQPNT4 0x0224
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_DWBCN1_CTRL 0x0228
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_RQPN_CTRL_1 0x0228
+#define REG_RQPN_CTRL_2 0x022C
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+#define REG_RQPN_EXQ1_EXQ2 0x0230
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_FIFOPAGE_INFO_1 0x0230
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define REG_TXPKTNUM_0 0x0230
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+#define REG_TQPNT3_V1 0x0234
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_FIFOPAGE_INFO_2 0x0234
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define REG_TXPKTNUM_1 0x0234
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_FIFOPAGE_INFO_3 0x0238
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define REG_TXPKTNUM_2 0x0238
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_FIFOPAGE_INFO_4 0x023C
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define REG_TXPKTNUM_3 0x023C
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_FIFOPAGE_INFO_5 0x0240
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define REG_TX_AGG_ALIGN 0x0240
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_H2C_HEAD 0x0244
+#define REG_H2C_TAIL 0x0248
+#define REG_H2C_READ_ADDR 0x024C
+#define REG_H2C_WR_ADDR 0x0250
+#define REG_H2C_INFO 0x0254
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+#define REG_TQPNT5 0x0260
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define REG_DMA_OQT_0 0x0260
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+#define REG_TQPNT6 0x0264
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define REG_DMA_OQT_1 0x0264
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+#define REG_FIFOPAGE_INFO_6 0x0268
+#define REG_FIFOPAGE_INFO_7 0x026C
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_PGSUB_CNT 0x026C
+#define REG_PGSUB_H 0x0270
+#define REG_PGSUB_N 0x0274
+#define REG_PGSUB_L 0x0278
+#define REG_PGSUB_E 0x027C
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_RXDMA_AGG_PG_TH 0x0280
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_RXPKT_NUM 0x0284
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define REG_RXDMA_CTRL 0x0284
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_RXDMA_STATUS 0x0288
+#define REG_RXDMA_DPR 0x028C
+#define REG_RXDMA_MODE 0x0290
+#define REG_C2H_PKT 0x0294
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_FWFF_C2H 0x0298
+#define REG_FWFF_CTRL 0x029C
+#define REG_FWFF_PKT_INFO 0x02A0
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+#define REG_FC2H_INFO 0x02A4
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define REG_FWFF_PKT_INFO2 0x02A4
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_RXPKTNUM 0x02B0
+#define REG_RXPKTNUM_TH 0x02B4
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define REG_FW_UPD_RXDES_RDPTR 0x02B8
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_FW_MSG1 0x02E0
+#define REG_FW_MSG2 0x02E4
+#define REG_FW_MSG3 0x02E8
+#define REG_FW_MSG4 0x02EC
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_PCIE_CTRL 0x0300
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+#define REG_HCI_CTRL 0x0300
+
+#endif
+
+#if (HALMAC_8881A_SUPPORT)
+
+#define REG_LX_CTRL1 0x0300
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_INT_MIG 0x0304
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define REG_ACH_CTRL 0x0304
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_BCNQ_TXBD_DESA 0x0308
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define REG_HIQ_CTRL 0x0308
+#define REG_INT_MIG_V1 0x030C
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_MGQ_TXBD_DESA 0x0310
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define REG_P0MGQ_TXBD_DESA_L 0x0310
+#define REG_P0MGQ_TXBD_DESA_H 0x0314
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_VOQ_TXBD_DESA 0x0318
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define REG_ACH0_TXBD_DESA_L 0x0318
+#define REG_ACH0_TXBD_DESA_H 0x031C
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_VIQ_TXBD_DESA 0x0320
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define REG_ACH1_TXBD_DESA_L 0x0320
+#define REG_ACH1_TXBD_DESA_H 0x0324
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_BEQ_TXBD_DESA 0x0328
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define REG_ACH2_TXBD_DESA_L 0x0328
+#define REG_ACH2_TXBD_DESA_H 0x032C
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_BKQ_TXBD_DESA 0x0330
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define REG_ACH3_TXBD_DESA_L 0x0330
+#define REG_ACH3_TXBD_DESA_H 0x0334
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_RXQ_RXBD_DESA 0x0338
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define REG_P0RXQ_RXBD_DESA_L 0x0338
+#define REG_P0RXQ_RXBD_DESA_H 0x033C
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_HI0Q_TXBD_DESA 0x0340
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define REG_P0BCNQ_TXBD_DESA_L 0x0340
+#define REG_P0BCNQ_TXBD_DESA_H 0x0344
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_HI1Q_TXBD_DESA 0x0348
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define REG_FWCMDQ_TXBD_DESA_L 0x0348
+#define REG_FWCMDQ_TXBD_DESA_H 0x034C
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_HI2Q_TXBD_DESA 0x0350
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define REG_PCIE_HRPWM1_HCPWM1_DCPU 0x0354
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_HI3Q_TXBD_DESA 0x0358
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define REG_P0_MPRT_BCNQ_TXBD_DESA_L 0x0358
+#define REG_P0_MPRT_BCNQ_TXBD_DESA_H 0x035C
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_HI4Q_TXBD_DESA 0x0360
+#define REG_HI5Q_TXBD_DESA 0x0368
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define REG_P0_MPRT_BCNQ_TXRXBD_NUM 0x036C
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_HI6Q_TXBD_DESA 0x0370
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define REG_BD_RWPTR_CLR2 0x0370
+#define REG_BD_RWPTR_CLR3 0x0374
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_HI7Q_TXBD_DESA 0x0378
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define REG_P0MGQ_RXQ_TXRXBD_NUM 0x0378
+#define REG_CHNL_DMA_CFG 0x037C
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_MGQ_TXBD_NUM 0x0380
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define REG_FWCMDQ_TXBD_NUM 0x0380
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_RX_RXBD_NUM 0x0382
+#define REG_VOQ_TXBD_NUM 0x0384
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define REG_ACH0_ACH1_TXBD_NUM 0x0384
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_VIQ_TXBD_NUM 0x0386
+#define REG_BEQ_TXBD_NUM 0x0388
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define REG_ACH2_ACH3_TXBD_NUM 0x0388
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_BKQ_TXBD_NUM 0x038A
+#define REG_HI0Q_TXBD_NUM 0x038C
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define REG_P0HI0Q_HI1Q_TXBD_NUM 0x038C
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_HI1Q_TXBD_NUM 0x038E
+#define REG_HI2Q_TXBD_NUM 0x0390
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define REG_P0HI2Q_HI3Q_TXBD_NUM 0x0390
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_HI3Q_TXBD_NUM 0x0392
+#define REG_HI4Q_TXBD_NUM 0x0394
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define REG_P0HI4Q_HI5Q_TXBD_NUM 0x0394
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_HI5Q_TXBD_NUM 0x0396
+#define REG_HI6Q_TXBD_NUM 0x0398
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define REG_P0HI6Q_HI7Q_TXBD_NUM 0x0398
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_HI7Q_TXBD_NUM 0x039A
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_TSFTIMER_HCI 0x039C
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_BD_RWPTR_CLR 0x039C
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define REG_BD_RWPTR_CLR1 0x039C
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_VOQ_TXBD_IDX 0x03A0
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define REG_ACH0_TXBD_IDX 0x03A0
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_VIQ_TXBD_IDX 0x03A4
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define REG_ACH1_TXBD_IDX 0x03A4
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_BEQ_TXBD_IDX 0x03A8
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define REG_ACH2_TXBD_IDX 0x03A8
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_BKQ_TXBD_IDX 0x03AC
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define REG_ACH3_TXBD_IDX 0x03AC
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_MGQ_TXBD_IDX 0x03B0
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define REG_P0MGQ_TXBD_IDX 0x03B0
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_RXQ_RXBD_IDX 0x03B4
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define REG_P0RXQ_RXBD_IDX 0x03B4
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_HI0Q_TXBD_IDX 0x03B8
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define REG_P0HI0Q_TXBD_IDX 0x03B8
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_HI1Q_TXBD_IDX 0x03BC
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define REG_P0HI1Q_TXBD_IDX 0x03BC
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_HI2Q_TXBD_IDX 0x03C0
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define REG_P0HI2Q_TXBD_IDX 0x03C0
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_HI3Q_TXBD_IDX 0x03C4
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define REG_P0HI3Q_TXBD_IDX 0x03C4
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_HI4Q_TXBD_IDX 0x03C8
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define REG_P0HI4Q_TXBD_IDX 0x03C8
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_HI5Q_TXBD_IDX 0x03CC
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define REG_P0HI5Q_TXBD_IDX 0x03CC
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_HI6Q_TXBD_IDX 0x03D0
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define REG_P0HI6Q_TXBD_IDX 0x03D0
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_HI7Q_TXBD_IDX 0x03D4
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define REG_P0HI7Q_TXBD_IDX 0x03D4
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+     HALMAC_8822C_SUPPORT)
+
+#define REG_DBG_SEL_V1 0x03D8
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define REG_DBGSEL_PCIE_HRPWM1_HCPWM1_V1 0x03D8
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_PCIE_HRPWM1_V1 0x03D9
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+#define REG_HCI_HRPWM1_V1 0x03D9
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_PCIE_HCPWM1_V1 0x03DA
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+#define REG_HCI_HCPWM1_V1 0x03DA
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_PCIE_CTRL2 0x03DB
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+#define REG_HCI_CTRL2 0x03DB
+
+#endif
+
+#if (HALMAC_8881A_SUPPORT)
+
+#define REG_LX_CTRL2 0x03DB
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_PCIE_HRPWM2_V1 0x03DC
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+#define REG_HCI_HRPWM2_V1 0x03DC
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define REG_PCIE_HRPWM2_HCPWM2_V1 0x03DC
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_PCIE_HCPWM2_V1 0x03DE
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+#define REG_HCI_HCPWM2_V1 0x03DE
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8881A_SUPPORT)
+
+#define REG_PCIE_H2C_MSG_V1 0x03E0
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+#define REG_HCI_H2C_MSG_V1 0x03E0
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8881A_SUPPORT)
+
+#define REG_PCIE_C2H_MSG_V1 0x03E4
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+#define REG_HCI_C2H_MSG_V1 0x03E4
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_DBI_WDATA_V1 0x03E8
+
+#endif
+
+#if (HALMAC_8881A_SUPPORT)
+
+#define REG_LX_DMA_ISR 0x03E8
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_DBI_RDATA_V1 0x03EC
+
+#endif
+
+#if (HALMAC_8881A_SUPPORT)
+
+#define REG_LX_DMA_IMR 0x03EC
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_DBI_FLAG_V1 0x03F0
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+#define REG_STUCK_FLAG_V1 0x03F0
+
+#endif
+
+#if (HALMAC_8881A_SUPPORT)
+
+#define REG_LX_DMA_DBG 0x03F0
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_MDIO_V1 0x03F4
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT)
+
+#define REG_MDIO2_V1 0x03F8
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_PCIE_MIX_CFG 0x03F8
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+#define REG_WDT_CFG 0x03F8
+
+#endif
+
+#if (HALMAC_8881A_SUPPORT)
+
+#define REG_BUS_MIX_CFG 0x03F8
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+#define REG_HCI_MIX_CFG 0x03FC
+
+#endif
+
+#if (HALMAC_8881A_SUPPORT)
+
+#define REG_BUS_MIX_CFG1 0x03FC
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_Q0_INFO 0x0400
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8814B_SUPPORT)
+
+#define REG_QUEUELIST_INFO0 0x0400
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+#define REG_QUEUE_INFO1 0x0400
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_Q1_INFO 0x0404
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8814B_SUPPORT)
+
+#define REG_QUEUELIST_INFO1 0x0404
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+#define REG_QUEUE_INFO2 0x0404
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_Q2_INFO 0x0408
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+#define REG_QUEUE_INFO3 0x0408
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define REG_QUEUELIST_INFO2 0x0408
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_Q3_INFO 0x040C
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+#define REG_QINFO_INDEX 0x040C
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define REG_QUEUELIST_INFO3 0x040C
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_MGQ_INFO 0x0410
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+#define REG_QUEUE_EMPTY 0x0410
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define REG_QUEUELIST_INFO_EMPTY 0x0410
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_HIQ_INFO 0x0414
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+#define REG_QUEUELIST_INFO2_V1 0x0414
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+#define REG_ACQ_STOP_V1 0x0414
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define REG_QUEUELIST_ACQ_EN 0x0414
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_BCNQ_INFO 0x0418
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+#define REG_TXPKT_EMPTY_V1 0x0418
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define REG_BCNQ_BDNY_V2 0x0418
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_TXPKT_EMPTY 0x041A
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_CPU_MGQ_INFO 0x041C
+#define REG_FWHW_TXQ_CTRL 0x0420
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_HWSEQ_CTRL 0x0423
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_DATAFB_SEL 0x0423
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_BCNQ_BDNY 0x0424
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_BCNQ_BDNY_V1 0x0424
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define REG_TXBDNY 0x0424
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_MGQ_BDNY 0x0425
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_LIFETIME_EN 0x0426
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_FW_FREE_TAIL 0x0427
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_SPEC_SIFS 0x0428
+#define REG_RETRY_LIMIT 0x042A
+#define REG_TXBF_CTRL 0x042C
+#define REG_DARFRC 0x0430
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_DARFRCH 0x0434
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_RARFRC 0x0438
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_RARFRCH 0x043C
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_RRSR 0x0440
+#define REG_ARFR0 0x0444
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_ARFRH0 0x0448
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8881A_SUPPORT)
+
+#define REG_ARFR1_V1 0x044C
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+#define REG_ARFR1 0x044C
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define REG_REG_ARFR_WT0 0x044C
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+#define REG_ARFRH1 0x0450
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_ARFRH1_V1 0x0450
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define REG_REG_ARFR_WT1 0x0450
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_CCK_CHECK 0x0454
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_AMPDU_BURST_CTRL 0x0455
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+#define REG_BCNQ2_HEAD 0x0455
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_AMPDU_MAX_TIME_V1 0x0455
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_AMPDU_MAX_TIME 0x0456
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_BCNQ1_BDNY_V1 0x0456
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define REG_TAB_SEL 0x0456
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_BCNQ1_BDNY 0x0457
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define REG_BCN_INVALID_CTRL 0x0457
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_AMPDU_MAX_LENGTH 0x0458
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_AMPDU_MAX_LENGTH_HT 0x0458
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_ACQ_STOP 0x045C
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_WMAC_LBK_BUF_HD 0x045D
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_NDPA_RATE 0x045D
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_TX_HANG_CTRL 0x045E
+#define REG_NDPA_OPT_CTRL 0x045F
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_FAST_EDCA_CTRL 0x0460
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_AMPDU_MAX_LENGTH_VHT 0x0460
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_RD_RESP_PKT_TH 0x0463
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8881A_SUPPORT)
+
+#define REG_CMDQ_INFO 0x0464
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define REG_NEW_EDCA_CTRL_V1 0x0464
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_Q4_INFO 0x0468
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define REG_ACQ_STOP_V2 0x0468
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_Q5_INFO 0x046C
+#define REG_Q6_INFO 0x0470
+#define REG_Q7_INFO 0x0474
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_WMAC_LBK_BUF_HD_V1 0x0478
+#define REG_MGQ_BDNY_V1 0x047A
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_TXRPT_CTRL 0x047C
+#define REG_INIRTS_RATE_SEL 0x0480
+#define REG_BASIC_CFEND_RATE 0x0481
+#define REG_STBC_CFEND_RATE 0x0482
+#define REG_DATA_SC 0x0483
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_MACID_SLEEP3 0x0484
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define REG_MOREDATA_V1 0x0484
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+#define REG_MACID_SLEEP4 0x0485
+#define REG_MACID_SLEEP5 0x0487
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define REG_DATA_SC1 0x0487
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_MACID_SLEEP1 0x0488
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8881A_SUPPORT)
+
+#define REG_ARFR2_V1 0x048C
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+#define REG_ARFR2 0x048C
+#define REG_ARFRH2 0x0490
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_ARFRH2_V1 0x0490
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8881A_SUPPORT)
+
+#define REG_ARFR3_V1 0x0494
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+#define REG_ARFR3 0x0494
+#define REG_ARFRH3 0x0498
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_ARFRH3_V1 0x0498
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_ARFR4 0x049C
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+#define REG_ARFRH4 0x04A0
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_ARFR5 0x04A4
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+#define REG_ARFRH5 0x04A8
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_TXRPT_START_OFFSET 0x04AC
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_TRYING_CNT_TH 0x04B0
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+#define REG_TRY_CNT_IDX 0x04B0
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT)
+
+#define REG_RRSR_CTS 0x04B0
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_POWER_STAGE1 0x04B4
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+#define REG_POWER_STAGE2 0x04B8
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_SW_AMPDU_BURST_MODE_CTRL 0x04BC
+#define REG_PKT_LIFE_TIME 0x04C0
+#define REG_STBC_SETTING 0x04C4
+#define REG_STBC_SETTING2 0x04C5
+#define REG_QUEUE_CTRL 0x04C6
+#define REG_SINGLE_AMPDU_CTRL 0x04C7
+#define REG_PROT_MODE_CTRL 0x04C8
+#define REG_BAR_MODE_CTRL 0x04CC
+#define REG_RA_TRY_RATE_AGG_LMT 0x04CF
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_MACID_SLEEP2 0x04D0
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define REG_MACID_SLEEP_CTRL 0x04D0
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_MACID_SLEEP 0x04D4
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define REG_MACID_SLEEP_INFO 0x04D4
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8881A_SUPPORT)
+
+#define REG_HW_SEQ0 0x04D8
+#define REG_HW_SEQ1 0x04DA
+#define REG_HW_SEQ2 0x04DC
+#define REG_HW_SEQ3 0x04DE
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+#define REG_CSI_SEQ 0x04DE
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_NULL_PKT_STATUS 0x04E0
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_NULL_PKT_STATUS_V1 0x04E0
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8881A_SUPPORT)
+
+#define REG_PTCL_ERR_STATUS 0x04E2
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8814B_SUPPORT)
+
+#define REG_PTCL_ERR_STATUS_V1 0x04E2
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_PTCL_PKT_NUM 0x04E3
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_NULL_PKT_STATUS_EXTEND 0x04E3
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+#define REG_TRXRPT_MISS_CNT 0x04E3
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_HQMGQ_DROP 0x04E4
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+
+#define REG_VIDEO_ENHANCEMENT_FUN 0x04E4
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define REG_NULL_PKT_STATUS_V2 0x04E4
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_PRECNT_CTRL 0x04E5
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define REG_NULL_PKT_STATUS_EXTEND_V1 0x04E7
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+#define REG_BT_POLLUTE_PKTCNT_V1 0x04E8
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_BT_POLLUTE_PKT_CNT 0x04E8
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+#define REG_DROP_PKT_NUM 0x04EC
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_PTCL_DBG 0x04EC
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+#define REG_DROP_NUM 0x04EC
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define REG_PTCL_DBG_V1 0x04EC
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_PTCL_TX_RPT 0x04F0
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+#define REG_TX_RPT_INFO_L32 0x04F0
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+#define REG_TXOP_EXTRA_CTRL 0x04F0
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define REG_BT_POLLUTE_PKTCNT 0x04F0
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+#define REG_TX_RPT_INFO_H32 0x04F4
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+#define REG_CPUMGQ_TIMER_CTRL2 0x04F4
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define REG_PTCL_DBG_OUT 0x04F8
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8881A_SUPPORT)
+
+#define REG_DUMMY_PAGE4 0x04FC
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_DUMMY_PAGE4_V1 0x04FC
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8814B_SUPPORT)
+
+#define REG_DUMMY_PAGE4_1 0x04FE
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_MOREDATA 0x04FE
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_EDCA_VO_PARAM 0x0500
+#define REG_EDCA_VI_PARAM 0x0504
+#define REG_EDCA_BE_PARAM 0x0508
+#define REG_EDCA_BK_PARAM 0x050C
+#define REG_BCNTCFG 0x0510
+#define REG_PIFS 0x0512
+#define REG_RDG_PIFS 0x0513
+#define REG_SIFS 0x0514
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_TSFTR_SYN_OFFSET 0x0518
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define REG_FORCE_BCN_IFS_V1 0x0518
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_AGGR_BREAK_TIME 0x051A
+#define REG_SLOT 0x051B
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+#define REG_NOA_ON_ERLY_TIME 0x051C
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define REG_EDCA_CPUMGQ_PARAM 0x051C
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+#define REG_NOA_OFF_ERLY_TIME 0x051D
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define REG_CPUMGQ_PAUSE 0x051E
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+#define REG_PS_TIMER_CTRL 0x051F
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_TX_PTCL_CTRL 0x0520
+#define REG_TXPAUSE 0x0522
+#define REG_DIS_TXREQ_CLR 0x0523
+#define REG_RD_CTRL 0x0524
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_MBSSID_CTRL 0x0526
+#define REG_P2PPS_CTRL 0x0527
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_PKT_LIFETIME_CTRL 0x0528
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8881A_SUPPORT)
+
+#define REG_P2PPS_SPEC_STATE 0x052B
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+#define REG_P2PPS0_SPEC_STATE 0x052B
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+#define REG_PS_TIMER_A_V2 0x052C
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+#define REG_TXOP_LIMIT_CTRL 0x052C
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+#define REG_BAR_TX_CTRL 0x0530
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_P2PON_DIS_TXTIME 0x0531
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+#define REG_PS_TIMER_B_V2 0x0534
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_CCA_TXEN_CNT 0x0534
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822B_SUPPORT)
+
+#define REG_QUEUE_INCOL_THR 0x0538
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_MAX_INTER_COLLISION 0x0538
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822B_SUPPORT)
+
+#define REG_QUEUE_INCOL_EN 0x053C
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_MAX_INTER_COLLISION_CNT 0x053C
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_TBTT_PROHIBIT 0x0540
+#define REG_P2PPS_STATE 0x0543
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_RD_NAV_NXT 0x0544
+#define REG_NAV_PROT_LEN 0x0546
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+#define REG_FTM_SETTING 0x0548
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+#define REG_FTM_CTRL 0x0548
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_FTM_PTT 0x0548
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+#define REG_FTM_TSF_CNT 0x054C
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_FTM_TSF 0x054C
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_BCN_CTRL 0x0550
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_BCN_CTRL1 0x0551
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_BCN_CTRL_CLINT0 0x0551
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_MBID_NUM 0x0552
+#define REG_DUAL_TSF_RST 0x0553
+#define REG_MBSSID_BCN_SPACE 0x0554
+#define REG_DRVERLYINT 0x0558
+#define REG_BCNDMATIM 0x0559
+#define REG_ATIMWND 0x055A
+#define REG_USTIME_TSF 0x055C
+#define REG_BCN_MAX_ERR 0x055D
+#define REG_RXTSF_OFFSET_CCK 0x055E
+#define REG_RXTSF_OFFSET_OFDM 0x055F
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8881A_SUPPORT)
+
+#define REG_TSFTR 0x0560
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+#define REG_TSFTR0_L 0x0560
+#define REG_TSFTR0_H 0x0564
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_TSFTR_1 0x0564
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_TSFTR1 0x0568
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+#define REG_TSFTR1_L 0x0568
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_FREERUN_CNT 0x0568
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+#define REG_TSFTR1_H 0x056C
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_FREERUN_CNT_1 0x056C
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8881A_SUPPORT)
+
+#define REG_ATIMWND1 0x0570
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+     HALMAC_8822C_SUPPORT)
+
+#define REG_ATIMWND1_V1 0x0570
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_TBTT_PROHIBIT_INFRA 0x0571
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_CTWND 0x0572
+#define REG_BCNIVLCUNT 0x0573
+#define REG_BCNDROPCTRL 0x0574
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_HGQ_TIMEOUT_PERIOD 0x0575
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+#define REG_TXCMD_TIMEOUT_PERIOD 0x0576
+#define REG_MISC_CTRL 0x0577
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+#define REG_TSFTR2_L 0x0578
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_BCN_CTRL_CLINT1 0x0578
+#define REG_BCN_CTRL_CLINT2 0x0579
+#define REG_BCN_CTRL_CLINT3 0x057A
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_EXTEND_CTRL 0x057B
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+#define REG_TSFTR2_H 0x057C
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_P2PPS1_SPEC_STATE 0x057C
+#define REG_P2PPS1_STATE 0x057D
+#define REG_P2PPS2_SPEC_STATE 0x057E
+#define REG_P2PPS2_STATE 0x057F
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_PS_TIMER 0x0580
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_PS_TIMER0 0x0580
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_TIMER0 0x0584
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_PS_TIMER1 0x0584
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_TIMER1 0x0588
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_PS_TIMER2 0x0588
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_TBTT_CTN_AREA 0x058C
+#define REG_FORCE_BCN_IFS 0x058E
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+#define REG_DRVERLYINT_V1 0x058F
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_TXOP_MIN 0x0590
+#define REG_PRE_BKF_TIME 0x0592
+#define REG_CROSS_TXOP_CTRL 0x0593
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+#define REG_FREERUN_CNT_L 0x0594
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+#define REG_TBTT_INT_SHIFT_CLI0 0x0594
+#define REG_TBTT_INT_SHIFT_CLI1 0x0595
+#define REG_TBTT_INT_SHIFT_CLI2 0x0596
+#define REG_TBTT_INT_SHIFT_CLI3 0x0597
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+#define REG_FREERUN_CNT_H 0x0598
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+#define REG_TBTT_INT_SHIFT_ENABLE 0x0598
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_RX_TBTT_SHIFT_V1 0x0598
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8881A_SUPPORT)
+
+#define REG_ATIMWND2 0x05A0
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+#define REG_ATIMWND_GROUP1 0x05A0
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8881A_SUPPORT)
+
+#define REG_ATIMWND3 0x05A1
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+#define REG_ATIMWND_GROUP2 0x05A1
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8881A_SUPPORT)
+
+#define REG_ATIMWND4 0x05A2
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+#define REG_ATIMWND_GROUP3 0x05A2
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8881A_SUPPORT)
+
+#define REG_ATIMWND5 0x05A3
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+#define REG_ATIMWND_GROUP4 0x05A3
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8881A_SUPPORT)
+
+#define REG_ATIMWND6 0x05A4
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+#define REG_DTIM_COUNT_GROUP1 0x05A4
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8881A_SUPPORT)
+
+#define REG_ATIMWND7 0x05A5
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+#define REG_DTIM_COUNT_GROUP2 0x05A5
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8881A_SUPPORT)
+
+#define REG_ATIMUGT 0x05A6
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+#define REG_DTIM_COUNT_GROUP3 0x05A6
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8881A_SUPPORT)
+
+#define REG_HIQ_NO_LMT_EN 0x05A7
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+#define REG_DTIM_COUNT_GROUP4 0x05A7
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8881A_SUPPORT)
+
+#define REG_DTIM_COUNTER_ROOT 0x05A8
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+#define REG_HIQ_NO_LMT_EN_V2 0x05A8
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8881A_SUPPORT)
+
+#define REG_DTIM_COUNTER_VAP1 0x05A9
+#define REG_DTIM_COUNTER_VAP2 0x05AA
+#define REG_DTIM_COUNTER_VAP3 0x05AB
+#define REG_DTIM_COUNTER_VAP4 0x05AC
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+#define REG_MBID_BCNQ_EN 0x05AC
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8881A_SUPPORT)
+
+#define REG_DTIM_COUNTER_VAP5 0x05AD
+#define REG_DTIM_COUNTER_VAP6 0x05AE
+#define REG_DTIM_COUNTER_VAP7 0x05AF
+#define REG_DIS_ATIM 0x05B0
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_EARLY_128US 0x05B1
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+#define REG_TBTT_HOLD_PREDICT_P1 0x05B2
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_P2PPS1_CTRL 0x05B2
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+#define REG_MULTI_BCN_CS 0x05B3
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_P2PPS2_CTRL 0x05B3
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+#define REG_TSFT_SHIFT 0x05B4
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_TIMER0_SRC_SEL 0x05B4
+#define REG_NOA_UNIT_SEL 0x05B5
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_P2POFF_DIS_TXTIME 0x05B7
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_MBSSID_BCN_SPACE2 0x05B8
+#define REG_MBSSID_BCN_SPACE3 0x05BC
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_ACMHWCTRL 0x05C0
+#define REG_ACMRSTCTRL 0x05C1
+#define REG_ACMAVG 0x05C2
+#define REG_VO_ADMTIME 0x05C4
+#define REG_VI_ADMTIME 0x05C6
+#define REG_BE_ADMTIME 0x05C8
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_MAC_HEADER_NAV_OFFSET 0x05CA
+#define REG_DIS_NDPA_NAV_CHECK 0x05CB
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_EDCA_RANDOM_GEN 0x05CC
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_TXCMD_NOA_SEL 0x05CF
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define REG_TXCMD_SEL 0x05CF
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+#define REG_DRVERLYINT2 0x05D0
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_32K_CLK_SEL 0x05D0
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+#define REG_NAN_SETTING 0x05D4
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_EARLYINT_ADJUST 0x05D4
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+#define REG_NAN_BCNSPACE 0x05D8
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_BCNERR_CNT 0x05D8
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+#define REG_NAN_SETTING1 0x05DC
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_BCNERR_CNT_2 0x05DC
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_NOA_PARAM 0x05E0
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+#define REG_NOA_PARAM_1 0x05E4
+#define REG_NOA_PARAM_2 0x05E8
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define REG_MU_DBG_INFO 0x05E8
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+#define REG_NOA_PARAM_3 0x05EC
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define REG_MU_DBG_INFO_1 0x05EC
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_NOA_SUBIE 0x05ED
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_P2P_RST 0x05F0
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define REG_SCH_DBG_SEL 0x05F0
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_SCHEDULER_RST 0x05F1
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define REG_MU_DBG_ERR_FLAG 0x05F2
+#define REG_TX_ERR_RECOVERY_RST 0x05F3
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+#define REG_SCH_DBG 0x05F4
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_SCH_DBG_VALUE 0x05F4
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_SCH_TXCMD 0x05F8
+#define REG_PAGE5_DUMMY 0x05FC
+#define REG_WMAC_CR 0x0600
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_WMAC_FWPKT_CR 0x0601
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+#define REG_FW_STS_FILTER 0x0602
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+#define REG_WMAC_BWOPMODE 0x0603
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT)
+
+#define REG_BWOPMODE 0x0603
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_TCR 0x0604
+#define REG_RCR 0x0608
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_RX_PKT_LIMIT 0x060C
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+#define REG_RXPKT_LIMIT 0x060C
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_RX_DLK_TIME 0x060D
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+#define REG_SDIO_RXINT_LEN_TH 0x1025060E
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_RX_DRVINFO_SZ 0x060F
+#define REG_MACID 0x0610
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_MACID_H 0x0614
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_BSSID 0x0618
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_BSSID_H 0x061C
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_MAR 0x0620
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_MAR_H 0x0624
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_MBIDCAMCFG_1 0x0628
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8881A_SUPPORT)
+
+#define REG_MBIDCAMCFG_2 0x062C
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+#define REG_MBIDCAM_CFG 0x062C
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define REG_WMAC_DEBUG_SEL 0x062C
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_MCU_TEST_1 0x0630
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_WMAC_TCR_TSFT_OFS 0x0630
+#define REG_UDF_THSD 0x0632
+#define REG_ZLD_NUM 0x0633
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_MCU_TEST_2 0x0634
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_STMP_THSD 0x0634
+#define REG_WMAC_TXTIMEOUT 0x0635
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT)
+
+#define REG_MCU_TEST_2_V1 0x0636
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_USTIME_EDCA 0x0638
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_ACKTO_CCK 0x0639
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_MAC_SPEC_SIFS 0x063A
+#define REG_RESP_SIFS_CCK 0x063C
+#define REG_RESP_SIFS_OFDM 0x063E
+#define REG_ACKTO 0x0640
+#define REG_CTS2TO 0x0641
+#define REG_EIFS 0x0642
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_RPFM_MAP0 0x0644
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+#define REG_RPFM_MAP1 0x0646
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+#define REG_RPFM_MAP1_V1 0x0646
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_RPFM_CAM_CMD 0x0648
+#define REG_RPFM_CAM_RWD 0x064C
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_NAV_CTRL 0x0650
+#define REG_BACAMCMD 0x0654
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_BACAMCONTENT 0x0658
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+#define REG_BACAM_WD 0x0658
+#define REG_BACAM_WD_H 0x065C
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+#define REG_BACAMCONTENT_H 0x065C
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_LBDLY 0x0660
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+#define REG_LBK_DLY 0x0660
+#define REG_BITMAP_CMD 0x0661
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_WMAC_BACAM_RPMEN 0x0661
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_TX_RX 0x0662
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_WMAC_BITMAP_CTL 0x0663
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_RXERR_RPT 0x0664
+#define REG_WMAC_TRXPTCL_CTL 0x0668
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_WMAC_TRXPTCL_CTL_H 0x066C
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_CAMCMD 0x0670
+#define REG_CAMWRITE 0x0674
+#define REG_CAMREAD 0x0678
+#define REG_CAMDBG 0x067C
+#define REG_SECCFG 0x0680
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_RXFILTER_CATEGORY_1 0x0682
+#define REG_RXFILTER_ACTION_1 0x0683
+#define REG_RXFILTER_CATEGORY_2 0x0684
+#define REG_RXFILTER_ACTION_2 0x0685
+#define REG_RXFILTER_CATEGORY_3 0x0686
+#define REG_RXFILTER_ACTION_3 0x0687
+#define REG_RXFLTMAP3 0x0688
+#define REG_RXFLTMAP4 0x068A
+#define REG_RXFLTMAP5 0x068C
+#define REG_RXFLTMAP6 0x068E
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_WOW_CTRL 0x0690
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_NAN_RX_TSF_FILTER 0x0691
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_PS_RX_INFO 0x0692
+#define REG_WMMPS_UAPSD_TID 0x0693
+#define REG_LPNAV_CTRL 0x0694
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_WKFMCAM_NUM 0x0698
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+#define REG_WKFMCAM_CMD 0x0698
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_WKFMCAM_RWD 0x069C
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_RXFLTMAP0 0x06A0
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+#define REG_RXFLTER0 0x06A0
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_RXFLTMAP1 0x06A2
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+#define REG_RXFLTER1 0x06A2
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_RXFLTMAP 0x06A4
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+#define REG_RXFLTER2 0x06A4
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_RXFLTMAP2 0x06A4
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_BCN_PSR_RPT 0x06A8
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_FLC_RPC 0x06AC
+#define REG_FLC_RPCT 0x06AD
+#define REG_FLC_PTS 0x06AE
+#define REG_FLC_TRPC 0x06AF
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+#define REG_RXPKTMON_CTRL 0x06B0
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_STATE_MON 0x06B4
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+#define REG_ERROR_EVT_CTL 0x06B8
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_ERROR_MON 0x06B8
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+#define REG_RESPINFO 0x06BC
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_SEARCH_MACID 0x06BC
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_BT_COEX_TABLE 0x06C0
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+#define REG_BT_COEX_TABLE_V1 0x06C0
+#define REG_BT_COEX_TABLE2_V1 0x06C4
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+#define REG_BT_COEX_TABLE2 0x06C4
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_BT_COEX_BREAK_TABLE 0x06C8
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+#define REG_BT_COEX_TABLE_H_V1 0x06CC
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+#define REG_BT_COEX_TABLE_H 0x06CC
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+#define REG_RXCMD_0 0x06D0
+#define REG_RXCMD_1 0x06D4
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_WMAC_RESP_TXINFO 0x06D8
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+#define REG_RESP_TXINFO_CFG 0x06D8
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+#define REG_BBPSF_CTRL 0x06DC
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+#define REG_RESP_TXINFO_RATE 0x06DE
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_P2P_RX_BCN_NOA 0x06E0
+#define REG_ASSOCIATED_BFMER0_INFO 0x06E4
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+#define REG_SOUNDING_CFG1 0x06E8
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+#define REG_ASSOCIATED_BFMER0_INFO_H 0x06E8
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_ASSOCIATED_BFMER1_INFO 0x06EC
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+#define REG_SOUNDING_CFG2 0x06EC
+#define REG_SOUNDING_CFG3 0x06F0
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+#define REG_ASSOCIATED_BFMER1_INFO_H 0x06F0
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_TX_CSI_RPT_PARAM_BW20 0x06F4
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+#define REG_SOUNDING_CFG0 0x06F4
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_TX_CSI_RPT_PARAM_BW40 0x06F8
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+#define REG_ANTCD_INFO 0x06F8
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT || \
+     HALMAC_8881A_SUPPORT)
+
+#define REG_TX_CSI_RPT_PARAM_BW80 0x06FC
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+#define REG_CSI_RRSR_V1 0x06FC
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_CSI_PTR 0x06FC
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_MACID1 0x0700
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_MACID1_1 0x0704
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+#define REG_BSSID1 0x0708
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define REG_PCIE_CFG_FORCE_LINK_L 0x0709
+#define REG_PCIE_CFG_FORCE_LINK_H 0x070A
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_BSSID1_1 0x070C
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define REG_PCIE_CFG_DEFAULT_ACK_FREQUENCY 0x070C
+#define REG_PCIE_CFG_CX_NFTS 0x070D
+#define REG_PCIE_CFG_DEFAULT_ENTR_LATENCY 0x070F
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_BCN_PSR_RPT1 0x0710
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define REG_PCIE_CFG_L1_MISC_SEL 0x0711
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_ASSOCIATED_BFMEE_SEL 0x0714
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+#define REG_ASSOCIATED_BFMEE_SEL_1 0x0714
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_SND_PTCL_CTRL 0x0718
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define REG_PCIE_CFG_TIMER_CTRL_MAX_FUNC_NUM_OFF 0x0718
+#define REG_PCIE_CFG_FORCE_CLKREQ_N_PAD 0x0719
+#define REG_PCIE_CFG_TIMER_MODIFIER_FOR_ACK_NAK_LATENCY 0x071A
+#define REG_PCIE_CFG_TIMER_MODIFIER_FOR_FLOW_CONTROL_WATCHDOG 0x071B
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_RX_CSI_RPT_INFO 0x071C
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define REG_PCIE_CFG_SKP_INTERVAL_VALUE_L 0x071C
+#define REG_PCIE_CFG_SKP_INTERVAL_VALUE_H 0x071D
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+#define REG_RX_CSI_RPT_INFO_H 0x071F
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_NS_ARP_CTRL 0x0720
+#define REG_NS_ARP_INFO 0x0724
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define REG_PCIE_CFG_L1_UNIT_SEL 0x0724
+#define REG_PCIE_CFG_MIN_CLKREQ_SEL 0x0725
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_NS_ARP_IPADDR 0x0728
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+#define REG_PWR_INT_CTRL 0x0728
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+#define REG_BEAMFORMING_INFO_NSARP_V1 0x0728
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_WRITE_RX_CSI_RPT_INFO 0x072C
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+#define REG_RX_CSI_RPT_INFO_V1 0x072C
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_BEAMFORMING_INFO_NSARP 0x072C
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_NS_ARP_IPV6_MYADDR 0x0730
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+#define REG_POWER_MGT_0_V1 0x0730
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+#define REG_IPV6 0x0730
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+#define REG_POWER_MGT_1_V1 0x0734
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+#define REG_IPV6_1 0x0734
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+#define REG_POWER_MGT_2_V1 0x0738
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+#define REG_IPV6_2 0x0738
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+#define REG_POWER_MGT_3_V1 0x073C
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+#define REG_IPV6_3 0x073C
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+#define REG_PLCP_HEADER 0x0740
+#define REG_TXDRXDMONITOR 0x0744
+#define REG_TXDRXDMONITOR_CTL 0x0748
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+#define REG_WMAC_RTX_CTX_SUBTYPE_CFG 0x0750
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+#define REG_WMAC_SWAES_RD0_V1 0x0754
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_WMAC_SWAES_DIO_B63_B32 0x0754
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+#define REG_WMAC_SWAES_RD1_V1 0x0758
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_WMAC_SWAES_DIO_B95_B64 0x0758
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+#define REG_WMAC_SWAES_RD3_V1 0x075C
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_WMAC_SWAES_DIO_B127_B96 0x075C
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_WMAC_SWAES_CFG 0x0760
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+#define REG_BT_COEX_V2 0x0762
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_BT_COEX 0x0764
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_WLAN_ACT_MSK_CTRL 0x0768
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+#define REG_WLAN_ACT_MASK_CTRL 0x0768
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_WLAN_ACT_MASK_CTRL_1 0x076C
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_BT_STATISTICS_CTRL 0x076E
+#define REG_BT_COEX_ENH_INTF_CTRL 0x076E
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+#define REG_BT_COEX_ENHANCED_INTR_CTRL 0x076E
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_BT_ACT_STATISTICS 0x0770
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_BT_ACT_STATISTICS_1 0x0774
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_BT_STATISTICS_OTH_CTRL 0x0778
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+#define REG_BT_STATISTICS_CONTROL_REGISTER 0x0778
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_BT_CMD_ID 0x077C
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+#define REG_BT_STATUS_REPORT_REGISTER 0x077C
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_BT__STATUS_RPT 0x077D
+#define REG_BT_DATA 0x0780
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+#define REG_BT_INTERRUPT_CONTROL_REGISTER 0x0780
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_WLAN_RPT_ 0x0781
+#define REG_BT_ISR_CTRL 0x0783
+#define REG_WLAN_RPT_TO_CTR 0x0784
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+#define REG_WLAN_REPORT_TIME_OUT_CONTROL_REGISTER 0x0784
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_BT_ISOLATION_TABLE 0x0785
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+#define REG_BT_ISOLATION_TABLE_REGISTER_REGISTER 0x0785
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_BT_ISOLATION_TABLE_REGISTER_REGISTER_1 0x0788
+#define REG_BT_ISOLATION_TABLE_REGISTER_REGISTER_2 0x078C
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_BT_ISR_STA 0x078F
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+#define REG_BT_INTERRUPT_STATUS_REGISTER 0x078F
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_TDMA_TIME_AND_RPT_SAM_SET 0x0790
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+#define REG_BT_TDMA_TIME_REGISTER 0x0790
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_BT_CH_INFO 0x0794
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+#define REG_BT_ACT_REGISTER 0x0794
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_BT_STATIC_INFO_EXT 0x0795
+#define REG_LTR_IDLE_LATENCY 0x0798
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+#define REG_LTR_IDLE_LATENCY_V2 0x0798
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_OBFF_CTRL_BASIC 0x0798
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_LTR_ACTIVE_LATENCY 0x079C
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+#define REG_LTR_ACTIVE_LATENCY_V2 0x079C
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_OBFF_CTRL2_TIMER 0x079C
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_OBFF_CTRL 0x07A0
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_LTR_CTRL_BASIC 0x07A0
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_LTR_CTRL 0x07A4
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_LTR_CTRL2_TIMER_THRESHOLD 0x07A4
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_LTR_CTRL2 0x07A8
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_LTR_IDLE_LATENCY_V1 0x07A8
+#define REG_LTR_ACTIVE_LATENCY_V1 0x07AC
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_ANTTRN_CTRL 0x07B0
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+#define REG_ANTTRN_CTR_V1 0x07B0
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_ANTENNA_TRAINING_CONTROL_REGISTER 0x07B0
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define REG_SMART_ANT_CONDITION 0x07B0
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+#define REG_ANTTRN_CTR 0x07B4
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_ANTENNA_TRAINING_CONTROL_REGISTER_1 0x07B4
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define REG_SMART_ANT_CTRL 0x07B4
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_WMAC_PKTCNT_RWD 0x07B8
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define REG_CONTROL_FRAME_REPORT 0x07B8
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+     HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_WMAC_PKTCNT_CTRL 0x07BC
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define REG_CONTROL_FRAME_CNT_CTRL 0x07BC
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+#define REG_WL2LTECOEX_INDIRECT_ACCESS_CTRL 0x07C0
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_IQ_DUMP 0x07C0
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+#define REG_WL2LTECOEX_INDIRECT_ACCESS_WRITE_DATA 0x07C4
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+#define REG_IQ_DUMP_1 0x07C4
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+#define REG_WL2LTECOEX_INDIRECT_ACCESS_READ_DATA 0x07C8
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+#define REG_IQ_DUMP_2 0x07C8
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_WMAC_FTM_CTL 0x07CC
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_WMAC_IQ_MDPK_FUNC 0x07CE
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+#define REG_IQ_DUMP_EXT 0x07CF
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+#define REG_OFDM_CCK_LEN_MASK 0x07D0
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_WMAC_OPTION_FUNCTION 0x07D0
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+#define REG_FA_FILTER1 0x07D4
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+#define REG_WMAC_OPTION_FUNCTION_1 0x07D4
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+#define REG_FA_FILTER2 0x07D8
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+#define REG_WMAC_OPTION_FUNCTION_2 0x07D8
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+#define REG_RX_FILTER_FUNCTION 0x07DA
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+#define REG_NAN_FUN 0x07DC
+#define REG_NAN_CTL 0x07E0
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_NDP_SIG 0x07E0
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+#define REG_RX_NAN_ADDR_FILTER 0x07E4
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_TXCMD_INFO_FOR_RSP_PKT 0x07E4
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+#define REG_NAN_ADDR 0x07E8
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+#define REG_TXCMD_INFO_FOR_RSP_PKT_1 0x07E8
+
+#endif
+
+#if (HALMAC_8814AMP_SUPPORT)
+
+#define REG_SEC_OPT 0x07E8
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+#define REG_RXA1_MASK 0x07EC
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+#define REG_SEC_OPT_V2 0x07EC
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+#define REG_WSEC_OPTION 0x07EC
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+#define REG_DUMP_FUNC 0x07F0
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+#define REG_RTS_ADDRESS_0 0x07F0
+
+#endif
+
+#if (HALMAC_8814AMP_SUPPORT)
+
+#define REG_RTS_ADDR0 0x07F0
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+#define REG_MASK_LA_MAC 0x07F4
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+#define REG_RTS_ADDRESS_0_1 0x07F4
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+#define REG_MATCH_REF_MAC 0x07F8
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+#define REG_RTS_ADDRESS_1 0x07F8
+
+#endif
+
+#if (HALMAC_8814AMP_SUPPORT)
+
+#define REG_RTS_ADDR1 0x07F8
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+#define REG_LA_DUMP_FUNC_EXT 0x07FC
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+#define REG_RTS_ADDRESS_1_1 0x07FC
+
+#endif
+
+#if (HALMAC_8822B_SUPPORT)
+
+#define REG__RPFM_MAP1 0x07FE
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_SYS_CFG3 0x1000
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_ANAPARSW_MAC_0 0x1010
+#define REG_ANAPARSW_MAC_1 0x1014
+#define REG_ANAPAR_MAC_0 0x1018
+#define REG_ANAPAR_MAC_1 0x101C
+#define REG_ANAPAR_MAC_2 0x1020
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define REG_ANAPAR_MAC_3 0x1024
+#define REG_ANAPAR_MAC_4 0x1028
+#define REG_ANAPAR_MAC_5 0x102C
+#define REG_ANAPAR_MAC_6 0x1030
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT)
+
+#define REG_SYS_CFG4 0x1034
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define REG_ANAPAR_MAC_7 0x1034
+#define REG_ANAPAR_MAC_8 0x1038
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_ANAPAR_XTAL_0 0x1040
+#define REG_ANAPAR_XTAL_1 0x1044
+#define REG_ANAPAR_XTAL_2 0x1048
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_ANAPAR_XTAL_3 0x104C
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define REG_ANAPAR_XTAL_AAC 0x104C
+#define REG_ANAPAR_XTAL_R_ONLY 0x1050
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_ANAPAR_XTAL_AACK_0 0x1054
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define REG_CPHY_LDO 0x1054
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_ANAPAR_XTAL_AACK_1 0x1058
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define REG_CPHY_BG 0x1058
+#define REG_HIMR_4 0x1060
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_ANAPAR_XTAL_MODE_DECODER 0x1064
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define REG_HISR_4 0x1064
+#define REG_HIMR_5 0x1068
+#define REG_HISR_5 0x106C
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_SYS_CFG5 0x1070
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT)
+
+#define REG_REGU_32K_1 0x1078
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define REG_HIMR_6 0x1078
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT)
+
+#define REG_REGU_32K_2 0x107C
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define REG_HISR_6 0x107C
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+#define REG_CPU_DMEM_CON 0x1080
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_BOOT_REASON 0x1088
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+#define REG_HIMR4 0x1090
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define REG_DATA_CPU_CTL0 0x1090
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+#define REG_HISR4 0x1094
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define REG_DATA_CPU_CTL1 0x1094
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+#define REG_HIMR5 0x1098
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define REG_TXDMA_STOP_HIMR 0x1098
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+#define REG_HISR5 0x109C
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define REG_TXDMA_STOP_HISR 0x109C
+#define REG_TXDMA_START_HIMR 0x10A0
+#define REG_TXDMA_START_HISR 0x10A4
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+
+#define REG_NFCPAD_CTRL 0x10A8
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+#define REG_HIMR2 0x10B0
+#define REG_HISR2 0x10B4
+#define REG_HIMR3 0x10B8
+#define REG_HISR3 0x10BC
+#define REG_SW_MDIO 0x10C0
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT)
+
+#define REG_SW_FLUSH 0x10C4
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+#define REG_DBG_GPIO_BMUX 0x10C8
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define REG_HIMR_7 0x10C8
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+#define REG_FPGA_TAG 0x10CC
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define REG_HISR_7 0x10CC
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+#define REG_WL_DSS_CTRL0 0x10D0
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_H2C_PKT_READADDR 0x10D0
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+#define REG_WL_DSS_STATUS0 0x10D4
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_H2C_PKT_WRITEADDR 0x10D4
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+#define REG_WL_DSS_CTRL1 0x10D8
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_MEM_PWR_CRTL 0x10D8
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+#define REG_WL_DSS_STATUS1 0x10DC
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define REG_FW_DRV_HANDSHAKE 0x10DC
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822B_SUPPORT)
+
+#define REG_FW_DBG0 0x10E0
+#define REG_FW_DBG1 0x10E4
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8822B_SUPPORT)
+
+#define REG_FW_DBG2 0x10E8
+#define REG_FW_DBG3 0x10EC
+#define REG_FW_DBG4 0x10F0
+#define REG_FW_DBG5 0x10F4
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+#define REG_FW_DBG6 0x10F8
+#define REG_FW_DBG7 0x10FC
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_CR_EXT 0x1100
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define REG_TC9_CTRL 0x1104
+#define REG_TC10_CTRL 0x1108
+#define REG_TC11_CTRL 0x110C
+#define REG_TC12_CTRL 0x1110
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_FWFF 0x1114
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_RXFF_PTR_V1 0x1118
+#define REG_RXFF_WTR_V1 0x111C
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_FE2IMR 0x1120
+#define REG_FE2ISR 0x1124
+#define REG_FE3IMR 0x1128
+#define REG_FE3ISR 0x112C
+#define REG_FE4IMR 0x1130
+#define REG_FE4ISR 0x1134
+#define REG_FT1IMR 0x1138
+#define REG_FT1ISR 0x113C
+#define REG_SPWR0 0x1140
+#define REG_SPWR1 0x1144
+#define REG_SPWR2 0x1148
+#define REG_SPWR3 0x114C
+#define REG_POWSEQ 0x1150
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_TC7_CTRL_V1 0x1158
+#define REG_TC8_CTRL_V1 0x115C
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+#define REG_RXBCN_TBTT_INTERVAL_PORT0TO3 0x1160
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+#define REG_RX_BCN_TBTT_ITVL0 0x1160
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+#define REG_RXBCN_TBTT_INTERVAL_PORT4 0x1164
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+#define REG_RX_BCN_TBTT_ITVL1 0x1164
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT)
+
+#define REG_FWIMR1 0x1168
+#define REG_FWISR1 0x116C
+#define REG_FWIMR2 0x1170
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_IO_WRAP_ERR_FLAG 0x1170
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT)
+
+#define REG_FWISR2 0x1174
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define REG_FWIMR3 0x1178
+#define REG_FWISR3 0x117C
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+#define REG_SPEED_SENSOR 0x1180
+#define REG_SPEED_SENSOR1 0x1184
+#define REG_SPEED_SENSOR2 0x1188
+#define REG_SPEED_SENSOR3 0x118C
+#define REG_SPEED_SENSOR4 0x1190
+#define REG_SPEED_SENSOR5 0x1194
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define REG_RXPKTBUF_1_MAX_ADDR 0x1198
+#define REG_RXFWBUF_1_MAX_ADDR 0x119C
+#define REG_IO_WRAP_ERR_FLAG_V1 0x11A0
+#define REG_RXPKTBUF_1_READ 0x11A4
+#define REG_RXPKTBUF_1_WRITE 0x11A8
+#define REG_BUFF_DBGUG 0x11AC
+#define REG_RFE_CTRL_PAD_E2 0x11B0
+#define REG_RFE_CTRL_PAD_SR 0x11B4
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+#define REG_EXT_QUEUE_REG 0x11C0
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define REG_H2C_PRIORITY_SEL 0x11C0
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+#define REG_COUNTER_CONTROL 0x11C4
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+#define REG_COUNTER_CTRL 0x11C4
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+#define REG_COUNTER_TH 0x11C8
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+#define REG_COUNTER_THRESHOLD 0x11C8
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822C_SUPPORT)
+
+#define REG_COUNTER_SET 0x11CC
+#define REG_COUNTER_OVERFLOW 0x11D0
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+#define REG_TDE_LEN_TH 0x11D4
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+#define REG_TXDMA_LEN_THRESHOLD 0x11D4
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+#define REG_RDE_LEN_TH 0x11D8
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+#define REG_RXDMA_LEN_THRESHOLD 0x11D8
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+#define REG_PCIE_EXEC_TIME 0x11DC
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+#define REG_PCIE_EXEC_TIME_THRESHOLD 0x11DC
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+#define REG_FT2IMR 0x11E0
+#define REG_FT2ISR 0x11E4
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_MSG2 0x11F0
+#define REG_MSG3 0x11F4
+#define REG_MSG4 0x11F8
+#define REG_MSG5 0x11FC
+#define REG_DDMA_CH0SA 0x1200
+#define REG_DDMA_CH0DA 0x1204
+#define REG_DDMA_CH0CTRL 0x1208
+#define REG_DDMA_CH1SA 0x1210
+#define REG_DDMA_CH1DA 0x1214
+#define REG_DDMA_CH1CTRL 0x1218
+#define REG_DDMA_CH2SA 0x1220
+#define REG_DDMA_CH2DA 0x1224
+#define REG_DDMA_CH2CTRL 0x1228
+#define REG_DDMA_CH3SA 0x1230
+#define REG_DDMA_CH3DA 0x1234
+#define REG_DDMA_CH3CTRL 0x1238
+#define REG_DDMA_CH4SA 0x1240
+#define REG_DDMA_CH4DA 0x1244
+#define REG_DDMA_CH4CTRL 0x1248
+#define REG_DDMA_CH5SA 0x1250
+#define REG_DDMA_CH5DA 0x1254
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT)
+
+#define REG_REG_DDMA_CH5CTRL 0x1258
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+#define REG_DDMA_CH5CTRL 0x1258
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_DDMA_INT_MSK 0x12E0
+#define REG_DDMA_CHSTATUS 0x12E8
+#define REG_DDMA_CHKSUM 0x12F0
+#define REG_DDMA_MONITOR 0x12FC
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_STC_INT_CS 0x1300
+#define REG_ST_INT_CFG 0x1304
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define REG_ACH4_ACH5_TXBD_NUM 0x130C
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+
+#define REG_CMU_DLY_CTRL 0x1310
+#define REG_CMU_DLY_CFG 0x1314
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define REG_FWCMDQ_TXBD_IDX 0x1318
+#define REG_P0HI8Q_TXBD_IDX 0x131C
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_H2CQ_TXBD_DESA 0x1320
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define REG_H2CQ_TXBD_DESA_L 0x1320
+#define REG_H2CQ_TXBD_DESA_H 0x1324
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_H2CQ_TXBD_NUM 0x1328
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_H2CQ_TXBD_IDX 0x132C
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_H2CQ_CSR 0x1330
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define REG_P0HI9Q_TXBD_IDX 0x1334
+#define REG_P0HI10Q_TXBD_IDX 0x1338
+#define REG_P0HI11Q_TXBD_IDX 0x133C
+#define REG_P0HI12Q_TXBD_IDX 0x1340
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+#define REG_CPL_BUFFER_MONITOR 0x1344
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define REG_P0HI13Q_TXBD_IDX 0x1344
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+#define REG_PTM_LOCAL_CLOCK 0x1348
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define REG_P0HI14Q_TXBD_IDX 0x1348
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+#define REG_PTM_LOCAL_CLOCK_H 0x134C
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define REG_P0HI15Q_TXBD_IDX 0x134C
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+#define REG_TSFT_PTM_DIFF 0x1350
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+#define REG_AXI_EXCEPT_CS 0x1350
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+#define REG_CHANGE_PCIE_SPEED 0x1350
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+#define REG_PTM_CTRL_STATUS 0x1354
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+#define REG_AXI_EXCEPT_TIME 0x1354
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_DEBUG_STATE1 0x1354
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+#define REG_QUEUE_HEADER_CUR_REMAIN 0x1358
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+#define REG_HI8Q_TXBD_IDX 0x1358
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_DEBUG_STATE2 0x1358
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+#define REG_QUEUE_HEADER_MIN_REMAIN 0x135C
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+#define REG_HI9Q_TXBD_IDX 0x135C
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_DEBUG_STATE3 0x135C
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+#define REG_HI10Q_TXBD_IDX 0x1360
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define REG_ACH5_TXBD_DESA_L 0x1360
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+#define REG_HI11Q_TXBD_IDX 0x1364
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define REG_ACH5_TXBD_DESA_H 0x1364
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+#define REG_HI12Q_TXBD_IDX 0x1368
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define REG_ACH6_TXBD_DESA_L 0x1368
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+#define REG_HI13Q_TXBD_IDX 0x136C
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define REG_ACH6_TXBD_DESA_H 0x136C
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+#define REG_HI14Q_TXBD_IDX 0x1370
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define REG_ACH7_TXBD_DESA_L 0x1370
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+#define REG_HI15Q_TXBD_IDX 0x1374
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define REG_ACH7_TXBD_DESA_H 0x1374
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+#define REG_HI8Q_TXBD_DESA 0x1378
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define REG_ACH8_TXBD_DESA_L 0x1378
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_CHNL_DMA_CFG_V1 0x137C
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define REG_ACH8_TXBD_DESA_H 0x137C
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+#define REG_HI9Q_TXBD_DESA 0x1380
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define REG_ACH9_TXBD_DESA_L 0x1380
+#define REG_ACH9_TXBD_DESA_H 0x1384
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+#define REG_HI10Q_TXBD_DESA 0x1388
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define REG_ACH10_TXBD_DESA_L 0x1388
+#define REG_ACH10_TXBD_DESA_H 0x138C
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+#define REG_HI11Q_TXBD_DESA 0x1390
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define REG_ACH11_TXBD_DESA_L 0x1390
+#define REG_ACH11_TXBD_DESA_H 0x1394
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+#define REG_HI12Q_TXBD_DESA 0x1398
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define REG_ACH12_TXBD_DESA_L 0x1398
+#define REG_ACH12_TXBD_DESA_H 0x139C
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+#define REG_HI13Q_TXBD_DESA 0x13A0
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define REG_ACH13_TXBD_DESA_L 0x13A0
+#define REG_ACH13_TXBD_DESA_H 0x13A4
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+#define REG_HI14Q_TXBD_DESA 0x13A8
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define REG_HI0Q_TXBD_DESA_L 0x13A8
+#define REG_HI0Q_TXBD_DESA_H 0x13AC
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+#define REG_HI15Q_TXBD_DESA 0x13B0
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define REG_HI1Q_TXBD_DESA_L 0x13B0
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_PCIE_HISR0_V1 0x13B4
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define REG_HI1Q_TXBD_DESA_H 0x13B4
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+#define REG_HI8Q_TXBD_NUM 0x13B8
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define REG_HI2Q_TXBD_DESA_L 0x13B8
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+#define REG_HI9Q_TXBD_NUM 0x13BA
+#define REG_HI10Q_TXBD_NUM 0x13BC
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_PCIE_HISR1_V1 0x13BC
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define REG_HI2Q_TXBD_DESA_H 0x13BC
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+#define REG_HI11Q_TXBD_NUM 0x13BE
+#define REG_HI12Q_TXBD_NUM 0x13C0
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define REG_HI3Q_TXBD_DESA_L 0x13C0
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+#define REG_HI13Q_TXBD_NUM 0x13C2
+#define REG_HI14Q_TXBD_NUM 0x13C4
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define REG_HI3Q_TXBD_DESA_H 0x13C4
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+#define REG_HI15Q_TXBD_NUM 0x13C6
+#define REG_HIQ_DMA_STOP 0x13C8
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define REG_HI4Q_TXBD_DESA_L 0x13C8
+#define REG_HI4Q_TXBD_DESA_H 0x13CC
+#define REG_HI5Q_TXBD_DESA_L 0x13D0
+#define REG_HI5Q_TXBD_DESA_H 0x13D4
+#define REG_HI6Q_TXBD_DESA_L 0x13D8
+#define REG_HI6Q_TXBD_DESA_H 0x13DC
+#define REG_HI7Q_TXBD_DESA_L 0x13E0
+#define REG_HI7Q_TXBD_DESA_H 0x13E4
+#define REG_ACH8_ACH9_TXBD_NUM 0x13E8
+#define REG_ACH10_ACH11_TXBD_NUM 0x13EC
+#define REG_ACH12_ACH13_TXBD_NUM 0x13F0
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT || HALMAC_8822B_SUPPORT)
+
+#define REG_OLD_DEHANG 0x13F4
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define REG_ACH4_TXBD_DESA_L 0x13F8
+#define REG_ACH4_TXBD_DESA_H 0x13FC
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+     HALMAC_8822C_SUPPORT)
+
+#define REG_Q0_Q1_INFO 0x1400
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+#define REG_ARFR6 0x1400
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define REG_MU_OFFSET 0x1400
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+     HALMAC_8822C_SUPPORT)
+
+#define REG_Q2_Q3_INFO 0x1404
+#define REG_Q4_Q5_INFO 0x1408
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+#define REG_ARFR7 0x1408
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+     HALMAC_8822C_SUPPORT)
+
+#define REG_Q6_Q7_INFO 0x140C
+#define REG_MGQ_HIQ_INFO 0x1410
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+#define REG_ARFR8 0x1410
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+     HALMAC_8822C_SUPPORT)
+
+#define REG_CMDQ_BCNQ_INFO 0x1414
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+
+#define REG_USEREG_SETTING 0x1420
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_LOOPBACK_OPTION 0x1420
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_AESIV_SETTING 0x1424
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_BF0_TIME_SETTING 0x1428
+#define REG_BF1_TIME_SETTING 0x142C
+#define REG_BF_TIMEOUT_EN 0x1430
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_MACID_RELEASE0 0x1434
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define REG_MACID_RELEASE_INFO 0x1434
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_MACID_RELEASE1 0x1438
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define REG_MACID_RELEASE_SUCCESS_INFO 0x1438
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_MACID_RELEASE2 0x143C
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define REG_MACID_RELEASE_CTRL 0x143C
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_MACID_RELEASE3 0x1440
+#define REG_MACID_RELEASE_SETTING 0x1444
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_FAST_EDCA_VOVI_SETTING 0x1448
+#define REG_FAST_EDCA_BEBK_SETTING 0x144C
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_MACID_DROP0 0x1450
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define REG_MACID_DROP_INFO 0x1450
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_MACID_DROP1 0x1454
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define REG_MACID_DROP_CTRL 0x1454
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_MACID_DROP2 0x1458
+#define REG_MACID_DROP3 0x145C
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_R_MACID_RELEASE_SUCCESS_0 0x1460
+#define REG_R_MACID_RELEASE_SUCCESS_1 0x1464
+#define REG_R_MACID_RELEASE_SUCCESS_2 0x1468
+#define REG_R_MACID_RELEASE_SUCCESS_3 0x146C
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822B_SUPPORT)
+
+#define REG_MGG_FIFO_CRTL 0x1470
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+#define REG_MGQ_FIFO_WRITE_POINTER 0x1470
+#define REG_MGQ_FIFO_READ_POINTER 0x1472
+#define REG_MGQ_FIFO_ENABLE 0x1472
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822B_SUPPORT)
+
+#define REG_MGG_FIFO_INT 0x1474
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+#define REG_MGQ_FIFO_RELEASE_INT_MASK 0x1474
+#define REG_MGQ_FIFO_RELEASE_INT_FLAG 0x1476
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822B_SUPPORT)
+
+#define REG_MGG_FIFO_LIFETIME 0x1478
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+#define REG_MGQ_FIFO_VALID_MAP 0x1478
+#define REG_MGQ_FIFO_LIFETIME 0x147A
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET 0x147C
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+     HALMAC_8822C_SUPPORT)
+
+#define REG_SHCUT_SETTING 0x1480
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define REG_PKT_TRANS 0x1480
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_SHCUT_LLC_ETH_TYPE0 0x1484
+#define REG_SHCUT_LLC_ETH_TYPE1 0x1488
+#define REG_SHCUT_LLC_OUI0 0x148C
+#define REG_SHCUT_LLC_OUI1 0x1490
+#define REG_SHCUT_LLC_OUI2 0x1494
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+     HALMAC_8822B_SUPPORT)
+
+#define REG_SHCUT_LLC_OUI3 0x1498
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define REG_FWCMDQ_CTRL 0x14A0
+#define REG_FWCMDQ_PAGE 0x14A4
+#define REG_FWCMDQ_INFO 0x14A8
+#define REG_FWCMDQ_HOLD_PKTNUM 0x14AC
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+#define REG_MU_TX_CTL 0x14C0
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define REG_MU_TX_CTRL 0x14C0
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_MU_STA_GID_VLD 0x14C4
+#define REG_MU_STA_USER_POS_INFO 0x14C8
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+#define REG_MU_STA_USER_POS_INFO_H 0x14CC
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_CHNL_INFO_CTRL 0x14D0
+
+#endif
+
+#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+
+#define REG_MU_TRX_DBG_CNT 0x14D0
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_CHNL_IDLE_TIME 0x14D4
+#define REG_CHNL_BUSY_TIME 0x14D8
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_MU_TRX_DBG_CNT_V1 0x14DC
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+#define REG_NEW_EDCA_CTRL 0x14F0
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT)
+
+#define REG_SU_DURATION 0x14F0
+#define REG_MU_DURATION 0x14F2
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT)
+
+#define REG_SWPS_CTRL 0x14F4
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT)
+
+#define REG_HW_NDPA_RTY_LIMIT 0x14F4
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT)
+
+#define REG_SWPS_PKT_TH 0x14F6
+#define REG_SWPS_TIME_TH 0x14F8
+#define REG_MACID_SWPS_EN 0x14FC
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_CPUMGQ_TX_TIMER 0x1500
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define REG_PORT_CTRL_SEL 0x1500
+#define REG_PORT_CTRL_CFG 0x1501
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_PS_TIMER_A 0x1504
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define REG_TBTT_PROHIBIT_CFG 0x1504
+#define REG_DRVERLYINT_CFG 0x1507
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_PS_TIMER_B 0x1508
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define REG_BCNDMATIM_CFG 0x1508
+#define REG_CTWND_CFG 0x1509
+#define REG_BCNIVLCUNT_CFG 0x150A
+#define REG_EARLY_128US_CFG 0x150B
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_PS_TIMER_C 0x150C
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define REG_TSFTR_SYNC_OFFSET_CFG 0x150C
+#define REG_TSFTR_SYNC_CTRL_CFG 0x150F
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_PS_TIMER_ABC_CPUMGQ_TIMER_CRTL 0x1510
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define REG_BCN_SPACE_CFG 0x1510
+#define REG_EARLY_INT_ADJUST_CFG 0x1512
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_CPUMGQ_TX_TIMER_EARLY 0x1514
+#define REG_PS_TIMER_A_EARLY 0x1515
+#define REG_PS_TIMER_B_EARLY 0x1516
+#define REG_PS_TIMER_C_EARLY 0x1517
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_CPUMGQ_PARAMETER 0x1518
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define REG_SW_TBTT_TSF_INFO 0x151C
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+#define REG_TSF_SYN_CTRL0 0x1520
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_TSF_SYNC_ADJ 0x1520
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define REG_TSFTR_LOW 0x1520
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+#define REG_TSF_SYN_CTRL1 0x1521
+#define REG_TSF_SYN_OFFSET0 0x1522
+#define REG_TSF_SYN_OFFSET1 0x1524
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_TSF_ADJ_VLAUE 0x1524
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define REG_TSFTR_HIGH 0x1524
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+#define REG_TSF_SYN_OFFSET2 0x1528
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_TSF_ADJ_VLAUE_2 0x1528
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define REG_BCN_ERR_CNT_MAC 0x1528
+#define REG_BCN_ERR_CNT_EDCCA 0x1529
+#define REG_BCN_ERR_CNT_CCA 0x152A
+#define REG_BCN_ERR_CNT_INVALID 0x152B
+#define REG_BCN_ERR_CNT_OTHERS 0x152C
+#define REG_RX_BCN_TIMER 0x152D
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+#define REG_TSF_SYN_COMPARE_VALUE 0x1530
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define REG_TBTT_CTN_AREA_V1 0x1530
+#define REG_BCN_MAX_ERR_V1 0x1531
+#define REG_RXTSF_OFFSET_CCK_V1 0x1532
+#define REG_RXTSF_OFFSET_OFDM_V1 0x1533
+#define REG_SUB_BCN_SPACE 0x1534
+#define REG_MBID_NUM_V1 0x1535
+#define REG_MBSSID_CTRL_V1 0x1536
+#define REG_USTIME_TSF_V1 0x1538
+#define REG_BW_CFG 0x1539
+#define REG_ATIMWND_CFG 0x153A
+#define REG_DTIM_COUNTER_CFG 0x153B
+#define REG_ATIM_DTIM_CTRL_SEL 0x153C
+#define REG_ATIMUGT_V1 0x153D
+#define REG_BCNDROPCTRL_V1 0x153E
+#define REG_DIS_ATIM_V1 0x1540
+#define REG_HIQ_NO_LMT_EN_V1 0x1544
+#define REG_P2PPS_CTRL_V1 0x1548
+#define REG_P2PPS_SPEC_STATE_V1 0x154A
+#define REG_P2PPS_STATE_V1 0x154B
+#define REG_P2PPS1_CTRL_V1 0x154C
+#define REG_P2PPS1_SPEC_STATE_V1 0x154E
+#define REG_P2PPS1_STATE_V1 0x154F
+#define REG_P2PPS2_CTRL_V1 0x1550
+#define REG_P2PPS2_SPEC_STATE_V1 0x1552
+#define REG_P2PPS2_STATE_V1 0x1553
+#define REG_P2PON_DIS_TXTIME_V1 0x1554
+#define REG_P2POFF_DIS_TXTIME_V1 0x1555
+#define REG_CHG_POWER_BCN_AREA 0x1556
+#define REG_NOA_SEL 0x1557
+#define REG_NOA_PARAM_V1 0x1558
+#define REG_NOA_PARAM_1_V1 0x155C
+#define REG_NOA_PARAM_2_V1 0x1560
+#define REG_NOA_PARAM_3_V1 0x1564
+#define REG_NOA_ON_ERLY_TIME_V1 0x1568
+#define REG_NOA_OFF_ERLY_TIME_V1 0x1569
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_P2PPS_HW_AUTO_PAUSE_CTRL 0x156C
+#define REG_P2PPS1_HW_AUTO_PAUSE_CTRL 0x1570
+#define REG_P2PPS2_HW_AUTO_PAUSE_CTRL 0x1574
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define REG_RX_TBTT_SHIFT 0x1578
+#define REG_FREERUN_CNT_LOW 0x1580
+#define REG_FREERUN_CNT_HIGH 0x1584
+#define REG_CPUMGQ_TX_TIMER_V1 0x1588
+#define REG_PS_TIMER_0 0x158C
+#define REG_PS_TIMER_1 0x1590
+#define REG_PS_TIMER_2 0x1594
+#define REG_PS_TIMER_3 0x1598
+#define REG_PS_TIMER_4 0x159C
+#define REG_PS_TIMER_5 0x15A0
+#define REG_PS_TIMER_01_CTRL 0x15A4
+#define REG_PS_TIMER_23_CTRL 0x15A8
+#define REG_PS_TIMER_45_CTRL 0x15AC
+#define REG_CPUMGQ_FREERUN_TIMER_CTRL 0x15B0
+#define REG_CPUMGQ_PROHIBIT 0x15B4
+#define REG_TIMER_COMPARE 0x15C0
+#define REG_TIMER_COMPARE_VALUE_LOW 0x15C4
+#define REG_TIMER_COMPARE_VALUE_HIGH 0x15C8
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_SCHEDULER_COUNTER 0x15D0
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_BCN_PSR_RPT2 0x1600
+#define REG_BCN_PSR_RPT3 0x1604
+#define REG_BCN_PSR_RPT4 0x1608
+#define REG_A1_ADDR_MASK 0x160C
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_RXPSF_CTRL 0x1610
+#define REG_RXPSF_TYPE_CTRL 0x1614
+#define REG_CAM_ACCESS_CTRL 0x1618
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_HT_SND_REF_RATE 0x161C
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define REG_CUT_AMSDU_CTRL 0x161C
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_MACID2 0x1620
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+#define REG_MACID2_H 0x1624
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_BSSID2 0x1628
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+#define REG_BSSID2_H 0x162C
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_MACID3 0x1630
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+#define REG_MACID3_H 0x1634
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_BSSID3 0x1638
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+#define REG_BSSID3_H 0x163C
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_MACID4 0x1640
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+#define REG_MACID4_H 0x1644
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+     HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_BSSID4 0x1648
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+#define REG_BSSID4_H 0x164C
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+#define REG_NOA_REPORT 0x1650
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+#define REG_NOA_REPORT_1 0x1654
+#define REG_NOA_REPORT_2 0x1658
+#define REG_NOA_REPORT_3 0x165C
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+#define REG_PWRBIT_SETTING 0x1660
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_GENERAL_OPTION 0x1664
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define REG_FWPHYFF_RCR 0x1668
+#define REG_ADDRCAM_WRITE_CONTENT 0x166C
+#define REG_ADDRCAM_READ_CONTENT 0x1670
+#define REG_ADDRCAM_CFG 0x1674
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+#define REG_WMAC_CSI_FRAME_RRSR_SETTING 0x1678
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_CSI_RRSR 0x1678
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822B_SUPPORT)
+
+#define REG_WMAC_MU_BF_OPTION 0x167C
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+#define REG_MU_BF_OPTION 0x167C
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_WMAC_PAUSE_BB_CLR_TH 0x167D
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT)
+
+#define REG_WMAC_MU_ARB 0x167E
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG__WMAC_MULBK_BUF 0x167E
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define REG_WMAC_MULBK_BUF 0x167E
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+#define REG_WMAC_MU_OPTION 0x167F
+#define REG_WMAC_MU_BF_CTL 0x1680
+#define REG_WMAC_MU_BFRPT_PARA 0x1682
+#define REG_WMAC_ASSOCIATED_MU_BFMEE2 0x1684
+#define REG_WMAC_ASSOCIATED_MU_BFMEE3 0x1686
+#define REG_WMAC_ASSOCIATED_MU_BFMEE4 0x1688
+#define REG_WMAC_ASSOCIATED_MU_BFMEE5 0x168A
+#define REG_WMAC_ASSOCIATED_MU_BFMEE6 0x168C
+#define REG_WMAC_ASSOCIATED_MU_BFMEE7 0x168E
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+#define REG_WMAC_BB_STOP_RX_COUNTER 0x1690
+#define REG_WMAC_PLCP_MONITOR 0x1694
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_WMAC_PLCP_MONITOR_MUTX 0x1698
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define REG_WMAC_DEBUG_PORT 0x1698
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_WMAC_CSIDMA_CFG 0x169C
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+#define REG_TRANSMIT_ADDRSS_0 0x16A0
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+#define REG_TRANSMIT_ADDRSS_0_H 0x16A4
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+#define REG_TRANSMIT_ADDRSS_1 0x16A8
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+#define REG_TRANSMIT_ADDRSS_1_H 0x16AC
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+#define REG_TRANSMIT_ADDRSS_2 0x16B0
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+#define REG_TRANSMIT_ADDRSS_2_H 0x16B4
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+#define REG_TRANSMIT_ADDRSS_3 0x16B8
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+#define REG_TRANSMIT_ADDRSS_3_H 0x16BC
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT ||   \
+     HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+#define REG_TRANSMIT_ADDRSS_4 0x16C0
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+#define REG_TRANSMIT_ADDRSS_4_H 0x16C4
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT)
+
+#define REG_SND_AID12 0x16D0
+#define REG_SND_PKT_INFO 0x16D2
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_WL2LTECOEX_INDIRECT_ACCESS_CTRL_V1 0x1700
+#define REG_WL2LTECOEX_INDIRECT_ACCESS_WRITE_DATA_V1 0x1704
+#define REG_WL2LTECOEX_INDIRECT_ACCESS_READ_DATA_V1 0x1708
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define REG_BIST_RSTN0 0x2100
+#define REG_BIST_RSTN2 0x2108
+#define REG_BIST_MODE_NRML0 0x2110
+#define REG_BIST_MODE_NRML1 0x2114
+#define REG_BIST_MODE_NRML2 0x2118
+#define REG_BIST_MODE_NRML3 0x211C
+#define REG_BIST_DONE_NRML_MAC 0x2150
+#define REG_BIST_DONE_NRML1 0x2158
+#define REG_BIST_DONE_DRF_MAC 0x2160
+#define REG_BIST_DONE_DRF 0x2164
+#define REG_BIST_DONE_DRF1 0x2168
+#define REG_BIST_FAIL_NRML_MAC 0x2170
+#define REG_BIST_FAIL_NRML 0x2174
+#define REG_BIST_FAIL_NRML1 0x2178
+#define REG_BIST_FAIL_NRML_MAC_V1 0x2180
+#define REG_BIST_FAIL_NRML_V1 0x2184
+#define REG_BIST_FAIL_NRML1_V1 0x2188
+#define REG_BIST_MISR_DATAOUT 0x2190
+#define REG_BIST_MISR_DATAOUT1 0x2194
+#define REG_BIST_MISR_DATAOUT_CPU 0x2198
+#define REG_BIST_MISR_DATAOUT_CPU1 0x219C
+#define REG_BIST_MISR_DATAOUT_CPU2 0x21A0
+#define REG_BIST_MISR_DATOUT_CPU3 0x21A4
+#define REG_DMA_RQPN_INFO_0 0x2200
+#define REG_DMA_RQPN_INFO_1 0x2204
+#define REG_DMA_RQPN_INFO_2 0x2208
+#define REG_DMA_RQPN_INFO_3 0x220C
+#define REG_DMA_RQPN_INFO_4 0x2210
+#define REG_DMA_RQPN_INFO_5 0x2214
+#define REG_DMA_RQPN_INFO_6 0x2218
+#define REG_DMA_RQPN_INFO_7 0x221C
+#define REG_DMA_RQPN_INFO_8 0x2220
+#define REG_DMA_RQPN_INFO_9 0x2224
+#define REG_DMA_RQPN_INFO_10 0x2228
+#define REG_DMA_RQPN_INFO_11 0x222C
+#define REG_DMA_RQPN_INFO_12 0x2230
+#define REG_DMA_RQPN_INFO_13 0x2234
+#define REG_DMA_RQPN_INFO_14 0x2238
+#define REG_DMA_RQPN_INFO_15 0x223C
+#define REG_DMA_RQPN_INFO_16 0x2240
+#define REG_HWAMSDU_CTL1 0x2250
+#define REG_HWAMSDU_CTL2 0x2254
+#define REG_HI8Q_TXBD_DESA_L 0x2300
+#define REG_HI8Q_TXBD_DESA_H 0x2304
+#define REG_HI9Q_TXBD_DESA_L 0x2308
+#define REG_HI9Q_TXBD_DESA_H 0x230C
+#define REG_HI10Q_TXBD_DESA_L 0x2310
+#define REG_HI10Q_TXBD_DESA_H 0x2314
+#define REG_HI11Q_TXBD_DESA_L 0x2318
+#define REG_HI11Q_TXBD_DESA_H 0x231C
+#define REG_HI12Q_TXBD_DESA_L 0x2320
+#define REG_HI12Q_TXBD_DESA_H 0x2324
+#define REG_HI13Q_TXBD_DESA_L 0x2328
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+#define REG_H2CQ_TXBD_IDX_V1 0x232C
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define REG_HI13Q_TXBD_DESA_H 0x232C
+#define REG_HI14Q_TXBD_DESA_L 0x2330
+#define REG_HI14Q_TXBD_DESA_H 0x2334
+#define REG_HI15Q_TXBD_DESA_L 0x2338
+#define REG_HI15Q_TXBD_DESA_H 0x233C
+#define REG_HI16Q_TXBD_DESA_L 0x2340
+#define REG_HI16Q_TXBD_DESA_H 0x2344
+#define REG_HI17Q_TXBD_DESA_L 0x2348
+#define REG_HI17Q_TXBD_DESA_H 0x234C
+#define REG_HI18Q_TXBD_DESA_L 0x2350
+#define REG_HI18Q_TXBD_DESA_H 0x2354
+#define REG_HI19Q_TXBD_DESA_L 0x2358
+#define REG_HI19Q_TXBD_DESA_H 0x235C
+#define REG_BD_RWPTR_CLR6 0x2364
+#define REG_P0HI16Q_TXBD_IDX 0x2370
+#define REG_P0HI17Q_TXBD_IDX 0x2374
+#define REG_P0HI18Q_TXBD_IDX 0x2378
+#define REG_P0HI19Q_TXBD_IDX 0x237C
+#define REG_P0HI16Q_HI17Q_TXBD_NUM 0x2380
+#define REG_P0HI18Q_HI19Q_TXBD_NUM 0x2384
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_PCIE_HISR2_V1 0x23B4
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define REG_PCIE_HISR0 0x23B4
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_PCIE_HISR3_V1 0x23BC
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define REG_PCIE_HISR1 0x23BC
+#define REG_P0HI8Q_HI9Q_TXBD_NUM 0x23C0
+#define REG_P0HI10Q_HI11Q_TXBD_NUM 0x23C4
+#define REG_P0HI12Q_HI13Q_TXBD_NUM 0x23C8
+#define REG_P0HI14Q_HI15Q_TXBD_NUM 0x23CC
+#define REG_ACH6_ACH7_TXBD_NUM 0x23F0
+
+#endif
+
+#if (HALMAC_8192F_SUPPORT)
+
+#define REG_BF0_TIME_SETTING_V1 0x2428
+#define REG_BF1_TIME_SETTING_V1 0x242C
+#define REG_BF_TIMEOUT_EN_V1 0x2430
+#define REG_MACID_RELEASE0_V1 0x2434
+#define REG_MACID_RELEASE1_V1 0x2438
+#define REG_MACID_RELEASE2_V1 0x243C
+#define REG_MACID_RELEASE3_V1 0x2440
+#define REG_MACID_RELEASE_SETTING_V1 0x2444
+#define REG_FAST_EDCA_VOVI_SETTING_V1 0x2448
+#define REG_FAST_EDCA_BEBK_SETTING_V1 0x244C
+#define REG_R_MACID_RELEASE_SUCCESS_0_V1 0x2460
+#define REG_R_MACID_RELEASE_SUCCESS_1_V1 0x2464
+#define REG_R_MACID_RELEASE_SUCCESS_2_V1 0x2468
+#define REG_R_MACID_RELEASE_SUCCESS_3_V1 0x246C
+#define REG_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_V1 0x247C
+#define REG_NAN_INFO0 0x2480
+#define REG_NAN_INFO1 0x2484
+#define REG_NAN_INFO2 0x2488
+#define REG_NAN_INFO3 0x248C
+#define REG_NAN_INFO4 0x2490
+#define REG_NAN_INFO5 0x2494
+#define REG_NAN_INFO6 0x2498
+#define REG_NAN_INFO7 0x249C
+#define REG_NAN_INFO8 0x24A0
+#define REG_NAN_INFO9 0x24A4
+#define REG_CHNL_INFO_CTRL_V1 0x24D0
+#define REG_CHNL_IDLE_TIME_V1 0x24D4
+#define REG_CHNL_BUSY_TIME_V1 0x24D8
+#define REG_SWPS_CTRL_V1 0x24F4
+#define REG_SWPS_PKT_TH_V1 0x24F6
+#define REG_SWPS_TIME_TH_V1 0x24F8
+#define REG_MACID_SWPS_EN_V1 0x24FC
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define REG_TXPAGE_INT_CTRL_0 0x3200
+#define REG_TXPAGE_INT_CTRL_1 0x3204
+#define REG_TXPAGE_INT_CTRL_2 0x3208
+#define REG_TXPAGE_INT_CTRL_3 0x320C
+#define REG_TXPAGE_INT_CTRL_4 0x3210
+#define REG_TXPAGE_INT_CTRL_5 0x3214
+#define REG_TXPAGE_INT_CTRL_6 0x3218
+#define REG_TXPAGE_INT_CTRL_7 0x321C
+#define REG_TXPAGE_INT_CTRL_8 0x3220
+#define REG_TXPAGE_INT_CTRL_9 0x3224
+#define REG_TXPAGE_INT_CTRL_10 0x3228
+#define REG_TXPAGE_INT_CTRL_11 0x322C
+#define REG_TXPAGE_INT_CTRL_12 0x3230
+#define REG_TXPAGE_INT_CTRL_13 0x3234
+#define REG_TXPAGE_INT_CTRL_14 0x3238
+#define REG_TXPAGE_INT_CTRL_15 0x323C
+#define REG_TXPAGE_INT_CTRL_16 0x3240
+#define REG_ACH4_TXBD_IDX 0x3340
+#define REG_ACH5_TXBD_IDX 0x3344
+#define REG_ACH6_TXBD_IDX 0x3348
+#define REG_ACH7_TXBD_IDX 0x334C
+#define REG_ACH8_TXBD_IDX 0x3350
+#define REG_ACH9_TXBD_IDX 0x3354
+#define REG_ACH10_TXBD_IDX 0x3358
+#define REG_ACH11_TXBD_IDX 0x335C
+#define REG_ACH12_TXBD_IDX 0x3360
+#define REG_ACH13_TXBD_IDX 0x3364
+#define REG_AC_CHANNEL0_WEIGHT 0x3368
+#define REG_AC_CHANNEL1_WEIGHT 0x3369
+#define REG_AC_CHANNEL2_WEIGHT 0x336A
+#define REG_AC_CHANNEL3_WEIGHT 0x336B
+#define REG_AC_CHANNEL4_WEIGHT 0x336C
+#define REG_AC_CHANNEL5_WEIGHT 0x336D
+#define REG_AC_CHANNEL6_WEIGHT 0x336E
+#define REG_AC_CHANNEL7_WEIGHT 0x336F
+#define REG_AC_CHANNEL8_WEIGHT 0x3370
+#define REG_AC_CHANNEL9_WEIGHT 0x3371
+#define REG_AC_CHANNEL10_WEIGHT 0x3372
+#define REG_AC_CHANNEL11_WEIGHT 0x3373
+#define REG_AC_CHANNEL12_WEIGHT 0x3374
+#define REG_AC_CHANNEL13_WEIGHT 0x3375
+#define REG_PCIE_HISR2 0x33B4
+#define REG_PCIE_HISR3 0x33BC
+
+#endif
+
+/* ----------------------------------------------------- */
+/*	*/
+/* 0xFB00h ~ 0xFCFFh	TX/RX packet buffer affress */
+/*	*/
+/* ----------------------------------------------------- */
+#define REG_RXPKTBUF_STARTADDR 0xFB00
+#define REG_TXPKTBUF_STARTADDR 0xFC00
+
+/* ----------------------------------------------------- */
+/*	*/
+/* 0xFD00h ~ 0xFDFFh	8051 CPU Local REG */
+/*	*/
+/* ----------------------------------------------------- */
+#define REG_SYS_CTRL 0xFD00
+#define REG_PONSTS_RPT1 0xFD01
+#define REG_PONSTS_RPT2 0xFD02
+#define REG_PONSTS_RPT3 0xFD03
+#define REG_PONSTS_RPT4 0xFD04 /* 0x84 */
+#define REG_PONSTS_RPT5 0xFD05 /* 0x85 */
+#define REG_8051ERRFLAG 0xFD08
+#define REG_8051ERRFLAG_MASK 0xFD09
+#define REG_TXADDRH 0xFD10 /* Tx Packet High Address */
+#define REG_RXADDRH 0xFD11 /* Rx Packet High Address */
+#define REG_TXADDRH_EXT 0xFD12
+
+#define REG_U3_STATE 0xFD48
+
+/* for MAILBOX */
+#define REG_OUTDATA0 0xFD50
+#define REG_OUTDATA1 0xFD54
+#define REG_OUTRDY 0xFD58 /* bit[0] : OutReady, bit[1] : OutEmptyIntEn */
+
+#define REG_INDATA0 0xFD60
+#define REG_INDATA1 0xFD64
+#define REG_INRDY 0xFD68 /* bit[0] : InReady, bit[1] : InRdyIntEn */
+
+/* MCU ERROR debug REG */
+#define REG_MCUERR_PCLSB 0xFD90 /* PC[7:0] */
+#define REG_MCUERR_PCMSB 0xFD91 /* PC[15:8] */
+#define REG_MCUERR_ACC 0xFD92
+#define REG_MCUERR_B 0xFD93
+#define REG_MCUERR_DPTRLSB 0xFD94 /* DPTR[7:0] */
+#define REG_MCUERR_DPTRMSB 0xFD95 /* DPTR[15:8] */
+#define REG_MCUERR_SP 0xFD96 /* SP[7:0] */
+#define REG_MCUERR_IE 0xFD97 /* IE[7:0] */
+#define REG_MCUERR_EIE 0xFD98 /* EIE[7:0] */
+#define REG_VERA_SIM 0xFD9F
+/* 0xFD99~0xFD9F are reserved.. */
+
+/* ----------------------------------------------------- */
+/*	*/
+/* 0xFE00h ~ 0xFEFFh	USB Configuration */
+/*	*/
+/* ----------------------------------------------------- */
+
+/* RTS5101 USB Register Definition */
+#define REG_USB_SETUP_DEC_INT 0xFE00
+#define REG_USB_DMACTL 0xFE01
+#define REG_USB_IRQSTAT0 0xFE02
+#define REG_USB_IRQSTAT1 0xFE03
+#define REG_USB_IRQEN0 0xFE04
+#define REG_USB_IRQEN1 0xFE05
+#define REG_USB_AUTOPTRL 0xFE06
+#define REG_USB_AUTOPTRH 0xFE07
+#define REG_USB_AUTODAT 0xFE08
+
+#define REG_USB_SCRATCH0 0xFE09
+#define REG_USB_SCRATCH1 0xFE0A
+#define REG_USB_SEEPROM 0xFE0B
+#define REG_USB_GPIO0 0xFE0C
+#define REG_USB_GPIO0DIR 0xFE0D
+#define REG_USB_CLKSEL 0xFE0E
+#define REG_USB_BOOTCTL 0xFE0F
+
+#define REG_USB_USBCTL 0xFE10
+#define REG_USB_USBSTAT 0xFE11
+#define REG_USB_DEVADDR 0xFE12
+#define REG_USB_USBTEST 0xFE13
+#define REG_USB_FNUM0 0xFE14
+#define REG_USB_FNUM1 0xFE15
+
+#define REG_USB_EP_IDX 0xFE20
+#define REG_USB_EP_CFG 0xFE21
+#define REG_USB_EP_CTL 0xFE22
+#define REG_USB_EP_STAT 0xFE23
+#define REG_USB_EP_IRQ 0xFE24
+#define REG_USB_EP_IRQEN 0xFE25
+#define REG_USB_EP_MAXPKT0 0xFE26
+#define REG_USB_EP_MAXPKT1 0xFE27
+#define REG_USB_EP_DAT 0xFE28
+#define REG_USB_EP_BC0 0xFE29
+#define REG_USB_EP_BC1 0xFE2A
+#define REG_USB_EP_TC0 0xFE2B
+#define REG_USB_EP_TC1 0xFE2C
+#define REG_USB_EP_TC2 0xFE2D
+#define REG_USB_EP_CTL2 0xFE2E
+
+#define REG_USB_INFO 0xFE17
+#define REG_USB_SPECIAL_OPTION 0xFE55
+#define REG_USB_DMA_AGG_TO 0xFE5B
+#define REG_USB_AGG_TO 0xFE5C
+#define REG_USB_AGG_TH 0xFE5D
+
+#define REG_USB_VID 0xFE60
+#define REG_USB_PID 0xFE62
+#define REG_USB_OPT 0xFE64
+#define REG_USB_CONFIG 0xFE65
+
+#define REG_USB_PHY_PARA1 0xFE68
+#define REG_USB_PHY_PARA2 0xFE69
+#define REG_USB_PHY_PARA3 0xFE6A
+#define REG_USB_PHY_PARA4 0xFE6B
+#define REG_USB_OPT2 0xFE6C
+#define REG_USB_MAC_ADDR 0xFE70
+#define REG_USB_MANUFACTURE_SETTING 0xFE80
+#define REG_USB_PRODUCT_STRING 0xFEA0
+#define REG_USB_SERIAL_NUMBER_STRING 0xFED0
+
+#define REG_USB_ALTERNATE_SETTING 0xFE4F
+#define REG_USB_INT_BINTERVAL 0xFE6E
+#define REG_USB_GPS_EP_CONFIG 0xFE6D
+
+#endif /* __HALMAC_COM_REG_H__ */
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/halmac/halmac_reg_8197f.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/halmac/halmac_reg_8197f.h
--- linux-5.6.3/3rdparty/rtl8821ce/hal/halmac/halmac_reg_8197f.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/halmac/halmac_reg_8197f.h	2020-04-10 16:35:06.816660067 +0300
@@ -0,0 +1,700 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ ******************************************************************************/
+
+#ifndef __INC_HALMAC_REG_8197F_H
+#define __INC_HALMAC_REG_8197F_H
+
+#define REG_SYS_ISO_CTRL_8197F 0x0000
+#define REG_SYS_FUNC_EN_8197F 0x0002
+#define REG_SYS_PW_CTRL_8197F 0x0004
+#define REG_SYS_CLK_CTRL_8197F 0x0008
+#define REG_SYS_EEPROM_CTRL_8197F 0x000A
+#define REG_EE_VPD_8197F 0x000C
+#define REG_SYS_SWR_CTRL1_8197F 0x0010
+#define REG_SYS_SWR_CTRL2_8197F 0x0014
+#define REG_SYS_SWR_CTRL3_8197F 0x0018
+#define REG_RSV_CTRL_8197F 0x001C
+#define REG_RF0_CTRL_8197F 0x001F
+#define REG_AFE_LDO_CTRL_8197F 0x0020
+#define REG_AFE_CTRL1_8197F 0x0024
+#define REG_AFE_CTRL2_8197F 0x0028
+#define REG_AFE_CTRL3_8197F 0x002C
+#define REG_EFUSE_CTRL_8197F 0x0030
+#define REG_LDO_EFUSE_CTRL_8197F 0x0034
+#define REG_PWR_OPTION_CTRL_8197F 0x0038
+#define REG_CAL_TIMER_8197F 0x003C
+#define REG_ACLK_MON_8197F 0x003E
+#define REG_GPIO_MUXCFG_8197F 0x0040
+#define REG_GPIO_PIN_CTRL_8197F 0x0044
+#define REG_GPIO_INTM_8197F 0x0048
+#define REG_LED_CFG_8197F 0x004C
+#define REG_FSIMR_8197F 0x0050
+#define REG_FSISR_8197F 0x0054
+#define REG_HSIMR_8197F 0x0058
+#define REG_HSISR_8197F 0x005C
+#define REG_GPIO_EXT_CTRL_8197F 0x0060
+#define REG_PAD_CTRL1_8197F 0x0064
+#define REG_WL_BT_PWR_CTRL_8197F 0x0068
+#define REG_SDM_DEBUG_8197F 0x006C
+#define REG_SYS_SDIO_CTRL_8197F 0x0070
+#define REG_HCI_OPT_CTRL_8197F 0x0074
+#define REG_AFE_CTRL4_8197F 0x0078
+#define REG_LDO_SWR_CTRL_8197F 0x007C
+#define REG_MCUFW_CTRL_8197F 0x0080
+#define REG_MCU_TST_CFG_8197F 0x0084
+#define REG_HMEBOX_E0_E1_8197F 0x0088
+#define REG_HMEBOX_E2_E3_8197F 0x008C
+#define REG_WLLPS_CTRL_8197F 0x0090
+#define REG_AFE_CTRL5_8197F 0x0094
+#define REG_GPIO_DEBOUNCE_CTRL_8197F 0x0098
+#define REG_RPWM2_8197F 0x009C
+#define REG_SYSON_FSM_MON_8197F 0x00A0
+#define REG_AFE_CTRL6_8197F 0x00A4
+#define REG_PMC_DBG_CTRL1_8197F 0x00A8
+#define REG_AFE_CTRL7_8197F 0x00AC
+#define REG_HIMR0_8197F 0x00B0
+#define REG_HISR0_8197F 0x00B4
+#define REG_HIMR1_8197F 0x00B8
+#define REG_HISR1_8197F 0x00BC
+#define REG_DBG_PORT_SEL_8197F 0x00C0
+#define REG_PAD_CTRL2_8197F 0x00C4
+#define REG_PMC_DBG_CTRL2_8197F 0x00CC
+#define REG_BIST_CTRL_8197F 0x00D0
+#define REG_BIST_RPT_8197F 0x00D4
+#define REG_MEM_CTRL_8197F 0x00D8
+#define REG_AFE_CTRL8_8197F 0x00DC
+#define REG_USB_SIE_INTF_8197F 0x00E0
+#define REG_PCIE_MIO_INTF_8197F 0x00E4
+#define REG_PCIE_MIO_INTD_8197F 0x00E8
+#define REG_WLRF1_8197F 0x00EC
+#define REG_SYS_CFG1_8197F 0x00F0
+#define REG_SYS_STATUS1_8197F 0x00F4
+#define REG_SYS_STATUS2_8197F 0x00F8
+#define REG_SYS_CFG2_8197F 0x00FC
+#define REG_SYS_CFG3_8197F 0x1000
+#define REG_SYS_CFG4_8197F 0x1034
+#define REG_CPU_DMEM_CON_8197F 0x1080
+#define REG_HIMR2_8197F 0x10B0
+#define REG_HISR2_8197F 0x10B4
+#define REG_HIMR3_8197F 0x10B8
+#define REG_HISR3_8197F 0x10BC
+#define REG_SW_MDIO_8197F 0x10C0
+#define REG_SW_FLUSH_8197F 0x10C4
+#define REG_DBG_GPIO_BMUX_8197F 0x10C8
+#define REG_FPGA_TAG_8197F 0x10CC
+#define REG_WL_DSS_CTRL0_8197F 0x10D0
+#define REG_WL_DSS_CTRL1_8197F 0x10D8
+#define REG_WL_DSS_STATUS1_8197F 0x10DC
+#define REG_FW_DBG0_8197F 0x10E0
+#define REG_FW_DBG1_8197F 0x10E4
+#define REG_FW_DBG2_8197F 0x10E8
+#define REG_FW_DBG3_8197F 0x10EC
+#define REG_FW_DBG4_8197F 0x10F0
+#define REG_FW_DBG5_8197F 0x10F4
+#define REG_FW_DBG6_8197F 0x10F8
+#define REG_FW_DBG7_8197F 0x10FC
+#define REG_CR_8197F 0x0100
+#define REG_TSF_CLK_STATE_8197F 0x0108
+#define REG_TXDMA_PQ_MAP_8197F 0x010C
+#define REG_TRXFF_BNDY_8197F 0x0114
+#define REG_PTA_I2C_MBOX_8197F 0x0118
+#define REG_RXFF_BNDY_8197F 0x011C
+#define REG_FE1IMR_8197F 0x0120
+#define REG_FE1ISR_8197F 0x0124
+#define REG_CPWM_8197F 0x012C
+#define REG_FWIMR_8197F 0x0130
+#define REG_FWISR_8197F 0x0134
+#define REG_FTIMR_8197F 0x0138
+#define REG_FTISR_8197F 0x013C
+#define REG_PKTBUF_DBG_CTRL_8197F 0x0140
+#define REG_PKTBUF_DBG_DATA_L_8197F 0x0144
+#define REG_PKTBUF_DBG_DATA_H_8197F 0x0148
+#define REG_CPWM2_8197F 0x014C
+#define REG_TC0_CTRL_8197F 0x0150
+#define REG_TC1_CTRL_8197F 0x0154
+#define REG_TC2_CTRL_8197F 0x0158
+#define REG_TC3_CTRL_8197F 0x015C
+#define REG_TC4_CTRL_8197F 0x0160
+#define REG_TCUNIT_BASE_8197F 0x0164
+#define REG_TC5_CTRL_8197F 0x0168
+#define REG_TC6_CTRL_8197F 0x016C
+#define REG_MBIST_FAIL_8197F 0x0170
+#define REG_MBIST_START_PAUSE_8197F 0x0174
+#define REG_MBIST_DONE_8197F 0x0178
+#define REG_MBIST_FAIL_NRML_8197F 0x017C
+#define REG_AES_DECRPT_DATA_8197F 0x0180
+#define REG_AES_DECRPT_CFG_8197F 0x0184
+#define REG_MACCLKFRQ_8197F 0x018C
+#define REG_TMETER_8197F 0x0190
+#define REG_OSC_32K_CTRL_8197F 0x0194
+#define REG_32K_CAL_REG1_8197F 0x0198
+#define REG_C2HEVT_8197F 0x01A0
+#define REG_SW_DEFINED_PAGE1_8197F 0x01B8
+#define REG_MCUTST_I_8197F 0x01C0
+#define REG_MCUTST_II_8197F 0x01C4
+#define REG_FMETHR_8197F 0x01C8
+#define REG_HMETFR_8197F 0x01CC
+#define REG_HMEBOX0_8197F 0x01D0
+#define REG_HMEBOX1_8197F 0x01D4
+#define REG_HMEBOX2_8197F 0x01D8
+#define REG_HMEBOX3_8197F 0x01DC
+#define REG_LLT_INIT_8197F 0x01E0
+#define REG_LLT_INIT_ADDR_8197F 0x01E4
+#define REG_BB_ACCESS_CTRL_8197F 0x01E8
+#define REG_BB_ACCESS_DATA_8197F 0x01EC
+#define REG_HMEBOX_E0_8197F 0x01F0
+#define REG_HMEBOX_E1_8197F 0x01F4
+#define REG_HMEBOX_E2_8197F 0x01F8
+#define REG_HMEBOX_E3_8197F 0x01FC
+#define REG_CR_EXT_8197F 0x1100
+#define REG_FWFF_8197F 0x1114
+#define REG_RXFF_PTR_V1_8197F 0x1118
+#define REG_RXFF_WTR_V1_8197F 0x111C
+#define REG_FE2IMR_8197F 0x1120
+#define REG_FE2ISR_8197F 0x1124
+#define REG_FE3IMR_8197F 0x1128
+#define REG_FE3ISR_8197F 0x112C
+#define REG_FE4IMR_8197F 0x1130
+#define REG_FE4ISR_8197F 0x1134
+#define REG_FT1IMR_8197F 0x1138
+#define REG_FT1ISR_8197F 0x113C
+#define REG_SPWR0_8197F 0x1140
+#define REG_SPWR1_8197F 0x1144
+#define REG_SPWR2_8197F 0x1148
+#define REG_SPWR3_8197F 0x114C
+#define REG_POWSEQ_8197F 0x1150
+#define REG_TC7_CTRL_V1_8197F 0x1158
+#define REG_TC8_CTRL_V1_8197F 0x115C
+#define REG_RXBCN_TBTT_INTERVAL_PORT0TO3_8197F 0x1160
+#define REG_RXBCN_TBTT_INTERVAL_PORT4_8197F 0x1164
+#define REG_EXT_QUEUE_REG_8197F 0x11C0
+#define REG_COUNTER_CONTROL_8197F 0x11C4
+#define REG_COUNTER_TH_8197F 0x11C8
+#define REG_COUNTER_SET_8197F 0x11CC
+#define REG_COUNTER_OVERFLOW_8197F 0x11D0
+#define REG_TDE_LEN_TH_8197F 0x11D4
+#define REG_RDE_LEN_TH_8197F 0x11D8
+#define REG_PCIE_EXEC_TIME_8197F 0x11DC
+#define REG_FT2IMR_8197F 0x11E0
+#define REG_FT2ISR_8197F 0x11E4
+#define REG_MSG2_8197F 0x11F0
+#define REG_MSG3_8197F 0x11F4
+#define REG_MSG4_8197F 0x11F8
+#define REG_MSG5_8197F 0x11FC
+#define REG_FIFOPAGE_CTRL_1_8197F 0x0200
+#define REG_FIFOPAGE_CTRL_2_8197F 0x0204
+#define REG_AUTO_LLT_V1_8197F 0x0208
+#define REG_TXDMA_OFFSET_CHK_8197F 0x020C
+#define REG_TXDMA_STATUS_8197F 0x0210
+#define REG_TX_DMA_DBG_8197F 0x0214
+#define REG_TQPNT1_8197F 0x0218
+#define REG_TQPNT2_8197F 0x021C
+#define REG_TQPNT3_8197F 0x0220
+#define REG_TQPNT4_8197F 0x0224
+#define REG_RQPN_CTRL_1_8197F 0x0228
+#define REG_RQPN_CTRL_2_8197F 0x022C
+#define REG_FIFOPAGE_INFO_1_8197F 0x0230
+#define REG_FIFOPAGE_INFO_2_8197F 0x0234
+#define REG_FIFOPAGE_INFO_3_8197F 0x0238
+#define REG_FIFOPAGE_INFO_4_8197F 0x023C
+#define REG_FIFOPAGE_INFO_5_8197F 0x0240
+#define REG_H2C_HEAD_8197F 0x0244
+#define REG_H2C_TAIL_8197F 0x0248
+#define REG_H2C_READ_ADDR_8197F 0x024C
+#define REG_H2C_WR_ADDR_8197F 0x0250
+#define REG_H2C_INFO_8197F 0x0254
+#define REG_RXDMA_AGG_PG_TH_8197F 0x0280
+#define REG_RXPKT_NUM_8197F 0x0284
+#define REG_RXDMA_STATUS_8197F 0x0288
+#define REG_RXDMA_DPR_8197F 0x028C
+#define REG_RXDMA_MODE_8197F 0x0290
+#define REG_C2H_PKT_8197F 0x0294
+#define REG_FWFF_C2H_8197F 0x0298
+#define REG_FWFF_CTRL_8197F 0x029C
+#define REG_FWFF_PKT_INFO_8197F 0x02A0
+#define REG_FC2H_INFO_8197F 0x02A4
+#define REG_DDMA_CH0SA_8197F 0x1200
+#define REG_DDMA_CH0DA_8197F 0x1204
+#define REG_DDMA_CH0CTRL_8197F 0x1208
+#define REG_DDMA_CH1SA_8197F 0x1210
+#define REG_DDMA_CH1DA_8197F 0x1214
+#define REG_DDMA_CH1CTRL_8197F 0x1218
+#define REG_DDMA_CH2SA_8197F 0x1220
+#define REG_DDMA_CH2DA_8197F 0x1224
+#define REG_DDMA_CH2CTRL_8197F 0x1228
+#define REG_DDMA_CH3SA_8197F 0x1230
+#define REG_DDMA_CH3DA_8197F 0x1234
+#define REG_DDMA_CH3CTRL_8197F 0x1238
+#define REG_DDMA_CH4SA_8197F 0x1240
+#define REG_DDMA_CH4DA_8197F 0x1244
+#define REG_DDMA_CH4CTRL_8197F 0x1248
+#define REG_DDMA_CH5SA_8197F 0x1250
+#define REG_DDMA_CH5DA_8197F 0x1254
+#define REG_REG_DDMA_CH5CTRL_8197F 0x1258
+#define REG_DDMA_INT_MSK_8197F 0x12E0
+#define REG_DDMA_CHSTATUS_8197F 0x12E8
+#define REG_DDMA_CHKSUM_8197F 0x12F0
+#define REG_DDMA_MONITOR_8197F 0x12FC
+#define REG_HCI_CTRL_8197F 0x0300
+#define REG_INT_MIG_8197F 0x0304
+#define REG_BCNQ_TXBD_DESA_8197F 0x0308
+#define REG_MGQ_TXBD_DESA_8197F 0x0310
+#define REG_VOQ_TXBD_DESA_8197F 0x0318
+#define REG_VIQ_TXBD_DESA_8197F 0x0320
+#define REG_BEQ_TXBD_DESA_8197F 0x0328
+#define REG_BKQ_TXBD_DESA_8197F 0x0330
+#define REG_RXQ_RXBD_DESA_8197F 0x0338
+#define REG_HI0Q_TXBD_DESA_8197F 0x0340
+#define REG_HI1Q_TXBD_DESA_8197F 0x0348
+#define REG_HI2Q_TXBD_DESA_8197F 0x0350
+#define REG_HI3Q_TXBD_DESA_8197F 0x0358
+#define REG_HI4Q_TXBD_DESA_8197F 0x0360
+#define REG_HI5Q_TXBD_DESA_8197F 0x0368
+#define REG_HI6Q_TXBD_DESA_8197F 0x0370
+#define REG_HI7Q_TXBD_DESA_8197F 0x0378
+#define REG_MGQ_TXBD_NUM_8197F 0x0380
+#define REG_RX_RXBD_NUM_8197F 0x0382
+#define REG_VOQ_TXBD_NUM_8197F 0x0384
+#define REG_VIQ_TXBD_NUM_8197F 0x0386
+#define REG_BEQ_TXBD_NUM_8197F 0x0388
+#define REG_BKQ_TXBD_NUM_8197F 0x038A
+#define REG_HI0Q_TXBD_NUM_8197F 0x038C
+#define REG_HI1Q_TXBD_NUM_8197F 0x038E
+#define REG_HI2Q_TXBD_NUM_8197F 0x0390
+#define REG_HI3Q_TXBD_NUM_8197F 0x0392
+#define REG_HI4Q_TXBD_NUM_8197F 0x0394
+#define REG_HI5Q_TXBD_NUM_8197F 0x0396
+#define REG_HI6Q_TXBD_NUM_8197F 0x0398
+#define REG_HI7Q_TXBD_NUM_8197F 0x039A
+#define REG_TSFTIMER_HCI_8197F 0x039C
+#define REG_BD_RWPTR_CLR_8197F 0x039C
+#define REG_VOQ_TXBD_IDX_8197F 0x03A0
+#define REG_VIQ_TXBD_IDX_8197F 0x03A4
+#define REG_BEQ_TXBD_IDX_8197F 0x03A8
+#define REG_BKQ_TXBD_IDX_8197F 0x03AC
+#define REG_MGQ_TXBD_IDX_8197F 0x03B0
+#define REG_RXQ_RXBD_IDX_8197F 0x03B4
+#define REG_HI0Q_TXBD_IDX_8197F 0x03B8
+#define REG_HI1Q_TXBD_IDX_8197F 0x03BC
+#define REG_HI2Q_TXBD_IDX_8197F 0x03C0
+#define REG_HI3Q_TXBD_IDX_8197F 0x03C4
+#define REG_HI4Q_TXBD_IDX_8197F 0x03C8
+#define REG_HI5Q_TXBD_IDX_8197F 0x03CC
+#define REG_HI6Q_TXBD_IDX_8197F 0x03D0
+#define REG_HI7Q_TXBD_IDX_8197F 0x03D4
+#define REG_DBG_SEL_V1_8197F 0x03D8
+#define REG_HCI_HRPWM1_V1_8197F 0x03D9
+#define REG_HCI_HCPWM1_V1_8197F 0x03DA
+#define REG_HCI_CTRL2_8197F 0x03DB
+#define REG_HCI_HRPWM2_V1_8197F 0x03DC
+#define REG_HCI_HCPWM2_V1_8197F 0x03DE
+#define REG_HCI_H2C_MSG_V1_8197F 0x03E0
+#define REG_HCI_C2H_MSG_V1_8197F 0x03E4
+#define REG_DBI_WDATA_V1_8197F 0x03E8
+#define REG_DBI_RDATA_V1_8197F 0x03EC
+#define REG_STUCK_FLAG_V1_8197F 0x03F0
+#define REG_MDIO_V1_8197F 0x03F4
+#define REG_WDT_CFG_8197F 0x03F8
+#define REG_HCI_MIX_CFG_8197F 0x03FC
+#define REG_STC_INT_CS_8197F 0x1300
+#define REG_ST_INT_CFG_8197F 0x1304
+#define REG_CMU_DLY_CTRL_8197F 0x1310
+#define REG_CMU_DLY_CFG_8197F 0x1314
+#define REG_H2CQ_TXBD_DESA_8197F 0x1320
+#define REG_H2CQ_TXBD_NUM_8197F 0x1328
+#define REG_H2CQ_TXBD_IDX_8197F 0x132C
+#define REG_H2CQ_CSR_8197F 0x1330
+#define REG_AXI_EXCEPT_CS_8197F 0x1350
+#define REG_AXI_EXCEPT_TIME_8197F 0x1354
+#define REG_Q0_INFO_8197F 0x0400
+#define REG_Q1_INFO_8197F 0x0404
+#define REG_Q2_INFO_8197F 0x0408
+#define REG_Q3_INFO_8197F 0x040C
+#define REG_MGQ_INFO_8197F 0x0410
+#define REG_HIQ_INFO_8197F 0x0414
+#define REG_BCNQ_INFO_8197F 0x0418
+#define REG_TXPKT_EMPTY_8197F 0x041A
+#define REG_CPU_MGQ_INFO_8197F 0x041C
+#define REG_FWHW_TXQ_CTRL_8197F 0x0420
+#define REG_BCNQ_BDNY_V1_8197F 0x0424
+#define REG_LIFETIME_EN_8197F 0x0426
+#define REG_SPEC_SIFS_8197F 0x0428
+#define REG_RETRY_LIMIT_8197F 0x042A
+#define REG_TXBF_CTRL_8197F 0x042C
+#define REG_DARFRC_8197F 0x0430
+#define REG_RARFRC_8197F 0x0438
+#define REG_RRSR_8197F 0x0440
+#define REG_ARFR0_8197F 0x0444
+#define REG_ARFR1_V1_8197F 0x044C
+#define REG_CCK_CHECK_8197F 0x0454
+#define REG_AMPDU_MAX_TIME_V1_8197F 0x0455
+#define REG_BCNQ1_BDNY_V1_8197F 0x0456
+#define REG_AMPDU_MAX_LENGTH_8197F 0x0458
+#define REG_ACQ_STOP_8197F 0x045C
+#define REG_NDPA_RATE_8197F 0x045D
+#define REG_TX_HANG_CTRL_8197F 0x045E
+#define REG_NDPA_OPT_CTRL_8197F 0x045F
+#define REG_RD_RESP_PKT_TH_8197F 0x0463
+#define REG_CMDQ_INFO_8197F 0x0464
+#define REG_Q4_INFO_8197F 0x0468
+#define REG_Q5_INFO_8197F 0x046C
+#define REG_Q6_INFO_8197F 0x0470
+#define REG_Q7_INFO_8197F 0x0474
+#define REG_WMAC_LBK_BUF_HD_V1_8197F 0x0478
+#define REG_MGQ_BDNY_V1_8197F 0x047A
+#define REG_TXRPT_CTRL_8197F 0x047C
+#define REG_INIRTS_RATE_SEL_8197F 0x0480
+#define REG_BASIC_CFEND_RATE_8197F 0x0481
+#define REG_STBC_CFEND_RATE_8197F 0x0482
+#define REG_DATA_SC_8197F 0x0483
+#define REG_MACID_SLEEP3_8197F 0x0484
+#define REG_MACID_SLEEP1_8197F 0x0488
+#define REG_ARFR2_V1_8197F 0x048C
+#define REG_ARFR3_V1_8197F 0x0494
+#define REG_ARFR4_8197F 0x049C
+#define REG_ARFR5_8197F 0x04A4
+#define REG_TXRPT_START_OFFSET_8197F 0x04AC
+#define REG_POWER_STAGE1_8197F 0x04B4
+#define REG_POWER_STAGE2_8197F 0x04B8
+#define REG_SW_AMPDU_BURST_MODE_CTRL_8197F 0x04BC
+#define REG_PKT_LIFE_TIME_8197F 0x04C0
+#define REG_STBC_SETTING_8197F 0x04C4
+#define REG_STBC_SETTING2_8197F 0x04C5
+#define REG_QUEUE_CTRL_8197F 0x04C6
+#define REG_SINGLE_AMPDU_CTRL_8197F 0x04C7
+#define REG_PROT_MODE_CTRL_8197F 0x04C8
+#define REG_BAR_MODE_CTRL_8197F 0x04CC
+#define REG_RA_TRY_RATE_AGG_LMT_8197F 0x04CF
+#define REG_MACID_SLEEP2_8197F 0x04D0
+#define REG_MACID_SLEEP_8197F 0x04D4
+#define REG_HW_SEQ0_8197F 0x04D8
+#define REG_HW_SEQ1_8197F 0x04DA
+#define REG_HW_SEQ2_8197F 0x04DC
+#define REG_HW_SEQ3_8197F 0x04DE
+#define REG_NULL_PKT_STATUS_V1_8197F 0x04E0
+#define REG_PTCL_ERR_STATUS_8197F 0x04E2
+#define REG_NULL_PKT_STATUS_EXTEND_8197F 0x04E3
+#define REG_VIDEO_ENHANCEMENT_FUN_8197F 0x04E4
+#define REG_BT_POLLUTE_PKT_CNT_8197F 0x04E8
+#define REG_PTCL_DBG_8197F 0x04EC
+#define REG_TXOP_EXTRA_CTRL_8197F 0x04F0
+#define REG_CPUMGQ_TIMER_CTRL2_8197F 0x04F4
+#define REG_DUMMY_PAGE4_8197F 0x04FC
+#define REG_Q0_Q1_INFO_8197F 0x1400
+#define REG_Q2_Q3_INFO_8197F 0x1404
+#define REG_Q4_Q5_INFO_8197F 0x1408
+#define REG_Q6_Q7_INFO_8197F 0x140C
+#define REG_MGQ_HIQ_INFO_8197F 0x1410
+#define REG_CMDQ_BCNQ_INFO_8197F 0x1414
+#define REG_USEREG_SETTING_8197F 0x1420
+#define REG_AESIV_SETTING_8197F 0x1424
+#define REG_BF0_TIME_SETTING_8197F 0x1428
+#define REG_BF1_TIME_SETTING_8197F 0x142C
+#define REG_BF_TIMEOUT_EN_8197F 0x1430
+#define REG_MACID_RELEASE0_8197F 0x1434
+#define REG_MACID_RELEASE1_8197F 0x1438
+#define REG_MACID_RELEASE2_8197F 0x143C
+#define REG_MACID_RELEASE3_8197F 0x1440
+#define REG_MACID_RELEASE_SETTING_8197F 0x1444
+#define REG_FAST_EDCA_VOVI_SETTING_8197F 0x1448
+#define REG_FAST_EDCA_BEBK_SETTING_8197F 0x144C
+#define REG_MACID_DROP0_8197F 0x1450
+#define REG_MACID_DROP1_8197F 0x1454
+#define REG_MACID_DROP2_8197F 0x1458
+#define REG_MACID_DROP3_8197F 0x145C
+#define REG_R_MACID_RELEASE_SUCCESS_0_8197F 0x1460
+#define REG_R_MACID_RELEASE_SUCCESS_1_8197F 0x1464
+#define REG_R_MACID_RELEASE_SUCCESS_2_8197F 0x1468
+#define REG_R_MACID_RELEASE_SUCCESS_3_8197F 0x146C
+#define REG_MGG_FIFO_CRTL_8197F 0x1470
+#define REG_MGG_FIFO_INT_8197F 0x1474
+#define REG_MGG_FIFO_LIFETIME_8197F 0x1478
+#define REG_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8197F 0x147C
+#define REG_SHCUT_SETTING_8197F 0x1480
+#define REG_SHCUT_LLC_ETH_TYPE0_8197F 0x1484
+#define REG_SHCUT_LLC_ETH_TYPE1_8197F 0x1488
+#define REG_SHCUT_LLC_OUI0_8197F 0x148C
+#define REG_SHCUT_LLC_OUI1_8197F 0x1490
+#define REG_SHCUT_LLC_OUI2_8197F 0x1494
+#define REG_SHCUT_LLC_OUI3_8197F 0x1498
+#define REG_CHNL_INFO_CTRL_8197F 0x14D0
+#define REG_CHNL_IDLE_TIME_8197F 0x14D4
+#define REG_CHNL_BUSY_TIME_8197F 0x14D8
+#define REG_EDCA_VO_PARAM_8197F 0x0500
+#define REG_EDCA_VI_PARAM_8197F 0x0504
+#define REG_EDCA_BE_PARAM_8197F 0x0508
+#define REG_EDCA_BK_PARAM_8197F 0x050C
+#define REG_BCNTCFG_8197F 0x0510
+#define REG_PIFS_8197F 0x0512
+#define REG_RDG_PIFS_8197F 0x0513
+#define REG_SIFS_8197F 0x0514
+#define REG_TSFTR_SYN_OFFSET_8197F 0x0518
+#define REG_AGGR_BREAK_TIME_8197F 0x051A
+#define REG_SLOT_8197F 0x051B
+#define REG_TX_PTCL_CTRL_8197F 0x0520
+#define REG_TXPAUSE_8197F 0x0522
+#define REG_DIS_TXREQ_CLR_8197F 0x0523
+#define REG_RD_CTRL_8197F 0x0524
+#define REG_MBSSID_CTRL_8197F 0x0526
+#define REG_P2PPS_CTRL_8197F 0x0527
+#define REG_PKT_LIFETIME_CTRL_8197F 0x0528
+#define REG_P2PPS_SPEC_STATE_8197F 0x052B
+#define REG_QUEUE_INCOL_THR_8197F 0x0538
+#define REG_QUEUE_INCOL_EN_8197F 0x053C
+#define REG_TBTT_PROHIBIT_8197F 0x0540
+#define REG_P2PPS_STATE_8197F 0x0543
+#define REG_RD_NAV_NXT_8197F 0x0544
+#define REG_NAV_PROT_LEN_8197F 0x0546
+#define REG_FTM_CTRL_8197F 0x0548
+#define REG_FTM_TSF_CNT_8197F 0x054C
+#define REG_BCN_CTRL_8197F 0x0550
+#define REG_BCN_CTRL_CLINT0_8197F 0x0551
+#define REG_MBID_NUM_8197F 0x0552
+#define REG_DUAL_TSF_RST_8197F 0x0553
+#define REG_MBSSID_BCN_SPACE_8197F 0x0554
+#define REG_DRVERLYINT_8197F 0x0558
+#define REG_BCNDMATIM_8197F 0x0559
+#define REG_ATIMWND_8197F 0x055A
+#define REG_USTIME_TSF_8197F 0x055C
+#define REG_BCN_MAX_ERR_8197F 0x055D
+#define REG_RXTSF_OFFSET_CCK_8197F 0x055E
+#define REG_RXTSF_OFFSET_OFDM_8197F 0x055F
+#define REG_TSFTR_8197F 0x0560
+#define REG_FREERUN_CNT_8197F 0x0568
+#define REG_ATIMWND1_8197F 0x0570
+#define REG_TBTT_PROHIBIT_INFRA_8197F 0x0571
+#define REG_CTWND_8197F 0x0572
+#define REG_BCNIVLCUNT_8197F 0x0573
+#define REG_BCNDROPCTRL_8197F 0x0574
+#define REG_HGQ_TIMEOUT_PERIOD_8197F 0x0575
+#define REG_TXCMD_TIMEOUT_PERIOD_8197F 0x0576
+#define REG_MISC_CTRL_8197F 0x0577
+#define REG_BCN_CTRL_CLINT1_8197F 0x0578
+#define REG_BCN_CTRL_CLINT2_8197F 0x0579
+#define REG_BCN_CTRL_CLINT3_8197F 0x057A
+#define REG_EXTEND_CTRL_8197F 0x057B
+#define REG_P2PPS1_SPEC_STATE_8197F 0x057C
+#define REG_P2PPS1_STATE_8197F 0x057D
+#define REG_P2PPS2_SPEC_STATE_8197F 0x057E
+#define REG_P2PPS2_STATE_8197F 0x057F
+#define REG_PS_TIMER0_8197F 0x0580
+#define REG_PS_TIMER1_8197F 0x0584
+#define REG_PS_TIMER2_8197F 0x0588
+#define REG_TBTT_CTN_AREA_8197F 0x058C
+#define REG_FORCE_BCN_IFS_8197F 0x058E
+#define REG_TXOP_MIN_8197F 0x0590
+#define REG_PRE_BKF_TIME_8197F 0x0592
+#define REG_CROSS_TXOP_CTRL_8197F 0x0593
+#define REG_TBTT_INT_SHIFT_CLI0_8197F 0x0594
+#define REG_TBTT_INT_SHIFT_CLI1_8197F 0x0595
+#define REG_TBTT_INT_SHIFT_CLI2_8197F 0x0596
+#define REG_TBTT_INT_SHIFT_CLI3_8197F 0x0597
+#define REG_TBTT_INT_SHIFT_ENABLE_8197F 0x0598
+#define REG_ATIMWND2_8197F 0x05A0
+#define REG_ATIMWND3_8197F 0x05A1
+#define REG_ATIMWND4_8197F 0x05A2
+#define REG_ATIMWND5_8197F 0x05A3
+#define REG_ATIMWND6_8197F 0x05A4
+#define REG_ATIMWND7_8197F 0x05A5
+#define REG_ATIMUGT_8197F 0x05A6
+#define REG_HIQ_NO_LMT_EN_8197F 0x05A7
+#define REG_DTIM_COUNTER_ROOT_8197F 0x05A8
+#define REG_DTIM_COUNTER_VAP1_8197F 0x05A9
+#define REG_DTIM_COUNTER_VAP2_8197F 0x05AA
+#define REG_DTIM_COUNTER_VAP3_8197F 0x05AB
+#define REG_DTIM_COUNTER_VAP4_8197F 0x05AC
+#define REG_DTIM_COUNTER_VAP5_8197F 0x05AD
+#define REG_DTIM_COUNTER_VAP6_8197F 0x05AE
+#define REG_DTIM_COUNTER_VAP7_8197F 0x05AF
+#define REG_DIS_ATIM_8197F 0x05B0
+#define REG_EARLY_128US_8197F 0x05B1
+#define REG_P2PPS1_CTRL_8197F 0x05B2
+#define REG_P2PPS2_CTRL_8197F 0x05B3
+#define REG_TIMER0_SRC_SEL_8197F 0x05B4
+#define REG_NOA_UNIT_SEL_8197F 0x05B5
+#define REG_P2POFF_DIS_TXTIME_8197F 0x05B7
+#define REG_MBSSID_BCN_SPACE2_8197F 0x05B8
+#define REG_MBSSID_BCN_SPACE3_8197F 0x05BC
+#define REG_ACMHWCTRL_8197F 0x05C0
+#define REG_ACMRSTCTRL_8197F 0x05C1
+#define REG_ACMAVG_8197F 0x05C2
+#define REG_VO_ADMTIME_8197F 0x05C4
+#define REG_VI_ADMTIME_8197F 0x05C6
+#define REG_BE_ADMTIME_8197F 0x05C8
+#define REG_EDCA_RANDOM_GEN_8197F 0x05CC
+#define REG_TXCMD_NOA_SEL_8197F 0x05CF
+#define REG_NOA_PARAM_8197F 0x05E0
+#define REG_P2P_RST_8197F 0x05F0
+#define REG_SCHEDULER_RST_8197F 0x05F1
+#define REG_SCH_TXCMD_8197F 0x05F8
+#define REG_PAGE5_DUMMY_8197F 0x05FC
+#define REG_CPUMGQ_TX_TIMER_8197F 0x1500
+#define REG_PS_TIMER_A_8197F 0x1504
+#define REG_PS_TIMER_B_8197F 0x1508
+#define REG_PS_TIMER_C_8197F 0x150C
+#define REG_PS_TIMER_ABC_CPUMGQ_TIMER_CRTL_8197F 0x1510
+#define REG_CPUMGQ_TX_TIMER_EARLY_8197F 0x1514
+#define REG_PS_TIMER_A_EARLY_8197F 0x1515
+#define REG_PS_TIMER_B_EARLY_8197F 0x1516
+#define REG_PS_TIMER_C_EARLY_8197F 0x1517
+#define REG_WMAC_CR_8197F 0x0600
+#define REG_WMAC_FWPKT_CR_8197F 0x0601
+#define REG_BWOPMODE_8197F 0x0603
+#define REG_TCR_8197F 0x0604
+#define REG_RCR_8197F 0x0608
+#define REG_RX_PKT_LIMIT_8197F 0x060C
+#define REG_RX_DLK_TIME_8197F 0x060D
+#define REG_RX_DRVINFO_SZ_8197F 0x060F
+#define REG_MACID_8197F 0x0610
+#define REG_BSSID_8197F 0x0618
+#define REG_MAR_8197F 0x0620
+#define REG_MBIDCAMCFG_1_8197F 0x0628
+#define REG_MBIDCAMCFG_2_8197F 0x062C
+#define REG_WMAC_TCR_TSFT_OFS_8197F 0x0630
+#define REG_UDF_THSD_8197F 0x0632
+#define REG_ZLD_NUM_8197F 0x0633
+#define REG_STMP_THSD_8197F 0x0634
+#define REG_WMAC_TXTIMEOUT_8197F 0x0635
+#define REG_MCU_TEST_2_V1_8197F 0x0636
+#define REG_USTIME_EDCA_8197F 0x0638
+#define REG_MAC_SPEC_SIFS_8197F 0x063A
+#define REG_RESP_SIFS_CCK_8197F 0x063C
+#define REG_RESP_SIFS_OFDM_8197F 0x063E
+#define REG_ACKTO_8197F 0x0640
+#define REG_CTS2TO_8197F 0x0641
+#define REG_EIFS_8197F 0x0642
+#define REG_NAV_CTRL_8197F 0x0650
+#define REG_BACAMCMD_8197F 0x0654
+#define REG_BACAMCONTENT_8197F 0x0658
+#define REG_LBDLY_8197F 0x0660
+#define REG_WMAC_BACAM_RPMEN_8197F 0x0661
+#define REG_WMAC_BITMAP_CTL_8197F 0x0663
+#define REG_RXERR_RPT_8197F 0x0664
+#define REG_WMAC_TRXPTCL_CTL_8197F 0x0668
+#define REG_CAMCMD_8197F 0x0670
+#define REG_CAMWRITE_8197F 0x0674
+#define REG_CAMREAD_8197F 0x0678
+#define REG_CAMDBG_8197F 0x067C
+#define REG_SECCFG_8197F 0x0680
+#define REG_RXFILTER_CATEGORY_1_8197F 0x0682
+#define REG_RXFILTER_ACTION_1_8197F 0x0683
+#define REG_RXFILTER_CATEGORY_2_8197F 0x0684
+#define REG_RXFILTER_ACTION_2_8197F 0x0685
+#define REG_RXFILTER_CATEGORY_3_8197F 0x0686
+#define REG_RXFILTER_ACTION_3_8197F 0x0687
+#define REG_RXFLTMAP3_8197F 0x0688
+#define REG_RXFLTMAP4_8197F 0x068A
+#define REG_RXFLTMAP5_8197F 0x068C
+#define REG_RXFLTMAP6_8197F 0x068E
+#define REG_WOW_CTRL_8197F 0x0690
+#define REG_PS_RX_INFO_8197F 0x0692
+#define REG_WMMPS_UAPSD_TID_8197F 0x0693
+#define REG_LPNAV_CTRL_8197F 0x0694
+#define REG_WKFMCAM_CMD_8197F 0x0698
+#define REG_WKFMCAM_RWD_8197F 0x069C
+#define REG_RXFLTMAP0_8197F 0x06A0
+#define REG_RXFLTMAP1_8197F 0x06A2
+#define REG_RXFLTMAP_8197F 0x06A4
+#define REG_BCN_PSR_RPT_8197F 0x06A8
+#define REG_RXPKTMON_CTRL_8197F 0x06B0
+#define REG_STATE_MON_8197F 0x06B4
+#define REG_ERROR_MON_8197F 0x06B8
+#define REG_SEARCH_MACID_8197F 0x06BC
+#define REG_BT_COEX_TABLE_8197F 0x06C0
+#define REG_RXCMD_0_8197F 0x06D0
+#define REG_RXCMD_1_8197F 0x06D4
+#define REG_WMAC_RESP_TXINFO_8197F 0x06D8
+#define REG_BBPSF_CTRL_8197F 0x06DC
+#define REG_P2P_RX_BCN_NOA_8197F 0x06E0
+#define REG_ASSOCIATED_BFMER0_INFO_8197F 0x06E4
+#define REG_ASSOCIATED_BFMER1_INFO_8197F 0x06EC
+#define REG_TX_CSI_RPT_PARAM_BW20_8197F 0x06F4
+#define REG_TX_CSI_RPT_PARAM_BW40_8197F 0x06F8
+#define REG_TX_CSI_RPT_PARAM_BW80_8197F 0x06FC
+#define REG_BCN_PSR_RPT2_8197F 0x1600
+#define REG_BCN_PSR_RPT3_8197F 0x1604
+#define REG_BCN_PSR_RPT4_8197F 0x1608
+#define REG_A1_ADDR_MASK_8197F 0x160C
+#define REG_MACID2_8197F 0x1620
+#define REG_BSSID2_8197F 0x1628
+#define REG_MACID3_8197F 0x1630
+#define REG_BSSID3_8197F 0x1638
+#define REG_MACID4_8197F 0x1640
+#define REG_BSSID4_8197F 0x1648
+#define REG_NOA_REPORT_8197F 0x1650
+#define REG_PWRBIT_SETTING_8197F 0x1660
+#define REG_WMAC_MU_BF_OPTION_8197F 0x167C
+#define REG_WMAC_PAUSE_BB_CLR_TH_8197F 0x167D
+#define REG_WMAC_MU_ARB_8197F 0x167E
+#define REG_WMAC_MU_OPTION_8197F 0x167F
+#define REG_WMAC_MU_BF_CTL_8197F 0x1680
+#define REG_WMAC_MU_BFRPT_PARA_8197F 0x1682
+#define REG_WMAC_ASSOCIATED_MU_BFMEE2_8197F 0x1684
+#define REG_WMAC_ASSOCIATED_MU_BFMEE3_8197F 0x1686
+#define REG_WMAC_ASSOCIATED_MU_BFMEE4_8197F 0x1688
+#define REG_WMAC_ASSOCIATED_MU_BFMEE5_8197F 0x168A
+#define REG_WMAC_ASSOCIATED_MU_BFMEE6_8197F 0x168C
+#define REG_WMAC_ASSOCIATED_MU_BFMEE7_8197F 0x168E
+#define REG_TRANSMIT_ADDRSS_0_8197F 0x16A0
+#define REG_TRANSMIT_ADDRSS_1_8197F 0x16A8
+#define REG_TRANSMIT_ADDRSS_2_8197F 0x16B0
+#define REG_TRANSMIT_ADDRSS_3_8197F 0x16B8
+#define REG_TRANSMIT_ADDRSS_4_8197F 0x16C0
+#define REG_MACID1_8197F 0x0700
+#define REG_BSSID1_8197F 0x0708
+#define REG_BCN_PSR_RPT1_8197F 0x0710
+#define REG_ASSOCIATED_BFMEE_SEL_8197F 0x0714
+#define REG_SND_PTCL_CTRL_8197F 0x0718
+#define REG_RX_CSI_RPT_INFO_8197F 0x071C
+#define REG_NS_ARP_CTRL_8197F 0x0720
+#define REG_NS_ARP_INFO_8197F 0x0724
+#define REG_BEAMFORMING_INFO_NSARP_V1_8197F 0x0728
+#define REG_BEAMFORMING_INFO_NSARP_8197F 0x072C
+#define REG_WMAC_RTX_CTX_SUBTYPE_CFG_8197F 0x0750
+#define REG_WMAC_SWAES_CFG_8197F 0x0760
+#define REG_BT_COEX_V2_8197F 0x0762
+#define REG_BT_COEX_8197F 0x0764
+#define REG_WLAN_ACT_MASK_CTRL_8197F 0x0768
+#define REG_BT_COEX_ENHANCED_INTR_CTRL_8197F 0x076E
+#define REG_BT_ACT_STATISTICS_8197F 0x0770
+#define REG_BT_STATISTICS_CONTROL_REGISTER_8197F 0x0778
+#define REG_BT_STATUS_REPORT_REGISTER_8197F 0x077C
+#define REG_BT_INTERRUPT_CONTROL_REGISTER_8197F 0x0780
+#define REG_WLAN_REPORT_TIME_OUT_CONTROL_REGISTER_8197F 0x0784
+#define REG_BT_ISOLATION_TABLE_REGISTER_REGISTER_8197F 0x0785
+#define REG_BT_INTERRUPT_STATUS_REGISTER_8197F 0x078F
+#define REG_BT_TDMA_TIME_REGISTER_8197F 0x0790
+#define REG_BT_ACT_REGISTER_8197F 0x0794
+#define REG_OBFF_CTRL_BASIC_8197F 0x0798
+#define REG_OBFF_CTRL2_TIMER_8197F 0x079C
+#define REG_LTR_CTRL_BASIC_8197F 0x07A0
+#define REG_LTR_CTRL2_TIMER_THRESHOLD_8197F 0x07A4
+#define REG_LTR_IDLE_LATENCY_V1_8197F 0x07A8
+#define REG_LTR_ACTIVE_LATENCY_V1_8197F 0x07AC
+#define REG_ANTENNA_TRAINING_CONTROL_REGISTER_8197F 0x07B0
+#define REG_WMAC_PKTCNT_RWD_8197F 0x07B8
+#define REG_WMAC_PKTCNT_CTRL_8197F 0x07BC
+#define REG_IQ_DUMP_8197F 0x07C0
+#define REG_WMAC_FTM_CTL_8197F 0x07CC
+#define REG_IQ_DUMP_EXT_8197F 0x07CF
+#define REG_OFDM_CCK_LEN_MASK_8197F 0x07D0
+#define REG_RX_FILTER_FUNCTION_8197F 0x07DA
+#define REG_NDP_SIG_8197F 0x07E0
+#define REG_TXCMD_INFO_FOR_RSP_PKT_8197F 0x07E4
+#define REG_SEC_OPT_V2_8197F 0x07EC
+#define REG_RTS_ADDRESS_0_8197F 0x07F0
+#define REG_RTS_ADDRESS_1_8197F 0x07F8
+
+#endif
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/halmac/halmac_reg_8814b.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/halmac/halmac_reg_8814b.h
--- linux-5.6.3/3rdparty/rtl8821ce/hal/halmac/halmac_reg_8814b.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/halmac/halmac_reg_8814b.h	2020-04-10 16:35:06.816660067 +0300
@@ -0,0 +1,1058 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ ******************************************************************************/
+
+#ifndef __INC_HALMAC_REG_8814B_H
+#define __INC_HALMAC_REG_8814B_H
+
+#define REG_SYS_ISO_CTRL_8814B 0x0000
+#define REG_SYS_FUNC_EN_8814B 0x0002
+#define REG_SYS_PW_CTRL_8814B 0x0004
+#define REG_SYS_CLK_CTRL_8814B 0x0008
+#define REG_SYS_EEPROM_CTRL_8814B 0x000A
+#define REG_EE_VPD_8814B 0x000C
+#define REG_SYS_SWR_CTRL1_8814B 0x0010
+#define REG_SYS_SWR_CTRL2_8814B 0x0014
+#define REG_SYS_SWR_CTRL3_8814B 0x0018
+#define REG_RSV_CTRL_8814B 0x001C
+#define REG_RF_CTRL_8814B 0x001F
+#define REG_AFE_LDO_CTRL_8814B 0x0020
+#define REG_AFE_CTRL1_8814B 0x0024
+#define REG_ANAPARSW_POW_MAC_8814B 0x0028
+#define REG_ANAPARLDO_POW_MAC_8814B 0x0029
+#define REG_ANAPAR_POW_MAC_8814B 0x002A
+#define REG_ANAPAR_POW_XTAL_8814B 0x002B
+#define REG_ANAPARLDO_MAC_8814B 0x002C
+#define REG_EFUSE_CTRL_8814B 0x0030
+#define REG_LDO_EFUSE_CTRL_8814B 0x0034
+#define REG_PWR_OPTION_CTRL_8814B 0x0038
+#define REG_CAL_TIMER_8814B 0x003C
+#define REG_ACLK_MON_8814B 0x003E
+#define REG_GPIO_MUXCFG_8814B 0x0040
+#define REG_GPIO_PIN_CTRL_8814B 0x0044
+#define REG_GPIO_INTM_8814B 0x0048
+#define REG_LED_CFG_8814B 0x004C
+#define REG_FSIMR_8814B 0x0050
+#define REG_FSISR_8814B 0x0054
+#define REG_HSIMR_8814B 0x0058
+#define REG_HSISR_8814B 0x005C
+#define REG_GPIO_EXT_CTRL_8814B 0x0060
+#define REG_PAD_CTRL1_8814B 0x0064
+#define REG_WL_BT_PWR_CTRL_8814B 0x0068
+#define REG_SDM_DEBUG_8814B 0x006C
+#define REG_SYS_SDIO_CTRL_8814B 0x0070
+#define REG_HCI_OPT_CTRL_8814B 0x0074
+#define REG_AFE_CTRL4_8814B 0x0078
+#define REG_LDO_SWR_CTRL_8814B 0x007C
+#define REG_MCUFW_CTRL_8814B 0x0080
+#define REG_MCU_TST_CFG_8814B 0x0084
+#define REG_HMEBOX_E0_E1_8814B 0x0088
+#define REG_HMEBOX_E2_E3_8814B 0x008C
+#define REG_WLLPS_CTRL_8814B 0x0090
+#define REG_AFE_CTRL5_8814B 0x0094
+#define REG_GPIO_DEBOUNCE_CTRL_8814B 0x0098
+#define REG_RPWM2_8814B 0x009C
+#define REG_SYSON_FSM_MON_8814B 0x00A0
+#define REG_AFE_CTRL6_8814B 0x00A4
+#define REG_PMC_DBG_CTRL1_8814B 0x00A8
+#define REG_AFE_CTRL7_8814B 0x00AC
+#define REG_HIMR0_8814B 0x00B0
+#define REG_HISR0_8814B 0x00B4
+#define REG_HIMR1_8814B 0x00B8
+#define REG_HISR1_8814B 0x00BC
+#define REG_DBG_PORT_SEL_8814B 0x00C0
+#define REG_PAD_CTRL2_8814B 0x00C4
+#define REG_PMC_DBG_CTRL2_8814B 0x00CC
+#define REG_MEM_CTRL_8814B 0x00D8
+#define REG_SYN_RFC_CTRL_8814B 0x00DC
+#define REG_USB_SIE_INTF_8814B 0x00E0
+#define REG_PCIE_MIO_INTF_8814B 0x00E4
+#define REG_PCIE_MIO_INTD_8814B 0x00E8
+#define REG_WLRF1_8814B 0x00EC
+#define REG_SYS_CFG1_8814B 0x00F0
+#define REG_SYS_STATUS1_8814B 0x00F4
+#define REG_SYS_STATUS2_8814B 0x00F8
+#define REG_SYS_CFG2_8814B 0x00FC
+#define REG_ANAPARSW_MAC_0_8814B 0x1010
+#define REG_ANAPARSW_MAC_1_8814B 0x1014
+#define REG_ANAPAR_MAC_0_8814B 0x1018
+#define REG_ANAPAR_MAC_1_8814B 0x101C
+#define REG_ANAPAR_MAC_2_8814B 0x1020
+#define REG_ANAPAR_MAC_3_8814B 0x1024
+#define REG_ANAPAR_MAC_4_8814B 0x1028
+#define REG_ANAPAR_MAC_5_8814B 0x102C
+#define REG_ANAPAR_MAC_6_8814B 0x1030
+#define REG_ANAPAR_MAC_7_8814B 0x1034
+#define REG_ANAPAR_MAC_8_8814B 0x1038
+#define REG_ANAPAR_XTAL_0_8814B 0x1040
+#define REG_ANAPAR_XTAL_1_8814B 0x1044
+#define REG_ANAPAR_XTAL_2_8814B 0x1048
+#define REG_ANAPAR_XTAL_AAC_8814B 0x104C
+#define REG_ANAPAR_XTAL_R_ONLY_8814B 0x1050
+#define REG_CPHY_LDO_8814B 0x1054
+#define REG_CPHY_BG_8814B 0x1058
+#define REG_HIMR_4_8814B 0x1060
+#define REG_HISR_4_8814B 0x1064
+#define REG_HIMR_5_8814B 0x1068
+#define REG_HISR_5_8814B 0x106C
+#define REG_SYS_CFG5_8814B 0x1070
+#define REG_HIMR_6_8814B 0x1078
+#define REG_HISR_6_8814B 0x107C
+#define REG_CPU_DMEM_CON_8814B 0x1080
+#define REG_BOOT_REASON_8814B 0x1088
+#define REG_DATA_CPU_CTL0_8814B 0x1090
+#define REG_DATA_CPU_CTL1_8814B 0x1094
+#define REG_TXDMA_STOP_HIMR_8814B 0x1098
+#define REG_TXDMA_STOP_HISR_8814B 0x109C
+#define REG_TXDMA_START_HIMR_8814B 0x10A0
+#define REG_TXDMA_START_HISR_8814B 0x10A4
+#define REG_NFCPAD_CTRL_8814B 0x10A8
+#define REG_HIMR2_8814B 0x10B0
+#define REG_HISR2_8814B 0x10B4
+#define REG_HIMR3_8814B 0x10B8
+#define REG_HISR3_8814B 0x10BC
+#define REG_SW_MDIO_8814B 0x10C0
+#define REG_HIMR_7_8814B 0x10C8
+#define REG_HISR_7_8814B 0x10CC
+#define REG_H2C_PKT_READADDR_8814B 0x10D0
+#define REG_H2C_PKT_WRITEADDR_8814B 0x10D4
+#define REG_MEM_PWR_CRTL_8814B 0x10D8
+#define REG_FW_DRV_HANDSHAKE_8814B 0x10DC
+#define REG_FW_DBG0_8814B 0x10E0
+#define REG_FW_DBG1_8814B 0x10E4
+#define REG_FW_DBG2_8814B 0x10E8
+#define REG_FW_DBG3_8814B 0x10EC
+#define REG_FW_DBG4_8814B 0x10F0
+#define REG_FW_DBG5_8814B 0x10F4
+#define REG_FW_DBG6_8814B 0x10F8
+#define REG_FW_DBG7_8814B 0x10FC
+#define REG_CR_8814B 0x0100
+#define REG_PG_SIZE_8814B 0x0104
+#define REG_PKT_BUFF_ACCESS_CTRL_8814B 0x0106
+#define REG_TSF_CLK_STATE_8814B 0x0108
+#define REG_TXDMA_PQ_MAP_8814B 0x010C
+#define REG_TRXFF_BNDY_8814B 0x0114
+#define REG_PTA_I2C_MBOX_8814B 0x0118
+#define REG_RXFF_BNDY_8814B 0x011C
+#define REG_FE1IMR_8814B 0x0120
+#define REG_FE1ISR_8814B 0x0124
+#define REG_CPWM_8814B 0x012C
+#define REG_FWIMR_8814B 0x0130
+#define REG_FWISR_8814B 0x0134
+#define REG_FTIMR_8814B 0x0138
+#define REG_FTISR_8814B 0x013C
+#define REG_PKTBUF_DBG_CTRL_8814B 0x0140
+#define REG_PKTBUF_DBG_DATA_L_8814B 0x0144
+#define REG_PKTBUF_DBG_DATA_H_8814B 0x0148
+#define REG_CPWM2_8814B 0x014C
+#define REG_TC0_CTRL_8814B 0x0150
+#define REG_TC1_CTRL_8814B 0x0154
+#define REG_TC2_CTRL_8814B 0x0158
+#define REG_TC3_CTRL_8814B 0x015C
+#define REG_TC4_CTRL_8814B 0x0160
+#define REG_TCUNIT_BASE_8814B 0x0164
+#define REG_TC5_CTRL_8814B 0x0168
+#define REG_TC6_CTRL_8814B 0x016C
+#define REG_AES_DECRPT_DATA_8814B 0x0180
+#define REG_AES_DECRPT_CFG_8814B 0x0184
+#define REG_HIOE_CTRL_8814B 0x0188
+#define REG_HIOE_CFG_FILE_8814B 0x018C
+#define REG_TMETER_8814B 0x0190
+#define REG_OSC_32K_CTRL_8814B 0x0194
+#define REG_32K_CAL_REG1_8814B 0x0198
+#define REG_C2HEVT_8814B 0x01A0
+#define REG_C2HEVT_1_8814B 0x01A4
+#define REG_C2HEVT_2_8814B 0x01A8
+#define REG_C2HEVT_3_8814B 0x01AC
+#define REG_RXDESC_BUFF_RPTR_8814B 0x01B0
+#define REG_RXDESC_BUFF_WPTR_8814B 0x01B4
+#define REG_SW_DEFINED_PAGE1_8814B 0x01B8
+#define REG_SW_DEFINED_PAGE2_8814B 0x01BC
+#define REG_MCUTST_I_8814B 0x01C0
+#define REG_MCUTST_II_8814B 0x01C4
+#define REG_FMETHR_8814B 0x01C8
+#define REG_HMETFR_8814B 0x01CC
+#define REG_HMEBOX0_8814B 0x01D0
+#define REG_HMEBOX1_8814B 0x01D4
+#define REG_HMEBOX2_8814B 0x01D8
+#define REG_HMEBOX3_8814B 0x01DC
+#define REG_RXDESC_BUFF_BNDY_8814B 0x01E0
+#define REG_BB_ACCESS_CTRL_8814B 0x01E8
+#define REG_BB_ACCESS_DATA_8814B 0x01EC
+#define REG_HMEBOX_E0_8814B 0x01F0
+#define REG_HMEBOX_E1_8814B 0x01F4
+#define REG_HMEBOX_E2_8814B 0x01F8
+#define REG_HMEBOX_E3_8814B 0x01FC
+#define REG_CR_EXT_8814B 0x1100
+#define REG_TC9_CTRL_8814B 0x1104
+#define REG_TC10_CTRL_8814B 0x1108
+#define REG_TC11_CTRL_8814B 0x110C
+#define REG_TC12_CTRL_8814B 0x1110
+#define REG_FWFF_8814B 0x1114
+#define REG_RXFF_PTR_V1_8814B 0x1118
+#define REG_RXFF_WTR_V1_8814B 0x111C
+#define REG_FE2IMR_8814B 0x1120
+#define REG_FE2ISR_8814B 0x1124
+#define REG_FE3IMR_8814B 0x1128
+#define REG_FE3ISR_8814B 0x112C
+#define REG_FE4IMR_8814B 0x1130
+#define REG_FE4ISR_8814B 0x1134
+#define REG_FT1IMR_8814B 0x1138
+#define REG_FT1ISR_8814B 0x113C
+#define REG_SPWR0_8814B 0x1140
+#define REG_SPWR1_8814B 0x1144
+#define REG_SPWR2_8814B 0x1148
+#define REG_SPWR3_8814B 0x114C
+#define REG_POWSEQ_8814B 0x1150
+#define REG_TC7_CTRL_V1_8814B 0x1158
+#define REG_TC8_CTRL_V1_8814B 0x115C
+#define REG_RX_BCN_TBTT_ITVL0_8814B 0x1160
+#define REG_RX_BCN_TBTT_ITVL1_8814B 0x1164
+#define REG_FWIMR1_8814B 0x1168
+#define REG_FWISR1_8814B 0x116C
+#define REG_FWIMR2_8814B 0x1170
+#define REG_FWISR2_8814B 0x1174
+#define REG_FWIMR3_8814B 0x1178
+#define REG_FWISR3_8814B 0x117C
+#define REG_SPEED_SENSOR_8814B 0x1180
+#define REG_SPEED_SENSOR1_8814B 0x1184
+#define REG_SPEED_SENSOR2_8814B 0x1188
+#define REG_SPEED_SENSOR3_8814B 0x118C
+#define REG_SPEED_SENSOR4_8814B 0x1190
+#define REG_SPEED_SENSOR5_8814B 0x1194
+#define REG_RXPKTBUF_1_MAX_ADDR_8814B 0x1198
+#define REG_RXFWBUF_1_MAX_ADDR_8814B 0x119C
+#define REG_IO_WRAP_ERR_FLAG_V1_8814B 0x11A0
+#define REG_RXPKTBUF_1_READ_8814B 0x11A4
+#define REG_RXPKTBUF_1_WRITE_8814B 0x11A8
+#define REG_BUFF_DBGUG_8814B 0x11AC
+#define REG_RFE_CTRL_PAD_E2_8814B 0x11B0
+#define REG_RFE_CTRL_PAD_SR_8814B 0x11B4
+#define REG_H2C_PRIORITY_SEL_8814B 0x11C0
+#define REG_COUNTER_CTRL_8814B 0x11C4
+#define REG_COUNTER_THRESHOLD_8814B 0x11C8
+#define REG_COUNTER_SET_8814B 0x11CC
+#define REG_COUNTER_OVERFLOW_8814B 0x11D0
+#define REG_TXDMA_LEN_THRESHOLD_8814B 0x11D4
+#define REG_RXDMA_LEN_THRESHOLD_8814B 0x11D8
+#define REG_PCIE_EXEC_TIME_THRESHOLD_8814B 0x11DC
+#define REG_FT2IMR_8814B 0x11E0
+#define REG_FT2ISR_8814B 0x11E4
+#define REG_MSG2_8814B 0x11F0
+#define REG_MSG3_8814B 0x11F4
+#define REG_MSG4_8814B 0x11F8
+#define REG_MSG5_8814B 0x11FC
+#define REG_BIST_RSTN0_8814B 0x2100
+#define REG_BIST_RSTN2_8814B 0x2108
+#define REG_BIST_MODE_NRML0_8814B 0x2110
+#define REG_BIST_MODE_NRML1_8814B 0x2114
+#define REG_BIST_MODE_NRML2_8814B 0x2118
+#define REG_BIST_MODE_NRML3_8814B 0x211C
+#define REG_BIST_DONE_NRML_MAC_8814B 0x2150
+#define REG_BIST_DONE_NRML1_8814B 0x2158
+#define REG_BIST_DONE_DRF_MAC_8814B 0x2160
+#define REG_BIST_DONE_DRF_8814B 0x2164
+#define REG_BIST_DONE_DRF1_8814B 0x2168
+#define REG_BIST_FAIL_NRML_MAC_8814B 0x2170
+#define REG_BIST_FAIL_NRML_8814B 0x2174
+#define REG_BIST_FAIL_NRML1_8814B 0x2178
+#define REG_BIST_FAIL_NRML_MAC_V1_8814B 0x2180
+#define REG_BIST_FAIL_NRML_V1_8814B 0x2184
+#define REG_BIST_FAIL_NRML1_V1_8814B 0x2188
+#define REG_BIST_MISR_DATAOUT_8814B 0x2190
+#define REG_BIST_MISR_DATAOUT1_8814B 0x2194
+#define REG_BIST_MISR_DATAOUT_CPU_8814B 0x2198
+#define REG_BIST_MISR_DATAOUT_CPU1_8814B 0x219C
+#define REG_BIST_MISR_DATAOUT_CPU2_8814B 0x21A0
+#define REG_BIST_MISR_DATOUT_CPU3_8814B 0x21A4
+#define REG_BCN_CTRL_0_8814B 0x0200
+#define REG_BCN_CTRL_1_8814B 0x0204
+#define REG_AUTO_LLT_V1_8814B 0x0208
+#define REG_TXDMA_OFFSET_CHK_8814B 0x020C
+#define REG_TXDMA_STATUS_8814B 0x0210
+#define REG_TX_DMA_DBG_8814B 0x0214
+#define REG_DMA_RQPN_INFO_PUB_8814B 0x0218
+#define REG_RQPN_CTRL_2_V1_8814B 0x021C
+#define REG_BCN_CTRL_2_8814B 0x0220
+#define REG_TXPKTNUM_0_8814B 0x0230
+#define REG_TXPKTNUM_1_8814B 0x0234
+#define REG_TXPKTNUM_2_8814B 0x0238
+#define REG_TXPKTNUM_3_8814B 0x023C
+#define REG_TX_AGG_ALIGN_8814B 0x0240
+#define REG_H2C_HEAD_8814B 0x0244
+#define REG_H2C_TAIL_8814B 0x0248
+#define REG_H2C_READ_ADDR_8814B 0x024C
+#define REG_H2C_WR_ADDR_8814B 0x0250
+#define REG_H2C_INFO_8814B 0x0254
+#define REG_DMA_OQT_0_8814B 0x0260
+#define REG_DMA_OQT_1_8814B 0x0264
+#define REG_RXDMA_AGG_PG_TH_8814B 0x0280
+#define REG_RXDMA_CTRL_8814B 0x0284
+#define REG_RXDMA_STATUS_8814B 0x0288
+#define REG_RXDMA_DPR_8814B 0x028C
+#define REG_RXDMA_MODE_8814B 0x0290
+#define REG_C2H_PKT_8814B 0x0294
+#define REG_FWFF_C2H_8814B 0x0298
+#define REG_FWFF_CTRL_8814B 0x029C
+#define REG_FWFF_PKT_INFO_8814B 0x02A0
+#define REG_FWFF_PKT_INFO2_8814B 0x02A4
+#define REG_RXPKTNUM_8814B 0x02B0
+#define REG_RXPKTNUM_TH_8814B 0x02B4
+#define REG_FW_UPD_RXDES_RDPTR_8814B 0x02B8
+#define REG_DDMA_CH0SA_8814B 0x1200
+#define REG_DDMA_CH0DA_8814B 0x1204
+#define REG_DDMA_CH0CTRL_8814B 0x1208
+#define REG_DDMA_CH1SA_8814B 0x1210
+#define REG_DDMA_CH1DA_8814B 0x1214
+#define REG_DDMA_CH1CTRL_8814B 0x1218
+#define REG_DDMA_CH2SA_8814B 0x1220
+#define REG_DDMA_CH2DA_8814B 0x1224
+#define REG_DDMA_CH2CTRL_8814B 0x1228
+#define REG_DDMA_CH3SA_8814B 0x1230
+#define REG_DDMA_CH3DA_8814B 0x1234
+#define REG_DDMA_CH3CTRL_8814B 0x1238
+#define REG_DDMA_CH4SA_8814B 0x1240
+#define REG_DDMA_CH4DA_8814B 0x1244
+#define REG_DDMA_CH4CTRL_8814B 0x1248
+#define REG_DDMA_CH5SA_8814B 0x1250
+#define REG_DDMA_CH5DA_8814B 0x1254
+#define REG_DDMA_CH5CTRL_8814B 0x1258
+#define REG_DDMA_INT_MSK_8814B 0x12E0
+#define REG_DDMA_CHSTATUS_8814B 0x12E8
+#define REG_DDMA_CHKSUM_8814B 0x12F0
+#define REG_DDMA_MONITOR_8814B 0x12FC
+#define REG_DMA_RQPN_INFO_0_8814B 0x2200
+#define REG_DMA_RQPN_INFO_1_8814B 0x2204
+#define REG_DMA_RQPN_INFO_2_8814B 0x2208
+#define REG_DMA_RQPN_INFO_3_8814B 0x220C
+#define REG_DMA_RQPN_INFO_4_8814B 0x2210
+#define REG_DMA_RQPN_INFO_5_8814B 0x2214
+#define REG_DMA_RQPN_INFO_6_8814B 0x2218
+#define REG_DMA_RQPN_INFO_7_8814B 0x221C
+#define REG_DMA_RQPN_INFO_8_8814B 0x2220
+#define REG_DMA_RQPN_INFO_9_8814B 0x2224
+#define REG_DMA_RQPN_INFO_10_8814B 0x2228
+#define REG_DMA_RQPN_INFO_11_8814B 0x222C
+#define REG_DMA_RQPN_INFO_12_8814B 0x2230
+#define REG_DMA_RQPN_INFO_13_8814B 0x2234
+#define REG_DMA_RQPN_INFO_14_8814B 0x2238
+#define REG_DMA_RQPN_INFO_15_8814B 0x223C
+#define REG_DMA_RQPN_INFO_16_8814B 0x2240
+#define REG_HWAMSDU_CTL1_8814B 0x2250
+#define REG_HWAMSDU_CTL2_8814B 0x2254
+#define REG_TXPAGE_INT_CTRL_0_8814B 0x3200
+#define REG_TXPAGE_INT_CTRL_1_8814B 0x3204
+#define REG_TXPAGE_INT_CTRL_2_8814B 0x3208
+#define REG_TXPAGE_INT_CTRL_3_8814B 0x320C
+#define REG_TXPAGE_INT_CTRL_4_8814B 0x3210
+#define REG_TXPAGE_INT_CTRL_5_8814B 0x3214
+#define REG_TXPAGE_INT_CTRL_6_8814B 0x3218
+#define REG_TXPAGE_INT_CTRL_7_8814B 0x321C
+#define REG_TXPAGE_INT_CTRL_8_8814B 0x3220
+#define REG_TXPAGE_INT_CTRL_9_8814B 0x3224
+#define REG_TXPAGE_INT_CTRL_10_8814B 0x3228
+#define REG_TXPAGE_INT_CTRL_11_8814B 0x322C
+#define REG_TXPAGE_INT_CTRL_12_8814B 0x3230
+#define REG_TXPAGE_INT_CTRL_13_8814B 0x3234
+#define REG_TXPAGE_INT_CTRL_14_8814B 0x3238
+#define REG_TXPAGE_INT_CTRL_15_8814B 0x323C
+#define REG_TXPAGE_INT_CTRL_16_8814B 0x3240
+#define REG_PCIE_CTRL_8814B 0x0300
+#define REG_ACH_CTRL_8814B 0x0304
+#define REG_HIQ_CTRL_8814B 0x0308
+#define REG_INT_MIG_V1_8814B 0x030C
+#define REG_P0MGQ_TXBD_DESA_L_8814B 0x0310
+#define REG_P0MGQ_TXBD_DESA_H_8814B 0x0314
+#define REG_ACH0_TXBD_DESA_L_8814B 0x0318
+#define REG_ACH0_TXBD_DESA_H_8814B 0x031C
+#define REG_ACH1_TXBD_DESA_L_8814B 0x0320
+#define REG_ACH1_TXBD_DESA_H_8814B 0x0324
+#define REG_ACH2_TXBD_DESA_L_8814B 0x0328
+#define REG_ACH2_TXBD_DESA_H_8814B 0x032C
+#define REG_ACH3_TXBD_DESA_L_8814B 0x0330
+#define REG_ACH3_TXBD_DESA_H_8814B 0x0334
+#define REG_P0RXQ_RXBD_DESA_L_8814B 0x0338
+#define REG_P0RXQ_RXBD_DESA_H_8814B 0x033C
+#define REG_P0BCNQ_TXBD_DESA_L_8814B 0x0340
+#define REG_P0BCNQ_TXBD_DESA_H_8814B 0x0344
+#define REG_FWCMDQ_TXBD_DESA_L_8814B 0x0348
+#define REG_FWCMDQ_TXBD_DESA_H_8814B 0x034C
+#define REG_PCIE_HRPWM1_HCPWM1_DCPU_8814B 0x0354
+#define REG_P0_MPRT_BCNQ_TXBD_DESA_L_8814B 0x0358
+#define REG_P0_MPRT_BCNQ_TXBD_DESA_H_8814B 0x035C
+#define REG_P0_MPRT_BCNQ_TXRXBD_NUM_8814B 0x036C
+#define REG_BD_RWPTR_CLR2_8814B 0x0370
+#define REG_BD_RWPTR_CLR3_8814B 0x0374
+#define REG_P0MGQ_RXQ_TXRXBD_NUM_8814B 0x0378
+#define REG_CHNL_DMA_CFG_8814B 0x037C
+#define REG_FWCMDQ_TXBD_NUM_8814B 0x0380
+#define REG_ACH0_ACH1_TXBD_NUM_8814B 0x0384
+#define REG_ACH2_ACH3_TXBD_NUM_8814B 0x0388
+#define REG_P0HI0Q_HI1Q_TXBD_NUM_8814B 0x038C
+#define REG_P0HI2Q_HI3Q_TXBD_NUM_8814B 0x0390
+#define REG_P0HI4Q_HI5Q_TXBD_NUM_8814B 0x0394
+#define REG_P0HI6Q_HI7Q_TXBD_NUM_8814B 0x0398
+#define REG_BD_RWPTR_CLR1_8814B 0x039C
+#define REG_TSFTIMER_HCI_8814B 0x039C
+#define REG_ACH0_TXBD_IDX_8814B 0x03A0
+#define REG_ACH1_TXBD_IDX_8814B 0x03A4
+#define REG_ACH2_TXBD_IDX_8814B 0x03A8
+#define REG_ACH3_TXBD_IDX_8814B 0x03AC
+#define REG_P0MGQ_TXBD_IDX_8814B 0x03B0
+#define REG_P0RXQ_RXBD_IDX_8814B 0x03B4
+#define REG_P0HI0Q_TXBD_IDX_8814B 0x03B8
+#define REG_P0HI1Q_TXBD_IDX_8814B 0x03BC
+#define REG_P0HI2Q_TXBD_IDX_8814B 0x03C0
+#define REG_P0HI3Q_TXBD_IDX_8814B 0x03C4
+#define REG_P0HI4Q_TXBD_IDX_8814B 0x03C8
+#define REG_P0HI5Q_TXBD_IDX_8814B 0x03CC
+#define REG_P0HI6Q_TXBD_IDX_8814B 0x03D0
+#define REG_P0HI7Q_TXBD_IDX_8814B 0x03D4
+#define REG_DBGSEL_PCIE_HRPWM1_HCPWM1_V1_8814B 0x03D8
+#define REG_PCIE_HRPWM2_HCPWM2_V1_8814B 0x03DC
+#define REG_PCIE_H2C_MSG_V1_8814B 0x03E0
+#define REG_PCIE_C2H_MSG_V1_8814B 0x03E4
+#define REG_DBI_WDATA_V1_8814B 0x03E8
+#define REG_DBI_RDATA_V1_8814B 0x03EC
+#define REG_DBI_FLAG_V1_8814B 0x03F0
+#define REG_MDIO_V1_8814B 0x03F4
+#define REG_PCIE_MIX_CFG_8814B 0x03F8
+#define REG_HCI_MIX_CFG_8814B 0x03FC
+#define REG_STC_INT_CS_8814B 0x1300
+#define REG_ST_INT_CFG_8814B 0x1304
+#define REG_ACH4_ACH5_TXBD_NUM_8814B 0x130C
+#define REG_FWCMDQ_TXBD_IDX_8814B 0x1318
+#define REG_P0HI8Q_TXBD_IDX_8814B 0x131C
+#define REG_H2CQ_TXBD_DESA_L_8814B 0x1320
+#define REG_H2CQ_TXBD_DESA_H_8814B 0x1324
+#define REG_H2CQ_TXBD_NUM_8814B 0x1328
+#define REG_H2CQ_TXBD_IDX_8814B 0x132C
+#define REG_H2CQ_CSR_8814B 0x1330
+#define REG_P0HI9Q_TXBD_IDX_8814B 0x1334
+#define REG_P0HI10Q_TXBD_IDX_8814B 0x1338
+#define REG_P0HI11Q_TXBD_IDX_8814B 0x133C
+#define REG_P0HI12Q_TXBD_IDX_8814B 0x1340
+#define REG_P0HI13Q_TXBD_IDX_8814B 0x1344
+#define REG_P0HI14Q_TXBD_IDX_8814B 0x1348
+#define REG_P0HI15Q_TXBD_IDX_8814B 0x134C
+#define REG_CHANGE_PCIE_SPEED_8814B 0x1350
+#define REG_DEBUG_STATE1_8814B 0x1354
+#define REG_DEBUG_STATE2_8814B 0x1358
+#define REG_DEBUG_STATE3_8814B 0x135C
+#define REG_ACH5_TXBD_DESA_L_8814B 0x1360
+#define REG_ACH5_TXBD_DESA_H_8814B 0x1364
+#define REG_ACH6_TXBD_DESA_L_8814B 0x1368
+#define REG_ACH6_TXBD_DESA_H_8814B 0x136C
+#define REG_ACH7_TXBD_DESA_L_8814B 0x1370
+#define REG_ACH7_TXBD_DESA_H_8814B 0x1374
+#define REG_ACH8_TXBD_DESA_L_8814B 0x1378
+#define REG_ACH8_TXBD_DESA_H_8814B 0x137C
+#define REG_ACH9_TXBD_DESA_L_8814B 0x1380
+#define REG_ACH9_TXBD_DESA_H_8814B 0x1384
+#define REG_ACH10_TXBD_DESA_L_8814B 0x1388
+#define REG_ACH10_TXBD_DESA_H_8814B 0x138C
+#define REG_ACH11_TXBD_DESA_L_8814B 0x1390
+#define REG_ACH11_TXBD_DESA_H_8814B 0x1394
+#define REG_ACH12_TXBD_DESA_L_8814B 0x1398
+#define REG_ACH12_TXBD_DESA_H_8814B 0x139C
+#define REG_ACH13_TXBD_DESA_L_8814B 0x13A0
+#define REG_ACH13_TXBD_DESA_H_8814B 0x13A4
+#define REG_HI0Q_TXBD_DESA_L_8814B 0x13A8
+#define REG_HI0Q_TXBD_DESA_H_8814B 0x13AC
+#define REG_HI1Q_TXBD_DESA_L_8814B 0x13B0
+#define REG_HI1Q_TXBD_DESA_H_8814B 0x13B4
+#define REG_HI2Q_TXBD_DESA_L_8814B 0x13B8
+#define REG_HI2Q_TXBD_DESA_H_8814B 0x13BC
+#define REG_HI3Q_TXBD_DESA_L_8814B 0x13C0
+#define REG_HI3Q_TXBD_DESA_H_8814B 0x13C4
+#define REG_HI4Q_TXBD_DESA_L_8814B 0x13C8
+#define REG_HI4Q_TXBD_DESA_H_8814B 0x13CC
+#define REG_HI5Q_TXBD_DESA_L_8814B 0x13D0
+#define REG_HI5Q_TXBD_DESA_H_8814B 0x13D4
+#define REG_HI6Q_TXBD_DESA_L_8814B 0x13D8
+#define REG_HI6Q_TXBD_DESA_H_8814B 0x13DC
+#define REG_HI7Q_TXBD_DESA_L_8814B 0x13E0
+#define REG_HI7Q_TXBD_DESA_H_8814B 0x13E4
+#define REG_ACH8_ACH9_TXBD_NUM_8814B 0x13E8
+#define REG_ACH10_ACH11_TXBD_NUM_8814B 0x13EC
+#define REG_ACH12_ACH13_TXBD_NUM_8814B 0x13F0
+#define REG_OLD_DEHANG_8814B 0x13F4
+#define REG_ACH4_TXBD_DESA_L_8814B 0x13F8
+#define REG_ACH4_TXBD_DESA_H_8814B 0x13FC
+#define REG_HI8Q_TXBD_DESA_L_8814B 0x2300
+#define REG_HI8Q_TXBD_DESA_H_8814B 0x2304
+#define REG_HI9Q_TXBD_DESA_L_8814B 0x2308
+#define REG_HI9Q_TXBD_DESA_H_8814B 0x230C
+#define REG_HI10Q_TXBD_DESA_L_8814B 0x2310
+#define REG_HI10Q_TXBD_DESA_H_8814B 0x2314
+#define REG_HI11Q_TXBD_DESA_L_8814B 0x2318
+#define REG_HI11Q_TXBD_DESA_H_8814B 0x231C
+#define REG_HI12Q_TXBD_DESA_L_8814B 0x2320
+#define REG_HI12Q_TXBD_DESA_H_8814B 0x2324
+#define REG_HI13Q_TXBD_DESA_L_8814B 0x2328
+#define REG_HI13Q_TXBD_DESA_H_8814B 0x232C
+#define REG_HI14Q_TXBD_DESA_L_8814B 0x2330
+#define REG_HI14Q_TXBD_DESA_H_8814B 0x2334
+#define REG_HI15Q_TXBD_DESA_L_8814B 0x2338
+#define REG_HI15Q_TXBD_DESA_H_8814B 0x233C
+#define REG_HI16Q_TXBD_DESA_L_8814B 0x2340
+#define REG_HI16Q_TXBD_DESA_H_8814B 0x2344
+#define REG_HI17Q_TXBD_DESA_L_8814B 0x2348
+#define REG_HI17Q_TXBD_DESA_H_8814B 0x234C
+#define REG_HI18Q_TXBD_DESA_L_8814B 0x2350
+#define REG_HI18Q_TXBD_DESA_H_8814B 0x2354
+#define REG_HI19Q_TXBD_DESA_L_8814B 0x2358
+#define REG_HI19Q_TXBD_DESA_H_8814B 0x235C
+#define REG_BD_RWPTR_CLR6_8814B 0x2364
+#define REG_P0HI16Q_TXBD_IDX_8814B 0x2370
+#define REG_P0HI17Q_TXBD_IDX_8814B 0x2374
+#define REG_P0HI18Q_TXBD_IDX_8814B 0x2378
+#define REG_P0HI19Q_TXBD_IDX_8814B 0x237C
+#define REG_P0HI16Q_HI17Q_TXBD_NUM_8814B 0x2380
+#define REG_P0HI18Q_HI19Q_TXBD_NUM_8814B 0x2384
+#define REG_PCIE_HISR0_8814B 0x23B4
+#define REG_PCIE_HISR1_8814B 0x23BC
+#define REG_P0HI8Q_HI9Q_TXBD_NUM_8814B 0x23C0
+#define REG_P0HI10Q_HI11Q_TXBD_NUM_8814B 0x23C4
+#define REG_P0HI12Q_HI13Q_TXBD_NUM_8814B 0x23C8
+#define REG_P0HI14Q_HI15Q_TXBD_NUM_8814B 0x23CC
+#define REG_ACH6_ACH7_TXBD_NUM_8814B 0x23F0
+#define REG_ACH4_TXBD_IDX_8814B 0x3340
+#define REG_ACH5_TXBD_IDX_8814B 0x3344
+#define REG_ACH6_TXBD_IDX_8814B 0x3348
+#define REG_ACH7_TXBD_IDX_8814B 0x334C
+#define REG_ACH8_TXBD_IDX_8814B 0x3350
+#define REG_ACH9_TXBD_IDX_8814B 0x3354
+#define REG_ACH10_TXBD_IDX_8814B 0x3358
+#define REG_ACH11_TXBD_IDX_8814B 0x335C
+#define REG_ACH12_TXBD_IDX_8814B 0x3360
+#define REG_ACH13_TXBD_IDX_8814B 0x3364
+#define REG_AC_CHANNEL0_WEIGHT_8814B 0x3368
+#define REG_AC_CHANNEL1_WEIGHT_8814B 0x3369
+#define REG_AC_CHANNEL2_WEIGHT_8814B 0x336A
+#define REG_AC_CHANNEL3_WEIGHT_8814B 0x336B
+#define REG_AC_CHANNEL4_WEIGHT_8814B 0x336C
+#define REG_AC_CHANNEL5_WEIGHT_8814B 0x336D
+#define REG_AC_CHANNEL6_WEIGHT_8814B 0x336E
+#define REG_AC_CHANNEL7_WEIGHT_8814B 0x336F
+#define REG_AC_CHANNEL8_WEIGHT_8814B 0x3370
+#define REG_AC_CHANNEL9_WEIGHT_8814B 0x3371
+#define REG_AC_CHANNEL10_WEIGHT_8814B 0x3372
+#define REG_AC_CHANNEL11_WEIGHT_8814B 0x3373
+#define REG_AC_CHANNEL12_WEIGHT_8814B 0x3374
+#define REG_AC_CHANNEL13_WEIGHT_8814B 0x3375
+#define REG_PCIE_HISR2_8814B 0x33B4
+#define REG_PCIE_HISR3_8814B 0x33BC
+#define REG_QUEUELIST_INFO0_8814B 0x0400
+#define REG_QUEUELIST_INFO1_8814B 0x0404
+#define REG_QUEUELIST_INFO2_8814B 0x0408
+#define REG_QUEUELIST_INFO3_8814B 0x040C
+#define REG_QUEUELIST_INFO_EMPTY_8814B 0x0410
+#define REG_QUEUELIST_ACQ_EN_8814B 0x0414
+#define REG_BCNQ_BDNY_V2_8814B 0x0418
+#define REG_CPU_MGQ_INFO_8814B 0x041C
+#define REG_FWHW_TXQ_CTRL_8814B 0x0420
+#define REG_DATAFB_SEL_8814B 0x0423
+#define REG_TXBDNY_8814B 0x0424
+#define REG_LIFETIME_EN_8814B 0x0426
+#define REG_SPEC_SIFS_8814B 0x0428
+#define REG_RETRY_LIMIT_8814B 0x042A
+#define REG_TXBF_CTRL_8814B 0x042C
+#define REG_DARFRC_8814B 0x0430
+#define REG_DARFRCH_8814B 0x0434
+#define REG_RARFRC_8814B 0x0438
+#define REG_RARFRCH_8814B 0x043C
+#define REG_RRSR_8814B 0x0440
+#define REG_ARFR0_8814B 0x0444
+#define REG_ARFRH0_8814B 0x0448
+#define REG_REG_ARFR_WT0_8814B 0x044C
+#define REG_REG_ARFR_WT1_8814B 0x0450
+#define REG_CCK_CHECK_8814B 0x0454
+#define REG_AMPDU_MAX_TIME_V1_8814B 0x0455
+#define REG_TAB_SEL_8814B 0x0456
+#define REG_BCN_INVALID_CTRL_8814B 0x0457
+#define REG_AMPDU_MAX_LENGTH_HT_8814B 0x0458
+#define REG_NDPA_RATE_8814B 0x045D
+#define REG_TX_HANG_CTRL_8814B 0x045E
+#define REG_NDPA_OPT_CTRL_8814B 0x045F
+#define REG_AMPDU_MAX_LENGTH_VHT_8814B 0x0460
+#define REG_RD_RESP_PKT_TH_8814B 0x0463
+#define REG_NEW_EDCA_CTRL_V1_8814B 0x0464
+#define REG_ACQ_STOP_V2_8814B 0x0468
+#define REG_WMAC_LBK_BUF_HD_V1_8814B 0x0478
+#define REG_MGQ_BDNY_V1_8814B 0x047A
+#define REG_TXRPT_CTRL_8814B 0x047C
+#define REG_INIRTS_RATE_SEL_8814B 0x0480
+#define REG_BASIC_CFEND_RATE_8814B 0x0481
+#define REG_STBC_CFEND_RATE_8814B 0x0482
+#define REG_DATA_SC_8814B 0x0483
+#define REG_MOREDATA_V1_8814B 0x0484
+#define REG_DATA_SC1_8814B 0x0487
+#define REG_TXRPT_START_OFFSET_8814B 0x04AC
+#define REG_POWER_STAGE1_8814B 0x04B4
+#define REG_POWER_STAGE2_8814B 0x04B8
+#define REG_SW_AMPDU_BURST_MODE_CTRL_8814B 0x04BC
+#define REG_PKT_LIFE_TIME_8814B 0x04C0
+#define REG_STBC_SETTING_8814B 0x04C4
+#define REG_STBC_SETTING2_8814B 0x04C5
+#define REG_QUEUE_CTRL_8814B 0x04C6
+#define REG_SINGLE_AMPDU_CTRL_8814B 0x04C7
+#define REG_PROT_MODE_CTRL_8814B 0x04C8
+#define REG_BAR_MODE_CTRL_8814B 0x04CC
+#define REG_RA_TRY_RATE_AGG_LMT_8814B 0x04CF
+#define REG_MACID_SLEEP_CTRL_8814B 0x04D0
+#define REG_MACID_SLEEP_INFO_8814B 0x04D4
+#define REG_HW_SEQ0_8814B 0x04D8
+#define REG_HW_SEQ1_8814B 0x04DA
+#define REG_HW_SEQ2_8814B 0x04DC
+#define REG_HW_SEQ3_8814B 0x04DE
+#define REG_PTCL_ERR_STATUS_V1_8814B 0x04E2
+#define REG_NULL_PKT_STATUS_V2_8814B 0x04E4
+#define REG_PRECNT_CTRL_8814B 0x04E5
+#define REG_NULL_PKT_STATUS_EXTEND_V1_8814B 0x04E7
+#define REG_PTCL_DBG_V1_8814B 0x04EC
+#define REG_BT_POLLUTE_PKTCNT_8814B 0x04F0
+#define REG_CPUMGQ_TIMER_CTRL2_8814B 0x04F4
+#define REG_PTCL_DBG_OUT_8814B 0x04F8
+#define REG_DUMMY_PAGE4_V1_8814B 0x04FC
+#define REG_DUMMY_PAGE4_1_8814B 0x04FE
+#define REG_MU_OFFSET_8814B 0x1400
+#define REG_BF0_TIME_SETTING_8814B 0x1428
+#define REG_BF1_TIME_SETTING_8814B 0x142C
+#define REG_BF_TIMEOUT_EN_8814B 0x1430
+#define REG_MACID_RELEASE_INFO_8814B 0x1434
+#define REG_MACID_RELEASE_SUCCESS_INFO_8814B 0x1438
+#define REG_MACID_RELEASE_CTRL_8814B 0x143C
+#define REG_FAST_EDCA_VOVI_SETTING_8814B 0x1448
+#define REG_FAST_EDCA_BEBK_SETTING_8814B 0x144C
+#define REG_MACID_DROP_INFO_8814B 0x1450
+#define REG_MACID_DROP_CTRL_8814B 0x1454
+#define REG_MGQ_FIFO_WRITE_POINTER_8814B 0x1470
+#define REG_MGQ_FIFO_READ_POINTER_8814B 0x1472
+#define REG_MGQ_FIFO_ENABLE_8814B 0x1472
+#define REG_MGQ_FIFO_RELEASE_INT_MASK_8814B 0x1474
+#define REG_MGQ_FIFO_RELEASE_INT_FLAG_8814B 0x1476
+#define REG_MGQ_FIFO_VALID_MAP_8814B 0x1478
+#define REG_MGQ_FIFO_LIFETIME_8814B 0x147A
+#define REG_PKT_TRANS_8814B 0x1480
+#define REG_SHCUT_LLC_ETH_TYPE0_8814B 0x1484
+#define REG_SHCUT_LLC_ETH_TYPE1_8814B 0x1488
+#define REG_SHCUT_LLC_OUI0_8814B 0x148C
+#define REG_SHCUT_LLC_OUI1_8814B 0x1490
+#define REG_SHCUT_LLC_OUI2_8814B 0x1494
+#define REG_FWCMDQ_CTRL_8814B 0x14A0
+#define REG_FWCMDQ_PAGE_8814B 0x14A4
+#define REG_FWCMDQ_INFO_8814B 0x14A8
+#define REG_FWCMDQ_HOLD_PKTNUM_8814B 0x14AC
+#define REG_MU_TX_CTRL_8814B 0x14C0
+#define REG_MU_STA_GID_VLD_8814B 0x14C4
+#define REG_MU_STA_USER_POS_INFO_8814B 0x14C8
+#define REG_MU_STA_USER_POS_INFO_H_8814B 0x14CC
+#define REG_CHNL_INFO_CTRL_8814B 0x14D0
+#define REG_CHNL_IDLE_TIME_8814B 0x14D4
+#define REG_CHNL_BUSY_TIME_8814B 0x14D8
+#define REG_MU_TRX_DBG_CNT_V1_8814B 0x14DC
+#define REG_SWPS_CTRL_8814B 0x14F4
+#define REG_SWPS_PKT_TH_8814B 0x14F6
+#define REG_SWPS_TIME_TH_8814B 0x14F8
+#define REG_MACID_SWPS_EN_8814B 0x14FC
+#define REG_EDCA_VO_PARAM_8814B 0x0500
+#define REG_EDCA_VI_PARAM_8814B 0x0504
+#define REG_EDCA_BE_PARAM_8814B 0x0508
+#define REG_EDCA_BK_PARAM_8814B 0x050C
+#define REG_BCNTCFG_8814B 0x0510
+#define REG_PIFS_8814B 0x0512
+#define REG_RDG_PIFS_8814B 0x0513
+#define REG_SIFS_8814B 0x0514
+#define REG_FORCE_BCN_IFS_V1_8814B 0x0518
+#define REG_AGGR_BREAK_TIME_8814B 0x051A
+#define REG_SLOT_8814B 0x051B
+#define REG_EDCA_CPUMGQ_PARAM_8814B 0x051C
+#define REG_CPUMGQ_PAUSE_8814B 0x051E
+#define REG_TX_PTCL_CTRL_8814B 0x0520
+#define REG_TXPAUSE_8814B 0x0522
+#define REG_DIS_TXREQ_CLR_8814B 0x0523
+#define REG_RD_CTRL_8814B 0x0524
+#define REG_PKT_LIFETIME_CTRL_8814B 0x0528
+#define REG_TXOP_LIMIT_CTRL_8814B 0x052C
+#define REG_CCA_TXEN_CNT_8814B 0x0534
+#define REG_MAX_INTER_COLLISION_8814B 0x0538
+#define REG_MAX_INTER_COLLISION_CNT_8814B 0x053C
+#define REG_RD_NAV_NXT_8814B 0x0544
+#define REG_NAV_PROT_LEN_8814B 0x0546
+#define REG_FTM_PTT_8814B 0x0548
+#define REG_FTM_TSF_8814B 0x054C
+#define REG_HGQ_TIMEOUT_PERIOD_8814B 0x0575
+#define REG_TXCMD_TIMEOUT_PERIOD_8814B 0x0576
+#define REG_MISC_CTRL_8814B 0x0577
+#define REG_TXOP_MIN_8814B 0x0590
+#define REG_PRE_BKF_TIME_8814B 0x0592
+#define REG_CROSS_TXOP_CTRL_8814B 0x0593
+#define REG_ACMHWCTRL_8814B 0x05C0
+#define REG_ACMRSTCTRL_8814B 0x05C1
+#define REG_ACMAVG_8814B 0x05C2
+#define REG_VO_ADMTIME_8814B 0x05C4
+#define REG_VI_ADMTIME_8814B 0x05C6
+#define REG_BE_ADMTIME_8814B 0x05C8
+#define REG_MAC_HEADER_NAV_OFFSET_8814B 0x05CA
+#define REG_DIS_NDPA_NAV_CHECK_8814B 0x05CB
+#define REG_EDCA_RANDOM_GEN_8814B 0x05CC
+#define REG_TXCMD_SEL_8814B 0x05CF
+#define REG_MU_DBG_INFO_8814B 0x05E8
+#define REG_MU_DBG_INFO_1_8814B 0x05EC
+#define REG_SCH_DBG_SEL_8814B 0x05F0
+#define REG_SCHEDULER_RST_8814B 0x05F1
+#define REG_MU_DBG_ERR_FLAG_8814B 0x05F2
+#define REG_TX_ERR_RECOVERY_RST_8814B 0x05F3
+#define REG_SCH_DBG_VALUE_8814B 0x05F4
+#define REG_SCH_TXCMD_8814B 0x05F8
+#define REG_PAGE5_DUMMY_8814B 0x05FC
+#define REG_PORT_CTRL_SEL_8814B 0x1500
+#define REG_PORT_CTRL_CFG_8814B 0x1501
+#define REG_TBTT_PROHIBIT_CFG_8814B 0x1504
+#define REG_DRVERLYINT_CFG_8814B 0x1507
+#define REG_BCNDMATIM_CFG_8814B 0x1508
+#define REG_CTWND_CFG_8814B 0x1509
+#define REG_BCNIVLCUNT_CFG_8814B 0x150A
+#define REG_EARLY_128US_CFG_8814B 0x150B
+#define REG_TSFTR_SYNC_OFFSET_CFG_8814B 0x150C
+#define REG_TSFTR_SYNC_CTRL_CFG_8814B 0x150F
+#define REG_BCN_SPACE_CFG_8814B 0x1510
+#define REG_EARLY_INT_ADJUST_CFG_8814B 0x1512
+#define REG_SW_TBTT_TSF_INFO_8814B 0x151C
+#define REG_TSFTR_LOW_8814B 0x1520
+#define REG_TSFTR_HIGH_8814B 0x1524
+#define REG_BCN_ERR_CNT_MAC_8814B 0x1528
+#define REG_BCN_ERR_CNT_EDCCA_8814B 0x1529
+#define REG_BCN_ERR_CNT_CCA_8814B 0x152A
+#define REG_BCN_ERR_CNT_INVALID_8814B 0x152B
+#define REG_BCN_ERR_CNT_OTHERS_8814B 0x152C
+#define REG_RX_BCN_TIMER_8814B 0x152D
+#define REG_TBTT_CTN_AREA_V1_8814B 0x1530
+#define REG_BCN_MAX_ERR_V1_8814B 0x1531
+#define REG_RXTSF_OFFSET_CCK_V1_8814B 0x1532
+#define REG_RXTSF_OFFSET_OFDM_V1_8814B 0x1533
+#define REG_SUB_BCN_SPACE_8814B 0x1534
+#define REG_MBID_NUM_V1_8814B 0x1535
+#define REG_MBSSID_CTRL_V1_8814B 0x1536
+#define REG_USTIME_TSF_V1_8814B 0x1538
+#define REG_BW_CFG_8814B 0x1539
+#define REG_ATIMWND_CFG_8814B 0x153A
+#define REG_DTIM_COUNTER_CFG_8814B 0x153B
+#define REG_ATIM_DTIM_CTRL_SEL_8814B 0x153C
+#define REG_ATIMUGT_V1_8814B 0x153D
+#define REG_BCNDROPCTRL_V1_8814B 0x153E
+#define REG_DIS_ATIM_V1_8814B 0x1540
+#define REG_HIQ_NO_LMT_EN_V1_8814B 0x1544
+#define REG_P2PPS_CTRL_V1_8814B 0x1548
+#define REG_P2PPS_SPEC_STATE_V1_8814B 0x154A
+#define REG_P2PPS_STATE_V1_8814B 0x154B
+#define REG_P2PPS1_CTRL_V1_8814B 0x154C
+#define REG_P2PPS1_SPEC_STATE_V1_8814B 0x154E
+#define REG_P2PPS1_STATE_V1_8814B 0x154F
+#define REG_P2PPS2_CTRL_V1_8814B 0x1550
+#define REG_P2PPS2_SPEC_STATE_V1_8814B 0x1552
+#define REG_P2PPS2_STATE_V1_8814B 0x1553
+#define REG_P2PON_DIS_TXTIME_V1_8814B 0x1554
+#define REG_P2POFF_DIS_TXTIME_V1_8814B 0x1555
+#define REG_CHG_POWER_BCN_AREA_8814B 0x1556
+#define REG_NOA_SEL_8814B 0x1557
+#define REG_NOA_PARAM_V1_8814B 0x1558
+#define REG_NOA_PARAM_1_V1_8814B 0x155C
+#define REG_NOA_PARAM_2_V1_8814B 0x1560
+#define REG_NOA_PARAM_3_V1_8814B 0x1564
+#define REG_NOA_ON_ERLY_TIME_V1_8814B 0x1568
+#define REG_NOA_OFF_ERLY_TIME_V1_8814B 0x1569
+#define REG_P2PPS_HW_AUTO_PAUSE_CTRL_8814B 0x156C
+#define REG_P2PPS1_HW_AUTO_PAUSE_CTRL_8814B 0x1570
+#define REG_P2PPS2_HW_AUTO_PAUSE_CTRL_8814B 0x1574
+#define REG_RX_TBTT_SHIFT_8814B 0x1578
+#define REG_FREERUN_CNT_LOW_8814B 0x1580
+#define REG_FREERUN_CNT_HIGH_8814B 0x1584
+#define REG_CPUMGQ_TX_TIMER_V1_8814B 0x1588
+#define REG_PS_TIMER_0_8814B 0x158C
+#define REG_PS_TIMER_1_8814B 0x1590
+#define REG_PS_TIMER_2_8814B 0x1594
+#define REG_PS_TIMER_3_8814B 0x1598
+#define REG_PS_TIMER_4_8814B 0x159C
+#define REG_PS_TIMER_5_8814B 0x15A0
+#define REG_PS_TIMER_01_CTRL_8814B 0x15A4
+#define REG_PS_TIMER_23_CTRL_8814B 0x15A8
+#define REG_PS_TIMER_45_CTRL_8814B 0x15AC
+#define REG_CPUMGQ_FREERUN_TIMER_CTRL_8814B 0x15B0
+#define REG_CPUMGQ_PROHIBIT_8814B 0x15B4
+#define REG_TIMER_COMPARE_8814B 0x15C0
+#define REG_TIMER_COMPARE_VALUE_LOW_8814B 0x15C4
+#define REG_TIMER_COMPARE_VALUE_HIGH_8814B 0x15C8
+#define REG_SCHEDULER_COUNTER_8814B 0x15D0
+#define REG_WMAC_CR_8814B 0x0600
+#define REG_WMAC_FWPKT_CR_8814B 0x0601
+#define REG_FW_STS_FILTER_8814B 0x0602
+#define REG_TCR_8814B 0x0604
+#define REG_RCR_8814B 0x0608
+#define REG_RX_PKT_LIMIT_8814B 0x060C
+#define REG_RX_DLK_TIME_8814B 0x060D
+#define REG_RX_DRVINFO_SZ_8814B 0x060F
+#define REG_MACID_8814B 0x0610
+#define REG_MACID_H_8814B 0x0614
+#define REG_BSSID_8814B 0x0618
+#define REG_BSSID_H_8814B 0x061C
+#define REG_MAR_8814B 0x0620
+#define REG_MAR_H_8814B 0x0624
+#define REG_WMAC_DEBUG_SEL_8814B 0x062C
+#define REG_WMAC_TCR_TSFT_OFS_8814B 0x0630
+#define REG_UDF_THSD_8814B 0x0632
+#define REG_ZLD_NUM_8814B 0x0633
+#define REG_STMP_THSD_8814B 0x0634
+#define REG_WMAC_TXTIMEOUT_8814B 0x0635
+#define REG_MCU_TEST_2_V1_8814B 0x0636
+#define REG_USTIME_EDCA_8814B 0x0638
+#define REG_ACKTO_CCK_8814B 0x0639
+#define REG_MAC_SPEC_SIFS_8814B 0x063A
+#define REG_RESP_SIFS_CCK_8814B 0x063C
+#define REG_RESP_SIFS_OFDM_8814B 0x063E
+#define REG_ACKTO_8814B 0x0640
+#define REG_CTS2TO_8814B 0x0641
+#define REG_EIFS_8814B 0x0642
+#define REG_RPFM_MAP0_8814B 0x0644
+#define REG_RPFM_MAP1_V1_8814B 0x0646
+#define REG_RPFM_CAM_CMD_8814B 0x0648
+#define REG_RPFM_CAM_RWD_8814B 0x064C
+#define REG_NAV_CTRL_8814B 0x0650
+#define REG_BACAMCMD_8814B 0x0654
+#define REG_BACAMCONTENT_8814B 0x0658
+#define REG_BACAMCONTENT_H_8814B 0x065C
+#define REG_LBDLY_8814B 0x0660
+#define REG_WMAC_BACAM_RPMEN_8814B 0x0661
+#define REG_TX_RX_8814B 0x0662
+#define REG_WMAC_BITMAP_CTL_8814B 0x0663
+#define REG_RXERR_RPT_8814B 0x0664
+#define REG_WMAC_TRXPTCL_CTL_8814B 0x0668
+#define REG_WMAC_TRXPTCL_CTL_H_8814B 0x066C
+#define REG_CAMCMD_8814B 0x0670
+#define REG_CAMWRITE_8814B 0x0674
+#define REG_CAMREAD_8814B 0x0678
+#define REG_CAMDBG_8814B 0x067C
+#define REG_SECCFG_8814B 0x0680
+#define REG_RXFILTER_CATEGORY_1_8814B 0x0682
+#define REG_RXFILTER_ACTION_1_8814B 0x0683
+#define REG_RXFILTER_CATEGORY_2_8814B 0x0684
+#define REG_RXFILTER_ACTION_2_8814B 0x0685
+#define REG_RXFILTER_CATEGORY_3_8814B 0x0686
+#define REG_RXFILTER_ACTION_3_8814B 0x0687
+#define REG_RXFLTMAP3_8814B 0x0688
+#define REG_RXFLTMAP4_8814B 0x068A
+#define REG_RXFLTMAP5_8814B 0x068C
+#define REG_RXFLTMAP6_8814B 0x068E
+#define REG_WOW_CTRL_8814B 0x0690
+#define REG_NAN_RX_TSF_FILTER_8814B 0x0691
+#define REG_PS_RX_INFO_8814B 0x0692
+#define REG_WMMPS_UAPSD_TID_8814B 0x0693
+#define REG_LPNAV_CTRL_8814B 0x0694
+#define REG_WKFMCAM_CMD_8814B 0x0698
+#define REG_WKFMCAM_RWD_8814B 0x069C
+#define REG_RXFLTMAP0_8814B 0x06A0
+#define REG_RXFLTMAP1_8814B 0x06A2
+#define REG_RXFLTMAP2_8814B 0x06A4
+#define REG_BCN_PSR_RPT_8814B 0x06A8
+#define REG_FLC_RPC_8814B 0x06AC
+#define REG_FLC_RPCT_8814B 0x06AD
+#define REG_FLC_PTS_8814B 0x06AE
+#define REG_FLC_TRPC_8814B 0x06AF
+#define REG_RXPKTMON_CTRL_8814B 0x06B0
+#define REG_STATE_MON_8814B 0x06B4
+#define REG_ERROR_MON_8814B 0x06B8
+#define REG_SEARCH_MACID_8814B 0x06BC
+#define REG_BT_COEX_TABLE_8814B 0x06C0
+#define REG_BT_COEX_TABLE2_8814B 0x06C4
+#define REG_BT_COEX_BREAK_TABLE_8814B 0x06C8
+#define REG_BT_COEX_TABLE_H_8814B 0x06CC
+#define REG_RXCMD_0_8814B 0x06D0
+#define REG_RXCMD_1_8814B 0x06D4
+#define REG_WMAC_RESP_TXINFO_8814B 0x06D8
+#define REG_BBPSF_CTRL_8814B 0x06DC
+#define REG_P2P_RX_BCN_NOA_8814B 0x06E0
+#define REG_ASSOCIATED_BFMER0_INFO_8814B 0x06E4
+#define REG_ASSOCIATED_BFMER0_INFO_H_8814B 0x06E8
+#define REG_ASSOCIATED_BFMER1_INFO_8814B 0x06EC
+#define REG_ASSOCIATED_BFMER1_INFO_H_8814B 0x06F0
+#define REG_TX_CSI_RPT_PARAM_BW20_8814B 0x06F4
+#define REG_TX_CSI_RPT_PARAM_BW40_8814B 0x06F8
+#define REG_BCN_PSR_RPT2_8814B 0x1600
+#define REG_BCN_PSR_RPT3_8814B 0x1604
+#define REG_BCN_PSR_RPT4_8814B 0x1608
+#define REG_A1_ADDR_MASK_8814B 0x160C
+#define REG_RXPSF_CTRL_8814B 0x1610
+#define REG_RXPSF_TYPE_CTRL_8814B 0x1614
+#define REG_CAM_ACCESS_CTRL_8814B 0x1618
+#define REG_CUT_AMSDU_CTRL_8814B 0x161C
+#define REG_MACID2_8814B 0x1620
+#define REG_MACID2_H_8814B 0x1624
+#define REG_BSSID2_8814B 0x1628
+#define REG_BSSID2_H_8814B 0x162C
+#define REG_MACID3_8814B 0x1630
+#define REG_MACID3_H_8814B 0x1634
+#define REG_BSSID3_8814B 0x1638
+#define REG_BSSID3_H_8814B 0x163C
+#define REG_MACID4_8814B 0x1640
+#define REG_MACID4_H_8814B 0x1644
+#define REG_BSSID4_8814B 0x1648
+#define REG_BSSID4_H_8814B 0x164C
+#define REG_NOA_REPORT_8814B 0x1650
+#define REG_NOA_REPORT_1_8814B 0x1654
+#define REG_NOA_REPORT_2_8814B 0x1658
+#define REG_NOA_REPORT_3_8814B 0x165C
+#define REG_PWRBIT_SETTING_8814B 0x1660
+#define REG_GENERAL_OPTION_8814B 0x1664
+#define REG_FWPHYFF_RCR_8814B 0x1668
+#define REG_ADDRCAM_WRITE_CONTENT_8814B 0x166C
+#define REG_ADDRCAM_READ_CONTENT_8814B 0x1670
+#define REG_ADDRCAM_CFG_8814B 0x1674
+#define REG_CSI_RRSR_8814B 0x1678
+#define REG_MU_BF_OPTION_8814B 0x167C
+#define REG_WMAC_PAUSE_BB_CLR_TH_8814B 0x167D
+#define REG_WMAC_MULBK_BUF_8814B 0x167E
+#define REG_WMAC_MU_OPTION_8814B 0x167F
+#define REG_WMAC_MU_BF_CTL_8814B 0x1680
+#define REG_WMAC_MU_BFRPT_PARA_8814B 0x1682
+#define REG_WMAC_ASSOCIATED_MU_BFMEE2_8814B 0x1684
+#define REG_WMAC_ASSOCIATED_MU_BFMEE3_8814B 0x1686
+#define REG_WMAC_ASSOCIATED_MU_BFMEE4_8814B 0x1688
+#define REG_WMAC_ASSOCIATED_MU_BFMEE5_8814B 0x168A
+#define REG_WMAC_ASSOCIATED_MU_BFMEE6_8814B 0x168C
+#define REG_WMAC_ASSOCIATED_MU_BFMEE7_8814B 0x168E
+#define REG_WMAC_BB_STOP_RX_COUNTER_8814B 0x1690
+#define REG_WMAC_PLCP_MONITOR_8814B 0x1694
+#define REG_WMAC_DEBUG_PORT_8814B 0x1698
+#define REG_TRANSMIT_ADDRSS_0_8814B 0x16A0
+#define REG_TRANSMIT_ADDRSS_0_H_8814B 0x16A4
+#define REG_TRANSMIT_ADDRSS_1_8814B 0x16A8
+#define REG_TRANSMIT_ADDRSS_1_H_8814B 0x16AC
+#define REG_TRANSMIT_ADDRSS_2_8814B 0x16B0
+#define REG_TRANSMIT_ADDRSS_2_H_8814B 0x16B4
+#define REG_TRANSMIT_ADDRSS_3_8814B 0x16B8
+#define REG_TRANSMIT_ADDRSS_3_H_8814B 0x16BC
+#define REG_TRANSMIT_ADDRSS_4_8814B 0x16C0
+#define REG_TRANSMIT_ADDRSS_4_H_8814B 0x16C4
+#define REG_MACID1_8814B 0x0700
+#define REG_MACID1_1_8814B 0x0704
+#define REG_BSSID1_8814B 0x0708
+#define REG_BSSID1_1_8814B 0x070C
+#define REG_BCN_PSR_RPT1_8814B 0x0710
+#define REG_ASSOCIATED_BFMEE_SEL_8814B 0x0714
+#define REG_SND_PTCL_CTRL_8814B 0x0718
+#define REG_RX_CSI_RPT_INFO_8814B 0x071C
+#define REG_NS_ARP_CTRL_8814B 0x0720
+#define REG_NS_ARP_INFO_8814B 0x0724
+#define REG_BEAMFORMING_INFO_NSARP_V1_8814B 0x0728
+#define REG_BEAMFORMING_INFO_NSARP_8814B 0x072C
+#define REG_IPV6_8814B 0x0730
+#define REG_IPV6_1_8814B 0x0734
+#define REG_IPV6_2_8814B 0x0738
+#define REG_IPV6_3_8814B 0x073C
+#define REG_WMAC_RTX_CTX_SUBTYPE_CFG_8814B 0x0750
+#define REG_WMAC_SWAES_CFG_8814B 0x0760
+#define REG_BT_COEX_V2_8814B 0x0762
+#define REG_BT_COEX_8814B 0x0764
+#define REG_WLAN_ACT_MASK_CTRL_8814B 0x0768
+#define REG_WLAN_ACT_MASK_CTRL_1_8814B 0x076C
+#define REG_BT_COEX_ENHANCED_INTR_CTRL_8814B 0x076E
+#define REG_BT_ACT_STATISTICS_8814B 0x0770
+#define REG_BT_ACT_STATISTICS_1_8814B 0x0774
+#define REG_BT_STATISTICS_CONTROL_REGISTER_8814B 0x0778
+#define REG_BT_STATUS_REPORT_REGISTER_8814B 0x077C
+#define REG_BT_INTERRUPT_CONTROL_REGISTER_8814B 0x0780
+#define REG_WLAN_REPORT_TIME_OUT_CONTROL_REGISTER_8814B 0x0784
+#define REG_BT_ISOLATION_TABLE_REGISTER_REGISTER_8814B 0x0785
+#define REG_BT_ISOLATION_TABLE_REGISTER_REGISTER_1_8814B 0x0788
+#define REG_BT_ISOLATION_TABLE_REGISTER_REGISTER_2_8814B 0x078C
+#define REG_BT_INTERRUPT_STATUS_REGISTER_8814B 0x078F
+#define REG_BT_TDMA_TIME_REGISTER_8814B 0x0790
+#define REG_BT_ACT_REGISTER_8814B 0x0794
+#define REG_OBFF_CTRL_BASIC_8814B 0x0798
+#define REG_OBFF_CTRL2_TIMER_8814B 0x079C
+#define REG_LTR_CTRL_BASIC_8814B 0x07A0
+#define REG_LTR_CTRL2_TIMER_THRESHOLD_8814B 0x07A4
+#define REG_LTR_IDLE_LATENCY_V1_8814B 0x07A8
+#define REG_LTR_ACTIVE_LATENCY_V1_8814B 0x07AC
+#define REG_SMART_ANT_CONDITION_8814B 0x07B0
+#define REG_SMART_ANT_CTRL_8814B 0x07B4
+#define REG_CONTROL_FRAME_REPORT_8814B 0x07B8
+#define REG_CONTROL_FRAME_CNT_CTRL_8814B 0x07BC
+#define REG_IQ_DUMP_8814B 0x07C0
+#define REG_IQ_DUMP_1_8814B 0x07C4
+#define REG_IQ_DUMP_2_8814B 0x07C8
+#define REG_WMAC_FTM_CTL_8814B 0x07CC
+#define REG_WMAC_IQ_MDPK_FUNC_8814B 0x07CE
+#define REG_WMAC_OPTION_FUNCTION_8814B 0x07D0
+#define REG_WMAC_OPTION_FUNCTION_1_8814B 0x07D4
+#define REG_WMAC_OPTION_FUNCTION_2_8814B 0x07D8
+#define REG_RX_FILTER_FUNCTION_8814B 0x07DA
+#define REG_NDP_SIG_8814B 0x07E0
+#define REG_TXCMD_INFO_FOR_RSP_PKT_8814B 0x07E4
+#define REG_TXCMD_INFO_FOR_RSP_PKT_1_8814B 0x07E8
+#define REG_WSEC_OPTION_8814B 0x07EC
+#define REG_RTS_ADDRESS_0_8814B 0x07F0
+#define REG_RTS_ADDRESS_0_1_8814B 0x07F4
+#define REG_RTS_ADDRESS_1_8814B 0x07F8
+#define REG_RTS_ADDRESS_1_1_8814B 0x07FC
+#define REG_WL2LTECOEX_INDIRECT_ACCESS_CTRL_V1_8814B 0x1700
+#define REG_WL2LTECOEX_INDIRECT_ACCESS_WRITE_DATA_V1_8814B 0x1704
+#define REG_WL2LTECOEX_INDIRECT_ACCESS_READ_DATA_V1_8814B 0x1708
+#define REG_PCIE_CFG_FORCE_LINK_L_8814B 0x0709
+#define REG_PCIE_CFG_FORCE_LINK_H_8814B 0x070A
+#define REG_PCIE_CFG_DEFAULT_ACK_FREQUENCY_8814B 0x070C
+#define REG_PCIE_CFG_CX_NFTS_8814B 0x070D
+#define REG_PCIE_CFG_DEFAULT_ENTR_LATENCY_8814B 0x070F
+#define REG_PCIE_CFG_L1_MISC_SEL_8814B 0x0711
+#define REG_PCIE_CFG_TIMER_CTRL_MAX_FUNC_NUM_OFF_8814B 0x0718
+#define REG_PCIE_CFG_FORCE_CLKREQ_N_PAD_8814B 0x0719
+#define REG_PCIE_CFG_TIMER_MODIFIER_FOR_ACK_NAK_LATENCY_8814B 0x071A
+#define REG_PCIE_CFG_TIMER_MODIFIER_FOR_FLOW_CONTROL_WATCHDOG_8814B 0x071B
+#define REG_PCIE_CFG_SKP_INTERVAL_VALUE_L_8814B 0x071C
+#define REG_PCIE_CFG_SKP_INTERVAL_VALUE_H_8814B 0x071D
+#define REG_PCIE_CFG_L1_UNIT_SEL_8814B 0x0724
+#define REG_PCIE_CFG_MIN_CLKREQ_SEL_8814B 0x0725
+#define REG_SDIO_TX_CTRL_8814B 0x10250000
+#define REG_SDIO_HIMR_8814B 0x10250014
+#define REG_SDIO_HISR_8814B 0x10250018
+#define REG_SDIO_RX_REQ_LEN_8814B 0x1025001C
+#define REG_SDIO_FREE_TXPG_SEQ_V1_8814B 0x1025001F
+#define REG_SDIO_FREE_TXPG_8814B 0x10250020
+#define REG_SDIO_FREE_TXPG2_8814B 0x10250024
+#define REG_SDIO_OQT_FREE_TXPG_V1_8814B 0x10250028
+#define REG_SDIO_HTSFR_INFO_8814B 0x10250030
+#define REG_SDIO_HCPWM1_V2_8814B 0x10250038
+#define REG_SDIO_HCPWM2_V2_8814B 0x1025003A
+#define REG_SDIO_INDIRECT_REG_CFG_8814B 0x10250040
+#define REG_SDIO_INDIRECT_REG_DATA_8814B 0x10250044
+#define REG_SDIO_H2C_8814B 0x10250060
+#define REG_SDIO_C2H_8814B 0x10250064
+#define REG_SDIO_HRPWM1_8814B 0x10250080
+#define REG_SDIO_HRPWM2_8814B 0x10250082
+#define REG_SDIO_HPS_CLKR_8814B 0x10250084
+#define REG_SDIO_BUS_CTRL_8814B 0x10250085
+#define REG_SDIO_HSUS_CTRL_8814B 0x10250086
+#define REG_SDIO_RESPONSE_TIMER_8814B 0x10250088
+#define REG_SDIO_CMD_CRC_8814B 0x1025008A
+#define REG_SDIO_HSISR_8814B 0x10250090
+#define REG_SDIO_ERR_RPT_8814B 0x102500C0
+#define REG_SDIO_CMD_ERRCNT_8814B 0x102500C2
+#define REG_SDIO_DATA_ERRCNT_8814B 0x102500C3
+#define REG_SDIO_CMD_ERR_CONTENT_8814B 0x102500C4
+#define REG_SDIO_CRC_ERR_IDX_8814B 0x102500C9
+#define REG_SDIO_DATA_CRC_8814B 0x102500CA
+#define REG_SDIO_DATA_REPLY_TIME_8814B 0x102500CB
+
+#endif
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/halmac/halmac_reg_8821c.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/halmac/halmac_reg_8821c.h
--- linux-5.6.3/3rdparty/rtl8821ce/hal/halmac/halmac_reg_8821c.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/halmac/halmac_reg_8821c.h	2020-04-10 16:35:06.816660067 +0300
@@ -0,0 +1,803 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ ******************************************************************************/
+
+#ifndef __INC_HALMAC_REG_8821C_H
+#define __INC_HALMAC_REG_8821C_H
+
+#define REG_SYS_ISO_CTRL_8821C 0x0000
+#define REG_SYS_FUNC_EN_8821C 0x0002
+#define REG_SYS_PW_CTRL_8821C 0x0004
+#define REG_SYS_CLK_CTRL_8821C 0x0008
+#define REG_SYS_EEPROM_CTRL_8821C 0x000A
+#define REG_EE_VPD_8821C 0x000C
+#define REG_SYS_SWR_CTRL1_8821C 0x0010
+#define REG_SYS_SWR_CTRL2_8821C 0x0014
+#define REG_SYS_SWR_CTRL3_8821C 0x0018
+#define REG_RSV_CTRL_8821C 0x001C
+#define REG_RF_CTRL_8821C 0x001F
+#define REG_AFE_LDO_CTRL_8821C 0x0020
+#define REG_AFE_CTRL1_8821C 0x0024
+#define REG_AFE_CTRL2_8821C 0x0028
+#define REG_AFE_CTRL3_8821C 0x002C
+#define REG_EFUSE_CTRL_8821C 0x0030
+#define REG_LDO_EFUSE_CTRL_8821C 0x0034
+#define REG_PWR_OPTION_CTRL_8821C 0x0038
+#define REG_CAL_TIMER_8821C 0x003C
+#define REG_ACLK_MON_8821C 0x003E
+#define REG_GPIO_MUXCFG_8821C 0x0040
+#define REG_GPIO_PIN_CTRL_8821C 0x0044
+#define REG_GPIO_INTM_8821C 0x0048
+#define REG_LED_CFG_8821C 0x004C
+#define REG_FSIMR_8821C 0x0050
+#define REG_FSISR_8821C 0x0054
+#define REG_HSIMR_8821C 0x0058
+#define REG_HSISR_8821C 0x005C
+#define REG_GPIO_EXT_CTRL_8821C 0x0060
+#define REG_PAD_CTRL1_8821C 0x0064
+#define REG_WL_BT_PWR_CTRL_8821C 0x0068
+#define REG_SDM_DEBUG_8821C 0x006C
+#define REG_SYS_SDIO_CTRL_8821C 0x0070
+#define REG_HCI_OPT_CTRL_8821C 0x0074
+#define REG_AFE_CTRL4_8821C 0x0078
+#define REG_LDO_SWR_CTRL_8821C 0x007C
+#define REG_MCUFW_CTRL_8821C 0x0080
+#define REG_MCU_TST_CFG_8821C 0x0084
+#define REG_HMEBOX_E0_E1_8821C 0x0088
+#define REG_HMEBOX_E2_E3_8821C 0x008C
+#define REG_WLLPS_CTRL_8821C 0x0090
+#define REG_AFE_CTRL5_8821C 0x0094
+#define REG_GPIO_DEBOUNCE_CTRL_8821C 0x0098
+#define REG_RPWM2_8821C 0x009C
+#define REG_SYSON_FSM_MON_8821C 0x00A0
+#define REG_AFE_CTRL6_8821C 0x00A4
+#define REG_PMC_DBG_CTRL1_8821C 0x00A8
+#define REG_AFE_CTRL7_8821C 0x00AC
+#define REG_HIMR0_8821C 0x00B0
+#define REG_HISR0_8821C 0x00B4
+#define REG_HIMR1_8821C 0x00B8
+#define REG_HISR1_8821C 0x00BC
+#define REG_DBG_PORT_SEL_8821C 0x00C0
+#define REG_PAD_CTRL2_8821C 0x00C4
+#define REG_PMC_DBG_CTRL2_8821C 0x00CC
+#define REG_BIST_CTRL_8821C 0x00D0
+#define REG_BIST_RPT_8821C 0x00D4
+#define REG_MEM_CTRL_8821C 0x00D8
+#define REG_AFE_CTRL8_8821C 0x00DC
+#define REG_USB_SIE_INTF_8821C 0x00E0
+#define REG_PCIE_MIO_INTF_8821C 0x00E4
+#define REG_PCIE_MIO_INTD_8821C 0x00E8
+#define REG_WLRF1_8821C 0x00EC
+#define REG_SYS_CFG1_8821C 0x00F0
+#define REG_SYS_STATUS1_8821C 0x00F4
+#define REG_SYS_STATUS2_8821C 0x00F8
+#define REG_SYS_CFG2_8821C 0x00FC
+#define REG_SYS_CFG3_8821C 0x1000
+#define REG_SYS_CFG5_8821C 0x1070
+#define REG_CPU_DMEM_CON_8821C 0x1080
+#define REG_BOOT_REASON_8821C 0x1088
+#define REG_NFCPAD_CTRL_8821C 0x10A8
+#define REG_HIMR2_8821C 0x10B0
+#define REG_HISR2_8821C 0x10B4
+#define REG_HIMR3_8821C 0x10B8
+#define REG_HISR3_8821C 0x10BC
+#define REG_SW_MDIO_8821C 0x10C0
+#define REG_H2C_PKT_READADDR_8821C 0x10D0
+#define REG_H2C_PKT_WRITEADDR_8821C 0x10D4
+#define REG_MEM_PWR_CRTL_8821C 0x10D8
+#define REG_FW_DBG6_8821C 0x10F8
+#define REG_FW_DBG7_8821C 0x10FC
+#define REG_CR_8821C 0x0100
+#define REG_PG_SIZE_8821C 0x0104
+#define REG_PKT_BUFF_ACCESS_CTRL_8821C 0x0106
+#define REG_TSF_CLK_STATE_8821C 0x0108
+#define REG_TXDMA_PQ_MAP_8821C 0x010C
+#define REG_TRXFF_BNDY_8821C 0x0114
+#define REG_PTA_I2C_MBOX_8821C 0x0118
+#define REG_RXFF_BNDY_8821C 0x011C
+#define REG_FE1IMR_8821C 0x0120
+#define REG_FE1ISR_8821C 0x0124
+#define REG_CPWM_8821C 0x012C
+#define REG_FWIMR_8821C 0x0130
+#define REG_FWISR_8821C 0x0134
+#define REG_FTIMR_8821C 0x0138
+#define REG_FTISR_8821C 0x013C
+#define REG_PKTBUF_DBG_CTRL_8821C 0x0140
+#define REG_PKTBUF_DBG_DATA_L_8821C 0x0144
+#define REG_PKTBUF_DBG_DATA_H_8821C 0x0148
+#define REG_CPWM2_8821C 0x014C
+#define REG_TC0_CTRL_8821C 0x0150
+#define REG_TC1_CTRL_8821C 0x0154
+#define REG_TC2_CTRL_8821C 0x0158
+#define REG_TC3_CTRL_8821C 0x015C
+#define REG_TC4_CTRL_8821C 0x0160
+#define REG_TCUNIT_BASE_8821C 0x0164
+#define REG_TC5_CTRL_8821C 0x0168
+#define REG_TC6_CTRL_8821C 0x016C
+#define REG_MBIST_DRF_FAIL_8821C 0x0170
+#define REG_MBIST_START_PAUSE_8821C 0x0174
+#define REG_MBIST_DONE_8821C 0x0178
+#define REG_MBIST_READ_BIST_RPT_8821C 0x017C
+#define REG_AES_DECRPT_DATA_8821C 0x0180
+#define REG_AES_DECRPT_CFG_8821C 0x0184
+#define REG_TMETER_8821C 0x0190
+#define REG_OSC_32K_CTRL_8821C 0x0194
+#define REG_32K_CAL_REG1_8821C 0x0198
+#define REG_C2HEVT_8821C 0x01A0
+#define REG_C2HEVT_1_8821C 0x01A4
+#define REG_C2HEVT_2_8821C 0x01A8
+#define REG_C2HEVT_3_8821C 0x01AC
+#define REG_SW_DEFINED_PAGE1_8821C 0x01B8
+#define REG_SW_DEFINED_PAGE2_8821C 0x01BC
+#define REG_MCUTST_I_8821C 0x01C0
+#define REG_MCUTST_II_8821C 0x01C4
+#define REG_FMETHR_8821C 0x01C8
+#define REG_HMETFR_8821C 0x01CC
+#define REG_HMEBOX0_8821C 0x01D0
+#define REG_HMEBOX1_8821C 0x01D4
+#define REG_HMEBOX2_8821C 0x01D8
+#define REG_HMEBOX3_8821C 0x01DC
+#define REG_BB_ACCESS_CTRL_8821C 0x01E8
+#define REG_BB_ACCESS_DATA_8821C 0x01EC
+#define REG_HMEBOX_E0_8821C 0x01F0
+#define REG_HMEBOX_E1_8821C 0x01F4
+#define REG_HMEBOX_E2_8821C 0x01F8
+#define REG_HMEBOX_E3_8821C 0x01FC
+#define REG_CR_EXT_8821C 0x1100
+#define REG_FWFF_8821C 0x1114
+#define REG_RXFF_PTR_V1_8821C 0x1118
+#define REG_RXFF_WTR_V1_8821C 0x111C
+#define REG_FE2IMR_8821C 0x1120
+#define REG_FE2ISR_8821C 0x1124
+#define REG_FE3IMR_8821C 0x1128
+#define REG_FE3ISR_8821C 0x112C
+#define REG_FE4IMR_8821C 0x1130
+#define REG_FE4ISR_8821C 0x1134
+#define REG_FT1IMR_8821C 0x1138
+#define REG_FT1ISR_8821C 0x113C
+#define REG_SPWR0_8821C 0x1140
+#define REG_SPWR1_8821C 0x1144
+#define REG_SPWR2_8821C 0x1148
+#define REG_SPWR3_8821C 0x114C
+#define REG_POWSEQ_8821C 0x1150
+#define REG_TC7_CTRL_V1_8821C 0x1158
+#define REG_TC8_CTRL_V1_8821C 0x115C
+#define REG_RX_BCN_TBTT_ITVL0_8821C 0x1160
+#define REG_RX_BCN_TBTT_ITVL1_8821C 0x1164
+#define REG_IO_WRAP_ERR_FLAG_8821C 0x1170
+#define REG_SPEED_SENSOR_8821C 0x1180
+#define REG_SPEED_SENSOR1_8821C 0x1184
+#define REG_SPEED_SENSOR2_8821C 0x1188
+#define REG_SPEED_SENSOR3_8821C 0x118C
+#define REG_SPEED_SENSOR4_8821C 0x1190
+#define REG_SPEED_SENSOR5_8821C 0x1194
+#define REG_COUNTER_CTRL_8821C 0x11C4
+#define REG_COUNTER_THRESHOLD_8821C 0x11C8
+#define REG_COUNTER_SET_8821C 0x11CC
+#define REG_COUNTER_OVERFLOW_8821C 0x11D0
+#define REG_TXDMA_LEN_THRESHOLD_8821C 0x11D4
+#define REG_RXDMA_LEN_THRESHOLD_8821C 0x11D8
+#define REG_PCIE_EXEC_TIME_THRESHOLD_8821C 0x11DC
+#define REG_FT2IMR_8821C 0x11E0
+#define REG_FT2ISR_8821C 0x11E4
+#define REG_MSG2_8821C 0x11F0
+#define REG_MSG3_8821C 0x11F4
+#define REG_MSG4_8821C 0x11F8
+#define REG_MSG5_8821C 0x11FC
+#define REG_FIFOPAGE_CTRL_1_8821C 0x0200
+#define REG_FIFOPAGE_CTRL_2_8821C 0x0204
+#define REG_AUTO_LLT_V1_8821C 0x0208
+#define REG_TXDMA_OFFSET_CHK_8821C 0x020C
+#define REG_TXDMA_STATUS_8821C 0x0210
+#define REG_TX_DMA_DBG_8821C 0x0214
+#define REG_TQPNT1_8821C 0x0218
+#define REG_TQPNT2_8821C 0x021C
+#define REG_TQPNT3_8821C 0x0220
+#define REG_TQPNT4_8821C 0x0224
+#define REG_RQPN_CTRL_1_8821C 0x0228
+#define REG_RQPN_CTRL_2_8821C 0x022C
+#define REG_FIFOPAGE_INFO_1_8821C 0x0230
+#define REG_FIFOPAGE_INFO_2_8821C 0x0234
+#define REG_FIFOPAGE_INFO_3_8821C 0x0238
+#define REG_FIFOPAGE_INFO_4_8821C 0x023C
+#define REG_FIFOPAGE_INFO_5_8821C 0x0240
+#define REG_H2C_HEAD_8821C 0x0244
+#define REG_H2C_TAIL_8821C 0x0248
+#define REG_H2C_READ_ADDR_8821C 0x024C
+#define REG_H2C_WR_ADDR_8821C 0x0250
+#define REG_H2C_INFO_8821C 0x0254
+#define REG_RXDMA_AGG_PG_TH_8821C 0x0280
+#define REG_RXPKT_NUM_8821C 0x0284
+#define REG_RXDMA_STATUS_8821C 0x0288
+#define REG_RXDMA_DPR_8821C 0x028C
+#define REG_RXDMA_MODE_8821C 0x0290
+#define REG_C2H_PKT_8821C 0x0294
+#define REG_FWFF_C2H_8821C 0x0298
+#define REG_FWFF_CTRL_8821C 0x029C
+#define REG_FWFF_PKT_INFO_8821C 0x02A0
+#define REG_DDMA_CH0SA_8821C 0x1200
+#define REG_DDMA_CH0DA_8821C 0x1204
+#define REG_DDMA_CH0CTRL_8821C 0x1208
+#define REG_DDMA_CH1SA_8821C 0x1210
+#define REG_DDMA_CH1DA_8821C 0x1214
+#define REG_DDMA_CH1CTRL_8821C 0x1218
+#define REG_DDMA_CH2SA_8821C 0x1220
+#define REG_DDMA_CH2DA_8821C 0x1224
+#define REG_DDMA_CH2CTRL_8821C 0x1228
+#define REG_DDMA_CH3SA_8821C 0x1230
+#define REG_DDMA_CH3DA_8821C 0x1234
+#define REG_DDMA_CH3CTRL_8821C 0x1238
+#define REG_DDMA_CH4SA_8821C 0x1240
+#define REG_DDMA_CH4DA_8821C 0x1244
+#define REG_DDMA_CH4CTRL_8821C 0x1248
+#define REG_DDMA_CH5SA_8821C 0x1250
+#define REG_DDMA_CH5DA_8821C 0x1254
+#define REG_DDMA_CH5CTRL_8821C 0x1258
+#define REG_DDMA_INT_MSK_8821C 0x12E0
+#define REG_DDMA_CHSTATUS_8821C 0x12E8
+#define REG_DDMA_CHKSUM_8821C 0x12F0
+#define REG_DDMA_MONITOR_8821C 0x12FC
+#define REG_PCIE_CTRL_8821C 0x0300
+#define REG_INT_MIG_8821C 0x0304
+#define REG_BCNQ_TXBD_DESA_8821C 0x0308
+#define REG_MGQ_TXBD_DESA_8821C 0x0310
+#define REG_VOQ_TXBD_DESA_8821C 0x0318
+#define REG_VIQ_TXBD_DESA_8821C 0x0320
+#define REG_BEQ_TXBD_DESA_8821C 0x0328
+#define REG_BKQ_TXBD_DESA_8821C 0x0330
+#define REG_RXQ_RXBD_DESA_8821C 0x0338
+#define REG_HI0Q_TXBD_DESA_8821C 0x0340
+#define REG_HI1Q_TXBD_DESA_8821C 0x0348
+#define REG_HI2Q_TXBD_DESA_8821C 0x0350
+#define REG_HI3Q_TXBD_DESA_8821C 0x0358
+#define REG_HI4Q_TXBD_DESA_8821C 0x0360
+#define REG_HI5Q_TXBD_DESA_8821C 0x0368
+#define REG_HI6Q_TXBD_DESA_8821C 0x0370
+#define REG_HI7Q_TXBD_DESA_8821C 0x0378
+#define REG_MGQ_TXBD_NUM_8821C 0x0380
+#define REG_RX_RXBD_NUM_8821C 0x0382
+#define REG_VOQ_TXBD_NUM_8821C 0x0384
+#define REG_VIQ_TXBD_NUM_8821C 0x0386
+#define REG_BEQ_TXBD_NUM_8821C 0x0388
+#define REG_BKQ_TXBD_NUM_8821C 0x038A
+#define REG_HI0Q_TXBD_NUM_8821C 0x038C
+#define REG_HI1Q_TXBD_NUM_8821C 0x038E
+#define REG_HI2Q_TXBD_NUM_8821C 0x0390
+#define REG_HI3Q_TXBD_NUM_8821C 0x0392
+#define REG_HI4Q_TXBD_NUM_8821C 0x0394
+#define REG_HI5Q_TXBD_NUM_8821C 0x0396
+#define REG_HI6Q_TXBD_NUM_8821C 0x0398
+#define REG_HI7Q_TXBD_NUM_8821C 0x039A
+#define REG_TSFTIMER_HCI_8821C 0x039C
+#define REG_BD_RWPTR_CLR_8821C 0x039C
+#define REG_VOQ_TXBD_IDX_8821C 0x03A0
+#define REG_VIQ_TXBD_IDX_8821C 0x03A4
+#define REG_BEQ_TXBD_IDX_8821C 0x03A8
+#define REG_BKQ_TXBD_IDX_8821C 0x03AC
+#define REG_MGQ_TXBD_IDX_8821C 0x03B0
+#define REG_RXQ_RXBD_IDX_8821C 0x03B4
+#define REG_HI0Q_TXBD_IDX_8821C 0x03B8
+#define REG_HI1Q_TXBD_IDX_8821C 0x03BC
+#define REG_HI2Q_TXBD_IDX_8821C 0x03C0
+#define REG_HI3Q_TXBD_IDX_8821C 0x03C4
+#define REG_HI4Q_TXBD_IDX_8821C 0x03C8
+#define REG_HI5Q_TXBD_IDX_8821C 0x03CC
+#define REG_HI6Q_TXBD_IDX_8821C 0x03D0
+#define REG_HI7Q_TXBD_IDX_8821C 0x03D4
+#define REG_DBG_SEL_V1_8821C 0x03D8
+#define REG_PCIE_HRPWM1_V1_8821C 0x03D9
+#define REG_PCIE_HCPWM1_V1_8821C 0x03DA
+#define REG_PCIE_CTRL2_8821C 0x03DB
+#define REG_PCIE_HRPWM2_V1_8821C 0x03DC
+#define REG_PCIE_HCPWM2_V1_8821C 0x03DE
+#define REG_PCIE_H2C_MSG_V1_8821C 0x03E0
+#define REG_PCIE_C2H_MSG_V1_8821C 0x03E4
+#define REG_DBI_WDATA_V1_8821C 0x03E8
+#define REG_DBI_RDATA_V1_8821C 0x03EC
+#define REG_DBI_FLAG_V1_8821C 0x03F0
+#define REG_MDIO_V1_8821C 0x03F4
+#define REG_PCIE_MIX_CFG_8821C 0x03F8
+#define REG_HCI_MIX_CFG_8821C 0x03FC
+#define REG_STC_INT_CS_8821C 0x1300
+#define REG_ST_INT_CFG_8821C 0x1304
+#define REG_CMU_DLY_CTRL_8821C 0x1310
+#define REG_CMU_DLY_CFG_8821C 0x1314
+#define REG_H2CQ_TXBD_DESA_8821C 0x1320
+#define REG_H2CQ_TXBD_NUM_8821C 0x1328
+#define REG_H2CQ_TXBD_IDX_8821C 0x132C
+#define REG_H2CQ_CSR_8821C 0x1330
+#define REG_Q0_INFO_8821C 0x0400
+#define REG_Q1_INFO_8821C 0x0404
+#define REG_Q2_INFO_8821C 0x0408
+#define REG_Q3_INFO_8821C 0x040C
+#define REG_MGQ_INFO_8821C 0x0410
+#define REG_HIQ_INFO_8821C 0x0414
+#define REG_BCNQ_INFO_8821C 0x0418
+#define REG_TXPKT_EMPTY_8821C 0x041A
+#define REG_CPU_MGQ_INFO_8821C 0x041C
+#define REG_FWHW_TXQ_CTRL_8821C 0x0420
+#define REG_DATAFB_SEL_8821C 0x0423
+#define REG_BCNQ_BDNY_V1_8821C 0x0424
+#define REG_LIFETIME_EN_8821C 0x0426
+#define REG_SPEC_SIFS_8821C 0x0428
+#define REG_RETRY_LIMIT_8821C 0x042A
+#define REG_TXBF_CTRL_8821C 0x042C
+#define REG_DARFRC_8821C 0x0430
+#define REG_DARFRCH_8821C 0x0434
+#define REG_RARFRC_8821C 0x0438
+#define REG_RARFRCH_8821C 0x043C
+#define REG_RRSR_8821C 0x0440
+#define REG_ARFR0_8821C 0x0444
+#define REG_ARFRH0_8821C 0x0448
+#define REG_ARFR1_V1_8821C 0x044C
+#define REG_ARFRH1_V1_8821C 0x0450
+#define REG_CCK_CHECK_8821C 0x0454
+#define REG_AMPDU_MAX_TIME_V1_8821C 0x0455
+#define REG_BCNQ1_BDNY_V1_8821C 0x0456
+#define REG_AMPDU_MAX_LENGTH_8821C 0x0458
+#define REG_ACQ_STOP_8821C 0x045C
+#define REG_NDPA_RATE_8821C 0x045D
+#define REG_TX_HANG_CTRL_8821C 0x045E
+#define REG_NDPA_OPT_CTRL_8821C 0x045F
+#define REG_RD_RESP_PKT_TH_8821C 0x0463
+#define REG_CMDQ_INFO_8821C 0x0464
+#define REG_Q4_INFO_8821C 0x0468
+#define REG_Q5_INFO_8821C 0x046C
+#define REG_Q6_INFO_8821C 0x0470
+#define REG_Q7_INFO_8821C 0x0474
+#define REG_WMAC_LBK_BUF_HD_V1_8821C 0x0478
+#define REG_MGQ_BDNY_V1_8821C 0x047A
+#define REG_TXRPT_CTRL_8821C 0x047C
+#define REG_INIRTS_RATE_SEL_8821C 0x0480
+#define REG_BASIC_CFEND_RATE_8821C 0x0481
+#define REG_STBC_CFEND_RATE_8821C 0x0482
+#define REG_DATA_SC_8821C 0x0483
+#define REG_MACID_SLEEP3_8821C 0x0484
+#define REG_MACID_SLEEP1_8821C 0x0488
+#define REG_ARFR2_V1_8821C 0x048C
+#define REG_ARFRH2_V1_8821C 0x0490
+#define REG_ARFR3_V1_8821C 0x0494
+#define REG_ARFRH3_V1_8821C 0x0498
+#define REG_ARFR4_8821C 0x049C
+#define REG_ARFRH4_8821C 0x04A0
+#define REG_ARFR5_8821C 0x04A4
+#define REG_ARFRH5_8821C 0x04A8
+#define REG_TXRPT_START_OFFSET_8821C 0x04AC
+#define REG_POWER_STAGE1_8821C 0x04B4
+#define REG_POWER_STAGE2_8821C 0x04B8
+#define REG_SW_AMPDU_BURST_MODE_CTRL_8821C 0x04BC
+#define REG_PKT_LIFE_TIME_8821C 0x04C0
+#define REG_STBC_SETTING_8821C 0x04C4
+#define REG_STBC_SETTING2_8821C 0x04C5
+#define REG_QUEUE_CTRL_8821C 0x04C6
+#define REG_SINGLE_AMPDU_CTRL_8821C 0x04C7
+#define REG_PROT_MODE_CTRL_8821C 0x04C8
+#define REG_BAR_MODE_CTRL_8821C 0x04CC
+#define REG_RA_TRY_RATE_AGG_LMT_8821C 0x04CF
+#define REG_MACID_SLEEP2_8821C 0x04D0
+#define REG_MACID_SLEEP_8821C 0x04D4
+#define REG_HW_SEQ0_8821C 0x04D8
+#define REG_HW_SEQ1_8821C 0x04DA
+#define REG_HW_SEQ2_8821C 0x04DC
+#define REG_HW_SEQ3_8821C 0x04DE
+#define REG_NULL_PKT_STATUS_V1_8821C 0x04E0
+#define REG_PTCL_ERR_STATUS_8821C 0x04E2
+#define REG_NULL_PKT_STATUS_EXTEND_8821C 0x04E3
+#define REG_VIDEO_ENHANCEMENT_FUN_8821C 0x04E4
+#define REG_PRECNT_CTRL_8821C 0x04E5
+#define REG_BT_POLLUTE_PKT_CNT_8821C 0x04E8
+#define REG_PTCL_DBG_8821C 0x04EC
+#define REG_CPUMGQ_TIMER_CTRL2_8821C 0x04F4
+#define REG_DUMMY_PAGE4_V1_8821C 0x04FC
+#define REG_MOREDATA_8821C 0x04FE
+#define REG_Q0_Q1_INFO_8821C 0x1400
+#define REG_Q2_Q3_INFO_8821C 0x1404
+#define REG_Q4_Q5_INFO_8821C 0x1408
+#define REG_Q6_Q7_INFO_8821C 0x140C
+#define REG_MGQ_HIQ_INFO_8821C 0x1410
+#define REG_CMDQ_BCNQ_INFO_8821C 0x1414
+#define REG_USEREG_SETTING_8821C 0x1420
+#define REG_AESIV_SETTING_8821C 0x1424
+#define REG_BF0_TIME_SETTING_8821C 0x1428
+#define REG_BF1_TIME_SETTING_8821C 0x142C
+#define REG_BF_TIMEOUT_EN_8821C 0x1430
+#define REG_MACID_RELEASE0_8821C 0x1434
+#define REG_MACID_RELEASE1_8821C 0x1438
+#define REG_MACID_RELEASE2_8821C 0x143C
+#define REG_MACID_RELEASE3_8821C 0x1440
+#define REG_MACID_RELEASE_SETTING_8821C 0x1444
+#define REG_FAST_EDCA_VOVI_SETTING_8821C 0x1448
+#define REG_FAST_EDCA_BEBK_SETTING_8821C 0x144C
+#define REG_MACID_DROP0_8821C 0x1450
+#define REG_MACID_DROP1_8821C 0x1454
+#define REG_MACID_DROP2_8821C 0x1458
+#define REG_MACID_DROP3_8821C 0x145C
+#define REG_R_MACID_RELEASE_SUCCESS_0_8821C 0x1460
+#define REG_R_MACID_RELEASE_SUCCESS_1_8821C 0x1464
+#define REG_R_MACID_RELEASE_SUCCESS_2_8821C 0x1468
+#define REG_R_MACID_RELEASE_SUCCESS_3_8821C 0x146C
+#define REG_MGQ_FIFO_WRITE_POINTER_8821C 0x1470
+#define REG_MGQ_FIFO_READ_POINTER_8821C 0x1472
+#define REG_MGQ_FIFO_ENABLE_8821C 0x1472
+#define REG_MGQ_FIFO_RELEASE_INT_MASK_8821C 0x1474
+#define REG_MGQ_FIFO_RELEASE_INT_FLAG_8821C 0x1476
+#define REG_MGQ_FIFO_VALID_MAP_8821C 0x1478
+#define REG_MGQ_FIFO_LIFETIME_8821C 0x147A
+#define REG_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8821C 0x147C
+#define REG_SHCUT_SETTING_8821C 0x1480
+#define REG_SHCUT_LLC_ETH_TYPE0_8821C 0x1484
+#define REG_SHCUT_LLC_ETH_TYPE1_8821C 0x1488
+#define REG_SHCUT_LLC_OUI0_8821C 0x148C
+#define REG_SHCUT_LLC_OUI1_8821C 0x1490
+#define REG_SHCUT_LLC_OUI2_8821C 0x1494
+#define REG_MU_TX_CTL_8821C 0x14C0
+#define REG_MU_STA_GID_VLD_8821C 0x14C4
+#define REG_MU_STA_USER_POS_INFO_8821C 0x14C8
+#define REG_MU_STA_USER_POS_INFO_H_8821C 0x14CC
+#define REG_MU_TRX_DBG_CNT_8821C 0x14D0
+#define REG_EDCA_VO_PARAM_8821C 0x0500
+#define REG_EDCA_VI_PARAM_8821C 0x0504
+#define REG_EDCA_BE_PARAM_8821C 0x0508
+#define REG_EDCA_BK_PARAM_8821C 0x050C
+#define REG_BCNTCFG_8821C 0x0510
+#define REG_PIFS_8821C 0x0512
+#define REG_RDG_PIFS_8821C 0x0513
+#define REG_SIFS_8821C 0x0514
+#define REG_TSFTR_SYN_OFFSET_8821C 0x0518
+#define REG_AGGR_BREAK_TIME_8821C 0x051A
+#define REG_SLOT_8821C 0x051B
+#define REG_NOA_ON_ERLY_TIME_8821C 0x051C
+#define REG_NOA_OFF_ERLY_TIME_8821C 0x051D
+#define REG_TX_PTCL_CTRL_8821C 0x0520
+#define REG_TXPAUSE_8821C 0x0522
+#define REG_DIS_TXREQ_CLR_8821C 0x0523
+#define REG_RD_CTRL_8821C 0x0524
+#define REG_MBSSID_CTRL_8821C 0x0526
+#define REG_P2PPS_CTRL_8821C 0x0527
+#define REG_PKT_LIFETIME_CTRL_8821C 0x0528
+#define REG_P2PPS_SPEC_STATE_8821C 0x052B
+#define REG_BAR_TX_CTRL_8821C 0x0530
+#define REG_P2PON_DIS_TXTIME_8821C 0x0531
+#define REG_TBTT_PROHIBIT_8821C 0x0540
+#define REG_P2PPS_STATE_8821C 0x0543
+#define REG_RD_NAV_NXT_8821C 0x0544
+#define REG_NAV_PROT_LEN_8821C 0x0546
+#define REG_BCN_CTRL_8821C 0x0550
+#define REG_BCN_CTRL_CLINT0_8821C 0x0551
+#define REG_MBID_NUM_8821C 0x0552
+#define REG_DUAL_TSF_RST_8821C 0x0553
+#define REG_MBSSID_BCN_SPACE_8821C 0x0554
+#define REG_DRVERLYINT_8821C 0x0558
+#define REG_BCNDMATIM_8821C 0x0559
+#define REG_ATIMWND_8821C 0x055A
+#define REG_USTIME_TSF_8821C 0x055C
+#define REG_BCN_MAX_ERR_8821C 0x055D
+#define REG_RXTSF_OFFSET_CCK_8821C 0x055E
+#define REG_RXTSF_OFFSET_OFDM_8821C 0x055F
+#define REG_TSFTR_8821C 0x0560
+#define REG_TSFTR_1_8821C 0x0564
+#define REG_FREERUN_CNT_8821C 0x0568
+#define REG_FREERUN_CNT_1_8821C 0x056C
+#define REG_ATIMWND1_V1_8821C 0x0570
+#define REG_TBTT_PROHIBIT_INFRA_8821C 0x0571
+#define REG_CTWND_8821C 0x0572
+#define REG_BCNIVLCUNT_8821C 0x0573
+#define REG_BCNDROPCTRL_8821C 0x0574
+#define REG_HGQ_TIMEOUT_PERIOD_8821C 0x0575
+#define REG_TXCMD_TIMEOUT_PERIOD_8821C 0x0576
+#define REG_MISC_CTRL_8821C 0x0577
+#define REG_BCN_CTRL_CLINT1_8821C 0x0578
+#define REG_BCN_CTRL_CLINT2_8821C 0x0579
+#define REG_BCN_CTRL_CLINT3_8821C 0x057A
+#define REG_EXTEND_CTRL_8821C 0x057B
+#define REG_P2PPS1_SPEC_STATE_8821C 0x057C
+#define REG_P2PPS1_STATE_8821C 0x057D
+#define REG_P2PPS2_SPEC_STATE_8821C 0x057E
+#define REG_P2PPS2_STATE_8821C 0x057F
+#define REG_PS_TIMER0_8821C 0x0580
+#define REG_PS_TIMER1_8821C 0x0584
+#define REG_PS_TIMER2_8821C 0x0588
+#define REG_TBTT_CTN_AREA_8821C 0x058C
+#define REG_FORCE_BCN_IFS_8821C 0x058E
+#define REG_TXOP_MIN_8821C 0x0590
+#define REG_PRE_BKF_TIME_8821C 0x0592
+#define REG_CROSS_TXOP_CTRL_8821C 0x0593
+#define REG_ATIMWND2_8821C 0x05A0
+#define REG_ATIMWND3_8821C 0x05A1
+#define REG_ATIMWND4_8821C 0x05A2
+#define REG_ATIMWND5_8821C 0x05A3
+#define REG_ATIMWND6_8821C 0x05A4
+#define REG_ATIMWND7_8821C 0x05A5
+#define REG_ATIMUGT_8821C 0x05A6
+#define REG_HIQ_NO_LMT_EN_8821C 0x05A7
+#define REG_DTIM_COUNTER_ROOT_8821C 0x05A8
+#define REG_DTIM_COUNTER_VAP1_8821C 0x05A9
+#define REG_DTIM_COUNTER_VAP2_8821C 0x05AA
+#define REG_DTIM_COUNTER_VAP3_8821C 0x05AB
+#define REG_DTIM_COUNTER_VAP4_8821C 0x05AC
+#define REG_DTIM_COUNTER_VAP5_8821C 0x05AD
+#define REG_DTIM_COUNTER_VAP6_8821C 0x05AE
+#define REG_DTIM_COUNTER_VAP7_8821C 0x05AF
+#define REG_DIS_ATIM_8821C 0x05B0
+#define REG_EARLY_128US_8821C 0x05B1
+#define REG_P2PPS1_CTRL_8821C 0x05B2
+#define REG_P2PPS2_CTRL_8821C 0x05B3
+#define REG_TIMER0_SRC_SEL_8821C 0x05B4
+#define REG_NOA_UNIT_SEL_8821C 0x05B5
+#define REG_P2POFF_DIS_TXTIME_8821C 0x05B7
+#define REG_MBSSID_BCN_SPACE2_8821C 0x05B8
+#define REG_MBSSID_BCN_SPACE3_8821C 0x05BC
+#define REG_ACMHWCTRL_8821C 0x05C0
+#define REG_ACMRSTCTRL_8821C 0x05C1
+#define REG_ACMAVG_8821C 0x05C2
+#define REG_VO_ADMTIME_8821C 0x05C4
+#define REG_VI_ADMTIME_8821C 0x05C6
+#define REG_BE_ADMTIME_8821C 0x05C8
+#define REG_EDCA_RANDOM_GEN_8821C 0x05CC
+#define REG_TXCMD_NOA_SEL_8821C 0x05CF
+#define REG_NOA_PARAM_8821C 0x05E0
+#define REG_NOA_PARAM_1_8821C 0x05E4
+#define REG_NOA_PARAM_2_8821C 0x05E8
+#define REG_NOA_PARAM_3_8821C 0x05EC
+#define REG_P2P_RST_8821C 0x05F0
+#define REG_SCHEDULER_RST_8821C 0x05F1
+#define REG_SCH_TXCMD_8821C 0x05F8
+#define REG_PAGE5_DUMMY_8821C 0x05FC
+#define REG_CPUMGQ_TX_TIMER_8821C 0x1500
+#define REG_PS_TIMER_A_8821C 0x1504
+#define REG_PS_TIMER_B_8821C 0x1508
+#define REG_PS_TIMER_C_8821C 0x150C
+#define REG_PS_TIMER_ABC_CPUMGQ_TIMER_CRTL_8821C 0x1510
+#define REG_CPUMGQ_TX_TIMER_EARLY_8821C 0x1514
+#define REG_PS_TIMER_A_EARLY_8821C 0x1515
+#define REG_PS_TIMER_B_EARLY_8821C 0x1516
+#define REG_PS_TIMER_C_EARLY_8821C 0x1517
+#define REG_CPUMGQ_PARAMETER_8821C 0x1518
+#define REG_WMAC_CR_8821C 0x0600
+#define REG_WMAC_FWPKT_CR_8821C 0x0601
+#define REG_FW_STS_FILTER_8821C 0x0602
+#define REG_TCR_8821C 0x0604
+#define REG_RCR_8821C 0x0608
+#define REG_RX_PKT_LIMIT_8821C 0x060C
+#define REG_RX_DLK_TIME_8821C 0x060D
+#define REG_RX_DRVINFO_SZ_8821C 0x060F
+#define REG_MACID_8821C 0x0610
+#define REG_MACID_H_8821C 0x0614
+#define REG_BSSID_8821C 0x0618
+#define REG_BSSID_H_8821C 0x061C
+#define REG_MAR_8821C 0x0620
+#define REG_MAR_H_8821C 0x0624
+#define REG_MBIDCAMCFG_1_8821C 0x0628
+#define REG_MBIDCAMCFG_2_8821C 0x062C
+#define REG_WMAC_TCR_TSFT_OFS_8821C 0x0630
+#define REG_UDF_THSD_8821C 0x0632
+#define REG_ZLD_NUM_8821C 0x0633
+#define REG_STMP_THSD_8821C 0x0634
+#define REG_WMAC_TXTIMEOUT_8821C 0x0635
+#define REG_MCU_TEST_2_V1_8821C 0x0636
+#define REG_USTIME_EDCA_8821C 0x0638
+#define REG_ACKTO_CCK_8821C 0x0639
+#define REG_MAC_SPEC_SIFS_8821C 0x063A
+#define REG_RESP_SIFS_CCK_8821C 0x063C
+#define REG_RESP_SIFS_OFDM_8821C 0x063E
+#define REG_ACKTO_8821C 0x0640
+#define REG_CTS2TO_8821C 0x0641
+#define REG_EIFS_8821C 0x0642
+#define REG_RPFM_MAP0_8821C 0x0644
+#define REG_RPFM_MAP1_V1_8821C 0x0646
+#define REG_RPFM_CAM_CMD_8821C 0x0648
+#define REG_RPFM_CAM_RWD_8821C 0x064C
+#define REG_NAV_CTRL_8821C 0x0650
+#define REG_BACAMCMD_8821C 0x0654
+#define REG_BACAMCONTENT_8821C 0x0658
+#define REG_BACAMCONTENT_H_8821C 0x065C
+#define REG_LBDLY_8821C 0x0660
+#define REG_WMAC_BACAM_RPMEN_8821C 0x0661
+#define REG_TX_RX_8821C 0x0662
+#define REG_WMAC_BITMAP_CTL_8821C 0x0663
+#define REG_RXERR_RPT_8821C 0x0664
+#define REG_WMAC_TRXPTCL_CTL_8821C 0x0668
+#define REG_WMAC_TRXPTCL_CTL_H_8821C 0x066C
+#define REG_CAMCMD_8821C 0x0670
+#define REG_CAMWRITE_8821C 0x0674
+#define REG_CAMREAD_8821C 0x0678
+#define REG_CAMDBG_8821C 0x067C
+#define REG_SECCFG_8821C 0x0680
+#define REG_RXFILTER_CATEGORY_1_8821C 0x0682
+#define REG_RXFILTER_ACTION_1_8821C 0x0683
+#define REG_RXFILTER_CATEGORY_2_8821C 0x0684
+#define REG_RXFILTER_ACTION_2_8821C 0x0685
+#define REG_RXFILTER_CATEGORY_3_8821C 0x0686
+#define REG_RXFILTER_ACTION_3_8821C 0x0687
+#define REG_RXFLTMAP3_8821C 0x0688
+#define REG_RXFLTMAP4_8821C 0x068A
+#define REG_RXFLTMAP5_8821C 0x068C
+#define REG_RXFLTMAP6_8821C 0x068E
+#define REG_WOW_CTRL_8821C 0x0690
+#define REG_NAN_RX_TSF_FILTER_8821C 0x0691
+#define REG_PS_RX_INFO_8821C 0x0692
+#define REG_WMMPS_UAPSD_TID_8821C 0x0693
+#define REG_LPNAV_CTRL_8821C 0x0694
+#define REG_WKFMCAM_CMD_8821C 0x0698
+#define REG_WKFMCAM_RWD_8821C 0x069C
+#define REG_RXFLTMAP0_8821C 0x06A0
+#define REG_RXFLTMAP1_8821C 0x06A2
+#define REG_RXFLTMAP2_8821C 0x06A4
+#define REG_BCN_PSR_RPT_8821C 0x06A8
+#define REG_FLC_RPC_8821C 0x06AC
+#define REG_FLC_RPCT_8821C 0x06AD
+#define REG_FLC_PTS_8821C 0x06AE
+#define REG_FLC_TRPC_8821C 0x06AF
+#define REG_RXPKTMON_CTRL_8821C 0x06B0
+#define REG_STATE_MON_8821C 0x06B4
+#define REG_ERROR_MON_8821C 0x06B8
+#define REG_SEARCH_MACID_8821C 0x06BC
+#define REG_BT_COEX_TABLE_8821C 0x06C0
+#define REG_BT_COEX_TABLE2_8821C 0x06C4
+#define REG_BT_COEX_BREAK_TABLE_8821C 0x06C8
+#define REG_BT_COEX_TABLE_H_8821C 0x06CC
+#define REG_RXCMD_0_8821C 0x06D0
+#define REG_RXCMD_1_8821C 0x06D4
+#define REG_WMAC_RESP_TXINFO_8821C 0x06D8
+#define REG_BBPSF_CTRL_8821C 0x06DC
+#define REG_P2P_RX_BCN_NOA_8821C 0x06E0
+#define REG_ASSOCIATED_BFMER0_INFO_8821C 0x06E4
+#define REG_ASSOCIATED_BFMER0_INFO_H_8821C 0x06E8
+#define REG_ASSOCIATED_BFMER1_INFO_8821C 0x06EC
+#define REG_ASSOCIATED_BFMER1_INFO_H_8821C 0x06F0
+#define REG_TX_CSI_RPT_PARAM_BW20_8821C 0x06F4
+#define REG_TX_CSI_RPT_PARAM_BW40_8821C 0x06F8
+#define REG_BCN_PSR_RPT2_8821C 0x1600
+#define REG_BCN_PSR_RPT3_8821C 0x1604
+#define REG_BCN_PSR_RPT4_8821C 0x1608
+#define REG_A1_ADDR_MASK_8821C 0x160C
+#define REG_MACID2_8821C 0x1620
+#define REG_MACID2_H_8821C 0x1624
+#define REG_BSSID2_8821C 0x1628
+#define REG_BSSID2_H_8821C 0x162C
+#define REG_MACID3_8821C 0x1630
+#define REG_MACID3_H_8821C 0x1634
+#define REG_BSSID3_8821C 0x1638
+#define REG_BSSID3_H_8821C 0x163C
+#define REG_MACID4_8821C 0x1640
+#define REG_MACID4_H_8821C 0x1644
+#define REG_BSSID4_8821C 0x1648
+#define REG_BSSID4_H_8821C 0x164C
+#define REG_NOA_REPORT_8821C 0x1650
+#define REG_NOA_REPORT_1_8821C 0x1654
+#define REG_NOA_REPORT_2_8821C 0x1658
+#define REG_NOA_REPORT_3_8821C 0x165C
+#define REG_PWRBIT_SETTING_8821C 0x1660
+#define REG_MU_BF_OPTION_8821C 0x167C
+#define REG_WMAC_PAUSE_BB_CLR_TH_8821C 0x167D
+#define REG_WMAC_MU_ARB_8821C 0x167E
+#define REG_WMAC_MU_OPTION_8821C 0x167F
+#define REG_WMAC_MU_BF_CTL_8821C 0x1680
+#define REG_WMAC_MU_BFRPT_PARA_8821C 0x1682
+#define REG_WMAC_ASSOCIATED_MU_BFMEE2_8821C 0x1684
+#define REG_WMAC_ASSOCIATED_MU_BFMEE3_8821C 0x1686
+#define REG_WMAC_ASSOCIATED_MU_BFMEE4_8821C 0x1688
+#define REG_WMAC_ASSOCIATED_MU_BFMEE5_8821C 0x168A
+#define REG_WMAC_ASSOCIATED_MU_BFMEE6_8821C 0x168C
+#define REG_WMAC_ASSOCIATED_MU_BFMEE7_8821C 0x168E
+#define REG_WMAC_BB_STOP_RX_COUNTER_8821C 0x1690
+#define REG_WMAC_PLCP_MONITOR_8821C 0x1694
+#define REG_WMAC_PLCP_MONITOR_MUTX_8821C 0x1698
+#define REG_TRANSMIT_ADDRSS_0_8821C 0x16A0
+#define REG_TRANSMIT_ADDRSS_0_H_8821C 0x16A4
+#define REG_TRANSMIT_ADDRSS_1_8821C 0x16A8
+#define REG_TRANSMIT_ADDRSS_1_H_8821C 0x16AC
+#define REG_TRANSMIT_ADDRSS_2_8821C 0x16B0
+#define REG_TRANSMIT_ADDRSS_2_H_8821C 0x16B4
+#define REG_TRANSMIT_ADDRSS_3_8821C 0x16B8
+#define REG_TRANSMIT_ADDRSS_3_H_8821C 0x16BC
+#define REG_TRANSMIT_ADDRSS_4_8821C 0x16C0
+#define REG_TRANSMIT_ADDRSS_4_H_8821C 0x16C4
+#define REG_MACID1_8821C 0x0700
+#define REG_MACID1_1_8821C 0x0704
+#define REG_BSSID1_8821C 0x0708
+#define REG_BSSID1_1_8821C 0x070C
+#define REG_BCN_PSR_RPT1_8821C 0x0710
+#define REG_ASSOCIATED_BFMEE_SEL_8821C 0x0714
+#define REG_SND_PTCL_CTRL_8821C 0x0718
+#define REG_RX_CSI_RPT_INFO_8821C 0x071C
+#define REG_NS_ARP_CTRL_8821C 0x0720
+#define REG_NS_ARP_INFO_8821C 0x0724
+#define REG_BEAMFORMING_INFO_NSARP_V1_8821C 0x0728
+#define REG_BEAMFORMING_INFO_NSARP_8821C 0x072C
+#define REG_IPV6_8821C 0x0730
+#define REG_IPV6_1_8821C 0x0734
+#define REG_IPV6_2_8821C 0x0738
+#define REG_IPV6_3_8821C 0x073C
+#define REG_WMAC_RTX_CTX_SUBTYPE_CFG_8821C 0x0750
+#define REG_WMAC_SWAES_CFG_8821C 0x0760
+#define REG_BT_COEX_V2_8821C 0x0762
+#define REG_BT_COEX_8821C 0x0764
+#define REG_WLAN_ACT_MASK_CTRL_8821C 0x0768
+#define REG_WLAN_ACT_MASK_CTRL_1_8821C 0x076C
+#define REG_BT_COEX_ENHANCED_INTR_CTRL_8821C 0x076E
+#define REG_BT_ACT_STATISTICS_8821C 0x0770
+#define REG_BT_ACT_STATISTICS_1_8821C 0x0774
+#define REG_BT_STATISTICS_CONTROL_REGISTER_8821C 0x0778
+#define REG_BT_STATUS_REPORT_REGISTER_8821C 0x077C
+#define REG_BT_INTERRUPT_CONTROL_REGISTER_8821C 0x0780
+#define REG_WLAN_REPORT_TIME_OUT_CONTROL_REGISTER_8821C 0x0784
+#define REG_BT_ISOLATION_TABLE_REGISTER_REGISTER_8821C 0x0785
+#define REG_BT_ISOLATION_TABLE_REGISTER_REGISTER_1_8821C 0x0788
+#define REG_BT_ISOLATION_TABLE_REGISTER_REGISTER_2_8821C 0x078C
+#define REG_BT_INTERRUPT_STATUS_REGISTER_8821C 0x078F
+#define REG_BT_TDMA_TIME_REGISTER_8821C 0x0790
+#define REG_BT_ACT_REGISTER_8821C 0x0794
+#define REG_OBFF_CTRL_BASIC_8821C 0x0798
+#define REG_OBFF_CTRL2_TIMER_8821C 0x079C
+#define REG_LTR_CTRL_BASIC_8821C 0x07A0
+#define REG_LTR_CTRL2_TIMER_THRESHOLD_8821C 0x07A4
+#define REG_LTR_IDLE_LATENCY_V1_8821C 0x07A8
+#define REG_LTR_ACTIVE_LATENCY_V1_8821C 0x07AC
+#define REG_ANTENNA_TRAINING_CONTROL_REGISTER_8821C 0x07B0
+#define REG_ANTENNA_TRAINING_CONTROL_REGISTER_1_8821C 0x07B4
+#define REG_WMAC_PKTCNT_RWD_8821C 0x07B8
+#define REG_WMAC_PKTCNT_CTRL_8821C 0x07BC
+#define REG_IQ_DUMP_8821C 0x07C0
+#define REG_IQ_DUMP_1_8821C 0x07C4
+#define REG_IQ_DUMP_2_8821C 0x07C8
+#define REG_WMAC_FTM_CTL_8821C 0x07CC
+#define REG_WMAC_IQ_MDPK_FUNC_8821C 0x07CE
+#define REG_WMAC_OPTION_FUNCTION_8821C 0x07D0
+#define REG_WMAC_OPTION_FUNCTION_1_8821C 0x07D4
+#define REG_WMAC_OPTION_FUNCTION_2_8821C 0x07D8
+#define REG_RX_FILTER_FUNCTION_8821C 0x07DA
+#define REG_NDP_SIG_8821C 0x07E0
+#define REG_TXCMD_INFO_FOR_RSP_PKT_8821C 0x07E4
+#define REG_TXCMD_INFO_FOR_RSP_PKT_1_8821C 0x07E8
+#define REG_WSEC_OPTION_8821C 0x07EC
+#define REG_RTS_ADDRESS_0_8821C 0x07F0
+#define REG_RTS_ADDRESS_0_1_8821C 0x07F4
+#define REG_RTS_ADDRESS_1_8821C 0x07F8
+#define REG_RTS_ADDRESS_1_1_8821C 0x07FC
+#define REG_WL2LTECOEX_INDIRECT_ACCESS_CTRL_V1_8821C 0x1700
+#define REG_WL2LTECOEX_INDIRECT_ACCESS_WRITE_DATA_V1_8821C 0x1704
+#define REG_WL2LTECOEX_INDIRECT_ACCESS_READ_DATA_V1_8821C 0x1708
+#define REG_SDIO_TX_CTRL_8821C 0x10250000
+#define REG_SDIO_HIMR_8821C 0x10250014
+#define REG_SDIO_HISR_8821C 0x10250018
+#define REG_SDIO_RX_REQ_LEN_8821C 0x1025001C
+#define REG_SDIO_FREE_TXPG_SEQ_V1_8821C 0x1025001F
+#define REG_SDIO_FREE_TXPG_8821C 0x10250020
+#define REG_SDIO_FREE_TXPG2_8821C 0x10250024
+#define REG_SDIO_OQT_FREE_TXPG_V1_8821C 0x10250028
+#define REG_SDIO_HTSFR_INFO_8821C 0x10250030
+#define REG_SDIO_HCPWM1_V2_8821C 0x10250038
+#define REG_SDIO_HCPWM2_V2_8821C 0x1025003A
+#define REG_SDIO_INDIRECT_REG_CFG_8821C 0x10250040
+#define REG_SDIO_INDIRECT_REG_DATA_8821C 0x10250044
+#define REG_SDIO_H2C_8821C 0x10250060
+#define REG_SDIO_C2H_8821C 0x10250064
+#define REG_SDIO_HRPWM1_8821C 0x10250080
+#define REG_SDIO_HRPWM2_8821C 0x10250082
+#define REG_SDIO_HPS_CLKR_8821C 0x10250084
+#define REG_SDIO_BUS_CTRL_8821C 0x10250085
+#define REG_SDIO_HSUS_CTRL_8821C 0x10250086
+#define REG_SDIO_RESPONSE_TIMER_8821C 0x10250088
+#define REG_SDIO_CMD_CRC_8821C 0x1025008A
+#define REG_SDIO_HSISR_8821C 0x10250090
+#define REG_SDIO_ERR_RPT_8821C 0x102500C0
+#define REG_SDIO_CMD_ERRCNT_8821C 0x102500C2
+#define REG_SDIO_DATA_ERRCNT_8821C 0x102500C3
+#define REG_SDIO_CMD_ERR_CONTENT_8821C 0x102500C4
+#define REG_SDIO_CRC_ERR_IDX_8821C 0x102500C9
+#define REG_SDIO_DATA_CRC_8821C 0x102500CA
+#define REG_SDIO_DATA_REPLY_TIME_8821C 0x102500CB
+
+#endif
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/halmac/halmac_reg_8822b.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/halmac/halmac_reg_8822b.h
--- linux-5.6.3/3rdparty/rtl8821ce/hal/halmac/halmac_reg_8822b.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/halmac/halmac_reg_8822b.h	2020-04-10 16:35:06.816660067 +0300
@@ -0,0 +1,733 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ ******************************************************************************/
+
+#ifndef __INC_HALMAC_REG_8822B_H
+#define __INC_HALMAC_REG_8822B_H
+
+#define REG_SYS_ISO_CTRL_8822B 0x0000
+#define REG_SYS_FUNC_EN_8822B 0x0002
+#define REG_SYS_PW_CTRL_8822B 0x0004
+#define REG_SYS_CLK_CTRL_8822B 0x0008
+#define REG_SYS_EEPROM_CTRL_8822B 0x000A
+#define REG_EE_VPD_8822B 0x000C
+#define REG_SYS_SWR_CTRL1_8822B 0x0010
+#define REG_SYS_SWR_CTRL2_8822B 0x0014
+#define REG_SYS_SWR_CTRL3_8822B 0x0018
+#define REG_RSV_CTRL_8822B 0x001C
+#define REG_RF_CTRL_8822B 0x001F
+#define REG_AFE_LDO_CTRL_8822B 0x0020
+#define REG_AFE_CTRL1_8822B 0x0024
+#define REG_AFE_CTRL2_8822B 0x0028
+#define REG_AFE_CTRL3_8822B 0x002C
+#define REG_EFUSE_CTRL_8822B 0x0030
+#define REG_LDO_EFUSE_CTRL_8822B 0x0034
+#define REG_PWR_OPTION_CTRL_8822B 0x0038
+#define REG_CAL_TIMER_8822B 0x003C
+#define REG_ACLK_MON_8822B 0x003E
+#define REG_GPIO_MUXCFG_8822B 0x0040
+#define REG_GPIO_PIN_CTRL_8822B 0x0044
+#define REG_GPIO_INTM_8822B 0x0048
+#define REG_LED_CFG_8822B 0x004C
+#define REG_FSIMR_8822B 0x0050
+#define REG_FSISR_8822B 0x0054
+#define REG_HSIMR_8822B 0x0058
+#define REG_HSISR_8822B 0x005C
+#define REG_GPIO_EXT_CTRL_8822B 0x0060
+#define REG_PAD_CTRL1_8822B 0x0064
+#define REG_WL_BT_PWR_CTRL_8822B 0x0068
+#define REG_SDM_DEBUG_8822B 0x006C
+#define REG_SYS_SDIO_CTRL_8822B 0x0070
+#define REG_HCI_OPT_CTRL_8822B 0x0074
+#define REG_AFE_CTRL4_8822B 0x0078
+#define REG_LDO_SWR_CTRL_8822B 0x007C
+#define REG_MCUFW_CTRL_8822B 0x0080
+#define REG_MCU_TST_CFG_8822B 0x0084
+#define REG_HMEBOX_E0_E1_8822B 0x0088
+#define REG_HMEBOX_E2_E3_8822B 0x008C
+#define REG_WLLPS_CTRL_8822B 0x0090
+#define REG_AFE_CTRL5_8822B 0x0094
+#define REG_GPIO_DEBOUNCE_CTRL_8822B 0x0098
+#define REG_RPWM2_8822B 0x009C
+#define REG_SYSON_FSM_MON_8822B 0x00A0
+#define REG_AFE_CTRL6_8822B 0x00A4
+#define REG_PMC_DBG_CTRL1_8822B 0x00A8
+#define REG_AFE_CTRL7_8822B 0x00AC
+#define REG_HIMR0_8822B 0x00B0
+#define REG_HISR0_8822B 0x00B4
+#define REG_HIMR1_8822B 0x00B8
+#define REG_HISR1_8822B 0x00BC
+#define REG_DBG_PORT_SEL_8822B 0x00C0
+#define REG_PAD_CTRL2_8822B 0x00C4
+#define REG_PMC_DBG_CTRL2_8822B 0x00CC
+#define REG_BIST_CTRL_8822B 0x00D0
+#define REG_BIST_RPT_8822B 0x00D4
+#define REG_MEM_CTRL_8822B 0x00D8
+#define REG_AFE_CTRL8_8822B 0x00DC
+#define REG_USB_SIE_INTF_8822B 0x00E0
+#define REG_PCIE_MIO_INTF_8822B 0x00E4
+#define REG_PCIE_MIO_INTD_8822B 0x00E8
+#define REG_WLRF1_8822B 0x00EC
+#define REG_SYS_CFG1_8822B 0x00F0
+#define REG_SYS_STATUS1_8822B 0x00F4
+#define REG_SYS_STATUS2_8822B 0x00F8
+#define REG_SYS_CFG2_8822B 0x00FC
+#define REG_SYS_CFG3_8822B 0x1000
+#define REG_SYS_CFG4_8822B 0x1034
+#define REG_SYS_CFG5_8822B 0x1070
+#define REG_CPU_DMEM_CON_8822B 0x1080
+#define REG_BOOT_REASON_8822B 0x1088
+#define REG_NFCPAD_CTRL_8822B 0x10A8
+#define REG_HIMR2_8822B 0x10B0
+#define REG_HISR2_8822B 0x10B4
+#define REG_HIMR3_8822B 0x10B8
+#define REG_HISR3_8822B 0x10BC
+#define REG_SW_MDIO_8822B 0x10C0
+#define REG_SW_FLUSH_8822B 0x10C4
+#define REG_H2C_PKT_READADDR_8822B 0x10D0
+#define REG_H2C_PKT_WRITEADDR_8822B 0x10D4
+#define REG_MEM_PWR_CRTL_8822B 0x10D8
+#define REG_FW_DBG0_8822B 0x10E0
+#define REG_FW_DBG1_8822B 0x10E4
+#define REG_FW_DBG2_8822B 0x10E8
+#define REG_FW_DBG3_8822B 0x10EC
+#define REG_FW_DBG4_8822B 0x10F0
+#define REG_FW_DBG5_8822B 0x10F4
+#define REG_FW_DBG6_8822B 0x10F8
+#define REG_FW_DBG7_8822B 0x10FC
+#define REG_CR_8822B 0x0100
+#define REG_TSF_CLK_STATE_8822B 0x0108
+#define REG_TXDMA_PQ_MAP_8822B 0x010C
+#define REG_TRXFF_BNDY_8822B 0x0114
+#define REG_PTA_I2C_MBOX_8822B 0x0118
+#define REG_RXFF_BNDY_8822B 0x011C
+#define REG_FE1IMR_8822B 0x0120
+#define REG_FE1ISR_8822B 0x0124
+#define REG_CPWM_8822B 0x012C
+#define REG_FWIMR_8822B 0x0130
+#define REG_FWISR_8822B 0x0134
+#define REG_FTIMR_8822B 0x0138
+#define REG_FTISR_8822B 0x013C
+#define REG_PKTBUF_DBG_CTRL_8822B 0x0140
+#define REG_PKTBUF_DBG_DATA_L_8822B 0x0144
+#define REG_PKTBUF_DBG_DATA_H_8822B 0x0148
+#define REG_CPWM2_8822B 0x014C
+#define REG_TC0_CTRL_8822B 0x0150
+#define REG_TC1_CTRL_8822B 0x0154
+#define REG_TC2_CTRL_8822B 0x0158
+#define REG_TC3_CTRL_8822B 0x015C
+#define REG_TC4_CTRL_8822B 0x0160
+#define REG_TCUNIT_BASE_8822B 0x0164
+#define REG_TC5_CTRL_8822B 0x0168
+#define REG_TC6_CTRL_8822B 0x016C
+#define REG_MBIST_FAIL_8822B 0x0170
+#define REG_MBIST_START_PAUSE_8822B 0x0174
+#define REG_MBIST_DONE_8822B 0x0178
+#define REG_MBIST_FAIL_NRML_8822B 0x017C
+#define REG_AES_DECRPT_DATA_8822B 0x0180
+#define REG_AES_DECRPT_CFG_8822B 0x0184
+#define REG_TMETER_8822B 0x0190
+#define REG_OSC_32K_CTRL_8822B 0x0194
+#define REG_32K_CAL_REG1_8822B 0x0198
+#define REG_C2HEVT_8822B 0x01A0
+#define REG_C2HEVT_1_8822B 0x01A4
+#define REG_C2HEVT_2_8822B 0x01A8
+#define REG_C2HEVT_3_8822B 0x01AC
+#define REG_SW_DEFINED_PAGE1_8822B 0x01B8
+#define REG_MCUTST_I_8822B 0x01C0
+#define REG_MCUTST_II_8822B 0x01C4
+#define REG_FMETHR_8822B 0x01C8
+#define REG_HMETFR_8822B 0x01CC
+#define REG_HMEBOX0_8822B 0x01D0
+#define REG_HMEBOX1_8822B 0x01D4
+#define REG_HMEBOX2_8822B 0x01D8
+#define REG_HMEBOX3_8822B 0x01DC
+#define REG_LLT_INIT_8822B 0x01E0
+#define REG_LLT_INIT_ADDR_8822B 0x01E4
+#define REG_BB_ACCESS_CTRL_8822B 0x01E8
+#define REG_BB_ACCESS_DATA_8822B 0x01EC
+#define REG_HMEBOX_E0_8822B 0x01F0
+#define REG_HMEBOX_E1_8822B 0x01F4
+#define REG_HMEBOX_E2_8822B 0x01F8
+#define REG_HMEBOX_E3_8822B 0x01FC
+#define REG_CR_EXT_8822B 0x1100
+#define REG_FWFF_8822B 0x1114
+#define REG_RXFF_PTR_V1_8822B 0x1118
+#define REG_RXFF_WTR_V1_8822B 0x111C
+#define REG_FE2IMR_8822B 0x1120
+#define REG_FE2ISR_8822B 0x1124
+#define REG_FE3IMR_8822B 0x1128
+#define REG_FE3ISR_8822B 0x112C
+#define REG_FE4IMR_8822B 0x1130
+#define REG_FE4ISR_8822B 0x1134
+#define REG_FT1IMR_8822B 0x1138
+#define REG_FT1ISR_8822B 0x113C
+#define REG_SPWR0_8822B 0x1140
+#define REG_SPWR1_8822B 0x1144
+#define REG_SPWR2_8822B 0x1148
+#define REG_SPWR3_8822B 0x114C
+#define REG_POWSEQ_8822B 0x1150
+#define REG_TC7_CTRL_V1_8822B 0x1158
+#define REG_TC8_CTRL_V1_8822B 0x115C
+#define REG_FT2IMR_8822B 0x11E0
+#define REG_FT2ISR_8822B 0x11E4
+#define REG_MSG2_8822B 0x11F0
+#define REG_MSG3_8822B 0x11F4
+#define REG_MSG4_8822B 0x11F8
+#define REG_MSG5_8822B 0x11FC
+#define REG_FIFOPAGE_CTRL_1_8822B 0x0200
+#define REG_FIFOPAGE_CTRL_2_8822B 0x0204
+#define REG_AUTO_LLT_V1_8822B 0x0208
+#define REG_TXDMA_OFFSET_CHK_8822B 0x020C
+#define REG_TXDMA_STATUS_8822B 0x0210
+#define REG_TX_DMA_DBG_8822B 0x0214
+#define REG_TQPNT1_8822B 0x0218
+#define REG_TQPNT2_8822B 0x021C
+#define REG_TQPNT3_8822B 0x0220
+#define REG_TQPNT4_8822B 0x0224
+#define REG_RQPN_CTRL_1_8822B 0x0228
+#define REG_RQPN_CTRL_2_8822B 0x022C
+#define REG_FIFOPAGE_INFO_1_8822B 0x0230
+#define REG_FIFOPAGE_INFO_2_8822B 0x0234
+#define REG_FIFOPAGE_INFO_3_8822B 0x0238
+#define REG_FIFOPAGE_INFO_4_8822B 0x023C
+#define REG_FIFOPAGE_INFO_5_8822B 0x0240
+#define REG_H2C_HEAD_8822B 0x0244
+#define REG_H2C_TAIL_8822B 0x0248
+#define REG_H2C_READ_ADDR_8822B 0x024C
+#define REG_H2C_WR_ADDR_8822B 0x0250
+#define REG_H2C_INFO_8822B 0x0254
+#define REG_RXDMA_AGG_PG_TH_8822B 0x0280
+#define REG_RXPKT_NUM_8822B 0x0284
+#define REG_RXDMA_STATUS_8822B 0x0288
+#define REG_RXDMA_DPR_8822B 0x028C
+#define REG_RXDMA_MODE_8822B 0x0290
+#define REG_C2H_PKT_8822B 0x0294
+#define REG_FWFF_C2H_8822B 0x0298
+#define REG_FWFF_CTRL_8822B 0x029C
+#define REG_FWFF_PKT_INFO_8822B 0x02A0
+#define REG_DDMA_CH0SA_8822B 0x1200
+#define REG_DDMA_CH0DA_8822B 0x1204
+#define REG_DDMA_CH0CTRL_8822B 0x1208
+#define REG_DDMA_CH1SA_8822B 0x1210
+#define REG_DDMA_CH1DA_8822B 0x1214
+#define REG_DDMA_CH1CTRL_8822B 0x1218
+#define REG_DDMA_CH2SA_8822B 0x1220
+#define REG_DDMA_CH2DA_8822B 0x1224
+#define REG_DDMA_CH2CTRL_8822B 0x1228
+#define REG_DDMA_CH3SA_8822B 0x1230
+#define REG_DDMA_CH3DA_8822B 0x1234
+#define REG_DDMA_CH3CTRL_8822B 0x1238
+#define REG_DDMA_CH4SA_8822B 0x1240
+#define REG_DDMA_CH4DA_8822B 0x1244
+#define REG_DDMA_CH4CTRL_8822B 0x1248
+#define REG_DDMA_CH5SA_8822B 0x1250
+#define REG_DDMA_CH5DA_8822B 0x1254
+#define REG_REG_DDMA_CH5CTRL_8822B 0x1258
+#define REG_DDMA_INT_MSK_8822B 0x12E0
+#define REG_DDMA_CHSTATUS_8822B 0x12E8
+#define REG_DDMA_CHKSUM_8822B 0x12F0
+#define REG_DDMA_MONITOR_8822B 0x12FC
+#define REG_PCIE_CTRL_8822B 0x0300
+#define REG_INT_MIG_8822B 0x0304
+#define REG_BCNQ_TXBD_DESA_8822B 0x0308
+#define REG_MGQ_TXBD_DESA_8822B 0x0310
+#define REG_VOQ_TXBD_DESA_8822B 0x0318
+#define REG_VIQ_TXBD_DESA_8822B 0x0320
+#define REG_BEQ_TXBD_DESA_8822B 0x0328
+#define REG_BKQ_TXBD_DESA_8822B 0x0330
+#define REG_RXQ_RXBD_DESA_8822B 0x0338
+#define REG_HI0Q_TXBD_DESA_8822B 0x0340
+#define REG_HI1Q_TXBD_DESA_8822B 0x0348
+#define REG_HI2Q_TXBD_DESA_8822B 0x0350
+#define REG_HI3Q_TXBD_DESA_8822B 0x0358
+#define REG_HI4Q_TXBD_DESA_8822B 0x0360
+#define REG_HI5Q_TXBD_DESA_8822B 0x0368
+#define REG_HI6Q_TXBD_DESA_8822B 0x0370
+#define REG_HI7Q_TXBD_DESA_8822B 0x0378
+#define REG_MGQ_TXBD_NUM_8822B 0x0380
+#define REG_RX_RXBD_NUM_8822B 0x0382
+#define REG_VOQ_TXBD_NUM_8822B 0x0384
+#define REG_VIQ_TXBD_NUM_8822B 0x0386
+#define REG_BEQ_TXBD_NUM_8822B 0x0388
+#define REG_BKQ_TXBD_NUM_8822B 0x038A
+#define REG_HI0Q_TXBD_NUM_8822B 0x038C
+#define REG_HI1Q_TXBD_NUM_8822B 0x038E
+#define REG_HI2Q_TXBD_NUM_8822B 0x0390
+#define REG_HI3Q_TXBD_NUM_8822B 0x0392
+#define REG_HI4Q_TXBD_NUM_8822B 0x0394
+#define REG_HI5Q_TXBD_NUM_8822B 0x0396
+#define REG_HI6Q_TXBD_NUM_8822B 0x0398
+#define REG_HI7Q_TXBD_NUM_8822B 0x039A
+#define REG_TSFTIMER_HCI_8822B 0x039C
+#define REG_BD_RWPTR_CLR_8822B 0x039C
+#define REG_VOQ_TXBD_IDX_8822B 0x03A0
+#define REG_VIQ_TXBD_IDX_8822B 0x03A4
+#define REG_BEQ_TXBD_IDX_8822B 0x03A8
+#define REG_BKQ_TXBD_IDX_8822B 0x03AC
+#define REG_MGQ_TXBD_IDX_8822B 0x03B0
+#define REG_RXQ_RXBD_IDX_8822B 0x03B4
+#define REG_HI0Q_TXBD_IDX_8822B 0x03B8
+#define REG_HI1Q_TXBD_IDX_8822B 0x03BC
+#define REG_HI2Q_TXBD_IDX_8822B 0x03C0
+#define REG_HI3Q_TXBD_IDX_8822B 0x03C4
+#define REG_HI4Q_TXBD_IDX_8822B 0x03C8
+#define REG_HI5Q_TXBD_IDX_8822B 0x03CC
+#define REG_HI6Q_TXBD_IDX_8822B 0x03D0
+#define REG_HI7Q_TXBD_IDX_8822B 0x03D4
+#define REG_DBG_SEL_V1_8822B 0x03D8
+#define REG_PCIE_HRPWM1_V1_8822B 0x03D9
+#define REG_PCIE_HCPWM1_V1_8822B 0x03DA
+#define REG_PCIE_CTRL2_8822B 0x03DB
+#define REG_PCIE_HRPWM2_V1_8822B 0x03DC
+#define REG_PCIE_HCPWM2_V1_8822B 0x03DE
+#define REG_PCIE_H2C_MSG_V1_8822B 0x03E0
+#define REG_PCIE_C2H_MSG_V1_8822B 0x03E4
+#define REG_DBI_WDATA_V1_8822B 0x03E8
+#define REG_DBI_RDATA_V1_8822B 0x03EC
+#define REG_DBI_FLAG_V1_8822B 0x03F0
+#define REG_MDIO_V1_8822B 0x03F4
+#define REG_PCIE_MIX_CFG_8822B 0x03F8
+#define REG_HCI_MIX_CFG_8822B 0x03FC
+#define REG_STC_INT_CS_8822B 0x1300
+#define REG_ST_INT_CFG_8822B 0x1304
+#define REG_CMU_DLY_CTRL_8822B 0x1310
+#define REG_CMU_DLY_CFG_8822B 0x1314
+#define REG_H2CQ_TXBD_DESA_8822B 0x1320
+#define REG_H2CQ_TXBD_NUM_8822B 0x1328
+#define REG_H2CQ_TXBD_IDX_8822B 0x132C
+#define REG_H2CQ_CSR_8822B 0x1330
+#define REG_CHANGE_PCIE_SPEED_8822B 0x1350
+#define REG_OLD_DEHANG_8822B 0x13F4
+#define REG_Q0_INFO_8822B 0x0400
+#define REG_Q1_INFO_8822B 0x0404
+#define REG_Q2_INFO_8822B 0x0408
+#define REG_Q3_INFO_8822B 0x040C
+#define REG_MGQ_INFO_8822B 0x0410
+#define REG_HIQ_INFO_8822B 0x0414
+#define REG_BCNQ_INFO_8822B 0x0418
+#define REG_TXPKT_EMPTY_8822B 0x041A
+#define REG_CPU_MGQ_INFO_8822B 0x041C
+#define REG_FWHW_TXQ_CTRL_8822B 0x0420
+#define REG_DATAFB_SEL_8822B 0x0423
+#define REG_BCNQ_BDNY_V1_8822B 0x0424
+#define REG_LIFETIME_EN_8822B 0x0426
+#define REG_SPEC_SIFS_8822B 0x0428
+#define REG_RETRY_LIMIT_8822B 0x042A
+#define REG_TXBF_CTRL_8822B 0x042C
+#define REG_DARFRC_8822B 0x0430
+#define REG_RARFRC_8822B 0x0438
+#define REG_RRSR_8822B 0x0440
+#define REG_ARFR0_8822B 0x0444
+#define REG_ARFR1_V1_8822B 0x044C
+#define REG_CCK_CHECK_8822B 0x0454
+#define REG_AMPDU_MAX_TIME_V1_8822B 0x0455
+#define REG_BCNQ1_BDNY_V1_8822B 0x0456
+#define REG_AMPDU_MAX_LENGTH_8822B 0x0458
+#define REG_ACQ_STOP_8822B 0x045C
+#define REG_NDPA_RATE_8822B 0x045D
+#define REG_TX_HANG_CTRL_8822B 0x045E
+#define REG_NDPA_OPT_CTRL_8822B 0x045F
+#define REG_RD_RESP_PKT_TH_8822B 0x0463
+#define REG_CMDQ_INFO_8822B 0x0464
+#define REG_Q4_INFO_8822B 0x0468
+#define REG_Q5_INFO_8822B 0x046C
+#define REG_Q6_INFO_8822B 0x0470
+#define REG_Q7_INFO_8822B 0x0474
+#define REG_WMAC_LBK_BUF_HD_V1_8822B 0x0478
+#define REG_MGQ_BDNY_V1_8822B 0x047A
+#define REG_TXRPT_CTRL_8822B 0x047C
+#define REG_INIRTS_RATE_SEL_8822B 0x0480
+#define REG_BASIC_CFEND_RATE_8822B 0x0481
+#define REG_STBC_CFEND_RATE_8822B 0x0482
+#define REG_DATA_SC_8822B 0x0483
+#define REG_MACID_SLEEP3_8822B 0x0484
+#define REG_MACID_SLEEP1_8822B 0x0488
+#define REG_ARFR2_V1_8822B 0x048C
+#define REG_ARFR3_V1_8822B 0x0494
+#define REG_ARFR4_8822B 0x049C
+#define REG_ARFR5_8822B 0x04A4
+#define REG_TXRPT_START_OFFSET_8822B 0x04AC
+#define REG_POWER_STAGE1_8822B 0x04B4
+#define REG_POWER_STAGE2_8822B 0x04B8
+#define REG_SW_AMPDU_BURST_MODE_CTRL_8822B 0x04BC
+#define REG_PKT_LIFE_TIME_8822B 0x04C0
+#define REG_STBC_SETTING_8822B 0x04C4
+#define REG_STBC_SETTING2_8822B 0x04C5
+#define REG_QUEUE_CTRL_8822B 0x04C6
+#define REG_SINGLE_AMPDU_CTRL_8822B 0x04C7
+#define REG_PROT_MODE_CTRL_8822B 0x04C8
+#define REG_BAR_MODE_CTRL_8822B 0x04CC
+#define REG_RA_TRY_RATE_AGG_LMT_8822B 0x04CF
+#define REG_MACID_SLEEP2_8822B 0x04D0
+#define REG_MACID_SLEEP_8822B 0x04D4
+#define REG_HW_SEQ0_8822B 0x04D8
+#define REG_HW_SEQ1_8822B 0x04DA
+#define REG_HW_SEQ2_8822B 0x04DC
+#define REG_HW_SEQ3_8822B 0x04DE
+#define REG_NULL_PKT_STATUS_V1_8822B 0x04E0
+#define REG_PTCL_ERR_STATUS_8822B 0x04E2
+#define REG_NULL_PKT_STATUS_EXTEND_8822B 0x04E3
+#define REG_VIDEO_ENHANCEMENT_FUN_8822B 0x04E4
+#define REG_BT_POLLUTE_PKT_CNT_8822B 0x04E8
+#define REG_PTCL_DBG_8822B 0x04EC
+#define REG_CPUMGQ_TIMER_CTRL2_8822B 0x04F4
+#define REG_DUMMY_PAGE4_V1_8822B 0x04FC
+#define REG_MOREDATA_8822B 0x04FE
+#define REG_Q0_Q1_INFO_8822B 0x1400
+#define REG_Q2_Q3_INFO_8822B 0x1404
+#define REG_Q4_Q5_INFO_8822B 0x1408
+#define REG_Q6_Q7_INFO_8822B 0x140C
+#define REG_MGQ_HIQ_INFO_8822B 0x1410
+#define REG_CMDQ_BCNQ_INFO_8822B 0x1414
+#define REG_USEREG_SETTING_8822B 0x1420
+#define REG_AESIV_SETTING_8822B 0x1424
+#define REG_BF0_TIME_SETTING_8822B 0x1428
+#define REG_BF1_TIME_SETTING_8822B 0x142C
+#define REG_BF_TIMEOUT_EN_8822B 0x1430
+#define REG_MACID_RELEASE0_8822B 0x1434
+#define REG_MACID_RELEASE1_8822B 0x1438
+#define REG_MACID_RELEASE2_8822B 0x143C
+#define REG_MACID_RELEASE3_8822B 0x1440
+#define REG_MACID_RELEASE_SETTING_8822B 0x1444
+#define REG_FAST_EDCA_VOVI_SETTING_8822B 0x1448
+#define REG_FAST_EDCA_BEBK_SETTING_8822B 0x144C
+#define REG_MACID_DROP0_8822B 0x1450
+#define REG_MACID_DROP1_8822B 0x1454
+#define REG_MACID_DROP2_8822B 0x1458
+#define REG_MACID_DROP3_8822B 0x145C
+#define REG_R_MACID_RELEASE_SUCCESS_0_8822B 0x1460
+#define REG_R_MACID_RELEASE_SUCCESS_1_8822B 0x1464
+#define REG_R_MACID_RELEASE_SUCCESS_2_8822B 0x1468
+#define REG_R_MACID_RELEASE_SUCCESS_3_8822B 0x146C
+#define REG_MGG_FIFO_CRTL_8822B 0x1470
+#define REG_MGG_FIFO_INT_8822B 0x1474
+#define REG_MGG_FIFO_LIFETIME_8822B 0x1478
+#define REG_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8822B 0x147C
+#define REG_SHCUT_SETTING_8822B 0x1480
+#define REG_SHCUT_LLC_ETH_TYPE0_8822B 0x1484
+#define REG_SHCUT_LLC_ETH_TYPE1_8822B 0x1488
+#define REG_SHCUT_LLC_OUI0_8822B 0x148C
+#define REG_SHCUT_LLC_OUI1_8822B 0x1490
+#define REG_SHCUT_LLC_OUI2_8822B 0x1494
+#define REG_SHCUT_LLC_OUI3_8822B 0x1498
+#define REG_MU_TX_CTL_8822B 0x14C0
+#define REG_MU_TX_CTL_8822B 0x14C0
+#define REG_MU_STA_GID_VLD_8822B 0x14C4
+#define REG_MU_STA_GID_VLD_8822B 0x14C4
+#define REG_MU_STA_USER_POS_INFO_8822B 0x14C8
+#define REG_MU_STA_USER_POS_INFO_8822B 0x14C8
+#define REG_MU_TRX_DBG_CNT_8822B 0x14D0
+#define REG_MU_TRX_DBG_CNT_8822B 0x14D0
+#define REG_EDCA_VO_PARAM_8822B 0x0500
+#define REG_EDCA_VI_PARAM_8822B 0x0504
+#define REG_EDCA_BE_PARAM_8822B 0x0508
+#define REG_EDCA_BK_PARAM_8822B 0x050C
+#define REG_BCNTCFG_8822B 0x0510
+#define REG_PIFS_8822B 0x0512
+#define REG_RDG_PIFS_8822B 0x0513
+#define REG_SIFS_8822B 0x0514
+#define REG_TSFTR_SYN_OFFSET_8822B 0x0518
+#define REG_AGGR_BREAK_TIME_8822B 0x051A
+#define REG_SLOT_8822B 0x051B
+#define REG_TX_PTCL_CTRL_8822B 0x0520
+#define REG_TXPAUSE_8822B 0x0522
+#define REG_DIS_TXREQ_CLR_8822B 0x0523
+#define REG_RD_CTRL_8822B 0x0524
+#define REG_MBSSID_CTRL_8822B 0x0526
+#define REG_P2PPS_CTRL_8822B 0x0527
+#define REG_PKT_LIFETIME_CTRL_8822B 0x0528
+#define REG_P2PPS_SPEC_STATE_8822B 0x052B
+#define REG_TXOP_LIMIT_CTRL_8822B 0x052C
+#define REG_BAR_TX_CTRL_8822B 0x0530
+#define REG_P2PON_DIS_TXTIME_8822B 0x0531
+#define REG_QUEUE_INCOL_THR_8822B 0x0538
+#define REG_QUEUE_INCOL_EN_8822B 0x053C
+#define REG_TBTT_PROHIBIT_8822B 0x0540
+#define REG_P2PPS_STATE_8822B 0x0543
+#define REG_RD_NAV_NXT_8822B 0x0544
+#define REG_NAV_PROT_LEN_8822B 0x0546
+#define REG_BCN_CTRL_8822B 0x0550
+#define REG_BCN_CTRL_CLINT0_8822B 0x0551
+#define REG_MBID_NUM_8822B 0x0552
+#define REG_DUAL_TSF_RST_8822B 0x0553
+#define REG_MBSSID_BCN_SPACE_8822B 0x0554
+#define REG_DRVERLYINT_8822B 0x0558
+#define REG_BCNDMATIM_8822B 0x0559
+#define REG_ATIMWND_8822B 0x055A
+#define REG_USTIME_TSF_8822B 0x055C
+#define REG_BCN_MAX_ERR_8822B 0x055D
+#define REG_RXTSF_OFFSET_CCK_8822B 0x055E
+#define REG_RXTSF_OFFSET_OFDM_8822B 0x055F
+#define REG_TSFTR_8822B 0x0560
+#define REG_FREERUN_CNT_8822B 0x0568
+#define REG_ATIMWND1_V1_8822B 0x0570
+#define REG_TBTT_PROHIBIT_INFRA_8822B 0x0571
+#define REG_CTWND_8822B 0x0572
+#define REG_BCNIVLCUNT_8822B 0x0573
+#define REG_BCNDROPCTRL_8822B 0x0574
+#define REG_HGQ_TIMEOUT_PERIOD_8822B 0x0575
+#define REG_TXCMD_TIMEOUT_PERIOD_8822B 0x0576
+#define REG_MISC_CTRL_8822B 0x0577
+#define REG_BCN_CTRL_CLINT1_8822B 0x0578
+#define REG_BCN_CTRL_CLINT2_8822B 0x0579
+#define REG_BCN_CTRL_CLINT3_8822B 0x057A
+#define REG_EXTEND_CTRL_8822B 0x057B
+#define REG_P2PPS1_SPEC_STATE_8822B 0x057C
+#define REG_P2PPS1_STATE_8822B 0x057D
+#define REG_P2PPS2_SPEC_STATE_8822B 0x057E
+#define REG_P2PPS2_STATE_8822B 0x057F
+#define REG_PS_TIMER0_8822B 0x0580
+#define REG_PS_TIMER1_8822B 0x0584
+#define REG_PS_TIMER2_8822B 0x0588
+#define REG_TBTT_CTN_AREA_8822B 0x058C
+#define REG_FORCE_BCN_IFS_8822B 0x058E
+#define REG_TXOP_MIN_8822B 0x0590
+#define REG_PRE_BKF_TIME_8822B 0x0592
+#define REG_CROSS_TXOP_CTRL_8822B 0x0593
+#define REG_ATIMWND2_8822B 0x05A0
+#define REG_ATIMWND3_8822B 0x05A1
+#define REG_ATIMWND4_8822B 0x05A2
+#define REG_ATIMWND5_8822B 0x05A3
+#define REG_ATIMWND6_8822B 0x05A4
+#define REG_ATIMWND7_8822B 0x05A5
+#define REG_ATIMUGT_8822B 0x05A6
+#define REG_HIQ_NO_LMT_EN_8822B 0x05A7
+#define REG_DTIM_COUNTER_ROOT_8822B 0x05A8
+#define REG_DTIM_COUNTER_VAP1_8822B 0x05A9
+#define REG_DTIM_COUNTER_VAP2_8822B 0x05AA
+#define REG_DTIM_COUNTER_VAP3_8822B 0x05AB
+#define REG_DTIM_COUNTER_VAP4_8822B 0x05AC
+#define REG_DTIM_COUNTER_VAP5_8822B 0x05AD
+#define REG_DTIM_COUNTER_VAP6_8822B 0x05AE
+#define REG_DTIM_COUNTER_VAP7_8822B 0x05AF
+#define REG_DIS_ATIM_8822B 0x05B0
+#define REG_EARLY_128US_8822B 0x05B1
+#define REG_P2PPS1_CTRL_8822B 0x05B2
+#define REG_P2PPS2_CTRL_8822B 0x05B3
+#define REG_TIMER0_SRC_SEL_8822B 0x05B4
+#define REG_NOA_UNIT_SEL_8822B 0x05B5
+#define REG_P2POFF_DIS_TXTIME_8822B 0x05B7
+#define REG_MBSSID_BCN_SPACE2_8822B 0x05B8
+#define REG_MBSSID_BCN_SPACE3_8822B 0x05BC
+#define REG_ACMHWCTRL_8822B 0x05C0
+#define REG_ACMRSTCTRL_8822B 0x05C1
+#define REG_ACMAVG_8822B 0x05C2
+#define REG_VO_ADMTIME_8822B 0x05C4
+#define REG_VI_ADMTIME_8822B 0x05C6
+#define REG_BE_ADMTIME_8822B 0x05C8
+#define REG_EDCA_RANDOM_GEN_8822B 0x05CC
+#define REG_TXCMD_NOA_SEL_8822B 0x05CF
+#define REG_NOA_PARAM_8822B 0x05E0
+#define REG_P2P_RST_8822B 0x05F0
+#define REG_SCHEDULER_RST_8822B 0x05F1
+#define REG_SCH_TXCMD_8822B 0x05F8
+#define REG_PAGE5_DUMMY_8822B 0x05FC
+#define REG_CPUMGQ_TX_TIMER_8822B 0x1500
+#define REG_PS_TIMER_A_8822B 0x1504
+#define REG_PS_TIMER_B_8822B 0x1508
+#define REG_PS_TIMER_C_8822B 0x150C
+#define REG_PS_TIMER_ABC_CPUMGQ_TIMER_CRTL_8822B 0x1510
+#define REG_CPUMGQ_TX_TIMER_EARLY_8822B 0x1514
+#define REG_PS_TIMER_A_EARLY_8822B 0x1515
+#define REG_PS_TIMER_B_EARLY_8822B 0x1516
+#define REG_PS_TIMER_C_EARLY_8822B 0x1517
+#define REG_CPUMGQ_PARAMETER_8822B 0x1518
+#define REG_WMAC_CR_8822B 0x0600
+#define REG_WMAC_FWPKT_CR_8822B 0x0601
+#define REG_BWOPMODE_8822B 0x0603
+#define REG_TCR_8822B 0x0604
+#define REG_RCR_8822B 0x0608
+#define REG_RX_PKT_LIMIT_8822B 0x060C
+#define REG_RX_DLK_TIME_8822B 0x060D
+#define REG_RX_DRVINFO_SZ_8822B 0x060F
+#define REG_MACID_8822B 0x0610
+#define REG_BSSID_8822B 0x0618
+#define REG_MAR_8822B 0x0620
+#define REG_MBIDCAMCFG_1_8822B 0x0628
+#define REG_MBIDCAMCFG_2_8822B 0x062C
+#define REG_WMAC_TCR_TSFT_OFS_8822B 0x0630
+#define REG_UDF_THSD_8822B 0x0632
+#define REG_ZLD_NUM_8822B 0x0633
+#define REG_STMP_THSD_8822B 0x0634
+#define REG_WMAC_TXTIMEOUT_8822B 0x0635
+#define REG_MCU_TEST_2_V1_8822B 0x0636
+#define REG_USTIME_EDCA_8822B 0x0638
+#define REG_MAC_SPEC_SIFS_8822B 0x063A
+#define REG_RESP_SIFS_CCK_8822B 0x063C
+#define REG_RESP_SIFS_OFDM_8822B 0x063E
+#define REG_ACKTO_8822B 0x0640
+#define REG_CTS2TO_8822B 0x0641
+#define REG_EIFS_8822B 0x0642
+#define REG_NAV_CTRL_8822B 0x0650
+#define REG_BACAMCMD_8822B 0x0654
+#define REG_BACAMCONTENT_8822B 0x0658
+#define REG_LBDLY_8822B 0x0660
+#define REG_WMAC_BACAM_RPMEN_8822B 0x0661
+#define REG_TX_RX_8822B 0x0662
+#define REG_WMAC_BITMAP_CTL_8822B 0x0663
+#define REG_RXERR_RPT_8822B 0x0664
+#define REG_WMAC_TRXPTCL_CTL_8822B 0x0668
+#define REG_CAMCMD_8822B 0x0670
+#define REG_CAMWRITE_8822B 0x0674
+#define REG_CAMREAD_8822B 0x0678
+#define REG_CAMDBG_8822B 0x067C
+#define REG_SECCFG_8822B 0x0680
+#define REG_RXFILTER_CATEGORY_1_8822B 0x0682
+#define REG_RXFILTER_ACTION_1_8822B 0x0683
+#define REG_RXFILTER_CATEGORY_2_8822B 0x0684
+#define REG_RXFILTER_ACTION_2_8822B 0x0685
+#define REG_RXFILTER_CATEGORY_3_8822B 0x0686
+#define REG_RXFILTER_ACTION_3_8822B 0x0687
+#define REG_RXFLTMAP3_8822B 0x0688
+#define REG_RXFLTMAP4_8822B 0x068A
+#define REG_RXFLTMAP5_8822B 0x068C
+#define REG_RXFLTMAP6_8822B 0x068E
+#define REG_WOW_CTRL_8822B 0x0690
+#define REG_NAN_RX_TSF_FILTER_8822B 0x0691
+#define REG_PS_RX_INFO_8822B 0x0692
+#define REG_WMMPS_UAPSD_TID_8822B 0x0693
+#define REG_LPNAV_CTRL_8822B 0x0694
+#define REG_WKFMCAM_CMD_8822B 0x0698
+#define REG_WKFMCAM_RWD_8822B 0x069C
+#define REG_RXFLTMAP0_8822B 0x06A0
+#define REG_RXFLTMAP1_8822B 0x06A2
+#define REG_RXFLTMAP2_8822B 0x06A4
+#define REG_BCN_PSR_RPT_8822B 0x06A8
+#define REG_FLC_RPC_8822B 0x06AC
+#define REG_FLC_RPCT_8822B 0x06AD
+#define REG_FLC_PTS_8822B 0x06AE
+#define REG_FLC_TRPC_8822B 0x06AF
+#define REG_RXPKTMON_CTRL_8822B 0x06B0
+#define REG_STATE_MON_8822B 0x06B4
+#define REG_ERROR_MON_8822B 0x06B8
+#define REG_SEARCH_MACID_8822B 0x06BC
+#define REG_BT_COEX_TABLE_8822B 0x06C0
+#define REG_RXCMD_0_8822B 0x06D0
+#define REG_RXCMD_1_8822B 0x06D4
+#define REG_WMAC_RESP_TXINFO_8822B 0x06D8
+#define REG_BBPSF_CTRL_8822B 0x06DC
+#define REG_P2P_RX_BCN_NOA_8822B 0x06E0
+#define REG_ASSOCIATED_BFMER0_INFO_8822B 0x06E4
+#define REG_ASSOCIATED_BFMER1_INFO_8822B 0x06EC
+#define REG_TX_CSI_RPT_PARAM_BW20_8822B 0x06F4
+#define REG_TX_CSI_RPT_PARAM_BW40_8822B 0x06F8
+#define REG_TX_CSI_RPT_PARAM_BW80_8822B 0x06FC
+#define REG_BCN_PSR_RPT2_8822B 0x1600
+#define REG_BCN_PSR_RPT3_8822B 0x1604
+#define REG_BCN_PSR_RPT4_8822B 0x1608
+#define REG_A1_ADDR_MASK_8822B 0x160C
+#define REG_MACID2_8822B 0x1620
+#define REG_BSSID2_8822B 0x1628
+#define REG_MACID3_8822B 0x1630
+#define REG_BSSID3_8822B 0x1638
+#define REG_MACID4_8822B 0x1640
+#define REG_BSSID4_8822B 0x1648
+#define REG_NOA_REPORT_8822B 0x1650
+#define REG_PWRBIT_SETTING_8822B 0x1660
+#define REG_WMAC_MU_BF_OPTION_8822B 0x167C
+#define REG_WMAC_MU_ARB_8822B 0x167E
+#define REG_WMAC_MU_OPTION_8822B 0x167F
+#define REG_WMAC_MU_BF_CTL_8822B 0x1680
+#define REG_WMAC_MU_BFRPT_PARA_8822B 0x1682
+#define REG_WMAC_ASSOCIATED_MU_BFMEE2_8822B 0x1684
+#define REG_WMAC_ASSOCIATED_MU_BFMEE3_8822B 0x1686
+#define REG_WMAC_ASSOCIATED_MU_BFMEE4_8822B 0x1688
+#define REG_WMAC_ASSOCIATED_MU_BFMEE5_8822B 0x168A
+#define REG_WMAC_ASSOCIATED_MU_BFMEE6_8822B 0x168C
+#define REG_WMAC_ASSOCIATED_MU_BFMEE7_8822B 0x168E
+#define REG_TRANSMIT_ADDRSS_0_8822B 0x16A0
+#define REG_TRANSMIT_ADDRSS_1_8822B 0x16A8
+#define REG_TRANSMIT_ADDRSS_2_8822B 0x16B0
+#define REG_TRANSMIT_ADDRSS_3_8822B 0x16B8
+#define REG_TRANSMIT_ADDRSS_4_8822B 0x16C0
+#define REG_MACID1_8822B 0x0700
+#define REG_BSSID1_8822B 0x0708
+#define REG_BCN_PSR_RPT1_8822B 0x0710
+#define REG_ASSOCIATED_BFMEE_SEL_8822B 0x0714
+#define REG_SND_PTCL_CTRL_8822B 0x0718
+#define REG_RX_CSI_RPT_INFO_8822B 0x071C
+#define REG_NS_ARP_CTRL_8822B 0x0720
+#define REG_NS_ARP_INFO_8822B 0x0724
+#define REG_BEAMFORMING_INFO_NSARP_V1_8822B 0x0728
+#define REG_BEAMFORMING_INFO_NSARP_8822B 0x072C
+#define REG_WMAC_RTX_CTX_SUBTYPE_CFG_8822B 0x0750
+#define REG_WMAC_SWAES_CFG_8822B 0x0760
+#define REG_BT_COEX_V2_8822B 0x0762
+#define REG_BT_COEX_8822B 0x0764
+#define REG_WLAN_ACT_MASK_CTRL_8822B 0x0768
+#define REG_BT_COEX_ENHANCED_INTR_CTRL_8822B 0x076E
+#define REG_BT_ACT_STATISTICS_8822B 0x0770
+#define REG_BT_STATISTICS_CONTROL_REGISTER_8822B 0x0778
+#define REG_BT_STATUS_REPORT_REGISTER_8822B 0x077C
+#define REG_BT_INTERRUPT_CONTROL_REGISTER_8822B 0x0780
+#define REG_WLAN_REPORT_TIME_OUT_CONTROL_REGISTER_8822B 0x0784
+#define REG_BT_ISOLATION_TABLE_REGISTER_REGISTER_8822B 0x0785
+#define REG_BT_INTERRUPT_STATUS_REGISTER_8822B 0x078F
+#define REG_BT_TDMA_TIME_REGISTER_8822B 0x0790
+#define REG_BT_ACT_REGISTER_8822B 0x0794
+#define REG_OBFF_CTRL_BASIC_8822B 0x0798
+#define REG_OBFF_CTRL2_TIMER_8822B 0x079C
+#define REG_LTR_CTRL_BASIC_8822B 0x07A0
+#define REG_LTR_CTRL2_TIMER_THRESHOLD_8822B 0x07A4
+#define REG_LTR_IDLE_LATENCY_V1_8822B 0x07A8
+#define REG_LTR_ACTIVE_LATENCY_V1_8822B 0x07AC
+#define REG_ANTENNA_TRAINING_CONTROL_REGISTER_8822B 0x07B0
+#define REG_WMAC_PKTCNT_RWD_8822B 0x07B8
+#define REG_WMAC_PKTCNT_CTRL_8822B 0x07BC
+#define REG_IQ_DUMP_8822B 0x07C0
+#define REG_WMAC_FTM_CTL_8822B 0x07CC
+#define REG_WMAC_IQ_MDPK_FUNC_8822B 0x07CE
+#define REG_WMAC_OPTION_FUNCTION_8822B 0x07D0
+#define REG_RX_FILTER_FUNCTION_8822B 0x07DA
+#define REG_NDP_SIG_8822B 0x07E0
+#define REG_TXCMD_INFO_FOR_RSP_PKT_8822B 0x07E4
+#define REG_RTS_ADDRESS_0_8822B 0x07F0
+#define REG_RTS_ADDRESS_1_8822B 0x07F8
+#define REG__RPFM_MAP1_8822B 0x07FE
+#define REG_WL2LTECOEX_INDIRECT_ACCESS_CTRL_V1_8822B 0x1700
+#define REG_WL2LTECOEX_INDIRECT_ACCESS_WRITE_DATA_V1_8822B 0x1704
+#define REG_WL2LTECOEX_INDIRECT_ACCESS_READ_DATA_V1_8822B 0x1708
+#define REG_SDIO_TX_CTRL_8822B 0x10250000
+#define REG_SDIO_HIMR_8822B 0x10250014
+#define REG_SDIO_HISR_8822B 0x10250018
+#define REG_SDIO_RX_REQ_LEN_8822B 0x1025001C
+#define REG_SDIO_FREE_TXPG_SEQ_V1_8822B 0x1025001F
+#define REG_SDIO_FREE_TXPG_8822B 0x10250020
+#define REG_SDIO_FREE_TXPG2_8822B 0x10250024
+#define REG_SDIO_OQT_FREE_TXPG_V1_8822B 0x10250028
+#define REG_SDIO_HTSFR_INFO_8822B 0x10250030
+#define REG_SDIO_HCPWM1_V2_8822B 0x10250038
+#define REG_SDIO_HCPWM2_V2_8822B 0x1025003A
+#define REG_SDIO_INDIRECT_REG_CFG_8822B 0x10250040
+#define REG_SDIO_INDIRECT_REG_DATA_8822B 0x10250044
+#define REG_SDIO_H2C_8822B 0x10250060
+#define REG_SDIO_C2H_8822B 0x10250064
+#define REG_SDIO_HRPWM1_8822B 0x10250080
+#define REG_SDIO_HRPWM2_8822B 0x10250082
+#define REG_SDIO_HPS_CLKR_8822B 0x10250084
+#define REG_SDIO_BUS_CTRL_8822B 0x10250085
+#define REG_SDIO_HSUS_CTRL_8822B 0x10250086
+#define REG_SDIO_RESPONSE_TIMER_8822B 0x10250088
+#define REG_SDIO_CMD_CRC_8822B 0x1025008A
+#define REG_SDIO_HSISR_8822B 0x10250090
+#define REG_SDIO_ERR_RPT_8822B 0x102500C0
+#define REG_SDIO_CMD_ERRCNT_8822B 0x102500C2
+#define REG_SDIO_DATA_ERRCNT_8822B 0x102500C3
+#define REG_SDIO_CMD_ERR_CONTENT_8822B 0x102500C4
+#define REG_SDIO_CRC_ERR_IDX_8822B 0x102500C9
+#define REG_SDIO_DATA_CRC_8822B 0x102500CA
+#define REG_SDIO_DATA_REPLY_TIME_8822B 0x102500CB
+
+#endif
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/halmac/halmac_reg_8822c.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/halmac/halmac_reg_8822c.h
--- linux-5.6.3/3rdparty/rtl8821ce/hal/halmac/halmac_reg_8822c.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/halmac/halmac_reg_8822c.h	2020-04-10 16:35:06.816660067 +0300
@@ -0,0 +1,877 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2017 - 2018 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ ******************************************************************************/
+
+#ifndef __INC_HALMAC_REG_8822C_H
+#define __INC_HALMAC_REG_8822C_H
+
+#define REG_SYS_ISO_CTRL_8822C 0x0000
+#define REG_SYS_FUNC_EN_8822C 0x0002
+#define REG_SYS_PW_CTRL_8822C 0x0004
+#define REG_SYS_CLK_CTRL_8822C 0x0008
+#define REG_SYS_EEPROM_CTRL_8822C 0x000A
+#define REG_EE_VPD_8822C 0x000C
+#define REG_SYS_SWR_CTRL1_8822C 0x0010
+#define REG_SYS_SWR_CTRL2_8822C 0x0014
+#define REG_SYS_SWR_CTRL3_8822C 0x0018
+#define REG_RSV_CTRL_8822C 0x001C
+#define REG_RF_CTRL_8822C 0x001F
+#define REG_AFE_LDO_CTRL_8822C 0x0020
+#define REG_AFE_CTRL1_8822C 0x0024
+#define REG_ANAPARSW_POW_MAC_8822C 0x0028
+#define REG_ANAPARLDO_POW_MAC_8822C 0x0029
+#define REG_ANAPAR_POW_MAC_8822C 0x002A
+#define REG_ANAPAR_POW_XTAL_8822C 0x002B
+#define REG_ANAPARLDO_MAC_8822C 0x002C
+#define REG_EFUSE_CTRL_8822C 0x0030
+#define REG_LDO_EFUSE_CTRL_8822C 0x0034
+#define REG_PWR_OPTION_CTRL_8822C 0x0038
+#define REG_CAL_TIMER_8822C 0x003C
+#define REG_ACLK_MON_8822C 0x003E
+#define REG_GPIO_MUXCFG_2_8822C 0x003F
+#define REG_GPIO_MUXCFG_8822C 0x0040
+#define REG_GPIO_PIN_CTRL_8822C 0x0044
+#define REG_GPIO_INTM_8822C 0x0048
+#define REG_LED_CFG_8822C 0x004C
+#define REG_FSIMR_8822C 0x0050
+#define REG_FSISR_8822C 0x0054
+#define REG_HSIMR_8822C 0x0058
+#define REG_HSISR_8822C 0x005C
+#define REG_GPIO_EXT_CTRL_8822C 0x0060
+#define REG_PAD_CTRL1_8822C 0x0064
+#define REG_WL_BT_PWR_CTRL_8822C 0x0068
+#define REG_SDM_DEBUG_8822C 0x006C
+#define REG_SYS_SDIO_CTRL_8822C 0x0070
+#define REG_HCI_OPT_CTRL_8822C 0x0074
+#define REG_HCI_BG_CTRL_8822C 0x0078
+#define REG_HCI_LDO_CTRL_8822C 0x007A
+#define REG_LDO_SWR_CTRL_8822C 0x007C
+#define REG_MCUFW_CTRL_8822C 0x0080
+#define REG_MCU_TST_CFG_8822C 0x0084
+#define REG_HMEBOX_E0_E1_8822C 0x0088
+#define REG_HMEBOX_E2_E3_8822C 0x008C
+#define REG_WLLPS_CTRL_8822C 0x0090
+#define REG_GPIO_DEBOUNCE_CTRL_8822C 0x0098
+#define REG_RPWM2_8822C 0x009C
+#define REG_SYSON_FSM_MON_8822C 0x00A0
+#define REG_PMC_DBG_CTRL1_8822C 0x00A8
+#define REG_HIMR0_8822C 0x00B0
+#define REG_HISR0_8822C 0x00B4
+#define REG_HIMR1_8822C 0x00B8
+#define REG_HISR1_8822C 0x00BC
+#define REG_DBG_PORT_SEL_8822C 0x00C0
+#define REG_PAD_CTRL2_8822C 0x00C4
+#define REG_PMC_DBG_CTRL2_8822C 0x00CC
+#define REG_BIST_CTRL_8822C 0x00D0
+#define REG_BIST_RPT_8822C 0x00D4
+#define REG_MEM_CTRL_8822C 0x00D8
+#define REG_USB_SIE_INTF_8822C 0x00E0
+#define REG_PCIE_MIO_INTF_8822C 0x00E4
+#define REG_PCIE_MIO_INTD_8822C 0x00E8
+#define REG_WLRF1_8822C 0x00EC
+#define REG_SYS_CFG1_8822C 0x00F0
+#define REG_SYS_STATUS1_8822C 0x00F4
+#define REG_SYS_STATUS2_8822C 0x00F8
+#define REG_SYS_CFG2_8822C 0x00FC
+#define REG_SYS_CFG3_8822C 0x1000
+#define REG_ANAPARSW_MAC_0_8822C 0x1010
+#define REG_ANAPARSW_MAC_1_8822C 0x1014
+#define REG_ANAPAR_MAC_0_8822C 0x1018
+#define REG_ANAPAR_MAC_1_8822C 0x101C
+#define REG_ANAPAR_MAC_2_8822C 0x1020
+#define REG_ANAPAR_XTAL_0_8822C 0x1040
+#define REG_ANAPAR_XTAL_1_8822C 0x1044
+#define REG_ANAPAR_XTAL_2_8822C 0x1048
+#define REG_ANAPAR_XTAL_3_8822C 0x104C
+#define REG_ANAPAR_XTAL_AACK_0_8822C 0x1054
+#define REG_ANAPAR_XTAL_AACK_1_8822C 0x1058
+#define REG_ANAPAR_XTAL_MODE_DECODER_8822C 0x1064
+#define REG_SYS_CFG5_8822C 0x1070
+#define REG_CPU_DMEM_CON_8822C 0x1080
+#define REG_BOOT_REASON_8822C 0x1088
+#define REG_HIMR2_8822C 0x10B0
+#define REG_HISR2_8822C 0x10B4
+#define REG_HIMR3_8822C 0x10B8
+#define REG_HISR3_8822C 0x10BC
+#define REG_SW_MDIO_8822C 0x10C0
+#define REG_H2C_PKT_READADDR_8822C 0x10D0
+#define REG_H2C_PKT_WRITEADDR_8822C 0x10D4
+#define REG_MEM_PWR_CRTL_8822C 0x10D8
+#define REG_FW_DBG6_8822C 0x10F8
+#define REG_FW_DBG7_8822C 0x10FC
+#define REG_CR_8822C 0x0100
+#define REG_PG_SIZE_8822C 0x0104
+#define REG_PKT_BUFF_ACCESS_CTRL_8822C 0x0106
+#define REG_TSF_CLK_STATE_8822C 0x0108
+#define REG_TXDMA_PQ_MAP_8822C 0x010C
+#define REG_TRXFF_BNDY_8822C 0x0114
+#define REG_PTA_I2C_MBOX_8822C 0x0118
+#define REG_RXFF_BNDY_8822C 0x011C
+#define REG_FE1IMR_8822C 0x0120
+#define REG_FE1ISR_8822C 0x0124
+#define REG_CPWM_8822C 0x012C
+#define REG_FWIMR_8822C 0x0130
+#define REG_FWISR_8822C 0x0134
+#define REG_FTIMR_8822C 0x0138
+#define REG_FTISR_8822C 0x013C
+#define REG_PKTBUF_DBG_CTRL_8822C 0x0140
+#define REG_PKTBUF_DBG_DATA_L_8822C 0x0144
+#define REG_PKTBUF_DBG_DATA_H_8822C 0x0148
+#define REG_CPWM2_8822C 0x014C
+#define REG_TC0_CTRL_8822C 0x0150
+#define REG_TC1_CTRL_8822C 0x0154
+#define REG_TC2_CTRL_8822C 0x0158
+#define REG_TC3_CTRL_8822C 0x015C
+#define REG_TC4_CTRL_8822C 0x0160
+#define REG_TCUNIT_BASE_8822C 0x0164
+#define REG_TC5_CTRL_8822C 0x0168
+#define REG_TC6_CTRL_8822C 0x016C
+#define REG_MBIST_DRF_FAIL_8822C 0x0170
+#define REG_MBIST_START_PAUSE_8822C 0x0174
+#define REG_MBIST_DONE_8822C 0x0178
+#define REG_MBIST_READ_BIST_RPT_8822C 0x017C
+#define REG_AES_DECRPT_DATA_8822C 0x0180
+#define REG_AES_DECRPT_CFG_8822C 0x0184
+#define REG_HIOE_CTRL_8822C 0x0188
+#define REG_HIOE_CFG_FILE_8822C 0x018C
+#define REG_TMETER_8822C 0x0190
+#define REG_OSC_32K_CTRL_8822C 0x0194
+#define REG_32K_CAL_REG1_8822C 0x0198
+#define REG_C2HEVT_8822C 0x01A0
+#define REG_C2HEVT_1_8822C 0x01A4
+#define REG_C2HEVT_2_8822C 0x01A8
+#define REG_C2HEVT_3_8822C 0x01AC
+#define REG_SW_DEFINED_PAGE1_8822C 0x01B8
+#define REG_SW_DEFINED_PAGE2_8822C 0x01BC
+#define REG_MCUTST_I_8822C 0x01C0
+#define REG_MCUTST_II_8822C 0x01C4
+#define REG_FMETHR_8822C 0x01C8
+#define REG_HMETFR_8822C 0x01CC
+#define REG_HMEBOX0_8822C 0x01D0
+#define REG_HMEBOX1_8822C 0x01D4
+#define REG_HMEBOX2_8822C 0x01D8
+#define REG_HMEBOX3_8822C 0x01DC
+#define REG_BB_ACCESS_CTRL_8822C 0x01E8
+#define REG_BB_ACCESS_DATA_8822C 0x01EC
+#define REG_HMEBOX_E0_8822C 0x01F0
+#define REG_HMEBOX_E1_8822C 0x01F4
+#define REG_HMEBOX_E2_8822C 0x01F8
+#define REG_HMEBOX_E3_8822C 0x01FC
+#define REG_CR_EXT_8822C 0x1100
+#define REG_FWFF_8822C 0x1114
+#define REG_RXFF_PTR_V1_8822C 0x1118
+#define REG_RXFF_WTR_V1_8822C 0x111C
+#define REG_FE2IMR_8822C 0x1120
+#define REG_FE2ISR_8822C 0x1124
+#define REG_FE3IMR_8822C 0x1128
+#define REG_FE3ISR_8822C 0x112C
+#define REG_FE4IMR_8822C 0x1130
+#define REG_FE4ISR_8822C 0x1134
+#define REG_FT1IMR_8822C 0x1138
+#define REG_FT1ISR_8822C 0x113C
+#define REG_SPWR0_8822C 0x1140
+#define REG_SPWR1_8822C 0x1144
+#define REG_SPWR2_8822C 0x1148
+#define REG_SPWR3_8822C 0x114C
+#define REG_POWSEQ_8822C 0x1150
+#define REG_TC7_CTRL_V1_8822C 0x1158
+#define REG_TC8_CTRL_V1_8822C 0x115C
+#define REG_RX_BCN_TBTT_ITVL0_8822C 0x1160
+#define REG_RX_BCN_TBTT_ITVL1_8822C 0x1164
+#define REG_IO_WRAP_ERR_FLAG_8822C 0x1170
+#define REG_SPEED_SENSOR_8822C 0x1180
+#define REG_SPEED_SENSOR1_8822C 0x1184
+#define REG_SPEED_SENSOR2_8822C 0x1188
+#define REG_SPEED_SENSOR3_8822C 0x118C
+#define REG_SPEED_SENSOR4_8822C 0x1190
+#define REG_SPEED_SENSOR5_8822C 0x1194
+#define REG_COUNTER_CTRL_8822C 0x11C4
+#define REG_COUNTER_THRESHOLD_8822C 0x11C8
+#define REG_COUNTER_SET_8822C 0x11CC
+#define REG_COUNTER_OVERFLOW_8822C 0x11D0
+#define REG_TXDMA_LEN_THRESHOLD_8822C 0x11D4
+#define REG_RXDMA_LEN_THRESHOLD_8822C 0x11D8
+#define REG_PCIE_EXEC_TIME_THRESHOLD_8822C 0x11DC
+#define REG_FT2IMR_8822C 0x11E0
+#define REG_FT2ISR_8822C 0x11E4
+#define REG_MSG2_8822C 0x11F0
+#define REG_MSG3_8822C 0x11F4
+#define REG_MSG4_8822C 0x11F8
+#define REG_MSG5_8822C 0x11FC
+#define REG_FIFOPAGE_CTRL_1_8822C 0x0200
+#define REG_FIFOPAGE_CTRL_2_8822C 0x0204
+#define REG_AUTO_LLT_V1_8822C 0x0208
+#define REG_TXDMA_OFFSET_CHK_8822C 0x020C
+#define REG_TXDMA_STATUS_8822C 0x0210
+#define REG_TX_DMA_DBG_8822C 0x0214
+#define REG_TQPNT1_8822C 0x0218
+#define REG_TQPNT2_8822C 0x021C
+#define REG_TQPNT3_8822C 0x0220
+#define REG_TQPNT4_8822C 0x0224
+#define REG_RQPN_CTRL_1_8822C 0x0228
+#define REG_RQPN_CTRL_2_8822C 0x022C
+#define REG_FIFOPAGE_INFO_1_8822C 0x0230
+#define REG_FIFOPAGE_INFO_2_8822C 0x0234
+#define REG_FIFOPAGE_INFO_3_8822C 0x0238
+#define REG_FIFOPAGE_INFO_4_8822C 0x023C
+#define REG_FIFOPAGE_INFO_5_8822C 0x0240
+#define REG_H2C_HEAD_8822C 0x0244
+#define REG_H2C_TAIL_8822C 0x0248
+#define REG_H2C_READ_ADDR_8822C 0x024C
+#define REG_H2C_WR_ADDR_8822C 0x0250
+#define REG_H2C_INFO_8822C 0x0254
+#define REG_PGSUB_CNT_8822C 0x026C
+#define REG_PGSUB_H_8822C 0x0270
+#define REG_PGSUB_N_8822C 0x0274
+#define REG_PGSUB_L_8822C 0x0278
+#define REG_PGSUB_E_8822C 0x027C
+#define REG_RXDMA_AGG_PG_TH_8822C 0x0280
+#define REG_RXPKT_NUM_8822C 0x0284
+#define REG_RXDMA_STATUS_8822C 0x0288
+#define REG_RXDMA_DPR_8822C 0x028C
+#define REG_RXDMA_MODE_8822C 0x0290
+#define REG_C2H_PKT_8822C 0x0294
+#define REG_FWFF_C2H_8822C 0x0298
+#define REG_FWFF_CTRL_8822C 0x029C
+#define REG_FWFF_PKT_INFO_8822C 0x02A0
+#define REG_RXPKTNUM_8822C 0x02B0
+#define REG_RXPKTNUM_TH_8822C 0x02B4
+#define REG_FW_MSG1_8822C 0x02E0
+#define REG_FW_MSG2_8822C 0x02E4
+#define REG_FW_MSG3_8822C 0x02E8
+#define REG_FW_MSG4_8822C 0x02EC
+#define REG_DDMA_CH0SA_8822C 0x1200
+#define REG_DDMA_CH0DA_8822C 0x1204
+#define REG_DDMA_CH0CTRL_8822C 0x1208
+#define REG_DDMA_CH1SA_8822C 0x1210
+#define REG_DDMA_CH1DA_8822C 0x1214
+#define REG_DDMA_CH1CTRL_8822C 0x1218
+#define REG_DDMA_CH2SA_8822C 0x1220
+#define REG_DDMA_CH2DA_8822C 0x1224
+#define REG_DDMA_CH2CTRL_8822C 0x1228
+#define REG_DDMA_CH3SA_8822C 0x1230
+#define REG_DDMA_CH3DA_8822C 0x1234
+#define REG_DDMA_CH3CTRL_8822C 0x1238
+#define REG_DDMA_CH4SA_8822C 0x1240
+#define REG_DDMA_CH4DA_8822C 0x1244
+#define REG_DDMA_CH4CTRL_8822C 0x1248
+#define REG_DDMA_CH5SA_8822C 0x1250
+#define REG_DDMA_CH5DA_8822C 0x1254
+#define REG_DDMA_CH5CTRL_8822C 0x1258
+#define REG_DDMA_INT_MSK_8822C 0x12E0
+#define REG_DDMA_CHSTATUS_8822C 0x12E8
+#define REG_DDMA_CHKSUM_8822C 0x12F0
+#define REG_DDMA_MONITOR_8822C 0x12FC
+#define REG_PCIE_CTRL_8822C 0x0300
+#define REG_INT_MIG_8822C 0x0304
+#define REG_BCNQ_TXBD_DESA_8822C 0x0308
+#define REG_MGQ_TXBD_DESA_8822C 0x0310
+#define REG_VOQ_TXBD_DESA_8822C 0x0318
+#define REG_VIQ_TXBD_DESA_8822C 0x0320
+#define REG_BEQ_TXBD_DESA_8822C 0x0328
+#define REG_BKQ_TXBD_DESA_8822C 0x0330
+#define REG_RXQ_RXBD_DESA_8822C 0x0338
+#define REG_HI0Q_TXBD_DESA_8822C 0x0340
+#define REG_HI1Q_TXBD_DESA_8822C 0x0348
+#define REG_HI2Q_TXBD_DESA_8822C 0x0350
+#define REG_HI3Q_TXBD_DESA_8822C 0x0358
+#define REG_HI4Q_TXBD_DESA_8822C 0x0360
+#define REG_HI5Q_TXBD_DESA_8822C 0x0368
+#define REG_HI6Q_TXBD_DESA_8822C 0x0370
+#define REG_HI7Q_TXBD_DESA_8822C 0x0378
+#define REG_MGQ_TXBD_NUM_8822C 0x0380
+#define REG_RX_RXBD_NUM_8822C 0x0382
+#define REG_VOQ_TXBD_NUM_8822C 0x0384
+#define REG_VIQ_TXBD_NUM_8822C 0x0386
+#define REG_BEQ_TXBD_NUM_8822C 0x0388
+#define REG_BKQ_TXBD_NUM_8822C 0x038A
+#define REG_HI0Q_TXBD_NUM_8822C 0x038C
+#define REG_HI1Q_TXBD_NUM_8822C 0x038E
+#define REG_HI2Q_TXBD_NUM_8822C 0x0390
+#define REG_HI3Q_TXBD_NUM_8822C 0x0392
+#define REG_HI4Q_TXBD_NUM_8822C 0x0394
+#define REG_HI5Q_TXBD_NUM_8822C 0x0396
+#define REG_HI6Q_TXBD_NUM_8822C 0x0398
+#define REG_HI7Q_TXBD_NUM_8822C 0x039A
+#define REG_TSFTIMER_HCI_8822C 0x039C
+#define REG_BD_RWPTR_CLR_8822C 0x039C
+#define REG_VOQ_TXBD_IDX_8822C 0x03A0
+#define REG_VIQ_TXBD_IDX_8822C 0x03A4
+#define REG_BEQ_TXBD_IDX_8822C 0x03A8
+#define REG_BKQ_TXBD_IDX_8822C 0x03AC
+#define REG_MGQ_TXBD_IDX_8822C 0x03B0
+#define REG_RXQ_RXBD_IDX_8822C 0x03B4
+#define REG_HI0Q_TXBD_IDX_8822C 0x03B8
+#define REG_HI1Q_TXBD_IDX_8822C 0x03BC
+#define REG_HI2Q_TXBD_IDX_8822C 0x03C0
+#define REG_HI3Q_TXBD_IDX_8822C 0x03C4
+#define REG_HI4Q_TXBD_IDX_8822C 0x03C8
+#define REG_HI5Q_TXBD_IDX_8822C 0x03CC
+#define REG_HI6Q_TXBD_IDX_8822C 0x03D0
+#define REG_HI7Q_TXBD_IDX_8822C 0x03D4
+#define REG_DBG_SEL_V1_8822C 0x03D8
+#define REG_PCIE_HRPWM1_V1_8822C 0x03D9
+#define REG_PCIE_HCPWM1_V1_8822C 0x03DA
+#define REG_PCIE_CTRL2_8822C 0x03DB
+#define REG_PCIE_HRPWM2_V1_8822C 0x03DC
+#define REG_PCIE_HCPWM2_V1_8822C 0x03DE
+#define REG_PCIE_H2C_MSG_V1_8822C 0x03E0
+#define REG_PCIE_C2H_MSG_V1_8822C 0x03E4
+#define REG_DBI_WDATA_V1_8822C 0x03E8
+#define REG_DBI_RDATA_V1_8822C 0x03EC
+#define REG_DBI_FLAG_V1_8822C 0x03F0
+#define REG_MDIO_V1_8822C 0x03F4
+#define REG_PCIE_MIX_CFG_8822C 0x03F8
+#define REG_HCI_MIX_CFG_8822C 0x03FC
+#define REG_STC_INT_CS_8822C 0x1300
+#define REG_ST_INT_CFG_8822C 0x1304
+#define REG_H2CQ_TXBD_DESA_8822C 0x1320
+#define REG_H2CQ_TXBD_NUM_8822C 0x1328
+#define REG_H2CQ_TXBD_IDX_8822C 0x132C
+#define REG_H2CQ_CSR_8822C 0x1330
+#define REG_CHANGE_PCIE_SPEED_8822C 0x1350
+#define REG_DEBUG_STATE1_8822C 0x1354
+#define REG_DEBUG_STATE2_8822C 0x1358
+#define REG_DEBUG_STATE3_8822C 0x135C
+#define REG_CHNL_DMA_CFG_V1_8822C 0x137C
+#define REG_PCIE_HISR0_V1_8822C 0x13B4
+#define REG_PCIE_HISR1_V1_8822C 0x13BC
+#define REG_PCIE_HISR2_V1_8822C 0x23B4
+#define REG_PCIE_HISR3_V1_8822C 0x23BC
+#define REG_Q0_INFO_8822C 0x0400
+#define REG_Q1_INFO_8822C 0x0404
+#define REG_Q2_INFO_8822C 0x0408
+#define REG_Q3_INFO_8822C 0x040C
+#define REG_MGQ_INFO_8822C 0x0410
+#define REG_HIQ_INFO_8822C 0x0414
+#define REG_BCNQ_INFO_8822C 0x0418
+#define REG_TXPKT_EMPTY_8822C 0x041A
+#define REG_CPU_MGQ_INFO_8822C 0x041C
+#define REG_FWHW_TXQ_CTRL_8822C 0x0420
+#define REG_DATAFB_SEL_8822C 0x0423
+#define REG_BCNQ_BDNY_V1_8822C 0x0424
+#define REG_LIFETIME_EN_8822C 0x0426
+#define REG_SPEC_SIFS_8822C 0x0428
+#define REG_RETRY_LIMIT_8822C 0x042A
+#define REG_TXBF_CTRL_8822C 0x042C
+#define REG_DARFRC_8822C 0x0430
+#define REG_DARFRCH_8822C 0x0434
+#define REG_RARFRC_8822C 0x0438
+#define REG_RARFRCH_8822C 0x043C
+#define REG_RRSR_8822C 0x0440
+#define REG_ARFR0_8822C 0x0444
+#define REG_ARFRH0_8822C 0x0448
+#define REG_ARFR1_V1_8822C 0x044C
+#define REG_ARFRH1_V1_8822C 0x0450
+#define REG_CCK_CHECK_8822C 0x0454
+#define REG_AMPDU_MAX_TIME_V1_8822C 0x0455
+#define REG_BCNQ1_BDNY_V1_8822C 0x0456
+#define REG_AMPDU_MAX_LENGTH_HT_8822C 0x0458
+#define REG_ACQ_STOP_8822C 0x045C
+#define REG_NDPA_RATE_8822C 0x045D
+#define REG_TX_HANG_CTRL_8822C 0x045E
+#define REG_NDPA_OPT_CTRL_8822C 0x045F
+#define REG_AMPDU_MAX_LENGTH_VHT_8822C 0x0460
+#define REG_RD_RESP_PKT_TH_8822C 0x0463
+#define REG_CMDQ_INFO_8822C 0x0464
+#define REG_Q4_INFO_8822C 0x0468
+#define REG_Q5_INFO_8822C 0x046C
+#define REG_Q6_INFO_8822C 0x0470
+#define REG_Q7_INFO_8822C 0x0474
+#define REG_WMAC_LBK_BUF_HD_V1_8822C 0x0478
+#define REG_MGQ_BDNY_V1_8822C 0x047A
+#define REG_TXRPT_CTRL_8822C 0x047C
+#define REG_INIRTS_RATE_SEL_8822C 0x0480
+#define REG_BASIC_CFEND_RATE_8822C 0x0481
+#define REG_STBC_CFEND_RATE_8822C 0x0482
+#define REG_DATA_SC_8822C 0x0483
+#define REG_MACID_SLEEP3_8822C 0x0484
+#define REG_MACID_SLEEP1_8822C 0x0488
+#define REG_ARFR2_V1_8822C 0x048C
+#define REG_ARFRH2_V1_8822C 0x0490
+#define REG_ARFR3_V1_8822C 0x0494
+#define REG_ARFRH3_V1_8822C 0x0498
+#define REG_ARFR4_8822C 0x049C
+#define REG_ARFRH4_8822C 0x04A0
+#define REG_ARFR5_8822C 0x04A4
+#define REG_ARFRH5_8822C 0x04A8
+#define REG_TXRPT_START_OFFSET_8822C 0x04AC
+#define REG_POWER_STAGE1_8822C 0x04B4
+#define REG_POWER_STAGE2_8822C 0x04B8
+#define REG_SW_AMPDU_BURST_MODE_CTRL_8822C 0x04BC
+#define REG_PKT_LIFE_TIME_8822C 0x04C0
+#define REG_STBC_SETTING_8822C 0x04C4
+#define REG_STBC_SETTING2_8822C 0x04C5
+#define REG_QUEUE_CTRL_8822C 0x04C6
+#define REG_SINGLE_AMPDU_CTRL_8822C 0x04C7
+#define REG_PROT_MODE_CTRL_8822C 0x04C8
+#define REG_BAR_MODE_CTRL_8822C 0x04CC
+#define REG_RA_TRY_RATE_AGG_LMT_8822C 0x04CF
+#define REG_MACID_SLEEP2_8822C 0x04D0
+#define REG_MACID_SLEEP_8822C 0x04D4
+#define REG_HW_SEQ0_8822C 0x04D8
+#define REG_HW_SEQ1_8822C 0x04DA
+#define REG_HW_SEQ2_8822C 0x04DC
+#define REG_HW_SEQ3_8822C 0x04DE
+#define REG_NULL_PKT_STATUS_V1_8822C 0x04E0
+#define REG_PTCL_ERR_STATUS_8822C 0x04E2
+#define REG_NULL_PKT_STATUS_EXTEND_8822C 0x04E3
+#define REG_HQMGQ_DROP_8822C 0x04E4
+#define REG_PRECNT_CTRL_8822C 0x04E5
+#define REG_BT_POLLUTE_PKT_CNT_8822C 0x04E8
+#define REG_PTCL_DBG_8822C 0x04EC
+#define REG_CPUMGQ_TIMER_CTRL2_8822C 0x04F4
+#define REG_DUMMY_PAGE4_V1_8822C 0x04FC
+#define REG_MOREDATA_8822C 0x04FE
+#define REG_Q0_Q1_INFO_8822C 0x1400
+#define REG_Q2_Q3_INFO_8822C 0x1404
+#define REG_Q4_Q5_INFO_8822C 0x1408
+#define REG_Q6_Q7_INFO_8822C 0x140C
+#define REG_MGQ_HIQ_INFO_8822C 0x1410
+#define REG_CMDQ_BCNQ_INFO_8822C 0x1414
+#define REG_LOOPBACK_OPTION_8822C 0x1420
+#define REG_AESIV_SETTING_8822C 0x1424
+#define REG_BF0_TIME_SETTING_8822C 0x1428
+#define REG_BF1_TIME_SETTING_8822C 0x142C
+#define REG_BF_TIMEOUT_EN_8822C 0x1430
+#define REG_MACID_RELEASE0_8822C 0x1434
+#define REG_MACID_RELEASE1_8822C 0x1438
+#define REG_MACID_RELEASE2_8822C 0x143C
+#define REG_MACID_RELEASE3_8822C 0x1440
+#define REG_MACID_RELEASE_SETTING_8822C 0x1444
+#define REG_FAST_EDCA_VOVI_SETTING_8822C 0x1448
+#define REG_FAST_EDCA_BEBK_SETTING_8822C 0x144C
+#define REG_MACID_DROP0_8822C 0x1450
+#define REG_MACID_DROP1_8822C 0x1454
+#define REG_MACID_DROP2_8822C 0x1458
+#define REG_MACID_DROP3_8822C 0x145C
+#define REG_R_MACID_RELEASE_SUCCESS_0_8822C 0x1460
+#define REG_R_MACID_RELEASE_SUCCESS_1_8822C 0x1464
+#define REG_R_MACID_RELEASE_SUCCESS_2_8822C 0x1468
+#define REG_R_MACID_RELEASE_SUCCESS_3_8822C 0x146C
+#define REG_MGQ_FIFO_WRITE_POINTER_8822C 0x1470
+#define REG_MGQ_FIFO_READ_POINTER_8822C 0x1472
+#define REG_MGQ_FIFO_ENABLE_8822C 0x1472
+#define REG_MGQ_FIFO_RELEASE_INT_MASK_8822C 0x1474
+#define REG_MGQ_FIFO_RELEASE_INT_FLAG_8822C 0x1476
+#define REG_MGQ_FIFO_VALID_MAP_8822C 0x1478
+#define REG_MGQ_FIFO_LIFETIME_8822C 0x147A
+#define REG_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8822C 0x147C
+#define REG_SHCUT_SETTING_8822C 0x1480
+#define REG_SHCUT_LLC_ETH_TYPE0_8822C 0x1484
+#define REG_SHCUT_LLC_ETH_TYPE1_8822C 0x1488
+#define REG_SHCUT_LLC_OUI0_8822C 0x148C
+#define REG_SHCUT_LLC_OUI1_8822C 0x1490
+#define REG_SHCUT_LLC_OUI2_8822C 0x1494
+#define REG_MU_TX_CTL_8822C 0x14C0
+#define REG_MU_STA_GID_VLD_8822C 0x14C4
+#define REG_MU_STA_USER_POS_INFO_8822C 0x14C8
+#define REG_MU_STA_USER_POS_INFO_H_8822C 0x14CC
+#define REG_CHNL_INFO_CTRL_8822C 0x14D0
+#define REG_CHNL_IDLE_TIME_8822C 0x14D4
+#define REG_CHNL_BUSY_TIME_8822C 0x14D8
+#define REG_MU_TRX_DBG_CNT_V1_8822C 0x14DC
+#define REG_EDCA_VO_PARAM_8822C 0x0500
+#define REG_EDCA_VI_PARAM_8822C 0x0504
+#define REG_EDCA_BE_PARAM_8822C 0x0508
+#define REG_EDCA_BK_PARAM_8822C 0x050C
+#define REG_BCNTCFG_8822C 0x0510
+#define REG_PIFS_8822C 0x0512
+#define REG_RDG_PIFS_8822C 0x0513
+#define REG_SIFS_8822C 0x0514
+#define REG_TSFTR_SYN_OFFSET_8822C 0x0518
+#define REG_AGGR_BREAK_TIME_8822C 0x051A
+#define REG_SLOT_8822C 0x051B
+#define REG_NOA_ON_ERLY_TIME_8822C 0x051C
+#define REG_NOA_OFF_ERLY_TIME_8822C 0x051D
+#define REG_TX_PTCL_CTRL_8822C 0x0520
+#define REG_TXPAUSE_8822C 0x0522
+#define REG_DIS_TXREQ_CLR_8822C 0x0523
+#define REG_RD_CTRL_8822C 0x0524
+#define REG_MBSSID_CTRL_8822C 0x0526
+#define REG_P2PPS_CTRL_8822C 0x0527
+#define REG_PKT_LIFETIME_CTRL_8822C 0x0528
+#define REG_P2PPS_SPEC_STATE_8822C 0x052B
+#define REG_TXOP_LIMIT_CTRL_8822C 0x052C
+#define REG_BAR_TX_CTRL_8822C 0x0530
+#define REG_P2PON_DIS_TXTIME_8822C 0x0531
+#define REG_CCA_TXEN_CNT_8822C 0x0534
+#define REG_MAX_INTER_COLLISION_8822C 0x0538
+#define REG_MAX_INTER_COLLISION_CNT_8822C 0x053C
+#define REG_TBTT_PROHIBIT_8822C 0x0540
+#define REG_P2PPS_STATE_8822C 0x0543
+#define REG_RD_NAV_NXT_8822C 0x0544
+#define REG_NAV_PROT_LEN_8822C 0x0546
+#define REG_FTM_PTT_8822C 0x0548
+#define REG_FTM_TSF_8822C 0x054C
+#define REG_BCN_CTRL_8822C 0x0550
+#define REG_BCN_CTRL_CLINT0_8822C 0x0551
+#define REG_MBID_NUM_8822C 0x0552
+#define REG_DUAL_TSF_RST_8822C 0x0553
+#define REG_MBSSID_BCN_SPACE_8822C 0x0554
+#define REG_DRVERLYINT_8822C 0x0558
+#define REG_BCNDMATIM_8822C 0x0559
+#define REG_ATIMWND_8822C 0x055A
+#define REG_USTIME_TSF_8822C 0x055C
+#define REG_BCN_MAX_ERR_8822C 0x055D
+#define REG_RXTSF_OFFSET_CCK_8822C 0x055E
+#define REG_RXTSF_OFFSET_OFDM_8822C 0x055F
+#define REG_TSFTR_8822C 0x0560
+#define REG_TSFTR_1_8822C 0x0564
+#define REG_FREERUN_CNT_8822C 0x0568
+#define REG_FREERUN_CNT_1_8822C 0x056C
+#define REG_ATIMWND1_V1_8822C 0x0570
+#define REG_TBTT_PROHIBIT_INFRA_8822C 0x0571
+#define REG_CTWND_8822C 0x0572
+#define REG_BCNIVLCUNT_8822C 0x0573
+#define REG_BCNDROPCTRL_8822C 0x0574
+#define REG_HGQ_TIMEOUT_PERIOD_8822C 0x0575
+#define REG_TXCMD_TIMEOUT_PERIOD_8822C 0x0576
+#define REG_MISC_CTRL_8822C 0x0577
+#define REG_BCN_CTRL_CLINT1_8822C 0x0578
+#define REG_BCN_CTRL_CLINT2_8822C 0x0579
+#define REG_BCN_CTRL_CLINT3_8822C 0x057A
+#define REG_EXTEND_CTRL_8822C 0x057B
+#define REG_P2PPS1_SPEC_STATE_8822C 0x057C
+#define REG_P2PPS1_STATE_8822C 0x057D
+#define REG_P2PPS2_SPEC_STATE_8822C 0x057E
+#define REG_P2PPS2_STATE_8822C 0x057F
+#define REG_PS_TIMER0_8822C 0x0580
+#define REG_PS_TIMER1_8822C 0x0584
+#define REG_PS_TIMER2_8822C 0x0588
+#define REG_TBTT_CTN_AREA_8822C 0x058C
+#define REG_FORCE_BCN_IFS_8822C 0x058E
+#define REG_TXOP_MIN_8822C 0x0590
+#define REG_PRE_BKF_TIME_8822C 0x0592
+#define REG_CROSS_TXOP_CTRL_8822C 0x0593
+#define REG_RX_TBTT_SHIFT_V1_8822C 0x0598
+#define REG_ATIMWND2_8822C 0x05A0
+#define REG_ATIMWND3_8822C 0x05A1
+#define REG_ATIMWND4_8822C 0x05A2
+#define REG_ATIMWND5_8822C 0x05A3
+#define REG_ATIMWND6_8822C 0x05A4
+#define REG_ATIMWND7_8822C 0x05A5
+#define REG_ATIMUGT_8822C 0x05A6
+#define REG_HIQ_NO_LMT_EN_8822C 0x05A7
+#define REG_DTIM_COUNTER_ROOT_8822C 0x05A8
+#define REG_DTIM_COUNTER_VAP1_8822C 0x05A9
+#define REG_DTIM_COUNTER_VAP2_8822C 0x05AA
+#define REG_DTIM_COUNTER_VAP3_8822C 0x05AB
+#define REG_DTIM_COUNTER_VAP4_8822C 0x05AC
+#define REG_DTIM_COUNTER_VAP5_8822C 0x05AD
+#define REG_DTIM_COUNTER_VAP6_8822C 0x05AE
+#define REG_DTIM_COUNTER_VAP7_8822C 0x05AF
+#define REG_DIS_ATIM_8822C 0x05B0
+#define REG_EARLY_128US_8822C 0x05B1
+#define REG_P2PPS1_CTRL_8822C 0x05B2
+#define REG_P2PPS2_CTRL_8822C 0x05B3
+#define REG_TIMER0_SRC_SEL_8822C 0x05B4
+#define REG_NOA_UNIT_SEL_8822C 0x05B5
+#define REG_P2POFF_DIS_TXTIME_8822C 0x05B7
+#define REG_MBSSID_BCN_SPACE2_8822C 0x05B8
+#define REG_MBSSID_BCN_SPACE3_8822C 0x05BC
+#define REG_ACMHWCTRL_8822C 0x05C0
+#define REG_ACMRSTCTRL_8822C 0x05C1
+#define REG_ACMAVG_8822C 0x05C2
+#define REG_VO_ADMTIME_8822C 0x05C4
+#define REG_VI_ADMTIME_8822C 0x05C6
+#define REG_BE_ADMTIME_8822C 0x05C8
+#define REG_MAC_HEADER_NAV_OFFSET_8822C 0x05CA
+#define REG_DIS_NDPA_NAV_CHECK_8822C 0x05CB
+#define REG_EDCA_RANDOM_GEN_8822C 0x05CC
+#define REG_TXCMD_NOA_SEL_8822C 0x05CF
+#define REG_32K_CLK_SEL_8822C 0x05D0
+#define REG_EARLYINT_ADJUST_8822C 0x05D4
+#define REG_BCNERR_CNT_8822C 0x05D8
+#define REG_BCNERR_CNT_2_8822C 0x05DC
+#define REG_NOA_PARAM_8822C 0x05E0
+#define REG_NOA_PARAM_1_8822C 0x05E4
+#define REG_NOA_PARAM_2_8822C 0x05E8
+#define REG_NOA_PARAM_3_8822C 0x05EC
+#define REG_P2P_RST_8822C 0x05F0
+#define REG_SCHEDULER_RST_8822C 0x05F1
+#define REG_SCH_DBG_VALUE_8822C 0x05F4
+#define REG_SCH_TXCMD_8822C 0x05F8
+#define REG_PAGE5_DUMMY_8822C 0x05FC
+#define REG_CPUMGQ_TX_TIMER_8822C 0x1500
+#define REG_PS_TIMER_A_8822C 0x1504
+#define REG_PS_TIMER_B_8822C 0x1508
+#define REG_PS_TIMER_C_8822C 0x150C
+#define REG_PS_TIMER_ABC_CPUMGQ_TIMER_CRTL_8822C 0x1510
+#define REG_CPUMGQ_TX_TIMER_EARLY_8822C 0x1514
+#define REG_PS_TIMER_A_EARLY_8822C 0x1515
+#define REG_PS_TIMER_B_EARLY_8822C 0x1516
+#define REG_PS_TIMER_C_EARLY_8822C 0x1517
+#define REG_CPUMGQ_PARAMETER_8822C 0x1518
+#define REG_TSF_SYNC_ADJ_8822C 0x1520
+#define REG_TSF_ADJ_VLAUE_8822C 0x1524
+#define REG_TSF_ADJ_VLAUE_2_8822C 0x1528
+#define REG_P2PPS_HW_AUTO_PAUSE_CTRL_8822C 0x156C
+#define REG_P2PPS1_HW_AUTO_PAUSE_CTRL_8822C 0x1570
+#define REG_P2PPS2_HW_AUTO_PAUSE_CTRL_8822C 0x1574
+#define REG_SCHEDULER_COUNTER_8822C 0x15D0
+#define REG_WMAC_CR_8822C 0x0600
+#define REG_WMAC_FWPKT_CR_8822C 0x0601
+#define REG_FW_STS_FILTER_8822C 0x0602
+#define REG_TCR_8822C 0x0604
+#define REG_RCR_8822C 0x0608
+#define REG_RX_PKT_LIMIT_8822C 0x060C
+#define REG_RX_DLK_TIME_8822C 0x060D
+#define REG_RX_DRVINFO_SZ_8822C 0x060F
+#define REG_MACID_8822C 0x0610
+#define REG_MACID_H_8822C 0x0614
+#define REG_BSSID_8822C 0x0618
+#define REG_BSSID_H_8822C 0x061C
+#define REG_MAR_8822C 0x0620
+#define REG_MAR_H_8822C 0x0624
+#define REG_MBIDCAMCFG_1_8822C 0x0628
+#define REG_MBIDCAMCFG_2_8822C 0x062C
+#define REG_WMAC_TCR_TSFT_OFS_8822C 0x0630
+#define REG_UDF_THSD_8822C 0x0632
+#define REG_ZLD_NUM_8822C 0x0633
+#define REG_STMP_THSD_8822C 0x0634
+#define REG_WMAC_TXTIMEOUT_8822C 0x0635
+#define REG_USTIME_EDCA_8822C 0x0638
+#define REG_ACKTO_CCK_8822C 0x0639
+#define REG_MAC_SPEC_SIFS_8822C 0x063A
+#define REG_RESP_SIFS_CCK_8822C 0x063C
+#define REG_RESP_SIFS_OFDM_8822C 0x063E
+#define REG_ACKTO_8822C 0x0640
+#define REG_CTS2TO_8822C 0x0641
+#define REG_EIFS_8822C 0x0642
+#define REG_RPFM_MAP0_8822C 0x0644
+#define REG_RPFM_MAP1_V1_8822C 0x0646
+#define REG_RPFM_CAM_CMD_8822C 0x0648
+#define REG_RPFM_CAM_RWD_8822C 0x064C
+#define REG_NAV_CTRL_8822C 0x0650
+#define REG_BACAMCMD_8822C 0x0654
+#define REG_BACAMCONTENT_8822C 0x0658
+#define REG_BACAMCONTENT_H_8822C 0x065C
+#define REG_LBDLY_8822C 0x0660
+#define REG_WMAC_BACAM_RPMEN_8822C 0x0661
+#define REG_TX_RX_8822C 0x0662
+#define REG_WMAC_BITMAP_CTL_8822C 0x0663
+#define REG_RXERR_RPT_8822C 0x0664
+#define REG_WMAC_TRXPTCL_CTL_8822C 0x0668
+#define REG_WMAC_TRXPTCL_CTL_H_8822C 0x066C
+#define REG_CAMCMD_8822C 0x0670
+#define REG_CAMWRITE_8822C 0x0674
+#define REG_CAMREAD_8822C 0x0678
+#define REG_CAMDBG_8822C 0x067C
+#define REG_SECCFG_8822C 0x0680
+#define REG_RXFILTER_CATEGORY_1_8822C 0x0682
+#define REG_RXFILTER_ACTION_1_8822C 0x0683
+#define REG_RXFILTER_CATEGORY_2_8822C 0x0684
+#define REG_RXFILTER_ACTION_2_8822C 0x0685
+#define REG_RXFILTER_CATEGORY_3_8822C 0x0686
+#define REG_RXFILTER_ACTION_3_8822C 0x0687
+#define REG_RXFLTMAP3_8822C 0x0688
+#define REG_RXFLTMAP4_8822C 0x068A
+#define REG_RXFLTMAP5_8822C 0x068C
+#define REG_RXFLTMAP6_8822C 0x068E
+#define REG_WOW_CTRL_8822C 0x0690
+#define REG_NAN_RX_TSF_FILTER_8822C 0x0691
+#define REG_PS_RX_INFO_8822C 0x0692
+#define REG_WMMPS_UAPSD_TID_8822C 0x0693
+#define REG_LPNAV_CTRL_8822C 0x0694
+#define REG_WKFMCAM_CMD_8822C 0x0698
+#define REG_WKFMCAM_RWD_8822C 0x069C
+#define REG_RXFLTMAP0_8822C 0x06A0
+#define REG_RXFLTMAP1_8822C 0x06A2
+#define REG_RXFLTMAP2_8822C 0x06A4
+#define REG_BCN_PSR_RPT_8822C 0x06A8
+#define REG_FLC_RPC_8822C 0x06AC
+#define REG_FLC_RPCT_8822C 0x06AD
+#define REG_FLC_PTS_8822C 0x06AE
+#define REG_FLC_TRPC_8822C 0x06AF
+#define REG_RXPKTMON_CTRL_8822C 0x06B0
+#define REG_STATE_MON_8822C 0x06B4
+#define REG_ERROR_MON_8822C 0x06B8
+#define REG_SEARCH_MACID_8822C 0x06BC
+#define REG_BT_COEX_TABLE_8822C 0x06C0
+#define REG_BT_COEX_TABLE2_8822C 0x06C4
+#define REG_BT_COEX_BREAK_TABLE_8822C 0x06C8
+#define REG_BT_COEX_TABLE_H_8822C 0x06CC
+#define REG_RXCMD_0_8822C 0x06D0
+#define REG_RXCMD_1_8822C 0x06D4
+#define REG_WMAC_RESP_TXINFO_8822C 0x06D8
+#define REG_BBPSF_CTRL_8822C 0x06DC
+#define REG_P2P_RX_BCN_NOA_8822C 0x06E0
+#define REG_ASSOCIATED_BFMER0_INFO_8822C 0x06E4
+#define REG_ASSOCIATED_BFMER0_INFO_H_8822C 0x06E8
+#define REG_ASSOCIATED_BFMER1_INFO_8822C 0x06EC
+#define REG_ASSOCIATED_BFMER1_INFO_H_8822C 0x06F0
+#define REG_TX_CSI_RPT_PARAM_BW20_8822C 0x06F4
+#define REG_TX_CSI_RPT_PARAM_BW40_8822C 0x06F8
+#define REG_CSI_PTR_8822C 0x06FC
+#define REG_BCN_PSR_RPT2_8822C 0x1600
+#define REG_BCN_PSR_RPT3_8822C 0x1604
+#define REG_BCN_PSR_RPT4_8822C 0x1608
+#define REG_A1_ADDR_MASK_8822C 0x160C
+#define REG_RXPSF_CTRL_8822C 0x1610
+#define REG_RXPSF_TYPE_CTRL_8822C 0x1614
+#define REG_CAM_ACCESS_CTRL_8822C 0x1618
+#define REG_HT_SND_REF_RATE_8822C 0x161C
+#define REG_MACID2_8822C 0x1620
+#define REG_MACID2_H_8822C 0x1624
+#define REG_BSSID2_8822C 0x1628
+#define REG_BSSID2_H_8822C 0x162C
+#define REG_MACID3_8822C 0x1630
+#define REG_MACID3_H_8822C 0x1634
+#define REG_BSSID3_8822C 0x1638
+#define REG_BSSID3_H_8822C 0x163C
+#define REG_MACID4_8822C 0x1640
+#define REG_MACID4_H_8822C 0x1644
+#define REG_BSSID4_8822C 0x1648
+#define REG_BSSID4_H_8822C 0x164C
+#define REG_NOA_REPORT_8822C 0x1650
+#define REG_NOA_REPORT_1_8822C 0x1654
+#define REG_NOA_REPORT_2_8822C 0x1658
+#define REG_NOA_REPORT_3_8822C 0x165C
+#define REG_PWRBIT_SETTING_8822C 0x1660
+#define REG_GENERAL_OPTION_8822C 0x1664
+#define REG_CSI_RRSR_8822C 0x1678
+#define REG_MU_BF_OPTION_8822C 0x167C
+#define REG_WMAC_PAUSE_BB_CLR_TH_8822C 0x167D
+#define REG__WMAC_MULBK_BUF_8822C 0x167E
+#define REG_WMAC_MU_OPTION_8822C 0x167F
+#define REG_WMAC_MU_BF_CTL_8822C 0x1680
+#define REG_WMAC_MU_BFRPT_PARA_8822C 0x1682
+#define REG_WMAC_ASSOCIATED_MU_BFMEE2_8822C 0x1684
+#define REG_WMAC_ASSOCIATED_MU_BFMEE3_8822C 0x1686
+#define REG_WMAC_ASSOCIATED_MU_BFMEE4_8822C 0x1688
+#define REG_WMAC_ASSOCIATED_MU_BFMEE5_8822C 0x168A
+#define REG_WMAC_ASSOCIATED_MU_BFMEE6_8822C 0x168C
+#define REG_WMAC_ASSOCIATED_MU_BFMEE7_8822C 0x168E
+#define REG_WMAC_BB_STOP_RX_COUNTER_8822C 0x1690
+#define REG_WMAC_PLCP_MONITOR_8822C 0x1694
+#define REG_WMAC_PLCP_MONITOR_MUTX_8822C 0x1698
+#define REG_WMAC_CSIDMA_CFG_8822C 0x169C
+#define REG_TRANSMIT_ADDRSS_0_8822C 0x16A0
+#define REG_TRANSMIT_ADDRSS_0_H_8822C 0x16A4
+#define REG_TRANSMIT_ADDRSS_1_8822C 0x16A8
+#define REG_TRANSMIT_ADDRSS_1_H_8822C 0x16AC
+#define REG_TRANSMIT_ADDRSS_2_8822C 0x16B0
+#define REG_TRANSMIT_ADDRSS_2_H_8822C 0x16B4
+#define REG_TRANSMIT_ADDRSS_3_8822C 0x16B8
+#define REG_TRANSMIT_ADDRSS_3_H_8822C 0x16BC
+#define REG_TRANSMIT_ADDRSS_4_8822C 0x16C0
+#define REG_TRANSMIT_ADDRSS_4_H_8822C 0x16C4
+#define REG_MACID1_8822C 0x0700
+#define REG_MACID1_1_8822C 0x0704
+#define REG_BSSID1_8822C 0x0708
+#define REG_BSSID1_1_8822C 0x070C
+#define REG_BCN_PSR_RPT1_8822C 0x0710
+#define REG_ASSOCIATED_BFMEE_SEL_8822C 0x0714
+#define REG_SND_PTCL_CTRL_8822C 0x0718
+#define REG_RX_CSI_RPT_INFO_8822C 0x071C
+#define REG_NS_ARP_CTRL_8822C 0x0720
+#define REG_NS_ARP_INFO_8822C 0x0724
+#define REG_BEAMFORMING_INFO_NSARP_V1_8822C 0x0728
+#define REG_BEAMFORMING_INFO_NSARP_8822C 0x072C
+#define REG_IPV6_8822C 0x0730
+#define REG_IPV6_1_8822C 0x0734
+#define REG_IPV6_2_8822C 0x0738
+#define REG_IPV6_3_8822C 0x073C
+#define REG_WMAC_RTX_CTX_SUBTYPE_CFG_8822C 0x0750
+#define REG_WMAC_SWAES_DIO_B63_B32_8822C 0x0754
+#define REG_WMAC_SWAES_DIO_B95_B64_8822C 0x0758
+#define REG_WMAC_SWAES_DIO_B127_B96_8822C 0x075C
+#define REG_WMAC_SWAES_CFG_8822C 0x0760
+#define REG_BT_COEX_V2_8822C 0x0762
+#define REG_BT_COEX_8822C 0x0764
+#define REG_WLAN_ACT_MASK_CTRL_8822C 0x0768
+#define REG_WLAN_ACT_MASK_CTRL_1_8822C 0x076C
+#define REG_BT_COEX_ENHANCED_INTR_CTRL_8822C 0x076E
+#define REG_BT_ACT_STATISTICS_8822C 0x0770
+#define REG_BT_ACT_STATISTICS_1_8822C 0x0774
+#define REG_BT_STATISTICS_CONTROL_REGISTER_8822C 0x0778
+#define REG_BT_STATUS_REPORT_REGISTER_8822C 0x077C
+#define REG_BT_INTERRUPT_CONTROL_REGISTER_8822C 0x0780
+#define REG_WLAN_REPORT_TIME_OUT_CONTROL_REGISTER_8822C 0x0784
+#define REG_BT_ISOLATION_TABLE_REGISTER_REGISTER_8822C 0x0785
+#define REG_BT_ISOLATION_TABLE_REGISTER_REGISTER_1_8822C 0x0788
+#define REG_BT_ISOLATION_TABLE_REGISTER_REGISTER_2_8822C 0x078C
+#define REG_BT_INTERRUPT_STATUS_REGISTER_8822C 0x078F
+#define REG_BT_TDMA_TIME_REGISTER_8822C 0x0790
+#define REG_BT_ACT_REGISTER_8822C 0x0794
+#define REG_OBFF_CTRL_BASIC_8822C 0x0798
+#define REG_OBFF_CTRL2_TIMER_8822C 0x079C
+#define REG_LTR_CTRL_BASIC_8822C 0x07A0
+#define REG_LTR_CTRL2_TIMER_THRESHOLD_8822C 0x07A4
+#define REG_LTR_IDLE_LATENCY_V1_8822C 0x07A8
+#define REG_LTR_ACTIVE_LATENCY_V1_8822C 0x07AC
+#define REG_ANTENNA_TRAINING_CONTROL_REGISTER_8822C 0x07B0
+#define REG_ANTENNA_TRAINING_CONTROL_REGISTER_1_8822C 0x07B4
+#define REG_WMAC_PKTCNT_RWD_8822C 0x07B8
+#define REG_WMAC_PKTCNT_CTRL_8822C 0x07BC
+#define REG_IQ_DUMP_8822C 0x07C0
+#define REG_IQ_DUMP_1_8822C 0x07C4
+#define REG_IQ_DUMP_2_8822C 0x07C8
+#define REG_WMAC_FTM_CTL_8822C 0x07CC
+#define REG_WMAC_IQ_MDPK_FUNC_8822C 0x07CE
+#define REG_WMAC_OPTION_FUNCTION_8822C 0x07D0
+#define REG_WMAC_OPTION_FUNCTION_1_8822C 0x07D4
+#define REG_WMAC_OPTION_FUNCTION_2_8822C 0x07D8
+#define REG_RX_FILTER_FUNCTION_8822C 0x07DA
+#define REG_NDP_SIG_8822C 0x07E0
+#define REG_TXCMD_INFO_FOR_RSP_PKT_8822C 0x07E4
+#define REG_TXCMD_INFO_FOR_RSP_PKT_1_8822C 0x07E8
+#define REG_WSEC_OPTION_8822C 0x07EC
+#define REG_RTS_ADDRESS_0_8822C 0x07F0
+#define REG_RTS_ADDRESS_0_1_8822C 0x07F4
+#define REG_RTS_ADDRESS_1_8822C 0x07F8
+#define REG_RTS_ADDRESS_1_1_8822C 0x07FC
+#define REG_WL2LTECOEX_INDIRECT_ACCESS_CTRL_V1_8822C 0x1700
+#define REG_WL2LTECOEX_INDIRECT_ACCESS_WRITE_DATA_V1_8822C 0x1704
+#define REG_WL2LTECOEX_INDIRECT_ACCESS_READ_DATA_V1_8822C 0x1708
+#define REG_SDIO_TX_CTRL_8822C 0x10250000
+#define REG_SDIO_CMD11_VOL_SWITCH_8822C 0x10250004
+#define REG_SDIO_CTRL_8822C 0x10250005
+#define REG_SDIO_DRIVING_8822C 0x10250006
+#define REG_SDIO_MONITOR_8822C 0x10250008
+#define REG_SDIO_MONITOR_2_8822C 0x1025000C
+#define REG_SDIO_HIMR_8822C 0x10250014
+#define REG_SDIO_HISR_8822C 0x10250018
+#define REG_SDIO_RX_REQ_LEN_8822C 0x1025001C
+#define REG_SDIO_FREE_TXPG_SEQ_V1_8822C 0x1025001F
+#define REG_SDIO_FREE_TXPG_8822C 0x10250020
+#define REG_SDIO_FREE_TXPG2_8822C 0x10250024
+#define REG_SDIO_OQT_FREE_TXPG_V1_8822C 0x10250028
+#define REG_SDIO_TXPKT_EMPTY_8822C 0x1025002C
+#define REG_SDIO_HTSFR_INFO_8822C 0x10250030
+#define REG_SDIO_HCPWM1_V2_8822C 0x10250038
+#define REG_SDIO_HCPWM2_V2_8822C 0x1025003A
+#define REG_SDIO_INDIRECT_REG_CFG_8822C 0x10250040
+#define REG_SDIO_INDIRECT_REG_DATA_8822C 0x10250044
+#define REG_SDIO_H2C_8822C 0x10250060
+#define REG_SDIO_C2H_8822C 0x10250064
+#define REG_SDIO_HRPWM1_8822C 0x10250080
+#define REG_SDIO_HRPWM2_8822C 0x10250082
+#define REG_SDIO_HPS_CLKR_8822C 0x10250084
+#define REG_SDIO_BUS_CTRL_8822C 0x10250085
+#define REG_SDIO_HSUS_CTRL_8822C 0x10250086
+#define REG_SDIO_RESPONSE_TIMER_8822C 0x10250088
+#define REG_SDIO_CMD_CRC_8822C 0x1025008A
+#define REG_SDIO_HSISR_8822C 0x10250090
+#define REG_SDIO_HSIMR_8822C 0x10250091
+#define REG_SDIO_DIOERR_RPT_8822C 0x102500C0
+#define REG_SDIO_CMD_ERRCNT_8822C 0x102500C2
+#define REG_SDIO_DATA_ERRCNT_8822C 0x102500C3
+#define REG_SDIO_CMD_ERR_CONTENT_8822C 0x102500C4
+#define REG_SDIO_CRC_ERR_IDX_8822C 0x102500C9
+#define REG_SDIO_DATA_CRC_8822C 0x102500CA
+#define REG_SDIO_TRANS_FIFO_STATUS_8822C 0x102500CC
+
+#endif
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/halmac/halmac_rx_bd_ap.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/halmac/halmac_rx_bd_ap.h
--- linux-5.6.3/3rdparty/rtl8821ce/hal/halmac/halmac_rx_bd_ap.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/halmac/halmac_rx_bd_ap.h	2020-04-10 16:35:06.816660067 +0300
@@ -0,0 +1,25 @@
+#ifndef _HALMAC_RX_BD_AP_H_
+#define _HALMAC_RX_BD_AP_H_
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8188F_SUPPORT)
+
+/*TXBD_DW0*/
+
+#define GET_RX_BD_RXFAIL(__pRxBd)    HALMAC_GET_BD_FIELD(((PHALMAC_RX_BD)__pRxBd)->Dword0, 0x1, 31)
+#define GET_RX_BD_TOTALRXPKTSIZE(__pRxBd)    HALMAC_GET_BD_FIELD(((PHALMAC_RX_BD)__pRxBd)->Dword0, 0x1fff, 16)
+#define GET_RX_BD_RXTAG(__pRxBd)    HALMAC_GET_BD_FIELD(((PHALMAC_RX_BD)__pRxBd)->Dword0, 0x1fff, 16)
+#define GET_RX_BD_FS(__pRxBd)    HALMAC_GET_BD_FIELD(((PHALMAC_RX_BD)__pRxBd)->Dword0, 0x1, 15)
+#define GET_RX_BD_LS(__pRxBd)    HALMAC_GET_BD_FIELD(((PHALMAC_RX_BD)__pRxBd)->Dword0, 0x1, 14)
+#define GET_RX_BD_RXBUFFSIZE(__pRxBd)    HALMAC_GET_BD_FIELD(((PHALMAC_RX_BD)__pRxBd)->Dword0, 0x3fff, 0)
+
+/*TXBD_DW1*/
+
+#define GET_RX_BD_PHYSICAL_ADDR_LOW(__pRxBd)    HALMAC_GET_BD_FIELD(((PHALMAC_RX_BD)__pRxBd)->Dword1, 0xffffffff, 0)
+
+/*TXBD_DW2*/
+
+#define GET_RX_BD_PHYSICAL_ADDR_HIGH(__pRxBd)    HALMAC_GET_BD_FIELD(((PHALMAC_RX_BD)__pRxBd)->Dword2, 0xffffffff, 0)
+
+#endif
+
+
+#endif
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/halmac/halmac_rx_bd_chip.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/halmac/halmac_rx_bd_chip.h
--- linux-5.6.3/3rdparty/rtl8821ce/hal/halmac/halmac_rx_bd_chip.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/halmac/halmac_rx_bd_chip.h	2020-04-10 16:35:06.816660067 +0300
@@ -0,0 +1,109 @@
+#ifndef _HALMAC_RX_BD_CHIP_H_
+#define _HALMAC_RX_BD_CHIP_H_
+#if (HALMAC_8814A_SUPPORT)
+
+/*TXBD_DW0*/
+
+#define GET_RX_BD_RXFAIL_8814A(__pRxBd)    GET_RX_BD_RXFAIL(__pRxBd)
+#define GET_RX_BD_TOTALRXPKTSIZE_8814A(__pRxBd)    GET_RX_BD_TOTALRXPKTSIZE(__pRxBd)
+#define GET_RX_BD_RXTAG_8814A(__pRxBd)    GET_RX_BD_RXTAG(__pRxBd)
+#define GET_RX_BD_FS_8814A(__pRxBd)    GET_RX_BD_FS(__pRxBd)
+#define GET_RX_BD_LS_8814A(__pRxBd)    GET_RX_BD_LS(__pRxBd)
+#define GET_RX_BD_RXBUFFSIZE_8814A(__pRxBd)    GET_RX_BD_RXBUFFSIZE(__pRxBd)
+
+/*TXBD_DW1*/
+
+#define GET_RX_BD_PHYSICAL_ADDR_LOW_8814A(__pRxBd)    GET_RX_BD_PHYSICAL_ADDR_LOW(__pRxBd)
+
+/*TXBD_DW2*/
+
+#define GET_RX_BD_PHYSICAL_ADDR_HIGH_8814A(__pRxBd)    GET_RX_BD_PHYSICAL_ADDR_HIGH(__pRxBd)
+
+#endif
+
+#if (HALMAC_8822B_SUPPORT)
+
+/*TXBD_DW0*/
+
+#define GET_RX_BD_RXFAIL_8822B(__pRxBd)    GET_RX_BD_RXFAIL(__pRxBd)
+#define GET_RX_BD_TOTALRXPKTSIZE_8822B(__pRxBd)    GET_RX_BD_TOTALRXPKTSIZE(__pRxBd)
+#define GET_RX_BD_RXTAG_8822B(__pRxBd)    GET_RX_BD_RXTAG(__pRxBd)
+#define GET_RX_BD_FS_8822B(__pRxBd)    GET_RX_BD_FS(__pRxBd)
+#define GET_RX_BD_LS_8822B(__pRxBd)    GET_RX_BD_LS(__pRxBd)
+#define GET_RX_BD_RXBUFFSIZE_8822B(__pRxBd)    GET_RX_BD_RXBUFFSIZE(__pRxBd)
+
+/*TXBD_DW1*/
+
+#define GET_RX_BD_PHYSICAL_ADDR_LOW_8822B(__pRxBd)    GET_RX_BD_PHYSICAL_ADDR_LOW(__pRxBd)
+
+/*TXBD_DW2*/
+
+#define GET_RX_BD_PHYSICAL_ADDR_HIGH_8822B(__pRxBd)    GET_RX_BD_PHYSICAL_ADDR_HIGH(__pRxBd)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT)
+
+/*TXBD_DW0*/
+
+#define GET_RX_BD_RXFAIL_8197F(__pRxBd)    GET_RX_BD_RXFAIL(__pRxBd)
+#define GET_RX_BD_TOTALRXPKTSIZE_8197F(__pRxBd)    GET_RX_BD_TOTALRXPKTSIZE(__pRxBd)
+#define GET_RX_BD_RXTAG_8197F(__pRxBd)    GET_RX_BD_RXTAG(__pRxBd)
+#define GET_RX_BD_FS_8197F(__pRxBd)    GET_RX_BD_FS(__pRxBd)
+#define GET_RX_BD_LS_8197F(__pRxBd)    GET_RX_BD_LS(__pRxBd)
+#define GET_RX_BD_RXBUFFSIZE_8197F(__pRxBd)    GET_RX_BD_RXBUFFSIZE(__pRxBd)
+
+/*TXBD_DW1*/
+
+#define GET_RX_BD_PHYSICAL_ADDR_LOW_8197F(__pRxBd)    GET_RX_BD_PHYSICAL_ADDR_LOW(__pRxBd)
+
+/*TXBD_DW2*/
+
+#define GET_RX_BD_PHYSICAL_ADDR_HIGH_8197F(__pRxBd)    GET_RX_BD_PHYSICAL_ADDR_HIGH(__pRxBd)
+
+#endif
+
+#if (HALMAC_8821C_SUPPORT)
+
+/*TXBD_DW0*/
+
+#define GET_RX_BD_RXFAIL_8821C(__pRxBd)    GET_RX_BD_RXFAIL(__pRxBd)
+#define GET_RX_BD_TOTALRXPKTSIZE_8821C(__pRxBd)    GET_RX_BD_TOTALRXPKTSIZE(__pRxBd)
+#define GET_RX_BD_RXTAG_8821C(__pRxBd)    GET_RX_BD_RXTAG(__pRxBd)
+#define GET_RX_BD_FS_8821C(__pRxBd)    GET_RX_BD_FS(__pRxBd)
+#define GET_RX_BD_LS_8821C(__pRxBd)    GET_RX_BD_LS(__pRxBd)
+#define GET_RX_BD_RXBUFFSIZE_8821C(__pRxBd)    GET_RX_BD_RXBUFFSIZE(__pRxBd)
+
+/*TXBD_DW1*/
+
+#define GET_RX_BD_PHYSICAL_ADDR_LOW_8821C(__pRxBd)    GET_RX_BD_PHYSICAL_ADDR_LOW(__pRxBd)
+
+/*TXBD_DW2*/
+
+#define GET_RX_BD_PHYSICAL_ADDR_HIGH_8821C(__pRxBd)    GET_RX_BD_PHYSICAL_ADDR_HIGH(__pRxBd)
+
+#endif
+
+#if (HALMAC_8188F_SUPPORT)
+
+/*TXBD_DW0*/
+
+#define GET_RX_BD_RXFAIL_8188F(__pRxBd)    GET_RX_BD_RXFAIL(__pRxBd)
+#define GET_RX_BD_TOTALRXPKTSIZE_8188F(__pRxBd)    GET_RX_BD_TOTALRXPKTSIZE(__pRxBd)
+#define GET_RX_BD_RXTAG_8188F(__pRxBd)    GET_RX_BD_RXTAG(__pRxBd)
+#define GET_RX_BD_FS_8188F(__pRxBd)    GET_RX_BD_FS(__pRxBd)
+#define GET_RX_BD_LS_8188F(__pRxBd)    GET_RX_BD_LS(__pRxBd)
+#define GET_RX_BD_RXBUFFSIZE_8188F(__pRxBd)    GET_RX_BD_RXBUFFSIZE(__pRxBd)
+
+/*TXBD_DW1*/
+
+#define GET_RX_BD_PHYSICAL_ADDR_LOW_8188F(__pRxBd)    GET_RX_BD_PHYSICAL_ADDR_LOW(__pRxBd)
+
+/*TXBD_DW2*/
+
+#define GET_RX_BD_PHYSICAL_ADDR_HIGH_8188F(__pRxBd)    GET_RX_BD_PHYSICAL_ADDR_HIGH(__pRxBd)
+
+#endif
+
+
+#endif
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/halmac/halmac_rx_bd_nic.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/halmac/halmac_rx_bd_nic.h
--- linux-5.6.3/3rdparty/rtl8821ce/hal/halmac/halmac_rx_bd_nic.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/halmac/halmac_rx_bd_nic.h	2020-04-10 16:35:06.816660067 +0300
@@ -0,0 +1,41 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ ******************************************************************************/
+
+#ifndef _HALMAC_RX_BD_NIC_H_
+#define _HALMAC_RX_BD_NIC_H_
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+	HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT ||\
+	HALMAC_8812F_SUPPORT)
+
+/*TXBD_DW0*/
+
+#define GET_RX_BD_RXFAIL(rxbd) LE_BITS_TO_4BYTE(rxbd + 0x00, 31, 1)
+#define GET_RX_BD_TOTALRXPKTSIZE(rxbd) LE_BITS_TO_4BYTE(rxbd + 0x00, 16, 13)
+#define GET_RX_BD_RXTAG(rxbd) LE_BITS_TO_4BYTE(rxbd + 0x00, 16, 13)
+#define GET_RX_BD_FS(rxbd) LE_BITS_TO_4BYTE(rxbd + 0x00, 15, 1)
+#define GET_RX_BD_LS(rxbd) LE_BITS_TO_4BYTE(rxbd + 0x00, 14, 1)
+#define GET_RX_BD_RXBUFFSIZE(rxbd) LE_BITS_TO_4BYTE(rxbd + 0x00, 0, 14)
+
+/*TXBD_DW1*/
+
+#define GET_RX_BD_PHYSICAL_ADDR_LOW(rxbd) LE_BITS_TO_4BYTE(rxbd + 0x04, 0, 32)
+
+/*TXBD_DW2*/
+
+#define GET_RX_BD_PHYSICAL_ADDR_HIGH(rxbd) LE_BITS_TO_4BYTE(rxbd + 0x08, 0, 32)
+
+#endif
+
+#endif
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/halmac/halmac_rx_desc_ap.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/halmac/halmac_rx_desc_ap.h
--- linux-5.6.3/3rdparty/rtl8821ce/hal/halmac/halmac_rx_desc_ap.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/halmac/halmac_rx_desc_ap.h	2020-04-10 16:35:06.816660067 +0300
@@ -0,0 +1,630 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ ******************************************************************************/
+
+#ifndef _HALMAC_RX_DESC_AP_H_
+#define _HALMAC_RX_DESC_AP_H_
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT)
+
+/*RXDESC_WORD0*/
+
+#define GET_RX_DESC_EOR(rxdesc)                                                \
+	HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword0, 0x1,  \
+			      30)
+#define GET_RX_DESC_PHYPKTIDC(rxdesc)                                          \
+	HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword0, 0x1,  \
+			      28)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define GET_RX_DESC_EVT_PKT(rxdesc)                                            \
+	HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword0, 0x1,  \
+			      28)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT || HALMAC_8812F_SUPPORT)
+
+#define GET_RX_DESC_SWDEC(rxdesc)                                              \
+	HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword0, 0x1,  \
+			      27)
+#define GET_RX_DESC_PHYST(rxdesc)                                              \
+	HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword0, 0x1,  \
+			      26)
+#define GET_RX_DESC_SHIFT(rxdesc)                                              \
+	HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword0, 0x3,  \
+			      24)
+#define GET_RX_DESC_QOS(rxdesc)                                                \
+	HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword0, 0x1,  \
+			      23)
+#define GET_RX_DESC_SECURITY(rxdesc)                                           \
+	HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword0, 0x7,  \
+			      20)
+#define GET_RX_DESC_DRV_INFO_SIZE(rxdesc)                                      \
+	HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword0, 0xf,  \
+			      16)
+#define GET_RX_DESC_ICV_ERR(rxdesc)                                            \
+	HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword0, 0x1,  \
+			      15)
+#define GET_RX_DESC_CRC32(rxdesc)                                              \
+	HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword0, 0x1,  \
+			      14)
+#define GET_RX_DESC_PKT_LEN(rxdesc)                                            \
+	HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword0,       \
+			      0x3fff, 0)
+
+/*RXDESC_WORD1*/
+
+#define GET_RX_DESC_BC(rxdesc)                                                 \
+	HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword1, 0x1,  \
+			      31)
+#define GET_RX_DESC_MC(rxdesc)                                                 \
+	HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword1, 0x1,  \
+			      30)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT)
+
+#define GET_RX_DESC_TY_PE(rxdesc)                                              \
+	HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword1, 0x3,  \
+			      28)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define GET_RX_DESC_TYPE(rxdesc)                                               \
+	HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword1, 0x3,  \
+			      28)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT || HALMAC_8812F_SUPPORT)
+
+#define GET_RX_DESC_MF(rxdesc)                                                 \
+	HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword1, 0x1,  \
+			      27)
+#define GET_RX_DESC_MD(rxdesc)                                                 \
+	HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword1, 0x1,  \
+			      26)
+#define GET_RX_DESC_PWR(rxdesc)                                                \
+	HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword1, 0x1,  \
+			      25)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT)
+
+#define GET_RX_DESC_PAM(rxdesc)                                                \
+	HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword1, 0x1,  \
+			      24)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define GET_RX_DESC_A1_MATCH(rxdesc)                                           \
+	HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword1, 0x1,  \
+			      24)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT)
+
+#define GET_RX_DESC_CHK_VLD(rxdesc)                                            \
+	HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword1, 0x1,  \
+			      23)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define GET_RX_DESC_TCP_CHKSUM_VLD(rxdesc)                                     \
+	HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword1, 0x1,  \
+			      23)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT || HALMAC_8812F_SUPPORT)
+
+#define GET_RX_DESC_RX_IS_TCP_UDP(rxdesc)                                      \
+	HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword1, 0x1,  \
+			      22)
+#define GET_RX_DESC_RX_IPV(rxdesc)                                             \
+	HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword1, 0x1,  \
+			      21)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT)
+
+#define GET_RX_DESC_CHKERR(rxdesc)                                             \
+	HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword1, 0x1,  \
+			      20)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define GET_RX_DESC_TCP_CHKSUM_ERR(rxdesc)                                     \
+	HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword1, 0x1,  \
+			      20)
+#define GET_RX_DESC_PHY_PKT_IDC(rxdesc)                                        \
+	HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword1, 0x1,  \
+			      17)
+#define GET_RX_DESC_FW_FIFO_FULL(rxdesc)                                       \
+	HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword1, 0x1,  \
+			      16)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT)
+
+#define GET_RX_DESC_PAGGR(rxdesc)                                              \
+	HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword1, 0x1,  \
+			      15)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define GET_RX_DESC_AMPDU(rxdesc)                                              \
+	HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword1, 0x1,  \
+			      15)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT)
+
+#define GET_RX_DESC_RXID_MATCH(rxdesc)                                         \
+	HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword1, 0x1,  \
+			      14)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define GET_RX_DESC_RXCMD_IDC(rxdesc)                                          \
+	HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword1, 0x1,  \
+			      14)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT || HALMAC_8812F_SUPPORT)
+
+#define GET_RX_DESC_AMSDU(rxdesc)                                              \
+	HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword1, 0x1,  \
+			      13)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT)
+
+#define GET_RX_DESC_MACID_VLD(rxdesc)                                          \
+	HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword1, 0x1,  \
+			      12)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT || HALMAC_8812F_SUPPORT)
+
+#define GET_RX_DESC_TID(rxdesc)                                                \
+	HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword1, 0xf, 8)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT)
+
+#define GET_RX_DESC_MACID(rxdesc)                                              \
+	HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword1, 0x7f, \
+			      0)
+
+/*RXDESC_WORD2*/
+
+#define GET_RX_DESC_FCS_OK(rxdesc)                                             \
+	HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword2, 0x1,  \
+			      31)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define GET_RX_DESC_AMSDU_CUT(rxdesc)                                          \
+	HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword2, 0x1,  \
+			      31)
+
+#endif
+
+#if (HALMAC_8822B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8814B_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8812F_SUPPORT)
+
+#define GET_RX_DESC_PPDU_CNT(rxdesc)                                           \
+	HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword2, 0x3,  \
+			      29)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT || HALMAC_8812F_SUPPORT)
+
+#define GET_RX_DESC_C2H(rxdesc)                                                \
+	HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword2, 0x1,  \
+			      28)
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+#define GET_RX_DESC_HWRSVD_V1(rxdesc)                                          \
+	HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword2, 0x7,  \
+			      25)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8812F_SUPPORT)
+
+#define GET_RX_DESC_HWRSVD(rxdesc)                                             \
+	HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword2, 0xf,  \
+			      24)
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+#define GET_RX_DESC_RXMAGPKT(rxdesc)                                           \
+	HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword2, 0x1,  \
+			      24)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT || HALMAC_8812F_SUPPORT)
+
+#define GET_RX_DESC_WLANHD_IV_LEN(rxdesc)                                      \
+	HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword2, 0x3f, \
+			      18)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define GET_RX_DESC_LAST_MSDU(rxdesc)                                          \
+	HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword2, 0x1,  \
+			      17)
+
+#endif
+
+#if (HALMAC_8822C_SUPPORT || HALMAC_8812F_SUPPORT)
+
+#define GET_RX_DESC_RX_STATISTICS(rxdesc)                                      \
+	HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword2, 0x1,  \
+			      17)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT)
+
+#define GET_RX_DESC_RX_IS_QOS(rxdesc)                                          \
+	HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword2, 0x1,  \
+			      16)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define GET_RX_DESC_EXT_SEC_TYPE(rxdesc)                                       \
+	HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword2, 0x1,  \
+			      16)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT || HALMAC_8812F_SUPPORT)
+
+#define GET_RX_DESC_FRAG(rxdesc)                                               \
+	HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword2, 0xf,  \
+			      12)
+#define GET_RX_DESC_SEQ(rxdesc)                                                \
+	HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword2,       \
+			      0xfff, 0)
+
+/*RXDESC_WORD3*/
+
+#define GET_RX_DESC_MAGIC_WAKE(rxdesc)                                         \
+	HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword3, 0x1,  \
+			      31)
+#define GET_RX_DESC_UNICAST_WAKE(rxdesc)                                       \
+	HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword3, 0x1,  \
+			      30)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT)
+
+#define GET_RX_DESC_PATTERN_MATCH(rxdesc)                                      \
+	HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword3, 0x1,  \
+			      29)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define GET_RX_DESC_PATTERN_WAKE(rxdesc)                                       \
+	HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword3, 0x1,  \
+			      29)
+
+#endif
+
+#if (HALMAC_8822B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8814B_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8812F_SUPPORT)
+
+#define GET_RX_DESC_RXPAYLOAD_MATCH(rxdesc)                                    \
+	HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword3, 0x1,  \
+			      28)
+#define GET_RX_DESC_RXPAYLOAD_ID(rxdesc)                                       \
+	HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword3, 0xf,  \
+			      24)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT || HALMAC_8812F_SUPPORT)
+
+#define GET_RX_DESC_DMA_AGG_NUM(rxdesc)                                        \
+	HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword3, 0xff, \
+			      16)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT)
+
+#define GET_RX_DESC_BSSID_FIT_1_0(rxdesc)                                      \
+	HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword3, 0x3,  \
+			      12)
+#define GET_RX_DESC_EOSP(rxdesc)                                               \
+	HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword3, 0x1,  \
+			      11)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define GET_RX_DESC_BSSID_FIT(rxdesc)                                          \
+	HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword3, 0x1f, \
+			      11)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT || HALMAC_8812F_SUPPORT)
+
+#define GET_RX_DESC_HTC(rxdesc)                                                \
+	HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword3, 0x1,  \
+			      10)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define GET_RX_DESC_AMPDU_END_PKT(rxdesc)                                      \
+	HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword3, 0x1, 9)
+#define GET_RX_DESC_ADDRESS_CAM_VLD(rxdesc)                                    \
+	HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword3, 0x1, 8)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT)
+
+#define GET_RX_DESC_BSSID_FIT_4_2(rxdesc)                                      \
+	HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword3, 0x7, 7)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define GET_RX_DESC_EOSP_V1(rxdesc)                                            \
+	HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword3, 0x1, 7)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT || HALMAC_8812F_SUPPORT)
+
+#define GET_RX_DESC_RX_RATE(rxdesc)                                            \
+	HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword3, 0x7f, \
+			      0)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8812F_SUPPORT)
+
+/*RXDESC_WORD4*/
+
+#define GET_RX_DESC_A1_FIT(rxdesc)                                             \
+	HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword4, 0x1f, \
+			      24)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define GET_RX_DESC_ADDRESS_CAM(rxdesc)                                        \
+	HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword4, 0xff, \
+			      24)
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+#define GET_RX_DESC_A1_FIT_A1(rxdesc)                                          \
+	HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword4, 0x7f, \
+			      24)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define GET_RX_DESC_MACID_VLD_V1(rxdesc)                                       \
+	HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword4, 0x1,  \
+			      23)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT)
+
+#define GET_RX_DESC_MACID_RPT_BUFF(rxdesc)                                     \
+	HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword4, 0x7f, \
+			      17)
+#define GET_RX_DESC_RX_PRE_NDP_VLD(rxdesc)                                     \
+	HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword4, 0x1,  \
+			      16)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define GET_RX_DESC_MACID_V1(rxdesc)                                           \
+	HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword4, 0xff, \
+			      15)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT)
+
+#define GET_RX_DESC_RX_SCRAMBLER(rxdesc)                                       \
+	HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword4, 0x7f, \
+			      9)
+#define GET_RX_DESC_RX_EOF(rxdesc)                                             \
+	HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword4, 0x1, 8)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+#define GET_RX_DESC_FC_POWER(rxdesc)                                           \
+	HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword4, 0x1, 7)
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+#define GET_RX_DESC_TXRPTMID_CTL_MASK(rxdesc)                                  \
+	HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword4, 0x1, 6)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT || HALMAC_8198F_SUPPORT)
+
+#define GET_RX_DESC_SWPS_RPT(rxdesc)                                           \
+	HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword4, 0x1, 5)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT || HALMAC_8812F_SUPPORT)
+
+#define GET_RX_DESC_PATTERN_IDX(rxdesc)                                        \
+	HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword4, 0xff, \
+			      0)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+#define GET_RX_DESC_PATTERN_IDX_V1(rxdesc)                                     \
+	HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword4, 0x1f, \
+			      0)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define GET_RX_DESC_PATTERN_IDX_V2(rxdesc)                                     \
+	HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword4, 0x1f, \
+			      0)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT)
+
+/*RXDESC_WORD5*/
+
+#define GET_RX_DESC_TSFL(rxdesc)                                               \
+	HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword5,       \
+			      0xffffffff, 0)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define GET_RX_DESC_FREERUN_CNT(rxdesc)                                        \
+	HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword5,       \
+			      0xffffffff, 0)
+
+#endif
+
+#endif
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/halmac/halmac_rx_desc_chip.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/halmac/halmac_rx_desc_chip.h
--- linux-5.6.3/3rdparty/rtl8821ce/hal/halmac/halmac_rx_desc_chip.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/halmac/halmac_rx_desc_chip.h	2020-04-10 16:35:06.816660067 +0300
@@ -0,0 +1,698 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ ******************************************************************************/
+
+#ifndef _HALMAC_RX_DESC_CHIP_H_
+#define _HALMAC_RX_DESC_CHIP_H_
+#if (HALMAC_8814A_SUPPORT)
+
+/*RXDESC_WORD0*/
+
+#define GET_RX_DESC_EOR_8814A(rxdesc) GET_RX_DESC_EOR(rxdesc)
+#define GET_RX_DESC_PHYPKTIDC_8814A(rxdesc) GET_RX_DESC_PHYPKTIDC(rxdesc)
+#define GET_RX_DESC_SWDEC_8814A(rxdesc) GET_RX_DESC_SWDEC(rxdesc)
+#define GET_RX_DESC_PHYST_8814A(rxdesc) GET_RX_DESC_PHYST(rxdesc)
+#define GET_RX_DESC_SHIFT_8814A(rxdesc) GET_RX_DESC_SHIFT(rxdesc)
+#define GET_RX_DESC_QOS_8814A(rxdesc) GET_RX_DESC_QOS(rxdesc)
+#define GET_RX_DESC_SECURITY_8814A(rxdesc) GET_RX_DESC_SECURITY(rxdesc)
+#define GET_RX_DESC_DRV_INFO_SIZE_8814A(rxdesc)                                \
+	GET_RX_DESC_DRV_INFO_SIZE(rxdesc)
+#define GET_RX_DESC_ICV_ERR_8814A(rxdesc) GET_RX_DESC_ICV_ERR(rxdesc)
+#define GET_RX_DESC_CRC32_8814A(rxdesc) GET_RX_DESC_CRC32(rxdesc)
+#define GET_RX_DESC_PKT_LEN_8814A(rxdesc) GET_RX_DESC_PKT_LEN(rxdesc)
+
+/*RXDESC_WORD1*/
+
+#define GET_RX_DESC_BC_8814A(rxdesc) GET_RX_DESC_BC(rxdesc)
+#define GET_RX_DESC_MC_8814A(rxdesc) GET_RX_DESC_MC(rxdesc)
+#define GET_RX_DESC_TY_PE_8814A(rxdesc) GET_RX_DESC_TY_PE(rxdesc)
+#define GET_RX_DESC_MF_8814A(rxdesc) GET_RX_DESC_MF(rxdesc)
+#define GET_RX_DESC_MD_8814A(rxdesc) GET_RX_DESC_MD(rxdesc)
+#define GET_RX_DESC_PWR_8814A(rxdesc) GET_RX_DESC_PWR(rxdesc)
+#define GET_RX_DESC_PAM_8814A(rxdesc) GET_RX_DESC_PAM(rxdesc)
+#define GET_RX_DESC_CHK_VLD_8814A(rxdesc) GET_RX_DESC_CHK_VLD(rxdesc)
+#define GET_RX_DESC_RX_IS_TCP_UDP_8814A(rxdesc)                                \
+	GET_RX_DESC_RX_IS_TCP_UDP(rxdesc)
+#define GET_RX_DESC_RX_IPV_8814A(rxdesc) GET_RX_DESC_RX_IPV(rxdesc)
+#define GET_RX_DESC_CHKERR_8814A(rxdesc) GET_RX_DESC_CHKERR(rxdesc)
+#define GET_RX_DESC_PAGGR_8814A(rxdesc) GET_RX_DESC_PAGGR(rxdesc)
+#define GET_RX_DESC_RXID_MATCH_8814A(rxdesc) GET_RX_DESC_RXID_MATCH(rxdesc)
+#define GET_RX_DESC_AMSDU_8814A(rxdesc) GET_RX_DESC_AMSDU(rxdesc)
+#define GET_RX_DESC_MACID_VLD_8814A(rxdesc) GET_RX_DESC_MACID_VLD(rxdesc)
+#define GET_RX_DESC_TID_8814A(rxdesc) GET_RX_DESC_TID(rxdesc)
+#define GET_RX_DESC_MACID_8814A(rxdesc) GET_RX_DESC_MACID(rxdesc)
+
+/*RXDESC_WORD2*/
+
+#define GET_RX_DESC_FCS_OK_8814A(rxdesc) GET_RX_DESC_FCS_OK(rxdesc)
+#define GET_RX_DESC_C2H_8814A(rxdesc) GET_RX_DESC_C2H(rxdesc)
+#define GET_RX_DESC_HWRSVD_8814A(rxdesc) GET_RX_DESC_HWRSVD(rxdesc)
+#define GET_RX_DESC_WLANHD_IV_LEN_8814A(rxdesc)                                \
+	GET_RX_DESC_WLANHD_IV_LEN(rxdesc)
+#define GET_RX_DESC_RX_IS_QOS_8814A(rxdesc) GET_RX_DESC_RX_IS_QOS(rxdesc)
+#define GET_RX_DESC_FRAG_8814A(rxdesc) GET_RX_DESC_FRAG(rxdesc)
+#define GET_RX_DESC_SEQ_8814A(rxdesc) GET_RX_DESC_SEQ(rxdesc)
+
+/*RXDESC_WORD3*/
+
+#define GET_RX_DESC_MAGIC_WAKE_8814A(rxdesc) GET_RX_DESC_MAGIC_WAKE(rxdesc)
+#define GET_RX_DESC_UNICAST_WAKE_8814A(rxdesc) GET_RX_DESC_UNICAST_WAKE(rxdesc)
+#define GET_RX_DESC_PATTERN_MATCH_8814A(rxdesc)                                \
+	GET_RX_DESC_PATTERN_MATCH(rxdesc)
+#define GET_RX_DESC_DMA_AGG_NUM_8814A(rxdesc) GET_RX_DESC_DMA_AGG_NUM(rxdesc)
+#define GET_RX_DESC_BSSID_FIT_1_0_8814A(rxdesc)                                \
+	GET_RX_DESC_BSSID_FIT_1_0(rxdesc)
+#define GET_RX_DESC_EOSP_8814A(rxdesc) GET_RX_DESC_EOSP(rxdesc)
+#define GET_RX_DESC_HTC_8814A(rxdesc) GET_RX_DESC_HTC(rxdesc)
+#define GET_RX_DESC_BSSID_FIT_4_2_8814A(rxdesc)                                \
+	GET_RX_DESC_BSSID_FIT_4_2(rxdesc)
+#define GET_RX_DESC_RX_RATE_8814A(rxdesc) GET_RX_DESC_RX_RATE(rxdesc)
+
+/*RXDESC_WORD4*/
+
+#define GET_RX_DESC_A1_FIT_8814A(rxdesc) GET_RX_DESC_A1_FIT(rxdesc)
+#define GET_RX_DESC_MACID_RPT_BUFF_8814A(rxdesc)                               \
+	GET_RX_DESC_MACID_RPT_BUFF(rxdesc)
+#define GET_RX_DESC_RX_PRE_NDP_VLD_8814A(rxdesc)                               \
+	GET_RX_DESC_RX_PRE_NDP_VLD(rxdesc)
+#define GET_RX_DESC_RX_SCRAMBLER_8814A(rxdesc) GET_RX_DESC_RX_SCRAMBLER(rxdesc)
+#define GET_RX_DESC_RX_EOF_8814A(rxdesc) GET_RX_DESC_RX_EOF(rxdesc)
+#define GET_RX_DESC_PATTERN_IDX_8814A(rxdesc) GET_RX_DESC_PATTERN_IDX(rxdesc)
+
+/*RXDESC_WORD5*/
+
+#define GET_RX_DESC_TSFL_8814A(rxdesc) GET_RX_DESC_TSFL(rxdesc)
+
+#endif
+
+#if (HALMAC_8822B_SUPPORT)
+
+/*RXDESC_WORD0*/
+
+#define GET_RX_DESC_EOR_8822B(rxdesc) GET_RX_DESC_EOR(rxdesc)
+#define GET_RX_DESC_PHYPKTIDC_8822B(rxdesc) GET_RX_DESC_PHYPKTIDC(rxdesc)
+#define GET_RX_DESC_SWDEC_8822B(rxdesc) GET_RX_DESC_SWDEC(rxdesc)
+#define GET_RX_DESC_PHYST_8822B(rxdesc) GET_RX_DESC_PHYST(rxdesc)
+#define GET_RX_DESC_SHIFT_8822B(rxdesc) GET_RX_DESC_SHIFT(rxdesc)
+#define GET_RX_DESC_QOS_8822B(rxdesc) GET_RX_DESC_QOS(rxdesc)
+#define GET_RX_DESC_SECURITY_8822B(rxdesc) GET_RX_DESC_SECURITY(rxdesc)
+#define GET_RX_DESC_DRV_INFO_SIZE_8822B(rxdesc)                                \
+	GET_RX_DESC_DRV_INFO_SIZE(rxdesc)
+#define GET_RX_DESC_ICV_ERR_8822B(rxdesc) GET_RX_DESC_ICV_ERR(rxdesc)
+#define GET_RX_DESC_CRC32_8822B(rxdesc) GET_RX_DESC_CRC32(rxdesc)
+#define GET_RX_DESC_PKT_LEN_8822B(rxdesc) GET_RX_DESC_PKT_LEN(rxdesc)
+
+/*RXDESC_WORD1*/
+
+#define GET_RX_DESC_BC_8822B(rxdesc) GET_RX_DESC_BC(rxdesc)
+#define GET_RX_DESC_MC_8822B(rxdesc) GET_RX_DESC_MC(rxdesc)
+#define GET_RX_DESC_TY_PE_8822B(rxdesc) GET_RX_DESC_TY_PE(rxdesc)
+#define GET_RX_DESC_MF_8822B(rxdesc) GET_RX_DESC_MF(rxdesc)
+#define GET_RX_DESC_MD_8822B(rxdesc) GET_RX_DESC_MD(rxdesc)
+#define GET_RX_DESC_PWR_8822B(rxdesc) GET_RX_DESC_PWR(rxdesc)
+#define GET_RX_DESC_PAM_8822B(rxdesc) GET_RX_DESC_PAM(rxdesc)
+#define GET_RX_DESC_CHK_VLD_8822B(rxdesc) GET_RX_DESC_CHK_VLD(rxdesc)
+#define GET_RX_DESC_RX_IS_TCP_UDP_8822B(rxdesc)                                \
+	GET_RX_DESC_RX_IS_TCP_UDP(rxdesc)
+#define GET_RX_DESC_RX_IPV_8822B(rxdesc) GET_RX_DESC_RX_IPV(rxdesc)
+#define GET_RX_DESC_CHKERR_8822B(rxdesc) GET_RX_DESC_CHKERR(rxdesc)
+#define GET_RX_DESC_PAGGR_8822B(rxdesc) GET_RX_DESC_PAGGR(rxdesc)
+#define GET_RX_DESC_RXID_MATCH_8822B(rxdesc) GET_RX_DESC_RXID_MATCH(rxdesc)
+#define GET_RX_DESC_AMSDU_8822B(rxdesc) GET_RX_DESC_AMSDU(rxdesc)
+#define GET_RX_DESC_MACID_VLD_8822B(rxdesc) GET_RX_DESC_MACID_VLD(rxdesc)
+#define GET_RX_DESC_TID_8822B(rxdesc) GET_RX_DESC_TID(rxdesc)
+#define GET_RX_DESC_MACID_8822B(rxdesc) GET_RX_DESC_MACID(rxdesc)
+
+/*RXDESC_WORD2*/
+
+#define GET_RX_DESC_FCS_OK_8822B(rxdesc) GET_RX_DESC_FCS_OK(rxdesc)
+#define GET_RX_DESC_PPDU_CNT_8822B(rxdesc) GET_RX_DESC_PPDU_CNT(rxdesc)
+#define GET_RX_DESC_C2H_8822B(rxdesc) GET_RX_DESC_C2H(rxdesc)
+#define GET_RX_DESC_HWRSVD_8822B(rxdesc) GET_RX_DESC_HWRSVD(rxdesc)
+#define GET_RX_DESC_WLANHD_IV_LEN_8822B(rxdesc)                                \
+	GET_RX_DESC_WLANHD_IV_LEN(rxdesc)
+#define GET_RX_DESC_RX_IS_QOS_8822B(rxdesc) GET_RX_DESC_RX_IS_QOS(rxdesc)
+#define GET_RX_DESC_FRAG_8822B(rxdesc) GET_RX_DESC_FRAG(rxdesc)
+#define GET_RX_DESC_SEQ_8822B(rxdesc) GET_RX_DESC_SEQ(rxdesc)
+
+/*RXDESC_WORD3*/
+
+#define GET_RX_DESC_MAGIC_WAKE_8822B(rxdesc) GET_RX_DESC_MAGIC_WAKE(rxdesc)
+#define GET_RX_DESC_UNICAST_WAKE_8822B(rxdesc) GET_RX_DESC_UNICAST_WAKE(rxdesc)
+#define GET_RX_DESC_PATTERN_MATCH_8822B(rxdesc)                                \
+	GET_RX_DESC_PATTERN_MATCH(rxdesc)
+#define GET_RX_DESC_RXPAYLOAD_MATCH_8822B(rxdesc)                              \
+	GET_RX_DESC_RXPAYLOAD_MATCH(rxdesc)
+#define GET_RX_DESC_RXPAYLOAD_ID_8822B(rxdesc) GET_RX_DESC_RXPAYLOAD_ID(rxdesc)
+#define GET_RX_DESC_DMA_AGG_NUM_8822B(rxdesc) GET_RX_DESC_DMA_AGG_NUM(rxdesc)
+#define GET_RX_DESC_BSSID_FIT_1_0_8822B(rxdesc)                                \
+	GET_RX_DESC_BSSID_FIT_1_0(rxdesc)
+#define GET_RX_DESC_EOSP_8822B(rxdesc) GET_RX_DESC_EOSP(rxdesc)
+#define GET_RX_DESC_HTC_8822B(rxdesc) GET_RX_DESC_HTC(rxdesc)
+#define GET_RX_DESC_BSSID_FIT_4_2_8822B(rxdesc)                                \
+	GET_RX_DESC_BSSID_FIT_4_2(rxdesc)
+#define GET_RX_DESC_RX_RATE_8822B(rxdesc) GET_RX_DESC_RX_RATE(rxdesc)
+
+/*RXDESC_WORD4*/
+
+#define GET_RX_DESC_A1_FIT_8822B(rxdesc) GET_RX_DESC_A1_FIT(rxdesc)
+#define GET_RX_DESC_MACID_RPT_BUFF_8822B(rxdesc)                               \
+	GET_RX_DESC_MACID_RPT_BUFF(rxdesc)
+#define GET_RX_DESC_RX_PRE_NDP_VLD_8822B(rxdesc)                               \
+	GET_RX_DESC_RX_PRE_NDP_VLD(rxdesc)
+#define GET_RX_DESC_RX_SCRAMBLER_8822B(rxdesc) GET_RX_DESC_RX_SCRAMBLER(rxdesc)
+#define GET_RX_DESC_RX_EOF_8822B(rxdesc) GET_RX_DESC_RX_EOF(rxdesc)
+#define GET_RX_DESC_PATTERN_IDX_8822B(rxdesc) GET_RX_DESC_PATTERN_IDX(rxdesc)
+
+/*RXDESC_WORD5*/
+
+#define GET_RX_DESC_TSFL_8822B(rxdesc) GET_RX_DESC_TSFL(rxdesc)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT)
+
+/*RXDESC_WORD0*/
+
+#define GET_RX_DESC_EOR_8197F(rxdesc) GET_RX_DESC_EOR(rxdesc)
+#define GET_RX_DESC_PHYPKTIDC_8197F(rxdesc) GET_RX_DESC_PHYPKTIDC(rxdesc)
+#define GET_RX_DESC_SWDEC_8197F(rxdesc) GET_RX_DESC_SWDEC(rxdesc)
+#define GET_RX_DESC_PHYST_8197F(rxdesc) GET_RX_DESC_PHYST(rxdesc)
+#define GET_RX_DESC_SHIFT_8197F(rxdesc) GET_RX_DESC_SHIFT(rxdesc)
+#define GET_RX_DESC_QOS_8197F(rxdesc) GET_RX_DESC_QOS(rxdesc)
+#define GET_RX_DESC_SECURITY_8197F(rxdesc) GET_RX_DESC_SECURITY(rxdesc)
+#define GET_RX_DESC_DRV_INFO_SIZE_8197F(rxdesc)                                \
+	GET_RX_DESC_DRV_INFO_SIZE(rxdesc)
+#define GET_RX_DESC_ICV_ERR_8197F(rxdesc) GET_RX_DESC_ICV_ERR(rxdesc)
+#define GET_RX_DESC_CRC32_8197F(rxdesc) GET_RX_DESC_CRC32(rxdesc)
+#define GET_RX_DESC_PKT_LEN_8197F(rxdesc) GET_RX_DESC_PKT_LEN(rxdesc)
+
+/*RXDESC_WORD1*/
+
+#define GET_RX_DESC_BC_8197F(rxdesc) GET_RX_DESC_BC(rxdesc)
+#define GET_RX_DESC_MC_8197F(rxdesc) GET_RX_DESC_MC(rxdesc)
+#define GET_RX_DESC_TY_PE_8197F(rxdesc) GET_RX_DESC_TY_PE(rxdesc)
+#define GET_RX_DESC_MF_8197F(rxdesc) GET_RX_DESC_MF(rxdesc)
+#define GET_RX_DESC_MD_8197F(rxdesc) GET_RX_DESC_MD(rxdesc)
+#define GET_RX_DESC_PWR_8197F(rxdesc) GET_RX_DESC_PWR(rxdesc)
+#define GET_RX_DESC_PAM_8197F(rxdesc) GET_RX_DESC_PAM(rxdesc)
+#define GET_RX_DESC_CHK_VLD_8197F(rxdesc) GET_RX_DESC_CHK_VLD(rxdesc)
+#define GET_RX_DESC_RX_IS_TCP_UDP_8197F(rxdesc)                                \
+	GET_RX_DESC_RX_IS_TCP_UDP(rxdesc)
+#define GET_RX_DESC_RX_IPV_8197F(rxdesc) GET_RX_DESC_RX_IPV(rxdesc)
+#define GET_RX_DESC_CHKERR_8197F(rxdesc) GET_RX_DESC_CHKERR(rxdesc)
+#define GET_RX_DESC_PAGGR_8197F(rxdesc) GET_RX_DESC_PAGGR(rxdesc)
+#define GET_RX_DESC_RXID_MATCH_8197F(rxdesc) GET_RX_DESC_RXID_MATCH(rxdesc)
+#define GET_RX_DESC_AMSDU_8197F(rxdesc) GET_RX_DESC_AMSDU(rxdesc)
+#define GET_RX_DESC_MACID_VLD_8197F(rxdesc) GET_RX_DESC_MACID_VLD(rxdesc)
+#define GET_RX_DESC_TID_8197F(rxdesc) GET_RX_DESC_TID(rxdesc)
+#define GET_RX_DESC_MACID_8197F(rxdesc) GET_RX_DESC_MACID(rxdesc)
+
+/*RXDESC_WORD2*/
+
+#define GET_RX_DESC_FCS_OK_8197F(rxdesc) GET_RX_DESC_FCS_OK(rxdesc)
+#define GET_RX_DESC_C2H_8197F(rxdesc) GET_RX_DESC_C2H(rxdesc)
+#define GET_RX_DESC_HWRSVD_8197F(rxdesc) GET_RX_DESC_HWRSVD(rxdesc)
+#define GET_RX_DESC_WLANHD_IV_LEN_8197F(rxdesc)                                \
+	GET_RX_DESC_WLANHD_IV_LEN(rxdesc)
+#define GET_RX_DESC_RX_IS_QOS_8197F(rxdesc) GET_RX_DESC_RX_IS_QOS(rxdesc)
+#define GET_RX_DESC_FRAG_8197F(rxdesc) GET_RX_DESC_FRAG(rxdesc)
+#define GET_RX_DESC_SEQ_8197F(rxdesc) GET_RX_DESC_SEQ(rxdesc)
+
+/*RXDESC_WORD3*/
+
+#define GET_RX_DESC_MAGIC_WAKE_8197F(rxdesc) GET_RX_DESC_MAGIC_WAKE(rxdesc)
+#define GET_RX_DESC_UNICAST_WAKE_8197F(rxdesc) GET_RX_DESC_UNICAST_WAKE(rxdesc)
+#define GET_RX_DESC_PATTERN_MATCH_8197F(rxdesc)                                \
+	GET_RX_DESC_PATTERN_MATCH(rxdesc)
+#define GET_RX_DESC_DMA_AGG_NUM_8197F(rxdesc) GET_RX_DESC_DMA_AGG_NUM(rxdesc)
+#define GET_RX_DESC_BSSID_FIT_1_0_8197F(rxdesc)                                \
+	GET_RX_DESC_BSSID_FIT_1_0(rxdesc)
+#define GET_RX_DESC_EOSP_8197F(rxdesc) GET_RX_DESC_EOSP(rxdesc)
+#define GET_RX_DESC_HTC_8197F(rxdesc) GET_RX_DESC_HTC(rxdesc)
+#define GET_RX_DESC_BSSID_FIT_4_2_8197F(rxdesc)                                \
+	GET_RX_DESC_BSSID_FIT_4_2(rxdesc)
+#define GET_RX_DESC_RX_RATE_8197F(rxdesc) GET_RX_DESC_RX_RATE(rxdesc)
+
+/*RXDESC_WORD4*/
+
+#define GET_RX_DESC_A1_FIT_8197F(rxdesc) GET_RX_DESC_A1_FIT(rxdesc)
+#define GET_RX_DESC_MACID_RPT_BUFF_8197F(rxdesc)                               \
+	GET_RX_DESC_MACID_RPT_BUFF(rxdesc)
+#define GET_RX_DESC_RX_PRE_NDP_VLD_8197F(rxdesc)                               \
+	GET_RX_DESC_RX_PRE_NDP_VLD(rxdesc)
+#define GET_RX_DESC_RX_SCRAMBLER_8197F(rxdesc) GET_RX_DESC_RX_SCRAMBLER(rxdesc)
+#define GET_RX_DESC_RX_EOF_8197F(rxdesc) GET_RX_DESC_RX_EOF(rxdesc)
+#define GET_RX_DESC_FC_POWER_8197F(rxdesc) GET_RX_DESC_FC_POWER(rxdesc)
+#define GET_RX_DESC_PATTERN_IDX_8197F(rxdesc) GET_RX_DESC_PATTERN_IDX_V1(rxdesc)
+
+/*RXDESC_WORD5*/
+
+#define GET_RX_DESC_TSFL_8197F(rxdesc) GET_RX_DESC_TSFL(rxdesc)
+
+#endif
+
+#if (HALMAC_8821C_SUPPORT)
+
+/*RXDESC_WORD0*/
+
+#define GET_RX_DESC_EOR_8821C(rxdesc) GET_RX_DESC_EOR(rxdesc)
+#define GET_RX_DESC_PHYPKTIDC_8821C(rxdesc) GET_RX_DESC_PHYPKTIDC(rxdesc)
+#define GET_RX_DESC_SWDEC_8821C(rxdesc) GET_RX_DESC_SWDEC(rxdesc)
+#define GET_RX_DESC_PHYST_8821C(rxdesc) GET_RX_DESC_PHYST(rxdesc)
+#define GET_RX_DESC_SHIFT_8821C(rxdesc) GET_RX_DESC_SHIFT(rxdesc)
+#define GET_RX_DESC_QOS_8821C(rxdesc) GET_RX_DESC_QOS(rxdesc)
+#define GET_RX_DESC_SECURITY_8821C(rxdesc) GET_RX_DESC_SECURITY(rxdesc)
+#define GET_RX_DESC_DRV_INFO_SIZE_8821C(rxdesc)                                \
+	GET_RX_DESC_DRV_INFO_SIZE(rxdesc)
+#define GET_RX_DESC_ICV_ERR_8821C(rxdesc) GET_RX_DESC_ICV_ERR(rxdesc)
+#define GET_RX_DESC_CRC32_8821C(rxdesc) GET_RX_DESC_CRC32(rxdesc)
+#define GET_RX_DESC_PKT_LEN_8821C(rxdesc) GET_RX_DESC_PKT_LEN(rxdesc)
+
+/*RXDESC_WORD1*/
+
+#define GET_RX_DESC_BC_8821C(rxdesc) GET_RX_DESC_BC(rxdesc)
+#define GET_RX_DESC_MC_8821C(rxdesc) GET_RX_DESC_MC(rxdesc)
+#define GET_RX_DESC_TY_PE_8821C(rxdesc) GET_RX_DESC_TY_PE(rxdesc)
+#define GET_RX_DESC_MF_8821C(rxdesc) GET_RX_DESC_MF(rxdesc)
+#define GET_RX_DESC_MD_8821C(rxdesc) GET_RX_DESC_MD(rxdesc)
+#define GET_RX_DESC_PWR_8821C(rxdesc) GET_RX_DESC_PWR(rxdesc)
+#define GET_RX_DESC_PAM_8821C(rxdesc) GET_RX_DESC_PAM(rxdesc)
+#define GET_RX_DESC_CHK_VLD_8821C(rxdesc) GET_RX_DESC_CHK_VLD(rxdesc)
+#define GET_RX_DESC_RX_IS_TCP_UDP_8821C(rxdesc)                                \
+	GET_RX_DESC_RX_IS_TCP_UDP(rxdesc)
+#define GET_RX_DESC_RX_IPV_8821C(rxdesc) GET_RX_DESC_RX_IPV(rxdesc)
+#define GET_RX_DESC_CHKERR_8821C(rxdesc) GET_RX_DESC_CHKERR(rxdesc)
+#define GET_RX_DESC_PAGGR_8821C(rxdesc) GET_RX_DESC_PAGGR(rxdesc)
+#define GET_RX_DESC_RXID_MATCH_8821C(rxdesc) GET_RX_DESC_RXID_MATCH(rxdesc)
+#define GET_RX_DESC_AMSDU_8821C(rxdesc) GET_RX_DESC_AMSDU(rxdesc)
+#define GET_RX_DESC_MACID_VLD_8821C(rxdesc) GET_RX_DESC_MACID_VLD(rxdesc)
+#define GET_RX_DESC_TID_8821C(rxdesc) GET_RX_DESC_TID(rxdesc)
+#define GET_RX_DESC_MACID_8821C(rxdesc) GET_RX_DESC_MACID(rxdesc)
+
+/*RXDESC_WORD2*/
+
+#define GET_RX_DESC_FCS_OK_8821C(rxdesc) GET_RX_DESC_FCS_OK(rxdesc)
+#define GET_RX_DESC_PPDU_CNT_8821C(rxdesc) GET_RX_DESC_PPDU_CNT(rxdesc)
+#define GET_RX_DESC_C2H_8821C(rxdesc) GET_RX_DESC_C2H(rxdesc)
+#define GET_RX_DESC_HWRSVD_8821C(rxdesc) GET_RX_DESC_HWRSVD(rxdesc)
+#define GET_RX_DESC_WLANHD_IV_LEN_8821C(rxdesc)                                \
+	GET_RX_DESC_WLANHD_IV_LEN(rxdesc)
+#define GET_RX_DESC_RX_IS_QOS_8821C(rxdesc) GET_RX_DESC_RX_IS_QOS(rxdesc)
+#define GET_RX_DESC_FRAG_8821C(rxdesc) GET_RX_DESC_FRAG(rxdesc)
+#define GET_RX_DESC_SEQ_8821C(rxdesc) GET_RX_DESC_SEQ(rxdesc)
+
+/*RXDESC_WORD3*/
+
+#define GET_RX_DESC_MAGIC_WAKE_8821C(rxdesc) GET_RX_DESC_MAGIC_WAKE(rxdesc)
+#define GET_RX_DESC_UNICAST_WAKE_8821C(rxdesc) GET_RX_DESC_UNICAST_WAKE(rxdesc)
+#define GET_RX_DESC_PATTERN_MATCH_8821C(rxdesc)                                \
+	GET_RX_DESC_PATTERN_MATCH(rxdesc)
+#define GET_RX_DESC_RXPAYLOAD_MATCH_8821C(rxdesc)                              \
+	GET_RX_DESC_RXPAYLOAD_MATCH(rxdesc)
+#define GET_RX_DESC_RXPAYLOAD_ID_8821C(rxdesc) GET_RX_DESC_RXPAYLOAD_ID(rxdesc)
+#define GET_RX_DESC_DMA_AGG_NUM_8821C(rxdesc) GET_RX_DESC_DMA_AGG_NUM(rxdesc)
+#define GET_RX_DESC_BSSID_FIT_1_0_8821C(rxdesc)                                \
+	GET_RX_DESC_BSSID_FIT_1_0(rxdesc)
+#define GET_RX_DESC_EOSP_8821C(rxdesc) GET_RX_DESC_EOSP(rxdesc)
+#define GET_RX_DESC_HTC_8821C(rxdesc) GET_RX_DESC_HTC(rxdesc)
+#define GET_RX_DESC_BSSID_FIT_4_2_8821C(rxdesc)                                \
+	GET_RX_DESC_BSSID_FIT_4_2(rxdesc)
+#define GET_RX_DESC_RX_RATE_8821C(rxdesc) GET_RX_DESC_RX_RATE(rxdesc)
+
+/*RXDESC_WORD4*/
+
+#define GET_RX_DESC_A1_FIT_8821C(rxdesc) GET_RX_DESC_A1_FIT(rxdesc)
+#define GET_RX_DESC_MACID_RPT_BUFF_8821C(rxdesc)                               \
+	GET_RX_DESC_MACID_RPT_BUFF(rxdesc)
+#define GET_RX_DESC_RX_PRE_NDP_VLD_8821C(rxdesc)                               \
+	GET_RX_DESC_RX_PRE_NDP_VLD(rxdesc)
+#define GET_RX_DESC_RX_SCRAMBLER_8821C(rxdesc) GET_RX_DESC_RX_SCRAMBLER(rxdesc)
+#define GET_RX_DESC_RX_EOF_8821C(rxdesc) GET_RX_DESC_RX_EOF(rxdesc)
+#define GET_RX_DESC_PATTERN_IDX_8821C(rxdesc) GET_RX_DESC_PATTERN_IDX(rxdesc)
+
+/*RXDESC_WORD5*/
+
+#define GET_RX_DESC_TSFL_8821C(rxdesc) GET_RX_DESC_TSFL(rxdesc)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/*RXDESC_WORD0*/
+
+#define GET_RX_DESC_EVT_PKT_8814B(rxdesc) GET_RX_DESC_EVT_PKT(rxdesc)
+#define GET_RX_DESC_SWDEC_8814B(rxdesc) GET_RX_DESC_SWDEC(rxdesc)
+#define GET_RX_DESC_PHYST_8814B(rxdesc) GET_RX_DESC_PHYST(rxdesc)
+#define GET_RX_DESC_SHIFT_8814B(rxdesc) GET_RX_DESC_SHIFT(rxdesc)
+#define GET_RX_DESC_QOS_8814B(rxdesc) GET_RX_DESC_QOS(rxdesc)
+#define GET_RX_DESC_SECURITY_8814B(rxdesc) GET_RX_DESC_SECURITY(rxdesc)
+#define GET_RX_DESC_DRV_INFO_SIZE_8814B(rxdesc)                                \
+	GET_RX_DESC_DRV_INFO_SIZE(rxdesc)
+#define GET_RX_DESC_ICV_ERR_8814B(rxdesc) GET_RX_DESC_ICV_ERR(rxdesc)
+#define GET_RX_DESC_CRC32_8814B(rxdesc) GET_RX_DESC_CRC32(rxdesc)
+#define GET_RX_DESC_PKT_LEN_8814B(rxdesc) GET_RX_DESC_PKT_LEN(rxdesc)
+
+/*RXDESC_WORD1*/
+
+#define GET_RX_DESC_BC_8814B(rxdesc) GET_RX_DESC_BC(rxdesc)
+#define GET_RX_DESC_MC_8814B(rxdesc) GET_RX_DESC_MC(rxdesc)
+#define GET_RX_DESC_TYPE_8814B(rxdesc) GET_RX_DESC_TYPE(rxdesc)
+#define GET_RX_DESC_MF_8814B(rxdesc) GET_RX_DESC_MF(rxdesc)
+#define GET_RX_DESC_MD_8814B(rxdesc) GET_RX_DESC_MD(rxdesc)
+#define GET_RX_DESC_PWR_8814B(rxdesc) GET_RX_DESC_PWR(rxdesc)
+#define GET_RX_DESC_A1_MATCH_8814B(rxdesc) GET_RX_DESC_A1_MATCH(rxdesc)
+#define GET_RX_DESC_TCP_CHKSUM_VLD_8814B(rxdesc)                               \
+	GET_RX_DESC_TCP_CHKSUM_VLD(rxdesc)
+#define GET_RX_DESC_RX_IS_TCP_UDP_8814B(rxdesc)                                \
+	GET_RX_DESC_RX_IS_TCP_UDP(rxdesc)
+#define GET_RX_DESC_RX_IPV_8814B(rxdesc) GET_RX_DESC_RX_IPV(rxdesc)
+#define GET_RX_DESC_TCP_CHKSUM_ERR_8814B(rxdesc)                               \
+	GET_RX_DESC_TCP_CHKSUM_ERR(rxdesc)
+#define GET_RX_DESC_PHY_PKT_IDC_8814B(rxdesc) GET_RX_DESC_PHY_PKT_IDC(rxdesc)
+#define GET_RX_DESC_FW_FIFO_FULL_8814B(rxdesc) GET_RX_DESC_FW_FIFO_FULL(rxdesc)
+#define GET_RX_DESC_AMPDU_8814B(rxdesc) GET_RX_DESC_AMPDU(rxdesc)
+#define GET_RX_DESC_RXCMD_IDC_8814B(rxdesc) GET_RX_DESC_RXCMD_IDC(rxdesc)
+#define GET_RX_DESC_AMSDU_8814B(rxdesc) GET_RX_DESC_AMSDU(rxdesc)
+#define GET_RX_DESC_TID_8814B(rxdesc) GET_RX_DESC_TID(rxdesc)
+
+/*RXDESC_WORD2*/
+
+#define GET_RX_DESC_AMSDU_CUT_8814B(rxdesc) GET_RX_DESC_AMSDU_CUT(rxdesc)
+#define GET_RX_DESC_PPDU_CNT_8814B(rxdesc) GET_RX_DESC_PPDU_CNT(rxdesc)
+#define GET_RX_DESC_C2H_8814B(rxdesc) GET_RX_DESC_C2H(rxdesc)
+#define GET_RX_DESC_WLANHD_IV_LEN_8814B(rxdesc)                                \
+	GET_RX_DESC_WLANHD_IV_LEN(rxdesc)
+#define GET_RX_DESC_LAST_MSDU_8814B(rxdesc) GET_RX_DESC_LAST_MSDU(rxdesc)
+#define GET_RX_DESC_EXT_SEC_TYPE_8814B(rxdesc) GET_RX_DESC_EXT_SEC_TYPE(rxdesc)
+#define GET_RX_DESC_FRAG_8814B(rxdesc) GET_RX_DESC_FRAG(rxdesc)
+#define GET_RX_DESC_SEQ_8814B(rxdesc) GET_RX_DESC_SEQ(rxdesc)
+
+/*RXDESC_WORD3*/
+
+#define GET_RX_DESC_MAGIC_WAKE_8814B(rxdesc) GET_RX_DESC_MAGIC_WAKE(rxdesc)
+#define GET_RX_DESC_UNICAST_WAKE_8814B(rxdesc) GET_RX_DESC_UNICAST_WAKE(rxdesc)
+#define GET_RX_DESC_PATTERN_WAKE_8814B(rxdesc) GET_RX_DESC_PATTERN_WAKE(rxdesc)
+#define GET_RX_DESC_RXPAYLOAD_MATCH_8814B(rxdesc)                              \
+	GET_RX_DESC_RXPAYLOAD_MATCH(rxdesc)
+#define GET_RX_DESC_RXPAYLOAD_ID_8814B(rxdesc) GET_RX_DESC_RXPAYLOAD_ID(rxdesc)
+#define GET_RX_DESC_DMA_AGG_NUM_8814B(rxdesc) GET_RX_DESC_DMA_AGG_NUM(rxdesc)
+#define GET_RX_DESC_BSSID_FIT_8814B(rxdesc) GET_RX_DESC_BSSID_FIT(rxdesc)
+#define GET_RX_DESC_HTC_8814B(rxdesc) GET_RX_DESC_HTC(rxdesc)
+#define GET_RX_DESC_AMPDU_END_PKT_8814B(rxdesc)                                \
+	GET_RX_DESC_AMPDU_END_PKT(rxdesc)
+#define GET_RX_DESC_ADDRESS_CAM_VLD_8814B(rxdesc)                              \
+	GET_RX_DESC_ADDRESS_CAM_VLD(rxdesc)
+#define GET_RX_DESC_EOSP_8814B(rxdesc) GET_RX_DESC_EOSP_V1(rxdesc)
+#define GET_RX_DESC_RX_RATE_8814B(rxdesc) GET_RX_DESC_RX_RATE(rxdesc)
+
+/*RXDESC_WORD4*/
+
+#define GET_RX_DESC_ADDRESS_CAM_8814B(rxdesc) GET_RX_DESC_ADDRESS_CAM(rxdesc)
+#define GET_RX_DESC_MACID_VLD_8814B(rxdesc) GET_RX_DESC_MACID_VLD_V1(rxdesc)
+#define GET_RX_DESC_MACID_8814B(rxdesc) GET_RX_DESC_MACID_V1(rxdesc)
+#define GET_RX_DESC_SWPS_RPT_8814B(rxdesc) GET_RX_DESC_SWPS_RPT(rxdesc)
+#define GET_RX_DESC_PATTERN_IDX_8814B(rxdesc) GET_RX_DESC_PATTERN_IDX_V2(rxdesc)
+
+/*RXDESC_WORD5*/
+
+#define GET_RX_DESC_FREERUN_CNT_8814B(rxdesc) GET_RX_DESC_FREERUN_CNT(rxdesc)
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+/*RXDESC_WORD0*/
+
+#define GET_RX_DESC_EOR_8198F(rxdesc) GET_RX_DESC_EOR(rxdesc)
+#define GET_RX_DESC_PHYPKTIDC_8198F(rxdesc) GET_RX_DESC_PHYPKTIDC(rxdesc)
+#define GET_RX_DESC_SWDEC_8198F(rxdesc) GET_RX_DESC_SWDEC(rxdesc)
+#define GET_RX_DESC_PHYST_8198F(rxdesc) GET_RX_DESC_PHYST(rxdesc)
+#define GET_RX_DESC_SHIFT_8198F(rxdesc) GET_RX_DESC_SHIFT(rxdesc)
+#define GET_RX_DESC_QOS_8198F(rxdesc) GET_RX_DESC_QOS(rxdesc)
+#define GET_RX_DESC_SECURITY_8198F(rxdesc) GET_RX_DESC_SECURITY(rxdesc)
+#define GET_RX_DESC_DRV_INFO_SIZE_8198F(rxdesc)                                \
+	GET_RX_DESC_DRV_INFO_SIZE(rxdesc)
+#define GET_RX_DESC_ICV_ERR_8198F(rxdesc) GET_RX_DESC_ICV_ERR(rxdesc)
+#define GET_RX_DESC_CRC32_8198F(rxdesc) GET_RX_DESC_CRC32(rxdesc)
+#define GET_RX_DESC_PKT_LEN_8198F(rxdesc) GET_RX_DESC_PKT_LEN(rxdesc)
+
+/*RXDESC_WORD1*/
+
+#define GET_RX_DESC_BC_8198F(rxdesc) GET_RX_DESC_BC(rxdesc)
+#define GET_RX_DESC_MC_8198F(rxdesc) GET_RX_DESC_MC(rxdesc)
+#define GET_RX_DESC_TY_PE_8198F(rxdesc) GET_RX_DESC_TY_PE(rxdesc)
+#define GET_RX_DESC_MF_8198F(rxdesc) GET_RX_DESC_MF(rxdesc)
+#define GET_RX_DESC_MD_8198F(rxdesc) GET_RX_DESC_MD(rxdesc)
+#define GET_RX_DESC_PWR_8198F(rxdesc) GET_RX_DESC_PWR(rxdesc)
+#define GET_RX_DESC_PAM_8198F(rxdesc) GET_RX_DESC_PAM(rxdesc)
+#define GET_RX_DESC_CHK_VLD_8198F(rxdesc) GET_RX_DESC_CHK_VLD(rxdesc)
+#define GET_RX_DESC_RX_IS_TCP_UDP_8198F(rxdesc)                                \
+	GET_RX_DESC_RX_IS_TCP_UDP(rxdesc)
+#define GET_RX_DESC_RX_IPV_8198F(rxdesc) GET_RX_DESC_RX_IPV(rxdesc)
+#define GET_RX_DESC_CHKERR_8198F(rxdesc) GET_RX_DESC_CHKERR(rxdesc)
+#define GET_RX_DESC_PAGGR_8198F(rxdesc) GET_RX_DESC_PAGGR(rxdesc)
+#define GET_RX_DESC_RXID_MATCH_8198F(rxdesc) GET_RX_DESC_RXID_MATCH(rxdesc)
+#define GET_RX_DESC_AMSDU_8198F(rxdesc) GET_RX_DESC_AMSDU(rxdesc)
+#define GET_RX_DESC_MACID_VLD_8198F(rxdesc) GET_RX_DESC_MACID_VLD(rxdesc)
+#define GET_RX_DESC_TID_8198F(rxdesc) GET_RX_DESC_TID(rxdesc)
+#define GET_RX_DESC_MACID_8198F(rxdesc) GET_RX_DESC_MACID(rxdesc)
+
+/*RXDESC_WORD2*/
+
+#define GET_RX_DESC_FCS_OK_8198F(rxdesc) GET_RX_DESC_FCS_OK(rxdesc)
+#define GET_RX_DESC_PPDU_CNT_8198F(rxdesc) GET_RX_DESC_PPDU_CNT(rxdesc)
+#define GET_RX_DESC_C2H_8198F(rxdesc) GET_RX_DESC_C2H(rxdesc)
+#define GET_RX_DESC_HWRSVD_8198F(rxdesc) GET_RX_DESC_HWRSVD_V1(rxdesc)
+#define GET_RX_DESC_RXMAGPKT_8198F(rxdesc) GET_RX_DESC_RXMAGPKT(rxdesc)
+#define GET_RX_DESC_WLANHD_IV_LEN_8198F(rxdesc)                                \
+	GET_RX_DESC_WLANHD_IV_LEN(rxdesc)
+#define GET_RX_DESC_RX_IS_QOS_8198F(rxdesc) GET_RX_DESC_RX_IS_QOS(rxdesc)
+#define GET_RX_DESC_FRAG_8198F(rxdesc) GET_RX_DESC_FRAG(rxdesc)
+#define GET_RX_DESC_SEQ_8198F(rxdesc) GET_RX_DESC_SEQ(rxdesc)
+
+/*RXDESC_WORD3*/
+
+#define GET_RX_DESC_MAGIC_WAKE_8198F(rxdesc) GET_RX_DESC_MAGIC_WAKE(rxdesc)
+#define GET_RX_DESC_UNICAST_WAKE_8198F(rxdesc) GET_RX_DESC_UNICAST_WAKE(rxdesc)
+#define GET_RX_DESC_PATTERN_MATCH_8198F(rxdesc)                                \
+	GET_RX_DESC_PATTERN_MATCH(rxdesc)
+#define GET_RX_DESC_RXPAYLOAD_MATCH_8198F(rxdesc)                              \
+	GET_RX_DESC_RXPAYLOAD_MATCH(rxdesc)
+#define GET_RX_DESC_RXPAYLOAD_ID_8198F(rxdesc) GET_RX_DESC_RXPAYLOAD_ID(rxdesc)
+#define GET_RX_DESC_DMA_AGG_NUM_8198F(rxdesc) GET_RX_DESC_DMA_AGG_NUM(rxdesc)
+#define GET_RX_DESC_BSSID_FIT_1_0_8198F(rxdesc)                                \
+	GET_RX_DESC_BSSID_FIT_1_0(rxdesc)
+#define GET_RX_DESC_EOSP_8198F(rxdesc) GET_RX_DESC_EOSP(rxdesc)
+#define GET_RX_DESC_HTC_8198F(rxdesc) GET_RX_DESC_HTC(rxdesc)
+#define GET_RX_DESC_BSSID_FIT_4_2_8198F(rxdesc)                                \
+	GET_RX_DESC_BSSID_FIT_4_2(rxdesc)
+#define GET_RX_DESC_RX_RATE_8198F(rxdesc) GET_RX_DESC_RX_RATE(rxdesc)
+
+/*RXDESC_WORD4*/
+
+#define GET_RX_DESC_A1_FIT_A1_8198F(rxdesc) GET_RX_DESC_A1_FIT_A1(rxdesc)
+#define GET_RX_DESC_MACID_RPT_BUFF_8198F(rxdesc)                               \
+	GET_RX_DESC_MACID_RPT_BUFF(rxdesc)
+#define GET_RX_DESC_RX_PRE_NDP_VLD_8198F(rxdesc)                               \
+	GET_RX_DESC_RX_PRE_NDP_VLD(rxdesc)
+#define GET_RX_DESC_RX_SCRAMBLER_8198F(rxdesc) GET_RX_DESC_RX_SCRAMBLER(rxdesc)
+#define GET_RX_DESC_RX_EOF_8198F(rxdesc) GET_RX_DESC_RX_EOF(rxdesc)
+#define GET_RX_DESC_FC_POWER_8198F(rxdesc) GET_RX_DESC_FC_POWER(rxdesc)
+#define GET_RX_DESC_TXRPTMID_CTL_MASK_8198F(rxdesc)                            \
+	GET_RX_DESC_TXRPTMID_CTL_MASK(rxdesc)
+#define GET_RX_DESC_SWPS_RPT_8198F(rxdesc) GET_RX_DESC_SWPS_RPT(rxdesc)
+#define GET_RX_DESC_PATTERN_IDX_8198F(rxdesc) GET_RX_DESC_PATTERN_IDX_V1(rxdesc)
+
+/*RXDESC_WORD5*/
+
+#define GET_RX_DESC_TSFL_8198F(rxdesc) GET_RX_DESC_TSFL(rxdesc)
+
+#endif
+
+#if (HALMAC_8822C_SUPPORT)
+
+/*RXDESC_WORD0*/
+
+#define GET_RX_DESC_EOR_8822C(rxdesc) GET_RX_DESC_EOR(rxdesc)
+#define GET_RX_DESC_PHYPKTIDC_8822C(rxdesc) GET_RX_DESC_PHYPKTIDC(rxdesc)
+#define GET_RX_DESC_SWDEC_8822C(rxdesc) GET_RX_DESC_SWDEC(rxdesc)
+#define GET_RX_DESC_PHYST_8822C(rxdesc) GET_RX_DESC_PHYST(rxdesc)
+#define GET_RX_DESC_SHIFT_8822C(rxdesc) GET_RX_DESC_SHIFT(rxdesc)
+#define GET_RX_DESC_QOS_8822C(rxdesc) GET_RX_DESC_QOS(rxdesc)
+#define GET_RX_DESC_SECURITY_8822C(rxdesc) GET_RX_DESC_SECURITY(rxdesc)
+#define GET_RX_DESC_DRV_INFO_SIZE_8822C(rxdesc)                                \
+	GET_RX_DESC_DRV_INFO_SIZE(rxdesc)
+#define GET_RX_DESC_ICV_ERR_8822C(rxdesc) GET_RX_DESC_ICV_ERR(rxdesc)
+#define GET_RX_DESC_CRC32_8822C(rxdesc) GET_RX_DESC_CRC32(rxdesc)
+#define GET_RX_DESC_PKT_LEN_8822C(rxdesc) GET_RX_DESC_PKT_LEN(rxdesc)
+
+/*RXDESC_WORD1*/
+
+#define GET_RX_DESC_BC_8822C(rxdesc) GET_RX_DESC_BC(rxdesc)
+#define GET_RX_DESC_MC_8822C(rxdesc) GET_RX_DESC_MC(rxdesc)
+#define GET_RX_DESC_TY_PE_8822C(rxdesc) GET_RX_DESC_TY_PE(rxdesc)
+#define GET_RX_DESC_MF_8822C(rxdesc) GET_RX_DESC_MF(rxdesc)
+#define GET_RX_DESC_MD_8822C(rxdesc) GET_RX_DESC_MD(rxdesc)
+#define GET_RX_DESC_PWR_8822C(rxdesc) GET_RX_DESC_PWR(rxdesc)
+#define GET_RX_DESC_PAM_8822C(rxdesc) GET_RX_DESC_PAM(rxdesc)
+#define GET_RX_DESC_CHK_VLD_8822C(rxdesc) GET_RX_DESC_CHK_VLD(rxdesc)
+#define GET_RX_DESC_RX_IS_TCP_UDP_8822C(rxdesc)                                \
+	GET_RX_DESC_RX_IS_TCP_UDP(rxdesc)
+#define GET_RX_DESC_RX_IPV_8822C(rxdesc) GET_RX_DESC_RX_IPV(rxdesc)
+#define GET_RX_DESC_CHKERR_8822C(rxdesc) GET_RX_DESC_CHKERR(rxdesc)
+#define GET_RX_DESC_PAGGR_8822C(rxdesc) GET_RX_DESC_PAGGR(rxdesc)
+#define GET_RX_DESC_RXID_MATCH_8822C(rxdesc) GET_RX_DESC_RXID_MATCH(rxdesc)
+#define GET_RX_DESC_AMSDU_8822C(rxdesc) GET_RX_DESC_AMSDU(rxdesc)
+#define GET_RX_DESC_MACID_VLD_8822C(rxdesc) GET_RX_DESC_MACID_VLD(rxdesc)
+#define GET_RX_DESC_TID_8822C(rxdesc) GET_RX_DESC_TID(rxdesc)
+#define GET_RX_DESC_MACID_8822C(rxdesc) GET_RX_DESC_MACID(rxdesc)
+
+/*RXDESC_WORD2*/
+
+#define GET_RX_DESC_FCS_OK_8822C(rxdesc) GET_RX_DESC_FCS_OK(rxdesc)
+#define GET_RX_DESC_PPDU_CNT_8822C(rxdesc) GET_RX_DESC_PPDU_CNT(rxdesc)
+#define GET_RX_DESC_C2H_8822C(rxdesc) GET_RX_DESC_C2H(rxdesc)
+#define GET_RX_DESC_HWRSVD_8822C(rxdesc) GET_RX_DESC_HWRSVD(rxdesc)
+#define GET_RX_DESC_WLANHD_IV_LEN_8822C(rxdesc)                                \
+	GET_RX_DESC_WLANHD_IV_LEN(rxdesc)
+#define GET_RX_DESC_RX_STATISTICS_8822C(rxdesc)                                \
+	GET_RX_DESC_RX_STATISTICS(rxdesc)
+#define GET_RX_DESC_RX_IS_QOS_8822C(rxdesc) GET_RX_DESC_RX_IS_QOS(rxdesc)
+#define GET_RX_DESC_FRAG_8822C(rxdesc) GET_RX_DESC_FRAG(rxdesc)
+#define GET_RX_DESC_SEQ_8822C(rxdesc) GET_RX_DESC_SEQ(rxdesc)
+
+/*RXDESC_WORD3*/
+
+#define GET_RX_DESC_MAGIC_WAKE_8822C(rxdesc) GET_RX_DESC_MAGIC_WAKE(rxdesc)
+#define GET_RX_DESC_UNICAST_WAKE_8822C(rxdesc) GET_RX_DESC_UNICAST_WAKE(rxdesc)
+#define GET_RX_DESC_PATTERN_MATCH_8822C(rxdesc)                                \
+	GET_RX_DESC_PATTERN_MATCH(rxdesc)
+#define GET_RX_DESC_RXPAYLOAD_MATCH_8822C(rxdesc)                              \
+	GET_RX_DESC_RXPAYLOAD_MATCH(rxdesc)
+#define GET_RX_DESC_RXPAYLOAD_ID_8822C(rxdesc) GET_RX_DESC_RXPAYLOAD_ID(rxdesc)
+#define GET_RX_DESC_DMA_AGG_NUM_8822C(rxdesc) GET_RX_DESC_DMA_AGG_NUM(rxdesc)
+#define GET_RX_DESC_BSSID_FIT_1_0_8822C(rxdesc)                                \
+	GET_RX_DESC_BSSID_FIT_1_0(rxdesc)
+#define GET_RX_DESC_EOSP_8822C(rxdesc) GET_RX_DESC_EOSP(rxdesc)
+#define GET_RX_DESC_HTC_8822C(rxdesc) GET_RX_DESC_HTC(rxdesc)
+#define GET_RX_DESC_BSSID_FIT_4_2_8822C(rxdesc)                                \
+	GET_RX_DESC_BSSID_FIT_4_2(rxdesc)
+#define GET_RX_DESC_RX_RATE_8822C(rxdesc) GET_RX_DESC_RX_RATE(rxdesc)
+
+/*RXDESC_WORD4*/
+
+#define GET_RX_DESC_A1_FIT_8822C(rxdesc) GET_RX_DESC_A1_FIT(rxdesc)
+#define GET_RX_DESC_MACID_RPT_BUFF_8822C(rxdesc)                               \
+	GET_RX_DESC_MACID_RPT_BUFF(rxdesc)
+#define GET_RX_DESC_RX_PRE_NDP_VLD_8822C(rxdesc)                               \
+	GET_RX_DESC_RX_PRE_NDP_VLD(rxdesc)
+#define GET_RX_DESC_RX_SCRAMBLER_8822C(rxdesc) GET_RX_DESC_RX_SCRAMBLER(rxdesc)
+#define GET_RX_DESC_RX_EOF_8822C(rxdesc) GET_RX_DESC_RX_EOF(rxdesc)
+#define GET_RX_DESC_PATTERN_IDX_8822C(rxdesc) GET_RX_DESC_PATTERN_IDX(rxdesc)
+
+/*RXDESC_WORD5*/
+
+#define GET_RX_DESC_TSFL_8822C(rxdesc) GET_RX_DESC_TSFL(rxdesc)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT)
+
+/*RXDESC_WORD0*/
+
+#define GET_RX_DESC_EOR_8812F(rxdesc) GET_RX_DESC_EOR(rxdesc)
+#define GET_RX_DESC_PHYPKTIDC_8812F(rxdesc) GET_RX_DESC_PHYPKTIDC(rxdesc)
+#define GET_RX_DESC_SWDEC_8812F(rxdesc) GET_RX_DESC_SWDEC(rxdesc)
+#define GET_RX_DESC_PHYST_8812F(rxdesc) GET_RX_DESC_PHYST(rxdesc)
+#define GET_RX_DESC_SHIFT_8812F(rxdesc) GET_RX_DESC_SHIFT(rxdesc)
+#define GET_RX_DESC_QOS_8812F(rxdesc) GET_RX_DESC_QOS(rxdesc)
+#define GET_RX_DESC_SECURITY_8812F(rxdesc) GET_RX_DESC_SECURITY(rxdesc)
+#define GET_RX_DESC_DRV_INFO_SIZE_8812F(rxdesc)                                \
+	GET_RX_DESC_DRV_INFO_SIZE(rxdesc)
+#define GET_RX_DESC_ICV_ERR_8812F(rxdesc) GET_RX_DESC_ICV_ERR(rxdesc)
+#define GET_RX_DESC_CRC32_8812F(rxdesc) GET_RX_DESC_CRC32(rxdesc)
+#define GET_RX_DESC_PKT_LEN_8812F(rxdesc) GET_RX_DESC_PKT_LEN(rxdesc)
+
+/*RXDESC_WORD1*/
+
+#define GET_RX_DESC_BC_8812F(rxdesc) GET_RX_DESC_BC(rxdesc)
+#define GET_RX_DESC_MC_8812F(rxdesc) GET_RX_DESC_MC(rxdesc)
+#define GET_RX_DESC_TY_PE_8812F(rxdesc) GET_RX_DESC_TY_PE(rxdesc)
+#define GET_RX_DESC_MF_8812F(rxdesc) GET_RX_DESC_MF(rxdesc)
+#define GET_RX_DESC_MD_8812F(rxdesc) GET_RX_DESC_MD(rxdesc)
+#define GET_RX_DESC_PWR_8812F(rxdesc) GET_RX_DESC_PWR(rxdesc)
+#define GET_RX_DESC_PAM_8812F(rxdesc) GET_RX_DESC_PAM(rxdesc)
+#define GET_RX_DESC_CHK_VLD_8812F(rxdesc) GET_RX_DESC_CHK_VLD(rxdesc)
+#define GET_RX_DESC_RX_IS_TCP_UDP_8812F(rxdesc)                                \
+	GET_RX_DESC_RX_IS_TCP_UDP(rxdesc)
+#define GET_RX_DESC_RX_IPV_8812F(rxdesc) GET_RX_DESC_RX_IPV(rxdesc)
+#define GET_RX_DESC_CHKERR_8812F(rxdesc) GET_RX_DESC_CHKERR(rxdesc)
+#define GET_RX_DESC_PAGGR_8812F(rxdesc) GET_RX_DESC_PAGGR(rxdesc)
+#define GET_RX_DESC_RXID_MATCH_8812F(rxdesc) GET_RX_DESC_RXID_MATCH(rxdesc)
+#define GET_RX_DESC_AMSDU_8812F(rxdesc) GET_RX_DESC_AMSDU(rxdesc)
+#define GET_RX_DESC_MACID_VLD_8812F(rxdesc) GET_RX_DESC_MACID_VLD(rxdesc)
+#define GET_RX_DESC_TID_8812F(rxdesc) GET_RX_DESC_TID(rxdesc)
+#define GET_RX_DESC_MACID_8812F(rxdesc) GET_RX_DESC_MACID(rxdesc)
+
+/*RXDESC_WORD2*/
+
+#define GET_RX_DESC_FCS_OK_8812F(rxdesc) GET_RX_DESC_FCS_OK(rxdesc)
+#define GET_RX_DESC_PPDU_CNT_8812F(rxdesc) GET_RX_DESC_PPDU_CNT(rxdesc)
+#define GET_RX_DESC_C2H_8812F(rxdesc) GET_RX_DESC_C2H(rxdesc)
+#define GET_RX_DESC_HWRSVD_8812F(rxdesc) GET_RX_DESC_HWRSVD(rxdesc)
+#define GET_RX_DESC_WLANHD_IV_LEN_8812F(rxdesc)                                \
+	GET_RX_DESC_WLANHD_IV_LEN(rxdesc)
+#define GET_RX_DESC_RX_STATISTICS_8812F(rxdesc)                                \
+	GET_RX_DESC_RX_STATISTICS(rxdesc)
+#define GET_RX_DESC_RX_IS_QOS_8812F(rxdesc) GET_RX_DESC_RX_IS_QOS(rxdesc)
+#define GET_RX_DESC_FRAG_8812F(rxdesc) GET_RX_DESC_FRAG(rxdesc)
+#define GET_RX_DESC_SEQ_8812F(rxdesc) GET_RX_DESC_SEQ(rxdesc)
+
+/*RXDESC_WORD3*/
+
+#define GET_RX_DESC_MAGIC_WAKE_8812F(rxdesc) GET_RX_DESC_MAGIC_WAKE(rxdesc)
+#define GET_RX_DESC_UNICAST_WAKE_8812F(rxdesc) GET_RX_DESC_UNICAST_WAKE(rxdesc)
+#define GET_RX_DESC_PATTERN_MATCH_8812F(rxdesc)                                \
+	GET_RX_DESC_PATTERN_MATCH(rxdesc)
+#define GET_RX_DESC_RXPAYLOAD_MATCH_8812F(rxdesc)                              \
+	GET_RX_DESC_RXPAYLOAD_MATCH(rxdesc)
+#define GET_RX_DESC_RXPAYLOAD_ID_8812F(rxdesc) GET_RX_DESC_RXPAYLOAD_ID(rxdesc)
+#define GET_RX_DESC_DMA_AGG_NUM_8812F(rxdesc) GET_RX_DESC_DMA_AGG_NUM(rxdesc)
+#define GET_RX_DESC_BSSID_FIT_1_0_8812F(rxdesc)                                \
+	GET_RX_DESC_BSSID_FIT_1_0(rxdesc)
+#define GET_RX_DESC_EOSP_8812F(rxdesc) GET_RX_DESC_EOSP(rxdesc)
+#define GET_RX_DESC_HTC_8812F(rxdesc) GET_RX_DESC_HTC(rxdesc)
+#define GET_RX_DESC_BSSID_FIT_4_2_8812F(rxdesc)                                \
+	GET_RX_DESC_BSSID_FIT_4_2(rxdesc)
+#define GET_RX_DESC_RX_RATE_8812F(rxdesc) GET_RX_DESC_RX_RATE(rxdesc)
+
+/*RXDESC_WORD4*/
+
+#define GET_RX_DESC_A1_FIT_8812F(rxdesc) GET_RX_DESC_A1_FIT(rxdesc)
+#define GET_RX_DESC_MACID_RPT_BUFF_8812F(rxdesc)                               \
+	GET_RX_DESC_MACID_RPT_BUFF(rxdesc)
+#define GET_RX_DESC_RX_PRE_NDP_VLD_8812F(rxdesc)                               \
+	GET_RX_DESC_RX_PRE_NDP_VLD(rxdesc)
+#define GET_RX_DESC_RX_SCRAMBLER_8812F(rxdesc) GET_RX_DESC_RX_SCRAMBLER(rxdesc)
+#define GET_RX_DESC_RX_EOF_8812F(rxdesc) GET_RX_DESC_RX_EOF(rxdesc)
+#define GET_RX_DESC_PATTERN_IDX_8812F(rxdesc) GET_RX_DESC_PATTERN_IDX(rxdesc)
+
+/*RXDESC_WORD5*/
+
+#define GET_RX_DESC_TSFL_8812F(rxdesc) GET_RX_DESC_TSFL(rxdesc)
+
+#endif
+
+#endif
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/halmac/halmac_rx_desc_nic.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/halmac/halmac_rx_desc_nic.h
--- linux-5.6.3/3rdparty/rtl8821ce/hal/halmac/halmac_rx_desc_nic.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/halmac/halmac_rx_desc_nic.h	2020-04-10 16:35:06.816660067 +0300
@@ -0,0 +1,478 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ ******************************************************************************/
+
+#ifndef _HALMAC_RX_DESC_NIC_H_
+#define _HALMAC_RX_DESC_NIC_H_
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT)
+
+/*RXDESC_WORD0*/
+
+#define GET_RX_DESC_EOR(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x00, 30, 1)
+#define GET_RX_DESC_PHYPKTIDC(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x00, 28, 1)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define GET_RX_DESC_EVT_PKT(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x00, 28, 1)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT || HALMAC_8812F_SUPPORT)
+
+#define GET_RX_DESC_SWDEC(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x00, 27, 1)
+#define GET_RX_DESC_PHYST(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x00, 26, 1)
+#define GET_RX_DESC_SHIFT(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x00, 24, 2)
+#define GET_RX_DESC_QOS(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x00, 23, 1)
+#define GET_RX_DESC_SECURITY(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x00, 20, 3)
+#define GET_RX_DESC_DRV_INFO_SIZE(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x00, 16, 4)
+#define GET_RX_DESC_ICV_ERR(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x00, 15, 1)
+#define GET_RX_DESC_CRC32(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x00, 14, 1)
+#define GET_RX_DESC_PKT_LEN(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x00, 0, 14)
+
+/*RXDESC_WORD1*/
+
+#define GET_RX_DESC_BC(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x04, 31, 1)
+#define GET_RX_DESC_MC(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x04, 30, 1)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT)
+
+#define GET_RX_DESC_TY_PE(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x04, 28, 2)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define GET_RX_DESC_TYPE(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x04, 28, 2)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT || HALMAC_8812F_SUPPORT)
+
+#define GET_RX_DESC_MF(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x04, 27, 1)
+#define GET_RX_DESC_MD(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x04, 26, 1)
+#define GET_RX_DESC_PWR(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x04, 25, 1)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT)
+
+#define GET_RX_DESC_PAM(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x04, 24, 1)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define GET_RX_DESC_A1_MATCH(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x04, 24, 1)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT)
+
+#define GET_RX_DESC_CHK_VLD(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x04, 23, 1)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define GET_RX_DESC_TCP_CHKSUM_VLD(rxdesc)                                     \
+	LE_BITS_TO_4BYTE(rxdesc + 0x04, 23, 1)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT || HALMAC_8812F_SUPPORT)
+
+#define GET_RX_DESC_RX_IS_TCP_UDP(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x04, 22, 1)
+#define GET_RX_DESC_RX_IPV(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x04, 21, 1)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT)
+
+#define GET_RX_DESC_CHKERR(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x04, 20, 1)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define GET_RX_DESC_TCP_CHKSUM_ERR(rxdesc)                                     \
+	LE_BITS_TO_4BYTE(rxdesc + 0x04, 20, 1)
+#define GET_RX_DESC_PHY_PKT_IDC(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x04, 17, 1)
+#define GET_RX_DESC_FW_FIFO_FULL(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x04, 16, 1)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT)
+
+#define GET_RX_DESC_PAGGR(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x04, 15, 1)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define GET_RX_DESC_AMPDU(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x04, 15, 1)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT)
+
+#define GET_RX_DESC_RXID_MATCH(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x04, 14, 1)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define GET_RX_DESC_RXCMD_IDC(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x04, 14, 1)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT || HALMAC_8812F_SUPPORT)
+
+#define GET_RX_DESC_AMSDU(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x04, 13, 1)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT)
+
+#define GET_RX_DESC_MACID_VLD(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x04, 12, 1)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT || HALMAC_8812F_SUPPORT)
+
+#define GET_RX_DESC_TID(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x04, 8, 4)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT)
+
+#define GET_RX_DESC_MACID(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x04, 0, 7)
+
+/*RXDESC_WORD2*/
+
+#define GET_RX_DESC_FCS_OK(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x08, 31, 1)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define GET_RX_DESC_AMSDU_CUT(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x08, 31, 1)
+
+#endif
+
+#if (HALMAC_8822B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8814B_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8812F_SUPPORT)
+
+#define GET_RX_DESC_PPDU_CNT(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x08, 29, 2)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT || HALMAC_8812F_SUPPORT)
+
+#define GET_RX_DESC_C2H(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x08, 28, 1)
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+#define GET_RX_DESC_HWRSVD_V1(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x08, 25, 3)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8812F_SUPPORT)
+
+#define GET_RX_DESC_HWRSVD(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x08, 24, 4)
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+#define GET_RX_DESC_RXMAGPKT(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x08, 24, 1)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT || HALMAC_8812F_SUPPORT)
+
+#define GET_RX_DESC_WLANHD_IV_LEN(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x08, 18, 6)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define GET_RX_DESC_LAST_MSDU(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x08, 17, 1)
+
+#endif
+
+#if (HALMAC_8822C_SUPPORT || HALMAC_8812F_SUPPORT)
+
+#define GET_RX_DESC_RX_STATISTICS(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x08, 17, 1)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT)
+
+#define GET_RX_DESC_RX_IS_QOS(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x08, 16, 1)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define GET_RX_DESC_EXT_SEC_TYPE(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x08, 16, 1)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT || HALMAC_8812F_SUPPORT)
+
+#define GET_RX_DESC_FRAG(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x08, 12, 4)
+#define GET_RX_DESC_SEQ(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x08, 0, 12)
+
+/*RXDESC_WORD3*/
+
+#define GET_RX_DESC_MAGIC_WAKE(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x0C, 31, 1)
+#define GET_RX_DESC_UNICAST_WAKE(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x0C, 30, 1)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT)
+
+#define GET_RX_DESC_PATTERN_MATCH(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x0C, 29, 1)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define GET_RX_DESC_PATTERN_WAKE(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x0C, 29, 1)
+
+#endif
+
+#if (HALMAC_8822B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8814B_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8812F_SUPPORT)
+
+#define GET_RX_DESC_RXPAYLOAD_MATCH(rxdesc)                                    \
+	LE_BITS_TO_4BYTE(rxdesc + 0x0C, 28, 1)
+#define GET_RX_DESC_RXPAYLOAD_ID(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x0C, 24, 4)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT || HALMAC_8812F_SUPPORT)
+
+#define GET_RX_DESC_DMA_AGG_NUM(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x0C, 16, 8)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT)
+
+#define GET_RX_DESC_BSSID_FIT_1_0(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x0C, 12, 2)
+#define GET_RX_DESC_EOSP(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x0C, 11, 1)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define GET_RX_DESC_BSSID_FIT(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x0C, 11, 5)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT || HALMAC_8812F_SUPPORT)
+
+#define GET_RX_DESC_HTC(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x0C, 10, 1)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define GET_RX_DESC_AMPDU_END_PKT(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x0C, 9, 1)
+#define GET_RX_DESC_ADDRESS_CAM_VLD(rxdesc)                                    \
+	LE_BITS_TO_4BYTE(rxdesc + 0x0C, 8, 1)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT)
+
+#define GET_RX_DESC_BSSID_FIT_4_2(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x0C, 7, 3)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define GET_RX_DESC_EOSP_V1(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x0C, 7, 1)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT || HALMAC_8812F_SUPPORT)
+
+#define GET_RX_DESC_RX_RATE(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x0C, 0, 7)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8812F_SUPPORT)
+
+/*RXDESC_WORD4*/
+
+#define GET_RX_DESC_A1_FIT(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x10, 24, 5)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define GET_RX_DESC_ADDRESS_CAM(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x10, 24, 8)
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+#define GET_RX_DESC_A1_FIT_A1(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x10, 24, 7)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define GET_RX_DESC_MACID_VLD_V1(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x10, 23, 1)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT)
+
+#define GET_RX_DESC_MACID_RPT_BUFF(rxdesc)                                     \
+	LE_BITS_TO_4BYTE(rxdesc + 0x10, 17, 7)
+#define GET_RX_DESC_RX_PRE_NDP_VLD(rxdesc)                                     \
+	LE_BITS_TO_4BYTE(rxdesc + 0x10, 16, 1)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define GET_RX_DESC_MACID_V1(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x10, 15, 8)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT)
+
+#define GET_RX_DESC_RX_SCRAMBLER(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x10, 9, 7)
+#define GET_RX_DESC_RX_EOF(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x10, 8, 1)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+#define GET_RX_DESC_FC_POWER(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x10, 7, 1)
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+#define GET_RX_DESC_TXRPTMID_CTL_MASK(rxdesc)                                  \
+	LE_BITS_TO_4BYTE(rxdesc + 0x10, 6, 1)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT || HALMAC_8198F_SUPPORT)
+
+#define GET_RX_DESC_SWPS_RPT(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x10, 5, 1)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT || HALMAC_8812F_SUPPORT)
+
+#define GET_RX_DESC_PATTERN_IDX(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x10, 0, 8)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+#define GET_RX_DESC_PATTERN_IDX_V1(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x10, 0, 5)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define GET_RX_DESC_PATTERN_IDX_V2(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x10, 0, 5)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT)
+
+/*RXDESC_WORD5*/
+
+#define GET_RX_DESC_TSFL(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x14, 0, 32)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define GET_RX_DESC_FREERUN_CNT(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x14, 0, 32)
+
+#endif
+
+#endif
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/halmac/halmac_sdio_reg.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/halmac/halmac_sdio_reg.h
--- linux-5.6.3/3rdparty/rtl8821ce/hal/halmac/halmac_sdio_reg.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/halmac/halmac_sdio_reg.h	2020-04-10 16:35:06.816660067 +0300
@@ -0,0 +1,55 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ ******************************************************************************/
+
+#ifndef __HALMAC_SDIO_REG_H__
+#define __HALMAC_SDIO_REG_H__
+
+/* SDIO CMD address mapping */
+
+#define HALMAC_SDIO_4BYTE_LEN_MASK      0x1FFF
+#define HALMAC_SDIO_LOCAL_MSK           0x0FFF
+#define HALMAC_WLAN_MAC_REG_MSK		0xFFFF
+#define	HALMAC_WLAN_IOREG_MSK		0xFFFF
+
+/* Sdio Address for SDIO Local Reg, TRX FIFO, MAC Reg */
+enum halmac_sdio_cmd_addr {
+	HALMAC_SDIO_CMD_ADDR_SDIO_REG = 0,
+	HALMAC_SDIO_CMD_ADDR_MAC_REG = 8,
+	HALMAC_SDIO_CMD_ADDR_TXFF_HIGH = 4,
+	HALMAC_SDIO_CMD_ADDR_TXFF_LOW = 6,
+	HALMAC_SDIO_CMD_ADDR_TXFF_NORMAL = 5,
+	HALMAC_SDIO_CMD_ADDR_TXFF_EXTRA = 7,
+	HALMAC_SDIO_CMD_ADDR_RXFF = 7,
+};
+
+/* IO Bus domain address mapping */
+#define SDIO_LOCAL_OFFSET		0x10250000
+#define WLAN_IOREG_OFFSET		0x10260000
+#define FW_FIFO_OFFSET			0x10270000
+#define TX_HIQ_OFFSET			0x10310000
+#define TX_MIQ_OFFSET			0x10320000
+#define TX_LOQ_OFFSET			0x10330000
+#define TX_EXQ_OFFSET			0x10350000
+#define RX_RXOFF_OFFSET			0x10340000
+
+/* Get TX WLAN FIFO information in CMD53 addr  */
+#if (HALMAC_8822B_SUPPORT || HALMAC_8821C_SUPPORT)
+#define GET_WLAN_TXFF_DEVICE_ID(cmd53_addr) \
+			LE_BITS_TO_4BYTE((u32 *)cmd53_addr, 13, 4)
+#define GET_WLAN_TXFF_PKT_SIZE(cmd53_addr) \
+			(LE_BITS_TO_4BYTE((u32 *)cmd53_addr, 0, 13) << 2)
+#endif
+
+#endif/* __HALMAC_SDIO_REG_H__ */
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/halmac/halmac_state_machine.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/halmac/halmac_state_machine.h
--- linux-5.6.3/3rdparty/rtl8821ce/hal/halmac/halmac_state_machine.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/halmac/halmac_state_machine.h	2020-04-10 16:35:06.817660114 +0300
@@ -0,0 +1,157 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2017 - 2018 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ ******************************************************************************/
+
+#ifndef _HALMAC_STATE_MACHINE_H_
+#define _HALMAC_STATE_MACHINE_H_
+
+enum halmac_dlfw_state {
+	HALMAC_DLFW_NONE = 0,
+	HALMAC_DLFW_DONE = 1,
+	HALMAC_GEN_INFO_SENT = 2,
+
+	/* Data CPU firmware download framework */
+	HALMAC_DLFW_INIT = 0x11,
+	HALMAC_DLFW_START = 0x12,
+	HALMAC_DLFW_CONF_READY = 0x13,
+	HALMAC_DLFW_CPU_READY = 0x14,
+	HALMAC_DLFW_MEM_READY = 0x15,
+	HALMAC_DLFW_SW_READY = 0x16,
+	HALMAC_DLFW_OFLD_READY = 0x17,
+
+	HALMAC_DLFW_UNDEFINED = 0x7F,
+};
+
+enum halmac_gpio_cfg_state {
+	HALMAC_GPIO_CFG_STATE_IDLE = 0,
+	HALMAC_GPIO_CFG_STATE_BUSY = 1,
+	HALMAC_GPIO_CFG_STATE_UNDEFINED = 0x7F,
+};
+
+enum halmac_rsvd_pg_state {
+	HALMAC_RSVD_PG_STATE_IDLE = 0,
+	HALMAC_RSVD_PG_STATE_BUSY = 1,
+	HALMAC_RSVD_PG_STATE_UNDEFINED = 0x7F,
+};
+
+enum halmac_api_state {
+	HALMAC_API_STATE_INIT = 0,
+	HALMAC_API_STATE_HALT = 1,
+	HALMAC_API_STATE_UNDEFINED = 0x7F,
+};
+
+enum halmac_cmd_construct_state {
+	HALMAC_CMD_CNSTR_IDLE = 0,
+	HALMAC_CMD_CNSTR_BUSY = 1,
+	HALMAC_CMD_CNSTR_H2C_SENT = 2,
+	HALMAC_CMD_CNSTR_CNSTR = 3,
+	HALMAC_CMD_CNSTR_BUF_CLR = 4,
+	HALMAC_CMD_CNSTR_UNDEFINED = 0x7F,
+};
+
+enum halmac_cmd_process_status {
+	HALMAC_CMD_PROCESS_IDLE = 0x01, /* Init status */
+	HALMAC_CMD_PROCESS_SENDING = 0x02, /* Wait ack */
+	HALMAC_CMD_PROCESS_RCVD = 0x03, /* Rcvd ack */
+	HALMAC_CMD_PROCESS_DONE = 0x04, /* Event done */
+	HALMAC_CMD_PROCESS_ERROR = 0x05, /* Return code error */
+	HALMAC_CMD_PROCESS_UNDEFINE = 0x7F,
+};
+
+enum halmac_mac_power {
+	HALMAC_MAC_POWER_OFF = 0x0,
+	HALMAC_MAC_POWER_ON = 0x1,
+	HALMAC_MAC_POWER_UNDEFINE = 0x7F,
+};
+
+enum halmac_wlcpu_mode {
+	HALMAC_WLCPU_ACTIVE = 0x0,
+	HALMAC_WLCPU_ENTER_SLEEP = 0x1,
+	HALMAC_WLCPU_SLEEP = 0x2,
+	HALMAC_WLCPU_UNDEFINE = 0x7F,
+};
+
+struct halmac_efuse_state {
+	enum halmac_cmd_construct_state cmd_cnstr_state;
+	enum halmac_cmd_process_status proc_status;
+	u8 fw_rc;
+	u16 seq_num;
+};
+
+struct halmac_cfg_param_state {
+	enum halmac_cmd_construct_state cmd_cnstr_state;
+	enum halmac_cmd_process_status proc_status;
+	u8 fw_rc;
+	u16 seq_num;
+};
+
+struct halmac_scan_state {
+	enum halmac_cmd_construct_state cmd_cnstr_state;
+	enum halmac_cmd_process_status proc_status;
+	u8 fw_rc;
+	u16 seq_num;
+};
+
+struct halmac_update_pkt_state {
+	enum halmac_cmd_process_status proc_status;
+	u8 fw_rc;
+	u16 seq_num;
+};
+
+struct halmac_iqk_state {
+	enum halmac_cmd_process_status proc_status;
+	u8 fw_rc;
+	u16 seq_num;
+};
+
+struct halmac_pwr_tracking_state {
+	enum halmac_cmd_process_status	proc_status;
+	u8 fw_rc;
+	u16 seq_num;
+};
+
+struct halmac_psd_state {
+	enum halmac_cmd_process_status proc_status;
+	u16 data_size;
+	u16 seg_size;
+	u8 *data;
+	u8 fw_rc;
+	u16 seq_num;
+};
+
+struct halmac_fw_snding_state {
+	enum halmac_cmd_construct_state cmd_cnstr_state;
+	enum halmac_cmd_process_status proc_status;
+	u8 fw_rc;
+	u16 seq_num;
+};
+
+struct halmac_state {
+	struct halmac_efuse_state efuse_state;
+	struct halmac_cfg_param_state cfg_param_state;
+	struct halmac_scan_state scan_state;
+	struct halmac_update_pkt_state update_pkt_state;
+	struct halmac_iqk_state iqk_state;
+	struct halmac_pwr_tracking_state pwr_trk_state;
+	struct halmac_psd_state psd_state;
+	struct halmac_fw_snding_state fw_snding_state;
+	enum halmac_api_state api_state;
+	enum halmac_mac_power mac_pwr;
+	enum halmac_dlfw_state dlfw_state;
+	enum halmac_wlcpu_mode wlcpu_mode;
+	enum halmac_gpio_cfg_state gpio_cfg_state;
+	enum halmac_rsvd_pg_state rsvd_pg_state;
+};
+
+#endif
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/halmac/halmac_tx_bd_ap.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/halmac/halmac_tx_bd_ap.h
--- linux-5.6.3/3rdparty/rtl8821ce/hal/halmac/halmac_tx_bd_ap.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/halmac/halmac_tx_bd_ap.h	2020-04-10 16:35:06.817660114 +0300
@@ -0,0 +1,95 @@
+#ifndef _HALMAC_TX_BD_AP_H_
+#define _HALMAC_TX_BD_AP_H_
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8188F_SUPPORT)
+
+/*TXBD_DW0*/
+
+#define SET_TX_BD_OWN(__pTxBd, __Value)    HALMAC_SET_BD_FIELD_CLR(((PHALMAC_TX_BD)__pTxBd)->Dword0, __Value, 0x1, 31)
+#define SET_TX_BD_OWN_NO_CLR(__pTxBd, __Value)    HALMAC_SET_BD_FIELD_NO_CLR(((PHALMAC_TX_BD)__pTxBd)->Dword0, __Value, 0x1, 31)
+#define GET_TX_BD_OWN(__pTxBd)    HALMAC_GET_BD_FIELD(((PHALMAC_TX_BD)__pTxBd)->Dword0, 0x1, 31)
+#define SET_TX_BD_PSB(__pTxBd, __Value)    HALMAC_SET_BD_FIELD_CLR(((PHALMAC_TX_BD)__pTxBd)->Dword0, __Value, 0xff, 16)
+#define SET_TX_BD_PSB_NO_CLR(__pTxBd, __Value)    HALMAC_SET_BD_FIELD_NO_CLR(((PHALMAC_TX_BD)__pTxBd)->Dword0, __Value, 0xff, 16)
+#define GET_TX_BD_PSB(__pTxBd)    HALMAC_GET_BD_FIELD(((PHALMAC_TX_BD)__pTxBd)->Dword0, 0xff, 16)
+#define SET_TX_BD_TX_BUFF_SIZE0(__pTxBd, __Value)    HALMAC_SET_BD_FIELD_CLR(((PHALMAC_TX_BD)__pTxBd)->Dword0, __Value, 0xffff, 0)
+#define SET_TX_BD_TX_BUFF_SIZE0_NO_CLR(__pTxBd, __Value)    HALMAC_SET_BD_FIELD_NO_CLR(((PHALMAC_TX_BD)__pTxBd)->Dword0, __Value, 0xffff, 0)
+#define GET_TX_BD_TX_BUFF_SIZE0(__pTxBd)    HALMAC_GET_BD_FIELD(((PHALMAC_TX_BD)__pTxBd)->Dword0, 0xffff, 0)
+
+/*TXBD_DW1*/
+
+#define SET_TX_BD_PHYSICAL_ADDR0_LOW(__pTxBd, __Value)    HALMAC_SET_BD_FIELD_CLR(((PHALMAC_TX_BD)__pTxBd)->Dword1, __Value, 0xffffffff, 0)
+#define SET_TX_BD_PHYSICAL_ADDR0_LOW_NO_CLR(__pTxBd, __Value)    HALMAC_SET_BD_FIELD_NO_CLR(((PHALMAC_TX_BD)__pTxBd)->Dword1, __Value, 0xffffffff, 0)
+#define GET_TX_BD_PHYSICAL_ADDR0_LOW(__pTxBd)    HALMAC_GET_BD_FIELD(((PHALMAC_TX_BD)__pTxBd)->Dword1, 0xffffffff, 0)
+
+/*TXBD_DW2*/
+
+#define SET_TX_BD_PHYSICAL_ADDR0_HIGH(__pTxBd, __Value)    HALMAC_SET_BD_FIELD_CLR(((PHALMAC_TX_BD)__pTxBd)->Dword2, __Value, 0xffffffff, 0)
+#define SET_TX_BD_PHYSICAL_ADDR0_HIGH_NO_CLR(__pTxBd, __Value)    HALMAC_SET_BD_FIELD_NO_CLR(((PHALMAC_TX_BD)__pTxBd)->Dword2, __Value, 0xffffffff, 0)
+#define GET_TX_BD_PHYSICAL_ADDR0_HIGH(__pTxBd)    HALMAC_GET_BD_FIELD(((PHALMAC_TX_BD)__pTxBd)->Dword2, 0xffffffff, 0)
+
+/*TXBD_DW4*/
+
+#define SET_TX_BD_A1(__pTxBd, __Value)    HALMAC_SET_BD_FIELD_CLR(((PHALMAC_TX_BD)__pTxBd)->Dword4, __Value, 0x1, 31)
+#define SET_TX_BD_A1_NO_CLR(__pTxBd, __Value)    HALMAC_SET_BD_FIELD_NO_CLR(((PHALMAC_TX_BD)__pTxBd)->Dword4, __Value, 0x1, 31)
+#define GET_TX_BD_A1(__pTxBd)    HALMAC_GET_BD_FIELD(((PHALMAC_TX_BD)__pTxBd)->Dword4, 0x1, 31)
+#define SET_TX_BD_TX_BUFF_SIZE1(__pTxBd, __Value)    HALMAC_SET_BD_FIELD_CLR(((PHALMAC_TX_BD)__pTxBd)->Dword4, __Value, 0xffff, 0)
+#define SET_TX_BD_TX_BUFF_SIZE1_NO_CLR(__pTxBd, __Value)    HALMAC_SET_BD_FIELD_NO_CLR(((PHALMAC_TX_BD)__pTxBd)->Dword4, __Value, 0xffff, 0)
+#define GET_TX_BD_TX_BUFF_SIZE1(__pTxBd)    HALMAC_GET_BD_FIELD(((PHALMAC_TX_BD)__pTxBd)->Dword4, 0xffff, 0)
+
+/*TXBD_DW5*/
+
+#define SET_TX_BD_PHYSICAL_ADDR1_LOW(__pTxBd, __Value)    HALMAC_SET_BD_FIELD_CLR(((PHALMAC_TX_BD)__pTxBd)->Dword5, __Value, 0xffffffff, 0)
+#define SET_TX_BD_PHYSICAL_ADDR1_LOW_NO_CLR(__pTxBd, __Value)    HALMAC_SET_BD_FIELD_NO_CLR(((PHALMAC_TX_BD)__pTxBd)->Dword5, __Value, 0xffffffff, 0)
+#define GET_TX_BD_PHYSICAL_ADDR1_LOW(__pTxBd)    HALMAC_GET_BD_FIELD(((PHALMAC_TX_BD)__pTxBd)->Dword5, 0xffffffff, 0)
+
+/*TXBD_DW6*/
+
+#define SET_TX_BD_PHYSICAL_ADDR1_HIGH(__pTxBd, __Value)    HALMAC_SET_BD_FIELD_CLR(((PHALMAC_TX_BD)__pTxBd)->Dword6, __Value, 0xffffffff, 0)
+#define SET_TX_BD_PHYSICAL_ADDR1_HIGH_NO_CLR(__pTxBd, __Value)    HALMAC_SET_BD_FIELD_NO_CLR(((PHALMAC_TX_BD)__pTxBd)->Dword6, __Value, 0xffffffff, 0)
+#define GET_TX_BD_PHYSICAL_ADDR1_HIGH(__pTxBd)    HALMAC_GET_BD_FIELD(((PHALMAC_TX_BD)__pTxBd)->Dword6, 0xffffffff, 0)
+
+/*TXBD_DW8*/
+
+#define SET_TX_BD_A2(__pTxBd, __Value)    HALMAC_SET_BD_FIELD_CLR(((PHALMAC_TX_BD)__pTxBd)->Dword8, __Value, 0x1, 31)
+#define SET_TX_BD_A2_NO_CLR(__pTxBd, __Value)    HALMAC_SET_BD_FIELD_NO_CLR(((PHALMAC_TX_BD)__pTxBd)->Dword8, __Value, 0x1, 31)
+#define GET_TX_BD_A2(__pTxBd)    HALMAC_GET_BD_FIELD(((PHALMAC_TX_BD)__pTxBd)->Dword8, 0x1, 31)
+#define SET_TX_BD_TX_BUFF_SIZE2(__pTxBd, __Value)    HALMAC_SET_BD_FIELD_CLR(((PHALMAC_TX_BD)__pTxBd)->Dword8, __Value, 0xffff, 0)
+#define SET_TX_BD_TX_BUFF_SIZE2_NO_CLR(__pTxBd, __Value)    HALMAC_SET_BD_FIELD_NO_CLR(((PHALMAC_TX_BD)__pTxBd)->Dword8, __Value, 0xffff, 0)
+#define GET_TX_BD_TX_BUFF_SIZE2(__pTxBd)    HALMAC_GET_BD_FIELD(((PHALMAC_TX_BD)__pTxBd)->Dword8, 0xffff, 0)
+
+/*TXBD_DW9*/
+
+#define SET_TX_BD_PHYSICAL_ADDR2_LOW(__pTxBd, __Value)    HALMAC_SET_BD_FIELD_CLR(((PHALMAC_TX_BD)__pTxBd)->Dword9, __Value, 0xffffffff, 0)
+#define SET_TX_BD_PHYSICAL_ADDR2_LOW_NO_CLR(__pTxBd, __Value)    HALMAC_SET_BD_FIELD_NO_CLR(((PHALMAC_TX_BD)__pTxBd)->Dword9, __Value, 0xffffffff, 0)
+#define GET_TX_BD_PHYSICAL_ADDR2_LOW(__pTxBd)    HALMAC_GET_BD_FIELD(((PHALMAC_TX_BD)__pTxBd)->Dword9, 0xffffffff, 0)
+
+/*TXBD_DW10*/
+
+#define SET_TX_BD_PHYSICAL_ADDR2_HIGH(__pTxBd, __Value)    HALMAC_SET_BD_FIELD_CLR(((PHALMAC_TX_BD)__pTxBd)->Dword10, __Value, 0xffffffff, 0)
+#define SET_TX_BD_PHYSICAL_ADDR2_HIGH_NO_CLR(__pTxBd, __Value)    HALMAC_SET_BD_FIELD_NO_CLR(((PHALMAC_TX_BD)__pTxBd)->Dword10, __Value, 0xffffffff, 0)
+#define GET_TX_BD_PHYSICAL_ADDR2_HIGH(__pTxBd)    HALMAC_GET_BD_FIELD(((PHALMAC_TX_BD)__pTxBd)->Dword10, 0xffffffff, 0)
+
+/*TXBD_DW12*/
+
+#define SET_TX_BD_A3(__pTxBd, __Value)    HALMAC_SET_BD_FIELD_CLR(((PHALMAC_TX_BD)__pTxBd)->Dword12, __Value, 0x1, 31)
+#define SET_TX_BD_A3_NO_CLR(__pTxBd, __Value)    HALMAC_SET_BD_FIELD_NO_CLR(((PHALMAC_TX_BD)__pTxBd)->Dword12, __Value, 0x1, 31)
+#define GET_TX_BD_A3(__pTxBd)    HALMAC_GET_BD_FIELD(((PHALMAC_TX_BD)__pTxBd)->Dword12, 0x1, 31)
+#define SET_TX_BD_TX_BUFF_SIZE3(__pTxBd, __Value)    HALMAC_SET_BD_FIELD_CLR(((PHALMAC_TX_BD)__pTxBd)->Dword12, __Value, 0xffff, 0)
+#define SET_TX_BD_TX_BUFF_SIZE3_NO_CLR(__pTxBd, __Value)    HALMAC_SET_BD_FIELD_NO_CLR(((PHALMAC_TX_BD)__pTxBd)->Dword12, __Value, 0xffff, 0)
+#define GET_TX_BD_TX_BUFF_SIZE3(__pTxBd)    HALMAC_GET_BD_FIELD(((PHALMAC_TX_BD)__pTxBd)->Dword12, 0xffff, 0)
+
+/*TXBD_DW13*/
+
+#define SET_TX_BD_PHYSICAL_ADDR3_LOW(__pTxBd, __Value)    HALMAC_SET_BD_FIELD_CLR(((PHALMAC_TX_BD)__pTxBd)->Dword13, __Value, 0xffffffff, 0)
+#define SET_TX_BD_PHYSICAL_ADDR3_LOW_NO_CLR(__pTxBd, __Value)    HALMAC_SET_BD_FIELD_NO_CLR(((PHALMAC_TX_BD)__pTxBd)->Dword13, __Value, 0xffffffff, 0)
+#define GET_TX_BD_PHYSICAL_ADDR3_LOW(__pTxBd)    HALMAC_GET_BD_FIELD(((PHALMAC_TX_BD)__pTxBd)->Dword13, 0xffffffff, 0)
+
+/*TXBD_DW14*/
+
+#define SET_TX_BD_PHYSICAL_ADDR3_HIGH(__pTxBd, __Value)    HALMAC_SET_BD_FIELD_CLR(((PHALMAC_TX_BD)__pTxBd)->Dword14, __Value, 0xffffffff, 0)
+#define SET_TX_BD_PHYSICAL_ADDR3_HIGH_NO_CLR(__pTxBd, __Value)    HALMAC_SET_BD_FIELD_NO_CLR(((PHALMAC_TX_BD)__pTxBd)->Dword14, __Value, 0xffffffff, 0)
+#define GET_TX_BD_PHYSICAL_ADDR3_HIGH(__pTxBd)    HALMAC_GET_BD_FIELD(((PHALMAC_TX_BD)__pTxBd)->Dword14, 0xffffffff, 0)
+
+#endif
+
+
+#endif
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/halmac/halmac_tx_bd_chip.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/halmac/halmac_tx_bd_chip.h
--- linux-5.6.3/3rdparty/rtl8821ce/hal/halmac/halmac_tx_bd_chip.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/halmac/halmac_tx_bd_chip.h	2020-04-10 16:35:06.817660114 +0300
@@ -0,0 +1,374 @@
+#ifndef _HALMAC_TX_BD_CHIP_H_
+#define _HALMAC_TX_BD_CHIP_H_
+#if (HALMAC_8814A_SUPPORT)
+
+/*TXBD_DW0*/
+
+#define SET_TX_BD_OWN_8814A(__pTxBd, __Value)    SET_TX_BD_OWN(__pTxBd, __Value)
+#define GET_TX_BD_OWN_8814A(__pTxBd)    GET_TX_BD_OWN(__pTxBd)
+#define SET_TX_BD_PSB_8814A(__pTxBd, __Value)    SET_TX_BD_PSB(__pTxBd, __Value)
+#define GET_TX_BD_PSB_8814A(__pTxBd)    GET_TX_BD_PSB(__pTxBd)
+#define SET_TX_BD_TX_BUFF_SIZE0_8814A(__pTxBd, __Value)    SET_TX_BD_TX_BUFF_SIZE0(__pTxBd, __Value)
+#define GET_TX_BD_TX_BUFF_SIZE0_8814A(__pTxBd)    GET_TX_BD_TX_BUFF_SIZE0(__pTxBd)
+
+/*TXBD_DW1*/
+
+#define SET_TX_BD_PHYSICAL_ADDR0_LOW_8814A(__pTxBd, __Value)    SET_TX_BD_PHYSICAL_ADDR0_LOW(__pTxBd, __Value)
+#define GET_TX_BD_PHYSICAL_ADDR0_LOW_8814A(__pTxBd)    GET_TX_BD_PHYSICAL_ADDR0_LOW(__pTxBd)
+
+/*TXBD_DW2*/
+
+#define SET_TX_BD_PHYSICAL_ADDR0_HIGH_8814A(__pTxBd, __Value)    SET_TX_BD_PHYSICAL_ADDR0_HIGH(__pTxBd, __Value)
+#define GET_TX_BD_PHYSICAL_ADDR0_HIGH_8814A(__pTxBd)    GET_TX_BD_PHYSICAL_ADDR0_HIGH(__pTxBd)
+
+/*TXBD_DW4*/
+
+#define SET_TX_BD_A1_8814A(__pTxBd, __Value)    SET_TX_BD_A1(__pTxBd, __Value)
+#define GET_TX_BD_A1_8814A(__pTxBd)    GET_TX_BD_A1(__pTxBd)
+#define SET_TX_BD_TX_BUFF_SIZE1_8814A(__pTxBd, __Value)    SET_TX_BD_TX_BUFF_SIZE1(__pTxBd, __Value)
+#define GET_TX_BD_TX_BUFF_SIZE1_8814A(__pTxBd)    GET_TX_BD_TX_BUFF_SIZE1(__pTxBd)
+
+/*TXBD_DW5*/
+
+#define SET_TX_BD_PHYSICAL_ADDR1_LOW_8814A(__pTxBd, __Value)    SET_TX_BD_PHYSICAL_ADDR1_LOW(__pTxBd, __Value)
+#define GET_TX_BD_PHYSICAL_ADDR1_LOW_8814A(__pTxBd)    GET_TX_BD_PHYSICAL_ADDR1_LOW(__pTxBd)
+
+/*TXBD_DW6*/
+
+#define SET_TX_BD_PHYSICAL_ADDR1_HIGH_8814A(__pTxBd, __Value)    SET_TX_BD_PHYSICAL_ADDR1_HIGH(__pTxBd, __Value)
+#define GET_TX_BD_PHYSICAL_ADDR1_HIGH_8814A(__pTxBd)    GET_TX_BD_PHYSICAL_ADDR1_HIGH(__pTxBd)
+
+/*TXBD_DW8*/
+
+#define SET_TX_BD_A2_8814A(__pTxBd, __Value)    SET_TX_BD_A2(__pTxBd, __Value)
+#define GET_TX_BD_A2_8814A(__pTxBd)    GET_TX_BD_A2(__pTxBd)
+#define SET_TX_BD_TX_BUFF_SIZE2_8814A(__pTxBd, __Value)    SET_TX_BD_TX_BUFF_SIZE2(__pTxBd, __Value)
+#define GET_TX_BD_TX_BUFF_SIZE2_8814A(__pTxBd)    GET_TX_BD_TX_BUFF_SIZE2(__pTxBd)
+
+/*TXBD_DW9*/
+
+#define SET_TX_BD_PHYSICAL_ADDR2_LOW_8814A(__pTxBd, __Value)    SET_TX_BD_PHYSICAL_ADDR2_LOW(__pTxBd, __Value)
+#define GET_TX_BD_PHYSICAL_ADDR2_LOW_8814A(__pTxBd)    GET_TX_BD_PHYSICAL_ADDR2_LOW(__pTxBd)
+
+/*TXBD_DW10*/
+
+#define SET_TX_BD_PHYSICAL_ADDR2_HIGH_8814A(__pTxBd, __Value)    SET_TX_BD_PHYSICAL_ADDR2_HIGH(__pTxBd, __Value)
+#define GET_TX_BD_PHYSICAL_ADDR2_HIGH_8814A(__pTxBd)    GET_TX_BD_PHYSICAL_ADDR2_HIGH(__pTxBd)
+
+/*TXBD_DW12*/
+
+#define SET_TX_BD_A3_8814A(__pTxBd, __Value)    SET_TX_BD_A3(__pTxBd, __Value)
+#define GET_TX_BD_A3_8814A(__pTxBd)    GET_TX_BD_A3(__pTxBd)
+#define SET_TX_BD_TX_BUFF_SIZE3_8814A(__pTxBd, __Value)    SET_TX_BD_TX_BUFF_SIZE3(__pTxBd, __Value)
+#define GET_TX_BD_TX_BUFF_SIZE3_8814A(__pTxBd)    GET_TX_BD_TX_BUFF_SIZE3(__pTxBd)
+
+/*TXBD_DW13*/
+
+#define SET_TX_BD_PHYSICAL_ADDR3_LOW_8814A(__pTxBd, __Value)    SET_TX_BD_PHYSICAL_ADDR3_LOW(__pTxBd, __Value)
+#define GET_TX_BD_PHYSICAL_ADDR3_LOW_8814A(__pTxBd)    GET_TX_BD_PHYSICAL_ADDR3_LOW(__pTxBd)
+
+/*TXBD_DW14*/
+
+#define SET_TX_BD_PHYSICAL_ADDR3_HIGH_8814A(__pTxBd, __Value)    SET_TX_BD_PHYSICAL_ADDR3_HIGH(__pTxBd, __Value)
+#define GET_TX_BD_PHYSICAL_ADDR3_HIGH_8814A(__pTxBd)    GET_TX_BD_PHYSICAL_ADDR3_HIGH(__pTxBd)
+
+#endif
+
+#if (HALMAC_8822B_SUPPORT)
+
+/*TXBD_DW0*/
+
+#define SET_TX_BD_OWN_8822B(__pTxBd, __Value)    SET_TX_BD_OWN(__pTxBd, __Value)
+#define GET_TX_BD_OWN_8822B(__pTxBd)    GET_TX_BD_OWN(__pTxBd)
+#define SET_TX_BD_PSB_8822B(__pTxBd, __Value)    SET_TX_BD_PSB(__pTxBd, __Value)
+#define GET_TX_BD_PSB_8822B(__pTxBd)    GET_TX_BD_PSB(__pTxBd)
+#define SET_TX_BD_TX_BUFF_SIZE0_8822B(__pTxBd, __Value)    SET_TX_BD_TX_BUFF_SIZE0(__pTxBd, __Value)
+#define GET_TX_BD_TX_BUFF_SIZE0_8822B(__pTxBd)    GET_TX_BD_TX_BUFF_SIZE0(__pTxBd)
+
+/*TXBD_DW1*/
+
+#define SET_TX_BD_PHYSICAL_ADDR0_LOW_8822B(__pTxBd, __Value)    SET_TX_BD_PHYSICAL_ADDR0_LOW(__pTxBd, __Value)
+#define GET_TX_BD_PHYSICAL_ADDR0_LOW_8822B(__pTxBd)    GET_TX_BD_PHYSICAL_ADDR0_LOW(__pTxBd)
+
+/*TXBD_DW2*/
+
+#define SET_TX_BD_PHYSICAL_ADDR0_HIGH_8822B(__pTxBd, __Value)    SET_TX_BD_PHYSICAL_ADDR0_HIGH(__pTxBd, __Value)
+#define GET_TX_BD_PHYSICAL_ADDR0_HIGH_8822B(__pTxBd)    GET_TX_BD_PHYSICAL_ADDR0_HIGH(__pTxBd)
+
+/*TXBD_DW4*/
+
+#define SET_TX_BD_A1_8822B(__pTxBd, __Value)    SET_TX_BD_A1(__pTxBd, __Value)
+#define GET_TX_BD_A1_8822B(__pTxBd)    GET_TX_BD_A1(__pTxBd)
+#define SET_TX_BD_TX_BUFF_SIZE1_8822B(__pTxBd, __Value)    SET_TX_BD_TX_BUFF_SIZE1(__pTxBd, __Value)
+#define GET_TX_BD_TX_BUFF_SIZE1_8822B(__pTxBd)    GET_TX_BD_TX_BUFF_SIZE1(__pTxBd)
+
+/*TXBD_DW5*/
+
+#define SET_TX_BD_PHYSICAL_ADDR1_LOW_8822B(__pTxBd, __Value)    SET_TX_BD_PHYSICAL_ADDR1_LOW(__pTxBd, __Value)
+#define GET_TX_BD_PHYSICAL_ADDR1_LOW_8822B(__pTxBd)    GET_TX_BD_PHYSICAL_ADDR1_LOW(__pTxBd)
+
+/*TXBD_DW6*/
+
+#define SET_TX_BD_PHYSICAL_ADDR1_HIGH_8822B(__pTxBd, __Value)    SET_TX_BD_PHYSICAL_ADDR1_HIGH(__pTxBd, __Value)
+#define GET_TX_BD_PHYSICAL_ADDR1_HIGH_8822B(__pTxBd)    GET_TX_BD_PHYSICAL_ADDR1_HIGH(__pTxBd)
+
+/*TXBD_DW8*/
+
+#define SET_TX_BD_A2_8822B(__pTxBd, __Value)    SET_TX_BD_A2(__pTxBd, __Value)
+#define GET_TX_BD_A2_8822B(__pTxBd)    GET_TX_BD_A2(__pTxBd)
+#define SET_TX_BD_TX_BUFF_SIZE2_8822B(__pTxBd, __Value)    SET_TX_BD_TX_BUFF_SIZE2(__pTxBd, __Value)
+#define GET_TX_BD_TX_BUFF_SIZE2_8822B(__pTxBd)    GET_TX_BD_TX_BUFF_SIZE2(__pTxBd)
+
+/*TXBD_DW9*/
+
+#define SET_TX_BD_PHYSICAL_ADDR2_LOW_8822B(__pTxBd, __Value)    SET_TX_BD_PHYSICAL_ADDR2_LOW(__pTxBd, __Value)
+#define GET_TX_BD_PHYSICAL_ADDR2_LOW_8822B(__pTxBd)    GET_TX_BD_PHYSICAL_ADDR2_LOW(__pTxBd)
+
+/*TXBD_DW10*/
+
+#define SET_TX_BD_PHYSICAL_ADDR2_HIGH_8822B(__pTxBd, __Value)    SET_TX_BD_PHYSICAL_ADDR2_HIGH(__pTxBd, __Value)
+#define GET_TX_BD_PHYSICAL_ADDR2_HIGH_8822B(__pTxBd)    GET_TX_BD_PHYSICAL_ADDR2_HIGH(__pTxBd)
+
+/*TXBD_DW12*/
+
+#define SET_TX_BD_A3_8822B(__pTxBd, __Value)    SET_TX_BD_A3(__pTxBd, __Value)
+#define GET_TX_BD_A3_8822B(__pTxBd)    GET_TX_BD_A3(__pTxBd)
+#define SET_TX_BD_TX_BUFF_SIZE3_8822B(__pTxBd, __Value)    SET_TX_BD_TX_BUFF_SIZE3(__pTxBd, __Value)
+#define GET_TX_BD_TX_BUFF_SIZE3_8822B(__pTxBd)    GET_TX_BD_TX_BUFF_SIZE3(__pTxBd)
+
+/*TXBD_DW13*/
+
+#define SET_TX_BD_PHYSICAL_ADDR3_LOW_8822B(__pTxBd, __Value)    SET_TX_BD_PHYSICAL_ADDR3_LOW(__pTxBd, __Value)
+#define GET_TX_BD_PHYSICAL_ADDR3_LOW_8822B(__pTxBd)    GET_TX_BD_PHYSICAL_ADDR3_LOW(__pTxBd)
+
+/*TXBD_DW14*/
+
+#define SET_TX_BD_PHYSICAL_ADDR3_HIGH_8822B(__pTxBd, __Value)    SET_TX_BD_PHYSICAL_ADDR3_HIGH(__pTxBd, __Value)
+#define GET_TX_BD_PHYSICAL_ADDR3_HIGH_8822B(__pTxBd)    GET_TX_BD_PHYSICAL_ADDR3_HIGH(__pTxBd)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT)
+
+/*TXBD_DW0*/
+
+#define SET_TX_BD_OWN_8197F(__pTxBd, __Value)    SET_TX_BD_OWN(__pTxBd, __Value)
+#define GET_TX_BD_OWN_8197F(__pTxBd)    GET_TX_BD_OWN(__pTxBd)
+#define SET_TX_BD_PSB_8197F(__pTxBd, __Value)    SET_TX_BD_PSB(__pTxBd, __Value)
+#define GET_TX_BD_PSB_8197F(__pTxBd)    GET_TX_BD_PSB(__pTxBd)
+#define SET_TX_BD_TX_BUFF_SIZE0_8197F(__pTxBd, __Value)    SET_TX_BD_TX_BUFF_SIZE0(__pTxBd, __Value)
+#define GET_TX_BD_TX_BUFF_SIZE0_8197F(__pTxBd)    GET_TX_BD_TX_BUFF_SIZE0(__pTxBd)
+
+/*TXBD_DW1*/
+
+#define SET_TX_BD_PHYSICAL_ADDR0_LOW_8197F(__pTxBd, __Value)    SET_TX_BD_PHYSICAL_ADDR0_LOW(__pTxBd, __Value)
+#define GET_TX_BD_PHYSICAL_ADDR0_LOW_8197F(__pTxBd)    GET_TX_BD_PHYSICAL_ADDR0_LOW(__pTxBd)
+
+/*TXBD_DW2*/
+
+#define SET_TX_BD_PHYSICAL_ADDR0_HIGH_8197F(__pTxBd, __Value)    SET_TX_BD_PHYSICAL_ADDR0_HIGH(__pTxBd, __Value)
+#define GET_TX_BD_PHYSICAL_ADDR0_HIGH_8197F(__pTxBd)    GET_TX_BD_PHYSICAL_ADDR0_HIGH(__pTxBd)
+
+/*TXBD_DW4*/
+
+#define SET_TX_BD_A1_8197F(__pTxBd, __Value)    SET_TX_BD_A1(__pTxBd, __Value)
+#define GET_TX_BD_A1_8197F(__pTxBd)    GET_TX_BD_A1(__pTxBd)
+#define SET_TX_BD_TX_BUFF_SIZE1_8197F(__pTxBd, __Value)    SET_TX_BD_TX_BUFF_SIZE1(__pTxBd, __Value)
+#define GET_TX_BD_TX_BUFF_SIZE1_8197F(__pTxBd)    GET_TX_BD_TX_BUFF_SIZE1(__pTxBd)
+
+/*TXBD_DW5*/
+
+#define SET_TX_BD_PHYSICAL_ADDR1_LOW_8197F(__pTxBd, __Value)    SET_TX_BD_PHYSICAL_ADDR1_LOW(__pTxBd, __Value)
+#define GET_TX_BD_PHYSICAL_ADDR1_LOW_8197F(__pTxBd)    GET_TX_BD_PHYSICAL_ADDR1_LOW(__pTxBd)
+
+/*TXBD_DW6*/
+
+#define SET_TX_BD_PHYSICAL_ADDR1_HIGH_8197F(__pTxBd, __Value)    SET_TX_BD_PHYSICAL_ADDR1_HIGH(__pTxBd, __Value)
+#define GET_TX_BD_PHYSICAL_ADDR1_HIGH_8197F(__pTxBd)    GET_TX_BD_PHYSICAL_ADDR1_HIGH(__pTxBd)
+
+/*TXBD_DW8*/
+
+#define SET_TX_BD_A2_8197F(__pTxBd, __Value)    SET_TX_BD_A2(__pTxBd, __Value)
+#define GET_TX_BD_A2_8197F(__pTxBd)    GET_TX_BD_A2(__pTxBd)
+#define SET_TX_BD_TX_BUFF_SIZE2_8197F(__pTxBd, __Value)    SET_TX_BD_TX_BUFF_SIZE2(__pTxBd, __Value)
+#define GET_TX_BD_TX_BUFF_SIZE2_8197F(__pTxBd)    GET_TX_BD_TX_BUFF_SIZE2(__pTxBd)
+
+/*TXBD_DW9*/
+
+#define SET_TX_BD_PHYSICAL_ADDR2_LOW_8197F(__pTxBd, __Value)    SET_TX_BD_PHYSICAL_ADDR2_LOW(__pTxBd, __Value)
+#define GET_TX_BD_PHYSICAL_ADDR2_LOW_8197F(__pTxBd)    GET_TX_BD_PHYSICAL_ADDR2_LOW(__pTxBd)
+
+/*TXBD_DW10*/
+
+#define SET_TX_BD_PHYSICAL_ADDR2_HIGH_8197F(__pTxBd, __Value)    SET_TX_BD_PHYSICAL_ADDR2_HIGH(__pTxBd, __Value)
+#define GET_TX_BD_PHYSICAL_ADDR2_HIGH_8197F(__pTxBd)    GET_TX_BD_PHYSICAL_ADDR2_HIGH(__pTxBd)
+
+/*TXBD_DW12*/
+
+#define SET_TX_BD_A3_8197F(__pTxBd, __Value)    SET_TX_BD_A3(__pTxBd, __Value)
+#define GET_TX_BD_A3_8197F(__pTxBd)    GET_TX_BD_A3(__pTxBd)
+#define SET_TX_BD_TX_BUFF_SIZE3_8197F(__pTxBd, __Value)    SET_TX_BD_TX_BUFF_SIZE3(__pTxBd, __Value)
+#define GET_TX_BD_TX_BUFF_SIZE3_8197F(__pTxBd)    GET_TX_BD_TX_BUFF_SIZE3(__pTxBd)
+
+/*TXBD_DW13*/
+
+#define SET_TX_BD_PHYSICAL_ADDR3_LOW_8197F(__pTxBd, __Value)    SET_TX_BD_PHYSICAL_ADDR3_LOW(__pTxBd, __Value)
+#define GET_TX_BD_PHYSICAL_ADDR3_LOW_8197F(__pTxBd)    GET_TX_BD_PHYSICAL_ADDR3_LOW(__pTxBd)
+
+/*TXBD_DW14*/
+
+#define SET_TX_BD_PHYSICAL_ADDR3_HIGH_8197F(__pTxBd, __Value)    SET_TX_BD_PHYSICAL_ADDR3_HIGH(__pTxBd, __Value)
+#define GET_TX_BD_PHYSICAL_ADDR3_HIGH_8197F(__pTxBd)    GET_TX_BD_PHYSICAL_ADDR3_HIGH(__pTxBd)
+
+#endif
+
+#if (HALMAC_8821C_SUPPORT)
+
+/*TXBD_DW0*/
+
+#define SET_TX_BD_OWN_8821C(__pTxBd, __Value)    SET_TX_BD_OWN(__pTxBd, __Value)
+#define GET_TX_BD_OWN_8821C(__pTxBd)    GET_TX_BD_OWN(__pTxBd)
+#define SET_TX_BD_PSB_8821C(__pTxBd, __Value)    SET_TX_BD_PSB(__pTxBd, __Value)
+#define GET_TX_BD_PSB_8821C(__pTxBd)    GET_TX_BD_PSB(__pTxBd)
+#define SET_TX_BD_TX_BUFF_SIZE0_8821C(__pTxBd, __Value)    SET_TX_BD_TX_BUFF_SIZE0(__pTxBd, __Value)
+#define GET_TX_BD_TX_BUFF_SIZE0_8821C(__pTxBd)    GET_TX_BD_TX_BUFF_SIZE0(__pTxBd)
+
+/*TXBD_DW1*/
+
+#define SET_TX_BD_PHYSICAL_ADDR0_LOW_8821C(__pTxBd, __Value)    SET_TX_BD_PHYSICAL_ADDR0_LOW(__pTxBd, __Value)
+#define GET_TX_BD_PHYSICAL_ADDR0_LOW_8821C(__pTxBd)    GET_TX_BD_PHYSICAL_ADDR0_LOW(__pTxBd)
+
+/*TXBD_DW2*/
+
+#define SET_TX_BD_PHYSICAL_ADDR0_HIGH_8821C(__pTxBd, __Value)    SET_TX_BD_PHYSICAL_ADDR0_HIGH(__pTxBd, __Value)
+#define GET_TX_BD_PHYSICAL_ADDR0_HIGH_8821C(__pTxBd)    GET_TX_BD_PHYSICAL_ADDR0_HIGH(__pTxBd)
+
+/*TXBD_DW4*/
+
+#define SET_TX_BD_A1_8821C(__pTxBd, __Value)    SET_TX_BD_A1(__pTxBd, __Value)
+#define GET_TX_BD_A1_8821C(__pTxBd)    GET_TX_BD_A1(__pTxBd)
+#define SET_TX_BD_TX_BUFF_SIZE1_8821C(__pTxBd, __Value)    SET_TX_BD_TX_BUFF_SIZE1(__pTxBd, __Value)
+#define GET_TX_BD_TX_BUFF_SIZE1_8821C(__pTxBd)    GET_TX_BD_TX_BUFF_SIZE1(__pTxBd)
+
+/*TXBD_DW5*/
+
+#define SET_TX_BD_PHYSICAL_ADDR1_LOW_8821C(__pTxBd, __Value)    SET_TX_BD_PHYSICAL_ADDR1_LOW(__pTxBd, __Value)
+#define GET_TX_BD_PHYSICAL_ADDR1_LOW_8821C(__pTxBd)    GET_TX_BD_PHYSICAL_ADDR1_LOW(__pTxBd)
+
+/*TXBD_DW6*/
+
+#define SET_TX_BD_PHYSICAL_ADDR1_HIGH_8821C(__pTxBd, __Value)    SET_TX_BD_PHYSICAL_ADDR1_HIGH(__pTxBd, __Value)
+#define GET_TX_BD_PHYSICAL_ADDR1_HIGH_8821C(__pTxBd)    GET_TX_BD_PHYSICAL_ADDR1_HIGH(__pTxBd)
+
+/*TXBD_DW8*/
+
+#define SET_TX_BD_A2_8821C(__pTxBd, __Value)    SET_TX_BD_A2(__pTxBd, __Value)
+#define GET_TX_BD_A2_8821C(__pTxBd)    GET_TX_BD_A2(__pTxBd)
+#define SET_TX_BD_TX_BUFF_SIZE2_8821C(__pTxBd, __Value)    SET_TX_BD_TX_BUFF_SIZE2(__pTxBd, __Value)
+#define GET_TX_BD_TX_BUFF_SIZE2_8821C(__pTxBd)    GET_TX_BD_TX_BUFF_SIZE2(__pTxBd)
+
+/*TXBD_DW9*/
+
+#define SET_TX_BD_PHYSICAL_ADDR2_LOW_8821C(__pTxBd, __Value)    SET_TX_BD_PHYSICAL_ADDR2_LOW(__pTxBd, __Value)
+#define GET_TX_BD_PHYSICAL_ADDR2_LOW_8821C(__pTxBd)    GET_TX_BD_PHYSICAL_ADDR2_LOW(__pTxBd)
+
+/*TXBD_DW10*/
+
+#define SET_TX_BD_PHYSICAL_ADDR2_HIGH_8821C(__pTxBd, __Value)    SET_TX_BD_PHYSICAL_ADDR2_HIGH(__pTxBd, __Value)
+#define GET_TX_BD_PHYSICAL_ADDR2_HIGH_8821C(__pTxBd)    GET_TX_BD_PHYSICAL_ADDR2_HIGH(__pTxBd)
+
+/*TXBD_DW12*/
+
+#define SET_TX_BD_A3_8821C(__pTxBd, __Value)    SET_TX_BD_A3(__pTxBd, __Value)
+#define GET_TX_BD_A3_8821C(__pTxBd)    GET_TX_BD_A3(__pTxBd)
+#define SET_TX_BD_TX_BUFF_SIZE3_8821C(__pTxBd, __Value)    SET_TX_BD_TX_BUFF_SIZE3(__pTxBd, __Value)
+#define GET_TX_BD_TX_BUFF_SIZE3_8821C(__pTxBd)    GET_TX_BD_TX_BUFF_SIZE3(__pTxBd)
+
+/*TXBD_DW13*/
+
+#define SET_TX_BD_PHYSICAL_ADDR3_LOW_8821C(__pTxBd, __Value)    SET_TX_BD_PHYSICAL_ADDR3_LOW(__pTxBd, __Value)
+#define GET_TX_BD_PHYSICAL_ADDR3_LOW_8821C(__pTxBd)    GET_TX_BD_PHYSICAL_ADDR3_LOW(__pTxBd)
+
+/*TXBD_DW14*/
+
+#define SET_TX_BD_PHYSICAL_ADDR3_HIGH_8821C(__pTxBd, __Value)    SET_TX_BD_PHYSICAL_ADDR3_HIGH(__pTxBd, __Value)
+#define GET_TX_BD_PHYSICAL_ADDR3_HIGH_8821C(__pTxBd)    GET_TX_BD_PHYSICAL_ADDR3_HIGH(__pTxBd)
+
+#endif
+
+#if (HALMAC_8188F_SUPPORT)
+
+/*TXBD_DW0*/
+
+#define SET_TX_BD_OWN_8188F(__pTxBd, __Value)    SET_TX_BD_OWN(__pTxBd, __Value)
+#define GET_TX_BD_OWN_8188F(__pTxBd)    GET_TX_BD_OWN(__pTxBd)
+#define SET_TX_BD_PSB_8188F(__pTxBd, __Value)    SET_TX_BD_PSB(__pTxBd, __Value)
+#define GET_TX_BD_PSB_8188F(__pTxBd)    GET_TX_BD_PSB(__pTxBd)
+#define SET_TX_BD_TX_BUFF_SIZE0_8188F(__pTxBd, __Value)    SET_TX_BD_TX_BUFF_SIZE0(__pTxBd, __Value)
+#define GET_TX_BD_TX_BUFF_SIZE0_8188F(__pTxBd)    GET_TX_BD_TX_BUFF_SIZE0(__pTxBd)
+
+/*TXBD_DW1*/
+
+#define SET_TX_BD_PHYSICAL_ADDR0_LOW_8188F(__pTxBd, __Value)    SET_TX_BD_PHYSICAL_ADDR0_LOW(__pTxBd, __Value)
+#define GET_TX_BD_PHYSICAL_ADDR0_LOW_8188F(__pTxBd)    GET_TX_BD_PHYSICAL_ADDR0_LOW(__pTxBd)
+
+/*TXBD_DW2*/
+
+#define SET_TX_BD_PHYSICAL_ADDR0_HIGH_8188F(__pTxBd, __Value)    SET_TX_BD_PHYSICAL_ADDR0_HIGH(__pTxBd, __Value)
+#define GET_TX_BD_PHYSICAL_ADDR0_HIGH_8188F(__pTxBd)    GET_TX_BD_PHYSICAL_ADDR0_HIGH(__pTxBd)
+
+/*TXBD_DW4*/
+
+#define SET_TX_BD_A1_8188F(__pTxBd, __Value)    SET_TX_BD_A1(__pTxBd, __Value)
+#define GET_TX_BD_A1_8188F(__pTxBd)    GET_TX_BD_A1(__pTxBd)
+#define SET_TX_BD_TX_BUFF_SIZE1_8188F(__pTxBd, __Value)    SET_TX_BD_TX_BUFF_SIZE1(__pTxBd, __Value)
+#define GET_TX_BD_TX_BUFF_SIZE1_8188F(__pTxBd)    GET_TX_BD_TX_BUFF_SIZE1(__pTxBd)
+
+/*TXBD_DW5*/
+
+#define SET_TX_BD_PHYSICAL_ADDR1_LOW_8188F(__pTxBd, __Value)    SET_TX_BD_PHYSICAL_ADDR1_LOW(__pTxBd, __Value)
+#define GET_TX_BD_PHYSICAL_ADDR1_LOW_8188F(__pTxBd)    GET_TX_BD_PHYSICAL_ADDR1_LOW(__pTxBd)
+
+/*TXBD_DW6*/
+
+#define SET_TX_BD_PHYSICAL_ADDR1_HIGH_8188F(__pTxBd, __Value)    SET_TX_BD_PHYSICAL_ADDR1_HIGH(__pTxBd, __Value)
+#define GET_TX_BD_PHYSICAL_ADDR1_HIGH_8188F(__pTxBd)    GET_TX_BD_PHYSICAL_ADDR1_HIGH(__pTxBd)
+
+/*TXBD_DW8*/
+
+#define SET_TX_BD_A2_8188F(__pTxBd, __Value)    SET_TX_BD_A2(__pTxBd, __Value)
+#define GET_TX_BD_A2_8188F(__pTxBd)    GET_TX_BD_A2(__pTxBd)
+#define SET_TX_BD_TX_BUFF_SIZE2_8188F(__pTxBd, __Value)    SET_TX_BD_TX_BUFF_SIZE2(__pTxBd, __Value)
+#define GET_TX_BD_TX_BUFF_SIZE2_8188F(__pTxBd)    GET_TX_BD_TX_BUFF_SIZE2(__pTxBd)
+
+/*TXBD_DW9*/
+
+#define SET_TX_BD_PHYSICAL_ADDR2_LOW_8188F(__pTxBd, __Value)    SET_TX_BD_PHYSICAL_ADDR2_LOW(__pTxBd, __Value)
+#define GET_TX_BD_PHYSICAL_ADDR2_LOW_8188F(__pTxBd)    GET_TX_BD_PHYSICAL_ADDR2_LOW(__pTxBd)
+
+/*TXBD_DW10*/
+
+#define SET_TX_BD_PHYSICAL_ADDR2_HIGH_8188F(__pTxBd, __Value)    SET_TX_BD_PHYSICAL_ADDR2_HIGH(__pTxBd, __Value)
+#define GET_TX_BD_PHYSICAL_ADDR2_HIGH_8188F(__pTxBd)    GET_TX_BD_PHYSICAL_ADDR2_HIGH(__pTxBd)
+
+/*TXBD_DW12*/
+
+#define SET_TX_BD_A3_8188F(__pTxBd, __Value)    SET_TX_BD_A3(__pTxBd, __Value)
+#define GET_TX_BD_A3_8188F(__pTxBd)    GET_TX_BD_A3(__pTxBd)
+#define SET_TX_BD_TX_BUFF_SIZE3_8188F(__pTxBd, __Value)    SET_TX_BD_TX_BUFF_SIZE3(__pTxBd, __Value)
+#define GET_TX_BD_TX_BUFF_SIZE3_8188F(__pTxBd)    GET_TX_BD_TX_BUFF_SIZE3(__pTxBd)
+
+/*TXBD_DW13*/
+
+#define SET_TX_BD_PHYSICAL_ADDR3_LOW_8188F(__pTxBd, __Value)    SET_TX_BD_PHYSICAL_ADDR3_LOW(__pTxBd, __Value)
+#define GET_TX_BD_PHYSICAL_ADDR3_LOW_8188F(__pTxBd)    GET_TX_BD_PHYSICAL_ADDR3_LOW(__pTxBd)
+
+/*TXBD_DW14*/
+
+#define SET_TX_BD_PHYSICAL_ADDR3_HIGH_8188F(__pTxBd, __Value)    SET_TX_BD_PHYSICAL_ADDR3_HIGH(__pTxBd, __Value)
+#define GET_TX_BD_PHYSICAL_ADDR3_HIGH_8188F(__pTxBd)    GET_TX_BD_PHYSICAL_ADDR3_HIGH(__pTxBd)
+
+#endif
+
+
+#endif
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/halmac/halmac_tx_bd_nic.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/halmac/halmac_tx_bd_nic.h
--- linux-5.6.3/3rdparty/rtl8821ce/hal/halmac/halmac_tx_bd_nic.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/halmac/halmac_tx_bd_nic.h	2020-04-10 16:35:06.817660114 +0300
@@ -0,0 +1,111 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ ******************************************************************************/
+
+#ifndef _HALMAC_TX_BD_NIC_H_
+#define _HALMAC_TX_BD_NIC_H_
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+	HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT ||\
+	HALMAC_8812F_SUPPORT)
+
+/*TXBD_DW0*/
+
+#define SET_TX_BD_OWN(txbd, value)                                             \
+	SET_BITS_TO_LE_4BYTE(txbd + 0x00, 31, 1, value)
+#define GET_TX_BD_OWN(txbd) LE_BITS_TO_4BYTE(txbd + 0x00, 31, 1)
+#define SET_TX_BD_PSB(txbd, value)                                             \
+	SET_BITS_TO_LE_4BYTE(txbd + 0x00, 16, 8, value)
+#define GET_TX_BD_PSB(txbd) LE_BITS_TO_4BYTE(txbd + 0x00, 16, 8)
+#define SET_TX_BD_TX_BUFF_SIZE0(txbd, value)                                   \
+	SET_BITS_TO_LE_4BYTE(txbd + 0x00, 0, 16, value)
+#define GET_TX_BD_TX_BUFF_SIZE0(txbd) LE_BITS_TO_4BYTE(txbd + 0x00, 0, 16)
+
+/*TXBD_DW1*/
+
+#define SET_TX_BD_PHYSICAL_ADDR0_LOW(txbd, value)                              \
+	SET_BITS_TO_LE_4BYTE(txbd + 0x04, 0, 32, value)
+#define GET_TX_BD_PHYSICAL_ADDR0_LOW(txbd) LE_BITS_TO_4BYTE(txbd + 0x04, 0, 32)
+
+/*TXBD_DW2*/
+
+#define SET_TX_BD_PHYSICAL_ADDR0_HIGH(txbd, value)                             \
+	SET_BITS_TO_LE_4BYTE(txbd + 0x08, 0, 32, value)
+#define GET_TX_BD_PHYSICAL_ADDR0_HIGH(txbd) LE_BITS_TO_4BYTE(txbd + 0x08, 0, 32)
+
+/*TXBD_DW4*/
+
+#define SET_TX_BD_A1(txbd, value)                                              \
+	SET_BITS_TO_LE_4BYTE(txbd + 0x10, 31, 1, value)
+#define GET_TX_BD_A1(txbd) LE_BITS_TO_4BYTE(txbd + 0x10, 31, 1)
+#define SET_TX_BD_TX_BUFF_SIZE1(txbd, value)                                   \
+	SET_BITS_TO_LE_4BYTE(txbd + 0x10, 0, 16, value)
+#define GET_TX_BD_TX_BUFF_SIZE1(txbd) LE_BITS_TO_4BYTE(txbd + 0x10, 0, 16)
+
+/*TXBD_DW5*/
+
+#define SET_TX_BD_PHYSICAL_ADDR1_LOW(txbd, value)                              \
+	SET_BITS_TO_LE_4BYTE(txbd + 0x14, 0, 32, value)
+#define GET_TX_BD_PHYSICAL_ADDR1_LOW(txbd) LE_BITS_TO_4BYTE(txbd + 0x14, 0, 32)
+
+/*TXBD_DW6*/
+
+#define SET_TX_BD_PHYSICAL_ADDR1_HIGH(txbd, value)                             \
+	SET_BITS_TO_LE_4BYTE(txbd + 0x18, 0, 32, value)
+#define GET_TX_BD_PHYSICAL_ADDR1_HIGH(txbd) LE_BITS_TO_4BYTE(txbd + 0x18, 0, 32)
+
+/*TXBD_DW8*/
+
+#define SET_TX_BD_A2(txbd, value)                                              \
+	SET_BITS_TO_LE_4BYTE(txbd + 0x20, 31, 1, value)
+#define GET_TX_BD_A2(txbd) LE_BITS_TO_4BYTE(txbd + 0x20, 31, 1)
+#define SET_TX_BD_TX_BUFF_SIZE2(txbd, value)                                   \
+	SET_BITS_TO_LE_4BYTE(txbd + 0x20, 0, 16, value)
+#define GET_TX_BD_TX_BUFF_SIZE2(txbd) LE_BITS_TO_4BYTE(txbd + 0x20, 0, 16)
+
+/*TXBD_DW9*/
+
+#define SET_TX_BD_PHYSICAL_ADDR2_LOW(txbd, value)                              \
+	SET_BITS_TO_LE_4BYTE(txbd + 0x24, 0, 32, value)
+#define GET_TX_BD_PHYSICAL_ADDR2_LOW(txbd) LE_BITS_TO_4BYTE(txbd + 0x24, 0, 32)
+
+/*TXBD_DW10*/
+
+#define SET_TX_BD_PHYSICAL_ADDR2_HIGH(txbd, value)                             \
+	SET_BITS_TO_LE_4BYTE(txbd + 0x28, 0, 32, value)
+#define GET_TX_BD_PHYSICAL_ADDR2_HIGH(txbd) LE_BITS_TO_4BYTE(txbd + 0x28, 0, 32)
+
+/*TXBD_DW12*/
+
+#define SET_TX_BD_A3(txbd, value)                                              \
+	SET_BITS_TO_LE_4BYTE(txbd + 0x30, 31, 1, value)
+#define GET_TX_BD_A3(txbd) LE_BITS_TO_4BYTE(txbd + 0x30, 31, 1)
+#define SET_TX_BD_TX_BUFF_SIZE3(txbd, value)                                   \
+	SET_BITS_TO_LE_4BYTE(txbd + 0x30, 0, 16, value)
+#define GET_TX_BD_TX_BUFF_SIZE3(txbd) LE_BITS_TO_4BYTE(txbd + 0x30, 0, 16)
+
+/*TXBD_DW13*/
+
+#define SET_TX_BD_PHYSICAL_ADDR3_LOW(txbd, value)                              \
+	SET_BITS_TO_LE_4BYTE(txbd + 0x34, 0, 32, value)
+#define GET_TX_BD_PHYSICAL_ADDR3_LOW(txbd) LE_BITS_TO_4BYTE(txbd + 0x34, 0, 32)
+
+/*TXBD_DW14*/
+
+#define SET_TX_BD_PHYSICAL_ADDR3_HIGH(txbd, value)                             \
+	SET_BITS_TO_LE_4BYTE(txbd + 0x38, 0, 32, value)
+#define GET_TX_BD_PHYSICAL_ADDR3_HIGH(txbd) LE_BITS_TO_4BYTE(txbd + 0x38, 0, 32)
+
+#endif
+
+#endif
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/halmac/halmac_tx_desc_ap.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/halmac/halmac_tx_desc_ap.h
--- linux-5.6.3/3rdparty/rtl8821ce/hal/halmac/halmac_tx_desc_ap.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/halmac/halmac_tx_desc_ap.h	2020-04-10 16:35:06.817660114 +0300
@@ -0,0 +1,1942 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ ******************************************************************************/
+
+#ifndef _HALMAC_TX_DESC_AP_H_
+#define _HALMAC_TX_DESC_AP_H_
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT)
+
+/*TXDESC_WORD0*/
+
+#define SET_TX_DESC_DISQSELSEQ(txdesc, value)                                  \
+	HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword0,   \
+				  value, 0x1, 31)
+#define SET_TX_DESC_DISQSELSEQ_NO_CLR(txdesc, value)                           \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc)->dword0, value, 0x1, 31)
+#define GET_TX_DESC_DISQSELSEQ(txdesc)                                         \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword0, 0x1,  \
+			      31)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define SET_TX_DESC_IE_END_BODY(txdesc, value)                                 \
+	HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword0,   \
+				  value, 0x1, 31)
+#define SET_TX_DESC_IE_END_BODY_NO_CLR(txdesc, value)                          \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc)->dword0, value, 0x1, 31)
+#define GET_TX_DESC_IE_END_BODY(txdesc)                                        \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword0, 0x1,  \
+			      31)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT)
+
+#define SET_TX_DESC_GF(txdesc, value)                                          \
+	HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword0,   \
+				  value, 0x1, 30)
+#define SET_TX_DESC_GF_NO_CLR(txdesc, value)                                   \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc)->dword0, value, 0x1, 30)
+#define GET_TX_DESC_GF(txdesc)                                                 \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword0, 0x1,  \
+			      30)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define SET_TX_DESC_AGG_EN_V1(txdesc, value)                                   \
+	HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword0,   \
+				  value, 0x1, 30)
+#define SET_TX_DESC_AGG_EN_V1_NO_CLR(txdesc, value)                            \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc)->dword0, value, 0x1, 30)
+#define GET_TX_DESC_AGG_EN_V1(txdesc)                                          \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword0, 0x1,  \
+			      30)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT)
+
+#define SET_TX_DESC_NO_ACM(txdesc, value)                                      \
+	HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword0,   \
+				  value, 0x1, 29)
+#define SET_TX_DESC_NO_ACM_NO_CLR(txdesc, value)                               \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc)->dword0, value, 0x1, 29)
+#define GET_TX_DESC_NO_ACM(txdesc)                                             \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword0, 0x1,  \
+			      29)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define SET_TX_DESC_BK_V1(txdesc, value)                                       \
+	HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword0,   \
+				  value, 0x1, 29)
+#define SET_TX_DESC_BK_V1_NO_CLR(txdesc, value)                                \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc)->dword0, value, 0x1, 29)
+#define GET_TX_DESC_BK_V1(txdesc)                                              \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword0, 0x1,  \
+			      29)
+
+#endif
+
+#if (HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8812F_SUPPORT)
+
+#define SET_TX_DESC_BCNPKT_TSF_CTRL(txdesc, value)                             \
+	HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword0,   \
+				  value, 0x1, 28)
+#define SET_TX_DESC_BCNPKT_TSF_CTRL_NO_CLR(txdesc, value)                      \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc)->dword0, value, 0x1, 28)
+#define GET_TX_DESC_BCNPKT_TSF_CTRL(txdesc)                                    \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword0, 0x1,  \
+			      28)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT)
+
+#define SET_TX_DESC_AMSDU_PAD_EN(txdesc, value)                                \
+	HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword0,   \
+				  value, 0x1, 27)
+#define SET_TX_DESC_AMSDU_PAD_EN_NO_CLR(txdesc, value)                         \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc)->dword0, value, 0x1, 27)
+#define GET_TX_DESC_AMSDU_PAD_EN(txdesc)                                       \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword0, 0x1,  \
+			      27)
+#define SET_TX_DESC_LS(txdesc, value)                                          \
+	HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword0,   \
+				  value, 0x1, 26)
+#define SET_TX_DESC_LS_NO_CLR(txdesc, value)                                   \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc)->dword0, value, 0x1, 26)
+#define GET_TX_DESC_LS(txdesc)                                                 \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword0, 0x1,  \
+			      26)
+#define SET_TX_DESC_HTC(txdesc, value)                                         \
+	HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword0,   \
+				  value, 0x1, 25)
+#define SET_TX_DESC_HTC_NO_CLR(txdesc, value)                                  \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc)->dword0, value, 0x1, 25)
+#define GET_TX_DESC_HTC(txdesc)                                                \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword0, 0x1,  \
+			      25)
+#define SET_TX_DESC_BMC(txdesc, value)                                         \
+	HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword0,   \
+				  value, 0x1, 24)
+#define SET_TX_DESC_BMC_NO_CLR(txdesc, value)                                  \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc)->dword0, value, 0x1, 24)
+#define GET_TX_DESC_BMC(txdesc)                                                \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword0, 0x1,  \
+			      24)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define SET_TX_DESC_PKT_OFFSET_V1(txdesc, value)                               \
+	HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword0,   \
+				  value, 0x1f, 24)
+#define SET_TX_DESC_PKT_OFFSET_V1_NO_CLR(txdesc, value)                        \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc)->dword0, value, 0x1f, 24)
+#define GET_TX_DESC_PKT_OFFSET_V1(txdesc)                                      \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword0, 0x1f, \
+			      24)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT || HALMAC_8812F_SUPPORT)
+
+#define SET_TX_DESC_OFFSET(txdesc, value)                                      \
+	HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword0,   \
+				  value, 0xff, 16)
+#define SET_TX_DESC_OFFSET_NO_CLR(txdesc, value)                               \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc)->dword0, value, 0xff, 16)
+#define GET_TX_DESC_OFFSET(txdesc)                                             \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword0, 0xff, \
+			      16)
+#define SET_TX_DESC_TXPKTSIZE(txdesc, value)                                   \
+	HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword0,   \
+				  value, 0xffff, 0)
+#define SET_TX_DESC_TXPKTSIZE_NO_CLR(txdesc, value)                            \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc)->dword0, value, 0xffff, 0)
+#define GET_TX_DESC_TXPKTSIZE(txdesc)                                          \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword0,       \
+			      0xffff, 0)
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+/*WORD1*/
+
+#define SET_TX_DESC_HW_AES_IV_V2(txdesc, value)                                \
+	HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword1,   \
+				  value, 0x1, 31)
+#define SET_TX_DESC_HW_AES_IV_V2_NO_CLR(txdesc, value)                         \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc)->dword1, value, 0x1, 31)
+#define GET_TX_DESC_HW_AES_IV_V2(txdesc)                                       \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword1, 0x1,  \
+			      31)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define SET_TX_DESC_AMSDU(txdesc, value)                                       \
+	HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword1,   \
+				  value, 0x1, 30)
+#define SET_TX_DESC_AMSDU_NO_CLR(txdesc, value)                                \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc)->dword1, value, 0x1, 30)
+#define GET_TX_DESC_AMSDU(txdesc)                                              \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword1, 0x1,  \
+			      30)
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+#define SET_TX_DESC_FTM_EN_V1(txdesc, value)                                   \
+	HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword1,   \
+				  value, 0x1, 30)
+#define SET_TX_DESC_FTM_EN_V1_NO_CLR(txdesc, value)                            \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc)->dword1, value, 0x1, 30)
+#define GET_TX_DESC_FTM_EN_V1(txdesc)                                          \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword1, 0x1,  \
+			      30)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT)
+
+#define SET_TX_DESC_MOREDATA(txdesc, value)                                    \
+	HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword1,   \
+				  value, 0x1, 29)
+#define SET_TX_DESC_MOREDATA_NO_CLR(txdesc, value)                             \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc)->dword1, value, 0x1, 29)
+#define GET_TX_DESC_MOREDATA(txdesc)                                           \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword1, 0x1,  \
+			      29)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define SET_TX_DESC_HW_AES_IV_V1(txdesc, value)                                \
+	HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword1,   \
+				  value, 0x1, 29)
+#define SET_TX_DESC_HW_AES_IV_V1_NO_CLR(txdesc, value)                         \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc)->dword1, value, 0x1, 29)
+#define GET_TX_DESC_HW_AES_IV_V1(txdesc)                                       \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword1, 0x1,  \
+			      29)
+#define SET_TX_DESC_MHR_CP(txdesc, value)                                      \
+	HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword1,   \
+				  value, 0x1, 25)
+#define SET_TX_DESC_MHR_CP_NO_CLR(txdesc, value)                               \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc)->dword1, value, 0x1, 25)
+#define GET_TX_DESC_MHR_CP(txdesc)                                             \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword1, 0x1,  \
+			      25)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT)
+
+#define SET_TX_DESC_PKT_OFFSET(txdesc, value)                                  \
+	HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword1,   \
+				  value, 0x1f, 24)
+#define SET_TX_DESC_PKT_OFFSET_NO_CLR(txdesc, value)                           \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc)->dword1, value, 0x1f, 24)
+#define GET_TX_DESC_PKT_OFFSET(txdesc)                                         \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword1, 0x1f, \
+			      24)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define SET_TX_DESC_SMH_EN_V1(txdesc, value)                                   \
+	HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword1,   \
+				  value, 0x1, 24)
+#define SET_TX_DESC_SMH_EN_V1_NO_CLR(txdesc, value)                            \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc)->dword1, value, 0x1, 24)
+#define GET_TX_DESC_SMH_EN_V1(txdesc)                                          \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword1, 0x1,  \
+			      24)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT)
+
+#define SET_TX_DESC_SEC_TYPE(txdesc, value)                                    \
+	HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword1,   \
+				  value, 0x3, 22)
+#define SET_TX_DESC_SEC_TYPE_NO_CLR(txdesc, value)                             \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc)->dword1, value, 0x3, 22)
+#define GET_TX_DESC_SEC_TYPE(txdesc)                                           \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword1, 0x3,  \
+			      22)
+#define SET_TX_DESC_EN_DESC_ID(txdesc, value)                                  \
+	HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword1,   \
+				  value, 0x1, 21)
+#define SET_TX_DESC_EN_DESC_ID_NO_CLR(txdesc, value)                           \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc)->dword1, value, 0x1, 21)
+#define GET_TX_DESC_EN_DESC_ID(txdesc)                                         \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword1, 0x1,  \
+			      21)
+#define SET_TX_DESC_RATE_ID(txdesc, value)                                     \
+	HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword1,   \
+				  value, 0x1f, 16)
+#define SET_TX_DESC_RATE_ID_NO_CLR(txdesc, value)                              \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc)->dword1, value, 0x1f, 16)
+#define GET_TX_DESC_RATE_ID(txdesc)                                            \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword1, 0x1f, \
+			      16)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define SET_TX_DESC_SMH_CAM(txdesc, value)                                     \
+	HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword1,   \
+				  value, 0xff, 16)
+#define SET_TX_DESC_SMH_CAM_NO_CLR(txdesc, value)                              \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc)->dword1, value, 0xff, 16)
+#define GET_TX_DESC_SMH_CAM(txdesc)                                            \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword1, 0xff, \
+			      16)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT)
+
+#define SET_TX_DESC_PIFS(txdesc, value)                                        \
+	HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword1,   \
+				  value, 0x1, 15)
+#define SET_TX_DESC_PIFS_NO_CLR(txdesc, value)                                 \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc)->dword1, value, 0x1, 15)
+#define GET_TX_DESC_PIFS(txdesc)                                               \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword1, 0x1,  \
+			      15)
+#define SET_TX_DESC_LSIG_TXOP_EN(txdesc, value)                                \
+	HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword1,   \
+				  value, 0x1, 14)
+#define SET_TX_DESC_LSIG_TXOP_EN_NO_CLR(txdesc, value)                         \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc)->dword1, value, 0x1, 14)
+#define GET_TX_DESC_LSIG_TXOP_EN(txdesc)                                       \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword1, 0x1,  \
+			      14)
+#define SET_TX_DESC_RD_NAV_EXT(txdesc, value)                                  \
+	HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword1,   \
+				  value, 0x1, 13)
+#define SET_TX_DESC_RD_NAV_EXT_NO_CLR(txdesc, value)                           \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc)->dword1, value, 0x1, 13)
+#define GET_TX_DESC_RD_NAV_EXT(txdesc)                                         \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword1, 0x1,  \
+			      13)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define SET_TX_DESC_EXT_EDCA(txdesc, value)                                    \
+	HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword1,   \
+				  value, 0x1, 13)
+#define SET_TX_DESC_EXT_EDCA_NO_CLR(txdesc, value)                             \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc)->dword1, value, 0x1, 13)
+#define GET_TX_DESC_EXT_EDCA(txdesc)                                           \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword1, 0x1,  \
+			      13)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT || HALMAC_8812F_SUPPORT)
+
+#define SET_TX_DESC_QSEL(txdesc, value)                                        \
+	HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword1,   \
+				  value, 0x1f, 8)
+#define SET_TX_DESC_QSEL_NO_CLR(txdesc, value)                                 \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc)->dword1, value, 0x1f, 8)
+#define GET_TX_DESC_QSEL(txdesc)                                               \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword1, 0x1f, \
+			      8)
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+#define SET_TX_DESC_SPECIAL_CW(txdesc, value)                                  \
+	HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword1,   \
+				  value, 0x1, 7)
+#define SET_TX_DESC_SPECIAL_CW_NO_CLR(txdesc, value)                           \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc)->dword1, value, 0x1, 7)
+#define GET_TX_DESC_SPECIAL_CW(txdesc)                                         \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword1, 0x1, 7)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT)
+
+#define SET_TX_DESC_MACID(txdesc, value)                                       \
+	HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword1,   \
+				  value, 0x7f, 0)
+#define SET_TX_DESC_MACID_NO_CLR(txdesc, value)                                \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc)->dword1, value, 0x7f, 0)
+#define GET_TX_DESC_MACID(txdesc)                                              \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword1, 0x7f, \
+			      0)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define SET_TX_DESC_MACID_V1(txdesc, value)                                    \
+	HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword1,   \
+				  value, 0x7f, 0)
+#define SET_TX_DESC_MACID_V1_NO_CLR(txdesc, value)                             \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc)->dword1, value, 0x7f, 0)
+#define GET_TX_DESC_MACID_V1(txdesc)                                           \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword1, 0x7f, \
+			      0)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8812F_SUPPORT)
+
+/*TXDESC_WORD2*/
+
+#define SET_TX_DESC_HW_AES_IV(txdesc, value)                                   \
+	HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword2,   \
+				  value, 0x1, 31)
+#define SET_TX_DESC_HW_AES_IV_NO_CLR(txdesc, value)                            \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc)->dword2, value, 0x1, 31)
+#define GET_TX_DESC_HW_AES_IV(txdesc)                                          \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword2, 0x1,  \
+			      31)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define SET_TX_DESC_CHK_EN_V1(txdesc, value)                                   \
+	HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword2,   \
+				  value, 0x1, 31)
+#define SET_TX_DESC_CHK_EN_V1_NO_CLR(txdesc, value)                            \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc)->dword2, value, 0x1, 31)
+#define GET_TX_DESC_CHK_EN_V1(txdesc)                                          \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword2, 0x1,  \
+			      31)
+
+#endif
+
+#if (HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT || HALMAC_8812F_SUPPORT)
+
+#define SET_TX_DESC_FTM_EN(txdesc, value)                                      \
+	HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword2,   \
+				  value, 0x1, 30)
+#define SET_TX_DESC_FTM_EN_NO_CLR(txdesc, value)                               \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc)->dword2, value, 0x1, 30)
+#define GET_TX_DESC_FTM_EN(txdesc)                                             \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword2, 0x1,  \
+			      30)
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+#define SET_TX_DESC_ANTCEL_D_V1(txdesc, value)                                 \
+	HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword2,   \
+				  value, 0xf, 28)
+#define SET_TX_DESC_ANTCEL_D_V1_NO_CLR(txdesc, value)                          \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc)->dword2, value, 0xf, 28)
+#define GET_TX_DESC_ANTCEL_D_V1(txdesc)                                        \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword2, 0xf,  \
+			      28)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define SET_TX_DESC_DMA_PRI(txdesc, value)                                     \
+	HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword2,   \
+				  value, 0x1, 27)
+#define SET_TX_DESC_DMA_PRI_NO_CLR(txdesc, value)                              \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc)->dword2, value, 0x1, 27)
+#define GET_TX_DESC_DMA_PRI(txdesc)                                            \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword2, 0x1,  \
+			      27)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8812F_SUPPORT)
+
+#define SET_TX_DESC_G_ID(txdesc, value)                                        \
+	HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword2,   \
+				  value, 0x3f, 24)
+#define SET_TX_DESC_G_ID_NO_CLR(txdesc, value)                                 \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc)->dword2, value, 0x3f, 24)
+#define GET_TX_DESC_G_ID(txdesc)                                               \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword2, 0x3f, \
+			      24)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define SET_TX_DESC_MAX_AMSDU_MODE(txdesc, value)                              \
+	HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword2,   \
+				  value, 0x7, 24)
+#define SET_TX_DESC_MAX_AMSDU_MODE_NO_CLR(txdesc, value)                       \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc)->dword2, value, 0x7, 24)
+#define GET_TX_DESC_MAX_AMSDU_MODE(txdesc)                                     \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword2, 0x7,  \
+			      24)
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+#define SET_TX_DESC_ANTSEL_C_V1(txdesc, value)                                 \
+	HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword2,   \
+				  value, 0xf, 24)
+#define SET_TX_DESC_ANTSEL_C_V1_NO_CLR(txdesc, value)                          \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc)->dword2, value, 0xf, 24)
+#define GET_TX_DESC_ANTSEL_C_V1(txdesc)                                        \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword2, 0xf,  \
+			      24)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT)
+
+#define SET_TX_DESC_BT_NULL(txdesc, value)                                     \
+	HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword2,   \
+				  value, 0x1, 23)
+#define SET_TX_DESC_BT_NULL_NO_CLR(txdesc, value)                              \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc)->dword2, value, 0x1, 23)
+#define GET_TX_DESC_BT_NULL(txdesc)                                            \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword2, 0x1,  \
+			      23)
+#define SET_TX_DESC_AMPDU_DENSITY(txdesc, value)                               \
+	HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword2,   \
+				  value, 0x7, 20)
+#define SET_TX_DESC_AMPDU_DENSITY_NO_CLR(txdesc, value)                        \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc)->dword2, value, 0x7, 20)
+#define GET_TX_DESC_AMPDU_DENSITY(txdesc)                                      \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword2, 0x7,  \
+			      20)
+#define SET_TX_DESC_SPE_RPT(txdesc, value)                                     \
+	HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword2,   \
+				  value, 0x1, 19)
+#define SET_TX_DESC_SPE_RPT_NO_CLR(txdesc, value)                              \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc)->dword2, value, 0x1, 19)
+#define GET_TX_DESC_SPE_RPT(txdesc)                                            \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword2, 0x1,  \
+			      19)
+#define SET_TX_DESC_RAW(txdesc, value)                                         \
+	HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword2,   \
+				  value, 0x1, 18)
+#define SET_TX_DESC_RAW_NO_CLR(txdesc, value)                                  \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc)->dword2, value, 0x1, 18)
+#define GET_TX_DESC_RAW(txdesc)                                                \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword2, 0x1,  \
+			      18)
+#define SET_TX_DESC_MOREFRAG(txdesc, value)                                    \
+	HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword2,   \
+				  value, 0x1, 17)
+#define SET_TX_DESC_MOREFRAG_NO_CLR(txdesc, value)                             \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc)->dword2, value, 0x1, 17)
+#define GET_TX_DESC_MOREFRAG(txdesc)                                           \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword2, 0x1,  \
+			      17)
+#define SET_TX_DESC_BK(txdesc, value)                                          \
+	HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword2,   \
+				  value, 0x1, 16)
+#define SET_TX_DESC_BK_NO_CLR(txdesc, value)                                   \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc)->dword2, value, 0x1, 16)
+#define GET_TX_DESC_BK(txdesc)                                                 \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword2, 0x1,  \
+			      16)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define SET_TX_DESC_DMA_TXAGG_NUM_V1(txdesc, value)                            \
+	HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword2,   \
+				  value, 0xff, 16)
+#define SET_TX_DESC_DMA_TXAGG_NUM_V1_NO_CLR(txdesc, value)                     \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc)->dword2, value, 0xff, 16)
+#define GET_TX_DESC_DMA_TXAGG_NUM_V1(txdesc)                                   \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword2, 0xff, \
+			      16)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT)
+
+#define SET_TX_DESC_NULL_1(txdesc, value)                                      \
+	HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword2,   \
+				  value, 0x1, 15)
+#define SET_TX_DESC_NULL_1_NO_CLR(txdesc, value)                               \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc)->dword2, value, 0x1, 15)
+#define GET_TX_DESC_NULL_1(txdesc)                                             \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword2, 0x1,  \
+			      15)
+#define SET_TX_DESC_NULL_0(txdesc, value)                                      \
+	HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword2,   \
+				  value, 0x1, 14)
+#define SET_TX_DESC_NULL_0_NO_CLR(txdesc, value)                               \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc)->dword2, value, 0x1, 14)
+#define GET_TX_DESC_NULL_0(txdesc)                                             \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword2, 0x1,  \
+			      14)
+#define SET_TX_DESC_RDG_EN(txdesc, value)                                      \
+	HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword2,   \
+				  value, 0x1, 13)
+#define SET_TX_DESC_RDG_EN_NO_CLR(txdesc, value)                               \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc)->dword2, value, 0x1, 13)
+#define GET_TX_DESC_RDG_EN(txdesc)                                             \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword2, 0x1,  \
+			      13)
+#define SET_TX_DESC_AGG_EN(txdesc, value)                                      \
+	HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword2,   \
+				  value, 0x1, 12)
+#define SET_TX_DESC_AGG_EN_NO_CLR(txdesc, value)                               \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc)->dword2, value, 0x1, 12)
+#define GET_TX_DESC_AGG_EN(txdesc)                                             \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword2, 0x1,  \
+			      12)
+#define SET_TX_DESC_CCA_RTS(txdesc, value)                                     \
+	HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword2,   \
+				  value, 0x3, 10)
+#define SET_TX_DESC_CCA_RTS_NO_CLR(txdesc, value)                              \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc)->dword2, value, 0x3, 10)
+#define GET_TX_DESC_CCA_RTS(txdesc)                                            \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword2, 0x3,  \
+			      10)
+
+#endif
+
+#if (HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8812F_SUPPORT)
+
+#define SET_TX_DESC_TRI_FRAME(txdesc, value)                                   \
+	HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword2,   \
+				  value, 0x1, 9)
+#define SET_TX_DESC_TRI_FRAME_NO_CLR(txdesc, value)                            \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc)->dword2, value, 0x1, 9)
+#define GET_TX_DESC_TRI_FRAME(txdesc)                                          \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword2, 0x1, 9)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT)
+
+#define SET_TX_DESC_P_AID(txdesc, value)                                       \
+	HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword2,   \
+				  value, 0x1ff, 0)
+#define SET_TX_DESC_P_AID_NO_CLR(txdesc, value)                                \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc)->dword2, value, 0x1ff, 0)
+#define GET_TX_DESC_P_AID(txdesc)                                              \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword2,       \
+			      0x1ff, 0)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define SET_TX_DESC_TXDESC_CHECKSUM_V1(txdesc, value)                          \
+	HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword2,   \
+				  value, 0xffff, 0)
+#define SET_TX_DESC_TXDESC_CHECKSUM_V1_NO_CLR(txdesc, value)                   \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc)->dword2, value, 0xffff, 0)
+#define GET_TX_DESC_TXDESC_CHECKSUM_V1(txdesc)                                 \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword2,       \
+			      0xffff, 0)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT)
+
+/*TXDESC_WORD3*/
+
+#define SET_TX_DESC_AMPDU_MAX_TIME(txdesc, value)                              \
+	HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword3,   \
+				  value, 0xff, 24)
+#define SET_TX_DESC_AMPDU_MAX_TIME_NO_CLR(txdesc, value)                       \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc)->dword3, value, 0xff, 24)
+#define GET_TX_DESC_AMPDU_MAX_TIME(txdesc)                                     \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword3, 0xff, \
+			      24)
+#define SET_TX_DESC_NDPA(txdesc, value)                                        \
+	HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword3,   \
+				  value, 0x3, 22)
+#define SET_TX_DESC_NDPA_NO_CLR(txdesc, value)                                 \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc)->dword3, value, 0x3, 22)
+#define GET_TX_DESC_NDPA(txdesc)                                               \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword3, 0x3,  \
+			      22)
+#define SET_TX_DESC_MAX_AGG_NUM(txdesc, value)                                 \
+	HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword3,   \
+				  value, 0x1f, 17)
+#define SET_TX_DESC_MAX_AGG_NUM_NO_CLR(txdesc, value)                          \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc)->dword3, value, 0x1f, 17)
+#define GET_TX_DESC_MAX_AGG_NUM(txdesc)                                        \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword3, 0x1f, \
+			      17)
+#define SET_TX_DESC_USE_MAX_TIME_EN(txdesc, value)                             \
+	HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword3,   \
+				  value, 0x1, 16)
+#define SET_TX_DESC_USE_MAX_TIME_EN_NO_CLR(txdesc, value)                      \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc)->dword3, value, 0x1, 16)
+#define GET_TX_DESC_USE_MAX_TIME_EN(txdesc)                                    \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword3, 0x1,  \
+			      16)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define SET_TX_DESC_OFFLOAD_SIZE(txdesc, value)                                \
+	HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword3,   \
+				  value, 0x7fff, 16)
+#define SET_TX_DESC_OFFLOAD_SIZE_NO_CLR(txdesc, value)                         \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc)->dword3, value, 0x7fff, 16)
+#define GET_TX_DESC_OFFLOAD_SIZE(txdesc)                                       \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword3,       \
+			      0x7fff, 16)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT)
+
+#define SET_TX_DESC_NAVUSEHDR(txdesc, value)                                   \
+	HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword3,   \
+				  value, 0x1, 15)
+#define SET_TX_DESC_NAVUSEHDR_NO_CLR(txdesc, value)                            \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc)->dword3, value, 0x1, 15)
+#define GET_TX_DESC_NAVUSEHDR(txdesc)                                          \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword3, 0x1,  \
+			      15)
+#define SET_TX_DESC_CHK_EN(txdesc, value)                                      \
+	HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword3,   \
+				  value, 0x1, 14)
+#define SET_TX_DESC_CHK_EN_NO_CLR(txdesc, value)                               \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc)->dword3, value, 0x1, 14)
+#define GET_TX_DESC_CHK_EN(txdesc)                                             \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword3, 0x1,  \
+			      14)
+#define SET_TX_DESC_HW_RTS_EN(txdesc, value)                                   \
+	HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword3,   \
+				  value, 0x1, 13)
+#define SET_TX_DESC_HW_RTS_EN_NO_CLR(txdesc, value)                            \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc)->dword3, value, 0x1, 13)
+#define GET_TX_DESC_HW_RTS_EN(txdesc)                                          \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword3, 0x1,  \
+			      13)
+#define SET_TX_DESC_RTSEN(txdesc, value)                                       \
+	HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword3,   \
+				  value, 0x1, 12)
+#define SET_TX_DESC_RTSEN_NO_CLR(txdesc, value)                                \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc)->dword3, value, 0x1, 12)
+#define GET_TX_DESC_RTSEN(txdesc)                                              \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword3, 0x1,  \
+			      12)
+#define SET_TX_DESC_CTS2SELF(txdesc, value)                                    \
+	HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword3,   \
+				  value, 0x1, 11)
+#define SET_TX_DESC_CTS2SELF_NO_CLR(txdesc, value)                             \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc)->dword3, value, 0x1, 11)
+#define GET_TX_DESC_CTS2SELF(txdesc)                                           \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword3, 0x1,  \
+			      11)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define SET_TX_DESC_CHANNEL_DMA(txdesc, value)                                 \
+	HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword3,   \
+				  value, 0x1f, 11)
+#define SET_TX_DESC_CHANNEL_DMA_NO_CLR(txdesc, value)                          \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc)->dword3, value, 0x1f, 11)
+#define GET_TX_DESC_CHANNEL_DMA(txdesc)                                        \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword3, 0x1f, \
+			      11)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT)
+
+#define SET_TX_DESC_DISDATAFB(txdesc, value)                                   \
+	HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword3,   \
+				  value, 0x1, 10)
+#define SET_TX_DESC_DISDATAFB_NO_CLR(txdesc, value)                            \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc)->dword3, value, 0x1, 10)
+#define GET_TX_DESC_DISDATAFB(txdesc)                                          \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword3, 0x1,  \
+			      10)
+#define SET_TX_DESC_DISRTSFB(txdesc, value)                                    \
+	HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword3,   \
+				  value, 0x1, 9)
+#define SET_TX_DESC_DISRTSFB_NO_CLR(txdesc, value)                             \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc)->dword3, value, 0x1, 9)
+#define GET_TX_DESC_DISRTSFB(txdesc)                                           \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword3, 0x1, 9)
+#define SET_TX_DESC_USE_RATE(txdesc, value)                                    \
+	HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword3,   \
+				  value, 0x1, 8)
+#define SET_TX_DESC_USE_RATE_NO_CLR(txdesc, value)                             \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc)->dword3, value, 0x1, 8)
+#define GET_TX_DESC_USE_RATE(txdesc)                                           \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword3, 0x1, 8)
+#define SET_TX_DESC_HW_SSN_SEL(txdesc, value)                                  \
+	HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword3,   \
+				  value, 0x3, 6)
+#define SET_TX_DESC_HW_SSN_SEL_NO_CLR(txdesc, value)                           \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc)->dword3, value, 0x3, 6)
+#define GET_TX_DESC_HW_SSN_SEL(txdesc)                                         \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword3, 0x3, 6)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define SET_TX_DESC_IE_CNT(txdesc, value)                                      \
+	HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword3,   \
+				  value, 0x7, 6)
+#define SET_TX_DESC_IE_CNT_NO_CLR(txdesc, value)                               \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc)->dword3, value, 0x7, 6)
+#define GET_TX_DESC_IE_CNT(txdesc)                                             \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword3, 0x7, 6)
+#define SET_TX_DESC_IE_CNT_EN(txdesc, value)                                   \
+	HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword3,   \
+				  value, 0x1, 5)
+#define SET_TX_DESC_IE_CNT_EN_NO_CLR(txdesc, value)                            \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc)->dword3, value, 0x1, 5)
+#define GET_TX_DESC_IE_CNT_EN(txdesc)                                          \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword3, 0x1, 5)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT)
+
+#define SET_TX_DESC_WHEADER_LEN(txdesc, value)                                 \
+	HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword3,   \
+				  value, 0x1f, 0)
+#define SET_TX_DESC_WHEADER_LEN_NO_CLR(txdesc, value)                          \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc)->dword3, value, 0x1f, 0)
+#define GET_TX_DESC_WHEADER_LEN(txdesc)                                        \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword3, 0x1f, \
+			      0)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define SET_TX_DESC_WHEADER_LEN_V1(txdesc, value)                              \
+	HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword3,   \
+				  value, 0x1f, 0)
+#define SET_TX_DESC_WHEADER_LEN_V1_NO_CLR(txdesc, value)                       \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc)->dword3, value, 0x1f, 0)
+#define GET_TX_DESC_WHEADER_LEN_V1(txdesc)                                     \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword3, 0x1f, \
+			      0)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT)
+
+/*TXDESC_WORD4*/
+
+#define SET_TX_DESC_PCTS_MASK_IDX(txdesc, value)                               \
+	HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword4,   \
+				  value, 0x3, 30)
+#define SET_TX_DESC_PCTS_MASK_IDX_NO_CLR(txdesc, value)                        \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc)->dword4, value, 0x3, 30)
+#define GET_TX_DESC_PCTS_MASK_IDX(txdesc)                                      \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword4, 0x3,  \
+			      30)
+#define SET_TX_DESC_PCTS_EN(txdesc, value)                                     \
+	HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword4,   \
+				  value, 0x1, 29)
+#define SET_TX_DESC_PCTS_EN_NO_CLR(txdesc, value)                              \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc)->dword4, value, 0x1, 29)
+#define GET_TX_DESC_PCTS_EN(txdesc)                                            \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword4, 0x1,  \
+			      29)
+#define SET_TX_DESC_RTSRATE(txdesc, value)                                     \
+	HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword4,   \
+				  value, 0x1f, 24)
+#define SET_TX_DESC_RTSRATE_NO_CLR(txdesc, value)                              \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc)->dword4, value, 0x1f, 24)
+#define GET_TX_DESC_RTSRATE(txdesc)                                            \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword4, 0x1f, \
+			      24)
+#define SET_TX_DESC_RTS_DATA_RTY_LMT(txdesc, value)                            \
+	HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword4,   \
+				  value, 0x3f, 18)
+#define SET_TX_DESC_RTS_DATA_RTY_LMT_NO_CLR(txdesc, value)                     \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc)->dword4, value, 0x3f, 18)
+#define GET_TX_DESC_RTS_DATA_RTY_LMT(txdesc)                                   \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword4, 0x3f, \
+			      18)
+#define SET_TX_DESC_RTY_LMT_EN(txdesc, value)                                  \
+	HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword4,   \
+				  value, 0x1, 17)
+#define SET_TX_DESC_RTY_LMT_EN_NO_CLR(txdesc, value)                           \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc)->dword4, value, 0x1, 17)
+#define GET_TX_DESC_RTY_LMT_EN(txdesc)                                         \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword4, 0x1,  \
+			      17)
+#define SET_TX_DESC_RTS_RTY_LOWEST_RATE(txdesc, value)                         \
+	HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword4,   \
+				  value, 0xf, 13)
+#define SET_TX_DESC_RTS_RTY_LOWEST_RATE_NO_CLR(txdesc, value)                  \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc)->dword4, value, 0xf, 13)
+#define GET_TX_DESC_RTS_RTY_LOWEST_RATE(txdesc)                                \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword4, 0xf,  \
+			      13)
+#define SET_TX_DESC_DATA_RTY_LOWEST_RATE(txdesc, value)                        \
+	HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword4,   \
+				  value, 0x1f, 8)
+#define SET_TX_DESC_DATA_RTY_LOWEST_RATE_NO_CLR(txdesc, value)                 \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc)->dword4, value, 0x1f, 8)
+#define GET_TX_DESC_DATA_RTY_LOWEST_RATE(txdesc)                               \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword4, 0x1f, \
+			      8)
+#define SET_TX_DESC_TRY_RATE(txdesc, value)                                    \
+	HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword4,   \
+				  value, 0x1, 7)
+#define SET_TX_DESC_TRY_RATE_NO_CLR(txdesc, value)                             \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc)->dword4, value, 0x1, 7)
+#define GET_TX_DESC_TRY_RATE(txdesc)                                           \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword4, 0x1, 7)
+#define SET_TX_DESC_DATARATE(txdesc, value)                                    \
+	HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword4,   \
+				  value, 0x7f, 0)
+#define SET_TX_DESC_DATARATE_NO_CLR(txdesc, value)                             \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc)->dword4, value, 0x7f, 0)
+#define GET_TX_DESC_DATARATE(txdesc)                                           \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword4, 0x7f, \
+			      0)
+
+/*TXDESC_WORD5*/
+
+#define SET_TX_DESC_POLLUTED(txdesc, value)                                    \
+	HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword5,   \
+				  value, 0x1, 31)
+#define SET_TX_DESC_POLLUTED_NO_CLR(txdesc, value)                             \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc)->dword5, value, 0x1, 31)
+#define GET_TX_DESC_POLLUTED(txdesc)                                           \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword5, 0x1,  \
+			      31)
+
+#endif
+
+#if (HALMAC_8822C_SUPPORT || HALMAC_8812F_SUPPORT)
+
+#define SET_TX_DESC_ANTSEL_EN_V1(txdesc, value)                                \
+	HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword5,   \
+				  value, 0x1, 30)
+#define SET_TX_DESC_ANTSEL_EN_V1_NO_CLR(txdesc, value)                         \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc)->dword5, value, 0x1, 30)
+#define GET_TX_DESC_ANTSEL_EN_V1(txdesc)                                       \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword5, 0x1,  \
+			      30)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT)
+
+#define SET_TX_DESC_TXPWR_OFSET(txdesc, value)                                 \
+	HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword5,   \
+				  value, 0x7, 28)
+#define SET_TX_DESC_TXPWR_OFSET_NO_CLR(txdesc, value)                          \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc)->dword5, value, 0x7, 28)
+#define GET_TX_DESC_TXPWR_OFSET(txdesc)                                        \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword5, 0x7,  \
+			      28)
+
+#endif
+
+#if (HALMAC_8822C_SUPPORT || HALMAC_8812F_SUPPORT)
+
+#define SET_TX_DESC_TXPWR_OFSET_TYPE(txdesc, value)                            \
+	HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword5,   \
+				  value, 0x3, 28)
+#define SET_TX_DESC_TXPWR_OFSET_TYPE_NO_CLR(txdesc, value)                     \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc)->dword5, value, 0x3, 28)
+#define GET_TX_DESC_TXPWR_OFSET_TYPE(txdesc)                                   \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword5, 0x3,  \
+			      28)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8812F_SUPPORT)
+
+#define SET_TX_DESC_TX_ANT(txdesc, value)                                      \
+	HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword5,   \
+				  value, 0xf, 24)
+#define SET_TX_DESC_TX_ANT_NO_CLR(txdesc, value)                               \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc)->dword5, value, 0xf, 24)
+#define GET_TX_DESC_TX_ANT(txdesc)                                             \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword5, 0xf,  \
+			      24)
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+#define SET_TX_DESC_DROP_ID(txdesc, value)                                     \
+	HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword5,   \
+				  value, 0x3, 24)
+#define SET_TX_DESC_DROP_ID_NO_CLR(txdesc, value)                              \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc)->dword5, value, 0x3, 24)
+#define GET_TX_DESC_DROP_ID(txdesc)                                            \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword5, 0x3,  \
+			      24)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT)
+
+#define SET_TX_DESC_PORT_ID(txdesc, value)                                     \
+	HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword5,   \
+				  value, 0x7, 21)
+#define SET_TX_DESC_PORT_ID_NO_CLR(txdesc, value)                              \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc)->dword5, value, 0x7, 21)
+#define GET_TX_DESC_PORT_ID(txdesc)                                            \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword5, 0x7,  \
+			      21)
+
+#endif
+
+#if (HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8812F_SUPPORT)
+
+#define SET_TX_DESC_MULTIPLE_PORT(txdesc, value)                               \
+	HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword5,   \
+				  value, 0x7, 18)
+#define SET_TX_DESC_MULTIPLE_PORT_NO_CLR(txdesc, value)                        \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc)->dword5, value, 0x7, 18)
+#define GET_TX_DESC_MULTIPLE_PORT(txdesc)                                      \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword5, 0x7,  \
+			      18)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT)
+
+#define SET_TX_DESC_SIGNALING_TAPKT_EN(txdesc, value)                          \
+	HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword5,   \
+				  value, 0x1, 17)
+#define SET_TX_DESC_SIGNALING_TAPKT_EN_NO_CLR(txdesc, value)                   \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc)->dword5, value, 0x1, 17)
+#define GET_TX_DESC_SIGNALING_TAPKT_EN(txdesc)                                 \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword5, 0x1,  \
+			      17)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+#define SET_TX_DESC_RTS_SC(txdesc, value)                                      \
+	HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword5,   \
+				  value, 0xf, 13)
+#define SET_TX_DESC_RTS_SC_NO_CLR(txdesc, value)                               \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc)->dword5, value, 0xf, 13)
+#define GET_TX_DESC_RTS_SC(txdesc)                                             \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword5, 0xf,  \
+			      13)
+
+#endif
+
+#if (HALMAC_8822B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT)
+
+#define SET_TX_DESC_SIGNALING_TA_PKT_SC(txdesc, value)                         \
+	HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword5,   \
+				  value, 0xf, 13)
+#define SET_TX_DESC_SIGNALING_TA_PKT_SC_NO_CLR(txdesc, value)                  \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc)->dword5, value, 0xf, 13)
+#define GET_TX_DESC_SIGNALING_TA_PKT_SC(txdesc)                                \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword5, 0xf,  \
+			      13)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT)
+
+#define SET_TX_DESC_RTS_SHORT(txdesc, value)                                   \
+	HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword5,   \
+				  value, 0x1, 12)
+#define SET_TX_DESC_RTS_SHORT_NO_CLR(txdesc, value)                            \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc)->dword5, value, 0x1, 12)
+#define GET_TX_DESC_RTS_SHORT(txdesc)                                          \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword5, 0x1,  \
+			      12)
+#define SET_TX_DESC_VCS_STBC(txdesc, value)                                    \
+	HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword5,   \
+				  value, 0x3, 10)
+#define SET_TX_DESC_VCS_STBC_NO_CLR(txdesc, value)                             \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc)->dword5, value, 0x3, 10)
+#define GET_TX_DESC_VCS_STBC(txdesc)                                           \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword5, 0x3,  \
+			      10)
+#define SET_TX_DESC_DATA_STBC(txdesc, value)                                   \
+	HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword5,   \
+				  value, 0x3, 8)
+#define SET_TX_DESC_DATA_STBC_NO_CLR(txdesc, value)                            \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc)->dword5, value, 0x3, 8)
+#define GET_TX_DESC_DATA_STBC(txdesc)                                          \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword5, 0x3, 8)
+#define SET_TX_DESC_DATA_LDPC(txdesc, value)                                   \
+	HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword5,   \
+				  value, 0x1, 7)
+#define SET_TX_DESC_DATA_LDPC_NO_CLR(txdesc, value)                            \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc)->dword5, value, 0x1, 7)
+#define GET_TX_DESC_DATA_LDPC(txdesc)                                          \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword5, 0x1, 7)
+#define SET_TX_DESC_DATA_BW(txdesc, value)                                     \
+	HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword5,   \
+				  value, 0x3, 5)
+#define SET_TX_DESC_DATA_BW_NO_CLR(txdesc, value)                              \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc)->dword5, value, 0x3, 5)
+#define GET_TX_DESC_DATA_BW(txdesc)                                            \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword5, 0x3, 5)
+#define SET_TX_DESC_DATA_SHORT(txdesc, value)                                  \
+	HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword5,   \
+				  value, 0x1, 4)
+#define SET_TX_DESC_DATA_SHORT_NO_CLR(txdesc, value)                           \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc)->dword5, value, 0x1, 4)
+#define GET_TX_DESC_DATA_SHORT(txdesc)                                         \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword5, 0x1, 4)
+#define SET_TX_DESC_DATA_SC(txdesc, value)                                     \
+	HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword5,   \
+				  value, 0xf, 0)
+#define SET_TX_DESC_DATA_SC_NO_CLR(txdesc, value)                              \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc)->dword5, value, 0xf, 0)
+#define GET_TX_DESC_DATA_SC(txdesc)                                            \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword5, 0xf, 0)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8812F_SUPPORT)
+
+/*TXDESC_WORD6*/
+
+#define SET_TX_DESC_ANTSEL_D(txdesc, value)                                    \
+	HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword6,   \
+				  value, 0x3, 30)
+#define SET_TX_DESC_ANTSEL_D_NO_CLR(txdesc, value)                             \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc)->dword6, value, 0x3, 30)
+#define GET_TX_DESC_ANTSEL_D(txdesc)                                           \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword6, 0x3,  \
+			      30)
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+#define SET_TX_DESC_ANT_MAPD_V1(txdesc, value)                                 \
+	HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword6,   \
+				  value, 0x3, 30)
+#define SET_TX_DESC_ANT_MAPD_V1_NO_CLR(txdesc, value)                          \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc)->dword6, value, 0x3, 30)
+#define GET_TX_DESC_ANT_MAPD_V1(txdesc)                                        \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword6, 0x3,  \
+			      30)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8812F_SUPPORT)
+
+#define SET_TX_DESC_ANT_MAPD(txdesc, value)                                    \
+	HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword6,   \
+				  value, 0x3, 28)
+#define SET_TX_DESC_ANT_MAPD_NO_CLR(txdesc, value)                             \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc)->dword6, value, 0x3, 28)
+#define GET_TX_DESC_ANT_MAPD(txdesc)                                           \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword6, 0x3,  \
+			      28)
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+#define SET_TX_DESC_ANT_MAPC_V1(txdesc, value)                                 \
+	HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword6,   \
+				  value, 0x3, 28)
+#define SET_TX_DESC_ANT_MAPC_V1_NO_CLR(txdesc, value)                          \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc)->dword6, value, 0x3, 28)
+#define GET_TX_DESC_ANT_MAPC_V1(txdesc)                                        \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword6, 0x3,  \
+			      28)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8812F_SUPPORT)
+
+#define SET_TX_DESC_ANT_MAPC(txdesc, value)                                    \
+	HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword6,   \
+				  value, 0x3, 26)
+#define SET_TX_DESC_ANT_MAPC_NO_CLR(txdesc, value)                             \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc)->dword6, value, 0x3, 26)
+#define GET_TX_DESC_ANT_MAPC(txdesc)                                           \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword6, 0x3,  \
+			      26)
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+#define SET_TX_DESC_ANT_MAPB_V1(txdesc, value)                                 \
+	HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword6,   \
+				  value, 0x3, 26)
+#define SET_TX_DESC_ANT_MAPB_V1_NO_CLR(txdesc, value)                          \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc)->dword6, value, 0x3, 26)
+#define GET_TX_DESC_ANT_MAPB_V1(txdesc)                                        \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword6, 0x3,  \
+			      26)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8812F_SUPPORT)
+
+#define SET_TX_DESC_ANT_MAPB(txdesc, value)                                    \
+	HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword6,   \
+				  value, 0x3, 24)
+#define SET_TX_DESC_ANT_MAPB_NO_CLR(txdesc, value)                             \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc)->dword6, value, 0x3, 24)
+#define GET_TX_DESC_ANT_MAPB(txdesc)                                           \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword6, 0x3,  \
+			      24)
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+#define SET_TX_DESC_ANT_MAPA_V1(txdesc, value)                                 \
+	HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword6,   \
+				  value, 0x3, 24)
+#define SET_TX_DESC_ANT_MAPA_V1_NO_CLR(txdesc, value)                          \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc)->dword6, value, 0x3, 24)
+#define GET_TX_DESC_ANT_MAPA_V1(txdesc)                                        \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword6, 0x3,  \
+			      24)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8812F_SUPPORT)
+
+#define SET_TX_DESC_ANT_MAPA(txdesc, value)                                    \
+	HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword6,   \
+				  value, 0x3, 22)
+#define SET_TX_DESC_ANT_MAPA_NO_CLR(txdesc, value)                             \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc)->dword6, value, 0x3, 22)
+#define GET_TX_DESC_ANT_MAPA(txdesc)                                           \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword6, 0x3,  \
+			      22)
+#define SET_TX_DESC_ANTSEL_C(txdesc, value)                                    \
+	HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword6,   \
+				  value, 0x3, 20)
+#define SET_TX_DESC_ANTSEL_C_NO_CLR(txdesc, value)                             \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc)->dword6, value, 0x3, 20)
+#define GET_TX_DESC_ANTSEL_C(txdesc)                                           \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword6, 0x3,  \
+			      20)
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+#define SET_TX_DESC_ANTSEL_B_V1(txdesc, value)                                 \
+	HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword6,   \
+				  value, 0xf, 20)
+#define SET_TX_DESC_ANTSEL_B_V1_NO_CLR(txdesc, value)                          \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc)->dword6, value, 0xf, 20)
+#define GET_TX_DESC_ANTSEL_B_V1(txdesc)                                        \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword6, 0xf,  \
+			      20)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8812F_SUPPORT)
+
+#define SET_TX_DESC_ANTSEL_B(txdesc, value)                                    \
+	HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword6,   \
+				  value, 0x3, 18)
+#define SET_TX_DESC_ANTSEL_B_NO_CLR(txdesc, value)                             \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc)->dword6, value, 0x3, 18)
+#define GET_TX_DESC_ANTSEL_B(txdesc)                                           \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword6, 0x3,  \
+			      18)
+#define SET_TX_DESC_ANTSEL_A(txdesc, value)                                    \
+	HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword6,   \
+				  value, 0x3, 16)
+#define SET_TX_DESC_ANTSEL_A_NO_CLR(txdesc, value)                             \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc)->dword6, value, 0x3, 16)
+#define GET_TX_DESC_ANTSEL_A(txdesc)                                           \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword6, 0x3,  \
+			      16)
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+#define SET_TX_DESC_ANTSEL_A_V1(txdesc, value)                                 \
+	HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword6,   \
+				  value, 0xf, 16)
+#define SET_TX_DESC_ANTSEL_A_V1_NO_CLR(txdesc, value)                          \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc)->dword6, value, 0xf, 16)
+#define GET_TX_DESC_ANTSEL_A_V1(txdesc)                                        \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword6, 0xf,  \
+			      16)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT)
+
+#define SET_TX_DESC_MBSSID(txdesc, value)                                      \
+	HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword6,   \
+				  value, 0xf, 12)
+#define SET_TX_DESC_MBSSID_NO_CLR(txdesc, value)                               \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc)->dword6, value, 0xf, 12)
+#define GET_TX_DESC_MBSSID(txdesc)                                             \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword6, 0xf,  \
+			      12)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8812F_SUPPORT)
+
+#define SET_TX_DESC_SW_DEFINE(txdesc, value)                                   \
+	HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword6,   \
+				  value, 0xfff, 0)
+#define SET_TX_DESC_SW_DEFINE_NO_CLR(txdesc, value)                            \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc)->dword6, value, 0xfff, 0)
+#define GET_TX_DESC_SW_DEFINE(txdesc)                                          \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword6,       \
+			      0xfff, 0)
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+#define SET_TX_DESC_SWPS_SEQ(txdesc, value)                                    \
+	HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword6,   \
+				  value, 0xfff, 0)
+#define SET_TX_DESC_SWPS_SEQ_NO_CLR(txdesc, value)                             \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc)->dword6, value, 0xfff, 0)
+#define GET_TX_DESC_SWPS_SEQ(txdesc)                                           \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword6,       \
+			      0xfff, 0)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT)
+
+/*TXDESC_WORD7*/
+
+#define SET_TX_DESC_DMA_TXAGG_NUM(txdesc, value)                               \
+	HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword7,   \
+				  value, 0xff, 24)
+#define SET_TX_DESC_DMA_TXAGG_NUM_NO_CLR(txdesc, value)                        \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc)->dword7, value, 0xff, 24)
+#define GET_TX_DESC_DMA_TXAGG_NUM(txdesc)                                      \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword7, 0xff, \
+			      24)
+#define SET_TX_DESC_FINAL_DATA_RATE(txdesc, value)                             \
+	HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword7,   \
+				  value, 0xff, 24)
+#define SET_TX_DESC_FINAL_DATA_RATE_NO_CLR(txdesc, value)                      \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc)->dword7, value, 0xff, 24)
+#define GET_TX_DESC_FINAL_DATA_RATE(txdesc)                                    \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword7, 0xff, \
+			      24)
+#define SET_TX_DESC_NTX_MAP(txdesc, value)                                     \
+	HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword7,   \
+				  value, 0xf, 20)
+#define SET_TX_DESC_NTX_MAP_NO_CLR(txdesc, value)                              \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc)->dword7, value, 0xf, 20)
+#define GET_TX_DESC_NTX_MAP(txdesc)                                            \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword7, 0xf,  \
+			      20)
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+#define SET_TX_DESC_ANTSEL_EN(txdesc, value)                                   \
+	HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword7,   \
+				  value, 0x1, 19)
+#define SET_TX_DESC_ANTSEL_EN_NO_CLR(txdesc, value)                            \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc)->dword7, value, 0x1, 19)
+#define GET_TX_DESC_ANTSEL_EN(txdesc)                                          \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword7, 0x1,  \
+			      19)
+#define SET_TX_DESC_MBSSID_EX(txdesc, value)                                   \
+	HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword7,   \
+				  value, 0x7, 16)
+#define SET_TX_DESC_MBSSID_EX_NO_CLR(txdesc, value)                            \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc)->dword7, value, 0x7, 16)
+#define GET_TX_DESC_MBSSID_EX(txdesc)                                          \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword7, 0x7,  \
+			      16)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT)
+
+#define SET_TX_DESC_TX_BUFF_SIZE(txdesc, value)                                \
+	HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword7,   \
+				  value, 0xffff, 0)
+#define SET_TX_DESC_TX_BUFF_SIZE_NO_CLR(txdesc, value)                         \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc)->dword7, value, 0xffff, 0)
+#define GET_TX_DESC_TX_BUFF_SIZE(txdesc)                                       \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword7,       \
+			      0xffff, 0)
+#define SET_TX_DESC_TXDESC_CHECKSUM(txdesc, value)                             \
+	HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword7,   \
+				  value, 0xffff, 0)
+#define SET_TX_DESC_TXDESC_CHECKSUM_NO_CLR(txdesc, value)                      \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc)->dword7, value, 0xffff, 0)
+#define GET_TX_DESC_TXDESC_CHECKSUM(txdesc)                                    \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword7,       \
+			      0xffff, 0)
+#define SET_TX_DESC_TIMESTAMP(txdesc, value)                                   \
+	HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword7,   \
+				  value, 0xffff, 0)
+#define SET_TX_DESC_TIMESTAMP_NO_CLR(txdesc, value)                            \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc)->dword7, value, 0xffff, 0)
+#define GET_TX_DESC_TIMESTAMP(txdesc)                                          \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword7,       \
+			      0xffff, 0)
+
+/*TXDESC_WORD8*/
+
+#define SET_TX_DESC_TXWIFI_CP(txdesc, value)                                   \
+	HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword8,   \
+				  value, 0x1, 31)
+#define SET_TX_DESC_TXWIFI_CP_NO_CLR(txdesc, value)                            \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc)->dword8, value, 0x1, 31)
+#define GET_TX_DESC_TXWIFI_CP(txdesc)                                          \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword8, 0x1,  \
+			      31)
+#define SET_TX_DESC_MAC_CP(txdesc, value)                                      \
+	HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword8,   \
+				  value, 0x1, 30)
+#define SET_TX_DESC_MAC_CP_NO_CLR(txdesc, value)                               \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc)->dword8, value, 0x1, 30)
+#define GET_TX_DESC_MAC_CP(txdesc)                                             \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword8, 0x1,  \
+			      30)
+#define SET_TX_DESC_STW_PKTRE_DIS(txdesc, value)                               \
+	HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword8,   \
+				  value, 0x1, 29)
+#define SET_TX_DESC_STW_PKTRE_DIS_NO_CLR(txdesc, value)                        \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc)->dword8, value, 0x1, 29)
+#define GET_TX_DESC_STW_PKTRE_DIS(txdesc)                                      \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword8, 0x1,  \
+			      29)
+#define SET_TX_DESC_STW_RB_DIS(txdesc, value)                                  \
+	HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword8,   \
+				  value, 0x1, 28)
+#define SET_TX_DESC_STW_RB_DIS_NO_CLR(txdesc, value)                           \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc)->dword8, value, 0x1, 28)
+#define GET_TX_DESC_STW_RB_DIS(txdesc)                                         \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword8, 0x1,  \
+			      28)
+#define SET_TX_DESC_STW_RATE_DIS(txdesc, value)                                \
+	HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword8,   \
+				  value, 0x1, 27)
+#define SET_TX_DESC_STW_RATE_DIS_NO_CLR(txdesc, value)                         \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc)->dword8, value, 0x1, 27)
+#define GET_TX_DESC_STW_RATE_DIS(txdesc)                                       \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword8, 0x1,  \
+			      27)
+#define SET_TX_DESC_STW_ANT_DIS(txdesc, value)                                 \
+	HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword8,   \
+				  value, 0x1, 26)
+#define SET_TX_DESC_STW_ANT_DIS_NO_CLR(txdesc, value)                          \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc)->dword8, value, 0x1, 26)
+#define GET_TX_DESC_STW_ANT_DIS(txdesc)                                        \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword8, 0x1,  \
+			      26)
+#define SET_TX_DESC_STW_EN(txdesc, value)                                      \
+	HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword8,   \
+				  value, 0x1, 25)
+#define SET_TX_DESC_STW_EN_NO_CLR(txdesc, value)                               \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc)->dword8, value, 0x1, 25)
+#define GET_TX_DESC_STW_EN(txdesc)                                             \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword8, 0x1,  \
+			      25)
+#define SET_TX_DESC_SMH_EN(txdesc, value)                                      \
+	HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword8,   \
+				  value, 0x1, 24)
+#define SET_TX_DESC_SMH_EN_NO_CLR(txdesc, value)                               \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc)->dword8, value, 0x1, 24)
+#define GET_TX_DESC_SMH_EN(txdesc)                                             \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword8, 0x1,  \
+			      24)
+#define SET_TX_DESC_TAILPAGE_L(txdesc, value)                                  \
+	HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword8,   \
+				  value, 0xff, 24)
+#define SET_TX_DESC_TAILPAGE_L_NO_CLR(txdesc, value)                           \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc)->dword8, value, 0xff, 24)
+#define GET_TX_DESC_TAILPAGE_L(txdesc)                                         \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword8, 0xff, \
+			      24)
+#define SET_TX_DESC_SDIO_DMASEQ(txdesc, value)                                 \
+	HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword8,   \
+				  value, 0xff, 16)
+#define SET_TX_DESC_SDIO_DMASEQ_NO_CLR(txdesc, value)                          \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc)->dword8, value, 0xff, 16)
+#define GET_TX_DESC_SDIO_DMASEQ(txdesc)                                        \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword8, 0xff, \
+			      16)
+#define SET_TX_DESC_NEXTHEADPAGE_L(txdesc, value)                              \
+	HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword8,   \
+				  value, 0xff, 16)
+#define SET_TX_DESC_NEXTHEADPAGE_L_NO_CLR(txdesc, value)                       \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc)->dword8, value, 0xff, 16)
+#define GET_TX_DESC_NEXTHEADPAGE_L(txdesc)                                     \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword8, 0xff, \
+			      16)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define SET_TX_DESC_EN_HWSEQ(txdesc, value)                                    \
+	HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword8,   \
+				  value, 0x1, 15)
+#define SET_TX_DESC_EN_HWSEQ_NO_CLR(txdesc, value)                             \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc)->dword8, value, 0x1, 15)
+#define GET_TX_DESC_EN_HWSEQ(txdesc)                                           \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword8, 0x1,  \
+			      15)
+#define SET_TX_DESC_EN_HWEXSEQ(txdesc, value)                                  \
+	HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword8,   \
+				  value, 0x1, 14)
+#define SET_TX_DESC_EN_HWEXSEQ_NO_CLR(txdesc, value)                           \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc)->dword8, value, 0x1, 14)
+#define GET_TX_DESC_EN_HWEXSEQ(txdesc)                                         \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword8, 0x1,  \
+			      14)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT)
+
+#define SET_TX_DESC_EN_HWSEQ_MODE(txdesc, value)                               \
+	HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword8,   \
+				  value, 0x3, 14)
+#define SET_TX_DESC_EN_HWSEQ_MODE_NO_CLR(txdesc, value)                        \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc)->dword8, value, 0x3, 14)
+#define GET_TX_DESC_EN_HWSEQ_MODE(txdesc)                                      \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword8, 0x3,  \
+			      14)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT)
+
+#define SET_TX_DESC_DATA_RC(txdesc, value)                                     \
+	HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword8,   \
+				  value, 0x3f, 8)
+#define SET_TX_DESC_DATA_RC_NO_CLR(txdesc, value)                              \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc)->dword8, value, 0x3f, 8)
+#define GET_TX_DESC_DATA_RC(txdesc)                                            \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword8, 0x3f, \
+			      8)
+#define SET_TX_DESC_BAR_RTY_TH(txdesc, value)                                  \
+	HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword8,   \
+				  value, 0x3, 6)
+#define SET_TX_DESC_BAR_RTY_TH_NO_CLR(txdesc, value)                           \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc)->dword8, value, 0x3, 6)
+#define GET_TX_DESC_BAR_RTY_TH(txdesc)                                         \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword8, 0x3, 6)
+#define SET_TX_DESC_RTS_RC(txdesc, value)                                      \
+	HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword8,   \
+				  value, 0x3f, 0)
+#define SET_TX_DESC_RTS_RC_NO_CLR(txdesc, value)                               \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc)->dword8, value, 0x3f, 0)
+#define GET_TX_DESC_RTS_RC(txdesc)                                             \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword8, 0x3f, \
+			      0)
+
+/*TXDESC_WORD9*/
+
+#define SET_TX_DESC_TAILPAGE_H(txdesc, value)                                  \
+	HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword9,   \
+				  value, 0xf, 28)
+#define SET_TX_DESC_TAILPAGE_H_NO_CLR(txdesc, value)                           \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc)->dword9, value, 0xf, 28)
+#define GET_TX_DESC_TAILPAGE_H(txdesc)                                         \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword9, 0xf,  \
+			      28)
+#define SET_TX_DESC_NEXTHEADPAGE_H(txdesc, value)                              \
+	HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword9,   \
+				  value, 0xf, 24)
+#define SET_TX_DESC_NEXTHEADPAGE_H_NO_CLR(txdesc, value)                       \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc)->dword9, value, 0xf, 24)
+#define GET_TX_DESC_NEXTHEADPAGE_H(txdesc)                                     \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword9, 0xf,  \
+			      24)
+#define SET_TX_DESC_SW_SEQ(txdesc, value)                                      \
+	HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword9,   \
+				  value, 0xfff, 12)
+#define SET_TX_DESC_SW_SEQ_NO_CLR(txdesc, value)                               \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc)->dword9, value, 0xfff, 12)
+#define GET_TX_DESC_SW_SEQ(txdesc)                                             \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword9,       \
+			      0xfff, 12)
+#define SET_TX_DESC_TXBF_PATH(txdesc, value)                                   \
+	HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword9,   \
+				  value, 0x1, 11)
+#define SET_TX_DESC_TXBF_PATH_NO_CLR(txdesc, value)                            \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc)->dword9, value, 0x1, 11)
+#define GET_TX_DESC_TXBF_PATH(txdesc)                                          \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword9, 0x1,  \
+			      11)
+#define SET_TX_DESC_PADDING_LEN(txdesc, value)                                 \
+	HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword9,   \
+				  value, 0x7ff, 0)
+#define SET_TX_DESC_PADDING_LEN_NO_CLR(txdesc, value)                          \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc)->dword9, value, 0x7ff, 0)
+#define GET_TX_DESC_PADDING_LEN(txdesc)                                        \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword9,       \
+			      0x7ff, 0)
+#define SET_TX_DESC_GROUP_BIT_IE_OFFSET(txdesc, value)                         \
+	HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword9,   \
+				  value, 0xff, 0)
+#define SET_TX_DESC_GROUP_BIT_IE_OFFSET_NO_CLR(txdesc, value)                  \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc)->dword9, value, 0xff, 0)
+#define GET_TX_DESC_GROUP_BIT_IE_OFFSET(txdesc)                                \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword9, 0xff, \
+			      0)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT)
+
+/*WORD10*/
+
+#define SET_TX_DESC_HT_DATA_SND(txdesc, value)                                 \
+	HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword10,  \
+				  value, 0x1, 31)
+#define SET_TX_DESC_HT_DATA_SND_NO_CLR(txdesc, value)                          \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc)->dword10, value, 0x1, 31)
+#define GET_TX_DESC_HT_DATA_SND(txdesc)                                        \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword10, 0x1, \
+			      31)
+#define SET_TX_DESC_SHCUT_CAM(txdesc, value)                                   \
+	HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword10,  \
+				  value, 0x3f, 16)
+#define SET_TX_DESC_SHCUT_CAM_NO_CLR(txdesc, value)                            \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc)->dword10, value, 0x3f, 16)
+#define GET_TX_DESC_SHCUT_CAM(txdesc)                                          \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword10,      \
+			      0x3f, 16)
+
+#endif
+
+#if (HALMAC_8822B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT)
+
+#define SET_TX_DESC_MU_DATARATE(txdesc, value)                                 \
+	HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword10,  \
+				  value, 0xff, 8)
+#define SET_TX_DESC_MU_DATARATE_NO_CLR(txdesc, value)                          \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc)->dword10, value, 0xff, 8)
+#define GET_TX_DESC_MU_DATARATE(txdesc)                                        \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword10,      \
+			      0xff, 8)
+#define SET_TX_DESC_MU_RC(txdesc, value)                                       \
+	HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword10,  \
+				  value, 0xf, 4)
+#define SET_TX_DESC_MU_RC_NO_CLR(txdesc, value)                                \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc)->dword10, value, 0xf, 4)
+#define GET_TX_DESC_MU_RC(txdesc)                                              \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword10, 0xf, \
+			      4)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT)
+
+#define SET_TX_DESC_NDPA_RATE_SEL(txdesc, value)                               \
+	HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword10,  \
+				  value, 0x1, 3)
+#define SET_TX_DESC_NDPA_RATE_SEL_NO_CLR(txdesc, value)                        \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc)->dword10, value, 0x1, 3)
+#define GET_TX_DESC_NDPA_RATE_SEL(txdesc)                                      \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword10, 0x1, \
+			      3)
+#define SET_TX_DESC_HW_NDPA_EN(txdesc, value)                                  \
+	HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword10,  \
+				  value, 0x1, 2)
+#define SET_TX_DESC_HW_NDPA_EN_NO_CLR(txdesc, value)                           \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc)->dword10, value, 0x1, 2)
+#define GET_TX_DESC_HW_NDPA_EN(txdesc)                                         \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword10, 0x1, \
+			      2)
+
+#endif
+
+#if (HALMAC_8822B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT)
+
+#define SET_TX_DESC_SND_PKT_SEL(txdesc, value)                                 \
+	HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword10,  \
+				  value, 0x3, 0)
+#define SET_TX_DESC_SND_PKT_SEL_NO_CLR(txdesc, value)                          \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc)->dword10, value, 0x3, 0)
+#define GET_TX_DESC_SND_PKT_SEL(txdesc)                                        \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword10, 0x3, \
+			      0)
+
+#endif
+
+#endif
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/halmac/halmac_tx_desc_buffer_ap.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/halmac/halmac_tx_desc_buffer_ap.h
--- linux-5.6.3/3rdparty/rtl8821ce/hal/halmac/halmac_tx_desc_buffer_ap.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/halmac/halmac_tx_desc_buffer_ap.h	2020-04-10 16:35:06.817660114 +0300
@@ -0,0 +1,1078 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ ******************************************************************************/
+
+#ifndef _HALMAC_TX_DESC_BUFFER_AP_H_
+#define _HALMAC_TX_DESC_BUFFER_AP_H_
+#if (HALMAC_8814B_SUPPORT)
+
+/*TXDESC_WORD0*/
+
+#define SET_TX_DESC_BUFFER_RDG_EN(txdesc, value)                               \
+	HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword0,   \
+				  value, 0x1, 31)
+#define SET_TX_DESC_BUFFER_RDG_EN_NO_CLR(txdesc, value)                        \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc)->dword0, value, 0x1, 31)
+#define GET_TX_DESC_BUFFER_RDG_EN(txdesc)                                      \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword0, 0x1,  \
+			      31)
+#define SET_TX_DESC_BUFFER_BCNPKT_TSF_CTRL(txdesc, value)                      \
+	HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword0,   \
+				  value, 0x1, 30)
+#define SET_TX_DESC_BUFFER_BCNPKT_TSF_CTRL_NO_CLR(txdesc, value)               \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc)->dword0, value, 0x1, 30)
+#define GET_TX_DESC_BUFFER_BCNPKT_TSF_CTRL(txdesc)                             \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword0, 0x1,  \
+			      30)
+#define SET_TX_DESC_BUFFER_AGG_EN(txdesc, value)                               \
+	HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword0,   \
+				  value, 0x1, 29)
+#define SET_TX_DESC_BUFFER_AGG_EN_NO_CLR(txdesc, value)                        \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc)->dword0, value, 0x1, 29)
+#define GET_TX_DESC_BUFFER_AGG_EN(txdesc)                                      \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword0, 0x1,  \
+			      29)
+#define SET_TX_DESC_BUFFER_PKT_OFFSET(txdesc, value)                           \
+	HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword0,   \
+				  value, 0x1f, 24)
+#define SET_TX_DESC_BUFFER_PKT_OFFSET_NO_CLR(txdesc, value)                    \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc)->dword0, value, 0x1f, 24)
+#define GET_TX_DESC_BUFFER_PKT_OFFSET(txdesc)                                  \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword0, 0x1f, \
+			      24)
+#define SET_TX_DESC_BUFFER_OFFSET(txdesc, value)                               \
+	HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword0,   \
+				  value, 0xff, 16)
+#define SET_TX_DESC_BUFFER_OFFSET_NO_CLR(txdesc, value)                        \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc)->dword0, value, 0xff, 16)
+#define GET_TX_DESC_BUFFER_OFFSET(txdesc)                                      \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword0, 0xff, \
+			      16)
+#define SET_TX_DESC_BUFFER_TXPKTSIZE(txdesc, value)                            \
+	HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword0,   \
+				  value, 0xffff, 0)
+#define SET_TX_DESC_BUFFER_TXPKTSIZE_NO_CLR(txdesc, value)                     \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc)->dword0, value, 0xffff, 0)
+#define GET_TX_DESC_BUFFER_TXPKTSIZE(txdesc)                                   \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword0,       \
+			      0xffff, 0)
+
+/*TXDESC_WORD1*/
+
+#define SET_TX_DESC_BUFFER_USERATE(txdesc, value)                              \
+	HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword1,   \
+				  value, 0x1, 31)
+#define SET_TX_DESC_BUFFER_USERATE_NO_CLR(txdesc, value)                       \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc)->dword1, value, 0x1, 31)
+#define GET_TX_DESC_BUFFER_USERATE(txdesc)                                     \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword1, 0x1,  \
+			      31)
+#define SET_TX_DESC_BUFFER_AMSDU(txdesc, value)                                \
+	HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword1,   \
+				  value, 0x1, 30)
+#define SET_TX_DESC_BUFFER_AMSDU_NO_CLR(txdesc, value)                         \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc)->dword1, value, 0x1, 30)
+#define GET_TX_DESC_BUFFER_AMSDU(txdesc)                                       \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword1, 0x1,  \
+			      30)
+#define SET_TX_DESC_BUFFER_EN_HWSEQ(txdesc, value)                             \
+	HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword1,   \
+				  value, 0x1, 29)
+#define SET_TX_DESC_BUFFER_EN_HWSEQ_NO_CLR(txdesc, value)                      \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc)->dword1, value, 0x1, 29)
+#define GET_TX_DESC_BUFFER_EN_HWSEQ(txdesc)                                    \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword1, 0x1,  \
+			      29)
+#define SET_TX_DESC_BUFFER_EN_HWEXSEQ(txdesc, value)                           \
+	HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword1,   \
+				  value, 0x1, 28)
+#define SET_TX_DESC_BUFFER_EN_HWEXSEQ_NO_CLR(txdesc, value)                    \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc)->dword1, value, 0x1, 28)
+#define GET_TX_DESC_BUFFER_EN_HWEXSEQ(txdesc)                                  \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword1, 0x1,  \
+			      28)
+#define SET_TX_DESC_BUFFER_SW_SEQ(txdesc, value)                               \
+	HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword1,   \
+				  value, 0xfff, 16)
+#define SET_TX_DESC_BUFFER_SW_SEQ_NO_CLR(txdesc, value)                        \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc)->dword1, value, 0xfff, 16)
+#define GET_TX_DESC_BUFFER_SW_SEQ(txdesc)                                      \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword1,       \
+			      0xfff, 16)
+#define SET_TX_DESC_BUFFER_DROP_ID(txdesc, value)                              \
+	HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword1,   \
+				  value, 0x3, 14)
+#define SET_TX_DESC_BUFFER_DROP_ID_NO_CLR(txdesc, value)                       \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc)->dword1, value, 0x3, 14)
+#define GET_TX_DESC_BUFFER_DROP_ID(txdesc)                                     \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword1, 0x3,  \
+			      14)
+#define SET_TX_DESC_BUFFER_MOREDATA(txdesc, value)                             \
+	HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword1,   \
+				  value, 0x1, 13)
+#define SET_TX_DESC_BUFFER_MOREDATA_NO_CLR(txdesc, value)                      \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc)->dword1, value, 0x1, 13)
+#define GET_TX_DESC_BUFFER_MOREDATA(txdesc)                                    \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword1, 0x1,  \
+			      13)
+#define SET_TX_DESC_BUFFER_QSEL(txdesc, value)                                 \
+	HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword1,   \
+				  value, 0x1f, 8)
+#define SET_TX_DESC_BUFFER_QSEL_NO_CLR(txdesc, value)                          \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc)->dword1, value, 0x1f, 8)
+#define GET_TX_DESC_BUFFER_QSEL(txdesc)                                        \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword1, 0x1f, \
+			      8)
+#define SET_TX_DESC_BUFFER_MACID(txdesc, value)                                \
+	HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword1,   \
+				  value, 0xff, 0)
+#define SET_TX_DESC_BUFFER_MACID_NO_CLR(txdesc, value)                         \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc)->dword1, value, 0xff, 0)
+#define GET_TX_DESC_BUFFER_MACID(txdesc)                                       \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword1, 0xff, \
+			      0)
+
+/*TXDESC_WORD2*/
+
+#define SET_TX_DESC_BUFFER_CHK_EN(txdesc, value)                               \
+	HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword2,   \
+				  value, 0x1, 31)
+#define SET_TX_DESC_BUFFER_CHK_EN_NO_CLR(txdesc, value)                        \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc)->dword2, value, 0x1, 31)
+#define GET_TX_DESC_BUFFER_CHK_EN(txdesc)                                      \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword2, 0x1,  \
+			      31)
+#define SET_TX_DESC_BUFFER_DISQSELSEQ(txdesc, value)                           \
+	HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword2,   \
+				  value, 0x1, 30)
+#define SET_TX_DESC_BUFFER_DISQSELSEQ_NO_CLR(txdesc, value)                    \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc)->dword2, value, 0x1, 30)
+#define GET_TX_DESC_BUFFER_DISQSELSEQ(txdesc)                                  \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword2, 0x1,  \
+			      30)
+#define SET_TX_DESC_BUFFER_SND_PKT_SEL(txdesc, value)                          \
+	HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword2,   \
+				  value, 0x3, 28)
+#define SET_TX_DESC_BUFFER_SND_PKT_SEL_NO_CLR(txdesc, value)                   \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc)->dword2, value, 0x3, 28)
+#define GET_TX_DESC_BUFFER_SND_PKT_SEL(txdesc)                                 \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword2, 0x3,  \
+			      28)
+#define SET_TX_DESC_BUFFER_DMA_PRI(txdesc, value)                              \
+	HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword2,   \
+				  value, 0x1, 27)
+#define SET_TX_DESC_BUFFER_DMA_PRI_NO_CLR(txdesc, value)                       \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc)->dword2, value, 0x1, 27)
+#define GET_TX_DESC_BUFFER_DMA_PRI(txdesc)                                     \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword2, 0x1,  \
+			      27)
+#define SET_TX_DESC_BUFFER_MAX_AMSDU_MODE(txdesc, value)                       \
+	HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword2,   \
+				  value, 0x7, 24)
+#define SET_TX_DESC_BUFFER_MAX_AMSDU_MODE_NO_CLR(txdesc, value)                \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc)->dword2, value, 0x7, 24)
+#define GET_TX_DESC_BUFFER_MAX_AMSDU_MODE(txdesc)                              \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword2, 0x7,  \
+			      24)
+#define SET_TX_DESC_BUFFER_DMA_TXAGG_NUM(txdesc, value)                        \
+	HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword2,   \
+				  value, 0xff, 16)
+#define SET_TX_DESC_BUFFER_DMA_TXAGG_NUM_NO_CLR(txdesc, value)                 \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc)->dword2, value, 0xff, 16)
+#define GET_TX_DESC_BUFFER_DMA_TXAGG_NUM(txdesc)                               \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword2, 0xff, \
+			      16)
+#define SET_TX_DESC_BUFFER_TXDESC_CHECKSUM(txdesc, value)                      \
+	HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword2,   \
+				  value, 0xffff, 0)
+#define SET_TX_DESC_BUFFER_TXDESC_CHECKSUM_NO_CLR(txdesc, value)               \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc)->dword2, value, 0xffff, 0)
+#define GET_TX_DESC_BUFFER_TXDESC_CHECKSUM(txdesc)                             \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword2,       \
+			      0xffff, 0)
+
+/*TXDESC_WORD3*/
+
+#define SET_TX_DESC_BUFFER_OFFLOAD_SIZE(txdesc, value)                         \
+	HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword3,   \
+				  value, 0x7fff, 16)
+#define SET_TX_DESC_BUFFER_OFFLOAD_SIZE_NO_CLR(txdesc, value)                  \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc)->dword3, value, 0x7fff, 16)
+#define GET_TX_DESC_BUFFER_OFFLOAD_SIZE(txdesc)                                \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword3,       \
+			      0x7fff, 16)
+#define SET_TX_DESC_BUFFER_CHANNEL_DMA(txdesc, value)                          \
+	HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword3,   \
+				  value, 0x1f, 11)
+#define SET_TX_DESC_BUFFER_CHANNEL_DMA_NO_CLR(txdesc, value)                   \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc)->dword3, value, 0x1f, 11)
+#define GET_TX_DESC_BUFFER_CHANNEL_DMA(txdesc)                                 \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword3, 0x1f, \
+			      11)
+#define SET_TX_DESC_BUFFER_MBSSID(txdesc, value)                               \
+	HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword3,   \
+				  value, 0xf, 7)
+#define SET_TX_DESC_BUFFER_MBSSID_NO_CLR(txdesc, value)                        \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc)->dword3, value, 0xf, 7)
+#define GET_TX_DESC_BUFFER_MBSSID(txdesc)                                      \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword3, 0xf, 7)
+#define SET_TX_DESC_BUFFER_BK(txdesc, value)                                   \
+	HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword3,   \
+				  value, 0x1, 6)
+#define SET_TX_DESC_BUFFER_BK_NO_CLR(txdesc, value)                            \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc)->dword3, value, 0x1, 6)
+#define GET_TX_DESC_BUFFER_BK(txdesc)                                          \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword3, 0x1, 6)
+#define SET_TX_DESC_BUFFER_WHEADER_LEN(txdesc, value)                          \
+	HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword3,   \
+				  value, 0x1f, 0)
+#define SET_TX_DESC_BUFFER_WHEADER_LEN_NO_CLR(txdesc, value)                   \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc)->dword3, value, 0x1f, 0)
+#define GET_TX_DESC_BUFFER_WHEADER_LEN(txdesc)                                 \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword3, 0x1f, \
+			      0)
+
+/*TXDESC_WORD4*/
+
+#define SET_TX_DESC_BUFFER_TRY_RATE(txdesc, value)                             \
+	HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword4,   \
+				  value, 0x1, 26)
+#define SET_TX_DESC_BUFFER_TRY_RATE_NO_CLR(txdesc, value)                      \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc)->dword4, value, 0x1, 26)
+#define GET_TX_DESC_BUFFER_TRY_RATE(txdesc)                                    \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword4, 0x1,  \
+			      26)
+#define SET_TX_DESC_BUFFER_DATA_BW(txdesc, value)                              \
+	HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword4,   \
+				  value, 0x3, 24)
+#define SET_TX_DESC_BUFFER_DATA_BW_NO_CLR(txdesc, value)                       \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc)->dword4, value, 0x3, 24)
+#define GET_TX_DESC_BUFFER_DATA_BW(txdesc)                                     \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword4, 0x3,  \
+			      24)
+#define SET_TX_DESC_BUFFER_DATA_SHORT(txdesc, value)                           \
+	HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword4,   \
+				  value, 0x1, 23)
+#define SET_TX_DESC_BUFFER_DATA_SHORT_NO_CLR(txdesc, value)                    \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc)->dword4, value, 0x1, 23)
+#define GET_TX_DESC_BUFFER_DATA_SHORT(txdesc)                                  \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword4, 0x1,  \
+			      23)
+#define SET_TX_DESC_BUFFER_DATARATE(txdesc, value)                             \
+	HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword4,   \
+				  value, 0x7f, 16)
+#define SET_TX_DESC_BUFFER_DATARATE_NO_CLR(txdesc, value)                      \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc)->dword4, value, 0x7f, 16)
+#define GET_TX_DESC_BUFFER_DATARATE(txdesc)                                    \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword4, 0x7f, \
+			      16)
+#define SET_TX_DESC_BUFFER_TXBF_PATH(txdesc, value)                            \
+	HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword4,   \
+				  value, 0x1, 11)
+#define SET_TX_DESC_BUFFER_TXBF_PATH_NO_CLR(txdesc, value)                     \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc)->dword4, value, 0x1, 11)
+#define GET_TX_DESC_BUFFER_TXBF_PATH(txdesc)                                   \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword4, 0x1,  \
+			      11)
+#define SET_TX_DESC_BUFFER_GROUP_BIT_IE_OFFSET(txdesc, value)                  \
+	HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword4,   \
+				  value, 0x7ff, 0)
+#define SET_TX_DESC_BUFFER_GROUP_BIT_IE_OFFSET_NO_CLR(txdesc, value)           \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc)->dword4, value, 0x7ff, 0)
+#define GET_TX_DESC_BUFFER_GROUP_BIT_IE_OFFSET(txdesc)                         \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword4,       \
+			      0x7ff, 0)
+
+/*TXDESC_WORD5*/
+
+#define SET_TX_DESC_BUFFER_RTY_LMT_EN(txdesc, value)                           \
+	HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword5,   \
+				  value, 0x1, 31)
+#define SET_TX_DESC_BUFFER_RTY_LMT_EN_NO_CLR(txdesc, value)                    \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc)->dword5, value, 0x1, 31)
+#define GET_TX_DESC_BUFFER_RTY_LMT_EN(txdesc)                                  \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword5, 0x1,  \
+			      31)
+#define SET_TX_DESC_BUFFER_HW_RTS_EN(txdesc, value)                            \
+	HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword5,   \
+				  value, 0x1, 30)
+#define SET_TX_DESC_BUFFER_HW_RTS_EN_NO_CLR(txdesc, value)                     \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc)->dword5, value, 0x1, 30)
+#define GET_TX_DESC_BUFFER_HW_RTS_EN(txdesc)                                   \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword5, 0x1,  \
+			      30)
+#define SET_TX_DESC_BUFFER_RTS_EN(txdesc, value)                               \
+	HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword5,   \
+				  value, 0x1, 29)
+#define SET_TX_DESC_BUFFER_RTS_EN_NO_CLR(txdesc, value)                        \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc)->dword5, value, 0x1, 29)
+#define GET_TX_DESC_BUFFER_RTS_EN(txdesc)                                      \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword5, 0x1,  \
+			      29)
+#define SET_TX_DESC_BUFFER_CTS2SELF(txdesc, value)                             \
+	HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword5,   \
+				  value, 0x1, 28)
+#define SET_TX_DESC_BUFFER_CTS2SELF_NO_CLR(txdesc, value)                      \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc)->dword5, value, 0x1, 28)
+#define GET_TX_DESC_BUFFER_CTS2SELF(txdesc)                                    \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword5, 0x1,  \
+			      28)
+#define SET_TX_DESC_BUFFER_TAILPAGE_H(txdesc, value)                           \
+	HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword5,   \
+				  value, 0xf, 24)
+#define SET_TX_DESC_BUFFER_TAILPAGE_H_NO_CLR(txdesc, value)                    \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc)->dword5, value, 0xf, 24)
+#define GET_TX_DESC_BUFFER_TAILPAGE_H(txdesc)                                  \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword5, 0xf,  \
+			      24)
+#define SET_TX_DESC_BUFFER_TAILPAGE_L(txdesc, value)                           \
+	HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword5,   \
+				  value, 0xff, 16)
+#define SET_TX_DESC_BUFFER_TAILPAGE_L_NO_CLR(txdesc, value)                    \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc)->dword5, value, 0xff, 16)
+#define GET_TX_DESC_BUFFER_TAILPAGE_L(txdesc)                                  \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword5, 0xff, \
+			      16)
+#define SET_TX_DESC_BUFFER_NAVUSEHDR(txdesc, value)                            \
+	HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword5,   \
+				  value, 0x1, 15)
+#define SET_TX_DESC_BUFFER_NAVUSEHDR_NO_CLR(txdesc, value)                     \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc)->dword5, value, 0x1, 15)
+#define GET_TX_DESC_BUFFER_NAVUSEHDR(txdesc)                                   \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword5, 0x1,  \
+			      15)
+#define SET_TX_DESC_BUFFER_BMC(txdesc, value)                                  \
+	HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword5,   \
+				  value, 0x1, 14)
+#define SET_TX_DESC_BUFFER_BMC_NO_CLR(txdesc, value)                           \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc)->dword5, value, 0x1, 14)
+#define GET_TX_DESC_BUFFER_BMC(txdesc)                                         \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword5, 0x1,  \
+			      14)
+#define SET_TX_DESC_BUFFER_RTS_DATA_RTY_LMT(txdesc, value)                     \
+	HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword5,   \
+				  value, 0x3f, 8)
+#define SET_TX_DESC_BUFFER_RTS_DATA_RTY_LMT_NO_CLR(txdesc, value)              \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc)->dword5, value, 0x3f, 8)
+#define GET_TX_DESC_BUFFER_RTS_DATA_RTY_LMT(txdesc)                            \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword5, 0x3f, \
+			      8)
+#define SET_TX_DESC_BUFFER_HW_AES_IV(txdesc, value)                            \
+	HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword5,   \
+				  value, 0x1, 7)
+#define SET_TX_DESC_BUFFER_HW_AES_IV_NO_CLR(txdesc, value)                     \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc)->dword5, value, 0x1, 7)
+#define GET_TX_DESC_BUFFER_HW_AES_IV(txdesc)                                   \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword5, 0x1, 7)
+#define SET_TX_DESC_BUFFER_BT_NULL(txdesc, value)                              \
+	HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword5,   \
+				  value, 0x1, 3)
+#define SET_TX_DESC_BUFFER_BT_NULL_NO_CLR(txdesc, value)                       \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc)->dword5, value, 0x1, 3)
+#define GET_TX_DESC_BUFFER_BT_NULL(txdesc)                                     \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword5, 0x1, 3)
+#define SET_TX_DESC_BUFFER_EN_DESC_ID(txdesc, value)                           \
+	HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword5,   \
+				  value, 0x1, 2)
+#define SET_TX_DESC_BUFFER_EN_DESC_ID_NO_CLR(txdesc, value)                    \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc)->dword5, value, 0x1, 2)
+#define GET_TX_DESC_BUFFER_EN_DESC_ID(txdesc)                                  \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword5, 0x1, 2)
+#define SET_TX_DESC_BUFFER_SECTYPE(txdesc, value)                              \
+	HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword5,   \
+				  value, 0x3, 0)
+#define SET_TX_DESC_BUFFER_SECTYPE_NO_CLR(txdesc, value)                       \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc)->dword5, value, 0x3, 0)
+#define GET_TX_DESC_BUFFER_SECTYPE(txdesc)                                     \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword5, 0x3, 0)
+
+/*TXDESC_WORD6*/
+
+#define SET_TX_DESC_BUFFER_MULTIPLE_PORT(txdesc, value)                        \
+	HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword6,   \
+				  value, 0x7, 29)
+#define SET_TX_DESC_BUFFER_MULTIPLE_PORT_NO_CLR(txdesc, value)                 \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc)->dword6, value, 0x7, 29)
+#define GET_TX_DESC_BUFFER_MULTIPLE_PORT(txdesc)                               \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword6, 0x7,  \
+			      29)
+#define SET_TX_DESC_BUFFER_POLLUTED(txdesc, value)                             \
+	HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword6,   \
+				  value, 0x1, 28)
+#define SET_TX_DESC_BUFFER_POLLUTED_NO_CLR(txdesc, value)                      \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc)->dword6, value, 0x1, 28)
+#define GET_TX_DESC_BUFFER_POLLUTED(txdesc)                                    \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword6, 0x1,  \
+			      28)
+#define SET_TX_DESC_BUFFER_NULL_1(txdesc, value)                               \
+	HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword6,   \
+				  value, 0x1, 27)
+#define SET_TX_DESC_BUFFER_NULL_1_NO_CLR(txdesc, value)                        \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc)->dword6, value, 0x1, 27)
+#define GET_TX_DESC_BUFFER_NULL_1(txdesc)                                      \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword6, 0x1,  \
+			      27)
+#define SET_TX_DESC_BUFFER_NULL_0(txdesc, value)                               \
+	HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword6,   \
+				  value, 0x1, 26)
+#define SET_TX_DESC_BUFFER_NULL_0_NO_CLR(txdesc, value)                        \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc)->dword6, value, 0x1, 26)
+#define GET_TX_DESC_BUFFER_NULL_0(txdesc)                                      \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword6, 0x1,  \
+			      26)
+#define SET_TX_DESC_BUFFER_TRI_FRAME(txdesc, value)                            \
+	HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword6,   \
+				  value, 0x1, 25)
+#define SET_TX_DESC_BUFFER_TRI_FRAME_NO_CLR(txdesc, value)                     \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc)->dword6, value, 0x1, 25)
+#define GET_TX_DESC_BUFFER_TRI_FRAME(txdesc)                                   \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword6, 0x1,  \
+			      25)
+#define SET_TX_DESC_BUFFER_SPE_RPT(txdesc, value)                              \
+	HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword6,   \
+				  value, 0x1, 24)
+#define SET_TX_DESC_BUFFER_SPE_RPT_NO_CLR(txdesc, value)                       \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc)->dword6, value, 0x1, 24)
+#define GET_TX_DESC_BUFFER_SPE_RPT(txdesc)                                     \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword6, 0x1,  \
+			      24)
+#define SET_TX_DESC_BUFFER_FTM_EN(txdesc, value)                               \
+	HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword6,   \
+				  value, 0x1, 23)
+#define SET_TX_DESC_BUFFER_FTM_EN_NO_CLR(txdesc, value)                        \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc)->dword6, value, 0x1, 23)
+#define GET_TX_DESC_BUFFER_FTM_EN(txdesc)                                      \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword6, 0x1,  \
+			      23)
+#define SET_TX_DESC_BUFFER_MU_DATARATE(txdesc, value)                          \
+	HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword6,   \
+				  value, 0x7f, 16)
+#define SET_TX_DESC_BUFFER_MU_DATARATE_NO_CLR(txdesc, value)                   \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc)->dword6, value, 0x7f, 16)
+#define GET_TX_DESC_BUFFER_MU_DATARATE(txdesc)                                 \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword6, 0x7f, \
+			      16)
+#define SET_TX_DESC_BUFFER_CCA_RTS(txdesc, value)                              \
+	HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword6,   \
+				  value, 0x3, 14)
+#define SET_TX_DESC_BUFFER_CCA_RTS_NO_CLR(txdesc, value)                       \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc)->dword6, value, 0x3, 14)
+#define GET_TX_DESC_BUFFER_CCA_RTS(txdesc)                                     \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword6, 0x3,  \
+			      14)
+#define SET_TX_DESC_BUFFER_NDPA(txdesc, value)                                 \
+	HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword6,   \
+				  value, 0x3, 12)
+#define SET_TX_DESC_BUFFER_NDPA_NO_CLR(txdesc, value)                          \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc)->dword6, value, 0x3, 12)
+#define GET_TX_DESC_BUFFER_NDPA(txdesc)                                        \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword6, 0x3,  \
+			      12)
+#define SET_TX_DESC_BUFFER_TXPWR_OFSET_TYPE(txdesc, value)                     \
+	HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword6,   \
+				  value, 0x3, 9)
+#define SET_TX_DESC_BUFFER_TXPWR_OFSET_TYPE_NO_CLR(txdesc, value)              \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc)->dword6, value, 0x3, 9)
+#define GET_TX_DESC_BUFFER_TXPWR_OFSET_TYPE(txdesc)                            \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword6, 0x3, 9)
+#define SET_TX_DESC_BUFFER_P_AID(txdesc, value)                                \
+	HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword6,   \
+				  value, 0x1ff, 0)
+#define SET_TX_DESC_BUFFER_P_AID_NO_CLR(txdesc, value)                         \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc)->dword6, value, 0x1ff, 0)
+#define GET_TX_DESC_BUFFER_P_AID(txdesc)                                       \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword6,       \
+			      0x1ff, 0)
+
+/*TXDESC_WORD7*/
+
+#define SET_TX_DESC_BUFFER_SW_DEFINE(txdesc, value)                            \
+	HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword7,   \
+				  value, 0xfff, 16)
+#define SET_TX_DESC_BUFFER_SW_DEFINE_NO_CLR(txdesc, value)                     \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc)->dword7, value, 0xfff, 16)
+#define GET_TX_DESC_BUFFER_SW_DEFINE(txdesc)                                   \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword7,       \
+			      0xfff, 16)
+#define SET_TX_DESC_BUFFER_CTRL_CNT_VALID(txdesc, value)                       \
+	HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword7,   \
+				  value, 0x1, 9)
+#define SET_TX_DESC_BUFFER_CTRL_CNT_VALID_NO_CLR(txdesc, value)                \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc)->dword7, value, 0x1, 9)
+#define GET_TX_DESC_BUFFER_CTRL_CNT_VALID(txdesc)                              \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword7, 0x1, 9)
+#define SET_TX_DESC_BUFFER_CTRL_CNT(txdesc, value)                             \
+	HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword7,   \
+				  value, 0xf, 5)
+#define SET_TX_DESC_BUFFER_CTRL_CNT_NO_CLR(txdesc, value)                      \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc)->dword7, value, 0xf, 5)
+#define GET_TX_DESC_BUFFER_CTRL_CNT(txdesc)                                    \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword7, 0xf, 5)
+#define SET_TX_DESC_BUFFER_DATA_RTY_LOWEST_RATE(txdesc, value)                 \
+	HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword7,   \
+				  value, 0x1f, 0)
+#define SET_TX_DESC_BUFFER_DATA_RTY_LOWEST_RATE_NO_CLR(txdesc, value)          \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc)->dword7, value, 0x1f, 0)
+#define GET_TX_DESC_BUFFER_DATA_RTY_LOWEST_RATE(txdesc)                        \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword7, 0x1f, \
+			      0)
+
+/*TXDESC_WORD8*/
+
+#define SET_TX_DESC_BUFFER_PATH_MAPA(txdesc, value)                            \
+	HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword8,   \
+				  value, 0x3, 30)
+#define SET_TX_DESC_BUFFER_PATH_MAPA_NO_CLR(txdesc, value)                     \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc)->dword8, value, 0x3, 30)
+#define GET_TX_DESC_BUFFER_PATH_MAPA(txdesc)                                   \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword8, 0x3,  \
+			      30)
+#define SET_TX_DESC_BUFFER_PATH_MAPB(txdesc, value)                            \
+	HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword8,   \
+				  value, 0x3, 28)
+#define SET_TX_DESC_BUFFER_PATH_MAPB_NO_CLR(txdesc, value)                     \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc)->dword8, value, 0x3, 28)
+#define GET_TX_DESC_BUFFER_PATH_MAPB(txdesc)                                   \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword8, 0x3,  \
+			      28)
+#define SET_TX_DESC_BUFFER_PATH_MAPC(txdesc, value)                            \
+	HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword8,   \
+				  value, 0x3, 26)
+#define SET_TX_DESC_BUFFER_PATH_MAPC_NO_CLR(txdesc, value)                     \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc)->dword8, value, 0x3, 26)
+#define GET_TX_DESC_BUFFER_PATH_MAPC(txdesc)                                   \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword8, 0x3,  \
+			      26)
+#define SET_TX_DESC_BUFFER_PATH_MAPD(txdesc, value)                            \
+	HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword8,   \
+				  value, 0x3, 24)
+#define SET_TX_DESC_BUFFER_PATH_MAPD_NO_CLR(txdesc, value)                     \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc)->dword8, value, 0x3, 24)
+#define GET_TX_DESC_BUFFER_PATH_MAPD(txdesc)                                   \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword8, 0x3,  \
+			      24)
+#define SET_TX_DESC_BUFFER_ANTSEL_A(txdesc, value)                             \
+	HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword8,   \
+				  value, 0xf, 20)
+#define SET_TX_DESC_BUFFER_ANTSEL_A_NO_CLR(txdesc, value)                      \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc)->dword8, value, 0xf, 20)
+#define GET_TX_DESC_BUFFER_ANTSEL_A(txdesc)                                    \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword8, 0xf,  \
+			      20)
+#define SET_TX_DESC_BUFFER_ANTSEL_B(txdesc, value)                             \
+	HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword8,   \
+				  value, 0xf, 16)
+#define SET_TX_DESC_BUFFER_ANTSEL_B_NO_CLR(txdesc, value)                      \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc)->dword8, value, 0xf, 16)
+#define GET_TX_DESC_BUFFER_ANTSEL_B(txdesc)                                    \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword8, 0xf,  \
+			      16)
+#define SET_TX_DESC_BUFFER_ANTSEL_C(txdesc, value)                             \
+	HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword8,   \
+				  value, 0xf, 12)
+#define SET_TX_DESC_BUFFER_ANTSEL_C_NO_CLR(txdesc, value)                      \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc)->dword8, value, 0xf, 12)
+#define GET_TX_DESC_BUFFER_ANTSEL_C(txdesc)                                    \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword8, 0xf,  \
+			      12)
+#define SET_TX_DESC_BUFFER_ANTSEL_D(txdesc, value)                             \
+	HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword8,   \
+				  value, 0xf, 8)
+#define SET_TX_DESC_BUFFER_ANTSEL_D_NO_CLR(txdesc, value)                      \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc)->dword8, value, 0xf, 8)
+#define GET_TX_DESC_BUFFER_ANTSEL_D(txdesc)                                    \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword8, 0xf, 8)
+#define SET_TX_DESC_BUFFER_NTX_PATH_EN(txdesc, value)                          \
+	HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword8,   \
+				  value, 0xf, 4)
+#define SET_TX_DESC_BUFFER_NTX_PATH_EN_NO_CLR(txdesc, value)                   \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc)->dword8, value, 0xf, 4)
+#define GET_TX_DESC_BUFFER_NTX_PATH_EN(txdesc)                                 \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword8, 0xf, 4)
+#define SET_TX_DESC_BUFFER_ANTLSEL_EN(txdesc, value)                           \
+	HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword8,   \
+				  value, 0x1, 3)
+#define SET_TX_DESC_BUFFER_ANTLSEL_EN_NO_CLR(txdesc, value)                    \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc)->dword8, value, 0x1, 3)
+#define GET_TX_DESC_BUFFER_ANTLSEL_EN(txdesc)                                  \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword8, 0x1, 3)
+#define SET_TX_DESC_BUFFER_AMPDU_DENSITY(txdesc, value)                        \
+	HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword8,   \
+				  value, 0x7, 0)
+#define SET_TX_DESC_BUFFER_AMPDU_DENSITY_NO_CLR(txdesc, value)                 \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc)->dword8, value, 0x7, 0)
+#define GET_TX_DESC_BUFFER_AMPDU_DENSITY(txdesc)                               \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword8, 0x7, 0)
+
+/*TXDESC_WORD9*/
+
+#define SET_TX_DESC_BUFFER_VCS_STBC(txdesc, value)                             \
+	HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword9,   \
+				  value, 0x3, 30)
+#define SET_TX_DESC_BUFFER_VCS_STBC_NO_CLR(txdesc, value)                      \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc)->dword9, value, 0x3, 30)
+#define GET_TX_DESC_BUFFER_VCS_STBC(txdesc)                                    \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword9, 0x3,  \
+			      30)
+#define SET_TX_DESC_BUFFER_DATA_STBC(txdesc, value)                            \
+	HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword9,   \
+				  value, 0x3, 28)
+#define SET_TX_DESC_BUFFER_DATA_STBC_NO_CLR(txdesc, value)                     \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc)->dword9, value, 0x3, 28)
+#define GET_TX_DESC_BUFFER_DATA_STBC(txdesc)                                   \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword9, 0x3,  \
+			      28)
+#define SET_TX_DESC_BUFFER_RTS_RTY_LOWEST_RATE(txdesc, value)                  \
+	HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword9,   \
+				  value, 0xf, 24)
+#define SET_TX_DESC_BUFFER_RTS_RTY_LOWEST_RATE_NO_CLR(txdesc, value)           \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc)->dword9, value, 0xf, 24)
+#define GET_TX_DESC_BUFFER_RTS_RTY_LOWEST_RATE(txdesc)                         \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword9, 0xf,  \
+			      24)
+#define SET_TX_DESC_BUFFER_SIGNALING_TA_PKT_EN(txdesc, value)                  \
+	HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword9,   \
+				  value, 0x1, 23)
+#define SET_TX_DESC_BUFFER_SIGNALING_TA_PKT_EN_NO_CLR(txdesc, value)           \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc)->dword9, value, 0x1, 23)
+#define GET_TX_DESC_BUFFER_SIGNALING_TA_PKT_EN(txdesc)                         \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword9, 0x1,  \
+			      23)
+#define SET_TX_DESC_BUFFER_MHR_CP(txdesc, value)                               \
+	HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword9,   \
+				  value, 0x1, 22)
+#define SET_TX_DESC_BUFFER_MHR_CP_NO_CLR(txdesc, value)                        \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc)->dword9, value, 0x1, 22)
+#define GET_TX_DESC_BUFFER_MHR_CP(txdesc)                                      \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword9, 0x1,  \
+			      22)
+#define SET_TX_DESC_BUFFER_SMH_EN(txdesc, value)                               \
+	HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword9,   \
+				  value, 0x1, 21)
+#define SET_TX_DESC_BUFFER_SMH_EN_NO_CLR(txdesc, value)                        \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc)->dword9, value, 0x1, 21)
+#define GET_TX_DESC_BUFFER_SMH_EN(txdesc)                                      \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword9, 0x1,  \
+			      21)
+#define SET_TX_DESC_BUFFER_RTSRATE(txdesc, value)                              \
+	HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword9,   \
+				  value, 0x1f, 16)
+#define SET_TX_DESC_BUFFER_RTSRATE_NO_CLR(txdesc, value)                       \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc)->dword9, value, 0x1f, 16)
+#define GET_TX_DESC_BUFFER_RTSRATE(txdesc)                                     \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword9, 0x1f, \
+			      16)
+#define SET_TX_DESC_BUFFER_SMH_CAM(txdesc, value)                              \
+	HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword9,   \
+				  value, 0xff, 8)
+#define SET_TX_DESC_BUFFER_SMH_CAM_NO_CLR(txdesc, value)                       \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc)->dword9, value, 0xff, 8)
+#define GET_TX_DESC_BUFFER_SMH_CAM(txdesc)                                     \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword9, 0xff, \
+			      8)
+#define SET_TX_DESC_BUFFER_ARFR_TABLE_SEL(txdesc, value)                       \
+	HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword9,   \
+				  value, 0x1, 7)
+#define SET_TX_DESC_BUFFER_ARFR_TABLE_SEL_NO_CLR(txdesc, value)                \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc)->dword9, value, 0x1, 7)
+#define GET_TX_DESC_BUFFER_ARFR_TABLE_SEL(txdesc)                              \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword9, 0x1, 7)
+#define SET_TX_DESC_BUFFER_ARFR_HT_EN(txdesc, value)                           \
+	HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword9,   \
+				  value, 0x1, 6)
+#define SET_TX_DESC_BUFFER_ARFR_HT_EN_NO_CLR(txdesc, value)                    \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc)->dword9, value, 0x1, 6)
+#define GET_TX_DESC_BUFFER_ARFR_HT_EN(txdesc)                                  \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword9, 0x1, 6)
+#define SET_TX_DESC_BUFFER_ARFR_OFDM_EN(txdesc, value)                         \
+	HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword9,   \
+				  value, 0x1, 5)
+#define SET_TX_DESC_BUFFER_ARFR_OFDM_EN_NO_CLR(txdesc, value)                  \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc)->dword9, value, 0x1, 5)
+#define GET_TX_DESC_BUFFER_ARFR_OFDM_EN(txdesc)                                \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword9, 0x1, 5)
+#define SET_TX_DESC_BUFFER_ARFR_CCK_EN(txdesc, value)                          \
+	HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword9,   \
+				  value, 0x1, 4)
+#define SET_TX_DESC_BUFFER_ARFR_CCK_EN_NO_CLR(txdesc, value)                   \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc)->dword9, value, 0x1, 4)
+#define GET_TX_DESC_BUFFER_ARFR_CCK_EN(txdesc)                                 \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword9, 0x1, 4)
+#define SET_TX_DESC_BUFFER_RTS_SHORT(txdesc, value)                            \
+	HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword9,   \
+				  value, 0x1, 3)
+#define SET_TX_DESC_BUFFER_RTS_SHORT_NO_CLR(txdesc, value)                     \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc)->dword9, value, 0x1, 3)
+#define GET_TX_DESC_BUFFER_RTS_SHORT(txdesc)                                   \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword9, 0x1, 3)
+#define SET_TX_DESC_BUFFER_DISDATAFB(txdesc, value)                            \
+	HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword9,   \
+				  value, 0x1, 2)
+#define SET_TX_DESC_BUFFER_DISDATAFB_NO_CLR(txdesc, value)                     \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc)->dword9, value, 0x1, 2)
+#define GET_TX_DESC_BUFFER_DISDATAFB(txdesc)                                   \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword9, 0x1, 2)
+#define SET_TX_DESC_BUFFER_DISRTSFB(txdesc, value)                             \
+	HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword9,   \
+				  value, 0x1, 1)
+#define SET_TX_DESC_BUFFER_DISRTSFB_NO_CLR(txdesc, value)                      \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc)->dword9, value, 0x1, 1)
+#define GET_TX_DESC_BUFFER_DISRTSFB(txdesc)                                    \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword9, 0x1, 1)
+#define SET_TX_DESC_BUFFER_EXT_EDCA(txdesc, value)                             \
+	HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword9,   \
+				  value, 0x1, 0)
+#define SET_TX_DESC_BUFFER_EXT_EDCA_NO_CLR(txdesc, value)                      \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc)->dword9, value, 0x1, 0)
+#define GET_TX_DESC_BUFFER_EXT_EDCA(txdesc)                                    \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword9, 0x1, 0)
+
+/*TXDESC_WORD10*/
+
+#define SET_TX_DESC_BUFFER_AMPDU_MAX_TIME(txdesc, value)                       \
+	HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword10,  \
+				  value, 0xff, 24)
+#define SET_TX_DESC_BUFFER_AMPDU_MAX_TIME_NO_CLR(txdesc, value)                \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc)->dword10, value, 0xff, 24)
+#define GET_TX_DESC_BUFFER_AMPDU_MAX_TIME(txdesc)                              \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword10,      \
+			      0xff, 24)
+#define SET_TX_DESC_BUFFER_SPECIAL_CW(txdesc, value)                           \
+	HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword10,  \
+				  value, 0x1, 23)
+#define SET_TX_DESC_BUFFER_SPECIAL_CW_NO_CLR(txdesc, value)                    \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc)->dword10, value, 0x1, 23)
+#define GET_TX_DESC_BUFFER_SPECIAL_CW(txdesc)                                  \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword10, 0x1, \
+			      23)
+#define SET_TX_DESC_BUFFER_RDG_NAV_EXT(txdesc, value)                          \
+	HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword10,  \
+				  value, 0x1, 22)
+#define SET_TX_DESC_BUFFER_RDG_NAV_EXT_NO_CLR(txdesc, value)                   \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc)->dword10, value, 0x1, 22)
+#define GET_TX_DESC_BUFFER_RDG_NAV_EXT(txdesc)                                 \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword10, 0x1, \
+			      22)
+#define SET_TX_DESC_BUFFER_RAW(txdesc, value)                                  \
+	HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword10,  \
+				  value, 0x1, 21)
+#define SET_TX_DESC_BUFFER_RAW_NO_CLR(txdesc, value)                           \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc)->dword10, value, 0x1, 21)
+#define GET_TX_DESC_BUFFER_RAW(txdesc)                                         \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword10, 0x1, \
+			      21)
+#define SET_TX_DESC_BUFFER_MAX_AGG_NUM(txdesc, value)                          \
+	HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword10,  \
+				  value, 0x1f, 16)
+#define SET_TX_DESC_BUFFER_MAX_AGG_NUM_NO_CLR(txdesc, value)                   \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc)->dword10, value, 0x1f, 16)
+#define GET_TX_DESC_BUFFER_MAX_AGG_NUM(txdesc)                                 \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword10,      \
+			      0x1f, 16)
+#define SET_TX_DESC_BUFFER_FINAL_DATA_RATE(txdesc, value)                      \
+	HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword10,  \
+				  value, 0xff, 8)
+#define SET_TX_DESC_BUFFER_FINAL_DATA_RATE_NO_CLR(txdesc, value)               \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc)->dword10, value, 0xff, 8)
+#define GET_TX_DESC_BUFFER_FINAL_DATA_RATE(txdesc)                             \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword10,      \
+			      0xff, 8)
+#define SET_TX_DESC_BUFFER_GF(txdesc, value)                                   \
+	HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword10,  \
+				  value, 0x1, 7)
+#define SET_TX_DESC_BUFFER_GF_NO_CLR(txdesc, value)                            \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc)->dword10, value, 0x1, 7)
+#define GET_TX_DESC_BUFFER_GF(txdesc)                                          \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword10, 0x1, \
+			      7)
+#define SET_TX_DESC_BUFFER_MOREFRAG(txdesc, value)                             \
+	HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword10,  \
+				  value, 0x1, 6)
+#define SET_TX_DESC_BUFFER_MOREFRAG_NO_CLR(txdesc, value)                      \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc)->dword10, value, 0x1, 6)
+#define GET_TX_DESC_BUFFER_MOREFRAG(txdesc)                                    \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword10, 0x1, \
+			      6)
+#define SET_TX_DESC_BUFFER_NOACM(txdesc, value)                                \
+	HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword10,  \
+				  value, 0x1, 5)
+#define SET_TX_DESC_BUFFER_NOACM_NO_CLR(txdesc, value)                         \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc)->dword10, value, 0x1, 5)
+#define GET_TX_DESC_BUFFER_NOACM(txdesc)                                       \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword10, 0x1, \
+			      5)
+#define SET_TX_DESC_BUFFER_HTC(txdesc, value)                                  \
+	HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword10,  \
+				  value, 0x1, 4)
+#define SET_TX_DESC_BUFFER_HTC_NO_CLR(txdesc, value)                           \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc)->dword10, value, 0x1, 4)
+#define GET_TX_DESC_BUFFER_HTC(txdesc)                                         \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword10, 0x1, \
+			      4)
+#define SET_TX_DESC_BUFFER_TX_PKT_AFTER_PIFS(txdesc, value)                    \
+	HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword10,  \
+				  value, 0x1, 3)
+#define SET_TX_DESC_BUFFER_TX_PKT_AFTER_PIFS_NO_CLR(txdesc, value)             \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc)->dword10, value, 0x1, 3)
+#define GET_TX_DESC_BUFFER_TX_PKT_AFTER_PIFS(txdesc)                           \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword10, 0x1, \
+			      3)
+#define SET_TX_DESC_BUFFER_USE_MAX_TIME_EN(txdesc, value)                      \
+	HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword10,  \
+				  value, 0x1, 2)
+#define SET_TX_DESC_BUFFER_USE_MAX_TIME_EN_NO_CLR(txdesc, value)               \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc)->dword10, value, 0x1, 2)
+#define GET_TX_DESC_BUFFER_USE_MAX_TIME_EN(txdesc)                             \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword10, 0x1, \
+			      2)
+#define SET_TX_DESC_BUFFER_HW_SSN_SEL(txdesc, value)                           \
+	HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword10,  \
+				  value, 0x3, 0)
+#define SET_TX_DESC_BUFFER_HW_SSN_SEL_NO_CLR(txdesc, value)                    \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc)->dword10, value, 0x3, 0)
+#define GET_TX_DESC_BUFFER_HW_SSN_SEL(txdesc)                                  \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword10, 0x3, \
+			      0)
+
+/*TXDESC_WORD11*/
+
+#define SET_TX_DESC_BUFFER_ADDR_CAM(txdesc, value)                             \
+	HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword11,  \
+				  value, 0xff, 24)
+#define SET_TX_DESC_BUFFER_ADDR_CAM_NO_CLR(txdesc, value)                      \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc)->dword11, value, 0xff, 24)
+#define GET_TX_DESC_BUFFER_ADDR_CAM(txdesc)                                    \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword11,      \
+			      0xff, 24)
+#define SET_TX_DESC_BUFFER_SND_TARGET(txdesc, value)                           \
+	HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword11,  \
+				  value, 0xff, 16)
+#define SET_TX_DESC_BUFFER_SND_TARGET_NO_CLR(txdesc, value)                    \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc)->dword11, value, 0xff, 16)
+#define GET_TX_DESC_BUFFER_SND_TARGET(txdesc)                                  \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword11,      \
+			      0xff, 16)
+#define SET_TX_DESC_BUFFER_DATA_LDPC(txdesc, value)                            \
+	HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword11,  \
+				  value, 0x1, 15)
+#define SET_TX_DESC_BUFFER_DATA_LDPC_NO_CLR(txdesc, value)                     \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc)->dword11, value, 0x1, 15)
+#define GET_TX_DESC_BUFFER_DATA_LDPC(txdesc)                                   \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword11, 0x1, \
+			      15)
+#define SET_TX_DESC_BUFFER_LSIG_TXOP_EN(txdesc, value)                         \
+	HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword11,  \
+				  value, 0x1, 14)
+#define SET_TX_DESC_BUFFER_LSIG_TXOP_EN_NO_CLR(txdesc, value)                  \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc)->dword11, value, 0x1, 14)
+#define GET_TX_DESC_BUFFER_LSIG_TXOP_EN(txdesc)                                \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword11, 0x1, \
+			      14)
+#define SET_TX_DESC_BUFFER_G_ID(txdesc, value)                                 \
+	HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword11,  \
+				  value, 0x3f, 8)
+#define SET_TX_DESC_BUFFER_G_ID_NO_CLR(txdesc, value)                          \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc)->dword11, value, 0x3f, 8)
+#define GET_TX_DESC_BUFFER_G_ID(txdesc)                                        \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword11,      \
+			      0x3f, 8)
+#define SET_TX_DESC_BUFFER_SIGNALING_TA_PKT_SC(txdesc, value)                  \
+	HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword11,  \
+				  value, 0xf, 4)
+#define SET_TX_DESC_BUFFER_SIGNALING_TA_PKT_SC_NO_CLR(txdesc, value)           \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc)->dword11, value, 0xf, 4)
+#define GET_TX_DESC_BUFFER_SIGNALING_TA_PKT_SC(txdesc)                         \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword11, 0xf, \
+			      4)
+#define SET_TX_DESC_BUFFER_DATA_SC(txdesc, value)                              \
+	HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword11,  \
+				  value, 0xf, 0)
+#define SET_TX_DESC_BUFFER_DATA_SC_NO_CLR(txdesc, value)                       \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc)->dword11, value, 0xf, 0)
+#define GET_TX_DESC_BUFFER_DATA_SC(txdesc)                                     \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword11, 0xf, \
+			      0)
+
+/*TXDESC_WORD12*/
+
+#define SET_TX_DESC_BUFFER_LEN1_L(txdesc, value)                               \
+	HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword12,  \
+				  value, 0x7f, 17)
+#define SET_TX_DESC_BUFFER_LEN1_L_NO_CLR(txdesc, value)                        \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc)->dword12, value, 0x7f, 17)
+#define GET_TX_DESC_BUFFER_LEN1_L(txdesc)                                      \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword12,      \
+			      0x7f, 17)
+#define SET_TX_DESC_BUFFER_LEN0(txdesc, value)                                 \
+	HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword12,  \
+				  value, 0x1fff, 4)
+#define SET_TX_DESC_BUFFER_LEN0_NO_CLR(txdesc, value)                          \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc)->dword12, value, 0x1fff, 4)
+#define GET_TX_DESC_BUFFER_LEN0(txdesc)                                        \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword12,      \
+			      0x1fff, 4)
+#define SET_TX_DESC_BUFFER_PKT_NUM(txdesc, value)                              \
+	HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword12,  \
+				  value, 0xf, 0)
+#define SET_TX_DESC_BUFFER_PKT_NUM_NO_CLR(txdesc, value)                       \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc)->dword12, value, 0xf, 0)
+#define GET_TX_DESC_BUFFER_PKT_NUM(txdesc)                                     \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword12, 0xf, \
+			      0)
+
+/*TXDESC_WORD13*/
+
+#define SET_TX_DESC_BUFFER_LEN3(txdesc, value)                                 \
+	HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword13,  \
+				  value, 0x1fff, 19)
+#define SET_TX_DESC_BUFFER_LEN3_NO_CLR(txdesc, value)                          \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc)->dword13, value, 0x1fff, 19)
+#define GET_TX_DESC_BUFFER_LEN3(txdesc)                                        \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword13,      \
+			      0x1fff, 19)
+#define SET_TX_DESC_BUFFER_LEN2(txdesc, value)                                 \
+	HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword13,  \
+				  value, 0x1fff, 6)
+#define SET_TX_DESC_BUFFER_LEN2_NO_CLR(txdesc, value)                          \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc)->dword13, value, 0x1fff, 6)
+#define GET_TX_DESC_BUFFER_LEN2(txdesc)                                        \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword13,      \
+			      0x1fff, 6)
+#define SET_TX_DESC_BUFFER_LEN1_H(txdesc, value)                               \
+	HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword13,  \
+				  value, 0x3f, 0)
+#define SET_TX_DESC_BUFFER_LEN1_H_NO_CLR(txdesc, value)                        \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc)->dword13, value, 0x3f, 0)
+#define GET_TX_DESC_BUFFER_LEN1_H(txdesc)                                      \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword13,      \
+			      0x3f, 0)
+
+#endif
+
+#endif
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/halmac/halmac_tx_desc_buffer_chip.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/halmac/halmac_tx_desc_buffer_chip.h
--- linux-5.6.3/3rdparty/rtl8821ce/hal/halmac/halmac_tx_desc_buffer_chip.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/halmac/halmac_tx_desc_buffer_chip.h	2020-04-10 16:35:06.817660114 +0300
@@ -0,0 +1,509 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ ******************************************************************************/
+
+#ifndef _HALMAC_TX_DESC_BUFFER_CHIP_H_
+#define _HALMAC_TX_DESC_BUFFER_CHIP_H_
+#if (HALMAC_8814B_SUPPORT)
+
+/*TXDESC_WORD0*/
+
+#define SET_TX_DESC_BUFFER_RDG_EN_8814B(txdesc, value)                         \
+	SET_TX_DESC_BUFFER_RDG_EN(txdesc, value)
+#define GET_TX_DESC_BUFFER_RDG_EN_8814B(txdesc)                                \
+	GET_TX_DESC_BUFFER_RDG_EN(txdesc)
+#define SET_TX_DESC_BUFFER_BCNPKT_TSF_CTRL_8814B(txdesc, value)                \
+	SET_TX_DESC_BUFFER_BCNPKT_TSF_CTRL(txdesc, value)
+#define GET_TX_DESC_BUFFER_BCNPKT_TSF_CTRL_8814B(txdesc)                       \
+	GET_TX_DESC_BUFFER_BCNPKT_TSF_CTRL(txdesc)
+#define SET_TX_DESC_BUFFER_AGG_EN_8814B(txdesc, value)                         \
+	SET_TX_DESC_BUFFER_AGG_EN(txdesc, value)
+#define GET_TX_DESC_BUFFER_AGG_EN_8814B(txdesc)                                \
+	GET_TX_DESC_BUFFER_AGG_EN(txdesc)
+#define SET_TX_DESC_BUFFER_PKT_OFFSET_8814B(txdesc, value)                     \
+	SET_TX_DESC_BUFFER_PKT_OFFSET(txdesc, value)
+#define GET_TX_DESC_BUFFER_PKT_OFFSET_8814B(txdesc)                            \
+	GET_TX_DESC_BUFFER_PKT_OFFSET(txdesc)
+#define SET_TX_DESC_BUFFER_OFFSET_8814B(txdesc, value)                         \
+	SET_TX_DESC_BUFFER_OFFSET(txdesc, value)
+#define GET_TX_DESC_BUFFER_OFFSET_8814B(txdesc)                                \
+	GET_TX_DESC_BUFFER_OFFSET(txdesc)
+#define SET_TX_DESC_BUFFER_TXPKTSIZE_8814B(txdesc, value)                      \
+	SET_TX_DESC_BUFFER_TXPKTSIZE(txdesc, value)
+#define GET_TX_DESC_BUFFER_TXPKTSIZE_8814B(txdesc)                             \
+	GET_TX_DESC_BUFFER_TXPKTSIZE(txdesc)
+
+/*TXDESC_WORD1*/
+
+#define SET_TX_DESC_BUFFER_USERATE_8814B(txdesc, value)                        \
+	SET_TX_DESC_BUFFER_USERATE(txdesc, value)
+#define GET_TX_DESC_BUFFER_USERATE_8814B(txdesc)                               \
+	GET_TX_DESC_BUFFER_USERATE(txdesc)
+#define SET_TX_DESC_BUFFER_AMSDU_8814B(txdesc, value)                          \
+	SET_TX_DESC_BUFFER_AMSDU(txdesc, value)
+#define GET_TX_DESC_BUFFER_AMSDU_8814B(txdesc) GET_TX_DESC_BUFFER_AMSDU(txdesc)
+#define SET_TX_DESC_BUFFER_EN_HWSEQ_8814B(txdesc, value)                       \
+	SET_TX_DESC_BUFFER_EN_HWSEQ(txdesc, value)
+#define GET_TX_DESC_BUFFER_EN_HWSEQ_8814B(txdesc)                              \
+	GET_TX_DESC_BUFFER_EN_HWSEQ(txdesc)
+#define SET_TX_DESC_BUFFER_EN_HWEXSEQ_8814B(txdesc, value)                     \
+	SET_TX_DESC_BUFFER_EN_HWEXSEQ(txdesc, value)
+#define GET_TX_DESC_BUFFER_EN_HWEXSEQ_8814B(txdesc)                            \
+	GET_TX_DESC_BUFFER_EN_HWEXSEQ(txdesc)
+#define SET_TX_DESC_BUFFER_SW_SEQ_8814B(txdesc, value)                         \
+	SET_TX_DESC_BUFFER_SW_SEQ(txdesc, value)
+#define GET_TX_DESC_BUFFER_SW_SEQ_8814B(txdesc)                                \
+	GET_TX_DESC_BUFFER_SW_SEQ(txdesc)
+#define SET_TX_DESC_BUFFER_DROP_ID_8814B(txdesc, value)                        \
+	SET_TX_DESC_BUFFER_DROP_ID(txdesc, value)
+#define GET_TX_DESC_BUFFER_DROP_ID_8814B(txdesc)                               \
+	GET_TX_DESC_BUFFER_DROP_ID(txdesc)
+#define SET_TX_DESC_BUFFER_MOREDATA_8814B(txdesc, value)                       \
+	SET_TX_DESC_BUFFER_MOREDATA(txdesc, value)
+#define GET_TX_DESC_BUFFER_MOREDATA_8814B(txdesc)                              \
+	GET_TX_DESC_BUFFER_MOREDATA(txdesc)
+#define SET_TX_DESC_BUFFER_QSEL_8814B(txdesc, value)                           \
+	SET_TX_DESC_BUFFER_QSEL(txdesc, value)
+#define GET_TX_DESC_BUFFER_QSEL_8814B(txdesc) GET_TX_DESC_BUFFER_QSEL(txdesc)
+#define SET_TX_DESC_BUFFER_MACID_8814B(txdesc, value)                          \
+	SET_TX_DESC_BUFFER_MACID(txdesc, value)
+#define GET_TX_DESC_BUFFER_MACID_8814B(txdesc) GET_TX_DESC_BUFFER_MACID(txdesc)
+
+/*TXDESC_WORD2*/
+
+#define SET_TX_DESC_BUFFER_CHK_EN_8814B(txdesc, value)                         \
+	SET_TX_DESC_BUFFER_CHK_EN(txdesc, value)
+#define GET_TX_DESC_BUFFER_CHK_EN_8814B(txdesc)                                \
+	GET_TX_DESC_BUFFER_CHK_EN(txdesc)
+#define SET_TX_DESC_BUFFER_DISQSELSEQ_8814B(txdesc, value)                     \
+	SET_TX_DESC_BUFFER_DISQSELSEQ(txdesc, value)
+#define GET_TX_DESC_BUFFER_DISQSELSEQ_8814B(txdesc)                            \
+	GET_TX_DESC_BUFFER_DISQSELSEQ(txdesc)
+#define SET_TX_DESC_BUFFER_SND_PKT_SEL_8814B(txdesc, value)                    \
+	SET_TX_DESC_BUFFER_SND_PKT_SEL(txdesc, value)
+#define GET_TX_DESC_BUFFER_SND_PKT_SEL_8814B(txdesc)                           \
+	GET_TX_DESC_BUFFER_SND_PKT_SEL(txdesc)
+#define SET_TX_DESC_BUFFER_DMA_PRI_8814B(txdesc, value)                        \
+	SET_TX_DESC_BUFFER_DMA_PRI(txdesc, value)
+#define GET_TX_DESC_BUFFER_DMA_PRI_8814B(txdesc)                               \
+	GET_TX_DESC_BUFFER_DMA_PRI(txdesc)
+#define SET_TX_DESC_BUFFER_MAX_AMSDU_MODE_8814B(txdesc, value)                 \
+	SET_TX_DESC_BUFFER_MAX_AMSDU_MODE(txdesc, value)
+#define GET_TX_DESC_BUFFER_MAX_AMSDU_MODE_8814B(txdesc)                        \
+	GET_TX_DESC_BUFFER_MAX_AMSDU_MODE(txdesc)
+#define SET_TX_DESC_BUFFER_DMA_TXAGG_NUM_8814B(txdesc, value)                  \
+	SET_TX_DESC_BUFFER_DMA_TXAGG_NUM(txdesc, value)
+#define GET_TX_DESC_BUFFER_DMA_TXAGG_NUM_8814B(txdesc)                         \
+	GET_TX_DESC_BUFFER_DMA_TXAGG_NUM(txdesc)
+#define SET_TX_DESC_BUFFER_TXDESC_CHECKSUM_8814B(txdesc, value)                \
+	SET_TX_DESC_BUFFER_TXDESC_CHECKSUM(txdesc, value)
+#define GET_TX_DESC_BUFFER_TXDESC_CHECKSUM_8814B(txdesc)                       \
+	GET_TX_DESC_BUFFER_TXDESC_CHECKSUM(txdesc)
+
+/*TXDESC_WORD3*/
+
+#define SET_TX_DESC_BUFFER_OFFLOAD_SIZE_8814B(txdesc, value)                   \
+	SET_TX_DESC_BUFFER_OFFLOAD_SIZE(txdesc, value)
+#define GET_TX_DESC_BUFFER_OFFLOAD_SIZE_8814B(txdesc)                          \
+	GET_TX_DESC_BUFFER_OFFLOAD_SIZE(txdesc)
+#define SET_TX_DESC_BUFFER_CHANNEL_DMA_8814B(txdesc, value)                    \
+	SET_TX_DESC_BUFFER_CHANNEL_DMA(txdesc, value)
+#define GET_TX_DESC_BUFFER_CHANNEL_DMA_8814B(txdesc)                           \
+	GET_TX_DESC_BUFFER_CHANNEL_DMA(txdesc)
+#define SET_TX_DESC_BUFFER_MBSSID_8814B(txdesc, value)                         \
+	SET_TX_DESC_BUFFER_MBSSID(txdesc, value)
+#define GET_TX_DESC_BUFFER_MBSSID_8814B(txdesc)                                \
+	GET_TX_DESC_BUFFER_MBSSID(txdesc)
+#define SET_TX_DESC_BUFFER_BK_8814B(txdesc, value)                             \
+	SET_TX_DESC_BUFFER_BK(txdesc, value)
+#define GET_TX_DESC_BUFFER_BK_8814B(txdesc) GET_TX_DESC_BUFFER_BK(txdesc)
+#define SET_TX_DESC_BUFFER_WHEADER_LEN_8814B(txdesc, value)                    \
+	SET_TX_DESC_BUFFER_WHEADER_LEN(txdesc, value)
+#define GET_TX_DESC_BUFFER_WHEADER_LEN_8814B(txdesc)                           \
+	GET_TX_DESC_BUFFER_WHEADER_LEN(txdesc)
+
+/*TXDESC_WORD4*/
+
+#define SET_TX_DESC_BUFFER_TRY_RATE_8814B(txdesc, value)                       \
+	SET_TX_DESC_BUFFER_TRY_RATE(txdesc, value)
+#define GET_TX_DESC_BUFFER_TRY_RATE_8814B(txdesc)                              \
+	GET_TX_DESC_BUFFER_TRY_RATE(txdesc)
+#define SET_TX_DESC_BUFFER_DATA_BW_8814B(txdesc, value)                        \
+	SET_TX_DESC_BUFFER_DATA_BW(txdesc, value)
+#define GET_TX_DESC_BUFFER_DATA_BW_8814B(txdesc)                               \
+	GET_TX_DESC_BUFFER_DATA_BW(txdesc)
+#define SET_TX_DESC_BUFFER_DATA_SHORT_8814B(txdesc, value)                     \
+	SET_TX_DESC_BUFFER_DATA_SHORT(txdesc, value)
+#define GET_TX_DESC_BUFFER_DATA_SHORT_8814B(txdesc)                            \
+	GET_TX_DESC_BUFFER_DATA_SHORT(txdesc)
+#define SET_TX_DESC_BUFFER_DATARATE_8814B(txdesc, value)                       \
+	SET_TX_DESC_BUFFER_DATARATE(txdesc, value)
+#define GET_TX_DESC_BUFFER_DATARATE_8814B(txdesc)                              \
+	GET_TX_DESC_BUFFER_DATARATE(txdesc)
+#define SET_TX_DESC_BUFFER_TXBF_PATH_8814B(txdesc, value)                      \
+	SET_TX_DESC_BUFFER_TXBF_PATH(txdesc, value)
+#define GET_TX_DESC_BUFFER_TXBF_PATH_8814B(txdesc)                             \
+	GET_TX_DESC_BUFFER_TXBF_PATH(txdesc)
+#define SET_TX_DESC_BUFFER_GROUP_BIT_IE_OFFSET_8814B(txdesc, value)            \
+	SET_TX_DESC_BUFFER_GROUP_BIT_IE_OFFSET(txdesc, value)
+#define GET_TX_DESC_BUFFER_GROUP_BIT_IE_OFFSET_8814B(txdesc)                   \
+	GET_TX_DESC_BUFFER_GROUP_BIT_IE_OFFSET(txdesc)
+
+/*TXDESC_WORD5*/
+
+#define SET_TX_DESC_BUFFER_RTY_LMT_EN_8814B(txdesc, value)                     \
+	SET_TX_DESC_BUFFER_RTY_LMT_EN(txdesc, value)
+#define GET_TX_DESC_BUFFER_RTY_LMT_EN_8814B(txdesc)                            \
+	GET_TX_DESC_BUFFER_RTY_LMT_EN(txdesc)
+#define SET_TX_DESC_BUFFER_HW_RTS_EN_8814B(txdesc, value)                      \
+	SET_TX_DESC_BUFFER_HW_RTS_EN(txdesc, value)
+#define GET_TX_DESC_BUFFER_HW_RTS_EN_8814B(txdesc)                             \
+	GET_TX_DESC_BUFFER_HW_RTS_EN(txdesc)
+#define SET_TX_DESC_BUFFER_RTS_EN_8814B(txdesc, value)                         \
+	SET_TX_DESC_BUFFER_RTS_EN(txdesc, value)
+#define GET_TX_DESC_BUFFER_RTS_EN_8814B(txdesc)                                \
+	GET_TX_DESC_BUFFER_RTS_EN(txdesc)
+#define SET_TX_DESC_BUFFER_CTS2SELF_8814B(txdesc, value)                       \
+	SET_TX_DESC_BUFFER_CTS2SELF(txdesc, value)
+#define GET_TX_DESC_BUFFER_CTS2SELF_8814B(txdesc)                              \
+	GET_TX_DESC_BUFFER_CTS2SELF(txdesc)
+#define SET_TX_DESC_BUFFER_TAILPAGE_H_8814B(txdesc, value)                     \
+	SET_TX_DESC_BUFFER_TAILPAGE_H(txdesc, value)
+#define GET_TX_DESC_BUFFER_TAILPAGE_H_8814B(txdesc)                            \
+	GET_TX_DESC_BUFFER_TAILPAGE_H(txdesc)
+#define SET_TX_DESC_BUFFER_TAILPAGE_L_8814B(txdesc, value)                     \
+	SET_TX_DESC_BUFFER_TAILPAGE_L(txdesc, value)
+#define GET_TX_DESC_BUFFER_TAILPAGE_L_8814B(txdesc)                            \
+	GET_TX_DESC_BUFFER_TAILPAGE_L(txdesc)
+#define SET_TX_DESC_BUFFER_NAVUSEHDR_8814B(txdesc, value)                      \
+	SET_TX_DESC_BUFFER_NAVUSEHDR(txdesc, value)
+#define GET_TX_DESC_BUFFER_NAVUSEHDR_8814B(txdesc)                             \
+	GET_TX_DESC_BUFFER_NAVUSEHDR(txdesc)
+#define SET_TX_DESC_BUFFER_BMC_8814B(txdesc, value)                            \
+	SET_TX_DESC_BUFFER_BMC(txdesc, value)
+#define GET_TX_DESC_BUFFER_BMC_8814B(txdesc) GET_TX_DESC_BUFFER_BMC(txdesc)
+#define SET_TX_DESC_BUFFER_RTS_DATA_RTY_LMT_8814B(txdesc, value)               \
+	SET_TX_DESC_BUFFER_RTS_DATA_RTY_LMT(txdesc, value)
+#define GET_TX_DESC_BUFFER_RTS_DATA_RTY_LMT_8814B(txdesc)                      \
+	GET_TX_DESC_BUFFER_RTS_DATA_RTY_LMT(txdesc)
+#define SET_TX_DESC_BUFFER_HW_AES_IV_8814B(txdesc, value)                      \
+	SET_TX_DESC_BUFFER_HW_AES_IV(txdesc, value)
+#define GET_TX_DESC_BUFFER_HW_AES_IV_8814B(txdesc)                             \
+	GET_TX_DESC_BUFFER_HW_AES_IV(txdesc)
+#define SET_TX_DESC_BUFFER_BT_NULL_8814B(txdesc, value)                        \
+	SET_TX_DESC_BUFFER_BT_NULL(txdesc, value)
+#define GET_TX_DESC_BUFFER_BT_NULL_8814B(txdesc)                               \
+	GET_TX_DESC_BUFFER_BT_NULL(txdesc)
+#define SET_TX_DESC_BUFFER_EN_DESC_ID_8814B(txdesc, value)                     \
+	SET_TX_DESC_BUFFER_EN_DESC_ID(txdesc, value)
+#define GET_TX_DESC_BUFFER_EN_DESC_ID_8814B(txdesc)                            \
+	GET_TX_DESC_BUFFER_EN_DESC_ID(txdesc)
+#define SET_TX_DESC_BUFFER_SECTYPE_8814B(txdesc, value)                        \
+	SET_TX_DESC_BUFFER_SECTYPE(txdesc, value)
+#define GET_TX_DESC_BUFFER_SECTYPE_8814B(txdesc)                               \
+	GET_TX_DESC_BUFFER_SECTYPE(txdesc)
+
+/*TXDESC_WORD6*/
+
+#define SET_TX_DESC_BUFFER_MULTIPLE_PORT_8814B(txdesc, value)                  \
+	SET_TX_DESC_BUFFER_MULTIPLE_PORT(txdesc, value)
+#define GET_TX_DESC_BUFFER_MULTIPLE_PORT_8814B(txdesc)                         \
+	GET_TX_DESC_BUFFER_MULTIPLE_PORT(txdesc)
+#define SET_TX_DESC_BUFFER_POLLUTED_8814B(txdesc, value)                       \
+	SET_TX_DESC_BUFFER_POLLUTED(txdesc, value)
+#define GET_TX_DESC_BUFFER_POLLUTED_8814B(txdesc)                              \
+	GET_TX_DESC_BUFFER_POLLUTED(txdesc)
+#define SET_TX_DESC_BUFFER_NULL_1_8814B(txdesc, value)                         \
+	SET_TX_DESC_BUFFER_NULL_1(txdesc, value)
+#define GET_TX_DESC_BUFFER_NULL_1_8814B(txdesc)                                \
+	GET_TX_DESC_BUFFER_NULL_1(txdesc)
+#define SET_TX_DESC_BUFFER_NULL_0_8814B(txdesc, value)                         \
+	SET_TX_DESC_BUFFER_NULL_0(txdesc, value)
+#define GET_TX_DESC_BUFFER_NULL_0_8814B(txdesc)                                \
+	GET_TX_DESC_BUFFER_NULL_0(txdesc)
+#define SET_TX_DESC_BUFFER_TRI_FRAME_8814B(txdesc, value)                      \
+	SET_TX_DESC_BUFFER_TRI_FRAME(txdesc, value)
+#define GET_TX_DESC_BUFFER_TRI_FRAME_8814B(txdesc)                             \
+	GET_TX_DESC_BUFFER_TRI_FRAME(txdesc)
+#define SET_TX_DESC_BUFFER_SPE_RPT_8814B(txdesc, value)                        \
+	SET_TX_DESC_BUFFER_SPE_RPT(txdesc, value)
+#define GET_TX_DESC_BUFFER_SPE_RPT_8814B(txdesc)                               \
+	GET_TX_DESC_BUFFER_SPE_RPT(txdesc)
+#define SET_TX_DESC_BUFFER_FTM_EN_8814B(txdesc, value)                         \
+	SET_TX_DESC_BUFFER_FTM_EN(txdesc, value)
+#define GET_TX_DESC_BUFFER_FTM_EN_8814B(txdesc)                                \
+	GET_TX_DESC_BUFFER_FTM_EN(txdesc)
+#define SET_TX_DESC_BUFFER_MU_DATARATE_8814B(txdesc, value)                    \
+	SET_TX_DESC_BUFFER_MU_DATARATE(txdesc, value)
+#define GET_TX_DESC_BUFFER_MU_DATARATE_8814B(txdesc)                           \
+	GET_TX_DESC_BUFFER_MU_DATARATE(txdesc)
+#define SET_TX_DESC_BUFFER_CCA_RTS_8814B(txdesc, value)                        \
+	SET_TX_DESC_BUFFER_CCA_RTS(txdesc, value)
+#define GET_TX_DESC_BUFFER_CCA_RTS_8814B(txdesc)                               \
+	GET_TX_DESC_BUFFER_CCA_RTS(txdesc)
+#define SET_TX_DESC_BUFFER_NDPA_8814B(txdesc, value)                           \
+	SET_TX_DESC_BUFFER_NDPA(txdesc, value)
+#define GET_TX_DESC_BUFFER_NDPA_8814B(txdesc) GET_TX_DESC_BUFFER_NDPA(txdesc)
+#define SET_TX_DESC_BUFFER_TXPWR_OFSET_TYPE_8814B(txdesc, value)               \
+	SET_TX_DESC_BUFFER_TXPWR_OFSET_TYPE(txdesc, value)
+#define GET_TX_DESC_BUFFER_TXPWR_OFSET_TYPE_8814B(txdesc)                      \
+	GET_TX_DESC_BUFFER_TXPWR_OFSET_TYPE(txdesc)
+#define SET_TX_DESC_BUFFER_P_AID_8814B(txdesc, value)                          \
+	SET_TX_DESC_BUFFER_P_AID(txdesc, value)
+#define GET_TX_DESC_BUFFER_P_AID_8814B(txdesc) GET_TX_DESC_BUFFER_P_AID(txdesc)
+
+/*TXDESC_WORD7*/
+
+#define SET_TX_DESC_BUFFER_SW_DEFINE_8814B(txdesc, value)                      \
+	SET_TX_DESC_BUFFER_SW_DEFINE(txdesc, value)
+#define GET_TX_DESC_BUFFER_SW_DEFINE_8814B(txdesc)                             \
+	GET_TX_DESC_BUFFER_SW_DEFINE(txdesc)
+#define SET_TX_DESC_BUFFER_CTRL_CNT_VALID_8814B(txdesc, value)                 \
+	SET_TX_DESC_BUFFER_CTRL_CNT_VALID(txdesc, value)
+#define GET_TX_DESC_BUFFER_CTRL_CNT_VALID_8814B(txdesc)                        \
+	GET_TX_DESC_BUFFER_CTRL_CNT_VALID(txdesc)
+#define SET_TX_DESC_BUFFER_CTRL_CNT_8814B(txdesc, value)                       \
+	SET_TX_DESC_BUFFER_CTRL_CNT(txdesc, value)
+#define GET_TX_DESC_BUFFER_CTRL_CNT_8814B(txdesc)                              \
+	GET_TX_DESC_BUFFER_CTRL_CNT(txdesc)
+#define SET_TX_DESC_BUFFER_DATA_RTY_LOWEST_RATE_8814B(txdesc, value)           \
+	SET_TX_DESC_BUFFER_DATA_RTY_LOWEST_RATE(txdesc, value)
+#define GET_TX_DESC_BUFFER_DATA_RTY_LOWEST_RATE_8814B(txdesc)                  \
+	GET_TX_DESC_BUFFER_DATA_RTY_LOWEST_RATE(txdesc)
+
+/*TXDESC_WORD8*/
+
+#define SET_TX_DESC_BUFFER_PATH_MAPA_8814B(txdesc, value)                      \
+	SET_TX_DESC_BUFFER_PATH_MAPA(txdesc, value)
+#define GET_TX_DESC_BUFFER_PATH_MAPA_8814B(txdesc)                             \
+	GET_TX_DESC_BUFFER_PATH_MAPA(txdesc)
+#define SET_TX_DESC_BUFFER_PATH_MAPB_8814B(txdesc, value)                      \
+	SET_TX_DESC_BUFFER_PATH_MAPB(txdesc, value)
+#define GET_TX_DESC_BUFFER_PATH_MAPB_8814B(txdesc)                             \
+	GET_TX_DESC_BUFFER_PATH_MAPB(txdesc)
+#define SET_TX_DESC_BUFFER_PATH_MAPC_8814B(txdesc, value)                      \
+	SET_TX_DESC_BUFFER_PATH_MAPC(txdesc, value)
+#define GET_TX_DESC_BUFFER_PATH_MAPC_8814B(txdesc)                             \
+	GET_TX_DESC_BUFFER_PATH_MAPC(txdesc)
+#define SET_TX_DESC_BUFFER_PATH_MAPD_8814B(txdesc, value)                      \
+	SET_TX_DESC_BUFFER_PATH_MAPD(txdesc, value)
+#define GET_TX_DESC_BUFFER_PATH_MAPD_8814B(txdesc)                             \
+	GET_TX_DESC_BUFFER_PATH_MAPD(txdesc)
+#define SET_TX_DESC_BUFFER_ANTSEL_A_8814B(txdesc, value)                       \
+	SET_TX_DESC_BUFFER_ANTSEL_A(txdesc, value)
+#define GET_TX_DESC_BUFFER_ANTSEL_A_8814B(txdesc)                              \
+	GET_TX_DESC_BUFFER_ANTSEL_A(txdesc)
+#define SET_TX_DESC_BUFFER_ANTSEL_B_8814B(txdesc, value)                       \
+	SET_TX_DESC_BUFFER_ANTSEL_B(txdesc, value)
+#define GET_TX_DESC_BUFFER_ANTSEL_B_8814B(txdesc)                              \
+	GET_TX_DESC_BUFFER_ANTSEL_B(txdesc)
+#define SET_TX_DESC_BUFFER_ANTSEL_C_8814B(txdesc, value)                       \
+	SET_TX_DESC_BUFFER_ANTSEL_C(txdesc, value)
+#define GET_TX_DESC_BUFFER_ANTSEL_C_8814B(txdesc)                              \
+	GET_TX_DESC_BUFFER_ANTSEL_C(txdesc)
+#define SET_TX_DESC_BUFFER_ANTSEL_D_8814B(txdesc, value)                       \
+	SET_TX_DESC_BUFFER_ANTSEL_D(txdesc, value)
+#define GET_TX_DESC_BUFFER_ANTSEL_D_8814B(txdesc)                              \
+	GET_TX_DESC_BUFFER_ANTSEL_D(txdesc)
+#define SET_TX_DESC_BUFFER_NTX_PATH_EN_8814B(txdesc, value)                    \
+	SET_TX_DESC_BUFFER_NTX_PATH_EN(txdesc, value)
+#define GET_TX_DESC_BUFFER_NTX_PATH_EN_8814B(txdesc)                           \
+	GET_TX_DESC_BUFFER_NTX_PATH_EN(txdesc)
+#define SET_TX_DESC_BUFFER_ANTLSEL_EN_8814B(txdesc, value)                     \
+	SET_TX_DESC_BUFFER_ANTLSEL_EN(txdesc, value)
+#define GET_TX_DESC_BUFFER_ANTLSEL_EN_8814B(txdesc)                            \
+	GET_TX_DESC_BUFFER_ANTLSEL_EN(txdesc)
+#define SET_TX_DESC_BUFFER_AMPDU_DENSITY_8814B(txdesc, value)                  \
+	SET_TX_DESC_BUFFER_AMPDU_DENSITY(txdesc, value)
+#define GET_TX_DESC_BUFFER_AMPDU_DENSITY_8814B(txdesc)                         \
+	GET_TX_DESC_BUFFER_AMPDU_DENSITY(txdesc)
+
+/*TXDESC_WORD9*/
+
+#define SET_TX_DESC_BUFFER_VCS_STBC_8814B(txdesc, value)                       \
+	SET_TX_DESC_BUFFER_VCS_STBC(txdesc, value)
+#define GET_TX_DESC_BUFFER_VCS_STBC_8814B(txdesc)                              \
+	GET_TX_DESC_BUFFER_VCS_STBC(txdesc)
+#define SET_TX_DESC_BUFFER_DATA_STBC_8814B(txdesc, value)                      \
+	SET_TX_DESC_BUFFER_DATA_STBC(txdesc, value)
+#define GET_TX_DESC_BUFFER_DATA_STBC_8814B(txdesc)                             \
+	GET_TX_DESC_BUFFER_DATA_STBC(txdesc)
+#define SET_TX_DESC_BUFFER_RTS_RTY_LOWEST_RATE_8814B(txdesc, value)            \
+	SET_TX_DESC_BUFFER_RTS_RTY_LOWEST_RATE(txdesc, value)
+#define GET_TX_DESC_BUFFER_RTS_RTY_LOWEST_RATE_8814B(txdesc)                   \
+	GET_TX_DESC_BUFFER_RTS_RTY_LOWEST_RATE(txdesc)
+#define SET_TX_DESC_BUFFER_SIGNALING_TA_PKT_EN_8814B(txdesc, value)            \
+	SET_TX_DESC_BUFFER_SIGNALING_TA_PKT_EN(txdesc, value)
+#define GET_TX_DESC_BUFFER_SIGNALING_TA_PKT_EN_8814B(txdesc)                   \
+	GET_TX_DESC_BUFFER_SIGNALING_TA_PKT_EN(txdesc)
+#define SET_TX_DESC_BUFFER_MHR_CP_8814B(txdesc, value)                         \
+	SET_TX_DESC_BUFFER_MHR_CP(txdesc, value)
+#define GET_TX_DESC_BUFFER_MHR_CP_8814B(txdesc)                                \
+	GET_TX_DESC_BUFFER_MHR_CP(txdesc)
+#define SET_TX_DESC_BUFFER_SMH_EN_8814B(txdesc, value)                         \
+	SET_TX_DESC_BUFFER_SMH_EN(txdesc, value)
+#define GET_TX_DESC_BUFFER_SMH_EN_8814B(txdesc)                                \
+	GET_TX_DESC_BUFFER_SMH_EN(txdesc)
+#define SET_TX_DESC_BUFFER_RTSRATE_8814B(txdesc, value)                        \
+	SET_TX_DESC_BUFFER_RTSRATE(txdesc, value)
+#define GET_TX_DESC_BUFFER_RTSRATE_8814B(txdesc)                               \
+	GET_TX_DESC_BUFFER_RTSRATE(txdesc)
+#define SET_TX_DESC_BUFFER_SMH_CAM_8814B(txdesc, value)                        \
+	SET_TX_DESC_BUFFER_SMH_CAM(txdesc, value)
+#define GET_TX_DESC_BUFFER_SMH_CAM_8814B(txdesc)                               \
+	GET_TX_DESC_BUFFER_SMH_CAM(txdesc)
+#define SET_TX_DESC_BUFFER_ARFR_TABLE_SEL_8814B(txdesc, value)                 \
+	SET_TX_DESC_BUFFER_ARFR_TABLE_SEL(txdesc, value)
+#define GET_TX_DESC_BUFFER_ARFR_TABLE_SEL_8814B(txdesc)                        \
+	GET_TX_DESC_BUFFER_ARFR_TABLE_SEL(txdesc)
+#define SET_TX_DESC_BUFFER_ARFR_HT_EN_8814B(txdesc, value)                     \
+	SET_TX_DESC_BUFFER_ARFR_HT_EN(txdesc, value)
+#define GET_TX_DESC_BUFFER_ARFR_HT_EN_8814B(txdesc)                            \
+	GET_TX_DESC_BUFFER_ARFR_HT_EN(txdesc)
+#define SET_TX_DESC_BUFFER_ARFR_OFDM_EN_8814B(txdesc, value)                   \
+	SET_TX_DESC_BUFFER_ARFR_OFDM_EN(txdesc, value)
+#define GET_TX_DESC_BUFFER_ARFR_OFDM_EN_8814B(txdesc)                          \
+	GET_TX_DESC_BUFFER_ARFR_OFDM_EN(txdesc)
+#define SET_TX_DESC_BUFFER_ARFR_CCK_EN_8814B(txdesc, value)                    \
+	SET_TX_DESC_BUFFER_ARFR_CCK_EN(txdesc, value)
+#define GET_TX_DESC_BUFFER_ARFR_CCK_EN_8814B(txdesc)                           \
+	GET_TX_DESC_BUFFER_ARFR_CCK_EN(txdesc)
+#define SET_TX_DESC_BUFFER_RTS_SHORT_8814B(txdesc, value)                      \
+	SET_TX_DESC_BUFFER_RTS_SHORT(txdesc, value)
+#define GET_TX_DESC_BUFFER_RTS_SHORT_8814B(txdesc)                             \
+	GET_TX_DESC_BUFFER_RTS_SHORT(txdesc)
+#define SET_TX_DESC_BUFFER_DISDATAFB_8814B(txdesc, value)                      \
+	SET_TX_DESC_BUFFER_DISDATAFB(txdesc, value)
+#define GET_TX_DESC_BUFFER_DISDATAFB_8814B(txdesc)                             \
+	GET_TX_DESC_BUFFER_DISDATAFB(txdesc)
+#define SET_TX_DESC_BUFFER_DISRTSFB_8814B(txdesc, value)                       \
+	SET_TX_DESC_BUFFER_DISRTSFB(txdesc, value)
+#define GET_TX_DESC_BUFFER_DISRTSFB_8814B(txdesc)                              \
+	GET_TX_DESC_BUFFER_DISRTSFB(txdesc)
+#define SET_TX_DESC_BUFFER_EXT_EDCA_8814B(txdesc, value)                       \
+	SET_TX_DESC_BUFFER_EXT_EDCA(txdesc, value)
+#define GET_TX_DESC_BUFFER_EXT_EDCA_8814B(txdesc)                              \
+	GET_TX_DESC_BUFFER_EXT_EDCA(txdesc)
+
+/*TXDESC_WORD10*/
+
+#define SET_TX_DESC_BUFFER_AMPDU_MAX_TIME_8814B(txdesc, value)                 \
+	SET_TX_DESC_BUFFER_AMPDU_MAX_TIME(txdesc, value)
+#define GET_TX_DESC_BUFFER_AMPDU_MAX_TIME_8814B(txdesc)                        \
+	GET_TX_DESC_BUFFER_AMPDU_MAX_TIME(txdesc)
+#define SET_TX_DESC_BUFFER_SPECIAL_CW_8814B(txdesc, value)                     \
+	SET_TX_DESC_BUFFER_SPECIAL_CW(txdesc, value)
+#define GET_TX_DESC_BUFFER_SPECIAL_CW_8814B(txdesc)                            \
+	GET_TX_DESC_BUFFER_SPECIAL_CW(txdesc)
+#define SET_TX_DESC_BUFFER_RDG_NAV_EXT_8814B(txdesc, value)                    \
+	SET_TX_DESC_BUFFER_RDG_NAV_EXT(txdesc, value)
+#define GET_TX_DESC_BUFFER_RDG_NAV_EXT_8814B(txdesc)                           \
+	GET_TX_DESC_BUFFER_RDG_NAV_EXT(txdesc)
+#define SET_TX_DESC_BUFFER_RAW_8814B(txdesc, value)                            \
+	SET_TX_DESC_BUFFER_RAW(txdesc, value)
+#define GET_TX_DESC_BUFFER_RAW_8814B(txdesc) GET_TX_DESC_BUFFER_RAW(txdesc)
+#define SET_TX_DESC_BUFFER_MAX_AGG_NUM_8814B(txdesc, value)                    \
+	SET_TX_DESC_BUFFER_MAX_AGG_NUM(txdesc, value)
+#define GET_TX_DESC_BUFFER_MAX_AGG_NUM_8814B(txdesc)                           \
+	GET_TX_DESC_BUFFER_MAX_AGG_NUM(txdesc)
+#define SET_TX_DESC_BUFFER_FINAL_DATA_RATE_8814B(txdesc, value)                \
+	SET_TX_DESC_BUFFER_FINAL_DATA_RATE(txdesc, value)
+#define GET_TX_DESC_BUFFER_FINAL_DATA_RATE_8814B(txdesc)                       \
+	GET_TX_DESC_BUFFER_FINAL_DATA_RATE(txdesc)
+#define SET_TX_DESC_BUFFER_GF_8814B(txdesc, value)                             \
+	SET_TX_DESC_BUFFER_GF(txdesc, value)
+#define GET_TX_DESC_BUFFER_GF_8814B(txdesc) GET_TX_DESC_BUFFER_GF(txdesc)
+#define SET_TX_DESC_BUFFER_MOREFRAG_8814B(txdesc, value)                       \
+	SET_TX_DESC_BUFFER_MOREFRAG(txdesc, value)
+#define GET_TX_DESC_BUFFER_MOREFRAG_8814B(txdesc)                              \
+	GET_TX_DESC_BUFFER_MOREFRAG(txdesc)
+#define SET_TX_DESC_BUFFER_NOACM_8814B(txdesc, value)                          \
+	SET_TX_DESC_BUFFER_NOACM(txdesc, value)
+#define GET_TX_DESC_BUFFER_NOACM_8814B(txdesc) GET_TX_DESC_BUFFER_NOACM(txdesc)
+#define SET_TX_DESC_BUFFER_HTC_8814B(txdesc, value)                            \
+	SET_TX_DESC_BUFFER_HTC(txdesc, value)
+#define GET_TX_DESC_BUFFER_HTC_8814B(txdesc) GET_TX_DESC_BUFFER_HTC(txdesc)
+#define SET_TX_DESC_BUFFER_TX_PKT_AFTER_PIFS_8814B(txdesc, value)              \
+	SET_TX_DESC_BUFFER_TX_PKT_AFTER_PIFS(txdesc, value)
+#define GET_TX_DESC_BUFFER_TX_PKT_AFTER_PIFS_8814B(txdesc)                     \
+	GET_TX_DESC_BUFFER_TX_PKT_AFTER_PIFS(txdesc)
+#define SET_TX_DESC_BUFFER_USE_MAX_TIME_EN_8814B(txdesc, value)                \
+	SET_TX_DESC_BUFFER_USE_MAX_TIME_EN(txdesc, value)
+#define GET_TX_DESC_BUFFER_USE_MAX_TIME_EN_8814B(txdesc)                       \
+	GET_TX_DESC_BUFFER_USE_MAX_TIME_EN(txdesc)
+#define SET_TX_DESC_BUFFER_HW_SSN_SEL_8814B(txdesc, value)                     \
+	SET_TX_DESC_BUFFER_HW_SSN_SEL(txdesc, value)
+#define GET_TX_DESC_BUFFER_HW_SSN_SEL_8814B(txdesc)                            \
+	GET_TX_DESC_BUFFER_HW_SSN_SEL(txdesc)
+
+/*TXDESC_WORD11*/
+
+#define SET_TX_DESC_BUFFER_ADDR_CAM_8814B(txdesc, value)                       \
+	SET_TX_DESC_BUFFER_ADDR_CAM(txdesc, value)
+#define GET_TX_DESC_BUFFER_ADDR_CAM_8814B(txdesc)                              \
+	GET_TX_DESC_BUFFER_ADDR_CAM(txdesc)
+#define SET_TX_DESC_BUFFER_SND_TARGET_8814B(txdesc, value)                     \
+	SET_TX_DESC_BUFFER_SND_TARGET(txdesc, value)
+#define GET_TX_DESC_BUFFER_SND_TARGET_8814B(txdesc)                            \
+	GET_TX_DESC_BUFFER_SND_TARGET(txdesc)
+#define SET_TX_DESC_BUFFER_DATA_LDPC_8814B(txdesc, value)                      \
+	SET_TX_DESC_BUFFER_DATA_LDPC(txdesc, value)
+#define GET_TX_DESC_BUFFER_DATA_LDPC_8814B(txdesc)                             \
+	GET_TX_DESC_BUFFER_DATA_LDPC(txdesc)
+#define SET_TX_DESC_BUFFER_LSIG_TXOP_EN_8814B(txdesc, value)                   \
+	SET_TX_DESC_BUFFER_LSIG_TXOP_EN(txdesc, value)
+#define GET_TX_DESC_BUFFER_LSIG_TXOP_EN_8814B(txdesc)                          \
+	GET_TX_DESC_BUFFER_LSIG_TXOP_EN(txdesc)
+#define SET_TX_DESC_BUFFER_G_ID_8814B(txdesc, value)                           \
+	SET_TX_DESC_BUFFER_G_ID(txdesc, value)
+#define GET_TX_DESC_BUFFER_G_ID_8814B(txdesc) GET_TX_DESC_BUFFER_G_ID(txdesc)
+#define SET_TX_DESC_BUFFER_SIGNALING_TA_PKT_SC_8814B(txdesc, value)            \
+	SET_TX_DESC_BUFFER_SIGNALING_TA_PKT_SC(txdesc, value)
+#define GET_TX_DESC_BUFFER_SIGNALING_TA_PKT_SC_8814B(txdesc)                   \
+	GET_TX_DESC_BUFFER_SIGNALING_TA_PKT_SC(txdesc)
+#define SET_TX_DESC_BUFFER_DATA_SC_8814B(txdesc, value)                        \
+	SET_TX_DESC_BUFFER_DATA_SC(txdesc, value)
+#define GET_TX_DESC_BUFFER_DATA_SC_8814B(txdesc)                               \
+	GET_TX_DESC_BUFFER_DATA_SC(txdesc)
+
+/*TXDESC_WORD12*/
+
+#define SET_TX_DESC_BUFFER_LEN1_L_8814B(txdesc, value)                         \
+	SET_TX_DESC_BUFFER_LEN1_L(txdesc, value)
+#define GET_TX_DESC_BUFFER_LEN1_L_8814B(txdesc)                                \
+	GET_TX_DESC_BUFFER_LEN1_L(txdesc)
+#define SET_TX_DESC_BUFFER_LEN0_8814B(txdesc, value)                           \
+	SET_TX_DESC_BUFFER_LEN0(txdesc, value)
+#define GET_TX_DESC_BUFFER_LEN0_8814B(txdesc) GET_TX_DESC_BUFFER_LEN0(txdesc)
+#define SET_TX_DESC_BUFFER_PKT_NUM_8814B(txdesc, value)                        \
+	SET_TX_DESC_BUFFER_PKT_NUM(txdesc, value)
+#define GET_TX_DESC_BUFFER_PKT_NUM_8814B(txdesc)                               \
+	GET_TX_DESC_BUFFER_PKT_NUM(txdesc)
+
+/*TXDESC_WORD13*/
+
+#define SET_TX_DESC_BUFFER_LEN3_8814B(txdesc, value)                           \
+	SET_TX_DESC_BUFFER_LEN3(txdesc, value)
+#define GET_TX_DESC_BUFFER_LEN3_8814B(txdesc) GET_TX_DESC_BUFFER_LEN3(txdesc)
+#define SET_TX_DESC_BUFFER_LEN2_8814B(txdesc, value)                           \
+	SET_TX_DESC_BUFFER_LEN2(txdesc, value)
+#define GET_TX_DESC_BUFFER_LEN2_8814B(txdesc) GET_TX_DESC_BUFFER_LEN2(txdesc)
+#define SET_TX_DESC_BUFFER_LEN1_H_8814B(txdesc, value)                         \
+	SET_TX_DESC_BUFFER_LEN1_H(txdesc, value)
+#define GET_TX_DESC_BUFFER_LEN1_H_8814B(txdesc)                                \
+	GET_TX_DESC_BUFFER_LEN1_H(txdesc)
+
+#endif
+
+#endif
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/halmac/halmac_tx_desc_buffer_nic.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/halmac/halmac_tx_desc_buffer_nic.h
--- linux-5.6.3/3rdparty/rtl8821ce/hal/halmac/halmac_tx_desc_buffer_nic.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/halmac/halmac_tx_desc_buffer_nic.h	2020-04-10 16:35:06.817660114 +0300
@@ -0,0 +1,491 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ ******************************************************************************/
+
+#ifndef _HALMAC_TX_DESC_BUFFER_NIC_H_
+#define _HALMAC_TX_DESC_BUFFER_NIC_H_
+#if (HALMAC_8814B_SUPPORT)
+
+/*TXDESC_WORD0*/
+
+#define SET_TX_DESC_BUFFER_RDG_EN(txdesc, value)                               \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x00, 31, 1, value)
+#define GET_TX_DESC_BUFFER_RDG_EN(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x00, 31, 1)
+#define SET_TX_DESC_BUFFER_BCNPKT_TSF_CTRL(txdesc, value)                      \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x00, 30, 1, value)
+#define GET_TX_DESC_BUFFER_BCNPKT_TSF_CTRL(txdesc)                             \
+	LE_BITS_TO_4BYTE(txdesc + 0x00, 30, 1)
+#define SET_TX_DESC_BUFFER_AGG_EN(txdesc, value)                               \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x00, 29, 1, value)
+#define GET_TX_DESC_BUFFER_AGG_EN(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x00, 29, 1)
+#define SET_TX_DESC_BUFFER_PKT_OFFSET(txdesc, value)                           \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x00, 24, 5, value)
+#define GET_TX_DESC_BUFFER_PKT_OFFSET(txdesc)                                  \
+	LE_BITS_TO_4BYTE(txdesc + 0x00, 24, 5)
+#define SET_TX_DESC_BUFFER_OFFSET(txdesc, value)                               \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x00, 16, 8, value)
+#define GET_TX_DESC_BUFFER_OFFSET(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x00, 16, 8)
+#define SET_TX_DESC_BUFFER_TXPKTSIZE(txdesc, value)                            \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x00, 0, 16, value)
+#define GET_TX_DESC_BUFFER_TXPKTSIZE(txdesc)                                   \
+	LE_BITS_TO_4BYTE(txdesc + 0x00, 0, 16)
+
+/*TXDESC_WORD1*/
+
+#define SET_TX_DESC_BUFFER_USERATE(txdesc, value)                              \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x04, 31, 1, value)
+#define GET_TX_DESC_BUFFER_USERATE(txdesc)                                     \
+	LE_BITS_TO_4BYTE(txdesc + 0x04, 31, 1)
+#define SET_TX_DESC_BUFFER_AMSDU(txdesc, value)                                \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x04, 30, 1, value)
+#define GET_TX_DESC_BUFFER_AMSDU(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x04, 30, 1)
+#define SET_TX_DESC_BUFFER_EN_HWSEQ(txdesc, value)                             \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x04, 29, 1, value)
+#define GET_TX_DESC_BUFFER_EN_HWSEQ(txdesc)                                    \
+	LE_BITS_TO_4BYTE(txdesc + 0x04, 29, 1)
+#define SET_TX_DESC_BUFFER_EN_HWEXSEQ(txdesc, value)                           \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x04, 28, 1, value)
+#define GET_TX_DESC_BUFFER_EN_HWEXSEQ(txdesc)                                  \
+	LE_BITS_TO_4BYTE(txdesc + 0x04, 28, 1)
+#define SET_TX_DESC_BUFFER_SW_SEQ(txdesc, value)                               \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x04, 16, 12, value)
+#define GET_TX_DESC_BUFFER_SW_SEQ(txdesc)                                      \
+	LE_BITS_TO_4BYTE(txdesc + 0x04, 16, 12)
+#define SET_TX_DESC_BUFFER_DROP_ID(txdesc, value)                              \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x04, 14, 2, value)
+#define GET_TX_DESC_BUFFER_DROP_ID(txdesc)                                     \
+	LE_BITS_TO_4BYTE(txdesc + 0x04, 14, 2)
+#define SET_TX_DESC_BUFFER_MOREDATA(txdesc, value)                             \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x04, 13, 1, value)
+#define GET_TX_DESC_BUFFER_MOREDATA(txdesc)                                    \
+	LE_BITS_TO_4BYTE(txdesc + 0x04, 13, 1)
+#define SET_TX_DESC_BUFFER_QSEL(txdesc, value)                                 \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x04, 8, 5, value)
+#define GET_TX_DESC_BUFFER_QSEL(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x04, 8, 5)
+#define SET_TX_DESC_BUFFER_MACID(txdesc, value)                                \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x04, 0, 8, value)
+#define GET_TX_DESC_BUFFER_MACID(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x04, 0, 8)
+
+/*TXDESC_WORD2*/
+
+#define SET_TX_DESC_BUFFER_CHK_EN(txdesc, value)                               \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x08, 31, 1, value)
+#define GET_TX_DESC_BUFFER_CHK_EN(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x08, 31, 1)
+#define SET_TX_DESC_BUFFER_DISQSELSEQ(txdesc, value)                           \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x08, 30, 1, value)
+#define GET_TX_DESC_BUFFER_DISQSELSEQ(txdesc)                                  \
+	LE_BITS_TO_4BYTE(txdesc + 0x08, 30, 1)
+#define SET_TX_DESC_BUFFER_SND_PKT_SEL(txdesc, value)                          \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x08, 28, 2, value)
+#define GET_TX_DESC_BUFFER_SND_PKT_SEL(txdesc)                                 \
+	LE_BITS_TO_4BYTE(txdesc + 0x08, 28, 2)
+#define SET_TX_DESC_BUFFER_DMA_PRI(txdesc, value)                              \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x08, 27, 1, value)
+#define GET_TX_DESC_BUFFER_DMA_PRI(txdesc)                                     \
+	LE_BITS_TO_4BYTE(txdesc + 0x08, 27, 1)
+#define SET_TX_DESC_BUFFER_MAX_AMSDU_MODE(txdesc, value)                       \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x08, 24, 3, value)
+#define GET_TX_DESC_BUFFER_MAX_AMSDU_MODE(txdesc)                              \
+	LE_BITS_TO_4BYTE(txdesc + 0x08, 24, 3)
+#define SET_TX_DESC_BUFFER_DMA_TXAGG_NUM(txdesc, value)                        \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x08, 16, 8, value)
+#define GET_TX_DESC_BUFFER_DMA_TXAGG_NUM(txdesc)                               \
+	LE_BITS_TO_4BYTE(txdesc + 0x08, 16, 8)
+#define SET_TX_DESC_BUFFER_TXDESC_CHECKSUM(txdesc, value)                      \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x08, 0, 16, value)
+#define GET_TX_DESC_BUFFER_TXDESC_CHECKSUM(txdesc)                             \
+	LE_BITS_TO_4BYTE(txdesc + 0x08, 0, 16)
+
+/*TXDESC_WORD3*/
+
+#define SET_TX_DESC_BUFFER_OFFLOAD_SIZE(txdesc, value)                         \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x0C, 16, 15, value)
+#define GET_TX_DESC_BUFFER_OFFLOAD_SIZE(txdesc)                                \
+	LE_BITS_TO_4BYTE(txdesc + 0x0C, 16, 15)
+#define SET_TX_DESC_BUFFER_CHANNEL_DMA(txdesc, value)                          \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x0C, 11, 5, value)
+#define GET_TX_DESC_BUFFER_CHANNEL_DMA(txdesc)                                 \
+	LE_BITS_TO_4BYTE(txdesc + 0x0C, 11, 5)
+#define SET_TX_DESC_BUFFER_MBSSID(txdesc, value)                               \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x0C, 7, 4, value)
+#define GET_TX_DESC_BUFFER_MBSSID(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x0C, 7, 4)
+#define SET_TX_DESC_BUFFER_BK(txdesc, value)                                   \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x0C, 6, 1, value)
+#define GET_TX_DESC_BUFFER_BK(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x0C, 6, 1)
+#define SET_TX_DESC_BUFFER_WHEADER_LEN(txdesc, value)                          \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x0C, 0, 5, value)
+#define GET_TX_DESC_BUFFER_WHEADER_LEN(txdesc)                                 \
+	LE_BITS_TO_4BYTE(txdesc + 0x0C, 0, 5)
+
+/*TXDESC_WORD4*/
+
+#define SET_TX_DESC_BUFFER_TRY_RATE(txdesc, value)                             \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x10, 26, 1, value)
+#define GET_TX_DESC_BUFFER_TRY_RATE(txdesc)                                    \
+	LE_BITS_TO_4BYTE(txdesc + 0x10, 26, 1)
+#define SET_TX_DESC_BUFFER_DATA_BW(txdesc, value)                              \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x10, 24, 2, value)
+#define GET_TX_DESC_BUFFER_DATA_BW(txdesc)                                     \
+	LE_BITS_TO_4BYTE(txdesc + 0x10, 24, 2)
+#define SET_TX_DESC_BUFFER_DATA_SHORT(txdesc, value)                           \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x10, 23, 1, value)
+#define GET_TX_DESC_BUFFER_DATA_SHORT(txdesc)                                  \
+	LE_BITS_TO_4BYTE(txdesc + 0x10, 23, 1)
+#define SET_TX_DESC_BUFFER_DATARATE(txdesc, value)                             \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x10, 16, 7, value)
+#define GET_TX_DESC_BUFFER_DATARATE(txdesc)                                    \
+	LE_BITS_TO_4BYTE(txdesc + 0x10, 16, 7)
+#define SET_TX_DESC_BUFFER_TXBF_PATH(txdesc, value)                            \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x10, 11, 1, value)
+#define GET_TX_DESC_BUFFER_TXBF_PATH(txdesc)                                   \
+	LE_BITS_TO_4BYTE(txdesc + 0x10, 11, 1)
+#define SET_TX_DESC_BUFFER_GROUP_BIT_IE_OFFSET(txdesc, value)                  \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x10, 0, 11, value)
+#define GET_TX_DESC_BUFFER_GROUP_BIT_IE_OFFSET(txdesc)                         \
+	LE_BITS_TO_4BYTE(txdesc + 0x10, 0, 11)
+
+/*TXDESC_WORD5*/
+
+#define SET_TX_DESC_BUFFER_RTY_LMT_EN(txdesc, value)                           \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x14, 31, 1, value)
+#define GET_TX_DESC_BUFFER_RTY_LMT_EN(txdesc)                                  \
+	LE_BITS_TO_4BYTE(txdesc + 0x14, 31, 1)
+#define SET_TX_DESC_BUFFER_HW_RTS_EN(txdesc, value)                            \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x14, 30, 1, value)
+#define GET_TX_DESC_BUFFER_HW_RTS_EN(txdesc)                                   \
+	LE_BITS_TO_4BYTE(txdesc + 0x14, 30, 1)
+#define SET_TX_DESC_BUFFER_RTS_EN(txdesc, value)                               \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x14, 29, 1, value)
+#define GET_TX_DESC_BUFFER_RTS_EN(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x14, 29, 1)
+#define SET_TX_DESC_BUFFER_CTS2SELF(txdesc, value)                             \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x14, 28, 1, value)
+#define GET_TX_DESC_BUFFER_CTS2SELF(txdesc)                                    \
+	LE_BITS_TO_4BYTE(txdesc + 0x14, 28, 1)
+#define SET_TX_DESC_BUFFER_TAILPAGE_H(txdesc, value)                           \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x14, 24, 4, value)
+#define GET_TX_DESC_BUFFER_TAILPAGE_H(txdesc)                                  \
+	LE_BITS_TO_4BYTE(txdesc + 0x14, 24, 4)
+#define SET_TX_DESC_BUFFER_TAILPAGE_L(txdesc, value)                           \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x14, 16, 8, value)
+#define GET_TX_DESC_BUFFER_TAILPAGE_L(txdesc)                                  \
+	LE_BITS_TO_4BYTE(txdesc + 0x14, 16, 8)
+#define SET_TX_DESC_BUFFER_NAVUSEHDR(txdesc, value)                            \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x14, 15, 1, value)
+#define GET_TX_DESC_BUFFER_NAVUSEHDR(txdesc)                                   \
+	LE_BITS_TO_4BYTE(txdesc + 0x14, 15, 1)
+#define SET_TX_DESC_BUFFER_BMC(txdesc, value)                                  \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x14, 14, 1, value)
+#define GET_TX_DESC_BUFFER_BMC(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x14, 14, 1)
+#define SET_TX_DESC_BUFFER_RTS_DATA_RTY_LMT(txdesc, value)                     \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x14, 8, 6, value)
+#define GET_TX_DESC_BUFFER_RTS_DATA_RTY_LMT(txdesc)                            \
+	LE_BITS_TO_4BYTE(txdesc + 0x14, 8, 6)
+#define SET_TX_DESC_BUFFER_HW_AES_IV(txdesc, value)                            \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x14, 7, 1, value)
+#define GET_TX_DESC_BUFFER_HW_AES_IV(txdesc)                                   \
+	LE_BITS_TO_4BYTE(txdesc + 0x14, 7, 1)
+#define SET_TX_DESC_BUFFER_BT_NULL(txdesc, value)                              \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x14, 3, 1, value)
+#define GET_TX_DESC_BUFFER_BT_NULL(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x14, 3, 1)
+#define SET_TX_DESC_BUFFER_EN_DESC_ID(txdesc, value)                           \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x14, 2, 1, value)
+#define GET_TX_DESC_BUFFER_EN_DESC_ID(txdesc)                                  \
+	LE_BITS_TO_4BYTE(txdesc + 0x14, 2, 1)
+#define SET_TX_DESC_BUFFER_SECTYPE(txdesc, value)                              \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x14, 0, 2, value)
+#define GET_TX_DESC_BUFFER_SECTYPE(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x14, 0, 2)
+
+/*TXDESC_WORD6*/
+
+#define SET_TX_DESC_BUFFER_MULTIPLE_PORT(txdesc, value)                        \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x18, 29, 3, value)
+#define GET_TX_DESC_BUFFER_MULTIPLE_PORT(txdesc)                               \
+	LE_BITS_TO_4BYTE(txdesc + 0x18, 29, 3)
+#define SET_TX_DESC_BUFFER_POLLUTED(txdesc, value)                             \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x18, 28, 1, value)
+#define GET_TX_DESC_BUFFER_POLLUTED(txdesc)                                    \
+	LE_BITS_TO_4BYTE(txdesc + 0x18, 28, 1)
+#define SET_TX_DESC_BUFFER_NULL_1(txdesc, value)                               \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x18, 27, 1, value)
+#define GET_TX_DESC_BUFFER_NULL_1(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x18, 27, 1)
+#define SET_TX_DESC_BUFFER_NULL_0(txdesc, value)                               \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x18, 26, 1, value)
+#define GET_TX_DESC_BUFFER_NULL_0(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x18, 26, 1)
+#define SET_TX_DESC_BUFFER_TRI_FRAME(txdesc, value)                            \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x18, 25, 1, value)
+#define GET_TX_DESC_BUFFER_TRI_FRAME(txdesc)                                   \
+	LE_BITS_TO_4BYTE(txdesc + 0x18, 25, 1)
+#define SET_TX_DESC_BUFFER_SPE_RPT(txdesc, value)                              \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x18, 24, 1, value)
+#define GET_TX_DESC_BUFFER_SPE_RPT(txdesc)                                     \
+	LE_BITS_TO_4BYTE(txdesc + 0x18, 24, 1)
+#define SET_TX_DESC_BUFFER_FTM_EN(txdesc, value)                               \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x18, 23, 1, value)
+#define GET_TX_DESC_BUFFER_FTM_EN(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x18, 23, 1)
+#define SET_TX_DESC_BUFFER_MU_DATARATE(txdesc, value)                          \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x18, 16, 7, value)
+#define GET_TX_DESC_BUFFER_MU_DATARATE(txdesc)                                 \
+	LE_BITS_TO_4BYTE(txdesc + 0x18, 16, 7)
+#define SET_TX_DESC_BUFFER_CCA_RTS(txdesc, value)                              \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x18, 14, 2, value)
+#define GET_TX_DESC_BUFFER_CCA_RTS(txdesc)                                     \
+	LE_BITS_TO_4BYTE(txdesc + 0x18, 14, 2)
+#define SET_TX_DESC_BUFFER_NDPA(txdesc, value)                                 \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x18, 12, 2, value)
+#define GET_TX_DESC_BUFFER_NDPA(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x18, 12, 2)
+#define SET_TX_DESC_BUFFER_TXPWR_OFSET_TYPE(txdesc, value)                     \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x18, 9, 2, value)
+#define GET_TX_DESC_BUFFER_TXPWR_OFSET_TYPE(txdesc)                            \
+	LE_BITS_TO_4BYTE(txdesc + 0x18, 9, 2)
+#define SET_TX_DESC_BUFFER_P_AID(txdesc, value)                                \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x18, 0, 9, value)
+#define GET_TX_DESC_BUFFER_P_AID(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x18, 0, 9)
+
+/*TXDESC_WORD7*/
+
+#define SET_TX_DESC_BUFFER_SW_DEFINE(txdesc, value)                            \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x1C, 16, 12, value)
+#define GET_TX_DESC_BUFFER_SW_DEFINE(txdesc)                                   \
+	LE_BITS_TO_4BYTE(txdesc + 0x1C, 16, 12)
+#define SET_TX_DESC_BUFFER_CTRL_CNT_VALID(txdesc, value)                       \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x1C, 9, 1, value)
+#define GET_TX_DESC_BUFFER_CTRL_CNT_VALID(txdesc)                              \
+	LE_BITS_TO_4BYTE(txdesc + 0x1C, 9, 1)
+#define SET_TX_DESC_BUFFER_CTRL_CNT(txdesc, value)                             \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x1C, 5, 4, value)
+#define GET_TX_DESC_BUFFER_CTRL_CNT(txdesc)                                    \
+	LE_BITS_TO_4BYTE(txdesc + 0x1C, 5, 4)
+#define SET_TX_DESC_BUFFER_DATA_RTY_LOWEST_RATE(txdesc, value)                 \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x1C, 0, 5, value)
+#define GET_TX_DESC_BUFFER_DATA_RTY_LOWEST_RATE(txdesc)                        \
+	LE_BITS_TO_4BYTE(txdesc + 0x1C, 0, 5)
+
+/*TXDESC_WORD8*/
+
+#define SET_TX_DESC_BUFFER_PATH_MAPA(txdesc, value)                            \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x20, 30, 2, value)
+#define GET_TX_DESC_BUFFER_PATH_MAPA(txdesc)                                   \
+	LE_BITS_TO_4BYTE(txdesc + 0x20, 30, 2)
+#define SET_TX_DESC_BUFFER_PATH_MAPB(txdesc, value)                            \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x20, 28, 2, value)
+#define GET_TX_DESC_BUFFER_PATH_MAPB(txdesc)                                   \
+	LE_BITS_TO_4BYTE(txdesc + 0x20, 28, 2)
+#define SET_TX_DESC_BUFFER_PATH_MAPC(txdesc, value)                            \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x20, 26, 2, value)
+#define GET_TX_DESC_BUFFER_PATH_MAPC(txdesc)                                   \
+	LE_BITS_TO_4BYTE(txdesc + 0x20, 26, 2)
+#define SET_TX_DESC_BUFFER_PATH_MAPD(txdesc, value)                            \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x20, 24, 2, value)
+#define GET_TX_DESC_BUFFER_PATH_MAPD(txdesc)                                   \
+	LE_BITS_TO_4BYTE(txdesc + 0x20, 24, 2)
+#define SET_TX_DESC_BUFFER_ANTSEL_A(txdesc, value)                             \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x20, 20, 4, value)
+#define GET_TX_DESC_BUFFER_ANTSEL_A(txdesc)                                    \
+	LE_BITS_TO_4BYTE(txdesc + 0x20, 20, 4)
+#define SET_TX_DESC_BUFFER_ANTSEL_B(txdesc, value)                             \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x20, 16, 4, value)
+#define GET_TX_DESC_BUFFER_ANTSEL_B(txdesc)                                    \
+	LE_BITS_TO_4BYTE(txdesc + 0x20, 16, 4)
+#define SET_TX_DESC_BUFFER_ANTSEL_C(txdesc, value)                             \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x20, 12, 4, value)
+#define GET_TX_DESC_BUFFER_ANTSEL_C(txdesc)                                    \
+	LE_BITS_TO_4BYTE(txdesc + 0x20, 12, 4)
+#define SET_TX_DESC_BUFFER_ANTSEL_D(txdesc, value)                             \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x20, 8, 4, value)
+#define GET_TX_DESC_BUFFER_ANTSEL_D(txdesc)                                    \
+	LE_BITS_TO_4BYTE(txdesc + 0x20, 8, 4)
+#define SET_TX_DESC_BUFFER_NTX_PATH_EN(txdesc, value)                          \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x20, 4, 4, value)
+#define GET_TX_DESC_BUFFER_NTX_PATH_EN(txdesc)                                 \
+	LE_BITS_TO_4BYTE(txdesc + 0x20, 4, 4)
+#define SET_TX_DESC_BUFFER_ANTLSEL_EN(txdesc, value)                           \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x20, 3, 1, value)
+#define GET_TX_DESC_BUFFER_ANTLSEL_EN(txdesc)                                  \
+	LE_BITS_TO_4BYTE(txdesc + 0x20, 3, 1)
+#define SET_TX_DESC_BUFFER_AMPDU_DENSITY(txdesc, value)                        \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x20, 0, 3, value)
+#define GET_TX_DESC_BUFFER_AMPDU_DENSITY(txdesc)                               \
+	LE_BITS_TO_4BYTE(txdesc + 0x20, 0, 3)
+
+/*TXDESC_WORD9*/
+
+#define SET_TX_DESC_BUFFER_VCS_STBC(txdesc, value)                             \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x24, 30, 2, value)
+#define GET_TX_DESC_BUFFER_VCS_STBC(txdesc)                                    \
+	LE_BITS_TO_4BYTE(txdesc + 0x24, 30, 2)
+#define SET_TX_DESC_BUFFER_DATA_STBC(txdesc, value)                            \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x24, 28, 2, value)
+#define GET_TX_DESC_BUFFER_DATA_STBC(txdesc)                                   \
+	LE_BITS_TO_4BYTE(txdesc + 0x24, 28, 2)
+#define SET_TX_DESC_BUFFER_RTS_RTY_LOWEST_RATE(txdesc, value)                  \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x24, 24, 4, value)
+#define GET_TX_DESC_BUFFER_RTS_RTY_LOWEST_RATE(txdesc)                         \
+	LE_BITS_TO_4BYTE(txdesc + 0x24, 24, 4)
+#define SET_TX_DESC_BUFFER_SIGNALING_TA_PKT_EN(txdesc, value)                  \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x24, 23, 1, value)
+#define GET_TX_DESC_BUFFER_SIGNALING_TA_PKT_EN(txdesc)                         \
+	LE_BITS_TO_4BYTE(txdesc + 0x24, 23, 1)
+#define SET_TX_DESC_BUFFER_MHR_CP(txdesc, value)                               \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x24, 22, 1, value)
+#define GET_TX_DESC_BUFFER_MHR_CP(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x24, 22, 1)
+#define SET_TX_DESC_BUFFER_SMH_EN(txdesc, value)                               \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x24, 21, 1, value)
+#define GET_TX_DESC_BUFFER_SMH_EN(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x24, 21, 1)
+#define SET_TX_DESC_BUFFER_RTSRATE(txdesc, value)                              \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x24, 16, 5, value)
+#define GET_TX_DESC_BUFFER_RTSRATE(txdesc)                                     \
+	LE_BITS_TO_4BYTE(txdesc + 0x24, 16, 5)
+#define SET_TX_DESC_BUFFER_SMH_CAM(txdesc, value)                              \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x24, 8, 8, value)
+#define GET_TX_DESC_BUFFER_SMH_CAM(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x24, 8, 8)
+#define SET_TX_DESC_BUFFER_ARFR_TABLE_SEL(txdesc, value)                       \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x24, 7, 1, value)
+#define GET_TX_DESC_BUFFER_ARFR_TABLE_SEL(txdesc)                              \
+	LE_BITS_TO_4BYTE(txdesc + 0x24, 7, 1)
+#define SET_TX_DESC_BUFFER_ARFR_HT_EN(txdesc, value)                           \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x24, 6, 1, value)
+#define GET_TX_DESC_BUFFER_ARFR_HT_EN(txdesc)                                  \
+	LE_BITS_TO_4BYTE(txdesc + 0x24, 6, 1)
+#define SET_TX_DESC_BUFFER_ARFR_OFDM_EN(txdesc, value)                         \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x24, 5, 1, value)
+#define GET_TX_DESC_BUFFER_ARFR_OFDM_EN(txdesc)                                \
+	LE_BITS_TO_4BYTE(txdesc + 0x24, 5, 1)
+#define SET_TX_DESC_BUFFER_ARFR_CCK_EN(txdesc, value)                          \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x24, 4, 1, value)
+#define GET_TX_DESC_BUFFER_ARFR_CCK_EN(txdesc)                                 \
+	LE_BITS_TO_4BYTE(txdesc + 0x24, 4, 1)
+#define SET_TX_DESC_BUFFER_RTS_SHORT(txdesc, value)                            \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x24, 3, 1, value)
+#define GET_TX_DESC_BUFFER_RTS_SHORT(txdesc)                                   \
+	LE_BITS_TO_4BYTE(txdesc + 0x24, 3, 1)
+#define SET_TX_DESC_BUFFER_DISDATAFB(txdesc, value)                            \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x24, 2, 1, value)
+#define GET_TX_DESC_BUFFER_DISDATAFB(txdesc)                                   \
+	LE_BITS_TO_4BYTE(txdesc + 0x24, 2, 1)
+#define SET_TX_DESC_BUFFER_DISRTSFB(txdesc, value)                             \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x24, 1, 1, value)
+#define GET_TX_DESC_BUFFER_DISRTSFB(txdesc)                                    \
+	LE_BITS_TO_4BYTE(txdesc + 0x24, 1, 1)
+#define SET_TX_DESC_BUFFER_EXT_EDCA(txdesc, value)                             \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x24, 0, 1, value)
+#define GET_TX_DESC_BUFFER_EXT_EDCA(txdesc)                                    \
+	LE_BITS_TO_4BYTE(txdesc + 0x24, 0, 1)
+
+/*TXDESC_WORD10*/
+
+#define SET_TX_DESC_BUFFER_AMPDU_MAX_TIME(txdesc, value)                       \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x28, 24, 8, value)
+#define GET_TX_DESC_BUFFER_AMPDU_MAX_TIME(txdesc)                              \
+	LE_BITS_TO_4BYTE(txdesc + 0x28, 24, 8)
+#define SET_TX_DESC_BUFFER_SPECIAL_CW(txdesc, value)                           \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x28, 23, 1, value)
+#define GET_TX_DESC_BUFFER_SPECIAL_CW(txdesc)                                  \
+	LE_BITS_TO_4BYTE(txdesc + 0x28, 23, 1)
+#define SET_TX_DESC_BUFFER_RDG_NAV_EXT(txdesc, value)                          \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x28, 22, 1, value)
+#define GET_TX_DESC_BUFFER_RDG_NAV_EXT(txdesc)                                 \
+	LE_BITS_TO_4BYTE(txdesc + 0x28, 22, 1)
+#define SET_TX_DESC_BUFFER_RAW(txdesc, value)                                  \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x28, 21, 1, value)
+#define GET_TX_DESC_BUFFER_RAW(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x28, 21, 1)
+#define SET_TX_DESC_BUFFER_MAX_AGG_NUM(txdesc, value)                          \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x28, 16, 5, value)
+#define GET_TX_DESC_BUFFER_MAX_AGG_NUM(txdesc)                                 \
+	LE_BITS_TO_4BYTE(txdesc + 0x28, 16, 5)
+#define SET_TX_DESC_BUFFER_FINAL_DATA_RATE(txdesc, value)                      \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x28, 8, 8, value)
+#define GET_TX_DESC_BUFFER_FINAL_DATA_RATE(txdesc)                             \
+	LE_BITS_TO_4BYTE(txdesc + 0x28, 8, 8)
+#define SET_TX_DESC_BUFFER_GF(txdesc, value)                                   \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x28, 7, 1, value)
+#define GET_TX_DESC_BUFFER_GF(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x28, 7, 1)
+#define SET_TX_DESC_BUFFER_MOREFRAG(txdesc, value)                             \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x28, 6, 1, value)
+#define GET_TX_DESC_BUFFER_MOREFRAG(txdesc)                                    \
+	LE_BITS_TO_4BYTE(txdesc + 0x28, 6, 1)
+#define SET_TX_DESC_BUFFER_NOACM(txdesc, value)                                \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x28, 5, 1, value)
+#define GET_TX_DESC_BUFFER_NOACM(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x28, 5, 1)
+#define SET_TX_DESC_BUFFER_HTC(txdesc, value)                                  \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x28, 4, 1, value)
+#define GET_TX_DESC_BUFFER_HTC(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x28, 4, 1)
+#define SET_TX_DESC_BUFFER_TX_PKT_AFTER_PIFS(txdesc, value)                    \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x28, 3, 1, value)
+#define GET_TX_DESC_BUFFER_TX_PKT_AFTER_PIFS(txdesc)                           \
+	LE_BITS_TO_4BYTE(txdesc + 0x28, 3, 1)
+#define SET_TX_DESC_BUFFER_USE_MAX_TIME_EN(txdesc, value)                      \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x28, 2, 1, value)
+#define GET_TX_DESC_BUFFER_USE_MAX_TIME_EN(txdesc)                             \
+	LE_BITS_TO_4BYTE(txdesc + 0x28, 2, 1)
+#define SET_TX_DESC_BUFFER_HW_SSN_SEL(txdesc, value)                           \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x28, 0, 2, value)
+#define GET_TX_DESC_BUFFER_HW_SSN_SEL(txdesc)                                  \
+	LE_BITS_TO_4BYTE(txdesc + 0x28, 0, 2)
+
+/*TXDESC_WORD11*/
+
+#define SET_TX_DESC_BUFFER_ADDR_CAM(txdesc, value)                             \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x2C, 24, 8, value)
+#define GET_TX_DESC_BUFFER_ADDR_CAM(txdesc)                                    \
+	LE_BITS_TO_4BYTE(txdesc + 0x2C, 24, 8)
+#define SET_TX_DESC_BUFFER_SND_TARGET(txdesc, value)                           \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x2C, 16, 8, value)
+#define GET_TX_DESC_BUFFER_SND_TARGET(txdesc)                                  \
+	LE_BITS_TO_4BYTE(txdesc + 0x2C, 16, 8)
+#define SET_TX_DESC_BUFFER_DATA_LDPC(txdesc, value)                            \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x2C, 15, 1, value)
+#define GET_TX_DESC_BUFFER_DATA_LDPC(txdesc)                                   \
+	LE_BITS_TO_4BYTE(txdesc + 0x2C, 15, 1)
+#define SET_TX_DESC_BUFFER_LSIG_TXOP_EN(txdesc, value)                         \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x2C, 14, 1, value)
+#define GET_TX_DESC_BUFFER_LSIG_TXOP_EN(txdesc)                                \
+	LE_BITS_TO_4BYTE(txdesc + 0x2C, 14, 1)
+#define SET_TX_DESC_BUFFER_G_ID(txdesc, value)                                 \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x2C, 8, 6, value)
+#define GET_TX_DESC_BUFFER_G_ID(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x2C, 8, 6)
+#define SET_TX_DESC_BUFFER_SIGNALING_TA_PKT_SC(txdesc, value)                  \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x2C, 4, 4, value)
+#define GET_TX_DESC_BUFFER_SIGNALING_TA_PKT_SC(txdesc)                         \
+	LE_BITS_TO_4BYTE(txdesc + 0x2C, 4, 4)
+#define SET_TX_DESC_BUFFER_DATA_SC(txdesc, value)                              \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x2C, 0, 4, value)
+#define GET_TX_DESC_BUFFER_DATA_SC(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x2C, 0, 4)
+
+/*TXDESC_WORD12*/
+
+#define SET_TX_DESC_BUFFER_LEN1_L(txdesc, value)                               \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x30, 17, 7, value)
+#define GET_TX_DESC_BUFFER_LEN1_L(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x30, 17, 7)
+#define SET_TX_DESC_BUFFER_LEN0(txdesc, value)                                 \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x30, 4, 13, value)
+#define GET_TX_DESC_BUFFER_LEN0(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x30, 4, 13)
+#define SET_TX_DESC_BUFFER_PKT_NUM(txdesc, value)                              \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x30, 0, 4, value)
+#define GET_TX_DESC_BUFFER_PKT_NUM(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x30, 0, 4)
+
+/*TXDESC_WORD13*/
+
+#define SET_TX_DESC_BUFFER_LEN3(txdesc, value)                                 \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x34, 19, 13, value)
+#define GET_TX_DESC_BUFFER_LEN3(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x34, 19, 13)
+#define SET_TX_DESC_BUFFER_LEN2(txdesc, value)                                 \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x34, 6, 13, value)
+#define GET_TX_DESC_BUFFER_LEN2(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x34, 6, 13)
+#define SET_TX_DESC_BUFFER_LEN1_H(txdesc, value)                               \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x34, 0, 6, value)
+#define GET_TX_DESC_BUFFER_LEN1_H(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x34, 0, 6)
+
+#endif
+
+#endif
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/halmac/halmac_tx_desc_chip.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/halmac/halmac_tx_desc_chip.h
--- linux-5.6.3/3rdparty/rtl8821ce/hal/halmac/halmac_tx_desc_chip.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/halmac/halmac_tx_desc_chip.h	2020-04-10 16:35:06.817660114 +0300
@@ -0,0 +1,2783 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ ******************************************************************************/
+
+#ifndef _HALMAC_TX_DESC_CHIP_H_
+#define _HALMAC_TX_DESC_CHIP_H_
+#if (HALMAC_8814A_SUPPORT)
+
+/*TXDESC_WORD0*/
+
+#define SET_TX_DESC_DISQSELSEQ_8814A(txdesc, value)                            \
+	SET_TX_DESC_DISQSELSEQ(txdesc, value)
+#define GET_TX_DESC_DISQSELSEQ_8814A(txdesc) GET_TX_DESC_DISQSELSEQ(txdesc)
+#define SET_TX_DESC_GF_8814A(txdesc, value) SET_TX_DESC_GF(txdesc, value)
+#define GET_TX_DESC_GF_8814A(txdesc) GET_TX_DESC_GF(txdesc)
+#define SET_TX_DESC_NO_ACM_8814A(txdesc, value)                                \
+	SET_TX_DESC_NO_ACM(txdesc, value)
+#define GET_TX_DESC_NO_ACM_8814A(txdesc) GET_TX_DESC_NO_ACM(txdesc)
+#define SET_TX_DESC_AMSDU_PAD_EN_8814A(txdesc, value)                          \
+	SET_TX_DESC_AMSDU_PAD_EN(txdesc, value)
+#define GET_TX_DESC_AMSDU_PAD_EN_8814A(txdesc) GET_TX_DESC_AMSDU_PAD_EN(txdesc)
+#define SET_TX_DESC_LS_8814A(txdesc, value) SET_TX_DESC_LS(txdesc, value)
+#define GET_TX_DESC_LS_8814A(txdesc) GET_TX_DESC_LS(txdesc)
+#define SET_TX_DESC_HTC_8814A(txdesc, value) SET_TX_DESC_HTC(txdesc, value)
+#define GET_TX_DESC_HTC_8814A(txdesc) GET_TX_DESC_HTC(txdesc)
+#define SET_TX_DESC_BMC_8814A(txdesc, value) SET_TX_DESC_BMC(txdesc, value)
+#define GET_TX_DESC_BMC_8814A(txdesc) GET_TX_DESC_BMC(txdesc)
+#define SET_TX_DESC_OFFSET_8814A(txdesc, value)                                \
+	SET_TX_DESC_OFFSET(txdesc, value)
+#define GET_TX_DESC_OFFSET_8814A(txdesc) GET_TX_DESC_OFFSET(txdesc)
+#define SET_TX_DESC_TXPKTSIZE_8814A(txdesc, value)                             \
+	SET_TX_DESC_TXPKTSIZE(txdesc, value)
+#define GET_TX_DESC_TXPKTSIZE_8814A(txdesc) GET_TX_DESC_TXPKTSIZE(txdesc)
+
+/*WORD1*/
+
+#define SET_TX_DESC_MOREDATA_8814A(txdesc, value)                              \
+	SET_TX_DESC_MOREDATA(txdesc, value)
+#define GET_TX_DESC_MOREDATA_8814A(txdesc) GET_TX_DESC_MOREDATA(txdesc)
+#define SET_TX_DESC_PKT_OFFSET_8814A(txdesc, value)                            \
+	SET_TX_DESC_PKT_OFFSET(txdesc, value)
+#define GET_TX_DESC_PKT_OFFSET_8814A(txdesc) GET_TX_DESC_PKT_OFFSET(txdesc)
+#define SET_TX_DESC_SEC_TYPE_8814A(txdesc, value)                              \
+	SET_TX_DESC_SEC_TYPE(txdesc, value)
+#define GET_TX_DESC_SEC_TYPE_8814A(txdesc) GET_TX_DESC_SEC_TYPE(txdesc)
+#define SET_TX_DESC_EN_DESC_ID_8814A(txdesc, value)                            \
+	SET_TX_DESC_EN_DESC_ID(txdesc, value)
+#define GET_TX_DESC_EN_DESC_ID_8814A(txdesc) GET_TX_DESC_EN_DESC_ID(txdesc)
+#define SET_TX_DESC_RATE_ID_8814A(txdesc, value)                               \
+	SET_TX_DESC_RATE_ID(txdesc, value)
+#define GET_TX_DESC_RATE_ID_8814A(txdesc) GET_TX_DESC_RATE_ID(txdesc)
+#define SET_TX_DESC_PIFS_8814A(txdesc, value) SET_TX_DESC_PIFS(txdesc, value)
+#define GET_TX_DESC_PIFS_8814A(txdesc) GET_TX_DESC_PIFS(txdesc)
+#define SET_TX_DESC_LSIG_TXOP_EN_8814A(txdesc, value)                          \
+	SET_TX_DESC_LSIG_TXOP_EN(txdesc, value)
+#define GET_TX_DESC_LSIG_TXOP_EN_8814A(txdesc) GET_TX_DESC_LSIG_TXOP_EN(txdesc)
+#define SET_TX_DESC_RD_NAV_EXT_8814A(txdesc, value)                            \
+	SET_TX_DESC_RD_NAV_EXT(txdesc, value)
+#define GET_TX_DESC_RD_NAV_EXT_8814A(txdesc) GET_TX_DESC_RD_NAV_EXT(txdesc)
+#define SET_TX_DESC_QSEL_8814A(txdesc, value) SET_TX_DESC_QSEL(txdesc, value)
+#define GET_TX_DESC_QSEL_8814A(txdesc) GET_TX_DESC_QSEL(txdesc)
+#define SET_TX_DESC_MACID_8814A(txdesc, value) SET_TX_DESC_MACID(txdesc, value)
+#define GET_TX_DESC_MACID_8814A(txdesc) GET_TX_DESC_MACID(txdesc)
+
+/*TXDESC_WORD2*/
+
+#define SET_TX_DESC_HW_AES_IV_8814A(txdesc, value)                             \
+	SET_TX_DESC_HW_AES_IV(txdesc, value)
+#define GET_TX_DESC_HW_AES_IV_8814A(txdesc) GET_TX_DESC_HW_AES_IV(txdesc)
+#define SET_TX_DESC_G_ID_8814A(txdesc, value) SET_TX_DESC_G_ID(txdesc, value)
+#define GET_TX_DESC_G_ID_8814A(txdesc) GET_TX_DESC_G_ID(txdesc)
+#define SET_TX_DESC_BT_NULL_8814A(txdesc, value)                               \
+	SET_TX_DESC_BT_NULL(txdesc, value)
+#define GET_TX_DESC_BT_NULL_8814A(txdesc) GET_TX_DESC_BT_NULL(txdesc)
+#define SET_TX_DESC_AMPDU_DENSITY_8814A(txdesc, value)                         \
+	SET_TX_DESC_AMPDU_DENSITY(txdesc, value)
+#define GET_TX_DESC_AMPDU_DENSITY_8814A(txdesc)                                \
+	GET_TX_DESC_AMPDU_DENSITY(txdesc)
+#define SET_TX_DESC_SPE_RPT_8814A(txdesc, value)                               \
+	SET_TX_DESC_SPE_RPT(txdesc, value)
+#define GET_TX_DESC_SPE_RPT_8814A(txdesc) GET_TX_DESC_SPE_RPT(txdesc)
+#define SET_TX_DESC_RAW_8814A(txdesc, value) SET_TX_DESC_RAW(txdesc, value)
+#define GET_TX_DESC_RAW_8814A(txdesc) GET_TX_DESC_RAW(txdesc)
+#define SET_TX_DESC_MOREFRAG_8814A(txdesc, value)                              \
+	SET_TX_DESC_MOREFRAG(txdesc, value)
+#define GET_TX_DESC_MOREFRAG_8814A(txdesc) GET_TX_DESC_MOREFRAG(txdesc)
+#define SET_TX_DESC_BK_8814A(txdesc, value) SET_TX_DESC_BK(txdesc, value)
+#define GET_TX_DESC_BK_8814A(txdesc) GET_TX_DESC_BK(txdesc)
+#define SET_TX_DESC_NULL_1_8814A(txdesc, value)                                \
+	SET_TX_DESC_NULL_1(txdesc, value)
+#define GET_TX_DESC_NULL_1_8814A(txdesc) GET_TX_DESC_NULL_1(txdesc)
+#define SET_TX_DESC_NULL_0_8814A(txdesc, value)                                \
+	SET_TX_DESC_NULL_0(txdesc, value)
+#define GET_TX_DESC_NULL_0_8814A(txdesc) GET_TX_DESC_NULL_0(txdesc)
+#define SET_TX_DESC_RDG_EN_8814A(txdesc, value)                                \
+	SET_TX_DESC_RDG_EN(txdesc, value)
+#define GET_TX_DESC_RDG_EN_8814A(txdesc) GET_TX_DESC_RDG_EN(txdesc)
+#define SET_TX_DESC_AGG_EN_8814A(txdesc, value)                                \
+	SET_TX_DESC_AGG_EN(txdesc, value)
+#define GET_TX_DESC_AGG_EN_8814A(txdesc) GET_TX_DESC_AGG_EN(txdesc)
+#define SET_TX_DESC_CCA_RTS_8814A(txdesc, value)                               \
+	SET_TX_DESC_CCA_RTS(txdesc, value)
+#define GET_TX_DESC_CCA_RTS_8814A(txdesc) GET_TX_DESC_CCA_RTS(txdesc)
+#define SET_TX_DESC_P_AID_8814A(txdesc, value) SET_TX_DESC_P_AID(txdesc, value)
+#define GET_TX_DESC_P_AID_8814A(txdesc) GET_TX_DESC_P_AID(txdesc)
+
+/*TXDESC_WORD3*/
+
+#define SET_TX_DESC_AMPDU_MAX_TIME_8814A(txdesc, value)                        \
+	SET_TX_DESC_AMPDU_MAX_TIME(txdesc, value)
+#define GET_TX_DESC_AMPDU_MAX_TIME_8814A(txdesc)                               \
+	GET_TX_DESC_AMPDU_MAX_TIME(txdesc)
+#define SET_TX_DESC_NDPA_8814A(txdesc, value) SET_TX_DESC_NDPA(txdesc, value)
+#define GET_TX_DESC_NDPA_8814A(txdesc) GET_TX_DESC_NDPA(txdesc)
+#define SET_TX_DESC_MAX_AGG_NUM_8814A(txdesc, value)                           \
+	SET_TX_DESC_MAX_AGG_NUM(txdesc, value)
+#define GET_TX_DESC_MAX_AGG_NUM_8814A(txdesc) GET_TX_DESC_MAX_AGG_NUM(txdesc)
+#define SET_TX_DESC_USE_MAX_TIME_EN_8814A(txdesc, value)                       \
+	SET_TX_DESC_USE_MAX_TIME_EN(txdesc, value)
+#define GET_TX_DESC_USE_MAX_TIME_EN_8814A(txdesc)                              \
+	GET_TX_DESC_USE_MAX_TIME_EN(txdesc)
+#define SET_TX_DESC_NAVUSEHDR_8814A(txdesc, value)                             \
+	SET_TX_DESC_NAVUSEHDR(txdesc, value)
+#define GET_TX_DESC_NAVUSEHDR_8814A(txdesc) GET_TX_DESC_NAVUSEHDR(txdesc)
+#define SET_TX_DESC_CHK_EN_8814A(txdesc, value)                                \
+	SET_TX_DESC_CHK_EN(txdesc, value)
+#define GET_TX_DESC_CHK_EN_8814A(txdesc) GET_TX_DESC_CHK_EN(txdesc)
+#define SET_TX_DESC_HW_RTS_EN_8814A(txdesc, value)                             \
+	SET_TX_DESC_HW_RTS_EN(txdesc, value)
+#define GET_TX_DESC_HW_RTS_EN_8814A(txdesc) GET_TX_DESC_HW_RTS_EN(txdesc)
+#define SET_TX_DESC_RTSEN_8814A(txdesc, value) SET_TX_DESC_RTSEN(txdesc, value)
+#define GET_TX_DESC_RTSEN_8814A(txdesc) GET_TX_DESC_RTSEN(txdesc)
+#define SET_TX_DESC_CTS2SELF_8814A(txdesc, value)                              \
+	SET_TX_DESC_CTS2SELF(txdesc, value)
+#define GET_TX_DESC_CTS2SELF_8814A(txdesc) GET_TX_DESC_CTS2SELF(txdesc)
+#define SET_TX_DESC_DISDATAFB_8814A(txdesc, value)                             \
+	SET_TX_DESC_DISDATAFB(txdesc, value)
+#define GET_TX_DESC_DISDATAFB_8814A(txdesc) GET_TX_DESC_DISDATAFB(txdesc)
+#define SET_TX_DESC_DISRTSFB_8814A(txdesc, value)                              \
+	SET_TX_DESC_DISRTSFB(txdesc, value)
+#define GET_TX_DESC_DISRTSFB_8814A(txdesc) GET_TX_DESC_DISRTSFB(txdesc)
+#define SET_TX_DESC_USE_RATE_8814A(txdesc, value)                              \
+	SET_TX_DESC_USE_RATE(txdesc, value)
+#define GET_TX_DESC_USE_RATE_8814A(txdesc) GET_TX_DESC_USE_RATE(txdesc)
+#define SET_TX_DESC_HW_SSN_SEL_8814A(txdesc, value)                            \
+	SET_TX_DESC_HW_SSN_SEL(txdesc, value)
+#define GET_TX_DESC_HW_SSN_SEL_8814A(txdesc) GET_TX_DESC_HW_SSN_SEL(txdesc)
+#define SET_TX_DESC_WHEADER_LEN_8814A(txdesc, value)                           \
+	SET_TX_DESC_WHEADER_LEN(txdesc, value)
+#define GET_TX_DESC_WHEADER_LEN_8814A(txdesc) GET_TX_DESC_WHEADER_LEN(txdesc)
+
+/*TXDESC_WORD4*/
+
+#define SET_TX_DESC_PCTS_MASK_IDX_8814A(txdesc, value)                         \
+	SET_TX_DESC_PCTS_MASK_IDX(txdesc, value)
+#define GET_TX_DESC_PCTS_MASK_IDX_8814A(txdesc)                                \
+	GET_TX_DESC_PCTS_MASK_IDX(txdesc)
+#define SET_TX_DESC_PCTS_EN_8814A(txdesc, value)                               \
+	SET_TX_DESC_PCTS_EN(txdesc, value)
+#define GET_TX_DESC_PCTS_EN_8814A(txdesc) GET_TX_DESC_PCTS_EN(txdesc)
+#define SET_TX_DESC_RTSRATE_8814A(txdesc, value)                               \
+	SET_TX_DESC_RTSRATE(txdesc, value)
+#define GET_TX_DESC_RTSRATE_8814A(txdesc) GET_TX_DESC_RTSRATE(txdesc)
+#define SET_TX_DESC_RTS_DATA_RTY_LMT_8814A(txdesc, value)                      \
+	SET_TX_DESC_RTS_DATA_RTY_LMT(txdesc, value)
+#define GET_TX_DESC_RTS_DATA_RTY_LMT_8814A(txdesc)                             \
+	GET_TX_DESC_RTS_DATA_RTY_LMT(txdesc)
+#define SET_TX_DESC_RTY_LMT_EN_8814A(txdesc, value)                            \
+	SET_TX_DESC_RTY_LMT_EN(txdesc, value)
+#define GET_TX_DESC_RTY_LMT_EN_8814A(txdesc) GET_TX_DESC_RTY_LMT_EN(txdesc)
+#define SET_TX_DESC_RTS_RTY_LOWEST_RATE_8814A(txdesc, value)                   \
+	SET_TX_DESC_RTS_RTY_LOWEST_RATE(txdesc, value)
+#define GET_TX_DESC_RTS_RTY_LOWEST_RATE_8814A(txdesc)                          \
+	GET_TX_DESC_RTS_RTY_LOWEST_RATE(txdesc)
+#define SET_TX_DESC_DATA_RTY_LOWEST_RATE_8814A(txdesc, value)                  \
+	SET_TX_DESC_DATA_RTY_LOWEST_RATE(txdesc, value)
+#define GET_TX_DESC_DATA_RTY_LOWEST_RATE_8814A(txdesc)                         \
+	GET_TX_DESC_DATA_RTY_LOWEST_RATE(txdesc)
+#define SET_TX_DESC_TRY_RATE_8814A(txdesc, value)                              \
+	SET_TX_DESC_TRY_RATE(txdesc, value)
+#define GET_TX_DESC_TRY_RATE_8814A(txdesc) GET_TX_DESC_TRY_RATE(txdesc)
+#define SET_TX_DESC_DATARATE_8814A(txdesc, value)                              \
+	SET_TX_DESC_DATARATE(txdesc, value)
+#define GET_TX_DESC_DATARATE_8814A(txdesc) GET_TX_DESC_DATARATE(txdesc)
+
+/*TXDESC_WORD5*/
+
+#define SET_TX_DESC_POLLUTED_8814A(txdesc, value)                              \
+	SET_TX_DESC_POLLUTED(txdesc, value)
+#define GET_TX_DESC_POLLUTED_8814A(txdesc) GET_TX_DESC_POLLUTED(txdesc)
+#define SET_TX_DESC_TXPWR_OFSET_8814A(txdesc, value)                           \
+	SET_TX_DESC_TXPWR_OFSET(txdesc, value)
+#define GET_TX_DESC_TXPWR_OFSET_8814A(txdesc) GET_TX_DESC_TXPWR_OFSET(txdesc)
+#define SET_TX_DESC_TX_ANT_8814A(txdesc, value)                                \
+	SET_TX_DESC_TX_ANT(txdesc, value)
+#define GET_TX_DESC_TX_ANT_8814A(txdesc) GET_TX_DESC_TX_ANT(txdesc)
+#define SET_TX_DESC_PORT_ID_8814A(txdesc, value)                               \
+	SET_TX_DESC_PORT_ID(txdesc, value)
+#define GET_TX_DESC_PORT_ID_8814A(txdesc) GET_TX_DESC_PORT_ID(txdesc)
+#define SET_TX_DESC_SIGNALING_TAPKT_EN_8814A(txdesc, value)                    \
+	SET_TX_DESC_SIGNALING_TAPKT_EN(txdesc, value)
+#define GET_TX_DESC_SIGNALING_TAPKT_EN_8814A(txdesc)                           \
+	GET_TX_DESC_SIGNALING_TAPKT_EN(txdesc)
+#define SET_TX_DESC_RTS_SC_8814A(txdesc, value)                                \
+	SET_TX_DESC_RTS_SC(txdesc, value)
+#define GET_TX_DESC_RTS_SC_8814A(txdesc) GET_TX_DESC_RTS_SC(txdesc)
+#define SET_TX_DESC_RTS_SHORT_8814A(txdesc, value)                             \
+	SET_TX_DESC_RTS_SHORT(txdesc, value)
+#define GET_TX_DESC_RTS_SHORT_8814A(txdesc) GET_TX_DESC_RTS_SHORT(txdesc)
+#define SET_TX_DESC_VCS_STBC_8814A(txdesc, value)                              \
+	SET_TX_DESC_VCS_STBC(txdesc, value)
+#define GET_TX_DESC_VCS_STBC_8814A(txdesc) GET_TX_DESC_VCS_STBC(txdesc)
+#define SET_TX_DESC_DATA_STBC_8814A(txdesc, value)                             \
+	SET_TX_DESC_DATA_STBC(txdesc, value)
+#define GET_TX_DESC_DATA_STBC_8814A(txdesc) GET_TX_DESC_DATA_STBC(txdesc)
+#define SET_TX_DESC_DATA_LDPC_8814A(txdesc, value)                             \
+	SET_TX_DESC_DATA_LDPC(txdesc, value)
+#define GET_TX_DESC_DATA_LDPC_8814A(txdesc) GET_TX_DESC_DATA_LDPC(txdesc)
+#define SET_TX_DESC_DATA_BW_8814A(txdesc, value)                               \
+	SET_TX_DESC_DATA_BW(txdesc, value)
+#define GET_TX_DESC_DATA_BW_8814A(txdesc) GET_TX_DESC_DATA_BW(txdesc)
+#define SET_TX_DESC_DATA_SHORT_8814A(txdesc, value)                            \
+	SET_TX_DESC_DATA_SHORT(txdesc, value)
+#define GET_TX_DESC_DATA_SHORT_8814A(txdesc) GET_TX_DESC_DATA_SHORT(txdesc)
+#define SET_TX_DESC_DATA_SC_8814A(txdesc, value)                               \
+	SET_TX_DESC_DATA_SC(txdesc, value)
+#define GET_TX_DESC_DATA_SC_8814A(txdesc) GET_TX_DESC_DATA_SC(txdesc)
+
+/*TXDESC_WORD6*/
+
+#define SET_TX_DESC_ANTSEL_D_8814A(txdesc, value)                              \
+	SET_TX_DESC_ANTSEL_D(txdesc, value)
+#define GET_TX_DESC_ANTSEL_D_8814A(txdesc) GET_TX_DESC_ANTSEL_D(txdesc)
+#define SET_TX_DESC_ANT_MAPD_8814A(txdesc, value)                              \
+	SET_TX_DESC_ANT_MAPD(txdesc, value)
+#define GET_TX_DESC_ANT_MAPD_8814A(txdesc) GET_TX_DESC_ANT_MAPD(txdesc)
+#define SET_TX_DESC_ANT_MAPC_8814A(txdesc, value)                              \
+	SET_TX_DESC_ANT_MAPC(txdesc, value)
+#define GET_TX_DESC_ANT_MAPC_8814A(txdesc) GET_TX_DESC_ANT_MAPC(txdesc)
+#define SET_TX_DESC_ANT_MAPB_8814A(txdesc, value)                              \
+	SET_TX_DESC_ANT_MAPB(txdesc, value)
+#define GET_TX_DESC_ANT_MAPB_8814A(txdesc) GET_TX_DESC_ANT_MAPB(txdesc)
+#define SET_TX_DESC_ANT_MAPA_8814A(txdesc, value)                              \
+	SET_TX_DESC_ANT_MAPA(txdesc, value)
+#define GET_TX_DESC_ANT_MAPA_8814A(txdesc) GET_TX_DESC_ANT_MAPA(txdesc)
+#define SET_TX_DESC_ANTSEL_C_8814A(txdesc, value)                              \
+	SET_TX_DESC_ANTSEL_C(txdesc, value)
+#define GET_TX_DESC_ANTSEL_C_8814A(txdesc) GET_TX_DESC_ANTSEL_C(txdesc)
+#define SET_TX_DESC_ANTSEL_B_8814A(txdesc, value)                              \
+	SET_TX_DESC_ANTSEL_B(txdesc, value)
+#define GET_TX_DESC_ANTSEL_B_8814A(txdesc) GET_TX_DESC_ANTSEL_B(txdesc)
+#define SET_TX_DESC_ANTSEL_A_8814A(txdesc, value)                              \
+	SET_TX_DESC_ANTSEL_A(txdesc, value)
+#define GET_TX_DESC_ANTSEL_A_8814A(txdesc) GET_TX_DESC_ANTSEL_A(txdesc)
+#define SET_TX_DESC_MBSSID_8814A(txdesc, value)                                \
+	SET_TX_DESC_MBSSID(txdesc, value)
+#define GET_TX_DESC_MBSSID_8814A(txdesc) GET_TX_DESC_MBSSID(txdesc)
+#define SET_TX_DESC_SW_DEFINE_8814A(txdesc, value)                             \
+	SET_TX_DESC_SW_DEFINE(txdesc, value)
+#define GET_TX_DESC_SW_DEFINE_8814A(txdesc) GET_TX_DESC_SW_DEFINE(txdesc)
+
+/*TXDESC_WORD7*/
+
+#define SET_TX_DESC_DMA_TXAGG_NUM_8814A(txdesc, value)                         \
+	SET_TX_DESC_DMA_TXAGG_NUM(txdesc, value)
+#define GET_TX_DESC_DMA_TXAGG_NUM_8814A(txdesc)                                \
+	GET_TX_DESC_DMA_TXAGG_NUM(txdesc)
+#define SET_TX_DESC_FINAL_DATA_RATE_8814A(txdesc, value)                       \
+	SET_TX_DESC_FINAL_DATA_RATE(txdesc, value)
+#define GET_TX_DESC_FINAL_DATA_RATE_8814A(txdesc)                              \
+	GET_TX_DESC_FINAL_DATA_RATE(txdesc)
+#define SET_TX_DESC_NTX_MAP_8814A(txdesc, value)                               \
+	SET_TX_DESC_NTX_MAP(txdesc, value)
+#define GET_TX_DESC_NTX_MAP_8814A(txdesc) GET_TX_DESC_NTX_MAP(txdesc)
+#define SET_TX_DESC_TX_BUFF_SIZE_8814A(txdesc, value)                          \
+	SET_TX_DESC_TX_BUFF_SIZE(txdesc, value)
+#define GET_TX_DESC_TX_BUFF_SIZE_8814A(txdesc) GET_TX_DESC_TX_BUFF_SIZE(txdesc)
+#define SET_TX_DESC_TXDESC_CHECKSUM_8814A(txdesc, value)                       \
+	SET_TX_DESC_TXDESC_CHECKSUM(txdesc, value)
+#define GET_TX_DESC_TXDESC_CHECKSUM_8814A(txdesc)                              \
+	GET_TX_DESC_TXDESC_CHECKSUM(txdesc)
+#define SET_TX_DESC_TIMESTAMP_8814A(txdesc, value)                             \
+	SET_TX_DESC_TIMESTAMP(txdesc, value)
+#define GET_TX_DESC_TIMESTAMP_8814A(txdesc) GET_TX_DESC_TIMESTAMP(txdesc)
+
+/*TXDESC_WORD8*/
+
+#define SET_TX_DESC_TXWIFI_CP_8814A(txdesc, value)                             \
+	SET_TX_DESC_TXWIFI_CP(txdesc, value)
+#define GET_TX_DESC_TXWIFI_CP_8814A(txdesc) GET_TX_DESC_TXWIFI_CP(txdesc)
+#define SET_TX_DESC_MAC_CP_8814A(txdesc, value)                                \
+	SET_TX_DESC_MAC_CP(txdesc, value)
+#define GET_TX_DESC_MAC_CP_8814A(txdesc) GET_TX_DESC_MAC_CP(txdesc)
+#define SET_TX_DESC_STW_PKTRE_DIS_8814A(txdesc, value)                         \
+	SET_TX_DESC_STW_PKTRE_DIS(txdesc, value)
+#define GET_TX_DESC_STW_PKTRE_DIS_8814A(txdesc)                                \
+	GET_TX_DESC_STW_PKTRE_DIS(txdesc)
+#define SET_TX_DESC_STW_RB_DIS_8814A(txdesc, value)                            \
+	SET_TX_DESC_STW_RB_DIS(txdesc, value)
+#define GET_TX_DESC_STW_RB_DIS_8814A(txdesc) GET_TX_DESC_STW_RB_DIS(txdesc)
+#define SET_TX_DESC_STW_RATE_DIS_8814A(txdesc, value)                          \
+	SET_TX_DESC_STW_RATE_DIS(txdesc, value)
+#define GET_TX_DESC_STW_RATE_DIS_8814A(txdesc) GET_TX_DESC_STW_RATE_DIS(txdesc)
+#define SET_TX_DESC_STW_ANT_DIS_8814A(txdesc, value)                           \
+	SET_TX_DESC_STW_ANT_DIS(txdesc, value)
+#define GET_TX_DESC_STW_ANT_DIS_8814A(txdesc) GET_TX_DESC_STW_ANT_DIS(txdesc)
+#define SET_TX_DESC_STW_EN_8814A(txdesc, value)                                \
+	SET_TX_DESC_STW_EN(txdesc, value)
+#define GET_TX_DESC_STW_EN_8814A(txdesc) GET_TX_DESC_STW_EN(txdesc)
+#define SET_TX_DESC_SMH_EN_8814A(txdesc, value)                                \
+	SET_TX_DESC_SMH_EN(txdesc, value)
+#define GET_TX_DESC_SMH_EN_8814A(txdesc) GET_TX_DESC_SMH_EN(txdesc)
+#define SET_TX_DESC_TAILPAGE_L_8814A(txdesc, value)                            \
+	SET_TX_DESC_TAILPAGE_L(txdesc, value)
+#define GET_TX_DESC_TAILPAGE_L_8814A(txdesc) GET_TX_DESC_TAILPAGE_L(txdesc)
+#define SET_TX_DESC_SDIO_DMASEQ_8814A(txdesc, value)                           \
+	SET_TX_DESC_SDIO_DMASEQ(txdesc, value)
+#define GET_TX_DESC_SDIO_DMASEQ_8814A(txdesc) GET_TX_DESC_SDIO_DMASEQ(txdesc)
+#define SET_TX_DESC_NEXTHEADPAGE_L_8814A(txdesc, value)                        \
+	SET_TX_DESC_NEXTHEADPAGE_L(txdesc, value)
+#define GET_TX_DESC_NEXTHEADPAGE_L_8814A(txdesc)                               \
+	GET_TX_DESC_NEXTHEADPAGE_L(txdesc)
+#define SET_TX_DESC_EN_HWSEQ_8814A(txdesc, value)                              \
+	SET_TX_DESC_EN_HWSEQ(txdesc, value)
+#define GET_TX_DESC_EN_HWSEQ_8814A(txdesc) GET_TX_DESC_EN_HWSEQ(txdesc)
+#define SET_TX_DESC_EN_HWEXSEQ_8814A(txdesc, value)                            \
+	SET_TX_DESC_EN_HWEXSEQ(txdesc, value)
+#define GET_TX_DESC_EN_HWEXSEQ_8814A(txdesc) GET_TX_DESC_EN_HWEXSEQ(txdesc)
+#define SET_TX_DESC_DATA_RC_8814A(txdesc, value)                               \
+	SET_TX_DESC_DATA_RC(txdesc, value)
+#define GET_TX_DESC_DATA_RC_8814A(txdesc) GET_TX_DESC_DATA_RC(txdesc)
+#define SET_TX_DESC_BAR_RTY_TH_8814A(txdesc, value)                            \
+	SET_TX_DESC_BAR_RTY_TH(txdesc, value)
+#define GET_TX_DESC_BAR_RTY_TH_8814A(txdesc) GET_TX_DESC_BAR_RTY_TH(txdesc)
+#define SET_TX_DESC_RTS_RC_8814A(txdesc, value)                                \
+	SET_TX_DESC_RTS_RC(txdesc, value)
+#define GET_TX_DESC_RTS_RC_8814A(txdesc) GET_TX_DESC_RTS_RC(txdesc)
+
+/*TXDESC_WORD9*/
+
+#define SET_TX_DESC_TAILPAGE_H_8814A(txdesc, value)                            \
+	SET_TX_DESC_TAILPAGE_H(txdesc, value)
+#define GET_TX_DESC_TAILPAGE_H_8814A(txdesc) GET_TX_DESC_TAILPAGE_H(txdesc)
+#define SET_TX_DESC_NEXTHEADPAGE_H_8814A(txdesc, value)                        \
+	SET_TX_DESC_NEXTHEADPAGE_H(txdesc, value)
+#define GET_TX_DESC_NEXTHEADPAGE_H_8814A(txdesc)                               \
+	GET_TX_DESC_NEXTHEADPAGE_H(txdesc)
+#define SET_TX_DESC_SW_SEQ_8814A(txdesc, value)                                \
+	SET_TX_DESC_SW_SEQ(txdesc, value)
+#define GET_TX_DESC_SW_SEQ_8814A(txdesc) GET_TX_DESC_SW_SEQ(txdesc)
+#define SET_TX_DESC_TXBF_PATH_8814A(txdesc, value)                             \
+	SET_TX_DESC_TXBF_PATH(txdesc, value)
+#define GET_TX_DESC_TXBF_PATH_8814A(txdesc) GET_TX_DESC_TXBF_PATH(txdesc)
+#define SET_TX_DESC_PADDING_LEN_8814A(txdesc, value)                           \
+	SET_TX_DESC_PADDING_LEN(txdesc, value)
+#define GET_TX_DESC_PADDING_LEN_8814A(txdesc) GET_TX_DESC_PADDING_LEN(txdesc)
+#define SET_TX_DESC_GROUP_BIT_IE_OFFSET_8814A(txdesc, value)                   \
+	SET_TX_DESC_GROUP_BIT_IE_OFFSET(txdesc, value)
+#define GET_TX_DESC_GROUP_BIT_IE_OFFSET_8814A(txdesc)                          \
+	GET_TX_DESC_GROUP_BIT_IE_OFFSET(txdesc)
+
+/*WORD10*/
+
+#endif
+
+#if (HALMAC_8822B_SUPPORT)
+
+/*TXDESC_WORD0*/
+
+#define SET_TX_DESC_DISQSELSEQ_8822B(txdesc, value)                            \
+	SET_TX_DESC_DISQSELSEQ(txdesc, value)
+#define GET_TX_DESC_DISQSELSEQ_8822B(txdesc) GET_TX_DESC_DISQSELSEQ(txdesc)
+#define SET_TX_DESC_GF_8822B(txdesc, value) SET_TX_DESC_GF(txdesc, value)
+#define GET_TX_DESC_GF_8822B(txdesc) GET_TX_DESC_GF(txdesc)
+#define SET_TX_DESC_NO_ACM_8822B(txdesc, value)                                \
+	SET_TX_DESC_NO_ACM(txdesc, value)
+#define GET_TX_DESC_NO_ACM_8822B(txdesc) GET_TX_DESC_NO_ACM(txdesc)
+#define SET_TX_DESC_BCNPKT_TSF_CTRL_8822B(txdesc, value)                       \
+	SET_TX_DESC_BCNPKT_TSF_CTRL(txdesc, value)
+#define GET_TX_DESC_BCNPKT_TSF_CTRL_8822B(txdesc)                              \
+	GET_TX_DESC_BCNPKT_TSF_CTRL(txdesc)
+#define SET_TX_DESC_AMSDU_PAD_EN_8822B(txdesc, value)                          \
+	SET_TX_DESC_AMSDU_PAD_EN(txdesc, value)
+#define GET_TX_DESC_AMSDU_PAD_EN_8822B(txdesc) GET_TX_DESC_AMSDU_PAD_EN(txdesc)
+#define SET_TX_DESC_LS_8822B(txdesc, value) SET_TX_DESC_LS(txdesc, value)
+#define GET_TX_DESC_LS_8822B(txdesc) GET_TX_DESC_LS(txdesc)
+#define SET_TX_DESC_HTC_8822B(txdesc, value) SET_TX_DESC_HTC(txdesc, value)
+#define GET_TX_DESC_HTC_8822B(txdesc) GET_TX_DESC_HTC(txdesc)
+#define SET_TX_DESC_BMC_8822B(txdesc, value) SET_TX_DESC_BMC(txdesc, value)
+#define GET_TX_DESC_BMC_8822B(txdesc) GET_TX_DESC_BMC(txdesc)
+#define SET_TX_DESC_OFFSET_8822B(txdesc, value)                                \
+	SET_TX_DESC_OFFSET(txdesc, value)
+#define GET_TX_DESC_OFFSET_8822B(txdesc) GET_TX_DESC_OFFSET(txdesc)
+#define SET_TX_DESC_TXPKTSIZE_8822B(txdesc, value)                             \
+	SET_TX_DESC_TXPKTSIZE(txdesc, value)
+#define GET_TX_DESC_TXPKTSIZE_8822B(txdesc) GET_TX_DESC_TXPKTSIZE(txdesc)
+
+/*WORD1*/
+
+#define SET_TX_DESC_MOREDATA_8822B(txdesc, value)                              \
+	SET_TX_DESC_MOREDATA(txdesc, value)
+#define GET_TX_DESC_MOREDATA_8822B(txdesc) GET_TX_DESC_MOREDATA(txdesc)
+#define SET_TX_DESC_PKT_OFFSET_8822B(txdesc, value)                            \
+	SET_TX_DESC_PKT_OFFSET(txdesc, value)
+#define GET_TX_DESC_PKT_OFFSET_8822B(txdesc) GET_TX_DESC_PKT_OFFSET(txdesc)
+#define SET_TX_DESC_SEC_TYPE_8822B(txdesc, value)                              \
+	SET_TX_DESC_SEC_TYPE(txdesc, value)
+#define GET_TX_DESC_SEC_TYPE_8822B(txdesc) GET_TX_DESC_SEC_TYPE(txdesc)
+#define SET_TX_DESC_EN_DESC_ID_8822B(txdesc, value)                            \
+	SET_TX_DESC_EN_DESC_ID(txdesc, value)
+#define GET_TX_DESC_EN_DESC_ID_8822B(txdesc) GET_TX_DESC_EN_DESC_ID(txdesc)
+#define SET_TX_DESC_RATE_ID_8822B(txdesc, value)                               \
+	SET_TX_DESC_RATE_ID(txdesc, value)
+#define GET_TX_DESC_RATE_ID_8822B(txdesc) GET_TX_DESC_RATE_ID(txdesc)
+#define SET_TX_DESC_PIFS_8822B(txdesc, value) SET_TX_DESC_PIFS(txdesc, value)
+#define GET_TX_DESC_PIFS_8822B(txdesc) GET_TX_DESC_PIFS(txdesc)
+#define SET_TX_DESC_LSIG_TXOP_EN_8822B(txdesc, value)                          \
+	SET_TX_DESC_LSIG_TXOP_EN(txdesc, value)
+#define GET_TX_DESC_LSIG_TXOP_EN_8822B(txdesc) GET_TX_DESC_LSIG_TXOP_EN(txdesc)
+#define SET_TX_DESC_RD_NAV_EXT_8822B(txdesc, value)                            \
+	SET_TX_DESC_RD_NAV_EXT(txdesc, value)
+#define GET_TX_DESC_RD_NAV_EXT_8822B(txdesc) GET_TX_DESC_RD_NAV_EXT(txdesc)
+#define SET_TX_DESC_QSEL_8822B(txdesc, value) SET_TX_DESC_QSEL(txdesc, value)
+#define GET_TX_DESC_QSEL_8822B(txdesc) GET_TX_DESC_QSEL(txdesc)
+#define SET_TX_DESC_MACID_8822B(txdesc, value) SET_TX_DESC_MACID(txdesc, value)
+#define GET_TX_DESC_MACID_8822B(txdesc) GET_TX_DESC_MACID(txdesc)
+
+/*TXDESC_WORD2*/
+
+#define SET_TX_DESC_HW_AES_IV_8822B(txdesc, value)                             \
+	SET_TX_DESC_HW_AES_IV(txdesc, value)
+#define GET_TX_DESC_HW_AES_IV_8822B(txdesc) GET_TX_DESC_HW_AES_IV(txdesc)
+#define SET_TX_DESC_FTM_EN_8822B(txdesc, value)                                \
+	SET_TX_DESC_FTM_EN(txdesc, value)
+#define GET_TX_DESC_FTM_EN_8822B(txdesc) GET_TX_DESC_FTM_EN(txdesc)
+#define SET_TX_DESC_G_ID_8822B(txdesc, value) SET_TX_DESC_G_ID(txdesc, value)
+#define GET_TX_DESC_G_ID_8822B(txdesc) GET_TX_DESC_G_ID(txdesc)
+#define SET_TX_DESC_BT_NULL_8822B(txdesc, value)                               \
+	SET_TX_DESC_BT_NULL(txdesc, value)
+#define GET_TX_DESC_BT_NULL_8822B(txdesc) GET_TX_DESC_BT_NULL(txdesc)
+#define SET_TX_DESC_AMPDU_DENSITY_8822B(txdesc, value)                         \
+	SET_TX_DESC_AMPDU_DENSITY(txdesc, value)
+#define GET_TX_DESC_AMPDU_DENSITY_8822B(txdesc)                                \
+	GET_TX_DESC_AMPDU_DENSITY(txdesc)
+#define SET_TX_DESC_SPE_RPT_8822B(txdesc, value)                               \
+	SET_TX_DESC_SPE_RPT(txdesc, value)
+#define GET_TX_DESC_SPE_RPT_8822B(txdesc) GET_TX_DESC_SPE_RPT(txdesc)
+#define SET_TX_DESC_RAW_8822B(txdesc, value) SET_TX_DESC_RAW(txdesc, value)
+#define GET_TX_DESC_RAW_8822B(txdesc) GET_TX_DESC_RAW(txdesc)
+#define SET_TX_DESC_MOREFRAG_8822B(txdesc, value)                              \
+	SET_TX_DESC_MOREFRAG(txdesc, value)
+#define GET_TX_DESC_MOREFRAG_8822B(txdesc) GET_TX_DESC_MOREFRAG(txdesc)
+#define SET_TX_DESC_BK_8822B(txdesc, value) SET_TX_DESC_BK(txdesc, value)
+#define GET_TX_DESC_BK_8822B(txdesc) GET_TX_DESC_BK(txdesc)
+#define SET_TX_DESC_NULL_1_8822B(txdesc, value)                                \
+	SET_TX_DESC_NULL_1(txdesc, value)
+#define GET_TX_DESC_NULL_1_8822B(txdesc) GET_TX_DESC_NULL_1(txdesc)
+#define SET_TX_DESC_NULL_0_8822B(txdesc, value)                                \
+	SET_TX_DESC_NULL_0(txdesc, value)
+#define GET_TX_DESC_NULL_0_8822B(txdesc) GET_TX_DESC_NULL_0(txdesc)
+#define SET_TX_DESC_RDG_EN_8822B(txdesc, value)                                \
+	SET_TX_DESC_RDG_EN(txdesc, value)
+#define GET_TX_DESC_RDG_EN_8822B(txdesc) GET_TX_DESC_RDG_EN(txdesc)
+#define SET_TX_DESC_AGG_EN_8822B(txdesc, value)                                \
+	SET_TX_DESC_AGG_EN(txdesc, value)
+#define GET_TX_DESC_AGG_EN_8822B(txdesc) GET_TX_DESC_AGG_EN(txdesc)
+#define SET_TX_DESC_CCA_RTS_8822B(txdesc, value)                               \
+	SET_TX_DESC_CCA_RTS(txdesc, value)
+#define GET_TX_DESC_CCA_RTS_8822B(txdesc) GET_TX_DESC_CCA_RTS(txdesc)
+#define SET_TX_DESC_TRI_FRAME_8822B(txdesc, value)                             \
+	SET_TX_DESC_TRI_FRAME(txdesc, value)
+#define GET_TX_DESC_TRI_FRAME_8822B(txdesc) GET_TX_DESC_TRI_FRAME(txdesc)
+#define SET_TX_DESC_P_AID_8822B(txdesc, value) SET_TX_DESC_P_AID(txdesc, value)
+#define GET_TX_DESC_P_AID_8822B(txdesc) GET_TX_DESC_P_AID(txdesc)
+
+/*TXDESC_WORD3*/
+
+#define SET_TX_DESC_AMPDU_MAX_TIME_8822B(txdesc, value)                        \
+	SET_TX_DESC_AMPDU_MAX_TIME(txdesc, value)
+#define GET_TX_DESC_AMPDU_MAX_TIME_8822B(txdesc)                               \
+	GET_TX_DESC_AMPDU_MAX_TIME(txdesc)
+#define SET_TX_DESC_NDPA_8822B(txdesc, value) SET_TX_DESC_NDPA(txdesc, value)
+#define GET_TX_DESC_NDPA_8822B(txdesc) GET_TX_DESC_NDPA(txdesc)
+#define SET_TX_DESC_MAX_AGG_NUM_8822B(txdesc, value)                           \
+	SET_TX_DESC_MAX_AGG_NUM(txdesc, value)
+#define GET_TX_DESC_MAX_AGG_NUM_8822B(txdesc) GET_TX_DESC_MAX_AGG_NUM(txdesc)
+#define SET_TX_DESC_USE_MAX_TIME_EN_8822B(txdesc, value)                       \
+	SET_TX_DESC_USE_MAX_TIME_EN(txdesc, value)
+#define GET_TX_DESC_USE_MAX_TIME_EN_8822B(txdesc)                              \
+	GET_TX_DESC_USE_MAX_TIME_EN(txdesc)
+#define SET_TX_DESC_NAVUSEHDR_8822B(txdesc, value)                             \
+	SET_TX_DESC_NAVUSEHDR(txdesc, value)
+#define GET_TX_DESC_NAVUSEHDR_8822B(txdesc) GET_TX_DESC_NAVUSEHDR(txdesc)
+#define SET_TX_DESC_CHK_EN_8822B(txdesc, value)                                \
+	SET_TX_DESC_CHK_EN(txdesc, value)
+#define GET_TX_DESC_CHK_EN_8822B(txdesc) GET_TX_DESC_CHK_EN(txdesc)
+#define SET_TX_DESC_HW_RTS_EN_8822B(txdesc, value)                             \
+	SET_TX_DESC_HW_RTS_EN(txdesc, value)
+#define GET_TX_DESC_HW_RTS_EN_8822B(txdesc) GET_TX_DESC_HW_RTS_EN(txdesc)
+#define SET_TX_DESC_RTSEN_8822B(txdesc, value) SET_TX_DESC_RTSEN(txdesc, value)
+#define GET_TX_DESC_RTSEN_8822B(txdesc) GET_TX_DESC_RTSEN(txdesc)
+#define SET_TX_DESC_CTS2SELF_8822B(txdesc, value)                              \
+	SET_TX_DESC_CTS2SELF(txdesc, value)
+#define GET_TX_DESC_CTS2SELF_8822B(txdesc) GET_TX_DESC_CTS2SELF(txdesc)
+#define SET_TX_DESC_DISDATAFB_8822B(txdesc, value)                             \
+	SET_TX_DESC_DISDATAFB(txdesc, value)
+#define GET_TX_DESC_DISDATAFB_8822B(txdesc) GET_TX_DESC_DISDATAFB(txdesc)
+#define SET_TX_DESC_DISRTSFB_8822B(txdesc, value)                              \
+	SET_TX_DESC_DISRTSFB(txdesc, value)
+#define GET_TX_DESC_DISRTSFB_8822B(txdesc) GET_TX_DESC_DISRTSFB(txdesc)
+#define SET_TX_DESC_USE_RATE_8822B(txdesc, value)                              \
+	SET_TX_DESC_USE_RATE(txdesc, value)
+#define GET_TX_DESC_USE_RATE_8822B(txdesc) GET_TX_DESC_USE_RATE(txdesc)
+#define SET_TX_DESC_HW_SSN_SEL_8822B(txdesc, value)                            \
+	SET_TX_DESC_HW_SSN_SEL(txdesc, value)
+#define GET_TX_DESC_HW_SSN_SEL_8822B(txdesc) GET_TX_DESC_HW_SSN_SEL(txdesc)
+#define SET_TX_DESC_WHEADER_LEN_8822B(txdesc, value)                           \
+	SET_TX_DESC_WHEADER_LEN(txdesc, value)
+#define GET_TX_DESC_WHEADER_LEN_8822B(txdesc) GET_TX_DESC_WHEADER_LEN(txdesc)
+
+/*TXDESC_WORD4*/
+
+#define SET_TX_DESC_PCTS_MASK_IDX_8822B(txdesc, value)                         \
+	SET_TX_DESC_PCTS_MASK_IDX(txdesc, value)
+#define GET_TX_DESC_PCTS_MASK_IDX_8822B(txdesc)                                \
+	GET_TX_DESC_PCTS_MASK_IDX(txdesc)
+#define SET_TX_DESC_PCTS_EN_8822B(txdesc, value)                               \
+	SET_TX_DESC_PCTS_EN(txdesc, value)
+#define GET_TX_DESC_PCTS_EN_8822B(txdesc) GET_TX_DESC_PCTS_EN(txdesc)
+#define SET_TX_DESC_RTSRATE_8822B(txdesc, value)                               \
+	SET_TX_DESC_RTSRATE(txdesc, value)
+#define GET_TX_DESC_RTSRATE_8822B(txdesc) GET_TX_DESC_RTSRATE(txdesc)
+#define SET_TX_DESC_RTS_DATA_RTY_LMT_8822B(txdesc, value)                      \
+	SET_TX_DESC_RTS_DATA_RTY_LMT(txdesc, value)
+#define GET_TX_DESC_RTS_DATA_RTY_LMT_8822B(txdesc)                             \
+	GET_TX_DESC_RTS_DATA_RTY_LMT(txdesc)
+#define SET_TX_DESC_RTY_LMT_EN_8822B(txdesc, value)                            \
+	SET_TX_DESC_RTY_LMT_EN(txdesc, value)
+#define GET_TX_DESC_RTY_LMT_EN_8822B(txdesc) GET_TX_DESC_RTY_LMT_EN(txdesc)
+#define SET_TX_DESC_RTS_RTY_LOWEST_RATE_8822B(txdesc, value)                   \
+	SET_TX_DESC_RTS_RTY_LOWEST_RATE(txdesc, value)
+#define GET_TX_DESC_RTS_RTY_LOWEST_RATE_8822B(txdesc)                          \
+	GET_TX_DESC_RTS_RTY_LOWEST_RATE(txdesc)
+#define SET_TX_DESC_DATA_RTY_LOWEST_RATE_8822B(txdesc, value)                  \
+	SET_TX_DESC_DATA_RTY_LOWEST_RATE(txdesc, value)
+#define GET_TX_DESC_DATA_RTY_LOWEST_RATE_8822B(txdesc)                         \
+	GET_TX_DESC_DATA_RTY_LOWEST_RATE(txdesc)
+#define SET_TX_DESC_TRY_RATE_8822B(txdesc, value)                              \
+	SET_TX_DESC_TRY_RATE(txdesc, value)
+#define GET_TX_DESC_TRY_RATE_8822B(txdesc) GET_TX_DESC_TRY_RATE(txdesc)
+#define SET_TX_DESC_DATARATE_8822B(txdesc, value)                              \
+	SET_TX_DESC_DATARATE(txdesc, value)
+#define GET_TX_DESC_DATARATE_8822B(txdesc) GET_TX_DESC_DATARATE(txdesc)
+
+/*TXDESC_WORD5*/
+
+#define SET_TX_DESC_POLLUTED_8822B(txdesc, value)                              \
+	SET_TX_DESC_POLLUTED(txdesc, value)
+#define GET_TX_DESC_POLLUTED_8822B(txdesc) GET_TX_DESC_POLLUTED(txdesc)
+#define SET_TX_DESC_TXPWR_OFSET_8822B(txdesc, value)                           \
+	SET_TX_DESC_TXPWR_OFSET(txdesc, value)
+#define GET_TX_DESC_TXPWR_OFSET_8822B(txdesc) GET_TX_DESC_TXPWR_OFSET(txdesc)
+#define SET_TX_DESC_TX_ANT_8822B(txdesc, value)                                \
+	SET_TX_DESC_TX_ANT(txdesc, value)
+#define GET_TX_DESC_TX_ANT_8822B(txdesc) GET_TX_DESC_TX_ANT(txdesc)
+#define SET_TX_DESC_PORT_ID_8822B(txdesc, value)                               \
+	SET_TX_DESC_PORT_ID(txdesc, value)
+#define GET_TX_DESC_PORT_ID_8822B(txdesc) GET_TX_DESC_PORT_ID(txdesc)
+#define SET_TX_DESC_MULTIPLE_PORT_8822B(txdesc, value)                         \
+	SET_TX_DESC_MULTIPLE_PORT(txdesc, value)
+#define GET_TX_DESC_MULTIPLE_PORT_8822B(txdesc)                                \
+	GET_TX_DESC_MULTIPLE_PORT(txdesc)
+#define SET_TX_DESC_SIGNALING_TAPKT_EN_8822B(txdesc, value)                    \
+	SET_TX_DESC_SIGNALING_TAPKT_EN(txdesc, value)
+#define GET_TX_DESC_SIGNALING_TAPKT_EN_8822B(txdesc)                           \
+	GET_TX_DESC_SIGNALING_TAPKT_EN(txdesc)
+#define SET_TX_DESC_SIGNALING_TA_PKT_SC_8822B(txdesc, value)                   \
+	SET_TX_DESC_SIGNALING_TA_PKT_SC(txdesc, value)
+#define GET_TX_DESC_SIGNALING_TA_PKT_SC_8822B(txdesc)                          \
+	GET_TX_DESC_SIGNALING_TA_PKT_SC(txdesc)
+#define SET_TX_DESC_RTS_SHORT_8822B(txdesc, value)                             \
+	SET_TX_DESC_RTS_SHORT(txdesc, value)
+#define GET_TX_DESC_RTS_SHORT_8822B(txdesc) GET_TX_DESC_RTS_SHORT(txdesc)
+#define SET_TX_DESC_VCS_STBC_8822B(txdesc, value)                              \
+	SET_TX_DESC_VCS_STBC(txdesc, value)
+#define GET_TX_DESC_VCS_STBC_8822B(txdesc) GET_TX_DESC_VCS_STBC(txdesc)
+#define SET_TX_DESC_DATA_STBC_8822B(txdesc, value)                             \
+	SET_TX_DESC_DATA_STBC(txdesc, value)
+#define GET_TX_DESC_DATA_STBC_8822B(txdesc) GET_TX_DESC_DATA_STBC(txdesc)
+#define SET_TX_DESC_DATA_LDPC_8822B(txdesc, value)                             \
+	SET_TX_DESC_DATA_LDPC(txdesc, value)
+#define GET_TX_DESC_DATA_LDPC_8822B(txdesc) GET_TX_DESC_DATA_LDPC(txdesc)
+#define SET_TX_DESC_DATA_BW_8822B(txdesc, value)                               \
+	SET_TX_DESC_DATA_BW(txdesc, value)
+#define GET_TX_DESC_DATA_BW_8822B(txdesc) GET_TX_DESC_DATA_BW(txdesc)
+#define SET_TX_DESC_DATA_SHORT_8822B(txdesc, value)                            \
+	SET_TX_DESC_DATA_SHORT(txdesc, value)
+#define GET_TX_DESC_DATA_SHORT_8822B(txdesc) GET_TX_DESC_DATA_SHORT(txdesc)
+#define SET_TX_DESC_DATA_SC_8822B(txdesc, value)                               \
+	SET_TX_DESC_DATA_SC(txdesc, value)
+#define GET_TX_DESC_DATA_SC_8822B(txdesc) GET_TX_DESC_DATA_SC(txdesc)
+
+/*TXDESC_WORD6*/
+
+#define SET_TX_DESC_ANTSEL_D_8822B(txdesc, value)                              \
+	SET_TX_DESC_ANTSEL_D(txdesc, value)
+#define GET_TX_DESC_ANTSEL_D_8822B(txdesc) GET_TX_DESC_ANTSEL_D(txdesc)
+#define SET_TX_DESC_ANT_MAPD_8822B(txdesc, value)                              \
+	SET_TX_DESC_ANT_MAPD(txdesc, value)
+#define GET_TX_DESC_ANT_MAPD_8822B(txdesc) GET_TX_DESC_ANT_MAPD(txdesc)
+#define SET_TX_DESC_ANT_MAPC_8822B(txdesc, value)                              \
+	SET_TX_DESC_ANT_MAPC(txdesc, value)
+#define GET_TX_DESC_ANT_MAPC_8822B(txdesc) GET_TX_DESC_ANT_MAPC(txdesc)
+#define SET_TX_DESC_ANT_MAPB_8822B(txdesc, value)                              \
+	SET_TX_DESC_ANT_MAPB(txdesc, value)
+#define GET_TX_DESC_ANT_MAPB_8822B(txdesc) GET_TX_DESC_ANT_MAPB(txdesc)
+#define SET_TX_DESC_ANT_MAPA_8822B(txdesc, value)                              \
+	SET_TX_DESC_ANT_MAPA(txdesc, value)
+#define GET_TX_DESC_ANT_MAPA_8822B(txdesc) GET_TX_DESC_ANT_MAPA(txdesc)
+#define SET_TX_DESC_ANTSEL_C_8822B(txdesc, value)                              \
+	SET_TX_DESC_ANTSEL_C(txdesc, value)
+#define GET_TX_DESC_ANTSEL_C_8822B(txdesc) GET_TX_DESC_ANTSEL_C(txdesc)
+#define SET_TX_DESC_ANTSEL_B_8822B(txdesc, value)                              \
+	SET_TX_DESC_ANTSEL_B(txdesc, value)
+#define GET_TX_DESC_ANTSEL_B_8822B(txdesc) GET_TX_DESC_ANTSEL_B(txdesc)
+#define SET_TX_DESC_ANTSEL_A_8822B(txdesc, value)                              \
+	SET_TX_DESC_ANTSEL_A(txdesc, value)
+#define GET_TX_DESC_ANTSEL_A_8822B(txdesc) GET_TX_DESC_ANTSEL_A(txdesc)
+#define SET_TX_DESC_MBSSID_8822B(txdesc, value)                                \
+	SET_TX_DESC_MBSSID(txdesc, value)
+#define GET_TX_DESC_MBSSID_8822B(txdesc) GET_TX_DESC_MBSSID(txdesc)
+#define SET_TX_DESC_SW_DEFINE_8822B(txdesc, value)                             \
+	SET_TX_DESC_SW_DEFINE(txdesc, value)
+#define GET_TX_DESC_SW_DEFINE_8822B(txdesc) GET_TX_DESC_SW_DEFINE(txdesc)
+
+/*TXDESC_WORD7*/
+
+#define SET_TX_DESC_DMA_TXAGG_NUM_8822B(txdesc, value)                         \
+	SET_TX_DESC_DMA_TXAGG_NUM(txdesc, value)
+#define GET_TX_DESC_DMA_TXAGG_NUM_8822B(txdesc)                                \
+	GET_TX_DESC_DMA_TXAGG_NUM(txdesc)
+#define SET_TX_DESC_FINAL_DATA_RATE_8822B(txdesc, value)                       \
+	SET_TX_DESC_FINAL_DATA_RATE(txdesc, value)
+#define GET_TX_DESC_FINAL_DATA_RATE_8822B(txdesc)                              \
+	GET_TX_DESC_FINAL_DATA_RATE(txdesc)
+#define SET_TX_DESC_NTX_MAP_8822B(txdesc, value)                               \
+	SET_TX_DESC_NTX_MAP(txdesc, value)
+#define GET_TX_DESC_NTX_MAP_8822B(txdesc) GET_TX_DESC_NTX_MAP(txdesc)
+#define SET_TX_DESC_TX_BUFF_SIZE_8822B(txdesc, value)                          \
+	SET_TX_DESC_TX_BUFF_SIZE(txdesc, value)
+#define GET_TX_DESC_TX_BUFF_SIZE_8822B(txdesc) GET_TX_DESC_TX_BUFF_SIZE(txdesc)
+#define SET_TX_DESC_TXDESC_CHECKSUM_8822B(txdesc, value)                       \
+	SET_TX_DESC_TXDESC_CHECKSUM(txdesc, value)
+#define GET_TX_DESC_TXDESC_CHECKSUM_8822B(txdesc)                              \
+	GET_TX_DESC_TXDESC_CHECKSUM(txdesc)
+#define SET_TX_DESC_TIMESTAMP_8822B(txdesc, value)                             \
+	SET_TX_DESC_TIMESTAMP(txdesc, value)
+#define GET_TX_DESC_TIMESTAMP_8822B(txdesc) GET_TX_DESC_TIMESTAMP(txdesc)
+
+/*TXDESC_WORD8*/
+
+#define SET_TX_DESC_TXWIFI_CP_8822B(txdesc, value)                             \
+	SET_TX_DESC_TXWIFI_CP(txdesc, value)
+#define GET_TX_DESC_TXWIFI_CP_8822B(txdesc) GET_TX_DESC_TXWIFI_CP(txdesc)
+#define SET_TX_DESC_MAC_CP_8822B(txdesc, value)                                \
+	SET_TX_DESC_MAC_CP(txdesc, value)
+#define GET_TX_DESC_MAC_CP_8822B(txdesc) GET_TX_DESC_MAC_CP(txdesc)
+#define SET_TX_DESC_STW_PKTRE_DIS_8822B(txdesc, value)                         \
+	SET_TX_DESC_STW_PKTRE_DIS(txdesc, value)
+#define GET_TX_DESC_STW_PKTRE_DIS_8822B(txdesc)                                \
+	GET_TX_DESC_STW_PKTRE_DIS(txdesc)
+#define SET_TX_DESC_STW_RB_DIS_8822B(txdesc, value)                            \
+	SET_TX_DESC_STW_RB_DIS(txdesc, value)
+#define GET_TX_DESC_STW_RB_DIS_8822B(txdesc) GET_TX_DESC_STW_RB_DIS(txdesc)
+#define SET_TX_DESC_STW_RATE_DIS_8822B(txdesc, value)                          \
+	SET_TX_DESC_STW_RATE_DIS(txdesc, value)
+#define GET_TX_DESC_STW_RATE_DIS_8822B(txdesc) GET_TX_DESC_STW_RATE_DIS(txdesc)
+#define SET_TX_DESC_STW_ANT_DIS_8822B(txdesc, value)                           \
+	SET_TX_DESC_STW_ANT_DIS(txdesc, value)
+#define GET_TX_DESC_STW_ANT_DIS_8822B(txdesc) GET_TX_DESC_STW_ANT_DIS(txdesc)
+#define SET_TX_DESC_STW_EN_8822B(txdesc, value)                                \
+	SET_TX_DESC_STW_EN(txdesc, value)
+#define GET_TX_DESC_STW_EN_8822B(txdesc) GET_TX_DESC_STW_EN(txdesc)
+#define SET_TX_DESC_SMH_EN_8822B(txdesc, value)                                \
+	SET_TX_DESC_SMH_EN(txdesc, value)
+#define GET_TX_DESC_SMH_EN_8822B(txdesc) GET_TX_DESC_SMH_EN(txdesc)
+#define SET_TX_DESC_TAILPAGE_L_8822B(txdesc, value)                            \
+	SET_TX_DESC_TAILPAGE_L(txdesc, value)
+#define GET_TX_DESC_TAILPAGE_L_8822B(txdesc) GET_TX_DESC_TAILPAGE_L(txdesc)
+#define SET_TX_DESC_SDIO_DMASEQ_8822B(txdesc, value)                           \
+	SET_TX_DESC_SDIO_DMASEQ(txdesc, value)
+#define GET_TX_DESC_SDIO_DMASEQ_8822B(txdesc) GET_TX_DESC_SDIO_DMASEQ(txdesc)
+#define SET_TX_DESC_NEXTHEADPAGE_L_8822B(txdesc, value)                        \
+	SET_TX_DESC_NEXTHEADPAGE_L(txdesc, value)
+#define GET_TX_DESC_NEXTHEADPAGE_L_8822B(txdesc)                               \
+	GET_TX_DESC_NEXTHEADPAGE_L(txdesc)
+#define SET_TX_DESC_EN_HWSEQ_8822B(txdesc, value)                              \
+	SET_TX_DESC_EN_HWSEQ(txdesc, value)
+#define GET_TX_DESC_EN_HWSEQ_8822B(txdesc) GET_TX_DESC_EN_HWSEQ(txdesc)
+#define SET_TX_DESC_EN_HWEXSEQ_8822B(txdesc, value)                            \
+	SET_TX_DESC_EN_HWEXSEQ(txdesc, value)
+#define GET_TX_DESC_EN_HWEXSEQ_8822B(txdesc) GET_TX_DESC_EN_HWEXSEQ(txdesc)
+#define SET_TX_DESC_DATA_RC_8822B(txdesc, value)                               \
+	SET_TX_DESC_DATA_RC(txdesc, value)
+#define GET_TX_DESC_DATA_RC_8822B(txdesc) GET_TX_DESC_DATA_RC(txdesc)
+#define SET_TX_DESC_BAR_RTY_TH_8822B(txdesc, value)                            \
+	SET_TX_DESC_BAR_RTY_TH(txdesc, value)
+#define GET_TX_DESC_BAR_RTY_TH_8822B(txdesc) GET_TX_DESC_BAR_RTY_TH(txdesc)
+#define SET_TX_DESC_RTS_RC_8822B(txdesc, value)                                \
+	SET_TX_DESC_RTS_RC(txdesc, value)
+#define GET_TX_DESC_RTS_RC_8822B(txdesc) GET_TX_DESC_RTS_RC(txdesc)
+
+/*TXDESC_WORD9*/
+
+#define SET_TX_DESC_TAILPAGE_H_8822B(txdesc, value)                            \
+	SET_TX_DESC_TAILPAGE_H(txdesc, value)
+#define GET_TX_DESC_TAILPAGE_H_8822B(txdesc) GET_TX_DESC_TAILPAGE_H(txdesc)
+#define SET_TX_DESC_NEXTHEADPAGE_H_8822B(txdesc, value)                        \
+	SET_TX_DESC_NEXTHEADPAGE_H(txdesc, value)
+#define GET_TX_DESC_NEXTHEADPAGE_H_8822B(txdesc)                               \
+	GET_TX_DESC_NEXTHEADPAGE_H(txdesc)
+#define SET_TX_DESC_SW_SEQ_8822B(txdesc, value)                                \
+	SET_TX_DESC_SW_SEQ(txdesc, value)
+#define GET_TX_DESC_SW_SEQ_8822B(txdesc) GET_TX_DESC_SW_SEQ(txdesc)
+#define SET_TX_DESC_TXBF_PATH_8822B(txdesc, value)                             \
+	SET_TX_DESC_TXBF_PATH(txdesc, value)
+#define GET_TX_DESC_TXBF_PATH_8822B(txdesc) GET_TX_DESC_TXBF_PATH(txdesc)
+#define SET_TX_DESC_PADDING_LEN_8822B(txdesc, value)                           \
+	SET_TX_DESC_PADDING_LEN(txdesc, value)
+#define GET_TX_DESC_PADDING_LEN_8822B(txdesc) GET_TX_DESC_PADDING_LEN(txdesc)
+#define SET_TX_DESC_GROUP_BIT_IE_OFFSET_8822B(txdesc, value)                   \
+	SET_TX_DESC_GROUP_BIT_IE_OFFSET(txdesc, value)
+#define GET_TX_DESC_GROUP_BIT_IE_OFFSET_8822B(txdesc)                          \
+	GET_TX_DESC_GROUP_BIT_IE_OFFSET(txdesc)
+
+/*WORD10*/
+
+#define SET_TX_DESC_MU_DATARATE_8822B(txdesc, value)                           \
+	SET_TX_DESC_MU_DATARATE(txdesc, value)
+#define GET_TX_DESC_MU_DATARATE_8822B(txdesc) GET_TX_DESC_MU_DATARATE(txdesc)
+#define SET_TX_DESC_MU_RC_8822B(txdesc, value) SET_TX_DESC_MU_RC(txdesc, value)
+#define GET_TX_DESC_MU_RC_8822B(txdesc) GET_TX_DESC_MU_RC(txdesc)
+#define SET_TX_DESC_SND_PKT_SEL_8822B(txdesc, value)                           \
+	SET_TX_DESC_SND_PKT_SEL(txdesc, value)
+#define GET_TX_DESC_SND_PKT_SEL_8822B(txdesc) GET_TX_DESC_SND_PKT_SEL(txdesc)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT)
+
+/*TXDESC_WORD0*/
+
+#define SET_TX_DESC_DISQSELSEQ_8197F(txdesc, value)                            \
+	SET_TX_DESC_DISQSELSEQ(txdesc, value)
+#define GET_TX_DESC_DISQSELSEQ_8197F(txdesc) GET_TX_DESC_DISQSELSEQ(txdesc)
+#define SET_TX_DESC_GF_8197F(txdesc, value) SET_TX_DESC_GF(txdesc, value)
+#define GET_TX_DESC_GF_8197F(txdesc) GET_TX_DESC_GF(txdesc)
+#define SET_TX_DESC_NO_ACM_8197F(txdesc, value)                                \
+	SET_TX_DESC_NO_ACM(txdesc, value)
+#define GET_TX_DESC_NO_ACM_8197F(txdesc) GET_TX_DESC_NO_ACM(txdesc)
+#define SET_TX_DESC_BCNPKT_TSF_CTRL_8197F(txdesc, value)                       \
+	SET_TX_DESC_BCNPKT_TSF_CTRL(txdesc, value)
+#define GET_TX_DESC_BCNPKT_TSF_CTRL_8197F(txdesc)                              \
+	GET_TX_DESC_BCNPKT_TSF_CTRL(txdesc)
+#define SET_TX_DESC_AMSDU_PAD_EN_8197F(txdesc, value)                          \
+	SET_TX_DESC_AMSDU_PAD_EN(txdesc, value)
+#define GET_TX_DESC_AMSDU_PAD_EN_8197F(txdesc) GET_TX_DESC_AMSDU_PAD_EN(txdesc)
+#define SET_TX_DESC_LS_8197F(txdesc, value) SET_TX_DESC_LS(txdesc, value)
+#define GET_TX_DESC_LS_8197F(txdesc) GET_TX_DESC_LS(txdesc)
+#define SET_TX_DESC_HTC_8197F(txdesc, value) SET_TX_DESC_HTC(txdesc, value)
+#define GET_TX_DESC_HTC_8197F(txdesc) GET_TX_DESC_HTC(txdesc)
+#define SET_TX_DESC_BMC_8197F(txdesc, value) SET_TX_DESC_BMC(txdesc, value)
+#define GET_TX_DESC_BMC_8197F(txdesc) GET_TX_DESC_BMC(txdesc)
+#define SET_TX_DESC_OFFSET_8197F(txdesc, value)                                \
+	SET_TX_DESC_OFFSET(txdesc, value)
+#define GET_TX_DESC_OFFSET_8197F(txdesc) GET_TX_DESC_OFFSET(txdesc)
+#define SET_TX_DESC_TXPKTSIZE_8197F(txdesc, value)                             \
+	SET_TX_DESC_TXPKTSIZE(txdesc, value)
+#define GET_TX_DESC_TXPKTSIZE_8197F(txdesc) GET_TX_DESC_TXPKTSIZE(txdesc)
+
+/*WORD1*/
+
+#define SET_TX_DESC_MOREDATA_8197F(txdesc, value)                              \
+	SET_TX_DESC_MOREDATA(txdesc, value)
+#define GET_TX_DESC_MOREDATA_8197F(txdesc) GET_TX_DESC_MOREDATA(txdesc)
+#define SET_TX_DESC_PKT_OFFSET_8197F(txdesc, value)                            \
+	SET_TX_DESC_PKT_OFFSET(txdesc, value)
+#define GET_TX_DESC_PKT_OFFSET_8197F(txdesc) GET_TX_DESC_PKT_OFFSET(txdesc)
+#define SET_TX_DESC_SEC_TYPE_8197F(txdesc, value)                              \
+	SET_TX_DESC_SEC_TYPE(txdesc, value)
+#define GET_TX_DESC_SEC_TYPE_8197F(txdesc) GET_TX_DESC_SEC_TYPE(txdesc)
+#define SET_TX_DESC_EN_DESC_ID_8197F(txdesc, value)                            \
+	SET_TX_DESC_EN_DESC_ID(txdesc, value)
+#define GET_TX_DESC_EN_DESC_ID_8197F(txdesc) GET_TX_DESC_EN_DESC_ID(txdesc)
+#define SET_TX_DESC_RATE_ID_8197F(txdesc, value)                               \
+	SET_TX_DESC_RATE_ID(txdesc, value)
+#define GET_TX_DESC_RATE_ID_8197F(txdesc) GET_TX_DESC_RATE_ID(txdesc)
+#define SET_TX_DESC_PIFS_8197F(txdesc, value) SET_TX_DESC_PIFS(txdesc, value)
+#define GET_TX_DESC_PIFS_8197F(txdesc) GET_TX_DESC_PIFS(txdesc)
+#define SET_TX_DESC_LSIG_TXOP_EN_8197F(txdesc, value)                          \
+	SET_TX_DESC_LSIG_TXOP_EN(txdesc, value)
+#define GET_TX_DESC_LSIG_TXOP_EN_8197F(txdesc) GET_TX_DESC_LSIG_TXOP_EN(txdesc)
+#define SET_TX_DESC_RD_NAV_EXT_8197F(txdesc, value)                            \
+	SET_TX_DESC_RD_NAV_EXT(txdesc, value)
+#define GET_TX_DESC_RD_NAV_EXT_8197F(txdesc) GET_TX_DESC_RD_NAV_EXT(txdesc)
+#define SET_TX_DESC_QSEL_8197F(txdesc, value) SET_TX_DESC_QSEL(txdesc, value)
+#define GET_TX_DESC_QSEL_8197F(txdesc) GET_TX_DESC_QSEL(txdesc)
+#define SET_TX_DESC_MACID_8197F(txdesc, value) SET_TX_DESC_MACID(txdesc, value)
+#define GET_TX_DESC_MACID_8197F(txdesc) GET_TX_DESC_MACID(txdesc)
+
+/*TXDESC_WORD2*/
+
+#define SET_TX_DESC_HW_AES_IV_8197F(txdesc, value)                             \
+	SET_TX_DESC_HW_AES_IV(txdesc, value)
+#define GET_TX_DESC_HW_AES_IV_8197F(txdesc) GET_TX_DESC_HW_AES_IV(txdesc)
+#define SET_TX_DESC_FTM_EN_8197F(txdesc, value)                                \
+	SET_TX_DESC_FTM_EN(txdesc, value)
+#define GET_TX_DESC_FTM_EN_8197F(txdesc) GET_TX_DESC_FTM_EN(txdesc)
+#define SET_TX_DESC_G_ID_8197F(txdesc, value) SET_TX_DESC_G_ID(txdesc, value)
+#define GET_TX_DESC_G_ID_8197F(txdesc) GET_TX_DESC_G_ID(txdesc)
+#define SET_TX_DESC_BT_NULL_8197F(txdesc, value)                               \
+	SET_TX_DESC_BT_NULL(txdesc, value)
+#define GET_TX_DESC_BT_NULL_8197F(txdesc) GET_TX_DESC_BT_NULL(txdesc)
+#define SET_TX_DESC_AMPDU_DENSITY_8197F(txdesc, value)                         \
+	SET_TX_DESC_AMPDU_DENSITY(txdesc, value)
+#define GET_TX_DESC_AMPDU_DENSITY_8197F(txdesc)                                \
+	GET_TX_DESC_AMPDU_DENSITY(txdesc)
+#define SET_TX_DESC_SPE_RPT_8197F(txdesc, value)                               \
+	SET_TX_DESC_SPE_RPT(txdesc, value)
+#define GET_TX_DESC_SPE_RPT_8197F(txdesc) GET_TX_DESC_SPE_RPT(txdesc)
+#define SET_TX_DESC_RAW_8197F(txdesc, value) SET_TX_DESC_RAW(txdesc, value)
+#define GET_TX_DESC_RAW_8197F(txdesc) GET_TX_DESC_RAW(txdesc)
+#define SET_TX_DESC_MOREFRAG_8197F(txdesc, value)                              \
+	SET_TX_DESC_MOREFRAG(txdesc, value)
+#define GET_TX_DESC_MOREFRAG_8197F(txdesc) GET_TX_DESC_MOREFRAG(txdesc)
+#define SET_TX_DESC_BK_8197F(txdesc, value) SET_TX_DESC_BK(txdesc, value)
+#define GET_TX_DESC_BK_8197F(txdesc) GET_TX_DESC_BK(txdesc)
+#define SET_TX_DESC_NULL_1_8197F(txdesc, value)                                \
+	SET_TX_DESC_NULL_1(txdesc, value)
+#define GET_TX_DESC_NULL_1_8197F(txdesc) GET_TX_DESC_NULL_1(txdesc)
+#define SET_TX_DESC_NULL_0_8197F(txdesc, value)                                \
+	SET_TX_DESC_NULL_0(txdesc, value)
+#define GET_TX_DESC_NULL_0_8197F(txdesc) GET_TX_DESC_NULL_0(txdesc)
+#define SET_TX_DESC_RDG_EN_8197F(txdesc, value)                                \
+	SET_TX_DESC_RDG_EN(txdesc, value)
+#define GET_TX_DESC_RDG_EN_8197F(txdesc) GET_TX_DESC_RDG_EN(txdesc)
+#define SET_TX_DESC_AGG_EN_8197F(txdesc, value)                                \
+	SET_TX_DESC_AGG_EN(txdesc, value)
+#define GET_TX_DESC_AGG_EN_8197F(txdesc) GET_TX_DESC_AGG_EN(txdesc)
+#define SET_TX_DESC_CCA_RTS_8197F(txdesc, value)                               \
+	SET_TX_DESC_CCA_RTS(txdesc, value)
+#define GET_TX_DESC_CCA_RTS_8197F(txdesc) GET_TX_DESC_CCA_RTS(txdesc)
+#define SET_TX_DESC_TRI_FRAME_8197F(txdesc, value)                             \
+	SET_TX_DESC_TRI_FRAME(txdesc, value)
+#define GET_TX_DESC_TRI_FRAME_8197F(txdesc) GET_TX_DESC_TRI_FRAME(txdesc)
+#define SET_TX_DESC_P_AID_8197F(txdesc, value) SET_TX_DESC_P_AID(txdesc, value)
+#define GET_TX_DESC_P_AID_8197F(txdesc) GET_TX_DESC_P_AID(txdesc)
+
+/*TXDESC_WORD3*/
+
+#define SET_TX_DESC_AMPDU_MAX_TIME_8197F(txdesc, value)                        \
+	SET_TX_DESC_AMPDU_MAX_TIME(txdesc, value)
+#define GET_TX_DESC_AMPDU_MAX_TIME_8197F(txdesc)                               \
+	GET_TX_DESC_AMPDU_MAX_TIME(txdesc)
+#define SET_TX_DESC_NDPA_8197F(txdesc, value) SET_TX_DESC_NDPA(txdesc, value)
+#define GET_TX_DESC_NDPA_8197F(txdesc) GET_TX_DESC_NDPA(txdesc)
+#define SET_TX_DESC_MAX_AGG_NUM_8197F(txdesc, value)                           \
+	SET_TX_DESC_MAX_AGG_NUM(txdesc, value)
+#define GET_TX_DESC_MAX_AGG_NUM_8197F(txdesc) GET_TX_DESC_MAX_AGG_NUM(txdesc)
+#define SET_TX_DESC_USE_MAX_TIME_EN_8197F(txdesc, value)                       \
+	SET_TX_DESC_USE_MAX_TIME_EN(txdesc, value)
+#define GET_TX_DESC_USE_MAX_TIME_EN_8197F(txdesc)                              \
+	GET_TX_DESC_USE_MAX_TIME_EN(txdesc)
+#define SET_TX_DESC_NAVUSEHDR_8197F(txdesc, value)                             \
+	SET_TX_DESC_NAVUSEHDR(txdesc, value)
+#define GET_TX_DESC_NAVUSEHDR_8197F(txdesc) GET_TX_DESC_NAVUSEHDR(txdesc)
+#define SET_TX_DESC_CHK_EN_8197F(txdesc, value)                                \
+	SET_TX_DESC_CHK_EN(txdesc, value)
+#define GET_TX_DESC_CHK_EN_8197F(txdesc) GET_TX_DESC_CHK_EN(txdesc)
+#define SET_TX_DESC_HW_RTS_EN_8197F(txdesc, value)                             \
+	SET_TX_DESC_HW_RTS_EN(txdesc, value)
+#define GET_TX_DESC_HW_RTS_EN_8197F(txdesc) GET_TX_DESC_HW_RTS_EN(txdesc)
+#define SET_TX_DESC_RTSEN_8197F(txdesc, value) SET_TX_DESC_RTSEN(txdesc, value)
+#define GET_TX_DESC_RTSEN_8197F(txdesc) GET_TX_DESC_RTSEN(txdesc)
+#define SET_TX_DESC_CTS2SELF_8197F(txdesc, value)                              \
+	SET_TX_DESC_CTS2SELF(txdesc, value)
+#define GET_TX_DESC_CTS2SELF_8197F(txdesc) GET_TX_DESC_CTS2SELF(txdesc)
+#define SET_TX_DESC_DISDATAFB_8197F(txdesc, value)                             \
+	SET_TX_DESC_DISDATAFB(txdesc, value)
+#define GET_TX_DESC_DISDATAFB_8197F(txdesc) GET_TX_DESC_DISDATAFB(txdesc)
+#define SET_TX_DESC_DISRTSFB_8197F(txdesc, value)                              \
+	SET_TX_DESC_DISRTSFB(txdesc, value)
+#define GET_TX_DESC_DISRTSFB_8197F(txdesc) GET_TX_DESC_DISRTSFB(txdesc)
+#define SET_TX_DESC_USE_RATE_8197F(txdesc, value)                              \
+	SET_TX_DESC_USE_RATE(txdesc, value)
+#define GET_TX_DESC_USE_RATE_8197F(txdesc) GET_TX_DESC_USE_RATE(txdesc)
+#define SET_TX_DESC_HW_SSN_SEL_8197F(txdesc, value)                            \
+	SET_TX_DESC_HW_SSN_SEL(txdesc, value)
+#define GET_TX_DESC_HW_SSN_SEL_8197F(txdesc) GET_TX_DESC_HW_SSN_SEL(txdesc)
+#define SET_TX_DESC_WHEADER_LEN_8197F(txdesc, value)                           \
+	SET_TX_DESC_WHEADER_LEN(txdesc, value)
+#define GET_TX_DESC_WHEADER_LEN_8197F(txdesc) GET_TX_DESC_WHEADER_LEN(txdesc)
+
+/*TXDESC_WORD4*/
+
+#define SET_TX_DESC_PCTS_MASK_IDX_8197F(txdesc, value)                         \
+	SET_TX_DESC_PCTS_MASK_IDX(txdesc, value)
+#define GET_TX_DESC_PCTS_MASK_IDX_8197F(txdesc)                                \
+	GET_TX_DESC_PCTS_MASK_IDX(txdesc)
+#define SET_TX_DESC_PCTS_EN_8197F(txdesc, value)                               \
+	SET_TX_DESC_PCTS_EN(txdesc, value)
+#define GET_TX_DESC_PCTS_EN_8197F(txdesc) GET_TX_DESC_PCTS_EN(txdesc)
+#define SET_TX_DESC_RTSRATE_8197F(txdesc, value)                               \
+	SET_TX_DESC_RTSRATE(txdesc, value)
+#define GET_TX_DESC_RTSRATE_8197F(txdesc) GET_TX_DESC_RTSRATE(txdesc)
+#define SET_TX_DESC_RTS_DATA_RTY_LMT_8197F(txdesc, value)                      \
+	SET_TX_DESC_RTS_DATA_RTY_LMT(txdesc, value)
+#define GET_TX_DESC_RTS_DATA_RTY_LMT_8197F(txdesc)                             \
+	GET_TX_DESC_RTS_DATA_RTY_LMT(txdesc)
+#define SET_TX_DESC_RTY_LMT_EN_8197F(txdesc, value)                            \
+	SET_TX_DESC_RTY_LMT_EN(txdesc, value)
+#define GET_TX_DESC_RTY_LMT_EN_8197F(txdesc) GET_TX_DESC_RTY_LMT_EN(txdesc)
+#define SET_TX_DESC_RTS_RTY_LOWEST_RATE_8197F(txdesc, value)                   \
+	SET_TX_DESC_RTS_RTY_LOWEST_RATE(txdesc, value)
+#define GET_TX_DESC_RTS_RTY_LOWEST_RATE_8197F(txdesc)                          \
+	GET_TX_DESC_RTS_RTY_LOWEST_RATE(txdesc)
+#define SET_TX_DESC_DATA_RTY_LOWEST_RATE_8197F(txdesc, value)                  \
+	SET_TX_DESC_DATA_RTY_LOWEST_RATE(txdesc, value)
+#define GET_TX_DESC_DATA_RTY_LOWEST_RATE_8197F(txdesc)                         \
+	GET_TX_DESC_DATA_RTY_LOWEST_RATE(txdesc)
+#define SET_TX_DESC_TRY_RATE_8197F(txdesc, value)                              \
+	SET_TX_DESC_TRY_RATE(txdesc, value)
+#define GET_TX_DESC_TRY_RATE_8197F(txdesc) GET_TX_DESC_TRY_RATE(txdesc)
+#define SET_TX_DESC_DATARATE_8197F(txdesc, value)                              \
+	SET_TX_DESC_DATARATE(txdesc, value)
+#define GET_TX_DESC_DATARATE_8197F(txdesc) GET_TX_DESC_DATARATE(txdesc)
+
+/*TXDESC_WORD5*/
+
+#define SET_TX_DESC_POLLUTED_8197F(txdesc, value)                              \
+	SET_TX_DESC_POLLUTED(txdesc, value)
+#define GET_TX_DESC_POLLUTED_8197F(txdesc) GET_TX_DESC_POLLUTED(txdesc)
+#define SET_TX_DESC_TXPWR_OFSET_8197F(txdesc, value)                           \
+	SET_TX_DESC_TXPWR_OFSET(txdesc, value)
+#define GET_TX_DESC_TXPWR_OFSET_8197F(txdesc) GET_TX_DESC_TXPWR_OFSET(txdesc)
+#define SET_TX_DESC_TX_ANT_8197F(txdesc, value)                                \
+	SET_TX_DESC_TX_ANT(txdesc, value)
+#define GET_TX_DESC_TX_ANT_8197F(txdesc) GET_TX_DESC_TX_ANT(txdesc)
+#define SET_TX_DESC_PORT_ID_8197F(txdesc, value)                               \
+	SET_TX_DESC_PORT_ID(txdesc, value)
+#define GET_TX_DESC_PORT_ID_8197F(txdesc) GET_TX_DESC_PORT_ID(txdesc)
+#define SET_TX_DESC_MULTIPLE_PORT_8197F(txdesc, value)                         \
+	SET_TX_DESC_MULTIPLE_PORT(txdesc, value)
+#define GET_TX_DESC_MULTIPLE_PORT_8197F(txdesc)                                \
+	GET_TX_DESC_MULTIPLE_PORT(txdesc)
+#define SET_TX_DESC_SIGNALING_TAPKT_EN_8197F(txdesc, value)                    \
+	SET_TX_DESC_SIGNALING_TAPKT_EN(txdesc, value)
+#define GET_TX_DESC_SIGNALING_TAPKT_EN_8197F(txdesc)                           \
+	GET_TX_DESC_SIGNALING_TAPKT_EN(txdesc)
+#define SET_TX_DESC_RTS_SC_8197F(txdesc, value)                                \
+	SET_TX_DESC_RTS_SC(txdesc, value)
+#define GET_TX_DESC_RTS_SC_8197F(txdesc) GET_TX_DESC_RTS_SC(txdesc)
+#define SET_TX_DESC_RTS_SHORT_8197F(txdesc, value)                             \
+	SET_TX_DESC_RTS_SHORT(txdesc, value)
+#define GET_TX_DESC_RTS_SHORT_8197F(txdesc) GET_TX_DESC_RTS_SHORT(txdesc)
+#define SET_TX_DESC_VCS_STBC_8197F(txdesc, value)                              \
+	SET_TX_DESC_VCS_STBC(txdesc, value)
+#define GET_TX_DESC_VCS_STBC_8197F(txdesc) GET_TX_DESC_VCS_STBC(txdesc)
+#define SET_TX_DESC_DATA_STBC_8197F(txdesc, value)                             \
+	SET_TX_DESC_DATA_STBC(txdesc, value)
+#define GET_TX_DESC_DATA_STBC_8197F(txdesc) GET_TX_DESC_DATA_STBC(txdesc)
+#define SET_TX_DESC_DATA_LDPC_8197F(txdesc, value)                             \
+	SET_TX_DESC_DATA_LDPC(txdesc, value)
+#define GET_TX_DESC_DATA_LDPC_8197F(txdesc) GET_TX_DESC_DATA_LDPC(txdesc)
+#define SET_TX_DESC_DATA_BW_8197F(txdesc, value)                               \
+	SET_TX_DESC_DATA_BW(txdesc, value)
+#define GET_TX_DESC_DATA_BW_8197F(txdesc) GET_TX_DESC_DATA_BW(txdesc)
+#define SET_TX_DESC_DATA_SHORT_8197F(txdesc, value)                            \
+	SET_TX_DESC_DATA_SHORT(txdesc, value)
+#define GET_TX_DESC_DATA_SHORT_8197F(txdesc) GET_TX_DESC_DATA_SHORT(txdesc)
+#define SET_TX_DESC_DATA_SC_8197F(txdesc, value)                               \
+	SET_TX_DESC_DATA_SC(txdesc, value)
+#define GET_TX_DESC_DATA_SC_8197F(txdesc) GET_TX_DESC_DATA_SC(txdesc)
+
+/*TXDESC_WORD6*/
+
+#define SET_TX_DESC_ANTSEL_D_8197F(txdesc, value)                              \
+	SET_TX_DESC_ANTSEL_D(txdesc, value)
+#define GET_TX_DESC_ANTSEL_D_8197F(txdesc) GET_TX_DESC_ANTSEL_D(txdesc)
+#define SET_TX_DESC_ANT_MAPD_8197F(txdesc, value)                              \
+	SET_TX_DESC_ANT_MAPD(txdesc, value)
+#define GET_TX_DESC_ANT_MAPD_8197F(txdesc) GET_TX_DESC_ANT_MAPD(txdesc)
+#define SET_TX_DESC_ANT_MAPC_8197F(txdesc, value)                              \
+	SET_TX_DESC_ANT_MAPC(txdesc, value)
+#define GET_TX_DESC_ANT_MAPC_8197F(txdesc) GET_TX_DESC_ANT_MAPC(txdesc)
+#define SET_TX_DESC_ANT_MAPB_8197F(txdesc, value)                              \
+	SET_TX_DESC_ANT_MAPB(txdesc, value)
+#define GET_TX_DESC_ANT_MAPB_8197F(txdesc) GET_TX_DESC_ANT_MAPB(txdesc)
+#define SET_TX_DESC_ANT_MAPA_8197F(txdesc, value)                              \
+	SET_TX_DESC_ANT_MAPA(txdesc, value)
+#define GET_TX_DESC_ANT_MAPA_8197F(txdesc) GET_TX_DESC_ANT_MAPA(txdesc)
+#define SET_TX_DESC_ANTSEL_C_8197F(txdesc, value)                              \
+	SET_TX_DESC_ANTSEL_C(txdesc, value)
+#define GET_TX_DESC_ANTSEL_C_8197F(txdesc) GET_TX_DESC_ANTSEL_C(txdesc)
+#define SET_TX_DESC_ANTSEL_B_8197F(txdesc, value)                              \
+	SET_TX_DESC_ANTSEL_B(txdesc, value)
+#define GET_TX_DESC_ANTSEL_B_8197F(txdesc) GET_TX_DESC_ANTSEL_B(txdesc)
+#define SET_TX_DESC_ANTSEL_A_8197F(txdesc, value)                              \
+	SET_TX_DESC_ANTSEL_A(txdesc, value)
+#define GET_TX_DESC_ANTSEL_A_8197F(txdesc) GET_TX_DESC_ANTSEL_A(txdesc)
+#define SET_TX_DESC_MBSSID_8197F(txdesc, value)                                \
+	SET_TX_DESC_MBSSID(txdesc, value)
+#define GET_TX_DESC_MBSSID_8197F(txdesc) GET_TX_DESC_MBSSID(txdesc)
+#define SET_TX_DESC_SW_DEFINE_8197F(txdesc, value)                             \
+	SET_TX_DESC_SW_DEFINE(txdesc, value)
+#define GET_TX_DESC_SW_DEFINE_8197F(txdesc) GET_TX_DESC_SW_DEFINE(txdesc)
+
+/*TXDESC_WORD7*/
+
+#define SET_TX_DESC_DMA_TXAGG_NUM_8197F(txdesc, value)                         \
+	SET_TX_DESC_DMA_TXAGG_NUM(txdesc, value)
+#define GET_TX_DESC_DMA_TXAGG_NUM_8197F(txdesc)                                \
+	GET_TX_DESC_DMA_TXAGG_NUM(txdesc)
+#define SET_TX_DESC_FINAL_DATA_RATE_8197F(txdesc, value)                       \
+	SET_TX_DESC_FINAL_DATA_RATE(txdesc, value)
+#define GET_TX_DESC_FINAL_DATA_RATE_8197F(txdesc)                              \
+	GET_TX_DESC_FINAL_DATA_RATE(txdesc)
+#define SET_TX_DESC_NTX_MAP_8197F(txdesc, value)                               \
+	SET_TX_DESC_NTX_MAP(txdesc, value)
+#define GET_TX_DESC_NTX_MAP_8197F(txdesc) GET_TX_DESC_NTX_MAP(txdesc)
+#define SET_TX_DESC_TX_BUFF_SIZE_8197F(txdesc, value)                          \
+	SET_TX_DESC_TX_BUFF_SIZE(txdesc, value)
+#define GET_TX_DESC_TX_BUFF_SIZE_8197F(txdesc) GET_TX_DESC_TX_BUFF_SIZE(txdesc)
+#define SET_TX_DESC_TXDESC_CHECKSUM_8197F(txdesc, value)                       \
+	SET_TX_DESC_TXDESC_CHECKSUM(txdesc, value)
+#define GET_TX_DESC_TXDESC_CHECKSUM_8197F(txdesc)                              \
+	GET_TX_DESC_TXDESC_CHECKSUM(txdesc)
+#define SET_TX_DESC_TIMESTAMP_8197F(txdesc, value)                             \
+	SET_TX_DESC_TIMESTAMP(txdesc, value)
+#define GET_TX_DESC_TIMESTAMP_8197F(txdesc) GET_TX_DESC_TIMESTAMP(txdesc)
+
+/*TXDESC_WORD8*/
+
+#define SET_TX_DESC_TXWIFI_CP_8197F(txdesc, value)                             \
+	SET_TX_DESC_TXWIFI_CP(txdesc, value)
+#define GET_TX_DESC_TXWIFI_CP_8197F(txdesc) GET_TX_DESC_TXWIFI_CP(txdesc)
+#define SET_TX_DESC_MAC_CP_8197F(txdesc, value)                                \
+	SET_TX_DESC_MAC_CP(txdesc, value)
+#define GET_TX_DESC_MAC_CP_8197F(txdesc) GET_TX_DESC_MAC_CP(txdesc)
+#define SET_TX_DESC_STW_PKTRE_DIS_8197F(txdesc, value)                         \
+	SET_TX_DESC_STW_PKTRE_DIS(txdesc, value)
+#define GET_TX_DESC_STW_PKTRE_DIS_8197F(txdesc)                                \
+	GET_TX_DESC_STW_PKTRE_DIS(txdesc)
+#define SET_TX_DESC_STW_RB_DIS_8197F(txdesc, value)                            \
+	SET_TX_DESC_STW_RB_DIS(txdesc, value)
+#define GET_TX_DESC_STW_RB_DIS_8197F(txdesc) GET_TX_DESC_STW_RB_DIS(txdesc)
+#define SET_TX_DESC_STW_RATE_DIS_8197F(txdesc, value)                          \
+	SET_TX_DESC_STW_RATE_DIS(txdesc, value)
+#define GET_TX_DESC_STW_RATE_DIS_8197F(txdesc) GET_TX_DESC_STW_RATE_DIS(txdesc)
+#define SET_TX_DESC_STW_ANT_DIS_8197F(txdesc, value)                           \
+	SET_TX_DESC_STW_ANT_DIS(txdesc, value)
+#define GET_TX_DESC_STW_ANT_DIS_8197F(txdesc) GET_TX_DESC_STW_ANT_DIS(txdesc)
+#define SET_TX_DESC_STW_EN_8197F(txdesc, value)                                \
+	SET_TX_DESC_STW_EN(txdesc, value)
+#define GET_TX_DESC_STW_EN_8197F(txdesc) GET_TX_DESC_STW_EN(txdesc)
+#define SET_TX_DESC_SMH_EN_8197F(txdesc, value)                                \
+	SET_TX_DESC_SMH_EN(txdesc, value)
+#define GET_TX_DESC_SMH_EN_8197F(txdesc) GET_TX_DESC_SMH_EN(txdesc)
+#define SET_TX_DESC_TAILPAGE_L_8197F(txdesc, value)                            \
+	SET_TX_DESC_TAILPAGE_L(txdesc, value)
+#define GET_TX_DESC_TAILPAGE_L_8197F(txdesc) GET_TX_DESC_TAILPAGE_L(txdesc)
+#define SET_TX_DESC_SDIO_DMASEQ_8197F(txdesc, value)                           \
+	SET_TX_DESC_SDIO_DMASEQ(txdesc, value)
+#define GET_TX_DESC_SDIO_DMASEQ_8197F(txdesc) GET_TX_DESC_SDIO_DMASEQ(txdesc)
+#define SET_TX_DESC_NEXTHEADPAGE_L_8197F(txdesc, value)                        \
+	SET_TX_DESC_NEXTHEADPAGE_L(txdesc, value)
+#define GET_TX_DESC_NEXTHEADPAGE_L_8197F(txdesc)                               \
+	GET_TX_DESC_NEXTHEADPAGE_L(txdesc)
+#define SET_TX_DESC_EN_HWSEQ_8197F(txdesc, value)                              \
+	SET_TX_DESC_EN_HWSEQ(txdesc, value)
+#define GET_TX_DESC_EN_HWSEQ_8197F(txdesc) GET_TX_DESC_EN_HWSEQ(txdesc)
+#define SET_TX_DESC_EN_HWEXSEQ_8197F(txdesc, value)                            \
+	SET_TX_DESC_EN_HWEXSEQ(txdesc, value)
+#define GET_TX_DESC_EN_HWEXSEQ_8197F(txdesc) GET_TX_DESC_EN_HWEXSEQ(txdesc)
+#define SET_TX_DESC_DATA_RC_8197F(txdesc, value)                               \
+	SET_TX_DESC_DATA_RC(txdesc, value)
+#define GET_TX_DESC_DATA_RC_8197F(txdesc) GET_TX_DESC_DATA_RC(txdesc)
+#define SET_TX_DESC_BAR_RTY_TH_8197F(txdesc, value)                            \
+	SET_TX_DESC_BAR_RTY_TH(txdesc, value)
+#define GET_TX_DESC_BAR_RTY_TH_8197F(txdesc) GET_TX_DESC_BAR_RTY_TH(txdesc)
+#define SET_TX_DESC_RTS_RC_8197F(txdesc, value)                                \
+	SET_TX_DESC_RTS_RC(txdesc, value)
+#define GET_TX_DESC_RTS_RC_8197F(txdesc) GET_TX_DESC_RTS_RC(txdesc)
+
+/*TXDESC_WORD9*/
+
+#define SET_TX_DESC_TAILPAGE_H_8197F(txdesc, value)                            \
+	SET_TX_DESC_TAILPAGE_H(txdesc, value)
+#define GET_TX_DESC_TAILPAGE_H_8197F(txdesc) GET_TX_DESC_TAILPAGE_H(txdesc)
+#define SET_TX_DESC_NEXTHEADPAGE_H_8197F(txdesc, value)                        \
+	SET_TX_DESC_NEXTHEADPAGE_H(txdesc, value)
+#define GET_TX_DESC_NEXTHEADPAGE_H_8197F(txdesc)                               \
+	GET_TX_DESC_NEXTHEADPAGE_H(txdesc)
+#define SET_TX_DESC_SW_SEQ_8197F(txdesc, value)                                \
+	SET_TX_DESC_SW_SEQ(txdesc, value)
+#define GET_TX_DESC_SW_SEQ_8197F(txdesc) GET_TX_DESC_SW_SEQ(txdesc)
+#define SET_TX_DESC_TXBF_PATH_8197F(txdesc, value)                             \
+	SET_TX_DESC_TXBF_PATH(txdesc, value)
+#define GET_TX_DESC_TXBF_PATH_8197F(txdesc) GET_TX_DESC_TXBF_PATH(txdesc)
+#define SET_TX_DESC_PADDING_LEN_8197F(txdesc, value)                           \
+	SET_TX_DESC_PADDING_LEN(txdesc, value)
+#define GET_TX_DESC_PADDING_LEN_8197F(txdesc) GET_TX_DESC_PADDING_LEN(txdesc)
+#define SET_TX_DESC_GROUP_BIT_IE_OFFSET_8197F(txdesc, value)                   \
+	SET_TX_DESC_GROUP_BIT_IE_OFFSET(txdesc, value)
+#define GET_TX_DESC_GROUP_BIT_IE_OFFSET_8197F(txdesc)                          \
+	GET_TX_DESC_GROUP_BIT_IE_OFFSET(txdesc)
+
+/*WORD10*/
+
+#endif
+
+#if (HALMAC_8821C_SUPPORT)
+
+/*TXDESC_WORD0*/
+
+#define SET_TX_DESC_DISQSELSEQ_8821C(txdesc, value)                            \
+	SET_TX_DESC_DISQSELSEQ(txdesc, value)
+#define GET_TX_DESC_DISQSELSEQ_8821C(txdesc) GET_TX_DESC_DISQSELSEQ(txdesc)
+#define SET_TX_DESC_GF_8821C(txdesc, value) SET_TX_DESC_GF(txdesc, value)
+#define GET_TX_DESC_GF_8821C(txdesc) GET_TX_DESC_GF(txdesc)
+#define SET_TX_DESC_NO_ACM_8821C(txdesc, value)                                \
+	SET_TX_DESC_NO_ACM(txdesc, value)
+#define GET_TX_DESC_NO_ACM_8821C(txdesc) GET_TX_DESC_NO_ACM(txdesc)
+#define SET_TX_DESC_BCNPKT_TSF_CTRL_8821C(txdesc, value)                       \
+	SET_TX_DESC_BCNPKT_TSF_CTRL(txdesc, value)
+#define GET_TX_DESC_BCNPKT_TSF_CTRL_8821C(txdesc)                              \
+	GET_TX_DESC_BCNPKT_TSF_CTRL(txdesc)
+#define SET_TX_DESC_AMSDU_PAD_EN_8821C(txdesc, value)                          \
+	SET_TX_DESC_AMSDU_PAD_EN(txdesc, value)
+#define GET_TX_DESC_AMSDU_PAD_EN_8821C(txdesc) GET_TX_DESC_AMSDU_PAD_EN(txdesc)
+#define SET_TX_DESC_LS_8821C(txdesc, value) SET_TX_DESC_LS(txdesc, value)
+#define GET_TX_DESC_LS_8821C(txdesc) GET_TX_DESC_LS(txdesc)
+#define SET_TX_DESC_HTC_8821C(txdesc, value) SET_TX_DESC_HTC(txdesc, value)
+#define GET_TX_DESC_HTC_8821C(txdesc) GET_TX_DESC_HTC(txdesc)
+#define SET_TX_DESC_BMC_8821C(txdesc, value) SET_TX_DESC_BMC(txdesc, value)
+#define GET_TX_DESC_BMC_8821C(txdesc) GET_TX_DESC_BMC(txdesc)
+#define SET_TX_DESC_OFFSET_8821C(txdesc, value)                                \
+	SET_TX_DESC_OFFSET(txdesc, value)
+#define GET_TX_DESC_OFFSET_8821C(txdesc) GET_TX_DESC_OFFSET(txdesc)
+#define SET_TX_DESC_TXPKTSIZE_8821C(txdesc, value)                             \
+	SET_TX_DESC_TXPKTSIZE(txdesc, value)
+#define GET_TX_DESC_TXPKTSIZE_8821C(txdesc) GET_TX_DESC_TXPKTSIZE(txdesc)
+
+/*WORD1*/
+
+#define SET_TX_DESC_MOREDATA_8821C(txdesc, value)                              \
+	SET_TX_DESC_MOREDATA(txdesc, value)
+#define GET_TX_DESC_MOREDATA_8821C(txdesc) GET_TX_DESC_MOREDATA(txdesc)
+#define SET_TX_DESC_PKT_OFFSET_8821C(txdesc, value)                            \
+	SET_TX_DESC_PKT_OFFSET(txdesc, value)
+#define GET_TX_DESC_PKT_OFFSET_8821C(txdesc) GET_TX_DESC_PKT_OFFSET(txdesc)
+#define SET_TX_DESC_SEC_TYPE_8821C(txdesc, value)                              \
+	SET_TX_DESC_SEC_TYPE(txdesc, value)
+#define GET_TX_DESC_SEC_TYPE_8821C(txdesc) GET_TX_DESC_SEC_TYPE(txdesc)
+#define SET_TX_DESC_EN_DESC_ID_8821C(txdesc, value)                            \
+	SET_TX_DESC_EN_DESC_ID(txdesc, value)
+#define GET_TX_DESC_EN_DESC_ID_8821C(txdesc) GET_TX_DESC_EN_DESC_ID(txdesc)
+#define SET_TX_DESC_RATE_ID_8821C(txdesc, value)                               \
+	SET_TX_DESC_RATE_ID(txdesc, value)
+#define GET_TX_DESC_RATE_ID_8821C(txdesc) GET_TX_DESC_RATE_ID(txdesc)
+#define SET_TX_DESC_PIFS_8821C(txdesc, value) SET_TX_DESC_PIFS(txdesc, value)
+#define GET_TX_DESC_PIFS_8821C(txdesc) GET_TX_DESC_PIFS(txdesc)
+#define SET_TX_DESC_LSIG_TXOP_EN_8821C(txdesc, value)                          \
+	SET_TX_DESC_LSIG_TXOP_EN(txdesc, value)
+#define GET_TX_DESC_LSIG_TXOP_EN_8821C(txdesc) GET_TX_DESC_LSIG_TXOP_EN(txdesc)
+#define SET_TX_DESC_RD_NAV_EXT_8821C(txdesc, value)                            \
+	SET_TX_DESC_RD_NAV_EXT(txdesc, value)
+#define GET_TX_DESC_RD_NAV_EXT_8821C(txdesc) GET_TX_DESC_RD_NAV_EXT(txdesc)
+#define SET_TX_DESC_QSEL_8821C(txdesc, value) SET_TX_DESC_QSEL(txdesc, value)
+#define GET_TX_DESC_QSEL_8821C(txdesc) GET_TX_DESC_QSEL(txdesc)
+#define SET_TX_DESC_MACID_8821C(txdesc, value) SET_TX_DESC_MACID(txdesc, value)
+#define GET_TX_DESC_MACID_8821C(txdesc) GET_TX_DESC_MACID(txdesc)
+
+/*TXDESC_WORD2*/
+
+#define SET_TX_DESC_HW_AES_IV_8821C(txdesc, value)                             \
+	SET_TX_DESC_HW_AES_IV(txdesc, value)
+#define GET_TX_DESC_HW_AES_IV_8821C(txdesc) GET_TX_DESC_HW_AES_IV(txdesc)
+#define SET_TX_DESC_FTM_EN_8821C(txdesc, value)                                \
+	SET_TX_DESC_FTM_EN(txdesc, value)
+#define GET_TX_DESC_FTM_EN_8821C(txdesc) GET_TX_DESC_FTM_EN(txdesc)
+#define SET_TX_DESC_G_ID_8821C(txdesc, value) SET_TX_DESC_G_ID(txdesc, value)
+#define GET_TX_DESC_G_ID_8821C(txdesc) GET_TX_DESC_G_ID(txdesc)
+#define SET_TX_DESC_BT_NULL_8821C(txdesc, value)                               \
+	SET_TX_DESC_BT_NULL(txdesc, value)
+#define GET_TX_DESC_BT_NULL_8821C(txdesc) GET_TX_DESC_BT_NULL(txdesc)
+#define SET_TX_DESC_AMPDU_DENSITY_8821C(txdesc, value)                         \
+	SET_TX_DESC_AMPDU_DENSITY(txdesc, value)
+#define GET_TX_DESC_AMPDU_DENSITY_8821C(txdesc)                                \
+	GET_TX_DESC_AMPDU_DENSITY(txdesc)
+#define SET_TX_DESC_SPE_RPT_8821C(txdesc, value)                               \
+	SET_TX_DESC_SPE_RPT(txdesc, value)
+#define GET_TX_DESC_SPE_RPT_8821C(txdesc) GET_TX_DESC_SPE_RPT(txdesc)
+#define SET_TX_DESC_RAW_8821C(txdesc, value) SET_TX_DESC_RAW(txdesc, value)
+#define GET_TX_DESC_RAW_8821C(txdesc) GET_TX_DESC_RAW(txdesc)
+#define SET_TX_DESC_MOREFRAG_8821C(txdesc, value)                              \
+	SET_TX_DESC_MOREFRAG(txdesc, value)
+#define GET_TX_DESC_MOREFRAG_8821C(txdesc) GET_TX_DESC_MOREFRAG(txdesc)
+#define SET_TX_DESC_BK_8821C(txdesc, value) SET_TX_DESC_BK(txdesc, value)
+#define GET_TX_DESC_BK_8821C(txdesc) GET_TX_DESC_BK(txdesc)
+#define SET_TX_DESC_NULL_1_8821C(txdesc, value)                                \
+	SET_TX_DESC_NULL_1(txdesc, value)
+#define GET_TX_DESC_NULL_1_8821C(txdesc) GET_TX_DESC_NULL_1(txdesc)
+#define SET_TX_DESC_NULL_0_8821C(txdesc, value)                                \
+	SET_TX_DESC_NULL_0(txdesc, value)
+#define GET_TX_DESC_NULL_0_8821C(txdesc) GET_TX_DESC_NULL_0(txdesc)
+#define SET_TX_DESC_RDG_EN_8821C(txdesc, value)                                \
+	SET_TX_DESC_RDG_EN(txdesc, value)
+#define GET_TX_DESC_RDG_EN_8821C(txdesc) GET_TX_DESC_RDG_EN(txdesc)
+#define SET_TX_DESC_AGG_EN_8821C(txdesc, value)                                \
+	SET_TX_DESC_AGG_EN(txdesc, value)
+#define GET_TX_DESC_AGG_EN_8821C(txdesc) GET_TX_DESC_AGG_EN(txdesc)
+#define SET_TX_DESC_CCA_RTS_8821C(txdesc, value)                               \
+	SET_TX_DESC_CCA_RTS(txdesc, value)
+#define GET_TX_DESC_CCA_RTS_8821C(txdesc) GET_TX_DESC_CCA_RTS(txdesc)
+#define SET_TX_DESC_TRI_FRAME_8821C(txdesc, value)                             \
+	SET_TX_DESC_TRI_FRAME(txdesc, value)
+#define GET_TX_DESC_TRI_FRAME_8821C(txdesc) GET_TX_DESC_TRI_FRAME(txdesc)
+#define SET_TX_DESC_P_AID_8821C(txdesc, value) SET_TX_DESC_P_AID(txdesc, value)
+#define GET_TX_DESC_P_AID_8821C(txdesc) GET_TX_DESC_P_AID(txdesc)
+
+/*TXDESC_WORD3*/
+
+#define SET_TX_DESC_AMPDU_MAX_TIME_8821C(txdesc, value)                        \
+	SET_TX_DESC_AMPDU_MAX_TIME(txdesc, value)
+#define GET_TX_DESC_AMPDU_MAX_TIME_8821C(txdesc)                               \
+	GET_TX_DESC_AMPDU_MAX_TIME(txdesc)
+#define SET_TX_DESC_NDPA_8821C(txdesc, value) SET_TX_DESC_NDPA(txdesc, value)
+#define GET_TX_DESC_NDPA_8821C(txdesc) GET_TX_DESC_NDPA(txdesc)
+#define SET_TX_DESC_MAX_AGG_NUM_8821C(txdesc, value)                           \
+	SET_TX_DESC_MAX_AGG_NUM(txdesc, value)
+#define GET_TX_DESC_MAX_AGG_NUM_8821C(txdesc) GET_TX_DESC_MAX_AGG_NUM(txdesc)
+#define SET_TX_DESC_USE_MAX_TIME_EN_8821C(txdesc, value)                       \
+	SET_TX_DESC_USE_MAX_TIME_EN(txdesc, value)
+#define GET_TX_DESC_USE_MAX_TIME_EN_8821C(txdesc)                              \
+	GET_TX_DESC_USE_MAX_TIME_EN(txdesc)
+#define SET_TX_DESC_NAVUSEHDR_8821C(txdesc, value)                             \
+	SET_TX_DESC_NAVUSEHDR(txdesc, value)
+#define GET_TX_DESC_NAVUSEHDR_8821C(txdesc) GET_TX_DESC_NAVUSEHDR(txdesc)
+#define SET_TX_DESC_CHK_EN_8821C(txdesc, value)                                \
+	SET_TX_DESC_CHK_EN(txdesc, value)
+#define GET_TX_DESC_CHK_EN_8821C(txdesc) GET_TX_DESC_CHK_EN(txdesc)
+#define SET_TX_DESC_HW_RTS_EN_8821C(txdesc, value)                             \
+	SET_TX_DESC_HW_RTS_EN(txdesc, value)
+#define GET_TX_DESC_HW_RTS_EN_8821C(txdesc) GET_TX_DESC_HW_RTS_EN(txdesc)
+#define SET_TX_DESC_RTSEN_8821C(txdesc, value) SET_TX_DESC_RTSEN(txdesc, value)
+#define GET_TX_DESC_RTSEN_8821C(txdesc) GET_TX_DESC_RTSEN(txdesc)
+#define SET_TX_DESC_CTS2SELF_8821C(txdesc, value)                              \
+	SET_TX_DESC_CTS2SELF(txdesc, value)
+#define GET_TX_DESC_CTS2SELF_8821C(txdesc) GET_TX_DESC_CTS2SELF(txdesc)
+#define SET_TX_DESC_DISDATAFB_8821C(txdesc, value)                             \
+	SET_TX_DESC_DISDATAFB(txdesc, value)
+#define GET_TX_DESC_DISDATAFB_8821C(txdesc) GET_TX_DESC_DISDATAFB(txdesc)
+#define SET_TX_DESC_DISRTSFB_8821C(txdesc, value)                              \
+	SET_TX_DESC_DISRTSFB(txdesc, value)
+#define GET_TX_DESC_DISRTSFB_8821C(txdesc) GET_TX_DESC_DISRTSFB(txdesc)
+#define SET_TX_DESC_USE_RATE_8821C(txdesc, value)                              \
+	SET_TX_DESC_USE_RATE(txdesc, value)
+#define GET_TX_DESC_USE_RATE_8821C(txdesc) GET_TX_DESC_USE_RATE(txdesc)
+#define SET_TX_DESC_HW_SSN_SEL_8821C(txdesc, value)                            \
+	SET_TX_DESC_HW_SSN_SEL(txdesc, value)
+#define GET_TX_DESC_HW_SSN_SEL_8821C(txdesc) GET_TX_DESC_HW_SSN_SEL(txdesc)
+#define SET_TX_DESC_WHEADER_LEN_8821C(txdesc, value)                           \
+	SET_TX_DESC_WHEADER_LEN(txdesc, value)
+#define GET_TX_DESC_WHEADER_LEN_8821C(txdesc) GET_TX_DESC_WHEADER_LEN(txdesc)
+
+/*TXDESC_WORD4*/
+
+#define SET_TX_DESC_PCTS_MASK_IDX_8821C(txdesc, value)                         \
+	SET_TX_DESC_PCTS_MASK_IDX(txdesc, value)
+#define GET_TX_DESC_PCTS_MASK_IDX_8821C(txdesc)                                \
+	GET_TX_DESC_PCTS_MASK_IDX(txdesc)
+#define SET_TX_DESC_PCTS_EN_8821C(txdesc, value)                               \
+	SET_TX_DESC_PCTS_EN(txdesc, value)
+#define GET_TX_DESC_PCTS_EN_8821C(txdesc) GET_TX_DESC_PCTS_EN(txdesc)
+#define SET_TX_DESC_RTSRATE_8821C(txdesc, value)                               \
+	SET_TX_DESC_RTSRATE(txdesc, value)
+#define GET_TX_DESC_RTSRATE_8821C(txdesc) GET_TX_DESC_RTSRATE(txdesc)
+#define SET_TX_DESC_RTS_DATA_RTY_LMT_8821C(txdesc, value)                      \
+	SET_TX_DESC_RTS_DATA_RTY_LMT(txdesc, value)
+#define GET_TX_DESC_RTS_DATA_RTY_LMT_8821C(txdesc)                             \
+	GET_TX_DESC_RTS_DATA_RTY_LMT(txdesc)
+#define SET_TX_DESC_RTY_LMT_EN_8821C(txdesc, value)                            \
+	SET_TX_DESC_RTY_LMT_EN(txdesc, value)
+#define GET_TX_DESC_RTY_LMT_EN_8821C(txdesc) GET_TX_DESC_RTY_LMT_EN(txdesc)
+#define SET_TX_DESC_RTS_RTY_LOWEST_RATE_8821C(txdesc, value)                   \
+	SET_TX_DESC_RTS_RTY_LOWEST_RATE(txdesc, value)
+#define GET_TX_DESC_RTS_RTY_LOWEST_RATE_8821C(txdesc)                          \
+	GET_TX_DESC_RTS_RTY_LOWEST_RATE(txdesc)
+#define SET_TX_DESC_DATA_RTY_LOWEST_RATE_8821C(txdesc, value)                  \
+	SET_TX_DESC_DATA_RTY_LOWEST_RATE(txdesc, value)
+#define GET_TX_DESC_DATA_RTY_LOWEST_RATE_8821C(txdesc)                         \
+	GET_TX_DESC_DATA_RTY_LOWEST_RATE(txdesc)
+#define SET_TX_DESC_TRY_RATE_8821C(txdesc, value)                              \
+	SET_TX_DESC_TRY_RATE(txdesc, value)
+#define GET_TX_DESC_TRY_RATE_8821C(txdesc) GET_TX_DESC_TRY_RATE(txdesc)
+#define SET_TX_DESC_DATARATE_8821C(txdesc, value)                              \
+	SET_TX_DESC_DATARATE(txdesc, value)
+#define GET_TX_DESC_DATARATE_8821C(txdesc) GET_TX_DESC_DATARATE(txdesc)
+
+/*TXDESC_WORD5*/
+
+#define SET_TX_DESC_POLLUTED_8821C(txdesc, value)                              \
+	SET_TX_DESC_POLLUTED(txdesc, value)
+#define GET_TX_DESC_POLLUTED_8821C(txdesc) GET_TX_DESC_POLLUTED(txdesc)
+#define SET_TX_DESC_TXPWR_OFSET_8821C(txdesc, value)                           \
+	SET_TX_DESC_TXPWR_OFSET(txdesc, value)
+#define GET_TX_DESC_TXPWR_OFSET_8821C(txdesc) GET_TX_DESC_TXPWR_OFSET(txdesc)
+#define SET_TX_DESC_TX_ANT_8821C(txdesc, value)                                \
+	SET_TX_DESC_TX_ANT(txdesc, value)
+#define GET_TX_DESC_TX_ANT_8821C(txdesc) GET_TX_DESC_TX_ANT(txdesc)
+#define SET_TX_DESC_PORT_ID_8821C(txdesc, value)                               \
+	SET_TX_DESC_PORT_ID(txdesc, value)
+#define GET_TX_DESC_PORT_ID_8821C(txdesc) GET_TX_DESC_PORT_ID(txdesc)
+#define SET_TX_DESC_MULTIPLE_PORT_8821C(txdesc, value)                         \
+	SET_TX_DESC_MULTIPLE_PORT(txdesc, value)
+#define GET_TX_DESC_MULTIPLE_PORT_8821C(txdesc)                                \
+	GET_TX_DESC_MULTIPLE_PORT(txdesc)
+#define SET_TX_DESC_SIGNALING_TAPKT_EN_8821C(txdesc, value)                    \
+	SET_TX_DESC_SIGNALING_TAPKT_EN(txdesc, value)
+#define GET_TX_DESC_SIGNALING_TAPKT_EN_8821C(txdesc)                           \
+	GET_TX_DESC_SIGNALING_TAPKT_EN(txdesc)
+#define SET_TX_DESC_SIGNALING_TA_PKT_SC_8821C(txdesc, value)                   \
+	SET_TX_DESC_SIGNALING_TA_PKT_SC(txdesc, value)
+#define GET_TX_DESC_SIGNALING_TA_PKT_SC_8821C(txdesc)                          \
+	GET_TX_DESC_SIGNALING_TA_PKT_SC(txdesc)
+#define SET_TX_DESC_RTS_SHORT_8821C(txdesc, value)                             \
+	SET_TX_DESC_RTS_SHORT(txdesc, value)
+#define GET_TX_DESC_RTS_SHORT_8821C(txdesc) GET_TX_DESC_RTS_SHORT(txdesc)
+#define SET_TX_DESC_VCS_STBC_8821C(txdesc, value)                              \
+	SET_TX_DESC_VCS_STBC(txdesc, value)
+#define GET_TX_DESC_VCS_STBC_8821C(txdesc) GET_TX_DESC_VCS_STBC(txdesc)
+#define SET_TX_DESC_DATA_STBC_8821C(txdesc, value)                             \
+	SET_TX_DESC_DATA_STBC(txdesc, value)
+#define GET_TX_DESC_DATA_STBC_8821C(txdesc) GET_TX_DESC_DATA_STBC(txdesc)
+#define SET_TX_DESC_DATA_LDPC_8821C(txdesc, value)                             \
+	SET_TX_DESC_DATA_LDPC(txdesc, value)
+#define GET_TX_DESC_DATA_LDPC_8821C(txdesc) GET_TX_DESC_DATA_LDPC(txdesc)
+#define SET_TX_DESC_DATA_BW_8821C(txdesc, value)                               \
+	SET_TX_DESC_DATA_BW(txdesc, value)
+#define GET_TX_DESC_DATA_BW_8821C(txdesc) GET_TX_DESC_DATA_BW(txdesc)
+#define SET_TX_DESC_DATA_SHORT_8821C(txdesc, value)                            \
+	SET_TX_DESC_DATA_SHORT(txdesc, value)
+#define GET_TX_DESC_DATA_SHORT_8821C(txdesc) GET_TX_DESC_DATA_SHORT(txdesc)
+#define SET_TX_DESC_DATA_SC_8821C(txdesc, value)                               \
+	SET_TX_DESC_DATA_SC(txdesc, value)
+#define GET_TX_DESC_DATA_SC_8821C(txdesc) GET_TX_DESC_DATA_SC(txdesc)
+
+/*TXDESC_WORD6*/
+
+#define SET_TX_DESC_ANTSEL_D_8821C(txdesc, value)                              \
+	SET_TX_DESC_ANTSEL_D(txdesc, value)
+#define GET_TX_DESC_ANTSEL_D_8821C(txdesc) GET_TX_DESC_ANTSEL_D(txdesc)
+#define SET_TX_DESC_ANT_MAPD_8821C(txdesc, value)                              \
+	SET_TX_DESC_ANT_MAPD(txdesc, value)
+#define GET_TX_DESC_ANT_MAPD_8821C(txdesc) GET_TX_DESC_ANT_MAPD(txdesc)
+#define SET_TX_DESC_ANT_MAPC_8821C(txdesc, value)                              \
+	SET_TX_DESC_ANT_MAPC(txdesc, value)
+#define GET_TX_DESC_ANT_MAPC_8821C(txdesc) GET_TX_DESC_ANT_MAPC(txdesc)
+#define SET_TX_DESC_ANT_MAPB_8821C(txdesc, value)                              \
+	SET_TX_DESC_ANT_MAPB(txdesc, value)
+#define GET_TX_DESC_ANT_MAPB_8821C(txdesc) GET_TX_DESC_ANT_MAPB(txdesc)
+#define SET_TX_DESC_ANT_MAPA_8821C(txdesc, value)                              \
+	SET_TX_DESC_ANT_MAPA(txdesc, value)
+#define GET_TX_DESC_ANT_MAPA_8821C(txdesc) GET_TX_DESC_ANT_MAPA(txdesc)
+#define SET_TX_DESC_ANTSEL_C_8821C(txdesc, value)                              \
+	SET_TX_DESC_ANTSEL_C(txdesc, value)
+#define GET_TX_DESC_ANTSEL_C_8821C(txdesc) GET_TX_DESC_ANTSEL_C(txdesc)
+#define SET_TX_DESC_ANTSEL_B_8821C(txdesc, value)                              \
+	SET_TX_DESC_ANTSEL_B(txdesc, value)
+#define GET_TX_DESC_ANTSEL_B_8821C(txdesc) GET_TX_DESC_ANTSEL_B(txdesc)
+#define SET_TX_DESC_ANTSEL_A_8821C(txdesc, value)                              \
+	SET_TX_DESC_ANTSEL_A(txdesc, value)
+#define GET_TX_DESC_ANTSEL_A_8821C(txdesc) GET_TX_DESC_ANTSEL_A(txdesc)
+#define SET_TX_DESC_MBSSID_8821C(txdesc, value)                                \
+	SET_TX_DESC_MBSSID(txdesc, value)
+#define GET_TX_DESC_MBSSID_8821C(txdesc) GET_TX_DESC_MBSSID(txdesc)
+#define SET_TX_DESC_SW_DEFINE_8821C(txdesc, value)                             \
+	SET_TX_DESC_SW_DEFINE(txdesc, value)
+#define GET_TX_DESC_SW_DEFINE_8821C(txdesc) GET_TX_DESC_SW_DEFINE(txdesc)
+
+/*TXDESC_WORD7*/
+
+#define SET_TX_DESC_DMA_TXAGG_NUM_8821C(txdesc, value)                         \
+	SET_TX_DESC_DMA_TXAGG_NUM(txdesc, value)
+#define GET_TX_DESC_DMA_TXAGG_NUM_8821C(txdesc)                                \
+	GET_TX_DESC_DMA_TXAGG_NUM(txdesc)
+#define SET_TX_DESC_FINAL_DATA_RATE_8821C(txdesc, value)                       \
+	SET_TX_DESC_FINAL_DATA_RATE(txdesc, value)
+#define GET_TX_DESC_FINAL_DATA_RATE_8821C(txdesc)                              \
+	GET_TX_DESC_FINAL_DATA_RATE(txdesc)
+#define SET_TX_DESC_NTX_MAP_8821C(txdesc, value)                               \
+	SET_TX_DESC_NTX_MAP(txdesc, value)
+#define GET_TX_DESC_NTX_MAP_8821C(txdesc) GET_TX_DESC_NTX_MAP(txdesc)
+#define SET_TX_DESC_TX_BUFF_SIZE_8821C(txdesc, value)                          \
+	SET_TX_DESC_TX_BUFF_SIZE(txdesc, value)
+#define GET_TX_DESC_TX_BUFF_SIZE_8821C(txdesc) GET_TX_DESC_TX_BUFF_SIZE(txdesc)
+#define SET_TX_DESC_TXDESC_CHECKSUM_8821C(txdesc, value)                       \
+	SET_TX_DESC_TXDESC_CHECKSUM(txdesc, value)
+#define GET_TX_DESC_TXDESC_CHECKSUM_8821C(txdesc)                              \
+	GET_TX_DESC_TXDESC_CHECKSUM(txdesc)
+#define SET_TX_DESC_TIMESTAMP_8821C(txdesc, value)                             \
+	SET_TX_DESC_TIMESTAMP(txdesc, value)
+#define GET_TX_DESC_TIMESTAMP_8821C(txdesc) GET_TX_DESC_TIMESTAMP(txdesc)
+
+/*TXDESC_WORD8*/
+
+#define SET_TX_DESC_TXWIFI_CP_8821C(txdesc, value)                             \
+	SET_TX_DESC_TXWIFI_CP(txdesc, value)
+#define GET_TX_DESC_TXWIFI_CP_8821C(txdesc) GET_TX_DESC_TXWIFI_CP(txdesc)
+#define SET_TX_DESC_MAC_CP_8821C(txdesc, value)                                \
+	SET_TX_DESC_MAC_CP(txdesc, value)
+#define GET_TX_DESC_MAC_CP_8821C(txdesc) GET_TX_DESC_MAC_CP(txdesc)
+#define SET_TX_DESC_STW_PKTRE_DIS_8821C(txdesc, value)                         \
+	SET_TX_DESC_STW_PKTRE_DIS(txdesc, value)
+#define GET_TX_DESC_STW_PKTRE_DIS_8821C(txdesc)                                \
+	GET_TX_DESC_STW_PKTRE_DIS(txdesc)
+#define SET_TX_DESC_STW_RB_DIS_8821C(txdesc, value)                            \
+	SET_TX_DESC_STW_RB_DIS(txdesc, value)
+#define GET_TX_DESC_STW_RB_DIS_8821C(txdesc) GET_TX_DESC_STW_RB_DIS(txdesc)
+#define SET_TX_DESC_STW_RATE_DIS_8821C(txdesc, value)                          \
+	SET_TX_DESC_STW_RATE_DIS(txdesc, value)
+#define GET_TX_DESC_STW_RATE_DIS_8821C(txdesc) GET_TX_DESC_STW_RATE_DIS(txdesc)
+#define SET_TX_DESC_STW_ANT_DIS_8821C(txdesc, value)                           \
+	SET_TX_DESC_STW_ANT_DIS(txdesc, value)
+#define GET_TX_DESC_STW_ANT_DIS_8821C(txdesc) GET_TX_DESC_STW_ANT_DIS(txdesc)
+#define SET_TX_DESC_STW_EN_8821C(txdesc, value)                                \
+	SET_TX_DESC_STW_EN(txdesc, value)
+#define GET_TX_DESC_STW_EN_8821C(txdesc) GET_TX_DESC_STW_EN(txdesc)
+#define SET_TX_DESC_SMH_EN_8821C(txdesc, value)                                \
+	SET_TX_DESC_SMH_EN(txdesc, value)
+#define GET_TX_DESC_SMH_EN_8821C(txdesc) GET_TX_DESC_SMH_EN(txdesc)
+#define SET_TX_DESC_TAILPAGE_L_8821C(txdesc, value)                            \
+	SET_TX_DESC_TAILPAGE_L(txdesc, value)
+#define GET_TX_DESC_TAILPAGE_L_8821C(txdesc) GET_TX_DESC_TAILPAGE_L(txdesc)
+#define SET_TX_DESC_SDIO_DMASEQ_8821C(txdesc, value)                           \
+	SET_TX_DESC_SDIO_DMASEQ(txdesc, value)
+#define GET_TX_DESC_SDIO_DMASEQ_8821C(txdesc) GET_TX_DESC_SDIO_DMASEQ(txdesc)
+#define SET_TX_DESC_NEXTHEADPAGE_L_8821C(txdesc, value)                        \
+	SET_TX_DESC_NEXTHEADPAGE_L(txdesc, value)
+#define GET_TX_DESC_NEXTHEADPAGE_L_8821C(txdesc)                               \
+	GET_TX_DESC_NEXTHEADPAGE_L(txdesc)
+#define SET_TX_DESC_EN_HWSEQ_8821C(txdesc, value)                              \
+	SET_TX_DESC_EN_HWSEQ(txdesc, value)
+#define GET_TX_DESC_EN_HWSEQ_8821C(txdesc) GET_TX_DESC_EN_HWSEQ(txdesc)
+#define SET_TX_DESC_EN_HWEXSEQ_8821C(txdesc, value)                            \
+	SET_TX_DESC_EN_HWEXSEQ(txdesc, value)
+#define GET_TX_DESC_EN_HWEXSEQ_8821C(txdesc) GET_TX_DESC_EN_HWEXSEQ(txdesc)
+#define SET_TX_DESC_DATA_RC_8821C(txdesc, value)                               \
+	SET_TX_DESC_DATA_RC(txdesc, value)
+#define GET_TX_DESC_DATA_RC_8821C(txdesc) GET_TX_DESC_DATA_RC(txdesc)
+#define SET_TX_DESC_BAR_RTY_TH_8821C(txdesc, value)                            \
+	SET_TX_DESC_BAR_RTY_TH(txdesc, value)
+#define GET_TX_DESC_BAR_RTY_TH_8821C(txdesc) GET_TX_DESC_BAR_RTY_TH(txdesc)
+#define SET_TX_DESC_RTS_RC_8821C(txdesc, value)                                \
+	SET_TX_DESC_RTS_RC(txdesc, value)
+#define GET_TX_DESC_RTS_RC_8821C(txdesc) GET_TX_DESC_RTS_RC(txdesc)
+
+/*TXDESC_WORD9*/
+
+#define SET_TX_DESC_TAILPAGE_H_8821C(txdesc, value)                            \
+	SET_TX_DESC_TAILPAGE_H(txdesc, value)
+#define GET_TX_DESC_TAILPAGE_H_8821C(txdesc) GET_TX_DESC_TAILPAGE_H(txdesc)
+#define SET_TX_DESC_NEXTHEADPAGE_H_8821C(txdesc, value)                        \
+	SET_TX_DESC_NEXTHEADPAGE_H(txdesc, value)
+#define GET_TX_DESC_NEXTHEADPAGE_H_8821C(txdesc)                               \
+	GET_TX_DESC_NEXTHEADPAGE_H(txdesc)
+#define SET_TX_DESC_SW_SEQ_8821C(txdesc, value)                                \
+	SET_TX_DESC_SW_SEQ(txdesc, value)
+#define GET_TX_DESC_SW_SEQ_8821C(txdesc) GET_TX_DESC_SW_SEQ(txdesc)
+#define SET_TX_DESC_TXBF_PATH_8821C(txdesc, value)                             \
+	SET_TX_DESC_TXBF_PATH(txdesc, value)
+#define GET_TX_DESC_TXBF_PATH_8821C(txdesc) GET_TX_DESC_TXBF_PATH(txdesc)
+#define SET_TX_DESC_PADDING_LEN_8821C(txdesc, value)                           \
+	SET_TX_DESC_PADDING_LEN(txdesc, value)
+#define GET_TX_DESC_PADDING_LEN_8821C(txdesc) GET_TX_DESC_PADDING_LEN(txdesc)
+#define SET_TX_DESC_GROUP_BIT_IE_OFFSET_8821C(txdesc, value)                   \
+	SET_TX_DESC_GROUP_BIT_IE_OFFSET(txdesc, value)
+#define GET_TX_DESC_GROUP_BIT_IE_OFFSET_8821C(txdesc)                          \
+	GET_TX_DESC_GROUP_BIT_IE_OFFSET(txdesc)
+
+/*WORD10*/
+
+#define SET_TX_DESC_MU_DATARATE_8821C(txdesc, value)                           \
+	SET_TX_DESC_MU_DATARATE(txdesc, value)
+#define GET_TX_DESC_MU_DATARATE_8821C(txdesc) GET_TX_DESC_MU_DATARATE(txdesc)
+#define SET_TX_DESC_MU_RC_8821C(txdesc, value) SET_TX_DESC_MU_RC(txdesc, value)
+#define GET_TX_DESC_MU_RC_8821C(txdesc) GET_TX_DESC_MU_RC(txdesc)
+#define SET_TX_DESC_SND_PKT_SEL_8821C(txdesc, value)                           \
+	SET_TX_DESC_SND_PKT_SEL(txdesc, value)
+#define GET_TX_DESC_SND_PKT_SEL_8821C(txdesc) GET_TX_DESC_SND_PKT_SEL(txdesc)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/*TXDESC_WORD0*/
+
+#define SET_TX_DESC_IE_END_BODY_8814B(txdesc, value)                           \
+	SET_TX_DESC_IE_END_BODY(txdesc, value)
+#define GET_TX_DESC_IE_END_BODY_8814B(txdesc) GET_TX_DESC_IE_END_BODY(txdesc)
+#define SET_TX_DESC_AGG_EN_8814B(txdesc, value)                                \
+	SET_TX_DESC_AGG_EN_V1(txdesc, value)
+#define GET_TX_DESC_AGG_EN_8814B(txdesc) GET_TX_DESC_AGG_EN_V1(txdesc)
+#define SET_TX_DESC_BK_8814B(txdesc, value) SET_TX_DESC_BK_V1(txdesc, value)
+#define GET_TX_DESC_BK_8814B(txdesc) GET_TX_DESC_BK_V1(txdesc)
+#define SET_TX_DESC_PKT_OFFSET_8814B(txdesc, value)                            \
+	SET_TX_DESC_PKT_OFFSET_V1(txdesc, value)
+#define GET_TX_DESC_PKT_OFFSET_8814B(txdesc) GET_TX_DESC_PKT_OFFSET_V1(txdesc)
+#define SET_TX_DESC_OFFSET_8814B(txdesc, value)                                \
+	SET_TX_DESC_OFFSET(txdesc, value)
+#define GET_TX_DESC_OFFSET_8814B(txdesc) GET_TX_DESC_OFFSET(txdesc)
+#define SET_TX_DESC_TXPKTSIZE_8814B(txdesc, value)                             \
+	SET_TX_DESC_TXPKTSIZE(txdesc, value)
+#define GET_TX_DESC_TXPKTSIZE_8814B(txdesc) GET_TX_DESC_TXPKTSIZE(txdesc)
+
+/*WORD1*/
+
+#define SET_TX_DESC_AMSDU_8814B(txdesc, value) SET_TX_DESC_AMSDU(txdesc, value)
+#define GET_TX_DESC_AMSDU_8814B(txdesc) GET_TX_DESC_AMSDU(txdesc)
+#define SET_TX_DESC_HW_AES_IV_8814B(txdesc, value)                             \
+	SET_TX_DESC_HW_AES_IV_V1(txdesc, value)
+#define GET_TX_DESC_HW_AES_IV_8814B(txdesc) GET_TX_DESC_HW_AES_IV_V1(txdesc)
+#define SET_TX_DESC_MHR_CP_8814B(txdesc, value)                                \
+	SET_TX_DESC_MHR_CP(txdesc, value)
+#define GET_TX_DESC_MHR_CP_8814B(txdesc) GET_TX_DESC_MHR_CP(txdesc)
+#define SET_TX_DESC_SMH_EN_8814B(txdesc, value)                                \
+	SET_TX_DESC_SMH_EN_V1(txdesc, value)
+#define GET_TX_DESC_SMH_EN_8814B(txdesc) GET_TX_DESC_SMH_EN_V1(txdesc)
+#define SET_TX_DESC_SMH_CAM_8814B(txdesc, value)                               \
+	SET_TX_DESC_SMH_CAM(txdesc, value)
+#define GET_TX_DESC_SMH_CAM_8814B(txdesc) GET_TX_DESC_SMH_CAM(txdesc)
+#define SET_TX_DESC_EXT_EDCA_8814B(txdesc, value)                              \
+	SET_TX_DESC_EXT_EDCA(txdesc, value)
+#define GET_TX_DESC_EXT_EDCA_8814B(txdesc) GET_TX_DESC_EXT_EDCA(txdesc)
+#define SET_TX_DESC_QSEL_8814B(txdesc, value) SET_TX_DESC_QSEL(txdesc, value)
+#define GET_TX_DESC_QSEL_8814B(txdesc) GET_TX_DESC_QSEL(txdesc)
+#define SET_TX_DESC_MACID_8814B(txdesc, value)                                 \
+	SET_TX_DESC_MACID_V1(txdesc, value)
+#define GET_TX_DESC_MACID_8814B(txdesc) GET_TX_DESC_MACID_V1(txdesc)
+
+/*TXDESC_WORD2*/
+
+#define SET_TX_DESC_CHK_EN_8814B(txdesc, value)                                \
+	SET_TX_DESC_CHK_EN_V1(txdesc, value)
+#define GET_TX_DESC_CHK_EN_8814B(txdesc) GET_TX_DESC_CHK_EN_V1(txdesc)
+#define SET_TX_DESC_DMA_PRI_8814B(txdesc, value)                               \
+	SET_TX_DESC_DMA_PRI(txdesc, value)
+#define GET_TX_DESC_DMA_PRI_8814B(txdesc) GET_TX_DESC_DMA_PRI(txdesc)
+#define SET_TX_DESC_MAX_AMSDU_MODE_8814B(txdesc, value)                        \
+	SET_TX_DESC_MAX_AMSDU_MODE(txdesc, value)
+#define GET_TX_DESC_MAX_AMSDU_MODE_8814B(txdesc)                               \
+	GET_TX_DESC_MAX_AMSDU_MODE(txdesc)
+#define SET_TX_DESC_DMA_TXAGG_NUM_8814B(txdesc, value)                         \
+	SET_TX_DESC_DMA_TXAGG_NUM_V1(txdesc, value)
+#define GET_TX_DESC_DMA_TXAGG_NUM_8814B(txdesc)                                \
+	GET_TX_DESC_DMA_TXAGG_NUM_V1(txdesc)
+#define SET_TX_DESC_TXDESC_CHECKSUM_8814B(txdesc, value)                       \
+	SET_TX_DESC_TXDESC_CHECKSUM_V1(txdesc, value)
+#define GET_TX_DESC_TXDESC_CHECKSUM_8814B(txdesc)                              \
+	GET_TX_DESC_TXDESC_CHECKSUM_V1(txdesc)
+
+/*TXDESC_WORD3*/
+
+#define SET_TX_DESC_OFFLOAD_SIZE_8814B(txdesc, value)                          \
+	SET_TX_DESC_OFFLOAD_SIZE(txdesc, value)
+#define GET_TX_DESC_OFFLOAD_SIZE_8814B(txdesc) GET_TX_DESC_OFFLOAD_SIZE(txdesc)
+#define SET_TX_DESC_CHANNEL_DMA_8814B(txdesc, value)                           \
+	SET_TX_DESC_CHANNEL_DMA(txdesc, value)
+#define GET_TX_DESC_CHANNEL_DMA_8814B(txdesc) GET_TX_DESC_CHANNEL_DMA(txdesc)
+#define SET_TX_DESC_IE_CNT_8814B(txdesc, value)                                \
+	SET_TX_DESC_IE_CNT(txdesc, value)
+#define GET_TX_DESC_IE_CNT_8814B(txdesc) GET_TX_DESC_IE_CNT(txdesc)
+#define SET_TX_DESC_IE_CNT_EN_8814B(txdesc, value)                             \
+	SET_TX_DESC_IE_CNT_EN(txdesc, value)
+#define GET_TX_DESC_IE_CNT_EN_8814B(txdesc) GET_TX_DESC_IE_CNT_EN(txdesc)
+#define SET_TX_DESC_WHEADER_LEN_8814B(txdesc, value)                           \
+	SET_TX_DESC_WHEADER_LEN_V1(txdesc, value)
+#define GET_TX_DESC_WHEADER_LEN_8814B(txdesc) GET_TX_DESC_WHEADER_LEN_V1(txdesc)
+
+/*TXDESC_WORD4*/
+
+/*TXDESC_WORD5*/
+
+/*TXDESC_WORD6*/
+
+/*TXDESC_WORD7*/
+
+/*TXDESC_WORD8*/
+
+/*TXDESC_WORD9*/
+
+/*WORD10*/
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+/*TXDESC_WORD0*/
+
+#define SET_TX_DESC_DISQSELSEQ_8198F(txdesc, value)                            \
+	SET_TX_DESC_DISQSELSEQ(txdesc, value)
+#define GET_TX_DESC_DISQSELSEQ_8198F(txdesc) GET_TX_DESC_DISQSELSEQ(txdesc)
+#define SET_TX_DESC_GF_8198F(txdesc, value) SET_TX_DESC_GF(txdesc, value)
+#define GET_TX_DESC_GF_8198F(txdesc) GET_TX_DESC_GF(txdesc)
+#define SET_TX_DESC_NO_ACM_8198F(txdesc, value)                                \
+	SET_TX_DESC_NO_ACM(txdesc, value)
+#define GET_TX_DESC_NO_ACM_8198F(txdesc) GET_TX_DESC_NO_ACM(txdesc)
+#define SET_TX_DESC_BCNPKT_TSF_CTRL_8198F(txdesc, value)                       \
+	SET_TX_DESC_BCNPKT_TSF_CTRL(txdesc, value)
+#define GET_TX_DESC_BCNPKT_TSF_CTRL_8198F(txdesc)                              \
+	GET_TX_DESC_BCNPKT_TSF_CTRL(txdesc)
+#define SET_TX_DESC_AMSDU_PAD_EN_8198F(txdesc, value)                          \
+	SET_TX_DESC_AMSDU_PAD_EN(txdesc, value)
+#define GET_TX_DESC_AMSDU_PAD_EN_8198F(txdesc) GET_TX_DESC_AMSDU_PAD_EN(txdesc)
+#define SET_TX_DESC_LS_8198F(txdesc, value) SET_TX_DESC_LS(txdesc, value)
+#define GET_TX_DESC_LS_8198F(txdesc) GET_TX_DESC_LS(txdesc)
+#define SET_TX_DESC_HTC_8198F(txdesc, value) SET_TX_DESC_HTC(txdesc, value)
+#define GET_TX_DESC_HTC_8198F(txdesc) GET_TX_DESC_HTC(txdesc)
+#define SET_TX_DESC_BMC_8198F(txdesc, value) SET_TX_DESC_BMC(txdesc, value)
+#define GET_TX_DESC_BMC_8198F(txdesc) GET_TX_DESC_BMC(txdesc)
+#define SET_TX_DESC_OFFSET_8198F(txdesc, value)                                \
+	SET_TX_DESC_OFFSET(txdesc, value)
+#define GET_TX_DESC_OFFSET_8198F(txdesc) GET_TX_DESC_OFFSET(txdesc)
+#define SET_TX_DESC_TXPKTSIZE_8198F(txdesc, value)                             \
+	SET_TX_DESC_TXPKTSIZE(txdesc, value)
+#define GET_TX_DESC_TXPKTSIZE_8198F(txdesc) GET_TX_DESC_TXPKTSIZE(txdesc)
+
+/*WORD1*/
+
+#define SET_TX_DESC_HW_AES_IV_8198F(txdesc, value)                             \
+	SET_TX_DESC_HW_AES_IV_V2(txdesc, value)
+#define GET_TX_DESC_HW_AES_IV_8198F(txdesc) GET_TX_DESC_HW_AES_IV_V2(txdesc)
+#define SET_TX_DESC_FTM_EN_8198F(txdesc, value)                                \
+	SET_TX_DESC_FTM_EN_V1(txdesc, value)
+#define GET_TX_DESC_FTM_EN_8198F(txdesc) GET_TX_DESC_FTM_EN_V1(txdesc)
+#define SET_TX_DESC_MOREDATA_8198F(txdesc, value)                              \
+	SET_TX_DESC_MOREDATA(txdesc, value)
+#define GET_TX_DESC_MOREDATA_8198F(txdesc) GET_TX_DESC_MOREDATA(txdesc)
+#define SET_TX_DESC_PKT_OFFSET_8198F(txdesc, value)                            \
+	SET_TX_DESC_PKT_OFFSET(txdesc, value)
+#define GET_TX_DESC_PKT_OFFSET_8198F(txdesc) GET_TX_DESC_PKT_OFFSET(txdesc)
+#define SET_TX_DESC_SEC_TYPE_8198F(txdesc, value)                              \
+	SET_TX_DESC_SEC_TYPE(txdesc, value)
+#define GET_TX_DESC_SEC_TYPE_8198F(txdesc) GET_TX_DESC_SEC_TYPE(txdesc)
+#define SET_TX_DESC_EN_DESC_ID_8198F(txdesc, value)                            \
+	SET_TX_DESC_EN_DESC_ID(txdesc, value)
+#define GET_TX_DESC_EN_DESC_ID_8198F(txdesc) GET_TX_DESC_EN_DESC_ID(txdesc)
+#define SET_TX_DESC_RATE_ID_8198F(txdesc, value)                               \
+	SET_TX_DESC_RATE_ID(txdesc, value)
+#define GET_TX_DESC_RATE_ID_8198F(txdesc) GET_TX_DESC_RATE_ID(txdesc)
+#define SET_TX_DESC_PIFS_8198F(txdesc, value) SET_TX_DESC_PIFS(txdesc, value)
+#define GET_TX_DESC_PIFS_8198F(txdesc) GET_TX_DESC_PIFS(txdesc)
+#define SET_TX_DESC_LSIG_TXOP_EN_8198F(txdesc, value)                          \
+	SET_TX_DESC_LSIG_TXOP_EN(txdesc, value)
+#define GET_TX_DESC_LSIG_TXOP_EN_8198F(txdesc) GET_TX_DESC_LSIG_TXOP_EN(txdesc)
+#define SET_TX_DESC_RD_NAV_EXT_8198F(txdesc, value)                            \
+	SET_TX_DESC_RD_NAV_EXT(txdesc, value)
+#define GET_TX_DESC_RD_NAV_EXT_8198F(txdesc) GET_TX_DESC_RD_NAV_EXT(txdesc)
+#define SET_TX_DESC_QSEL_8198F(txdesc, value) SET_TX_DESC_QSEL(txdesc, value)
+#define GET_TX_DESC_QSEL_8198F(txdesc) GET_TX_DESC_QSEL(txdesc)
+#define SET_TX_DESC_SPECIAL_CW_8198F(txdesc, value)                            \
+	SET_TX_DESC_SPECIAL_CW(txdesc, value)
+#define GET_TX_DESC_SPECIAL_CW_8198F(txdesc) GET_TX_DESC_SPECIAL_CW(txdesc)
+#define SET_TX_DESC_MACID_8198F(txdesc, value) SET_TX_DESC_MACID(txdesc, value)
+#define GET_TX_DESC_MACID_8198F(txdesc) GET_TX_DESC_MACID(txdesc)
+
+/*TXDESC_WORD2*/
+
+#define SET_TX_DESC_ANTCEL_D_8198F(txdesc, value)                              \
+	SET_TX_DESC_ANTCEL_D_V1(txdesc, value)
+#define GET_TX_DESC_ANTCEL_D_8198F(txdesc) GET_TX_DESC_ANTCEL_D_V1(txdesc)
+#define SET_TX_DESC_ANTSEL_C_8198F(txdesc, value)                              \
+	SET_TX_DESC_ANTSEL_C_V1(txdesc, value)
+#define GET_TX_DESC_ANTSEL_C_8198F(txdesc) GET_TX_DESC_ANTSEL_C_V1(txdesc)
+#define SET_TX_DESC_BT_NULL_8198F(txdesc, value)                               \
+	SET_TX_DESC_BT_NULL(txdesc, value)
+#define GET_TX_DESC_BT_NULL_8198F(txdesc) GET_TX_DESC_BT_NULL(txdesc)
+#define SET_TX_DESC_AMPDU_DENSITY_8198F(txdesc, value)                         \
+	SET_TX_DESC_AMPDU_DENSITY(txdesc, value)
+#define GET_TX_DESC_AMPDU_DENSITY_8198F(txdesc)                                \
+	GET_TX_DESC_AMPDU_DENSITY(txdesc)
+#define SET_TX_DESC_SPE_RPT_8198F(txdesc, value)                               \
+	SET_TX_DESC_SPE_RPT(txdesc, value)
+#define GET_TX_DESC_SPE_RPT_8198F(txdesc) GET_TX_DESC_SPE_RPT(txdesc)
+#define SET_TX_DESC_RAW_8198F(txdesc, value) SET_TX_DESC_RAW(txdesc, value)
+#define GET_TX_DESC_RAW_8198F(txdesc) GET_TX_DESC_RAW(txdesc)
+#define SET_TX_DESC_MOREFRAG_8198F(txdesc, value)                              \
+	SET_TX_DESC_MOREFRAG(txdesc, value)
+#define GET_TX_DESC_MOREFRAG_8198F(txdesc) GET_TX_DESC_MOREFRAG(txdesc)
+#define SET_TX_DESC_BK_8198F(txdesc, value) SET_TX_DESC_BK(txdesc, value)
+#define GET_TX_DESC_BK_8198F(txdesc) GET_TX_DESC_BK(txdesc)
+#define SET_TX_DESC_NULL_1_8198F(txdesc, value)                                \
+	SET_TX_DESC_NULL_1(txdesc, value)
+#define GET_TX_DESC_NULL_1_8198F(txdesc) GET_TX_DESC_NULL_1(txdesc)
+#define SET_TX_DESC_NULL_0_8198F(txdesc, value)                                \
+	SET_TX_DESC_NULL_0(txdesc, value)
+#define GET_TX_DESC_NULL_0_8198F(txdesc) GET_TX_DESC_NULL_0(txdesc)
+#define SET_TX_DESC_RDG_EN_8198F(txdesc, value)                                \
+	SET_TX_DESC_RDG_EN(txdesc, value)
+#define GET_TX_DESC_RDG_EN_8198F(txdesc) GET_TX_DESC_RDG_EN(txdesc)
+#define SET_TX_DESC_AGG_EN_8198F(txdesc, value)                                \
+	SET_TX_DESC_AGG_EN(txdesc, value)
+#define GET_TX_DESC_AGG_EN_8198F(txdesc) GET_TX_DESC_AGG_EN(txdesc)
+#define SET_TX_DESC_CCA_RTS_8198F(txdesc, value)                               \
+	SET_TX_DESC_CCA_RTS(txdesc, value)
+#define GET_TX_DESC_CCA_RTS_8198F(txdesc) GET_TX_DESC_CCA_RTS(txdesc)
+#define SET_TX_DESC_TRI_FRAME_8198F(txdesc, value)                             \
+	SET_TX_DESC_TRI_FRAME(txdesc, value)
+#define GET_TX_DESC_TRI_FRAME_8198F(txdesc) GET_TX_DESC_TRI_FRAME(txdesc)
+#define SET_TX_DESC_P_AID_8198F(txdesc, value) SET_TX_DESC_P_AID(txdesc, value)
+#define GET_TX_DESC_P_AID_8198F(txdesc) GET_TX_DESC_P_AID(txdesc)
+
+/*TXDESC_WORD3*/
+
+#define SET_TX_DESC_AMPDU_MAX_TIME_8198F(txdesc, value)                        \
+	SET_TX_DESC_AMPDU_MAX_TIME(txdesc, value)
+#define GET_TX_DESC_AMPDU_MAX_TIME_8198F(txdesc)                               \
+	GET_TX_DESC_AMPDU_MAX_TIME(txdesc)
+#define SET_TX_DESC_NDPA_8198F(txdesc, value) SET_TX_DESC_NDPA(txdesc, value)
+#define GET_TX_DESC_NDPA_8198F(txdesc) GET_TX_DESC_NDPA(txdesc)
+#define SET_TX_DESC_MAX_AGG_NUM_8198F(txdesc, value)                           \
+	SET_TX_DESC_MAX_AGG_NUM(txdesc, value)
+#define GET_TX_DESC_MAX_AGG_NUM_8198F(txdesc) GET_TX_DESC_MAX_AGG_NUM(txdesc)
+#define SET_TX_DESC_USE_MAX_TIME_EN_8198F(txdesc, value)                       \
+	SET_TX_DESC_USE_MAX_TIME_EN(txdesc, value)
+#define GET_TX_DESC_USE_MAX_TIME_EN_8198F(txdesc)                              \
+	GET_TX_DESC_USE_MAX_TIME_EN(txdesc)
+#define SET_TX_DESC_NAVUSEHDR_8198F(txdesc, value)                             \
+	SET_TX_DESC_NAVUSEHDR(txdesc, value)
+#define GET_TX_DESC_NAVUSEHDR_8198F(txdesc) GET_TX_DESC_NAVUSEHDR(txdesc)
+#define SET_TX_DESC_CHK_EN_8198F(txdesc, value)                                \
+	SET_TX_DESC_CHK_EN(txdesc, value)
+#define GET_TX_DESC_CHK_EN_8198F(txdesc) GET_TX_DESC_CHK_EN(txdesc)
+#define SET_TX_DESC_HW_RTS_EN_8198F(txdesc, value)                             \
+	SET_TX_DESC_HW_RTS_EN(txdesc, value)
+#define GET_TX_DESC_HW_RTS_EN_8198F(txdesc) GET_TX_DESC_HW_RTS_EN(txdesc)
+#define SET_TX_DESC_RTSEN_8198F(txdesc, value) SET_TX_DESC_RTSEN(txdesc, value)
+#define GET_TX_DESC_RTSEN_8198F(txdesc) GET_TX_DESC_RTSEN(txdesc)
+#define SET_TX_DESC_CTS2SELF_8198F(txdesc, value)                              \
+	SET_TX_DESC_CTS2SELF(txdesc, value)
+#define GET_TX_DESC_CTS2SELF_8198F(txdesc) GET_TX_DESC_CTS2SELF(txdesc)
+#define SET_TX_DESC_DISDATAFB_8198F(txdesc, value)                             \
+	SET_TX_DESC_DISDATAFB(txdesc, value)
+#define GET_TX_DESC_DISDATAFB_8198F(txdesc) GET_TX_DESC_DISDATAFB(txdesc)
+#define SET_TX_DESC_DISRTSFB_8198F(txdesc, value)                              \
+	SET_TX_DESC_DISRTSFB(txdesc, value)
+#define GET_TX_DESC_DISRTSFB_8198F(txdesc) GET_TX_DESC_DISRTSFB(txdesc)
+#define SET_TX_DESC_USE_RATE_8198F(txdesc, value)                              \
+	SET_TX_DESC_USE_RATE(txdesc, value)
+#define GET_TX_DESC_USE_RATE_8198F(txdesc) GET_TX_DESC_USE_RATE(txdesc)
+#define SET_TX_DESC_HW_SSN_SEL_8198F(txdesc, value)                            \
+	SET_TX_DESC_HW_SSN_SEL(txdesc, value)
+#define GET_TX_DESC_HW_SSN_SEL_8198F(txdesc) GET_TX_DESC_HW_SSN_SEL(txdesc)
+#define SET_TX_DESC_WHEADER_LEN_8198F(txdesc, value)                           \
+	SET_TX_DESC_WHEADER_LEN(txdesc, value)
+#define GET_TX_DESC_WHEADER_LEN_8198F(txdesc) GET_TX_DESC_WHEADER_LEN(txdesc)
+
+/*TXDESC_WORD4*/
+
+#define SET_TX_DESC_PCTS_MASK_IDX_8198F(txdesc, value)                         \
+	SET_TX_DESC_PCTS_MASK_IDX(txdesc, value)
+#define GET_TX_DESC_PCTS_MASK_IDX_8198F(txdesc)                                \
+	GET_TX_DESC_PCTS_MASK_IDX(txdesc)
+#define SET_TX_DESC_PCTS_EN_8198F(txdesc, value)                               \
+	SET_TX_DESC_PCTS_EN(txdesc, value)
+#define GET_TX_DESC_PCTS_EN_8198F(txdesc) GET_TX_DESC_PCTS_EN(txdesc)
+#define SET_TX_DESC_RTSRATE_8198F(txdesc, value)                               \
+	SET_TX_DESC_RTSRATE(txdesc, value)
+#define GET_TX_DESC_RTSRATE_8198F(txdesc) GET_TX_DESC_RTSRATE(txdesc)
+#define SET_TX_DESC_RTS_DATA_RTY_LMT_8198F(txdesc, value)                      \
+	SET_TX_DESC_RTS_DATA_RTY_LMT(txdesc, value)
+#define GET_TX_DESC_RTS_DATA_RTY_LMT_8198F(txdesc)                             \
+	GET_TX_DESC_RTS_DATA_RTY_LMT(txdesc)
+#define SET_TX_DESC_RTY_LMT_EN_8198F(txdesc, value)                            \
+	SET_TX_DESC_RTY_LMT_EN(txdesc, value)
+#define GET_TX_DESC_RTY_LMT_EN_8198F(txdesc) GET_TX_DESC_RTY_LMT_EN(txdesc)
+#define SET_TX_DESC_RTS_RTY_LOWEST_RATE_8198F(txdesc, value)                   \
+	SET_TX_DESC_RTS_RTY_LOWEST_RATE(txdesc, value)
+#define GET_TX_DESC_RTS_RTY_LOWEST_RATE_8198F(txdesc)                          \
+	GET_TX_DESC_RTS_RTY_LOWEST_RATE(txdesc)
+#define SET_TX_DESC_DATA_RTY_LOWEST_RATE_8198F(txdesc, value)                  \
+	SET_TX_DESC_DATA_RTY_LOWEST_RATE(txdesc, value)
+#define GET_TX_DESC_DATA_RTY_LOWEST_RATE_8198F(txdesc)                         \
+	GET_TX_DESC_DATA_RTY_LOWEST_RATE(txdesc)
+#define SET_TX_DESC_TRY_RATE_8198F(txdesc, value)                              \
+	SET_TX_DESC_TRY_RATE(txdesc, value)
+#define GET_TX_DESC_TRY_RATE_8198F(txdesc) GET_TX_DESC_TRY_RATE(txdesc)
+#define SET_TX_DESC_DATARATE_8198F(txdesc, value)                              \
+	SET_TX_DESC_DATARATE(txdesc, value)
+#define GET_TX_DESC_DATARATE_8198F(txdesc) GET_TX_DESC_DATARATE(txdesc)
+
+/*TXDESC_WORD5*/
+
+#define SET_TX_DESC_POLLUTED_8198F(txdesc, value)                              \
+	SET_TX_DESC_POLLUTED(txdesc, value)
+#define GET_TX_DESC_POLLUTED_8198F(txdesc) GET_TX_DESC_POLLUTED(txdesc)
+#define SET_TX_DESC_TXPWR_OFSET_8198F(txdesc, value)                           \
+	SET_TX_DESC_TXPWR_OFSET(txdesc, value)
+#define GET_TX_DESC_TXPWR_OFSET_8198F(txdesc) GET_TX_DESC_TXPWR_OFSET(txdesc)
+#define SET_TX_DESC_DROP_ID_8198F(txdesc, value)                               \
+	SET_TX_DESC_DROP_ID(txdesc, value)
+#define GET_TX_DESC_DROP_ID_8198F(txdesc) GET_TX_DESC_DROP_ID(txdesc)
+#define SET_TX_DESC_PORT_ID_8198F(txdesc, value)                               \
+	SET_TX_DESC_PORT_ID(txdesc, value)
+#define GET_TX_DESC_PORT_ID_8198F(txdesc) GET_TX_DESC_PORT_ID(txdesc)
+#define SET_TX_DESC_MULTIPLE_PORT_8198F(txdesc, value)                         \
+	SET_TX_DESC_MULTIPLE_PORT(txdesc, value)
+#define GET_TX_DESC_MULTIPLE_PORT_8198F(txdesc)                                \
+	GET_TX_DESC_MULTIPLE_PORT(txdesc)
+#define SET_TX_DESC_SIGNALING_TAPKT_EN_8198F(txdesc, value)                    \
+	SET_TX_DESC_SIGNALING_TAPKT_EN(txdesc, value)
+#define GET_TX_DESC_SIGNALING_TAPKT_EN_8198F(txdesc)                           \
+	GET_TX_DESC_SIGNALING_TAPKT_EN(txdesc)
+#define SET_TX_DESC_RTS_SC_8198F(txdesc, value)                                \
+	SET_TX_DESC_RTS_SC(txdesc, value)
+#define GET_TX_DESC_RTS_SC_8198F(txdesc) GET_TX_DESC_RTS_SC(txdesc)
+#define SET_TX_DESC_RTS_SHORT_8198F(txdesc, value)                             \
+	SET_TX_DESC_RTS_SHORT(txdesc, value)
+#define GET_TX_DESC_RTS_SHORT_8198F(txdesc) GET_TX_DESC_RTS_SHORT(txdesc)
+#define SET_TX_DESC_VCS_STBC_8198F(txdesc, value)                              \
+	SET_TX_DESC_VCS_STBC(txdesc, value)
+#define GET_TX_DESC_VCS_STBC_8198F(txdesc) GET_TX_DESC_VCS_STBC(txdesc)
+#define SET_TX_DESC_DATA_STBC_8198F(txdesc, value)                             \
+	SET_TX_DESC_DATA_STBC(txdesc, value)
+#define GET_TX_DESC_DATA_STBC_8198F(txdesc) GET_TX_DESC_DATA_STBC(txdesc)
+#define SET_TX_DESC_DATA_LDPC_8198F(txdesc, value)                             \
+	SET_TX_DESC_DATA_LDPC(txdesc, value)
+#define GET_TX_DESC_DATA_LDPC_8198F(txdesc) GET_TX_DESC_DATA_LDPC(txdesc)
+#define SET_TX_DESC_DATA_BW_8198F(txdesc, value)                               \
+	SET_TX_DESC_DATA_BW(txdesc, value)
+#define GET_TX_DESC_DATA_BW_8198F(txdesc) GET_TX_DESC_DATA_BW(txdesc)
+#define SET_TX_DESC_DATA_SHORT_8198F(txdesc, value)                            \
+	SET_TX_DESC_DATA_SHORT(txdesc, value)
+#define GET_TX_DESC_DATA_SHORT_8198F(txdesc) GET_TX_DESC_DATA_SHORT(txdesc)
+#define SET_TX_DESC_DATA_SC_8198F(txdesc, value)                               \
+	SET_TX_DESC_DATA_SC(txdesc, value)
+#define GET_TX_DESC_DATA_SC_8198F(txdesc) GET_TX_DESC_DATA_SC(txdesc)
+
+/*TXDESC_WORD6*/
+
+#define SET_TX_DESC_ANT_MAPD_8198F(txdesc, value)                              \
+	SET_TX_DESC_ANT_MAPD_V1(txdesc, value)
+#define GET_TX_DESC_ANT_MAPD_8198F(txdesc) GET_TX_DESC_ANT_MAPD_V1(txdesc)
+#define SET_TX_DESC_ANT_MAPC_8198F(txdesc, value)                              \
+	SET_TX_DESC_ANT_MAPC_V1(txdesc, value)
+#define GET_TX_DESC_ANT_MAPC_8198F(txdesc) GET_TX_DESC_ANT_MAPC_V1(txdesc)
+#define SET_TX_DESC_ANT_MAPB_8198F(txdesc, value)                              \
+	SET_TX_DESC_ANT_MAPB_V1(txdesc, value)
+#define GET_TX_DESC_ANT_MAPB_8198F(txdesc) GET_TX_DESC_ANT_MAPB_V1(txdesc)
+#define SET_TX_DESC_ANT_MAPA_8198F(txdesc, value)                              \
+	SET_TX_DESC_ANT_MAPA_V1(txdesc, value)
+#define GET_TX_DESC_ANT_MAPA_8198F(txdesc) GET_TX_DESC_ANT_MAPA_V1(txdesc)
+#define SET_TX_DESC_ANTSEL_B_8198F(txdesc, value)                              \
+	SET_TX_DESC_ANTSEL_B_V1(txdesc, value)
+#define GET_TX_DESC_ANTSEL_B_8198F(txdesc) GET_TX_DESC_ANTSEL_B_V1(txdesc)
+#define SET_TX_DESC_ANTSEL_A_8198F(txdesc, value)                              \
+	SET_TX_DESC_ANTSEL_A_V1(txdesc, value)
+#define GET_TX_DESC_ANTSEL_A_8198F(txdesc) GET_TX_DESC_ANTSEL_A_V1(txdesc)
+#define SET_TX_DESC_MBSSID_8198F(txdesc, value)                                \
+	SET_TX_DESC_MBSSID(txdesc, value)
+#define GET_TX_DESC_MBSSID_8198F(txdesc) GET_TX_DESC_MBSSID(txdesc)
+#define SET_TX_DESC_SWPS_SEQ_8198F(txdesc, value)                              \
+	SET_TX_DESC_SWPS_SEQ(txdesc, value)
+#define GET_TX_DESC_SWPS_SEQ_8198F(txdesc) GET_TX_DESC_SWPS_SEQ(txdesc)
+
+/*TXDESC_WORD7*/
+
+#define SET_TX_DESC_DMA_TXAGG_NUM_8198F(txdesc, value)                         \
+	SET_TX_DESC_DMA_TXAGG_NUM(txdesc, value)
+#define GET_TX_DESC_DMA_TXAGG_NUM_8198F(txdesc)                                \
+	GET_TX_DESC_DMA_TXAGG_NUM(txdesc)
+#define SET_TX_DESC_FINAL_DATA_RATE_8198F(txdesc, value)                       \
+	SET_TX_DESC_FINAL_DATA_RATE(txdesc, value)
+#define GET_TX_DESC_FINAL_DATA_RATE_8198F(txdesc)                              \
+	GET_TX_DESC_FINAL_DATA_RATE(txdesc)
+#define SET_TX_DESC_NTX_MAP_8198F(txdesc, value)                               \
+	SET_TX_DESC_NTX_MAP(txdesc, value)
+#define GET_TX_DESC_NTX_MAP_8198F(txdesc) GET_TX_DESC_NTX_MAP(txdesc)
+#define SET_TX_DESC_ANTSEL_EN_8198F(txdesc, value)                             \
+	SET_TX_DESC_ANTSEL_EN(txdesc, value)
+#define GET_TX_DESC_ANTSEL_EN_8198F(txdesc) GET_TX_DESC_ANTSEL_EN(txdesc)
+#define SET_TX_DESC_MBSSID_EX_8198F(txdesc, value)                             \
+	SET_TX_DESC_MBSSID_EX(txdesc, value)
+#define GET_TX_DESC_MBSSID_EX_8198F(txdesc) GET_TX_DESC_MBSSID_EX(txdesc)
+#define SET_TX_DESC_TX_BUFF_SIZE_8198F(txdesc, value)                          \
+	SET_TX_DESC_TX_BUFF_SIZE(txdesc, value)
+#define GET_TX_DESC_TX_BUFF_SIZE_8198F(txdesc) GET_TX_DESC_TX_BUFF_SIZE(txdesc)
+#define SET_TX_DESC_TXDESC_CHECKSUM_8198F(txdesc, value)                       \
+	SET_TX_DESC_TXDESC_CHECKSUM(txdesc, value)
+#define GET_TX_DESC_TXDESC_CHECKSUM_8198F(txdesc)                              \
+	GET_TX_DESC_TXDESC_CHECKSUM(txdesc)
+#define SET_TX_DESC_TIMESTAMP_8198F(txdesc, value)                             \
+	SET_TX_DESC_TIMESTAMP(txdesc, value)
+#define GET_TX_DESC_TIMESTAMP_8198F(txdesc) GET_TX_DESC_TIMESTAMP(txdesc)
+
+/*TXDESC_WORD8*/
+
+#define SET_TX_DESC_TXWIFI_CP_8198F(txdesc, value)                             \
+	SET_TX_DESC_TXWIFI_CP(txdesc, value)
+#define GET_TX_DESC_TXWIFI_CP_8198F(txdesc) GET_TX_DESC_TXWIFI_CP(txdesc)
+#define SET_TX_DESC_MAC_CP_8198F(txdesc, value)                                \
+	SET_TX_DESC_MAC_CP(txdesc, value)
+#define GET_TX_DESC_MAC_CP_8198F(txdesc) GET_TX_DESC_MAC_CP(txdesc)
+#define SET_TX_DESC_STW_PKTRE_DIS_8198F(txdesc, value)                         \
+	SET_TX_DESC_STW_PKTRE_DIS(txdesc, value)
+#define GET_TX_DESC_STW_PKTRE_DIS_8198F(txdesc)                                \
+	GET_TX_DESC_STW_PKTRE_DIS(txdesc)
+#define SET_TX_DESC_STW_RB_DIS_8198F(txdesc, value)                            \
+	SET_TX_DESC_STW_RB_DIS(txdesc, value)
+#define GET_TX_DESC_STW_RB_DIS_8198F(txdesc) GET_TX_DESC_STW_RB_DIS(txdesc)
+#define SET_TX_DESC_STW_RATE_DIS_8198F(txdesc, value)                          \
+	SET_TX_DESC_STW_RATE_DIS(txdesc, value)
+#define GET_TX_DESC_STW_RATE_DIS_8198F(txdesc) GET_TX_DESC_STW_RATE_DIS(txdesc)
+#define SET_TX_DESC_STW_ANT_DIS_8198F(txdesc, value)                           \
+	SET_TX_DESC_STW_ANT_DIS(txdesc, value)
+#define GET_TX_DESC_STW_ANT_DIS_8198F(txdesc) GET_TX_DESC_STW_ANT_DIS(txdesc)
+#define SET_TX_DESC_STW_EN_8198F(txdesc, value)                                \
+	SET_TX_DESC_STW_EN(txdesc, value)
+#define GET_TX_DESC_STW_EN_8198F(txdesc) GET_TX_DESC_STW_EN(txdesc)
+#define SET_TX_DESC_SMH_EN_8198F(txdesc, value)                                \
+	SET_TX_DESC_SMH_EN(txdesc, value)
+#define GET_TX_DESC_SMH_EN_8198F(txdesc) GET_TX_DESC_SMH_EN(txdesc)
+#define SET_TX_DESC_TAILPAGE_L_8198F(txdesc, value)                            \
+	SET_TX_DESC_TAILPAGE_L(txdesc, value)
+#define GET_TX_DESC_TAILPAGE_L_8198F(txdesc) GET_TX_DESC_TAILPAGE_L(txdesc)
+#define SET_TX_DESC_SDIO_DMASEQ_8198F(txdesc, value)                           \
+	SET_TX_DESC_SDIO_DMASEQ(txdesc, value)
+#define GET_TX_DESC_SDIO_DMASEQ_8198F(txdesc) GET_TX_DESC_SDIO_DMASEQ(txdesc)
+#define SET_TX_DESC_NEXTHEADPAGE_L_8198F(txdesc, value)                        \
+	SET_TX_DESC_NEXTHEADPAGE_L(txdesc, value)
+#define GET_TX_DESC_NEXTHEADPAGE_L_8198F(txdesc)                               \
+	GET_TX_DESC_NEXTHEADPAGE_L(txdesc)
+#define SET_TX_DESC_EN_HWSEQ_8198F(txdesc, value)                              \
+	SET_TX_DESC_EN_HWSEQ(txdesc, value)
+#define GET_TX_DESC_EN_HWSEQ_8198F(txdesc) GET_TX_DESC_EN_HWSEQ(txdesc)
+#define SET_TX_DESC_EN_HWEXSEQ_8198F(txdesc, value)                            \
+	SET_TX_DESC_EN_HWEXSEQ(txdesc, value)
+#define GET_TX_DESC_EN_HWEXSEQ_8198F(txdesc) GET_TX_DESC_EN_HWEXSEQ(txdesc)
+#define SET_TX_DESC_DATA_RC_8198F(txdesc, value)                               \
+	SET_TX_DESC_DATA_RC(txdesc, value)
+#define GET_TX_DESC_DATA_RC_8198F(txdesc) GET_TX_DESC_DATA_RC(txdesc)
+#define SET_TX_DESC_BAR_RTY_TH_8198F(txdesc, value)                            \
+	SET_TX_DESC_BAR_RTY_TH(txdesc, value)
+#define GET_TX_DESC_BAR_RTY_TH_8198F(txdesc) GET_TX_DESC_BAR_RTY_TH(txdesc)
+#define SET_TX_DESC_RTS_RC_8198F(txdesc, value)                                \
+	SET_TX_DESC_RTS_RC(txdesc, value)
+#define GET_TX_DESC_RTS_RC_8198F(txdesc) GET_TX_DESC_RTS_RC(txdesc)
+
+/*TXDESC_WORD9*/
+
+#define SET_TX_DESC_TAILPAGE_H_8198F(txdesc, value)                            \
+	SET_TX_DESC_TAILPAGE_H(txdesc, value)
+#define GET_TX_DESC_TAILPAGE_H_8198F(txdesc) GET_TX_DESC_TAILPAGE_H(txdesc)
+#define SET_TX_DESC_NEXTHEADPAGE_H_8198F(txdesc, value)                        \
+	SET_TX_DESC_NEXTHEADPAGE_H(txdesc, value)
+#define GET_TX_DESC_NEXTHEADPAGE_H_8198F(txdesc)                               \
+	GET_TX_DESC_NEXTHEADPAGE_H(txdesc)
+#define SET_TX_DESC_SW_SEQ_8198F(txdesc, value)                                \
+	SET_TX_DESC_SW_SEQ(txdesc, value)
+#define GET_TX_DESC_SW_SEQ_8198F(txdesc) GET_TX_DESC_SW_SEQ(txdesc)
+#define SET_TX_DESC_TXBF_PATH_8198F(txdesc, value)                             \
+	SET_TX_DESC_TXBF_PATH(txdesc, value)
+#define GET_TX_DESC_TXBF_PATH_8198F(txdesc) GET_TX_DESC_TXBF_PATH(txdesc)
+#define SET_TX_DESC_PADDING_LEN_8198F(txdesc, value)                           \
+	SET_TX_DESC_PADDING_LEN(txdesc, value)
+#define GET_TX_DESC_PADDING_LEN_8198F(txdesc) GET_TX_DESC_PADDING_LEN(txdesc)
+#define SET_TX_DESC_GROUP_BIT_IE_OFFSET_8198F(txdesc, value)                   \
+	SET_TX_DESC_GROUP_BIT_IE_OFFSET(txdesc, value)
+#define GET_TX_DESC_GROUP_BIT_IE_OFFSET_8198F(txdesc)                          \
+	GET_TX_DESC_GROUP_BIT_IE_OFFSET(txdesc)
+
+/*WORD10*/
+
+#endif
+
+#if (HALMAC_8822C_SUPPORT)
+
+/*TXDESC_WORD0*/
+
+#define SET_TX_DESC_DISQSELSEQ_8822C(txdesc, value)                            \
+	SET_TX_DESC_DISQSELSEQ(txdesc, value)
+#define GET_TX_DESC_DISQSELSEQ_8822C(txdesc) GET_TX_DESC_DISQSELSEQ(txdesc)
+#define SET_TX_DESC_GF_8822C(txdesc, value) SET_TX_DESC_GF(txdesc, value)
+#define GET_TX_DESC_GF_8822C(txdesc) GET_TX_DESC_GF(txdesc)
+#define SET_TX_DESC_NO_ACM_8822C(txdesc, value)                                \
+	SET_TX_DESC_NO_ACM(txdesc, value)
+#define GET_TX_DESC_NO_ACM_8822C(txdesc) GET_TX_DESC_NO_ACM(txdesc)
+#define SET_TX_DESC_BCNPKT_TSF_CTRL_8822C(txdesc, value)                       \
+	SET_TX_DESC_BCNPKT_TSF_CTRL(txdesc, value)
+#define GET_TX_DESC_BCNPKT_TSF_CTRL_8822C(txdesc)                              \
+	GET_TX_DESC_BCNPKT_TSF_CTRL(txdesc)
+#define SET_TX_DESC_AMSDU_PAD_EN_8822C(txdesc, value)                          \
+	SET_TX_DESC_AMSDU_PAD_EN(txdesc, value)
+#define GET_TX_DESC_AMSDU_PAD_EN_8822C(txdesc) GET_TX_DESC_AMSDU_PAD_EN(txdesc)
+#define SET_TX_DESC_LS_8822C(txdesc, value) SET_TX_DESC_LS(txdesc, value)
+#define GET_TX_DESC_LS_8822C(txdesc) GET_TX_DESC_LS(txdesc)
+#define SET_TX_DESC_HTC_8822C(txdesc, value) SET_TX_DESC_HTC(txdesc, value)
+#define GET_TX_DESC_HTC_8822C(txdesc) GET_TX_DESC_HTC(txdesc)
+#define SET_TX_DESC_BMC_8822C(txdesc, value) SET_TX_DESC_BMC(txdesc, value)
+#define GET_TX_DESC_BMC_8822C(txdesc) GET_TX_DESC_BMC(txdesc)
+#define SET_TX_DESC_OFFSET_8822C(txdesc, value)                                \
+	SET_TX_DESC_OFFSET(txdesc, value)
+#define GET_TX_DESC_OFFSET_8822C(txdesc) GET_TX_DESC_OFFSET(txdesc)
+#define SET_TX_DESC_TXPKTSIZE_8822C(txdesc, value)                             \
+	SET_TX_DESC_TXPKTSIZE(txdesc, value)
+#define GET_TX_DESC_TXPKTSIZE_8822C(txdesc) GET_TX_DESC_TXPKTSIZE(txdesc)
+
+/*WORD1*/
+
+#define SET_TX_DESC_MOREDATA_8822C(txdesc, value)                              \
+	SET_TX_DESC_MOREDATA(txdesc, value)
+#define GET_TX_DESC_MOREDATA_8822C(txdesc) GET_TX_DESC_MOREDATA(txdesc)
+#define SET_TX_DESC_PKT_OFFSET_8822C(txdesc, value)                            \
+	SET_TX_DESC_PKT_OFFSET(txdesc, value)
+#define GET_TX_DESC_PKT_OFFSET_8822C(txdesc) GET_TX_DESC_PKT_OFFSET(txdesc)
+#define SET_TX_DESC_SEC_TYPE_8822C(txdesc, value)                              \
+	SET_TX_DESC_SEC_TYPE(txdesc, value)
+#define GET_TX_DESC_SEC_TYPE_8822C(txdesc) GET_TX_DESC_SEC_TYPE(txdesc)
+#define SET_TX_DESC_EN_DESC_ID_8822C(txdesc, value)                            \
+	SET_TX_DESC_EN_DESC_ID(txdesc, value)
+#define GET_TX_DESC_EN_DESC_ID_8822C(txdesc) GET_TX_DESC_EN_DESC_ID(txdesc)
+#define SET_TX_DESC_RATE_ID_8822C(txdesc, value)                               \
+	SET_TX_DESC_RATE_ID(txdesc, value)
+#define GET_TX_DESC_RATE_ID_8822C(txdesc) GET_TX_DESC_RATE_ID(txdesc)
+#define SET_TX_DESC_PIFS_8822C(txdesc, value) SET_TX_DESC_PIFS(txdesc, value)
+#define GET_TX_DESC_PIFS_8822C(txdesc) GET_TX_DESC_PIFS(txdesc)
+#define SET_TX_DESC_LSIG_TXOP_EN_8822C(txdesc, value)                          \
+	SET_TX_DESC_LSIG_TXOP_EN(txdesc, value)
+#define GET_TX_DESC_LSIG_TXOP_EN_8822C(txdesc) GET_TX_DESC_LSIG_TXOP_EN(txdesc)
+#define SET_TX_DESC_RD_NAV_EXT_8822C(txdesc, value)                            \
+	SET_TX_DESC_RD_NAV_EXT(txdesc, value)
+#define GET_TX_DESC_RD_NAV_EXT_8822C(txdesc) GET_TX_DESC_RD_NAV_EXT(txdesc)
+#define SET_TX_DESC_QSEL_8822C(txdesc, value) SET_TX_DESC_QSEL(txdesc, value)
+#define GET_TX_DESC_QSEL_8822C(txdesc) GET_TX_DESC_QSEL(txdesc)
+#define SET_TX_DESC_MACID_8822C(txdesc, value) SET_TX_DESC_MACID(txdesc, value)
+#define GET_TX_DESC_MACID_8822C(txdesc) GET_TX_DESC_MACID(txdesc)
+
+/*TXDESC_WORD2*/
+
+#define SET_TX_DESC_HW_AES_IV_8822C(txdesc, value)                             \
+	SET_TX_DESC_HW_AES_IV(txdesc, value)
+#define GET_TX_DESC_HW_AES_IV_8822C(txdesc) GET_TX_DESC_HW_AES_IV(txdesc)
+#define SET_TX_DESC_FTM_EN_8822C(txdesc, value)                                \
+	SET_TX_DESC_FTM_EN(txdesc, value)
+#define GET_TX_DESC_FTM_EN_8822C(txdesc) GET_TX_DESC_FTM_EN(txdesc)
+#define SET_TX_DESC_G_ID_8822C(txdesc, value) SET_TX_DESC_G_ID(txdesc, value)
+#define GET_TX_DESC_G_ID_8822C(txdesc) GET_TX_DESC_G_ID(txdesc)
+#define SET_TX_DESC_BT_NULL_8822C(txdesc, value)                               \
+	SET_TX_DESC_BT_NULL(txdesc, value)
+#define GET_TX_DESC_BT_NULL_8822C(txdesc) GET_TX_DESC_BT_NULL(txdesc)
+#define SET_TX_DESC_AMPDU_DENSITY_8822C(txdesc, value)                         \
+	SET_TX_DESC_AMPDU_DENSITY(txdesc, value)
+#define GET_TX_DESC_AMPDU_DENSITY_8822C(txdesc)                                \
+	GET_TX_DESC_AMPDU_DENSITY(txdesc)
+#define SET_TX_DESC_SPE_RPT_8822C(txdesc, value)                               \
+	SET_TX_DESC_SPE_RPT(txdesc, value)
+#define GET_TX_DESC_SPE_RPT_8822C(txdesc) GET_TX_DESC_SPE_RPT(txdesc)
+#define SET_TX_DESC_RAW_8822C(txdesc, value) SET_TX_DESC_RAW(txdesc, value)
+#define GET_TX_DESC_RAW_8822C(txdesc) GET_TX_DESC_RAW(txdesc)
+#define SET_TX_DESC_MOREFRAG_8822C(txdesc, value)                              \
+	SET_TX_DESC_MOREFRAG(txdesc, value)
+#define GET_TX_DESC_MOREFRAG_8822C(txdesc) GET_TX_DESC_MOREFRAG(txdesc)
+#define SET_TX_DESC_BK_8822C(txdesc, value) SET_TX_DESC_BK(txdesc, value)
+#define GET_TX_DESC_BK_8822C(txdesc) GET_TX_DESC_BK(txdesc)
+#define SET_TX_DESC_NULL_1_8822C(txdesc, value)                                \
+	SET_TX_DESC_NULL_1(txdesc, value)
+#define GET_TX_DESC_NULL_1_8822C(txdesc) GET_TX_DESC_NULL_1(txdesc)
+#define SET_TX_DESC_NULL_0_8822C(txdesc, value)                                \
+	SET_TX_DESC_NULL_0(txdesc, value)
+#define GET_TX_DESC_NULL_0_8822C(txdesc) GET_TX_DESC_NULL_0(txdesc)
+#define SET_TX_DESC_RDG_EN_8822C(txdesc, value)                                \
+	SET_TX_DESC_RDG_EN(txdesc, value)
+#define GET_TX_DESC_RDG_EN_8822C(txdesc) GET_TX_DESC_RDG_EN(txdesc)
+#define SET_TX_DESC_AGG_EN_8822C(txdesc, value)                                \
+	SET_TX_DESC_AGG_EN(txdesc, value)
+#define GET_TX_DESC_AGG_EN_8822C(txdesc) GET_TX_DESC_AGG_EN(txdesc)
+#define SET_TX_DESC_CCA_RTS_8822C(txdesc, value)                               \
+	SET_TX_DESC_CCA_RTS(txdesc, value)
+#define GET_TX_DESC_CCA_RTS_8822C(txdesc) GET_TX_DESC_CCA_RTS(txdesc)
+#define SET_TX_DESC_TRI_FRAME_8822C(txdesc, value)                             \
+	SET_TX_DESC_TRI_FRAME(txdesc, value)
+#define GET_TX_DESC_TRI_FRAME_8822C(txdesc) GET_TX_DESC_TRI_FRAME(txdesc)
+#define SET_TX_DESC_P_AID_8822C(txdesc, value) SET_TX_DESC_P_AID(txdesc, value)
+#define GET_TX_DESC_P_AID_8822C(txdesc) GET_TX_DESC_P_AID(txdesc)
+
+/*TXDESC_WORD3*/
+
+#define SET_TX_DESC_AMPDU_MAX_TIME_8822C(txdesc, value)                        \
+	SET_TX_DESC_AMPDU_MAX_TIME(txdesc, value)
+#define GET_TX_DESC_AMPDU_MAX_TIME_8822C(txdesc)                               \
+	GET_TX_DESC_AMPDU_MAX_TIME(txdesc)
+#define SET_TX_DESC_NDPA_8822C(txdesc, value) SET_TX_DESC_NDPA(txdesc, value)
+#define GET_TX_DESC_NDPA_8822C(txdesc) GET_TX_DESC_NDPA(txdesc)
+#define SET_TX_DESC_MAX_AGG_NUM_8822C(txdesc, value)                           \
+	SET_TX_DESC_MAX_AGG_NUM(txdesc, value)
+#define GET_TX_DESC_MAX_AGG_NUM_8822C(txdesc) GET_TX_DESC_MAX_AGG_NUM(txdesc)
+#define SET_TX_DESC_USE_MAX_TIME_EN_8822C(txdesc, value)                       \
+	SET_TX_DESC_USE_MAX_TIME_EN(txdesc, value)
+#define GET_TX_DESC_USE_MAX_TIME_EN_8822C(txdesc)                              \
+	GET_TX_DESC_USE_MAX_TIME_EN(txdesc)
+#define SET_TX_DESC_NAVUSEHDR_8822C(txdesc, value)                             \
+	SET_TX_DESC_NAVUSEHDR(txdesc, value)
+#define GET_TX_DESC_NAVUSEHDR_8822C(txdesc) GET_TX_DESC_NAVUSEHDR(txdesc)
+#define SET_TX_DESC_CHK_EN_8822C(txdesc, value)                                \
+	SET_TX_DESC_CHK_EN(txdesc, value)
+#define GET_TX_DESC_CHK_EN_8822C(txdesc) GET_TX_DESC_CHK_EN(txdesc)
+#define SET_TX_DESC_HW_RTS_EN_8822C(txdesc, value)                             \
+	SET_TX_DESC_HW_RTS_EN(txdesc, value)
+#define GET_TX_DESC_HW_RTS_EN_8822C(txdesc) GET_TX_DESC_HW_RTS_EN(txdesc)
+#define SET_TX_DESC_RTSEN_8822C(txdesc, value) SET_TX_DESC_RTSEN(txdesc, value)
+#define GET_TX_DESC_RTSEN_8822C(txdesc) GET_TX_DESC_RTSEN(txdesc)
+#define SET_TX_DESC_CTS2SELF_8822C(txdesc, value)                              \
+	SET_TX_DESC_CTS2SELF(txdesc, value)
+#define GET_TX_DESC_CTS2SELF_8822C(txdesc) GET_TX_DESC_CTS2SELF(txdesc)
+#define SET_TX_DESC_DISDATAFB_8822C(txdesc, value)                             \
+	SET_TX_DESC_DISDATAFB(txdesc, value)
+#define GET_TX_DESC_DISDATAFB_8822C(txdesc) GET_TX_DESC_DISDATAFB(txdesc)
+#define SET_TX_DESC_DISRTSFB_8822C(txdesc, value)                              \
+	SET_TX_DESC_DISRTSFB(txdesc, value)
+#define GET_TX_DESC_DISRTSFB_8822C(txdesc) GET_TX_DESC_DISRTSFB(txdesc)
+#define SET_TX_DESC_USE_RATE_8822C(txdesc, value)                              \
+	SET_TX_DESC_USE_RATE(txdesc, value)
+#define GET_TX_DESC_USE_RATE_8822C(txdesc) GET_TX_DESC_USE_RATE(txdesc)
+#define SET_TX_DESC_HW_SSN_SEL_8822C(txdesc, value)                            \
+	SET_TX_DESC_HW_SSN_SEL(txdesc, value)
+#define GET_TX_DESC_HW_SSN_SEL_8822C(txdesc) GET_TX_DESC_HW_SSN_SEL(txdesc)
+#define SET_TX_DESC_WHEADER_LEN_8822C(txdesc, value)                           \
+	SET_TX_DESC_WHEADER_LEN(txdesc, value)
+#define GET_TX_DESC_WHEADER_LEN_8822C(txdesc) GET_TX_DESC_WHEADER_LEN(txdesc)
+
+/*TXDESC_WORD4*/
+
+#define SET_TX_DESC_PCTS_MASK_IDX_8822C(txdesc, value)                         \
+	SET_TX_DESC_PCTS_MASK_IDX(txdesc, value)
+#define GET_TX_DESC_PCTS_MASK_IDX_8822C(txdesc)                                \
+	GET_TX_DESC_PCTS_MASK_IDX(txdesc)
+#define SET_TX_DESC_PCTS_EN_8822C(txdesc, value)                               \
+	SET_TX_DESC_PCTS_EN(txdesc, value)
+#define GET_TX_DESC_PCTS_EN_8822C(txdesc) GET_TX_DESC_PCTS_EN(txdesc)
+#define SET_TX_DESC_RTSRATE_8822C(txdesc, value)                               \
+	SET_TX_DESC_RTSRATE(txdesc, value)
+#define GET_TX_DESC_RTSRATE_8822C(txdesc) GET_TX_DESC_RTSRATE(txdesc)
+#define SET_TX_DESC_RTS_DATA_RTY_LMT_8822C(txdesc, value)                      \
+	SET_TX_DESC_RTS_DATA_RTY_LMT(txdesc, value)
+#define GET_TX_DESC_RTS_DATA_RTY_LMT_8822C(txdesc)                             \
+	GET_TX_DESC_RTS_DATA_RTY_LMT(txdesc)
+#define SET_TX_DESC_RTY_LMT_EN_8822C(txdesc, value)                            \
+	SET_TX_DESC_RTY_LMT_EN(txdesc, value)
+#define GET_TX_DESC_RTY_LMT_EN_8822C(txdesc) GET_TX_DESC_RTY_LMT_EN(txdesc)
+#define SET_TX_DESC_RTS_RTY_LOWEST_RATE_8822C(txdesc, value)                   \
+	SET_TX_DESC_RTS_RTY_LOWEST_RATE(txdesc, value)
+#define GET_TX_DESC_RTS_RTY_LOWEST_RATE_8822C(txdesc)                          \
+	GET_TX_DESC_RTS_RTY_LOWEST_RATE(txdesc)
+#define SET_TX_DESC_DATA_RTY_LOWEST_RATE_8822C(txdesc, value)                  \
+	SET_TX_DESC_DATA_RTY_LOWEST_RATE(txdesc, value)
+#define GET_TX_DESC_DATA_RTY_LOWEST_RATE_8822C(txdesc)                         \
+	GET_TX_DESC_DATA_RTY_LOWEST_RATE(txdesc)
+#define SET_TX_DESC_TRY_RATE_8822C(txdesc, value)                              \
+	SET_TX_DESC_TRY_RATE(txdesc, value)
+#define GET_TX_DESC_TRY_RATE_8822C(txdesc) GET_TX_DESC_TRY_RATE(txdesc)
+#define SET_TX_DESC_DATARATE_8822C(txdesc, value)                              \
+	SET_TX_DESC_DATARATE(txdesc, value)
+#define GET_TX_DESC_DATARATE_8822C(txdesc) GET_TX_DESC_DATARATE(txdesc)
+
+/*TXDESC_WORD5*/
+
+#define SET_TX_DESC_POLLUTED_8822C(txdesc, value)                              \
+	SET_TX_DESC_POLLUTED(txdesc, value)
+#define GET_TX_DESC_POLLUTED_8822C(txdesc) GET_TX_DESC_POLLUTED(txdesc)
+#define SET_TX_DESC_ANTSEL_EN_8822C(txdesc, value)                             \
+	SET_TX_DESC_ANTSEL_EN_V1(txdesc, value)
+#define GET_TX_DESC_ANTSEL_EN_8822C(txdesc) GET_TX_DESC_ANTSEL_EN_V1(txdesc)
+#define SET_TX_DESC_TXPWR_OFSET_TYPE_8822C(txdesc, value)                      \
+	SET_TX_DESC_TXPWR_OFSET_TYPE(txdesc, value)
+#define GET_TX_DESC_TXPWR_OFSET_TYPE_8822C(txdesc)                             \
+	GET_TX_DESC_TXPWR_OFSET_TYPE(txdesc)
+#define SET_TX_DESC_TX_ANT_8822C(txdesc, value)                                \
+	SET_TX_DESC_TX_ANT(txdesc, value)
+#define GET_TX_DESC_TX_ANT_8822C(txdesc) GET_TX_DESC_TX_ANT(txdesc)
+#define SET_TX_DESC_PORT_ID_8822C(txdesc, value)                               \
+	SET_TX_DESC_PORT_ID(txdesc, value)
+#define GET_TX_DESC_PORT_ID_8822C(txdesc) GET_TX_DESC_PORT_ID(txdesc)
+#define SET_TX_DESC_MULTIPLE_PORT_8822C(txdesc, value)                         \
+	SET_TX_DESC_MULTIPLE_PORT(txdesc, value)
+#define GET_TX_DESC_MULTIPLE_PORT_8822C(txdesc)                                \
+	GET_TX_DESC_MULTIPLE_PORT(txdesc)
+#define SET_TX_DESC_SIGNALING_TAPKT_EN_8822C(txdesc, value)                    \
+	SET_TX_DESC_SIGNALING_TAPKT_EN(txdesc, value)
+#define GET_TX_DESC_SIGNALING_TAPKT_EN_8822C(txdesc)                           \
+	GET_TX_DESC_SIGNALING_TAPKT_EN(txdesc)
+#define SET_TX_DESC_SIGNALING_TA_PKT_SC_8822C(txdesc, value)                   \
+	SET_TX_DESC_SIGNALING_TA_PKT_SC(txdesc, value)
+#define GET_TX_DESC_SIGNALING_TA_PKT_SC_8822C(txdesc)                          \
+	GET_TX_DESC_SIGNALING_TA_PKT_SC(txdesc)
+#define SET_TX_DESC_RTS_SHORT_8822C(txdesc, value)                             \
+	SET_TX_DESC_RTS_SHORT(txdesc, value)
+#define GET_TX_DESC_RTS_SHORT_8822C(txdesc) GET_TX_DESC_RTS_SHORT(txdesc)
+#define SET_TX_DESC_VCS_STBC_8822C(txdesc, value)                              \
+	SET_TX_DESC_VCS_STBC(txdesc, value)
+#define GET_TX_DESC_VCS_STBC_8822C(txdesc) GET_TX_DESC_VCS_STBC(txdesc)
+#define SET_TX_DESC_DATA_STBC_8822C(txdesc, value)                             \
+	SET_TX_DESC_DATA_STBC(txdesc, value)
+#define GET_TX_DESC_DATA_STBC_8822C(txdesc) GET_TX_DESC_DATA_STBC(txdesc)
+#define SET_TX_DESC_DATA_LDPC_8822C(txdesc, value)                             \
+	SET_TX_DESC_DATA_LDPC(txdesc, value)
+#define GET_TX_DESC_DATA_LDPC_8822C(txdesc) GET_TX_DESC_DATA_LDPC(txdesc)
+#define SET_TX_DESC_DATA_BW_8822C(txdesc, value)                               \
+	SET_TX_DESC_DATA_BW(txdesc, value)
+#define GET_TX_DESC_DATA_BW_8822C(txdesc) GET_TX_DESC_DATA_BW(txdesc)
+#define SET_TX_DESC_DATA_SHORT_8822C(txdesc, value)                            \
+	SET_TX_DESC_DATA_SHORT(txdesc, value)
+#define GET_TX_DESC_DATA_SHORT_8822C(txdesc) GET_TX_DESC_DATA_SHORT(txdesc)
+#define SET_TX_DESC_DATA_SC_8822C(txdesc, value)                               \
+	SET_TX_DESC_DATA_SC(txdesc, value)
+#define GET_TX_DESC_DATA_SC_8822C(txdesc) GET_TX_DESC_DATA_SC(txdesc)
+
+/*TXDESC_WORD6*/
+
+#define SET_TX_DESC_ANTSEL_D_8822C(txdesc, value)                              \
+	SET_TX_DESC_ANTSEL_D(txdesc, value)
+#define GET_TX_DESC_ANTSEL_D_8822C(txdesc) GET_TX_DESC_ANTSEL_D(txdesc)
+#define SET_TX_DESC_ANT_MAPD_8822C(txdesc, value)                              \
+	SET_TX_DESC_ANT_MAPD(txdesc, value)
+#define GET_TX_DESC_ANT_MAPD_8822C(txdesc) GET_TX_DESC_ANT_MAPD(txdesc)
+#define SET_TX_DESC_ANT_MAPC_8822C(txdesc, value)                              \
+	SET_TX_DESC_ANT_MAPC(txdesc, value)
+#define GET_TX_DESC_ANT_MAPC_8822C(txdesc) GET_TX_DESC_ANT_MAPC(txdesc)
+#define SET_TX_DESC_ANT_MAPB_8822C(txdesc, value)                              \
+	SET_TX_DESC_ANT_MAPB(txdesc, value)
+#define GET_TX_DESC_ANT_MAPB_8822C(txdesc) GET_TX_DESC_ANT_MAPB(txdesc)
+#define SET_TX_DESC_ANT_MAPA_8822C(txdesc, value)                              \
+	SET_TX_DESC_ANT_MAPA(txdesc, value)
+#define GET_TX_DESC_ANT_MAPA_8822C(txdesc) GET_TX_DESC_ANT_MAPA(txdesc)
+#define SET_TX_DESC_ANTSEL_C_8822C(txdesc, value)                              \
+	SET_TX_DESC_ANTSEL_C(txdesc, value)
+#define GET_TX_DESC_ANTSEL_C_8822C(txdesc) GET_TX_DESC_ANTSEL_C(txdesc)
+#define SET_TX_DESC_ANTSEL_B_8822C(txdesc, value)                              \
+	SET_TX_DESC_ANTSEL_B(txdesc, value)
+#define GET_TX_DESC_ANTSEL_B_8822C(txdesc) GET_TX_DESC_ANTSEL_B(txdesc)
+#define SET_TX_DESC_ANTSEL_A_8822C(txdesc, value)                              \
+	SET_TX_DESC_ANTSEL_A(txdesc, value)
+#define GET_TX_DESC_ANTSEL_A_8822C(txdesc) GET_TX_DESC_ANTSEL_A(txdesc)
+#define SET_TX_DESC_MBSSID_8822C(txdesc, value)                                \
+	SET_TX_DESC_MBSSID(txdesc, value)
+#define GET_TX_DESC_MBSSID_8822C(txdesc) GET_TX_DESC_MBSSID(txdesc)
+#define SET_TX_DESC_SW_DEFINE_8822C(txdesc, value)                             \
+	SET_TX_DESC_SW_DEFINE(txdesc, value)
+#define GET_TX_DESC_SW_DEFINE_8822C(txdesc) GET_TX_DESC_SW_DEFINE(txdesc)
+
+/*TXDESC_WORD7*/
+
+#define SET_TX_DESC_DMA_TXAGG_NUM_8822C(txdesc, value)                         \
+	SET_TX_DESC_DMA_TXAGG_NUM(txdesc, value)
+#define GET_TX_DESC_DMA_TXAGG_NUM_8822C(txdesc)                                \
+	GET_TX_DESC_DMA_TXAGG_NUM(txdesc)
+#define SET_TX_DESC_FINAL_DATA_RATE_8822C(txdesc, value)                       \
+	SET_TX_DESC_FINAL_DATA_RATE(txdesc, value)
+#define GET_TX_DESC_FINAL_DATA_RATE_8822C(txdesc)                              \
+	GET_TX_DESC_FINAL_DATA_RATE(txdesc)
+#define SET_TX_DESC_NTX_MAP_8822C(txdesc, value)                               \
+	SET_TX_DESC_NTX_MAP(txdesc, value)
+#define GET_TX_DESC_NTX_MAP_8822C(txdesc) GET_TX_DESC_NTX_MAP(txdesc)
+#define SET_TX_DESC_TX_BUFF_SIZE_8822C(txdesc, value)                          \
+	SET_TX_DESC_TX_BUFF_SIZE(txdesc, value)
+#define GET_TX_DESC_TX_BUFF_SIZE_8822C(txdesc) GET_TX_DESC_TX_BUFF_SIZE(txdesc)
+#define SET_TX_DESC_TXDESC_CHECKSUM_8822C(txdesc, value)                       \
+	SET_TX_DESC_TXDESC_CHECKSUM(txdesc, value)
+#define GET_TX_DESC_TXDESC_CHECKSUM_8822C(txdesc)                              \
+	GET_TX_DESC_TXDESC_CHECKSUM(txdesc)
+#define SET_TX_DESC_TIMESTAMP_8822C(txdesc, value)                             \
+	SET_TX_DESC_TIMESTAMP(txdesc, value)
+#define GET_TX_DESC_TIMESTAMP_8822C(txdesc) GET_TX_DESC_TIMESTAMP(txdesc)
+
+/*TXDESC_WORD8*/
+
+#define SET_TX_DESC_TXWIFI_CP_8822C(txdesc, value)                             \
+	SET_TX_DESC_TXWIFI_CP(txdesc, value)
+#define GET_TX_DESC_TXWIFI_CP_8822C(txdesc) GET_TX_DESC_TXWIFI_CP(txdesc)
+#define SET_TX_DESC_MAC_CP_8822C(txdesc, value)                                \
+	SET_TX_DESC_MAC_CP(txdesc, value)
+#define GET_TX_DESC_MAC_CP_8822C(txdesc) GET_TX_DESC_MAC_CP(txdesc)
+#define SET_TX_DESC_STW_PKTRE_DIS_8822C(txdesc, value)                         \
+	SET_TX_DESC_STW_PKTRE_DIS(txdesc, value)
+#define GET_TX_DESC_STW_PKTRE_DIS_8822C(txdesc)                                \
+	GET_TX_DESC_STW_PKTRE_DIS(txdesc)
+#define SET_TX_DESC_STW_RB_DIS_8822C(txdesc, value)                            \
+	SET_TX_DESC_STW_RB_DIS(txdesc, value)
+#define GET_TX_DESC_STW_RB_DIS_8822C(txdesc) GET_TX_DESC_STW_RB_DIS(txdesc)
+#define SET_TX_DESC_STW_RATE_DIS_8822C(txdesc, value)                          \
+	SET_TX_DESC_STW_RATE_DIS(txdesc, value)
+#define GET_TX_DESC_STW_RATE_DIS_8822C(txdesc) GET_TX_DESC_STW_RATE_DIS(txdesc)
+#define SET_TX_DESC_STW_ANT_DIS_8822C(txdesc, value)                           \
+	SET_TX_DESC_STW_ANT_DIS(txdesc, value)
+#define GET_TX_DESC_STW_ANT_DIS_8822C(txdesc) GET_TX_DESC_STW_ANT_DIS(txdesc)
+#define SET_TX_DESC_STW_EN_8822C(txdesc, value)                                \
+	SET_TX_DESC_STW_EN(txdesc, value)
+#define GET_TX_DESC_STW_EN_8822C(txdesc) GET_TX_DESC_STW_EN(txdesc)
+#define SET_TX_DESC_SMH_EN_8822C(txdesc, value)                                \
+	SET_TX_DESC_SMH_EN(txdesc, value)
+#define GET_TX_DESC_SMH_EN_8822C(txdesc) GET_TX_DESC_SMH_EN(txdesc)
+#define SET_TX_DESC_TAILPAGE_L_8822C(txdesc, value)                            \
+	SET_TX_DESC_TAILPAGE_L(txdesc, value)
+#define GET_TX_DESC_TAILPAGE_L_8822C(txdesc) GET_TX_DESC_TAILPAGE_L(txdesc)
+#define SET_TX_DESC_SDIO_DMASEQ_8822C(txdesc, value)                           \
+	SET_TX_DESC_SDIO_DMASEQ(txdesc, value)
+#define GET_TX_DESC_SDIO_DMASEQ_8822C(txdesc) GET_TX_DESC_SDIO_DMASEQ(txdesc)
+#define SET_TX_DESC_NEXTHEADPAGE_L_8822C(txdesc, value)                        \
+	SET_TX_DESC_NEXTHEADPAGE_L(txdesc, value)
+#define GET_TX_DESC_NEXTHEADPAGE_L_8822C(txdesc)                               \
+	GET_TX_DESC_NEXTHEADPAGE_L(txdesc)
+#define SET_TX_DESC_EN_HWSEQ_8822C(txdesc, value)                              \
+	SET_TX_DESC_EN_HWSEQ(txdesc, value)
+#define GET_TX_DESC_EN_HWSEQ_8822C(txdesc) GET_TX_DESC_EN_HWSEQ(txdesc)
+#define SET_TX_DESC_EN_HWEXSEQ_8822C(txdesc, value)                            \
+	SET_TX_DESC_EN_HWEXSEQ(txdesc, value)
+#define GET_TX_DESC_EN_HWEXSEQ_8822C(txdesc) GET_TX_DESC_EN_HWEXSEQ(txdesc)
+#define SET_TX_DESC_DATA_RC_8822C(txdesc, value)                               \
+	SET_TX_DESC_DATA_RC(txdesc, value)
+#define GET_TX_DESC_DATA_RC_8822C(txdesc) GET_TX_DESC_DATA_RC(txdesc)
+#define SET_TX_DESC_BAR_RTY_TH_8822C(txdesc, value)                            \
+	SET_TX_DESC_BAR_RTY_TH(txdesc, value)
+#define GET_TX_DESC_BAR_RTY_TH_8822C(txdesc) GET_TX_DESC_BAR_RTY_TH(txdesc)
+#define SET_TX_DESC_RTS_RC_8822C(txdesc, value)                                \
+	SET_TX_DESC_RTS_RC(txdesc, value)
+#define GET_TX_DESC_RTS_RC_8822C(txdesc) GET_TX_DESC_RTS_RC(txdesc)
+
+/*TXDESC_WORD9*/
+
+#define SET_TX_DESC_TAILPAGE_H_8822C(txdesc, value)                            \
+	SET_TX_DESC_TAILPAGE_H(txdesc, value)
+#define GET_TX_DESC_TAILPAGE_H_8822C(txdesc) GET_TX_DESC_TAILPAGE_H(txdesc)
+#define SET_TX_DESC_NEXTHEADPAGE_H_8822C(txdesc, value)                        \
+	SET_TX_DESC_NEXTHEADPAGE_H(txdesc, value)
+#define GET_TX_DESC_NEXTHEADPAGE_H_8822C(txdesc)                               \
+	GET_TX_DESC_NEXTHEADPAGE_H(txdesc)
+#define SET_TX_DESC_SW_SEQ_8822C(txdesc, value)                                \
+	SET_TX_DESC_SW_SEQ(txdesc, value)
+#define GET_TX_DESC_SW_SEQ_8822C(txdesc) GET_TX_DESC_SW_SEQ(txdesc)
+#define SET_TX_DESC_TXBF_PATH_8822C(txdesc, value)                             \
+	SET_TX_DESC_TXBF_PATH(txdesc, value)
+#define GET_TX_DESC_TXBF_PATH_8822C(txdesc) GET_TX_DESC_TXBF_PATH(txdesc)
+#define SET_TX_DESC_PADDING_LEN_8822C(txdesc, value)                           \
+	SET_TX_DESC_PADDING_LEN(txdesc, value)
+#define GET_TX_DESC_PADDING_LEN_8822C(txdesc) GET_TX_DESC_PADDING_LEN(txdesc)
+#define SET_TX_DESC_GROUP_BIT_IE_OFFSET_8822C(txdesc, value)                   \
+	SET_TX_DESC_GROUP_BIT_IE_OFFSET(txdesc, value)
+#define GET_TX_DESC_GROUP_BIT_IE_OFFSET_8822C(txdesc)                          \
+	GET_TX_DESC_GROUP_BIT_IE_OFFSET(txdesc)
+
+/*WORD10*/
+
+#define SET_TX_DESC_MU_DATARATE_8822C(txdesc, value)                           \
+	SET_TX_DESC_MU_DATARATE(txdesc, value)
+#define GET_TX_DESC_MU_DATARATE_8822C(txdesc) GET_TX_DESC_MU_DATARATE(txdesc)
+#define SET_TX_DESC_MU_RC_8822C(txdesc, value) SET_TX_DESC_MU_RC(txdesc, value)
+#define GET_TX_DESC_MU_RC_8822C(txdesc) GET_TX_DESC_MU_RC(txdesc)
+#define SET_TX_DESC_SND_PKT_SEL_8822C(txdesc, value)                           \
+	SET_TX_DESC_SND_PKT_SEL(txdesc, value)
+#define GET_TX_DESC_SND_PKT_SEL_8822C(txdesc) GET_TX_DESC_SND_PKT_SEL(txdesc)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT)
+
+/*TXDESC_WORD0*/
+
+#define SET_TX_DESC_DISQSELSEQ_8812F(txdesc, value)                            \
+	SET_TX_DESC_DISQSELSEQ(txdesc, value)
+#define GET_TX_DESC_DISQSELSEQ_8812F(txdesc) GET_TX_DESC_DISQSELSEQ(txdesc)
+#define SET_TX_DESC_GF_8812F(txdesc, value) SET_TX_DESC_GF(txdesc, value)
+#define GET_TX_DESC_GF_8812F(txdesc) GET_TX_DESC_GF(txdesc)
+#define SET_TX_DESC_NO_ACM_8812F(txdesc, value)                                \
+	SET_TX_DESC_NO_ACM(txdesc, value)
+#define GET_TX_DESC_NO_ACM_8812F(txdesc) GET_TX_DESC_NO_ACM(txdesc)
+#define SET_TX_DESC_BCNPKT_TSF_CTRL_8812F(txdesc, value)                       \
+	SET_TX_DESC_BCNPKT_TSF_CTRL(txdesc, value)
+#define GET_TX_DESC_BCNPKT_TSF_CTRL_8812F(txdesc)                              \
+	GET_TX_DESC_BCNPKT_TSF_CTRL(txdesc)
+#define SET_TX_DESC_AMSDU_PAD_EN_8812F(txdesc, value)                          \
+	SET_TX_DESC_AMSDU_PAD_EN(txdesc, value)
+#define GET_TX_DESC_AMSDU_PAD_EN_8812F(txdesc) GET_TX_DESC_AMSDU_PAD_EN(txdesc)
+#define SET_TX_DESC_LS_8812F(txdesc, value) SET_TX_DESC_LS(txdesc, value)
+#define GET_TX_DESC_LS_8812F(txdesc) GET_TX_DESC_LS(txdesc)
+#define SET_TX_DESC_HTC_8812F(txdesc, value) SET_TX_DESC_HTC(txdesc, value)
+#define GET_TX_DESC_HTC_8812F(txdesc) GET_TX_DESC_HTC(txdesc)
+#define SET_TX_DESC_BMC_8812F(txdesc, value) SET_TX_DESC_BMC(txdesc, value)
+#define GET_TX_DESC_BMC_8812F(txdesc) GET_TX_DESC_BMC(txdesc)
+#define SET_TX_DESC_OFFSET_8812F(txdesc, value)                                \
+	SET_TX_DESC_OFFSET(txdesc, value)
+#define GET_TX_DESC_OFFSET_8812F(txdesc) GET_TX_DESC_OFFSET(txdesc)
+#define SET_TX_DESC_TXPKTSIZE_8812F(txdesc, value)                             \
+	SET_TX_DESC_TXPKTSIZE(txdesc, value)
+#define GET_TX_DESC_TXPKTSIZE_8812F(txdesc) GET_TX_DESC_TXPKTSIZE(txdesc)
+
+/*WORD1*/
+
+#define SET_TX_DESC_MOREDATA_8812F(txdesc, value)                              \
+	SET_TX_DESC_MOREDATA(txdesc, value)
+#define GET_TX_DESC_MOREDATA_8812F(txdesc) GET_TX_DESC_MOREDATA(txdesc)
+#define SET_TX_DESC_PKT_OFFSET_8812F(txdesc, value)                            \
+	SET_TX_DESC_PKT_OFFSET(txdesc, value)
+#define GET_TX_DESC_PKT_OFFSET_8812F(txdesc) GET_TX_DESC_PKT_OFFSET(txdesc)
+#define SET_TX_DESC_SEC_TYPE_8812F(txdesc, value)                              \
+	SET_TX_DESC_SEC_TYPE(txdesc, value)
+#define GET_TX_DESC_SEC_TYPE_8812F(txdesc) GET_TX_DESC_SEC_TYPE(txdesc)
+#define SET_TX_DESC_EN_DESC_ID_8812F(txdesc, value)                            \
+	SET_TX_DESC_EN_DESC_ID(txdesc, value)
+#define GET_TX_DESC_EN_DESC_ID_8812F(txdesc) GET_TX_DESC_EN_DESC_ID(txdesc)
+#define SET_TX_DESC_RATE_ID_8812F(txdesc, value)                               \
+	SET_TX_DESC_RATE_ID(txdesc, value)
+#define GET_TX_DESC_RATE_ID_8812F(txdesc) GET_TX_DESC_RATE_ID(txdesc)
+#define SET_TX_DESC_PIFS_8812F(txdesc, value) SET_TX_DESC_PIFS(txdesc, value)
+#define GET_TX_DESC_PIFS_8812F(txdesc) GET_TX_DESC_PIFS(txdesc)
+#define SET_TX_DESC_LSIG_TXOP_EN_8812F(txdesc, value)                          \
+	SET_TX_DESC_LSIG_TXOP_EN(txdesc, value)
+#define GET_TX_DESC_LSIG_TXOP_EN_8812F(txdesc) GET_TX_DESC_LSIG_TXOP_EN(txdesc)
+#define SET_TX_DESC_RD_NAV_EXT_8812F(txdesc, value)                            \
+	SET_TX_DESC_RD_NAV_EXT(txdesc, value)
+#define GET_TX_DESC_RD_NAV_EXT_8812F(txdesc) GET_TX_DESC_RD_NAV_EXT(txdesc)
+#define SET_TX_DESC_QSEL_8812F(txdesc, value) SET_TX_DESC_QSEL(txdesc, value)
+#define GET_TX_DESC_QSEL_8812F(txdesc) GET_TX_DESC_QSEL(txdesc)
+#define SET_TX_DESC_MACID_8812F(txdesc, value) SET_TX_DESC_MACID(txdesc, value)
+#define GET_TX_DESC_MACID_8812F(txdesc) GET_TX_DESC_MACID(txdesc)
+
+/*TXDESC_WORD2*/
+
+#define SET_TX_DESC_HW_AES_IV_8812F(txdesc, value)                             \
+	SET_TX_DESC_HW_AES_IV(txdesc, value)
+#define GET_TX_DESC_HW_AES_IV_8812F(txdesc) GET_TX_DESC_HW_AES_IV(txdesc)
+#define SET_TX_DESC_FTM_EN_8812F(txdesc, value)                                \
+	SET_TX_DESC_FTM_EN(txdesc, value)
+#define GET_TX_DESC_FTM_EN_8812F(txdesc) GET_TX_DESC_FTM_EN(txdesc)
+#define SET_TX_DESC_G_ID_8812F(txdesc, value) SET_TX_DESC_G_ID(txdesc, value)
+#define GET_TX_DESC_G_ID_8812F(txdesc) GET_TX_DESC_G_ID(txdesc)
+#define SET_TX_DESC_BT_NULL_8812F(txdesc, value)                               \
+	SET_TX_DESC_BT_NULL(txdesc, value)
+#define GET_TX_DESC_BT_NULL_8812F(txdesc) GET_TX_DESC_BT_NULL(txdesc)
+#define SET_TX_DESC_AMPDU_DENSITY_8812F(txdesc, value)                         \
+	SET_TX_DESC_AMPDU_DENSITY(txdesc, value)
+#define GET_TX_DESC_AMPDU_DENSITY_8812F(txdesc)                                \
+	GET_TX_DESC_AMPDU_DENSITY(txdesc)
+#define SET_TX_DESC_SPE_RPT_8812F(txdesc, value)                               \
+	SET_TX_DESC_SPE_RPT(txdesc, value)
+#define GET_TX_DESC_SPE_RPT_8812F(txdesc) GET_TX_DESC_SPE_RPT(txdesc)
+#define SET_TX_DESC_RAW_8812F(txdesc, value) SET_TX_DESC_RAW(txdesc, value)
+#define GET_TX_DESC_RAW_8812F(txdesc) GET_TX_DESC_RAW(txdesc)
+#define SET_TX_DESC_MOREFRAG_8812F(txdesc, value)                              \
+	SET_TX_DESC_MOREFRAG(txdesc, value)
+#define GET_TX_DESC_MOREFRAG_8812F(txdesc) GET_TX_DESC_MOREFRAG(txdesc)
+#define SET_TX_DESC_BK_8812F(txdesc, value) SET_TX_DESC_BK(txdesc, value)
+#define GET_TX_DESC_BK_8812F(txdesc) GET_TX_DESC_BK(txdesc)
+#define SET_TX_DESC_NULL_1_8812F(txdesc, value)                                \
+	SET_TX_DESC_NULL_1(txdesc, value)
+#define GET_TX_DESC_NULL_1_8812F(txdesc) GET_TX_DESC_NULL_1(txdesc)
+#define SET_TX_DESC_NULL_0_8812F(txdesc, value)                                \
+	SET_TX_DESC_NULL_0(txdesc, value)
+#define GET_TX_DESC_NULL_0_8812F(txdesc) GET_TX_DESC_NULL_0(txdesc)
+#define SET_TX_DESC_RDG_EN_8812F(txdesc, value)                                \
+	SET_TX_DESC_RDG_EN(txdesc, value)
+#define GET_TX_DESC_RDG_EN_8812F(txdesc) GET_TX_DESC_RDG_EN(txdesc)
+#define SET_TX_DESC_AGG_EN_8812F(txdesc, value)                                \
+	SET_TX_DESC_AGG_EN(txdesc, value)
+#define GET_TX_DESC_AGG_EN_8812F(txdesc) GET_TX_DESC_AGG_EN(txdesc)
+#define SET_TX_DESC_CCA_RTS_8812F(txdesc, value)                               \
+	SET_TX_DESC_CCA_RTS(txdesc, value)
+#define GET_TX_DESC_CCA_RTS_8812F(txdesc) GET_TX_DESC_CCA_RTS(txdesc)
+#define SET_TX_DESC_TRI_FRAME_8812F(txdesc, value)                             \
+	SET_TX_DESC_TRI_FRAME(txdesc, value)
+#define GET_TX_DESC_TRI_FRAME_8812F(txdesc) GET_TX_DESC_TRI_FRAME(txdesc)
+#define SET_TX_DESC_P_AID_8812F(txdesc, value) SET_TX_DESC_P_AID(txdesc, value)
+#define GET_TX_DESC_P_AID_8812F(txdesc) GET_TX_DESC_P_AID(txdesc)
+
+/*TXDESC_WORD3*/
+
+#define SET_TX_DESC_AMPDU_MAX_TIME_8812F(txdesc, value)                        \
+	SET_TX_DESC_AMPDU_MAX_TIME(txdesc, value)
+#define GET_TX_DESC_AMPDU_MAX_TIME_8812F(txdesc)                               \
+	GET_TX_DESC_AMPDU_MAX_TIME(txdesc)
+#define SET_TX_DESC_NDPA_8812F(txdesc, value) SET_TX_DESC_NDPA(txdesc, value)
+#define GET_TX_DESC_NDPA_8812F(txdesc) GET_TX_DESC_NDPA(txdesc)
+#define SET_TX_DESC_MAX_AGG_NUM_8812F(txdesc, value)                           \
+	SET_TX_DESC_MAX_AGG_NUM(txdesc, value)
+#define GET_TX_DESC_MAX_AGG_NUM_8812F(txdesc) GET_TX_DESC_MAX_AGG_NUM(txdesc)
+#define SET_TX_DESC_USE_MAX_TIME_EN_8812F(txdesc, value)                       \
+	SET_TX_DESC_USE_MAX_TIME_EN(txdesc, value)
+#define GET_TX_DESC_USE_MAX_TIME_EN_8812F(txdesc)                              \
+	GET_TX_DESC_USE_MAX_TIME_EN(txdesc)
+#define SET_TX_DESC_NAVUSEHDR_8812F(txdesc, value)                             \
+	SET_TX_DESC_NAVUSEHDR(txdesc, value)
+#define GET_TX_DESC_NAVUSEHDR_8812F(txdesc) GET_TX_DESC_NAVUSEHDR(txdesc)
+#define SET_TX_DESC_CHK_EN_8812F(txdesc, value)                                \
+	SET_TX_DESC_CHK_EN(txdesc, value)
+#define GET_TX_DESC_CHK_EN_8812F(txdesc) GET_TX_DESC_CHK_EN(txdesc)
+#define SET_TX_DESC_HW_RTS_EN_8812F(txdesc, value)                             \
+	SET_TX_DESC_HW_RTS_EN(txdesc, value)
+#define GET_TX_DESC_HW_RTS_EN_8812F(txdesc) GET_TX_DESC_HW_RTS_EN(txdesc)
+#define SET_TX_DESC_RTSEN_8812F(txdesc, value) SET_TX_DESC_RTSEN(txdesc, value)
+#define GET_TX_DESC_RTSEN_8812F(txdesc) GET_TX_DESC_RTSEN(txdesc)
+#define SET_TX_DESC_CTS2SELF_8812F(txdesc, value)                              \
+	SET_TX_DESC_CTS2SELF(txdesc, value)
+#define GET_TX_DESC_CTS2SELF_8812F(txdesc) GET_TX_DESC_CTS2SELF(txdesc)
+#define SET_TX_DESC_DISDATAFB_8812F(txdesc, value)                             \
+	SET_TX_DESC_DISDATAFB(txdesc, value)
+#define GET_TX_DESC_DISDATAFB_8812F(txdesc) GET_TX_DESC_DISDATAFB(txdesc)
+#define SET_TX_DESC_DISRTSFB_8812F(txdesc, value)                              \
+	SET_TX_DESC_DISRTSFB(txdesc, value)
+#define GET_TX_DESC_DISRTSFB_8812F(txdesc) GET_TX_DESC_DISRTSFB(txdesc)
+#define SET_TX_DESC_USE_RATE_8812F(txdesc, value)                              \
+	SET_TX_DESC_USE_RATE(txdesc, value)
+#define GET_TX_DESC_USE_RATE_8812F(txdesc) GET_TX_DESC_USE_RATE(txdesc)
+#define SET_TX_DESC_HW_SSN_SEL_8812F(txdesc, value)                            \
+	SET_TX_DESC_HW_SSN_SEL(txdesc, value)
+#define GET_TX_DESC_HW_SSN_SEL_8812F(txdesc) GET_TX_DESC_HW_SSN_SEL(txdesc)
+#define SET_TX_DESC_WHEADER_LEN_8812F(txdesc, value)                           \
+	SET_TX_DESC_WHEADER_LEN(txdesc, value)
+#define GET_TX_DESC_WHEADER_LEN_8812F(txdesc) GET_TX_DESC_WHEADER_LEN(txdesc)
+
+/*TXDESC_WORD4*/
+
+#define SET_TX_DESC_PCTS_MASK_IDX_8812F(txdesc, value)                         \
+	SET_TX_DESC_PCTS_MASK_IDX(txdesc, value)
+#define GET_TX_DESC_PCTS_MASK_IDX_8812F(txdesc)                                \
+	GET_TX_DESC_PCTS_MASK_IDX(txdesc)
+#define SET_TX_DESC_PCTS_EN_8812F(txdesc, value)                               \
+	SET_TX_DESC_PCTS_EN(txdesc, value)
+#define GET_TX_DESC_PCTS_EN_8812F(txdesc) GET_TX_DESC_PCTS_EN(txdesc)
+#define SET_TX_DESC_RTSRATE_8812F(txdesc, value)                               \
+	SET_TX_DESC_RTSRATE(txdesc, value)
+#define GET_TX_DESC_RTSRATE_8812F(txdesc) GET_TX_DESC_RTSRATE(txdesc)
+#define SET_TX_DESC_RTS_DATA_RTY_LMT_8812F(txdesc, value)                      \
+	SET_TX_DESC_RTS_DATA_RTY_LMT(txdesc, value)
+#define GET_TX_DESC_RTS_DATA_RTY_LMT_8812F(txdesc)                             \
+	GET_TX_DESC_RTS_DATA_RTY_LMT(txdesc)
+#define SET_TX_DESC_RTY_LMT_EN_8812F(txdesc, value)                            \
+	SET_TX_DESC_RTY_LMT_EN(txdesc, value)
+#define GET_TX_DESC_RTY_LMT_EN_8812F(txdesc) GET_TX_DESC_RTY_LMT_EN(txdesc)
+#define SET_TX_DESC_RTS_RTY_LOWEST_RATE_8812F(txdesc, value)                   \
+	SET_TX_DESC_RTS_RTY_LOWEST_RATE(txdesc, value)
+#define GET_TX_DESC_RTS_RTY_LOWEST_RATE_8812F(txdesc)                          \
+	GET_TX_DESC_RTS_RTY_LOWEST_RATE(txdesc)
+#define SET_TX_DESC_DATA_RTY_LOWEST_RATE_8812F(txdesc, value)                  \
+	SET_TX_DESC_DATA_RTY_LOWEST_RATE(txdesc, value)
+#define GET_TX_DESC_DATA_RTY_LOWEST_RATE_8812F(txdesc)                         \
+	GET_TX_DESC_DATA_RTY_LOWEST_RATE(txdesc)
+#define SET_TX_DESC_TRY_RATE_8812F(txdesc, value)                              \
+	SET_TX_DESC_TRY_RATE(txdesc, value)
+#define GET_TX_DESC_TRY_RATE_8812F(txdesc) GET_TX_DESC_TRY_RATE(txdesc)
+#define SET_TX_DESC_DATARATE_8812F(txdesc, value)                              \
+	SET_TX_DESC_DATARATE(txdesc, value)
+#define GET_TX_DESC_DATARATE_8812F(txdesc) GET_TX_DESC_DATARATE(txdesc)
+
+/*TXDESC_WORD5*/
+
+#define SET_TX_DESC_POLLUTED_8812F(txdesc, value)                              \
+	SET_TX_DESC_POLLUTED(txdesc, value)
+#define GET_TX_DESC_POLLUTED_8812F(txdesc) GET_TX_DESC_POLLUTED(txdesc)
+#define SET_TX_DESC_ANTSEL_EN_8812F(txdesc, value)                             \
+	SET_TX_DESC_ANTSEL_EN_V1(txdesc, value)
+#define GET_TX_DESC_ANTSEL_EN_8812F(txdesc) GET_TX_DESC_ANTSEL_EN_V1(txdesc)
+#define SET_TX_DESC_TXPWR_OFSET_TYPE_8812F(txdesc, value)                      \
+	SET_TX_DESC_TXPWR_OFSET_TYPE(txdesc, value)
+#define GET_TX_DESC_TXPWR_OFSET_TYPE_8812F(txdesc)                             \
+	GET_TX_DESC_TXPWR_OFSET_TYPE(txdesc)
+#define SET_TX_DESC_TX_ANT_8812F(txdesc, value)                                \
+	SET_TX_DESC_TX_ANT(txdesc, value)
+#define GET_TX_DESC_TX_ANT_8812F(txdesc) GET_TX_DESC_TX_ANT(txdesc)
+#define SET_TX_DESC_PORT_ID_8812F(txdesc, value)                               \
+	SET_TX_DESC_PORT_ID(txdesc, value)
+#define GET_TX_DESC_PORT_ID_8812F(txdesc) GET_TX_DESC_PORT_ID(txdesc)
+#define SET_TX_DESC_MULTIPLE_PORT_8812F(txdesc, value)                         \
+	SET_TX_DESC_MULTIPLE_PORT(txdesc, value)
+#define GET_TX_DESC_MULTIPLE_PORT_8812F(txdesc)                                \
+	GET_TX_DESC_MULTIPLE_PORT(txdesc)
+#define SET_TX_DESC_SIGNALING_TAPKT_EN_8812F(txdesc, value)                    \
+	SET_TX_DESC_SIGNALING_TAPKT_EN(txdesc, value)
+#define GET_TX_DESC_SIGNALING_TAPKT_EN_8812F(txdesc)                           \
+	GET_TX_DESC_SIGNALING_TAPKT_EN(txdesc)
+#define SET_TX_DESC_SIGNALING_TA_PKT_SC_8812F(txdesc, value)                   \
+	SET_TX_DESC_SIGNALING_TA_PKT_SC(txdesc, value)
+#define GET_TX_DESC_SIGNALING_TA_PKT_SC_8812F(txdesc)                          \
+	GET_TX_DESC_SIGNALING_TA_PKT_SC(txdesc)
+#define SET_TX_DESC_RTS_SHORT_8812F(txdesc, value)                             \
+	SET_TX_DESC_RTS_SHORT(txdesc, value)
+#define GET_TX_DESC_RTS_SHORT_8812F(txdesc) GET_TX_DESC_RTS_SHORT(txdesc)
+#define SET_TX_DESC_VCS_STBC_8812F(txdesc, value)                              \
+	SET_TX_DESC_VCS_STBC(txdesc, value)
+#define GET_TX_DESC_VCS_STBC_8812F(txdesc) GET_TX_DESC_VCS_STBC(txdesc)
+#define SET_TX_DESC_DATA_STBC_8812F(txdesc, value)                             \
+	SET_TX_DESC_DATA_STBC(txdesc, value)
+#define GET_TX_DESC_DATA_STBC_8812F(txdesc) GET_TX_DESC_DATA_STBC(txdesc)
+#define SET_TX_DESC_DATA_LDPC_8812F(txdesc, value)                             \
+	SET_TX_DESC_DATA_LDPC(txdesc, value)
+#define GET_TX_DESC_DATA_LDPC_8812F(txdesc) GET_TX_DESC_DATA_LDPC(txdesc)
+#define SET_TX_DESC_DATA_BW_8812F(txdesc, value)                               \
+	SET_TX_DESC_DATA_BW(txdesc, value)
+#define GET_TX_DESC_DATA_BW_8812F(txdesc) GET_TX_DESC_DATA_BW(txdesc)
+#define SET_TX_DESC_DATA_SHORT_8812F(txdesc, value)                            \
+	SET_TX_DESC_DATA_SHORT(txdesc, value)
+#define GET_TX_DESC_DATA_SHORT_8812F(txdesc) GET_TX_DESC_DATA_SHORT(txdesc)
+#define SET_TX_DESC_DATA_SC_8812F(txdesc, value)                               \
+	SET_TX_DESC_DATA_SC(txdesc, value)
+#define GET_TX_DESC_DATA_SC_8812F(txdesc) GET_TX_DESC_DATA_SC(txdesc)
+
+/*TXDESC_WORD6*/
+
+#define SET_TX_DESC_ANTSEL_D_8812F(txdesc, value)                              \
+	SET_TX_DESC_ANTSEL_D(txdesc, value)
+#define GET_TX_DESC_ANTSEL_D_8812F(txdesc) GET_TX_DESC_ANTSEL_D(txdesc)
+#define SET_TX_DESC_ANT_MAPD_8812F(txdesc, value)                              \
+	SET_TX_DESC_ANT_MAPD(txdesc, value)
+#define GET_TX_DESC_ANT_MAPD_8812F(txdesc) GET_TX_DESC_ANT_MAPD(txdesc)
+#define SET_TX_DESC_ANT_MAPC_8812F(txdesc, value)                              \
+	SET_TX_DESC_ANT_MAPC(txdesc, value)
+#define GET_TX_DESC_ANT_MAPC_8812F(txdesc) GET_TX_DESC_ANT_MAPC(txdesc)
+#define SET_TX_DESC_ANT_MAPB_8812F(txdesc, value)                              \
+	SET_TX_DESC_ANT_MAPB(txdesc, value)
+#define GET_TX_DESC_ANT_MAPB_8812F(txdesc) GET_TX_DESC_ANT_MAPB(txdesc)
+#define SET_TX_DESC_ANT_MAPA_8812F(txdesc, value)                              \
+	SET_TX_DESC_ANT_MAPA(txdesc, value)
+#define GET_TX_DESC_ANT_MAPA_8812F(txdesc) GET_TX_DESC_ANT_MAPA(txdesc)
+#define SET_TX_DESC_ANTSEL_C_8812F(txdesc, value)                              \
+	SET_TX_DESC_ANTSEL_C(txdesc, value)
+#define GET_TX_DESC_ANTSEL_C_8812F(txdesc) GET_TX_DESC_ANTSEL_C(txdesc)
+#define SET_TX_DESC_ANTSEL_B_8812F(txdesc, value)                              \
+	SET_TX_DESC_ANTSEL_B(txdesc, value)
+#define GET_TX_DESC_ANTSEL_B_8812F(txdesc) GET_TX_DESC_ANTSEL_B(txdesc)
+#define SET_TX_DESC_ANTSEL_A_8812F(txdesc, value)                              \
+	SET_TX_DESC_ANTSEL_A(txdesc, value)
+#define GET_TX_DESC_ANTSEL_A_8812F(txdesc) GET_TX_DESC_ANTSEL_A(txdesc)
+#define SET_TX_DESC_MBSSID_8812F(txdesc, value)                                \
+	SET_TX_DESC_MBSSID(txdesc, value)
+#define GET_TX_DESC_MBSSID_8812F(txdesc) GET_TX_DESC_MBSSID(txdesc)
+#define SET_TX_DESC_SW_DEFINE_8812F(txdesc, value)                             \
+	SET_TX_DESC_SW_DEFINE(txdesc, value)
+#define GET_TX_DESC_SW_DEFINE_8812F(txdesc) GET_TX_DESC_SW_DEFINE(txdesc)
+
+/*TXDESC_WORD7*/
+
+#define SET_TX_DESC_DMA_TXAGG_NUM_8812F(txdesc, value)                         \
+	SET_TX_DESC_DMA_TXAGG_NUM(txdesc, value)
+#define GET_TX_DESC_DMA_TXAGG_NUM_8812F(txdesc)                                \
+	GET_TX_DESC_DMA_TXAGG_NUM(txdesc)
+#define SET_TX_DESC_FINAL_DATA_RATE_8812F(txdesc, value)                       \
+	SET_TX_DESC_FINAL_DATA_RATE(txdesc, value)
+#define GET_TX_DESC_FINAL_DATA_RATE_8812F(txdesc)                              \
+	GET_TX_DESC_FINAL_DATA_RATE(txdesc)
+#define SET_TX_DESC_NTX_MAP_8812F(txdesc, value)                               \
+	SET_TX_DESC_NTX_MAP(txdesc, value)
+#define GET_TX_DESC_NTX_MAP_8812F(txdesc) GET_TX_DESC_NTX_MAP(txdesc)
+#define SET_TX_DESC_TX_BUFF_SIZE_8812F(txdesc, value)                          \
+	SET_TX_DESC_TX_BUFF_SIZE(txdesc, value)
+#define GET_TX_DESC_TX_BUFF_SIZE_8812F(txdesc) GET_TX_DESC_TX_BUFF_SIZE(txdesc)
+#define SET_TX_DESC_TXDESC_CHECKSUM_8812F(txdesc, value)                       \
+	SET_TX_DESC_TXDESC_CHECKSUM(txdesc, value)
+#define GET_TX_DESC_TXDESC_CHECKSUM_8812F(txdesc)                              \
+	GET_TX_DESC_TXDESC_CHECKSUM(txdesc)
+#define SET_TX_DESC_TIMESTAMP_8812F(txdesc, value)                             \
+	SET_TX_DESC_TIMESTAMP(txdesc, value)
+#define GET_TX_DESC_TIMESTAMP_8812F(txdesc) GET_TX_DESC_TIMESTAMP(txdesc)
+
+/*TXDESC_WORD8*/
+
+#define SET_TX_DESC_TXWIFI_CP_8812F(txdesc, value)                             \
+	SET_TX_DESC_TXWIFI_CP(txdesc, value)
+#define GET_TX_DESC_TXWIFI_CP_8812F(txdesc) GET_TX_DESC_TXWIFI_CP(txdesc)
+#define SET_TX_DESC_MAC_CP_8812F(txdesc, value)                                \
+	SET_TX_DESC_MAC_CP(txdesc, value)
+#define GET_TX_DESC_MAC_CP_8812F(txdesc) GET_TX_DESC_MAC_CP(txdesc)
+#define SET_TX_DESC_STW_PKTRE_DIS_8812F(txdesc, value)                         \
+	SET_TX_DESC_STW_PKTRE_DIS(txdesc, value)
+#define GET_TX_DESC_STW_PKTRE_DIS_8812F(txdesc)                                \
+	GET_TX_DESC_STW_PKTRE_DIS(txdesc)
+#define SET_TX_DESC_STW_RB_DIS_8812F(txdesc, value)                            \
+	SET_TX_DESC_STW_RB_DIS(txdesc, value)
+#define GET_TX_DESC_STW_RB_DIS_8812F(txdesc) GET_TX_DESC_STW_RB_DIS(txdesc)
+#define SET_TX_DESC_STW_RATE_DIS_8812F(txdesc, value)                          \
+	SET_TX_DESC_STW_RATE_DIS(txdesc, value)
+#define GET_TX_DESC_STW_RATE_DIS_8812F(txdesc) GET_TX_DESC_STW_RATE_DIS(txdesc)
+#define SET_TX_DESC_STW_ANT_DIS_8812F(txdesc, value)                           \
+	SET_TX_DESC_STW_ANT_DIS(txdesc, value)
+#define GET_TX_DESC_STW_ANT_DIS_8812F(txdesc) GET_TX_DESC_STW_ANT_DIS(txdesc)
+#define SET_TX_DESC_STW_EN_8812F(txdesc, value)                                \
+	SET_TX_DESC_STW_EN(txdesc, value)
+#define GET_TX_DESC_STW_EN_8812F(txdesc) GET_TX_DESC_STW_EN(txdesc)
+#define SET_TX_DESC_SMH_EN_8812F(txdesc, value)                                \
+	SET_TX_DESC_SMH_EN(txdesc, value)
+#define GET_TX_DESC_SMH_EN_8812F(txdesc) GET_TX_DESC_SMH_EN(txdesc)
+#define SET_TX_DESC_TAILPAGE_L_8812F(txdesc, value)                            \
+	SET_TX_DESC_TAILPAGE_L(txdesc, value)
+#define GET_TX_DESC_TAILPAGE_L_8812F(txdesc) GET_TX_DESC_TAILPAGE_L(txdesc)
+#define SET_TX_DESC_SDIO_DMASEQ_8812F(txdesc, value)                           \
+	SET_TX_DESC_SDIO_DMASEQ(txdesc, value)
+#define GET_TX_DESC_SDIO_DMASEQ_8812F(txdesc) GET_TX_DESC_SDIO_DMASEQ(txdesc)
+#define SET_TX_DESC_NEXTHEADPAGE_L_8812F(txdesc, value)                        \
+	SET_TX_DESC_NEXTHEADPAGE_L(txdesc, value)
+#define GET_TX_DESC_NEXTHEADPAGE_L_8812F(txdesc)                               \
+	GET_TX_DESC_NEXTHEADPAGE_L(txdesc)
+#define SET_TX_DESC_EN_HWSEQ_MODE_8812F(txdesc, value)                         \
+	SET_TX_DESC_EN_HWSEQ_MODE(txdesc, value)
+#define GET_TX_DESC_EN_HWSEQ_MODE_8812F(txdesc)                                \
+	GET_TX_DESC_EN_HWSEQ_MODE(txdesc)
+#define SET_TX_DESC_DATA_RC_8812F(txdesc, value)                               \
+	SET_TX_DESC_DATA_RC(txdesc, value)
+#define GET_TX_DESC_DATA_RC_8812F(txdesc) GET_TX_DESC_DATA_RC(txdesc)
+#define SET_TX_DESC_BAR_RTY_TH_8812F(txdesc, value)                            \
+	SET_TX_DESC_BAR_RTY_TH(txdesc, value)
+#define GET_TX_DESC_BAR_RTY_TH_8812F(txdesc) GET_TX_DESC_BAR_RTY_TH(txdesc)
+#define SET_TX_DESC_RTS_RC_8812F(txdesc, value)                                \
+	SET_TX_DESC_RTS_RC(txdesc, value)
+#define GET_TX_DESC_RTS_RC_8812F(txdesc) GET_TX_DESC_RTS_RC(txdesc)
+
+/*TXDESC_WORD9*/
+
+#define SET_TX_DESC_TAILPAGE_H_8812F(txdesc, value)                            \
+	SET_TX_DESC_TAILPAGE_H(txdesc, value)
+#define GET_TX_DESC_TAILPAGE_H_8812F(txdesc) GET_TX_DESC_TAILPAGE_H(txdesc)
+#define SET_TX_DESC_NEXTHEADPAGE_H_8812F(txdesc, value)                        \
+	SET_TX_DESC_NEXTHEADPAGE_H(txdesc, value)
+#define GET_TX_DESC_NEXTHEADPAGE_H_8812F(txdesc)                               \
+	GET_TX_DESC_NEXTHEADPAGE_H(txdesc)
+#define SET_TX_DESC_SW_SEQ_8812F(txdesc, value)                                \
+	SET_TX_DESC_SW_SEQ(txdesc, value)
+#define GET_TX_DESC_SW_SEQ_8812F(txdesc) GET_TX_DESC_SW_SEQ(txdesc)
+#define SET_TX_DESC_TXBF_PATH_8812F(txdesc, value)                             \
+	SET_TX_DESC_TXBF_PATH(txdesc, value)
+#define GET_TX_DESC_TXBF_PATH_8812F(txdesc) GET_TX_DESC_TXBF_PATH(txdesc)
+#define SET_TX_DESC_PADDING_LEN_8812F(txdesc, value)                           \
+	SET_TX_DESC_PADDING_LEN(txdesc, value)
+#define GET_TX_DESC_PADDING_LEN_8812F(txdesc) GET_TX_DESC_PADDING_LEN(txdesc)
+#define SET_TX_DESC_GROUP_BIT_IE_OFFSET_8812F(txdesc, value)                   \
+	SET_TX_DESC_GROUP_BIT_IE_OFFSET(txdesc, value)
+#define GET_TX_DESC_GROUP_BIT_IE_OFFSET_8812F(txdesc)                          \
+	GET_TX_DESC_GROUP_BIT_IE_OFFSET(txdesc)
+
+/*WORD10*/
+
+#define SET_TX_DESC_HT_DATA_SND_8812F(txdesc, value)                           \
+	SET_TX_DESC_HT_DATA_SND(txdesc, value)
+#define GET_TX_DESC_HT_DATA_SND_8812F(txdesc) GET_TX_DESC_HT_DATA_SND(txdesc)
+#define SET_TX_DESC_SHCUT_CAM_8812F(txdesc, value)                             \
+	SET_TX_DESC_SHCUT_CAM(txdesc, value)
+#define GET_TX_DESC_SHCUT_CAM_8812F(txdesc) GET_TX_DESC_SHCUT_CAM(txdesc)
+#define SET_TX_DESC_MU_DATARATE_8812F(txdesc, value)                           \
+	SET_TX_DESC_MU_DATARATE(txdesc, value)
+#define GET_TX_DESC_MU_DATARATE_8812F(txdesc) GET_TX_DESC_MU_DATARATE(txdesc)
+#define SET_TX_DESC_MU_RC_8812F(txdesc, value) SET_TX_DESC_MU_RC(txdesc, value)
+#define GET_TX_DESC_MU_RC_8812F(txdesc) GET_TX_DESC_MU_RC(txdesc)
+#define SET_TX_DESC_NDPA_RATE_SEL_8812F(txdesc, value)                         \
+	SET_TX_DESC_NDPA_RATE_SEL(txdesc, value)
+#define GET_TX_DESC_NDPA_RATE_SEL_8812F(txdesc)                                \
+	GET_TX_DESC_NDPA_RATE_SEL(txdesc)
+#define SET_TX_DESC_HW_NDPA_EN_8812F(txdesc, value)                            \
+	SET_TX_DESC_HW_NDPA_EN(txdesc, value)
+#define GET_TX_DESC_HW_NDPA_EN_8812F(txdesc) GET_TX_DESC_HW_NDPA_EN(txdesc)
+#define SET_TX_DESC_SND_PKT_SEL_8812F(txdesc, value)                           \
+	SET_TX_DESC_SND_PKT_SEL(txdesc, value)
+#define GET_TX_DESC_SND_PKT_SEL_8812F(txdesc) GET_TX_DESC_SND_PKT_SEL(txdesc)
+
+#endif
+
+#endif
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/halmac/halmac_tx_desc_ie_ap.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/halmac/halmac_tx_desc_ie_ap.h
--- linux-5.6.3/3rdparty/rtl8821ce/hal/halmac/halmac_tx_desc_ie_ap.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/halmac/halmac_tx_desc_ie_ap.h	2020-04-10 16:35:06.817660114 +0300
@@ -0,0 +1,1005 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ ******************************************************************************/
+
+#ifndef _HALMAC_TX_DESC_IE_AP_H_
+#define _HALMAC_TX_DESC_IE_AP_H_
+#if (HALMAC_8814B_SUPPORT)
+
+#define IE0_GET_TX_DESC_IE_END(txdesc_ie)                                      \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0,    \
+			      0x1, 31)
+#define IE0_SET_TX_DESC_IE_END(txdesc_ie, value)                               \
+	HALMAC_SET_DESC_FIELD_CLR(                                             \
+		((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 31)
+#define IE0_SET_TX_DESC_IE_END_NO_CLR(txdesc_ie, value)                        \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 31)
+#define IE0_GET_TX_DESC_IE_UP(txdesc_ie)                                       \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0,    \
+			      0x1, 30)
+#define IE0_SET_TX_DESC_IE_UP(txdesc_ie, value)                                \
+	HALMAC_SET_DESC_FIELD_CLR(                                             \
+		((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 30)
+#define IE0_SET_TX_DESC_IE_UP_NO_CLR(txdesc_ie, value)                         \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 30)
+#define IE0_GET_TX_DESC_IE_NUM(txdesc_ie)                                      \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0,    \
+			      0xf, 24)
+#define IE0_SET_TX_DESC_IE_NUM(txdesc_ie, value)                               \
+	HALMAC_SET_DESC_FIELD_CLR(                                             \
+		((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0xf, 24)
+#define IE0_SET_TX_DESC_IE_NUM_NO_CLR(txdesc_ie, value)                        \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0xf, 24)
+#define IE0_GET_TX_DESC_ARFR_TABLE_SEL(txdesc_ie)                              \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0,    \
+			      0x1, 19)
+#define IE0_SET_TX_DESC_ARFR_TABLE_SEL(txdesc_ie, value)                       \
+	HALMAC_SET_DESC_FIELD_CLR(                                             \
+		((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 19)
+#define IE0_SET_TX_DESC_ARFR_TABLE_SEL_NO_CLR(txdesc_ie, value)                \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 19)
+#define IE0_GET_TX_DESC_ARFR_HT_EN(txdesc_ie)                                  \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0,    \
+			      0x1, 18)
+#define IE0_SET_TX_DESC_ARFR_HT_EN(txdesc_ie, value)                           \
+	HALMAC_SET_DESC_FIELD_CLR(                                             \
+		((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 18)
+#define IE0_SET_TX_DESC_ARFR_HT_EN_NO_CLR(txdesc_ie, value)                    \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 18)
+#define IE0_GET_TX_DESC_ARFR_OFDM_EN(txdesc_ie)                                \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0,    \
+			      0x1, 17)
+#define IE0_SET_TX_DESC_ARFR_OFDM_EN(txdesc_ie, value)                         \
+	HALMAC_SET_DESC_FIELD_CLR(                                             \
+		((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 17)
+#define IE0_SET_TX_DESC_ARFR_OFDM_EN_NO_CLR(txdesc_ie, value)                  \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 17)
+#define IE0_GET_TX_DESC_ARFR_CCK_EN(txdesc_ie)                                 \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0,    \
+			      0x1, 16)
+#define IE0_SET_TX_DESC_ARFR_CCK_EN(txdesc_ie, value)                          \
+	HALMAC_SET_DESC_FIELD_CLR(                                             \
+		((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 16)
+#define IE0_SET_TX_DESC_ARFR_CCK_EN_NO_CLR(txdesc_ie, value)                   \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 16)
+#define IE0_GET_TX_DESC_HW_RTS_EN(txdesc_ie)                                   \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0,    \
+			      0x1, 9)
+#define IE0_SET_TX_DESC_HW_RTS_EN(txdesc_ie, value)                            \
+	HALMAC_SET_DESC_FIELD_CLR(                                             \
+		((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 9)
+#define IE0_SET_TX_DESC_HW_RTS_EN_NO_CLR(txdesc_ie, value)                     \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 9)
+#define IE0_GET_TX_DESC_RTS_EN(txdesc_ie)                                      \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0,    \
+			      0x1, 8)
+#define IE0_SET_TX_DESC_RTS_EN(txdesc_ie, value)                               \
+	HALMAC_SET_DESC_FIELD_CLR(                                             \
+		((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 8)
+#define IE0_SET_TX_DESC_RTS_EN_NO_CLR(txdesc_ie, value)                        \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 8)
+#define IE0_GET_TX_DESC_CTS2SELF(txdesc_ie)                                    \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0,    \
+			      0x1, 7)
+#define IE0_SET_TX_DESC_CTS2SELF(txdesc_ie, value)                             \
+	HALMAC_SET_DESC_FIELD_CLR(                                             \
+		((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 7)
+#define IE0_SET_TX_DESC_CTS2SELF_NO_CLR(txdesc_ie, value)                      \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 7)
+#define IE0_GET_TX_DESC_RTY_LMT_EN(txdesc_ie)                                  \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0,    \
+			      0x1, 6)
+#define IE0_SET_TX_DESC_RTY_LMT_EN(txdesc_ie, value)                           \
+	HALMAC_SET_DESC_FIELD_CLR(                                             \
+		((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 6)
+#define IE0_SET_TX_DESC_RTY_LMT_EN_NO_CLR(txdesc_ie, value)                    \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 6)
+#define IE0_GET_TX_DESC_RTS_SHORT(txdesc_ie)                                   \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0,    \
+			      0x1, 5)
+#define IE0_SET_TX_DESC_RTS_SHORT(txdesc_ie, value)                            \
+	HALMAC_SET_DESC_FIELD_CLR(                                             \
+		((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 5)
+#define IE0_SET_TX_DESC_RTS_SHORT_NO_CLR(txdesc_ie, value)                     \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 5)
+#define IE0_GET_TX_DESC_DISDATAFB(txdesc_ie)                                   \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0,    \
+			      0x1, 4)
+#define IE0_SET_TX_DESC_DISDATAFB(txdesc_ie, value)                            \
+	HALMAC_SET_DESC_FIELD_CLR(                                             \
+		((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 4)
+#define IE0_SET_TX_DESC_DISDATAFB_NO_CLR(txdesc_ie, value)                     \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 4)
+#define IE0_GET_TX_DESC_DISRTSFB(txdesc_ie)                                    \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0,    \
+			      0x1, 3)
+#define IE0_SET_TX_DESC_DISRTSFB(txdesc_ie, value)                             \
+	HALMAC_SET_DESC_FIELD_CLR(                                             \
+		((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 3)
+#define IE0_SET_TX_DESC_DISRTSFB_NO_CLR(txdesc_ie, value)                      \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 3)
+#define IE0_GET_TX_DESC_DATA_SHORT(txdesc_ie)                                  \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0,    \
+			      0x1, 2)
+#define IE0_SET_TX_DESC_DATA_SHORT(txdesc_ie, value)                           \
+	HALMAC_SET_DESC_FIELD_CLR(                                             \
+		((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 2)
+#define IE0_SET_TX_DESC_DATA_SHORT_NO_CLR(txdesc_ie, value)                    \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 2)
+#define IE0_GET_TX_DESC_TRY_RATE(txdesc_ie)                                    \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0,    \
+			      0x1, 1)
+#define IE0_SET_TX_DESC_TRY_RATE(txdesc_ie, value)                             \
+	HALMAC_SET_DESC_FIELD_CLR(                                             \
+		((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 1)
+#define IE0_SET_TX_DESC_TRY_RATE_NO_CLR(txdesc_ie, value)                      \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 1)
+#define IE0_GET_TX_DESC_USERATE(txdesc_ie)                                     \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0,    \
+			      0x1, 0)
+#define IE0_SET_TX_DESC_USERATE(txdesc_ie, value)                              \
+	HALMAC_SET_DESC_FIELD_CLR(                                             \
+		((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 0)
+#define IE0_SET_TX_DESC_USERATE_NO_CLR(txdesc_ie, value)                       \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 0)
+#define IE0_GET_TX_DESC_RTS_RTY_LOWEST_RATE(txdesc_ie)                         \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword1,    \
+			      0xf, 27)
+#define IE0_SET_TX_DESC_RTS_RTY_LOWEST_RATE(txdesc_ie, value)                  \
+	HALMAC_SET_DESC_FIELD_CLR(                                             \
+		((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0xf, 27)
+#define IE0_SET_TX_DESC_RTS_RTY_LOWEST_RATE_NO_CLR(txdesc_ie, value)           \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0xf, 27)
+#define IE0_GET_TX_DESC_DATA_RTY_LOWEST_RATE(txdesc_ie)                        \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword1,    \
+			      0x1f, 22)
+#define IE0_SET_TX_DESC_DATA_RTY_LOWEST_RATE(txdesc_ie, value)                 \
+	HALMAC_SET_DESC_FIELD_CLR(                                             \
+		((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0x1f, 22)
+#define IE0_SET_TX_DESC_DATA_RTY_LOWEST_RATE_NO_CLR(txdesc_ie, value)          \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0x1f, 22)
+#define IE0_GET_TX_DESC_RTS_DATA_RTY_LMT(txdesc_ie)                            \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword1,    \
+			      0x3f, 16)
+#define IE0_SET_TX_DESC_RTS_DATA_RTY_LMT(txdesc_ie, value)                     \
+	HALMAC_SET_DESC_FIELD_CLR(                                             \
+		((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0x3f, 16)
+#define IE0_SET_TX_DESC_RTS_DATA_RTY_LMT_NO_CLR(txdesc_ie, value)              \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0x3f, 16)
+#define IE0_GET_TX_DESC_DATA_BW(txdesc_ie)                                     \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword1,    \
+			      0x3, 12)
+#define IE0_SET_TX_DESC_DATA_BW(txdesc_ie, value)                              \
+	HALMAC_SET_DESC_FIELD_CLR(                                             \
+		((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0x3, 12)
+#define IE0_SET_TX_DESC_DATA_BW_NO_CLR(txdesc_ie, value)                       \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0x3, 12)
+#define IE0_GET_TX_DESC_RTSRATE(txdesc_ie)                                     \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword1,    \
+			      0xf, 7)
+#define IE0_SET_TX_DESC_RTSRATE(txdesc_ie, value)                              \
+	HALMAC_SET_DESC_FIELD_CLR(                                             \
+		((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0xf, 7)
+#define IE0_SET_TX_DESC_RTSRATE_NO_CLR(txdesc_ie, value)                       \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0xf, 7)
+#define IE0_GET_TX_DESC_DATARATE(txdesc_ie)                                    \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword1,    \
+			      0x7f, 0)
+#define IE0_SET_TX_DESC_DATARATE(txdesc_ie, value)                             \
+	HALMAC_SET_DESC_FIELD_CLR(                                             \
+		((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0x7f, 0)
+#define IE0_SET_TX_DESC_DATARATE_NO_CLR(txdesc_ie, value)                      \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0x7f, 0)
+#define IE1_GET_TX_DESC_IE_END(txdesc_ie)                                      \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0,    \
+			      0x1, 31)
+#define IE1_SET_TX_DESC_IE_END(txdesc_ie, value)                               \
+	HALMAC_SET_DESC_FIELD_CLR(                                             \
+		((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 31)
+#define IE1_SET_TX_DESC_IE_END_NO_CLR(txdesc_ie, value)                        \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 31)
+#define IE1_GET_TX_DESC_IE_UP(txdesc_ie)                                       \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0,    \
+			      0x1, 30)
+#define IE1_SET_TX_DESC_IE_UP(txdesc_ie, value)                                \
+	HALMAC_SET_DESC_FIELD_CLR(                                             \
+		((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 30)
+#define IE1_SET_TX_DESC_IE_UP_NO_CLR(txdesc_ie, value)                         \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 30)
+#define IE1_GET_TX_DESC_IE_NUM(txdesc_ie)                                      \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0,    \
+			      0xf, 24)
+#define IE1_SET_TX_DESC_IE_NUM(txdesc_ie, value)                               \
+	HALMAC_SET_DESC_FIELD_CLR(                                             \
+		((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0xf, 24)
+#define IE1_SET_TX_DESC_IE_NUM_NO_CLR(txdesc_ie, value)                        \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0xf, 24)
+#define IE1_GET_TX_DESC_AMPDU_DENSITY(txdesc_ie)                               \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0,    \
+			      0x7, 21)
+#define IE1_SET_TX_DESC_AMPDU_DENSITY(txdesc_ie, value)                        \
+	HALMAC_SET_DESC_FIELD_CLR(                                             \
+		((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x7, 21)
+#define IE1_SET_TX_DESC_AMPDU_DENSITY_NO_CLR(txdesc_ie, value)                 \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x7, 21)
+#define IE1_GET_TX_DESC_MAX_AGG_NUM(txdesc_ie)                                 \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0,    \
+			      0x1f, 16)
+#define IE1_SET_TX_DESC_MAX_AGG_NUM(txdesc_ie, value)                          \
+	HALMAC_SET_DESC_FIELD_CLR(                                             \
+		((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1f, 16)
+#define IE1_SET_TX_DESC_MAX_AGG_NUM_NO_CLR(txdesc_ie, value)                   \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1f, 16)
+#define IE1_GET_TX_DESC_SECTYPE(txdesc_ie)                                     \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0,    \
+			      0x3, 14)
+#define IE1_SET_TX_DESC_SECTYPE(txdesc_ie, value)                              \
+	HALMAC_SET_DESC_FIELD_CLR(                                             \
+		((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x3, 14)
+#define IE1_SET_TX_DESC_SECTYPE_NO_CLR(txdesc_ie, value)                       \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x3, 14)
+#define IE1_GET_TX_DESC_MOREFRAG(txdesc_ie)                                    \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0,    \
+			      0x1, 13)
+#define IE1_SET_TX_DESC_MOREFRAG(txdesc_ie, value)                             \
+	HALMAC_SET_DESC_FIELD_CLR(                                             \
+		((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 13)
+#define IE1_SET_TX_DESC_MOREFRAG_NO_CLR(txdesc_ie, value)                      \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 13)
+#define IE1_GET_TX_DESC_NOACM(txdesc_ie)                                       \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0,    \
+			      0x1, 12)
+#define IE1_SET_TX_DESC_NOACM(txdesc_ie, value)                                \
+	HALMAC_SET_DESC_FIELD_CLR(                                             \
+		((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 12)
+#define IE1_SET_TX_DESC_NOACM_NO_CLR(txdesc_ie, value)                         \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 12)
+#define IE1_GET_TX_DESC_BCNPKT_TSF_CTRL(txdesc_ie)                             \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0,    \
+			      0x1, 11)
+#define IE1_SET_TX_DESC_BCNPKT_TSF_CTRL(txdesc_ie, value)                      \
+	HALMAC_SET_DESC_FIELD_CLR(                                             \
+		((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 11)
+#define IE1_SET_TX_DESC_BCNPKT_TSF_CTRL_NO_CLR(txdesc_ie, value)               \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 11)
+#define IE1_GET_TX_DESC_NAVUSEHDR(txdesc_ie)                                   \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0,    \
+			      0x1, 10)
+#define IE1_SET_TX_DESC_NAVUSEHDR(txdesc_ie, value)                            \
+	HALMAC_SET_DESC_FIELD_CLR(                                             \
+		((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 10)
+#define IE1_SET_TX_DESC_NAVUSEHDR_NO_CLR(txdesc_ie, value)                     \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 10)
+#define IE1_GET_TX_DESC_HTC(txdesc_ie)                                         \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0,    \
+			      0x1, 9)
+#define IE1_SET_TX_DESC_HTC(txdesc_ie, value)                                  \
+	HALMAC_SET_DESC_FIELD_CLR(                                             \
+		((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 9)
+#define IE1_SET_TX_DESC_HTC_NO_CLR(txdesc_ie, value)                           \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 9)
+#define IE1_GET_TX_DESC_BMC(txdesc_ie)                                         \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0,    \
+			      0x1, 8)
+#define IE1_SET_TX_DESC_BMC(txdesc_ie, value)                                  \
+	HALMAC_SET_DESC_FIELD_CLR(                                             \
+		((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 8)
+#define IE1_SET_TX_DESC_BMC_NO_CLR(txdesc_ie, value)                           \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 8)
+#define IE1_GET_TX_DESC_TX_PKT_AFTER_PIFS(txdesc_ie)                           \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0,    \
+			      0x1, 7)
+#define IE1_SET_TX_DESC_TX_PKT_AFTER_PIFS(txdesc_ie, value)                    \
+	HALMAC_SET_DESC_FIELD_CLR(                                             \
+		((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 7)
+#define IE1_SET_TX_DESC_TX_PKT_AFTER_PIFS_NO_CLR(txdesc_ie, value)             \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 7)
+#define IE1_GET_TX_DESC_USE_MAX_TIME_EN(txdesc_ie)                             \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0,    \
+			      0x1, 6)
+#define IE1_SET_TX_DESC_USE_MAX_TIME_EN(txdesc_ie, value)                      \
+	HALMAC_SET_DESC_FIELD_CLR(                                             \
+		((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 6)
+#define IE1_SET_TX_DESC_USE_MAX_TIME_EN_NO_CLR(txdesc_ie, value)               \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 6)
+#define IE1_GET_TX_DESC_HW_SSN_SEL(txdesc_ie)                                  \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0,    \
+			      0x3, 4)
+#define IE1_SET_TX_DESC_HW_SSN_SEL(txdesc_ie, value)                           \
+	HALMAC_SET_DESC_FIELD_CLR(                                             \
+		((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x3, 4)
+#define IE1_SET_TX_DESC_HW_SSN_SEL_NO_CLR(txdesc_ie, value)                    \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x3, 4)
+#define IE1_GET_TX_DESC_DISQSELSEQ(txdesc_ie)                                  \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0,    \
+			      0x1, 3)
+#define IE1_SET_TX_DESC_DISQSELSEQ(txdesc_ie, value)                           \
+	HALMAC_SET_DESC_FIELD_CLR(                                             \
+		((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 3)
+#define IE1_SET_TX_DESC_DISQSELSEQ_NO_CLR(txdesc_ie, value)                    \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 3)
+#define IE1_GET_TX_DESC_EN_HWSEQ(txdesc_ie)                                    \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0,    \
+			      0x1, 2)
+#define IE1_SET_TX_DESC_EN_HWSEQ(txdesc_ie, value)                             \
+	HALMAC_SET_DESC_FIELD_CLR(                                             \
+		((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 2)
+#define IE1_SET_TX_DESC_EN_HWSEQ_NO_CLR(txdesc_ie, value)                      \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 2)
+#define IE1_GET_TX_DESC_EN_HWEXSEQ(txdesc_ie)                                  \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0,    \
+			      0x1, 1)
+#define IE1_SET_TX_DESC_EN_HWEXSEQ(txdesc_ie, value)                           \
+	HALMAC_SET_DESC_FIELD_CLR(                                             \
+		((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 1)
+#define IE1_SET_TX_DESC_EN_HWEXSEQ_NO_CLR(txdesc_ie, value)                    \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 1)
+#define IE1_GET_TX_DESC_EN_DESC_ID(txdesc_ie)                                  \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0,    \
+			      0x1, 0)
+#define IE1_SET_TX_DESC_EN_DESC_ID(txdesc_ie, value)                           \
+	HALMAC_SET_DESC_FIELD_CLR(                                             \
+		((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 0)
+#define IE1_SET_TX_DESC_EN_DESC_ID_NO_CLR(txdesc_ie, value)                    \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 0)
+#define IE1_GET_TX_DESC_AMPDU_MAX_TIME(txdesc_ie)                              \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword1,    \
+			      0xff, 24)
+#define IE1_SET_TX_DESC_AMPDU_MAX_TIME(txdesc_ie, value)                       \
+	HALMAC_SET_DESC_FIELD_CLR(                                             \
+		((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0xff, 24)
+#define IE1_SET_TX_DESC_AMPDU_MAX_TIME_NO_CLR(txdesc_ie, value)                \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0xff, 24)
+#define IE1_GET_TX_DESC_P_AID(txdesc_ie)                                       \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword1,    \
+			      0x1ff, 15)
+#define IE1_SET_TX_DESC_P_AID(txdesc_ie, value)                                \
+	HALMAC_SET_DESC_FIELD_CLR(                                             \
+		((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0x1ff,    \
+		15)
+#define IE1_SET_TX_DESC_P_AID_NO_CLR(txdesc_ie, value)                         \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0x1ff,    \
+		15)
+#define IE1_GET_TX_DESC_MOREDATA(txdesc_ie)                                    \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword1,    \
+			      0x1, 14)
+#define IE1_SET_TX_DESC_MOREDATA(txdesc_ie, value)                             \
+	HALMAC_SET_DESC_FIELD_CLR(                                             \
+		((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0x1, 14)
+#define IE1_SET_TX_DESC_MOREDATA_NO_CLR(txdesc_ie, value)                      \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0x1, 14)
+#define IE1_GET_TX_DESC_SW_SEQ(txdesc_ie)                                      \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword1,    \
+			      0xfff, 0)
+#define IE1_SET_TX_DESC_SW_SEQ(txdesc_ie, value)                               \
+	HALMAC_SET_DESC_FIELD_CLR(                                             \
+		((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0xfff, 0)
+#define IE1_SET_TX_DESC_SW_SEQ_NO_CLR(txdesc_ie, value)                        \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0xfff, 0)
+#define IE2_GET_TX_DESC_IE_END(txdesc_ie)                                      \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0,    \
+			      0x1, 31)
+#define IE2_SET_TX_DESC_IE_END(txdesc_ie, value)                               \
+	HALMAC_SET_DESC_FIELD_CLR(                                             \
+		((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 31)
+#define IE2_SET_TX_DESC_IE_END_NO_CLR(txdesc_ie, value)                        \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 31)
+#define IE2_GET_TX_DESC_IE_UP(txdesc_ie)                                       \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0,    \
+			      0x1, 30)
+#define IE2_SET_TX_DESC_IE_UP(txdesc_ie, value)                                \
+	HALMAC_SET_DESC_FIELD_CLR(                                             \
+		((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 30)
+#define IE2_SET_TX_DESC_IE_UP_NO_CLR(txdesc_ie, value)                         \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 30)
+#define IE2_GET_TX_DESC_IE_NUM(txdesc_ie)                                      \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0,    \
+			      0xf, 24)
+#define IE2_SET_TX_DESC_IE_NUM(txdesc_ie, value)                               \
+	HALMAC_SET_DESC_FIELD_CLR(                                             \
+		((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0xf, 24)
+#define IE2_SET_TX_DESC_IE_NUM_NO_CLR(txdesc_ie, value)                        \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0xf, 24)
+#define IE2_GET_TX_DESC_ADDR_CAM(txdesc_ie)                                    \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0,    \
+			      0xff, 16)
+#define IE2_SET_TX_DESC_ADDR_CAM(txdesc_ie, value)                             \
+	HALMAC_SET_DESC_FIELD_CLR(                                             \
+		((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0xff, 16)
+#define IE2_SET_TX_DESC_ADDR_CAM_NO_CLR(txdesc_ie, value)                      \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0xff, 16)
+#define IE2_GET_TX_DESC_MULTIPLE_PORT(txdesc_ie)                               \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0,    \
+			      0x7, 12)
+#define IE2_SET_TX_DESC_MULTIPLE_PORT(txdesc_ie, value)                        \
+	HALMAC_SET_DESC_FIELD_CLR(                                             \
+		((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x7, 12)
+#define IE2_SET_TX_DESC_MULTIPLE_PORT_NO_CLR(txdesc_ie, value)                 \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x7, 12)
+#define IE2_GET_TX_DESC_RAW(txdesc_ie)                                         \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0,    \
+			      0x1, 11)
+#define IE2_SET_TX_DESC_RAW(txdesc_ie, value)                                  \
+	HALMAC_SET_DESC_FIELD_CLR(                                             \
+		((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 11)
+#define IE2_SET_TX_DESC_RAW_NO_CLR(txdesc_ie, value)                           \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 11)
+#define IE2_GET_TX_DESC_RDG_EN(txdesc_ie)                                      \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0,    \
+			      0x1, 10)
+#define IE2_SET_TX_DESC_RDG_EN(txdesc_ie, value)                               \
+	HALMAC_SET_DESC_FIELD_CLR(                                             \
+		((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 10)
+#define IE2_SET_TX_DESC_RDG_EN_NO_CLR(txdesc_ie, value)                        \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 10)
+#define IE2_GET_TX_DESC_SPECIAL_CW(txdesc_ie)                                  \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0,    \
+			      0x1, 7)
+#define IE2_SET_TX_DESC_SPECIAL_CW(txdesc_ie, value)                           \
+	HALMAC_SET_DESC_FIELD_CLR(                                             \
+		((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 7)
+#define IE2_SET_TX_DESC_SPECIAL_CW_NO_CLR(txdesc_ie, value)                    \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 7)
+#define IE2_GET_TX_DESC_POLLUTED(txdesc_ie)                                    \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0,    \
+			      0x1, 6)
+#define IE2_SET_TX_DESC_POLLUTED(txdesc_ie, value)                             \
+	HALMAC_SET_DESC_FIELD_CLR(                                             \
+		((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 6)
+#define IE2_SET_TX_DESC_POLLUTED_NO_CLR(txdesc_ie, value)                      \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 6)
+#define IE2_GET_TX_DESC_BT_NULL(txdesc_ie)                                     \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0,    \
+			      0x1, 5)
+#define IE2_SET_TX_DESC_BT_NULL(txdesc_ie, value)                              \
+	HALMAC_SET_DESC_FIELD_CLR(                                             \
+		((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 5)
+#define IE2_SET_TX_DESC_BT_NULL_NO_CLR(txdesc_ie, value)                       \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 5)
+#define IE2_GET_TX_DESC_NULL_1(txdesc_ie)                                      \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0,    \
+			      0x1, 4)
+#define IE2_SET_TX_DESC_NULL_1(txdesc_ie, value)                               \
+	HALMAC_SET_DESC_FIELD_CLR(                                             \
+		((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 4)
+#define IE2_SET_TX_DESC_NULL_1_NO_CLR(txdesc_ie, value)                        \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 4)
+#define IE2_GET_TX_DESC_NULL_0(txdesc_ie)                                      \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0,    \
+			      0x1, 3)
+#define IE2_SET_TX_DESC_NULL_0(txdesc_ie, value)                               \
+	HALMAC_SET_DESC_FIELD_CLR(                                             \
+		((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 3)
+#define IE2_SET_TX_DESC_NULL_0_NO_CLR(txdesc_ie, value)                        \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 3)
+#define IE2_GET_TX_DESC_TRI_FRAME(txdesc_ie)                                   \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0,    \
+			      0x1, 2)
+#define IE2_SET_TX_DESC_TRI_FRAME(txdesc_ie, value)                            \
+	HALMAC_SET_DESC_FIELD_CLR(                                             \
+		((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 2)
+#define IE2_SET_TX_DESC_TRI_FRAME_NO_CLR(txdesc_ie, value)                     \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 2)
+#define IE2_GET_TX_DESC_SPE_RPT(txdesc_ie)                                     \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0,    \
+			      0x1, 1)
+#define IE2_SET_TX_DESC_SPE_RPT(txdesc_ie, value)                              \
+	HALMAC_SET_DESC_FIELD_CLR(                                             \
+		((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 1)
+#define IE2_SET_TX_DESC_SPE_RPT_NO_CLR(txdesc_ie, value)                       \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 1)
+#define IE2_GET_TX_DESC_FTM_EN(txdesc_ie)                                      \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0,    \
+			      0x1, 0)
+#define IE2_SET_TX_DESC_FTM_EN(txdesc_ie, value)                               \
+	HALMAC_SET_DESC_FIELD_CLR(                                             \
+		((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 0)
+#define IE2_SET_TX_DESC_FTM_EN_NO_CLR(txdesc_ie, value)                        \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 0)
+#define IE2_GET_TX_DESC_MBSSID(txdesc_ie)                                      \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword1,    \
+			      0xf, 27)
+#define IE2_SET_TX_DESC_MBSSID(txdesc_ie, value)                               \
+	HALMAC_SET_DESC_FIELD_CLR(                                             \
+		((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0xf, 27)
+#define IE2_SET_TX_DESC_MBSSID_NO_CLR(txdesc_ie, value)                        \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0xf, 27)
+#define IE2_GET_TX_DESC_GROUP_BIT_IE_OFFSET(txdesc_ie)                         \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword1,    \
+			      0x7ff, 16)
+#define IE2_SET_TX_DESC_GROUP_BIT_IE_OFFSET(txdesc_ie, value)                  \
+	HALMAC_SET_DESC_FIELD_CLR(                                             \
+		((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0x7ff,    \
+		16)
+#define IE2_SET_TX_DESC_GROUP_BIT_IE_OFFSET_NO_CLR(txdesc_ie, value)           \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0x7ff,    \
+		16)
+#define IE2_GET_TX_DESC_RDG_NAV_EXT(txdesc_ie)                                 \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword1,    \
+			      0x1, 15)
+#define IE2_SET_TX_DESC_RDG_NAV_EXT(txdesc_ie, value)                          \
+	HALMAC_SET_DESC_FIELD_CLR(                                             \
+		((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0x1, 15)
+#define IE2_SET_TX_DESC_RDG_NAV_EXT_NO_CLR(txdesc_ie, value)                   \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0x1, 15)
+#define IE2_GET_TX_DESC_DROP_ID(txdesc_ie)                                     \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword1,    \
+			      0x3, 12)
+#define IE2_SET_TX_DESC_DROP_ID(txdesc_ie, value)                              \
+	HALMAC_SET_DESC_FIELD_CLR(                                             \
+		((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0x3, 12)
+#define IE2_SET_TX_DESC_DROP_ID_NO_CLR(txdesc_ie, value)                       \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0x3, 12)
+#define IE2_GET_TX_DESC_SW_DEFINE(txdesc_ie)                                   \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword1,    \
+			      0xfff, 0)
+#define IE2_SET_TX_DESC_SW_DEFINE(txdesc_ie, value)                            \
+	HALMAC_SET_DESC_FIELD_CLR(                                             \
+		((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0xfff, 0)
+#define IE2_SET_TX_DESC_SW_DEFINE_NO_CLR(txdesc_ie, value)                     \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0xfff, 0)
+#define IE3_GET_TX_DESC_IE_END(txdesc_ie)                                      \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0,    \
+			      0x1, 31)
+#define IE3_SET_TX_DESC_IE_END(txdesc_ie, value)                               \
+	HALMAC_SET_DESC_FIELD_CLR(                                             \
+		((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 31)
+#define IE3_SET_TX_DESC_IE_END_NO_CLR(txdesc_ie, value)                        \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 31)
+#define IE3_GET_TX_DESC_IE_UP(txdesc_ie)                                       \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0,    \
+			      0x1, 30)
+#define IE3_SET_TX_DESC_IE_UP(txdesc_ie, value)                                \
+	HALMAC_SET_DESC_FIELD_CLR(                                             \
+		((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 30)
+#define IE3_SET_TX_DESC_IE_UP_NO_CLR(txdesc_ie, value)                         \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 30)
+#define IE3_GET_TX_DESC_IE_NUM(txdesc_ie)                                      \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0,    \
+			      0xf, 24)
+#define IE3_SET_TX_DESC_IE_NUM(txdesc_ie, value)                               \
+	HALMAC_SET_DESC_FIELD_CLR(                                             \
+		((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0xf, 24)
+#define IE3_SET_TX_DESC_IE_NUM_NO_CLR(txdesc_ie, value)                        \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0xf, 24)
+#define IE3_GET_TX_DESC_DATA_SC(txdesc_ie)                                     \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0,    \
+			      0xf, 20)
+#define IE3_SET_TX_DESC_DATA_SC(txdesc_ie, value)                              \
+	HALMAC_SET_DESC_FIELD_CLR(                                             \
+		((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0xf, 20)
+#define IE3_SET_TX_DESC_DATA_SC_NO_CLR(txdesc_ie, value)                       \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0xf, 20)
+#define IE3_GET_TX_DESC_SIGNALING_TA_PKT_SC(txdesc_ie)                         \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0,    \
+			      0xf, 16)
+#define IE3_SET_TX_DESC_SIGNALING_TA_PKT_SC(txdesc_ie, value)                  \
+	HALMAC_SET_DESC_FIELD_CLR(                                             \
+		((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0xf, 16)
+#define IE3_SET_TX_DESC_SIGNALING_TA_PKT_SC_NO_CLR(txdesc_ie, value)           \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0xf, 16)
+#define IE3_GET_TX_DESC_CTRL_CNT(txdesc_ie)                                    \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0,    \
+			      0xf, 8)
+#define IE3_SET_TX_DESC_CTRL_CNT(txdesc_ie, value)                             \
+	HALMAC_SET_DESC_FIELD_CLR(                                             \
+		((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0xf, 8)
+#define IE3_SET_TX_DESC_CTRL_CNT_NO_CLR(txdesc_ie, value)                      \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0xf, 8)
+#define IE3_GET_TX_DESC_CTRL_CNT_VALID(txdesc_ie)                              \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0,    \
+			      0x1, 1)
+#define IE3_SET_TX_DESC_CTRL_CNT_VALID(txdesc_ie, value)                       \
+	HALMAC_SET_DESC_FIELD_CLR(                                             \
+		((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 1)
+#define IE3_SET_TX_DESC_CTRL_CNT_VALID_NO_CLR(txdesc_ie, value)                \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 1)
+#define IE3_GET_TX_DESC_SIGNALING_TA_PKT_EN(txdesc_ie)                         \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0,    \
+			      0x1, 0)
+#define IE3_SET_TX_DESC_SIGNALING_TA_PKT_EN(txdesc_ie, value)                  \
+	HALMAC_SET_DESC_FIELD_CLR(                                             \
+		((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 0)
+#define IE3_SET_TX_DESC_SIGNALING_TA_PKT_EN_NO_CLR(txdesc_ie, value)           \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 0)
+#define IE3_GET_TX_DESC_G_ID(txdesc_ie)                                        \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword1,    \
+			      0x3f, 24)
+#define IE3_SET_TX_DESC_G_ID(txdesc_ie, value)                                 \
+	HALMAC_SET_DESC_FIELD_CLR(                                             \
+		((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0x3f, 24)
+#define IE3_SET_TX_DESC_G_ID_NO_CLR(txdesc_ie, value)                          \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0x3f, 24)
+#define IE3_GET_TX_DESC_SND_TARGET(txdesc_ie)                                  \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword1,    \
+			      0xff, 16)
+#define IE3_SET_TX_DESC_SND_TARGET(txdesc_ie, value)                           \
+	HALMAC_SET_DESC_FIELD_CLR(                                             \
+		((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0xff, 16)
+#define IE3_SET_TX_DESC_SND_TARGET_NO_CLR(txdesc_ie, value)                    \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0xff, 16)
+#define IE3_GET_TX_DESC_CCA_RTS(txdesc_ie)                                     \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword1,    \
+			      0x3, 11)
+#define IE3_SET_TX_DESC_CCA_RTS(txdesc_ie, value)                              \
+	HALMAC_SET_DESC_FIELD_CLR(                                             \
+		((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0x3, 11)
+#define IE3_SET_TX_DESC_CCA_RTS_NO_CLR(txdesc_ie, value)                       \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0x3, 11)
+#define IE3_GET_TX_DESC_SND_PKT_SEL(txdesc_ie)                                 \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword1,    \
+			      0x3, 9)
+#define IE3_SET_TX_DESC_SND_PKT_SEL(txdesc_ie, value)                          \
+	HALMAC_SET_DESC_FIELD_CLR(                                             \
+		((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0x3, 9)
+#define IE3_SET_TX_DESC_SND_PKT_SEL_NO_CLR(txdesc_ie, value)                   \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0x3, 9)
+#define IE3_GET_TX_DESC_NDPA(txdesc_ie)                                        \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword1,    \
+			      0x3, 7)
+#define IE3_SET_TX_DESC_NDPA(txdesc_ie, value)                                 \
+	HALMAC_SET_DESC_FIELD_CLR(                                             \
+		((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0x3, 7)
+#define IE3_SET_TX_DESC_NDPA_NO_CLR(txdesc_ie, value)                          \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0x3, 7)
+#define IE3_GET_TX_DESC_MU_DATARATE(txdesc_ie)                                 \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword1,    \
+			      0x7f, 0)
+#define IE3_SET_TX_DESC_MU_DATARATE(txdesc_ie, value)                          \
+	HALMAC_SET_DESC_FIELD_CLR(                                             \
+		((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0x7f, 0)
+#define IE3_SET_TX_DESC_MU_DATARATE_NO_CLR(txdesc_ie, value)                   \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0x7f, 0)
+#define IE4_GET_TX_DESC_IE_END(txdesc_ie)                                      \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0,    \
+			      0x1, 31)
+#define IE4_SET_TX_DESC_IE_END(txdesc_ie, value)                               \
+	HALMAC_SET_DESC_FIELD_CLR(                                             \
+		((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 31)
+#define IE4_SET_TX_DESC_IE_END_NO_CLR(txdesc_ie, value)                        \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 31)
+#define IE4_GET_TX_DESC_IE_UP(txdesc_ie)                                       \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0,    \
+			      0x1, 30)
+#define IE4_SET_TX_DESC_IE_UP(txdesc_ie, value)                                \
+	HALMAC_SET_DESC_FIELD_CLR(                                             \
+		((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 30)
+#define IE4_SET_TX_DESC_IE_UP_NO_CLR(txdesc_ie, value)                         \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 30)
+#define IE4_GET_TX_DESC_IE_NUM(txdesc_ie)                                      \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0,    \
+			      0xf, 24)
+#define IE4_SET_TX_DESC_IE_NUM(txdesc_ie, value)                               \
+	HALMAC_SET_DESC_FIELD_CLR(                                             \
+		((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0xf, 24)
+#define IE4_SET_TX_DESC_IE_NUM_NO_CLR(txdesc_ie, value)                        \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0xf, 24)
+#define IE4_GET_TX_DESC_VCS_STBC(txdesc_ie)                                    \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0,    \
+			      0x3, 10)
+#define IE4_SET_TX_DESC_VCS_STBC(txdesc_ie, value)                             \
+	HALMAC_SET_DESC_FIELD_CLR(                                             \
+		((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x3, 10)
+#define IE4_SET_TX_DESC_VCS_STBC_NO_CLR(txdesc_ie, value)                      \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x3, 10)
+#define IE4_GET_TX_DESC_DATA_STBC(txdesc_ie)                                   \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0,    \
+			      0x3, 8)
+#define IE4_SET_TX_DESC_DATA_STBC(txdesc_ie, value)                            \
+	HALMAC_SET_DESC_FIELD_CLR(                                             \
+		((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x3, 8)
+#define IE4_SET_TX_DESC_DATA_STBC_NO_CLR(txdesc_ie, value)                     \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x3, 8)
+#define IE4_GET_TX_DESC_DATA_LDPC(txdesc_ie)                                   \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0,    \
+			      0x1, 2)
+#define IE4_SET_TX_DESC_DATA_LDPC(txdesc_ie, value)                            \
+	HALMAC_SET_DESC_FIELD_CLR(                                             \
+		((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 2)
+#define IE4_SET_TX_DESC_DATA_LDPC_NO_CLR(txdesc_ie, value)                     \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 2)
+#define IE4_GET_TX_DESC_GF(txdesc_ie)                                          \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0,    \
+			      0x1, 1)
+#define IE4_SET_TX_DESC_GF(txdesc_ie, value)                                   \
+	HALMAC_SET_DESC_FIELD_CLR(                                             \
+		((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 1)
+#define IE4_SET_TX_DESC_GF_NO_CLR(txdesc_ie, value)                            \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 1)
+#define IE4_GET_TX_DESC_LSIG_TXOP_EN(txdesc_ie)                                \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0,    \
+			      0x1, 0)
+#define IE4_SET_TX_DESC_LSIG_TXOP_EN(txdesc_ie, value)                         \
+	HALMAC_SET_DESC_FIELD_CLR(                                             \
+		((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 0)
+#define IE4_SET_TX_DESC_LSIG_TXOP_EN_NO_CLR(txdesc_ie, value)                  \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 0)
+#define IE4_GET_TX_DESC_PATH_MAPA(txdesc_ie)                                   \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword1,    \
+			      0x3, 30)
+#define IE4_SET_TX_DESC_PATH_MAPA(txdesc_ie, value)                            \
+	HALMAC_SET_DESC_FIELD_CLR(                                             \
+		((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0x3, 30)
+#define IE4_SET_TX_DESC_PATH_MAPA_NO_CLR(txdesc_ie, value)                     \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0x3, 30)
+#define IE4_GET_TX_DESC_PATH_MAPB(txdesc_ie)                                   \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword1,    \
+			      0x3, 28)
+#define IE4_SET_TX_DESC_PATH_MAPB(txdesc_ie, value)                            \
+	HALMAC_SET_DESC_FIELD_CLR(                                             \
+		((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0x3, 28)
+#define IE4_SET_TX_DESC_PATH_MAPB_NO_CLR(txdesc_ie, value)                     \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0x3, 28)
+#define IE4_GET_TX_DESC_PATH_MAPC(txdesc_ie)                                   \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword1,    \
+			      0x3, 26)
+#define IE4_SET_TX_DESC_PATH_MAPC(txdesc_ie, value)                            \
+	HALMAC_SET_DESC_FIELD_CLR(                                             \
+		((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0x3, 26)
+#define IE4_SET_TX_DESC_PATH_MAPC_NO_CLR(txdesc_ie, value)                     \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0x3, 26)
+#define IE4_GET_TX_DESC_PATH_MAPD(txdesc_ie)                                   \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword1,    \
+			      0x3, 24)
+#define IE4_SET_TX_DESC_PATH_MAPD(txdesc_ie, value)                            \
+	HALMAC_SET_DESC_FIELD_CLR(                                             \
+		((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0x3, 24)
+#define IE4_SET_TX_DESC_PATH_MAPD_NO_CLR(txdesc_ie, value)                     \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0x3, 24)
+#define IE4_GET_TX_DESC_ANTSEL_A(txdesc_ie)                                    \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword1,    \
+			      0xf, 20)
+#define IE4_SET_TX_DESC_ANTSEL_A(txdesc_ie, value)                             \
+	HALMAC_SET_DESC_FIELD_CLR(                                             \
+		((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0xf, 20)
+#define IE4_SET_TX_DESC_ANTSEL_A_NO_CLR(txdesc_ie, value)                      \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0xf, 20)
+#define IE4_GET_TX_DESC_ANTSEL_B(txdesc_ie)                                    \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword1,    \
+			      0xf, 16)
+#define IE4_SET_TX_DESC_ANTSEL_B(txdesc_ie, value)                             \
+	HALMAC_SET_DESC_FIELD_CLR(                                             \
+		((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0xf, 16)
+#define IE4_SET_TX_DESC_ANTSEL_B_NO_CLR(txdesc_ie, value)                      \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0xf, 16)
+#define IE4_GET_TX_DESC_ANTSEL_C(txdesc_ie)                                    \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword1,    \
+			      0xf, 12)
+#define IE4_SET_TX_DESC_ANTSEL_C(txdesc_ie, value)                             \
+	HALMAC_SET_DESC_FIELD_CLR(                                             \
+		((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0xf, 12)
+#define IE4_SET_TX_DESC_ANTSEL_C_NO_CLR(txdesc_ie, value)                      \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0xf, 12)
+#define IE4_GET_TX_DESC_ANTSEL_D(txdesc_ie)                                    \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword1,    \
+			      0xf, 8)
+#define IE4_SET_TX_DESC_ANTSEL_D(txdesc_ie, value)                             \
+	HALMAC_SET_DESC_FIELD_CLR(                                             \
+		((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0xf, 8)
+#define IE4_SET_TX_DESC_ANTSEL_D_NO_CLR(txdesc_ie, value)                      \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0xf, 8)
+#define IE4_GET_TX_DESC_NTX_PATH_EN(txdesc_ie)                                 \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword1,    \
+			      0xf, 4)
+#define IE4_SET_TX_DESC_NTX_PATH_EN(txdesc_ie, value)                          \
+	HALMAC_SET_DESC_FIELD_CLR(                                             \
+		((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0xf, 4)
+#define IE4_SET_TX_DESC_NTX_PATH_EN_NO_CLR(txdesc_ie, value)                   \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0xf, 4)
+#define IE4_GET_TX_DESC_ANTLSEL_EN(txdesc_ie)                                  \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword1,    \
+			      0x1, 3)
+#define IE4_SET_TX_DESC_ANTLSEL_EN(txdesc_ie, value)                           \
+	HALMAC_SET_DESC_FIELD_CLR(                                             \
+		((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0x1, 3)
+#define IE4_SET_TX_DESC_ANTLSEL_EN_NO_CLR(txdesc_ie, value)                    \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0x1, 3)
+#define IE4_GET_TX_DESC_TXPWR_OFSET_TYPE(txdesc_ie)                            \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword1,    \
+			      0x3, 0)
+#define IE4_SET_TX_DESC_TXPWR_OFSET_TYPE(txdesc_ie, value)                     \
+	HALMAC_SET_DESC_FIELD_CLR(                                             \
+		((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0x3, 0)
+#define IE4_SET_TX_DESC_TXPWR_OFSET_TYPE_NO_CLR(txdesc_ie, value)              \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0x3, 0)
+#define IE5_GET_TX_DESC_IE_END(txdesc_ie)                                      \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0,    \
+			      0x1, 31)
+#define IE5_SET_TX_DESC_IE_END(txdesc_ie, value)                               \
+	HALMAC_SET_DESC_FIELD_CLR(                                             \
+		((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 31)
+#define IE5_SET_TX_DESC_IE_END_NO_CLR(txdesc_ie, value)                        \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 31)
+#define IE5_GET_TX_DESC_IE_UP(txdesc_ie)                                       \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0,    \
+			      0x1, 30)
+#define IE5_SET_TX_DESC_IE_UP(txdesc_ie, value)                                \
+	HALMAC_SET_DESC_FIELD_CLR(                                             \
+		((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 30)
+#define IE5_SET_TX_DESC_IE_UP_NO_CLR(txdesc_ie, value)                         \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 30)
+#define IE5_GET_TX_DESC_IE_NUM(txdesc_ie)                                      \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0,    \
+			      0xf, 24)
+#define IE5_SET_TX_DESC_IE_NUM(txdesc_ie, value)                               \
+	HALMAC_SET_DESC_FIELD_CLR(                                             \
+		((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0xf, 24)
+#define IE5_SET_TX_DESC_IE_NUM_NO_CLR(txdesc_ie, value)                        \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0xf, 24)
+#define IE5_GET_TX_DESC_LEN1_L(txdesc_ie)                                      \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0,    \
+			      0x7f, 17)
+#define IE5_SET_TX_DESC_LEN1_L(txdesc_ie, value)                               \
+	HALMAC_SET_DESC_FIELD_CLR(                                             \
+		((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x7f, 17)
+#define IE5_SET_TX_DESC_LEN1_L_NO_CLR(txdesc_ie, value)                        \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x7f, 17)
+#define IE5_GET_TX_DESC_LEN0(txdesc_ie)                                        \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0,    \
+			      0x1fff, 4)
+#define IE5_SET_TX_DESC_LEN0(txdesc_ie, value)                                 \
+	HALMAC_SET_DESC_FIELD_CLR(                                             \
+		((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1fff,   \
+		4)
+#define IE5_SET_TX_DESC_LEN0_NO_CLR(txdesc_ie, value)                          \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1fff,   \
+		4)
+#define IE5_GET_TX_DESC_PKT_NUM(txdesc_ie)                                     \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0,    \
+			      0xf, 0)
+#define IE5_SET_TX_DESC_PKT_NUM(txdesc_ie, value)                              \
+	HALMAC_SET_DESC_FIELD_CLR(                                             \
+		((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0xf, 0)
+#define IE5_SET_TX_DESC_PKT_NUM_NO_CLR(txdesc_ie, value)                       \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0xf, 0)
+#define IE5_GET_TX_DESC_LEN3(txdesc_ie)                                        \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword1,    \
+			      0x1fff, 19)
+#define IE5_SET_TX_DESC_LEN3(txdesc_ie, value)                                 \
+	HALMAC_SET_DESC_FIELD_CLR(                                             \
+		((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0x1fff,   \
+		19)
+#define IE5_SET_TX_DESC_LEN3_NO_CLR(txdesc_ie, value)                          \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0x1fff,   \
+		19)
+#define IE5_GET_TX_DESC_LEN2(txdesc_ie)                                        \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword1,    \
+			      0x1fff, 6)
+#define IE5_SET_TX_DESC_LEN2(txdesc_ie, value)                                 \
+	HALMAC_SET_DESC_FIELD_CLR(                                             \
+		((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0x1fff,   \
+		6)
+#define IE5_SET_TX_DESC_LEN2_NO_CLR(txdesc_ie, value)                          \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0x1fff,   \
+		6)
+#define IE5_GET_TX_DESC_LEN1_H(txdesc_ie)                                      \
+	HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword1,    \
+			      0x3f, 0)
+#define IE5_SET_TX_DESC_LEN1_H(txdesc_ie, value)                               \
+	HALMAC_SET_DESC_FIELD_CLR(                                             \
+		((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0x3f, 0)
+#define IE5_SET_TX_DESC_LEN1_H_NO_CLR(txdesc_ie, value)                        \
+	HALMAC_SET_DESC_FIELD_NO_CLR(                                          \
+		((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0x3f, 0)
+
+#endif
+
+#endif
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/halmac/halmac_tx_desc_ie_chip.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/halmac/halmac_tx_desc_ie_chip.h
--- linux-5.6.3/3rdparty/rtl8821ce/hal/halmac/halmac_tx_desc_ie_chip.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/halmac/halmac_tx_desc_ie_chip.h	2020-04-10 16:35:06.817660114 +0300
@@ -0,0 +1,438 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ ******************************************************************************/
+
+#ifndef _HALMAC_TX_DESC_IE_CHIP_H_
+#define _HALMAC_TX_DESC_IE_CHIP_H_
+#if (HALMAC_8814B_SUPPORT)
+
+#define IE0_GET_TX_DESC_IE_END_8814B(txdesc_ie)                                \
+	IE0_GET_TX_DESC_IE_END(txdesc_ie)
+#define IE0_SET_TX_DESC_IE_END_8814B(txdesc_ie, value)                         \
+	IE0_SET_TX_DESC_IE_END(txdesc_ie, value)
+#define IE0_GET_TX_DESC_IE_UP_8814B(txdesc_ie) IE0_GET_TX_DESC_IE_UP(txdesc_ie)
+#define IE0_SET_TX_DESC_IE_UP_8814B(txdesc_ie, value)                          \
+	IE0_SET_TX_DESC_IE_UP(txdesc_ie, value)
+#define IE0_GET_TX_DESC_IE_NUM_8814B(txdesc_ie)                                \
+	IE0_GET_TX_DESC_IE_NUM(txdesc_ie)
+#define IE0_SET_TX_DESC_IE_NUM_8814B(txdesc_ie, value)                         \
+	IE0_SET_TX_DESC_IE_NUM(txdesc_ie, value)
+#define IE0_GET_TX_DESC_ARFR_TABLE_SEL_8814B(txdesc_ie)                        \
+	IE0_GET_TX_DESC_ARFR_TABLE_SEL(txdesc_ie)
+#define IE0_SET_TX_DESC_ARFR_TABLE_SEL_8814B(txdesc_ie, value)                 \
+	IE0_SET_TX_DESC_ARFR_TABLE_SEL(txdesc_ie, value)
+#define IE0_GET_TX_DESC_ARFR_HT_EN_8814B(txdesc_ie)                            \
+	IE0_GET_TX_DESC_ARFR_HT_EN(txdesc_ie)
+#define IE0_SET_TX_DESC_ARFR_HT_EN_8814B(txdesc_ie, value)                     \
+	IE0_SET_TX_DESC_ARFR_HT_EN(txdesc_ie, value)
+#define IE0_GET_TX_DESC_ARFR_OFDM_EN_8814B(txdesc_ie)                          \
+	IE0_GET_TX_DESC_ARFR_OFDM_EN(txdesc_ie)
+#define IE0_SET_TX_DESC_ARFR_OFDM_EN_8814B(txdesc_ie, value)                   \
+	IE0_SET_TX_DESC_ARFR_OFDM_EN(txdesc_ie, value)
+#define IE0_GET_TX_DESC_ARFR_CCK_EN_8814B(txdesc_ie)                           \
+	IE0_GET_TX_DESC_ARFR_CCK_EN(txdesc_ie)
+#define IE0_SET_TX_DESC_ARFR_CCK_EN_8814B(txdesc_ie, value)                    \
+	IE0_SET_TX_DESC_ARFR_CCK_EN(txdesc_ie, value)
+#define IE0_GET_TX_DESC_HW_RTS_EN_8814B(txdesc_ie)                             \
+	IE0_GET_TX_DESC_HW_RTS_EN(txdesc_ie)
+#define IE0_SET_TX_DESC_HW_RTS_EN_8814B(txdesc_ie, value)                      \
+	IE0_SET_TX_DESC_HW_RTS_EN(txdesc_ie, value)
+#define IE0_GET_TX_DESC_RTS_EN_8814B(txdesc_ie)                                \
+	IE0_GET_TX_DESC_RTS_EN(txdesc_ie)
+#define IE0_SET_TX_DESC_RTS_EN_8814B(txdesc_ie, value)                         \
+	IE0_SET_TX_DESC_RTS_EN(txdesc_ie, value)
+#define IE0_GET_TX_DESC_CTS2SELF_8814B(txdesc_ie)                              \
+	IE0_GET_TX_DESC_CTS2SELF(txdesc_ie)
+#define IE0_SET_TX_DESC_CTS2SELF_8814B(txdesc_ie, value)                       \
+	IE0_SET_TX_DESC_CTS2SELF(txdesc_ie, value)
+#define IE0_GET_TX_DESC_RTY_LMT_EN_8814B(txdesc_ie)                            \
+	IE0_GET_TX_DESC_RTY_LMT_EN(txdesc_ie)
+#define IE0_SET_TX_DESC_RTY_LMT_EN_8814B(txdesc_ie, value)                     \
+	IE0_SET_TX_DESC_RTY_LMT_EN(txdesc_ie, value)
+#define IE0_GET_TX_DESC_RTS_SHORT_8814B(txdesc_ie)                             \
+	IE0_GET_TX_DESC_RTS_SHORT(txdesc_ie)
+#define IE0_SET_TX_DESC_RTS_SHORT_8814B(txdesc_ie, value)                      \
+	IE0_SET_TX_DESC_RTS_SHORT(txdesc_ie, value)
+#define IE0_GET_TX_DESC_DISDATAFB_8814B(txdesc_ie)                             \
+	IE0_GET_TX_DESC_DISDATAFB(txdesc_ie)
+#define IE0_SET_TX_DESC_DISDATAFB_8814B(txdesc_ie, value)                      \
+	IE0_SET_TX_DESC_DISDATAFB(txdesc_ie, value)
+#define IE0_GET_TX_DESC_DISRTSFB_8814B(txdesc_ie)                              \
+	IE0_GET_TX_DESC_DISRTSFB(txdesc_ie)
+#define IE0_SET_TX_DESC_DISRTSFB_8814B(txdesc_ie, value)                       \
+	IE0_SET_TX_DESC_DISRTSFB(txdesc_ie, value)
+#define IE0_GET_TX_DESC_DATA_SHORT_8814B(txdesc_ie)                            \
+	IE0_GET_TX_DESC_DATA_SHORT(txdesc_ie)
+#define IE0_SET_TX_DESC_DATA_SHORT_8814B(txdesc_ie, value)                     \
+	IE0_SET_TX_DESC_DATA_SHORT(txdesc_ie, value)
+#define IE0_GET_TX_DESC_TRY_RATE_8814B(txdesc_ie)                              \
+	IE0_GET_TX_DESC_TRY_RATE(txdesc_ie)
+#define IE0_SET_TX_DESC_TRY_RATE_8814B(txdesc_ie, value)                       \
+	IE0_SET_TX_DESC_TRY_RATE(txdesc_ie, value)
+#define IE0_GET_TX_DESC_USERATE_8814B(txdesc_ie)                               \
+	IE0_GET_TX_DESC_USERATE(txdesc_ie)
+#define IE0_SET_TX_DESC_USERATE_8814B(txdesc_ie, value)                        \
+	IE0_SET_TX_DESC_USERATE(txdesc_ie, value)
+#define IE0_GET_TX_DESC_RTS_RTY_LOWEST_RATE_8814B(txdesc_ie)                   \
+	IE0_GET_TX_DESC_RTS_RTY_LOWEST_RATE(txdesc_ie)
+#define IE0_SET_TX_DESC_RTS_RTY_LOWEST_RATE_8814B(txdesc_ie, value)            \
+	IE0_SET_TX_DESC_RTS_RTY_LOWEST_RATE(txdesc_ie, value)
+#define IE0_GET_TX_DESC_DATA_RTY_LOWEST_RATE_8814B(txdesc_ie)                  \
+	IE0_GET_TX_DESC_DATA_RTY_LOWEST_RATE(txdesc_ie)
+#define IE0_SET_TX_DESC_DATA_RTY_LOWEST_RATE_8814B(txdesc_ie, value)           \
+	IE0_SET_TX_DESC_DATA_RTY_LOWEST_RATE(txdesc_ie, value)
+#define IE0_GET_TX_DESC_RTS_DATA_RTY_LMT_8814B(txdesc_ie)                      \
+	IE0_GET_TX_DESC_RTS_DATA_RTY_LMT(txdesc_ie)
+#define IE0_SET_TX_DESC_RTS_DATA_RTY_LMT_8814B(txdesc_ie, value)               \
+	IE0_SET_TX_DESC_RTS_DATA_RTY_LMT(txdesc_ie, value)
+#define IE0_GET_TX_DESC_DATA_BW_8814B(txdesc_ie)                               \
+	IE0_GET_TX_DESC_DATA_BW(txdesc_ie)
+#define IE0_SET_TX_DESC_DATA_BW_8814B(txdesc_ie, value)                        \
+	IE0_SET_TX_DESC_DATA_BW(txdesc_ie, value)
+#define IE0_GET_TX_DESC_RTSRATE_8814B(txdesc_ie)                               \
+	IE0_GET_TX_DESC_RTSRATE(txdesc_ie)
+#define IE0_SET_TX_DESC_RTSRATE_8814B(txdesc_ie, value)                        \
+	IE0_SET_TX_DESC_RTSRATE(txdesc_ie, value)
+#define IE0_GET_TX_DESC_DATARATE_8814B(txdesc_ie)                              \
+	IE0_GET_TX_DESC_DATARATE(txdesc_ie)
+#define IE0_SET_TX_DESC_DATARATE_8814B(txdesc_ie, value)                       \
+	IE0_SET_TX_DESC_DATARATE(txdesc_ie, value)
+#define IE1_GET_TX_DESC_IE_END_8814B(txdesc_ie)                                \
+	IE1_GET_TX_DESC_IE_END(txdesc_ie)
+#define IE1_SET_TX_DESC_IE_END_8814B(txdesc_ie, value)                         \
+	IE1_SET_TX_DESC_IE_END(txdesc_ie, value)
+#define IE1_GET_TX_DESC_IE_UP_8814B(txdesc_ie) IE1_GET_TX_DESC_IE_UP(txdesc_ie)
+#define IE1_SET_TX_DESC_IE_UP_8814B(txdesc_ie, value)                          \
+	IE1_SET_TX_DESC_IE_UP(txdesc_ie, value)
+#define IE1_GET_TX_DESC_IE_NUM_8814B(txdesc_ie)                                \
+	IE1_GET_TX_DESC_IE_NUM(txdesc_ie)
+#define IE1_SET_TX_DESC_IE_NUM_8814B(txdesc_ie, value)                         \
+	IE1_SET_TX_DESC_IE_NUM(txdesc_ie, value)
+#define IE1_GET_TX_DESC_AMPDU_DENSITY_8814B(txdesc_ie)                         \
+	IE1_GET_TX_DESC_AMPDU_DENSITY(txdesc_ie)
+#define IE1_SET_TX_DESC_AMPDU_DENSITY_8814B(txdesc_ie, value)                  \
+	IE1_SET_TX_DESC_AMPDU_DENSITY(txdesc_ie, value)
+#define IE1_GET_TX_DESC_MAX_AGG_NUM_8814B(txdesc_ie)                           \
+	IE1_GET_TX_DESC_MAX_AGG_NUM(txdesc_ie)
+#define IE1_SET_TX_DESC_MAX_AGG_NUM_8814B(txdesc_ie, value)                    \
+	IE1_SET_TX_DESC_MAX_AGG_NUM(txdesc_ie, value)
+#define IE1_GET_TX_DESC_SECTYPE_8814B(txdesc_ie)                               \
+	IE1_GET_TX_DESC_SECTYPE(txdesc_ie)
+#define IE1_SET_TX_DESC_SECTYPE_8814B(txdesc_ie, value)                        \
+	IE1_SET_TX_DESC_SECTYPE(txdesc_ie, value)
+#define IE1_GET_TX_DESC_MOREFRAG_8814B(txdesc_ie)                              \
+	IE1_GET_TX_DESC_MOREFRAG(txdesc_ie)
+#define IE1_SET_TX_DESC_MOREFRAG_8814B(txdesc_ie, value)                       \
+	IE1_SET_TX_DESC_MOREFRAG(txdesc_ie, value)
+#define IE1_GET_TX_DESC_NOACM_8814B(txdesc_ie) IE1_GET_TX_DESC_NOACM(txdesc_ie)
+#define IE1_SET_TX_DESC_NOACM_8814B(txdesc_ie, value)                          \
+	IE1_SET_TX_DESC_NOACM(txdesc_ie, value)
+#define IE1_GET_TX_DESC_BCNPKT_TSF_CTRL_8814B(txdesc_ie)                       \
+	IE1_GET_TX_DESC_BCNPKT_TSF_CTRL(txdesc_ie)
+#define IE1_SET_TX_DESC_BCNPKT_TSF_CTRL_8814B(txdesc_ie, value)                \
+	IE1_SET_TX_DESC_BCNPKT_TSF_CTRL(txdesc_ie, value)
+#define IE1_GET_TX_DESC_NAVUSEHDR_8814B(txdesc_ie)                             \
+	IE1_GET_TX_DESC_NAVUSEHDR(txdesc_ie)
+#define IE1_SET_TX_DESC_NAVUSEHDR_8814B(txdesc_ie, value)                      \
+	IE1_SET_TX_DESC_NAVUSEHDR(txdesc_ie, value)
+#define IE1_GET_TX_DESC_HTC_8814B(txdesc_ie) IE1_GET_TX_DESC_HTC(txdesc_ie)
+#define IE1_SET_TX_DESC_HTC_8814B(txdesc_ie, value)                            \
+	IE1_SET_TX_DESC_HTC(txdesc_ie, value)
+#define IE1_GET_TX_DESC_BMC_8814B(txdesc_ie) IE1_GET_TX_DESC_BMC(txdesc_ie)
+#define IE1_SET_TX_DESC_BMC_8814B(txdesc_ie, value)                            \
+	IE1_SET_TX_DESC_BMC(txdesc_ie, value)
+#define IE1_GET_TX_DESC_TX_PKT_AFTER_PIFS_8814B(txdesc_ie)                     \
+	IE1_GET_TX_DESC_TX_PKT_AFTER_PIFS(txdesc_ie)
+#define IE1_SET_TX_DESC_TX_PKT_AFTER_PIFS_8814B(txdesc_ie, value)              \
+	IE1_SET_TX_DESC_TX_PKT_AFTER_PIFS(txdesc_ie, value)
+#define IE1_GET_TX_DESC_USE_MAX_TIME_EN_8814B(txdesc_ie)                       \
+	IE1_GET_TX_DESC_USE_MAX_TIME_EN(txdesc_ie)
+#define IE1_SET_TX_DESC_USE_MAX_TIME_EN_8814B(txdesc_ie, value)                \
+	IE1_SET_TX_DESC_USE_MAX_TIME_EN(txdesc_ie, value)
+#define IE1_GET_TX_DESC_HW_SSN_SEL_8814B(txdesc_ie)                            \
+	IE1_GET_TX_DESC_HW_SSN_SEL(txdesc_ie)
+#define IE1_SET_TX_DESC_HW_SSN_SEL_8814B(txdesc_ie, value)                     \
+	IE1_SET_TX_DESC_HW_SSN_SEL(txdesc_ie, value)
+#define IE1_GET_TX_DESC_DISQSELSEQ_8814B(txdesc_ie)                            \
+	IE1_GET_TX_DESC_DISQSELSEQ(txdesc_ie)
+#define IE1_SET_TX_DESC_DISQSELSEQ_8814B(txdesc_ie, value)                     \
+	IE1_SET_TX_DESC_DISQSELSEQ(txdesc_ie, value)
+#define IE1_GET_TX_DESC_EN_HWSEQ_8814B(txdesc_ie)                              \
+	IE1_GET_TX_DESC_EN_HWSEQ(txdesc_ie)
+#define IE1_SET_TX_DESC_EN_HWSEQ_8814B(txdesc_ie, value)                       \
+	IE1_SET_TX_DESC_EN_HWSEQ(txdesc_ie, value)
+#define IE1_GET_TX_DESC_EN_HWEXSEQ_8814B(txdesc_ie)                            \
+	IE1_GET_TX_DESC_EN_HWEXSEQ(txdesc_ie)
+#define IE1_SET_TX_DESC_EN_HWEXSEQ_8814B(txdesc_ie, value)                     \
+	IE1_SET_TX_DESC_EN_HWEXSEQ(txdesc_ie, value)
+#define IE1_GET_TX_DESC_EN_DESC_ID_8814B(txdesc_ie)                            \
+	IE1_GET_TX_DESC_EN_DESC_ID(txdesc_ie)
+#define IE1_SET_TX_DESC_EN_DESC_ID_8814B(txdesc_ie, value)                     \
+	IE1_SET_TX_DESC_EN_DESC_ID(txdesc_ie, value)
+#define IE1_GET_TX_DESC_AMPDU_MAX_TIME_8814B(txdesc_ie)                        \
+	IE1_GET_TX_DESC_AMPDU_MAX_TIME(txdesc_ie)
+#define IE1_SET_TX_DESC_AMPDU_MAX_TIME_8814B(txdesc_ie, value)                 \
+	IE1_SET_TX_DESC_AMPDU_MAX_TIME(txdesc_ie, value)
+#define IE1_GET_TX_DESC_P_AID_8814B(txdesc_ie) IE1_GET_TX_DESC_P_AID(txdesc_ie)
+#define IE1_SET_TX_DESC_P_AID_8814B(txdesc_ie, value)                          \
+	IE1_SET_TX_DESC_P_AID(txdesc_ie, value)
+#define IE1_GET_TX_DESC_MOREDATA_8814B(txdesc_ie)                              \
+	IE1_GET_TX_DESC_MOREDATA(txdesc_ie)
+#define IE1_SET_TX_DESC_MOREDATA_8814B(txdesc_ie, value)                       \
+	IE1_SET_TX_DESC_MOREDATA(txdesc_ie, value)
+#define IE1_GET_TX_DESC_SW_SEQ_8814B(txdesc_ie)                                \
+	IE1_GET_TX_DESC_SW_SEQ(txdesc_ie)
+#define IE1_SET_TX_DESC_SW_SEQ_8814B(txdesc_ie, value)                         \
+	IE1_SET_TX_DESC_SW_SEQ(txdesc_ie, value)
+#define IE2_GET_TX_DESC_IE_END_8814B(txdesc_ie)                                \
+	IE2_GET_TX_DESC_IE_END(txdesc_ie)
+#define IE2_SET_TX_DESC_IE_END_8814B(txdesc_ie, value)                         \
+	IE2_SET_TX_DESC_IE_END(txdesc_ie, value)
+#define IE2_GET_TX_DESC_IE_UP_8814B(txdesc_ie) IE2_GET_TX_DESC_IE_UP(txdesc_ie)
+#define IE2_SET_TX_DESC_IE_UP_8814B(txdesc_ie, value)                          \
+	IE2_SET_TX_DESC_IE_UP(txdesc_ie, value)
+#define IE2_GET_TX_DESC_IE_NUM_8814B(txdesc_ie)                                \
+	IE2_GET_TX_DESC_IE_NUM(txdesc_ie)
+#define IE2_SET_TX_DESC_IE_NUM_8814B(txdesc_ie, value)                         \
+	IE2_SET_TX_DESC_IE_NUM(txdesc_ie, value)
+#define IE2_GET_TX_DESC_ADDR_CAM_8814B(txdesc_ie)                              \
+	IE2_GET_TX_DESC_ADDR_CAM(txdesc_ie)
+#define IE2_SET_TX_DESC_ADDR_CAM_8814B(txdesc_ie, value)                       \
+	IE2_SET_TX_DESC_ADDR_CAM(txdesc_ie, value)
+#define IE2_GET_TX_DESC_MULTIPLE_PORT_8814B(txdesc_ie)                         \
+	IE2_GET_TX_DESC_MULTIPLE_PORT(txdesc_ie)
+#define IE2_SET_TX_DESC_MULTIPLE_PORT_8814B(txdesc_ie, value)                  \
+	IE2_SET_TX_DESC_MULTIPLE_PORT(txdesc_ie, value)
+#define IE2_GET_TX_DESC_RAW_8814B(txdesc_ie) IE2_GET_TX_DESC_RAW(txdesc_ie)
+#define IE2_SET_TX_DESC_RAW_8814B(txdesc_ie, value)                            \
+	IE2_SET_TX_DESC_RAW(txdesc_ie, value)
+#define IE2_GET_TX_DESC_RDG_EN_8814B(txdesc_ie)                                \
+	IE2_GET_TX_DESC_RDG_EN(txdesc_ie)
+#define IE2_SET_TX_DESC_RDG_EN_8814B(txdesc_ie, value)                         \
+	IE2_SET_TX_DESC_RDG_EN(txdesc_ie, value)
+#define IE2_GET_TX_DESC_SPECIAL_CW_8814B(txdesc_ie)                            \
+	IE2_GET_TX_DESC_SPECIAL_CW(txdesc_ie)
+#define IE2_SET_TX_DESC_SPECIAL_CW_8814B(txdesc_ie, value)                     \
+	IE2_SET_TX_DESC_SPECIAL_CW(txdesc_ie, value)
+#define IE2_GET_TX_DESC_POLLUTED_8814B(txdesc_ie)                              \
+	IE2_GET_TX_DESC_POLLUTED(txdesc_ie)
+#define IE2_SET_TX_DESC_POLLUTED_8814B(txdesc_ie, value)                       \
+	IE2_SET_TX_DESC_POLLUTED(txdesc_ie, value)
+#define IE2_GET_TX_DESC_BT_NULL_8814B(txdesc_ie)                               \
+	IE2_GET_TX_DESC_BT_NULL(txdesc_ie)
+#define IE2_SET_TX_DESC_BT_NULL_8814B(txdesc_ie, value)                        \
+	IE2_SET_TX_DESC_BT_NULL(txdesc_ie, value)
+#define IE2_GET_TX_DESC_NULL_1_8814B(txdesc_ie)                                \
+	IE2_GET_TX_DESC_NULL_1(txdesc_ie)
+#define IE2_SET_TX_DESC_NULL_1_8814B(txdesc_ie, value)                         \
+	IE2_SET_TX_DESC_NULL_1(txdesc_ie, value)
+#define IE2_GET_TX_DESC_NULL_0_8814B(txdesc_ie)                                \
+	IE2_GET_TX_DESC_NULL_0(txdesc_ie)
+#define IE2_SET_TX_DESC_NULL_0_8814B(txdesc_ie, value)                         \
+	IE2_SET_TX_DESC_NULL_0(txdesc_ie, value)
+#define IE2_GET_TX_DESC_TRI_FRAME_8814B(txdesc_ie)                             \
+	IE2_GET_TX_DESC_TRI_FRAME(txdesc_ie)
+#define IE2_SET_TX_DESC_TRI_FRAME_8814B(txdesc_ie, value)                      \
+	IE2_SET_TX_DESC_TRI_FRAME(txdesc_ie, value)
+#define IE2_GET_TX_DESC_SPE_RPT_8814B(txdesc_ie)                               \
+	IE2_GET_TX_DESC_SPE_RPT(txdesc_ie)
+#define IE2_SET_TX_DESC_SPE_RPT_8814B(txdesc_ie, value)                        \
+	IE2_SET_TX_DESC_SPE_RPT(txdesc_ie, value)
+#define IE2_GET_TX_DESC_FTM_EN_8814B(txdesc_ie)                                \
+	IE2_GET_TX_DESC_FTM_EN(txdesc_ie)
+#define IE2_SET_TX_DESC_FTM_EN_8814B(txdesc_ie, value)                         \
+	IE2_SET_TX_DESC_FTM_EN(txdesc_ie, value)
+#define IE2_GET_TX_DESC_MBSSID_8814B(txdesc_ie)                                \
+	IE2_GET_TX_DESC_MBSSID(txdesc_ie)
+#define IE2_SET_TX_DESC_MBSSID_8814B(txdesc_ie, value)                         \
+	IE2_SET_TX_DESC_MBSSID(txdesc_ie, value)
+#define IE2_GET_TX_DESC_GROUP_BIT_IE_OFFSET_8814B(txdesc_ie)                   \
+	IE2_GET_TX_DESC_GROUP_BIT_IE_OFFSET(txdesc_ie)
+#define IE2_SET_TX_DESC_GROUP_BIT_IE_OFFSET_8814B(txdesc_ie, value)            \
+	IE2_SET_TX_DESC_GROUP_BIT_IE_OFFSET(txdesc_ie, value)
+#define IE2_GET_TX_DESC_RDG_NAV_EXT_8814B(txdesc_ie)                           \
+	IE2_GET_TX_DESC_RDG_NAV_EXT(txdesc_ie)
+#define IE2_SET_TX_DESC_RDG_NAV_EXT_8814B(txdesc_ie, value)                    \
+	IE2_SET_TX_DESC_RDG_NAV_EXT(txdesc_ie, value)
+#define IE2_GET_TX_DESC_DROP_ID_8814B(txdesc_ie)                               \
+	IE2_GET_TX_DESC_DROP_ID(txdesc_ie)
+#define IE2_SET_TX_DESC_DROP_ID_8814B(txdesc_ie, value)                        \
+	IE2_SET_TX_DESC_DROP_ID(txdesc_ie, value)
+#define IE2_GET_TX_DESC_SW_DEFINE_8814B(txdesc_ie)                             \
+	IE2_GET_TX_DESC_SW_DEFINE(txdesc_ie)
+#define IE2_SET_TX_DESC_SW_DEFINE_8814B(txdesc_ie, value)                      \
+	IE2_SET_TX_DESC_SW_DEFINE(txdesc_ie, value)
+#define IE3_GET_TX_DESC_IE_END_8814B(txdesc_ie)                                \
+	IE3_GET_TX_DESC_IE_END(txdesc_ie)
+#define IE3_SET_TX_DESC_IE_END_8814B(txdesc_ie, value)                         \
+	IE3_SET_TX_DESC_IE_END(txdesc_ie, value)
+#define IE3_GET_TX_DESC_IE_UP_8814B(txdesc_ie) IE3_GET_TX_DESC_IE_UP(txdesc_ie)
+#define IE3_SET_TX_DESC_IE_UP_8814B(txdesc_ie, value)                          \
+	IE3_SET_TX_DESC_IE_UP(txdesc_ie, value)
+#define IE3_GET_TX_DESC_IE_NUM_8814B(txdesc_ie)                                \
+	IE3_GET_TX_DESC_IE_NUM(txdesc_ie)
+#define IE3_SET_TX_DESC_IE_NUM_8814B(txdesc_ie, value)                         \
+	IE3_SET_TX_DESC_IE_NUM(txdesc_ie, value)
+#define IE3_GET_TX_DESC_DATA_SC_8814B(txdesc_ie)                               \
+	IE3_GET_TX_DESC_DATA_SC(txdesc_ie)
+#define IE3_SET_TX_DESC_DATA_SC_8814B(txdesc_ie, value)                        \
+	IE3_SET_TX_DESC_DATA_SC(txdesc_ie, value)
+#define IE3_GET_TX_DESC_SIGNALING_TA_PKT_SC_8814B(txdesc_ie)                   \
+	IE3_GET_TX_DESC_SIGNALING_TA_PKT_SC(txdesc_ie)
+#define IE3_SET_TX_DESC_SIGNALING_TA_PKT_SC_8814B(txdesc_ie, value)            \
+	IE3_SET_TX_DESC_SIGNALING_TA_PKT_SC(txdesc_ie, value)
+#define IE3_GET_TX_DESC_CTRL_CNT_8814B(txdesc_ie)                              \
+	IE3_GET_TX_DESC_CTRL_CNT(txdesc_ie)
+#define IE3_SET_TX_DESC_CTRL_CNT_8814B(txdesc_ie, value)                       \
+	IE3_SET_TX_DESC_CTRL_CNT(txdesc_ie, value)
+#define IE3_GET_TX_DESC_CTRL_CNT_VALID_8814B(txdesc_ie)                        \
+	IE3_GET_TX_DESC_CTRL_CNT_VALID(txdesc_ie)
+#define IE3_SET_TX_DESC_CTRL_CNT_VALID_8814B(txdesc_ie, value)                 \
+	IE3_SET_TX_DESC_CTRL_CNT_VALID(txdesc_ie, value)
+#define IE3_GET_TX_DESC_SIGNALING_TA_PKT_EN_8814B(txdesc_ie)                   \
+	IE3_GET_TX_DESC_SIGNALING_TA_PKT_EN(txdesc_ie)
+#define IE3_SET_TX_DESC_SIGNALING_TA_PKT_EN_8814B(txdesc_ie, value)            \
+	IE3_SET_TX_DESC_SIGNALING_TA_PKT_EN(txdesc_ie, value)
+#define IE3_GET_TX_DESC_G_ID_8814B(txdesc_ie) IE3_GET_TX_DESC_G_ID(txdesc_ie)
+#define IE3_SET_TX_DESC_G_ID_8814B(txdesc_ie, value)                           \
+	IE3_SET_TX_DESC_G_ID(txdesc_ie, value)
+#define IE3_GET_TX_DESC_SND_TARGET_8814B(txdesc_ie)                            \
+	IE3_GET_TX_DESC_SND_TARGET(txdesc_ie)
+#define IE3_SET_TX_DESC_SND_TARGET_8814B(txdesc_ie, value)                     \
+	IE3_SET_TX_DESC_SND_TARGET(txdesc_ie, value)
+#define IE3_GET_TX_DESC_CCA_RTS_8814B(txdesc_ie)                               \
+	IE3_GET_TX_DESC_CCA_RTS(txdesc_ie)
+#define IE3_SET_TX_DESC_CCA_RTS_8814B(txdesc_ie, value)                        \
+	IE3_SET_TX_DESC_CCA_RTS(txdesc_ie, value)
+#define IE3_GET_TX_DESC_SND_PKT_SEL_8814B(txdesc_ie)                           \
+	IE3_GET_TX_DESC_SND_PKT_SEL(txdesc_ie)
+#define IE3_SET_TX_DESC_SND_PKT_SEL_8814B(txdesc_ie, value)                    \
+	IE3_SET_TX_DESC_SND_PKT_SEL(txdesc_ie, value)
+#define IE3_GET_TX_DESC_NDPA_8814B(txdesc_ie) IE3_GET_TX_DESC_NDPA(txdesc_ie)
+#define IE3_SET_TX_DESC_NDPA_8814B(txdesc_ie, value)                           \
+	IE3_SET_TX_DESC_NDPA(txdesc_ie, value)
+#define IE3_GET_TX_DESC_MU_DATARATE_8814B(txdesc_ie)                           \
+	IE3_GET_TX_DESC_MU_DATARATE(txdesc_ie)
+#define IE3_SET_TX_DESC_MU_DATARATE_8814B(txdesc_ie, value)                    \
+	IE3_SET_TX_DESC_MU_DATARATE(txdesc_ie, value)
+#define IE4_GET_TX_DESC_IE_END_8814B(txdesc_ie)                                \
+	IE4_GET_TX_DESC_IE_END(txdesc_ie)
+#define IE4_SET_TX_DESC_IE_END_8814B(txdesc_ie, value)                         \
+	IE4_SET_TX_DESC_IE_END(txdesc_ie, value)
+#define IE4_GET_TX_DESC_IE_UP_8814B(txdesc_ie) IE4_GET_TX_DESC_IE_UP(txdesc_ie)
+#define IE4_SET_TX_DESC_IE_UP_8814B(txdesc_ie, value)                          \
+	IE4_SET_TX_DESC_IE_UP(txdesc_ie, value)
+#define IE4_GET_TX_DESC_IE_NUM_8814B(txdesc_ie)                                \
+	IE4_GET_TX_DESC_IE_NUM(txdesc_ie)
+#define IE4_SET_TX_DESC_IE_NUM_8814B(txdesc_ie, value)                         \
+	IE4_SET_TX_DESC_IE_NUM(txdesc_ie, value)
+#define IE4_GET_TX_DESC_VCS_STBC_8814B(txdesc_ie)                              \
+	IE4_GET_TX_DESC_VCS_STBC(txdesc_ie)
+#define IE4_SET_TX_DESC_VCS_STBC_8814B(txdesc_ie, value)                       \
+	IE4_SET_TX_DESC_VCS_STBC(txdesc_ie, value)
+#define IE4_GET_TX_DESC_DATA_STBC_8814B(txdesc_ie)                             \
+	IE4_GET_TX_DESC_DATA_STBC(txdesc_ie)
+#define IE4_SET_TX_DESC_DATA_STBC_8814B(txdesc_ie, value)                      \
+	IE4_SET_TX_DESC_DATA_STBC(txdesc_ie, value)
+#define IE4_GET_TX_DESC_DATA_LDPC_8814B(txdesc_ie)                             \
+	IE4_GET_TX_DESC_DATA_LDPC(txdesc_ie)
+#define IE4_SET_TX_DESC_DATA_LDPC_8814B(txdesc_ie, value)                      \
+	IE4_SET_TX_DESC_DATA_LDPC(txdesc_ie, value)
+#define IE4_GET_TX_DESC_GF_8814B(txdesc_ie) IE4_GET_TX_DESC_GF(txdesc_ie)
+#define IE4_SET_TX_DESC_GF_8814B(txdesc_ie, value)                             \
+	IE4_SET_TX_DESC_GF(txdesc_ie, value)
+#define IE4_GET_TX_DESC_LSIG_TXOP_EN_8814B(txdesc_ie)                          \
+	IE4_GET_TX_DESC_LSIG_TXOP_EN(txdesc_ie)
+#define IE4_SET_TX_DESC_LSIG_TXOP_EN_8814B(txdesc_ie, value)                   \
+	IE4_SET_TX_DESC_LSIG_TXOP_EN(txdesc_ie, value)
+#define IE4_GET_TX_DESC_PATH_MAPA_8814B(txdesc_ie)                             \
+	IE4_GET_TX_DESC_PATH_MAPA(txdesc_ie)
+#define IE4_SET_TX_DESC_PATH_MAPA_8814B(txdesc_ie, value)                      \
+	IE4_SET_TX_DESC_PATH_MAPA(txdesc_ie, value)
+#define IE4_GET_TX_DESC_PATH_MAPB_8814B(txdesc_ie)                             \
+	IE4_GET_TX_DESC_PATH_MAPB(txdesc_ie)
+#define IE4_SET_TX_DESC_PATH_MAPB_8814B(txdesc_ie, value)                      \
+	IE4_SET_TX_DESC_PATH_MAPB(txdesc_ie, value)
+#define IE4_GET_TX_DESC_PATH_MAPC_8814B(txdesc_ie)                             \
+	IE4_GET_TX_DESC_PATH_MAPC(txdesc_ie)
+#define IE4_SET_TX_DESC_PATH_MAPC_8814B(txdesc_ie, value)                      \
+	IE4_SET_TX_DESC_PATH_MAPC(txdesc_ie, value)
+#define IE4_GET_TX_DESC_PATH_MAPD_8814B(txdesc_ie)                             \
+	IE4_GET_TX_DESC_PATH_MAPD(txdesc_ie)
+#define IE4_SET_TX_DESC_PATH_MAPD_8814B(txdesc_ie, value)                      \
+	IE4_SET_TX_DESC_PATH_MAPD(txdesc_ie, value)
+#define IE4_GET_TX_DESC_ANTSEL_A_8814B(txdesc_ie)                              \
+	IE4_GET_TX_DESC_ANTSEL_A(txdesc_ie)
+#define IE4_SET_TX_DESC_ANTSEL_A_8814B(txdesc_ie, value)                       \
+	IE4_SET_TX_DESC_ANTSEL_A(txdesc_ie, value)
+#define IE4_GET_TX_DESC_ANTSEL_B_8814B(txdesc_ie)                              \
+	IE4_GET_TX_DESC_ANTSEL_B(txdesc_ie)
+#define IE4_SET_TX_DESC_ANTSEL_B_8814B(txdesc_ie, value)                       \
+	IE4_SET_TX_DESC_ANTSEL_B(txdesc_ie, value)
+#define IE4_GET_TX_DESC_ANTSEL_C_8814B(txdesc_ie)                              \
+	IE4_GET_TX_DESC_ANTSEL_C(txdesc_ie)
+#define IE4_SET_TX_DESC_ANTSEL_C_8814B(txdesc_ie, value)                       \
+	IE4_SET_TX_DESC_ANTSEL_C(txdesc_ie, value)
+#define IE4_GET_TX_DESC_ANTSEL_D_8814B(txdesc_ie)                              \
+	IE4_GET_TX_DESC_ANTSEL_D(txdesc_ie)
+#define IE4_SET_TX_DESC_ANTSEL_D_8814B(txdesc_ie, value)                       \
+	IE4_SET_TX_DESC_ANTSEL_D(txdesc_ie, value)
+#define IE4_GET_TX_DESC_NTX_PATH_EN_8814B(txdesc_ie)                           \
+	IE4_GET_TX_DESC_NTX_PATH_EN(txdesc_ie)
+#define IE4_SET_TX_DESC_NTX_PATH_EN_8814B(txdesc_ie, value)                    \
+	IE4_SET_TX_DESC_NTX_PATH_EN(txdesc_ie, value)
+#define IE4_GET_TX_DESC_ANTLSEL_EN_8814B(txdesc_ie)                            \
+	IE4_GET_TX_DESC_ANTLSEL_EN(txdesc_ie)
+#define IE4_SET_TX_DESC_ANTLSEL_EN_8814B(txdesc_ie, value)                     \
+	IE4_SET_TX_DESC_ANTLSEL_EN(txdesc_ie, value)
+#define IE4_GET_TX_DESC_TXPWR_OFSET_TYPE_8814B(txdesc_ie)                      \
+	IE4_GET_TX_DESC_TXPWR_OFSET_TYPE(txdesc_ie)
+#define IE4_SET_TX_DESC_TXPWR_OFSET_TYPE_8814B(txdesc_ie, value)               \
+	IE4_SET_TX_DESC_TXPWR_OFSET_TYPE(txdesc_ie, value)
+#define IE5_GET_TX_DESC_IE_END_8814B(txdesc_ie)                                \
+	IE5_GET_TX_DESC_IE_END(txdesc_ie)
+#define IE5_SET_TX_DESC_IE_END_8814B(txdesc_ie, value)                         \
+	IE5_SET_TX_DESC_IE_END(txdesc_ie, value)
+#define IE5_GET_TX_DESC_IE_UP_8814B(txdesc_ie) IE5_GET_TX_DESC_IE_UP(txdesc_ie)
+#define IE5_SET_TX_DESC_IE_UP_8814B(txdesc_ie, value)                          \
+	IE5_SET_TX_DESC_IE_UP(txdesc_ie, value)
+#define IE5_GET_TX_DESC_IE_NUM_8814B(txdesc_ie)                                \
+	IE5_GET_TX_DESC_IE_NUM(txdesc_ie)
+#define IE5_SET_TX_DESC_IE_NUM_8814B(txdesc_ie, value)                         \
+	IE5_SET_TX_DESC_IE_NUM(txdesc_ie, value)
+#define IE5_GET_TX_DESC_LEN1_L_8814B(txdesc_ie)                                \
+	IE5_GET_TX_DESC_LEN1_L(txdesc_ie)
+#define IE5_SET_TX_DESC_LEN1_L_8814B(txdesc_ie, value)                         \
+	IE5_SET_TX_DESC_LEN1_L(txdesc_ie, value)
+#define IE5_GET_TX_DESC_LEN0_8814B(txdesc_ie) IE5_GET_TX_DESC_LEN0(txdesc_ie)
+#define IE5_SET_TX_DESC_LEN0_8814B(txdesc_ie, value)                           \
+	IE5_SET_TX_DESC_LEN0(txdesc_ie, value)
+#define IE5_GET_TX_DESC_PKT_NUM_8814B(txdesc_ie)                               \
+	IE5_GET_TX_DESC_PKT_NUM(txdesc_ie)
+#define IE5_SET_TX_DESC_PKT_NUM_8814B(txdesc_ie, value)                        \
+	IE5_SET_TX_DESC_PKT_NUM(txdesc_ie, value)
+#define IE5_GET_TX_DESC_LEN3_8814B(txdesc_ie) IE5_GET_TX_DESC_LEN3(txdesc_ie)
+#define IE5_SET_TX_DESC_LEN3_8814B(txdesc_ie, value)                           \
+	IE5_SET_TX_DESC_LEN3(txdesc_ie, value)
+#define IE5_GET_TX_DESC_LEN2_8814B(txdesc_ie) IE5_GET_TX_DESC_LEN2(txdesc_ie)
+#define IE5_SET_TX_DESC_LEN2_8814B(txdesc_ie, value)                           \
+	IE5_SET_TX_DESC_LEN2(txdesc_ie, value)
+#define IE5_GET_TX_DESC_LEN1_H_8814B(txdesc_ie)                                \
+	IE5_GET_TX_DESC_LEN1_H(txdesc_ie)
+#define IE5_SET_TX_DESC_LEN1_H_8814B(txdesc_ie, value)                         \
+	IE5_SET_TX_DESC_LEN1_H(txdesc_ie, value)
+
+#endif
+
+#endif
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/halmac/halmac_tx_desc_ie_nic.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/halmac/halmac_tx_desc_ie_nic.h
--- linux-5.6.3/3rdparty/rtl8821ce/hal/halmac/halmac_tx_desc_ie_nic.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/halmac/halmac_tx_desc_ie_nic.h	2020-04-10 16:35:06.817660114 +0300
@@ -0,0 +1,450 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ ******************************************************************************/
+
+#ifndef _HALMAC_TX_DESC_IE_NIC_H_
+#define _HALMAC_TX_DESC_IE_NIC_H_
+#if (HALMAC_8814B_SUPPORT)
+
+#define IE0_GET_TX_DESC_IE_END(txdesc_ie)                                      \
+	LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 31, 1)
+#define IE0_SET_TX_DESC_IE_END(txdesc_ie, value)                               \
+	SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 31, 1, value)
+#define IE0_GET_TX_DESC_IE_UP(txdesc_ie)                                       \
+	LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 30, 1)
+#define IE0_SET_TX_DESC_IE_UP(txdesc_ie, value)                                \
+	SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 30, 1, value)
+#define IE0_GET_TX_DESC_IE_NUM(txdesc_ie)                                      \
+	LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 24, 4)
+#define IE0_SET_TX_DESC_IE_NUM(txdesc_ie, value)                               \
+	SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 24, 4, value)
+#define IE0_GET_TX_DESC_ARFR_TABLE_SEL(txdesc_ie)                              \
+	LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 19, 1)
+#define IE0_SET_TX_DESC_ARFR_TABLE_SEL(txdesc_ie, value)                       \
+	SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 19, 1, value)
+#define IE0_GET_TX_DESC_ARFR_HT_EN(txdesc_ie)                                  \
+	LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 18, 1)
+#define IE0_SET_TX_DESC_ARFR_HT_EN(txdesc_ie, value)                           \
+	SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 18, 1, value)
+#define IE0_GET_TX_DESC_ARFR_OFDM_EN(txdesc_ie)                                \
+	LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 17, 1)
+#define IE0_SET_TX_DESC_ARFR_OFDM_EN(txdesc_ie, value)                         \
+	SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 17, 1, value)
+#define IE0_GET_TX_DESC_ARFR_CCK_EN(txdesc_ie)                                 \
+	LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 16, 1)
+#define IE0_SET_TX_DESC_ARFR_CCK_EN(txdesc_ie, value)                          \
+	SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 16, 1, value)
+#define IE0_GET_TX_DESC_HW_RTS_EN(txdesc_ie)                                   \
+	LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 9, 1)
+#define IE0_SET_TX_DESC_HW_RTS_EN(txdesc_ie, value)                            \
+	SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 9, 1, value)
+#define IE0_GET_TX_DESC_RTS_EN(txdesc_ie)                                      \
+	LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 8, 1)
+#define IE0_SET_TX_DESC_RTS_EN(txdesc_ie, value)                               \
+	SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 8, 1, value)
+#define IE0_GET_TX_DESC_CTS2SELF(txdesc_ie)                                    \
+	LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 7, 1)
+#define IE0_SET_TX_DESC_CTS2SELF(txdesc_ie, value)                             \
+	SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 7, 1, value)
+#define IE0_GET_TX_DESC_RTY_LMT_EN(txdesc_ie)                                  \
+	LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 6, 1)
+#define IE0_SET_TX_DESC_RTY_LMT_EN(txdesc_ie, value)                           \
+	SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 6, 1, value)
+#define IE0_GET_TX_DESC_RTS_SHORT(txdesc_ie)                                   \
+	LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 5, 1)
+#define IE0_SET_TX_DESC_RTS_SHORT(txdesc_ie, value)                            \
+	SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 5, 1, value)
+#define IE0_GET_TX_DESC_DISDATAFB(txdesc_ie)                                   \
+	LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 4, 1)
+#define IE0_SET_TX_DESC_DISDATAFB(txdesc_ie, value)                            \
+	SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 4, 1, value)
+#define IE0_GET_TX_DESC_DISRTSFB(txdesc_ie)                                    \
+	LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 3, 1)
+#define IE0_SET_TX_DESC_DISRTSFB(txdesc_ie, value)                             \
+	SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 3, 1, value)
+#define IE0_GET_TX_DESC_DATA_SHORT(txdesc_ie)                                  \
+	LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 2, 1)
+#define IE0_SET_TX_DESC_DATA_SHORT(txdesc_ie, value)                           \
+	SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 2, 1, value)
+#define IE0_GET_TX_DESC_TRY_RATE(txdesc_ie)                                    \
+	LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 1, 1)
+#define IE0_SET_TX_DESC_TRY_RATE(txdesc_ie, value)                             \
+	SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 1, 1, value)
+#define IE0_GET_TX_DESC_USERATE(txdesc_ie)                                     \
+	LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 0, 1)
+#define IE0_SET_TX_DESC_USERATE(txdesc_ie, value)                              \
+	SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 0, 1, value)
+#define IE0_GET_TX_DESC_RTS_RTY_LOWEST_RATE(txdesc_ie)                         \
+	LE_BITS_TO_4BYTE(txdesc_ie + 0x04, 27, 4)
+#define IE0_SET_TX_DESC_RTS_RTY_LOWEST_RATE(txdesc_ie, value)                  \
+	SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x04, 27, 4, value)
+#define IE0_GET_TX_DESC_DATA_RTY_LOWEST_RATE(txdesc_ie)                        \
+	LE_BITS_TO_4BYTE(txdesc_ie + 0x04, 22, 5)
+#define IE0_SET_TX_DESC_DATA_RTY_LOWEST_RATE(txdesc_ie, value)                 \
+	SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x04, 22, 5, value)
+#define IE0_GET_TX_DESC_RTS_DATA_RTY_LMT(txdesc_ie)                            \
+	LE_BITS_TO_4BYTE(txdesc_ie + 0x04, 16, 6)
+#define IE0_SET_TX_DESC_RTS_DATA_RTY_LMT(txdesc_ie, value)                     \
+	SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x04, 16, 6, value)
+#define IE0_GET_TX_DESC_DATA_BW(txdesc_ie)                                     \
+	LE_BITS_TO_4BYTE(txdesc_ie + 0x04, 12, 2)
+#define IE0_SET_TX_DESC_DATA_BW(txdesc_ie, value)                              \
+	SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x04, 12, 2, value)
+#define IE0_GET_TX_DESC_RTSRATE(txdesc_ie)                                     \
+	LE_BITS_TO_4BYTE(txdesc_ie + 0x04, 7, 4)
+#define IE0_SET_TX_DESC_RTSRATE(txdesc_ie, value)                              \
+	SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x04, 7, 4, value)
+#define IE0_GET_TX_DESC_DATARATE(txdesc_ie)                                    \
+	LE_BITS_TO_4BYTE(txdesc_ie + 0x04, 0, 7)
+#define IE0_SET_TX_DESC_DATARATE(txdesc_ie, value)                             \
+	SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x04, 0, 7, value)
+#define IE1_GET_TX_DESC_IE_END(txdesc_ie)                                      \
+	LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 31, 1)
+#define IE1_SET_TX_DESC_IE_END(txdesc_ie, value)                               \
+	SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 31, 1, value)
+#define IE1_GET_TX_DESC_IE_UP(txdesc_ie)                                       \
+	LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 30, 1)
+#define IE1_SET_TX_DESC_IE_UP(txdesc_ie, value)                                \
+	SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 30, 1, value)
+#define IE1_GET_TX_DESC_IE_NUM(txdesc_ie)                                      \
+	LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 24, 4)
+#define IE1_SET_TX_DESC_IE_NUM(txdesc_ie, value)                               \
+	SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 24, 4, value)
+#define IE1_GET_TX_DESC_AMPDU_DENSITY(txdesc_ie)                               \
+	LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 21, 3)
+#define IE1_SET_TX_DESC_AMPDU_DENSITY(txdesc_ie, value)                        \
+	SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 21, 3, value)
+#define IE1_GET_TX_DESC_MAX_AGG_NUM(txdesc_ie)                                 \
+	LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 16, 5)
+#define IE1_SET_TX_DESC_MAX_AGG_NUM(txdesc_ie, value)                          \
+	SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 16, 5, value)
+#define IE1_GET_TX_DESC_SECTYPE(txdesc_ie)                                     \
+	LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 14, 2)
+#define IE1_SET_TX_DESC_SECTYPE(txdesc_ie, value)                              \
+	SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 14, 2, value)
+#define IE1_GET_TX_DESC_MOREFRAG(txdesc_ie)                                    \
+	LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 13, 1)
+#define IE1_SET_TX_DESC_MOREFRAG(txdesc_ie, value)                             \
+	SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 13, 1, value)
+#define IE1_GET_TX_DESC_NOACM(txdesc_ie)                                       \
+	LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 12, 1)
+#define IE1_SET_TX_DESC_NOACM(txdesc_ie, value)                                \
+	SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 12, 1, value)
+#define IE1_GET_TX_DESC_BCNPKT_TSF_CTRL(txdesc_ie)                             \
+	LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 11, 1)
+#define IE1_SET_TX_DESC_BCNPKT_TSF_CTRL(txdesc_ie, value)                      \
+	SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 11, 1, value)
+#define IE1_GET_TX_DESC_NAVUSEHDR(txdesc_ie)                                   \
+	LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 10, 1)
+#define IE1_SET_TX_DESC_NAVUSEHDR(txdesc_ie, value)                            \
+	SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 10, 1, value)
+#define IE1_GET_TX_DESC_HTC(txdesc_ie) LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 9, 1)
+#define IE1_SET_TX_DESC_HTC(txdesc_ie, value)                                  \
+	SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 9, 1, value)
+#define IE1_GET_TX_DESC_BMC(txdesc_ie) LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 8, 1)
+#define IE1_SET_TX_DESC_BMC(txdesc_ie, value)                                  \
+	SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 8, 1, value)
+#define IE1_GET_TX_DESC_TX_PKT_AFTER_PIFS(txdesc_ie)                           \
+	LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 7, 1)
+#define IE1_SET_TX_DESC_TX_PKT_AFTER_PIFS(txdesc_ie, value)                    \
+	SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 7, 1, value)
+#define IE1_GET_TX_DESC_USE_MAX_TIME_EN(txdesc_ie)                             \
+	LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 6, 1)
+#define IE1_SET_TX_DESC_USE_MAX_TIME_EN(txdesc_ie, value)                      \
+	SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 6, 1, value)
+#define IE1_GET_TX_DESC_HW_SSN_SEL(txdesc_ie)                                  \
+	LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 4, 2)
+#define IE1_SET_TX_DESC_HW_SSN_SEL(txdesc_ie, value)                           \
+	SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 4, 2, value)
+#define IE1_GET_TX_DESC_DISQSELSEQ(txdesc_ie)                                  \
+	LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 3, 1)
+#define IE1_SET_TX_DESC_DISQSELSEQ(txdesc_ie, value)                           \
+	SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 3, 1, value)
+#define IE1_GET_TX_DESC_EN_HWSEQ(txdesc_ie)                                    \
+	LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 2, 1)
+#define IE1_SET_TX_DESC_EN_HWSEQ(txdesc_ie, value)                             \
+	SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 2, 1, value)
+#define IE1_GET_TX_DESC_EN_HWEXSEQ(txdesc_ie)                                  \
+	LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 1, 1)
+#define IE1_SET_TX_DESC_EN_HWEXSEQ(txdesc_ie, value)                           \
+	SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 1, 1, value)
+#define IE1_GET_TX_DESC_EN_DESC_ID(txdesc_ie)                                  \
+	LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 0, 1)
+#define IE1_SET_TX_DESC_EN_DESC_ID(txdesc_ie, value)                           \
+	SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 0, 1, value)
+#define IE1_GET_TX_DESC_AMPDU_MAX_TIME(txdesc_ie)                              \
+	LE_BITS_TO_4BYTE(txdesc_ie + 0x04, 24, 8)
+#define IE1_SET_TX_DESC_AMPDU_MAX_TIME(txdesc_ie, value)                       \
+	SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x04, 24, 8, value)
+#define IE1_GET_TX_DESC_P_AID(txdesc_ie)                                       \
+	LE_BITS_TO_4BYTE(txdesc_ie + 0x04, 15, 9)
+#define IE1_SET_TX_DESC_P_AID(txdesc_ie, value)                                \
+	SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x04, 15, 9, value)
+#define IE1_GET_TX_DESC_MOREDATA(txdesc_ie)                                    \
+	LE_BITS_TO_4BYTE(txdesc_ie + 0x04, 14, 1)
+#define IE1_SET_TX_DESC_MOREDATA(txdesc_ie, value)                             \
+	SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x04, 14, 1, value)
+#define IE1_GET_TX_DESC_SW_SEQ(txdesc_ie)                                      \
+	LE_BITS_TO_4BYTE(txdesc_ie + 0x04, 0, 12)
+#define IE1_SET_TX_DESC_SW_SEQ(txdesc_ie, value)                               \
+	SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x04, 0, 12, value)
+#define IE2_GET_TX_DESC_IE_END(txdesc_ie)                                      \
+	LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 31, 1)
+#define IE2_SET_TX_DESC_IE_END(txdesc_ie, value)                               \
+	SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 31, 1, value)
+#define IE2_GET_TX_DESC_IE_UP(txdesc_ie)                                       \
+	LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 30, 1)
+#define IE2_SET_TX_DESC_IE_UP(txdesc_ie, value)                                \
+	SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 30, 1, value)
+#define IE2_GET_TX_DESC_IE_NUM(txdesc_ie)                                      \
+	LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 24, 4)
+#define IE2_SET_TX_DESC_IE_NUM(txdesc_ie, value)                               \
+	SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 24, 4, value)
+#define IE2_GET_TX_DESC_ADDR_CAM(txdesc_ie)                                    \
+	LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 16, 8)
+#define IE2_SET_TX_DESC_ADDR_CAM(txdesc_ie, value)                             \
+	SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 16, 8, value)
+#define IE2_GET_TX_DESC_MULTIPLE_PORT(txdesc_ie)                               \
+	LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 12, 3)
+#define IE2_SET_TX_DESC_MULTIPLE_PORT(txdesc_ie, value)                        \
+	SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 12, 3, value)
+#define IE2_GET_TX_DESC_RAW(txdesc_ie) LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 11, 1)
+#define IE2_SET_TX_DESC_RAW(txdesc_ie, value)                                  \
+	SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 11, 1, value)
+#define IE2_GET_TX_DESC_RDG_EN(txdesc_ie)                                      \
+	LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 10, 1)
+#define IE2_SET_TX_DESC_RDG_EN(txdesc_ie, value)                               \
+	SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 10, 1, value)
+#define IE2_GET_TX_DESC_SPECIAL_CW(txdesc_ie)                                  \
+	LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 7, 1)
+#define IE2_SET_TX_DESC_SPECIAL_CW(txdesc_ie, value)                           \
+	SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 7, 1, value)
+#define IE2_GET_TX_DESC_POLLUTED(txdesc_ie)                                    \
+	LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 6, 1)
+#define IE2_SET_TX_DESC_POLLUTED(txdesc_ie, value)                             \
+	SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 6, 1, value)
+#define IE2_GET_TX_DESC_BT_NULL(txdesc_ie)                                     \
+	LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 5, 1)
+#define IE2_SET_TX_DESC_BT_NULL(txdesc_ie, value)                              \
+	SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 5, 1, value)
+#define IE2_GET_TX_DESC_NULL_1(txdesc_ie)                                      \
+	LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 4, 1)
+#define IE2_SET_TX_DESC_NULL_1(txdesc_ie, value)                               \
+	SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 4, 1, value)
+#define IE2_GET_TX_DESC_NULL_0(txdesc_ie)                                      \
+	LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 3, 1)
+#define IE2_SET_TX_DESC_NULL_0(txdesc_ie, value)                               \
+	SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 3, 1, value)
+#define IE2_GET_TX_DESC_TRI_FRAME(txdesc_ie)                                   \
+	LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 2, 1)
+#define IE2_SET_TX_DESC_TRI_FRAME(txdesc_ie, value)                            \
+	SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 2, 1, value)
+#define IE2_GET_TX_DESC_SPE_RPT(txdesc_ie)                                     \
+	LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 1, 1)
+#define IE2_SET_TX_DESC_SPE_RPT(txdesc_ie, value)                              \
+	SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 1, 1, value)
+#define IE2_GET_TX_DESC_FTM_EN(txdesc_ie)                                      \
+	LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 0, 1)
+#define IE2_SET_TX_DESC_FTM_EN(txdesc_ie, value)                               \
+	SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 0, 1, value)
+#define IE2_GET_TX_DESC_MBSSID(txdesc_ie)                                      \
+	LE_BITS_TO_4BYTE(txdesc_ie + 0x04, 27, 4)
+#define IE2_SET_TX_DESC_MBSSID(txdesc_ie, value)                               \
+	SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x04, 27, 4, value)
+#define IE2_GET_TX_DESC_GROUP_BIT_IE_OFFSET(txdesc_ie)                         \
+	LE_BITS_TO_4BYTE(txdesc_ie + 0x04, 16, 11)
+#define IE2_SET_TX_DESC_GROUP_BIT_IE_OFFSET(txdesc_ie, value)                  \
+	SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x04, 16, 11, value)
+#define IE2_GET_TX_DESC_RDG_NAV_EXT(txdesc_ie)                                 \
+	LE_BITS_TO_4BYTE(txdesc_ie + 0x04, 15, 1)
+#define IE2_SET_TX_DESC_RDG_NAV_EXT(txdesc_ie, value)                          \
+	SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x04, 15, 1, value)
+#define IE2_GET_TX_DESC_DROP_ID(txdesc_ie)                                     \
+	LE_BITS_TO_4BYTE(txdesc_ie + 0x04, 12, 2)
+#define IE2_SET_TX_DESC_DROP_ID(txdesc_ie, value)                              \
+	SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x04, 12, 2, value)
+#define IE2_GET_TX_DESC_SW_DEFINE(txdesc_ie)                                   \
+	LE_BITS_TO_4BYTE(txdesc_ie + 0x04, 0, 12)
+#define IE2_SET_TX_DESC_SW_DEFINE(txdesc_ie, value)                            \
+	SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x04, 0, 12, value)
+#define IE3_GET_TX_DESC_IE_END(txdesc_ie)                                      \
+	LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 31, 1)
+#define IE3_SET_TX_DESC_IE_END(txdesc_ie, value)                               \
+	SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 31, 1, value)
+#define IE3_GET_TX_DESC_IE_UP(txdesc_ie)                                       \
+	LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 30, 1)
+#define IE3_SET_TX_DESC_IE_UP(txdesc_ie, value)                                \
+	SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 30, 1, value)
+#define IE3_GET_TX_DESC_IE_NUM(txdesc_ie)                                      \
+	LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 24, 4)
+#define IE3_SET_TX_DESC_IE_NUM(txdesc_ie, value)                               \
+	SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 24, 4, value)
+#define IE3_GET_TX_DESC_DATA_SC(txdesc_ie)                                     \
+	LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 20, 4)
+#define IE3_SET_TX_DESC_DATA_SC(txdesc_ie, value)                              \
+	SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 20, 4, value)
+#define IE3_GET_TX_DESC_SIGNALING_TA_PKT_SC(txdesc_ie)                         \
+	LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 16, 4)
+#define IE3_SET_TX_DESC_SIGNALING_TA_PKT_SC(txdesc_ie, value)                  \
+	SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 16, 4, value)
+#define IE3_GET_TX_DESC_CTRL_CNT(txdesc_ie)                                    \
+	LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 8, 4)
+#define IE3_SET_TX_DESC_CTRL_CNT(txdesc_ie, value)                             \
+	SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 8, 4, value)
+#define IE3_GET_TX_DESC_CTRL_CNT_VALID(txdesc_ie)                              \
+	LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 1, 1)
+#define IE3_SET_TX_DESC_CTRL_CNT_VALID(txdesc_ie, value)                       \
+	SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 1, 1, value)
+#define IE3_GET_TX_DESC_SIGNALING_TA_PKT_EN(txdesc_ie)                         \
+	LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 0, 1)
+#define IE3_SET_TX_DESC_SIGNALING_TA_PKT_EN(txdesc_ie, value)                  \
+	SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 0, 1, value)
+#define IE3_GET_TX_DESC_G_ID(txdesc_ie)                                        \
+	LE_BITS_TO_4BYTE(txdesc_ie + 0x04, 24, 6)
+#define IE3_SET_TX_DESC_G_ID(txdesc_ie, value)                                 \
+	SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x04, 24, 6, value)
+#define IE3_GET_TX_DESC_SND_TARGET(txdesc_ie)                                  \
+	LE_BITS_TO_4BYTE(txdesc_ie + 0x04, 16, 8)
+#define IE3_SET_TX_DESC_SND_TARGET(txdesc_ie, value)                           \
+	SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x04, 16, 8, value)
+#define IE3_GET_TX_DESC_CCA_RTS(txdesc_ie)                                     \
+	LE_BITS_TO_4BYTE(txdesc_ie + 0x04, 11, 2)
+#define IE3_SET_TX_DESC_CCA_RTS(txdesc_ie, value)                              \
+	SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x04, 11, 2, value)
+#define IE3_GET_TX_DESC_SND_PKT_SEL(txdesc_ie)                                 \
+	LE_BITS_TO_4BYTE(txdesc_ie + 0x04, 9, 2)
+#define IE3_SET_TX_DESC_SND_PKT_SEL(txdesc_ie, value)                          \
+	SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x04, 9, 2, value)
+#define IE3_GET_TX_DESC_NDPA(txdesc_ie) LE_BITS_TO_4BYTE(txdesc_ie + 0x04, 7, 2)
+#define IE3_SET_TX_DESC_NDPA(txdesc_ie, value)                                 \
+	SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x04, 7, 2, value)
+#define IE3_GET_TX_DESC_MU_DATARATE(txdesc_ie)                                 \
+	LE_BITS_TO_4BYTE(txdesc_ie + 0x04, 0, 7)
+#define IE3_SET_TX_DESC_MU_DATARATE(txdesc_ie, value)                          \
+	SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x04, 0, 7, value)
+#define IE4_GET_TX_DESC_IE_END(txdesc_ie)                                      \
+	LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 31, 1)
+#define IE4_SET_TX_DESC_IE_END(txdesc_ie, value)                               \
+	SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 31, 1, value)
+#define IE4_GET_TX_DESC_IE_UP(txdesc_ie)                                       \
+	LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 30, 1)
+#define IE4_SET_TX_DESC_IE_UP(txdesc_ie, value)                                \
+	SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 30, 1, value)
+#define IE4_GET_TX_DESC_IE_NUM(txdesc_ie)                                      \
+	LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 24, 4)
+#define IE4_SET_TX_DESC_IE_NUM(txdesc_ie, value)                               \
+	SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 24, 4, value)
+#define IE4_GET_TX_DESC_VCS_STBC(txdesc_ie)                                    \
+	LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 10, 2)
+#define IE4_SET_TX_DESC_VCS_STBC(txdesc_ie, value)                             \
+	SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 10, 2, value)
+#define IE4_GET_TX_DESC_DATA_STBC(txdesc_ie)                                   \
+	LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 8, 2)
+#define IE4_SET_TX_DESC_DATA_STBC(txdesc_ie, value)                            \
+	SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 8, 2, value)
+#define IE4_GET_TX_DESC_DATA_LDPC(txdesc_ie)                                   \
+	LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 2, 1)
+#define IE4_SET_TX_DESC_DATA_LDPC(txdesc_ie, value)                            \
+	SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 2, 1, value)
+#define IE4_GET_TX_DESC_GF(txdesc_ie) LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 1, 1)
+#define IE4_SET_TX_DESC_GF(txdesc_ie, value)                                   \
+	SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 1, 1, value)
+#define IE4_GET_TX_DESC_LSIG_TXOP_EN(txdesc_ie)                                \
+	LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 0, 1)
+#define IE4_SET_TX_DESC_LSIG_TXOP_EN(txdesc_ie, value)                         \
+	SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 0, 1, value)
+#define IE4_GET_TX_DESC_PATH_MAPA(txdesc_ie)                                   \
+	LE_BITS_TO_4BYTE(txdesc_ie + 0x04, 30, 2)
+#define IE4_SET_TX_DESC_PATH_MAPA(txdesc_ie, value)                            \
+	SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x04, 30, 2, value)
+#define IE4_GET_TX_DESC_PATH_MAPB(txdesc_ie)                                   \
+	LE_BITS_TO_4BYTE(txdesc_ie + 0x04, 28, 2)
+#define IE4_SET_TX_DESC_PATH_MAPB(txdesc_ie, value)                            \
+	SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x04, 28, 2, value)
+#define IE4_GET_TX_DESC_PATH_MAPC(txdesc_ie)                                   \
+	LE_BITS_TO_4BYTE(txdesc_ie + 0x04, 26, 2)
+#define IE4_SET_TX_DESC_PATH_MAPC(txdesc_ie, value)                            \
+	SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x04, 26, 2, value)
+#define IE4_GET_TX_DESC_PATH_MAPD(txdesc_ie)                                   \
+	LE_BITS_TO_4BYTE(txdesc_ie + 0x04, 24, 2)
+#define IE4_SET_TX_DESC_PATH_MAPD(txdesc_ie, value)                            \
+	SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x04, 24, 2, value)
+#define IE4_GET_TX_DESC_ANTSEL_A(txdesc_ie)                                    \
+	LE_BITS_TO_4BYTE(txdesc_ie + 0x04, 20, 4)
+#define IE4_SET_TX_DESC_ANTSEL_A(txdesc_ie, value)                             \
+	SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x04, 20, 4, value)
+#define IE4_GET_TX_DESC_ANTSEL_B(txdesc_ie)                                    \
+	LE_BITS_TO_4BYTE(txdesc_ie + 0x04, 16, 4)
+#define IE4_SET_TX_DESC_ANTSEL_B(txdesc_ie, value)                             \
+	SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x04, 16, 4, value)
+#define IE4_GET_TX_DESC_ANTSEL_C(txdesc_ie)                                    \
+	LE_BITS_TO_4BYTE(txdesc_ie + 0x04, 12, 4)
+#define IE4_SET_TX_DESC_ANTSEL_C(txdesc_ie, value)                             \
+	SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x04, 12, 4, value)
+#define IE4_GET_TX_DESC_ANTSEL_D(txdesc_ie)                                    \
+	LE_BITS_TO_4BYTE(txdesc_ie + 0x04, 8, 4)
+#define IE4_SET_TX_DESC_ANTSEL_D(txdesc_ie, value)                             \
+	SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x04, 8, 4, value)
+#define IE4_GET_TX_DESC_NTX_PATH_EN(txdesc_ie)                                 \
+	LE_BITS_TO_4BYTE(txdesc_ie + 0x04, 4, 4)
+#define IE4_SET_TX_DESC_NTX_PATH_EN(txdesc_ie, value)                          \
+	SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x04, 4, 4, value)
+#define IE4_GET_TX_DESC_ANTLSEL_EN(txdesc_ie)                                  \
+	LE_BITS_TO_4BYTE(txdesc_ie + 0x04, 3, 1)
+#define IE4_SET_TX_DESC_ANTLSEL_EN(txdesc_ie, value)                           \
+	SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x04, 3, 1, value)
+#define IE4_GET_TX_DESC_TXPWR_OFSET_TYPE(txdesc_ie)                            \
+	LE_BITS_TO_4BYTE(txdesc_ie + 0x04, 0, 2)
+#define IE4_SET_TX_DESC_TXPWR_OFSET_TYPE(txdesc_ie, value)                     \
+	SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x04, 0, 2, value)
+#define IE5_GET_TX_DESC_IE_END(txdesc_ie)                                      \
+	LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 31, 1)
+#define IE5_SET_TX_DESC_IE_END(txdesc_ie, value)                               \
+	SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 31, 1, value)
+#define IE5_GET_TX_DESC_IE_UP(txdesc_ie)                                       \
+	LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 30, 1)
+#define IE5_SET_TX_DESC_IE_UP(txdesc_ie, value)                                \
+	SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 30, 1, value)
+#define IE5_GET_TX_DESC_IE_NUM(txdesc_ie)                                      \
+	LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 24, 4)
+#define IE5_SET_TX_DESC_IE_NUM(txdesc_ie, value)                               \
+	SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 24, 4, value)
+#define IE5_GET_TX_DESC_LEN1_L(txdesc_ie)                                      \
+	LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 17, 7)
+#define IE5_SET_TX_DESC_LEN1_L(txdesc_ie, value)                               \
+	SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 17, 7, value)
+#define IE5_GET_TX_DESC_LEN0(txdesc_ie)                                        \
+	LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 4, 13)
+#define IE5_SET_TX_DESC_LEN0(txdesc_ie, value)                                 \
+	SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 4, 13, value)
+#define IE5_GET_TX_DESC_PKT_NUM(txdesc_ie)                                     \
+	LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 0, 4)
+#define IE5_SET_TX_DESC_PKT_NUM(txdesc_ie, value)                              \
+	SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 0, 4, value)
+#define IE5_GET_TX_DESC_LEN3(txdesc_ie)                                        \
+	LE_BITS_TO_4BYTE(txdesc_ie + 0x04, 19, 13)
+#define IE5_SET_TX_DESC_LEN3(txdesc_ie, value)                                 \
+	SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x04, 19, 13, value)
+#define IE5_GET_TX_DESC_LEN2(txdesc_ie)                                        \
+	LE_BITS_TO_4BYTE(txdesc_ie + 0x04, 6, 13)
+#define IE5_SET_TX_DESC_LEN2(txdesc_ie, value)                                 \
+	SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x04, 6, 13, value)
+#define IE5_GET_TX_DESC_LEN1_H(txdesc_ie)                                      \
+	LE_BITS_TO_4BYTE(txdesc_ie + 0x04, 0, 6)
+#define IE5_SET_TX_DESC_LEN1_H(txdesc_ie, value)                               \
+	SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x04, 0, 6, value)
+
+#endif
+
+#endif
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/halmac/halmac_tx_desc_nic.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/halmac/halmac_tx_desc_nic.h
--- linux-5.6.3/3rdparty/rtl8821ce/hal/halmac/halmac_tx_desc_nic.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/halmac/halmac_tx_desc_nic.h	2020-04-10 16:35:06.817660114 +0300
@@ -0,0 +1,1025 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ ******************************************************************************/
+
+#ifndef _HALMAC_TX_DESC_NIC_H_
+#define _HALMAC_TX_DESC_NIC_H_
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT)
+
+/*TXDESC_WORD0*/
+
+#define SET_TX_DESC_DISQSELSEQ(txdesc, value)                                  \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x00, 31, 1, value)
+#define GET_TX_DESC_DISQSELSEQ(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x00, 31, 1)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define SET_TX_DESC_IE_END_BODY(txdesc, value)                                 \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x00, 31, 1, value)
+#define GET_TX_DESC_IE_END_BODY(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x00, 31, 1)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT)
+
+#define SET_TX_DESC_GF(txdesc, value)                                          \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x00, 30, 1, value)
+#define GET_TX_DESC_GF(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x00, 30, 1)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define SET_TX_DESC_AGG_EN_V1(txdesc, value)                                   \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x00, 30, 1, value)
+#define GET_TX_DESC_AGG_EN_V1(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x00, 30, 1)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT)
+
+#define SET_TX_DESC_NO_ACM(txdesc, value)                                      \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x00, 29, 1, value)
+#define GET_TX_DESC_NO_ACM(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x00, 29, 1)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define SET_TX_DESC_BK_V1(txdesc, value)                                       \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x00, 29, 1, value)
+#define GET_TX_DESC_BK_V1(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x00, 29, 1)
+
+#endif
+
+#if (HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8812F_SUPPORT)
+
+#define SET_TX_DESC_BCNPKT_TSF_CTRL(txdesc, value)                             \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x00, 28, 1, value)
+#define GET_TX_DESC_BCNPKT_TSF_CTRL(txdesc)                                    \
+	LE_BITS_TO_4BYTE(txdesc + 0x00, 28, 1)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT)
+
+#define SET_TX_DESC_AMSDU_PAD_EN(txdesc, value)                                \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x00, 27, 1, value)
+#define GET_TX_DESC_AMSDU_PAD_EN(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x00, 27, 1)
+#define SET_TX_DESC_LS(txdesc, value)                                          \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x00, 26, 1, value)
+#define GET_TX_DESC_LS(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x00, 26, 1)
+#define SET_TX_DESC_HTC(txdesc, value)                                         \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x00, 25, 1, value)
+#define GET_TX_DESC_HTC(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x00, 25, 1)
+#define SET_TX_DESC_BMC(txdesc, value)                                         \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x00, 24, 1, value)
+#define GET_TX_DESC_BMC(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x00, 24, 1)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define SET_TX_DESC_PKT_OFFSET_V1(txdesc, value)                               \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x00, 24, 5, value)
+#define GET_TX_DESC_PKT_OFFSET_V1(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x00, 24, 5)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT || HALMAC_8812F_SUPPORT)
+
+#define SET_TX_DESC_OFFSET(txdesc, value)                                      \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x00, 16, 8, value)
+#define GET_TX_DESC_OFFSET(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x00, 16, 8)
+#define SET_TX_DESC_TXPKTSIZE(txdesc, value)                                   \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x00, 0, 16, value)
+#define GET_TX_DESC_TXPKTSIZE(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x00, 0, 16)
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+/*WORD1*/
+
+#define SET_TX_DESC_HW_AES_IV_V2(txdesc, value)                                \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x04, 31, 1, value)
+#define GET_TX_DESC_HW_AES_IV_V2(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x04, 31, 1)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define SET_TX_DESC_AMSDU(txdesc, value)                                       \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x04, 30, 1, value)
+#define GET_TX_DESC_AMSDU(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x04, 30, 1)
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+#define SET_TX_DESC_FTM_EN_V1(txdesc, value)                                   \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x04, 30, 1, value)
+#define GET_TX_DESC_FTM_EN_V1(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x04, 30, 1)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT)
+
+#define SET_TX_DESC_MOREDATA(txdesc, value)                                    \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x04, 29, 1, value)
+#define GET_TX_DESC_MOREDATA(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x04, 29, 1)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define SET_TX_DESC_HW_AES_IV_V1(txdesc, value)                                \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x04, 29, 1, value)
+#define GET_TX_DESC_HW_AES_IV_V1(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x04, 29, 1)
+#define SET_TX_DESC_MHR_CP(txdesc, value)                                      \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x04, 25, 1, value)
+#define GET_TX_DESC_MHR_CP(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x04, 25, 1)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT)
+
+#define SET_TX_DESC_PKT_OFFSET(txdesc, value)                                  \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x04, 24, 5, value)
+#define GET_TX_DESC_PKT_OFFSET(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x04, 24, 5)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define SET_TX_DESC_SMH_EN_V1(txdesc, value)                                   \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x04, 24, 1, value)
+#define GET_TX_DESC_SMH_EN_V1(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x04, 24, 1)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT)
+
+#define SET_TX_DESC_SEC_TYPE(txdesc, value)                                    \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x04, 22, 2, value)
+#define GET_TX_DESC_SEC_TYPE(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x04, 22, 2)
+#define SET_TX_DESC_EN_DESC_ID(txdesc, value)                                  \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x04, 21, 1, value)
+#define GET_TX_DESC_EN_DESC_ID(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x04, 21, 1)
+#define SET_TX_DESC_RATE_ID(txdesc, value)                                     \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x04, 16, 5, value)
+#define GET_TX_DESC_RATE_ID(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x04, 16, 5)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define SET_TX_DESC_SMH_CAM(txdesc, value)                                     \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x04, 16, 8, value)
+#define GET_TX_DESC_SMH_CAM(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x04, 16, 8)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT)
+
+#define SET_TX_DESC_PIFS(txdesc, value)                                        \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x04, 15, 1, value)
+#define GET_TX_DESC_PIFS(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x04, 15, 1)
+#define SET_TX_DESC_LSIG_TXOP_EN(txdesc, value)                                \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x04, 14, 1, value)
+#define GET_TX_DESC_LSIG_TXOP_EN(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x04, 14, 1)
+#define SET_TX_DESC_RD_NAV_EXT(txdesc, value)                                  \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x04, 13, 1, value)
+#define GET_TX_DESC_RD_NAV_EXT(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x04, 13, 1)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define SET_TX_DESC_EXT_EDCA(txdesc, value)                                    \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x04, 13, 1, value)
+#define GET_TX_DESC_EXT_EDCA(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x04, 13, 1)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT || HALMAC_8812F_SUPPORT)
+
+#define SET_TX_DESC_QSEL(txdesc, value)                                        \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x04, 8, 5, value)
+#define GET_TX_DESC_QSEL(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x04, 8, 5)
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+#define SET_TX_DESC_SPECIAL_CW(txdesc, value)                                  \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x04, 7, 1, value)
+#define GET_TX_DESC_SPECIAL_CW(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x04, 7, 1)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT)
+
+#define SET_TX_DESC_MACID(txdesc, value)                                       \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x04, 0, 7, value)
+#define GET_TX_DESC_MACID(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x04, 0, 7)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define SET_TX_DESC_MACID_V1(txdesc, value)                                    \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x04, 0, 7, value)
+#define GET_TX_DESC_MACID_V1(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x04, 0, 7)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8812F_SUPPORT)
+
+/*TXDESC_WORD2*/
+
+#define SET_TX_DESC_HW_AES_IV(txdesc, value)                                   \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x08, 31, 1, value)
+#define GET_TX_DESC_HW_AES_IV(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x08, 31, 1)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define SET_TX_DESC_CHK_EN_V1(txdesc, value)                                   \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x08, 31, 1, value)
+#define GET_TX_DESC_CHK_EN_V1(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x08, 31, 1)
+
+#endif
+
+#if (HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT || HALMAC_8812F_SUPPORT)
+
+#define SET_TX_DESC_FTM_EN(txdesc, value)                                      \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x08, 30, 1, value)
+#define GET_TX_DESC_FTM_EN(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x08, 30, 1)
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+#define SET_TX_DESC_ANTCEL_D_V1(txdesc, value)                                 \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x08, 28, 4, value)
+#define GET_TX_DESC_ANTCEL_D_V1(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x08, 28, 4)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define SET_TX_DESC_DMA_PRI(txdesc, value)                                     \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x08, 27, 1, value)
+#define GET_TX_DESC_DMA_PRI(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x08, 27, 1)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8812F_SUPPORT)
+
+#define SET_TX_DESC_G_ID(txdesc, value)                                        \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x08, 24, 6, value)
+#define GET_TX_DESC_G_ID(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x08, 24, 6)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define SET_TX_DESC_MAX_AMSDU_MODE(txdesc, value)                              \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x08, 24, 3, value)
+#define GET_TX_DESC_MAX_AMSDU_MODE(txdesc)                                     \
+	LE_BITS_TO_4BYTE(txdesc + 0x08, 24, 3)
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+#define SET_TX_DESC_ANTSEL_C_V1(txdesc, value)                                 \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x08, 24, 4, value)
+#define GET_TX_DESC_ANTSEL_C_V1(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x08, 24, 4)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT)
+
+#define SET_TX_DESC_BT_NULL(txdesc, value)                                     \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x08, 23, 1, value)
+#define GET_TX_DESC_BT_NULL(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x08, 23, 1)
+#define SET_TX_DESC_AMPDU_DENSITY(txdesc, value)                               \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x08, 20, 3, value)
+#define GET_TX_DESC_AMPDU_DENSITY(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x08, 20, 3)
+#define SET_TX_DESC_SPE_RPT(txdesc, value)                                     \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x08, 19, 1, value)
+#define GET_TX_DESC_SPE_RPT(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x08, 19, 1)
+#define SET_TX_DESC_RAW(txdesc, value)                                         \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x08, 18, 1, value)
+#define GET_TX_DESC_RAW(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x08, 18, 1)
+#define SET_TX_DESC_MOREFRAG(txdesc, value)                                    \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x08, 17, 1, value)
+#define GET_TX_DESC_MOREFRAG(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x08, 17, 1)
+#define SET_TX_DESC_BK(txdesc, value)                                          \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x08, 16, 1, value)
+#define GET_TX_DESC_BK(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x08, 16, 1)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define SET_TX_DESC_DMA_TXAGG_NUM_V1(txdesc, value)                            \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x08, 16, 8, value)
+#define GET_TX_DESC_DMA_TXAGG_NUM_V1(txdesc)                                   \
+	LE_BITS_TO_4BYTE(txdesc + 0x08, 16, 8)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT)
+
+#define SET_TX_DESC_NULL_1(txdesc, value)                                      \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x08, 15, 1, value)
+#define GET_TX_DESC_NULL_1(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x08, 15, 1)
+#define SET_TX_DESC_NULL_0(txdesc, value)                                      \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x08, 14, 1, value)
+#define GET_TX_DESC_NULL_0(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x08, 14, 1)
+#define SET_TX_DESC_RDG_EN(txdesc, value)                                      \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x08, 13, 1, value)
+#define GET_TX_DESC_RDG_EN(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x08, 13, 1)
+#define SET_TX_DESC_AGG_EN(txdesc, value)                                      \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x08, 12, 1, value)
+#define GET_TX_DESC_AGG_EN(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x08, 12, 1)
+#define SET_TX_DESC_CCA_RTS(txdesc, value)                                     \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x08, 10, 2, value)
+#define GET_TX_DESC_CCA_RTS(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x08, 10, 2)
+
+#endif
+
+#if (HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8812F_SUPPORT)
+
+#define SET_TX_DESC_TRI_FRAME(txdesc, value)                                   \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x08, 9, 1, value)
+#define GET_TX_DESC_TRI_FRAME(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x08, 9, 1)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT)
+
+#define SET_TX_DESC_P_AID(txdesc, value)                                       \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x08, 0, 9, value)
+#define GET_TX_DESC_P_AID(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x08, 0, 9)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define SET_TX_DESC_TXDESC_CHECKSUM_V1(txdesc, value)                          \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x08, 0, 16, value)
+#define GET_TX_DESC_TXDESC_CHECKSUM_V1(txdesc)                                 \
+	LE_BITS_TO_4BYTE(txdesc + 0x08, 0, 16)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT)
+
+/*TXDESC_WORD3*/
+
+#define SET_TX_DESC_AMPDU_MAX_TIME(txdesc, value)                              \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x0C, 24, 8, value)
+#define GET_TX_DESC_AMPDU_MAX_TIME(txdesc)                                     \
+	LE_BITS_TO_4BYTE(txdesc + 0x0C, 24, 8)
+#define SET_TX_DESC_NDPA(txdesc, value)                                        \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x0C, 22, 2, value)
+#define GET_TX_DESC_NDPA(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x0C, 22, 2)
+#define SET_TX_DESC_MAX_AGG_NUM(txdesc, value)                                 \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x0C, 17, 5, value)
+#define GET_TX_DESC_MAX_AGG_NUM(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x0C, 17, 5)
+#define SET_TX_DESC_USE_MAX_TIME_EN(txdesc, value)                             \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x0C, 16, 1, value)
+#define GET_TX_DESC_USE_MAX_TIME_EN(txdesc)                                    \
+	LE_BITS_TO_4BYTE(txdesc + 0x0C, 16, 1)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define SET_TX_DESC_OFFLOAD_SIZE(txdesc, value)                                \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x0C, 16, 15, value)
+#define GET_TX_DESC_OFFLOAD_SIZE(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x0C, 16, 15)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT)
+
+#define SET_TX_DESC_NAVUSEHDR(txdesc, value)                                   \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x0C, 15, 1, value)
+#define GET_TX_DESC_NAVUSEHDR(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x0C, 15, 1)
+#define SET_TX_DESC_CHK_EN(txdesc, value)                                      \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x0C, 14, 1, value)
+#define GET_TX_DESC_CHK_EN(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x0C, 14, 1)
+#define SET_TX_DESC_HW_RTS_EN(txdesc, value)                                   \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x0C, 13, 1, value)
+#define GET_TX_DESC_HW_RTS_EN(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x0C, 13, 1)
+#define SET_TX_DESC_RTSEN(txdesc, value)                                       \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x0C, 12, 1, value)
+#define GET_TX_DESC_RTSEN(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x0C, 12, 1)
+#define SET_TX_DESC_CTS2SELF(txdesc, value)                                    \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x0C, 11, 1, value)
+#define GET_TX_DESC_CTS2SELF(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x0C, 11, 1)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define SET_TX_DESC_CHANNEL_DMA(txdesc, value)                                 \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x0C, 11, 5, value)
+#define GET_TX_DESC_CHANNEL_DMA(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x0C, 11, 5)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT)
+
+#define SET_TX_DESC_DISDATAFB(txdesc, value)                                   \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x0C, 10, 1, value)
+#define GET_TX_DESC_DISDATAFB(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x0C, 10, 1)
+#define SET_TX_DESC_DISRTSFB(txdesc, value)                                    \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x0C, 9, 1, value)
+#define GET_TX_DESC_DISRTSFB(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x0C, 9, 1)
+#define SET_TX_DESC_USE_RATE(txdesc, value)                                    \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x0C, 8, 1, value)
+#define GET_TX_DESC_USE_RATE(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x0C, 8, 1)
+#define SET_TX_DESC_HW_SSN_SEL(txdesc, value)                                  \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x0C, 6, 2, value)
+#define GET_TX_DESC_HW_SSN_SEL(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x0C, 6, 2)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define SET_TX_DESC_IE_CNT(txdesc, value)                                      \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x0C, 6, 3, value)
+#define GET_TX_DESC_IE_CNT(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x0C, 6, 3)
+#define SET_TX_DESC_IE_CNT_EN(txdesc, value)                                   \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x0C, 5, 1, value)
+#define GET_TX_DESC_IE_CNT_EN(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x0C, 5, 1)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT)
+
+#define SET_TX_DESC_WHEADER_LEN(txdesc, value)                                 \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x0C, 0, 5, value)
+#define GET_TX_DESC_WHEADER_LEN(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x0C, 0, 5)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define SET_TX_DESC_WHEADER_LEN_V1(txdesc, value)                              \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x0C, 0, 5, value)
+#define GET_TX_DESC_WHEADER_LEN_V1(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x0C, 0, 5)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT)
+
+/*TXDESC_WORD4*/
+
+#define SET_TX_DESC_PCTS_MASK_IDX(txdesc, value)                               \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x10, 30, 2, value)
+#define GET_TX_DESC_PCTS_MASK_IDX(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x10, 30, 2)
+#define SET_TX_DESC_PCTS_EN(txdesc, value)                                     \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x10, 29, 1, value)
+#define GET_TX_DESC_PCTS_EN(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x10, 29, 1)
+#define SET_TX_DESC_RTSRATE(txdesc, value)                                     \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x10, 24, 5, value)
+#define GET_TX_DESC_RTSRATE(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x10, 24, 5)
+#define SET_TX_DESC_RTS_DATA_RTY_LMT(txdesc, value)                            \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x10, 18, 6, value)
+#define GET_TX_DESC_RTS_DATA_RTY_LMT(txdesc)                                   \
+	LE_BITS_TO_4BYTE(txdesc + 0x10, 18, 6)
+#define SET_TX_DESC_RTY_LMT_EN(txdesc, value)                                  \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x10, 17, 1, value)
+#define GET_TX_DESC_RTY_LMT_EN(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x10, 17, 1)
+#define SET_TX_DESC_RTS_RTY_LOWEST_RATE(txdesc, value)                         \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x10, 13, 4, value)
+#define GET_TX_DESC_RTS_RTY_LOWEST_RATE(txdesc)                                \
+	LE_BITS_TO_4BYTE(txdesc + 0x10, 13, 4)
+#define SET_TX_DESC_DATA_RTY_LOWEST_RATE(txdesc, value)                        \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x10, 8, 5, value)
+#define GET_TX_DESC_DATA_RTY_LOWEST_RATE(txdesc)                               \
+	LE_BITS_TO_4BYTE(txdesc + 0x10, 8, 5)
+#define SET_TX_DESC_TRY_RATE(txdesc, value)                                    \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x10, 7, 1, value)
+#define GET_TX_DESC_TRY_RATE(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x10, 7, 1)
+#define SET_TX_DESC_DATARATE(txdesc, value)                                    \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x10, 0, 7, value)
+#define GET_TX_DESC_DATARATE(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x10, 0, 7)
+
+/*TXDESC_WORD5*/
+
+#define SET_TX_DESC_POLLUTED(txdesc, value)                                    \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x14, 31, 1, value)
+#define GET_TX_DESC_POLLUTED(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x14, 31, 1)
+
+#endif
+
+#if (HALMAC_8822C_SUPPORT || HALMAC_8812F_SUPPORT)
+
+#define SET_TX_DESC_ANTSEL_EN_V1(txdesc, value)                                \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x14, 30, 1, value)
+#define GET_TX_DESC_ANTSEL_EN_V1(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x14, 30, 1)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT)
+
+#define SET_TX_DESC_TXPWR_OFSET(txdesc, value)                                 \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x14, 28, 3, value)
+#define GET_TX_DESC_TXPWR_OFSET(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x14, 28, 3)
+
+#endif
+
+#if (HALMAC_8822C_SUPPORT || HALMAC_8812F_SUPPORT)
+
+#define SET_TX_DESC_TXPWR_OFSET_TYPE(txdesc, value)                            \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x14, 28, 2, value)
+#define GET_TX_DESC_TXPWR_OFSET_TYPE(txdesc)                                   \
+	LE_BITS_TO_4BYTE(txdesc + 0x14, 28, 2)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8812F_SUPPORT)
+
+#define SET_TX_DESC_TX_ANT(txdesc, value)                                      \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x14, 24, 4, value)
+#define GET_TX_DESC_TX_ANT(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x14, 24, 4)
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+#define SET_TX_DESC_DROP_ID(txdesc, value)                                     \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x14, 24, 2, value)
+#define GET_TX_DESC_DROP_ID(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x14, 24, 2)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT)
+
+#define SET_TX_DESC_PORT_ID(txdesc, value)                                     \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x14, 21, 3, value)
+#define GET_TX_DESC_PORT_ID(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x14, 21, 3)
+
+#endif
+
+#if (HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8812F_SUPPORT)
+
+#define SET_TX_DESC_MULTIPLE_PORT(txdesc, value)                               \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x14, 18, 3, value)
+#define GET_TX_DESC_MULTIPLE_PORT(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x14, 18, 3)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT)
+
+#define SET_TX_DESC_SIGNALING_TAPKT_EN(txdesc, value)                          \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x14, 17, 1, value)
+#define GET_TX_DESC_SIGNALING_TAPKT_EN(txdesc)                                 \
+	LE_BITS_TO_4BYTE(txdesc + 0x14, 17, 1)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+#define SET_TX_DESC_RTS_SC(txdesc, value)                                      \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x14, 13, 4, value)
+#define GET_TX_DESC_RTS_SC(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x14, 13, 4)
+
+#endif
+
+#if (HALMAC_8822B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT)
+
+#define SET_TX_DESC_SIGNALING_TA_PKT_SC(txdesc, value)                         \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x14, 13, 4, value)
+#define GET_TX_DESC_SIGNALING_TA_PKT_SC(txdesc)                                \
+	LE_BITS_TO_4BYTE(txdesc + 0x14, 13, 4)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT)
+
+#define SET_TX_DESC_RTS_SHORT(txdesc, value)                                   \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x14, 12, 1, value)
+#define GET_TX_DESC_RTS_SHORT(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x14, 12, 1)
+#define SET_TX_DESC_VCS_STBC(txdesc, value)                                    \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x14, 10, 2, value)
+#define GET_TX_DESC_VCS_STBC(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x14, 10, 2)
+#define SET_TX_DESC_DATA_STBC(txdesc, value)                                   \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x14, 8, 2, value)
+#define GET_TX_DESC_DATA_STBC(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x14, 8, 2)
+#define SET_TX_DESC_DATA_LDPC(txdesc, value)                                   \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x14, 7, 1, value)
+#define GET_TX_DESC_DATA_LDPC(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x14, 7, 1)
+#define SET_TX_DESC_DATA_BW(txdesc, value)                                     \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x14, 5, 2, value)
+#define GET_TX_DESC_DATA_BW(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x14, 5, 2)
+#define SET_TX_DESC_DATA_SHORT(txdesc, value)                                  \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x14, 4, 1, value)
+#define GET_TX_DESC_DATA_SHORT(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x14, 4, 1)
+#define SET_TX_DESC_DATA_SC(txdesc, value)                                     \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x14, 0, 4, value)
+#define GET_TX_DESC_DATA_SC(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x14, 0, 4)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8812F_SUPPORT)
+
+/*TXDESC_WORD6*/
+
+#define SET_TX_DESC_ANTSEL_D(txdesc, value)                                    \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x18, 30, 2, value)
+#define GET_TX_DESC_ANTSEL_D(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x18, 30, 2)
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+#define SET_TX_DESC_ANT_MAPD_V1(txdesc, value)                                 \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x18, 30, 2, value)
+#define GET_TX_DESC_ANT_MAPD_V1(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x18, 30, 2)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8812F_SUPPORT)
+
+#define SET_TX_DESC_ANT_MAPD(txdesc, value)                                    \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x18, 28, 2, value)
+#define GET_TX_DESC_ANT_MAPD(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x18, 28, 2)
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+#define SET_TX_DESC_ANT_MAPC_V1(txdesc, value)                                 \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x18, 28, 2, value)
+#define GET_TX_DESC_ANT_MAPC_V1(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x18, 28, 2)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8812F_SUPPORT)
+
+#define SET_TX_DESC_ANT_MAPC(txdesc, value)                                    \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x18, 26, 2, value)
+#define GET_TX_DESC_ANT_MAPC(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x18, 26, 2)
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+#define SET_TX_DESC_ANT_MAPB_V1(txdesc, value)                                 \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x18, 26, 2, value)
+#define GET_TX_DESC_ANT_MAPB_V1(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x18, 26, 2)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8812F_SUPPORT)
+
+#define SET_TX_DESC_ANT_MAPB(txdesc, value)                                    \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x18, 24, 2, value)
+#define GET_TX_DESC_ANT_MAPB(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x18, 24, 2)
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+#define SET_TX_DESC_ANT_MAPA_V1(txdesc, value)                                 \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x18, 24, 2, value)
+#define GET_TX_DESC_ANT_MAPA_V1(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x18, 24, 2)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8812F_SUPPORT)
+
+#define SET_TX_DESC_ANT_MAPA(txdesc, value)                                    \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x18, 22, 2, value)
+#define GET_TX_DESC_ANT_MAPA(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x18, 22, 2)
+#define SET_TX_DESC_ANTSEL_C(txdesc, value)                                    \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x18, 20, 2, value)
+#define GET_TX_DESC_ANTSEL_C(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x18, 20, 2)
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+#define SET_TX_DESC_ANTSEL_B_V1(txdesc, value)                                 \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x18, 20, 4, value)
+#define GET_TX_DESC_ANTSEL_B_V1(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x18, 20, 4)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8812F_SUPPORT)
+
+#define SET_TX_DESC_ANTSEL_B(txdesc, value)                                    \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x18, 18, 2, value)
+#define GET_TX_DESC_ANTSEL_B(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x18, 18, 2)
+#define SET_TX_DESC_ANTSEL_A(txdesc, value)                                    \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x18, 16, 2, value)
+#define GET_TX_DESC_ANTSEL_A(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x18, 16, 2)
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+#define SET_TX_DESC_ANTSEL_A_V1(txdesc, value)                                 \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x18, 16, 4, value)
+#define GET_TX_DESC_ANTSEL_A_V1(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x18, 16, 4)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT)
+
+#define SET_TX_DESC_MBSSID(txdesc, value)                                      \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x18, 12, 4, value)
+#define GET_TX_DESC_MBSSID(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x18, 12, 4)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8812F_SUPPORT)
+
+#define SET_TX_DESC_SW_DEFINE(txdesc, value)                                   \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x18, 0, 12, value)
+#define GET_TX_DESC_SW_DEFINE(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x18, 0, 12)
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+#define SET_TX_DESC_SWPS_SEQ(txdesc, value)                                    \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x18, 0, 12, value)
+#define GET_TX_DESC_SWPS_SEQ(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x18, 0, 12)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT)
+
+/*TXDESC_WORD7*/
+
+#define SET_TX_DESC_DMA_TXAGG_NUM(txdesc, value)                               \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x1C, 24, 8, value)
+#define GET_TX_DESC_DMA_TXAGG_NUM(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x1C, 24, 8)
+#define SET_TX_DESC_FINAL_DATA_RATE(txdesc, value)                             \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x1C, 24, 8, value)
+#define GET_TX_DESC_FINAL_DATA_RATE(txdesc)                                    \
+	LE_BITS_TO_4BYTE(txdesc + 0x1C, 24, 8)
+#define SET_TX_DESC_NTX_MAP(txdesc, value)                                     \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x1C, 20, 4, value)
+#define GET_TX_DESC_NTX_MAP(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x1C, 20, 4)
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+#define SET_TX_DESC_ANTSEL_EN(txdesc, value)                                   \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x1C, 19, 1, value)
+#define GET_TX_DESC_ANTSEL_EN(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x1C, 19, 1)
+#define SET_TX_DESC_MBSSID_EX(txdesc, value)                                   \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x1C, 16, 3, value)
+#define GET_TX_DESC_MBSSID_EX(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x1C, 16, 3)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT)
+
+#define SET_TX_DESC_TX_BUFF_SIZE(txdesc, value)                                \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x1C, 0, 16, value)
+#define GET_TX_DESC_TX_BUFF_SIZE(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x1C, 0, 16)
+#define SET_TX_DESC_TXDESC_CHECKSUM(txdesc, value)                             \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x1C, 0, 16, value)
+#define GET_TX_DESC_TXDESC_CHECKSUM(txdesc)                                    \
+	LE_BITS_TO_4BYTE(txdesc + 0x1C, 0, 16)
+#define SET_TX_DESC_TIMESTAMP(txdesc, value)                                   \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x1C, 0, 16, value)
+#define GET_TX_DESC_TIMESTAMP(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x1C, 0, 16)
+
+/*TXDESC_WORD8*/
+
+#define SET_TX_DESC_TXWIFI_CP(txdesc, value)                                   \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x20, 31, 1, value)
+#define GET_TX_DESC_TXWIFI_CP(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x20, 31, 1)
+#define SET_TX_DESC_MAC_CP(txdesc, value)                                      \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x20, 30, 1, value)
+#define GET_TX_DESC_MAC_CP(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x20, 30, 1)
+#define SET_TX_DESC_STW_PKTRE_DIS(txdesc, value)                               \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x20, 29, 1, value)
+#define GET_TX_DESC_STW_PKTRE_DIS(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x20, 29, 1)
+#define SET_TX_DESC_STW_RB_DIS(txdesc, value)                                  \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x20, 28, 1, value)
+#define GET_TX_DESC_STW_RB_DIS(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x20, 28, 1)
+#define SET_TX_DESC_STW_RATE_DIS(txdesc, value)                                \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x20, 27, 1, value)
+#define GET_TX_DESC_STW_RATE_DIS(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x20, 27, 1)
+#define SET_TX_DESC_STW_ANT_DIS(txdesc, value)                                 \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x20, 26, 1, value)
+#define GET_TX_DESC_STW_ANT_DIS(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x20, 26, 1)
+#define SET_TX_DESC_STW_EN(txdesc, value)                                      \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x20, 25, 1, value)
+#define GET_TX_DESC_STW_EN(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x20, 25, 1)
+#define SET_TX_DESC_SMH_EN(txdesc, value)                                      \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x20, 24, 1, value)
+#define GET_TX_DESC_SMH_EN(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x20, 24, 1)
+#define SET_TX_DESC_TAILPAGE_L(txdesc, value)                                  \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x20, 24, 8, value)
+#define GET_TX_DESC_TAILPAGE_L(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x20, 24, 8)
+#define SET_TX_DESC_SDIO_DMASEQ(txdesc, value)                                 \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x20, 16, 8, value)
+#define GET_TX_DESC_SDIO_DMASEQ(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x20, 16, 8)
+#define SET_TX_DESC_NEXTHEADPAGE_L(txdesc, value)                              \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x20, 16, 8, value)
+#define GET_TX_DESC_NEXTHEADPAGE_L(txdesc)                                     \
+	LE_BITS_TO_4BYTE(txdesc + 0x20, 16, 8)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define SET_TX_DESC_EN_HWSEQ(txdesc, value)                                    \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x20, 15, 1, value)
+#define GET_TX_DESC_EN_HWSEQ(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x20, 15, 1)
+#define SET_TX_DESC_EN_HWEXSEQ(txdesc, value)                                  \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x20, 14, 1, value)
+#define GET_TX_DESC_EN_HWEXSEQ(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x20, 14, 1)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT)
+
+#define SET_TX_DESC_EN_HWSEQ_MODE(txdesc, value)                               \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x20, 14, 2, value)
+#define GET_TX_DESC_EN_HWSEQ_MODE(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x20, 14, 2)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT)
+
+#define SET_TX_DESC_DATA_RC(txdesc, value)                                     \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x20, 8, 6, value)
+#define GET_TX_DESC_DATA_RC(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x20, 8, 6)
+#define SET_TX_DESC_BAR_RTY_TH(txdesc, value)                                  \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x20, 6, 2, value)
+#define GET_TX_DESC_BAR_RTY_TH(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x20, 6, 2)
+#define SET_TX_DESC_RTS_RC(txdesc, value)                                      \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x20, 0, 6, value)
+#define GET_TX_DESC_RTS_RC(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x20, 0, 6)
+
+/*TXDESC_WORD9*/
+
+#define SET_TX_DESC_TAILPAGE_H(txdesc, value)                                  \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x24, 28, 4, value)
+#define GET_TX_DESC_TAILPAGE_H(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x24, 28, 4)
+#define SET_TX_DESC_NEXTHEADPAGE_H(txdesc, value)                              \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x24, 24, 4, value)
+#define GET_TX_DESC_NEXTHEADPAGE_H(txdesc)                                     \
+	LE_BITS_TO_4BYTE(txdesc + 0x24, 24, 4)
+#define SET_TX_DESC_SW_SEQ(txdesc, value)                                      \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x24, 12, 12, value)
+#define GET_TX_DESC_SW_SEQ(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x24, 12, 12)
+#define SET_TX_DESC_TXBF_PATH(txdesc, value)                                   \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x24, 11, 1, value)
+#define GET_TX_DESC_TXBF_PATH(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x24, 11, 1)
+#define SET_TX_DESC_PADDING_LEN(txdesc, value)                                 \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x24, 0, 11, value)
+#define GET_TX_DESC_PADDING_LEN(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x24, 0, 11)
+#define SET_TX_DESC_GROUP_BIT_IE_OFFSET(txdesc, value)                         \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x24, 0, 8, value)
+#define GET_TX_DESC_GROUP_BIT_IE_OFFSET(txdesc)                                \
+	LE_BITS_TO_4BYTE(txdesc + 0x24, 0, 8)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT)
+
+/*WORD10*/
+
+#define SET_TX_DESC_HT_DATA_SND(txdesc, value)                                 \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x28, 31, 1, value)
+#define GET_TX_DESC_HT_DATA_SND(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x28, 31, 1)
+#define SET_TX_DESC_SHCUT_CAM(txdesc, value)                                   \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x28, 16, 6, value)
+#define GET_TX_DESC_SHCUT_CAM(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x28, 16, 6)
+
+#endif
+
+#if (HALMAC_8822B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT)
+
+#define SET_TX_DESC_MU_DATARATE(txdesc, value)                                 \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x28, 8, 8, value)
+#define GET_TX_DESC_MU_DATARATE(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x28, 8, 8)
+#define SET_TX_DESC_MU_RC(txdesc, value)                                       \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x28, 4, 4, value)
+#define GET_TX_DESC_MU_RC(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x28, 4, 4)
+
+#endif
+
+#if (HALMAC_8812F_SUPPORT)
+
+#define SET_TX_DESC_NDPA_RATE_SEL(txdesc, value)                               \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x28, 3, 1, value)
+#define GET_TX_DESC_NDPA_RATE_SEL(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x28, 3, 1)
+#define SET_TX_DESC_HW_NDPA_EN(txdesc, value)                                  \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x28, 2, 1, value)
+#define GET_TX_DESC_HW_NDPA_EN(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x28, 2, 1)
+
+#endif
+
+#if (HALMAC_8822B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT ||   \
+     HALMAC_8812F_SUPPORT)
+
+#define SET_TX_DESC_SND_PKT_SEL(txdesc, value)                                 \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x28, 0, 2, value)
+#define GET_TX_DESC_SND_PKT_SEL(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x28, 0, 2)
+
+#endif
+
+#endif
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/halmac/halmac_type.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/halmac/halmac_type.h
--- linux-5.6.3/3rdparty/rtl8821ce/hal/halmac/halmac_type.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/halmac/halmac_type.h	2020-04-10 16:35:06.817660114 +0300
@@ -0,0 +1,2412 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ ******************************************************************************/
+
+#ifndef _HALMAC_TYPE_H_
+#define _HALMAC_TYPE_H_
+
+#include "halmac_2_platform.h"
+#include "halmac_hw_cfg.h"
+#include "halmac_fw_info.h"
+#include "halmac_intf_phy_cmd.h"
+#include "halmac_state_machine.h"
+
+#define IN
+#define OUT
+#define INOUT
+
+#define HALMAC_BCN_IE_BMP_SIZE	24 /* ID0~ID191, 192/8=24 */
+
+#ifndef HALMAC_RX_FIFO_EXPANDING_MODE_PKT_SIZE
+#define HALMAC_RX_FIFO_EXPANDING_MODE_PKT_SIZE	80
+#endif
+
+#ifndef HALMAC_MSG_LEVEL_TRACE
+#define HALMAC_MSG_LEVEL_TRACE		3
+#endif
+
+#ifndef HALMAC_MSG_LEVEL_WARNING
+#define HALMAC_MSG_LEVEL_WARNING	2
+#endif
+
+#ifndef HALMAC_MSG_LEVEL_ERR
+#define HALMAC_MSG_LEVEL_ERR		1
+#endif
+
+#ifndef HALMAC_MSG_LEVEL_NO_LOG
+#define HALMAC_MSG_LEVEL_NO_LOG		0
+#endif
+
+#ifndef HALMAC_SDIO_SUPPORT
+#define HALMAC_SDIO_SUPPORT		1
+#endif
+
+#ifndef HALMAC_USB_SUPPORT
+#define HALMAC_USB_SUPPORT		1
+#endif
+
+#ifndef HALMAC_PCIE_SUPPORT
+#define HALMAC_PCIE_SUPPORT		1
+#endif
+
+#ifndef HALMAC_MSG_LEVEL
+#define HALMAC_MSG_LEVEL HALMAC_MSG_LEVEL_TRACE
+#endif
+
+/* platform api */
+#define PLTFM_SDIO_CMD52_R(offset)                                             \
+	adapter->pltfm_api->SDIO_CMD52_READ(adapter->drv_adapter, offset)
+#define PLTFM_SDIO_CMD53_R8(offset)                                            \
+	adapter->pltfm_api->SDIO_CMD53_READ_8(adapter->drv_adapter, offset)
+#define PLTFM_SDIO_CMD53_R16(offset)                                           \
+	adapter->pltfm_api->SDIO_CMD53_READ_16(adapter->drv_adapter, offset)
+#define PLTFM_SDIO_CMD53_R32(offset)                                           \
+	adapter->pltfm_api->SDIO_CMD53_READ_32(adapter->drv_adapter, offset)
+#define PLTFM_SDIO_CMD53_RN(offset, size, data)                                \
+	adapter->pltfm_api->SDIO_CMD53_READ_N(adapter->drv_adapter, offset,    \
+					      size, data)
+#define PLTFM_SDIO_CMD52_W(offset, val)                                        \
+	adapter->pltfm_api->SDIO_CMD52_WRITE(adapter->drv_adapter, offset, val)
+#define PLTFM_SDIO_CMD53_W8(offset, val)                                       \
+	adapter->pltfm_api->SDIO_CMD53_WRITE_8(adapter->drv_adapter, offset,   \
+					       val)
+#define PLTFM_SDIO_CMD53_W16(offset, val)                                      \
+	adapter->pltfm_api->SDIO_CMD53_WRITE_16(adapter->drv_adapter, offset,  \
+						val)
+#define PLTFM_SDIO_CMD53_W32(offset, val)                                      \
+	adapter->pltfm_api->SDIO_CMD53_WRITE_32(adapter->drv_adapter, offset,  \
+						val)
+#define PLTFM_SDIO_CMD52_CIA_R(offset)                                         \
+	adapter->pltfm_api->SDIO_CMD52_CIA_READ(adapter->drv_adapter, offset)
+
+#define PLTFM_REG_R8(offset)                                                   \
+	adapter->pltfm_api->REG_READ_8(adapter->drv_adapter, offset)
+#define PLTFM_REG_R16(offset)                                                  \
+	adapter->pltfm_api->REG_READ_16(adapter->drv_adapter, offset)
+#define PLTFM_REG_R32(offset)                                                  \
+	adapter->pltfm_api->REG_READ_32(adapter->drv_adapter, offset)
+#define PLTFM_REG_W8(offset, val)                                              \
+	adapter->pltfm_api->REG_WRITE_8(adapter->drv_adapter, offset, val)
+#define PLTFM_REG_W16(offset, val)                                             \
+	adapter->pltfm_api->REG_WRITE_16(adapter->drv_adapter, offset, val)
+#define PLTFM_REG_W32(offset, val)                                             \
+	adapter->pltfm_api->REG_WRITE_32(adapter->drv_adapter, offset, val)
+
+#define PLTFM_SEND_RSVD_PAGE(buf, size)                                        \
+	adapter->pltfm_api->SEND_RSVD_PAGE(adapter->drv_adapter, buf, size)
+#define PLTFM_SEND_H2C_PKT(buf, size)                                          \
+	adapter->pltfm_api->SEND_H2C_PKT(adapter->drv_adapter, buf, size)
+
+#define PLTFM_FREE(buf, size)                                                  \
+	adapter->pltfm_api->RTL_FREE(adapter->drv_adapter, buf, size)
+#define PLTFM_MALLOC(size)                                                     \
+	adapter->pltfm_api->RTL_MALLOC(adapter->drv_adapter, size)
+#define PLTFM_MEMCPY(dest, src, size)                                          \
+	adapter->pltfm_api->RTL_MEMCPY(adapter->drv_adapter, dest, src, size)
+#define PLTFM_MEMSET(addr, value, size)                                        \
+	adapter->pltfm_api->RTL_MEMSET(adapter->drv_adapter, addr, value, size)
+#define PLTFM_DELAY_US(us)                                                     \
+	adapter->pltfm_api->RTL_DELAY_US(adapter->drv_adapter, us)
+
+#define PLTFM_MUTEX_INIT(mutex)                                                \
+	adapter->pltfm_api->MUTEX_INIT(adapter->drv_adapter, mutex)
+#define PLTFM_MUTEX_DEINIT(mutex)                                              \
+	adapter->pltfm_api->MUTEX_DEINIT(adapter->drv_adapter, mutex)
+#define PLTFM_MUTEX_LOCK(mutex)                                                \
+	adapter->pltfm_api->MUTEX_LOCK(adapter->drv_adapter, mutex)
+#define PLTFM_MUTEX_UNLOCK(mutex)                                              \
+	adapter->pltfm_api->MUTEX_UNLOCK(adapter->drv_adapter, mutex)
+
+#define PLTFM_EVENT_SIG(feature_id, proc_status, buf, size)                    \
+	adapter->pltfm_api->EVENT_INDICATION(adapter->drv_adapter, feature_id, \
+					     proc_status, buf, size)
+
+#if HALMAC_PLATFORM_WINDOWS
+#define PLTFM_MSG_PRINT	adapter->pltfm_api->MSG_PRINT
+#endif
+
+#define PLTFM_MSG_ALWAYS(...)                                                  \
+	adapter->pltfm_api->MSG_PRINT(adapter->drv_adapter, HALMAC_MSG_INIT,   \
+				      HALMAC_DBG_ALWAYS, __VA_ARGS__)
+
+#if HALMAC_DBG_MSG_ENABLE
+
+/* Enable debug msg depends on  HALMAC_MSG_LEVEL */
+#if (HALMAC_MSG_LEVEL >= HALMAC_MSG_LEVEL_ERR)
+#define PLTFM_MSG_ERR(...)                                                     \
+	adapter->pltfm_api->MSG_PRINT(adapter->drv_adapter, HALMAC_MSG_INIT,   \
+				      HALMAC_DBG_ERR, __VA_ARGS__)
+#else
+#define PLTFM_MSG_ERR(...)	do {} while (0)
+#endif
+
+#if (HALMAC_MSG_LEVEL >= HALMAC_MSG_LEVEL_WARNING)
+#define PLTFM_MSG_WARN(...)                                                    \
+	adapter->pltfm_api->MSG_PRINT(adapter->drv_adapter, HALMAC_MSG_INIT,   \
+				      HALMAC_DBG_WARN, __VA_ARGS__)
+#else
+#define PLTFM_MSG_WARN(...)	do {} while (0)
+#endif
+
+#if (HALMAC_MSG_LEVEL >= HALMAC_MSG_LEVEL_TRACE)
+#define PLTFM_MSG_TRACE(...)                                                   \
+	adapter->pltfm_api->MSG_PRINT(adapter->drv_adapter, HALMAC_MSG_INIT,   \
+				      HALMAC_DBG_TRACE, __VA_ARGS__)
+#else
+#define PLTFM_MSG_TRACE(...)	do {} while (0)
+#endif
+
+#else
+
+/* Disable debug msg  */
+#define PLTFM_MSG_ERR(...)	do {} while (0)
+#define PLTFM_MSG_WARN(...)	do {} while (0)
+#define PLTFM_MSG_TRACE(...)	do {} while (0)
+
+#endif
+
+#define HALMAC_REG_R8(offset) api->halmac_reg_read_8(adapter, offset)
+#define HALMAC_REG_R16(offset) api->halmac_reg_read_16(adapter, offset)
+#define HALMAC_REG_R32(offset) api->halmac_reg_read_32(adapter, offset)
+#define HALMAC_REG_W8(offset, val) api->halmac_reg_write_8(adapter, offset, val)
+#define HALMAC_REG_W16(offset, val)                                            \
+	api->halmac_reg_write_16(adapter, offset, val)
+#define HALMAC_REG_W32(offset, val)                                            \
+	api->halmac_reg_write_32(adapter, offset, val)
+#define HALMAC_REG_SDIO_RN(offset, size, data)                                 \
+	api->halmac_reg_sdio_cmd53_read_n(adapter, offset, size, data)
+
+#define HALMAC_REG_W8_CLR(offset, mask)                                        \
+	do {                                                                   \
+		u32 __offset = (u32)offset;                                    \
+		HALMAC_REG_W8(__offset, HALMAC_REG_R8(__offset) & ~(mask));    \
+	} while (0)
+#define HALMAC_REG_W16_CLR(offset, mask)                                       \
+	do {                                                                   \
+		u32 __offset = (u32)offset;                                    \
+		HALMAC_REG_W16(__offset, HALMAC_REG_R16(__offset) & ~(mask));  \
+	} while (0)
+#define HALMAC_REG_W32_CLR(offset, mask)                                       \
+	do {                                                                   \
+		u32 __offset = (u32)offset;                                    \
+		HALMAC_REG_W32(__offset, HALMAC_REG_R32(__offset) & ~(mask));  \
+	} while (0)
+
+#define HALMAC_REG_W8_SET(offset, mask)                                        \
+	do {                                                                   \
+		u32 __offset = (u32)offset;                                    \
+		HALMAC_REG_W8(__offset, HALMAC_REG_R8(__offset) | mask);       \
+	} while (0)
+#define HALMAC_REG_W16_SET(offset, mask)                                       \
+	do {                                                                   \
+		u32 __offset = (u32)offset;                                    \
+		HALMAC_REG_W16(__offset, HALMAC_REG_R16(__offset) | mask);     \
+	} while (0)
+#define HALMAC_REG_W32_SET(offset, mask)                                       \
+	do {                                                                   \
+		u32 __offset = (u32)offset;                                    \
+		HALMAC_REG_W32(__offset, HALMAC_REG_R32(__offset) | mask);     \
+	} while (0)
+
+/* Swap Little-endian <-> Big-endia*/
+#define SWAP32(x)                                                              \
+	((u32)((((u32)(x) & (u32)0x000000ff) << 24) |                          \
+	       (((u32)(x) & (u32)0x0000ff00) << 8) |                           \
+	       (((u32)(x) & (u32)0x00ff0000) >> 8) |                           \
+	       (((u32)(x) & (u32)0xff000000) >> 24)))
+
+#define SWAP16(x)                                                              \
+	((u16)((((u16)(x) & (u16)0x00ff) << 8) |                               \
+	       (((u16)(x) & (u16)0xff00) >> 8)))
+
+/*1->Little endian 0->Big endian*/
+#if HALMAC_SYSTEM_ENDIAN
+#ifndef rtk_le16_to_cpu
+#define rtk_cpu_to_le32(x)              ((u32)(x))
+#define rtk_le32_to_cpu(x)              ((u32)(x))
+#define rtk_cpu_to_le16(x)              ((u16)(x))
+#define rtk_le16_to_cpu(x)              ((u16)(x))
+#define rtk_cpu_to_be32(x)              SWAP32((x))
+#define rtk_be32_to_cpu(x)              SWAP32((x))
+#define rtk_cpu_to_be16(x)              SWAP16((x))
+#define rtk_be16_to_cpu(x)              SWAP16((x))
+#endif
+#else
+#ifndef rtk_le16_to_cpu
+#define rtk_cpu_to_le32(x)              SWAP32((x))
+#define rtk_le32_to_cpu(x)              SWAP32((x))
+#define rtk_cpu_to_le16(x)              SWAP16((x))
+#define rtk_le16_to_cpu(x)              SWAP16((x))
+#define rtk_cpu_to_be32(x)              ((u32)(x))
+#define rtk_be32_to_cpu(x)              ((u32)(x))
+#define rtk_cpu_to_be16(x)              ((u16)(x))
+#define rtk_be16_to_cpu(x)              ((u16)(x))
+#endif
+#endif
+
+#define HALMAC_ALIGN(x, a)               HALMAC_ALIGN_MASK(x, (a) - 1)
+#define HALMAC_ALIGN_MASK(x, mask)       (((x) + (mask)) & ~(mask))
+
+/* #if !HALMAC_PLATFORM_WINDOWS */
+#if !((HALMAC_PLATFORM_WINDOWS == 1) && (HALMAC_PLATFORM_TESTPROGRAM == 0))
+
+/* Byte Swapping routine */
+#ifndef EF1BYTE
+#define EF1BYTE (u8)
+#endif
+
+#ifndef EF2BYTE
+#define EF2BYTE rtk_le16_to_cpu
+#endif
+
+#ifndef EF4BYTE
+#define EF4BYTE rtk_le32_to_cpu
+#endif
+
+/* Example:
+ * BIT_LEN_MASK_32(0) => 0x00000000
+ * BIT_LEN_MASK_32(1) => 0x00000001
+ * BIT_LEN_MASK_32(2) => 0x00000003
+ * BIT_LEN_MASK_32(32) => 0xFFFFFFFF
+ */
+#ifndef BIT_LEN_MASK_32
+#define BIT_LEN_MASK_32(__bitlen) (0xFFFFFFFF >> (32 - (__bitlen)))
+#endif
+
+/* Example:
+ * BIT_OFFSET_LEN_MASK_32(0, 2) => 0x00000003
+ * BIT_OFFSET_LEN_MASK_32(16, 2) => 0x00030000
+ */
+#ifndef BIT_OFFSET_LEN_MASK_32
+#define BIT_OFFSET_LEN_MASK_32(__bitoffset, __bitlen)                          \
+	(BIT_LEN_MASK_32(__bitlen) << (__bitoffset))
+#endif
+
+/* Return 4-byte value in host byte ordering from
+ * 4-byte pointer in litten-endian system
+ */
+#ifndef LE_P4BYTE_TO_HOST_4BYTE
+#define LE_P4BYTE_TO_HOST_4BYTE(__start) (EF4BYTE(*((u32 *)(__start))))
+#endif
+
+/* Translate subfield (continuous bits in little-endian) of
+ * 4-byte value in litten byte to 4-byte value in host byte ordering
+ */
+#ifndef LE_BITS_TO_4BYTE
+#define LE_BITS_TO_4BYTE(__start, __bitoffset, __bitlen)                       \
+	((LE_P4BYTE_TO_HOST_4BYTE(__start) >> (__bitoffset)) &                 \
+	 BIT_LEN_MASK_32(__bitlen))
+#endif
+
+/* Mask subfield (continuous bits in little-endian) of 4-byte
+ * value in litten byte oredering and return the result in 4-byte
+ * value in host byte ordering
+ */
+#ifndef LE_BITS_CLEARED_TO_4BYTE
+#define LE_BITS_CLEARED_TO_4BYTE(__start, __bitoffset, __bitlen)               \
+	(LE_P4BYTE_TO_HOST_4BYTE(__start) &                                    \
+	 (~BIT_OFFSET_LEN_MASK_32(__bitoffset, __bitlen)))
+#endif
+
+/* Set subfield of little-endian 4-byte value to specified value */
+#ifndef SET_BITS_TO_LE_4BYTE
+#define SET_BITS_TO_LE_4BYTE(__start, __bitoffset, __bitlen, __value)          \
+	do {                                                                   \
+		*((u32 *)(__start)) = \
+		EF4BYTE( \
+		LE_BITS_CLEARED_TO_4BYTE(__start, __bitoffset, __bitlen) |     \
+		((((u32)__value) & BIT_LEN_MASK_32(__bitlen)) << (__bitoffset))\
+		);                                                             \
+	} while (0)
+#endif
+
+#ifndef HALMAC_BIT_OFFSET_VAL_MASK_32
+#define HALMAC_BIT_OFFSET_VAL_MASK_32(__bitval, __bitoffset)                   \
+	(__bitval << (__bitoffset))
+#endif
+
+#ifndef SET_MEM_OP
+#define SET_MEM_OP(dw, value32, mask, shift)                                   \
+	(((dw) & ~((mask) << (shift))) | (((value32) & (mask)) << (shift)))
+#endif
+
+#ifndef HALMAC_SET_DESC_FIELD_CLR
+#define HALMAC_SET_DESC_FIELD_CLR(dw, value32, mask, shift)                    \
+	(dw = (rtk_cpu_to_le32(                                                \
+		 SET_MEM_OP(rtk_cpu_to_le32(dw), value32, mask, shift))))
+#endif
+
+#ifndef HALMAC_SET_DESC_FIELD_NO_CLR
+#define HALMAC_SET_DESC_FIELD_NO_CLR(dw, value32, mask, shift)                 \
+	(dw |= (rtk_cpu_to_le32(((value32) & (mask)) << (shift))))
+#endif
+
+#ifndef HALMAC_GET_DESC_FIELD
+#define HALMAC_GET_DESC_FIELD(dw, mask, shift)                                 \
+	((rtk_le32_to_cpu(dw) >> (shift)) & (mask))
+#endif
+
+#define HALMAC_SET_BD_FIELD_CLR HALMAC_SET_DESC_FIELD_CLR
+#define HALMAC_SET_BD_FIELD_NO_CLR HALMAC_SET_DESC_FIELD_NO_CLR
+#define HALMAC_GET_BD_FIELD HALMAC_GET_DESC_FIELD
+
+#ifndef GET_H2C_FIELD
+#define GET_H2C_FIELD   LE_BITS_TO_4BYTE
+#endif
+
+#ifndef SET_H2C_FIELD_CLR
+#define SET_H2C_FIELD_CLR       SET_BITS_TO_LE_4BYTE
+#endif
+
+#ifndef SET_H2C_FIELD_NO_CLR
+#define SET_H2C_FIELD_NO_CLR    SET_BITS_TO_LE_4BYTE
+#endif
+
+#ifndef GET_C2H_FIELD
+#define GET_C2H_FIELD   LE_BITS_TO_4BYTE
+#endif
+
+#ifndef SET_C2H_FIELD_CLR
+#define SET_C2H_FIELD_CLR       SET_BITS_TO_LE_4BYTE
+#endif
+
+#ifndef SET_C2H_FIELD_NO_CLR
+#define SET_C2H_FIELD_NO_CLR    SET_BITS_TO_LE_4BYTE
+#endif
+
+#endif /* #if !HALMAC_PLATFORM_WINDOWS */
+
+#ifndef BIT
+#define BIT(x)              (1 << (x))
+#endif
+
+#ifndef ARRAY_SIZE
+#define ARRAY_SIZE(arr)		(sizeof(arr) / sizeof((arr)[0]))
+#endif
+
+/* HALMAC API return status*/
+enum halmac_ret_status {
+	HALMAC_RET_SUCCESS = 0x00,
+	HALMAC_RET_NOT_SUPPORT = 0x01,
+	HALMAC_RET_SUCCESS_ENQUEUE = 0x01, /*Don't use this return code!!*/
+	HALMAC_RET_PLATFORM_API_NULL = 0x02,
+	HALMAC_RET_EFUSE_SIZE_INCORRECT = 0x03,
+	HALMAC_RET_MALLOC_FAIL = 0x04,
+	HALMAC_RET_ADAPTER_INVALID = 0x05,
+	HALMAC_RET_ITF_INCORRECT = 0x06,
+	HALMAC_RET_DLFW_FAIL = 0x07,
+	HALMAC_RET_PORT_NOT_SUPPORT = 0x08,
+	HALMAC_RET_TXAGG_OVERFLOW = 0x09,
+	HALMAC_RET_INIT_LLT_FAIL = 0x0A,
+	HALMAC_RET_POWER_STATE_INVALID = 0x0B,
+	HALMAC_RET_H2C_ACK_NOT_RECEIVED = 0x0C,
+	HALMAC_RET_DL_RSVD_PAGE_FAIL = 0x0D,
+	HALMAC_RET_EFUSE_R_FAIL = 0x0E,
+	HALMAC_RET_EFUSE_W_FAIL = 0x0F,
+	HALMAC_RET_H2C_SW_RES_FAIL = 0x10,
+	HALMAC_RET_SEND_H2C_FAIL = 0x11,
+	HALMAC_RET_PARA_NOT_SUPPORT = 0x12,
+	HALMAC_RET_PLATFORM_API_INCORRECT = 0x13,
+	HALMAC_RET_ENDIAN_ERR = 0x14,
+	HALMAC_RET_FW_SIZE_ERR = 0x15,
+	HALMAC_RET_TRX_MODE_NOT_SUPPORT = 0x16,
+	HALMAC_RET_FAIL = 0x17,
+	HALMAC_RET_CHANGE_PS_FAIL = 0x18,
+	HALMAC_RET_CFG_PARA_FAIL = 0x19,
+	HALMAC_RET_UPDATE_PROBE_FAIL = 0x1A,
+	HALMAC_RET_SCAN_FAIL = 0x1B,
+	HALMAC_RET_STOP_SCAN_FAIL = 0x1C,
+	HALMAC_RET_BCN_PARSER_CMD_FAIL = 0x1D,
+	HALMAC_RET_POWER_ON_FAIL = 0x1E,
+	HALMAC_RET_POWER_OFF_FAIL = 0x1F,
+	HALMAC_RET_RX_AGG_MODE_FAIL = 0x20,
+	HALMAC_RET_DATA_BUF_NULL = 0x21,
+	HALMAC_RET_DATA_SIZE_INCORRECT = 0x22,
+	HALMAC_RET_QSEL_INCORRECT = 0x23,
+	HALMAC_RET_DMA_MAP_INCORRECT = 0x24,
+	HALMAC_RET_SEND_ORIGINAL_H2C_FAIL = 0x25,
+	HALMAC_RET_DDMA_FAIL = 0x26,
+	HALMAC_RET_FW_CHECKSUM_FAIL = 0x27,
+	HALMAC_RET_PWRSEQ_POLLING_FAIL = 0x28,
+	HALMAC_RET_PWRSEQ_CMD_INCORRECT = 0x29,
+	HALMAC_RET_WRITE_DATA_FAIL = 0x2A,
+	HALMAC_RET_DUMP_FIFOSIZE_INCORRECT = 0x2B,
+	HALMAC_RET_NULL_POINTER = 0x2C,
+	HALMAC_RET_PROBE_NOT_FOUND = 0x2D,
+	HALMAC_RET_FW_NO_MEMORY = 0x2E,
+	HALMAC_RET_H2C_STATUS_ERR = 0x2F,
+	HALMAC_RET_GET_H2C_SPACE_ERR = 0x30,
+	HALMAC_RET_H2C_SPACE_FULL = 0x31,
+	HALMAC_RET_DATAPACK_NO_FOUND = 0x32,
+	HALMAC_RET_CANNOT_FIND_H2C_RESOURCE = 0x33,
+	HALMAC_RET_TX_DMA_ERR = 0x34,
+	HALMAC_RET_RX_DMA_ERR = 0x35,
+	HALMAC_RET_CHIP_NOT_SUPPORT = 0x36,
+	HALMAC_RET_FREE_SPACE_NOT_ENOUGH = 0x37,
+	HALMAC_RET_CH_SW_SEQ_WRONG = 0x38,
+	HALMAC_RET_CH_SW_NO_BUF = 0x39,
+	HALMAC_RET_SW_CASE_NOT_SUPPORT = 0x3A,
+	HALMAC_RET_CONVERT_SDIO_OFFSET_FAIL = 0x3B,
+	HALMAC_RET_INVALID_SOUNDING_SETTING = 0x3C,
+	HALMAC_RET_GEN_INFO_NOT_SENT = 0x3D,
+	HALMAC_RET_STATE_INCORRECT = 0x3E,
+	HALMAC_RET_H2C_BUSY = 0x3F,
+	HALMAC_RET_INVALID_FEATURE_ID = 0x40,
+	HALMAC_RET_BUFFER_TOO_SMALL = 0x41,
+	HALMAC_RET_ZERO_LEN_RSVD_PACKET = 0x42,
+	HALMAC_RET_BUSY_STATE = 0x43,
+	HALMAC_RET_ERROR_STATE = 0x44,
+	HALMAC_RET_API_INVALID = 0x45,
+	HALMAC_RET_POLLING_BCN_VALID_FAIL = 0x46,
+	HALMAC_RET_SDIO_LEAVE_SUSPEND_FAIL = 0x47,
+	HALMAC_RET_EEPROM_PARSING_FAIL = 0x48,
+	HALMAC_RET_EFUSE_NOT_ENOUGH = 0x49,
+	HALMAC_RET_WRONG_ARGUMENT = 0x4A,
+	HALMAC_RET_C2H_NOT_HANDLED = 0x4C,
+	HALMAC_RET_PARA_SENDING = 0x4D,
+	HALMAC_RET_CFG_DLFW_SIZE_FAIL = 0x4E,
+	HALMAC_RET_CFG_TXFIFO_PAGE_FAIL = 0x4F,
+	HALMAC_RET_SWITCH_CASE_ERROR = 0x50,
+	HALMAC_RET_EFUSE_BANK_INCORRECT = 0x51,
+	HALMAC_RET_SWITCH_EFUSE_BANK_FAIL = 0x52,
+	HALMAC_RET_USB_MODE_UNCHANGE = 0x53,
+	HALMAC_RET_NO_DLFW = 0x54,
+	HALMAC_RET_USB2_3_SWITCH_UNSUPPORT = 0x55,
+	HALMAC_RET_BIP_NO_SUPPORT = 0x56,
+	HALMAC_RET_ENTRY_INDEX_ERROR = 0x57,
+	HALMAC_RET_ENTRY_KEY_ID_ERROR = 0x58,
+	HALMAC_RET_DRV_DL_ERR = 0x59,
+	HALMAC_RET_OQT_NOT_ENOUGH = 0x5A,
+	HALMAC_RET_PWR_UNCHANGE = 0x5B,
+	HALMAC_RET_WRONG_INTF = 0x5C,
+	HALMAC_RET_POLLING_HIOE_REQ_FAIL = 0x5E,
+	HALMAC_RET_HIOE_CHKSUM_FAIL = 0x5F,
+	HALMAC_RET_HIOE_ERR = 0x60,
+	HALMAC_RET_FW_NO_SUPPORT = 0x60,
+	HALMAC_RET_TXFIFO_NO_EMPTY = 0x61,
+	HALMAC_RET_SDIO_CLOCK_ERR = 0x62,
+	HALMAC_RET_GET_PINMUX_ERR = 0x63,
+	HALMAC_RET_PINMUX_USED = 0x64,
+	HALMAC_RET_WRONG_GPIO = 0x65,
+	HALMAC_RET_LTECOEX_READY_FAIL = 0x66,
+	HALMAC_RET_IDMEM_CHKSUM_FAIL = 0x67,
+	HALMAC_RET_ILLEGAL_KEY_FAIL = 0x68,
+	HALMAC_RET_FW_READY_CHK_FAIL = 0x69,
+	HALMAC_RET_RSVD_PG_OVERFLOW_FAIL = 0x70,
+	HALMAC_RET_THRESHOLD_FAIL = 0x71,
+	HALMAC_RET_SDIO_MIX_MODE = 0x72,
+	HALMAC_RET_TXDESC_SET_FAIL = 0x73,
+	HALMAC_RET_WLHDR_FAIL = 0x74,
+	HALMAC_RET_WLAN_MODE_FAIL = 0x75,
+};
+
+enum halmac_chip_id {
+	HALMAC_CHIP_ID_8822B = 0,
+	HALMAC_CHIP_ID_8821C = 1,
+	HALMAC_CHIP_ID_8814B = 2,
+	HALMAC_CHIP_ID_8197F = 3,
+	HALMAC_CHIP_ID_8822C = 4,
+	HALMAC_CHIP_ID_8812F = 5,
+	HALMAC_CHIP_ID_UNDEFINE = 0x7F,
+};
+
+enum halmac_chip_ver {
+	HALMAC_CHIP_VER_A_CUT = 0x00,
+	HALMAC_CHIP_VER_B_CUT = 0x01,
+	HALMAC_CHIP_VER_C_CUT = 0x02,
+	HALMAC_CHIP_VER_D_CUT = 0x03,
+	HALMAC_CHIP_VER_E_CUT = 0x04,
+	HALMAC_CHIP_VER_F_CUT = 0x05,
+	HALMAC_CHIP_VER_TEST = 0xFF,
+	HALMAC_CHIP_VER_UNDEFINE = 0x7FFF,
+};
+
+enum halmac_network_type_select {
+	HALMAC_NETWORK_NO_LINK = 0,
+	HALMAC_NETWORK_ADHOC = 1,
+	HALMAC_NETWORK_INFRASTRUCTURE = 2,
+	HALMAC_NETWORK_AP = 3,
+	HALMAC_NETWORK_UNDEFINE = 0x7F,
+};
+
+enum halmac_transfer_mode_select {
+	HALMAC_TRNSFER_NORMAL = 0x0,
+	HALMAC_TRNSFER_LOOPBACK_DIRECT = 0xB,
+	HALMAC_TRNSFER_LOOPBACK_DELAY = 0x3,
+	HALMAC_TRNSFER_UNDEFINE = 0x7F,
+};
+
+enum halmac_dma_mapping {
+	HALMAC_DMA_MAPPING_EXTRA = 0,
+	HALMAC_DMA_MAPPING_LOW = 1,
+	HALMAC_DMA_MAPPING_NORMAL = 2,
+	HALMAC_DMA_MAPPING_HIGH = 3,
+	HALMAC_DMA_MAPPING_UNDEFINE = 0x7F,
+};
+
+enum halmac_io_size {
+	HALMAC_IO_BYTE = 0x0,
+	HALMAC_IO_WORD = 0x1,
+	HALMAC_IO_DWORD = 0x2,
+	HALMAC_IO_UNDEFINE = 0x7F,
+};
+
+#define HALMAC_MAP2_HQ		HALMAC_DMA_MAPPING_HIGH
+#define HALMAC_MAP2_NQ		HALMAC_DMA_MAPPING_NORMAL
+#define HALMAC_MAP2_LQ		HALMAC_DMA_MAPPING_LOW
+#define HALMAC_MAP2_EXQ		HALMAC_DMA_MAPPING_EXTRA
+#define HALMAC_MAP2_UNDEF	HALMAC_DMA_MAPPING_UNDEFINE
+
+enum halmac_txdesc_queue_tid {
+	HALMAC_TXDESC_QSEL_TID0 = 0,
+	HALMAC_TXDESC_QSEL_TID1 = 1,
+	HALMAC_TXDESC_QSEL_TID2 = 2,
+	HALMAC_TXDESC_QSEL_TID3 = 3,
+	HALMAC_TXDESC_QSEL_TID4 = 4,
+	HALMAC_TXDESC_QSEL_TID5 = 5,
+	HALMAC_TXDESC_QSEL_TID6 = 6,
+	HALMAC_TXDESC_QSEL_TID7 = 7,
+	HALMAC_TXDESC_QSEL_TID8 = 8,
+	HALMAC_TXDESC_QSEL_TID9 = 9,
+	HALMAC_TXDESC_QSEL_TIDA = 10,
+	HALMAC_TXDESC_QSEL_TIDB = 11,
+	HALMAC_TXDESC_QSEL_TIDC = 12,
+	HALMAC_TXDESC_QSEL_TIDD = 13,
+	HALMAC_TXDESC_QSEL_TIDE = 14,
+	HALMAC_TXDESC_QSEL_TIDF = 15,
+
+	HALMAC_TXDESC_QSEL_BEACON = 0x10,
+	HALMAC_TXDESC_QSEL_HIGH = 0x11,
+	HALMAC_TXDESC_QSEL_MGT = 0x12,
+	HALMAC_TXDESC_QSEL_H2C_CMD = 0x13,
+	HALMAC_TXDESC_QSEL_FWCMD = 0x14,
+
+	HALMAC_TXDESC_QSEL_UNDEFINE = 0x7F,
+};
+
+enum halmac_pq_map_id {
+	HALMAC_PQ_MAP_VO = 0x0,
+	HALMAC_PQ_MAP_VI = 0x1,
+	HALMAC_PQ_MAP_BE = 0x2,
+	HALMAC_PQ_MAP_BK = 0x3,
+	HALMAC_PQ_MAP_MG = 0x4,
+	HALMAC_PQ_MAP_HI = 0x5,
+	HALMAC_PQ_MAP_NUM = 0x6,
+	HALMAC_PQ_MAP_UNDEF = 0x7F,
+};
+
+enum halmac_qsel {
+	HALMAC_QSEL_VO = HALMAC_TXDESC_QSEL_TID6,
+	HALMAC_QSEL_VI = HALMAC_TXDESC_QSEL_TID4,
+	HALMAC_QSEL_BE = HALMAC_TXDESC_QSEL_TID0,
+	HALMAC_QSEL_BK = HALMAC_TXDESC_QSEL_TID1,
+	HALMAC_QSEL_VO_V2 = HALMAC_TXDESC_QSEL_TID7,
+	HALMAC_QSEL_VI_V2 = HALMAC_TXDESC_QSEL_TID5,
+	HALMAC_QSEL_BE_V2 = HALMAC_TXDESC_QSEL_TID3,
+	HALMAC_QSEL_BK_V2 = HALMAC_TXDESC_QSEL_TID2,
+	HALMAC_QSEL_TID8 = HALMAC_TXDESC_QSEL_TID8,
+	HALMAC_QSEL_TID9 = HALMAC_TXDESC_QSEL_TID9,
+	HALMAC_QSEL_TIDA = HALMAC_TXDESC_QSEL_TIDA,
+	HALMAC_QSEL_TIDB = HALMAC_TXDESC_QSEL_TIDB,
+	HALMAC_QSEL_TIDC = HALMAC_TXDESC_QSEL_TIDC,
+	HALMAC_QSEL_TIDD = HALMAC_TXDESC_QSEL_TIDD,
+	HALMAC_QSEL_TIDE = HALMAC_TXDESC_QSEL_TIDE,
+	HALMAC_QSEL_TIDF = HALMAC_TXDESC_QSEL_TIDF,
+	HALMAC_QSEL_BCN = HALMAC_TXDESC_QSEL_BEACON,
+	HALMAC_QSEL_HIGH = HALMAC_TXDESC_QSEL_HIGH,
+	HALMAC_QSEL_MGNT = HALMAC_TXDESC_QSEL_MGT,
+	HALMAC_QSEL_CMD = HALMAC_TXDESC_QSEL_H2C_CMD,
+	HALMAC_QSEL_FWCMD = HALMAC_TXDESC_QSEL_FWCMD,
+	HALMAC_QSEL_UNDEFINE = 0x7F,
+};
+
+enum halmac_acq_id {
+	HALMAC_ACQ_ID_VO = 0,
+	HALMAC_ACQ_ID_VI = 1,
+	HALMAC_ACQ_ID_BE = 2,
+	HALMAC_ACQ_ID_BK = 3,
+	HALMAC_ACQ_ID_MAX = 0x7F,
+};
+
+enum halmac_txdesc_dma_ch {
+	HALMAC_TXDESC_DMA_CH0 = 0,
+	HALMAC_TXDESC_DMA_CH1 = 1,
+	HALMAC_TXDESC_DMA_CH2 = 2,
+	HALMAC_TXDESC_DMA_CH3 = 3,
+	HALMAC_TXDESC_DMA_CH4 = 4,
+	HALMAC_TXDESC_DMA_CH5 = 5,
+	HALMAC_TXDESC_DMA_CH6 = 6,
+	HALMAC_TXDESC_DMA_CH7 = 7,
+	HALMAC_TXDESC_DMA_CH8 = 8,
+	HALMAC_TXDESC_DMA_CH9 = 9,
+	HALMAC_TXDESC_DMA_CH10 = 10,
+	HALMAC_TXDESC_DMA_CH11 = 11,
+	HALMAC_TXDESC_DMA_CH12 = 12,
+	HALMAC_TXDESC_DMA_CH13 = 13,
+	HALMAC_TXDESC_DMA_CH14 = 14,
+	HALMAC_TXDESC_DMA_CH15 = 15,
+	HALMAC_TXDESC_DMA_CH16 = 16,
+	HALMAC_TXDESC_DMA_CH17 = 17,
+	HALMAC_TXDESC_DMA_CH18 = 18,
+	HALMAC_TXDESC_DMA_CH19 = 19,
+	HALMAC_TXDESC_DMA_CH20 = 20,
+	HALMAC_TXDESC_DMA_CHMAX,
+	HALMAC_TXDESC_DMA_CHUNDEFINE = 0x7F,
+};
+
+enum halmac_dma_ch {
+	HALMAC_DMA_CH_0 = HALMAC_TXDESC_DMA_CH0,
+	HALMAC_DMA_CH_1 = HALMAC_TXDESC_DMA_CH1,
+	HALMAC_DMA_CH_2 = HALMAC_TXDESC_DMA_CH2,
+	HALMAC_DMA_CH_3 = HALMAC_TXDESC_DMA_CH3,
+	HALMAC_DMA_CH_4 = HALMAC_TXDESC_DMA_CH4,
+	HALMAC_DMA_CH_5 = HALMAC_TXDESC_DMA_CH5,
+	HALMAC_DMA_CH_6 = HALMAC_TXDESC_DMA_CH6,
+	HALMAC_DMA_CH_7 = HALMAC_TXDESC_DMA_CH7,
+	HALMAC_DMA_CH_8 = HALMAC_TXDESC_DMA_CH8,
+	HALMAC_DMA_CH_9 = HALMAC_TXDESC_DMA_CH9,
+	HALMAC_DMA_CH_10 = HALMAC_TXDESC_DMA_CH10,
+	HALMAC_DMA_CH_11 = HALMAC_TXDESC_DMA_CH11,
+	HALMAC_DMA_CH_S0 = HALMAC_TXDESC_DMA_CH12,
+	HALMAC_DMA_CH_S1 = HALMAC_TXDESC_DMA_CH13,
+	HALMAC_DMA_CH_MGQ = HALMAC_TXDESC_DMA_CH14,
+	HALMAC_DMA_CH_HIGH = HALMAC_TXDESC_DMA_CH15,
+	HALMAC_DMA_CH_FWCMD = HALMAC_TXDESC_DMA_CH16,
+	HALMAC_DMA_CH_MGQ_BAND1 = HALMAC_TXDESC_DMA_CH17,
+	HALMAC_DMA_CH_HIGH_BAND1 = HALMAC_TXDESC_DMA_CH18,
+	HALMAC_DMA_CH_BCN = HALMAC_TXDESC_DMA_CH19,
+	HALMAC_DMA_CH_H2C = HALMAC_TXDESC_DMA_CH20,
+	HALMAC_DMA_CH_MAX = HALMAC_TXDESC_DMA_CHMAX,
+	HALMAC_DMA_CH_UNDEFINE = 0x7F,
+};
+
+enum halmac_interface {
+	HALMAC_INTERFACE_PCIE = 0x0,
+	HALMAC_INTERFACE_USB = 0x1,
+	HALMAC_INTERFACE_SDIO = 0x2,
+	HALMAC_INTERFACE_AXI = 0x3,
+	HALMAC_INTERFACE_UNDEFINE = 0x7F,
+};
+
+enum halmac_rx_agg_mode {
+	HALMAC_RX_AGG_MODE_NONE = 0x0,
+	HALMAC_RX_AGG_MODE_DMA = 0x1,
+	HALMAC_RX_AGG_MODE_USB = 0x2,
+	HALMAC_RX_AGG_MODE_UNDEFINE = 0x7F,
+};
+
+struct halmac_rxagg_th {
+	u8 drv_define;
+	u8 timeout;
+	u8 size;
+	u8 size_limit_en;
+};
+
+struct halmac_rxagg_cfg {
+	enum halmac_rx_agg_mode mode;
+	struct halmac_rxagg_th threshold;
+};
+
+struct halmac_api_registry {
+	u8 rx_exp_en:1;
+	u8 la_mode_en:1;
+	u8 cfg_drv_rsvd_pg_en:1;
+	u8 sdio_cmd53_4byte_en:1;
+	u8 rsvd:4;
+};
+
+enum halmac_trx_mode {
+	HALMAC_TRX_MODE_NORMAL = 0x0,
+	HALMAC_TRX_MODE_TRXSHARE = 0x1,
+	HALMAC_TRX_MODE_WMM = 0x2,
+	HALMAC_TRX_MODE_P2P = 0x3,
+	HALMAC_TRX_MODE_LOOPBACK = 0x4,
+	HALMAC_TRX_MODE_DELAY_LOOPBACK = 0x5,
+	HALMAC_TRX_MODE_MAX = 0x6,
+	HALMAC_TRX_MODE_WMM_LINUX = 0x7E,
+	HALMAC_TRX_MODE_UNDEFINE = 0x7F,
+};
+
+enum halmac_wireless_mode {
+	HALMAC_WIRELESS_MODE_B = 0x0,
+	HALMAC_WIRELESS_MODE_G = 0x1,
+	HALMAC_WIRELESS_MODE_N = 0x2,
+	HALMAC_WIRELESS_MODE_AC = 0x3,
+	HALMAC_WIRELESS_MODE_UNDEFINE = 0x7F,
+};
+
+enum halmac_bw {
+	HALMAC_BW_20 = 0x00,
+	HALMAC_BW_40 = 0x01,
+	HALMAC_BW_80 = 0x02,
+	HALMAC_BW_160 = 0x03,
+	HALMAC_BW_5 = 0x04,
+	HALMAC_BW_10 = 0x05,
+	HALMAC_BW_MAX = 0x06,
+	HALMAC_BW_UNDEFINE = 0x7F,
+};
+
+enum halmac_efuse_read_cfg {
+	HALMAC_EFUSE_R_AUTO = 0x00,
+	HALMAC_EFUSE_R_DRV = 0x01,
+	HALMAC_EFUSE_R_FW = 0x02,
+	HALMAC_EFUSE_R_UNDEFINE = 0x7F,
+};
+
+enum halmac_dlfw_mem {
+	HALMAC_DLFW_MEM_EMEM = 0x00,
+	HALMAC_DLFW_MEM_EMEM_RSVD_PG = 0x01,
+	HALMAC_DLFW_MEM_UNDEFINE = 0x7F,
+};
+
+struct halmac_tx_desc {
+	u32 dword0;
+	u32 dword1;
+	u32 dword2;
+	u32 dword3;
+	u32 dword4;
+	u32 dword5;
+	u32 dword6;
+	u32 dword7;
+	u32 dword8;
+	u32 dword9;
+	u32 dword10;
+	u32 dword11;
+};
+
+struct halmac_rx_desc {
+	u32 dword0;
+	u32 dword1;
+	u32 dword2;
+	u32 dword3;
+	u32 dword4;
+	u32 dword5;
+};
+
+struct halmac_bcn_ie_info {
+	u8 func_en;
+	u8 size_th;
+	u8 timeout;
+	u8 ie_bmp[HALMAC_BCN_IE_BMP_SIZE];
+};
+
+enum halmac_parameter_cmd {
+	/* HALMAC_PARAMETER_CMD_LLT	= 0x1, */
+	/* HALMAC_PARAMETER_CMD_R_EFUSE = 0x2, */
+	/* HALMAC_PARAMETER_CMD_EFUSE_PATCH = 0x3, */
+	HALMAC_PARAMETER_CMD_MAC_W8 = 0x4,
+	HALMAC_PARAMETER_CMD_MAC_W16 = 0x5,
+	HALMAC_PARAMETER_CMD_MAC_W32 = 0x6,
+	HALMAC_PARAMETER_CMD_RF_W = 0x7,
+	HALMAC_PARAMETER_CMD_BB_W8 = 0x8,
+	HALMAC_PARAMETER_CMD_BB_W16 = 0x9,
+	HALMAC_PARAMETER_CMD_BB_W32 = 0XA,
+	HALMAC_PARAMETER_CMD_DELAY_US = 0X10,
+	HALMAC_PARAMETER_CMD_DELAY_MS = 0X11,
+	HALMAC_PARAMETER_CMD_END = 0XFF,
+};
+
+union halmac_parameter_content {
+	struct _MAC_REG_W {
+		u32 value;
+		u32 msk;
+		u16 offset;
+		u8 msk_en;
+	} MAC_REG_W;
+	struct _BB_REG_W {
+		u32 value;
+		u32 msk;
+		u16 offset;
+		u8 msk_en;
+	} BB_REG_W;
+	struct _RF_REG_W {
+		u32 value;
+		u32 msk;
+		u8 offset;
+		u8 msk_en;
+		u8 rf_path;
+	} RF_REG_W;
+	struct _DELAY_TIME {
+		u32 rsvd1;
+		u32 rsvd2;
+		u16 delay_time;
+		u8 rsvd3;
+	} DELAY_TIME;
+};
+
+struct halmac_phy_parameter_info {
+	enum halmac_parameter_cmd cmd_id;
+	union halmac_parameter_content content;
+};
+
+struct halmac_pg_efuse_info {
+	u8 *efuse_map;
+	u32 efuse_map_size;
+	u8 *efuse_mask;
+	u32 efuse_mask_size;
+};
+
+struct halmac_cfg_param_info {
+	u32 buf_size;
+	u8 *buf;
+	u8 *buf_wptr;
+	u32 num;
+	u32 avl_buf_size;
+	u32 offset_accum;
+	u32 value_accum;
+	enum halmac_data_type data_type;
+	u8 full_fifo_mode;
+};
+
+struct halmac_hw_cfg_info {
+	u32 efuse_size;
+	u32 eeprom_size;
+	u32 bt_efuse_size;
+	u32 tx_fifo_size;
+	u32 rx_fifo_size;
+	u32 rx_desc_fifo_size;
+	u32 page_size;
+	u16 tx_align_size;
+	u8 txdesc_size;
+	u8 rxdesc_size;
+	u8 cam_entry_num;
+	u8 chk_security_keyid;
+	u8 txdesc_ie_max_num;
+	u8 txdesc_body_size;
+	u8 ac_oqt_size;
+	u8 non_ac_oqt_size;
+	u8 acq_num;
+	u8 trx_mode;
+	u8 usb_txagg_num;
+};
+
+struct halmac_sdio_free_space {
+	u16 hiq_pg_num;
+	u16 miq_pg_num;
+	u16 lowq_pg_num;
+	u16 pubq_pg_num;
+	u16 exq_pg_num;
+	u8 ac_oqt_num;
+	u8 non_ac_oqt_num;
+	u8 ac_empty;
+	u8 *macid_map;
+	u32 macid_map_size;
+};
+
+enum hal_fifo_sel {
+	HAL_FIFO_SEL_TX,
+	HAL_FIFO_SEL_RX,
+	HAL_FIFO_SEL_RSVD_PAGE,
+	HAL_FIFO_SEL_REPORT,
+	HAL_FIFO_SEL_LLT,
+	HAL_FIFO_SEL_RXBUF_FW,
+	HAL_FIFO_SEL_RXBUF_PHY,
+	HAL_FIFO_SEL_RXDESC,
+	HAL_BUF_SECURITY_CAM,
+	HAL_BUF_WOW_CAM,
+	HAL_BUF_RX_FILTER_CAM,
+	HAL_BUF_BA_CAM,
+	HAL_BUF_MBSSID_CAM
+};
+
+enum halmac_drv_info {
+	/* No information is appended in rx_pkt */
+	HALMAC_DRV_INFO_NONE,
+	/* PHY status is appended after rx_desc */
+	HALMAC_DRV_INFO_PHY_STATUS,
+	/* PHY status and sniffer info are appended after rx_desc */
+	HALMAC_DRV_INFO_PHY_SNIFFER,
+	/* PHY status and plcp header are appended after rx_desc */
+	HALMAC_DRV_INFO_PHY_PLCP,
+	HALMAC_DRV_INFO_UNDEFINE,
+};
+
+enum halmac_pri_ch_idx {
+	HALMAC_CH_IDX_UNDEFINE = 0,
+	HALMAC_CH_IDX_1 = 1,
+	HALMAC_CH_IDX_2 = 2,
+	HALMAC_CH_IDX_3 = 3,
+	HALMAC_CH_IDX_4 = 4,
+	HALMAC_CH_IDX_MAX = 5,
+};
+
+struct halmac_ch_info {
+	enum halmac_cs_action_id action_id;
+	enum halmac_bw bw;
+	enum halmac_pri_ch_idx pri_ch_idx;
+	u8 channel;
+	u8 timeout;
+	u8 extra_info;
+};
+
+struct halmac_ch_extra_info {
+	u8 extra_info;
+	enum halmac_cs_extra_action_id extra_action_id;
+	u8 extra_info_size;
+	u8 *extra_info_data;
+};
+
+enum halmac_cs_periodic_option {
+	HALMAC_CS_PERIODIC_NONE,
+	HALMAC_CS_PERIODIC_NORMAL,
+	HALMAC_CS_PERIODIC_2_PHASE,
+	HALMAC_CS_PERIODIC_SEAMLESS,
+};
+
+struct halmac_ch_switch_option {
+	enum halmac_bw dest_bw;
+	enum halmac_cs_periodic_option periodic_option;
+	enum halmac_pri_ch_idx dest_pri_ch_idx;
+	/* u32 tsf_high; */
+	u32 tsf_low;
+	u8 switch_en;
+	u8 dest_ch_en;
+	u8 absolute_time_en;
+	u8 dest_ch;
+	u8 normal_period;
+	u8 normal_period_sel;
+	u8 normal_cycle;
+	u8 phase_2_period;
+	u8 phase_2_period_sel;
+};
+
+struct halmac_p2pps {
+	u8 offload_en:1;
+	u8 role:1;
+	u8 ctwindow_en:1;
+	u8 noa_en:1;
+	u8 noa_sel:1;
+	u8 all_sta_sleep:1;
+	u8 discovery:1;
+	u8 disable_close_rf:1;
+	u8 p2p_port_id;
+	u8 p2p_group;
+	u8 p2p_macid;
+	u8 ctwindow_length;
+	u8 rsvd3;
+	u8 rsvd4;
+	u8 rsvd5;
+	u32 noa_duration_para;
+	u32 noa_interval_para;
+	u32 noa_start_time_para;
+	u32 noa_count_para;
+};
+
+struct halmac_fw_build_time {
+	u16 year;
+	u8 month;
+	u8 date;
+	u8 hour;
+	u8 min;
+};
+
+struct halmac_fw_version {
+	u16 version;
+	u8 sub_version;
+	u8 sub_index;
+	u16 h2c_version;
+	struct halmac_fw_build_time build_time;
+};
+
+enum halmac_rf_type {
+	HALMAC_RF_1T2R = 0,
+	HALMAC_RF_2T4R = 1,
+	HALMAC_RF_2T2R = 2,
+	HALMAC_RF_2T3R = 3,
+	HALMAC_RF_1T1R = 4,
+	HALMAC_RF_2T2R_GREEN = 5,
+	HALMAC_RF_3T3R = 6,
+	HALMAC_RF_3T4R = 7,
+	HALMAC_RF_4T4R = 8,
+	HALMAC_RF_MAX_TYPE = 0xF,
+};
+
+struct halmac_general_info {
+	u8 rfe_type;
+	enum halmac_rf_type rf_type;
+	u8 tx_ant_status;
+	u8 rx_ant_status;
+};
+
+struct halmac_pwr_tracking_para {
+	u8 enable;
+	u8 tx_pwr_index;
+	u8 pwr_tracking_offset_value;
+	u8 tssi_value;
+};
+
+struct halmac_pwr_tracking_option {
+	u8 type;
+	u8 bbswing_index;
+	/* pathA, pathB, pathC, pathD */
+	struct halmac_pwr_tracking_para pwr_tracking_para[4];
+};
+
+struct halmac_fast_edca_cfg {
+	enum halmac_acq_id acq_id;
+	u8 queue_to; /* unit : 32us*/
+};
+
+enum halmac_data_rate {
+	HALMAC_CCK1,
+	HALMAC_CCK2,
+	HALMAC_CCK5_5,
+	HALMAC_CCK11,
+	HALMAC_OFDM6,
+	HALMAC_OFDM9,
+	HALMAC_OFDM12,
+	HALMAC_OFDM18,
+	HALMAC_OFDM24,
+	HALMAC_OFDM36,
+	HALMAC_OFDM48,
+	HALMAC_OFDM54,
+	HALMAC_MCS0,
+	HALMAC_MCS1,
+	HALMAC_MCS2,
+	HALMAC_MCS3,
+	HALMAC_MCS4,
+	HALMAC_MCS5,
+	HALMAC_MCS6,
+	HALMAC_MCS7,
+	HALMAC_MCS8,
+	HALMAC_MCS9,
+	HALMAC_MCS10,
+	HALMAC_MCS11,
+	HALMAC_MCS12,
+	HALMAC_MCS13,
+	HALMAC_MCS14,
+	HALMAC_MCS15,
+	HALMAC_MCS16,
+	HALMAC_MCS17,
+	HALMAC_MCS18,
+	HALMAC_MCS19,
+	HALMAC_MCS20,
+	HALMAC_MCS21,
+	HALMAC_MCS22,
+	HALMAC_MCS23,
+	HALMAC_MCS24,
+	HALMAC_MCS25,
+	HALMAC_MCS26,
+	HALMAC_MCS27,
+	HALMAC_MCS28,
+	HALMAC_MCS29,
+	HALMAC_MCS30,
+	HALMAC_MCS31,
+	HALMAC_VHT_NSS1_MCS0,
+	HALMAC_VHT_NSS1_MCS1,
+	HALMAC_VHT_NSS1_MCS2,
+	HALMAC_VHT_NSS1_MCS3,
+	HALMAC_VHT_NSS1_MCS4,
+	HALMAC_VHT_NSS1_MCS5,
+	HALMAC_VHT_NSS1_MCS6,
+	HALMAC_VHT_NSS1_MCS7,
+	HALMAC_VHT_NSS1_MCS8,
+	HALMAC_VHT_NSS1_MCS9,
+	HALMAC_VHT_NSS2_MCS0,
+	HALMAC_VHT_NSS2_MCS1,
+	HALMAC_VHT_NSS2_MCS2,
+	HALMAC_VHT_NSS2_MCS3,
+	HALMAC_VHT_NSS2_MCS4,
+	HALMAC_VHT_NSS2_MCS5,
+	HALMAC_VHT_NSS2_MCS6,
+	HALMAC_VHT_NSS2_MCS7,
+	HALMAC_VHT_NSS2_MCS8,
+	HALMAC_VHT_NSS2_MCS9,
+	HALMAC_VHT_NSS3_MCS0,
+	HALMAC_VHT_NSS3_MCS1,
+	HALMAC_VHT_NSS3_MCS2,
+	HALMAC_VHT_NSS3_MCS3,
+	HALMAC_VHT_NSS3_MCS4,
+	HALMAC_VHT_NSS3_MCS5,
+	HALMAC_VHT_NSS3_MCS6,
+	HALMAC_VHT_NSS3_MCS7,
+	HALMAC_VHT_NSS3_MCS8,
+	HALMAC_VHT_NSS3_MCS9,
+	HALMAC_VHT_NSS4_MCS0,
+	HALMAC_VHT_NSS4_MCS1,
+	HALMAC_VHT_NSS4_MCS2,
+	HALMAC_VHT_NSS4_MCS3,
+	HALMAC_VHT_NSS4_MCS4,
+	HALMAC_VHT_NSS4_MCS5,
+	HALMAC_VHT_NSS4_MCS6,
+	HALMAC_VHT_NSS4_MCS7,
+	HALMAC_VHT_NSS4_MCS8,
+	HALMAC_VHT_NSS4_MCS9,
+	 /*FPGA only*/
+	HALMAC_VHT_NSS5_MCS0,
+	HALMAC_VHT_NSS6_MCS0,
+	HALMAC_VHT_NSS7_MCS0,
+	HALMAC_VHT_NSS8_MCS0
+};
+
+enum halmac_rf_path {
+	HALMAC_RF_PATH_A,
+	HALMAC_RF_PATH_B,
+	HALMAC_RF_PATH_C,
+	HALMAC_RF_PATH_D
+};
+
+enum hal_security_type {
+	HAL_SECURITY_TYPE_NONE = 0,
+	HAL_SECURITY_TYPE_WEP40 = 1,
+	HAL_SECURITY_TYPE_WEP104 = 2,
+	HAL_SECURITY_TYPE_TKIP = 3,
+	HAL_SECURITY_TYPE_AES128 = 4,
+	HAL_SECURITY_TYPE_WAPI = 5,
+	HAL_SECURITY_TYPE_AES256 = 6,
+	HAL_SECURITY_TYPE_GCMP128 = 7,
+	HAL_SECURITY_TYPE_GCMP256 = 8,
+	HAL_SECURITY_TYPE_GCMSMS4 = 9,
+	HAL_SECURITY_TYPE_BIP = 10,
+	HAL_SECURITY_TYPE_UNDEFINE = 0x7F,
+};
+
+enum hal_intf_phy {
+	HAL_INTF_PHY_USB2 = 0,
+	HAL_INTF_PHY_USB3 = 1,
+	HAL_INTF_PHY_PCIE_GEN1 = 2,
+	HAL_INTF_PHY_PCIE_GEN2 = 3,
+	HAL_INTF_PHY_UNDEFINE = 0x7F,
+};
+
+struct halmac_cut_amsdu_cfg {
+	u8 cut_amsdu_en;
+	u8 chk_len_en;
+	u8 chk_len_def_val;
+	u8 chk_len_l_th;
+	u16 chk_len_h_th;
+};
+
+enum halmac_dbg_msg_info {
+	HALMAC_DBG_ALWAYS,
+	HALMAC_DBG_ERR,
+	HALMAC_DBG_WARN,
+	HALMAC_DBG_TRACE,
+};
+
+enum halmac_dbg_msg_type {
+	HALMAC_MSG_INIT,
+	HALMAC_MSG_EFUSE,
+	HALMAC_MSG_FW,
+	HALMAC_MSG_H2C,
+	HALMAC_MSG_PWR,
+	HALMAC_MSG_SND,
+	HALMAC_MSG_COMMON,
+	HALMAC_MSG_DBI,
+	HALMAC_MSG_MDIO,
+	HALMAC_MSG_USB,
+};
+
+enum halmac_feature_id {
+	HALMAC_FEATURE_CFG_PARA,                /* Support */
+	HALMAC_FEATURE_DUMP_PHYSICAL_EFUSE,     /* Support */
+	HALMAC_FEATURE_DUMP_LOGICAL_EFUSE,      /* Support */
+	HALMAC_FEATURE_UPDATE_PACKET,           /* Support */
+	HALMAC_FEATURE_UPDATE_DATAPACK,
+	HALMAC_FEATURE_RUN_DATAPACK,
+	HALMAC_FEATURE_CHANNEL_SWITCH,  /* Support */
+	HALMAC_FEATURE_IQK,             /* Support */
+	HALMAC_FEATURE_POWER_TRACKING,  /* Support */
+	HALMAC_FEATURE_PSD,             /* Support */
+	HALMAC_FEATURE_FW_SNDING,       /* Support */
+	HALMAC_FEATURE_ALL,             /* Support, only for reset */
+};
+
+enum halmac_drv_rsvd_pg_num {
+	HALMAC_RSVD_PG_NUM8,	/* 1K */
+	HALMAC_RSVD_PG_NUM16,   /* 2K */
+	HALMAC_RSVD_PG_NUM24,   /* 3K */
+	HALMAC_RSVD_PG_NUM32,   /* 4K */
+	HALMAC_RSVD_PG_NUM64,   /* 8K */
+	HALMAC_RSVD_PG_NUM128,  /* 16K */
+};
+
+enum halmac_pcie_cfg {
+	HALMAC_PCIE_GEN1,
+	HALMAC_PCIE_GEN2,
+	HALMAC_PCIE_CFG_UNDEFINE,
+};
+
+enum halmac_portid {
+	HALMAC_PORTID0 = 0,
+	HALMAC_PORTID1 = 1,
+	HALMAC_PORTID2 = 2,
+	HALMAC_PORTID3 = 3,
+	HALMAC_PORTID4 = 4,
+	HALMAC_PORTID_NUM = 5,
+};
+
+struct halmac_bcn_ctrl {
+	u8 dis_rx_bssid_fit;
+	u8 en_txbcn_rpt;
+	u8 dis_tsf_udt;
+	u8 en_bcn;
+	u8 en_rxbcn_rpt;
+	u8 en_p2p_ctwin;
+	u8 en_p2p_bcn_area;
+};
+
+/* User only can use  Address[6]*/
+/* Address[0] is lowest, Address[5] is highest */
+union halmac_wlan_addr {
+	u8 addr[6];
+	struct {
+		union {
+			__le32 low;
+			u8 low_byte[4];
+		};
+		union {
+			__le16 high;
+			u8 high_byte[2];
+		};
+	} addr_l_h;
+};
+
+struct halmac_platform_api {
+	/* R/W register */
+	u8 (*SDIO_CMD52_READ)(void *drv_adapter, u32 offset);
+	u8 (*SDIO_CMD53_READ_8)(void *drv_adapter, u32 offset);
+	u16 (*SDIO_CMD53_READ_16)(void *drv_adapter, u32 offset);
+	u32 (*SDIO_CMD53_READ_32)(void *drv_adapter, u32 offset);
+	u8 (*SDIO_CMD53_READ_N)(void *drv_adapter, u32 offset, u32 size,
+				u8 *data);
+	void (*SDIO_CMD52_WRITE)(void *drv_adapter, u32 offset, u8 value);
+	void (*SDIO_CMD53_WRITE_8)(void *drv_adapter, u32 offset, u8 value);
+	void (*SDIO_CMD53_WRITE_16)(void *drv_adapter, u32 offset, u16 value);
+	void (*SDIO_CMD53_WRITE_32)(void *drv_adapter, u32 offset, u32 value);
+	u8 (*REG_READ_8)(void *drv_adapter, u32 offset);
+	u16 (*REG_READ_16)(void *drv_adapter, u32 offset);
+	u32 (*REG_READ_32)(void *drv_adapter, u32 offset);
+	void (*REG_WRITE_8)(void *drv_adapter, u32 offset, u8 value);
+	void (*REG_WRITE_16)(void *drv_adapter, u32 offset, u16 value);
+	void (*REG_WRITE_32)(void *drv_adapter, u32 offset, u32 value);
+	u8 (*SDIO_CMD52_CIA_READ)(void *drv_adapter, u32 offset);
+
+	/* send pBuf to reserved page, the tx_desc is not included in pBuf */
+	/* driver need to fill tx_desc with qsel = bcn */
+	u8 (*SEND_RSVD_PAGE)(void *drv_adapter, u8 *buf, u32 size);
+	/* send pBuf to h2c queue, the tx_desc is not included in pBuf */
+	/* driver need to fill tx_desc with qsel = h2c */
+	u8 (*SEND_H2C_PKT)(void *drv_adapter, u8 *buf, u32 size);
+
+	u8 (*RTL_FREE)(void *drv_adapter, void *buf, u32 size);
+	void* (*RTL_MALLOC)(void *drv_adapter, u32 size);
+	u8 (*RTL_MEMCPY)(void *drv_adapter, void *dest, void *src, u32 size);
+	u8 (*RTL_MEMSET)(void *drv_adapter, void *addr, u8 value, u32 size);
+	void (*RTL_DELAY_US)(void *drv_adapter, u32 us);
+
+	u8 (*MUTEX_INIT)(void *drv_adapter, HALMAC_MUTEX *mutex);
+	u8 (*MUTEX_DEINIT)(void *drv_adapter, HALMAC_MUTEX *mutex);
+	u8 (*MUTEX_LOCK)(void *drv_adapter, HALMAC_MUTEX *mutex);
+	u8 (*MUTEX_UNLOCK)(void *drv_adapter, HALMAC_MUTEX *mutex);
+
+	u8 (*MSG_PRINT)(void *drv_adapter, u32 msg_type, u8 msg_level,
+			s8 *fmt, ...);
+	u8 (*BUFF_PRINT)(void *drv_adapter, u32 msg_type, u8 msg_level, s8 *buf,
+			 u32 size);
+
+	u8 (*EVENT_INDICATION)(void *drv_adapter,
+			       enum halmac_feature_id feature_id,
+			       enum halmac_cmd_process_status process_status,
+			       u8 *buf, u32 size);
+
+#if HALMAC_PLATFORM_TESTPROGRAM
+	struct halmisc_platform_api *halmisc_pltfm_api;
+#endif
+};
+
+enum halmac_snd_role {
+	HAL_BFER = 0,
+	HAL_BFEE = 1,
+};
+
+enum halmac_csi_seg_len {
+	HAL_CSI_SEG_4K = 0,
+	HAL_CSI_SEG_8K = 1,
+	HAL_CSI_SEG_11K = 2,
+};
+
+struct halmac_cfg_mumimo_para {
+	enum halmac_snd_role role;
+	u8 sounding_sts[6];
+	u16 grouping_bitmap;
+	u8 mu_tx_en;
+	u32 given_gid_tab[2];
+	u32 given_user_pos[4];
+};
+
+struct halmac_su_bfer_init_para {
+	u8 userid;
+	u16 paid;
+	u16 csi_para;
+	union halmac_wlan_addr bfer_address;
+};
+
+struct halmac_mu_bfee_init_para {
+	u8 userid;
+	u16 paid;
+	u32 user_position_l;	/*for gid 0~15*/
+	u32 user_position_h;	/*for gid 16~31*/
+	u32 user_position_l_1;	/*for gid 32~47*/
+	u32 user_position_h_1;	/*for gid 48~63*/
+};
+
+struct halmac_mu_bfer_init_para {
+	u16 paid;
+	u16 csi_para;
+	u16 my_aid;
+	enum halmac_csi_seg_len csi_length_sel;
+	union halmac_wlan_addr bfer_address;
+};
+
+struct halmac_ch_sw_info {
+	u8 *buf;
+	u8 *buf_wptr;
+	u8 extra_info_en;
+	u32 buf_size;
+	u32 avl_buf_size;
+	u32 total_size;
+	u32 ch_num;
+};
+
+struct halmac_event_trigger {
+	u32 phy_efuse_map : 1;
+	u32 log_efuse_map : 1;
+	u32 rsvd1 : 28;
+};
+
+struct halmac_h2c_header_info {
+	u16 sub_cmd_id;
+	u16 content_size;
+	u8 ack;
+};
+
+struct halmac_ver {
+	u8 major_ver;
+	u8 prototype_ver;
+	u8 minor_ver;
+};
+
+enum halmac_api_id {
+	/*stuff, need to be the 1st*/
+	HALMAC_API_STUFF = 0x0,
+	/*stuff, need to be the 1st*/
+	HALMAC_API_MAC_POWER_SWITCH = 0x1,
+	HALMAC_API_DOWNLOAD_FIRMWARE = 0x2,
+	HALMAC_API_CFG_MAC_ADDR = 0x3,
+	HALMAC_API_CFG_BSSID = 0x4,
+	HALMAC_API_CFG_MULTICAST_ADDR = 0x5,
+	HALMAC_API_PRE_INIT_SYSTEM_CFG = 0x6,
+	HALMAC_API_INIT_SYSTEM_CFG = 0x7,
+	HALMAC_API_INIT_TRX_CFG = 0x8,
+	HALMAC_API_CFG_RX_AGGREGATION = 0x9,
+	HALMAC_API_INIT_PROTOCOL_CFG = 0xA,
+	HALMAC_API_INIT_EDCA_CFG = 0xB,
+	HALMAC_API_CFG_OPERATION_MODE = 0xC,
+	HALMAC_API_CFG_CH_BW = 0xD,
+	HALMAC_API_CFG_BW = 0xE,
+	HALMAC_API_INIT_WMAC_CFG = 0xF,
+	HALMAC_API_INIT_MAC_CFG = 0x10,
+	HALMAC_API_INIT_SDIO_CFG = 0x11,
+	HALMAC_API_INIT_USB_CFG = 0x12,
+	HALMAC_API_INIT_PCIE_CFG = 0x13,
+	HALMAC_API_INIT_INTERFACE_CFG = 0x14,
+	HALMAC_API_DEINIT_SDIO_CFG = 0x15,
+	HALMAC_API_DEINIT_USB_CFG = 0x16,
+	HALMAC_API_DEINIT_PCIE_CFG = 0x17,
+	HALMAC_API_DEINIT_INTERFACE_CFG = 0x18,
+	HALMAC_API_GET_EFUSE_SIZE = 0x19,
+	HALMAC_API_DUMP_EFUSE_MAP = 0x1A,
+	HALMAC_API_GET_LOGICAL_EFUSE_SIZE = 0x1D,
+	HALMAC_API_DUMP_LOGICAL_EFUSE_MAP = 0x1E,
+	HALMAC_API_WRITE_LOGICAL_EFUSE = 0x1F,
+	HALMAC_API_READ_LOGICAL_EFUSE = 0x20,
+	HALMAC_API_PG_EFUSE_BY_MAP = 0x21,
+	HALMAC_API_GET_C2H_INFO = 0x22,
+	HALMAC_API_CFG_FWLPS_OPTION = 0x23,
+	HALMAC_API_CFG_FWIPS_OPTION = 0x24,
+	HALMAC_API_ENTER_WOWLAN = 0x25,
+	HALMAC_API_LEAVE_WOWLAN = 0x26,
+	HALMAC_API_ENTER_PS = 0x27,
+	HALMAC_API_LEAVE_PS = 0x28,
+	HALMAC_API_H2C_LB = 0x29,
+	HALMAC_API_DEBUG = 0x2A,
+	HALMAC_API_CFG_PARAMETER = 0x2B,
+	HALMAC_API_UPDATE_PACKET = 0x2C,
+	HALMAC_API_BCN_IE_FILTER = 0x2D,
+	HALMAC_API_REG_READ_8 = 0x2E,
+	HALMAC_API_REG_WRITE_8 = 0x2F,
+	HALMAC_API_REG_READ_16 = 0x30,
+	HALMAC_API_REG_WRITE_16 = 0x31,
+	HALMAC_API_REG_READ_32 = 0x32,
+	HALMAC_API_REG_WRITE_32 = 0x33,
+	HALMAC_API_TX_ALLOWED_SDIO = 0x34,
+	HALMAC_API_SET_BULKOUT_NUM = 0x35,
+	HALMAC_API_GET_SDIO_TX_ADDR = 0x36,
+	HALMAC_API_GET_USB_BULKOUT_ID = 0x37,
+	HALMAC_API_TIMER_2S = 0x38,
+	HALMAC_API_FILL_TXDESC_CHECKSUM = 0x39,
+	HALMAC_API_SEND_ORIGINAL_H2C = 0x3A,
+	HALMAC_API_UPDATE_DATAPACK = 0x3B,
+	HALMAC_API_RUN_DATAPACK = 0x3C,
+	HALMAC_API_CFG_DRV_INFO = 0x3D,
+	HALMAC_API_SEND_BT_COEX = 0x3E,
+	HALMAC_API_VERIFY_PLATFORM_API = 0x3F,
+	HALMAC_API_GET_FIFO_SIZE = 0x40,
+	HALMAC_API_DUMP_FIFO = 0x41,
+	HALMAC_API_CFG_TXBF = 0x42,
+	HALMAC_API_CFG_MUMIMO = 0x43,
+	HALMAC_API_CFG_SOUNDING = 0x44,
+	HALMAC_API_DEL_SOUNDING = 0x45,
+	HALMAC_API_SU_BFER_ENTRY_INIT = 0x46,
+	HALMAC_API_SU_BFEE_ENTRY_INIT = 0x47,
+	HALMAC_API_MU_BFER_ENTRY_INIT = 0x48,
+	HALMAC_API_MU_BFEE_ENTRY_INIT = 0x49,
+	HALMAC_API_SU_BFER_ENTRY_DEL = 0x4A,
+	HALMAC_API_SU_BFEE_ENTRY_DEL = 0x4B,
+	HALMAC_API_MU_BFER_ENTRY_DEL = 0x4C,
+	HALMAC_API_MU_BFEE_ENTRY_DEL = 0x4D,
+	HALMAC_API_ADD_CH_INFO = 0x4E,
+	HALMAC_API_ADD_EXTRA_CH_INFO = 0x4F,
+	HALMAC_API_CTRL_CH_SWITCH = 0x50,
+	HALMAC_API_CLEAR_CH_INFO = 0x51,
+	HALMAC_API_SEND_GENERAL_INFO = 0x52,
+	HALMAC_API_START_IQK = 0x53,
+	HALMAC_API_CTRL_PWR_TRACKING = 0x54,
+	HALMAC_API_PSD = 0x55,
+	HALMAC_API_CFG_TX_AGG_ALIGN = 0x56,
+	HALMAC_API_QUERY_STATE = 0x57,
+	HALMAC_API_RESET_FEATURE = 0x58,
+	HALMAC_API_CHECK_FW_STATUS = 0x59,
+	HALMAC_API_DUMP_FW_DMEM = 0x5A,
+	HALMAC_API_CFG_MAX_DL_SIZE = 0x5B,
+	HALMAC_API_INIT_OBJ = 0x5C,
+	HALMAC_API_DEINIT_OBJ = 0x5D,
+	HALMAC_API_CFG_LA_MODE = 0x5E,
+	HALMAC_API_GET_HW_VALUE = 0x5F,
+	HALMAC_API_SET_HW_VALUE = 0x60,
+	HALMAC_API_CFG_DRV_RSVD_PG_NUM = 0x61,
+	HALMAC_API_WRITE_EFUSE_BT = 0x63,
+	HALMAC_API_DUMP_EFUSE_MAP_BT = 0x64,
+	HALMAC_API_DL_DRV_RSVD_PG = 0x65,
+	HALMAC_API_PCIE_SWITCH = 0x66,
+	HALMAC_API_PHY_CFG = 0x67,
+	HALMAC_API_CFG_RX_FIFO_EXPANDING_MODE = 0x68,
+	HALMAC_API_CFG_CSI_RATE = 0x69,
+	HALMAC_API_P2PPS = 0x6A,
+	HALMAC_API_CFG_TX_ADDR = 0x6B,
+	HALMAC_API_CFG_NET_TYPE = 0x6C,
+	HALMAC_API_CFG_TSF_RESET = 0x6D,
+	HALMAC_API_CFG_BCN_SPACE = 0x6E,
+	HALMAC_API_CFG_BCN_CTRL = 0x6F,
+	HALMAC_API_CFG_SIDEBAND_INT = 0x70,
+	HALMAC_API_REGISTER_API = 0x71,
+	HALMAC_API_FREE_DOWNLOAD_FIRMWARE = 0x72,
+	HALMAC_API_GET_FW_VERSION = 0x73,
+	HALMAC_API_GET_EFUSE_AVAL_SIZE = 0x74,
+	HALMAC_API_CHK_TXDESC = 0x75,
+	HALMAC_API_SDIO_CMD53_4BYTE = 0x76,
+	HALMAC_API_CFG_TRANS_ADDR = 0x77,
+	HALMAC_API_INTF_INTEGRA_TUNING	= 0x78,
+	HALMAC_API_TXFIFO_IS_EMPTY = 0x79,
+	HALMAC_API_DOWNLOAD_FLASH = 0x7A,
+	HALMAC_API_READ_FLASH = 0x7B,
+	HALMAC_API_ERASE_FLASH = 0x7C,
+	HALMAC_API_CHECK_FLASH = 0x7D,
+	HALMAC_API_SDIO_HW_INFO = 0x80,
+	HALMAC_API_READ_EFUSE_BT = 0x81,
+	HALMAC_API_CFG_EFUSE_AUTO_CHECK = 0x82,
+	HALMAC_API_CFG_PINMUX_GET_FUNC = 0x83,
+	HALMAC_API_CFG_PINMUX_SET_FUNC = 0x84,
+	HALMAC_API_CFG_PINMUX_FREE_FUNC = 0x85,
+	HALMAC_API_CFG_PINMUX_WL_LED_MODE = 0x86,
+	HALMAC_API_CFG_PINMUX_WL_LED_SW_CTRL = 0x87,
+	HALMAC_API_CFG_PINMUX_SDIO_INT_POLARITY = 0x88,
+	HALMAC_API_CFG_PINMUX_GPIO_MODE = 0x89,
+	HALMAC_API_CFG_PINMUX_GPIO_OUTPUT = 0x90,
+	HALMAC_API_REG_READ_INDIRECT_32 = 0x91,
+	HALMAC_API_REG_SDIO_CMD53_READ_N = 0x92,
+	HALMAC_API_PINMUX_PIN_STATUS = 0x94,
+	HALMAC_API_OFLD_FUNC_CFG = 0x95,
+	HALMAC_API_MASK_LOGICAL_EFUSE = 0x96,
+	HALMAC_API_RX_CUT_AMSDU_CFG = 0x97,
+	HALMAC_API_FW_SNDING = 0x98,
+	HALMAC_API_ENTER_CPU_SLEEP_MODE = 0x99,
+	HALMAC_API_GET_CPU_MODE = 0x9A,
+	HALMAC_API_DRV_FWCTRL = 0x9B,
+	HALMAC_API_EN_REF_AUTOK = 0x9C,
+	HALMAC_API_MAX
+};
+
+enum halmac_la_mode {
+	HALMAC_LA_MODE_DISABLE = 0,
+	HALMAC_LA_MODE_PARTIAL = 1,
+	HALMAC_LA_MODE_FULL = 2,
+	HALMAC_LA_MODE_UNDEFINE = 0x7F,
+};
+
+enum halmac_rx_fifo_expanding_mode {
+	HALMAC_RX_FIFO_EXPANDING_MODE_DISABLE = 0,
+	HALMAC_RX_FIFO_EXPANDING_MODE_1_BLOCK = 1,
+	HALMAC_RX_FIFO_EXPANDING_MODE_2_BLOCK = 2,
+	HALMAC_RX_FIFO_EXPANDING_MODE_3_BLOCK = 3,
+	HALMAC_RX_FIFO_EXPANDING_MODE_4_BLOCK = 4,
+	HALMAC_RX_FIFO_EXPANDING_MODE_UNDEFINE = 0x7F,
+};
+
+enum halmac_sdio_cmd53_4byte_mode {
+	HALMAC_SDIO_CMD53_4BYTE_MODE_DISABLE = 0,
+	HALMAC_SDIO_CMD53_4BYTE_MODE_RW = 1,
+	HALMAC_SDIO_CMD53_4BYTE_MODE_R = 2,
+	HALMAC_SDIO_CMD53_4BYTE_MODE_W = 3,
+	HALMAC_SDIO_CMD53_4BYTE_MODE_UNDEFINE = 0x7F,
+};
+
+enum halmac_usb_mode {
+	HALMAC_USB_MODE_U2 = 1,
+	HALMAC_USB_MODE_U3 = 2,
+};
+
+enum halmac_sdio_tx_format {
+	HALMAC_SDIO_AGG_MODE = 1,
+	HALMAC_SDIO_DUMMY_BLOCK_MODE = 2,
+	HALMAC_SDIO_DUMMY_AUTO_MODE = 3,
+};
+
+enum halmac_sdio_clk_monitor {
+	HALMAC_MONITOR_5US = 1,
+	HALMAC_MONITOR_50US = 2,
+	HALMAC_MONITOR_9MS = 3,
+};
+
+enum halmac_hw_id {
+	/* Get HW value */
+	HALMAC_HW_RQPN_MAPPING = 0x00,
+	HALMAC_HW_EFUSE_SIZE = 0x01,
+	HALMAC_HW_EEPROM_SIZE = 0x02,
+	HALMAC_HW_BT_BANK_EFUSE_SIZE = 0x03,
+	HALMAC_HW_BT_BANK1_EFUSE_SIZE = 0x04,
+	HALMAC_HW_BT_BANK2_EFUSE_SIZE = 0x05,
+	HALMAC_HW_TXFIFO_SIZE = 0x06,
+	HALMAC_HW_RXFIFO_SIZE = 0x07,
+	HALMAC_HW_RSVD_PG_BNDY = 0x08,
+	HALMAC_HW_CAM_ENTRY_NUM = 0x09,
+	HALMAC_HW_IC_VERSION = 0x0A,
+	HALMAC_HW_PAGE_SIZE = 0x0B,
+	HALMAC_HW_TX_AGG_ALIGN_SIZE = 0x0C,
+	HALMAC_HW_RX_AGG_ALIGN_SIZE = 0x0D,
+	HALMAC_HW_DRV_INFO_SIZE = 0x0E,
+	HALMAC_HW_TXFF_ALLOCATION = 0x0F,
+	HALMAC_HW_RSVD_EFUSE_SIZE = 0x10,
+	HALMAC_HW_FW_HDR_SIZE = 0x11,
+	HALMAC_HW_TX_DESC_SIZE = 0x12,
+	HALMAC_HW_RX_DESC_SIZE = 0x13,
+	HALMAC_HW_FW_MAX_SIZE = 0x14,
+	HALMAC_HW_ORI_H2C_SIZE = 0x15,
+	HALMAC_HW_RSVD_DRV_PGNUM = 0x16,
+	HALMAC_HW_TX_PAGE_SIZE = 0x17,
+	HALMAC_HW_USB_TXAGG_DESC_NUM = 0x18,
+	HALMAC_HW_WLAN_EFUSE_AVAILABLE_SIZE = 0x19,
+	HALMAC_HW_AC_OQT_SIZE = 0x1C,
+	HALMAC_HW_NON_AC_OQT_SIZE = 0x1D,
+	HALMAC_HW_AC_QUEUE_NUM = 0x1E,
+	HALMAC_HW_RQPN_CH_MAPPING = 0x1F,
+	HALMAC_HW_PWR_STATE = 0x20,
+	HALMAC_HW_SDIO_INT_LAT = 0x21,
+	HALMAC_HW_SDIO_CLK_CNT = 0x22,
+	/* Set HW value */
+	HALMAC_HW_USB_MODE = 0x60,
+	HALMAC_HW_SEQ_EN = 0x61,
+	HALMAC_HW_BANDWIDTH = 0x62,
+	HALMAC_HW_CHANNEL = 0x63,
+	HALMAC_HW_PRI_CHANNEL_IDX = 0x64,
+	HALMAC_HW_EN_BB_RF = 0x65,
+	HALMAC_HW_SDIO_TX_PAGE_THRESHOLD = 0x66,
+	HALMAC_HW_AMPDU_CONFIG = 0x67,
+	HALMAC_HW_RX_SHIFT = 0x68,
+	HALMAC_HW_TXDESC_CHECKSUM = 0x69,
+	HALMAC_HW_RX_CLK_GATE = 0x6A,
+	HALMAC_HW_RXGCK_FIFO = 0x6B,
+	HALMAC_HW_RX_IGNORE = 0x6C,
+	HALMAC_HW_SDIO_TX_FORMAT = 0x6D,
+	HALMAC_HW_FAST_EDCA = 0x6E,
+	HALMAC_HW_LDO25_EN = 0x6F,
+	HALMAC_HW_PCIE_REF_AUTOK = 0x70,
+	HALMAC_HW_RTS_FULL_BW = 0x71,
+	HALMAC_HW_FREE_CNT_EN = 0x72,
+	HALMAC_HW_SDIO_WT_EN = 0x73,
+	HALMAC_HW_SDIO_CLK_MONITOR = 0x74,
+	HALMAC_HW_ID_UNDEFINE = 0x7F,
+};
+
+enum halmac_efuse_bank {
+	HALMAC_EFUSE_BANK_WIFI = 0,
+	HALMAC_EFUSE_BANK_BT = 1,
+	HALMAC_EFUSE_BANK_BT_1 = 2,
+	HALMAC_EFUSE_BANK_BT_2 = 3,
+	HALMAC_EFUSE_BANK_MAX,
+	HALMAC_EFUSE_BANK_UNDEFINE = 0X7F,
+};
+
+enum halmac_sdio_spec_ver {
+	HALMAC_SDIO_SPEC_VER_2_00 = 0,
+	HALMAC_SDIO_SPEC_VER_3_00 = 1,
+	HALMAC_SDIO_SPEC_VER_UNDEFINE = 0X7F,
+};
+
+enum halmac_gpio_func {
+	HALMAC_GPIO_FUNC_WL_LED = 0,
+	HALMAC_GPIO_FUNC_SDIO_INT = 1,
+	HALMAC_GPIO_FUNC_SW_IO_0 = 2,
+	HALMAC_GPIO_FUNC_SW_IO_1 = 3,
+	HALMAC_GPIO_FUNC_SW_IO_2 = 4,
+	HALMAC_GPIO_FUNC_SW_IO_3 = 5,
+	HALMAC_GPIO_FUNC_SW_IO_4 = 6,
+	HALMAC_GPIO_FUNC_SW_IO_5 = 7,
+	HALMAC_GPIO_FUNC_SW_IO_6 = 8,
+	HALMAC_GPIO_FUNC_SW_IO_7 = 9,
+	HALMAC_GPIO_FUNC_SW_IO_8 = 10,
+	HALMAC_GPIO_FUNC_SW_IO_9 = 11,
+	HALMAC_GPIO_FUNC_SW_IO_10 = 12,
+	HALMAC_GPIO_FUNC_SW_IO_11 = 13,
+	HALMAC_GPIO_FUNC_SW_IO_12 = 14,
+	HALMAC_GPIO_FUNC_SW_IO_13 = 15,
+	HALMAC_GPIO_FUNC_SW_IO_14 = 16,
+	HALMAC_GPIO_FUNC_SW_IO_15 = 17,
+	HALMAC_GPIO_FUNC_BT_HOST_WAKE1 = 18,
+	HALMAC_GPIO_FUNC_BT_DEV_WAKE1 = 19,
+	HALMAC_GPIO_FUNC_UNDEFINE = 0X7F,
+};
+
+enum halmac_wlled_mode {
+	HALMAC_WLLED_MODE_TRX = 0,
+	HALMAC_WLLED_MODE_TX = 1,
+	HALMAC_WLLED_MODE_RX = 2,
+	HALMAC_WLLED_MODE_SW_CTRL = 3,
+	HALMAC_WLLED_MODE_UNDEFINE = 0X7F,
+};
+
+enum halmac_psf_fcs_chk_thr {
+	HALMAC_PSF_FCS_CHK_THR_1 = 0,
+	HALMAC_PSF_FCS_CHK_THR_4 = 1,
+	HALMAC_PSF_FCS_CHK_THR_8 = 2,
+	HALMAC_PSF_FCS_CHK_THR_12 = 3,
+	HALMAC_PSF_FCS_CHK_THR_16 = 4,
+	HALMAC_PSF_FCS_CHK_THR_20 = 5,
+	HALMAC_PSF_FCS_CHK_THR_24 = 6,
+	HALMAC_PSF_FCS_CHK_THR_28 = 7,
+};
+
+struct halmac_txff_allocation {
+	u16 tx_fifo_pg_num;
+	u16 rsvd_pg_num;
+	u16 rsvd_drv_pg_num;
+	u16 acq_pg_num;
+	u16 high_queue_pg_num;
+	u16 low_queue_pg_num;
+	u16 normal_queue_pg_num;
+	u16 extra_queue_pg_num;
+	u16 pub_queue_pg_num;
+	u16 rsvd_boundary;
+	u16 rsvd_drv_addr;
+	u16 rsvd_h2c_info_addr;
+	u16 rsvd_h2c_sta_info_addr;
+	u16 rsvd_h2cq_addr;
+	u16 rsvd_cpu_instr_addr;
+	u16 rsvd_fw_txbuf_addr;
+	u16 rsvd_csibuf_addr;
+	enum halmac_la_mode la_mode;
+	enum halmac_rx_fifo_expanding_mode rx_fifo_exp_mode;
+};
+
+struct halmac_rqpn_map {
+	enum halmac_dma_mapping dma_map_vo;
+	enum halmac_dma_mapping dma_map_vi;
+	enum halmac_dma_mapping dma_map_be;
+	enum halmac_dma_mapping dma_map_bk;
+	enum halmac_dma_mapping dma_map_mg;
+	enum halmac_dma_mapping dma_map_hi;
+};
+
+struct halmac_rqpn_ch_map {
+	enum halmac_dma_ch dma_map_vo;
+	enum halmac_dma_ch dma_map_vi;
+	enum halmac_dma_ch dma_map_be;
+	enum halmac_dma_ch dma_map_bk;
+	enum halmac_dma_ch dma_map_mg;
+	enum halmac_dma_ch dma_map_hi;
+};
+
+struct halmac_security_setting {
+	u8 tx_encryption;
+	u8 rx_decryption;
+	u8 bip_enable;
+	u8 compare_keyid;
+};
+
+struct halmac_cam_entry_info {
+	enum hal_security_type security_type;
+	u32 key[4];
+	u32 key_ext[4];
+	u8 mac_address[6];
+	u8 unicast;
+	u8 key_id;
+	u8 valid;
+};
+
+struct halmac_cam_entry_format {
+	u16 key_id : 2;
+	u16 type : 3;
+	u16 mic : 1;
+	u16 grp : 1;
+	u16 spp_mode : 1;
+	u16 rpt_md : 1;
+	u16 ext_sectype : 1;
+	u16 mgnt : 1;
+	u16 rsvd1 : 4;
+	u16 valid : 1;
+	u8 mac_address[6];
+	u32 key[4];
+	u32 rsvd[2];
+};
+
+struct halmac_tx_page_threshold_info {
+	u32	threshold;
+	enum halmac_dma_mapping dma_queue_sel;
+	u8 enable;
+};
+
+struct halmac_ampdu_config {
+	u8 max_agg_num;
+	u8 max_len_en;
+	u32 ht_max_len;
+	u32 vht_max_len;
+};
+
+struct halmac_rqpn {
+	enum halmac_trx_mode mode;
+	enum halmac_dma_mapping dma_map_vo;
+	enum halmac_dma_mapping dma_map_vi;
+	enum halmac_dma_mapping dma_map_be;
+	enum halmac_dma_mapping dma_map_bk;
+	enum halmac_dma_mapping dma_map_mg;
+	enum halmac_dma_mapping dma_map_hi;
+};
+
+struct halmac_ch_mapping {
+	enum halmac_trx_mode mode;
+	enum halmac_dma_ch dma_map_vo;
+	enum halmac_dma_ch dma_map_vi;
+	enum halmac_dma_ch dma_map_be;
+	enum halmac_dma_ch dma_map_bk;
+	enum halmac_dma_ch dma_map_mg;
+	enum halmac_dma_ch dma_map_hi;
+};
+
+struct halmac_pg_num {
+	enum halmac_trx_mode mode;
+	u16 hq_num;
+	u16 nq_num;
+	u16 lq_num;
+	u16 exq_num;
+	u16 gap_num;/*used for loopback mode*/
+};
+
+struct halmac_ch_pg_num {
+	enum halmac_trx_mode mode;
+	u16 ch_num[HALMAC_TXDESC_DMA_CH16 + 1];
+	u16 gap_num;
+};
+
+struct halmac_intf_phy_para {
+	u16 offset;
+	u16 value;
+	u16 ip_sel;
+	u16 cut;
+	u16 plaform;
+};
+
+struct halmac_iqk_para {
+	u8 clear;
+	u8 segment_iqk;
+};
+
+struct halmac_txdesc_ie_param {
+	u8 *start_offset;
+	u8 *end_offset;
+	u8 *ie_offset;
+	u8 *ie_exist;
+};
+
+struct halmac_sdio_hw_info {
+	enum halmac_sdio_spec_ver spec_ver;
+	u32 clock_speed;
+	u8 io_hi_speed_flag; /* Halmac internal use */
+	enum halmac_sdio_tx_format tx_addr_format;
+	u16 block_size;
+	u8 tx_seq;
+	u8 io_indir_flag; /* Halmac internal use */
+};
+
+struct halmac_edca_para {
+	u8 aifs;
+	u8 cw;
+	u16 txop_limit;
+};
+
+struct halmac_mac_rx_ignore_cfg {
+	u8 hdr_chk_en;
+	u8 fcs_chk_en;
+	u8 cck_rst_en;
+	enum halmac_psf_fcs_chk_thr fcs_chk_thr;
+};
+
+struct halmac_rx_ignore_info {
+	u8 hdr_chk_mask;
+	u8 fcs_chk_mask;
+	u8 hdr_chk_en;
+	u8 fcs_chk_en;
+	u8 cck_rst_en;
+	enum halmac_psf_fcs_chk_thr fcs_chk_thr;
+};
+
+struct halmac_pinmux_info {
+	/* byte0 */
+	u8 wl_led:1;
+	u8 sdio_int:1;
+	u8 bt_host_wake:1;
+	u8 bt_dev_wake:1;
+	u8 rsvd1:4;
+	/* byte1 */
+	u8 sw_io_0:1;
+	u8 sw_io_1:1;
+	u8 sw_io_2:1;
+	u8 sw_io_3:1;
+	u8 sw_io_4:1;
+	u8 sw_io_5:1;
+	u8 sw_io_6:1;
+	u8 sw_io_7:1;
+	/* byte2 */
+	u8 sw_io_8:1;
+	u8 sw_io_9:1;
+	u8 sw_io_10:1;
+	u8 sw_io_11:1;
+	u8 sw_io_12:1;
+	u8 sw_io_13:1;
+	u8 sw_io_14:1;
+	u8 sw_io_15:1;
+};
+
+struct halmac_ofld_func_info {
+	u32 halmac_malloc_max_sz;
+	u32 rsvd_pg_drv_buf_max_sz;
+};
+
+struct halmac_pltfm_cfg_info {
+	u32 malloc_size;
+	u32 rsvd_pg_size;
+};
+
+struct halmac_su_snding_info {
+	u8 su0_en;
+	u8 *su0_ndpa_pkt;
+	u32 su0_pkt_sz;
+};
+
+struct halmac_mu_snding_info {
+	u8 tmp;
+};
+
+struct halmac_h2c_info {
+	u32 buf_fs;
+	u32 buf_size;
+	u8 seq_num;
+};
+
+struct halmac_adapter {
+	enum halmac_dma_mapping pq_map[HALMAC_PQ_MAP_NUM];
+	enum halmac_dma_ch ch_map[HALMAC_PQ_MAP_NUM];
+	HALMAC_MUTEX h2c_seq_mutex; /* protect h2c seq num */
+	HALMAC_MUTEX efuse_mutex; /*protect adapter efuse map */
+	HALMAC_MUTEX sdio_indir_mutex; /*protect sdio indirect access */
+	struct halmac_cfg_param_info cfg_param_info;
+	struct halmac_ch_sw_info ch_sw_info;
+	struct halmac_event_trigger evnt;
+	struct halmac_hw_cfg_info hw_cfg_info;
+	struct halmac_sdio_free_space sdio_fs;
+	struct halmac_api_registry api_registry;
+	struct halmac_pinmux_info pinmux_info;
+	struct halmac_pltfm_cfg_info pltfm_info;
+	struct halmac_h2c_info h2c_info;
+	void *drv_adapter;
+	u8 *efuse_map;
+	void *halmac_api;
+	struct halmac_platform_api *pltfm_api;
+	u32 efuse_end;
+	u32 dlfw_pkt_size;
+	enum halmac_chip_id chip_id;
+	enum halmac_chip_ver chip_ver;
+	struct halmac_fw_version fw_ver;
+	struct halmac_state halmac_state;
+	enum halmac_interface intf;
+	enum halmac_trx_mode trx_mode;
+	struct halmac_txff_allocation txff_alloc;
+	u8 efuse_map_valid;
+	u8 efuse_seg_size;
+	u8 rpwm;
+	u8 bulkout_num;
+	u8 drv_info_size;
+	enum halmac_sdio_cmd53_4byte_mode sdio_cmd53_4byte;
+	struct halmac_sdio_hw_info sdio_hw_info;
+	u8 tx_desc_transfer;
+	u8 tx_desc_checksum;
+	u8 efuse_auto_check_en;
+	u8 pcie_refautok_en;
+	u8 pwr_off_flow_flag;
+	struct halmac_rx_ignore_info rx_ignore_info;
+#if HALMAC_PLATFORM_TESTPROGRAM
+	struct halmisc_adapter *halmisc_adapter;
+#endif
+};
+
+struct halmac_api {
+	enum halmac_ret_status
+	(*halmac_register_api)(struct halmac_adapter *adapter,
+			       struct halmac_api_registry *registry);
+	enum halmac_ret_status
+	(*halmac_mac_power_switch)(struct halmac_adapter *adapter,
+				   enum halmac_mac_power pwr);
+	enum halmac_ret_status
+	(*halmac_download_firmware)(struct halmac_adapter *adapter, u8 *fw_bin,
+				    u32 size);
+	enum halmac_ret_status
+	(*halmac_free_download_firmware)(struct halmac_adapter *adapter,
+					 enum halmac_dlfw_mem mem_sel,
+					 u8 *fw_bin, u32 size);
+	enum halmac_ret_status
+	(*halmac_get_fw_version)(struct halmac_adapter *adapter,
+				 struct halmac_fw_version *ver);
+	enum halmac_ret_status
+	(*halmac_cfg_mac_addr)(struct halmac_adapter *adapter,
+			       u8 port, union halmac_wlan_addr *addr);
+	enum halmac_ret_status
+	(*halmac_cfg_bssid)(struct halmac_adapter *adapter, u8 port,
+			    union halmac_wlan_addr *addr);
+	enum halmac_ret_status
+	(*halmac_cfg_multicast_addr)(struct halmac_adapter *adapter,
+				     union halmac_wlan_addr *addr);
+	enum halmac_ret_status
+	(*halmac_pre_init_system_cfg)(struct halmac_adapter *adapter);
+	enum halmac_ret_status
+	(*halmac_init_system_cfg)(struct halmac_adapter *adapter);
+	enum halmac_ret_status
+	(*halmac_init_trx_cfg)(struct halmac_adapter *adapter,
+			       enum halmac_trx_mode mode);
+	enum halmac_ret_status
+	(*halmac_init_h2c)(struct halmac_adapter *adapter);
+	enum halmac_ret_status
+	(*halmac_cfg_rx_aggregation)(struct halmac_adapter *adapter,
+				     struct halmac_rxagg_cfg *cfg);
+	enum halmac_ret_status
+	(*halmac_init_protocol_cfg)(struct halmac_adapter *adapter);
+	enum halmac_ret_status
+	(*halmac_init_edca_cfg)(struct halmac_adapter *adapter);
+	enum halmac_ret_status
+	(*halmac_cfg_operation_mode)(struct halmac_adapter *adapter,
+				     enum halmac_wireless_mode mode);
+	enum halmac_ret_status
+	(*halmac_cfg_ch_bw)(struct halmac_adapter *adapter, u8 ch,
+			    enum halmac_pri_ch_idx idx, enum halmac_bw bw);
+	enum halmac_ret_status
+	(*halmac_cfg_bw)(struct halmac_adapter *adapter, enum halmac_bw bw);
+	enum halmac_ret_status
+	(*halmac_init_wmac_cfg)(struct halmac_adapter *adapter);
+	enum halmac_ret_status
+	(*halmac_init_mac_cfg)(struct halmac_adapter *adapter,
+			       enum halmac_trx_mode mode);
+	enum halmac_ret_status
+	(*halmac_init_interface_cfg)(struct halmac_adapter *adapter);
+	enum halmac_ret_status
+	(*halmac_deinit_interface_cfg)(struct halmac_adapter *adapter);
+	enum halmac_ret_status
+	(*halmac_init_sdio_cfg)(struct halmac_adapter *adapter);
+	enum halmac_ret_status
+	(*halmac_init_usb_cfg)(struct halmac_adapter *adapter);
+	enum halmac_ret_status
+	(*halmac_init_pcie_cfg)(struct halmac_adapter *adapter);
+	enum halmac_ret_status
+	(*halmac_deinit_sdio_cfg)(struct halmac_adapter *adapter);
+	enum halmac_ret_status
+	(*halmac_deinit_usb_cfg)(struct halmac_adapter *adapter);
+	enum halmac_ret_status
+	(*halmac_deinit_pcie_cfg)(struct halmac_adapter *adapter);
+	enum halmac_ret_status
+	(*halmac_get_efuse_size)(struct halmac_adapter *adapter, u32 *size);
+	enum halmac_ret_status
+	(*halmac_get_efuse_available_size)(struct halmac_adapter *adapter,
+					   u32 *size);
+	enum halmac_ret_status
+	(*halmac_dump_efuse_map)(struct halmac_adapter *adapter,
+				 enum halmac_efuse_read_cfg cfg);
+	enum halmac_ret_status
+	(*halmac_dump_efuse_map_bt)(struct halmac_adapter *adapter,
+				    enum halmac_efuse_bank bank, u32 size,
+				    u8 *map);
+	enum halmac_ret_status
+	(*halmac_write_efuse_bt)(struct halmac_adapter *adapter, u32 offset,
+				 u8 value, enum halmac_efuse_bank bank);
+	enum halmac_ret_status
+	(*halmac_read_efuse_bt)(struct halmac_adapter *adapter, u32 offset,
+				u8 *value, enum halmac_efuse_bank bank);
+	enum halmac_ret_status
+	(*halmac_cfg_efuse_auto_check)(struct halmac_adapter *adapter,
+				       u8 enable);
+	enum halmac_ret_status
+	(*halmac_get_logical_efuse_size)(struct halmac_adapter *adapter,
+					 u32 *size);
+	enum halmac_ret_status
+	(*halmac_dump_logical_efuse_map)(struct halmac_adapter *adapter,
+					 enum halmac_efuse_read_cfg cfg);
+	enum halmac_ret_status
+	(*halmac_write_logical_efuse)(struct halmac_adapter *adapter,
+				      u32 offset, u8 value);
+	enum halmac_ret_status
+	(*halmac_read_logical_efuse)(struct halmac_adapter *adapter, u32 offset,
+				     u8 *value);
+	enum halmac_ret_status
+	(*halmac_pg_efuse_by_map)(struct halmac_adapter *adapter,
+				  struct halmac_pg_efuse_info *info,
+				  enum halmac_efuse_read_cfg cfg);
+	enum halmac_ret_status
+	(*halmac_mask_logical_efuse)(struct halmac_adapter *adapter,
+				     struct halmac_pg_efuse_info *info);
+	enum halmac_ret_status
+	(*halmac_get_c2h_info)(struct halmac_adapter *adapter, u8 *buf,
+			       u32 size);
+	enum halmac_ret_status
+	(*halmac_h2c_lb)(struct halmac_adapter *adapter);
+	enum halmac_ret_status
+	(*halmac_debug)(struct halmac_adapter *adapter);
+	enum halmac_ret_status
+	(*halmac_cfg_parameter)(struct halmac_adapter *adapter,
+				struct halmac_phy_parameter_info *info,
+				u8 full_fifo);
+	enum halmac_ret_status
+	(*halmac_update_packet)(struct halmac_adapter *adapter,
+				enum halmac_packet_id pkt_id, u8 *pkt,
+				u32 size);
+	enum halmac_ret_status
+	(*halmac_bcn_ie_filter)(struct halmac_adapter *adapter,
+				struct halmac_bcn_ie_info *info);
+	u8
+	(*halmac_reg_read_8)(struct halmac_adapter *adapter, u32 offset);
+	enum halmac_ret_status
+	(*halmac_reg_write_8)(struct halmac_adapter *adapter, u32 offset,
+			      u8 value);
+	u16
+	(*halmac_reg_read_16)(struct halmac_adapter *adapter, u32 offset);
+	enum halmac_ret_status
+	(*halmac_reg_write_16)(struct halmac_adapter *adapter, u32 offset,
+			       u16 value);
+	u32
+	(*halmac_reg_read_32)(struct halmac_adapter *adapter, u32 offset);
+	enum halmac_ret_status
+	(*halmac_reg_write_32)(struct halmac_adapter *adapter, u32 offset,
+			       u32 value);
+	u32
+	(*halmac_reg_read_indirect_32)(struct halmac_adapter *adapter,
+				       u32 offset);
+	enum halmac_ret_status
+	(*halmac_reg_sdio_cmd53_read_n)(struct halmac_adapter *adapter,
+					u32 offset, u32 size, u8 *value);
+	enum halmac_ret_status
+	(*halmac_tx_allowed_sdio)(struct halmac_adapter *adapter, u8 *buf,
+				  u32 size);
+	enum halmac_ret_status
+	(*halmac_set_bulkout_num)(struct halmac_adapter *adapter, u8 num);
+	enum halmac_ret_status
+	(*halmac_get_sdio_tx_addr)(struct halmac_adapter *adapter, u8 *buf,
+				   u32 size, u32 *cmd53_addr);
+	enum halmac_ret_status
+	(*halmac_get_usb_bulkout_id)(struct halmac_adapter *adapter, u8 *buf,
+				     u32 size, u8 *id);
+	enum halmac_ret_status
+	(*halmac_fill_txdesc_checksum)(struct halmac_adapter *adapter,
+				       u8 *txdesc);
+	enum halmac_ret_status
+	(*halmac_update_datapack)(struct halmac_adapter *adapter,
+				  enum halmac_data_type data_type,
+				  struct halmac_phy_parameter_info *info);
+	enum halmac_ret_status
+	(*halmac_run_datapack)(struct halmac_adapter *adapter,
+			       enum halmac_data_type data_type);
+	enum halmac_ret_status
+	(*halmac_cfg_drv_info)(struct halmac_adapter *adapter,
+			       enum halmac_drv_info drv_info);
+	enum halmac_ret_status
+	(*halmac_send_bt_coex)(struct halmac_adapter *adapter, u8 *buf,
+			       u32 size, u8 ack);
+	enum halmac_ret_status
+	(*halmac_verify_platform_api)(struct halmac_adapter *adapter);
+	u32
+	(*halmac_get_fifo_size)(struct halmac_adapter *adapter,
+				enum hal_fifo_sel sel);
+	enum halmac_ret_status
+	(*halmac_dump_fifo)(struct halmac_adapter *adapter,
+			    enum hal_fifo_sel sel, u32 start_addr, u32 size,
+			    u8 *data);
+	enum halmac_ret_status
+	(*halmac_cfg_txbf)(struct halmac_adapter *adapter, u8 userid,
+			   enum halmac_bw bw, u8 txbf_en);
+	enum halmac_ret_status
+	(*halmac_cfg_mumimo)(struct halmac_adapter *adapter,
+			     struct halmac_cfg_mumimo_para *param);
+	enum halmac_ret_status
+	(*halmac_cfg_sounding)(struct halmac_adapter *adapter,
+			       enum halmac_snd_role role,
+			       enum halmac_data_rate rate);
+	enum halmac_ret_status
+	(*halmac_del_sounding)(struct halmac_adapter *adapter,
+			       enum halmac_snd_role role);
+	enum halmac_ret_status
+	(*halmac_su_bfer_entry_init)(struct halmac_adapter *adapter,
+				     struct halmac_su_bfer_init_para *param);
+	enum halmac_ret_status
+	(*halmac_su_bfee_entry_init)(struct halmac_adapter *adapter, u8 userid,
+				     u16 paid);
+	enum halmac_ret_status
+	(*halmac_mu_bfer_entry_init)(struct halmac_adapter *adapter,
+				     struct halmac_mu_bfer_init_para *param);
+	enum halmac_ret_status
+	(*halmac_mu_bfee_entry_init)(struct halmac_adapter *adapter,
+				     struct halmac_mu_bfee_init_para *param);
+	enum halmac_ret_status
+	(*halmac_su_bfer_entry_del)(struct halmac_adapter *adapter, u8 userid);
+	enum halmac_ret_status
+	(*halmac_su_bfee_entry_del)(struct halmac_adapter *adapter, u8 userid);
+	enum halmac_ret_status
+	(*halmac_mu_bfer_entry_del)(struct halmac_adapter *adapter);
+	enum halmac_ret_status
+	(*halmac_mu_bfee_entry_del)(struct halmac_adapter *adapter, u8 userid);
+	enum halmac_ret_status
+	(*halmac_add_ch_info)(struct halmac_adapter *adapter,
+			      struct halmac_ch_info *info);
+	enum halmac_ret_status
+	(*halmac_add_extra_ch_info)(struct halmac_adapter *adapter,
+				    struct halmac_ch_extra_info *info);
+	enum halmac_ret_status
+	(*halmac_ctrl_ch_switch)(struct halmac_adapter *adapter,
+				 struct halmac_ch_switch_option *opt);
+	enum halmac_ret_status
+	(*halmac_p2pps)(struct halmac_adapter *adapter,
+			struct halmac_p2pps *info);
+	enum halmac_ret_status
+	(*halmac_clear_ch_info)(struct halmac_adapter *adapter);
+	enum halmac_ret_status
+	(*halmac_send_general_info)(struct halmac_adapter *adapter,
+				    struct halmac_general_info *info);
+	enum halmac_ret_status
+	(*halmac_start_iqk)(struct halmac_adapter *adapter,
+			    struct halmac_iqk_para *param);
+	enum halmac_ret_status
+	(*halmac_ctrl_pwr_tracking)(struct halmac_adapter *adapter,
+				    struct halmac_pwr_tracking_option *opt);
+	enum halmac_ret_status
+	(*halmac_psd)(struct halmac_adapter *adapter, u16 start_psd,
+		      u16 end_psd);
+	enum halmac_ret_status
+	(*halmac_cfg_tx_agg_align)(struct halmac_adapter *adapter, u8 enable,
+				   u16 align_size);
+	enum halmac_ret_status
+	(*halmac_query_status)(struct halmac_adapter *adapter,
+			       enum halmac_feature_id feature_id,
+			       enum halmac_cmd_process_status *proc_status,
+			       u8 *data, u32 *size);
+	enum halmac_ret_status
+	(*halmac_reset_feature)(struct halmac_adapter *adapter,
+				enum halmac_feature_id feature_id);
+	enum halmac_ret_status
+	(*halmac_check_fw_status)(struct halmac_adapter *adapter,
+				  u8 *fw_status);
+	enum halmac_ret_status
+	(*halmac_dump_fw_dmem)(struct halmac_adapter *adapter, u8 *dmem,
+			       u32 *size);
+	enum halmac_ret_status
+	(*halmac_cfg_max_dl_size)(struct halmac_adapter *adapter, u32 size);
+	enum halmac_ret_status
+	(*halmac_cfg_la_mode)(struct halmac_adapter *adapter,
+			      enum halmac_la_mode mode);
+	enum halmac_ret_status
+	(*halmac_cfg_rxff_expand_mode)(struct halmac_adapter *adapter,
+				       enum halmac_rx_fifo_expanding_mode mode);
+	enum halmac_ret_status
+	(*halmac_config_security)(struct halmac_adapter *adapter,
+				  struct halmac_security_setting *setting);
+	u8
+	(*halmac_get_used_cam_entry_num)(struct halmac_adapter *adapter,
+					 enum hal_security_type sec_type);
+	enum halmac_ret_status
+	(*halmac_write_cam)(struct halmac_adapter *adapter, u32 idx,
+			    struct halmac_cam_entry_info *info);
+	enum halmac_ret_status
+	(*halmac_read_cam_entry)(struct halmac_adapter *adapter, u32 idx,
+				 struct halmac_cam_entry_format *content);
+	enum halmac_ret_status
+	(*halmac_clear_cam_entry)(struct halmac_adapter *adapter, u32 idx);
+	enum halmac_ret_status
+	(*halmac_get_hw_value)(struct halmac_adapter *adapter,
+			       enum halmac_hw_id hw_id, void *value);
+	enum halmac_ret_status
+	(*halmac_set_hw_value)(struct halmac_adapter *adapter,
+			       enum halmac_hw_id hw_id, void *value);
+	enum halmac_ret_status
+	(*halmac_cfg_drv_rsvd_pg_num)(struct halmac_adapter *adapter,
+				      enum halmac_drv_rsvd_pg_num pg_num);
+	enum halmac_ret_status
+	(*halmac_get_chip_version)(struct halmac_adapter *adapter,
+				   struct halmac_ver *ver);
+	enum halmac_ret_status
+	(*halmac_chk_txdesc)(struct halmac_adapter *adapter, u8 *buf, u32 size);
+	enum halmac_ret_status
+	(*halmac_dl_drv_rsvd_page)(struct halmac_adapter *adapter, u8 pg_offset,
+				   u8 *buf, u32 size);
+	enum halmac_ret_status
+	(*halmac_pcie_switch)(struct halmac_adapter *adapter,
+			      enum halmac_pcie_cfg cfg);
+	enum halmac_ret_status
+	(*halmac_phy_cfg)(struct halmac_adapter *adapter,
+			  enum halmac_intf_phy_platform pltfm);
+	enum halmac_ret_status
+	(*halmac_cfg_csi_rate)(struct halmac_adapter *adapter, u8 rssi,
+			       u8 cur_rate, u8 fixrate_en, u8 *new_rate);
+#if HALMAC_SDIO_SUPPORT
+	enum halmac_ret_status
+	(*halmac_sdio_cmd53_4byte)(struct halmac_adapter *adapter,
+				   enum halmac_sdio_cmd53_4byte_mode mode);
+	enum halmac_ret_status
+	(*halmac_sdio_hw_info)(struct halmac_adapter *adapter,
+			       struct halmac_sdio_hw_info *info);
+#endif
+	enum halmac_ret_status
+	(*halmac_cfg_transmitter_addr)(struct halmac_adapter *adapter, u8 port,
+				       union halmac_wlan_addr *addr);
+	enum halmac_ret_status
+	(*halmac_cfg_net_type)(struct halmac_adapter *adapter, u8 port,
+			       enum halmac_network_type_select net_type);
+	enum halmac_ret_status
+	(*halmac_cfg_tsf_rst)(struct halmac_adapter *adapter, u8 port);
+	enum halmac_ret_status
+	(*halmac_cfg_bcn_space)(struct halmac_adapter *adapter, u8 port,
+				u32 bcn_space);
+	enum halmac_ret_status
+	(*halmac_rw_bcn_ctrl)(struct halmac_adapter *adapter, u8 port,
+			      u8 write_en, struct halmac_bcn_ctrl *ctrl);
+	enum halmac_ret_status
+	(*halmac_interface_integration_tuning)(struct halmac_adapter *adapter);
+	enum halmac_ret_status
+	(*halmac_txfifo_is_empty)(struct halmac_adapter *adapter, u32 chk_num);
+	enum halmac_ret_status
+	(*halmac_download_flash)(struct halmac_adapter *adapter, u8 *fw_bin,
+				 u32 size, u32 rom_addr);
+	enum halmac_ret_status
+	(*halmac_read_flash)(struct halmac_adapter *adapter, u32 addr,
+			     u32 length);
+	enum halmac_ret_status
+	(*halmac_erase_flash)(struct halmac_adapter *adapter, u8 erase_cmd,
+			      u32 addr);
+	enum halmac_ret_status
+	(*halmac_check_flash)(struct halmac_adapter *adapter, u8 *fw_bin,
+			      u32 size, u32 addr);
+	enum halmac_ret_status
+	(*halmac_cfg_edca_para)(struct halmac_adapter *adapter,
+				enum halmac_acq_id acq_id,
+				struct halmac_edca_para *param);
+	enum halmac_ret_status
+	(*halmac_pinmux_get_func)(struct halmac_adapter *adapter,
+				  enum halmac_gpio_func gpio_func, u8 *enable);
+	enum halmac_ret_status
+	(*halmac_pinmux_set_func)(struct halmac_adapter *adapter,
+				  enum halmac_gpio_func gpio_func);
+	enum halmac_ret_status
+	(*halmac_pinmux_free_func)(struct halmac_adapter *adapter,
+				   enum halmac_gpio_func gpio_func);
+	enum halmac_ret_status
+	(*halmac_pinmux_wl_led_mode)(struct halmac_adapter *adapter,
+				     enum halmac_wlled_mode mode);
+	void
+	(*halmac_pinmux_wl_led_sw_ctrl)(struct halmac_adapter *adapter, u8 on);
+	void
+	(*halmac_pinmux_sdio_int_polarity)(struct halmac_adapter *adapter,
+					   u8 low_active);
+	enum halmac_ret_status
+	(*halmac_pinmux_gpio_mode)(struct halmac_adapter *adapter, u8 gpio_id,
+				   u8 output);
+	enum halmac_ret_status
+	(*halmac_pinmux_gpio_output)(struct halmac_adapter *adapter, u8 gpio_id,
+				     u8 high);
+	enum halmac_ret_status
+	(*halmac_pinmux_pin_status)(struct halmac_adapter *adapter, u8 pin_id,
+				    u8 *high);
+	enum halmac_ret_status
+	(*halmac_ofld_func_cfg)(struct halmac_adapter *adapter,
+				struct halmac_ofld_func_info *info);
+	enum halmac_ret_status
+	(*halmac_rx_cut_amsdu_cfg)(struct halmac_adapter *adapter,
+				   struct halmac_cut_amsdu_cfg *cfg);
+	enum halmac_ret_status
+	(*halmac_fw_snding)(struct halmac_adapter *adapter,
+			    struct halmac_su_snding_info *su_info,
+			    struct halmac_mu_snding_info *mu_info, u8 period);
+	enum halmac_ret_status
+	(*halmac_get_mac_addr)(struct halmac_adapter *adapter, u8 port,
+			       union halmac_wlan_addr *addr);
+	enum halmac_ret_status
+	(*halmac_init_low_pwr)(struct halmac_adapter *adapter);
+	enum halmac_ret_status
+	(*halmac_enter_cpu_sleep_mode)(struct halmac_adapter *adapter);
+	enum halmac_ret_status
+	(*halmac_get_cpu_mode)(struct halmac_adapter *adapter,
+			       enum halmac_wlcpu_mode *mode);
+	enum halmac_ret_status
+	(*halmac_drv_fwctrl)(struct halmac_adapter *adapter, u8 *payload,
+			     u32 size, u8 ack);
+	enum halmac_ret_status
+	(*halmac_read_efuse)(struct halmac_adapter *adapter, u32 offset,
+			     u8 *value);
+	enum halmac_ret_status
+	(*halmac_write_efuse)(struct halmac_adapter *adapter, u32 offset,
+			      u8 value);
+#if HALMAC_PCIE_SUPPORT
+	void
+	(*halmac_en_ref_autok_pcie)(struct halmac_adapter *adapter, u8 en);
+#endif
+#if HALMAC_PLATFORM_TESTPROGRAM
+	struct halmisc_api *halmisc_api;
+#endif
+};
+
+#define HALMAC_GET_API(halmac_adapter)                                         \
+	((struct halmac_api *)halmac_adapter->halmac_api)
+
+static HALMAC_INLINE enum halmac_ret_status
+halmac_fw_validate(struct halmac_adapter *adapter)
+{
+	if (adapter->halmac_state.dlfw_state != HALMAC_DLFW_DONE &&
+	    adapter->halmac_state.dlfw_state != HALMAC_GEN_INFO_SENT)
+		return HALMAC_RET_NO_DLFW;
+
+	return HALMAC_RET_SUCCESS;
+}
+
+#endif
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/halmac/halmac_usb_reg.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/halmac/halmac_usb_reg.h
--- linux-5.6.3/3rdparty/rtl8821ce/hal/halmac/halmac_usb_reg.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/halmac/halmac_usb_reg.h	2020-04-10 16:35:06.817660114 +0300
@@ -0,0 +1,19 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ ******************************************************************************/
+
+#ifndef __HALMAC_USB_REG_H__
+#define __HALMAC_USB_REG_H__
+
+#endif/* __HALMAC_USB_REG_H__ */
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/hal_mcc.c linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/hal_mcc.c
--- linux-5.6.3/3rdparty/rtl8821ce/hal/hal_mcc.c	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/hal_mcc.c	2020-04-10 16:35:06.790658854 +0300
@@ -0,0 +1,3488 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2015 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#ifdef CONFIG_MCC_MODE
+#define _HAL_MCC_C_
+
+#include <drv_types.h> /* PADAPTER */
+#include <rtw_mcc.h> /* mcc structure */
+#include <hal_data.h> /* HAL_DATA */
+#include <rtw_pwrctrl.h> /* power control */
+
+/*  use for AP/GO + STA/GC case */
+#define MCC_DURATION_IDX 0 /* druration for station side */
+#define MCC_TSF_SYNC_OFFSET_IDX 1
+#define MCC_START_TIME_OFFSET_IDX 2
+#define MCC_INTERVAL_IDX 3
+#define MCC_GUARD_OFFSET0_IDX 4
+#define MCC_GUARD_OFFSET1_IDX 5
+#define MCC_STOP_THRESHOLD 6
+#define TU 1024 /* 1 TU equals 1024 microseconds */
+/* druration, TSF sync offset, start time offset, interval (unit:TU (1024 microseconds))*/
+u8 mcc_switch_channel_policy_table[][7]={
+	{20, 50, 40, 100, 0, 0, 30},
+	{80, 50, 10, 100, 0, 0, 30},
+	{36, 50, 32, 100, 0, 0, 30},
+	{30, 50, 35, 100, 0, 0, 30},
+};
+
+const int mcc_max_policy_num = sizeof(mcc_switch_channel_policy_table) /sizeof(u8) /7;
+
+static void dump_iqk_val_table(PADAPTER padapter)
+{
+	HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
+	struct hal_iqk_reg_backup *iqk_reg_backup = pHalData->iqk_reg_backup;
+	u8 total_rf_path = pHalData->NumTotalRFPath;
+	u8 rf_path_idx = 0;
+	u8 backup_chan_idx = 0;
+	u8 backup_reg_idx = 0;
+
+#ifdef CONFIG_MCC_MODE_V2
+#else
+
+	RTW_INFO("=============dump IQK backup table================\n");
+	for (backup_chan_idx = 0; backup_chan_idx < MAX_IQK_INFO_BACKUP_CHNL_NUM; backup_chan_idx++) {
+		for (rf_path_idx = 0; rf_path_idx < total_rf_path; rf_path_idx++) {
+			for(backup_reg_idx = 0; backup_reg_idx < MAX_IQK_INFO_BACKUP_REG_NUM; backup_reg_idx++) {
+				RTW_INFO("ch:%d. bw:%d. rf path:%d. reg[%d] = 0x%02x \n"
+						, iqk_reg_backup[backup_chan_idx].central_chnl
+						, iqk_reg_backup[backup_chan_idx].bw_mode
+						, rf_path_idx
+						, backup_reg_idx
+						, iqk_reg_backup[backup_chan_idx].reg_backup[rf_path_idx][backup_reg_idx]
+						);
+			}
+		}
+	}	
+	RTW_INFO("=============================================\n");
+
+#endif
+}
+
+static void rtw_hal_mcc_build_p2p_noa_attr(PADAPTER padapter, u8 *ie, u32 *ie_len)
+{
+	struct mcc_adapter_priv *pmccadapriv = &padapter->mcc_adapterpriv;
+	struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
+	struct mcc_obj_priv *pmccobjpriv = &(dvobj->mcc_objpriv);
+	u8 p2p_noa_attr_ie[MAX_P2P_IE_LEN] = {0x00};
+	u32 p2p_noa_attr_len = 0;
+	u8 noa_desc_num = 1;
+	u8 opp_ps = 0; /* Disable OppPS */
+	u8 noa_count = 255;
+	u32 noa_duration;
+	u32 noa_interval;
+	u8 noa_index = 0;
+	u8 mcc_policy_idx = 0;
+
+	mcc_policy_idx = pmccobjpriv->policy_index;
+	noa_duration = mcc_switch_channel_policy_table[mcc_policy_idx][MCC_DURATION_IDX] * TU;
+	noa_interval = mcc_switch_channel_policy_table[mcc_policy_idx][MCC_INTERVAL_IDX] * TU;
+
+	/* P2P OUI(4 bytes) */
+	_rtw_memcpy(p2p_noa_attr_ie, P2P_OUI, 4);
+	p2p_noa_attr_len = p2p_noa_attr_len + 4;
+
+	/* attrute ID(1 byte) */
+	p2p_noa_attr_ie[p2p_noa_attr_len] = P2P_ATTR_NOA;
+	p2p_noa_attr_len = p2p_noa_attr_len + 1;
+	
+	/* attrute length(2 bytes) length = noa_desc_num*13 + 2 */
+	RTW_PUT_LE16(p2p_noa_attr_ie + p2p_noa_attr_len, (noa_desc_num * 13 + 2));
+	p2p_noa_attr_len = p2p_noa_attr_len + 2;
+
+	/* Index (1 byte) */
+	p2p_noa_attr_ie[p2p_noa_attr_len] = noa_index;
+	p2p_noa_attr_len = p2p_noa_attr_len + 1;
+
+	/* CTWindow and OppPS Parameters (1 byte) */
+	p2p_noa_attr_ie[p2p_noa_attr_len] = opp_ps;
+	p2p_noa_attr_len = p2p_noa_attr_len+ 1;
+
+	/* NoA Count (1 byte) */
+	p2p_noa_attr_ie[p2p_noa_attr_len] = noa_count;
+	p2p_noa_attr_len = p2p_noa_attr_len + 1;
+
+	/* NoA Duration (4 bytes) unit: microseconds */
+	RTW_PUT_LE32(p2p_noa_attr_ie + p2p_noa_attr_len, noa_duration);
+	p2p_noa_attr_len = p2p_noa_attr_len + 4;
+
+	/* NoA Interval (4 bytes) unit: microseconds */
+	RTW_PUT_LE32(p2p_noa_attr_ie + p2p_noa_attr_len, noa_interval);
+	p2p_noa_attr_len = p2p_noa_attr_len + 4;
+
+	/* NoA Start Time (4 bytes) unit: microseconds */
+	RTW_PUT_LE32(p2p_noa_attr_ie + p2p_noa_attr_len, pmccadapriv->noa_start_time);
+	if (0)
+		RTW_INFO("indxe:%d, start_time=0x%02x:0x%02x:0x%02x:0x%02x\n"
+		, noa_index
+		, p2p_noa_attr_ie[p2p_noa_attr_len]
+		, p2p_noa_attr_ie[p2p_noa_attr_len + 1]
+		, p2p_noa_attr_ie[p2p_noa_attr_len + 2]
+		, p2p_noa_attr_ie[p2p_noa_attr_len + 3]);
+
+	p2p_noa_attr_len = p2p_noa_attr_len + 4;
+	rtw_set_ie(ie, _VENDOR_SPECIFIC_IE_, p2p_noa_attr_len, (u8 *)p2p_noa_attr_ie, ie_len);
+}
+
+
+/**
+ * rtw_hal_mcc_update_go_p2p_ie - update go p2p ie(add NoA attribute)
+ * @padapter: the adapter to be update go p2p ie
+ */
+static void rtw_hal_mcc_update_go_p2p_ie(PADAPTER padapter)
+{
+	struct mcc_adapter_priv *pmccadapriv = &padapter->mcc_adapterpriv;
+	struct mcc_obj_priv *mccobjpriv = &(adapter_to_dvobj(padapter)->mcc_objpriv);
+	u8 *pos = NULL;
+
+
+	/* no noa attribute, build it */
+	if (pmccadapriv->p2p_go_noa_ie_len == 0)
+		rtw_hal_mcc_build_p2p_noa_attr(padapter, pmccadapriv->p2p_go_noa_ie, &pmccadapriv->p2p_go_noa_ie_len);
+	else {
+		/* has noa attribut, modify it */
+		u32 noa_duration = 0;
+		
+		/* update index */
+		pos = pmccadapriv->p2p_go_noa_ie + pmccadapriv->p2p_go_noa_ie_len - 15;
+		/* 0~255 */
+		(*pos) = ((*pos) + 1) % 256;
+		if (0)
+			RTW_INFO("indxe:%d\n", (*pos));
+
+
+		/* update duration */
+		noa_duration = mcc_switch_channel_policy_table[mccobjpriv->policy_index][MCC_DURATION_IDX] * TU;
+		pos = pmccadapriv->p2p_go_noa_ie + pmccadapriv->p2p_go_noa_ie_len - 12;
+		RTW_PUT_LE32(pos, noa_duration);
+
+		/* update start time */
+		pos = pmccadapriv->p2p_go_noa_ie + pmccadapriv->p2p_go_noa_ie_len - 4;
+		RTW_PUT_LE32(pos, pmccadapriv->noa_start_time);
+		if (0)
+			RTW_INFO("start_time=0x%02x:0x%02x:0x%02x:0x%02x\n"
+			, ((u8*)(pos))[0]
+			, ((u8*)(pos))[1]
+			, ((u8*)(pos))[2]
+			, ((u8*)(pos))[3]);
+
+	}
+
+	if (0) {
+		RTW_INFO("p2p_go_noa_ie_len:%d\n", pmccadapriv->p2p_go_noa_ie_len);
+		RTW_INFO_DUMP("\n", pmccadapriv->p2p_go_noa_ie, pmccadapriv->p2p_go_noa_ie_len);
+	}
+	update_beacon(padapter, _VENDOR_SPECIFIC_IE_, P2P_OUI, _TRUE);
+}
+
+/**
+ * rtw_hal_mcc_remove_go_p2p_ie - remove go p2p ie(add NoA attribute)
+ * @padapter: the adapter to be update go p2p ie
+ */
+static void rtw_hal_mcc_remove_go_p2p_ie(PADAPTER padapter)
+{
+	struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
+	struct mcc_adapter_priv *pmccadapriv = &padapter->mcc_adapterpriv;
+
+	/* chech has noa ie or not */
+	if (pmccadapriv->p2p_go_noa_ie_len == 0)
+		return;
+
+	pmccadapriv->p2p_go_noa_ie_len = 0;
+	update_beacon(padapter, _VENDOR_SPECIFIC_IE_, P2P_OUI, _TRUE);
+}
+
+/* restore IQK value for all interface */
+void rtw_hal_mcc_restore_iqk_val(PADAPTER padapter)
+{
+	u8 take_care_iqk = _FALSE;
+	struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
+	_adapter *iface = NULL;
+	struct mcc_adapter_priv *mccadapriv = NULL;
+	u8 i = 0;
+
+	rtw_hal_get_hwreg(padapter, HW_VAR_CH_SW_NEED_TO_TAKE_CARE_IQK_INFO, &take_care_iqk);
+	if (take_care_iqk == _TRUE && MCC_EN(padapter)) {
+		for (i = 0; i < dvobj->iface_nums; i++) {
+			iface = dvobj->padapters[i];
+			if (iface == NULL)
+				continue;
+
+			mccadapriv = &iface->mcc_adapterpriv;
+			if (mccadapriv->role == MCC_ROLE_MAX)
+				continue;
+
+			rtw_hal_ch_sw_iqk_info_restore(iface, CH_SW_USE_CASE_MCC);
+		}
+	}
+
+	if (0)
+		dump_iqk_val_table(padapter);
+}
+
+u8 rtw_hal_check_mcc_status(PADAPTER padapter, u8 mcc_status)
+{
+	struct mcc_obj_priv *pmccobjpriv = &(adapter_to_dvobj(padapter)->mcc_objpriv);
+
+	if (pmccobjpriv->mcc_status & (mcc_status))
+		return _TRUE;
+	else
+		return _FALSE;
+}
+
+void rtw_hal_set_mcc_status(PADAPTER padapter, u8 mcc_status)
+{
+	struct mcc_obj_priv *pmccobjpriv = &(adapter_to_dvobj(padapter)->mcc_objpriv);
+
+	pmccobjpriv->mcc_status |= (mcc_status);
+}
+
+void rtw_hal_clear_mcc_status(PADAPTER padapter, u8 mcc_status)
+{
+	struct mcc_obj_priv *pmccobjpriv = &(adapter_to_dvobj(padapter)->mcc_objpriv);
+
+	pmccobjpriv->mcc_status &= (~mcc_status);
+}
+
+static void rtw_hal_mcc_update_policy_table(PADAPTER adapter)
+{
+	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
+	struct mcc_obj_priv *mccobjpriv = &(dvobj->mcc_objpriv);
+	u8 mcc_duration = mccobjpriv->duration;
+	s8 mcc_policy_idx = mccobjpriv->policy_index;
+	u8 interval = mcc_switch_channel_policy_table[mcc_policy_idx][MCC_INTERVAL_IDX];
+	u8 new_mcc_duration_time = 0;
+	u8 new_starttime_offset = 0;
+
+	/* convert % to ms */
+	new_mcc_duration_time = mcc_duration * interval / 100;
+
+	/* start time offset = (interval - duration time)/2 */
+	new_starttime_offset = (interval - new_mcc_duration_time) >> 1;
+
+	/* update modified parameters */
+	mcc_switch_channel_policy_table[mcc_policy_idx][MCC_DURATION_IDX]
+		= new_mcc_duration_time;
+
+	mcc_switch_channel_policy_table[mcc_policy_idx][MCC_START_TIME_OFFSET_IDX]
+		= new_starttime_offset;
+	
+
+}
+
+static void rtw_hal_config_mcc_switch_channel_setting(PADAPTER padapter)
+{
+	struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
+	struct mcc_obj_priv *mccobjpriv = &(dvobj->mcc_objpriv);
+	struct registry_priv *registry_par = &padapter->registrypriv;
+	u8 mcc_duration = 0;
+	s8 mcc_policy_idx = 0;
+
+	mcc_policy_idx = registry_par->rtw_mcc_policy_table_idx;
+	mcc_duration = mccobjpriv->duration;
+
+	if (mcc_policy_idx < 0 || mcc_policy_idx >= mcc_max_policy_num) {
+		mccobjpriv->policy_index = 0;
+		RTW_INFO("[MCC] can't find table(%d), use default policy(%d)\n",
+			mcc_policy_idx, mccobjpriv->policy_index);
+	} else
+		mccobjpriv->policy_index = mcc_policy_idx;
+
+	/* convert % to time */
+	if (mcc_duration != 0)
+		rtw_hal_mcc_update_policy_table(padapter);
+
+	RTW_INFO("[MCC] policy(%d): %d,%d,%d,%d,%d,%d\n"
+		, mccobjpriv->policy_index
+		, mcc_switch_channel_policy_table[mccobjpriv->policy_index][MCC_DURATION_IDX]
+		, mcc_switch_channel_policy_table[mccobjpriv->policy_index][MCC_TSF_SYNC_OFFSET_IDX]
+		, mcc_switch_channel_policy_table[mccobjpriv->policy_index][MCC_START_TIME_OFFSET_IDX]
+		, mcc_switch_channel_policy_table[mccobjpriv->policy_index][MCC_INTERVAL_IDX]
+		, mcc_switch_channel_policy_table[mccobjpriv->policy_index][MCC_GUARD_OFFSET0_IDX]
+		, mcc_switch_channel_policy_table[mccobjpriv->policy_index][MCC_GUARD_OFFSET1_IDX]);
+
+}
+
+static void rtw_hal_mcc_assign_tx_threshold(PADAPTER padapter) 
+{
+	struct registry_priv *preg = &padapter->registrypriv;
+	struct mcc_adapter_priv *pmccadapriv = &padapter->mcc_adapterpriv;
+	struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
+
+	switch (pmccadapriv->role) {
+	case MCC_ROLE_STA:
+	case MCC_ROLE_GC:
+		switch (pmlmeext->cur_bwmode) {
+		case CHANNEL_WIDTH_20:
+			/*
+			* target tx byte(bytes) = target tx tp(Mbits/sec) * 1024 * 1024 / 8 * (duration(ms) / 1024)
+			*					= target tx tp(Mbits/sec) * 128 * duration(ms)
+			* note:
+			* target tx tp(Mbits/sec) * 1024 * 1024 / 8 ==> Mbits to bytes
+			* duration(ms) / 1024 ==> msec to sec
+			*/
+			pmccadapriv->mcc_target_tx_bytes_to_port = preg->rtw_mcc_sta_bw20_target_tx_tp * 128 * pmccadapriv->mcc_duration;
+			break;
+		case CHANNEL_WIDTH_40:
+			pmccadapriv->mcc_target_tx_bytes_to_port = preg->rtw_mcc_sta_bw40_target_tx_tp * 128 * pmccadapriv->mcc_duration;
+			break;
+		case CHANNEL_WIDTH_80:
+			pmccadapriv->mcc_target_tx_bytes_to_port = preg->rtw_mcc_sta_bw80_target_tx_tp * 128 * pmccadapriv->mcc_duration;
+			break;
+		case CHANNEL_WIDTH_160:
+		case CHANNEL_WIDTH_80_80:
+			RTW_INFO(FUNC_ADPT_FMT": not support bwmode = %d\n"
+				, FUNC_ADPT_ARG(padapter), pmlmeext->cur_bwmode);
+			break;
+		}
+		break;
+	case MCC_ROLE_AP:
+	case MCC_ROLE_GO:
+		switch (pmlmeext->cur_bwmode) {
+		case CHANNEL_WIDTH_20:
+			pmccadapriv->mcc_target_tx_bytes_to_port = preg->rtw_mcc_ap_bw20_target_tx_tp * 128 * pmccadapriv->mcc_duration;
+			break;
+		case CHANNEL_WIDTH_40:
+			pmccadapriv->mcc_target_tx_bytes_to_port = preg->rtw_mcc_ap_bw40_target_tx_tp * 128 * pmccadapriv->mcc_duration;
+			break;
+		case CHANNEL_WIDTH_80:
+			pmccadapriv->mcc_target_tx_bytes_to_port = preg->rtw_mcc_ap_bw80_target_tx_tp * 128 * pmccadapriv->mcc_duration;
+			break;
+		case CHANNEL_WIDTH_160:
+		case CHANNEL_WIDTH_80_80:
+			RTW_INFO(FUNC_ADPT_FMT": not support bwmode = %d\n"
+				, FUNC_ADPT_ARG(padapter), pmlmeext->cur_bwmode);
+			break;
+		}
+		break;
+	default:
+		RTW_INFO(FUNC_ADPT_FMT": unknown role = %d\n"
+			, FUNC_ADPT_ARG(padapter), pmccadapriv->role);
+		break;
+	}
+}
+
+static void rtw_hal_config_mcc_role_setting(PADAPTER padapter, u8 order)
+{
+	struct dvobj_priv	*pdvobjpriv = adapter_to_dvobj(padapter);
+	struct mcc_obj_priv *pmccobjpriv = &(pdvobjpriv->mcc_objpriv);
+	struct mcc_adapter_priv *pmccadapriv = &padapter->mcc_adapterpriv;
+	struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
+	struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
+	struct wlan_network *cur_network = &(pmlmepriv->cur_network);
+	struct sta_priv *pstapriv = &padapter->stapriv;
+	struct sta_info *psta = NULL;
+	struct registry_priv *preg = &padapter->registrypriv;
+	_irqL irqL;
+	_list	*phead =NULL, *plist = NULL;
+	u8 policy_index = 0;
+	u8 mcc_duration = 0;
+	u8 mcc_interval = 0;
+	u8 starting_ap_num = DEV_AP_STARTING_NUM(pdvobjpriv);
+	u8 ap_num = DEV_AP_NUM(pdvobjpriv);
+
+	policy_index = pmccobjpriv->policy_index;
+	mcc_duration = mcc_switch_channel_policy_table[pmccobjpriv->policy_index][MCC_DURATION_IDX]
+		- mcc_switch_channel_policy_table[pmccobjpriv->policy_index][MCC_GUARD_OFFSET0_IDX]
+			- mcc_switch_channel_policy_table[pmccobjpriv->policy_index][MCC_GUARD_OFFSET1_IDX];
+	mcc_interval = mcc_switch_channel_policy_table[pmccobjpriv->policy_index][MCC_INTERVAL_IDX];
+
+	if (starting_ap_num == 0 && ap_num == 0) {
+		pmccadapriv->order = order;
+
+		if (pmccadapriv->order == 0) {
+			/* setting is smiliar to GO/AP */
+			/* pmccadapriv->mcc_duration = mcc_interval - mcc_duration;*/
+			pmccadapriv->mgmt_queue_macid = MCC_ROLE_SOFTAP_GO_MGMT_QUEUE_MACID;
+		} else if (pmccadapriv->order == 1) {
+			/* pmccadapriv->mcc_duration = mcc_duration; */
+			pmccadapriv->mgmt_queue_macid = MCC_ROLE_STA_GC_MGMT_QUEUE_MACID;
+		} else {
+			RTW_INFO("[MCC] not support >= 3 interface\n");
+			rtw_warn_on(1);
+		}
+
+		rtw_hal_mcc_assign_tx_threshold(padapter);
+
+		psta = rtw_get_stainfo(pstapriv, cur_network->network.MacAddress);
+		if (psta) {
+			/* combine AP/GO macid and mgmt queue macid to bitmap */
+			pmccadapriv->mcc_macid_bitmap = BIT(psta->cmn.mac_id) | BIT(pmccadapriv->mgmt_queue_macid);
+		} else {
+			RTW_INFO(FUNC_ADPT_FMT":AP/GO station info is NULL\n", FUNC_ADPT_ARG(padapter));
+			rtw_warn_on(1);
+		}
+	} else {
+		/* GO/AP is 1nd order  GC/STA is 2nd order */
+		switch (pmccadapriv->role) {
+		case MCC_ROLE_STA:
+		case MCC_ROLE_GC:
+			pmccadapriv->order = 1;
+			pmccadapriv->mcc_duration = mcc_duration;
+
+			rtw_hal_mcc_assign_tx_threshold(padapter);
+			/* assign used mac to avoid affecting RA */
+			pmccadapriv->mgmt_queue_macid = MCC_ROLE_STA_GC_MGMT_QUEUE_MACID;
+
+			psta = rtw_get_stainfo(pstapriv, cur_network->network.MacAddress);
+			if (psta) {
+				/* combine AP/GO macid and mgmt queue macid to bitmap */
+				pmccadapriv->mcc_macid_bitmap = BIT(psta->cmn.mac_id) | BIT(pmccadapriv->mgmt_queue_macid);
+			} else {
+				RTW_INFO(FUNC_ADPT_FMT":AP/GO station info is NULL\n", FUNC_ADPT_ARG(padapter));
+				rtw_warn_on(1);
+			}
+			break;
+		case MCC_ROLE_AP:
+		case MCC_ROLE_GO:
+			pmccadapriv->order = 0;
+			/* total druation value equals interval */
+			pmccadapriv->mcc_duration = mcc_interval - mcc_duration;
+			pmccadapriv->p2p_go_noa_ie_len = 0; /* not NoA attribute at init time */
+
+			rtw_hal_mcc_assign_tx_threshold(padapter);
+
+			_enter_critical_bh(&pstapriv->asoc_list_lock, &irqL);
+
+			phead = &pstapriv->asoc_list;
+			plist = get_next(phead);
+			pmccadapriv->mcc_macid_bitmap = 0;
+	
+			while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) {
+				psta = LIST_CONTAINOR(plist, struct sta_info, asoc_list);
+				plist = get_next(plist);
+				pmccadapriv->mcc_macid_bitmap |= BIT(psta->cmn.mac_id);
+			}
+
+			_exit_critical_bh(&pstapriv->asoc_list_lock, &irqL);
+
+			psta = rtw_get_bcmc_stainfo(padapter);
+
+			if (psta != NULL)
+				pmccadapriv->mgmt_queue_macid = psta->cmn.mac_id;
+			else {
+				pmccadapriv->mgmt_queue_macid = MCC_ROLE_SOFTAP_GO_MGMT_QUEUE_MACID;
+				RTW_INFO(FUNC_ADPT_FMT":bcmc station is NULL, use macid %d\n"
+					, FUNC_ADPT_ARG(padapter), pmccadapriv->mgmt_queue_macid);
+			}
+
+			/* combine client macid and mgmt queue macid to bitmap */
+			pmccadapriv->mcc_macid_bitmap |= BIT(pmccadapriv->mgmt_queue_macid);
+			break;
+		default:
+			RTW_INFO("Unknown role\n");
+			rtw_warn_on(1);
+			break;
+		}
+
+	}
+
+	/* setting Null data parameters */
+	if (pmccadapriv->role == MCC_ROLE_STA) {
+			pmccadapriv->null_early = 3;
+			pmccadapriv->null_rty_num= 5;
+	} else if (pmccadapriv->role == MCC_ROLE_GC) {
+			pmccadapriv->null_early = 2;
+			pmccadapriv->null_rty_num= 5;
+	} else {
+			pmccadapriv->null_early = 0;
+			pmccadapriv->null_rty_num= 0;
+	}
+
+	RTW_INFO("********* "FUNC_ADPT_FMT" *********\n", FUNC_ADPT_ARG(padapter));
+	RTW_INFO("order:%d\n", pmccadapriv->order);
+	RTW_INFO("role:%d\n", pmccadapriv->role);
+	RTW_INFO("mcc duration:%d\n", pmccadapriv->mcc_duration);
+	RTW_INFO("null_early:%d\n", pmccadapriv->null_early);
+	RTW_INFO("null_rty_num:%d\n", pmccadapriv->null_rty_num);
+	RTW_INFO("mgmt queue macid:%d\n", pmccadapriv->mgmt_queue_macid);
+	RTW_INFO("bitmap:0x%02x\n", pmccadapriv->mcc_macid_bitmap);
+	RTW_INFO("target tx bytes:%d\n", pmccadapriv->mcc_target_tx_bytes_to_port);
+	RTW_INFO("**********************************\n");
+
+	pmccobjpriv->iface[pmccadapriv->order] = padapter;
+
+}
+
+static void rtw_hal_clear_mcc_macid(PADAPTER padapter)
+{
+	u16 media_status_rpt;
+	struct mcc_adapter_priv *pmccadapriv = &padapter->mcc_adapterpriv;
+
+	switch (pmccadapriv->role) {
+	case MCC_ROLE_STA:
+	case MCC_ROLE_GC:
+		break;
+	case MCC_ROLE_AP:
+	case MCC_ROLE_GO:
+	/* nothing to do */
+		break;
+	default:
+		RTW_INFO("Unknown role\n");
+		rtw_warn_on(1);
+		break;
+	}
+}
+
+static void rtw_hal_mcc_rqt_tsf(PADAPTER padapter, u64 *out_tsf)
+{
+	struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
+	struct mcc_obj_priv *mccobjpriv = &(dvobj->mcc_objpriv);
+	PADAPTER order0_iface = NULL;
+	PADAPTER order1_iface = NULL;
+	struct submit_ctx *tsf_req_sctx = NULL;
+	enum _hw_port tsfx = MAX_HW_PORT;
+	enum _hw_port tsfy = MAX_HW_PORT;
+	u8 cmd[H2C_MCC_RQT_TSF_LEN] = {0};
+
+	_enter_critical_mutex(&mccobjpriv->mcc_tsf_req_mutex, NULL);
+
+	order0_iface = mccobjpriv->iface[0];
+	order1_iface = mccobjpriv->iface[1];
+
+	tsf_req_sctx = &mccobjpriv->mcc_tsf_req_sctx;
+	rtw_sctx_init(tsf_req_sctx, MCC_EXPIRE_TIME);
+	mccobjpriv->mcc_tsf_req_sctx_order = 0;
+	tsfx = rtw_hal_get_port(order0_iface);
+	tsfy = rtw_hal_get_port(order1_iface);
+
+	SET_H2CCMD_MCC_RQT_TSFX(cmd, tsfx);
+	SET_H2CCMD_MCC_RQT_TSFY(cmd, tsfy);
+
+	rtw_hal_fill_h2c_cmd(padapter, H2C_MCC_RQT_TSF, H2C_MCC_RQT_TSF_LEN, cmd);
+
+	if (!rtw_sctx_wait(tsf_req_sctx, __func__))
+		RTW_INFO(FUNC_ADPT_FMT": wait for mcc tsf req C2H time out\n", FUNC_ADPT_ARG(padapter));
+
+	if (tsf_req_sctx->status  == RTW_SCTX_DONE_SUCCESS && out_tsf != NULL) {
+		out_tsf[0] = order0_iface->mcc_adapterpriv.tsf;
+		out_tsf[1] = order1_iface->mcc_adapterpriv.tsf;
+	}
+
+
+	_exit_critical_mutex(&mccobjpriv->mcc_tsf_req_mutex, NULL);
+}
+
+static u8 rtw_hal_mcc_check_start_time_is_valid(PADAPTER padapter, u8 case_num,
+	u32 tsfdiff, s8 *upper_bound_0, s8 *lower_bound_0, s8 *upper_bound_1, s8 *lower_bound_1)
+{
+	struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
+	struct mcc_obj_priv *mccobjpriv = &(dvobj->mcc_objpriv);
+	u8 duration_0 = 0, duration_1 = 0;
+	s8 final_upper_bound = 0, final_lower_bound = 0;
+	u8 intersection =  _FALSE;
+	u8 min_start_time = 5;
+	u8 max_start_time = 95;
+	
+	duration_0 = mccobjpriv->iface[0]->mcc_adapterpriv.mcc_duration;
+	duration_1 = mccobjpriv->iface[1]->mcc_adapterpriv.mcc_duration;
+
+	switch(case_num) {
+	case 1:
+		*upper_bound_0 = tsfdiff;
+		*lower_bound_0 = tsfdiff - duration_1;
+		*upper_bound_1 = 150 - duration_1;
+		*lower_bound_1= 0;
+		break;
+	case 2:
+		*upper_bound_0 = tsfdiff + 100;
+		*lower_bound_0 = tsfdiff + 100 - duration_1;
+		*upper_bound_1 = 150 - duration_1;
+		*lower_bound_1= 0;
+		break;
+	case 3:
+		*upper_bound_0 = tsfdiff + 50;
+		*lower_bound_0 = tsfdiff + 50 - duration_1;
+		*upper_bound_1 = 150 - duration_1;
+		*lower_bound_1= 0;
+		break;
+	case 4:
+		*upper_bound_0 = tsfdiff;
+		*lower_bound_0 = tsfdiff - duration_1;
+		*upper_bound_1 = 150 - duration_1;
+		*lower_bound_1= 0;
+		break;
+	case 5:
+		*upper_bound_0 = 200 - tsfdiff;
+		*lower_bound_0 = 200 - tsfdiff - duration_1;
+		*upper_bound_1 = 150 - duration_1;
+		*lower_bound_1= 0;
+		break;
+	case 6:
+		*upper_bound_0 = tsfdiff - 50;
+		*lower_bound_0 = tsfdiff - 50 - duration_1;
+		*upper_bound_1 = 150 - duration_1;
+		*lower_bound_1= 0;
+		break;
+	default:
+		RTW_ERR("[MCC] %s: error case number(%d\n)", __func__, case_num);
+	}
+
+
+	/* check Intersection or not */
+	if ((*lower_bound_1 >= *upper_bound_0) ||
+		(*lower_bound_0 >= *upper_bound_1))
+		intersection = _FALSE;
+	else
+		intersection = _TRUE;
+
+	if (intersection) {
+		if (*upper_bound_0 > *upper_bound_1)
+			final_upper_bound = *upper_bound_1;
+		else
+			final_upper_bound = *upper_bound_0;
+
+		if (*lower_bound_0 > *lower_bound_1)
+			final_lower_bound = *lower_bound_0;
+		else
+			final_lower_bound = *lower_bound_1;
+
+		mccobjpriv->start_time = (final_lower_bound + final_upper_bound) / 2;
+
+		/* check start time less than 5ms, request by Pablo@SD1 */
+		if (mccobjpriv->start_time <= min_start_time) {
+			mccobjpriv->start_time = 6;
+			if (mccobjpriv->start_time < final_lower_bound && mccobjpriv->start_time > final_upper_bound) {
+				intersection = _FALSE;
+				goto exit;
+			}
+		}
+
+		/* check start time less than 95ms */
+		if (mccobjpriv->start_time >= max_start_time) {
+			mccobjpriv->start_time = 90;
+			if (mccobjpriv->start_time < final_lower_bound && mccobjpriv->start_time > final_upper_bound) {
+				intersection = _FALSE;
+				goto exit;
+			}
+		}
+	}
+
+exit:
+	return intersection;
+}
+
+static void rtw_hal_mcc_decide_duration(PADAPTER padapter)
+{
+	struct registry_priv *registry_par = &padapter->registrypriv;
+	struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
+	struct mcc_obj_priv *mccobjpriv = &(dvobj->mcc_objpriv);
+	struct mcc_adapter_priv *mccadapriv = NULL, *mccadapriv_order0 = NULL, *mccadapriv_order1 = NULL;
+	_adapter *iface = NULL, *iface_order0 = NULL,  *iface_order1 = NULL;
+	u8 duration = 0, i = 0, duration_time;
+	u8 mcc_interval = 150;
+
+	iface_order0 = mccobjpriv->iface[0];
+	iface_order1 = mccobjpriv->iface[1];
+	mccadapriv_order0 = &iface_order0->mcc_adapterpriv;
+	mccadapriv_order1 = &iface_order1->mcc_adapterpriv;
+	
+	if (mccobjpriv->duration == 0) {
+		/* default */
+		duration = 30;/*(%)*/
+		RTW_INFO("%s: mccobjpriv->duration=0, use default value(%d)\n",
+			__FUNCTION__, duration);
+	} else {
+		duration = mccobjpriv->duration;/*(%)*/
+		RTW_INFO("%s: mccobjpriv->duration=%d\n",
+			__FUNCTION__, duration);
+	}
+
+	mccobjpriv->interval = mcc_interval;
+	mccobjpriv->mcc_stop_threshold = 2000 * 4 / 300 - 6;
+	/* convert % to ms, for primary adapter */
+	duration_time = mccobjpriv->interval * duration / 100;
+
+	for (i = 0; i < dvobj->iface_nums; i++) {
+		iface = dvobj->padapters[i];
+
+		if (!iface)
+			continue;
+
+		mccadapriv = &iface->mcc_adapterpriv;
+		if (mccadapriv->role == MCC_ROLE_MAX)
+			continue;
+
+		if (is_primary_adapter(iface))
+			mccadapriv->mcc_duration = duration_time;
+		else
+			mccadapriv->mcc_duration = mccobjpriv->interval - duration_time;
+	}
+
+	RTW_INFO("[MCC]"  FUNC_ADPT_FMT " order 0 duration=%d\n", FUNC_ADPT_ARG(iface_order0), mccadapriv_order0->mcc_duration);
+	RTW_INFO("[MCC]"  FUNC_ADPT_FMT " order 1 duration=%d\n", FUNC_ADPT_ARG(iface_order1), mccadapriv_order1->mcc_duration);
+}
+
+static u8 rtw_hal_mcc_update_timing_parameters(PADAPTER padapter, u8 force_update)
+{
+	struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
+	u8 need_update = _FALSE;
+	u8 starting_ap_num = DEV_AP_STARTING_NUM(dvobj);
+	u8 ap_num = DEV_AP_NUM(dvobj);
+
+
+	/* for STA+STA, modify policy table */
+	if (starting_ap_num == 0 && ap_num == 0) {
+		struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
+		struct mcc_obj_priv *pmccobjpriv = &(dvobj->mcc_objpriv);
+		struct mcc_adapter_priv *pmccadapriv = NULL;
+		_adapter *iface = NULL;
+		u64 tsf[MAX_MCC_NUM] = {0};
+		u64 tsf0 = 0, tsf1 = 0;
+		u32 beaconperiod_0 = 0, beaconperiod_1 = 0, tsfdiff = 0;
+		s8 upper_bound_0 = 0, lower_bound_0 = 0;
+		s8 upper_bound_1 = 0, lower_bound_1 = 0;
+		u8 valid = _FALSE;
+		u8 case_num = 1;
+		u8 i = 0;
+		
+		/* query TSF */
+		rtw_hal_mcc_rqt_tsf(padapter, tsf);
+
+		/* selecet policy table according TSF diff */
+		tsf0 = tsf[0];
+		beaconperiod_0 = pmccobjpriv->iface[0]->mlmepriv.cur_network.network.Configuration.BeaconPeriod;
+		tsf0 = rtw_modular64(tsf0, (beaconperiod_0 * TU));
+
+		tsf1 = tsf[1];
+		beaconperiod_1 = pmccobjpriv->iface[1]->mlmepriv.cur_network.network.Configuration.BeaconPeriod;
+		tsf1 = rtw_modular64(tsf1, (beaconperiod_1 * TU));
+
+		if (tsf0 > tsf1)
+			tsfdiff = tsf0- tsf1;
+		else
+			tsfdiff = (tsf0 +  beaconperiod_0 * TU) - tsf1;
+
+		/* convert to ms */
+		tsfdiff = (tsfdiff / TU);
+
+		/* force update*/
+		if (force_update) {
+			RTW_INFO("orig TSF0:%lld, orig TSF1:%lld\n",
+				pmccobjpriv->iface[0]->mcc_adapterpriv.tsf, pmccobjpriv->iface[1]->mcc_adapterpriv.tsf);
+			RTW_INFO("tsf0:%lld, tsf1:%lld\n", tsf0, tsf1);
+			RTW_INFO("%s: force=%d, last_tsfdiff=%d, tsfdiff=%d, THRESHOLD=%d\n",
+				__func__, force_update, pmccobjpriv->last_tsfdiff, tsfdiff, MCC_UPDATE_PARAMETER_THRESHOLD);
+			pmccobjpriv->last_tsfdiff = tsfdiff;
+			need_update = _TRUE;
+		} else {
+			if (pmccobjpriv->last_tsfdiff > tsfdiff) {
+				/* last tsfdiff - current tsfdiff > THRESHOLD, update parameters */
+				if (pmccobjpriv->last_tsfdiff > (tsfdiff + MCC_UPDATE_PARAMETER_THRESHOLD)) {
+					RTW_INFO("orig TSF0:%lld, orig TSF1:%lld\n",
+						pmccobjpriv->iface[0]->mcc_adapterpriv.tsf, pmccobjpriv->iface[1]->mcc_adapterpriv.tsf);
+					RTW_INFO("tsf0:%lld, tsf1:%lld\n", tsf0, tsf1);
+					RTW_INFO("%s: force=%d, last_tsfdiff=%d, tsfdiff=%d, THRESHOLD=%d\n",
+						__func__, force_update, pmccobjpriv->last_tsfdiff, tsfdiff, MCC_UPDATE_PARAMETER_THRESHOLD);
+
+					pmccobjpriv->last_tsfdiff = tsfdiff;
+					need_update = _TRUE;
+				} else {
+					need_update = _FALSE;
+				}
+			} else if (tsfdiff > pmccobjpriv->last_tsfdiff){
+				/* current tsfdiff - last tsfdiff > THRESHOLD, update parameters */
+				if (tsfdiff > (pmccobjpriv->last_tsfdiff + MCC_UPDATE_PARAMETER_THRESHOLD)) {
+					RTW_INFO("orig TSF0:%lld, orig TSF1:%lld\n",
+						pmccobjpriv->iface[0]->mcc_adapterpriv.tsf, pmccobjpriv->iface[1]->mcc_adapterpriv.tsf);
+					RTW_INFO("tsf0:%lld, tsf1:%lld\n", tsf0, tsf1);
+					RTW_INFO("%s: force=%d, last_tsfdiff=%d, tsfdiff=%d, THRESHOLD=%d\n",
+						__func__, force_update, pmccobjpriv->last_tsfdiff, tsfdiff, MCC_UPDATE_PARAMETER_THRESHOLD);
+
+					pmccobjpriv->last_tsfdiff = tsfdiff;
+					need_update = _TRUE;
+				} else {
+					need_update = _FALSE;
+				}
+			} else {
+				need_update = _FALSE;
+			}
+		}
+
+		if (need_update == _FALSE)
+			goto exit;
+
+		rtw_hal_mcc_decide_duration(padapter);
+
+		if (tsfdiff <= 50) {
+	
+			/* RX TBTT 0 */
+			case_num = 1;
+			valid = rtw_hal_mcc_check_start_time_is_valid(padapter, case_num, tsfdiff,
+				&upper_bound_0, &lower_bound_0, &upper_bound_1, &lower_bound_1);
+
+			if (valid)
+				goto valid_result;
+	
+			/* RX TBTT 1 */
+			case_num = 2;
+			valid = rtw_hal_mcc_check_start_time_is_valid(padapter, case_num, tsfdiff,
+				&upper_bound_0, &lower_bound_0, &upper_bound_1, &lower_bound_1);
+
+			if (valid)
+				goto valid_result;
+			
+			/* RX TBTT 2 */
+			case_num = 3;
+			valid = rtw_hal_mcc_check_start_time_is_valid(padapter, case_num, tsfdiff,
+				&upper_bound_0, &lower_bound_0, &upper_bound_1, &lower_bound_1);
+
+			if (valid)
+				goto valid_result;
+
+			if (valid == _FALSE) {
+				RTW_INFO("[MCC] do not find fit start time\n");
+				RTW_INFO("[MCC] tsfdiff:%d, duration:%d(%c), interval:%d\n",
+					tsfdiff, pmccobjpriv->duration, 37, pmccobjpriv->interval);
+
+			}
+
+		} else {
+
+			/* RX TBTT 0 */
+			case_num = 4;
+			valid = rtw_hal_mcc_check_start_time_is_valid(padapter, case_num, tsfdiff,
+				&upper_bound_0, &lower_bound_0, &upper_bound_1, &lower_bound_1);
+
+			if (valid)
+				goto valid_result;
+			
+			
+			/* RX TBTT 1 */
+			case_num = 5;
+			valid = rtw_hal_mcc_check_start_time_is_valid(padapter, case_num, tsfdiff,
+				&upper_bound_0, &lower_bound_0, &upper_bound_1, &lower_bound_1);
+
+			if (valid)
+				goto valid_result;
+
+			
+			/* RX TBTT 2 */
+			case_num = 6;
+			valid = rtw_hal_mcc_check_start_time_is_valid(padapter, case_num, tsfdiff,
+				&upper_bound_0, &lower_bound_0, &upper_bound_1, &lower_bound_1);
+
+			if (valid)
+				goto valid_result;
+
+			if (valid == _FALSE) {
+				RTW_INFO("[MCC] do not find fit start time\n");
+				RTW_INFO("[MCC] tsfdiff:%d, duration:%d(%c), interval:%d\n",
+					tsfdiff, pmccobjpriv->duration, 37, pmccobjpriv->interval);
+			}
+		}
+
+		
+
+	valid_result:
+		RTW_INFO("********************\n");
+		RTW_INFO("%s: case_num:%d, start time:%d\n",
+				__func__, case_num, pmccobjpriv->start_time);
+		RTW_INFO("%s: upper_bound_0:%d, lower_bound_0:%d\n",
+				__func__, upper_bound_0, lower_bound_0);
+		RTW_INFO("%s: upper_bound_1:%d, lower_bound_1:%d\n",
+				__func__, upper_bound_1, lower_bound_1);
+		
+		for (i = 0; i < dvobj->iface_nums; i++) {
+			iface = dvobj->padapters[i];
+			if (iface == NULL)
+				continue;
+
+			pmccadapriv = &iface->mcc_adapterpriv;
+			pmccadapriv = &iface->mcc_adapterpriv;
+			if (pmccadapriv->role == MCC_ROLE_MAX)
+				continue;
+#if 0
+			if (pmccadapriv->order == 0) {
+				pmccadapriv->mcc_duration = mcc_duration;
+			} else if (pmccadapriv->order == 1) {
+				pmccadapriv->mcc_duration = mcc_interval - mcc_duration;
+			} else {
+				RTW_INFO("[MCC] not support >= 3 interface\n");
+				rtw_warn_on(1);
+			}
+#endif
+			RTW_INFO("********************\n");
+			RTW_INFO(FUNC_ADPT_FMT": order:%d, role:%d\n",
+				FUNC_ADPT_ARG(iface), pmccadapriv->order, pmccadapriv->role);
+			RTW_INFO(FUNC_ADPT_FMT": mcc duration:%d, target tx bytes:%d\n",
+				FUNC_ADPT_ARG(iface), pmccadapriv->mcc_duration, pmccadapriv->mcc_target_tx_bytes_to_port);
+			RTW_INFO(FUNC_ADPT_FMT": mgmt queue macid:%d, bitmap:0x%02x\n",
+				FUNC_ADPT_ARG(iface), pmccadapriv->mgmt_queue_macid, pmccadapriv->mcc_macid_bitmap);
+			RTW_INFO("********************\n");
+		}
+		
+	}
+exit:
+	return need_update;
+}
+
+static u8 rtw_hal_decide_mcc_role(PADAPTER padapter)
+{
+	struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
+	_adapter *iface = NULL;
+	struct mcc_adapter_priv *pmccadapriv = NULL;
+	struct wifidirect_info *pwdinfo = NULL;
+	struct mlme_priv *pmlmepriv = NULL;
+	u8 ret = _SUCCESS, i = 0;
+	u8 order = 1;
+
+	for (i = 0; i < dvobj->iface_nums; i++) {
+		iface = dvobj->padapters[i];
+		if (iface == NULL)
+			continue;
+
+		pmccadapriv = &iface->mcc_adapterpriv;
+		pwdinfo = &iface->wdinfo;
+
+		if (MLME_IS_GO(iface))
+			pmccadapriv->role = MCC_ROLE_GO;
+		else if (MLME_IS_AP(iface))
+			pmccadapriv->role = MCC_ROLE_AP;
+		else if (MLME_IS_GC(iface))
+			pmccadapriv->role = MCC_ROLE_GC;
+		else if (MLME_IS_STA(iface)) {
+			if (MLME_IS_LINKING(iface) || MLME_IS_ASOC(iface))
+				pmccadapriv->role = MCC_ROLE_STA;
+			else {
+				/* bypass non-linked/non-linking interface */
+				RTW_INFO(FUNC_ADPT_FMT" mlme state:0x%2x\n",
+					FUNC_ADPT_ARG(iface), MLME_STATE(iface));
+				continue;
+			}
+		} else {
+			/* bypass non-linked/non-linking interface */
+			RTW_INFO(FUNC_ADPT_FMT" P2P Role:%d, mlme state:0x%2x\n",
+				FUNC_ADPT_ARG(iface), pwdinfo->role, MLME_STATE(iface));
+			continue;
+		}
+
+		if (padapter == iface) {
+			/* current adapter is order 0 */
+			rtw_hal_config_mcc_role_setting(iface, 0);
+		} else {
+			rtw_hal_config_mcc_role_setting(iface, order);
+			order ++;
+		}
+	}
+
+	rtw_hal_mcc_update_timing_parameters(padapter, _TRUE);
+exit:
+	return ret;
+}
+
+static void rtw_hal_construct_CTS(PADAPTER padapter, u8 *pframe, u32 *pLength)
+{
+	u8 broadcast_addr[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
+
+	/* frame type, length = 1*/
+	set_frame_sub_type(pframe, WIFI_RTS);
+
+	/* frame control flag, length = 1 */
+	*(pframe + 1) = 0;
+
+	/* frame duration, length = 2 */
+	*(pframe + 2) = 0x00;
+	*(pframe + 3) = 0x78;
+
+	/* frame recvaddr, length = 6 */
+	_rtw_memcpy((pframe + 4), broadcast_addr, ETH_ALEN);
+	_rtw_memcpy((pframe + 4 + ETH_ALEN), adapter_mac_addr(padapter), ETH_ALEN);
+	_rtw_memcpy((pframe + 4 + ETH_ALEN*2), adapter_mac_addr(padapter), ETH_ALEN);
+	*pLength = 22;
+}
+
+/* avoid wrong information for power limit */
+void rtw_hal_mcc_upadate_chnl_bw(_adapter *padapter, u8 ch, u8 ch_offset, u8 bw, u8 print)
+{
+
+	u8 center_ch, chnl_offset80 = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
+	struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
+	PHAL_DATA_TYPE	hal = GET_HAL_DATA(padapter);
+	u8 cch_160, cch_80, cch_40, cch_20;
+
+	center_ch = rtw_get_center_ch(ch, bw, ch_offset);
+
+	if (bw == CHANNEL_WIDTH_80) {
+		if (center_ch > ch)
+			chnl_offset80 = HAL_PRIME_CHNL_OFFSET_LOWER;
+		else if (center_ch < ch)
+			chnl_offset80 = HAL_PRIME_CHNL_OFFSET_UPPER;
+		else
+			chnl_offset80 = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
+	}
+
+	/* set Channel */
+	/* saved channel/bw info */
+	rtw_set_oper_ch(padapter, ch);
+	rtw_set_oper_bw(padapter, bw);
+	rtw_set_oper_choffset(padapter, ch_offset);
+
+	cch_80 = bw == CHANNEL_WIDTH_80 ? center_ch : 0;
+	cch_40 = bw == CHANNEL_WIDTH_40 ? center_ch : 0;
+	cch_20 = bw == CHANNEL_WIDTH_20 ? center_ch : 0;
+
+	if (cch_80 != 0)
+		cch_40 = rtw_get_scch_by_cch_offset(cch_80, CHANNEL_WIDTH_80, chnl_offset80);
+	if (cch_40 != 0)
+		cch_20 = rtw_get_scch_by_cch_offset(cch_40, CHANNEL_WIDTH_40, ch_offset);
+
+
+	hal->cch_80 = cch_80;
+	hal->cch_40 = cch_40;
+	hal->cch_20 = cch_20;
+	hal->current_channel = center_ch;
+	hal->CurrentCenterFrequencyIndex1 = center_ch;
+	hal->current_channel_bw = bw;
+	hal->nCur40MhzPrimeSC = ch_offset;
+	hal->nCur80MhzPrimeSC = chnl_offset80;
+	hal->current_band_type = ch > 14 ? BAND_ON_5G:BAND_ON_2_4G;
+
+	if (print) {
+		RTW_INFO(FUNC_ADPT_FMT" cch:%u, %s, offset40:%u, offset80:%u (%u, %u, %u), band:%s\n"
+			, FUNC_ADPT_ARG(padapter), center_ch, ch_width_str(bw)
+			, ch_offset, chnl_offset80
+			, hal->cch_80, hal->cch_40, hal->cch_20
+			, band_str(hal->current_band_type));
+	}
+}
+
+#ifdef DBG_RSVD_PAGE_CFG
+#define RSVD_PAGE_CFG(ops, v1, v2, v3)	\
+	RTW_INFO("=== [RSVD][%s]-NeedPage:%d, TotalPageNum:%d TotalPacketLen:%d ===\n",	\
+		ops, v1, v2, v3)
+#endif
+
+u8 rtw_hal_dl_mcc_fw_rsvd_page(_adapter *adapter, u8 *pframe, u16 *index,
+	u8 tx_desc, u32 page_size, u8 *total_page_num, RSVDPAGE_LOC *rsvd_page_loc, u8 *page_num)
+{
+	u32 len = 0;
+	_adapter *iface = NULL;
+	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
+	struct mcc_obj_priv *pmccobjpriv = &(dvobj->mcc_objpriv);
+	struct mlme_ext_info *pmlmeinfo = NULL;
+	struct mlme_ext_priv *pmlmeext = NULL;
+	struct hal_com_data *hal = GET_HAL_DATA(adapter);
+	struct mcc_adapter_priv *mccadapriv = NULL;
+	u8 ret = _SUCCESS, i = 0, j  =0, order = 0, CurtPktPageNum = 0;
+	u8 *start = NULL;
+	u8 path = RF_PATH_A;
+
+	if (page_num) {
+#ifdef CONFIG_MCC_MODE_V2
+		if (!hal->RegIQKFWOffload)
+			RTW_WARN("[MCC] must enable FW IQK for New IC\n");
+#endif /* CONFIG_MCC_MODE_V2 */
+		/* Null data(interface number) + power index(interface number) + 1  */
+		*total_page_num += (2 * dvobj->iface_nums + 3);
+		goto exit;
+	}
+
+	/* check proccess mcc start setting */
+	if (!rtw_hal_check_mcc_status(adapter, MCC_STATUS_PROCESS_MCC_START_SETTING)) {
+		ret = _FAIL;
+		goto exit;
+	}
+
+	for (i = 0; i < dvobj->iface_nums; i++) {
+		iface = dvobj->padapters[i];
+		if (iface == NULL)
+			continue;
+
+		mccadapriv = &iface->mcc_adapterpriv;
+		if (mccadapriv->role == MCC_ROLE_MAX)
+			continue;
+
+		order = mccadapriv->order;
+		pmccobjpriv->mcc_loc_rsvd_paga[order] = *total_page_num;
+
+		switch (mccadapriv->role) {
+		case MCC_ROLE_STA:
+		case MCC_ROLE_GC:
+			/* Build NULL DATA */
+			RTW_INFO("LocNull(order:%d): %d\n"
+				, order, pmccobjpriv->mcc_loc_rsvd_paga[order]);
+			len = 0;
+
+			rtw_hal_construct_NullFunctionData(iface
+				, &pframe[*index], &len, _FALSE, 0, 0, _FALSE);
+			rtw_hal_fill_fake_txdesc(iface, &pframe[*index-tx_desc],
+				len, _FALSE, _FALSE, _FALSE);
+
+			CurtPktPageNum = (u8)PageNum(tx_desc + len, page_size);
+			*total_page_num += CurtPktPageNum;
+			*index += (CurtPktPageNum * page_size);
+			#ifdef DBG_RSVD_PAGE_CFG
+			RSVD_PAGE_CFG("LocNull", CurtPktPageNum, *total_page_num, *index);
+			#endif
+			break;
+		case MCC_ROLE_AP:
+			/* Bulid CTS */
+			RTW_INFO("LocCTS(order:%d): %d\n"
+				, order, pmccobjpriv->mcc_loc_rsvd_paga[order]);
+
+			len = 0;
+			rtw_hal_construct_CTS(iface, &pframe[*index], &len);
+			rtw_hal_fill_fake_txdesc(iface, &pframe[*index-tx_desc],
+				len, _FALSE, _FALSE, _FALSE);
+
+			CurtPktPageNum = (u8)PageNum(tx_desc + len, page_size);
+			*total_page_num += CurtPktPageNum;
+			*index += (CurtPktPageNum * page_size);
+			#ifdef DBG_RSVD_PAGE_CFG
+			RSVD_PAGE_CFG("LocCTS", CurtPktPageNum, *total_page_num, *index);
+			#endif
+			break;
+		case MCC_ROLE_GO:
+		/* To DO */
+			break;
+		default:
+			RTW_INFO(FUNC_ADPT_FMT": unknown role = %d\n"
+				, FUNC_ADPT_ARG(iface), mccadapriv->role);
+			break;
+		}
+	}
+
+	for (i = 0; i < MAX_MCC_NUM; i++) {
+		u8 center_ch = 0, ch = 0, bw = 0, bw_offset = 0;
+		u8 power_index = 0;
+		u8 rate_array_sz = 0;
+		u8 *rates = NULL;
+		u8 rate = 0;
+		u8 shift = 0;
+		u32 power_index_4bytes = 0;
+		u8 total_rate = 0;
+		u8 *total_rate_offset = NULL;
+
+		iface = pmccobjpriv->iface[i];
+		pmlmeext = &iface->mlmeextpriv;
+		ch = pmlmeext->cur_channel;
+		bw = pmlmeext->cur_bwmode;
+		bw_offset = pmlmeext->cur_ch_offset;
+		center_ch = rtw_get_center_ch(ch, bw, bw_offset);
+		rtw_hal_mcc_upadate_chnl_bw(iface, ch, bw_offset, bw, _TRUE);
+
+		start = &pframe[*index - tx_desc];
+		_rtw_memset(start, 0, page_size);
+		pmccobjpriv->mcc_pwr_idx_rsvd_page[i] = *total_page_num;
+		RTW_INFO(ADPT_FMT" order:%d, pwr_idx_rsvd_page location[%d]: %d\n",
+			ADPT_ARG(iface), mccadapriv->order,
+			i, pmccobjpriv->mcc_pwr_idx_rsvd_page[i]);
+
+		total_rate_offset = start;
+			
+		for (path = RF_PATH_A; path < hal->NumTotalRFPath; ++path) {
+			total_rate = 0;
+			/* PATH A for 0~63 byte, PATH B for 64~127 byte*/
+			if (path == RF_PATH_A)
+				start = total_rate_offset + 1;
+			else if (path == RF_PATH_B)
+				start = total_rate_offset + 64;
+			else {
+				RTW_INFO("[MCC] %s: unknow RF PATH(%d)\n", __func__, path);
+				break;
+			}
+
+			/* CCK */
+			if (ch <= 14) {
+				rate_array_sz = rates_by_sections[CCK].rate_num;
+				rates = rates_by_sections[CCK].rates;
+				for (j = 0; j < rate_array_sz; ++j) {
+					power_index = rtw_hal_get_tx_power_index(iface, path, rates[j], bw, center_ch, NULL);
+					rate = PHY_GetRateIndexOfTxPowerByRate(rates[j]);
+
+					shift = rate % 4;
+					if (shift == 0) {
+						*start = rate;
+						start++;
+						total_rate++;
+
+						#ifdef DBG_PWR_IDX_RSVD_PAGE
+						RTW_INFO("TXPWR("ADPT_FMT"): [%c][%s]ch:%u, %s, pwr_idx:%u\n",
+							ADPT_ARG(iface), rf_path_char(path), ch_width_str(bw),
+							center_ch, MGN_RATE_STR(rates[j]), power_index);
+						#endif
+					}
+
+					*start = power_index;
+					start++;
+
+					#ifdef DBG_PWR_IDX_RSVD_PAGE
+					RTW_INFO("TXPWR("ADPT_FMT"): [%c][%s]ch:%u, %s, pwr_idx:%u\n",
+						ADPT_ARG(iface), rf_path_char(path), ch_width_str(bw),
+						center_ch, MGN_RATE_STR(rates[j]), power_index);
+
+					
+					shift = rate % 4;
+					power_index_4bytes |= ((power_index & 0xff) << (shift * 8));
+					if (shift == 3) {
+						rate = rate - 3;
+						RTW_INFO("(index:0x%02x, rfpath:%d, rate:0x%02x)\n", index, path, rate);
+						power_index_4bytes = 0;
+						total_rate++;
+					}
+					#endif
+						
+				}
+			}
+
+			/* OFDM */
+			rate_array_sz = rates_by_sections[OFDM].rate_num;
+			rates = rates_by_sections[OFDM].rates;
+			for (j = 0; j < rate_array_sz; ++j) {
+				power_index = rtw_hal_get_tx_power_index(iface, path, rates[j], bw, center_ch, NULL);
+				rate = PHY_GetRateIndexOfTxPowerByRate(rates[j]);
+
+				shift = rate % 4;
+				if (shift == 0) {
+					*start = rate;
+					start++;
+					total_rate++;
+
+					#ifdef DBG_PWR_IDX_RSVD_PAGE
+					RTW_INFO("TXPWR("ADPT_FMT"): [%c][%s]ch:%u, %s, pwr_idx:%u\n",
+						ADPT_ARG(iface), rf_path_char(path), ch_width_str(bw),
+						center_ch, MGN_RATE_STR(rates[j]), power_index);
+					#endif
+
+				}
+
+				*start = power_index;
+				start++;
+
+				#ifdef DBG_PWR_IDX_RSVD_PAGE
+				RTW_INFO("TXPWR("ADPT_FMT"): [%c][%s]ch:%u, %s, pwr_idx:%u\n",
+					ADPT_ARG(iface), rf_path_char(path), ch_width_str(bw),
+					center_ch, MGN_RATE_STR(rates[j]), power_index);
+
+				shift = rate % 4;
+				power_index_4bytes |= ((power_index & 0xff) << (shift * 8));
+				if (shift == 3) {
+					rate = rate - 3;
+					RTW_INFO("(index:0x%02x, rfpath:%d, rate:0x%02x)\n", index, path, rate);
+					power_index_4bytes = 0;
+					total_rate++;
+				}
+				#endif
+			}
+
+			/* HT_MCS0_MCS7 */
+			rate_array_sz = rates_by_sections[HT_MCS0_MCS7].rate_num;
+			rates = rates_by_sections[HT_MCS0_MCS7].rates;
+			for (j = 0; j < rate_array_sz; ++j) {
+				power_index = rtw_hal_get_tx_power_index(iface, path, rates[j], bw, center_ch, NULL);
+				rate = PHY_GetRateIndexOfTxPowerByRate(rates[j]);
+
+				shift = rate % 4;
+				if (shift == 0) {
+					*start = rate;
+					start++;
+					total_rate++;
+
+					#ifdef DBG_PWR_IDX_RSVD_PAGE
+					RTW_INFO("TXPWR("ADPT_FMT"): [%c][%s]ch:%u, %s, pwr_idx:%u\n",
+						ADPT_ARG(iface), rf_path_char(path), ch_width_str(bw),
+						center_ch, MGN_RATE_STR(rates[j]), power_index);
+					#endif
+
+				}
+
+				*start = power_index;
+				start++;
+
+				#ifdef DBG_PWR_IDX_RSVD_PAGE
+				RTW_INFO("TXPWR("ADPT_FMT"): [%c][%s]ch:%u, %s, pwr_idx:%u\n",
+					ADPT_ARG(iface), rf_path_char(path), ch_width_str(bw),
+					center_ch, MGN_RATE_STR(rates[j]), power_index);
+
+				shift = rate % 4;
+				power_index_4bytes |= ((power_index & 0xff) << (shift * 8));
+				if (shift == 3) {
+					rate = rate - 3;
+					RTW_INFO("(index:0x%02x, rfpath:%d, rate:0x%02x)\n", index, path, rate);
+					power_index_4bytes = 0;
+					total_rate++;
+				}
+				#endif
+			}
+
+			/* HT_MCS8_MCS15 */
+			rate_array_sz = rates_by_sections[HT_MCS8_MCS15].rate_num;
+			rates = rates_by_sections[HT_MCS8_MCS15].rates;
+			for (j = 0; j < rate_array_sz; ++j) {
+				power_index = rtw_hal_get_tx_power_index(iface, path, rates[j], bw, center_ch, NULL);
+				rate = PHY_GetRateIndexOfTxPowerByRate(rates[j]);
+
+				shift = rate % 4;
+				if (shift == 0) {
+					*start = rate;
+					start++;
+					total_rate++;
+
+					#ifdef DBG_PWR_IDX_RSVD_PAGE
+					RTW_INFO("TXPWR("ADPT_FMT"): [%c][%s]ch:%u, %s, pwr_idx:%u\n",
+						ADPT_ARG(iface), rf_path_char(path), ch_width_str(bw),
+						center_ch, MGN_RATE_STR(rates[j]), power_index);
+					#endif
+				}
+
+				*start = power_index;
+				start++;
+
+				#ifdef DBG_PWR_IDX_RSVD_PAGE
+				RTW_INFO("TXPWR("ADPT_FMT"): [%c][%s]ch:%u, %s, pwr_idx:%u\n",
+					ADPT_ARG(iface), rf_path_char(path), ch_width_str(bw),
+					center_ch, MGN_RATE_STR(rates[j]), power_index);
+				
+				shift = rate % 4;
+				power_index_4bytes |= ((power_index & 0xff) << (shift * 8));
+				if (shift == 3) {
+					rate = rate - 3;
+					RTW_INFO("(index:0x%02x, rfpath:%d, rate:0x%02x)\n", index, path, rate);
+					power_index_4bytes = 0;
+					total_rate++;
+				}
+				#endif
+			}
+
+			/* VHT_1SSMCS0_1SSMCS9 */
+			rate_array_sz = rates_by_sections[VHT_1SSMCS0_1SSMCS9].rate_num;
+			rates = rates_by_sections[VHT_1SSMCS0_1SSMCS9].rates;
+			for (j = 0; j < rate_array_sz; ++j) {
+				power_index = rtw_hal_get_tx_power_index(iface, path, rates[j], bw, center_ch, NULL);
+				rate = PHY_GetRateIndexOfTxPowerByRate(rates[j]);
+
+				shift = rate % 4;
+				if (shift == 0) {
+					*start = rate;
+					start++;
+					total_rate++;
+					#ifdef DBG_PWR_IDX_RSVD_PAGE
+					RTW_INFO("TXPWR("ADPT_FMT"): [%c][%s]ch:%u, %s, pwr_idx:0x%02x\n",
+						ADPT_ARG(iface), rf_path_char(path), ch_width_str(bw),
+						center_ch, MGN_RATE_STR(rates[j]), power_index);
+					#endif
+				}
+				*start = power_index;
+				start++;
+				#ifdef DBG_PWR_IDX_RSVD_PAGE
+				RTW_INFO("TXPWR("ADPT_FMT"): [%c][%s]ch:%u, %s, pwr_idx:%u\n",
+					ADPT_ARG(iface), rf_path_char(path), ch_width_str(bw),
+					center_ch, MGN_RATE_STR(rates[j]), power_index);
+
+				shift = rate % 4;
+				power_index_4bytes |= ((power_index & 0xff) << (shift * 8));
+				if (shift == 3) {
+					rate = rate - 3;
+					RTW_INFO("(index:0x%02x, rfpath:%d, rate:0x%02x)\n", index, path, rate);
+					power_index_4bytes = 0;
+					total_rate++;
+				}
+				#endif
+			}
+
+			/* VHT_2SSMCS0_2SSMCS9 */
+			rate_array_sz = rates_by_sections[VHT_2SSMCS0_2SSMCS9].rate_num;
+			rates = rates_by_sections[VHT_2SSMCS0_2SSMCS9].rates;
+			for (j = 0; j < rate_array_sz; ++j) {
+				power_index = rtw_hal_get_tx_power_index(iface, path, rates[j], bw, center_ch, NULL);
+				rate = PHY_GetRateIndexOfTxPowerByRate(rates[j]);
+
+				shift = rate % 4;
+				if (shift == 0) {
+					*start = rate;
+					start++;
+					total_rate++;
+					#ifdef DBG_PWR_IDX_RSVD_PAGE
+					RTW_INFO("TXPWR("ADPT_FMT"): [%c][%s]ch:%u, %s, pwr_idx:%u\n",
+						ADPT_ARG(iface), rf_path_char(path), ch_width_str(bw),
+						center_ch, MGN_RATE_STR(rates[j]), power_index);
+					#endif
+				}
+				*start = power_index;
+				start++;
+				#ifdef DBG_PWR_IDX_RSVD_PAGE
+				RTW_INFO("TXPWR("ADPT_FMT"): [%c][%s]ch:%u, %s, pwr_idx:%u\n",
+					ADPT_ARG(iface), rf_path_char(path), ch_width_str(bw),
+					center_ch, MGN_RATE_STR(rates[j]), power_index);
+
+				shift = rate % 4;
+				power_index_4bytes |= ((power_index & 0xff) << (shift * 8));
+				if (shift == 3) {
+					rate = rate - 3;
+					RTW_INFO("(index:0x%02x, rfpath:%d, rate:0x%02x)\n", index, path, rate);
+					power_index_4bytes = 0;
+						total_rate++;
+				}
+				#endif
+			}
+				
+		}
+		/*  total rate store in offset 0 */
+		*total_rate_offset = total_rate;
+
+#ifdef DBG_PWR_IDX_RSVD_PAGE
+			RTW_INFO("total_rate=%d\n", total_rate);
+			RTW_INFO(" ======================="ADPT_FMT"===========================\n", ADPT_ARG(iface));
+			RTW_INFO_DUMP("\n", total_rate_offset, 128);
+			RTW_INFO(" ==================================================\n");
+#endif
+
+			CurtPktPageNum = 1;
+			*total_page_num += CurtPktPageNum;
+			*index += (CurtPktPageNum * page_size);
+			#ifdef DBG_RSVD_PAGE_CFG
+			RSVD_PAGE_CFG("mcc_pwr_idx_rsvd_page", CurtPktPageNum, *total_page_num, *index);
+			#endif
+		}
+
+exit:
+	return ret;
+}
+
+/*
+* 1. Download MCC rsvd page
+* 2. Re-Download beacon after download rsvd page
+*/
+static void rtw_hal_set_fw_mcc_rsvd_page(PADAPTER padapter)
+{
+	HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
+	struct mcc_adapter_priv *pmccadapriv = &padapter->mcc_adapterpriv;
+	struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
+	PADAPTER port0_iface = dvobj_get_port0_adapter(dvobj);
+	PADAPTER iface = NULL;
+	struct mcc_obj_priv *pmccobjpriv = &(dvobj->mcc_objpriv);
+	u8 mstatus = RT_MEDIA_CONNECT, i = 0;
+
+	RTW_INFO(FUNC_ADPT_FMT"\n", FUNC_ADPT_ARG(padapter));
+
+	rtw_hal_set_hwreg(port0_iface, HW_VAR_H2C_FW_JOINBSSRPT, (u8 *)(&mstatus));
+
+	/* Re-Download beacon */
+	for (i = 0; i < MAX_MCC_NUM; i++) {
+		iface = pmccobjpriv->iface[i];
+		if (iface == NULL)
+			continue;
+
+		pmccadapriv = &iface->mcc_adapterpriv;
+
+		if (pmccadapriv->role == MCC_ROLE_AP
+			|| pmccadapriv->role == MCC_ROLE_GO) {
+			tx_beacon_hdl(iface, NULL);
+		}
+	}
+}
+
+static void rtw_hal_set_mcc_rsvdpage_cmd(_adapter *padapter)
+{
+	u8 cmd[H2C_MCC_LOCATION_LEN] = {0}, i = 0, order = 0;
+	_adapter *iface = NULL;
+	PHAL_DATA_TYPE hal = GET_HAL_DATA(padapter);
+	struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
+	struct mcc_obj_priv *pmccobjpriv = &(dvobj->mcc_objpriv);
+
+	SET_H2CCMD_MCC_PWRIDX_OFFLOAD_EN(cmd, _TRUE);
+	SET_H2CCMD_MCC_PWRIDX_OFFLOAD_RFNUM(cmd, hal->NumTotalRFPath);
+	for (order = 0; order < MAX_MCC_NUM; order++) {
+		iface = pmccobjpriv->iface[i];
+
+		SET_H2CCMD_MCC_RSVDPAGE_LOC((cmd + order), pmccobjpriv->mcc_loc_rsvd_paga[order]);
+		SET_H2CCMD_MCC_PWRIDX_RSVDPAGE_LOC ((cmd + order), pmccobjpriv->mcc_pwr_idx_rsvd_page[order]);
+	}
+
+#ifdef CONFIG_MCC_MODE_DEBUG
+	RTW_INFO("=========================\n");
+	RTW_INFO("MCC RSVD PAGE LOC:\n");
+	for (i = 0; i < H2C_MCC_LOCATION_LEN; i++)
+		pr_dbg("0x%x ", cmd[i]);
+	pr_dbg("\n");
+	RTW_INFO("=========================\n");
+#endif /* CONFIG_MCC_MODE_DEBUG */
+
+	rtw_hal_fill_h2c_cmd(padapter, H2C_MCC_LOCATION, H2C_MCC_LOCATION_LEN, cmd);
+}
+
+static void rtw_hal_set_mcc_time_setting_cmd(PADAPTER padapter)
+{
+	struct mcc_adapter_priv *pmccadapriv = &padapter->mcc_adapterpriv;
+	struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
+	struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
+	struct mcc_obj_priv *mccobjpriv = &(dvobj->mcc_objpriv);
+	u8 cmd[H2C_MCC_TIME_SETTING_LEN] = {0};
+	u8 fw_eable = 1;
+	u8 swchannel_early_time = MCC_SWCH_FW_EARLY_TIME;
+	u8 starting_ap_num = DEV_AP_STARTING_NUM(dvobj);
+	u8 ap_num = DEV_AP_NUM(dvobj);	
+
+	if (starting_ap_num == 0 && ap_num == 0)
+		/* For STA+GC/STA+STA, TSF of GC/STA does not need to sync from TSF of other STA/GC */
+		fw_eable = 0;
+	else
+		/* Only for STA+GO/STA+AP, TSF of AP/GO need to sync from TSF of STA */
+		fw_eable = 1;
+
+	if (fw_eable == 1) {
+		PADAPTER order0_iface = NULL;
+		PADAPTER order1_iface = NULL;
+		u8 policy_idx = mccobjpriv->policy_index;
+		u8 tsf_sync_offset = mcc_switch_channel_policy_table[policy_idx][MCC_TSF_SYNC_OFFSET_IDX];
+		u8 start_time_offset = mcc_switch_channel_policy_table[policy_idx][MCC_START_TIME_OFFSET_IDX];
+		u8 interval = mcc_switch_channel_policy_table[policy_idx][MCC_INTERVAL_IDX];
+		u8 guard_offset0 = mcc_switch_channel_policy_table[policy_idx][MCC_GUARD_OFFSET0_IDX];
+		u8 guard_offset1 = mcc_switch_channel_policy_table[policy_idx][MCC_GUARD_OFFSET1_IDX];
+		enum _hw_port tsf_bsae_port = MAX_HW_PORT;
+		enum _hw_port tsf_sync_port = MAX_HW_PORT;
+		order0_iface = mccobjpriv->iface[0];
+		order1_iface = mccobjpriv->iface[1];
+
+		tsf_bsae_port = rtw_hal_get_port(order1_iface);
+		tsf_sync_port = rtw_hal_get_port(order0_iface);
+		
+		/* FW set enable */
+		SET_H2CCMD_MCC_TIME_SETTING_FW_EN(cmd, fw_eable);
+		/* TSF Sync offset */
+		SET_H2CCMD_MCC_TIME_SETTING_TSF_SYNC_OFFSET(cmd, tsf_sync_offset);
+		/* start time offset */
+		SET_H2CCMD_MCC_TIME_SETTING_START_TIME(cmd, (start_time_offset + guard_offset0));
+		/* interval */
+		SET_H2CCMD_MCC_TIME_SETTING_INTERVAL(cmd, interval);
+		/* Early time to inform driver by C2H before switch channel */
+		SET_H2CCMD_MCC_TIME_SETTING_EARLY_SWITCH_RPT(cmd, swchannel_early_time);
+		/* Port0 sync from Port1, not support multi-port */
+		SET_H2CCMD_MCC_TIME_SETTING_ORDER_BASE(cmd, tsf_bsae_port);
+		SET_H2CCMD_MCC_TIME_SETTING_ORDER_SYNC(cmd, tsf_sync_port);
+	} else {
+		/* start time offset */
+		SET_H2CCMD_MCC_TIME_SETTING_START_TIME(cmd, mccobjpriv->start_time);
+		/* interval */
+		SET_H2CCMD_MCC_TIME_SETTING_INTERVAL(cmd, mccobjpriv->interval);
+		/* Early time to inform driver by C2H before switch channel */
+		SET_H2CCMD_MCC_TIME_SETTING_EARLY_SWITCH_RPT(cmd, swchannel_early_time);
+	}
+
+#ifdef CONFIG_MCC_MODE_DEBUG
+	{
+		u8 i = 0;
+
+		RTW_INFO("=========================\n");
+		RTW_INFO("NoA:\n");
+		for (i = 0; i < H2C_MCC_TIME_SETTING_LEN; i++)
+			pr_dbg("0x%x ", cmd[i]);
+		pr_dbg("\n");
+		RTW_INFO("=========================\n");
+	}
+#endif /* CONFIG_MCC_MODE_DEBUG */
+
+	rtw_hal_fill_h2c_cmd(padapter, H2C_MCC_TIME_SETTING, H2C_MCC_TIME_SETTING_LEN, cmd);
+}
+
+static void rtw_hal_set_mcc_IQK_offload_cmd(PADAPTER padapter)
+{
+	struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
+	struct mcc_obj_priv *pmccobjpriv = &(dvobj->mcc_objpriv);
+	struct mcc_adapter_priv *pmccadapriv = NULL;
+	_adapter *iface = NULL;
+	u8 cmd[H2C_MCC_IQK_PARAM_LEN] = {0}, bready = 0, i = 0, order = 0;
+	u16 TX_X = 0, TX_Y = 0, RX_X = 0, RX_Y = 0;
+	u8 total_rf_path = GET_HAL_DATA(padapter)->NumTotalRFPath;
+	u8 rf_path_idx = 0, last_order = MAX_MCC_NUM - 1, last_rf_path_index = total_rf_path - 1;
+
+	/* by order, last order & last_rf_path_index must set ready bit = 1 */
+	for (i = 0; i < MAX_MCC_NUM; i++) {
+		iface = pmccobjpriv->iface[i];
+		if (iface == NULL)
+			continue;
+
+		pmccadapriv = &iface->mcc_adapterpriv;
+		order = pmccadapriv->order;
+
+		for (rf_path_idx = 0; rf_path_idx < total_rf_path; rf_path_idx ++) {
+
+			_rtw_memset(cmd, 0, H2C_MCC_IQK_PARAM_LEN);
+			TX_X = pmccadapriv->mcc_iqk_arr[rf_path_idx].TX_X & 0x7ff;/* [10:0]  */
+			TX_Y = pmccadapriv->mcc_iqk_arr[rf_path_idx].TX_Y & 0x7ff;/* [10:0]  */
+			RX_X = pmccadapriv->mcc_iqk_arr[rf_path_idx].RX_X & 0x3ff;/* [9:0]  */
+			RX_Y = pmccadapriv->mcc_iqk_arr[rf_path_idx].RX_Y & 0x3ff;/* [9:0]  */
+
+			/* ready or not */
+			if (order == last_order && rf_path_idx == last_rf_path_index)
+				bready = 1;
+			else
+				bready = 0;
+
+			SET_H2CCMD_MCC_IQK_READY(cmd, bready);
+			SET_H2CCMD_MCC_IQK_ORDER(cmd, order);
+			SET_H2CCMD_MCC_IQK_PATH(cmd, rf_path_idx);
+
+			/* fill RX_X[7:0] to (cmd+1)[7:0] bitlen=8 */
+			SET_H2CCMD_MCC_IQK_RX_L(cmd, (u8)(RX_X & 0xff));
+			/* fill RX_X[9:8] to (cmd+2)[1:0] bitlen=2 */
+			SET_H2CCMD_MCC_IQK_RX_M1(cmd, (u8)((RX_X >> 8) & 0x03));
+			/* fill RX_Y[5:0] to (cmd+2)[7:2] bitlen=6 */
+			SET_H2CCMD_MCC_IQK_RX_M2(cmd, (u8)(RX_Y & 0x3f));
+			/* fill RX_Y[9:6] to (cmd+3)[3:0] bitlen=4 */
+			SET_H2CCMD_MCC_IQK_RX_H(cmd, (u8)((RX_Y >> 6) & 0x0f));
+
+
+			/* fill TX_X[7:0] to (cmd+4)[7:0] bitlen=8 */
+			SET_H2CCMD_MCC_IQK_TX_L(cmd, (u8)(TX_X & 0xff));
+			/* fill TX_X[10:8] to (cmd+5)[2:0] bitlen=3 */
+			SET_H2CCMD_MCC_IQK_TX_M1(cmd, (u8)((TX_X >> 8) & 0x07));
+			/* fill TX_Y[4:0] to (cmd+5)[7:3] bitlen=5 */
+			SET_H2CCMD_MCC_IQK_TX_M2(cmd, (u8)(TX_Y & 0x1f));
+			/* fill TX_Y[10:5] to (cmd+6)[5:0] bitlen=6 */
+			SET_H2CCMD_MCC_IQK_TX_H(cmd, (u8)((TX_Y >> 5) & 0x3f));
+
+#ifdef CONFIG_MCC_MODE_DEBUG
+			RTW_INFO("=========================\n");
+			RTW_INFO(FUNC_ADPT_FMT" IQK:\n", FUNC_ADPT_ARG(iface));
+			RTW_INFO("TX_X: 0x%02x\n", TX_X);
+			RTW_INFO("TX_Y: 0x%02x\n", TX_Y);
+			RTW_INFO("RX_X: 0x%02x\n", RX_X);
+			RTW_INFO("RX_Y: 0x%02x\n", RX_Y);
+			RTW_INFO("cmd[0]:0x%02x\n", cmd[0]);
+			RTW_INFO("cmd[1]:0x%02x\n", cmd[1]);
+			RTW_INFO("cmd[2]:0x%02x\n", cmd[2]);
+			RTW_INFO("cmd[3]:0x%02x\n", cmd[3]);
+			RTW_INFO("cmd[4]:0x%02x\n", cmd[4]);
+			RTW_INFO("cmd[5]:0x%02x\n", cmd[5]);
+			RTW_INFO("cmd[6]:0x%02x\n", cmd[6]);
+			RTW_INFO("=========================\n");
+#endif /* CONFIG_MCC_MODE_DEBUG */
+
+			rtw_hal_fill_h2c_cmd(padapter, H2C_MCC_IQK_PARAM, H2C_MCC_IQK_PARAM_LEN, cmd);
+		}
+	}
+}
+
+
+static void rtw_hal_set_mcc_macid_cmd(PADAPTER padapter)
+{
+	struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
+	struct mcc_adapter_priv *pmccadapriv = NULL;
+	_adapter *iface = NULL;
+	u8 cmd[H2C_MCC_MACID_BITMAP_LEN] = {0}, i = 0, order = 0;
+	u16 bitmap = 0;
+
+	for (i = 0; i < dvobj->iface_nums; i++) {
+		iface = dvobj->padapters[i];
+		if (iface == NULL)
+			continue;
+
+		pmccadapriv = &iface->mcc_adapterpriv;
+		if (pmccadapriv->role == MCC_ROLE_MAX)
+			continue;
+		
+		order = pmccadapriv->order;
+		bitmap = pmccadapriv->mcc_macid_bitmap;
+
+		if (order >= (H2C_MCC_MACID_BITMAP_LEN/2)) {
+			RTW_INFO(FUNC_ADPT_FMT" only support 3 interface at most(%d)\n"
+				, FUNC_ADPT_ARG(padapter), order);
+			continue;
+		}
+		SET_H2CCMD_MCC_MACID_BITMAP_L((cmd + order * 2), (u8)(bitmap & 0xff));
+		SET_H2CCMD_MCC_MACID_BITMAP_H((cmd + order * 2), (u8)((bitmap >> 8) & 0xff));
+	}
+
+#ifdef CONFIG_MCC_MODE_DEBUG
+	RTW_INFO("=========================\n");
+	RTW_INFO("MACID BITMAP: ");
+	for (i = 0; i < H2C_MCC_MACID_BITMAP_LEN; i++)
+		printk("0x%x ", cmd[i]);
+	printk("\n");
+	RTW_INFO("=========================\n");
+#endif /* CONFIG_MCC_MODE_DEBUG */
+	rtw_hal_fill_h2c_cmd(padapter, H2C_MCC_MACID_BITMAP, H2C_MCC_MACID_BITMAP_LEN, cmd);
+}
+
+#ifdef CONFIG_MCC_MODE_V2
+static u8 get_pri_ch_idx_by_adapter(u8 center_ch, u8 channel, u8 bw, u8 ch_offset40)
+{
+	u8 pri_ch_idx = 0, chnl_offset80 = 0;
+
+	if (bw == CHANNEL_WIDTH_80) {
+		if (center_ch > channel)
+			chnl_offset80 = HAL_PRIME_CHNL_OFFSET_LOWER;
+		else if (center_ch < channel)
+			chnl_offset80 = HAL_PRIME_CHNL_OFFSET_UPPER;
+		else
+			chnl_offset80 = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
+	}
+
+	if (bw == CHANNEL_WIDTH_80) {
+		/* primary channel is at lower subband of 80MHz & 40MHz */
+		if ((ch_offset40 == HAL_PRIME_CHNL_OFFSET_LOWER) && (chnl_offset80 == HAL_PRIME_CHNL_OFFSET_LOWER))
+			pri_ch_idx = VHT_DATA_SC_20_LOWEST_OF_80MHZ;
+		/* primary channel is at lower subband of 80MHz & upper subband of 40MHz */
+		else if ((ch_offset40 == HAL_PRIME_CHNL_OFFSET_UPPER) && (chnl_offset80 == HAL_PRIME_CHNL_OFFSET_LOWER))
+			pri_ch_idx = VHT_DATA_SC_20_LOWER_OF_80MHZ;
+		/* primary channel is at upper subband of 80MHz & lower subband of 40MHz */
+		else if ((ch_offset40 == HAL_PRIME_CHNL_OFFSET_LOWER) && (chnl_offset80 == HAL_PRIME_CHNL_OFFSET_UPPER))
+			pri_ch_idx = VHT_DATA_SC_20_UPPER_OF_80MHZ;
+		/* primary channel is at upper subband of 80MHz & upper subband of 40MHz */
+		else if ((ch_offset40 == HAL_PRIME_CHNL_OFFSET_UPPER) && (chnl_offset80 == HAL_PRIME_CHNL_OFFSET_UPPER))
+			pri_ch_idx = VHT_DATA_SC_20_UPPERST_OF_80MHZ;
+		else {
+			if (chnl_offset80 == HAL_PRIME_CHNL_OFFSET_LOWER)
+				pri_ch_idx = VHT_DATA_SC_40_LOWER_OF_80MHZ;
+			else if (chnl_offset80 == HAL_PRIME_CHNL_OFFSET_UPPER)
+				pri_ch_idx = VHT_DATA_SC_40_UPPER_OF_80MHZ;
+			else
+				RTW_INFO("SCMapping: DONOT CARE Mode Setting\n");
+		}
+	} else if (bw == CHANNEL_WIDTH_40) {
+		/* primary channel is at upper subband of 40MHz */
+		if (ch_offset40== HAL_PRIME_CHNL_OFFSET_UPPER)
+			pri_ch_idx = VHT_DATA_SC_20_UPPER_OF_80MHZ;
+		/* primary channel is at lower subband of 40MHz */
+		else if (ch_offset40 == HAL_PRIME_CHNL_OFFSET_LOWER)
+			pri_ch_idx = VHT_DATA_SC_20_LOWER_OF_80MHZ;
+		else
+			RTW_INFO("SCMapping: DONOT CARE Mode Setting\n");
+	}
+
+	return  pri_ch_idx;
+}
+
+static void rtw_hal_set_mcc_ctrl_cmd_v2(PADAPTER padapter, u8 stop)
+{
+	u8 cmd[H2C_MCC_CTRL_LEN] = {0}, i = 0;
+	u8 order = 0, totalnum = 0;
+	u8 center_ch = 0, pri_ch_idx = 0, bw = 0;
+	u8 duration = 0, role = 0, incurch = 0, rfetype = 0, distxnull = 0, c2hrpt = 0;
+	u8 dis_sw_retry = 0, null_early_time=2, tsfx = 0, update_parm = 0;
+	struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
+	struct mcc_obj_priv *pmccobjpriv = &(dvobj->mcc_objpriv);
+	struct mcc_adapter_priv *mccadapriv = NULL;
+	struct mlme_ext_priv *pmlmeext = NULL;
+	struct mlme_ext_info *pmlmeinfo = NULL;
+	_adapter *iface = NULL;
+
+	RTW_INFO(FUNC_ADPT_FMT": stop=%d\n", FUNC_ADPT_ARG(padapter), stop);
+
+	for (i = 0; i < MAX_MCC_NUM; i++) {
+		iface = pmccobjpriv->iface[i];
+		if (iface == NULL)
+			continue;
+
+		if (stop) {
+			if (iface != padapter)
+				continue;
+		}
+
+		mccadapriv = &iface->mcc_adapterpriv;
+		order = mccadapriv->order;
+
+		if (!stop)
+			totalnum = MAX_MCC_NUM;
+		else
+			totalnum = 0xff; /* 0xff means stop */
+
+		pmlmeext = &iface->mlmeextpriv;
+		center_ch = rtw_get_center_ch(pmlmeext->cur_channel, pmlmeext->cur_bwmode, pmlmeext->cur_ch_offset);
+		pri_ch_idx = get_pri_ch_idx_by_adapter(center_ch, pmlmeext->cur_channel, pmlmeext->cur_bwmode, pmlmeext->cur_ch_offset);
+		bw = pmlmeext->cur_bwmode;
+		duration = mccadapriv->mcc_duration;
+		role = mccadapriv->role;
+
+		incurch = _FALSE;
+		dis_sw_retry = _TRUE;
+
+		/* STA/GC TX NULL data to inform AP/GC for ps mode */
+		switch (role) {
+		case MCC_ROLE_GO:
+		case MCC_ROLE_AP:
+			distxnull = MCC_DISABLE_TX_NULL;
+			break;
+		case MCC_ROLE_GC:
+			set_channel_bwmode(iface, pmlmeext->cur_channel, pmlmeext->cur_ch_offset, pmlmeext->cur_bwmode);
+			distxnull = MCC_ENABLE_TX_NULL;
+			break;
+		case MCC_ROLE_STA:
+			distxnull = MCC_ENABLE_TX_NULL;
+			break;
+		}
+
+		null_early_time = mccadapriv->null_early;
+
+		c2hrpt = MCC_C2H_REPORT_ALL_STATUS;
+		tsfx = rtw_hal_get_port(iface);
+		update_parm = 0;
+
+		SET_H2CCMD_MCC_CTRL_V2_ORDER(cmd, order);
+		SET_H2CCMD_MCC_CTRL_V2_TOTALNUM(cmd, totalnum);
+		SET_H2CCMD_MCC_CTRL_V2_CENTRAL_CH(cmd, center_ch);
+		SET_H2CCMD_MCC_CTRL_V2_PRIMARY_CH(cmd, pri_ch_idx);
+		SET_H2CCMD_MCC_CTRL_V2_BW(cmd, bw);
+		SET_H2CCMD_MCC_CTRL_V2_DURATION(cmd, duration);
+		SET_H2CCMD_MCC_CTRL_V2_ROLE(cmd, role);
+		SET_H2CCMD_MCC_CTRL_V2_INCURCH(cmd, incurch);
+		SET_H2CCMD_MCC_CTRL_V2_DIS_SW_RETRY(cmd, dis_sw_retry);
+		SET_H2CCMD_MCC_CTRL_V2_DISTXNULL(cmd, distxnull);
+		SET_H2CCMD_MCC_CTRL_V2_C2HRPT(cmd, c2hrpt);
+		SET_H2CCMD_MCC_CTRL_V2_TSFX(cmd, tsfx);
+		SET_H2CCMD_MCC_CTRL_V2_NULL_EARLY(cmd, null_early_time);
+		SET_H2CCMD_MCC_CTRL_V2_UPDATE_PARM(cmd, update_parm);
+
+#ifdef CONFIG_MCC_MODE_DEBUG
+		RTW_INFO("=========================\n");
+		RTW_INFO(FUNC_ADPT_FMT" MCC INFO:\n", FUNC_ADPT_ARG(iface));
+		RTW_INFO("cmd[0]:0x%02x\n", cmd[0]);
+		RTW_INFO("cmd[1]:0x%02x\n", cmd[1]);
+		RTW_INFO("cmd[2]:0x%02x\n", cmd[2]);
+		RTW_INFO("cmd[3]:0x%02x\n", cmd[3]);
+		RTW_INFO("cmd[4]:0x%02x\n", cmd[4]);
+		RTW_INFO("cmd[5]:0x%02x\n", cmd[5]);
+		RTW_INFO("cmd[6]:0x%02x\n", cmd[6]);
+		RTW_INFO("=========================\n");
+#endif /* CONFIG_MCC_MODE_DEBUG */
+
+		rtw_hal_fill_h2c_cmd(padapter, H2C_MCC_CTRL_V2, H2C_MCC_CTRL_LEN, cmd);
+	}
+}
+
+#else
+static void rtw_hal_set_mcc_ctrl_cmd_v1(PADAPTER padapter, u8 stop)
+{
+	u8 cmd[H2C_MCC_CTRL_LEN] = {0}, i = 0;
+	u8 order = 0, totalnum = 0, chidx = 0, bw = 0, bw40sc = 0, bw80sc = 0;
+	u8 duration = 0, role = 0, incurch = 0, rfetype = 0, distxnull = 0, c2hrpt = 0, chscan = 0;
+	struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
+	struct mcc_obj_priv *pmccobjpriv = &(dvobj->mcc_objpriv);
+	struct mcc_adapter_priv *mccadapriv = NULL;
+	struct mlme_ext_priv *pmlmeext = NULL;
+	struct mlme_ext_info *pmlmeinfo = NULL;
+	HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
+	_adapter *iface = NULL;
+
+	RTW_INFO(FUNC_ADPT_FMT": stop=%d\n", FUNC_ADPT_ARG(padapter), stop);
+
+	for (i = 0; i < MAX_MCC_NUM; i++) {
+		iface = pmccobjpriv->iface[i];
+		if (iface == NULL)
+			continue;
+
+		if (stop) {
+			if (iface != padapter)
+				continue;
+		}
+
+		mccadapriv = &iface->mcc_adapterpriv;
+		order = mccadapriv->order;
+
+		if (!stop)
+			totalnum = MAX_MCC_NUM;
+		else
+			totalnum = 0xff; /* 0xff means stop */
+
+		pmlmeext = &iface->mlmeextpriv;
+		chidx = pmlmeext->cur_channel;
+		bw = pmlmeext->cur_bwmode;
+		bw40sc = pmlmeext->cur_ch_offset;
+
+		/* decide 80 band width offset */
+		if (bw == CHANNEL_WIDTH_80) {
+			u8 center_ch = rtw_get_center_ch(chidx, bw, bw40sc);
+
+			if (center_ch > chidx)
+				bw80sc = HAL_PRIME_CHNL_OFFSET_LOWER;
+			else if (center_ch < chidx)
+				bw80sc = HAL_PRIME_CHNL_OFFSET_UPPER;
+			else
+				bw80sc = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
+		} else
+			bw80sc = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
+
+		duration = mccadapriv->mcc_duration;
+		role = mccadapriv->role;
+
+		incurch = _FALSE;
+
+		if (IS_HARDWARE_TYPE_8812(padapter))
+			rfetype = pHalData->rfe_type; /* RFETYPE (only for 8812)*/
+		else
+			rfetype = 0;
+
+		/* STA/GC TX NULL data to inform AP/GC for ps mode */
+		switch (role) {
+		case MCC_ROLE_GO:
+		case MCC_ROLE_AP:
+			distxnull = MCC_DISABLE_TX_NULL;
+			break;
+		case MCC_ROLE_GC:
+		case MCC_ROLE_STA:
+			distxnull = MCC_ENABLE_TX_NULL;
+			break;
+		}
+
+		c2hrpt = MCC_C2H_REPORT_ALL_STATUS;
+		chscan = MCC_CHIDX;
+
+		SET_H2CCMD_MCC_CTRL_ORDER(cmd, order);
+		SET_H2CCMD_MCC_CTRL_TOTALNUM(cmd, totalnum);
+		SET_H2CCMD_MCC_CTRL_CHIDX(cmd, chidx);
+		SET_H2CCMD_MCC_CTRL_BW(cmd, bw);
+		SET_H2CCMD_MCC_CTRL_BW40SC(cmd, bw40sc);
+		SET_H2CCMD_MCC_CTRL_BW80SC(cmd, bw80sc);
+		SET_H2CCMD_MCC_CTRL_DURATION(cmd, duration);
+		SET_H2CCMD_MCC_CTRL_ROLE(cmd, role);
+		SET_H2CCMD_MCC_CTRL_INCURCH(cmd, incurch);
+		SET_H2CCMD_MCC_CTRL_RFETYPE(cmd, rfetype);
+		SET_H2CCMD_MCC_CTRL_DISTXNULL(cmd, distxnull);
+		SET_H2CCMD_MCC_CTRL_C2HRPT(cmd, c2hrpt);
+		SET_H2CCMD_MCC_CTRL_CHSCAN(cmd, chscan);
+
+#ifdef CONFIG_MCC_MODE_DEBUG
+		RTW_INFO("=========================\n");
+		RTW_INFO(FUNC_ADPT_FMT" MCC INFO:\n", FUNC_ADPT_ARG(iface));
+		RTW_INFO("cmd[0]:0x%02x\n", cmd[0]);
+		RTW_INFO("cmd[1]:0x%02x\n", cmd[1]);
+		RTW_INFO("cmd[2]:0x%02x\n", cmd[2]);
+		RTW_INFO("cmd[3]:0x%02x\n", cmd[3]);
+		RTW_INFO("cmd[4]:0x%02x\n", cmd[4]);
+		RTW_INFO("cmd[5]:0x%02x\n", cmd[5]);
+		RTW_INFO("cmd[6]:0x%02x\n", cmd[6]);
+		RTW_INFO("=========================\n");
+#endif /* CONFIG_MCC_MODE_DEBUG */
+
+		rtw_hal_fill_h2c_cmd(padapter, H2C_MCC_CTRL, H2C_MCC_CTRL_LEN, cmd);
+	}
+}
+#endif
+
+static void rtw_hal_set_mcc_ctrl_cmd(PADAPTER padapter, u8 stop)
+{
+	#ifdef CONFIG_MCC_MODE_V2
+		/* new cmd 0x17 */
+		rtw_hal_set_mcc_ctrl_cmd_v2(padapter, stop);
+	#else
+		/* old cmd 0x18 */
+		rtw_hal_set_mcc_ctrl_cmd_v1(padapter, stop);
+	#endif
+}
+
+static u8 check_mcc_support(PADAPTER adapter)
+{
+	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
+	u8 sta_linking_num = DEV_STA_LG_NUM(dvobj);
+	u8 sta_linked_num = DEV_STA_LD_NUM(dvobj);
+	u8 starting_ap_num = DEV_AP_STARTING_NUM(dvobj);
+	u8 ap_num = DEV_AP_NUM(dvobj);
+	u8 ret = _SUCCESS;
+
+	/* case for linking sta + linked sta  */
+	if ((sta_linking_num + sta_linked_num) != MAX_MCC_NUM) {
+		ret = _FAIL;
+		goto exit;
+	}
+
+	/* case for starting AP + linked sta */
+	if ((starting_ap_num + sta_linked_num) != MAX_MCC_NUM) {
+		ret = _FAIL;
+		goto exit;
+	}
+
+	/* case for linking sta  + started AP */
+	if ((sta_linking_num + ap_num) != MAX_MCC_NUM) {
+		ret = _FAIL;
+		goto exit;
+	}
+
+	/* case for starting AP +  started AP */
+	if ((starting_ap_num + ap_num) != MAX_MCC_NUM) {
+		ret = _FAIL;
+		goto exit;
+	}
+
+exit:
+		return ret;
+}
+
+static void rtw_hal_mcc_start_prehdl(PADAPTER padapter)
+{
+	struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
+	_adapter *iface = NULL;
+	struct mcc_adapter_priv *mccadapriv = NULL;
+	u8 i = 1;
+
+	for (i = 0; i < dvobj->iface_nums; i++) {
+		iface = dvobj->padapters[i];
+		if (iface == NULL)
+			continue;
+
+		mccadapriv = &iface->mcc_adapterpriv;
+		mccadapriv->role = MCC_ROLE_MAX;
+	}
+}
+
+static u8 rtw_hal_set_mcc_start_setting(PADAPTER padapter, u8 status)
+{
+	u8 ret = _SUCCESS, enable_tsf_auto_sync = _FALSE;
+	struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
+	struct pwrctrl_priv *pwrpriv = dvobj_to_pwrctl(dvobj);
+
+	if (pwrpriv->pwr_mode != PS_MODE_ACTIVE) {
+		rtw_warn_on(1);
+		RTW_INFO("PS mode is not active before start mcc, force exit ps mode\n");
+		LeaveAllPowerSaveModeDirect(padapter);
+	}
+
+	if (check_mcc_support(padapter)) {
+		RTW_INFO("%s: check_mcc_support fail\n", __func__);
+		dump_dvobj_mi_status(RTW_DBGDUMP, __func__, padapter);
+		ret = _FAIL;
+		goto exit;
+	}
+
+	rtw_hal_mcc_start_prehdl(padapter);
+
+	/* configure mcc switch channel setting */
+	rtw_hal_config_mcc_switch_channel_setting(padapter);
+
+	if (rtw_hal_decide_mcc_role(padapter) == _FAIL) {
+		ret = _FAIL;
+		goto exit;
+	}
+
+	/* set mcc status to indicate process mcc start setting */
+	rtw_hal_set_mcc_status(padapter, MCC_STATUS_PROCESS_MCC_START_SETTING);
+
+	/* only download rsvd page for connect */
+	if (status == MCC_SETCMD_STATUS_START_CONNECT) {
+		/* download mcc rsvd page */
+		rtw_hal_set_fw_mcc_rsvd_page(padapter);
+		rtw_hal_set_mcc_rsvdpage_cmd(padapter);
+	}
+
+	/* configure time setting */
+	rtw_hal_set_mcc_time_setting_cmd(padapter);
+
+#ifndef CONFIG_MCC_MODE_V2
+	/* IQK value offload */
+	rtw_hal_set_mcc_IQK_offload_cmd(padapter);
+#endif
+
+	/* set mac id to fw */
+	rtw_hal_set_mcc_macid_cmd(padapter);
+
+	if (dvobj->p0_tsf.sync_port != MAX_HW_PORT ) {
+		/* disable tsf auto sync */
+		RTW_INFO("[MCC] disable HW TSF sync\n");
+		rtw_hal_set_hwreg(padapter, HW_VAR_TSF_AUTO_SYNC, &enable_tsf_auto_sync);
+	} else {
+		RTW_INFO("[MCC] already disable HW TSF sync\n");
+	}
+
+	/* set mcc parameter  */
+	rtw_hal_set_mcc_ctrl_cmd(padapter, _FALSE);
+
+exit:
+	return ret;
+}
+
+static void rtw_hal_set_mcc_stop_setting(PADAPTER padapter, u8 status)
+{
+	struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
+	struct mcc_obj_priv *mccobjpriv = &dvobj->mcc_objpriv;
+	_adapter *iface = NULL;
+	struct mcc_adapter_priv *mccadapriv = NULL;
+	u8 i = 0;
+	/*
+	 * when adapter disconnect, stop mcc mod
+	 * total=0xf means stop mcc mode
+	 */
+
+	switch (status) {
+	default:
+		/* let fw switch to other interface channel */
+		for (i = 0; i < MAX_MCC_NUM; i++) {
+			iface = mccobjpriv->iface[i];
+			if (iface == NULL)
+				continue;
+
+			mccadapriv = &iface->mcc_adapterpriv;
+
+			/* use other interface to set cmd */
+			if (iface != padapter) {
+				rtw_hal_set_mcc_ctrl_cmd(iface, _TRUE);
+				break;
+			}
+		}
+		break;
+	}
+}
+
+static void rtw_hal_mcc_status_hdl(PADAPTER padapter, u8 status)
+{
+	switch (status) {
+	case MCC_SETCMD_STATUS_STOP_DISCONNECT:
+		rtw_hal_clear_mcc_status(padapter, MCC_STATUS_NEED_MCC | MCC_STATUS_DOING_MCC);
+		break;
+	case MCC_SETCMD_STATUS_STOP_SCAN_START:
+		rtw_hal_set_mcc_status(padapter, MCC_STATUS_NEED_MCC);
+		rtw_hal_clear_mcc_status(padapter, MCC_STATUS_DOING_MCC);
+		break;
+
+	case MCC_SETCMD_STATUS_START_CONNECT:
+	case MCC_SETCMD_STATUS_START_SCAN_DONE:
+		rtw_hal_set_mcc_status(padapter, MCC_STATUS_NEED_MCC | MCC_STATUS_DOING_MCC);
+		break;
+	default:
+		RTW_INFO(FUNC_ADPT_FMT" error status(%d)\n", FUNC_ADPT_ARG(padapter), status);
+		break;
+	}
+}
+
+static void rtw_hal_mcc_stop_posthdl(PADAPTER padapter)
+{
+	struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
+	struct mcc_obj_priv *mccobjpriv = &(adapter_to_dvobj(padapter)->mcc_objpriv);
+	struct mcc_adapter_priv *mccadapriv = NULL;
+	_adapter *iface = NULL;
+	PHAL_DATA_TYPE hal;
+	struct dm_struct *p_dm_odm;
+	u8 i = 0;
+	u8 enable_rx_bar = _FALSE;
+
+	for (i = 0; i < MAX_MCC_NUM; i++) {
+		iface = mccobjpriv->iface[i];
+		if (iface == NULL)
+			continue;
+
+		/* release network queue */
+		rtw_netif_wake_queue(iface->pnetdev);
+		mccadapriv = &iface->mcc_adapterpriv;
+		mccadapriv->mcc_tx_bytes_from_kernel = 0;
+		mccadapriv->mcc_last_tx_bytes_from_kernel = 0;
+		mccadapriv->mcc_tx_bytes_to_port = 0;
+
+		if (mccadapriv->role == MCC_ROLE_GO)
+			rtw_hal_mcc_remove_go_p2p_ie(iface);
+
+#ifdef CONFIG_TDLS
+		if (MLME_IS_STA(iface)) {
+			if (mccadapriv->backup_tdls_en) {
+				rtw_enable_tdls_func(iface);
+				RTW_INFO("%s: Disable MCC, Enable TDLS\n", __func__);
+				mccadapriv->backup_tdls_en = _FALSE;
+			}
+		}
+#endif /* CONFIG_TDLS */
+
+		mccadapriv->role = MCC_ROLE_MAX;
+		mccobjpriv->iface[i] = NULL;
+	}
+
+	hal = GET_HAL_DATA(padapter);
+	p_dm_odm = &hal->odmpriv;
+	phydm_dm_early_init(p_dm_odm);
+
+	/* force switch channel */
+	hal->current_channel = 0;
+	hal->current_channel_bw = CHANNEL_WIDTH_MAX;
+}
+
+static void rtw_hal_mcc_start_posthdl(PADAPTER padapter)
+{
+	struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
+	struct mcc_obj_priv *mccobjpriv = &(adapter_to_dvobj(padapter)->mcc_objpriv);
+	struct mcc_adapter_priv *mccadapriv = NULL;
+	_adapter *iface = NULL;
+	PHAL_DATA_TYPE hal;
+	struct dm_struct *p_dm_odm;
+	struct _hal_rf_ *p_rf;
+	u32 support_ability = 0;
+	u8 i = 0;
+	u8 enable_rx_bar = _TRUE;
+
+	for (i = 0; i < dvobj->iface_nums; i++) {
+		iface = dvobj->padapters[i];
+		if (iface == NULL)
+			continue;
+
+		mccadapriv = &iface->mcc_adapterpriv;
+		if (mccadapriv->role == MCC_ROLE_MAX)
+			continue;
+		
+		mccadapriv->mcc_tx_bytes_from_kernel = 0;
+		mccadapriv->mcc_last_tx_bytes_from_kernel = 0;
+		mccadapriv->mcc_tx_bytes_to_port = 0;
+
+#ifdef CONFIG_TDLS
+		if (MLME_IS_STA(iface)) {
+			if (rtw_is_tdls_enabled(iface)) {
+				mccadapriv->backup_tdls_en = _TRUE;
+				rtw_disable_tdls_func(iface, _TRUE);
+				RTW_INFO("%s: Enable MCC, Disable TDLS\n", __func__);
+			}
+		}
+#endif /* CONFIG_TDLS */
+	}
+
+	hal = GET_HAL_DATA(padapter);
+	p_dm_odm = &hal->odmpriv;
+	p_rf = &(p_dm_odm->rf_table);
+	mccobjpriv->backup_phydm_ability = p_rf->rf_supportability;
+	p_rf->rf_supportability = p_rf->rf_supportability & (~HAL_RF_TX_PWR_TRACK) & (~HAL_RF_IQK);
+}
+
+/*
+ * rtw_hal_set_mcc_setting - set mcc setting
+ * @padapter: currnet padapter to stop/start MCC
+ * @stop: stop mcc or not
+ * @return val: 1 for SUCCESS, 0 for fail
+ */
+static u8 rtw_hal_set_mcc_setting(PADAPTER padapter, u8 status)
+{
+	u8 ret = _FAIL;
+	struct mcc_obj_priv *pmccobjpriv = &(adapter_to_dvobj(padapter)->mcc_objpriv);
+	u8 stop = (status < MCC_SETCMD_STATUS_START_CONNECT) ? _TRUE : _FALSE;
+	u32 start_time = rtw_get_current_time();
+
+	RTW_INFO("===> "FUNC_ADPT_FMT"\n", FUNC_ADPT_ARG(padapter));
+
+	rtw_sctx_init(&pmccobjpriv->mcc_sctx, MCC_EXPIRE_TIME);
+	pmccobjpriv->mcc_c2h_status = MCC_RPT_MAX;
+
+	if (stop == _FALSE) {
+		/* handle mcc start */
+		if (rtw_hal_set_mcc_start_setting(padapter, status) == _FAIL)
+			goto exit;
+
+		/* wait for C2H */
+		if (!rtw_sctx_wait(&pmccobjpriv->mcc_sctx, __func__))
+			RTW_INFO(FUNC_ADPT_FMT": wait for mcc start C2H time out\n", FUNC_ADPT_ARG(padapter));
+		else
+			ret = _SUCCESS;
+
+		if (ret == _SUCCESS) {
+			RTW_INFO(FUNC_ADPT_FMT": mcc start sucecssfully\n", FUNC_ADPT_ARG(padapter));
+			rtw_hal_mcc_status_hdl(padapter, status);
+			rtw_hal_mcc_start_posthdl(padapter);
+		}
+	} else {
+
+		/* set mcc status to indicate process mcc start setting */
+		rtw_hal_set_mcc_status(padapter, MCC_STATUS_PROCESS_MCC_STOP_SETTING);
+
+		/* handle mcc stop */
+		rtw_hal_set_mcc_stop_setting(padapter, status);
+
+		/* wait for C2H */
+		if (!rtw_sctx_wait(&pmccobjpriv->mcc_sctx, __func__))
+			RTW_INFO(FUNC_ADPT_FMT": wait for mcc stop C2H time out\n", FUNC_ADPT_ARG(padapter));
+		else {
+			ret = _SUCCESS;
+			rtw_hal_mcc_status_hdl(padapter, status);
+			rtw_hal_mcc_stop_posthdl(padapter);
+		}
+	}
+
+exit:
+	/* clear mcc status */
+	rtw_hal_clear_mcc_status(padapter
+		, MCC_STATUS_PROCESS_MCC_START_SETTING | MCC_STATUS_PROCESS_MCC_STOP_SETTING);
+
+	RTW_INFO(FUNC_ADPT_FMT" in %dms <===\n"
+		, FUNC_ADPT_ARG(padapter), rtw_get_passing_time_ms(start_time));
+	return ret;
+}
+
+/**
+ * rtw_hal_mcc_check_case_not_limit_traffic - handler flow ctrl for special case
+ * @cur_iface: fw stay channel setting of this iface
+ * @next_iface: fw will swich channel setting of this iface
+ */
+static void rtw_hal_mcc_check_case_not_limit_traffic(PADAPTER cur_iface, PADAPTER next_iface)
+{
+	u8 cur_bw = cur_iface->mlmeextpriv.cur_bwmode;
+	u8 next_bw = next_iface->mlmeextpriv.cur_bwmode;
+
+	/* for both interface are VHT80, doesn't limit_traffic according to iperf results */
+	if (cur_bw == CHANNEL_WIDTH_80 && next_bw == CHANNEL_WIDTH_80) {
+		cur_iface->mcc_adapterpriv.mcc_tp_limit = _FALSE;
+		next_iface->mcc_adapterpriv.mcc_tp_limit = _FALSE;
+	}
+}
+
+
+/**
+ * rtw_hal_mcc_sw_ch_fw_notify_hdl - handler flow ctrl
+ */
+static void rtw_hal_mcc_sw_ch_fw_notify_hdl(PADAPTER padapter)
+{
+	struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(padapter);
+	struct mcc_obj_priv *pmccobjpriv = &(pdvobjpriv->mcc_objpriv);
+	struct mcc_adapter_priv *cur_mccadapriv = NULL, *next_mccadapriv = NULL;
+	_adapter *iface = NULL, *cur_iface = NULL, *next_iface = NULL;
+	struct registry_priv *preg = &padapter->registrypriv;
+	u8 cur_op_ch = pdvobjpriv->oper_channel;
+	u8 i = 0, iface_num = pdvobjpriv->iface_nums, cur_order = 0, next_order = 0;
+	static u8 cnt = 1;
+	u32 single_tx_cri = preg->rtw_mcc_single_tx_cri;
+
+	for (i = 0; i < iface_num; i++) {
+		iface = pdvobjpriv->padapters[i];
+		if (iface == NULL)
+			continue;
+
+		if (cur_op_ch == iface->mlmeextpriv.cur_channel) {
+			cur_iface = iface;
+			cur_mccadapriv = &cur_iface->mcc_adapterpriv;
+			cur_order = cur_mccadapriv->order;
+			next_order = (cur_order + 1) % iface_num;
+			next_iface = pmccobjpriv->iface[next_order];
+			next_mccadapriv = &next_iface->mcc_adapterpriv;
+			break;
+		}
+	}
+
+	if (cur_iface == NULL || next_iface == NULL) {
+		RTW_ERR("cur_iface=%p,next_iface=%p\n", cur_iface, next_iface);
+		rtw_warn_on(1);
+		return;
+	}
+
+	/* check other interface tx busy traffic or not under every 2 switch channel notify(Mbits/100ms) */
+	if (cnt == 2) {
+		cur_mccadapriv->mcc_tp = (cur_mccadapriv->mcc_tx_bytes_from_kernel
+			- cur_mccadapriv->mcc_last_tx_bytes_from_kernel) * 10 * 8 / 1024 / 1024;
+		cur_mccadapriv->mcc_last_tx_bytes_from_kernel = cur_mccadapriv->mcc_tx_bytes_from_kernel;
+
+		next_mccadapriv->mcc_tp = (next_mccadapriv->mcc_tx_bytes_from_kernel
+			- next_mccadapriv->mcc_last_tx_bytes_from_kernel) * 10 * 8 / 1024 / 1024;
+		next_mccadapriv->mcc_last_tx_bytes_from_kernel = next_mccadapriv->mcc_tx_bytes_from_kernel;
+
+		cnt = 1;
+	} else
+		cnt = 2;
+
+	/* check single TX or cuncurrnet TX */
+	if (next_mccadapriv->mcc_tp < single_tx_cri) {
+		/* single TX, does not stop */
+		cur_mccadapriv->mcc_tx_stop = _FALSE;
+		cur_mccadapriv->mcc_tp_limit = _FALSE;
+	} else {
+		/* concurrent TX, stop */
+		cur_mccadapriv->mcc_tx_stop = _TRUE;
+		cur_mccadapriv->mcc_tp_limit = _TRUE;
+	}
+
+	if (cur_mccadapriv->mcc_tp < single_tx_cri) {
+		next_mccadapriv->mcc_tx_stop  = _FALSE;
+		next_mccadapriv->mcc_tp_limit = _FALSE;
+	} else {
+		next_mccadapriv->mcc_tx_stop = _FALSE;
+		next_mccadapriv->mcc_tp_limit = _TRUE;
+		next_mccadapriv->mcc_tx_bytes_to_port = 0;
+	}
+
+	/* stop current iface kernel queue or not */
+	if (cur_mccadapriv->mcc_tx_stop)
+		rtw_netif_stop_queue(cur_iface->pnetdev);
+	else
+		rtw_netif_wake_queue(cur_iface->pnetdev);
+
+	/* stop next iface kernel queue or not */
+	if (next_mccadapriv->mcc_tx_stop)
+		rtw_netif_stop_queue(next_iface->pnetdev);
+	else
+		rtw_netif_wake_queue(next_iface->pnetdev);
+
+	/* start xmit tasklet */
+	rtw_os_xmit_schedule(next_iface);
+
+	rtw_hal_mcc_check_case_not_limit_traffic(cur_iface, next_iface);
+
+	if (0) {
+		RTW_INFO("order:%d, mcc_tx_stop:%d, mcc_tp:%d\n",
+			cur_mccadapriv->order, cur_mccadapriv->mcc_tx_stop, cur_mccadapriv->mcc_tp);
+		dump_os_queue(0, cur_iface);
+		RTW_INFO("order:%d, mcc_tx_stop:%d, mcc_tp:%d\n",
+			next_mccadapriv->order, next_mccadapriv->mcc_tx_stop, next_mccadapriv->mcc_tp);
+		dump_os_queue(0, next_iface);
+	}
+}
+
+static void rtw_hal_mcc_update_noa_start_time_hdl(PADAPTER padapter, u8 buflen, u8 *tmpBuf)
+{
+	struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(padapter);
+	struct mcc_obj_priv *pmccobjpriv = &(pdvobjpriv->mcc_objpriv);
+	struct mcc_adapter_priv *pmccadapriv = NULL;
+	PADAPTER iface = NULL;
+	u8 i = 0;
+	u8 policy_idx = pmccobjpriv->policy_index;
+	u8 noa_tsf_sync_offset = mcc_switch_channel_policy_table[policy_idx][MCC_TSF_SYNC_OFFSET_IDX];
+	u8 noa_start_time_offset = mcc_switch_channel_policy_table[policy_idx][MCC_START_TIME_OFFSET_IDX];
+	
+	for (i = 0; i < pdvobjpriv->iface_nums; i++) {
+		iface = pdvobjpriv->padapters[i];
+		if (iface == NULL)
+			continue;
+		
+		pmccadapriv = &iface->mcc_adapterpriv;
+		if (pmccadapriv->role == MCC_ROLE_MAX)
+			continue;
+
+		/* GO & channel match */
+		if (pmccadapriv->role == MCC_ROLE_GO) {
+			/* convert GO TBTT from FW to noa_start_time(TU convert to mircosecond) */
+			pmccadapriv->noa_start_time = RTW_GET_LE32(tmpBuf + 2) + noa_start_time_offset * TU;
+
+			if (0) {
+				RTW_INFO("TBTT:0x%02x\n", RTW_GET_LE32(tmpBuf + 2));
+				RTW_INFO("noa_tsf_sync_offset:%d, noa_start_time_offset:%d\n", noa_tsf_sync_offset, noa_start_time_offset);
+				RTW_INFO(FUNC_ADPT_FMT"buf=0x%02x:0x%02x:0x%02x:0x%02x, noa_start_time=0x%02x\n"
+					, FUNC_ADPT_ARG(iface)
+					, tmpBuf[2]
+					, tmpBuf[3]
+					, tmpBuf[4]
+					, tmpBuf[5]
+					,pmccadapriv->noa_start_time);
+				}
+
+			rtw_hal_mcc_update_go_p2p_ie(iface);
+
+			break;
+		}
+	}
+
+}
+
+static void rtw_hal_mcc_rpt_tsf_hdl(PADAPTER padapter, u8 buflen, u8 *tmpBuf)
+{
+	struct dvobj_priv *dvobjpriv = adapter_to_dvobj(padapter);
+	struct mcc_obj_priv *mccobjpriv = &(adapter_to_dvobj(padapter)->mcc_objpriv);
+	struct submit_ctx *mcc_tsf_req_sctx = &mccobjpriv->mcc_tsf_req_sctx;
+	struct mcc_adapter_priv *mccadapriv = NULL;
+	_adapter *iface = NULL;
+	u8 order = 0;
+
+	order = mccobjpriv->mcc_tsf_req_sctx_order;
+	iface = mccobjpriv->iface[order];
+	mccadapriv = &iface->mcc_adapterpriv;
+	mccadapriv->tsf = RTW_GET_LE64(tmpBuf + 2);
+
+
+	if (0)
+		RTW_INFO(FUNC_ADPT_FMT" TSF(order:%d):0x%02llx\n", FUNC_ADPT_ARG(iface), mccadapriv->order, mccadapriv->tsf);
+
+	if (mccadapriv->order == (MAX_MCC_NUM - 1))
+		rtw_sctx_done(&mcc_tsf_req_sctx);
+	else
+		mccobjpriv->mcc_tsf_req_sctx_order ++;
+
+}
+
+/**
+ * rtw_hal_mcc_c2h_handler - mcc c2h handler
+ */
+void rtw_hal_mcc_c2h_handler(PADAPTER padapter, u8 buflen, u8 *tmpBuf)
+{
+	struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(padapter);
+	struct mcc_obj_priv *pmccobjpriv = &(adapter_to_dvobj(padapter)->mcc_objpriv);
+	struct mcc_adapter_priv *pmccadapriv = &padapter->mcc_adapterpriv;
+	struct submit_ctx *mcc_sctx = &pmccobjpriv->mcc_sctx;
+	_adapter *cur_adapter = NULL;
+	u8 cur_ch = 0, cur_bw = 0, cur_ch_offset = 0;
+	_irqL irqL;
+
+	/* RTW_INFO("[length]=%d, [C2H data]="MAC_FMT"\n", buflen, MAC_ARG(tmpBuf)); */
+	/* To avoid reg is set, but driver recive c2h to set wrong oper_channel */
+	if (MCC_RPT_STOPMCC == pmccobjpriv->mcc_c2h_status) {
+		RTW_INFO(FUNC_ADPT_FMT" MCC alread stops return\n", FUNC_ADPT_ARG(padapter));
+		return;
+	}
+
+	pmccobjpriv->mcc_c2h_status = tmpBuf[0];
+	pmccobjpriv->current_order = tmpBuf[1];
+	cur_adapter = pmccobjpriv->iface[pmccobjpriv->current_order];
+	cur_ch = cur_adapter->mlmeextpriv.cur_channel;
+	cur_bw = cur_adapter->mlmeextpriv.cur_bwmode;
+	cur_ch_offset = cur_adapter->mlmeextpriv.cur_ch_offset;
+	rtw_set_oper_ch(cur_adapter, cur_ch);
+	rtw_set_oper_bw(cur_adapter, cur_bw);
+	rtw_set_oper_choffset(cur_adapter, cur_ch_offset);
+
+	if (0)
+		RTW_INFO("%d,order:%d,TSF:0x%llx\n", tmpBuf[0], tmpBuf[1], RTW_GET_LE64(tmpBuf + 2));
+	
+	switch (pmccobjpriv->mcc_c2h_status) {
+	case MCC_RPT_SUCCESS:
+		_enter_critical_bh(&pmccobjpriv->mcc_lock, &irqL);
+		pmccobjpriv->cur_mcc_success_cnt++;
+		rtw_hal_mcc_upadate_chnl_bw(cur_adapter, cur_ch, cur_ch_offset, cur_bw, _FALSE);
+		_exit_critical_bh(&pmccobjpriv->mcc_lock, &irqL);
+		break;
+	case MCC_RPT_TXNULL_FAIL:
+		RTW_INFO("[MCC] TXNULL FAIL\n");
+		break;
+	case MCC_RPT_STOPMCC:
+		RTW_INFO("[MCC] MCC stop\n");
+		pmccobjpriv->mcc_c2h_status = MCC_RPT_STOPMCC;
+		rtw_hal_mcc_upadate_chnl_bw(cur_adapter, cur_ch, cur_ch_offset, cur_bw, _TRUE);
+		rtw_sctx_done(&mcc_sctx);
+		break;
+	case MCC_RPT_READY:
+		_enter_critical_bh(&pmccobjpriv->mcc_lock, &irqL);
+		/* initialize counter & time */
+		pmccobjpriv->mcc_launch_time = rtw_get_current_time();
+		pmccobjpriv->mcc_c2h_status = MCC_RPT_READY;
+		pmccobjpriv->cur_mcc_success_cnt = 0;
+		pmccobjpriv->prev_mcc_success_cnt = 0;
+		pmccobjpriv->mcc_tolerance_time = MCC_TOLERANCE_TIME;
+		_exit_critical_bh(&pmccobjpriv->mcc_lock, &irqL);
+
+		RTW_INFO("[MCC] MCC ready\n");
+		rtw_sctx_done(&mcc_sctx);
+		break;
+	case MCC_RPT_SWICH_CHANNEL_NOTIFY:
+		rtw_hal_mcc_sw_ch_fw_notify_hdl(padapter);
+		break;
+	case MCC_RPT_UPDATE_NOA_START_TIME:
+		rtw_hal_mcc_update_noa_start_time_hdl(padapter, buflen, tmpBuf);
+		break;
+	case MCC_RPT_TSF:
+		_enter_critical_bh(&pmccobjpriv->mcc_lock, &irqL);
+		rtw_hal_mcc_rpt_tsf_hdl(padapter, buflen, tmpBuf);
+		_exit_critical_bh(&pmccobjpriv->mcc_lock, &irqL);
+		break;
+	default:
+		/* RTW_INFO("[MCC] Other MCC status(%d)\n", pmccobjpriv->mcc_c2h_status); */
+		break;
+	}
+}
+
+void rtw_hal_mcc_update_parameter(PADAPTER padapter, u8 force_update)
+{	
+	struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
+	struct mcc_obj_priv *mccobjpriv = &(dvobj->mcc_objpriv);
+	u8 cmd[H2C_MCC_TIME_SETTING_LEN] = {0};
+	u8 swchannel_early_time = MCC_SWCH_FW_EARLY_TIME;
+	u8 ap_num = DEV_AP_NUM(dvobj);	
+
+	if (ap_num == 0) {
+		u8 need_update = _FALSE;
+		u8 start_time_offset = 0, interval = 0, duration = 0;
+
+		need_update = rtw_hal_mcc_update_timing_parameters(padapter, force_update);
+
+		if (need_update == _FALSE)
+			return;
+		
+		start_time_offset = mccobjpriv->start_time;
+		interval = mccobjpriv->interval;
+		duration = mccobjpriv->iface[0]->mcc_adapterpriv.mcc_duration;
+
+		SET_H2CCMD_MCC_TIME_SETTING_START_TIME(cmd, start_time_offset);
+		SET_H2CCMD_MCC_TIME_SETTING_INTERVAL(cmd, interval);
+		SET_H2CCMD_MCC_TIME_SETTING_EARLY_SWITCH_RPT(cmd, swchannel_early_time);
+		SET_H2CCMD_MCC_TIME_SETTING_UPDATE(cmd, _TRUE);
+		SET_H2CCMD_MCC_TIME_SETTING_ORDER0_DURATION(cmd, duration);
+	} else {
+		PADAPTER order0_iface = NULL;
+		PADAPTER order1_iface = NULL;
+		u8 policy_idx = mccobjpriv->policy_index;
+		u8 duration = mcc_switch_channel_policy_table[policy_idx][MCC_DURATION_IDX];
+		u8 tsf_sync_offset = mcc_switch_channel_policy_table[policy_idx][MCC_TSF_SYNC_OFFSET_IDX];
+		u8 start_time_offset = mcc_switch_channel_policy_table[policy_idx][MCC_START_TIME_OFFSET_IDX];
+		u8 interval = mcc_switch_channel_policy_table[policy_idx][MCC_INTERVAL_IDX];
+		u8 guard_offset0 = mcc_switch_channel_policy_table[policy_idx][MCC_GUARD_OFFSET0_IDX];
+		u8 guard_offset1 = mcc_switch_channel_policy_table[policy_idx][MCC_GUARD_OFFSET1_IDX];
+		u8 order0_duration = 0;
+		u8 i = 0;
+		enum _hw_port tsf_bsae_port = MAX_HW_PORT;
+		enum _hw_port tsf_sync_port = MAX_HW_PORT;
+
+		RTW_INFO("%s: policy_idx=%d\n", __func__, policy_idx);
+
+		order0_iface = mccobjpriv->iface[0];
+		order1_iface = mccobjpriv->iface[1];
+
+		/* GO/AP is order 0, GC/STA is order 1 */
+		order0_duration = order0_iface->mcc_adapterpriv.mcc_duration = interval - duration;
+		order0_iface->mcc_adapterpriv.mcc_duration = duration;
+
+		tsf_bsae_port = rtw_hal_get_port(order1_iface);
+		tsf_sync_port = rtw_hal_get_port(order0_iface);
+
+		/* update IE */
+		for (i = 0; i < dvobj->iface_nums; i++) {
+			PADAPTER iface = NULL;
+			struct mcc_adapter_priv *mccadapriv = NULL;
+
+			iface = dvobj->padapters[i];
+			if (iface == NULL)
+				continue;
+		
+			mccadapriv = &iface->mcc_adapterpriv;
+			if (mccadapriv->role == MCC_ROLE_MAX)
+				continue;
+			
+			if (mccadapriv->role == MCC_ROLE_GO)
+				rtw_hal_mcc_update_go_p2p_ie(iface);
+		}
+
+		/* update H2C cmd */
+		/* FW set enable */
+		SET_H2CCMD_MCC_TIME_SETTING_FW_EN(cmd, _TRUE);
+		/* TSF Sync offset */
+		SET_H2CCMD_MCC_TIME_SETTING_TSF_SYNC_OFFSET(cmd, tsf_sync_offset);
+		/* start time offset */
+		SET_H2CCMD_MCC_TIME_SETTING_START_TIME(cmd, (start_time_offset + guard_offset0));
+		/* interval */
+		SET_H2CCMD_MCC_TIME_SETTING_INTERVAL(cmd, interval);
+		/* Early time to inform driver by C2H before switch channel */
+		SET_H2CCMD_MCC_TIME_SETTING_EARLY_SWITCH_RPT(cmd, swchannel_early_time);
+		/* Port0 sync from Port1, not support multi-port */
+		SET_H2CCMD_MCC_TIME_SETTING_ORDER_BASE(cmd, tsf_bsae_port);
+		SET_H2CCMD_MCC_TIME_SETTING_ORDER_SYNC(cmd, tsf_sync_port);
+		SET_H2CCMD_MCC_TIME_SETTING_UPDATE(cmd, _TRUE);
+		SET_H2CCMD_MCC_TIME_SETTING_ORDER0_DURATION(cmd, order0_duration);
+	}
+
+	rtw_hal_fill_h2c_cmd(padapter, H2C_MCC_TIME_SETTING, H2C_MCC_TIME_SETTING_LEN, cmd);
+}
+
+/**
+ * rtw_hal_mcc_sw_status_check - check mcc swich channel status
+ * @padapter: primary adapter
+ */
+void rtw_hal_mcc_sw_status_check(PADAPTER padapter)
+{
+	struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
+	struct mcc_obj_priv *pmccobjpriv = &(dvobj->mcc_objpriv);
+	struct pwrctrl_priv	*pwrpriv = dvobj_to_pwrctl(dvobj);
+	struct mcc_adapter_priv *mccadapriv = NULL;
+	_adapter *iface = NULL;
+	u8 cur_cnt = 0, prev_cnt = 0, diff_cnt = 0, check_ret = _FAIL, threshold = 0;
+	u8 policy_idx = pmccobjpriv->policy_index;
+	u8 noa_enable = _FALSE;
+	u8 i = 0;
+	_irqL irqL;
+	u8 ap_num = DEV_AP_NUM(dvobj);	
+
+/* #define MCC_RESTART 1 */
+
+	if (!MCC_EN(padapter))
+		return;
+
+	_enter_critical_mutex(&pmccobjpriv->mcc_mutex, NULL);
+
+	if (rtw_hal_check_mcc_status(padapter, MCC_STATUS_DOING_MCC)) {
+
+		/* check noa enable or not */
+		for (i = 0; i < dvobj->iface_nums; i++) {
+			iface = dvobj->padapters[i];
+			if (iface == NULL)
+				continue;
+
+			mccadapriv = &iface->mcc_adapterpriv;
+			if (mccadapriv->role == MCC_ROLE_MAX)
+				continue;
+			
+			if (iface->wdinfo.p2p_ps_mode == P2P_PS_NOA) {
+				noa_enable = _TRUE;
+				break;
+			}
+		}		
+
+		if (!noa_enable && ap_num == 0)
+			rtw_hal_mcc_update_parameter(padapter, _FALSE);
+
+		threshold = pmccobjpriv->mcc_stop_threshold;
+
+		if (pwrpriv->pwr_mode != PS_MODE_ACTIVE) {
+			rtw_warn_on(1);
+			RTW_INFO("PS mode is not active under mcc, force exit ps mode\n");
+			LeaveAllPowerSaveModeDirect(padapter);
+		}
+
+		if (rtw_get_passing_time_ms(pmccobjpriv->mcc_launch_time) > 2000) {
+			_enter_critical_bh(&pmccobjpriv->mcc_lock, &irqL);
+
+			cur_cnt = pmccobjpriv->cur_mcc_success_cnt;
+			prev_cnt = pmccobjpriv->prev_mcc_success_cnt;
+			if (cur_cnt < prev_cnt)
+				diff_cnt = (cur_cnt + 255) - prev_cnt;
+			else
+				diff_cnt = cur_cnt - prev_cnt;
+
+			if (diff_cnt < threshold) {
+				pmccobjpriv->mcc_tolerance_time--;
+				RTW_INFO("%s: diff_cnt:%d, tolerance_time:%d\n",
+					__func__, diff_cnt, pmccobjpriv->mcc_tolerance_time);
+			} else
+				pmccobjpriv->mcc_tolerance_time = MCC_TOLERANCE_TIME;
+
+			pmccobjpriv->prev_mcc_success_cnt = pmccobjpriv->cur_mcc_success_cnt;
+
+			if (pmccobjpriv->mcc_tolerance_time != 0)
+				check_ret = _SUCCESS;
+
+			_exit_critical_bh(&pmccobjpriv->mcc_lock, &irqL);
+
+			if (check_ret != _SUCCESS) {
+				RTW_INFO("============ MCC swich channel check fail (%d)=============\n", diff_cnt);
+				/* restart MCC */
+				#ifdef MCC_RESTART
+					rtw_hal_set_mcc_setting(padapter, MCC_SETCMD_STATUS_STOP_DISCONNECT);
+					rtw_hal_set_mcc_setting(padapter, MCC_SETCMD_STATUS_START_CONNECT);
+				#endif /* MCC_RESTART */
+			}
+		} else {
+			_enter_critical_bh(&pmccobjpriv->mcc_lock, &irqL);
+			pmccobjpriv->prev_mcc_success_cnt = pmccobjpriv->cur_mcc_success_cnt;
+			_exit_critical_bh(&pmccobjpriv->mcc_lock, &irqL);
+		}
+
+	}
+	_exit_critical_mutex(&pmccobjpriv->mcc_mutex, NULL);
+}
+
+/**
+ * rtw_hal_mcc_change_scan_flag - change scan flag under mcc
+ *
+ * MCC mode under sitesurvey goto AP channel to tx bcn & data
+ * MCC mode under sitesurvey doesn't support TX data for station mode (FW not support)
+ *
+ * @padapter: the adapter to be change scan flag
+ * @ch: pointer to rerurn ch
+ * @bw: pointer to rerurn bw
+ * @offset: pointer to rerurn offset
+ */
+u8 rtw_hal_mcc_change_scan_flag(PADAPTER padapter, u8 *ch, u8 *bw, u8 *offset)
+{
+	u8 need_ch_setting_union = _TRUE, i = 0, flags = 0, back_op = _FALSE;
+	struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
+	struct mcc_adapter_priv *mccadapriv = NULL;
+	struct mlme_ext_priv *mlmeext = NULL;
+	_adapter *iface = NULL;
+
+	if (!MCC_EN(padapter))
+		goto exit;
+
+	if (!rtw_hal_check_mcc_status(padapter, MCC_STATUS_NEED_MCC))
+		goto exit;
+
+	/* disable PS_ANNC & TX_RESUME for all interface */
+	/* ToDo: TX_RESUME by interface in SCAN_BACKING_OP */
+	mlmeext = &padapter->mlmeextpriv;
+	
+	flags = mlmeext_scan_backop_flags(mlmeext);
+	if (mlmeext_chk_scan_backop_flags(mlmeext, SS_BACKOP_PS_ANNC))
+		flags &= ~SS_BACKOP_PS_ANNC;
+
+	if (mlmeext_chk_scan_backop_flags(mlmeext, SS_BACKOP_TX_RESUME))
+		flags &= ~SS_BACKOP_TX_RESUME;
+
+	mlmeext_assign_scan_backop_flags(mlmeext, flags);
+
+	for (i = 0; i < dvobj->iface_nums; i++) {
+		iface = dvobj->padapters[i];
+		if (!iface)
+			continue;
+
+		mlmeext = &iface->mlmeextpriv;
+
+		if (MLME_IS_GO(iface) || MLME_IS_AP(iface))
+			back_op = _TRUE;
+		else if (MLME_IS_GC(iface) && (iface != padapter))
+			/* switch to another linked interface(GO) to receive beacon to avoid no beacon disconnect */
+			back_op = _TRUE;
+		else if (MLME_IS_STA(iface) && MLME_IS_ASOC(iface) && (iface != padapter))
+			/* switch to another linked interface(STA) to receive beacon to avoid no beacon disconnect  */
+			back_op = _TRUE;
+		else {
+			/* bypass non-linked/non-linking interface/scan interface */
+			continue;
+		}
+		
+		if (back_op) {
+			*ch = mlmeext->cur_channel;
+			*bw = mlmeext->cur_bwmode;
+			*offset = mlmeext->cur_ch_offset;
+			need_ch_setting_union = _FALSE;
+		}
+	}
+exit:
+	return need_ch_setting_union;
+}
+
+/**
+ * rtw_hal_mcc_calc_tx_bytes_from_kernel - calculte tx bytes from kernel to check concurrent tx or not
+ * @padapter: the adapter to be record tx bytes
+ * @len: data len
+ */
+inline void rtw_hal_mcc_calc_tx_bytes_from_kernel(PADAPTER padapter, u32 len)
+{
+	struct mcc_adapter_priv *pmccadapriv = &padapter->mcc_adapterpriv;
+
+	if (MCC_EN(padapter)) {
+		if (rtw_hal_check_mcc_status(padapter, MCC_STATUS_DOING_MCC)) {
+			pmccadapriv->mcc_tx_bytes_from_kernel += len;
+			if (0)
+				RTW_INFO("%s(order:%d): mcc tx bytes from kernel:%lld\n"
+					, __func__, pmccadapriv->order, pmccadapriv->mcc_tx_bytes_from_kernel);
+		}
+	}
+}
+
+/**
+ * rtw_hal_mcc_calc_tx_bytes_to_port - calculte tx bytes to write port in order to flow crtl
+ * @padapter: the adapter to be record tx bytes
+ * @len: data len
+ */
+inline void rtw_hal_mcc_calc_tx_bytes_to_port(PADAPTER padapter, u32 len)
+{
+	if (MCC_EN(padapter)) {
+		struct mcc_obj_priv *pmccobjpriv = &(adapter_to_dvobj(padapter)->mcc_objpriv);
+		struct mcc_adapter_priv *pmccadapriv = &padapter->mcc_adapterpriv;
+
+		if (rtw_hal_check_mcc_status(padapter, MCC_STATUS_DOING_MCC)) {
+			pmccadapriv->mcc_tx_bytes_to_port += len;
+			if (0)
+				RTW_INFO("%s(order:%d): mcc tx bytes to port:%d, mcc target tx bytes to port:%d\n"
+					, __func__, pmccadapriv->order, pmccadapriv->mcc_tx_bytes_to_port
+					, pmccadapriv->mcc_target_tx_bytes_to_port);
+		}
+	}
+}
+
+/**
+ * rtw_hal_mcc_stop_tx_bytes_to_port - stop write port to hw or not
+ * @padapter: the adapter to be stopped
+ */
+inline u8 rtw_hal_mcc_stop_tx_bytes_to_port(PADAPTER padapter)
+{
+	if (MCC_EN(padapter)) {
+		struct mcc_obj_priv *pmccobjpriv = &(adapter_to_dvobj(padapter)->mcc_objpriv);
+		struct mcc_adapter_priv *pmccadapriv = &padapter->mcc_adapterpriv;
+
+		if (rtw_hal_check_mcc_status(padapter, MCC_STATUS_DOING_MCC)) {
+			if (pmccadapriv->mcc_tp_limit) {
+				if (pmccadapriv->mcc_tx_bytes_to_port >= pmccadapriv->mcc_target_tx_bytes_to_port) {
+					pmccadapriv->mcc_tx_stop = _TRUE;
+					rtw_netif_stop_queue(padapter->pnetdev);
+					return _TRUE;
+				}
+			}
+		}
+	}
+
+	return _FALSE;
+}
+
+static void rtw_hal_mcc_assign_scan_flag(PADAPTER padapter, u8 scan_done)
+{
+	struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
+	struct mcc_adapter_priv *mccadapriv = NULL;
+	_adapter *iface = NULL;
+	struct mlme_ext_priv *pmlmeext = NULL;
+	u8 i = 0, flags;
+
+	if (!MCC_EN(padapter))
+		return;
+
+	for (i = 0; i < dvobj->iface_nums; i++) {
+		iface = dvobj->padapters[i];
+		if (iface == NULL)
+			continue;
+
+		mccadapriv = &iface->mcc_adapterpriv;
+		if (mccadapriv->role == MCC_ROLE_MAX)
+			continue;
+
+		pmlmeext = &iface->mlmeextpriv;
+		if (is_client_associated_to_ap(iface)) {
+			flags = mlmeext_scan_backop_flags_sta(pmlmeext);
+			if (scan_done) {
+				if (mlmeext_chk_scan_backop_flags_sta(pmlmeext, SS_BACKOP_EN)) {
+					flags &= ~SS_BACKOP_EN;
+					mlmeext_assign_scan_backop_flags_sta(pmlmeext, flags);
+				}
+			} else {
+				if (!mlmeext_chk_scan_backop_flags_sta(pmlmeext, SS_BACKOP_EN)) {
+					flags |= SS_BACKOP_EN;
+					mlmeext_assign_scan_backop_flags_sta(pmlmeext, flags);
+				}
+			}
+
+		}
+	}
+}
+
+/**
+ * rtw_hal_set_mcc_setting_scan_start - setting mcc under scan start
+ * @padapter: the adapter to be setted
+ * @ch_setting_changed: softap channel setting to be changed or not
+ */
+u8 rtw_hal_set_mcc_setting_scan_start(PADAPTER padapter)
+{
+	u8 ret = _FAIL;
+
+	if (MCC_EN(padapter)) {
+		struct mcc_obj_priv *pmccobjpriv = &(adapter_to_dvobj(padapter)->mcc_objpriv);
+
+		_enter_critical_mutex(&pmccobjpriv->mcc_mutex, NULL);
+		if (rtw_hal_check_mcc_status(padapter, MCC_STATUS_NEED_MCC)) {
+			if (rtw_hal_check_mcc_status(padapter, MCC_STATUS_DOING_MCC)) {
+				ret = rtw_hal_set_mcc_setting(padapter,  MCC_SETCMD_STATUS_STOP_SCAN_START);
+				rtw_hal_mcc_assign_scan_flag(padapter, 0);
+			}
+		}
+		_exit_critical_mutex(&pmccobjpriv->mcc_mutex, NULL);
+	}
+
+	return ret;
+}
+
+/**
+ * rtw_hal_set_mcc_setting_scan_complete - setting mcc after scan commplete
+ * @padapter: the adapter to be setted
+ * @ch_setting_changed: softap channel setting to be changed or not
+ */
+u8 rtw_hal_set_mcc_setting_scan_complete(PADAPTER padapter)
+{
+	u8 ret = _FAIL;
+
+	if (MCC_EN(padapter)) {
+		struct mcc_obj_priv *pmccobjpriv = &(adapter_to_dvobj(padapter)->mcc_objpriv);
+
+		_enter_critical_mutex(&pmccobjpriv->mcc_mutex, NULL);
+
+		if (rtw_hal_check_mcc_status(padapter, MCC_STATUS_NEED_MCC)) {
+				rtw_hal_mcc_assign_scan_flag(padapter, 1);
+				ret = rtw_hal_set_mcc_setting(padapter,  MCC_SETCMD_STATUS_START_SCAN_DONE);	
+		}
+		_exit_critical_mutex(&pmccobjpriv->mcc_mutex, NULL);
+	}
+
+	return ret;
+}
+
+
+/**
+ * rtw_hal_set_mcc_setting_start_bss_network - setting mcc under softap start
+ * @padapter: the adapter to be setted
+ * @chbw_grouped: channel bw offset can not be allowed or not
+ */
+u8 rtw_hal_set_mcc_setting_start_bss_network(PADAPTER padapter, u8 chbw_allow)
+{
+	u8 ret = _FAIL;
+
+	if (MCC_EN(padapter)) {
+		/* channel bw offset can not be allowed, start MCC */
+		if (chbw_allow == _FALSE) {
+				struct mcc_obj_priv *pmccobjpriv = &(adapter_to_dvobj(padapter)->mcc_objpriv);
+
+				rtw_hal_mcc_restore_iqk_val(padapter);
+				_enter_critical_mutex(&pmccobjpriv->mcc_mutex, NULL);
+				ret = rtw_hal_set_mcc_setting(padapter, MCC_SETCMD_STATUS_START_CONNECT);
+				_exit_critical_mutex(&pmccobjpriv->mcc_mutex, NULL);
+			}
+		}
+
+	return ret;
+}
+
+/**
+ * rtw_hal_set_mcc_setting_disconnect - setting mcc under mlme disconnect(stop softap/disconnect from AP)
+ * @padapter: the adapter to be setted
+ */
+u8 rtw_hal_set_mcc_setting_disconnect(PADAPTER padapter)
+{
+	u8 ret = _FAIL;
+
+	if (MCC_EN(padapter)) {
+		struct mcc_obj_priv *pmccobjpriv = &(adapter_to_dvobj(padapter)->mcc_objpriv);
+
+		_enter_critical_mutex(&pmccobjpriv->mcc_mutex, NULL);
+		if (rtw_hal_check_mcc_status(padapter, MCC_STATUS_NEED_MCC)) {
+			if (rtw_hal_check_mcc_status(padapter, MCC_STATUS_DOING_MCC))
+				ret = rtw_hal_set_mcc_setting(padapter,  MCC_SETCMD_STATUS_STOP_DISCONNECT);
+		}
+		_exit_critical_mutex(&pmccobjpriv->mcc_mutex, NULL);
+	}
+
+	return ret;
+}
+
+/**
+ * rtw_hal_set_mcc_setting_join_done_chk_ch - setting mcc under join done
+ * @padapter: the adapter to be checked
+ */
+u8 rtw_hal_set_mcc_setting_join_done_chk_ch(PADAPTER padapter)
+{
+	u8 ret = _FAIL;
+
+	if (MCC_EN(padapter)) {
+		struct mi_state mstate;
+
+		rtw_mi_status_no_self(padapter, &mstate);
+
+		if (MSTATE_STA_LD_NUM(&mstate) || MSTATE_STA_LG_NUM(&mstate) || MSTATE_AP_NUM(&mstate)) {
+			bool chbw_allow = _TRUE;
+			u8 u_ch, u_offset, u_bw;
+			struct mlme_ext_priv *cur_mlmeext = &padapter->mlmeextpriv;
+			struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
+
+			if (rtw_mi_get_ch_setting_union_no_self(padapter, &u_ch, &u_bw, &u_offset) <= 0) {
+				dump_adapters_status(RTW_DBGDUMP , dvobj);
+				rtw_warn_on(1);
+			}
+
+			RTW_INFO(FUNC_ADPT_FMT" union no self: %u,%u,%u\n"
+				, FUNC_ADPT_ARG(padapter), u_ch, u_bw, u_offset);
+
+			/* chbw_allow? */
+			chbw_allow = rtw_is_chbw_grouped(cur_mlmeext->cur_channel
+				, cur_mlmeext->cur_bwmode, cur_mlmeext->cur_ch_offset
+					, u_ch, u_bw, u_offset);
+
+			RTW_INFO(FUNC_ADPT_FMT" chbw_allow:%d\n"
+				, FUNC_ADPT_ARG(padapter), chbw_allow);
+
+			/* if chbw_allow = false, start MCC setting */
+			if (chbw_allow == _FALSE) {
+				struct mcc_obj_priv *pmccobjpriv = &dvobj->mcc_objpriv;
+
+				rtw_hal_mcc_restore_iqk_val(padapter);
+				_enter_critical_mutex(&pmccobjpriv->mcc_mutex, NULL);
+				ret = rtw_hal_set_mcc_setting(padapter, MCC_SETCMD_STATUS_START_CONNECT);
+				_exit_critical_mutex(&pmccobjpriv->mcc_mutex, NULL);
+		}
+	}
+	}
+
+	return ret;
+}
+
+/**
+ * rtw_hal_set_mcc_setting_chk_start_clnt_join - check change channel under start clnt join
+ * @padapter: the adapter to be checked
+ * @ch: pointer to rerurn ch
+ * @bw: pointer to rerurn bw
+ * @offset: pointer to rerurn offset
+ * @chbw_allow: allow to use adapter's channel setting
+ */
+u8 rtw_hal_set_mcc_setting_chk_start_clnt_join(PADAPTER padapter, u8 *ch, u8 *bw, u8 *offset, u8 chbw_allow)
+{
+	u8 ret = _FAIL;
+
+	/* if chbw_allow = false under en_mcc = TRUE, we do not change channel related setting  */
+	if (MCC_EN(padapter)) {
+		/* restore union channel related setting to current channel related setting */
+		if (chbw_allow == _FALSE) {
+			struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
+
+			/* issue null data to other interface connected to AP */
+			rtw_hal_mcc_issue_null_data(padapter, chbw_allow, _TRUE);
+
+			*ch = pmlmeext->cur_channel;
+			*bw = pmlmeext->cur_bwmode;
+			*offset = pmlmeext->cur_ch_offset;
+
+			RTW_INFO(FUNC_ADPT_FMT" en_mcc:%d(%d,%d,%d,)\n"
+				, FUNC_ADPT_ARG(padapter), MCC_EN(padapter)
+				, *ch, *bw, *offset);
+			ret = _SUCCESS;
+		}
+	}
+
+	return ret;
+}
+
+static void rtw_hal_mcc_dump_noa_content(void *sel, PADAPTER padapter)
+{
+	struct mcc_adapter_priv *pmccadapriv = NULL;
+	u8 *pos = NULL;
+	pmccadapriv = &padapter->mcc_adapterpriv;
+	/* last position for NoA attribute */
+	pos = pmccadapriv->p2p_go_noa_ie + pmccadapriv->p2p_go_noa_ie_len;
+
+
+	RTW_PRINT_SEL(sel, "\nStart to dump NoA Content\n");
+	RTW_PRINT_SEL(sel, "NoA Counts:%d\n", *(pos - 13));
+	RTW_PRINT_SEL(sel, "NoA Duration(TU):%d\n", (RTW_GET_LE32(pos - 12))/TU);
+	RTW_PRINT_SEL(sel, "NoA Interval(TU):%d\n", (RTW_GET_LE32(pos - 8))/TU);
+	RTW_PRINT_SEL(sel, "NoA Start time(microseconds):0x%02x\n", RTW_GET_LE32(pos - 4));
+	RTW_PRINT_SEL(sel, "End to dump NoA Content\n");
+}
+
+void rtw_hal_dump_mcc_info(void *sel, struct dvobj_priv *dvobj)
+{
+	struct mcc_obj_priv *mccobjpriv = &(dvobj->mcc_objpriv);
+	struct mcc_adapter_priv *mccadapriv = NULL;
+	_adapter *iface = NULL, *adapter = NULL;
+	struct registry_priv *regpriv = NULL;
+	u64 tsf[MAX_MCC_NUM] = {0};
+	u8 i = 0;
+
+	/* regpriv is common for all adapter */
+	adapter = dvobj_get_primary_adapter(dvobj);
+
+	RTW_PRINT_SEL(sel, "**********************************************\n");
+	RTW_PRINT_SEL(sel, "en_mcc:%d\n", MCC_EN(adapter));
+	RTW_PRINT_SEL(sel, "primary adapter("ADPT_FMT") duration:%d%c\n",
+		ADPT_ARG(dvobj_get_primary_adapter(dvobj)), mccobjpriv->duration, 37);
+	RTW_PRINT_SEL(sel, "runtime duration:%s\n", mccobjpriv->enable_runtime_duration ? "enable":"disable");
+
+	rtw_hal_mcc_rqt_tsf(dvobj_get_primary_adapter(dvobj), tsf);
+
+	for (i = 0; i < dvobj->iface_nums; i++) {
+		iface = dvobj->padapters[i];
+		if (!iface)
+			continue;
+
+		regpriv = &iface->registrypriv;
+		mccadapriv = &iface->mcc_adapterpriv;
+		if (mccadapriv->role == MCC_ROLE_MAX)
+			continue;
+
+		if (mccadapriv) {
+			u8 p2p_ps_mode = iface->wdinfo.p2p_ps_mode;
+
+			RTW_PRINT_SEL(sel, "adapter mcc info:\n");
+			RTW_PRINT_SEL(sel, "ifname:%s\n", ADPT_ARG(iface));
+			RTW_PRINT_SEL(sel, "order:%d\n", mccadapriv->order);
+			RTW_PRINT_SEL(sel, "duration:%d\n", mccadapriv->mcc_duration);
+			RTW_PRINT_SEL(sel, "target tx bytes:%d\n", mccadapriv->mcc_target_tx_bytes_to_port);
+			RTW_PRINT_SEL(sel, "current TP:%d\n", mccadapriv->mcc_tp);
+			RTW_PRINT_SEL(sel, "mgmt queue macid:%d\n", mccadapriv->mgmt_queue_macid);
+			RTW_PRINT_SEL(sel, "macid bitmap:0x%02x\n", mccadapriv->mcc_macid_bitmap);
+			RTW_PRINT_SEL(sel, "P2P NoA:%s\n\n", p2p_ps_mode == P2P_PS_NOA ? "enable":"disable");
+			RTW_PRINT_SEL(sel, "registry data:\n");
+			RTW_PRINT_SEL(sel, "ap target tx TP(BW:20M):%d Mbps\n", regpriv->rtw_mcc_ap_bw20_target_tx_tp);
+			RTW_PRINT_SEL(sel, "ap target tx TP(BW:40M):%d Mbps\n", regpriv->rtw_mcc_ap_bw40_target_tx_tp);
+			RTW_PRINT_SEL(sel, "ap target tx TP(BW:80M):%d Mbps\n", regpriv->rtw_mcc_ap_bw80_target_tx_tp);
+			RTW_PRINT_SEL(sel, "sta target tx TP(BW:20M):%d Mbps\n", regpriv->rtw_mcc_sta_bw20_target_tx_tp);
+			RTW_PRINT_SEL(sel, "sta target tx TP(BW:40M ):%d Mbps\n", regpriv->rtw_mcc_sta_bw40_target_tx_tp);
+			RTW_PRINT_SEL(sel, "sta target tx TP(BW:80M):%d Mbps\n", regpriv->rtw_mcc_sta_bw80_target_tx_tp);
+			RTW_PRINT_SEL(sel, "single tx criteria:%d Mbps\n", regpriv->rtw_mcc_single_tx_cri);
+			RTW_PRINT_SEL(sel, "HW TSF=0x%llx\n", tsf[mccadapriv->order]);
+			if (MLME_IS_GO(iface))
+				rtw_hal_mcc_dump_noa_content(sel, iface);
+			RTW_PRINT_SEL(sel, "**********************************************\n");
+		}
+	}
+	RTW_PRINT_SEL(sel, "------------------------------------------\n");
+	RTW_PRINT_SEL(sel, "policy index:%d\n", mccobjpriv->policy_index);	
+	RTW_PRINT_SEL(sel, "------------------------------------------\n");
+	RTW_PRINT_SEL(sel, "define data:\n");
+	RTW_PRINT_SEL(sel, "ap target tx TP(BW:20M):%d Mbps\n", MCC_AP_BW20_TARGET_TX_TP);
+	RTW_PRINT_SEL(sel, "ap target tx TP(BW:40M):%d Mbps\n", MCC_AP_BW40_TARGET_TX_TP);
+	RTW_PRINT_SEL(sel, "ap target tx TP(BW:80M):%d Mbps\n", MCC_AP_BW80_TARGET_TX_TP);
+	RTW_PRINT_SEL(sel, "sta target tx TP(BW:20M):%d Mbps\n", MCC_STA_BW20_TARGET_TX_TP);
+	RTW_PRINT_SEL(sel, "sta target tx TP(BW:40M):%d Mbps\n", MCC_STA_BW40_TARGET_TX_TP);
+	RTW_PRINT_SEL(sel, "sta target tx TP(BW:80M):%d Mbps\n", MCC_STA_BW80_TARGET_TX_TP);
+	RTW_PRINT_SEL(sel, "single tx criteria:%d Mbps\n", MCC_SINGLE_TX_CRITERIA);
+	RTW_PRINT_SEL(sel, "------------------------------------------\n");
+}
+
+inline void update_mcc_mgntframe_attrib(_adapter *padapter, struct pkt_attrib *pattrib)
+{
+	if (MCC_EN(padapter)) {
+		if (rtw_hal_check_mcc_status(padapter, MCC_STATUS_DOING_MCC)) {
+			/* use QSLT_MGNT to check mgnt queue or bcn queue */
+			if (pattrib->qsel == QSLT_MGNT) {
+				pattrib->mac_id = padapter->mcc_adapterpriv.mgmt_queue_macid;
+				pattrib->qsel = QSLT_VO;
+			}
+		}
+	}
+}
+
+inline u8 rtw_hal_mcc_link_status_chk(_adapter *padapter, const char *msg)
+{
+	u8 ret = _TRUE, i = 0;
+	struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
+	_adapter *iface;
+	struct mlme_ext_priv *mlmeext;
+
+	if (MCC_EN(padapter)) {
+		if (rtw_hal_check_mcc_status(padapter, MCC_STATUS_NEED_MCC)) {
+			for (i = 0; i < dvobj->iface_nums; i++) {
+				iface = dvobj->padapters[i];
+				mlmeext = &iface->mlmeextpriv;
+				if (mlmeext_scan_state(mlmeext) != SCAN_DISABLE) {
+					#ifdef DBG_EXPIRATION_CHK
+						RTW_INFO(FUNC_ADPT_FMT" don't enter %s under scan for MCC mode\n", FUNC_ADPT_ARG(padapter), msg);
+					#endif
+					ret = _FALSE;
+					goto exit;
+				}
+			}
+		}
+	}
+
+exit:
+	return ret;
+}
+
+void rtw_hal_mcc_issue_null_data(_adapter *padapter, u8 chbw_allow, u8 ps_mode)
+{
+	struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
+	_adapter *iface = NULL;
+	systime start = rtw_get_current_time();
+	u8 i = 0;
+
+	if (!MCC_EN(padapter))
+		return;
+
+	if (rtw_hal_check_mcc_status(padapter, MCC_STATUS_DOING_MCC))
+		return;
+
+	if (chbw_allow == _TRUE)
+		return;
+
+	for (i = 0; i < dvobj->iface_nums; i++) {
+		iface = dvobj->padapters[i];
+		/* issue null data to inform ap station will leave */
+		if (is_client_associated_to_ap(iface)) {
+			struct mlme_ext_priv *mlmeext = &iface->mlmeextpriv;
+			struct mlme_ext_info *mlmeextinfo = &mlmeext->mlmext_info;
+			u8 ch = mlmeext->cur_channel;
+			u8 bw = mlmeext->cur_bwmode;
+			u8 offset = mlmeext->cur_ch_offset;
+			struct sta_info *sta = rtw_get_stainfo(&iface->stapriv, get_my_bssid(&(mlmeextinfo->network)));
+
+			if (!sta)
+				continue;
+
+			set_channel_bwmode(iface, ch, offset, bw);
+
+			if (ps_mode)
+				rtw_hal_macid_sleep(iface, sta->cmn.mac_id);
+			else
+				rtw_hal_macid_wakeup(iface, sta->cmn.mac_id);
+
+			issue_nulldata(iface, NULL, ps_mode, 3, 50);
+		}
+	}
+	RTW_INFO("%s(%d ms)\n", __func__, rtw_get_passing_time_ms(start));
+}
+
+u8 *rtw_hal_mcc_append_go_p2p_ie(PADAPTER padapter, u8 *pframe, u32 *len)
+{
+	struct mcc_adapter_priv *pmccadapriv = &padapter->mcc_adapterpriv;
+
+	if (!MCC_EN(padapter))
+		return pframe;
+	
+	if (!rtw_hal_check_mcc_status(padapter, MCC_STATUS_DOING_MCC))
+		return pframe;
+
+	if (pmccadapriv->p2p_go_noa_ie_len == 0)
+		return pframe;
+
+	_rtw_memcpy(pframe, pmccadapriv->p2p_go_noa_ie, pmccadapriv->p2p_go_noa_ie_len);
+	*len = *len + pmccadapriv->p2p_go_noa_ie_len;
+
+	return pframe + pmccadapriv->p2p_go_noa_ie_len;
+}
+
+void rtw_hal_dump_mcc_policy_table(void *sel)
+{
+	u8 idx = 0;
+	RTW_PRINT_SEL(sel, "duration\t,tsf sync offset\t,start time offset\t,interval\t,guard offset0\t,guard offset1\n");
+
+	for (idx = 0; idx < mcc_max_policy_num; idx ++) {
+		RTW_PRINT_SEL(sel, "%d\t\t,%d\t\t\t,%d\t\t\t,%d\t\t,%d\t\t,%d\n"
+			, mcc_switch_channel_policy_table[idx][MCC_DURATION_IDX]
+			, mcc_switch_channel_policy_table[idx][MCC_TSF_SYNC_OFFSET_IDX]
+			, mcc_switch_channel_policy_table[idx][MCC_START_TIME_OFFSET_IDX]
+			, mcc_switch_channel_policy_table[idx][MCC_INTERVAL_IDX]
+			, mcc_switch_channel_policy_table[idx][MCC_GUARD_OFFSET0_IDX]
+			, mcc_switch_channel_policy_table[idx][MCC_GUARD_OFFSET1_IDX]);
+	}
+}
+
+void rtw_hal_mcc_update_macid_bitmap(PADAPTER padapter, int mac_id, u8 add)
+{
+	struct mcc_adapter_priv *pmccadapriv = &padapter->mcc_adapterpriv;
+
+	if (!MCC_EN(padapter))
+		return;
+
+	if (!rtw_hal_check_mcc_status(padapter, MCC_STATUS_DOING_MCC))
+		return;
+
+	if (pmccadapriv->role == MCC_ROLE_GC || pmccadapriv->role == MCC_ROLE_STA)
+		return;
+
+	if (mac_id < 0) {
+		RTW_WARN("%s: mac_id < 0(%d)\n", __func__, mac_id);
+		return;
+	}
+
+	RTW_INFO(ADPT_FMT" %s macid=%d, ori mcc_macid_bitmap=0x%08x\n"
+		, ADPT_ARG(padapter), add ? "add" : "clear"
+		, mac_id, pmccadapriv->mcc_macid_bitmap);
+
+	if (add)
+		pmccadapriv->mcc_macid_bitmap |= BIT(mac_id);
+	else
+		pmccadapriv->mcc_macid_bitmap &= ~(BIT(mac_id));
+
+	rtw_hal_set_mcc_macid_cmd(padapter);
+}
+
+void rtw_hal_mcc_process_noa(PADAPTER padapter)
+{
+	struct wifidirect_info *pwdinfo = &(padapter->wdinfo);
+	struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
+	struct mcc_obj_priv *pmccobjpriv = &(dvobj->mcc_objpriv);
+
+	if (!MCC_EN(padapter))
+		return;
+
+	if (!rtw_hal_check_mcc_status(padapter, MCC_STATUS_DOING_MCC))
+		return;
+
+	if (!MLME_IS_GC(padapter))
+		return;
+
+	switch(pwdinfo->p2p_ps_mode) {
+	case P2P_PS_NONE:
+		RTW_INFO("[MCC] Disable NoA under MCC\n");
+		rtw_hal_mcc_update_parameter(padapter, _TRUE);
+		break;
+	case P2P_PS_NOA:
+		RTW_INFO("[MCC] Enable NoA under MCC\n");
+		break;
+	default:
+		break;
+
+	}
+}
+
+void rtw_hal_mcc_parameter_init(PADAPTER padapter)
+{
+	if (!padapter->registrypriv.en_mcc)
+		return;
+
+	if (is_primary_adapter(padapter)) {
+		SET_MCC_EN_FLAG(padapter, padapter->registrypriv.en_mcc);
+		SET_MCC_DURATION(padapter, padapter->registrypriv.rtw_mcc_duration);
+		SET_MCC_RUNTIME_DURATION(padapter, padapter->registrypriv.rtw_mcc_enable_runtime_duration);
+	}
+}
+
+
+u8 rtw_set_mcc_duration_hdl(PADAPTER adapter, u8 type, const u8 *val)
+{
+	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
+	struct mcc_obj_priv *mccobjpriv = &(dvobj->mcc_objpriv);
+	_adapter *iface = NULL;
+	u8 duration = 50;
+	u8 ret = _SUCCESS, noa_enable = _FALSE, i = 0;
+
+	if (!mccobjpriv->enable_runtime_duration)
+		goto exit;
+
+#ifdef CONFIG_P2P_PS
+	/* check noa enable or not */
+	for (i = 0; i < dvobj->iface_nums; i++) {
+		iface = dvobj->padapters[i];
+		if (iface->wdinfo.p2p_ps_mode == P2P_PS_NOA) {
+			noa_enable = _TRUE;
+			break;
+		}
+	}
+#endif /* CONFIG_P2P_PS */
+
+
+
+	if (type == MCC_DURATION_MAPPING) {
+		switch (*val) {
+			/* 0 = fair scheduling */
+			case 0:
+				mccobjpriv->duration= 40;
+				mccobjpriv->policy_index = 2;
+				mccobjpriv->mchan_sched_mode = MCC_FAIR_SCHEDULE;
+				break;
+			/* 1 = favor STA */
+			case 1:
+				mccobjpriv->duration= 70;
+				mccobjpriv->policy_index = 1;
+				mccobjpriv->mchan_sched_mode = MCC_FAVOE_STA;
+				break;
+			/* 2 = favor P2P*/
+			case 2:
+			default:
+				mccobjpriv->duration= 30;
+				mccobjpriv->policy_index = 0;
+				mccobjpriv->mchan_sched_mode = MCC_FAVOE_P2P;
+				break;
+		}
+	} else {
+		mccobjpriv->duration = *val;
+		rtw_hal_mcc_update_policy_table(adapter);
+	}
+
+	/* only update sw parameter under MCC 
+	    it will be force update during */
+	if (noa_enable)
+		goto exit;
+
+	if (rtw_hal_check_mcc_status(adapter, MCC_STATUS_DOING_MCC))
+		rtw_hal_mcc_update_parameter(adapter, _TRUE);
+exit:
+	return ret;
+}
+
+u8 rtw_set_mcc_duration_cmd(_adapter *adapter, u8 type, u8 val)
+{
+	struct cmd_obj *cmdobj;
+	struct drvextra_cmd_parm *pdrvextra_cmd_parm;
+	struct cmd_priv *pcmdpriv = &adapter->cmdpriv;
+	u8 *mcc_duration = NULL;
+	u8 res = _FAIL;
+
+	
+	cmdobj = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj));
+	if (cmdobj == NULL)
+		goto exit;
+
+	pdrvextra_cmd_parm = (struct drvextra_cmd_parm *)rtw_zmalloc(sizeof(struct drvextra_cmd_parm));
+	if (pdrvextra_cmd_parm == NULL) {
+		rtw_mfree((u8 *)cmdobj, sizeof(struct cmd_obj));
+		goto exit;
+	}
+
+	mcc_duration = rtw_zmalloc(sizeof(u8));
+	if (mcc_duration == NULL) {
+		rtw_mfree((u8 *)cmdobj, sizeof(struct cmd_obj));
+		rtw_mfree((u8 *)pdrvextra_cmd_parm, sizeof(struct drvextra_cmd_parm));
+		res = _FAIL;
+		goto exit;
+	}
+
+	pdrvextra_cmd_parm->ec_id = MCC_SET_DURATION_WK_CID;
+	pdrvextra_cmd_parm->type = type;
+	pdrvextra_cmd_parm->size = 1;
+	pdrvextra_cmd_parm->pbuf = mcc_duration;
+
+	_rtw_memcpy(mcc_duration, &val, 1);
+
+	init_h2fwcmd_w_parm_no_rsp(cmdobj, pdrvextra_cmd_parm, GEN_CMD_CODE(_Set_Drv_Extra));
+	res = rtw_enqueue_cmd(pcmdpriv, cmdobj);
+
+exit:
+	return res;
+}
+
+#endif /* CONFIG_MCC_MODE */
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/hal_mp.c linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/hal_mp.c
--- linux-5.6.3/3rdparty/rtl8821ce/hal/hal_mp.c	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/hal_mp.c	2020-04-10 16:35:06.790658854 +0300
@@ -0,0 +1,2396 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#define _HAL_MP_C_
+
+#include <drv_types.h>
+
+#ifdef CONFIG_MP_INCLUDED
+
+#ifdef RTW_HALMAC
+	#include <hal_data.h>		/* struct HAL_DATA_TYPE, RF register definition and etc. */
+#else /* !RTW_HALMAC */
+	#ifdef CONFIG_RTL8188E
+		#include <rtl8188e_hal.h>
+	#endif
+	#ifdef CONFIG_RTL8723B
+		#include <rtl8723b_hal.h>
+	#endif
+	#ifdef CONFIG_RTL8192E
+		#include <rtl8192e_hal.h>
+	#endif
+	#ifdef CONFIG_RTL8814A
+		#include <rtl8814a_hal.h>
+	#endif
+	#if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A)
+		#include <rtl8812a_hal.h>
+	#endif
+	#ifdef CONFIG_RTL8703B
+		#include <rtl8703b_hal.h>
+	#endif
+	#ifdef CONFIG_RTL8723D
+		#include <rtl8723d_hal.h>
+	#endif
+	#ifdef CONFIG_RTL8710B
+		#include <rtl8710b_hal.h>
+	#endif
+	#ifdef CONFIG_RTL8188F
+		#include <rtl8188f_hal.h>
+	#endif
+	#ifdef CONFIG_RTL8188GTV
+		#include <rtl8188gtv_hal.h>
+	#endif
+	#ifdef CONFIG_RTL8192F
+		#include <rtl8192f_hal.h>
+	#endif
+#endif /* !RTW_HALMAC */
+
+
+u8 MgntQuery_NssTxRate(u16 Rate)
+{
+	u8	NssNum = RF_TX_NUM_NONIMPLEMENT;
+
+	if ((Rate >= MGN_MCS8 && Rate <= MGN_MCS15) ||
+	    (Rate >= MGN_VHT2SS_MCS0 && Rate <= MGN_VHT2SS_MCS9))
+		NssNum = RF_2TX;
+	else if ((Rate >= MGN_MCS16 && Rate <= MGN_MCS23) ||
+		 (Rate >= MGN_VHT3SS_MCS0 && Rate <= MGN_VHT3SS_MCS9))
+		NssNum = RF_3TX;
+	else if ((Rate >= MGN_MCS24 && Rate <= MGN_MCS31) ||
+		 (Rate >= MGN_VHT4SS_MCS0 && Rate <= MGN_VHT4SS_MCS9))
+		NssNum = RF_4TX;
+	else
+		NssNum = RF_1TX;
+
+	return NssNum;
+}
+
+void hal_mpt_SwitchRfSetting(PADAPTER	pAdapter)
+{
+	HAL_DATA_TYPE		*pHalData = GET_HAL_DATA(pAdapter);
+	PMPT_CONTEXT		pMptCtx = &(pAdapter->mppriv.mpt_ctx);
+	u8				ChannelToSw = pMptCtx->MptChannelToSw;
+	ULONG				ulRateIdx = pMptCtx->mpt_rate_index;
+	ULONG				ulbandwidth = pMptCtx->MptBandWidth;
+
+	/* <20120525, Kordan> Dynamic mechanism for APK, asked by Dennis.*/
+	if (IS_HARDWARE_TYPE_8188ES(pAdapter) && (1 <= ChannelToSw && ChannelToSw <= 11) &&
+	    (ulRateIdx == MPT_RATE_MCS0 || ulRateIdx == MPT_RATE_1M || ulRateIdx == MPT_RATE_6M)) {
+		pMptCtx->backup0x52_RF_A = (u1Byte)phy_query_rf_reg(pAdapter, RF_PATH_A, RF_0x52, 0x000F0);
+		pMptCtx->backup0x52_RF_B = (u1Byte)phy_query_rf_reg(pAdapter, RF_PATH_B, RF_0x52, 0x000F0);
+
+		if ((PlatformEFIORead4Byte(pAdapter, 0xF4) & BIT29) == BIT29) {
+			phy_set_rf_reg(pAdapter, RF_PATH_A, RF_0x52, 0x000F0, 0xB);
+			phy_set_rf_reg(pAdapter, RF_PATH_B, RF_0x52, 0x000F0, 0xB);
+		} else {
+			phy_set_rf_reg(pAdapter, RF_PATH_A, RF_0x52, 0x000F0, 0xD);
+			phy_set_rf_reg(pAdapter, RF_PATH_B, RF_0x52, 0x000F0, 0xD);
+		}
+	} else if (IS_HARDWARE_TYPE_8188EE(pAdapter)) { /* <20140903, VincentL> Asked by RF Eason and Edlu*/
+		if (ChannelToSw == 3 && ulbandwidth == MPT_BW_40MHZ) {
+			phy_set_rf_reg(pAdapter, RF_PATH_A, RF_0x52, 0x000F0, 0xB); /*RF 0x52 = 0x0007E4BD*/
+			phy_set_rf_reg(pAdapter, RF_PATH_B, RF_0x52, 0x000F0, 0xB); /*RF 0x52 = 0x0007E4BD*/
+		} else {
+			phy_set_rf_reg(pAdapter, RF_PATH_A, RF_0x52, 0x000F0, 0x9); /*RF 0x52 = 0x0007E49D*/
+			phy_set_rf_reg(pAdapter, RF_PATH_B, RF_0x52, 0x000F0, 0x9); /*RF 0x52 = 0x0007E49D*/
+		}
+	} else if (IS_HARDWARE_TYPE_8188E(pAdapter)) {
+		phy_set_rf_reg(pAdapter, RF_PATH_A, RF_0x52, 0x000F0, pMptCtx->backup0x52_RF_A);
+		phy_set_rf_reg(pAdapter, RF_PATH_B, RF_0x52, 0x000F0, pMptCtx->backup0x52_RF_B);
+	}
+}
+
+s32 hal_mpt_SetPowerTracking(PADAPTER padapter, u8 enable)
+{
+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(padapter);
+	struct dm_struct		*pDM_Odm = &(pHalData->odmpriv);
+
+
+	if (!netif_running(padapter->pnetdev)) {
+		return _FAIL;
+	}
+
+	if (check_fwstate(&padapter->mlmepriv, WIFI_MP_STATE) == _FALSE) {
+		return _FAIL;
+	}
+	if (enable)
+		pDM_Odm->rf_calibrate_info.txpowertrack_control = _TRUE;
+	else
+		pDM_Odm->rf_calibrate_info.txpowertrack_control = _FALSE;
+
+	return _SUCCESS;
+}
+
+void hal_mpt_GetPowerTracking(PADAPTER padapter, u8 *enable)
+{
+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(padapter);
+	struct dm_struct		*pDM_Odm = &(pHalData->odmpriv);
+
+
+	*enable = pDM_Odm->rf_calibrate_info.txpowertrack_control;
+}
+
+
+void hal_mpt_CCKTxPowerAdjust(PADAPTER Adapter, BOOLEAN bInCH14)
+{
+	u32		TempVal = 0, TempVal2 = 0, TempVal3 = 0;
+	u32		CurrCCKSwingVal = 0, CCKSwingIndex = 12;
+	u8		i;
+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(Adapter);
+	PMPT_CONTEXT		pMptCtx = &(Adapter->mppriv.mpt_ctx);
+	u1Byte				u1Channel = pHalData->current_channel;
+	ULONG				ulRateIdx = pMptCtx->mpt_rate_index;
+	u1Byte				DataRate = 0xFF;
+
+	/* Do not modify CCK TX filter parameters for 8822B*/
+	if(IS_HARDWARE_TYPE_8822B(Adapter) || IS_HARDWARE_TYPE_8821C(Adapter) ||
+		IS_HARDWARE_TYPE_8723D(Adapter) || IS_HARDWARE_TYPE_8192F(Adapter))
+		return;
+
+	DataRate = mpt_to_mgnt_rate(ulRateIdx);
+
+	if (u1Channel == 14 && IS_CCK_RATE(DataRate))
+		pHalData->bCCKinCH14 = TRUE;
+	else
+		pHalData->bCCKinCH14 = FALSE;
+
+	if (IS_HARDWARE_TYPE_8703B(Adapter)) {
+		if ((u1Channel == 14) && IS_CCK_RATE(DataRate)) {
+			/* Channel 14 in CCK, need to set 0xA26~0xA29 to 0 for 8703B */
+			phy_set_bb_reg(Adapter, rCCK0_TxFilter2, bMaskHWord, 0);
+			phy_set_bb_reg(Adapter, rCCK0_DebugPort, bMaskLWord, 0);
+
+		} else {
+			/* Normal setting for 8703B, just recover to the default setting. */
+			/* This hardcore values reference from the parameter which BB team gave. */
+			for (i = 0 ; i < 2 ; ++i)
+				phy_set_bb_reg(Adapter, pHalData->RegForRecover[i].offset, bMaskDWord, pHalData->RegForRecover[i].value);
+
+		}
+	} else if (IS_HARDWARE_TYPE_8723D(Adapter)) {
+		/* 2.4G CCK TX DFIR */
+		/* 2016.01.20 Suggest from RS BB mingzhi*/
+		if ((u1Channel == 14)) {
+			phy_set_bb_reg(Adapter, rCCK0_TxFilter2, bMaskDWord, 0x0000B81C);
+			phy_set_bb_reg(Adapter, rCCK0_DebugPort, bMaskDWord, 0x00000000);
+			phy_set_bb_reg(Adapter, 0xAAC, bMaskDWord, 0x00003667);
+		} else {
+			for (i = 0 ; i < 3 ; ++i) {
+				phy_set_bb_reg(Adapter,
+					     pHalData->RegForRecover[i].offset,
+					     bMaskDWord,
+					     pHalData->RegForRecover[i].value);
+			}
+		}
+	} else if (IS_HARDWARE_TYPE_8188F(Adapter) || IS_HARDWARE_TYPE_8188GTV(Adapter)) {
+		/* get current cck swing value and check 0xa22 & 0xa23 later to match the table.*/
+		CurrCCKSwingVal = read_bbreg(Adapter, rCCK0_TxFilter1, bMaskHWord);
+		CCKSwingIndex = 20; /* default index */
+
+		if (!pHalData->bCCKinCH14) {
+			/* Readback the current bb cck swing value and compare with the table to */
+			/* get the current swing index */
+			for (i = 0; i < CCK_TABLE_SIZE_88F; i++) {
+				if (((CurrCCKSwingVal & 0xff) == (u32)cck_swing_table_ch1_ch13_88f[i][0]) &&
+				    (((CurrCCKSwingVal & 0xff00) >> 8) == (u32)cck_swing_table_ch1_ch13_88f[i][1])) {
+					CCKSwingIndex = i;
+					break;
+				}
+			}
+			write_bbreg(Adapter, 0xa22, bMaskByte0, cck_swing_table_ch1_ch13_88f[CCKSwingIndex][0]);
+			write_bbreg(Adapter, 0xa23, bMaskByte0, cck_swing_table_ch1_ch13_88f[CCKSwingIndex][1]);
+			write_bbreg(Adapter, 0xa24, bMaskByte0, cck_swing_table_ch1_ch13_88f[CCKSwingIndex][2]);
+			write_bbreg(Adapter, 0xa25, bMaskByte0, cck_swing_table_ch1_ch13_88f[CCKSwingIndex][3]);
+			write_bbreg(Adapter, 0xa26, bMaskByte0, cck_swing_table_ch1_ch13_88f[CCKSwingIndex][4]);
+			write_bbreg(Adapter, 0xa27, bMaskByte0, cck_swing_table_ch1_ch13_88f[CCKSwingIndex][5]);
+			write_bbreg(Adapter, 0xa28, bMaskByte0, cck_swing_table_ch1_ch13_88f[CCKSwingIndex][6]);
+			write_bbreg(Adapter, 0xa29, bMaskByte0, cck_swing_table_ch1_ch13_88f[CCKSwingIndex][7]);
+			write_bbreg(Adapter, 0xa9a, bMaskByte0, cck_swing_table_ch1_ch13_88f[CCKSwingIndex][8]);
+			write_bbreg(Adapter, 0xa9b, bMaskByte0, cck_swing_table_ch1_ch13_88f[CCKSwingIndex][9]);
+			write_bbreg(Adapter, 0xa9c, bMaskByte0, cck_swing_table_ch1_ch13_88f[CCKSwingIndex][10]);
+			write_bbreg(Adapter, 0xa9d, bMaskByte0, cck_swing_table_ch1_ch13_88f[CCKSwingIndex][11]);
+			write_bbreg(Adapter, 0xaa0, bMaskByte0, cck_swing_table_ch1_ch13_88f[CCKSwingIndex][12]);
+			write_bbreg(Adapter, 0xaa1, bMaskByte0, cck_swing_table_ch1_ch13_88f[CCKSwingIndex][13]);
+			write_bbreg(Adapter, 0xaa2, bMaskByte0, cck_swing_table_ch1_ch13_88f[CCKSwingIndex][14]);
+			write_bbreg(Adapter, 0xaa3, bMaskByte0, cck_swing_table_ch1_ch13_88f[CCKSwingIndex][15]);
+			RTW_INFO("%s , cck_swing_table_ch1_ch13_88f[%d]\n", __func__, CCKSwingIndex);
+		}  else {
+			for (i = 0; i < CCK_TABLE_SIZE_88F; i++) {
+				if (((CurrCCKSwingVal & 0xff) == (u32)cck_swing_table_ch14_88f[i][0]) &&
+				    (((CurrCCKSwingVal & 0xff00) >> 8) == (u32)cck_swing_table_ch14_88f[i][1])) {
+					CCKSwingIndex = i;
+					break;
+				}
+			}
+			write_bbreg(Adapter, 0xa22, bMaskByte0, cck_swing_table_ch14_88f[CCKSwingIndex][0]);
+			write_bbreg(Adapter, 0xa23, bMaskByte0, cck_swing_table_ch14_88f[CCKSwingIndex][1]);
+			write_bbreg(Adapter, 0xa24, bMaskByte0, cck_swing_table_ch14_88f[CCKSwingIndex][2]);
+			write_bbreg(Adapter, 0xa25, bMaskByte0, cck_swing_table_ch14_88f[CCKSwingIndex][3]);
+			write_bbreg(Adapter, 0xa26, bMaskByte0, cck_swing_table_ch14_88f[CCKSwingIndex][4]);
+			write_bbreg(Adapter, 0xa27, bMaskByte0, cck_swing_table_ch14_88f[CCKSwingIndex][5]);
+			write_bbreg(Adapter, 0xa28, bMaskByte0, cck_swing_table_ch14_88f[CCKSwingIndex][6]);
+			write_bbreg(Adapter, 0xa29, bMaskByte0, cck_swing_table_ch14_88f[CCKSwingIndex][7]);
+			write_bbreg(Adapter, 0xa9a, bMaskByte0, cck_swing_table_ch14_88f[CCKSwingIndex][8]);
+			write_bbreg(Adapter, 0xa9b, bMaskByte0, cck_swing_table_ch14_88f[CCKSwingIndex][9]);
+			write_bbreg(Adapter, 0xa9c, bMaskByte0, cck_swing_table_ch14_88f[CCKSwingIndex][10]);
+			write_bbreg(Adapter, 0xa9d, bMaskByte0, cck_swing_table_ch14_88f[CCKSwingIndex][11]);
+			write_bbreg(Adapter, 0xaa0, bMaskByte0, cck_swing_table_ch14_88f[CCKSwingIndex][12]);
+			write_bbreg(Adapter, 0xaa1, bMaskByte0, cck_swing_table_ch14_88f[CCKSwingIndex][13]);
+			write_bbreg(Adapter, 0xaa2, bMaskByte0, cck_swing_table_ch14_88f[CCKSwingIndex][14]);
+			write_bbreg(Adapter, 0xaa3, bMaskByte0, cck_swing_table_ch14_88f[CCKSwingIndex][15]);
+			RTW_INFO("%s , cck_swing_table_ch14_88f[%d]\n", __func__, CCKSwingIndex);
+		}
+	} else {
+
+		/* get current cck swing value and check 0xa22 & 0xa23 later to match the table.*/
+		CurrCCKSwingVal = read_bbreg(Adapter, rCCK0_TxFilter1, bMaskHWord);
+
+		if (!pHalData->bCCKinCH14) {
+			/* Readback the current bb cck swing value and compare with the table to */
+			/* get the current swing index */
+			for (i = 0; i < CCK_TABLE_SIZE; i++) {
+				if (((CurrCCKSwingVal & 0xff) == (u32)cck_swing_table_ch1_ch13[i][0]) &&
+				    (((CurrCCKSwingVal & 0xff00) >> 8) == (u32)cck_swing_table_ch1_ch13[i][1])) {
+					CCKSwingIndex = i;
+					break;
+				}
+			}
+
+			/*Write 0xa22 0xa23*/
+			TempVal = cck_swing_table_ch1_ch13[CCKSwingIndex][0] +
+				(cck_swing_table_ch1_ch13[CCKSwingIndex][1] << 8);
+
+
+			/*Write 0xa24 ~ 0xa27*/
+			TempVal2 = 0;
+			TempVal2 = cck_swing_table_ch1_ch13[CCKSwingIndex][2] +
+				(cck_swing_table_ch1_ch13[CCKSwingIndex][3] << 8) +
+				(cck_swing_table_ch1_ch13[CCKSwingIndex][4] << 16) +
+				(cck_swing_table_ch1_ch13[CCKSwingIndex][5] << 24);
+
+			/*Write 0xa28  0xa29*/
+			TempVal3 = 0;
+			TempVal3 = cck_swing_table_ch1_ch13[CCKSwingIndex][6] +
+				(cck_swing_table_ch1_ch13[CCKSwingIndex][7] << 8);
+		}  else {
+			for (i = 0; i < CCK_TABLE_SIZE; i++) {
+				if (((CurrCCKSwingVal & 0xff) == (u32)cck_swing_table_ch14[i][0]) &&
+				    (((CurrCCKSwingVal & 0xff00) >> 8) == (u32)cck_swing_table_ch14[i][1])) {
+					CCKSwingIndex = i;
+					break;
+				}
+			}
+
+			/*Write 0xa22 0xa23*/
+			TempVal = cck_swing_table_ch14[CCKSwingIndex][0] +
+				  (cck_swing_table_ch14[CCKSwingIndex][1] << 8);
+
+			/*Write 0xa24 ~ 0xa27*/
+			TempVal2 = 0;
+			TempVal2 = cck_swing_table_ch14[CCKSwingIndex][2] +
+				   (cck_swing_table_ch14[CCKSwingIndex][3] << 8) +
+				(cck_swing_table_ch14[CCKSwingIndex][4] << 16) +
+				   (cck_swing_table_ch14[CCKSwingIndex][5] << 24);
+
+			/*Write 0xa28  0xa29*/
+			TempVal3 = 0;
+			TempVal3 = cck_swing_table_ch14[CCKSwingIndex][6] +
+				   (cck_swing_table_ch14[CCKSwingIndex][7] << 8);
+		}
+
+		write_bbreg(Adapter, rCCK0_TxFilter1, bMaskHWord, TempVal);
+		write_bbreg(Adapter, rCCK0_TxFilter2, bMaskDWord, TempVal2);
+		write_bbreg(Adapter, rCCK0_DebugPort, bMaskLWord, TempVal3);
+	}
+
+}
+
+void hal_mpt_SetChannel(PADAPTER pAdapter)
+{
+	enum rf_path eRFPath;
+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(pAdapter);
+	struct dm_struct		*pDM_Odm = &(pHalData->odmpriv);
+	struct mp_priv	*pmp = &pAdapter->mppriv;
+	u8		channel = pmp->channel;
+	u8		bandwidth = pmp->bandwidth;
+
+	hal_mpt_SwitchRfSetting(pAdapter);
+
+	pHalData->bSwChnl = _TRUE;
+	pHalData->bSetChnlBW = _TRUE;
+
+#ifdef CONFIG_RTL8822B
+	if (bandwidth == 2) {
+		rtw_hal_set_chnl_bw(pAdapter, channel, bandwidth, HAL_PRIME_CHNL_OFFSET_LOWER, HAL_PRIME_CHNL_OFFSET_UPPER);
+	} else if (bandwidth == 1) {
+		rtw_hal_set_chnl_bw(pAdapter, channel, bandwidth, HAL_PRIME_CHNL_OFFSET_UPPER, 0);
+	} else
+#endif
+		rtw_hal_set_chnl_bw(pAdapter, channel, bandwidth, pmp->prime_channel_offset, 0);
+
+	hal_mpt_CCKTxPowerAdjust(pAdapter, pHalData->bCCKinCH14);
+	rtw_btcoex_wifionly_scan_notify(pAdapter);
+
+}
+
+/*
+ * Notice
+ *	Switch bandwitdth may change center frequency(channel)
+ */
+void hal_mpt_SetBandwidth(PADAPTER pAdapter)
+{
+	struct mp_priv *pmp = &pAdapter->mppriv;
+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(pAdapter);
+
+	u8		channel = pmp->channel;
+	u8		bandwidth = pmp->bandwidth;
+
+	pHalData->bSwChnl = _TRUE;
+	pHalData->bSetChnlBW = _TRUE;
+
+#ifdef CONFIG_RTL8822B
+	if (bandwidth == 2) {
+		rtw_hal_set_chnl_bw(pAdapter, channel, bandwidth, HAL_PRIME_CHNL_OFFSET_LOWER, HAL_PRIME_CHNL_OFFSET_UPPER);
+	} else if (bandwidth == 1) {
+		rtw_hal_set_chnl_bw(pAdapter, channel, bandwidth, HAL_PRIME_CHNL_OFFSET_UPPER, 0);
+	} else
+#endif
+		rtw_hal_set_chnl_bw(pAdapter, channel, bandwidth, pmp->prime_channel_offset, 0);
+
+	hal_mpt_SwitchRfSetting(pAdapter);
+	rtw_btcoex_wifionly_scan_notify(pAdapter);
+
+}
+
+void mpt_SetTxPower_Old(PADAPTER pAdapter, MPT_TXPWR_DEF Rate, u8 *pTxPower)
+{
+	switch (Rate) {
+	case MPT_CCK: {
+		u4Byte	TxAGC = 0, pwr = 0;
+		u1Byte	rf;
+
+		pwr = pTxPower[RF_PATH_A];
+		if (pwr < 0x3f) {
+			TxAGC = (pwr << 16) | (pwr << 8) | (pwr);
+			phy_set_bb_reg(pAdapter, rTxAGC_A_CCK1_Mcs32, bMaskByte1, pTxPower[RF_PATH_A]);
+			phy_set_bb_reg(pAdapter, rTxAGC_B_CCK11_A_CCK2_11, 0xffffff00, TxAGC);
+		}
+		pwr = pTxPower[RF_PATH_B];
+		if (pwr < 0x3f) {
+			TxAGC = (pwr << 16) | (pwr << 8) | (pwr);
+			phy_set_bb_reg(pAdapter, rTxAGC_B_CCK11_A_CCK2_11, bMaskByte0, pTxPower[RF_PATH_B]);
+			phy_set_bb_reg(pAdapter, rTxAGC_B_CCK1_55_Mcs32, 0xffffff00, TxAGC);
+		}
+	}
+	break;
+
+	case MPT_OFDM_AND_HT: {
+		u4Byte	TxAGC = 0;
+		u1Byte	pwr = 0, rf;
+
+		pwr = pTxPower[0];
+		if (pwr < 0x3f) {
+			TxAGC |= ((pwr << 24) | (pwr << 16) | (pwr << 8) | pwr);
+			RTW_INFO("HT Tx-rf(A) Power = 0x%x\n", TxAGC);
+			phy_set_bb_reg(pAdapter, rTxAGC_A_Rate18_06, bMaskDWord, TxAGC);
+			phy_set_bb_reg(pAdapter, rTxAGC_A_Rate54_24, bMaskDWord, TxAGC);
+			phy_set_bb_reg(pAdapter, rTxAGC_A_Mcs03_Mcs00, bMaskDWord, TxAGC);
+			phy_set_bb_reg(pAdapter, rTxAGC_A_Mcs07_Mcs04, bMaskDWord, TxAGC);
+			phy_set_bb_reg(pAdapter, rTxAGC_A_Mcs11_Mcs08, bMaskDWord, TxAGC);
+			phy_set_bb_reg(pAdapter, rTxAGC_A_Mcs15_Mcs12, bMaskDWord, TxAGC);
+		}
+		TxAGC = 0;
+		pwr = pTxPower[1];
+		if (pwr < 0x3f) {
+			TxAGC |= ((pwr << 24) | (pwr << 16) | (pwr << 8) | pwr);
+			RTW_INFO("HT Tx-rf(B) Power = 0x%x\n", TxAGC);
+			phy_set_bb_reg(pAdapter, rTxAGC_B_Rate18_06, bMaskDWord, TxAGC);
+			phy_set_bb_reg(pAdapter, rTxAGC_B_Rate54_24, bMaskDWord, TxAGC);
+			phy_set_bb_reg(pAdapter, rTxAGC_B_Mcs03_Mcs00, bMaskDWord, TxAGC);
+			phy_set_bb_reg(pAdapter, rTxAGC_B_Mcs07_Mcs04, bMaskDWord, TxAGC);
+			phy_set_bb_reg(pAdapter, rTxAGC_B_Mcs11_Mcs08, bMaskDWord, TxAGC);
+			phy_set_bb_reg(pAdapter, rTxAGC_B_Mcs15_Mcs12, bMaskDWord, TxAGC);
+		}
+	}
+	break;
+
+	default:
+		break;
+	}
+	RTW_INFO("<===mpt_SetTxPower_Old()\n");
+}
+
+void
+mpt_SetTxPower(
+	PADAPTER		pAdapter,
+	MPT_TXPWR_DEF	Rate,
+	pu1Byte	pTxPower
+)
+{
+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(pAdapter);
+
+	u1Byte path = 0 , i = 0, MaxRate = MGN_6M;
+	u1Byte StartPath = RF_PATH_A, EndPath = RF_PATH_B;
+
+	if (IS_HARDWARE_TYPE_8814A(pAdapter))
+		EndPath = RF_PATH_D;
+	else if (IS_HARDWARE_TYPE_8188F(pAdapter) || IS_HARDWARE_TYPE_8188GTV(pAdapter)
+		|| IS_HARDWARE_TYPE_8723D(pAdapter) || IS_HARDWARE_TYPE_8821C(pAdapter))
+		EndPath = RF_PATH_A;
+
+	switch (Rate) {
+	case MPT_CCK: {
+		u1Byte rate[] = {MGN_1M, MGN_2M, MGN_5_5M, MGN_11M};
+
+		for (path = StartPath; path <= EndPath; path++)
+			for (i = 0; i < sizeof(rate); ++i)
+				PHY_SetTxPowerIndex(pAdapter, pTxPower[path], path, rate[i]);
+	}
+	break;
+	case MPT_OFDM: {
+		u1Byte rate[] = {
+			MGN_6M, MGN_9M, MGN_12M, MGN_18M,
+			MGN_24M, MGN_36M, MGN_48M, MGN_54M,
+		};
+
+		for (path = StartPath; path <= EndPath; path++)
+			for (i = 0; i < sizeof(rate); ++i)
+				PHY_SetTxPowerIndex(pAdapter, pTxPower[path], path, rate[i]);
+	}
+	break;
+	case MPT_HT: {
+		u1Byte rate[] = {
+			MGN_MCS0, MGN_MCS1, MGN_MCS2, MGN_MCS3, MGN_MCS4,
+			MGN_MCS5, MGN_MCS6, MGN_MCS7, MGN_MCS8, MGN_MCS9,
+			MGN_MCS10, MGN_MCS11, MGN_MCS12, MGN_MCS13, MGN_MCS14,
+			MGN_MCS15, MGN_MCS16, MGN_MCS17, MGN_MCS18, MGN_MCS19,
+			MGN_MCS20, MGN_MCS21, MGN_MCS22, MGN_MCS23, MGN_MCS24,
+			MGN_MCS25, MGN_MCS26, MGN_MCS27, MGN_MCS28, MGN_MCS29,
+			MGN_MCS30, MGN_MCS31,
+		};
+		if (pHalData->rf_type == RF_3T3R)
+			MaxRate = MGN_MCS23;
+		else if (pHalData->rf_type == RF_2T2R)
+			MaxRate = MGN_MCS15;
+		else
+			MaxRate = MGN_MCS7;
+		for (path = StartPath; path <= EndPath; path++) {
+			for (i = 0; i < sizeof(rate); ++i) {
+				if (rate[i] > MaxRate)
+					break;
+				PHY_SetTxPowerIndex(pAdapter, pTxPower[path], path, rate[i]);
+			}
+		}
+	}
+	break;
+	case MPT_VHT: {
+		u1Byte rate[] = {
+			MGN_VHT1SS_MCS0, MGN_VHT1SS_MCS1, MGN_VHT1SS_MCS2, MGN_VHT1SS_MCS3, MGN_VHT1SS_MCS4,
+			MGN_VHT1SS_MCS5, MGN_VHT1SS_MCS6, MGN_VHT1SS_MCS7, MGN_VHT1SS_MCS8, MGN_VHT1SS_MCS9,
+			MGN_VHT2SS_MCS0, MGN_VHT2SS_MCS1, MGN_VHT2SS_MCS2, MGN_VHT2SS_MCS3, MGN_VHT2SS_MCS4,
+			MGN_VHT2SS_MCS5, MGN_VHT2SS_MCS6, MGN_VHT2SS_MCS7, MGN_VHT2SS_MCS8, MGN_VHT2SS_MCS9,
+			MGN_VHT3SS_MCS0, MGN_VHT3SS_MCS1, MGN_VHT3SS_MCS2, MGN_VHT3SS_MCS3, MGN_VHT3SS_MCS4,
+			MGN_VHT3SS_MCS5, MGN_VHT3SS_MCS6, MGN_VHT3SS_MCS7, MGN_VHT3SS_MCS8, MGN_VHT3SS_MCS9,
+			MGN_VHT4SS_MCS0, MGN_VHT4SS_MCS1, MGN_VHT4SS_MCS2, MGN_VHT4SS_MCS3, MGN_VHT4SS_MCS4,
+			MGN_VHT4SS_MCS5, MGN_VHT4SS_MCS6, MGN_VHT4SS_MCS7, MGN_VHT4SS_MCS8, MGN_VHT4SS_MCS9,
+		};
+		if (pHalData->rf_type == RF_3T3R)
+			MaxRate = MGN_VHT3SS_MCS9;
+		else if (pHalData->rf_type == RF_2T2R || pHalData->rf_type == RF_2T4R)
+			MaxRate = MGN_VHT2SS_MCS9;
+		else
+			MaxRate = MGN_VHT1SS_MCS9;
+
+		for (path = StartPath; path <= EndPath; path++) {
+			for (i = 0; i < sizeof(rate); ++i) {
+				if (rate[i] > MaxRate)
+					break;
+				PHY_SetTxPowerIndex(pAdapter, pTxPower[path], path, rate[i]);
+			}
+		}
+	}
+	break;
+	default:
+		RTW_INFO("<===mpt_SetTxPower: Illegal channel!!\n");
+		break;
+	}
+}
+
+void hal_mpt_SetTxPower(PADAPTER pAdapter)
+{
+	HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
+	PMPT_CONTEXT		pMptCtx = &(pAdapter->mppriv.mpt_ctx);
+	struct dm_struct		*pDM_Odm = &pHalData->odmpriv;
+
+	if (pHalData->rf_chip < RF_CHIP_MAX) {
+		if (IS_HARDWARE_TYPE_8188E(pAdapter) ||
+		    IS_HARDWARE_TYPE_8723B(pAdapter) ||
+		    IS_HARDWARE_TYPE_8192E(pAdapter) ||
+		    IS_HARDWARE_TYPE_8703B(pAdapter) ||
+		    IS_HARDWARE_TYPE_8188F(pAdapter) ||
+		    IS_HARDWARE_TYPE_8188GTV(pAdapter)
+		) {
+			u8 path = (pHalData->antenna_tx_path == ANTENNA_A) ? (RF_PATH_A) : (RF_PATH_B);
+
+			RTW_INFO("===> MPT_ProSetTxPower: Old\n");
+
+			mpt_SetTxPower_Old(pAdapter, MPT_CCK, pMptCtx->TxPwrLevel);
+			mpt_SetTxPower_Old(pAdapter, MPT_OFDM_AND_HT, pMptCtx->TxPwrLevel);
+
+		} else {
+
+			mpt_SetTxPower(pAdapter, MPT_CCK, pMptCtx->TxPwrLevel);
+			mpt_SetTxPower(pAdapter, MPT_OFDM, pMptCtx->TxPwrLevel);
+			mpt_SetTxPower(pAdapter, MPT_HT, pMptCtx->TxPwrLevel);
+			if(IS_HARDWARE_TYPE_JAGUAR(pAdapter)||IS_HARDWARE_TYPE_JAGUAR2(pAdapter)) {
+				RTW_INFO("===> MPT_ProSetTxPower: Jaguar/Jaguar2\n");
+				mpt_SetTxPower(pAdapter, MPT_VHT, pMptCtx->TxPwrLevel);
+			}
+		}
+	} else
+		RTW_INFO("RFChipID < RF_CHIP_MAX, the RF chip is not supported - %d\n", pHalData->rf_chip);
+
+	odm_clear_txpowertracking_state(pDM_Odm);
+}
+
+void hal_mpt_SetDataRate(PADAPTER pAdapter)
+{
+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(pAdapter);
+	PMPT_CONTEXT		pMptCtx = &(pAdapter->mppriv.mpt_ctx);
+	u32 DataRate;
+
+	DataRate = mpt_to_mgnt_rate(pMptCtx->mpt_rate_index);
+
+	hal_mpt_SwitchRfSetting(pAdapter);
+
+	hal_mpt_CCKTxPowerAdjust(pAdapter, pHalData->bCCKinCH14);
+#ifdef CONFIG_RTL8723B
+	if (IS_HARDWARE_TYPE_8723B(pAdapter)) {
+		if (IS_CCK_RATE(DataRate)) {
+			if (pMptCtx->mpt_rf_path == RF_PATH_A)
+				phy_set_rf_reg(pAdapter, RF_PATH_A, 0x51, 0xF, 0x6);
+			else
+				phy_set_rf_reg(pAdapter, RF_PATH_A, 0x71, 0xF, 0x6);
+		} else {
+			if (pMptCtx->mpt_rf_path == RF_PATH_A)
+				phy_set_rf_reg(pAdapter, RF_PATH_A, 0x51, 0xF, 0xE);
+			else
+				phy_set_rf_reg(pAdapter, RF_PATH_A, 0x71, 0xF, 0xE);
+		}
+	}
+
+	if ((IS_HARDWARE_TYPE_8723BS(pAdapter) &&
+	     ((pHalData->PackageType == PACKAGE_TFBGA79) || (pHalData->PackageType == PACKAGE_TFBGA90)))) {
+		if (pMptCtx->mpt_rf_path == RF_PATH_A)
+			phy_set_rf_reg(pAdapter, RF_PATH_A, 0x51, 0xF, 0xE);
+		else
+			phy_set_rf_reg(pAdapter, RF_PATH_A, 0x71, 0xF, 0xE);
+	}
+#endif
+}
+
+#define RF_PATH_AB	22
+
+#ifdef CONFIG_RTL8814A
+VOID mpt_ToggleIG_8814A(PADAPTER	pAdapter)
+{
+	u1Byte Path = 0;
+	u4Byte IGReg = rA_IGI_Jaguar, IGvalue = 0;
+
+	for (Path; Path <= RF_PATH_D; Path++) {
+		switch (Path) {
+		case RF_PATH_B:
+			IGReg = rB_IGI_Jaguar;
+			break;
+		case RF_PATH_C:
+			IGReg = rC_IGI_Jaguar2;
+			break;
+		case RF_PATH_D:
+			IGReg = rD_IGI_Jaguar2;
+			break;
+		default:
+			IGReg = rA_IGI_Jaguar;
+			break;
+		}
+
+		IGvalue = phy_query_bb_reg(pAdapter, IGReg, bMaskByte0);
+		phy_set_bb_reg(pAdapter, IGReg, bMaskByte0, IGvalue + 2);
+		phy_set_bb_reg(pAdapter, IGReg, bMaskByte0, IGvalue);
+	}
+}
+
+VOID mpt_SetRFPath_8814A(PADAPTER	pAdapter)
+{
+
+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(pAdapter);
+	PMPT_CONTEXT	pMptCtx = &pAdapter->mppriv.mpt_ctx;
+	R_ANTENNA_SELECT_OFDM	*p_ofdm_tx;	/* OFDM Tx register */
+	R_ANTENNA_SELECT_CCK	*p_cck_txrx;
+	u8	ForcedDataRate = mpt_to_mgnt_rate(pMptCtx->mpt_rate_index);
+	/*/PRT_HIGH_THROUGHPUT		pHTInfo = GET_HT_INFO(pMgntInfo);*/
+	/*/PRT_VERY_HIGH_THROUGHPUT	pVHTInfo = GET_VHT_INFO(pMgntInfo);*/
+
+	u32	ulAntennaTx = pHalData->antenna_tx_path;
+	u32	ulAntennaRx = pHalData->AntennaRxPath;
+	u8	NssforRate = MgntQuery_NssTxRate(ForcedDataRate);
+
+	if (NssforRate == RF_3TX) {
+		RTW_INFO("===> SetAntenna 3T Rate ForcedDataRate %d NssforRate %d AntennaTx %d\n", ForcedDataRate, NssforRate, ulAntennaTx);
+
+		switch (ulAntennaTx) {
+		case ANTENNA_BCD:
+			pMptCtx->mpt_rf_path = RF_PATH_BCD;
+			/*pHalData->ValidTxPath = 0x0e;*/
+			phy_set_bb_reg(pAdapter, rTxAnt_23Nsts_Jaguar2, 0x0fff0000, 0x90e);	/*/ 0x940[27:16]=12'b0010_0100_0111*/
+			break;
+
+		case ANTENNA_ABC:
+		default:
+			pMptCtx->mpt_rf_path = RF_PATH_ABC;
+			/*pHalData->ValidTxPath = 0x0d;*/
+			phy_set_bb_reg(pAdapter, rTxAnt_23Nsts_Jaguar2, 0x0fff0000, 0x247);	/*/ 0x940[27:16]=12'b0010_0100_0111*/
+			break;
+		}
+
+	} else { /*/if(NssforRate == RF_1TX)*/
+		RTW_INFO("===> SetAntenna for 1T/2T Rate, ForcedDataRate %d NssforRate %d AntennaTx %d\n", ForcedDataRate, NssforRate, ulAntennaTx);
+		switch (ulAntennaTx) {
+		case ANTENNA_BCD:
+			pMptCtx->mpt_rf_path = RF_PATH_BCD;
+			/*pHalData->ValidTxPath = 0x0e;*/
+			phy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, 0xf0000000, 0x7);
+			phy_set_bb_reg(pAdapter, rTxAnt_1Nsts_Jaguar2, 0x000f00000, 0xe);
+			phy_set_bb_reg(pAdapter, rTxPath_Jaguar, 0xf0, 0xe);
+			break;
+
+		case ANTENNA_BC:
+			pMptCtx->mpt_rf_path = RF_PATH_BC;
+			/*pHalData->ValidTxPath = 0x06;*/
+			phy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, 0xf0000000, 0x6);
+			phy_set_bb_reg(pAdapter, rTxAnt_1Nsts_Jaguar2, 0x000f00000, 0x6);
+			phy_set_bb_reg(pAdapter, rTxPath_Jaguar, 0xf0, 0x6);
+			break;
+		case ANTENNA_B:
+			pMptCtx->mpt_rf_path = RF_PATH_B;
+			/*pHalData->ValidTxPath = 0x02;*/
+			phy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, 0xf0000000, 0x4);			/*/ 0xa07[7:4] = 4'b0100*/
+			phy_set_bb_reg(pAdapter, rTxAnt_1Nsts_Jaguar2, 0xfff00000, 0x002);	/*/ 0x93C[31:20]=12'b0000_0000_0010*/
+			phy_set_bb_reg(pAdapter, rTxPath_Jaguar, 0xf0, 0x2);					/* 0x80C[7:4] = 4'b0010*/
+			break;
+
+		case ANTENNA_C:
+			pMptCtx->mpt_rf_path = RF_PATH_C;
+			/*pHalData->ValidTxPath = 0x04;*/
+			phy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, 0xf0000000, 0x2);			/*/ 0xa07[7:4] = 4'b0010*/
+			phy_set_bb_reg(pAdapter, rTxAnt_1Nsts_Jaguar2, 0xfff00000, 0x004);	/*/ 0x93C[31:20]=12'b0000_0000_0100*/
+			phy_set_bb_reg(pAdapter, rTxPath_Jaguar, 0xf0, 0x4);					/*/ 0x80C[7:4] = 4'b0100*/
+			break;
+
+		case ANTENNA_D:
+			pMptCtx->mpt_rf_path = RF_PATH_D;
+			/*pHalData->ValidTxPath = 0x08;*/
+			phy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, 0xf0000000, 0x1);			/*/ 0xa07[7:4] = 4'b0001*/
+			phy_set_bb_reg(pAdapter, rTxAnt_1Nsts_Jaguar2, 0xfff00000, 0x008);	/*/ 0x93C[31:20]=12'b0000_0000_1000*/
+			phy_set_bb_reg(pAdapter, rTxPath_Jaguar, 0xf0, 0x8);					/*/ 0x80C[7:4] = 4'b1000*/
+			break;
+
+		case ANTENNA_A:
+		default:
+			pMptCtx->mpt_rf_path = RF_PATH_A;
+			/*pHalData->ValidTxPath = 0x01;*/
+			phy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, 0xf0000000, 0x8);			/*/ 0xa07[7:4] = 4'b1000*/
+			phy_set_bb_reg(pAdapter, rTxAnt_1Nsts_Jaguar2, 0xfff00000, 0x001);	/*/ 0x93C[31:20]=12'b0000_0000_0001*/
+			phy_set_bb_reg(pAdapter, rTxPath_Jaguar, 0xf0, 0x1);					/*/ 0x80C[7:4] = 4'b0001*/
+			break;
+		}
+	}
+
+	switch (ulAntennaRx) {
+	case ANTENNA_A:
+		/*pHalData->ValidRxPath = 0x01;*/
+		phy_set_bb_reg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x1);
+		phy_set_bb_reg(pAdapter, 0x1000, bMaskByte2, 0x2);
+		phy_set_bb_reg(pAdapter, rRxPath_Jaguar, bMaskByte0, 0x11);
+		phy_set_bb_reg(pAdapter, 0x1000, bMaskByte2, 0x3);
+		phy_set_bb_reg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x0);
+		phy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, 0x0C000000, 0x0);
+		phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_A_0x0[19:16] = 3, RX mode*/
+		phy_set_rf_reg(pAdapter, RF_PATH_B, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_B_0x0[19:16] = 1, Standby mode*/
+		phy_set_rf_reg(pAdapter, RF_PATH_C, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_C_0x0[19:16] = 1, Standby mode*/
+		phy_set_rf_reg(pAdapter, RF_PATH_D, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_D_0x0[19:16] = 1, Standby mode*/
+		/*/ CCA related PD_delay_th*/
+		phy_set_bb_reg(pAdapter, rAGC_table_Jaguar, 0x0F000000, 0x5);
+		phy_set_bb_reg(pAdapter, rPwed_TH_Jaguar, 0x0000000F, 0xA);
+		break;
+
+	case ANTENNA_B:
+		/*pHalData->ValidRxPath = 0x02;*/
+		phy_set_bb_reg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x1);
+		phy_set_bb_reg(pAdapter, 0x1000, bMaskByte2, 0x2);
+		phy_set_bb_reg(pAdapter, rRxPath_Jaguar, bMaskByte0, 0x22);
+		phy_set_bb_reg(pAdapter, 0x1000, bMaskByte2, 0x3);
+		phy_set_bb_reg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x0);
+		phy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, 0x0C000000, 0x1);
+		phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_A_0x0[19:16] = 1, Standby mode*/
+		phy_set_rf_reg(pAdapter, RF_PATH_B, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_B_0x0[19:16] = 3, RX mode*/
+		phy_set_rf_reg(pAdapter, RF_PATH_C, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_C_0x0[19:16] = 1, Standby mode*/
+		phy_set_rf_reg(pAdapter, RF_PATH_D, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_D_0x0[19:16] = 1, Standby mode*/
+		/*/ CCA related PD_delay_th*/
+		phy_set_bb_reg(pAdapter, rAGC_table_Jaguar, 0x0F000000, 0x5);
+		phy_set_bb_reg(pAdapter, rPwed_TH_Jaguar, 0x0000000F, 0xA);
+		break;
+
+	case ANTENNA_C:
+		/*pHalData->ValidRxPath = 0x04;*/
+		phy_set_bb_reg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x1);
+		phy_set_bb_reg(pAdapter, 0x1000, bMaskByte2, 0x2);
+		phy_set_bb_reg(pAdapter, rRxPath_Jaguar, bMaskByte0, 0x44);
+		phy_set_bb_reg(pAdapter, 0x1000, bMaskByte2, 0x3);
+		phy_set_bb_reg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x0);
+		phy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, 0x0C000000, 0x2);
+		phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_A_0x0[19:16] = 1, Standby mode*/
+		phy_set_rf_reg(pAdapter, RF_PATH_B, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_B_0x0[19:16] = 1, Standby mode*/
+		phy_set_rf_reg(pAdapter, RF_PATH_C, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_C_0x0[19:16] = 3, RX mode*/
+		phy_set_rf_reg(pAdapter, RF_PATH_D, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_D_0x0[19:16] = 1, Standby mode*/
+		/*/ CCA related PD_delay_th*/
+		phy_set_bb_reg(pAdapter, rAGC_table_Jaguar, 0x0F000000, 0x5);
+		phy_set_bb_reg(pAdapter, rPwed_TH_Jaguar, 0x0000000F, 0xA);
+		break;
+
+	case ANTENNA_D:
+		/*pHalData->ValidRxPath = 0x08;*/
+		phy_set_bb_reg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x1);
+		phy_set_bb_reg(pAdapter, 0x1000, bMaskByte2, 0x2);
+		phy_set_bb_reg(pAdapter, rRxPath_Jaguar, bMaskByte0, 0x88);
+		phy_set_bb_reg(pAdapter, 0x1000, bMaskByte2, 0x3);
+		phy_set_bb_reg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x0);
+		phy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, 0x0C000000, 0x3);
+		phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_A_0x0[19:16] = 1, Standby mode*/
+		phy_set_rf_reg(pAdapter, RF_PATH_B, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_B_0x0[19:16] = 1, Standby mode*/
+		phy_set_rf_reg(pAdapter, RF_PATH_C, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_C_0x0[19:16] = 1, Standby mode*/
+		phy_set_rf_reg(pAdapter, RF_PATH_D, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_D_0x0[19:16] = 3, RX mode*/
+		/*/ CCA related PD_delay_th*/
+		phy_set_bb_reg(pAdapter, rAGC_table_Jaguar, 0x0F000000, 0x5);
+		phy_set_bb_reg(pAdapter, rPwed_TH_Jaguar, 0x0000000F, 0xA);
+		break;
+
+	case ANTENNA_BC:
+		/*pHalData->ValidRxPath = 0x06;*/
+		phy_set_bb_reg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x1);
+		phy_set_bb_reg(pAdapter, 0x1000, bMaskByte2, 0x2);
+		phy_set_bb_reg(pAdapter, rRxPath_Jaguar, bMaskByte0, 0x66);
+		phy_set_bb_reg(pAdapter, 0x1000, bMaskByte2, 0x3);
+		phy_set_bb_reg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x0);
+		phy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, 0x0f000000, 0x6);
+		phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_A_0x0[19:16] = 1, Standby mode*/
+		phy_set_rf_reg(pAdapter, RF_PATH_B, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_B_0x0[19:16] = 3, RX mode*/
+		phy_set_rf_reg(pAdapter, RF_PATH_C, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_C_0x0[19:16] = 3, Rx mode*/
+		phy_set_rf_reg(pAdapter, RF_PATH_D, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_D_0x0[19:16] = 1, Standby mode*/
+		/*/ CCA related PD_delay_th*/
+		phy_set_bb_reg(pAdapter, rAGC_table_Jaguar, 0x0F000000, 0x5);
+		phy_set_bb_reg(pAdapter, rPwed_TH_Jaguar, 0x0000000F, 0xA);
+		break;
+
+	case ANTENNA_CD:
+		/*pHalData->ValidRxPath = 0x0C;*/
+		phy_set_bb_reg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x1);
+		phy_set_bb_reg(pAdapter, 0x1000, bMaskByte2, 0x2);
+		phy_set_bb_reg(pAdapter, rRxPath_Jaguar, bMaskByte0, 0xcc);
+		phy_set_bb_reg(pAdapter, 0x1000, bMaskByte2, 0x3);
+		phy_set_bb_reg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x0);
+		phy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, 0x0f000000, 0xB);
+		phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_A_0x0[19:16] = 1, Standby mode*/
+		phy_set_rf_reg(pAdapter, RF_PATH_B, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_B_0x0[19:16] = 1, Standby mode*/
+		phy_set_rf_reg(pAdapter, RF_PATH_C, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_C_0x0[19:16] = 3, Rx mode*/
+		phy_set_rf_reg(pAdapter, RF_PATH_D, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_D_0x0[19:16] = 3, RX mode*/
+		/*/ CCA related PD_delay_th*/
+		phy_set_bb_reg(pAdapter, rAGC_table_Jaguar, 0x0F000000, 0x5);
+		phy_set_bb_reg(pAdapter, rPwed_TH_Jaguar, 0x0000000F, 0xA);
+		break;
+
+	case ANTENNA_BCD:
+		/*pHalData->ValidRxPath = 0x0e;*/
+		phy_set_bb_reg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x1);
+		phy_set_bb_reg(pAdapter, 0x1000, bMaskByte2, 0x2);
+		phy_set_bb_reg(pAdapter, rRxPath_Jaguar, bMaskByte0, 0xee);
+		phy_set_bb_reg(pAdapter, 0x1000, bMaskByte2, 0x3);
+		phy_set_bb_reg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x0);
+		phy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, 0x0f000000, 0x6);
+		phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_A_0x0[19:16] = 1, Standby mode*/
+		phy_set_rf_reg(pAdapter, RF_PATH_B, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_B_0x0[19:16] = 3, RX mode*/
+		phy_set_rf_reg(pAdapter, RF_PATH_C, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_C_0x0[19:16] = 3, RX mode*/
+		phy_set_rf_reg(pAdapter, RF_PATH_D, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_D_0x0[19:16] = 3, Rx mode*/
+		/*/ CCA related PD_delay_th*/
+		phy_set_bb_reg(pAdapter, rAGC_table_Jaguar, 0x0F000000, 0x3);
+		phy_set_bb_reg(pAdapter, rPwed_TH_Jaguar, 0x0000000F, 0x8);
+		break;
+
+	case ANTENNA_ABCD:
+		/*pHalData->ValidRxPath = 0x0f;*/
+		phy_set_bb_reg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x1);
+		phy_set_bb_reg(pAdapter, 0x1000, bMaskByte2, 0x2);
+		phy_set_bb_reg(pAdapter, rRxPath_Jaguar, bMaskByte0, 0xff);
+		phy_set_bb_reg(pAdapter, 0x1000, bMaskByte2, 0x3);
+		phy_set_bb_reg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x0);
+		phy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, 0x0f000000, 0x1);
+		phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_A_0x0[19:16] = 3, RX mode*/
+		phy_set_rf_reg(pAdapter, RF_PATH_B, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_B_0x0[19:16] = 3, RX mode*/
+		phy_set_rf_reg(pAdapter, RF_PATH_C, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_C_0x0[19:16] = 3, RX mode*/
+		phy_set_rf_reg(pAdapter, RF_PATH_D, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_D_0x0[19:16] = 3, RX mode*/
+		/*/ CCA related PD_delay_th*/
+		phy_set_bb_reg(pAdapter, rAGC_table_Jaguar, 0x0F000000, 0x3);
+		phy_set_bb_reg(pAdapter, rPwed_TH_Jaguar, 0x0000000F, 0x8);
+		break;
+
+	default:
+		break;
+	}
+
+	PHY_Set_SecCCATH_by_RXANT_8814A(pAdapter, ulAntennaRx);
+
+	mpt_ToggleIG_8814A(pAdapter);
+}
+#endif /* CONFIG_RTL8814A */
+#if defined(CONFIG_RTL8814A) || defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C)
+VOID
+mpt_SetSingleTone_8814A(
+	IN	PADAPTER	pAdapter,
+	IN	BOOLEAN	bSingleTone,
+	IN	BOOLEAN	bEnPMacTx)
+{
+
+	PMPT_CONTEXT	pMptCtx = &(pAdapter->mppriv.mpt_ctx);
+	u1Byte StartPath = RF_PATH_A,  EndPath = RF_PATH_A;
+	static u4Byte		regIG0 = 0, regIG1 = 0, regIG2 = 0, regIG3 = 0;
+
+	if (bSingleTone) {
+		regIG0 = phy_query_bb_reg(pAdapter, rA_TxScale_Jaguar, bMaskDWord);		/*/ 0xC1C[31:21]*/
+		regIG1 = phy_query_bb_reg(pAdapter, rB_TxScale_Jaguar, bMaskDWord);		/*/ 0xE1C[31:21]*/
+		regIG2 = phy_query_bb_reg(pAdapter, rC_TxScale_Jaguar2, bMaskDWord);	/*/ 0x181C[31:21]*/
+		regIG3 = phy_query_bb_reg(pAdapter, rD_TxScale_Jaguar2, bMaskDWord);	/*/ 0x1A1C[31:21]*/
+
+		switch (pMptCtx->mpt_rf_path) {
+		case RF_PATH_A:
+		case RF_PATH_B:
+		case RF_PATH_C:
+		case RF_PATH_D:
+			StartPath = pMptCtx->mpt_rf_path;
+			EndPath = pMptCtx->mpt_rf_path;
+			break;
+		case RF_PATH_AB:
+			EndPath = RF_PATH_B;
+			break;
+		case RF_PATH_BC:
+			StartPath = RF_PATH_B;
+			EndPath = RF_PATH_C;
+			break;
+		case RF_PATH_ABC:
+			EndPath = RF_PATH_C;
+			break;
+		case RF_PATH_BCD:
+			StartPath = RF_PATH_B;
+			EndPath = RF_PATH_D;
+			break;
+		case RF_PATH_ABCD:
+			EndPath = RF_PATH_D;
+			break;
+		}
+
+		if (bEnPMacTx == FALSE) {
+			hal_mpt_SetContinuousTx(pAdapter, _TRUE);
+			issue_nulldata(pAdapter, NULL, 1, 3, 500);
+		}
+
+		phy_set_bb_reg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x1); /*/ Disable CCA*/
+
+		for (StartPath; StartPath <= EndPath; StartPath++) {
+			phy_set_rf_reg(pAdapter, StartPath, RF_AC_Jaguar, 0xF0000, 0x2); /*/ Tx mode: RF0x00[19:16]=4'b0010 */
+			phy_set_rf_reg(pAdapter, StartPath, RF_AC_Jaguar, 0x1F, 0x0); /*/ Lowest RF gain index: RF_0x0[4:0] = 0*/
+
+			phy_set_rf_reg(pAdapter, StartPath, lna_low_gain_3, BIT1, 0x1); /*/ RF LO enabled*/
+		}
+
+		phy_set_bb_reg(pAdapter, rA_TxScale_Jaguar, 0xFFE00000, 0); /*/ 0xC1C[31:21]*/
+		phy_set_bb_reg(pAdapter, rB_TxScale_Jaguar, 0xFFE00000, 0); /*/ 0xE1C[31:21]*/
+		phy_set_bb_reg(pAdapter, rC_TxScale_Jaguar2, 0xFFE00000, 0); /*/ 0x181C[31:21]*/
+		phy_set_bb_reg(pAdapter, rD_TxScale_Jaguar2, 0xFFE00000, 0); /*/ 0x1A1C[31:21]*/
+	} else {
+		switch (pMptCtx->mpt_rf_path) {
+		case RF_PATH_A:
+		case RF_PATH_B:
+		case RF_PATH_C:
+		case RF_PATH_D:
+			StartPath = pMptCtx->mpt_rf_path;
+			EndPath = pMptCtx->mpt_rf_path;
+			break;
+		case RF_PATH_AB:
+			EndPath = RF_PATH_B;
+			break;
+		case RF_PATH_BC:
+			StartPath = RF_PATH_B;
+			EndPath = RF_PATH_C;
+			break;
+		case RF_PATH_ABC:
+			EndPath = RF_PATH_C;
+			break;
+		case RF_PATH_BCD:
+			StartPath = RF_PATH_B;
+			EndPath = RF_PATH_D;
+			break;
+		case RF_PATH_ABCD:
+			EndPath = RF_PATH_D;
+			break;
+		}
+		for (StartPath; StartPath <= EndPath; StartPath++)
+			phy_set_rf_reg(pAdapter, StartPath, lna_low_gain_3, BIT1, 0x0); /* RF LO disabled */
+
+		phy_set_bb_reg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x0); /* Enable CCA*/
+
+		if (bEnPMacTx == FALSE)
+			hal_mpt_SetContinuousTx(pAdapter, _FALSE);
+
+		phy_set_bb_reg(pAdapter, rA_TxScale_Jaguar, bMaskDWord, regIG0); /* 0xC1C[31:21]*/
+		phy_set_bb_reg(pAdapter, rB_TxScale_Jaguar, bMaskDWord, regIG1); /* 0xE1C[31:21]*/
+		phy_set_bb_reg(pAdapter, rC_TxScale_Jaguar2, bMaskDWord, regIG2); /* 0x181C[31:21]*/
+		phy_set_bb_reg(pAdapter, rD_TxScale_Jaguar2, bMaskDWord, regIG3); /* 0x1A1C[31:21]*/
+	}
+}
+
+#endif
+
+#if	defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A)
+void mpt_SetRFPath_8812A(PADAPTER pAdapter)
+{
+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(pAdapter);
+	PMPT_CONTEXT	pMptCtx = &pAdapter->mppriv.mpt_ctx;
+	struct mp_priv *pmp = &pAdapter->mppriv;
+	u8		channel = pmp->channel;
+	u8		bandwidth = pmp->bandwidth;
+	u8		eLNA_2g = pHalData->ExternalLNA_2G;
+	u32		ulAntennaTx, ulAntennaRx;
+
+	ulAntennaTx = pHalData->antenna_tx_path;
+	ulAntennaRx = pHalData->AntennaRxPath;
+
+	switch (ulAntennaTx) {
+	case ANTENNA_A:
+		pMptCtx->mpt_rf_path = RF_PATH_A;
+		phy_set_bb_reg(pAdapter, rTxPath_Jaguar, bMaskLWord, 0x1111);
+		if (pHalData->rfe_type == 3 && IS_HARDWARE_TYPE_8812(pAdapter))
+			phy_set_bb_reg(pAdapter, r_ANTSEL_SW_Jaguar, bMask_AntselPathFollow_Jaguar, 0x0);
+		break;
+	case ANTENNA_B:
+		pMptCtx->mpt_rf_path = RF_PATH_B;
+		phy_set_bb_reg(pAdapter, rTxPath_Jaguar, bMaskLWord, 0x2222);
+		if (pHalData->rfe_type == 3 && IS_HARDWARE_TYPE_8812(pAdapter))
+			phy_set_bb_reg(pAdapter,	r_ANTSEL_SW_Jaguar, bMask_AntselPathFollow_Jaguar, 0x1);
+		break;
+	case ANTENNA_AB:
+		pMptCtx->mpt_rf_path = RF_PATH_AB;
+		phy_set_bb_reg(pAdapter, rTxPath_Jaguar, bMaskLWord, 0x3333);
+		if (pHalData->rfe_type == 3 && IS_HARDWARE_TYPE_8812(pAdapter))
+			phy_set_bb_reg(pAdapter, r_ANTSEL_SW_Jaguar, bMask_AntselPathFollow_Jaguar, 0x0);
+		break;
+	default:
+		pMptCtx->mpt_rf_path = RF_PATH_AB;
+		RTW_INFO("Unknown Tx antenna.\n");
+		break;
+	}
+
+	switch (ulAntennaRx) {
+		u32 reg0xC50 = 0;
+	case ANTENNA_A:
+		phy_set_bb_reg(pAdapter, rRxPath_Jaguar, bMaskByte0, 0x11);
+		phy_set_rf_reg(pAdapter, RF_PATH_B, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_B_0x0[19:16] = 1, Standby mode*/
+		phy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, bCCK_RX_Jaguar, 0x0);
+		phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC_Jaguar, BIT19 | BIT18 | BIT17 | BIT16, 0x3);
+
+		/*/ <20121101, Kordan> To prevent gain table from not switched, asked by Ynlin.*/
+		reg0xC50 = phy_query_bb_reg(pAdapter, rA_IGI_Jaguar, bMaskByte0);
+		phy_set_bb_reg(pAdapter, rA_IGI_Jaguar, bMaskByte0, reg0xC50 + 2);
+		phy_set_bb_reg(pAdapter, rA_IGI_Jaguar, bMaskByte0, reg0xC50);
+
+		/* set PWED_TH for BB Yn user guide R29 */
+		if (IS_HARDWARE_TYPE_8812(pAdapter)) {
+			if (channel <= 14) { /* 2.4G */
+				if (bandwidth == CHANNEL_WIDTH_20
+				    && eLNA_2g == 0) {
+					/* 0x830[3:1]=3'b010 */
+					phy_set_bb_reg(pAdapter, rPwed_TH_Jaguar, BIT1 | BIT2 | BIT3, 0x02);
+				} else
+					/* 0x830[3:1]=3'b100 */
+					phy_set_bb_reg(pAdapter, rPwed_TH_Jaguar, BIT1 | BIT2 | BIT3, 0x04);
+			} else
+				/* 0x830[3:1]=3'b100 for 5G */
+				phy_set_bb_reg(pAdapter, rPwed_TH_Jaguar, BIT1 | BIT2 | BIT3, 0x04);
+		}
+		break;
+	case ANTENNA_B:
+		phy_set_bb_reg(pAdapter, rRxPath_Jaguar, bMaskByte0, 0x22);
+		phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC_Jaguar, 0xF0000, 0x1);/*/ RF_A_0x0[19:16] = 1, Standby mode */
+		phy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, bCCK_RX_Jaguar, 0x1);
+		phy_set_rf_reg(pAdapter, RF_PATH_B, RF_AC_Jaguar, BIT19 | BIT18 | BIT17 | BIT16, 0x3);
+
+		/*/ <20121101, Kordan> To prevent gain table from not switched, asked by Ynlin.*/
+		reg0xC50 = phy_query_bb_reg(pAdapter, rB_IGI_Jaguar, bMaskByte0);
+		phy_set_bb_reg(pAdapter, rB_IGI_Jaguar, bMaskByte0, reg0xC50 + 2);
+		phy_set_bb_reg(pAdapter, rB_IGI_Jaguar, bMaskByte0, reg0xC50);
+
+		/* set PWED_TH for BB Yn user guide R29 */
+		if (IS_HARDWARE_TYPE_8812(pAdapter)) {
+			if (channel <= 14) {
+				if (bandwidth == CHANNEL_WIDTH_20
+				    && eLNA_2g == 0) {
+					/* 0x830[3:1]=3'b010 */
+					phy_set_bb_reg(pAdapter, rPwed_TH_Jaguar, BIT1 | BIT2 | BIT3, 0x02);
+				} else
+					/* 0x830[3:1]=3'b100 */
+					phy_set_bb_reg(pAdapter, rPwed_TH_Jaguar, BIT1 | BIT2 | BIT3, 0x04);
+			} else
+				/* 0x830[3:1]=3'b100 for 5G */
+				phy_set_bb_reg(pAdapter, rPwed_TH_Jaguar, BIT1 | BIT2 | BIT3, 0x04);
+		}
+		break;
+	case ANTENNA_AB:
+		phy_set_bb_reg(pAdapter, rRxPath_Jaguar, bMaskByte0, 0x33);
+		phy_set_rf_reg(pAdapter, RF_PATH_B, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_B_0x0[19:16] = 3, Rx mode*/
+		phy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, bCCK_RX_Jaguar, 0x0);
+		/* set PWED_TH for BB Yn user guide R29 */
+		phy_set_bb_reg(pAdapter, rPwed_TH_Jaguar, BIT1 | BIT2 | BIT3, 0x04);
+		break;
+	default:
+		RTW_INFO("Unknown Rx antenna.\n");
+		break;
+	}
+
+	if (pHalData->rfe_type == 5 || pHalData->rfe_type == 1) {
+		if (ulAntennaTx == ANTENNA_A || ulAntennaTx == ANTENNA_AB) {
+			/* WiFi */
+			phy_set_bb_reg(pAdapter, r_ANTSEL_SW_Jaguar, BIT(1) | BIT(0), 0x2);
+			phy_set_bb_reg(pAdapter, r_ANTSEL_SW_Jaguar, BIT(9) | BIT(8), 0x3);
+		} else {
+			/* BT */
+			phy_set_bb_reg(pAdapter, r_ANTSEL_SW_Jaguar, BIT(1) | BIT(0), 0x1);
+			phy_set_bb_reg(pAdapter, r_ANTSEL_SW_Jaguar, BIT(9) | BIT(8), 0x3);
+		}
+	}
+}
+#endif
+
+#ifdef CONFIG_RTL8723B
+void mpt_SetRFPath_8723B(PADAPTER pAdapter)
+{
+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(pAdapter);
+	u32		ulAntennaTx, ulAntennaRx;
+	PMPT_CONTEXT	pMptCtx = &(pAdapter->mppriv.mpt_ctx);
+	struct dm_struct	*pDM_Odm = &pHalData->odmpriv;
+	struct dm_rf_calibration_struct	*pRFCalibrateInfo = &(pDM_Odm->rf_calibrate_info);
+
+	ulAntennaTx = pHalData->antenna_tx_path;
+	ulAntennaRx = pHalData->AntennaRxPath;
+
+	if (pHalData->rf_chip >= RF_CHIP_MAX) {
+		RTW_INFO("This RF chip ID is not supported\n");
+		return;
+	}
+
+	switch (pAdapter->mppriv.antenna_tx) {
+		u8 p = 0, i = 0;
+	case ANTENNA_A: { /*/ Actually path S1  (Wi-Fi)*/
+		pMptCtx->mpt_rf_path = RF_PATH_A;
+		phy_set_bb_reg(pAdapter, rS0S1_PathSwitch, BIT9 | BIT8 | BIT7, 0x0);
+		phy_set_bb_reg(pAdapter, 0xB2C, BIT31, 0x0); /* AGC Table Sel*/
+
+		for (i = 0; i < 3; ++i) {
+			u4Byte offset = pRFCalibrateInfo->tx_iqc_8723b[RF_PATH_A][i][0];
+			u4Byte data = pRFCalibrateInfo->tx_iqc_8723b[RF_PATH_A][i][1];
+
+			if (offset != 0) {
+				phy_set_bb_reg(pAdapter, offset, bMaskDWord, data);
+				RTW_INFO("Switch to S1 TxIQC(offset, data) = (0x%X, 0x%X)\n", offset, data);
+			}
+		}
+		for (i = 0; i < 2; ++i) {
+			u4Byte offset = pRFCalibrateInfo->rx_iqc_8723b[RF_PATH_A][i][0];
+			u4Byte data = pRFCalibrateInfo->rx_iqc_8723b[RF_PATH_A][i][1];
+
+			if (offset != 0) {
+				phy_set_bb_reg(pAdapter, offset, bMaskDWord, data);
+				RTW_INFO("Switch to S1 RxIQC (offset, data) = (0x%X, 0x%X)\n", offset, data);
+			}
+		}
+	}
+	break;
+	case ANTENNA_B: { /*/ Actually path S0 (BT)*/
+		u4Byte offset;
+		u4Byte data;
+
+		pMptCtx->mpt_rf_path = RF_PATH_B;
+		phy_set_bb_reg(pAdapter, rS0S1_PathSwitch, BIT9 | BIT8 | BIT7, 0x5);
+		phy_set_bb_reg(pAdapter, 0xB2C, BIT31, 0x1); /*/ AGC Table Sel.*/
+
+		for (i = 0; i < 3; ++i) {
+			/*/ <20130603, Kordan> Because BB suppors only 1T1R, we restore IQC  to S1 instead of S0.*/
+			offset = pRFCalibrateInfo->tx_iqc_8723b[RF_PATH_A][i][0];
+			data = pRFCalibrateInfo->tx_iqc_8723b[RF_PATH_B][i][1];
+			if (pRFCalibrateInfo->tx_iqc_8723b[RF_PATH_B][i][0] != 0) {
+				phy_set_bb_reg(pAdapter, offset, bMaskDWord, data);
+				RTW_INFO("Switch to S0 TxIQC (offset, data) = (0x%X, 0x%X)\n", offset, data);
+			}
+		}
+		/*/ <20130603, Kordan> Because BB suppors only 1T1R, we restore IQC to S1 instead of S0.*/
+		for (i = 0; i < 2; ++i) {
+			offset = pRFCalibrateInfo->rx_iqc_8723b[RF_PATH_A][i][0];
+			data = pRFCalibrateInfo->rx_iqc_8723b[RF_PATH_B][i][1];
+			if (pRFCalibrateInfo->rx_iqc_8723b[RF_PATH_B][i][0] != 0) {
+				phy_set_bb_reg(pAdapter, offset, bMaskDWord, data);
+				RTW_INFO("Switch to S0 RxIQC (offset, data) = (0x%X, 0x%X)\n", offset, data);
+			}
+		}
+	}
+	break;
+	default:
+		pMptCtx->mpt_rf_path = RF_PATH_AB;
+		break;
+	}
+}
+#endif
+
+#ifdef CONFIG_RTL8703B
+void mpt_SetRFPath_8703B(PADAPTER pAdapter)
+{
+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(pAdapter);
+	u4Byte					ulAntennaTx, ulAntennaRx;
+	PMPT_CONTEXT		pMptCtx = &(pAdapter->mppriv.mpt_ctx);
+	struct dm_struct		*pDM_Odm = &pHalData->odmpriv;
+	struct dm_rf_calibration_struct			*pRFCalibrateInfo = &(pDM_Odm->rf_calibrate_info);
+
+	ulAntennaTx = pHalData->antenna_tx_path;
+	ulAntennaRx = pHalData->AntennaRxPath;
+
+	if (pHalData->rf_chip >= RF_CHIP_MAX) {
+		RTW_INFO("This RF chip ID is not supported\n");
+		return;
+	}
+
+	switch (pAdapter->mppriv.antenna_tx) {
+		u1Byte p = 0, i = 0;
+
+	case ANTENNA_A: { /* Actually path S1  (Wi-Fi) */
+		pMptCtx->mpt_rf_path = RF_PATH_A;
+		phy_set_bb_reg(pAdapter, rS0S1_PathSwitch, BIT9 | BIT8 | BIT7, 0x0);
+		phy_set_bb_reg(pAdapter, 0xB2C, BIT31, 0x0); /* AGC Table Sel*/
+
+		for (i = 0; i < 3; ++i) {
+			u4Byte offset = pRFCalibrateInfo->tx_iqc_8703b[i][0];
+			u4Byte data = pRFCalibrateInfo->tx_iqc_8703b[i][1];
+
+			if (offset != 0) {
+				phy_set_bb_reg(pAdapter, offset, bMaskDWord, data);
+				RTW_INFO("Switch to S1 TxIQC(offset, data) = (0x%X, 0x%X)\n", offset, data);
+			}
+
+		}
+		for (i = 0; i < 2; ++i) {
+			u4Byte offset = pRFCalibrateInfo->rx_iqc_8703b[i][0];
+			u4Byte data = pRFCalibrateInfo->rx_iqc_8703b[i][1];
+
+			if (offset != 0) {
+				phy_set_bb_reg(pAdapter, offset, bMaskDWord, data);
+				RTW_INFO("Switch to S1 RxIQC (offset, data) = (0x%X, 0x%X)\n", offset, data);
+			}
+		}
+	}
+	break;
+	case ANTENNA_B: { /* Actually path S0 (BT)*/
+		pMptCtx->mpt_rf_path = RF_PATH_B;
+		phy_set_bb_reg(pAdapter, rS0S1_PathSwitch, BIT9 | BIT8 | BIT7, 0x5);
+		phy_set_bb_reg(pAdapter, 0xB2C, BIT31, 0x1); /* AGC Table Sel */
+
+		for (i = 0; i < 3; ++i) {
+			u4Byte offset = pRFCalibrateInfo->tx_iqc_8703b[i][0];
+			u4Byte data = pRFCalibrateInfo->tx_iqc_8703b[i][1];
+
+			if (pRFCalibrateInfo->tx_iqc_8703b[i][0] != 0) {
+				phy_set_bb_reg(pAdapter, offset, bMaskDWord, data);
+				RTW_INFO("Switch to S0 TxIQC (offset, data) = (0x%X, 0x%X)\n", offset, data);
+			}
+		}
+		for (i = 0; i < 2; ++i) {
+			u4Byte offset = pRFCalibrateInfo->rx_iqc_8703b[i][0];
+			u4Byte data = pRFCalibrateInfo->rx_iqc_8703b[i][1];
+
+			if (pRFCalibrateInfo->rx_iqc_8703b[i][0] != 0) {
+				phy_set_bb_reg(pAdapter, offset, bMaskDWord, data);
+				RTW_INFO("Switch to S0 RxIQC (offset, data) = (0x%X, 0x%X)\n", offset, data);
+			}
+		}
+	}
+	break;
+	default:
+		pMptCtx->mpt_rf_path = RF_PATH_AB;
+		break;
+	}
+
+}
+#endif
+
+#ifdef CONFIG_RTL8723D
+void mpt_SetRFPath_8723D(PADAPTER pAdapter)
+{
+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(pAdapter);
+	u1Byte	p = 0, i = 0;
+	u4Byte	ulAntennaTx, ulAntennaRx, offset = 0, data = 0, val32 = 0;
+	PMPT_CONTEXT	pMptCtx = &(pAdapter->mppriv.mpt_ctx);
+	struct dm_struct	*pDM_Odm = &pHalData->odmpriv;
+	struct dm_rf_calibration_struct	*pRFCalibrateInfo = &(pDM_Odm->rf_calibrate_info);
+
+	ulAntennaTx = pHalData->antenna_tx_path;
+	ulAntennaRx = pHalData->AntennaRxPath;
+
+	if (pHalData->rf_chip >= RF_CHIP_MAX) {
+		RTW_INFO("This RF chip ID is not supported\n");
+		return;
+	}
+
+	switch (pAdapter->mppriv.antenna_tx) {
+	/* Actually path S1  (Wi-Fi) */
+	case ANTENNA_A: {
+		pMptCtx->mpt_rf_path = RF_PATH_A;
+		phy_set_bb_reg(pAdapter, rS0S1_PathSwitch, BIT9|BIT8|BIT7|BIT6, 0);
+	}
+	break;
+	/* Actually path S0 (BT) */
+	case ANTENNA_B: {
+		pMptCtx->mpt_rf_path = RF_PATH_B;
+		phy_set_bb_reg(pAdapter, rS0S1_PathSwitch, BIT9|BIT8|BIT7|BIT6, 0xA);
+
+	}
+	break;
+	default:
+		pMptCtx->mpt_rf_path = RF_PATH_AB;
+		break;
+	}
+}
+#endif
+
+VOID mpt_SetRFPath_819X(PADAPTER	pAdapter)
+{
+	HAL_DATA_TYPE			*pHalData	= GET_HAL_DATA(pAdapter);
+	PMPT_CONTEXT		pMptCtx = &(pAdapter->mppriv.mpt_ctx);
+	u4Byte			ulAntennaTx, ulAntennaRx;
+	R_ANTENNA_SELECT_OFDM	*p_ofdm_tx;	/* OFDM Tx register */
+	R_ANTENNA_SELECT_CCK	*p_cck_txrx;
+	u1Byte		r_rx_antenna_ofdm = 0, r_ant_select_cck_val = 0;
+	u1Byte		chgTx = 0, chgRx = 0;
+	u4Byte		r_ant_sel_cck_val = 0, r_ant_select_ofdm_val = 0, r_ofdm_tx_en_val = 0;
+
+	ulAntennaTx = pHalData->antenna_tx_path;
+	ulAntennaRx = pHalData->AntennaRxPath;
+
+	p_ofdm_tx = (R_ANTENNA_SELECT_OFDM *)&r_ant_select_ofdm_val;
+	p_cck_txrx = (R_ANTENNA_SELECT_CCK *)&r_ant_select_cck_val;
+
+	p_ofdm_tx->r_ant_ht1			= 0x1;
+	p_ofdm_tx->r_ant_ht2			= 0x2;/*Second TX RF path is A*/
+	p_ofdm_tx->r_ant_non_ht			= 0x3;/*/ 0x1+0x2=0x3 */
+
+	switch (ulAntennaTx) {
+	case ANTENNA_A:
+		p_ofdm_tx->r_tx_antenna		= 0x1;
+		r_ofdm_tx_en_val		= 0x1;
+		p_ofdm_tx->r_ant_l		= 0x1;
+		p_ofdm_tx->r_ant_ht_s1		= 0x1;
+		p_ofdm_tx->r_ant_non_ht_s1	= 0x1;
+		p_cck_txrx->r_ccktx_enable	= 0x8;
+		chgTx = 1;
+		/*/ From SD3 Willis suggestion !!! Set RF A=TX and B as standby*/
+		/*/if (IS_HARDWARE_TYPE_8192S(pAdapter))*/
+		{
+			phy_set_bb_reg(pAdapter, rFPGA0_XA_HSSIParameter2, 0xe, 2);
+			phy_set_bb_reg(pAdapter, rFPGA0_XB_HSSIParameter2, 0xe, 1);
+			r_ofdm_tx_en_val			= 0x3;
+			/*/ Power save*/
+			/*/cosa r_ant_select_ofdm_val = 0x11111111;*/
+			/*/ We need to close RFB by SW control*/
+			if (pHalData->rf_type == RF_2T2R) {
+				phy_set_bb_reg(pAdapter, rFPGA0_XAB_RFInterfaceSW, BIT10, 0);
+				phy_set_bb_reg(pAdapter, rFPGA0_XAB_RFInterfaceSW, BIT26, 1);
+				phy_set_bb_reg(pAdapter, rFPGA0_XB_RFInterfaceOE, BIT10, 0);
+				phy_set_bb_reg(pAdapter, rFPGA0_XAB_RFParameter, BIT1, 1);
+				phy_set_bb_reg(pAdapter, rFPGA0_XAB_RFParameter, BIT17, 0);
+			}
+		}
+		pMptCtx->mpt_rf_path = RF_PATH_A;
+		break;
+	case ANTENNA_B:
+		p_ofdm_tx->r_tx_antenna		= 0x2;
+		r_ofdm_tx_en_val		= 0x2;
+		p_ofdm_tx->r_ant_l		= 0x2;
+		p_ofdm_tx->r_ant_ht_s1		= 0x2;
+		p_ofdm_tx->r_ant_non_ht_s1	= 0x2;
+		p_cck_txrx->r_ccktx_enable	= 0x4;
+		chgTx = 1;
+		/*/ From SD3 Willis suggestion !!! Set RF A as standby*/
+		/*/if (IS_HARDWARE_TYPE_8192S(pAdapter))*/
+		{
+			phy_set_bb_reg(pAdapter, rFPGA0_XA_HSSIParameter2, 0xe, 1);
+			phy_set_bb_reg(pAdapter, rFPGA0_XB_HSSIParameter2, 0xe, 2);
+
+			/*/ 2008/10/31 MH From SD3 Willi's suggestion. We must read RF 1T table.*/
+			/*/ 2009/01/08 MH From Sd3 Willis. We need to close RFA by SW control*/
+			if (pHalData->rf_type == RF_2T2R || pHalData->rf_type == RF_1T2R) {
+				phy_set_bb_reg(pAdapter, rFPGA0_XAB_RFInterfaceSW, BIT10, 1);
+				phy_set_bb_reg(pAdapter, rFPGA0_XA_RFInterfaceOE, BIT10, 0);
+				phy_set_bb_reg(pAdapter, rFPGA0_XAB_RFInterfaceSW, BIT26, 0);
+				/*/phy_set_bb_reg(pAdapter, rFPGA0_XB_RFInterfaceOE, BIT10, 0);*/
+				phy_set_bb_reg(pAdapter, rFPGA0_XAB_RFParameter, BIT1, 0);
+				phy_set_bb_reg(pAdapter, rFPGA0_XAB_RFParameter, BIT17, 1);
+			}
+		}
+		pMptCtx->mpt_rf_path = RF_PATH_B;
+		break;
+	case ANTENNA_AB:/*/ For 8192S*/
+		p_ofdm_tx->r_tx_antenna		= 0x3;
+		r_ofdm_tx_en_val		= 0x3;
+		p_ofdm_tx->r_ant_l		= 0x3;
+		p_ofdm_tx->r_ant_ht_s1		= 0x3;
+		p_ofdm_tx->r_ant_non_ht_s1	= 0x3;
+		p_cck_txrx->r_ccktx_enable	= 0xC;
+		chgTx = 1;
+		/*/ From SD3Willis suggestion !!! Set RF B as standby*/
+		/*/if (IS_HARDWARE_TYPE_8192S(pAdapter))*/
+		{
+			phy_set_bb_reg(pAdapter, rFPGA0_XA_HSSIParameter2, 0xe, 2);
+			phy_set_bb_reg(pAdapter, rFPGA0_XB_HSSIParameter2, 0xe, 2);
+			/* Disable Power save*/
+			/*cosa r_ant_select_ofdm_val = 0x3321333;*/
+			/* 2009/01/08 MH From Sd3 Willis. We need to enable RFA/B by SW control*/
+			if (pHalData->rf_type == RF_2T2R) {
+				phy_set_bb_reg(pAdapter, rFPGA0_XAB_RFInterfaceSW, BIT10, 0);
+
+				phy_set_bb_reg(pAdapter, rFPGA0_XAB_RFInterfaceSW, BIT26, 0);
+				/*/phy_set_bb_reg(pAdapter, rFPGA0_XB_RFInterfaceOE, BIT10, 0);*/
+				phy_set_bb_reg(pAdapter, rFPGA0_XAB_RFParameter, BIT1, 1);
+				phy_set_bb_reg(pAdapter, rFPGA0_XAB_RFParameter, BIT17, 1);
+			}
+		}
+		pMptCtx->mpt_rf_path = RF_PATH_AB;
+		break;
+	default:
+		break;
+	}
+#if 0
+	/*  r_rx_antenna_ofdm, bit0=A, bit1=B, bit2=C, bit3=D */
+	/*  r_cckrx_enable : CCK default, 0=A, 1=B, 2=C, 3=D */
+	/* r_cckrx_enable_2 : CCK option, 0=A, 1=B, 2=C, 3=D	 */
+#endif
+	switch (ulAntennaRx) {
+	case ANTENNA_A:
+		r_rx_antenna_ofdm		= 0x1;	/* A*/
+		p_cck_txrx->r_cckrx_enable	= 0x0;	/* default: A*/
+		p_cck_txrx->r_cckrx_enable_2	= 0x0;	/* option: A*/
+		chgRx = 1;
+		break;
+	case ANTENNA_B:
+		r_rx_antenna_ofdm			= 0x2;	/*/ B*/
+		p_cck_txrx->r_cckrx_enable	= 0x1;	/*/ default: B*/
+		p_cck_txrx->r_cckrx_enable_2	= 0x1;	/*/ option: B*/
+		chgRx = 1;
+		break;
+	case ANTENNA_AB:/*/ For 8192S and 8192E/U...*/
+		r_rx_antenna_ofdm		= 0x3;/*/ AB*/
+		p_cck_txrx->r_cckrx_enable	= 0x0;/*/ default:A*/
+		p_cck_txrx->r_cckrx_enable_2	= 0x1;/*/ option:B*/
+		chgRx = 1;
+		break;
+	default:
+		break;
+	}
+
+
+	if (chgTx && chgRx) {
+		switch (pHalData->rf_chip) {
+		case RF_8225:
+		case RF_8256:
+		case RF_6052:
+			/*/r_ant_sel_cck_val = r_ant_select_cck_val;*/
+			phy_set_bb_reg(pAdapter, rFPGA1_TxInfo, 0x7fffffff, r_ant_select_ofdm_val);		/*/OFDM Tx*/
+			phy_set_bb_reg(pAdapter, rFPGA0_TxInfo, 0x0000000f, r_ofdm_tx_en_val);		/*/OFDM Tx*/
+			phy_set_bb_reg(pAdapter, rOFDM0_TRxPathEnable, 0x0000000f, r_rx_antenna_ofdm);	/*/OFDM Rx*/
+			phy_set_bb_reg(pAdapter, rOFDM1_TRxPathEnable, 0x0000000f, r_rx_antenna_ofdm);	/*/OFDM Rx*/
+			if (IS_HARDWARE_TYPE_8192E(pAdapter)) {
+				phy_set_bb_reg(pAdapter, rOFDM0_TRxPathEnable, 0x000000F0, r_rx_antenna_ofdm);	/*/OFDM Rx*/
+				phy_set_bb_reg(pAdapter, rOFDM1_TRxPathEnable, 0x000000F0, r_rx_antenna_ofdm);	/*/OFDM Rx*/
+			}
+			phy_set_bb_reg(pAdapter, rCCK0_AFESetting, bMaskByte3, r_ant_select_cck_val);/*/r_ant_sel_cck_val); /CCK TxRx*/
+			break;
+
+		default:
+			RTW_INFO("Unsupported RFChipID for switching antenna.\n");
+			break;
+		}
+	}
+}	/* MPT_ProSetRFPath */
+
+#ifdef CONFIG_RTL8192F
+
+void mpt_set_rfpath_8192f(PADAPTER	pAdapter)
+{
+	HAL_DATA_TYPE			*pHalData	= GET_HAL_DATA(pAdapter);
+	PMPT_CONTEXT		pMptCtx = &(pAdapter->mppriv.mpt_ctx);
+
+	u16		ForcedDataRate = mpt_to_mgnt_rate(pMptCtx->mpt_rate_index);
+	u8				NssforRate, odmNssforRate;
+	u32				ulAntennaTx, ulAntennaRx;
+	u8				RxAntToPhyDm;
+	u8				TxAntToPhyDm;
+
+	ulAntennaTx = pHalData->antenna_tx_path;
+	ulAntennaRx = pHalData->AntennaRxPath;
+	NssforRate = MgntQuery_NssTxRate(ForcedDataRate);
+
+	if (pHalData->rf_chip >= RF_TYPE_MAX)
+		RTW_INFO("This RF chip ID is not supported\n");
+
+	switch (ulAntennaTx) {
+	case ANTENNA_A:
+			pMptCtx->mpt_rf_path = RF_PATH_A;
+			TxAntToPhyDm = BB_PATH_A;
+			break;
+	case ANTENNA_B:
+			pMptCtx->mpt_rf_path = RF_PATH_B;
+			TxAntToPhyDm = BB_PATH_B;
+			break;
+	case ANTENNA_AB:
+			pMptCtx->mpt_rf_path = RF_PATH_AB;
+			TxAntToPhyDm = (BB_PATH_A|BB_PATH_B);
+			break;
+	default:
+			pMptCtx->mpt_rf_path = RF_PATH_AB;
+			TxAntToPhyDm = (BB_PATH_A|BB_PATH_B);
+			break;
+	}
+
+	switch (ulAntennaRx) {
+	case ANTENNA_A:
+			RxAntToPhyDm = BB_PATH_A;
+			break;
+	case ANTENNA_B:
+			RxAntToPhyDm = BB_PATH_B;
+			break;
+	case ANTENNA_AB:
+			RxAntToPhyDm = (BB_PATH_A|BB_PATH_B);
+			break;
+	default:
+			RxAntToPhyDm = (BB_PATH_A|BB_PATH_B);
+			break;
+	}
+
+	config_phydm_trx_mode_8192f(GET_PDM_ODM(pAdapter), TxAntToPhyDm, RxAntToPhyDm, FALSE);
+
+}
+
+#endif
+
+void hal_mpt_SetAntenna(PADAPTER	pAdapter)
+
+{
+	RTW_INFO("Do %s\n", __func__);
+#ifdef CONFIG_RTL8814A
+	if (IS_HARDWARE_TYPE_8814A(pAdapter)) {
+		mpt_SetRFPath_8814A(pAdapter);
+		return;
+	}
+#endif
+#ifdef CONFIG_RTL8822B
+	if (IS_HARDWARE_TYPE_8822B(pAdapter)) {
+		rtl8822b_mp_config_rfpath(pAdapter);
+		return;
+	}
+#endif
+#ifdef CONFIG_RTL8821C
+	if (IS_HARDWARE_TYPE_8821C(pAdapter)) {
+		rtl8821c_mp_config_rfpath(pAdapter);
+		return;
+	}
+#endif
+#if	defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A)
+	if (IS_HARDWARE_TYPE_JAGUAR(pAdapter)) {
+		mpt_SetRFPath_8812A(pAdapter);
+		return;
+	}
+#endif
+#ifdef CONFIG_RTL8723B
+	if (IS_HARDWARE_TYPE_8723B(pAdapter)) {
+		mpt_SetRFPath_8723B(pAdapter);
+		return;
+	}
+#endif
+
+#ifdef CONFIG_RTL8703B
+	if (IS_HARDWARE_TYPE_8703B(pAdapter)) {
+		mpt_SetRFPath_8703B(pAdapter);
+		return;
+	}
+#endif
+
+#ifdef CONFIG_RTL8723D
+	if (IS_HARDWARE_TYPE_8723D(pAdapter)) {
+		mpt_SetRFPath_8723D(pAdapter);
+		return;
+	}
+#endif
+
+#ifdef CONFIG_RTL8192F
+		if (IS_HARDWARE_TYPE_8192F(pAdapter)) {
+			mpt_set_rfpath_8192f(pAdapter);
+			return;
+		}
+#endif
+
+	/*	else if (IS_HARDWARE_TYPE_8821B(pAdapter))
+			mpt_SetRFPath_8821B(pAdapter);
+		Prepare for 8822B
+		else if (IS_HARDWARE_TYPE_8822B(Context))
+			mpt_SetRFPath_8822B(Context);
+	*/
+	mpt_SetRFPath_819X(pAdapter);
+	RTW_INFO("mpt_SetRFPath_819X Do %s\n", __func__);
+}
+
+s32 hal_mpt_SetThermalMeter(PADAPTER pAdapter, u8 target_ther)
+{
+	HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
+
+	if (!netif_running(pAdapter->pnetdev)) {
+		return _FAIL;
+	}
+
+
+	if (check_fwstate(&pAdapter->mlmepriv, WIFI_MP_STATE) == _FALSE) {
+		return _FAIL;
+	}
+
+
+	target_ther &= 0xff;
+	if (target_ther < 0x07)
+		target_ther = 0x07;
+	else if (target_ther > 0x1d)
+		target_ther = 0x1d;
+
+	pHalData->eeprom_thermal_meter = target_ther;
+
+	return _SUCCESS;
+}
+
+
+void hal_mpt_TriggerRFThermalMeter(PADAPTER pAdapter)
+{
+	phy_set_rf_reg(pAdapter, RF_PATH_A, 0x42, BIT17 | BIT16, 0x03);
+
+}
+
+
+u8 hal_mpt_ReadRFThermalMeter(PADAPTER pAdapter)
+
+{
+	struct dm_struct *p_dm_odm = adapter_to_phydm(pAdapter);
+	u32 ThermalValue = 0;
+	s32 thermal_value_temp = 0;
+	s8 thermal_offset = 0;
+
+	ThermalValue = (u1Byte)phy_query_rf_reg(pAdapter, RF_PATH_A, 0x42, 0xfc00);	/*0x42: RF Reg[15:10]*/
+	thermal_offset = phydm_get_thermal_offset(p_dm_odm);
+
+	thermal_value_temp = ThermalValue + thermal_offset;
+
+	if (thermal_value_temp > 63)
+		ThermalValue = 63;
+	else if (thermal_value_temp < 0)
+		ThermalValue = 0;
+	else
+		ThermalValue = thermal_value_temp;
+
+	return (u8)ThermalValue;
+}
+
+
+void hal_mpt_GetThermalMeter(PADAPTER pAdapter, u8 *value)
+{
+#if 0
+	fw_cmd(pAdapter, IOCMD_GET_THERMAL_METER);
+	rtw_msleep_os(1000);
+	fw_cmd_data(pAdapter, value, 1);
+	*value &= 0xFF;
+#else
+	hal_mpt_TriggerRFThermalMeter(pAdapter);
+	rtw_msleep_os(1000);
+	*value = hal_mpt_ReadRFThermalMeter(pAdapter);
+#endif
+
+}
+
+
+void hal_mpt_SetSingleCarrierTx(PADAPTER pAdapter, u8 bStart)
+{
+	HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
+
+	pAdapter->mppriv.mpt_ctx.bSingleCarrier = bStart;
+
+	if (bStart) {/*/ Start Single Carrier.*/
+		/*/ Start Single Carrier.*/
+		/*/ 1. if OFDM block on?*/
+		if (!phy_query_bb_reg(pAdapter, rFPGA0_RFMOD, bOFDMEn))
+			phy_set_bb_reg(pAdapter, rFPGA0_RFMOD, bOFDMEn, 1); /*set OFDM block on*/
+
+		/*/ 2. set CCK test mode off, set to CCK normal mode*/
+		phy_set_bb_reg(pAdapter, rCCK0_System, bCCKBBMode, 0);
+
+		/*/ 3. turn on scramble setting*/
+		phy_set_bb_reg(pAdapter, rCCK0_System, bCCKScramble, 1);
+
+		/*/ 4. Turn On Continue Tx and turn off the other test modes.*/
+#if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A) || defined(CONFIG_RTL8814A) || defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C)
+		if (IS_HARDWARE_TYPE_JAGUAR_AND_JAGUAR2(pAdapter))
+			phy_set_bb_reg(pAdapter, rSingleTone_ContTx_Jaguar, BIT18 | BIT17 | BIT16, OFDM_SingleCarrier);
+		else
+#endif /* CONFIG_RTL8812A || CONFIG_RTL8821A || CONFIG_RTL8814A || CONFIG_RTL8822B || CONFIG_RTL8821C */
+			phy_set_bb_reg(pAdapter, rOFDM1_LSTF, BIT30 | BIT29 | BIT28, OFDM_SingleCarrier);
+
+	} else {
+		/*/ Stop Single Carrier.*/
+		/*/ Stop Single Carrier.*/
+		/*/ Turn off all test modes.*/
+#if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A) || defined(CONFIG_RTL8814A) || defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C)
+		if (IS_HARDWARE_TYPE_JAGUAR_AND_JAGUAR2(pAdapter))
+			phy_set_bb_reg(pAdapter, rSingleTone_ContTx_Jaguar, BIT18 | BIT17 | BIT16, OFDM_ALL_OFF);
+		else
+#endif /* CONFIG_RTL8812A || CONFIG_RTL8821A || CONFIG_RTL8814A || CONFIG_RTL8822B || CONFIG_RTL8821C */
+			phy_set_bb_reg(pAdapter, rOFDM1_LSTF, BIT30 | BIT29 | BIT28, OFDM_ALL_OFF);
+
+		rtw_msleep_os(10);
+		/*/BB Reset*/
+		phy_set_bb_reg(pAdapter, rPMAC_Reset, bBBResetB, 0x0);
+		phy_set_bb_reg(pAdapter, rPMAC_Reset, bBBResetB, 0x1);
+	}
+}
+
+
+void hal_mpt_SetSingleToneTx(PADAPTER pAdapter, u8 bStart)
+{
+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(pAdapter);
+	PMPT_CONTEXT		pMptCtx = &(pAdapter->mppriv.mpt_ctx);
+	struct dm_struct		*pDM_Odm = &pHalData->odmpriv;
+	u4Byte			ulAntennaTx = pHalData->antenna_tx_path;
+	static u4Byte		regRF = 0, regBB0 = 0, regBB1 = 0, regBB2 = 0, regBB3 = 0;
+	u8 rfPath;
+
+	switch (ulAntennaTx) {
+	case ANTENNA_B:
+		rfPath = RF_PATH_B;
+		break;
+	case ANTENNA_C:
+		rfPath = RF_PATH_C;
+		break;
+	case ANTENNA_D:
+		rfPath = RF_PATH_D;
+		break;
+	case ANTENNA_A:
+	default:
+		rfPath = RF_PATH_A;
+		break;
+	}
+
+	pAdapter->mppriv.mpt_ctx.is_single_tone = bStart;
+	if (bStart) {
+		/*/ Start Single Tone.*/
+		/*/ <20120326, Kordan> To amplify the power of tone for Xtal calibration. (asked by Edlu)*/
+		if (IS_HARDWARE_TYPE_8188E(pAdapter)) {
+			regRF = phy_query_rf_reg(pAdapter, rfPath, lna_low_gain_3, bRFRegOffsetMask);
+			phy_set_rf_reg(pAdapter, RF_PATH_A, lna_low_gain_3, BIT1, 0x1); /*/ RF LO enabled*/
+			phy_set_bb_reg(pAdapter, rFPGA0_RFMOD, bCCKEn, 0x0);
+			phy_set_bb_reg(pAdapter, rFPGA0_RFMOD, bOFDMEn, 0x0);
+		} else if (IS_HARDWARE_TYPE_8192E(pAdapter)) { /*/ USB need to do RF LO disable first, PCIE isn't required to follow this order.*/
+			/*/Set MAC REG 88C: Prevent SingleTone Fail*/
+			phy_set_mac_reg(pAdapter, 0x88C, 0xF00000, 0xF);
+			phy_set_rf_reg(pAdapter, pMptCtx->mpt_rf_path, lna_low_gain_3, BIT1, 0x1); /*/ RF LO disabled*/
+			phy_set_rf_reg(pAdapter, pMptCtx->mpt_rf_path, RF_AC, 0xF0000, 0x2); /*/ Tx mode*/
+		}	else if (IS_HARDWARE_TYPE_8192F(pAdapter)) { /* USB need to do RF LO disable first, PCIE isn't required to follow this order.*/
+ #ifdef CONFIG_RTL8192F
+			phy_set_mac_reg(pAdapter, REG_LEDCFG0_8192F, BIT23, 0x1);
+			phy_set_mac_reg(pAdapter, REG_LEDCFG0_8192F, BIT26, 0x1);
+			phy_set_mac_reg(pAdapter, REG_PAD_CTRL1_8192F, BIT7, 0x1);
+			phy_set_mac_reg(pAdapter, REG_PAD_CTRL1_8192F, BIT1, 0x1);
+			phy_set_mac_reg(pAdapter, REG_PAD_CTRL1_8192F, BIT0, 0x1);
+			phy_set_mac_reg(pAdapter, REG_AFE_CTRL_4_8192F, BIT16, 0x1);
+			phy_set_bb_reg(pAdapter, 0x88C, 0xF00000, 0xF);
+			phy_set_rf_reg(pAdapter, pMptCtx->mpt_rf_path, 0x57, BIT1, 0x1); /* RF LO disabled*/
+			phy_set_rf_reg(pAdapter, pMptCtx->mpt_rf_path, RF_AC, 0xF0000, 0x2); /* Tx mode*/
+#endif
+		} else if (IS_HARDWARE_TYPE_8723B(pAdapter)) {
+			if (pMptCtx->mpt_rf_path == RF_PATH_A) {
+				phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC, 0xF0000, 0x2); /*/ Tx mode*/
+				phy_set_rf_reg(pAdapter, RF_PATH_A, 0x56, 0xF, 0x1); /*/ RF LO enabled*/
+			} else {
+				/*/ S0/S1 both use PATH A to configure*/
+				phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC, 0xF0000, 0x2); /*/ Tx mode*/
+				phy_set_rf_reg(pAdapter, RF_PATH_A, 0x76, 0xF, 0x1); /*/ RF LO enabled*/
+			}
+		} else if (IS_HARDWARE_TYPE_8703B(pAdapter)) {
+			if (pMptCtx->mpt_rf_path == RF_PATH_A) {
+				phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC, 0xF0000, 0x2); /* Tx mode */
+				phy_set_rf_reg(pAdapter, RF_PATH_A, 0x53, 0xF000, 0x1); /* RF LO enabled */
+			}
+		} else if (IS_HARDWARE_TYPE_8188F(pAdapter) || IS_HARDWARE_TYPE_8188GTV(pAdapter)) {
+			/*Set BB REG 88C: Prevent SingleTone Fail*/
+			phy_set_bb_reg(pAdapter, rFPGA0_AnalogParameter4, 0xF00000, 0xF);
+			phy_set_rf_reg(pAdapter, pMptCtx->mpt_rf_path, lna_low_gain_3, BIT1, 0x1);
+			phy_set_rf_reg(pAdapter, pMptCtx->mpt_rf_path, RF_AC, 0xF0000, 0x2);
+
+		} else if (IS_HARDWARE_TYPE_8723D(pAdapter)) {
+			if (pMptCtx->mpt_rf_path == RF_PATH_A) {
+				phy_set_bb_reg(pAdapter, rFPGA0_RFMOD, bCCKEn|bOFDMEn, 0);
+				phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC, BIT16, 0x0);
+				phy_set_rf_reg(pAdapter, RF_PATH_A, 0x53, BIT0, 0x1);
+			} else {/* S0/S1 both use PATH A to configure */
+				phy_set_bb_reg(pAdapter, rFPGA0_RFMOD, bCCKEn|bOFDMEn, 0);
+				phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC, BIT16, 0x0);
+				phy_set_rf_reg(pAdapter, RF_PATH_A, 0x63, BIT0, 0x1);
+			}
+		} else if (IS_HARDWARE_TYPE_JAGUAR(pAdapter) || IS_HARDWARE_TYPE_8822B(pAdapter) || IS_HARDWARE_TYPE_8821C(pAdapter)) {
+#if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A) || defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C)
+			u1Byte p = RF_PATH_A;
+
+			regRF = phy_query_rf_reg(pAdapter, RF_PATH_A, RF_AC_Jaguar, bRFRegOffsetMask);
+			regBB0 = phy_query_bb_reg(pAdapter, rA_RFE_Pinmux_Jaguar, bMaskDWord);
+			regBB1 = phy_query_bb_reg(pAdapter, rB_RFE_Pinmux_Jaguar, bMaskDWord);
+			regBB2 = phy_query_bb_reg(pAdapter, rA_RFE_Pinmux_Jaguar + 4, bMaskDWord);
+			regBB3 = phy_query_bb_reg(pAdapter, rB_RFE_Pinmux_Jaguar + 4, bMaskDWord);
+
+			phy_set_bb_reg(pAdapter, rOFDMCCKEN_Jaguar, BIT29 | BIT28, 0x0); /*/ Disable CCK and OFDM*/
+
+			if (pMptCtx->mpt_rf_path == RF_PATH_AB) {
+				for (p = RF_PATH_A; p <= RF_PATH_B; ++p) {
+					phy_set_rf_reg(pAdapter, p, RF_AC_Jaguar, 0xF0000, 0x2); /*/ Tx mode: RF0x00[19:16]=4'b0010 */
+					phy_set_rf_reg(pAdapter, p, RF_AC_Jaguar, 0x1F, 0x0); /*/ Lowest RF gain index: RF_0x0[4:0] = 0*/
+					phy_set_rf_reg(pAdapter, p, lna_low_gain_3, BIT1, 0x1); /*/ RF LO enabled*/
+				}
+			} else {
+				phy_set_rf_reg(pAdapter, pMptCtx->mpt_rf_path, RF_AC_Jaguar, 0xF0000, 0x2); /*/ Tx mode: RF0x00[19:16]=4'b0010 */
+				phy_set_rf_reg(pAdapter, pMptCtx->mpt_rf_path, RF_AC_Jaguar, 0x1F, 0x0); /*/ Lowest RF gain index: RF_0x0[4:0] = 0*/
+#ifdef CONFIG_RTL8821C
+				if (IS_HARDWARE_TYPE_8821C(pAdapter) && pDM_Odm->current_rf_set_8821c == SWITCH_TO_BTG)
+					phy_set_rf_reg(pAdapter, pMptCtx->mpt_rf_path, 0x75, BIT16, 0x1); /* RF LO (for BTG) enabled */
+				else
+#endif
+					phy_set_rf_reg(pAdapter, pMptCtx->mpt_rf_path, lna_low_gain_3, BIT1, 0x1); /*/ RF LO enabled*/
+			}
+			if (IS_HARDWARE_TYPE_8822B(pAdapter)) {
+					phy_set_bb_reg(pAdapter, rA_RFE_Pinmux_Jaguar, bMaskDWord, 0x77777777);  /* 0xCB0=0x77777777*/
+					phy_set_bb_reg(pAdapter, rB_RFE_Pinmux_Jaguar, bMaskDWord, 0x77777777);  /* 0xEB0=0x77777777*/
+					phy_set_bb_reg(pAdapter, rA_RFE_Pinmux_Jaguar + 4, bMaskLWord, 0x7777);  /* 0xCB4[15:0] = 0x7777*/
+					phy_set_bb_reg(pAdapter, rB_RFE_Pinmux_Jaguar + 4, bMaskLWord, 0x7777);  /* 0xEB4[15:0] = 0x7777*/
+					phy_set_bb_reg(pAdapter, rA_RFE_Inverse_Jaguar, 0xFFF, 0xb); /* 0xCBC[23:16] = 0x12*/
+					phy_set_bb_reg(pAdapter, rB_RFE_Inverse_Jaguar, 0xFFF, 0x830); /* 0xEBC[23:16] = 0x12*/
+			} else if (IS_HARDWARE_TYPE_8821C(pAdapter)) {
+				phy_set_bb_reg(pAdapter, rA_RFE_Pinmux_Jaguar, 0xF0F0, 0x707);  /* 0xCB0[[15:12, 7:4] = 0x707*/
+
+				if (pHalData->external_pa_5g)
+				{
+					phy_set_bb_reg(pAdapter, rA_RFE_Pinmux_Jaguar + 4, 0xA00000, 0x1); /* 0xCB4[23, 21] = 0x1*/
+				}
+				else if (pHalData->ExternalPA_2G)
+				{
+					phy_set_bb_reg(pAdapter, rA_RFE_Pinmux_Jaguar + 4, 0xA00000, 0x1); /* 0xCB4[23, 21] = 0x1*/
+				}
+			} else {
+				phy_set_bb_reg(pAdapter, rA_RFE_Pinmux_Jaguar, 0xFF00F0, 0x77007);  /*/ 0xCB0[[23:16, 7:4] = 0x77007*/
+				phy_set_bb_reg(pAdapter, rB_RFE_Pinmux_Jaguar, 0xFF00F0, 0x77007);  /*/ 0xCB0[[23:16, 7:4] = 0x77007*/
+
+				if (pHalData->external_pa_5g) {
+					phy_set_bb_reg(pAdapter, rA_RFE_Pinmux_Jaguar + 4, 0xFF00000, 0x12); /*/ 0xCB4[23:16] = 0x12*/
+					phy_set_bb_reg(pAdapter, rB_RFE_Pinmux_Jaguar + 4, 0xFF00000, 0x12); /*/ 0xEB4[23:16] = 0x12*/
+				} else if (pHalData->ExternalPA_2G) {
+					phy_set_bb_reg(pAdapter, rA_RFE_Pinmux_Jaguar + 4, 0xFF00000, 0x11); /*/ 0xCB4[23:16] = 0x11*/
+					phy_set_bb_reg(pAdapter, rB_RFE_Pinmux_Jaguar + 4, 0xFF00000, 0x11); /*/ 0xEB4[23:16] = 0x11*/
+				}
+			}
+#endif
+		}
+#if defined(CONFIG_RTL8814A)
+				else if (IS_HARDWARE_TYPE_8814A(pAdapter))
+						mpt_SetSingleTone_8814A(pAdapter, TRUE, FALSE);
+#endif
+		else	/*/ Turn On SingleTone and turn off the other test modes.*/
+			phy_set_bb_reg(pAdapter, rOFDM1_LSTF, BIT30 | BIT29 | BIT28, OFDM_SingleTone);
+
+		write_bbreg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000500);
+		write_bbreg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000500);
+
+	} else {/*/ Stop Single Ton e.*/
+
+		if (IS_HARDWARE_TYPE_8188E(pAdapter)) {
+			phy_set_rf_reg(pAdapter, RF_PATH_A, lna_low_gain_3, bRFRegOffsetMask, regRF);
+			phy_set_bb_reg(pAdapter, rFPGA0_RFMOD, bCCKEn, 0x1);
+			phy_set_bb_reg(pAdapter, rFPGA0_RFMOD, bOFDMEn, 0x1);
+		} else if (IS_HARDWARE_TYPE_8192E(pAdapter)) {
+			phy_set_rf_reg(pAdapter, pMptCtx->mpt_rf_path, RF_AC, 0xF0000, 0x3);/*/ Tx mode*/
+			phy_set_rf_reg(pAdapter, pMptCtx->mpt_rf_path, lna_low_gain_3, BIT1, 0x0);/*/ RF LO disabled */
+			/*/ RESTORE MAC REG 88C: Enable RF Functions*/
+			phy_set_mac_reg(pAdapter, 0x88C, 0xF00000, 0x0);
+		} else if (IS_HARDWARE_TYPE_8192F(pAdapter)){
+#ifdef CONFIG_RTL8192F
+			phy_set_mac_reg(pAdapter, REG_LEDCFG0_8192F, BIT23, 0x0);
+			phy_set_mac_reg(pAdapter, REG_LEDCFG0_8192F, BIT26, 0x0);
+			phy_set_mac_reg(pAdapter, REG_PAD_CTRL1_8192F, BIT7, 0x0);
+			phy_set_mac_reg(pAdapter, REG_PAD_CTRL1_8192F, BIT1, 0x0);
+			phy_set_mac_reg(pAdapter, REG_PAD_CTRL1_8192F, BIT0, 0x0);
+			phy_set_mac_reg(pAdapter, REG_AFE_CTRL_4_8192F, BIT16, 0x0);
+			phy_set_bb_reg(pAdapter, 0x88C, 0xF00000, 0x0);
+			phy_set_rf_reg(pAdapter, pMptCtx->mpt_rf_path, 0x57, BIT1, 0x0); /* RF LO disabled*/
+			phy_set_rf_reg(pAdapter, pMptCtx->mpt_rf_path, RF_AC, 0xF0000, 0x3); /* Rx mode*/
+#endif
+		} else if (IS_HARDWARE_TYPE_8723B(pAdapter)) {
+			if (pMptCtx->mpt_rf_path == RF_PATH_A) {
+				phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC, 0xF0000, 0x3); /*/ Rx mode*/
+				phy_set_rf_reg(pAdapter, RF_PATH_A, 0x56, 0xF, 0x0); /*/ RF LO disabled*/
+			} else {
+				/*/ S0/S1 both use PATH A to configure*/
+				phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC, 0xF0000, 0x3); /*/ Rx mode*/
+				phy_set_rf_reg(pAdapter, RF_PATH_A, 0x76, 0xF, 0x0); /*/ RF LO disabled*/
+			}
+		} else if (IS_HARDWARE_TYPE_8703B(pAdapter)) {
+			if (pMptCtx->mpt_rf_path == RF_PATH_A) {
+				phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC, 0xF0000, 0x3); /* Rx mode */
+				phy_set_rf_reg(pAdapter, RF_PATH_A, 0x53, 0xF000, 0x0); /* RF LO disabled */
+			}
+		} else if (IS_HARDWARE_TYPE_8188F(pAdapter) || IS_HARDWARE_TYPE_8188GTV(pAdapter)) {
+			phy_set_rf_reg(pAdapter, pMptCtx->mpt_rf_path, RF_AC, 0xF0000, 0x3); /*Tx mode*/
+			phy_set_rf_reg(pAdapter, pMptCtx->mpt_rf_path, lna_low_gain_3, BIT1, 0x0); /*RF LO disabled*/
+			/*Set BB REG 88C: Prevent SingleTone Fail*/
+			phy_set_bb_reg(pAdapter, rFPGA0_AnalogParameter4, 0xF00000, 0xc);
+		} else if (IS_HARDWARE_TYPE_8723D(pAdapter)) {
+			if (pMptCtx->mpt_rf_path == RF_PATH_A) {
+				phy_set_bb_reg(pAdapter, rFPGA0_RFMOD, bCCKEn|bOFDMEn, 0x3);
+				phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC, BIT16, 0x1);
+				phy_set_rf_reg(pAdapter, RF_PATH_A, 0x53, BIT0, 0x0);
+			} else {	/* S0/S1 both use PATH A to configure */
+				phy_set_bb_reg(pAdapter, rFPGA0_RFMOD, bCCKEn|bOFDMEn, 0x3);
+				phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC, BIT16, 0x1);
+				phy_set_rf_reg(pAdapter, RF_PATH_A, 0x63, BIT0, 0x0);
+			}
+		} else if (IS_HARDWARE_TYPE_JAGUAR(pAdapter) || IS_HARDWARE_TYPE_8822B(pAdapter) || IS_HARDWARE_TYPE_8821C(pAdapter)) {
+#if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A) || defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C)
+			u1Byte p = RF_PATH_A;
+
+			phy_set_bb_reg(pAdapter, rOFDMCCKEN_Jaguar, BIT29 | BIT28, 0x3); /*/ Disable CCK and OFDM*/
+
+			if (pMptCtx->mpt_rf_path == RF_PATH_AB) {
+				for (p = RF_PATH_A; p <= RF_PATH_B; ++p) {
+					phy_set_rf_reg(pAdapter, p, RF_AC_Jaguar, bRFRegOffsetMask, regRF);
+					phy_set_rf_reg(pAdapter, p, lna_low_gain_3, BIT1, 0x0); /*/ RF LO disabled*/
+				}
+			} else {
+				p = pMptCtx->mpt_rf_path;
+				phy_set_rf_reg(pAdapter, p, RF_AC_Jaguar, bRFRegOffsetMask, regRF);
+
+				if (IS_HARDWARE_TYPE_8821C(pAdapter))
+					phy_set_rf_reg(pAdapter, p, 0x75, BIT16, 0x0); /* RF LO (for BTG) disabled */
+
+				phy_set_rf_reg(pAdapter, p, lna_low_gain_3, BIT1, 0x0); /*/ RF LO disabled*/
+			}
+
+			phy_set_bb_reg(pAdapter, rA_RFE_Pinmux_Jaguar, bMaskDWord, regBB0);
+			phy_set_bb_reg(pAdapter, rB_RFE_Pinmux_Jaguar, bMaskDWord, regBB1);
+			phy_set_bb_reg(pAdapter, rA_RFE_Pinmux_Jaguar + 4, bMaskDWord, regBB2);
+			phy_set_bb_reg(pAdapter, rB_RFE_Pinmux_Jaguar + 4, bMaskDWord, regBB3);
+
+			if (IS_HARDWARE_TYPE_8822B(pAdapter)) {
+				RTW_INFO("Restore RFE control Pin cbc\n");
+				phy_set_bb_reg(pAdapter, rA_RFE_Inverse_Jaguar, 0xfff, 0x0);
+				phy_set_bb_reg(pAdapter, rB_RFE_Inverse_Jaguar, 0xfff, 0x0);
+			}
+#endif
+		}
+#if defined(CONFIG_RTL8814A)
+		else if (IS_HARDWARE_TYPE_8814A(pAdapter))
+			mpt_SetSingleTone_8814A(pAdapter, FALSE, FALSE);
+
+		else/*/ Turn off all test modes.*/
+			phy_set_bb_reg(pAdapter, rSingleTone_ContTx_Jaguar, BIT18 | BIT17 | BIT16, OFDM_ALL_OFF);
+#endif
+		write_bbreg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000100);
+		write_bbreg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000100);
+
+	}
+}
+
+void hal_mpt_SetCarrierSuppressionTx(PADAPTER pAdapter, u8 bStart)
+{
+	u8 Rate;
+
+	pAdapter->mppriv.mpt_ctx.is_carrier_suppression = bStart;
+
+	Rate = HwRateToMPTRate(pAdapter->mppriv.rateidx);
+	if (bStart) {/* Start Carrier Suppression.*/
+		if (Rate <= MPT_RATE_11M) {
+			/*/ 1. if CCK block on?*/
+			if (!read_bbreg(pAdapter, rFPGA0_RFMOD, bCCKEn))
+				write_bbreg(pAdapter, rFPGA0_RFMOD, bCCKEn, bEnable);/*set CCK block on*/
+
+			/*/Turn Off All Test Mode*/
+			if (IS_HARDWARE_TYPE_JAGUAR(pAdapter) || IS_HARDWARE_TYPE_8814A(pAdapter) /*|| IS_HARDWARE_TYPE_8822B(pAdapter)*/)
+				phy_set_bb_reg(pAdapter, 0x914, BIT18 | BIT17 | BIT16, OFDM_ALL_OFF); /* rSingleTone_ContTx_Jaguar*/
+			else
+				phy_set_bb_reg(pAdapter, rOFDM1_LSTF, BIT30 | BIT29 | BIT28, OFDM_ALL_OFF);
+
+			write_bbreg(pAdapter, rCCK0_System, bCCKBBMode, 0x2);    /*/transmit mode*/
+			write_bbreg(pAdapter, rCCK0_System, bCCKScramble, 0x0);  /*/turn off scramble setting*/
+
+			/*/Set CCK Tx Test Rate*/
+			write_bbreg(pAdapter, rCCK0_System, bCCKTxRate, 0x0);    /*/Set FTxRate to 1Mbps*/
+		}
+
+		/*Set for dynamic set Power index*/
+		write_bbreg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000500);
+		write_bbreg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000500);
+
+	} else {/* Stop Carrier Suppression.*/
+
+		if (Rate <= MPT_RATE_11M) {
+			write_bbreg(pAdapter, rCCK0_System, bCCKBBMode, 0x0);    /*normal mode*/
+			write_bbreg(pAdapter, rCCK0_System, bCCKScramble, 0x1);  /*turn on scramble setting*/
+
+			/*BB Reset*/
+			write_bbreg(pAdapter, rPMAC_Reset, bBBResetB, 0x0);
+			write_bbreg(pAdapter, rPMAC_Reset, bBBResetB, 0x1);
+		}
+		/*Stop for dynamic set Power index*/
+		write_bbreg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000100);
+		write_bbreg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000100);
+	}
+	RTW_INFO("\n MPT_ProSetCarrierSupp() is finished.\n");
+}
+
+u32 hal_mpt_query_phytxok(PADAPTER	pAdapter)
+{
+	PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.mpt_ctx);
+	RT_PMAC_TX_INFO PMacTxInfo = pMptCtx->PMacTxInfo;
+	u16 count = 0;
+
+	if (IS_MPT_CCK_RATE(PMacTxInfo.TX_RATE))
+		count = phy_query_bb_reg(pAdapter, 0xF50, bMaskLWord); /* [15:0]*/
+	else
+		count = phy_query_bb_reg(pAdapter, 0xF50, bMaskHWord); /* [31:16]*/
+
+	if (count > 50000) {
+		rtw_reset_phy_trx_ok_counters(pAdapter);
+		pAdapter->mppriv.tx.sended += count;
+		count = 0;
+	}
+
+	return pAdapter->mppriv.tx.sended + count;
+
+}
+
+static	VOID mpt_StopCckContTx(
+	PADAPTER	pAdapter
+)
+{
+	HAL_DATA_TYPE	*pHalData	= GET_HAL_DATA(pAdapter);
+	PMPT_CONTEXT	pMptCtx = &(pAdapter->mppriv.mpt_ctx);
+	u1Byte			u1bReg;
+
+	pMptCtx->bCckContTx = FALSE;
+	pMptCtx->bOfdmContTx = FALSE;
+
+	phy_set_bb_reg(pAdapter, rCCK0_System, bCCKBBMode, 0x0);	/*normal mode*/
+	phy_set_bb_reg(pAdapter, rCCK0_System, bCCKScramble, 0x1);	/*turn on scramble setting*/
+
+	if (!IS_HARDWARE_TYPE_JAGUAR2(pAdapter)) {
+		phy_set_bb_reg(pAdapter, 0xa14, 0x300, 0x0);			/* 0xa15[1:0] = 2b00*/
+		phy_set_bb_reg(pAdapter, rOFDM0_TRMuxPar, 0x10000, 0x0);		/* 0xc08[16] = 0*/
+
+		phy_set_bb_reg(pAdapter, rFPGA0_XA_HSSIParameter2, BIT14, 0);
+		phy_set_bb_reg(pAdapter, rFPGA0_XB_HSSIParameter2, BIT14, 0);
+		phy_set_bb_reg(pAdapter, 0x0B34, BIT14, 0);
+	}
+
+	/*BB Reset*/
+	phy_set_bb_reg(pAdapter, rPMAC_Reset, bBBResetB, 0x0);
+	phy_set_bb_reg(pAdapter, rPMAC_Reset, bBBResetB, 0x1);
+
+	phy_set_bb_reg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000100);
+	phy_set_bb_reg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000100);
+
+}	/* mpt_StopCckContTx */
+
+
+static	VOID mpt_StopOfdmContTx(
+	PADAPTER	pAdapter
+)
+{
+	HAL_DATA_TYPE	*pHalData	= GET_HAL_DATA(pAdapter);
+	PMPT_CONTEXT	pMptCtx = &(pAdapter->mppriv.mpt_ctx);
+	u1Byte			u1bReg;
+	u4Byte			data;
+
+	pMptCtx->bCckContTx = FALSE;
+	pMptCtx->bOfdmContTx = FALSE;
+
+	if (IS_HARDWARE_TYPE_JAGUAR(pAdapter) || IS_HARDWARE_TYPE_JAGUAR2(pAdapter))
+		phy_set_bb_reg(pAdapter, 0x914, BIT18 | BIT17 | BIT16, OFDM_ALL_OFF);
+	else
+		phy_set_bb_reg(pAdapter, rOFDM1_LSTF, BIT30 | BIT29 | BIT28, OFDM_ALL_OFF);
+
+	rtw_mdelay_os(10);
+
+	if (!IS_HARDWARE_TYPE_JAGUAR(pAdapter) && !IS_HARDWARE_TYPE_JAGUAR2(pAdapter)) {
+		phy_set_bb_reg(pAdapter, 0xa14, 0x300, 0x0);			/* 0xa15[1:0] = 0*/
+		phy_set_bb_reg(pAdapter, rOFDM0_TRMuxPar, 0x10000, 0x0);		/* 0xc08[16] = 0*/
+	}
+
+	/*BB Reset*/
+	phy_set_bb_reg(pAdapter, rPMAC_Reset, bBBResetB, 0x0);
+	phy_set_bb_reg(pAdapter, rPMAC_Reset, bBBResetB, 0x1);
+
+	phy_set_bb_reg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000100);
+	phy_set_bb_reg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000100);
+}	/* mpt_StopOfdmContTx */
+
+
+static	VOID mpt_StartCckContTx(
+	PADAPTER		pAdapter
+)
+{
+	HAL_DATA_TYPE	*pHalData	= GET_HAL_DATA(pAdapter);
+	PMPT_CONTEXT	pMptCtx = &(pAdapter->mppriv.mpt_ctx);
+	u4Byte			cckrate;
+
+	/* 1. if CCK block on */
+	if (!phy_query_bb_reg(pAdapter, rFPGA0_RFMOD, bCCKEn))
+		phy_set_bb_reg(pAdapter, rFPGA0_RFMOD, bCCKEn, 1);/*set CCK block on*/
+
+	/*Turn Off All Test Mode*/
+	if (IS_HARDWARE_TYPE_JAGUAR_AND_JAGUAR2(pAdapter))
+		phy_set_bb_reg(pAdapter, 0x914, BIT18 | BIT17 | BIT16, OFDM_ALL_OFF);
+	else
+		phy_set_bb_reg(pAdapter, rOFDM1_LSTF, BIT30 | BIT29 | BIT28, OFDM_ALL_OFF);
+
+	cckrate  = pAdapter->mppriv.rateidx;
+
+	phy_set_bb_reg(pAdapter, rCCK0_System, bCCKTxRate, cckrate);
+
+	phy_set_bb_reg(pAdapter, rCCK0_System, bCCKBBMode, 0x2);	/*transmit mode*/
+	phy_set_bb_reg(pAdapter, rCCK0_System, bCCKScramble, 0x1);	/*turn on scramble setting*/
+
+	if (!IS_HARDWARE_TYPE_JAGUAR_AND_JAGUAR2(pAdapter)) {
+		phy_set_bb_reg(pAdapter, 0xa14, 0x300, 0x3);			/* 0xa15[1:0] = 11 force cck rxiq = 0*/
+		phy_set_bb_reg(pAdapter, rOFDM0_TRMuxPar, 0x10000, 0x1);		/* 0xc08[16] = 1 force ofdm rxiq = ofdm txiq*/
+		phy_set_bb_reg(pAdapter, rFPGA0_XA_HSSIParameter2, BIT14, 1);
+		phy_set_bb_reg(pAdapter, rFPGA0_XB_HSSIParameter2, BIT14, 1);
+		phy_set_bb_reg(pAdapter, 0x0B34, BIT14, 1);
+	}
+
+	phy_set_bb_reg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000500);
+	phy_set_bb_reg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000500);
+
+	pMptCtx->bCckContTx = TRUE;
+	pMptCtx->bOfdmContTx = FALSE;
+
+}	/* mpt_StartCckContTx */
+
+
+static	VOID mpt_StartOfdmContTx(
+	PADAPTER		pAdapter
+)
+{
+	HAL_DATA_TYPE	*pHalData	= GET_HAL_DATA(pAdapter);
+	PMPT_CONTEXT	pMptCtx = &(pAdapter->mppriv.mpt_ctx);
+
+	/* 1. if OFDM block on?*/
+	if (!phy_query_bb_reg(pAdapter, rFPGA0_RFMOD, bOFDMEn))
+		phy_set_bb_reg(pAdapter, rFPGA0_RFMOD, bOFDMEn, 1);/*set OFDM block on*/
+
+	/* 2. set CCK test mode off, set to CCK normal mode*/
+	phy_set_bb_reg(pAdapter, rCCK0_System, bCCKBBMode, 0);
+
+	/* 3. turn on scramble setting*/
+	phy_set_bb_reg(pAdapter, rCCK0_System, bCCKScramble, 1);
+
+	if (!IS_HARDWARE_TYPE_JAGUAR(pAdapter) && !IS_HARDWARE_TYPE_JAGUAR2(pAdapter)) {
+		phy_set_bb_reg(pAdapter, 0xa14, 0x300, 0x3);			/* 0xa15[1:0] = 2b'11*/
+		phy_set_bb_reg(pAdapter, rOFDM0_TRMuxPar, 0x10000, 0x1);		/* 0xc08[16] = 1*/
+	}
+
+	/* 4. Turn On Continue Tx and turn off the other test modes.*/
+	if (IS_HARDWARE_TYPE_JAGUAR(pAdapter) || IS_HARDWARE_TYPE_JAGUAR2(pAdapter))
+		phy_set_bb_reg(pAdapter, 0x914, BIT18 | BIT17 | BIT16, OFDM_ContinuousTx);
+	else
+		phy_set_bb_reg(pAdapter, rOFDM1_LSTF, BIT30 | BIT29 | BIT28, OFDM_ContinuousTx);
+
+	phy_set_bb_reg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000500);
+	phy_set_bb_reg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000500);
+
+	pMptCtx->bCckContTx = FALSE;
+	pMptCtx->bOfdmContTx = TRUE;
+}	/* mpt_StartOfdmContTx */
+
+
+#if defined(CONFIG_RTL8814A) || defined(CONFIG_RTL8821B) || defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C)
+/* for HW TX mode */
+void mpt_ProSetPMacTx(PADAPTER	Adapter)
+{
+	PMPT_CONTEXT	pMptCtx		=	&(Adapter->mppriv.mpt_ctx);
+	struct mp_priv *pmppriv = &Adapter->mppriv;
+	RT_PMAC_TX_INFO	PMacTxInfo	=	pMptCtx->PMacTxInfo;
+	u32			u4bTmp;
+
+#if 0
+	PRINT_DATA("LSIG ", PMacTxInfo.LSIG, 3);
+	PRINT_DATA("HT_SIG", PMacTxInfo.HT_SIG, 6);
+	PRINT_DATA("VHT_SIG_A", PMacTxInfo.VHT_SIG_A, 6);
+	PRINT_DATA("VHT_SIG_B", PMacTxInfo.VHT_SIG_B, 4);
+	dbg_print("VHT_SIG_B_CRC %x\n", PMacTxInfo.VHT_SIG_B_CRC);
+	PRINT_DATA("VHT_Delimiter", PMacTxInfo.VHT_Delimiter, 4);
+
+	PRINT_DATA("Src Address", Adapter->mac_addr, ETH_ALEN);
+	PRINT_DATA("Dest Address", PMacTxInfo.MacAddress, ETH_ALEN);
+#endif
+	if (pmppriv->pktInterval != 0)
+		PMacTxInfo.PacketPeriod = pmppriv->pktInterval;
+
+    	if (pmppriv->tx.count != 0)
+        	PMacTxInfo.PacketCount = pmppriv->tx.count;
+
+	RTW_INFO("SGI %d bSPreamble %d bSTBC %d bLDPC %d NDP_sound %d\n", PMacTxInfo.bSGI, PMacTxInfo.bSPreamble, PMacTxInfo.bSTBC, PMacTxInfo.bLDPC, PMacTxInfo.NDP_sound);
+	RTW_INFO("TXSC %d BandWidth %d PacketPeriod %d PacketCount %d PacketLength %d PacketPattern %d\n", PMacTxInfo.TX_SC, PMacTxInfo.BandWidth, PMacTxInfo.PacketPeriod, PMacTxInfo.PacketCount,
+		 PMacTxInfo.PacketLength, PMacTxInfo.PacketPattern);
+
+	if (PMacTxInfo.bEnPMacTx == FALSE) {
+		if (pMptCtx->HWTxmode == CONTINUOUS_TX) {
+			phy_set_bb_reg(Adapter, 0xb04, 0xf, 2);			/*	TX Stop*/
+			if (IS_MPT_CCK_RATE(pMptCtx->mpt_rate_index))
+				mpt_StopCckContTx(Adapter);
+			else
+				mpt_StopOfdmContTx(Adapter);
+		} else if (IS_MPT_CCK_RATE(pMptCtx->mpt_rate_index)) {
+			u4bTmp = phy_query_bb_reg(Adapter, 0xf50, bMaskLWord);
+			phy_set_bb_reg(Adapter, 0xb1c, bMaskLWord, u4bTmp + 50);
+			phy_set_bb_reg(Adapter, 0xb04, 0xf, 2);		/*TX Stop*/
+		} else
+			phy_set_bb_reg(Adapter, 0xb04, 0xf, 2);		/*	TX Stop*/
+
+		if (pMptCtx->HWTxmode == OFDM_Single_Tone_TX) {
+			/* Stop HW TX -> Stop Continuous TX -> Stop RF Setting*/
+			if (IS_MPT_CCK_RATE(pMptCtx->mpt_rate_index))
+				mpt_StopCckContTx(Adapter);
+			else
+				mpt_StopOfdmContTx(Adapter);
+
+			mpt_SetSingleTone_8814A(Adapter, FALSE, TRUE);
+		}
+		pMptCtx->HWTxmode = TEST_NONE;
+		return;
+	}
+
+    	pMptCtx->mpt_rate_index = PMacTxInfo.TX_RATE;
+
+	if (PMacTxInfo.Mode == CONTINUOUS_TX) {
+		pMptCtx->HWTxmode = CONTINUOUS_TX;
+		PMacTxInfo.PacketCount = 1;
+
+        	hal_mpt_SetTxPower(Adapter);
+
+		if (IS_MPT_CCK_RATE(PMacTxInfo.TX_RATE))
+			mpt_StartCckContTx(Adapter);
+		else
+			mpt_StartOfdmContTx(Adapter);
+	} else if (PMacTxInfo.Mode == OFDM_Single_Tone_TX) {
+		/* Continuous TX -> HW TX -> RF Setting */
+		pMptCtx->HWTxmode = OFDM_Single_Tone_TX;
+		PMacTxInfo.PacketCount = 1;
+
+		if (IS_MPT_CCK_RATE(PMacTxInfo.TX_RATE))
+			mpt_StartCckContTx(Adapter);
+		else
+			mpt_StartOfdmContTx(Adapter);
+	} else if (PMacTxInfo.Mode == PACKETS_TX) {
+		pMptCtx->HWTxmode = PACKETS_TX;
+		if (IS_MPT_CCK_RATE(PMacTxInfo.TX_RATE) && PMacTxInfo.PacketCount == 0)
+			PMacTxInfo.PacketCount = 0xffff;
+	}
+
+	if (IS_MPT_CCK_RATE(PMacTxInfo.TX_RATE)) {
+		/* 0xb1c[0:15] TX packet count 0xb1C[31:16]	SFD*/
+		u4bTmp = PMacTxInfo.PacketCount | (PMacTxInfo.SFD << 16);
+		phy_set_bb_reg(Adapter, 0xb1c, bMaskDWord, u4bTmp);
+		/* 0xb40 7:0 SIGNAL	15:8 SERVICE	31:16 LENGTH*/
+		u4bTmp = PMacTxInfo.SignalField | (PMacTxInfo.ServiceField << 8) | (PMacTxInfo.LENGTH << 16);
+		phy_set_bb_reg(Adapter, 0xb40, bMaskDWord, u4bTmp);
+		u4bTmp = PMacTxInfo.CRC16[0] | (PMacTxInfo.CRC16[1] << 8);
+		phy_set_bb_reg(Adapter, 0xb44, bMaskLWord, u4bTmp);
+
+		if (PMacTxInfo.bSPreamble)
+			phy_set_bb_reg(Adapter, 0xb0c, BIT27, 0);
+		else
+			phy_set_bb_reg(Adapter, 0xb0c, BIT27, 1);
+	} else {
+		phy_set_bb_reg(Adapter, 0xb18, 0xfffff, PMacTxInfo.PacketCount);
+
+		u4bTmp = PMacTxInfo.LSIG[0] | ((PMacTxInfo.LSIG[1]) << 8) | ((PMacTxInfo.LSIG[2]) << 16) | ((PMacTxInfo.PacketPattern) << 24);
+		phy_set_bb_reg(Adapter, 0xb08, bMaskDWord, u4bTmp);	/*	Set 0xb08[23:0] = LSIG, 0xb08[31:24] =  Data init octet*/
+
+		if (PMacTxInfo.PacketPattern == 0x12)
+			u4bTmp = 0x3000000;
+		else
+			u4bTmp = 0;
+	}
+
+	if (IS_MPT_HT_RATE(PMacTxInfo.TX_RATE)) {
+		u4bTmp |= PMacTxInfo.HT_SIG[0] | ((PMacTxInfo.HT_SIG[1]) << 8) | ((PMacTxInfo.HT_SIG[2]) << 16);
+		phy_set_bb_reg(Adapter, 0xb0c, bMaskDWord, u4bTmp);
+		u4bTmp = PMacTxInfo.HT_SIG[3] | ((PMacTxInfo.HT_SIG[4]) << 8) | ((PMacTxInfo.HT_SIG[5]) << 16);
+		phy_set_bb_reg(Adapter, 0xb10, 0xffffff, u4bTmp);
+	} else if (IS_MPT_VHT_RATE(PMacTxInfo.TX_RATE)) {
+		u4bTmp |= PMacTxInfo.VHT_SIG_A[0] | ((PMacTxInfo.VHT_SIG_A[1]) << 8) | ((PMacTxInfo.VHT_SIG_A[2]) << 16);
+		phy_set_bb_reg(Adapter, 0xb0c, bMaskDWord, u4bTmp);
+		u4bTmp = PMacTxInfo.VHT_SIG_A[3] | ((PMacTxInfo.VHT_SIG_A[4]) << 8) | ((PMacTxInfo.VHT_SIG_A[5]) << 16);
+		phy_set_bb_reg(Adapter, 0xb10, 0xffffff, u4bTmp);
+
+		_rtw_memcpy(&u4bTmp, PMacTxInfo.VHT_SIG_B, 4);
+		phy_set_bb_reg(Adapter, 0xb14, bMaskDWord, u4bTmp);
+	}
+
+	if (IS_MPT_VHT_RATE(PMacTxInfo.TX_RATE)) {
+		u4bTmp = (PMacTxInfo.VHT_SIG_B_CRC << 24) | PMacTxInfo.PacketPeriod;	/* for TX interval */
+		phy_set_bb_reg(Adapter, 0xb20, bMaskDWord, u4bTmp);
+
+		_rtw_memcpy(&u4bTmp, PMacTxInfo.VHT_Delimiter, 4);
+		phy_set_bb_reg(Adapter, 0xb24, bMaskDWord, u4bTmp);
+
+		/* 0xb28 - 0xb34 24 byte Probe Request MAC Header*/
+		/*& Duration & Frame control*/
+		phy_set_bb_reg(Adapter, 0xb28, bMaskDWord, 0x00000040);
+
+		/* Address1 [0:3]*/
+		u4bTmp = PMacTxInfo.MacAddress[0] | (PMacTxInfo.MacAddress[1] << 8) | (PMacTxInfo.MacAddress[2] << 16) | (PMacTxInfo.MacAddress[3] << 24);
+		phy_set_bb_reg(Adapter, 0xb2C, bMaskDWord, u4bTmp);
+
+		/* Address3 [3:0]*/
+		phy_set_bb_reg(Adapter, 0xb38, bMaskDWord, u4bTmp);
+
+		/* Address2[0:1] & Address1 [5:4]*/
+		u4bTmp = PMacTxInfo.MacAddress[4] | (PMacTxInfo.MacAddress[5] << 8) | (Adapter->mac_addr[0] << 16) | (Adapter->mac_addr[1] << 24);
+		phy_set_bb_reg(Adapter, 0xb30, bMaskDWord, u4bTmp);
+
+		/* Address2 [5:2]*/
+		u4bTmp = Adapter->mac_addr[2] | (Adapter->mac_addr[3] << 8) | (Adapter->mac_addr[4] << 16) | (Adapter->mac_addr[5] << 24);
+		phy_set_bb_reg(Adapter, 0xb34, bMaskDWord, u4bTmp);
+
+		/* Sequence Control & Address3 [5:4]*/
+		/*u4bTmp = PMacTxInfo.MacAddress[4]|(PMacTxInfo.MacAddress[5] << 8) ;*/
+		/*phy_set_bb_reg(Adapter, 0xb38, bMaskDWord, u4bTmp);*/
+	} else {
+		phy_set_bb_reg(Adapter, 0xb20, bMaskDWord, PMacTxInfo.PacketPeriod);	/* for TX interval*/
+		/* & Duration & Frame control */
+		phy_set_bb_reg(Adapter, 0xb24, bMaskDWord, 0x00000040);
+
+		/* 0xb24 - 0xb38 24 byte Probe Request MAC Header*/
+		/* Address1 [0:3]*/
+		u4bTmp = PMacTxInfo.MacAddress[0] | (PMacTxInfo.MacAddress[1] << 8) | (PMacTxInfo.MacAddress[2] << 16) | (PMacTxInfo.MacAddress[3] << 24);
+		phy_set_bb_reg(Adapter, 0xb28, bMaskDWord, u4bTmp);
+
+		/* Address3 [3:0]*/
+		phy_set_bb_reg(Adapter, 0xb34, bMaskDWord, u4bTmp);
+
+		/* Address2[0:1] & Address1 [5:4]*/
+		u4bTmp = PMacTxInfo.MacAddress[4] | (PMacTxInfo.MacAddress[5] << 8) | (Adapter->mac_addr[0] << 16) | (Adapter->mac_addr[1] << 24);
+		phy_set_bb_reg(Adapter, 0xb2c, bMaskDWord, u4bTmp);
+
+		/* Address2 [5:2] */
+		u4bTmp = Adapter->mac_addr[2] | (Adapter->mac_addr[3] << 8) | (Adapter->mac_addr[4] << 16) | (Adapter->mac_addr[5] << 24);
+		phy_set_bb_reg(Adapter, 0xb30, bMaskDWord, u4bTmp);
+
+		/* Sequence Control & Address3 [5:4]*/
+		u4bTmp = PMacTxInfo.MacAddress[4] | (PMacTxInfo.MacAddress[5] << 8);
+		phy_set_bb_reg(Adapter, 0xb38, bMaskDWord, u4bTmp);
+	}
+
+	phy_set_bb_reg(Adapter, 0xb48, bMaskByte3, PMacTxInfo.TX_RATE_HEX);
+
+	/* 0xb4c 3:0 TXSC	5:4	BW	7:6 m_STBC	8 NDP_Sound*/
+	u4bTmp = (PMacTxInfo.TX_SC) | ((PMacTxInfo.BandWidth) << 4) | ((PMacTxInfo.m_STBC - 1) << 6) | ((PMacTxInfo.NDP_sound) << 8);
+	phy_set_bb_reg(Adapter, 0xb4c, 0x1ff, u4bTmp);
+
+	if (IS_HARDWARE_TYPE_JAGUAR2(Adapter)) {
+		u4Byte offset = 0xb44;
+
+		if (IS_MPT_OFDM_RATE(PMacTxInfo.TX_RATE))
+			phy_set_bb_reg(Adapter, offset, 0xc0000000, 0);
+		else if (IS_MPT_HT_RATE(PMacTxInfo.TX_RATE))
+			phy_set_bb_reg(Adapter, offset, 0xc0000000, 1);
+		else if (IS_MPT_VHT_RATE(PMacTxInfo.TX_RATE))
+			phy_set_bb_reg(Adapter, offset, 0xc0000000, 2);
+
+	} else if(IS_HARDWARE_TYPE_JAGUAR(Adapter)) {
+		u4Byte offset = 0xb4c;
+
+		if(IS_MPT_OFDM_RATE(PMacTxInfo.TX_RATE))
+			phy_set_bb_reg(Adapter, offset, 0xc0000000, 0);
+		else if(IS_MPT_HT_RATE(PMacTxInfo.TX_RATE))
+			phy_set_bb_reg(Adapter, offset, 0xc0000000, 1);
+		else if(IS_MPT_VHT_RATE(PMacTxInfo.TX_RATE))
+			phy_set_bb_reg(Adapter, offset, 0xc0000000, 2);
+	}
+
+	phy_set_bb_reg(Adapter, 0xb00, BIT8, 1);		/*	Turn on PMAC*/
+	/* phy_set_bb_reg(Adapter, 0xb04, 0xf, 2);				 */ /* TX Stop */
+	if (IS_MPT_CCK_RATE(PMacTxInfo.TX_RATE)) {
+		phy_set_bb_reg(Adapter, 0xb04, 0xf, 8);		/*TX CCK ON*/
+		phy_set_bb_reg(Adapter, 0xA84, BIT31, 0);
+	} else
+		phy_set_bb_reg(Adapter, 0xb04, 0xf, 4);		/*	TX Ofdm ON	*/
+
+	if (PMacTxInfo.Mode == OFDM_Single_Tone_TX)
+		mpt_SetSingleTone_8814A(Adapter, TRUE, TRUE);
+
+}
+
+#endif
+
+void hal_mpt_SetContinuousTx(PADAPTER pAdapter, u8 bStart)
+{
+	u8 Rate;
+
+	RTW_INFO("SetContinuousTx: rate:%d\n", pAdapter->mppriv.rateidx);
+	Rate = HwRateToMPTRate(pAdapter->mppriv.rateidx);
+	pAdapter->mppriv.mpt_ctx.is_start_cont_tx = bStart;
+
+	if (Rate <= MPT_RATE_11M) {
+		if (bStart)
+			mpt_StartCckContTx(pAdapter);
+		else
+			mpt_StopCckContTx(pAdapter);
+
+	} else if (Rate >= MPT_RATE_6M) {
+		if (bStart)
+			mpt_StartOfdmContTx(pAdapter);
+		else
+			mpt_StopOfdmContTx(pAdapter);
+	}
+}
+
+#endif /* CONFIG_MP_INCLUDE*/
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/hal_phy.c linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/hal_phy.c
--- linux-5.6.3/3rdparty/rtl8821ce/hal/hal_phy.c	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/hal_phy.c	2020-04-10 16:35:06.790658854 +0300
@@ -0,0 +1,257 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#define _HAL_PHY_C_
+
+#include <drv_types.h>
+
+/**
+* Function:	PHY_CalculateBitShift
+*
+* OverView:	Get shifted position of the BitMask
+*
+* Input:
+*			u4Byte		BitMask,
+*
+* Output:	none
+* Return:		u4Byte		Return the shift bit bit position of the mask
+*/
+u32
+PHY_CalculateBitShift(
+	u32 BitMask
+)
+{
+	u32 i;
+
+	for (i = 0; i <= 31; i++) {
+		if (((BitMask >> i) &  0x1) == 1)
+			break;
+	}
+
+	return i;
+}
+
+
+#ifdef CONFIG_RF_SHADOW_RW
+/* ********************************************************************************
+ *	Constant.
+ * ********************************************************************************
+ * 2008/11/20 MH For Debug only, RF */
+static RF_SHADOW_T RF_Shadow[RF6052_MAX_PATH][RF6052_MAX_REG];
+
+/*
+ * ==> RF shadow Operation API Code Section!!!
+ *
+ *-----------------------------------------------------------------------------
+ * Function:	PHY_RFShadowRead
+ *				PHY_RFShadowWrite
+ *				PHY_RFShadowCompare
+ *				PHY_RFShadowRecorver
+ *				PHY_RFShadowCompareAll
+ *				PHY_RFShadowRecorverAll
+ *				PHY_RFShadowCompareFlagSet
+ *				PHY_RFShadowRecorverFlagSet
+ *
+ * Overview:	When we set RF register, we must write shadow at first.
+ *			When we are running, we must compare shadow abd locate error addr.
+ *			Decide to recorver or not.
+ *
+ * Input:       NONE
+ *
+ * Output:      NONE
+ *
+ * Return:      NONE
+ *
+ * Revised History:
+ * When			Who		Remark
+ * 11/20/2008	MHC		Create Version 0.
+ *
+ *---------------------------------------------------------------------------*/
+u32
+PHY_RFShadowRead(
+	IN	PADAPTER		Adapter,
+	IN	enum rf_path		eRFPath,
+	IN	u32				Offset)
+{
+	return	RF_Shadow[eRFPath][Offset].Value;
+
+}	/* PHY_RFShadowRead */
+
+
+VOID
+PHY_RFShadowWrite(
+	IN	PADAPTER		Adapter,
+	IN	enum rf_path		eRFPath,
+	IN	u32				Offset,
+	IN	u32				Data)
+{
+	RF_Shadow[eRFPath][Offset].Value = (Data & bRFRegOffsetMask);
+	RF_Shadow[eRFPath][Offset].Driver_Write = _TRUE;
+
+}	/* PHY_RFShadowWrite */
+
+
+BOOLEAN
+PHY_RFShadowCompare(
+	IN	PADAPTER		Adapter,
+	IN	enum rf_path		eRFPath,
+	IN	u32				Offset)
+{
+	u32	reg;
+	/* Check if we need to check the register */
+	if (RF_Shadow[eRFPath][Offset].Compare == _TRUE) {
+		reg = rtw_hal_read_rfreg(Adapter, eRFPath, Offset, bRFRegOffsetMask);
+		/* Compare shadow and real rf register for 20bits!! */
+		if (RF_Shadow[eRFPath][Offset].Value != reg) {
+			/* Locate error position. */
+			RF_Shadow[eRFPath][Offset].ErrorOrNot = _TRUE;
+		}
+		return RF_Shadow[eRFPath][Offset].ErrorOrNot ;
+	}
+	return _FALSE;
+}	/* PHY_RFShadowCompare */
+
+
+VOID
+PHY_RFShadowRecorver(
+	IN	PADAPTER		Adapter,
+	IN	enum rf_path		eRFPath,
+	IN	u32				Offset)
+{
+	/* Check if the address is error */
+	if (RF_Shadow[eRFPath][Offset].ErrorOrNot == _TRUE) {
+		/* Check if we need to recorver the register. */
+		if (RF_Shadow[eRFPath][Offset].Recorver == _TRUE) {
+			rtw_hal_write_rfreg(Adapter, eRFPath, Offset, bRFRegOffsetMask,
+					    RF_Shadow[eRFPath][Offset].Value);
+		}
+	}
+
+}	/* PHY_RFShadowRecorver */
+
+
+VOID
+PHY_RFShadowCompareAll(
+	IN	PADAPTER			Adapter)
+{
+	enum rf_path	eRFPath = RF_PATH_A;
+	u32		Offset = 0, maxReg = GET_RF6052_REAL_MAX_REG(Adapter);
+
+	for (eRFPath = 0; eRFPath < RF6052_MAX_PATH; eRFPath++) {
+		for (Offset = 0; Offset < maxReg; Offset++)
+			PHY_RFShadowCompare(Adapter, eRFPath, Offset);
+	}
+
+}	/* PHY_RFShadowCompareAll */
+
+
+VOID
+PHY_RFShadowRecorverAll(
+	IN	PADAPTER			Adapter)
+{
+	enum rf_path		eRFPath = RF_PATH_A;
+	u32		Offset = 0, maxReg = GET_RF6052_REAL_MAX_REG(Adapter);
+
+	for (eRFPath = 0; eRFPath < RF6052_MAX_PATH; eRFPath++) {
+		for (Offset = 0; Offset < maxReg; Offset++)
+			PHY_RFShadowRecorver(Adapter, eRFPath, Offset);
+	}
+
+}	/* PHY_RFShadowRecorverAll */
+
+
+VOID
+PHY_RFShadowCompareFlagSet(
+	IN	PADAPTER		Adapter,
+	IN	enum rf_path		eRFPath,
+	IN	u32				Offset,
+	IN	u8				Type)
+{
+	/* Set True or False!!! */
+	RF_Shadow[eRFPath][Offset].Compare = Type;
+
+}	/* PHY_RFShadowCompareFlagSet */
+
+
+VOID
+PHY_RFShadowRecorverFlagSet(
+	IN	PADAPTER		Adapter,
+	IN	enum rf_path		eRFPath,
+	IN	u32				Offset,
+	IN	u8				Type)
+{
+	/* Set True or False!!! */
+	RF_Shadow[eRFPath][Offset].Recorver = Type;
+
+}	/* PHY_RFShadowRecorverFlagSet */
+
+
+VOID
+PHY_RFShadowCompareFlagSetAll(
+	IN	PADAPTER			Adapter)
+{
+	enum rf_path	eRFPath = RF_PATH_A;
+	u32		Offset = 0, maxReg = GET_RF6052_REAL_MAX_REG(Adapter);
+
+	for (eRFPath = 0; eRFPath < RF6052_MAX_PATH; eRFPath++) {
+		for (Offset = 0; Offset < maxReg; Offset++) {
+			/* 2008/11/20 MH For S3S4 test, we only check reg 26/27 now!!!! */
+			if (Offset != 0x26 && Offset != 0x27)
+				PHY_RFShadowCompareFlagSet(Adapter, eRFPath, Offset, _FALSE);
+			else
+				PHY_RFShadowCompareFlagSet(Adapter, eRFPath, Offset, _TRUE);
+		}
+	}
+
+}	/* PHY_RFShadowCompareFlagSetAll */
+
+
+VOID
+PHY_RFShadowRecorverFlagSetAll(
+	IN	PADAPTER			Adapter)
+{
+	enum rf_path		eRFPath = RF_PATH_A;
+	u32		Offset = 0, maxReg = GET_RF6052_REAL_MAX_REG(Adapter);
+
+	for (eRFPath = 0; eRFPath < RF6052_MAX_PATH; eRFPath++) {
+		for (Offset = 0; Offset < maxReg; Offset++) {
+			/* 2008/11/20 MH For S3S4 test, we only check reg 26/27 now!!!! */
+			if (Offset != 0x26 && Offset != 0x27)
+				PHY_RFShadowRecorverFlagSet(Adapter, eRFPath, Offset, _FALSE);
+			else
+				PHY_RFShadowRecorverFlagSet(Adapter, eRFPath, Offset, _TRUE);
+		}
+	}
+
+}	/* PHY_RFShadowCompareFlagSetAll */
+
+VOID
+PHY_RFShadowRefresh(
+	IN	PADAPTER			Adapter)
+{
+	enum rf_path		eRFPath = RF_PATH_A;
+	u32		Offset = 0, maxReg = GET_RF6052_REAL_MAX_REG(Adapter);
+
+	for (eRFPath = 0; eRFPath < RF6052_MAX_PATH; eRFPath++) {
+		for (Offset = 0; Offset < maxReg; Offset++) {
+			RF_Shadow[eRFPath][Offset].Value = 0;
+			RF_Shadow[eRFPath][Offset].Compare = _FALSE;
+			RF_Shadow[eRFPath][Offset].Recorver  = _FALSE;
+			RF_Shadow[eRFPath][Offset].ErrorOrNot = _FALSE;
+			RF_Shadow[eRFPath][Offset].Driver_Write = _FALSE;
+		}
+	}
+
+}	/* PHY_RFShadowRead */
+#endif /*CONFIG_RF_SHADOW_RW*/
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/HalPwrSeqCmd.c linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/HalPwrSeqCmd.c
--- linux-5.6.3/3rdparty/rtl8821ce/hal/HalPwrSeqCmd.c	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/HalPwrSeqCmd.c	2020-04-10 16:35:06.780658387 +0300
@@ -0,0 +1,185 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+/*++
+Copyright (c) Realtek Semiconductor Corp. All rights reserved.
+
+Module Name:
+	HalPwrSeqCmd.c
+
+Abstract:
+	Implement HW Power sequence configuration CMD handling routine for Realtek devices.
+
+Major Change History:
+	When       Who               What
+	---------- ---------------   -------------------------------
+	2011-10-26 Lucas            Modify to be compatible with SD4-CE driver.
+	2011-07-07 Roger            Create.
+
+--*/
+#include <HalPwrSeqCmd.h>
+
+
+/*
+ *	Description:
+ *		This routine deal with the Power Configuration CMDs parsing for RTL8723/RTL8188E Series IC.
+ *
+ *	Assumption:
+ *		We should follow specific format which was released from HW SD.
+ *
+ *	2011.07.07, added by Roger.
+ *   */
+u8 HalPwrSeqCmdParsing(
+	PADAPTER		padapter,
+	u8				CutVersion,
+	u8				FabVersion,
+	u8				InterfaceType,
+	WLAN_PWR_CFG	PwrSeqCmd[])
+{
+	WLAN_PWR_CFG	PwrCfgCmd = {0};
+	u8				bPollingBit = _FALSE;
+	u8				bHWICSupport = _FALSE;
+	u32				AryIdx = 0;
+	u8				value = 0;
+	u32				offset = 0;
+	u8				flag = 0;
+	u32				pollingCount = 0; /* polling autoload done. */
+	u32				maxPollingCnt = 5000;
+
+	do {
+		PwrCfgCmd = PwrSeqCmd[AryIdx];
+
+
+		/* 2 Only Handle the command whose FAB, CUT, and Interface are matched */
+		if ((GET_PWR_CFG_FAB_MASK(PwrCfgCmd) & FabVersion) &&
+		    (GET_PWR_CFG_CUT_MASK(PwrCfgCmd) & CutVersion) &&
+		    (GET_PWR_CFG_INTF_MASK(PwrCfgCmd) & InterfaceType)) {
+			switch (GET_PWR_CFG_CMD(PwrCfgCmd)) {
+			case PWR_CMD_READ:
+				break;
+
+			case PWR_CMD_WRITE:
+				offset = GET_PWR_CFG_OFFSET(PwrCfgCmd);
+
+#ifdef CONFIG_SDIO_HCI
+				/*  */
+				/* <Roger_Notes> We should deal with interface specific address mapping for some interfaces, e.g., SDIO interface */
+				/* 2011.07.07. */
+				/*  */
+				if (GET_PWR_CFG_BASE(PwrCfgCmd) == PWR_BASEADDR_SDIO) {
+					/* Read Back SDIO Local value */
+					value = SdioLocalCmd52Read1Byte(padapter, offset);
+
+					value &= ~(GET_PWR_CFG_MASK(PwrCfgCmd));
+					value |= (GET_PWR_CFG_VALUE(PwrCfgCmd) & GET_PWR_CFG_MASK(PwrCfgCmd));
+
+					/* Write Back SDIO Local value */
+					SdioLocalCmd52Write1Byte(padapter, offset, value);
+				} else
+#endif
+				{
+#ifdef CONFIG_GSPI_HCI
+					if (GET_PWR_CFG_BASE(PwrCfgCmd) == PWR_BASEADDR_SDIO)
+						offset = SPI_LOCAL_OFFSET | offset;
+#endif
+					/* Read the value from system register */
+					value = rtw_read8(padapter, offset);
+
+					value = value & (~(GET_PWR_CFG_MASK(PwrCfgCmd)));
+					value = value | (GET_PWR_CFG_VALUE(PwrCfgCmd) & GET_PWR_CFG_MASK(PwrCfgCmd));
+
+					/* Write the value back to sytem register */
+					rtw_write8(padapter, offset, value);
+				}
+				break;
+
+			case PWR_CMD_POLLING:
+
+				bPollingBit = _FALSE;
+				offset = GET_PWR_CFG_OFFSET(PwrCfgCmd);
+
+				rtw_hal_get_hwreg(padapter, HW_VAR_PWR_CMD, &bHWICSupport);
+				if (bHWICSupport && offset == 0x06) {
+					flag = 0;
+					maxPollingCnt = 100000;
+				} else
+					maxPollingCnt = 5000;
+
+#ifdef CONFIG_GSPI_HCI
+				if (GET_PWR_CFG_BASE(PwrCfgCmd) == PWR_BASEADDR_SDIO)
+					offset = SPI_LOCAL_OFFSET | offset;
+#endif
+				do {
+#ifdef CONFIG_SDIO_HCI
+					if (GET_PWR_CFG_BASE(PwrCfgCmd) == PWR_BASEADDR_SDIO)
+						value = SdioLocalCmd52Read1Byte(padapter, offset);
+					else
+#endif
+						value = rtw_read8(padapter, offset);
+
+					value = value & GET_PWR_CFG_MASK(PwrCfgCmd);
+					if (value == (GET_PWR_CFG_VALUE(PwrCfgCmd) & GET_PWR_CFG_MASK(PwrCfgCmd)))
+						bPollingBit = _TRUE;
+					else
+						rtw_udelay_os(10);
+
+					if (pollingCount++ > maxPollingCnt) {
+						RTW_ERR("HalPwrSeqCmdParsing: Fail to polling Offset[%#x]=%02x\n", offset, value);
+
+						/* For PCIE + USB package poll power bit timeout issue only modify 8821AE and 8723BE */
+						if (bHWICSupport && offset == 0x06  && flag == 0) {
+
+							RTW_ERR("[WARNING] PCIE polling(0x%X) timeout(%d), Toggle 0x04[3] and try again.\n", offset, maxPollingCnt);
+							if (IS_HARDWARE_TYPE_8723DE(padapter))
+								PlatformEFIOWrite1Byte(padapter, 0x40, (PlatformEFIORead1Byte(padapter, 0x40)) & (~BIT3));
+
+							PlatformEFIOWrite1Byte(padapter, 0x04, PlatformEFIORead1Byte(padapter, 0x04) | BIT3);
+							PlatformEFIOWrite1Byte(padapter, 0x04, PlatformEFIORead1Byte(padapter, 0x04) & ~BIT3);
+
+							if (IS_HARDWARE_TYPE_8723DE(padapter))
+								PlatformEFIOWrite1Byte(padapter, 0x40, PlatformEFIORead1Byte(padapter, 0x40)|BIT3);
+
+							/* Retry Polling Process one more time */
+							pollingCount = 0;
+							flag = 1;
+						} else {
+							return _FALSE;
+						}
+					}
+				} while (!bPollingBit);
+
+				break;
+
+			case PWR_CMD_DELAY:
+				if (GET_PWR_CFG_VALUE(PwrCfgCmd) == PWRSEQ_DELAY_US)
+					rtw_udelay_os(GET_PWR_CFG_OFFSET(PwrCfgCmd));
+				else
+					rtw_udelay_os(GET_PWR_CFG_OFFSET(PwrCfgCmd) * 1000);
+				break;
+
+			case PWR_CMD_END:
+				/* When this command is parsed, end the process */
+				return _TRUE;
+				break;
+
+			default:
+				break;
+			}
+		}
+
+		AryIdx++;/* Add Array Index */
+	} while (1);
+
+	return _TRUE;
+}
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/led/hal_led.c linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/led/hal_led.c
--- linux-5.6.3/3rdparty/rtl8821ce/hal/led/hal_led.c	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/led/hal_led.c	2020-04-10 16:35:06.817660114 +0300
@@ -0,0 +1,254 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+
+#include <drv_types.h>
+#include <hal_data.h>
+
+#ifdef CONFIG_RTW_LED
+void dump_led_config(void *sel, _adapter *adapter)
+{
+	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
+	struct led_priv	*ledpriv = adapter_to_led(adapter);
+	int i;
+
+	RTW_PRINT_SEL(sel, "strategy:%u\n", ledpriv->LedStrategy);
+#ifdef CONFIG_RTW_SW_LED
+	RTW_PRINT_SEL(sel, "bRegUseLed:%u\n", ledpriv->bRegUseLed);
+	RTW_PRINT_SEL(sel, "iface_en_mask:0x%02X\n", ledpriv->iface_en_mask);
+	for (i = 0; i < dvobj->iface_nums; i++)
+		RTW_PRINT_SEL(sel, "ctl_en_mask[%d]:0x%08X\n", i, ledpriv->ctl_en_mask[i]);
+#endif
+}
+
+void rtw_led_set_strategy(_adapter *adapter, u8 strategy)
+{
+	struct led_priv *ledpriv = adapter_to_led(adapter);
+	_adapter *pri_adapter = GET_PRIMARY_ADAPTER(adapter);
+
+#ifndef CONFIG_RTW_SW_LED
+	if (IS_SW_LED_STRATEGY(strategy)) {
+		RTW_WARN("CONFIG_RTW_SW_LED is not defined\n");
+		return;
+	}
+#endif
+
+#ifdef CONFIG_RTW_SW_LED
+	if (!ledpriv->bRegUseLed)
+		return;
+#endif
+
+	if (ledpriv->LedStrategy == strategy)
+		return;
+
+	if (IS_HW_LED_STRATEGY(strategy) || IS_HW_LED_STRATEGY(ledpriv->LedStrategy)) {
+		RTW_WARN("switching on/off HW_LED strategy is not supported\n");
+		return;
+	}
+
+	ledpriv->LedStrategy = strategy;
+
+#ifdef CONFIG_RTW_SW_LED
+	rtw_hal_sw_led_deinit(pri_adapter);
+#endif
+
+	rtw_led_control(pri_adapter, RTW_LED_OFF);
+}
+
+#ifdef CONFIG_RTW_SW_LED
+#if CONFIG_RTW_SW_LED_TRX_DA_CLASSIFY
+void rtw_sw_led_blink_uc_trx_only(LED_DATA *led)
+{
+	_adapter *adapter = led->padapter;
+	BOOLEAN bStopBlinking = _FALSE;
+
+	if (led->BlinkingLedState == RTW_LED_ON)
+		SwLedOn(adapter, led);
+	else
+		SwLedOff(adapter, led);
+
+	switch (led->CurrLedState) {
+	case RTW_LED_ON:
+		SwLedOn(adapter, led);
+		break;
+
+	case RTW_LED_OFF:
+		SwLedOff(adapter, led);
+		break;
+
+	case LED_BLINK_TXRX:
+		led->BlinkTimes--;
+		if (led->BlinkTimes == 0)
+			bStopBlinking = _TRUE;
+
+		if (adapter_to_pwrctl(adapter)->rf_pwrstate != rf_on
+			&& adapter_to_pwrctl(adapter)->rfoff_reason > RF_CHANGE_BY_PS
+		) {
+			SwLedOff(adapter, led);
+			led->bLedBlinkInProgress = _FALSE;
+		} else {
+			if (led->bLedOn)
+				led->BlinkingLedState = RTW_LED_OFF;
+			else
+				led->BlinkingLedState = RTW_LED_ON;
+			
+			if (bStopBlinking) {
+				led->CurrLedState = RTW_LED_OFF;
+				led->bLedBlinkInProgress = _FALSE;
+			}
+			_set_timer(&(led->BlinkTimer), LED_BLINK_FASTER_INTERVAL_ALPHA);
+		}
+		break;
+
+	default:
+		break;
+	}
+}
+
+void rtw_sw_led_ctl_mode_uc_trx_only(_adapter *adapter, LED_CTL_MODE ctl)
+{
+	struct led_priv	*ledpriv = adapter_to_led(adapter);
+	LED_DATA *led = &(ledpriv->SwLed0);
+	LED_DATA *led1 = &(ledpriv->SwLed1);
+	LED_DATA *led2 = &(ledpriv->SwLed2);
+
+	switch (ctl) {
+	case LED_CTL_UC_TX:
+	case LED_CTL_UC_RX:
+		if (led->bLedBlinkInProgress == _FALSE) {
+			led->bLedBlinkInProgress = _TRUE;
+			led->CurrLedState = LED_BLINK_TXRX;
+			led->BlinkTimes = 2;
+			if (led->bLedOn)
+				led->BlinkingLedState = RTW_LED_OFF;
+			else
+				led->BlinkingLedState = RTW_LED_ON;
+			_set_timer(&(led->BlinkTimer), LED_BLINK_FASTER_INTERVAL_ALPHA);
+		}
+		break;
+
+	case LED_CTL_POWER_OFF:
+		led->CurrLedState = RTW_LED_OFF;
+		led->BlinkingLedState = RTW_LED_OFF;
+
+		if (led->bLedBlinkInProgress) {
+			_cancel_timer_ex(&(led->BlinkTimer));
+			led->bLedBlinkInProgress = _FALSE;
+		}
+
+		SwLedOff(adapter, led);
+		SwLedOff(adapter, led1);
+		SwLedOff(adapter, led2);
+		break;
+
+	default:
+		break;
+	}
+}
+#endif /* CONFIG_RTW_SW_LED_TRX_DA_CLASSIFY */
+
+void rtw_led_control(_adapter *adapter, LED_CTL_MODE ctl)
+{
+	struct led_priv	*ledpriv = adapter_to_led(adapter);
+
+	if (ledpriv->LedControlHandler) {
+		#if CONFIG_RTW_SW_LED_TRX_DA_CLASSIFY
+		if (ledpriv->LedStrategy != SW_LED_MODE_UC_TRX_ONLY) {
+			if (ctl == LED_CTL_UC_TX || ctl == LED_CTL_BMC_TX) {
+				if (ledpriv->ctl_en_mask[adapter->iface_id] & BIT(LED_CTL_TX))
+					ctl = LED_CTL_TX; /* transform specific TX ctl to general TX ctl */
+			} else if (ctl == LED_CTL_UC_RX || ctl == LED_CTL_BMC_RX) {
+				if (ledpriv->ctl_en_mask[adapter->iface_id] & BIT(LED_CTL_RX))
+					ctl = LED_CTL_RX; /* transform specific RX ctl to general RX ctl */
+			}
+		}
+		#endif
+
+		if ((ledpriv->iface_en_mask & BIT(adapter->iface_id))
+			&& (ledpriv->ctl_en_mask[adapter->iface_id] & BIT(ctl)))
+			ledpriv->LedControlHandler(adapter, ctl);
+	}
+}
+
+void rtw_led_tx_control(_adapter *adapter, const u8 *da)
+{
+#if CONFIG_RTW_SW_LED_TRX_DA_CLASSIFY
+	if (IS_MCAST(da))
+		rtw_led_control(adapter, LED_CTL_BMC_TX);
+	else
+		rtw_led_control(adapter, LED_CTL_UC_TX);
+#else
+	rtw_led_control(adapter, LED_CTL_TX);
+#endif
+}
+
+void rtw_led_rx_control(_adapter *adapter, const u8 *da)
+{
+#if CONFIG_RTW_SW_LED_TRX_DA_CLASSIFY
+	if (IS_MCAST(da))
+		rtw_led_control(adapter, LED_CTL_BMC_RX);
+	else
+		rtw_led_control(adapter, LED_CTL_UC_RX);
+#else
+	rtw_led_control(adapter, LED_CTL_RX);
+#endif
+}
+
+void rtw_led_set_iface_en(_adapter *adapter, u8 en)
+{
+	struct led_priv *ledpriv = adapter_to_led(adapter);
+
+	if (en)
+		ledpriv->iface_en_mask |= BIT(adapter->iface_id);
+	else
+		ledpriv->iface_en_mask &= ~BIT(adapter->iface_id);
+}
+
+void rtw_led_set_iface_en_mask(_adapter *adapter, u8 mask)
+{
+	struct led_priv *ledpriv = adapter_to_led(adapter);
+
+	ledpriv->iface_en_mask = mask;
+}
+
+void rtw_led_set_ctl_en_mask(_adapter *adapter, u32 ctl_mask)
+{
+	struct led_priv *ledpriv = adapter_to_led(adapter);
+	
+#if CONFIG_RTW_SW_LED_TRX_DA_CLASSIFY
+	if (ctl_mask & BIT(LED_CTL_TX))
+		ctl_mask |= BIT(LED_CTL_UC_TX) | BIT(LED_CTL_BMC_TX);
+	if (ctl_mask & BIT(LED_CTL_RX))
+		ctl_mask |= BIT(LED_CTL_UC_RX) | BIT(LED_CTL_BMC_RX);
+#endif
+
+	ledpriv->ctl_en_mask[adapter->iface_id] = ctl_mask;
+}
+
+void rtw_led_set_ctl_en_mask_primary(_adapter *adapter)
+{
+	rtw_led_set_ctl_en_mask(adapter, 0xFFFFFFFF);
+}
+
+void rtw_led_set_ctl_en_mask_virtual(_adapter *adapter)
+{
+	rtw_led_set_ctl_en_mask(adapter
+		, BIT(LED_CTL_POWER_ON) | BIT(LED_CTL_POWER_OFF)
+		| BIT(LED_CTL_TX) | BIT(LED_CTL_RX)
+	);
+}
+#endif /* CONFIG_RTW_SW_LED */
+
+#endif /* CONFIG_RTW_LED */
+
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/led/hal_pci_led.c linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/led/hal_pci_led.c
--- linux-5.6.3/3rdparty/rtl8821ce/hal/led/hal_pci_led.c	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/led/hal_pci_led.c	2020-04-10 16:35:06.818660161 +0300
@@ -0,0 +1,2169 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+
+#include <drv_types.h>
+#include <hal_data.h>
+#ifdef CONFIG_RTW_SW_LED
+
+/*
+ *	Description:
+ *		Turn on LED according to LedPin specified.
+ *   */
+VOID
+HwLedBlink(
+	IN	PADAPTER			Adapter,
+	IN	PLED_PCIE			pLed
+)
+{
+
+
+	switch (pLed->LedPin) {
+	case LED_PIN_GPIO0:
+		break;
+
+	case LED_PIN_LED0:
+		/* rtw_write8(Adapter, LED0Cfg, 0x2); */
+		break;
+
+	case LED_PIN_LED1:
+		/* rtw_write8(Adapter, LED1Cfg, 0x2); */
+		break;
+
+	default:
+		break;
+	}
+
+	pLed->bLedOn = _TRUE;
+}
+
+/*
+ *	Description:
+ *		Implement LED blinking behavior for SW_LED_MODE0.
+ *		It toggle off LED and schedule corresponding timer if necessary.
+ *   */
+VOID
+SwLedBlink(
+	IN PLED_PCIE		pLed
+)
+{
+	PADAPTER		Adapter = pLed->padapter;
+	struct mlme_priv	*pmlmepriv = &(Adapter->mlmepriv);
+	BOOLEAN bStopBlinking = _FALSE;
+
+	/* Change LED according to BlinkingLedState specified. */
+	if (pLed->BlinkingLedState == RTW_LED_ON) {
+		SwLedOn(Adapter, pLed);
+	} else {
+		SwLedOff(Adapter, pLed);
+	}
+
+	/* Determine if we shall change LED state again. */
+	pLed->BlinkTimes--;
+	switch (pLed->CurrLedState) {
+	case LED_BLINK_NORMAL:
+	case LED_BLINK_TXRX:
+	case LED_BLINK_RUNTOP:
+		if (pLed->BlinkTimes == 0)
+			bStopBlinking = _TRUE;
+		break;
+
+	case LED_BLINK_SCAN:
+		if (((check_fwstate(pmlmepriv, WIFI_STATION_STATE) && check_fwstate(pmlmepriv, _FW_LINKED)) ||
+		     (check_fwstate(pmlmepriv, WIFI_ADHOC_STATE) || check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE))) &&     /* Linked. */
+		    (!check_fwstate(pmlmepriv, _FW_UNDER_SURVEY)) && /* Not in scan stage. */
+		    (pLed->BlinkTimes % 2 == 0)) /* Even */
+			bStopBlinking = _TRUE;
+		break;
+
+	case LED_BLINK_NO_LINK:
+	case LED_BLINK_StartToBlink:
+		if (check_fwstate(pmlmepriv, _FW_LINKED) && check_fwstate(pmlmepriv, WIFI_STATION_STATE))
+			bStopBlinking = _TRUE;
+		else if ((check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE) &&
+			(check_fwstate(pmlmepriv, WIFI_ADHOC_STATE) || check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE)))
+			bStopBlinking = _TRUE;
+		else if (pLed->BlinkTimes == 0)
+			bStopBlinking = _TRUE;
+		break;
+
+	case LED_BLINK_CAMEO:
+		if (check_fwstate(pmlmepriv, _FW_LINKED) && check_fwstate(pmlmepriv, WIFI_STATION_STATE))
+			bStopBlinking = _TRUE;
+		else if (check_fwstate(pmlmepriv, _FW_LINKED) &&
+			(check_fwstate(pmlmepriv, WIFI_ADHOC_STATE) || check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE)))
+			bStopBlinking = _TRUE;
+		break;
+
+	default:
+		bStopBlinking = _TRUE;
+		break;
+	}
+
+	if (bStopBlinking) {
+		if (adapter_to_pwrctl(Adapter)->rf_pwrstate != rf_on)
+			SwLedOff(Adapter, pLed);
+		else if (pLed->CurrLedState == LED_BLINK_TXRX)
+			SwLedOff(Adapter, pLed);
+		else if (pLed->CurrLedState == LED_BLINK_RUNTOP)
+			SwLedOff(Adapter, pLed);
+		else if ((check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE) && pLed->bLedOn == _FALSE)
+			SwLedOn(Adapter, pLed);
+		else if ((check_fwstate(pmlmepriv, _FW_LINKED) == _FALSE) &&  pLed->bLedOn == _TRUE)
+			SwLedOff(Adapter, pLed);
+
+		pLed->BlinkTimes = 0;
+		pLed->bLedBlinkInProgress = _FALSE;
+	} else {
+		/* Assign LED state to toggle. */
+		if (pLed->BlinkingLedState == RTW_LED_ON)
+			pLed->BlinkingLedState = RTW_LED_OFF;
+		else
+			pLed->BlinkingLedState = RTW_LED_ON;
+
+		/* Schedule a timer to toggle LED state. */
+		switch (pLed->CurrLedState) {
+		case LED_BLINK_NORMAL:
+		case LED_BLINK_TXRX:
+		case LED_BLINK_StartToBlink:
+			_set_timer(&(pLed->BlinkTimer), LED_BLINK_NORMAL_INTERVAL);
+			break;
+
+		case LED_BLINK_SLOWLY:
+			_set_timer(&(pLed->BlinkTimer), LED_BLINK_SLOWLY_INTERVAL);
+			break;
+
+		case LED_BLINK_SCAN:
+		case LED_BLINK_NO_LINK:
+			if (pLed->bLedOn)
+				_set_timer(&(pLed->BlinkTimer), LED_CM2_BLINK_ON_INTERVAL);
+			else
+				_set_timer(&(pLed->BlinkTimer), LED_CM2_BLINK_OFF_INTERVAL);
+			break;
+
+		case LED_BLINK_RUNTOP:
+			_set_timer(&(pLed->BlinkTimer), LED_RunTop_BLINK_INTERVAL);
+			break;
+
+		case LED_BLINK_CAMEO:
+			_set_timer(&(pLed->BlinkTimer), LED_BLINK_SLOWLY_INTERVAL_PORNET);
+			break;
+
+		default:
+			/* RTW_INFO("SwLedCm2Blink(): unexpected state!\n"); */
+			_set_timer(&(pLed->BlinkTimer), LED_BLINK_SLOWLY_INTERVAL);
+			break;
+		}
+	}
+}
+
+VOID
+SwLedBlink5(
+	IN PLED_PCIE		pLed
+)
+{
+	PADAPTER		Adapter = pLed->padapter;
+	struct mlme_priv	*pmlmepriv = &(Adapter->mlmepriv);
+	BOOLEAN bStopBlinking = _FALSE;
+
+	/* Change LED according to BlinkingLedState specified. */
+	if (pLed->BlinkingLedState == RTW_LED_ON) {
+		SwLedOn(Adapter, pLed);
+	} else {
+		SwLedOff(Adapter, pLed);
+	}
+
+	switch (pLed->CurrLedState) {
+	case RTW_LED_OFF:
+		SwLedOff(Adapter, pLed);
+		break;
+
+	case LED_BLINK_SLOWLY:
+		if (pLed->bLedOn)
+			pLed->BlinkingLedState = RTW_LED_OFF;
+		else
+			pLed->BlinkingLedState = RTW_LED_ON;
+		_set_timer(&(pLed->BlinkTimer), LED_BLINK_SLOWLY_INTERVAL_NETTRONIX);
+		break;
+
+	case LED_BLINK_NORMAL:
+		pLed->BlinkTimes--;
+		if (pLed->BlinkTimes == 0)
+			bStopBlinking = _TRUE;
+		if (bStopBlinking) {
+			if (adapter_to_pwrctl(Adapter)->rf_pwrstate != rf_on)
+				SwLedOff(Adapter, pLed);
+			else {
+				pLed->bLedSlowBlinkInProgress = _TRUE;
+				pLed->CurrLedState = LED_BLINK_SLOWLY;
+				if (pLed->bLedOn)
+					pLed->BlinkingLedState = RTW_LED_OFF;
+				else
+					pLed->BlinkingLedState = RTW_LED_ON;
+				_set_timer(&(pLed->BlinkTimer), LED_BLINK_SLOWLY_INTERVAL_NETTRONIX);
+			}
+			pLed->BlinkTimes = 0;
+			pLed->bLedBlinkInProgress = _FALSE;
+		} else {
+			if (adapter_to_pwrctl(Adapter)->rf_pwrstate != rf_on)
+				SwLedOff(Adapter, pLed);
+			else {
+				if (pLed->bLedOn)
+					pLed->BlinkingLedState = RTW_LED_OFF;
+				else
+					pLed->BlinkingLedState = RTW_LED_ON;
+
+				_set_timer(&(pLed->BlinkTimer), LED_BLINK_NORMAL_INTERVAL_NETTRONIX);
+			}
+		}
+		break;
+
+	default:
+		break;
+	}
+
+}
+
+
+VOID
+SwLedBlink6(
+	IN PLED_PCIE		pLed
+)
+{
+	PADAPTER		Adapter = pLed->padapter;
+	struct mlme_priv	*pmlmepriv = &(Adapter->mlmepriv);
+	BOOLEAN bStopBlinking = _FALSE;
+
+	/* Change LED according to BlinkingLedState specified. */
+	if (pLed->BlinkingLedState == RTW_LED_ON) {
+		SwLedOn(Adapter, pLed);
+	} else {
+		SwLedOff(Adapter, pLed);
+	}
+
+	switch (pLed->CurrLedState) {
+	case RTW_LED_OFF:
+		SwLedOff(Adapter, pLed);
+		break;
+
+	case LED_BLINK_SLOWLY:
+		if (pLed->bLedOn)
+			pLed->BlinkingLedState = RTW_LED_OFF;
+		else
+			pLed->BlinkingLedState = RTW_LED_ON;
+		_set_timer(&(pLed->BlinkTimer), LED_BLINK_SLOWLY_INTERVAL_PORNET);
+		break;
+
+	case LED_BLINK_NORMAL:
+		pLed->BlinkTimes--;
+		if (pLed->BlinkTimes == 0)
+			bStopBlinking = _TRUE;
+		if (bStopBlinking) {
+			if (adapter_to_pwrctl(Adapter)->rf_pwrstate != rf_on)
+				SwLedOff(Adapter, pLed);
+			else {
+				pLed->bLedSlowBlinkInProgress = _TRUE;
+				pLed->CurrLedState = LED_BLINK_SLOWLY;
+				if (pLed->bLedOn)
+					pLed->BlinkingLedState = RTW_LED_OFF;
+				else
+					pLed->BlinkingLedState = RTW_LED_ON;
+				_set_timer(&(pLed->BlinkTimer), LED_BLINK_SLOWLY_INTERVAL_PORNET);
+			}
+			pLed->BlinkTimes = 0;
+			pLed->bLedBlinkInProgress = _FALSE;
+		} else {
+			if (adapter_to_pwrctl(Adapter)->rf_pwrstate != rf_on)
+				SwLedOff(Adapter, pLed);
+			else {
+				if (pLed->bLedOn)
+					pLed->BlinkingLedState = RTW_LED_OFF;
+				else
+					pLed->BlinkingLedState = RTW_LED_ON;
+
+				_set_timer(&(pLed->BlinkTimer), LED_BLINK_NORMAL_INTERVAL_PORNET);
+			}
+		}
+		break;
+
+	default:
+		break;
+	}
+
+}
+
+VOID
+SwLedBlink7(
+	IN PLED_PCIE		pLed
+)
+{
+	PADAPTER		Adapter = pLed->padapter;
+
+	SwLedOn(Adapter, pLed);
+}
+
+
+
+/*
+ *	Description:
+ *		Implement LED blinking behavior for SW_LED_MODE8.
+ *		It toggle off LED and schedule corresponding timer if necessary.
+ *   */
+VOID
+SwLedBlink8(
+	IN PLED_PCIE		pLed
+)
+{
+	PADAPTER		Adapter = pLed->padapter;
+	struct mlme_priv	*pmlmepriv = &(Adapter->mlmepriv);
+	BOOLEAN bStopBlinking = _FALSE;
+
+	/* Change LED according to BlinkingLedState specified. */
+	if (pLed->BlinkingLedState == RTW_LED_ON) {
+		SwLedOn(Adapter, pLed);
+	} else {
+		SwLedOff(Adapter, pLed);
+	}
+
+
+	/* Determine if we shall change LED state again. */
+	if (pLed->CurrLedState != LED_BLINK_NO_LINK)
+		pLed->BlinkTimes--;
+
+	switch (pLed->CurrLedState) {
+	case LED_BLINK_NORMAL:
+	case LED_BLINK_SCAN:
+		if (pLed->BlinkTimes == 0)
+			bStopBlinking = _TRUE;
+		break;
+
+	default:
+		break;
+	}
+
+	if (bStopBlinking) {
+		if (adapter_to_pwrctl(Adapter)->rf_pwrstate != rf_on && adapter_to_pwrctl(Adapter)->rfoff_reason > RF_CHANGE_BY_PS) {
+			pLed->CurrLedState = RTW_LED_OFF;
+			SwLedOff(Adapter, pLed);
+		} else {
+			pLed->CurrLedState = RTW_LED_ON;
+			SwLedOn(Adapter, pLed);
+		}
+
+		pLed->BlinkTimes = 0;
+		pLed->bLedBlinkInProgress = _FALSE;
+	} else {
+		/* Assign LED state to toggle. */
+		if (pLed->BlinkingLedState == RTW_LED_ON)
+			pLed->BlinkingLedState = RTW_LED_OFF;
+		else
+			pLed->BlinkingLedState = RTW_LED_ON;
+
+		/* Schedule a timer to toggle LED state. */
+		switch (pLed->CurrLedState) {
+		case LED_BLINK_NORMAL:
+			_set_timer(&(pLed->BlinkTimer), LED_BLINK_NORMAL_INTERVAL);
+			break;
+
+		default:
+			/* RTW_INFO("SwLedCm8Blink(): unexpected state!\n"); */
+			break;
+		}
+	}
+}
+
+VOID
+SwLedBlink9(
+	IN PLED_PCIE		pLed
+)
+{
+	PADAPTER		Adapter = pLed->padapter;
+	struct mlme_priv	*pmlmepriv = &(Adapter->mlmepriv);
+	BOOLEAN bStopBlinking = _FALSE;
+
+	/* Change LED according to BlinkingLedState specified. */
+	if (pLed->BlinkingLedState == RTW_LED_ON) {
+		SwLedOn(Adapter, pLed);
+	} else {
+		SwLedOff(Adapter, pLed);
+	}
+
+	/* Determine if we shall change LED state again. */
+	if (pLed->CurrLedState != LED_BLINK_NO_LINK)
+		pLed->BlinkTimes--;
+
+	switch (pLed->CurrLedState) {
+	case LED_BLINK_NORMAL:
+	case LED_BLINK_SCAN:
+		if (pLed->BlinkTimes == 0)
+			bStopBlinking = _TRUE;
+		break;
+
+	case LED_BLINK_NO_LINK:
+		if (check_fwstate(pmlmepriv, _FW_LINKED) && check_fwstate(pmlmepriv, WIFI_STATION_STATE))
+			bStopBlinking = _TRUE;
+		else if (check_fwstate(pmlmepriv, _FW_LINKED) &&
+			(check_fwstate(pmlmepriv, WIFI_ADHOC_STATE) || check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE)))
+			bStopBlinking = _TRUE;
+		break;
+
+	default:
+		break;
+	}
+
+	if (bStopBlinking) {
+		if (adapter_to_pwrctl(Adapter)->rf_pwrstate != rf_on && adapter_to_pwrctl(Adapter)->rfoff_reason > RF_CHANGE_BY_PS) {
+			pLed->CurrLedState = RTW_LED_OFF;
+			SwLedOff(Adapter, pLed);
+		} else if (check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE) {
+			pLed->CurrLedState = RTW_LED_ON;
+			SwLedOn(Adapter, pLed);
+		} else if (check_fwstate(pmlmepriv, _FW_LINKED) == _FALSE) {
+			pLed->CurrLedState = LED_BLINK_NO_LINK;
+			if (pLed->bLedOn)
+				_set_timer(&(pLed->BlinkTimer), LED_CM2_BLINK_ON_INTERVAL);
+			else
+				_set_timer(&(pLed->BlinkTimer), LED_CM8_BLINK_OFF_INTERVAL);
+		}
+
+		pLed->BlinkTimes = 0;
+		if (pLed->CurrLedState != LED_BLINK_NO_LINK)
+			pLed->bLedBlinkInProgress = _FALSE;
+	} else {
+		/* Assign LED state to toggle. */
+		if (pLed->BlinkingLedState == RTW_LED_ON)
+			pLed->BlinkingLedState = RTW_LED_OFF;
+		else
+			pLed->BlinkingLedState = RTW_LED_ON;
+
+		/* Schedule a timer to toggle LED state. */
+		switch (pLed->CurrLedState) {
+		case LED_BLINK_NORMAL:
+			_set_timer(&(pLed->BlinkTimer), LED_BLINK_FAST_INTERVAL_BITLAND);
+			break;
+
+		case LED_BLINK_SCAN:
+		case LED_BLINK_NO_LINK:
+			if (pLed->bLedOn)
+				_set_timer(&(pLed->BlinkTimer), LED_CM2_BLINK_ON_INTERVAL);
+			else
+				_set_timer(&(pLed->BlinkTimer), LED_CM8_BLINK_OFF_INTERVAL);
+			break;
+
+		default:
+			/* RTW_INFO("SwLedCm2Blink(): unexpected state!\n"); */
+			break;
+		}
+	}
+
+
+}
+
+
+VOID
+SwLedBlink10(
+	IN PLED_PCIE		pLed
+)
+{
+	PADAPTER		Adapter = pLed->padapter;
+	struct mlme_priv	*pmlmepriv = &(Adapter->mlmepriv);
+	BOOLEAN bStopBlinking = _FALSE;
+
+	/* Change LED according to BlinkingLedState specified. */
+	if (pLed->BlinkingLedState == RTW_LED_ON) {
+		SwLedOn(Adapter, pLed);
+	} else {
+		SwLedOff(Adapter, pLed);
+	}
+
+	/* Determine if we shall change LED state again. */
+	if (pLed->CurrLedState != LED_BLINK_NO_LINK)
+		pLed->BlinkTimes--;
+
+	switch (pLed->CurrLedState) {
+	case LED_BLINK_NORMAL:
+	case LED_BLINK_SCAN:
+		if (pLed->BlinkTimes == 0)
+			bStopBlinking = _TRUE;
+		break;
+	default:
+		break;
+	}
+
+	if (bStopBlinking) {
+		pLed->CurrLedState = RTW_LED_OFF;
+		SwLedOff(Adapter, pLed);
+
+		pLed->BlinkTimes = 0;
+		pLed->bLedBlinkInProgress = _FALSE;
+	} else {
+		/* Assign LED state to toggle. */
+		if (pLed->BlinkingLedState == RTW_LED_ON)
+			pLed->BlinkingLedState = RTW_LED_OFF;
+		else
+			pLed->BlinkingLedState = RTW_LED_ON;
+
+		/* Schedule a timer to toggle LED state. */
+		switch (pLed->CurrLedState) {
+		case LED_BLINK_NORMAL:
+		case LED_BLINK_SCAN:
+			_set_timer(&(pLed->BlinkTimer), LED_BLINK_FAST_INTERVAL_BITLAND);
+			break;
+
+		default:
+			/* RT_ASSERT(_FALSE, ("SwLedCm2Blink(): unexpected state!\n")); */
+			break;
+		}
+	}
+
+
+}
+
+
+VOID
+SwLedBlink11(
+	IN PLED_PCIE		pLed
+)
+{
+	PADAPTER		Adapter = pLed->padapter;
+	BOOLEAN bStopBlinking = _FALSE;
+
+	/* Change LED according to BlinkingLedState specified. */
+	if (pLed->bLedBlinkInProgress == _TRUE) {
+		if (pLed->BlinkingLedState == RTW_LED_ON) {
+			SwLedOn(Adapter, pLed);
+		} else {
+			SwLedOff(Adapter, pLed);
+		}
+	}
+
+	/* Determine if we shall change LED state again. */
+	if (pLed->CurrLedState != LED_BLINK_NO_LINK)
+		pLed->BlinkTimes--;
+
+	switch (pLed->CurrLedState) {
+	case RTW_LED_ON:
+		bStopBlinking = _TRUE;	/* LED on for 3 seconds */
+	default:
+		break;
+	}
+
+	if (bStopBlinking) {
+		pLed->CurrLedState = RTW_LED_OFF;
+		SwLedOff(Adapter, pLed);
+
+		pLed->BlinkTimes = 0;
+		pLed->bLedBlinkInProgress = _FALSE;
+	} else {
+		/* Assign LED state to toggle. */
+		if (pLed->BlinkingLedState == RTW_LED_ON)
+			pLed->BlinkingLedState = RTW_LED_OFF;
+		else
+			pLed->BlinkingLedState = RTW_LED_ON;
+
+		/* Schedule a timer to toggle LED state. */
+		switch (pLed->CurrLedState) {
+		case LED_BLINK_XAVI:
+			_set_timer(&(pLed->BlinkTimer), LED_CM11_BLINK_INTERVAL);
+			break;
+
+		default:
+			/* RT_ASSERT(_FALSE, ("SwLedCm11Blink(): unexpected state!\n")); */
+			break;
+		}
+	}
+
+
+}
+
+
+VOID
+SwLedBlink12(
+	IN PLED_PCIE		pLed
+)
+{
+	PADAPTER		Adapter = pLed->padapter;
+	struct mlme_priv	*pmlmepriv = &(Adapter->mlmepriv);
+	BOOLEAN bStopBlinking = _FALSE;
+
+	/* Change LED according to BlinkingLedState specified. */
+	if (pLed->BlinkingLedState == RTW_LED_ON) {
+		SwLedOn(Adapter, pLed);
+	} else {
+		SwLedOff(Adapter, pLed);
+	}
+
+	/* Determine if we shall change LED state again. */
+	if (pLed->CurrLedState != LED_BLINK_NO_LINK && pLed->CurrLedState != LED_BLINK_Azurewave_5Mbps
+	    && pLed->CurrLedState != LED_BLINK_Azurewave_10Mbps && pLed->CurrLedState != LED_BLINK_Azurewave_20Mbps
+	    && pLed->CurrLedState != LED_BLINK_Azurewave_40Mbps && pLed->CurrLedState != LED_BLINK_Azurewave_80Mbps
+	    && pLed->CurrLedState != LED_BLINK_Azurewave_MAXMbps)
+		pLed->BlinkTimes--;
+
+	switch (pLed->CurrLedState) {
+	case LED_BLINK_NORMAL:
+	case LED_BLINK_SCAN:
+		if (pLed->BlinkTimes == 0)
+			bStopBlinking = _TRUE;
+		break;
+
+	case LED_BLINK_NO_LINK:
+		if (check_fwstate(pmlmepriv, _FW_LINKED) && check_fwstate(pmlmepriv, WIFI_STATION_STATE))
+			bStopBlinking = _TRUE;
+		else if (check_fwstate(pmlmepriv, _FW_LINKED) &&
+			(check_fwstate(pmlmepriv, WIFI_ADHOC_STATE) || check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE)))
+			bStopBlinking = _TRUE;
+		break;
+
+	case LED_BLINK_Azurewave_5Mbps:
+	case LED_BLINK_Azurewave_10Mbps:
+	case LED_BLINK_Azurewave_20Mbps:
+	case LED_BLINK_Azurewave_40Mbps:
+	case LED_BLINK_Azurewave_80Mbps:
+	case LED_BLINK_Azurewave_MAXMbps:
+	/* if(pTurboCa->TxThroughput + pTurboCa->RxThroughput == 0) */
+	/*	bStopBlinking = _TRUE; */
+
+	default:
+		break;
+	}
+
+	if (bStopBlinking) {
+		if (adapter_to_pwrctl(Adapter)->rf_pwrstate != rf_on && adapter_to_pwrctl(Adapter)->rfoff_reason > RF_CHANGE_BY_PS) {
+			pLed->CurrLedState = RTW_LED_OFF;
+			pLed->BlinkingLedState = RTW_LED_OFF;
+			SwLedOff(Adapter, pLed);
+		} else if (check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE) {
+			pLed->CurrLedState = RTW_LED_ON;
+			pLed->BlinkingLedState = RTW_LED_ON;
+			SwLedOn(Adapter, pLed);
+		} else if (check_fwstate(pmlmepriv, _FW_LINKED) == _FALSE) {
+			pLed->CurrLedState = LED_BLINK_NO_LINK;
+			if (pLed->bLedOn) {
+				pLed->BlinkingLedState = RTW_LED_OFF;
+				_set_timer(&(pLed->BlinkTimer), LED_CM2_BLINK_ON_INTERVAL);
+			} else {
+				pLed->BlinkingLedState = RTW_LED_ON;
+				_set_timer(&(pLed->BlinkTimer), LED_CM8_BLINK_OFF_INTERVAL);
+			}
+		}
+
+		pLed->BlinkTimes = 0;
+		if (pLed->CurrLedState != LED_BLINK_NO_LINK)
+			pLed->bLedBlinkInProgress = _FALSE;
+	} else {
+		/* Assign LED state to toggle. */
+		if (pLed->BlinkingLedState == RTW_LED_ON)
+			pLed->BlinkingLedState = RTW_LED_OFF;
+		else
+			pLed->BlinkingLedState = RTW_LED_ON;
+
+		/* Schedule a timer to toggle LED state. */
+		switch (pLed->CurrLedState) {
+		case LED_BLINK_Azurewave_5Mbps:
+			_set_timer(&(pLed->BlinkTimer), LED_CM12_BLINK_INTERVAL_5Mbps);
+			break;
+
+		case LED_BLINK_Azurewave_10Mbps:
+			_set_timer(&(pLed->BlinkTimer), LED_CM12_BLINK_INTERVAL_10Mbps);
+			break;
+
+		case LED_BLINK_Azurewave_20Mbps:
+			_set_timer(&(pLed->BlinkTimer), LED_CM12_BLINK_INTERVAL_20Mbps);
+			break;
+
+		case LED_BLINK_Azurewave_40Mbps:
+			_set_timer(&(pLed->BlinkTimer), LED_CM12_BLINK_INTERVAL_40Mbps);
+			break;
+
+		case LED_BLINK_Azurewave_80Mbps:
+			_set_timer(&(pLed->BlinkTimer), LED_CM12_BLINK_INTERVAL_80Mbps);
+			break;
+
+		case LED_BLINK_Azurewave_MAXMbps:
+			_set_timer(&(pLed->BlinkTimer), LED_CM12_BLINK_INTERVAL_MAXMbps);
+			break;
+
+		case LED_BLINK_SCAN:
+		case LED_BLINK_NO_LINK:
+			if (pLed->bLedOn)
+				_set_timer(&(pLed->BlinkTimer), LED_CM2_BLINK_ON_INTERVAL);
+			else
+				_set_timer(&(pLed->BlinkTimer), LED_CM8_BLINK_OFF_INTERVAL);
+			break;
+
+		default:
+			/* RT_ASSERT(_FALSE, ("SwLedCm12Blink(): unexpected state!\n")); */
+			break;
+		}
+	}
+
+
+}
+
+/*
+ *	Description:
+ *		Handler function of LED Blinking.
+ *		We dispatch acture LED blink action according to LedStrategy.
+ *   */
+void BlinkHandler(PLED_PCIE pLed)
+{
+	_adapter			*padapter = pLed->padapter;
+	struct led_priv	*ledpriv = adapter_to_led(padapter);
+
+	if (RTW_CANNOT_RUN(padapter))
+		return;
+
+	if (IS_HARDWARE_TYPE_8188E(padapter) ||
+	    IS_HARDWARE_TYPE_JAGUAR(padapter) ||
+	    IS_HARDWARE_TYPE_8723B(padapter) ||
+	    IS_HARDWARE_TYPE_8192E(padapter))
+		return;
+
+	switch (ledpriv->LedStrategy) {
+	#if CONFIG_RTW_SW_LED_TRX_DA_CLASSIFY
+	case SW_LED_MODE_UC_TRX_ONLY:
+		rtw_sw_led_blink_uc_trx_only(pLed);
+		break;
+	#endif
+
+	case SW_LED_MODE1:
+		/* SwLedBlink(pLed); */
+		break;
+	case SW_LED_MODE2:
+		/* SwLedBlink(pLed); */
+		break;
+	case SW_LED_MODE3:
+		/* SwLedBlink(pLed); */
+		break;
+	case SW_LED_MODE5:
+		/* SwLedBlink5(pLed); */
+		break;
+	case SW_LED_MODE6:
+		/* SwLedBlink6(pLed); */
+		break;
+	case SW_LED_MODE7:
+		SwLedBlink7(pLed);
+		break;
+	case SW_LED_MODE8:
+		SwLedBlink8(pLed);
+		break;
+
+	case SW_LED_MODE9:
+		SwLedBlink9(pLed);
+		break;
+
+	case SW_LED_MODE10:
+		SwLedBlink10(pLed);
+		break;
+
+	case SW_LED_MODE11:
+		SwLedBlink11(pLed);
+		break;
+
+	case SW_LED_MODE12:
+		SwLedBlink12(pLed);
+		break;
+
+	default:
+		/* SwLedBlink(pLed); */
+		break;
+	}
+}
+
+/*
+ *	Description:
+ *		Callback function of LED BlinkTimer,
+ *		it just schedules to corresponding BlinkWorkItem/led_blink_hdl
+ *   */
+void BlinkTimerCallback(void *data)
+{
+	PLED_PCIE	 pLed = (PLED_PCIE)data;
+	_adapter		*padapter = pLed->padapter;
+
+	/* RTW_INFO("%s\n", __FUNCTION__); */
+
+	if (RTW_CANNOT_RUN(padapter) || (!rtw_is_hw_init_completed(padapter))) {
+		/*RTW_INFO("%s bDriverStopped:%s, bSurpriseRemoved:%s\n"
+			, __func__
+			, rtw_is_drv_stopped(padapter)?"True":"False"
+			, rtw_is_surprise_removed(padapter)?"True":"False" );
+		*/
+		return;
+	}
+
+#ifdef CONFIG_RTW_LED_HANDLED_BY_CMD_THREAD
+	rtw_led_blink_cmd(padapter, pLed);
+#else
+	BlinkHandler(pLed);
+#endif
+}
+
+/*
+ *	Description:
+ *		Implement each led action for SW_LED_MODE0. */
+VOID
+SwLedControlMode0(
+	IN	PADAPTER			Adapter,
+	IN	LED_CTL_MODE		LedAction
+)
+{
+	struct led_priv	*ledpriv = adapter_to_led(Adapter);
+	PLED_PCIE pLed0 = &(ledpriv->SwLed0);
+	PLED_PCIE pLed1 = &(ledpriv->SwLed1);
+
+	switch (LedAction) {
+	case LED_CTL_TX:
+	case LED_CTL_RX:
+		break;
+
+	case LED_CTL_LINK:
+		pLed0->CurrLedState = RTW_LED_ON;
+		SwLedOn(Adapter, pLed0);
+
+		pLed1->CurrLedState = LED_BLINK_NORMAL;
+		HwLedBlink(Adapter, pLed1);
+		break;
+
+	case LED_CTL_POWER_ON:
+		pLed0->CurrLedState = RTW_LED_OFF;
+		SwLedOff(Adapter, pLed0);
+
+		pLed1->CurrLedState = LED_BLINK_NORMAL;
+		HwLedBlink(Adapter, pLed1);
+
+		break;
+
+	case LED_CTL_POWER_OFF:
+		pLed0->CurrLedState = RTW_LED_OFF;
+		SwLedOff(Adapter, pLed0);
+
+		pLed1->CurrLedState = RTW_LED_OFF;
+		SwLedOff(Adapter, pLed1);
+		break;
+
+	case LED_CTL_SITE_SURVEY:
+		break;
+
+	case LED_CTL_NO_LINK:
+		pLed0->CurrLedState = RTW_LED_OFF;
+		SwLedOff(Adapter, pLed0);
+
+		pLed1->CurrLedState = LED_BLINK_NORMAL;
+		HwLedBlink(Adapter, pLed1);
+		break;
+
+	default:
+		break;
+	}
+
+}
+
+
+VOID
+SwLedControlMode1(
+	IN	PADAPTER			Adapter,
+	IN	LED_CTL_MODE		LedAction
+)
+{
+	struct led_priv	*ledpriv = adapter_to_led(Adapter);
+	struct mlme_priv	*pmlmepriv = &(Adapter->mlmepriv);
+	PLED_PCIE	pLed = &(ledpriv->SwLed1);
+
+	/* Decide led state */
+	switch (LedAction) {
+	case LED_CTL_TX:
+	case LED_CTL_RX:
+		if (pLed->bLedBlinkInProgress == _FALSE) {
+			pLed->bLedBlinkInProgress = _TRUE;
+
+			pLed->CurrLedState = LED_BLINK_NORMAL;
+			pLed->BlinkTimes = 2;
+
+			if (pLed->bLedOn)
+				pLed->BlinkingLedState = RTW_LED_OFF;
+			else
+				pLed->BlinkingLedState = RTW_LED_ON;
+			_set_timer(&(pLed->BlinkTimer), LED_BLINK_NORMAL_INTERVAL);
+		}
+		break;
+
+	case LED_CTL_SITE_SURVEY:
+		if (pLed->bLedBlinkInProgress == _FALSE) {
+			pLed->bLedBlinkInProgress = _TRUE;
+
+			if ((check_fwstate(pmlmepriv, _FW_LINKED) && check_fwstate(pmlmepriv, WIFI_STATION_STATE)) ||
+			    (check_fwstate(pmlmepriv, WIFI_ADHOC_STATE) || check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE))) {
+				pLed->CurrLedState = LED_BLINK_SCAN;
+				pLed->BlinkTimes = 4;
+			} else {
+				pLed->CurrLedState = LED_BLINK_NO_LINK;
+				pLed->BlinkTimes = 24;
+			}
+
+			if (pLed->bLedOn) {
+				pLed->BlinkingLedState = RTW_LED_OFF;
+				_set_timer(&(pLed->BlinkTimer), LED_CM2_BLINK_ON_INTERVAL);
+			} else {
+				pLed->BlinkingLedState = RTW_LED_ON;
+				_set_timer(&(pLed->BlinkTimer), LED_CM2_BLINK_OFF_INTERVAL);
+			}
+		} else {
+			if (pLed->CurrLedState != LED_BLINK_NO_LINK) {
+				if ((check_fwstate(pmlmepriv, _FW_LINKED) && check_fwstate(pmlmepriv, WIFI_STATION_STATE)) ||
+				    (check_fwstate(pmlmepriv, WIFI_ADHOC_STATE) || check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE)))
+					pLed->CurrLedState = LED_BLINK_SCAN;
+				else
+					pLed->CurrLedState = LED_BLINK_NO_LINK;
+			}
+		}
+		break;
+
+	case LED_CTL_NO_LINK:
+		if (pLed->bLedBlinkInProgress == _FALSE) {
+			pLed->bLedBlinkInProgress = _TRUE;
+
+			pLed->CurrLedState = LED_BLINK_NO_LINK;
+			pLed->BlinkTimes = 24;
+
+			if (pLed->bLedOn) {
+				pLed->BlinkingLedState = RTW_LED_OFF;
+				_set_timer(&(pLed->BlinkTimer), LED_CM2_BLINK_ON_INTERVAL);
+			} else {
+				pLed->BlinkingLedState = RTW_LED_ON;
+				_set_timer(&(pLed->BlinkTimer), LED_CM2_BLINK_OFF_INTERVAL);
+			}
+		} else
+			pLed->CurrLedState = LED_BLINK_NO_LINK;
+		break;
+
+	case LED_CTL_LINK:
+		pLed->CurrLedState = RTW_LED_ON;
+		if (pLed->bLedBlinkInProgress == _FALSE)
+			SwLedOn(Adapter, pLed);
+		break;
+
+	case LED_CTL_POWER_OFF:
+		pLed->CurrLedState = RTW_LED_OFF;
+		if (pLed->bLedBlinkInProgress) {
+			_cancel_timer_ex(&(pLed->BlinkTimer));
+			pLed->bLedBlinkInProgress = _FALSE;
+		}
+		SwLedOff(Adapter, pLed);
+		break;
+
+	default:
+		break;
+	}
+
+}
+
+VOID
+SwLedControlMode2(
+	IN	PADAPTER			Adapter,
+	IN	LED_CTL_MODE		LedAction
+)
+{
+	struct led_priv	*ledpriv = adapter_to_led(Adapter);
+	struct mlme_priv	*pmlmepriv = &(Adapter->mlmepriv);
+	PLED_PCIE pLed0 = &(ledpriv->SwLed0);
+	PLED_PCIE pLed1 = &(ledpriv->SwLed1);
+
+	/* Decide led state */
+	switch (LedAction) {
+	case LED_CTL_POWER_ON:
+		pLed0->CurrLedState = RTW_LED_OFF;
+		SwLedOff(Adapter, pLed0);
+
+		pLed1->CurrLedState = LED_BLINK_CAMEO;
+		if (pLed1->bLedBlinkInProgress == _FALSE) {
+			pLed1->bLedBlinkInProgress = _TRUE;
+
+			pLed1->BlinkTimes = 6;
+
+			if (pLed1->bLedOn)
+				pLed1->BlinkingLedState = RTW_LED_OFF;
+			else
+				pLed1->BlinkingLedState = RTW_LED_ON;
+			_set_timer(&(pLed1->BlinkTimer), LED_BLINK_SLOWLY_INTERVAL_PORNET);
+		}
+		break;
+
+	case LED_CTL_TX:
+	case LED_CTL_RX:
+		if (pLed0->bLedBlinkInProgress == _FALSE) {
+			pLed0->bLedBlinkInProgress = _TRUE;
+
+			pLed0->CurrLedState = LED_BLINK_TXRX;
+			pLed0->BlinkTimes = 2;
+
+			if (pLed0->bLedOn)
+				pLed0->BlinkingLedState = RTW_LED_OFF;
+			else
+				pLed0->BlinkingLedState = RTW_LED_ON;
+
+			_set_timer(&(pLed0->BlinkTimer), LED_BLINK_NORMAL_INTERVAL);
+		}
+		break;
+
+	case LED_CTL_NO_LINK:
+		pLed1->CurrLedState = LED_BLINK_CAMEO;
+		if (pLed1->bLedBlinkInProgress == _FALSE) {
+			pLed1->bLedBlinkInProgress = _TRUE;
+
+			pLed1->BlinkTimes = 6;
+
+			if (pLed1->bLedOn)
+				pLed1->BlinkingLedState = RTW_LED_OFF;
+			else
+				pLed1->BlinkingLedState = RTW_LED_ON;
+			_set_timer(&(pLed1->BlinkTimer), LED_BLINK_SLOWLY_INTERVAL_PORNET);
+		}
+		break;
+
+	case LED_CTL_LINK:
+		pLed1->CurrLedState = RTW_LED_ON;
+		if (pLed1->bLedBlinkInProgress == _FALSE)
+			SwLedOn(Adapter, pLed1);
+		break;
+
+	case LED_CTL_POWER_OFF:
+		pLed0->CurrLedState = RTW_LED_OFF;
+		pLed1->CurrLedState = RTW_LED_OFF;
+		if (pLed0->bLedBlinkInProgress) {
+			_cancel_timer_ex(&(pLed0->BlinkTimer));
+			pLed0->bLedBlinkInProgress = _FALSE;
+		}
+		if (pLed1->bLedBlinkInProgress) {
+			_cancel_timer_ex(&(pLed1->BlinkTimer));
+			pLed1->bLedBlinkInProgress = _FALSE;
+		}
+		SwLedOff(Adapter, pLed0);
+		SwLedOff(Adapter, pLed1);
+		break;
+
+	default:
+		break;
+	}
+
+}
+
+
+
+VOID
+SwLedControlMode3(
+	IN	PADAPTER			Adapter,
+	IN	LED_CTL_MODE		LedAction
+)
+{
+	struct led_priv	*ledpriv = adapter_to_led(Adapter);
+	PLED_PCIE pLed0 = &(ledpriv->SwLed0);
+	PLED_PCIE pLed1 = &(ledpriv->SwLed1);
+
+	/* Decide led state */
+	switch (LedAction) {
+	case LED_CTL_POWER_ON:
+		pLed0->CurrLedState = RTW_LED_ON;
+		SwLedOn(Adapter, pLed0);
+		pLed1->CurrLedState = RTW_LED_OFF;
+		SwLedOff(Adapter, pLed1);
+		break;
+
+	case LED_CTL_TX:
+	case LED_CTL_RX:
+		if (pLed1->bLedBlinkInProgress == _FALSE) {
+			pLed1->bLedBlinkInProgress = _TRUE;
+
+			pLed1->CurrLedState = LED_BLINK_RUNTOP;
+			pLed1->BlinkTimes = 2;
+
+			if (pLed1->bLedOn)
+				pLed1->BlinkingLedState = RTW_LED_OFF;
+			else
+				pLed1->BlinkingLedState = RTW_LED_ON;
+
+			_set_timer(&(pLed1->BlinkTimer), LED_RunTop_BLINK_INTERVAL);
+		}
+		break;
+
+	case LED_CTL_POWER_OFF:
+		pLed0->CurrLedState = RTW_LED_OFF;
+		pLed1->CurrLedState = RTW_LED_OFF;
+		if (pLed0->bLedBlinkInProgress) {
+			_cancel_timer_ex(&(pLed0->BlinkTimer));
+			pLed0->bLedBlinkInProgress = _FALSE;
+		}
+		if (pLed1->bLedBlinkInProgress) {
+			_cancel_timer_ex(&(pLed1->BlinkTimer));
+			pLed1->bLedBlinkInProgress = _FALSE;
+		}
+		SwLedOff(Adapter, pLed0);
+		SwLedOff(Adapter, pLed1);
+		break;
+
+	default:
+		break;
+	}
+
+}
+
+
+VOID
+SwLedControlMode4(
+	IN	PADAPTER			Adapter,
+	IN	LED_CTL_MODE		LedAction
+)
+{
+	struct led_priv	*ledpriv = adapter_to_led(Adapter);
+	PLED_PCIE pLed0 = &(ledpriv->SwLed0);
+	PLED_PCIE pLed1 = &(ledpriv->SwLed1);
+
+	/* Decide led state */
+	switch (LedAction) {
+	case LED_CTL_POWER_ON:
+		pLed1->CurrLedState = RTW_LED_ON;
+		SwLedOn(Adapter, pLed1);
+		pLed0->CurrLedState = RTW_LED_OFF;
+		SwLedOff(Adapter, pLed0);
+		break;
+
+	case LED_CTL_TX:
+	case LED_CTL_RX:
+		if (pLed0->bLedBlinkInProgress == _FALSE) {
+			pLed0->bLedBlinkInProgress = _TRUE;
+
+			pLed0->CurrLedState = LED_BLINK_RUNTOP;
+			pLed0->BlinkTimes = 2;
+
+			if (pLed0->bLedOn)
+				pLed0->BlinkingLedState = RTW_LED_OFF;
+			else
+				pLed0->BlinkingLedState = RTW_LED_ON;
+
+			_set_timer(&(pLed0->BlinkTimer), LED_RunTop_BLINK_INTERVAL);
+		}
+		break;
+
+	case LED_CTL_POWER_OFF:
+		pLed0->CurrLedState = RTW_LED_OFF;
+		pLed1->CurrLedState = RTW_LED_OFF;
+		if (pLed0->bLedBlinkInProgress) {
+			_cancel_timer_ex(&(pLed0->BlinkTimer));
+			pLed0->bLedBlinkInProgress = _FALSE;
+		}
+		if (pLed1->bLedBlinkInProgress) {
+			_cancel_timer_ex(&(pLed1->BlinkTimer));
+			pLed1->bLedBlinkInProgress = _FALSE;
+		}
+		SwLedOff(Adapter, pLed0);
+		SwLedOff(Adapter, pLed1);
+		break;
+
+	default:
+		break;
+	}
+
+}
+
+/* added by vivi, for led new mode */
+VOID
+SwLedControlMode5(
+	IN	PADAPTER			Adapter,
+	IN	LED_CTL_MODE		LedAction
+)
+{
+	struct led_priv	*ledpriv = adapter_to_led(Adapter);
+	PLED_PCIE pLed0 = &(ledpriv->SwLed0);
+	PLED_PCIE pLed1 = &(ledpriv->SwLed1);
+	/* Decide led state */
+	switch (LedAction) {
+	case LED_CTL_POWER_ON:
+	case LED_CTL_START_TO_LINK:
+	case LED_CTL_NO_LINK:
+		pLed1->CurrLedState = RTW_LED_OFF;
+		SwLedOff(Adapter, pLed1);
+
+
+		if (pLed0->bLedSlowBlinkInProgress == _FALSE) {
+			pLed0->bLedSlowBlinkInProgress = _TRUE;
+			pLed0->CurrLedState = LED_BLINK_SLOWLY;
+			if (pLed0->bLedOn)
+				pLed0->BlinkingLedState = RTW_LED_OFF;
+			else
+				pLed0->BlinkingLedState = RTW_LED_ON;
+			_set_timer(&(pLed0->BlinkTimer), LED_BLINK_SLOWLY_INTERVAL_NETTRONIX);
+		}
+
+		break;
+
+	case LED_CTL_TX:
+	case LED_CTL_RX:
+		pLed1->CurrLedState = RTW_LED_ON;
+		SwLedOn(Adapter, pLed1);
+
+		if (pLed0->bLedBlinkInProgress == _FALSE) {
+			_cancel_timer_ex(&(pLed0->BlinkTimer));
+			pLed0->bLedSlowBlinkInProgress = _FALSE;
+			pLed0->bLedBlinkInProgress = _TRUE;
+			pLed0->CurrLedState = LED_BLINK_NORMAL;
+			pLed0->BlinkTimes = 2;
+
+			if (pLed0->bLedOn)
+				pLed0->BlinkingLedState = RTW_LED_OFF;
+			else
+				pLed0->BlinkingLedState = RTW_LED_ON;
+			_set_timer(&(pLed0->BlinkTimer), LED_BLINK_NORMAL_INTERVAL_NETTRONIX);
+		}
+		break;
+
+	case LED_CTL_LINK:
+		pLed1->CurrLedState = RTW_LED_ON;
+		SwLedOn(Adapter, pLed1);
+
+		if (pLed0->bLedSlowBlinkInProgress == _FALSE) {
+			pLed0->bLedSlowBlinkInProgress = _TRUE;
+			pLed0->CurrLedState = LED_BLINK_SLOWLY;
+			if (pLed0->bLedOn)
+				pLed0->BlinkingLedState = RTW_LED_OFF;
+			else
+				pLed0->BlinkingLedState = RTW_LED_ON;
+			_set_timer(&(pLed0->BlinkTimer), LED_BLINK_SLOWLY_INTERVAL_NETTRONIX);
+		}
+		break;
+
+
+	case LED_CTL_POWER_OFF:
+		pLed0->CurrLedState = RTW_LED_OFF;
+		pLed1->CurrLedState = RTW_LED_OFF;
+		if (pLed0->bLedSlowBlinkInProgress == _TRUE) {
+			_cancel_timer_ex(&(pLed0->BlinkTimer));
+			pLed0->bLedSlowBlinkInProgress = _FALSE;
+		}
+		if (pLed0->bLedBlinkInProgress == _TRUE) {
+			_cancel_timer_ex(&(pLed0->BlinkTimer));
+			pLed0->bLedBlinkInProgress = _FALSE;
+		}
+		SwLedOff(Adapter, pLed0);
+		SwLedOff(Adapter, pLed1);
+		break;
+
+	default:
+		break;
+	}
+
+
+}
+
+/* added by vivi, for led new mode */
+VOID
+SwLedControlMode6(
+	IN	PADAPTER			Adapter,
+	IN	LED_CTL_MODE		LedAction
+)
+{
+	struct led_priv	*ledpriv = adapter_to_led(Adapter);
+	PLED_PCIE pLed0 = &(ledpriv->SwLed0);
+	PLED_PCIE pLed1 = &(ledpriv->SwLed1);
+
+
+	switch (LedAction) {
+	case LED_CTL_POWER_ON:
+	case LED_CTL_START_TO_LINK:
+	case LED_CTL_NO_LINK:
+	case LED_CTL_LINK:
+	case LED_CTL_SITE_SURVEY:
+		pLed1->CurrLedState = RTW_LED_OFF;
+		SwLedOff(Adapter, pLed1);
+
+		if (pLed0->bLedSlowBlinkInProgress == _FALSE) {
+			pLed0->bLedSlowBlinkInProgress = _TRUE;
+			pLed0->CurrLedState = LED_BLINK_SLOWLY;
+			if (pLed0->bLedOn)
+				pLed0->BlinkingLedState = RTW_LED_OFF;
+			else
+				pLed0->BlinkingLedState = RTW_LED_ON;
+			_set_timer(&(pLed0->BlinkTimer), LED_BLINK_SLOWLY_INTERVAL_PORNET);
+		}
+		break;
+
+	case LED_CTL_TX:
+	case LED_CTL_RX:
+		pLed1->CurrLedState = RTW_LED_OFF;
+		SwLedOff(Adapter, pLed1);
+		if (pLed0->bLedBlinkInProgress == _FALSE) {
+			_cancel_timer_ex(&(pLed0->BlinkTimer));
+			pLed0->bLedSlowBlinkInProgress = _FALSE;
+			pLed0->bLedBlinkInProgress = _TRUE;
+			pLed0->CurrLedState = LED_BLINK_NORMAL;
+			pLed0->BlinkTimes = 2;
+			if (pLed0->bLedOn)
+				pLed0->BlinkingLedState = RTW_LED_OFF;
+			else
+				pLed0->BlinkingLedState = RTW_LED_ON;
+			_set_timer(&(pLed0->BlinkTimer), LED_BLINK_NORMAL_INTERVAL_PORNET);
+		}
+		break;
+
+	case LED_CTL_POWER_OFF:
+		pLed1->CurrLedState = RTW_LED_OFF;
+		SwLedOff(Adapter, pLed1);
+
+		pLed0->CurrLedState = RTW_LED_OFF;
+		if (pLed0->bLedSlowBlinkInProgress == _TRUE) {
+			_cancel_timer_ex(&(pLed0->BlinkTimer));
+			pLed0->bLedSlowBlinkInProgress = _FALSE;
+		}
+		if (pLed0->bLedBlinkInProgress == _TRUE) {
+			_cancel_timer_ex(&(pLed0->BlinkTimer));
+			pLed0->bLedBlinkInProgress = _FALSE;
+		}
+		SwLedOff(Adapter, pLed0);
+		break;
+
+	default:
+		break;
+
+	}
+}
+
+
+/* added by chiyokolin, for Lenovo */
+VOID
+SwLedControlMode7(
+	IN	PADAPTER			Adapter,
+	IN	LED_CTL_MODE		LedAction
+)
+{
+	struct led_priv	*ledpriv = adapter_to_led(Adapter);
+	PLED_PCIE	pLed0 = &(ledpriv->SwLed0);
+
+	switch (LedAction) {
+	case LED_CTL_POWER_ON:
+	case LED_CTL_LINK:
+	case LED_CTL_NO_LINK:
+		SwLedOn(Adapter, pLed0);
+		break;
+
+	case LED_CTL_POWER_OFF:
+		SwLedOff(Adapter, pLed0);
+		break;
+
+	default:
+		break;
+	}
+}
+
+/* added by chiyokolin, for QMI */
+VOID
+SwLedControlMode8(
+	IN	PADAPTER			Adapter,
+	IN	LED_CTL_MODE		LedAction
+)
+{
+	struct led_priv	*ledpriv = adapter_to_led(Adapter);
+	PLED_PCIE pLed = &(ledpriv->SwLed0);
+	struct mlme_priv	*pmlmepriv = &(Adapter->mlmepriv);
+
+	/* Decide led state */
+	switch (LedAction) {
+	case LED_CTL_TX:
+	case LED_CTL_RX:
+		if (pLed->bLedBlinkInProgress == _FALSE && (check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE)) {
+			pLed->bLedBlinkInProgress = _TRUE;
+
+			pLed->CurrLedState = LED_BLINK_NORMAL;
+			pLed->BlinkTimes = 2;
+
+			if (pLed->bLedOn)
+				pLed->BlinkingLedState = RTW_LED_OFF;
+			else
+				pLed->BlinkingLedState = RTW_LED_ON;
+			_set_timer(&(pLed->BlinkTimer), LED_BLINK_NORMAL_INTERVAL);
+		}
+		break;
+
+	case LED_CTL_SITE_SURVEY:
+	case LED_CTL_POWER_ON:
+	case LED_CTL_NO_LINK:
+	case LED_CTL_LINK:
+		pLed->CurrLedState = RTW_LED_ON;
+		if (pLed->bLedBlinkInProgress) {
+			_cancel_timer_ex(&(pLed->BlinkTimer));
+			pLed->bLedBlinkInProgress = _FALSE;
+		}
+		SwLedOn(Adapter, pLed);
+		break;
+
+	case LED_CTL_POWER_OFF:
+		pLed->CurrLedState = RTW_LED_OFF;
+		if (pLed->bLedBlinkInProgress) {
+			_cancel_timer_ex(&(pLed->BlinkTimer));
+			pLed->bLedBlinkInProgress = _FALSE;
+		}
+		SwLedOff(Adapter, pLed);
+		break;
+
+	default:
+		break;
+	}
+}
+
+/* added by chiyokolin, for MSI */
+VOID
+SwLedControlMode9(
+	IN	PADAPTER			Adapter,
+	IN	LED_CTL_MODE		LedAction
+)
+{
+	struct led_priv	*ledpriv = adapter_to_led(Adapter);
+	PLED_PCIE pLed = &(ledpriv->SwLed0);
+	struct mlme_priv	*pmlmepriv = &(Adapter->mlmepriv);
+
+	/* Decide led state */
+	switch (LedAction) {
+	case LED_CTL_TX:
+	case LED_CTL_RX:
+		if (pLed->bLedBlinkInProgress == _FALSE && (check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE)) {
+			pLed->bLedBlinkInProgress = _TRUE;
+
+			pLed->CurrLedState = LED_BLINK_NORMAL;
+			pLed->BlinkTimes = 2;
+
+			if (pLed->bLedOn)
+				pLed->BlinkingLedState = RTW_LED_OFF;
+			else
+				pLed->BlinkingLedState = RTW_LED_ON;
+			_set_timer(&(pLed->BlinkTimer), LED_BLINK_FAST_INTERVAL_BITLAND);
+		}
+		break;
+
+	case LED_CTL_SITE_SURVEY:
+		if (pLed->bLedBlinkInProgress == _FALSE) {
+			pLed->bLedBlinkInProgress = _TRUE;
+			pLed->CurrLedState = LED_BLINK_SCAN;
+			pLed->BlinkTimes = 2;
+
+			if (pLed->bLedOn) {
+				pLed->BlinkingLedState = RTW_LED_OFF;
+				_set_timer(&(pLed->BlinkTimer), LED_CM2_BLINK_ON_INTERVAL);
+			} else {
+				pLed->BlinkingLedState = RTW_LED_ON;
+				_set_timer(&(pLed->BlinkTimer), LED_CM8_BLINK_OFF_INTERVAL);
+			}
+		} else if (pLed->CurrLedState != LED_BLINK_SCAN) {
+			_cancel_timer_ex(&(pLed->BlinkTimer));
+			pLed->CurrLedState = LED_BLINK_SCAN;
+			pLed->BlinkTimes = 2;
+
+			if (pLed->bLedOn) {
+				pLed->BlinkingLedState = RTW_LED_OFF;
+				_set_timer(&(pLed->BlinkTimer), LED_CM2_BLINK_ON_INTERVAL);
+			} else {
+				pLed->BlinkingLedState = RTW_LED_ON;
+				_set_timer(&(pLed->BlinkTimer), LED_CM8_BLINK_OFF_INTERVAL);
+			}
+		}
+		break;
+
+	case LED_CTL_POWER_ON:
+	case LED_CTL_NO_LINK:
+		if (pLed->bLedBlinkInProgress == _FALSE) {
+			pLed->bLedBlinkInProgress = _TRUE;
+
+			pLed->CurrLedState = LED_BLINK_NO_LINK;
+			pLed->BlinkTimes = 24;
+
+			if (pLed->bLedOn) {
+				pLed->BlinkingLedState = RTW_LED_OFF;
+				_set_timer(&(pLed->BlinkTimer), LED_CM2_BLINK_ON_INTERVAL);
+			} else {
+				pLed->BlinkingLedState = RTW_LED_ON;
+				_set_timer(&(pLed->BlinkTimer), LED_CM8_BLINK_OFF_INTERVAL);
+			}
+		} else if (pLed->CurrLedState != LED_BLINK_SCAN && pLed->CurrLedState != LED_BLINK_NO_LINK) {
+			pLed->CurrLedState = LED_BLINK_NO_LINK;
+			pLed->BlinkTimes = 24;
+
+			if (pLed->bLedOn) {
+				pLed->BlinkingLedState = RTW_LED_OFF;
+				_set_timer(&(pLed->BlinkTimer), LED_CM2_BLINK_ON_INTERVAL);
+			} else {
+				pLed->BlinkingLedState = RTW_LED_ON;
+				_set_timer(&(pLed->BlinkTimer), LED_CM8_BLINK_OFF_INTERVAL);
+			}
+		}
+		break;
+
+	case LED_CTL_LINK:
+		pLed->CurrLedState = RTW_LED_ON;
+		if (pLed->bLedBlinkInProgress) {
+			_cancel_timer_ex(&(pLed->BlinkTimer));
+			pLed->bLedBlinkInProgress = _FALSE;
+		}
+		SwLedOn(Adapter, pLed);
+		break;
+
+	case LED_CTL_POWER_OFF:
+		pLed->CurrLedState = RTW_LED_OFF;
+		if (pLed->bLedBlinkInProgress) {
+			_cancel_timer_ex(&(pLed->BlinkTimer));
+			pLed->bLedBlinkInProgress = _FALSE;
+		}
+		SwLedOff(Adapter, pLed);
+		break;
+
+	default:
+		break;
+	}
+
+
+}
+
+
+/* added by chiyokolin, for Edimax-ASUS */
+VOID
+SwLedControlMode10(
+	IN	PADAPTER			Adapter,
+	IN	LED_CTL_MODE		LedAction
+)
+{
+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(Adapter);
+	struct led_priv	*ledpriv = adapter_to_led(Adapter);
+	PLED_PCIE	pLed0 = &(ledpriv->SwLed0);
+	PLED_PCIE	pLed1 = &(ledpriv->SwLed1);
+	struct mlme_priv	*pmlmepriv = &(Adapter->mlmepriv);
+
+	/* Decide led state */
+	switch (LedAction) {
+	case LED_CTL_TX:
+	case LED_CTL_RX:
+		if (pLed1->bLedBlinkInProgress == _FALSE && pLed1->bLedWPSBlinkInProgress == _FALSE &&
+		    (check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE)) {
+			pLed1->bLedBlinkInProgress = _TRUE;
+
+			pLed1->CurrLedState = LED_BLINK_NORMAL;
+			pLed1->BlinkTimes = 2;
+
+			if (pLed1->bLedOn)
+				pLed1->BlinkingLedState = RTW_LED_OFF;
+			else
+				pLed1->BlinkingLedState = RTW_LED_ON;
+			_set_timer(&(pLed1->BlinkTimer), LED_BLINK_NORMAL_INTERVAL);
+		}
+		break;
+
+	case LED_CTL_SITE_SURVEY:
+		if (pLed1->bLedBlinkInProgress == _FALSE && pLed1->bLedWPSBlinkInProgress == _FALSE) {
+			pLed1->bLedBlinkInProgress = _TRUE;
+			pLed1->CurrLedState = LED_BLINK_SCAN;
+			pLed1->BlinkTimes = 12;
+
+			if (pLed1->bLedOn) {
+				pLed1->BlinkingLedState = RTW_LED_OFF;
+				_set_timer(&(pLed1->BlinkTimer), LED_BLINK_NORMAL_INTERVAL);
+			} else {
+				pLed1->BlinkingLedState = RTW_LED_ON;
+				_set_timer(&(pLed1->BlinkTimer), LED_BLINK_NORMAL_INTERVAL);
+			}
+		} else if (pLed1->CurrLedState != LED_BLINK_SCAN && pLed1->bLedWPSBlinkInProgress == _FALSE) {
+			_cancel_timer_ex(&(pLed1->BlinkTimer));
+			pLed1->CurrLedState = LED_BLINK_SCAN;
+			pLed1->BlinkTimes = 24;
+
+			if (pLed1->bLedOn) {
+				pLed1->BlinkingLedState = RTW_LED_OFF;
+				_set_timer(&(pLed1->BlinkTimer), LED_BLINK_NORMAL_INTERVAL);
+			} else {
+				pLed1->BlinkingLedState = RTW_LED_ON;
+				_set_timer(&(pLed1->BlinkTimer), LED_BLINK_NORMAL_INTERVAL);
+			}
+		}
+		break;
+
+	case LED_CTL_START_WPS:
+	case LED_CTL_START_WPS_BOTTON:
+		pLed1->CurrLedState = RTW_LED_ON;
+		if (pLed1->bLedBlinkInProgress == _TRUE) {
+			_cancel_timer_ex(&(pLed1->BlinkTimer));
+			pLed1->bLedBlinkInProgress = _FALSE;
+		}
+
+		if (pLed1->bLedWPSBlinkInProgress == _FALSE) {
+			pLed1->bLedWPSBlinkInProgress = _TRUE;
+			SwLedOn(Adapter, pLed1);
+		}
+		break;
+
+	case	LED_CTL_STOP_WPS:
+	case	LED_CTL_STOP_WPS_FAIL:
+	case	LED_CTL_STOP_WPS_FAIL_OVERLAP:
+		if (check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE) {
+			pLed0->CurrLedState = RTW_LED_ON;
+			if (pLed0->bLedBlinkInProgress) {
+				_cancel_timer_ex(&(pLed0->BlinkTimer));
+				pLed0->bLedBlinkInProgress = _FALSE;
+			}
+			SwLedOn(Adapter, pLed0);
+		} else {
+			pLed0->CurrLedState = RTW_LED_OFF;
+			if (pLed0->bLedBlinkInProgress) {
+				_cancel_timer_ex(&(pLed0->BlinkTimer));
+				pLed0->bLedBlinkInProgress = _FALSE;
+			}
+			SwLedOff(Adapter, pLed0);
+		}
+
+		pLed1->CurrLedState = RTW_LED_OFF;
+		if (pLed1->bLedBlinkInProgress) {
+			_cancel_timer_ex(&(pLed1->BlinkTimer));
+			pLed1->bLedBlinkInProgress = _FALSE;
+		}
+		SwLedOff(Adapter, pLed1);
+
+		pLed1->bLedWPSBlinkInProgress = _FALSE;
+
+		break;
+
+	case LED_CTL_LINK:
+		pLed0->CurrLedState = RTW_LED_ON;
+		if (pLed0->bLedBlinkInProgress) {
+			_cancel_timer_ex(&(pLed0->BlinkTimer));
+			pLed0->bLedBlinkInProgress = _FALSE;
+		}
+		SwLedOn(Adapter, pLed0);
+		break;
+
+	case LED_CTL_NO_LINK:
+		if (pLed1->bLedWPSBlinkInProgress == _TRUE) {
+			SwLedOn(Adapter, pLed1);
+			break;
+		}
+
+		if (pLed1->CurrLedState == LED_BLINK_SCAN)
+			break;
+
+		pLed0->CurrLedState = RTW_LED_OFF;
+		if (pLed0->bLedBlinkInProgress) {
+			_cancel_timer_ex(&(pLed0->BlinkTimer));
+			pLed0->bLedBlinkInProgress = _FALSE;
+		}
+		SwLedOff(Adapter, pLed0);
+
+		pLed1->CurrLedState = RTW_LED_OFF;
+		if (pLed1->bLedBlinkInProgress) {
+			_cancel_timer_ex(&(pLed1->BlinkTimer));
+			pLed1->bLedBlinkInProgress = _FALSE;
+		}
+		SwLedOff(Adapter, pLed1);
+
+		break;
+
+
+	case LED_CTL_POWER_ON:
+	case LED_CTL_POWER_OFF:
+		if (pLed1->bLedWPSBlinkInProgress == _TRUE) {
+			SwLedOn(Adapter, pLed1);
+			break;
+		}
+		pLed0->CurrLedState = RTW_LED_OFF;
+		if (pLed0->bLedBlinkInProgress) {
+			_cancel_timer_ex(&(pLed0->BlinkTimer));
+			pLed0->bLedBlinkInProgress = _FALSE;
+		}
+		SwLedOff(Adapter, pLed0);
+
+		pLed1->CurrLedState = RTW_LED_OFF;
+		if (pLed1->bLedBlinkInProgress) {
+			_cancel_timer_ex(&(pLed1->BlinkTimer));
+			pLed1->bLedBlinkInProgress = _FALSE;
+		}
+		SwLedOff(Adapter, pLed1);
+
+		break;
+
+	default:
+		break;
+
+	}
+
+
+}
+
+
+/* added by hpfan, for Xavi */
+VOID
+SwLedControlMode11(
+	IN	PADAPTER			Adapter,
+	IN	LED_CTL_MODE		LedAction
+)
+{
+	struct led_priv	*ledpriv = adapter_to_led(Adapter);
+	PLED_PCIE	pLed = &(ledpriv->SwLed0);
+
+	/* Decide led state */
+	switch (LedAction) {
+	case LED_CTL_START_WPS:
+	case LED_CTL_START_WPS_BOTTON:
+		pLed->bLedWPSBlinkInProgress = _TRUE;
+		if (pLed->bLedBlinkInProgress == _FALSE) {
+			pLed->bLedBlinkInProgress = _TRUE;
+			pLed->CurrLedState = LED_BLINK_XAVI;
+
+			if (pLed->bLedOn) {
+				pLed->BlinkingLedState = RTW_LED_OFF;
+				_set_timer(&(pLed->BlinkTimer), LED_CM11_BLINK_INTERVAL);
+			} else {
+				pLed->BlinkingLedState = RTW_LED_ON;
+				_set_timer(&(pLed->BlinkTimer), LED_CM11_BLINK_INTERVAL);
+			}
+		}
+		break;
+
+	case LED_CTL_STOP_WPS:
+	case LED_CTL_STOP_WPS_FAIL:
+	case LED_CTL_STOP_WPS_FAIL_OVERLAP:
+		pLed->bLedWPSBlinkInProgress = _FALSE;
+		if (pLed->bLedBlinkInProgress) {
+			_cancel_timer_ex(&(pLed->BlinkTimer));
+			pLed->bLedBlinkInProgress = _FALSE;
+			pLed->CurrLedState = RTW_LED_OFF;
+		}
+		SwLedOff(Adapter, pLed);
+		break;
+
+	case LED_CTL_LINK:
+		if (pLed->bLedWPSBlinkInProgress)
+			break;
+
+		if (pLed->bLedBlinkInProgress) {
+			_cancel_timer_ex(&(pLed->BlinkTimer));
+			pLed->bLedBlinkInProgress = _FALSE;
+			pLed->CurrLedState = RTW_LED_ON;
+
+			if (!pLed->bLedOn)
+				SwLedOn(Adapter, pLed);
+		} else {
+			pLed->CurrLedState = RTW_LED_ON;
+			SwLedOn(Adapter, pLed);
+		}
+
+		_set_timer(&(pLed->BlinkTimer), LED_CM11_LINK_ON_INTERVEL);
+		pLed->BlinkingLedState = RTW_LED_OFF;
+		break;
+
+	case LED_CTL_NO_LINK:
+		if (pLed->bLedWPSBlinkInProgress)
+			break;
+
+		if (pLed->bLedBlinkInProgress == _TRUE) {
+			_cancel_timer_ex(&(pLed->BlinkTimer));
+			pLed->bLedBlinkInProgress = _FALSE;
+		}
+		pLed->CurrLedState = RTW_LED_OFF;
+		SwLedOff(Adapter, pLed);
+		break;
+
+	case LED_CTL_POWER_ON:
+	case LED_CTL_POWER_OFF:
+		if (pLed->bLedBlinkInProgress == _TRUE) {
+			_cancel_timer_ex(&(pLed->BlinkTimer));
+			pLed->bLedBlinkInProgress = _FALSE;
+		}
+
+		pLed->CurrLedState = RTW_LED_OFF;
+		SwLedOff(Adapter, pLed);
+		break;
+
+	default:
+		break;
+
+	}
+
+
+}
+
+/* added by chiyokolin, for Azurewave */
+VOID
+SwLedControlMode12(
+	IN	PADAPTER			Adapter,
+	IN	LED_CTL_MODE		LedAction
+)
+{
+	struct led_priv	*ledpriv = adapter_to_led(Adapter);
+	PLED_PCIE	pLed = &(ledpriv->SwLed0);
+	struct mlme_priv	*pmlmepriv = &(Adapter->mlmepriv);
+	LED_STATE	LedState = LED_UNKNOWN;
+
+
+	/* Decide led state */
+	switch (LedAction) {
+	case LED_CTL_TX:
+	case LED_CTL_RX:
+		if (check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE) {
+			if (pLed->CurrLedState == LED_BLINK_SCAN)
+				break;
+
+			pLed->BlinkTimes = 0;
+
+			if (pLed->bLedOn)
+				pLed->BlinkingLedState = RTW_LED_OFF;
+			else
+				pLed->BlinkingLedState = RTW_LED_ON;
+
+			/*if(pTurboCa->TotalThroughput <= 5)
+				LedState = LED_BLINK_Azurewave_5Mbps;
+			else if(pTurboCa->TotalThroughput <= 10)
+				LedState = LED_BLINK_Azurewave_10Mbps;
+			else if(pTurboCa->TotalThroughput <=20)
+				LedState = LED_BLINK_Azurewave_20Mbps;
+			else if(pTurboCa->TotalThroughput <=40)
+				LedState = LED_BLINK_Azurewave_40Mbps;
+			else if(pTurboCa->TotalThroughput <=80)
+				LedState = LED_BLINK_Azurewave_80Mbps;
+			else*/
+			LedState = LED_BLINK_Azurewave_MAXMbps;
+
+			if (pLed->bLedBlinkInProgress == _FALSE || pLed->CurrLedState != LedState) {
+				_cancel_timer_ex(&(pLed->BlinkTimer));
+				pLed->CurrLedState = LedState;
+				pLed->bLedBlinkInProgress = _TRUE;
+
+				switch (LedState) {
+				case LED_BLINK_Azurewave_5Mbps:
+					_set_timer(&(pLed->BlinkTimer), LED_CM12_BLINK_INTERVAL_5Mbps);
+					break;
+
+				case LED_BLINK_Azurewave_10Mbps:
+					_set_timer(&(pLed->BlinkTimer), LED_CM12_BLINK_INTERVAL_10Mbps);
+					break;
+
+				case LED_BLINK_Azurewave_20Mbps:
+					_set_timer(&(pLed->BlinkTimer), LED_CM12_BLINK_INTERVAL_20Mbps);
+					break;
+
+				case LED_BLINK_Azurewave_40Mbps:
+					_set_timer(&(pLed->BlinkTimer), LED_CM12_BLINK_INTERVAL_40Mbps);
+					break;
+
+				case LED_BLINK_Azurewave_80Mbps:
+					_set_timer(&(pLed->BlinkTimer), LED_CM12_BLINK_INTERVAL_80Mbps);
+					break;
+
+				case LED_BLINK_Azurewave_MAXMbps:
+					_set_timer(&(pLed->BlinkTimer), LED_CM12_BLINK_INTERVAL_MAXMbps);
+					break;
+
+				default:
+					break;
+				}
+			}
+		}
+
+		break;
+
+	case LED_CTL_SITE_SURVEY:
+	case LED_CTL_START_WPS:
+	case LED_CTL_START_WPS_BOTTON:
+		if (pLed->bLedBlinkInProgress == _FALSE)
+			pLed->bLedBlinkInProgress = _TRUE;
+		else if (pLed->CurrLedState != LED_BLINK_SCAN)
+			_cancel_timer_ex(&(pLed->BlinkTimer));
+
+		pLed->CurrLedState = LED_BLINK_SCAN;
+		pLed->BlinkTimes = 2;
+
+		if (pLed->bLedOn) {
+			pLed->BlinkingLedState = RTW_LED_OFF;
+			_set_timer(&(pLed->BlinkTimer), LED_CM2_BLINK_ON_INTERVAL);
+		} else {
+			pLed->BlinkingLedState = RTW_LED_ON;
+			_set_timer(&(pLed->BlinkTimer), LED_CM8_BLINK_OFF_INTERVAL);
+		}
+		break;
+
+	case LED_CTL_LINK:
+		pLed->CurrLedState = RTW_LED_ON;
+		if (pLed->bLedBlinkInProgress) {
+			_cancel_timer_ex(&(pLed->BlinkTimer));
+			pLed->bLedBlinkInProgress = _FALSE;
+		}
+		SwLedOn(Adapter, pLed);
+		break;
+
+	case LED_CTL_NO_LINK:
+	case LED_CTL_POWER_ON:
+		if (pLed->CurrLedState == LED_BLINK_SCAN)
+			break;
+
+		pLed->CurrLedState = LED_BLINK_NO_LINK;
+		pLed->bLedBlinkInProgress = _TRUE;
+
+		if (pLed->bLedOn) {
+			pLed->BlinkingLedState = RTW_LED_OFF;
+			_set_timer(&(pLed->BlinkTimer), LED_CM2_BLINK_ON_INTERVAL);
+		} else {
+			pLed->BlinkingLedState = RTW_LED_ON;
+			_set_timer(&(pLed->BlinkTimer), LED_CM8_BLINK_OFF_INTERVAL);
+		}
+		break;
+
+	case LED_CTL_POWER_OFF:
+		pLed->CurrLedState = RTW_LED_OFF;
+		if (pLed->bLedBlinkInProgress) {
+			_cancel_timer_ex(&(pLed->BlinkTimer));
+			pLed->bLedBlinkInProgress = _FALSE;
+		}
+		SwLedOff(Adapter, pLed);
+		break;
+
+	default:
+		break;
+
+	}
+
+
+}
+
+void
+LedControlPCIE(
+	_adapter				*padapter,
+	LED_CTL_MODE		LedAction
+)
+{
+	struct led_priv	*ledpriv = adapter_to_led(padapter);
+
+#if (MP_DRIVER == 1)
+	if (padapter->registrypriv.mp_mode == 1)
+		return;
+#endif
+
+	if (RTW_CANNOT_RUN(padapter) || (!rtw_is_hw_init_completed(padapter)))
+		return;
+
+	/* if(priv->bInHctTest) */
+	/*	return; */
+
+	if ((adapter_to_pwrctl(padapter)->rfoff_reason > RF_CHANGE_BY_PS) &&
+	    (LedAction == LED_CTL_TX ||
+	     LedAction == LED_CTL_RX ||
+	     LedAction == LED_CTL_SITE_SURVEY ||
+	     LedAction == LED_CTL_LINK ||
+	     LedAction == LED_CTL_NO_LINK ||
+	     LedAction == LED_CTL_START_TO_LINK ||
+	     LedAction == LED_CTL_POWER_ON)) {
+		return;
+	}
+
+	switch (ledpriv->LedStrategy) {
+	#if CONFIG_RTW_SW_LED_TRX_DA_CLASSIFY
+	case SW_LED_MODE_UC_TRX_ONLY:
+		rtw_sw_led_ctl_mode_uc_trx_only(padapter, LedAction);
+		break;
+	#endif
+
+	case SW_LED_MODE0:
+		/* SwLedControlMode0(padapter, LedAction); */
+		break;
+
+	case SW_LED_MODE1:
+		/* SwLedControlMode1(padapter, LedAction); */
+		break;
+
+	case SW_LED_MODE2:
+		/* SwLedControlMode2(padapter, LedAction); */
+		break;
+
+	case SW_LED_MODE3:
+		/* SwLedControlMode3(padapter, LedAction); */
+		break;
+
+	case SW_LED_MODE4:
+		/* SwLedControlMode4(padapter, LedAction); */
+		break;
+
+	case SW_LED_MODE5:
+		/* SwLedControlMode5(padapter, LedAction); */
+		break;
+
+	case SW_LED_MODE6:
+		/* SwLedControlMode6(padapter, LedAction); */
+		break;
+
+	case SW_LED_MODE7:
+		SwLedControlMode7(padapter, LedAction);
+		break;
+
+	case SW_LED_MODE8:
+		SwLedControlMode8(padapter, LedAction);
+		break;
+
+	case SW_LED_MODE9:
+		SwLedControlMode9(padapter, LedAction);
+		break;
+
+	case SW_LED_MODE10:
+		SwLedControlMode10(padapter, LedAction);
+		break;
+
+	case SW_LED_MODE11:
+		SwLedControlMode11(padapter, LedAction);
+		break;
+
+	case SW_LED_MODE12:
+		SwLedControlMode12(padapter, LedAction);
+		break;
+
+	default:
+		break;
+	}
+}
+
+/*-----------------------------------------------------------------------------
+ * Function:	gen_RefreshLedState()
+ *
+ * Overview:	When we call the function, media status is no link. It must be in SW/HW
+ *			radio off. Or IPS state. If IPS no link we will turn on LED, otherwise, we must turn off.
+ *			After MAC IO reset, we must write LED control 0x2f2 again.
+ *
+ * Input:		IN	PADAPTER			Adapter)
+ *
+ * Output:		NONE
+ *
+ * Return:		NONE
+ *
+ * Revised History:
+ *	When		Who		Remark
+ *	03/27/2009	MHC		Create for LED judge only~!!
+ *
+ *---------------------------------------------------------------------------*/
+VOID
+gen_RefreshLedState(
+	IN	PADAPTER			Adapter)
+{
+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(Adapter);
+	struct pwrctrl_priv	*pwrctrlpriv = adapter_to_pwrctl(Adapter);
+	struct led_priv	*pledpriv = adapter_to_led(Adapter);
+	PLED_PCIE		pLed0 = &(pledpriv->SwLed0);
+
+	RTW_INFO("gen_RefreshLedState:() pwrctrlpriv->rfoff_reason=%x\n", pwrctrlpriv->rfoff_reason);
+
+	if (Adapter->bDriverIsGoingToUnload) {
+		switch (pledpriv->LedStrategy) {
+		case SW_LED_MODE9:
+		case SW_LED_MODE10:
+			rtw_led_control(Adapter, LED_CTL_POWER_OFF);
+			break;
+
+		default:
+			/* Turn off LED if RF is not ON. */
+			SwLedOff(Adapter, pLed0);
+			break;
+		}
+	} else if (pwrctrlpriv->rfoff_reason == RF_CHANGE_BY_IPS) {
+		switch (pledpriv->LedStrategy) {
+		case SW_LED_MODE7:
+			SwLedOn(Adapter, pLed0);
+			break;
+
+		case SW_LED_MODE8:
+		case SW_LED_MODE9:
+			rtw_led_control(Adapter, LED_CTL_NO_LINK);
+			break;
+
+		default:
+			SwLedOn(Adapter, pLed0);
+			break;
+		}
+	} else if (pwrctrlpriv->rfoff_reason == RF_CHANGE_BY_INIT) {
+		switch (pledpriv->LedStrategy) {
+		case SW_LED_MODE7:
+			SwLedOn(Adapter, pLed0);
+			break;
+
+		case SW_LED_MODE9:
+			rtw_led_control(Adapter, LED_CTL_NO_LINK);
+			break;
+
+		default:
+			SwLedOn(Adapter, pLed0);
+			break;
+
+		}
+	} else {	/* SW/HW radio off */
+
+		switch (pledpriv->LedStrategy) {
+		case SW_LED_MODE9:
+			rtw_led_control(Adapter, LED_CTL_POWER_OFF);
+			break;
+
+		default:
+			/* Turn off LED if RF is not ON. */
+			SwLedOff(Adapter, pLed0);
+			break;
+		}
+	}
+
+}
+
+/*
+ *	Description:
+ *		Reset status of LED_871x object.
+ *   */
+void ResetLedStatus(PLED_PCIE pLed)
+{
+
+	pLed->CurrLedState = RTW_LED_OFF; /* Current LED state. */
+	pLed->bLedOn = _FALSE; /* true if LED is ON, false if LED is OFF. */
+
+	pLed->bLedBlinkInProgress = _FALSE; /* true if it is blinking, false o.w.. */
+	pLed->bLedWPSBlinkInProgress = _FALSE;
+	pLed->bLedSlowBlinkInProgress = _FALSE;
+
+	pLed->BlinkTimes = 0; /* Number of times to toggle led state for blinking. */
+	pLed->BlinkingLedState = LED_UNKNOWN; /* Next state for blinking, either RTW_LED_ON or RTW_LED_OFF are. */
+}
+
+/*
+*	Description:
+*		Initialize an LED_871x object.
+*   */
+void
+InitLed(
+	_adapter			*padapter,
+	PLED_PCIE		pLed,
+	LED_PIN			LedPin
+)
+{
+	pLed->padapter = padapter;
+	pLed->LedPin = LedPin;
+
+	ResetLedStatus(pLed);
+
+	rtw_init_timer(&(pLed->BlinkTimer), padapter, BlinkTimerCallback, pLed);
+}
+
+
+/*
+ *	Description:
+ *		DeInitialize an LED_871x object.
+ *   */
+void
+DeInitLed(
+	PLED_PCIE		pLed
+)
+{
+	_cancel_timer_ex(&(pLed->BlinkTimer));
+	ResetLedStatus(pLed);
+}
+#endif
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/ap_makefile.mk linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/ap_makefile.mk
--- linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/ap_makefile.mk	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/ap_makefile.mk	2020-04-10 16:35:06.818660161 +0300
@@ -0,0 +1,174 @@
+
+_PHYDM_FILES :=\
+	phydm/phydm.o \
+	phydm/phydm_dig.o\
+	phydm/phydm_antdiv.o\
+	phydm/phydm_soml.o\
+	phydm/phydm_smt_ant.o\
+	phydm/phydm_pathdiv.o\
+	phydm/phydm_rainfo.o\
+	phydm/phydm_dynamictxpower.o\
+	phydm/phydm_adaptivity.o\
+	phydm/phydm_debug.o\
+	phydm/phydm_interface.o\
+	phydm/phydm_phystatus.o\
+	phydm/phydm_hwconfig.o\
+	phydm/phydm_dfs.o\
+	phydm/phydm_cfotracking.o\
+	phydm/phydm_adc_sampling.o\
+	phydm/phydm_ccx.o\
+	phydm/phydm_primary_cca.o\
+	phydm/phydm_cck_pd.o\
+	phydm/phydm_rssi_monitor.o\
+	phydm/phydm_auto_dbg.o\
+	phydm/phydm_math_lib.o\
+	phydm/phydm_noisemonitor.o\
+	phydm/phydm_api.o\
+	phydm/phydm_pow_train.o\
+	phydm/phydm_lna_sat.o\
+	phydm/phydm_pmac_tx_setting.o\
+	phydm/phydm_mp.o\
+	phydm/txbf/phydm_hal_txbf_api.o\
+	EdcaTurboCheck.o\
+	phydm/halrf/halrf.o\
+	phydm/halrf/halrf_debug.o\
+	phydm/halrf/halphyrf_ap.o\
+	phydm/halrf/halrf_powertracking_ap.o\
+	phydm/halrf/halrf_powertracking.o\
+	phydm/halrf/halrf_kfree.o
+
+ifeq ($(CONFIG_RTL_88E_SUPPORT),y)
+	ifeq ($(CONFIG_RTL_ODM_WLAN_DRIVER),y)
+		_PHYDM_FILES += \
+		phydm/rtl8188e/halhwimg8188e_bb.o\
+		phydm/rtl8188e/halhwimg8188e_mac.o\
+		phydm/rtl8188e/halhwimg8188e_rf.o\
+		phydm/rtl8188e/phydm_regconfig8188e.o\
+		phydm/rtl8188e/hal8188erateadaptive.o\
+		phydm/rtl8188e/phydm_rtl8188e.o\
+		phydm/halrf/rtl8188e/halrf_8188e_ap.o
+	endif
+endif
+
+ifeq ($(CONFIG_RTL_8812_SUPPORT),y)
+	ifeq ($(CONFIG_RTL_ODM_WLAN_DRIVER),y)
+		_PHYDM_FILES += ./phydm/halrf/rtl8812a/halrf_8812a_ap.o
+	endif
+	_PHYDM_FILES += phydm/rtl8812a/phydm_rtl8812a.o
+endif
+
+ifeq ($(CONFIG_WLAN_HAL_8881A),y)
+	_PHYDM_FILES += phydm/halrf/rtl8821a/halrf_iqk_8821a_ap.o
+endif
+
+ifeq ($(CONFIG_WLAN_HAL_8192EE),y)
+	_PHYDM_FILES += \
+	phydm/halrf/rtl8192e/halrf_8192e_ap.o\
+	phydm/rtl8192e/phydm_rtl8192e.o
+endif
+
+ifeq ($(CONFIG_WLAN_HAL_8814AE),y)
+	rtl8192cd-objs += phydm/halrf/rtl8814a/halrf_8814a_ap.o
+	rtl8192cd-objs += phydm/halrf/rtl8814a/halrf_iqk_8814a.o
+	ifeq ($(CONFIG_RTL_ODM_WLAN_DRIVER),y)
+		rtl8192cd-objs += \
+		phydm/rtl8814a/halhwimg8814a_bb.o\
+		phydm/rtl8814a/halhwimg8814a_mac.o\
+		phydm/rtl8814a/halhwimg8814a_rf.o\
+		phydm/rtl8814a/phydm_regconfig8814a.o\
+		phydm/rtl8814a/phydm_rtl8814a.o
+	endif
+endif
+
+ifeq ($(CONFIG_WLAN_HAL_8822BE),y)
+	_PHYDM_FILES += phydm/halrf/rtl8822b/halrf_8822b.o
+	_PHYDM_FILES += phydm/halrf/rtl8822b/halrf_iqk_8822b.o
+	ifeq ($(CONFIG_RTL_ODM_WLAN_DRIVER),y)
+		_PHYDM_FILES += \
+		phydm/rtl8822b/halhwimg8822b_bb.o\
+		phydm/rtl8822b/halhwimg8822b_mac.o\
+		phydm/rtl8822b/halhwimg8822b_rf.o\
+		phydm/rtl8822b/phydm_regconfig8822b.o\
+		phydm/rtl8822b/phydm_hal_api8822b.o\
+		phydm/rtl8822b/phydm_rtl8822b.o
+	endif
+endif
+
+ifeq ($(CONFIG_WLAN_HAL_8821CE),y)
+	_PHYDM_FILES += phydm/halrf/rtl8821c/halrf_8821c.o
+	_PHYDM_FILES += phydm/halrf/rtl8821c/halrf_iqk_8821c.o
+	ifeq ($(CONFIG_RTL_ODM_WLAN_DRIVER),y)
+		_PHYDM_FILES += \
+		phydm/rtl8821c/halhwimg8821c_bb.o\
+		phydm/rtl8821c/halhwimg8821c_mac.o\
+		phydm/rtl8821c/halhwimg8821c_rf.o\
+		phydm/rtl8821c/phydm_regconfig8821c.o\
+		phydm/rtl8821c/phydm_hal_api8821c.o
+	endif
+endif
+
+ifeq ($(CONFIG_WLAN_HAL_8197F),y)
+		_PHYDM_FILES += phydm/halrf/rtl8197f/halrf_8197f.o
+		_PHYDM_FILES += phydm/halrf/rtl8197f/halrf_iqk_8197f.o
+		_PHYDM_FILES += phydm/halrf/rtl8197f/halrf_dpk_8197f.o
+		_PHYDM_FILES += efuse_97f/efuse.o
+	ifeq ($(CONFIG_RTL_ODM_WLAN_DRIVER),y)
+		_PHYDM_FILES += \
+		phydm/rtl8197f/halhwimg8197f_bb.o\
+		phydm/rtl8197f/halhwimg8197f_mac.o\
+		phydm/rtl8197f/halhwimg8197f_rf.o\
+		phydm/rtl8197f/phydm_hal_api8197f.o\
+		phydm/rtl8197f/phydm_regconfig8197f.o\
+		phydm/rtl8197f/phydm_rtl8197f.o
+	endif
+endif
+
+
+ifeq ($(CONFIG_WLAN_HAL_8192FE),y)
+		_PHYDM_FILES += phydm/halrf/rtl8192f/halrf_8192f.o
+		_PHYDM_FILES += phydm/halrf/rtl8192f/halrf_dpk_8192f.o
+	ifeq ($(CONFIG_RTL_ODM_WLAN_DRIVER),y)
+		_PHYDM_FILES += \
+		phydm/rtl8192f/halhwimg8192f_bb.o\
+		phydm/rtl8192f/halhwimg8192f_mac.o\
+		phydm/rtl8192f/halhwimg8192f_rf.o\
+		phydm/rtl8192f/phydm_hal_api8192f.o\
+		phydm/rtl8192f/phydm_regconfig8192f.o\
+		phydm/rtl8192f/phydm_rtl8192f.o
+	endif
+endif
+
+ifeq ($(CONFIG_WLAN_HAL_8198F),y)
+		_PHYDM_FILES += phydm/halrf/rtl8198f/halrf_8198f.o
+		_PHYDM_FILES += phydm/halrf/rtl8198f/halrf_iqk_8198f.o
+		_PHYDM_FILES += phydm/halrf/rtl8198f/halrf_dpk_8198f.o
+		_PHYDM_FILES += phydm/halrf/rtl8198f/halrf_rfk_init_8198f.o
+	ifeq ($(CONFIG_RTL_ODM_WLAN_DRIVER),y)
+		_PHYDM_FILES += \
+		phydm/rtl8198f/phydm_hal_api8198f.o\
+		phydm/rtl8198f/halhwimg8198f_bb.o\
+		phydm/rtl8198f/halhwimg8198f_mac.o\
+		phydm/rtl8198f/halhwimg8198f_rf.o\
+		phydm/rtl8198f/phydm_regconfig8198f.o \
+		phydm/halrf/rtl8198f/halrf_8198f.o
+	endif
+endif
+
+ifeq ($(CONFIG_WLAN_HAL_8814B),y)
+		_PHYDM_FILES += phydm/halrf/rtl8814b/halrf_8814b.o
+		_PHYDM_FILES += phydm/halrf/rtl8814b/halrf_iqk_8814b.o
+		_PHYDM_FILES += phydm/halrf/rtl8814b/halrf_dpk_8814b.o
+		_PHYDM_FILES += phydm/halrf/rtl8814b/halrf_rfk_init_8814b.o
+	ifeq ($(CONFIG_RTL_ODM_WLAN_DRIVER),y)
+		_PHYDM_FILES += \
+		phydm/rtl8814b/phydm_hal_api8814b.o\
+		phydm/rtl8814b/halhwimg8814b_bb.o\
+		phydm/rtl8814b/halhwimg8814b_mac.o\
+		phydm/rtl8814b/halhwimg8814b_rf.o\
+		phydm/rtl8814b/phydm_regconfig8814b.o \
+		phydm/halrf/rtl8814b/halrf_8814b.o
+	endif
+endif
+
+
+
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/halhwimg.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/halhwimg.h
--- linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/halhwimg.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/halhwimg.h	2020-04-10 16:35:06.818660161 +0300
@@ -0,0 +1,137 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2016 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#pragma once
+#ifndef __INC_HW_IMG_H
+#define __INC_HW_IMG_H
+
+/*@
+ * 2011/03/15 MH Add for different IC HW image file selection. code size consideration.
+ *   */
+#if RT_PLATFORM == PLATFORM_LINUX
+
+	#if (DEV_BUS_TYPE == RT_PCI_INTERFACE)
+		/* @For 92C */
+		#define		RTL8192CE_HWIMG_SUPPORT					1
+		#define		RTL8192CE_TEST_HWIMG_SUPPORT			0
+		#define		RTL8192CU_HWIMG_SUPPORT					0
+		#define		RTL8192CU_TEST_HWIMG_SUPPORT			0
+
+		/* @For 92D */
+		#define		RTL8192DE_HWIMG_SUPPORT					1
+		#define		RTL8192DE_TEST_HWIMG_SUPPORT			0
+		#define		RTL8192DU_HWIMG_SUPPORT					0
+		#define		RTL8192DU_TEST_HWIMG_SUPPORT			0
+
+		/* @For 8723 */
+		#define		RTL8723E_HWIMG_SUPPORT					1
+		#define		RTL8723U_HWIMG_SUPPORT					0
+		#define		RTL8723S_HWIMG_SUPPORT					0
+
+		/* @For 88E */
+		#define		RTL8188EE_HWIMG_SUPPORT					0
+		#define		RTL8188EU_HWIMG_SUPPORT					0
+		#define		RTL8188ES_HWIMG_SUPPORT					0
+
+	#elif (DEV_BUS_TYPE == RT_USB_INTERFACE)
+		/* @For 92C */
+		#define	RTL8192CE_HWIMG_SUPPORT				0
+		#define	RTL8192CE_TEST_HWIMG_SUPPORT			0
+		#define	RTL8192CU_HWIMG_SUPPORT				1
+		#define	RTL8192CU_TEST_HWIMG_SUPPORT			0
+
+		/* @For 92D */
+		#define	RTL8192DE_HWIMG_SUPPORT				0
+		#define	RTL8192DE_TEST_HWIMG_SUPPORT			0
+		#define	RTL8192DU_HWIMG_SUPPORT				1
+		#define	RTL8192DU_TEST_HWIMG_SUPPORT			0
+
+		/* @For 8723 */
+		#define	RTL8723E_HWIMG_SUPPORT					0
+		#define	RTL8723U_HWIMG_SUPPORT					1
+		#define	RTL8723S_HWIMG_SUPPORT					0
+
+		/* @For 88E */
+		#define		RTL8188EE_HWIMG_SUPPORT					0
+		#define		RTL8188EU_HWIMG_SUPPORT					0
+		#define		RTL8188ES_HWIMG_SUPPORT					0
+
+	#elif (DEV_BUS_TYPE == RT_SDIO_INTERFACE)
+		/* @For 92C */
+		#define	RTL8192CE_HWIMG_SUPPORT				0
+		#define	RTL8192CE_TEST_HWIMG_SUPPORT			0
+		#define	RTL8192CU_HWIMG_SUPPORT				1
+		#define	RTL8192CU_TEST_HWIMG_SUPPORT			0
+
+		/* @For 92D */
+		#define	RTL8192DE_HWIMG_SUPPORT				0
+		#define	RTL8192DE_TEST_HWIMG_SUPPORT			0
+		#define	RTL8192DU_HWIMG_SUPPORT				1
+		#define	RTL8192DU_TEST_HWIMG_SUPPORT			0
+
+		/* @For 8723 */
+		#define	RTL8723E_HWIMG_SUPPORT					0
+		#define	RTL8723U_HWIMG_SUPPORT					0
+		#define	RTL8723S_HWIMG_SUPPORT					1
+
+		/* @For 88E */
+		#define		RTL8188EE_HWIMG_SUPPORT					0
+		#define		RTL8188EU_HWIMG_SUPPORT					0
+		#define		RTL8188ES_HWIMG_SUPPORT					0
+	#endif
+
+#else	/* PLATFORM_WINDOWS & MacOSX */
+
+	/* @For 92C */
+	#define		RTL8192CE_HWIMG_SUPPORT						1
+	#define		RTL8192CE_TEST_HWIMG_SUPPORT				1
+	#define		RTL8192CU_HWIMG_SUPPORT						1
+	#define		RTL8192CU_TEST_HWIMG_SUPPORT				1
+
+	/* @For 92D */
+	#define		RTL8192DE_HWIMG_SUPPORT					1
+	#define		RTL8192DE_TEST_HWIMG_SUPPORT				1
+	#define		RTL8192DU_HWIMG_SUPPORT					1
+	#define		RTL8192DU_TEST_HWIMG_SUPPORT				1
+
+	#if defined(UNDER_CE)
+		/* @For 8723 */
+		#define		RTL8723E_HWIMG_SUPPORT					0
+		#define		RTL8723U_HWIMG_SUPPORT					0
+		#define		RTL8723S_HWIMG_SUPPORT					1
+
+		/* @For 88E */
+		#define		RTL8188EE_HWIMG_SUPPORT					0
+		#define		RTL8188EU_HWIMG_SUPPORT					0
+		#define		RTL8188ES_HWIMG_SUPPORT					0
+
+	#else
+
+		/* @For 8723 */
+		#define		RTL8723E_HWIMG_SUPPORT					1
+		/* @#define		RTL_8723E_TEST_HWIMG_SUPPORT			1 */
+		#define		RTL8723U_HWIMG_SUPPORT					1
+		/* @#define		RTL_8723U_TEST_HWIMG_SUPPORT			1 */
+		#define		RTL8723S_HWIMG_SUPPORT					1
+		/* @#define		RTL_8723S_TEST_HWIMG_SUPPORT			1 */
+
+		/* @For 88E */
+		#define		RTL8188EE_HWIMG_SUPPORT					1
+		#define		RTL8188EU_HWIMG_SUPPORT					1
+		#define		RTL8188ES_HWIMG_SUPPORT					1
+	#endif
+
+#endif
+
+#endif /* @__INC_HW_IMG_H */
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/halphyrf_ap.c linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/halphyrf_ap.c
--- linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/halphyrf_ap.c	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/halphyrf_ap.c	2020-04-10 16:35:06.818660161 +0300
@@ -0,0 +1,2668 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
+ *
+ *
+ ******************************************************************************/
+
+#include "mp_precomp.h"
+#include "phydm_precomp.h"
+
+#ifndef index_mapping_NUM_88E
+	#define	index_mapping_NUM_88E	15
+#endif
+
+/* #if(DM_ODM_SUPPORT_TYPE & ODM_WIN) */
+
+#define	CALCULATE_SWINGTALBE_OFFSET(_offset, _direction, _size, _delta_thermal) \
+	do {\
+		for (_offset = 0; _offset < _size; _offset++) { \
+			\
+			if (_delta_thermal < thermal_threshold[_direction][_offset]) { \
+				\
+				if (_offset != 0)\
+					_offset--;\
+				break;\
+			} \
+		}			\
+		if (_offset >= _size)\
+			_offset = _size-1;\
+	} while (0)
+
+
+void configure_txpower_track(
+	void		*p_dm_void,
+	struct _TXPWRTRACK_CFG	*p_config
+)
+{
+	struct PHY_DM_STRUCT		*p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
+#if RTL8812A_SUPPORT
+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
+	/* if (IS_HARDWARE_TYPE_8812(p_dm_odm->adapter)) */
+	if (p_dm_odm->support_ic_type == ODM_RTL8812)
+		configure_txpower_track_8812a(p_config);
+	/* else */
+#endif
+#endif
+
+#if RTL8814A_SUPPORT
+	if (p_dm_odm->support_ic_type == ODM_RTL8814A)
+		configure_txpower_track_8814a(p_config);
+#endif
+
+
+#if RTL8188E_SUPPORT
+	if (p_dm_odm->support_ic_type == ODM_RTL8188E)
+		configure_txpower_track_8188e(p_config);
+#endif
+
+#if RTL8197F_SUPPORT
+	if (p_dm_odm->support_ic_type == ODM_RTL8197F)
+		configure_txpower_track_8197f(p_config);
+#endif
+
+#if RTL8822B_SUPPORT
+	if (p_dm_odm->support_ic_type == ODM_RTL8822B)
+		configure_txpower_track_8822b(p_config);
+#endif
+
+
+}
+
+#if (RTL8192E_SUPPORT == 1)
+void
+odm_txpowertracking_callback_thermal_meter_92e(
+#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
+	void		*p_dm_void
+#else
+	struct _ADAPTER	*adapter
+#endif
+)
+{
+	struct PHY_DM_STRUCT		*p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
+	u8	thermal_value = 0, delta, delta_IQK, delta_LCK, channel, is_decrease, rf_mimo_mode;
+	u8	thermal_value_avg_count = 0;
+	u8     OFDM_min_index = 10; /* OFDM BB Swing should be less than +2.5dB, which is required by Arthur */
+	s8	OFDM_index[2], index ;
+	u32	thermal_value_avg = 0, reg0x18;
+	u32	i = 0, j = 0, rf;
+	s32	value32, CCK_index = 0, ele_A, ele_D, ele_C, X, Y;
+	struct rtl8192cd_priv	*priv = p_dm_odm->priv;
+
+	rf_mimo_mode = p_dm_odm->rf_type;
+	/* ODM_RT_TRACE(p_dm_odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("%s:%d rf_mimo_mode:%d\n", __FUNCTION__, __LINE__, rf_mimo_mode)); */
+
+#ifdef MP_TEST
+	if ((OPMODE & WIFI_MP_STATE) || priv->pshare->rf_ft_var.mp_specific) {
+		channel = priv->pshare->working_channel;
+		if (priv->pshare->mp_txpwr_tracking == false)
+			return;
+	} else
+#endif
+	{
+		channel = (priv->pmib->dot11RFEntry.dot11channel);
+	}
+
+	thermal_value = (unsigned char)odm_get_rf_reg(p_dm_odm, RF_PATH_A, ODM_RF_T_METER_92E, 0xfc00);	/* 0x42: RF Reg[15:10] 88E */
+	ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("\nReadback Thermal Meter = 0x%x pre thermal meter 0x%x EEPROMthermalmeter 0x%x\n", thermal_value, priv->pshare->thermal_value, priv->pmib->dot11RFEntry.ther));
+
+
+	switch (rf_mimo_mode) {
+	case MIMO_1T1R:
+		rf = 1;
+		break;
+	case MIMO_2T2R:
+		rf = 2;
+		break;
+	default:
+		rf = 2;
+		break;
+	}
+
+	/* Query OFDM path A default setting 	Bit[31:21] */
+	ele_D = phy_query_bb_reg(priv, REG_OFDM_0_XA_TX_IQ_IMBALANCE, MASKOFDM_D);
+	for (i = 0; i < OFDM_TABLE_SIZE_92E; i++) {
+		if (ele_D == (ofdm_swing_table_92e[i] >> 22)) {
+			OFDM_index[0] = (unsigned char)i;
+			ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("PathA 0xC80[31:22] = 0x%x, OFDM_index=%d\n", ele_D, OFDM_index[0]));
+			break;
+		}
+	}
+
+	/* Query OFDM path B default setting */
+	if (rf_mimo_mode == MIMO_2T2R) {
+		ele_D = phy_query_bb_reg(priv, REG_OFDM_0_XB_TX_IQ_IMBALANCE, MASKOFDM_D);
+		for (i = 0; i < OFDM_TABLE_SIZE_92E; i++) {
+			if (ele_D == (ofdm_swing_table_92e[i] >> 22)) {
+				OFDM_index[1] = (unsigned char)i;
+				ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("PathB 0xC88[31:22] = 0x%x, OFDM_index=%d\n", ele_D, OFDM_index[1]));
+				break;
+			}
+		}
+	}
+
+	/* calculate average thermal meter */
+	{
+		priv->pshare->thermal_value_avg_88xx[priv->pshare->thermal_value_avg_index_88xx] = thermal_value;
+		priv->pshare->thermal_value_avg_index_88xx++;
+		if (priv->pshare->thermal_value_avg_index_88xx == AVG_THERMAL_NUM_88XX)
+			priv->pshare->thermal_value_avg_index_88xx = 0;
+
+		for (i = 0; i < AVG_THERMAL_NUM_88XX; i++) {
+			if (priv->pshare->thermal_value_avg_88xx[i]) {
+				thermal_value_avg += priv->pshare->thermal_value_avg_88xx[i];
+				thermal_value_avg_count++;
+			}
+		}
+
+		if (thermal_value_avg_count) {
+			thermal_value = (unsigned char)(thermal_value_avg / thermal_value_avg_count);
+			ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("AVG Thermal Meter = 0x%x\n", thermal_value));
+		}
+	}
+
+	/* Initialize */
+	if (!priv->pshare->thermal_value) {
+		priv->pshare->thermal_value = priv->pmib->dot11RFEntry.ther;
+		priv->pshare->thermal_value_iqk = thermal_value;
+		priv->pshare->thermal_value_lck = thermal_value;
+	}
+
+	if (thermal_value != priv->pshare->thermal_value) {
+		ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("\n******** START POWER TRACKING ********\n"));
+		ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("\nReadback Thermal Meter = 0x%x pre thermal meter 0x%x EEPROMthermalmeter 0x%x\n", thermal_value, priv->pshare->thermal_value, priv->pmib->dot11RFEntry.ther));
+
+		delta = RTL_ABS(thermal_value, priv->pmib->dot11RFEntry.ther);
+		delta_IQK = RTL_ABS(thermal_value, priv->pshare->thermal_value_iqk);
+		delta_LCK = RTL_ABS(thermal_value, priv->pshare->thermal_value_lck);
+		is_decrease = ((thermal_value < priv->pmib->dot11RFEntry.ther) ? 1 : 0);
+
+#ifdef _TRACKING_TABLE_FILE
+		if (priv->pshare->rf_ft_var.pwr_track_file) {
+			ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("diff: (%s)%d ==> get index from table : %d)\n", (is_decrease ? "-" : "+"), delta, get_tx_tracking_index(priv, channel, i, delta, is_decrease, 0)));
+
+			if (is_decrease) {
+				for (i = 0; i < rf; i++) {
+					OFDM_index[i] = priv->pshare->OFDM_index0[i] + get_tx_tracking_index(priv, channel, i, delta, is_decrease, 0);
+					OFDM_index[i] = ((OFDM_index[i] > (OFDM_TABLE_SIZE_92E- 1)) ? (OFDM_TABLE_SIZE_92E - 1) : OFDM_index[i]);
+					ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, (">>> decrese power ---> new OFDM_INDEX:%d (%d + %d)\n", OFDM_index[i], priv->pshare->OFDM_index0[i], get_tx_tracking_index(priv, channel, i, delta, is_decrease, 0)));
+					CCK_index = priv->pshare->CCK_index0 + get_tx_tracking_index(priv, channel, i, delta, is_decrease, 1);
+					CCK_index = ((CCK_index > (CCK_TABLE_SIZE_92E - 1)) ? (CCK_TABLE_SIZE_92E - 1) : CCK_index);
+					ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, (">>> Decrese power ---> new CCK_INDEX:%d (%d + %d)\n",  CCK_index, priv->pshare->CCK_index0, get_tx_tracking_index(priv, channel, i, delta, is_decrease, 1)));
+				}
+			} else {
+				for (i = 0; i < rf; i++) {
+					OFDM_index[i] = priv->pshare->OFDM_index0[i] - get_tx_tracking_index(priv, channel, i, delta, is_decrease, 0);
+					OFDM_index[i] = ((OFDM_index[i] < OFDM_min_index) ?  OFDM_min_index : OFDM_index[i]);
+					ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, (">>> Increse power ---> new OFDM_INDEX:%d (%d - %d)\n", OFDM_index[i], priv->pshare->OFDM_index0[i], get_tx_tracking_index(priv, channel, i, delta, is_decrease, 0)));
+					CCK_index = priv->pshare->CCK_index0 - get_tx_tracking_index(priv, channel, i, delta, is_decrease, 1);
+					CCK_index = ((CCK_index < 0) ? 0 : CCK_index);
+					ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, (">>> Increse power ---> new CCK_INDEX:%d (%d - %d)\n", CCK_index, priv->pshare->CCK_index0, get_tx_tracking_index(priv, channel, i, delta, is_decrease, 1)));
+				}
+			}
+		}
+#endif /* CFG_TRACKING_TABLE_FILE */
+
+		ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("ofdm_swing_table_92e[(unsigned int)OFDM_index[0]] = %x\n", ofdm_swing_table_92e[(unsigned int)OFDM_index[0]]));
+		ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("ofdm_swing_table_92e[(unsigned int)OFDM_index[1]] = %x\n", ofdm_swing_table_92e[(unsigned int)OFDM_index[1]]));
+
+		/* Adujst OFDM Ant_A according to IQK result */
+		ele_D = (ofdm_swing_table_92e[(unsigned int)OFDM_index[0]] & 0xFFC00000) >> 22;
+		X = priv->pshare->rege94;
+		Y = priv->pshare->rege9c;
+
+		if (X != 0) {
+			if ((X & 0x00000200) != 0)
+				X = X | 0xFFFFFC00;
+			ele_A = ((X * ele_D) >> 8) & 0x000003FF;
+
+			/* new element C = element D x Y */
+			if ((Y & 0x00000200) != 0)
+				Y = Y | 0xFFFFFC00;
+			ele_C = ((Y * ele_D) >> 8) & 0x000003FF;
+
+			/* wirte new elements A, C, D to regC80 and regC94, element B is always 0 */
+			value32 = (ele_D << 22) | ((ele_C & 0x3F) << 16) | ele_A;
+			phy_set_bb_reg(priv, REG_OFDM_0_XA_TX_IQ_IMBALANCE, MASKDWORD, value32);
+
+			value32 = (ele_C & 0x000003C0) >> 6;
+			phy_set_bb_reg(priv, REG_OFDM_0_XC_TX_AFE, MASKH4BITS, value32);
+
+			value32 = ((X * ele_D) >> 7) & 0x01;
+			phy_set_bb_reg(priv, REG_OFDM_0_ECCA_THRESHOLD, BIT(24), value32);
+		} else {
+			phy_set_bb_reg(priv, REG_OFDM_0_XA_TX_IQ_IMBALANCE, MASKDWORD, ofdm_swing_table_92e[(unsigned int)OFDM_index[0]]);
+			phy_set_bb_reg(priv, REG_OFDM_0_XC_TX_AFE, MASKH4BITS, 0x00);
+			phy_set_bb_reg(priv, REG_OFDM_0_ECCA_THRESHOLD, BIT(24), 0x00);
+		}
+
+		set_CCK_swing_index(priv, CCK_index);
+
+		if (rf == 2) {
+			ele_D = (ofdm_swing_table_92e[(unsigned int)OFDM_index[1]] & 0xFFC00000) >> 22;
+			X = priv->pshare->regeb4;
+			Y = priv->pshare->regebc;
+
+			if (X != 0) {
+				if ((X & 0x00000200) != 0)	/* consider minus */
+					X = X | 0xFFFFFC00;
+				ele_A = ((X * ele_D) >> 8) & 0x000003FF;
+
+				/* new element C = element D x Y */
+				if ((Y & 0x00000200) != 0)
+					Y = Y | 0xFFFFFC00;
+				ele_C = ((Y * ele_D) >> 8) & 0x00003FF;
+
+				/* wirte new elements A, C, D to regC88 and regC9C, element B is always 0 */
+				value32 = (ele_D << 22) | ((ele_C & 0x3F) << 16) | ele_A;
+				phy_set_bb_reg(priv, REG_OFDM_0_XB_TX_IQ_IMBALANCE, MASKDWORD, value32);
+
+				value32 = (ele_C & 0x000003C0) >> 6;
+				phy_set_bb_reg(priv, REG_OFDM_0_XD_TX_AFE, MASKH4BITS, value32);
+
+				value32 = ((X * ele_D) >> 7) & 0x01;
+				phy_set_bb_reg(priv, REG_OFDM_0_ECCA_THRESHOLD, BIT(28), value32);
+			} else {
+				phy_set_bb_reg(priv, REG_OFDM_0_XB_TX_IQ_IMBALANCE, MASKDWORD, ofdm_swing_table_92e[(unsigned int)OFDM_index[1]]);
+				phy_set_bb_reg(priv, REG_OFDM_0_XD_TX_AFE, MASKH4BITS, 0x00);
+				phy_set_bb_reg(priv, REG_OFDM_0_ECCA_THRESHOLD, BIT(28), 0x00);
+			}
+
+		}
+
+		ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("0xc80 = 0x%x\n", phy_query_bb_reg(priv, REG_OFDM_0_XA_TX_IQ_IMBALANCE, MASKDWORD)));
+		ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("0xc88 = 0x%x\n", phy_query_bb_reg(priv, REG_OFDM_0_XB_TX_IQ_IMBALANCE, MASKDWORD)));
+
+		if (delta_IQK > 3) {
+			priv->pshare->thermal_value_iqk = thermal_value;
+#ifdef MP_TEST
+			if (!(priv->pshare->rf_ft_var.mp_specific && (OPMODE & (WIFI_MP_CTX_BACKGROUND | WIFI_MP_CTX_PACKET))))
+#endif
+				phy_iq_calibrate_8192e(p_dm_odm, false);
+		}
+
+		if (delta_LCK > 8) {
+			RTL_W8(0x522, 0xff);
+			reg0x18 = phy_query_rf_reg(priv, RF_PATH_A, 0x18, MASK20BITS, 1);
+			phy_set_rf_reg(priv, RF_PATH_A, 0xB4, BIT(14), 1);
+			phy_set_rf_reg(priv, RF_PATH_A, 0x18, BIT(15), 1);
+			delay_ms(1);
+			phy_set_rf_reg(priv, RF_PATH_A, 0xB4, BIT(14), 0);
+			phy_set_rf_reg(priv, RF_PATH_A, 0x18, MASK20BITS, reg0x18);
+			RTL_W8(0x522, 0x0);
+			priv->pshare->thermal_value_lck = thermal_value;
+		}
+	}
+
+	/* update thermal meter value */
+	priv->pshare->thermal_value = thermal_value;
+	for (i = 0 ; i < rf ; i++)
+		priv->pshare->OFDM_index[i] = OFDM_index[i];
+	priv->pshare->CCK_index = CCK_index;
+
+	ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("\n******** END:%s() ********\n", __FUNCTION__));
+}
+#endif
+
+
+
+#if (RTL8197F_SUPPORT == 1 || RTL8822B_SUPPORT == 1)
+void
+odm_txpowertracking_callback_thermal_meter_jaguar_series3(
+#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
+	void		*p_dm_void
+#else
+	struct _ADAPTER	*adapter
+#endif
+)
+{
+#if 1
+	struct PHY_DM_STRUCT		*p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
+	u8			thermal_value = 0, delta, delta_LCK, delta_IQK, channel, is_increase;
+	u8			thermal_value_avg_count = 0, p = 0, i = 0;
+	u32			thermal_value_avg = 0;
+	struct rtl8192cd_priv		*priv = p_dm_odm->priv;
+	struct _TXPWRTRACK_CFG	c;
+	struct odm_rf_calibration_structure	*p_rf_calibrate_info = &(p_dm_odm->rf_calibrate_info);
+
+	/*4 1. The following TWO tables decide the final index of OFDM/CCK swing table.*/
+	u8			*delta_swing_table_idx_tup_a = NULL, *delta_swing_table_idx_tdown_a = NULL;
+	u8			*delta_swing_table_idx_tup_b = NULL, *delta_swing_table_idx_tdown_b = NULL;
+	u8			*delta_swing_table_idx_tup_cck_a = NULL, *delta_swing_table_idx_tdown_cck_a = NULL;
+	u8			*delta_swing_table_idx_tup_cck_b = NULL, *delta_swing_table_idx_tdown_cck_b = NULL;
+	/*for 8814 add by Yu Chen*/
+	u8			*delta_swing_table_idx_tup_c = NULL, *delta_swing_table_idx_tdown_c = NULL;
+	u8			*delta_swing_table_idx_tup_d = NULL, *delta_swing_table_idx_tdown_d = NULL;
+	u8			*delta_swing_table_idx_tup_cck_c = NULL, *delta_swing_table_idx_tdown_cck_c = NULL;
+	u8			*delta_swing_table_idx_tup_cck_d = NULL, *delta_swing_table_idx_tdown_cck_d = NULL;
+
+#ifdef MP_TEST
+	if ((OPMODE & WIFI_MP_STATE) || priv->pshare->rf_ft_var.mp_specific) {
+		channel = priv->pshare->working_channel;
+		if (priv->pshare->mp_txpwr_tracking == false)
+			return;
+	} else
+#endif
+	{
+		channel = (priv->pmib->dot11RFEntry.dot11channel);
+	}
+
+	configure_txpower_track(p_dm_odm, &c);
+
+	(*c.get_delta_all_swing_table)(p_dm_odm, (u8 **)&delta_swing_table_idx_tup_a, (u8 **)&delta_swing_table_idx_tdown_a,
+		(u8 **)&delta_swing_table_idx_tup_b, (u8 **)&delta_swing_table_idx_tdown_b,
+		(u8 **)&delta_swing_table_idx_tup_cck_a, (u8 **)&delta_swing_table_idx_tdown_cck_a,
+		(u8 **)&delta_swing_table_idx_tup_cck_b, (u8 **)&delta_swing_table_idx_tdown_cck_b);
+
+	thermal_value = (u8)odm_get_rf_reg(p_dm_odm, ODM_RF_PATH_A, c.thermal_reg_addr, 0xfc00); /*0x42: RF Reg[15:10] 88E*/
+
+	ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
+		("Readback Thermal Meter = 0x%x(%d) EEPROMthermalmeter 0x%x(%d)\n"
+		, thermal_value, thermal_value, priv->pmib->dot11RFEntry.ther, priv->pmib->dot11RFEntry.ther));
+
+	/* Initialize */
+	if (!p_dm_odm->rf_calibrate_info.thermal_value)
+		p_dm_odm->rf_calibrate_info.thermal_value = priv->pmib->dot11RFEntry.ther;
+
+	if (!p_dm_odm->rf_calibrate_info.thermal_value_lck)
+		p_dm_odm->rf_calibrate_info.thermal_value_lck = priv->pmib->dot11RFEntry.ther;
+
+	if (!p_dm_odm->rf_calibrate_info.thermal_value_iqk)
+		p_dm_odm->rf_calibrate_info.thermal_value_iqk = priv->pmib->dot11RFEntry.ther;
+
+	/* calculate average thermal meter */
+	p_dm_odm->rf_calibrate_info.thermal_value_avg[p_dm_odm->rf_calibrate_info.thermal_value_avg_index] = thermal_value;
+	p_dm_odm->rf_calibrate_info.thermal_value_avg_index++;
+
+	if (p_dm_odm->rf_calibrate_info.thermal_value_avg_index == c.average_thermal_num)   /*Average times =  c.average_thermal_num*/
+		p_dm_odm->rf_calibrate_info.thermal_value_avg_index = 0;
+
+	for (i = 0; i < c.average_thermal_num; i++) {
+		if (p_dm_odm->rf_calibrate_info.thermal_value_avg[i]) {
+			thermal_value_avg += p_dm_odm->rf_calibrate_info.thermal_value_avg[i];
+			thermal_value_avg_count++;
+		}
+	}
+
+	if (thermal_value_avg_count) {/*Calculate Average thermal_value after average enough times*/
+		ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
+			("thermal_value_avg=0x%x(%d)  thermal_value_avg_count = %d\n"
+			, thermal_value_avg, thermal_value_avg, thermal_value_avg_count));
+
+		thermal_value = (u8)(thermal_value_avg / thermal_value_avg_count);
+
+		ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
+			("AVG Thermal Meter = 0x%X(%d), EEPROMthermalmeter = 0x%X(%d)\n", thermal_value, thermal_value, priv->pmib->dot11RFEntry.ther, priv->pmib->dot11RFEntry.ther));
+	}
+
+	/*4 Calculate delta, delta_LCK, delta_IQK.*/
+	delta = RTL_ABS(thermal_value, priv->pmib->dot11RFEntry.ther);
+	delta_LCK = RTL_ABS(thermal_value, p_dm_odm->rf_calibrate_info.thermal_value_lck);
+	delta_IQK = RTL_ABS(thermal_value, p_dm_odm->rf_calibrate_info.thermal_value_iqk);
+	is_increase = ((thermal_value < priv->pmib->dot11RFEntry.ther) ? 0 : 1);
+
+	if (delta > 29) { /* power track table index(thermal diff.) upper bound*/
+		ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("delta(%d) > 29, set delta to 29\n", delta));
+		delta = 29;
+	}
+
+
+	/*4 if necessary, do LCK.*/
+	if (delta_LCK > c.threshold_iqk) {
+		ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("delta_LCK(%d) >= threshold_iqk(%d)\n", delta_LCK, c.threshold_iqk));
+		p_dm_odm->rf_calibrate_info.thermal_value_lck = thermal_value;
+#if (RTL8822B_SUPPORT != 1)
+		if (!(p_dm_odm->support_ic_type & ODM_RTL8822B)) {
+		if (c.phy_lc_calibrate)
+			(*c.phy_lc_calibrate)(p_dm_odm);
+	}
+#endif
+	}
+
+	if (delta_IQK > c.threshold_iqk) {
+		ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("delta_IQK(%d) >= threshold_iqk(%d)\n", delta_IQK, c.threshold_iqk));
+		p_dm_odm->rf_calibrate_info.thermal_value_iqk = thermal_value;
+		if (c.do_iqk)
+			(*c.do_iqk)(p_dm_odm, true, 0, 0);
+	}
+
+	if (!priv->pmib->dot11RFEntry.ther)	/*Don't do power tracking since no calibrated thermal value*/
+		return;
+
+	/*4 Do Power Tracking*/
+
+	if (thermal_value != p_dm_odm->rf_calibrate_info.thermal_value) {
+		ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
+			     ("\n\n******** START POWER TRACKING ********\n"));
+		ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
+			("Readback Thermal Meter = 0x%x pre thermal meter 0x%x EEPROMthermalmeter 0x%x\n",
+			thermal_value, p_dm_odm->rf_calibrate_info.thermal_value, priv->pmib->dot11RFEntry.ther));
+
+#ifdef _TRACKING_TABLE_FILE
+		if (priv->pshare->rf_ft_var.pwr_track_file) {
+			if (is_increase) {			/*thermal is higher than base*/
+				for (p = ODM_RF_PATH_A; p < c.rf_path_count; p++) {
+					switch (p) {
+					case ODM_RF_PATH_B:
+						ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
+							("delta_swing_table_idx_tup_b[%d] = %d delta_swing_table_idx_tup_cck_b[%d] = %d\n", delta, delta_swing_table_idx_tup_b[delta], delta, delta_swing_table_idx_tup_cck_b[delta]));
+						p_rf_calibrate_info->absolute_ofdm_swing_idx[p] = delta_swing_table_idx_tup_b[delta];
+						p_rf_calibrate_info->absolute_cck_swing_idx[p] = delta_swing_table_idx_tup_cck_b[delta];
+						ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
+							("******Temp is higher and pRF->absolute_ofdm_swing_idx[ODM_RF_PATH_B] = %d pRF->absolute_cck_swing_idx[ODM_RF_PATH_B] = %d\n", p_rf_calibrate_info->absolute_ofdm_swing_idx[p], p_rf_calibrate_info->absolute_cck_swing_idx[p]));
+						break;
+
+					case ODM_RF_PATH_C:
+						ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
+							("delta_swing_table_idx_tup_c[%d] = %d delta_swing_table_idx_tup_cck_c[%d] = %d\n", delta, delta_swing_table_idx_tup_c[delta], delta, delta_swing_table_idx_tup_cck_c[delta]));
+						p_rf_calibrate_info->absolute_ofdm_swing_idx[p] = delta_swing_table_idx_tup_c[delta];
+						p_rf_calibrate_info->absolute_cck_swing_idx[p] = delta_swing_table_idx_tup_cck_c[delta];
+						ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
+							("******Temp is higher and pRF->absolute_ofdm_swing_idx[ODM_RF_PATH_C] = %d pRF->absolute_cck_swing_idx[ODM_RF_PATH_C] = %d\n", p_rf_calibrate_info->absolute_ofdm_swing_idx[p], p_rf_calibrate_info->absolute_cck_swing_idx[p]));
+						break;
+
+					case ODM_RF_PATH_D:
+						ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
+							("delta_swing_table_idx_tup_d[%d] = %d delta_swing_table_idx_tup_cck_d[%d] = %d\n", delta, delta_swing_table_idx_tup_d[delta], delta, delta_swing_table_idx_tup_cck_d[delta]));
+						p_rf_calibrate_info->absolute_ofdm_swing_idx[p] = delta_swing_table_idx_tup_d[delta];
+						p_rf_calibrate_info->absolute_cck_swing_idx[p] = delta_swing_table_idx_tup_cck_d[delta];
+						ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
+							("******Temp is higher and pRF->absolute_ofdm_swing_idx[ODM_RF_PATH_D] = %d pRF->absolute_cck_swing_idx[ODM_RF_PATH_D] = %d\n", p_rf_calibrate_info->absolute_ofdm_swing_idx[p], p_rf_calibrate_info->absolute_cck_swing_idx[p]));
+						break;
+					default:
+						ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
+							("delta_swing_table_idx_tup_a[%d] = %d delta_swing_table_idx_tup_cck_a[%d] = %d\n", delta, delta_swing_table_idx_tup_a[delta], delta, delta_swing_table_idx_tup_cck_a[delta]));
+						p_rf_calibrate_info->absolute_ofdm_swing_idx[p] = delta_swing_table_idx_tup_a[delta];
+						p_rf_calibrate_info->absolute_cck_swing_idx[p] = delta_swing_table_idx_tup_cck_a[delta];
+						ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
+							("******Temp is higher and pRF->absolute_ofdm_swing_idx[ODM_RF_PATH_A] = %d pRF->absolute_cck_swing_idx[ODM_RF_PATH_A] = %d\n", p_rf_calibrate_info->absolute_ofdm_swing_idx[p], p_rf_calibrate_info->absolute_cck_swing_idx[p]));
+						break;
+					}
+				}
+			} else {			/* thermal is lower than base*/
+				for (p = ODM_RF_PATH_A; p < c.rf_path_count; p++) {
+					switch (p) {
+					case ODM_RF_PATH_B:
+						ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
+							("delta_swing_table_idx_tdown_b[%d] = %d   delta_swing_table_idx_tdown_cck_b[%d] = %d\n", delta, delta_swing_table_idx_tdown_b[delta], delta, delta_swing_table_idx_tdown_cck_b[delta]));
+						p_rf_calibrate_info->absolute_ofdm_swing_idx[p] = -1 * delta_swing_table_idx_tdown_b[delta];
+						p_rf_calibrate_info->absolute_cck_swing_idx[p] = -1 * delta_swing_table_idx_tdown_cck_b[delta];
+						ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
+							("******Temp is lower and pRF->absolute_ofdm_swing_idx[ODM_RF_PATH_B] = %d   pRF->absolute_cck_swing_idx[ODM_RF_PATH_B] = %d\n", p_rf_calibrate_info->absolute_ofdm_swing_idx[p], p_rf_calibrate_info->absolute_cck_swing_idx[p]));
+						break;
+
+					case ODM_RF_PATH_C:
+						ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
+							("delta_swing_table_idx_tdown_c[%d] = %d   delta_swing_table_idx_tdown_cck_c[%d] = %d\n", delta, delta_swing_table_idx_tdown_c[delta], delta, delta_swing_table_idx_tdown_cck_c[delta]));
+						p_rf_calibrate_info->absolute_ofdm_swing_idx[p] = -1 * delta_swing_table_idx_tdown_c[delta];
+						p_rf_calibrate_info->absolute_cck_swing_idx[p] = -1 * delta_swing_table_idx_tdown_cck_c[delta];
+						ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
+							("******Temp is lower and pRF->absolute_ofdm_swing_idx[ODM_RF_PATH_C] = %d   pRF->absolute_cck_swing_idx[ODM_RF_PATH_C] = %d\n", p_rf_calibrate_info->absolute_ofdm_swing_idx[p], p_rf_calibrate_info->absolute_cck_swing_idx[p]));
+						break;
+
+					case ODM_RF_PATH_D:
+						ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
+							("delta_swing_table_idx_tdown_d[%d] = %d   delta_swing_table_idx_tdown_cck_d[%d] = %d\n", delta, delta_swing_table_idx_tdown_d[delta], delta, delta_swing_table_idx_tdown_cck_d[delta]));
+						p_rf_calibrate_info->absolute_ofdm_swing_idx[p] = -1 * delta_swing_table_idx_tdown_d[delta];
+						p_rf_calibrate_info->absolute_cck_swing_idx[p] = -1 * delta_swing_table_idx_tdown_cck_d[delta];
+						ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
+							("******Temp is lower and pRF->absolute_ofdm_swing_idx[ODM_RF_PATH_D] = %d   pRF->absolute_cck_swing_idx[ODM_RF_PATH_D] = %d\n", p_rf_calibrate_info->absolute_ofdm_swing_idx[p], p_rf_calibrate_info->absolute_cck_swing_idx[p]));
+						break;
+
+					default:
+						ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
+							("delta_swing_table_idx_tdown_a[%d] = %d   delta_swing_table_idx_tdown_cck_a[%d] = %d\n", delta, delta_swing_table_idx_tdown_a[delta], delta, delta_swing_table_idx_tdown_cck_a[delta]));
+						p_rf_calibrate_info->absolute_ofdm_swing_idx[p] = -1 * delta_swing_table_idx_tdown_a[delta];
+						p_rf_calibrate_info->absolute_cck_swing_idx[p] = -1 * delta_swing_table_idx_tdown_cck_a[delta];
+						ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
+							("******Temp is lower and pRF->absolute_ofdm_swing_idx[ODM_RF_PATH_A] = %d   pRF->absolute_cck_swing_idx[ODM_RF_PATH_A] = %d\n", p_rf_calibrate_info->absolute_ofdm_swing_idx[p], p_rf_calibrate_info->absolute_cck_swing_idx[p]));
+						break;
+					}
+				}
+			}
+
+			if (is_increase) {
+				ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, (">>> increse power --->\n"));
+				if (GET_CHIP_VER(priv) == VERSION_8197F) {
+					for (p = ODM_RF_PATH_A; p < c.rf_path_count; p++)
+						(*c.odm_tx_pwr_track_set_pwr)(p_dm_odm, BBSWING, p, 0);
+				} else if (GET_CHIP_VER(priv) == VERSION_8822B) {
+					for (p = ODM_RF_PATH_A; p < c.rf_path_count; p++)
+						(*c.odm_tx_pwr_track_set_pwr)(p_dm_odm, MIX_MODE, p, 0);
+				}
+			} else {
+				ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, (">>> decrese power --->\n"));
+				if (GET_CHIP_VER(priv) == VERSION_8197F) {
+					for (p = ODM_RF_PATH_A; p < c.rf_path_count; p++)
+						(*c.odm_tx_pwr_track_set_pwr)(p_dm_odm, BBSWING, p, 0);
+				} else if (GET_CHIP_VER(priv) == VERSION_8822B) {
+					for (p = ODM_RF_PATH_A; p < c.rf_path_count; p++)
+						(*c.odm_tx_pwr_track_set_pwr)(p_dm_odm, MIX_MODE, p, 0);
+				}
+			}
+		}
+#endif
+
+		ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("\n******** END:%s() ********\n\n", __func__));
+		/*update thermal meter value*/
+		p_dm_odm->rf_calibrate_info.thermal_value =  thermal_value;
+
+	}
+
+#endif
+}
+#endif
+
+/*#if (RTL8814A_SUPPORT == 1)*/
+#if (RTL8814A_SUPPORT == 1)
+
+void
+odm_txpowertracking_callback_thermal_meter_jaguar_series2(
+#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
+	void		*p_dm_void
+#else
+	struct _ADAPTER	*adapter
+#endif
+)
+{
+	struct PHY_DM_STRUCT		*p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
+	u8			thermal_value = 0, delta, delta_LCK, delta_IQK, channel, is_increase;
+	u8			thermal_value_avg_count = 0, p = 0, i = 0;
+	u32			thermal_value_avg = 0, reg0x18;
+	u32			bb_swing_reg[4] = {REG_A_TX_SCALE_JAGUAR, REG_B_TX_SCALE_JAGUAR, REG_C_TX_SCALE_JAGUAR2, REG_D_TX_SCALE_JAGUAR2};
+	s32			ele_D;
+	u32			bb_swing_idx;
+	struct rtl8192cd_priv	*priv = p_dm_odm->priv;
+	struct _TXPWRTRACK_CFG	c;
+	boolean			is_tssi_enable = false;
+	struct odm_rf_calibration_structure	*p_rf_calibrate_info = &(p_dm_odm->rf_calibrate_info);
+
+	/* 4 1. The following TWO tables decide the final index of OFDM/CCK swing table. */
+	u8			*delta_swing_table_idx_tup_a = NULL, *delta_swing_table_idx_tdown_a = NULL;
+	u8			*delta_swing_table_idx_tup_b = NULL, *delta_swing_table_idx_tdown_b = NULL;
+	/* for 8814 add by Yu Chen */
+	u8			*delta_swing_table_idx_tup_c = NULL, *delta_swing_table_idx_tdown_c = NULL;
+	u8			*delta_swing_table_idx_tup_d = NULL, *delta_swing_table_idx_tdown_d = NULL;
+
+#ifdef MP_TEST
+	if ((OPMODE & WIFI_MP_STATE) || priv->pshare->rf_ft_var.mp_specific) {
+		channel = priv->pshare->working_channel;
+		if (priv->pshare->mp_txpwr_tracking == false)
+			return;
+	} else
+#endif
+	{
+		channel = (priv->pmib->dot11RFEntry.dot11channel);
+	}
+
+	configure_txpower_track(p_dm_odm, &c);
+	p_rf_calibrate_info->default_ofdm_index = priv->pshare->OFDM_index0[ODM_RF_PATH_A];
+
+	(*c.get_delta_swing_table)(p_dm_odm, (u8 **)&delta_swing_table_idx_tup_a, (u8 **)&delta_swing_table_idx_tdown_a,
+		(u8 **)&delta_swing_table_idx_tup_b, (u8 **)&delta_swing_table_idx_tdown_b);
+
+	if (p_dm_odm->support_ic_type & ODM_RTL8814A)	/* for 8814 path C & D */
+		(*c.get_delta_swing_table8814only)(p_dm_odm, (u8 **)&delta_swing_table_idx_tup_c, (u8 **)&delta_swing_table_idx_tdown_c,
+			(u8 **)&delta_swing_table_idx_tup_d, (u8 **)&delta_swing_table_idx_tdown_d);
+
+	thermal_value = (u8)odm_get_rf_reg(p_dm_odm, ODM_RF_PATH_A, c.thermal_reg_addr, 0xfc00); /* 0x42: RF Reg[15:10] 88E */
+	ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
+		("\nReadback Thermal Meter = 0x%x, pre thermal meter 0x%x, EEPROMthermalmeter 0x%x\n", thermal_value, p_dm_odm->rf_calibrate_info.thermal_value, priv->pmib->dot11RFEntry.ther));
+
+	/* Initialize */
+	if (!p_dm_odm->rf_calibrate_info.thermal_value)
+		p_dm_odm->rf_calibrate_info.thermal_value = priv->pmib->dot11RFEntry.ther;
+
+	if (!p_dm_odm->rf_calibrate_info.thermal_value_lck)
+		p_dm_odm->rf_calibrate_info.thermal_value_lck = priv->pmib->dot11RFEntry.ther;
+
+	if (!p_dm_odm->rf_calibrate_info.thermal_value_iqk)
+		p_dm_odm->rf_calibrate_info.thermal_value_iqk = priv->pmib->dot11RFEntry.ther;
+
+	is_tssi_enable = (boolean)odm_get_rf_reg(p_dm_odm, ODM_RF_PATH_A, REG_RF_TX_GAIN_OFFSET, BIT(7));	/* check TSSI enable */
+
+	/* 4 Query OFDM BB swing default setting 	Bit[31:21] */
+	for (p = ODM_RF_PATH_A ; p < c.rf_path_count ; p++) {
+		ele_D = odm_get_bb_reg(p_dm_odm, bb_swing_reg[p], 0xffe00000);
+		ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
+			("0x%x:0x%x ([31:21] = 0x%x)\n", bb_swing_reg[p], odm_get_bb_reg(p_dm_odm, bb_swing_reg[p], MASKDWORD), ele_D));
+
+		for (bb_swing_idx = 0; bb_swing_idx < TXSCALE_TABLE_SIZE; bb_swing_idx++) {/* 4 */
+			if (ele_D == tx_scaling_table_jaguar[bb_swing_idx]) {
+				p_dm_odm->rf_calibrate_info.OFDM_index[p] = (u8)bb_swing_idx;
+				ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
+					("OFDM_index[%d]=%d\n", p, p_dm_odm->rf_calibrate_info.OFDM_index[p]));
+				break;
+			}
+		}
+		ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("kfree_offset[%d]=%d\n", p, p_rf_calibrate_info->kfree_offset[p]));
+
+	}
+
+	/* calculate average thermal meter */
+	p_dm_odm->rf_calibrate_info.thermal_value_avg[p_dm_odm->rf_calibrate_info.thermal_value_avg_index] = thermal_value;
+	p_dm_odm->rf_calibrate_info.thermal_value_avg_index++;
+	if (p_dm_odm->rf_calibrate_info.thermal_value_avg_index == c.average_thermal_num)  /* Average times =  c.average_thermal_num */
+		p_dm_odm->rf_calibrate_info.thermal_value_avg_index = 0;
+
+	for (i = 0; i < c.average_thermal_num; i++) {
+		if (p_dm_odm->rf_calibrate_info.thermal_value_avg[i]) {
+			thermal_value_avg += p_dm_odm->rf_calibrate_info.thermal_value_avg[i];
+			thermal_value_avg_count++;
+		}
+	}
+
+	if (thermal_value_avg_count) {            /* Calculate Average thermal_value after average enough times */
+		thermal_value = (u8)(thermal_value_avg / thermal_value_avg_count);
+		ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
+			("AVG Thermal Meter = 0x%X, EEPROMthermalmeter = 0x%X\n", thermal_value, priv->pmib->dot11RFEntry.ther));
+	}
+
+	/* 4 Calculate delta, delta_LCK, delta_IQK. */
+	delta = RTL_ABS(thermal_value, priv->pmib->dot11RFEntry.ther);
+	delta_LCK = RTL_ABS(thermal_value, p_dm_odm->rf_calibrate_info.thermal_value_lck);
+	delta_IQK = RTL_ABS(thermal_value, p_dm_odm->rf_calibrate_info.thermal_value_iqk);
+	is_increase = ((thermal_value < priv->pmib->dot11RFEntry.ther) ? 0 : 1);
+
+	/* 4 if necessary, do LCK. */
+	if (!(p_dm_odm->support_ic_type & ODM_RTL8821)) {
+		if (delta_LCK > c.threshold_iqk) {
+			ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("delta_LCK(%d) >= threshold_iqk(%d)\n", delta_LCK, c.threshold_iqk));
+			p_dm_odm->rf_calibrate_info.thermal_value_lck = thermal_value;
+
+			/*Use RTLCK, so close power tracking driver LCK*/
+#if (RTL8814A_SUPPORT != 1)
+			if (!(p_dm_odm->support_ic_type & ODM_RTL8814A)) {
+				if (c.phy_lc_calibrate)
+					(*c.phy_lc_calibrate)(p_dm_odm);
+			}
+#endif
+		}
+	}
+
+	if (delta_IQK > c.threshold_iqk) {
+		panic_printk("%s(%d)\n", __FUNCTION__, __LINE__);
+		ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("delta_IQK(%d) >= threshold_iqk(%d)\n", delta_IQK, c.threshold_iqk));
+		p_dm_odm->rf_calibrate_info.thermal_value_iqk = thermal_value;
+		if (c.do_iqk)
+			(*c.do_iqk)(p_dm_odm, true, 0, 0);
+	}
+
+	if (!priv->pmib->dot11RFEntry.ther)	/*Don't do power tracking since no calibrated thermal value*/
+		return;
+
+	/* 4 Do Power Tracking */
+
+	if (is_tssi_enable == true) {
+		ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("**********Enter PURE TSSI MODE**********\n"));
+		for (p = ODM_RF_PATH_A; p < c.rf_path_count; p++)
+			(*c.odm_tx_pwr_track_set_pwr)(p_dm_odm, TSSI_MODE, p, 0);
+	} else if (thermal_value != p_dm_odm->rf_calibrate_info.thermal_value) {
+		ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
+			     ("\n******** START POWER TRACKING ********\n"));
+		ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
+			("\nReadback Thermal Meter = 0x%x pre thermal meter 0x%x EEPROMthermalmeter 0x%x\n", thermal_value, p_dm_odm->rf_calibrate_info.thermal_value, priv->pmib->dot11RFEntry.ther));
+
+#ifdef _TRACKING_TABLE_FILE
+		if (priv->pshare->rf_ft_var.pwr_track_file) {
+			if (is_increase) {		/* thermal is higher than base */
+				for (p = ODM_RF_PATH_A; p < c.rf_path_count; p++) {
+					switch (p) {
+					case ODM_RF_PATH_B:
+						ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
+							("delta_swing_table_idx_tup_b[%d] = %d\n", delta, delta_swing_table_idx_tup_b[delta]));
+						p_rf_calibrate_info->absolute_ofdm_swing_idx[p] = delta_swing_table_idx_tup_b[delta];       /* Record delta swing for mix mode power tracking */
+						ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
+							("******Temp is higher and p_dm_odm->absolute_ofdm_swing_idx[ODM_RF_PATH_B] = %d\n", p_rf_calibrate_info->absolute_ofdm_swing_idx[p]));
+						break;
+
+					case ODM_RF_PATH_C:
+						ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
+							("delta_swing_table_idx_tup_c[%d] = %d\n", delta, delta_swing_table_idx_tup_c[delta]));
+						p_rf_calibrate_info->absolute_ofdm_swing_idx[p] = delta_swing_table_idx_tup_c[delta];       /* Record delta swing for mix mode power tracking */
+						ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
+							("******Temp is higher and p_dm_odm->absolute_ofdm_swing_idx[ODM_RF_PATH_C] = %d\n", p_rf_calibrate_info->absolute_ofdm_swing_idx[p]));
+						break;
+
+					case ODM_RF_PATH_D:
+						ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
+							("delta_swing_table_idx_tup_d[%d] = %d\n", delta, delta_swing_table_idx_tup_d[delta]));
+						p_rf_calibrate_info->absolute_ofdm_swing_idx[p] = delta_swing_table_idx_tup_d[delta];       /* Record delta swing for mix mode power tracking */
+						ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
+							("******Temp is higher and p_dm_odm->absolute_ofdm_swing_idx[ODM_RF_PATH_D] = %d\n", p_rf_calibrate_info->absolute_ofdm_swing_idx[p]));
+						break;
+
+					default:
+						ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
+							("delta_swing_table_idx_tup_a[%d] = %d\n", delta, delta_swing_table_idx_tup_a[delta]));
+						p_rf_calibrate_info->absolute_ofdm_swing_idx[p] = delta_swing_table_idx_tup_a[delta];        /* Record delta swing for mix mode power tracking */
+						ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
+							("******Temp is higher and p_dm_odm->absolute_ofdm_swing_idx[ODM_RF_PATH_A] = %d\n", p_rf_calibrate_info->absolute_ofdm_swing_idx[p]));
+						break;
+					}
+				}
+			} else {				/* thermal is lower than base */
+				for (p = ODM_RF_PATH_A; p < c.rf_path_count; p++) {
+					switch (p) {
+					case ODM_RF_PATH_B:
+						ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
+							("delta_swing_table_idx_tdown_b[%d] = %d\n", delta, delta_swing_table_idx_tdown_b[delta]));
+						p_rf_calibrate_info->absolute_ofdm_swing_idx[p] = -1 * delta_swing_table_idx_tdown_b[delta];        /* Record delta swing for mix mode power tracking */
+						ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
+							("******Temp is lower and p_dm_odm->absolute_ofdm_swing_idx[ODM_RF_PATH_B] = %d\n", p_rf_calibrate_info->absolute_ofdm_swing_idx[p]));
+						break;
+
+					case ODM_RF_PATH_C:
+						ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
+							("delta_swing_table_idx_tdown_c[%d] = %d\n", delta, delta_swing_table_idx_tdown_c[delta]));
+						p_rf_calibrate_info->absolute_ofdm_swing_idx[p] = -1 * delta_swing_table_idx_tdown_c[delta];        /* Record delta swing for mix mode power tracking */
+						ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
+							("******Temp is lower and p_dm_odm->absolute_ofdm_swing_idx[ODM_RF_PATH_C] = %d\n", p_rf_calibrate_info->absolute_ofdm_swing_idx[p]));
+						break;
+
+					case ODM_RF_PATH_D:
+						ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
+							("delta_swing_table_idx_tdown_d[%d] = %d\n", delta, delta_swing_table_idx_tdown_d[delta]));
+						p_rf_calibrate_info->absolute_ofdm_swing_idx[p] = -1 * delta_swing_table_idx_tdown_d[delta];        /* Record delta swing for mix mode power tracking */
+						ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
+							("******Temp is lower and p_dm_odm->absolute_ofdm_swing_idx[ODM_RF_PATH_D] = %d\n", p_rf_calibrate_info->absolute_ofdm_swing_idx[p]));
+						break;
+
+					default:
+						ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
+							("delta_swing_table_idx_tdown_a[%d] = %d\n", delta, delta_swing_table_idx_tdown_a[delta]));
+						p_rf_calibrate_info->absolute_ofdm_swing_idx[p] = -1 * delta_swing_table_idx_tdown_a[delta];        /* Record delta swing for mix mode power tracking */
+						ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
+							("******Temp is lower and p_dm_odm->absolute_ofdm_swing_idx[ODM_RF_PATH_A] = %d\n", p_rf_calibrate_info->absolute_ofdm_swing_idx[p]));
+						break;
+					}
+				}
+			}
+
+			if (is_increase) {
+				ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, (">>> increse power --->\n"));
+				for (p = ODM_RF_PATH_A; p < c.rf_path_count; p++)
+					(*c.odm_tx_pwr_track_set_pwr)(p_dm_odm, MIX_MODE, p, 0);
+			} else {
+				ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, (">>> decrese power --->\n"));
+				for (p = ODM_RF_PATH_A; p < c.rf_path_count; p++)
+					(*c.odm_tx_pwr_track_set_pwr)(p_dm_odm, MIX_MODE, p, 0);
+			}
+		}
+#endif
+
+		ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("\n******** END:%s() ********\n", __FUNCTION__));
+		/* update thermal meter value */
+		p_dm_odm->rf_calibrate_info.thermal_value =  thermal_value;
+
+	}
+}
+#endif
+
+#if (RTL8812A_SUPPORT == 1 || RTL8881A_SUPPORT == 1)
+void
+odm_txpowertracking_callback_thermal_meter_jaguar_series(
+#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
+	void		*p_dm_void
+#else
+	struct _ADAPTER	*adapter
+#endif
+)
+{
+	struct PHY_DM_STRUCT		*p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
+	unsigned char			thermal_value = 0, delta, delta_LCK, channel, is_decrease;
+	unsigned char			thermal_value_avg_count = 0;
+	unsigned int			thermal_value_avg = 0, reg0x18;
+	unsigned int			bb_swing_reg[4] = {0xc1c, 0xe1c, 0x181c, 0x1a1c};
+	int					ele_D, value32;
+	char					OFDM_index[2], index;
+	unsigned int			i = 0, j = 0, rf_path, max_rf_path = 2, rf;
+	struct rtl8192cd_priv		*priv = p_dm_odm->priv;
+	unsigned char			OFDM_min_index = 7; /* OFDM BB Swing should be less than +2.5dB, which is required by Arthur and Mimic */
+
+
+
+#ifdef MP_TEST
+	if ((OPMODE & WIFI_MP_STATE) || priv->pshare->rf_ft_var.mp_specific) {
+		channel = priv->pshare->working_channel;
+		if (priv->pshare->mp_txpwr_tracking == false)
+			return;
+	} else
+#endif
+	{
+		channel = (priv->pmib->dot11RFEntry.dot11channel);
+	}
+
+#if RTL8881A_SUPPORT
+	if (p_dm_odm->support_ic_type == ODM_RTL8881A) {
+		max_rf_path = 1;
+		if ((get_bonding_type_8881A() == BOND_8881AM || get_bonding_type_8881A() == BOND_8881AN)
+		    && priv->pshare->rf_ft_var.use_intpa8881A && (*p_dm_odm->p_band_type == ODM_BAND_2_4G))
+			OFDM_min_index = 6;		/* intPA - upper bond set to +3 dB (base: -2 dB)ot11RFEntry.phy_band_select == PHY_BAND_2G)) */
+		else
+			OFDM_min_index = 10;		/* OFDM BB Swing should be less than +1dB, which is required by Arthur and Mimic */
+	}
+#endif
+
+
+	thermal_value = (unsigned char)phy_query_rf_reg(priv, RF_PATH_A, 0x42, 0xfc00, 1); /* 0x42: RF Reg[15:10] 88E */
+	ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("\nReadback Thermal Meter = 0x%x pre thermal meter 0x%x EEPROMthermalmeter 0x%x\n", thermal_value, priv->pshare->thermal_value, priv->pmib->dot11RFEntry.ther));
+
+
+	/* 4 Query OFDM BB swing default setting 	Bit[31:21] */
+	for (rf_path = 0 ; rf_path < max_rf_path ; rf_path++) {
+		ele_D = phy_query_bb_reg(priv, bb_swing_reg[rf_path], 0xffe00000);
+		ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("0x%x:0x%x ([31:21] = 0x%x)\n", bb_swing_reg[rf_path], phy_query_bb_reg(priv, bb_swing_reg[rf_path], MASKDWORD), ele_D));
+		for (i = 0; i < OFDM_TABLE_SIZE_8812; i++) {/* 4 */
+			if (ele_D == ofdm_swing_table_8812[i]) {
+				OFDM_index[rf_path] = (unsigned char)i;
+				ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("OFDM_index[%d]=%d\n", rf_path, OFDM_index[rf_path]));
+				break;
+			}
+		}
+	}
+#if 0
+	/* Query OFDM path A default setting 	Bit[31:21] */
+	ele_D = phy_query_bb_reg(priv, 0xc1c, 0xffe00000);
+	ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("0xc1c:0x%x ([31:21] = 0x%x)\n", phy_query_bb_reg(priv, 0xc1c, MASKDWORD), ele_D));
+	for (i = 0; i < OFDM_TABLE_SIZE_8812; i++) {/* 4 */
+		if (ele_D == ofdm_swing_table_8812[i]) {
+			OFDM_index[0] = (unsigned char)i;
+			ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("OFDM_index[0]=%d\n", OFDM_index[0]));
+			break;
+		}
+	}
+	/* Query OFDM path B default setting */
+	if (rf == 2) {
+		ele_D = phy_query_bb_reg(priv, 0xe1c, 0xffe00000);
+		ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("0xe1c:0x%x ([32:21] = 0x%x)\n", phy_query_bb_reg(priv, 0xe1c, MASKDWORD), ele_D));
+		for (i = 0; i < OFDM_TABLE_SIZE_8812; i++) {
+			if (ele_D == ofdm_swing_table_8812[i]) {
+				OFDM_index[1] = (unsigned char)i;
+				ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("OFDM_index[1]=%d\n", OFDM_index[1]));
+				break;
+			}
+		}
+	}
+#endif
+	/* Initialize */
+	if (!priv->pshare->thermal_value) {
+		priv->pshare->thermal_value = priv->pmib->dot11RFEntry.ther;
+		priv->pshare->thermal_value_lck = thermal_value;
+	}
+
+	/* calculate average thermal meter */
+	{
+		priv->pshare->thermal_value_avg_8812[priv->pshare->thermal_value_avg_index_8812] = thermal_value;
+		priv->pshare->thermal_value_avg_index_8812++;
+		if (priv->pshare->thermal_value_avg_index_8812 == AVG_THERMAL_NUM_8812)
+			priv->pshare->thermal_value_avg_index_8812 = 0;
+
+		for (i = 0; i < AVG_THERMAL_NUM_8812; i++) {
+			if (priv->pshare->thermal_value_avg_8812[i]) {
+				thermal_value_avg += priv->pshare->thermal_value_avg_8812[i];
+				thermal_value_avg_count++;
+			}
+		}
+
+		if (thermal_value_avg_count) {
+			thermal_value = (unsigned char)(thermal_value_avg / thermal_value_avg_count);
+			/* printk("AVG Thermal Meter = 0x%x\n", thermal_value); */
+		}
+	}
+
+
+	/* 4 If necessary,  do power tracking */
+
+	if (!priv->pmib->dot11RFEntry.ther) /*Don't do power tracking since no calibrated thermal value*/
+		return;
+
+	if (thermal_value != priv->pshare->thermal_value) {
+		ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("\n******** START POWER TRACKING ********\n"));
+		ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("\nReadback Thermal Meter = 0x%x pre thermal meter 0x%x EEPROMthermalmeter 0x%x\n", thermal_value, priv->pshare->thermal_value, priv->pmib->dot11RFEntry.ther));
+		delta = RTL_ABS(thermal_value, priv->pmib->dot11RFEntry.ther);
+		delta_LCK = RTL_ABS(thermal_value, priv->pshare->thermal_value_lck);
+		is_decrease = ((thermal_value < priv->pmib->dot11RFEntry.ther) ? 1 : 0);
+		/* if (*p_dm_odm->p_band_type == ODM_BAND_5G) */
+		{
+#ifdef _TRACKING_TABLE_FILE
+			if (priv->pshare->rf_ft_var.pwr_track_file) {
+				for (rf_path = 0; rf_path < max_rf_path; rf_path++) {
+					ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("diff: (%s)%d ==> get index from table : %d)\n", (is_decrease ? "-" : "+"), delta, get_tx_tracking_index(priv, channel, rf_path, delta, is_decrease, 0)));
+					if (is_decrease) {
+						OFDM_index[rf_path] = priv->pshare->OFDM_index0[rf_path] + get_tx_tracking_index(priv, channel, rf_path, delta, is_decrease, 0);
+						OFDM_index[rf_path] = ((OFDM_index[rf_path] > (OFDM_TABLE_SIZE_8812 - 1)) ? (OFDM_TABLE_SIZE_8812 - 1) : OFDM_index[rf_path]);
+						ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, (">>> decrese power ---> new OFDM_INDEX:%d (%d + %d)\n", OFDM_index[rf_path], priv->pshare->OFDM_index0[rf_path], get_tx_tracking_index(priv, channel, rf_path, delta, is_decrease, 0)));
+#if 0/* RTL8881A_SUPPORT */
+						if (p_dm_odm->support_ic_type == ODM_RTL8881A) {
+							if (priv->pshare->rf_ft_var.pwrtrk_tx_agc_enable) {
+								if (priv->pshare->add_tx_agc) { /* tx_agc has been added */
+									add_tx_power88xx_ac(priv, 0);
+									priv->pshare->add_tx_agc = 0;
+									priv->pshare->add_tx_agc_index = 0;
+								}
+							}
+						}
+#endif
+					} else {
+
+						OFDM_index[rf_path] = priv->pshare->OFDM_index0[rf_path] - get_tx_tracking_index(priv, channel, rf_path, delta, is_decrease, 0);
+#if 0/* RTL8881A_SUPPORT */
+						if (p_dm_odm->support_ic_type == ODM_RTL8881A) {
+							if (priv->pshare->rf_ft_var.pwrtrk_tx_agc_enable) {
+								if (OFDM_index[i] < OFDM_min_index) {
+									priv->pshare->add_tx_agc_index = (OFDM_min_index - OFDM_index[i]) / 2; /* Calculate Remnant tx_agc value,  2 index for 1 tx_agc */
+									add_tx_power88xx_ac(priv, priv->pshare->add_tx_agc_index);
+									priv->pshare->add_tx_agc = 1;     /* add_tx_agc Flag = 1 */
+									OFDM_index[i] = OFDM_min_index;
+								} else {
+									if (priv->pshare->add_tx_agc) { /* tx_agc been added */
+										priv->pshare->add_tx_agc = 0;
+										priv->pshare->add_tx_agc_index = 0;
+										add_tx_power88xx_ac(priv, 0); /* minus the added TPI */
+									}
+								}
+							}
+						}
+#else
+						OFDM_index[rf_path] = ((OFDM_index[rf_path] < OFDM_min_index) ?  OFDM_min_index : OFDM_index[rf_path]);
+#endif
+						ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, (">>> increse power ---> new OFDM_INDEX:%d (%d - %d)\n", OFDM_index[rf_path], priv->pshare->OFDM_index0[rf_path], get_tx_tracking_index(priv, channel, rf_path, delta, is_decrease, 0)));
+					}
+				}
+			}
+#endif
+			/* 4 Set new BB swing index */
+			for (rf_path = 0; rf_path < max_rf_path; rf_path++) {
+				phy_set_bb_reg(priv, bb_swing_reg[rf_path], 0xffe00000, ofdm_swing_table_8812[(unsigned int)OFDM_index[rf_path]]);
+				ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("Readback 0x%x[31:21] = 0x%x, OFDM_index:%d\n", bb_swing_reg[rf_path], phy_query_bb_reg(priv, bb_swing_reg[rf_path], 0xffe00000), OFDM_index[rf_path]));
+			}
+
+		}
+		if (delta_LCK > 8) {
+			RTL_W8(0x522, 0xff);
+			reg0x18 = phy_query_rf_reg(priv, RF_PATH_A, 0x18, MASK20BITS, 1);
+			phy_set_rf_reg(priv, RF_PATH_A, 0xB4, BIT(14), 1);
+			phy_set_rf_reg(priv, RF_PATH_A, 0x18, BIT(15), 1);
+			delay_ms(200); /* frequency deviation */
+			phy_set_rf_reg(priv, RF_PATH_A, 0xB4, BIT(14), 0);
+			phy_set_rf_reg(priv, RF_PATH_A, 0x18, MASK20BITS, reg0x18);
+#ifdef CONFIG_RTL_8812_SUPPORT
+			if (GET_CHIP_VER(priv) == VERSION_8812E)
+				update_bbrf_val8812(priv, priv->pmib->dot11RFEntry.dot11channel);
+#endif
+			RTL_W8(0x522, 0x0);
+			priv->pshare->thermal_value_lck = thermal_value;
+		}
+		ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("\n******** END:%s() ********\n", __FUNCTION__));
+
+		/* update thermal meter value */
+		priv->pshare->thermal_value = thermal_value;
+		for (rf_path = 0; rf_path < max_rf_path; rf_path++)
+			priv->pshare->OFDM_index[rf_path] = OFDM_index[rf_path];
+	}
+}
+
+#endif
+
+
+void
+odm_txpowertracking_callback_thermal_meter(
+#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
+	void		*p_dm_void
+#else
+	struct _ADAPTER	*adapter
+#endif
+)
+{
+	struct PHY_DM_STRUCT		*p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
+	struct odm_rf_calibration_structure	*p_rf_calibrate_info = &(p_dm_odm->rf_calibrate_info);
+
+
+#if (RTL8197F_SUPPORT == 1 || RTL8822B_SUPPORT == 1)
+	if (p_dm_odm->support_ic_type == ODM_RTL8197F || p_dm_odm->support_ic_type == ODM_RTL8822B) {
+		odm_txpowertracking_callback_thermal_meter_jaguar_series3(p_dm_odm);
+		return;
+	}
+#endif
+#if (RTL8814A_SUPPORT == 1)		/*use this function to do power tracking after 8814 by YuChen*/
+	if (p_dm_odm->support_ic_type & ODM_RTL8814A) {
+		odm_txpowertracking_callback_thermal_meter_jaguar_series2(p_dm_odm);
+		return;
+	}
+#endif
+#if (RTL8881A_SUPPORT || RTL8812A_SUPPORT == 1)
+	if (p_dm_odm->support_ic_type & ODM_RTL8812 || p_dm_odm->support_ic_type & ODM_RTL8881A) {
+		odm_txpowertracking_callback_thermal_meter_jaguar_series(p_dm_odm);
+		return;
+	}
+#endif
+
+#if (RTL8192E_SUPPORT == 1)
+	if (p_dm_odm->support_ic_type == ODM_RTL8192E) {
+		odm_txpowertracking_callback_thermal_meter_92e(p_dm_odm);
+		return;
+	}
+#endif
+
+#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
+	HAL_DATA_TYPE	*p_hal_data = GET_HAL_DATA(adapter);
+	/* PMGNT_INFO      		p_mgnt_info = &adapter->mgnt_info; */
+#endif
+
+
+	u8			thermal_value = 0, delta, delta_LCK, delta_IQK, offset;
+	u8			thermal_value_avg_count = 0;
+	u32			thermal_value_avg = 0;
+	/*	s32			ele_A=0, ele_D, TempCCk, X, value32;
+	 *	s32			Y, ele_C=0;
+	 *	s8			OFDM_index[2], CCK_index=0, OFDM_index_old[2]={0,0}, CCK_index_old=0, index;
+	 *	s8			deltaPowerIndex = 0; */
+	u32			i = 0;/* , j = 0; */
+	boolean		is2T = false;
+	/*	bool 		bInteralPA = false; */
+
+	u8			OFDM_max_index = 34, rf = (is2T) ? 2 : 1; /* OFDM BB Swing should be less than +3.0dB, which is required by Arthur */
+	u8			indexforchannel = 0;/*get_right_chnl_place_for_iqk(p_hal_data->current_channel)*/
+	enum            _POWER_DEC_INC { POWER_DEC, POWER_INC };
+#if (DM_ODM_SUPPORT_TYPE == ODM_CE)
+	struct PHY_DM_STRUCT		*p_dm_odm = &p_hal_data->odmpriv;
+#endif
+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
+	struct PHY_DM_STRUCT		*p_dm_odm = &p_hal_data->DM_OutSrc;
+#endif
+
+	struct _TXPWRTRACK_CFG	c;
+
+
+	/* 4 1. The following TWO tables decide the final index of OFDM/CCK swing table. */
+	s8			delta_swing_table_idx[2][index_mapping_NUM_88E] = {
+		/* {{Power decreasing(lower temperature)}, {Power increasing(higher temperature)}} */
+		{0, 0, 2, 3, 4, 4, 5, 6, 7, 7, 8, 9, 10, 10, 11}, {0, 0, 1, 2, 3, 4, 4, 4, 4, 5, 7, 8, 9, 9, 10}
+	};
+	u8			thermal_threshold[2][index_mapping_NUM_88E] = {
+		/* {{Power decreasing(lower temperature)}, {Power increasing(higher temperature)}} */
+		{0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 27}, {0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 25, 25, 25}
+	};
+
+#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
+	struct rtl8192cd_priv	*priv = p_dm_odm->priv;
+#endif
+
+	/* 4 2. Initilization ( 7 steps in total ) */
+
+	configure_txpower_track(p_dm_odm, &c);
+
+	p_dm_odm->rf_calibrate_info.txpowertracking_callback_cnt++; /* cosa add for debug */
+	p_dm_odm->rf_calibrate_info.is_txpowertracking_init = true;
+
+#if (MP_DRIVER == 1)
+	p_dm_odm->rf_calibrate_info.txpowertrack_control = p_hal_data->txpowertrack_control; /* <Kordan> We should keep updating the control variable according to HalData.
+     * <Kordan> rf_calibrate_info.rega24 will be initialized when ODM HW configuring, but MP configures with para files. */
+	p_dm_odm->rf_calibrate_info.rega24 = 0x090e1317;
+#endif
+
+#if (DM_ODM_SUPPORT_TYPE == ODM_AP) && defined(MP_TEST)
+	if ((OPMODE & WIFI_MP_STATE) || p_dm_odm->priv->pshare->rf_ft_var.mp_specific) {
+		if (p_dm_odm->priv->pshare->mp_txpwr_tracking == false)
+			return;
+	}
+#endif
+	ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("===>odm_txpowertracking_callback_thermal_meter_8188e, p_dm_odm->bb_swing_idx_cck_base: %d, p_dm_odm->bb_swing_idx_ofdm_base: %d\n", p_rf_calibrate_info->bb_swing_idx_cck_base, p_rf_calibrate_info->bb_swing_idx_ofdm_base));
+	/*
+		if (!p_dm_odm->rf_calibrate_info.tm_trigger) {
+			odm_set_rf_reg(p_dm_odm, RF_PATH_A, c.thermal_reg_addr, BIT(17) | BIT(16), 0x3);
+			p_dm_odm->rf_calibrate_info.tm_trigger = 1;
+			return;
+		}
+	*/
+	thermal_value = (u8)odm_get_rf_reg(p_dm_odm, RF_PATH_A, c.thermal_reg_addr, 0xfc00);	/* 0x42: RF Reg[15:10] 88E */
+#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
+	if (!thermal_value || !p_dm_odm->rf_calibrate_info.txpowertrack_control)
+#else
+	if (!p_dm_odm->rf_calibrate_info.txpowertrack_control)
+#endif
+		return;
+
+	/* 4 3. Initialize ThermalValues of rf_calibrate_info */
+
+	if (!p_dm_odm->rf_calibrate_info.thermal_value) {
+		p_dm_odm->rf_calibrate_info.thermal_value_lck = thermal_value;
+		p_dm_odm->rf_calibrate_info.thermal_value_iqk = thermal_value;
+	}
+
+	if (p_dm_odm->rf_calibrate_info.is_reloadtxpowerindex)
+		ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("reload ofdm index for band switch\n"));
+
+	/* 4 4. Calculate average thermal meter */
+
+	p_dm_odm->rf_calibrate_info.thermal_value_avg[p_dm_odm->rf_calibrate_info.thermal_value_avg_index] = thermal_value;
+	p_dm_odm->rf_calibrate_info.thermal_value_avg_index++;
+	if (p_dm_odm->rf_calibrate_info.thermal_value_avg_index == c.average_thermal_num)
+		p_dm_odm->rf_calibrate_info.thermal_value_avg_index = 0;
+
+	for (i = 0; i < c.average_thermal_num; i++) {
+		if (p_dm_odm->rf_calibrate_info.thermal_value_avg[i]) {
+			thermal_value_avg += p_dm_odm->rf_calibrate_info.thermal_value_avg[i];
+			thermal_value_avg_count++;
+		}
+	}
+
+	if (thermal_value_avg_count) {
+		/* Give the new thermo value a weighting */
+		thermal_value_avg += (thermal_value * 4);
+
+		thermal_value = (u8)(thermal_value_avg / (thermal_value_avg_count + 4));
+		p_rf_calibrate_info->thermal_value_delta = thermal_value - priv->pmib->dot11RFEntry.ther;
+		ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("AVG Thermal Meter = 0x%x\n", thermal_value));
+	}
+
+	/* 4 5. Calculate delta, delta_LCK, delta_IQK. */
+
+	delta	  = (thermal_value > p_dm_odm->rf_calibrate_info.thermal_value) ? (thermal_value - p_dm_odm->rf_calibrate_info.thermal_value) : (p_dm_odm->rf_calibrate_info.thermal_value - thermal_value);
+	delta_LCK = (thermal_value > p_dm_odm->rf_calibrate_info.thermal_value_lck) ? (thermal_value - p_dm_odm->rf_calibrate_info.thermal_value_lck) : (p_dm_odm->rf_calibrate_info.thermal_value_lck - thermal_value);
+	delta_IQK = (thermal_value > p_dm_odm->rf_calibrate_info.thermal_value_iqk) ? (thermal_value - p_dm_odm->rf_calibrate_info.thermal_value_iqk) : (p_dm_odm->rf_calibrate_info.thermal_value_iqk - thermal_value);
+
+	/* 4 6. If necessary, do LCK. */
+	if (!(p_dm_odm->support_ic_type & ODM_RTL8821)) {
+		/*if((delta_LCK > p_hal_data->delta_lck) && (p_hal_data->delta_lck != 0))*/
+		if (delta_LCK >= c.threshold_iqk) {
+			/*Delta temperature is equal to or larger than 20 centigrade.*/
+			p_dm_odm->rf_calibrate_info.thermal_value_lck = thermal_value;
+			(*c.phy_lc_calibrate)(p_dm_odm);
+		}
+	}
+
+	/* 3 7. If necessary, move the index of swing table to adjust Tx power. */
+
+	if (delta > 0 && p_dm_odm->rf_calibrate_info.txpowertrack_control) {
+#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
+		delta = thermal_value > p_hal_data->eeprom_thermal_meter ? (thermal_value - p_hal_data->eeprom_thermal_meter) : (p_hal_data->eeprom_thermal_meter - thermal_value);
+#else
+		delta = (thermal_value > p_dm_odm->priv->pmib->dot11RFEntry.ther) ? (thermal_value - p_dm_odm->priv->pmib->dot11RFEntry.ther) : (p_dm_odm->priv->pmib->dot11RFEntry.ther - thermal_value);
+#endif
+
+
+		/* 4 7.1 The Final Power index = BaseIndex + power_index_offset */
+
+#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
+		if (thermal_value > p_hal_data->eeprom_thermal_meter) {
+#else
+		if (thermal_value > p_dm_odm->priv->pmib->dot11RFEntry.ther) {
+#endif
+			CALCULATE_SWINGTALBE_OFFSET(offset, POWER_INC, index_mapping_NUM_88E, delta);
+			p_dm_odm->rf_calibrate_info.delta_power_index_last = p_dm_odm->rf_calibrate_info.delta_power_index;
+			p_dm_odm->rf_calibrate_info.delta_power_index =  delta_swing_table_idx[POWER_INC][offset];
+
+		} else {
+
+			CALCULATE_SWINGTALBE_OFFSET(offset, POWER_DEC, index_mapping_NUM_88E, delta);
+			p_dm_odm->rf_calibrate_info.delta_power_index_last = p_dm_odm->rf_calibrate_info.delta_power_index;
+			p_dm_odm->rf_calibrate_info.delta_power_index = (-1) * delta_swing_table_idx[POWER_DEC][offset];
+		}
+
+		if (p_dm_odm->rf_calibrate_info.delta_power_index == p_dm_odm->rf_calibrate_info.delta_power_index_last)
+			p_dm_odm->rf_calibrate_info.power_index_offset = 0;
+		else
+			p_dm_odm->rf_calibrate_info.power_index_offset = p_dm_odm->rf_calibrate_info.delta_power_index - p_dm_odm->rf_calibrate_info.delta_power_index_last;
+
+		for (i = 0; i < rf; i++)
+			p_dm_odm->rf_calibrate_info.OFDM_index[i] = p_rf_calibrate_info->bb_swing_idx_ofdm_base + p_dm_odm->rf_calibrate_info.power_index_offset;
+		p_dm_odm->rf_calibrate_info.CCK_index = p_rf_calibrate_info->bb_swing_idx_cck_base + p_dm_odm->rf_calibrate_info.power_index_offset;
+
+		p_rf_calibrate_info->bb_swing_idx_cck = p_dm_odm->rf_calibrate_info.CCK_index;
+		p_rf_calibrate_info->bb_swing_idx_ofdm[RF_PATH_A] = p_dm_odm->rf_calibrate_info.OFDM_index[RF_PATH_A];
+
+		ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("The 'CCK' final index(%d) = BaseIndex(%d) + power_index_offset(%d)\n", p_rf_calibrate_info->bb_swing_idx_cck, p_rf_calibrate_info->bb_swing_idx_cck_base, p_dm_odm->rf_calibrate_info.power_index_offset));
+		ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("The 'OFDM' final index(%d) = BaseIndex(%d) + power_index_offset(%d)\n", p_rf_calibrate_info->bb_swing_idx_ofdm[RF_PATH_A], p_rf_calibrate_info->bb_swing_idx_ofdm_base, p_dm_odm->rf_calibrate_info.power_index_offset));
+
+		/* 4 7.1 Handle boundary conditions of index. */
+
+
+		for (i = 0; i < rf; i++) {
+			if (p_dm_odm->rf_calibrate_info.OFDM_index[i] > OFDM_max_index)
+				p_dm_odm->rf_calibrate_info.OFDM_index[i] = OFDM_max_index;
+			else if (p_dm_odm->rf_calibrate_info.OFDM_index[i] < 0)
+				p_dm_odm->rf_calibrate_info.OFDM_index[i] = 0;
+		}
+
+		if (p_dm_odm->rf_calibrate_info.CCK_index > c.swing_table_size_cck - 1)
+			p_dm_odm->rf_calibrate_info.CCK_index = c.swing_table_size_cck - 1;
+		else if (p_dm_odm->rf_calibrate_info.CCK_index < 0)
+			p_dm_odm->rf_calibrate_info.CCK_index = 0;
+	} else {
+		ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
+			("The thermal meter is unchanged or TxPowerTracking OFF: thermal_value: %d, p_dm_odm->rf_calibrate_info.thermal_value: %d)\n", thermal_value, p_dm_odm->rf_calibrate_info.thermal_value));
+		p_dm_odm->rf_calibrate_info.power_index_offset = 0;
+	}
+	ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
+		("TxPowerTracking: [CCK] Swing Current index: %d, Swing base index: %d\n", p_dm_odm->rf_calibrate_info.CCK_index, p_rf_calibrate_info->bb_swing_idx_cck_base));
+
+	ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
+		("TxPowerTracking: [OFDM] Swing Current index: %d, Swing base index: %d\n", p_dm_odm->rf_calibrate_info.OFDM_index[RF_PATH_A], p_rf_calibrate_info->bb_swing_idx_ofdm_base));
+
+	if (p_dm_odm->rf_calibrate_info.power_index_offset != 0 && p_dm_odm->rf_calibrate_info.txpowertrack_control) {
+		/* 4 7.2 Configure the Swing Table to adjust Tx Power. */
+
+		p_dm_odm->rf_calibrate_info.is_tx_power_changed = true; /* Always true after Tx Power is adjusted by power tracking. */
+		/*  */
+		/* 2012/04/23 MH According to Luke's suggestion, we can not write BB digital */
+		/* to increase TX power. Otherwise, EVM will be bad. */
+		/*  */
+		/* 2012/04/25 MH Add for tx power tracking to set tx power in tx agc for 88E. */
+		if (thermal_value > p_dm_odm->rf_calibrate_info.thermal_value) {
+			/* ODM_RT_TRACE(p_dm_odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, */
+			/*	("Temperature Increasing: delta_pi: %d, delta_t: %d, Now_t: %d, EFUSE_t: %d, Last_t: %d\n", */
+			/*	p_dm_odm->rf_calibrate_info.power_index_offset, delta, thermal_value, p_hal_data->eeprom_thermal_meter, p_dm_odm->rf_calibrate_info.thermal_value)); */
+		} else if (thermal_value < p_dm_odm->rf_calibrate_info.thermal_value) { /* Low temperature */
+			/* ODM_RT_TRACE(p_dm_odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, */
+			/*	("Temperature Decreasing: delta_pi: %d, delta_t: %d, Now_t: %d, EFUSE_t: %d, Last_t: %d\n", */
+			/*		p_dm_odm->rf_calibrate_info.power_index_offset, delta, thermal_value, p_hal_data->eeprom_thermal_meter, p_dm_odm->rf_calibrate_info.thermal_value)); */
+		}
+#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
+		if (thermal_value > p_hal_data->eeprom_thermal_meter)
+#else
+		if (thermal_value > p_dm_odm->priv->pmib->dot11RFEntry.ther)
+#endif
+		{
+			/*				ODM_RT_TRACE(p_dm_odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("Temperature(%d) hugher than PG value(%d), increases the power by tx_agc\n", thermal_value, p_hal_data->eeprom_thermal_meter)); */
+			(*c.odm_tx_pwr_track_set_pwr)(p_dm_odm, TXAGC, 0, 0);
+		} else {
+			/*			ODM_RT_TRACE(p_dm_odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("Temperature(%d) lower than PG value(%d), increases the power by tx_agc\n", thermal_value, p_hal_data->eeprom_thermal_meter)); */
+			(*c.odm_tx_pwr_track_set_pwr)(p_dm_odm, BBSWING, RF_PATH_A, indexforchannel);
+			if (is2T)
+				(*c.odm_tx_pwr_track_set_pwr)(p_dm_odm, BBSWING, RF_PATH_B, indexforchannel);
+		}
+
+		p_rf_calibrate_info->bb_swing_idx_cck_base = p_rf_calibrate_info->bb_swing_idx_cck;
+		p_rf_calibrate_info->bb_swing_idx_ofdm_base = p_rf_calibrate_info->bb_swing_idx_ofdm[RF_PATH_A];
+		p_dm_odm->rf_calibrate_info.thermal_value = thermal_value;
+
+	}
+
+#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
+	/* if((delta_IQK > p_hal_data->delta_iqk) && (p_hal_data->delta_iqk != 0)) */
+	if ((delta_IQK >= 8)) /* Delta temperature is equal to or larger than 20 centigrade. */
+		(*c.do_iqk)(p_dm_odm, delta_IQK, thermal_value, 8);
+#endif
+
+	ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("<===dm_TXPowerTrackingCallback_ThermalMeter_8188E\n"));
+
+	p_dm_odm->rf_calibrate_info.tx_powercount = 0;
+}
+
+#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
+
+
+void
+phy_path_a_stand_by(
+	struct _ADAPTER	*p_adapter
+)
+{
+	RTPRINT(FINIT, INIT_IQK, ("path-A standby mode!\n"));
+
+	phy_set_bb_reg(p_adapter, REG_FPGA0_IQK, 0xffffff00, 0x0);
+	phy_set_bb_reg(p_adapter, 0x840, MASKDWORD, 0x00010000);
+	phy_set_bb_reg(p_adapter, REG_FPGA0_IQK, 0xffffff00, 0x808000);
+}
+
+/* 1 7.	IQK
+ * #define MAX_TOLERANCE		5
+ * #define IQK_DELAY_TIME		1 */		/* ms */
+
+u8			/* bit0 = 1 => Tx OK, bit1 = 1 => Rx OK */
+phy_path_a_iqk_8192c(
+	struct _ADAPTER	*p_adapter,
+	boolean		config_path_b
+)
+{
+
+	u32 reg_eac, reg_e94, reg_e9c, reg_ea4;
+	u8 result = 0x00;
+	HAL_DATA_TYPE	*p_hal_data = GET_HAL_DATA(p_adapter);
+
+	RTPRINT(FINIT, INIT_IQK, ("path A IQK!\n"));
+
+	/* path-A IQK setting */
+	RTPRINT(FINIT, INIT_IQK, ("path-A IQK setting!\n"));
+	if (p_adapter->interface_index == 0) {
+		phy_set_bb_reg(p_adapter, REG_TX_IQK_TONE_A, MASKDWORD, 0x10008c1f);
+		phy_set_bb_reg(p_adapter, REG_RX_IQK_TONE_A, MASKDWORD, 0x10008c1f);
+	} else {
+		phy_set_bb_reg(p_adapter, REG_TX_IQK_TONE_A, MASKDWORD, 0x10008c22);
+		phy_set_bb_reg(p_adapter, REG_RX_IQK_TONE_A, MASKDWORD, 0x10008c22);
+	}
+
+	phy_set_bb_reg(p_adapter, REG_TX_IQK_PI_A, MASKDWORD, 0x82140102);
+
+	phy_set_bb_reg(p_adapter, REG_RX_IQK_PI_A, MASKDWORD, config_path_b ? 0x28160202 :
+		IS_81xxC_VENDOR_UMC_B_CUT(p_hal_data->version_id) ? 0x28160202 : 0x28160502);
+
+	/* path-B IQK setting */
+	if (config_path_b) {
+		phy_set_bb_reg(p_adapter, REG_TX_IQK_TONE_B, MASKDWORD, 0x10008c22);
+		phy_set_bb_reg(p_adapter, REG_RX_IQK_TONE_B, MASKDWORD, 0x10008c22);
+		phy_set_bb_reg(p_adapter, REG_TX_IQK_PI_B, MASKDWORD, 0x82140102);
+		phy_set_bb_reg(p_adapter, REG_RX_IQK_PI_B, MASKDWORD, 0x28160202);
+	}
+
+	/* LO calibration setting */
+	RTPRINT(FINIT, INIT_IQK, ("LO calibration setting!\n"));
+	phy_set_bb_reg(p_adapter, REG_IQK_AGC_RSP, MASKDWORD, 0x001028d1);
+
+	/* One shot, path A LOK & IQK */
+	RTPRINT(FINIT, INIT_IQK, ("One shot, path A LOK & IQK!\n"));
+	phy_set_bb_reg(p_adapter, REG_IQK_AGC_PTS, MASKDWORD, 0xf9000000);
+	phy_set_bb_reg(p_adapter, REG_IQK_AGC_PTS, MASKDWORD, 0xf8000000);
+
+	/* delay x ms */
+	RTPRINT(FINIT, INIT_IQK, ("delay %d ms for One shot, path A LOK & IQK.\n", IQK_DELAY_TIME));
+	platform_stall_execution(IQK_DELAY_TIME * 1000);
+
+	/* Check failed */
+	reg_eac = phy_query_bb_reg(p_adapter, REG_RX_POWER_AFTER_IQK_A_2, MASKDWORD);
+	RTPRINT(FINIT, INIT_IQK, ("0xeac = 0x%x\n", reg_eac));
+	reg_e94 = phy_query_bb_reg(p_adapter, REG_TX_POWER_BEFORE_IQK_A, MASKDWORD);
+	RTPRINT(FINIT, INIT_IQK, ("0xe94 = 0x%x\n", reg_e94));
+	reg_e9c = phy_query_bb_reg(p_adapter, REG_TX_POWER_AFTER_IQK_A, MASKDWORD);
+	RTPRINT(FINIT, INIT_IQK, ("0xe9c = 0x%x\n", reg_e9c));
+	reg_ea4 = phy_query_bb_reg(p_adapter, REG_RX_POWER_BEFORE_IQK_A_2, MASKDWORD);
+	RTPRINT(FINIT, INIT_IQK, ("0xea4 = 0x%x\n", reg_ea4));
+
+	if (!(reg_eac & BIT(28)) &&
+	    (((reg_e94 & 0x03FF0000) >> 16) != 0x142) &&
+	    (((reg_e9c & 0x03FF0000) >> 16) != 0x42))
+		result |= 0x01;
+	else							/* if Tx not OK, ignore Rx */
+		return result;
+
+	if (!(reg_eac & BIT(27)) &&		/* if Tx is OK, check whether Rx is OK */
+	    (((reg_ea4 & 0x03FF0000) >> 16) != 0x132) &&
+	    (((reg_eac & 0x03FF0000) >> 16) != 0x36))
+		result |= 0x02;
+	else
+		RTPRINT(FINIT, INIT_IQK, ("path A Rx IQK fail!!\n"));
+
+	return result;
+
+
+}
+
+u8				/* bit0 = 1 => Tx OK, bit1 = 1 => Rx OK */
+phy_path_b_iqk_8192c(
+	struct _ADAPTER	*p_adapter
+)
+{
+	u32 reg_eac, reg_eb4, reg_ebc, reg_ec4, reg_ecc;
+	u8	result = 0x00;
+	RTPRINT(FINIT, INIT_IQK, ("path B IQK!\n"));
+
+	/* One shot, path B LOK & IQK */
+	RTPRINT(FINIT, INIT_IQK, ("One shot, path A LOK & IQK!\n"));
+	phy_set_bb_reg(p_adapter, REG_IQK_AGC_CONT, MASKDWORD, 0x00000002);
+	phy_set_bb_reg(p_adapter, REG_IQK_AGC_CONT, MASKDWORD, 0x00000000);
+
+	/* delay x ms */
+	RTPRINT(FINIT, INIT_IQK, ("delay %d ms for One shot, path B LOK & IQK.\n", IQK_DELAY_TIME));
+	platform_stall_execution(IQK_DELAY_TIME * 1000);
+
+	/* Check failed */
+	reg_eac = phy_query_bb_reg(p_adapter, REG_RX_POWER_AFTER_IQK_A_2, MASKDWORD);
+	RTPRINT(FINIT, INIT_IQK, ("0xeac = 0x%x\n", reg_eac));
+	reg_eb4 = phy_query_bb_reg(p_adapter, REG_TX_POWER_BEFORE_IQK_B, MASKDWORD);
+	RTPRINT(FINIT, INIT_IQK, ("0xeb4 = 0x%x\n", reg_eb4));
+	reg_ebc = phy_query_bb_reg(p_adapter, REG_TX_POWER_AFTER_IQK_B, MASKDWORD);
+	RTPRINT(FINIT, INIT_IQK, ("0xebc = 0x%x\n", reg_ebc));
+	reg_ec4 = phy_query_bb_reg(p_adapter, REG_RX_POWER_BEFORE_IQK_B_2, MASKDWORD);
+	RTPRINT(FINIT, INIT_IQK, ("0xec4 = 0x%x\n", reg_ec4));
+	reg_ecc = phy_query_bb_reg(p_adapter, REG_RX_POWER_AFTER_IQK_B_2, MASKDWORD);
+	RTPRINT(FINIT, INIT_IQK, ("0xecc = 0x%x\n", reg_ecc));
+
+	if (!(reg_eac & BIT(31)) &&
+	    (((reg_eb4 & 0x03FF0000) >> 16) != 0x142) &&
+	    (((reg_ebc & 0x03FF0000) >> 16) != 0x42))
+		result |= 0x01;
+	else
+		return result;
+
+	if (!(reg_eac & BIT(30)) &&
+	    (((reg_ec4 & 0x03FF0000) >> 16) != 0x132) &&
+	    (((reg_ecc & 0x03FF0000) >> 16) != 0x36))
+		result |= 0x02;
+	else
+		RTPRINT(FINIT, INIT_IQK, ("path B Rx IQK fail!!\n"));
+
+
+	return result;
+
+}
+
+void
+phy_path_a_fill_iqk_matrix(
+	struct _ADAPTER	*p_adapter,
+	boolean	is_iqk_ok,
+	s32		result[][8],
+	u8		final_candidate,
+	boolean		is_tx_only
+)
+{
+	u32	oldval_0, X, TX0_A, reg;
+	s32	Y, TX0_C;
+	HAL_DATA_TYPE	*p_hal_data = GET_HAL_DATA(p_adapter);
+
+	RTPRINT(FINIT, INIT_IQK, ("path A IQ Calibration %s !\n", (is_iqk_ok) ? "Success" : "Failed"));
+
+	if (final_candidate == 0xFF)
+		return;
+
+	else if (is_iqk_ok) {
+		oldval_0 = (phy_query_bb_reg(p_adapter, REG_OFDM_0_XA_TX_IQ_IMBALANCE, MASKDWORD) >> 22) & 0x3FF;
+
+		X = result[final_candidate][0];
+		if ((X & 0x00000200) != 0)
+			X = X | 0xFFFFFC00;
+		TX0_A = (X * oldval_0) >> 8;
+		RTPRINT(FINIT, INIT_IQK, ("X = 0x%x, TX0_A = 0x%x, oldval_0 0x%x\n", X, TX0_A, oldval_0));
+		phy_set_bb_reg(p_adapter, REG_OFDM_0_XA_TX_IQ_IMBALANCE, 0x3FF, TX0_A);
+		phy_set_bb_reg(p_adapter, REG_OFDM_0_ECCA_THRESHOLD, BIT(31), ((X * oldval_0 >> 7) & 0x1));
+
+		Y = result[final_candidate][1];
+		if ((Y & 0x00000200) != 0)
+			Y = Y | 0xFFFFFC00;
+
+		/* path B IQK result + 3 */
+		if (p_adapter->interface_index == 1 && p_hal_data->current_band_type == BAND_ON_5G)
+			Y += 3;
+
+		TX0_C = (Y * oldval_0) >> 8;
+		RTPRINT(FINIT, INIT_IQK, ("Y = 0x%x, TX = 0x%x\n", Y, TX0_C));
+		phy_set_bb_reg(p_adapter, REG_OFDM_0_XC_TX_AFE, 0xF0000000, ((TX0_C & 0x3C0) >> 6));
+		phy_set_bb_reg(p_adapter, REG_OFDM_0_XA_TX_IQ_IMBALANCE, 0x003F0000, (TX0_C & 0x3F));
+		phy_set_bb_reg(p_adapter, REG_OFDM_0_ECCA_THRESHOLD, BIT(29), ((Y * oldval_0 >> 7) & 0x1));
+
+		if (is_tx_only) {
+			RTPRINT(FINIT, INIT_IQK, ("phy_path_a_fill_iqk_matrix only Tx OK\n"));
+			return;
+		}
+
+		reg = result[final_candidate][2];
+		phy_set_bb_reg(p_adapter, REG_OFDM_0_XA_RX_IQ_IMBALANCE, 0x3FF, reg);
+
+		reg = result[final_candidate][3] & 0x3F;
+		phy_set_bb_reg(p_adapter, REG_OFDM_0_XA_RX_IQ_IMBALANCE, 0xFC00, reg);
+
+		reg = (result[final_candidate][3] >> 6) & 0xF;
+		phy_set_bb_reg(p_adapter, REG_OFDM_0_RX_IQ_EXT_ANTA, 0xF0000000, reg);
+	}
+}
+
+void
+phy_path_b_fill_iqk_matrix(
+	struct _ADAPTER	*p_adapter,
+	boolean	is_iqk_ok,
+	s32		result[][8],
+	u8		final_candidate,
+	boolean		is_tx_only			/* do Tx only */
+)
+{
+	u32	oldval_1, X, TX1_A, reg;
+	s32	Y, TX1_C;
+	HAL_DATA_TYPE	*p_hal_data = GET_HAL_DATA(p_adapter);
+
+	RTPRINT(FINIT, INIT_IQK, ("path B IQ Calibration %s !\n", (is_iqk_ok) ? "Success" : "Failed"));
+
+	if (final_candidate == 0xFF)
+		return;
+
+	else if (is_iqk_ok) {
+		oldval_1 = (phy_query_bb_reg(p_adapter, REG_OFDM_0_XB_TX_IQ_IMBALANCE, MASKDWORD) >> 22) & 0x3FF;
+
+		X = result[final_candidate][4];
+		if ((X & 0x00000200) != 0)
+			X = X | 0xFFFFFC00;
+		TX1_A = (X * oldval_1) >> 8;
+		RTPRINT(FINIT, INIT_IQK, ("X = 0x%x, TX1_A = 0x%x\n", X, TX1_A));
+		phy_set_bb_reg(p_adapter, REG_OFDM_0_XB_TX_IQ_IMBALANCE, 0x3FF, TX1_A);
+		phy_set_bb_reg(p_adapter, REG_OFDM_0_ECCA_THRESHOLD, BIT(27), ((X * oldval_1 >> 7) & 0x1));
+
+		Y = result[final_candidate][5];
+		if ((Y & 0x00000200) != 0)
+			Y = Y | 0xFFFFFC00;
+		if (p_hal_data->current_band_type == BAND_ON_5G)
+			Y += 3;		/* temp modify for preformance */
+		TX1_C = (Y * oldval_1) >> 8;
+		RTPRINT(FINIT, INIT_IQK, ("Y = 0x%x, TX1_C = 0x%x\n", Y, TX1_C));
+		phy_set_bb_reg(p_adapter, REG_OFDM_0_XD_TX_AFE, 0xF0000000, ((TX1_C & 0x3C0) >> 6));
+		phy_set_bb_reg(p_adapter, REG_OFDM_0_XB_TX_IQ_IMBALANCE, 0x003F0000, (TX1_C & 0x3F));
+		phy_set_bb_reg(p_adapter, REG_OFDM_0_ECCA_THRESHOLD, BIT(25), ((Y * oldval_1 >> 7) & 0x1));
+
+		if (is_tx_only)
+			return;
+
+		reg = result[final_candidate][6];
+		phy_set_bb_reg(p_adapter, REG_OFDM_0_XB_RX_IQ_IMBALANCE, 0x3FF, reg);
+
+		reg = result[final_candidate][7] & 0x3F;
+		phy_set_bb_reg(p_adapter, REG_OFDM_0_XB_RX_IQ_IMBALANCE, 0xFC00, reg);
+
+		reg = (result[final_candidate][7] >> 6) & 0xF;
+		phy_set_bb_reg(p_adapter, REG_OFDM_0_AGC_RSSI_TABLE, 0x0000F000, reg);
+	}
+}
+
+
+boolean
+phy_simularity_compare_92c(
+	struct _ADAPTER	*p_adapter,
+	s32		result[][8],
+	u8		 c1,
+	u8		 c2
+)
+{
+	u32		i, j, diff, simularity_bit_map, bound = 0;
+	HAL_DATA_TYPE	*p_hal_data = GET_HAL_DATA(p_adapter);
+	u8		final_candidate[2] = {0xFF, 0xFF};	/* for path A and path B */
+	boolean		is_result = true, is2T = IS_92C_SERIAL(p_hal_data->version_id);
+
+	if (is2T)
+		bound = 8;
+	else
+		bound = 4;
+
+	simularity_bit_map = 0;
+
+	for (i = 0; i < bound; i++) {
+		diff = (result[c1][i] > result[c2][i]) ? (result[c1][i] - result[c2][i]) : (result[c2][i] - result[c1][i]);
+		if (diff > MAX_TOLERANCE) {
+			if ((i == 2 || i == 6) && !simularity_bit_map) {
+				if (result[c1][i] + result[c1][i + 1] == 0)
+					final_candidate[(i / 4)] = c2;
+				else if (result[c2][i] + result[c2][i + 1] == 0)
+					final_candidate[(i / 4)] = c1;
+				else
+					simularity_bit_map = simularity_bit_map | (1 << i);
+			} else
+				simularity_bit_map = simularity_bit_map | (1 << i);
+		}
+	}
+
+	if (simularity_bit_map == 0) {
+		for (i = 0; i < (bound / 4); i++) {
+			if (final_candidate[i] != 0xFF) {
+				for (j = i * 4; j < (i + 1) * 4 - 2; j++)
+					result[3][j] = result[final_candidate[i]][j];
+				is_result = false;
+			}
+		}
+		return is_result;
+	} else if (!(simularity_bit_map & 0x0F)) {		/* path A OK */
+		for (i = 0; i < 4; i++)
+			result[3][i] = result[c1][i];
+		return false;
+	} else if (!(simularity_bit_map & 0xF0) && is2T) {	/* path B OK */
+		for (i = 4; i < 8; i++)
+			result[3][i] = result[c1][i];
+		return false;
+	} else
+		return false;
+
+}
+
+/*
+return false => do IQK again
+*/
+boolean
+phy_simularity_compare(
+	struct _ADAPTER	*p_adapter,
+	s32		result[][8],
+	u8		 c1,
+	u8		 c2
+)
+{
+	return phy_simularity_compare_92c(p_adapter, result, c1, c2);
+
+}
+
+void
+_phy_iq_calibrate_8192c(
+	struct _ADAPTER	*p_adapter,
+	s32		result[][8],
+	u8		t,
+	boolean		is2T
+)
+{
+	HAL_DATA_TYPE	*p_hal_data = GET_HAL_DATA(p_adapter);
+	u32			i;
+	u8			path_aok, path_bok;
+	u32			ADDA_REG[IQK_ADDA_REG_NUM] = {
+		REG_FPGA0_XCD_SWITCH_CONTROL,	REG_BLUE_TOOTH,
+		REG_RX_WAIT_CCA,		REG_TX_CCK_RFON,
+		REG_TX_CCK_BBON,	REG_TX_OFDM_RFON,
+		REG_TX_OFDM_BBON,	REG_TX_TO_RX,
+		REG_TX_TO_TX,		REG_RX_CCK,
+		REG_RX_OFDM,		REG_RX_WAIT_RIFS,
+		REG_RX_TO_RX,		REG_STANDBY,
+		REG_SLEEP,			REG_PMPD_ANAEN
+	};
+	u32			IQK_MAC_REG[IQK_MAC_REG_NUM] = {
+		REG_TXPAUSE,		REG_BCN_CTRL,
+		REG_BCN_CTRL_1,	REG_GPIO_MUXCFG
+	};
+
+	/* since 92C & 92D have the different define in IQK_BB_REG */
+	u32	IQK_BB_REG_92C[IQK_BB_REG_NUM] = {
+		REG_OFDM_0_TRX_PATH_ENABLE,		REG_OFDM_0_TR_MUX_PAR,
+		REG_FPGA0_XCD_RF_INTERFACE_SW,	REG_CONFIG_ANT_A,	REG_CONFIG_ANT_B,
+		REG_FPGA0_XAB_RF_INTERFACE_SW,	REG_FPGA0_XA_RF_INTERFACE_OE,
+		REG_FPGA0_XB_RF_INTERFACE_OE,	/*REG_FPGA0_RFMOD*/ REG_CCK_0_AFE_SETTING
+	};
+
+	u32	IQK_BB_REG_92D[IQK_BB_REG_NUM_92D] = {	/* for normal */
+		REG_FPGA0_XAB_RF_INTERFACE_SW,	REG_FPGA0_XA_RF_INTERFACE_OE,
+		REG_FPGA0_XB_RF_INTERFACE_OE,	REG_OFDM_0_TR_MUX_PAR,
+		REG_FPGA0_XCD_RF_INTERFACE_SW,	REG_OFDM_0_TRX_PATH_ENABLE,
+		/*REG_FPGA0_RFMOD*/ REG_CCK_0_AFE_SETTING,			REG_FPGA0_ANALOG_PARAMETER4,
+		REG_OFDM_0_XA_AGC_CORE1,		REG_OFDM_0_XB_AGC_CORE1
+	};
+#if MP_DRIVER
+	const u32	retry_count = 9;
+#else
+	const u32	retry_count = 2;
+#endif
+	/* Neil Chen--2011--05--19--
+	* 3 path Div */
+	u8                 rf_path_switch = 0x0;
+
+	/* Note: IQ calibration must be performed after loading */
+	/*		PHY_REG.txt , and radio_a, radio_b.txt */
+
+	u32 bbvalue;
+
+	if (t == 0) {
+		/* bbvalue = phy_query_bb_reg(p_adapter, REG_FPGA0_RFMOD, MASKDWORD); */
+		/*	RTPRINT(FINIT, INIT_IQK, ("_phy_iq_calibrate_8192c()==>0x%08x\n",bbvalue)); */
+
+		RTPRINT(FINIT, INIT_IQK, ("IQ Calibration for %s\n", (is2T ? "2T2R" : "1T1R")));
+
+		/* Save ADDA parameters, turn path A ADDA on */
+		phy_save_adda_registers(p_adapter, ADDA_REG, p_hal_data->ADDA_backup, IQK_ADDA_REG_NUM);
+		phy_save_mac_registers(p_adapter, IQK_MAC_REG, p_hal_data->IQK_MAC_backup);
+		phy_save_adda_registers(p_adapter, IQK_BB_REG_92C, p_hal_data->IQK_BB_backup, IQK_BB_REG_NUM);
+	}
+
+	phy_path_adda_on(p_adapter, ADDA_REG, true, is2T);
+
+	if (t == 0)
+		p_hal_data->is_rf_pi_enable = (u8)phy_query_bb_reg(p_adapter, REG_FPGA0_XA_HSSI_PARAMETER1, BIT(8));
+
+	if (!p_hal_data->is_rf_pi_enable) {
+		/* Switch BB to PI mode to do IQ Calibration. */
+		phy_pi_mode_switch(p_adapter, true);
+	}
+
+	/* MAC settings */
+	phy_mac_setting_calibration(p_adapter, IQK_MAC_REG, p_hal_data->IQK_MAC_backup);
+
+	/* phy_set_bb_reg(p_adapter, REG_FPGA0_RFMOD, BIT24, 0x00); */
+	phy_set_bb_reg(p_adapter, REG_CCK_0_AFE_SETTING, MASKDWORD, (0x0f000000 | (phy_query_bb_reg(p_adapter, REG_CCK_0_AFE_SETTING, MASKDWORD))));
+	phy_set_bb_reg(p_adapter, REG_OFDM_0_TRX_PATH_ENABLE, MASKDWORD, 0x03a05600);
+	phy_set_bb_reg(p_adapter, REG_OFDM_0_TR_MUX_PAR, MASKDWORD, 0x000800e4);
+	phy_set_bb_reg(p_adapter, REG_FPGA0_XCD_RF_INTERFACE_SW, MASKDWORD, 0x22204000);
+	{
+		phy_set_bb_reg(p_adapter, REG_FPGA0_XAB_RF_INTERFACE_SW, BIT(10), 0x01);
+		phy_set_bb_reg(p_adapter, REG_FPGA0_XAB_RF_INTERFACE_SW, BIT(26), 0x01);
+		phy_set_bb_reg(p_adapter, REG_FPGA0_XA_RF_INTERFACE_OE, BIT(10), 0x00);
+		phy_set_bb_reg(p_adapter, REG_FPGA0_XB_RF_INTERFACE_OE, BIT(10), 0x00);
+	}
+
+	if (is2T) {
+		phy_set_bb_reg(p_adapter, REG_FPGA0_XA_LSSI_PARAMETER, MASKDWORD, 0x00010000);
+		phy_set_bb_reg(p_adapter, REG_FPGA0_XB_LSSI_PARAMETER, MASKDWORD, 0x00010000);
+	}
+
+	{
+		/* Page B init */
+		phy_set_bb_reg(p_adapter, REG_CONFIG_ANT_A, MASKDWORD, 0x00080000);
+
+		if (is2T)
+			phy_set_bb_reg(p_adapter, REG_CONFIG_ANT_B, MASKDWORD, 0x00080000);
+	}
+	/* IQ calibration setting */
+	RTPRINT(FINIT, INIT_IQK, ("IQK setting!\n"));
+	phy_set_bb_reg(p_adapter, REG_FPGA0_IQK, 0xffffff00, 0x808000);
+	phy_set_bb_reg(p_adapter, REG_TX_IQK, MASKDWORD, 0x01007c00);
+	phy_set_bb_reg(p_adapter, REG_RX_IQK, MASKDWORD, 0x01004800);
+
+	for (i = 0 ; i < retry_count ; i++) {
+		path_aok = phy_path_a_iqk_8192c(p_adapter, is2T);
+		if (path_aok == 0x03) {
+			RTPRINT(FINIT, INIT_IQK, ("path A IQK Success!!\n"));
+			result[t][0] = (phy_query_bb_reg(p_adapter, REG_TX_POWER_BEFORE_IQK_A, MASKDWORD) & 0x3FF0000) >> 16;
+			result[t][1] = (phy_query_bb_reg(p_adapter, REG_TX_POWER_AFTER_IQK_A, MASKDWORD) & 0x3FF0000) >> 16;
+			result[t][2] = (phy_query_bb_reg(p_adapter, REG_RX_POWER_BEFORE_IQK_A_2, MASKDWORD) & 0x3FF0000) >> 16;
+			result[t][3] = (phy_query_bb_reg(p_adapter, REG_RX_POWER_AFTER_IQK_A_2, MASKDWORD) & 0x3FF0000) >> 16;
+			break;
+		} else if (i == (retry_count - 1) && path_aok == 0x01) {	/* Tx IQK OK */
+			RTPRINT(FINIT, INIT_IQK, ("path A IQK Only  Tx Success!!\n"));
+
+			result[t][0] = (phy_query_bb_reg(p_adapter, REG_TX_POWER_BEFORE_IQK_A, MASKDWORD) & 0x3FF0000) >> 16;
+			result[t][1] = (phy_query_bb_reg(p_adapter, REG_TX_POWER_AFTER_IQK_A, MASKDWORD) & 0x3FF0000) >> 16;
+		}
+	}
+
+	if (0x00 == path_aok)
+		RTPRINT(FINIT, INIT_IQK, ("path A IQK failed!!\n"));
+
+	if (is2T) {
+		phy_path_a_stand_by(p_adapter);
+
+		/* Turn path B ADDA on */
+		phy_path_adda_on(p_adapter, ADDA_REG, false, is2T);
+
+		for (i = 0 ; i < retry_count ; i++) {
+			path_bok = phy_path_b_iqk_8192c(p_adapter);
+			if (path_bok == 0x03) {
+				RTPRINT(FINIT, INIT_IQK, ("path B IQK Success!!\n"));
+				result[t][4] = (phy_query_bb_reg(p_adapter, REG_TX_POWER_BEFORE_IQK_B, MASKDWORD) & 0x3FF0000) >> 16;
+				result[t][5] = (phy_query_bb_reg(p_adapter, REG_TX_POWER_AFTER_IQK_B, MASKDWORD) & 0x3FF0000) >> 16;
+				result[t][6] = (phy_query_bb_reg(p_adapter, REG_RX_POWER_BEFORE_IQK_B_2, MASKDWORD) & 0x3FF0000) >> 16;
+				result[t][7] = (phy_query_bb_reg(p_adapter, REG_RX_POWER_AFTER_IQK_B_2, MASKDWORD) & 0x3FF0000) >> 16;
+				break;
+			} else if (i == (retry_count - 1) && path_bok == 0x01) {	/* Tx IQK OK */
+				RTPRINT(FINIT, INIT_IQK, ("path B Only Tx IQK Success!!\n"));
+				result[t][4] = (phy_query_bb_reg(p_adapter, REG_TX_POWER_BEFORE_IQK_B, MASKDWORD) & 0x3FF0000) >> 16;
+				result[t][5] = (phy_query_bb_reg(p_adapter, REG_TX_POWER_AFTER_IQK_B, MASKDWORD) & 0x3FF0000) >> 16;
+			}
+		}
+
+		if (0x00 == path_bok)
+			RTPRINT(FINIT, INIT_IQK, ("path B IQK failed!!\n"));
+	}
+
+	/* Back to BB mode, load original value */
+	RTPRINT(FINIT, INIT_IQK, ("IQK:Back to BB mode, load original value!\n"));
+	phy_set_bb_reg(p_adapter, REG_FPGA0_IQK, 0xffffff00, 0);
+
+	if (t != 0) {
+		if (!p_hal_data->is_rf_pi_enable) {
+			/* Switch back BB to SI mode after finish IQ Calibration. */
+			phy_pi_mode_switch(p_adapter, false);
+		}
+
+		/* Reload ADDA power saving parameters */
+		phy_reload_adda_registers(p_adapter, ADDA_REG, p_hal_data->ADDA_backup, IQK_ADDA_REG_NUM);
+
+		/* Reload MAC parameters */
+		phy_reload_mac_registers(p_adapter, IQK_MAC_REG, p_hal_data->IQK_MAC_backup);
+
+		/* Reload BB parameters */
+		phy_reload_adda_registers(p_adapter, IQK_BB_REG_92C, p_hal_data->IQK_BB_backup, IQK_BB_REG_NUM);
+
+		/*Restore RX initial gain*/
+		phy_set_bb_reg(p_adapter, REG_FPGA0_XA_LSSI_PARAMETER, MASKDWORD, 0x00032ed3);
+		if (is2T)
+			phy_set_bb_reg(p_adapter, REG_FPGA0_XB_LSSI_PARAMETER, MASKDWORD, 0x00032ed3);
+		/* load 0xe30 IQC default value */
+		phy_set_bb_reg(p_adapter, REG_TX_IQK_TONE_A, MASKDWORD, 0x01008c00);
+		phy_set_bb_reg(p_adapter, REG_RX_IQK_TONE_A, MASKDWORD, 0x01008c00);
+
+	}
+	RTPRINT(FINIT, INIT_IQK, ("_phy_iq_calibrate_8192c() <==\n"));
+
+}
+
+
+void
+_phy_lccalibrate92c(
+	struct _ADAPTER	*p_adapter,
+	boolean		is2T
+)
+{
+	u8	tmp_reg;
+	u32	rf_amode = 0, rf_bmode = 0, lc_cal;
+	/*	HAL_DATA_TYPE	*p_hal_data = GET_HAL_DATA(p_adapter); */
+
+	/* Check continuous TX and Packet TX */
+	tmp_reg = platform_efio_read_1byte(p_adapter, 0xd03);
+
+	if ((tmp_reg & 0x70) != 0)			/* Deal with contisuous TX case */
+		platform_efio_write_1byte(p_adapter, 0xd03, tmp_reg & 0x8F);	/* disable all continuous TX */
+	else							/* Deal with Packet TX case */
+		platform_efio_write_1byte(p_adapter, REG_TXPAUSE, 0xFF);			/* block all queues */
+
+	if ((tmp_reg & 0x70) != 0) {
+		/* 1. Read original RF mode */
+		/* path-A */
+		rf_amode = phy_query_rf_reg(p_adapter, RF_PATH_A, RF_AC, MASK12BITS);
+
+		/* path-B */
+		if (is2T)
+			rf_bmode = phy_query_rf_reg(p_adapter, RF_PATH_B, RF_AC, MASK12BITS);
+
+		/* 2. Set RF mode = standby mode */
+		/* path-A */
+		phy_set_rf_reg(p_adapter, RF_PATH_A, RF_AC, MASK12BITS, (rf_amode & 0x8FFFF) | 0x10000);
+
+		/* path-B */
+		if (is2T)
+			phy_set_rf_reg(p_adapter, RF_PATH_B, RF_AC, MASK12BITS, (rf_bmode & 0x8FFFF) | 0x10000);
+	}
+
+	/* 3. Read RF reg18 */
+	lc_cal = phy_query_rf_reg(p_adapter, RF_PATH_A, RF_CHNLBW, MASK12BITS);
+
+	/* 4. Set LC calibration begin	bit15 */
+	phy_set_rf_reg(p_adapter, RF_PATH_A, RF_CHNLBW, MASK12BITS, lc_cal | 0x08000);
+
+	delay_ms(100);
+
+
+	/* Restore original situation */
+	if ((tmp_reg & 0x70) != 0) {	/* Deal with contisuous TX case */
+		/* path-A */
+		platform_efio_write_1byte(p_adapter, 0xd03, tmp_reg);
+		phy_set_rf_reg(p_adapter, RF_PATH_A, RF_AC, MASK12BITS, rf_amode);
+
+		/* path-B */
+		if (is2T)
+			phy_set_rf_reg(p_adapter, RF_PATH_B, RF_AC, MASK12BITS, rf_bmode);
+	} else /* Deal with Packet TX case */
+		platform_efio_write_1byte(p_adapter, REG_TXPAUSE, 0x00);
+}
+
+
+void
+phy_lc_calibrate(
+	struct _ADAPTER	*p_adapter,
+	boolean		is2T
+)
+{
+	_phy_lccalibrate92c(p_adapter, is2T);
+}
+
+
+
+/* Analog Pre-distortion calibration */
+#define		APK_BB_REG_NUM	8
+#define		APK_CURVE_REG_NUM 4
+#define		PATH_NUM		2
+
+void
+_phy_ap_calibrate_8192c(
+	struct _ADAPTER	*p_adapter,
+	s8		delta,
+	boolean		is2T
+)
+{
+	HAL_DATA_TYPE	*p_hal_data = GET_HAL_DATA(p_adapter);
+
+	u32			reg_d[PATH_NUM];
+	u32			tmp_reg, index, offset, i, apkbound;
+	u8			path, pathbound = PATH_NUM;
+	u32			BB_backup[APK_BB_REG_NUM];
+	u32			BB_REG[APK_BB_REG_NUM] = {
+		REG_FPGA1_TX_BLOCK,	REG_OFDM_0_TRX_PATH_ENABLE,
+		REG_FPGA0_RFMOD,	REG_OFDM_0_TR_MUX_PAR,
+		REG_FPGA0_XCD_RF_INTERFACE_SW,	REG_FPGA0_XAB_RF_INTERFACE_SW,
+		REG_FPGA0_XA_RF_INTERFACE_OE,	REG_FPGA0_XB_RF_INTERFACE_OE
+	};
+	u32			BB_AP_MODE[APK_BB_REG_NUM] = {
+		0x00000020, 0x00a05430, 0x02040000,
+		0x000800e4, 0x00204000
+	};
+	u32			BB_normal_AP_MODE[APK_BB_REG_NUM] = {
+		0x00000020, 0x00a05430, 0x02040000,
+		0x000800e4, 0x22204000
+	};
+
+	u32			AFE_backup[IQK_ADDA_REG_NUM];
+	u32			AFE_REG[IQK_ADDA_REG_NUM] = {
+		REG_FPGA0_XCD_SWITCH_CONTROL,	REG_BLUE_TOOTH,
+		REG_RX_WAIT_CCA,		REG_TX_CCK_RFON,
+		REG_TX_CCK_BBON,	REG_TX_OFDM_RFON,
+		REG_TX_OFDM_BBON,	REG_TX_TO_RX,
+		REG_TX_TO_TX,		REG_RX_CCK,
+		REG_RX_OFDM,		REG_RX_WAIT_RIFS,
+		REG_RX_TO_RX,		REG_STANDBY,
+		REG_SLEEP,			REG_PMPD_ANAEN
+	};
+
+	u32			MAC_backup[IQK_MAC_REG_NUM];
+	u32			MAC_REG[IQK_MAC_REG_NUM] = {
+		REG_TXPAUSE,		REG_BCN_CTRL,
+		REG_BCN_CTRL_1,	REG_GPIO_MUXCFG
+	};
+
+	u32			APK_RF_init_value[PATH_NUM][APK_BB_REG_NUM] = {
+		{0x0852c, 0x1852c, 0x5852c, 0x1852c, 0x5852c},
+		{0x2852e, 0x0852e, 0x3852e, 0x0852e, 0x0852e}
+	};
+
+	u32			APK_normal_RF_init_value[PATH_NUM][APK_BB_REG_NUM] = {
+		{0x0852c, 0x0a52c, 0x3a52c, 0x5a52c, 0x5a52c},	/* path settings equal to path b settings */
+		{0x0852c, 0x0a52c, 0x5a52c, 0x5a52c, 0x5a52c}
+	};
+
+	u32			APK_RF_value_0[PATH_NUM][APK_BB_REG_NUM] = {
+		{0x52019, 0x52014, 0x52013, 0x5200f, 0x5208d},
+		{0x5201a, 0x52019, 0x52016, 0x52033, 0x52050}
+	};
+
+	u32			APK_normal_RF_value_0[PATH_NUM][APK_BB_REG_NUM] = {
+		{0x52019, 0x52017, 0x52010, 0x5200d, 0x5206a},	/* path settings equal to path b settings */
+		{0x52019, 0x52017, 0x52010, 0x5200d, 0x5206a}
+	};
+#if 0
+	u32			APK_RF_value_A[PATH_NUM][APK_BB_REG_NUM] = {
+		{0x1adb0, 0x1adb0, 0x1ada0, 0x1ad90, 0x1ad80},
+		{0x00fb0, 0x00fb0, 0x00fa0, 0x00f90, 0x00f80}
+	};
+#endif
+	u32			AFE_on_off[PATH_NUM] = {
+		0x04db25a4, 0x0b1b25a4
+	};	/* path A on path B off / path A off path B on */
+
+	u32			APK_offset[PATH_NUM] = {
+		REG_CONFIG_ANT_A, REG_CONFIG_ANT_B
+	};
+
+	u32			APK_normal_offset[PATH_NUM] = {
+		REG_CONFIG_PMPD_ANT_A, REG_CONFIG_PMPD_ANT_B
+	};
+
+	u32			APK_value[PATH_NUM] = {
+		0x92fc0000, 0x12fc0000
+	};
+
+	u32			APK_normal_value[PATH_NUM] = {
+		0x92680000, 0x12680000
+	};
+
+	s8			APK_delta_mapping[APK_BB_REG_NUM][13] = {
+		{-4, -3, -2, -2, -1, -1, 0, 1, 2, 3, 4, 5, 6},
+		{-4, -3, -2, -2, -1, -1, 0, 1, 2, 3, 4, 5, 6},
+		{-6, -4, -2, -2, -1, -1, 0, 1, 2, 3, 4, 5, 6},
+		{-1, -1, -1, -1, -1, -1, 0, 1, 2, 3, 4, 5, 6},
+		{-11, -9, -7, -5, -3, -1, 0, 0, 0, 0, 0, 0, 0}
+	};
+
+	u32			APK_normal_setting_value_1[13] = {
+		0x01017018, 0xf7ed8f84, 0x1b1a1816, 0x2522201e, 0x322e2b28,
+		0x433f3a36, 0x5b544e49, 0x7b726a62, 0xa69a8f84, 0xdfcfc0b3,
+		0x12680000, 0x00880000, 0x00880000
+	};
+
+	u32			APK_normal_setting_value_2[16] = {
+		0x01c7021d, 0x01670183, 0x01000123, 0x00bf00e2, 0x008d00a3,
+		0x0068007b, 0x004d0059, 0x003a0042, 0x002b0031, 0x001f0025,
+		0x0017001b, 0x00110014, 0x000c000f, 0x0009000b, 0x00070008,
+		0x00050006
+	};
+
+	u32			APK_result[PATH_NUM][APK_BB_REG_NUM];	/* val_1_1a, val_1_2a, val_2a, val_3a, val_4a
+ *	u32			AP_curve[PATH_NUM][APK_CURVE_REG_NUM]; */
+
+	s32			BB_offset, delta_V, delta_offset;
+
+#if MP_DRIVER == 1
+	PMPT_CONTEXT	p_mpt_ctx = &(p_adapter->mpt_ctx);
+
+	p_mpt_ctx->APK_bound[0] = 45;
+	p_mpt_ctx->APK_bound[1] = 52;
+#endif
+
+	RTPRINT(FINIT, INIT_IQK, ("==>_phy_ap_calibrate_8192c() delta %d\n", delta));
+	RTPRINT(FINIT, INIT_IQK, ("AP Calibration for %s\n", (is2T ? "2T2R" : "1T1R")));
+	if (!is2T)
+		pathbound = 1;
+
+	/* 2 FOR NORMAL CHIP SETTINGS */
+
+	/* Temporarily do not allow normal driver to do the following settings because these offset
+	 * and value will cause RF internal PA to be unpredictably disabled by HW, such that RF Tx signal
+	 * will disappear after disable/enable card many times on 88CU. RF SD and DD have not find the
+	 * root cause, so we remove these actions temporarily. Added by tynli and SD3 Allen. 2010.05.31. */
+#if MP_DRIVER != 1
+	return;
+#endif
+	/* settings adjust for normal chip */
+	for (index = 0; index < PATH_NUM; index++) {
+		APK_offset[index] = APK_normal_offset[index];
+		APK_value[index] = APK_normal_value[index];
+		AFE_on_off[index] = 0x6fdb25a4;
+	}
+
+	for (index = 0; index < APK_BB_REG_NUM; index++) {
+		for (path = 0; path < pathbound; path++) {
+			APK_RF_init_value[path][index] = APK_normal_RF_init_value[path][index];
+			APK_RF_value_0[path][index] = APK_normal_RF_value_0[path][index];
+		}
+		BB_AP_MODE[index] = BB_normal_AP_MODE[index];
+	}
+
+	apkbound = 6;
+
+	/* save BB default value */
+	for (index = 0; index < APK_BB_REG_NUM ; index++) {
+		if (index == 0)		/* skip */
+			continue;
+		BB_backup[index] = phy_query_bb_reg(p_adapter, BB_REG[index], MASKDWORD);
+	}
+
+	/* save MAC default value */
+	phy_save_mac_registers(p_adapter, MAC_REG, MAC_backup);
+
+	/* save AFE default value */
+	phy_save_adda_registers(p_adapter, AFE_REG, AFE_backup, IQK_ADDA_REG_NUM);
+
+	for (path = 0; path < pathbound; path++) {
+
+
+		if (path == RF_PATH_A) {
+			/* path A APK */
+			/* load APK setting */
+			/* path-A */
+			offset = REG_PDP_ANT_A;
+			for (index = 0; index < 11; index++) {
+				phy_set_bb_reg(p_adapter, offset, MASKDWORD, APK_normal_setting_value_1[index]);
+				RTPRINT(FINIT, INIT_IQK, ("_phy_ap_calibrate_8192c() offset 0x%x value 0x%x\n", offset, phy_query_bb_reg(p_adapter, offset, MASKDWORD)));
+
+				offset += 0x04;
+			}
+
+			phy_set_bb_reg(p_adapter, REG_CONFIG_PMPD_ANT_B, MASKDWORD, 0x12680000);
+
+			offset = REG_CONFIG_ANT_A;
+			for (; index < 13; index++) {
+				phy_set_bb_reg(p_adapter, offset, MASKDWORD, APK_normal_setting_value_1[index]);
+				RTPRINT(FINIT, INIT_IQK, ("_phy_ap_calibrate_8192c() offset 0x%x value 0x%x\n", offset, phy_query_bb_reg(p_adapter, offset, MASKDWORD)));
+
+				offset += 0x04;
+			}
+
+			/* page-B1 */
+			phy_set_bb_reg(p_adapter, REG_FPGA0_IQK, 0xffffff00, 0x400000);
+
+			/* path A */
+			offset = REG_PDP_ANT_A;
+			for (index = 0; index < 16; index++) {
+				phy_set_bb_reg(p_adapter, offset, MASKDWORD, APK_normal_setting_value_2[index]);
+				RTPRINT(FINIT, INIT_IQK, ("_phy_ap_calibrate_8192c() offset 0x%x value 0x%x\n", offset, phy_query_bb_reg(p_adapter, offset, MASKDWORD)));
+
+				offset += 0x04;
+			}
+			phy_set_bb_reg(p_adapter, REG_FPGA0_IQK, 0xffffff00, 0);
+		} else if (path == RF_PATH_B) {
+			/* path B APK */
+			/* load APK setting */
+			/* path-B */
+			offset = REG_PDP_ANT_B;
+			for (index = 0; index < 10; index++) {
+				phy_set_bb_reg(p_adapter, offset, MASKDWORD, APK_normal_setting_value_1[index]);
+				RTPRINT(FINIT, INIT_IQK, ("_phy_ap_calibrate_8192c() offset 0x%x value 0x%x\n", offset, phy_query_bb_reg(p_adapter, offset, MASKDWORD)));
+
+				offset += 0x04;
+			}
+			phy_set_bb_reg(p_adapter, REG_CONFIG_PMPD_ANT_A, MASKDWORD, 0x12680000);
+
+			phy_set_bb_reg(p_adapter, REG_CONFIG_PMPD_ANT_B, MASKDWORD, 0x12680000);
+
+			offset = REG_CONFIG_ANT_A;
+			index = 11;
+			for (; index < 13; index++) { /* offset 0xb68, 0xb6c */
+				phy_set_bb_reg(p_adapter, offset, MASKDWORD, APK_normal_setting_value_1[index]);
+				RTPRINT(FINIT, INIT_IQK, ("_phy_ap_calibrate_8192c() offset 0x%x value 0x%x\n", offset, phy_query_bb_reg(p_adapter, offset, MASKDWORD)));
+
+				offset += 0x04;
+			}
+
+			/* page-B1 */
+			phy_set_bb_reg(p_adapter, REG_FPGA0_IQK, 0xffffff00, 0x400000);
+
+			/* path B */
+			offset = 0xb60;
+			for (index = 0; index < 16; index++) {
+				phy_set_bb_reg(p_adapter, offset, MASKDWORD, APK_normal_setting_value_2[index]);
+				RTPRINT(FINIT, INIT_IQK, ("_phy_ap_calibrate_8192c() offset 0x%x value 0x%x\n", offset, phy_query_bb_reg(p_adapter, offset, MASKDWORD)));
+
+				offset += 0x04;
+			}
+			phy_set_bb_reg(p_adapter, REG_FPGA0_IQK, 0xffffff00, 0);
+		}
+
+		/* save RF default value */
+		reg_d[path] = phy_query_rf_reg(p_adapter, path, RF_TXBIAS_A, RFREGOFFSETMASK);
+
+		/* path A AFE all on, path B AFE All off or vise versa */
+		for (index = 0; index < IQK_ADDA_REG_NUM ; index++)
+			phy_set_bb_reg(p_adapter, AFE_REG[index], MASKDWORD, AFE_on_off[path]);
+		RTPRINT(FINIT, INIT_IQK, ("_phy_ap_calibrate_8192c() offset 0xe70 %x\n", phy_query_bb_reg(p_adapter, REG_RX_WAIT_CCA, MASKDWORD)));
+
+		/* BB to AP mode */
+		if (path == 0) {
+			for (index = 0; index < APK_BB_REG_NUM ; index++) {
+
+				if (index == 0)		/* skip */
+					continue;
+				else if (index < 5)
+					phy_set_bb_reg(p_adapter, BB_REG[index], MASKDWORD, BB_AP_MODE[index]);
+				else if (BB_REG[index] == 0x870)
+					phy_set_bb_reg(p_adapter, BB_REG[index], MASKDWORD, BB_backup[index] | BIT(10) | BIT(26));
+				else
+					phy_set_bb_reg(p_adapter, BB_REG[index], BIT(10), 0x0);
+			}
+
+			phy_set_bb_reg(p_adapter, REG_TX_IQK_TONE_A, MASKDWORD, 0x01008c00);
+			phy_set_bb_reg(p_adapter, REG_RX_IQK_TONE_A, MASKDWORD, 0x01008c00);
+		} else {	/* path B */
+			phy_set_bb_reg(p_adapter, REG_TX_IQK_TONE_B, MASKDWORD, 0x01008c00);
+			phy_set_bb_reg(p_adapter, REG_RX_IQK_TONE_B, MASKDWORD, 0x01008c00);
+
+		}
+
+		RTPRINT(FINIT, INIT_IQK, ("_phy_ap_calibrate_8192c() offset 0x800 %x\n", phy_query_bb_reg(p_adapter, 0x800, MASKDWORD)));
+
+		/* MAC settings */
+		phy_mac_setting_calibration(p_adapter, MAC_REG, MAC_backup);
+
+		if (path == RF_PATH_A)	/* path B to standby mode */
+			phy_set_rf_reg(p_adapter, RF_PATH_B, RF_AC, RFREGOFFSETMASK, 0x10000);
+		else {		/* path A to standby mode */
+			phy_set_rf_reg(p_adapter, RF_PATH_A, RF_AC, RFREGOFFSETMASK, 0x10000);
+			phy_set_rf_reg(p_adapter, RF_PATH_A, RF_MODE1, RFREGOFFSETMASK, 0x1000f);
+			phy_set_rf_reg(p_adapter, RF_PATH_A, RF_MODE2, RFREGOFFSETMASK, 0x20103);
+		}
+
+		delta_offset = ((delta + 14) / 2);
+		if (delta_offset < 0)
+			delta_offset = 0;
+		else if (delta_offset > 12)
+			delta_offset = 12;
+
+		/* AP calibration */
+		for (index = 0; index < APK_BB_REG_NUM; index++) {
+			if (index != 1)	/* only DO PA11+PAD01001, AP RF setting */
+				continue;
+
+			tmp_reg = APK_RF_init_value[path][index];
+#if 1
+			if (!p_hal_data->is_apk_thermal_meter_ignore) {
+				BB_offset = (tmp_reg & 0xF0000) >> 16;
+
+				if (!(tmp_reg & BIT(15))) /* sign bit 0 */
+					BB_offset = -BB_offset;
+
+				delta_V = APK_delta_mapping[index][delta_offset];
+
+				BB_offset += delta_V;
+
+				RTPRINT(FINIT, INIT_IQK, ("_phy_ap_calibrate_8192c() APK index %d tmp_reg 0x%x delta_V %d delta_offset %d\n", index, tmp_reg, delta_V, delta_offset));
+
+				if (BB_offset < 0) {
+					tmp_reg = tmp_reg & (~BIT(15));
+					BB_offset = -BB_offset;
+				} else
+					tmp_reg = tmp_reg | BIT(15);
+				tmp_reg = (tmp_reg & 0xFFF0FFFF) | (BB_offset << 16);
+			}
+#endif
+
+#if DEV_BUS_TYPE == RT_PCI_INTERFACE
+			if (IS_81xxC_VENDOR_UMC_B_CUT(p_hal_data->version_id))
+				phy_set_rf_reg(p_adapter, path, RF_IPA_A, RFREGOFFSETMASK, 0x894ae);
+			else
+#endif
+				phy_set_rf_reg(p_adapter, path, RF_IPA_A, RFREGOFFSETMASK, 0x8992e);
+			RTPRINT(FINIT, INIT_IQK, ("_phy_ap_calibrate_8192c() offset 0xc %x\n", phy_query_rf_reg(p_adapter, path, RF_IPA_A, RFREGOFFSETMASK)));
+			phy_set_rf_reg(p_adapter, path, RF_AC, RFREGOFFSETMASK, APK_RF_value_0[path][index]);
+			RTPRINT(FINIT, INIT_IQK, ("_phy_ap_calibrate_8192c() offset 0x0 %x\n", phy_query_rf_reg(p_adapter, path, RF_AC, RFREGOFFSETMASK)));
+			phy_set_rf_reg(p_adapter, path, RF_TXBIAS_A, RFREGOFFSETMASK, tmp_reg);
+			RTPRINT(FINIT, INIT_IQK, ("_phy_ap_calibrate_8192c() offset 0xd %x\n", phy_query_rf_reg(p_adapter, path, RF_TXBIAS_A, RFREGOFFSETMASK)));
+
+			/* PA11+PAD01111, one shot */
+			i = 0;
+			do {
+				phy_set_bb_reg(p_adapter, REG_FPGA0_IQK, 0xffffff00, 0x800000);
+				{
+					phy_set_bb_reg(p_adapter, APK_offset[path], MASKDWORD, APK_value[0]);
+					RTPRINT(FINIT, INIT_IQK, ("_phy_ap_calibrate_8192c() offset 0x%x value 0x%x\n", APK_offset[path], phy_query_bb_reg(p_adapter, APK_offset[path], MASKDWORD)));
+					delay_ms(3);
+					phy_set_bb_reg(p_adapter, APK_offset[path], MASKDWORD, APK_value[1]);
+					RTPRINT(FINIT, INIT_IQK, ("_phy_ap_calibrate_8192c() offset 0x%x value 0x%x\n", APK_offset[path], phy_query_bb_reg(p_adapter, APK_offset[path], MASKDWORD)));
+
+					delay_ms(20);
+				}
+				phy_set_bb_reg(p_adapter, REG_FPGA0_IQK, 0xffffff00, 0);
+
+				if (path == RF_PATH_A)
+					tmp_reg = phy_query_bb_reg(p_adapter, REG_APK, 0x03E00000);
+				else
+					tmp_reg = phy_query_bb_reg(p_adapter, REG_APK, 0xF8000000);
+				RTPRINT(FINIT, INIT_IQK, ("_phy_ap_calibrate_8192c() offset 0xbd8[25:21] %x\n", tmp_reg));
+
+
+				i++;
+			} while (tmp_reg > apkbound && i < 4);
+
+			APK_result[path][index] = tmp_reg;
+		}
+	}
+
+	/* reload MAC default value */
+	phy_reload_mac_registers(p_adapter, MAC_REG, MAC_backup);
+
+	/* reload BB default value */
+	for (index = 0; index < APK_BB_REG_NUM ; index++) {
+
+		if (index == 0)		/* skip */
+			continue;
+		phy_set_bb_reg(p_adapter, BB_REG[index], MASKDWORD, BB_backup[index]);
+	}
+
+	/* reload AFE default value */
+	phy_reload_adda_registers(p_adapter, AFE_REG, AFE_backup, IQK_ADDA_REG_NUM);
+
+	/* reload RF path default value */
+	for (path = 0; path < pathbound; path++) {
+		phy_set_rf_reg(p_adapter, path, RF_TXBIAS_A, RFREGOFFSETMASK, reg_d[path]);
+		if (path == RF_PATH_B) {
+			phy_set_rf_reg(p_adapter, RF_PATH_A, RF_MODE1, RFREGOFFSETMASK, 0x1000f);
+			phy_set_rf_reg(p_adapter, RF_PATH_A, RF_MODE2, RFREGOFFSETMASK, 0x20101);
+		}
+
+		/* note no index == 0 */
+		if (APK_result[path][1] > 6)
+			APK_result[path][1] = 6;
+		RTPRINT(FINIT, INIT_IQK, ("apk path %d result %d 0x%x \t", path, 1, APK_result[path][1]));
+	}
+
+	RTPRINT(FINIT, INIT_IQK, ("\n"));
+
+
+	for (path = 0; path < pathbound; path++) {
+		phy_set_rf_reg(p_adapter, path, RF_BS_PA_APSET_G1_G4, RFREGOFFSETMASK,
+			((APK_result[path][1] << 15) | (APK_result[path][1] << 10) | (APK_result[path][1] << 5) | APK_result[path][1]));
+		if (path == RF_PATH_A)
+			phy_set_rf_reg(p_adapter, path, RF_BS_PA_APSET_G5_G8, RFREGOFFSETMASK,
+				((APK_result[path][1] << 15) | (APK_result[path][1] << 10) | (0x00 << 5) | 0x05));
+		else
+			phy_set_rf_reg(p_adapter, path, RF_BS_PA_APSET_G5_G8, RFREGOFFSETMASK,
+				((APK_result[path][1] << 15) | (APK_result[path][1] << 10) | (0x02 << 5) | 0x05));
+
+		phy_set_rf_reg(p_adapter, path, RF_BS_PA_APSET_G9_G11, RFREGOFFSETMASK, ((0x08 << 15) | (0x08 << 10) | (0x08 << 5) | 0x08));
+	}
+
+	p_hal_data->is_ap_kdone = true;
+
+	RTPRINT(FINIT, INIT_IQK, ("<==_phy_ap_calibrate_8192c()\n"));
+}
+
+
+void
+phy_iq_calibrate_8192c(
+	struct _ADAPTER	*p_adapter,
+	boolean	is_recovery
+)
+{
+	HAL_DATA_TYPE	*p_hal_data = GET_HAL_DATA(p_adapter);
+	s32			result[4][8];	/* last is final result */
+	u8			i, final_candidate, indexforchannel;
+	boolean			is_patha_ok, is_pathb_ok;
+	s32			rege94, rege9c, regea4, regeac, regeb4, regebc, regec4, regecc, reg_tmp = 0;
+	boolean			is12simular, is13simular, is23simular;
+	boolean		is_start_cont_tx = false, is_single_tone = false, is_carrier_suppression = false;
+	u32			IQK_BB_REG_92C[IQK_BB_REG_NUM] = {
+		REG_OFDM_0_XA_RX_IQ_IMBALANCE,	REG_OFDM_0_XB_RX_IQ_IMBALANCE,
+		REG_OFDM_0_ECCA_THRESHOLD,	REG_OFDM_0_AGC_RSSI_TABLE,
+		REG_OFDM_0_XA_TX_IQ_IMBALANCE,	REG_OFDM_0_XB_TX_IQ_IMBALANCE,
+		REG_OFDM_0_XC_TX_AFE,			REG_OFDM_0_XD_TX_AFE,
+		REG_OFDM_0_RX_IQ_EXT_ANTA
+	};
+
+	if (odm_check_power_status(p_adapter) == false)
+		return;
+
+#if MP_DRIVER == 1
+	is_start_cont_tx = p_adapter->mpt_ctx.is_start_cont_tx;
+	is_single_tone = p_adapter->mpt_ctx.is_single_tone;
+	is_carrier_suppression = p_adapter->mpt_ctx.is_carrier_suppression;
+#endif
+
+	/* ignore IQK when continuous Tx */
+	if (is_start_cont_tx || is_single_tone || is_carrier_suppression)
+		return;
+
+#ifdef DISABLE_BB_RF
+	return;
+#endif
+	if (p_adapter->is_slave_of_dmsp)
+		return;
+
+	if (is_recovery) {
+		phy_reload_adda_registers(p_adapter, IQK_BB_REG_92C, p_hal_data->IQK_BB_backup_recover, 9);
+		return;
+
+	}
+
+	RTPRINT(FINIT, INIT_IQK, ("IQK:Start!!!\n"));
+
+	for (i = 0; i < 8; i++) {
+		result[0][i] = 0;
+		result[1][i] = 0;
+		result[2][i] = 0;
+		result[3][i] = 0;
+	}
+	final_candidate = 0xff;
+	is_patha_ok = false;
+	is_pathb_ok = false;
+	is12simular = false;
+	is23simular = false;
+	is13simular = false;
+
+	acquire_cck_and_rw_page_a_control(p_adapter);
+	/*RT_TRACE(COMP_INIT,DBG_LOUD,("Acquire Mutex in IQCalibrate\n"));*/
+	for (i = 0; i < 3; i++) {
+		/*For 88C 1T1R*/
+		_phy_iq_calibrate_8192c(p_adapter, result, i, false);
+
+		if (i == 1) {
+			is12simular = phy_simularity_compare(p_adapter, result, 0, 1);
+			if (is12simular) {
+				final_candidate = 0;
+				break;
+			}
+		}
+
+		if (i == 2) {
+			is13simular = phy_simularity_compare(p_adapter, result, 0, 2);
+			if (is13simular) {
+				final_candidate = 0;
+				break;
+			}
+
+			is23simular = phy_simularity_compare(p_adapter, result, 1, 2);
+			if (is23simular)
+				final_candidate = 1;
+			else {
+				for (i = 0; i < 8; i++)
+					reg_tmp += result[3][i];
+
+				if (reg_tmp != 0)
+					final_candidate = 3;
+				else
+					final_candidate = 0xFF;
+			}
+		}
+	}
+	/*	RT_TRACE(COMP_INIT,DBG_LOUD,("Release Mutex in IQCalibrate\n")); */
+	release_cck_and_rw_pagea_control(p_adapter);
+
+	for (i = 0; i < 4; i++) {
+		rege94 = result[i][0];
+		rege9c = result[i][1];
+		regea4 = result[i][2];
+		regeac = result[i][3];
+		regeb4 = result[i][4];
+		regebc = result[i][5];
+		regec4 = result[i][6];
+		regecc = result[i][7];
+		RTPRINT(FINIT, INIT_IQK, ("IQK: rege94=%x rege9c=%x regea4=%x regeac=%x regeb4=%x regebc=%x regec4=%x regecc=%x\n ", rege94, rege9c, regea4, regeac, regeb4, regebc, regec4, regecc));
+	}
+
+	if (final_candidate != 0xff) {
+		p_hal_data->rege94 = rege94 = result[final_candidate][0];
+		p_hal_data->rege9c = rege9c = result[final_candidate][1];
+		regea4 = result[final_candidate][2];
+		regeac = result[final_candidate][3];
+		p_hal_data->regeb4 = regeb4 = result[final_candidate][4];
+		p_hal_data->regebc = regebc = result[final_candidate][5];
+		regec4 = result[final_candidate][6];
+		regecc = result[final_candidate][7];
+		RTPRINT(FINIT, INIT_IQK, ("IQK: final_candidate is %x\n", final_candidate));
+		RTPRINT(FINIT, INIT_IQK, ("IQK: rege94=%x rege9c=%x regea4=%x regeac=%x regeb4=%x regebc=%x regec4=%x regecc=%x\n ", rege94, rege9c, regea4, regeac, regeb4, regebc, regec4, regecc));
+		is_patha_ok = is_pathb_ok = true;
+	} else {
+		rege94 = regeb4 = p_hal_data->rege94 = p_hal_data->regeb4 = 0x100;	/* X default value */
+		rege9c = regebc = p_hal_data->rege9c = p_hal_data->regebc = 0x0;		/* Y default value */
+	}
+
+	if ((rege94 != 0)/*&&(regea4 != 0)*/) {
+		if (p_hal_data->current_band_type == BAND_ON_5G)
+			phy_path_a_fill_iqk_matrix_5g_normal(p_adapter, is_patha_ok, result, final_candidate, (regea4 == 0));
+		else
+			phy_path_a_fill_iqk_matrix(p_adapter, is_patha_ok, result, final_candidate, (regea4 == 0));
+
+	}
+
+	if (IS_92C_SERIAL(p_hal_data->version_id) || IS_92D_SINGLEPHY(p_hal_data->version_id)) {
+		if ((regeb4 != 0)/*&&(regec4 != 0)*/) {
+			if (p_hal_data->current_band_type == BAND_ON_5G)
+				phy_path_b_fill_iqk_matrix_5g_normal(p_adapter, is_pathb_ok, result, final_candidate, (regec4 == 0));
+			else
+				phy_path_b_fill_iqk_matrix(p_adapter, is_pathb_ok, result, final_candidate, (regec4 == 0));
+		}
+	}
+
+	phy_save_adda_registers(p_adapter, IQK_BB_REG_92C, p_hal_data->IQK_BB_backup_recover, 9);
+
+}
+
+
+void
+phy_lc_calibrate_8192c(
+	struct _ADAPTER	*p_adapter
+)
+{
+	HAL_DATA_TYPE	*p_hal_data = GET_HAL_DATA(p_adapter);
+	boolean		is_start_cont_tx = false, is_single_tone = false, is_carrier_suppression = false;
+	PMGNT_INFO		p_mgnt_info = &p_adapter->MgntInfo;
+	PMGNT_INFO		p_mgnt_info_buddy_adapter;
+	u32			timeout = 2000, timecount = 0;
+	struct _ADAPTER	*buddy_adapter = p_adapter->buddy_adapter;
+
+#if MP_DRIVER == 1
+	is_start_cont_tx = p_adapter->mpt_ctx.is_start_cont_tx;
+	is_single_tone = p_adapter->mpt_ctx.is_single_tone;
+	is_carrier_suppression = p_adapter->mpt_ctx.is_carrier_suppression;
+#endif
+
+#ifdef DISABLE_BB_RF
+	return;
+#endif
+
+	/* ignore LCK when continuous Tx */
+	if (is_start_cont_tx || is_single_tone || is_carrier_suppression)
+		return;
+
+	if (buddy_adapter != NULL &&
+	    ((p_adapter->interface_index == 0 && p_hal_data->current_band_type == BAND_ON_2_4G) ||
+	     (p_adapter->interface_index == 1 && p_hal_data->current_band_type == BAND_ON_5G))) {
+		p_mgnt_info_buddy_adapter = &buddy_adapter->MgntInfo;
+		while (p_mgnt_info_buddy_adapter->is_scan_in_progress && timecount < timeout) {
+			delay_ms(50);
+			timecount += 50;
+		}
+	}
+
+	while (p_mgnt_info->is_scan_in_progress && timecount < timeout) {
+		delay_ms(50);
+		timecount += 50;
+	}
+
+	p_hal_data->is_lck_in_progress = true;
+
+	RTPRINT(FINIT, INIT_IQK, ("LCK:Start!!!interface %d currentband %x delay %d ms\n", p_adapter->interface_index, p_hal_data->current_band_type, timecount));
+
+	/* if(IS_92C_SERIAL(p_hal_data->version_id) || IS_92D_SINGLEPHY(p_hal_data->version_id)) */
+	if (IS_2T2R(p_hal_data->version_id))
+		phy_lc_calibrate(p_adapter, true);
+	else {
+		/* For 88C 1T1R */
+		phy_lc_calibrate(p_adapter, false);
+	}
+
+	p_hal_data->is_lck_in_progress = false;
+
+	RTPRINT(FINIT, INIT_IQK, ("LCK:Finish!!!interface %d\n", p_adapter->interface_index));
+
+
+}
+
+void
+phy_ap_calibrate_8192c(
+	struct _ADAPTER	*p_adapter,
+	s8		delta
+)
+{
+	HAL_DATA_TYPE	*p_hal_data = GET_HAL_DATA(p_adapter);
+
+	/* default disable APK, because Tx NG issue, suggest by Jenyu, 2011.11.25 */
+	return;
+
+#ifdef DISABLE_BB_RF
+	return;
+#endif
+
+#if FOR_BRAZIL_PRETEST != 1
+	if (p_hal_data->is_ap_kdone)
+#endif
+		return;
+
+	if (IS_92C_SERIAL(p_hal_data->version_id))
+		_phy_ap_calibrate_8192c(p_adapter, delta, true);
+	else {
+		/* For 88C 1T1R */
+		_phy_ap_calibrate_8192c(p_adapter, delta, false);
+	}
+}
+
+
+#endif
+
+
+/* 3============================================================
+ * 3 IQ Calibration
+ * 3============================================================ */
+
+void
+odm_reset_iqk_result(
+	void		*p_dm_void
+)
+{
+	return;
+}
+#if 1/* !(DM_ODM_SUPPORT_TYPE & ODM_AP) */
+u8 odm_get_right_chnl_place_for_iqk(u8 chnl)
+{
+	u8	channel_all[ODM_TARGET_CHNL_NUM_2G_5G] = {
+		1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 36, 38, 40, 42, 44, 46, 48, 50, 52, 54, 56, 58, 60, 62, 64, 100, 102, 104, 106, 108, 110, 112, 114, 116, 118, 120, 122, 124, 126, 128, 130, 132, 134, 136, 138, 140, 149, 151, 153, 155, 157, 159, 161, 163, 165
+	};
+	u8	place = chnl;
+
+
+	if (chnl > 14) {
+		for (place = 14; place < sizeof(channel_all); place++) {
+			if (channel_all[place] == chnl)
+				return place - 13;
+		}
+	}
+	return 0;
+
+}
+#endif
+
+void
+odm_iq_calibrate(
+	struct PHY_DM_STRUCT	*p_dm_odm
+)
+{
+	struct _ADAPTER	*adapter = p_dm_odm->adapter;
+
+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
+	if (*p_dm_odm->p_is_fcs_mode_enable)
+		return;
+#endif
+
+
+
+	if (p_dm_odm->is_linked) {
+		if ((*p_dm_odm->p_channel != p_dm_odm->pre_channel) && (!*p_dm_odm->p_is_scan_in_process)) {
+			p_dm_odm->pre_channel = *p_dm_odm->p_channel;
+			p_dm_odm->linked_interval = 0;
+		}
+
+		if (p_dm_odm->linked_interval < 3)
+			p_dm_odm->linked_interval++;
+
+		if (p_dm_odm->linked_interval == 2) {
+
+#if (RTL8814A_SUPPORT == 1)
+			if (p_dm_odm->support_ic_type == ODM_RTL8814A)
+				phy_iq_calibrate_8814a(p_dm_odm, false);
+#endif
+
+#if (RTL8822B_SUPPORT == 1)
+			if (p_dm_odm->support_ic_type == ODM_RTL8822B)
+				phy_iq_calibrate_8822b(p_dm_odm, false);
+#endif
+
+#if (RTL8821C_SUPPORT == 1)
+			if (p_dm_odm->support_ic_type == ODM_RTL8821C)
+				phy_iq_calibrate_8821c(p_dm_odm, false);
+#endif
+
+#if (RTL8821A_SUPPORT == 1)
+			if (p_dm_odm->support_ic_type == ODM_RTL8821)
+				phy_iq_calibrate_8821a(p_dm_odm, false);
+#endif
+
+#if (RTL8812A_SUPPORT == 1)
+			if (p_dm_odm->support_ic_type == ODM_RTL8812)
+				_phy_iq_calibrate_8812a(p_dm_odm, false);
+#endif
+		}
+	} else
+		p_dm_odm->linked_interval = 0;
+
+}
+
+void phydm_rf_init(void		*p_dm_void)
+{
+	struct PHY_DM_STRUCT		*p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
+	odm_txpowertracking_init(p_dm_odm);
+
+#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
+	odm_clear_txpowertracking_state(p_dm_odm);
+#endif
+
+#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
+#if (RTL8814A_SUPPORT == 1)
+	if (p_dm_odm->support_ic_type & ODM_RTL8814A)
+		phy_iq_calibrate_8814a_init(p_dm_odm);
+#endif
+#endif
+
+}
+
+void phydm_rf_watchdog(void		*p_dm_void)
+{
+	struct PHY_DM_STRUCT		*p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
+#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
+	odm_txpowertracking_check(p_dm_odm);
+	if (p_dm_odm->support_ic_type & ODM_IC_11AC_SERIES)
+		odm_iq_calibrate(p_dm_odm);
+#endif
+}
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/halphyrf_ap.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/halphyrf_ap.h
--- linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/halphyrf_ap.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/halphyrf_ap.h	2020-04-10 16:35:06.818660161 +0300
@@ -0,0 +1,178 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
+ *
+ *
+ ******************************************************************************/
+
+#ifndef __HAL_PHY_RF_H__
+#define __HAL_PHY_RF_H__
+
+#include "phydm_powertracking_ap.h"
+#if (RTL8814A_SUPPORT == 1)
+	#include "rtl8814a/phydm_iqk_8814a.h"
+#endif
+
+#if (RTL8822B_SUPPORT == 1)
+	#include "rtl8822b/phydm_iqk_8822b.h"
+#endif
+
+#if (RTL8821C_SUPPORT == 1)
+	#include "rtl8822b/phydm_iqk_8821c.h"
+#endif
+
+enum pwrtrack_method {
+	BBSWING,
+	TXAGC,
+	MIX_MODE,
+	TSSI_MODE
+};
+
+typedef void	(*func_set_pwr)(void *, enum pwrtrack_method, u8, u8);
+typedef void(*func_iqk)(void *, u8, u8, u8);
+typedef void	(*func_lck)(void *);
+/* refine by YuChen for 8814A */
+typedef void	(*func_swing)(void *, u8 **, u8 **, u8 **, u8 **);
+typedef void	(*func_swing8814only)(void *, u8 **, u8 **, u8 **, u8 **);
+typedef void	(*func_all_swing)(void *, u8 **, u8 **, u8 **, u8 **, u8 **, u8 **, u8 **, u8 **);
+
+
+struct _TXPWRTRACK_CFG {
+	u8		swing_table_size_cck;
+	u8		swing_table_size_ofdm;
+	u8		threshold_iqk;
+	u8		threshold_dpk;
+	u8		average_thermal_num;
+	u8		rf_path_count;
+	u32		thermal_reg_addr;
+	func_set_pwr	odm_tx_pwr_track_set_pwr;
+	func_iqk	do_iqk;
+	func_lck		phy_lc_calibrate;
+	func_swing	get_delta_swing_table;
+	func_swing8814only	get_delta_swing_table8814only;
+	func_all_swing	get_delta_all_swing_table;
+};
+
+void
+configure_txpower_track(
+	void		*p_dm_void,
+	struct _TXPWRTRACK_CFG	*p_config
+);
+
+
+void
+odm_txpowertracking_callback_thermal_meter(
+#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
+	void		*p_dm_void
+#else
+	struct _ADAPTER	*adapter
+#endif
+);
+
+#if (RTL8192E_SUPPORT == 1)
+void
+odm_txpowertracking_callback_thermal_meter_92e(
+#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
+	void		*p_dm_void
+#else
+	struct _ADAPTER	*adapter
+#endif
+);
+#endif
+
+#if (RTL8814A_SUPPORT == 1)
+void
+odm_txpowertracking_callback_thermal_meter_jaguar_series2(
+#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
+	void		*p_dm_void
+#else
+	struct _ADAPTER	*adapter
+#endif
+);
+
+#elif ODM_IC_11AC_SERIES_SUPPORT
+void
+odm_txpowertracking_callback_thermal_meter_jaguar_series(
+#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
+	void		*p_dm_void
+#else
+	struct _ADAPTER	*adapter
+#endif
+);
+
+#elif (RTL8197F_SUPPORT == 1 || RTL8822B_SUPPORT == 1)
+void
+odm_txpowertracking_callback_thermal_meter_jaguar_series3(
+#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
+	void		*p_dm_void
+#else
+	struct _ADAPTER	*adapter
+#endif
+);
+
+#endif
+
+#define IS_CCK_RATE(_rate)				(ODM_MGN_1M == _rate || _rate == ODM_MGN_2M || _rate == ODM_MGN_5_5M || _rate == ODM_MGN_11M)
+
+
+#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
+#define MAX_TOLERANCE          5
+#define IQK_DELAY_TIME         1               /* ms */
+
+/*
+* BB/MAC/RF other monitor API
+*   */
+
+void	phy_set_monitor_mode8192c(struct _ADAPTER	*p_adapter,
+				  boolean		is_enable_monitor_mode);
+
+/*
+ * IQ calibrate
+ *   */
+void
+phy_iq_calibrate_8192c(struct _ADAPTER	*p_adapter,
+		       boolean	is_recovery);
+
+/*
+ * LC calibrate
+ *   */
+void
+phy_lc_calibrate_8192c(struct _ADAPTER	*p_adapter);
+
+/*
+ * AP calibrate
+ *   */
+void
+phy_ap_calibrate_8192c(struct _ADAPTER	*p_adapter,
+		       s8		delta);
+#endif
+
+#define ODM_TARGET_CHNL_NUM_2G_5G	59
+
+
+void
+odm_reset_iqk_result(
+	void		*p_dm_void
+);
+u8
+odm_get_right_chnl_place_for_iqk(
+	u8 chnl
+);
+
+void phydm_rf_init(void		*p_dm_void);
+void phydm_rf_watchdog(void		*p_dm_void);
+
+#endif	/*  #ifndef __HAL_PHY_RF_H__ */
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/halphyrf_ce.c linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/halphyrf_ce.c
--- linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/halphyrf_ce.c	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/halphyrf_ce.c	2020-04-10 16:35:06.818660161 +0300
@@ -0,0 +1,837 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
+ *
+ *
+ ******************************************************************************/
+
+#include "mp_precomp.h"
+#include "phydm_precomp.h"
+
+#define	CALCULATE_SWINGTALBE_OFFSET(_offset, _direction, _size, _delta_thermal) \
+	do {\
+		for (_offset = 0; _offset < _size; _offset++) { \
+			\
+			if (_delta_thermal < thermal_threshold[_direction][_offset]) { \
+				\
+				if (_offset != 0)\
+					_offset--;\
+				break;\
+			} \
+		}			\
+		if (_offset >= _size)\
+			_offset = _size-1;\
+	} while (0)
+
+void configure_txpower_track(
+	void					*p_dm_void,
+	struct _TXPWRTRACK_CFG	*p_config
+)
+{
+	struct PHY_DM_STRUCT		*p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
+
+#if RTL8192E_SUPPORT
+	if (p_dm_odm->support_ic_type == ODM_RTL8192E)
+		configure_txpower_track_8192e(p_config);
+#endif
+#if RTL8821A_SUPPORT
+	if (p_dm_odm->support_ic_type == ODM_RTL8821)
+		configure_txpower_track_8821a(p_config);
+#endif
+#if RTL8812A_SUPPORT
+	if (p_dm_odm->support_ic_type == ODM_RTL8812)
+		configure_txpower_track_8812a(p_config);
+#endif
+#if RTL8188E_SUPPORT
+	if (p_dm_odm->support_ic_type == ODM_RTL8188E)
+		configure_txpower_track_8188e(p_config);
+#endif
+
+#if RTL8723B_SUPPORT
+	if (p_dm_odm->support_ic_type == ODM_RTL8723B)
+		configure_txpower_track_8723b(p_config);
+#endif
+
+#if RTL8814A_SUPPORT
+	if (p_dm_odm->support_ic_type == ODM_RTL8814A)
+		configure_txpower_track_8814a(p_config);
+#endif
+
+#if RTL8703B_SUPPORT
+	if (p_dm_odm->support_ic_type == ODM_RTL8703B)
+		configure_txpower_track_8703b(p_config);
+#endif
+
+#if RTL8188F_SUPPORT
+	if (p_dm_odm->support_ic_type == ODM_RTL8188F)
+		configure_txpower_track_8188f(p_config);
+#endif
+#if RTL8723D_SUPPORT
+	if (p_dm_odm->support_ic_type == ODM_RTL8723D)
+		configure_txpower_track_8723d(p_config);
+#endif
+/* JJ ADD 20161014 */
+#if RTL8710B_SUPPORT
+	if (p_dm_odm->support_ic_type == ODM_RTL8710B)
+		configure_txpower_track_8710b(p_config);
+#endif
+
+#if RTL8822B_SUPPORT
+	if (p_dm_odm->support_ic_type == ODM_RTL8822B)
+		configure_txpower_track_8822b(p_config);
+#endif
+#if RTL8821C_SUPPORT
+	if (p_dm_odm->support_ic_type == ODM_RTL8821C)
+		configure_txpower_track_8821c(p_config);
+#endif
+
+}
+
+/* **********************************************************************
+ * <20121113, Kordan> This function should be called when tx_agc changed.
+ * Otherwise the previous compensation is gone, because we record the
+ * delta of temperature between two TxPowerTracking watch dogs.
+ *
+ * NOTE: If Tx BB swing or Tx scaling is varified during run-time, still
+ * need to call this function.
+ * ********************************************************************** */
+void
+odm_clear_txpowertracking_state(
+	void					*p_dm_void
+)
+{
+	struct PHY_DM_STRUCT		*p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
+	PHAL_DATA_TYPE	p_hal_data = GET_HAL_DATA(p_dm_odm->adapter);
+	u8			p = 0;
+	struct odm_rf_calibration_structure	*p_rf_calibrate_info = &(p_dm_odm->rf_calibrate_info);
+
+	p_rf_calibrate_info->bb_swing_idx_cck_base = p_rf_calibrate_info->default_cck_index;
+	p_rf_calibrate_info->bb_swing_idx_cck = p_rf_calibrate_info->default_cck_index;
+	p_dm_odm->rf_calibrate_info.CCK_index = 0;
+
+	for (p = ODM_RF_PATH_A; p < MAX_RF_PATH; ++p) {
+		p_rf_calibrate_info->bb_swing_idx_ofdm_base[p] = p_rf_calibrate_info->default_ofdm_index;
+		p_rf_calibrate_info->bb_swing_idx_ofdm[p] = p_rf_calibrate_info->default_ofdm_index;
+		p_rf_calibrate_info->OFDM_index[p] = p_rf_calibrate_info->default_ofdm_index;
+
+		p_rf_calibrate_info->power_index_offset[p] = 0;
+		p_rf_calibrate_info->delta_power_index[p] = 0;
+		p_rf_calibrate_info->delta_power_index_last[p] = 0;
+
+		p_rf_calibrate_info->absolute_ofdm_swing_idx[p] = 0;    /* Initial Mix mode power tracking*/
+		p_rf_calibrate_info->remnant_ofdm_swing_idx[p] = 0;
+		p_rf_calibrate_info->kfree_offset[p] = 0;
+	}
+
+	p_rf_calibrate_info->modify_tx_agc_flag_path_a = false;       /*Initial at Modify Tx Scaling mode*/
+	p_rf_calibrate_info->modify_tx_agc_flag_path_b = false;       /*Initial at Modify Tx Scaling mode*/
+	p_rf_calibrate_info->modify_tx_agc_flag_path_c = false;       /*Initial at Modify Tx Scaling mode*/
+	p_rf_calibrate_info->modify_tx_agc_flag_path_d = false;       /*Initial at Modify Tx Scaling mode*/
+	p_rf_calibrate_info->remnant_cck_swing_idx = 0;
+	p_rf_calibrate_info->thermal_value = p_hal_data->eeprom_thermal_meter;
+
+	p_rf_calibrate_info->modify_tx_agc_value_cck = 0;			/* modify by Mingzhi.Guo */
+	p_rf_calibrate_info->modify_tx_agc_value_ofdm = 0;		/* modify by Mingzhi.Guo */
+
+}
+
+void
+odm_txpowertracking_callback_thermal_meter(
+#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
+	struct PHY_DM_STRUCT		*p_dm_odm
+#else
+	struct _ADAPTER	*adapter
+#endif
+)
+{
+
+#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
+	HAL_DATA_TYPE	*p_hal_data = GET_HAL_DATA(adapter);
+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
+	struct PHY_DM_STRUCT		*p_dm_odm = &p_hal_data->DM_OutSrc;
+#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
+	struct PHY_DM_STRUCT		*p_dm_odm = &p_hal_data->odmpriv;
+#endif
+#endif
+
+	struct odm_rf_calibration_structure	*p_rf_calibrate_info = &(p_dm_odm->rf_calibrate_info);
+
+	u8			thermal_value = 0, delta, delta_LCK, delta_IQK, p = 0, i = 0;
+	s8			diff_DPK[4] = {0};
+	u8			thermal_value_avg_count = 0;
+	u32			thermal_value_avg = 0, regc80, regcd0, regcd4, regab4;
+
+	u8			OFDM_min_index = 0;  /* OFDM BB Swing should be less than +3.0dB, which is required by Arthur */
+	u8			indexforchannel = 0; /* get_right_chnl_place_for_iqk(p_hal_data->current_channel) */
+	u8			power_tracking_type = p_hal_data->rf_power_tracking_type;
+	u8			xtal_offset_eanble = 0;
+	s8			thermal_value_temp = 0;
+
+	struct _TXPWRTRACK_CFG	c;
+
+	/* 4 1. The following TWO tables decide the final index of OFDM/CCK swing table. */
+	u8			*delta_swing_table_idx_tup_a = NULL;
+	u8			*delta_swing_table_idx_tdown_a = NULL;
+	u8			*delta_swing_table_idx_tup_b = NULL;
+	u8			*delta_swing_table_idx_tdown_b = NULL;
+	/*for 8814 add by Yu Chen*/
+	u8			*delta_swing_table_idx_tup_c = NULL;
+	u8			*delta_swing_table_idx_tdown_c = NULL;
+	u8			*delta_swing_table_idx_tup_d = NULL;
+	u8			*delta_swing_table_idx_tdown_d = NULL;
+	/*for Xtal Offset by James.Tung*/
+	s8			*delta_swing_table_xtal_up = NULL;
+	s8			*delta_swing_table_xtal_down = NULL;
+
+	/* 4 2. Initilization ( 7 steps in total ) */
+
+	configure_txpower_track(p_dm_odm, &c);
+
+	(*c.get_delta_swing_table)(p_dm_odm, (u8 **)&delta_swing_table_idx_tup_a, (u8 **)&delta_swing_table_idx_tdown_a,
+		(u8 **)&delta_swing_table_idx_tup_b, (u8 **)&delta_swing_table_idx_tdown_b);
+
+	if (p_dm_odm->support_ic_type & ODM_RTL8814A)	/*for 8814 path C & D*/
+		(*c.get_delta_swing_table8814only)(p_dm_odm, (u8 **)&delta_swing_table_idx_tup_c, (u8 **)&delta_swing_table_idx_tdown_c,
+			(u8 **)&delta_swing_table_idx_tup_d, (u8 **)&delta_swing_table_idx_tdown_d);
+	/* JJ ADD 20161014 */
+	if (p_dm_odm->support_ic_type & (ODM_RTL8703B | ODM_RTL8723D | ODM_RTL8710B))	/*for Xtal Offset*/
+		(*c.get_delta_swing_xtal_table)(p_dm_odm, (s8 **)&delta_swing_table_xtal_up, (s8 **)&delta_swing_table_xtal_down);
+
+	p_rf_calibrate_info->txpowertracking_callback_cnt++;	/*cosa add for debug*/
+	p_rf_calibrate_info->is_txpowertracking_init = true;
+
+	/*p_rf_calibrate_info->txpowertrack_control = p_hal_data->txpowertrack_control;
+	<Kordan> We should keep updating the control variable according to HalData.
+	<Kordan> rf_calibrate_info.rega24 will be initialized when ODM HW configuring, but MP configures with para files. */
+#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
+#if (MP_DRIVER == 1)
+	p_rf_calibrate_info->rega24 = 0x090e1317;
+#endif
+#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
+	if (p_dm_odm->mp_mode == true)
+		p_rf_calibrate_info->rega24 = 0x090e1317;
+#endif
+
+	ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
+		("===>odm_txpowertracking_callback_thermal_meter\n p_rf_calibrate_info->bb_swing_idx_cck_base: %d, p_rf_calibrate_info->bb_swing_idx_ofdm_base[A]: %d, p_rf_calibrate_info->default_ofdm_index: %d\n",
+		p_rf_calibrate_info->bb_swing_idx_cck_base, p_rf_calibrate_info->bb_swing_idx_ofdm_base[ODM_RF_PATH_A], p_rf_calibrate_info->default_ofdm_index));
+
+	ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
+		("p_rf_calibrate_info->txpowertrack_control=%d,  p_hal_data->eeprom_thermal_meter %d\n", p_rf_calibrate_info->txpowertrack_control,  p_hal_data->eeprom_thermal_meter));
+	thermal_value = (u8)odm_get_rf_reg(p_dm_odm, ODM_RF_PATH_A, c.thermal_reg_addr, 0xfc00);	/* 0x42: RF Reg[15:10] 88E */
+
+	thermal_value_temp = thermal_value + phydm_get_thermal_offset(p_dm_odm);
+
+	ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
+		("thermal_value_temp(%d) thermal_value(%d) power_time_thermal(%d)\n", thermal_value_temp, thermal_value, phydm_get_thermal_offset(p_dm_odm)));
+
+	if (thermal_value_temp > 63)
+		thermal_value = 63;
+	else if (thermal_value_temp < 0)
+		thermal_value = 0;
+	else
+		thermal_value = thermal_value_temp;
+
+	/*add log by zhao he, check c80/c94/c14/ca0 value*/
+	if (p_dm_odm->support_ic_type == ODM_RTL8723D) {
+		regc80 = odm_get_bb_reg(p_dm_odm, 0xc80, MASKDWORD);
+		regcd0 = odm_get_bb_reg(p_dm_odm, 0xcd0, MASKDWORD);
+		regcd4 = odm_get_bb_reg(p_dm_odm, 0xcd4, MASKDWORD);
+		regab4 = odm_get_bb_reg(p_dm_odm, 0xab4, 0x000007FF);
+		ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xc80 = 0x%x 0xcd0 = 0x%x 0xcd4 = 0x%x 0xab4 = 0x%x\n", regc80, regcd0, regcd4, regab4));
+	}
+	/* JJ ADD 20161014 */
+	if (p_dm_odm->support_ic_type == ODM_RTL8710B) {
+		regc80 = odm_get_bb_reg(p_dm_odm, 0xc80, MASKDWORD);
+		regcd0 = odm_get_bb_reg(p_dm_odm, 0xcd0, MASKDWORD);
+		regcd4 = odm_get_bb_reg(p_dm_odm, 0xcd4, MASKDWORD);
+		regab4 = odm_get_bb_reg(p_dm_odm, 0xab4, 0x000007FF);
+		ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xc80 = 0x%x 0xcd0 = 0x%x 0xcd4 = 0x%x 0xab4 = 0x%x\n", regc80, regcd0, regcd4, regab4));
+	}
+
+	if (!p_rf_calibrate_info->txpowertrack_control)
+		return;
+
+	if (p_hal_data->eeprom_thermal_meter == 0xff) {
+		ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("no pg, p_hal_data->eeprom_thermal_meter = 0x%x\n", p_hal_data->eeprom_thermal_meter));
+		return;
+	}
+
+	/*4 3. Initialize ThermalValues of rf_calibrate_info*/
+
+	if (p_rf_calibrate_info->is_reloadtxpowerindex)
+		ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("reload ofdm index for band switch\n"));
+
+	/*4 4. Calculate average thermal meter*/
+
+	p_rf_calibrate_info->thermal_value_avg[p_rf_calibrate_info->thermal_value_avg_index] = thermal_value;
+	p_rf_calibrate_info->thermal_value_avg_index++;
+	if (p_rf_calibrate_info->thermal_value_avg_index == c.average_thermal_num)   /*Average times =  c.average_thermal_num*/
+		p_rf_calibrate_info->thermal_value_avg_index = 0;
+
+	for (i = 0; i < c.average_thermal_num; i++) {
+		if (p_rf_calibrate_info->thermal_value_avg[i]) {
+			thermal_value_avg += p_rf_calibrate_info->thermal_value_avg[i];
+			thermal_value_avg_count++;
+		}
+	}
+
+	if (thermal_value_avg_count) {            /* Calculate Average thermal_value after average enough times */
+		thermal_value = (u8)(thermal_value_avg / thermal_value_avg_count);
+		p_rf_calibrate_info->thermal_value_delta = thermal_value - p_hal_data->eeprom_thermal_meter;
+		ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
+			("AVG Thermal Meter = 0x%X, EFUSE Thermal base = 0x%X\n", thermal_value, p_hal_data->eeprom_thermal_meter));
+	}
+
+	/* 4 5. Calculate delta, delta_LCK, delta_IQK. */
+
+	/* "delta" here is used to determine whether thermal value changes or not. */
+	delta	= (thermal_value > p_rf_calibrate_info->thermal_value) ? (thermal_value - p_rf_calibrate_info->thermal_value) : (p_rf_calibrate_info->thermal_value - thermal_value);
+	delta_LCK = (thermal_value > p_rf_calibrate_info->thermal_value_lck) ? (thermal_value - p_rf_calibrate_info->thermal_value_lck) : (p_rf_calibrate_info->thermal_value_lck - thermal_value);
+	delta_IQK = (thermal_value > p_rf_calibrate_info->thermal_value_iqk) ? (thermal_value - p_rf_calibrate_info->thermal_value_iqk) : (p_rf_calibrate_info->thermal_value_iqk - thermal_value);
+
+	if (p_rf_calibrate_info->thermal_value_iqk == 0xff) {	/*no PG, use thermal value for IQK*/
+		p_rf_calibrate_info->thermal_value_iqk = thermal_value;
+		delta_IQK = (thermal_value > p_rf_calibrate_info->thermal_value_iqk) ? (thermal_value - p_rf_calibrate_info->thermal_value_iqk) : (p_rf_calibrate_info->thermal_value_iqk - thermal_value);
+		ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("no PG, use thermal_value for IQK\n"));
+	}
+
+	for (p = ODM_RF_PATH_A; p < c.rf_path_count; p++)
+		diff_DPK[p] = (s8)thermal_value - (s8)p_rf_calibrate_info->dpk_thermal[p];
+
+	/*4 6. If necessary, do LCK.*/
+
+	if (!(p_dm_odm->support_ic_type & ODM_RTL8821)) {	/*no PG, do LCK at initial status*/
+		if (p_rf_calibrate_info->thermal_value_lck == 0xff) {
+			ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("no PG, do LCK\n"));
+			p_rf_calibrate_info->thermal_value_lck = thermal_value;
+
+			/*Use RTLCK, so close power tracking driver LCK*/
+			if ((!(p_dm_odm->support_ic_type & ODM_RTL8814A)) && (!(p_dm_odm->support_ic_type & ODM_RTL8822B))) {
+				if (c.phy_lc_calibrate)
+					(*c.phy_lc_calibrate)(p_dm_odm);
+			}
+
+			delta_LCK = (thermal_value > p_rf_calibrate_info->thermal_value_lck) ? (thermal_value - p_rf_calibrate_info->thermal_value_lck) : (p_rf_calibrate_info->thermal_value_lck - thermal_value);
+		}
+
+		ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("(delta, delta_LCK, delta_IQK) = (%d, %d, %d)\n", delta, delta_LCK, delta_IQK));
+
+		/* Wait sacn to do LCK by RF Jenyu*/
+		if (*p_dm_odm->p_is_scan_in_process == false) {
+			/* Delta temperature is equal to or larger than 20 centigrade.*/
+			if (delta_LCK >= c.threshold_iqk) {
+				ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("delta_LCK(%d) >= threshold_iqk(%d)\n", delta_LCK, c.threshold_iqk));
+				p_rf_calibrate_info->thermal_value_lck = thermal_value;
+
+				/*Use RTLCK, so close power tracking driver LCK*/
+				if ((!(p_dm_odm->support_ic_type & ODM_RTL8814A)) && (!(p_dm_odm->support_ic_type & ODM_RTL8822B))) {
+					if (c.phy_lc_calibrate)
+						(*c.phy_lc_calibrate)(p_dm_odm);
+				}
+			}
+		}
+	}
+
+	/*3 7. If necessary, move the index of swing table to adjust Tx power.*/
+
+	if (delta > 0 && p_rf_calibrate_info->txpowertrack_control) {
+		/* "delta" here is used to record the absolute value of differrence. */
+#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
+		delta = thermal_value > p_hal_data->eeprom_thermal_meter ? (thermal_value - p_hal_data->eeprom_thermal_meter) : (p_hal_data->eeprom_thermal_meter - thermal_value);
+#else
+		delta = (thermal_value > p_dm_odm->priv->pmib->dot11RFEntry.ther) ? (thermal_value - p_dm_odm->priv->pmib->dot11RFEntry.ther) : (p_dm_odm->priv->pmib->dot11RFEntry.ther - thermal_value);
+#endif
+		if (delta >= TXPWR_TRACK_TABLE_SIZE)
+			delta = TXPWR_TRACK_TABLE_SIZE - 1;
+
+		/*4 7.1 The Final Power index = BaseIndex + power_index_offset*/
+
+#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
+		if (thermal_value > p_hal_data->eeprom_thermal_meter) {
+#else
+		if (thermal_value > p_dm_odm->priv->pmib->dot11RFEntry.ther) {
+#endif
+
+			for (p = ODM_RF_PATH_A; p < c.rf_path_count; p++) {
+				p_rf_calibrate_info->delta_power_index_last[p] = p_rf_calibrate_info->delta_power_index[p];	/*recording poer index offset*/
+				switch (p) {
+				case ODM_RF_PATH_B:
+					ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
+						("delta_swing_table_idx_tup_b[%d] = %d\n", delta, delta_swing_table_idx_tup_b[delta]));
+
+					p_rf_calibrate_info->delta_power_index[p] = delta_swing_table_idx_tup_b[delta];
+					p_rf_calibrate_info->absolute_ofdm_swing_idx[p] =  delta_swing_table_idx_tup_b[delta];       /*Record delta swing for mix mode power tracking*/
+					ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
+						("******Temp is higher and p_rf_calibrate_info->absolute_ofdm_swing_idx[ODM_RF_PATH_B] = %d\n", p_rf_calibrate_info->absolute_ofdm_swing_idx[p]));
+					break;
+
+				case ODM_RF_PATH_C:
+					ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
+						("delta_swing_table_idx_tup_c[%d] = %d\n", delta, delta_swing_table_idx_tup_c[delta]));
+
+					p_rf_calibrate_info->delta_power_index[p] = delta_swing_table_idx_tup_c[delta];
+					p_rf_calibrate_info->absolute_ofdm_swing_idx[p] =  delta_swing_table_idx_tup_c[delta];       /*Record delta swing for mix mode power tracking*/
+					ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
+						("******Temp is higher and p_rf_calibrate_info->absolute_ofdm_swing_idx[ODM_RF_PATH_C] = %d\n", p_rf_calibrate_info->absolute_ofdm_swing_idx[p]));
+					break;
+
+				case ODM_RF_PATH_D:
+					ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
+						("delta_swing_table_idx_tup_d[%d] = %d\n", delta, delta_swing_table_idx_tup_d[delta]));
+
+					p_rf_calibrate_info->delta_power_index[p] = delta_swing_table_idx_tup_d[delta];
+					p_rf_calibrate_info->absolute_ofdm_swing_idx[p] =  delta_swing_table_idx_tup_d[delta];       /*Record delta swing for mix mode power tracking*/
+					ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
+						("******Temp is higher and p_rf_calibrate_info->absolute_ofdm_swing_idx[ODM_RF_PATH_D] = %d\n", p_rf_calibrate_info->absolute_ofdm_swing_idx[p]));
+					break;
+
+				default:
+					ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
+						("delta_swing_table_idx_tup_a[%d] = %d\n", delta, delta_swing_table_idx_tup_a[delta]));
+
+					p_rf_calibrate_info->delta_power_index[p] = delta_swing_table_idx_tup_a[delta];
+					p_rf_calibrate_info->absolute_ofdm_swing_idx[p] =  delta_swing_table_idx_tup_a[delta];        /*Record delta swing for mix mode power tracking*/
+					ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
+						("******Temp is higher and p_rf_calibrate_info->absolute_ofdm_swing_idx[ODM_RF_PATH_A] = %d\n", p_rf_calibrate_info->absolute_ofdm_swing_idx[p]));
+					break;
+				}
+			}
+			/* JJ ADD 20161014 */
+			if (p_dm_odm->support_ic_type & (ODM_RTL8703B | ODM_RTL8723D | ODM_RTL8710B)) {
+				/*Save xtal_offset from Xtal table*/
+				p_rf_calibrate_info->xtal_offset_last = p_rf_calibrate_info->xtal_offset;	/*recording last Xtal offset*/
+				ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
+					("[Xtal] delta_swing_table_xtal_up[%d] = %d\n", delta, delta_swing_table_xtal_up[delta]));
+				p_rf_calibrate_info->xtal_offset = delta_swing_table_xtal_up[delta];
+
+				if (p_rf_calibrate_info->xtal_offset_last == p_rf_calibrate_info->xtal_offset)
+					xtal_offset_eanble = 0;
+				else
+					xtal_offset_eanble = 1;
+			}
+
+		} else {
+			for (p = ODM_RF_PATH_A; p < c.rf_path_count; p++) {
+				p_rf_calibrate_info->delta_power_index_last[p] = p_rf_calibrate_info->delta_power_index[p];	/*recording poer index offset*/
+
+				switch (p) {
+				case ODM_RF_PATH_B:
+					ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
+						("delta_swing_table_idx_tdown_b[%d] = %d\n", delta, delta_swing_table_idx_tdown_b[delta]));
+					p_rf_calibrate_info->delta_power_index[p] = -1 * delta_swing_table_idx_tdown_b[delta];
+					p_rf_calibrate_info->absolute_ofdm_swing_idx[p] =  -1 * delta_swing_table_idx_tdown_b[delta];        /*Record delta swing for mix mode power tracking*/
+					ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
+						("******Temp is lower and p_rf_calibrate_info->absolute_ofdm_swing_idx[ODM_RF_PATH_B] = %d\n", p_rf_calibrate_info->absolute_ofdm_swing_idx[p]));
+					break;
+
+				case ODM_RF_PATH_C:
+					ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
+						("delta_swing_table_idx_tdown_c[%d] = %d\n", delta, delta_swing_table_idx_tdown_c[delta]));
+					p_rf_calibrate_info->delta_power_index[p] = -1 * delta_swing_table_idx_tdown_c[delta];
+					p_rf_calibrate_info->absolute_ofdm_swing_idx[p] =  -1 * delta_swing_table_idx_tdown_c[delta];        /*Record delta swing for mix mode power tracking*/
+					ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
+						("******Temp is lower and p_rf_calibrate_info->absolute_ofdm_swing_idx[ODM_RF_PATH_C] = %d\n", p_rf_calibrate_info->absolute_ofdm_swing_idx[p]));
+					break;
+
+				case ODM_RF_PATH_D:
+					ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
+						("delta_swing_table_idx_tdown_d[%d] = %d\n", delta, delta_swing_table_idx_tdown_d[delta]));
+					p_rf_calibrate_info->delta_power_index[p] = -1 * delta_swing_table_idx_tdown_d[delta];
+					p_rf_calibrate_info->absolute_ofdm_swing_idx[p] =  -1 * delta_swing_table_idx_tdown_d[delta];        /*Record delta swing for mix mode power tracking*/
+					ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
+						("******Temp is lower and p_rf_calibrate_info->absolute_ofdm_swing_idx[ODM_RF_PATH_D] = %d\n", p_rf_calibrate_info->absolute_ofdm_swing_idx[p]));
+					break;
+
+				default:
+					ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
+						("delta_swing_table_idx_tdown_a[%d] = %d\n", delta, delta_swing_table_idx_tdown_a[delta]));
+					p_rf_calibrate_info->delta_power_index[p] = -1 * delta_swing_table_idx_tdown_a[delta];
+					p_rf_calibrate_info->absolute_ofdm_swing_idx[p] =  -1 * delta_swing_table_idx_tdown_a[delta];        /*Record delta swing for mix mode power tracking*/
+					ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
+						("******Temp is lower and p_rf_calibrate_info->absolute_ofdm_swing_idx[ODM_RF_PATH_A] = %d\n", p_rf_calibrate_info->absolute_ofdm_swing_idx[p]));
+					break;
+				}
+			}
+			/* JJ ADD 20161014 */
+			if (p_dm_odm->support_ic_type & (ODM_RTL8703B | ODM_RTL8723D | ODM_RTL8710B)) {
+				/*Save xtal_offset from Xtal table*/
+				p_rf_calibrate_info->xtal_offset_last = p_rf_calibrate_info->xtal_offset;	/*recording last Xtal offset*/
+				ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
+					("[Xtal] delta_swing_table_xtal_down[%d] = %d\n", delta, delta_swing_table_xtal_down[delta]));
+				p_rf_calibrate_info->xtal_offset = delta_swing_table_xtal_down[delta];
+
+				if (p_rf_calibrate_info->xtal_offset_last == p_rf_calibrate_info->xtal_offset)
+					xtal_offset_eanble = 0;
+				else
+					xtal_offset_eanble = 1;
+			}
+
+		}
+
+		for (p = ODM_RF_PATH_A; p < c.rf_path_count; p++) {
+			ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
+				("\n\n=========================== [path-%d] Calculating power_index_offset===========================\n", p));
+
+			if (p_rf_calibrate_info->delta_power_index[p] == p_rf_calibrate_info->delta_power_index_last[p])         /*If Thermal value changes but lookup table value still the same*/
+				p_rf_calibrate_info->power_index_offset[p] = 0;
+			else
+				p_rf_calibrate_info->power_index_offset[p] = p_rf_calibrate_info->delta_power_index[p] - p_rf_calibrate_info->delta_power_index_last[p];      /*Power index diff between 2 times Power Tracking*/
+
+			ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
+				("[path-%d] power_index_offset(%d) = delta_power_index(%d) - delta_power_index_last(%d)\n", p, p_rf_calibrate_info->power_index_offset[p], p_rf_calibrate_info->delta_power_index[p], p_rf_calibrate_info->delta_power_index_last[p]));
+
+			p_rf_calibrate_info->OFDM_index[p] = p_rf_calibrate_info->bb_swing_idx_ofdm_base[p] + p_rf_calibrate_info->power_index_offset[p];
+			p_rf_calibrate_info->CCK_index = p_rf_calibrate_info->bb_swing_idx_cck_base + p_rf_calibrate_info->power_index_offset[p];
+
+			p_rf_calibrate_info->bb_swing_idx_cck = p_rf_calibrate_info->CCK_index;
+			p_rf_calibrate_info->bb_swing_idx_ofdm[p] = p_rf_calibrate_info->OFDM_index[p];
+
+			/*************Print BB Swing base and index Offset*************/
+
+			ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
+				("The 'CCK' final index(%d) = BaseIndex(%d) + power_index_offset(%d)\n", p_rf_calibrate_info->bb_swing_idx_cck, p_rf_calibrate_info->bb_swing_idx_cck_base, p_rf_calibrate_info->power_index_offset[p]));
+			ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
+				("The 'OFDM' final index(%d) = BaseIndex[%d](%d) + power_index_offset(%d)\n", p_rf_calibrate_info->bb_swing_idx_ofdm[p], p, p_rf_calibrate_info->bb_swing_idx_ofdm_base[p], p_rf_calibrate_info->power_index_offset[p]));
+
+			/*4 7.1 Handle boundary conditions of index.*/
+
+			if (p_rf_calibrate_info->OFDM_index[p] > c.swing_table_size_ofdm - 1)
+				p_rf_calibrate_info->OFDM_index[p] = c.swing_table_size_ofdm - 1;
+			else if (p_rf_calibrate_info->OFDM_index[p] <= OFDM_min_index)
+				p_rf_calibrate_info->OFDM_index[p] = OFDM_min_index;
+		}
+
+		ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
+			("\n\n========================================================================================================\n"));
+
+		if (p_rf_calibrate_info->CCK_index > c.swing_table_size_cck - 1)
+			p_rf_calibrate_info->CCK_index = c.swing_table_size_cck - 1;
+		else if (p_rf_calibrate_info->CCK_index <= 0)
+			p_rf_calibrate_info->CCK_index = 0;
+	} else {
+		ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
+			("The thermal meter is unchanged or TxPowerTracking OFF(%d): thermal_value: %d, p_rf_calibrate_info->thermal_value: %d\n",
+			p_rf_calibrate_info->txpowertrack_control, thermal_value, p_rf_calibrate_info->thermal_value));
+
+		for (p = ODM_RF_PATH_A; p < c.rf_path_count; p++)
+			p_rf_calibrate_info->power_index_offset[p] = 0;
+	}
+
+	ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
+		("TxPowerTracking: [CCK] Swing Current index: %d, Swing base index: %d\n",
+		p_rf_calibrate_info->CCK_index, p_rf_calibrate_info->bb_swing_idx_cck_base));       /*Print Swing base & current*/
+
+	for (p = ODM_RF_PATH_A; p < c.rf_path_count; p++) {
+		ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
+			("TxPowerTracking: [OFDM] Swing Current index: %d, Swing base index[%d]: %d\n",
+			p_rf_calibrate_info->OFDM_index[p], p, p_rf_calibrate_info->bb_swing_idx_ofdm_base[p]));
+	}
+
+	if ((p_dm_odm->support_ic_type & ODM_RTL8814A)) {
+		ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("power_tracking_type=%d\n", power_tracking_type));
+
+		if (power_tracking_type == 0) {
+			ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("**********Enter POWER Tracking MIX_MODE**********\n"));
+			for (p = ODM_RF_PATH_A; p < c.rf_path_count; p++)
+				(*c.odm_tx_pwr_track_set_pwr)(p_dm_odm, MIX_MODE, p, 0);
+		} else if (power_tracking_type == 1) {
+			ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("**********Enter POWER Tracking MIX(2G) TSSI(5G) MODE**********\n"));
+			for (p = ODM_RF_PATH_A; p < c.rf_path_count; p++)
+				(*c.odm_tx_pwr_track_set_pwr)(p_dm_odm, MIX_2G_TSSI_5G_MODE, p, 0);
+		} else if (power_tracking_type == 2) {
+			ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("**********Enter POWER Tracking MIX(5G) TSSI(2G)MODE**********\n"));
+			for (p = ODM_RF_PATH_A; p < c.rf_path_count; p++)
+				(*c.odm_tx_pwr_track_set_pwr)(p_dm_odm, MIX_5G_TSSI_2G_MODE, p, 0);
+		} else if (power_tracking_type == 3) {
+			ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("**********Enter POWER Tracking TSSI MODE**********\n"));
+			for (p = ODM_RF_PATH_A; p < c.rf_path_count; p++)
+				(*c.odm_tx_pwr_track_set_pwr)(p_dm_odm, TSSI_MODE, p, 0);
+		}
+		p_rf_calibrate_info->thermal_value = thermal_value;         /*Record last Power Tracking Thermal value*/
+
+	} else if ((p_rf_calibrate_info->power_index_offset[ODM_RF_PATH_A] != 0 ||
+		p_rf_calibrate_info->power_index_offset[ODM_RF_PATH_B] != 0 ||
+		p_rf_calibrate_info->power_index_offset[ODM_RF_PATH_C] != 0 ||
+		p_rf_calibrate_info->power_index_offset[ODM_RF_PATH_D] != 0) &&
+		p_rf_calibrate_info->txpowertrack_control && (p_hal_data->eeprom_thermal_meter != 0xff)) {
+		/* 4 7.2 Configure the Swing Table to adjust Tx Power. */
+
+		p_rf_calibrate_info->is_tx_power_changed = true;	/*Always true after Tx Power is adjusted by power tracking.*/
+		/*  */
+		/* 2012/04/23 MH According to Luke's suggestion, we can not write BB digital */
+		/* to increase TX power. Otherwise, EVM will be bad. */
+		/*  */
+		/* 2012/04/25 MH Add for tx power tracking to set tx power in tx agc for 88E. */
+		if (thermal_value > p_rf_calibrate_info->thermal_value) {
+			for (p = ODM_RF_PATH_A; p < c.rf_path_count; p++) {
+				ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
+					("Temperature Increasing(%d): delta_pi: %d, delta_t: %d, Now_t: %d, EFUSE_t: %d, Last_t: %d\n",
+					p, p_rf_calibrate_info->power_index_offset[p], delta, thermal_value, p_hal_data->eeprom_thermal_meter, p_rf_calibrate_info->thermal_value));
+			}
+		} else if (thermal_value < p_rf_calibrate_info->thermal_value) {	/*Low temperature*/
+			for (p = ODM_RF_PATH_A; p < c.rf_path_count; p++) {
+				ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
+					("Temperature Decreasing(%d): delta_pi: %d, delta_t: %d, Now_t: %d, EFUSE_t: %d, Last_t: %d\n",
+					p, p_rf_calibrate_info->power_index_offset[p], delta, thermal_value, p_hal_data->eeprom_thermal_meter, p_rf_calibrate_info->thermal_value));
+			}
+		}
+
+#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
+		if (thermal_value > p_hal_data->eeprom_thermal_meter)
+#else
+		if (thermal_value > p_dm_odm->priv->pmib->dot11RFEntry.ther)
+#endif
+		{
+			ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
+				("Temperature(%d) higher than PG value(%d)\n", thermal_value, p_hal_data->eeprom_thermal_meter));
+
+			if (p_dm_odm->support_ic_type == ODM_RTL8188E || p_dm_odm->support_ic_type == ODM_RTL8192E || p_dm_odm->support_ic_type == ODM_RTL8821 ||
+			    p_dm_odm->support_ic_type == ODM_RTL8812 || p_dm_odm->support_ic_type == ODM_RTL8723B || p_dm_odm->support_ic_type == ODM_RTL8814A ||
+			    p_dm_odm->support_ic_type == ODM_RTL8703B || p_dm_odm->support_ic_type == ODM_RTL8188F || p_dm_odm->support_ic_type == ODM_RTL8822B ||
+			    p_dm_odm->support_ic_type == ODM_RTL8723D || p_dm_odm->support_ic_type == ODM_RTL8821C || p_dm_odm->support_ic_type == ODM_RTL8710B) {/* JJ ADD 20161014 */
+
+				ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("**********Enter POWER Tracking MIX_MODE**********\n"));
+				for (p = ODM_RF_PATH_A; p < c.rf_path_count; p++)
+					(*c.odm_tx_pwr_track_set_pwr)(p_dm_odm, MIX_MODE, p, 0);
+			} else {
+				ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("**********Enter POWER Tracking BBSWING_MODE**********\n"));
+				for (p = ODM_RF_PATH_A; p < c.rf_path_count; p++)
+					(*c.odm_tx_pwr_track_set_pwr)(p_dm_odm, BBSWING, p, indexforchannel);
+			}
+		} else {
+			ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
+				("Temperature(%d) lower than PG value(%d)\n", thermal_value, p_hal_data->eeprom_thermal_meter));
+
+			if (p_dm_odm->support_ic_type == ODM_RTL8188E || p_dm_odm->support_ic_type == ODM_RTL8192E || p_dm_odm->support_ic_type == ODM_RTL8821 ||
+			    p_dm_odm->support_ic_type == ODM_RTL8812 || p_dm_odm->support_ic_type == ODM_RTL8723B || p_dm_odm->support_ic_type == ODM_RTL8814A ||
+			    p_dm_odm->support_ic_type == ODM_RTL8703B || p_dm_odm->support_ic_type == ODM_RTL8188F || p_dm_odm->support_ic_type == ODM_RTL8822B ||
+			    p_dm_odm->support_ic_type == ODM_RTL8723D || p_dm_odm->support_ic_type == ODM_RTL8821C || p_dm_odm->support_ic_type == ODM_RTL8710B) {/* JJ ADD 20161014 */
+
+				ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("**********Enter POWER Tracking MIX_MODE**********\n"));
+				for (p = ODM_RF_PATH_A; p < c.rf_path_count; p++)
+					(*c.odm_tx_pwr_track_set_pwr)(p_dm_odm, MIX_MODE, p, indexforchannel);
+			} else {
+				ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("**********Enter POWER Tracking BBSWING_MODE**********\n"));
+				for (p = ODM_RF_PATH_A; p < c.rf_path_count; p++)
+					(*c.odm_tx_pwr_track_set_pwr)(p_dm_odm, BBSWING, p, indexforchannel);
+			}
+
+		}
+
+		p_rf_calibrate_info->bb_swing_idx_cck_base = p_rf_calibrate_info->bb_swing_idx_cck;    /*Record last time Power Tracking result as base.*/
+		for (p = ODM_RF_PATH_A; p < c.rf_path_count; p++)
+			p_rf_calibrate_info->bb_swing_idx_ofdm_base[p] = p_rf_calibrate_info->bb_swing_idx_ofdm[p];
+
+		ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
+			("p_rf_calibrate_info->thermal_value = %d thermal_value= %d\n", p_rf_calibrate_info->thermal_value, thermal_value));
+
+		p_rf_calibrate_info->thermal_value = thermal_value;         /*Record last Power Tracking Thermal value*/
+
+	}
+
+
+	if (p_dm_odm->support_ic_type == ODM_RTL8703B || p_dm_odm->support_ic_type == ODM_RTL8723D || p_dm_odm->support_ic_type == ODM_RTL8710B) {/* JJ ADD 20161014 */
+
+		if (xtal_offset_eanble != 0 && p_rf_calibrate_info->txpowertrack_control && (p_hal_data->eeprom_thermal_meter != 0xff)) {
+
+			ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("**********Enter Xtal Tracking**********\n"));
+
+#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
+			if (thermal_value > p_hal_data->eeprom_thermal_meter) {
+#else
+			if (thermal_value > p_dm_odm->priv->pmib->dot11RFEntry.ther) {
+#endif
+				ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
+					("Temperature(%d) higher than PG value(%d)\n", thermal_value, p_hal_data->eeprom_thermal_meter));
+				(*c.odm_txxtaltrack_set_xtal)(p_dm_odm);
+			} else {
+				ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
+					("Temperature(%d) lower than PG value(%d)\n", thermal_value, p_hal_data->eeprom_thermal_meter));
+				(*c.odm_txxtaltrack_set_xtal)(p_dm_odm);
+			}
+		}
+		ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("**********End Xtal Tracking**********\n"));
+	}
+
+#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
+
+	/* Wait sacn to do IQK by RF Jenyu*/
+	if (*p_dm_odm->p_is_scan_in_process == false) {
+		if (!IS_HARDWARE_TYPE_8723B(adapter)) {
+			/*Delta temperature is equal to or larger than 20 centigrade (When threshold is 8).*/
+			if (delta_IQK >= c.threshold_iqk) {
+				p_rf_calibrate_info->thermal_value_iqk = thermal_value;
+				ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("delta_IQK(%d) >= threshold_iqk(%d)\n", delta_IQK, c.threshold_iqk));
+				if (!p_rf_calibrate_info->is_iqk_in_progress)
+					(*c.do_iqk)(p_dm_odm, delta_IQK, thermal_value, 8);
+			}
+		}
+	}
+	if (p_rf_calibrate_info->dpk_thermal[ODM_RF_PATH_A] != 0) {
+		if (diff_DPK[ODM_RF_PATH_A] >= c.threshold_dpk) {
+			odm_set_bb_reg(p_dm_odm, 0x82c, BIT(31), 0x1);
+			odm_set_bb_reg(p_dm_odm, 0xcc4, BIT(14) | BIT(13) | BIT(12) | BIT(11) | BIT(10), (diff_DPK[ODM_RF_PATH_A] / c.threshold_dpk));
+			odm_set_bb_reg(p_dm_odm, 0x82c, BIT(31), 0x0);
+		} else if ((diff_DPK[ODM_RF_PATH_A] <= -1 * c.threshold_dpk)) {
+			s32 value = 0x20 + (diff_DPK[ODM_RF_PATH_A] / c.threshold_dpk);
+
+			odm_set_bb_reg(p_dm_odm, 0x82c, BIT(31), 0x1);
+			odm_set_bb_reg(p_dm_odm, 0xcc4, BIT(14) | BIT(13) | BIT(12) | BIT(11) | BIT(10), value);
+			odm_set_bb_reg(p_dm_odm, 0x82c, BIT(31), 0x0);
+		} else {
+			odm_set_bb_reg(p_dm_odm, 0x82c, BIT(31), 0x1);
+			odm_set_bb_reg(p_dm_odm, 0xcc4, BIT(14) | BIT(13) | BIT(12) | BIT(11) | BIT(10), 0);
+			odm_set_bb_reg(p_dm_odm, 0x82c, BIT(31), 0x0);
+		}
+	}
+	if (p_rf_calibrate_info->dpk_thermal[ODM_RF_PATH_B] != 0) {
+		if (diff_DPK[ODM_RF_PATH_B] >= c.threshold_dpk) {
+			odm_set_bb_reg(p_dm_odm, 0x82c, BIT(31), 0x1);
+			odm_set_bb_reg(p_dm_odm, 0xec4, BIT(14) | BIT(13) | BIT(12) | BIT(11) | BIT(10), (diff_DPK[ODM_RF_PATH_B] / c.threshold_dpk));
+			odm_set_bb_reg(p_dm_odm, 0x82c, BIT(31), 0x0);
+		} else if ((diff_DPK[ODM_RF_PATH_B] <= -1 * c.threshold_dpk)) {
+			s32 value = 0x20 + (diff_DPK[ODM_RF_PATH_B] / c.threshold_dpk);
+
+			odm_set_bb_reg(p_dm_odm, 0x82c, BIT(31), 0x1);
+			odm_set_bb_reg(p_dm_odm, 0xec4, BIT(14) | BIT(13) | BIT(12) | BIT(11) | BIT(10), value);
+			odm_set_bb_reg(p_dm_odm, 0x82c, BIT(31), 0x0);
+		} else {
+			odm_set_bb_reg(p_dm_odm, 0x82c, BIT(31), 0x1);
+			odm_set_bb_reg(p_dm_odm, 0xec4, BIT(14) | BIT(13) | BIT(12) | BIT(11) | BIT(10), 0);
+			odm_set_bb_reg(p_dm_odm, 0x82c, BIT(31), 0x0);
+		}
+	}
+
+#endif
+
+	ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("<===odm_txpowertracking_callback_thermal_meter\n"));
+
+	p_rf_calibrate_info->tx_powercount = 0;
+}
+
+
+
+/* 3============================================================
+ * 3 IQ Calibration
+ * 3============================================================ */
+
+void
+odm_reset_iqk_result(
+	void					*p_dm_void
+)
+{
+	return;
+}
+#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
+u8 odm_get_right_chnl_place_for_iqk(u8 chnl)
+{
+	u8	channel_all[ODM_TARGET_CHNL_NUM_2G_5G] = {
+		1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 36, 38, 40, 42, 44, 46, 48, 50, 52, 54, 56, 58, 60, 62, 64, 100, 102, 104, 106, 108, 110, 112, 114, 116, 118, 120, 122, 124, 126, 128, 130, 132, 134, 136, 138, 140, 149, 151, 153, 155, 157, 159, 161, 163, 165
+	};
+	u8	place = chnl;
+
+
+	if (chnl > 14) {
+		for (place = 14; place < sizeof(channel_all); place++) {
+			if (channel_all[place] == chnl)
+				return place - 13;
+		}
+	}
+	return 0;
+
+}
+#endif
+
+void
+odm_iq_calibrate(
+	struct PHY_DM_STRUCT	*p_dm_odm
+)
+{
+	struct _ADAPTER	*adapter = p_dm_odm->adapter;
+
+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
+	if (*p_dm_odm->p_is_fcs_mode_enable)
+		return;
+#endif
+
+#if (DM_ODM_SUPPORT_TYPE & (ODM_CE))
+	if (IS_HARDWARE_TYPE_8812AU(adapter))
+		return;
+#endif
+
+	if (p_dm_odm->is_linked) {
+		if ((*p_dm_odm->p_channel != p_dm_odm->pre_channel) && (!*p_dm_odm->p_is_scan_in_process)) {
+			p_dm_odm->pre_channel = *p_dm_odm->p_channel;
+			p_dm_odm->linked_interval = 0;
+		}
+
+		if (p_dm_odm->linked_interval < 3)
+			p_dm_odm->linked_interval++;
+
+		if (p_dm_odm->linked_interval == 2) {
+			if (IS_HARDWARE_TYPE_8814A(adapter)) {
+#if (RTL8814A_SUPPORT == 1)
+				phy_iq_calibrate_8814a(p_dm_odm, false);
+#endif
+			}
+
+#if (RTL8822B_SUPPORT == 1)
+			else if (IS_HARDWARE_TYPE_8822B(adapter))
+				phy_iq_calibrate_8822b(p_dm_odm, false);
+#endif
+
+#if (RTL8821C_SUPPORT == 1)
+			else if (IS_HARDWARE_TYPE_8821C(adapter))
+				phy_iq_calibrate_8821c(p_dm_odm, false);
+#endif
+
+#if (RTL8821A_SUPPORT == 1)
+			else if (IS_HARDWARE_TYPE_8821(adapter))
+				phy_iq_calibrate_8821a(p_dm_odm, false);
+#endif
+		}
+	} else
+		p_dm_odm->linked_interval = 0;
+}
+
+void phydm_rf_init(void		*p_dm_void)
+{
+	struct PHY_DM_STRUCT		*p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
+	odm_txpowertracking_init(p_dm_odm);
+
+#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
+	odm_clear_txpowertracking_state(p_dm_odm);
+#endif
+
+#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
+#if (RTL8814A_SUPPORT == 1)
+	if (p_dm_odm->support_ic_type & ODM_RTL8814A)
+		phy_iq_calibrate_8814a_init(p_dm_odm);
+#endif
+#endif
+
+}
+
+void phydm_rf_watchdog(void		*p_dm_void)
+{
+	struct PHY_DM_STRUCT		*p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
+#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
+	odm_txpowertracking_check(p_dm_odm);
+	/*if (p_dm_odm->support_ic_type & ODM_IC_11AC_SERIES)*/
+		/*odm_iq_calibrate(p_dm_odm);*/
+#endif
+}
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/halphyrf_ce.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/halphyrf_ce.h
--- linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/halphyrf_ce.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/halphyrf_ce.h	2020-04-10 16:35:06.818660161 +0300
@@ -0,0 +1,117 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
+ *
+ *
+ ******************************************************************************/
+
+#ifndef __HAL_PHY_RF_H__
+#define __HAL_PHY_RF_H__
+
+#include "phydm_kfree.h"
+#if (RTL8814A_SUPPORT == 1)
+	#include "rtl8814a/phydm_iqk_8814a.h"
+#endif
+
+#if (RTL8822B_SUPPORT == 1)
+	#include "rtl8822b/phydm_iqk_8822b.h"
+#endif
+
+#if (RTL8821C_SUPPORT == 1)
+	#include "rtl8821c/phydm_iqk_8821c.h"
+#endif
+
+#include "phydm_powertracking_ce.h"
+
+
+enum spur_cal_method {
+	PLL_RESET,
+	AFE_PHASE_SEL
+};
+
+enum pwrtrack_method {
+	BBSWING,
+	TXAGC,
+	MIX_MODE,
+	TSSI_MODE,
+	MIX_2G_TSSI_5G_MODE,
+	MIX_5G_TSSI_2G_MODE
+};
+
+typedef void	(*func_set_pwr)(void *, enum pwrtrack_method, u8, u8);
+typedef void(*func_iqk)(void *, u8, u8, u8);
+typedef void	(*func_lck)(void *);
+typedef void	(*func_swing)(void *, u8 **, u8 **, u8 **, u8 **);
+typedef void	(*func_swing8814only)(void *, u8 **, u8 **, u8 **, u8 **);
+typedef void(*func_swing_xtal)(void *, s8 **, s8 **);
+typedef void(*func_set_xtal)(void *);
+
+struct _TXPWRTRACK_CFG {
+	u8		swing_table_size_cck;
+	u8		swing_table_size_ofdm;
+	u8		threshold_iqk;
+	u8		threshold_dpk;
+	u8		average_thermal_num;
+	u8		rf_path_count;
+	u32		thermal_reg_addr;
+	func_set_pwr	odm_tx_pwr_track_set_pwr;
+	func_iqk	do_iqk;
+	func_lck		phy_lc_calibrate;
+	func_swing	get_delta_swing_table;
+	func_swing8814only	get_delta_swing_table8814only;
+	func_swing_xtal			get_delta_swing_xtal_table;
+	func_set_xtal			odm_txxtaltrack_set_xtal;
+};
+
+void
+configure_txpower_track(
+	void					*p_dm_void,
+	struct _TXPWRTRACK_CFG	*p_config
+);
+
+
+void
+odm_clear_txpowertracking_state(
+	void					*p_dm_void
+);
+
+void
+odm_txpowertracking_callback_thermal_meter(
+#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
+	void					*p_dm_void
+#else
+	struct _ADAPTER	*adapter
+#endif
+);
+
+
+
+#define ODM_TARGET_CHNL_NUM_2G_5G	59
+
+
+void
+odm_reset_iqk_result(
+	void					*p_dm_void
+);
+u8
+odm_get_right_chnl_place_for_iqk(
+	u8 chnl
+);
+
+void phydm_rf_init(void					*p_dm_void);
+void phydm_rf_watchdog(void					*p_dm_void);
+
+#endif	/*  #ifndef __HAL_PHY_RF_H__ */
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/halphyrf_win.c linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/halphyrf_win.c
--- linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/halphyrf_win.c	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/halphyrf_win.c	2020-04-10 16:35:06.818660161 +0300
@@ -0,0 +1,821 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
+ *
+ *
+ ******************************************************************************/
+
+#include "mp_precomp.h"
+#include "phydm_precomp.h"
+
+#define	CALCULATE_SWINGTALBE_OFFSET(_offset, _direction, _size, _delta_thermal) \
+	do {\
+		for (_offset = 0; _offset < _size; _offset++) { \
+			\
+			if (_delta_thermal < thermal_threshold[_direction][_offset]) { \
+				\
+				if (_offset != 0)\
+					_offset--;\
+				break;\
+			} \
+		}			\
+		if (_offset >= _size)\
+			_offset = _size-1;\
+	} while (0)
+
+void configure_txpower_track(
+	struct PHY_DM_STRUCT		*p_dm_odm,
+	struct _TXPWRTRACK_CFG	*p_config
+)
+{
+#if RTL8192E_SUPPORT
+	if (p_dm_odm->support_ic_type == ODM_RTL8192E)
+		configure_txpower_track_8192e(p_config);
+#endif
+#if RTL8821A_SUPPORT
+	if (p_dm_odm->support_ic_type == ODM_RTL8821)
+		configure_txpower_track_8821a(p_config);
+#endif
+#if RTL8812A_SUPPORT
+	if (p_dm_odm->support_ic_type == ODM_RTL8812)
+		configure_txpower_track_8812a(p_config);
+#endif
+#if RTL8188E_SUPPORT
+	if (p_dm_odm->support_ic_type == ODM_RTL8188E)
+		configure_txpower_track_8188e(p_config);
+#endif
+
+#if RTL8188F_SUPPORT
+	if (p_dm_odm->support_ic_type == ODM_RTL8188F)
+		configure_txpower_track_8188f(p_config);
+#endif
+
+#if RTL8723B_SUPPORT
+	if (p_dm_odm->support_ic_type == ODM_RTL8723B)
+		configure_txpower_track_8723b(p_config);
+#endif
+
+#if RTL8814A_SUPPORT
+	if (p_dm_odm->support_ic_type == ODM_RTL8814A)
+		configure_txpower_track_8814a(p_config);
+#endif
+
+#if RTL8703B_SUPPORT
+	if (p_dm_odm->support_ic_type == ODM_RTL8703B)
+		configure_txpower_track_8703b(p_config);
+#endif
+
+#if RTL8822B_SUPPORT
+	if (p_dm_odm->support_ic_type == ODM_RTL8822B)
+		configure_txpower_track_8822b(p_config);
+#endif
+
+#if RTL8723D_SUPPORT
+	if (p_dm_odm->support_ic_type == ODM_RTL8723D)
+		configure_txpower_track_8723d(p_config);
+#endif
+
+/* JJ ADD 20161014 */
+#if RTL8710B_SUPPORT
+	if (p_dm_odm->support_ic_type == ODM_RTL8710B)
+		configure_txpower_track_8710b(p_config);
+#endif
+
+#if RTL8821C_SUPPORT
+	if (p_dm_odm->support_ic_type == ODM_RTL8821C)
+		configure_txpower_track_8821c(p_config);
+#endif
+
+}
+
+/* **********************************************************************
+ * <20121113, Kordan> This function should be called when tx_agc changed.
+ * Otherwise the previous compensation is gone, because we record the
+ * delta of temperature between two TxPowerTracking watch dogs.
+ *
+ * NOTE: If Tx BB swing or Tx scaling is varified during run-time, still
+ * need to call this function.
+ * ********************************************************************** */
+void
+odm_clear_txpowertracking_state(
+	struct PHY_DM_STRUCT		*p_dm_odm
+)
+{
+	PHAL_DATA_TYPE	p_hal_data = GET_HAL_DATA(p_dm_odm->adapter);
+	u8			p = 0;
+	struct odm_rf_calibration_structure	*p_rf_calibrate_info = &(p_dm_odm->rf_calibrate_info);
+
+	p_rf_calibrate_info->bb_swing_idx_cck_base = p_rf_calibrate_info->default_cck_index;
+	p_rf_calibrate_info->bb_swing_idx_cck = p_rf_calibrate_info->default_cck_index;
+	p_rf_calibrate_info->CCK_index = 0;
+
+	for (p = ODM_RF_PATH_A; p < MAX_RF_PATH; ++p) {
+		p_rf_calibrate_info->bb_swing_idx_ofdm_base[p] = p_rf_calibrate_info->default_ofdm_index;
+		p_rf_calibrate_info->bb_swing_idx_ofdm[p] = p_rf_calibrate_info->default_ofdm_index;
+		p_rf_calibrate_info->OFDM_index[p] = p_rf_calibrate_info->default_ofdm_index;
+
+		p_rf_calibrate_info->power_index_offset[p] = 0;
+		p_rf_calibrate_info->delta_power_index[p] = 0;
+		p_rf_calibrate_info->delta_power_index_last[p] = 0;
+
+		p_rf_calibrate_info->absolute_ofdm_swing_idx[p] = 0;    /* Initial Mix mode power tracking*/
+		p_rf_calibrate_info->remnant_ofdm_swing_idx[p] = 0;
+		p_rf_calibrate_info->kfree_offset[p] = 0;
+	}
+
+	p_rf_calibrate_info->modify_tx_agc_flag_path_a = false;       /*Initial at Modify Tx Scaling mode*/
+	p_rf_calibrate_info->modify_tx_agc_flag_path_b = false;       /*Initial at Modify Tx Scaling mode*/
+	p_rf_calibrate_info->modify_tx_agc_flag_path_c = false;       /*Initial at Modify Tx Scaling mode*/
+	p_rf_calibrate_info->modify_tx_agc_flag_path_d = false;       /*Initial at Modify Tx Scaling mode*/
+	p_rf_calibrate_info->remnant_cck_swing_idx = 0;
+	p_rf_calibrate_info->thermal_value = p_hal_data->eeprom_thermal_meter;
+
+	p_rf_calibrate_info->modify_tx_agc_value_cck = 0;			/* modify by Mingzhi.Guo */
+	p_rf_calibrate_info->modify_tx_agc_value_ofdm = 0;		/* modify by Mingzhi.Guo */
+
+}
+
+void
+odm_txpowertracking_callback_thermal_meter(
+#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
+	struct PHY_DM_STRUCT		*p_dm_odm
+#else
+	struct _ADAPTER	*adapter
+#endif
+)
+{
+#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
+	HAL_DATA_TYPE	*p_hal_data = GET_HAL_DATA(adapter);
+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
+	struct PHY_DM_STRUCT		*p_dm_odm = &p_hal_data->DM_OutSrc;
+#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
+	struct PHY_DM_STRUCT		*p_dm_odm = &p_hal_data->odmpriv;
+#endif
+#endif
+
+	struct odm_rf_calibration_structure	*p_rf_calibrate_info = &(p_dm_odm->rf_calibrate_info);
+
+	u8			thermal_value = 0, delta, delta_LCK, delta_IQK, p = 0, i = 0;
+	s8			diff_DPK[4] = {0};
+	u8			thermal_value_avg_count = 0;
+	u32			thermal_value_avg = 0, regc80, regcd0, regcd4, regab4;
+
+	u8			OFDM_min_index = 0;  /* OFDM BB Swing should be less than +3.0dB, which is required by Arthur */
+	u8			indexforchannel = 0; /* get_right_chnl_place_for_iqk(p_hal_data->current_channel) */
+	u8			power_tracking_type = p_hal_data->RfPowerTrackingType;
+	u8			xtal_offset_eanble = 0;
+	s8			thermal_value_temp = 0;
+
+	struct _TXPWRTRACK_CFG	c;
+
+	/* 4 1. The following TWO tables decide the final index of OFDM/CCK swing table. */
+	u8			*delta_swing_table_idx_tup_a = NULL;
+	u8			*delta_swing_table_idx_tdown_a = NULL;
+	u8			*delta_swing_table_idx_tup_b = NULL;
+	u8			*delta_swing_table_idx_tdown_b = NULL;
+	/*for 8814 add by Yu Chen*/
+	u8			*delta_swing_table_idx_tup_c = NULL;
+	u8			*delta_swing_table_idx_tdown_c = NULL;
+	u8			*delta_swing_table_idx_tup_d = NULL;
+	u8			*delta_swing_table_idx_tdown_d = NULL;
+	/*for Xtal Offset by James.Tung*/
+	s8			*delta_swing_table_xtal_up = NULL;
+	s8			*delta_swing_table_xtal_down = NULL;
+
+	/* 4 2. Initilization ( 7 steps in total ) */
+
+	configure_txpower_track(p_dm_odm, &c);
+
+	(*c.get_delta_swing_table)(p_dm_odm, (u8 **)&delta_swing_table_idx_tup_a, (u8 **)&delta_swing_table_idx_tdown_a,
+		(u8 **)&delta_swing_table_idx_tup_b, (u8 **)&delta_swing_table_idx_tdown_b);
+
+	if (p_dm_odm->support_ic_type & ODM_RTL8814A)	/*for 8814 path C & D*/
+		(*c.get_delta_swing_table8814only)(p_dm_odm, (u8 **)&delta_swing_table_idx_tup_c, (u8 **)&delta_swing_table_idx_tdown_c,
+			(u8 **)&delta_swing_table_idx_tup_d, (u8 **)&delta_swing_table_idx_tdown_d);
+	/* JJ ADD 20161014 */
+	if (p_dm_odm->support_ic_type & (ODM_RTL8703B | ODM_RTL8723D | ODM_RTL8710B))	/*for Xtal Offset*/
+		(*c.get_delta_swing_xtal_table)(p_dm_odm, (s8 **)&delta_swing_table_xtal_up, (s8 **)&delta_swing_table_xtal_down);
+
+
+	p_rf_calibrate_info->txpowertracking_callback_cnt++;	/*cosa add for debug*/
+	p_rf_calibrate_info->is_txpowertracking_init = true;
+
+	/*p_rf_calibrate_info->txpowertrack_control = p_hal_data->txpowertrack_control;
+	<Kordan> We should keep updating the control variable according to HalData.
+	<Kordan> rf_calibrate_info.rega24 will be initialized when ODM HW configuring, but MP configures with para files. */
+#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
+#if (MP_DRIVER == 1)
+	p_rf_calibrate_info->rega24 = 0x090e1317;
+#endif
+#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
+	if (p_dm_odm->mp_mode == true)
+		p_rf_calibrate_info->rega24 = 0x090e1317;
+#endif
+
+	ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
+		("===>odm_txpowertracking_callback_thermal_meter\n p_rf_calibrate_info->bb_swing_idx_cck_base: %d, p_rf_calibrate_info->bb_swing_idx_ofdm_base[A]: %d, p_rf_calibrate_info->default_ofdm_index: %d\n",
+		p_rf_calibrate_info->bb_swing_idx_cck_base, p_rf_calibrate_info->bb_swing_idx_ofdm_base[ODM_RF_PATH_A], p_rf_calibrate_info->default_ofdm_index));
+
+	ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
+		("p_rf_calibrate_info->txpowertrack_control=%d,  p_hal_data->eeprom_thermal_meter %d\n", p_rf_calibrate_info->txpowertrack_control,  p_hal_data->eeprom_thermal_meter));
+	thermal_value = (u8)odm_get_rf_reg(p_dm_odm, ODM_RF_PATH_A, c.thermal_reg_addr, 0xfc00);	/* 0x42: RF Reg[15:10] 88E */
+
+	thermal_value_temp = thermal_value + phydm_get_thermal_offset(p_dm_odm);
+
+	ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
+		("thermal_value_temp(%d) thermal_value(%d) power_time_thermal(%d)\n", thermal_value_temp, thermal_value, phydm_get_thermal_offset(p_dm_odm)));
+
+	if (thermal_value_temp > 63)
+		thermal_value = 63;
+	else if (thermal_value_temp < 0)
+		thermal_value = 0;
+	else
+		thermal_value = thermal_value_temp;
+
+	/*add log by zhao he, check c80/c94/c14/ca0 value*/
+	if (p_dm_odm->support_ic_type == ODM_RTL8723D) {
+		regc80 = odm_get_bb_reg(p_dm_odm, 0xc80, MASKDWORD);
+		regcd0 = odm_get_bb_reg(p_dm_odm, 0xcd0, MASKDWORD);
+		regcd4 = odm_get_bb_reg(p_dm_odm, 0xcd4, MASKDWORD);
+		regab4 = odm_get_bb_reg(p_dm_odm, 0xab4, 0x000007FF);
+		ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xc80 = 0x%x 0xcd0 = 0x%x 0xcd4 = 0x%x 0xab4 = 0x%x\n", regc80, regcd0, regcd4, regab4));
+	}
+
+	/* JJ ADD 20161014 */
+	if (p_dm_odm->support_ic_type == ODM_RTL8710B) {
+		regc80 = odm_get_bb_reg(p_dm_odm, 0xc80, MASKDWORD);
+		regcd0 = odm_get_bb_reg(p_dm_odm, 0xcd0, MASKDWORD);
+		regcd4 = odm_get_bb_reg(p_dm_odm, 0xcd4, MASKDWORD);
+		regab4 = odm_get_bb_reg(p_dm_odm, 0xab4, 0x000007FF);
+		ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xc80 = 0x%x 0xcd0 = 0x%x 0xcd4 = 0x%x 0xab4 = 0x%x\n", regc80, regcd0, regcd4, regab4));
+	}
+
+	if (!p_rf_calibrate_info->txpowertrack_control)
+		return;
+
+	if (p_hal_data->eeprom_thermal_meter == 0xff) {
+		ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("no pg, p_hal_data->eeprom_thermal_meter = 0x%x\n", p_hal_data->eeprom_thermal_meter));
+		return;
+	}
+
+	/*4 3. Initialize ThermalValues of rf_calibrate_info*/
+
+	if (p_rf_calibrate_info->is_reloadtxpowerindex)
+		ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("reload ofdm index for band switch\n"));
+
+	/*4 4. Calculate average thermal meter*/
+
+	p_rf_calibrate_info->thermal_value_avg[p_rf_calibrate_info->thermal_value_avg_index] = thermal_value;
+	p_rf_calibrate_info->thermal_value_avg_index++;
+	if (p_rf_calibrate_info->thermal_value_avg_index == c.average_thermal_num)   /*Average times =  c.average_thermal_num*/
+		p_rf_calibrate_info->thermal_value_avg_index = 0;
+
+	for (i = 0; i < c.average_thermal_num; i++) {
+		if (p_rf_calibrate_info->thermal_value_avg[i]) {
+			thermal_value_avg += p_rf_calibrate_info->thermal_value_avg[i];
+			thermal_value_avg_count++;
+		}
+	}
+
+	if (thermal_value_avg_count) {            /* Calculate Average thermal_value after average enough times */
+		thermal_value = (u8)(thermal_value_avg / thermal_value_avg_count);
+		p_rf_calibrate_info->thermal_value_delta = thermal_value - p_hal_data->eeprom_thermal_meter;
+		ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
+			("AVG Thermal Meter = 0x%X, EFUSE Thermal base = 0x%X\n", thermal_value, p_hal_data->eeprom_thermal_meter));
+	}
+
+	/* 4 5. Calculate delta, delta_LCK, delta_IQK. */
+
+	/* "delta" here is used to determine whether thermal value changes or not. */
+	delta	= (thermal_value > p_rf_calibrate_info->thermal_value) ? (thermal_value - p_rf_calibrate_info->thermal_value) : (p_rf_calibrate_info->thermal_value - thermal_value);
+	delta_LCK = (thermal_value > p_rf_calibrate_info->thermal_value_lck) ? (thermal_value - p_rf_calibrate_info->thermal_value_lck) : (p_rf_calibrate_info->thermal_value_lck - thermal_value);
+	delta_IQK = (thermal_value > p_rf_calibrate_info->thermal_value_iqk) ? (thermal_value - p_rf_calibrate_info->thermal_value_iqk) : (p_rf_calibrate_info->thermal_value_iqk - thermal_value);
+
+	if (p_rf_calibrate_info->thermal_value_iqk == 0xff) {	/*no PG, use thermal value for IQK*/
+		p_rf_calibrate_info->thermal_value_iqk = thermal_value;
+		delta_IQK = (thermal_value > p_rf_calibrate_info->thermal_value_iqk) ? (thermal_value - p_rf_calibrate_info->thermal_value_iqk) : (p_rf_calibrate_info->thermal_value_iqk - thermal_value);
+		ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("no PG, use thermal_value for IQK\n"));
+	}
+
+	for (p = ODM_RF_PATH_A; p < c.rf_path_count; p++)
+		diff_DPK[p] = (s8)thermal_value - (s8)p_rf_calibrate_info->dpk_thermal[p];
+
+	/*4 6. If necessary, do LCK.*/
+
+	if (!(p_dm_odm->support_ic_type & ODM_RTL8821)) {	/*no PG, do LCK at initial status*/
+		if (p_rf_calibrate_info->thermal_value_lck == 0xff) {
+			ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("no PG, do LCK\n"));
+			p_rf_calibrate_info->thermal_value_lck = thermal_value;
+
+			/*Use RTLCK, so close power tracking driver LCK*/
+			if ((!(p_dm_odm->support_ic_type & ODM_RTL8814A)) && (!(p_dm_odm->support_ic_type & ODM_RTL8822B))) {
+				if (c.phy_lc_calibrate)
+					(*c.phy_lc_calibrate)(p_dm_odm);
+			}
+			delta_LCK = (thermal_value > p_rf_calibrate_info->thermal_value_lck) ? (thermal_value - p_rf_calibrate_info->thermal_value_lck) : (p_rf_calibrate_info->thermal_value_lck - thermal_value);
+		}
+
+		ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("(delta, delta_LCK, delta_IQK) = (%d, %d, %d)\n", delta, delta_LCK, delta_IQK));
+
+		/* Wait sacn to do LCK by RF Jenyu*/
+		if (*p_dm_odm->p_is_scan_in_process == false) {
+			/* Delta temperature is equal to or larger than 20 centigrade.*/
+			if (delta_LCK >= c.threshold_iqk) {
+				ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("delta_LCK(%d) >= threshold_iqk(%d)\n", delta_LCK, c.threshold_iqk));
+				p_rf_calibrate_info->thermal_value_lck = thermal_value;
+
+				/*Use RTLCK, so close power tracking driver LCK*/
+				if ((!(p_dm_odm->support_ic_type & ODM_RTL8814A)) && (!(p_dm_odm->support_ic_type & ODM_RTL8822B))) {
+					if (c.phy_lc_calibrate)
+						(*c.phy_lc_calibrate)(p_dm_odm);
+				}
+			}
+		}
+	}
+
+	/*3 7. If necessary, move the index of swing table to adjust Tx power.*/
+
+	if (delta > 0 && p_rf_calibrate_info->txpowertrack_control) {
+		/* "delta" here is used to record the absolute value of differrence. */
+#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
+		delta = thermal_value > p_hal_data->eeprom_thermal_meter ? (thermal_value - p_hal_data->eeprom_thermal_meter) : (p_hal_data->eeprom_thermal_meter - thermal_value);
+#else
+		delta = (thermal_value > p_dm_odm->priv->pmib->dot11RFEntry.ther) ? (thermal_value - p_dm_odm->priv->pmib->dot11RFEntry.ther) : (p_dm_odm->priv->pmib->dot11RFEntry.ther - thermal_value);
+#endif
+		if (delta >= TXPWR_TRACK_TABLE_SIZE)
+			delta = TXPWR_TRACK_TABLE_SIZE - 1;
+
+		/*4 7.1 The Final Power index = BaseIndex + power_index_offset*/
+
+#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
+		if (thermal_value > p_hal_data->eeprom_thermal_meter) {
+#else
+		if (thermal_value > p_dm_odm->priv->pmib->dot11RFEntry.ther) {
+#endif
+
+			for (p = ODM_RF_PATH_A; p < c.rf_path_count; p++) {
+				p_rf_calibrate_info->delta_power_index_last[p] = p_rf_calibrate_info->delta_power_index[p];	/*recording poer index offset*/
+				switch (p) {
+				case ODM_RF_PATH_B:
+					ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
+						("delta_swing_table_idx_tup_b[%d] = %d\n", delta, delta_swing_table_idx_tup_b[delta]));
+
+					p_rf_calibrate_info->delta_power_index[p] = delta_swing_table_idx_tup_b[delta];
+					p_rf_calibrate_info->absolute_ofdm_swing_idx[p] =  delta_swing_table_idx_tup_b[delta];       /*Record delta swing for mix mode power tracking*/
+					ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
+						("******Temp is higher and p_rf_calibrate_info->absolute_ofdm_swing_idx[ODM_RF_PATH_B] = %d\n", p_rf_calibrate_info->absolute_ofdm_swing_idx[p]));
+					break;
+
+				case ODM_RF_PATH_C:
+					ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
+						("delta_swing_table_idx_tup_c[%d] = %d\n", delta, delta_swing_table_idx_tup_c[delta]));
+
+					p_rf_calibrate_info->delta_power_index[p] = delta_swing_table_idx_tup_c[delta];
+					p_rf_calibrate_info->absolute_ofdm_swing_idx[p] =  delta_swing_table_idx_tup_c[delta];       /*Record delta swing for mix mode power tracking*/
+					ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
+						("******Temp is higher and p_rf_calibrate_info->absolute_ofdm_swing_idx[ODM_RF_PATH_C] = %d\n", p_rf_calibrate_info->absolute_ofdm_swing_idx[p]));
+					break;
+
+				case ODM_RF_PATH_D:
+					ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
+						("delta_swing_table_idx_tup_d[%d] = %d\n", delta, delta_swing_table_idx_tup_d[delta]));
+
+					p_rf_calibrate_info->delta_power_index[p] = delta_swing_table_idx_tup_d[delta];
+					p_rf_calibrate_info->absolute_ofdm_swing_idx[p] =  delta_swing_table_idx_tup_d[delta];       /*Record delta swing for mix mode power tracking*/
+					ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
+						("******Temp is higher and p_rf_calibrate_info->absolute_ofdm_swing_idx[ODM_RF_PATH_D] = %d\n", p_rf_calibrate_info->absolute_ofdm_swing_idx[p]));
+					break;
+
+				default:
+					ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
+						("delta_swing_table_idx_tup_a[%d] = %d\n", delta, delta_swing_table_idx_tup_a[delta]));
+
+					p_rf_calibrate_info->delta_power_index[p] = delta_swing_table_idx_tup_a[delta];
+					p_rf_calibrate_info->absolute_ofdm_swing_idx[p] =  delta_swing_table_idx_tup_a[delta];        /*Record delta swing for mix mode power tracking*/
+					ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
+						("******Temp is higher and p_rf_calibrate_info->absolute_ofdm_swing_idx[ODM_RF_PATH_A] = %d\n", p_rf_calibrate_info->absolute_ofdm_swing_idx[p]));
+					break;
+				}
+			}
+			/* JJ ADD 20161014 */
+			if (p_dm_odm->support_ic_type & (ODM_RTL8703B | ODM_RTL8723D | ODM_RTL8710B)) {
+				/*Save xtal_offset from Xtal table*/
+				p_rf_calibrate_info->xtal_offset_last = p_rf_calibrate_info->xtal_offset;	/*recording last Xtal offset*/
+				ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
+					("[Xtal] delta_swing_table_xtal_up[%d] = %d\n", delta, delta_swing_table_xtal_up[delta]));
+				p_rf_calibrate_info->xtal_offset = delta_swing_table_xtal_up[delta];
+
+				if (p_rf_calibrate_info->xtal_offset_last == p_rf_calibrate_info->xtal_offset)
+					xtal_offset_eanble = 0;
+				else
+					xtal_offset_eanble = 1;
+			}
+
+		} else {
+			for (p = ODM_RF_PATH_A; p < c.rf_path_count; p++) {
+				p_rf_calibrate_info->delta_power_index_last[p] = p_rf_calibrate_info->delta_power_index[p];	/*recording poer index offset*/
+
+				switch (p) {
+				case ODM_RF_PATH_B:
+					ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
+						("delta_swing_table_idx_tdown_b[%d] = %d\n", delta, delta_swing_table_idx_tdown_b[delta]));
+					p_rf_calibrate_info->delta_power_index[p] = -1 * delta_swing_table_idx_tdown_b[delta];
+					p_rf_calibrate_info->absolute_ofdm_swing_idx[p] =  -1 * delta_swing_table_idx_tdown_b[delta];        /*Record delta swing for mix mode power tracking*/
+					ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
+						("******Temp is lower and p_rf_calibrate_info->absolute_ofdm_swing_idx[ODM_RF_PATH_B] = %d\n", p_rf_calibrate_info->absolute_ofdm_swing_idx[p]));
+					break;
+
+				case ODM_RF_PATH_C:
+					ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
+						("delta_swing_table_idx_tdown_c[%d] = %d\n", delta, delta_swing_table_idx_tdown_c[delta]));
+					p_rf_calibrate_info->delta_power_index[p] = -1 * delta_swing_table_idx_tdown_c[delta];
+					p_rf_calibrate_info->absolute_ofdm_swing_idx[p] =  -1 * delta_swing_table_idx_tdown_c[delta];        /*Record delta swing for mix mode power tracking*/
+					ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
+						("******Temp is lower and p_rf_calibrate_info->absolute_ofdm_swing_idx[ODM_RF_PATH_C] = %d\n", p_rf_calibrate_info->absolute_ofdm_swing_idx[p]));
+					break;
+
+				case ODM_RF_PATH_D:
+					ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
+						("delta_swing_table_idx_tdown_d[%d] = %d\n", delta, delta_swing_table_idx_tdown_d[delta]));
+					p_rf_calibrate_info->delta_power_index[p] = -1 * delta_swing_table_idx_tdown_d[delta];
+					p_rf_calibrate_info->absolute_ofdm_swing_idx[p] =  -1 * delta_swing_table_idx_tdown_d[delta];        /*Record delta swing for mix mode power tracking*/
+					ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
+						("******Temp is lower and p_rf_calibrate_info->absolute_ofdm_swing_idx[ODM_RF_PATH_D] = %d\n", p_rf_calibrate_info->absolute_ofdm_swing_idx[p]));
+					break;
+
+				default:
+					ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
+						("delta_swing_table_idx_tdown_a[%d] = %d\n", delta, delta_swing_table_idx_tdown_a[delta]));
+					p_rf_calibrate_info->delta_power_index[p] = -1 * delta_swing_table_idx_tdown_a[delta];
+					p_rf_calibrate_info->absolute_ofdm_swing_idx[p] =  -1 * delta_swing_table_idx_tdown_a[delta];        /*Record delta swing for mix mode power tracking*/
+					ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
+						("******Temp is lower and p_rf_calibrate_info->absolute_ofdm_swing_idx[ODM_RF_PATH_A] = %d\n", p_rf_calibrate_info->absolute_ofdm_swing_idx[p]));
+					break;
+				}
+			}
+			/* JJ ADD 20161014 */
+			if (p_dm_odm->support_ic_type & (ODM_RTL8703B | ODM_RTL8723D | ODM_RTL8710B)) {
+				/*Save xtal_offset from Xtal table*/
+				p_rf_calibrate_info->xtal_offset_last = p_rf_calibrate_info->xtal_offset;	/*recording last Xtal offset*/
+				ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
+					("[Xtal] delta_swing_table_xtal_down[%d] = %d\n", delta, delta_swing_table_xtal_down[delta]));
+				p_rf_calibrate_info->xtal_offset = delta_swing_table_xtal_down[delta];
+
+				if (p_rf_calibrate_info->xtal_offset_last == p_rf_calibrate_info->xtal_offset)
+					xtal_offset_eanble = 0;
+				else
+					xtal_offset_eanble = 1;
+			}
+
+		}
+
+		for (p = ODM_RF_PATH_A; p < c.rf_path_count; p++) {
+			ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
+				("\n\n=========================== [path-%d] Calculating power_index_offset===========================\n", p));
+
+			if (p_rf_calibrate_info->delta_power_index[p] == p_rf_calibrate_info->delta_power_index_last[p])         /*If Thermal value changes but lookup table value still the same*/
+				p_rf_calibrate_info->power_index_offset[p] = 0;
+			else
+				p_rf_calibrate_info->power_index_offset[p] = p_rf_calibrate_info->delta_power_index[p] - p_rf_calibrate_info->delta_power_index_last[p];      /*Power index diff between 2 times Power Tracking*/
+
+			ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
+				("[path-%d] power_index_offset(%d) = delta_power_index(%d) - delta_power_index_last(%d)\n", p, p_rf_calibrate_info->power_index_offset[p], p_rf_calibrate_info->delta_power_index[p], p_rf_calibrate_info->delta_power_index_last[p]));
+
+			p_rf_calibrate_info->OFDM_index[p] = p_rf_calibrate_info->bb_swing_idx_ofdm_base[p] + p_rf_calibrate_info->power_index_offset[p];
+			p_rf_calibrate_info->CCK_index = p_rf_calibrate_info->bb_swing_idx_cck_base + p_rf_calibrate_info->power_index_offset[p];
+
+			p_rf_calibrate_info->bb_swing_idx_cck = p_rf_calibrate_info->CCK_index;
+			p_rf_calibrate_info->bb_swing_idx_ofdm[p] = p_rf_calibrate_info->OFDM_index[p];
+
+			/*************Print BB Swing base and index Offset*************/
+
+			ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
+				("The 'CCK' final index(%d) = BaseIndex(%d) + power_index_offset(%d)\n", p_rf_calibrate_info->bb_swing_idx_cck, p_rf_calibrate_info->bb_swing_idx_cck_base, p_rf_calibrate_info->power_index_offset[p]));
+			ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
+				("The 'OFDM' final index(%d) = BaseIndex[%d](%d) + power_index_offset(%d)\n", p_rf_calibrate_info->bb_swing_idx_ofdm[p], p, p_rf_calibrate_info->bb_swing_idx_ofdm_base[p], p_rf_calibrate_info->power_index_offset[p]));
+
+			/*4 7.1 Handle boundary conditions of index.*/
+
+			if (p_rf_calibrate_info->OFDM_index[p] > c.swing_table_size_ofdm - 1)
+				p_rf_calibrate_info->OFDM_index[p] = c.swing_table_size_ofdm - 1;
+			else if (p_rf_calibrate_info->OFDM_index[p] <= OFDM_min_index)
+				p_rf_calibrate_info->OFDM_index[p] = OFDM_min_index;
+		}
+
+		ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
+			("\n\n========================================================================================================\n"));
+
+		if (p_rf_calibrate_info->CCK_index > c.swing_table_size_cck - 1)
+			p_rf_calibrate_info->CCK_index = c.swing_table_size_cck - 1;
+		else if (p_rf_calibrate_info->CCK_index <= 0)
+			p_rf_calibrate_info->CCK_index = 0;
+	} else {
+		ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
+			("The thermal meter is unchanged or TxPowerTracking OFF(%d): thermal_value: %d, p_rf_calibrate_info->thermal_value: %d\n",
+			p_rf_calibrate_info->txpowertrack_control, thermal_value, p_rf_calibrate_info->thermal_value));
+
+		for (p = ODM_RF_PATH_A; p < c.rf_path_count; p++)
+			p_rf_calibrate_info->power_index_offset[p] = 0;
+	}
+
+	ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
+		("TxPowerTracking: [CCK] Swing Current index: %d, Swing base index: %d\n",
+		p_rf_calibrate_info->CCK_index, p_rf_calibrate_info->bb_swing_idx_cck_base));       /*Print Swing base & current*/
+
+	for (p = ODM_RF_PATH_A; p < c.rf_path_count; p++) {
+		ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
+			("TxPowerTracking: [OFDM] Swing Current index: %d, Swing base index[%d]: %d\n",
+			p_rf_calibrate_info->OFDM_index[p], p, p_rf_calibrate_info->bb_swing_idx_ofdm_base[p]));
+	}
+
+	if ((p_dm_odm->support_ic_type & ODM_RTL8814A)) {
+		ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("power_tracking_type=%d\n", power_tracking_type));
+
+		if (power_tracking_type == 0) {
+			ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("**********Enter POWER Tracking MIX_MODE**********\n"));
+			for (p = ODM_RF_PATH_A; p < c.rf_path_count; p++)
+				(*c.odm_tx_pwr_track_set_pwr)(p_dm_odm, MIX_MODE, p, 0);
+		} else if (power_tracking_type == 1) {
+			ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("**********Enter POWER Tracking MIX(2G) TSSI(5G) MODE**********\n"));
+			for (p = ODM_RF_PATH_A; p < c.rf_path_count; p++)
+				(*c.odm_tx_pwr_track_set_pwr)(p_dm_odm, MIX_2G_TSSI_5G_MODE, p, 0);
+		} else if (power_tracking_type == 2) {
+			ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("**********Enter POWER Tracking MIX(5G) TSSI(2G)MODE**********\n"));
+			for (p = ODM_RF_PATH_A; p < c.rf_path_count; p++)
+				(*c.odm_tx_pwr_track_set_pwr)(p_dm_odm, MIX_5G_TSSI_2G_MODE, p, 0);
+		} else if (power_tracking_type == 3) {
+			ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("**********Enter POWER Tracking TSSI MODE**********\n"));
+			for (p = ODM_RF_PATH_A; p < c.rf_path_count; p++)
+				(*c.odm_tx_pwr_track_set_pwr)(p_dm_odm, TSSI_MODE, p, 0);
+		}
+		p_rf_calibrate_info->thermal_value = thermal_value;         /*Record last Power Tracking Thermal value*/
+
+	} else if ((p_rf_calibrate_info->power_index_offset[ODM_RF_PATH_A] != 0 ||
+		p_rf_calibrate_info->power_index_offset[ODM_RF_PATH_B] != 0 ||
+		p_rf_calibrate_info->power_index_offset[ODM_RF_PATH_C] != 0 ||
+		p_rf_calibrate_info->power_index_offset[ODM_RF_PATH_D] != 0) &&
+		p_rf_calibrate_info->txpowertrack_control && (p_hal_data->eeprom_thermal_meter != 0xff)) {
+		/* 4 7.2 Configure the Swing Table to adjust Tx Power. */
+
+		p_rf_calibrate_info->is_tx_power_changed = true;	/*Always true after Tx Power is adjusted by power tracking.*/
+		/*  */
+		/* 2012/04/23 MH According to Luke's suggestion, we can not write BB digital */
+		/* to increase TX power. Otherwise, EVM will be bad. */
+		/*  */
+		/* 2012/04/25 MH Add for tx power tracking to set tx power in tx agc for 88E. */
+		if (thermal_value > p_rf_calibrate_info->thermal_value) {
+			for (p = ODM_RF_PATH_A; p < c.rf_path_count; p++) {
+				ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
+					("Temperature Increasing(%d): delta_pi: %d, delta_t: %d, Now_t: %d, EFUSE_t: %d, Last_t: %d\n",
+					p, p_rf_calibrate_info->power_index_offset[p], delta, thermal_value, p_hal_data->eeprom_thermal_meter, p_rf_calibrate_info->thermal_value));
+			}
+		} else if (thermal_value < p_rf_calibrate_info->thermal_value) {	/*Low temperature*/
+			for (p = ODM_RF_PATH_A; p < c.rf_path_count; p++) {
+				ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
+					("Temperature Decreasing(%d): delta_pi: %d, delta_t: %d, Now_t: %d, EFUSE_t: %d, Last_t: %d\n",
+					p, p_rf_calibrate_info->power_index_offset[p], delta, thermal_value, p_hal_data->eeprom_thermal_meter, p_rf_calibrate_info->thermal_value));
+			}
+		}
+
+#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
+		if (thermal_value > p_hal_data->eeprom_thermal_meter)
+#else
+		if (thermal_value > p_dm_odm->priv->pmib->dot11RFEntry.ther)
+#endif
+		{
+			ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
+				("Temperature(%d) higher than PG value(%d)\n", thermal_value, p_hal_data->eeprom_thermal_meter));
+
+			if (p_dm_odm->support_ic_type == ODM_RTL8188E || p_dm_odm->support_ic_type == ODM_RTL8192E || p_dm_odm->support_ic_type == ODM_RTL8821 ||
+			    p_dm_odm->support_ic_type == ODM_RTL8812 || p_dm_odm->support_ic_type == ODM_RTL8723B || p_dm_odm->support_ic_type == ODM_RTL8814A ||
+			    p_dm_odm->support_ic_type == ODM_RTL8703B || p_dm_odm->support_ic_type == ODM_RTL8188F || p_dm_odm->support_ic_type == ODM_RTL8822B ||
+			    p_dm_odm->support_ic_type == ODM_RTL8723D || p_dm_odm->support_ic_type == ODM_RTL8821C || p_dm_odm->support_ic_type == ODM_RTL8710B) {/* JJ ADD 20161014 */
+
+				ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("**********Enter POWER Tracking MIX_MODE**********\n"));
+				for (p = ODM_RF_PATH_A; p < c.rf_path_count; p++)
+					(*c.odm_tx_pwr_track_set_pwr)(p_dm_odm, MIX_MODE, p, 0);
+			} else {
+				ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("**********Enter POWER Tracking BBSWING_MODE**********\n"));
+				for (p = ODM_RF_PATH_A; p < c.rf_path_count; p++)
+					(*c.odm_tx_pwr_track_set_pwr)(p_dm_odm, BBSWING, p, indexforchannel);
+			}
+		} else {
+			ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
+				("Temperature(%d) lower than PG value(%d)\n", thermal_value, p_hal_data->eeprom_thermal_meter));
+
+			if (p_dm_odm->support_ic_type == ODM_RTL8188E || p_dm_odm->support_ic_type == ODM_RTL8192E || p_dm_odm->support_ic_type == ODM_RTL8821 ||
+			    p_dm_odm->support_ic_type == ODM_RTL8812 || p_dm_odm->support_ic_type == ODM_RTL8723B || p_dm_odm->support_ic_type == ODM_RTL8814A ||
+			    p_dm_odm->support_ic_type == ODM_RTL8703B || p_dm_odm->support_ic_type == ODM_RTL8188F || p_dm_odm->support_ic_type == ODM_RTL8822B ||
+			    p_dm_odm->support_ic_type == ODM_RTL8723D || p_dm_odm->support_ic_type == ODM_RTL8821C || p_dm_odm->support_ic_type == ODM_RTL8710B) {/* JJ ADD 20161014 */
+
+				ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("**********Enter POWER Tracking MIX_MODE**********\n"));
+				for (p = ODM_RF_PATH_A; p < c.rf_path_count; p++)
+					(*c.odm_tx_pwr_track_set_pwr)(p_dm_odm, MIX_MODE, p, indexforchannel);
+			} else {
+				ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("**********Enter POWER Tracking BBSWING_MODE**********\n"));
+				for (p = ODM_RF_PATH_A; p < c.rf_path_count; p++)
+					(*c.odm_tx_pwr_track_set_pwr)(p_dm_odm, BBSWING, p, indexforchannel);
+			}
+
+		}
+
+		p_rf_calibrate_info->bb_swing_idx_cck_base = p_rf_calibrate_info->bb_swing_idx_cck;    /*Record last time Power Tracking result as base.*/
+		for (p = ODM_RF_PATH_A; p < c.rf_path_count; p++)
+			p_rf_calibrate_info->bb_swing_idx_ofdm_base[p] = p_rf_calibrate_info->bb_swing_idx_ofdm[p];
+
+		ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
+			("p_rf_calibrate_info->thermal_value = %d thermal_value= %d\n", p_rf_calibrate_info->thermal_value, thermal_value));
+
+		p_rf_calibrate_info->thermal_value = thermal_value;         /*Record last Power Tracking Thermal value*/
+
+	}
+
+
+	if (p_dm_odm->support_ic_type == ODM_RTL8703B || p_dm_odm->support_ic_type == ODM_RTL8723D || p_dm_odm->support_ic_type == ODM_RTL8710B) {/* JJ ADD 20161014 */
+
+		if (xtal_offset_eanble != 0 && p_rf_calibrate_info->txpowertrack_control && (p_hal_data->eeprom_thermal_meter != 0xff)) {
+
+			ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("**********Enter Xtal Tracking**********\n"));
+
+#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
+			if (thermal_value > p_hal_data->eeprom_thermal_meter) {
+#else
+			if (thermal_value > p_dm_odm->priv->pmib->dot11RFEntry.ther) {
+#endif
+				ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
+					("Temperature(%d) higher than PG value(%d)\n", thermal_value, p_hal_data->eeprom_thermal_meter));
+				(*c.odm_txxtaltrack_set_xtal)(p_dm_odm);
+			} else {
+				ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
+					("Temperature(%d) lower than PG value(%d)\n", thermal_value, p_hal_data->eeprom_thermal_meter));
+				(*c.odm_txxtaltrack_set_xtal)(p_dm_odm);
+			}
+		}
+		ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("**********End Xtal Tracking**********\n"));
+	}
+
+#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
+
+	/* Wait sacn to do IQK by RF Jenyu*/
+	if (*p_dm_odm->p_is_scan_in_process == false) {
+		if (!IS_HARDWARE_TYPE_8723B(adapter)) {
+			/*Delta temperature is equal to or larger than 20 centigrade (When threshold is 8).*/
+			if (delta_IQK >= c.threshold_iqk) {
+				p_rf_calibrate_info->thermal_value_iqk = thermal_value;
+				ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("delta_IQK(%d) >= threshold_iqk(%d)\n", delta_IQK, c.threshold_iqk));
+				if (!p_rf_calibrate_info->is_iqk_in_progress)
+					(*c.do_iqk)(p_dm_odm, delta_IQK, thermal_value, 8);
+			}
+		}
+	}
+	if (p_rf_calibrate_info->dpk_thermal[ODM_RF_PATH_A] != 0) {
+		if (diff_DPK[ODM_RF_PATH_A] >= c.threshold_dpk) {
+			odm_set_bb_reg(p_dm_odm, 0x82c, BIT(31), 0x1);
+			odm_set_bb_reg(p_dm_odm, 0xcc4, BIT(14) | BIT(13) | BIT(12) | BIT(11) | BIT(10), (diff_DPK[ODM_RF_PATH_A] / c.threshold_dpk));
+			odm_set_bb_reg(p_dm_odm, 0x82c, BIT(31), 0x0);
+		} else if ((diff_DPK[ODM_RF_PATH_A] <= -1 * c.threshold_dpk)) {
+			s32 value = 0x20 + (diff_DPK[ODM_RF_PATH_A] / c.threshold_dpk);
+
+			odm_set_bb_reg(p_dm_odm, 0x82c, BIT(31), 0x1);
+			odm_set_bb_reg(p_dm_odm, 0xcc4, BIT(14) | BIT(13) | BIT(12) | BIT(11) | BIT(10), value);
+			odm_set_bb_reg(p_dm_odm, 0x82c, BIT(31), 0x0);
+		} else {
+			odm_set_bb_reg(p_dm_odm, 0x82c, BIT(31), 0x1);
+			odm_set_bb_reg(p_dm_odm, 0xcc4, BIT(14) | BIT(13) | BIT(12) | BIT(11) | BIT(10), 0);
+			odm_set_bb_reg(p_dm_odm, 0x82c, BIT(31), 0x0);
+		}
+	}
+	if (p_rf_calibrate_info->dpk_thermal[ODM_RF_PATH_B] != 0) {
+		if (diff_DPK[ODM_RF_PATH_B] >= c.threshold_dpk) {
+			odm_set_bb_reg(p_dm_odm, 0x82c, BIT(31), 0x1);
+			odm_set_bb_reg(p_dm_odm, 0xec4, BIT(14) | BIT(13) | BIT(12) | BIT(11) | BIT(10), (diff_DPK[ODM_RF_PATH_B] / c.threshold_dpk));
+			odm_set_bb_reg(p_dm_odm, 0x82c, BIT(31), 0x0);
+		} else if ((diff_DPK[ODM_RF_PATH_B] <= -1 * c.threshold_dpk)) {
+			s32 value = 0x20 + (diff_DPK[ODM_RF_PATH_B] / c.threshold_dpk);
+
+			odm_set_bb_reg(p_dm_odm, 0x82c, BIT(31), 0x1);
+			odm_set_bb_reg(p_dm_odm, 0xec4, BIT(14) | BIT(13) | BIT(12) | BIT(11) | BIT(10), value);
+			odm_set_bb_reg(p_dm_odm, 0x82c, BIT(31), 0x0);
+		} else {
+			odm_set_bb_reg(p_dm_odm, 0x82c, BIT(31), 0x1);
+			odm_set_bb_reg(p_dm_odm, 0xec4, BIT(14) | BIT(13) | BIT(12) | BIT(11) | BIT(10), 0);
+			odm_set_bb_reg(p_dm_odm, 0x82c, BIT(31), 0x0);
+		}
+	}
+
+#endif
+
+	ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("<===odm_txpowertracking_callback_thermal_meter\n"));
+
+	p_rf_calibrate_info->tx_powercount = 0;
+}
+
+
+
+/* 3============================================================
+ * 3 IQ Calibration
+ * 3============================================================ */
+
+void
+odm_reset_iqk_result(
+	struct PHY_DM_STRUCT	*p_dm_odm
+)
+{
+	return;
+}
+#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
+u8 odm_get_right_chnl_place_for_iqk(u8 chnl)
+{
+	u8	channel_all[ODM_TARGET_CHNL_NUM_2G_5G] = {
+		1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 36, 38, 40, 42, 44, 46, 48, 50, 52, 54, 56, 58, 60, 62, 64, 100, 102, 104, 106, 108, 110, 112, 114, 116, 118, 120, 122, 124, 126, 128, 130, 132, 134, 136, 138, 140, 149, 151, 153, 155, 157, 159, 161, 163, 165
+	};
+	u8	place = chnl;
+
+
+	if (chnl > 14) {
+		for (place = 14; place < sizeof(channel_all); place++) {
+			if (channel_all[place] == chnl)
+				return place - 13;
+		}
+	}
+	return 0;
+
+}
+#endif
+
+void
+odm_iq_calibrate(
+	struct PHY_DM_STRUCT	*p_dm_odm
+)
+{
+	struct _ADAPTER	*adapter = p_dm_odm->adapter;
+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(adapter);
+
+	RT_TRACE(COMP_SCAN, ODM_DBG_LOUD, ("=>%s\n" , __FUNCTION__));
+
+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
+	if (*p_dm_odm->p_is_fcs_mode_enable)
+		return;
+#endif
+
+	if (p_dm_odm->is_linked) {
+		RT_TRACE(COMP_SCAN, ODM_DBG_LOUD, ("interval=%d ch=%d prech=%d scan=%s\n", p_dm_odm->linked_interval,
+			*p_dm_odm->p_channel,  p_dm_odm->pre_channel, *p_dm_odm->p_is_scan_in_process == TRUE ? "TRUE":"FALSE"));
+
+		if (*p_dm_odm->p_channel != p_dm_odm->pre_channel) {
+			p_dm_odm->pre_channel = *p_dm_odm->p_channel;
+			p_dm_odm->linked_interval = 0;
+		}
+
+		if ((p_dm_odm->linked_interval < 3) && (!*p_dm_odm->p_is_scan_in_process))
+			p_dm_odm->linked_interval++;
+
+		if (p_dm_odm->linked_interval == 2)
+			PHY_IQCalibrate(adapter, false);
+	} else
+		p_dm_odm->linked_interval = 0;
+
+		RT_TRACE(COMP_SCAN, ODM_DBG_LOUD, ("<=%s interval=%d ch=%d prech=%d scan=%s\n", __FUNCTION__, p_dm_odm->linked_interval,
+			*p_dm_odm->p_channel,  p_dm_odm->pre_channel, *p_dm_odm->p_is_scan_in_process == TRUE?"TRUE":"FALSE"));
+}
+
+void phydm_rf_init(struct PHY_DM_STRUCT		*p_dm_odm)
+{
+
+	odm_txpowertracking_init(p_dm_odm);
+
+#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
+	odm_clear_txpowertracking_state(p_dm_odm);
+#endif
+
+#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
+#if (RTL8814A_SUPPORT == 1)
+	if (p_dm_odm->support_ic_type & ODM_RTL8814A)
+		phy_iq_calibrate_8814a_init(p_dm_odm);
+#endif
+#endif
+
+}
+
+void phydm_rf_watchdog(struct PHY_DM_STRUCT		*p_dm_odm)
+{
+
+#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
+	odm_txpowertracking_check(p_dm_odm);
+	if (p_dm_odm->support_ic_type & ODM_IC_11AC_SERIES)
+		odm_iq_calibrate(p_dm_odm);
+#endif
+}
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/halphyrf_win.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/halphyrf_win.h
--- linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/halphyrf_win.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/halphyrf_win.h	2020-04-10 16:35:06.818660161 +0300
@@ -0,0 +1,119 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
+ *
+ *
+ ******************************************************************************/
+
+#ifndef __HAL_PHY_RF_H__
+#define __HAL_PHY_RF_H__
+
+#include "phydm_kfree.h"
+#if (RTL8814A_SUPPORT == 1)
+	#include "rtl8814a/phydm_iqk_8814a.h"
+#endif
+
+#if (RTL8822B_SUPPORT == 1)
+	#include "rtl8822b/phydm_iqk_8822b.h"
+	#include "../mac/Halmac_type.h"
+#endif
+#include "phydm_powertracking_win.h"
+
+#if (RTL8821C_SUPPORT == 1)
+	#include "rtl8821c/phydm_iqk_8821c.h"
+#endif
+
+enum spur_cal_method {
+	PLL_RESET,
+	AFE_PHASE_SEL
+};
+
+enum pwrtrack_method {
+	BBSWING,
+	TXAGC,
+	MIX_MODE,
+	TSSI_MODE,
+	MIX_2G_TSSI_5G_MODE,
+	MIX_5G_TSSI_2G_MODE
+};
+
+typedef void(*func_set_pwr)(void *, enum pwrtrack_method, u8, u8);
+typedef void(*func_iqk)(void *, u8, u8, u8);
+typedef void(*func_lck)(void *);
+typedef void(*func_swing)(void *, u8 **, u8 **, u8 **, u8 **);
+typedef void(*func_swing8814only)(void *, u8 **, u8 **, u8 **, u8 **);
+typedef void (*func_swing_xtal)(void *, s8 **, s8 **);
+typedef void (*func_set_xtal)(void *);
+typedef void(*func_all_swing)(void *, u8 **, u8 **, u8 **, u8 **, u8 **, u8 **, u8 **, u8 **);
+
+struct _TXPWRTRACK_CFG {
+	u8		swing_table_size_cck;
+	u8		swing_table_size_ofdm;
+	u8		threshold_iqk;
+	u8		threshold_dpk;
+	u8		average_thermal_num;
+	u8		rf_path_count;
+	u32		thermal_reg_addr;
+	func_set_pwr	odm_tx_pwr_track_set_pwr;
+	func_iqk	do_iqk;
+	func_lck		phy_lc_calibrate;
+	func_swing	get_delta_swing_table;
+	func_swing8814only	get_delta_swing_table8814only;
+	func_swing_xtal			get_delta_swing_xtal_table;
+	func_set_xtal			odm_txxtaltrack_set_xtal;
+	func_all_swing	get_delta_all_swing_table;
+};
+
+void
+configure_txpower_track(
+	struct PHY_DM_STRUCT		*p_dm_odm,
+	struct _TXPWRTRACK_CFG	*p_config
+);
+
+
+void
+odm_clear_txpowertracking_state(
+	struct PHY_DM_STRUCT		*p_dm_odm
+);
+
+void
+odm_txpowertracking_callback_thermal_meter(
+#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
+	struct PHY_DM_STRUCT		*p_dm_odm
+#else
+	struct _ADAPTER	*adapter
+#endif
+);
+
+
+
+#define ODM_TARGET_CHNL_NUM_2G_5G	59
+
+
+void
+odm_reset_iqk_result(
+	struct PHY_DM_STRUCT	*p_dm_odm
+);
+u8
+odm_get_right_chnl_place_for_iqk(
+	u8 chnl
+);
+
+void odm_iq_calibrate(struct PHY_DM_STRUCT	*p_dm_odm);
+void phydm_rf_init(struct PHY_DM_STRUCT		*p_dm_odm);
+void phydm_rf_watchdog(struct PHY_DM_STRUCT		*p_dm_odm);
+
+#endif	/*  #ifndef __HAL_PHY_RF_H__ */
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/halrf/halphyrf_ap.c linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/halrf/halphyrf_ap.c
--- linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/halrf/halphyrf_ap.c	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/halrf/halphyrf_ap.c	2020-04-10 16:35:06.818660161 +0300
@@ -0,0 +1,1340 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+
+#include "mp_precomp.h"
+#include "phydm_precomp.h"
+
+#ifndef index_mapping_NUM_88E
+	#define	index_mapping_NUM_88E	15
+#endif
+
+/* #if(DM_ODM_SUPPORT_TYPE & ODM_WIN) */
+
+#define	CALCULATE_SWINGTALBE_OFFSET(_offset, _direction, _size, _delta_thermal) \
+	do {\
+		for (_offset = 0; _offset < _size; _offset++) { \
+			\
+			if (_delta_thermal < thermal_threshold[_direction][_offset]) { \
+				\
+				if (_offset != 0)\
+					_offset--;\
+				break;\
+			} \
+		}			\
+		if (_offset >= _size)\
+			_offset = _size-1;\
+	} while (0)
+
+
+void configure_txpower_track(
+	void		*dm_void,
+	struct txpwrtrack_cfg	*config
+)
+{
+	struct dm_struct		*dm = (struct dm_struct *)dm_void;
+#if RTL8812A_SUPPORT
+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
+	/* if (IS_HARDWARE_TYPE_8812(dm->adapter)) */
+	if (dm->support_ic_type == ODM_RTL8812)
+		configure_txpower_track_8812a(config);
+	/* else */
+#endif
+#endif
+
+#if RTL8814A_SUPPORT
+	if (dm->support_ic_type == ODM_RTL8814A)
+		configure_txpower_track_8814a(config);
+#endif
+
+
+#if RTL8188E_SUPPORT
+	if (dm->support_ic_type == ODM_RTL8188E)
+		configure_txpower_track_8188e(config);
+#endif
+
+#if RTL8197F_SUPPORT
+	if (dm->support_ic_type == ODM_RTL8197F)
+		configure_txpower_track_8197f(config);
+#endif
+
+#if RTL8822B_SUPPORT
+	if (dm->support_ic_type == ODM_RTL8822B)
+		configure_txpower_track_8822b(config);
+#endif
+
+#if RTL8192F_SUPPORT
+	if (dm->support_ic_type == ODM_RTL8192F)
+		configure_txpower_track_8192f(config);
+#endif
+
+#if RTL8198F_SUPPORT
+	if (dm->support_ic_type == ODM_RTL8198F)
+		configure_txpower_track_8198f(config);
+#endif
+
+}
+
+#if (RTL8192E_SUPPORT == 1)
+void
+odm_txpowertracking_callback_thermal_meter_92e(
+	void		*dm_void
+)
+{
+	struct dm_struct		*dm = (struct dm_struct *)dm_void;
+	struct dm_iqk_info	*iqk_info = &dm->IQK_info;
+	u8	thermal_value = 0, delta, delta_IQK, delta_LCK, channel, is_decrease, rf_mimo_mode;
+	u8	thermal_value_avg_count = 0;
+	u8     OFDM_min_index = 10; /* OFDM BB Swing should be less than +2.5dB, which is required by Arthur */
+	s8	OFDM_index[2], index ;
+	u32	thermal_value_avg = 0, reg0x18;
+	u32	i = 0, j = 0, rf;
+	s32	value32, CCK_index = 0, ele_A, ele_D, ele_C, X, Y;
+	struct rtl8192cd_priv	*priv = dm->priv;
+
+	rf_mimo_mode = dm->rf_type;
+	/* RF_DBG(dm,DBG_RF_TX_PWR_TRACK,"%s:%d rf_mimo_mode:%d\n", __FUNCTION__, __LINE__, rf_mimo_mode); */
+
+#ifdef MP_TEST
+	if ((OPMODE & WIFI_MP_STATE) || *(dm->mp_mode)) {
+		channel = priv->pshare->working_channel;
+		if (priv->pshare->mp_txpwr_tracking == false)
+			return;
+	} else
+#endif
+	{
+		channel = (priv->pmib->dot11RFEntry.dot11channel);
+	}
+
+	thermal_value = (unsigned char)odm_get_rf_reg(dm, RF_PATH_A, ODM_RF_T_METER_92E, 0xfc00);	/* 0x42: RF Reg[15:10] 88E */
+	RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "\nReadback Thermal Meter = 0x%x pre thermal meter 0x%x EEPROMthermalmeter 0x%x\n", thermal_value, priv->pshare->thermal_value, priv->pmib->dot11RFEntry.ther);
+
+
+	switch (rf_mimo_mode) {
+	case RF_1T1R:
+		rf = 1;
+		break;
+	case RF_2T2R:
+		rf = 2;
+		break;
+	default:
+		rf = 2;
+		break;
+	}
+
+	/* Query OFDM path A default setting 	Bit[31:21] */
+	ele_D = phy_query_bb_reg(priv, REG_OFDM_0_XA_TX_IQ_IMBALANCE, MASKOFDM_D);
+	for (i = 0; i < OFDM_TABLE_SIZE_92E; i++) {
+		if (ele_D == (ofdm_swing_table_92e[i] >> 22)) {
+			OFDM_index[0] = (unsigned char)i;
+			RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "PathA 0xC80[31:22] = 0x%x, OFDM_index=%d\n", ele_D, OFDM_index[0]);
+			break;
+		}
+	}
+
+	/* Query OFDM path B default setting */
+	if (rf_mimo_mode == RF_2T2R) {
+		ele_D = phy_query_bb_reg(priv, REG_OFDM_0_XB_TX_IQ_IMBALANCE, MASKOFDM_D);
+		for (i = 0; i < OFDM_TABLE_SIZE_92E; i++) {
+			if (ele_D == (ofdm_swing_table_92e[i] >> 22)) {
+				OFDM_index[1] = (unsigned char)i;
+				RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "PathB 0xC88[31:22] = 0x%x, OFDM_index=%d\n", ele_D, OFDM_index[1]);
+				break;
+			}
+		}
+	}
+
+	/* calculate average thermal meter */
+	{
+		priv->pshare->thermal_value_avg_88xx[priv->pshare->thermal_value_avg_index_88xx] = thermal_value;
+		priv->pshare->thermal_value_avg_index_88xx++;
+		if (priv->pshare->thermal_value_avg_index_88xx == AVG_THERMAL_NUM_88XX)
+			priv->pshare->thermal_value_avg_index_88xx = 0;
+
+		for (i = 0; i < AVG_THERMAL_NUM_88XX; i++) {
+			if (priv->pshare->thermal_value_avg_88xx[i]) {
+				thermal_value_avg += priv->pshare->thermal_value_avg_88xx[i];
+				thermal_value_avg_count++;
+			}
+		}
+
+		if (thermal_value_avg_count) {
+			thermal_value = (unsigned char)(thermal_value_avg / thermal_value_avg_count);
+			RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "AVG Thermal Meter = 0x%x\n", thermal_value);
+		}
+	}
+
+	/* Initialize */
+	if (!priv->pshare->thermal_value) {
+		priv->pshare->thermal_value = priv->pmib->dot11RFEntry.ther;
+		priv->pshare->thermal_value_iqk = thermal_value;
+		priv->pshare->thermal_value_lck = thermal_value;
+	}
+
+	if (thermal_value != priv->pshare->thermal_value) {
+		RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "\n******** START POWER TRACKING ********\n");
+		RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "\nReadback Thermal Meter = 0x%x pre thermal meter 0x%x EEPROMthermalmeter 0x%x\n", thermal_value, priv->pshare->thermal_value, priv->pmib->dot11RFEntry.ther);
+
+		delta = RTL_ABS(thermal_value, priv->pmib->dot11RFEntry.ther);
+		delta_IQK = RTL_ABS(thermal_value, priv->pshare->thermal_value_iqk);
+		delta_LCK = RTL_ABS(thermal_value, priv->pshare->thermal_value_lck);
+		is_decrease = ((thermal_value < priv->pmib->dot11RFEntry.ther) ? 1 : 0);
+
+#ifdef _TRACKING_TABLE_FILE
+		if (priv->pshare->rf_ft_var.pwr_track_file) {
+			RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "diff: (%s)%d ==> get index from table : %d)\n", (is_decrease ? "-" : "+"), delta, get_tx_tracking_index(priv, channel, i, delta, is_decrease, 0));
+
+			if (is_decrease) {
+				for (i = 0; i < rf; i++) {
+					OFDM_index[i] = priv->pshare->OFDM_index0[i] + get_tx_tracking_index(priv, channel, i, delta, is_decrease, 0);
+					OFDM_index[i] = ((OFDM_index[i] > (OFDM_TABLE_SIZE_92E- 1)) ? (OFDM_TABLE_SIZE_92E - 1) : OFDM_index[i]);
+					RF_DBG(dm, DBG_RF_TX_PWR_TRACK, ">>> decrese power ---> new OFDM_INDEX:%d (%d + %d)\n", OFDM_index[i], priv->pshare->OFDM_index0[i], get_tx_tracking_index(priv, channel, i, delta, is_decrease, 0));
+					CCK_index = priv->pshare->CCK_index0 + get_tx_tracking_index(priv, channel, i, delta, is_decrease, 1);
+					CCK_index = ((CCK_index > (CCK_TABLE_SIZE_92E - 1)) ? (CCK_TABLE_SIZE_92E - 1) : CCK_index);
+					RF_DBG(dm, DBG_RF_TX_PWR_TRACK, ">>> Decrese power ---> new CCK_INDEX:%d (%d + %d)\n",  CCK_index, priv->pshare->CCK_index0, get_tx_tracking_index(priv, channel, i, delta, is_decrease, 1));
+				}
+			} else {
+				for (i = 0; i < rf; i++) {
+					OFDM_index[i] = priv->pshare->OFDM_index0[i] - get_tx_tracking_index(priv, channel, i, delta, is_decrease, 0);
+					OFDM_index[i] = ((OFDM_index[i] < OFDM_min_index) ?  OFDM_min_index : OFDM_index[i]);
+					RF_DBG(dm, DBG_RF_TX_PWR_TRACK, ">>> Increse power ---> new OFDM_INDEX:%d (%d - %d)\n", OFDM_index[i], priv->pshare->OFDM_index0[i], get_tx_tracking_index(priv, channel, i, delta, is_decrease, 0));
+					CCK_index = priv->pshare->CCK_index0 - get_tx_tracking_index(priv, channel, i, delta, is_decrease, 1);
+					CCK_index = ((CCK_index < 0) ? 0 : CCK_index);
+					RF_DBG(dm, DBG_RF_TX_PWR_TRACK, ">>> Increse power ---> new CCK_INDEX:%d (%d - %d)\n", CCK_index, priv->pshare->CCK_index0, get_tx_tracking_index(priv, channel, i, delta, is_decrease, 1));
+				}
+			}
+		}
+#endif /* CFG_TRACKING_TABLE_FILE */
+
+		RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "ofdm_swing_table_92e[(unsigned int)OFDM_index[0]] = %x\n", ofdm_swing_table_92e[(unsigned int)OFDM_index[0]]);
+		RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "ofdm_swing_table_92e[(unsigned int)OFDM_index[1]] = %x\n", ofdm_swing_table_92e[(unsigned int)OFDM_index[1]]);
+
+		/* Adujst OFDM Ant_A according to IQK result */
+		ele_D = (ofdm_swing_table_92e[(unsigned int)OFDM_index[0]] & 0xFFC00000) >> 22;
+		X = priv->pshare->rege94;
+		Y = priv->pshare->rege9c;
+
+		if (X != 0) {
+			if ((X & 0x00000200) != 0)
+				X = X | 0xFFFFFC00;
+			ele_A = ((X * ele_D) >> 8) & 0x000003FF;
+
+			/* new element C = element D x Y */
+			if ((Y & 0x00000200) != 0)
+				Y = Y | 0xFFFFFC00;
+			ele_C = ((Y * ele_D) >> 8) & 0x000003FF;
+
+			/* wirte new elements A, C, D to regC80 and regC94, element B is always 0 */
+			value32 = (ele_D << 22) | ((ele_C & 0x3F) << 16) | ele_A;
+			phy_set_bb_reg(priv, REG_OFDM_0_XA_TX_IQ_IMBALANCE, MASKDWORD, value32);
+
+			value32 = (ele_C & 0x000003C0) >> 6;
+			phy_set_bb_reg(priv, REG_OFDM_0_XC_TX_AFE, MASKH4BITS, value32);
+
+			value32 = ((X * ele_D) >> 7) & 0x01;
+			phy_set_bb_reg(priv, REG_OFDM_0_ECCA_THRESHOLD, BIT(24), value32);
+		} else {
+			phy_set_bb_reg(priv, REG_OFDM_0_XA_TX_IQ_IMBALANCE, MASKDWORD, ofdm_swing_table_92e[(unsigned int)OFDM_index[0]]);
+			phy_set_bb_reg(priv, REG_OFDM_0_XC_TX_AFE, MASKH4BITS, 0x00);
+			phy_set_bb_reg(priv, REG_OFDM_0_ECCA_THRESHOLD, BIT(24), 0x00);
+		}
+
+		set_CCK_swing_index(priv, CCK_index);
+
+		if (rf == 2) {
+			ele_D = (ofdm_swing_table_92e[(unsigned int)OFDM_index[1]] & 0xFFC00000) >> 22;
+			X = priv->pshare->regeb4;
+			Y = priv->pshare->regebc;
+
+			if (X != 0) {
+				if ((X & 0x00000200) != 0)	/* consider minus */
+					X = X | 0xFFFFFC00;
+				ele_A = ((X * ele_D) >> 8) & 0x000003FF;
+
+				/* new element C = element D x Y */
+				if ((Y & 0x00000200) != 0)
+					Y = Y | 0xFFFFFC00;
+				ele_C = ((Y * ele_D) >> 8) & 0x00003FF;
+
+				/* wirte new elements A, C, D to regC88 and regC9C, element B is always 0 */
+				value32 = (ele_D << 22) | ((ele_C & 0x3F) << 16) | ele_A;
+				phy_set_bb_reg(priv, REG_OFDM_0_XB_TX_IQ_IMBALANCE, MASKDWORD, value32);
+
+				value32 = (ele_C & 0x000003C0) >> 6;
+				phy_set_bb_reg(priv, REG_OFDM_0_XD_TX_AFE, MASKH4BITS, value32);
+
+				value32 = ((X * ele_D) >> 7) & 0x01;
+				phy_set_bb_reg(priv, REG_OFDM_0_ECCA_THRESHOLD, BIT(28), value32);
+			} else {
+				phy_set_bb_reg(priv, REG_OFDM_0_XB_TX_IQ_IMBALANCE, MASKDWORD, ofdm_swing_table_92e[(unsigned int)OFDM_index[1]]);
+				phy_set_bb_reg(priv, REG_OFDM_0_XD_TX_AFE, MASKH4BITS, 0x00);
+				phy_set_bb_reg(priv, REG_OFDM_0_ECCA_THRESHOLD, BIT(28), 0x00);
+			}
+
+		}
+
+		RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "0xc80 = 0x%x\n", phy_query_bb_reg(priv, REG_OFDM_0_XA_TX_IQ_IMBALANCE, MASKDWORD));
+		RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "0xc88 = 0x%x\n", phy_query_bb_reg(priv, REG_OFDM_0_XB_TX_IQ_IMBALANCE, MASKDWORD));
+
+		if ((delta_IQK > 3) && (!iqk_info->rfk_forbidden)) {
+			priv->pshare->thermal_value_iqk = thermal_value;
+#ifdef MP_TEST
+#endif			if (!(*(dm->mp_mode) && (OPMODE & (WIFI_MP_CTX_BACKGROUND | WIFI_MP_CTX_PACKET))))
+
+				halrf_iqk_trigger(dm, false);
+		}
+
+		if ((delta_LCK > 8)  && (!iqk_info->rfk_forbidden)) {
+			RTL_W8(0x522, 0xff);
+			reg0x18 = phy_query_rf_reg(priv, RF_PATH_A, 0x18, MASK20BITS, 1);
+			phy_set_rf_reg(priv, RF_PATH_A, 0xB4, BIT(14), 1);
+			phy_set_rf_reg(priv, RF_PATH_A, 0x18, BIT(15), 1);
+			delay_ms(1);
+			phy_set_rf_reg(priv, RF_PATH_A, 0xB4, BIT(14), 0);
+			phy_set_rf_reg(priv, RF_PATH_A, 0x18, MASK20BITS, reg0x18);
+			RTL_W8(0x522, 0x0);
+			priv->pshare->thermal_value_lck = thermal_value;
+		}
+	}
+
+	/* update thermal meter value */
+	priv->pshare->thermal_value = thermal_value;
+	for (i = 0 ; i < rf ; i++)
+		priv->pshare->OFDM_index[i] = OFDM_index[i];
+	priv->pshare->CCK_index = CCK_index;
+
+	RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "\n******** END:%s() ********\n", __FUNCTION__);
+}
+#endif
+
+
+
+#if (RTL8197F_SUPPORT == 1 || RTL8192F_SUPPORT == 1 || RTL8822B_SUPPORT == 1 ||\
+	RTL8821C_SUPPORT == 1 || RTL8198F_SUPPORT == 1)
+void
+odm_txpowertracking_callback_thermal_meter_jaguar_series3(
+	void		*dm_void
+)
+{
+#if 1
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	u8 thermal_value = 0, delta, delta_LCK, delta_IQK, channel, is_increase;
+	u8 thermal_value_avg_count = 0, p = 0, i = 0;
+	u32 thermal_value_avg = 0;
+	struct rtl8192cd_priv *priv = dm->priv;
+	struct txpwrtrack_cfg c;
+	struct dm_rf_calibration_struct *cali_info = &(dm->rf_calibrate_info);
+	struct dm_iqk_info *iqk_info = &dm->IQK_info;
+	struct _hal_rf_ *rf = &dm->rf_table;
+	/*The following tables decide the final index of OFDM/CCK swing table.*/
+	u8 *pwrtrk_tab_up_a = NULL, *pwrtrk_tab_down_a = NULL;
+	u8 *pwrtrk_tab_up_b = NULL, *pwrtrk_tab_down_b = NULL;
+	u8 *pwrtrk_tab_up_cck_a = NULL, *pwrtrk_tab_down_cck_a = NULL;
+	u8 *pwrtrk_tab_up_cck_b = NULL, *pwrtrk_tab_down_cck_b = NULL;
+	/*for 8814 add by Yu Chen*/
+	u8 *pwrtrk_tab_up_c = NULL, *pwrtrk_tab_down_c = NULL;
+	u8 *pwrtrk_tab_up_d = NULL, *pwrtrk_tab_down_d = NULL;
+	u8 *pwrtrk_tab_up_cck_c = NULL, *pwrtrk_tab_down_cck_c = NULL;
+	u8 *pwrtrk_tab_up_cck_d = NULL, *pwrtrk_tab_down_cck_d = NULL;
+
+#ifdef MP_TEST
+	if ((OPMODE & WIFI_MP_STATE) || *(dm->mp_mode)) {
+		channel = priv->pshare->working_channel;
+		if (priv->pshare->mp_txpwr_tracking == false)
+			return;
+	} else
+#endif
+	{
+		channel = (priv->pmib->dot11RFEntry.dot11channel);
+	}
+
+	configure_txpower_track(dm, &c);
+
+	(*c.get_delta_all_swing_table)(dm,
+		(u8 **)&pwrtrk_tab_up_a, (u8 **)&pwrtrk_tab_down_a,
+		(u8 **)&pwrtrk_tab_up_b, (u8 **)&pwrtrk_tab_down_b,
+		(u8 **)&pwrtrk_tab_up_cck_a, (u8 **)&pwrtrk_tab_down_cck_a,
+		(u8 **)&pwrtrk_tab_up_cck_b, (u8 **)&pwrtrk_tab_down_cck_b);
+
+	if (GET_CHIP_VER(priv) == VERSION_8198F) {
+		(*c.get_delta_all_swing_table_ex)(dm,
+			(u8 **)&pwrtrk_tab_up_c, (u8 **)&pwrtrk_tab_down_c,
+			(u8 **)&pwrtrk_tab_up_d, (u8 **)&pwrtrk_tab_down_d,
+			(u8 **)&pwrtrk_tab_up_cck_c, (u8 **)&pwrtrk_tab_down_cck_c,
+			(u8 **)&pwrtrk_tab_up_cck_d, (u8 **)&pwrtrk_tab_down_cck_d);
+	}
+	/*0x42: RF Reg[15:10] 88E*/
+	thermal_value = (u8)odm_get_rf_reg(dm, RF_PATH_A, c.thermal_reg_addr, 0xfc00);
+#ifdef THER_TRIM
+	if (GET_CHIP_VER(priv) == VERSION_8197F) {
+		RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"orig thermal_value=%d, ther_trim_val=%d\n", thermal_value, priv->pshare->rf_ft_var.ther_trim_val);
+
+		thermal_value += priv->pshare->rf_ft_var.ther_trim_val;
+
+		RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"after thermal trim, thermal_value=%d\n", thermal_value);
+	}
+#endif
+	RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"\n\n\nCurrent Thermal = 0x%x(%d) EEPROMthermalmeter 0x%x(%d)\n"
+		, thermal_value, thermal_value, priv->pmib->dot11RFEntry.ther, priv->pmib->dot11RFEntry.ther);
+
+	/* Initialize */
+	if (!dm->rf_calibrate_info.thermal_value)
+		dm->rf_calibrate_info.thermal_value = priv->pmib->dot11RFEntry.ther;
+
+	if (!dm->rf_calibrate_info.thermal_value_lck)
+		dm->rf_calibrate_info.thermal_value_lck = priv->pmib->dot11RFEntry.ther;
+
+	if (!dm->rf_calibrate_info.thermal_value_iqk)
+		dm->rf_calibrate_info.thermal_value_iqk = priv->pmib->dot11RFEntry.ther;
+
+	/* calculate average thermal meter */
+	dm->rf_calibrate_info.thermal_value_avg[dm->rf_calibrate_info.thermal_value_avg_index] = thermal_value;
+	dm->rf_calibrate_info.thermal_value_avg_index++;
+
+	if (dm->rf_calibrate_info.thermal_value_avg_index == c.average_thermal_num)   /*Average times =  c.average_thermal_num*/
+		dm->rf_calibrate_info.thermal_value_avg_index = 0;
+
+	for (i = 0; i < c.average_thermal_num; i++) {
+		if (dm->rf_calibrate_info.thermal_value_avg[i]) {
+			thermal_value_avg += dm->rf_calibrate_info.thermal_value_avg[i];
+			thermal_value_avg_count++;
+		}
+	}
+
+	if (thermal_value_avg_count) {/*Calculate Average thermal_value after average enough times*/
+		RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"thermal_value_avg=0x%x(%d)  thermal_value_avg_count = %d\n"
+			, thermal_value_avg, thermal_value_avg, thermal_value_avg_count);
+
+		thermal_value = (u8)(thermal_value_avg / thermal_value_avg_count);
+
+		RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"AVG Thermal Meter = 0x%X(%d), EEPROMthermalmeter = 0x%X(%d)\n", thermal_value, thermal_value, priv->pmib->dot11RFEntry.ther, priv->pmib->dot11RFEntry.ther);
+	}
+
+	/*4 Calculate delta, delta_LCK, delta_IQK.*/
+	delta = RTL_ABS(thermal_value, priv->pmib->dot11RFEntry.ther);
+	delta_LCK = RTL_ABS(thermal_value, dm->rf_calibrate_info.thermal_value_lck);
+	delta_IQK = RTL_ABS(thermal_value, dm->rf_calibrate_info.thermal_value_iqk);
+	is_increase = ((thermal_value < priv->pmib->dot11RFEntry.ther) ? 0 : 1);
+
+	if (delta > 29) { /* power track table index(thermal diff.) upper bound*/
+		RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "delta(%d) > 29, set delta to 29\n", delta);
+		delta = 29;
+	}
+
+	RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "(delta, delta_LCK, delta_IQK) = (%d, %d, %d)\n", delta, delta_LCK, delta_IQK);
+
+	/*4 if necessary, do LCK.*/
+	if ((delta_LCK >= c.threshold_iqk) && (!iqk_info->rfk_forbidden)) {
+		RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "delta_LCK(%d) >= threshold_iqk(%d)\n", delta_LCK, c.threshold_iqk);
+		dm->rf_calibrate_info.thermal_value_lck = thermal_value;
+#if (RTL8822B_SUPPORT != 1)
+		if (!(dm->support_ic_type & ODM_RTL8822B)) {
+			if (c.phy_lc_calibrate)
+				(*c.phy_lc_calibrate)(dm);
+		}
+#endif
+	}
+
+	if (!priv->pmib->dot11RFEntry.ther) /*Don't do power tracking since no calibrated thermal value*/
+		return;
+
+	/*4 Do Power Tracking*/
+
+	if (thermal_value != dm->rf_calibrate_info.thermal_value) {
+		RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"******** START POWER TRACKING ********\n");
+		RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"Readback Thermal Meter = 0x%x pre thermal meter 0x%x EEPROMthermalmeter 0x%x\n",
+		       thermal_value, dm->rf_calibrate_info.thermal_value, priv->pmib->dot11RFEntry.ther);
+
+#ifdef _TRACKING_TABLE_FILE
+		if (priv->pshare->rf_ft_var.pwr_track_file) {
+			if (is_increase) { /*thermal is higher than base*/
+				for (p = RF_PATH_A; p < c.rf_path_count; p++) {
+					switch (p) {
+					case RF_PATH_B:
+						RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"pwrtrk_tab_up_b[%d] = %d pwrtrk_tab_up_cck_b[%d] = %d\n", delta, pwrtrk_tab_up_b[delta], delta, pwrtrk_tab_up_cck_b[delta]);
+						cali_info->absolute_ofdm_swing_idx[p] = pwrtrk_tab_up_b[delta];
+						cali_info->absolute_cck_swing_idx[p] = pwrtrk_tab_up_cck_b[delta];
+						RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"******Temp is higher and pRF->absolute_ofdm_swing_idx[RF_PATH_B] = %d pRF->absolute_cck_swing_idx[RF_PATH_B] = %d\n", cali_info->absolute_ofdm_swing_idx[p], cali_info->absolute_cck_swing_idx[p]);
+						break;
+
+					case RF_PATH_C:
+						RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"pwrtrk_tab_up_c[%d] = %d pwrtrk_tab_up_cck_c[%d] = %d\n", delta, pwrtrk_tab_up_c[delta], delta, pwrtrk_tab_up_cck_c[delta]);
+						cali_info->absolute_ofdm_swing_idx[p] = pwrtrk_tab_up_c[delta];
+						cali_info->absolute_cck_swing_idx[p] = pwrtrk_tab_up_cck_c[delta];
+						RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"******Temp is higher and pRF->absolute_ofdm_swing_idx[RF_PATH_C] = %d pRF->absolute_cck_swing_idx[RF_PATH_C] = %d\n", cali_info->absolute_ofdm_swing_idx[p], cali_info->absolute_cck_swing_idx[p]);
+						break;
+
+					case RF_PATH_D:
+						RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"pwrtrk_tab_up_d[%d] = %d pwrtrk_tab_up_cck_d[%d] = %d\n", delta, pwrtrk_tab_up_d[delta], delta, pwrtrk_tab_up_cck_d[delta]);
+						cali_info->absolute_ofdm_swing_idx[p] = pwrtrk_tab_up_d[delta];
+						cali_info->absolute_cck_swing_idx[p] = pwrtrk_tab_up_cck_d[delta];
+						RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"******Temp is higher and pRF->absolute_ofdm_swing_idx[RF_PATH_D] = %d pRF->absolute_cck_swing_idx[RF_PATH_D] = %d\n", cali_info->absolute_ofdm_swing_idx[p], cali_info->absolute_cck_swing_idx[p]);
+						break;
+					default:
+						RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"pwrtrk_tab_up_a[%d] = %d pwrtrk_tab_up_cck_a[%d] = %d\n", delta, pwrtrk_tab_up_a[delta], delta, pwrtrk_tab_up_cck_a[delta]);
+						cali_info->absolute_ofdm_swing_idx[p] = pwrtrk_tab_up_a[delta];
+						cali_info->absolute_cck_swing_idx[p] = pwrtrk_tab_up_cck_a[delta];
+						RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"******Temp is higher and pRF->absolute_ofdm_swing_idx[RF_PATH_A] = %d pRF->absolute_cck_swing_idx[RF_PATH_A] = %d\n", cali_info->absolute_ofdm_swing_idx[p], cali_info->absolute_cck_swing_idx[p]);
+						break;
+					}
+				}
+			} else { /* thermal is lower than base*/
+				for (p = RF_PATH_A; p < c.rf_path_count; p++) {
+					switch (p) {
+					case RF_PATH_B:
+						RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"pwrtrk_tab_down_b[%d] = %d   pwrtrk_tab_down_cck_b[%d] = %d\n", delta, pwrtrk_tab_down_b[delta], delta, pwrtrk_tab_down_cck_b[delta]);
+						cali_info->absolute_ofdm_swing_idx[p] = -1 * pwrtrk_tab_down_b[delta];
+						cali_info->absolute_cck_swing_idx[p] = -1 * pwrtrk_tab_down_cck_b[delta];
+						RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"******Temp is lower and pRF->absolute_ofdm_swing_idx[RF_PATH_B] = %d   pRF->absolute_cck_swing_idx[RF_PATH_B] = %d\n", cali_info->absolute_ofdm_swing_idx[p], cali_info->absolute_cck_swing_idx[p]);
+						break;
+
+					case RF_PATH_C:
+						RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"pwrtrk_tab_down_c[%d] = %d   pwrtrk_tab_down_cck_c[%d] = %d\n", delta, pwrtrk_tab_down_c[delta], delta, pwrtrk_tab_down_cck_c[delta]);
+						cali_info->absolute_ofdm_swing_idx[p] = -1 * pwrtrk_tab_down_c[delta];
+						cali_info->absolute_cck_swing_idx[p] = -1 * pwrtrk_tab_down_cck_c[delta];
+						RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"******Temp is lower and pRF->absolute_ofdm_swing_idx[RF_PATH_C] = %d   pRF->absolute_cck_swing_idx[RF_PATH_C] = %d\n", cali_info->absolute_ofdm_swing_idx[p], cali_info->absolute_cck_swing_idx[p]);
+						break;
+
+					case RF_PATH_D:
+						RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"pwrtrk_tab_down_d[%d] = %d   pwrtrk_tab_down_cck_d[%d] = %d\n", delta, pwrtrk_tab_down_d[delta], delta, pwrtrk_tab_down_cck_d[delta]);
+						cali_info->absolute_ofdm_swing_idx[p] = -1 * pwrtrk_tab_down_d[delta];
+						cali_info->absolute_cck_swing_idx[p] = -1 * pwrtrk_tab_down_cck_d[delta];
+						RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"******Temp is lower and pRF->absolute_ofdm_swing_idx[RF_PATH_D] = %d   pRF->absolute_cck_swing_idx[RF_PATH_D] = %d\n", cali_info->absolute_ofdm_swing_idx[p], cali_info->absolute_cck_swing_idx[p]);
+						break;
+
+					default:
+						RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"pwrtrk_tab_down_a[%d] = %d   pwrtrk_tab_down_cck_a[%d] = %d\n", delta, pwrtrk_tab_down_a[delta], delta, pwrtrk_tab_down_cck_a[delta]);
+						cali_info->absolute_ofdm_swing_idx[p] = -1 * pwrtrk_tab_down_a[delta];
+						cali_info->absolute_cck_swing_idx[p] = -1 * pwrtrk_tab_down_cck_a[delta];
+						RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"******Temp is lower and pRF->absolute_ofdm_swing_idx[RF_PATH_A] = %d   pRF->absolute_cck_swing_idx[RF_PATH_A] = %d\n", cali_info->absolute_ofdm_swing_idx[p], cali_info->absolute_cck_swing_idx[p]);
+						break;
+					}
+				}
+			}
+
+			if (is_increase) {
+				RF_DBG(dm, DBG_RF_TX_PWR_TRACK, ">>> increse power --->\n");
+				if (GET_CHIP_VER(priv) == VERSION_8197F) {
+					for (p = RF_PATH_A; p < c.rf_path_count; p++)
+						(*c.odm_tx_pwr_track_set_pwr)(dm, BBSWING, p, 0);
+				//}  else if (GET_CHIP_VER(priv) == VERSION_8192F) {
+				//	for (p = RF_PATH_A; p < c.rf_path_count; p++)
+				//		(*c.odm_tx_pwr_track_set_pwr)(dm, MIX_MODE, p, 0);
+				} else if (GET_CHIP_VER(priv) == VERSION_8822B) {
+					for (p = RF_PATH_A; p < c.rf_path_count; p++)
+						(*c.odm_tx_pwr_track_set_pwr)(dm, MIX_MODE, p, 0);
+				} else if (GET_CHIP_VER(priv) == VERSION_8821C) {
+					for (p = RF_PATH_A; p < c.rf_path_count; p++)
+						(*c.odm_tx_pwr_track_set_pwr)(dm, MIX_MODE, p, 0);
+				}  else if (GET_CHIP_VER(priv) == VERSION_8198F) {
+					for (p = RF_PATH_A; p < c.rf_path_count; p++)
+						(*c.odm_tx_pwr_track_set_pwr)(dm, MIX_MODE, p, 0);
+				}
+			} else {
+				RF_DBG(dm, DBG_RF_TX_PWR_TRACK, ">>> decrese power --->\n");
+				if (GET_CHIP_VER(priv) == VERSION_8197F) {
+					for (p = RF_PATH_A; p < c.rf_path_count; p++)
+						(*c.odm_tx_pwr_track_set_pwr)(dm, BBSWING, p, 0);
+				//} else if (GET_CHIP_VER(priv) == VERSION_8192F) {
+				//	for (p = RF_PATH_A; p < c.rf_path_count; p++)
+				//		(*c.odm_tx_pwr_track_set_pwr)(dm, MIX_MODE, p, 0);
+				} else if (GET_CHIP_VER(priv) == VERSION_8822B) {
+					for (p = RF_PATH_A; p < c.rf_path_count; p++)
+						(*c.odm_tx_pwr_track_set_pwr)(dm, MIX_MODE, p, 0);
+				} else if (GET_CHIP_VER(priv) == VERSION_8821C) {
+					for (p = RF_PATH_A; p < c.rf_path_count; p++)
+						(*c.odm_tx_pwr_track_set_pwr)(dm, MIX_MODE, p, 0);
+				} else if (GET_CHIP_VER(priv) == VERSION_8198F) {
+					for (p = RF_PATH_A; p < c.rf_path_count; p++)
+						(*c.odm_tx_pwr_track_set_pwr)(dm, MIX_MODE, p, 0);
+				}
+			}
+		}
+#endif
+
+		if (GET_CHIP_VER(priv) != VERSION_8198F) {
+			if ((delta_IQK >= c.threshold_iqk) && (!iqk_info->rfk_forbidden)) {
+				RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "delta_IQK(%d) >= threshold_iqk(%d)\n", delta_IQK, c.threshold_iqk);
+				dm->rf_calibrate_info.thermal_value_iqk = thermal_value;
+				if (c.do_iqk)
+					(*c.do_iqk)(dm, false, thermal_value, 0);
+			}
+		}
+
+		RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "\n******** END:%s() ********\n\n", __func__);
+		/*update thermal meter value*/
+		dm->rf_calibrate_info.thermal_value =  thermal_value;
+
+	}
+
+#endif
+}
+#endif
+
+/*#if (RTL8814A_SUPPORT == 1)*/
+#if (RTL8814A_SUPPORT == 1)
+
+void
+odm_txpowertracking_callback_thermal_meter_jaguar_series2(
+	void		*dm_void
+)
+{
+	struct dm_struct		*dm = (struct dm_struct *)dm_void;
+	u8			thermal_value = 0, delta, delta_LCK, delta_IQK, channel, is_increase;
+	u8			thermal_value_avg_count = 0, p = 0, i = 0;
+	u32			thermal_value_avg = 0, reg0x18;
+	u32			bb_swing_reg[4] = {REG_A_TX_SCALE_JAGUAR, REG_B_TX_SCALE_JAGUAR, REG_C_TX_SCALE_JAGUAR2, REG_D_TX_SCALE_JAGUAR2};
+	s32			ele_D;
+	u32			bb_swing_idx;
+	struct rtl8192cd_priv	*priv = dm->priv;
+	struct txpwrtrack_cfg	c;
+	boolean			is_tssi_enable = false;
+	struct dm_rf_calibration_struct	*cali_info = &(dm->rf_calibrate_info);
+	struct dm_iqk_info	*iqk_info = &dm->IQK_info;
+
+	/* 4 1. The following TWO tables decide the final index of OFDM/CCK swing table. */
+	u8			*delta_swing_table_idx_tup_a = NULL, *delta_swing_table_idx_tdown_a = NULL;
+	u8			*delta_swing_table_idx_tup_b = NULL, *delta_swing_table_idx_tdown_b = NULL;
+	/* for 8814 add by Yu Chen */
+	u8			*delta_swing_table_idx_tup_c = NULL, *delta_swing_table_idx_tdown_c = NULL;
+	u8			*delta_swing_table_idx_tup_d = NULL, *delta_swing_table_idx_tdown_d = NULL;
+
+#ifdef MP_TEST
+	if ((OPMODE & WIFI_MP_STATE) || *(dm->mp_mode)) {
+		channel = priv->pshare->working_channel;
+		if (priv->pshare->mp_txpwr_tracking == false)
+			return;
+	} else
+#endif
+	{
+		channel = (priv->pmib->dot11RFEntry.dot11channel);
+	}
+
+	configure_txpower_track(dm, &c);
+	cali_info->default_ofdm_index = priv->pshare->OFDM_index0[RF_PATH_A];
+
+	(*c.get_delta_swing_table)(dm, (u8 **)&delta_swing_table_idx_tup_a, (u8 **)&delta_swing_table_idx_tdown_a,
+		(u8 **)&delta_swing_table_idx_tup_b, (u8 **)&delta_swing_table_idx_tdown_b);
+
+	if (dm->support_ic_type & ODM_RTL8814A)	/* for 8814 path C & D */
+		(*c.get_delta_swing_table8814only)(dm, (u8 **)&delta_swing_table_idx_tup_c, (u8 **)&delta_swing_table_idx_tdown_c,
+			(u8 **)&delta_swing_table_idx_tup_d, (u8 **)&delta_swing_table_idx_tdown_d);
+
+	thermal_value = (u8)odm_get_rf_reg(dm, RF_PATH_A, c.thermal_reg_addr, 0xfc00); /* 0x42: RF Reg[15:10] 88E */
+	RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"\nReadback Thermal Meter = 0x%x, pre thermal meter 0x%x, EEPROMthermalmeter 0x%x\n", thermal_value, dm->rf_calibrate_info.thermal_value, priv->pmib->dot11RFEntry.ther);
+
+	/* Initialize */
+	if (!dm->rf_calibrate_info.thermal_value)
+		dm->rf_calibrate_info.thermal_value = priv->pmib->dot11RFEntry.ther;
+
+	if (!dm->rf_calibrate_info.thermal_value_lck)
+		dm->rf_calibrate_info.thermal_value_lck = priv->pmib->dot11RFEntry.ther;
+
+	if (!dm->rf_calibrate_info.thermal_value_iqk)
+		dm->rf_calibrate_info.thermal_value_iqk = priv->pmib->dot11RFEntry.ther;
+
+	is_tssi_enable = (boolean)odm_get_rf_reg(dm, RF_PATH_A, REG_RF_TX_GAIN_OFFSET, BIT(7));	/* check TSSI enable */
+
+	/* 4 Query OFDM BB swing default setting 	Bit[31:21] */
+	for (p = RF_PATH_A ; p < c.rf_path_count ; p++) {
+		ele_D = odm_get_bb_reg(dm, bb_swing_reg[p], 0xffe00000);
+		RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"0x%x:0x%x ([31:21] = 0x%x)\n", bb_swing_reg[p], odm_get_bb_reg(dm, bb_swing_reg[p], MASKDWORD), ele_D);
+
+		for (bb_swing_idx = 0; bb_swing_idx < TXSCALE_TABLE_SIZE; bb_swing_idx++) {/* 4 */
+			if (ele_D == tx_scaling_table_jaguar[bb_swing_idx]) {
+				dm->rf_calibrate_info.OFDM_index[p] = (u8)bb_swing_idx;
+				RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"OFDM_index[%d]=%d\n", p, dm->rf_calibrate_info.OFDM_index[p]);
+				break;
+			}
+		}
+		RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "kfree_offset[%d]=%d\n", p, cali_info->kfree_offset[p]);
+
+	}
+
+	/* calculate average thermal meter */
+	dm->rf_calibrate_info.thermal_value_avg[dm->rf_calibrate_info.thermal_value_avg_index] = thermal_value;
+	dm->rf_calibrate_info.thermal_value_avg_index++;
+	if (dm->rf_calibrate_info.thermal_value_avg_index == c.average_thermal_num)  /* Average times =  c.average_thermal_num */
+		dm->rf_calibrate_info.thermal_value_avg_index = 0;
+
+	for (i = 0; i < c.average_thermal_num; i++) {
+		if (dm->rf_calibrate_info.thermal_value_avg[i]) {
+			thermal_value_avg += dm->rf_calibrate_info.thermal_value_avg[i];
+			thermal_value_avg_count++;
+		}
+	}
+
+	if (thermal_value_avg_count) {            /* Calculate Average thermal_value after average enough times */
+		thermal_value = (u8)(thermal_value_avg / thermal_value_avg_count);
+		RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"AVG Thermal Meter = 0x%X, EEPROMthermalmeter = 0x%X\n", thermal_value, priv->pmib->dot11RFEntry.ther);
+	}
+
+	/* 4 Calculate delta, delta_LCK, delta_IQK. */
+	delta = RTL_ABS(thermal_value, priv->pmib->dot11RFEntry.ther);
+	delta_LCK = RTL_ABS(thermal_value, dm->rf_calibrate_info.thermal_value_lck);
+	delta_IQK = RTL_ABS(thermal_value, dm->rf_calibrate_info.thermal_value_iqk);
+	is_increase = ((thermal_value < priv->pmib->dot11RFEntry.ther) ? 0 : 1);
+
+	/* 4 if necessary, do LCK. */
+	if (!(dm->support_ic_type & ODM_RTL8821)) {
+		if ((delta_LCK > c.threshold_iqk) && (!iqk_info->rfk_forbidden)) {
+			RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "delta_LCK(%d) >= threshold_iqk(%d)\n", delta_LCK, c.threshold_iqk);
+			dm->rf_calibrate_info.thermal_value_lck = thermal_value;
+
+			/*Use RTLCK, so close power tracking driver LCK*/
+#if (RTL8814A_SUPPORT != 1)
+			if (!(dm->support_ic_type & ODM_RTL8814A)) {
+				if (c.phy_lc_calibrate)
+					(*c.phy_lc_calibrate)(dm);
+			}
+#endif
+		}
+	}
+
+	if ((delta_IQK > c.threshold_iqk) && (!iqk_info->rfk_forbidden)) {
+		panic_printk("%s(%d)\n", __FUNCTION__, __LINE__);
+		RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "delta_IQK(%d) >= threshold_iqk(%d)\n", delta_IQK, c.threshold_iqk);
+		dm->rf_calibrate_info.thermal_value_iqk = thermal_value;
+		if (c.do_iqk)
+			(*c.do_iqk)(dm, true, 0, 0);
+	}
+
+	if (!priv->pmib->dot11RFEntry.ther)	/*Don't do power tracking since no calibrated thermal value*/
+		return;
+
+	/* 4 Do Power Tracking */
+
+	if (is_tssi_enable == true) {
+		RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "**********Enter PURE TSSI MODE**********\n");
+		for (p = RF_PATH_A; p < c.rf_path_count; p++)
+			(*c.odm_tx_pwr_track_set_pwr)(dm, TSSI_MODE, p, 0);
+	} else if (thermal_value != dm->rf_calibrate_info.thermal_value) {
+		RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"\n******** START POWER TRACKING ********\n");
+		RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"\nReadback Thermal Meter = 0x%x pre thermal meter 0x%x EEPROMthermalmeter 0x%x\n", thermal_value, dm->rf_calibrate_info.thermal_value, priv->pmib->dot11RFEntry.ther);
+
+#ifdef _TRACKING_TABLE_FILE
+		if (priv->pshare->rf_ft_var.pwr_track_file) {
+			if (is_increase) {		/* thermal is higher than base */
+				for (p = RF_PATH_A; p < c.rf_path_count; p++) {
+					switch (p) {
+					case RF_PATH_B:
+						RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"delta_swing_table_idx_tup_b[%d] = %d\n", delta, delta_swing_table_idx_tup_b[delta]);
+						cali_info->absolute_ofdm_swing_idx[p] = delta_swing_table_idx_tup_b[delta];       /* Record delta swing for mix mode power tracking */
+						RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"******Temp is higher and dm->absolute_ofdm_swing_idx[RF_PATH_B] = %d\n", cali_info->absolute_ofdm_swing_idx[p]);
+						break;
+
+					case RF_PATH_C:
+						RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"delta_swing_table_idx_tup_c[%d] = %d\n", delta, delta_swing_table_idx_tup_c[delta]);
+						cali_info->absolute_ofdm_swing_idx[p] = delta_swing_table_idx_tup_c[delta];       /* Record delta swing for mix mode power tracking */
+						RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"******Temp is higher and dm->absolute_ofdm_swing_idx[RF_PATH_C] = %d\n", cali_info->absolute_ofdm_swing_idx[p]);
+						break;
+
+					case RF_PATH_D:
+						RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"delta_swing_table_idx_tup_d[%d] = %d\n", delta, delta_swing_table_idx_tup_d[delta]);
+						cali_info->absolute_ofdm_swing_idx[p] = delta_swing_table_idx_tup_d[delta];       /* Record delta swing for mix mode power tracking */
+						RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"******Temp is higher and dm->absolute_ofdm_swing_idx[RF_PATH_D] = %d\n", cali_info->absolute_ofdm_swing_idx[p]);
+						break;
+
+					default:
+						RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"delta_swing_table_idx_tup_a[%d] = %d\n", delta, delta_swing_table_idx_tup_a[delta]);
+						cali_info->absolute_ofdm_swing_idx[p] = delta_swing_table_idx_tup_a[delta];        /* Record delta swing for mix mode power tracking */
+						RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"******Temp is higher and dm->absolute_ofdm_swing_idx[RF_PATH_A] = %d\n", cali_info->absolute_ofdm_swing_idx[p]);
+						break;
+					}
+				}
+			} else {				/* thermal is lower than base */
+				for (p = RF_PATH_A; p < c.rf_path_count; p++) {
+					switch (p) {
+					case RF_PATH_B:
+						RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"delta_swing_table_idx_tdown_b[%d] = %d\n", delta, delta_swing_table_idx_tdown_b[delta]);
+						cali_info->absolute_ofdm_swing_idx[p] = -1 * delta_swing_table_idx_tdown_b[delta];        /* Record delta swing for mix mode power tracking */
+						RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"******Temp is lower and dm->absolute_ofdm_swing_idx[RF_PATH_B] = %d\n", cali_info->absolute_ofdm_swing_idx[p]);
+						break;
+
+					case RF_PATH_C:
+						RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"delta_swing_table_idx_tdown_c[%d] = %d\n", delta, delta_swing_table_idx_tdown_c[delta]);
+						cali_info->absolute_ofdm_swing_idx[p] = -1 * delta_swing_table_idx_tdown_c[delta];        /* Record delta swing for mix mode power tracking */
+						RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"******Temp is lower and dm->absolute_ofdm_swing_idx[RF_PATH_C] = %d\n", cali_info->absolute_ofdm_swing_idx[p]);
+						break;
+
+					case RF_PATH_D:
+						RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"delta_swing_table_idx_tdown_d[%d] = %d\n", delta, delta_swing_table_idx_tdown_d[delta]);
+						cali_info->absolute_ofdm_swing_idx[p] = -1 * delta_swing_table_idx_tdown_d[delta];        /* Record delta swing for mix mode power tracking */
+						RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"******Temp is lower and dm->absolute_ofdm_swing_idx[RF_PATH_D] = %d\n", cali_info->absolute_ofdm_swing_idx[p]);
+						break;
+
+					default:
+						RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"delta_swing_table_idx_tdown_a[%d] = %d\n", delta, delta_swing_table_idx_tdown_a[delta]);
+						cali_info->absolute_ofdm_swing_idx[p] = -1 * delta_swing_table_idx_tdown_a[delta];        /* Record delta swing for mix mode power tracking */
+						RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"******Temp is lower and dm->absolute_ofdm_swing_idx[RF_PATH_A] = %d\n", cali_info->absolute_ofdm_swing_idx[p]);
+						break;
+					}
+				}
+			}
+
+			if (is_increase) {
+				RF_DBG(dm, DBG_RF_TX_PWR_TRACK, ">>> increse power --->\n");
+				for (p = RF_PATH_A; p < c.rf_path_count; p++)
+					(*c.odm_tx_pwr_track_set_pwr)(dm, MIX_MODE, p, 0);
+			} else {
+				RF_DBG(dm, DBG_RF_TX_PWR_TRACK, ">>> decrese power --->\n");
+				for (p = RF_PATH_A; p < c.rf_path_count; p++)
+					(*c.odm_tx_pwr_track_set_pwr)(dm, MIX_MODE, p, 0);
+			}
+		}
+#endif
+
+		RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "\n******** END:%s() ********\n", __FUNCTION__);
+		/* update thermal meter value */
+		dm->rf_calibrate_info.thermal_value =  thermal_value;
+
+	}
+}
+#endif
+
+#if (RTL8812A_SUPPORT == 1 || RTL8881A_SUPPORT == 1)
+void
+odm_txpowertracking_callback_thermal_meter_jaguar_series(
+	void		*dm_void
+)
+{
+	struct dm_struct		*dm = (struct dm_struct *)dm_void;
+	unsigned char			thermal_value = 0, delta, delta_LCK, channel, is_decrease;
+	unsigned char			thermal_value_avg_count = 0;
+	unsigned int			thermal_value_avg = 0, reg0x18;
+	unsigned int			bb_swing_reg[4] = {0xc1c, 0xe1c, 0x181c, 0x1a1c};
+	int					ele_D, value32;
+	char					OFDM_index[2], index;
+	unsigned int			i = 0, j = 0, rf_path, max_rf_path = 2, rf;
+	struct rtl8192cd_priv		*priv = dm->priv;
+	unsigned char			OFDM_min_index = 7; /* OFDM BB Swing should be less than +2.5dB, which is required by Arthur and Mimic */
+	struct dm_iqk_info	*iqk_info = &dm->IQK_info;
+
+
+#ifdef MP_TEST
+	if ((OPMODE & WIFI_MP_STATE) || *(dm->mp_mode)) {
+		channel = priv->pshare->working_channel;
+		if (priv->pshare->mp_txpwr_tracking == false)
+			return;
+	} else
+#endif
+	{
+		channel = (priv->pmib->dot11RFEntry.dot11channel);
+	}
+
+#if RTL8881A_SUPPORT
+	if (dm->support_ic_type == ODM_RTL8881A) {
+		max_rf_path = 1;
+		if ((get_bonding_type_8881A() == BOND_8881AM || get_bonding_type_8881A() == BOND_8881AN)
+		    && priv->pshare->rf_ft_var.use_intpa8881A && (*dm->band_type == ODM_BAND_2_4G))
+			OFDM_min_index = 6;		/* intPA - upper bond set to +3 dB (base: -2 dB)ot11RFEntry.phy_band_select == PHY_BAND_2G)) */
+		else
+			OFDM_min_index = 10;		/* OFDM BB Swing should be less than +1dB, which is required by Arthur and Mimic */
+	}
+#endif
+
+
+	thermal_value = (unsigned char)phy_query_rf_reg(priv, RF_PATH_A, 0x42, 0xfc00, 1); /* 0x42: RF Reg[15:10] 88E */
+	RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "\nReadback Thermal Meter = 0x%x pre thermal meter 0x%x EEPROMthermalmeter 0x%x\n", thermal_value, priv->pshare->thermal_value, priv->pmib->dot11RFEntry.ther);
+
+
+	/* 4 Query OFDM BB swing default setting 	Bit[31:21] */
+	for (rf_path = 0 ; rf_path < max_rf_path ; rf_path++) {
+		ele_D = phy_query_bb_reg(priv, bb_swing_reg[rf_path], 0xffe00000);
+		RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "0x%x:0x%x ([31:21] = 0x%x)\n", bb_swing_reg[rf_path], phy_query_bb_reg(priv, bb_swing_reg[rf_path], MASKDWORD), ele_D);
+		for (i = 0; i < OFDM_TABLE_SIZE_8812; i++) {/* 4 */
+			if (ele_D == ofdm_swing_table_8812[i]) {
+				OFDM_index[rf_path] = (unsigned char)i;
+				RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "OFDM_index[%d]=%d\n", rf_path, OFDM_index[rf_path]);
+				break;
+			}
+		}
+	}
+#if 0
+	/* Query OFDM path A default setting 	Bit[31:21] */
+	ele_D = phy_query_bb_reg(priv, 0xc1c, 0xffe00000);
+	RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "0xc1c:0x%x ([31:21] = 0x%x)\n", phy_query_bb_reg(priv, 0xc1c, MASKDWORD), ele_D);
+	for (i = 0; i < OFDM_TABLE_SIZE_8812; i++) {/* 4 */
+		if (ele_D == ofdm_swing_table_8812[i]) {
+			OFDM_index[0] = (unsigned char)i;
+			RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "OFDM_index[0]=%d\n", OFDM_index[0]);
+			break;
+		}
+	}
+	/* Query OFDM path B default setting */
+	if (rf == 2) {
+		ele_D = phy_query_bb_reg(priv, 0xe1c, 0xffe00000);
+		RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "0xe1c:0x%x ([32:21] = 0x%x)\n", phy_query_bb_reg(priv, 0xe1c, MASKDWORD), ele_D);
+		for (i = 0; i < OFDM_TABLE_SIZE_8812; i++) {
+			if (ele_D == ofdm_swing_table_8812[i]) {
+				OFDM_index[1] = (unsigned char)i;
+				RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "OFDM_index[1]=%d\n", OFDM_index[1]);
+				break;
+			}
+		}
+	}
+#endif
+	/* Initialize */
+	if (!priv->pshare->thermal_value) {
+		priv->pshare->thermal_value = priv->pmib->dot11RFEntry.ther;
+		priv->pshare->thermal_value_lck = thermal_value;
+	}
+
+	/* calculate average thermal meter */
+	{
+		priv->pshare->thermal_value_avg_8812[priv->pshare->thermal_value_avg_index_8812] = thermal_value;
+		priv->pshare->thermal_value_avg_index_8812++;
+		if (priv->pshare->thermal_value_avg_index_8812 == AVG_THERMAL_NUM_8812)
+			priv->pshare->thermal_value_avg_index_8812 = 0;
+
+		for (i = 0; i < AVG_THERMAL_NUM_8812; i++) {
+			if (priv->pshare->thermal_value_avg_8812[i]) {
+				thermal_value_avg += priv->pshare->thermal_value_avg_8812[i];
+				thermal_value_avg_count++;
+			}
+		}
+
+		if (thermal_value_avg_count) {
+			thermal_value = (unsigned char)(thermal_value_avg / thermal_value_avg_count);
+			/* printk("AVG Thermal Meter = 0x%x\n", thermal_value); */
+		}
+	}
+
+
+	/* 4 If necessary,  do power tracking */
+
+	if (!priv->pmib->dot11RFEntry.ther) /*Don't do power tracking since no calibrated thermal value*/
+		return;
+
+	if (thermal_value != priv->pshare->thermal_value) {
+		RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "\n******** START POWER TRACKING ********\n");
+		RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "\nReadback Thermal Meter = 0x%x pre thermal meter 0x%x EEPROMthermalmeter 0x%x\n", thermal_value, priv->pshare->thermal_value, priv->pmib->dot11RFEntry.ther);
+		delta = RTL_ABS(thermal_value, priv->pmib->dot11RFEntry.ther);
+		delta_LCK = RTL_ABS(thermal_value, priv->pshare->thermal_value_lck);
+		is_decrease = ((thermal_value < priv->pmib->dot11RFEntry.ther) ? 1 : 0);
+		/* if (*dm->band_type == ODM_BAND_5G) */
+		{
+#ifdef _TRACKING_TABLE_FILE
+			if (priv->pshare->rf_ft_var.pwr_track_file) {
+				for (rf_path = 0; rf_path < max_rf_path; rf_path++) {
+					RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "diff: (%s)%d ==> get index from table : %d)\n", (is_decrease ? "-" : "+"), delta, get_tx_tracking_index(priv, channel, rf_path, delta, is_decrease, 0));
+					if (is_decrease) {
+						OFDM_index[rf_path] = priv->pshare->OFDM_index0[rf_path] + get_tx_tracking_index(priv, channel, rf_path, delta, is_decrease, 0);
+						OFDM_index[rf_path] = ((OFDM_index[rf_path] > (OFDM_TABLE_SIZE_8812 - 1)) ? (OFDM_TABLE_SIZE_8812 - 1) : OFDM_index[rf_path]);
+						RF_DBG(dm, DBG_RF_TX_PWR_TRACK, ">>> decrese power ---> new OFDM_INDEX:%d (%d + %d)\n", OFDM_index[rf_path], priv->pshare->OFDM_index0[rf_path], get_tx_tracking_index(priv, channel, rf_path, delta, is_decrease, 0));
+#if 0/* RTL8881A_SUPPORT */
+						if (dm->support_ic_type == ODM_RTL8881A) {
+							if (priv->pshare->rf_ft_var.pwrtrk_tx_agc_enable) {
+								if (priv->pshare->add_tx_agc) { /* tx_agc has been added */
+									add_tx_power88xx_ac(priv, 0);
+									priv->pshare->add_tx_agc = 0;
+									priv->pshare->add_tx_agc_index = 0;
+								}
+							}
+						}
+#endif
+					} else {
+
+						OFDM_index[rf_path] = priv->pshare->OFDM_index0[rf_path] - get_tx_tracking_index(priv, channel, rf_path, delta, is_decrease, 0);
+#if 0/* RTL8881A_SUPPORT */
+						if (dm->support_ic_type == ODM_RTL8881A) {
+							if (priv->pshare->rf_ft_var.pwrtrk_tx_agc_enable) {
+								if (OFDM_index[i] < OFDM_min_index) {
+									priv->pshare->add_tx_agc_index = (OFDM_min_index - OFDM_index[i]) / 2; /* Calculate Remnant tx_agc value,  2 index for 1 tx_agc */
+									add_tx_power88xx_ac(priv, priv->pshare->add_tx_agc_index);
+									priv->pshare->add_tx_agc = 1;     /* add_tx_agc Flag = 1 */
+									OFDM_index[i] = OFDM_min_index;
+								} else {
+									if (priv->pshare->add_tx_agc) { /* tx_agc been added */
+										priv->pshare->add_tx_agc = 0;
+										priv->pshare->add_tx_agc_index = 0;
+										add_tx_power88xx_ac(priv, 0); /* minus the added TPI */
+									}
+								}
+							}
+						}
+#else
+						OFDM_index[rf_path] = ((OFDM_index[rf_path] < OFDM_min_index) ?  OFDM_min_index : OFDM_index[rf_path]);
+#endif
+						RF_DBG(dm, DBG_RF_TX_PWR_TRACK, ">>> increse power ---> new OFDM_INDEX:%d (%d - %d)\n", OFDM_index[rf_path], priv->pshare->OFDM_index0[rf_path], get_tx_tracking_index(priv, channel, rf_path, delta, is_decrease, 0));
+					}
+				}
+			}
+#endif
+			/* 4 Set new BB swing index */
+			for (rf_path = 0; rf_path < max_rf_path; rf_path++) {
+				phy_set_bb_reg(priv, bb_swing_reg[rf_path], 0xffe00000, ofdm_swing_table_8812[(unsigned int)OFDM_index[rf_path]]);
+				RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "Readback 0x%x[31:21] = 0x%x, OFDM_index:%d\n", bb_swing_reg[rf_path], phy_query_bb_reg(priv, bb_swing_reg[rf_path], 0xffe00000), OFDM_index[rf_path]);
+			}
+
+		}
+		if ((delta_LCK > 8) && (!iqk_info->rfk_forbidden)) {
+			RTL_W8(0x522, 0xff);
+			reg0x18 = phy_query_rf_reg(priv, RF_PATH_A, 0x18, MASK20BITS, 1);
+			phy_set_rf_reg(priv, RF_PATH_A, 0xB4, BIT(14), 1);
+			phy_set_rf_reg(priv, RF_PATH_A, 0x18, BIT(15), 1);
+			delay_ms(200); /* frequency deviation */
+			phy_set_rf_reg(priv, RF_PATH_A, 0xB4, BIT(14), 0);
+			phy_set_rf_reg(priv, RF_PATH_A, 0x18, MASK20BITS, reg0x18);
+#ifdef CONFIG_RTL_8812_SUPPORT
+			if (GET_CHIP_VER(priv) == VERSION_8812E)
+				update_bbrf_val8812(priv, priv->pmib->dot11RFEntry.dot11channel);
+#endif
+			RTL_W8(0x522, 0x0);
+			priv->pshare->thermal_value_lck = thermal_value;
+		}
+		RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "\n******** END:%s() ********\n", __FUNCTION__);
+
+		/* update thermal meter value */
+		priv->pshare->thermal_value = thermal_value;
+		for (rf_path = 0; rf_path < max_rf_path; rf_path++)
+			priv->pshare->OFDM_index[rf_path] = OFDM_index[rf_path];
+	}
+}
+
+#endif
+
+
+void
+odm_txpowertracking_callback_thermal_meter(
+	void		*dm_void
+)
+{
+	struct dm_struct		*dm = (struct dm_struct *)dm_void;
+	struct dm_rf_calibration_struct	*cali_info = &(dm->rf_calibrate_info);
+	struct dm_iqk_info	*iqk_info = &dm->IQK_info;
+
+#if (RTL8197F_SUPPORT == 1 ||RTL8192F_SUPPORT == 1 || RTL8822B_SUPPORT == 1 || RTL8821C_SUPPORT == 1 || RTL8198F_SUPPORT == 1)
+	if (dm->support_ic_type == ODM_RTL8197F || dm->support_ic_type == ODM_RTL8192F || dm->support_ic_type == ODM_RTL8822B
+		|| dm->support_ic_type == ODM_RTL8821C || dm->support_ic_type == ODM_RTL8198F) {
+		odm_txpowertracking_callback_thermal_meter_jaguar_series3(dm);
+		return;
+	}
+#endif
+#if (RTL8814A_SUPPORT == 1)		/*use this function to do power tracking after 8814 by YuChen*/
+	if (dm->support_ic_type & ODM_RTL8814A) {
+		odm_txpowertracking_callback_thermal_meter_jaguar_series2(dm);
+		return;
+	}
+#endif
+#if (RTL8881A_SUPPORT || RTL8812A_SUPPORT == 1)
+	if (dm->support_ic_type & ODM_RTL8812 || dm->support_ic_type & ODM_RTL8881A) {
+		odm_txpowertracking_callback_thermal_meter_jaguar_series(dm);
+		return;
+	}
+#endif
+
+#if (RTL8192E_SUPPORT == 1)
+	if (dm->support_ic_type == ODM_RTL8192E) {
+		odm_txpowertracking_callback_thermal_meter_92e(dm);
+		return;
+	}
+#endif
+
+#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
+	HAL_DATA_TYPE	*hal_data = GET_HAL_DATA(((PADAPTER)adapter));
+	/* PMGNT_INFO      		mgnt_info = &adapter->mgnt_info; */
+#endif
+
+
+	u8			thermal_value = 0, delta, delta_LCK, delta_IQK, offset;
+	u8			thermal_value_avg_count = 0;
+	u32			thermal_value_avg = 0;
+	/*	s32			ele_A=0, ele_D, TempCCk, X, value32;
+	 *	s32			Y, ele_C=0;
+	 *	s8			OFDM_index[2], CCK_index=0, OFDM_index_old[2]={0,0}, CCK_index_old=0, index;
+	 *	s8			deltaPowerIndex = 0; */
+	u32			i = 0;/* , j = 0; */
+	boolean		is2T = false;
+	/*	bool 		bInteralPA = false; */
+
+	u8			OFDM_max_index = 34, rf = (is2T) ? 2 : 1; /* OFDM BB Swing should be less than +3.0dB, which is required by Arthur */
+	u8			indexforchannel = 0;/*get_right_chnl_place_for_iqk(hal_data->current_channel)*/
+	enum            _POWER_DEC_INC { POWER_DEC, POWER_INC };
+
+	struct txpwrtrack_cfg	c;
+
+
+	/* 4 1. The following TWO tables decide the final index of OFDM/CCK swing table. */
+	s8			delta_swing_table_idx[2][index_mapping_NUM_88E] = {
+		/* {{Power decreasing(lower temperature)}, {Power increasing(higher temperature)}} */
+		{0, 0, 2, 3, 4, 4, 5, 6, 7, 7, 8, 9, 10, 10, 11}, {0, 0, 1, 2, 3, 4, 4, 4, 4, 5, 7, 8, 9, 9, 10}
+	};
+	u8			thermal_threshold[2][index_mapping_NUM_88E] = {
+		/* {{Power decreasing(lower temperature)}, {Power increasing(higher temperature)}} */
+		{0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 27}, {0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 25, 25, 25}
+	};
+
+#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
+	struct rtl8192cd_priv	*priv = dm->priv;
+#endif
+
+	/* 4 2. Initilization ( 7 steps in total ) */
+
+	configure_txpower_track(dm, &c);
+
+	dm->rf_calibrate_info.txpowertracking_callback_cnt++; /* cosa add for debug */
+	dm->rf_calibrate_info.is_txpowertracking_init = true;
+
+#if (MP_DRIVER == 1)
+	dm->rf_calibrate_info.txpowertrack_control = hal_data->txpowertrack_control; /* <Kordan> We should keep updating the control variable according to HalData.
+     * <Kordan> rf_calibrate_info.rega24 will be initialized when ODM HW configuring, but MP configures with para files. */
+	dm->rf_calibrate_info.rega24 = 0x090e1317;
+#endif
+
+#if (DM_ODM_SUPPORT_TYPE == ODM_AP) && defined(MP_TEST)
+	if ((OPMODE & WIFI_MP_STATE) || *(dm->mp_mode)) {
+		if (dm->priv->pshare->mp_txpwr_tracking == false)
+			return;
+	}
+#endif
+	RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "===>odm_txpowertracking_callback_thermal_meter_8188e, dm->bb_swing_idx_cck_base: %d, dm->bb_swing_idx_ofdm_base: %d\n", cali_info->bb_swing_idx_cck_base, cali_info->bb_swing_idx_ofdm_base);
+	/*
+		if (!dm->rf_calibrate_info.tm_trigger) {
+			odm_set_rf_reg(dm, RF_PATH_A, c.thermal_reg_addr, BIT(17) | BIT(16), 0x3);
+			dm->rf_calibrate_info.tm_trigger = 1;
+			return;
+		}
+	*/
+	thermal_value = (u8)odm_get_rf_reg(dm, RF_PATH_A, c.thermal_reg_addr, 0xfc00);	/* 0x42: RF Reg[15:10] 88E */
+#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
+	if (!thermal_value || !dm->rf_calibrate_info.txpowertrack_control)
+#else
+	if (!dm->rf_calibrate_info.txpowertrack_control)
+#endif
+		return;
+
+	/* 4 3. Initialize ThermalValues of rf_calibrate_info */
+
+	if (!dm->rf_calibrate_info.thermal_value) {
+		dm->rf_calibrate_info.thermal_value_lck = thermal_value;
+		dm->rf_calibrate_info.thermal_value_iqk = thermal_value;
+	}
+
+	if (dm->rf_calibrate_info.is_reloadtxpowerindex)
+		RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "reload ofdm index for band switch\n");
+
+	/* 4 4. Calculate average thermal meter */
+
+	dm->rf_calibrate_info.thermal_value_avg[dm->rf_calibrate_info.thermal_value_avg_index] = thermal_value;
+	dm->rf_calibrate_info.thermal_value_avg_index++;
+	if (dm->rf_calibrate_info.thermal_value_avg_index == c.average_thermal_num)
+		dm->rf_calibrate_info.thermal_value_avg_index = 0;
+
+	for (i = 0; i < c.average_thermal_num; i++) {
+		if (dm->rf_calibrate_info.thermal_value_avg[i]) {
+			thermal_value_avg += dm->rf_calibrate_info.thermal_value_avg[i];
+			thermal_value_avg_count++;
+		}
+	}
+
+	if (thermal_value_avg_count) {
+		/* Give the new thermo value a weighting */
+		thermal_value_avg += (thermal_value * 4);
+
+		thermal_value = (u8)(thermal_value_avg / (thermal_value_avg_count + 4));
+		cali_info->thermal_value_delta = thermal_value - priv->pmib->dot11RFEntry.ther;
+		RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "AVG Thermal Meter = 0x%x\n", thermal_value);
+	}
+
+	/* 4 5. Calculate delta, delta_LCK, delta_IQK. */
+
+	delta	  = (thermal_value > dm->rf_calibrate_info.thermal_value) ? (thermal_value - dm->rf_calibrate_info.thermal_value) : (dm->rf_calibrate_info.thermal_value - thermal_value);
+	delta_LCK = (thermal_value > dm->rf_calibrate_info.thermal_value_lck) ? (thermal_value - dm->rf_calibrate_info.thermal_value_lck) : (dm->rf_calibrate_info.thermal_value_lck - thermal_value);
+	delta_IQK = (thermal_value > dm->rf_calibrate_info.thermal_value_iqk) ? (thermal_value - dm->rf_calibrate_info.thermal_value_iqk) : (dm->rf_calibrate_info.thermal_value_iqk - thermal_value);
+
+	/* 4 6. If necessary, do LCK. */
+	if (!(dm->support_ic_type & ODM_RTL8821)) {
+		/*if((delta_LCK > hal_data->delta_lck) && (hal_data->delta_lck != 0))*/
+		if ((delta_LCK >= c.threshold_iqk) && (!iqk_info->rfk_forbidden)) {
+			/*Delta temperature is equal to or larger than 20 centigrade.*/
+			dm->rf_calibrate_info.thermal_value_lck = thermal_value;
+			(*c.phy_lc_calibrate)(dm);
+		}
+	}
+
+	/* 3 7. If necessary, move the index of swing table to adjust Tx power. */
+
+	if (delta > 0 && dm->rf_calibrate_info.txpowertrack_control) {
+
+		delta = (thermal_value > dm->priv->pmib->dot11RFEntry.ther) ? (thermal_value - dm->priv->pmib->dot11RFEntry.ther) : (dm->priv->pmib->dot11RFEntry.ther - thermal_value);
+
+		/* 4 7.1 The Final Power index = BaseIndex + power_index_offset */
+
+		if (thermal_value > dm->priv->pmib->dot11RFEntry.ther) {
+			CALCULATE_SWINGTALBE_OFFSET(offset, POWER_INC, index_mapping_NUM_88E, delta);
+			dm->rf_calibrate_info.delta_power_index_last = dm->rf_calibrate_info.delta_power_index;
+			dm->rf_calibrate_info.delta_power_index =  delta_swing_table_idx[POWER_INC][offset];
+
+		} else {
+
+			CALCULATE_SWINGTALBE_OFFSET(offset, POWER_DEC, index_mapping_NUM_88E, delta);
+			dm->rf_calibrate_info.delta_power_index_last = dm->rf_calibrate_info.delta_power_index;
+			dm->rf_calibrate_info.delta_power_index = (-1) * delta_swing_table_idx[POWER_DEC][offset];
+		}
+
+		if (dm->rf_calibrate_info.delta_power_index == dm->rf_calibrate_info.delta_power_index_last)
+			dm->rf_calibrate_info.power_index_offset = 0;
+		else
+			dm->rf_calibrate_info.power_index_offset = dm->rf_calibrate_info.delta_power_index - dm->rf_calibrate_info.delta_power_index_last;
+
+		for (i = 0; i < rf; i++)
+			dm->rf_calibrate_info.OFDM_index[i] = cali_info->bb_swing_idx_ofdm_base + dm->rf_calibrate_info.power_index_offset;
+		dm->rf_calibrate_info.CCK_index = cali_info->bb_swing_idx_cck_base + dm->rf_calibrate_info.power_index_offset;
+
+		cali_info->bb_swing_idx_cck = dm->rf_calibrate_info.CCK_index;
+		cali_info->bb_swing_idx_ofdm[RF_PATH_A] = dm->rf_calibrate_info.OFDM_index[RF_PATH_A];
+
+		RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "The 'CCK' final index(%d) = BaseIndex(%d) + power_index_offset(%d)\n", cali_info->bb_swing_idx_cck, cali_info->bb_swing_idx_cck_base, dm->rf_calibrate_info.power_index_offset);
+		RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "The 'OFDM' final index(%d) = BaseIndex(%d) + power_index_offset(%d)\n", cali_info->bb_swing_idx_ofdm[RF_PATH_A], cali_info->bb_swing_idx_ofdm_base, dm->rf_calibrate_info.power_index_offset);
+
+		/* 4 7.1 Handle boundary conditions of index. */
+
+
+		for (i = 0; i < rf; i++) {
+			if (dm->rf_calibrate_info.OFDM_index[i] > OFDM_max_index)
+				dm->rf_calibrate_info.OFDM_index[i] = OFDM_max_index;
+			else if (dm->rf_calibrate_info.OFDM_index[i] < 0)
+				dm->rf_calibrate_info.OFDM_index[i] = 0;
+		}
+
+		if (dm->rf_calibrate_info.CCK_index > c.swing_table_size_cck - 1)
+			dm->rf_calibrate_info.CCK_index = c.swing_table_size_cck - 1;
+		else if (dm->rf_calibrate_info.CCK_index < 0)
+			dm->rf_calibrate_info.CCK_index = 0;
+	} else {
+		RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"The thermal meter is unchanged or TxPowerTracking OFF: thermal_value: %d, dm->rf_calibrate_info.thermal_value: %d)\n", thermal_value, dm->rf_calibrate_info.thermal_value);
+		dm->rf_calibrate_info.power_index_offset = 0;
+	}
+	RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"TxPowerTracking: [CCK] Swing Current index: %d, Swing base index: %d\n", dm->rf_calibrate_info.CCK_index, cali_info->bb_swing_idx_cck_base);
+
+	RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"TxPowerTracking: [OFDM] Swing Current index: %d, Swing base index: %d\n", dm->rf_calibrate_info.OFDM_index[RF_PATH_A], cali_info->bb_swing_idx_ofdm_base);
+
+	if (dm->rf_calibrate_info.power_index_offset != 0 && dm->rf_calibrate_info.txpowertrack_control) {
+		/* 4 7.2 Configure the Swing Table to adjust Tx Power. */
+
+		dm->rf_calibrate_info.is_tx_power_changed = true; /* Always true after Tx Power is adjusted by power tracking. */
+		/*  */
+		/* 2012/04/23 MH According to Luke's suggestion, we can not write BB digital */
+		/* to increase TX power. Otherwise, EVM will be bad. */
+		/*  */
+		/* 2012/04/25 MH Add for tx power tracking to set tx power in tx agc for 88E. */
+		if (thermal_value > dm->rf_calibrate_info.thermal_value) {
+			/* RF_DBG(dm,DBG_RF_TX_PWR_TRACK, */
+			/*	"Temperature Increasing: delta_pi: %d, delta_t: %d, Now_t: %d, EFUSE_t: %d, Last_t: %d\n", */
+			/*	dm->rf_calibrate_info.power_index_offset, delta, thermal_value, hal_data->eeprom_thermal_meter, dm->rf_calibrate_info.thermal_value); */
+		} else if (thermal_value < dm->rf_calibrate_info.thermal_value) { /* Low temperature */
+			/* RF_DBG(dm,DBG_RF_TX_PWR_TRACK, */
+			/*	"Temperature Decreasing: delta_pi: %d, delta_t: %d, Now_t: %d, EFUSE_t: %d, Last_t: %d\n", */
+			/*		dm->rf_calibrate_info.power_index_offset, delta, thermal_value, hal_data->eeprom_thermal_meter, dm->rf_calibrate_info.thermal_value); */
+		}
+		if (thermal_value > dm->priv->pmib->dot11RFEntry.ther)
+		{
+			/*				RF_DBG(dm,DBG_RF_TX_PWR_TRACK,"Temperature(%d) hugher than PG value(%d), increases the power by tx_agc\n", thermal_value, hal_data->eeprom_thermal_meter); */
+			(*c.odm_tx_pwr_track_set_pwr)(dm, TXAGC, 0, 0);
+		} else {
+			/*			RF_DBG(dm,DBG_RF_TX_PWR_TRACK,"Temperature(%d) lower than PG value(%d), increases the power by tx_agc\n", thermal_value, hal_data->eeprom_thermal_meter); */
+			(*c.odm_tx_pwr_track_set_pwr)(dm, BBSWING, RF_PATH_A, indexforchannel);
+			if (is2T)
+				(*c.odm_tx_pwr_track_set_pwr)(dm, BBSWING, RF_PATH_B, indexforchannel);
+		}
+
+		cali_info->bb_swing_idx_cck_base = cali_info->bb_swing_idx_cck;
+		cali_info->bb_swing_idx_ofdm_base = cali_info->bb_swing_idx_ofdm[RF_PATH_A];
+		dm->rf_calibrate_info.thermal_value = thermal_value;
+
+	}
+
+	RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "<===dm_TXPowerTrackingCallback_ThermalMeter_8188E\n");
+
+	dm->rf_calibrate_info.tx_powercount = 0;
+}
+
+/* 3============================================================
+ * 3 IQ Calibration
+ * 3============================================================ */
+
+void
+odm_reset_iqk_result(
+	void		*dm_void
+)
+{
+	return;
+}
+#if 1/* !(DM_ODM_SUPPORT_TYPE & ODM_AP) */
+u8 odm_get_right_chnl_place_for_iqk(u8 chnl)
+{
+	u8	channel_all[ODM_TARGET_CHNL_NUM_2G_5G] = {
+		1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 36, 38, 40, 42, 44, 46, 48, 50, 52, 54, 56, 58, 60, 62, 64, 100, 102, 104, 106, 108, 110, 112, 114, 116, 118, 120, 122, 124, 126, 128, 130, 132, 134, 136, 138, 140, 149, 151, 153, 155, 157, 159, 161, 163, 165
+	};
+	u8	place = chnl;
+
+
+	if (chnl > 14) {
+		for (place = 14; place < sizeof(channel_all); place++) {
+			if (channel_all[place] == chnl)
+				return place - 13;
+		}
+	}
+	return 0;
+
+}
+#endif
+
+void
+odm_iq_calibrate(
+	struct dm_struct	*dm
+)
+{
+	struct dm_iqk_info	*iqk_info = &dm->IQK_info;
+
+	if ((dm->is_linked) && (!iqk_info->rfk_forbidden)) {
+		if ((*dm->channel != dm->pre_channel) && (!*dm->is_scan_in_process)) {
+			dm->pre_channel = *dm->channel;
+			dm->linked_interval = 0;
+		}
+
+		if (dm->linked_interval < 3)
+			dm->linked_interval++;
+
+		if (dm->linked_interval == 2)
+			halrf_iqk_trigger(dm, false);
+	} else
+		dm->linked_interval = 0;
+
+}
+
+void phydm_rf_init(void		*dm_void)
+{
+	struct dm_struct		*dm = (struct dm_struct *)dm_void;
+	odm_txpowertracking_init(dm);
+
+#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
+#if (RTL8814A_SUPPORT == 1)
+	if (dm->support_ic_type & ODM_RTL8814A)
+		phy_iq_calibrate_8814a_init(dm);
+#endif
+#endif
+
+}
+
+void phydm_rf_watchdog(void		*dm_void)
+{
+	struct dm_struct		*dm = (struct dm_struct *)dm_void;
+#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
+	odm_txpowertracking_check(dm);
+	if (dm->support_ic_type & ODM_IC_11AC_SERIES)
+		odm_iq_calibrate(dm);
+#endif
+}
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/halrf/halphyrf_ap.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/halrf/halphyrf_ap.h
--- linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/halrf/halphyrf_ap.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/halrf/halphyrf_ap.h	2020-04-10 16:35:06.818660161 +0300
@@ -0,0 +1,134 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+
+#ifndef __HALPHYRF_H__
+#define __HALPHYRF_H__
+
+#include "halrf/halrf_powertracking_ap.h"
+#include "halrf/halrf_kfree.h"
+
+#if (RTL8814A_SUPPORT == 1)
+	#include "halrf/rtl8814a/halrf_iqk_8814a.h"
+#endif
+
+#if (RTL8822B_SUPPORT == 1)
+	#include "halrf/rtl8822b/halrf_iqk_8822b.h"
+#endif
+
+#if (RTL8821C_SUPPORT == 1)
+	#include "halrf/rtl8821c/halrf_iqk_8821c.h"
+#endif
+
+#if (RTL8195B_SUPPORT == 1)
+//	#include "halrf/rtl8195b/halrf.h"
+	#include "halrf/rtl8195b/halrf_iqk_8195b.h"
+	#include "halrf/rtl8195b/halrf_txgapk_8195b.h"
+	#include "halrf/rtl8195b/halrf_dpk_8195b.h"
+#endif
+#if (RTL8198F_SUPPORT == 1)
+	#include "halrf/rtl8198f/halrf_iqk_8198f.h"
+	#include "halrf/rtl8198f/halrf_dpk_8198f.h"
+#endif
+
+enum pwrtrack_method {
+	BBSWING,
+	TXAGC,
+	MIX_MODE,
+	TSSI_MODE
+};
+
+typedef void	(*func_set_pwr)(void *, enum pwrtrack_method, u8, u8);
+typedef void(*func_iqk)(void *, u8, u8, u8);
+typedef void	(*func_lck)(void *);
+/* refine by YuChen for 8814A */
+typedef void	(*func_swing)(void *, u8 **, u8 **, u8 **, u8 **);
+typedef void	(*func_swing8814only)(void *, u8 **, u8 **, u8 **, u8 **);
+typedef void	(*func_all_swing)(void *, u8 **, u8 **, u8 **, u8 **, u8 **, u8 **, u8 **, u8 **);
+typedef void	(*func_all_swing_ex)(void *, u8 **, u8 **, u8 **, u8 **, u8 **, u8 **, u8 **, u8 **);
+
+struct txpwrtrack_cfg {
+	u8		swing_table_size_cck;
+	u8		swing_table_size_ofdm;
+	u8		threshold_iqk;
+	u8		threshold_dpk;
+	u8		average_thermal_num;
+	u8		rf_path_count;
+	u32		thermal_reg_addr;
+	func_set_pwr	odm_tx_pwr_track_set_pwr;
+	func_iqk	do_iqk;
+	func_lck		phy_lc_calibrate;
+	func_swing	get_delta_swing_table;
+	func_swing8814only	get_delta_swing_table8814only;
+	func_all_swing		get_delta_all_swing_table;
+	func_all_swing_ex	get_delta_all_swing_table_ex;
+};
+
+void
+configure_txpower_track(
+	void		*dm_void,
+	struct txpwrtrack_cfg	*config
+);
+
+
+void
+odm_txpowertracking_callback_thermal_meter(
+	void		*dm_void
+);
+
+#if (RTL8192E_SUPPORT == 1)
+void
+odm_txpowertracking_callback_thermal_meter_92e(
+	void		*dm_void
+);
+#endif
+
+#if (RTL8814A_SUPPORT == 1)
+void
+odm_txpowertracking_callback_thermal_meter_jaguar_series2(
+	void		*dm_void
+);
+
+#elif ODM_IC_11AC_SERIES_SUPPORT
+void
+odm_txpowertracking_callback_thermal_meter_jaguar_series(
+	void		*dm_void
+);
+
+#elif (RTL8197F_SUPPORT == 1 || RTL8822B_SUPPORT == 1)
+void
+odm_txpowertracking_callback_thermal_meter_jaguar_series3(
+	void		*dm_void
+);
+
+#endif
+
+#define IS_CCK_RATE(_rate)				(ODM_MGN_1M == _rate || _rate == ODM_MGN_2M || _rate == ODM_MGN_5_5M || _rate == ODM_MGN_11M)
+
+#define ODM_TARGET_CHNL_NUM_2G_5G	59
+
+
+void
+odm_reset_iqk_result(
+	void		*dm_void
+);
+u8
+odm_get_right_chnl_place_for_iqk(
+	u8 chnl
+);
+
+void phydm_rf_init(void		*dm_void);
+void phydm_rf_watchdog(void		*dm_void);
+
+#endif	/*#ifndef __HALPHYRF_H__*/
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/halrf/halphyrf_ce.c linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/halrf/halphyrf_ce.c
--- linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/halrf/halphyrf_ce.c	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/halrf/halphyrf_ce.c	2020-04-10 16:35:06.819660208 +0300
@@ -0,0 +1,918 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017  Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * The full GNU General Public License is included in this distribution in the
+ * file called LICENSE.
+ *
+ * Contact Information:
+ * wlanfae <wlanfae@realtek.com>
+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
+ * Hsinchu 300, Taiwan.
+ *
+ * Larry Finger <Larry.Finger@lwfinger.net>
+ *
+ *****************************************************************************/
+
+#include "mp_precomp.h"
+#include "phydm_precomp.h"
+
+#define CALCULATE_SWINGTALBE_OFFSET(_offset, _direction, _size, _delta_thermal)\
+	do {                                                                   \
+		u32 __offset = (u32)_offset;                                   \
+		u32 __size = (u32)_size;                                       \
+		for (__offset = 0; __offset < __size; __offset++) {            \
+			if (_delta_thermal <                                   \
+				thermal_threshold[_direction][__offset]) {     \
+				if (__offset != 0)                             \
+					__offset--;                            \
+				break;                                         \
+			}                                                      \
+		}                                                              \
+		if (__offset >= __size)                                        \
+			__offset = __size - 1;                                 \
+	} while (0)
+
+void configure_txpower_track(void *dm_void, struct txpwrtrack_cfg *config)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+
+#if RTL8192E_SUPPORT
+	if (dm->support_ic_type == ODM_RTL8192E)
+		configure_txpower_track_8192e(config);
+#endif
+#if RTL8821A_SUPPORT
+	if (dm->support_ic_type == ODM_RTL8821)
+		configure_txpower_track_8821a(config);
+#endif
+#if RTL8812A_SUPPORT
+	if (dm->support_ic_type == ODM_RTL8812)
+		configure_txpower_track_8812a(config);
+#endif
+#if RTL8188E_SUPPORT
+	if (dm->support_ic_type == ODM_RTL8188E)
+		configure_txpower_track_8188e(config);
+#endif
+
+#if RTL8723B_SUPPORT
+	if (dm->support_ic_type == ODM_RTL8723B)
+		configure_txpower_track_8723b(config);
+#endif
+
+#if RTL8814A_SUPPORT
+	if (dm->support_ic_type == ODM_RTL8814A)
+		configure_txpower_track_8814a(config);
+#endif
+
+#if RTL8703B_SUPPORT
+	if (dm->support_ic_type == ODM_RTL8703B)
+		configure_txpower_track_8703b(config);
+#endif
+
+#if RTL8188F_SUPPORT
+	if (dm->support_ic_type == ODM_RTL8188F)
+		configure_txpower_track_8188f(config);
+#endif
+#if RTL8723D_SUPPORT
+	if (dm->support_ic_type == ODM_RTL8723D)
+		configure_txpower_track_8723d(config);
+#endif
+/* JJ ADD 20161014 */
+#if RTL8710B_SUPPORT
+	if (dm->support_ic_type == ODM_RTL8710B)
+		configure_txpower_track_8710b(config);
+#endif
+#if RTL8822B_SUPPORT
+	if (dm->support_ic_type == ODM_RTL8822B)
+		configure_txpower_track_8822b(config);
+#endif
+#if RTL8821C_SUPPORT
+	if (dm->support_ic_type == ODM_RTL8821C)
+		configure_txpower_track_8821c(config);
+#endif
+
+#if RTL8192F_SUPPORT
+	if (dm->support_ic_type == ODM_RTL8192F)
+		configure_txpower_track_8192f(config);
+#endif
+}
+
+/* **********************************************************************
+ * <20121113, Kordan> This function should be called when tx_agc changed.
+ * Otherwise the previous compensation is gone, because we record the
+ * delta of temperature between two TxPowerTracking watch dogs.
+ *
+ * NOTE: If Tx BB swing or Tx scaling is varified during run-time, still
+ * need to call this function.
+ * **********************************************************************
+ */
+void odm_clear_txpowertracking_state(void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct _hal_rf_ *rf = &dm->rf_table;
+	u8 p = 0;
+	struct dm_rf_calibration_struct *cali_info = &dm->rf_calibrate_info;
+
+	cali_info->bb_swing_idx_cck_base = cali_info->default_cck_index;
+	cali_info->bb_swing_idx_cck = cali_info->default_cck_index;
+	dm->rf_calibrate_info.CCK_index = 0;
+
+	for (p = RF_PATH_A; p < MAX_RF_PATH; ++p) {
+		cali_info->bb_swing_idx_ofdm_base[p]
+						= cali_info->default_ofdm_index;
+		cali_info->bb_swing_idx_ofdm[p] = cali_info->default_ofdm_index;
+		cali_info->OFDM_index[p] = cali_info->default_ofdm_index;
+
+		cali_info->power_index_offset[p] = 0;
+		cali_info->delta_power_index[p] = 0;
+		cali_info->delta_power_index_last[p] = 0;
+
+		/* Initial Mix mode power tracking*/
+		cali_info->absolute_ofdm_swing_idx[p] = 0;
+		cali_info->remnant_ofdm_swing_idx[p] = 0;
+		cali_info->kfree_offset[p] = 0;
+	}
+	/* Initial Mix mode power tracking*/
+	cali_info->modify_tx_agc_flag_path_a = false;
+	cali_info->modify_tx_agc_flag_path_b = false;
+	cali_info->modify_tx_agc_flag_path_c = false;
+	cali_info->modify_tx_agc_flag_path_d = false;
+	cali_info->remnant_cck_swing_idx = 0;
+	cali_info->thermal_value = rf->eeprom_thermal;
+	cali_info->modify_tx_agc_value_cck = 0;
+	cali_info->modify_tx_agc_value_ofdm = 0;
+}
+
+void odm_get_tracking_table(void *dm_void, u8 thermal_value, u8 delta)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct dm_rf_calibration_struct *cali_info = &dm->rf_calibrate_info;
+	struct _hal_rf_ *rf = &dm->rf_table;
+	struct txpwrtrack_cfg c = {0};
+
+	u8 p;
+	/* 4 1. TWO tables decide the final index of OFDM/CCK swing table. */
+	u8 *pwrtrk_tab_up_a = NULL;
+	u8 *pwrtrk_tab_down_a = NULL;
+	u8 *pwrtrk_tab_up_b = NULL;
+	u8 *pwrtrk_tab_down_b = NULL;
+	/*for 8814 add by Yu Chen*/
+	u8 *pwrtrk_tab_up_c = NULL;
+	u8 *pwrtrk_tab_down_c = NULL;
+	u8 *pwrtrk_tab_up_d = NULL;
+	u8 *pwrtrk_tab_down_d = NULL;
+	/*for Xtal Offset by James.Tung*/
+	s8 *xtal_tab_up = NULL;
+	s8 *xtal_tab_down = NULL;
+
+	configure_txpower_track(dm, &c);
+
+	(*c.get_delta_swing_table)(dm,
+				   (u8 **)&pwrtrk_tab_up_a,
+				   (u8 **)&pwrtrk_tab_down_a,
+				   (u8 **)&pwrtrk_tab_up_b,
+				   (u8 **)&pwrtrk_tab_down_b);
+
+	if (dm->support_ic_type & ODM_RTL8814A) /*for 8814 path C & D*/
+		(*c.get_delta_swing_table8814only)(dm,
+						   (u8 **)&pwrtrk_tab_up_c,
+						   (u8 **)&pwrtrk_tab_down_c,
+						   (u8 **)&pwrtrk_tab_up_d,
+						   (u8 **)&pwrtrk_tab_down_d);
+	/*for Xtal Offset*/
+	if (dm->support_ic_type &
+	    (ODM_RTL8703B | ODM_RTL8723D | ODM_RTL8710B | ODM_RTL8192F))
+		(*c.get_delta_swing_xtal_table)(dm,
+						(s8 **)&xtal_tab_up,
+						(s8 **)&xtal_tab_down);
+
+	if (thermal_value > rf->eeprom_thermal) {
+		for (p = RF_PATH_A; p < c.rf_path_count; p++) {
+			/*recording power index offset*/
+			cali_info->delta_power_index_last[p] =
+					cali_info->delta_power_index[p];
+			RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
+			       "******Temp is higher******\n");
+			switch (p) {
+			case RF_PATH_B:
+				RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
+				       "pwrtrk_tab_up_b[%d] = %d\n", delta,
+				       pwrtrk_tab_up_b[delta]);
+
+				cali_info->delta_power_index[p] =
+							pwrtrk_tab_up_b[delta];
+				cali_info->absolute_ofdm_swing_idx[p] =
+							pwrtrk_tab_up_b[delta];
+				RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
+				       "absolute_ofdm_swing_idx[PATH_B] = %d\n",
+				       cali_info->absolute_ofdm_swing_idx[p]);
+				break;
+
+			case RF_PATH_C:
+				RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
+				       "pwrtrk_tab_up_c[%d] = %d\n", delta,
+				       pwrtrk_tab_up_c[delta]);
+
+				cali_info->delta_power_index[p] =
+							pwrtrk_tab_up_c[delta];
+				cali_info->absolute_ofdm_swing_idx[p] =
+							pwrtrk_tab_up_c[delta];
+				RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
+				       "absolute_ofdm_swing_idx[PATH_C] = %d\n",
+				       cali_info->absolute_ofdm_swing_idx[p]);
+				break;
+
+			case RF_PATH_D:
+				RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
+				       "pwrtrk_tab_up_d[%d] = %d\n", delta,
+				       pwrtrk_tab_up_d[delta]);
+
+				cali_info->delta_power_index[p] =
+							pwrtrk_tab_up_d[delta];
+				cali_info->absolute_ofdm_swing_idx[p] =
+							pwrtrk_tab_up_d[delta];
+				RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
+				       "absolute_ofdm_swing_idx[PATH_D] = %d\n",
+				       cali_info->absolute_ofdm_swing_idx[p]);
+				break;
+
+			default:
+				RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
+				       "pwrtrk_tab_up_a[%d] = %d\n", delta,
+				       pwrtrk_tab_up_a[delta]);
+
+				cali_info->delta_power_index[p] =
+							pwrtrk_tab_up_a[delta];
+				cali_info->absolute_ofdm_swing_idx[p] =
+							pwrtrk_tab_up_a[delta];
+				RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
+				       "absolute_ofdm_swing_idx[PATH_A] = %d\n",
+				       cali_info->absolute_ofdm_swing_idx[p]);
+				break;
+			}
+		}
+		/* JJ ADD 20161014 */
+		/*Save xtal_offset from Xtal table*/
+		if (dm->support_ic_type &
+		    (ODM_RTL8703B | ODM_RTL8723D | ODM_RTL8710B |
+		    ODM_RTL8192F)) {
+			/*recording last Xtal offset*/
+			cali_info->xtal_offset_last = cali_info->xtal_offset;
+			RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
+			       "[Xtal] xtal_tab_up[%d] = %d\n",
+			       delta, xtal_tab_up[delta]);
+			cali_info->xtal_offset = xtal_tab_up[delta];
+			if (cali_info->xtal_offset_last != xtal_tab_up[delta])
+				cali_info->xtal_offset_eanble = 1;
+		}
+	} else {
+		for (p = RF_PATH_A; p < c.rf_path_count; p++) {
+			/*recording power index offset*/
+			cali_info->delta_power_index_last[p] =
+						cali_info->delta_power_index[p];
+			RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
+			       "******Temp is lower******\n");
+			switch (p) {
+			case RF_PATH_B:
+				RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
+				       "pwrtrk_tab_down_b[%d] = %d\n", delta,
+				       pwrtrk_tab_down_b[delta]);
+				cali_info->delta_power_index[p] =
+						-1 * pwrtrk_tab_down_b[delta];
+				cali_info->absolute_ofdm_swing_idx[p] =
+						-1 * pwrtrk_tab_down_b[delta];
+				RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
+				       "absolute_ofdm_swing_idx[PATH_B] = %d\n",
+				       cali_info->absolute_ofdm_swing_idx[p]);
+				break;
+
+			case RF_PATH_C:
+				RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
+				       "pwrtrk_tab_down_c[%d] = %d\n", delta,
+				       pwrtrk_tab_down_c[delta]);
+				cali_info->delta_power_index[p] =
+						-1 * pwrtrk_tab_down_c[delta];
+				cali_info->absolute_ofdm_swing_idx[p] =
+						-1 * pwrtrk_tab_down_c[delta];
+				RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
+				       "absolute_ofdm_swing_idx[PATH_C] = %d\n",
+				       cali_info->absolute_ofdm_swing_idx[p]);
+				break;
+
+			case RF_PATH_D:
+				RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
+				       "pwrtrk_tab_down_d[%d] = %d\n", delta,
+				       pwrtrk_tab_down_d[delta]);
+				cali_info->delta_power_index[p] =
+						-1 * pwrtrk_tab_down_d[delta];
+				cali_info->absolute_ofdm_swing_idx[p] =
+						-1 * pwrtrk_tab_down_d[delta];
+				RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
+				       "absolute_ofdm_swing_idx[PATH_D] = %d\n",
+				       cali_info->absolute_ofdm_swing_idx[p]);
+				break;
+
+			default:
+				RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
+				       "pwrtrk_tab_down_a[%d] = %d\n", delta,
+				       pwrtrk_tab_down_a[delta]);
+				cali_info->delta_power_index[p] =
+						-1 * pwrtrk_tab_down_a[delta];
+				cali_info->absolute_ofdm_swing_idx[p] =
+						-1 * pwrtrk_tab_down_a[delta];
+				RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
+				       "absolute_ofdm_swing_idx[PATH_A] = %d\n",
+				       cali_info->absolute_ofdm_swing_idx[p]);
+				break;
+			}
+		}
+		/* JJ ADD 20161014 */
+		if (dm->support_ic_type &
+		    (ODM_RTL8703B | ODM_RTL8723D | ODM_RTL8710B |
+		    ODM_RTL8192F)) {
+			/*recording last Xtal offset*/
+			cali_info->xtal_offset_last = cali_info->xtal_offset;
+			RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
+			       "[Xtal] xtal_tab_down[%d] = %d\n", delta,
+			       xtal_tab_down[delta]);
+			/*Save xtal_offset from Xtal table*/
+			cali_info->xtal_offset = xtal_tab_down[delta];
+			if (cali_info->xtal_offset_last != xtal_tab_down[delta])
+				cali_info->xtal_offset_eanble = 1;
+		}
+	}
+}
+
+void odm_pwrtrk_method(void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	u8 p, idxforchnl = 0;
+
+	struct txpwrtrack_cfg c = {0};
+
+	configure_txpower_track(dm, &c);
+
+	if (dm->support_ic_type &
+		(ODM_RTL8188E | ODM_RTL8192E | ODM_RTL8821 | ODM_RTL8812 |
+		ODM_RTL8723B | ODM_RTL8814A | ODM_RTL8703B | ODM_RTL8188F |
+		ODM_RTL8822B | ODM_RTL8723D | ODM_RTL8821C | ODM_RTL8710B |
+		ODM_RTL8192F)) {
+		RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
+		       "***Enter PwrTrk MIX_MODE***\n");
+		for (p = RF_PATH_A; p < c.rf_path_count; p++)
+			(*c.odm_tx_pwr_track_set_pwr)(dm, MIX_MODE, p, 0);
+	} else {
+		RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
+		       "***Enter PwrTrk BBSWING_MODE***\n");
+		for (p = RF_PATH_A; p < c.rf_path_count; p++)
+			(*c.odm_tx_pwr_track_set_pwr)
+				(dm, BBSWING, p, idxforchnl);
+	}
+}
+
+#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
+void odm_txpowertracking_callback_thermal_meter(struct dm_struct *dm)
+#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
+void odm_txpowertracking_callback_thermal_meter(void *dm_void)
+#else
+void odm_txpowertracking_callback_thermal_meter(void *adapter)
+#endif
+{
+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
+	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter));
+	struct dm_struct *dm = &hal_data->DM_OutSrc;
+#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+#endif
+
+	struct _hal_rf_ *rf = &dm->rf_table;
+	struct dm_rf_calibration_struct *cali_info = &dm->rf_calibrate_info;
+	struct dm_iqk_info *iqk_info = &dm->IQK_info;
+
+	u8 thermal_value = 0, delta, delta_lck, delta_iqk, p = 0, i = 0;
+	u8 thermal_value_avg_count = 0;
+	u32 thermal_value_avg = 0, regc80, regcd0, regcd4, regab4;
+
+	/* OFDM BB Swing should be less than +3.0dB, required by Arthur */
+#if 0
+	u8 OFDM_min_index = 0;
+#endif
+	/* get_right_chnl_place_for_iqk(hal_data->current_channel) */
+	u8 power_tracking_type = rf->pwt_type;
+	s8 thermal_value_temp = 0;
+
+	struct txpwrtrack_cfg c = {0};
+
+	/* 4 2. Initialization ( 7 steps in total ) */
+
+	configure_txpower_track(dm, &c);
+
+	cali_info->txpowertracking_callback_cnt++;
+	cali_info->is_txpowertracking_init = true;
+
+	RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
+	       "\n\n\n===>%s bbsw_idx_cck_base=%d\n",
+	       __func__, cali_info->bb_swing_idx_cck_base);
+
+	RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
+	       "bbsw_idx_ofdm_base[A]=%d default_ofdm_idx=%d\n",
+	       cali_info->bb_swing_idx_ofdm_base[RF_PATH_A],
+	       cali_info->default_ofdm_index);
+
+	RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
+	       "cali_info->txpowertrack_control=%d, rf->eeprom_thermal %d\n",
+	       cali_info->txpowertrack_control, rf->eeprom_thermal);
+
+	 /* 0x42: RF Reg[15:10] 88E */
+	thermal_value =
+		(u8)odm_get_rf_reg(dm, RF_PATH_A, c.thermal_reg_addr, 0xfc00);
+
+	thermal_value_temp = thermal_value + phydm_get_thermal_offset(dm);
+
+	RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
+	       "thermal_value_temp(%d) = ther_value(%d) + pwr_trim_ther(%d)\n",
+	       thermal_value_temp, thermal_value,
+	       phydm_get_thermal_offset(dm));
+
+	if (thermal_value_temp > 63)
+		thermal_value = 63;
+	else if (thermal_value_temp < 0)
+		thermal_value = 0;
+	else
+		thermal_value = thermal_value_temp;
+
+	/*add log by zhao he, check c80/c94/c14/ca0 value*/
+	if (dm->support_ic_type &
+	    (ODM_RTL8723D | ODM_RTL8710B)) {
+		regc80 = odm_get_bb_reg(dm, R_0xc80, MASKDWORD);
+		regcd0 = odm_get_bb_reg(dm, R_0xcd0, MASKDWORD);
+		regcd4 = odm_get_bb_reg(dm, R_0xcd4, MASKDWORD);
+		regab4 = odm_get_bb_reg(dm, R_0xab4, 0x000007FF);
+		RF_DBG(dm, DBG_RF_IQK,
+		       "0xc80 = 0x%x 0xcd0 = 0x%x 0xcd4 = 0x%x 0xab4 = 0x%x\n",
+		       regc80, regcd0, regcd4, regab4);
+	}
+
+	if (!cali_info->txpowertrack_control)
+		return;
+
+	if (rf->eeprom_thermal == 0xff) {
+		RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
+		       "no pg, hal_data->eeprom_thermal_meter = 0x%x\n",
+		       rf->eeprom_thermal);
+		return;
+	}
+
+	/*4 3. Initialize ThermalValues of rf_calibrate_info*/
+
+	if (cali_info->is_reloadtxpowerindex)
+		RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
+		       "reload ofdm index for band switch\n");
+
+	/*4 4. Calculate average thermal meter*/
+
+	cali_info->thermal_value_avg[cali_info->thermal_value_avg_index]
+		= thermal_value;
+
+	cali_info->thermal_value_avg_index++;
+	/*Average times =  c.average_thermal_num*/
+	if (cali_info->thermal_value_avg_index == c.average_thermal_num)
+		cali_info->thermal_value_avg_index = 0;
+
+	for (i = 0; i < c.average_thermal_num; i++) {
+		if (cali_info->thermal_value_avg[i]) {
+			thermal_value_avg += cali_info->thermal_value_avg[i];
+			thermal_value_avg_count++;
+		}
+	}
+
+	/* Calculate Average thermal_value after average enough times */
+	if (thermal_value_avg_count) {
+		thermal_value =
+			(u8)(thermal_value_avg / thermal_value_avg_count);
+		cali_info->thermal_value_delta
+			= thermal_value - rf->eeprom_thermal;
+		RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
+		       "AVG Thermal Meter = 0x%X, EFUSE Thermal base = 0x%X\n",
+		       thermal_value, rf->eeprom_thermal);
+	}
+
+	/* 4 5. Calculate delta, delta_lck, delta_iqk. */
+	/* "delta" here is used to determine thermal value changes or not. */
+	if (thermal_value > cali_info->thermal_value)
+		delta = thermal_value - cali_info->thermal_value;
+	else
+		delta = cali_info->thermal_value - thermal_value;
+
+	if (thermal_value > cali_info->thermal_value_lck)
+		delta_lck = thermal_value - cali_info->thermal_value_lck;
+	else
+		delta_lck = cali_info->thermal_value_lck - thermal_value;
+
+	if (thermal_value > cali_info->thermal_value_iqk)
+		delta_iqk = thermal_value - cali_info->thermal_value_iqk;
+	else
+		delta_iqk = cali_info->thermal_value_iqk - thermal_value;
+
+	RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
+	       "(delta, delta_lck, delta_iqk) = (%d, %d, %d)\n", delta,
+	       delta_lck, delta_iqk);
+
+	/*4 6. If necessary, do LCK.*/
+	/* Wait sacn to do LCK by RF Jenyu*/
+	if (!(*dm->is_scan_in_process) && !iqk_info->rfk_forbidden) {
+		/* Delta temperature is equal to or larger than 20 centigrade.*/
+		if (delta_lck >= c.threshold_iqk) {
+			RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
+			       "delta_lck(%d) >= threshold_iqk(%d)\n",
+			       delta_lck, c.threshold_iqk);
+			cali_info->thermal_value_lck = thermal_value;
+
+			/*Use RTLCK, close power tracking driver LCK*/
+			/*8821 don't do LCK*/
+			if (!(dm->support_ic_type &
+				(ODM_RTL8821 | ODM_RTL8814A | ODM_RTL8822B)) &&
+				c.phy_lc_calibrate) {
+				(*c.phy_lc_calibrate)(dm);
+				RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
+				       "do pwrtrk lck\n");
+			}
+		}
+	}
+
+	/*3 7. If necessary, move the index of swing table to adjust Tx power.*/
+	/* "delta" here is used to record the absolute value of difference. */
+	if (delta > 0 && cali_info->txpowertrack_control) {
+		if (thermal_value > rf->eeprom_thermal)
+			delta = thermal_value - rf->eeprom_thermal;
+		else
+			delta = rf->eeprom_thermal - thermal_value;
+
+		if (delta >= TXPWR_TRACK_TABLE_SIZE)
+			delta = TXPWR_TRACK_TABLE_SIZE - 1;
+
+		odm_get_tracking_table(dm, thermal_value, delta);
+
+		for (p = RF_PATH_A; p < c.rf_path_count; p++) {
+			RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
+			       "\n[path-%d] Calculate pwr_idx_offset\n", p);
+
+			/*If Thermal value changes but table value is the same*/
+			if (cali_info->delta_power_index[p] ==
+				cali_info->delta_power_index_last[p])
+				cali_info->power_index_offset[p] = 0;
+			else
+				cali_info->power_index_offset[p] =
+				cali_info->delta_power_index[p] -
+				cali_info->delta_power_index_last[p];
+
+			RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
+			       "path-%d pwridx_diff%d=pwr_idx%d - last_idx%d\n",
+			       p, cali_info->power_index_offset[p],
+			       cali_info->delta_power_index[p],
+			       cali_info->delta_power_index_last[p]);
+#if 0
+
+			cali_info->OFDM_index[p] = cali_info->bb_swing_idx_ofdm_base[p] + cali_info->power_index_offset[p];
+			cali_info->CCK_index = cali_info->bb_swing_idx_cck_base + cali_info->power_index_offset[p];
+
+			cali_info->bb_swing_idx_cck = cali_info->CCK_index;
+			cali_info->bb_swing_idx_ofdm[p] = cali_info->OFDM_index[p];
+
+			/*************Print BB Swing base and index Offset*************/
+
+			RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
+			       "The 'CCK' final index(%d) = BaseIndex(%d) + power_index_offset(%d)\n",
+			       cali_info->bb_swing_idx_cck,
+			       cali_info->bb_swing_idx_cck_base,
+			       cali_info->power_index_offset[p]);
+			RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
+			       "The 'OFDM' final index(%d) = BaseIndex[%d](%d) + power_index_offset(%d)\n",
+			       cali_info->bb_swing_idx_ofdm[p], p,
+			       cali_info->bb_swing_idx_ofdm_base[p],
+			       cali_info->power_index_offset[p]);
+
+			/*4 7.1 Handle boundary conditions of index.*/
+
+			if (cali_info->OFDM_index[p] > c.swing_table_size_ofdm - 1)
+				cali_info->OFDM_index[p] = c.swing_table_size_ofdm - 1;
+			else if (cali_info->OFDM_index[p] <= OFDM_min_index)
+				cali_info->OFDM_index[p] = OFDM_min_index;
+#endif
+		}
+#if 0
+		RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
+		       "\n\n========================================================================================================\n");
+
+		if (cali_info->CCK_index > c.swing_table_size_cck - 1)
+			cali_info->CCK_index = c.swing_table_size_cck - 1;
+		else if (cali_info->CCK_index <= 0)
+			cali_info->CCK_index = 0;
+#endif
+	} else {
+		RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
+		       "Thermal is unchanged thermal=%d last_thermal=%d\n",
+		       thermal_value,
+		       cali_info->thermal_value);
+		for (p = RF_PATH_A; p < c.rf_path_count; p++)
+			cali_info->power_index_offset[p] = 0;
+	}
+
+#if 0
+	RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
+	       "TxPowerTracking: [CCK] Swing Current index: %d, Swing base index: %d\n",
+	       cali_info->CCK_index,
+	       cali_info->bb_swing_idx_cck_base); /*Print Swing base & current*/
+
+	for (p = RF_PATH_A; p < c.rf_path_count; p++) {
+		RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
+		       "TxPowerTracking: [OFDM] Swing Current index: %d, Swing base index[%d]: %d\n",
+		       cali_info->OFDM_index[p], p,
+		       cali_info->bb_swing_idx_ofdm_base[p]);
+	}
+#endif
+
+	if ((dm->support_ic_type & ODM_RTL8814A)) {
+		RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "power_tracking_type=%d\n",
+		       power_tracking_type);
+
+		if (power_tracking_type == 0) {
+			RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
+			       "***Enter PwrTrk MIX_MODE***\n");
+			for (p = RF_PATH_A; p < c.rf_path_count; p++)
+				(*c.odm_tx_pwr_track_set_pwr)
+					(dm, MIX_MODE, p, 0);
+		} else if (power_tracking_type == 1) {
+			RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
+			       "***Enter PwrTrk MIX(2G) TSSI(5G) MODE***\n");
+			for (p = RF_PATH_A; p < c.rf_path_count; p++)
+				(*c.odm_tx_pwr_track_set_pwr)
+					(dm, MIX_2G_TSSI_5G_MODE, p, 0);
+		} else if (power_tracking_type == 2) {
+			RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
+			       "***Enter PwrTrk MIX(5G) TSSI(2G)MODE***\n");
+			for (p = RF_PATH_A; p < c.rf_path_count; p++)
+				(*c.odm_tx_pwr_track_set_pwr)
+					(dm, MIX_5G_TSSI_2G_MODE, p, 0);
+		} else if (power_tracking_type == 3) {
+			RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
+			       "***Enter PwrTrk TSSI MODE***\n");
+			for (p = RF_PATH_A; p < c.rf_path_count; p++)
+				(*c.odm_tx_pwr_track_set_pwr)
+					(dm, TSSI_MODE, p, 0);
+		}
+	} else if ((cali_info->power_index_offset[RF_PATH_A] != 0 ||
+		    cali_info->power_index_offset[RF_PATH_B] != 0 ||
+		    cali_info->power_index_offset[RF_PATH_C] != 0 ||
+		    cali_info->power_index_offset[RF_PATH_D] != 0)) {
+#if 0
+		/* 4 7.2 Configure the Swing Table to adjust Tx Power. */
+		/*Always true after Tx Power is adjusted by power tracking.*/
+
+		cali_info->is_tx_power_changed = true;
+		/* 2012/04/23 MH According to Luke's suggestion, we can not write BB digital
+		 * to increase TX power. Otherwise, EVM will be bad.
+		 *
+		 * 2012/04/25 MH Add for tx power tracking to set tx power in tx agc for 88E.
+		 */
+		if (thermal_value > cali_info->thermal_value) {
+			for (p = RF_PATH_A; p < c.rf_path_count; p++) {
+				RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
+				       "Temperature Increasing(%d): delta_pi: %d, delta_t: %d, Now_t: %d, EFUSE_t: %d, Last_t: %d\n",
+				       p, cali_info->power_index_offset[p],
+				       delta, thermal_value, rf->eeprom_thermal,
+				       cali_info->thermal_value);
+			}
+		} else if (thermal_value < cali_info->thermal_value) { /*Low temperature*/
+			for (p = RF_PATH_A; p < c.rf_path_count; p++) {
+				RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
+				       "Temperature Decreasing(%d): delta_pi: %d, delta_t: %d, Now_t: %d, EFUSE_t: %d, Last_t: %d\n",
+				       p, cali_info->power_index_offset[p],
+				       delta, thermal_value, rf->eeprom_thermal,
+				       cali_info->thermal_value);
+			}
+		}
+#endif
+
+#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
+		if (thermal_value > rf->eeprom_thermal) {
+#else
+		if (thermal_value > dm->priv->pmib->dot11RFEntry.ther) {
+#endif
+			RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
+			       "Temperature(%d) higher than PG value(%d)\n",
+			       thermal_value, rf->eeprom_thermal);
+
+			odm_pwrtrk_method(dm);
+		} else {
+			RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
+			       "Temperature(%d) lower than PG value(%d)\n",
+			       thermal_value, rf->eeprom_thermal);
+
+			odm_pwrtrk_method(dm);
+		}
+
+#if 0
+		/*Record last time Power Tracking result as base.*/
+		cali_info->bb_swing_idx_cck_base = cali_info->bb_swing_idx_cck;
+		for (p = RF_PATH_A; p < c.rf_path_count; p++)
+			cali_info->bb_swing_idx_ofdm_base[p] = cali_info->bb_swing_idx_ofdm[p];
+#endif
+		RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
+		       "cali_info->thermal_value = %d thermal_value= %d\n",
+		       cali_info->thermal_value, thermal_value);
+	}
+	/*Record last Power Tracking Thermal value*/
+	cali_info->thermal_value = thermal_value;
+
+	if (dm->support_ic_type &
+		(ODM_RTL8703B | ODM_RTL8723D | ODM_RTL8192F | ODM_RTL8710B)) {
+		if (cali_info->xtal_offset_eanble != 0 &&
+		    cali_info->txpowertrack_control &&
+		    rf->eeprom_thermal != 0xff) {
+			RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
+			       "**********Enter Xtal Tracking**********\n");
+
+#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
+			if (thermal_value > rf->eeprom_thermal) {
+#else
+			if (thermal_value > dm->priv->pmib->dot11RFEntry.ther) {
+#endif
+				RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
+				       "Temperature(%d) higher than PG (%d)\n",
+				       thermal_value, rf->eeprom_thermal);
+				(*c.odm_txxtaltrack_set_xtal)(dm);
+			} else {
+				RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
+				       "Temperature(%d) lower than PG (%d)\n",
+				       thermal_value, rf->eeprom_thermal);
+				(*c.odm_txxtaltrack_set_xtal)(dm);
+			}
+		}
+		RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
+		       "**********End Xtal Tracking**********\n");
+	}
+
+#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
+
+	/* Wait sacn to do IQK by RF Jenyu*/
+	if (!(*dm->is_scan_in_process) && !iqk_info->rfk_forbidden &&
+	    !cali_info->is_iqk_in_progress) {
+		if (!(dm->support_ic_type & ODM_RTL8723B)) {
+			/*Delta temperature is equal or larger than 20 Celsius*/
+			/*When threshold is 8*/
+			if (delta_iqk >= c.threshold_iqk) {
+				cali_info->thermal_value_iqk = thermal_value;
+				RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
+				       "delta_iqk(%d) >= threshold_iqk(%d)\n",
+				       delta_iqk, c.threshold_iqk);
+				(*c.do_iqk)(dm, delta_iqk, thermal_value, 8);
+				RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
+				       "do pwrtrk iqk\n");
+			}
+		}
+	}
+
+#if 0
+	if (cali_info->dpk_thermal[RF_PATH_A] != 0) {
+		if (diff_DPK[RF_PATH_A] >= c.threshold_dpk) {
+			odm_set_bb_reg(dm, R_0x82c, BIT(31), 0x1);
+			odm_set_bb_reg(dm, R_0xcc4, BIT(14) | BIT(13) | BIT(12) | BIT(11) | BIT(10), (diff_DPK[RF_PATH_A] / c.threshold_dpk));
+			odm_set_bb_reg(dm, R_0x82c, BIT(31), 0x0);
+		} else if ((diff_DPK[RF_PATH_A] <= -1 * c.threshold_dpk)) {
+			s32 value = 0x20 + (diff_DPK[RF_PATH_A] / c.threshold_dpk);
+
+			odm_set_bb_reg(dm, R_0x82c, BIT(31), 0x1);
+			odm_set_bb_reg(dm, R_0xcc4, BIT(14) | BIT(13) | BIT(12) | BIT(11) | BIT(10), value);
+			odm_set_bb_reg(dm, R_0x82c, BIT(31), 0x0);
+		} else {
+			odm_set_bb_reg(dm, R_0x82c, BIT(31), 0x1);
+			odm_set_bb_reg(dm, R_0xcc4, BIT(14) | BIT(13) | BIT(12) | BIT(11) | BIT(10), 0);
+			odm_set_bb_reg(dm, R_0x82c, BIT(31), 0x0);
+		}
+	}
+	if (cali_info->dpk_thermal[RF_PATH_B] != 0) {
+		if (diff_DPK[RF_PATH_B] >= c.threshold_dpk) {
+			odm_set_bb_reg(dm, R_0x82c, BIT(31), 0x1);
+			odm_set_bb_reg(dm, R_0xec4, BIT(14) | BIT(13) | BIT(12) | BIT(11) | BIT(10), (diff_DPK[RF_PATH_B] / c.threshold_dpk));
+			odm_set_bb_reg(dm, R_0x82c, BIT(31), 0x0);
+		} else if ((diff_DPK[RF_PATH_B] <= -1 * c.threshold_dpk)) {
+			s32 value = 0x20 + (diff_DPK[RF_PATH_B] / c.threshold_dpk);
+
+			odm_set_bb_reg(dm, R_0x82c, BIT(31), 0x1);
+			odm_set_bb_reg(dm, R_0xec4, BIT(14) | BIT(13) | BIT(12) | BIT(11) | BIT(10), value);
+			odm_set_bb_reg(dm, R_0x82c, BIT(31), 0x0);
+		} else {
+			odm_set_bb_reg(dm, R_0x82c, BIT(31), 0x1);
+			odm_set_bb_reg(dm, R_0xec4, BIT(14) | BIT(13) | BIT(12) | BIT(11) | BIT(10), 0);
+			odm_set_bb_reg(dm, R_0x82c, BIT(31), 0x0);
+		}
+	}
+#endif
+
+#endif
+
+	RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "<===%s\n", __func__);
+
+	cali_info->tx_powercount = 0;
+}
+
+/* 3============================================================
+ * 3 IQ Calibration
+ * 3============================================================
+ */
+
+void odm_reset_iqk_result(void *dm_void)
+{
+}
+
+#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
+u8 odm_get_right_chnl_place_for_iqk(u8 chnl)
+{
+	u8 channel_all[ODM_TARGET_CHNL_NUM_2G_5G] = {
+		1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14,
+		36, 38, 40, 42, 44, 46, 48, 50, 52, 54, 56, 58, 60, 62, 64,
+		100, 102, 104, 106, 108, 110, 112, 114, 116, 118, 120, 122,
+		124, 126, 128, 130, 132, 134, 136, 138, 140,
+		149, 151, 153, 155, 157, 159, 161, 163, 165};
+	u8 place = chnl;
+
+	if (chnl > 14) {
+		for (place = 14; place < sizeof(channel_all); place++) {
+			if (channel_all[place] == chnl)
+				return place - 13;
+		}
+	}
+	return 0;
+}
+#endif
+
+void odm_iq_calibrate(struct dm_struct *dm)
+{
+	void *adapter = dm->adapter;
+	struct dm_iqk_info *iqk_info = &dm->IQK_info;
+
+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
+	if (*dm->is_fcs_mode_enable)
+		return;
+#endif
+
+#if (DM_ODM_SUPPORT_TYPE & (ODM_CE))
+	if (IS_HARDWARE_TYPE_8812AU(adapter))
+		return;
+#endif
+
+	if (dm->is_linked && !iqk_info->rfk_forbidden) {
+		if ((*dm->channel != dm->pre_channel) &&
+		    (!*dm->is_scan_in_process)) {
+			dm->pre_channel = *dm->channel;
+			dm->linked_interval = 0;
+		}
+
+		if (dm->linked_interval < 3)
+			dm->linked_interval++;
+
+		if (dm->linked_interval == 2)
+			halrf_iqk_trigger(dm, false);
+	} else {
+		dm->linked_interval = 0;
+	}
+}
+
+void phydm_rf_init(void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+
+	odm_txpowertracking_init(dm);
+
+#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
+	odm_clear_txpowertracking_state(dm);
+#endif
+#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
+#if (RTL8814A_SUPPORT == 1)
+	if (dm->support_ic_type & ODM_RTL8814A)
+		phy_iq_calibrate_8814a_init(dm);
+#endif
+#endif
+}
+
+void phydm_rf_watchdog(void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
+	odm_txpowertracking_check(dm);
+#if 0
+/*if (dm->support_ic_type & ODM_IC_11AC_SERIES)*/
+/*odm_iq_calibrate(dm);*/
+#endif
+#endif
+}
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/halrf/halphyrf_ce.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/halrf/halphyrf_ce.h
--- linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/halrf/halphyrf_ce.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/halrf/halphyrf_ce.h	2020-04-10 16:35:06.819660208 +0300
@@ -0,0 +1,110 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017  Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * The full GNU General Public License is included in this distribution in the
+ * file called LICENSE.
+ *
+ * Contact Information:
+ * wlanfae <wlanfae@realtek.com>
+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
+ * Hsinchu 300, Taiwan.
+ *
+ * Larry Finger <Larry.Finger@lwfinger.net>
+ *
+ *****************************************************************************/
+
+#ifndef __HALPHYRF_H__
+#define __HALPHYRF_H__
+
+#include "halrf/halrf_kfree.h"
+#if (RTL8814A_SUPPORT == 1)
+#include "halrf/rtl8814a/halrf_iqk_8814a.h"
+#endif
+
+#if (RTL8822B_SUPPORT == 1)
+#include "halrf/rtl8822b/halrf_iqk_8822b.h"
+#endif
+
+#if (RTL8821C_SUPPORT == 1)
+#include "halrf/rtl8821c/halrf_iqk_8821c.h"
+#endif
+
+#if (RTL8195B_SUPPORT == 1)
+/* #include "halrf/rtl8195b/halrf.h" */
+#include "halrf/rtl8195b/halrf_iqk_8195b.h"
+#include "halrf/rtl8195b/halrf_txgapk_8195b.h"
+#include "halrf/rtl8195b/halrf_dpk_8195b.h"
+#endif
+
+#include "halrf/halrf_powertracking_ce.h"
+
+enum spur_cal_method {
+	PLL_RESET,
+	AFE_PHASE_SEL
+};
+
+enum pwrtrack_method {
+	BBSWING,
+	TXAGC,
+	MIX_MODE,
+	TSSI_MODE,
+	MIX_2G_TSSI_5G_MODE,
+	MIX_5G_TSSI_2G_MODE
+};
+
+typedef void (*func_set_pwr)(void *, enum pwrtrack_method, u8, u8);
+typedef void (*func_iqk)(void *, u8, u8, u8);
+typedef void (*func_lck)(void *);
+typedef void (*func_swing)(void *, u8 **, u8 **, u8 **, u8 **);
+typedef void (*func_swing8814only)(void *, u8 **, u8 **, u8 **, u8 **);
+typedef void (*func_swing_xtal)(void *, s8 **, s8 **);
+typedef void (*func_set_xtal)(void *);
+
+struct txpwrtrack_cfg {
+	u8 swing_table_size_cck;
+	u8 swing_table_size_ofdm;
+	u8 threshold_iqk;
+	u8 threshold_dpk;
+	u8 average_thermal_num;
+	u8 rf_path_count;
+	u32 thermal_reg_addr;
+	func_set_pwr odm_tx_pwr_track_set_pwr;
+	func_iqk do_iqk;
+	func_lck phy_lc_calibrate;
+	func_swing get_delta_swing_table;
+	func_swing8814only get_delta_swing_table8814only;
+	func_swing_xtal get_delta_swing_xtal_table;
+	func_set_xtal odm_txxtaltrack_set_xtal;
+};
+
+void configure_txpower_track(void *dm_void, struct txpwrtrack_cfg *config);
+
+void odm_clear_txpowertracking_state(void *dm_void);
+
+#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
+void odm_txpowertracking_callback_thermal_meter(void *dm_void);
+#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
+void odm_txpowertracking_callback_thermal_meter(void *dm);
+#else
+void odm_txpowertracking_callback_thermal_meter(void *adapter);
+#endif
+
+#define ODM_TARGET_CHNL_NUM_2G_5G 59
+
+void odm_reset_iqk_result(void *dm_void);
+u8 odm_get_right_chnl_place_for_iqk(u8 chnl);
+
+void phydm_rf_init(void *dm_void);
+void phydm_rf_watchdog(void *dm_void);
+
+#endif /*#ifndef __HALPHYRF_H__*/
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/halrf/halphyrf_iot.c linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/halrf/halphyrf_iot.c
--- linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/halrf/halphyrf_iot.c	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/halrf/halphyrf_iot.c	2020-04-10 16:35:06.819660208 +0300
@@ -0,0 +1,478 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017  Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * The full GNU General Public License is included in this distribution in the
+ * file called LICENSE.
+ *
+ * Contact Information:
+ * wlanfae <wlanfae@realtek.com>
+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
+ * Hsinchu 300, Taiwan.
+ *
+ * Larry Finger <Larry.Finger@lwfinger.net>
+ *
+ *****************************************************************************/
+
+#include "mp_precomp.h"
+#include "phydm_precomp.h"
+
+#define	CALCULATE_SWINGTALBE_OFFSET(_offset, _direction, _size, _delta_thermal) \
+	do {\
+		for (_offset = 0; _offset < _size; _offset++) { \
+			if (_delta_thermal < thermal_threshold[_direction][_offset]) { \
+				if (_offset != 0)\
+					_offset--;\
+				break;\
+			} \
+		}			\
+		if (_offset >= _size)\
+			_offset = _size-1;\
+	} while (0)
+
+void configure_txpower_track(
+	void					*dm_void,
+	struct txpwrtrack_cfg	*config
+)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+#if RTL8195B_SUPPORT
+	if (dm->support_ic_type == ODM_RTL8195B)
+		configure_txpower_track_8195b(config);
+#endif
+
+}
+
+/* **********************************************************************
+ * <20121113, Kordan> This function should be called when tx_agc changed.
+ * Otherwise the previous compensation is gone, because we record the
+ * delta of temperature between two TxPowerTracking watch dogs.
+ *
+ * NOTE: If Tx BB swing or Tx scaling is varified during run-time, still
+ * need to call this function.
+ * ********************************************************************** */
+void
+odm_clear_txpowertracking_state(
+	void					*dm_void
+)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct _hal_rf_ *rf = &dm->rf_table;
+	u8			p = 0;
+	struct dm_rf_calibration_struct	*cali_info = &dm->rf_calibrate_info;
+
+	cali_info->bb_swing_idx_cck_base = cali_info->default_cck_index;
+	cali_info->bb_swing_idx_cck = cali_info->default_cck_index;
+	dm->rf_calibrate_info.CCK_index = 0;
+
+	for (p = RF_PATH_A; p < MAX_RF_PATH; ++p) {
+		cali_info->bb_swing_idx_ofdm_base[p] = cali_info->default_ofdm_index;
+		cali_info->bb_swing_idx_ofdm[p] = cali_info->default_ofdm_index;
+		cali_info->OFDM_index[p] = cali_info->default_ofdm_index;
+
+		cali_info->power_index_offset[p] = 0;
+		cali_info->delta_power_index[p] = 0;
+		cali_info->delta_power_index_last[p] = 0;
+
+		cali_info->absolute_ofdm_swing_idx[p] = 0;
+		cali_info->remnant_ofdm_swing_idx[p] = 0;
+		cali_info->kfree_offset[p] = 0;
+	}
+
+	cali_info->modify_tx_agc_flag_path_a = false;
+	cali_info->modify_tx_agc_flag_path_b = false;
+	cali_info->modify_tx_agc_flag_path_c = false;
+	cali_info->modify_tx_agc_flag_path_d = false;
+	cali_info->remnant_cck_swing_idx = 0;
+	cali_info->thermal_value = rf->eeprom_thermal;
+	cali_info->modify_tx_agc_value_cck = 0;
+	cali_info->modify_tx_agc_value_ofdm = 0;
+}
+
+void
+odm_txpowertracking_callback_thermal_meter(
+	void	*dm_void
+)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct _hal_rf_ *rf = &dm->rf_table;
+	struct dm_rf_calibration_struct *cali_info = &dm->rf_calibrate_info;
+	struct	dm_iqk_info *iqk_info = &dm->IQK_info;
+
+	u8 thermal_value = 0, delta, delta_LCK, delta_IQK, p = 0, i = 0;
+	u8 thermal_value_avg_count = 0;
+	u32 thermal_value_avg = 0, regc80, regcd0, regcd4, regab4;
+
+	u8 OFDM_min_index = 0;  /* OFDM BB Swing should be less than +3.0dB, which is required by Arthur */
+	u8 indexforchannel = 0; /* get_right_chnl_place_for_iqk(hal_data->current_channel) */
+	u8 power_tracking_type = rf->pwt_type;
+	u8 xtal_offset_eanble = 0;
+	s8 thermal_value_temp = 0;
+
+	struct txpwrtrack_cfg	c = {0};
+
+	/* 4 1. The following TWO tables decide the final index of OFDM/CCK swing table. */
+	u8 *delta_swing_table_idx_tup_a = NULL;
+	u8 *delta_swing_table_idx_tdown_a = NULL;
+	u8 *delta_swing_table_idx_tup_b = NULL;
+	u8 *delta_swing_table_idx_tdown_b = NULL;
+	/*for Xtal Offset by James.Tung*/
+	s8 *delta_swing_table_xtal_up = NULL;
+	s8 *delta_swing_table_xtal_down = NULL;
+
+	/* 4 2. Initialization ( 7 steps in total ) */
+
+	configure_txpower_track(dm, &c);
+
+	(*c.get_delta_swing_table)(dm, (u8 **)&delta_swing_table_idx_tup_a, (u8 **)&delta_swing_table_idx_tdown_a,
+		(u8 **)&delta_swing_table_idx_tup_b, (u8 **)&delta_swing_table_idx_tdown_b);
+
+	if (dm->support_ic_type & ODM_RTL8195B)	/*for Xtal Offset*/
+		(*c.get_delta_swing_xtal_table)(dm, (s8 **)&delta_swing_table_xtal_up, (s8 **)&delta_swing_table_xtal_down);
+
+	cali_info->txpowertracking_callback_cnt++;	/*cosa add for debug*/
+	cali_info->is_txpowertracking_init = true;
+
+	RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
+	       "===>odm_txpowertracking_callback_thermal_meter\n cali_info->bb_swing_idx_cck_base: %d, cali_info->bb_swing_idx_ofdm_base[A]: %d, cali_info->default_ofdm_index: %d\n",
+	       cali_info->bb_swing_idx_cck_base, cali_info->bb_swing_idx_ofdm_base[RF_PATH_A], cali_info->default_ofdm_index);
+
+	RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
+	       "cali_info->txpowertrack_control = %d, hal_data->eeprom_thermal_meter %d\n", cali_info->txpowertrack_control, rf->eeprom_thermal);
+
+	thermal_value = (u8)odm_get_rf_reg(dm, RF_PATH_A, c.thermal_reg_addr, 0xfc00);	/* 0x42: RF Reg[15:10] 88E */
+
+	thermal_value_temp = thermal_value + phydm_get_thermal_offset(dm);
+
+	RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
+	       "thermal_value_temp(%d) = thermal_value(%d) + power_trim_thermal(%d)\n", thermal_value_temp, thermal_value, phydm_get_thermal_offset(dm));
+
+	if (thermal_value_temp > 63)
+		thermal_value = 63;
+	else if (thermal_value_temp < 0)
+		thermal_value = 0;
+	else
+		thermal_value = thermal_value_temp;
+
+	if (!cali_info->txpowertrack_control)
+		return;
+
+	if (rf->eeprom_thermal == 0xff) {
+		RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "no pg, hal_data->eeprom_thermal_meter = 0x%x\n", rf->eeprom_thermal);
+		return;
+	}
+
+	/*4 3. Initialize ThermalValues of rf_calibrate_info*/
+	//if (cali_info->is_reloadtxpowerindex)
+	//	RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "reload ofdm index for band switch\n");
+
+	/*4 4. Calculate average thermal meter*/
+
+	cali_info->thermal_value_avg[cali_info->thermal_value_avg_index] = thermal_value;
+	cali_info->thermal_value_avg_index++;
+	if (cali_info->thermal_value_avg_index == c.average_thermal_num)   /*Average times =  c.average_thermal_num*/
+		cali_info->thermal_value_avg_index = 0;
+
+	for (i = 0; i < c.average_thermal_num; i++) {
+		if (cali_info->thermal_value_avg[i]) {
+			thermal_value_avg += cali_info->thermal_value_avg[i];
+			thermal_value_avg_count++;
+		}
+	}
+
+	if (thermal_value_avg_count) {			  /* Calculate Average thermal_value after average enough times */
+		thermal_value = (u8)(thermal_value_avg / thermal_value_avg_count);
+		cali_info->thermal_value_delta = thermal_value - rf->eeprom_thermal;
+		RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
+		       "AVG Thermal Meter = 0x%X, EFUSE Thermal base = 0x%X\n", thermal_value, rf->eeprom_thermal);
+	}
+
+	/* 4 5. Calculate delta, delta_LCK, delta_IQK. */
+	/* "delta" here is used to determine whether thermal value changes or not. */
+	delta	= (thermal_value > cali_info->thermal_value) ? (thermal_value - cali_info->thermal_value) : (cali_info->thermal_value - thermal_value);
+	delta_LCK = (thermal_value > cali_info->thermal_value_lck) ? (thermal_value - cali_info->thermal_value_lck) : (cali_info->thermal_value_lck - thermal_value);
+	delta_IQK = (thermal_value > cali_info->thermal_value_iqk) ? (thermal_value - cali_info->thermal_value_iqk) : (cali_info->thermal_value_iqk - thermal_value);
+
+	/*4 6. If necessary, do LCK.*/
+	RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "(delta, delta_LCK, delta_IQK) = (%d, %d, %d)\n", delta, delta_LCK, delta_IQK);
+
+	/* Wait sacn to do LCK by RF Jenyu*/
+	if ((!*dm->is_scan_in_process) && (!iqk_info->rfk_forbidden)) {
+		/* Delta temperature is equal to or larger than 20 centigrade.*/
+		if (delta_LCK >= c.threshold_iqk) {
+			RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "delta_LCK(%d) >= threshold_iqk(%d)\n", delta_LCK, c.threshold_iqk);
+			cali_info->thermal_value_lck = thermal_value;
+
+			/*Use RTLCK, so close power tracking driver LCK*/
+			(*c.phy_lc_calibrate)(dm);
+		}
+	}
+
+	/*3 7. If necessary, move the index of swing table to adjust Tx power.*/
+	if (delta > 0 && cali_info->txpowertrack_control) {
+		/* "delta" here is used to record the absolute value of difference. */
+		delta = thermal_value > rf->eeprom_thermal ? (thermal_value - rf->eeprom_thermal) : (rf->eeprom_thermal - thermal_value);
+
+		if (delta >= TXPWR_TRACK_TABLE_SIZE)
+			delta = TXPWR_TRACK_TABLE_SIZE - 1;
+
+		/*4 7.1 The Final Power index = BaseIndex + power_index_offset*/
+		if (thermal_value > rf->eeprom_thermal) {
+			for (p = RF_PATH_A; p < c.rf_path_count; p++) {
+				cali_info->delta_power_index_last[p] = cali_info->delta_power_index[p]; /*recording poer index offset*/
+				switch (p) {
+				case RF_PATH_B:
+					RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
+					       "delta_swing_table_idx_tup_b[%d] = %d\n", delta, delta_swing_table_idx_tup_b[delta]);
+
+					cali_info->delta_power_index[p] = delta_swing_table_idx_tup_b[delta];
+					cali_info->absolute_ofdm_swing_idx[p] =  delta_swing_table_idx_tup_b[delta];	   /*Record delta swing for mix mode power tracking*/
+					RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
+					       "******Temp is higher and cali_info->absolute_ofdm_swing_idx[RF_PATH_B] = %d\n", cali_info->absolute_ofdm_swing_idx[p]);
+					break;
+
+				default:
+					RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
+					       "delta_swing_table_idx_tup_a[%d] = %d\n", delta, delta_swing_table_idx_tup_a[delta]);
+
+					cali_info->delta_power_index[p] = delta_swing_table_idx_tup_a[delta];
+					cali_info->absolute_ofdm_swing_idx[p] =  delta_swing_table_idx_tup_a[delta];		/*Record delta swing for mix mode power tracking*/
+					RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
+					       "******Temp is higher and cali_info->absolute_ofdm_swing_idx[RF_PATH_A] = %d\n", cali_info->absolute_ofdm_swing_idx[p]);
+					break;
+				}
+			}
+			/* JJ ADD 20161014 */
+			if (dm->support_ic_type & ODM_RTL8195B) {
+				/*Save xtal_offset from Xtal table*/
+				cali_info->xtal_offset_last = cali_info->xtal_offset;	/*recording last Xtal offset*/
+				RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
+				       "[Xtal] delta_swing_table_xtal_up[%d] = %d\n", delta, delta_swing_table_xtal_up[delta]);
+				cali_info->xtal_offset = delta_swing_table_xtal_up[delta];
+				xtal_offset_eanble = (cali_info->xtal_offset_last != cali_info->xtal_offset);
+			}
+
+		} else {
+			for (p = RF_PATH_A; p < c.rf_path_count; p++) {
+				cali_info->delta_power_index_last[p] = cali_info->delta_power_index[p]; /*recording poer index offset*/
+
+				switch (p) {
+				case RF_PATH_B:
+					RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
+					       "delta_swing_table_idx_tdown_b[%d] = %d\n", delta, delta_swing_table_idx_tdown_b[delta]);
+					cali_info->delta_power_index[p] = -1 * delta_swing_table_idx_tdown_b[delta];
+					cali_info->absolute_ofdm_swing_idx[p] = -1 * delta_swing_table_idx_tdown_b[delta]; /*Record delta swing for mix mode power tracking*/
+					RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
+					       "******Temp is lower and cali_info->absolute_ofdm_swing_idx[RF_PATH_B] = %d\n", cali_info->absolute_ofdm_swing_idx[p]);
+					break;
+
+				default:
+					RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
+					       "delta_swing_table_idx_tdown_a[%d] = %d\n", delta, delta_swing_table_idx_tdown_a[delta]);
+					cali_info->delta_power_index[p] = -1 * delta_swing_table_idx_tdown_a[delta];
+					cali_info->absolute_ofdm_swing_idx[p] = -1 * delta_swing_table_idx_tdown_a[delta]; /*Record delta swing for mix mode power tracking*/
+					RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
+					       "******Temp is lower and cali_info->absolute_ofdm_swing_idx[RF_PATH_A] = %d\n", cali_info->absolute_ofdm_swing_idx[p]);
+					break;
+				}
+			}
+			/* JJ ADD 20161014 */
+
+			if (dm->support_ic_type & ODM_RTL8195B) {
+				/*Save xtal_offset from Xtal table*/
+				cali_info->xtal_offset_last = cali_info->xtal_offset;	/*recording last Xtal offset*/
+				RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
+				       "[Xtal] delta_swing_table_xtal_down[%d] = %d\n", delta, delta_swing_table_xtal_down[delta]);
+				cali_info->xtal_offset = delta_swing_table_xtal_down[delta];
+				xtal_offset_eanble = (cali_info->xtal_offset_last != cali_info->xtal_offset);
+			}
+		}
+#if 0
+		for (p = RF_PATH_A; p < c.rf_path_count; p++) {
+			RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
+			       "\n\n=========================== [path-%d] Calculating power_index_offset===========================\n", p);
+
+			if (cali_info->delta_power_index[p] == cali_info->delta_power_index_last[p])		 /*If Thermal value changes but lookup table value still the same*/
+				cali_info->power_index_offset[p] = 0;
+			else
+				cali_info->power_index_offset[p] = cali_info->delta_power_index[p] - cali_info->delta_power_index_last[p];		/*Power index diff between 2 times Power Tracking*/
+
+			RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
+			       "[path-%d] power_index_offset(%d) = delta_power_index(%d) - delta_power_index_last(%d)\n", p, cali_info->power_index_offset[p], cali_info->delta_power_index[p], cali_info->delta_power_index_last[p]);
+
+			cali_info->OFDM_index[p] = cali_info->bb_swing_idx_ofdm_base[p] + cali_info->power_index_offset[p];
+			cali_info->CCK_index = cali_info->bb_swing_idx_cck_base + cali_info->power_index_offset[p];
+
+			cali_info->bb_swing_idx_cck = cali_info->CCK_index;
+			cali_info->bb_swing_idx_ofdm[p] = cali_info->OFDM_index[p];
+
+			/*************Print BB Swing base and index Offset*************/
+
+			RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
+			       "The 'CCK' final index(%d) = BaseIndex(%d) + power_index_offset(%d)\n", cali_info->bb_swing_idx_cck, cali_info->bb_swing_idx_cck_base, cali_info->power_index_offset[p]);
+			RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
+			       "The 'OFDM' final index(%d) = BaseIndex[%d](%d) + power_index_offset(%d)\n", cali_info->bb_swing_idx_ofdm[p], p, cali_info->bb_swing_idx_ofdm_base[p], cali_info->power_index_offset[p]);
+
+			/*4 7.1 Handle boundary conditions of index.*/
+
+			if (cali_info->OFDM_index[p] > c.swing_table_size_ofdm - 1)
+				cali_info->OFDM_index[p] = c.swing_table_size_ofdm - 1;
+			else if (cali_info->OFDM_index[p] <= OFDM_min_index)
+				cali_info->OFDM_index[p] = OFDM_min_index;
+		}
+
+		RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
+		       "\n\n========================================================================================================\n");
+
+		if (cali_info->CCK_index > c.swing_table_size_cck - 1)
+			cali_info->CCK_index = c.swing_table_size_cck - 1;
+		else if (cali_info->CCK_index <= 0)
+			cali_info->CCK_index = 0;
+#endif
+	} else {
+		RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
+		       "The thermal meter is unchanged or TxPowerTracking OFF(%d): thermal_value: %d, cali_info->thermal_value: %d\n",
+		       cali_info->txpowertrack_control, thermal_value, cali_info->thermal_value);
+
+		for (p = RF_PATH_A; p < c.rf_path_count; p++)
+			cali_info->power_index_offset[p] = 0;
+	}
+#if 0
+	RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
+	       "TxPowerTracking: [CCK] Swing Current index: %d, Swing base index: %d\n",
+	       cali_info->CCK_index, cali_info->bb_swing_idx_cck_base);	   /*Print Swing base & current*/
+
+	for (p = RF_PATH_A; p < c.rf_path_count; p++) {
+		RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
+		       "TxPowerTracking: [OFDM] Swing Current index: %d, Swing base index[%d]: %d\n",
+		       cali_info->OFDM_index[p], p, cali_info->bb_swing_idx_ofdm_base[p]);
+	}
+#endif
+	if (thermal_value > rf->eeprom_thermal) {
+		RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
+		       "Temperature(%d) higher than PG value(%d)\n", thermal_value, rf->eeprom_thermal);
+
+		if (dm->support_ic_type == ODM_RTL8188E || dm->support_ic_type == ODM_RTL8192E || dm->support_ic_type == ODM_RTL8821 ||
+		    dm->support_ic_type == ODM_RTL8812 || dm->support_ic_type == ODM_RTL8723B || dm->support_ic_type == ODM_RTL8814A ||
+		    dm->support_ic_type == ODM_RTL8703B || dm->support_ic_type == ODM_RTL8188F || dm->support_ic_type == ODM_RTL8822B ||
+		    dm->support_ic_type == ODM_RTL8723D || dm->support_ic_type == ODM_RTL8821C || dm->support_ic_type == ODM_RTL8710B ||
+		    dm->support_ic_type == ODM_RTL8192F || dm->support_ic_type == ODM_RTL8195B){
+			RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "**********Enter POWER Tracking MIX_MODE**********\n");
+			for (p = RF_PATH_A; p < c.rf_path_count; p++)
+				(*c.odm_tx_pwr_track_set_pwr)(dm, MIX_MODE, p, 0);
+		} else {
+			RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "**********Enter POWER Tracking BBSWING_MODE**********\n");
+			for (p = RF_PATH_A; p < c.rf_path_count; p++)
+				(*c.odm_tx_pwr_track_set_pwr)(dm, BBSWING, p, indexforchannel);
+		}
+	} else {
+		RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
+		       "Temperature(%d) lower than PG value(%d)\n", thermal_value, rf->eeprom_thermal);
+
+		if (dm->support_ic_type == ODM_RTL8188E || dm->support_ic_type == ODM_RTL8192E || dm->support_ic_type == ODM_RTL8821 ||
+		    dm->support_ic_type == ODM_RTL8812 || dm->support_ic_type == ODM_RTL8723B || dm->support_ic_type == ODM_RTL8814A ||
+		    dm->support_ic_type == ODM_RTL8703B || dm->support_ic_type == ODM_RTL8188F || dm->support_ic_type == ODM_RTL8822B ||
+		    dm->support_ic_type == ODM_RTL8723D || dm->support_ic_type == ODM_RTL8821C || dm->support_ic_type == ODM_RTL8710B ||
+		    dm->support_ic_type == ODM_RTL8192F || dm->support_ic_type == ODM_RTL8195B) {
+			RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "**********Enter POWER Tracking MIX_MODE**********\n");
+			for (p = RF_PATH_A; p < c.rf_path_count; p++)
+				(*c.odm_tx_pwr_track_set_pwr)(dm, MIX_MODE, p, indexforchannel);
+		} else {
+			RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "**********Enter POWER Tracking BBSWING_MODE**********\n");
+			for (p = RF_PATH_A; p < c.rf_path_count; p++)
+				(*c.odm_tx_pwr_track_set_pwr)(dm, BBSWING, p, indexforchannel);
+		}
+
+		cali_info->bb_swing_idx_cck_base = cali_info->bb_swing_idx_cck;    /*Record last time Power Tracking result as base.*/
+		for (p = RF_PATH_A; p < c.rf_path_count; p++)
+			cali_info->bb_swing_idx_ofdm_base[p] = cali_info->bb_swing_idx_ofdm[p];
+
+		RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
+		       "cali_info->thermal_value = %d thermal_value= %d\n", cali_info->thermal_value, thermal_value);
+
+		cali_info->thermal_value = thermal_value; /*Record last Power Tracking Thermal value*/
+	}
+
+	if (dm->support_ic_type == ODM_RTL8195B) {/* JJ ADD 20161014 */
+		if (xtal_offset_eanble != 0 && cali_info->txpowertrack_control && (rf->eeprom_thermal != 0xff)) {
+			RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "**********Enter Xtal Tracking**********\n");
+
+			if (thermal_value > rf->eeprom_thermal) {
+				RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
+				       "Temperature(%d) higher than PG value(%d)\n", thermal_value, rf->eeprom_thermal);
+				(*c.odm_txxtaltrack_set_xtal)(dm);
+			} else {
+				RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
+				       "Temperature(%d) lower than PG value(%d)\n", thermal_value, rf->eeprom_thermal);
+				(*c.odm_txxtaltrack_set_xtal)(dm);
+			}
+			RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "**********End Xtal Tracking**********\n");
+		}
+	}
+
+	/* Wait sacn to do IQK by RF Jenyu*/
+	if ((!*dm->is_scan_in_process) && (!iqk_info->rfk_forbidden)) {
+		/*Delta temperature is equal to or larger than 20 centigrade (When threshold is 8).*/
+		if (delta_IQK >= c.threshold_iqk) {
+			cali_info->thermal_value_iqk = thermal_value;
+			RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "delta_IQK(%d) >= threshold_iqk(%d)\n", delta_IQK, c.threshold_iqk);
+			if (!cali_info->is_iqk_in_progress)
+				(*c.do_iqk)(dm, delta_IQK, thermal_value, 8);
+		}
+	}
+
+	RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "<===odm_txpowertracking_callback_thermal_meter\n");
+
+	cali_info->tx_powercount = 0;
+}
+
+/* 3============================================================
+ * 3 IQ Calibration
+ * 3============================================================
+ */
+
+void
+odm_reset_iqk_result(
+	void					*dm_void
+)
+{
+	return;
+}
+
+u8 odm_get_right_chnl_place_for_iqk(u8 chnl)
+{
+	
+}
+
+void
+odm_iq_calibrate(
+	struct dm_struct	*dm
+)
+{
+	
+}
+
+void phydm_rf_init(void		*dm_void)
+{
+	struct dm_struct	*dm = (struct dm_struct *)dm_void;
+
+	odm_txpowertracking_init(dm);
+	
+	odm_clear_txpowertracking_state(dm);
+}
+
+void phydm_rf_watchdog(void		*dm_void)
+{
+	struct dm_struct		*dm = (struct dm_struct *)dm_void;
+
+	odm_txpowertracking_check(dm);
+}
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/halrf/halphyrf_iot.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/halrf/halphyrf_iot.h
--- linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/halrf/halphyrf_iot.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/halrf/halphyrf_iot.h	2020-04-10 16:35:06.819660208 +0300
@@ -0,0 +1,124 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017  Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * The full GNU General Public License is included in this distribution in the
+ * file called LICENSE.
+ *
+ * Contact Information:
+ * wlanfae <wlanfae@realtek.com>
+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
+ * Hsinchu 300, Taiwan.
+ *
+ * Larry Finger <Larry.Finger@lwfinger.net>
+ *
+ *****************************************************************************/
+
+#ifndef __HALPHYRF_H__
+#define __HALPHYRF_H__
+
+#include "halrf/halrf_kfree.h"
+
+#if (RTL8821C_SUPPORT == 1)
+	#include "halrf/rtl8821c/halrf_iqk_8821c.h"
+#endif
+
+#if (RTL8195B_SUPPORT == 1)
+//	#include "halrf/rtl8195b/halrf.h"
+	#include "halrf/rtl8195b/halrf_iqk_8195b.h"
+	#include "halrf/rtl8195b/halrf_txgapk_8195b.h"
+	#include "halrf/rtl8195b/halrf_dpk_8195b.h"
+#endif
+
+#include "halrf/halrf_powertracking_iot.h"
+
+
+enum spur_cal_method {
+	PLL_RESET,
+	AFE_PHASE_SEL
+};
+
+enum pwrtrack_method {
+	BBSWING,
+	TXAGC,
+	MIX_MODE,
+	TSSI_MODE,
+	MIX_2G_TSSI_5G_MODE,
+	MIX_5G_TSSI_2G_MODE
+};
+
+typedef void	(*func_set_pwr)(void *, enum pwrtrack_method, u8, u8);
+typedef void(*func_iqk)(void *, u8, u8, u8);
+typedef void	(*func_lck)(void *);
+typedef void	(*func_swing)(void *, u8 **, u8 **, u8 **, u8 **);
+typedef void	(*func_swing8814only)(void *, u8 **, u8 **, u8 **, u8 **);
+typedef void(*func_swing_xtal)(void *, s8 **, s8 **);
+typedef void(*func_set_xtal)(void *);
+
+struct txpwrtrack_cfg {
+	u8		swing_table_size_cck;
+	u8		swing_table_size_ofdm;
+	u8		threshold_iqk;
+	u8		threshold_dpk;
+	u8		average_thermal_num;
+	u8		rf_path_count;
+	u32		thermal_reg_addr;
+	func_set_pwr	odm_tx_pwr_track_set_pwr;
+	func_iqk	do_iqk;
+	func_lck		phy_lc_calibrate;
+	func_swing	get_delta_swing_table;
+	func_swing8814only	get_delta_swing_table8814only;
+	func_swing_xtal			get_delta_swing_xtal_table;
+	func_set_xtal			odm_txxtaltrack_set_xtal;
+};
+
+void
+configure_txpower_track(
+	void					*dm_void,
+	struct txpwrtrack_cfg	*config
+);
+
+
+void
+odm_clear_txpowertracking_state(
+	void					*dm_void
+);
+
+void
+odm_txpowertracking_callback_thermal_meter(
+#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
+	void					*dm_void
+#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
+	void	*dm
+#else
+	void	*adapter
+#endif
+);
+
+
+
+#define ODM_TARGET_CHNL_NUM_2G_5G	59
+
+
+void
+odm_reset_iqk_result(
+	void					*dm_void
+);
+u8
+odm_get_right_chnl_place_for_iqk(
+	u8 chnl
+);
+
+void phydm_rf_init(void					*dm_void);
+void phydm_rf_watchdog(void					*dm_void);
+
+#endif	/*#ifndef __HALPHYRF_H__*/
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/halrf/halphyrf_win.c linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/halrf/halphyrf_win.c
--- linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/halrf/halphyrf_win.c	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/halrf/halphyrf_win.c	2020-04-10 16:35:06.819660208 +0300
@@ -0,0 +1,836 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+
+#include "mp_precomp.h"
+#include "phydm_precomp.h"
+
+#define	CALCULATE_SWINGTALBE_OFFSET(_offset, _direction, _size, _delta_thermal) \
+	do {\
+		for (_offset = 0; _offset < _size; _offset++) { \
+			\
+			if (_delta_thermal < thermal_threshold[_direction][_offset]) { \
+				\
+				if (_offset != 0)\
+					_offset--;\
+				break;\
+			} \
+		}			\
+		if (_offset >= _size)\
+			_offset = _size-1;\
+	} while (0)
+
+void configure_txpower_track(
+	struct dm_struct		*dm,
+	struct txpwrtrack_cfg	*config
+)
+{
+#if RTL8192E_SUPPORT
+	if (dm->support_ic_type == ODM_RTL8192E)
+		configure_txpower_track_8192e(config);
+#endif
+#if RTL8821A_SUPPORT
+	if (dm->support_ic_type == ODM_RTL8821)
+		configure_txpower_track_8821a(config);
+#endif
+#if RTL8812A_SUPPORT
+	if (dm->support_ic_type == ODM_RTL8812)
+		configure_txpower_track_8812a(config);
+#endif
+#if RTL8188E_SUPPORT
+	if (dm->support_ic_type == ODM_RTL8188E)
+		configure_txpower_track_8188e(config);
+#endif
+
+#if RTL8188F_SUPPORT
+	if (dm->support_ic_type == ODM_RTL8188F)
+		configure_txpower_track_8188f(config);
+#endif
+
+#if RTL8723B_SUPPORT
+	if (dm->support_ic_type == ODM_RTL8723B)
+		configure_txpower_track_8723b(config);
+#endif
+
+#if RTL8814A_SUPPORT
+	if (dm->support_ic_type == ODM_RTL8814A)
+		configure_txpower_track_8814a(config);
+#endif
+
+#if RTL8703B_SUPPORT
+	if (dm->support_ic_type == ODM_RTL8703B)
+		configure_txpower_track_8703b(config);
+#endif
+
+#if RTL8822B_SUPPORT
+	if (dm->support_ic_type == ODM_RTL8822B)
+		configure_txpower_track_8822b(config);
+#endif
+
+#if RTL8723D_SUPPORT
+	if (dm->support_ic_type == ODM_RTL8723D)
+		configure_txpower_track_8723d(config);
+#endif
+
+/* JJ ADD 20161014 */
+#if RTL8710B_SUPPORT
+	if (dm->support_ic_type == ODM_RTL8710B)
+		configure_txpower_track_8710b(config);
+#endif
+
+#if RTL8821C_SUPPORT
+	if (dm->support_ic_type == ODM_RTL8821C)
+		configure_txpower_track_8821c(config);
+#endif
+
+#if RTL8192F_SUPPORT
+	if (dm->support_ic_type == ODM_RTL8192F)
+		configure_txpower_track_8192f(config);
+#endif
+
+}
+
+/* **********************************************************************
+ * <20121113, Kordan> This function should be called when tx_agc changed.
+ * Otherwise the previous compensation is gone, because we record the
+ * delta of temperature between two TxPowerTracking watch dogs.
+ *
+ * NOTE: If Tx BB swing or Tx scaling is varified during run-time, still
+ * need to call this function.
+ * ********************************************************************** */
+void
+odm_clear_txpowertracking_state(
+	struct dm_struct		*dm
+)
+{
+	PHAL_DATA_TYPE	hal_data = GET_HAL_DATA((PADAPTER)(dm->adapter));
+	u8			p = 0;
+	struct dm_rf_calibration_struct	*cali_info = &(dm->rf_calibrate_info);
+
+	cali_info->bb_swing_idx_cck_base = cali_info->default_cck_index;
+	cali_info->bb_swing_idx_cck = cali_info->default_cck_index;
+	cali_info->CCK_index = 0;
+
+	for (p = RF_PATH_A; p < MAX_RF_PATH; ++p) {
+		cali_info->bb_swing_idx_ofdm_base[p] = cali_info->default_ofdm_index;
+		cali_info->bb_swing_idx_ofdm[p] = cali_info->default_ofdm_index;
+		cali_info->OFDM_index[p] = cali_info->default_ofdm_index;
+
+		cali_info->power_index_offset[p] = 0;
+		cali_info->delta_power_index[p] = 0;
+		cali_info->delta_power_index_last[p] = 0;
+
+		cali_info->absolute_ofdm_swing_idx[p] = 0;    /* Initial Mix mode power tracking*/
+		cali_info->remnant_ofdm_swing_idx[p] = 0;
+		cali_info->kfree_offset[p] = 0;
+	}
+
+	cali_info->modify_tx_agc_flag_path_a = false;       /*Initial at Modify Tx Scaling mode*/
+	cali_info->modify_tx_agc_flag_path_b = false;       /*Initial at Modify Tx Scaling mode*/
+	cali_info->modify_tx_agc_flag_path_c = false;       /*Initial at Modify Tx Scaling mode*/
+	cali_info->modify_tx_agc_flag_path_d = false;       /*Initial at Modify Tx Scaling mode*/
+	cali_info->remnant_cck_swing_idx = 0;
+	cali_info->thermal_value = hal_data->eeprom_thermal_meter;
+
+	cali_info->modify_tx_agc_value_cck = 0;			/* modify by Mingzhi.Guo */
+	cali_info->modify_tx_agc_value_ofdm = 0;		/* modify by Mingzhi.Guo */
+
+}
+
+void
+odm_txpowertracking_callback_thermal_meter(
+#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
+	struct dm_struct		*dm
+#else
+	void	*adapter
+#endif
+)
+{
+#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
+	HAL_DATA_TYPE	*hal_data = GET_HAL_DATA(((PADAPTER)adapter));
+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
+	struct dm_struct		*dm = &hal_data->DM_OutSrc;
+#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
+	struct dm_struct		*dm = &hal_data->odmpriv;
+#endif
+#endif
+
+	struct dm_rf_calibration_struct	*cali_info = &(dm->rf_calibrate_info);
+ 	struct dm_iqk_info	*iqk_info = &dm->IQK_info;
+	u8			thermal_value = 0, delta, delta_LCK, delta_IQK, p = 0, i = 0;
+	s8			diff_DPK[4] = {0};
+	u8			thermal_value_avg_count = 0;
+	u32			thermal_value_avg = 0, regc80, regcd0, regcd4, regab4, regc88, rege14, reg848,reg838, reg86c;
+
+	u8			OFDM_min_index = 0;  /* OFDM BB Swing should be less than +3.0dB, which is required by Arthur */
+	u8			indexforchannel = 0; /* get_right_chnl_place_for_iqk(hal_data->current_channel) */
+	u8			power_tracking_type = hal_data->RfPowerTrackingType;
+	u8			xtal_offset_eanble = 0;
+	s8			thermal_value_temp = 0;
+
+	struct txpwrtrack_cfg	c;
+
+	/* 4 1. The following TWO tables decide the final index of OFDM/CCK swing table. */
+	u8			*delta_swing_table_idx_tup_a = NULL;
+	u8			*delta_swing_table_idx_tdown_a = NULL;
+	u8			*delta_swing_table_idx_tup_b = NULL;
+	u8			*delta_swing_table_idx_tdown_b = NULL;
+	/*for 8814 add by Yu Chen*/
+	u8			*delta_swing_table_idx_tup_c = NULL;
+	u8			*delta_swing_table_idx_tdown_c = NULL;
+	u8			*delta_swing_table_idx_tup_d = NULL;
+	u8			*delta_swing_table_idx_tdown_d = NULL;
+	/*for Xtal Offset by James.Tung*/
+	s8			*delta_swing_table_xtal_up = NULL;
+	s8			*delta_swing_table_xtal_down = NULL;
+
+	/* 4 2. Initilization ( 7 steps in total ) */
+
+	configure_txpower_track(dm, &c);
+
+	(*c.get_delta_swing_table)(dm, (u8 **)&delta_swing_table_idx_tup_a, (u8 **)&delta_swing_table_idx_tdown_a,
+		(u8 **)&delta_swing_table_idx_tup_b, (u8 **)&delta_swing_table_idx_tdown_b);
+
+	if (dm->support_ic_type & ODM_RTL8814A)	/*for 8814 path C & D*/
+		(*c.get_delta_swing_table8814only)(dm, (u8 **)&delta_swing_table_idx_tup_c, (u8 **)&delta_swing_table_idx_tdown_c,
+			(u8 **)&delta_swing_table_idx_tup_d, (u8 **)&delta_swing_table_idx_tdown_d);
+	/* JJ ADD 20161014 */
+	if (dm->support_ic_type & (ODM_RTL8703B | ODM_RTL8723D | ODM_RTL8710B | ODM_RTL8192F))	/*for Xtal Offset*/
+		(*c.get_delta_swing_xtal_table)(dm, (s8 **)&delta_swing_table_xtal_up, (s8 **)&delta_swing_table_xtal_down);
+
+
+	cali_info->txpowertracking_callback_cnt++;	/*cosa add for debug*/
+	cali_info->is_txpowertracking_init = true;
+
+	/*cali_info->txpowertrack_control = hal_data->txpowertrack_control;
+	<Kordan> We should keep updating the control variable according to HalData.
+	<Kordan> rf_calibrate_info.rega24 will be initialized when ODM HW configuring, but MP configures with para files. */
+#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
+#if (MP_DRIVER == 1)
+	cali_info->rega24 = 0x090e1317;
+#endif
+#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
+	if (*(dm->mp_mode) == true)
+		cali_info->rega24 = 0x090e1317;
+#endif
+
+	RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
+		"===>odm_txpowertracking_callback_thermal_meter\n cali_info->bb_swing_idx_cck_base: %d, cali_info->bb_swing_idx_ofdm_base[A]: %d, cali_info->default_ofdm_index: %d\n",
+		cali_info->bb_swing_idx_cck_base, cali_info->bb_swing_idx_ofdm_base[RF_PATH_A], cali_info->default_ofdm_index);
+
+	RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
+		"cali_info->txpowertrack_control=%d,  hal_data->eeprom_thermal_meter %d\n", cali_info->txpowertrack_control,  hal_data->eeprom_thermal_meter);
+	thermal_value = (u8)odm_get_rf_reg(dm, RF_PATH_A, c.thermal_reg_addr, 0xfc00);	/* 0x42: RF Reg[15:10] 88E */
+
+	thermal_value_temp = thermal_value + phydm_get_thermal_offset(dm);
+
+	RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
+		"thermal_value_temp(%d) = thermal_value(%d) + power_time_thermal(%d)\n", thermal_value_temp, thermal_value, phydm_get_thermal_offset(dm));
+
+	if (thermal_value_temp > 63)
+		thermal_value = 63;
+	else if (thermal_value_temp < 0)
+		thermal_value = 0;
+	else
+		thermal_value = thermal_value_temp;
+
+	/*add log by zhao he, check c80/c94/c14/ca0 value*/
+	if (dm->support_ic_type == ODM_RTL8723D) {
+		regc80 = odm_get_bb_reg(dm, R_0xc80, MASKDWORD);
+		regcd0 = odm_get_bb_reg(dm, R_0xcd0, MASKDWORD);
+		regcd4 = odm_get_bb_reg(dm, R_0xcd4, MASKDWORD);
+		regab4 = odm_get_bb_reg(dm, R_0xab4, 0x000007FF);
+		RF_DBG(dm, DBG_RF_IQK, "0xc80 = 0x%x 0xcd0 = 0x%x 0xcd4 = 0x%x 0xab4 = 0x%x\n", regc80, regcd0, regcd4, regab4);
+	}
+
+	/* JJ ADD 20161014 */
+	if (dm->support_ic_type == ODM_RTL8710B) {
+		regc80 = odm_get_bb_reg(dm, R_0xc80, MASKDWORD);
+		regcd0 = odm_get_bb_reg(dm, R_0xcd0, MASKDWORD);
+		regcd4 = odm_get_bb_reg(dm, R_0xcd4, MASKDWORD);
+		regab4 = odm_get_bb_reg(dm, R_0xab4, 0x000007FF);
+		RF_DBG(dm, DBG_RF_IQK, "0xc80 = 0x%x 0xcd0 = 0x%x 0xcd4 = 0x%x 0xab4 = 0x%x\n", regc80, regcd0, regcd4, regab4);
+	}
+	/* Winnita add 20171205 */
+	if (dm->support_ic_type == ODM_RTL8192F) {
+		regc80 = odm_get_bb_reg(dm, R_0xc80, MASKDWORD);
+		regc88 = odm_get_bb_reg(dm, R_0xc88, MASKDWORD);
+		regab4 = odm_get_bb_reg(dm, R_0xab4, MASKDWORD);
+		rege14 = odm_get_bb_reg(dm, R_0xe14, MASKDWORD);
+		reg848 = odm_get_bb_reg(dm, R_0x848, MASKDWORD);
+		reg838 = odm_get_bb_reg(dm, R_0x838, MASKDWORD);
+		reg86c = odm_get_bb_reg(dm, R_0x86c, MASKDWORD);
+		RF_DBG(dm, DBG_RF_IQK, "0xc80 = 0x%x 0xc88 = 0x%x 0xab4 = 0x%x 0xe14 = 0x%x\n", regc80, regc88, regab4, rege14);
+		RF_DBG(dm, DBG_RF_IQK, "0x848 = 0x%x 0x838 = 0x%x 0x86c = 0x%x\n", reg848, reg838, reg86c);
+	}
+
+	if (!cali_info->txpowertrack_control)
+		return;
+
+	if (hal_data->eeprom_thermal_meter == 0xff) {
+		RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "no pg, hal_data->eeprom_thermal_meter = 0x%x\n", hal_data->eeprom_thermal_meter);
+		return;
+	}
+
+	/*4 3. Initialize ThermalValues of rf_calibrate_info*/
+
+	if (cali_info->is_reloadtxpowerindex)
+		RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "reload ofdm index for band switch\n");
+
+	/*4 4. Calculate average thermal meter*/
+
+	cali_info->thermal_value_avg[cali_info->thermal_value_avg_index] = thermal_value;
+	cali_info->thermal_value_avg_index++;
+	if (cali_info->thermal_value_avg_index == c.average_thermal_num)   /*Average times =  c.average_thermal_num*/
+		cali_info->thermal_value_avg_index = 0;
+
+	for (i = 0; i < c.average_thermal_num; i++) {
+		if (cali_info->thermal_value_avg[i]) {
+			thermal_value_avg += cali_info->thermal_value_avg[i];
+			thermal_value_avg_count++;
+		}
+	}
+
+	if (thermal_value_avg_count) {            /* Calculate Average thermal_value after average enough times */
+		thermal_value = (u8)(thermal_value_avg / thermal_value_avg_count);
+		cali_info->thermal_value_delta = thermal_value - hal_data->eeprom_thermal_meter;
+		RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
+			"AVG Thermal Meter = 0x%X, EFUSE Thermal base = 0x%X\n", thermal_value, hal_data->eeprom_thermal_meter);
+	}
+
+	/* 4 5. Calculate delta, delta_LCK, delta_IQK. */
+
+	/* "delta" here is used to determine whether thermal value changes or not. */
+	delta	= (thermal_value > cali_info->thermal_value) ? (thermal_value - cali_info->thermal_value) : (cali_info->thermal_value - thermal_value);
+	delta_LCK = (thermal_value > cali_info->thermal_value_lck) ? (thermal_value - cali_info->thermal_value_lck) : (cali_info->thermal_value_lck - thermal_value);
+	delta_IQK = (thermal_value > cali_info->thermal_value_iqk) ? (thermal_value - cali_info->thermal_value_iqk) : (cali_info->thermal_value_iqk - thermal_value);
+
+	if (cali_info->thermal_value_iqk == 0xff) {	/*no PG, use thermal value for IQK*/
+		cali_info->thermal_value_iqk = thermal_value;
+		delta_IQK = (thermal_value > cali_info->thermal_value_iqk) ? (thermal_value - cali_info->thermal_value_iqk) : (cali_info->thermal_value_iqk - thermal_value);
+		RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "no PG, use thermal_value for IQK\n");
+	}
+
+	for (p = RF_PATH_A; p < c.rf_path_count; p++)
+		diff_DPK[p] = (s8)thermal_value - (s8)cali_info->dpk_thermal[p];
+
+	/*4 6. If necessary, do LCK.*/
+
+	if (!(dm->support_ic_type & ODM_RTL8821)) {	/*no PG, do LCK at initial status*/
+		if (cali_info->thermal_value_lck == 0xff) {
+			RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "no PG, do LCK\n");
+			cali_info->thermal_value_lck = thermal_value;
+
+			/*Use RTLCK, so close power tracking driver LCK*/
+			if ((!(dm->support_ic_type & ODM_RTL8814A)) && (!(dm->support_ic_type & ODM_RTL8822B))) {
+				if (c.phy_lc_calibrate)
+					(*c.phy_lc_calibrate)(dm);
+			}
+
+			delta_LCK = (thermal_value > cali_info->thermal_value_lck) ? (thermal_value - cali_info->thermal_value_lck) : (cali_info->thermal_value_lck - thermal_value);
+		}
+
+		RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "(delta, delta_LCK, delta_IQK) = (%d, %d, %d)\n", delta, delta_LCK, delta_IQK);
+
+		/* Wait sacn to do LCK by RF Jenyu*/
+		if( (*dm->is_scan_in_process == false) && (!iqk_info->rfk_forbidden)) {
+			/* Delta temperature is equal to or larger than 20 centigrade.*/
+			if (delta_LCK >= c.threshold_iqk) {
+				RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "delta_LCK(%d) >= threshold_iqk(%d)\n", delta_LCK, c.threshold_iqk);
+				cali_info->thermal_value_lck = thermal_value;
+
+				/*Use RTLCK, so close power tracking driver LCK*/
+				if ((!(dm->support_ic_type & ODM_RTL8814A)) && (!(dm->support_ic_type & ODM_RTL8822B))) {
+					if (c.phy_lc_calibrate)
+						(*c.phy_lc_calibrate)(dm);
+				}
+			}
+		}
+	}
+
+	/*3 7. If necessary, move the index of swing table to adjust Tx power.*/
+
+	if (delta > 0 && cali_info->txpowertrack_control) {
+		/* "delta" here is used to record the absolute value of differrence. */
+#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
+		delta = thermal_value > hal_data->eeprom_thermal_meter ? (thermal_value - hal_data->eeprom_thermal_meter) : (hal_data->eeprom_thermal_meter - thermal_value);
+#else
+		delta = (thermal_value > dm->priv->pmib->dot11RFEntry.ther) ? (thermal_value - dm->priv->pmib->dot11RFEntry.ther) : (dm->priv->pmib->dot11RFEntry.ther - thermal_value);
+#endif
+		if (delta >= TXPWR_TRACK_TABLE_SIZE)
+			delta = TXPWR_TRACK_TABLE_SIZE - 1;
+
+		/*4 7.1 The Final Power index = BaseIndex + power_index_offset*/
+
+#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
+		if (thermal_value > hal_data->eeprom_thermal_meter) {
+#else
+		if (thermal_value > dm->priv->pmib->dot11RFEntry.ther) {
+#endif
+
+			for (p = RF_PATH_A; p < c.rf_path_count; p++) {
+				cali_info->delta_power_index_last[p] = cali_info->delta_power_index[p];	/*recording poer index offset*/
+				switch (p) {
+				case RF_PATH_B:
+					RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
+						"delta_swing_table_idx_tup_b[%d] = %d\n", delta, delta_swing_table_idx_tup_b[delta]);
+
+					cali_info->delta_power_index[p] = delta_swing_table_idx_tup_b[delta];
+					cali_info->absolute_ofdm_swing_idx[p] =  delta_swing_table_idx_tup_b[delta];       /*Record delta swing for mix mode power tracking*/
+					RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
+						"******Temp is higher and cali_info->absolute_ofdm_swing_idx[RF_PATH_B] = %d\n", cali_info->absolute_ofdm_swing_idx[p]);
+					break;
+
+				case RF_PATH_C:
+					RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
+						"delta_swing_table_idx_tup_c[%d] = %d\n", delta, delta_swing_table_idx_tup_c[delta]);
+
+					cali_info->delta_power_index[p] = delta_swing_table_idx_tup_c[delta];
+					cali_info->absolute_ofdm_swing_idx[p] =  delta_swing_table_idx_tup_c[delta];       /*Record delta swing for mix mode power tracking*/
+					RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
+						"******Temp is higher and cali_info->absolute_ofdm_swing_idx[RF_PATH_C] = %d\n", cali_info->absolute_ofdm_swing_idx[p]);
+					break;
+
+				case RF_PATH_D:
+					RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
+						"delta_swing_table_idx_tup_d[%d] = %d\n", delta, delta_swing_table_idx_tup_d[delta]);
+
+					cali_info->delta_power_index[p] = delta_swing_table_idx_tup_d[delta];
+					cali_info->absolute_ofdm_swing_idx[p] =  delta_swing_table_idx_tup_d[delta];       /*Record delta swing for mix mode power tracking*/
+					RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
+						"******Temp is higher and cali_info->absolute_ofdm_swing_idx[RF_PATH_D] = %d\n", cali_info->absolute_ofdm_swing_idx[p]);
+					break;
+
+				default:
+					RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
+						"delta_swing_table_idx_tup_a[%d] = %d\n", delta, delta_swing_table_idx_tup_a[delta]);
+
+					cali_info->delta_power_index[p] = delta_swing_table_idx_tup_a[delta];
+					cali_info->absolute_ofdm_swing_idx[p] =  delta_swing_table_idx_tup_a[delta];        /*Record delta swing for mix mode power tracking*/
+					RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
+						"******Temp is higher and cali_info->absolute_ofdm_swing_idx[RF_PATH_A] = %d\n", cali_info->absolute_ofdm_swing_idx[p]);
+					break;
+				}
+			}
+			/* JJ ADD 20161014 */
+			if (dm->support_ic_type & (ODM_RTL8703B | ODM_RTL8723D | ODM_RTL8710B | ODM_RTL8192F)) {
+				/*Save xtal_offset from Xtal table*/
+				cali_info->xtal_offset_last = cali_info->xtal_offset;	/*recording last Xtal offset*/
+				RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
+					"[Xtal] delta_swing_table_xtal_up[%d] = %d\n", delta, delta_swing_table_xtal_up[delta]);
+				cali_info->xtal_offset = delta_swing_table_xtal_up[delta];
+
+				if (cali_info->xtal_offset_last == cali_info->xtal_offset)
+					xtal_offset_eanble = 0;
+				else
+					xtal_offset_eanble = 1;
+			}
+
+		} else {
+			for (p = RF_PATH_A; p < c.rf_path_count; p++) {
+				cali_info->delta_power_index_last[p] = cali_info->delta_power_index[p];	/*recording poer index offset*/
+
+				switch (p) {
+				case RF_PATH_B:
+					RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
+						"delta_swing_table_idx_tdown_b[%d] = %d\n", delta, delta_swing_table_idx_tdown_b[delta]);
+					cali_info->delta_power_index[p] = -1 * delta_swing_table_idx_tdown_b[delta];
+					cali_info->absolute_ofdm_swing_idx[p] =  -1 * delta_swing_table_idx_tdown_b[delta];        /*Record delta swing for mix mode power tracking*/
+					RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
+						"******Temp is lower and cali_info->absolute_ofdm_swing_idx[RF_PATH_B] = %d\n", cali_info->absolute_ofdm_swing_idx[p]);
+					break;
+
+				case RF_PATH_C:
+					RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
+						"delta_swing_table_idx_tdown_c[%d] = %d\n", delta, delta_swing_table_idx_tdown_c[delta]);
+					cali_info->delta_power_index[p] = -1 * delta_swing_table_idx_tdown_c[delta];
+					cali_info->absolute_ofdm_swing_idx[p] =  -1 * delta_swing_table_idx_tdown_c[delta];        /*Record delta swing for mix mode power tracking*/
+					RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
+						"******Temp is lower and cali_info->absolute_ofdm_swing_idx[RF_PATH_C] = %d\n", cali_info->absolute_ofdm_swing_idx[p]);
+					break;
+
+				case RF_PATH_D:
+					RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
+						"delta_swing_table_idx_tdown_d[%d] = %d\n", delta, delta_swing_table_idx_tdown_d[delta]);
+					cali_info->delta_power_index[p] = -1 * delta_swing_table_idx_tdown_d[delta];
+					cali_info->absolute_ofdm_swing_idx[p] =  -1 * delta_swing_table_idx_tdown_d[delta];        /*Record delta swing for mix mode power tracking*/
+					RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
+						"******Temp is lower and cali_info->absolute_ofdm_swing_idx[RF_PATH_D] = %d\n", cali_info->absolute_ofdm_swing_idx[p]);
+					break;
+
+				default:
+					RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
+						"delta_swing_table_idx_tdown_a[%d] = %d\n", delta, delta_swing_table_idx_tdown_a[delta]);
+					cali_info->delta_power_index[p] = -1 * delta_swing_table_idx_tdown_a[delta];
+					cali_info->absolute_ofdm_swing_idx[p] =  -1 * delta_swing_table_idx_tdown_a[delta];        /*Record delta swing for mix mode power tracking*/
+					RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
+						"******Temp is lower and cali_info->absolute_ofdm_swing_idx[RF_PATH_A] = %d\n", cali_info->absolute_ofdm_swing_idx[p]);
+					break;
+				}
+			}
+			/* JJ ADD 20161014 */
+			if (dm->support_ic_type & (ODM_RTL8703B | ODM_RTL8723D | ODM_RTL8710B | ODM_RTL8192F)) {
+				/*Save xtal_offset from Xtal table*/
+				cali_info->xtal_offset_last = cali_info->xtal_offset;	/*recording last Xtal offset*/
+				RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
+					"[Xtal] delta_swing_table_xtal_down[%d] = %d\n", delta, delta_swing_table_xtal_down[delta]);
+				cali_info->xtal_offset = delta_swing_table_xtal_down[delta];
+
+				if (cali_info->xtal_offset_last == cali_info->xtal_offset)
+					xtal_offset_eanble = 0;
+				else
+					xtal_offset_eanble = 1;
+			}
+
+		}
+
+		for (p = RF_PATH_A; p < c.rf_path_count; p++) {
+			RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
+				"\n\n=========================== [path-%d] Calculating power_index_offset===========================\n", p);
+
+			if (cali_info->delta_power_index[p] == cali_info->delta_power_index_last[p])         /*If Thermal value changes but lookup table value still the same*/
+				cali_info->power_index_offset[p] = 0;
+			else
+				cali_info->power_index_offset[p] = cali_info->delta_power_index[p] - cali_info->delta_power_index_last[p];      /*Power index diff between 2 times Power Tracking*/
+
+			RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
+				"[path-%d] power_index_offset(%d) = delta_power_index(%d) - delta_power_index_last(%d)\n", p, cali_info->power_index_offset[p], cali_info->delta_power_index[p], cali_info->delta_power_index_last[p]);
+
+			cali_info->OFDM_index[p] = cali_info->bb_swing_idx_ofdm_base[p] + cali_info->power_index_offset[p];
+			cali_info->CCK_index = cali_info->bb_swing_idx_cck_base + cali_info->power_index_offset[p];
+
+			cali_info->bb_swing_idx_cck = cali_info->CCK_index;
+			cali_info->bb_swing_idx_ofdm[p] = cali_info->OFDM_index[p];
+
+			/*************Print BB Swing base and index Offset*************/
+
+			RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
+				"The 'CCK' final index(%d) = BaseIndex(%d) + power_index_offset(%d)\n", cali_info->bb_swing_idx_cck, cali_info->bb_swing_idx_cck_base, cali_info->power_index_offset[p]);
+			RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
+				"The 'OFDM' final index(%d) = BaseIndex[%d](%d) + power_index_offset(%d)\n", cali_info->bb_swing_idx_ofdm[p], p, cali_info->bb_swing_idx_ofdm_base[p], cali_info->power_index_offset[p]);
+
+			/*4 7.1 Handle boundary conditions of index.*/
+
+			if (cali_info->OFDM_index[p] > c.swing_table_size_ofdm - 1)
+				cali_info->OFDM_index[p] = c.swing_table_size_ofdm - 1;
+			else if (cali_info->OFDM_index[p] <= OFDM_min_index)
+				cali_info->OFDM_index[p] = OFDM_min_index;
+		}
+
+		RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
+			"\n\n========================================================================================================\n");
+
+		if (cali_info->CCK_index > c.swing_table_size_cck - 1)
+			cali_info->CCK_index = c.swing_table_size_cck - 1;
+		else if (cali_info->CCK_index <= 0)
+			cali_info->CCK_index = 0;
+	} else {
+		RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
+			"The thermal meter is unchanged or TxPowerTracking OFF(%d): thermal_value: %d, cali_info->thermal_value: %d\n",
+			cali_info->txpowertrack_control, thermal_value, cali_info->thermal_value);
+
+		for (p = RF_PATH_A; p < c.rf_path_count; p++)
+			cali_info->power_index_offset[p] = 0;
+	}
+
+	RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
+		"TxPowerTracking: [CCK] Swing Current index: %d, Swing base index: %d\n",
+		cali_info->CCK_index, cali_info->bb_swing_idx_cck_base);       /*Print Swing base & current*/
+
+	for (p = RF_PATH_A; p < c.rf_path_count; p++) {
+		RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
+			"TxPowerTracking: [OFDM] Swing Current index: %d, Swing base index[%d]: %d\n",
+			cali_info->OFDM_index[p], p, cali_info->bb_swing_idx_ofdm_base[p]);
+	}
+
+	if ((dm->support_ic_type & ODM_RTL8814A)) {
+		RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "power_tracking_type=%d\n", power_tracking_type);
+
+		if (power_tracking_type == 0) {
+			RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "**********Enter POWER Tracking MIX_MODE**********\n");
+			for (p = RF_PATH_A; p < c.rf_path_count; p++)
+				(*c.odm_tx_pwr_track_set_pwr)(dm, MIX_MODE, p, 0);
+		} else if (power_tracking_type == 1) {
+			RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "**********Enter POWER Tracking MIX(2G) TSSI(5G) MODE**********\n");
+			for (p = RF_PATH_A; p < c.rf_path_count; p++)
+				(*c.odm_tx_pwr_track_set_pwr)(dm, MIX_2G_TSSI_5G_MODE, p, 0);
+		} else if (power_tracking_type == 2) {
+			RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "**********Enter POWER Tracking MIX(5G) TSSI(2G)MODE**********\n");
+			for (p = RF_PATH_A; p < c.rf_path_count; p++)
+				(*c.odm_tx_pwr_track_set_pwr)(dm, MIX_5G_TSSI_2G_MODE, p, 0);
+		} else if (power_tracking_type == 3) {
+			RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "**********Enter POWER Tracking TSSI MODE**********\n");
+			for (p = RF_PATH_A; p < c.rf_path_count; p++)
+				(*c.odm_tx_pwr_track_set_pwr)(dm, TSSI_MODE, p, 0);
+		}
+		cali_info->thermal_value = thermal_value;         /*Record last Power Tracking Thermal value*/
+
+	} else if ((cali_info->power_index_offset[RF_PATH_A] != 0 ||
+		cali_info->power_index_offset[RF_PATH_B] != 0 ||
+		cali_info->power_index_offset[RF_PATH_C] != 0 ||
+		cali_info->power_index_offset[RF_PATH_D] != 0) &&
+		cali_info->txpowertrack_control && (hal_data->eeprom_thermal_meter != 0xff)) {
+		/* 4 7.2 Configure the Swing Table to adjust Tx Power. */
+
+		cali_info->is_tx_power_changed = true;	/*Always true after Tx Power is adjusted by power tracking.*/
+		/*  */
+		/* 2012/04/23 MH According to Luke's suggestion, we can not write BB digital */
+		/* to increase TX power. Otherwise, EVM will be bad. */
+		/*  */
+		/* 2012/04/25 MH Add for tx power tracking to set tx power in tx agc for 88E. */
+		if (thermal_value > cali_info->thermal_value) {
+			for (p = RF_PATH_A; p < c.rf_path_count; p++) {
+				RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
+					"Temperature Increasing(%d): delta_pi: %d, delta_t: %d, Now_t: %d, EFUSE_t: %d, Last_t: %d\n",
+					p, cali_info->power_index_offset[p], delta, thermal_value, hal_data->eeprom_thermal_meter, cali_info->thermal_value);
+			}
+		} else if (thermal_value < cali_info->thermal_value) {	/*Low temperature*/
+			for (p = RF_PATH_A; p < c.rf_path_count; p++) {
+				RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
+					"Temperature Decreasing(%d): delta_pi: %d, delta_t: %d, Now_t: %d, EFUSE_t: %d, Last_t: %d\n",
+					p, cali_info->power_index_offset[p], delta, thermal_value, hal_data->eeprom_thermal_meter, cali_info->thermal_value);
+			}
+		}
+
+#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
+		if (thermal_value > hal_data->eeprom_thermal_meter)
+#else
+		if (thermal_value > dm->priv->pmib->dot11RFEntry.ther)
+#endif
+		{
+			RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
+				"Temperature(%d) higher than PG value(%d)\n", thermal_value, hal_data->eeprom_thermal_meter);
+
+			if (dm->support_ic_type == ODM_RTL8188E || dm->support_ic_type == ODM_RTL8192E || dm->support_ic_type == ODM_RTL8821 ||
+			    dm->support_ic_type == ODM_RTL8812 || dm->support_ic_type == ODM_RTL8723B || dm->support_ic_type == ODM_RTL8814A ||
+			    dm->support_ic_type == ODM_RTL8703B || dm->support_ic_type == ODM_RTL8188F || dm->support_ic_type == ODM_RTL8822B ||
+			    dm->support_ic_type == ODM_RTL8723D || dm->support_ic_type == ODM_RTL8821C || dm->support_ic_type == ODM_RTL8710B ||
+			    dm->support_ic_type == ODM_RTL8192F) {
+
+				RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "**********Enter POWER Tracking MIX_MODE**********\n");
+				for (p = RF_PATH_A; p < c.rf_path_count; p++)
+					(*c.odm_tx_pwr_track_set_pwr)(dm, MIX_MODE, p, 0);
+			} else {
+				RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "**********Enter POWER Tracking BBSWING_MODE**********\n");
+				for (p = RF_PATH_A; p < c.rf_path_count; p++)
+					(*c.odm_tx_pwr_track_set_pwr)(dm, BBSWING, p, indexforchannel);
+			}
+		} else {
+			RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
+				"Temperature(%d) lower than PG value(%d)\n", thermal_value, hal_data->eeprom_thermal_meter);
+
+			if (dm->support_ic_type == ODM_RTL8188E || dm->support_ic_type == ODM_RTL8192E || dm->support_ic_type == ODM_RTL8821 ||
+			    dm->support_ic_type == ODM_RTL8812 || dm->support_ic_type == ODM_RTL8723B || dm->support_ic_type == ODM_RTL8814A ||
+			    dm->support_ic_type == ODM_RTL8703B || dm->support_ic_type == ODM_RTL8188F || dm->support_ic_type == ODM_RTL8822B ||
+			    dm->support_ic_type == ODM_RTL8723D || dm->support_ic_type == ODM_RTL8821C || dm->support_ic_type == ODM_RTL8710B ||
+				dm->support_ic_type == ODM_RTL8192F) {
+				RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "**********Enter POWER Tracking MIX_MODE**********\n");
+				for (p = RF_PATH_A; p < c.rf_path_count; p++)
+					(*c.odm_tx_pwr_track_set_pwr)(dm, MIX_MODE, p, indexforchannel);
+			} else {
+				RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "**********Enter POWER Tracking BBSWING_MODE**********\n");
+				for (p = RF_PATH_A; p < c.rf_path_count; p++)
+					(*c.odm_tx_pwr_track_set_pwr)(dm, BBSWING, p, indexforchannel);
+			}
+
+		}
+
+		cali_info->bb_swing_idx_cck_base = cali_info->bb_swing_idx_cck;    /*Record last time Power Tracking result as base.*/
+		for (p = RF_PATH_A; p < c.rf_path_count; p++)
+			cali_info->bb_swing_idx_ofdm_base[p] = cali_info->bb_swing_idx_ofdm[p];
+
+		RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
+			"cali_info->thermal_value = %d thermal_value= %d\n", cali_info->thermal_value, thermal_value);
+
+		cali_info->thermal_value = thermal_value;         /*Record last Power Tracking Thermal value*/
+
+	}
+
+
+	if (dm->support_ic_type == ODM_RTL8703B || dm->support_ic_type == ODM_RTL8723D ||
+		dm->support_ic_type == ODM_RTL8192F || dm->support_ic_type == ODM_RTL8710B) {/* JJ ADD 20161014 */
+
+		if (xtal_offset_eanble != 0 && cali_info->txpowertrack_control && (hal_data->eeprom_thermal_meter != 0xff)) {
+
+			RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "**********Enter Xtal Tracking**********\n");
+
+#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
+			if (thermal_value > hal_data->eeprom_thermal_meter) {
+#else
+			if (thermal_value > dm->priv->pmib->dot11RFEntry.ther) {
+#endif
+				RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
+					"Temperature(%d) higher than PG value(%d)\n", thermal_value, hal_data->eeprom_thermal_meter);
+				(*c.odm_txxtaltrack_set_xtal)(dm);
+			} else {
+				RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
+					"Temperature(%d) lower than PG value(%d)\n", thermal_value, hal_data->eeprom_thermal_meter);
+				(*c.odm_txxtaltrack_set_xtal)(dm);
+			}
+		}
+		RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "**********End Xtal Tracking**********\n");
+	}
+
+#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
+
+	/* Wait sacn to do IQK by RF Jenyu*/
+	if ((*dm->is_scan_in_process == false) && (!iqk_info->rfk_forbidden)) {
+		if (!IS_HARDWARE_TYPE_8723B(adapter)) {
+			/*Delta temperature is equal to or larger than 20 centigrade (When threshold is 8).*/
+			if (delta_IQK >= c.threshold_iqk) {
+				cali_info->thermal_value_iqk = thermal_value;
+				RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "delta_IQK(%d) >= threshold_iqk(%d)\n", delta_IQK, c.threshold_iqk);
+				if (!cali_info->is_iqk_in_progress)
+					(*c.do_iqk)(dm, delta_IQK, thermal_value, 8);
+			}
+		}
+	}
+	if (cali_info->dpk_thermal[RF_PATH_A] != 0) {
+		if (diff_DPK[RF_PATH_A] >= c.threshold_dpk) {
+			odm_set_bb_reg(dm, R_0x82c, BIT(31), 0x1);
+			odm_set_bb_reg(dm, R_0xcc4, BIT(14) | BIT(13) | BIT(12) | BIT(11) | BIT(10), (diff_DPK[RF_PATH_A] / c.threshold_dpk));
+			odm_set_bb_reg(dm, R_0x82c, BIT(31), 0x0);
+		} else if ((diff_DPK[RF_PATH_A] <= -1 * c.threshold_dpk)) {
+			s32 value = 0x20 + (diff_DPK[RF_PATH_A] / c.threshold_dpk);
+
+			odm_set_bb_reg(dm, R_0x82c, BIT(31), 0x1);
+			odm_set_bb_reg(dm, R_0xcc4, BIT(14) | BIT(13) | BIT(12) | BIT(11) | BIT(10), value);
+			odm_set_bb_reg(dm, R_0x82c, BIT(31), 0x0);
+		} else {
+			odm_set_bb_reg(dm, R_0x82c, BIT(31), 0x1);
+			odm_set_bb_reg(dm, R_0xcc4, BIT(14) | BIT(13) | BIT(12) | BIT(11) | BIT(10), 0);
+			odm_set_bb_reg(dm, R_0x82c, BIT(31), 0x0);
+		}
+	}
+	if (cali_info->dpk_thermal[RF_PATH_B] != 0) {
+		if (diff_DPK[RF_PATH_B] >= c.threshold_dpk) {
+			odm_set_bb_reg(dm, R_0x82c, BIT(31), 0x1);
+			odm_set_bb_reg(dm, R_0xec4, BIT(14) | BIT(13) | BIT(12) | BIT(11) | BIT(10), (diff_DPK[RF_PATH_B] / c.threshold_dpk));
+			odm_set_bb_reg(dm, R_0x82c, BIT(31), 0x0);
+		} else if ((diff_DPK[RF_PATH_B] <= -1 * c.threshold_dpk)) {
+			s32 value = 0x20 + (diff_DPK[RF_PATH_B] / c.threshold_dpk);
+
+			odm_set_bb_reg(dm, R_0x82c, BIT(31), 0x1);
+			odm_set_bb_reg(dm, R_0xec4, BIT(14) | BIT(13) | BIT(12) | BIT(11) | BIT(10), value);
+			odm_set_bb_reg(dm, R_0x82c, BIT(31), 0x0);
+		} else {
+			odm_set_bb_reg(dm, R_0x82c, BIT(31), 0x1);
+			odm_set_bb_reg(dm, R_0xec4, BIT(14) | BIT(13) | BIT(12) | BIT(11) | BIT(10), 0);
+			odm_set_bb_reg(dm, R_0x82c, BIT(31), 0x0);
+		}
+	}
+
+#endif
+
+	RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "<===odm_txpowertracking_callback_thermal_meter\n");
+
+	cali_info->tx_powercount = 0;
+}
+
+
+
+/* 3============================================================
+ * 3 IQ Calibration
+ * 3============================================================ */
+
+void
+odm_reset_iqk_result(
+	struct dm_struct	*dm
+)
+{
+	return;
+}
+#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
+u8 odm_get_right_chnl_place_for_iqk(u8 chnl)
+{
+	u8	channel_all[ODM_TARGET_CHNL_NUM_2G_5G] = {
+		1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 36, 38, 40, 42, 44, 46, 48, 50, 52, 54, 56, 58, 60, 62, 64, 100, 102, 104, 106, 108, 110, 112, 114, 116, 118, 120, 122, 124, 126, 128, 130, 132, 134, 136, 138, 140, 149, 151, 153, 155, 157, 159, 161, 163, 165
+	};
+	u8	place = chnl;
+
+
+	if (chnl > 14) {
+		for (place = 14; place < sizeof(channel_all); place++) {
+			if (channel_all[place] == chnl)
+				return place - 13;
+		}
+	}
+	return 0;
+
+}
+#endif
+
+void
+odm_iq_calibrate(
+	struct dm_struct	*dm
+)
+{
+	void	*adapter = dm->adapter;
+	struct dm_iqk_info	*iqk_info = &dm->IQK_info;
+	
+	RF_DBG(dm, DBG_RF_IQK, "=>%s\n",__FUNCTION__);
+
+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
+	if (*dm->is_fcs_mode_enable)
+		return;
+#endif
+
+	if ((dm->is_linked) && (!iqk_info->rfk_forbidden)) {
+		RF_DBG(dm, DBG_RF_IQK, "interval=%d ch=%d prech=%d scan=%s\n", dm->linked_interval,
+		       *dm->channel,  dm->pre_channel, *dm->is_scan_in_process == TRUE ? "TRUE":"FALSE");
+
+		if (*dm->channel != dm->pre_channel) {
+			dm->pre_channel = *dm->channel;
+			dm->linked_interval = 0;
+		}
+
+		if ((dm->linked_interval < 3) && (!*dm->is_scan_in_process))
+			dm->linked_interval++;
+
+		if (dm->linked_interval == 2)
+			PHY_IQCalibrate(adapter, false);
+	} else
+		dm->linked_interval = 0;
+
+		RF_DBG(dm, DBG_RF_IQK, "<=%s interval=%d ch=%d prech=%d scan=%s\n", __FUNCTION__, dm->linked_interval,
+			*dm->channel,  dm->pre_channel, *dm->is_scan_in_process == TRUE?"TRUE":"FALSE");
+}
+
+void phydm_rf_init(struct dm_struct		*dm)
+{
+
+	odm_txpowertracking_init(dm);
+
+#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
+	odm_clear_txpowertracking_state(dm);
+#endif
+
+#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
+#if (RTL8814A_SUPPORT == 1)
+	if (dm->support_ic_type & ODM_RTL8814A)
+		phy_iq_calibrate_8814a_init(dm);
+#endif
+#endif
+
+}
+
+void phydm_rf_watchdog(struct dm_struct		*dm)
+{
+
+#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
+	odm_txpowertracking_check(dm);
+	if (dm->support_ic_type & ODM_IC_11AC_SERIES)
+		odm_iq_calibrate(dm);
+#endif
+}
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/halrf/halphyrf_win.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/halrf/halphyrf_win.h
--- linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/halrf/halphyrf_win.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/halrf/halphyrf_win.h	2020-04-10 16:35:06.819660208 +0300
@@ -0,0 +1,122 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+
+#ifndef __HALPHYRF_H__
+#define __HALPHYRF_H__
+
+#if (RTL8814A_SUPPORT == 1)
+	#include "halrf/rtl8814a/halrf_iqk_8814a.h"
+#endif
+
+#if (RTL8822B_SUPPORT == 1)
+	#include "halrf/rtl8822b/halrf_iqk_8822b.h"
+	#include "../mac/Halmac_type.h"
+#endif
+#include "halrf/halrf_powertracking_win.h"
+#include "halrf/halrf_kfree.h"
+#include "halrf/halrf_txgapcal.h"
+#if (RTL8821C_SUPPORT == 1)
+	#include "halrf/rtl8821c/halrf_iqk_8821c.h"
+#endif
+
+#if (RTL8195B_SUPPORT == 1)
+//	#include "halrf/rtl8195b/halrf.h"
+	#include "halrf/rtl8195b/halrf_iqk_8195b.h"
+	#include "halrf/rtl8195b/halrf_txgapk_8195b.h"
+	#include "halrf/rtl8195b/halrf_dpk_8195b.h"
+#endif
+
+
+enum spur_cal_method {
+	PLL_RESET,
+	AFE_PHASE_SEL
+};
+
+enum pwrtrack_method {
+	BBSWING,
+	TXAGC,
+	MIX_MODE,
+	TSSI_MODE,
+	MIX_2G_TSSI_5G_MODE,
+	MIX_5G_TSSI_2G_MODE
+};
+
+typedef void(*func_set_pwr)(void *, enum pwrtrack_method, u8, u8);
+typedef void(*func_iqk)(void *, u8, u8, u8);
+typedef void(*func_lck)(void *);
+typedef void(*func_swing)(void *, u8 **, u8 **, u8 **, u8 **);
+typedef void(*func_swing8814only)(void *, u8 **, u8 **, u8 **, u8 **);
+typedef void (*func_swing_xtal)(void *, s8 **, s8 **);
+typedef void (*func_set_xtal)(void *);
+typedef void(*func_all_swing)(void *, u8 **, u8 **, u8 **, u8 **, u8 **, u8 **, u8 **, u8 **);
+
+struct txpwrtrack_cfg {
+	u8		swing_table_size_cck;
+	u8		swing_table_size_ofdm;
+	u8		threshold_iqk;
+	u8		threshold_dpk;
+	u8		average_thermal_num;
+	u8		rf_path_count;
+	u32		thermal_reg_addr;
+	func_set_pwr	odm_tx_pwr_track_set_pwr;
+	func_iqk	do_iqk;
+	func_lck		phy_lc_calibrate;
+	func_swing	get_delta_swing_table;
+	func_swing8814only	get_delta_swing_table8814only;
+	func_swing_xtal			get_delta_swing_xtal_table;
+	func_set_xtal			odm_txxtaltrack_set_xtal;
+	func_all_swing	get_delta_all_swing_table;
+};
+
+void
+configure_txpower_track(
+	struct dm_struct		*dm,
+	struct txpwrtrack_cfg	*config
+);
+
+
+void
+odm_clear_txpowertracking_state(
+	struct dm_struct		*dm
+);
+
+void
+odm_txpowertracking_callback_thermal_meter(
+#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
+	struct dm_struct		*dm
+#else
+	void	*adapter
+#endif
+);
+
+
+
+#define ODM_TARGET_CHNL_NUM_2G_5G	59
+
+
+void
+odm_reset_iqk_result(
+	struct dm_struct	*dm
+);
+u8
+odm_get_right_chnl_place_for_iqk(
+	u8 chnl
+);
+
+void odm_iq_calibrate(struct dm_struct	*dm);
+void phydm_rf_init(struct dm_struct		*dm);
+void phydm_rf_watchdog(struct dm_struct		*dm);
+
+#endif	/*#ifndef __HALPHYRF_H__*/
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/halrf/halrf.c linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/halrf/halrf.c
--- linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/halrf/halrf.c	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/halrf/halrf.c	2020-04-10 16:35:06.819660208 +0300
@@ -0,0 +1,1806 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017  Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * The full GNU General Public License is included in this distribution in the
+ * file called LICENSE.
+ *
+ * Contact Information:
+ * wlanfae <wlanfae@realtek.com>
+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
+ * Hsinchu 300, Taiwan.
+ *
+ * Larry Finger <Larry.Finger@lwfinger.net>
+ *
+ *****************************************************************************/
+
+/* ************************************************************
+ * include files
+ * ************************************************************
+ */
+
+#include "mp_precomp.h"
+#include "phydm_precomp.h"
+
+#if (RTL8822B_SUPPORT == 1 || RTL8821C_SUPPORT == 1 ||\
+	RTL8195B_SUPPORT == 1 || RTL8198F_SUPPORT == 1)
+void _iqk_page_switch(void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+
+	if (dm->support_ic_type == ODM_RTL8821C)
+		odm_write_4byte(dm, 0x1b00, 0xf8000008);
+	else
+		odm_write_4byte(dm, 0x1b00, 0xf800000a);
+}
+
+u32 halrf_psd_log2base(u32 val)
+{
+	u8 j;
+	u32 tmp, tmp2, val_integerd_b = 0, tindex, shiftcount = 0;
+	u32 result, val_fractiond_b = 0;
+	u32 table_fraction[21] = {
+		0, 432, 332, 274, 232, 200, 174, 151, 132, 115,
+		100, 86, 74, 62, 51, 42, 32, 23, 15, 7, 0};
+
+	if (val == 0)
+		return 0;
+
+	tmp = val;
+
+	while (1) {
+		if (tmp == 1)
+			break;
+
+		tmp = (tmp >> 1);
+		shiftcount++;
+	}
+
+	val_integerd_b = shiftcount + 1;
+
+	tmp2 = 1;
+	for (j = 1; j <= val_integerd_b; j++)
+		tmp2 = tmp2 * 2;
+
+	tmp = (val * 100) / tmp2;
+	tindex = tmp / 5;
+
+	if (tindex > 20)
+		tindex = 20;
+
+	val_fractiond_b = table_fraction[tindex];
+
+	result = val_integerd_b * 100 - val_fractiond_b;
+
+	return result;
+}
+
+void phydm_get_iqk_cfir(void *dm_void, u8 idx, u8 path, boolean debug)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct dm_iqk_info *iqk_info = &dm->IQK_info;
+
+	u8 i, ch;
+	u32 tmp;
+	u32 bit_mask_20_16 = BIT(20) | BIT(19) | BIT(18) | BIT(17) | BIT(16);
+
+	if (debug)
+		ch = 2;
+	else
+		ch = 0;
+
+	odm_set_bb_reg(dm, R_0x1b00, MASKDWORD, 0xf8000008 | path << 1);
+	if (idx == 0)
+		odm_set_bb_reg(dm, R_0x1b0c, BIT(13) | BIT(12), 0x3);
+	else
+		odm_set_bb_reg(dm, R_0x1b0c, BIT(13) | BIT(12), 0x1);
+	odm_set_bb_reg(dm, R_0x1bd4, bit_mask_20_16, 0x10);
+	for (i = 0; i < 8; i++) {
+		odm_set_bb_reg(dm, R_0x1bd8, MASKDWORD, 0xe0000001 + (i * 4));
+		tmp = odm_get_bb_reg(dm, R_0x1bfc, MASKDWORD);
+		iqk_info->iqk_cfir_real[ch][path][idx][i] =
+						(tmp & 0x0fff0000) >> 16;
+		iqk_info->iqk_cfir_imag[ch][path][idx][i] = tmp & 0xfff;
+	}
+	odm_set_bb_reg(dm, R_0x1bd8, MASKDWORD, 0x0);
+	odm_set_bb_reg(dm, R_0x1b0c, BIT(13) | BIT(12), 0x0);
+}
+
+void halrf_iqk_xym_enable(struct dm_struct *dm, u8 xym_enable)
+{
+	struct dm_iqk_info *iqk_info = &dm->IQK_info;
+
+	if (xym_enable == 0)
+		iqk_info->xym_read = false;
+	else
+		iqk_info->xym_read = true;
+
+	RF_DBG(dm, DBG_RF_IQK, "[IQK]%-20s %s\n", "xym_read = ",
+	       (iqk_info->xym_read ? "true" : "false"));
+}
+
+/*xym_type => 0: rx_sym; 1: tx_xym; 2:gs1_xym; 3:gs2_sym; 4: rxk1_xym*/
+void halrf_iqk_xym_read(void *dm_void, u8 path, u8 xym_type)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct dm_iqk_info *iqk_info = &dm->IQK_info;
+	u8 i, start, num;
+	u32 tmp1, tmp2;
+
+	if (!iqk_info->xym_read)
+		return;
+
+	if (*dm->band_width == 0) {
+		start = 3;
+		num = 4;
+	} else if (*dm->band_width == 1) {
+		start = 2;
+		num = 6;
+	} else {
+		start = 0;
+		num = 10;
+	}
+
+	odm_write_4byte(dm, 0x1b00, 0xf8000008);
+	tmp1 = odm_read_4byte(dm, 0x1b1c);
+	odm_write_4byte(dm, 0x1b1c, 0xa2193c32);
+
+	odm_write_4byte(dm, 0x1b00, 0xf800000a);
+	tmp2 = odm_read_4byte(dm, 0x1b1c);
+	odm_write_4byte(dm, 0x1b1c, 0xa2193c32);
+
+	for (path = 0; path < 2; path++) {
+		odm_write_4byte(dm, 0x1b00, 0xf8000008 | path << 1);
+		switch (xym_type) {
+		case 0:
+			for (i = 0; i < num; i++) {
+				odm_write_4byte(dm, 0x1b14, 0xe6 + start + i);
+				odm_write_4byte(dm, 0x1b14, 0x0);
+				iqk_info->rx_xym[path][i] =
+						odm_read_4byte(dm, 0x1b38);
+			}
+			break;
+		case 1:
+			for (i = 0; i < num; i++) {
+				odm_write_4byte(dm, 0x1b14, 0xe6 + start + i);
+				odm_write_4byte(dm, 0x1b14, 0x0);
+				iqk_info->tx_xym[path][i] =
+						odm_read_4byte(dm, 0x1b38);
+			}
+			break;
+		case 2:
+			for (i = 0; i < 6; i++) {
+				odm_write_4byte(dm, 0x1b14, 0xe0 + i);
+				odm_write_4byte(dm, 0x1b14, 0x0);
+				iqk_info->gs1_xym[path][i] =
+						odm_read_4byte(dm, 0x1b38);
+			}
+			break;
+		case 3:
+			for (i = 0; i < 6; i++) {
+				odm_write_4byte(dm, 0x1b14, 0xe0 + i);
+				odm_write_4byte(dm, 0x1b14, 0x0);
+				iqk_info->gs2_xym[path][i] =
+						odm_read_4byte(dm, 0x1b38);
+			}
+			break;
+		case 4:
+			for (i = 0; i < 6; i++) {
+				odm_write_4byte(dm, 0x1b14, 0xe0 + i);
+				odm_write_4byte(dm, 0x1b14, 0x0);
+				iqk_info->rxk1_xym[path][i] =
+						odm_read_4byte(dm, 0x1b38);
+			}
+			break;
+		}
+		odm_write_4byte(dm, 0x1b38, 0x20000000);
+		odm_write_4byte(dm, 0x1b00, 0xf8000008);
+		odm_write_4byte(dm, 0x1b1c, tmp1);
+		odm_write_4byte(dm, 0x1b00, 0xf800000a);
+		odm_write_4byte(dm, 0x1b1c, tmp2);
+		_iqk_page_switch(dm);
+	}
+}
+
+/*xym_type => 0: rx_sym; 1: tx_xym; 2:gs1_xym; 3:gs2_sym; 4: rxk1_xym*/
+void halrf_iqk_xym_show(struct dm_struct *dm, u8 xym_type)
+{
+	u8 num, path, path_num, i;
+	struct dm_iqk_info *iqk_info = &dm->IQK_info;
+
+	if (dm->rf_type == RF_1T1R)
+		path_num = 0x1;
+	else if (dm->rf_type == RF_2T2R)
+		path_num = 0x2;
+	else
+		path_num = 0x4;
+
+	if (*dm->band_width == CHANNEL_WIDTH_20)
+		num = 4;
+	else if (*dm->band_width == CHANNEL_WIDTH_40)
+		num = 6;
+	else
+		num = 10;
+
+	for (path = 0; path < path_num; path++) {
+		switch (xym_type) {
+		case 0:
+			for (i = 0; i < num; i++)
+				RF_DBG(dm, DBG_RF_IQK,
+				       "[IQK]%-20s %-2d: 0x%x\n",
+				       (path == 0) ? "PATH A RX-XYM " :
+				       "PATH B RX-XYM", i,
+				       iqk_info->rx_xym[path][i]);
+			break;
+		case 1:
+			for (i = 0; i < num; i++)
+				RF_DBG(dm, DBG_RF_IQK,
+				       "[IQK]%-20s %-2d: 0x%x\n",
+				       (path == 0) ? "PATH A TX-XYM " :
+				       "PATH B TX-XYM", i,
+				       iqk_info->tx_xym[path][i]);
+			break;
+		case 2:
+			for (i = 0; i < 6; i++)
+				RF_DBG(dm, DBG_RF_IQK,
+				       "[IQK]%-20s %-2d: 0x%x\n",
+				       (path == 0) ? "PATH A GS1-XYM " :
+				       "PATH B GS1-XYM", i,
+				       iqk_info->gs1_xym[path][i]);
+			break;
+		case 3:
+			for (i = 0; i < 6; i++)
+				RF_DBG(dm, DBG_RF_IQK,
+				       "[IQK]%-20s %-2d: 0x%x\n",
+				       (path == 0) ? "PATH A GS2-XYM " :
+				       "PATH B GS2-XYM", i,
+				       iqk_info->gs2_xym[path][i]);
+			break;
+		case 4:
+			for (i = 0; i < 6; i++)
+				RF_DBG(dm, DBG_RF_IQK,
+				       "[IQK]%-20s %-2d: 0x%x\n",
+				       (path == 0) ? "PATH A RXK1-XYM " :
+				       "PATH B RXK1-XYM", i,
+				       iqk_info->rxk1_xym[path][i]);
+			break;
+		}
+	}
+}
+
+void halrf_iqk_xym_dump(void *dm_void)
+{
+	u32 tmp1, tmp2;
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+
+	odm_write_4byte(dm, 0x1b00, 0xf8000008);
+	tmp1 = odm_read_4byte(dm, 0x1b1c);
+	odm_write_4byte(dm, 0x1b00, 0xf800000a);
+	tmp2 = odm_read_4byte(dm, 0x1b1c);
+#if 0
+	/*halrf_iqk_xym_read(dm, xym_type);*/
+#endif
+	odm_write_4byte(dm, 0x1b00, 0xf8000008);
+	odm_write_4byte(dm, 0x1b1c, tmp1);
+	odm_write_4byte(dm, 0x1b00, 0xf800000a);
+	odm_write_4byte(dm, 0x1b1c, tmp2);
+	_iqk_page_switch(dm);
+}
+
+void halrf_iqk_info_dump(void *dm_void, u32 *_used, char *output, u32 *_out_len)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	u32 used = *_used;
+	u32 out_len = *_out_len;
+	u8 rf_path, j, reload_iqk = 0;
+	u32 tmp;
+	/*two channel, PATH, TX/RX, 0:pass 1 :fail*/
+	boolean iqk_result[2][NUM][2];
+	struct dm_iqk_info *iqk_info = &dm->IQK_info;
+
+	if (!(dm->support_ic_type & (ODM_RTL8822B | ODM_RTL8821C)))
+		return;
+
+	/* IQK INFO */
+	PDM_SNPF(out_len, used, output + used, out_len - used, "%-20s\n",
+		 "% IQK Info %");
+	PDM_SNPF(out_len, used, output + used, out_len - used, "%-20s\n",
+		 (dm->fw_offload_ability & PHYDM_RF_IQK_OFFLOAD) ? "FW-IQK" :
+		 "Driver-IQK");
+
+	reload_iqk = (u8)odm_get_bb_reg(dm, R_0x1bf0, BIT(16));
+	PDM_SNPF(out_len, used, output + used, out_len - used, "%-20s: %s\n",
+		 "reload", (reload_iqk) ? "True" : "False");
+
+	PDM_SNPF(out_len, used, output + used, out_len - used, "%-20s: %s\n",
+		 "rfk_forbidden", (iqk_info->rfk_forbidden) ? "True" : "False");
+#if (RTL8814A_SUPPORT == 1 || RTL8822B_SUPPORT == 1 || \
+	RTL8821C_SUPPORT == 1 || RTL8195B_SUPPORT == 1)
+	PDM_SNPF(out_len, used, output + used, out_len - used, "%-20s: %s\n",
+		 "segment_iqk", (iqk_info->segment_iqk) ? "True" : "False");
+#endif
+
+	PDM_SNPF(out_len, used, output + used, out_len - used, "%-20s:%d %d\n",
+		 "iqk count / fail count", dm->n_iqk_cnt, dm->n_iqk_fail_cnt);
+
+	PDM_SNPF(out_len, used, output + used, out_len - used, "%-20s: %d\n",
+		 "channel", *dm->channel);
+
+	if (*dm->band_width == CHANNEL_WIDTH_20)
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "%-20s: %s\n", "bandwidth", "BW_20");
+	else if (*dm->band_width == CHANNEL_WIDTH_40)
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "%-20s: %s\n", "bandwidth", "BW_40");
+	else if (*dm->band_width == CHANNEL_WIDTH_80)
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "%-20s: %s\n", "bandwidth", "BW_80");
+	else if (*dm->band_width == CHANNEL_WIDTH_160)
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "%-20s: %s\n", "bandwidth", "BW_160");
+	else
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "%-20s: %s\n", "bandwidth", "BW_UNKNOWN");
+
+	PDM_SNPF(out_len, used, output + used, out_len - used,
+		 "%-20s: %llu %s\n", "progressing_time",
+		 dm->rf_calibrate_info.iqk_total_progressing_time, "(ms)");
+
+	tmp = odm_read_4byte(dm, 0x1bf0);
+	for (rf_path = RF_PATH_A; rf_path <= RF_PATH_B; rf_path++)
+		for (j = 0; j < 2; j++)
+			iqk_result[0][rf_path][j] = (boolean)
+			(tmp & (BIT(rf_path + (j * 4)) >> (rf_path + (j * 4))));
+
+	PDM_SNPF(out_len, used, output + used, out_len - used,
+		 "%-20s: 0x%08x\n", "Reg0x1bf0", tmp);
+	PDM_SNPF(out_len, used, output + used, out_len - used, "%-20s: %s\n",
+		 "PATH_A-Tx result",
+		 (iqk_result[0][RF_PATH_A][0]) ? "Fail" : "Pass");
+	PDM_SNPF(out_len, used, output + used, out_len - used, "%-20s: %s\n",
+		 "PATH_A-Rx result",
+		 (iqk_result[0][RF_PATH_A][1]) ? "Fail" : "Pass");
+#if (RTL8822B_SUPPORT == 1)
+	PDM_SNPF(out_len, used, output + used, out_len - used, "%-20s: %s\n",
+		 "PATH_B-Tx result",
+		 (iqk_result[0][RF_PATH_B][0]) ? "Fail" : "Pass");
+	PDM_SNPF(out_len, used, output + used, out_len - used, "%-20s: %s\n",
+		 "PATH_B-Rx result",
+		 (iqk_result[0][RF_PATH_B][1]) ? "Fail" : "Pass");
+#endif
+	*_used = used;
+	*_out_len = out_len;
+}
+
+void halrf_get_fw_version(void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct _hal_rf_ *rf = &dm->rf_table;
+
+	rf->fw_ver = (dm->fw_version << 16) | dm->fw_sub_version;
+}
+
+void halrf_iqk_dbg(void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	u8 rf_path, j;
+	u32 tmp;
+	/*two channel, PATH, TX/RX, 0:pass 1 :fail*/
+	boolean iqk_result[2][NUM][2];
+	struct dm_iqk_info *iqk_info = &dm->IQK_info;
+	struct _hal_rf_ *rf = &dm->rf_table;
+
+	/* IQK INFO */
+	RF_DBG(dm, DBG_RF_IQK, "%-20s\n", "====== IQK Info ======");
+
+	RF_DBG(dm, DBG_RF_IQK, "%-20s\n",
+	       (dm->fw_offload_ability & PHYDM_RF_IQK_OFFLOAD) ? "FW-IQK" :
+	       "Driver-IQK");
+
+	if (dm->fw_offload_ability & PHYDM_RF_IQK_OFFLOAD) {
+		halrf_get_fw_version(dm);
+		RF_DBG(dm, DBG_RF_IQK, "%-20s: 0x%x\n", "FW_VER", rf->fw_ver);
+	} else {
+		RF_DBG(dm, DBG_RF_IQK, "%-20s: %s\n", "IQK_VER", HALRF_IQK_VER);
+	}
+
+	RF_DBG(dm, DBG_RF_IQK, "%-20s: %s\n", "reload",
+	       (iqk_info->is_reload) ? "True" : "False");
+
+	RF_DBG(dm, DBG_RF_IQK, "%-20s: %d %d\n", "iqk count / fail count",
+	       dm->n_iqk_cnt, dm->n_iqk_fail_cnt);
+
+	RF_DBG(dm, DBG_RF_IQK, "%-20s: %d\n", "channel", *dm->channel);
+
+	if (*dm->band_width == CHANNEL_WIDTH_20)
+		RF_DBG(dm, DBG_RF_IQK, "%-20s: %s\n", "bandwidth", "BW_20");
+	else if (*dm->band_width == CHANNEL_WIDTH_40)
+		RF_DBG(dm, DBG_RF_IQK, "%-20s: %s\n", "bandwidth", "BW_40");
+	else if (*dm->band_width == CHANNEL_WIDTH_80)
+		RF_DBG(dm, DBG_RF_IQK, "%-20s: %s\n", "bandwidth", "BW_80");
+	else if (*dm->band_width == CHANNEL_WIDTH_160)
+		RF_DBG(dm, DBG_RF_IQK, "%-20s: %s\n", "bandwidth", "BW_160");
+	else
+		RF_DBG(dm, DBG_RF_IQK, "%-20s: %s\n", "bandwidth",
+		       "BW_UNKNOWN");
+#if 0
+/*
+ *	RF_DBG(dm, DBG_RF_IQK, "%-20s: %llu %s\n",
+ *	       "progressing_time",
+ *	       dm->rf_calibrate_info.iqk_total_progressing_time, "(ms)");
+ */
+#endif
+	RF_DBG(dm, DBG_RF_IQK, "%-20s: %s\n", "rfk_forbidden",
+	       (iqk_info->rfk_forbidden) ? "True" : "False");
+#if (RTL8814A_SUPPORT == 1 || RTL8822B_SUPPORT == 1 || \
+	RTL8821C_SUPPORT == 1 || RTL8195B_SUPPORT == 1)
+	RF_DBG(dm, DBG_RF_IQK, "%-20s: %s\n", "segment_iqk",
+	       (iqk_info->segment_iqk) ? "True" : "False");
+#endif
+
+	RF_DBG(dm, DBG_RF_IQK, "%-20s: %llu %s\n", "progressing_time",
+	       dm->rf_calibrate_info.iqk_progressing_time, "(ms)");
+
+	tmp = odm_read_4byte(dm, 0x1bf0);
+	for (rf_path = RF_PATH_A; rf_path <= RF_PATH_B; rf_path++)
+		for (j = 0; j < 2; j++)
+			iqk_result[0][rf_path][j] = (boolean)
+			(tmp & (BIT(rf_path + (j * 4)) >> (rf_path + (j * 4))));
+
+	RF_DBG(dm, DBG_RF_IQK, "%-20s: 0x%08x\n", "Reg0x1bf0", tmp);
+	RF_DBG(dm, DBG_RF_IQK, "%-20s: 0x%08x\n", "Reg0x1be8",
+	       odm_read_4byte(dm, 0x1be8));
+	RF_DBG(dm, DBG_RF_IQK, "%-20s: %s\n", "PATH_A-Tx result",
+	       (iqk_result[0][RF_PATH_A][0]) ? "Fail" : "Pass");
+	RF_DBG(dm, DBG_RF_IQK, "%-20s: %s\n", "PATH_A-Rx result",
+	       (iqk_result[0][RF_PATH_A][1]) ? "Fail" : "Pass");
+#if (RTL8822B_SUPPORT == 1)
+	RF_DBG(dm, DBG_RF_IQK, "%-20s: %s\n", "PATH_B-Tx result",
+	       (iqk_result[0][RF_PATH_B][0]) ? "Fail" : "Pass");
+	RF_DBG(dm, DBG_RF_IQK, "%-20s: %s\n", "PATH_B-Rx result",
+	       (iqk_result[0][RF_PATH_B][1]) ? "Fail" : "Pass");
+#endif
+}
+
+void halrf_lck_dbg(struct dm_struct *dm)
+{
+	RF_DBG(dm, DBG_RF_IQK, "%-20s\n", "====== LCK Info ======");
+#if 0
+	/*RF_DBG(dm, DBG_RF_IQK, "%-20s\n",
+	 *	 (dm->fw_offload_ability & PHYDM_RF_IQK_OFFLOAD) ? "LCK" : "RTK"));
+	 */
+#endif
+	RF_DBG(dm, DBG_RF_IQK, "%-20s: %llu %s\n", "progressing_time",
+	       dm->rf_calibrate_info.lck_progressing_time, "(ms)");
+}
+
+void halrf_iqk_dbg_cfir_backup(struct dm_struct *dm)
+{
+	struct dm_iqk_info *iqk_info = &dm->IQK_info;
+	u8 path, idx, i;
+
+	RF_DBG(dm, DBG_RF_IQK, "[IQK]%-20s\n", "backup TX/RX CFIR");
+
+	for (path = 0; path < 2; path++)
+		for (idx = 0; idx < 2; idx++)
+			phydm_get_iqk_cfir(dm, idx, path, true);
+
+	for (path = 0; path < 2; path++) {
+		for (idx = 0; idx < 2; idx++) {
+			for (i = 0; i < 8; i++) {
+				RF_DBG(dm, DBG_RF_IQK,
+				       "[IQK]%-7s %-3s CFIR_real: %-2d: 0x%x\n",
+				       (path == 0) ? "PATH A" : "PATH B",
+				       (idx == 0) ? "TX" : "RX", i,
+				       iqk_info->iqk_cfir_real[2][path][idx][i])
+				       ;
+			}
+			for (i = 0; i < 8; i++) {
+				RF_DBG(dm, DBG_RF_IQK,
+				       "[IQK]%-7s %-3s CFIR_img:%-2d: 0x%x\n",
+				       (path == 0) ? "PATH A" : "PATH B",
+				       (idx == 0) ? "TX" : "RX", i,
+				       iqk_info->iqk_cfir_imag[2][path][idx][i])
+				       ;
+			}
+		}
+	}
+}
+
+void halrf_iqk_dbg_cfir_backup_update(struct dm_struct *dm)
+{
+	struct dm_iqk_info *iqk = &dm->IQK_info;
+	u8 i, path, idx;
+	u32 bmask13_12 = BIT(13) | BIT(12);
+	u32 bmask20_16 = BIT(20) | BIT(19) | BIT(18) | BIT(17) | BIT(16);
+	u32 data;
+
+	if (iqk->iqk_cfir_real[2][0][0][0] == 0) {
+		RF_DBG(dm, DBG_RF_IQK, "[IQK]%-20s\n", "CFIR is invalid");
+		return;
+	}
+	for (path = 0; path < 2; path++) {
+		for (idx = 0; idx < 2; idx++) {
+			odm_set_bb_reg(dm, R_0x1b00, MASKDWORD,
+				       0xf8000008 | path << 1);
+			odm_set_bb_reg(dm, R_0x1b2c, MASKDWORD, 0x7);
+			odm_set_bb_reg(dm, R_0x1b38, MASKDWORD, 0x20000000);
+			odm_set_bb_reg(dm, R_0x1b3c, MASKDWORD, 0x20000000);
+			odm_set_bb_reg(dm, R_0x1bcc, MASKDWORD, 0x00000000);
+			if (idx == 0)
+				odm_set_bb_reg(dm, R_0x1b0c, bmask13_12, 0x3);
+			else
+				odm_set_bb_reg(dm, R_0x1b0c, bmask13_12, 0x1);
+			odm_set_bb_reg(dm, R_0x1bd4, bmask20_16, 0x10);
+			for (i = 0; i < 8; i++) {
+				data = ((0xc0000000 >> idx) + 0x3) + (i * 4) +
+					(iqk->iqk_cfir_real[2][path][idx][i]
+					<< 9);
+				odm_write_4byte(dm, 0x1bd8, data);
+				data = ((0xc0000000 >> idx) + 0x1) + (i * 4) +
+					(iqk->iqk_cfir_imag[2][path][idx][i]
+					<< 9);
+				odm_write_4byte(dm, 0x1bd8, data);
+#if 0
+				/*odm_write_4byte(dm, 0x1bd8, iqk->iqk_cfir_real[2][path][idx][i]);*/
+				/*odm_write_4byte(dm, 0x1bd8, iqk->iqk_cfir_imag[2][path][idx][i]);*/
+#endif
+			}
+		}
+		odm_set_bb_reg(dm, R_0x1bd8, MASKDWORD, 0x0);
+		odm_set_bb_reg(dm, R_0x1b0c, bmask13_12, 0x0);
+	}
+	RF_DBG(dm, DBG_RF_IQK, "[IQK]%-20s\n", "update new CFIR");
+}
+
+void halrf_iqk_dbg_cfir_reload(struct dm_struct *dm)
+{
+	struct dm_iqk_info *iqk = &dm->IQK_info;
+	u8 i, path, idx;
+	u32 bmask13_12 = BIT(13) | BIT(12);
+	u32 bmask20_16 = BIT(20) | BIT(19) | BIT(18) | BIT(17) | BIT(16);
+	u32 data;
+
+	if (iqk->iqk_cfir_real[0][0][0][0] == 0) {
+		RF_DBG(dm, DBG_RF_IQK, "[IQK]%-20s\n", "CFIR is invalid");
+		return;
+	}
+	for (path = 0; path < 2; path++) {
+		for (idx = 0; idx < 2; idx++) {
+			odm_set_bb_reg(dm, R_0x1b00, MASKDWORD,
+				       0xf8000008 | path << 1);
+			odm_set_bb_reg(dm, R_0x1b2c, MASKDWORD, 0x7);
+			odm_set_bb_reg(dm, R_0x1b38, MASKDWORD, 0x20000000);
+			odm_set_bb_reg(dm, R_0x1b3c, MASKDWORD, 0x20000000);
+			odm_set_bb_reg(dm, R_0x1bcc, MASKDWORD, 0x00000000);
+			if (idx == 0)
+				odm_set_bb_reg(dm, R_0x1b0c, bmask13_12, 0x3);
+			else
+				odm_set_bb_reg(dm, R_0x1b0c, bmask13_12, 0x1);
+			odm_set_bb_reg(dm, R_0x1bd4, bmask20_16, 0x10);
+			for (i = 0; i < 8; i++) {
+#if 0
+				/*odm_write_4byte(dm, 0x1bd8, iqk->iqk_cfir_real[0][path][idx][i]);*/
+				/*odm_write_4byte(dm, 0x1bd8, iqk->iqk_cfir_imag[0][path][idx][i]);*/
+#endif
+				data = ((0xc0000000 >> idx) + 0x3) + (i * 4) +
+					(iqk->iqk_cfir_real[0][path][idx][i]
+					<< 9);
+				odm_write_4byte(dm, 0x1bd8, data);
+				data = ((0xc0000000 >> idx) + 0x1) + (i * 4) +
+					(iqk->iqk_cfir_imag[0][path][idx][i]
+					<< 9);
+				odm_write_4byte(dm, 0x1bd8, data);
+			}
+		}
+		odm_set_bb_reg(dm, R_0x1bd8, MASKDWORD, 0x0);
+		odm_set_bb_reg(dm, R_0x1b0c, bmask13_12, 0x0);
+	}
+	RF_DBG(dm, DBG_RF_IQK, "[IQK]%-20s\n", "write CFIR with default value");
+}
+
+void halrf_iqk_dbg_cfir_write(struct dm_struct *dm, u8 type, u32 path, u32 idx,
+			      u32 i, u32 data)
+{
+	struct dm_iqk_info *iqk_info = &dm->IQK_info;
+
+	if (type == 0)
+		iqk_info->iqk_cfir_real[2][path][idx][i] = data;
+	else
+		iqk_info->iqk_cfir_imag[2][path][idx][i] = data;
+}
+
+void halrf_iqk_dbg_cfir_backup_show(struct dm_struct *dm)
+{
+	struct dm_iqk_info *iqk_info = &dm->IQK_info;
+	u8 path, idx, i;
+
+	RF_DBG(dm, DBG_RF_IQK, "[IQK]%-20s\n", "backup TX/RX CFIR");
+
+	for (path = 0; path < 2; path++) {
+		for (idx = 0; idx < 2; idx++) {
+			for (i = 0; i < 8; i++) {
+				RF_DBG(dm, DBG_RF_IQK,
+				       "[IQK]%-10s %-3s CFIR_real:%-2d: 0x%x\n",
+				       (path == 0) ? "PATH A" : "PATH B",
+				       (idx == 0) ? "TX" : "RX", i,
+				       iqk_info->iqk_cfir_real[2][path][idx][i])
+				       ;
+			}
+			for (i = 0; i < 8; i++) {
+				RF_DBG(dm, DBG_RF_IQK,
+				       "[IQK]%-10s %-3s CFIR_img:%-2d: 0x%x\n",
+				       (path == 0) ? "PATH A" : "PATH B",
+				       (idx == 0) ? "TX" : "RX", i,
+				       iqk_info->iqk_cfir_imag[2][path][idx][i])
+				       ;
+			}
+		}
+	}
+}
+
+void halrf_do_imr_test(void *dm_void, u8 flag_imr_test)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+
+	if (flag_imr_test != 0x0)
+		switch (dm->support_ic_type) {
+#if (RTL8822B_SUPPORT == 1)
+		case ODM_RTL8822B:
+			do_imr_test_8822b(dm);
+			break;
+#endif
+#if (RTL8821C_SUPPORT == 1)
+		case ODM_RTL8821C:
+			do_imr_test_8821c(dm);
+			break;
+#endif
+		default:
+			break;
+		}
+}
+
+void halrf_iqk_debug(void *dm_void, u32 *const dm_value, u32 *_used,
+		     char *output, u32 *_out_len)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+
+#if 0
+	/*dm_value[0]=0x0: backup from SRAM & show*/
+	/*dm_value[0]=0x1: write backup CFIR to SRAM*/
+	/*dm_value[0]=0x2: reload default CFIR to SRAM*/
+	/*dm_value[0]=0x3: show backup*/
+	/*dm_value[0]=0x10: write backup CFIR real part*/
+	/*--> dm_value[1]:path, dm_value[2]:tx/rx, dm_value[3]:index, dm_value[4]:data*/
+	/*dm_value[0]=0x11: write backup CFIR imag*/
+	/*--> dm_value[1]:path, dm_value[2]:tx/rx, dm_value[3]:index, dm_value[4]:data*/
+	/*dm_value[0]=0x20 :xym_read enable*/
+	/*--> dm_value[1]:0:disable, 1:enable*/
+	/*if dm_value[0]=0x20 = enable, */
+	/*0x1:show rx_sym; 0x2: tx_xym; 0x3:gs1_xym; 0x4:gs2_sym; 0x5:rxk1_xym*/
+#endif
+	if (dm_value[0] == 0x0)
+		halrf_iqk_dbg_cfir_backup(dm);
+	else if (dm_value[0] == 0x1)
+		halrf_iqk_dbg_cfir_backup_update(dm);
+	else if (dm_value[0] == 0x2)
+		halrf_iqk_dbg_cfir_reload(dm);
+	else if (dm_value[0] == 0x3)
+		halrf_iqk_dbg_cfir_backup_show(dm);
+	else if (dm_value[0] == 0x10)
+		halrf_iqk_dbg_cfir_write(dm, 0, dm_value[1], dm_value[2],
+					 dm_value[3], dm_value[4]);
+	else if (dm_value[0] == 0x11)
+		halrf_iqk_dbg_cfir_write(dm, 1, dm_value[1], dm_value[2],
+					 dm_value[3], dm_value[4]);
+	else if (dm_value[0] == 0x20)
+		halrf_iqk_xym_enable(dm, (u8)dm_value[1]);
+	else if (dm_value[0] == 0x21)
+		halrf_iqk_xym_show(dm, (u8)dm_value[1]);
+	else if (dm_value[0] == 0x30)
+		halrf_do_imr_test(dm, (u8)dm_value[1]);
+}
+
+void halrf_iqk_hwtx_check(void *dm_void, boolean is_check)
+{
+#if 0
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct dm_iqk_info *iqk_info = &dm->IQK_info;
+	u32 tmp_b04;
+
+	if (is_check) {
+		iqk_info->is_hwtx = (boolean)odm_get_bb_reg(dm, R_0xb00, BIT(8));
+	} else {
+		if (iqk_info->is_hwtx) {
+			tmp_b04 = odm_read_4byte(dm, 0xb04);
+			odm_set_bb_reg(dm, R_0xb04, BIT(3) | BIT(2), 0x0);
+			odm_write_4byte(dm, 0xb04, tmp_b04);
+		}
+	}
+#endif
+}
+
+void halrf_segment_iqk_trigger(void *dm_void, boolean clear,
+			       boolean segment_iqk)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct dm_iqk_info *iqk_info = &dm->IQK_info;
+	struct _hal_rf_ *rf = &dm->rf_table;
+	u64 start_time;
+
+#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN))
+	if (odm_check_power_status(dm) == false)
+		return;
+#endif
+
+	if (dm->mp_mode &&
+	    rf->is_con_tx &&
+	    rf->is_single_tone &&
+	    rf->is_carrier_suppresion)
+		if (*dm->mp_mode &&
+		    ((*rf->is_con_tx ||
+		     *rf->is_single_tone ||
+		     *rf->is_carrier_suppresion)))
+			return;
+
+#if (DM_ODM_SUPPORT_TYPE == ODM_CE)
+	if (!(rf->rf_supportability & HAL_RF_IQK))
+		return;
+#endif
+
+#if DISABLE_BB_RF
+	return;
+#endif
+	if (iqk_info->rfk_forbidden)
+		return;
+
+	if (!dm->rf_calibrate_info.is_iqk_in_progress) {
+		odm_acquire_spin_lock(dm, RT_IQK_SPINLOCK);
+		dm->rf_calibrate_info.is_iqk_in_progress = true;
+		odm_release_spin_lock(dm, RT_IQK_SPINLOCK);
+		start_time = odm_get_current_time(dm);
+		dm->IQK_info.segment_iqk = segment_iqk;
+
+		switch (dm->support_ic_type) {
+#if (RTL8822B_SUPPORT == 1)
+		case ODM_RTL8822B:
+			phy_iq_calibrate_8822b(dm, clear, segment_iqk);
+			break;
+#endif
+#if (RTL8821C_SUPPORT == 1)
+		case ODM_RTL8821C:
+			phy_iq_calibrate_8821c(dm, clear, segment_iqk);
+			break;
+#endif
+#if (RTL8814B_SUPPORT == 1)
+		case ODM_RTL8814B:
+			break;
+#endif
+#if (RTL8195B_SUPPORT == 1)
+		case ODM_RTL8195B:
+			phy_iq_calibrate_8195b(dm, clear, segment_iqk);
+			break;
+#endif
+#if (RTL8198F_SUPPORT == 1)
+		case ODM_RTL8198F:
+			phy_iq_calibrate_8198f(dm, clear, segment_iqk);
+			break;
+#endif
+
+		default:
+			break;
+		}
+		dm->rf_calibrate_info.iqk_progressing_time =
+				odm_get_progressing_time(dm, start_time);
+		RF_DBG(dm, DBG_RF_IQK, "[IQK]IQK progressing_time = %lld ms\n",
+		       dm->rf_calibrate_info.iqk_progressing_time);
+
+		odm_acquire_spin_lock(dm, RT_IQK_SPINLOCK);
+		dm->rf_calibrate_info.is_iqk_in_progress = false;
+		odm_release_spin_lock(dm, RT_IQK_SPINLOCK);
+	} else {
+		RF_DBG(dm, DBG_RF_IQK,
+		       "== Return the IQK CMD, because RFKs in Progress ==\n");
+	}
+}
+
+#endif
+
+u8 halrf_match_iqk_version(void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+
+	u32 iqk_version = 0;
+	char temp[10] = {0};
+
+	odm_move_memory(dm, temp, HALRF_IQK_VER, sizeof(temp));
+	PHYDM_SSCANF(temp + 2, DCMD_HEX, &iqk_version);
+
+	if (dm->support_ic_type == ODM_RTL8822B) {
+		if (iqk_version >= 0x24 && (odm_get_hw_img_version(dm) >= 72))
+			return 1;
+		else if ((iqk_version <= 0x23) &&
+			 (odm_get_hw_img_version(dm) <= 71))
+			return 1;
+		else
+			return 0;
+	}
+
+	if (dm->support_ic_type == ODM_RTL8821C) {
+		if (iqk_version >= 0x18 && (odm_get_hw_img_version(dm) >= 37))
+			return 1;
+		else
+			return 0;
+	}
+
+	return 1;
+}
+
+void halrf_rf_lna_setting(void *dm_void, enum halrf_lna_set type)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+
+	switch (dm->support_ic_type) {
+#if (RTL8188E_SUPPORT == 1)
+	case ODM_RTL8188E:
+		halrf_rf_lna_setting_8188e(dm, type);
+		break;
+#endif
+#if (RTL8192E_SUPPORT == 1)
+	case ODM_RTL8192E:
+		halrf_rf_lna_setting_8192e(dm, type);
+		break;
+#endif
+#if (RTL8192F_SUPPORT == 1)
+	case ODM_RTL8192F:
+		halrf_rf_lna_setting_8192f(dm, type);
+		break;
+#endif
+
+#if (RTL8723B_SUPPORT == 1)
+	case ODM_RTL8723B:
+		halrf_rf_lna_setting_8723b(dm, type);
+		break;
+#endif
+#if (RTL8812A_SUPPORT == 1)
+	case ODM_RTL8812:
+		halrf_rf_lna_setting_8812a(dm, type);
+		break;
+#endif
+#if ((RTL8821A_SUPPORT == 1) || (RTL8881A_SUPPORT == 1))
+	case ODM_RTL8881A:
+	case ODM_RTL8821:
+		halrf_rf_lna_setting_8821a(dm, type);
+		break;
+#endif
+#if (RTL8822B_SUPPORT == 1)
+	case ODM_RTL8822B:
+		halrf_rf_lna_setting_8822b(dm_void, type);
+		break;
+#endif
+#if (RTL8821C_SUPPORT == 1)
+	case ODM_RTL8821C:
+		halrf_rf_lna_setting_8821c(dm_void, type);
+		break;
+#endif
+	default:
+		break;
+	}
+}
+
+void halrf_support_ability_debug(void *dm_void, char input[][16], u32 *_used,
+				 char *output, u32 *_out_len)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct _hal_rf_ *rf = &dm->rf_table;
+	u32 dm_value[10] = {0};
+	u32 used = *_used;
+	u32 out_len = *_out_len;
+	u8 i;
+
+	for (i = 0; i < 5; i++)
+		if (input[i + 1])
+			PHYDM_SSCANF(input[i + 2], DCMD_DECIMAL, &dm_value[i]);
+
+	if (dm_value[0] == 100) {
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "\n[RF Supportability]\n");
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "00. (( %s ))Power Tracking\n",
+			 ((rf->rf_supportability & HAL_RF_TX_PWR_TRACK) ?
+			 ("V") : (".")));
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "01. (( %s ))IQK\n",
+			 ((rf->rf_supportability & HAL_RF_IQK) ? ("V") :
+			 (".")));
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "02. (( %s ))LCK\n",
+			 ((rf->rf_supportability & HAL_RF_LCK) ? ("V") :
+			 (".")));
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "03. (( %s ))DPK\n",
+			 ((rf->rf_supportability & HAL_RF_DPK) ? ("V") :
+			 (".")));
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "04. (( %s ))HAL_RF_TXGAPK\n",
+			 ((rf->rf_supportability & HAL_RF_TXGAPK) ? ("V") :
+			 (".")));
+	} else {
+		if (dm_value[1] == 1) /* enable */
+			rf->rf_supportability |= BIT(dm_value[0]);
+		else if (dm_value[1] == 2) /* disable */
+			rf->rf_supportability &= ~(BIT(dm_value[0]));
+		else
+			PDM_SNPF(out_len, used, output + used, out_len - used,
+				 "[Warning!!!]  1:enable,  2:disable\n");
+	}
+	PDM_SNPF(out_len, used, output + used, out_len - used,
+		 "\nCurr-RF_supportability =  0x%x\n\n", rf->rf_supportability);
+
+	*_used = used;
+	*_out_len = out_len;
+}
+
+void halrf_cmn_info_init(void *dm_void, enum halrf_cmninfo_init cmn_info,
+			 u32 value)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct _hal_rf_ *rf = &dm->rf_table;
+
+	switch (cmn_info) {
+	case HALRF_CMNINFO_EEPROM_THERMAL_VALUE:
+		rf->eeprom_thermal = (u8)value;
+		break;
+	case HALRF_CMNINFO_PWT_TYPE:
+		rf->pwt_type = (u8)value;
+		break;
+	default:
+		break;
+	}
+}
+
+void halrf_cmn_info_hook(void *dm_void, enum halrf_cmninfo_hook cmn_info,
+			 void *value)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct _hal_rf_ *rf = &dm->rf_table;
+
+	switch (cmn_info) {
+	case HALRF_CMNINFO_CON_TX:
+		rf->is_con_tx = (boolean *)value;
+		break;
+	case HALRF_CMNINFO_SINGLE_TONE:
+		rf->is_single_tone = (boolean *)value;
+		break;
+	case HALRF_CMNINFO_CARRIER_SUPPRESSION:
+		rf->is_carrier_suppresion = (boolean *)value;
+		break;
+	case HALRF_CMNINFO_MP_RATE_INDEX:
+		rf->mp_rate_index = (u8 *)value;
+		break;
+	default:
+		/*do nothing*/
+		break;
+	}
+}
+
+void halrf_cmn_info_set(void *dm_void, u32 cmn_info, u64 value)
+{
+	/* This init variable may be changed in run time. */
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct _hal_rf_ *rf = &dm->rf_table;
+
+	switch (cmn_info) {
+	case HALRF_CMNINFO_ABILITY:
+		rf->rf_supportability = (u32)value;
+		break;
+
+	case HALRF_CMNINFO_DPK_EN:
+		rf->dpk_en = (u8)value;
+		break;
+	case HALRF_CMNINFO_RFK_FORBIDDEN:
+		dm->IQK_info.rfk_forbidden = (boolean)value;
+		break;
+#if (RTL8814A_SUPPORT == 1 || RTL8822B_SUPPORT == 1 || \
+	RTL8821C_SUPPORT == 1 || RTL8195B_SUPPORT == 1)
+	case HALRF_CMNINFO_IQK_SEGMENT:
+		dm->IQK_info.segment_iqk = (boolean)value;
+		break;
+#endif
+	case HALRF_CMNINFO_RATE_INDEX:
+		rf->p_rate_index = (u32)value;
+		break;
+#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
+	case HALRF_CMNINFO_MP_PSD_POINT:
+		rf->halrf_psd_data.point = (u32)value;
+		break;
+	case HALRF_CMNINFO_MP_PSD_START_POINT:
+		rf->halrf_psd_data.start_point = (u32)value;
+		break;
+	case HALRF_CMNINFO_MP_PSD_STOP_POINT:
+		rf->halrf_psd_data.stop_point = (u32)value;
+		break;
+	case HALRF_CMNINFO_MP_PSD_AVERAGE:
+		rf->halrf_psd_data.average = (u32)value;
+		break;
+#endif
+	default:
+		/* do nothing */
+		break;
+	}
+}
+
+u64 halrf_cmn_info_get(void *dm_void, u32 cmn_info)
+{
+	/* This init variable may be changed in run time. */
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct _hal_rf_ *rf = &dm->rf_table;
+	u64 return_value = 0;
+
+	switch (cmn_info) {
+	case HALRF_CMNINFO_ABILITY:
+		return_value = (u32)rf->rf_supportability;
+		break;
+	case HALRF_CMNINFO_RFK_FORBIDDEN:
+		return_value = dm->IQK_info.rfk_forbidden;
+		break;
+#if (RTL8814A_SUPPORT == 1 || RTL8822B_SUPPORT == 1 || \
+	RTL8821C_SUPPORT == 1 || RTL8195B_SUPPORT == 1)
+	case HALRF_CMNINFO_IQK_SEGMENT:
+		return_value = dm->IQK_info.segment_iqk;
+		break;
+#endif
+	default:
+		/* do nothing */
+		break;
+	}
+
+	return return_value;
+}
+
+void halrf_supportability_init_mp(void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct _hal_rf_ *rf = &dm->rf_table;
+
+	switch (dm->support_ic_type) {
+	case ODM_RTL8814B:
+#if (RTL8814B_SUPPORT == 1)
+		rf->rf_supportability =
+			HAL_RF_TX_PWR_TRACK |
+			HAL_RF_IQK |
+			HAL_RF_LCK |
+			/*HAL_RF_DPK |*/
+			0;
+#endif
+		break;
+#if (RTL8822B_SUPPORT == 1)
+	case ODM_RTL8822B:
+		rf->rf_supportability =
+			HAL_RF_TX_PWR_TRACK |
+			HAL_RF_IQK |
+			HAL_RF_LCK |
+			/*HAL_RF_DPK |*/
+			0;
+		break;
+#endif
+
+#if (RTL8821C_SUPPORT == 1)
+	case ODM_RTL8821C:
+		rf->rf_supportability =
+			HAL_RF_TX_PWR_TRACK |
+			HAL_RF_IQK |
+			HAL_RF_LCK |
+			/*HAL_RF_DPK |*/
+			/*HAL_RF_TXGAPK |*/
+			0;
+		break;
+#endif
+#if (RTL8195B_SUPPORT == 1)
+	case ODM_RTL8195B:
+		rf->rf_supportability =
+			HAL_RF_TX_PWR_TRACK |
+			HAL_RF_IQK |
+			HAL_RF_LCK |
+			HAL_RF_DPK |
+			HAL_RF_TXGAPK |
+			0;
+		break;
+#endif
+
+	default:
+		rf->rf_supportability =
+			HAL_RF_TX_PWR_TRACK |
+			HAL_RF_IQK |
+			HAL_RF_LCK |
+			/*HAL_RF_DPK |*/
+			/*HAL_RF_TXGAPK |*/
+			0;
+		break;
+	}
+
+	RF_DBG(dm, DBG_RF_INIT,
+	       "IC = ((0x%x)), RF_Supportability Init MP = ((0x%x))\n",
+	       dm->support_ic_type, rf->rf_supportability);
+}
+
+void halrf_supportability_init(void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct _hal_rf_ *rf = &dm->rf_table;
+
+	switch (dm->support_ic_type) {
+	case ODM_RTL8814B:
+#if (RTL8814B_SUPPORT == 1)
+		rf->rf_supportability =
+			HAL_RF_TX_PWR_TRACK |
+			HAL_RF_IQK |
+			HAL_RF_LCK |
+			/*HAL_RF_DPK |*/
+			0;
+#endif
+		break;
+#if (RTL8822B_SUPPORT == 1)
+	case ODM_RTL8822B:
+		rf->rf_supportability =
+			HAL_RF_TX_PWR_TRACK |
+			HAL_RF_IQK |
+			HAL_RF_LCK |
+			/*HAL_RF_DPK |*/
+			0;
+		break;
+#endif
+
+#if (RTL8821C_SUPPORT == 1)
+	case ODM_RTL8821C:
+		rf->rf_supportability =
+			HAL_RF_TX_PWR_TRACK |
+			HAL_RF_IQK |
+			HAL_RF_LCK |
+			/*HAL_RF_DPK |*/
+			/*HAL_RF_TXGAPK |*/
+			0;
+		break;
+#endif
+#if (RTL8195B_SUPPORT == 1)
+	case ODM_RTL8195B:
+		rf->rf_supportability =
+			HAL_RF_TX_PWR_TRACK |
+			HAL_RF_IQK |
+			HAL_RF_LCK |
+			HAL_RF_DPK |
+			HAL_RF_TXGAPK |
+			0;
+		break;
+#endif
+
+	default:
+		rf->rf_supportability =
+			HAL_RF_TX_PWR_TRACK |
+			HAL_RF_IQK |
+			HAL_RF_LCK |
+			/*HAL_RF_DPK |*/
+			0;
+		break;
+	}
+
+	RF_DBG(dm, DBG_RF_INIT,
+	       "IC = ((0x%x)), RF_Supportability Init = ((0x%x))\n",
+	       dm->support_ic_type, rf->rf_supportability);
+}
+
+void halrf_watchdog(void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+#if 0
+	/*RF_DBG(dm, DBG_RF_TMP, "%s\n", __func__);*/
+#endif
+
+	phydm_rf_watchdog(dm);
+}
+
+#if 0
+void
+halrf_iqk_init(
+	void			*dm_void
+)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct _hal_rf_ *rf = &dm->rf_table;
+
+	switch (dm->support_ic_type) {
+#if (RTL8814B_SUPPORT == 1)
+	case ODM_RTL8814B:
+		break;
+#endif
+#if (RTL8822B_SUPPORT == 1)
+	case ODM_RTL8822B:
+		_iq_calibrate_8822b_init(dm);
+		break;
+#endif
+#if (RTL8821C_SUPPORT == 1)
+	case ODM_RTL8821C:
+		break;
+#endif
+
+	default:
+		break;
+	}
+}
+#endif
+
+void halrf_iqk_trigger(void *dm_void, boolean is_recovery)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct dm_iqk_info *iqk_info = &dm->IQK_info;
+	struct dm_dpk_info *dpk_info = &dm->dpk_info;
+	struct _hal_rf_ *rf = &dm->rf_table;
+	u64 start_time;
+
+#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN))
+	if (odm_check_power_status(dm) == false)
+		return;
+#endif
+
+	if (dm->mp_mode &&
+	    rf->is_con_tx &&
+	    rf->is_single_tone &&
+	    rf->is_carrier_suppresion)
+		if (*dm->mp_mode &&
+		    ((*rf->is_con_tx ||
+		     *rf->is_single_tone ||
+		     *rf->is_carrier_suppresion)))
+			return;
+
+#if (DM_ODM_SUPPORT_TYPE == ODM_CE)
+	if (!(rf->rf_supportability & HAL_RF_IQK))
+		return;
+#endif
+
+#if DISABLE_BB_RF
+	return;
+#endif
+
+	if (iqk_info->rfk_forbidden)
+		return;
+
+	if (!dm->rf_calibrate_info.is_iqk_in_progress) {
+		odm_acquire_spin_lock(dm, RT_IQK_SPINLOCK);
+		dm->rf_calibrate_info.is_iqk_in_progress = true;
+		odm_release_spin_lock(dm, RT_IQK_SPINLOCK);
+		start_time = odm_get_current_time(dm);
+		switch (dm->support_ic_type) {
+#if (RTL8188E_SUPPORT == 1)
+		case ODM_RTL8188E:
+			phy_iq_calibrate_8188e(dm, is_recovery);
+			break;
+#endif
+#if (RTL8188F_SUPPORT == 1)
+		case ODM_RTL8188F:
+			phy_iq_calibrate_8188f(dm, is_recovery);
+			break;
+#endif
+#if (RTL8192E_SUPPORT == 1)
+		case ODM_RTL8192E:
+			phy_iq_calibrate_8192e(dm, is_recovery);
+			break;
+#endif
+#if (RTL8197F_SUPPORT == 1)
+		case ODM_RTL8197F:
+			phy_iq_calibrate_8197f(dm, is_recovery);
+			break;
+#endif
+#if (RTL8192F_SUPPORT == 1)
+		case ODM_RTL8192F:
+			phy_iq_calibrate_8192f(dm, is_recovery);
+			break;
+#endif
+#if (RTL8703B_SUPPORT == 1)
+		case ODM_RTL8703B:
+			phy_iq_calibrate_8703b(dm, is_recovery);
+			break;
+#endif
+#if (RTL8710B_SUPPORT == 1)
+		case ODM_RTL8710B:
+			phy_iq_calibrate_8710b(dm, is_recovery);
+			break;
+#endif
+#if (RTL8723B_SUPPORT == 1)
+		case ODM_RTL8723B:
+			phy_iq_calibrate_8723b(dm, is_recovery);
+			break;
+#endif
+#if (RTL8723D_SUPPORT == 1)
+		case ODM_RTL8723D:
+			phy_iq_calibrate_8723d(dm, is_recovery);
+			break;
+#endif
+#if (RTL8812A_SUPPORT == 1)
+		case ODM_RTL8812:
+			phy_iq_calibrate_8812a(dm, is_recovery);
+			break;
+#endif
+#if (RTL8821A_SUPPORT == 1)
+		case ODM_RTL8821:
+			phy_iq_calibrate_8821a(dm, is_recovery);
+			break;
+#endif
+#if (RTL8814A_SUPPORT == 1)
+		case ODM_RTL8814A:
+			phy_iq_calibrate_8814a(dm, is_recovery);
+			break;
+#endif
+#if (RTL8822B_SUPPORT == 1)
+		case ODM_RTL8822B:
+			phy_iq_calibrate_8822b(dm, false, false);
+			break;
+#endif
+#if (RTL8821C_SUPPORT == 1)
+		case ODM_RTL8821C:
+			phy_iq_calibrate_8821c(dm, false, false);
+			break;
+#endif
+#if (RTL8814B_SUPPORT == 1)
+		case ODM_RTL8814B:
+			break;
+#endif
+#if (RTL8195B_SUPPORT == 1)
+		case ODM_RTL8195B:
+			phy_iq_calibrate_8195b(dm, false, false);
+			break;
+#endif
+#if (RTL8198F_SUPPORT == 1)
+		case ODM_RTL8198F:
+			phy_iq_calibrate_8198f(dm, false, false);
+			break;
+#endif
+
+		default:
+			break;
+		}
+		dm->rf_calibrate_info.iqk_progressing_time =
+				odm_get_progressing_time(dm, start_time);
+		RF_DBG(dm, DBG_RF_IQK, "[IQK]IQK progressing_time = %lld ms\n",
+		       dm->rf_calibrate_info.iqk_progressing_time);
+
+		odm_acquire_spin_lock(dm, RT_IQK_SPINLOCK);
+		dm->rf_calibrate_info.is_iqk_in_progress = false;
+		odm_release_spin_lock(dm, RT_IQK_SPINLOCK);
+	} else {
+		RF_DBG(dm, DBG_RF_IQK,
+		       "== Return the IQK CMD, because RFKs in Progress ==\n");
+	}
+}
+
+void halrf_lck_trigger(void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct dm_iqk_info *iqk_info = &dm->IQK_info;
+	struct _hal_rf_ *rf = &dm->rf_table;
+	u64 start_time;
+
+#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN))
+	if (odm_check_power_status(dm) == false)
+		return;
+#endif
+
+	if (dm->mp_mode &&
+	    rf->is_con_tx &&
+	    rf->is_single_tone &&
+	    rf->is_carrier_suppresion)
+		if (*dm->mp_mode &&
+		    ((*rf->is_con_tx ||
+		     *rf->is_single_tone ||
+		     *rf->is_carrier_suppresion)))
+			return;
+
+#if (DM_ODM_SUPPORT_TYPE == ODM_CE)
+	if (!(rf->rf_supportability & HAL_RF_LCK))
+		return;
+#endif
+
+#if DISABLE_BB_RF
+	return;
+#endif
+	if (iqk_info->rfk_forbidden)
+		return;
+	while (*dm->is_scan_in_process) {
+		RF_DBG(dm, DBG_RF_IQK, "[LCK]scan is in process, bypass LCK\n");
+		return;
+	}
+
+	if (!dm->rf_calibrate_info.is_lck_in_progress) {
+		odm_acquire_spin_lock(dm, RT_IQK_SPINLOCK);
+		dm->rf_calibrate_info.is_lck_in_progress = true;
+		odm_release_spin_lock(dm, RT_IQK_SPINLOCK);
+		start_time = odm_get_current_time(dm);
+		switch (dm->support_ic_type) {
+#if (RTL8188E_SUPPORT == 1)
+		case ODM_RTL8188E:
+			phy_lc_calibrate_8188e(dm);
+			break;
+#endif
+#if (RTL8188F_SUPPORT == 1)
+		case ODM_RTL8188F:
+			phy_lc_calibrate_8188f(dm);
+			break;
+#endif
+#if (RTL8192E_SUPPORT == 1)
+		case ODM_RTL8192E:
+			phy_lc_calibrate_8192e(dm);
+			break;
+#endif
+#if (RTL8197F_SUPPORT == 1)
+		case ODM_RTL8197F:
+			phy_lc_calibrate_8197f(dm);
+			break;
+#endif
+#if (RTL8192F_SUPPORT == 1)
+		case ODM_RTL8192F:
+			phy_lc_calibrate_8192f(dm);
+			break;
+#endif
+#if (RTL8703B_SUPPORT == 1)
+		case ODM_RTL8703B:
+			phy_lc_calibrate_8703b(dm);
+			break;
+#endif
+#if (RTL8710B_SUPPORT == 1)
+		case ODM_RTL8710B:
+			phy_lc_calibrate_8710b(dm);
+			break;
+#endif
+#if (RTL8723B_SUPPORT == 1)
+		case ODM_RTL8723B:
+			phy_lc_calibrate_8723b(dm);
+			break;
+#endif
+#if (RTL8723D_SUPPORT == 1)
+		case ODM_RTL8723D:
+			phy_lc_calibrate_8723d(dm);
+			break;
+#endif
+#if (RTL8812A_SUPPORT == 1)
+		case ODM_RTL8812:
+			phy_lc_calibrate_8812a(dm);
+			break;
+#endif
+#if (RTL8821A_SUPPORT == 1)
+		case ODM_RTL8821:
+			phy_lc_calibrate_8821a(dm);
+			break;
+#endif
+#if (RTL8814A_SUPPORT == 1)
+		case ODM_RTL8814A:
+			phy_lc_calibrate_8814a(dm);
+			break;
+#endif
+#if (RTL8822B_SUPPORT == 1)
+		case ODM_RTL8822B:
+			phy_lc_calibrate_8822b(dm);
+			break;
+#endif
+#if (RTL8821C_SUPPORT == 1)
+		case ODM_RTL8821C:
+			phy_lc_calibrate_8821c(dm);
+			break;
+#endif
+#if (RTL8814B_SUPPORT == 1)
+		case ODM_RTL8814B:
+			break;
+#endif
+		default:
+			break;
+		}
+		dm->rf_calibrate_info.lck_progressing_time =
+				odm_get_progressing_time(dm, start_time);
+		RF_DBG(dm, DBG_RF_IQK, "[IQK]LCK progressing_time = %lld ms\n",
+		       dm->rf_calibrate_info.lck_progressing_time);
+#if (RTL8822B_SUPPORT == 1 || RTL8821C_SUPPORT == 1)
+		halrf_lck_dbg(dm);
+#endif
+		odm_acquire_spin_lock(dm, RT_IQK_SPINLOCK);
+		dm->rf_calibrate_info.is_lck_in_progress = false;
+		odm_release_spin_lock(dm, RT_IQK_SPINLOCK);
+	} else {
+		RF_DBG(dm, DBG_RF_IQK,
+		       "= Return the LCK CMD, because RFK is in Progress =\n");
+	}
+}
+
+void halrf_aac_check(struct dm_struct *dm)
+{
+	switch (dm->support_ic_type) {
+#if (RTL8821C_SUPPORT == 1)
+	case ODM_RTL8821C:
+#if 0
+		aac_check_8821c(dm);
+#endif
+		break;
+#endif
+#if (RTL8822B_SUPPORT == 1)
+	case ODM_RTL8822B:
+#if 1
+		aac_check_8822b(dm);
+#endif
+		break;
+#endif
+	default:
+		break;
+	}
+}
+
+void halrf_init(void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct _hal_rf_ *rf = &dm->rf_table;
+
+	RF_DBG(dm, DBG_RF_INIT, "HALRF_Init\n");
+	rf->aac_checked = false;
+	halrf_init_debug_setting(dm);
+
+	if (*dm->mp_mode)
+		halrf_supportability_init_mp(dm);
+	else
+		halrf_supportability_init(dm);
+
+	/*Init all RF funciton*/
+	halrf_aac_check(dm);
+}
+
+void halrf_dpk_trigger(void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct _hal_rf_ *rf = &dm->rf_table;
+
+	u64 start_time;
+
+	start_time = odm_get_current_time(dm);
+
+	switch (dm->support_ic_type) {
+#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
+#if (RTL8197F_SUPPORT == 1)
+	case ODM_RTL8197F:
+		do_dpk_8197f(dm);
+		break;
+#endif
+#if (RTL8192F_SUPPORT == 1)
+	case ODM_RTL8192F:
+		do_dpk_8192f(dm);
+		break;
+#endif
+
+#if (RTL8198F_SUPPORT == 1)
+	case ODM_RTL8198F:
+		do_dpk_8198f(dm);
+		break;
+#endif
+
+#endif
+
+#if (DM_ODM_SUPPORT_TYPE & (ODM_IOT))
+#if (RTL8195B_SUPPORT == 1)
+	case ODM_RTL8195B:
+		do_dpk_8195b(dm, false);
+	break;
+#endif
+#endif
+
+	default:
+		break;
+	}
+	rf->dpk_progressing_time = odm_get_progressing_time(dm, start_time);
+	RF_DBG(dm, DBG_RF_DPK, "[DPK]DPK progressing_time = %lld ms\n",
+	       rf->dpk_progressing_time);
+}
+
+u8 halrf_dpk_result_check(void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct dm_dpk_info *dpk_info = &dm->dpk_info;
+
+	u8 result = 0;
+
+	switch (dm->support_ic_type) {
+#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
+
+#if (RTL8197F_SUPPORT == 1)
+	case ODM_RTL8197F:
+		if (dpk_info->dpk_path_ok == 0x3)
+			result = 1;
+		else
+			result = 0;
+		break;
+#endif
+
+#if (RTL8192F_SUPPORT == 1)
+	case ODM_RTL8192F:
+		if (dpk_info->dpk_path_ok == 0x3)
+			result = 1;
+		else
+			result = 0;
+		break;
+#endif
+
+#if (RTL8198F_SUPPORT == 1)
+	case ODM_RTL8198F:
+		if (dpk_info->dpk_path_ok == 0xf)
+			result = 1;
+		else
+			result = 0;
+		break;
+#endif
+
+#endif
+	default:
+		break;
+	}
+	return result;
+}
+
+void halrf_dpk_sram_read(void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+
+	u8 path, group;
+
+	switch (dm->support_ic_type) {
+#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
+
+#if (RTL8197F_SUPPORT == 1)
+	case ODM_RTL8197F:
+		dpk_sram_read_8197f(dm);
+		break;
+#endif
+
+#if (RTL8192F_SUPPORT == 1)
+	case ODM_RTL8192F:
+		dpk_sram_read_8192f(dm);
+		break;
+#endif
+
+#if (RTL8198F_SUPPORT == 1)
+	case ODM_RTL8198F:
+		dpk_sram_read_8198f(dm);
+		break;
+#endif
+
+#endif
+	default:
+		break;
+	}
+}
+
+void halrf_dpk_enable_disable(void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+
+	switch (dm->support_ic_type) {
+#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
+
+#if (RTL8197F_SUPPORT == 1)
+	case ODM_RTL8197F:
+		phy_dpk_enable_disable_8197f(dm);
+		break;
+#endif
+#if (RTL8192F_SUPPORT == 1)
+	case ODM_RTL8192F:
+		phy_dpk_enable_disable_8192f(dm);
+		break;
+#endif
+
+#if (RTL8198F_SUPPORT == 1)
+	case ODM_RTL8198F:
+		dpk_enable_disable_8198f(dm);
+		break;
+#endif
+
+#endif
+	default:
+		break;
+	}
+}
+
+void halrf_dpk_track(void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct dm_dpk_info *dpk_info = &dm->dpk_info;
+
+	switch (dm->support_ic_type) {
+#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
+
+#if (RTL8197F_SUPPORT == 1)
+	case ODM_RTL8197F:
+		phy_dpk_track_8197f(dm);
+		break;
+#endif
+
+#if (RTL8192F_SUPPORT == 1)
+	case ODM_RTL8192F:
+		phy_dpk_track_8192f(dm);
+		break;
+#endif
+
+#if (RTL8198F_SUPPORT == 1)
+	case ODM_RTL8198F:
+		dpk_track_8198f(dm);
+		break;		
+#endif
+
+#endif
+	default:
+		break;
+	}
+}
+
+void halrf_dpk_reload(void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct dm_dpk_info *dpk_info = &dm->dpk_info;
+
+	switch (dm->support_ic_type) {
+#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
+
+#if (RTL8197F_SUPPORT == 1)
+	case ODM_RTL8197F:
+		if (dpk_info->dpk_path_ok > 0)
+			dpk_reload_8197f(dm);
+		break;
+#endif
+
+#if (RTL8192F_SUPPORT == 1)
+	case ODM_RTL8192F:
+		if (dpk_info->dpk_path_ok > 0)
+			dpk_reload_8192f(dm);
+
+		break;
+#endif
+
+#if (RTL8198F_SUPPORT == 1)
+	case ODM_RTL8198F:
+		if (dpk_info->dpk_path_ok > 0)
+			dpk_reload_8198f(dm);
+		break;		
+#endif
+
+#endif
+	default:
+		break;
+	}
+}
+
+enum hal_status
+halrf_config_rfk_with_header_file(void *dm_void, u32 config_type)
+{
+#if (RTL8198F_SUPPORT == 1)
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+#endif
+	enum hal_status result = HAL_STATUS_SUCCESS;
+#if 0
+#if (RTL8822B_SUPPORT == 1)
+	if (dm->support_ic_type == ODM_RTL8822B) {
+		if (config_type == CONFIG_BB_RF_CAL_INIT)
+			odm_read_and_config_mp_8822b_cal_init(dm);
+	}
+#endif
+#endif
+
+#if 1
+#if (RTL8198F_SUPPORT == 1)
+	if (dm->support_ic_type == ODM_RTL8198F) {
+		if (config_type == CONFIG_BB_RF_CAL_INIT)
+			odm_read_and_config_mp_8198f_cal_init(dm);
+	}
+#endif
+#endif
+	return result;
+}
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/halrf/halrf_debug.c linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/halrf/halrf_debug.c
--- linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/halrf/halrf_debug.c	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/halrf/halrf_debug.c	2020-04-10 16:35:06.819660208 +0300
@@ -0,0 +1,259 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017  Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * The full GNU General Public License is included in this distribution in the
+ * file called LICENSE.
+ *
+ * Contact Information:
+ * wlanfae <wlanfae@realtek.com>
+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
+ * Hsinchu 300, Taiwan.
+ *
+ * Larry Finger <Larry.Finger@lwfinger.net>
+ *
+ *****************************************************************************/
+
+/* ************************************************************
+ * include files
+ * ************************************************************
+ */
+
+#include "mp_precomp.h"
+#include "phydm_precomp.h"
+
+void halrf_basic_profile(void *dm_void, u32 *_used, char *output, u32 *_out_len)
+{
+#ifdef CONFIG_PHYDM_DEBUG_FUNCTION
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	u32 used = *_used;
+	u32 out_len = *_out_len;
+
+	/* HAL RF version List */
+	PDM_SNPF(out_len, used, output + used, out_len - used, "%-35s\n",
+		 "% HAL RF version %");
+	PDM_SNPF(out_len, used, output + used, out_len - used, "  %-35s: %s\n",
+		 "Power Tracking", HALRF_POWRTRACKING_VER);
+	PDM_SNPF(out_len, used, output + used, out_len - used,
+		 "  %-35s: %s %s\n", "IQK",
+		 (dm->fw_offload_ability & PHYDM_RF_IQK_OFFLOAD) ? "FW" :
+		 HALRF_IQK_VER,
+		 (halrf_match_iqk_version(dm_void)) ? "(match)" : "(mismatch)");
+
+	PDM_SNPF(out_len, used, output + used, out_len - used, "  %-35s: %s\n",
+		 "LCK", HALRF_LCK_VER);
+	PDM_SNPF(out_len, used, output + used, out_len - used, "  %-35s: %s\n",
+		 "DPK", HALRF_DPK_VER);
+	PDM_SNPF(out_len, used, output + used, out_len - used, "  %-35s: %s\n",
+		 "KFREE", HALRF_KFREE_VER);
+	PDM_SNPF(out_len, used, output + used, out_len - used, "  %-35s: %s\n",
+		 "TX 2G Current Calibration", HALRF_PABIASK_VER);
+	PDM_SNPF(out_len, used, output + used, out_len - used, "  %-35s: %s\n",
+		 "RFK Init. Parameter", HALRF_RFK_INIT_VER);
+
+	*_used = used;
+	*_out_len = out_len;
+#endif
+}
+
+void halrf_debug_trace(void *dm_void, char input[][16], u32 *_used,
+		       char *output, u32 *_out_len)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct _hal_rf_ *rf = &dm->rf_table;
+	u32 one = 1;
+	u32 used = *_used;
+	u32 out_len = *_out_len;
+	u32 rf_var[10] = {0};
+	u8 i;
+
+	for (i = 0; i < 5; i++)
+		if (input[i + 1])
+			PHYDM_SSCANF(input[i + 2], DCMD_DECIMAL, &rf_var[i]);
+
+	if (rf_var[0] == 100) {
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "\n[DBG MSG] RF Selection\n");
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "00. (( %s ))TX_PWR_TRACK\n",
+			 ((rf->rf_dbg_comp & DBG_RF_TX_PWR_TRACK) ? ("V") :
+			 (".")));
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "01. (( %s ))IQK\n",
+			 ((rf->rf_dbg_comp & DBG_RF_IQK) ? ("V") : (".")));
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "02. (( %s ))LCK\n",
+			 ((rf->rf_dbg_comp & DBG_RF_LCK) ? ("V") : (".")));
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "03. (( %s ))DPK\n",
+			 ((rf->rf_dbg_comp & DBG_RF_DPK) ? ("V") : (".")));
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "04. (( %s ))TXGAPK\n",
+			 ((rf->rf_dbg_comp & DBG_RF_TXGAPK) ? ("V") : (".")));
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "29. (( %s ))MP\n",
+			 ((rf->rf_dbg_comp & DBG_RF_MP) ? ("V") : (".")));
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "30. (( %s ))TMP\n",
+			 ((rf->rf_dbg_comp & DBG_RF_TMP) ? ("V") : (".")));
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "31. (( %s ))INIT\n",
+			 ((rf->rf_dbg_comp & DBG_RF_INIT) ? ("V") : (".")));
+
+	} else if (rf_var[0] == 101) {
+		rf->rf_dbg_comp = 0;
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "Disable all DBG COMP\n");
+	} else {
+		if (rf_var[1] == 1) /*enable*/
+			rf->rf_dbg_comp |= (one << rf_var[0]);
+		else if (rf_var[1] == 2) /*disable*/
+			rf->rf_dbg_comp &= ~(one << rf_var[0]);
+	}
+	PDM_SNPF(out_len, used, output + used, out_len - used,
+		 "\nCurr-RF_Dbg_Comp = 0x%x\n", rf->rf_dbg_comp);
+
+	*_used = used;
+	*_out_len = out_len;
+}
+
+struct halrf_command {
+	char name[16];
+	u8 id;
+};
+
+enum halrf_CMD_ID {
+	HALRF_HELP,
+	HALRF_SUPPORTABILITY,
+	HALRF_DBG_COMP,
+	HALRF_PROFILE,
+	HALRF_IQK_INFO,
+	HALRF_IQK,
+	HALRF_IQK_DEBUG,
+};
+
+struct halrf_command halrf_cmd_ary[] = {
+	{"-h", HALRF_HELP},
+	{"ability", HALRF_SUPPORTABILITY},
+	{"dbg", HALRF_DBG_COMP},
+	{"profile", HALRF_PROFILE},
+	{"iqk_info", HALRF_IQK_INFO},
+	{"iqk", HALRF_IQK},
+	{"iqk_dbg", HALRF_IQK_DEBUG},
+};
+
+void halrf_cmd_parser(void *dm_void, char input[][16], u32 *_used, char *output,
+		      u32 *_out_len, u32 input_num)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+#ifdef CONFIG_PHYDM_DEBUG_FUNCTION
+	u8 id = 0;
+	u32 rf_var[10] = {0};
+	u32 i, input_idx = 0;
+	u32 halrf_ary_size =
+			sizeof(halrf_cmd_ary) / sizeof(struct halrf_command);
+	u32 used = *_used;
+	u32 out_len = *_out_len;
+
+	/* Parsing Cmd ID */
+	for (i = 0; i < halrf_ary_size; i++) {
+		if (strcmp(halrf_cmd_ary[i].name, input[1]) == 0) {
+			id = halrf_cmd_ary[i].id;
+			break;
+		}
+	}
+
+	if (i == halrf_ary_size) {
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "RF Cmd not found\n");
+		return;
+	}
+
+	switch (id) {
+	case HALRF_HELP:
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "RF cmd ==>\n");
+
+		for (i = 0; i < halrf_ary_size - 1; i++) {
+			PDM_SNPF(out_len, used, output + used, out_len - used,
+				 "  %-5d: %s\n", i, halrf_cmd_ary[i + 1].name);
+		}
+		break;
+	case HALRF_SUPPORTABILITY:
+		halrf_support_ability_debug(dm, &input[0], &used, output,
+					    &out_len);
+		break;
+	case HALRF_DBG_COMP:
+		halrf_debug_trace(dm, &input[0], &used, output, &out_len);
+		break;
+	case HALRF_PROFILE:
+		halrf_basic_profile(dm, &used, output, &out_len);
+		break;
+	case HALRF_IQK_INFO:
+#if (RTL8822B_SUPPORT == 1 || RTL8821C_SUPPORT == 1)
+		halrf_iqk_info_dump(dm, &used, output, &out_len);
+#endif
+		break;
+	case HALRF_IQK:
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "TRX IQK Trigger\n");
+		halrf_iqk_trigger(dm, false);
+#if (RTL8822B_SUPPORT == 1 || RTL8821C_SUPPORT == 1)
+		halrf_iqk_info_dump(dm, &used, output, &out_len);
+#endif
+		break;
+	case HALRF_IQK_DEBUG:
+
+		for (i = 0; i < 5; i++) {
+			if (input[i + 1]) {
+				PHYDM_SSCANF(input[i + 2], DCMD_HEX,
+					     &rf_var[i]);
+				input_idx++;
+			}
+		}
+
+		if (input_idx >= 1) {
+#if (RTL8822B_SUPPORT == 1 || RTL8821C_SUPPORT == 1)
+			if (dm->support_ic_type & (ODM_RTL8822B | ODM_RTL8821C))
+				halrf_iqk_debug(dm, (u32 *)rf_var, &used,
+						output, &out_len);
+#endif
+		}
+		break;
+	default:
+		break;
+	}
+
+	*_used = used;
+	*_out_len = out_len;
+#endif
+}
+
+void halrf_init_debug_setting(void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct _hal_rf_ *rf = &dm->rf_table;
+
+	rf->rf_dbg_comp =
+#if DBG
+#if 0
+	/*DBG_RF_TX_PWR_TRACK	|*/
+	/*DBG_RF_IQK		| */
+	/*DBG_RF_LCK		| */
+	/*DBG_RF_DPK		| */
+	/*DBG_RF_TXGAPK		| */
+	/*DBG_RF_TMP		| */
+	/*DBG_RF_INIT		| */
+#endif
+#endif
+	0;
+}
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/halrf/halrf_debug.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/halrf/halrf_debug.h
--- linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/halrf/halrf_debug.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/halrf/halrf_debug.h	2020-04-10 16:35:06.819660208 +0300
@@ -0,0 +1,123 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017  Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * The full GNU General Public License is included in this distribution in the
+ * file called LICENSE.
+ *
+ * Contact Information:
+ * wlanfae <wlanfae@realtek.com>
+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
+ * Hsinchu 300, Taiwan.
+ *
+ * Larry Finger <Larry.Finger@lwfinger.net>
+ *
+ *****************************************************************************/
+
+#ifndef __HALRF_DEBUG_H__
+#define __HALRF_DEBUG_H__
+
+/*============================================================*/
+/*include files*/
+/*============================================================*/
+
+/*============================================================*/
+/*Definition */
+/*============================================================*/
+
+#if DBG
+
+#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
+#define RF_DBG(dm, comp, fmt, args...)                     \
+	do {                                               \
+		if ((comp) & dm->rf_table.rf_dbg_comp) { \
+			pr_debug("[RF] ");                 \
+			RT_PRINTK(fmt, ##args);            \
+		}                                          \
+	} while (0)
+
+#elif (DM_ODM_SUPPORT_TYPE == ODM_WIN)
+
+static __inline void RF_DBG(PDM_ODM_T dm, int comp, char *fmt, ...)
+{
+	RT_STATUS rt_status;
+	va_list args;
+	char buf[PRINT_MAX_SIZE] = {0};
+
+	if ((comp & dm->rf_table.rf_dbg_comp) == 0)
+		return;
+
+	if (fmt == NULL)
+		return;
+
+	va_start(args, fmt);
+	rt_status = (RT_STATUS)RtlStringCbVPrintfA(buf, PRINT_MAX_SIZE, fmt, args);
+	va_end(args);
+
+	if (rt_status != RT_STATUS_SUCCESS) {
+		DbgPrint("Failed (%d) to print message to buffer\n", rt_status);
+		return;
+	}
+
+	DbgPrint("[RF] %s", buf);
+}
+
+#elif (DM_ODM_SUPPORT_TYPE == ODM_IOT)
+
+#define RF_DBG(dm, comp, fmt, args...)                     \
+	do {                                               \
+		if ((comp) & dm->rf_table.rf_dbg_comp) { \
+			RT_DEBUG(COMP_PHYDM, DBG_DMESG, "[RF] " fmt, ##args);  \
+		}                                          \
+	} while (0)
+
+#else
+#define RF_DBG(dm, comp, fmt, args...)                                         \
+	do {                                                                   \
+		struct dm_struct *__dm = dm;                                   \
+		if ((comp) & __dm->rf_table.rf_dbg_comp) {                     \
+			RT_TRACE(((struct rtl_priv *)__dm->adapter),           \
+				 COMP_PHYDM, DBG_DMESG, "[RF] " fmt, ##args);  \
+		}                                                              \
+	} while (0)
+#endif
+
+#else /*#if DBG*/
+
+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
+static __inline void RF_DBG(struct dm_struct *dm, int comp, char *fmt, ...)
+{
+}
+#else
+#define RF_DBG(dm, comp, fmt, args...)
+#endif
+
+#endif /*#if DBG*/
+
+/*============================================================*/
+/* enumeration */
+/*============================================================*/
+
+/*============================================================*/
+/* structure */
+/*============================================================*/
+
+/*============================================================*/
+/* function prototype */
+/*============================================================*/
+
+void halrf_cmd_parser(void *dm_void, char input[][16], u32 *_used, char *output,
+		      u32 *_out_len, u32 input_num);
+
+void halrf_init_debug_setting(void *dm_void);
+
+#endif /*#ifndef __HALRF_H__*/
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/halrf/halrf_dpk.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/halrf/halrf_dpk.h
--- linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/halrf/halrf_dpk.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/halrf/halrf_dpk.h	2020-04-10 16:35:06.819660208 +0300
@@ -0,0 +1,74 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017  Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * The full GNU General Public License is included in this distribution in the
+ * file called LICENSE.
+ *
+ * Contact Information:
+ * wlanfae <wlanfae@realtek.com>
+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
+ * Hsinchu 300, Taiwan.
+ *
+ * Larry Finger <Larry.Finger@lwfinger.net>
+ *
+ *****************************************************************************/
+
+#ifndef __HALRF_DPK_H__
+#define __HALRF_DPK_H__
+
+/*--------------------------Define Parameters-------------------------------*/
+#define GAIN_LOSS 1
+#define DO_DPK 2
+#define DPK_ON 3
+#define AVG_THERMAL_NUM 8
+#define AVG_THERMAL_NUM_DPK 8
+#define THERMAL_DPK_AVG_NUM 4
+
+/*---------------------------End Define Parameters---------------------------*/
+
+struct dm_dpk_info {
+
+	boolean	is_dpk_enable;
+	/*boolean	is_dpk_path_ok[4];*/		/*path*/
+	u16 dpk_path_ok;
+	/*BIT(15)~BIT(12) : 5G reserved, BIT(11)~BIT(8) 5G_S3~5G_S0*/
+	/*BIT(7)~BIT(4) : 2G reserved, BIT(3)~BIT(0) 2G_S3~2G_S0*/
+
+#if (RTL8198F_SUPPORT == 1 || RTL8192F_SUPPORT == 1 || RTL8197F_SUPPORT == 1)
+	/*2G DPK data*/
+	u8 	dpk_result[4][3];		/*path/group*/
+	u8 	pwsf_2g[4][3];			/*path/group*/
+	u32	lut_2g_even[4][3][64];		/*path/group/LUT data*/
+	u32	lut_2g_odd[4][3][64];		/*path/group/LUT data*/
+#if 0
+	/*5G DPK data*/
+	u8 	dpk_5g_result[4][9];		/*path/group*/
+	u8 	pwsf_5g[4][9];			/*path/group*/
+	u32	lut_5g_even[4][9][64];		/*path/group/LUT data*/
+	u32	lut_5g_odd[4][9][64];		/*path/group/LUT data*/
+#endif
+	u8	thermal_dpk;
+	u8	thermal_dpk_avg[AVG_THERMAL_NUM_DPK];
+	u8	thermal_dpk_avg_index;
+
+#endif
+
+#if (RTL8195B_SUPPORT == 1)
+	u32 sram_even[7][64];
+	u32 sram_odd[7][64];
+	boolean dpk_result[7];
+	u32 dpk_pwsf[7];
+#endif
+};
+
+#endif /*#ifndef __HALRF_DPK_H__*/
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/halrf/halrf_features.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/halrf/halrf_features.h
--- linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/halrf/halrf_features.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/halrf/halrf_features.h	2020-04-10 16:35:06.819660208 +0300
@@ -0,0 +1,43 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017  Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * The full GNU General Public License is included in this distribution in the
+ * file called LICENSE.
+ *
+ * Contact Information:
+ * wlanfae <wlanfae@realtek.com>
+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
+ * Hsinchu 300, Taiwan.
+ *
+ * Larry Finger <Larry.Finger@lwfinger.net>
+ *
+ *****************************************************************************/
+
+#ifndef __HALRF_FEATURES_H__
+#define __HALRF_FEATURES_H__
+
+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
+
+#define CONFIG_HALRF_POWERTRACKING 1
+
+#elif (DM_ODM_SUPPORT_TYPE == ODM_AP)
+
+#define CONFIG_HALRF_POWERTRACKING 1
+
+#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
+
+#define CONFIG_HALRF_POWERTRACKING 1
+
+#endif
+
+#endif /*#ifndef __HALRF_FEATURES_H__*/
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/halrf/halrf.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/halrf/halrf.h
--- linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/halrf/halrf.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/halrf/halrf.h	2020-04-10 16:35:06.819660208 +0300
@@ -0,0 +1,471 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017  Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * The full GNU General Public License is included in this distribution in the
+ * file called LICENSE.
+ *
+ * Contact Information:
+ * wlanfae <wlanfae@realtek.com>
+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
+ * Hsinchu 300, Taiwan.
+ *
+ * Larry Finger <Larry.Finger@lwfinger.net>
+ *
+ *****************************************************************************/
+
+#ifndef __HALRF_H__
+#define __HALRF_H__
+
+/*============================================================*/
+/*include files*/
+/*============================================================*/
+#include "halrf/halrf_psd.h"
+#if (RTL8822B_SUPPORT == 1)
+#include "halrf/rtl8822b/halrf_rfk_init_8822b.h"
+#endif
+
+#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
+#if (RTL8198F_SUPPORT == 1)
+#include "halrf/rtl8198f/halrf_rfk_init_8198f.h"
+#endif
+#endif
+
+/*============================================================*/
+/*Definition */
+/*============================================================*/
+/*IQK version*/
+#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN))
+#define IQK_VER_8188E "0x14"
+#define IQK_VER_8192E "0x01"
+#define IQK_VER_8192F "0x01"
+#define IQK_VER_8723B "0x1e"
+#define IQK_VER_8812A "0x01"
+#define IQK_VER_8821A "0x01"
+#elif (DM_ODM_SUPPORT_TYPE & (ODM_CE))
+#define IQK_VER_8188E "0x01"
+#define IQK_VER_8192E "0x01"
+#define IQK_VER_8192F "0x01"
+#define IQK_VER_8723B "0x1e"
+#define IQK_VER_8812A "0x01"
+#define IQK_VER_8821A "0x01"
+#elif (DM_ODM_SUPPORT_TYPE & (ODM_AP))
+#define IQK_VER_8188E "0x01"
+#define IQK_VER_8192E "0x01"
+#define IQK_VER_8192F "0x01"
+#define IQK_VER_8723B "0x1e"
+#define IQK_VER_8812A "0x01"
+#define IQK_VER_8821A "0x01"
+#elif (DM_ODM_SUPPORT_TYPE & (ODM_IOT))
+#define IQK_VER_8188E "0x01"
+#define IQK_VER_8192E "0x01"
+#define IQK_VER_8192F "0x01"
+#define IQK_VER_8723B "0x1e"
+#define IQK_VER_8812A "0x01"
+#define IQK_VER_8821A "0x01"
+#endif
+#define IQK_VER_8814A "0x0f"
+#define IQK_VER_8188F "0x01"
+#define IQK_VER_8197F "0x1c"
+#define IQK_VER_8703B "0x05"
+#define IQK_VER_8710B "0x01"
+#define IQK_VER_8723D "0x02"
+#define IQK_VER_8822B "0x2f"
+#define IQK_VER_8821C "0x23"
+#define IQK_VER_8198F "0x06"
+
+/*LCK version*/
+#define LCK_VER_8188E "0x01"
+#define LCK_VER_8192E "0x01"
+#define LCK_VER_8192F "0x01"
+#define LCK_VER_8723B "0x01"
+#define LCK_VER_8812A "0x01"
+#define LCK_VER_8821A "0x01"
+#define LCK_VER_8814A "0x01"
+#define LCK_VER_8188F "0x01"
+#define LCK_VER_8197F "0x01"
+#define LCK_VER_8703B "0x01"
+#define LCK_VER_8710B "0x01"
+#define LCK_VER_8723D "0x01"
+#define LCK_VER_8822B "0x01"
+#define LCK_VER_8821C "0x02"
+
+/*power tracking version*/
+#define PWRTRK_VER_8188E "0x01"
+#define PWRTRK_VER_8192E "0x01"
+#define PWRTRK_VER_8192F "0x01"
+#define PWRTRK_VER_8723B "0x01"
+#define PWRTRK_VER_8812A "0x01"
+#define PWRTRK_VER_8821A "0x01"
+#define PWRTRK_VER_8814A "0x01"
+#define PWRTRK_VER_8188F "0x01"
+#define PWRTRK_VER_8197F "0x01"
+#define PWRTRK_VER_8703B "0x01"
+#define PWRTRK_VER_8710B "0x01"
+#define PWRTRK_VER_8723D "0x01"
+#define PWRTRK_VER_8822B "0x01"
+#define PWRTRK_VER_8821C "0x01"
+
+/*DPK tracking version*/
+#define DPK_VER_8188E "NONE"
+#define DPK_VER_8192E "NONE"
+#define DPK_VER_8723B "NONE"
+#define DPK_VER_8812A "NONE"
+#define DPK_VER_8821A "NONE"
+#define DPK_VER_8814A "NONE"
+#define DPK_VER_8188F "NONE"
+#define DPK_VER_8197F "0x07"
+#define DPK_VER_8703B "NONE"
+#define DPK_VER_8710B "NONE"
+#define DPK_VER_8723D "NONE"
+#define DPK_VER_8822B "NONE"
+#define DPK_VER_8821C "NONE"
+#define DPK_VER_8192F "0x0a"
+#define DPK_VER_8198F "0x06"
+
+/*RFK_INIT version*/
+#define RFK_INIT_VER_8822B "0x8"
+#define RFK_INIT_VER_8195B "0x1"
+#define RFK_INIT_VER_8198F "0x5"
+
+/*Kfree tracking version*/
+#define KFREE_VER_8188E \
+		(dm->power_trim_data.flag & KFREE_FLAG_ON) ? "0x01" : "NONE"
+#define KFREE_VER_8192E \
+		(dm->power_trim_data.flag & KFREE_FLAG_ON) ? "0x01" : "NONE"
+#define KFREE_VER_8192F \
+		(dm->power_trim_data.flag & KFREE_FLAG_ON) ? "0x01" : "NONE"
+#define KFREE_VER_8723B \
+		(dm->power_trim_data.flag & KFREE_FLAG_ON) ? "0x01" : "NONE"
+#define KFREE_VER_8812A \
+		(dm->power_trim_data.flag & KFREE_FLAG_ON) ? "0x01" : "NONE"
+#define KFREE_VER_8821A \
+		(dm->power_trim_data.flag & KFREE_FLAG_ON) ? "0x01" : "NONE"
+#define KFREE_VER_8814A \
+		(dm->power_trim_data.flag & KFREE_FLAG_ON) ? "0x01" : "NONE"
+#define KFREE_VER_8188F \
+		(dm->power_trim_data.flag & KFREE_FLAG_ON) ? "0x01" : "NONE"
+#define KFREE_VER_8197F \
+		(dm->power_trim_data.flag & KFREE_FLAG_ON) ? "0x01" : "NONE"
+#define KFREE_VER_8703B \
+		(dm->power_trim_data.flag & KFREE_FLAG_ON) ? "0x01" : "NONE"
+#define KFREE_VER_8710B \
+		(dm->power_trim_data.flag & KFREE_FLAG_ON) ? "0x01" : "NONE"
+#define KFREE_VER_8723D \
+		(dm->power_trim_data.flag & KFREE_FLAG_ON) ? "0x01" : "NONE"
+#define KFREE_VER_8822B \
+		(dm->power_trim_data.flag & KFREE_FLAG_ON) ? "0x01" : "NONE"
+#define KFREE_VER_8821C \
+		(dm->power_trim_data.flag & KFREE_FLAG_ON) ? "0x01" : "NONE"
+
+/*PA Bias Calibration version*/
+#define PABIASK_VER_8188E \
+	(dm->power_trim_data.pa_bias_flag & PA_BIAS_FLAG_ON) ? "0x01" : "NONE"
+#define PABIASK_VER_8192E \
+	(dm->power_trim_data.pa_bias_flag & PA_BIAS_FLAG_ON) ? "0x01" : "NONE"
+#define PABIASK_VER_8192F \
+	(dm->power_trim_data.pa_bias_flag & PA_BIAS_FLAG_ON) ? "0x01" : "NONE"
+#define PABIASK_VER_8723B \
+	(dm->power_trim_data.pa_bias_flag & PA_BIAS_FLAG_ON) ? "0x01" : "NONE"
+#define PABIASK_VER_8812A \
+	(dm->power_trim_data.pa_bias_flag & PA_BIAS_FLAG_ON) ? "0x01" : "NONE"
+#define PABIASK_VER_8821A \
+	(dm->power_trim_data.pa_bias_flag & PA_BIAS_FLAG_ON) ? "0x01" : "NONE"
+#define PABIASK_VER_8814A \
+	(dm->power_trim_data.pa_bias_flag & PA_BIAS_FLAG_ON) ? "0x01" : "NONE"
+#define PABIASK_VER_8188F \
+	(dm->power_trim_data.pa_bias_flag & PA_BIAS_FLAG_ON) ? "0x01" : "NONE"
+#define PABIASK_VER_8197F \
+	(dm->power_trim_data.pa_bias_flag & PA_BIAS_FLAG_ON) ? "0x01" : "NONE"
+#define PABIASK_VER_8703B \
+	(dm->power_trim_data.pa_bias_flag & PA_BIAS_FLAG_ON) ? "0x01" : "NONE"
+#define PABIASK_VER_8710B \
+	(dm->power_trim_data.pa_bias_flag & PA_BIAS_FLAG_ON) ? "0x01" : "NONE"
+#define PABIASK_VER_8723D \
+	(dm->power_trim_data.pa_bias_flag & PA_BIAS_FLAG_ON) ? "0x01" : "NONE"
+#define PABIASK_VER_8822B \
+	(dm->power_trim_data.pa_bias_flag & PA_BIAS_FLAG_ON) ? "0x01" : "NONE"
+#define PABIASK_VER_8821C \
+	(dm->power_trim_data.pa_bias_flag & PA_BIAS_FLAG_ON) ? "0x01" : "NONE"
+
+#define HALRF_IQK_VER \
+	(dm->support_ic_type == ODM_RTL8188E) ? IQK_VER_8188E : \
+	(dm->support_ic_type == ODM_RTL8192E) ? IQK_VER_8192E : \
+	(dm->support_ic_type == ODM_RTL8192F) ? IQK_VER_8192F : \
+	(dm->support_ic_type == ODM_RTL8723B) ? IQK_VER_8723B : \
+	(dm->support_ic_type == ODM_RTL8812) ? IQK_VER_8812A : \
+	(dm->support_ic_type == ODM_RTL8821) ? IQK_VER_8821A : \
+	(dm->support_ic_type == ODM_RTL8814A) ? IQK_VER_8814A : \
+	(dm->support_ic_type == ODM_RTL8188F) ? IQK_VER_8188F : \
+	(dm->support_ic_type == ODM_RTL8197F) ? IQK_VER_8197F : \
+	(dm->support_ic_type == ODM_RTL8703B) ? IQK_VER_8703B : \
+	(dm->support_ic_type == ODM_RTL8710B) ? IQK_VER_8710B : \
+	(dm->support_ic_type == ODM_RTL8723D) ? IQK_VER_8723D : \
+	(dm->support_ic_type == ODM_RTL8822B) ? IQK_VER_8822B : \
+	(dm->support_ic_type == ODM_RTL8821C) ? IQK_VER_8821C : "unknown"
+
+#define HALRF_LCK_VER \
+	(dm->support_ic_type == ODM_RTL8188E) ? LCK_VER_8188E : \
+	(dm->support_ic_type == ODM_RTL8192E) ? LCK_VER_8192E : \
+	(dm->support_ic_type == ODM_RTL8192F) ? LCK_VER_8192F : \
+	(dm->support_ic_type == ODM_RTL8723B) ? LCK_VER_8723B : \
+	(dm->support_ic_type == ODM_RTL8812) ? LCK_VER_8812A : \
+	(dm->support_ic_type == ODM_RTL8821) ? LCK_VER_8821A : \
+	(dm->support_ic_type == ODM_RTL8814A) ? LCK_VER_8814A : \
+	(dm->support_ic_type == ODM_RTL8188F) ? LCK_VER_8188F : \
+	(dm->support_ic_type == ODM_RTL8197F) ? LCK_VER_8197F : \
+	(dm->support_ic_type == ODM_RTL8703B) ? LCK_VER_8703B : \
+	(dm->support_ic_type == ODM_RTL8710B) ? LCK_VER_8710B : \
+	(dm->support_ic_type == ODM_RTL8723D) ? LCK_VER_8723D : \
+	(dm->support_ic_type == ODM_RTL8822B) ? LCK_VER_8822B : \
+	(dm->support_ic_type == ODM_RTL8821C) ? LCK_VER_8821C : "unknown"
+
+#define HALRF_POWRTRACKING_VER \
+	(dm->support_ic_type == ODM_RTL8188E) ? PWRTRK_VER_8188E : \
+	(dm->support_ic_type == ODM_RTL8192E) ? PWRTRK_VER_8192E : \
+	(dm->support_ic_type == ODM_RTL8192F) ? PWRTRK_VER_8192F : \
+	(dm->support_ic_type == ODM_RTL8723B) ? PWRTRK_VER_8723B : \
+	(dm->support_ic_type == ODM_RTL8812) ? PWRTRK_VER_8812A : \
+	(dm->support_ic_type == ODM_RTL8821) ? PWRTRK_VER_8821A : \
+	(dm->support_ic_type == ODM_RTL8814A) ? PWRTRK_VER_8814A : \
+	(dm->support_ic_type == ODM_RTL8188F) ? PWRTRK_VER_8188F : \
+	(dm->support_ic_type == ODM_RTL8197F) ? PWRTRK_VER_8197F : \
+	(dm->support_ic_type == ODM_RTL8703B) ? PWRTRK_VER_8703B : \
+	(dm->support_ic_type == ODM_RTL8710B) ? PWRTRK_VER_8710B : \
+	(dm->support_ic_type == ODM_RTL8723D) ? PWRTRK_VER_8723D : \
+	(dm->support_ic_type == ODM_RTL8822B) ? PWRTRK_VER_8822B : \
+	(dm->support_ic_type == ODM_RTL8821C) ? PWRTRK_VER_8821C : "unknown"
+
+#define HALRF_DPK_VER \
+	(dm->support_ic_type == ODM_RTL8188E) ? DPK_VER_8188E : \
+	(dm->support_ic_type == ODM_RTL8192E) ? DPK_VER_8192E : \
+	(dm->support_ic_type == ODM_RTL8192F) ? DPK_VER_8192F : \
+	(dm->support_ic_type == ODM_RTL8723B) ? DPK_VER_8723B : \
+	(dm->support_ic_type == ODM_RTL8812) ? DPK_VER_8812A : \
+	(dm->support_ic_type == ODM_RTL8821) ? DPK_VER_8821A : \
+	(dm->support_ic_type == ODM_RTL8814A) ? DPK_VER_8814A : \
+	(dm->support_ic_type == ODM_RTL8188F) ? DPK_VER_8188F : \
+	(dm->support_ic_type == ODM_RTL8197F) ? DPK_VER_8197F : \
+	(dm->support_ic_type == ODM_RTL8198F) ? DPK_VER_8198F : \
+	(dm->support_ic_type == ODM_RTL8703B) ? DPK_VER_8703B : \
+	(dm->support_ic_type == ODM_RTL8710B) ? DPK_VER_8710B : \
+	(dm->support_ic_type == ODM_RTL8723D) ? DPK_VER_8723D : \
+	(dm->support_ic_type == ODM_RTL8822B) ? DPK_VER_8822B : \
+	(dm->support_ic_type == ODM_RTL8821C) ? DPK_VER_8821C : "unknown"
+
+#define HALRF_KFREE_VER \
+	(dm->support_ic_type == ODM_RTL8188E) ? KFREE_VER_8188E : \
+	(dm->support_ic_type == ODM_RTL8192E) ? KFREE_VER_8192E : \
+	(dm->support_ic_type == ODM_RTL8192F) ? KFREE_VER_8192F : \
+	(dm->support_ic_type == ODM_RTL8723B) ? KFREE_VER_8723B : \
+	(dm->support_ic_type == ODM_RTL8812) ? KFREE_VER_8812A : \
+	(dm->support_ic_type == ODM_RTL8821) ? KFREE_VER_8821A : \
+	(dm->support_ic_type == ODM_RTL8814A) ? KFREE_VER_8814A : \
+	(dm->support_ic_type == ODM_RTL8188F) ? KFREE_VER_8188F : \
+	(dm->support_ic_type == ODM_RTL8197F) ? KFREE_VER_8197F : \
+	(dm->support_ic_type == ODM_RTL8703B) ? KFREE_VER_8703B : \
+	(dm->support_ic_type == ODM_RTL8710B) ? KFREE_VER_8710B : \
+	(dm->support_ic_type == ODM_RTL8723D) ? KFREE_VER_8723D : \
+	(dm->support_ic_type == ODM_RTL8822B) ? KFREE_VER_8822B : \
+	(dm->support_ic_type == ODM_RTL8821C) ? KFREE_VER_8821C : "unknown"
+
+#define HALRF_PABIASK_VER \
+	(dm->support_ic_type == ODM_RTL8188E) ? PABIASK_VER_8188E : \
+	(dm->support_ic_type == ODM_RTL8192E) ? PABIASK_VER_8192E : \
+	(dm->support_ic_type == ODM_RTL8192F) ? PABIASK_VER_8192F : \
+	(dm->support_ic_type == ODM_RTL8723B) ? PABIASK_VER_8723B : \
+	(dm->support_ic_type == ODM_RTL8812) ? PABIASK_VER_8812A : \
+	(dm->support_ic_type == ODM_RTL8821) ? PABIASK_VER_8821A : \
+	(dm->support_ic_type == ODM_RTL8814A) ? PABIASK_VER_8814A : \
+	(dm->support_ic_type == ODM_RTL8188F) ? PABIASK_VER_8188F : \
+	(dm->support_ic_type == ODM_RTL8197F) ? PABIASK_VER_8197F : \
+	(dm->support_ic_type == ODM_RTL8703B) ? PABIASK_VER_8703B : \
+	(dm->support_ic_type == ODM_RTL8710B) ? PABIASK_VER_8710B : \
+	(dm->support_ic_type == ODM_RTL8723D) ? PABIASK_VER_8723D : \
+	(dm->support_ic_type == ODM_RTL8822B) ? PABIASK_VER_8822B : \
+	(dm->support_ic_type == ODM_RTL8821C) ? PABIASK_VER_8821C : "unknown"
+
+#define HALRF_RFK_INIT_VER \
+	(dm->support_ic_type == ODM_RTL8822B) ? RFK_INIT_VER_8822B : "unknown"
+
+#define IQK_THRESHOLD 8
+#define DPK_THRESHOLD 4
+
+/*===========================================================*/
+/*AGC RX High Power mode*/
+/*===========================================================*/
+#define lna_low_gain_1 0x64
+#define lna_low_gain_2 0x5A
+#define lna_low_gain_3 0x58
+
+/*============================================================*/
+/* enumeration */
+/*============================================================*/
+
+enum halrf_func_idx { /*F_XXX = PHYDM XXX function*/
+	RF00_PWR_TRK = 0,
+	RF01_IQK = 1,
+	RF02_LCK = 2,
+	RF03_DPK = 3,
+	RF04_TXGAPK = 4,
+};
+
+enum halrf_ability {
+	HAL_RF_TX_PWR_TRACK = BIT(RF00_PWR_TRK),
+	HAL_RF_IQK = BIT(RF01_IQK),
+	HAL_RF_LCK = BIT(RF02_LCK),
+	HAL_RF_DPK = BIT(RF03_DPK),
+	HAL_RF_TXGAPK = BIT(RF04_TXGAPK)
+};
+
+enum halrf_dbg_comp {
+	DBG_RF_TX_PWR_TRACK = BIT(RF00_PWR_TRK),
+	DBG_RF_IQK = BIT(RF01_IQK),
+	DBG_RF_LCK = BIT(RF02_LCK),
+	DBG_RF_DPK = BIT(RF03_DPK),
+	DBG_RF_TXGAPK = BIT(RF04_TXGAPK),
+	DBG_RF_MP = BIT(29),
+	DBG_RF_TMP = BIT(30),
+	DBG_RF_INIT = BIT(31)
+};
+
+enum halrf_cmninfo_init {
+	HALRF_CMNINFO_ABILITY = 0,
+	HALRF_CMNINFO_DPK_EN = 1,
+	HALRF_CMNINFO_EEPROM_THERMAL_VALUE,
+	HALRF_CMNINFO_RFK_FORBIDDEN,
+	HALRF_CMNINFO_IQK_SEGMENT,
+	HALRF_CMNINFO_RATE_INDEX,
+	HALRF_CMNINFO_PWT_TYPE,
+	HALRF_CMNINFO_MP_PSD_POINT,
+	HALRF_CMNINFO_MP_PSD_START_POINT,
+	HALRF_CMNINFO_MP_PSD_STOP_POINT,
+	HALRF_CMNINFO_MP_PSD_AVERAGE
+};
+
+enum halrf_cmninfo_hook {
+	HALRF_CMNINFO_CON_TX,
+	HALRF_CMNINFO_SINGLE_TONE,
+	HALRF_CMNINFO_CARRIER_SUPPRESSION,
+	HALRF_CMNINFO_MP_RATE_INDEX
+};
+
+enum halrf_lna_set {
+	HALRF_LNA_DISABLE = 0,
+	HALRF_LNA_ENABLE = 1,
+};
+
+/*============================================================*/
+/* structure */
+/*============================================================*/
+
+struct _hal_rf_ {
+	/*hook*/
+	u8 *test1;
+
+	/*update*/
+	u32 rf_supportability;
+
+	u8 eeprom_thermal;
+	u8 dpk_en; /*Enable Function DPK OFF/ON = 0/1*/
+	boolean dpk_done;
+	u64 dpk_progressing_time;
+	u32 fw_ver;
+
+	boolean *is_con_tx;
+	boolean *is_single_tone;
+	boolean *is_carrier_suppresion;
+	boolean aac_checked;
+
+	u8 *mp_rate_index;
+	u32 p_rate_index;
+	u8 pwt_type;
+	u32 rf_dbg_comp;
+#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
+	struct _halrf_psd_data halrf_psd_data;
+#endif
+};
+
+/*============================================================*/
+/* function prototype */
+/*============================================================*/
+
+#if (RTL8822B_SUPPORT == 1 || RTL8821C_SUPPORT == 1 ||\
+	RTL8195B_SUPPORT == 1 || RTL8198F_SUPPORT == 1)
+void halrf_iqk_info_dump(void *dm_void, u32 *_used, char *output,
+			 u32 *_out_len);
+
+void halrf_iqk_hwtx_check(void *dm_void, boolean is_check);
+#endif
+
+u8 halrf_match_iqk_version(void *dm_void);
+
+void halrf_support_ability_debug(void *dm_void, char input[][16], u32 *_used,
+				 char *output, u32 *_out_len);
+
+void halrf_cmn_info_init(void *dm_void, enum halrf_cmninfo_init cmn_info,
+			 u32 value);
+
+void halrf_cmn_info_hook(void *dm_void, enum halrf_cmninfo_hook cmn_info,
+			 void *value);
+
+void halrf_cmn_info_set(void *dm_void, u32 cmn_info, u64 value);
+
+u64 halrf_cmn_info_get(void *dm_void, u32 cmn_info);
+
+void halrf_watchdog(void *dm_void);
+
+void halrf_supportability_init(void *dm_void);
+
+void halrf_init(void *dm_void);
+
+void halrf_iqk_trigger(void *dm_void, boolean is_recovery);
+
+void halrf_segment_iqk_trigger(void *dm_void, boolean clear,
+			       boolean segment_iqk);
+
+void halrf_lck_trigger(void *dm_void);
+
+void halrf_iqk_debug(void *dm_void, u32 *const dm_value, u32 *_used,
+		     char *output, u32 *_out_len);
+
+void phydm_get_iqk_cfir(void *dm_void, u8 idx, u8 path, boolean debug);
+
+void halrf_iqk_xym_read(void *dm_void, u8 path, u8 xym_type);
+
+void halrf_rf_lna_setting(void *dm_void, enum halrf_lna_set type);
+
+void halrf_do_imr_test(void *dm_void, u8 data);
+
+u32 halrf_psd_log2base(u32 val);
+
+void halrf_dpk_trigger(void *dm_void);
+
+u8 halrf_dpk_result_check(void *dm_void);
+
+void halrf_dpk_sram_read(void *dm_void);
+
+void halrf_dpk_enable_disable(void *dm_void);
+
+void halrf_dpk_track(void *dm_void);
+
+void halrf_dpk_reload(void *dm_void);
+
+enum hal_status
+halrf_config_rfk_with_header_file(void *dm_void, u32 config_type);
+
+#if (RTL8822B_SUPPORT == 1 || RTL8821C_SUPPORT == 1 ||\
+	RTL8195B_SUPPORT == 1 || RTL8198F_SUPPORT == 1)
+void halrf_iqk_dbg(void *dm_void);
+#endif
+
+#endif /*#ifndef __HALRF_H__*/
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/halrf/halrf_iqk.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/halrf/halrf_iqk.h
--- linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/halrf/halrf_iqk.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/halrf/halrf_iqk.h	2020-04-10 16:35:06.819660208 +0300
@@ -0,0 +1,92 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017  Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * The full GNU General Public License is included in this distribution in the
+ * file called LICENSE.
+ *
+ * Contact Information:
+ * wlanfae <wlanfae@realtek.com>
+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
+ * Hsinchu 300, Taiwan.
+ *
+ * Larry Finger <Larry.Finger@lwfinger.net>
+ *
+ *****************************************************************************/
+
+#ifndef __HALRF_IQK_H__
+#define __HALRF_IQK_H__
+
+/*--------------------------Define Parameters-------------------------------*/
+#define LOK_delay 1
+#define WBIQK_delay 10
+#define TX_IQK 0
+#define RX_IQK 1
+#define TXIQK 0
+#define RXIQK1 1
+#define RXIQK2 2
+#define kcount_limit_80m 2
+#define kcount_limit_others 4
+#define rxiqk_gs_limit 10
+
+#define NUM 4
+/*-----------------------End Define Parameters-----------------------*/
+
+struct dm_iqk_info {
+	boolean lok_fail[NUM];
+	boolean iqk_fail[2][NUM];
+	u32 iqc_matrix[2][NUM];
+	u8 iqk_times;
+	u32 rf_reg18;
+	u32 rf_reg08;
+	u32 lna_idx;
+	u8 iqk_step;
+	u8 rxiqk_step;
+	u8 tmp1bcc;
+	u8 kcount;
+	u8 rfk_ing; /*bit0:IQKing, bit1:LCKing, bit2:DPKing*/
+	boolean rfk_forbidden;
+#if (RTL8814A_SUPPORT == 1 || RTL8822B_SUPPORT == 1 || RTL8821C_SUPPORT == 1 ||\
+	RTL8195B_SUPPORT == 1 || RTL8198F_SUPPORT == 1)
+	u32 iqk_channel[2];
+	boolean iqk_fail_report[2][4][2]; /*channel/path/TRX(TX:0, RX:1) */
+	/*channel / path / TRX(TX:0, RX:1) / CFIR_real*/
+	/*channel index = 2 is just for debug*/
+	u32 iqk_cfir_real[3][4][2][8];
+	/*channel / path / TRX(TX:0, RX:1) / CFIR_imag*/
+	/*channel index = 2 is just for debug*/
+	u32 iqk_cfir_imag[3][4][2][8];
+	u8 retry_count[2][4][3]; /* channel / path / (TXK:0, RXK1:1, RXK2:2) */
+	u8 gs_retry_count[2][4][2]; /* channel / path / (GSRXK1:0, GSRXK2:1) */
+	/* channel / path 0:SRXK1 fail, 1:RXK1 fail 2:RXK2 fail */
+	u8 rxiqk_fail_code[2][4];
+	u32 lok_idac[2][4]; /*channel / path*/
+	u16 rxiqk_agc[2][4]; /*channel / path*/
+	u32 bypass_iqk[2][4]; /*channel / 0xc94/0xe94*/
+	u32 txgap_result[8]; /*txagpK result  */
+	u32 tmp_gntwl;
+	boolean is_btg;
+	boolean isbnd;
+	boolean is_reload;
+	boolean segment_iqk;
+	boolean is_hwtx;
+	boolean xym_read;
+	boolean trximr_enable;
+	u32 rx_xym[2][10];
+	u32 tx_xym[2][10];
+	u32 gs1_xym[2][6];
+	u32 gs2_xym[2][6];
+	u32 rxk1_xym[2][6];
+#endif
+};
+
+#endif /*#ifndef __HALRF_IQK_H__*/
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/halrf/halrf_kfree.c linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/halrf/halrf_kfree.c
--- linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/halrf/halrf_kfree.c	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/halrf/halrf_kfree.c	2020-04-10 16:35:06.819660208 +0300
@@ -0,0 +1,1013 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017  Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * The full GNU General Public License is included in this distribution in the
+ * file called LICENSE.
+ *
+ * Contact Information:
+ * wlanfae <wlanfae@realtek.com>
+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
+ * Hsinchu 300, Taiwan.
+ *
+ * Larry Finger <Larry.Finger@lwfinger.net>
+ *
+ *****************************************************************************/
+
+/*============================================================*/
+/*include files*/
+/*============================================================*/
+#include "mp_precomp.h"
+#include "phydm_precomp.h"
+
+/*<YuChen, 150720> Add for KFree Feature Requested by RF David.*/
+/*This is a phydm API*/
+
+void phydm_set_kfree_to_rf_8814a(void *dm_void, u8 e_rf_path, u8 data)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct dm_rf_calibration_struct *cali_info = &dm->rf_calibrate_info;
+	boolean is_odd;
+	u32 tx_gain_bitmask = (BIT(17) | BIT(16) | BIT(15));
+
+	if ((data % 2) != 0) { /*odd->positive*/
+		data = data - 1;
+		odm_set_rf_reg(dm, e_rf_path, RF_0x55, BIT(19), 1);
+		is_odd = true;
+	} else { /*even->negative*/
+		odm_set_rf_reg(dm, e_rf_path, RF_0x55, BIT(19), 0);
+		is_odd = false;
+	}
+	RF_DBG(dm, DBG_RF_MP, "phy_ConfigKFree8814A(): RF_0x55[19]= %d\n",
+	       is_odd);
+	switch (data) {
+	case 0:
+		odm_set_rf_reg(dm, e_rf_path, RF_0x55, BIT(14), 0);
+		odm_set_rf_reg(dm, e_rf_path, RF_0x55, tx_gain_bitmask, 0);
+		cali_info->kfree_offset[e_rf_path] = 0;
+		break;
+	case 2:
+		odm_set_rf_reg(dm, e_rf_path, RF_0x55, BIT(14), 1);
+		odm_set_rf_reg(dm, e_rf_path, RF_0x55, tx_gain_bitmask, 0);
+		cali_info->kfree_offset[e_rf_path] = 0;
+		break;
+	case 4:
+		odm_set_rf_reg(dm, e_rf_path, RF_0x55, BIT(14), 0);
+		odm_set_rf_reg(dm, e_rf_path, RF_0x55, tx_gain_bitmask, 1);
+		cali_info->kfree_offset[e_rf_path] = 1;
+		break;
+	case 6:
+		odm_set_rf_reg(dm, e_rf_path, RF_0x55, BIT(14), 1);
+		odm_set_rf_reg(dm, e_rf_path, RF_0x55, tx_gain_bitmask, 1);
+		cali_info->kfree_offset[e_rf_path] = 1;
+		break;
+	case 8:
+		odm_set_rf_reg(dm, e_rf_path, RF_0x55, BIT(14), 0);
+		odm_set_rf_reg(dm, e_rf_path, RF_0x55, tx_gain_bitmask, 2);
+		cali_info->kfree_offset[e_rf_path] = 2;
+		break;
+	case 10:
+		odm_set_rf_reg(dm, e_rf_path, RF_0x55, BIT(14), 1);
+		odm_set_rf_reg(dm, e_rf_path, RF_0x55, tx_gain_bitmask, 2);
+		cali_info->kfree_offset[e_rf_path] = 2;
+		break;
+	case 12:
+		odm_set_rf_reg(dm, e_rf_path, RF_0x55, BIT(14), 0);
+		odm_set_rf_reg(dm, e_rf_path, RF_0x55, tx_gain_bitmask, 3);
+		cali_info->kfree_offset[e_rf_path] = 3;
+		break;
+	case 14:
+		odm_set_rf_reg(dm, e_rf_path, RF_0x55, BIT(14), 1);
+		odm_set_rf_reg(dm, e_rf_path, RF_0x55, tx_gain_bitmask, 3);
+		cali_info->kfree_offset[e_rf_path] = 3;
+		break;
+	case 16:
+		odm_set_rf_reg(dm, e_rf_path, RF_0x55, BIT(14), 0);
+		odm_set_rf_reg(dm, e_rf_path, RF_0x55, tx_gain_bitmask, 4);
+		cali_info->kfree_offset[e_rf_path] = 4;
+		break;
+	case 18:
+		odm_set_rf_reg(dm, e_rf_path, RF_0x55, BIT(14), 1);
+		odm_set_rf_reg(dm, e_rf_path, RF_0x55, tx_gain_bitmask, 4);
+		cali_info->kfree_offset[e_rf_path] = 4;
+		break;
+	case 20:
+		odm_set_rf_reg(dm, e_rf_path, RF_0x55, BIT(14), 0);
+		odm_set_rf_reg(dm, e_rf_path, RF_0x55, tx_gain_bitmask, 5);
+		cali_info->kfree_offset[e_rf_path] = 5;
+		break;
+
+	default:
+		break;
+	}
+
+	if (!is_odd) {
+		/*that means Kfree offset is negative, we need to record it.*/
+		cali_info->kfree_offset[e_rf_path] =
+				(-1) * cali_info->kfree_offset[e_rf_path];
+		RF_DBG(dm, DBG_RF_MP,
+		       "phy_ConfigKFree8814A(): kfree_offset = %d\n",
+		       cali_info->kfree_offset[e_rf_path]);
+	} else {
+		RF_DBG(dm, DBG_RF_MP,
+		       "phy_ConfigKFree8814A(): kfree_offset = %d\n",
+		       cali_info->kfree_offset[e_rf_path]);
+	}
+}
+
+void phydm_get_thermal_trim_offset_8821c(void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct odm_power_trim_data *power_trim_info = &dm->power_trim_data;
+
+	u8 pg_therm = 0xff;
+
+	odm_efuse_one_byte_read(dm, PPG_THERMAL_OFFSET_21C, &pg_therm, false);
+
+	if (pg_therm != 0xff) {
+		pg_therm = pg_therm & 0x1f;
+		if ((pg_therm & BIT(0)) == 0)
+			power_trim_info->thermal = (-1 * (pg_therm >> 1));
+		else
+			power_trim_info->thermal = (pg_therm >> 1);
+
+		power_trim_info->flag |= KFREE_FLAG_THERMAL_K_ON;
+	}
+
+	RF_DBG(dm, DBG_RF_MP, "[kfree] 8821c thermal trim flag:0x%02x\n",
+	       power_trim_info->flag);
+
+	if (power_trim_info->flag & KFREE_FLAG_THERMAL_K_ON)
+		RF_DBG(dm, DBG_RF_MP, "[kfree] 8821c thermal:%d\n",
+		       power_trim_info->thermal);
+}
+
+void phydm_get_power_trim_offset_8821c(void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct odm_power_trim_data *power_trim_info = &dm->power_trim_data;
+
+	u8 pg_power = 0xff, i;
+
+	odm_efuse_one_byte_read(dm, PPG_2G_TXAB_21C, &pg_power, false);
+
+	if (pg_power != 0xff) {
+		power_trim_info->bb_gain[0][0] = pg_power;
+		odm_efuse_one_byte_read(dm, PPG_5GL1_TXA_21C, &pg_power, false);
+		power_trim_info->bb_gain[1][0] = pg_power;
+		odm_efuse_one_byte_read(dm, PPG_5GL2_TXA_21C, &pg_power, false);
+		power_trim_info->bb_gain[2][0] = pg_power;
+		odm_efuse_one_byte_read(dm, PPG_5GM1_TXA_21C, &pg_power, false);
+		power_trim_info->bb_gain[3][0] = pg_power;
+		odm_efuse_one_byte_read(dm, PPG_5GM2_TXA_21C, &pg_power, false);
+		power_trim_info->bb_gain[4][0] = pg_power;
+		odm_efuse_one_byte_read(dm, PPG_5GH1_TXA_21C, &pg_power, false);
+		power_trim_info->bb_gain[5][0] = pg_power;
+		power_trim_info->flag =
+			power_trim_info->flag | KFREE_FLAG_ON |
+			KFREE_FLAG_ON_2G | KFREE_FLAG_ON_5G;
+	}
+
+	RF_DBG(dm, DBG_RF_MP, "[kfree] 8821c power trim flag:0x%02x\n",
+	       power_trim_info->flag);
+
+	if (power_trim_info->flag & KFREE_FLAG_ON) {
+		for (i = 0; i < KFREE_BAND_NUM; i++)
+			RF_DBG(dm, DBG_RF_MP,
+			       "[kfree] 8821c pwr_trim->bb_gain[%d][0]=0x%X\n",
+			       i, power_trim_info->bb_gain[i][0]);
+	}
+}
+
+void phydm_set_kfree_to_rf_8821c(void *dm_void, u8 e_rf_path, boolean wlg_btg,
+				 u8 data)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	u8 wlg, btg;
+	u32 gain_bmask = (BIT(18) | BIT(17) | BIT(16) | BIT(15) | BIT(14));
+	u32 s_gain_bmask = (BIT(19) | BIT(18) | BIT(17) |
+			    BIT(16) | BIT(15) | BIT(14));
+
+	odm_set_rf_reg(dm, e_rf_path, RF_0xde, BIT(0), 1);
+	odm_set_rf_reg(dm, e_rf_path, RF_0xde, BIT(5), 1);
+	odm_set_rf_reg(dm, e_rf_path, RF_0x55, BIT(6), 1);
+	odm_set_rf_reg(dm, e_rf_path, RF_0x65, BIT(6), 1);
+
+	if (wlg_btg) {
+		wlg = data & 0xf;
+		btg = (data & 0xf0) >> 4;
+
+		odm_set_rf_reg(dm, e_rf_path, RF_0x55, BIT(19), (wlg & BIT(0)));
+		odm_set_rf_reg(dm, e_rf_path, RF_0x55, gain_bmask, (wlg >> 1));
+
+		odm_set_rf_reg(dm, e_rf_path, RF_0x65, BIT(19), (btg & BIT(0)));
+		odm_set_rf_reg(dm, e_rf_path, RF_0x65, gain_bmask, (btg >> 1));
+	} else {
+		odm_set_rf_reg(dm, e_rf_path, RF_0x55, BIT(19), data & BIT(0));
+		odm_set_rf_reg(dm, e_rf_path, RF_0x55, gain_bmask,
+			       ((data & 0x1f) >> 1));
+	}
+
+	RF_DBG(dm, DBG_RF_MP,
+	       "[kfree] 8821c 0x55[19:14]=0x%X 0x65[19:14]=0x%X\n",
+	       odm_get_rf_reg(dm, e_rf_path, RF_0x55, s_gain_bmask),
+	       odm_get_rf_reg(dm, e_rf_path, RF_0x65, s_gain_bmask));
+}
+
+void phydm_clear_kfree_to_rf_8821c(void *dm_void, u8 e_rf_path, u8 data)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	u32 gain_bmask = (BIT(18) | BIT(17) | BIT(16) | BIT(15) | BIT(14));
+	u32 s_gain_bmask = (BIT(19) | BIT(18) | BIT(17) |
+			    BIT(16) | BIT(15) | BIT(14));
+
+	odm_set_rf_reg(dm, e_rf_path, RF_0xde, BIT(0), 1);
+	odm_set_rf_reg(dm, e_rf_path, RF_0xde, BIT(5), 1);
+	odm_set_rf_reg(dm, e_rf_path, RF_0x55, BIT(6), 1);
+	odm_set_rf_reg(dm, e_rf_path, RF_0x65, BIT(6), 1);
+
+	odm_set_rf_reg(dm, e_rf_path, RF_0x55, BIT(19), (data & BIT(0)));
+	odm_set_rf_reg(dm, e_rf_path, RF_0x55, gain_bmask, (data >> 1));
+
+	odm_set_rf_reg(dm, e_rf_path, RF_0x65, BIT(19), (data & BIT(0)));
+	odm_set_rf_reg(dm, e_rf_path, RF_0x65, gain_bmask, (data >> 1));
+
+	odm_set_rf_reg(dm, e_rf_path, RF_0xde, BIT(0), 0);
+	odm_set_rf_reg(dm, e_rf_path, RF_0xde, BIT(5), 0);
+	odm_set_rf_reg(dm, e_rf_path, RF_0x55, BIT(6), 0);
+	odm_set_rf_reg(dm, e_rf_path, RF_0x65, BIT(6), 0);
+
+	RF_DBG(dm, DBG_RF_MP,
+	       "[kfree] 8821c 0x55[19:14]=0x%X 0x65[19:14]=0x%X\n",
+	       odm_get_rf_reg(dm, e_rf_path, RF_0x55, s_gain_bmask),
+	       odm_get_rf_reg(dm, e_rf_path, RF_0x65, s_gain_bmask));
+}
+
+void phydm_get_thermal_trim_offset_8822b(void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct odm_power_trim_data *power_trim_info = &dm->power_trim_data;
+
+	u8 pg_therm = 0xff;
+
+	odm_efuse_one_byte_read(dm, PPG_THERMAL_OFFSET_22B, &pg_therm, false);
+
+	if (pg_therm != 0xff) {
+		pg_therm = pg_therm & 0x1f;
+		if ((pg_therm & BIT(0)) == 0)
+			power_trim_info->thermal = (-1 * (pg_therm >> 1));
+		else
+			power_trim_info->thermal = (pg_therm >> 1);
+
+		power_trim_info->flag |= KFREE_FLAG_THERMAL_K_ON;
+	}
+
+	RF_DBG(dm, DBG_RF_MP, "[kfree] 8822b thermal trim flag:0x%02x\n",
+	       power_trim_info->flag);
+
+	if (power_trim_info->flag & KFREE_FLAG_THERMAL_K_ON)
+		RF_DBG(dm, DBG_RF_MP, "[kfree] 8822b thermal:%d\n",
+		       power_trim_info->thermal);
+}
+
+void phydm_get_power_trim_offset_8822b(void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct odm_power_trim_data *power_trim_info = &dm->power_trim_data;
+
+	u8 pg_power = 0xff, i, j;
+
+	odm_efuse_one_byte_read(dm, PPG_2G_TXAB_22B, &pg_power, false);
+
+	if (pg_power != 0xff) {
+		/*Path A*/
+		odm_efuse_one_byte_read(dm, PPG_2G_TXAB_22B, &pg_power, false);
+		power_trim_info->bb_gain[0][0] = (pg_power & 0xf);
+
+		/*Path B*/
+		odm_efuse_one_byte_read(dm, PPG_2G_TXAB_22B, &pg_power, false);
+		power_trim_info->bb_gain[0][1] = ((pg_power & 0xf0) >> 4);
+
+		power_trim_info->flag |= KFREE_FLAG_ON_2G;
+		power_trim_info->flag |= KFREE_FLAG_ON;
+	}
+
+	odm_efuse_one_byte_read(dm, PPG_5GL1_TXA_22B, &pg_power, false);
+
+	if (pg_power != 0xff) {
+		/*Path A*/
+		odm_efuse_one_byte_read(dm, PPG_5GL1_TXA_22B, &pg_power, false);
+		power_trim_info->bb_gain[1][0] = pg_power;
+		odm_efuse_one_byte_read(dm, PPG_5GL2_TXA_22B, &pg_power, false);
+		power_trim_info->bb_gain[2][0] = pg_power;
+		odm_efuse_one_byte_read(dm, PPG_5GM1_TXA_22B, &pg_power, false);
+		power_trim_info->bb_gain[3][0] = pg_power;
+		odm_efuse_one_byte_read(dm, PPG_5GM2_TXA_22B, &pg_power, false);
+		power_trim_info->bb_gain[4][0] = pg_power;
+		odm_efuse_one_byte_read(dm, PPG_5GH1_TXA_22B, &pg_power, false);
+		power_trim_info->bb_gain[5][0] = pg_power;
+
+		/*Path B*/
+		odm_efuse_one_byte_read(dm, PPG_5GL1_TXB_22B, &pg_power, false);
+		power_trim_info->bb_gain[1][1] = pg_power;
+		odm_efuse_one_byte_read(dm, PPG_5GL2_TXB_22B, &pg_power, false);
+		power_trim_info->bb_gain[2][1] = pg_power;
+		odm_efuse_one_byte_read(dm, PPG_5GM1_TXB_22B, &pg_power, false);
+		power_trim_info->bb_gain[3][1] = pg_power;
+		odm_efuse_one_byte_read(dm, PPG_5GM2_TXB_22B, &pg_power, false);
+		power_trim_info->bb_gain[4][1] = pg_power;
+		odm_efuse_one_byte_read(dm, PPG_5GH1_TXB_22B, &pg_power, false);
+		power_trim_info->bb_gain[5][1] = pg_power;
+
+		power_trim_info->flag |= KFREE_FLAG_ON_5G;
+		power_trim_info->flag |= KFREE_FLAG_ON;
+	}
+
+	RF_DBG(dm, DBG_RF_MP, "[kfree] 8822b power trim flag:0x%02x\n",
+	       power_trim_info->flag);
+
+	if (!(power_trim_info->flag & KFREE_FLAG_ON))
+		return;
+
+	for (i = 0; i < KFREE_BAND_NUM; i++) {
+		for (j = 0; j < 2; j++)
+			RF_DBG(dm, DBG_RF_MP,
+			       "[kfree] 8822b PwrTrim->bb_gain[%d][%d]=0x%X\n",
+			       i, j, power_trim_info->bb_gain[i][j]);
+	}
+}
+
+void phydm_set_pa_bias_to_rf_8822b(void *dm_void, u8 e_rf_path, s8 tx_pa_bias)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	u32 rf_reg_51 = 0, rf_reg_52 = 0, rf_reg_3f = 0;
+	u32 tx_pa_bias_bmask = (BIT(12) | BIT(11) | BIT(10) | BIT(9));
+
+	rf_reg_51 = odm_get_rf_reg(dm, e_rf_path, RF_0x51, RFREGOFFSETMASK);
+	rf_reg_52 = odm_get_rf_reg(dm, e_rf_path, RF_0x52, RFREGOFFSETMASK);
+
+	RF_DBG(dm, DBG_RF_MP,
+	       "[kfree] 8822b 2g rf(0x51)=0x%X rf(0x52)=0x%X path=%d\n",
+	       rf_reg_51, rf_reg_52, e_rf_path);
+
+#if 0
+	/*rf3f => rf52[19:17] = rf3f[2:0] rf52[16:15] = rf3f[4:3] rf52[3:0] = rf3f[8:5]*/
+	/*rf3f => rf51[6:3] = rf3f[12:9] rf52[13] = rf3f[13]*/
+#endif
+	rf_reg_3f = ((rf_reg_52 & 0xe0000) >> 17) |
+		    (((rf_reg_52 & 0x18000) >> 15) << 3) |
+		    ((rf_reg_52 & 0xf) << 5) |
+		    (((rf_reg_51 & 0x78) >> 3) << 9) |
+		    (((rf_reg_52 & 0x2000) >> 13) << 13);
+
+	RF_DBG(dm, DBG_RF_MP,
+	       "[kfree] 8822b 2g original pa_bias=%d rf_reg_3f=0x%X path=%d\n",
+	       tx_pa_bias, rf_reg_3f, e_rf_path);
+
+	tx_pa_bias = (s8)((rf_reg_3f & tx_pa_bias_bmask) >> 9) + tx_pa_bias;
+
+	if (tx_pa_bias < 0)
+		tx_pa_bias = 0;
+	else if (tx_pa_bias > 7)
+		tx_pa_bias = 7;
+
+	rf_reg_3f = ((rf_reg_3f & 0xfe1ff) | (tx_pa_bias << 9));
+
+	RF_DBG(dm, DBG_RF_MP,
+	       "[kfree] 8822b 2g 0x%X 0x%X pa_bias=%d rfreg_3f=0x%X path=%d\n",
+	       PPG_PABIAS_2GA_22B, PPG_PABIAS_2GB_22B,
+	       tx_pa_bias, rf_reg_3f, e_rf_path);
+
+	odm_set_rf_reg(dm, e_rf_path, RF_0xef, BIT(10), 0x1);
+	odm_set_rf_reg(dm, e_rf_path, RF_0x33, RFREGOFFSETMASK, 0x0);
+	odm_set_rf_reg(dm, e_rf_path, RF_0x3f, RFREGOFFSETMASK, rf_reg_3f);
+	odm_set_rf_reg(dm, e_rf_path, RF_0x33, BIT(0), 0x1);
+	odm_set_rf_reg(dm, e_rf_path, RF_0x3f, RFREGOFFSETMASK, rf_reg_3f);
+	odm_set_rf_reg(dm, e_rf_path, RF_0x33, BIT(1), 0x1);
+	odm_set_rf_reg(dm, e_rf_path, RF_0x3f, RFREGOFFSETMASK, rf_reg_3f);
+	odm_set_rf_reg(dm, e_rf_path, RF_0x33, (BIT(1) | BIT(0)), 0x3);
+	odm_set_rf_reg(dm, e_rf_path, RF_0x3f, RFREGOFFSETMASK, rf_reg_3f);
+	odm_set_rf_reg(dm, e_rf_path, RF_0xef, BIT(10), 0x0);
+
+	RF_DBG(dm, DBG_RF_MP,
+	       "[kfree] 8822b 2g tx pa bias rf_0x3f(0x%X) path=%d\n",
+	       odm_get_rf_reg(dm, e_rf_path, RF_0x3f,
+			      (BIT(12) | BIT(11) | BIT(10) | BIT(9))),
+			      e_rf_path);
+}
+
+void phydm_get_pa_bias_offset_8822b(void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct odm_power_trim_data *power_trim_info = &dm->power_trim_data;
+
+	u8 pg_pa_bias = 0xff, e_rf_path = 0;
+	s8 tx_pa_bias[2] = {0};
+
+	odm_efuse_one_byte_read(dm, PPG_PABIAS_2GA_22B, &pg_pa_bias, false);
+
+	if (pg_pa_bias != 0xff) {
+		/*paht a*/
+		odm_efuse_one_byte_read(dm, PPG_PABIAS_2GA_22B,
+					&pg_pa_bias, false);
+		pg_pa_bias = pg_pa_bias & 0xf;
+
+		if ((pg_pa_bias & BIT(0)) == 0)
+			tx_pa_bias[0] = (-1 * (pg_pa_bias >> 1));
+		else
+			tx_pa_bias[0] = (pg_pa_bias >> 1);
+
+		/*paht b*/
+		odm_efuse_one_byte_read(dm, PPG_PABIAS_2GB_22B,
+					&pg_pa_bias, false);
+		pg_pa_bias = pg_pa_bias & 0xf;
+
+		if ((pg_pa_bias & BIT(0)) == 0)
+			tx_pa_bias[1] = (-1 * (pg_pa_bias >> 1));
+		else
+			tx_pa_bias[1] = (pg_pa_bias >> 1);
+
+		RF_DBG(dm, DBG_RF_MP,
+		       "[kfree] 8822b 2g PathA_pa_bias:%d PathB_pa_bias:%d\n",
+		       tx_pa_bias[0], tx_pa_bias[1]);
+
+		for (e_rf_path = RF_PATH_A; e_rf_path < 2; e_rf_path++)
+			phydm_set_pa_bias_to_rf_8822b(dm, e_rf_path,
+						      tx_pa_bias[e_rf_path]);
+
+		power_trim_info->pa_bias_flag |= PA_BIAS_FLAG_ON;
+	} else {
+		RF_DBG(dm, DBG_RF_MP, "[kfree] 8822b 2g tx pa bias no pg\n");
+	}
+}
+
+void phydm_set_kfree_to_rf_8822b(void *dm_void, u8 e_rf_path, u8 data)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	u32 gain_bmask = (BIT(18) | BIT(17) | BIT(16) | BIT(15) | BIT(14));
+
+	odm_set_rf_reg(dm, e_rf_path, RF_0xde, BIT(0), 1);
+	odm_set_rf_reg(dm, e_rf_path, RF_0xde, BIT(4), 1);
+	odm_set_rf_reg(dm, e_rf_path, RF_0x65, MASKLWORD, 0x9000);
+	odm_set_rf_reg(dm, e_rf_path, RF_0x55, BIT(5), 1);
+
+	odm_set_rf_reg(dm, e_rf_path, RF_0x55, BIT(19), (data & BIT(0)));
+	odm_set_rf_reg(dm, e_rf_path, RF_0x55, gain_bmask,
+		       ((data & 0x1f) >> 1));
+
+	RF_DBG(dm, DBG_RF_MP, "[kfree] 8822b 0x55[19:14]=0x%X path=%d\n",
+	       odm_get_rf_reg(dm, e_rf_path, RF_0x55,
+			      (BIT(19) | BIT(18) | BIT(17) | BIT(16) |
+			      BIT(15) | BIT(14))), e_rf_path);
+}
+
+void phydm_clear_kfree_to_rf_8822b(void *dm_void, u8 e_rf_path, u8 data)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	u32 gain_bmask = (BIT(18) | BIT(17) | BIT(16) | BIT(15) | BIT(14));
+
+	odm_set_rf_reg(dm, e_rf_path, RF_0xde, BIT(0), 1);
+	odm_set_rf_reg(dm, e_rf_path, RF_0xde, BIT(4), 1);
+	odm_set_rf_reg(dm, e_rf_path, RF_0x65, MASKLWORD, 0x9000);
+	odm_set_rf_reg(dm, e_rf_path, RF_0x55, BIT(5), 1);
+
+	odm_set_rf_reg(dm, e_rf_path, RF_0x55, BIT(19), (data & BIT(0)));
+	odm_set_rf_reg(dm, e_rf_path, RF_0x55, gain_bmask,
+		       ((data & 0x1f) >> 1));
+
+	odm_set_rf_reg(dm, e_rf_path, RF_0xde, BIT(0), 0);
+	odm_set_rf_reg(dm, e_rf_path, RF_0xde, BIT(4), 1);
+	odm_set_rf_reg(dm, e_rf_path, RF_0x65, MASKLWORD, 0x9000);
+	odm_set_rf_reg(dm, e_rf_path, RF_0x55, BIT(5), 0);
+	odm_set_rf_reg(dm, e_rf_path, RF_0x55, BIT(7), 0);
+
+	RF_DBG(dm, DBG_RF_MP,
+	       "[kfree] 8822b clear power trim 0x55[19:14]=0x%X path=%d\n",
+	       odm_get_rf_reg(dm, e_rf_path, RF_0x55,
+			      (BIT(19) | BIT(18) | BIT(17) | BIT(16) |
+			      BIT(15) | BIT(14))), e_rf_path);
+}
+
+void phydm_get_thermal_trim_offset_8710b(void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct odm_power_trim_data *power_trim_info = &dm->power_trim_data;
+
+	u8 pg_therm = 0xff;
+
+	odm_efuse_one_byte_read(dm, 0x0EF, &pg_therm, false);
+
+	if (pg_therm != 0xff) {
+		pg_therm = pg_therm & 0x1f;
+		if ((pg_therm & BIT(0)) == 0)
+			power_trim_info->thermal = (-1 * (pg_therm >> 1));
+		else
+			power_trim_info->thermal = (pg_therm >> 1);
+
+		power_trim_info->flag |= KFREE_FLAG_THERMAL_K_ON;
+	}
+
+	RF_DBG(dm, DBG_RF_MP, "[kfree] 8710b thermal trim flag:0x%02x\n",
+	       power_trim_info->flag);
+
+	if (power_trim_info->flag & KFREE_FLAG_THERMAL_K_ON)
+		RF_DBG(dm, DBG_RF_MP, "[kfree] 8710b thermal:%d\n",
+		       power_trim_info->thermal);
+}
+
+void phydm_get_power_trim_offset_8710b(void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct odm_power_trim_data *power_trim_info = &dm->power_trim_data;
+
+	u8 pg_power = 0xff;
+
+	odm_efuse_one_byte_read(dm, 0xEE, &pg_power, false);
+
+	if (pg_power != 0xff) {
+		/*Path A*/
+		odm_efuse_one_byte_read(dm, 0xEE, &pg_power, false);
+		power_trim_info->bb_gain[0][0] = (pg_power & 0xf);
+
+		power_trim_info->flag |= KFREE_FLAG_ON_2G;
+		power_trim_info->flag |= KFREE_FLAG_ON;
+	}
+
+	RF_DBG(dm, DBG_RF_MP, "[kfree] 8710b power trim flag:0x%02x\n",
+	       power_trim_info->flag);
+
+	if (power_trim_info->flag & KFREE_FLAG_ON)
+		RF_DBG(dm, DBG_RF_MP,
+		       "[kfree] 8710b power_trim_data->bb_gain[0][0]=0x%X\n",
+		       power_trim_info->bb_gain[0][0]);
+}
+
+void phydm_set_kfree_to_rf_8710b(void *dm_void, u8 e_rf_path, u8 data)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	u32 gain_bmask = (BIT(18) | BIT(17) | BIT(16) | BIT(15));
+
+	odm_set_rf_reg(dm, e_rf_path, RF_0x55, BIT(19), (data & BIT(0)));
+	odm_set_rf_reg(dm, e_rf_path, RF_0x55, gain_bmask, ((data & 0xf) >> 1));
+
+	RF_DBG(dm, DBG_RF_MP, "[kfree] 8710b 0x55[19:14]=0x%X path=%d\n",
+	       odm_get_rf_reg(dm, e_rf_path, RF_0x55,
+			      (BIT(19) | BIT(18) | BIT(17) | BIT(16) |
+			      BIT(15) | BIT(14))), e_rf_path);
+}
+
+void phydm_clear_kfree_to_rf_8710b(void *dm_void, u8 e_rf_path, u8 data)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	u32 gain_bmask = (BIT(18) | BIT(17) | BIT(16) | BIT(15) | BIT(14));
+
+	odm_set_rf_reg(dm, e_rf_path, RF_0x55, BIT(19), (data & BIT(0)));
+	odm_set_rf_reg(dm, e_rf_path, RF_0x55, gain_bmask,
+		       ((data & 0x1f) >> 1));
+
+	RF_DBG(dm, DBG_RF_MP,
+	       "[kfree] 8710b clear power trim 0x55[19:14]=0x%X path=%d\n",
+	       odm_get_rf_reg(dm, e_rf_path, RF_0x55,
+			      (BIT(19) | BIT(18) | BIT(17) | BIT(16) |
+			      BIT(15) | BIT(14))), e_rf_path);
+}
+
+void phydm_get_thermal_trim_offset_8192f(void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct odm_power_trim_data *power_trim_info = &dm->power_trim_data;
+
+	u8 pg_therm = 0xff;
+
+	odm_efuse_one_byte_read(dm, 0x1EF, &pg_therm, false);
+
+	if (pg_therm != 0xff) {
+		pg_therm = pg_therm & 0x1f;
+		if ((pg_therm & BIT(0)) == 0)
+			power_trim_info->thermal = (-1 * (pg_therm >> 1));
+		else
+			power_trim_info->thermal = (pg_therm >> 1);
+
+		power_trim_info->flag |= KFREE_FLAG_THERMAL_K_ON;
+	}
+
+	RF_DBG(dm, DBG_RF_MP, "[kfree] 8192f thermal trim flag:0x%02x\n",
+	       power_trim_info->flag);
+
+	if (power_trim_info->flag & KFREE_FLAG_THERMAL_K_ON)
+		RF_DBG(dm, DBG_RF_MP, "[kfree] 8192f thermal:%d\n",
+		       power_trim_info->thermal);
+}
+
+void phydm_get_power_trim_offset_8192f(void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct odm_power_trim_data *power_trim_info = &dm->power_trim_data;
+
+	u8 pg_power1 = 0xff, pg_power2 = 0xff, pg_power3 = 0xff, i, j;
+
+	odm_efuse_one_byte_read(dm, 0x1EE, &pg_power1, false); /*CH4-9*/
+
+	if (pg_power1 != 0xff) {
+		/*Path A*/
+		odm_efuse_one_byte_read(dm, 0x1EE, &pg_power1, false);
+		power_trim_info->bb_gain[1][0] = (pg_power1 & 0xf);
+		/*Path B*/
+		odm_efuse_one_byte_read(dm, 0x1EE, &pg_power1, false);
+		power_trim_info->bb_gain[1][1] = ((pg_power1 & 0xf0) >> 4);
+
+		power_trim_info->flag |= KFREE_FLAG_ON_2G;
+		power_trim_info->flag |= KFREE_FLAG_ON;
+	}
+
+	odm_efuse_one_byte_read(dm, 0x1EC, &pg_power2, false); /*CH1-3*/
+
+	if (pg_power2 != 0xff) {
+		/*Path A*/
+		odm_efuse_one_byte_read(dm, 0x1EC, &pg_power2, false);
+		power_trim_info->bb_gain[0][0] = (pg_power2 & 0xf);
+		/*Path B*/
+		odm_efuse_one_byte_read(dm, 0x1EC, &pg_power2, false);
+		power_trim_info->bb_gain[0][1] = ((pg_power2 & 0xf0) >> 4);
+
+		power_trim_info->flag |= KFREE_FLAG_ON_2G;
+		power_trim_info->flag |= KFREE_FLAG_ON;
+	} else {
+		power_trim_info->bb_gain[0][0] = (pg_power1 & 0xf);
+		power_trim_info->bb_gain[0][1] = ((pg_power1 & 0xf0) >> 4);
+	}
+
+	odm_efuse_one_byte_read(dm, 0x1EA, &pg_power3, false); /*CH10-14*/
+
+	if (pg_power3 != 0xff) {
+		/*Path A*/
+		odm_efuse_one_byte_read(dm, 0x1EA, &pg_power3, false);
+		power_trim_info->bb_gain[2][0] = (pg_power3 & 0xf);
+		/*Path B*/
+		odm_efuse_one_byte_read(dm, 0x1EA, &pg_power3, false);
+		power_trim_info->bb_gain[2][1] = ((pg_power3 & 0xf0) >> 4);
+
+		power_trim_info->flag |= KFREE_FLAG_ON_2G;
+		power_trim_info->flag |= KFREE_FLAG_ON;
+	} else {
+		power_trim_info->bb_gain[2][0] = (pg_power1 & 0xf);
+		power_trim_info->bb_gain[2][1] = ((pg_power1 & 0xf0) >> 4);
+	}
+
+	RF_DBG(dm, DBG_RF_MP, "[kfree] 8192F power trim flag:0x%02x\n",
+	       power_trim_info->flag);
+
+	if (!(power_trim_info->flag & KFREE_FLAG_ON))
+		return;
+
+	for (i = 0; i < KFREE_CH_NUM; i++) {
+		for (j = 0; j < 2; j++)
+			RF_DBG(dm, DBG_RF_MP,
+			       "[kfree] 8192F PwrTrim->bb_gain[%d][%d]=0x%X\n",
+			       i, j, power_trim_info->bb_gain[i][j]);
+	}
+}
+
+void phydm_set_kfree_to_rf_8192f(void *dm_void, u8 e_rf_path, u8 channel_idx,
+				 u8 data)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+
+	/*power_trim based on 55[19:14]*/
+	odm_set_rf_reg(dm, e_rf_path, RF_0x55, BIT(5), 1);
+	/*enable 55[14] for 0.5db step*/
+	odm_set_rf_reg(dm, e_rf_path, RF_0xf5, BIT(18), 1);
+	/*enter power_trim debug mode*/
+	odm_set_rf_reg(dm, e_rf_path, RF_0xdf, BIT(7), 1);
+	/*write enable*/
+	odm_set_rf_reg(dm, e_rf_path, RF_0xef, BIT(7), 1);
+
+	if (e_rf_path == 0) {
+		if (channel_idx == 0) {
+			odm_set_rf_reg(dm, e_rf_path, RF_0x33, 0x70000, 0);
+			odm_set_rf_reg(dm, e_rf_path, 0x33, 0x3F, data);
+
+			odm_set_rf_reg(dm, e_rf_path, RF_0x33, 0x70000, 1);
+			odm_set_rf_reg(dm, e_rf_path, 0x33, 0x3F, data);
+
+		} else if (channel_idx == 1) {
+			odm_set_rf_reg(dm, e_rf_path, RF_0x33, 0x70000, 2);
+			odm_set_rf_reg(dm, e_rf_path, 0x33, 0x3F, data);
+
+			odm_set_rf_reg(dm, e_rf_path, RF_0x33, 0x70000, 3);
+			odm_set_rf_reg(dm, e_rf_path, 0x33, 0x3F, data);
+		} else if (channel_idx == 2) {
+			odm_set_rf_reg(dm, e_rf_path, RF_0x33, 0x70000, 4);
+			odm_set_rf_reg(dm, e_rf_path, 0x33, 0x3F, data);
+
+			odm_set_rf_reg(dm, e_rf_path, RF_0x33, 0x70000, 5);
+			odm_set_rf_reg(dm, e_rf_path, 0x33, 0x3F, data);
+		}
+	} else if (e_rf_path == 1) {
+		if (channel_idx == 0) {
+			odm_set_rf_reg(dm, e_rf_path, RF_0x33, 0x70000, 0);
+			odm_set_rf_reg(dm, e_rf_path, 0x33, 0x3F, data);
+
+			odm_set_rf_reg(dm, e_rf_path, RF_0x33, 0x70000, 1);
+			odm_set_rf_reg(dm, e_rf_path, 0x33, 0x3F, data);
+		} else if (channel_idx == 1) {
+			odm_set_rf_reg(dm, e_rf_path, RF_0x33, 0x70000, 2);
+			odm_set_rf_reg(dm, e_rf_path, 0x33, 0x3F, data);
+
+			odm_set_rf_reg(dm, e_rf_path, RF_0x33, 0x70000, 3);
+			odm_set_rf_reg(dm, e_rf_path, 0x33, 0x3F, data);
+		} else if (channel_idx == 2) {
+			odm_set_rf_reg(dm, e_rf_path, RF_0x33, 0x70000, 4);
+			odm_set_rf_reg(dm, e_rf_path, 0x33, 0x3F, data);
+
+			odm_set_rf_reg(dm, e_rf_path, RF_0x33, 0x70000, 5);
+			odm_set_rf_reg(dm, e_rf_path, 0x33, 0x3F, data);
+		}
+	}
+
+	/*leave power_trim debug mode*/
+	odm_set_rf_reg(dm, e_rf_path, RF_0xdf, BIT(7), 0);
+	/*write disable*/
+	odm_set_rf_reg(dm, e_rf_path, RF_0xef, BIT(7), 0);
+
+	RF_DBG(dm, DBG_RF_MP,
+	       "[kfree] 8192F 0x55[19:14]=0x%X path=%d channel=%d\n",
+	       odm_get_rf_reg(dm, e_rf_path, RF_0x55,
+			      (BIT(19) | BIT(18) | BIT(17) | BIT(16) |
+			      BIT(15) | BIT(14))), e_rf_path, channel_idx);
+}
+
+#if 0
+/*
+void phydm_clear_kfree_to_rf_8192f(void *dm_void, u8 e_rf_path, u8 data)
+{
+	struct dm_struct		*dm = (struct dm_struct *)dm_void;
+	struct dm_rf_calibration_struct	*cali_info = &dm->rf_calibrate_info;
+
+	odm_set_rf_reg(dm, e_rf_path, RF_0x55, BIT(19), (data & BIT(0)));
+	odm_set_rf_reg(dm, e_rf_path, RF_0x55, (BIT(18) | BIT(17) | BIT(16) | BIT(15) | BIT(14)), ((data & 0x1f) >> 1));
+
+	RF_DBG(dm, DBG_RF_MP,
+		"[kfree] 8192F clear power trim 0x55[19:14]=0x%X path=%d\n",
+		odm_get_rf_reg(dm, e_rf_path, RF_0x55, (BIT(19) | BIT(18) | BIT(17) | BIT(16) | BIT(15) | BIT(14))),
+		e_rf_path
+		);
+}
+*/
+#endif
+
+void phydm_set_kfree_to_rf(void *dm_void, u8 e_rf_path, u8 data)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+
+	if (dm->support_ic_type & ODM_RTL8814A)
+		phydm_set_kfree_to_rf_8814a(dm, e_rf_path, data);
+
+	if ((dm->support_ic_type & ODM_RTL8821C) &&
+	    (*dm->band_type == ODM_BAND_2_4G))
+		phydm_set_kfree_to_rf_8821c(dm, e_rf_path, true, data);
+	else if (dm->support_ic_type & ODM_RTL8821C)
+		phydm_set_kfree_to_rf_8821c(dm, e_rf_path, false, data);
+
+	if (dm->support_ic_type & ODM_RTL8822B)
+		phydm_set_kfree_to_rf_8822b(dm, e_rf_path, data);
+
+	if (dm->support_ic_type & ODM_RTL8710B)
+		phydm_set_kfree_to_rf_8710b(dm, e_rf_path, data);
+}
+
+void phydm_clear_kfree_to_rf(void *dm_void, u8 e_rf_path, u8 data)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+
+	if (dm->support_ic_type & ODM_RTL8822B)
+		phydm_clear_kfree_to_rf_8822b(dm, e_rf_path, 1);
+
+	if (dm->support_ic_type & ODM_RTL8821C)
+		phydm_clear_kfree_to_rf_8821c(dm, e_rf_path, 1);
+}
+
+void phydm_get_thermal_trim_offset(void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+
+#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
+	void *adapter = dm->adapter;
+	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter));
+	PEFUSE_HAL pEfuseHal = &hal_data->EfuseHal;
+	u1Byte eFuseContent[DCMD_EFUSE_MAX_SECTION_NUM * EFUSE_MAX_WORD_UNIT * 2];
+
+	if (HAL_MAC_Dump_EFUSE(&GET_HAL_MAC_INFO((PADAPTER)adapter), EFUSE_WIFI, eFuseContent, pEfuseHal->PhysicalLen_WiFi, HAL_MAC_EFUSE_PHYSICAL, HAL_MAC_EFUSE_PARSE_DRV) != RT_STATUS_SUCCESS)
+		RF_DBG(dm, DBG_RF_MP, "[kfree] dump efuse fail !!!\n");
+#endif
+
+	if (dm->support_ic_type & ODM_RTL8821C)
+		phydm_get_thermal_trim_offset_8821c(dm_void);
+	else if (dm->support_ic_type & ODM_RTL8822B)
+		phydm_get_thermal_trim_offset_8822b(dm_void);
+	else if (dm->support_ic_type & ODM_RTL8710B)
+		phydm_get_thermal_trim_offset_8710b(dm_void);
+	else if (dm->support_ic_type & ODM_RTL8192F)
+		phydm_get_thermal_trim_offset_8192f(dm_void);
+}
+
+void phydm_get_power_trim_offset(void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+
+#if 0 //(DM_ODM_SUPPORT_TYPE & ODM_WIN)	// 2017 MH DM Should use the same code.s
+	void		*adapter = dm->adapter;
+	HAL_DATA_TYPE	*hal_data = GET_HAL_DATA(((PADAPTER)adapter));
+	PEFUSE_HAL		pEfuseHal = &hal_data->EfuseHal;
+	u1Byte			eFuseContent[DCMD_EFUSE_MAX_SECTION_NUM * EFUSE_MAX_WORD_UNIT * 2];
+
+	if (HAL_MAC_Dump_EFUSE(&GET_HAL_MAC_INFO(adapter), EFUSE_WIFI, eFuseContent, pEfuseHal->PhysicalLen_WiFi, HAL_MAC_EFUSE_PHYSICAL, HAL_MAC_EFUSE_PARSE_DRV) != RT_STATUS_SUCCESS)
+		RF_DBG(dm, DBG_RF_MP, "[kfree] dump efuse fail !!!\n");
+#endif
+
+	if (dm->support_ic_type & ODM_RTL8821C)
+		phydm_get_power_trim_offset_8821c(dm_void);
+	else if (dm->support_ic_type & ODM_RTL8822B)
+		phydm_get_power_trim_offset_8822b(dm_void);
+	else if (dm->support_ic_type & ODM_RTL8710B)
+		phydm_get_power_trim_offset_8710b(dm_void);
+	else if (dm->support_ic_type & ODM_RTL8192F)
+		phydm_get_power_trim_offset_8192f(dm_void);
+}
+
+void phydm_get_pa_bias_offset(void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+
+#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
+	void *adapter = dm->adapter;
+	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter));
+	PEFUSE_HAL pEfuseHal = &hal_data->EfuseHal;
+	u1Byte eFuseContent[DCMD_EFUSE_MAX_SECTION_NUM * EFUSE_MAX_WORD_UNIT * 2];
+
+	if (HAL_MAC_Dump_EFUSE(&GET_HAL_MAC_INFO((PADAPTER)adapter), EFUSE_WIFI, eFuseContent, pEfuseHal->PhysicalLen_WiFi, HAL_MAC_EFUSE_PHYSICAL, HAL_MAC_EFUSE_PARSE_DRV) != RT_STATUS_SUCCESS)
+		RF_DBG(dm, DBG_RF_MP, "[kfree] dump efuse fail !!!\n");
+#endif
+
+	if (dm->support_ic_type & ODM_RTL8822B)
+		phydm_get_pa_bias_offset_8822b(dm_void);
+}
+
+s8 phydm_get_thermal_offset(void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct odm_power_trim_data *power_trim_info = &dm->power_trim_data;
+
+	if (power_trim_info->flag & KFREE_FLAG_THERMAL_K_ON)
+		return power_trim_info->thermal;
+	else
+		return 0;
+}
+
+void phydm_do_kfree(void *dm_void, u8 channel_to_sw)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct odm_power_trim_data *pwrtrim = &dm->power_trim_data;
+	u8 channel_idx = 0, rfpath = 0, max_path = 0, kfree_band_num = 0;
+	u8 i, j;
+	s8 bb_gain;
+
+	if (dm->support_ic_type & ODM_RTL8814A)
+		max_path = 4; /*0~3*/
+	else if (dm->support_ic_type &
+		 (ODM_RTL8812 | ODM_RTL8822B | ODM_RTL8192F)) {
+		max_path = 2; /*0~1*/
+		kfree_band_num = KFREE_BAND_NUM;
+	} else if (dm->support_ic_type & ODM_RTL8821C) {
+		max_path = 1;
+		kfree_band_num = KFREE_BAND_NUM;
+	} else if (dm->support_ic_type & ODM_RTL8710B) {
+		max_path = 1;
+		kfree_band_num = 1;
+	}
+
+	if (dm->support_ic_type &
+	    (ODM_RTL8192F | ODM_RTL8822B | ODM_RTL8821C |
+	    ODM_RTL8814A | ODM_RTL8710B)) {
+		for (i = 0; i < kfree_band_num; i++) {
+			for (j = 0; j < max_path; j++)
+				RF_DBG(dm, DBG_RF_MP,
+				       "[kfree] PwrTrim->gain[%d][%d]=0x%X\n",
+				       i, j, pwrtrim->bb_gain[i][j]);
+		}
+	}
+	if (*dm->band_type == ODM_BAND_2_4G &&
+	    pwrtrim->flag & KFREE_FLAG_ON_2G) {
+		if (!(dm->support_ic_type & ODM_RTL8192F)) {
+			if (channel_to_sw >= 1 && channel_to_sw <= 14)
+				channel_idx = PHYDM_2G;
+			for (rfpath = RF_PATH_A; rfpath < max_path; rfpath++) {
+				RF_DBG(dm, DBG_RF_MP,
+				       "[kfree] %s:chnl=%d PATH=%d gain:0x%X\n",
+				       __func__, channel_to_sw, rfpath,
+				       pwrtrim->bb_gain[channel_idx][rfpath]);
+				bb_gain = pwrtrim->bb_gain[channel_idx][rfpath];
+				phydm_set_kfree_to_rf(dm, rfpath, bb_gain);
+			}
+		} else if (dm->support_ic_type & ODM_RTL8192F) {
+			if (channel_to_sw >= 1 && channel_to_sw <= 3)
+				channel_idx = 0;
+			if (channel_to_sw >= 4 && channel_to_sw <= 9)
+				channel_idx = 1;
+			if (channel_to_sw >= 10 && channel_to_sw <= 14)
+				channel_idx = 2;
+			for (rfpath = RF_PATH_A; rfpath < max_path; rfpath++) {
+				RF_DBG(dm, DBG_RF_MP,
+				       "[kfree] %s:chnl=%d PATH=%d gain:0x%X\n",
+				       __func__, channel_to_sw, rfpath,
+				       pwrtrim->bb_gain[channel_idx][rfpath]);
+				bb_gain = pwrtrim->bb_gain[channel_idx][rfpath];
+				phydm_set_kfree_to_rf_8192f(dm, rfpath,
+							    channel_idx,
+							    bb_gain);
+			}
+		}
+	} else if (*dm->band_type == ODM_BAND_5G &&
+		   pwrtrim->flag & KFREE_FLAG_ON_5G) {
+		if (channel_to_sw >= 36 && channel_to_sw <= 48)
+			channel_idx = PHYDM_5GLB1;
+		if (channel_to_sw >= 52 && channel_to_sw <= 64)
+			channel_idx = PHYDM_5GLB2;
+		if (channel_to_sw >= 100 && channel_to_sw <= 120)
+			channel_idx = PHYDM_5GMB1;
+		if (channel_to_sw >= 122 && channel_to_sw <= 144)
+			channel_idx = PHYDM_5GMB2;
+		if (channel_to_sw >= 149 && channel_to_sw <= 177)
+			channel_idx = PHYDM_5GHB;
+
+		for (rfpath = RF_PATH_A; rfpath < max_path; rfpath++) {
+			RF_DBG(dm, DBG_RF_MP,
+			       "[kfree] %s: channel=%d PATH=%d bb_gain:0x%X\n",
+			       __func__, channel_to_sw, rfpath,
+			       pwrtrim->bb_gain[channel_idx][rfpath]);
+			bb_gain = pwrtrim->bb_gain[channel_idx][rfpath];
+			phydm_set_kfree_to_rf(dm, rfpath, bb_gain);
+		}
+	} else {
+		RF_DBG(dm, DBG_RF_MP, "[kfree] Set default Register\n");
+		if (!(dm->support_ic_type & ODM_RTL8192F)) {
+			for (rfpath = RF_PATH_A; rfpath < max_path; rfpath++) {
+				bb_gain = pwrtrim->bb_gain[channel_idx][rfpath];
+				phydm_clear_kfree_to_rf(dm, rfpath, bb_gain);
+			}
+		}
+#if 0
+		/*else if(dm->support_ic_type & ODM_RTL8192F){
+			if (channel_to_sw >= 1 && channel_to_sw <= 3)
+				channel_idx = 0;
+			if (channel_to_sw >= 4 && channel_to_sw <= 9)
+				channel_idx = 1;
+			if (channel_to_sw >= 9 && channel_to_sw <= 14)
+				channel_idx = 2;
+			for (rfpath = RF_PATH_A;  rfpath < max_path; rfpath++)
+				phydm_clear_kfree_to_rf_8192f(dm, rfpath, pwrtrim->bb_gain[channel_idx][rfpath]);
+		}*/
+#endif
+	}
+}
+
+void phydm_config_kfree(void *dm_void, u8 channel_to_sw)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct dm_rf_calibration_struct *cali_info = &dm->rf_calibrate_info;
+	struct odm_power_trim_data *pwrtrim = &dm->power_trim_data;
+
+	RF_DBG(dm, DBG_RF_MP, "===>[kfree] phy_ConfigKFree()\n");
+
+	if (cali_info->reg_rf_kfree_enable == 2) {
+		RF_DBG(dm, DBG_RF_MP,
+		       "[kfree] %s: reg_rf_kfree_enable == 2, Disable\n",
+		       __func__);
+		return;
+	} else if (cali_info->reg_rf_kfree_enable == 1 ||
+			cali_info->reg_rf_kfree_enable == 0) {
+		RF_DBG(dm, DBG_RF_MP,
+		       "[kfree] %s: reg_rf_kfree_enable == true\n", __func__);
+		/*Make sure the targetval is defined*/
+		if (!(pwrtrim->flag & KFREE_FLAG_ON)) {
+			RF_DBG(dm, DBG_RF_MP,
+			       "[kfree] %s: efuse is 0xff, KFree not work\n",
+			       __func__);
+			return;
+		}
+#if 0
+		/*if kfree_table[0] == 0xff, means no Kfree*/
+#endif
+		phydm_do_kfree(dm, channel_to_sw);
+	}
+	RF_DBG(dm, DBG_RF_MP, "<===[kfree] phy_ConfigKFree()\n");
+}
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/halrf/halrf_kfree.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/halrf/halrf_kfree.h
--- linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/halrf/halrf_kfree.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/halrf/halrf_kfree.h	2020-04-10 16:35:06.819660208 +0300
@@ -0,0 +1,111 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017  Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * The full GNU General Public License is included in this distribution in the
+ * file called LICENSE.
+ *
+ * Contact Information:
+ * wlanfae <wlanfae@realtek.com>
+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
+ * Hsinchu 300, Taiwan.
+ *
+ * Larry Finger <Larry.Finger@lwfinger.net>
+ *
+ *****************************************************************************/
+
+#ifndef __HALRF_KFREE_H__
+#define __HALRF_KFREE_H__
+
+#define KFREE_VERSION "1.0"
+
+#define KFREE_BAND_NUM 6
+#define KFREE_CH_NUM 3
+
+#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_AP))
+
+#define BB_GAIN_NUM 6
+
+#endif
+
+#define KFREE_FLAG_ON BIT(0)
+#define KFREE_FLAG_THERMAL_K_ON BIT(1)
+
+#define KFREE_FLAG_ON_2G BIT(2)
+#define KFREE_FLAG_ON_5G BIT(3)
+
+#define PA_BIAS_FLAG_ON BIT(4)
+
+#define PPG_THERMAL_OFFSET_21C 0x1EF
+#define PPG_2G_TXAB_21C 0x1EE
+#define PPG_5GL1_TXA_21C 0x1EC
+#define PPG_5GL2_TXA_21C 0x1E8
+#define PPG_5GM1_TXA_21C 0x1E4
+#define PPG_5GM2_TXA_21C 0x1E0
+#define PPG_5GH1_TXA_21C 0x1DC
+
+#define PPG_THERMAL_OFFSET_22B 0x3EF
+#define PPG_2G_TXAB_22B 0x3EE
+#define PPG_2G_TXCD_22B 0x3ED
+#define PPG_5GL1_TXA_22B 0x3EC
+#define PPG_5GL1_TXB_22B 0x3EB
+#define PPG_5GL1_TXC_22B 0x3EA
+#define PPG_5GL1_TXD_22B 0x3E9
+#define PPG_5GL2_TXA_22B 0x3E8
+#define PPG_5GL2_TXB_22B 0x3E7
+#define PPG_5GL2_TXC_22B 0x3E6
+#define PPG_5GL2_TXD_22B 0x3E5
+#define PPG_5GM1_TXA_22B 0x3E4
+#define PPG_5GM1_TXB_22B 0x3E3
+#define PPG_5GM1_TXC_22B 0x3E2
+#define PPG_5GM1_TXD_22B 0x3E1
+#define PPG_5GM2_TXA_22B 0x3E0
+#define PPG_5GM2_TXB_22B 0x3DF
+#define PPG_5GM2_TXC_22B 0x3DE
+#define PPG_5GM2_TXD_22B 0x3DD
+#define PPG_5GH1_TXA_22B 0x3DC
+#define PPG_5GH1_TXB_22B 0x3DB
+#define PPG_5GH1_TXC_22B 0x3DA
+#define PPG_5GH1_TXD_22B 0x3D9
+
+#define PPG_PABIAS_2GA_22B 0x3D5
+#define PPG_PABIAS_2GB_22B 0x3D6
+
+struct odm_power_trim_data {
+	u8 flag;
+	u8 pa_bias_flag;
+	s8 bb_gain[KFREE_BAND_NUM][MAX_RF_PATH];
+	s8 thermal;
+};
+
+enum phydm_kfree_channeltosw {
+	PHYDM_2G = 0,
+	PHYDM_5GLB1 = 1,
+	PHYDM_5GLB2 = 2,
+	PHYDM_5GMB1 = 3,
+	PHYDM_5GMB2 = 4,
+	PHYDM_5GHB = 5,
+};
+
+void phydm_get_thermal_trim_offset(void *dm_void);
+
+void phydm_get_power_trim_offset(void *dm_void);
+
+void phydm_get_pa_bias_offset(void *dm_void);
+
+s8 phydm_get_thermal_offset(void *dm_void);
+
+void phydm_clear_kfree_to_rf(void *dm_void, u8 e_rf_path, u8 data);
+
+void phydm_config_kfree(void *dm_void, u8 channel_to_sw);
+
+#endif /*#ifndef __HALRF_KFREE_H__*/
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/halrf/halrf_powertracking_ap.c linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/halrf/halrf_powertracking_ap.c
--- linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/halrf/halrf_powertracking_ap.c	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/halrf/halrf_powertracking_ap.c	2020-04-10 16:35:06.820660254 +0300
@@ -0,0 +1,1219 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+
+/* ************************************************************
+ * include files
+ * ************************************************************ */
+#include "mp_precomp.h"
+#include "phydm_precomp.h"
+
+#if !defined(_OUTSRC_COEXIST)
+/* ************************************************************
+ * Global var
+ * ************************************************************ */
+
+
+u32 ofdm_swing_table_new[OFDM_TABLE_SIZE_92D] = {
+	0x0b40002d, /* 0,  -15.0dB */
+	0x0c000030, /* 1,  -14.5dB */
+	0x0cc00033, /* 2,  -14.0dB */
+	0x0d800036, /* 3,  -13.5dB */
+	0x0e400039, /* 4,  -13.0dB */
+	0x0f00003c, /* 5,  -12.5dB */
+	0x10000040, /* 6,  -12.0dB */
+	0x11000044, /* 7,  -11.5dB */
+	0x12000048, /* 8,  -11.0dB */
+	0x1300004c, /* 9,  -10.5dB */
+	0x14400051, /* 10, -10.0dB */
+	0x15800056, /* 11, -9.5dB */
+	0x16c0005b, /* 12, -9.0dB */
+	0x18000060, /* 13, -8.5dB */
+	0x19800066, /* 14, -8.0dB */
+	0x1b00006c, /* 15, -7.5dB */
+	0x1c800072, /* 16, -7.0dB */
+	0x1e400079, /* 17, -6.5dB */
+	0x20000080, /* 18, -6.0dB */
+	0x22000088, /* 19, -5.5dB */
+	0x24000090, /* 20, -5.0dB */
+	0x26000098, /* 21, -4.5dB */
+	0x288000a2, /* 22, -4.0dB */
+	0x2ac000ab, /* 23, -3.5dB */
+	0x2d4000b5, /* 24, -3.0dB */
+	0x300000c0, /* 25, -2.5dB */
+	0x32c000cb, /* 26, -2.0dB */
+	0x35c000d7, /* 27, -1.5dB */
+	0x390000e4, /* 28, -1.0dB */
+	0x3c8000f2, /* 29, -0.5dB */
+	0x40000100, /* 30, +0dB */
+	0x43c0010f, /* 31, +0.5dB */
+	0x47c0011f, /* 32, +1.0dB */
+	0x4c000130, /* 33, +1.5dB */
+	0x50800142, /* 34, +2.0dB */
+	0x55400155, /* 35, +2.5dB */
+	0x5a400169, /* 36, +3.0dB */
+	0x5fc0017f, /* 37, +3.5dB */
+	0x65400195, /* 38, +4.0dB */
+	0x6b8001ae, /* 39, +4.5dB */
+	0x71c001c7, /* 40, +5.0dB */
+	0x788001e2, /* 41, +5.5dB */
+	0x7f8001fe  /* 42, +6.0dB */
+};
+
+u8 cck_swing_table_ch1_ch13_new[CCK_TABLE_SIZE][8] = {
+	{0x09, 0x08, 0x07, 0x06, 0x04, 0x03, 0x01, 0x01},	/* 0, -16.0dB */
+	{0x09, 0x09, 0x08, 0x06, 0x05, 0x03, 0x01, 0x01},	/* 1, -15.5dB */
+	{0x0a, 0x09, 0x08, 0x07, 0x05, 0x03, 0x02, 0x01},	/* 2, -15.0dB */
+	{0x0a, 0x0a, 0x09, 0x07, 0x05, 0x03, 0x02, 0x01},	/* 3, -14.5dB */
+	{0x0b, 0x0a, 0x09, 0x08, 0x06, 0x04, 0x02, 0x01},	/* 4, -14.0dB */
+	{0x0b, 0x0b, 0x0a, 0x08, 0x06, 0x04, 0x02, 0x01},	/* 5, -13.5dB */
+	{0x0c, 0x0c, 0x0a, 0x09, 0x06, 0x04, 0x02, 0x01},	/* 6, -13.0dB */
+	{0x0d, 0x0c, 0x0b, 0x09, 0x07, 0x04, 0x02, 0x01},	/* 7, -12.5dB */
+	{0x0d, 0x0d, 0x0c, 0x0a, 0x07, 0x05, 0x02, 0x01},	/* 8, -12.0dB */
+	{0x0e, 0x0e, 0x0c, 0x0a, 0x08, 0x05, 0x02, 0x01},	/* 9, -11.5dB */
+	{0x0f, 0x0f, 0x0d, 0x0b, 0x08, 0x05, 0x03, 0x01},	/* 10, -11.0dB */
+	{0x10, 0x10, 0x0e, 0x0b, 0x08, 0x05, 0x03, 0x01},	/* 11, -10.5dB */
+	{0x11, 0x11, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01},	/* 12, -10.0dB */
+	{0x12, 0x12, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01},	/* 13, -9.5dB */
+	{0x13, 0x13, 0x10, 0x0d, 0x0a, 0x06, 0x03, 0x01},	/* 14, -9.0dB */
+	{0x14, 0x14, 0x11, 0x0e, 0x0b, 0x07, 0x03, 0x02},	/* 15, -8.5dB */
+	{0x16, 0x15, 0x12, 0x0f, 0x0b, 0x07, 0x04, 0x01},	/* 16, -8.0dB */
+	{0x17, 0x16, 0x13, 0x10, 0x0c, 0x08, 0x04, 0x02},	/* 17, -7.5dB */
+	{0x18, 0x17, 0x15, 0x11, 0x0c, 0x08, 0x04, 0x02},	/* 18, -7.0dB */
+	{0x1a, 0x19, 0x16, 0x12, 0x0d, 0x09, 0x04, 0x02},	/* 19, -6.5dB */
+	{0x1c, 0x1a, 0x18, 0x12, 0x0e, 0x08, 0x04, 0x02},	/* 20, -6.0dB */
+	{0x1d, 0x1c, 0x18, 0x14, 0x0f, 0x0a, 0x05, 0x02},	/* 21, -5.5dB */
+	{0x1f, 0x1e, 0x1a, 0x15, 0x10, 0x0a, 0x05, 0x02},	/* 22, -5.0dB */
+	{0x20, 0x20, 0x1b, 0x16, 0x11, 0x08, 0x05, 0x02},	/* 23, -4.5dB */
+	{0x22, 0x21, 0x1d, 0x18, 0x11, 0x0b, 0x06, 0x02},	/* 24, -4.0dB */
+	{0x24, 0x23, 0x1f, 0x19, 0x13, 0x0c, 0x06, 0x03},	/* 25, -3.5dB */
+	{0x26, 0x25, 0x21, 0x1b, 0x14, 0x0d, 0x06, 0x03},	/* 26, -3.0dB */
+	{0x28, 0x28, 0x22, 0x1c, 0x15, 0x0d, 0x07, 0x03},	/* 27, -2.5dB */
+	{0x2b, 0x2a, 0x25, 0x1e, 0x16, 0x0e, 0x07, 0x03},	/* 28, -2.0dB */
+	{0x2d, 0x2d, 0x27, 0x1f, 0x18, 0x0f, 0x08, 0x03},	/* 29, -1.5dB */
+	{0x30, 0x2f, 0x29, 0x21, 0x19, 0x10, 0x08, 0x03},	/* 30, -1.0dB */
+	{0x33, 0x32, 0x2b, 0x23, 0x1a, 0x11, 0x08, 0x04},	/* 31, -0.5dB */
+	{0x36, 0x35, 0x2e, 0x25, 0x1c, 0x12, 0x09, 0x04}	/* 32, +0dB */
+};
+
+
+u8 cck_swing_table_ch14_new[CCK_TABLE_SIZE][8] = {
+	{0x09, 0x08, 0x07, 0x04, 0x00, 0x00, 0x00, 0x00},	/* 0, -16.0dB */
+	{0x09, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00},	/* 1, -15.5dB */
+	{0x0a, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00},	/* 2, -15.0dB */
+	{0x0a, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00},	/* 3, -14.5dB */
+	{0x0b, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00},	/* 4, -14.0dB */
+	{0x0b, 0x0b, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00},	/* 5, -13.5dB */
+	{0x0c, 0x0c, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00},	/* 6, -13.0dB */
+	{0x0d, 0x0c, 0x0b, 0x06, 0x00, 0x00, 0x00, 0x00},	/* 7, -12.5dB */
+	{0x0d, 0x0d, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00},	/* 8, -12.0dB */
+	{0x0e, 0x0e, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00},	/* 9, -11.5dB */
+	{0x0f, 0x0f, 0x0d, 0x08, 0x00, 0x00, 0x00, 0x00},	/* 10, -11.0dB */
+	{0x10, 0x10, 0x0e, 0x08, 0x00, 0x00, 0x00, 0x00},	/* 11, -10.5dB */
+	{0x11, 0x11, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00},	/* 12, -10.0dB */
+	{0x12, 0x12, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00},	/* 13, -9.5dB */
+	{0x13, 0x13, 0x10, 0x0a, 0x00, 0x00, 0x00, 0x00},	/* 14, -9.0dB */
+	{0x14, 0x14, 0x11, 0x0a, 0x00, 0x00, 0x00, 0x00},	/* 15, -8.5dB */
+	{0x16, 0x15, 0x12, 0x0b, 0x00, 0x00, 0x00, 0x00},	/* 16, -8.0dB */
+	{0x17, 0x16, 0x13, 0x0b, 0x00, 0x00, 0x00, 0x00},	/* 17, -7.5dB */
+	{0x18, 0x17, 0x15, 0x0c, 0x00, 0x00, 0x00, 0x00},	/* 18, -7.0dB */
+	{0x1a, 0x19, 0x16, 0x0d, 0x00, 0x00, 0x00, 0x00},	/* 19, -6.5dB */
+	{0x1c, 0x1a, 0x18, 0x0e, 0x00, 0x00, 0x00, 0x00},	/* 20, -6.0dB */
+	{0x1d, 0x1c, 0x18, 0x0e, 0x00, 0x00, 0x00, 0x00},	/* 21, -5.5dB */
+	{0x1f, 0x1e, 0x1a, 0x0f, 0x00, 0x00, 0x00, 0x00},	/* 22, -5.0dB */
+	{0x20, 0x20, 0x1b, 0x10, 0x00, 0x00, 0x00, 0x00},	/* 23, -4.5dB */
+	{0x22, 0x21, 0x1d, 0x11, 0x00, 0x00, 0x00, 0x00},	/* 24, -4.0dB */
+	{0x24, 0x23, 0x1f, 0x12, 0x00, 0x00, 0x00, 0x00},	/* 25, -3.5dB */
+	{0x26, 0x25, 0x21, 0x13, 0x00, 0x00, 0x00, 0x00},	/* 26, -3.0dB */
+	{0x28, 0x28, 0x24, 0x14, 0x00, 0x00, 0x00, 0x00},	/* 27, -2.5dB */
+	{0x2b, 0x2a, 0x25, 0x15, 0x00, 0x00, 0x00, 0x00},	/* 28, -2.0dB */
+	{0x2d, 0x2d, 0x17, 0x17, 0x00, 0x00, 0x00, 0x00},	/* 29, -1.5dB */
+	{0x30, 0x2f, 0x29, 0x18, 0x00, 0x00, 0x00, 0x00},	/* 30, -1.0dB */
+	{0x33, 0x32, 0x2b, 0x19, 0x00, 0x00, 0x00, 0x00},	/* 31, -0.5dB */
+	{0x36, 0x35, 0x2e, 0x1b, 0x00, 0x00, 0x00, 0x00}	/* 32, +0dB */
+};
+
+u32 ofdm_swing_table[OFDM_TABLE_SIZE_92D] = {
+	0x0b40002d, /* 0,  -15.0dB */
+	0x0c000030, /* 1,  -14.5dB */
+	0x0cc00033, /* 2,  -14.0dB */
+	0x0d800036, /* 3,  -13.5dB */
+	0x0e400039, /* 4,  -13.0dB */
+	0x0f00003c, /* 5,  -12.5dB */
+	0x10000040, /* 6,  -12.0dB */
+	0x11000044, /* 7,  -11.5dB */
+	0x12000048, /* 8,  -11.0dB */
+	0x1300004c, /* 9,  -10.5dB */
+	0x14400051, /* 10, -10.0dB */
+	0x15800056, /* 11, -9.5dB */
+	0x16c0005b, /* 12, -9.0dB */
+	0x18000060, /* 13, -8.5dB */
+	0x19800066, /* 14, -8.0dB */
+	0x1b00006c, /* 15, -7.5dB */
+	0x1c800072, /* 16, -7.0dB */
+	0x1e400079, /* 17, -6.5dB */
+	0x20000080, /* 18, -6.0dB */
+	0x22000088, /* 19, -5.5dB */
+	0x24000090, /* 20, -5.0dB */
+	0x26000098, /* 21, -4.5dB */
+	0x288000a2, /* 22, -4.0dB */
+	0x2ac000ab, /* 23, -3.5dB */
+	0x2d4000b5, /* 24, -3.0dB */
+	0x300000c0, /* 25, -2.5dB */
+	0x32c000cb, /* 26, -2.0dB */
+	0x35c000d7, /* 27, -1.5dB */
+	0x390000e4, /* 28, -1.0dB */
+	0x3c8000f2, /* 29, -0.5dB */
+	0x40000100, /* 30, +0dB */
+	0x43c0010f, /* 31, +0.5dB */
+	0x47c0011f, /* 32, +1.0dB */
+	0x4c000130, /* 33, +1.5dB */
+	0x50800142, /* 34, +2.0dB */
+	0x55400155, /* 35, +2.5dB */
+	0x5a400169, /* 36, +3.0dB */
+	0x5fc0017f, /* 37, +3.5dB */
+	0x65400195, /* 38, +4.0dB */
+	0x6b8001ae, /* 39, +4.5dB */
+	0x71c001c7, /* 40, +5.0dB */
+	0x788001e2, /* 41, +5.5dB */
+	0x7f8001fe  /* 42, +6.0dB */
+};
+
+
+u8 cck_swing_table_ch1_ch13[CCK_TABLE_SIZE][8] = {
+	{0x09, 0x08, 0x07, 0x06, 0x04, 0x03, 0x01, 0x01},	/* 0, -16.0dB */
+	{0x09, 0x09, 0x08, 0x06, 0x05, 0x03, 0x01, 0x01},	/* 1, -15.5dB */
+	{0x0a, 0x09, 0x08, 0x07, 0x05, 0x03, 0x02, 0x01},	/* 2, -15.0dB */
+	{0x0a, 0x0a, 0x09, 0x07, 0x05, 0x03, 0x02, 0x01},	/* 3, -14.5dB */
+	{0x0b, 0x0a, 0x09, 0x08, 0x06, 0x04, 0x02, 0x01},	/* 4, -14.0dB */
+	{0x0b, 0x0b, 0x0a, 0x08, 0x06, 0x04, 0x02, 0x01},	/* 5, -13.5dB */
+	{0x0c, 0x0c, 0x0a, 0x09, 0x06, 0x04, 0x02, 0x01},	/* 6, -13.0dB */
+	{0x0d, 0x0c, 0x0b, 0x09, 0x07, 0x04, 0x02, 0x01},	/* 7, -12.5dB */
+	{0x0d, 0x0d, 0x0c, 0x0a, 0x07, 0x05, 0x02, 0x01},	/* 8, -12.0dB */
+	{0x0e, 0x0e, 0x0c, 0x0a, 0x08, 0x05, 0x02, 0x01},	/* 9, -11.5dB */
+	{0x0f, 0x0f, 0x0d, 0x0b, 0x08, 0x05, 0x03, 0x01},	/* 10, -11.0dB */
+	{0x10, 0x10, 0x0e, 0x0b, 0x08, 0x05, 0x03, 0x01},	/* 11, -10.5dB */
+	{0x11, 0x11, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01},	/* 12, -10.0dB */
+	{0x12, 0x12, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01},	/* 13, -9.5dB */
+	{0x13, 0x13, 0x10, 0x0d, 0x0a, 0x06, 0x03, 0x01},	/* 14, -9.0dB */
+	{0x14, 0x14, 0x11, 0x0e, 0x0b, 0x07, 0x03, 0x02},	/* 15, -8.5dB */
+	{0x16, 0x15, 0x12, 0x0f, 0x0b, 0x07, 0x04, 0x01},	/* 16, -8.0dB */
+	{0x17, 0x16, 0x13, 0x10, 0x0c, 0x08, 0x04, 0x02},	/* 17, -7.5dB */
+	{0x18, 0x17, 0x15, 0x11, 0x0c, 0x08, 0x04, 0x02},	/* 18, -7.0dB */
+	{0x1a, 0x19, 0x16, 0x12, 0x0d, 0x09, 0x04, 0x02},	/* 19, -6.5dB */
+	{0x1c, 0x1a, 0x18, 0x12, 0x0e, 0x08, 0x04, 0x02},	/* 20, -6.0dB */
+	{0x1d, 0x1c, 0x18, 0x14, 0x0f, 0x0a, 0x05, 0x02},	/* 21, -5.5dB */
+	{0x1f, 0x1e, 0x1a, 0x15, 0x10, 0x0a, 0x05, 0x02},	/* 22, -5.0dB */
+	{0x20, 0x20, 0x1b, 0x16, 0x11, 0x08, 0x05, 0x02},	/* 23, -4.5dB */
+	{0x22, 0x21, 0x1d, 0x18, 0x11, 0x0b, 0x06, 0x02},	/* 24, -4.0dB */
+	{0x24, 0x23, 0x1f, 0x19, 0x13, 0x0c, 0x06, 0x03},	/* 25, -3.5dB */
+	{0x26, 0x25, 0x21, 0x1b, 0x14, 0x0d, 0x06, 0x03},	/* 26, -3.0dB */
+	{0x28, 0x28, 0x22, 0x1c, 0x15, 0x0d, 0x07, 0x03},	/* 27, -2.5dB */
+	{0x2b, 0x2a, 0x25, 0x1e, 0x16, 0x0e, 0x07, 0x03},	/* 28, -2.0dB */
+	{0x2d, 0x2d, 0x27, 0x1f, 0x18, 0x0f, 0x08, 0x03},	/* 29, -1.5dB */
+	{0x30, 0x2f, 0x29, 0x21, 0x19, 0x10, 0x08, 0x03},	/* 30, -1.0dB */
+	{0x33, 0x32, 0x2b, 0x23, 0x1a, 0x11, 0x08, 0x04},	/* 31, -0.5dB */
+	{0x36, 0x35, 0x2e, 0x25, 0x1c, 0x12, 0x09, 0x04}	/* 32, +0dB */
+};
+
+
+u8 cck_swing_table_ch14[CCK_TABLE_SIZE][8] = {
+	{0x09, 0x08, 0x07, 0x04, 0x00, 0x00, 0x00, 0x00},	/* 0, -16.0dB */
+	{0x09, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00},	/* 1, -15.5dB */
+	{0x0a, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00},	/* 2, -15.0dB */
+	{0x0a, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00},	/* 3, -14.5dB */
+	{0x0b, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00},	/* 4, -14.0dB */
+	{0x0b, 0x0b, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00},	/* 5, -13.5dB */
+	{0x0c, 0x0c, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00},	/* 6, -13.0dB */
+	{0x0d, 0x0c, 0x0b, 0x06, 0x00, 0x00, 0x00, 0x00},	/* 7, -12.5dB */
+	{0x0d, 0x0d, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00},	/* 8, -12.0dB */
+	{0x0e, 0x0e, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00},	/* 9, -11.5dB */
+	{0x0f, 0x0f, 0x0d, 0x08, 0x00, 0x00, 0x00, 0x00},	/* 10, -11.0dB */
+	{0x10, 0x10, 0x0e, 0x08, 0x00, 0x00, 0x00, 0x00},	/* 11, -10.5dB */
+	{0x11, 0x11, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00},	/* 12, -10.0dB */
+	{0x12, 0x12, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00},	/* 13, -9.5dB */
+	{0x13, 0x13, 0x10, 0x0a, 0x00, 0x00, 0x00, 0x00},	/* 14, -9.0dB */
+	{0x14, 0x14, 0x11, 0x0a, 0x00, 0x00, 0x00, 0x00},	/* 15, -8.5dB */
+	{0x16, 0x15, 0x12, 0x0b, 0x00, 0x00, 0x00, 0x00},	/* 16, -8.0dB */
+	{0x17, 0x16, 0x13, 0x0b, 0x00, 0x00, 0x00, 0x00},	/* 17, -7.5dB */
+	{0x18, 0x17, 0x15, 0x0c, 0x00, 0x00, 0x00, 0x00},	/* 18, -7.0dB */
+	{0x1a, 0x19, 0x16, 0x0d, 0x00, 0x00, 0x00, 0x00},	/* 19, -6.5dB */
+	{0x1c, 0x1a, 0x18, 0x0e, 0x00, 0x00, 0x00, 0x00},	/* 20, -6.0dB */
+	{0x1d, 0x1c, 0x18, 0x0e, 0x00, 0x00, 0x00, 0x00},	/* 21, -5.5dB */
+	{0x1f, 0x1e, 0x1a, 0x0f, 0x00, 0x00, 0x00, 0x00},	/* 22, -5.0dB */
+	{0x20, 0x20, 0x1b, 0x10, 0x00, 0x00, 0x00, 0x00},	/* 23, -4.5dB */
+	{0x22, 0x21, 0x1d, 0x11, 0x00, 0x00, 0x00, 0x00},	/* 24, -4.0dB */
+	{0x24, 0x23, 0x1f, 0x12, 0x00, 0x00, 0x00, 0x00},	/* 25, -3.5dB */
+	{0x26, 0x25, 0x21, 0x13, 0x00, 0x00, 0x00, 0x00},	/* 26, -3.0dB */
+	{0x28, 0x28, 0x24, 0x14, 0x00, 0x00, 0x00, 0x00},	/* 27, -2.5dB */
+	{0x2b, 0x2a, 0x25, 0x15, 0x00, 0x00, 0x00, 0x00},	/* 28, -2.0dB */
+	{0x2d, 0x2d, 0x17, 0x17, 0x00, 0x00, 0x00, 0x00},	/* 29, -1.5dB */
+	{0x30, 0x2f, 0x29, 0x18, 0x00, 0x00, 0x00, 0x00},	/* 30, -1.0dB */
+	{0x33, 0x32, 0x2b, 0x19, 0x00, 0x00, 0x00, 0x00},	/* 31, -0.5dB */
+	{0x36, 0x35, 0x2e, 0x1b, 0x00, 0x00, 0x00, 0x00}	/* 32, +0dB */
+};
+
+u8 cck_swing_table_ch1_ch14_88f[CCK_TABLE_SIZE_88F][16] = {
+	{0x16, 0x15, 0x13, 0x10, 0xD, 0x9, 0x6, 0x3, 0x2, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},        /* 0  -16dB */
+	{0x18, 0x17, 0x15, 0x12, 0xE, 0xA, 0x7, 0x4, 0x2, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},        /* 1  -15.5dB */
+	{0x1B, 0x1A, 0x18, 0x14, 0x10, 0xB, 0x7, 0x4, 0x2, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},        /* 2  -15dB */
+	{0x1F, 0x1E, 0x1B, 0x17, 0x12, 0xD, 0x8, 0x5, 0x2, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},        /* 3  -14.5dB */
+	{0x22, 0x21, 0x1E, 0x19, 0x14, 0xE, 0x9, 0x5, 0x3, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},        /* 4  -14dB */
+	{0x26, 0x25, 0x22, 0x1C, 0x16, 0x10, 0xA, 0x6, 0x3, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},        /* 5  -13.5dB */
+	{0x2B, 0x2A, 0x26, 0x20, 0x19, 0x12, 0xC, 0x7, 0x3, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},        /* 6  -13dB */
+	{0x30, 0x2F, 0x2A, 0x24, 0x1C, 0x14, 0xD, 0x8, 0x4, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},        /* 7  -12.5dB */
+	{0x36, 0x34, 0x2F, 0x28, 0x1F, 0x17, 0xF, 0x9, 0x4, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},        /* 8  -12dB */
+	{0x3D, 0x3B, 0x35, 0x2D, 0x23, 0x19, 0x11, 0xA, 0x5, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},        /* 9  -11.5dB */
+	{0x44, 0x42, 0x3C, 0x33, 0x28, 0x1C, 0x13, 0xB, 0x5, 0x2, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},        /* 10  -11dB */
+	{0x4D, 0x4A, 0x43, 0x39, 0x2C, 0x20, 0x15, 0xC, 0x6, 0x2, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},        /* 11  -10.5dB */
+	{0x56, 0x53, 0x4B, 0x40, 0x32, 0x24, 0x17, 0xE, 0x6, 0x2, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},        /* 12  -10dB */
+	{0x60, 0x5D, 0x54, 0x47, 0x38, 0x28, 0x1A, 0xF, 0x7, 0x2, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},        /* 13  -9.5dB */
+	{0x6C, 0x69, 0x5F, 0x50, 0x3F, 0x2D, 0x1E, 0x11, 0x8, 0x3, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},        /* 14  -9dB */
+	{0x79, 0x76, 0x6A, 0x5A, 0x46, 0x33, 0x21, 0x13, 0x9, 0x3, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},        /* 15  -8.5dB */
+	{0x88, 0x84, 0x77, 0x65, 0x4F, 0x39, 0x25, 0x15, 0xA, 0x3, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},        /* 16  -8dB */
+	{0x99, 0x94, 0x86, 0x71, 0x58, 0x40, 0x2A, 0x18, 0xB, 0x4, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},        /* 17  -7.5dB */
+	{0xAC, 0xA6, 0x96, 0x7F, 0x63, 0x47, 0x2F, 0x1B, 0xD, 0x4, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},        /* 18  -7dB */
+	{0xC1, 0xBA, 0xA8, 0x8F, 0x6F, 0x50, 0x35, 0x1E, 0xE, 0x4, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},        /* 19  -6.5dB */
+	{0xD8, 0xD1, 0xBD, 0xA0, 0x7D, 0x5A, 0x3B, 0x22, 0x10, 0x5, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}      /* 20  -6dB */
+};
+
+
+u8 cck_swing_table_ch1_ch13_88f[CCK_TABLE_SIZE_88F][16] = {
+	{0x16, 0x15, 0x13, 0x10, 0xD, 0x9, 0x6, 0x3, 0x2, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},        /* 0  -16dB */
+	{0x18, 0x17, 0x15, 0x12, 0xE, 0xA, 0x7, 0x4, 0x2, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},        /* 1  -15.5dB */
+	{0x1B, 0x1A, 0x18, 0x14, 0x10, 0xB, 0x7, 0x4, 0x2, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},        /* 2  -15dB */
+	{0x1F, 0x1E, 0x1B, 0x17, 0x12, 0xD, 0x8, 0x5, 0x2, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},        /* 3  -14.5dB */
+	{0x22, 0x21, 0x1E, 0x19, 0x14, 0xE, 0x9, 0x5, 0x3, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},        /* 4  -14dB */
+	{0x26, 0x25, 0x22, 0x1C, 0x16, 0x10, 0xA, 0x6, 0x3, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},        /* 5  -13.5dB */
+	{0x2B, 0x2A, 0x26, 0x20, 0x19, 0x12, 0xC, 0x7, 0x3, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},        /* 6  -13dB */
+	{0x30, 0x2F, 0x2A, 0x24, 0x1C, 0x14, 0xD, 0x8, 0x4, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},        /* 7  -12.5dB */
+	{0x36, 0x34, 0x2F, 0x28, 0x1F, 0x17, 0xF, 0x9, 0x4, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},        /* 8  -12dB */
+	{0x3D, 0x3B, 0x35, 0x2D, 0x23, 0x19, 0x11, 0xA, 0x5, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},        /* 9  -11.5dB */
+	{0x44, 0x42, 0x3C, 0x33, 0x28, 0x1C, 0x13, 0xB, 0x5, 0x2, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},        /* 10  -11dB */
+	{0x4D, 0x4A, 0x43, 0x39, 0x2C, 0x20, 0x15, 0xC, 0x6, 0x2, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},        /* 11  -10.5dB */
+	{0x56, 0x53, 0x4B, 0x40, 0x32, 0x24, 0x17, 0xE, 0x6, 0x2, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},        /* 12  -10dB */
+	{0x60, 0x5D, 0x54, 0x47, 0x38, 0x28, 0x1A, 0xF, 0x7, 0x2, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},        /* 13  -9.5dB */
+	{0x6C, 0x69, 0x5F, 0x50, 0x3F, 0x2D, 0x1E, 0x11, 0x8, 0x3, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},        /* 14  -9dB */
+	{0x79, 0x76, 0x6A, 0x5A, 0x46, 0x33, 0x21, 0x13, 0x9, 0x3, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},        /* 15  -8.5dB */
+	{0x88, 0x84, 0x77, 0x65, 0x4F, 0x39, 0x25, 0x15, 0xA, 0x3, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},        /* 16  -8dB */
+	{0x99, 0x94, 0x86, 0x71, 0x58, 0x40, 0x2A, 0x18, 0xB, 0x4, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},        /* 17  -7.5dB */
+	{0xAC, 0xA6, 0x96, 0x7F, 0x63, 0x47, 0x2F, 0x1B, 0xD, 0x4, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},        /* 18  -7dB */
+	{0xC1, 0xBA, 0xA8, 0x8F, 0x6F, 0x50, 0x35, 0x1E, 0xE, 0x4, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},        /* 19  -6.5dB */
+	{0xD8, 0xD1, 0xBD, 0xA0, 0x7D, 0x5A, 0x3B, 0x22, 0x10, 0x5, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}      /* 20  -6dB */
+};
+
+
+u8 cck_swing_table_ch14_88f[CCK_TABLE_SIZE_88F][16] = {
+	{0x44,	 0x42, 0x3C, 0x28, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-16dB*/
+	{0x48, 0x46, 0x3F, 0x2A, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-15.5dB*/
+	{0x4D, 0x4A, 0x43, 0x2C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-15dB*/
+	{0x51, 0x4F, 0x47, 0x2F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},	    /*-14.5dB*/
+	{0x56, 0x53, 0x4B, 0x32, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-14dB*/
+	{0x5B, 0x58, 0x50, 0x35, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-13.5dB*/
+	{0x60, 0x5D, 0x54, 0x38, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-13dB*/
+	{0x66, 0x63, 0x59, 0x3B, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-12.5dB*/
+	{0x6C, 0x69, 0x5F, 0x3F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-12dB*/
+	{0x73, 0x6F, 0x64, 0x42, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-11.5dB*/
+	{0x79, 0x76, 0x6A, 0x46, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-11dB*/
+	{0x81, 0x7C, 0x71, 0x4A, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-10.5dB*/
+	{0x88, 0x84, 0x77, 0x4F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-10dB*/
+	{0x90, 0x8C, 0x7E, 0x54, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-9.5dB*/
+	{0x99, 0x94, 0x86, 0x58, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-9dB*/
+	{0xA2, 0x9D, 0x8E, 0x5E, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-8.5dB*/
+	{0xAC, 0xA6, 0x96, 0x63, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-8dB*/
+	{0xB6, 0xB0, 0x9F, 0x69, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-7.5dB*/
+	{0xC1, 0xBA, 0xA8, 0x6F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-7dB*/
+	{0xCC, 0xC5, 0xB2, 0x76, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-6.5dB*/
+	{0xD8, 0xD1, 0xBD, 0x7D, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}     /*-6dB*/
+};
+
+/* Winnita ADD 20171113 PathA 0xAB4[10:0],PathB 0xAB4[21:11]*/
+u32 cck_swing_table_ch1_ch14_8192f[CCK_TABLE_SIZE_8192F] = {
+	0x0CD,			 /*0 ,    -20dB*/
+	0x0D9,
+	0x0E6,
+	0x0F3,
+	0x102,
+	0x111,
+	0x121,
+	0x132,
+	0x144,
+	0x158,
+	0x16C,
+	0x182,
+	0x198,
+	0x1B1,
+	0x1CA,
+	0x1E5,
+	0x202,
+	0x221,
+	0x241,
+	0x263,		/*19*/
+	0x287,		/*20*/
+	0x2AE,		/*21*/
+	0x2D6,		/*22*/
+	0x301,		/*23*/
+	0x32F,		/*24*/
+	0x35F,		/*25*/
+	0x392,		/*26*/
+	0x3C9,		/*27*/
+	0x402,		/*28*/
+	0x43F,		/*29*/
+	0x47F,		/*30*/
+	0x4C3,		/*31*/
+	0x50C,		/*32*/
+	0x558,		/*33*/
+	0x5A9,		/*34*/
+	0x5FF,		/*35*/
+	0x65A,		/*36*/
+	0x6BA,
+	0x720,
+	0x78C,
+	0x7FF,
+};
+
+
+#if 0
+u32 ofdm_swing_table_92e[OFDM_TABLE_SIZE_92E] = {
+	/* Index0   6  dB */ 0x7fc001ff,
+	/* Index1   5.7dB */ 0x7b4001ed,
+	/* Index2   5.4dB */ 0x774001dd,
+	/* Index3   5.1dB */ 0x734001cd,
+	/* Index4   4.8dB */ 0x6f4001bd,
+	/* Index5   4.5dB */ 0x6b8001ae,
+	/* Index6   4.2dB */ 0x67c0019f,
+	/* Index7   3.9dB */ 0x64400191,
+	/* Index8   3.6dB */ 0x60c00183,
+	/* Index9   3.3dB */ 0x5d800176,
+	/* Index10  3  dB */ 0x5a80016a,
+	/* Index11  2.7dB */ 0x5740015d,
+	/* Index12  2.4dB */ 0x54400151,
+	/* Index13  2.1dB */ 0x51800146,
+	/* Index14  1.8dB */ 0x4ec0013b,
+	/* Index15  1.5dB */ 0x4c000130,
+	/* Index16  1.2dB */ 0x49800126,
+	/* Index17  0.9dB */ 0x4700011c,
+	/* Index18  0.6dB */ 0x44800112,
+	/* Index19  0.3dB */ 0x42000108,
+	/* Index20  0  dB */ 0x40000100, /* 20 This is OFDM base index */
+	/* Index21 -0.3dB */ 0x3dc000f7,
+	/* Index22 -0.6dB */ 0x3bc000ef,
+	/* Index23 -0.9dB */ 0x39c000e7,
+	/* Index24 -1.2dB */ 0x37c000df,
+	/* Index25 -1.5dB */ 0x35c000d7,
+	/* Index26 -1.8dB */ 0x340000d0,
+	/* Index27 -2.1dB */ 0x324000c9,
+	/* Index28 -2.4dB */ 0x308000c2,
+	/* Index29 -2.7dB */ 0x2f0000bc,
+	/* Index30 -3  dB */ 0x2d4000b5,
+	/* Index31 -3.3dB */ 0x2bc000af,
+	/* Index32 -3.6dB */ 0x2a4000a9,
+	/* Index33 -3.9dB */ 0x28c000a3,
+	/* Index34 -4.2dB */ 0x2780009e,
+	/* Index35 -4.5dB */ 0x26000098,
+	/* Index36 -4.8dB */ 0x24c00093,
+	/* Index37 -5.1dB */ 0x2380008e,
+	/* Index38 -5.4dB */ 0x22400089,
+	/* Index39 -5.7dB */ 0x21400085,
+	/* Index40 -6  dB */ 0x20000080,
+	/* Index41 -6.3dB */ 0x1f00007c,
+	/* Index42 -6.6dB */ 0x1e000078,
+	/* Index43 -6.9dB */ 0x1d000074,
+	/* Index44 -7.2dB */ 0x1c000070,
+	/* Index45 -7.5dB */ 0x1b00006c,
+	/* Index46 -7.8dB */ 0x1a000068,
+	/* Index47 -8.1dB */ 0x19400065,
+	/* Index48 -8.4dB */ 0x18400061,
+	/* Index49 -8.7dB */ 0x1780005e,
+	/* Index50 -9  dB */ 0x16c0005b,
+	/* Index51 -9.3dB */ 0x16000058,
+	/* Index52 -9.6dB */ 0x15400055,
+	/* Index53 -9.9dB */ 0x14800052
+};
+u8 cck_swing_table_ch1_ch13_92e[CCK_TABLE_SIZE_92E][8] = {
+	/* Index0    0  dB */    {0x36, 0x34, 0x2E, 0x26, 0x1C, 0x12, 0x08, 0x04},
+	/* Index1   -0.3dB */    {0x34, 0x32, 0x2C, 0x25, 0x1B, 0x11, 0x08, 0x04},
+	/* Index2   -0.6dB */    {0x32, 0x30, 0x2B, 0x23, 0x1A, 0x11, 0x07, 0x04},
+	/* Index3   -0.9dB */    {0x31, 0x2F, 0x29, 0x22, 0x19, 0x10, 0x07, 0x04},
+	/* Index4   -1.2dB */    {0x2F, 0x2D, 0x28, 0x21, 0x18, 0x10, 0x07, 0x03},
+	/* Index5   -1.5dB */    {0x2D, 0x2C, 0x27, 0x20, 0x18, 0x0F, 0x07, 0x03},
+	/* Index6   -1.8dB */    {0x2C, 0x2A, 0x25, 0x1F, 0x17, 0x0F, 0x06, 0x03},
+	/* Index7   -2.1dB */    {0x2A, 0x29, 0x24, 0x1E, 0x16, 0x0E, 0x06, 0x03},
+	/* Index8   -2.4dB */    {0x29, 0x27, 0x23, 0x1D, 0x15, 0x0E, 0x06, 0x03},
+	/* Index9   -2.7dB */    {0x27, 0x26, 0x22, 0x1C, 0x14, 0x0D, 0x06, 0x03},
+	/* Index10  -3  dB */    {0x26, 0x25, 0x20, 0x1B, 0x14, 0x0D, 0x06, 0x03},
+	/* Index11  -3.3dB */    {0x25, 0x23, 0x1F, 0x1A, 0x13, 0x0C, 0x05, 0x03},
+	/* Index12  -3.6dB */    {0x24, 0x22, 0x1E, 0x19, 0x12, 0x0C, 0x05, 0x03},
+	/* Index13  -3.9dB */    {0x22, 0x21, 0x1D, 0x18, 0x12, 0x0B, 0x05, 0x03},
+	/* Index14  -4.2dB */    {0x21, 0x20, 0x1C, 0x17, 0x11, 0x0B, 0x05, 0x02},
+	/* Index15  -4.5dB */    {0x20, 0x1F, 0x1B, 0x17, 0x11, 0x0B, 0x05, 0x02},
+	/* Index16  -4.8dB */    {0x1F, 0x1E, 0x1A, 0x16, 0x10, 0x0A, 0x05, 0x02},
+	/* Index17  -5.1dB */    {0x1E, 0x1D, 0x1A, 0x15, 0x10, 0x0A, 0x04, 0x02},
+	/* Index18  -5.4dB */    {0x1D, 0x1C, 0x19, 0x14, 0x0F, 0x0A, 0x04, 0x02},
+	/* Index19  -5.7dB */    {0x1C, 0x1B, 0x18, 0x14, 0x0E, 0x09, 0x04, 0x02},
+	/* Index20  -6.0dB */    {0x1B, 0x1A, 0x17, 0x13, 0x0E, 0x09, 0x04, 0x02}, /* 20 This is CCK base index */
+	/* Index21  -6.3dB */    {0x1A, 0x19, 0x16, 0x12, 0x0E, 0x09, 0x04, 0x02},
+	/* Index22  -6.6dB */    {0x19, 0x18, 0x15, 0x12, 0x0D, 0x08, 0x04, 0x02},
+	/* Index23  -6.9dB */    {0x18, 0x17, 0x15, 0x11, 0x0D, 0x08, 0x04, 0x02},
+	/* Index24  -7.2dB */    {0x18, 0x17, 0x14, 0x11, 0x0C, 0x08, 0x03, 0x02},
+	/* Index25  -7.5dB */    {0x17, 0x16, 0x13, 0x10, 0x0C, 0x08, 0x03, 0x02},
+	/* Index26  -7.8dB */    {0x16, 0x15, 0x13, 0x0F, 0x0B, 0x07, 0x03, 0x02},
+	/* Index27  -8.1dB */    {0x15, 0x14, 0x12, 0x0F, 0x0B, 0x07, 0x03, 0x02},
+	/* Index28  -8.4dB */    {0x14, 0x14, 0x11, 0x0E, 0x0B, 0x07, 0x03, 0x02},
+	/* Index29  -8.7dB */    {0x14, 0x13, 0x11, 0x0E, 0x0A, 0x07, 0x03, 0x01},
+	/* Index30  -9.0dB */    {0x13, 0x12, 0x10, 0x0D, 0x0A, 0x06, 0x03, 0x01}, /* 30 This is hp CCK base index */
+	/* Index31  -9.3dB */    {0x12, 0x12, 0x0F, 0x0D, 0x0A, 0x06, 0x03, 0x01},
+	/* Index32  -9.6dB */    {0x12, 0x11, 0x0F, 0x0D, 0x09, 0x06, 0x03, 0x01},
+	/* Index33  -9.9dB */    {0x11, 0x11, 0x0F, 0x0C, 0x09, 0x06, 0x03, 0x01},
+	/* Index34 -10.2dB */    {0x11, 0x11, 0x0E, 0x0C, 0x09, 0x06, 0x02, 0x01},
+	/* Index35 -10.5dB */    {0x10, 0x0F, 0x0E, 0x0B, 0x08, 0x05, 0x02, 0x01},
+	/* Index36 -10.8dB */    {0x10, 0x0F, 0x0D, 0x0B, 0x08, 0x05, 0x02, 0x01},
+	/* Index37 -11.1dB */    {0x0F, 0x0E, 0x0D, 0x0A, 0x08, 0x05, 0x02, 0x01},
+	/* Index38 -11.4dB */    {0x0E, 0x0E, 0x0C, 0x0A, 0x07, 0x05, 0x02, 0x01},
+	/* Index39 -11.7dB */    {0x0E, 0x0D, 0x0C, 0x0A, 0x07, 0x05, 0x02, 0x01},
+	/* Index40 -12  dB */    {0x0E, 0x0D, 0x0C, 0x0A, 0x07, 0x05, 0x02, 0x01},
+	/* Index41 -12.3dB */    {0x0D, 0x0D, 0x0B, 0x09, 0x07, 0x04, 0x02, 0x01},
+	/* Index42 -12.6dB */    {0x0D, 0x0C, 0x0B, 0x09, 0x07, 0x04, 0x02, 0x01},
+	/* Index43 -12.9dB */    {0x0C, 0x0C, 0x0A, 0x09, 0x06, 0x04, 0x02, 0x01},
+	/* Index44 -13.2dB */    {0x0C, 0x0B, 0x0A, 0x08, 0x06, 0x04, 0x02, 0x01},
+	/* Index45 -13.5dB */    {0x0B, 0x0B, 0x0A, 0x08, 0x06, 0x04, 0x02, 0x01},
+	/* Index46 -13.8dB */    {0x0B, 0x0B, 0x09, 0x08, 0x06, 0x04, 0x02, 0x01},
+	/* Index47 -14.1dB */    {0x0B, 0x0A, 0x09, 0x07, 0x06, 0x04, 0x02, 0x01},
+	/* Index48 -14.4dB */    {0x0A, 0x0A, 0x09, 0x07, 0x05, 0x03, 0x02, 0x01},
+	/* Index49 -14.7dB */    {0x0A, 0x0A, 0x08, 0x07, 0x05, 0x03, 0x01, 0x01},
+	/* Index50 -15  dB */    {0x0A, 0x09, 0x08, 0x07, 0x05, 0x03, 0x01, 0x01},
+	/* Index51 -15.3dB */    {0x09, 0x09, 0x08, 0x06, 0x05, 0x03, 0x01, 0x01},
+	/* Index52 -15.6dB */    {0x09, 0x09, 0x08, 0x06, 0x05, 0x03, 0x01, 0x01},
+	/* Index53 -15.9dB */    {0x09, 0x08, 0x07, 0x06, 0x04, 0x03, 0x01, 0x01}
+};
+u8 cck_swing_table_ch14_92e[CCK_TABLE_SIZE_92E][8] = {
+	/* Index0    0  dB */    {0x36, 0x34, 0x2E, 0x26, 0x00, 0x00, 0x00, 0x00},
+	/* Index1   -0.3dB */    {0x34, 0x32, 0x2C, 0x25, 0x00, 0x00, 0x00, 0x00},
+	/* Index2   -0.6dB */    {0x32, 0x30, 0x2B, 0x23, 0x00, 0x00, 0x00, 0x00},
+	/* Index3   -0.9dB */    {0x31, 0x2F, 0x29, 0x22, 0x00, 0x00, 0x00, 0x00},
+	/* Index4   -1.2dB */    {0x2F, 0x2D, 0x28, 0x21, 0x00, 0x00, 0x00, 0x00},
+	/* Index5   -1.5dB */    {0x2D, 0x2C, 0x27, 0x20, 0x00, 0x00, 0x00, 0x00},
+	/* Index6   -1.8dB */    {0x2C, 0x2A, 0x25, 0x1F, 0x00, 0x00, 0x00, 0x00},
+	/* Index7   -2.1dB */    {0x2A, 0x29, 0x24, 0x1E, 0x00, 0x00, 0x00, 0x00},
+	/* Index8   -2.4dB */    {0x29, 0x27, 0x23, 0x1D, 0x00, 0x00, 0x00, 0x00},
+	/* Index9   -2.7dB */    {0x27, 0x26, 0x22, 0x1C, 0x00, 0x00, 0x00, 0x00},
+	/* Index10  -3  dB */    {0x26, 0x25, 0x20, 0x1B, 0x00, 0x00, 0x00, 0x00},
+	/* Index11  -3.3dB */    {0x25, 0x23, 0x1F, 0x1A, 0x00, 0x00, 0x00, 0x00},
+	/* Index12  -3.6dB */    {0x24, 0x22, 0x1E, 0x19, 0x00, 0x00, 0x00, 0x00},
+	/* Index13  -3.9dB */    {0x22, 0x21, 0x1D, 0x18, 0x00, 0x00, 0x00, 0x00},
+	/* Index14  -4.2dB */    {0x21, 0x20, 0x1C, 0x17, 0x00, 0x00, 0x00, 0x00},
+	/* Index15  -4.5dB */    {0x20, 0x1F, 0x1B, 0x17, 0x00, 0x00, 0x00, 0x00},
+	/* Index16  -4.8dB */    {0x1F, 0x1E, 0x1A, 0x16, 0x00, 0x00, 0x00, 0x00},
+	/* Index17  -5.1dB */    {0x1E, 0x1D, 0x1A, 0x15, 0x00, 0x00, 0x00, 0x00},
+	/* Index18  -5.4dB */    {0x1D, 0x1C, 0x19, 0x14, 0x00, 0x00, 0x00, 0x00},
+	/* Index19  -5.7dB */    {0x1C, 0x1B, 0x18, 0x14, 0x00, 0x00, 0x00, 0x00},
+	/* Index20  -6  dB */     {0x1B, 0x1A, 0x17, 0x13, 0x00, 0x00, 0x00, 0x00},
+	/* Index21  -6.3dB */    {0x1A, 0x19, 0x16, 0x12, 0x00, 0x00, 0x00, 0x00},
+	/* Index22  -6.6dB */    {0x19, 0x18, 0x15, 0x12, 0x00, 0x00, 0x00, 0x00},
+	/* Index23  -6.9dB */    {0x18, 0x17, 0x15, 0x11, 0x00, 0x00, 0x00, 0x00},
+	/* Index24  -7.2dB */    {0x18, 0x17, 0x14, 0x11, 0x00, 0x00, 0x00, 0x00},
+	/* Index25  -7.5dB */    {0x17, 0x16, 0x13, 0x10, 0x00, 0x00, 0x00, 0x00},
+	/* Index26  -7.8dB */    {0x16, 0x15, 0x13, 0x0F, 0x00, 0x00, 0x00, 0x00},
+	/* Index27  -8.1dB */    {0x15, 0x14, 0x12, 0x0F, 0x00, 0x00, 0x00, 0x00},
+	/* Index28  -8.4dB */    {0x14, 0x14, 0x11, 0x0E, 0x00, 0x00, 0x00, 0x00},
+	/* Index29  -8.7dB */    {0x14, 0x13, 0x11, 0x0E, 0x00, 0x00, 0x00, 0x00},
+	/* Index30  -9  dB */    {0x13, 0x12, 0x10, 0x0D, 0x00, 0x00, 0x00, 0x00},
+	/* Index31  -9.3dB */    {0x12, 0x12, 0x0F, 0x0D, 0x00, 0x00, 0x00, 0x00},
+	/* Index32  -9.6dB */    {0x12, 0x11, 0x0F, 0x0D, 0x00, 0x00, 0x00, 0x00},
+	/* Index33  -9.9dB */    {0x11, 0x11, 0x0F, 0x0C, 0x00, 0x00, 0x00, 0x00},
+	/* Index34 -10.2dB */    {0x11, 0x11, 0x0E, 0x0C, 0x00, 0x00, 0x00, 0x00},
+	/* Index35 -10.5dB */    {0x10, 0x0F, 0x0E, 0x0B, 0x00, 0x00, 0x00, 0x00},
+	/* Index36 -10.8dB */    {0x10, 0x0F, 0x0D, 0x0B, 0x00, 0x00, 0x00, 0x00},
+	/* Index37 -11.1dB */    {0x0F, 0x0E, 0x0D, 0x0A, 0x00, 0x00, 0x00, 0x00},
+	/* Index38 -11.4dB */    {0x0E, 0x0E, 0x0C, 0x0A, 0x00, 0x00, 0x00, 0x00},
+	/* Index39 -11.7dB */    {0x0E, 0x0D, 0x0C, 0x0A, 0x00, 0x00, 0x00, 0x00},
+	/* Index40 -12  dB */    {0x0E, 0x0D, 0x0C, 0x0A, 0x00, 0x00, 0x00, 0x00},
+	/* Index41 -12.3dB */    {0x0D, 0x0D, 0x0B, 0x09, 0x00, 0x00, 0x00, 0x00},
+	/* Index42 -12.6dB */    {0x0D, 0x0C, 0x0B, 0x09, 0x00, 0x00, 0x00, 0x00},
+	/* Index43 -12.9dB */    {0x0C, 0x0C, 0x0A, 0x09, 0x00, 0x00, 0x00, 0x00},
+	/* Index44 -13.2dB */    {0x0C, 0x0B, 0x0A, 0x08, 0x00, 0x00, 0x00, 0x00},
+	/* Index45 -13.5dB */    {0x0B, 0x0B, 0x0A, 0x08, 0x00, 0x00, 0x00, 0x00},
+	/* Index46 -13.8dB */    {0x0B, 0x0B, 0x09, 0x08, 0x00, 0x00, 0x00, 0x00},
+	/* Index47 -14.1dB */    {0x0B, 0x0A, 0x09, 0x07, 0x00, 0x00, 0x00, 0x00},
+	/* Index48 -14.4dB */    {0x0A, 0x0A, 0x09, 0x07, 0x00, 0x00, 0x00, 0x00},
+	/* Index49 -14.7dB */    {0x0A, 0x0A, 0x08, 0x07, 0x00, 0x00, 0x00, 0x00},
+	/* Index50 -15  dB */    {0x0A, 0x09, 0x08, 0x07, 0x00, 0x00, 0x00, 0x00},
+	/* Index51 -15.3dB */    {0x09, 0x09, 0x08, 0x06, 0x00, 0x00, 0x00, 0x00},
+	/* Index52 -15.6dB */    {0x09, 0x09, 0x08, 0x06, 0x00, 0x00, 0x00, 0x00},
+	/* Index53 -15.9dB */    {0x09, 0x08, 0x07, 0x06, 0x00, 0x00, 0x00, 0x00}
+};
+#endif
+#endif
+
+
+u8 delta_swing_table_idx_2ga_p_default[DELTA_SWINGIDX_SIZE] = {0, 0, 0, 0, 1, 1, 2, 2, 3, 3
+	, 4, 4, 4,  4,  4,  4,  4,  4,  5,  5,  7,  7,  8,  8,  8,  9,  9,  9,  9,  9
+							      };
+u8 delta_swing_table_idx_2ga_n_default[DELTA_SWINGIDX_SIZE] = {0, 0, 0, 2, 2, 3, 3, 4, 4, 4
+	, 4, 5, 5,  6,  6,  7,  7,  7,  7,  8,  8,  9,  9, 10, 10, 10, 11, 11, 11, 11
+							      };
+
+
+#ifdef CONFIG_WLAN_HAL_8192EE
+u32 ofdm_swing_table_92e[OFDM_TABLE_SIZE_92E] = {
+	/* Index0   6  dB */ 0x7fc001ff,
+	/* Index1   5.7dB */ 0x7b4001ed,
+	/* Index2   5.4dB */ 0x774001dd,
+	/* Index3   5.1dB */ 0x734001cd,
+	/* Index4   4.8dB */ 0x6f4001bd,
+	/* Index5   4.5dB */ 0x6b8001ae,
+	/* Index6   4.2dB */ 0x67c0019f,
+	/* Index7   3.9dB */ 0x64400191,
+	/* Index8   3.6dB */ 0x60c00183,
+	/* Index9   3.3dB */ 0x5d800176,
+	/* Index10  3  dB */ 0x5a80016a,
+	/* Index11  2.7dB */ 0x5740015d,
+	/* Index12  2.4dB */ 0x54400151,
+	/* Index13  2.1dB */ 0x51800146,
+	/* Index14  1.8dB */ 0x4ec0013b,
+	/* Index15  1.5dB */ 0x4c000130,
+	/* Index16  1.2dB */ 0x49800126,
+	/* Index17  0.9dB */ 0x4700011c,
+	/* Index18  0.6dB */ 0x44800112,
+	/* Index19  0.3dB */ 0x42000108,
+	/* Index20  0  dB */ 0x40000100, /* 20 This is OFDM base index */
+	/* Index21 -0.3dB */ 0x3dc000f7,
+	/* Index22 -0.6dB */ 0x3bc000ef,
+	/* Index23 -0.9dB */ 0x39c000e7,
+	/* Index24 -1.2dB */ 0x37c000df,
+	/* Index25 -1.5dB */ 0x35c000d7,
+	/* Index26 -1.8dB */ 0x340000d0,
+	/* Index27 -2.1dB */ 0x324000c9,
+	/* Index28 -2.4dB */ 0x308000c2,
+	/* Index29 -2.7dB */ 0x2f0000bc,
+	/* Index30 -3  dB */ 0x2d4000b5,
+	/* Index31 -3.3dB */ 0x2bc000af,
+	/* Index32 -3.6dB */ 0x2a4000a9,
+	/* Index33 -3.9dB */ 0x28c000a3,
+	/* Index34 -4.2dB */ 0x2780009e,
+	/* Index35 -4.5dB */ 0x26000098,
+	/* Index36 -4.8dB */ 0x24c00093,
+	/* Index37 -5.1dB */ 0x2380008e,
+	/* Index38 -5.4dB */ 0x22400089,
+	/* Index39 -5.7dB */ 0x21400085,
+	/* Index40 -6  dB */ 0x20000080,
+	/* Index41 -6.3dB */ 0x1f00007c,
+	/* Index42 -6.6dB */ 0x1e000078,
+	/* Index43 -6.9dB */ 0x1d000074,
+	/* Index44 -7.2dB */ 0x1c000070,
+	/* Index45 -7.5dB */ 0x1b00006c,
+	/* Index46 -7.8dB */ 0x1a000068,
+	/* Index47 -8.1dB */ 0x19400065,
+	/* Index48 -8.4dB */ 0x18400061,
+	/* Index49 -8.7dB */ 0x1780005e,
+	/* Index50 -9  dB */ 0x16c0005b,
+	/* Index51 -9.3dB */ 0x16000058,
+	/* Index52 -9.6dB */ 0x15400055,
+	/* Index53 -9.9dB */ 0x14800052
+};
+u8 cck_swing_table_ch1_ch13_92e[CCK_TABLE_SIZE_92E][8] = {
+	/* Index0    0  dB */    {0x36, 0x34, 0x2E, 0x26, 0x1C, 0x12, 0x08, 0x04},
+	/* Index1   -0.3dB */    {0x34, 0x32, 0x2C, 0x25, 0x1B, 0x11, 0x08, 0x04},
+	/* Index2   -0.6dB */    {0x32, 0x30, 0x2B, 0x23, 0x1A, 0x11, 0x07, 0x04},
+	/* Index3   -0.9dB */    {0x31, 0x2F, 0x29, 0x22, 0x19, 0x10, 0x07, 0x04},
+	/* Index4   -1.2dB */    {0x2F, 0x2D, 0x28, 0x21, 0x18, 0x10, 0x07, 0x03},
+	/* Index5   -1.5dB */    {0x2D, 0x2C, 0x27, 0x20, 0x18, 0x0F, 0x07, 0x03},
+	/* Index6   -1.8dB */    {0x2C, 0x2A, 0x25, 0x1F, 0x17, 0x0F, 0x06, 0x03},
+	/* Index7   -2.1dB */    {0x2A, 0x29, 0x24, 0x1E, 0x16, 0x0E, 0x06, 0x03},
+	/* Index8   -2.4dB */    {0x29, 0x27, 0x23, 0x1D, 0x15, 0x0E, 0x06, 0x03},
+	/* Index9   -2.7dB */    {0x27, 0x26, 0x22, 0x1C, 0x14, 0x0D, 0x06, 0x03},
+	/* Index10  -3  dB */    {0x26, 0x25, 0x20, 0x1B, 0x14, 0x0D, 0x06, 0x03},
+	/* Index11  -3.3dB */    {0x25, 0x23, 0x1F, 0x1A, 0x13, 0x0C, 0x05, 0x03},
+	/* Index12  -3.6dB */    {0x24, 0x22, 0x1E, 0x19, 0x12, 0x0C, 0x05, 0x03},
+	/* Index13  -3.9dB */    {0x22, 0x21, 0x1D, 0x18, 0x12, 0x0B, 0x05, 0x03},
+	/* Index14  -4.2dB */    {0x21, 0x20, 0x1C, 0x17, 0x11, 0x0B, 0x05, 0x02},
+	/* Index15  -4.5dB */    {0x20, 0x1F, 0x1B, 0x17, 0x11, 0x0B, 0x05, 0x02},
+	/* Index16  -4.8dB */    {0x1F, 0x1E, 0x1A, 0x16, 0x10, 0x0A, 0x05, 0x02},
+	/* Index17  -5.1dB */    {0x1E, 0x1D, 0x1A, 0x15, 0x10, 0x0A, 0x04, 0x02},
+	/* Index18  -5.4dB */    {0x1D, 0x1C, 0x19, 0x14, 0x0F, 0x0A, 0x04, 0x02},
+	/* Index19  -5.7dB */    {0x1C, 0x1B, 0x18, 0x14, 0x0E, 0x09, 0x04, 0x02},
+	/* Index20  -6.0dB */    {0x1B, 0x1A, 0x17, 0x13, 0x0E, 0x09, 0x04, 0x02}, /* 20 This is CCK base index */
+	/* Index21  -6.3dB */    {0x1A, 0x19, 0x16, 0x12, 0x0E, 0x09, 0x04, 0x02},
+	/* Index22  -6.6dB */    {0x19, 0x18, 0x15, 0x12, 0x0D, 0x08, 0x04, 0x02},
+	/* Index23  -6.9dB */    {0x18, 0x17, 0x15, 0x11, 0x0D, 0x08, 0x04, 0x02},
+	/* Index24  -7.2dB */    {0x18, 0x17, 0x14, 0x11, 0x0C, 0x08, 0x03, 0x02},
+	/* Index25  -7.5dB */    {0x17, 0x16, 0x13, 0x10, 0x0C, 0x08, 0x03, 0x02},
+	/* Index26  -7.8dB */    {0x16, 0x15, 0x13, 0x0F, 0x0B, 0x07, 0x03, 0x02},
+	/* Index27  -8.1dB */    {0x15, 0x14, 0x12, 0x0F, 0x0B, 0x07, 0x03, 0x02},
+	/* Index28  -8.4dB */    {0x14, 0x14, 0x11, 0x0E, 0x0B, 0x07, 0x03, 0x02},
+	/* Index29  -8.7dB */    {0x14, 0x13, 0x11, 0x0E, 0x0A, 0x07, 0x03, 0x01},
+	/* Index30  -9.0dB */    {0x13, 0x12, 0x10, 0x0D, 0x0A, 0x06, 0x03, 0x01}, /* 30 This is hp CCK base index */
+	/* Index31  -9.3dB */    {0x12, 0x12, 0x0F, 0x0D, 0x0A, 0x06, 0x03, 0x01},
+	/* Index32  -9.6dB */    {0x12, 0x11, 0x0F, 0x0D, 0x09, 0x06, 0x03, 0x01},
+	/* Index33  -9.9dB */    {0x11, 0x11, 0x0F, 0x0C, 0x09, 0x06, 0x03, 0x01},
+	/* Index34 -10.2dB */    {0x11, 0x11, 0x0E, 0x0C, 0x09, 0x06, 0x02, 0x01},
+	/* Index35 -10.5dB */    {0x10, 0x0F, 0x0E, 0x0B, 0x08, 0x05, 0x02, 0x01},
+	/* Index36 -10.8dB */    {0x10, 0x0F, 0x0D, 0x0B, 0x08, 0x05, 0x02, 0x01},
+	/* Index37 -11.1dB */    {0x0F, 0x0E, 0x0D, 0x0A, 0x08, 0x05, 0x02, 0x01},
+	/* Index38 -11.4dB */    {0x0E, 0x0E, 0x0C, 0x0A, 0x07, 0x05, 0x02, 0x01},
+	/* Index39 -11.7dB */    {0x0E, 0x0D, 0x0C, 0x0A, 0x07, 0x05, 0x02, 0x01},
+	/* Index40 -12  dB */    {0x0E, 0x0D, 0x0C, 0x0A, 0x07, 0x05, 0x02, 0x01},
+	/* Index41 -12.3dB */    {0x0D, 0x0D, 0x0B, 0x09, 0x07, 0x04, 0x02, 0x01},
+	/* Index42 -12.6dB */    {0x0D, 0x0C, 0x0B, 0x09, 0x07, 0x04, 0x02, 0x01},
+	/* Index43 -12.9dB */    {0x0C, 0x0C, 0x0A, 0x09, 0x06, 0x04, 0x02, 0x01},
+	/* Index44 -13.2dB */    {0x0C, 0x0B, 0x0A, 0x08, 0x06, 0x04, 0x02, 0x01},
+	/* Index45 -13.5dB */    {0x0B, 0x0B, 0x0A, 0x08, 0x06, 0x04, 0x02, 0x01},
+	/* Index46 -13.8dB */    {0x0B, 0x0B, 0x09, 0x08, 0x06, 0x04, 0x02, 0x01},
+	/* Index47 -14.1dB */    {0x0B, 0x0A, 0x09, 0x07, 0x06, 0x04, 0x02, 0x01},
+	/* Index48 -14.4dB */    {0x0A, 0x0A, 0x09, 0x07, 0x05, 0x03, 0x02, 0x01},
+	/* Index49 -14.7dB */    {0x0A, 0x0A, 0x08, 0x07, 0x05, 0x03, 0x01, 0x01},
+	/* Index50 -15  dB */    {0x0A, 0x09, 0x08, 0x07, 0x05, 0x03, 0x01, 0x01},
+	/* Index51 -15.3dB */    {0x09, 0x09, 0x08, 0x06, 0x05, 0x03, 0x01, 0x01},
+	/* Index52 -15.6dB */    {0x09, 0x09, 0x08, 0x06, 0x05, 0x03, 0x01, 0x01},
+	/* Index53 -15.9dB */    {0x09, 0x08, 0x07, 0x06, 0x04, 0x03, 0x01, 0x01}
+};
+u8 cck_swing_table_ch14_92e[CCK_TABLE_SIZE_92E][8] = {
+	/* Index0    0  dB */    {0x36, 0x34, 0x2E, 0x26, 0x00, 0x00, 0x00, 0x00},
+	/* Index1   -0.3dB */    {0x34, 0x32, 0x2C, 0x25, 0x00, 0x00, 0x00, 0x00},
+	/* Index2   -0.6dB */    {0x32, 0x30, 0x2B, 0x23, 0x00, 0x00, 0x00, 0x00},
+	/* Index3   -0.9dB */    {0x31, 0x2F, 0x29, 0x22, 0x00, 0x00, 0x00, 0x00},
+	/* Index4   -1.2dB */    {0x2F, 0x2D, 0x28, 0x21, 0x00, 0x00, 0x00, 0x00},
+	/* Index5   -1.5dB */    {0x2D, 0x2C, 0x27, 0x20, 0x00, 0x00, 0x00, 0x00},
+	/* Index6   -1.8dB */    {0x2C, 0x2A, 0x25, 0x1F, 0x00, 0x00, 0x00, 0x00},
+	/* Index7   -2.1dB */    {0x2A, 0x29, 0x24, 0x1E, 0x00, 0x00, 0x00, 0x00},
+	/* Index8   -2.4dB */    {0x29, 0x27, 0x23, 0x1D, 0x00, 0x00, 0x00, 0x00},
+	/* Index9   -2.7dB */    {0x27, 0x26, 0x22, 0x1C, 0x00, 0x00, 0x00, 0x00},
+	/* Index10  -3  dB */    {0x26, 0x25, 0x20, 0x1B, 0x00, 0x00, 0x00, 0x00},
+	/* Index11  -3.3dB */    {0x25, 0x23, 0x1F, 0x1A, 0x00, 0x00, 0x00, 0x00},
+	/* Index12  -3.6dB */    {0x24, 0x22, 0x1E, 0x19, 0x00, 0x00, 0x00, 0x00},
+	/* Index13  -3.9dB */    {0x22, 0x21, 0x1D, 0x18, 0x00, 0x00, 0x00, 0x00},
+	/* Index14  -4.2dB */    {0x21, 0x20, 0x1C, 0x17, 0x00, 0x00, 0x00, 0x00},
+	/* Index15  -4.5dB */    {0x20, 0x1F, 0x1B, 0x17, 0x00, 0x00, 0x00, 0x00},
+	/* Index16  -4.8dB */    {0x1F, 0x1E, 0x1A, 0x16, 0x00, 0x00, 0x00, 0x00},
+	/* Index17  -5.1dB */    {0x1E, 0x1D, 0x1A, 0x15, 0x00, 0x00, 0x00, 0x00},
+	/* Index18  -5.4dB */    {0x1D, 0x1C, 0x19, 0x14, 0x00, 0x00, 0x00, 0x00},
+	/* Index19  -5.7dB */    {0x1C, 0x1B, 0x18, 0x14, 0x00, 0x00, 0x00, 0x00},
+	/* Index20  -6  dB */     {0x1B, 0x1A, 0x17, 0x13, 0x00, 0x00, 0x00, 0x00},
+	/* Index21  -6.3dB */    {0x1A, 0x19, 0x16, 0x12, 0x00, 0x00, 0x00, 0x00},
+	/* Index22  -6.6dB */    {0x19, 0x18, 0x15, 0x12, 0x00, 0x00, 0x00, 0x00},
+	/* Index23  -6.9dB */    {0x18, 0x17, 0x15, 0x11, 0x00, 0x00, 0x00, 0x00},
+	/* Index24  -7.2dB */    {0x18, 0x17, 0x14, 0x11, 0x00, 0x00, 0x00, 0x00},
+	/* Index25  -7.5dB */    {0x17, 0x16, 0x13, 0x10, 0x00, 0x00, 0x00, 0x00},
+	/* Index26  -7.8dB */    {0x16, 0x15, 0x13, 0x0F, 0x00, 0x00, 0x00, 0x00},
+	/* Index27  -8.1dB */    {0x15, 0x14, 0x12, 0x0F, 0x00, 0x00, 0x00, 0x00},
+	/* Index28  -8.4dB */    {0x14, 0x14, 0x11, 0x0E, 0x00, 0x00, 0x00, 0x00},
+	/* Index29  -8.7dB */    {0x14, 0x13, 0x11, 0x0E, 0x00, 0x00, 0x00, 0x00},
+	/* Index30  -9  dB */    {0x13, 0x12, 0x10, 0x0D, 0x00, 0x00, 0x00, 0x00},
+	/* Index31  -9.3dB */    {0x12, 0x12, 0x0F, 0x0D, 0x00, 0x00, 0x00, 0x00},
+	/* Index32  -9.6dB */    {0x12, 0x11, 0x0F, 0x0D, 0x00, 0x00, 0x00, 0x00},
+	/* Index33  -9.9dB */    {0x11, 0x11, 0x0F, 0x0C, 0x00, 0x00, 0x00, 0x00},
+	/* Index34 -10.2dB */    {0x11, 0x11, 0x0E, 0x0C, 0x00, 0x00, 0x00, 0x00},
+	/* Index35 -10.5dB */    {0x10, 0x0F, 0x0E, 0x0B, 0x00, 0x00, 0x00, 0x00},
+	/* Index36 -10.8dB */    {0x10, 0x0F, 0x0D, 0x0B, 0x00, 0x00, 0x00, 0x00},
+	/* Index37 -11.1dB */    {0x0F, 0x0E, 0x0D, 0x0A, 0x00, 0x00, 0x00, 0x00},
+	/* Index38 -11.4dB */    {0x0E, 0x0E, 0x0C, 0x0A, 0x00, 0x00, 0x00, 0x00},
+	/* Index39 -11.7dB */    {0x0E, 0x0D, 0x0C, 0x0A, 0x00, 0x00, 0x00, 0x00},
+	/* Index40 -12  dB */    {0x0E, 0x0D, 0x0C, 0x0A, 0x00, 0x00, 0x00, 0x00},
+	/* Index41 -12.3dB */    {0x0D, 0x0D, 0x0B, 0x09, 0x00, 0x00, 0x00, 0x00},
+	/* Index42 -12.6dB */    {0x0D, 0x0C, 0x0B, 0x09, 0x00, 0x00, 0x00, 0x00},
+	/* Index43 -12.9dB */    {0x0C, 0x0C, 0x0A, 0x09, 0x00, 0x00, 0x00, 0x00},
+	/* Index44 -13.2dB */    {0x0C, 0x0B, 0x0A, 0x08, 0x00, 0x00, 0x00, 0x00},
+	/* Index45 -13.5dB */    {0x0B, 0x0B, 0x0A, 0x08, 0x00, 0x00, 0x00, 0x00},
+	/* Index46 -13.8dB */    {0x0B, 0x0B, 0x09, 0x08, 0x00, 0x00, 0x00, 0x00},
+	/* Index47 -14.1dB */    {0x0B, 0x0A, 0x09, 0x07, 0x00, 0x00, 0x00, 0x00},
+	/* Index48 -14.4dB */    {0x0A, 0x0A, 0x09, 0x07, 0x00, 0x00, 0x00, 0x00},
+	/* Index49 -14.7dB */    {0x0A, 0x0A, 0x08, 0x07, 0x00, 0x00, 0x00, 0x00},
+	/* Index50 -15  dB */    {0x0A, 0x09, 0x08, 0x07, 0x00, 0x00, 0x00, 0x00},
+	/* Index51 -15.3dB */    {0x09, 0x09, 0x08, 0x06, 0x00, 0x00, 0x00, 0x00},
+	/* Index52 -15.6dB */    {0x09, 0x09, 0x08, 0x06, 0x00, 0x00, 0x00, 0x00},
+	/* Index53 -15.9dB */    {0x09, 0x08, 0x07, 0x06, 0x00, 0x00, 0x00, 0x00}
+};
+#endif
+
+#if (RTL8814A_SUPPORT == 1 || RTL8822B_SUPPORT == 1 ||\
+	RTL8821C_SUPPORT == 1 || RTL8198F_SUPPORT == 1)
+u32 tx_scaling_table_jaguar[TXSCALE_TABLE_SIZE] = {
+	0x081, /* 0,  -12.0dB */
+	0x088, /* 1,  -11.5dB */
+	0x090, /* 2,  -11.0dB */
+	0x099, /* 3,  -10.5dB */
+	0x0A2, /* 4,  -10.0dB */
+	0x0AC, /* 5,  -9.5dB */
+	0x0B6, /* 6,  -9.0dB */
+	0x0C0, /* 7,  -8.5dB */
+	0x0CC, /* 8,  -8.0dB */
+	0x0D8, /* 9,  -7.5dB */
+	0x0E5, /* 10, -7.0dB */
+	0x0F2, /* 11, -6.5dB */
+	0x101, /* 12, -6.0dB */
+	0x110, /* 13, -5.5dB */
+	0x120, /* 14, -5.0dB */
+	0x131, /* 15, -4.5dB */
+	0x143, /* 16, -4.0dB */
+	0x156, /* 17, -3.5dB */
+	0x16A, /* 18, -3.0dB */
+	0x180, /* 19, -2.5dB */
+	0x197, /* 20, -2.0dB */
+	0x1AF, /* 21, -1.5dB */
+	0x1C8, /* 22, -1.0dB */
+	0x1E3, /* 23, -0.5dB */
+	0x200, /* 24, +0  dB */
+	0x21E, /* 25, +0.5dB */
+	0x23E, /* 26, +1.0dB */
+	0x261, /* 27, +1.5dB */
+	0x285, /* 28, +2.0dB */
+	0x2AB, /* 29, +2.5dB */
+	0x2D3, /* 30, +3.0dB */
+	0x2FE, /* 31, +3.5dB */
+	0x32B, /* 32, +4.0dB */
+	0x35C, /* 33, +4.5dB */
+	0x38E, /* 34, +5.0dB */
+	0x3C4, /* 35, +5.5dB */
+	0x3FE  /* 36, +6.0dB */
+};
+#elif(ODM_IC_11AC_SERIES_SUPPORT)
+u32 ofdm_swing_table_8812[OFDM_TABLE_SIZE_8812] = {
+	0x3FE, /* 0,  (6dB) */
+	0x3C4, /* 1,  (5.5dB) */
+	0x38E, /* 2,  (5dB) */
+	0x35C, /* 3,  (4.5dB) */
+	0x32B, /* 4,  (4dB) */
+	0x2FE, /* 5,  (3.5dB) */
+	0x2D3, /* 6,  (3dB) */
+	0x2AB, /* 7,  (2.5dB) */
+	0x285, /* 8,  (2dB) */
+	0x261, /* 9,  (1.5dB */
+	0x23E, /* 10, (1dB) */
+	0x21E, /* 11, (0.5dB) */
+	0x200, /* 12, (0dB)		8814 int PA 2G default */
+	0x1E3, /* 13, (-0.5dB) */
+	0x1C8, /* 14, (-1dB) */
+	0x1AF, /* 15, (-1.5dB) */
+	0x197, /* 16, (-2dB) */
+	0x180, /* 17, (-2.5dB) */
+	0x16A, /* 18, (-3dB)		8812 / 8814 int PA 5G / 8814 ext PA 2G5G default */
+	0x156, /* 19, (-3.5dB) */
+	0x143, /* 20, (-4dB)		8812 HP default */
+	0x131, /* 21, (-4.5dB) */
+	0x120, /* 22, (-5dB) */
+	0x110, /* 23, (-5.5dB) */
+	0x101, /* 24, (-6dB) */
+	0x0F2, /* 25, (-6.5dB) */
+	0x0E5, /* 26, (-7dB) */
+	0x0D8, /* 27, (-7.5dB) */
+	0x0CC, /* 28, (-8dB) */
+	0x0C0, /* 29, (-8.5dB) */
+	0x0B6, /* 30, (-9dB) */
+	0x0AC, /* 31, (-9.5dB) */
+	0x0A2, /* 32, (-10dB) */
+	0x099, /* 33, (-10.5dB) */
+	0x090, /* 34, (-11dB) */
+	0x088, /* 35, (-11.5dB) */
+	0x081, /* 36, (-12dB) */
+	0x079, /* 37, (-12.5dB) */
+	0x072, /* 38, (-13dB) */
+	0x06c, /* 39, (-13.5dB) */
+	0x066, /* 40, (-14dB) */
+	0x060, /* 41, (-14.5dB) */
+	0x05B  /* 42, (-15dB) */
+};
+#endif
+
+u32 cck_swing_table_ch1_ch14_8723d[CCK_TABLE_SIZE_8723D] = {
+	0x0CD,
+	0x0D9,
+	0x0E6,
+	0x0F3,
+	0x102,
+	0x111,
+	0x121,
+	0x132,
+	0x144,
+	0x158,
+	0x16C,
+	0x182,
+	0x198,
+	0x1B1,
+	0x1CA,
+	0x1E5,
+	0x202,
+	0x221,
+	0x241,
+	0x263,
+	0x287,
+	0x2AE,
+	0x2D6,
+	0x301,
+	0x32F,
+	0x35F,
+	0x392,
+	0x3C9,
+	0x402,
+	0x43F,
+	0x47F,
+	0x4C3,
+	0x50C,
+	0x558,
+	0x5A9,
+	0x5FF,
+	0x65A,
+	0x6BA,
+	0x720,
+	0x78C,
+	0x7FF,
+};
+/* JJ ADD 20161014 */
+u32 cck_swing_table_ch1_ch14_8710b[CCK_TABLE_SIZE_8710B] = {
+	0x0CD,
+	0x0D9,
+	0x0E6,
+	0x0F3,
+	0x102,
+	0x111,
+	0x121,
+	0x132,
+	0x144,
+	0x158,
+	0x16C,
+	0x182,
+	0x198,
+	0x1B1,
+	0x1CA,
+	0x1E5,
+	0x202,
+	0x221,
+	0x241,
+	0x263,
+	0x287,
+	0x2AE,
+	0x2D6,
+	0x301,
+	0x32F,
+	0x35F,
+	0x392,
+	0x3C9,
+	0x402,
+	0x43F,
+	0x47F,
+	0x4C3,
+	0x50C,
+	0x558,
+	0x5A9,
+	0x5FF,
+	0x65A,
+	0x6BA,
+	0x720,
+	0x78C,
+	0x7FF,
+};
+
+
+/* #endif */
+/* 3============================================================
+ * 3 Tx Power Tracking
+ * 3============================================================ */
+
+void
+odm_txpowertracking_init(
+	void		*dm_void
+)
+{
+	struct dm_struct		*dm = (struct dm_struct *)dm_void;
+#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
+	if (!(dm->support_ic_type & (ODM_RTL8814A | ODM_RTL8822B | ODM_IC_11N_SERIES)))
+		return;
+#endif
+
+	odm_txpowertracking_thermal_meter_init(dm);
+}
+
+
+u8
+get_swing_index(
+	void		*dm_void
+)
+{
+	struct dm_struct		*dm = (struct dm_struct *)dm_void;
+	u8			i = 0, bb_swing_mask = 0;
+	u32			bb_swing = 0;
+	u32			swing_table_size = 0;
+	u32			*swing_table = 0;
+	struct rtl8192cd_priv	*priv = dm->priv;
+
+#if (RTL8197F_SUPPORT == 1)
+	if (GET_CHIP_VER(priv) == VERSION_8197F) {
+		bb_swing = phy_query_bb_reg(priv, REG_OFDM_0_XA_TX_IQ_IMBALANCE, MASKOFDM_D);
+		swing_table = ofdm_swing_table_new;
+		swing_table_size = OFDM_TABLE_SIZE_92D;
+		bb_swing_mask = 22;
+	}
+#endif
+
+#if (RTL8192F_SUPPORT == 1)
+	if (GET_CHIP_VER(priv) == VERSION_8192F) {
+		bb_swing = phy_query_bb_reg(priv, REG_OFDM_0_XA_TX_IQ_IMBALANCE, MASKOFDM_D);
+		swing_table = ofdm_swing_table_new;
+		swing_table_size = OFDM_TABLE_SIZE_92D;
+		bb_swing_mask = 22;
+	}
+#endif
+
+#if (RTL8822B_SUPPORT == 1)
+	if (GET_CHIP_VER(priv) == VERSION_8822B) {
+		bb_swing = phy_query_bb_reg(priv, REG_A_TX_SCALE_JAGUAR, 0xFFE00000);
+		swing_table = tx_scaling_table_jaguar;
+		swing_table_size = TXSCALE_TABLE_SIZE;
+		bb_swing_mask = 0;
+	}
+#endif
+
+	for (i = 0; i < swing_table_size - 1; i++) {
+		u32 table_value = swing_table[i] >> bb_swing_mask;
+
+		if (bb_swing == table_value)
+			break;
+	}
+
+	RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "bb_swing=0x%x bbswing_index=%d\n", bb_swing, i);
+
+
+	return i;
+}
+
+
+void
+odm_txpowertracking_thermal_meter_init(
+	void		*dm_void
+)
+{
+	struct dm_struct		*dm = (struct dm_struct *)dm_void;
+	struct dm_rf_calibration_struct	*cali_info = &(dm->rf_calibrate_info);
+	struct rtl8192cd_priv		*priv = dm->priv;
+	u8 p;
+	u8 default_swing_index;
+#if (RTL8197F_SUPPORT == 1 || RTL8822B_SUPPORT == 1 || RTL8192F_SUPPORT == 1)
+	if ((GET_CHIP_VER(priv) == VERSION_8197F) || (GET_CHIP_VER(priv) == VERSION_8822B) ||(GET_CHIP_VER(priv) == VERSION_8192F))
+		default_swing_index = get_swing_index(dm);
+#endif
+
+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
+	void		*adapter = dm->adapter;
+	PMGNT_INFO	mgnt_info = &adapter->MgntInfo;
+	HAL_DATA_TYPE		*hal_data = GET_HAL_DATA(((PADAPTER)adapter));
+
+	mgnt_info->is_txpowertracking = true;
+	hal_data->tx_powercount       = 0;
+	hal_data->is_txpowertracking_init = false;
+
+	if (*(dm->mp_mode) == false)
+		hal_data->txpowertrack_control = true;
+	RF_DBG(dm, COMP_POWER_TRACKING, "mgnt_info->is_txpowertracking = %d\n", mgnt_info->is_txpowertracking);
+#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
+#ifdef CONFIG_RTL8188E
+	{
+		dm->rf_calibrate_info.is_txpowertracking = true;
+		dm->rf_calibrate_info.tx_powercount = 0;
+		dm->rf_calibrate_info.is_txpowertracking_init = false;
+
+		if (*(dm->mp_mode) == false)
+			dm->rf_calibrate_info.txpowertrack_control = true;
+
+		MSG_8192C("dm txpowertrack_control = %d\n", dm->rf_calibrate_info.txpowertrack_control);
+	}
+#else
+	{
+		void		*adapter = dm->adapter;
+		HAL_DATA_TYPE	*hal_data = GET_HAL_DATA(((PADAPTER)adapter));
+		struct dm_priv	*pdmpriv = &hal_data->dmpriv;
+		
+		pdmpriv->is_txpowertracking = true;
+		pdmpriv->tx_powercount = 0;
+		pdmpriv->is_txpowertracking_init = false;
+
+		if (*(dm->mp_mode) == false)		/* for mp driver, turn off txpwrtracking as default */
+			pdmpriv->txpowertrack_control = true;
+
+		MSG_8192C("pdmpriv->txpowertrack_control = %d\n", pdmpriv->txpowertrack_control);
+
+	}
+#endif/* endif (CONFIG_RTL8188E==1) */
+#elif (DM_ODM_SUPPORT_TYPE & (ODM_AP))
+
+#ifdef RTL8188E_SUPPORT
+	{
+		dm->rf_calibrate_info.is_txpowertracking = true;
+		dm->rf_calibrate_info.tx_powercount = 0;
+		dm->rf_calibrate_info.is_txpowertracking_init = false;
+		dm->rf_calibrate_info.txpowertrack_control = true;
+		dm->rf_calibrate_info.tm_trigger = 0;
+	}
+#endif
+#endif
+
+	dm->rf_calibrate_info.txpowertrack_control = true;
+	dm->rf_calibrate_info.delta_power_index = 0;
+	dm->rf_calibrate_info.delta_power_index_last = 0;
+	dm->rf_calibrate_info.power_index_offset = 0;
+	dm->rf_calibrate_info.thermal_value = 0;
+	cali_info->default_ofdm_index = 28;
+
+#if (RTL8197F_SUPPORT == 1)
+	if (GET_CHIP_VER(priv) == VERSION_8197F) {
+		cali_info->default_ofdm_index = (default_swing_index >= (OFDM_TABLE_SIZE_92D - 1)) ? 30 : default_swing_index;
+		cali_info->default_cck_index = 28;
+	}
+#endif
+
+#if (RTL8192F_SUPPORT == 1)
+	if (GET_CHIP_VER(priv) == VERSION_8192F) {
+		cali_info->default_ofdm_index = 30;
+		cali_info->default_cck_index = 28;
+	}
+#endif
+
+#if (RTL8822B_SUPPORT == 1)
+	if (GET_CHIP_VER(priv) == VERSION_8822B) {
+		cali_info->default_ofdm_index = (default_swing_index >= (TXSCALE_TABLE_SIZE - 1)) ? 24 : default_swing_index;
+		cali_info->default_cck_index = 20;
+	}
+#endif
+
+
+#if RTL8188E_SUPPORT
+	cali_info->default_cck_index = 20;	/* -6 dB */
+#elif RTL8192E_SUPPORT
+	cali_info->default_cck_index = 8;	/* -12 dB */
+#endif
+	cali_info->bb_swing_idx_ofdm_base = cali_info->default_ofdm_index;
+	cali_info->bb_swing_idx_cck_base = cali_info->default_cck_index;
+	dm->rf_calibrate_info.CCK_index = cali_info->default_cck_index;
+
+	for (p = 0; p < MAX_RF_PATH; p++) {
+		dm->rf_calibrate_info.OFDM_index[p] = cali_info->default_ofdm_index;
+		cali_info->bb_swing_idx_ofdm[p] = cali_info->default_ofdm_index;
+		cali_info->kfree_offset[p] = 0;	/* for 8814 kfree*/
+	}
+	cali_info->bb_swing_idx_cck = cali_info->default_cck_index;
+
+	RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "cali_info->default_ofdm_index=%d cali_info->default_cck_index=%d\n", cali_info->default_ofdm_index, cali_info->default_cck_index);
+
+	cali_info->tm_trigger = 0;
+}
+
+
+void
+odm_txpowertracking_check(
+	void		*dm_void
+)
+{
+	/*  */
+	/* For AP/ADSL use struct rtl8192cd_priv* */
+	/* For CE/NIC use struct void* */
+	/*  */
+	struct dm_struct		*dm = (struct dm_struct *)dm_void;
+	struct _hal_rf_				*rf = &(dm->rf_table);
+
+
+	if (!(rf->rf_supportability & HAL_RF_TX_PWR_TRACK))
+		return;
+
+	/*  */
+	/* 2011/09/29 MH In HW integration first stage, we provide 4 different handle to operate */
+	/* at the same time. In the stage2/3, we need to prive universal interface and merge all */
+	/* HW dynamic mechanism. */
+	/*  */
+	switch	(dm->support_platform) {
+	case	ODM_WIN:
+		odm_txpowertracking_check_mp(dm);
+		break;
+
+	case	ODM_CE:
+		odm_txpowertracking_check_ce(dm);
+		break;
+
+	case	ODM_AP:
+		odm_txpowertracking_check_ap(dm);
+		break;
+	}
+
+}
+
+void
+odm_txpowertracking_check_ce(
+	void		*dm_void
+)
+{
+#if (DM_ODM_SUPPORT_TYPE == ODM_CE)
+	struct dm_struct		*dm = (struct dm_struct *)dm_void;
+	void	*adapter = dm->adapter;
+	struct _hal_rf_				*rf = &(dm->rf_table);
+
+#if (RTL8188E_SUPPORT == 1)
+
+	/* if(!mgnt_info->is_txpowertracking || (!pdmpriv->txpowertrack_control && pdmpriv->is_ap_kdone)) */
+
+	if (!(rf->rf_supportability & HAL_RF_TX_PWR_TRACK))
+		return;
+
+	if (!dm->rf_calibrate_info.tm_trigger) {	/* at least delay 1 sec */
+		/* hal_data->TxPowerCheckCnt++;	 */ /* cosa add for debug */
+		odm_set_rf_reg(dm, RF_PATH_A, RF_T_METER, RFREGOFFSETMASK, 0x60);
+		/* DBG_8192C("Trigger 92C Thermal Meter!!\n"); */
+
+		dm->rf_calibrate_info.tm_trigger = 1;
+		return;
+
+	} else {
+		/* DBG_8192C("Schedule TxPowerTracking direct call!!\n"); */
+		odm_txpowertracking_callback_thermal_meter_8188e(adapter);
+		dm->rf_calibrate_info.tm_trigger = 0;
+	}
+#endif
+
+#endif
+}
+
+void
+odm_txpowertracking_check_mp(
+	void		*dm_void
+)
+{
+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
+	struct dm_struct		*dm = (struct dm_struct *)dm_void;
+	void	*adapter = dm->adapter;
+
+	if (odm_check_power_status(adapter) == false)
+		return;
+
+	if (!adapter->is_slave_of_dmsp || adapter->dual_mac_smart_concurrent == false)
+		odm_txpowertracking_thermal_meter_check(adapter);
+#endif
+
+}
+
+
+void
+odm_txpowertracking_check_ap(
+	void		*dm_void
+)
+{
+	struct dm_struct		*dm = (struct dm_struct *)dm_void;
+#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
+	struct rtl8192cd_priv	*priv		= dm->priv;
+
+#if ((RTL8188E_SUPPORT == 1) || (RTL8192E_SUPPORT == 1) || (RTL8812A_SUPPORT == 1) || (RTL8881A_SUPPORT == 1) || (RTL8814A_SUPPORT == 1) || (RTL8197F_SUPPORT == 1) || (RTL8192F_SUPPORT == 1) || (RTL8198F_SUPPORT == 1))
+	if (dm->support_ic_type & (ODM_RTL8188E | ODM_RTL8192E | ODM_RTL8812 | ODM_RTL8881A | ODM_RTL8814A | ODM_RTL8197F | ODM_RTL8822B | ODM_RTL8821C | ODM_RTL8192F | ODM_RTL8198F))
+		odm_txpowertracking_callback_thermal_meter(dm);
+	else
+#endif
+	{
+	}
+#endif
+
+}
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/halrf/halrf_powertracking_ap.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/halrf/halrf_powertracking_ap.h
--- linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/halrf/halrf_powertracking_ap.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/halrf/halrf_powertracking_ap.h	2020-04-10 16:35:06.820660254 +0300
@@ -0,0 +1,397 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+
+#ifndef __HALRF_POWERTRACKING_H__
+#define __HALRF_POWERTRACKING_H__
+
+#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
+	#ifdef RTK_AC_SUPPORT
+		#define ODM_IC_11AC_SERIES_SUPPORT		1
+	#else
+		#define ODM_IC_11AC_SERIES_SUPPORT		0
+	#endif
+#else
+	#define ODM_IC_11AC_SERIES_SUPPORT		1
+#endif
+
+#define		DPK_DELTA_MAPPING_NUM	13
+#define		index_mapping_HP_NUM	15
+#define		DELTA_SWINGIDX_SIZE     30
+#define		DELTA_SWINTSSI_SIZE     61
+#define		BAND_NUM				3
+#define		MAX_RF_PATH	4
+#define		TXSCALE_TABLE_SIZE		37
+#define		CCK_TABLE_SIZE_8723D		41
+/* JJ ADD 20161014 */
+#define		CCK_TABLE_SIZE_8710B		41
+
+#define IQK_MAC_REG_NUM		4
+#define IQK_ADDA_REG_NUM		16
+#define IQK_BB_REG_NUM_MAX	10
+
+#define IQK_BB_REG_NUM		9
+
+#define AVG_THERMAL_NUM		8
+#define AVG_THERMAL_NUM_DPK		8
+#define THERMAL_DPK_AVG_NUM		4
+
+#define iqk_matrix_reg_num	8
+/* #define IQK_MATRIX_SETTINGS_NUM	1+24+21 */
+#define IQK_MATRIX_SETTINGS_NUM	(14+24+21) /* Channels_2_4G_NUM + Channels_5G_20M_NUM + Channels_5G */
+
+#if !defined(_OUTSRC_COEXIST)
+	#define	OFDM_TABLE_SIZE_92D	43
+	#define	OFDM_TABLE_SIZE	37
+	#define	CCK_TABLE_SIZE		33
+	#define	CCK_TABLE_SIZE_88F	21
+	#define	CCK_TABLE_SIZE_8192F	41
+
+
+
+	/* #define	OFDM_TABLE_SIZE_92E	54 */
+	/* #define	CCK_TABLE_SIZE_92E	54 */
+	extern	u32 ofdm_swing_table[OFDM_TABLE_SIZE_92D];
+	extern	u8 cck_swing_table_ch1_ch13[CCK_TABLE_SIZE][8];
+	extern	u8 cck_swing_table_ch14[CCK_TABLE_SIZE][8];
+
+
+	extern	u32 ofdm_swing_table_new[OFDM_TABLE_SIZE_92D];
+	extern	u8 cck_swing_table_ch1_ch13_new[CCK_TABLE_SIZE][8];
+	extern	u8 cck_swing_table_ch14_new[CCK_TABLE_SIZE][8];
+	extern	u8 cck_swing_table_ch1_ch14_88f[CCK_TABLE_SIZE_88F][16];
+	extern	u8 cck_swing_table_ch1_ch13_88f[CCK_TABLE_SIZE_88F][16];
+	extern	u8 cck_swing_table_ch14_88f[CCK_TABLE_SIZE_88F][16];
+	extern	u32 cck_swing_table_ch1_ch14_8192f[CCK_TABLE_SIZE_8192F];
+
+#endif
+
+#define	ODM_OFDM_TABLE_SIZE	37
+#define	ODM_CCK_TABLE_SIZE		33
+/* <20140613, YuChen> In case fail to read TxPowerTrack.txt, we use the table of 88E as the default table. */
+extern u8 delta_swing_table_idx_2ga_p_default[DELTA_SWINGIDX_SIZE];
+extern u8 delta_swing_table_idx_2ga_n_default[DELTA_SWINGIDX_SIZE];
+
+static u8 delta_swing_table_idx_2ga_p_8188e[] = {0, 0, 0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 4,  4,  4,  4,  4,  4,  5,  5,  7,  7,  8,  8,  8,  9,  9,  9,  9,  9};
+static u8 delta_swing_table_idx_2ga_n_8188e[] = {0, 0, 0, 2, 2, 3, 3, 4, 4, 4, 4, 5, 5,  6,  6,  7,  7,  7,  7,  8,  8,  9,  9, 10, 10, 10, 11, 11, 11, 11};
+
+/* extern	u32 ofdm_swing_table_92e[OFDM_TABLE_SIZE_92E];
+ * extern	u8 cck_swing_table_ch1_ch13_92e[CCK_TABLE_SIZE_92E][8];
+ * extern	u8 cck_swing_table_ch14_92e[CCK_TABLE_SIZE_92E][8]; */
+
+#ifdef CONFIG_WLAN_HAL_8192EE
+	#define	OFDM_TABLE_SIZE_92E	54
+	#define	CCK_TABLE_SIZE_92E	54
+	extern	u32 ofdm_swing_table_92e[OFDM_TABLE_SIZE_92E];
+	extern	u8 cck_swing_table_ch1_ch13_92e[CCK_TABLE_SIZE_92E][8];
+	extern	u8 cck_swing_table_ch14_92e[CCK_TABLE_SIZE_92E][8];
+#endif
+
+#define	OFDM_TABLE_SIZE_8812	43
+#define	AVG_THERMAL_NUM_8812	4
+
+#if (RTL8814A_SUPPORT == 1 || RTL8822B_SUPPORT == 1 ||\
+	RTL8821C_SUPPORT == 1 || RTL8198F_SUPPORT == 1)
+	extern u32 tx_scaling_table_jaguar[TXSCALE_TABLE_SIZE];
+	#elif(ODM_IC_11AC_SERIES_SUPPORT)
+	extern unsigned int ofdm_swing_table_8812[OFDM_TABLE_SIZE_8812];
+#endif
+
+extern u32 cck_swing_table_ch1_ch14_8723d[CCK_TABLE_SIZE_8723D];
+/* JJ ADD 20161014 */
+extern u32 cck_swing_table_ch1_ch14_8710b[CCK_TABLE_SIZE_8710B];
+
+#define dm_check_txpowertracking	odm_txpowertracking_check
+
+struct iqk_matrix_regs_setting {
+	boolean	is_iqk_done;
+	s32		value[1][iqk_matrix_reg_num];
+};
+
+struct dm_rf_calibration_struct {
+	/* for tx power tracking */
+
+	u32	rega24; /* for TempCCK */
+	s32	rege94;
+	s32	rege9c;
+	s32	regeb4;
+	s32	regebc;
+
+	/* u8 is_txpowertracking; */
+	u8	tx_powercount;
+	boolean is_txpowertracking_init;
+	boolean is_txpowertracking;
+	u8  	txpowertrack_control; /* for mp mode, turn off txpwrtracking as default */
+	u8	tm_trigger;
+	u8  	internal_pa_5g[2];	/* pathA / pathB */
+
+	u8  	thermal_meter[2];    /* thermal_meter, index 0 for RFIC0, and 1 for RFIC1 */
+	u8	thermal_value;
+	u8	thermal_value_lck;
+	u8	thermal_value_iqk;
+	s8  	thermal_value_delta; /* delta of thermal_value and efuse thermal */
+
+	u8	thermal_value_avg[AVG_THERMAL_NUM];
+	u8	thermal_value_avg_index;
+	u8	thermal_value_rx_gain;
+	u8	thermal_value_crystal;
+	u8	thermal_value_dpk_store;
+	u8	thermal_value_dpk_track;
+	boolean	txpowertracking_in_progress;
+
+
+	boolean	is_reloadtxpowerindex;
+	u8	is_rf_pi_enable;
+	u32 	txpowertracking_callback_cnt; /* cosa add for debug */
+
+	u8	is_cck_in_ch14;
+	u8	CCK_index;
+	u8	OFDM_index[MAX_RF_PATH];
+	s8	power_index_offset;
+	s8	delta_power_index;
+	s8	delta_power_index_last;
+	boolean is_tx_power_changed;
+
+	struct iqk_matrix_regs_setting iqk_matrix_reg_setting[IQK_MATRIX_SETTINGS_NUM];
+	u8	delta_lck;
+	u8  delta_swing_table_idx_2g_cck_a_p[DELTA_SWINGIDX_SIZE];
+	u8  delta_swing_table_idx_2g_cck_a_n[DELTA_SWINGIDX_SIZE];
+	u8  delta_swing_table_idx_2g_cck_b_p[DELTA_SWINGIDX_SIZE];
+	u8  delta_swing_table_idx_2g_cck_b_n[DELTA_SWINGIDX_SIZE];
+	u8  delta_swing_table_idx_2g_cck_c_p[DELTA_SWINGIDX_SIZE];
+	u8  delta_swing_table_idx_2g_cck_c_n[DELTA_SWINGIDX_SIZE];
+	u8  delta_swing_table_idx_2g_cck_d_p[DELTA_SWINGIDX_SIZE];
+	u8  delta_swing_table_idx_2g_cck_d_n[DELTA_SWINGIDX_SIZE];
+	u8  delta_swing_table_idx_2ga_p[DELTA_SWINGIDX_SIZE];
+	u8  delta_swing_table_idx_2ga_n[DELTA_SWINGIDX_SIZE];
+	u8  delta_swing_table_idx_2gb_p[DELTA_SWINGIDX_SIZE];
+	u8  delta_swing_table_idx_2gb_n[DELTA_SWINGIDX_SIZE];
+	u8  delta_swing_table_idx_2gc_p[DELTA_SWINGIDX_SIZE];
+	u8  delta_swing_table_idx_2gc_n[DELTA_SWINGIDX_SIZE];
+	u8  delta_swing_table_idx_2gd_p[DELTA_SWINGIDX_SIZE];
+	u8  delta_swing_table_idx_2gd_n[DELTA_SWINGIDX_SIZE];
+	u8  delta_swing_table_idx_5ga_p[BAND_NUM][DELTA_SWINGIDX_SIZE];
+	u8  delta_swing_table_idx_5ga_n[BAND_NUM][DELTA_SWINGIDX_SIZE];
+	u8  delta_swing_table_idx_5gb_p[BAND_NUM][DELTA_SWINGIDX_SIZE];
+	u8  delta_swing_table_idx_5gb_n[BAND_NUM][DELTA_SWINGIDX_SIZE];
+	u8  delta_swing_table_idx_5gc_p[BAND_NUM][DELTA_SWINGIDX_SIZE];
+	u8  delta_swing_table_idx_5gc_n[BAND_NUM][DELTA_SWINGIDX_SIZE];
+	u8  delta_swing_table_idx_5gd_p[BAND_NUM][DELTA_SWINGIDX_SIZE];
+	u8  delta_swing_table_idx_5gd_n[BAND_NUM][DELTA_SWINGIDX_SIZE];
+	u8  delta_swing_tssi_table_2g_cck_a[DELTA_SWINTSSI_SIZE];
+	u8  delta_swing_tssi_table_2g_cck_b[DELTA_SWINTSSI_SIZE];
+	u8  delta_swing_tssi_table_2g_cck_c[DELTA_SWINTSSI_SIZE];
+	u8  delta_swing_tssi_table_2g_cck_d[DELTA_SWINTSSI_SIZE];
+	u8  delta_swing_tssi_table_2ga[DELTA_SWINTSSI_SIZE];
+	u8  delta_swing_tssi_table_2gb[DELTA_SWINTSSI_SIZE];
+	u8  delta_swing_tssi_table_2gc[DELTA_SWINTSSI_SIZE];
+	u8  delta_swing_tssi_table_2gd[DELTA_SWINTSSI_SIZE];
+	u8  delta_swing_tssi_table_5ga[BAND_NUM][DELTA_SWINTSSI_SIZE];
+	u8  delta_swing_tssi_table_5gb[BAND_NUM][DELTA_SWINTSSI_SIZE];
+	u8  delta_swing_tssi_table_5gc[BAND_NUM][DELTA_SWINTSSI_SIZE];
+	u8  delta_swing_tssi_table_5gd[BAND_NUM][DELTA_SWINTSSI_SIZE];
+	s8  delta_swing_table_xtal_p[DELTA_SWINGIDX_SIZE];
+	s8  delta_swing_table_xtal_n[DELTA_SWINGIDX_SIZE];
+	u8  delta_swing_table_idx_2ga_p_8188e[DELTA_SWINGIDX_SIZE];
+	u8  delta_swing_table_idx_2ga_n_8188e[DELTA_SWINGIDX_SIZE];
+
+	u8			bb_swing_idx_ofdm[MAX_RF_PATH];
+	u8			bb_swing_idx_ofdm_current;
+#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
+	u8			bb_swing_idx_ofdm_base[MAX_RF_PATH];
+#else
+	u8			bb_swing_idx_ofdm_base;
+#endif
+	boolean			bb_swing_flag_ofdm;
+	u8			bb_swing_idx_cck;
+	u8			bb_swing_idx_cck_current;
+	u8			bb_swing_idx_cck_base;
+	u8			default_ofdm_index;
+	u8			default_cck_index;
+	boolean			bb_swing_flag_cck;
+
+	s8			absolute_ofdm_swing_idx[MAX_RF_PATH];
+	s8			remnant_ofdm_swing_idx[MAX_RF_PATH];
+	s8			absolute_cck_swing_idx[MAX_RF_PATH];
+	s8			remnant_cck_swing_idx;
+	s8			modify_tx_agc_value;       /*Remnat compensate value at tx_agc */
+	boolean			modify_tx_agc_flag_path_a;
+	boolean			modify_tx_agc_flag_path_b;
+	boolean			modify_tx_agc_flag_path_c;
+	boolean			modify_tx_agc_flag_path_d;
+	boolean			modify_tx_agc_flag_path_a_cck;
+	boolean			modify_tx_agc_flag_path_b_cck;
+
+	s8			kfree_offset[MAX_RF_PATH];
+
+	/* -------------------------------------------------------------------- */
+
+	/* for IQK */
+	u32	regc04;
+	u32	reg874;
+	u32	regc08;
+	u32	regb68;
+	u32	regb6c;
+	u32	reg870;
+	u32	reg860;
+	u32	reg864;
+
+	boolean	is_iqk_initialized;
+	boolean is_lck_in_progress;
+	boolean	is_antenna_detected;
+	boolean	is_need_iqk;
+	boolean	is_iqk_in_progress;
+	boolean	is_iqk_pa_off;
+	u8	delta_iqk;
+	u32	ADDA_backup[IQK_ADDA_REG_NUM];
+	u32	IQK_MAC_backup[IQK_MAC_REG_NUM];
+	u32	IQK_BB_backup_recover[9];
+	u32	IQK_BB_backup[IQK_BB_REG_NUM];
+	u32	tx_iqc_8723b[2][3][2]; /* { {S1: 0xc94, 0xc80, 0xc4c} , {S0: 0xc9c, 0xc88, 0xc4c}} */
+	u32	rx_iqc_8723b[2][2][2]; /* { {S1: 0xc14, 0xca0} ,           {S0: 0xc14, 0xca0}} */
+	u32	tx_iqc_8703b[3][2];	/* { {S1: 0xc94, 0xc80, 0xc4c} , {S0: 0xc9c, 0xc88, 0xc4c}}*/
+	u32	rx_iqc_8703b[2][2];	/* { {S1: 0xc14, 0xca0} ,           {S0: 0xc14, 0xca0}}*/
+
+	u64	iqk_start_time;
+	u64	iqk_total_progressing_time;
+	u64	iqk_progressing_time;
+	u64	lck_progressing_time;
+	u32  lok_result;
+	u8	iqk_step;
+	u8	kcount;
+	u8	retry_count[4][2]; /* [4]: path ABCD, [2] TXK, RXK */
+	boolean	is_mp_mode;
+
+	/* for APK */
+	u32 	ap_koutput[2][2]; /* path A/B; output1_1a/output1_2a */
+	u8	is_ap_kdone;
+	u8	is_apk_thermal_meter_ignore;
+	u8	is_dp_done;
+#if 0 /*move below members to halrf_dpk.h*/
+	u8	is_dp_path_aok;
+	u8	is_dp_path_bok;
+	u8	is_dp_path_cok;
+	u8	is_dp_path_dok;
+	u8 	dp_path_a_result[3];
+	u8 	dp_path_b_result[3];
+	u8 	dp_path_c_result[3];
+	u8 	dp_path_d_result[3];
+	boolean	is_dpk_enable;
+	u32	txrate[11];
+	u8 	pwsf_2g_a[3];
+	u8 	pwsf_2g_b[3];
+	u8 	pwsf_2g_c[3];
+	u8 	pwsf_2g_d[3];
+	u32	lut_2g_even_a[3][64];
+	u32	lut_2g_odd_a[3][64];
+	u32	lut_2g_even_b[3][64];
+	u32	lut_2g_odd_b[3][64];
+	u32	lut_2g_even_c[3][64];
+	u32	lut_2g_odd_c[3][64];
+	u32	lut_2g_even_d[3][64];
+	u32	lut_2g_odd_d[3][64];
+	u1Byte 	is_5g_pdk_a_ok;
+	u1Byte 	is_5g_pdk_b_ok;
+	u1Byte 	is_5g_pdk_c_ok;
+	u1Byte 	is_5g_pdk_d_ok;
+	u1Byte 	pwsf_5g_a[9];
+	u1Byte 	pwsf_5g_b[9];
+	u1Byte 	pwsf_5g_c[9];
+	u1Byte 	pwsf_5g_d[9];
+	u4Byte	lut_5g_even_a[9][16];
+	u4Byte	lut_5g_odd_a[9][16];
+	u4Byte	lut_5g_even_b[9][16];
+	u4Byte	lut_5g_odd_b[9][16];
+	u4Byte	lut_5g_even_c[9][16];
+	u4Byte	lut_5g_odd_c[9][16];
+	u4Byte	lut_5g_even_d[9][16];
+	u4Byte	lut_5g_odd_d[9][16];
+	u8	thermal_value_dpk;
+	u8	thermal_value_dpk_avg[AVG_THERMAL_NUM_DPK];
+	u8	thermal_value_dpk_avg_index;
+#endif
+	s8  modify_tx_agc_value_ofdm;
+	s8  modify_tx_agc_value_cck;
+
+	/*Add by Yuchen for Kfree Phydm*/
+	u8			reg_rf_kfree_enable;	/*for registry*/
+	u8			rf_kfree_enable;		/*for efuse enable check*/
+	u32	tx_lok[2];
+};
+
+void
+odm_txpowertracking_check_ap(
+	void		*dm_void
+);
+
+void
+odm_txpowertracking_check(
+	void		*dm_void
+);
+
+
+void
+odm_txpowertracking_thermal_meter_init(
+	void		*dm_void
+);
+
+void
+odm_txpowertracking_init(
+	void		*dm_void
+);
+
+void
+odm_txpowertracking_check_mp(
+	void		*dm_void
+);
+
+
+void
+odm_txpowertracking_check_ce(
+	void		*dm_void
+);
+
+
+#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN))
+
+void
+odm_txpowertracking_callback_thermal_meter92c(
+	void	*adapter
+);
+
+void
+odm_txpowertracking_callback_rx_gain_thermal_meter92d(
+	void	*adapter
+);
+
+void
+odm_txpowertracking_callback_thermal_meter92d(
+	void	*adapter
+);
+
+void
+odm_txpowertracking_direct_call92c(
+	void		*adapter
+);
+
+void
+odm_txpowertracking_thermal_meter_check(
+	void		*adapter
+);
+
+#endif
+
+
+
+#endif	/*#ifndef __HALRF_POWER_TRACKING_H__*/
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/halrf/halrf_powertracking.c linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/halrf/halrf_powertracking.c
--- linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/halrf/halrf_powertracking.c	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/halrf/halrf_powertracking.c	2020-04-10 16:35:06.820660254 +0300
@@ -0,0 +1,152 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017  Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * The full GNU General Public License is included in this distribution in the
+ * file called LICENSE.
+ *
+ * Contact Information:
+ * wlanfae <wlanfae@realtek.com>
+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
+ * Hsinchu 300, Taiwan.
+ *
+ * Larry Finger <Larry.Finger@lwfinger.net>
+ *
+ *****************************************************************************/
+
+/* ************************************************************
+ * include files
+ * ************************************************************
+ */
+#include "mp_precomp.h"
+#include "phydm_precomp.h"
+
+boolean
+odm_check_power_status(void *dm_void)
+{
+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	PADAPTER *adapter = dm->adapter;
+
+	RT_RF_POWER_STATE rt_state;
+	MGNT_INFO *mgnt_info = &((PADAPTER)adapter)->MgntInfo;
+
+	/* 2011/07/27 MH We are not testing ready~~!! We may fail to get correct value when init sequence. */
+	if (mgnt_info->init_adpt_in_progress == true) {
+		RF_DBG(dm, DBG_RF_INIT,
+		       "check_pow_status Return true, due to initadapter\n");
+		return true;
+	}
+
+	/*
+	 *	2011/07/19 MH We can not execute tx pwoer tracking/ LLC calibrate or IQK.
+	 */
+	((PADAPTER)adapter)->HalFunc.GetHwRegHandler((PADAPTER)adapter, HW_VAR_RF_STATE, (u8 *)(&rt_state));
+	if (((PADAPTER)adapter)->bDriverStopped || ((PADAPTER)adapter)->bDriverIsGoingToPnpSetPowerSleep || rt_state == eRfOff) {
+		RF_DBG(dm, DBG_RF_INIT,
+		       "check_pow_status Return false, due to %d/%d/%d\n",
+		       ((PADAPTER)adapter)->bDriverStopped,
+		       ((PADAPTER)adapter)->bDriverIsGoingToPnpSetPowerSleep,
+		       rt_state);
+		return false;
+	}
+#endif
+	return true;
+}
+
+#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
+void halrf_update_pwr_track(void *dm_void, u8 rate)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
+	u8 path_idx = 0;
+#endif
+
+	RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "Pwr Track Get rate=0x%x\n", rate);
+
+	dm->tx_rate = rate;
+
+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
+#if DEV_BUS_TYPE == RT_PCI_INTERFACE
+#if USE_WORKITEM
+	odm_schedule_work_item(&dm->ra_rpt_workitem);
+#else
+	if (dm->support_ic_type == ODM_RTL8821) {
+#if (RTL8821A_SUPPORT == 1)
+		odm_tx_pwr_track_set_pwr8821a(dm, MIX_MODE, RF_PATH_A, 0);
+#endif
+	} else if (dm->support_ic_type == ODM_RTL8812) {
+		for (path_idx = RF_PATH_A; path_idx < MAX_PATH_NUM_8812A; path_idx++) {
+#if (RTL8812A_SUPPORT == 1)
+			odm_tx_pwr_track_set_pwr8812a(dm, MIX_MODE, path_idx, 0);
+#endif
+		}
+	} else if (dm->support_ic_type == ODM_RTL8723B) {
+#if (RTL8723B_SUPPORT == 1)
+		odm_tx_pwr_track_set_pwr_8723b(dm, MIX_MODE, RF_PATH_A, 0);
+#endif
+	} else if (dm->support_ic_type == ODM_RTL8192E) {
+		for (path_idx = RF_PATH_A; path_idx < MAX_PATH_NUM_8192E; path_idx++) {
+#if (RTL8192E_SUPPORT == 1)
+			odm_tx_pwr_track_set_pwr92_e(dm, MIX_MODE, path_idx, 0);
+#endif
+		}
+	} else if (dm->support_ic_type == ODM_RTL8188E) {
+#if (RTL8188E_SUPPORT == 1)
+		odm_tx_pwr_track_set_pwr88_e(dm, MIX_MODE, RF_PATH_A, 0);
+#endif
+	}
+#endif
+#else
+	odm_schedule_work_item(&dm->ra_rpt_workitem);
+#endif
+#endif
+}
+
+#endif
+
+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
+void halrf_update_init_rate_work_item_callback(
+	void *context)
+{
+	void *adapter = (void *)context;
+	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter));
+	struct dm_struct *dm = &hal_data->DM_OutSrc;
+	u8 p = 0;
+
+	if (dm->support_ic_type == ODM_RTL8821) {
+#if (RTL8821A_SUPPORT == 1)
+		odm_tx_pwr_track_set_pwr8821a(dm, MIX_MODE, RF_PATH_A, 0);
+#endif
+	} else if (dm->support_ic_type == ODM_RTL8812) {
+#if (RTL8812A_SUPPORT == 1)
+		/*Don't know how to include &c*/
+		for (p = RF_PATH_A; p < MAX_PATH_NUM_8812A; p++)
+			odm_tx_pwr_track_set_pwr8812a(dm, MIX_MODE, p, 0);
+#endif
+	} else if (dm->support_ic_type == ODM_RTL8723B) {
+#if (RTL8723B_SUPPORT == 1)
+		odm_tx_pwr_track_set_pwr_8723b(dm, MIX_MODE, RF_PATH_A, 0);
+#endif
+	} else if (dm->support_ic_type == ODM_RTL8192E) {
+#if (RTL8192E_SUPPORT == 1)
+		/*Don't know how to include &c*/
+		for (p = RF_PATH_A; p < MAX_PATH_NUM_8192E; p++)
+			odm_tx_pwr_track_set_pwr92_e(dm, MIX_MODE, p, 0);
+#endif
+	} else if (dm->support_ic_type == ODM_RTL8188E) {
+#if (RTL8188E_SUPPORT == 1)
+		odm_tx_pwr_track_set_pwr88_e(dm, MIX_MODE, RF_PATH_A, 0);
+#endif
+	}
+}
+#endif
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/halrf/halrf_powertracking_ce.c linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/halrf/halrf_powertracking_ce.c
--- linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/halrf/halrf_powertracking_ce.c	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/halrf/halrf_powertracking_ce.c	2020-04-10 16:35:06.820660254 +0300
@@ -0,0 +1,840 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017  Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * The full GNU General Public License is included in this distribution in the
+ * file called LICENSE.
+ *
+ * Contact Information:
+ * wlanfae <wlanfae@realtek.com>
+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
+ * Hsinchu 300, Taiwan.
+ *
+ * Larry Finger <Larry.Finger@lwfinger.net>
+ *
+ *****************************************************************************/
+
+/*============================================================
+ * include files
+ *============================================================
+ */
+
+#include "mp_precomp.h"
+#include "phydm_precomp.h"
+
+/* ************************************************************
+ * Global var
+ * ************************************************************
+ */
+
+u32 ofdm_swing_table[OFDM_TABLE_SIZE] = {
+	0x7f8001fe, /* 0, +6.0dB */
+	0x788001e2, /* 1, +5.5dB */
+	0x71c001c7, /* 2, +5.0dB*/
+	0x6b8001ae, /* 3, +4.5dB*/
+	0x65400195, /* 4, +4.0dB*/
+	0x5fc0017f, /* 5, +3.5dB*/
+	0x5a400169, /* 6, +3.0dB*/
+	0x55400155, /* 7, +2.5dB*/
+	0x50800142, /* 8, +2.0dB*/
+	0x4c000130, /* 9, +1.5dB*/
+	0x47c0011f, /* 10, +1.0dB*/
+	0x43c0010f, /* 11, +0.5dB*/
+	0x40000100, /* 12, +0dB*/
+	0x3c8000f2, /* 13, -0.5dB*/
+	0x390000e4, /* 14, -1.0dB*/
+	0x35c000d7, /* 15, -1.5dB*/
+	0x32c000cb, /* 16, -2.0dB*/
+	0x300000c0, /* 17, -2.5dB*/
+	0x2d4000b5, /* 18, -3.0dB*/
+	0x2ac000ab, /* 19, -3.5dB*/
+	0x288000a2, /* 20, -4.0dB*/
+	0x26000098, /* 21, -4.5dB*/
+	0x24000090, /* 22, -5.0dB*/
+	0x22000088, /* 23, -5.5dB*/
+	0x20000080, /* 24, -6.0dB*/
+	0x1e400079, /* 25, -6.5dB*/
+	0x1c800072, /* 26, -7.0dB*/
+	0x1b00006c, /* 27. -7.5dB*/
+	0x19800066, /* 28, -8.0dB*/
+	0x18000060, /* 29, -8.5dB*/
+	0x16c0005b, /* 30, -9.0dB*/
+	0x15800056, /* 31, -9.5dB*/
+	0x14400051, /* 32, -10.0dB*/
+	0x1300004c, /* 33, -10.5dB*/
+	0x12000048, /* 34, -11.0dB*/
+	0x11000044, /* 35, -11.5dB*/
+	0x10000040, /* 36, -12.0dB*/
+};
+
+u8 cck_swing_table_ch1_ch13[CCK_TABLE_SIZE][8] = {
+	{0x36, 0x35, 0x2e, 0x25, 0x1c, 0x12, 0x09, 0x04}, /* 0, +0dB */
+	{0x33, 0x32, 0x2b, 0x23, 0x1a, 0x11, 0x08, 0x04}, /* 1, -0.5dB */
+	{0x30, 0x2f, 0x29, 0x21, 0x19, 0x10, 0x08, 0x03}, /* 2, -1.0dB */
+	{0x2d, 0x2d, 0x27, 0x1f, 0x18, 0x0f, 0x08, 0x03}, /* 3, -1.5dB */
+	{0x2b, 0x2a, 0x25, 0x1e, 0x16, 0x0e, 0x07, 0x03}, /* 4, -2.0dB */
+	{0x28, 0x28, 0x22, 0x1c, 0x15, 0x0d, 0x07, 0x03}, /* 5, -2.5dB */
+	{0x26, 0x25, 0x21, 0x1b, 0x14, 0x0d, 0x06, 0x03}, /* 6, -3.0dB */
+	{0x24, 0x23, 0x1f, 0x19, 0x13, 0x0c, 0x06, 0x03}, /* 7, -3.5dB */
+	{0x22, 0x21, 0x1d, 0x18, 0x11, 0x0b, 0x06, 0x02}, /* 8, -4.0dB */
+	{0x20, 0x20, 0x1b, 0x16, 0x11, 0x08, 0x05, 0x02}, /* 9, -4.5dB */
+	{0x1f, 0x1e, 0x1a, 0x15, 0x10, 0x0a, 0x05, 0x02}, /* 10, -5.0dB */
+	{0x1d, 0x1c, 0x18, 0x14, 0x0f, 0x0a, 0x05, 0x02}, /* 11, -5.5dB */
+	{0x1b, 0x1a, 0x17, 0x13, 0x0e, 0x09, 0x04, 0x02}, /* 12, -6.0 default*/
+	{0x1a, 0x19, 0x16, 0x12, 0x0d, 0x09, 0x04, 0x02}, /* 13, -6.5dB */
+	{0x18, 0x17, 0x15, 0x11, 0x0c, 0x08, 0x04, 0x02}, /* 14, -7.0dB */
+	{0x17, 0x16, 0x13, 0x10, 0x0c, 0x08, 0x04, 0x02}, /* 15, -7.5dB */
+	{0x16, 0x15, 0x12, 0x0f, 0x0b, 0x07, 0x04, 0x01}, /* 16, -8.0dB */
+	{0x14, 0x14, 0x11, 0x0e, 0x0b, 0x07, 0x03, 0x02}, /* 17, -8.5dB */
+	{0x13, 0x13, 0x10, 0x0d, 0x0a, 0x06, 0x03, 0x01}, /* 18, -9.0dB */
+	{0x12, 0x12, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01}, /* 19, -9.5dB */
+	{0x11, 0x11, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01}, /* 20, -10.0dB */
+	{0x10, 0x10, 0x0e, 0x0b, 0x08, 0x05, 0x03, 0x01}, /* 21, -10.5dB */
+	{0x0f, 0x0f, 0x0d, 0x0b, 0x08, 0x05, 0x03, 0x01}, /* 22, -11.0dB */
+	{0x0e, 0x0e, 0x0c, 0x0a, 0x08, 0x05, 0x02, 0x01}, /* 23, -11.5dB */
+	{0x0d, 0x0d, 0x0c, 0x0a, 0x07, 0x05, 0x02, 0x01}, /* 24, -12.0dB */
+	{0x0d, 0x0c, 0x0b, 0x09, 0x07, 0x04, 0x02, 0x01}, /* 25, -12.5dB */
+	{0x0c, 0x0c, 0x0a, 0x09, 0x06, 0x04, 0x02, 0x01}, /* 26, -13.0dB */
+	{0x0b, 0x0b, 0x0a, 0x08, 0x06, 0x04, 0x02, 0x01}, /* 27, -13.5dB */
+	{0x0b, 0x0a, 0x09, 0x08, 0x06, 0x04, 0x02, 0x01}, /* 28, -14.0dB */
+	{0x0a, 0x0a, 0x09, 0x07, 0x05, 0x03, 0x02, 0x01}, /* 29, -14.5dB */
+	{0x0a, 0x09, 0x08, 0x07, 0x05, 0x03, 0x02, 0x01}, /* 30, -15.0dB */
+	{0x09, 0x09, 0x08, 0x06, 0x05, 0x03, 0x01, 0x01}, /* 31, -15.5dB */
+	{0x09, 0x08, 0x07, 0x06, 0x04, 0x03, 0x01, 0x01} /* 32, -16.0dB */
+};
+
+u8 cck_swing_table_ch14[CCK_TABLE_SIZE][8] = {
+	{0x36, 0x35, 0x2e, 0x1b, 0x00, 0x00, 0x00, 0x00}, /* 0, +0dB */
+	{0x33, 0x32, 0x2b, 0x19, 0x00, 0x00, 0x00, 0x00}, /* 1, -0.5dB */
+	{0x30, 0x2f, 0x29, 0x18, 0x00, 0x00, 0x00, 0x00}, /* 2, -1.0dB */
+	{0x2d, 0x2d, 0x17, 0x17, 0x00, 0x00, 0x00, 0x00}, /* 3, -1.5dB */
+	{0x2b, 0x2a, 0x25, 0x15, 0x00, 0x00, 0x00, 0x00}, /* 4, -2.0dB */
+	{0x28, 0x28, 0x24, 0x14, 0x00, 0x00, 0x00, 0x00}, /* 5, -2.5dB */
+	{0x26, 0x25, 0x21, 0x13, 0x00, 0x00, 0x00, 0x00}, /* 6, -3.0dB */
+	{0x24, 0x23, 0x1f, 0x12, 0x00, 0x00, 0x00, 0x00}, /* 7, -3.5dB */
+	{0x22, 0x21, 0x1d, 0x11, 0x00, 0x00, 0x00, 0x00}, /* 8, -4.0dB */
+	{0x20, 0x20, 0x1b, 0x10, 0x00, 0x00, 0x00, 0x00}, /* 9, -4.5dB */
+	{0x1f, 0x1e, 0x1a, 0x0f, 0x00, 0x00, 0x00, 0x00}, /* 10, -5.0dB */
+	{0x1d, 0x1c, 0x18, 0x0e, 0x00, 0x00, 0x00, 0x00}, /* 11, -5.5dB */
+	{0x1b, 0x1a, 0x17, 0x0e, 0x00, 0x00, 0x00, 0x00}, /* 12, -6.0 default*/
+	{0x1a, 0x19, 0x16, 0x0d, 0x00, 0x00, 0x00, 0x00}, /* 13, -6.5dB */
+	{0x18, 0x17, 0x15, 0x0c, 0x00, 0x00, 0x00, 0x00}, /* 14, -7.0dB */
+	{0x17, 0x16, 0x13, 0x0b, 0x00, 0x00, 0x00, 0x00}, /* 15, -7.5dB */
+	{0x16, 0x15, 0x12, 0x0b, 0x00, 0x00, 0x00, 0x00}, /* 16, -8.0dB */
+	{0x14, 0x14, 0x11, 0x0a, 0x00, 0x00, 0x00, 0x00}, /* 17, -8.5dB */
+	{0x13, 0x13, 0x10, 0x0a, 0x00, 0x00, 0x00, 0x00}, /* 18, -9.0dB */
+	{0x12, 0x12, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00}, /* 19, -9.5dB */
+	{0x11, 0x11, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00}, /* 20, -10.0dB */
+	{0x10, 0x10, 0x0e, 0x08, 0x00, 0x00, 0x00, 0x00}, /* 21, -10.5dB */
+	{0x0f, 0x0f, 0x0d, 0x08, 0x00, 0x00, 0x00, 0x00}, /* 22, -11.0dB */
+	{0x0e, 0x0e, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00}, /* 23, -11.5dB */
+	{0x0d, 0x0d, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00}, /* 24, -12.0dB */
+	{0x0d, 0x0c, 0x0b, 0x06, 0x00, 0x00, 0x00, 0x00}, /* 25, -12.5dB */
+	{0x0c, 0x0c, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00}, /* 26, -13.0dB */
+	{0x0b, 0x0b, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00}, /* 27, -13.5dB */
+	{0x0b, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 28, -14.0dB */
+	{0x0a, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 29, -14.5dB */
+	{0x0a, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 30, -15.0dB */
+	{0x09, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 31, -15.5dB */
+	{0x09, 0x08, 0x07, 0x04, 0x00, 0x00, 0x00, 0x00} /* 32, -16.0dB */
+};
+
+u32 ofdm_swing_table_new[OFDM_TABLE_SIZE] = {
+	0x0b40002d, /* 0,  -15.0dB */
+	0x0c000030, /* 1,  -14.5dB */
+	0x0cc00033, /* 2,  -14.0dB */
+	0x0d800036, /* 3,  -13.5dB */
+	0x0e400039, /* 4,  -13.0dB */
+	0x0f00003c, /* 5,  -12.5dB */
+	0x10000040, /* 6,  -12.0dB */
+	0x11000044, /* 7,  -11.5dB */
+	0x12000048, /* 8,  -11.0dB */
+	0x1300004c, /* 9,  -10.5dB */
+	0x14400051, /* 10, -10.0dB */
+	0x15800056, /* 11, -9.5dB */
+	0x16c0005b, /* 12, -9.0dB */
+	0x18000060, /* 13, -8.5dB */
+	0x19800066, /* 14, -8.0dB */
+	0x1b00006c, /* 15, -7.5dB */
+	0x1c800072, /* 16, -7.0dB */
+	0x1e400079, /* 17, -6.5dB */
+	0x20000080, /* 18, -6.0dB */
+	0x22000088, /* 19, -5.5dB */
+	0x24000090, /* 20, -5.0dB */
+	0x26000098, /* 21, -4.5dB */
+	0x288000a2, /* 22, -4.0dB */
+	0x2ac000ab, /* 23, -3.5dB */
+	0x2d4000b5, /* 24, -3.0dB */
+	0x300000c0, /* 25, -2.5dB */
+	0x32c000cb, /* 26, -2.0dB */
+	0x35c000d7, /* 27, -1.5dB */
+	0x390000e4, /* 28, -1.0dB */
+	0x3c8000f2, /* 29, -0.5dB */
+	0x40000100, /* 30, +0dB */
+	0x43c0010f, /* 31, +0.5dB */
+	0x47c0011f, /* 32, +1.0dB */
+	0x4c000130, /* 33, +1.5dB */
+	0x50800142, /* 34, +2.0dB */
+	0x55400155, /* 35, +2.5dB */
+	0x5a400169, /* 36, +3.0dB */
+	0x5fc0017f, /* 37, +3.5dB */
+	0x65400195, /* 38, +4.0dB */
+	0x6b8001ae, /* 39, +4.5dB */
+	0x71c001c7, /* 40, +5.0dB */
+	0x788001e2, /* 41, +5.5dB */
+	0x7f8001fe /* 42, +6.0dB */
+};
+
+u8 cck_swing_table_ch1_ch14_88f[CCK_TABLE_SIZE_88F][16] = {
+	{0x44, 0x42, 0x3C, 0x33, 0x28, 0x1C, 0x13, 0x0B, 0x05, 0x02,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-16dB*/
+	{0x48, 0x46, 0x3F, 0x36, 0x2A, 0x1E, 0x14, 0x0B, 0x05, 0x02,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-15.5dB*/
+	{0x4D, 0x4A, 0x43, 0x39, 0x2C, 0x20, 0x15, 0x0C, 0x06, 0x02,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-15dB*/
+	{0x51, 0x4F, 0x47, 0x3C, 0x2F, 0x22, 0x16, 0x0D, 0x06, 0x02,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-14.5dB*/
+	{0x56, 0x53, 0x4B, 0x40, 0x32, 0x24, 0x17, 0x0E, 0x06, 0x02,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-14dB*/
+	{0x5B, 0x58, 0x50, 0x43, 0x35, 0x26, 0x19, 0x0E, 0x07, 0x02,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-13.5dB*/
+	{0x60, 0x5D, 0x54, 0x47, 0x38, 0x28, 0x1A, 0x0F, 0x07, 0x02,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-13dB*/
+	{0x66, 0x63, 0x59, 0x4C, 0x3B, 0x2B, 0x1C, 0x10, 0x08, 0x02,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-12.5dB*/
+	{0x6C, 0x69, 0x5F, 0x50, 0x3F, 0x2D, 0x1E, 0x11, 0x08, 0x03,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-12dB*/
+	{0x73, 0x6F, 0x64, 0x55, 0x42, 0x30, 0x1F, 0x12, 0x08, 0x03,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-11.5dB*/
+	{0x79, 0x76, 0x6A, 0x5A, 0x46, 0x33, 0x21, 0x13, 0x09, 0x03,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-11dB*/
+	{0x81, 0x7C, 0x71, 0x5F, 0x4A, 0x36, 0x23, 0x14, 0x0A, 0x03,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-10.5dB*/
+	{0x88, 0x84, 0x77, 0x65, 0x4F, 0x39, 0x25, 0x15, 0x0A, 0x03,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-10dB*/
+	{0x90, 0x8C, 0x7E, 0x6B, 0x54, 0x3C, 0x27, 0x17, 0x0B, 0x03,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-9.5dB*/
+	{0x99, 0x94, 0x86, 0x71, 0x58, 0x40, 0x2A, 0x18, 0x0B, 0x04,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-9dB*/
+	{0xA2, 0x9D, 0x8E, 0x78, 0x5E, 0x43, 0x2C, 0x19, 0x0C, 0x04,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-8.5dB*/
+	{0xAC, 0xA6, 0x96, 0x7F, 0x63, 0x47, 0x2F, 0x1B, 0x0D, 0x04,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-8dB*/
+	{0xB6, 0xB0, 0x9F, 0x87, 0x69, 0x4C, 0x32, 0x1D, 0x0D, 0x04,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-7.5dB*/
+	{0xC1, 0xBA, 0xA8, 0x8F, 0x6F, 0x50, 0x35, 0x1E, 0x0E, 0x04,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-7dB*/
+	{0xCC, 0xC5, 0xB2, 0x97, 0x76, 0x55, 0x38, 0x20, 0x0F, 0x05,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-6.5dB*/
+	{0xD8, 0xD1, 0xBD, 0xA0, 0x7D, 0x5A, 0x3B, 0x22, 0x10, 0x05,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00} /*-6dB*/
+};
+
+u8 cck_swing_table_ch1_ch13_88f[CCK_TABLE_SIZE_88F][16] = {
+	{0x44, 0x42, 0x3C, 0x33, 0x28, 0x1C, 0x13, 0x0B, 0x05, 0x02,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-16dB*/
+	{0x48, 0x46, 0x3F, 0x36, 0x2A, 0x1E, 0x14, 0x0B, 0x05, 0x02,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-15.5dB*/
+	{0x4D, 0x4A, 0x43, 0x39, 0x2C, 0x20, 0x15, 0x0C, 0x06, 0x02,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-15dB*/
+	{0x51, 0x4F, 0x47, 0x3C, 0x2F, 0x22, 0x16, 0x0D, 0x06, 0x02,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-14.5dB*/
+	{0x56, 0x53, 0x4B, 0x40, 0x32, 0x24, 0x17, 0x0E, 0x06, 0x02,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-14dB*/
+	{0x5B, 0x58, 0x50, 0x43, 0x35, 0x26, 0x19, 0x0E, 0x07, 0x02,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-13.5dB*/
+	{0x60, 0x5D, 0x54, 0x47, 0x38, 0x28, 0x1A, 0x0F, 0x07, 0x02,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-13dB*/
+	{0x66, 0x63, 0x59, 0x4C, 0x3B, 0x2B, 0x1C, 0x10, 0x08, 0x02,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-12.5dB*/
+	{0x6C, 0x69, 0x5F, 0x50, 0x3F, 0x2D, 0x1E, 0x11, 0x08, 0x03,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-12dB*/
+	{0x73, 0x6F, 0x64, 0x55, 0x42, 0x30, 0x1F, 0x12, 0x08, 0x03,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-11.5dB*/
+	{0x79, 0x76, 0x6A, 0x5A, 0x46, 0x33, 0x21, 0x13, 0x09, 0x03,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-11dB*/
+	{0x81, 0x7C, 0x71, 0x5F, 0x4A, 0x36, 0x23, 0x14, 0x0A, 0x03,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-10.5dB*/
+	{0x88, 0x84, 0x77, 0x65, 0x4F, 0x39, 0x25, 0x15, 0x0A, 0x03,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-10dB*/
+	{0x90, 0x8C, 0x7E, 0x6B, 0x54, 0x3C, 0x27, 0x17, 0x0B, 0x03,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-9.5dB*/
+	{0x99, 0x94, 0x86, 0x71, 0x58, 0x40, 0x2A, 0x18, 0x0B, 0x04,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-9dB*/
+	{0xA2, 0x9D, 0x8E, 0x78, 0x5E, 0x43, 0x2C, 0x19, 0x0C, 0x04,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-8.5dB*/
+	{0xAC, 0xA6, 0x96, 0x7F, 0x63, 0x47, 0x2F, 0x1B, 0x0D, 0x04,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-8dB*/
+	{0xB6, 0xB0, 0x9F, 0x87, 0x69, 0x4C, 0x32, 0x1D, 0x0D, 0x04,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-7.5dB*/
+	{0xC1, 0xBA, 0xA8, 0x8F, 0x6F, 0x50, 0x35, 0x1E, 0x0E, 0x04,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-7dB*/
+	{0xCC, 0xC5, 0xB2, 0x97, 0x76, 0x55, 0x38, 0x20, 0x0F, 0x05,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-6.5dB*/
+	{0xD8, 0xD1, 0xBD, 0xA0, 0x7D, 0x5A, 0x3B, 0x22, 0x10, 0x05,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00} /*-6dB*/
+};
+
+u8 cck_swing_table_ch14_88f[CCK_TABLE_SIZE_88F][16] = {
+	{0x44, 0x42, 0x3C, 0x28, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-16dB*/
+	{0x48, 0x46, 0x3F, 0x2A, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-15.5dB*/
+	{0x4D, 0x4A, 0x43, 0x2C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-15dB*/
+	{0x51, 0x4F, 0x47, 0x2F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-14.5dB*/
+	{0x56, 0x53, 0x4B, 0x32, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-14dB*/
+	{0x5B, 0x58, 0x50, 0x35, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-13.5dB*/
+	{0x60, 0x5D, 0x54, 0x38, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-13dB*/
+	{0x66, 0x63, 0x59, 0x3B, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-12.5dB*/
+	{0x6C, 0x69, 0x5F, 0x3F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-12dB*/
+	{0x73, 0x6F, 0x64, 0x42, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-11.5dB*/
+	{0x79, 0x76, 0x6A, 0x46, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-11dB*/
+	{0x81, 0x7C, 0x71, 0x4A, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-10.5dB*/
+	{0x88, 0x84, 0x77, 0x4F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-10dB*/
+	{0x90, 0x8C, 0x7E, 0x54, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-9.5dB*/
+	{0x99, 0x94, 0x86, 0x58, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-9dB*/
+	{0xA2, 0x9D, 0x8E, 0x5E, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-8.5dB*/
+	{0xAC, 0xA6, 0x96, 0x63, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-8dB*/
+	{0xB6, 0xB0, 0x9F, 0x69, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-7.5dB*/
+	{0xC1, 0xBA, 0xA8, 0x6F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-7dB*/
+	{0xCC, 0xC5, 0xB2, 0x76, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-6.5dB*/
+	{0xD8, 0xD1, 0xBD, 0x7D, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00} /*-6dB*/
+};
+
+u8 cck_swing_table_ch1_ch13_new[CCK_TABLE_SIZE][8] = {
+	{0x09, 0x08, 0x07, 0x06, 0x04, 0x03, 0x01, 0x01}, /*   0, -16.0dB*/
+	{0x09, 0x09, 0x08, 0x06, 0x05, 0x03, 0x01, 0x01}, /*   1, -15.5dB*/
+	{0x0a, 0x09, 0x08, 0x07, 0x05, 0x03, 0x02, 0x01}, /*   2, -15.0dB*/
+	{0x0a, 0x0a, 0x09, 0x07, 0x05, 0x03, 0x02, 0x01}, /*   3, -14.5dB*/
+	{0x0b, 0x0a, 0x09, 0x08, 0x06, 0x04, 0x02, 0x01}, /*   4, -14.0dB*/
+	{0x0b, 0x0b, 0x0a, 0x08, 0x06, 0x04, 0x02, 0x01}, /*   5, -13.5dB*/
+	{0x0c, 0x0c, 0x0a, 0x09, 0x06, 0x04, 0x02, 0x01}, /*   6, -13.0dB*/
+	{0x0d, 0x0c, 0x0b, 0x09, 0x07, 0x04, 0x02, 0x01}, /*   7, -12.5dB*/
+	{0x0d, 0x0d, 0x0c, 0x0a, 0x07, 0x05, 0x02, 0x01}, /*   8, -12.0dB*/
+	{0x0e, 0x0e, 0x0c, 0x0a, 0x08, 0x05, 0x02, 0x01}, /*   9, -11.5dB*/
+	{0x0f, 0x0f, 0x0d, 0x0b, 0x08, 0x05, 0x03, 0x01}, /*  10, -11.0dB*/
+	{0x10, 0x10, 0x0e, 0x0b, 0x08, 0x05, 0x03, 0x01}, /*  11, -10.5dB*/
+	{0x11, 0x11, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01}, /*  12, -10.0dB*/
+	{0x12, 0x12, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01}, /*  13, -9.5dB*/
+	{0x13, 0x13, 0x10, 0x0d, 0x0a, 0x06, 0x03, 0x01}, /*  14, -9.0dB */
+	{0x14, 0x14, 0x11, 0x0e, 0x0b, 0x07, 0x03, 0x02}, /*  15, -8.5dB*/
+	{0x16, 0x15, 0x12, 0x0f, 0x0b, 0x07, 0x04, 0x01}, /*  16, -8.0dB */
+	{0x17, 0x16, 0x13, 0x10, 0x0c, 0x08, 0x04, 0x02}, /*  17, -7.5dB*/
+	{0x18, 0x17, 0x15, 0x11, 0x0c, 0x08, 0x04, 0x02}, /*  18, -7.0dB */
+	{0x1a, 0x19, 0x16, 0x12, 0x0d, 0x09, 0x04, 0x02}, /*  19, -6.5dB*/
+	{0x1b, 0x1a, 0x17, 0x13, 0x0e, 0x09, 0x04, 0x02}, /*  20, -6.0dB */
+	{0x1d, 0x1c, 0x18, 0x14, 0x0f, 0x0a, 0x05, 0x02}, /*  21, -5.5dB*/
+	{0x1f, 0x1e, 0x1a, 0x15, 0x10, 0x0a, 0x05, 0x02}, /*  22, -5.0dB */
+	{0x20, 0x20, 0x1b, 0x16, 0x11, 0x08, 0x05, 0x02}, /*  23, -4.5dB*/
+	{0x22, 0x21, 0x1d, 0x18, 0x11, 0x0b, 0x06, 0x02}, /*  24, -4.0dB */
+	{0x24, 0x23, 0x1f, 0x19, 0x13, 0x0c, 0x06, 0x03}, /*  25, -3.5dB*/
+	{0x26, 0x25, 0x21, 0x1b, 0x14, 0x0d, 0x06, 0x03}, /*  26, -3.0dB*/
+	{0x28, 0x28, 0x22, 0x1c, 0x15, 0x0d, 0x07, 0x03}, /*  27, -2.5dB*/
+	{0x2b, 0x2a, 0x25, 0x1e, 0x16, 0x0e, 0x07, 0x03}, /*  28, -2.0dB */
+	{0x2d, 0x2d, 0x27, 0x1f, 0x18, 0x0f, 0x08, 0x03}, /*  29, -1.5dB*/
+	{0x30, 0x2f, 0x29, 0x21, 0x19, 0x10, 0x08, 0x03}, /*  30, -1.0dB*/
+	{0x33, 0x32, 0x2b, 0x23, 0x1a, 0x11, 0x08, 0x04}, /*  31, -0.5dB*/
+	{0x36, 0x35, 0x2e, 0x25, 0x1c, 0x12, 0x09, 0x04} /*   32, +0dB*/
+};
+
+u8 cck_swing_table_ch14_new[CCK_TABLE_SIZE][8] = {
+	{0x09, 0x08, 0x07, 0x04, 0x00, 0x00, 0x00, 0x00}, /*  0, -16.0dB*/
+	{0x09, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 1, -15.5dB*/
+	{0x0a, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00}, /*  2, -15.0dB*/
+	{0x0a, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 3, -14.5dB*/
+	{0x0b, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00}, /*  4, -14.0dB*/
+	{0x0b, 0x0b, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00}, /*5, -13.5dB*/
+	{0x0c, 0x0c, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00}, /* 6, -13.0dB*/
+	{0x0d, 0x0c, 0x0b, 0x06, 0x00, 0x00, 0x00, 0x00}, /*  7, -12.5dB*/
+	{0x0d, 0x0d, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00}, /* 8, -12.0dB*/
+	{0x0e, 0x0e, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00}, /* 9, -11.5dB*/
+	{0x0f, 0x0f, 0x0d, 0x08, 0x00, 0x00, 0x00, 0x00}, /* 10, -11.0dB*/
+	{0x10, 0x10, 0x0e, 0x08, 0x00, 0x00, 0x00, 0x00}, /*11, -10.5dB*/
+	{0x11, 0x11, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00}, /* 12, -10.0dB*/
+	{0x12, 0x12, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00}, /* 13, -9.5dB*/
+	{0x13, 0x13, 0x10, 0x0a, 0x00, 0x00, 0x00, 0x00}, /*14, -9.0dB */
+	{0x14, 0x14, 0x11, 0x0a, 0x00, 0x00, 0x00, 0x00}, /* 15, -8.5dB*/
+	{0x16, 0x15, 0x12, 0x0b, 0x00, 0x00, 0x00, 0x00}, /* 16, -8.0dB */
+	{0x17, 0x16, 0x13, 0x0b, 0x00, 0x00, 0x00, 0x00}, /* 17, -7.5dB*/
+	{0x18, 0x17, 0x15, 0x0c, 0x00, 0x00, 0x00, 0x00}, /* 18, -7.0dB */
+	{0x1a, 0x19, 0x16, 0x0d, 0x00, 0x00, 0x00, 0x00}, /* 19, -6.5dB */
+	{0x1b, 0x1a, 0x17, 0x0e, 0x00, 0x00, 0x00, 0x00}, /* 20, -6.0dB */
+	{0x1d, 0x1c, 0x18, 0x0e, 0x00, 0x00, 0x00, 0x00}, /* 21, -5.5dB*/
+	{0x1f, 0x1e, 0x1a, 0x0f, 0x00, 0x00, 0x00, 0x00}, /* 22, -5.0dB */
+	{0x20, 0x20, 0x1b, 0x10, 0x00, 0x00, 0x00, 0x00}, /*23, -4.5dB*/
+	{0x22, 0x21, 0x1d, 0x11, 0x00, 0x00, 0x00, 0x00}, /* 24, -4.0dB */
+	{0x24, 0x23, 0x1f, 0x12, 0x00, 0x00, 0x00, 0x00}, /* 25, -3.5dB */
+	{0x26, 0x25, 0x21, 0x13, 0x00, 0x00, 0x00, 0x00}, /* 26, -3.0dB */
+	{0x28, 0x28, 0x24, 0x14, 0x00, 0x00, 0x00, 0x00}, /*27, -2.5dB*/
+	{0x2b, 0x2a, 0x25, 0x15, 0x00, 0x00, 0x00, 0x00}, /* 28, -2.0dB */
+	{0x2d, 0x2d, 0x17, 0x17, 0x00, 0x00, 0x00, 0x00}, /*29, -1.5dB*/
+	{0x30, 0x2f, 0x29, 0x18, 0x00, 0x00, 0x00, 0x00}, /* 30, -1.0dB */
+	{0x33, 0x32, 0x2b, 0x19, 0x00, 0x00, 0x00, 0x00}, /* 31, -0.5dB */
+	{0x36, 0x35, 0x2e, 0x1b, 0x00, 0x00, 0x00, 0x00} /* 32, +0dB	*/
+};
+
+u32 cck_swing_table_ch1_ch14_8723d[CCK_TABLE_SIZE_8723D] = {
+	0x0CD, /*0 ,    -20dB*/
+	0x0D9,
+	0x0E6,
+	0x0F3,
+	0x102,
+	0x111,
+	0x121,
+	0x132,
+	0x144,
+	0x158,
+	0x16C,
+	0x182,
+	0x198,
+	0x1B1,
+	0x1CA,
+	0x1E5,
+	0x202,
+	0x221,
+	0x241,
+	0x263,
+	0x287,
+	0x2AE,
+	0x2D6,
+	0x301,
+	0x32F,
+	0x35F,
+	0x392,
+	0x3C9,
+	0x402,
+	0x43F,
+	0x47F,
+	0x4C3,
+	0x50C,
+	0x558,
+	0x5A9,
+	0x5FF,
+	0x65A,
+	0x6BA,
+	0x720,
+	0x78C,
+	0x7FF,
+};
+
+/* JJ ADD 20161014 */
+u32 cck_swing_table_ch1_ch14_8710b[CCK_TABLE_SIZE_8710B] = {
+	0x0CD, /*0 ,    -20dB*/
+	0x0D9,
+	0x0E6,
+	0x0F3,
+	0x102,
+	0x111,
+	0x121,
+	0x132,
+	0x144,
+	0x158,
+	0x16C,
+	0x182,
+	0x198,
+	0x1B1,
+	0x1CA,
+	0x1E5,
+	0x202,
+	0x221,
+	0x241,
+	0x263,
+	0x287,
+	0x2AE,
+	0x2D6,
+	0x301,
+	0x32F,
+	0x35F,
+	0x392,
+	0x3C9,
+	0x402,
+	0x43F,
+	0x47F,
+	0x4C3,
+	0x50C,
+	0x558,
+	0x5A9,
+	0x5FF,
+	0x65A,
+	0x6BA,
+	0x720,
+	0x78C,
+	0x7FF,
+};
+
+/* Winnita ADD 20171116 PathA 0xAB4[10:0],PathB 0xAB4[21:11]*/
+u32 cck_swing_table_ch1_ch14_8192f[CCK_TABLE_SIZE_8192F] = {
+	0x0CD, /*0 ,    -20dB*/
+	0x0D9,
+	0x0E6,
+	0x0F3,
+	0x102,
+	0x111,
+	0x121,
+	0x132,
+	0x144,
+	0x158,
+	0x16C,
+	0x182,
+	0x198,
+	0x1B1,
+	0x1CA,
+	0x1E5,
+	0x202,
+	0x221,
+	0x241,
+	0x263, /*19*/
+	0x287, /*20*/
+	0x2AE, /*21*/
+	0x2D6, /*22*/
+	0x301, /*23*/
+	0x32F, /*24*/
+	0x35F, /*25*/
+	0x392, /*26*/
+	0x3C9, /*27*/
+	0x402, /*28*/
+	0x43F, /*29*/
+	0x47F, /*30*/
+	0x4C3, /*31*/
+	0x50C, /*32*/
+	0x558, /*33*/
+	0x5A9, /*34*/
+	0x5FF, /*35*/
+	0x65A, /*36*/
+	0x6BA,
+	0x720,
+	0x78C,
+	0x7FF,
+};
+
+u32 tx_scaling_table_jaguar[TXSCALE_TABLE_SIZE] = {
+	0x081, /* 0,  -12.0dB*/
+	0x088, /* 1,  -11.5dB*/
+	0x090, /* 2,  -11.0dB*/
+	0x099, /* 3,  -10.5dB*/
+	0x0A2, /* 4,  -10.0dB*/
+	0x0AC, /* 5,  -9.5dB*/
+	0x0B6, /* 6,  -9.0dB*/
+	0x0C0, /*7,  -8.5dB*/
+	0x0CC, /* 8,  -8.0dB*/
+	0x0D8, /* 9,  -7.5dB*/
+	0x0E5, /* 10, -7.0dB*/
+	0x0F2, /* 11, -6.5dB*/
+	0x101, /* 12, -6.0dB*/
+	0x110, /* 13, -5.5dB*/
+	0x120, /* 14, -5.0dB*/
+	0x131, /* 15, -4.5dB*/
+	0x143, /* 16, -4.0dB*/
+	0x156, /* 17, -3.5dB*/
+	0x16A, /* 18, -3.0dB*/
+	0x180, /* 19, -2.5dB*/
+	0x197, /* 20, -2.0dB*/
+	0x1AF, /* 21, -1.5dB*/
+	0x1C8, /* 22, -1.0dB*/
+	0x1E3, /* 23, -0.5dB*/
+	0x200, /* 24, +0  dB*/
+	0x21E, /* 25, +0.5dB*/
+	0x23E, /* 26, +1.0dB*/
+	0x261, /* 27, +1.5dB*/
+	0x285, /* 28, +2.0dB*/
+	0x2AB, /* 29, +2.5dB*/
+	0x2D3, /*30, +3.0dB*/
+	0x2FE, /* 31, +3.5dB*/
+	0x32B, /* 32, +4.0dB*/
+	0x35C, /* 33, +4.5dB*/
+	0x38E, /* 34, +5.0dB*/
+	0x3C4, /* 35, +5.5dB*/
+	0x3FE /* 36, +6.0dB	*/
+};
+
+#if (DM_ODM_SUPPORT_TYPE == ODM_CE) && defined(DM_ODM_CE_MAC80211)
+#else
+u8 delta_swing_table_idx_2ga_p_8188e[] = {0, 0, 0, 0, 1, 1, 2, 2, 3, 3,
+					  4, 4, 4, 4, 4, 4, 4, 4, 5, 5,
+					  7, 7, 8, 8, 8, 9, 9, 9, 9, 9};
+u8 delta_swing_table_idx_2ga_n_8188e[] = {0, 0, 0, 2, 2, 3, 3, 4, 4, 4,
+					  4, 5, 5, 6, 6, 7, 7, 7, 7, 8,
+					  8, 9, 9, 10, 10, 10, 11, 11, 11, 11};
+#endif
+
+void odm_txpowertracking_init(void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+
+	odm_txpowertracking_thermal_meter_init(dm);
+}
+
+u8 get_swing_index(void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+#if ((RTL8812A_SUPPORT == 1) || (RTL8821A_SUPPORT == 1))
+	void *adapter = dm->adapter;
+	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
+#endif
+	u8 i = 0;
+	u32 bb_swing, table_value;
+
+	if (dm->support_ic_type &
+		(ODM_RTL8188E | ODM_RTL8723B | ODM_RTL8192E |
+		ODM_RTL8188F | ODM_RTL8703B | ODM_RTL8723D |
+		ODM_RTL8710B | ODM_RTL8821)) {
+#if (RTL8821A_SUPPORT == 1)
+		bb_swing =
+		phy_get_tx_bb_swing_8812a(adapter,
+					  hal_data->current_band_type,
+					  RF_PATH_A);
+#else
+		bb_swing = odm_get_bb_reg(dm, R_0xc80, 0xFFC00000);
+#endif
+		for (i = 0; i < OFDM_TABLE_SIZE; i++) {
+			table_value = ofdm_swing_table_new[i];
+
+			if (table_value >= 0x100000)
+				table_value >>= 22;
+			if (bb_swing == table_value)
+				break;
+		}
+	} else {
+#if (RTL8812A_SUPPORT == 1)
+		bb_swing =
+		phy_get_tx_bb_swing_8812a(adapter,
+					  hal_data->current_band_type,
+					  RF_PATH_A);
+#else
+		bb_swing = odm_get_bb_reg(dm, R_0xc1c, 0xFFE00000);
+#endif
+		for (i = 0; i < TXSCALE_TABLE_SIZE; i++) {
+			table_value = tx_scaling_table_jaguar[i];
+
+			if (bb_swing == table_value)
+				break;
+		}
+	}
+
+	return i;
+}
+
+u8 get_cck_swing_index(void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+
+	u8 i = 0;
+	u32 bb_cck_swing;
+
+	if (dm->support_ic_type &
+		(ODM_RTL8188E | ODM_RTL8723B | ODM_RTL8192E)) {
+		bb_cck_swing = odm_read_1byte(dm, 0xa22);
+
+		for (i = 0; i < CCK_TABLE_SIZE; i++) {
+			if (bb_cck_swing == cck_swing_table_ch1_ch13_new[i][0])
+				break;
+		}
+	} else if (dm->support_ic_type & ODM_RTL8703B) {
+		bb_cck_swing = odm_read_1byte(dm, 0xa22);
+
+		for (i = 0; i < CCK_TABLE_SIZE_88F; i++) {
+			if (bb_cck_swing == cck_swing_table_ch1_ch14_88f[i][0])
+				break;
+		}
+	}
+
+	return i;
+}
+
+void odm_txpowertracking_thermal_meter_init(void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	u8 swing_idx = get_swing_index(dm);
+	u8 cckswing_idx = get_cck_swing_index(dm);
+	u8 p = 0;
+	struct dm_rf_calibration_struct *cali_info = &dm->rf_calibrate_info;
+	struct _hal_rf_ *rf = &dm->rf_table;
+
+	cali_info->is_txpowertracking = true;
+	cali_info->tx_powercount = 0;
+	cali_info->is_txpowertracking_init = false;
+
+	if (!(*dm->mp_mode))
+		cali_info->txpowertrack_control = true;
+	else
+		cali_info->txpowertrack_control = false;
+
+	if (!(*dm->mp_mode))
+		cali_info->txpowertrack_control = true;
+
+	RF_DBG(dm, DBG_RF_IQK, "dm txpowertrack_control = %d\n",
+	       cali_info->txpowertrack_control);
+#if 0
+	/* dm->rf_calibrate_info.txpowertrack_control = true; */
+#endif
+	cali_info->thermal_value = rf->eeprom_thermal;
+	cali_info->thermal_value_iqk = rf->eeprom_thermal;
+	cali_info->thermal_value_lck = rf->eeprom_thermal;
+
+	if (!cali_info->default_bb_swing_index_flag) {
+		if (dm->support_ic_type &
+			(ODM_RTL8188E | ODM_RTL8723B | ODM_RTL8192E |
+			ODM_RTL8703B | ODM_RTL8821)) {
+			if (swing_idx >= OFDM_TABLE_SIZE)
+				cali_info->default_ofdm_index = 30;
+			else
+				cali_info->default_ofdm_index = swing_idx;
+
+			if (cckswing_idx >= CCK_TABLE_SIZE)
+				cali_info->default_cck_index = 20;
+			else
+				cali_info->default_cck_index = cckswing_idx;
+		/*add by Mingzhi.Guo  2015-03-23*/
+		} else if (dm->support_ic_type == ODM_RTL8188F) {
+			cali_info->default_ofdm_index = 28; /*OFDM: -1dB*/
+			cali_info->default_cck_index = 20; /*CCK:-6dB*/
+		/*add by zhaohe  2015-10-27*/
+		} else if (dm->support_ic_type == ODM_RTL8723D) {
+			cali_info->default_ofdm_index = 28; /*OFDM: -1dB*/
+			cali_info->default_cck_index = 28; /*CCK:   -6dB*/
+		/* JJ ADD 20161014 */
+		} else if (dm->support_ic_type == ODM_RTL8710B) {
+			cali_info->default_ofdm_index = 28; /*OFDM: -1dB*/
+			cali_info->default_cck_index = 28; /*CCK:   -6dB*/
+		} else if (dm->support_ic_type == ODM_RTL8192F) {
+			cali_info->default_ofdm_index = 30;/*OFDM: 0dB*/
+			cali_info->default_cck_index = 28; /*CCK:   -6dB*/
+		} else {
+			if (swing_idx >= TXSCALE_TABLE_SIZE)
+				cali_info->default_ofdm_index = 24;
+			else
+				cali_info->default_ofdm_index = swing_idx;
+
+			cali_info->default_cck_index = 24;
+		}
+		cali_info->default_bb_swing_index_flag = true;
+	}
+
+	cali_info->bb_swing_idx_cck_base = cali_info->default_cck_index;
+	cali_info->CCK_index = cali_info->default_cck_index;
+
+	for (p = RF_PATH_A; p < MAX_RF_PATH; ++p) {
+		cali_info->bb_swing_idx_ofdm_base[p] =
+						cali_info->default_ofdm_index;
+		cali_info->OFDM_index[p] = cali_info->default_ofdm_index;
+		cali_info->delta_power_index[p] = 0;
+		cali_info->delta_power_index_last[p] = 0;
+		cali_info->power_index_offset[p] = 0;
+	}
+	cali_info->modify_tx_agc_value_ofdm = 0;
+	cali_info->modify_tx_agc_value_cck = 0;
+	cali_info->tm_trigger = 0;
+}
+
+void odm_txpowertracking_check(void *dm_void)
+{
+	/* 2011/09/29 MH In HW integration first stage
+	 * we provide 4 different handle to operate at the same time.
+	 * In the stage2/3, we need to prive universal interface and merge all
+	 * HW dynamic mechanism.
+	 */
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+
+	switch (dm->support_platform) {
+	case ODM_WIN:
+		odm_txpowertracking_check_mp(dm);
+		break;
+
+	case ODM_CE:
+		odm_txpowertracking_check_ce(dm);
+		break;
+
+	case ODM_AP:
+		odm_txpowertracking_check_ap(dm);
+		break;
+
+	default:
+		break;
+	}
+}
+
+void odm_txpowertracking_check_ce(void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct _hal_rf_ *rf = &dm->rf_table;
+
+#if (DM_ODM_SUPPORT_TYPE == ODM_CE)
+	if (!(rf->rf_supportability & HAL_RF_TX_PWR_TRACK))
+		return;
+
+	if (!dm->rf_calibrate_info.tm_trigger) {
+		if (dm->support_ic_type &
+			(ODM_RTL8188E | ODM_RTL8188F | ODM_RTL8192E |
+			ODM_RTL8723B | ODM_RTL8812 | ODM_RTL8821 |
+			ODM_RTL8814A | ODM_RTL8703B | ODM_RTL8723D |
+			ODM_RTL8822B | ODM_RTL8821C | ODM_RTL8710B |
+			ODM_RTL8192F))
+			odm_set_rf_reg(dm, RF_PATH_A, RF_T_METER_NEW,
+				       (BIT(17) | BIT(16)), 0x03);
+		else
+			odm_set_rf_reg(dm, RF_PATH_A, RF_T_METER_OLD,
+				       RFREGOFFSETMASK, 0x60);
+
+		dm->rf_calibrate_info.tm_trigger = 1;
+		return;
+	}
+
+	odm_txpowertracking_callback_thermal_meter(dm);
+	dm->rf_calibrate_info.tm_trigger = 0;
+#endif
+}
+
+void odm_txpowertracking_check_mp(void *dm_void)
+{
+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	void *adapter = dm->adapter;
+
+	if (odm_check_power_status(adapter) == false) {
+		RT_TRACE(COMP_POWER_TRACKING, DBG_LOUD,
+			 ("check_pow_status, return false\n"));
+		return;
+	}
+
+	odm_txpowertracking_thermal_meter_check(adapter);
+#endif
+}
+
+void odm_txpowertracking_check_ap(void *dm_void)
+{
+#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct rtl8192cd_priv *priv = dm->priv;
+
+	return;
+
+#endif
+}
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/halrf/halrf_powertracking_ce.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/halrf/halrf_powertracking_ce.h
--- linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/halrf/halrf_powertracking_ce.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/halrf/halrf_powertracking_ce.h	2020-04-10 16:35:06.820660254 +0300
@@ -0,0 +1,325 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017  Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * The full GNU General Public License is included in this distribution in the
+ * file called LICENSE.
+ *
+ * Contact Information:
+ * wlanfae <wlanfae@realtek.com>
+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
+ * Hsinchu 300, Taiwan.
+ *
+ * Larry Finger <Larry.Finger@lwfinger.net>
+ *
+ *****************************************************************************/
+
+#ifndef __HALRF_POWERTRACKING_H__
+#define __HALRF_POWERTRACKING_H__
+
+#define DPK_DELTA_MAPPING_NUM 13
+#define index_mapping_HP_NUM 15
+#define OFDM_TABLE_SIZE 43
+#define CCK_TABLE_SIZE 33
+#define CCK_TABLE_SIZE_88F 21
+#define TXSCALE_TABLE_SIZE 37
+#define CCK_TABLE_SIZE_8723D 41
+/* JJ ADD 20161014 */
+#define CCK_TABLE_SIZE_8710B 41
+#define CCK_TABLE_SIZE_8192F 41
+
+#define TXPWR_TRACK_TABLE_SIZE 30
+#define DELTA_SWINGIDX_SIZE 30
+#define DELTA_SWINTSSI_SIZE 61
+#define BAND_NUM 4
+
+#define AVG_THERMAL_NUM 8
+#define IQK_MAC_REG_NUM 4
+#define IQK_ADDA_REG_NUM 16
+#define IQK_BB_REG_NUM_MAX 10
+
+#define IQK_BB_REG_NUM 9
+
+#define iqk_matrix_reg_num 8
+#if (DM_ODM_SUPPORT_TYPE == ODM_CE) && defined(DM_ODM_CE_MAC80211)
+#else
+/* Channels_2_4G_NUM + Channels_5G_20M_NUM + Channels_5G */
+#define IQK_MATRIX_SETTINGS_NUM (14 + 24 + 21)
+#endif
+
+extern u32 ofdm_swing_table[OFDM_TABLE_SIZE];
+extern u8 cck_swing_table_ch1_ch13[CCK_TABLE_SIZE][8];
+extern u8 cck_swing_table_ch14[CCK_TABLE_SIZE][8];
+
+extern u32 ofdm_swing_table_new[OFDM_TABLE_SIZE];
+extern u8 cck_swing_table_ch1_ch13_new[CCK_TABLE_SIZE][8];
+extern u8 cck_swing_table_ch14_new[CCK_TABLE_SIZE][8];
+extern u8 cck_swing_table_ch1_ch14_88f[CCK_TABLE_SIZE_88F][16];
+extern u8 cck_swing_table_ch1_ch13_88f[CCK_TABLE_SIZE_88F][16];
+extern u8 cck_swing_table_ch14_88f[CCK_TABLE_SIZE_88F][16];
+extern u32 cck_swing_table_ch1_ch14_8723d[CCK_TABLE_SIZE_8723D];
+/* JJ ADD 20161014 */
+extern u32 cck_swing_table_ch1_ch14_8710b[CCK_TABLE_SIZE_8710B];
+extern u32 cck_swing_table_ch1_ch14_8192f[CCK_TABLE_SIZE_8192F];
+
+extern u32 tx_scaling_table_jaguar[TXSCALE_TABLE_SIZE];
+
+/* <20121018, Kordan> In case fail to read TxPowerTrack.txt */
+/* we use the table of 88E as the default table. */
+#if (DM_ODM_SUPPORT_TYPE == ODM_CE) && defined(DM_ODM_CE_MAC80211)
+#else
+extern u8 delta_swing_table_idx_2ga_p_8188e[];
+extern u8 delta_swing_table_idx_2ga_n_8188e[];
+#endif
+
+#define dm_check_txpowertracking odm_txpowertracking_check
+
+struct iqk_matrix_regs_setting {
+	boolean is_iqk_done;
+	s32 value[3][iqk_matrix_reg_num];
+	boolean is_bw_iqk_result_saved[3];
+};
+
+struct dm_rf_calibration_struct {
+	/* for tx power tracking */
+
+	u32 rega24; /* for TempCCK */
+	s32 rege94;
+	s32 rege9c;
+	s32 regeb4;
+	s32 regebc;
+
+	u8 tx_powercount;
+	boolean is_txpowertracking_init;
+	boolean is_txpowertracking;
+	/* for mp mode, turn off txpwrtracking as default */
+	u8 txpowertrack_control;
+	u8 tm_trigger;
+	u8 internal_pa_5g[2]; /* pathA / pathB */
+
+	/* thermal_meter, index 0 for RFIC0, and 1 for RFIC1 */
+	u8 thermal_meter[2];
+	u8 thermal_value;
+	u8 thermal_value_lck;
+	u8 thermal_value_iqk;
+	s8 thermal_value_delta; /* delta of thermal_value and efuse thermal */
+	u8 thermal_value_dpk;
+	u8 thermal_value_avg[AVG_THERMAL_NUM];
+	u8 thermal_value_avg_index;
+	u8 thermal_value_rx_gain;
+	u8 thermal_value_crystal;
+	u8 thermal_value_dpk_store;
+	u8 thermal_value_dpk_track;
+	boolean txpowertracking_in_progress;
+
+	boolean is_reloadtxpowerindex;
+	u8 is_rf_pi_enable;
+	u32 txpowertracking_callback_cnt; /* cosa add for debug */
+
+	/* ---------------------- Tx power Tracking ---------------------- */
+	u8 is_cck_in_ch14;
+	u8 CCK_index;
+	u8 OFDM_index[MAX_RF_PATH];
+	s8 power_index_offset[MAX_RF_PATH];
+	s8 delta_power_index[MAX_RF_PATH];
+	s8 delta_power_index_last[MAX_RF_PATH];
+	boolean is_tx_power_changed;
+	s8 xtal_offset;
+	s8 xtal_offset_last;
+	u8 xtal_offset_eanble;
+
+	struct iqk_matrix_regs_setting
+				iqk_matrix_reg_setting[IQK_MATRIX_SETTINGS_NUM];
+	u8 delta_lck;
+	s8 bb_swing_diff_2g, bb_swing_diff_5g; /* Unit: dB */
+	u8 delta_swing_table_idx_2g_cck_a_p[DELTA_SWINGIDX_SIZE];
+	u8 delta_swing_table_idx_2g_cck_a_n[DELTA_SWINGIDX_SIZE];
+	u8 delta_swing_table_idx_2g_cck_b_p[DELTA_SWINGIDX_SIZE];
+	u8 delta_swing_table_idx_2g_cck_b_n[DELTA_SWINGIDX_SIZE];
+	u8 delta_swing_table_idx_2g_cck_c_p[DELTA_SWINGIDX_SIZE];
+	u8 delta_swing_table_idx_2g_cck_c_n[DELTA_SWINGIDX_SIZE];
+	u8 delta_swing_table_idx_2g_cck_d_p[DELTA_SWINGIDX_SIZE];
+	u8 delta_swing_table_idx_2g_cck_d_n[DELTA_SWINGIDX_SIZE];
+	u8 delta_swing_table_idx_2ga_p[DELTA_SWINGIDX_SIZE];
+	u8 delta_swing_table_idx_2ga_n[DELTA_SWINGIDX_SIZE];
+	u8 delta_swing_table_idx_2gb_p[DELTA_SWINGIDX_SIZE];
+	u8 delta_swing_table_idx_2gb_n[DELTA_SWINGIDX_SIZE];
+	u8 delta_swing_table_idx_2gc_p[DELTA_SWINGIDX_SIZE];
+	u8 delta_swing_table_idx_2gc_n[DELTA_SWINGIDX_SIZE];
+	u8 delta_swing_table_idx_2gd_p[DELTA_SWINGIDX_SIZE];
+	u8 delta_swing_table_idx_2gd_n[DELTA_SWINGIDX_SIZE];
+	u8 delta_swing_table_idx_5ga_p[BAND_NUM][DELTA_SWINGIDX_SIZE];
+	u8 delta_swing_table_idx_5ga_n[BAND_NUM][DELTA_SWINGIDX_SIZE];
+	u8 delta_swing_table_idx_5gb_p[BAND_NUM][DELTA_SWINGIDX_SIZE];
+	u8 delta_swing_table_idx_5gb_n[BAND_NUM][DELTA_SWINGIDX_SIZE];
+	u8 delta_swing_table_idx_5gc_p[BAND_NUM][DELTA_SWINGIDX_SIZE];
+	u8 delta_swing_table_idx_5gc_n[BAND_NUM][DELTA_SWINGIDX_SIZE];
+	u8 delta_swing_table_idx_5gd_p[BAND_NUM][DELTA_SWINGIDX_SIZE];
+	u8 delta_swing_table_idx_5gd_n[BAND_NUM][DELTA_SWINGIDX_SIZE];
+	u8 delta_swing_tssi_table_2g_cck_a[DELTA_SWINTSSI_SIZE];
+	u8 delta_swing_tssi_table_2g_cck_b[DELTA_SWINTSSI_SIZE];
+	u8 delta_swing_tssi_table_2g_cck_c[DELTA_SWINTSSI_SIZE];
+	u8 delta_swing_tssi_table_2g_cck_d[DELTA_SWINTSSI_SIZE];
+	u8 delta_swing_tssi_table_2ga[DELTA_SWINTSSI_SIZE];
+	u8 delta_swing_tssi_table_2gb[DELTA_SWINTSSI_SIZE];
+	u8 delta_swing_tssi_table_2gc[DELTA_SWINTSSI_SIZE];
+	u8 delta_swing_tssi_table_2gd[DELTA_SWINTSSI_SIZE];
+	u8 delta_swing_tssi_table_5ga[BAND_NUM][DELTA_SWINTSSI_SIZE];
+	u8 delta_swing_tssi_table_5gb[BAND_NUM][DELTA_SWINTSSI_SIZE];
+	u8 delta_swing_tssi_table_5gc[BAND_NUM][DELTA_SWINTSSI_SIZE];
+	u8 delta_swing_tssi_table_5gd[BAND_NUM][DELTA_SWINTSSI_SIZE];
+	s8 delta_swing_table_xtal_p[DELTA_SWINGIDX_SIZE];
+	s8 delta_swing_table_xtal_n[DELTA_SWINGIDX_SIZE];
+	u8 delta_swing_table_idx_2ga_p_8188e[DELTA_SWINGIDX_SIZE];
+	u8 delta_swing_table_idx_2ga_n_8188e[DELTA_SWINGIDX_SIZE];
+
+	u8 bb_swing_idx_ofdm[MAX_RF_PATH];
+	u8 bb_swing_idx_ofdm_current;
+#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
+	u8 bb_swing_idx_ofdm_base[MAX_RF_PATH];
+#else
+	u8 bb_swing_idx_ofdm_base;
+#endif
+	boolean default_bb_swing_index_flag;
+	boolean bb_swing_flag_ofdm;
+	u8 bb_swing_idx_cck;
+	u8 bb_swing_idx_cck_current;
+	u8 bb_swing_idx_cck_base;
+	u8 default_ofdm_index;
+	u8 default_cck_index;
+	boolean bb_swing_flag_cck;
+
+	s8 absolute_ofdm_swing_idx[MAX_RF_PATH];
+	s8 remnant_ofdm_swing_idx[MAX_RF_PATH];
+	s8 absolute_cck_swing_idx[MAX_RF_PATH];
+	s8 remnant_cck_swing_idx;
+	s8 modify_tx_agc_value; /*Remnat compensate value at tx_agc */
+	boolean modify_tx_agc_flag_path_a;
+	boolean modify_tx_agc_flag_path_b;
+	boolean modify_tx_agc_flag_path_c;
+	boolean modify_tx_agc_flag_path_d;
+	boolean modify_tx_agc_flag_path_a_cck;
+	boolean modify_tx_agc_flag_path_b_cck;
+
+	s8 kfree_offset[MAX_RF_PATH];
+
+	/* ----------------------------------------------------------------- */
+
+	/* for IQK */
+	u32 regc04;
+	u32 reg874;
+	u32 regc08;
+	u32 regb68;
+	u32 regb6c;
+	u32 reg870;
+	u32 reg860;
+	u32 reg864;
+
+	boolean is_iqk_initialized;
+	boolean is_lck_in_progress;
+	boolean is_antenna_detected;
+	boolean is_need_iqk;
+	boolean is_iqk_in_progress;
+	boolean is_iqk_pa_off;
+	u8 delta_iqk;
+	u32 ADDA_backup[IQK_ADDA_REG_NUM];
+	u32 IQK_MAC_backup[IQK_MAC_REG_NUM];
+	u32 IQK_BB_backup_recover[9];
+	u32 IQK_BB_backup[IQK_BB_REG_NUM];
+	/* { {S1: 0xc94, 0xc80, 0xc4c} , {S0: 0xc9c, 0xc88, 0xc4c}} */
+	u32 tx_iqc_8723b[2][3][2];
+	/* { {S1: 0xc14, 0xca0} , {S0: 0xc14, 0xca0}} */
+	u32 rx_iqc_8723b[2][2][2];
+	/* { {S1: 0xc94, 0xc80, 0xc4c} , {S0: 0xc9c, 0xc88, 0xc4c}} */
+	u32 tx_iqc_8703b[3][2];
+	/* { {S1: 0xc14, 0xca0} , {S0: 0xc14, 0xca0}} */
+	u32 rx_iqc_8703b[2][2];
+	/* { {S1: 0xc94, 0xc80, 0xc4c} , {S0: 0xc9c, 0xc88, 0xc4c}} */
+	u32 tx_iqc_8723d[2][3][2];
+	/* { {S1: 0xc14, 0xca0} , {S0: 0xc14, 0xca0}} */
+	u32 rx_iqc_8723d[2][2][2];
+	/* JJ ADD 20161014 */
+	/* { {S1: 0xc94, 0xc80, 0xc4c} , {S0: 0xc9c, 0xc88, 0xc4c}} */
+	u32 tx_iqc_8710b[2][3][2];
+	/* { {S1: 0xc14, 0xca0} , {S0: 0xc14, 0xca0}} */
+	u32 rx_iqc_8710b[2][2][2];
+
+	u8 iqk_step;
+	u8 kcount;
+	u8 retry_count[4][2]; /* [4]: path ABCD, [2] TXK, RXK */
+	boolean is_mp_mode;
+
+	/* <James> IQK time measurement */
+	u64 iqk_start_time;
+	u64 iqk_progressing_time;
+	u64 iqk_total_progressing_time;
+	u64 lck_progressing_time;
+
+	u32 lok_result;
+
+	/* for APK */
+	u32 ap_koutput[2][2]; /* path A/B; output1_1a/output1_2a */
+	u8 is_ap_kdone;
+	u8 is_apk_thermal_meter_ignore;
+
+	/* DPK */
+	boolean is_dpk_fail;
+	u8 is_dp_done;
+	u8 is_dp_path_aok;
+	u8 is_dp_path_bok;
+
+	u32 tx_lok[2];
+	u32 dpk_tx_agc;
+	s32 dpk_gain;
+	u32 dpk_thermal[4];
+	s8 modify_tx_agc_value_ofdm;
+	s8 modify_tx_agc_value_cck;
+
+	/*Add by Yuchen for Kfree Phydm*/
+	u8 reg_rf_kfree_enable; /*for registry*/
+	u8 rf_kfree_enable; /*for efuse enable check*/
+};
+
+void odm_txpowertracking_check(void *dm_void);
+
+void odm_txpowertracking_init(void *dm_void);
+
+void odm_txpowertracking_check_ap(void *dm_void);
+
+void odm_txpowertracking_thermal_meter_init(void *dm_void);
+
+void odm_txpowertracking_init(void *dm_void);
+
+void odm_txpowertracking_check_mp(void *dm_void);
+
+void odm_txpowertracking_check_ce(void *dm_void);
+
+#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN))
+
+void odm_txpowertracking_callback_thermal_meter92c(
+	void *adapter);
+
+void odm_txpowertracking_callback_rx_gain_thermal_meter92d(
+	void *adapter);
+
+void odm_txpowertracking_callback_thermal_meter92d(
+	void *adapter);
+
+void odm_txpowertracking_direct_call92c(
+	void *adapter);
+
+void odm_txpowertracking_thermal_meter_check(
+	void *adapter);
+
+#endif
+
+#endif /*#ifndef __HALRF_POWER_TRACKING_H__*/
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/halrf/halrf_powertracking.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/halrf/halrf_powertracking.h
--- linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/halrf/halrf_powertracking.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/halrf/halrf_powertracking.h	2020-04-10 16:35:06.820660254 +0300
@@ -0,0 +1,41 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017  Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * The full GNU General Public License is included in this distribution in the
+ * file called LICENSE.
+ *
+ * Contact Information:
+ * wlanfae <wlanfae@realtek.com>
+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
+ * Hsinchu 300, Taiwan.
+ *
+ * Larry Finger <Larry.Finger@lwfinger.net>
+ *
+ *****************************************************************************/
+
+#ifndef __HALRF_POWER_TRACKING_H__
+#define __HALRF_POWER_TRACKING_H__
+
+boolean
+odm_check_power_status(void *dm_void);
+
+#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
+void halrf_update_pwr_track(void *dm_void, u8 rate);
+#endif
+
+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
+void halrf_update_init_rate_work_item_callback(
+	void *context);
+#endif
+
+#endif /*#ifndef __HALRF_POWERTRACKING_H__*/
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/halrf/halrf_powertracking_iot.c linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/halrf/halrf_powertracking_iot.c
--- linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/halrf/halrf_powertracking_iot.c	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/halrf/halrf_powertracking_iot.c	2020-04-10 16:35:06.820660254 +0300
@@ -0,0 +1,690 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017  Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * The full GNU General Public License is included in this distribution in the
+ * file called LICENSE.
+ *
+ * Contact Information:
+ * wlanfae <wlanfae@realtek.com>
+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
+ * Hsinchu 300, Taiwan.
+ *
+ * Larry Finger <Larry.Finger@lwfinger.net>
+ *
+ *****************************************************************************/
+
+/*============================================================	*/
+/* include files												*/
+/*============================================================	*/
+#include "mp_precomp.h"
+#include "phydm_precomp.h"
+
+/* ************************************************************
+ * Global var
+ * ************************************************************
+ */
+
+u32	ofdm_swing_table[OFDM_TABLE_SIZE] = {
+	0x7f8001fe,	/* 0, +6.0dB */
+	0x788001e2,	/* 1, +5.5dB */
+	0x71c001c7,	/* 2, +5.0dB*/
+	0x6b8001ae,	/* 3, +4.5dB*/
+	0x65400195,	/* 4, +4.0dB*/
+	0x5fc0017f,	/* 5, +3.5dB*/
+	0x5a400169,	/* 6, +3.0dB*/
+	0x55400155,	/* 7, +2.5dB*/
+	0x50800142,	/* 8, +2.0dB*/
+	0x4c000130,	/* 9, +1.5dB*/
+	0x47c0011f,	/* 10, +1.0dB*/
+	0x43c0010f,	/* 11, +0.5dB*/
+	0x40000100,	/* 12, +0dB*/
+	0x3c8000f2,	/* 13, -0.5dB*/
+	0x390000e4,	/* 14, -1.0dB*/
+	0x35c000d7,	/* 15, -1.5dB*/
+	0x32c000cb,	/* 16, -2.0dB*/
+	0x300000c0,	/* 17, -2.5dB*/
+	0x2d4000b5,	/* 18, -3.0dB*/
+	0x2ac000ab,	/* 19, -3.5dB*/
+	0x288000a2,	/* 20, -4.0dB*/
+	0x26000098,	/* 21, -4.5dB*/
+	0x24000090,	/* 22, -5.0dB*/
+	0x22000088,	/* 23, -5.5dB*/
+	0x20000080,	/* 24, -6.0dB*/
+	0x1e400079,	/* 25, -6.5dB*/
+	0x1c800072,	/* 26, -7.0dB*/
+	0x1b00006c,	/* 27. -7.5dB*/
+	0x19800066,	/* 28, -8.0dB*/
+	0x18000060,	/* 29, -8.5dB*/
+	0x16c0005b,	/* 30, -9.0dB*/
+	0x15800056,	/* 31, -9.5dB*/
+	0x14400051,	/* 32, -10.0dB*/
+	0x1300004c,	/* 33, -10.5dB*/
+	0x12000048,	/* 34, -11.0dB*/
+	0x11000044,	/* 35, -11.5dB*/
+	0x10000040,	/* 36, -12.0dB*/
+};
+
+u8	cck_swing_table_ch1_ch13[CCK_TABLE_SIZE][8] = {
+	{0x36, 0x35, 0x2e, 0x25, 0x1c, 0x12, 0x09, 0x04},	/* 0, +0dB */
+	{0x33, 0x32, 0x2b, 0x23, 0x1a, 0x11, 0x08, 0x04},	/* 1, -0.5dB */
+	{0x30, 0x2f, 0x29, 0x21, 0x19, 0x10, 0x08, 0x03},	/* 2, -1.0dB*/
+	{0x2d, 0x2d, 0x27, 0x1f, 0x18, 0x0f, 0x08, 0x03},	/* 3, -1.5dB*/
+	{0x2b, 0x2a, 0x25, 0x1e, 0x16, 0x0e, 0x07, 0x03},	/* 4, -2.0dB */
+	{0x28, 0x28, 0x22, 0x1c, 0x15, 0x0d, 0x07, 0x03},	/* 5, -2.5dB*/
+	{0x26, 0x25, 0x21, 0x1b, 0x14, 0x0d, 0x06, 0x03},	/* 6, -3.0dB*/
+	{0x24, 0x23, 0x1f, 0x19, 0x13, 0x0c, 0x06, 0x03},	/* 7, -3.5dB*/
+	{0x22, 0x21, 0x1d, 0x18, 0x11, 0x0b, 0x06, 0x02},	/* 8, -4.0dB */
+	{0x20, 0x20, 0x1b, 0x16, 0x11, 0x08, 0x05, 0x02},	/* 9, -4.5dB*/
+	{0x1f, 0x1e, 0x1a, 0x15, 0x10, 0x0a, 0x05, 0x02},	/* 10, -5.0dB */
+	{0x1d, 0x1c, 0x18, 0x14, 0x0f, 0x0a, 0x05, 0x02},	/* 11, -5.5dB*/
+	{0x1b, 0x1a, 0x17, 0x13, 0x0e, 0x09, 0x04, 0x02},	/* 12, -6.0dB <== default */
+	{0x1a, 0x19, 0x16, 0x12, 0x0d, 0x09, 0x04, 0x02},	/* 13, -6.5dB*/
+	{0x18, 0x17, 0x15, 0x11, 0x0c, 0x08, 0x04, 0x02},	/* 14, -7.0dB */
+	{0x17, 0x16, 0x13, 0x10, 0x0c, 0x08, 0x04, 0x02},	/* 15, -7.5dB*/
+	{0x16, 0x15, 0x12, 0x0f, 0x0b, 0x07, 0x04, 0x01},	/* 16, -8.0dB */
+	{0x14, 0x14, 0x11, 0x0e, 0x0b, 0x07, 0x03, 0x02},	/* 17, -8.5dB*/
+	{0x13, 0x13, 0x10, 0x0d, 0x0a, 0x06, 0x03, 0x01},	/* 18, -9.0dB */
+	{0x12, 0x12, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01},	/* 19, -9.5dB*/
+	{0x11, 0x11, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01},	/* 20, -10.0dB*/
+	{0x10, 0x10, 0x0e, 0x0b, 0x08, 0x05, 0x03, 0x01},	/* 21, -10.5dB*/
+	{0x0f, 0x0f, 0x0d, 0x0b, 0x08, 0x05, 0x03, 0x01},	/* 22, -11.0dB*/
+	{0x0e, 0x0e, 0x0c, 0x0a, 0x08, 0x05, 0x02, 0x01},	/* 23, -11.5dB*/
+	{0x0d, 0x0d, 0x0c, 0x0a, 0x07, 0x05, 0x02, 0x01},	/* 24, -12.0dB*/
+	{0x0d, 0x0c, 0x0b, 0x09, 0x07, 0x04, 0x02, 0x01},	/* 25, -12.5dB*/
+	{0x0c, 0x0c, 0x0a, 0x09, 0x06, 0x04, 0x02, 0x01},	/* 26, -13.0dB*/
+	{0x0b, 0x0b, 0x0a, 0x08, 0x06, 0x04, 0x02, 0x01},	/* 27, -13.5dB*/
+	{0x0b, 0x0a, 0x09, 0x08, 0x06, 0x04, 0x02, 0x01},	/* 28, -14.0dB*/
+	{0x0a, 0x0a, 0x09, 0x07, 0x05, 0x03, 0x02, 0x01},	/* 29, -14.5dB*/
+	{0x0a, 0x09, 0x08, 0x07, 0x05, 0x03, 0x02, 0x01},	/* 30, -15.0dB*/
+	{0x09, 0x09, 0x08, 0x06, 0x05, 0x03, 0x01, 0x01},	/* 31, -15.5dB*/
+	{0x09, 0x08, 0x07, 0x06, 0x04, 0x03, 0x01, 0x01}	/* 32, -16.0dB*/
+};
+
+u8	cck_swing_table_ch14[CCK_TABLE_SIZE][8] = {
+	{0x36, 0x35, 0x2e, 0x1b, 0x00, 0x00, 0x00, 0x00},	/* 0, +0dB */
+	{0x33, 0x32, 0x2b, 0x19, 0x00, 0x00, 0x00, 0x00},	/* 1, -0.5dB */
+	{0x30, 0x2f, 0x29, 0x18, 0x00, 0x00, 0x00, 0x00},	/* 2, -1.0dB */
+	{0x2d, 0x2d, 0x17, 0x17, 0x00, 0x00, 0x00, 0x00},	/* 3, -1.5dB*/
+	{0x2b, 0x2a, 0x25, 0x15, 0x00, 0x00, 0x00, 0x00},	/* 4, -2.0dB */
+	{0x28, 0x28, 0x24, 0x14, 0x00, 0x00, 0x00, 0x00},	/* 5, -2.5dB*/
+	{0x26, 0x25, 0x21, 0x13, 0x00, 0x00, 0x00, 0x00},	/* 6, -3.0dB */
+	{0x24, 0x23, 0x1f, 0x12, 0x00, 0x00, 0x00, 0x00},	/* 7, -3.5dB */
+	{0x22, 0x21, 0x1d, 0x11, 0x00, 0x00, 0x00, 0x00},	/* 8, -4.0dB */
+	{0x20, 0x20, 0x1b, 0x10, 0x00, 0x00, 0x00, 0x00},	/* 9, -4.5dB*/
+	{0x1f, 0x1e, 0x1a, 0x0f, 0x00, 0x00, 0x00, 0x00},	/* 10, -5.0dB */
+	{0x1d, 0x1c, 0x18, 0x0e, 0x00, 0x00, 0x00, 0x00},	/* 11, -5.5dB*/
+	{0x1b, 0x1a, 0x17, 0x0e, 0x00, 0x00, 0x00, 0x00},	/* 12, -6.0dB  <== default*/
+	{0x1a, 0x19, 0x16, 0x0d, 0x00, 0x00, 0x00, 0x00},	/* 13, -6.5dB */
+	{0x18, 0x17, 0x15, 0x0c, 0x00, 0x00, 0x00, 0x00},	/* 14, -7.0dB */
+	{0x17, 0x16, 0x13, 0x0b, 0x00, 0x00, 0x00, 0x00},	/* 15, -7.5dB*/
+	{0x16, 0x15, 0x12, 0x0b, 0x00, 0x00, 0x00, 0x00},	/* 16, -8.0dB */
+	{0x14, 0x14, 0x11, 0x0a, 0x00, 0x00, 0x00, 0x00},	/* 17, -8.5dB*/
+	{0x13, 0x13, 0x10, 0x0a, 0x00, 0x00, 0x00, 0x00},	/* 18, -9.0dB */
+	{0x12, 0x12, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00},	/* 19, -9.5dB*/
+	{0x11, 0x11, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00},	/* 20, -10.0dB*/
+	{0x10, 0x10, 0x0e, 0x08, 0x00, 0x00, 0x00, 0x00},	/* 21, -10.5dB*/
+	{0x0f, 0x0f, 0x0d, 0x08, 0x00, 0x00, 0x00, 0x00},	/* 22, -11.0dB*/
+	{0x0e, 0x0e, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00},	/* 23, -11.5dB*/
+	{0x0d, 0x0d, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00},	/* 24, -12.0dB*/
+	{0x0d, 0x0c, 0x0b, 0x06, 0x00, 0x00, 0x00, 0x00},	/* 25, -12.5dB*/
+	{0x0c, 0x0c, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00},	/* 26, -13.0dB*/
+	{0x0b, 0x0b, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00},	/* 27, -13.5dB*/
+	{0x0b, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00},	/* 28, -14.0dB*/
+	{0x0a, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00},	/* 29, -14.5dB*/
+	{0x0a, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00},	/* 30, -15.0dB*/
+	{0x09, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00},	/* 31, -15.5dB*/
+	{0x09, 0x08, 0x07, 0x04, 0x00, 0x00, 0x00, 0x00}	/* 32, -16.0dB*/
+};
+
+u32 ofdm_swing_table_new[OFDM_TABLE_SIZE] = {
+	0x0b40002d, /* 0,  -15.0dB	*/
+	0x0c000030, /* 1,  -14.5dB*/
+	0x0cc00033, /* 2,  -14.0dB*/
+	0x0d800036, /* 3,  -13.5dB*/
+	0x0e400039, /* 4,  -13.0dB */
+	0x0f00003c, /* 5,  -12.5dB*/
+	0x10000040, /* 6,  -12.0dB*/
+	0x11000044, /* 7,  -11.5dB*/
+	0x12000048, /* 8,  -11.0dB*/
+	0x1300004c, /* 9,  -10.5dB*/
+	0x14400051, /* 10, -10.0dB*/
+	0x15800056, /* 11, -9.5dB*/
+	0x16c0005b, /* 12, -9.0dB*/
+	0x18000060, /* 13, -8.5dB*/
+	0x19800066, /* 14, -8.0dB*/
+	0x1b00006c, /* 15, -7.5dB*/
+	0x1c800072, /* 16, -7.0dB*/
+	0x1e400079, /* 17, -6.5dB*/
+	0x20000080, /* 18, -6.0dB*/
+	0x22000088, /* 19, -5.5dB*/
+	0x24000090, /* 20, -5.0dB*/
+	0x26000098, /* 21, -4.5dB*/
+	0x288000a2, /* 22, -4.0dB*/
+	0x2ac000ab, /* 23, -3.5dB*/
+	0x2d4000b5, /* 24, -3.0dB*/
+	0x300000c0, /* 25, -2.5dB*/
+	0x32c000cb, /* 26, -2.0dB*/
+	0x35c000d7, /* 27, -1.5dB*/
+	0x390000e4, /* 28, -1.0dB*/
+	0x3c8000f2, /* 29, -0.5dB*/
+	0x40000100, /* 30, +0dB*/
+	0x43c0010f, /* 31, +0.5dB*/
+	0x47c0011f, /* 32, +1.0dB*/
+	0x4c000130, /* 33, +1.5dB*/
+	0x50800142, /* 34, +2.0dB*/
+	0x55400155, /* 35, +2.5dB*/
+	0x5a400169, /* 36, +3.0dB*/
+	0x5fc0017f, /* 37, +3.5dB*/
+	0x65400195, /* 38, +4.0dB*/
+	0x6b8001ae, /* 39, +4.5dB*/
+	0x71c001c7, /* 40, +5.0dB*/
+	0x788001e2, /* 41, +5.5dB*/
+	0x7f8001fe  /* 42, +6.0dB*/
+};
+
+u8 cck_swing_table_ch1_ch14_88f[CCK_TABLE_SIZE_88F][16] = {
+	{0x44, 0x42, 0x3C, 0x33, 0x28, 0x1C, 0x13, 0x0B, 0x05, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-16dB*/
+	{0x48, 0x46, 0x3F, 0x36, 0x2A, 0x1E, 0x14, 0x0B, 0x05, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-15.5dB*/
+	{0x4D, 0x4A, 0x43, 0x39, 0x2C, 0x20, 0x15, 0x0C, 0x06, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-15dB*/
+	{0x51, 0x4F, 0x47, 0x3C, 0x2F, 0x22, 0x16, 0x0D, 0x06, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-14.5dB*/
+	{0x56, 0x53, 0x4B, 0x40, 0x32, 0x24, 0x17, 0x0E, 0x06, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-14dB*/
+	{0x5B, 0x58, 0x50, 0x43, 0x35, 0x26, 0x19, 0x0E, 0x07, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-13.5dB*/
+	{0x60, 0x5D, 0x54, 0x47, 0x38, 0x28, 0x1A, 0x0F, 0x07, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-13dB*/
+	{0x66, 0x63, 0x59, 0x4C, 0x3B, 0x2B, 0x1C, 0x10, 0x08, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-12.5dB*/
+	{0x6C, 0x69, 0x5F, 0x50, 0x3F, 0x2D, 0x1E, 0x11, 0x08, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-12dB*/
+	{0x73, 0x6F, 0x64, 0x55, 0x42, 0x30, 0x1F, 0x12, 0x08, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-11.5dB*/
+	{0x79, 0x76, 0x6A, 0x5A, 0x46, 0x33, 0x21, 0x13, 0x09, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-11dB*/
+	{0x81, 0x7C, 0x71, 0x5F, 0x4A, 0x36, 0x23, 0x14, 0x0A, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-10.5dB*/
+	{0x88, 0x84, 0x77, 0x65, 0x4F, 0x39, 0x25, 0x15, 0x0A, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-10dB*/
+	{0x90, 0x8C, 0x7E, 0x6B, 0x54, 0x3C, 0x27, 0x17, 0x0B, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-9.5dB*/
+	{0x99, 0x94, 0x86, 0x71, 0x58, 0x40, 0x2A, 0x18, 0x0B, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-9dB*/
+	{0xA2, 0x9D, 0x8E, 0x78, 0x5E, 0x43, 0x2C, 0x19, 0x0C, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-8.5dB*/
+	{0xAC, 0xA6, 0x96, 0x7F, 0x63, 0x47, 0x2F, 0x1B, 0x0D, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-8dB*/
+	{0xB6, 0xB0, 0x9F, 0x87, 0x69, 0x4C, 0x32, 0x1D, 0x0D, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-7.5dB*/
+	{0xC1, 0xBA, 0xA8, 0x8F, 0x6F, 0x50, 0x35, 0x1E, 0x0E, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-7dB*/
+	{0xCC, 0xC5, 0xB2, 0x97, 0x76, 0x55, 0x38, 0x20, 0x0F, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-6.5dB*/
+	{0xD8, 0xD1, 0xBD, 0xA0, 0x7D, 0x5A, 0x3B, 0x22, 0x10, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}     /*-6dB*/
+};
+
+u8 cck_swing_table_ch1_ch13_88f[CCK_TABLE_SIZE_88F][16] = {
+	{0x44, 0x42, 0x3C, 0x33, 0x28, 0x1C, 0x13, 0x0B, 0x05, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-16dB*/
+	{0x48, 0x46, 0x3F, 0x36, 0x2A, 0x1E, 0x14, 0x0B, 0x05, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-15.5dB*/
+	{0x4D, 0x4A, 0x43, 0x39, 0x2C, 0x20, 0x15, 0x0C, 0x06, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-15dB*/
+	{0x51, 0x4F, 0x47, 0x3C, 0x2F, 0x22, 0x16, 0x0D, 0x06, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-14.5dB*/
+	{0x56, 0x53, 0x4B, 0x40, 0x32, 0x24, 0x17, 0x0E, 0x06, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-14dB*/
+	{0x5B, 0x58, 0x50, 0x43, 0x35, 0x26, 0x19, 0x0E, 0x07, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-13.5dB*/
+	{0x60, 0x5D, 0x54, 0x47, 0x38, 0x28, 0x1A, 0x0F, 0x07, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-13dB*/
+	{0x66, 0x63, 0x59, 0x4C, 0x3B, 0x2B, 0x1C, 0x10, 0x08, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-12.5dB*/
+	{0x6C, 0x69, 0x5F, 0x50, 0x3F, 0x2D, 0x1E, 0x11, 0x08, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-12dB*/
+	{0x73, 0x6F, 0x64, 0x55, 0x42, 0x30, 0x1F, 0x12, 0x08, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-11.5dB*/
+	{0x79, 0x76, 0x6A, 0x5A, 0x46, 0x33, 0x21, 0x13, 0x09, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-11dB*/
+	{0x81, 0x7C, 0x71, 0x5F, 0x4A, 0x36, 0x23, 0x14, 0x0A, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-10.5dB*/
+	{0x88, 0x84, 0x77, 0x65, 0x4F, 0x39, 0x25, 0x15, 0x0A, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-10dB*/
+	{0x90, 0x8C, 0x7E, 0x6B, 0x54, 0x3C, 0x27, 0x17, 0x0B, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-9.5dB*/
+	{0x99, 0x94, 0x86, 0x71, 0x58, 0x40, 0x2A, 0x18, 0x0B, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-9dB*/
+	{0xA2, 0x9D, 0x8E, 0x78, 0x5E, 0x43, 0x2C, 0x19, 0x0C, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-8.5dB*/
+	{0xAC, 0xA6, 0x96, 0x7F, 0x63, 0x47, 0x2F, 0x1B, 0x0D, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-8dB*/
+	{0xB6, 0xB0, 0x9F, 0x87, 0x69, 0x4C, 0x32, 0x1D, 0x0D, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-7.5dB*/
+	{0xC1, 0xBA, 0xA8, 0x8F, 0x6F, 0x50, 0x35, 0x1E, 0x0E, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-7dB*/
+	{0xCC, 0xC5, 0xB2, 0x97, 0x76, 0x55, 0x38, 0x20, 0x0F, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-6.5dB*/
+	{0xD8, 0xD1, 0xBD, 0xA0, 0x7D, 0x5A, 0x3B, 0x22, 0x10, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}     /*-6dB*/
+};
+
+u8 cck_swing_table_ch14_88f[CCK_TABLE_SIZE_88F][16] = {
+	{0x44,	 0x42, 0x3C, 0x28, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-16dB*/
+	{0x48, 0x46, 0x3F, 0x2A, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-15.5dB*/
+	{0x4D, 0x4A, 0x43, 0x2C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-15dB*/
+	{0x51, 0x4F, 0x47, 0x2F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},	    /*-14.5dB*/
+	{0x56, 0x53, 0x4B, 0x32, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-14dB*/
+	{0x5B, 0x58, 0x50, 0x35, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-13.5dB*/
+	{0x60, 0x5D, 0x54, 0x38, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-13dB*/
+	{0x66, 0x63, 0x59, 0x3B, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-12.5dB*/
+	{0x6C, 0x69, 0x5F, 0x3F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-12dB*/
+	{0x73, 0x6F, 0x64, 0x42, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-11.5dB*/
+	{0x79, 0x76, 0x6A, 0x46, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-11dB*/
+	{0x81, 0x7C, 0x71, 0x4A, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-10.5dB*/
+	{0x88, 0x84, 0x77, 0x4F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-10dB*/
+	{0x90, 0x8C, 0x7E, 0x54, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-9.5dB*/
+	{0x99, 0x94, 0x86, 0x58, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-9dB*/
+	{0xA2, 0x9D, 0x8E, 0x5E, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-8.5dB*/
+	{0xAC, 0xA6, 0x96, 0x63, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-8dB*/
+	{0xB6, 0xB0, 0x9F, 0x69, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-7.5dB*/
+	{0xC1, 0xBA, 0xA8, 0x6F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-7dB*/
+	{0xCC, 0xC5, 0xB2, 0x76, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-6.5dB*/
+	{0xD8, 0xD1, 0xBD, 0x7D, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}     /*-6dB*/
+};
+
+u8 cck_swing_table_ch1_ch13_new[CCK_TABLE_SIZE][8] = {
+	{0x09, 0x08, 0x07, 0x06, 0x04, 0x03, 0x01, 0x01},	/*  0, -16.0dB*/
+	{0x09, 0x09, 0x08, 0x06, 0x05, 0x03, 0x01, 0x01},	/*   1, -15.5dB*/
+	{0x0a, 0x09, 0x08, 0x07, 0x05, 0x03, 0x02, 0x01},	/*  2, -15.0dB*/
+	{0x0a, 0x0a, 0x09, 0x07, 0x05, 0x03, 0x02, 0x01},	/*   3, -14.5dB*/
+	{0x0b, 0x0a, 0x09, 0x08, 0x06, 0x04, 0x02, 0x01},	/*   4, -14.0dB*/
+	{0x0b, 0x0b, 0x0a, 0x08, 0x06, 0x04, 0x02, 0x01},	/*   5, -13.5dB*/
+	{0x0c, 0x0c, 0x0a, 0x09, 0x06, 0x04, 0x02, 0x01},	/*   6, -13.0dB*/
+	{0x0d, 0x0c, 0x0b, 0x09, 0x07, 0x04, 0x02, 0x01},	/*   7, -12.5dB*/
+	{0x0d, 0x0d, 0x0c, 0x0a, 0x07, 0x05, 0x02, 0x01},	/*  8, -12.0dB*/
+	{0x0e, 0x0e, 0x0c, 0x0a, 0x08, 0x05, 0x02, 0x01},	/*   9, -11.5dB*/
+	{0x0f, 0x0f, 0x0d, 0x0b, 0x08, 0x05, 0x03, 0x01},	/*  10, -11.0dB*/
+	{0x10, 0x10, 0x0e, 0x0b, 0x08, 0x05, 0x03, 0x01},	/*  11, -10.5dB*/
+	{0x11, 0x11, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01},	/*  12, -10.0dB*/
+	{0x12, 0x12, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01},	/*  13, -9.5dB*/
+	{0x13, 0x13, 0x10, 0x0d, 0x0a, 0x06, 0x03, 0x01},	/*  14, -9.0dB */
+	{0x14, 0x14, 0x11, 0x0e, 0x0b, 0x07, 0x03, 0x02},	/*  15, -8.5dB*/
+	{0x16, 0x15, 0x12, 0x0f, 0x0b, 0x07, 0x04, 0x01},	/*  16, -8.0dB */
+	{0x17, 0x16, 0x13, 0x10, 0x0c, 0x08, 0x04, 0x02},	/*  17, -7.5dB*/
+	{0x18, 0x17, 0x15, 0x11, 0x0c, 0x08, 0x04, 0x02},	/*  18, -7.0dB */
+	{0x1a, 0x19, 0x16, 0x12, 0x0d, 0x09, 0x04, 0x02},	/*  19, -6.5dB*/
+	{0x1b, 0x1a, 0x17, 0x13, 0x0e, 0x09, 0x04, 0x02},	/*20, -6.0dB */
+	{0x1d, 0x1c, 0x18, 0x14, 0x0f, 0x0a, 0x05, 0x02},	/*  21, -5.5dB*/
+	{0x1f, 0x1e, 0x1a, 0x15, 0x10, 0x0a, 0x05, 0x02},	/* 22, -5.0dB */
+	{0x20, 0x20, 0x1b, 0x16, 0x11, 0x08, 0x05, 0x02},	/*  23, -4.5dB*/
+	{0x22, 0x21, 0x1d, 0x18, 0x11, 0x0b, 0x06, 0x02},	/*  24, -4.0dB */
+	{0x24, 0x23, 0x1f, 0x19, 0x13, 0x0c, 0x06, 0x03},	/*  25, -3.5dB*/
+	{0x26, 0x25, 0x21, 0x1b, 0x14, 0x0d, 0x06, 0x03},	/*  26, -3.0dB*/
+	{0x28, 0x28, 0x22, 0x1c, 0x15, 0x0d, 0x07, 0x03},	/*  27, -2.5dB*/
+	{0x2b, 0x2a, 0x25, 0x1e, 0x16, 0x0e, 0x07, 0x03},	/*  28, -2.0dB */
+	{0x2d, 0x2d, 0x27, 0x1f, 0x18, 0x0f, 0x08, 0x03},	/*  29, -1.5dB*/
+	{0x30, 0x2f, 0x29, 0x21, 0x19, 0x10, 0x08, 0x03},	/*  30, -1.0dB*/
+	{0x33, 0x32, 0x2b, 0x23, 0x1a, 0x11, 0x08, 0x04},	/*  31, -0.5dB*/
+	{0x36, 0x35, 0x2e, 0x25, 0x1c, 0x12, 0x09, 0x04}	/*  32, +0dB*/
+};
+
+u8 cck_swing_table_ch14_new[CCK_TABLE_SIZE][8] = {
+	{0x09, 0x08, 0x07, 0x04, 0x00, 0x00, 0x00, 0x00},	/*  0, -16.0dB*/
+	{0x09, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00},	/* 1, -15.5dB*/
+	{0x0a, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00},	/*  2, -15.0dB*/
+	{0x0a, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00},	/* 3, -14.5dB*/
+	{0x0b, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00},	/*  4, -14.0dB*/
+	{0x0b, 0x0b, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00},	/*5, -13.5dB*/
+	{0x0c, 0x0c, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00},	/* 6, -13.0dB*/
+	{0x0d, 0x0c, 0x0b, 0x06, 0x00, 0x00, 0x00, 0x00},	/*  7, -12.5dB*/
+	{0x0d, 0x0d, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00},	/* 8, -12.0dB*/
+	{0x0e, 0x0e, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00},	/* 9, -11.5dB*/
+	{0x0f, 0x0f, 0x0d, 0x08, 0x00, 0x00, 0x00, 0x00},	/* 10, -11.0dB*/
+	{0x10, 0x10, 0x0e, 0x08, 0x00, 0x00, 0x00, 0x00},	/*11, -10.5dB*/
+	{0x11, 0x11, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00},	/* 12, -10.0dB*/
+	{0x12, 0x12, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00},	/* 13, -9.5dB*/
+	{0x13, 0x13, 0x10, 0x0a, 0x00, 0x00, 0x00, 0x00},	/*14, -9.0dB */
+	{0x14, 0x14, 0x11, 0x0a, 0x00, 0x00, 0x00, 0x00},	/* 15, -8.5dB*/
+	{0x16, 0x15, 0x12, 0x0b, 0x00, 0x00, 0x00, 0x00},	/* 16, -8.0dB */
+	{0x17, 0x16, 0x13, 0x0b, 0x00, 0x00, 0x00, 0x00},	/* 17, -7.5dB*/
+	{0x18, 0x17, 0x15, 0x0c, 0x00, 0x00, 0x00, 0x00},	/* 18, -7.0dB */
+	{0x1a, 0x19, 0x16, 0x0d, 0x00, 0x00, 0x00, 0x00},	/* 19, -6.5dB */
+	{0x1b, 0x1a, 0x17, 0x0e, 0x00, 0x00, 0x00, 0x00},	/* 20, -6.0dB */
+	{0x1d, 0x1c, 0x18, 0x0e, 0x00, 0x00, 0x00, 0x00},	/* 21, -5.5dB*/
+	{0x1f, 0x1e, 0x1a, 0x0f, 0x00, 0x00, 0x00, 0x00},	/* 22, -5.0dB */
+	{0x20, 0x20, 0x1b, 0x10, 0x00, 0x00, 0x00, 0x00},	/*23, -4.5dB*/
+	{0x22, 0x21, 0x1d, 0x11, 0x00, 0x00, 0x00, 0x00},	/* 24, -4.0dB */
+	{0x24, 0x23, 0x1f, 0x12, 0x00, 0x00, 0x00, 0x00},	/* 25, -3.5dB */
+	{0x26, 0x25, 0x21, 0x13, 0x00, 0x00, 0x00, 0x00},	/* 26, -3.0dB */
+	{0x28, 0x28, 0x24, 0x14, 0x00, 0x00, 0x00, 0x00},	/*27, -2.5dB*/
+	{0x2b, 0x2a, 0x25, 0x15, 0x00, 0x00, 0x00, 0x00},	/* 28, -2.0dB */
+	{0x2d, 0x2d, 0x17, 0x17, 0x00, 0x00, 0x00, 0x00},	/*29, -1.5dB*/
+	{0x30, 0x2f, 0x29, 0x18, 0x00, 0x00, 0x00, 0x00},	/* 30, -1.0dB */
+	{0x33, 0x32, 0x2b, 0x19, 0x00, 0x00, 0x00, 0x00},	/* 31, -0.5dB */
+	{0x36, 0x35, 0x2e, 0x1b, 0x00, 0x00, 0x00, 0x00}	/* 32, +0dB	*/
+};
+
+u32 cck_swing_table_ch1_ch14_8723d[CCK_TABLE_SIZE_8723D] = {
+	0x0CD,          /*0 ,    -20dB*/
+	0x0D9,
+	0x0E6,
+	0x0F3,
+	0x102,
+	0x111,
+	0x121,
+	0x132,
+	0x144,
+	0x158,
+	0x16C,
+	0x182,
+	0x198,
+	0x1B1,
+	0x1CA,
+	0x1E5,
+	0x202,
+	0x221,
+	0x241,
+	0x263,
+	0x287,
+	0x2AE,
+	0x2D6,
+	0x301,
+	0x32F,
+	0x35F,
+	0x392,
+	0x3C9,
+	0x402,
+	0x43F,
+	0x47F,
+	0x4C3,
+	0x50C,
+	0x558,
+	0x5A9,
+	0x5FF,
+	0x65A,
+	0x6BA,
+	0x720,
+	0x78C,
+	0x7FF,
+};
+
+/* JJ ADD 20161014 */
+u32 cck_swing_table_ch1_ch14_8710b[CCK_TABLE_SIZE_8710B] = {
+	0x0CD,          /*0 ,    -20dB*/
+	0x0D9,
+	0x0E6,
+	0x0F3,
+	0x102,
+	0x111,
+	0x121,
+	0x132,
+	0x144,
+	0x158,
+	0x16C,
+	0x182,
+	0x198,
+	0x1B1,
+	0x1CA,
+	0x1E5,
+	0x202,
+	0x221,
+	0x241,
+	0x263,
+	0x287,
+	0x2AE,
+	0x2D6,
+	0x301,
+	0x32F,
+	0x35F,
+	0x392,
+	0x3C9,
+	0x402,
+	0x43F,
+	0x47F,
+	0x4C3,
+	0x50C,
+	0x558,
+	0x5A9,
+	0x5FF,
+	0x65A,
+	0x6BA,
+	0x720,
+	0x78C,
+	0x7FF,
+};
+
+/* Winnita ADD 20171116 PathA 0xAB4[10:0],PathB 0xAB4[21:11]*/
+u32 cck_swing_table_ch1_ch14_8192f[CCK_TABLE_SIZE_8192F] = {
+	0x0CD,			 /*0 ,    -20dB*/
+	0x0D9,
+	0x0E6,
+	0x0F3,
+	0x102,
+	0x111,
+	0x121,
+	0x132,
+	0x144,
+	0x158,
+	0x16C,
+	0x182,
+	0x198,
+	0x1B1,
+	0x1CA,
+	0x1E5,
+	0x202,
+	0x221,
+	0x241,
+	0x263,		/*19*/
+	0x287,		/*20*/
+	0x2AE,		/*21*/
+	0x2D6,		/*22*/
+	0x301,		/*23*/
+	0x32F,		/*24*/
+	0x35F,		/*25*/
+	0x392,		/*26*/
+	0x3C9,		/*27*/
+	0x402,		/*28*/
+	0x43F,		/*29*/
+	0x47F,		/*30*/
+	0x4C3,		/*31*/
+	0x50C,		/*32*/
+	0x558,		/*33*/
+	0x5A9,		/*34*/
+	0x5FF,		/*35*/
+	0x65A,		/*36*/
+	0x6BA,
+	0x720,
+	0x78C,
+	0x7FF,
+};
+
+u32 tx_scaling_table_jaguar[TXSCALE_TABLE_SIZE] = {
+	0x081, /* 0,  -12.0dB*/
+	0x088, /* 1,  -11.5dB*/
+	0x090, /* 2,  -11.0dB*/
+	0x099, /* 3,  -10.5dB*/
+	0x0A2, /* 4,  -10.0dB*/
+	0x0AC, /* 5,  -9.5dB*/
+	0x0B6, /* 6,  -9.0dB*/
+	0x0C0, /*7,  -8.5dB*/
+	0x0CC, /* 8,  -8.0dB*/
+	0x0D8, /* 9,  -7.5dB*/
+	0x0E5, /* 10, -7.0dB*/
+	0x0F2, /* 11, -6.5dB*/
+	0x101, /* 12, -6.0dB*/
+	0x110, /* 13, -5.5dB*/
+	0x120, /* 14, -5.0dB*/
+	0x131, /* 15, -4.5dB*/
+	0x143, /* 16, -4.0dB*/
+	0x156, /* 17, -3.5dB*/
+	0x16A, /* 18, -3.0dB*/
+	0x180, /* 19, -2.5dB*/
+	0x197, /* 20, -2.0dB*/
+	0x1AF, /* 21, -1.5dB*/
+	0x1C8, /* 22, -1.0dB*/
+	0x1E3, /* 23, -0.5dB*/
+	0x200, /* 24, +0  dB*/
+	0x21E, /* 25, +0.5dB*/
+	0x23E, /* 26, +1.0dB*/
+	0x261, /* 27, +1.5dB*/
+	0x285,/* 28, +2.0dB*/
+	0x2AB, /* 29, +2.5dB*/
+	0x2D3, /*30, +3.0dB*/
+	0x2FE, /* 31, +3.5dB*/
+	0x32B, /* 32, +4.0dB*/
+	0x35C, /* 33, +4.5dB*/
+	0x38E, /* 34, +5.0dB*/
+	0x3C4, /* 35, +5.5dB*/
+	0x3FE  /* 36, +6.0dB	*/
+};
+
+void
+odm_txpowertracking_init(
+	void	*dm_void
+)
+{
+	struct dm_struct	*dm = (struct dm_struct *)dm_void;
+
+	odm_txpowertracking_thermal_meter_init(dm);
+}
+
+u8
+get_swing_index(
+	void	*dm_void
+)
+{
+	struct dm_struct	*dm = (struct dm_struct *)dm_void;
+
+	u8	i = 0;
+	u32	bb_swing;
+	u32	swing_table_size;
+	u32	*swing_table;
+
+	if (dm->support_ic_type == ODM_RTL8195B) {
+		bb_swing = odm_get_bb_reg(dm, R_0xc1c, 0xFFE00000);
+		swing_table = tx_scaling_table_jaguar;
+		swing_table_size = TXSCALE_TABLE_SIZE;
+	}
+
+	for (i = 0; i < swing_table_size; i++) {
+		u32 table_value = swing_table[i];
+
+		table_value = table_value;
+		if (bb_swing == table_value)
+			break;
+	}
+
+	return i;
+}
+
+u8
+get_cck_swing_index(
+	void		*dm_void
+)
+{
+	struct dm_struct		*dm = (struct dm_struct *)dm_void;
+
+	u8			i = 0;
+	u32			bb_cck_swing;
+
+	if (dm->support_ic_type == ODM_RTL8188E || dm->support_ic_type == ODM_RTL8723B ||
+	    dm->support_ic_type == ODM_RTL8192E) {
+		bb_cck_swing = odm_read_1byte(dm, 0xa22);
+
+		for (i = 0; i < CCK_TABLE_SIZE; i++) {
+			if (bb_cck_swing == cck_swing_table_ch1_ch13_new[i][0])
+				break;
+		}
+	} else if (dm->support_ic_type == ODM_RTL8703B) {
+		bb_cck_swing = odm_read_1byte(dm, 0xa22);
+
+		for (i = 0; i < CCK_TABLE_SIZE_88F; i++) {
+			if (bb_cck_swing == cck_swing_table_ch1_ch14_88f[i][0])
+				break;
+		}
+	}
+
+	return i;
+}
+
+void
+odm_txpowertracking_thermal_meter_init(
+	void	*dm_void
+)
+{
+	struct dm_struct	*dm = (struct dm_struct *)dm_void;
+	u8 default_swing_index = get_swing_index(dm);
+	u8 p = 0;
+	struct dm_rf_calibration_struct	*cali_info = &dm->rf_calibrate_info;
+	struct _hal_rf_ *rf = &dm->rf_table;
+
+	if (!(*dm->mp_mode))
+		cali_info->txpowertrack_control = true;
+	else
+		cali_info->txpowertrack_control = false;
+
+	RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "dm txpowertrack_control = %d\n", cali_info->txpowertrack_control);
+
+	/* dm->rf_calibrate_info.txpowertrack_control = true; */
+	cali_info->thermal_value = rf->eeprom_thermal;
+	cali_info->thermal_value_iqk = rf->eeprom_thermal;
+	cali_info->thermal_value_lck = rf->eeprom_thermal;
+
+	if (!cali_info->default_bb_swing_index_flag) {
+		if (dm->support_ic_type == ODM_RTL8195B) {
+			cali_info->default_ofdm_index = (default_swing_index >= TXSCALE_TABLE_SIZE) ? 24 : default_swing_index;
+			cali_info->default_cck_index = 24;
+		}
+		cali_info->default_bb_swing_index_flag = true;
+	}
+
+	cali_info->bb_swing_idx_cck_base = cali_info->default_cck_index;
+	cali_info->CCK_index = cali_info->default_cck_index;
+
+	for (p = RF_PATH_A; p < MAX_RF_PATH; ++p) {
+		cali_info->bb_swing_idx_ofdm_base[p] = cali_info->default_ofdm_index;
+		cali_info->OFDM_index[p] = cali_info->default_ofdm_index;
+		cali_info->delta_power_index[p] = 0;
+		cali_info->delta_power_index_last[p] = 0;
+		cali_info->power_index_offset[p] = 0;
+	}
+	cali_info->modify_tx_agc_value_ofdm = 0;
+	cali_info->modify_tx_agc_value_cck = 0;
+	cali_info->tm_trigger = 0;
+}
+
+void
+odm_txpowertracking_check(
+	void	*dm_void
+)
+{
+	struct dm_struct	*dm = (struct dm_struct *)dm_void;
+
+	odm_txpowertracking_check_iot(dm);
+}
+
+void
+odm_txpowertracking_check_iot(
+	void	*dm_void
+)
+{
+	struct dm_struct	*dm = (struct dm_struct *)dm_void;
+	struct _hal_rf_		*rf = &dm->rf_table;
+
+	if (!(rf->rf_supportability & HAL_RF_TX_PWR_TRACK))
+		return;
+
+	if (!dm->rf_calibrate_info.tm_trigger) {
+		if (dm->support_ic_type == ODM_RTL8195B)
+			odm_set_rf_reg(dm, RF_PATH_A, RF_T_METER_NEW, (BIT(17) | BIT(16)), 0x03);
+
+		dm->rf_calibrate_info.tm_trigger = 1;
+		return;
+	}
+	odm_txpowertracking_callback_thermal_meter(dm);
+	dm->rf_calibrate_info.tm_trigger = 0;
+}
+
+void
+odm_txpowertracking_check_mp(
+	void	*dm_void
+)
+{
+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
+	struct dm_struct		*dm = (struct dm_struct *)dm_void;
+	void	*adapter = dm->adapter;
+
+	if (odm_check_power_status(adapter) == false) {
+		RT_TRACE(COMP_POWER_TRACKING, DBG_LOUD, ("check_pow_status, return false\n"));
+		return;
+	}
+
+	odm_txpowertracking_thermal_meter_check(adapter);
+#endif
+}
+
+void
+odm_txpowertracking_check_ap(
+	void	*dm_void
+)
+{
+#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
+	struct dm_struct		*dm = (struct dm_struct *)dm_void;
+	struct rtl8192cd_priv	*priv		= dm->priv;
+
+	return;
+
+#endif
+}
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/halrf/halrf_powertracking_iot.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/halrf/halrf_powertracking_iot.h
--- linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/halrf/halrf_powertracking_iot.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/halrf/halrf_powertracking_iot.h	2020-04-10 16:35:06.820660254 +0300
@@ -0,0 +1,347 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017  Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * The full GNU General Public License is included in this distribution in the
+ * file called LICENSE.
+ *
+ * Contact Information:
+ * wlanfae <wlanfae@realtek.com>
+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
+ * Hsinchu 300, Taiwan.
+ *
+ * Larry Finger <Larry.Finger@lwfinger.net>
+ *
+ *****************************************************************************/
+
+#ifndef __HALRF_POWERTRACKING_H__
+#define __HALRF_POWERTRACKING_H__
+
+#define		DPK_DELTA_MAPPING_NUM	13
+#define		index_mapping_HP_NUM	15
+#define	OFDM_TABLE_SIZE	43
+#define	CCK_TABLE_SIZE			33
+#define	CCK_TABLE_SIZE_88F	21
+#define TXSCALE_TABLE_SIZE		37
+#define CCK_TABLE_SIZE_8723D	41
+/* JJ ADD 20161014 */
+#define CCK_TABLE_SIZE_8710B	41
+#define	CCK_TABLE_SIZE_8192F   41
+
+
+#define TXPWR_TRACK_TABLE_SIZE	30
+#define DELTA_SWINGIDX_SIZE     30
+#define DELTA_SWINTSSI_SIZE     61
+#define BAND_NUM				4
+
+#define AVG_THERMAL_NUM		8
+#define IQK_MAC_REG_NUM		4
+#define IQK_ADDA_REG_NUM		16
+#define IQK_BB_REG_NUM_MAX	10
+
+#define IQK_BB_REG_NUM		9
+
+
+
+#define iqk_matrix_reg_num	8
+#if (DM_ODM_SUPPORT_TYPE == ODM_CE) && defined(DM_ODM_CE_MAC80211)
+#else
+#define IQK_MATRIX_SETTINGS_NUM	(14+24+21) /* Channels_2_4G_NUM + Channels_5G_20M_NUM + Channels_5G */
+#endif
+
+extern	u32 ofdm_swing_table[OFDM_TABLE_SIZE];
+extern	u8 cck_swing_table_ch1_ch13[CCK_TABLE_SIZE][8];
+extern	u8 cck_swing_table_ch14[CCK_TABLE_SIZE][8];
+
+extern	u32 ofdm_swing_table_new[OFDM_TABLE_SIZE];
+extern	u8 cck_swing_table_ch1_ch13_new[CCK_TABLE_SIZE][8];
+extern	u8 cck_swing_table_ch14_new[CCK_TABLE_SIZE][8];
+extern	u8 cck_swing_table_ch1_ch14_88f[CCK_TABLE_SIZE_88F][16];
+extern	u8 cck_swing_table_ch1_ch13_88f[CCK_TABLE_SIZE_88F][16];
+extern	u8 cck_swing_table_ch14_88f[CCK_TABLE_SIZE_88F][16];
+extern	u32 cck_swing_table_ch1_ch14_8723d[CCK_TABLE_SIZE_8723D];
+/* JJ ADD 20161014 */
+extern	u32 cck_swing_table_ch1_ch14_8710b[CCK_TABLE_SIZE_8710B];
+extern	u32 cck_swing_table_ch1_ch14_8192f[CCK_TABLE_SIZE_8192F];
+
+extern  u32 tx_scaling_table_jaguar[TXSCALE_TABLE_SIZE];
+
+/* <20121018, Kordan> In case fail to read TxPowerTrack.txt, we use the table of 88E as the default table. */
+#if (DM_ODM_SUPPORT_TYPE == ODM_CE) && defined(DM_ODM_CE_MAC80211)
+#else
+static u8 delta_swing_table_idx_2ga_p_8188e[] = {0, 0, 0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 4,  4,  4,  4,  4,  4,  5,  5,  7,  7,  8,  8,  8,  9,  9,  9,  9,  9};
+static u8 delta_swing_table_idx_2ga_n_8188e[] = {0, 0, 0, 2, 2, 3, 3, 4, 4, 4, 4, 5, 5,  6,  6,  7,  7,  7,  7,  8,  8,  9,  9, 10, 10, 10, 11, 11, 11, 11};
+#endif
+
+void
+odm_txpowertracking_init(
+	void		*dm_void
+);
+
+#define dm_check_txpowertracking	odm_txpowertracking_check
+
+struct iqk_matrix_regs_setting {
+	boolean	is_iqk_done;
+	s32		value[3][iqk_matrix_reg_num];
+	boolean	is_bw_iqk_result_saved[3];
+};
+
+struct dm_rf_calibration_struct {
+	/* for tx power tracking */
+
+	u32	rega24; /* for TempCCK */
+	s32	rege94;
+	s32	rege9c;
+	s32	regeb4;
+	s32	regebc;
+
+	u8	tx_powercount;
+	boolean is_txpowertracking_init;
+	boolean is_txpowertracking;
+	u8  	txpowertrack_control; /* for mp mode, turn off txpwrtracking as default */
+	u8	tm_trigger;
+	u8  	internal_pa_5g[2];	/* pathA / pathB */
+
+	u8  	thermal_meter[2];    /* thermal_meter, index 0 for RFIC0, and 1 for RFIC1 */
+	u8	thermal_value;
+	u8	thermal_value_lck;
+	u8	thermal_value_iqk;
+	s8  	thermal_value_delta; /* delta of thermal_value and efuse thermal */
+	u8	thermal_value_dpk;
+	u8	thermal_value_avg[AVG_THERMAL_NUM];
+	u8	thermal_value_avg_index;
+	u8	thermal_value_rx_gain;
+	u8	thermal_value_crystal;
+	u8	thermal_value_dpk_store;
+	u8	thermal_value_dpk_track;
+	boolean	txpowertracking_in_progress;
+
+	boolean	is_reloadtxpowerindex;
+	u8	is_rf_pi_enable;
+	u32 	txpowertracking_callback_cnt; /* cosa add for debug */
+
+
+	/* ------------------------- Tx power Tracking ------------------------- */
+	u8	is_cck_in_ch14;
+	u8	CCK_index;
+	u8	OFDM_index[MAX_RF_PATH];
+	s8	power_index_offset[MAX_RF_PATH];
+	s8	delta_power_index[MAX_RF_PATH];
+	s8	delta_power_index_last[MAX_RF_PATH];
+	boolean is_tx_power_changed;
+	s8	xtal_offset;
+	s8	xtal_offset_last;
+
+	struct iqk_matrix_regs_setting iqk_matrix_reg_setting[IQK_MATRIX_SETTINGS_NUM];
+	u8	delta_lck;
+	s8  bb_swing_diff_2g, bb_swing_diff_5g; /* Unit: dB */
+	u8  delta_swing_table_idx_2g_cck_a_p[DELTA_SWINGIDX_SIZE];
+	u8  delta_swing_table_idx_2g_cck_a_n[DELTA_SWINGIDX_SIZE];
+	u8  delta_swing_table_idx_2g_cck_b_p[DELTA_SWINGIDX_SIZE];
+	u8  delta_swing_table_idx_2g_cck_b_n[DELTA_SWINGIDX_SIZE];
+	u8  delta_swing_table_idx_2g_cck_c_p[DELTA_SWINGIDX_SIZE];
+	u8  delta_swing_table_idx_2g_cck_c_n[DELTA_SWINGIDX_SIZE];
+	u8  delta_swing_table_idx_2g_cck_d_p[DELTA_SWINGIDX_SIZE];
+	u8  delta_swing_table_idx_2g_cck_d_n[DELTA_SWINGIDX_SIZE];
+	u8  delta_swing_table_idx_2ga_p[DELTA_SWINGIDX_SIZE];
+	u8  delta_swing_table_idx_2ga_n[DELTA_SWINGIDX_SIZE];
+	u8  delta_swing_table_idx_2gb_p[DELTA_SWINGIDX_SIZE];
+	u8  delta_swing_table_idx_2gb_n[DELTA_SWINGIDX_SIZE];
+	u8  delta_swing_table_idx_2gc_p[DELTA_SWINGIDX_SIZE];
+	u8  delta_swing_table_idx_2gc_n[DELTA_SWINGIDX_SIZE];
+	u8  delta_swing_table_idx_2gd_p[DELTA_SWINGIDX_SIZE];
+	u8  delta_swing_table_idx_2gd_n[DELTA_SWINGIDX_SIZE];
+	u8  delta_swing_table_idx_5ga_p[BAND_NUM][DELTA_SWINGIDX_SIZE];
+	u8  delta_swing_table_idx_5ga_n[BAND_NUM][DELTA_SWINGIDX_SIZE];
+	u8  delta_swing_table_idx_5gb_p[BAND_NUM][DELTA_SWINGIDX_SIZE];
+	u8  delta_swing_table_idx_5gb_n[BAND_NUM][DELTA_SWINGIDX_SIZE];
+	u8  delta_swing_table_idx_5gc_p[BAND_NUM][DELTA_SWINGIDX_SIZE];
+	u8  delta_swing_table_idx_5gc_n[BAND_NUM][DELTA_SWINGIDX_SIZE];
+	u8  delta_swing_table_idx_5gd_p[BAND_NUM][DELTA_SWINGIDX_SIZE];
+	u8  delta_swing_table_idx_5gd_n[BAND_NUM][DELTA_SWINGIDX_SIZE];
+	u8  delta_swing_tssi_table_2g_cck_a[DELTA_SWINTSSI_SIZE];
+	u8  delta_swing_tssi_table_2g_cck_b[DELTA_SWINTSSI_SIZE];
+	u8  delta_swing_tssi_table_2g_cck_c[DELTA_SWINTSSI_SIZE];
+	u8  delta_swing_tssi_table_2g_cck_d[DELTA_SWINTSSI_SIZE];
+	u8  delta_swing_tssi_table_2ga[DELTA_SWINTSSI_SIZE];
+	u8  delta_swing_tssi_table_2gb[DELTA_SWINTSSI_SIZE];
+	u8  delta_swing_tssi_table_2gc[DELTA_SWINTSSI_SIZE];
+	u8  delta_swing_tssi_table_2gd[DELTA_SWINTSSI_SIZE];
+	u8  delta_swing_tssi_table_5ga[BAND_NUM][DELTA_SWINTSSI_SIZE];
+	u8  delta_swing_tssi_table_5gb[BAND_NUM][DELTA_SWINTSSI_SIZE];
+	u8  delta_swing_tssi_table_5gc[BAND_NUM][DELTA_SWINTSSI_SIZE];
+	u8  delta_swing_tssi_table_5gd[BAND_NUM][DELTA_SWINTSSI_SIZE];
+	s8  delta_swing_table_xtal_p[DELTA_SWINGIDX_SIZE];
+	s8  delta_swing_table_xtal_n[DELTA_SWINGIDX_SIZE];
+	u8  delta_swing_table_idx_2ga_p_8188e[DELTA_SWINGIDX_SIZE];
+	u8  delta_swing_table_idx_2ga_n_8188e[DELTA_SWINGIDX_SIZE];
+
+	u8			bb_swing_idx_ofdm[MAX_RF_PATH];
+	u8			bb_swing_idx_ofdm_current;
+#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE | ODM_IOT))
+	u8			bb_swing_idx_ofdm_base[MAX_RF_PATH];
+#else
+	u8			bb_swing_idx_ofdm_base;
+#endif
+	boolean		default_bb_swing_index_flag;
+	boolean			bb_swing_flag_ofdm;
+	u8			bb_swing_idx_cck;
+	u8			bb_swing_idx_cck_current;
+	u8			bb_swing_idx_cck_base;
+	u8			default_ofdm_index;
+	u8			default_cck_index;
+	boolean			bb_swing_flag_cck;
+
+	s8			absolute_ofdm_swing_idx[MAX_RF_PATH];
+	s8			remnant_ofdm_swing_idx[MAX_RF_PATH];
+	s8			absolute_cck_swing_idx[MAX_RF_PATH];
+	s8			remnant_cck_swing_idx;
+	s8			modify_tx_agc_value;       /*Remnat compensate value at tx_agc */
+	boolean			modify_tx_agc_flag_path_a;
+	boolean			modify_tx_agc_flag_path_b;
+	boolean			modify_tx_agc_flag_path_c;
+	boolean			modify_tx_agc_flag_path_d;
+	boolean			modify_tx_agc_flag_path_a_cck;
+	boolean			modify_tx_agc_flag_path_b_cck;
+
+	s8			kfree_offset[MAX_RF_PATH];
+
+	/* -------------------------------------------------------------------- */
+
+	/* for IQK */
+	u32	regc04;
+	u32	reg874;
+	u32	regc08;
+	u32	regb68;
+	u32	regb6c;
+	u32	reg870;
+	u32	reg860;
+	u32	reg864;
+
+	boolean	is_iqk_initialized;
+	boolean is_lck_in_progress;
+	boolean	is_antenna_detected;
+	boolean	is_need_iqk;
+	boolean	is_iqk_in_progress;
+	boolean is_iqk_pa_off;
+	u8	delta_iqk;
+	u32	ADDA_backup[IQK_ADDA_REG_NUM];
+	u32	IQK_MAC_backup[IQK_MAC_REG_NUM];
+	u32	IQK_BB_backup_recover[9];
+	u32	IQK_BB_backup[IQK_BB_REG_NUM];
+	u32 	tx_iqc_8723b[2][3][2]; /* { {S1: 0xc94, 0xc80, 0xc4c} , {S0: 0xc9c, 0xc88, 0xc4c}} */
+	u32 	rx_iqc_8723b[2][2][2]; /* { {S1: 0xc14, 0xca0} ,           {S0: 0xc14, 0xca0}} */
+	u32	tx_iqc_8703b[3][2];	/* { {S1: 0xc94, 0xc80, 0xc4c} , {S0: 0xc9c, 0xc88, 0xc4c}}*/
+	u32	rx_iqc_8703b[2][2];	/* { {S1: 0xc14, 0xca0} ,           {S0: 0xc14, 0xca0}}*/
+	u32	tx_iqc_8723d[2][3][2];	/* { {S1: 0xc94, 0xc80, 0xc4c} , {S0: 0xc9c, 0xc88, 0xc4c}}*/
+	u32	rx_iqc_8723d[2][2][2];	/* { {S1: 0xc14, 0xca0} ,           {S0: 0xc14, 0xca0}}*/
+	/* JJ ADD 20161014 */
+	u32	tx_iqc_8710b[2][3][2];	/* { {S1: 0xc94, 0xc80, 0xc4c} , {S0: 0xc9c, 0xc88, 0xc4c}}*/
+	u32	rx_iqc_8710b[2][2][2];	/* { {S1: 0xc14, 0xca0} ,           {S0: 0xc14, 0xca0}}*/
+
+	u8	iqk_step;
+	u8	kcount;
+	u8	retry_count[4][2]; /* [4]: path ABCD, [2] TXK, RXK */
+	boolean	is_mp_mode;
+
+
+
+	/* <James> IQK time measurement */
+	u64	iqk_start_time;
+	u64	iqk_progressing_time;
+	u64	iqk_total_progressing_time;
+	u64 lck_progressing_time;
+
+	u32  lok_result;
+
+	/* for APK */
+	u32 	ap_koutput[2][2]; /* path A/B; output1_1a/output1_2a */
+	u8	is_ap_kdone;
+	u8	is_apk_thermal_meter_ignore;
+
+	/* DPK */
+	boolean is_dpk_fail;
+	u8	is_dp_done;
+	u8	is_dp_path_aok;
+	u8	is_dp_path_bok;
+
+	u32	tx_lok[2];
+	u32  dpk_tx_agc;
+	s32  dpk_gain;
+	u32  dpk_thermal[4];
+	s8 modify_tx_agc_value_ofdm;
+	s8 modify_tx_agc_value_cck;
+
+	/*Add by Yuchen for Kfree Phydm*/
+	u8			reg_rf_kfree_enable;	/*for registry*/
+	u8			rf_kfree_enable;		/*for efuse enable check*/
+
+};
+
+
+void
+odm_txpowertracking_check(
+	void		*dm_void
+);
+
+void
+odm_txpowertracking_check_ap(
+	void		*dm_void
+);
+
+void
+odm_txpowertracking_thermal_meter_init(
+	void		*dm_void
+);
+
+
+void
+odm_txpowertracking_check_mp(
+	void		*dm_void
+);
+
+
+void
+odm_txpowertracking_check_iot(
+	void		*dm_void
+);
+
+#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN))
+
+void
+odm_txpowertracking_callback_thermal_meter92c(
+	void	*adapter
+);
+
+void
+odm_txpowertracking_callback_rx_gain_thermal_meter92d(
+	void	*adapter
+);
+
+void
+odm_txpowertracking_callback_thermal_meter92d(
+	void	*adapter
+);
+
+void
+odm_txpowertracking_direct_call92c(
+	void		*adapter
+);
+
+void
+odm_txpowertracking_thermal_meter_check(
+	void		*adapter
+);
+
+#endif
+
+#endif	/*#ifndef __HALRF_POWER_TRACKING_H__*/
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/halrf/halrf_powertracking_win.c linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/halrf/halrf_powertracking_win.c
--- linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/halrf/halrf_powertracking_win.c	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/halrf/halrf_powertracking_win.c	2020-04-10 16:35:06.820660254 +0300
@@ -0,0 +1,859 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+
+/*============================================================	*/
+/* include files												*/
+/*============================================================	*/
+#include "mp_precomp.h"
+#include "phydm_precomp.h"
+
+/* ************************************************************
+ * Global var
+ * ************************************************************ */
+
+u32	ofdm_swing_table[OFDM_TABLE_SIZE] = {
+	0x7f8001fe,	/* 0, +6.0dB */
+	0x788001e2,	/* 1, +5.5dB */
+	0x71c001c7,	/* 2, +5.0dB */
+	0x6b8001ae,	/* 3, +4.5dB */
+	0x65400195,	/* 4, +4.0dB */
+	0x5fc0017f,	/* 5, +3.5dB */
+	0x5a400169,	/* 6, +3.0dB */
+	0x55400155,	/* 7, +2.5dB */
+	0x50800142,	/* 8, +2.0dB */
+	0x4c000130,	/* 9, +1.5dB */
+	0x47c0011f,	/* 10, +1.0dB */
+	0x43c0010f,	/* 11, +0.5dB */
+	0x40000100,	/* 12, +0dB */
+	0x3c8000f2,	/* 13, -0.5dB */
+	0x390000e4,	/* 14, -1.0dB */
+	0x35c000d7,	/* 15, -1.5dB */
+	0x32c000cb,	/* 16, -2.0dB */
+	0x300000c0,	/* 17, -2.5dB */
+	0x2d4000b5,	/* 18, -3.0dB */
+	0x2ac000ab,	/* 19, -3.5dB */
+	0x288000a2,	/* 20, -4.0dB */
+	0x26000098,	/* 21, -4.5dB */
+	0x24000090,	/* 22, -5.0dB */
+	0x22000088,	/* 23, -5.5dB */
+	0x20000080,	/* 24, -6.0dB */
+	0x1e400079,	/* 25, -6.5dB */
+	0x1c800072,	/* 26, -7.0dB */
+	0x1b00006c,	/* 27. -7.5dB */
+	0x19800066,	/* 28, -8.0dB */
+	0x18000060,	/* 29, -8.5dB */
+	0x16c0005b,	/* 30, -9.0dB */
+	0x15800056,	/* 31, -9.5dB */
+	0x14400051,	/* 32, -10.0dB */
+	0x1300004c,	/* 33, -10.5dB */
+	0x12000048,	/* 34, -11.0dB */
+	0x11000044,	/* 35, -11.5dB */
+	0x10000040,	/* 36, -12.0dB */
+};
+
+u8	cck_swing_table_ch1_ch13[CCK_TABLE_SIZE][8] = {
+	{0x36, 0x35, 0x2e, 0x25, 0x1c, 0x12, 0x09, 0x04},	/* 0, +0dB */
+	{0x33, 0x32, 0x2b, 0x23, 0x1a, 0x11, 0x08, 0x04},	/* 1, -0.5dB */
+	{0x30, 0x2f, 0x29, 0x21, 0x19, 0x10, 0x08, 0x03},	/* 2, -1.0dB */
+	{0x2d, 0x2d, 0x27, 0x1f, 0x18, 0x0f, 0x08, 0x03},	/* 3, -1.5dB */
+	{0x2b, 0x2a, 0x25, 0x1e, 0x16, 0x0e, 0x07, 0x03},	/* 4, -2.0dB */
+	{0x28, 0x28, 0x22, 0x1c, 0x15, 0x0d, 0x07, 0x03},	/* 5, -2.5dB */
+	{0x26, 0x25, 0x21, 0x1b, 0x14, 0x0d, 0x06, 0x03},	/* 6, -3.0dB */
+	{0x24, 0x23, 0x1f, 0x19, 0x13, 0x0c, 0x06, 0x03},	/* 7, -3.5dB */
+	{0x22, 0x21, 0x1d, 0x18, 0x11, 0x0b, 0x06, 0x02},	/* 8, -4.0dB */
+	{0x20, 0x20, 0x1b, 0x16, 0x11, 0x08, 0x05, 0x02},	/* 9, -4.5dB */
+	{0x1f, 0x1e, 0x1a, 0x15, 0x10, 0x0a, 0x05, 0x02},	/* 10, -5.0dB */
+	{0x1d, 0x1c, 0x18, 0x14, 0x0f, 0x0a, 0x05, 0x02},	/* 11, -5.5dB */
+	{0x1b, 0x1a, 0x17, 0x13, 0x0e, 0x09, 0x04, 0x02},	/* 12, -6.0dB <== default */
+	{0x1a, 0x19, 0x16, 0x12, 0x0d, 0x09, 0x04, 0x02},	/* 13, -6.5dB */
+	{0x18, 0x17, 0x15, 0x11, 0x0c, 0x08, 0x04, 0x02},	/* 14, -7.0dB */
+	{0x17, 0x16, 0x13, 0x10, 0x0c, 0x08, 0x04, 0x02},	/* 15, -7.5dB */
+	{0x16, 0x15, 0x12, 0x0f, 0x0b, 0x07, 0x04, 0x01},	/* 16, -8.0dB */
+	{0x14, 0x14, 0x11, 0x0e, 0x0b, 0x07, 0x03, 0x02},	/* 17, -8.5dB */
+	{0x13, 0x13, 0x10, 0x0d, 0x0a, 0x06, 0x03, 0x01},	/* 18, -9.0dB */
+	{0x12, 0x12, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01},	/* 19, -9.5dB */
+	{0x11, 0x11, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01},	/* 20, -10.0dB */
+	{0x10, 0x10, 0x0e, 0x0b, 0x08, 0x05, 0x03, 0x01},	/* 21, -10.5dB */
+	{0x0f, 0x0f, 0x0d, 0x0b, 0x08, 0x05, 0x03, 0x01},	/* 22, -11.0dB */
+	{0x0e, 0x0e, 0x0c, 0x0a, 0x08, 0x05, 0x02, 0x01},	/* 23, -11.5dB */
+	{0x0d, 0x0d, 0x0c, 0x0a, 0x07, 0x05, 0x02, 0x01},	/* 24, -12.0dB */
+	{0x0d, 0x0c, 0x0b, 0x09, 0x07, 0x04, 0x02, 0x01},	/* 25, -12.5dB */
+	{0x0c, 0x0c, 0x0a, 0x09, 0x06, 0x04, 0x02, 0x01},	/* 26, -13.0dB */
+	{0x0b, 0x0b, 0x0a, 0x08, 0x06, 0x04, 0x02, 0x01},	/* 27, -13.5dB */
+	{0x0b, 0x0a, 0x09, 0x08, 0x06, 0x04, 0x02, 0x01},	/* 28, -14.0dB */
+	{0x0a, 0x0a, 0x09, 0x07, 0x05, 0x03, 0x02, 0x01},	/* 29, -14.5dB */
+	{0x0a, 0x09, 0x08, 0x07, 0x05, 0x03, 0x02, 0x01},	/* 30, -15.0dB */
+	{0x09, 0x09, 0x08, 0x06, 0x05, 0x03, 0x01, 0x01},	/* 31, -15.5dB */
+	{0x09, 0x08, 0x07, 0x06, 0x04, 0x03, 0x01, 0x01}	/* 32, -16.0dB */
+};
+
+
+u8	cck_swing_table_ch14[CCK_TABLE_SIZE][8] = {
+	{0x36, 0x35, 0x2e, 0x1b, 0x00, 0x00, 0x00, 0x00},	/* 0, +0dB */
+	{0x33, 0x32, 0x2b, 0x19, 0x00, 0x00, 0x00, 0x00},	/* 1, -0.5dB */
+	{0x30, 0x2f, 0x29, 0x18, 0x00, 0x00, 0x00, 0x00},	/* 2, -1.0dB */
+	{0x2d, 0x2d, 0x17, 0x17, 0x00, 0x00, 0x00, 0x00},	/* 3, -1.5dB */
+	{0x2b, 0x2a, 0x25, 0x15, 0x00, 0x00, 0x00, 0x00},	/* 4, -2.0dB */
+	{0x28, 0x28, 0x24, 0x14, 0x00, 0x00, 0x00, 0x00},	/* 5, -2.5dB */
+	{0x26, 0x25, 0x21, 0x13, 0x00, 0x00, 0x00, 0x00},	/* 6, -3.0dB */
+	{0x24, 0x23, 0x1f, 0x12, 0x00, 0x00, 0x00, 0x00},	/* 7, -3.5dB */
+	{0x22, 0x21, 0x1d, 0x11, 0x00, 0x00, 0x00, 0x00},	/* 8, -4.0dB */
+	{0x20, 0x20, 0x1b, 0x10, 0x00, 0x00, 0x00, 0x00},	/* 9, -4.5dB */
+	{0x1f, 0x1e, 0x1a, 0x0f, 0x00, 0x00, 0x00, 0x00},	/* 10, -5.0dB */
+	{0x1d, 0x1c, 0x18, 0x0e, 0x00, 0x00, 0x00, 0x00},	/* 11, -5.5dB */
+	{0x1b, 0x1a, 0x17, 0x0e, 0x00, 0x00, 0x00, 0x00},	/* 12, -6.0dB  <== default */
+	{0x1a, 0x19, 0x16, 0x0d, 0x00, 0x00, 0x00, 0x00},	/* 13, -6.5dB */
+	{0x18, 0x17, 0x15, 0x0c, 0x00, 0x00, 0x00, 0x00},	/* 14, -7.0dB */
+	{0x17, 0x16, 0x13, 0x0b, 0x00, 0x00, 0x00, 0x00},	/* 15, -7.5dB */
+	{0x16, 0x15, 0x12, 0x0b, 0x00, 0x00, 0x00, 0x00},	/* 16, -8.0dB */
+	{0x14, 0x14, 0x11, 0x0a, 0x00, 0x00, 0x00, 0x00},	/* 17, -8.5dB */
+	{0x13, 0x13, 0x10, 0x0a, 0x00, 0x00, 0x00, 0x00},	/* 18, -9.0dB */
+	{0x12, 0x12, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00},	/* 19, -9.5dB */
+	{0x11, 0x11, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00},	/* 20, -10.0dB */
+	{0x10, 0x10, 0x0e, 0x08, 0x00, 0x00, 0x00, 0x00},	/* 21, -10.5dB */
+	{0x0f, 0x0f, 0x0d, 0x08, 0x00, 0x00, 0x00, 0x00},	/* 22, -11.0dB */
+	{0x0e, 0x0e, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00},	/* 23, -11.5dB */
+	{0x0d, 0x0d, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00},	/* 24, -12.0dB */
+	{0x0d, 0x0c, 0x0b, 0x06, 0x00, 0x00, 0x00, 0x00},	/* 25, -12.5dB */
+	{0x0c, 0x0c, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00},	/* 26, -13.0dB */
+	{0x0b, 0x0b, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00},	/* 27, -13.5dB */
+	{0x0b, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00},	/* 28, -14.0dB */
+	{0x0a, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00},	/* 29, -14.5dB */
+	{0x0a, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00},	/* 30, -15.0dB */
+	{0x09, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00},	/* 31, -15.5dB */
+	{0x09, 0x08, 0x07, 0x04, 0x00, 0x00, 0x00, 0x00}	/* 32, -16.0dB */
+};
+
+
+u32 ofdm_swing_table_new[OFDM_TABLE_SIZE] = {
+	0x0b40002d, /* 0,  -15.0dB */
+	0x0c000030, /* 1,  -14.5dB */
+	0x0cc00033, /* 2,  -14.0dB */
+	0x0d800036, /* 3,  -13.5dB */
+	0x0e400039, /* 4,  -13.0dB */
+	0x0f00003c, /* 5,  -12.5dB */
+	0x10000040, /* 6,  -12.0dB */
+	0x11000044, /* 7,  -11.5dB */
+	0x12000048, /* 8,  -11.0dB */
+	0x1300004c, /* 9,  -10.5dB */
+	0x14400051, /* 10, -10.0dB */
+	0x15800056, /* 11, -9.5dB */
+	0x16c0005b, /* 12, -9.0dB */
+	0x18000060, /* 13, -8.5dB */
+	0x19800066, /* 14, -8.0dB */
+	0x1b00006c, /* 15, -7.5dB */
+	0x1c800072, /* 16, -7.0dB */
+	0x1e400079, /* 17, -6.5dB */
+	0x20000080, /* 18, -6.0dB */
+	0x22000088, /* 19, -5.5dB */
+	0x24000090, /* 20, -5.0dB */
+	0x26000098, /* 21, -4.5dB */
+	0x288000a2, /* 22, -4.0dB */
+	0x2ac000ab, /* 23, -3.5dB */
+	0x2d4000b5, /* 24, -3.0dB */
+	0x300000c0, /* 25, -2.5dB */
+	0x32c000cb, /* 26, -2.0dB */
+	0x35c000d7, /* 27, -1.5dB */
+	0x390000e4, /* 28, -1.0dB */
+	0x3c8000f2, /* 29, -0.5dB */
+	0x40000100, /* 30, +0dB */
+	0x43c0010f, /* 31, +0.5dB */
+	0x47c0011f, /* 32, +1.0dB */
+	0x4c000130, /* 33, +1.5dB */
+	0x50800142, /* 34, +2.0dB */
+	0x55400155, /* 35, +2.5dB */
+	0x5a400169, /* 36, +3.0dB */
+	0x5fc0017f, /* 37, +3.5dB */
+	0x65400195, /* 38, +4.0dB */
+	0x6b8001ae, /* 39, +4.5dB */
+	0x71c001c7, /* 40, +5.0dB */
+	0x788001e2, /* 41, +5.5dB */
+	0x7f8001fe  /* 42, +6.0dB */
+};
+
+
+u8 cck_swing_table_ch1_ch14_88f[CCK_TABLE_SIZE_88F][16] = {
+	{0x44, 0x42, 0x3C, 0x33, 0x28, 0x1C, 0x13, 0x0B, 0x05, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-16dB*/
+	{0x48, 0x46, 0x3F, 0x36, 0x2A, 0x1E, 0x14, 0x0B, 0x05, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-15.5dB*/
+	{0x4D, 0x4A, 0x43, 0x39, 0x2C, 0x20, 0x15, 0x0C, 0x06, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-15dB*/
+	{0x51, 0x4F, 0x47, 0x3C, 0x2F, 0x22, 0x16, 0x0D, 0x06, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-14.5dB*/
+	{0x56, 0x53, 0x4B, 0x40, 0x32, 0x24, 0x17, 0x0E, 0x06, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-14dB*/
+	{0x5B, 0x58, 0x50, 0x43, 0x35, 0x26, 0x19, 0x0E, 0x07, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-13.5dB*/
+	{0x60, 0x5D, 0x54, 0x47, 0x38, 0x28, 0x1A, 0x0F, 0x07, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-13dB*/
+	{0x66, 0x63, 0x59, 0x4C, 0x3B, 0x2B, 0x1C, 0x10, 0x08, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-12.5dB*/
+	{0x6C, 0x69, 0x5F, 0x50, 0x3F, 0x2D, 0x1E, 0x11, 0x08, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-12dB*/
+	{0x73, 0x6F, 0x64, 0x55, 0x42, 0x30, 0x1F, 0x12, 0x08, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-11.5dB*/
+	{0x79, 0x76, 0x6A, 0x5A, 0x46, 0x33, 0x21, 0x13, 0x09, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-11dB*/
+	{0x81, 0x7C, 0x71, 0x5F, 0x4A, 0x36, 0x23, 0x14, 0x0A, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-10.5dB*/
+	{0x88, 0x84, 0x77, 0x65, 0x4F, 0x39, 0x25, 0x15, 0x0A, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-10dB*/
+	{0x90, 0x8C, 0x7E, 0x6B, 0x54, 0x3C, 0x27, 0x17, 0x0B, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-9.5dB*/
+	{0x99, 0x94, 0x86, 0x71, 0x58, 0x40, 0x2A, 0x18, 0x0B, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-9dB*/
+	{0xA2, 0x9D, 0x8E, 0x78, 0x5E, 0x43, 0x2C, 0x19, 0x0C, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-8.5dB*/
+	{0xAC, 0xA6, 0x96, 0x7F, 0x63, 0x47, 0x2F, 0x1B, 0x0D, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-8dB*/
+	{0xB6, 0xB0, 0x9F, 0x87, 0x69, 0x4C, 0x32, 0x1D, 0x0D, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-7.5dB*/
+	{0xC1, 0xBA, 0xA8, 0x8F, 0x6F, 0x50, 0x35, 0x1E, 0x0E, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-7dB*/
+	{0xCC, 0xC5, 0xB2, 0x97, 0x76, 0x55, 0x38, 0x20, 0x0F, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-6.5dB*/
+	{0xD8, 0xD1, 0xBD, 0xA0, 0x7D, 0x5A, 0x3B, 0x22, 0x10, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}     /*-6dB*/
+};
+
+
+u8 cck_swing_table_ch1_ch13_88f[CCK_TABLE_SIZE_88F][16] = {
+	{0x44, 0x42, 0x3C, 0x33, 0x28, 0x1C, 0x13, 0x0B, 0x05, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-16dB*/
+	{0x48, 0x46, 0x3F, 0x36, 0x2A, 0x1E, 0x14, 0x0B, 0x05, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-15.5dB*/
+	{0x4D, 0x4A, 0x43, 0x39, 0x2C, 0x20, 0x15, 0x0C, 0x06, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-15dB*/
+	{0x51, 0x4F, 0x47, 0x3C, 0x2F, 0x22, 0x16, 0x0D, 0x06, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-14.5dB*/
+	{0x56, 0x53, 0x4B, 0x40, 0x32, 0x24, 0x17, 0x0E, 0x06, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-14dB*/
+	{0x5B, 0x58, 0x50, 0x43, 0x35, 0x26, 0x19, 0x0E, 0x07, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-13.5dB*/
+	{0x60, 0x5D, 0x54, 0x47, 0x38, 0x28, 0x1A, 0x0F, 0x07, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-13dB*/
+	{0x66, 0x63, 0x59, 0x4C, 0x3B, 0x2B, 0x1C, 0x10, 0x08, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-12.5dB*/
+	{0x6C, 0x69, 0x5F, 0x50, 0x3F, 0x2D, 0x1E, 0x11, 0x08, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-12dB*/
+	{0x73, 0x6F, 0x64, 0x55, 0x42, 0x30, 0x1F, 0x12, 0x08, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-11.5dB*/
+	{0x79, 0x76, 0x6A, 0x5A, 0x46, 0x33, 0x21, 0x13, 0x09, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-11dB*/
+	{0x81, 0x7C, 0x71, 0x5F, 0x4A, 0x36, 0x23, 0x14, 0x0A, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-10.5dB*/
+	{0x88, 0x84, 0x77, 0x65, 0x4F, 0x39, 0x25, 0x15, 0x0A, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-10dB*/
+	{0x90, 0x8C, 0x7E, 0x6B, 0x54, 0x3C, 0x27, 0x17, 0x0B, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-9.5dB*/
+	{0x99, 0x94, 0x86, 0x71, 0x58, 0x40, 0x2A, 0x18, 0x0B, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-9dB*/
+	{0xA2, 0x9D, 0x8E, 0x78, 0x5E, 0x43, 0x2C, 0x19, 0x0C, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-8.5dB*/
+	{0xAC, 0xA6, 0x96, 0x7F, 0x63, 0x47, 0x2F, 0x1B, 0x0D, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-8dB*/
+	{0xB6, 0xB0, 0x9F, 0x87, 0x69, 0x4C, 0x32, 0x1D, 0x0D, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-7.5dB*/
+	{0xC1, 0xBA, 0xA8, 0x8F, 0x6F, 0x50, 0x35, 0x1E, 0x0E, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-7dB*/
+	{0xCC, 0xC5, 0xB2, 0x97, 0x76, 0x55, 0x38, 0x20, 0x0F, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-6.5dB*/
+	{0xD8, 0xD1, 0xBD, 0xA0, 0x7D, 0x5A, 0x3B, 0x22, 0x10, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}     /*-6dB*/
+};
+
+
+u8 cck_swing_table_ch14_88f[CCK_TABLE_SIZE_88F][16] = {
+	{0x44,	 0x42, 0x3C, 0x28, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-16dB*/
+	{0x48, 0x46, 0x3F, 0x2A, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-15.5dB*/
+	{0x4D, 0x4A, 0x43, 0x2C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-15dB*/
+	{0x51, 0x4F, 0x47, 0x2F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},	    /*-14.5dB*/
+	{0x56, 0x53, 0x4B, 0x32, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-14dB*/
+	{0x5B, 0x58, 0x50, 0x35, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-13.5dB*/
+	{0x60, 0x5D, 0x54, 0x38, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-13dB*/
+	{0x66, 0x63, 0x59, 0x3B, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-12.5dB*/
+	{0x6C, 0x69, 0x5F, 0x3F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-12dB*/
+	{0x73, 0x6F, 0x64, 0x42, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-11.5dB*/
+	{0x79, 0x76, 0x6A, 0x46, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-11dB*/
+	{0x81, 0x7C, 0x71, 0x4A, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-10.5dB*/
+	{0x88, 0x84, 0x77, 0x4F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-10dB*/
+	{0x90, 0x8C, 0x7E, 0x54, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-9.5dB*/
+	{0x99, 0x94, 0x86, 0x58, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-9dB*/
+	{0xA2, 0x9D, 0x8E, 0x5E, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-8.5dB*/
+	{0xAC, 0xA6, 0x96, 0x63, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-8dB*/
+	{0xB6, 0xB0, 0x9F, 0x69, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-7.5dB*/
+	{0xC1, 0xBA, 0xA8, 0x6F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-7dB*/
+	{0xCC, 0xC5, 0xB2, 0x76, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-6.5dB*/
+	{0xD8, 0xD1, 0xBD, 0x7D, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}     /*-6dB*/
+};
+
+
+u8 cck_swing_table_ch1_ch13_new[CCK_TABLE_SIZE][8] = {
+	{0x09, 0x08, 0x07, 0x06, 0x04, 0x03, 0x01, 0x01},	/* 0, -16.0dB */
+	{0x09, 0x09, 0x08, 0x06, 0x05, 0x03, 0x01, 0x01},	/* 1, -15.5dB */
+	{0x0a, 0x09, 0x08, 0x07, 0x05, 0x03, 0x02, 0x01},	/* 2, -15.0dB */
+	{0x0a, 0x0a, 0x09, 0x07, 0x05, 0x03, 0x02, 0x01},	/* 3, -14.5dB */
+	{0x0b, 0x0a, 0x09, 0x08, 0x06, 0x04, 0x02, 0x01},	/* 4, -14.0dB */
+	{0x0b, 0x0b, 0x0a, 0x08, 0x06, 0x04, 0x02, 0x01},	/* 5, -13.5dB */
+	{0x0c, 0x0c, 0x0a, 0x09, 0x06, 0x04, 0x02, 0x01},	/* 6, -13.0dB */
+	{0x0d, 0x0c, 0x0b, 0x09, 0x07, 0x04, 0x02, 0x01},	/* 7, -12.5dB */
+	{0x0d, 0x0d, 0x0c, 0x0a, 0x07, 0x05, 0x02, 0x01},	/* 8, -12.0dB */
+	{0x0e, 0x0e, 0x0c, 0x0a, 0x08, 0x05, 0x02, 0x01},	/* 9, -11.5dB */
+	{0x0f, 0x0f, 0x0d, 0x0b, 0x08, 0x05, 0x03, 0x01},	/* 10, -11.0dB */
+	{0x10, 0x10, 0x0e, 0x0b, 0x08, 0x05, 0x03, 0x01},	/* 11, -10.5dB */
+	{0x11, 0x11, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01},	/* 12, -10.0dB */
+	{0x12, 0x12, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01},	/* 13, -9.5dB */
+	{0x13, 0x13, 0x10, 0x0d, 0x0a, 0x06, 0x03, 0x01},	/* 14, -9.0dB */
+	{0x14, 0x14, 0x11, 0x0e, 0x0b, 0x07, 0x03, 0x02},	/* 15, -8.5dB */
+	{0x16, 0x15, 0x12, 0x0f, 0x0b, 0x07, 0x04, 0x01},	/* 16, -8.0dB */
+	{0x17, 0x16, 0x13, 0x10, 0x0c, 0x08, 0x04, 0x02},	/* 17, -7.5dB */
+	{0x18, 0x17, 0x15, 0x11, 0x0c, 0x08, 0x04, 0x02},	/* 18, -7.0dB */
+	{0x1a, 0x19, 0x16, 0x12, 0x0d, 0x09, 0x04, 0x02},	/* 19, -6.5dB */
+	{0x1b, 0x1a, 0x17, 0x13, 0x0e, 0x09, 0x04, 0x02},	/* 20, -6.0dB */
+	{0x1d, 0x1c, 0x18, 0x14, 0x0f, 0x0a, 0x05, 0x02},	/* 21, -5.5dB */
+	{0x1f, 0x1e, 0x1a, 0x15, 0x10, 0x0a, 0x05, 0x02},	/* 22, -5.0dB */
+	{0x20, 0x20, 0x1b, 0x16, 0x11, 0x08, 0x05, 0x02},	/* 23, -4.5dB */
+	{0x22, 0x21, 0x1d, 0x18, 0x11, 0x0b, 0x06, 0x02},	/* 24, -4.0dB */
+	{0x24, 0x23, 0x1f, 0x19, 0x13, 0x0c, 0x06, 0x03},	/* 25, -3.5dB */
+	{0x26, 0x25, 0x21, 0x1b, 0x14, 0x0d, 0x06, 0x03},	/* 26, -3.0dB */
+	{0x28, 0x28, 0x22, 0x1c, 0x15, 0x0d, 0x07, 0x03},	/* 27, -2.5dB */
+	{0x2b, 0x2a, 0x25, 0x1e, 0x16, 0x0e, 0x07, 0x03},	/* 28, -2.0dB */
+	{0x2d, 0x2d, 0x27, 0x1f, 0x18, 0x0f, 0x08, 0x03},	/* 29, -1.5dB */
+	{0x30, 0x2f, 0x29, 0x21, 0x19, 0x10, 0x08, 0x03},	/* 30, -1.0dB */
+	{0x33, 0x32, 0x2b, 0x23, 0x1a, 0x11, 0x08, 0x04},	/* 31, -0.5dB */
+	{0x36, 0x35, 0x2e, 0x25, 0x1c, 0x12, 0x09, 0x04}	/* 32, +0dB */
+};
+
+
+u8 cck_swing_table_ch14_new[CCK_TABLE_SIZE][8] = {
+	{0x09, 0x08, 0x07, 0x04, 0x00, 0x00, 0x00, 0x00},	/* 0, -16.0dB */
+	{0x09, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00},	/* 1, -15.5dB */
+	{0x0a, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00},	/* 2, -15.0dB */
+	{0x0a, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00},	/* 3, -14.5dB */
+	{0x0b, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00},	/* 4, -14.0dB */
+	{0x0b, 0x0b, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00},	/* 5, -13.5dB */
+	{0x0c, 0x0c, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00},	/* 6, -13.0dB */
+	{0x0d, 0x0c, 0x0b, 0x06, 0x00, 0x00, 0x00, 0x00},	/* 7, -12.5dB */
+	{0x0d, 0x0d, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00},	/* 8, -12.0dB */
+	{0x0e, 0x0e, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00},	/* 9, -11.5dB */
+	{0x0f, 0x0f, 0x0d, 0x08, 0x00, 0x00, 0x00, 0x00},	/* 10, -11.0dB */
+	{0x10, 0x10, 0x0e, 0x08, 0x00, 0x00, 0x00, 0x00},	/* 11, -10.5dB */
+	{0x11, 0x11, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00},	/* 12, -10.0dB */
+	{0x12, 0x12, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00},	/* 13, -9.5dB */
+	{0x13, 0x13, 0x10, 0x0a, 0x00, 0x00, 0x00, 0x00},	/* 14, -9.0dB */
+	{0x14, 0x14, 0x11, 0x0a, 0x00, 0x00, 0x00, 0x00},	/* 15, -8.5dB */
+	{0x16, 0x15, 0x12, 0x0b, 0x00, 0x00, 0x00, 0x00},	/* 16, -8.0dB */
+	{0x17, 0x16, 0x13, 0x0b, 0x00, 0x00, 0x00, 0x00},	/* 17, -7.5dB */
+	{0x18, 0x17, 0x15, 0x0c, 0x00, 0x00, 0x00, 0x00},	/* 18, -7.0dB */
+	{0x1a, 0x19, 0x16, 0x0d, 0x00, 0x00, 0x00, 0x00},	/* 19, -6.5dB */
+	{0x1b, 0x1a, 0x17, 0x0e, 0x00, 0x00, 0x00, 0x00},	/* 20, -6.0dB */
+	{0x1d, 0x1c, 0x18, 0x0e, 0x00, 0x00, 0x00, 0x00},	/* 21, -5.5dB */
+	{0x1f, 0x1e, 0x1a, 0x0f, 0x00, 0x00, 0x00, 0x00},	/* 22, -5.0dB */
+	{0x20, 0x20, 0x1b, 0x10, 0x00, 0x00, 0x00, 0x00},	/* 23, -4.5dB */
+	{0x22, 0x21, 0x1d, 0x11, 0x00, 0x00, 0x00, 0x00},	/* 24, -4.0dB */
+	{0x24, 0x23, 0x1f, 0x12, 0x00, 0x00, 0x00, 0x00},	/* 25, -3.5dB */
+	{0x26, 0x25, 0x21, 0x13, 0x00, 0x00, 0x00, 0x00},	/* 26, -3.0dB */
+	{0x28, 0x28, 0x24, 0x14, 0x00, 0x00, 0x00, 0x00},	/* 27, -2.5dB */
+	{0x2b, 0x2a, 0x25, 0x15, 0x00, 0x00, 0x00, 0x00},	/* 28, -2.0dB */
+	{0x2d, 0x2d, 0x17, 0x17, 0x00, 0x00, 0x00, 0x00},	/* 29, -1.5dB */
+	{0x30, 0x2f, 0x29, 0x18, 0x00, 0x00, 0x00, 0x00},	/* 30, -1.0dB */
+	{0x33, 0x32, 0x2b, 0x19, 0x00, 0x00, 0x00, 0x00},	/* 31, -0.5dB */
+	{0x36, 0x35, 0x2e, 0x1b, 0x00, 0x00, 0x00, 0x00}	/* 32, +0dB */
+};
+u32 cck_swing_table_ch1_ch14_8723d[CCK_TABLE_SIZE_8723D] = {
+	0x0CD,
+	0x0D9,
+	0x0E6,
+	0x0F3,
+	0x102,
+	0x111,
+	0x121,
+	0x132,
+	0x144,
+	0x158,
+	0x16C,
+	0x182,
+	0x198,
+	0x1B1,
+	0x1CA,
+	0x1E5,
+	0x202,
+	0x221,
+	0x241,
+	0x263,
+	0x287,
+	0x2AE,
+	0x2D6,
+	0x301,
+	0x32F,
+	0x35F,
+	0x392,
+	0x3C9,
+	0x402,
+	0x43F,
+	0x47F,
+	0x4C3,
+	0x50C,
+	0x558,
+	0x5A9,
+	0x5FF,
+	0x65A,
+	0x6BA,
+	0x720,
+	0x78C,
+	0x7FF,
+};
+/* JJ ADD 20161014 */
+u32 cck_swing_table_ch1_ch14_8710b[CCK_TABLE_SIZE_8710B] = {
+	0x0CD,			 /*0 ,    -20dB*/
+	0x0D9,
+	0x0E6,
+	0x0F3,
+	0x102,
+	0x111,
+	0x121,
+	0x132,
+	0x144,
+	0x158,
+	0x16C,
+	0x182,
+	0x198,
+	0x1B1,
+	0x1CA,
+	0x1E5,
+	0x202,
+	0x221,
+	0x241,
+	0x263,		/*19*/
+	0x287,		/*20*/
+	0x2AE,		/*21*/
+	0x2D6,		/*22*/
+	0x301,		/*23*/
+	0x32F,		/*24*/
+	0x35F,		/*25*/
+	0x392,		/*26*/
+	0x3C9,		/*27*/
+	0x402,		/*28*/
+	0x43F,		/*29*/
+	0x47F,		/*30*/
+	0x4C3,		/*31*/
+	0x50C,		/*32*/
+	0x558,		/*33*/
+	0x5A9,		/*34*/
+	0x5FF,		/*35*/
+	0x65A,		/*36*/
+	0x6BA,
+	0x720,
+	0x78C,
+	0x7FF,
+};
+
+/* Winnita ADD 20170828 PathA 0xAB4[10:0],PathB 0xAB4[21:11]*/
+u32 cck_swing_table_ch1_ch14_8192f[CCK_TABLE_SIZE_8192F] = {
+	0x0CD,			 /*0 ,    -20dB*/
+	0x0D9,
+	0x0E6,
+	0x0F3,
+	0x102,
+	0x111,
+	0x121,
+	0x132,
+	0x144,
+	0x158,
+	0x16C,
+	0x182,
+	0x198,
+	0x1B1,
+	0x1CA,
+	0x1E5,
+	0x202,
+	0x221,
+	0x241,
+	0x263,		/*19*/
+	0x287,		/*20*/
+	0x2AE,		/*21*/
+	0x2D6,		/*22*/
+	0x301,		/*23*/
+	0x32F,		/*24*/
+	0x35F,		/*25*/
+	0x392,		/*26*/
+	0x3C9,		/*27*/
+	0x402,		/*28*/
+	0x43F,		/*29*/
+	0x47F,		/*30*/
+	0x4C3,		/*31*/
+	0x50C,		/*32*/
+	0x558,		/*33*/
+	0x5A9,		/*34*/
+	0x5FF,		/*35*/
+	0x65A,		/*36*/
+	0x6BA,
+	0x720,
+	0x78C,
+	0x7FF,
+};
+
+u32 tx_scaling_table_jaguar[TXSCALE_TABLE_SIZE] = {
+	0x081, /* 0,  -12.0dB */
+	0x088, /* 1,  -11.5dB */
+	0x090, /* 2,  -11.0dB */
+	0x099, /* 3,  -10.5dB */
+	0x0A2, /* 4,  -10.0dB */
+	0x0AC, /* 5,  -9.5dB */
+	0x0B6, /* 6,  -9.0dB */
+	0x0C0, /* 7,  -8.5dB */
+	0x0CC, /* 8,  -8.0dB */
+	0x0D8, /* 9,  -7.5dB */
+	0x0E5, /* 10, -7.0dB */
+	0x0F2, /* 11, -6.5dB */
+	0x101, /* 12, -6.0dB */
+	0x110, /* 13, -5.5dB */
+	0x120, /* 14, -5.0dB */
+	0x131, /* 15, -4.5dB */
+	0x143, /* 16, -4.0dB */
+	0x156, /* 17, -3.5dB */
+	0x16A, /* 18, -3.0dB */
+	0x180, /* 19, -2.5dB */
+	0x197, /* 20, -2.0dB */
+	0x1AF, /* 21, -1.5dB */
+	0x1C8, /* 22, -1.0dB */
+	0x1E3, /* 23, -0.5dB */
+	0x200, /* 24, +0  dB */
+	0x21E, /* 25, +0.5dB */
+	0x23E, /* 26, +1.0dB */
+	0x261, /* 27, +1.5dB */
+	0x285, /* 28, +2.0dB */
+	0x2AB, /* 29, +2.5dB */
+	0x2D3, /* 30, +3.0dB */
+	0x2FE, /* 31, +3.5dB */
+	0x32B, /* 32, +4.0dB */
+	0x35C, /* 33, +4.5dB */
+	0x38E, /* 34, +5.0dB */
+	0x3C4, /* 35, +5.5dB */
+	0x3FE  /* 36, +6.0dB */
+};
+
+void
+odm_txpowertracking_init(
+	void		*dm_void
+)
+{
+	struct dm_struct		*dm = (struct dm_struct *)dm_void;
+#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
+	if (!(dm->support_ic_type & (ODM_RTL8814A | ODM_IC_11N_SERIES | ODM_RTL8822B)))
+		return;
+#endif
+
+	odm_txpowertracking_thermal_meter_init(dm);
+}
+
+u8
+get_swing_index(
+	void		*dm_void
+)
+{
+	struct dm_struct		*dm = (struct dm_struct *)dm_void;
+	void		*adapter = dm->adapter;
+	HAL_DATA_TYPE	*hal_data = GET_HAL_DATA(((PADAPTER)adapter));
+	u8			i = 0;
+	u32			bb_swing, table_value;
+
+	if (dm->support_ic_type == ODM_RTL8188E || dm->support_ic_type == ODM_RTL8723B ||
+	    dm->support_ic_type == ODM_RTL8192E || dm->support_ic_type == ODM_RTL8188F || 
+	    dm->support_ic_type == ODM_RTL8703B || dm->support_ic_type == ODM_RTL8723D || 
+	    dm->support_ic_type == ODM_RTL8192F || dm->support_ic_type == ODM_RTL8710B ||
+	    dm->support_ic_type == ODM_RTL8821) {
+		bb_swing = odm_get_bb_reg(dm, REG_OFDM_0_XA_TX_IQ_IMBALANCE, 0xFFC00000);
+
+		for (i = 0; i < OFDM_TABLE_SIZE; i++) {
+			table_value = ofdm_swing_table_new[i];
+
+			if (table_value >= 0x100000)
+				table_value >>= 22;
+			if (bb_swing == table_value)
+				break;
+		}
+	} else {
+		bb_swing = PHY_GetTxBBSwing_8812A(adapter, hal_data->CurrentBandType, RF_PATH_A);
+
+		for (i = 0; i < TXSCALE_TABLE_SIZE; i++) {
+			table_value = tx_scaling_table_jaguar[i];
+
+			if (bb_swing == table_value)
+				break;
+		}
+	}
+
+	return i;
+}
+
+u8
+get_cck_swing_index(
+	void		*dm_void
+)
+{
+	struct dm_struct		*dm = (struct dm_struct *)dm_void;
+
+	u8			i = 0;
+	u32			bb_cck_swing;
+
+	if (dm->support_ic_type == ODM_RTL8188E || dm->support_ic_type == ODM_RTL8723B ||
+	    dm->support_ic_type == ODM_RTL8192E) {
+		bb_cck_swing = odm_read_1byte(dm, 0xa22);
+
+		for (i = 0; i < CCK_TABLE_SIZE; i++) {
+			if (bb_cck_swing == cck_swing_table_ch1_ch13_new[i][0])
+				break;
+		}
+	} else if (dm->support_ic_type == ODM_RTL8703B) {
+		bb_cck_swing = odm_read_1byte(dm, 0xa22);
+
+		for (i = 0; i < CCK_TABLE_SIZE_88F; i++) {
+			if (bb_cck_swing == cck_swing_table_ch1_ch14_88f[i][0])
+				break;
+		}
+	}
+
+	return i;
+}
+
+
+void
+odm_txpowertracking_thermal_meter_init(
+	void		*dm_void
+)
+{
+	struct dm_struct		*dm = (struct dm_struct *)dm_void;
+	u8 default_swing_index = get_swing_index(dm);
+	u8 default_cck_swing_index = get_cck_swing_index(dm);
+	struct dm_rf_calibration_struct	*cali_info = &(dm->rf_calibrate_info);
+
+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
+	void		*adapter = dm->adapter;
+	HAL_DATA_TYPE	*hal_data = GET_HAL_DATA(((PADAPTER)adapter));
+	u8			p = 0;
+
+	if (*(dm->mp_mode) == false)
+		cali_info->txpowertrack_control = true;
+#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
+#ifdef CONFIG_RTL8188E
+	{
+		cali_info->is_txpowertracking = true;
+		cali_info->tx_powercount = 0;
+		cali_info->is_txpowertracking_init = false;
+
+		if (*(dm->mp_mode) == false)
+			cali_info->txpowertrack_control = true;
+
+		MSG_8192C("dm txpowertrack_control = %d\n", cali_info->txpowertrack_control);
+	}
+#else
+	{
+		void		*adapter = dm->adapter;
+		HAL_DATA_TYPE	*hal_data = GET_HAL_DATA(((PADAPTER)adapter));
+		struct dm_priv	*pdmpriv = &hal_data->dmpriv;
+
+		pdmpriv->is_txpowertracking = true;
+		pdmpriv->tx_powercount = 0;
+		pdmpriv->is_txpowertracking_init = false;
+
+		if (*(dm->mp_mode) == false)
+			pdmpriv->txpowertrack_control = true;
+
+		MSG_8192C("pdmpriv->txpowertrack_control = %d\n", pdmpriv->txpowertrack_control);
+
+	}
+#endif
+#elif (DM_ODM_SUPPORT_TYPE & (ODM_AP))
+#ifdef RTL8188E_SUPPORT
+	{
+		cali_info->is_txpowertracking = true;
+		cali_info->tx_powercount = 0;
+		cali_info->is_txpowertracking_init = false;
+		cali_info->txpowertrack_control = true;
+	}
+#endif
+#endif
+
+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
+#if (MP_DRIVER == 1)
+	cali_info->txpowertrack_control = false;
+#else
+	cali_info->txpowertrack_control = true;
+#endif
+#else
+	cali_info->txpowertrack_control = true;
+#endif
+
+	cali_info->thermal_value		= hal_data->eeprom_thermal_meter;
+	cali_info->thermal_value_iqk	= hal_data->eeprom_thermal_meter;
+	cali_info->thermal_value_lck	= hal_data->eeprom_thermal_meter;
+
+	if (cali_info->default_bb_swing_index_flag != true) {
+		/*The index of "0 dB" in SwingTable.*/
+		if (dm->support_ic_type == ODM_RTL8188E || dm->support_ic_type == ODM_RTL8723B ||
+		    dm->support_ic_type == ODM_RTL8192E || dm->support_ic_type == ODM_RTL8703B ||
+		    dm->support_ic_type == ODM_RTL8821) {
+			cali_info->default_ofdm_index = (default_swing_index >= OFDM_TABLE_SIZE) ? 30 : default_swing_index;
+			cali_info->default_cck_index = (default_cck_swing_index >= CCK_TABLE_SIZE) ? 20 : default_cck_swing_index;
+		} else if (dm->support_ic_type == ODM_RTL8188F) {          /*add by Mingzhi.Guo  2015-03-23*/
+			cali_info->default_ofdm_index = 28;							/*OFDM: -1dB*/
+			cali_info->default_cck_index = 20;							/*CCK:-6dB*/
+		} else if (dm->support_ic_type == ODM_RTL8723D) {			 /*add by zhaohe  2015-10-27*/
+			cali_info->default_ofdm_index = 28;						 	   /*OFDM: -1dB*/
+			cali_info->default_cck_index = 28;							/*CCK:   -6dB*/
+			/* JJ ADD 20161014 */
+		} else if (dm->support_ic_type == ODM_RTL8710B) {			
+			cali_info->default_ofdm_index = 28;					/*OFDM: -1dB*/
+			cali_info->default_cck_index = 28;					/*CCK:   -6dB*/
+		/*Winnita add 20170828*/
+		} else if (dm->support_ic_type == ODM_RTL8192F) {			
+			cali_info->default_ofdm_index = 30;					/*OFDM: 0dB*/
+			cali_info->default_cck_index = 28;					/*CCK:   -6dB*/
+		} else {
+			cali_info->default_ofdm_index = (default_swing_index >= TXSCALE_TABLE_SIZE) ? 24 : default_swing_index;
+			cali_info->default_cck_index = 24;
+		}
+		cali_info->default_bb_swing_index_flag = true;
+	}
+
+	cali_info->bb_swing_idx_cck_base = cali_info->default_cck_index;
+	cali_info->CCK_index = cali_info->default_cck_index;
+
+	for (p = RF_PATH_A; p < MAX_RF_PATH; ++p) {
+		cali_info->bb_swing_idx_ofdm_base[p] = cali_info->default_ofdm_index;
+		cali_info->OFDM_index[p] = cali_info->default_ofdm_index;
+		cali_info->delta_power_index[p] = 0;
+		cali_info->delta_power_index_last[p] = 0;
+		cali_info->power_index_offset[p] = 0;
+		cali_info->kfree_offset[p] = 0;
+	}
+	cali_info->modify_tx_agc_value_ofdm = 0;
+	cali_info->modify_tx_agc_value_cck = 0;
+	cali_info->tm_trigger = 0;
+}
+
+
+void
+odm_txpowertracking_check(
+	void		*dm_void
+)
+{
+
+#if 0
+	/* 2011/09/29 MH In HW integration first stage, we provide 4 different handle to operate */
+	/*  at the same time. In the stage2/3, we need to prive universal interface and merge all */
+	/* HW dynamic mechanism. */
+#endif
+
+	struct dm_struct		*dm = (struct dm_struct *)dm_void;
+	switch	(dm->support_platform) {
+	case	ODM_WIN:
+		odm_txpowertracking_check_mp(dm);
+		break;
+
+	case	ODM_CE:
+		odm_txpowertracking_check_ce(dm);
+		break;
+
+	case	ODM_AP:
+		odm_txpowertracking_check_ap(dm);
+		break;
+
+	default:
+		break;
+	}
+
+}
+
+void
+odm_txpowertracking_check_ce(
+	void		*dm_void
+)
+{
+	struct dm_struct		*dm = (struct dm_struct *)dm_void;
+	struct _hal_rf_				*rf = &(dm->rf_table);
+#if (DM_ODM_SUPPORT_TYPE == ODM_CE)
+	void	*adapter = dm->adapter;
+#if ((RTL8188F_SUPPORT == 1))
+	rtl8192c_odm_check_txpowertracking(adapter);
+#endif
+
+#if (RTL8188E_SUPPORT == 1)
+
+	if (!(rf->rf_supportability & HAL_RF_TX_PWR_TRACK))
+		return;
+
+	if (!cali_info->tm_trigger) {
+		odm_set_rf_reg(dm, RF_PATH_A, RF_T_METER, RFREGOFFSETMASK, 0x60);
+		/*DBG_8192C("Trigger 92C Thermal Meter!!\n");*/
+
+		cali_info->tm_trigger = 1;
+		return;
+
+	} else {
+		/*DBG_8192C("Schedule TxPowerTracking direct call!!\n");*/
+		odm_txpowertracking_callback_thermal_meter_8188e(adapter);
+		cali_info->tm_trigger = 0;
+	}
+#endif
+#endif
+}
+
+void
+odm_txpowertracking_check_mp(
+	void		*dm_void
+)
+{
+	struct dm_struct		*dm = (struct dm_struct *)dm_void;
+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
+	void	*adapter = dm->adapter;
+
+	if (*dm->is_fcs_mode_enable)
+		return;
+
+	if (odm_check_power_status(dm) == false) {
+		RT_TRACE(COMP_POWER_TRACKING, DBG_LOUD, ("check_pow_status return false\n"));
+		return;
+	}
+
+	if (IS_HARDWARE_TYPE_8821B(adapter)) /* TODO: Don't Do PowerTracking*/
+		return;
+
+	odm_txpowertracking_thermal_meter_check(adapter);
+
+
+#endif
+
+}
+
+
+void
+odm_txpowertracking_check_ap(
+	void		*dm_void
+)
+{
+	return;
+
+}
+
+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
+
+void
+odm_txpowertracking_direct_call(
+	void		*adapter
+)
+{
+	HAL_DATA_TYPE		*hal_data	= GET_HAL_DATA(((PADAPTER)adapter));
+	struct dm_struct			*dm = &hal_data->DM_OutSrc;
+
+	odm_txpowertracking_callback_thermal_meter(adapter);
+}
+
+void
+odm_txpowertracking_thermal_meter_check(
+	void		*adapter
+)
+{
+	static u8			tm_trigger = 0;
+	HAL_DATA_TYPE			*pHalData = GET_HAL_DATA(((PADAPTER)adapter));
+	struct dm_struct	*dm = &(pHalData->DM_OutSrc);
+	struct _hal_rf_			*rf = &(dm->rf_table);
+
+	if (!(rf->rf_supportability & HAL_RF_TX_PWR_TRACK)) {
+		RT_TRACE(COMP_POWER_TRACKING, DBG_LOUD,
+			("===>odm_txpowertracking_thermal_meter_check(),mgnt_info->is_txpowertracking is false, return!!\n"));
+		return;
+	}
+
+	if (!tm_trigger) {
+		if (IS_HARDWARE_TYPE_8188E(adapter) || IS_HARDWARE_TYPE_JAGUAR(adapter) || IS_HARDWARE_TYPE_8192E(adapter) || IS_HARDWARE_TYPE_8192F(adapter)
+		    ||IS_HARDWARE_TYPE_8723B(adapter) || IS_HARDWARE_TYPE_8814A(adapter) || IS_HARDWARE_TYPE_8188F(adapter) || IS_HARDWARE_TYPE_8703B(adapter)
+		    || IS_HARDWARE_TYPE_8822B(adapter) || IS_HARDWARE_TYPE_8723D(adapter) || IS_HARDWARE_TYPE_8821C(adapter) || IS_HARDWARE_TYPE_8710B(adapter))/* JJ ADD 20161014 */
+			PHY_SetRFReg(adapter, RF_PATH_A, RF_T_METER_88E, BIT(17) | BIT(16), 0x03);
+		else
+			PHY_SetRFReg(adapter, RF_PATH_A, RF_T_METER, RFREGOFFSETMASK, 0x60);
+
+		RT_TRACE(COMP_POWER_TRACKING, DBG_LOUD, ("Trigger Thermal Meter!!\n"));
+
+		tm_trigger = 1;
+		return;
+	} else {
+		RT_TRACE(COMP_POWER_TRACKING, DBG_LOUD, ("Schedule TxPowerTracking direct call!!\n"));
+		odm_txpowertracking_direct_call(adapter);
+		tm_trigger = 0;
+	}
+}
+
+#endif
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/halrf/halrf_powertracking_win.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/halrf/halrf_powertracking_win.h
--- linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/halrf/halrf_powertracking_win.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/halrf/halrf_powertracking_win.h	2020-04-10 16:35:06.820660254 +0300
@@ -0,0 +1,302 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+
+#ifndef __HALRF_POWERTRACKING_H__
+#define __HALRF_POWERTRACKING_H__
+
+#define	DPK_DELTA_MAPPING_NUM	13
+#define	index_mapping_HP_NUM	15
+#define	TXSCALE_TABLE_SIZE		37
+#define	OFDM_TABLE_SIZE			43
+#define	CCK_TABLE_SIZE			33
+#define	CCK_TABLE_SIZE_8723D    41
+#define	TXPWR_TRACK_TABLE_SIZE	30
+#define	DELTA_SWINGIDX_SIZE     30
+#define	DELTA_SWINTSSI_SIZE     61
+#define	BAND_NUM				3
+#define	MAX_RF_PATH	4
+#define	CCK_TABLE_SIZE_88F	21
+/* JJ ADD 20161014 */
+#define	CCK_TABLE_SIZE_8710B   41
+#define	CCK_TABLE_SIZE_8192F   41
+
+
+#define	dm_check_txpowertracking	odm_txpowertracking_check
+
+#define IQK_MATRIX_SETTINGS_NUM	(14+24+21) /* Channels_2_4G_NUM + Channels_5G_20M_NUM + Channels_5G */
+#define	AVG_THERMAL_NUM		8
+#define	iqk_matrix_reg_num	8
+#define	IQK_MAC_REG_NUM		4
+#define	IQK_ADDA_REG_NUM		16
+
+#define	IQK_BB_REG_NUM		9
+
+
+extern	u32 ofdm_swing_table[OFDM_TABLE_SIZE];
+extern	u8 cck_swing_table_ch1_ch13[CCK_TABLE_SIZE][8];
+extern	u8 cck_swing_table_ch14[CCK_TABLE_SIZE][8];
+
+extern	u32 ofdm_swing_table_new[OFDM_TABLE_SIZE];
+extern	u8 cck_swing_table_ch1_ch13_new[CCK_TABLE_SIZE][8];
+extern	u8 cck_swing_table_ch14_new[CCK_TABLE_SIZE][8];
+extern	u8 cck_swing_table_ch1_ch14_88f[CCK_TABLE_SIZE_88F][16];
+extern	u8 cck_swing_table_ch1_ch13_88f[CCK_TABLE_SIZE_88F][16];
+extern	u8 cck_swing_table_ch14_88f[CCK_TABLE_SIZE_88F][16];
+extern	u32 cck_swing_table_ch1_ch14_8723d[CCK_TABLE_SIZE_8723D];
+/* JJ ADD 20161014 */
+extern	u32 cck_swing_table_ch1_ch14_8710b[CCK_TABLE_SIZE_8710B];
+extern	u32 cck_swing_table_ch1_ch14_8192f[CCK_TABLE_SIZE_8192F];
+
+extern  u32 tx_scaling_table_jaguar[TXSCALE_TABLE_SIZE];
+
+/* <20121018, Kordan> In case fail to read TxPowerTrack.txt, we use the table of 88E as the default table. */
+static u8 delta_swing_table_idx_2ga_p_8188e[] = {0, 0, 0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 4,  4,  4,  4,  4,  4,  5,  5,  7,  7,  8,  8,  8,  9,  9,  9,  9,  9};
+static u8 delta_swing_table_idx_2ga_n_8188e[] = {0, 0, 0, 2, 2, 3, 3, 4, 4, 4, 4, 5, 5,  6,  6,  7,  7,  7,  7,  8,  8,  9,  9, 10, 10, 10, 11, 11, 11, 11};
+
+void
+odm_txpowertracking_check(
+	void		*dm_void
+);
+
+void
+odm_txpowertracking_check_ap(
+	void		*dm_void
+);
+
+void
+odm_txpowertracking_thermal_meter_init(
+	void		*dm_void
+);
+
+void
+odm_txpowertracking_init(
+	void		*dm_void
+);
+
+void
+odm_txpowertracking_check_mp(
+	void		*dm_void
+);
+
+
+void
+odm_txpowertracking_check_ce(
+	void		*dm_void
+);
+
+#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN))
+
+
+void
+odm_txpowertracking_thermal_meter_check(
+	void		*adapter
+);
+
+#endif
+
+struct iqk_matrix_regs_setting {
+	boolean	is_iqk_done;
+	s32		value[3][iqk_matrix_reg_num];
+	boolean	is_bw_iqk_result_saved[3];
+};
+
+struct dm_rf_calibration_struct {
+	/* for tx power tracking */
+
+	u32	rega24; /* for TempCCK */
+	s32	rege94;
+	s32	rege9c;
+	s32	regeb4;
+	s32	regebc;
+	/* u8 is_txpowertracking; */
+	u8	tx_powercount;
+	boolean is_txpowertracking_init;
+	boolean is_txpowertracking;
+	u8  	txpowertrack_control; /* for mp mode, turn off txpwrtracking as default */
+	u8	tm_trigger;
+	u8  	internal_pa_5g[2];	/* pathA / pathB */
+
+	u8  	thermal_meter[2];    /* thermal_meter, index 0 for RFIC0, and 1 for RFIC1 */
+	u8	thermal_value;
+	u8	thermal_value_lck;
+	u8	thermal_value_iqk;
+	u8  thermal_value_dpk;
+	s8  	thermal_value_delta; /* delta of thermal_value and efuse thermal */
+	u8	thermal_value_avg[AVG_THERMAL_NUM];
+	u8	thermal_value_avg_index;
+	u8	thermal_value_rx_gain;
+
+
+	boolean	is_reloadtxpowerindex;
+	u8	is_rf_pi_enable;
+	u32 	txpowertracking_callback_cnt; /* cosa add for debug */
+
+
+	/* ------------------------- Tx power Tracking ------------------------- */
+	u8	is_cck_in_ch14;
+	u8	CCK_index;
+	u8	OFDM_index[MAX_RF_PATH];
+	s8	power_index_offset[MAX_RF_PATH];
+	s8	delta_power_index[MAX_RF_PATH];
+	s8	delta_power_index_last[MAX_RF_PATH];
+	boolean is_tx_power_changed;
+	s8	xtal_offset;
+	s8	xtal_offset_last;
+
+	struct iqk_matrix_regs_setting iqk_matrix_reg_setting[IQK_MATRIX_SETTINGS_NUM];
+	u8	delta_lck;
+	s8  bb_swing_diff_2g, bb_swing_diff_5g; /* Unit: dB */
+	u8  delta_swing_table_idx_2g_cck_a_p[DELTA_SWINGIDX_SIZE];
+	u8  delta_swing_table_idx_2g_cck_a_n[DELTA_SWINGIDX_SIZE];
+	u8  delta_swing_table_idx_2g_cck_b_p[DELTA_SWINGIDX_SIZE];
+	u8  delta_swing_table_idx_2g_cck_b_n[DELTA_SWINGIDX_SIZE];
+	u8  delta_swing_table_idx_2g_cck_c_p[DELTA_SWINGIDX_SIZE];
+	u8  delta_swing_table_idx_2g_cck_c_n[DELTA_SWINGIDX_SIZE];
+	u8  delta_swing_table_idx_2g_cck_d_p[DELTA_SWINGIDX_SIZE];
+	u8  delta_swing_table_idx_2g_cck_d_n[DELTA_SWINGIDX_SIZE];
+	u8  delta_swing_table_idx_2ga_p[DELTA_SWINGIDX_SIZE];
+	u8  delta_swing_table_idx_2ga_n[DELTA_SWINGIDX_SIZE];
+	u8  delta_swing_table_idx_2gb_p[DELTA_SWINGIDX_SIZE];
+	u8  delta_swing_table_idx_2gb_n[DELTA_SWINGIDX_SIZE];
+	u8  delta_swing_table_idx_2gc_p[DELTA_SWINGIDX_SIZE];
+	u8  delta_swing_table_idx_2gc_n[DELTA_SWINGIDX_SIZE];
+	u8  delta_swing_table_idx_2gd_p[DELTA_SWINGIDX_SIZE];
+	u8  delta_swing_table_idx_2gd_n[DELTA_SWINGIDX_SIZE];
+	u8  delta_swing_table_idx_5ga_p[BAND_NUM][DELTA_SWINGIDX_SIZE];
+	u8  delta_swing_table_idx_5ga_n[BAND_NUM][DELTA_SWINGIDX_SIZE];
+	u8  delta_swing_table_idx_5gb_p[BAND_NUM][DELTA_SWINGIDX_SIZE];
+	u8  delta_swing_table_idx_5gb_n[BAND_NUM][DELTA_SWINGIDX_SIZE];
+	u8  delta_swing_table_idx_5gc_p[BAND_NUM][DELTA_SWINGIDX_SIZE];
+	u8  delta_swing_table_idx_5gc_n[BAND_NUM][DELTA_SWINGIDX_SIZE];
+	u8  delta_swing_table_idx_5gd_p[BAND_NUM][DELTA_SWINGIDX_SIZE];
+	u8  delta_swing_table_idx_5gd_n[BAND_NUM][DELTA_SWINGIDX_SIZE];
+	u8  delta_swing_tssi_table_2g_cck_a[DELTA_SWINTSSI_SIZE];
+	u8  delta_swing_tssi_table_2g_cck_b[DELTA_SWINTSSI_SIZE];
+	u8  delta_swing_tssi_table_2g_cck_c[DELTA_SWINTSSI_SIZE];
+	u8  delta_swing_tssi_table_2g_cck_d[DELTA_SWINTSSI_SIZE];
+	u8  delta_swing_tssi_table_2ga[DELTA_SWINTSSI_SIZE];
+	u8  delta_swing_tssi_table_2gb[DELTA_SWINTSSI_SIZE];
+	u8  delta_swing_tssi_table_2gc[DELTA_SWINTSSI_SIZE];
+	u8  delta_swing_tssi_table_2gd[DELTA_SWINTSSI_SIZE];
+	u8  delta_swing_tssi_table_5ga[BAND_NUM][DELTA_SWINTSSI_SIZE];
+	u8  delta_swing_tssi_table_5gb[BAND_NUM][DELTA_SWINTSSI_SIZE];
+	u8  delta_swing_tssi_table_5gc[BAND_NUM][DELTA_SWINTSSI_SIZE];
+	u8  delta_swing_tssi_table_5gd[BAND_NUM][DELTA_SWINTSSI_SIZE];
+	s8  delta_swing_table_xtal_p[DELTA_SWINGIDX_SIZE];
+	s8  delta_swing_table_xtal_n[DELTA_SWINGIDX_SIZE];
+	u8  delta_swing_table_idx_2ga_p_8188e[DELTA_SWINGIDX_SIZE];
+	u8  delta_swing_table_idx_2ga_n_8188e[DELTA_SWINGIDX_SIZE];
+
+	u8			bb_swing_idx_ofdm[MAX_RF_PATH];
+	u8			bb_swing_idx_ofdm_current;
+#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
+	u8			bb_swing_idx_ofdm_base[MAX_RF_PATH];
+#else
+	u8			bb_swing_idx_ofdm_base;
+#endif
+	boolean		default_bb_swing_index_flag;
+	boolean			bb_swing_flag_ofdm;
+	u8			bb_swing_idx_cck;
+	u8			bb_swing_idx_cck_current;
+	u8			bb_swing_idx_cck_base;
+	u8			default_ofdm_index;
+	u8			default_cck_index;
+	boolean			bb_swing_flag_cck;
+
+	s8			absolute_ofdm_swing_idx[MAX_RF_PATH];
+	s8			remnant_ofdm_swing_idx[MAX_RF_PATH];
+	s8			absolute_cck_swing_idx[MAX_RF_PATH];
+	s8			remnant_cck_swing_idx;
+	s8			modify_tx_agc_value;       /*Remnat compensate value at tx_agc */
+	boolean			modify_tx_agc_flag_path_a;
+	boolean			modify_tx_agc_flag_path_b;
+	boolean			modify_tx_agc_flag_path_c;
+	boolean			modify_tx_agc_flag_path_d;
+	boolean			modify_tx_agc_flag_path_a_cck;
+	boolean			modify_tx_agc_flag_path_b_cck;
+
+	s8			kfree_offset[MAX_RF_PATH];
+
+	/* -------------------------------------------------------------------- */
+
+	/* for IQK */
+	u32	regc04;
+	u32	reg874;
+	u32	regc08;
+	u32	regb68;
+	u32	regb6c;
+	u32	reg870;
+	u32	reg860;
+	u32	reg864;
+
+	boolean	is_iqk_initialized;
+	boolean is_lck_in_progress;
+	boolean	is_antenna_detected;
+	boolean	is_need_iqk;
+	boolean	is_iqk_in_progress;
+	boolean	is_iqk_pa_off;
+	u8	delta_iqk;
+	u32	ADDA_backup[IQK_ADDA_REG_NUM];
+	u32	IQK_MAC_backup[IQK_MAC_REG_NUM];
+	u32	IQK_BB_backup_recover[9];
+	u32	IQK_BB_backup[IQK_BB_REG_NUM];
+	u32	tx_iqc_8723b[2][3][2]; /* { {S1: 0xc94, 0xc80, 0xc4c} , {S0: 0xc9c, 0xc88, 0xc4c}} */
+	u32	rx_iqc_8723b[2][2][2]; /* { {S1: 0xc14, 0xca0} ,           {S0: 0xc14, 0xca0}} */
+	u32	tx_iqc_8703b[3][2];	/* { {S1: 0xc94, 0xc80, 0xc4c} , {S0: 0xc9c, 0xc88, 0xc4c}}*/
+	u32	rx_iqc_8703b[2][2];	/* { {S1: 0xc14, 0xca0} ,           {S0: 0xc14, 0xca0}}*/
+	u32	tx_iqc_8723d[2][3][2];	/* { {S1: 0xc94, 0xc80, 0xc4c} , {S0: 0xc9c, 0xc88, 0xc4c}}*/
+	u32	rx_iqc_8723d[2][2][2];	/* { {S1: 0xc14, 0xca0} ,           {S0: 0xc14, 0xca0}}*/
+	/* JJ ADD 20161014 */
+	u32	tx_iqc_8710b[2][3][2];	/* { {S1: 0xc94, 0xc80, 0xc4c} , {S0: 0xc9c, 0xc88, 0xc4c}}*/
+	u32	rx_iqc_8710b[2][2][2];	/* { {S1: 0xc14, 0xca0} ,           {S0: 0xc14, 0xca0}}*/
+
+	u64	iqk_start_time;
+	u64	iqk_total_progressing_time;
+	u64	iqk_progressing_time;
+	u64	lck_progressing_time;
+	u32  lok_result;
+	u8	iqk_step;
+	u8	kcount;
+	u8	retry_count[4][2]; /* [4]: path ABCD, [2] TXK, RXK */
+	boolean	is_mp_mode;
+
+	/* for APK */
+	u32 	ap_koutput[2][2]; /* path A/B; output1_1a/output1_2a */
+	u8	is_ap_kdone;
+	u8	is_apk_thermal_meter_ignore;
+
+	/* DPK */
+	boolean is_dpk_fail;
+	u8	is_dp_done;
+	u8	is_dp_path_aok;
+	u8	is_dp_path_bok;
+
+	u32	tx_lok[2];
+	u32  dpk_tx_agc;
+	s32  dpk_gain;
+	u32  dpk_thermal[4];
+
+	s8 modify_tx_agc_value_ofdm;
+	s8 modify_tx_agc_value_cck;
+
+	/*Add by Yuchen for Kfree Phydm*/
+	u8			reg_rf_kfree_enable;	/*for registry*/
+	u8			rf_kfree_enable;		/*for efuse enable check*/
+};
+
+
+
+
+#endif	/*#ifndef __HALRF_POWER_TRACKING_H__*/
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/halrf/halrf_psd.c linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/halrf/halrf_psd.c
--- linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/halrf/halrf_psd.c	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/halrf/halrf_psd.c	2020-04-10 16:35:06.820660254 +0300
@@ -0,0 +1,301 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+
+/*============================================================
+ * include files
+ *============================================================
+ */
+#include "mp_precomp.h"
+#include "phydm_precomp.h"
+
+#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
+
+#if 0
+u32 _sqrt(u64 n)
+{
+	u64	ans = 0, q = 0;
+	s64	i;
+
+	/*for (i = sizeof(n) * 8 - 2; i > -1; i = i - 2) {*/
+	for (i = 8 * 8 - 2; i > -1; i = i - 2) {
+		q = (q << 2) | ((n & (3 << i)) >> i);
+		if (q >= ((ans << 2) | 1))
+		{
+			q = q - ((ans << 2) | 1);
+			ans = (ans << 1) | 1;
+		}
+		else
+			ans = ans << 1;
+	}
+	DbgPrint("ans=0x%x\n", ans);
+
+	return (u32)ans;
+}
+#endif
+
+u64 _sqrt(u64 x)
+{
+	u64 i = 0;
+	u64 j = x / 2 + 1;
+
+	while (i <= j) {
+		u64 mid = (i + j) / 2;
+
+		u64 sq = mid * mid;
+
+		if (sq == x)
+			return mid;
+		else if (sq < x)
+			i = mid + 1;
+		else
+			j = mid - 1;
+	}
+
+	return j;
+}
+
+u32 halrf_get_psd_data(
+	struct dm_struct *dm,
+	u32 point)
+{
+	struct _hal_rf_ *rf = &(dm->rf_table);
+	struct _halrf_psd_data *psd = &(rf->halrf_psd_data);
+	u32 psd_val = 0, psd_reg, psd_report, psd_point, psd_start, i, delay_time;
+
+#if (DEV_BUS_TYPE == RT_USB_INTERFACE) || (DEV_BUS_TYPE == RT_SDIO_INTERFACE)
+	if (psd->average == 0)
+		delay_time = 100;
+	else
+		delay_time = 0;
+#else
+	if (psd->average == 0)
+		delay_time = 1000;
+	else
+		delay_time = 100;
+#endif
+
+	if (dm->support_ic_type & (ODM_RTL8812 | ODM_RTL8821 | ODM_RTL8814A | ODM_RTL8822B | ODM_RTL8821C)) {
+		psd_reg = R_0x910;
+		psd_report = R_0xf44;
+	} else {
+		psd_reg = R_0x808;
+		psd_report = R_0x8b4;
+	}
+
+	if (dm->support_ic_type & ODM_RTL8710B) {
+		psd_point = 0xeffffc00;
+		psd_start = 0x10000000;
+	} else {
+		psd_point = 0xffbffc00;
+		psd_start = 0x00400000;
+	}
+
+	psd_val = odm_get_bb_reg(dm, psd_reg, MASKDWORD);
+
+	psd_val &= psd_point;
+	psd_val |= point;
+
+	odm_set_bb_reg(dm, psd_reg, MASKDWORD, psd_val);
+
+	psd_val |= psd_start;
+
+	odm_set_bb_reg(dm, psd_reg, MASKDWORD, psd_val);
+
+	for (i = 0; i < delay_time; i++)
+		ODM_delay_us(1);
+
+	psd_val = odm_get_bb_reg(dm, psd_report, MASKDWORD);
+
+	if (dm->support_ic_type & (ODM_RTL8821C | ODM_RTL8710B)) {
+		psd_val &= MASKL3BYTES;
+		psd_val = psd_val / 32;
+	} else {
+		psd_val &= MASKLWORD;
+	}
+
+	return psd_val;
+}
+
+void halrf_psd(
+	struct dm_struct *dm,
+	u32 point,
+	u32 start_point,
+	u32 stop_point,
+	u32 average)
+{
+	struct _hal_rf_ *rf = &(dm->rf_table);
+	struct _halrf_psd_data *psd = &(rf->halrf_psd_data);
+
+	u32 i = 0, j = 0, k = 0;
+	u32 psd_reg, avg_org, point_temp, average_tmp;
+	u64 data_tatal = 0, data_temp[64] = {0};
+
+	psd->buf_size = 256;
+
+	if (average == 0)
+		average_tmp = 1;
+	else
+		average_tmp = average;
+
+	if (dm->support_ic_type & (ODM_RTL8812 | ODM_RTL8821 | ODM_RTL8814A | ODM_RTL8822B | ODM_RTL8821C))
+		psd_reg = R_0x910;
+	else
+		psd_reg = R_0x808;
+
+#if 0
+	dbg_print("[PSD]point=%d, start_point=%d, stop_point=%d, average=%d, average_tmp=%d, buf_size=%d\n",
+		point, start_point, stop_point, average, average_tmp, psd->buf_size);
+#endif
+
+	for (i = 0; i < psd->buf_size; i++)
+		psd->psd_data[i] = 0;
+
+	if (dm->support_ic_type & ODM_RTL8710B)
+		avg_org = odm_get_bb_reg(dm, psd_reg, 0x30000);
+	else
+		avg_org = odm_get_bb_reg(dm, psd_reg, 0x3000);
+
+	if (average != 0) {
+		if (dm->support_ic_type & ODM_RTL8710B)
+			odm_set_bb_reg(dm, psd_reg, 0x30000, 0x1);
+		else
+			odm_set_bb_reg(dm, psd_reg, 0x3000, 0x1);
+	}
+
+#if 0
+	if (avg_temp == 0)
+		avg = 1;
+	else if (avg_temp == 1)
+		avg = 8;
+	else if (avg_temp == 2)
+		avg = 16;
+	else if (avg_temp == 3)
+		avg = 32;
+#endif
+
+	i = start_point;
+	while (i < stop_point) {
+		data_tatal = 0;
+
+		if (i >= point)
+			point_temp = i - point;
+		else
+			point_temp = i;
+
+		for (k = 0; k < average_tmp; k++) {
+			data_temp[k] = halrf_get_psd_data(dm, point_temp);
+			data_tatal = data_tatal + (data_temp[k] * data_temp[k]);
+
+#if 0
+			if ((k % 20) == 0)
+				dbg_print("\n ");
+
+			dbg_print("0x%x ", data_temp[k]);
+#endif
+		}
+		/*dbg_print("\n");*/
+
+		data_tatal = ((data_tatal * 100) / average_tmp);
+		psd->psd_data[j] = (u32)_sqrt(data_tatal);
+
+		i++;
+		j++;
+	}
+
+#if 0
+	for (i = 0; i < psd->buf_size; i++) {
+		if ((i % 20) == 0)
+			dbg_print("\n ");
+
+		dbg_print("0x%x ", psd->psd_data[i]);
+	}
+	dbg_print("\n\n");
+#endif
+
+	if (dm->support_ic_type & ODM_RTL8710B)
+		odm_set_bb_reg(dm, psd_reg, 0x30000, avg_org);
+	else
+		odm_set_bb_reg(dm, psd_reg, 0x3000, avg_org);
+}
+
+enum rt_status
+halrf_psd_init(
+	struct dm_struct *dm)
+{
+	enum rt_status ret_status = RT_STATUS_SUCCESS;
+	struct _hal_rf_ *rf = &(dm->rf_table);
+	struct _halrf_psd_data *psd = &(rf->halrf_psd_data);
+
+	if (psd->psd_progress) {
+		ret_status = RT_STATUS_PENDING;
+	} else {
+		psd->psd_progress = 1;
+		halrf_psd(dm, psd->point, psd->start_point, psd->stop_point, psd->average);
+		psd->psd_progress = 0;
+	}
+
+	return ret_status;
+}
+
+enum rt_status
+halrf_psd_query(
+	struct dm_struct *dm,
+	u32 *outbuf,
+	u32 buf_size)
+{
+	enum rt_status ret_status = RT_STATUS_SUCCESS;
+	struct _hal_rf_ *rf = &(dm->rf_table);
+	struct _halrf_psd_data *psd = &(rf->halrf_psd_data);
+
+	if (psd->psd_progress)
+		ret_status = RT_STATUS_PENDING;
+	else
+		PlatformMoveMemory(outbuf, psd->psd_data, 0x400);
+
+	return ret_status;
+}
+
+enum rt_status
+halrf_psd_init_query(
+	struct dm_struct *dm,
+	u32 *outbuf,
+	u32 point,
+	u32 start_point,
+	u32 stop_point,
+	u32 average,
+	u32 buf_size)
+{
+	enum rt_status ret_status = RT_STATUS_SUCCESS;
+	struct _hal_rf_ *rf = &(dm->rf_table);
+	struct _halrf_psd_data *psd = &(rf->halrf_psd_data);
+
+	psd->point = point;
+	psd->start_point = start_point;
+	psd->stop_point = stop_point;
+	psd->average = average;
+
+	if (psd->psd_progress) {
+		ret_status = RT_STATUS_PENDING;
+	} else {
+		psd->psd_progress = 1;
+		halrf_psd(dm, psd->point, psd->start_point, psd->stop_point, psd->average);
+		PlatformMoveMemory(outbuf, psd->psd_data, 0x400);
+		psd->psd_progress = 0;
+	}
+
+	return ret_status;
+}
+
+#endif /*#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)*/
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/halrf/halrf_psd.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/halrf/halrf_psd.h
--- linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/halrf/halrf_psd.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/halrf/halrf_psd.h	2020-04-10 16:35:06.820660254 +0300
@@ -0,0 +1,52 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+
+#ifndef __HALRF_PSD_H__
+#define __HALRF_PSD_H__
+
+#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
+
+struct _halrf_psd_data {
+	u32 point;
+	u32 start_point;
+	u32 stop_point;
+	u32 average;
+	u32 buf_size;
+	u32 psd_data[256];
+	u32 psd_progress;
+};
+
+enum rt_status
+halrf_psd_init(
+	struct dm_struct *dm);
+
+enum rt_status
+halrf_psd_query(
+	struct dm_struct *dm,
+	u32 *outbuf,
+	u32 buf_size);
+
+enum rt_status
+halrf_psd_init_query(
+	struct dm_struct *dm,
+	u32 *outbuf,
+	u32 point,
+	u32 start_point,
+	u32 stop_point,
+	u32 average,
+	u32 buf_size);
+
+#endif /*#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)*/
+#endif /*#ifndef __HALRF_PSD_H__*/
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/halrf/halrf_txgapcal.c linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/halrf/halrf_txgapcal.c
--- linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/halrf/halrf_txgapcal.c	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/halrf/halrf_txgapcal.c	2020-04-10 16:35:06.821660301 +0300
@@ -0,0 +1,298 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017  Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * The full GNU General Public License is included in this distribution in the
+ * file called LICENSE.
+ *
+ * Contact Information:
+ * wlanfae <wlanfae@realtek.com>
+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
+ * Hsinchu 300, Taiwan.
+ *
+ * Larry Finger <Larry.Finger@lwfinger.net>
+ *
+ *****************************************************************************/
+#include "mp_precomp.h"
+#include "phydm_precomp.h"
+
+void odm_bub_sort(u32 *data, u32 n)
+{
+	int i, j, temp, sp;
+
+	for (i = n - 1; i >= 0; i--) {
+		sp = 1;
+		for (j = 0; j < i; j++) {
+			if (data[j] < data[j + 1]) {
+				temp = data[j];
+				data[j] = data[j + 1];
+				data[j + 1] = temp;
+				sp = 0;
+			}
+		}
+		if (sp == 1)
+			break;
+	}
+}
+
+#if (RTL8197F_SUPPORT == 1)
+
+u4Byte
+odm_tx_gain_gap_psd_8197f(
+	void *dm_void,
+	u1Byte rf_path,
+	u4Byte rf56)
+{
+	PDM_ODM_T dm = (PDM_ODM_T)dm_void;
+
+	u1Byte i, j;
+	u4Byte psd_vaule[5], psd_avg_time = 5, psd_vaule_temp;
+
+	u4Byte iqk_ctl_addr[2][6] = {{0xe30, 0xe34, 0xe50, 0xe54, 0xe38, 0xe3c},
+				     {0xe50, 0xe54, 0xe30, 0xe34, 0xe58, 0xe5c}};
+
+	u4Byte psd_finish_bit[2] = {0x04000000, 0x20000000};
+	u4Byte psd_fail_bit[2] = {0x08000000, 0x40000000};
+
+	u4Byte psd_cntl_value[2][2] = {{0x38008c1c, 0x10008c1c},
+				       {0x38008c2c, 0x10008c2c}};
+
+	u4Byte psd_report_addr[2] = {0xea0, 0xec0};
+
+	odm_set_rf_reg(dm, rf_path, RF_0xdf, bRFRegOffsetMask, 0x00e02);
+
+	ODM_delay_us(100);
+
+	odm_set_bb_reg(dm, R_0xe28, 0xffffffff, 0x0);
+
+	odm_set_rf_reg(dm, rf_path, RF_0x56, 0xfff, rf56);
+	while (rf56 != (odm_get_rf_reg(dm, rf_path, RF_0x56, 0xfff)))
+		odm_set_rf_reg(dm, rf_path, RF_0x56, 0xfff, rf56);
+
+	odm_set_bb_reg(dm, R_0xd94, 0xffffffff, 0x44FFBB44);
+	odm_set_bb_reg(dm, R_0xe70, 0xffffffff, 0x00400040);
+	odm_set_bb_reg(dm, R_0xc04, 0xffffffff, 0x6f005403);
+	odm_set_bb_reg(dm, R_0xc08, 0xffffffff, 0x000804e4);
+	odm_set_bb_reg(dm, R_0x874, 0xffffffff, 0x04203400);
+	odm_set_bb_reg(dm, R_0xe28, 0xffffffff, 0x80800000);
+
+	odm_set_bb_reg(dm, iqk_ctl_addr[rf_path][0], 0xffffffff, psd_cntl_value[rf_path][0]);
+	odm_set_bb_reg(dm, iqk_ctl_addr[rf_path][1], 0xffffffff, psd_cntl_value[rf_path][1]);
+	odm_set_bb_reg(dm, iqk_ctl_addr[rf_path][2], 0xffffffff, psd_cntl_value[rf_path][0]);
+	odm_set_bb_reg(dm, iqk_ctl_addr[rf_path][3], 0xffffffff, psd_cntl_value[rf_path][0]);
+	odm_set_bb_reg(dm, iqk_ctl_addr[rf_path][4], 0xffffffff, 0x8215001F);
+	odm_set_bb_reg(dm, iqk_ctl_addr[rf_path][5], 0xffffffff, 0x2805001F);
+
+	odm_set_bb_reg(dm, R_0xe40, 0xffffffff, 0x81007C00);
+	odm_set_bb_reg(dm, R_0xe44, 0xffffffff, 0x81004800);
+	odm_set_bb_reg(dm, R_0xe4c, 0xffffffff, 0x0046a8d0);
+
+	for (i = 0; i < psd_avg_time; i++) {
+		for (j = 0; j < 1000; j++) {
+			odm_set_bb_reg(dm, R_0xe48, 0xffffffff, 0xfa005800);
+			odm_set_bb_reg(dm, R_0xe48, 0xffffffff, 0xf8005800);
+
+			while (!odm_get_bb_reg(dm, R_0xeac, psd_finish_bit[rf_path]))
+				; /*wait finish bit*/
+
+			if (!odm_get_bb_reg(dm, R_0xeac, psd_fail_bit[rf_path])) { /*check fail bit*/
+
+				psd_vaule[i] = odm_get_bb_reg(dm, psd_report_addr[rf_path], 0xffffffff);
+
+				if (psd_vaule[i] > 0xffff)
+					break;
+			}
+		}
+
+		RF_DBG(dm, DBG_RF_IQK,
+		       "[TGGC] rf0=0x%x rf56=0x%x rf56_reg=0x%x time=%d psd_vaule=0x%x\n",
+		       odm_get_rf_reg(dm, rf_path, RF_0x0, 0xff), rf56,
+		       odm_get_rf_reg(dm, rf_path, RF_0x56, 0xfff), j,
+		       psd_vaule[i]);
+	}
+
+	odm_bub_sort(psd_vaule, psd_avg_time);
+
+	psd_vaule_temp = psd_vaule[(UINT)(psd_avg_time / 2)];
+
+	odm_set_bb_reg(dm, R_0xd94, 0xffffffff, 0x44BBBB44);
+	odm_set_bb_reg(dm, R_0xe70, 0xffffffff, 0x80408040);
+	odm_set_bb_reg(dm, R_0xc04, 0xffffffff, 0x6f005433);
+	odm_set_bb_reg(dm, R_0xc08, 0xffffffff, 0x000004e4);
+	odm_set_bb_reg(dm, R_0x874, 0xffffffff, 0x04003400);
+	odm_set_bb_reg(dm, R_0xe28, 0xffffffff, 0x00000000);
+
+	RF_DBG(dm, DBG_RF_IQK,
+	       "[TGGC] rf0=0x%x rf56=0x%x rf56_reg=0x%x psd_vaule_temp=0x%x\n",
+	       odm_get_rf_reg(dm, rf_path, RF_0x0, 0xff), rf56,
+	       odm_get_rf_reg(dm, rf_path, RF_0x56, 0xfff), psd_vaule_temp);
+
+	odm_set_rf_reg(dm, rf_path, RF_0xdf, bRFRegOffsetMask, 0x00602);
+
+	return psd_vaule_temp;
+}
+
+void odm_tx_gain_gap_calibration_8197f(
+	void *dm_void)
+{
+	PDM_ODM_T dm = (PDM_ODM_T)dm_void;
+
+	u1Byte rf_path, rf0_idx, rf0_idx_current, rf0_idx_next, i, delta_gain_retry = 3;
+
+	s1Byte delta_gain_gap_pre, delta_gain_gap[2][11];
+	u4Byte rf56_current, rf56_next, psd_value_current, psd_value_next;
+	u4Byte psd_gap, rf56_current_temp[2][11];
+	s4Byte rf33[2][11];
+
+	memset(rf33, 0x0, sizeof(rf33));
+
+	for (rf_path = RF_PATH_A; rf_path <= RF_PATH_B; rf_path++) {
+		if (rf_path == RF_PATH_A)
+			odm_set_bb_reg(dm, R_0x88c, (BIT(21) | BIT(20)), 0x3); /*disable 3-wire*/
+		else if (rf_path == RF_PATH_B)
+			odm_set_bb_reg(dm, R_0x88c, (BIT(23) | BIT(22)), 0x3); /*disable 3-wire*/
+
+		ODM_delay_us(100);
+
+		for (rf0_idx = 1; rf0_idx <= 10; rf0_idx++) {
+			rf0_idx_current = 3 * (rf0_idx - 1) + 1;
+			odm_set_rf_reg(dm, rf_path, RF_0x0, 0xff, rf0_idx_current);
+			ODM_delay_us(100);
+			rf56_current_temp[rf_path][rf0_idx] = odm_get_rf_reg(dm, rf_path, RF_0x56, 0xfff);
+			rf56_current = rf56_current_temp[rf_path][rf0_idx];
+
+			rf0_idx_next = 3 * rf0_idx + 1;
+			odm_set_rf_reg(dm, rf_path, RF_0x0, 0xff, rf0_idx_next);
+			ODM_delay_us(100);
+			rf56_next = odm_get_rf_reg(dm, rf_path, RF_0x56, 0xfff);
+
+			RF_DBG(dm, DBG_RF_IQK,
+			       "[TGGC] rf56_current[%d][%d]=0x%x rf56_next[%d][%d]=0x%x\n",
+			       rf_path, rf0_idx, rf56_current, rf_path, rf0_idx,
+			       rf56_next);
+
+			if ((rf56_current >> 5) == (rf56_next >> 5)) {
+				delta_gain_gap[rf_path][rf0_idx] = 0;
+
+				RF_DBG(dm, DBG_RF_IQK,
+				       "[TGGC] rf56_current[11:5] == rf56_next[%d][%d][11:5]=0x%x delta_gain_gap[%d][%d]=%d\n",
+				       rf_path, rf0_idx, (rf56_next >> 5),
+				       rf_path, rf0_idx,
+				       delta_gain_gap[rf_path][rf0_idx]);
+
+				continue;
+			}
+
+			RF_DBG(dm, DBG_RF_IQK,
+			       "[TGGC] rf56_current[%d][%d][11:5]=0x%x != rf56_next[%d][%d][11:5]=0x%x\n",
+			       rf_path, rf0_idx, (rf56_current >> 5), rf_path,
+			       rf0_idx, (rf56_next >> 5));
+
+			for (i = 0; i < delta_gain_retry; i++) {
+				psd_value_current = odm_tx_gain_gap_psd_8197f(dm, rf_path, rf56_current);
+
+				psd_value_next = odm_tx_gain_gap_psd_8197f(dm, rf_path, rf56_next - 2);
+
+				psd_gap = psd_value_next / (psd_value_current / 1000);
+
+#if 0
+				if (psd_gap > 1413)
+					delta_gain_gap[rf_path][rf0_idx] = 1;
+				else if (psd_gap > 1122)
+					delta_gain_gap[rf_path][rf0_idx] = 0;
+				else
+					delta_gain_gap[rf_path][rf0_idx] = -1;
+#endif
+
+				if (psd_gap > 1445)
+					delta_gain_gap[rf_path][rf0_idx] = 1;
+				else if (psd_gap > 1096)
+					delta_gain_gap[rf_path][rf0_idx] = 0;
+				else
+					delta_gain_gap[rf_path][rf0_idx] = -1;
+
+				if (i == 0)
+					delta_gain_gap_pre = delta_gain_gap[rf_path][rf0_idx];
+
+				RF_DBG(dm, DBG_RF_IQK,
+				       "[TGGC] psd_value_current=0x%x psd_value_next=0x%x psd_value_next/psd_value_current=%d delta_gain_gap[%d][%d]=%d\n",
+				       psd_value_current, psd_value_next,
+				       psd_gap, rf_path, rf0_idx,
+				       delta_gain_gap[rf_path][rf0_idx]);
+
+				if (i == 0 && delta_gain_gap[rf_path][rf0_idx] == 0)
+					break;
+
+				if (delta_gain_gap_pre != delta_gain_gap[rf_path][rf0_idx]) {
+					delta_gain_gap[rf_path][rf0_idx] = 0;
+
+					RF_DBG(dm, DBG_RF_IQK, "[TGGC] delta_gain_gap_pre(%d) != delta_gain_gap[%d][%d](%d) time=%d\n",
+					       delta_gain_gap_pre, rf_path, rf0_idx, delta_gain_gap[rf_path][rf0_idx], i);
+
+					break;
+				}
+
+				RF_DBG(dm, DBG_RF_IQK,
+				       "[TGGC] delta_gain_gap_pre(%d) == delta_gain_gap[%d][%d](%d) time=%d\n",
+				       delta_gain_gap_pre, rf_path, rf0_idx,
+				       delta_gain_gap[rf_path][rf0_idx], i);
+			}
+		}
+
+		if (rf_path == RF_PATH_A)
+			odm_set_bb_reg(dm, R_0x88c, (BIT(21) | BIT(20)), 0x0); /*enable 3-wire*/
+		else if (rf_path == RF_PATH_B)
+			odm_set_bb_reg(dm, R_0x88c, (BIT(23) | BIT(22)), 0x0); /*enable 3-wire*/
+
+		ODM_delay_us(100);
+	}
+
+	/*odm_set_bb_reg(dm, R_0x88c, (BIT(23) | BIT(22) | BIT(21) | BIT(20)), 0x0);*/ /*enable 3-wire*/
+
+	for (rf_path = RF_PATH_A; rf_path <= RF_PATH_B; rf_path++) {
+		odm_set_rf_reg(dm, rf_path, RF_0xef, bRFRegOffsetMask, 0x00100);
+
+		for (rf0_idx = 1; rf0_idx <= 10; rf0_idx++) {
+			rf33[rf_path][rf0_idx] = rf33[rf_path][rf0_idx] + (rf56_current_temp[rf_path][rf0_idx] & 0x1f);
+
+			for (i = rf0_idx; i <= 10; i++)
+				rf33[rf_path][rf0_idx] = rf33[rf_path][rf0_idx] + delta_gain_gap[rf_path][i];
+
+			if (rf33[rf_path][rf0_idx] >= 0x1d)
+				rf33[rf_path][rf0_idx] = 0x1d;
+			else if (rf33[rf_path][rf0_idx] <= 0x2)
+				rf33[rf_path][rf0_idx] = 0x2;
+
+			rf33[rf_path][rf0_idx] = rf33[rf_path][rf0_idx] + ((rf0_idx - 1) * 0x4000) + (rf56_current_temp[rf_path][rf0_idx] & 0xfffe0);
+
+			RF_DBG(dm, DBG_RF_IQK,
+			       "[TGGC] rf56[%d][%d]=0x%05x rf33[%d][%d]=0x%05x\n",
+			       rf_path, rf0_idx,
+			       rf56_current_temp[rf_path][rf0_idx], rf_path,
+			       rf0_idx, rf33[rf_path][rf0_idx]);
+
+			odm_set_rf_reg(dm, rf_path, RF_0x33, bRFRegOffsetMask, rf33[rf_path][rf0_idx]);
+		}
+
+		odm_set_rf_reg(dm, rf_path, RF_0xef, bRFRegOffsetMask, 0x00000);
+	}
+}
+#endif
+
+void odm_tx_gain_gap_calibration(void *dm_void)
+{
+	PDM_ODM_T dm = (PDM_ODM_T)dm_void;
+#if (RTL8197F_SUPPORT == 1)
+	if (dm->SupportICType & ODM_RTL8197F)
+		odm_tx_gain_gap_calibration_8197f(dm_void);
+#endif
+}
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/halrf/halrf_txgapcal.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/halrf/halrf_txgapcal.h
--- linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/halrf/halrf_txgapcal.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/halrf/halrf_txgapcal.h	2020-04-10 16:35:06.821660301 +0300
@@ -0,0 +1,31 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017  Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * The full GNU General Public License is included in this distribution in the
+ * file called LICENSE.
+ *
+ * Contact Information:
+ * wlanfae <wlanfae@realtek.com>
+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
+ * Hsinchu 300, Taiwan.
+ *
+ * Larry Finger <Larry.Finger@lwfinger.net>
+ *
+ *****************************************************************************/
+
+#ifndef __HALRF_TXGAPCAL_H__
+#define __HALRF_TXGAPCAL_H__
+
+void odm_tx_gain_gap_calibration(void *dm_void);
+
+#endif /*#ifndef __HALRF_TXGAPCAL_H__*/
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/halrf/rtl8821c/halrf_8821c.c linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/halrf/rtl8821c/halrf_8821c.c
--- linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/halrf/rtl8821c/halrf_8821c.c	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/halrf/rtl8821c/halrf_8821c.c	2020-04-10 16:35:06.821660301 +0300
@@ -0,0 +1,469 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+
+#include "mp_precomp.h"
+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
+#if RT_PLATFORM == PLATFORM_MACOSX
+#include "phydm_precomp.h"
+#else
+#include "../phydm_precomp.h"
+#endif
+#else
+#include "../../phydm_precomp.h"
+#endif
+
+#if (RTL8821C_SUPPORT == 1)
+void halrf_rf_lna_setting_8821c(struct dm_struct *dm_void,
+				enum halrf_lna_set type)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	u8 path = 0x0;
+
+	if (type == HALRF_LNA_DISABLE) {
+		odm_set_rf_reg(dm, (enum rf_path)path, RF_0xef, BIT(19), 0x1);
+		odm_set_rf_reg(dm, (enum rf_path)path, RF_0x33, RFREGOFFSETMASK, 0x00003);
+		odm_set_rf_reg(dm, (enum rf_path)path, RF_0x3e, RFREGOFFSETMASK, 0x00064);
+		odm_set_rf_reg(dm, (enum rf_path)path, RF_0x3f, RFREGOFFSETMASK, 0x0afce);
+		odm_set_rf_reg(dm, (enum rf_path)path, RF_0xef, BIT(19), 0x0);
+		odm_set_rf_reg(dm, (enum rf_path)path, RF_0xee, BIT(12), 0x1);
+		odm_set_rf_reg(dm, (enum rf_path)path, RF_0x33, RFREGOFFSETMASK, 0x00003);
+		odm_set_rf_reg(dm, (enum rf_path)path, RF_0x3e, RFREGOFFSETMASK, 0x00064);
+		odm_set_rf_reg(dm, (enum rf_path)path, RF_0x3f, RFREGOFFSETMASK, 0x0280d);
+		odm_set_rf_reg(dm, (enum rf_path)path, RF_0xee, BIT(12), 0x0);
+	} else if (type == HALRF_LNA_ENABLE) {
+		odm_set_rf_reg(dm, (enum rf_path)path, RF_0xef, BIT(19), 0x1);
+		odm_set_rf_reg(dm, (enum rf_path)path, RF_0x33, RFREGOFFSETMASK, 0x00003);
+		odm_set_rf_reg(dm, (enum rf_path)path, RF_0x3e, RFREGOFFSETMASK, 0x00064);
+		odm_set_rf_reg(dm, (enum rf_path)path, RF_0x3f, RFREGOFFSETMASK, 0x1afce);
+		odm_set_rf_reg(dm, (enum rf_path)path, RF_0xef, BIT(19), 0x0);
+		odm_set_rf_reg(dm, (enum rf_path)path, RF_0xee, BIT(12), 0x1);
+		odm_set_rf_reg(dm, (enum rf_path)path, RF_0x33, RFREGOFFSETMASK, 0x00003);
+		odm_set_rf_reg(dm, (enum rf_path)path, RF_0x3e, RFREGOFFSETMASK, 0x00064);
+		odm_set_rf_reg(dm, (enum rf_path)path, RF_0x3f, RFREGOFFSETMASK, 0x0281d);
+		odm_set_rf_reg(dm, (enum rf_path)path, RF_0xee, BIT(12), 0x0);
+	}
+}
+
+boolean
+get_mix_mode_tx_agc_bbs_wing_offset_8821c(void *dm_void,
+					  enum pwrtrack_method method,
+					  u8 rf_path,
+					  u8 tx_power_index_offest_upper_bound,
+					  s8 tx_power_index_offest_lower_bound)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct dm_rf_calibration_struct *cali_info = &dm->rf_calibrate_info;
+
+	u8 bb_swing_upper_bound = cali_info->default_ofdm_index + 10;
+	u8 bb_swing_lower_bound = 0;
+
+	s8 tx_agc_index = 0;
+	u8 tx_bb_swing_index = cali_info->default_ofdm_index;
+
+	RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
+	       "Path_%d pRF->absolute_ofdm_swing_idx[rf_path]=%d, tx_power_index_offest_upper_bound=%d, tx_power_index_offest_lower_bound=%d\n",
+	       rf_path, cali_info->absolute_ofdm_swing_idx[rf_path],
+	       tx_power_index_offest_upper_bound,
+	       tx_power_index_offest_lower_bound);
+
+	if (tx_power_index_offest_upper_bound > 0XF)
+		tx_power_index_offest_upper_bound = 0XF;
+
+	if (tx_power_index_offest_lower_bound < -15)
+		tx_power_index_offest_lower_bound = -15;
+
+	if (cali_info->absolute_ofdm_swing_idx[rf_path] >= 0 && cali_info->absolute_ofdm_swing_idx[rf_path] <= tx_power_index_offest_upper_bound) {
+		tx_agc_index = cali_info->absolute_ofdm_swing_idx[rf_path];
+		tx_bb_swing_index = cali_info->default_ofdm_index;
+	} else if (cali_info->absolute_ofdm_swing_idx[rf_path] >= 0 && (cali_info->absolute_ofdm_swing_idx[rf_path] > tx_power_index_offest_upper_bound)) {
+		tx_agc_index = tx_power_index_offest_upper_bound;
+		cali_info->remnant_ofdm_swing_idx[rf_path] = cali_info->absolute_ofdm_swing_idx[rf_path] - tx_power_index_offest_upper_bound;
+		tx_bb_swing_index = cali_info->default_ofdm_index + cali_info->remnant_ofdm_swing_idx[rf_path];
+
+		if (tx_bb_swing_index > bb_swing_upper_bound)
+			tx_bb_swing_index = bb_swing_upper_bound;
+	} else if (cali_info->absolute_ofdm_swing_idx[rf_path] < 0 && (cali_info->absolute_ofdm_swing_idx[rf_path] >= tx_power_index_offest_lower_bound)) {
+		tx_agc_index = cali_info->absolute_ofdm_swing_idx[rf_path];
+		tx_bb_swing_index = cali_info->default_ofdm_index;
+	} else if (cali_info->absolute_ofdm_swing_idx[rf_path] < 0 && (cali_info->absolute_ofdm_swing_idx[rf_path] < tx_power_index_offest_lower_bound)) {
+		tx_agc_index = tx_power_index_offest_lower_bound;
+		cali_info->remnant_ofdm_swing_idx[rf_path] = cali_info->absolute_ofdm_swing_idx[rf_path] - tx_power_index_offest_lower_bound;
+
+		if (cali_info->default_ofdm_index > (cali_info->remnant_ofdm_swing_idx[rf_path] * (-1)))
+			tx_bb_swing_index = cali_info->default_ofdm_index + cali_info->remnant_ofdm_swing_idx[rf_path];
+		else
+			tx_bb_swing_index = bb_swing_lower_bound;
+	}
+
+	cali_info->absolute_ofdm_swing_idx[rf_path] = tx_agc_index;
+	cali_info->bb_swing_idx_ofdm[rf_path] = tx_bb_swing_index;
+
+	RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
+	       "MixMode Offset Path_%d   pRF->absolute_ofdm_swing_idx[rf_path]=%d   pRF->bb_swing_idx_ofdm[rf_path]=%d   TxPwrIdxOffestUpper=%d   TxPwrIdxOffestLower=%d\n",
+	       rf_path, cali_info->absolute_ofdm_swing_idx[rf_path],
+	       cali_info->bb_swing_idx_ofdm[rf_path],
+	       tx_power_index_offest_upper_bound,
+	       tx_power_index_offest_lower_bound);
+
+	return true;
+}
+
+void odm_tx_pwr_track_set_pwr8821c(void *dm_void, enum pwrtrack_method method,
+				   u8 rf_path, u8 channel_mapped_index)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
+	struct _ADAPTER *adapter = dm->adapter;
+	u8 channel = *dm->channel;
+	u8 band_width = *dm->band_width;
+#endif
+	struct dm_rf_calibration_struct *cali_info = &dm->rf_calibrate_info;
+	struct _hal_rf_ *rf = &dm->rf_table;
+	u8 tx_power_index_offest_upper_bound = 0;
+	s8 tx_power_index_offest_lower_bound = 0;
+	u8 tx_power_index = 0;
+	u8 tx_rate = 0xFF;
+
+	if (*dm->mp_mode) {
+#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
+#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
+#if (MP_DRIVER == 1)
+		PMPT_CONTEXT p_mpt_ctx = &adapter->MptCtx;
+
+		tx_rate = MptToMgntRate(p_mpt_ctx->MptRateIndex);
+#endif
+#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
+#ifdef CONFIG_MP_INCLUDED
+		PMPT_CONTEXT p_mpt_ctx = &(adapter->mppriv.mpt_ctx);
+
+		tx_rate = mpt_to_mgnt_rate(p_mpt_ctx->mpt_rate_index);
+#endif
+#endif
+#endif
+	} else {
+		u16 rate = *dm->forced_data_rate;
+
+		if (!rate) { /*auto rate*/
+#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
+			tx_rate = ((PADAPTER)adapter)->HalFunc.GetHwRateFromMRateHandler(dm->tx_rate);
+#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211)
+			tx_rate = dm->tx_rate;
+#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
+			if (dm->number_linked_client != 0)
+				tx_rate = hw_rate_to_m_rate(dm->tx_rate);
+			else
+				tx_rate = rf->p_rate_index;
+#endif
+		} else { /*force rate*/
+			tx_rate = (u8)rate;
+		}
+	}
+
+	RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "Call:%s tx_rate=0x%X\n", __func__,
+	       tx_rate);
+
+	RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
+	       "pRF->default_ofdm_index=%d   pRF->default_cck_index=%d\n",
+	       cali_info->default_ofdm_index, cali_info->default_cck_index);
+
+	RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
+	       "pRF->absolute_ofdm_swing_idx=%d   pRF->remnant_ofdm_swing_idx=%d   pRF->absolute_cck_swing_idx=%d   pRF->remnant_cck_swing_idx=%d   rf_path=%d\n",
+	       cali_info->absolute_ofdm_swing_idx[rf_path],
+	       cali_info->remnant_ofdm_swing_idx[rf_path],
+	       cali_info->absolute_cck_swing_idx[rf_path],
+	       cali_info->remnant_cck_swing_idx, rf_path);
+
+#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
+	tx_power_index = odm_get_tx_power_index(dm, (enum rf_path)rf_path, tx_rate, band_width, channel);
+#else
+	tx_power_index = config_phydm_read_txagc_8821c(dm, rf_path, 0x04); /*0x04(TX_AGC_OFDM_6M)*/
+#endif
+
+	if (tx_power_index >= 63)
+		tx_power_index = 63;
+
+	tx_power_index_offest_upper_bound = 63 - tx_power_index;
+
+	tx_power_index_offest_lower_bound = 0 - tx_power_index;
+
+	RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
+	       "tx_power_index=%d tx_power_index_offest_upper_bound=%d tx_power_index_offest_lower_bound=%d rf_path=%d\n",
+	       tx_power_index, tx_power_index_offest_upper_bound,
+	       tx_power_index_offest_lower_bound, rf_path);
+
+	if (method == BBSWING) { /*use for mp driver clean power tracking status*/
+		switch (rf_path) {
+		case RF_PATH_A:
+			odm_set_bb_reg(dm, R_0xc94, (BIT(6) | BIT(5) | BIT(4) | BIT(3) | BIT(2) | BIT(1)), ((cali_info->absolute_ofdm_swing_idx[rf_path]) & 0x3f));
+			odm_set_bb_reg(dm, REG_A_TX_SCALE_JAGUAR, 0xFFE00000, tx_scaling_table_jaguar[cali_info->bb_swing_idx_ofdm[rf_path]]);
+			break;
+
+		default:
+			break;
+		}
+
+	} else if (method == MIX_MODE) {
+		switch (rf_path) {
+		case RF_PATH_A:
+			get_mix_mode_tx_agc_bbs_wing_offset_8821c(dm, method, rf_path, tx_power_index_offest_upper_bound, tx_power_index_offest_lower_bound);
+			odm_set_bb_reg(dm, R_0xc94, (BIT(6) | BIT(5) | BIT(4) | BIT(3) | BIT(2) | BIT(1)), ((cali_info->absolute_ofdm_swing_idx[rf_path]) & 0x3f));
+			odm_set_bb_reg(dm, REG_A_TX_SCALE_JAGUAR, 0xFFE00000, tx_scaling_table_jaguar[cali_info->bb_swing_idx_ofdm[rf_path]]);
+
+			RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
+			       "TXAGC(0xC94)=0x%x BBSwing(0xc1c)=0x%x BBSwingIndex=%d rf_path=%d\n",
+			       odm_get_bb_reg(dm, R_0xc94,
+					      (BIT(6) | BIT(5) | BIT(4) |
+					       BIT(3) | BIT(2) | BIT(1))),
+			       odm_get_bb_reg(dm, R_0xc1c, 0xFFE00000),
+			       cali_info->bb_swing_idx_ofdm[rf_path], rf_path);
+			break;
+
+		default:
+			break;
+		}
+	}
+}
+
+void get_delta_swing_table_8821c(void *dm_void,
+#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
+				 u8 **temperature_up_a, u8 **temperature_down_a,
+				 u8 **temperature_up_b, u8 **temperature_down_b,
+				 u8 **temperature_up_cck_a,
+				 u8 **temperature_down_cck_a,
+				 u8 **temperature_up_cck_b,
+				 u8 **temperature_down_cck_b
+#else
+				 u8 **temperature_up_a, u8 **temperature_down_a,
+				 u8 **temperature_up_b,
+				 u8 **temperature_down_b
+#endif
+				 )
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct dm_rf_calibration_struct *cali_info = &dm->rf_calibrate_info;
+
+#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
+	u8 channel = *(dm->channel);
+#else
+	u8 channel = *dm->channel;
+#endif
+
+#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
+	*temperature_up_cck_a = cali_info->delta_swing_table_idx_2g_cck_a_p;
+	*temperature_down_cck_a = cali_info->delta_swing_table_idx_2g_cck_a_n;
+	*temperature_up_cck_b = cali_info->delta_swing_table_idx_2g_cck_b_p;
+	*temperature_down_cck_b = cali_info->delta_swing_table_idx_2g_cck_b_n;
+#endif
+
+	*temperature_up_a = cali_info->delta_swing_table_idx_2ga_p;
+	*temperature_down_a = cali_info->delta_swing_table_idx_2ga_n;
+	*temperature_up_b = cali_info->delta_swing_table_idx_2gb_p;
+	*temperature_down_b = cali_info->delta_swing_table_idx_2gb_n;
+
+	if (channel >= 36 && channel <= 64) {
+		*temperature_up_a = cali_info->delta_swing_table_idx_5ga_p[0];
+		*temperature_down_a = cali_info->delta_swing_table_idx_5ga_n[0];
+		*temperature_up_b = cali_info->delta_swing_table_idx_5gb_p[0];
+		*temperature_down_b = cali_info->delta_swing_table_idx_5gb_n[0];
+	} else if (channel >= 100 && channel <= 144) {
+		*temperature_up_a = cali_info->delta_swing_table_idx_5ga_p[1];
+		*temperature_down_a = cali_info->delta_swing_table_idx_5ga_n[1];
+		*temperature_up_b = cali_info->delta_swing_table_idx_5gb_p[1];
+		*temperature_down_b = cali_info->delta_swing_table_idx_5gb_n[1];
+	} else if (channel >= 149 && channel <= 177) {
+		*temperature_up_a = cali_info->delta_swing_table_idx_5ga_p[2];
+		*temperature_down_a = cali_info->delta_swing_table_idx_5ga_n[2];
+		*temperature_up_b = cali_info->delta_swing_table_idx_5gb_p[2];
+		*temperature_down_b = cali_info->delta_swing_table_idx_5gb_n[2];
+	}
+}
+
+void aac_check_8821c(struct dm_struct *dm)
+{
+	struct _hal_rf_ *rf = &dm->rf_table;
+	u32 temp;
+
+	if (!rf->aac_checked) {
+		RF_DBG(dm, DBG_RF_LCK, "[LCK]AAC check for 8821c\n");
+		temp = odm_get_rf_reg(dm, RF_PATH_A, 0xc9, 0xf8);
+		if (temp < 4 || temp > 7) {
+			odm_set_rf_reg(dm, RF_PATH_A, 0xca, BIT(19), 0x0);
+			odm_set_rf_reg(dm, RF_PATH_A, 0xb2, 0x7c000, 0x6);
+		}
+		rf->aac_checked = true;
+	}
+}
+
+void _phy_aac_calibrate_8821c(struct dm_struct *dm)
+{
+	u32 cnt = 0;
+
+	RF_DBG(dm, DBG_RF_IQK, "[AACK]AACK start!!!!!!!\n");
+	odm_set_rf_reg(dm, RF_PATH_A, RF_0xb8, RFREGOFFSETMASK, 0x80a00);
+	odm_set_rf_reg(dm, RF_PATH_A, RF_0xb0, RFREGOFFSETMASK, 0xff0fa);
+	ODM_delay_ms(10);
+	odm_set_rf_reg(dm, RF_PATH_A, RF_0xca, RFREGOFFSETMASK, 0x80000);
+	odm_set_rf_reg(dm, RF_PATH_A, RF_0xc9, RFREGOFFSETMASK, 0x1c141);
+	for (cnt = 0; cnt < 100; cnt++) {
+		ODM_delay_ms(1);
+		if (odm_get_rf_reg(dm, RF_PATH_A, RF_0xca, 0x1000) != 0x1)
+			break;
+	}
+
+	odm_set_rf_reg(dm, RF_PATH_A, RF_0xb0, RFREGOFFSETMASK, 0xff0f8);
+
+	RF_DBG(dm, DBG_RF_IQK, "[AACK]AACK end!!!!!!!\n");
+}
+
+void _phy_lc_calibrate_8821c(struct dm_struct *dm)
+{
+#if 1
+	aac_check_8821c(dm);
+	RF_DBG(dm, DBG_RF_IQK, "[LCK]real-time LCK!!!!!!!\n");
+	odm_set_rf_reg(dm, RF_PATH_A, RF_0xcc, RFREGOFFSETMASK, 0x2018);
+	odm_set_rf_reg(dm, RF_PATH_A, RF_0xc4, RFREGOFFSETMASK, 0x8f602);
+	odm_set_rf_reg(dm, RF_PATH_A, RF_0xcc, RFREGOFFSETMASK, 0x201c);
+#endif
+#if 0
+	u32 lc_cal = 0, cnt = 0, tmp0xc00;
+	/*RF to standby mode*/
+	tmp0xc00 = odm_read_4byte(dm, 0xc00);
+	odm_write_4byte(dm, 0xc00, 0x4);
+	odm_set_rf_reg(dm, RF_PATH_A, RF_0x0, RFREGOFFSETMASK, 0x10000);
+
+	_phy_aac_calibrate_8821c(dm);
+
+	/*backup RF0x18*/
+	lc_cal = odm_get_rf_reg(dm, RF_PATH_A, RF_CHNLBW, RFREGOFFSETMASK);
+	/*Start LCK*/
+	odm_set_rf_reg(dm, RF_PATH_A, RF_CHNLBW, RFREGOFFSETMASK, lc_cal | 0x08000);
+	ODM_delay_ms(50);
+
+	for (cnt = 0; cnt < 100; cnt++) {
+		if (odm_get_rf_reg(dm, RF_PATH_A, RF_CHNLBW, 0x8000) != 0x1)
+			break;
+		ODM_delay_ms(10);
+	}
+
+	/*Recover channel number*/
+	odm_set_rf_reg(dm, RF_PATH_A, RF_CHNLBW, RFREGOFFSETMASK, lc_cal);
+	/**restore*/
+	odm_write_4byte(dm, 0xc00, tmp0xc00);
+	odm_set_rf_reg(dm, RF_PATH_A, RF_0x0, RFREGOFFSETMASK, 0x3ffff);
+	RF_DBG(dm, DBG_RF_IQK, "[LCK]LCK end!!!!!!!\n");
+#endif
+}
+
+/*LCK:0x2*/
+/*1. add AACK check*/
+void phy_lc_calibrate_8821c(void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+
+	_phy_lc_calibrate_8821c(dm);
+}
+
+void configure_txpower_track_8821c(struct txpwrtrack_cfg *config)
+{
+	config->swing_table_size_cck = TXSCALE_TABLE_SIZE;
+	config->swing_table_size_ofdm = TXSCALE_TABLE_SIZE;
+	config->threshold_iqk = IQK_THRESHOLD;
+	config->threshold_dpk = DPK_THRESHOLD;
+	config->average_thermal_num = AVG_THERMAL_NUM_8821C;
+	config->rf_path_count = MAX_PATH_NUM_8821C;
+	config->thermal_reg_addr = RF_T_METER_8821C;
+
+	config->odm_tx_pwr_track_set_pwr = odm_tx_pwr_track_set_pwr8821c;
+	config->do_iqk = do_iqk_8821c;
+	config->phy_lc_calibrate = phy_lc_calibrate_8821c;
+
+#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
+	config->get_delta_all_swing_table = get_delta_swing_table_8821c;
+#else
+	config->get_delta_swing_table = get_delta_swing_table_8821c;
+#endif
+}
+
+#if ((DM_ODM_SUPPORT_TYPE & ODM_AP) || (DM_ODM_SUPPORT_TYPE == ODM_CE))
+void phy_set_rf_path_switch_8821c(struct dm_struct *dm,
+#else
+void phy_set_rf_path_switch_8821c(void *adapter,
+#endif
+				  boolean is_main)
+{
+#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
+	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter));
+	struct dm_struct *dm = &hal_data->DM_OutSrc;
+#endif
+#endif
+	u8 ant_num = 0; /*0: ANT_1, 1: ANT_2*/
+
+	if (is_main)
+		ant_num = SWITCH_TO_ANT1; /*Main = ANT_1*/
+	else
+		ant_num = SWITCH_TO_ANT2; /*Aux = ANT_2*/
+
+	config_phydm_set_ant_path(dm, dm->current_rf_set_8821c, ant_num);
+}
+
+
+#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
+boolean _phy_query_rf_path_switch_8821c(struct dm_struct *dm
+#else
+boolean _phy_query_rf_path_switch_8821c(void *adapter
+#endif
+				)
+{
+#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
+	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter));
+#if (DM_ODM_SUPPORT_TYPE == ODM_CE)
+	struct dm_struct *dm = &hal_data->odmpriv;
+#endif
+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
+	struct dm_struct *dm = &hal_data->DM_OutSrc;
+#endif
+#endif
+	u8 ant_num = 0; /*0: ANT_1, 1: ANT_2*/
+
+	ODM_delay_ms(300);
+
+	ant_num = query_phydm_current_ant_num_8821c(dm);
+
+	if (ant_num == SWITCH_TO_ANT1)
+		return true; /*Main = ANT_1*/
+	else
+		return false; /*Aux = ANT_2*/
+}
+
+#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
+boolean phy_query_rf_path_switch_8821c(struct dm_struct *dm
+#else
+boolean phy_query_rf_path_switch_8821c(void *adapter
+#endif
+				       )
+{
+#if DISABLE_BB_RF
+	return true;
+#endif
+
+#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
+	return _phy_query_rf_path_switch_8821c(dm);
+#else
+	return _phy_query_rf_path_switch_8821c(adapter);
+#endif
+}
+
+#endif /* (RTL8821C_SUPPORT == 0)*/
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/halrf/rtl8821c/halrf_8821c.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/halrf/rtl8821c/halrf_8821c.h
--- linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/halrf/rtl8821c/halrf_8821c.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/halrf/rtl8821c/halrf_8821c.h	2020-04-10 16:35:06.821660301 +0300
@@ -0,0 +1,60 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+
+#ifndef __HALRF_8821C_H__
+#define __HALRF_8821C_H__
+
+#define AVG_THERMAL_NUM_8821C 4
+#define RF_T_METER_8821C 0x42
+
+void configure_txpower_track_8821c(struct txpwrtrack_cfg *config);
+
+void odm_tx_pwr_track_set_pwr8821c(void *dm_void, enum pwrtrack_method method,
+				   u8 rf_path, u8 channel_mapped_index);
+
+void get_delta_swing_table_8821c(void *dm_void,
+#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
+				 u8 **temperature_up_a, u8 **temperature_down_a,
+				 u8 **temperature_up_b, u8 **temperature_down_b,
+				 u8 **temperature_up_cck_a,
+				 u8 **temperature_down_cck_a,
+				 u8 **temperature_up_cck_b,
+				 u8 **temperature_down_cck_b
+#else
+				 u8 **temperature_up_a, u8 **temperature_down_a,
+				 u8 **temperature_up_b,
+				 u8 **temperature_down_b
+#endif
+				 );
+
+void phy_lc_calibrate_8821c(void *dm_void);
+
+void halrf_rf_lna_setting_8821c(struct dm_struct *dm, enum halrf_lna_set type);
+
+#if ((DM_ODM_SUPPORT_TYPE & ODM_AP) || (DM_ODM_SUPPORT_TYPE == ODM_CE))
+void phy_set_rf_path_switch_8821c(struct dm_struct *dm,
+#else
+void phy_set_rf_path_switch_8821c(void *adapter,
+#endif
+				  boolean is_main);
+
+#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
+boolean phy_query_rf_path_switch_8821c(struct dm_struct *dm
+#else
+boolean phy_query_rf_path_switch_8821c(void *adapter
+#endif
+				       );
+
+#endif /*#ifndef __HALRF_8821C_H__*/
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/halrf/rtl8821c/halrf_iqk_8821c.c linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/halrf/rtl8821c/halrf_iqk_8821c.c
--- linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/halrf/rtl8821c/halrf_iqk_8821c.c	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/halrf/rtl8821c/halrf_iqk_8821c.c	2020-04-10 16:35:06.821660301 +0300
@@ -0,0 +1,3777 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2016 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+
+#include "mp_precomp.h"
+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
+#if RT_PLATFORM == PLATFORM_MACOSX
+#include "phydm_precomp.h"
+#else
+#include "../phydm_precomp.h"
+#endif
+#else
+#include "../../phydm_precomp.h"
+#endif
+
+#if (RTL8821C_SUPPORT == 1)
+/*---------------------------Define Local Constant---------------------------*/
+
+static u32 dpk_result[DPK_BACKUP_REG_NUM_8821C];
+static boolean txgap_done[3] = {false, false, false};
+static boolean overflowflag;
+#define dpk_forcein_sram4 1
+#define txgap_ref_index 0x0
+#define txgap_k_number 0x7
+
+/*---------------------------Define Local Constant---------------------------*/
+#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
+void do_iqk_8821c(void *dm_void, u8 delta_thermal_index, u8 thermal_value,
+		  u8 threshold)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct dm_iqk_info *iqk_info = &dm->IQK_info;
+
+	dm->rf_calibrate_info.thermal_value_iqk = thermal_value;
+	halrf_segment_iqk_trigger(dm, true, iqk_info->segment_iqk);
+}
+#else
+/*Originally config->do_iqk is hooked phy_iq_calibrate_8821c, but do_iqk_8821c and phy_iq_calibrate_8821c have different arguments*/
+void do_iqk_8821c(void *dm_void, u8 delta_thermal_index, u8 thermal_value,
+		  u8 threshold)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct dm_iqk_info *iqk_info = &dm->IQK_info;
+	/*boolean		is_recovery = (boolean) delta_thermal_index;*/
+	halrf_segment_iqk_trigger(dm, true, iqk_info->segment_iqk);
+}
+#endif
+void do_dpk_8821c(void *dm_void, u8 delta_thermal_index, u8 thermal_value,
+		  u8 threshold)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	/*boolean		is_recovery = (boolean) delta_thermal_index;*/
+	phy_dp_calibrate_8821c(dm, true);
+}
+
+boolean
+_iqk_check_nctl_done_8821c(struct dm_struct *dm, u8 path, u32 IQK_CMD)
+{
+	/*this function is only used after the version of nctl8.0*/
+	boolean notready = true;
+	boolean fail = true;
+	u32 delay_count = 0x0;
+
+	while (notready) {
+		if ((IQK_CMD & 0x00000f00) >> 8 == 0xc) {
+			if (odm_get_rf_reg(dm, path, RF_0x08, RFREGOFFSETMASK) == 0x1a3b5)
+				notready = false;
+			else
+				notready = true;
+		} else {
+			if (odm_get_rf_reg(dm, path, RF_0x08, RFREGOFFSETMASK) == 0x12345)
+				notready = false;
+			else
+				notready = true;
+		}
+		if (notready) {
+			/*ODM_sleep_ms(1);*/
+			ODM_delay_ms(1);
+			delay_count++;
+		} else {
+			fail = (boolean)odm_get_bb_reg(dm, R_0x1b08, BIT(26));
+			if (fail) {
+				RF_DBG(dm, DBG_RF_IQK,
+				       "[IQK](1)IQK_CMD =0x%x, Fail, 0x1b08=0x%x, RF08=0x%x, 1b00=0x%x,fail=0x%x, notready=0x%x!!!\n",
+				       IQK_CMD, odm_read_4byte(dm, 0x1b08),
+				       odm_get_rf_reg(dm, path, RF_0x08,
+						      RFREGOFFSETMASK),
+				       odm_read_4byte(dm, 0x1b00), fail,
+						      notready);
+			}
+			break;
+		}
+		if (delay_count >= 50) {
+			RF_DBG(dm, DBG_RF_IQK, "[IQK]S%d IQK timeout!!!\n",
+			       path);
+			break;
+		}
+	}
+	odm_set_rf_reg(dm, path, RF_0x8, RFREGOFFSETMASK, 0x0);
+
+	if (!fail) {
+		RF_DBG(dm, DBG_RF_IQK,
+		       "[IQK]IQK_CMD =0x%x, delay_count =0x%x RF0x08=0x%x, 0x1b08=0x%x,RF0xef=0x%x,RF0xdf=0x%x, !!!\n",
+		       IQK_CMD, delay_count,
+		       odm_get_rf_reg(dm, path, RF_0x8, RFREGOFFSETMASK),
+		       odm_read_4byte(dm, 0x1b08),
+		       odm_get_rf_reg(dm, path, RF_0xef, RFREGOFFSETMASK),
+		       odm_get_rf_reg(dm, path, RF_0xdf, RFREGOFFSETMASK));
+	} else {
+		RF_DBG(dm, DBG_RF_IQK,
+		       "[IQK](2)IQK_CMD =0x%x, Fail, 0x1b08=0x%x, RF08=0x%x!!!\n",
+		       IQK_CMD, odm_read_4byte(dm, 0x1b08),
+		       odm_get_rf_reg(dm, path, RF_0x08, RFREGOFFSETMASK));
+	}
+	return fail;
+}
+
+void phydm_get_read_counter_8821c(struct dm_struct *dm)
+{
+	u32 counter = 0x0;
+
+	while (1) {
+		if ((odm_get_rf_reg(dm, RF_PATH_A, RF_0x8, RFREGOFFSETMASK) == 0xabcde) || counter > 300)
+			break;
+		counter++;
+		/*ODM_sleep_ms(1);*/
+		ODM_delay_ms(1);
+	};
+	odm_set_rf_reg(dm, RF_PATH_A, RF_0x8, RFREGOFFSETMASK, 0x0);
+	RF_DBG(dm, DBG_RF_IQK, "[IQK]counter = %d\n", counter);
+}
+
+void _iqk_check_coex_status(struct dm_struct *dm, boolean beforeK)
+{
+	u8 u1b_tmp;
+	u16 count = 0;
+	u8 h2c_parameter;
+
+	h2c_parameter = 1;
+
+	if (beforeK) {
+		u1b_tmp = odm_read_1byte(dm, 0x49c);
+		RF_DBG(dm, DBG_RF_IQK,
+		       "[IQK]check 0x49c[0] = 0x%x before h2c 0x6d\n", u1b_tmp);
+
+		/*check if BT IQK */
+		u1b_tmp = odm_read_1byte(dm, 0x49c);
+		while ((u1b_tmp & BIT(1)) && (count < 100)) {
+			/*ODM_sleep_ms(10);*/
+			ODM_delay_ms(10);
+			u1b_tmp = odm_read_1byte(dm, 0x49c);
+			count++;
+			RF_DBG(dm, DBG_RF_IQK,
+			       "[IQK]check 0x49c[1]=0x%x, count = %d\n",
+			       u1b_tmp, count);
+		}
+#if 1
+		odm_fill_h2c_cmd(dm, ODM_H2C_WIFI_CALIBRATION, 1, &h2c_parameter);
+
+		u1b_tmp = odm_read_1byte(dm, 0x49c);
+		RF_DBG(dm, DBG_RF_IQK,
+		       "[IQK]check 0x49c[0] = 0x%x after h2c 0x6d\n", u1b_tmp);
+
+		u1b_tmp = odm_read_1byte(dm, 0x49c);
+		/*check if WL IQK available form WL FW */
+		while ((!(u1b_tmp & BIT(0))) && (count < 100)) {
+#if 0
+			/*ODM_sleep_ms(10);*/
+#endif
+			ODM_delay_ms(10);
+			u1b_tmp = odm_read_1byte(dm, 0x49c);
+			count++;
+			RF_DBG(dm, DBG_RF_IQK,
+			       "[IQK]check 0x49c[1]=0x%x, count = %d\n",
+			       u1b_tmp, count);
+		}
+
+		if (count >= 100)
+			RF_DBG(dm, DBG_RF_IQK,
+			       "[IQK]Polling 0x49c to 1 for WiFi calibration H2C cmd FAIL! count(%d)\n",
+			       count);
+#endif
+
+	} else {
+		odm_set_bb_reg(dm, R_0x49c, BIT(0), 0x0);
+	}
+}
+
+u32 _iqk_indirect_read_reg(struct dm_struct *dm, u16 reg_addr)
+{
+	u32 j = 0;
+
+	/*wait for ready bit before access 0x1700*/
+	odm_write_4byte(dm, 0x1700, 0x800f0000 | reg_addr);
+
+	do {
+		j++;
+	} while (((odm_read_1byte(dm, 0x1703) & BIT(5)) == 0) && (j < 30000));
+
+	return odm_read_4byte(dm, 0x1708); /*get read data*/
+}
+
+void _iqk_indirect_write_reg(struct dm_struct *dm, u16 reg_addr, u32 bit_mask,
+			     u32 reg_value)
+{
+	u32 val, i = 0, j = 0, bitpos = 0;
+
+	if (bit_mask == 0x0)
+		return;
+	if (bit_mask == 0xffffffff) {
+		odm_write_4byte(dm, 0x1704, reg_value); /*put write data*/
+
+		/*wait for ready bit before access 0x1700*/
+		do {
+			j++;
+		} while (((odm_read_1byte(dm, 0x1703) & BIT(5)) == 0) && (j < 30000));
+
+		odm_write_4byte(dm, 0x1700, 0xc00f0000 | reg_addr);
+	} else {
+		for (i = 0; i <= 31; i++) {
+			if (((bit_mask >> i) & 0x1) == 0x1) {
+				bitpos = i;
+				break;
+			}
+		}
+
+		/*read back register value before write*/
+		val = _iqk_indirect_read_reg(dm, reg_addr);
+		val = (val & (~bit_mask)) | (reg_value << bitpos);
+
+		odm_write_4byte(dm, 0x1704, val); /*put write data*/
+
+		/*wait for ready bit before access 0x1700*/
+		do {
+			j++;
+		} while (((odm_read_1byte(dm, 0x1703) & BIT(5)) == 0) && (j < 30000));
+
+		odm_write_4byte(dm, 0x1700, 0xc00f0000 | reg_addr);
+	}
+}
+
+void _iqk_set_gnt_wl_high(struct dm_struct *dm)
+{
+	u32 val = 0;
+	u8 state = 0x1, sw_control = 0x1;
+
+	/*GNT_WL = 1*/
+	val = (sw_control) ? ((state << 1) | 0x1) : 0;
+	_iqk_indirect_write_reg(dm, 0x38, 0x3000, val); /*0x38[13:12]*/
+	_iqk_indirect_write_reg(dm, 0x38, 0x0300, val); /*0x38[9:8]*/
+}
+
+void _iqk_set_gnt_bt_low(struct dm_struct *dm)
+{
+	u32 val = 0;
+	u8 state = 0x0, sw_control = 0x1;
+
+	/*GNT_BT = 0*/
+	val = (sw_control) ? ((state << 1) | 0x1) : 0;
+	_iqk_indirect_write_reg(dm, 0x38, 0xc000, val); /*0x38[15:14]*/
+	_iqk_indirect_write_reg(dm, 0x38, 0x0c00, val); /*0x38[11:10]*/
+}
+
+void _iqk_set_gnt_wl_gnt_bt(struct dm_struct *dm, boolean beforeK)
+{
+	struct dm_iqk_info *iqk_info = &dm->IQK_info;
+
+	if (beforeK) {
+		_iqk_set_gnt_wl_high(dm);
+		_iqk_set_gnt_bt_low(dm);
+	} else {
+		_iqk_indirect_write_reg(dm, 0x38, MASKDWORD, iqk_info->tmp_gntwl);
+	}
+}
+
+void _iqk_fail_count_8821c(void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct dm_iqk_info *iqk_info = &dm->IQK_info;
+	u8 i;
+
+	dm->n_iqk_cnt++;
+	if (odm_get_rf_reg(dm, RF_PATH_A, RF_0x1bf0, BIT(16)) == 1)
+		iqk_info->is_reload = true;
+	else
+		iqk_info->is_reload = false;
+
+	if (!iqk_info->is_reload) {
+		for (i = 0; i < 8; i++) {
+			if (odm_get_bb_reg(dm, R_0x1bf0, BIT(i)) == 1)
+				dm->n_iqk_fail_cnt++;
+		}
+	}
+	RF_DBG(dm, DBG_RF_IQK, "[IQK]All/Fail = %d %d\n", dm->n_iqk_cnt,
+	       dm->n_iqk_fail_cnt);
+}
+
+void _iqk_fill_iqk_report_8821c(void *dm_void, u8 channel)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct dm_iqk_info *iqk_info = &dm->IQK_info;
+	u32 tmp1 = 0x0, tmp2 = 0x0, tmp3 = 0x0;
+	u8 i;
+
+	for (i = 0; i < SS_8821C; i++) {
+		tmp1 = tmp1 + ((iqk_info->iqk_fail_report[channel][i][TX_IQK] & 0x1) << i);
+		tmp2 = tmp2 + ((iqk_info->iqk_fail_report[channel][i][RX_IQK] & 0x1) << (i + 4));
+		tmp3 = tmp3 + ((iqk_info->rxiqk_fail_code[channel][i] & 0x3) << (i * 2 + 8));
+	}
+	odm_write_4byte(dm, 0x1b00, 0xf8000008);
+	odm_set_bb_reg(dm, R_0x1bf0, 0x00ffffff, tmp1 | tmp2 | tmp3);
+
+	for (i = 0; i < SS_8821C; i++)
+		odm_write_4byte(dm, 0x1be8 + (i * 4), (iqk_info->rxiqk_agc[channel][(i * 2) + 1] << 16) | iqk_info->rxiqk_agc[channel][i * 2]);
+	RF_DBG(dm, DBG_RF_IQK, "[IQK] 0x1be8 = %x\n",
+	       odm_read_4byte(dm, 0x1be8));
+}
+
+void _iqk_iqk_fail_report_8821c(struct dm_struct *dm)
+{
+	u32 tmp1bf0 = 0x0;
+	u8 i;
+
+	tmp1bf0 = odm_read_4byte(dm, 0x1bf0);
+
+	for (i = 0; i < 4; i++) {
+		if (tmp1bf0 & (0x1 << i))
+#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
+			RF_DBG(dm, DBG_RF_IQK, "[IQK] please check S%d TXIQK\n",
+			       i);
+#else
+			panic_printk("[IQK] please check S%d TXIQK\n", i);
+#endif
+		if (tmp1bf0 & (0x1 << (i + 12)))
+#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
+			RF_DBG(dm, DBG_RF_IQK, "[IQK] please check S%d RXIQK\n",
+			       i);
+#else
+			panic_printk("[IQK] please check S%d RXIQK\n", i);
+#endif
+	}
+}
+
+void _iqk_backup_mac_bb_8821c(struct dm_struct *dm, u32 *MAC_backup,
+			      u32 *BB_backup, u32 *backup_mac_reg,
+			      u32 *backup_bb_reg, u8 num_backup_bb_reg)
+{
+	u32 i;
+
+	for (i = 0; i < MAC_REG_NUM_8821C; i++)
+		MAC_backup[i] = odm_read_4byte(dm, backup_mac_reg[i]);
+
+	for (i = 0; i < num_backup_bb_reg; i++)
+		BB_backup[i] = odm_read_4byte(dm, backup_bb_reg[i]);
+#if 0
+	/*	RF_DBG(dm, DBG_RF_IQK, "[IQK]BackupMacBB Success!!!!\n"); */
+#endif
+}
+
+void _iqk_backup_rf_8821c(struct dm_struct *dm, u32 RF_backup[][SS_8821C],
+			  u32 *backup_rf_reg)
+{
+	u32 i, j;
+
+	for (i = 0; i < RF_REG_NUM_8821C; i++)
+		for (j = 0; j < SS_8821C; j++)
+			RF_backup[i][j] = odm_get_rf_reg(dm, (u8)j, backup_rf_reg[i], RFREGOFFSETMASK);
+#if 0
+	/*	RF_DBG(dm, DBG_RF_IQK, "[IQK]BackupRF Success!!!!\n"); */
+#endif
+}
+
+void _iqk_agc_bnd_int_8821c(struct dm_struct *dm)
+{
+	/*initialize RX AGC bnd, it must do after bbreset*/
+	odm_write_4byte(dm, 0x1b00, 0xf8000008);
+	odm_write_4byte(dm, 0x1b00, 0xf80a7008);
+	odm_write_4byte(dm, 0x1b00, 0xf8015008);
+	odm_write_4byte(dm, 0x1b00, 0xf8000008);
+#if 0
+	/*RF_DBG(dm, DBG_RF_IQK, "[IQK]init. rx agc bnd\n");*/
+#endif
+}
+
+void _iqk_bb_reset_8821c(struct dm_struct *dm)
+{
+	boolean cca_ing = false;
+	u32 count = 0;
+
+	odm_set_rf_reg(dm, RF_PATH_A, RF_0x0, RFREGOFFSETMASK, 0x10000);
+	odm_set_bb_reg(dm, R_0x8f8,
+		       BIT(27) | BIT26 | BIT25 | BIT24 | BIT23 | BIT22 | BIT21 | BIT20, 0x0);
+
+	while (1) {
+		odm_write_4byte(dm, 0x8fc, 0x0);
+		odm_set_bb_reg(dm, R_0x198c, 0x7, 0x7);
+		cca_ing = (boolean)odm_get_bb_reg(dm, R_0xfa0, BIT(3));
+
+		if (count > 30)
+			cca_ing = false;
+
+		if (cca_ing) {
+			ODM_sleep_ms(1);
+			count++;
+		} else {
+			odm_write_1byte(dm, 0x808, 0x0); /*RX ant off*/
+			odm_set_bb_reg(dm, R_0xa04, BIT(27) | BIT26 | BIT25 | BIT24, 0x0); /*CCK RX path off*/
+
+			/*BBreset*/
+			odm_set_bb_reg(dm, R_0x0, BIT(16), 0x0);
+			odm_set_bb_reg(dm, R_0x0, BIT(16), 0x1);
+
+			if (odm_get_bb_reg(dm, R_0x660, BIT(16)))
+				odm_write_4byte(dm, 0x6b4, 0x89000006);
+			RF_DBG(dm, DBG_RF_IQK, "[IQK]BBreset!!!!\n");
+			break;
+		}
+	}
+}
+
+void _iqk_afe_setting_8821c(struct dm_struct *dm, boolean do_iqk)
+{
+	if (do_iqk) {
+		/*IQK AFE setting RX_WAIT_CCA mode */
+		odm_write_4byte(dm, 0xc60, 0x50000000);
+		odm_write_4byte(dm, 0xc60, 0x700F0040);
+
+		/*AFE setting*/
+		odm_write_4byte(dm, 0xc58, 0xd8000402);
+		odm_write_4byte(dm, 0xc5c, 0xd1000120);
+		odm_write_4byte(dm, 0xc6c, 0x00000a15);
+		_iqk_bb_reset_8821c(dm);
+#if 0
+		/*		RF_DBG(dm, DBG_RF_IQK, "[IQK]AFE setting for IQK mode!!!!\n"); */
+#endif
+	} else {
+		/*IQK AFE setting RX_WAIT_CCA mode */
+		odm_write_4byte(dm, 0xc60, 0x50000000);
+		odm_write_4byte(dm, 0xc60, 0x700B8040);
+
+		/*AFE setting*/
+		odm_write_4byte(dm, 0xc58, 0xd8020402);
+		odm_write_4byte(dm, 0xc5c, 0xde000120);
+		odm_write_4byte(dm, 0xc6c, 0x0000122a);
+#if 0
+		/*		RF_DBG(dm, DBG_RF_IQK, "[IQK]AFE setting for Normal mode!!!!\n"); */
+#endif
+	}
+	/*0x9a4[31]=0: Select da clock*/
+	odm_set_bb_reg(dm, R_0x9a4, BIT(31), 0x0);
+}
+
+void _iqk_restore_mac_bb_8821c(struct dm_struct *dm, u32 *MAC_backup,
+			       u32 *BB_backup, u32 *backup_mac_reg,
+			       u32 *backup_bb_reg, u8 num_backup_bb_reg)
+{
+	u32 i;
+
+	for (i = 0; i < MAC_REG_NUM_8821C; i++)
+		odm_write_4byte(dm, backup_mac_reg[i], MAC_backup[i]);
+	for (i = 0; i < num_backup_bb_reg; i++)
+		odm_write_4byte(dm, backup_bb_reg[i], BB_backup[i]);
+#if 0
+	/*	RF_DBG(dm, DBG_RF_IQK, "[IQK]RestoreMacBB Success!!!!\n"); */
+#endif
+}
+
+void _iqk_restore_rf_8821c(struct dm_struct *dm, u32 *backup_rf_reg,
+			   u32 RF_backup[][SS_8821C])
+{
+	u32 i;
+
+	odm_set_rf_reg(dm, RF_PATH_A, RF_0xef, RFREGOFFSETMASK, 0x0);
+	odm_set_rf_reg(dm, RF_PATH_A, RF_0xee, RFREGOFFSETMASK, 0x0);
+	odm_set_rf_reg(dm, RF_PATH_A, RF_0xdf, RFREGOFFSETMASK, RF_backup[0][RF_PATH_A] & (~BIT(4)));
+#if 0
+	/*odm_set_rf_reg(dm, RF_PATH_A, RF_0xde, RFREGOFFSETMASK, RF_backup[1][RF_PATH_A]|BIT(4));*/
+#endif
+	odm_set_rf_reg(dm, RF_PATH_A, RF_0xde, RFREGOFFSETMASK, RF_backup[1][RF_PATH_A] & (~BIT(4)));
+
+	for (i = 2; i < (RF_REG_NUM_8821C - 1); i++)
+		odm_set_rf_reg(dm, RF_PATH_A, backup_rf_reg[i], RFREGOFFSETMASK, RF_backup[i][RF_PATH_A]);
+
+	odm_set_rf_reg(dm, RF_PATH_A, RF_0x1, RFREGOFFSETMASK, (RF_backup[4][RF_PATH_A] & (~BIT(0))));
+#if 0
+	/*RF_DBG(dm, DBG_RF_IQK, "[IQK]RestoreRF Success!!!!\n"); */
+#endif
+}
+
+void _iqk_backup_iqk_8821c(struct dm_struct *dm, u8 step, u8 path)
+{
+	struct dm_iqk_info *iqk_info = &dm->IQK_info;
+	u8 i, j, k;
+#if 0
+	/*u16		iqk_apply[2] = {0xc94, 0xe94};*/
+#endif
+
+	switch (step) {
+	case 0:
+		iqk_info->iqk_channel[1] = iqk_info->iqk_channel[0];
+		for (i = 0; i < SS_8821C; i++) {
+			iqk_info->lok_idac[1][i] = iqk_info->lok_idac[0][i];
+			iqk_info->rxiqk_agc[1][i] = iqk_info->rxiqk_agc[0][i];
+			iqk_info->bypass_iqk[1][i] = iqk_info->bypass_iqk[0][i];
+			iqk_info->rxiqk_fail_code[1][i] = iqk_info->rxiqk_fail_code[0][i];
+			for (j = 0; j < 2; j++) {
+				iqk_info->iqk_fail_report[1][i][j] = iqk_info->iqk_fail_report[0][i][j];
+				for (k = 0; k < 8; k++) {
+					iqk_info->iqk_cfir_real[1][i][j][k] = iqk_info->iqk_cfir_real[0][i][j][k];
+					iqk_info->iqk_cfir_imag[1][i][j][k] = iqk_info->iqk_cfir_imag[0][i][j][k];
+				}
+			}
+		}
+		for (i = 0; i < 4; i++) {
+			iqk_info->rxiqk_fail_code[0][i] = 0x0;
+			iqk_info->rxiqk_agc[0][i] = 0x0;
+			for (j = 0; j < 2; j++) {
+				iqk_info->iqk_fail_report[0][i][j] = true;
+				iqk_info->gs_retry_count[0][i][j] = 0x0;
+			}
+			for (j = 0; j < 3; j++)
+				iqk_info->retry_count[0][i][j] = 0x0;
+		}
+		/*backup channel*/
+		iqk_info->iqk_channel[0] = iqk_info->rf_reg18;
+		break;
+	case 1: /*LOK backup*/
+		iqk_info->lok_idac[0][path] = odm_get_rf_reg(dm, (enum rf_path)path, RF_0x58, RFREGOFFSETMASK);
+		break;
+	case 2: /*TXIQK backup*/
+	case 3: /*RXIQK backup*/
+		phydm_get_iqk_cfir(dm, (step - 2), path, false);
+		break;
+	}
+}
+
+void _iqk_reload_iqk_setting_8821c(struct dm_struct *dm, u8 channel,
+				   u8 reload_idx
+				   /*1: reload TX, 2: reload TX, RX*/)
+{
+	struct dm_iqk_info *iqk_info = &dm->IQK_info;
+	u8 i, path, idx;
+	u16 iqk_apply[2] = {0xc94, 0xe94};
+
+	for (path = 0; path < SS_8821C; path++) {
+#if 0
+		if (reload_idx == 2) {
+			odm_set_rf_reg(dm, (enum rf_path)path, RF_0xdf, BIT(4), 0x1);
+			odm_set_rf_reg(dm, (enum rf_path)path, RF_0x58, RFREGOFFSETMASK, iqk_info->lok_idac[channel][path]);
+		}
+#endif
+		for (idx = 0; idx < reload_idx; idx++) {
+			odm_set_bb_reg(dm, R_0x1b00, MASKDWORD, 0xf8000008 | path << 1);
+			odm_set_bb_reg(dm, R_0x1b2c, MASKDWORD, 0x7);
+			odm_set_bb_reg(dm, R_0x1b38, MASKDWORD, 0x20000000);
+			odm_set_bb_reg(dm, R_0x1b3c, MASKDWORD, 0x20000000);
+			odm_set_bb_reg(dm, R_0x1bcc, MASKDWORD, 0x00000000);
+			if (idx == 0)
+				odm_set_bb_reg(dm, R_0x1b0c, BIT(13) | BIT(12), 0x3);
+			else
+				odm_set_bb_reg(dm, R_0x1b0c, BIT(13) | BIT(12), 0x1);
+			odm_set_bb_reg(dm, R_0x1bd4, BIT(20) | BIT(19) | BIT(18) | BIT(17) | BIT(16), 0x10);
+			for (i = 0; i < 8; i++) {
+				odm_write_4byte(dm, 0x1bd8, ((0xc0000000 >> idx) + 0x3) + (i * 4) + (iqk_info->iqk_cfir_real[channel][path][idx][i] << 9));
+				odm_write_4byte(dm, 0x1bd8, ((0xc0000000 >> idx) + 0x1) + (i * 4) + (iqk_info->iqk_cfir_imag[channel][path][idx][i] << 9));
+			}
+			if (idx == 0)
+				odm_set_bb_reg(dm, iqk_apply[path], BIT(0), ~(u32)(iqk_info->iqk_fail_report[channel][path][idx]));
+			else
+				odm_set_bb_reg(dm, iqk_apply[path], BIT(10), ~(u32)(iqk_info->iqk_fail_report[channel][path][idx]));
+		}
+		odm_set_bb_reg(dm, R_0x1bd8, MASKDWORD, 0x0);
+		odm_set_bb_reg(dm, R_0x1b0c, BIT(13) | BIT(12), 0x0);
+	}
+}
+
+boolean
+_iqk_reload_iqk_8821c(struct dm_struct *dm, boolean reset)
+{
+	struct dm_iqk_info *iqk_info = &dm->IQK_info;
+	u8 i;
+	iqk_info->is_reload = false;
+	odm_set_bb_reg(dm, R_0x1bf0, BIT(16), 0x0); /*clear the reload flag*/
+
+	if (reset) {
+		for (i = 0; i < SS_8821C; i++)
+			iqk_info->iqk_channel[i] = 0x0;
+	} else {
+		iqk_info->rf_reg18 = odm_get_rf_reg(dm, RF_PATH_A, RF_0x18, RFREGOFFSETMASK);
+
+		for (i = 0; i < SS_8821C; i++) {
+			if (iqk_info->rf_reg18 == iqk_info->iqk_channel[i]) {
+				_iqk_reload_iqk_setting_8821c(dm, i, 2);
+				_iqk_fill_iqk_report_8821c(dm, i);
+				RF_DBG(dm, DBG_RF_IQK,
+				       "[IQK]reload IQK result before!!!!\n");
+				odm_set_bb_reg(dm, R_0x1bf0, BIT(16), 0x1);
+				iqk_info->is_reload = true;
+			}
+		}
+	}
+
+	return iqk_info->is_reload;
+}
+
+void _iqk_rfe_setting_8821c(struct dm_struct *dm, boolean ext_pa_on)
+{
+	if (ext_pa_on) {
+		/*RFE setting*/
+		odm_write_4byte(dm, 0xcb0, 0x77777777);
+		odm_write_4byte(dm, 0xcb4, 0x00007777);
+		odm_write_4byte(dm, 0xcbc, 0x0000083B);
+#if 0
+		/*odm_write_4byte(dm, 0x1990, 0x00000c30);*/
+#endif
+		RF_DBG(dm, DBG_RF_IQK, "[IQK]external PA on!!!!\n");
+	} else {
+		/*RFE setting*/
+		odm_write_4byte(dm, 0xcb0, 0x77171117);
+		odm_write_4byte(dm, 0xcb4, 0x00001177);
+		odm_write_4byte(dm, 0xcbc, 0x00000404);
+#if 0
+		/*odm_write_4byte(dm, 0x1990, 0x00000c30);*/
+#endif
+		RF_DBG(dm, DBG_RF_IQK, "[IQK]external PA off!!!!\n");
+	}
+}
+
+void _iqk_rfsetting_8821c(struct dm_struct *dm)
+{
+	struct dm_iqk_info *iqk_info = &dm->IQK_info;
+
+	u8 path;
+	u32 tmp;
+
+	odm_write_4byte(dm, 0x1b00, 0xf8000008);
+	odm_write_4byte(dm, 0x1bb8, 0x00000000);
+
+	for (path = 0; path < SS_8821C; path++) {
+		/*0xdf:B11 = 1,B4 = 0, B1 = 1*/
+		tmp = odm_get_rf_reg(dm, (enum rf_path)path, RF_0xdf, RFREGOFFSETMASK);
+		tmp = (tmp & (~BIT(4))) | BIT(1) | BIT(11);
+		odm_set_rf_reg(dm, (enum rf_path)path, RF_0xdf, RFREGOFFSETMASK, tmp);
+
+		if (iqk_info->is_btg) {
+			tmp = odm_get_rf_reg(dm, RF_PATH_A, RF_0xde, RFREGOFFSETMASK);
+			tmp = (tmp & (~BIT(4))) | BIT(15);
+#if 0
+			/*tmp = tmp|BIT(4)|BIT(15); //manual LOK value  for A-cut*/
+#endif
+			odm_set_rf_reg(dm, RF_PATH_A, RF_0xde, RFREGOFFSETMASK, tmp);
+		}
+
+		if (!iqk_info->is_btg) {
+			/*WLAN_AG*/
+			/*TX IQK	 mode init*/
+			odm_set_rf_reg(dm, (enum rf_path)path, RF_0xef, RFREGOFFSETMASK, 0x80000);
+			odm_set_rf_reg(dm, (enum rf_path)path, RF_0x33, RFREGOFFSETMASK, 0x00024);
+			odm_set_rf_reg(dm, (enum rf_path)path, RF_0x3e, RFREGOFFSETMASK, 0x0003f);
+#if 0
+			/*odm_set_rf_reg(dm, (enum rf_path)path, RF_0x3f, RFREGOFFSETMASK, 0x60fde);*/
+#endif
+			odm_set_rf_reg(dm, (enum rf_path)path, RF_0x3f, RFREGOFFSETMASK, 0xe0fde);
+			odm_set_rf_reg(dm, (enum rf_path)path, RF_0xef, RFREGOFFSETMASK, 0x00000);
+			if (*dm->band_type == ODM_BAND_5G) {
+				odm_set_rf_reg(dm, (enum rf_path)path, RF_0xef, BIT(19), 0x1);
+				odm_set_rf_reg(dm, (enum rf_path)path, RF_0x33, RFREGOFFSETMASK, 0x00026);
+				odm_set_rf_reg(dm, (enum rf_path)path, RF_0x3e, RFREGOFFSETMASK, 0x00037);
+				odm_set_rf_reg(dm, (enum rf_path)path, RF_0x3f, RFREGOFFSETMASK, 0xdefce);
+				odm_set_rf_reg(dm, (enum rf_path)path, RF_0xef, BIT(19), 0x0);
+			} else {
+				odm_set_rf_reg(dm, (enum rf_path)path, RF_0xef, BIT(19), 0x1);
+				odm_set_rf_reg(dm, (enum rf_path)path, RF_0x33, RFREGOFFSETMASK, 0x00026);
+				odm_set_rf_reg(dm, (enum rf_path)path, RF_0x3e, RFREGOFFSETMASK, 0x00037);
+				odm_set_rf_reg(dm, (enum rf_path)path, RF_0x3f, RFREGOFFSETMASK, 0x5efce);
+				odm_set_rf_reg(dm, (enum rf_path)path, RF_0xef, BIT(19), 0x0);
+			}
+		} else {
+			/*WLAN_BTG*/
+			/*TX IQK	 mode init*/
+			odm_set_rf_reg(dm, (enum rf_path)path, RF_0xee, RFREGOFFSETMASK, 0x01000);
+			odm_set_rf_reg(dm, (enum rf_path)path, RF_0x33, RFREGOFFSETMASK, 0x00004);
+			odm_set_rf_reg(dm, (enum rf_path)path, RF_0x3f, RFREGOFFSETMASK, 0x01ec1);
+			odm_set_rf_reg(dm, (enum rf_path)path, RF_0xee, RFREGOFFSETMASK, 0x00000);
+		}
+	}
+}
+
+void _iqk_configure_macbb_8821c(struct dm_struct *dm)
+{
+	/*MACBB register setting*/
+	odm_write_1byte(dm, 0x522, 0x7f);
+	odm_set_bb_reg(dm, R_0x1518, BIT(16), 0x1);
+	odm_set_bb_reg(dm, R_0x550, BIT(11) | BIT(3), 0x0);
+	odm_set_bb_reg(dm, R_0x90c, BIT(15), 0x1); /*0x90c[15]=1: dac_buf reset selection*/
+
+	/*0xc94[0]=1, 0xe94[0]=1: Let tx from IQK*/
+	odm_set_bb_reg(dm, R_0xc94, BIT(0), 0x1);
+	odm_set_bb_reg(dm, R_0xc94, (BIT(11) | BIT(10)), 0x1);
+	/* 3-wire off*/
+	odm_write_4byte(dm, 0xc00, 0x00000004);
+	/*disable PMAC*/
+	odm_set_bb_reg(dm, R_0xb00, BIT(8), 0x0);
+#if 0
+	/*	RF_DBG(dm, DBG_RF_IQK, "[IQK]Set MACBB setting for IQK!!!!\n");*/
+#endif
+	/*disable CCK block*/
+	odm_set_bb_reg(dm, R_0x808, BIT(28), 0x0);
+	/*disable OFDM CCA*/
+	odm_set_bb_reg(dm, R_0x838, BIT(3) | BIT(2) | BIT(1), 0x7);
+
+}
+
+void _iqk_lok_setting_8821c(struct dm_struct *dm, u8 path, u8 pad_index)
+{
+	u32 LOK0x56_2G = 0x50ef3;
+	u32 LOK0x56_5G = 0x50ee8;
+	u32 LOK0x33 = 0;
+	u32 LOK0x78 = 0xbcbba;
+	u32 tmp = 0;
+
+	struct dm_iqk_info *iqk_info = &dm->IQK_info;
+
+	LOK0x33 = pad_index;
+	/*add delay of MAC send packet*/
+
+	if (*dm->mp_mode)
+		odm_set_bb_reg(dm, R_0x810, BIT(7) | BIT(6) | BIT(5) | BIT(4), 0x8);
+
+	if (iqk_info->is_btg) {
+		tmp = (LOK0x78 & 0x1c000) >> 14;
+		odm_write_4byte(dm, 0x1b00, 0xf8000008 | path << 1);
+		odm_write_4byte(dm, 0x1bcc, 0x1b);
+		odm_write_1byte(dm, 0x1b23, 0x00);
+		odm_write_1byte(dm, 0x1b2b, 0x80);
+		/*0x78[11:0] = IDAC value*/
+		LOK0x78 = LOK0x78 & (0xe3fff | ((u32)pad_index << 14));
+		odm_set_rf_reg(dm, path, RF_0x78, RFREGOFFSETMASK, LOK0x78);
+		odm_set_rf_reg(dm, path, RF_0x5c, RFREGOFFSETMASK, 0x05320);
+		odm_set_rf_reg(dm, path, RF_0x8f, RFREGOFFSETMASK, 0xac018);
+		odm_set_rf_reg(dm, RF_PATH_A, RF_0xee, BIT(4), 0x1);
+		odm_set_rf_reg(dm, RF_PATH_A, RF_0x33, BIT(3), 0x0);
+		RF_DBG(dm, DBG_RF_IQK, "[IQK] In the BTG\n");
+	} else {
+		/*tmp = (LOK0x56 & 0xe0) >> 5;*/
+		odm_write_4byte(dm, 0x1b00, 0xf8000008 | path << 1);
+		odm_write_4byte(dm, 0x1bcc, 0x9);
+		odm_write_1byte(dm, 0x1b23, 0x00);
+
+		switch (*dm->band_type) {
+		case ODM_BAND_2_4G:
+			odm_write_1byte(dm, 0x1b2b, 0x00);
+			LOK0x56_2G = LOK0x56_2G & (0xfff1f | ((u32)pad_index << 5));
+			odm_set_rf_reg(dm, path, RF_0x56, RFREGOFFSETMASK, LOK0x56_2G);
+			odm_set_rf_reg(dm, path, RF_0x8f, RFREGOFFSETMASK, 0xadc18);
+			odm_set_rf_reg(dm, RF_PATH_A, RF_0xef, BIT(4), 0x1);
+			odm_set_rf_reg(dm, RF_PATH_A, RF_0x33, BIT(3), 0x0);
+			break;
+		case ODM_BAND_5G:
+			odm_write_1byte(dm, 0x1b2b, 0x00);
+			LOK0x56_5G = LOK0x56_5G & (0xfff1f | ((u32)pad_index << 5));
+			odm_set_rf_reg(dm, path, RF_0x56, RFREGOFFSETMASK, LOK0x56_5G);
+			odm_set_rf_reg(dm, path, RF_0x8f, RFREGOFFSETMASK, 0xadc18);
+			odm_set_rf_reg(dm, RF_PATH_A, RF_0xef, BIT(4), 0x1);
+			odm_set_rf_reg(dm, RF_PATH_A, RF_0x33, BIT(3), 0x1);
+			break;
+		}
+	}
+	/*for IDAC LUT by PAD idx*/
+	odm_set_rf_reg(dm, path, RF_0x33, BIT(2) | BIT(1) | BIT(0), LOK0x33);
+#if 0
+	/*	RF_DBG(dm, DBG_RF_IQK, "[IQK]Set LOK setting!!!!\n");*/
+#endif
+}
+
+void _iqk_txk_setting_8821c(struct dm_struct *dm, u8 path)
+{
+	struct dm_iqk_info *iqk_info = &dm->IQK_info;
+
+	if (iqk_info->is_btg) {
+		odm_write_4byte(dm, 0x1b00, 0xf8000008 | path << 1);
+		odm_write_4byte(dm, 0x1bcc, 0x1b);
+		odm_write_4byte(dm, 0x1b20, 0x00840008);
+
+		/*0x78[11:0] = IDAC value*/
+		odm_set_rf_reg(dm, path, RF_0x78, RFREGOFFSETMASK, 0xbcbba);
+		odm_set_rf_reg(dm, path, RF_0x5c, RFREGOFFSETMASK, 0x04320);
+		odm_set_rf_reg(dm, path, RF_0x8f, RFREGOFFSETMASK, 0xac018);
+		odm_write_1byte(dm, 0x1b2b, 0x80);
+	} else {
+		odm_write_4byte(dm, 0x1b00, 0xf8000008 | path << 1);
+		odm_write_4byte(dm, 0x1bcc, 0x9);
+		odm_write_4byte(dm, 0x1b20, 0x01440008);
+
+		switch (*dm->band_type) {
+		case ODM_BAND_2_4G:
+			odm_set_rf_reg(dm, path, RF_0x56, RFREGOFFSETMASK, 0x50EF3);
+			odm_set_rf_reg(dm, path, RF_0x8f, RFREGOFFSETMASK, 0xadc18);
+			odm_write_1byte(dm, 0x1b2b, 0x00);
+			break;
+		case ODM_BAND_5G:
+#if 0
+			/*odm_set_rf_reg(dm, path, RF_0x56, RFREGOFFSETMASK, 0x50EF0);*/
+			/*odm_set_rf_reg(dm, path, RF_0x56, RFREGOFFSETMASK, 0x50Ec8);*/
+#endif
+			odm_set_rf_reg(dm, path, RF_0x56, RFREGOFFSETMASK, 0x5004e);
+			odm_set_rf_reg(dm, path, RF_0x8f, RFREGOFFSETMASK, 0xa9c18);
+			odm_write_1byte(dm, 0x1b2b, 0x00);
+			break;
+		}
+	}
+#if 0
+	/*	RF_DBG(dm, DBG_RF_IQK, "[IQK]Set TXK setting!!!!\n");*/
+#endif
+}
+
+void _iqk_rxk1setting_8821c(struct dm_struct *dm, u8 path)
+{
+	struct dm_iqk_info *iqk_info = &dm->IQK_info;
+
+	if (iqk_info->is_btg) {
+		odm_write_4byte(dm, 0x1b00, 0xf8000008 | path << 1);
+		odm_write_1byte(dm, 0x1b2b, 0x80);
+		odm_write_4byte(dm, 0x1bcc, 0x09);
+		odm_write_4byte(dm, 0x1b20, 0x01450008);
+		odm_write_4byte(dm, 0x1b24, 0x01460c88);
+
+		/*0x78[11:0] = IDAC value*/
+		odm_set_rf_reg(dm, path, RF_0x78, RFREGOFFSETMASK, 0x8cbba);
+		odm_set_rf_reg(dm, path, RF_0x5c, RFREGOFFSETMASK, 0x00320);
+		odm_set_rf_reg(dm, path, RF_0x8f, RFREGOFFSETMASK, 0xa8018);
+	} else {
+		odm_write_4byte(dm, 0x1b00, 0xf8000008 | path << 1);
+		switch (*dm->band_type) {
+		case ODM_BAND_2_4G:
+			odm_write_1byte(dm, 0x1bcc, 0x12);
+			odm_write_1byte(dm, 0x1b2b, 0x00);
+			odm_write_4byte(dm, 0x1b20, 0x01450008);
+			odm_write_4byte(dm, 0x1b24, 0x01461068);
+
+			odm_set_rf_reg(dm, path, RF_0x56, RFREGOFFSETMASK, 0x510f3);
+			odm_set_rf_reg(dm, path, RF_0x8f, RFREGOFFSETMASK, 0xa9c00);
+			break;
+		case ODM_BAND_5G:
+			odm_write_1byte(dm, 0x1bcc, 0x9);
+			odm_write_1byte(dm, 0x1b2b, 0x00);
+			odm_write_4byte(dm, 0x1b20, 0x00450008);
+			odm_write_4byte(dm, 0x1b24, 0x00461468);
+
+			odm_set_rf_reg(dm, path, RF_0x56, RFREGOFFSETMASK, 0x510f3);
+			odm_set_rf_reg(dm, path, RF_0x8f, RFREGOFFSETMASK, 0xa9c00);
+			break;
+		}
+	}
+#if 0
+	/*RF_DBG(dm, DBG_RF_IQK, "[IQK]Set RXK setting!!!!\n");*/
+#endif
+}
+
+static u8 btg_lna[5] = {0x0, 0x4, 0x8, 0xc, 0xf};
+static u8 wlg_lna[5] = {0x0, 0x1, 0x2, 0x3, 0x5};
+static u8 wla_lna[5] = {0x0, 0x1, 0x3, 0x4, 0x5};
+
+void _iqk_rxk2setting_8821c(struct dm_struct *dm, u8 path, boolean is_gs)
+{
+	struct dm_iqk_info *iqk_info = &dm->IQK_info;
+
+	if (iqk_info->is_btg) {
+		if (is_gs) {
+			iqk_info->tmp1bcc = 0x1b;
+			iqk_info->lna_idx = 2;
+		}
+		odm_write_4byte(dm, 0x1b00, 0xf8000008 | path << 1);
+		odm_write_1byte(dm, 0x1b2b, 0x80);
+		odm_write_4byte(dm, 0x1bcc, iqk_info->tmp1bcc);
+		odm_write_4byte(dm, 0x1b20, 0x01450008);
+		odm_write_4byte(dm, 0x1b24, (0x01460048 | (btg_lna[iqk_info->lna_idx] << 10)));
+		/*0x78[11:0] = IDAC value*/
+		odm_set_rf_reg(dm, path, RF_0x78, RFREGOFFSETMASK, 0x8cbba);
+		odm_set_rf_reg(dm, path, RF_0x5c, RFREGOFFSETMASK, 0x00320);
+		odm_set_rf_reg(dm, path, RF_0x8f, RFREGOFFSETMASK, 0xa8018);
+	} else {
+		odm_write_4byte(dm, 0x1b00, 0xf8000008 | path << 1);
+		switch (*dm->band_type) {
+		case ODM_BAND_2_4G:
+			if (is_gs) {
+				iqk_info->tmp1bcc = 0x12;
+				iqk_info->lna_idx = 2;
+			}
+			odm_write_1byte(dm, 0x1bcc, iqk_info->tmp1bcc);
+			odm_write_1byte(dm, 0x1b2b, 0x00);
+			odm_write_4byte(dm, 0x1b20, 0x01450008);
+			odm_write_4byte(dm, 0x1b24, (0x01460048 | (wlg_lna[iqk_info->lna_idx] << 10)));
+			odm_set_rf_reg(dm, path, RF_0x56, RFREGOFFSETMASK, 0x510f3);
+			odm_set_rf_reg(dm, path, RF_0x8f, RFREGOFFSETMASK, 0xa9c00);
+			break;
+		case ODM_BAND_5G:
+			if (is_gs) {
+				/*iqk_info->tmp1bcc = 0x12;*/
+				iqk_info->tmp1bcc = 0x09;
+				iqk_info->lna_idx = 2;
+			}
+			odm_write_1byte(dm, 0x1bcc, iqk_info->tmp1bcc);
+			odm_write_1byte(dm, 0x1b2b, 0x00);
+			odm_write_4byte(dm, 0x1b20, 0x00450008);
+			odm_write_4byte(dm, 0x1b24, (0x01460048 | (wla_lna[iqk_info->lna_idx] << 10)));
+#if 0
+			/*odm_set_rf_reg(dm, path, RF_0x56, RFREGOFFSETMASK, 0x51000);*/
+#endif
+			odm_set_rf_reg(dm, path, RF_0x56, RFREGOFFSETMASK, 0x51060);
+			odm_set_rf_reg(dm, path, RF_0x8f, RFREGOFFSETMASK, 0xa9c00);
+			break;
+		}
+	}
+#if 0
+	/*	RF_DBG(dm, DBG_RF_IQK, "[IQK]Set RXK setting!!!!\n");*/
+#endif
+}
+
+boolean
+_iqk_check_cal_8821c(struct dm_struct *dm, u32 IQK_CMD)
+{
+	boolean notready = true, fail = true;
+	u32 delay_count = 0x0;
+
+	while (notready) {
+		if (odm_read_4byte(dm, 0x1b00) == (IQK_CMD & 0xffffff0f)) {
+			fail = (boolean)odm_get_bb_reg(dm, R_0x1b08, BIT(26));
+			notready = false;
+		} else {
+#if 0
+			/*ODM_sleep_ms(1);*/
+#endif
+			ODM_delay_ms(1);
+			delay_count++;
+		}
+
+		if (delay_count >= 50) {
+			fail = true;
+			RF_DBG(dm, DBG_RF_IQK, "[IQK]IQK timeout!!!\n");
+			break;
+		}
+	}
+#if 0
+	/*
+	RF_DBG(dm, DBG_RF_IQK,
+		     "[IQK]delay count = 0x%x!!!\n", delay_count);
+*/
+#endif
+	return fail;
+}
+
+boolean
+_iqk_rx_iqk_gain_search_fail_8821c(struct dm_struct *dm, u8 path, u8 step)
+{
+	struct dm_iqk_info *iqk_info = &dm->IQK_info;
+	boolean fail = true;
+	u32 IQK_CMD = 0x0, rf_reg0, tmp, rxbb;
+	u8 IQMUX[4] = {0x9, 0x12, 0x1b, 0x24}, *plna;
+	u8 idx;
+	/*u8	lna_setting[5];*/
+
+	if (iqk_info->is_btg)
+		plna = btg_lna;
+	else if (*dm->band_type == ODM_BAND_2_4G)
+		plna = wlg_lna;
+	else
+		plna = wla_lna;
+
+	for (idx = 0; idx < 4; idx++)
+		if (iqk_info->tmp1bcc == IQMUX[idx])
+			break;
+
+	odm_write_4byte(dm, 0x1b00, 0xf8000008 | path << 1);
+	odm_write_4byte(dm, 0x1bcc, iqk_info->tmp1bcc);
+
+	if (step == RXIQK1)
+		RF_DBG(dm, DBG_RF_IQK,
+		       "[IQK]============ S%d RXIQK GainSearch ============\n",
+		       iqk_info->is_btg);
+
+	if (step == RXIQK1)
+		IQK_CMD = 0xf8000208 | (1 << (path + 4));
+	else
+		IQK_CMD = 0xf8000308 | (1 << (path + 4));
+
+	RF_DBG(dm, DBG_RF_IQK, "[IQK]S%d GS%d_Trigger = 0x%x\n", path, step,
+	       IQK_CMD);
+
+	_iqk_set_gnt_wl_gnt_bt(dm, true);
+	odm_write_4byte(dm, 0x1b00, IQK_CMD);
+	odm_write_4byte(dm, 0x1b00, IQK_CMD + 0x1);
+#if 0
+	/*ODM_sleep_ms(GS_delay_8821C);*/
+#endif
+	ODM_delay_ms(GS_delay_8821C);
+	fail = _iqk_check_cal_8821c(dm, IQK_CMD);
+	RF_DBG(dm, DBG_RF_IQK, "[IQK]check 0x49c = %x\n",
+	       odm_read_1byte(dm, 0x49c));
+	_iqk_set_gnt_wl_gnt_bt(dm, false);
+
+	if (step == RXIQK2) {
+		rf_reg0 = odm_get_rf_reg(dm, (enum rf_path)path, RF_0x0, RFREGOFFSETMASK);
+		odm_write_4byte(dm, 0x1b00, 0xf8000008 | path << 1);
+		RF_DBG(dm, DBG_RF_IQK,
+		       "[IQK]S%d ==> RF0x0 = 0x%x, tmp1bcc = 0x%x, idx = %d, 0x1b3c = 0x%x\n",
+		       path, rf_reg0, iqk_info->tmp1bcc, idx,
+		       odm_read_4byte(dm, 0x1b3c));
+		tmp = (rf_reg0 & 0x1fe0) >> 5;
+		rxbb = tmp & 0x1f;
+#if 1
+
+		if (rxbb == 0x1) {
+			if (idx != 3)
+				idx++;
+			else if (iqk_info->lna_idx != 0x0)
+				iqk_info->lna_idx--;
+			else
+				iqk_info->isbnd = true;
+			fail = true;
+		} else if (rxbb == 0xa) {
+			if (idx != 0)
+				idx--;
+			else if (iqk_info->lna_idx != 0x4)
+				iqk_info->lna_idx++;
+			else
+				iqk_info->isbnd = true;
+			fail = true;
+		} else {
+			fail = false;
+		}
+
+		if (iqk_info->isbnd)
+			fail = false;
+#endif
+
+#if 0
+		if (rxbb == 0x1) {
+			if (iqk_info->lna_idx != 0x0)
+				iqk_info->lna_idx--;
+			else if (idx != 3)
+				idx++;
+			else
+				iqk_info->isbnd = true;
+			fail = true;
+		} else if (rxbb == 0xa) {
+			if (idx != 0)
+				idx--;
+			else if (iqk_info->lna_idx != 0x7)
+				iqk_info->lna_idx++;
+			else
+				iqk_info->isbnd = true;
+			fail = true;
+		} else
+			fail = false;
+
+		if (iqk_info->isbnd == true)
+			fail = false;
+#endif
+		iqk_info->tmp1bcc = IQMUX[idx];
+
+		if (fail) {
+			odm_write_4byte(dm, 0x1b00, 0xf8000008 | path << 1);
+			odm_write_4byte(dm, 0x1b24, (odm_read_4byte(dm, 0x1b24) & 0xffffc3ff) | (*(plna + iqk_info->lna_idx) << 10));
+		}
+	}
+	return fail;
+}
+void _iqk_rxk2setting_by_toneindex_8821c(struct dm_struct *dm, u8 path,
+					 boolean is_gs, u8 toneindex)
+{
+	struct dm_iqk_info *iqk_info = &dm->IQK_info;
+
+	if (iqk_info->is_btg) {
+		iqk_info->tmp1bcc = 0x1b;
+		iqk_info->lna_idx = 2;
+		odm_write_4byte(dm, 0x1b00, 0xf8000008 | path << 1);
+		odm_write_1byte(dm, 0x1b2b, 0x80);
+		odm_write_4byte(dm, 0x1bcc, iqk_info->tmp1bcc);
+		odm_write_4byte(dm, 0x1b20, 0x01450008);
+		odm_write_4byte(dm, 0x1b24, (0x01460048 | (btg_lna[iqk_info->lna_idx] << 10)));
+		/*0x78[11:0] = IDAC value*/
+		odm_set_rf_reg(dm, path, RF_0x78, RFREGOFFSETMASK, 0x8cbba);
+		odm_set_rf_reg(dm, path, RF_0x5c, RFREGOFFSETMASK, 0x00320);
+		odm_set_rf_reg(dm, path, RF_0x8f, RFREGOFFSETMASK, 0xa8018);
+	} else {
+		odm_write_4byte(dm, 0x1b00, 0xf8000008 | path << 1);
+		switch (*dm->band_type) {
+		case ODM_BAND_2_4G:
+			iqk_info->tmp1bcc = 0x12;
+			iqk_info->lna_idx = 2;
+			odm_write_1byte(dm, 0x1bcc, iqk_info->tmp1bcc);
+			odm_write_1byte(dm, 0x1b2b, 0x00);
+			odm_write_4byte(dm, 0x1b20, 0x01450008);
+			odm_write_4byte(dm, 0x1b24, (0x01460048 | (wlg_lna[iqk_info->lna_idx] << 10)));
+			odm_set_rf_reg(dm, path, RF_0x56, RFREGOFFSETMASK, 0x510f3);
+			odm_set_rf_reg(dm, path, RF_0x8f, RFREGOFFSETMASK, 0xa9c00);
+			break;
+		case ODM_BAND_5G:
+			iqk_info->tmp1bcc = 0x09;
+			iqk_info->lna_idx = 2;
+			odm_write_1byte(dm, 0x1bcc, iqk_info->tmp1bcc);
+			odm_write_1byte(dm, 0x1b2b, 0x00);
+			odm_write_4byte(dm, 0x1b20, 0x00450008);
+			odm_write_4byte(dm, 0x1b24, (0x01460048 | (wla_lna[iqk_info->lna_idx] << 10)));
+#if 0
+			/*odm_set_rf_reg(dm, path, RF_0x56, RFREGOFFSETMASK, 0x51000);*/
+#endif
+			odm_set_rf_reg(dm, path, RF_0x56, RFREGOFFSETMASK, 0x51060);
+			odm_set_rf_reg(dm, path, RF_0x8f, RFREGOFFSETMASK, 0xa9c00);
+			break;
+		}
+	}
+	odm_write_4byte(dm, 0x1b20, (odm_read_4byte(dm, 0x1b20) & 0x000fffff) | toneindex << 20);
+	odm_write_4byte(dm, 0x1b24, (odm_read_4byte(dm, 0x1b24) & 0x000fffff) | toneindex << 20);
+}
+
+boolean
+_iqk_rx_iqk_gain_search_fail_by_toneindex_8821c(struct dm_struct *dm, u8 path,
+						u8 step, u8 tone_index)
+{
+	boolean fail = true;
+	u32 IQK_CMD;
+#if 0
+	/*u8	lna_setting[5];*/
+#endif
+
+	_iqk_rxk2setting_by_toneindex_8821c(dm, path, RXIQK1, tone_index);
+	odm_write_4byte(dm, 0x1b00, 0xf8000008 | path << 1);
+
+	IQK_CMD = 0xf8000208 | (1 << (path + 4));
+
+	_iqk_set_gnt_wl_gnt_bt(dm, true);
+	odm_write_4byte(dm, 0x1b00, IQK_CMD);
+	odm_write_4byte(dm, 0x1b00, IQK_CMD + 0x1);
+#if 0
+	/*ODM_sleep_ms(GS_delay_8821C);*/
+#endif
+	ODM_delay_ms(GS_delay_8821C);
+	fail = _iqk_check_cal_8821c(dm, IQK_CMD);
+	_iqk_set_gnt_wl_gnt_bt(dm, false);
+
+	return fail;
+}
+
+boolean
+_lok_one_shot_8821c(void *dm_void, u8 path, u8 pad_index)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct dm_iqk_info *iqk_info = &dm->IQK_info;
+	u8 delay_count = 0;
+	boolean LOK_notready = false;
+	u32 LOK_temp2 = 0, LOK_temp3 = 0;
+	u32 IQK_CMD = 0x0;
+#if 0
+	/*u8		LOKreg[] = {0x58, 0x78};*/
+#endif
+	RF_DBG(dm, DBG_RF_IQK, "[IQK]==========S%d LOK ==========\n",
+	       iqk_info->is_btg);
+
+	IQK_CMD = 0xf8000008 | (1 << (4 + path));
+
+	RF_DBG(dm, DBG_RF_IQK, "[IQK]LOK_Trigger = 0x%x\n", IQK_CMD);
+
+	_iqk_set_gnt_wl_gnt_bt(dm, true);
+	odm_write_4byte(dm, 0x1b00, IQK_CMD);
+	odm_write_4byte(dm, 0x1b00, IQK_CMD + 1);
+	/*LOK: CMD ID = 0	{0xf8000018, 0xf8000028}*/
+	/*LOK: CMD ID = 0	{0xf8000019, 0xf8000029}*/
+#if 0
+	/*ODM_sleep_ms(LOK_delay_8821C);*/
+#endif
+	ODM_delay_ms(LOK_delay_8821C);
+
+	delay_count = 0;
+	LOK_notready = true;
+
+	while (LOK_notready) {
+		if (odm_get_rf_reg(dm, path, RF_0x8, RFREGOFFSETMASK) == 0x12345)
+			LOK_notready = false;
+		else
+			LOK_notready = true;
+
+		if (LOK_notready) {
+#if 0
+			/*ODM_sleep_ms(1);*/
+#endif
+			ODM_delay_ms(1);
+			delay_count++;
+		}
+
+		if (delay_count >= 50) {
+			RF_DBG(dm, DBG_RF_IQK, "[IQK]S%d LOK timeout!!!\n",
+			       path);
+			break;
+		}
+	}
+	odm_set_rf_reg(dm, path, RF_0x8, RFREGOFFSETMASK, 0x0);
+
+	_iqk_set_gnt_wl_gnt_bt(dm, false);
+	RF_DBG(dm, DBG_RF_IQK, "[IQK]S%d ==> delay_count = 0x%x\n", path,
+	       delay_count);
+
+	if (!LOK_notready) {
+		LOK_temp2 = odm_get_rf_reg(dm, (enum rf_path)path, RF_0x8, RFREGOFFSETMASK);
+		LOK_temp3 = odm_get_rf_reg(dm, (enum rf_path)path, RF_0x58, RFREGOFFSETMASK);
+
+		RF_DBG(dm, DBG_RF_IQK, "[IQK]0x8 = 0x%x, 0x58 = 0x%x\n",
+		       LOK_temp2, LOK_temp3);
+	} else {
+		RF_DBG(dm, DBG_RF_IQK, "[IQK]==>S%d LOK Fail!!!\n", path);
+	}
+
+	iqk_info->lok_fail[path] = LOK_notready;
+
+	/*fill IDAC LUT table*/
+#if 0
+	/*
+	for (i = 0; i < 8; i++) {
+		odm_set_rf_reg(dm, path, RF_0x33, BIT(2)|BIT(1)|BIT(0), i);
+		odm_set_rf_reg(dm, path, RF_0x8, RFREGOFFSETMASK, LOK_temp2);
+	}
+	*/
+#endif
+	return LOK_notready;
+}
+
+boolean
+_iqk_one_shot_8821c(void *dm_void, u8 path, u8 idx)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct dm_iqk_info *iqk_info = &dm->IQK_info;
+	u8 delay_count = 0;
+	boolean fail = true;
+	u32 IQK_CMD = 0x0;
+	u16 iqk_apply[2] = {0xc94, 0xe94};
+
+	if (idx == TX_IQK)
+		RF_DBG(dm, DBG_RF_IQK,
+		       "[IQK]============ S%d WBTXIQK ============\n",
+		       iqk_info->is_btg);
+	else if (idx == RXIQK1)
+		RF_DBG(dm, DBG_RF_IQK,
+		       "[IQK]============ S%d WBRXIQK STEP1============\n",
+		       iqk_info->is_btg);
+	else
+		RF_DBG(dm, DBG_RF_IQK,
+		       "[IQK]============ S%d WBRXIQK STEP2============\n",
+		       iqk_info->is_btg);
+
+	if (idx == TXIQK) {
+		IQK_CMD = 0xf8000008 | ((*dm->band_width + 4) << 8) | (1 << (path + 4));
+		RF_DBG(dm, DBG_RF_IQK, "[IQK]TXK_Trigger = 0x%x\n", IQK_CMD);
+#if 0
+		/*{0xf8000418, 0xf800042a} ==> 20 WBTXK (CMD = 4)*/
+		/*{0xf8000518, 0xf800052a} ==> 40 WBTXK (CMD = 5)*/
+		/*{0xf8000618, 0xf800062a} ==> 80 WBTXK (CMD = 6)*/
+#endif
+	} else if (idx == RXIQK1) {
+		if (*dm->band_width == 2)
+			IQK_CMD = 0xf8000808 | (1 << (path + 4));
+		else
+			IQK_CMD = 0xf8000708 | (1 << (path + 4));
+		RF_DBG(dm, DBG_RF_IQK, "[IQK]RXK1_Trigger = 0x%x\n", IQK_CMD);
+#if 0
+		/*{0xf8000718, 0xf800072a} ==> 20 WBTXK (CMD = 7)*/
+		/*{0xf8000718, 0xf800072a} ==> 40 WBTXK (CMD = 7)*/
+		/*{0xf8000818, 0xf800082a} ==> 80 WBTXK (CMD = 8)*/
+#endif
+	} else if (idx == RXIQK2) {
+		IQK_CMD = 0xf8000008 | ((*dm->band_width + 9) << 8) | (1 << (path + 4));
+		RF_DBG(dm, DBG_RF_IQK, "[IQK]RXK2_Trigger = 0x%x\n", IQK_CMD);
+#if 0
+		/*{0xf8000918, 0xf800092a} ==> 20 WBRXK (CMD = 9)*/
+		/*{0xf8000a18, 0xf8000a2a} ==> 40 WBRXK (CMD = 10)*/
+		/*{0xf8000b18, 0xf8000b2a} ==> 80 WBRXK (CMD = 11)*/
+#endif
+	}
+
+	_iqk_set_gnt_wl_gnt_bt(dm, true);
+
+	odm_write_4byte(dm, 0x1bc8, 0x80000000);
+	odm_write_4byte(dm, 0x8f8, 0x41400080);
+
+	if (odm_get_rf_reg(dm, path, RF_0x08, RFREGOFFSETMASK) != 0x0)
+		odm_set_rf_reg(dm, path, RF_0x8, RFREGOFFSETMASK, 0x0);
+
+	odm_write_4byte(dm, 0x1b00, IQK_CMD);
+	odm_write_4byte(dm, 0x1b00, IQK_CMD + 0x1);
+
+#if 0
+	/*ODM_sleep_ms(WBIQK_delay_8821C);*/
+#endif
+	ODM_delay_ms(WBIQK_delay_8821C);
+
+	fail = _iqk_check_nctl_done_8821c(dm, path, IQK_CMD);
+
+	RF_DBG(dm, DBG_RF_IQK, "[IQK]check 0x49c = %x\n",
+	       odm_read_1byte(dm, 0x49c));
+
+	_iqk_set_gnt_wl_gnt_bt(dm, false);
+
+	if (dm->debug_components & DBG_RF_IQK) {
+		odm_write_4byte(dm, 0x1b00, 0xf8000008 | path << 1);
+		RF_DBG(dm, DBG_RF_IQK,
+		       "[IQK]S%d ==> 0x1b00 = 0x%x, 0x1b08 = 0x%x\n", path,
+		       odm_read_4byte(dm, 0x1b00), odm_read_4byte(dm, 0x1b08));
+		RF_DBG(dm, DBG_RF_IQK, "[IQK]S%d ==> delay_count = 0x%x\n",
+		       path, delay_count);
+		if (idx != TXIQK)
+			RF_DBG(dm, DBG_RF_IQK,
+			       "[IQK]S%d ==> RF0x0 = 0x%x, RF0x%x = 0x%x\n",
+			       path,
+			       odm_get_rf_reg(dm, path, RF_0x0,
+					      RFREGOFFSETMASK),
+			       (iqk_info->is_btg) ? 0x78 : 0x56,
+			       (iqk_info->is_btg) ?
+			       odm_get_rf_reg(dm, path, RF_0x78,
+					      RFREGOFFSETMASK) :
+			       odm_get_rf_reg(dm, path, RF_0x56,
+					      RFREGOFFSETMASK));
+	}
+
+	odm_write_4byte(dm, 0x1b00, 0xf8000008 | path << 1);
+	if (idx == TXIQK) {
+		if (fail)
+			odm_set_bb_reg(dm, iqk_apply[path], BIT(0), 0x0);
+		else
+			_iqk_backup_iqk_8821c(dm, 0x2, path);
+	}
+	if (idx == RXIQK2) {
+		iqk_info->rxiqk_agc[0][path] =
+			(u16)(((odm_get_rf_reg(dm, (enum rf_path)path, RF_0x0, RFREGOFFSETMASK) >> 5) & 0xff) |
+			      (iqk_info->tmp1bcc << 8));
+
+		odm_write_4byte(dm, 0x1b38, 0x20000000);
+
+		if (fail)
+			odm_set_bb_reg(dm, iqk_apply[path], (BIT(11) | BIT(10)), 0x0);
+		else
+			_iqk_backup_iqk_8821c(dm, 0x3, path);
+	}
+
+	if (idx == TXIQK)
+		iqk_info->iqk_fail_report[0][path][TXIQK] = fail;
+	else
+		iqk_info->iqk_fail_report[0][path][RXIQK] = fail;
+
+	return fail;
+}
+
+boolean
+_iqk_rxiqkbystep_8821c(void *dm_void, u8 path)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct dm_iqk_info *iqk_info = &dm->IQK_info;
+	boolean KFAIL = true, gonext;
+
+#if 1
+	switch (iqk_info->rxiqk_step) {
+	case 1: /*gain search_RXK1*/
+		_iqk_rxk1setting_8821c(dm, path);
+		gonext = false;
+		while (1) {
+			KFAIL = _iqk_rx_iqk_gain_search_fail_8821c(dm, path, RXIQK1);
+			if (KFAIL && iqk_info->gs_retry_count[0][path][0] < 2) {
+				iqk_info->gs_retry_count[0][path][0]++;
+			} else if (KFAIL) {
+				iqk_info->rxiqk_fail_code[0][path] = 0;
+				iqk_info->rxiqk_step = 5;
+				gonext = true;
+			} else {
+				iqk_info->rxiqk_step++;
+				gonext = true;
+			}
+			if (gonext)
+				break;
+		}
+		halrf_iqk_xym_read(dm, 0x0, 0x2);
+		break;
+	case 2: /*gain search_RXK2*/
+		_iqk_rxk2setting_8821c(dm, path, true);
+		iqk_info->isbnd = false;
+		while (1) {
+			KFAIL = _iqk_rx_iqk_gain_search_fail_8821c(dm, path, RXIQK2);
+			if (KFAIL && iqk_info->gs_retry_count[0][path][1] < rxiqk_gs_limit) {
+				iqk_info->gs_retry_count[0][path][1]++;
+			} else {
+				iqk_info->rxiqk_step++;
+				break;
+			}
+		}
+		halrf_iqk_xym_read(dm, 0x0, 0x3);
+		break;
+	case 3: /*RXK1*/
+		_iqk_rxk1setting_8821c(dm, path);
+		gonext = false;
+		while (1) {
+			KFAIL = _iqk_one_shot_8821c(dm, path, RXIQK1);
+			if (KFAIL && iqk_info->retry_count[0][path][RXIQK1] < 2) {
+				iqk_info->retry_count[0][path][RXIQK1]++;
+			} else if (KFAIL) {
+				iqk_info->rxiqk_fail_code[0][path] = 1;
+				iqk_info->rxiqk_step = 5;
+				gonext = true;
+			} else {
+				iqk_info->rxiqk_step++;
+				gonext = true;
+			}
+			if (gonext)
+				break;
+		}
+		halrf_iqk_xym_read(dm, 0x0, 0x4);
+		break;
+	case 4: /*RXK2*/
+		_iqk_rxk2setting_8821c(dm, path, false);
+		gonext = false;
+		while (1) {
+			KFAIL = _iqk_one_shot_8821c(dm, path, RXIQK2);
+			if (KFAIL && iqk_info->retry_count[0][path][RXIQK2] < 2) {
+				iqk_info->retry_count[0][path][RXIQK2]++;
+			} else if (KFAIL) {
+				iqk_info->rxiqk_fail_code[0][path] = 2;
+				iqk_info->rxiqk_step = 5;
+				gonext = true;
+			} else {
+				iqk_info->rxiqk_step++;
+				gonext = true;
+			}
+			if (gonext)
+				break;
+		}
+		halrf_iqk_xym_read(dm, 0x0, 0x0);
+		break;
+	}
+	return KFAIL;
+#endif
+}
+void _iqk_iqk_by_path_8821c(void *dm_void, boolean segment_iqk)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct dm_iqk_info *iqk_info = &dm->IQK_info;
+	boolean KFAIL = true;
+	u8 i, kcount_limit;
+
+#if 0
+	/*	RF_DBG(dm, DBG_RF_IQK, "[IQK]iqk_step = 0x%x\n", dm->rf_calibrate_info.iqk_step); */
+#endif
+	if (*dm->band_width == 2)
+		kcount_limit = kcount_limit_80m;
+	else
+		kcount_limit = kcount_limit_others;
+
+	while (1) {
+		switch (dm->rf_calibrate_info.iqk_step) {
+		case 1: /*S0 LOK*/
+			for (i = 0; i < 8; i++) { /* the LOK Cal in the each PAD stage*/
+				_iqk_lok_setting_8821c(dm, RF_PATH_A, i);
+				_lok_one_shot_8821c(dm, RF_PATH_A, i);
+			}
+			dm->rf_calibrate_info.iqk_step++;
+			break;
+		case 2: /*S0 TXIQK*/
+			_iqk_txk_setting_8821c(dm, RF_PATH_A);
+			KFAIL = _iqk_one_shot_8821c(dm, RF_PATH_A, TXIQK);
+			iqk_info->kcount++;
+			RF_DBG(dm, DBG_RF_IQK, "[IQK]KFail = 0x%x\n", KFAIL);
+			if (KFAIL && iqk_info->retry_count[0][RF_PATH_A][TXIQK] < 3)
+				iqk_info->retry_count[0][RF_PATH_A][TXIQK]++;
+			else
+				dm->rf_calibrate_info.iqk_step++;
+			halrf_iqk_xym_read(dm, 0x0, 0x1);
+			break;
+		case 3: /*S0 RXIQK*/
+			while (1) {
+				KFAIL = _iqk_rxiqkbystep_8821c(dm, RF_PATH_A);
+				RF_DBG(dm, DBG_RF_IQK,
+				       "[IQK]S0RXK KFail = 0x%x\n", KFAIL);
+				if (iqk_info->rxiqk_step == 5) {
+					dm->rf_calibrate_info.iqk_step++;
+					iqk_info->rxiqk_step = 1;
+					if (KFAIL)
+						RF_DBG(dm, DBG_RF_IQK, "[IQK]S0RXK fail code: %d!!!\n", iqk_info->rxiqk_fail_code[0][RF_PATH_A]);
+					break;
+				}
+			}
+			iqk_info->kcount++;
+			break;
+		}
+
+		if (dm->rf_calibrate_info.iqk_step == 4) {
+			RF_DBG(dm, DBG_RF_IQK,
+			       "[IQK]==========LOK summary ==========\n");
+			RF_DBG(dm, DBG_RF_IQK, "[IQK]PathA_LOK_notready = %d\n",
+			       iqk_info->lok_fail[RF_PATH_A]);
+			RF_DBG(dm, DBG_RF_IQK,
+			       "[IQK]==========IQK summary ==========\n");
+			RF_DBG(dm, DBG_RF_IQK, "[IQK]PathA_TXIQK_fail = %d\n",
+			       iqk_info->iqk_fail_report[0][RF_PATH_A][TXIQK]);
+			RF_DBG(dm, DBG_RF_IQK, "[IQK]PathA_RXIQK_fail = %d\n",
+			       iqk_info->iqk_fail_report[0][RF_PATH_A][RXIQK]);
+			RF_DBG(dm, DBG_RF_IQK, "[IQK]PathA_TXIQK_retry = %d\n",
+			       iqk_info->retry_count[0][RF_PATH_A][TXIQK]);
+			RF_DBG(dm, DBG_RF_IQK,
+			       "[IQK]PathA_RXK1_retry = %d, PathA_RXK2_retry = %d\n",
+			       iqk_info->retry_count[0][RF_PATH_A][RXIQK1],
+			       iqk_info->retry_count[0][RF_PATH_A][RXIQK2]);
+			RF_DBG(dm, DBG_RF_IQK,
+			       "[IQK]PathA_GS1_retry = %d, PathA_GS2_retry = %d\n",
+			       iqk_info->gs_retry_count[0][RF_PATH_A][0],
+			       iqk_info->gs_retry_count[0][RF_PATH_A][1]);
+
+			for (i = 0; i < SS_8821C; i++) {
+				odm_write_4byte(dm, 0x1b00, 0xf8000008 | i << 1);
+				odm_write_4byte(dm, 0x1b2c, 0x7);
+				odm_write_4byte(dm, 0x1bcc, 0x0);
+				odm_write_4byte(dm, 0x1b38, 0x20000000);
+			}
+			break;
+		}
+		RF_DBG(dm, DBG_RF_IQK, "[IQK]segmentIQK = %d, Kcount = %d\n",
+		       segment_iqk, iqk_info->kcount);
+		if (segment_iqk && iqk_info->kcount == kcount_limit)
+			break;
+	}
+}
+
+void _iqk_start_iqk_8821c(struct dm_struct *dm, boolean segment_iqk)
+{
+	struct dm_iqk_info *iqk_info = &dm->IQK_info;
+	u32 tmp;
+
+	odm_write_4byte(dm, 0x1b00, 0xf8000008);
+	odm_write_4byte(dm, 0x1bb8, 0x00000000);
+	/*GNT_WL = 1*/
+	if (iqk_info->is_btg) {
+		tmp = odm_get_rf_reg(dm, RF_PATH_A, RF_0x1, RFREGOFFSETMASK);
+		tmp = (tmp & (~BIT(3))) | BIT(0) | BIT(2) | BIT(5);
+		odm_set_rf_reg(dm, RF_PATH_A, RF_0x1, RFREGOFFSETMASK, tmp);
+	} else {
+		tmp = odm_get_rf_reg(dm, RF_PATH_A, RF_0x1, RFREGOFFSETMASK);
+		tmp = ((tmp & (~BIT(3))) & (~BIT(5))) | BIT(0) | BIT(2);
+		odm_set_rf_reg(dm, RF_PATH_A, RF_0x1, RFREGOFFSETMASK, tmp);
+		RF_DBG(dm, DBG_RF_IQK, "[IQK]==> RF0x1 = 0x%x\n",
+		       odm_get_rf_reg(dm, RF_PATH_A, RF_0x1, RFREGOFFSETMASK));
+	}
+	_iqk_iqk_by_path_8821c(dm, segment_iqk);
+}
+
+void _iq_calibrate_8821c_init(struct dm_struct *dm)
+{
+	struct dm_iqk_info *iqk_info = &dm->IQK_info;
+	u8 i, j, k, m;
+	static boolean firstrun = true;
+
+	if (firstrun) {
+		firstrun = false;
+		RF_DBG(dm, DBG_RF_IQK,
+		       "[IQK]=====>PHY_IQCalibrate_8821C_Init\n");
+
+		for (i = 0; i < SS_8821C; i++) {
+			for (j = 0; j < 2; j++) {
+				iqk_info->lok_fail[i] = true;
+				iqk_info->iqk_fail[j][i] = true;
+				iqk_info->iqc_matrix[j][i] = 0x20000000;
+			}
+		}
+
+		for (i = 0; i < 2; i++) {
+			iqk_info->iqk_channel[i] = 0x0;
+
+			for (j = 0; j < SS_8821C; j++) {
+				iqk_info->lok_idac[i][j] = 0x0;
+				iqk_info->rxiqk_agc[i][j] = 0x0;
+				iqk_info->bypass_iqk[i][j] = 0x0;
+
+				for (k = 0; k < 2; k++) {
+					iqk_info->iqk_fail_report[i][j][k] = true;
+					for (m = 0; m < 8; m++) {
+						iqk_info->iqk_cfir_real[i][j][k][m] = 0x0;
+						iqk_info->iqk_cfir_imag[i][j][k][m] = 0x0;
+					}
+				}
+
+				for (k = 0; k < 3; k++)
+					iqk_info->retry_count[i][j][k] = 0x0;
+			}
+		}
+	}
+}
+
+u8 _txgapk_txpower_compare_8821c(struct dm_struct *dm, u8 path, u32 pw1,
+				 u32 pw2, u32 *pwr_table)
+{
+	u8 pwr_delta;
+	u32 temp = 0x0;
+	temp = (u32)(pw1 / (pw2 / 1000));
+
+	if (temp < pwr_table[0]) /*<-3.5 dB*/
+		pwr_delta = 0x0;
+	else if (temp < pwr_table[1])
+		pwr_delta = 0x1;
+	else if (temp < pwr_table[2])
+		pwr_delta = 0x2;
+	else if (temp < pwr_table[3])
+		pwr_delta = 0x3;
+	else if (temp < pwr_table[4])
+		pwr_delta = 0x4;
+	else if (temp < pwr_table[5])
+		pwr_delta = 0x5;
+	else if (temp < pwr_table[6])
+		pwr_delta = 0x6;
+	else if (temp < pwr_table[7])
+		pwr_delta = 0x7;
+	else if (temp < pwr_table[8])
+		pwr_delta = 0x8;
+	else if (temp < pwr_table[9])
+		pwr_delta = 0x9;
+	else if (temp < pwr_table[0xa])
+		pwr_delta = 0xa;
+	else if (temp < pwr_table[0xb])
+		pwr_delta = 0xb;
+	else if (temp < pwr_table[0xc])
+		pwr_delta = 0xc;
+	else if (temp < pwr_table[0xd])
+		pwr_delta = 0xd;
+	else if (temp < pwr_table[0xe])
+		pwr_delta = 0xe;
+	else if (temp < pwr_table[0xf])
+		pwr_delta = 0xf;
+	else if (temp < pwr_table[0x10])
+		pwr_delta = 0x10;
+	else if (temp < pwr_table[0x11])
+		pwr_delta = 0x11;
+	else if (temp < pwr_table[0x12])
+		pwr_delta = 0x12;
+	else if (temp < pwr_table[0x13])
+		pwr_delta = 0x13;
+	else if (temp < pwr_table[0x14])
+		pwr_delta = 0x14;
+	else if (temp < pwr_table[0x15])
+		pwr_delta = 0x15;
+	else if (temp < pwr_table[0x16])
+		pwr_delta = 0x16;
+	else if (temp < pwr_table[0x17])
+		pwr_delta = 0x17;
+	else if (temp < pwr_table[0x18])
+		pwr_delta = 0x18;
+	else if (temp < pwr_table[0x19])
+		pwr_delta = 0x19;
+	else
+		pwr_delta = 0x1a;
+
+	RF_DBG(dm, DBG_RF_IQK, "[TXGAPK] temp =%d, pwr_delta =%x\n", temp,
+	       pwr_delta);
+
+	return pwr_delta;
+}
+
+u32 _txgapk_txgap_compenstion_8821c(struct dm_struct *dm, u8 path,
+				    u32 txgain_0x56, u8 pwr_delta)
+{
+	u32 new_txgain_0x56;
+
+	/*	0	1	2	3	4	5	6	7	8	9	10	11	12	13	14 */
+	/*	-3.5	-3 -2.5  -2  -1.5  -1  -0.5    0   0.5	  1	1.5   2   2.5	  3    3.5 (dB)*/
+#if 0
+	/* 	pwr_table[0xf]={89,100,112,125,141,158,177,199,223,251,281,316,354,398,446}*/
+#endif
+
+	switch (pwr_delta) {
+	case 0x1a:
+	case 0x19:
+	case 0x18:
+	case 0x17:
+	case 0x16:
+	case 0x15:
+	case 0x14:
+#if 0
+	/*
+						if ((txgain_0x56 & 0x1f)<=0x1d)
+							new_txgain_0x56 = txgain_0x56 + 0x2; //< -1.5 ~ -2.5dB
+						else if ((txgain_0x56 & 0x1f)<=  0x1e)
+							new_txgain_0x56 = txgain_0x56 + 0x1;
+						else
+							new_txgain_0x56 = txgain_0x56;
+						break;
+*/
+#endif
+	case 0x13:
+	case 0x12:
+		if ((txgain_0x56 & 0x1f) <= 0x1e)
+			new_txgain_0x56 = txgain_0x56 + 0x1;/*< -0.5 ~ -1.5dB*/
+		else
+			new_txgain_0x56 = txgain_0x56;
+		break;
+	case 0x11:
+	case 0x10:
+	case 0xf:
+	case 0xe:
+	case 0xd:
+	case 0xc:
+		new_txgain_0x56 = txgain_0x56; /*<  -0.5~0.5dB*/
+		break;
+	case 0xb:
+	case 0xa:
+	case 0x9:
+	case 0x8:
+	case 0x7:
+		if ((txgain_0x56 & 0x1f) >= 0x01)
+			new_txgain_0x56 = txgain_0x56 - 0x1; /* >0.5~1.5dB */
+		else
+			new_txgain_0x56 = txgain_0x56;
+		break;
+	case 0x6:
+	case 0x5:
+	case 0x4:
+	case 0x3:
+#if 0
+	/*
+						if ((txgain_0x56 & 0x1f)>= 0x02)
+							new_txgain_0x56 = txgain_0x56 - 0x2; //>1.5~2.5dB
+						else if ((txgain_0x56 & 0x1f)>= 0x01)
+							new_txgain_0x56 = txgain_0x56 - 0x1;
+						else
+							new_txgain_0x56 = txgain_0x56;
+						break;
+*/
+#endif
+	case 0x2:
+	case 0x1:
+	case 0x0:
+#if 0
+	/*
+						if ((txgain_0x56 & 0x1f)>= 0x03)
+							new_txgain_0x56 = txgain_0x56 - 0x3; //>2.5~3.5dB
+						else if ((txgain_0x56 & 0x1f)>= 0x02)
+							new_txgain_0x56 = txgain_0x56 - 0x2;
+						else if ((txgain_0x56 & 0x1f)>= 0x01)
+							new_txgain_0x56 = txgain_0x56 - 0x1;
+						else
+							new_txgain_0x56 = txgain_0x56;
+						break;
+*/
+#endif
+	default:
+		new_txgain_0x56 = txgain_0x56;
+		break;
+	}
+	if ((new_txgain_0x56 & 0x1f) < 0x02)
+		new_txgain_0x56 = (new_txgain_0x56 & 0xffffc) + 0x2;
+	if ((new_txgain_0x56 & 0x1f) > 0x1d)
+		new_txgain_0x56 = (new_txgain_0x56 | 0x3) - 0x2;
+
+	return new_txgain_0x56;
+}
+
+void _txgapk_backup_8821c(struct dm_struct *dm, u32 *backup_txgap,
+			  u32 *backup_txgap_reg, u8 txgapk_reg_num)
+{
+	u32 i;
+
+	for (i = 0; i < txgapk_reg_num; i++)
+		backup_txgap[i] = odm_read_4byte(dm, backup_txgap_reg[i]);
+}
+u32 _txgapk_get_rf_tx_index_8821c(struct dm_struct *dm, u8 path,
+				  u32 txgain_index)
+{
+	u32 rf_backup_reg00, rf_backup_regdf, rf_reg56;
+
+	rf_backup_reg00 = odm_get_rf_reg(dm, RF_PATH_A, RF_0x00, RFREGOFFSETMASK);
+	rf_backup_regdf = odm_get_rf_reg(dm, RF_PATH_A, RF_0xdf, RFREGOFFSETMASK);
+
+	odm_set_rf_reg(dm, RF_PATH_A, RF_0xdf, RFREGOFFSETMASK, 0x08009);
+	odm_set_rf_reg(dm, RF_PATH_A, RF_0x00, RFREGOFFSETMASK, 0x20000 + txgain_index);
+	/*ODM_sleep_us(10);*/
+
+	ODM_delay_us(10);
+	rf_reg56 = odm_get_rf_reg(dm, RF_PATH_A, RF_0x56, RFREGOFFSETMASK);
+
+	RF_DBG(dm, DBG_RF_IQK,
+	       "[TXGAPK](2) txgain_index =0x%x, rf_reg56=0x%x\n", txgain_index,
+	       rf_reg56);
+	odm_set_rf_reg(dm, RF_PATH_A, RF_0x00, RFREGOFFSETMASK, rf_backup_reg00);
+	odm_set_rf_reg(dm, RF_PATH_A, RF_0xdf, RFREGOFFSETMASK, rf_backup_regdf);
+	return rf_reg56;
+}
+
+void _txgapk_restore_8821c(struct dm_struct *dm, u32 *backup_txgap,
+			   u32 *backup_txgap_reg, u8 txgapk_reg_num)
+{
+	u32 i;
+
+	for (i = 0; i < txgapk_reg_num; i++)
+		odm_write_4byte(dm, backup_txgap_reg[i], backup_txgap[i]);
+}
+
+void _txgapk_setting_8821c(struct dm_struct *dm, u8 path)
+{
+	struct dm_iqk_info *iqk_info = &dm->IQK_info;
+
+	/*RF*/
+	odm_set_rf_reg(dm, RF_PATH_A, RF_0xef, RFREGOFFSETMASK, 0x80000);
+	odm_set_rf_reg(dm, RF_PATH_A, RF_0x33, RFREGOFFSETMASK, 0x00024);
+	odm_set_rf_reg(dm, RF_PATH_A, RF_0x3e, RFREGOFFSETMASK, 0x0003F);
+	odm_set_rf_reg(dm, RF_PATH_A, RF_0x3f, RFREGOFFSETMASK, 0xCBFCE);
+	odm_set_rf_reg(dm, RF_PATH_A, RF_0xef, RFREGOFFSETMASK, 0x00000);
+	if (iqk_info->is_btg) {
+	} else {
+		switch (*dm->band_type) {
+		case ODM_BAND_2_4G:
+			break;
+		case ODM_BAND_5G:
+			odm_set_rf_reg(dm, RF_PATH_A, RF_0x8f, RFREGOFFSETMASK, 0xA9C00);
+			odm_set_rf_reg(dm, RF_PATH_A, RF_0xdf, RFREGOFFSETMASK, 0x00809);
+			odm_set_rf_reg(dm, RF_PATH_A, RF_0x00, RFREGOFFSETMASK, 0x4001c);
+
+			odm_write_4byte(dm, 0x1bcc, 0x00000009); /*try the iqk swing*/
+			odm_write_4byte(dm, 0x1b20, 0x01040008);
+			odm_write_4byte(dm, 0x1b24, 0x01040848);
+
+			odm_write_4byte(dm, 0x1b14, 0x00001000);
+			odm_write_4byte(dm, 0x1b1c, 0x82193d31);
+
+			odm_write_1byte(dm, 0x1b22, 0x04); /*sync with RF0x33[3:0]*/
+			odm_write_1byte(dm, 0x1b26, 0x04); /*sync with RF0x33[3:0]*/
+			odm_write_1byte(dm, 0x1b2c, 0x03);
+			odm_write_4byte(dm, 0x1b38, 0x20000000);
+			odm_write_4byte(dm, 0x1b3c, 0x20000000);
+			odm_write_4byte(dm, 0xc00, 0x4);
+
+			RF_DBG(dm, DBG_RF_IQK,
+			       "[IQK](1) txgap calibration setting!!!\n");
+
+			break;
+		}
+	}
+}
+
+u32 _txgapk_one_shot_8821c(struct dm_struct *dm_void, u8 path, u32 reg0x56)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	boolean txgap_k_notready = true;
+	u8 delay_count = 0x0;
+	u32 txgap_k_tmp1 = 0x1, txgap_k_tmp2 = 0x2;
+	u8 offset;
+	u32 reg_1bb8;
+	u32 rx_dsp_power;
+
+	reg_1bb8 = odm_read_4byte(dm, 0x1bb8);
+	/*clear the flag*/
+	odm_write_1byte(dm, 0x1bd6, 0x0b);
+	odm_set_bb_reg(dm, R_0x1bfc, BIT(1), 0x0);
+	txgap_k_notready = true;
+	delay_count = 0x0;
+	/* get tx gain*/
+	odm_write_1byte(dm, 0x1b2b, 0x00);
+	odm_write_1byte(dm, 0x1bb8, 0x00);
+	odm_set_rf_reg(dm, path, RF_0xdf, RFREGOFFSETMASK, 0x00802);
+	odm_set_rf_reg(dm, path, RF_0x8f, RFREGOFFSETMASK, 0xa9c00);
+	odm_set_rf_reg(dm, path, RF_0x56, RFREGOFFSETMASK, reg0x56);
+	odm_write_4byte(dm, 0x1bb8, 0x00100000);
+#if 0
+	/*ODM_sleep_us(10);*/
+#endif
+
+	ODM_delay_us(10);
+	/* one-shot-1*/
+	odm_write_4byte(dm, 0x1b34, 0x1);
+	odm_write_4byte(dm, 0x1b34, 0x0);
+
+#if 1
+	while (txgap_k_notready) {
+		odm_write_1byte(dm, 0x1bd6, 0x0b);
+		if ((boolean)odm_get_bb_reg(dm, R_0x1bfc, BIT(1)))
+			txgap_k_notready = false;
+		else
+			txgap_k_notready = true;
+
+		if (txgap_k_notready) {
+#if 0
+			/*ODM_sleep_us(100);*/
+#endif
+			ODM_delay_us(100);
+			delay_count++;
+		}
+
+		if (delay_count >= 20) {
+			RF_DBG(dm, DBG_RF_IQK,
+			       "[TXGAPK] (3)txgapktimeout,delay_count=0x%x !!!\n",
+			       delay_count);
+			txgap_k_notready = false;
+			break;
+		}
+	}
+#else
+	ODM_sleep_ms(1);
+	if ((boolean)odm_get_bb_reg(dm, R_0x1bfc, BIT(1)))
+		txgap_k_notready = false;
+	else
+		txgap_k_notready = true;
+
+#endif
+
+	if (!txgap_k_notready) {
+		odm_write_1byte(dm, 0x1bd6, 0x5);
+		txgap_k_tmp1 = odm_read_4byte(dm, 0x1bfc) >> 27;
+		odm_write_1byte(dm, 0x1bd6, 0xe);
+		txgap_k_tmp2 = odm_read_4byte(dm, 0x1bfc);
+
+		RF_DBG(dm, DBG_RF_IQK,
+		       "[TXGAPK] reg0x56 =0x%x, txgapK_tmp1 =0x%x, txgapK_tmp2 =0x%x!!!\n",
+		       reg0x56, txgap_k_tmp1, txgap_k_tmp2);
+
+		if (txgap_k_tmp1 == 0)
+			offset = 0x0;
+		else if (txgap_k_tmp1 < 2)
+			offset = 0x1;
+		else if (txgap_k_tmp1 < 4)
+			offset = 0x2;
+		else
+			offset = 0x3;
+
+		if (txgap_k_tmp1 == 0x0) {
+			rx_dsp_power = txgap_k_tmp2;
+		} else {
+			txgap_k_tmp1 = txgap_k_tmp1 << (32 - offset);
+			txgap_k_tmp2 = txgap_k_tmp2 >> offset;
+			rx_dsp_power = txgap_k_tmp1 + txgap_k_tmp2;
+			overflowflag = true;
+			RF_DBG(dm, DBG_RF_IQK,
+			       "[TXGAPK](3) (1)overflowflag = true, txgapK_tmp1 =0x%x, txgapK_tmp2 =0x%x!!!\n",
+			       txgap_k_tmp1, txgap_k_tmp2);
+		}
+	} else {
+		RF_DBG(dm, DBG_RF_IQK, "[TXGAPK](3) txgapK Fail!!!\n");
+	}
+
+	odm_write_4byte(dm, 0x1bb8, reg_1bb8);
+
+	return rx_dsp_power;
+}
+
+void _phy_txgapk_calibrate_8821c(void *dm_void, u8 path)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	u32 txgain[txgap_k_number] = {0, 0, 0, 0, 0, 0, 0};
+	u32 txgain_rf56[txgap_k_number] = {0, 0, 0, 0, 0, 0, 0};
+	u8 add_base, txgapk_num = 0x0, psd_delta = 0x0;
+	u8 i, bandselect = 0x0;
+	u32 backup_txgap_reg[11] = {0x1b14, 0x1b1c, 0x1b20, 0x1b24, 0x1b28, 0x1b2c, 0x1b38, 0x1b3c, 0x1bd6, 0x1bb8, 0x1bcc};
+	u32 backup_txgap[11];
+	u8 gain_gap_index[txgap_k_number] = {0x13, 0x10, 0xd, 0xa, 0x7, 0x4, 0x1};
+	u32 txgainindex[txgap_k_number] = {0x26, 0x25, 0x24, 0x23, 0x22, 0x21, 0x20};
+	u32 tmp1, tmp2, tmp3, tmp4, tmp5;
+	u8 skip_low_power_index = 0x3;
+
+	s8 psd_single_tone_offset_1db[3][3] = {{-1, 0, 0}, {-2, -1, -1}, {-1, -1, -1} }; /*5G, L,M,H, index 32,26,20*/
+	static u32 pwr_table_1db[27] = {590, 630, 668, 707, 749, 794, 841, 891, 944, 1000, 1040, 1096, 1148, 1202, 1258, 1318,
+					1380, 1412, 1513, 1584, 1678, 1778, 1888, 1995, 2113, 2387, 2391};
+	static u32 pwr_table_3db[27] = {944, 1000, 1059, 1122, 1185, 1258, 1333, 1412, 1496, 1584, 1659, 1737, 1819, 1905, 1995, 2089,
+					2187, 2290, 2398, 2511, 2660, 2818, 2985, 3162, 3349, 3548, 3758};
+	boolean txgapkdone = false;
+	u8 txgap_changed = 0x0;
+	u8 ref_val = 0x0;
+
+	overflowflag = 0;
+	RF_DBG(dm, DBG_RF_IQK,
+	       "[TXGAPK] (1) *dm->band_width = %x, *dm->channel =%d, *dm->band_type=%x\n",
+	       *dm->band_width, *dm->channel, *dm->band_type);
+
+	if (!(*dm->mp_mode))
+		return;
+
+	if (!(*dm->band_type == ODM_BAND_5G))
+		return;
+
+	if (*dm->band_width == 0) {
+#if 0
+		/*		return;*/
+#endif
+		if (*dm->channel < 64) {
+			bandselect = 0x0;
+			add_base = 0x0;
+		} else if (*dm->channel < 153) {
+			bandselect = 0x1;
+			add_base = 0x40;
+#if 0
+		/*else if (*dm->channel ==153){*/
+#endif
+		} else {
+			bandselect = 0x2;
+			add_base = 0x80;
+		}
+	} else if (*dm->band_width == 1) {
+		if (*dm->channel < 102) {
+			bandselect = 0x0;
+			add_base = 0x0;
+		} else if (*dm->channel < 151) {
+			bandselect = 0x1;
+			add_base = 0x40;
+#if 0
+		/*else if (*dm->channel ==151){*/
+#endif
+		} else {
+			bandselect = 0x2;
+			add_base = 0x80;
+		}
+	} else if (*dm->band_width == 2) {
+		/*		return;*/
+		if (*dm->channel < 106) {
+			bandselect = 0x0;
+			add_base = 0x0;
+		} else if (*dm->channel < 155) {
+			bandselect = 0x1;
+			add_base = 0x40;
+#if 0
+		/*else if (*dm->channel ==155){*/
+#endif
+		} else {
+			bandselect = 0x2;
+			add_base = 0x80;
+		}
+	} else {
+		return;
+	}
+
+	if (txgap_done[bandselect])
+		return;
+
+	/*Step 1*/
+	_txgapk_backup_8821c(dm, backup_txgap, backup_txgap_reg, 0xb);
+	/*step 2*/
+	phydm_clear_kfree_to_rf(dm, RF_PATH_A, 1);
+
+	for (i = 0; i < txgap_k_number; i++) {
+		txgain_rf56[i] = _txgapk_get_rf_tx_index_8821c(dm, RF_PATH_A, gain_gap_index[i]);
+		txgain[i] = txgain_rf56[i];
+	}
+
+	for (i = 0; i < txgap_k_number; i++) {
+		RF_DBG(dm, DBG_RF_IQK, "[TXGAPK] start txgain1[%x]=0x%x\n", i,
+		       txgain_rf56[i]);
+	}
+
+	_txgapk_setting_8821c(dm, RF_PATH_A);
+
+	/*step 3*/
+
+	/*1st*/
+	while (!txgapkdone) {
+		txgapk_num++;
+		if (txgapk_num > 2)
+			break;
+
+		for (i = 0; i < txgap_k_number - 1 - skip_low_power_index; i++) {
+			tmp1 = (txgain[i] & 0x000000e0) >> 5;
+			tmp2 = (txgain[i + 1] & 0x000000e0) >> 5;
+			tmp5 = txgain[i + 1];
+#if 0
+			//if (tmp1 != tmp2){
+#endif
+			if (true) {
+				tmp3 = _txgapk_one_shot_8821c(dm, RF_PATH_A, txgain[i] - 2);
+				tmp4 = _txgapk_one_shot_8821c(dm, RF_PATH_A, txgain[i + 1]);
+				if (overflowflag)
+					overflowflag = false;
+#if 0
+					//tmp4 = tmp4>>1;
+#endif
+
+				psd_delta =
+					_txgapk_txpower_compare_8821c(dm, RF_PATH_A, tmp3, tmp4, pwr_table_1db);
+
+				psd_delta = psd_delta + psd_single_tone_offset_1db[bandselect][i];
+				RF_DBG(dm, DBG_RF_IQK,
+				       "[TXGAPK] new psd_detla = %x\n",
+				       psd_delta);
+
+				if (psd_delta <= 0xb)
+					txgap_changed++;
+				else if (psd_delta <= 0x11)
+					;
+				else
+					txgap_changed++;
+
+				txgain[i + 1] =
+					_txgapk_txgap_compenstion_8821c(dm, RF_PATH_A, txgain[i + 1], psd_delta);
+			} else {
+				RF_DBG(dm, DBG_RF_IQK,
+				       "[TXGAPK]skip i=%d, txgain[%x]=0x%x\n",
+				       i, i + 1, txgain[i + 1]);
+			}
+		}
+
+		/*2nd*/
+
+		if (txgap_changed > 0x0) {
+			RF_DBG(dm, DBG_RF_IQK, "[TXGAPK] do 3dB check\n");
+
+			for (i = 0; i < txgap_k_number - 1 - skip_low_power_index; i++) {
+				tmp1 = (txgain[i] & 0x000000e0) >> 5;
+				tmp2 = (txgain[i + 1] & 0x000000e0) >> 5;
+
+				if (tmp1 != tmp2) {
+					if (i == 0)
+						tmp3 = _txgapk_one_shot_8821c(dm, RF_PATH_A, txgain[i] - 2);
+					else
+						tmp3 = _txgapk_one_shot_8821c(dm, RF_PATH_A, txgain[i]);
+
+					tmp4 = _txgapk_one_shot_8821c(dm, RF_PATH_A, txgain[i + 1]);
+
+					if (overflowflag) {
+						overflowflag = false;
+						RF_DBG(dm, DBG_RF_IQK, "[IQK] tmp3= %x, tmp4= %x\n", tmp3, tmp4);
+					}
+					if (i == 0)
+						psd_delta =
+							_txgapk_txpower_compare_8821c(dm, RF_PATH_A, tmp3, tmp4, pwr_table_1db);
+
+					else
+						psd_delta =
+							_txgapk_txpower_compare_8821c(dm, RF_PATH_A, tmp3, tmp4, pwr_table_3db);
+
+					if (psd_delta <= 0xa)
+						ref_val++;
+					else if (psd_delta <= 0x12)
+						;
+					else
+						ref_val++;
+				} else {
+					RF_DBG(dm, DBG_RF_IQK, "[TXGAPK]skip i=%d, txgain[%x]=0x%x\n", i, i + 1, txgain[i + 1]);
+				}
+			}
+
+			if (ref_val == 0x0) {
+				txgapkdone = true;
+				txgap_changed = 0x0;
+			} else {
+				/* restore default rf 0x56 */
+				for (i = 0; i < txgap_k_number; i++)
+					txgain[i] = txgain_rf56[i];
+			}
+
+		} else {
+			txgapkdone = true;
+		}
+	}
+
+	/*step 7*/
+	_txgapk_restore_8821c(dm, backup_txgap, backup_txgap_reg, 0xb);
+
+	/*step 8*/
+	RF_DBG(dm, DBG_RF_IQK,
+	       "[TXGAPK]txgapkdone =%x, txgap_changed=0x%x, ref_val =0x%x\n",
+	       txgapkdone, txgap_changed, ref_val);
+
+	if (txgapkdone) {
+		odm_set_rf_reg(dm, RF_PATH_A, RF_0xef, RFREGOFFSETMASK, 0x00800);
+
+		for (i = 0; i < txgap_k_number; i++) {
+			odm_set_rf_reg(dm, RF_PATH_A, RF_0x33, RFREGOFFSETMASK, txgainindex[i] + add_base);
+			odm_set_rf_reg(dm, RF_PATH_A, RF_0x3f, RFREGOFFSETMASK, txgain[i]);
+		}
+		odm_set_rf_reg(dm, RF_PATH_A, RF_0xef, RFREGOFFSETMASK, 0x00000);
+		txgap_done[bandselect] = true;
+		txgapkdone = false;
+	}
+}
+
+#if 0
+/*
+void
+_DPK_BackupReg_8821C(
+	struct dm_struct*	dm,
+	static u32*	DPK_backup,
+	u32*		backup_dpk_reg
+	)
+{
+
+	u32 i;
+
+	for (i = 0; i < DPK_BACKUP_REG_NUM_8821C; i++)
+		DPK_backup[i] = odm_read_4byte(dm, backup_dpk_reg[i]);
+
+}
+void
+_DPK_Restore_8821C(
+	struct dm_struct*		dm,
+	static  u32*		DPK_backup,
+	u32*		backup_dpk_reg
+	)
+{
+	u32 i;
+	for (i = 0; i < DPK_BACKUP_REG_NUM_8821C; i++)
+		odm_write_4byte(dm, backup_dpk_reg[i], DPK_backup[i]);
+}
+
+*/
+#endif
+void _dpk_toggle_rxagc(struct dm_struct *dm, boolean reset)
+{
+	/*toggle RXAGC  workaround method*/
+	u32 tmp1;
+	tmp1 = odm_read_4byte(dm, 0xc50);
+	odm_set_bb_reg(dm, R_0xc50, BIT(3) | BIT(2) | BIT(1) | BIT(0), 0x0);
+#if 0
+	/* 	 ODM_sleep_ms(2);*/
+#endif
+	ODM_delay_ms(2);
+	odm_set_bb_reg(dm, R_0xc50, BIT(3) | BIT(2) | BIT(1) | BIT(0), 0x2);
+#if 0
+	/*	 ODM_sleep_ms(2);*/
+#endif
+	ODM_delay_ms(2);
+	odm_set_bb_reg(dm, R_0xc50, BIT(3) | BIT(2) | BIT(1) | BIT(0), 0x0);
+	odm_write_4byte(dm, 0xc50, tmp1);
+}
+
+void _dpk_set_gain_scaling(struct dm_struct *dm, u8 path)
+{
+	u32 tmp1, tmp2, tmp3, tmp4, reg_1bfc;
+	u32 lut_i = 0x0, lut_q = 0x0, lut_pw = 0x0, lut_pw_avg = 0x0;
+	u16 gain_scaling = 0x0;
+
+	tmp1 = odm_read_4byte(dm, 0x1b00);
+	tmp2 = odm_read_4byte(dm, 0x1b08);
+	tmp3 = odm_read_4byte(dm, 0x1bd4);
+	tmp4 = odm_read_4byte(dm, 0x1bdc);
+
+	odm_write_4byte(dm, 0x1b00, 0xf8000008);
+	odm_write_4byte(dm, 0x1b08, 0x00000080);
+	odm_write_4byte(dm, 0x1bd4, 0x00040001);
+	odm_write_4byte(dm, 0x1bdc, 0xc0000081);
+
+	reg_1bfc = odm_read_4byte(dm, 0x1bfc);
+	lut_i = (reg_1bfc & 0x003ff800) >> 11;
+	lut_q = (reg_1bfc & 0x00007ff);
+
+	if ((lut_i & 0x400) == 0x400)
+		lut_i = 0x800 - lut_i;
+	if ((lut_q & 0x400) == 0x400)
+		lut_q = 0x800 - lut_q;
+
+	lut_pw = lut_i * lut_i + lut_q * lut_q;
+	lut_pw_avg = (u32)(lut_i + lut_q) >> 1;
+	gain_scaling = (u16)(0x800000 / lut_pw_avg);
+
+	odm_set_bb_reg(dm, R_0x1b98, 0x0000ffff, gain_scaling);
+	odm_set_bb_reg(dm, R_0x1b98, 0xffff0000, gain_scaling);
+
+	odm_write_4byte(dm, 0x1b00, tmp1);
+	odm_write_4byte(dm, 0x1b08, tmp2);
+	odm_write_4byte(dm, 0x1bd4, tmp3);
+	odm_write_4byte(dm, 0x1bdc, tmp4);
+
+	RF_DBG(dm, DBG_RF_IQK,
+	       "[IQK] reg_1bfc =0x%x, lut_pw =0x%x, lut_i = 0x%x, lut_q = 0x%x, lut_pw_avg = 0x%x, gain_scaling = 0x%x, 0x1b98 =0x%x!!!\n",
+	       reg_1bfc, lut_pw, lut_i, lut_q, lut_pw_avg, gain_scaling,
+	       odm_read_4byte(dm, 0x1b98));
+}
+
+void _dpk_set_dpk_pa_scan(struct dm_struct *dm, u8 path)
+{
+	u32 tmp1, tmp2, reg_1bfc;
+	u32 pa_scan_i = 0x0, pa_scan_q = 0x0, pa_scan_pw = 0x0;
+	u32 gainloss_back = 0x0;
+#if 0
+	/*	boolean pa_scan_search_fail = false;*/
+#endif
+	tmp1 = odm_read_4byte(dm, 0x1bcf);
+	tmp2 = odm_read_4byte(dm, 0x1bd4);
+
+	odm_write_4byte(dm, 0x1bcf, 0x11);
+	odm_write_4byte(dm, 0x1bd4, 0x00060000);
+
+	reg_1bfc = odm_read_4byte(dm, 0x1bfc);
+	odm_write_4byte(dm, 0x1bcf, 0x15);
+	pa_scan_i = (reg_1bfc & 0xffff0000) >> 16;
+	pa_scan_q = (reg_1bfc & 0x0000ffff);
+
+	if ((pa_scan_i & 0x8000) == 0x8000)
+		pa_scan_i = 0x10000 - pa_scan_i;
+	if ((pa_scan_q & 0x8000) == 0x8000)
+		pa_scan_q = 0x10000 - pa_scan_q;
+
+	pa_scan_pw = pa_scan_i * pa_scan_i + pa_scan_q * pa_scan_q;
+
+	/*estimated pa_scan_pw*/
+#if 0
+	/*0dB => (512^2) * 10^(0/10) = 262144*/
+	/*1dB => (512^2) * 10^(1/10) = 330019*/
+	/*2dB => (512^2) * 10^(2/10) = 415470*/
+	/*3dB => (512^2) * 10^(3/10) = 523046*/
+	/*4dB => (512^2) * 10^(4/10) = 658475*/
+	/*5dB => (512^2) * 10^(5/10) = 828972*/
+	/*6dB => (512^2) * 10^(6/10) = 1043614*/
+	/*7dB => (512^2) * 10^(7/10) = 1313832*/
+	/*8dB => (512^2) * 10^(0/10) = 1654016*/
+	/*9dB => (512^2) * 10^(1/10) = 2082283*/
+	/*10dB => (512^2) * 10^(2/10) = 2621440*/
+	/*11dB => (512^2) * 10^(3/10) = 3300197*/
+	/*12dB => (512^2) * 10^(4/10) = 4154702*/
+	/*13dB => (512^2) * 10^(5/10) = 5230460*/
+	/*14dB => (512^2) * 10^(6/10) = 6584759*/
+	/*15dB => (512^2) * 10^(7/10) = 8289721*/
+#endif
+	if (pa_scan_pw >= 0x7e7db9)
+		pa_scan_pw = 0x0f;
+	else if (pa_scan_pw >= 0x6479b7)
+		pa_scan_pw = 0x0e;
+	else if (pa_scan_pw >= 0x4fcf7c)
+		pa_scan_pw = 0x0d;
+	else if (pa_scan_pw >= 0x3f654e)
+		pa_scan_pw = 0x0c;
+	else if (pa_scan_pw >= 0x325b65)
+		pa_scan_pw = 0x0b;
+	else if (pa_scan_pw >= 0x280000)
+		pa_scan_pw = 0x0a;
+	else if (pa_scan_pw >= 0x1fc5eb)
+		pa_scan_pw = 0x09;
+	else if (pa_scan_pw >= 0x193d00)
+		pa_scan_pw = 0x8;
+	else if (pa_scan_pw >= 0x140c28)
+		pa_scan_pw = 0x7;
+	else if (pa_scan_pw >= 0xefc9e)
+		pa_scan_pw = 0x6;
+	else if (pa_scan_pw >= 0xca62c)
+		pa_scan_pw = 0x5;
+	else if (pa_scan_pw > 0xa0c2b)
+		pa_scan_pw = 0x4;
+	else if (pa_scan_pw > 0x7fb26)
+		pa_scan_pw = 0x3;
+	else if (pa_scan_pw > 0x656ee)
+		pa_scan_pw = 0x2;
+	else if (pa_scan_pw > 0x50923)
+		pa_scan_pw = 0x1;
+	else /*262144 >= pa_scan_pw*/
+		pa_scan_pw = 0x0;
+
+	odm_write_4byte(dm, 0x1bd4, 0x00060001);
+	gainloss_back = (odm_read_4byte(dm, 0x1bfc) & 0x0000000f);
+
+	if (gainloss_back <= 0xa)
+		gainloss_back = 0xa - gainloss_back;
+
+	if (gainloss_back > pa_scan_pw + 0x8)
+		odm_set_rf_reg(dm, path, RF_0x8f, BIT(14) | BIT(13), 0x11);
+	else if ((pa_scan_pw + 0x8 - gainloss_back) >= 0x6)
+		odm_set_rf_reg(dm, path, RF_0x8f, BIT(14) | BIT(13), 0x00);
+	else
+#if 0
+		/*if (0x6 >= (pa_scan_pw + 0x8 - gainloss_back)> 0x0 )*/
+#endif
+		odm_set_rf_reg(dm, path, RF_0x8f, BIT(14) | BIT(13), 0x01);
+
+	RF_DBG(dm, DBG_RF_IQK,
+	       "[IQK] reg_1bfc =0x%x, pa_scan_pw =0x%x, gainloss_back = 0x%x, pa_scan_i = 0x%x, pa_scan_q = 0x%x, RF0x8f = 0x%x, !!!\n",
+	       reg_1bfc, pa_scan_pw, gainloss_back, pa_scan_i, pa_scan_q,
+	       odm_get_rf_reg(dm, path, RF_0x8f, RFREGOFFSETMASK));
+
+	odm_write_4byte(dm, 0x1bcf, tmp1);
+	odm_write_4byte(dm, 0x1bd4, tmp2);
+}
+
+void _dpk_disable_bb_dynamic_pwr_threshold(struct dm_struct *dm, boolean flag)
+{
+	if (flag) /*disable BB dynamic pwr threshold hold*/
+		odm_set_bb_reg(dm, R_0x1c74, BIT(31) | BIT(30) | BIT(29) | BIT(28), 0x0);
+	else
+		odm_set_bb_reg(dm, R_0x1c74, BIT(31) | BIT(30) | BIT(29) | BIT(28), 0x2);
+	RF_DBG(dm, DBG_RF_IQK, "[DPK]\nset 0x1c74 = 0x%x\n",
+	       odm_read_4byte(dm, 0x1c74));
+}
+
+void _dpk_set_dpk_sram_to_10_8821c(struct dm_struct *dm, u8 path)
+{
+	u32 tmp1, tmp2;
+	u8 i;
+	tmp1 = odm_read_4byte(dm, 0x1b00);
+	tmp2 = odm_read_4byte(dm, 0x1b08);
+
+	for (i = 0; i < 64; i++)
+		odm_write_4byte(dm, 0x1bdc, 0xd0000001 + (i * 2) + 1);
+
+	for (i = 0; i < 64; i++)
+		odm_write_4byte(dm, 0x1bdc, 0x90000080 + (i * 2) + 1);
+
+#if 0
+	/*
+	RF_DBG(dm, DBG_RF_IQK,
+		"[DPK]return  txagc = 0x%x , 1bfc = 0x%x,rf00=0x%x\n",
+		tmp4, odm_read_4byte(dm, 0x1bfc),
+		odm_get_rf_reg(dm, path, RF_0x00, RFREGOFFSETMASK));
+*/
+#endif
+	odm_write_4byte(dm, 0x1bdc, 0x0);
+	odm_write_4byte(dm, 0x1b00, tmp1);
+	odm_write_4byte(dm, 0x1b08, tmp2);
+}
+
+void _dpk_set_bbtxagc_8821c(struct dm_struct *dm, u8 path)
+{
+	u8 hw_rate, tmp;
+
+	for (hw_rate = 0; hw_rate < 0x53; hw_rate++) {
+		phydm_write_txagc_1byte_8821c(dm, 0x30, (enum rf_path)0x0, hw_rate);
+
+		tmp = config_phydm_read_txagc_8821c(dm, (enum rf_path)0x0, hw_rate);
+#if 0
+		/*
+	  RF_DBG(dm, DBG_RF_IQK,
+		  "hw_rate =0x%x, tmp =0x%x \n", hw_rate, tmp);
+*/
+#endif
+	}
+}
+
+u8 _dpk_get_txagcindpk_8821c(struct dm_struct *dm, u8 path)
+{
+	u32 tmp1, tmp2, tmp3;
+	u8 tmp4;
+	tmp1 = odm_read_4byte(dm, 0x1bcc);
+	odm_set_bb_reg(dm, R_0x1bcc, BIT(26), 0x01);
+	tmp2 = odm_read_4byte(dm, 0x1bd4);
+	odm_set_bb_reg(dm, R_0x1bd4, BIT(20) | BIT(19) | BIT(18) | BIT(17) | BIT(16), 0x0a);
+	tmp3 = odm_read_4byte(dm, 0x1bfc);
+	tmp4 = ((u8)odm_get_bb_reg(dm, R_0x1bfc, MASKDWORD)) >> 2;
+#if 0
+	/*
+	RF_DBG(dm, DBG_RF_IQK,
+		"[DPK]return  txagc = 0x%x , 1bfc = 0x%x,rf00=0x%x\n",
+		tmp4, odm_read_4byte(dm, 0x1bfc),
+		odm_get_rf_reg(dm, path, RF_0x00, RFREGOFFSETMASK));
+*/
+#endif
+	odm_write_4byte(dm, 0x1bcc, tmp1);
+	odm_write_4byte(dm, 0x1bd4, tmp2);
+
+	return tmp4;
+}
+
+void _dpk_ampmcurce_8821c(struct dm_struct *dm, u8 path)
+{
+	u8 i;
+	RF_DBG(dm, DBG_RF_IQK, "[DPK] 0x1bcc = 0x%x, 0x1bb8 =0x%x\n",
+	       odm_read_4byte(dm, 0x1bcc), odm_read_4byte(dm, 0x1bb8));
+
+	odm_write_4byte(dm, 0x1bcc, 0x118f8800);
+	for (i = 0; i < 8; i++) {
+		odm_write_4byte(dm, 0x1b90, 0x0101e018 + i);
+		odm_write_4byte(dm, 0x1bd4, 0x00060000);
+		RF_DBG(dm, DBG_RF_IQK, "0x%x\n", odm_read_4byte(dm, 0x1bfc));
+		odm_write_4byte(dm, 0x1bd4, 0x00070000);
+		RF_DBG(dm, DBG_RF_IQK, "0x%x\n", odm_read_4byte(dm, 0x1bfc));
+		odm_write_4byte(dm, 0x1bd4, 0x00080000);
+		RF_DBG(dm, DBG_RF_IQK, "0x%x\n", odm_read_4byte(dm, 0x1bfc));
+		odm_write_4byte(dm, 0x1bd4, 0x00090000);
+		RF_DBG(dm, DBG_RF_IQK, "0x%x\n", odm_read_4byte(dm, 0x1bfc));
+	}
+
+	odm_write_4byte(dm, 0x1b90, 0x0001e018);
+}
+void _dpk_readsram_8821c(struct dm_struct *dm, u8 path)
+{
+	/* dbg message*/
+	u8 i;
+	odm_write_4byte(dm, 0x1b00, 0xf8000008);
+	odm_write_4byte(dm, 0x1b08, 0x00000080);
+	odm_write_4byte(dm, 0x1bd4, 0x00040001);
+
+	RF_DBG(dm, DBG_RF_IQK, "[DPK] SRAM value!!!\n");
+
+	for (i = 0; i < 64; i++) {
+#if 0
+		/*odm_write_4byte(dm, 0x1b90, 0x0101e018+i);*/
+#endif
+		odm_write_4byte(dm, 0x1bdc, 0xc0000081 + i * 2);
+
+		RF_DBG(dm, DBG_RF_IQK, "0x%x\n", odm_read_4byte(dm, 0x1bfc));
+	}
+	odm_write_4byte(dm, 0x1bd4, 0x00050001);
+	for (i = 0; i < 64; i++) {
+#if 0
+		/*odm_write_4byte(dm, 0x1b90, 0x0101e018+i);*/
+#endif
+		odm_write_4byte(dm, 0x1bdc, 0xc0000081 + i * 2);
+
+		RF_DBG(dm, DBG_RF_IQK, "0x%x\n", odm_read_4byte(dm, 0x1bfc));
+	}
+#if 0
+	/*ODM_sleep_ms(200);*/
+#endif
+	ODM_delay_ms(200);
+#if 0
+	/*odm_write_4byte(dm, 0x1b08, 0x00000080);*/
+#endif
+	odm_write_4byte(dm, 0x1bd4, 0xA0001);
+	odm_write_4byte(dm, 0x1bdc, 0x00000000);
+}
+
+void _dpk_restore_8821c(struct dm_struct *dm, u8 path)
+{
+	odm_write_4byte(dm, 0xc60, 0x700B8040);
+	odm_write_4byte(dm, 0xc60, 0x700B8040);
+	odm_write_4byte(dm, 0xc60, 0x70146040);
+	odm_write_4byte(dm, 0xc60, 0x70246040);
+	odm_write_4byte(dm, 0xc60, 0x70346040);
+	odm_write_4byte(dm, 0xc60, 0x70446040);
+	odm_write_4byte(dm, 0xc60, 0x705B2040);
+	odm_write_4byte(dm, 0xc60, 0x70646040);
+	odm_write_4byte(dm, 0xc60, 0x707B8040);
+	odm_write_4byte(dm, 0xc60, 0x708B8040);
+	odm_write_4byte(dm, 0xc60, 0x709B8040);
+	odm_write_4byte(dm, 0xc60, 0x70aB8040);
+	odm_write_4byte(dm, 0xc60, 0x70bB6040);
+	odm_write_4byte(dm, 0xc60, 0x70c06040);
+	odm_write_4byte(dm, 0xc60, 0x70d06040);
+	odm_write_4byte(dm, 0xc60, 0x70eF6040);
+	odm_write_4byte(dm, 0xc60, 0x70f06040);
+
+	odm_write_4byte(dm, 0xc58, 0xd8020402);
+	odm_write_4byte(dm, 0xc5c, 0xde000120);
+	odm_write_4byte(dm, 0xc6c, 0x0000122a);
+
+	odm_write_4byte(dm, 0x808, 0x24028211);
+#if 0
+	/*odm_write_4byte(dm, 0x810, 0x211042A5);*/
+#endif
+	odm_write_4byte(dm, 0x90c, 0x13000000);
+	odm_write_4byte(dm, 0x9a4, 0x80000088);
+	odm_write_4byte(dm, 0xc94, 0x01000101);
+	odm_write_4byte(dm, 0x1904, 0x00238000);
+	odm_write_4byte(dm, 0x1904, 0x00228000);
+	odm_write_4byte(dm, 0xC00, 0x00000007);
+}
+
+void _dpk_clear_sram_8821c(struct dm_struct *dm, u8 path)
+{
+	u8 i;
+
+	/* write pwsf*/
+	/*S3*/
+	odm_write_4byte(dm, 0x1bdc, 0x40caffe1);
+	odm_write_4byte(dm, 0x1bdc, 0x4080a1e3);
+	odm_write_4byte(dm, 0x1bdc, 0x405165e5);
+	odm_write_4byte(dm, 0x1bdc, 0x403340e7);
+	odm_write_4byte(dm, 0x1bdc, 0x402028e9);
+	odm_write_4byte(dm, 0x1bdc, 0x401419eb);
+	odm_write_4byte(dm, 0x1bdc, 0x400d10ed);
+	odm_write_4byte(dm, 0x1bdc, 0x40080aef);
+
+	odm_write_4byte(dm, 0x1bdc, 0x400506f1);
+	odm_write_4byte(dm, 0x1bdc, 0x400304f3);
+	odm_write_4byte(dm, 0x1bdc, 0x400203f5);
+	odm_write_4byte(dm, 0x1bdc, 0x400102f7);
+	odm_write_4byte(dm, 0x1bdc, 0x400101f9);
+	odm_write_4byte(dm, 0x1bdc, 0x400101fb);
+	odm_write_4byte(dm, 0x1bdc, 0x400101fd);
+	odm_write_4byte(dm, 0x1bdc, 0x400101ff);
+	/*S0*/
+	odm_write_4byte(dm, 0x1bdc, 0x40caff81);
+	odm_write_4byte(dm, 0x1bdc, 0x4080a183);
+	odm_write_4byte(dm, 0x1bdc, 0x40516585);
+	odm_write_4byte(dm, 0x1bdc, 0x40334087);
+	odm_write_4byte(dm, 0x1bdc, 0x40202889);
+	odm_write_4byte(dm, 0x1bdc, 0x4014198b);
+	odm_write_4byte(dm, 0x1bdc, 0x400d108d);
+	odm_write_4byte(dm, 0x1bdc, 0x40080a8f);
+	odm_write_4byte(dm, 0x1bdc, 0x40050691);
+	odm_write_4byte(dm, 0x1bdc, 0x40030493);
+	odm_write_4byte(dm, 0x1bdc, 0x40020395);
+	odm_write_4byte(dm, 0x1bdc, 0x40010297);
+	odm_write_4byte(dm, 0x1bdc, 0x40010199);
+	odm_write_4byte(dm, 0x1bdc, 0x4001019b);
+	odm_write_4byte(dm, 0x1bdc, 0x4001019d);
+	odm_write_4byte(dm, 0x1bdc, 0x4001019f);
+
+	odm_write_4byte(dm, 0x1bdc, 0x00000000);
+
+	/*clear sram even*/
+	for (i = 0; i < 0x40; i++)
+		odm_write_4byte(dm, 0x1bdc, 0xd0000000 + ((i * 2) + 1));
+	/*clear sram odd*/
+	for (i = 0; i < 0x40; i++)
+		odm_write_4byte(dm, 0x1bdc, 0x90000080 + ((i * 2) + 1));
+
+	odm_write_4byte(dm, 0x1bdc, 0x0);
+	RF_DBG(dm, DBG_RF_IQK, "[DPK]==========write pwsf and clear sram/n");
+}
+
+void _dpk_setting_8821c(struct dm_struct *dm, u8 path)
+{
+	RF_DBG(dm, DBG_RF_IQK,
+	       "[DPK]==========Start the DPD setting Initilaize/n");
+	/*AFE setting*/
+	odm_write_4byte(dm, 0xc60, 0x50000000);
+	odm_write_4byte(dm, 0xc60, 0x700F0040);
+	odm_write_4byte(dm, 0xc5c, 0xd1000120);
+	odm_write_4byte(dm, 0xc58, 0xd8000402);
+	odm_write_4byte(dm, 0xc6c, 0x00000a15);
+	odm_write_4byte(dm, 0xc00, 0x00000004);
+#if 0
+	/*_iqk_bb_reset_8821c(dm);*/
+#endif
+	odm_write_4byte(dm, 0xe5c, 0xD1000120);
+	odm_write_4byte(dm, 0xc6c, 0x00000A15);
+	odm_write_4byte(dm, 0xe6c, 0x00000A15);
+	odm_write_4byte(dm, 0x808, 0x2D028200);
+#if 0
+	/*odm_write_4byte(dm, 0x810, 0x211042A5);*/
+#endif
+	odm_write_4byte(dm, 0x8f4, 0x00d80fb1);
+	odm_write_4byte(dm, 0x90c, 0x0B00C000);
+	odm_write_4byte(dm, 0x9a4, 0x00000080);
+	odm_write_4byte(dm, 0xc94, 0x01000101);
+	odm_write_4byte(dm, 0xe94, 0x01000101);
+	odm_write_4byte(dm, 0xe5c, 0xD1000120);
+	odm_write_4byte(dm, 0xc6c, 0x00000A15);
+	odm_write_4byte(dm, 0xe6c, 0x00000A15);
+	odm_write_4byte(dm, 0x1904, 0x00020000);
+	/*path A*/
+	/*RF*/
+	odm_set_rf_reg(dm, RF_PATH_A, RF_0xef, RFREGOFFSETMASK, 0x80000);
+	odm_set_rf_reg(dm, RF_PATH_A, RF_0x33, RFREGOFFSETMASK, 0x00024);
+	odm_set_rf_reg(dm, RF_PATH_A, RF_0x3e, RFREGOFFSETMASK, 0x0003F);
+	odm_set_rf_reg(dm, RF_PATH_A, RF_0x3f, RFREGOFFSETMASK, 0xCBFCE);
+	odm_set_rf_reg(dm, RF_PATH_A, RF_0xef, RFREGOFFSETMASK, 0x00000);
+	/*AGC boundary selection*/
+	odm_write_4byte(dm, 0x1bbc, 0x0001abf6);
+	odm_write_4byte(dm, 0x1b90, 0x0001e018);
+	odm_write_4byte(dm, 0x1bb8, 0x000fffff);
+	odm_write_4byte(dm, 0x1bc8, 0x000c55aa);
+#if 0
+	/*odm_write_4byte(dm, 0x1bcc, 0x11978200);*/
+#endif
+	odm_write_4byte(dm, 0x1bcc, 0x11978800);
+#if 0
+	/*odm_write_4byte(dm, 0xcb0, 0x77775747);*/
+	/*odm_write_4byte(dm, 0xcb4, 0x100000f7);*/
+	/*odm_write_4byte(dm, 0xcb4, 0x10000007);*/
+	/*odm_write_4byte(dm, 0xcbc, 0x0);*/
+#endif
+}
+
+void _dpk_dynamic_bias_8821c(struct dm_struct *dm, u8 path, u8 dynamicbias)
+{
+	u32 tmp;
+	tmp = odm_get_rf_reg(dm, RF_PATH_A, RF_0xdf, RFREGOFFSETMASK);
+	tmp = tmp | BIT(8);
+	odm_set_rf_reg(dm, RF_PATH_A, RF_0xdf, RFREGOFFSETMASK, tmp);
+	if ((*dm->band_type == ODM_BAND_5G) && (*dm->band_width == 1))
+		odm_set_rf_reg(dm, path, RF_0x61, BIT(7) | BIT(6) | BIT(5) | BIT(4), dynamicbias);
+	if ((*dm->band_type == ODM_BAND_5G) && (*dm->band_width == 2))
+		odm_set_rf_reg(dm, path, RF_0x61, BIT(7) | BIT(6) | BIT(5) | BIT(4), dynamicbias);
+	tmp = tmp & (~BIT(8));
+	odm_set_rf_reg(dm, RF_PATH_A, RF_0xdf, RFREGOFFSETMASK, tmp);
+	RF_DBG(dm, DBG_RF_IQK, "[DPK]Set DynamicBias 0xdf=0x%x, 0x61=0x%x\n",
+	       odm_get_rf_reg(dm, RF_PATH_A, RF_0xdf, RFREGOFFSETMASK),
+	       odm_get_rf_reg(dm, RF_PATH_A, RF_0x61, RFREGOFFSETMASK));
+}
+
+void _dpk_boundary_selection_8821c(struct dm_struct *dm, u8 path)
+{
+	u8 tmp_pad, compared_pad, compared_txbb;
+	u32 rf_backup_reg00;
+	u8 i = 0;
+	u8 j = 1;
+	u32 boundaryselect = 0;
+	struct dm_iqk_info *iqk_info = &dm->IQK_info;
+
+	RF_DBG(dm, DBG_RF_IQK, "[DPK]Start the DPD boundary selection\n");
+	rf_backup_reg00 = odm_get_rf_reg(dm, (enum rf_path)path, RF_0x00, RFREGOFFSETMASK);
+	tmp_pad = 0;
+	compared_pad = 0;
+	boundaryselect = 0;
+#if dpk_forcein_sram4
+	for (i = 0x1f; i > 0x0; i--) { /*i=tx index*/
+		odm_set_rf_reg(dm, RF_PATH_A, RF_0x00, RFREGOFFSETMASK, 0x20000 + i);
+
+		if (iqk_info->is_btg) {
+			compared_pad = (u8)((0x1c000 & odm_get_rf_reg(dm, (enum rf_path)path, RF_0x78, RFREGOFFSETMASK)) >> 14);
+			compared_txbb = (u8)((0x07C00 & odm_get_rf_reg(dm, (enum rf_path)path, RF_0x5c, RFREGOFFSETMASK)) >> 10);
+		} else {
+			compared_pad = (u8)((0xe0 & odm_get_rf_reg(dm, (enum rf_path)path, RF_0x56, RFREGOFFSETMASK)) >> 5);
+			compared_txbb = (u8)((0x1f & odm_get_rf_reg(dm, (enum rf_path)path, RF_0x56, RFREGOFFSETMASK)));
+		}
+		if (i == 0x1f) {
+			/*boundaryselect = compared_txbb;*/
+			boundaryselect = 0x1f;
+			tmp_pad = compared_pad;
+		}
+		if (compared_pad < tmp_pad) {
+			boundaryselect = boundaryselect + (i << (j * 5));
+			tmp_pad = compared_pad;
+			j++;
+		}
+
+		if (j >= 4)
+			break;
+	}
+
+#else
+	boundaryselect = 0x0;
+#endif
+	odm_set_rf_reg(dm, RF_PATH_A, RF_0x00, RFREGOFFSETMASK, rf_backup_reg00);
+	odm_write_4byte(dm, 0x1bbc, boundaryselect);
+}
+
+u8 _dpk_get_dpk_tx_agc_8821c(struct dm_struct *dm, u8 path)
+{
+	u8 tx_agc_init_value = 0x1f; /* DPK TXAGC value*/
+	u32 rf_reg00 = 0x0;
+	u8 gainloss = 0x1;
+	u8 best_tx_agc, txagcindpk = 0x0;
+	u8 tmp;
+	boolean fail = true;
+	u32 IQK_CMD = 0xf8000d18;
+
+	/* rf_reg00 = 0x40000 + tx_agc_init_value;  set TXAGC value */
+	if (*dm->band_type == ODM_BAND_5G) {
+		tx_agc_init_value = 0x1c;
+		rf_reg00 = 0x40000 + tx_agc_init_value; /* set TXAGC value*/
+#if 0
+		/*rf_reg00 = 0x54000 + tx_agc_init_value;*/ /* set TXAGC value*/
+#endif
+		odm_write_4byte(dm, 0x1bc8, 0x000c55aa);
+		odm_set_rf_reg(dm, RF_PATH_A, RF_0x8f, RFREGOFFSETMASK, 0xa9c00);
+	} else {
+		tx_agc_init_value = 0x17;
+		rf_reg00 = 0x44000 + tx_agc_init_value; /* set TXAGC value*/
+#if 0
+		/*rf_reg00 = 0x54000 + tx_agc_init_value; */ /* set TXAGC value*/
+#endif
+		odm_write_4byte(dm, 0x1bc8, 0x000c44aa);
+		odm_set_rf_reg(dm, RF_PATH_A, RF_0x8f, RFREGOFFSETMASK, 0xaec00);
+	}
+	odm_set_rf_reg(dm, RF_PATH_A, RF_0x00, RFREGOFFSETMASK, rf_reg00);
+	odm_set_bb_reg(dm, R_0x1b8c, BIT(15) | BIT(14) | BIT(13), gainloss);
+	odm_set_bb_reg(dm, R_0x1bc8, BIT(31), 0x1);
+	odm_set_bb_reg(dm, R_0x8f8, BIT(25) | BIT(24) | BIT(23) | BIT(22), 0x5);
+
+	_dpk_set_bbtxagc_8821c(dm, RF_PATH_A);
+	txagcindpk = _dpk_get_txagcindpk_8821c(dm, RF_PATH_A);
+
+	if (odm_get_rf_reg(dm, path, RF_0x08, RFREGOFFSETMASK) != 0x0)
+		odm_set_rf_reg(dm, path, RF_0x8, RFREGOFFSETMASK, 0x0);
+	;
+#if 0
+	/*ODM_sleep_ms(1);*/
+#endif
+	ODM_delay_ms(1);
+	odm_write_4byte(dm, 0x1b00, IQK_CMD);
+	odm_write_4byte(dm, 0x1b00, IQK_CMD + 1);
+
+	fail = _iqk_check_nctl_done_8821c(dm, path, IQK_CMD);
+
+	odm_write_4byte(dm, 0x1b90, 0x0001e018);
+#if 0
+	/*
+	RF_DBG(dm, DBG_RF_IQK,
+		"[DPK]rf_reg00 =0x%x, 0x8F =0x%x, txagcindpk =0x%x\n",
+		odm_get_rf_reg(dm, path, RF_0x00, RFREGOFFSETMASK),
+		odm_get_rf_reg(dm, path, RF_0x8f, RFREGOFFSETMASK),txagcindpk);
+*/
+#endif
+
+	odm_write_4byte(dm, 0x1bd4, 0x60001);
+	tmp = (u8)odm_read_4byte(dm, 0x1bfc);
+	best_tx_agc = tx_agc_init_value - (0xa - tmp);
+#if 0
+/*
+	RF_DBG(dm, DBG_RF_IQK,
+		"[DPK](2), 0x1b8c =0x%x, rf_reg00 = 0x%x, 0x1b00 = 0x%x, 0x1bfc = 0x%x, 0x1bd4 = 0x%x,best_tx_agc =0x%x, 0x1bfc[7:0] =0x%x\n",
+		odm_read_4byte(dm, 0x1b8c),
+		odm_get_rf_reg(dm, path, RF_0x00, RFREGOFFSETMASK),
+		odm_read_4byte(dm, 0x1b00),
+		odm_read_4byte(dm, 0x1bfc), odm_read_4byte(dm, 0x1bd4),
+		best_tx_agc, tmp);
+*/
+#endif
+/* dbg message*/
+#if 0
+
+	RF_DBG(dm, DBG_RF_IQK, "[DPK] 0x1bcc = 0x%x, 0x1bb8 =0x%x\n",
+	       odm_read_4byte(dm, 0x1bcc), odm_read_4byte(dm, 0x1bb8));
+
+	odm_write_4byte(dm, 0x1bcc, 0x118f8800);
+	for (i = 0 ; i < 8; i++) {
+		odm_write_4byte(dm, 0x1b90, 0x0101e018 + i);
+		odm_write_4byte(dm, 0x1bd4, 0x00060000);
+		RF_DBG(dm, DBG_RF_IQK, "0x%x\n", odm_read_4byte(dm, 0x1bfc));
+		odm_write_4byte(dm, 0x1bd4, 0x00070000);
+		RF_DBG(dm, DBG_RF_IQK, "0x%x\n", odm_read_4byte(dm, 0x1bfc));
+		odm_write_4byte(dm, 0x1bd4, 0x00080000);
+		RF_DBG(dm, DBG_RF_IQK, "0x%x\n", odm_read_4byte(dm, 0x1bfc));
+		odm_write_4byte(dm, 0x1bd4, 0x00090000);
+		RF_DBG(dm, DBG_RF_IQK, "0x%x\n", odm_read_4byte(dm, 0x1bfc));
+	}
+
+	odm_write_4byte(dm, 0x1b90, 0x0001e018);
+
+#endif
+	return best_tx_agc;
+}
+
+boolean
+_dpk_enable_dpk_8821c(struct dm_struct *dm, u8 path, u8 best_tx_agc)
+{
+	u32 rf_reg00 = 0x0;
+	boolean fail = true;
+	u32 IQK_CMD = 0xf8000e18;
+
+	if (*dm->band_type == ODM_BAND_5G)
+		rf_reg00 = 0x40000 + best_tx_agc; /* set TXAGC value*/
+	else
+		rf_reg00 = 0x44000 + best_tx_agc; /* set TXAGC value*/
+	odm_set_rf_reg(dm, RF_PATH_A, RF_0x00, RFREGOFFSETMASK, rf_reg00);
+	_dpk_set_dpk_pa_scan(dm, RF_PATH_A);
+
+	/*ODM_sleep_ms(1);*/
+	ODM_delay_ms(1);
+	odm_set_bb_reg(dm, R_0x1bc8, BIT(31), 0x1);
+	odm_write_4byte(dm, 0x8f8, 0x41400080);
+
+	if (odm_get_rf_reg(dm, path, RF_0x08, RFREGOFFSETMASK) != 0x0)
+		odm_set_rf_reg(dm, path, RF_0x8, RFREGOFFSETMASK, 0x0);
+
+	/*ODM_sleep_ms(1);*/
+	ODM_delay_ms(1);
+	odm_write_4byte(dm, 0x1b00, IQK_CMD);
+	odm_write_4byte(dm, 0x1b00, IQK_CMD + 1);
+
+	odm_write_4byte(dm, 0x1b90, 0x0001e018);
+	odm_write_4byte(dm, 0x1bd4, 0xA0001);
+	fail = _iqk_check_nctl_done_8821c(dm, path, IQK_CMD);
+#if 0
+/*
+	RF_DBG(dm, DBG_RF_IQK,
+		"[DPK] (3) 0x1b0b = 0x%x, 0x1bc8 = 0x%x, rf_reg00 = 0x%x, ,0x1bfc = 0x%x, 0x1b90=0x%x, 0x1b94=0x%x\n",
+		odm_read_1byte(dm, 0x1b0b), odm_read_4byte(dm, 0x1bc8), odm_get_rf_reg(dm, path, RF_0x00, RFREGOFFSETMASK),
+		odm_read_4byte(dm, 0x1bfc), odm_read_4byte(dm, 0x1b90), odm_read_4byte(dm, 0x1b94));
+*/
+#endif
+#if 0 /* dbg message*/
+	u8 delay_count = 0x0;
+    u8 i;
+	u32 tmp;
+	odm_write_4byte(dm, 0x1b00, 0xf8000008);
+	odm_write_4byte(dm, 0x1b08, 0x00000080);
+	odm_write_4byte(dm, 0x1bd4, 0x00040001);
+
+	RF_DBG(dm, DBG_RF_IQK, "[DPK] SRAM value!!!\n");
+
+	for (i = 0 ; i < 64; i++) {
+		/*odm_write_4byte(dm, 0x1b90, 0x0101e018+i);*/
+		odm_write_4byte(dm, 0x1bdc, 0xc0000081 + i * 2);
+
+		RF_DBG(dm, DBG_RF_IQK, "0x%x\n", odm_read_4byte(dm, 0x1bfc));
+	}
+	odm_write_4byte(dm, 0x1bd4, 0x00050001);
+	for (i = 0 ; i < 64; i++) {
+		/*odm_write_4byte(dm, 0x1b90, 0x0101e018+i);*/
+		odm_write_4byte(dm, 0x1bdc, 0xc0000081 + i * 2);
+
+		RF_DBG(dm, DBG_RF_IQK, "0x%x\n", odm_read_4byte(dm, 0x1bfc));
+	}
+
+	/*odm_write_4byte(dm, 0x1b08, 0x00000080);*/
+	odm_write_4byte(dm, 0x1bd4, 0xA0001);
+	odm_write_4byte(dm, 0x1bdc, 0x00000000);
+#endif
+	return fail;
+}
+
+boolean
+_dpk_enable_dpd_8821c(struct dm_struct *dm, u8 path, u8 best_tx_agc)
+{
+	boolean fail = true;
+	u8 offset = 0x0;
+	u32 IQK_CMD = 0xf8000f18;
+	u8 external_pswf_gain;
+	boolean gain_scaling_enable = false;
+
+	odm_set_bb_reg(dm, R_0x1bc8, BIT(31), 0x1);
+	odm_write_4byte(dm, 0x8f8, 0x41400080);
+	if (odm_get_rf_reg(dm, path, RF_0x08, RFREGOFFSETMASK) != 0x0)
+		odm_set_rf_reg(dm, path, RF_0x8, RFREGOFFSETMASK, 0x0);
+	/*ODM_sleep_ms(1);*/
+	ODM_delay_ms(1);
+	odm_write_4byte(dm, 0x1b00, IQK_CMD);
+	odm_write_4byte(dm, 0x1b00, IQK_CMD + 1);
+	fail = _iqk_check_nctl_done_8821c(dm, path, IQK_CMD);
+
+	odm_write_4byte(dm, 0x1b90, 0x0001e018);
+	odm_write_4byte(dm, 0x1bd4, 0xA0001);
+
+	if (!fail) {
+		odm_write_4byte(dm, 0x1bcf, 0x19);
+		odm_write_4byte(dm, 0x1bdc, 0x0);
+		/*add 2db extrnal for compensate performnace, the reason is unknown*/
+		external_pswf_gain = 0x2;
+		best_tx_agc = best_tx_agc + external_pswf_gain;
+
+		if (best_tx_agc >= 0x19)
+			offset = best_tx_agc - 0x19;
+		else
+			offset = 0x20 - (0x19 - best_tx_agc);
+		odm_set_bb_reg(dm, R_0x1bd0, BIT(12) | BIT(11) | BIT(10) | BIT(9) | BIT(8), offset);
+		if (gain_scaling_enable)
+			_dpk_set_gain_scaling(dm, RF_PATH_A);
+		else
+			odm_write_4byte(dm, 0x1b98, 0x4c004c00);
+
+	} else {
+		RF_DBG(dm, DBG_RF_IQK,
+		       "[DPK](4)0x1b08 =%x, 0x1bc8 = 0x%x,0x1bfc = 0x%x, ,0x1bd0 = 0x%x, offset =%x, 1bcc =%x\n",
+		       odm_read_4byte(dm, 0x1b08), odm_read_4byte(dm, 0x1bc8),
+		       odm_read_1byte(dm, 0x1bfc), odm_read_4byte(dm, 0x1bd0),
+		       offset, odm_read_4byte(dm, 0x1bcc));
+	}
+
+	return fail;
+}
+
+void _phy_dpd_calibrate_8821c(struct dm_struct *dm, boolean reset)
+{
+	u32 backup_dpdbb[3];
+	u8 best_tx_agc = 0x1c;
+	u32 MAC_backup[MAC_REG_NUM_8821C], RF_backup[RF_REG_NUM_8821C][1];
+	u32 backup_mac_reg[MAC_REG_NUM_8821C] = {0x520, 0x550, 0x1518};
+	u32 BB_backup[DPK_BB_REG_NUM_8821C];
+	u32 backup_bb_reg[DPK_BB_REG_NUM_8821C] = {0x808, 0x90c, 0xc00, 0xcb0, 0xcb4, 0xcbc, 0x1990, 0x9a4, 0xa04, 0xc58, 0xc5c, 0xe58, 0xe5c, 0xc6c, 0xe6c, 0x90c, 0xc94, 0xe94, 0x1904, 0xcb0, 0xcb4, 0xcbc, 0xc00};
+	u32 backup_rf_reg[RF_REG_NUM_8821C] = {0xdf, 0xde, 0x8f, 0x0, 0x1};
+	u8 i;
+	u32 backup_dpk_reg[3] = {0x1bd0, 0x1b98, 0x1bbc};
+
+	struct dm_iqk_info *iqk_info = &dm->IQK_info;
+	iqk_info->is_btg = (boolean)odm_get_bb_reg(dm, R_0xcb8, BIT(16));
+	if (!(*dm->mp_mode))
+		if (_iqk_reload_iqk_8821c(dm, reset))
+			return;
+	if (!(*dm->band_type == ODM_BAND_5G))
+		return;
+
+	RF_DBG(dm, DBG_RF_IQK, "[DPK]==========DPK strat!!!!!==========\n");
+	RF_DBG(dm, DBG_RF_IQK,
+	       "[DPK]band_type = %s, band_width = %d, ExtPA2G = %d, ext_pa_5g = %d\n",
+	       (*dm->band_type == ODM_BAND_5G) ? "5G" : "2G", *dm->band_width,
+	       dm->ext_pa, dm->ext_pa_5g);
+	_iqk_backup_mac_bb_8821c(dm, MAC_backup, BB_backup, backup_mac_reg, backup_bb_reg, DPK_BB_REG_NUM_8821C);
+	_iqk_afe_setting_8821c(dm, true);
+	_iqk_backup_rf_8821c(dm, RF_backup, backup_rf_reg);
+
+	if (iqk_info->is_btg) {
+	} else {
+		if (*dm->band_type == ODM_BAND_2_4G)
+			odm_set_bb_reg(dm, R_0xcb8, BIT(8), 0x1);
+		else
+			odm_set_bb_reg(dm, R_0xcb8, BIT(8), 0x0);
+	}
+
+	/*backup 0x1b2c, 1b38,0x1b3c*/
+	backup_dpdbb[0] = odm_read_4byte(dm, 0x1b2c);
+	backup_dpdbb[1] = odm_read_4byte(dm, 0x1b38);
+	backup_dpdbb[2] = odm_read_4byte(dm, 0x1b3c);
+	RF_DBG(dm, DBG_RF_IQK, "[DPK]In DPD Process(1), Backup\n");
+
+	/*PDK Init Register setting*/
+	_dpk_clear_sram_8821c(dm, RF_PATH_A);
+	_dpk_setting_8821c(dm, RF_PATH_A);
+	_dpk_boundary_selection_8821c(dm, RF_PATH_A);
+	odm_set_bb_reg(dm, R_0x1bc8, BIT(31), 0x1);
+	odm_set_bb_reg(dm, R_0x8f8, BIT(25) | BIT(24) | BIT(23) | BIT(22), 0x5);
+	/* Get the best TXAGC*/
+
+	best_tx_agc = _dpk_get_dpk_tx_agc_8821c(dm, RF_PATH_A);
+#if 0
+	/*ODM_sleep_ms(2);*/
+#endif
+
+	ODM_delay_ms(2);
+	RF_DBG(dm, DBG_RF_IQK, "[DPK]In DPD Process(2), Best TXAGC = 0x%x\n",
+	       best_tx_agc);
+
+	if (_dpk_enable_dpk_8821c(dm, RF_PATH_A, best_tx_agc)) {
+		RF_DBG(dm, DBG_RF_IQK,
+		       "[DPK]In DPD Process(3), DPK process is Fail\n");
+	}
+#if 0
+	/*ODM_sleep_ms(2);*/
+#endif
+	ODM_delay_ms(2);
+	if (_dpk_enable_dpd_8821c(dm, RF_PATH_A, best_tx_agc)) {
+		RF_DBG(dm, DBG_RF_IQK,
+		       "[DPK]In DPD Process(4), DPD process is Fail\n");
+	}
+	/* restore IQK */
+	iqk_info->rf_reg18 = odm_get_rf_reg(dm, RF_PATH_A, RF_0x18, RFREGOFFSETMASK);
+	_iqk_reload_iqk_setting_8821c(dm, 0, 2);
+	_iqk_fill_iqk_report_8821c(dm, 0);
+#if 0
+	/*
+	RF_DBG(dm, DBG_RF_IQK,
+		"[DPK]reload IQK result before, iqk_info->rf_reg18=0x%x, iqk_info->iqk_channel[0]=0x%x, iqk_info->iqk_channel[1]=0x%x!!!!\n",
+		iqk_info->rf_reg18, iqk_info->iqk_channel[0], iqk_info->iqk_channel[1]);
+      */
+#endif
+
+	/* Restore setup */
+#if 0
+	/*_dpk_readsram_8821c(dm, RF_PATH_A);*/
+#endif
+	_dpk_restore_8821c(dm, RF_PATH_A);
+	odm_set_bb_reg(dm, R_0x8f8, BIT(25) | BIT(24) | BIT(23) | BIT(22), 0x5);
+	odm_set_bb_reg(dm, R_0x1bd4, BIT(20) | BIT(19) | BIT(18) | BIT(17) | BIT(16), 0x0);
+	odm_set_bb_reg(dm, R_0x1b00, BIT(2) | BIT(1), 0x0);
+	odm_set_bb_reg(dm, R_0x1b08, BIT(6) | BIT(5), 0x2);
+
+	odm_write_4byte(dm, 0x1b2c, backup_dpdbb[0]);
+	odm_write_4byte(dm, 0x1b38, backup_dpdbb[1]);
+	odm_write_4byte(dm, 0x1b3c, backup_dpdbb[2]);
+	/*enable DPK*/
+	odm_set_bb_reg(dm, R_0x1b2c, BIT(7) | BIT(6) | BIT(5) | BIT(4) | BIT(3) | BIT(2) | BIT(1) | BIT(0), 0x5);
+/*enable boundary condition*/
+#if dpk_forcein_sram4 /* disable : froce in sram4*/
+	odm_set_bb_reg(dm, R_0x1bcc, BIT(27), 0x1);
+#endif
+	odm_write_4byte(dm, 0x1bcc, 0x11868800);
+	RF_DBG(dm, DBG_RF_IQK, "[DPK]In DPD Process(5), Restore\n");
+	_iqk_restore_mac_bb_8821c(dm, MAC_backup, BB_backup, backup_mac_reg, backup_bb_reg, DPK_BB_REG_NUM_8821C);
+	_iqk_afe_setting_8821c(dm, false);
+	_iqk_restore_rf_8821c(dm, backup_rf_reg, RF_backup);
+	/*toggle dynamic_pwr_threshold*/
+
+	/* backup the DPK current result*/
+	for (i = 0; i < DPK_BACKUP_REG_NUM_8821C; i++)
+		dpk_result[i] = odm_read_4byte(dm, backup_dpk_reg[i]);
+
+	RF_DBG(dm, DBG_RF_IQK,
+	       "[DPK]the DPD calibration Process Finish (6), 0x1bd0 = 0x%x, 0x1b98 = 0x%x, 0x1bbc0= 0x%x\n",
+	       dpk_result[0], dpk_result[1], dpk_result[2]);
+}
+
+u32 _iqk_tximr_selfcheck_8821c(void *dm_void, u8 tone_index, u8 path)
+{
+	u32 tx_ini_power_H[2], tx_ini_power_L[2];
+	u32 tmp1, tmp2, tmp3, tmp4, tmp5;
+	u32 IQK_CMD;
+	u32 tximr = 0x0;
+	u8 i;
+
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	/*backup*/
+	odm_write_4byte(dm, 0x1b00, 0xf8000008 | path << 1);
+	odm_write_4byte(dm, 0x1bc8, 0x80000000);
+	odm_write_4byte(dm, 0x8f8, 0x41400080);
+	tmp1 = odm_read_4byte(dm, 0x1b0c);
+	tmp2 = odm_read_4byte(dm, 0x1b14);
+	tmp3 = odm_read_4byte(dm, 0x1b1c);
+	tmp4 = odm_read_4byte(dm, 0x1b20);
+	tmp5 = odm_read_4byte(dm, 0x1b24);
+	/*setup*/
+	odm_write_4byte(dm, 0x1b0c, 0x00003000);
+	odm_write_4byte(dm, 0x1b1c, 0xA2193C32);
+	odm_write_1byte(dm, 0x1b15, 0x00);
+	odm_write_4byte(dm, 0x1b20, (u32)(tone_index << 20 | 0x00040008));
+	odm_write_4byte(dm, 0x1b24, (u32)(tone_index << 20 | 0x00060008));
+	odm_write_4byte(dm, 0x1b2c, 0x07);
+	odm_write_4byte(dm, 0x1b38, 0x20000000);
+	odm_write_4byte(dm, 0x1b3c, 0x20000000);
+	/* ======derive pwr1========*/
+	for (i = 0; i < 2; i++) {
+		if (i == 0)
+			odm_write_4byte(dm, 0x1bcc, 0x0f);
+		else
+			odm_write_4byte(dm, 0x1bcc, 0x09);
+		/* One Shot*/
+		IQK_CMD = 0x00000800;
+		odm_write_4byte(dm, 0x1b34, IQK_CMD + 1);
+		odm_write_4byte(dm, 0x1b34, IQK_CMD);
+		ODM_delay_ms(1);
+		odm_write_4byte(dm, 0x1bd4, 0x00040001);
+		tx_ini_power_H[i] = odm_read_4byte(dm, 0x1bfc);
+		odm_write_4byte(dm, 0x1bd4, 0x000C0001);
+		tx_ini_power_L[i] = odm_read_4byte(dm, 0x1bfc);
+	}
+	/*restore*/
+	odm_write_4byte(dm, 0x1b0c, tmp1);
+	odm_write_4byte(dm, 0x1b14, tmp2);
+	odm_write_4byte(dm, 0x1b1c, tmp3);
+	odm_write_4byte(dm, 0x1b20, tmp4);
+	odm_write_4byte(dm, 0x1b24, tmp5);
+
+	if (tx_ini_power_H[1] == tx_ini_power_H[0])
+		tximr = (3 * (halrf_psd_log2base(tx_ini_power_L[0] << 2) - halrf_psd_log2base(tx_ini_power_L[1]))) / 100;
+	else
+		tximr = 0;
+	return tximr;
+}
+
+u32 _iqk_rximr_selfcheck_8821c(void *dm_void, u8 tone_index, u8 path,
+			       u32 tmp1b38)
+{
+	u32 rx_ini_power_H[2], rx_ini_power_L[2]; /*[0]: psd tone; [1]: image tone*/
+	u32 tmp1, tmp2, tmp3, tmp4, tmp5;
+	u32 IQK_CMD, tmp1bcc;
+	u8 i;
+	u32 rximr = 0x0;
+
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+
+	/*backup*/
+	odm_write_4byte(dm, 0x1b00, 0xf8000008 | path << 1);
+	tmp1 = odm_read_4byte(dm, 0x1b0c);
+	tmp2 = odm_read_4byte(dm, 0x1b14);
+	tmp3 = odm_read_4byte(dm, 0x1b1c);
+	tmp4 = odm_read_4byte(dm, 0x1b20);
+	tmp5 = odm_read_4byte(dm, 0x1b24);
+
+	tmp1bcc = (odm_read_4byte(dm, 0x1be8) & 0x0000ff00) >> 8;
+	odm_write_4byte(dm, 0x1b0c, 0x00001000);
+	odm_write_1byte(dm, 0x1b15, 0x00);
+	odm_write_4byte(dm, 0x1b1c, 0x82193d31);
+	odm_write_4byte(dm, 0x1b20, (u32)(tone_index << 20 | 0x00040008));
+	odm_write_4byte(dm, 0x1b24, (u32)(tone_index << 20 | 0x00060048));
+	odm_write_4byte(dm, 0x1b2c, 0x07);
+#if 0
+	//odm_write_4byte(dm, 0x1b38, iqk_info->rxk1_tmp1b38[path][(tone_index&0xff0)>>4]);
+#endif
+	odm_write_4byte(dm, 0x1b38, tmp1b38);
+
+	odm_write_4byte(dm, 0x1b3c, 0x20000000);
+	odm_write_4byte(dm, 0x1bcc, tmp1bcc);
+	for (i = 0; i < 2; i++) {
+		if (i == 0)
+			odm_write_4byte(dm, 0x1b1c, 0x82193d31);
+		else
+			odm_write_4byte(dm, 0x1b1c, 0xA2193d31);
+		IQK_CMD = 0x00000800;
+		odm_write_4byte(dm, 0x1b34, IQK_CMD + 1);
+		odm_write_4byte(dm, 0x1b34, IQK_CMD);
+		ODM_delay_us(2000);
+		odm_write_1byte(dm, 0x1bd6, 0xb);
+#if 0
+		/*if ((boolean)odm_get_bb_reg(dm, R_0x1bfc, BIT(1))){*/
+#endif
+		if (1) {
+			odm_write_1byte(dm, 0x1bd6, 0x5);
+			rx_ini_power_H[i] = odm_read_4byte(dm, 0x1bfc);
+			odm_write_1byte(dm, 0x1bd6, 0xe);
+			rx_ini_power_L[i] = odm_read_4byte(dm, 0x1bfc);
+		} else {
+			rx_ini_power_H[i] = 0x0;
+			rx_ini_power_L[i] = 0x0;
+		}
+	}
+	/*restore*/
+	odm_write_4byte(dm, 0x1b0c, tmp1);
+	odm_write_4byte(dm, 0x1b14, tmp2);
+	odm_write_4byte(dm, 0x1b1c, tmp3);
+	odm_write_4byte(dm, 0x1b20, tmp4);
+	odm_write_4byte(dm, 0x1b24, tmp5);
+
+	for (i = 0; i < 2; i++)
+		rx_ini_power_H[i] = (rx_ini_power_H[i] & 0xf8000000) >> 27;
+
+	if (rx_ini_power_H[0] != rx_ini_power_H[1])
+		switch (rx_ini_power_H[0]) {
+		case 1:
+			rx_ini_power_L[0] = (u32)((rx_ini_power_L[0] >> 1) | 0x80000000);
+			rx_ini_power_L[1] = (u32)rx_ini_power_L[1] >> 1;
+			break;
+		case 2:
+			rx_ini_power_L[0] = (u32)((rx_ini_power_L[0] >> 2) | 0x80000000);
+			rx_ini_power_L[1] = (u32)rx_ini_power_L[1] >> 2;
+			break;
+		case 3:
+			rx_ini_power_L[0] = (u32)((rx_ini_power_L[0] >> 2) | 0xc0000000);
+			rx_ini_power_L[1] = (u32)rx_ini_power_L[1] >> 2;
+			break;
+		case 4:
+			rx_ini_power_L[0] = (u32)((rx_ini_power_L[0] >> 3) | 0x80000000);
+			rx_ini_power_L[1] = (u32)rx_ini_power_L[1] >> 3;
+			break;
+		case 5:
+			rx_ini_power_L[0] = (u32)((rx_ini_power_L[0] >> 3) | 0xa0000000);
+			rx_ini_power_L[1] = (u32)rx_ini_power_L[1] >> 3;
+			break;
+		case 6:
+			rx_ini_power_L[0] = (u32)((rx_ini_power_L[0] >> 3) | 0xc0000000);
+			rx_ini_power_L[1] = (u32)rx_ini_power_L[1] >> 3;
+			break;
+		case 7:
+			rx_ini_power_L[0] = (u32)((rx_ini_power_L[0] >> 3) | 0xe0000000);
+			rx_ini_power_L[1] = (u32)rx_ini_power_L[1] >> 3;
+			break;
+		default:
+			break;
+		}
+	rximr = (u32)(3 * ((halrf_psd_log2base(rx_ini_power_L[0] / 100) - halrf_psd_log2base(rx_ini_power_L[1] / 100))) / 100);
+#if 0
+	/*
+		RF_DBG(dm, DBG_RF_IQK, "%-20s: 0x%x, 0x%x, 0x%x, 0x%x,0x%x, tone_index=%x, rximr= %d\n",
+		(path == 0) ? "PATH A RXIMR ": "PATH B RXIMR",
+		rx_ini_power_H[0], rx_ini_power_L[0], rx_ini_power_H[1], rx_ini_power_L[1], tmp1bcc, tone_index, rximr);
+*/
+#endif
+	return rximr;
+}
+
+void _iqk_start_imr_test_8821c(void *dm_void, u8 path)
+{
+	u8 imr_limit, i, tone_index;
+	u32 tmp;
+	boolean KFAIL;
+	u32 rxk1_tmp1b38[2][15];
+	u32 imr_result[2];
+
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+
+	/*TX IMR*/
+	if (*dm->band_width == 2)
+		imr_limit = 0xe;
+	else if (*dm->band_width == 1)
+		imr_limit = 0x7;
+	else
+		imr_limit = 0x3;
+
+	_iqk_txk_setting_8821c(dm, RF_PATH_A);
+	KFAIL = _iqk_one_shot_8821c(dm, RF_PATH_A, TXIQK);
+	for (i = 0x0; i <= imr_limit; i++) {
+		tone_index = (u8)(0x08 | i << 4);
+		imr_result[RF_PATH_A] = _iqk_tximr_selfcheck_8821c(dm, tone_index, RF_PATH_A);
+		RF_DBG(dm, DBG_RF_IQK, "[IQK]toneindex = %x, TXIMR = %d\n",
+		       tone_index, imr_result[RF_PATH_A]);
+	}
+	RF_DBG(dm, DBG_RF_IQK, "\n");
+	/*RX IMR*/
+	/*get the rxk1 tone index 0x1b38 setting*/
+	_iqk_rxk1setting_8821c(dm, path);
+	tmp = odm_read_4byte(dm, 0x1b1c);
+	for (path = 0; path < SS_8821C; path++) {
+		for (i = 0; i <= imr_limit; i++) {
+			tone_index = (u8)(0x08 | i << 4);
+			KFAIL = _iqk_rx_iqk_gain_search_fail_by_toneindex_8821c(dm, path, RXIQK1, tone_index);
+			if (!KFAIL) {
+				odm_write_4byte(dm, 0x1b1c, 0xa2193c32);
+				odm_write_4byte(dm, 0x1b14, 0xe5);
+				odm_write_4byte(dm, 0x1b14, 0x0);
+				rxk1_tmp1b38[path][i] = odm_read_4byte(dm, 0x1b38);
+			} else {
+				rxk1_tmp1b38[path][i] = 0x0;
+			}
+		}
+	}
+	_iqk_rxk2setting_8821c(dm, path, true);
+	for (path = 0; path < SS_8821C; path++) {
+		for (i = 0x0; i <= imr_limit; i++) {
+			tone_index = (u8)(0x08 | i << 4);
+			imr_result[RF_PATH_A] = _iqk_rximr_selfcheck_8821c(dm, tone_index, RF_PATH_A, rxk1_tmp1b38[path][i]);
+			RF_DBG(dm, DBG_RF_IQK,
+			       "[IQK]toneindex = %x, RXIMR = %d\n", tone_index,
+			       imr_result[RF_PATH_A]);
+		}
+	}
+	odm_write_4byte(dm, 0x1b1c, tmp);
+	odm_write_4byte(dm, 0x1b38, 0x20000000);
+}
+
+void _phy_iq_calibrate_8821c(struct dm_struct *dm, boolean reset,
+			     boolean segment_iqk, boolean do_imr_test)
+{
+	u32 MAC_backup[MAC_REG_NUM_8821C], BB_backup[BB_REG_NUM_8821C];
+	u32 RF_backup[RF_REG_NUM_8821C][1];
+	u32 backup_mac_reg[MAC_REG_NUM_8821C] = {0x520, 0x550, 0x1518};
+	u32 backup_bb_reg[BB_REG_NUM_8821C] = {0x808, 0x90c, 0xc00, 0xcb0,
+						0xcb4, 0xcbc, 0x1990,
+						0x9a4, 0xa04, 0x838};
+	u32 backup_rf_reg[RF_REG_NUM_8821C] = {0xdf, 0xde, 0x8f, 0x0, 0x1};
+	boolean is_mp = false;
+
+	struct dm_iqk_info *iqk_info = &dm->IQK_info;
+
+	if (*dm->mp_mode)
+		is_mp = true;
+	else if (dm->is_linked)
+		segment_iqk = false;
+	iqk_info->is_btg = (boolean)odm_get_bb_reg(dm, R_0xcb8, BIT(16));
+
+	if (!is_mp)
+		if (_iqk_reload_iqk_8821c(dm, reset))
+			return;
+	if (!do_imr_test)
+		RF_DBG(dm, DBG_RF_IQK,
+		       "[IQK]==========IQK strat!!!!!==========\n");
+	RF_DBG(dm, DBG_RF_IQK,
+	       "[IQK]band_type = %s, band_width = %d, ExtPA2G = %d, ext_pa_5g = %d\n",
+	       (*dm->band_type == ODM_BAND_5G) ? "5G" : "2G", *dm->band_width,
+	       dm->ext_pa, dm->ext_pa_5g);
+	RF_DBG(dm, DBG_RF_IQK, "[IQK]Interface = %d, cut_version = %x\n",
+	       dm->support_interface, dm->cut_version);
+
+	iqk_info->tmp_gntwl = _iqk_indirect_read_reg(dm, 0x38);
+	iqk_info->iqk_times++;
+	iqk_info->kcount = 0;
+	dm->rf_calibrate_info.iqk_total_progressing_time = 0;
+	dm->rf_calibrate_info.iqk_step = 1;
+	iqk_info->rxiqk_step = 1;
+	iqk_info->is_reload = false;
+
+	_iqk_backup_iqk_8821c(dm, 0x0, 0x0);
+	_iqk_backup_mac_bb_8821c(dm, MAC_backup, BB_backup, backup_mac_reg, backup_bb_reg, BB_REG_NUM_8821C);
+	_iqk_backup_rf_8821c(dm, RF_backup, backup_rf_reg);
+
+	while (1) {
+		if (!is_mp)
+			dm->rf_calibrate_info.iqk_start_time = odm_get_current_time(dm);
+
+		_iqk_configure_macbb_8821c(dm);
+		_iqk_afe_setting_8821c(dm, true);
+		_iqk_rfe_setting_8821c(dm, false);
+		_iqk_agc_bnd_int_8821c(dm);
+		_iqk_rfsetting_8821c(dm);
+		if (do_imr_test) {
+			_iqk_start_imr_test_8821c(dm, 0x0);
+			dm->rf_calibrate_info.iqk_step = 4;
+		} else {
+			_iqk_start_iqk_8821c(dm, segment_iqk);
+		}
+		_iqk_afe_setting_8821c(dm, false);
+		_iqk_restore_mac_bb_8821c(dm, MAC_backup, BB_backup, backup_mac_reg, backup_bb_reg, BB_REG_NUM_8821C);
+		_iqk_restore_rf_8821c(dm, backup_rf_reg, RF_backup);
+
+		if (!is_mp) {
+			dm->rf_calibrate_info.iqk_progressing_time = odm_get_progressing_time(dm, dm->rf_calibrate_info.iqk_start_time);
+			dm->rf_calibrate_info.iqk_total_progressing_time += odm_get_progressing_time(dm, dm->rf_calibrate_info.iqk_start_time);
+			RF_DBG(dm, DBG_RF_IQK,
+			       "[IQK]IQK progressing_time = %lld ms\n",
+			       dm->rf_calibrate_info.iqk_progressing_time);
+		}
+
+		if (dm->rf_calibrate_info.iqk_step == 4)
+			break;
+
+		iqk_info->kcount = 0;
+		RF_DBG(dm, DBG_RF_IQK, "[IQK]delay 50ms!!!\n");
+#if 0
+		/*ODM_sleep_ms(50);*/
+#endif
+		ODM_delay_ms(50);
+	}
+
+	if (!do_imr_test) {
+		if (segment_iqk)
+			_iqk_reload_iqk_setting_8821c(dm, 0x0, 0x1);
+		_iqk_fill_iqk_report_8821c(dm, 0);
+		if (!is_mp)
+			RF_DBG(dm, DBG_RF_IQK,
+			       "[IQK]Total IQK progressing_time = %lld ms\n",
+			       dm->rf_calibrate_info.iqk_total_progressing_time)
+			       ;
+		RF_DBG(dm, DBG_RF_IQK,
+		       "[IQK]==========IQK end!!!!!==========\n");
+		RF_DBG(dm, DBG_RF_IQK, "[IQK]check 0x49c = %x\n",
+		       odm_read_1byte(dm, 0x49c));
+	}
+}
+
+void _phy_iq_calibrate_by_fw_8821c(void *dm_void, u8 clear, u8 segment_iqk)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	enum hal_status status = HAL_STATUS_FAILURE;
+
+	if (*dm->mp_mode)
+		clear = 0x1;
+	else if (dm->is_linked)
+		segment_iqk = 0x1;
+
+	status = odm_iq_calibrate_by_fw(dm, clear, segment_iqk);
+
+	if (status == HAL_STATUS_SUCCESS)
+		RF_DBG(dm, DBG_RF_IQK, "[IQK]FWIQK  OK!!!\n");
+	else
+		RF_DBG(dm, DBG_RF_IQK, "[IQK]FWIQK fail!!!\n");
+}
+
+/*********debug message start**************/
+
+void _phy_iqk_XYM_Read_Using_0x1b38_8821c(struct dm_struct *dm, u8 path)
+{
+	u32 tmp = 0x0;
+	u32 tmp2;
+	u8 i;
+
+	tmp = odm_read_4byte(dm, 0x1b1c);
+	odm_write_4byte(dm, 0x1b1c, 0xA2193C32);
+	RF_DBG(dm, DBG_RF_IQK, "\n");
+	for (i = 0; i < 0xa; i++) {
+		odm_write_4byte(dm, 0x1b14, 0xe6 + i);
+		odm_write_4byte(dm, 0x1b14, 0x0);
+		tmp2 = odm_read_4byte(dm, 0x1b38);
+		RF_DBG(dm, DBG_RF_IQK, "%x\n", tmp2);
+	}
+	odm_write_4byte(dm, 0x1b1c, tmp);
+	RF_DBG(dm, DBG_RF_IQK, "\n");
+	odm_write_4byte(dm, 0x1b38, 0x20000000);
+}
+
+void _phy_iqk_debug_inner_lpbk_psd_8821c(struct dm_struct *dm, u8 path)
+{
+	s16 tx_x;
+	s16 tx_y;
+	u32 temp = 0x0;
+	u32 psd_pwr = 0x0;
+	u32 tmp1, tmp2, tmp3, tmp4, tmp5, tmp6, tmp7, tmp8, tmp9, tmp10;
+
+	tmp1 = odm_read_4byte(dm, 0x1b20);
+	tmp2 = odm_read_4byte(dm, 0x1b24);
+	tmp3 = odm_read_4byte(dm, 0x1b15);
+	tmp4 = odm_read_4byte(dm, 0x1b18);
+	tmp5 = odm_read_4byte(dm, 0x1b1c);
+	tmp6 = odm_read_4byte(dm, 0x1b28);
+	tmp7 = odm_read_4byte(dm, 0x1b90);
+	tmp8 = odm_read_4byte(dm, 0x1bcc);
+	tmp9 = odm_read_4byte(dm, 0x1b2c);
+	tmp10 = odm_read_4byte(dm, 0x1b30);
+	odm_write_4byte(dm, 0x1b20, 0x03840008);
+	odm_write_4byte(dm, 0x1b24, 0x03860008);
+	odm_write_1byte(dm, 0x1b15, 0x00);
+	odm_write_4byte(dm, 0x1b18, 0x00010101);
+	odm_write_4byte(dm, 0x1b1c, 0x02effcb2);
+	odm_write_4byte(dm, 0x1b28, 0x00060c00);
+	odm_write_4byte(dm, 0x1b90, 0x00080003);
+	odm_write_4byte(dm, 0x1bcc, 0x00000009);
+	odm_write_4byte(dm, 0x1b2c, 0x20000003);
+	odm_write_4byte(dm, 0x1b30, 0x20000000);
+	RF_DBG(dm, DBG_RF_IQK, "\n");
+	for (tx_x = 507; tx_x <= 532; tx_x++) {
+		for (tx_y = 0; tx_y <= 10 + 20; tx_y++) {
+			if (tx_y < 0)
+				temp = (tx_x << 20) | (tx_y + 2048) << 8;
+			else
+				temp = (tx_x << 20) | (tx_y << 8);
+			odm_write_4byte(dm, 0x1b38, temp);
+			odm_write_4byte(dm, 0x1b3c, 0x20000000);
+			odm_write_4byte(dm, 0x1b34, 0x00000801);
+			odm_write_4byte(dm, 0x1b34, 0x00000800);
+			ODM_delay_ms(2);
+			/*PSD_bef_K*/
+			odm_write_4byte(dm, 0x1bd4, 0x000c0001);
+			psd_pwr = odm_read_4byte(dm, 0x1bfc);
+			RF_DBG(dm, DBG_RF_IQK, "%d ", psd_pwr);
+		}
+	}
+	RF_DBG(dm, DBG_RF_IQK, "\n");
+	odm_write_4byte(dm, 0x1b20, tmp1);
+	odm_write_4byte(dm, 0x1b24, tmp2);
+	odm_write_4byte(dm, 0x1b15, tmp3);
+	odm_write_4byte(dm, 0x1b18, tmp4);
+	odm_write_4byte(dm, 0x1b1c, tmp5);
+	odm_write_4byte(dm, 0x1b28, tmp6);
+	odm_write_4byte(dm, 0x1b90, tmp7);
+	odm_write_4byte(dm, 0x1bcc, tmp8);
+	odm_write_4byte(dm, 0x1b2c, tmp9);
+	odm_write_4byte(dm, 0x1b30, tmp10);
+	odm_write_4byte(dm, 0x1b38, 0x20000000);
+}
+
+void _iqk_readsram_8821c(struct dm_struct *dm, u8 path)
+{
+	u32 tmp1bd4, tmp1bd8, tmp;
+	u8 i;
+
+	tmp1bd4 = odm_read_4byte(dm, 0x1bd4);
+	tmp1bd8 = odm_read_4byte(dm, 0x1bd8);
+	odm_write_4byte(dm, 0x1bd4, 0x00010001);
+	for (i = 0; i < 0x80; i++) {
+		odm_write_4byte(dm, 0x1bd8, 0xa0000101 + (u32)(i << 1));
+		tmp = (u32)odm_read_4byte(dm, 0x1bfc) & 0x3ff;
+		if (i < 0x40)
+			RF_DBG(dm, DBG_RF_IQK, "adc_i[%d] = %x\n", i, tmp);
+		else
+			RF_DBG(dm, DBG_RF_IQK, "adc_q[%d] = %x\n", i, tmp);
+	}
+}
+
+void do_imr_test_8821c(void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+
+	RF_DBG(dm, DBG_RF_IQK,
+	       "[IQK]  ************IMR Test *****************\n");
+	_phy_iq_calibrate_8821c(dm, false, false, true);
+	RF_DBG(dm, DBG_RF_IQK,
+	       "[IQK]  **********End IMR Test *******************\n");
+}
+
+/*********debug message end***************/
+
+/*IQK version:0x23, NCTL:0x8*/
+/*1. modify the iqk counters for coex.*/
+
+void phy_iq_calibrate_8821c(void *dm_void, boolean clear, boolean segment_iqk)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct _hal_rf_ *rf = &dm->rf_table;
+
+	if (!(*dm->mp_mode))
+		_iqk_check_coex_status(dm, true);
+
+	RF_DBG(dm, DBG_RF_IQK, "[IQK]fw_ver= 0x%x\n", rf->fw_ver);
+	if (*dm->mp_mode)
+		halrf_iqk_hwtx_check(dm, true);
+	/*FW IQK*/
+	if (dm->fw_offload_ability & PHYDM_RF_IQK_OFFLOAD) {
+		_phy_iq_calibrate_by_fw_8821c(dm, clear, segment_iqk);
+		phydm_get_read_counter_8821c(dm);
+		RF_DBG(dm, DBG_RF_IQK, "[IQK]0x38= 0x%x\n",
+		       _iqk_indirect_read_reg(dm, 0x38));
+	} else {
+		_iq_calibrate_8821c_init(dm);
+		_phy_iq_calibrate_8821c(dm, clear, segment_iqk, false);
+	}
+	_iqk_fail_count_8821c(dm);
+
+	if (*dm->mp_mode)
+		halrf_iqk_hwtx_check(dm, false);
+#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
+	_iqk_iqk_fail_report_8821c(dm);
+#endif
+	halrf_iqk_dbg(dm);
+
+	if (!(*dm->mp_mode))
+		_iqk_check_coex_status(dm, false);
+	RF_DBG(dm, DBG_RF_IQK, "[IQK]final 0x49c = %x\n",
+	       odm_read_1byte(dm, 0x49c));
+}
+
+void phy_dp_calibrate_8821c(void *dm_void, boolean clear)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct _hal_rf_ *rf = &dm->rf_table;
+
+#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN))
+	if (odm_check_power_status(dm) == false)
+		return;
+#endif
+
+#if (MP_DRIVER)
+	if ((dm->mp_mode != NULL) && (rf->is_con_tx != NULL) && (rf->is_single_tone != NULL) && (rf->is_carrier_suppresion != NULL))
+		if (*(dm->mp_mode) && ((*(rf->is_con_tx) || *(rf->is_single_tone) || *(rf->is_carrier_suppresion))))
+			return;
+#endif
+
+#if (DM_ODM_SUPPORT_TYPE == ODM_CE)
+	if (!(rf->rf_supportability & HAL_RF_DPK))
+		return;
+#endif
+
+#if DISABLE_BB_RF
+	return;
+#endif
+
+	RF_DBG(dm, DBG_RF_IQK, "[DPK] In PHY, dm->dpk_en == %x\n", rf->dpk_en);
+
+	/*if dpk is not enable*/
+	if (rf->dpk_en == 0x0)
+		return;
+
+	/*start*/
+	if (!dm->rf_calibrate_info.is_iqk_in_progress) {
+		odm_acquire_spin_lock(dm, RT_IQK_SPINLOCK);
+		dm->rf_calibrate_info.is_iqk_in_progress = true;
+		odm_release_spin_lock(dm, RT_IQK_SPINLOCK);
+		if (*dm->mp_mode)
+			dm->rf_calibrate_info.iqk_start_time = odm_get_current_time(dm);
+
+		if (*dm->mp_mode) {
+			/*do DPK*/
+			_phy_dpd_calibrate_8821c(dm, clear);
+			_dpk_toggle_rxagc(dm, clear);
+		}
+
+		if (*dm->mp_mode) {
+			dm->rf_calibrate_info.iqk_progressing_time = odm_get_progressing_time(dm, dm->rf_calibrate_info.iqk_start_time);
+			RF_DBG(dm, DBG_RF_IQK,
+			       "[DPK]DPK progressing_time = %lld ms\n",
+			       dm->rf_calibrate_info.iqk_progressing_time);
+		}
+		odm_acquire_spin_lock(dm, RT_IQK_SPINLOCK);
+		dm->rf_calibrate_info.is_iqk_in_progress = false;
+		odm_release_spin_lock(dm, RT_IQK_SPINLOCK);
+	} else {
+		RF_DBG(dm, DBG_RF_IQK,
+		       "[DPK]== Return the DPK CMD, because the DPK in Progress ==\n");
+	}
+}
+void phy_txtap_calibrate_8821c(void *dm_void, boolean clear)
+{
+	u32 MAC_backup[MAC_REG_NUM_8821C], BB_backup[BB_REG_NUM_8821C], RF_backup[RF_REG_NUM_8821C][1];
+	u32 backup_mac_reg[MAC_REG_NUM_8821C] = {0x520, 0x550, 0x1518};
+	u32 backup_bb_reg[BB_REG_NUM_8821C] = {0x808, 0x90c, 0xc00, 0xcb0, 0xcb4, 0xcbc, 0x1990, 0x9a4, 0xa04};
+	u32 backup_rf_reg[RF_REG_NUM_8821C] = {0xdf, 0xde, 0x8f, 0x0, 0x1};
+
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct dm_iqk_info *iqk_info = &dm->IQK_info;
+
+#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
+	struct _ADAPTER *adapter = dm->adapter;
+
+#if (MP_DRIVER == 1)
+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
+	PMPT_CONTEXT p_mpt_ctx = &(adapter->MptCtx);
+#else
+#ifdef CONFIG_MP_INCLUDED
+	PMPT_CONTEXT p_mpt_ctx = &(adapter->mppriv.mpt_ctx);
+#endif
+#endif
+#endif
+
+	struct _hal_rf_ *rf = &dm->rf_table;
+
+#if (DM_ODM_SUPPORT_TYPE == ODM_CE)
+	if (!(rf->rf_supportability & HAL_RF_IQK))
+		return;
+#endif
+
+#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN))
+	if (odm_check_power_status(adapter) == false)
+		return;
+#endif
+
+#if MP_DRIVER == 1
+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
+	if (p_mpt_ctx->bSingleTone || p_mpt_ctx->bCarrierSuppression)
+		return;
+#else
+#ifdef CONFIG_MP_INCLUDED
+	if (p_mpt_ctx->is_single_tone || p_mpt_ctx->is_carrier_suppression)
+		return;
+#endif
+#endif
+#endif
+#endif
+
+	if (!(*dm->mp_mode))
+		_iqk_check_coex_status(dm, true);
+
+	if ((dm->rf_table.rf_supportability & HAL_RF_TXGAPK))
+		if (iqk_info->lok_fail[RF_PATH_A] == 0 &&
+		    iqk_info->iqk_fail_report[0][RF_PATH_A][TXIQK] == 0 &&
+		    iqk_info->iqk_fail_report[0][RF_PATH_A][RXIQK] == 0) {
+			_iqk_backup_iqk_8821c(dm, 0x0, 0x0);
+			_iqk_backup_mac_bb_8821c(dm, MAC_backup, BB_backup, backup_mac_reg, backup_bb_reg, BB_REG_NUM_8821C);
+			_iqk_backup_rf_8821c(dm, RF_backup, backup_rf_reg);
+
+			_iqk_configure_macbb_8821c(dm);
+			_iqk_afe_setting_8821c(dm, true);
+			_iqk_rfe_setting_8821c(dm, false);
+			_iqk_agc_bnd_int_8821c(dm);
+			_iqk_rfsetting_8821c(dm);
+
+			_phy_txgapk_calibrate_8821c(dm, RF_PATH_A);
+
+			_iqk_afe_setting_8821c(dm, false);
+			_iqk_restore_mac_bb_8821c(dm, MAC_backup, BB_backup, backup_mac_reg, backup_bb_reg, BB_REG_NUM_8821C);
+			_iqk_restore_rf_8821c(dm, backup_rf_reg, RF_backup);
+		}
+}
+void dpk_temperature_compensate_8821c(void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct _hal_rf_ *rf = &dm->rf_table;
+#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
+	void *adapter = dm->adapter;
+	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter));
+	u8 pgthermal = hal_data->eeprom_thermal_meter;
+#else
+	struct rtl8192cd_priv *priv = dm->priv;
+	u8 pgthermal = (u8)priv->pmib->dot11RFEntry.ther;
+
+#endif
+	static u8 dpk_tm_trigger;
+	u8 thermal_value = 0, delta_dpk, i = 0;
+	u8 thermal_value_avg_count = 0;
+	u8 thermal_value_avg_times = 2;
+	u32 thermal_value_avg = 0;
+	u8 tmp, abs_temperature;
+
+	/*if dpk is not enable*/
+	if (rf->dpk_en == 0x0)
+		return;
+	/*if ap mode, disable dpk*/
+	if (DM_ODM_SUPPORT_TYPE & ODM_AP)
+		return;
+	if (!dpk_tm_trigger) {
+		odm_set_rf_reg(dm, RF_PATH_A, RF_0x42, BIT(17) | BIT(16), 0x03);
+#if 0
+		/*RF_DBG(dm, DBG_RF_IQK, "[DPK] (1) Trigger Thermal Meter!!\n");*/
+#endif
+		dpk_tm_trigger = 1;
+		return;
+	}
+
+	/* Initialize */
+	dpk_tm_trigger = 0;
+#if 0
+	/*RF_DBG(dm, DBG_RF_IQK, "[DPK] (2) calculate the thermal !!\n");
+	*/
+#endif
+
+	/* calculate average thermal meter */
+	thermal_value = (u8)odm_get_rf_reg(dm, RF_PATH_A, RF_0x42, 0xfc00); /*0x42: RF Reg[15:10] 88E*/
+	RF_DBG(dm, DBG_RF_IQK, "[DPK] (3) current Thermal Meter = %d\n",
+	       thermal_value);
+
+	dm->rf_calibrate_info.thermal_value_dpk = thermal_value;
+	dm->rf_calibrate_info.thermal_value_avg[dm->rf_calibrate_info.thermal_value_avg_index] = thermal_value;
+	dm->rf_calibrate_info.thermal_value_avg_index++;
+	if (dm->rf_calibrate_info.thermal_value_avg_index == thermal_value_avg_times)
+		dm->rf_calibrate_info.thermal_value_avg_index = 0;
+	for (i = 0; i < thermal_value_avg_times; i++) {
+		if (dm->rf_calibrate_info.thermal_value_avg[i]) {
+			thermal_value_avg += dm->rf_calibrate_info.thermal_value_avg[i];
+			thermal_value_avg_count++;
+		}
+	}
+	if (thermal_value_avg_count) /*Calculate Average thermal_value after average enough times*/
+		thermal_value = (u8)(thermal_value_avg / thermal_value_avg_count);
+	/* compensate the DPK */
+	delta_dpk = (thermal_value > pgthermal) ? (thermal_value - pgthermal) : (pgthermal - thermal_value);
+	tmp = (u8)((dpk_result[0] & 0x00001f00) >> 8);
+	RF_DBG(dm, DBG_RF_IQK,
+	       "[DPK] (5)delta_dpk = %d, eeprom_thermal_meter = %d, tmp=%d\n",
+	       delta_dpk, pgthermal, tmp);
+
+	if (thermal_value > pgthermal) {
+		abs_temperature = thermal_value - pgthermal;
+		if (abs_temperature >= 20)
+			tmp = tmp + 4;
+		else if (abs_temperature >= 15)
+			tmp = tmp + 3;
+		else if (abs_temperature >= 10)
+			tmp = tmp + 2;
+		else if (abs_temperature >= 5)
+			tmp = tmp + 1;
+	} else { /*low temperature*/
+		abs_temperature = pgthermal - thermal_value;
+		if (abs_temperature >= 20)
+			tmp = tmp - 4;
+		else if (abs_temperature >= 15)
+			tmp = tmp - 3;
+		else if (abs_temperature >= 10)
+			tmp = tmp - 2;
+		else if (abs_temperature >= 5)
+			tmp = tmp - 1;
+	}
+
+	odm_set_bb_reg(dm, R_0x1bd0, BIT(12) | BIT(11) | BIT(10) | BIT(9) | BIT(8), tmp);
+	RF_DBG(dm, DBG_RF_IQK,
+	       "[DPK] (6)delta_dpk = %d, eeprom_thermal_meter = %d, new tmp=%d, 0x1bd0=0x%x\n",
+	       delta_dpk, pgthermal, tmp, odm_read_4byte(dm, 0x1bd0));
+}
+
+#endif
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/halrf/rtl8821c/halrf_iqk_8821c.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/halrf/rtl8821c/halrf_iqk_8821c.h
--- linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/halrf/rtl8821c/halrf_iqk_8821c.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/halrf/rtl8821c/halrf_iqk_8821c.h	2020-04-10 16:35:06.821660301 +0300
@@ -0,0 +1,62 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2016 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+
+#ifndef __HALRF_IQK_8821C_H__
+#define __HALRF_IQK_8821C_H__
+
+#if (RTL8821C_SUPPORT == 1)
+/*============================================================*/
+/*Definition */
+/*============================================================*/
+
+/*--------------------------Define Parameters-------------------------------*/
+#define MAC_REG_NUM_8821C 3
+#define BB_REG_NUM_8821C 10
+#define RF_REG_NUM_8821C 5
+#define DPK_BB_REG_NUM_8821C 23
+#define DPK_BACKUP_REG_NUM_8821C 3
+
+#define LOK_delay_8821C 2
+#define GS_delay_8821C 2
+#define WBIQK_delay_8821C 2
+
+#define TXIQK 0
+#define RXIQK 1
+#define SS_8821C 1
+
+/*---------------------------End Define Parameters-------------------------------*/
+
+#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
+void do_iqk_8821c(void *dm_void, u8 delta_thermal_index, u8 thermal_value,
+		  u8 threshold);
+#else
+void do_iqk_8821c(void *dm_void, u8 delta_thermal_index, u8 thermal_value,
+		  u8 threshold);
+#endif
+
+void phy_iq_calibrate_8821c(void *dm_void, boolean clear, boolean segment_iqk);
+
+void phy_dp_calibrate_8821c(void *dm_void, boolean clear);
+
+void do_imr_test_8821c(void *dm_void);
+
+#else /* (RTL8821C_SUPPORT == 0)*/
+
+#define phy_iq_calibrate_8821c(_pdm_void, clear, segment_iqk)
+#define phy_dp_calibrate_8821c(_pDM_VOID, clear)
+
+#endif /* RTL8821C_SUPPORT */
+
+#endif /*#ifndef __HALRF_IQK_8821C_H__*/
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/mp_precomp.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/mp_precomp.h
--- linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/mp_precomp.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/mp_precomp.h	2020-04-10 16:35:06.821660301 +0300
@@ -0,0 +1,24 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017  Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * The full GNU General Public License is included in this distribution in the
+ * file called LICENSE.
+ *
+ * Contact Information:
+ * wlanfae <wlanfae@realtek.com>
+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
+ * Hsinchu 300, Taiwan.
+ *
+ * Larry Finger <Larry.Finger@lwfinger.net>
+ *
+ *****************************************************************************/
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/phydm_acs.c linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/phydm_acs.c
--- linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/phydm_acs.c	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/phydm_acs.c	2020-04-10 16:35:06.822660348 +0300
@@ -0,0 +1,1154 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
+ *
+ *
+ ******************************************************************************/
+
+/* ************************************************************
+ * include files
+ * ************************************************************ */
+#include "mp_precomp.h"
+#include "phydm_precomp.h"
+
+
+u8
+odm_get_auto_channel_select_result(
+	void			*p_dm_void,
+	u8			band
+)
+{
+	struct PHY_DM_STRUCT				*p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
+	struct _ACS_					*p_acs = &p_dm_odm->dm_acs;
+
+#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
+	if (band == ODM_BAND_2_4G) {
+		ODM_RT_TRACE(p_dm_odm, ODM_COMP_ACS, ODM_DBG_LOUD, ("[struct _ACS_] odm_get_auto_channel_select_result(): clean_channel_2g(%d)\n", p_acs->clean_channel_2g));
+		return (u8)p_acs->clean_channel_2g;
+	} else {
+		ODM_RT_TRACE(p_dm_odm, ODM_COMP_ACS, ODM_DBG_LOUD, ("[struct _ACS_] odm_get_auto_channel_select_result(): clean_channel_5g(%d)\n", p_acs->clean_channel_5g));
+		return (u8)p_acs->clean_channel_5g;
+	}
+#else
+	return (u8)p_acs->clean_channel_2g;
+#endif
+
+}
+
+void
+odm_auto_channel_select_setting(
+	void			*p_dm_void,
+	boolean			is_enable
+)
+{
+#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
+	struct PHY_DM_STRUCT					*p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
+	u16						period = 0x2710;/* 40ms in default */
+	u16						nhm_type = 0x7;
+
+	ODM_RT_TRACE(p_dm_odm, ODM_COMP_ACS, ODM_DBG_LOUD, ("odm_auto_channel_select_setting()=========>\n"));
+
+	if (is_enable) {
+		/* 20 ms */
+		period = 0x1388;
+		nhm_type = 0x1;
+	}
+
+	if (p_dm_odm->support_ic_type & ODM_IC_11AC_SERIES) {
+		/* PHY parameters initialize for ac series */
+		odm_write_2byte(p_dm_odm, ODM_REG_CCX_PERIOD_11AC + 2, period);	/* 0x990[31:16]=0x2710	Time duration for NHM unit: 4us, 0x2710=40ms */
+		/* odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH9_TH10_11AC, BIT(8)|BIT9|BIT10, nhm_type);	 */ /* 0x994[9:8]=3			enable CCX */
+	} else if (p_dm_odm->support_ic_type & ODM_IC_11N_SERIES) {
+		/* PHY parameters initialize for n series */
+		odm_write_2byte(p_dm_odm, ODM_REG_CCX_PERIOD_11N + 2, period);	/* 0x894[31:16]=0x2710	Time duration for NHM unit: 4us, 0x2710=40ms */
+		/* odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH9_TH10_11N, BIT(10)|BIT9|BIT8, nhm_type);	 */ /* 0x890[9:8]=3			enable CCX */
+	}
+#endif
+}
+
+void
+odm_auto_channel_select_init(
+	void			*p_dm_void
+)
+{
+#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
+	struct PHY_DM_STRUCT					*p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
+	struct _ACS_						*p_acs = &p_dm_odm->dm_acs;
+	u8						i;
+
+	if (!(p_dm_odm->support_ability & ODM_BB_NHM_CNT))
+		return;
+
+	if (p_acs->is_force_acs_result)
+		return;
+
+	ODM_RT_TRACE(p_dm_odm, ODM_COMP_ACS, ODM_DBG_LOUD, ("odm_auto_channel_select_init()=========>\n"));
+
+	p_acs->clean_channel_2g = 1;
+	p_acs->clean_channel_5g = 36;
+
+	for (i = 0; i < ODM_MAX_CHANNEL_2G; ++i) {
+		p_acs->channel_info_2g[0][i] = 0;
+		p_acs->channel_info_2g[1][i] = 0;
+	}
+
+	if (p_dm_odm->support_ic_type & ODM_IC_11AC_SERIES) {
+		for (i = 0; i < ODM_MAX_CHANNEL_5G; ++i) {
+			p_acs->channel_info_5g[0][i] = 0;
+			p_acs->channel_info_5g[1][i] = 0;
+		}
+	}
+#endif
+}
+
+void
+odm_auto_channel_select_reset(
+	void			*p_dm_void
+)
+{
+#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
+	struct PHY_DM_STRUCT					*p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
+	struct _ACS_						*p_acs = &p_dm_odm->dm_acs;
+
+	if (!(p_dm_odm->support_ability & ODM_BB_NHM_CNT))
+		return;
+
+	if (p_acs->is_force_acs_result)
+		return;
+
+	ODM_RT_TRACE(p_dm_odm, ODM_COMP_ACS, ODM_DBG_LOUD, ("odm_auto_channel_select_reset()=========>\n"));
+
+	odm_auto_channel_select_setting(p_dm_odm, true); /* for 20ms measurement */
+	phydm_nhm_counter_statistics_reset(p_dm_odm);
+#endif
+}
+
+void
+odm_auto_channel_select(
+	void			*p_dm_void,
+	u8			channel
+)
+{
+#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
+	struct PHY_DM_STRUCT					*p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
+	struct _ACS_						*p_acs = &p_dm_odm->dm_acs;
+	u8						channel_idx = 0, search_idx = 0;
+	u16						max_score = 0;
+
+	if (!(p_dm_odm->support_ability & ODM_BB_NHM_CNT)) {
+		ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_auto_channel_select(): Return: support_ability ODM_BB_NHM_CNT is disabled\n"));
+		return;
+	}
+
+	if (p_acs->is_force_acs_result) {
+		ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_auto_channel_select(): Force 2G clean channel = %d, 5G clean channel = %d\n",
+			p_acs->clean_channel_2g, p_acs->clean_channel_5g));
+		return;
+	}
+
+	ODM_RT_TRACE(p_dm_odm, ODM_COMP_ACS, ODM_DBG_LOUD, ("odm_auto_channel_select(): channel = %d=========>\n", channel));
+
+	phydm_get_nhm_counter_statistics(p_dm_odm);
+	odm_auto_channel_select_setting(p_dm_odm, false);
+
+	if (channel >= 1 && channel <= 14) {
+		channel_idx = channel - 1;
+		p_acs->channel_info_2g[1][channel_idx]++;
+
+		if (p_acs->channel_info_2g[1][channel_idx] >= 2)
+			p_acs->channel_info_2g[0][channel_idx] = (p_acs->channel_info_2g[0][channel_idx] >> 1) +
+				(p_acs->channel_info_2g[0][channel_idx] >> 2) + (p_dm_odm->nhm_cnt_0 >> 2);
+		else
+			p_acs->channel_info_2g[0][channel_idx] = p_dm_odm->nhm_cnt_0;
+
+		ODM_RT_TRACE(p_dm_odm, ODM_COMP_ACS, ODM_DBG_LOUD, ("odm_auto_channel_select(): nhm_cnt_0 = %d\n", p_dm_odm->nhm_cnt_0));
+		ODM_RT_TRACE(p_dm_odm, ODM_COMP_ACS, ODM_DBG_LOUD, ("odm_auto_channel_select(): Channel_Info[0][%d] = %d, Channel_Info[1][%d] = %d\n", channel_idx, p_acs->channel_info_2g[0][channel_idx], channel_idx, p_acs->channel_info_2g[1][channel_idx]));
+
+		for (search_idx = 0; search_idx < ODM_MAX_CHANNEL_2G; search_idx++) {
+			if (p_acs->channel_info_2g[1][search_idx] != 0) {
+				if (p_acs->channel_info_2g[0][search_idx] >= max_score) {
+					max_score = p_acs->channel_info_2g[0][search_idx];
+					p_acs->clean_channel_2g = search_idx + 1;
+				}
+			}
+		}
+		ODM_RT_TRACE(p_dm_odm, ODM_COMP_ACS, ODM_DBG_LOUD, ("(1)odm_auto_channel_select(): 2G: clean_channel_2g = %d, max_score = %d\n",
+				p_acs->clean_channel_2g, max_score));
+
+	} else if (channel >= 36) {
+		/* Need to do */
+		p_acs->clean_channel_5g = channel;
+	}
+#endif
+}
+
+#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
+
+void
+phydm_auto_channel_select_setting_ap(
+	void   *p_dm_void,
+	u32  setting,             /* 0: STORE_DEFAULT_NHM_SETTING; 1: RESTORE_DEFAULT_NHM_SETTING, 2: ACS_NHM_SETTING */
+	u32  acs_step
+)
+{
+	struct PHY_DM_STRUCT           *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
+	struct rtl8192cd_priv       *priv           = p_dm_odm->priv;
+	struct _ACS_                    *p_acs         = &p_dm_odm->dm_acs;
+
+	ODM_RT_TRACE(p_dm_odm, ODM_COMP_ACS, ODM_DBG_LOUD, ("odm_AutoChannelSelectSettingAP()=========>\n"));
+
+	/* 3 Store Default setting */
+	if (setting == STORE_DEFAULT_NHM_SETTING) {
+		ODM_RT_TRACE(p_dm_odm, ODM_COMP_ACS, ODM_DBG_LOUD, ("STORE_DEFAULT_NHM_SETTING\n"));
+
+		if (p_dm_odm->support_ic_type & ODM_IC_11AC_SERIES) {  /* store reg0x990, reg0x994, reg0x998, reg0x99c, Reg0x9a0 */
+			p_acs->reg0x990 = odm_read_4byte(p_dm_odm, ODM_REG_CCX_PERIOD_11AC);                /* reg0x990 */
+			p_acs->reg0x994 = odm_read_4byte(p_dm_odm, ODM_REG_NHM_TH9_TH10_11AC);           /* reg0x994 */
+			p_acs->reg0x998 = odm_read_4byte(p_dm_odm, ODM_REG_NHM_TH3_TO_TH0_11AC);       /* reg0x998 */
+			p_acs->reg0x99c = odm_read_4byte(p_dm_odm, ODM_REG_NHM_TH7_TO_TH4_11AC);       /* Reg0x99c */
+			p_acs->reg0x9a0 = odm_read_1byte(p_dm_odm, ODM_REG_NHM_TH8_11AC);                   /* Reg0x9a0, u8 */
+		} else if (p_dm_odm->support_ic_type & ODM_IC_11N_SERIES) {
+			p_acs->reg0x890 = odm_read_4byte(p_dm_odm, ODM_REG_NHM_TH9_TH10_11N);             /* reg0x890 */
+			p_acs->reg0x894 = odm_read_4byte(p_dm_odm, ODM_REG_CCX_PERIOD_11N);                  /* reg0x894 */
+			p_acs->reg0x898 = odm_read_4byte(p_dm_odm, ODM_REG_NHM_TH3_TO_TH0_11N);         /* reg0x898 */
+			p_acs->reg0x89c = odm_read_4byte(p_dm_odm, ODM_REG_NHM_TH7_TO_TH4_11N);         /* Reg0x89c */
+			p_acs->reg0xe28 = odm_read_1byte(p_dm_odm, ODM_REG_NHM_TH8_11N);                     /* Reg0xe28, u8 */
+		}
+	}
+
+	/* 3 Restore Default setting */
+	else if (setting == RESTORE_DEFAULT_NHM_SETTING) {
+		ODM_RT_TRACE(p_dm_odm, ODM_COMP_ACS, ODM_DBG_LOUD, ("RESTORE_DEFAULT_NHM_SETTING\n"));
+
+		if (p_dm_odm->support_ic_type & ODM_IC_11AC_SERIES) {  /* store reg0x990, reg0x994, reg0x998, reg0x99c, Reg0x9a0 */
+			odm_write_4byte(p_dm_odm, ODM_REG_CCX_PERIOD_11AC,          p_acs->reg0x990);
+			odm_write_4byte(p_dm_odm, ODM_REG_NHM_TH9_TH10_11AC,     p_acs->reg0x994);
+			odm_write_4byte(p_dm_odm, ODM_REG_NHM_TH3_TO_TH0_11AC, p_acs->reg0x998);
+			odm_write_4byte(p_dm_odm, ODM_REG_NHM_TH7_TO_TH4_11AC, p_acs->reg0x99c);
+			odm_write_1byte(p_dm_odm, ODM_REG_NHM_TH8_11AC,             p_acs->reg0x9a0);
+		} else if (p_dm_odm->support_ic_type & ODM_IC_11N_SERIES) {
+			odm_write_4byte(p_dm_odm, ODM_REG_NHM_TH9_TH10_11N,     p_acs->reg0x890);
+			odm_write_4byte(p_dm_odm, ODM_REG_CCX_PERIOD_11AC,          p_acs->reg0x894);
+			odm_write_4byte(p_dm_odm, ODM_REG_NHM_TH3_TO_TH0_11N, p_acs->reg0x898);
+			odm_write_4byte(p_dm_odm, ODM_REG_NHM_TH7_TO_TH4_11N, p_acs->reg0x89c);
+			odm_write_1byte(p_dm_odm, ODM_REG_NHM_TH8_11N,             p_acs->reg0xe28);
+		}
+	}
+
+	/* 3 struct _ACS_ setting */
+	else if (setting == ACS_NHM_SETTING) {
+		ODM_RT_TRACE(p_dm_odm, ODM_COMP_ACS, ODM_DBG_LOUD, ("ACS_NHM_SETTING\n"));
+		u16  period;
+		period = 0x61a8;
+		p_acs->acs_step = acs_step;
+
+		if (p_dm_odm->support_ic_type & ODM_IC_11AC_SERIES) {
+			/* 4 Set NHM period, 0x990[31:16]=0x61a8, Time duration for NHM unit: 4us, 0x61a8=100ms */
+			odm_write_2byte(p_dm_odm, ODM_REG_CCX_PERIOD_11AC + 2, period);
+			/* 4 Set NHM ignore_cca=1, ignore_txon=1, ccx_en=0 */
+			odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH9_TH10_11AC, BIT(8) | BIT(9) | BIT(10), 3);
+
+			if (p_acs->acs_step == 0) {
+				/* 4 Set IGI */
+				odm_set_bb_reg(p_dm_odm, 0xc50, BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(5) | BIT(6), 0x3E);
+				if (get_rf_mimo_mode(priv) != MIMO_1T1R)
+					odm_set_bb_reg(p_dm_odm, 0xe50, BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(5) | BIT(6), 0x3E);
+
+				/* 4 Set struct _ACS_ NHM threshold */
+				odm_write_4byte(p_dm_odm, ODM_REG_NHM_TH3_TO_TH0_11AC, 0x82786e64);
+				odm_write_4byte(p_dm_odm, ODM_REG_NHM_TH7_TO_TH4_11AC, 0xffffff8c);
+				odm_write_1byte(p_dm_odm, ODM_REG_NHM_TH8_11AC, 0xff);
+				odm_write_2byte(p_dm_odm, ODM_REG_NHM_TH9_TH10_11AC + 2, 0xffff);
+
+			} else if (p_acs->acs_step == 1) {
+				/* 4 Set IGI */
+				odm_set_bb_reg(p_dm_odm, 0xc50, BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(5) | BIT(6), 0x2A);
+				if (get_rf_mimo_mode(priv) != MIMO_1T1R)
+					odm_set_bb_reg(p_dm_odm, 0xe50, BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(5) | BIT(6), 0x2A);
+
+				/* 4 Set struct _ACS_ NHM threshold */
+				odm_write_4byte(p_dm_odm, ODM_REG_NHM_TH3_TO_TH0_11AC, 0x5a50463c);
+				odm_write_4byte(p_dm_odm, ODM_REG_NHM_TH7_TO_TH4_11AC, 0xffffff64);
+
+			}
+
+		} else if (p_dm_odm->support_ic_type & ODM_IC_11N_SERIES) {
+			/* 4 Set NHM period, 0x894[31:16]=0x61a8, Time duration for NHM unit: 4us, 0x61a8=100ms */
+			odm_write_2byte(p_dm_odm, ODM_REG_CCX_PERIOD_11AC + 2, period);
+			/* 4 Set NHM ignore_cca=1, ignore_txon=1, ccx_en=0 */
+			odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH9_TH10_11N, BIT(8) | BIT(9) | BIT(10), 3);
+
+			if (p_acs->acs_step == 0) {
+				/* 4 Set IGI */
+				odm_set_bb_reg(p_dm_odm, 0xc50, BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(5) | BIT(6), 0x3E);
+				if (get_rf_mimo_mode(priv) != MIMO_1T1R)
+					odm_set_bb_reg(p_dm_odm, 0xc58, BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(5) | BIT(6), 0x3E);
+
+				/* 4 Set struct _ACS_ NHM threshold */
+				odm_write_4byte(p_dm_odm, ODM_REG_NHM_TH3_TO_TH0_11N, 0x82786e64);
+				odm_write_4byte(p_dm_odm, ODM_REG_NHM_TH7_TO_TH4_11N, 0xffffff8c);
+				odm_write_1byte(p_dm_odm, ODM_REG_NHM_TH8_11N, 0xff);
+				odm_write_2byte(p_dm_odm, ODM_REG_NHM_TH9_TH10_11N + 2, 0xffff);
+
+			} else if (p_acs->acs_step == 1) {
+				/* 4 Set IGI */
+				odm_set_bb_reg(p_dm_odm, 0xc50, BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(5) | BIT(6), 0x2A);
+				if (get_rf_mimo_mode(priv) != MIMO_1T1R)
+					odm_set_bb_reg(p_dm_odm, 0xc58, BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(5) | BIT(6), 0x2A);
+
+				/* 4 Set struct _ACS_ NHM threshold */
+				odm_write_4byte(p_dm_odm, ODM_REG_NHM_TH3_TO_TH0_11N, 0x5a50463c);
+				odm_write_4byte(p_dm_odm, ODM_REG_NHM_TH7_TO_TH4_11N, 0xffffff64);
+
+			}
+		}
+	}
+
+}
+
+void
+phydm_get_nhm_statistics_ap(
+	void       *p_dm_void,
+	u32      idx,                /* @ 2G, Real channel number = idx+1 */
+	u32      acs_step
+)
+{
+	struct PHY_DM_STRUCT	*p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
+	struct rtl8192cd_priv     *priv    = p_dm_odm->priv;
+	struct _ACS_                  *p_acs    = &p_dm_odm->dm_acs;
+	u32                value32 = 0;
+	u8                i;
+
+	p_acs->acs_step = acs_step;
+
+	if (p_dm_odm->support_ic_type & ODM_IC_11N_SERIES) {
+		/* 4 Check if NHM result is ready */
+		for (i = 0; i < 20; i++) {
+
+			ODM_delay_ms(1);
+			if (odm_get_bb_reg(p_dm_odm, REG_FPGA0_PSD_REPORT, BIT(17)))
+				break;
+		}
+
+		/* 4 Get NHM Statistics */
+		if (p_acs->acs_step == 1) {
+
+			value32 = odm_read_4byte(p_dm_odm, ODM_REG_NHM_CNT7_TO_CNT4_11N);
+
+			p_acs->nhm_cnt[idx][9] = (value32 & MASKBYTE1) >> 8;
+			p_acs->nhm_cnt[idx][8] = (value32 & MASKBYTE0);
+
+			value32 = odm_read_4byte(p_dm_odm, ODM_REG_NHM_CNT_11N);   /* ODM_REG_NHM_CNT3_TO_CNT0_11N */
+
+			p_acs->nhm_cnt[idx][7] = (value32 & MASKBYTE3) >> 24;
+			p_acs->nhm_cnt[idx][6] = (value32 & MASKBYTE2) >> 16;
+			p_acs->nhm_cnt[idx][5] = (value32 & MASKBYTE1) >> 8;
+
+		} else if (p_acs->acs_step == 2) {
+
+			value32 = odm_read_4byte(p_dm_odm, ODM_REG_NHM_CNT_11N);  /* ODM_REG_NHM_CNT3_TO_CNT0_11N */
+
+			p_acs->nhm_cnt[idx][4] = odm_read_1byte(p_dm_odm, ODM_REG_NHM_CNT7_TO_CNT4_11N);
+			p_acs->nhm_cnt[idx][3] = (value32 & MASKBYTE3) >> 24;
+			p_acs->nhm_cnt[idx][2] = (value32 & MASKBYTE2) >> 16;
+			p_acs->nhm_cnt[idx][1] = (value32 & MASKBYTE1) >> 8;
+			p_acs->nhm_cnt[idx][0] = (value32 & MASKBYTE0);
+		}
+	} else if (p_dm_odm->support_ic_type & ODM_IC_11AC_SERIES) {
+		/* 4 Check if NHM result is ready */
+		for (i = 0; i < 20; i++) {
+
+			ODM_delay_ms(1);
+			if (odm_get_bb_reg(p_dm_odm, ODM_REG_NHM_DUR_READY_11AC, BIT(16)))
+				break;
+		}
+
+		if (p_acs->acs_step == 1) {
+
+			value32 = odm_read_4byte(p_dm_odm, ODM_REG_NHM_CNT7_TO_CNT4_11AC);
+
+			p_acs->nhm_cnt[idx][9] = (value32 & MASKBYTE1) >> 8;
+			p_acs->nhm_cnt[idx][8] = (value32 & MASKBYTE0);
+
+			value32 = odm_read_4byte(p_dm_odm, ODM_REG_NHM_CNT_11AC);    /* ODM_REG_NHM_CNT3_TO_CNT0_11AC */
+
+			p_acs->nhm_cnt[idx][7] = (value32 & MASKBYTE3) >> 24;
+			p_acs->nhm_cnt[idx][6] = (value32 & MASKBYTE2) >> 16;
+			p_acs->nhm_cnt[idx][5] = (value32 & MASKBYTE1) >> 8;
+
+		} else if (p_acs->acs_step == 2) {
+
+			value32 = odm_read_4byte(p_dm_odm, ODM_REG_NHM_CNT_11AC);     /* ODM_REG_NHM_CNT3_TO_CNT0_11AC */
+
+			p_acs->nhm_cnt[idx][4] = odm_read_1byte(p_dm_odm, ODM_REG_NHM_CNT7_TO_CNT4_11AC);
+			p_acs->nhm_cnt[idx][3] = (value32 & MASKBYTE3) >> 24;
+			p_acs->nhm_cnt[idx][2] = (value32 & MASKBYTE2) >> 16;
+			p_acs->nhm_cnt[idx][1] = (value32 & MASKBYTE1) >> 8;
+			p_acs->nhm_cnt[idx][0] = (value32 & MASKBYTE0);
+		}
+	}
+
+}
+
+
+/* #define ACS_DEBUG_INFO */ /* acs debug default off */
+#if 0
+int phydm_AutoChannelSelectAP(
+	void   *p_dm_void,
+	u32  ACS_Type,                      /*  0: RXCount_Type, 1:NHM_Type */
+	u32  available_chnl_num        /*  amount of all channels */
+)
+{
+	struct PHY_DM_STRUCT               *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
+	struct _ACS_                    *p_acs    = &p_dm_odm->dm_acs;
+	struct rtl8192cd_priv			*priv    = p_dm_odm->priv;
+
+	static u32           score2G[MAX_2G_CHANNEL_NUM], score5G[MAX_5G_CHANNEL_NUM];
+	u32                  score[MAX_BSS_NUM], use_nhm = 0;
+	u32                  minScore = 0xffffffff;
+	u32                  tmpScore, tmpIdx = 0;
+	u32                  traffic_check = 0;
+	u32                  fa_count_weighting = 1;
+	int                     i, j, idx = 0, idx_2G_end = -1, idx_5G_begin = -1, minChan = 0;
+	struct bss_desc *pBss = NULL;
+
+#ifdef _DEBUG_RTL8192CD_
+	char tmpbuf[400];
+	int len = 0;
+#endif
+
+	memset(score2G, '\0', sizeof(score2G));
+	memset(score5G, '\0', sizeof(score5G));
+
+	for (i = 0; i < priv->available_chnl_num; i++) {
+		if (priv->available_chnl[i] <= 14)
+			idx_2G_end = i;
+		else
+			break;
+	}
+
+	for (i = 0; i < priv->available_chnl_num; i++) {
+		if (priv->available_chnl[i] > 14) {
+			idx_5G_begin = i;
+			break;
+		}
+	}
+
+	/*  DELETE */
+#ifndef CONFIG_RTL_NEW_AUTOCH
+	for (i = 0; i < priv->site_survey->count; i++) {
+		pBss = &priv->site_survey->bss[i];
+		for (idx = 0; idx < priv->available_chnl_num; idx++) {
+			if (pBss->channel == priv->available_chnl[idx]) {
+				if (pBss->channel <= 14)
+					setChannelScore(idx, score2G, 0, MAX_2G_CHANNEL_NUM - 1);
+				else
+					score5G[idx - idx_5G_begin] += 5;
+				break;
+			}
+		}
+	}
+#endif
+
+	if (idx_2G_end >= 0)
+		for (i = 0; i <= idx_2G_end; i++)
+			score[i] = score2G[i];
+	if (idx_5G_begin >= 0)
+		for (i = idx_5G_begin; i < priv->available_chnl_num; i++)
+			score[i] = score5G[i - idx_5G_begin];
+
+#ifdef CONFIG_RTL_NEW_AUTOCH
+	{
+		u32 y, ch_begin = 0, ch_end = priv->available_chnl_num;
+
+		u32 do_ap_check = 1, ap_ratio = 0;
+
+		if (idx_2G_end >= 0)
+			ch_end = idx_2G_end + 1;
+		if (idx_5G_begin >= 0)
+			ch_begin = idx_5G_begin;
+
+#ifdef ACS_DEBUG_INFO/* for debug */
+		printk("\n");
+		for (y = ch_begin; y < ch_end; y++)
+			printk("1. init: chnl[%d] 20M_rx[%d] 40M_rx[%d] fa_cnt[%d] score[%d]\n",
+			       priv->available_chnl[y],
+			       priv->chnl_ss_mac_rx_count[y],
+			       priv->chnl_ss_mac_rx_count_40M[y],
+			       priv->chnl_ss_fa_count[y],
+			       score[y]);
+		printk("\n");
+#endif
+
+#if defined(CONFIG_RTL_88E_SUPPORT) || defined(CONFIG_WLAN_HAL_8192EE)
+		if (p_dm_odm->support_ic_type & (ODM_RTL8188E | ODM_RTL8192E) && priv->pmib->dot11RFEntry.acs_type) {
+			u32 tmp_score[MAX_BSS_NUM];
+			memcpy(tmp_score, score, sizeof(score));
+			if (find_clean_channel(priv, ch_begin, ch_end, tmp_score)) {
+				/* memcpy(score, tmp_score, sizeof(score)); */
+#ifdef _DEBUG_RTL8192CD_
+				printk("!! Found clean channel, select minimum FA channel\n");
+#endif
+				goto USE_CLN_CH;
+			}
+#ifdef _DEBUG_RTL8192CD_
+			printk("!! Not found clean channel, use NHM algorithm\n");
+#endif
+			use_nhm = 1;
+USE_CLN_CH:
+			for (y = ch_begin; y < ch_end; y++) {
+				for (i = 0; i <= 9; i++) {
+					u32 val32 = priv->nhm_cnt[y][i];
+					for (j = 0; j < i; j++)
+						val32 *= 3;
+					score[y] += val32;
+				}
+
+#ifdef _DEBUG_RTL8192CD_
+				printk("nhm_cnt_%d: H<-[ %3d %3d %3d %3d %3d %3d %3d %3d %3d %3d]->L, score: %d\n",
+				       y + 1, priv->nhm_cnt[y][9], priv->nhm_cnt[y][8], priv->nhm_cnt[y][7],
+				       priv->nhm_cnt[y][6], priv->nhm_cnt[y][5], priv->nhm_cnt[y][4],
+				       priv->nhm_cnt[y][3], priv->nhm_cnt[y][2], priv->nhm_cnt[y][1],
+				       priv->nhm_cnt[y][0], score[y]);
+#endif
+			}
+
+			if (!use_nhm)
+				memcpy(score, tmp_score, sizeof(score));
+
+			goto choose_ch;
+		}
+#endif
+
+		/*  For each channel, weighting behind channels with MAC RX counter */
+		/* For each channel, weighting the channel with FA counter */
+
+		for (y = ch_begin; y < ch_end; y++) {
+			score[y] += 8 * priv->chnl_ss_mac_rx_count[y];
+			if (priv->chnl_ss_mac_rx_count[y] > 30)
+				do_ap_check = 0;
+			if (priv->chnl_ss_mac_rx_count[y] > MAC_RX_COUNT_THRESHOLD)
+				traffic_check = 1;
+
+#ifdef RTK_5G_SUPPORT
+			if (*p_dm_odm->p_band_type == ODM_BAND_2_4G)
+#endif
+			{
+				if ((int)(y - 4) >= (int)ch_begin)
+					score[y - 4] += 2 * priv->chnl_ss_mac_rx_count[y];
+				if ((int)(y - 3) >= (int)ch_begin)
+					score[y - 3] += 8 * priv->chnl_ss_mac_rx_count[y];
+				if ((int)(y - 2) >= (int)ch_begin)
+					score[y - 2] += 8 * priv->chnl_ss_mac_rx_count[y];
+				if ((int)(y - 1) >= (int)ch_begin)
+					score[y - 1] += 10 * priv->chnl_ss_mac_rx_count[y];
+				if ((int)(y + 1) < (int)ch_end)
+					score[y + 1] += 10 * priv->chnl_ss_mac_rx_count[y];
+				if ((int)(y + 2) < (int)ch_end)
+					score[y + 2] += 8 * priv->chnl_ss_mac_rx_count[y];
+				if ((int)(y + 3) < (int)ch_end)
+					score[y + 3] += 8 * priv->chnl_ss_mac_rx_count[y];
+				if ((int)(y + 4) < (int)ch_end)
+					score[y + 4] += 2 * priv->chnl_ss_mac_rx_count[y];
+			}
+
+			/* this is for CH_LOAD caculation */
+			if (priv->chnl_ss_cca_count[y] > priv->chnl_ss_fa_count[y])
+				priv->chnl_ss_cca_count[y] -= priv->chnl_ss_fa_count[y];
+			else
+				priv->chnl_ss_cca_count[y] = 0;
+		}
+
+#ifdef ACS_DEBUG_INFO/* for debug */
+		printk("\n");
+		for (y = ch_begin; y < ch_end; y++)
+			printk("2. after 20M check: chnl[%d] score[%d]\n", priv->available_chnl[y], score[y]);
+		printk("\n");
+#endif
+
+		for (y = ch_begin; y < ch_end; y++) {
+			if (priv->chnl_ss_mac_rx_count_40M[y]) {
+				score[y] += 5 * priv->chnl_ss_mac_rx_count_40M[y];
+				if (priv->chnl_ss_mac_rx_count_40M[y] > 30)
+					do_ap_check = 0;
+				if (priv->chnl_ss_mac_rx_count_40M[y] > MAC_RX_COUNT_THRESHOLD)
+					traffic_check = 1;
+
+#ifdef RTK_5G_SUPPORT
+				if (*p_dm_odm->p_band_type == ODM_BAND_2_4G)
+#endif
+				{
+					if ((int)(y - 6) >= (int)ch_begin)
+						score[y - 6] += 1 * priv->chnl_ss_mac_rx_count_40M[y];
+					if ((int)(y - 5) >= (int)ch_begin)
+						score[y - 5] += 4 * priv->chnl_ss_mac_rx_count_40M[y];
+					if ((int)(y - 4) >= (int)ch_begin)
+						score[y - 4] += 4 * priv->chnl_ss_mac_rx_count_40M[y];
+					if ((int)(y - 3) >= (int)ch_begin)
+						score[y - 3] += 5 * priv->chnl_ss_mac_rx_count_40M[y];
+					if ((int)(y - 2) >= (int)ch_begin)
+						score[y - 2] += (5 * priv->chnl_ss_mac_rx_count_40M[y]) / 2;
+					if ((int)(y - 1) >= (int)ch_begin)
+						score[y - 1] += 5 * priv->chnl_ss_mac_rx_count_40M[y];
+					if ((int)(y + 1) < (int)ch_end)
+						score[y + 1] += 5 * priv->chnl_ss_mac_rx_count_40M[y];
+					if ((int)(y + 2) < (int)ch_end)
+						score[y + 2] += (5 * priv->chnl_ss_mac_rx_count_40M[y]) / 2;
+					if ((int)(y + 3) < (int)ch_end)
+						score[y + 3] += 5 * priv->chnl_ss_mac_rx_count_40M[y];
+					if ((int)(y + 4) < (int)ch_end)
+						score[y + 4] += 4 * priv->chnl_ss_mac_rx_count_40M[y];
+					if ((int)(y + 5) < (int)ch_end)
+						score[y + 5] += 4 * priv->chnl_ss_mac_rx_count_40M[y];
+					if ((int)(y + 6) < (int)ch_end)
+						score[y + 6] += 1 * priv->chnl_ss_mac_rx_count_40M[y];
+				}
+			}
+		}
+
+#ifdef ACS_DEBUG_INFO/* for debug */
+		printk("\n");
+		for (y = ch_begin; y < ch_end; y++)
+			printk("3. after 40M check: chnl[%d] score[%d]\n", priv->available_chnl[y], score[y]);
+		printk("\n");
+		printk("4. do_ap_check=%d traffic_check=%d\n", do_ap_check, traffic_check);
+		printk("\n");
+#endif
+
+		if (traffic_check == 0)
+			fa_count_weighting = 5;
+		else
+			fa_count_weighting = 1;
+
+		for (y = ch_begin; y < ch_end; y++)
+			score[y] += fa_count_weighting * priv->chnl_ss_fa_count[y];
+
+#ifdef ACS_DEBUG_INFO/* for debug */
+		printk("\n");
+		for (y = ch_begin; y < ch_end; y++)
+			printk("5. after fa check: chnl[%d] score[%d]\n", priv->available_chnl[y], score[y]);
+		printk("\n");
+#endif
+
+		if (do_ap_check) {
+			for (i = 0; i < priv->site_survey->count; i++) {
+				pBss = &priv->site_survey->bss[i];
+				for (y = ch_begin; y < ch_end; y++) {
+					if (pBss->channel == priv->available_chnl[y]) {
+						if (pBss->channel <= 14) {
+#ifdef ACS_DEBUG_INFO/* for debug */
+							printk("\n");
+							printk("chnl[%d] has ap rssi=%d bw[0x%02x]\n",
+							       pBss->channel, pBss->rssi, pBss->t_stamp[1]);
+							printk("\n");
+#endif
+							if (pBss->rssi > 60)
+								ap_ratio = 4;
+							else if (pBss->rssi > 35)
+								ap_ratio = 2;
+							else
+								ap_ratio = 1;
+
+							if ((pBss->t_stamp[1] & 0x6) == 0) {
+								score[y] += 50 * ap_ratio;
+								if ((int)(y - 4) >= (int)ch_begin)
+									score[y - 4] += 10 * ap_ratio;
+								if ((int)(y - 3) >= (int)ch_begin)
+									score[y - 3] += 20 * ap_ratio;
+								if ((int)(y - 2) >= (int)ch_begin)
+									score[y - 2] += 30 * ap_ratio;
+								if ((int)(y - 1) >= (int)ch_begin)
+									score[y - 1] += 40 * ap_ratio;
+								if ((int)(y + 1) < (int)ch_end)
+									score[y + 1] += 40 * ap_ratio;
+								if ((int)(y + 2) < (int)ch_end)
+									score[y + 2] += 30 * ap_ratio;
+								if ((int)(y + 3) < (int)ch_end)
+									score[y + 3] += 20 * ap_ratio;
+								if ((int)(y + 4) < (int)ch_end)
+									score[y + 4] += 10 * ap_ratio;
+							} else if ((pBss->t_stamp[1] & 0x4) == 0) {
+								score[y] += 50 * ap_ratio;
+								if ((int)(y - 3) >= (int)ch_begin)
+									score[y - 3] += 20 * ap_ratio;
+								if ((int)(y - 2) >= (int)ch_begin)
+									score[y - 2] += 30 * ap_ratio;
+								if ((int)(y - 1) >= (int)ch_begin)
+									score[y - 1] += 40 * ap_ratio;
+								if ((int)(y + 1) < (int)ch_end)
+									score[y + 1] += 50 * ap_ratio;
+								if ((int)(y + 2) < (int)ch_end)
+									score[y + 2] += 50 * ap_ratio;
+								if ((int)(y + 3) < (int)ch_end)
+									score[y + 3] += 50 * ap_ratio;
+								if ((int)(y + 4) < (int)ch_end)
+									score[y + 4] += 50 * ap_ratio;
+								if ((int)(y + 5) < (int)ch_end)
+									score[y + 5] += 40 * ap_ratio;
+								if ((int)(y + 6) < (int)ch_end)
+									score[y + 6] += 30 * ap_ratio;
+								if ((int)(y + 7) < (int)ch_end)
+									score[y + 7] += 20 * ap_ratio;
+							} else {
+								score[y] += 50 * ap_ratio;
+								if ((int)(y - 7) >= (int)ch_begin)
+									score[y - 7] += 20 * ap_ratio;
+								if ((int)(y - 6) >= (int)ch_begin)
+									score[y - 6] += 30 * ap_ratio;
+								if ((int)(y - 5) >= (int)ch_begin)
+									score[y - 5] += 40 * ap_ratio;
+								if ((int)(y - 4) >= (int)ch_begin)
+									score[y - 4] += 50 * ap_ratio;
+								if ((int)(y - 3) >= (int)ch_begin)
+									score[y - 3] += 50 * ap_ratio;
+								if ((int)(y - 2) >= (int)ch_begin)
+									score[y - 2] += 50 * ap_ratio;
+								if ((int)(y - 1) >= (int)ch_begin)
+									score[y - 1] += 50 * ap_ratio;
+								if ((int)(y + 1) < (int)ch_end)
+									score[y + 1] += 40 * ap_ratio;
+								if ((int)(y + 2) < (int)ch_end)
+									score[y + 2] += 30 * ap_ratio;
+								if ((int)(y + 3) < (int)ch_end)
+									score[y + 3] += 20 * ap_ratio;
+							}
+						} else {
+							if ((pBss->t_stamp[1] & 0x6) == 0)
+								score[y] += 500;
+							else if ((pBss->t_stamp[1] & 0x4) == 0) {
+								score[y] += 500;
+								if ((int)(y + 1) < (int)ch_end)
+									score[y + 1] += 500;
+							} else {
+								score[y] += 500;
+								if ((int)(y - 1) >= (int)ch_begin)
+									score[y - 1] += 500;
+							}
+						}
+						break;
+					}
+				}
+			}
+		}
+
+#ifdef ACS_DEBUG_INFO/* for debug */
+		printk("\n");
+		for (y = ch_begin; y < ch_end; y++)
+			printk("6. after ap check: chnl[%d]:%d\n", priv->available_chnl[y], score[y]);
+		printk("\n");
+#endif
+
+#ifdef SS_CH_LOAD_PROC
+
+		/*  caculate noise level -- suggested by wilson */
+		for (y = ch_begin; y < ch_end; y++)  {
+			int fa_lv = 0, cca_lv = 0;
+			if (priv->chnl_ss_fa_count[y] > 1000)
+				fa_lv = 100;
+			else if (priv->chnl_ss_fa_count[y] > 500)
+				fa_lv = 34 * (priv->chnl_ss_fa_count[y] - 500) / 500 + 66;
+			else if (priv->chnl_ss_fa_count[y] > 200)
+				fa_lv = 33 * (priv->chnl_ss_fa_count[y] - 200) / 300 + 33;
+			else if (priv->chnl_ss_fa_count[y] > 100)
+				fa_lv = 18 * (priv->chnl_ss_fa_count[y] - 100) / 100 + 15;
+			else
+				fa_lv = 15 * priv->chnl_ss_fa_count[y] / 100;
+			if (priv->chnl_ss_cca_count[y] > 400)
+				cca_lv = 100;
+			else if (priv->chnl_ss_cca_count[y] > 200)
+				cca_lv = 34 * (priv->chnl_ss_cca_count[y] - 200) / 200 + 66;
+			else if (priv->chnl_ss_cca_count[y] > 80)
+				cca_lv = 33 * (priv->chnl_ss_cca_count[y] - 80) / 120 + 33;
+			else if (priv->chnl_ss_cca_count[y] > 40)
+				cca_lv = 18 * (priv->chnl_ss_cca_count[y] - 40) / 40 + 15;
+			else
+				cca_lv = 15 * priv->chnl_ss_cca_count[y] / 40;
+
+			priv->chnl_ss_load[y] = (((fa_lv > cca_lv) ? fa_lv : cca_lv) * 75 + ((score[y] > 100) ? 100 : score[y]) * 25) / 100;
+
+			DEBUG_INFO("ch:%d f=%d (%d), c=%d (%d), fl=%d, cl=%d, sc=%d, cu=%d\n",
+				   priv->available_chnl[y],
+				   priv->chnl_ss_fa_count[y], fa_thd,
+				   priv->chnl_ss_cca_count[y], cca_thd,
+				   fa_lv,
+				   cca_lv,
+				   score[y],
+				   priv->chnl_ss_load[y]);
+
+		}
+#endif
+	}
+#endif
+
+choose_ch:
+
+#ifdef DFS
+	/*  heavy weighted DFS channel */
+	if (idx_5G_begin >= 0) {
+		for (i = idx_5G_begin; i < priv->available_chnl_num; i++) {
+			if (!priv->pmib->dot11DFSEntry.disable_DFS && is_DFS_channel(priv->available_chnl[i])
+			    && (score[i] != 0xffffffff))
+				score[i] += 1600;
+		}
+	}
+#endif
+
+
+	/* prevent Auto channel selecting wrong channel in 40M mode----------------- */
+	if ((priv->pmib->dot11BssType.net_work_type & WIRELESS_11N)
+	    && priv->pshare->is_40m_bw) {
+#if 0
+		if (GET_MIB(priv)->dot11nConfigEntry.dot11n2ndChOffset == 1) {
+			/* Upper Primary channel, cannot select the two lowest channels */
+			if (priv->pmib->dot11BssType.net_work_type & WIRELESS_11G) {
+				score[0] = 0xffffffff;
+				score[1] = 0xffffffff;
+				score[2] = 0xffffffff;
+				score[3] = 0xffffffff;
+				score[4] = 0xffffffff;
+
+				score[13] = 0xffffffff;
+				score[12] = 0xffffffff;
+				score[11] = 0xffffffff;
+			}
+
+			/*			if (priv->pmib->dot11BssType.net_work_type & WIRELESS_11A) { */
+			/*				score[idx_5G_begin] = 0xffffffff; */
+			/*				score[idx_5G_begin + 1] = 0xffffffff; */
+			/*			} */
+		} else if (GET_MIB(priv)->dot11nConfigEntry.dot11n2ndChOffset == 2) {
+			/* Lower Primary channel, cannot select the two highest channels */
+			if (priv->pmib->dot11BssType.net_work_type & WIRELESS_11G) {
+				score[0] = 0xffffffff;
+				score[1] = 0xffffffff;
+				score[2] = 0xffffffff;
+
+				score[13] = 0xffffffff;
+				score[12] = 0xffffffff;
+				score[11] = 0xffffffff;
+				score[10] = 0xffffffff;
+				score[9] = 0xffffffff;
+			}
+
+			/*			if (priv->pmib->dot11BssType.net_work_type & WIRELESS_11A) { */
+			/*				score[priv->available_chnl_num - 2] = 0xffffffff; */
+			/*				score[priv->available_chnl_num - 1] = 0xffffffff; */
+			/*			} */
+		}
+#endif
+		for (i = 0; i <= idx_2G_end; ++i)
+			if (priv->available_chnl[i] == 14)
+				score[i] = 0xffffffff;		/*  mask chan14 */
+
+#ifdef RTK_5G_SUPPORT
+		if (idx_5G_begin >= 0) {
+			for (i = idx_5G_begin; i < priv->available_chnl_num; i++) {
+				int ch = priv->available_chnl[i];
+				if (priv->available_chnl[i] > 144)
+					--ch;
+				if ((ch % 4) || ch == 140 || ch == 164)	/* mask ch 140, ch 165, ch 184... */
+					score[i] = 0xffffffff;
+			}
+		}
+#endif
+
+
+	}
+
+	if (priv->pmib->dot11RFEntry.disable_ch1213) {
+		for (i = 0; i <= idx_2G_end; ++i) {
+			int ch = priv->available_chnl[i];
+			if ((ch == 12) || (ch == 13))
+				score[i] = 0xffffffff;
+		}
+	}
+
+	if (((priv->pmib->dot11StationConfigEntry.dot11RegDomain == DOMAIN_GLOBAL) ||
+	     (priv->pmib->dot11StationConfigEntry.dot11RegDomain == DOMAIN_WORLD_WIDE)) &&
+	    (idx_2G_end >= 11) && (idx_2G_end < 14)) {
+		score[13] = 0xffffffff;	/*  mask chan14 */
+		score[12] = 0xffffffff; /*  mask chan13 */
+		score[11] = 0xffffffff; /*  mask chan12 */
+	}
+
+	/* ------------------------------------------------------------------ */
+
+#ifdef _DEBUG_RTL8192CD_
+	for (i = 0; i < priv->available_chnl_num; i++)
+		len += sprintf(tmpbuf + len, "ch%d:%u ", priv->available_chnl[i], score[i]);
+	strcat(tmpbuf, "\n");
+	panic_printk("%s", tmpbuf);
+
+#endif
+
+	if ((*p_dm_odm->p_band_type == ODM_BAND_5G)
+	    && (priv->pmib->dot11nConfigEntry.dot11nUse40M == HT_CHANNEL_WIDTH_80)) {
+		for (i = 0; i < priv->available_chnl_num; i++) {
+			if (is80MChannel(priv->available_chnl, priv->available_chnl_num, priv->available_chnl[i])) {
+				tmpScore = 0;
+				for (j = 0; j < 4; j++) {
+					if ((tmpScore != 0xffffffff) && (score[i + j] != 0xffffffff))
+						tmpScore += score[i + j];
+					else
+						tmpScore = 0xffffffff;
+				}
+				tmpScore = tmpScore / 4;
+				if (minScore > tmpScore) {
+					minScore = tmpScore;
+
+					tmpScore = 0xffffffff;
+					for (j = 0; j < 4; j++) {
+						if (score[i + j] < tmpScore) {
+							tmpScore = score[i + j];
+							tmpIdx = i + j;
+						}
+					}
+
+					idx = tmpIdx;
+				}
+				i += 3;
+			}
+		}
+		if (minScore == 0xffffffff) {
+			/*  there is no 80M channels */
+			priv->pshare->is_40m_bw = HT_CHANNEL_WIDTH_20;
+			for (i = 0; i < priv->available_chnl_num; i++) {
+				if (score[i] < minScore) {
+					minScore = score[i];
+					idx = i;
+				}
+			}
+		}
+	} else if ((*p_dm_odm->p_band_type == ODM_BAND_5G)
+		&& (priv->pmib->dot11nConfigEntry.dot11nUse40M == HT_CHANNEL_WIDTH_20_40)) {
+		for (i = 0; i < priv->available_chnl_num; i++) {
+			if (is40MChannel(priv->available_chnl, priv->available_chnl_num, priv->available_chnl[i])) {
+				tmpScore = 0;
+				for (j = 0; j < 2; j++) {
+					if ((tmpScore != 0xffffffff) && (score[i + j] != 0xffffffff))
+						tmpScore += score[i + j];
+					else
+						tmpScore = 0xffffffff;
+				}
+				tmpScore = tmpScore / 2;
+				if (minScore > tmpScore) {
+					minScore = tmpScore;
+
+					tmpScore = 0xffffffff;
+					for (j = 0; j < 2; j++) {
+						if (score[i + j] < tmpScore) {
+							tmpScore = score[i + j];
+							tmpIdx = i + j;
+						}
+					}
+
+					idx = tmpIdx;
+				}
+				i += 1;
+			}
+		}
+		if (minScore == 0xffffffff) {
+			/*  there is no 40M channels */
+			priv->pshare->is_40m_bw = HT_CHANNEL_WIDTH_20;
+			for (i = 0; i < priv->available_chnl_num; i++) {
+				if (score[i] < minScore) {
+					minScore = score[i];
+					idx = i;
+				}
+			}
+		}
+	} else if ((*p_dm_odm->p_band_type == ODM_BAND_2_4G)
+		&& (priv->pmib->dot11nConfigEntry.dot11nUse40M == HT_CHANNEL_WIDTH_20_40)
+		   && (priv->available_chnl_num >= 8)) {
+		u32 groupScore[14];
+
+		memset(groupScore, 0xff, sizeof(groupScore));
+		for (i = 0; i < priv->available_chnl_num - 4; i++) {
+			if (score[i] != 0xffffffff && score[i + 4] != 0xffffffff) {
+				groupScore[i] = score[i] + score[i + 4];
+				DEBUG_INFO("groupScore, ch %d,%d: %d\n", i + 1, i + 5, groupScore[i]);
+				if (groupScore[i] < minScore) {
+#ifdef AUTOCH_SS_SPEEDUP
+					if (priv->pmib->miscEntry.autoch_1611_enable) {
+						if (priv->available_chnl[i] == 1 || priv->available_chnl[i] == 6 || priv->available_chnl[i] == 11) {
+							minScore = groupScore[i];
+							idx = i;
+						}
+					} else
+#endif
+					{
+						minScore = groupScore[i];
+						idx = i;
+					}
+				}
+			}
+		}
+
+		if (score[idx] < score[idx + 4]) {
+			GET_MIB(priv)->dot11nConfigEntry.dot11n2ndChOffset = HT_2NDCH_OFFSET_ABOVE;
+			priv->pshare->offset_2nd_chan	= HT_2NDCH_OFFSET_ABOVE;
+		} else {
+			idx = idx + 4;
+			GET_MIB(priv)->dot11nConfigEntry.dot11n2ndChOffset = HT_2NDCH_OFFSET_BELOW;
+			priv->pshare->offset_2nd_chan	= HT_2NDCH_OFFSET_BELOW;
+		}
+	} else {
+		for (i = 0; i < priv->available_chnl_num; i++) {
+			if (score[i] < minScore) {
+#ifdef AUTOCH_SS_SPEEDUP
+				if (priv->pmib->miscEntry.autoch_1611_enable) {
+					if (priv->available_chnl[i] == 1 || priv->available_chnl[i] == 6 || priv->available_chnl[i] == 11) {
+						minScore = score[i];
+						idx = i;
+					}
+				} else
+#endif
+				{
+					minScore = score[i];
+					idx = i;
+				}
+			}
+		}
+	}
+
+	if (IS_A_CUT_8881A(priv) &&
+	    (priv->pmib->dot11nConfigEntry.dot11nUse40M == HT_CHANNEL_WIDTH_80)) {
+		if ((priv->available_chnl[idx] == 36) ||
+		    (priv->available_chnl[idx] == 52) ||
+		    (priv->available_chnl[idx] == 100) ||
+		    (priv->available_chnl[idx] == 116) ||
+		    (priv->available_chnl[idx] == 132) ||
+		    (priv->available_chnl[idx] == 149) ||
+		    (priv->available_chnl[idx] == 165))
+			idx++;
+		else if ((priv->available_chnl[idx] == 48) ||
+			 (priv->available_chnl[idx] == 64) ||
+			 (priv->available_chnl[idx] == 112) ||
+			 (priv->available_chnl[idx] == 128) ||
+			 (priv->available_chnl[idx] == 144) ||
+			 (priv->available_chnl[idx] == 161) ||
+			 (priv->available_chnl[idx] == 177))
+			idx--;
+	}
+
+	minChan = priv->available_chnl[idx];
+
+	/*  skip channel 14 if don't support ofdm */
+	if ((priv->pmib->dot11RFEntry.disable_ch14_ofdm) &&
+	    (minChan == 14)) {
+		score[idx] = 0xffffffff;
+
+		minScore = 0xffffffff;
+		for (i = 0; i < priv->available_chnl_num; i++) {
+			if (score[i] < minScore) {
+				minScore = score[i];
+				idx = i;
+			}
+		}
+		minChan = priv->available_chnl[idx];
+	}
+
+#if 0
+	/* Check if selected channel available for 80M/40M BW or NOT ? */
+	if (*p_dm_odm->p_band_type == ODM_BAND_5G) {
+		if (priv->pmib->dot11nConfigEntry.dot11nUse40M == HT_CHANNEL_WIDTH_80) {
+			if (!is80MChannel(priv->available_chnl, priv->available_chnl_num, minChan)) {
+
+				/* priv->pmib->dot11n_config_entry.dot11nUse40M = HT_CHANNEL_WIDTH_20_40; */
+				priv->pshare->is_40m_bw = HT_CHANNEL_WIDTH_20_40;
+			}
+		}
+
+		if (priv->pmib->dot11nConfigEntry.dot11nUse40M == HT_CHANNEL_WIDTH_20_40) {
+			if (!is40MChannel(priv->available_chnl, priv->available_chnl_num, minChan)) {
+
+				/* priv->pmib->dot11n_config_entry.dot11nUse40M = HT_CHANNEL_WIDTH_20; */
+				priv->pshare->is_40m_bw = HT_CHANNEL_WIDTH_20;
+			}
+		}
+	}
+#endif
+
+#ifdef CONFIG_RTL_NEW_AUTOCH
+	RTL_W32(RXERR_RPT, RXERR_RPT_RST);
+#endif
+
+	/*  auto adjust contro-sideband */
+	if ((priv->pmib->dot11BssType.net_work_type & WIRELESS_11N)
+	    && (priv->pshare->is_40m_bw == 1 || priv->pshare->is_40m_bw == 2)) {
+
+#ifdef RTK_5G_SUPPORT
+		if (*p_dm_odm->p_band_type == ODM_BAND_5G) {
+			if ((minChan > 144) ? ((minChan - 1) % 8) : (minChan % 8)) {
+				GET_MIB(priv)->dot11nConfigEntry.dot11n2ndChOffset = HT_2NDCH_OFFSET_ABOVE;
+				priv->pshare->offset_2nd_chan	= HT_2NDCH_OFFSET_ABOVE;
+			} else {
+				GET_MIB(priv)->dot11nConfigEntry.dot11n2ndChOffset = HT_2NDCH_OFFSET_BELOW;
+				priv->pshare->offset_2nd_chan	= HT_2NDCH_OFFSET_BELOW;
+			}
+
+		} else
+#endif
+		{
+#if 0
+#ifdef CONFIG_RTL_NEW_AUTOCH
+			unsigned int ch_max;
+
+			if (priv->available_chnl[idx_2G_end] >= 13)
+				ch_max = 13;
+			else
+				ch_max = priv->available_chnl[idx_2G_end];
+
+			if ((minChan >= 5) && (minChan <= (ch_max - 5))) {
+				if (score[minChan + 4] > score[minChan - 4]) { /*  what if some channels were cancelled? */
+					GET_MIB(priv)->dot11nConfigEntry.dot11n2ndChOffset = HT_2NDCH_OFFSET_BELOW;
+					priv->pshare->offset_2nd_chan	= HT_2NDCH_OFFSET_BELOW;
+				} else {
+					GET_MIB(priv)->dot11nConfigEntry.dot11n2ndChOffset = HT_2NDCH_OFFSET_ABOVE;
+					priv->pshare->offset_2nd_chan	= HT_2NDCH_OFFSET_ABOVE;
+				}
+			} else
+#endif
+			{
+				if (minChan < 5) {
+					GET_MIB(priv)->dot11nConfigEntry.dot11n2ndChOffset = HT_2NDCH_OFFSET_ABOVE;
+					priv->pshare->offset_2nd_chan	= HT_2NDCH_OFFSET_ABOVE;
+				} else if (minChan > 7) {
+					GET_MIB(priv)->dot11nConfigEntry.dot11n2ndChOffset = HT_2NDCH_OFFSET_BELOW;
+					priv->pshare->offset_2nd_chan	= HT_2NDCH_OFFSET_BELOW;
+				}
+			}
+#endif
+		}
+	}
+	/* ----------------------- */
+
+#if defined(__ECOS) && defined(CONFIG_SDIO_HCI)
+	panic_printk("Auto channel choose ch:%d\n", minChan);
+#else
+#ifdef _DEBUG_RTL8192CD_
+	panic_printk("Auto channel choose ch:%d\n", minChan);
+#endif
+#endif
+#ifdef ACS_DEBUG_INFO/* for debug */
+	printk("7. minChan:%d 2nd_offset:%d\n", minChan, priv->pshare->offset_2nd_chan);
+#endif
+
+	return minChan;
+}
+#endif
+
+#endif
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/phydm_acs.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/phydm_acs.h
--- linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/phydm_acs.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/phydm_acs.h	2020-04-10 16:35:06.822660348 +0300
@@ -0,0 +1,105 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
+ *
+ *
+ ******************************************************************************/
+
+#ifndef	__PHYDMACS_H__
+#define    __PHYDMACS_H__
+
+#define ACS_VERSION	"1.1"	/*20150729 by YuChen*/
+#define CLM_VERSION "1.0"
+
+#define ODM_MAX_CHANNEL_2G			14
+#define ODM_MAX_CHANNEL_5G			24
+
+/* For phydm_auto_channel_select_setting_ap() */
+#define STORE_DEFAULT_NHM_SETTING               0
+#define RESTORE_DEFAULT_NHM_SETTING             1
+#define ACS_NHM_SETTING                         2
+
+struct _ACS_ {
+	boolean		is_force_acs_result;
+	u8		clean_channel_2g;
+	u8		clean_channel_5g;
+	u16		channel_info_2g[2][ODM_MAX_CHANNEL_2G];		/* Channel_Info[1]: channel score, Channel_Info[2]:Channel_Scan_Times */
+	u16		channel_info_5g[2][ODM_MAX_CHANNEL_5G];
+
+#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
+	u8              acs_step;
+	/* NHM count 0-11 */
+	u8              nhm_cnt[14][11];
+
+	/* AC-Series, for storing previous setting */
+	u32              reg0x990;
+	u32              reg0x994;
+	u32              reg0x998;
+	u32              reg0x99c;
+	u8              reg0x9a0;   /* u8 */
+
+	/* N-Series, for storing previous setting */
+	u32              reg0x890;
+	u32              reg0x894;
+	u32              reg0x898;
+	u32              reg0x89c;
+	u8              reg0xe28;   /* u8 */
+#endif
+
+};
+
+
+void
+odm_auto_channel_select_init(
+	void			*p_dm_void
+);
+
+void
+odm_auto_channel_select_reset(
+	void			*p_dm_void
+);
+
+void
+odm_auto_channel_select(
+	void			*p_dm_void,
+	u8			channel
+);
+
+u8
+odm_get_auto_channel_select_result(
+	void			*p_dm_void,
+	u8			band
+);
+
+#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
+
+void
+phydm_auto_channel_select_setting_ap(
+	void   *p_dm_void,
+	u32  setting,             /* 0: STORE_DEFAULT_NHM_SETTING; 1: RESTORE_DEFAULT_NHM_SETTING, 2: ACS_NHM_SETTING */
+	u32  acs_step
+);
+
+void
+phydm_get_nhm_statistics_ap(
+	void       *p_dm_void,
+	u32      idx,                /* @ 2G, Real channel number = idx+1 */
+	u32      acs_step
+);
+
+#endif  /* #if ( DM_ODM_SUPPORT_TYPE & ODM_AP ) */
+
+#endif  /* #ifndef	__PHYDMACS_H__ */
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/phydm_adaptivity.c linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/phydm_adaptivity.c
--- linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/phydm_adaptivity.c	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/phydm_adaptivity.c	2020-04-10 16:35:06.822660348 +0300
@@ -0,0 +1,804 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017  Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * The full GNU General Public License is included in this distribution in the
+ * file called LICENSE.
+ *
+ * Contact Information:
+ * wlanfae <wlanfae@realtek.com>
+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
+ * Hsinchu 300, Taiwan.
+ *
+ * Larry Finger <Larry.Finger@lwfinger.net>
+ *
+ *****************************************************************************/
+
+/*@************************************************************
+ * include files
+ ************************************************************/
+#include "mp_precomp.h"
+#include "phydm_precomp.h"
+
+#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
+	#if WPP_SOFTWARE_TRACE
+		#include "PhyDM_Adaptivity.tmh"
+	#endif
+#endif
+#ifdef PHYDM_SUPPORT_ADAPTIVITY
+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
+boolean
+phydm_check_channel_plan(void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct phydm_adaptivity_struct *adapt = (struct phydm_adaptivity_struct *)phydm_get_structure(dm, PHYDM_ADAPTIVITY);
+	void *adapter = dm->adapter;
+	PMGNT_INFO mgnt_info = &((PADAPTER)adapter)->MgntInfo;
+
+	if (mgnt_info->RegEnableAdaptivity != 2)
+		return false;
+
+	if (!dm->carrier_sense_enable) { /*@check domain Code for adaptivity or CarrierSense*/
+		if ((*dm->band_type == ODM_BAND_5G) &&
+		    !(adapt->regulation_5g == REGULATION_ETSI || adapt->regulation_5g == REGULATION_WW)) {
+			PHYDM_DBG(dm, DBG_ADPTVTY,
+				  "adaptivity skip 5G domain code : %d\n",
+				  adapt->regulation_5g);
+			return true;
+		} else if ((*dm->band_type == ODM_BAND_2_4G) &&
+			   !(adapt->regulation_2g == REGULATION_ETSI || adapt->regulation_2g == REGULATION_WW)) {
+			PHYDM_DBG(dm, DBG_ADPTVTY,
+				  "adaptivity skip 2.4G domain code : %d\n",
+				  adapt->regulation_2g);
+			return true;
+		} else if ((*dm->band_type != ODM_BAND_2_4G) && (*dm->band_type != ODM_BAND_5G)) {
+			PHYDM_DBG(dm, DBG_ADPTVTY,
+				  "adaptivity neither 2G nor 5G band, return\n");
+			return true;
+		}
+	} else {
+		if ((*dm->band_type == ODM_BAND_5G) &&
+		    !(adapt->regulation_5g == REGULATION_MKK || adapt->regulation_5g == REGULATION_WW)) {
+			PHYDM_DBG(dm, DBG_ADPTVTY,
+				  "CarrierSense skip 5G domain code : %d\n",
+				  adapt->regulation_5g);
+			return true;
+		} else if ((*dm->band_type == ODM_BAND_2_4G) &&
+			   !(adapt->regulation_2g == REGULATION_MKK || adapt->regulation_2g == REGULATION_WW)) {
+			PHYDM_DBG(dm, DBG_ADPTVTY,
+				  "CarrierSense skip 2.4G domain code : %d\n",
+				  adapt->regulation_2g);
+			return true;
+		} else if ((*dm->band_type != ODM_BAND_2_4G) && (*dm->band_type != ODM_BAND_5G)) {
+			PHYDM_DBG(dm, DBG_ADPTVTY,
+				  "CarrierSense neither 2G nor 5G band, return\n");
+			return true;
+		}
+	}
+
+	return false;
+}
+
+boolean
+phydm_soft_ap_special_set(void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct phydm_adaptivity_struct *adaptivity = (struct phydm_adaptivity_struct *)phydm_get_structure(dm, PHYDM_ADAPTIVITY);
+	u8 disable_ap_adapt_setting = false;
+
+	if (dm->soft_ap_mode != NULL) {
+		if (*dm->soft_ap_mode != 0 &&
+		    (dm->soft_ap_special_setting & BIT(0)))
+			disable_ap_adapt_setting = true;
+		else
+			disable_ap_adapt_setting = false;
+		PHYDM_DBG(dm, DBG_ADPTVTY,
+			  "soft_ap_setting = %x, soft_ap = %d, dis_ap_adapt = %d\n",
+			  dm->soft_ap_special_setting, *dm->soft_ap_mode,
+			  disable_ap_adapt_setting);
+	}
+
+	return disable_ap_adapt_setting;
+}
+#endif
+
+void phydm_dig_up_bound_lmt_en(void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct phydm_adaptivity_struct *adapt = &dm->adaptivity;
+
+	if (!(dm->support_ability & ODM_BB_ADAPTIVITY) ||
+	    !dm->is_linked ||
+	    !adapt->is_adapt_en) {
+		adapt->igi_up_bound_lmt_cnt = 0;
+		adapt->igi_lmt_en = false;
+		return;
+	}
+
+	if (dm->total_tp > 1) {
+		adapt->igi_lmt_en = true;
+		adapt->igi_up_bound_lmt_cnt = adapt->igi_up_bound_lmt_val;
+		PHYDM_DBG(dm, DBG_ADPTVTY,
+			  "TP >1, Start limit IGI upper bound\n");
+	} else {
+		if (adapt->igi_up_bound_lmt_cnt == 0)
+			adapt->igi_lmt_en = false;
+		else
+			adapt->igi_up_bound_lmt_cnt--;
+	}
+
+	PHYDM_DBG(dm, DBG_ADPTVTY, "IGI_lmt_cnt = %d\n",
+		  adapt->igi_up_bound_lmt_cnt);
+}
+
+void phydm_check_adaptivity(void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct phydm_adaptivity_struct *adaptivity = &dm->adaptivity;
+
+	if (!(dm->support_ability & ODM_BB_ADAPTIVITY)) {
+		adaptivity->is_adapt_en = false;
+		return;
+	}
+
+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
+	if (phydm_check_channel_plan(dm) ||
+	    dm->ap_total_num > adaptivity->ap_num_th ||
+	    phydm_soft_ap_special_set(dm)) {
+		adaptivity->is_adapt_en = false;
+		PHYDM_DBG(dm, DBG_ADPTVTY,
+			  "AP total num > %d!!, disable adaptivity\n",
+			  adaptivity->ap_num_th);
+		return;
+	}
+#endif
+
+	adaptivity->is_adapt_en = true;
+}
+
+void phydm_set_edcca_threshold(void *dm_void, s8 H2L, s8 L2H)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+
+	if (dm->support_ic_type & ODM_IC_JGR3_SERIES) {
+		odm_set_bb_reg(dm, R_0x84c, MASKBYTE2, (u8)L2H + 128 - 4);
+		odm_set_bb_reg(dm, R_0x84c, MASKBYTE3, (u8)H2L + 128 - 4);
+	} else if (dm->support_ic_type & ODM_IC_11N_SERIES) {
+		odm_set_bb_reg(dm, R_0xc4c, MASKBYTE0, (u8)L2H);
+		odm_set_bb_reg(dm, R_0xc4c, MASKBYTE2, (u8)H2L);
+	} else if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
+		odm_set_bb_reg(dm, R_0x8a4, MASKBYTE0, (u8)L2H);
+		odm_set_bb_reg(dm, R_0x8a4, MASKBYTE1, (u8)H2L);
+	}
+}
+
+void phydm_mac_edcca_state(void *dm_void, enum phydm_mac_edcca_type state)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+
+	if (state == PHYDM_IGNORE_EDCCA) {
+		odm_set_mac_reg(dm, R_0x520, BIT(15), 1); /*@ignore EDCCA*/
+#if 0
+		/*odm_set_mac_reg(dm, REG_RD_CTRL, BIT(11), 0);*/
+#endif
+	} else { /*@don't set MAC ignore EDCCA signal*/
+		odm_set_mac_reg(dm, R_0x520, BIT(15), 0); /*@don't ignore EDCCA*/
+#if 0
+		/*odm_set_mac_reg(dm, REG_RD_CTRL, BIT(11), 1);*/
+#endif
+	}
+	PHYDM_DBG(dm, DBG_ADPTVTY, "EDCCA enable state = %d\n", state);
+}
+
+void phydm_search_pwdb_lower_bound(void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct phydm_adaptivity_struct *adapt = &dm->adaptivity;
+	u32 value32 = 0, reg_value32 = 0;
+	u8 cnt = 0, try_count = 0;
+	u8 tx_edcca1 = 0;
+	boolean is_adjust = true;
+	s8 th_l2h_dmc, th_h2l_dmc, igi_target = 0x32;
+	s8 diff = 0;
+	s8 IGI = adapt->igi_base + 30 + dm->th_l2h_ini - dm->th_edcca_hl_diff;
+
+	if (dm->support_ic_type & (ODM_RTL8723B | ODM_RTL8188E | ODM_RTL8192E |
+	    ODM_RTL8812 | ODM_RTL8821 | ODM_RTL8881A))
+		halrf_rf_lna_setting(dm, HALRF_LNA_DISABLE);
+
+	diff = igi_target - IGI;
+	th_l2h_dmc = dm->th_l2h_ini + diff;
+	if (th_l2h_dmc > 10)
+		th_l2h_dmc = 10;
+
+	th_h2l_dmc = th_l2h_dmc - dm->th_edcca_hl_diff;
+	phydm_set_edcca_threshold(dm, th_h2l_dmc, th_l2h_dmc);
+	ODM_delay_ms(30);
+
+	while (is_adjust) {
+		/*@check CCA status*/
+		/*set debug port to 0x0*/
+		if (phydm_set_bb_dbg_port(dm, DBGPORT_PRI_1, 0x0)) {
+			reg_value32 = phydm_get_bb_dbg_port_val(dm);
+
+			while (reg_value32 & BIT(3) && try_count < 3) {
+				ODM_delay_ms(3);
+				try_count = try_count + 1;
+				reg_value32 = phydm_get_bb_dbg_port_val(dm);
+			}
+			phydm_release_bb_dbg_port(dm);
+			try_count = 0;
+		}
+
+		/*@count EDCCA signal = 1 times*/
+		for (cnt = 0; cnt < 20; cnt++) {
+			if (phydm_set_bb_dbg_port(dm, DBGPORT_PRI_1,
+						  adapt->adaptivity_dbg_port)) {
+				value32 = phydm_get_bb_dbg_port_val(dm);
+				phydm_release_bb_dbg_port(dm);
+			}
+
+			if (value32 & BIT(30) && dm->support_ic_type &
+						 (ODM_RTL8723B | ODM_RTL8188E))
+				tx_edcca1 = tx_edcca1 + 1;
+			else if (value32 & BIT(29))
+				tx_edcca1 = tx_edcca1 + 1;
+		}
+
+		if (tx_edcca1 > 1) {
+			IGI = IGI - 1;
+			th_l2h_dmc = th_l2h_dmc + 1;
+			if (th_l2h_dmc > 10)
+				th_l2h_dmc = 10;
+
+			th_h2l_dmc = th_l2h_dmc - dm->th_edcca_hl_diff;
+			phydm_set_edcca_threshold(dm, th_h2l_dmc, th_l2h_dmc);
+			tx_edcca1 = 0;
+			if (th_l2h_dmc == 10)
+				is_adjust = false;
+
+		} else {
+			is_adjust = false;
+		}
+	}
+
+	adapt->adapt_igi_up = IGI - ADAPT_DC_BACKOFF;
+	adapt->h2l_lb = th_h2l_dmc + ADAPT_DC_BACKOFF;
+	adapt->l2h_lb = th_l2h_dmc + ADAPT_DC_BACKOFF;
+
+	if (dm->support_ic_type & (ODM_RTL8723B | ODM_RTL8188E | ODM_RTL8192E |
+	    ODM_RTL8812 | ODM_RTL8821 | ODM_RTL8881A))
+		halrf_rf_lna_setting(dm, HALRF_LNA_ENABLE);
+
+	phydm_set_edcca_threshold(dm, 0x7f, 0x7f); /*resume to no link state*/
+}
+
+boolean
+phydm_re_search_condition(void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct phydm_adaptivity_struct *adaptivity = &dm->adaptivity;
+	u8 adaptivity_igi_upper = adaptivity->adapt_igi_up + ADAPT_DC_BACKOFF;
+	/*s8		TH_L2H_dmc, IGI_target = 0x32;*/
+	/*s8		diff;*/
+
+	/*TH_L2H_dmc = 10;*/
+
+	/*@diff = TH_L2H_dmc - dm->TH_L2H_ini;*/
+	/*@lowest_IGI_upper = IGI_target - diff;*/
+	/*@if ((adaptivity_igi_upper - lowest_IGI_upper) <= 5)*/
+
+	if (adaptivity_igi_upper <= 0x26)
+		return true;
+	else
+		return false;
+}
+
+void phydm_set_l2h_th_ini(void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+
+	if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
+		if (dm->support_ic_type &
+		    (ODM_RTL8821C | ODM_RTL8822B | ODM_RTL8814A))
+			dm->th_l2h_ini = 0xf2;
+		else
+			dm->th_l2h_ini = 0xef;
+	} else {
+		dm->th_l2h_ini = 0xf5;
+	}
+}
+
+void phydm_set_forgetting_factor(void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+
+	if (dm->support_ic_type & (ODM_RTL8821C | ODM_RTL8822B | ODM_RTL8814A))
+		odm_set_bb_reg(dm, R_0x8a0, BIT(1) | BIT(0), 0);
+	else if (dm->support_ic_type & ODM_IC_JGR3_SERIES)
+		odm_set_bb_reg(dm, R_0x83c, BIT(31) | BIT(30) | BIT(29), 0x7);
+}
+
+void phydm_set_pwdb_mode(void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+
+	if (dm->support_ability & ODM_BB_ADAPTIVITY) {
+		if (dm->support_ic_type & ODM_RTL8822B)
+			odm_set_bb_reg(dm, R_0x8dc, BIT(5), 0x1);
+		else if (dm->support_ic_type & (ODM_RTL8197F | ODM_RTL8192F))
+			odm_set_bb_reg(dm, R_0xce8, BIT(13), 0x1);
+		else if (dm->support_ic_type & ODM_IC_JGR3_SERIES)
+			odm_set_bb_reg(dm, R_0x844, BIT(30) | BIT(29), 0x0);
+	} else {
+		if (dm->support_ic_type & ODM_RTL8822B)
+			odm_set_bb_reg(dm, R_0x8dc, BIT(5), 0x0);
+		else if (dm->support_ic_type & (ODM_RTL8197F | ODM_RTL8192F))
+			odm_set_bb_reg(dm, R_0xce8, BIT(13), 0x0);
+		else if (dm->support_ic_type & ODM_IC_JGR3_SERIES)
+			odm_set_bb_reg(dm, R_0x844, BIT(30) | BIT(29), 0x2);
+	}
+}
+
+void phydm_adaptivity_debug(void *dm_void, char input[][16], u32 *_used,
+			    char *output, u32 *_out_len)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct phydm_adaptivity_struct *adaptivity = &dm->adaptivity;
+	u32 used = *_used;
+	u32 out_len = *_out_len;
+	u32 dm_value[10] = {0};
+	u8 i = 0, input_idx = 0;
+	u32 reg_value32 = 0;
+	s8 h2l_diff = 0;
+
+	for (i = 0; i < 5; i++) {
+		if (input[i + 1]) {
+			PHYDM_SSCANF(input[i + 1], DCMD_HEX, &dm_value[i]);
+			input_idx++;
+		}
+	}
+
+	if (input_idx == 0)
+		return;
+
+	if (dm_value[0] == PHYDM_ADAPT_DEBUG) {
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "Adaptivity Debug Mode ===>\n");
+		adaptivity->debug_mode = true;
+		dm->th_l2h_ini = (s8)dm_value[1];
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "th_l2h_ini = %d\n", dm->th_l2h_ini);
+	} else if (dm_value[0] == PHYDM_ADAPT_RESUME) {
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "===> Adaptivity Resume\n");
+		adaptivity->debug_mode = false;
+		dm->th_l2h_ini = adaptivity->th_l2h_ini_backup;
+	} else if (dm_value[0] == PHYDM_EDCCA_TH_PAUSE) {
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "EDCCA Threshold Pause\n");
+		adaptivity->edcca_en = false;
+	} else if (dm_value[0] == PHYDM_EDCCA_RESUME) {
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "EDCCA Resume\n");
+		adaptivity->edcca_en = true;
+	} else if (dm_value[0] == PHYDM_ADAPT_MSG) {
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "debug_mode = %s, th_l2h_ini = %d\n",
+			 (adaptivity->debug_mode ? "TRUE" : "FALSE"),
+			 dm->th_l2h_ini);
+		if (dm->support_ic_type & ODM_IC_JGR3_SERIES) {
+			reg_value32 = odm_get_bb_reg(dm, R_0x84c, MASKDWORD);
+			h2l_diff = (s8)((0x00ff0000 & reg_value32) >> 16) -
+				   (s8)((0xff000000 & reg_value32) >> 24);
+		} else if (dm->support_ic_type & ODM_IC_11N_SERIES) {
+			reg_value32 = odm_get_bb_reg(dm, R_0xc4c, MASKDWORD);
+			h2l_diff = (s8)(0x000000ff & reg_value32) -
+				   (s8)((0x00ff0000 & reg_value32) >> 16);
+		} else if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
+			reg_value32 = odm_get_bb_reg(dm, R_0x8a4, MASKDWORD);
+			h2l_diff = (s8)(0x000000ff & reg_value32) -
+				   (s8)((0x0000ff00 & reg_value32) >> 8);
+		}
+
+		if (h2l_diff == 7)
+			PDM_SNPF(out_len, used, output + used, out_len - used,
+				 "adaptivity enable\n");
+		else
+			PDM_SNPF(out_len, used, output + used, out_len - used,
+				 "adaptivity disable\n");
+	}
+	*_used = used;
+	*_out_len = out_len;
+}
+
+void phydm_set_edcca_val(void *dm_void, u32 *val_buf, u8 val_len)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+
+	if (val_len != 2) {
+		PHYDM_DBG(dm, ODM_COMP_API,
+			  "[Error][adaptivity]Need val_len = 2\n");
+		return;
+	}
+	phydm_set_edcca_threshold(dm, (s8)val_buf[1], (s8)val_buf[0]);
+}
+
+#endif
+void phydm_set_edcca_threshold_api(void *dm_void, u8 IGI)
+{
+#ifdef PHYDM_SUPPORT_ADAPTIVITY
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct phydm_adaptivity_struct *adaptivity = &dm->adaptivity;
+	s8 th_l2h_dmc = 0, th_h2l_dmc = 0;
+	s8 diff = 0, igi_target = 0x32;
+
+	if (dm->support_ability & ODM_BB_ADAPTIVITY) {
+		if (!(dm->support_ic_type & ODM_IC_PWDB_EDCCA)) {
+			if (adaptivity->adajust_igi_level > IGI)
+				diff = adaptivity->adajust_igi_level - IGI;
+
+			th_l2h_dmc = dm->th_l2h_ini - diff + igi_target;
+			th_h2l_dmc = th_l2h_dmc - dm->th_edcca_hl_diff;
+		} else {
+			diff = igi_target - (s8)IGI;
+			th_l2h_dmc = dm->th_l2h_ini + diff;
+			if (th_l2h_dmc > 10)
+				th_l2h_dmc = 10;
+
+			th_h2l_dmc = th_l2h_dmc - dm->th_edcca_hl_diff;
+
+			/*replace lower bound to prevent EDCCA always equal 1*/
+			if (th_h2l_dmc < adaptivity->h2l_lb)
+				th_h2l_dmc = adaptivity->h2l_lb;
+			if (th_l2h_dmc < adaptivity->l2h_lb)
+				th_l2h_dmc = adaptivity->l2h_lb;
+		}
+
+		PHYDM_DBG(dm, DBG_ADPTVTY,
+			  "API :IGI=0x%x, th_l2h_dmc = %d, th_h2l_dmc = %d\n",
+			  IGI, th_l2h_dmc, th_h2l_dmc);
+
+		phydm_set_edcca_threshold(dm, th_h2l_dmc, th_l2h_dmc);
+	}
+#endif
+}
+
+void phydm_adaptivity_info_init(void *dm_void, enum phydm_adapinfo cmn_info,
+				u32 value)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct phydm_adaptivity_struct *adaptivity = &dm->adaptivity;
+
+	switch (cmn_info) {
+	case PHYDM_ADAPINFO_CARRIER_SENSE_ENABLE:
+		dm->carrier_sense_enable = (boolean)value;
+		break;
+	case PHYDM_ADAPINFO_TH_L2H_INI:
+		dm->th_l2h_ini = (s8)value;
+		break;
+	case PHYDM_ADAPINFO_TH_EDCCA_HL_DIFF:
+		dm->th_edcca_hl_diff = (s8)value;
+		break;
+	case PHYDM_ADAPINFO_AP_NUM_TH:
+		adaptivity->ap_num_th = (u8)value;
+		break;
+	default:
+		break;
+	}
+}
+
+void phydm_adaptivity_info_update(void *dm_void, enum phydm_adapinfo cmn_info,
+				  u32 value)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct phydm_adaptivity_struct *adapt = &dm->adaptivity;
+
+	/*This init variable may be changed in run time.*/
+	switch (cmn_info) {
+	case PHYDM_ADAPINFO_DOMAIN_CODE_2G:
+		adapt->regulation_2g = (u8)value;
+		break;
+	case PHYDM_ADAPINFO_DOMAIN_CODE_5G:
+		adapt->regulation_5g = (u8)value;
+		break;
+	default:
+		break;
+	}
+}
+
+void phydm_adaptivity_init(void *dm_void)
+{
+#ifdef PHYDM_SUPPORT_ADAPTIVITY
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct phydm_adaptivity_struct *adaptivity = &dm->adaptivity;
+
+#if (DM_ODM_SUPPORT_TYPE & (ODM_CE | ODM_WIN))
+
+	if (!dm->carrier_sense_enable) {
+		if (dm->th_l2h_ini == 0)
+			phydm_set_l2h_th_ini(dm);
+	} else {
+		dm->th_l2h_ini = 0xa;
+	}
+
+	if (dm->th_edcca_hl_diff == 0)
+		dm->th_edcca_hl_diff = 7;
+#if (DM_ODM_SUPPORT_TYPE & (ODM_CE))
+	if (dm->wifi_test || *dm->mp_mode)
+#else
+	if (dm->wifi_test & RT_WIFI_LOGO) /*@AP side use mib control*/
+#endif
+		/*@even no adaptivity, we still enable EDCCA*/
+		adaptivity->edcca_en = false;
+	else
+		adaptivity->edcca_en = true;
+
+#elif (DM_ODM_SUPPORT_TYPE & ODM_AP)
+	if (dm->carrier_sense_enable) {
+		dm->th_l2h_ini = 0xa;
+		dm->th_edcca_hl_diff = 7;
+	} else {
+		dm->th_l2h_ini = dm->TH_L2H_default; /*set by mib*/
+		dm->th_edcca_hl_diff = dm->th_edcca_hl_diff_default;
+	}
+
+	adaptivity->edcca_en = true;
+#endif
+
+	adaptivity->adapt_igi_up = 0;
+	adaptivity->is_adapt_en = false; /*@decide enable or not*/
+	adaptivity->th_l2h_ini_mode2 = 20;
+	adaptivity->th_edcca_hl_diff_mode2 = 8;
+	adaptivity->debug_mode = false;
+	adaptivity->th_l2h_ini_backup = dm->th_l2h_ini;
+	adaptivity->th_edcca_hl_diff_backup = dm->th_edcca_hl_diff;
+	adaptivity->igi_base = 0x32;
+	adaptivity->igi_target = 0x1c;
+	adaptivity->h2l_lb = 0;
+	adaptivity->l2h_lb = 0;
+	adaptivity->adajust_igi_level = 0;
+	phydm_mac_edcca_state(dm, PHYDM_DONT_IGNORE_EDCCA);
+
+	if (dm->support_ic_type & ODM_IC_JGR3_SERIES) {
+		adaptivity->adaptivity_dbg_port = 0x000;
+		odm_set_bb_reg(dm, R_0x1d6c, BIT(0), 1);
+	} else if (dm->support_ic_type & ODM_IC_11N_SERIES) {
+		adaptivity->adaptivity_dbg_port = 0x208;
+	} else {
+		adaptivity->adaptivity_dbg_port = 0x209;
+	}
+	if (dm->support_ic_type & ODM_IC_11N_SERIES &&
+	    !(dm->support_ic_type & ODM_IC_PWDB_EDCCA)) {
+		/*@interfernce need > 2^x us, and then EDCCA will be 1*/
+#if 0
+		/*odm_set_bb_reg(dm, 0x948, 0x1c00, 0x7);*/
+#endif
+		if (dm->support_ic_type & (ODM_RTL8197F | ODM_RTL8192F)) {
+			/*set to page B1*/
+			odm_set_bb_reg(dm, R_0xe28, BIT(30), 0x1);
+			/*@0:rx_dfir, 1: dcnf_out, 2 :rx_iq, 3: rx_nbi_nf_out*/
+			odm_set_bb_reg(dm, R_0xbc0, BIT(27) | BIT(26), 0x1);
+			odm_set_bb_reg(dm, R_0xe28, BIT(30), 0x0);
+		} else {
+			/*@0:rx_dfir, 1: dcnf_out, 2 :rx_iq, 3: rx_nbi_nf_out*/
+			odm_set_bb_reg(dm, R_0xe24, BIT(21) | BIT(20), 0x1);
+		}
+	} else if (dm->support_ic_type & ODM_IC_11AC_SERIES &&
+		   !(dm->support_ic_type & ODM_IC_PWDB_EDCCA)) {
+		/*@interfernce need > 2^x us, and then EDCCA will be 1*/
+#if 0
+		/*odm_set_bb_reg(dm, 0x900, 0x70000000, 0x7);*/
+#endif
+		/*@0:rx_dfir, 1: dcnf_out, 2 :rx_iq, 3: rx_nbi_nf_out*/
+		odm_set_bb_reg(dm, R_0x944, BIT(29) | BIT(28), 0x1);
+	}
+
+	if (dm->support_ic_type & ODM_IC_PWDB_EDCCA) {
+		phydm_search_pwdb_lower_bound(dm);
+		if (phydm_re_search_condition(dm))
+			phydm_search_pwdb_lower_bound(dm);
+	} else {
+		/*resume to no link state*/
+		phydm_set_edcca_threshold(dm, 0x7f, 0x7f);
+	}
+
+	/*@forgetting factor setting*/
+	phydm_set_forgetting_factor(dm);
+
+	/*pwdb mode setting with 0: mean, 1:max*/
+	phydm_set_pwdb_mode(dm);
+
+#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
+	adaptivity->igi_up_bound_lmt_val = 180;
+#else
+	adaptivity->igi_up_bound_lmt_val = 90;
+#endif
+	adaptivity->igi_up_bound_lmt_cnt = 0;
+	adaptivity->igi_lmt_en = false;
+#endif
+}
+
+void phydm_adaptivity(void *dm_void)
+{
+#ifdef PHYDM_SUPPORT_ADAPTIVITY
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
+	u8 igi = dig_t->cur_ig_value;
+	s8 th_l2h_dmc = 0, th_h2l_dmc = 0;
+	s8 diff = 0, igi_target = 0x32;
+	struct phydm_adaptivity_struct *adapt = &dm->adaptivity;
+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
+	void *adapter = dm->adapter;
+	u32 is_fw_current_in_ps_mode = false;
+	u8 disable_ap_adapt_setting;
+
+	((PADAPTER)adapter)->HalFunc.GetHwRegHandler(adapter, HW_VAR_FW_PSMODE_STATUS, (u8 *)(&is_fw_current_in_ps_mode));
+
+	/*@Disable EDCCA mode while under LPS mode, added by Roger, 2012.09.14.*/
+	if (is_fw_current_in_ps_mode)
+		return;
+#endif
+	if (dm->pause_ability & ODM_BB_ADAPTIVITY) {
+		PHYDM_DBG(dm, DBG_ADPTVTY, "Return: Pause ADPTVTY in LV=%d\n",
+			  dm->pause_lv_table.lv_adapt);
+		return;
+	}
+
+	if (!adapt->edcca_en) {
+		PHYDM_DBG(dm, DBG_ADPTVTY, "Disable EDCCA!!!\n");
+		return;
+	}
+
+	phydm_check_adaptivity(dm); /*@Check adaptivity enable*/
+	/*@Limit IGI upper bound for adaptivity*/
+	if (dm->support_ic_type & ODM_IC_PWDB_EDCCA)
+		phydm_dig_up_bound_lmt_en(dm);
+
+	if (!(dm->support_ability & ODM_BB_ADAPTIVITY) &&
+	    !adapt->debug_mode) {
+		PHYDM_DBG(dm, DBG_ADPTVTY,
+			  "adaptivity disable, enable EDCCA mode!!!\n");
+		dm->th_l2h_ini = adapt->th_l2h_ini_mode2;
+		dm->th_edcca_hl_diff = adapt->th_edcca_hl_diff_mode2;
+	}
+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
+	else if (!adapt->debug_mode) {
+		if (!adapt->is_adapt_en) {
+			dm->th_l2h_ini = adapt->th_l2h_ini_mode2;
+			dm->th_edcca_hl_diff = adapt->th_edcca_hl_diff_mode2;
+		} else {
+			dm->th_l2h_ini = adapt->th_l2h_ini_backup;
+			dm->th_edcca_hl_diff = adapt->th_edcca_hl_diff_backup;
+		}
+	}
+#endif
+
+	PHYDM_DBG(dm, DBG_ADPTVTY, "odm_Adaptivity() =====>\n");
+	PHYDM_DBG(dm, DBG_ADPTVTY,
+		  "igi_base=0x%x, th_l2h_ini = %d, th_edcca_hl_diff = %d\n",
+		  adapt->igi_base, dm->th_l2h_ini, dm->th_edcca_hl_diff);
+
+	if (dm->support_ic_type & ODM_RTL8812) {
+		/*@fix AC series when enable EDCCA hang issue*/
+		odm_set_bb_reg(dm, R_0x800, BIT(10), 1); /*@ADC_mask disable*/
+		odm_set_bb_reg(dm, R_0x800, BIT(10), 0); /*@ADC_mask enable*/
+	}
+
+	igi_target = adapt->igi_base;
+	adapt->igi_target = (u8)igi_target;
+	/*we need to consider PwdB upper bound for 8814 later IC*/
+	adapt->adajust_igi_level = (u8)(dm->th_l2h_ini + igi_target -
+				   PWDB_UPPER_BOUND + DFIR_LOSS);
+
+	PHYDM_DBG(dm, DBG_ADPTVTY,
+		  "adajust_igi_level= 0x%x, is_adapt_en = %d\n",
+		  adapt->adajust_igi_level, adapt->is_adapt_en);
+
+	if (!(dm->support_ic_type & ODM_IC_PWDB_EDCCA)) {
+		if (adapt->adajust_igi_level > igi && adapt->is_adapt_en)
+			diff = adapt->adajust_igi_level - igi;
+		else if (!adapt->is_adapt_en)
+			diff = 0x3e - igi;
+
+		th_l2h_dmc = dm->th_l2h_ini - diff + igi_target;
+		th_h2l_dmc = th_l2h_dmc - dm->th_edcca_hl_diff;
+	} else {
+		diff = igi_target - (s8)igi;
+		th_l2h_dmc = dm->th_l2h_ini + diff;
+		if (th_l2h_dmc > 10 && adapt->is_adapt_en)
+			th_l2h_dmc = 10;
+
+		th_h2l_dmc = th_l2h_dmc - dm->th_edcca_hl_diff;
+
+		/*replace lower bound to prevent EDCCA always equal 1*/
+		if (th_h2l_dmc < adapt->h2l_lb)
+			th_h2l_dmc = adapt->h2l_lb;
+		if (th_l2h_dmc < adapt->l2h_lb)
+			th_l2h_dmc = adapt->l2h_lb;
+	}
+
+	adapt->th_l2h = th_l2h_dmc;
+	adapt->th_h2l = th_h2l_dmc;
+	PHYDM_DBG(dm, DBG_ADPTVTY,
+		  "IGI=0x%x, th_l2h_dmc = %d, th_h2l_dmc = %d\n", igi,
+		  th_l2h_dmc, th_h2l_dmc);
+	PHYDM_DBG(dm, DBG_ADPTVTY,
+		  "adapt_igi_up=0x%x, h2l_lb = 0x%x, l2h_lb = 0x%x\n",
+		  adapt->adapt_igi_up, adapt->h2l_lb,
+		  adapt->l2h_lb);
+	PHYDM_DBG(dm, DBG_ADPTVTY, "debug_mode = %d\n", adapt->debug_mode);
+	phydm_set_edcca_threshold(dm, th_h2l_dmc, th_l2h_dmc);
+
+	if (adapt->is_adapt_en)
+		odm_set_mac_reg(dm, REG_RD_CTRL, BIT(11), 1);
+
+	return;
+#endif
+}
+
+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
+/*This API is for solving USB can't Tx due to USB3.0 interference in 2.4G*/
+void phydm_pause_edcca(void *dm_void, boolean is_pasue_edcca)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct phydm_adaptivity_struct *adapt = &dm->adaptivity;
+
+	if (is_pasue_edcca) {
+		dm->pause_ability |= ODM_BB_ADAPTIVITY;
+		PHYDM_DBG(dm, DBG_ADPTVTY, "pauseEDCCA\n");
+
+		/*@Disable EDCCA*/
+		if (!odm_is_work_item_scheduled(&adapt->phydm_pause_edcca_work_item))
+			odm_schedule_work_item(&adapt->phydm_pause_edcca_work_item);
+	} else {
+		dm->pause_ability &= ~ODM_BB_ADAPTIVITY;
+		PHYDM_DBG(dm, DBG_ADPTVTY,
+			  "resumeEDCCA : L2Hbak = 0x%x, H2Lbak = 0x%x\n",
+			  adapt->th_l2h, adapt->th_h2l);
+		/*Resume EDCCA*/
+		if (!odm_is_work_item_scheduled(&adapt->phydm_resume_edcca_work_item))
+			odm_schedule_work_item(&adapt->phydm_resume_edcca_work_item);
+	}
+}
+
+void phydm_pause_edcca_work_item_callback(void *adapter)
+{
+	PHAL_DATA_TYPE hal_data = GET_HAL_DATA(((PADAPTER)adapter));
+	struct dm_struct *dm = &hal_data->DM_OutSrc;
+
+	if (dm->support_ic_type & ODM_IC_11N_SERIES) {
+		odm_set_bb_reg(dm, R_0xc4c, MASKBYTE0, 0x7f);
+		odm_set_bb_reg(dm, R_0xc4c, MASKBYTE2, 0x7f);
+	} else if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
+		odm_set_bb_reg(dm, R_0x8a4, MASKLWORD, 0x7f7f);
+	}
+
+}
+
+void phydm_resume_edcca_work_item_callback(void *adapter)
+{
+	PHAL_DATA_TYPE hal_data = GET_HAL_DATA(((PADAPTER)adapter));
+	struct dm_struct *dm = &hal_data->DM_OutSrc;
+
+	struct phydm_adaptivity_struct *adapt = &dm->adaptivity;
+
+	if (dm->support_ic_type & ODM_IC_11N_SERIES) {
+		odm_set_bb_reg(dm, R_0xc4c, MASKBYTE0, (u8)adapt->th_l2h);
+		odm_set_bb_reg(dm, R_0xc4c, MASKBYTE2, (u8)adapt->th_h2l);
+	} else if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
+		odm_set_bb_reg(dm, R_0x8a4, MASKBYTE0, (u8)adapt->th_l2h);
+		odm_set_bb_reg(dm, R_0x8a4, MASKBYTE1, (u8)adapt->th_h2l);
+	}
+
+}
+#endif
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/phydm_adaptivity.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/phydm_adaptivity.h
--- linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/phydm_adaptivity.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/phydm_adaptivity.h	2020-04-10 16:35:06.822660348 +0300
@@ -0,0 +1,134 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017  Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * The full GNU General Public License is included in this distribution in the
+ * file called LICENSE.
+ *
+ * Contact Information:
+ * wlanfae <wlanfae@realtek.com>
+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
+ * Hsinchu 300, Taiwan.
+ *
+ * Larry Finger <Larry.Finger@lwfinger.net>
+ *
+ *****************************************************************************/
+
+#ifndef __PHYDMADAPTIVITY_H__
+#define __PHYDMADAPTIVITY_H__
+
+#define ADAPTIVITY_VERSION "9.5.20" /*@20180306 changed by Kevin,
+				     *remove phydm lna set and use halrf part
+				     */
+
+#define PWDB_UPPER_BOUND 7
+#define DFIR_LOSS 7
+#define ODM_IC_PWDB_EDCCA (ODM_RTL8188E | ODM_RTL8723B | ODM_RTL8192E |\
+			   ODM_RTL8881A | ODM_RTL8821 | ODM_RTL8812)
+
+#if (DM_ODM_SUPPORT_TYPE & (ODM_CE | ODM_AP))
+	#define ADAPT_DC_BACKOFF 2
+#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)
+	#define ADAPT_DC_BACKOFF 4
+#elif (DM_ODM_SUPPORT_TYPE & ODM_IOT)
+	#define ADAPT_DC_BACKOFF 0
+#endif
+#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN))
+enum phydm_regulation_type {
+	REGULATION_FCC		= 0,
+	REGULATION_MKK		= 1,
+	REGULATION_ETSI		= 2,
+	REGULATION_WW		= 3,
+	MAX_REGULATION_NUM	= 4
+};
+#endif
+
+enum phydm_adapinfo {
+	PHYDM_ADAPINFO_CARRIER_SENSE_ENABLE = 0,
+	PHYDM_ADAPINFO_TH_L2H_INI,
+	PHYDM_ADAPINFO_TH_EDCCA_HL_DIFF,
+	PHYDM_ADAPINFO_AP_NUM_TH,
+	PHYDM_ADAPINFO_DOMAIN_CODE_2G,
+	PHYDM_ADAPINFO_DOMAIN_CODE_5G
+};
+
+enum phydm_mac_edcca_type {
+	PHYDM_IGNORE_EDCCA		= 0,
+	PHYDM_DONT_IGNORE_EDCCA		= 1
+};
+
+enum phydm_adaptivity_mode {
+	PHYDM_ADAPT_MSG			= 0,
+	PHYDM_ADAPT_DEBUG		= 1,
+	PHYDM_ADAPT_RESUME		= 2,
+	PHYDM_EDCCA_TH_PAUSE		= 3,
+	PHYDM_EDCCA_RESUME		= 4
+};
+
+struct phydm_adaptivity_struct {
+	s8			th_l2h_ini_backup;
+	s8			th_edcca_hl_diff_backup;
+	s8			igi_base;
+	u8			igi_target;
+	s8			h2l_lb;
+	s8			l2h_lb;
+	u8			ap_num_th;
+	u8			adajust_igi_level;
+#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
+	RT_WORK_ITEM		phydm_pause_edcca_work_item;
+	RT_WORK_ITEM		phydm_resume_edcca_work_item;
+#endif
+	u32			adaptivity_dbg_port; /*N:0x208, AC:0x209*/
+	u8			debug_mode;
+	u16			igi_up_bound_lmt_cnt;	/*@When igi_up_bound_lmt_cnt !=0, limit IGI upper bound to "adapt_igi_up"*/
+	u16			igi_up_bound_lmt_val;	/*@max value of igi_up_bound_lmt_cnt*/
+	boolean			igi_lmt_en;
+	u8			adapt_igi_up;
+	s8			rvrt_val[2];
+	s8			th_l2h;
+	s8			th_h2l;
+	u8			regulation_2g;
+	u8			regulation_5g;
+	boolean			is_adapt_en;
+	boolean			edcca_en;
+	s8			th_l2h_ini_mode2;
+	s8			th_edcca_hl_diff_mode2;
+};
+
+#ifdef PHYDM_SUPPORT_ADAPTIVITY
+void phydm_adaptivity_debug(void *dm_void, char input[][16], u32 *_used,
+			    char *output, u32 *_out_len);
+
+void phydm_set_edcca_val(void *dm_void, u32 *val_buf, u8 val_len);
+#endif
+
+void phydm_set_edcca_threshold_api(void *dm_void, u8 IGI);
+
+void phydm_adaptivity_info_init(void *dm_void, enum phydm_adapinfo cmn_info,
+				u32 value);
+
+void phydm_adaptivity_info_update(void *dm_void, enum phydm_adapinfo cmn_info,
+				  u32 value);
+
+void phydm_adaptivity_init(void *dm_void);
+
+void phydm_adaptivity(void *dm_void);
+
+void phydm_pause_edcca(void *dm_void, boolean is_pasue_edcca);
+
+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
+void phydm_pause_edcca_work_item_callback(void *adapter);
+
+void phydm_resume_edcca_work_item_callback(void *adapter);
+#endif
+
+#endif
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/phydm_adc_sampling.c linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/phydm_adc_sampling.c
--- linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/phydm_adc_sampling.c	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/phydm_adc_sampling.c	2020-04-10 16:35:06.822660348 +0300
@@ -0,0 +1,1076 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017  Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * The full GNU General Public License is included in this distribution in the
+ * file called LICENSE.
+ *
+ * Contact Information:
+ * wlanfae <wlanfae@realtek.com>
+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
+ * Hsinchu 300, Taiwan.
+ *
+ * Larry Finger <Larry.Finger@lwfinger.net>
+ *
+ *****************************************************************************/
+
+#include "mp_precomp.h"
+#include "phydm_precomp.h"
+
+#if (PHYDM_LA_MODE_SUPPORT)
+
+#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
+#if (RTL8197F_SUPPORT || RTL8822B_SUPPORT || RTL8192F_SUPPORT)
+#include "rtl8197f/Hal8197FPhyReg.h"
+#include "WlanHAL/HalMac88XX/halmac_reg2.h"
+#else
+#include "WlanHAL/HalHeader/HalComReg.h"
+#endif
+#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)
+#if WPP_SOFTWARE_TRACE
+#include "phydm_adc_sampling.tmh"
+#endif
+#endif
+
+#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
+boolean
+phydm_la_buffer_allocate(void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct rt_adcsmp *smp = &dm->adcsmp;
+	#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
+	void *adapter = dm->adapter;
+	#endif
+	struct rt_adcsmp_string *buf = &smp->adc_smp_buf;
+	boolean ret = true;
+
+	pr_debug("[LA mode BufferAllocate]\n");
+
+	if (buf->length == 0) {
+	#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
+		if (PlatformAllocateMemoryWithZero(adapter, (void **)&
+						   buf->octet,
+						   buf->buffer_size) !=
+						   RT_STATUS_SUCCESS)
+			ret = false;
+	#else
+		odm_allocate_memory(dm, (void **)&buf->octet, buf->buffer_size);
+
+		if (!buf->octet)
+			ret = false;
+	#endif
+
+		if (ret)
+			buf->length = buf->buffer_size;
+	}
+
+	return ret;
+}
+#endif
+
+void phydm_la_get_tx_pkt_buf(void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct rt_adcsmp *smp = &dm->adcsmp;
+	struct rt_adcsmp_string *buf = &smp->adc_smp_buf;
+	u32 i = 0, value32 = 0, data_l = 0, data_h = 0;
+	u32 addr = 0, finish_addr = 0;
+	boolean is_round_up = false;
+	static u32 page = 0xFF;
+	u32 smp_cnt = 0, smp_number = 10, addr_8byte = 0;
+	#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
+	#if (RTL8197F_SUPPORT || RTL8198F_SUPPORT)
+	u8 backup_dma = 0;
+	#endif
+	#endif
+
+	odm_memory_set(dm, buf->octet, 0, buf->length);
+	pr_debug("GetTxPktBuf\n");
+
+	if (dm->support_ic_type & ODM_RTL8192F) {
+		value32 = odm_read_4byte(dm, 0x7F0);
+		is_round_up = (boolean)((value32 & BIT(31)) >> 31);
+		/*Reg7F0[30:15]: finish addr (unit: 8byte)*/
+		finish_addr = (value32 & 0x7FFF8000) >> 15;
+	} else {
+		odm_write_1byte(dm, 0x0106, 0x69);
+		value32 = odm_read_4byte(dm, 0x7C0);
+		is_round_up = (boolean)((value32 & BIT(31)) >> 31);
+		/*Reg7C0[30:16]: finish addr (unit: 8byte)*/
+		if (dm->support_ic_type & (ODM_RTL8822B | ODM_RTL8822C |
+		    ODM_RTL8821C | ODM_RTL8814A | ODM_RTL8814B))
+			finish_addr = (value32 & 0x7FFF0000) >> 16;
+		/*Reg7C0[30:15]: finish addr (unit: 8byte)*/
+		else if (dm->support_ic_type & (ODM_RTL8198F | ODM_RTL8197F))
+			finish_addr = (value32 & 0x7FFF8000) >> 15;
+	}
+
+	#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
+	#if (RTL8197F_SUPPORT || RTL8198F_SUPPORT)
+	if (dm->support_ic_type & (ODM_RTL8197F | ODM_RTL8198F)) {
+		pr_debug("98F GetTxPktBuf from iMEM\n");
+		odm_set_bb_reg(dm, R_0x7c0, BIT(0), 0x0);
+
+		/*Stop DMA*/
+		backup_dma = odm_get_mac_reg(dm, R_0x300, MASKLWORD);
+		odm_set_mac_reg(dm, R_0x300, 0x7fff, 0x7fff);
+
+		/*@move LA mode content from IMEM to TxPktBuffer
+			Source : OCPBASE_IMEM 0x00000000
+			Destination : OCPBASE_TXBUF 0x18780000
+			Length : 64K*/
+		GET_HAL_INTERFACE(dm->priv)->init_ddma_handler(dm->priv,
+							       OCPBASE_IMEM,
+							       OCPBASE_TXBUF,
+							       0x10000);
+	}
+	#endif
+	#endif
+
+	pr_debug("start_addr = ((0x%x)), end_addr = ((0x%x)), buffer_size = ((%d))\n",
+		 buf->start_pos, buf->end_pos, buf->buffer_size);
+	if (is_round_up) {
+		pr_debug("buf_start(%d)|----2---->|finish_addr(%d)|----1---->|buf_end(%d)\n",
+			 buf->start_pos, finish_addr << 3, buf->end_pos);
+		addr = (finish_addr + 1) << 3;
+		pr_debug("is_round_up = ((%d)), finish_addr=((0x%x)), 0x7c0/0x7F0=((0x%x))\n",
+			 is_round_up, finish_addr, value32);
+		/*@Byte to 8Byte (64bit)*/
+		smp_number = (buf->buffer_size) >> 3;
+	} else {
+		pr_debug("buf_start(%d)|------->|finish_addr(%d)             |buf_end(%d)\n",
+			 buf->start_pos, finish_addr << 3, buf->end_pos);
+		addr = buf->start_pos;
+		addr_8byte = addr >> 3;
+
+		if (addr_8byte > finish_addr)
+			smp_number = addr_8byte - finish_addr;
+		else
+			smp_number = finish_addr - addr_8byte;
+
+		pr_debug("is_round_up = ((%d)), finish_addr=((0x%x * 8Byte)), Start_Addr = ((0x%x * 8Byte)), smp_number = ((%d))\n",
+			 is_round_up, finish_addr, addr_8byte, smp_number);
+	}
+	#if 0
+	dbg_print("is_round_up = %d, finish_addr=0x%x, value32=0x%x\n",
+		  is_round_up, finish_addr, value32);
+	dbg_print(
+		  "end_addr = %x, buf->start_pos = 0x%x, buf->buffer_size = 0x%x\n",
+		  end_addr, buf->start_pos, buf->buffer_size);
+	#endif
+
+	#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
+	#if (RTL8197F_SUPPORT || RTL8198F_SUPPORT)
+	if (dm->support_ic_type & (ODM_RTL8197F | ODM_RTL8198F)) {
+		for (addr = 0x0; addr < buf->end_pos; addr += 8) {/*@64K byte*/
+			if ((addr & 0xfff) == 0)
+				odm_set_bb_reg(dm, R_0x0140, MASKLWORD, 0x780 +
+					       (addr >> 12));
+			data_l = odm_get_bb_reg(dm, 0x8000 + (addr & 0xfff),
+						MASKDWORD);
+			data_h = odm_get_bb_reg(dm, 0x8000 + (addr & 0xfff) +
+						4, MASKDWORD);
+
+			pr_debug("%08x%08x\n", data_h, data_l);
+		}
+	} else
+	#endif
+	#endif
+	{
+		for (i = 0; smp_cnt < smp_number; smp_cnt++, i += 2) {
+			if (dm->support_ic_type & ODM_RTL8192F) {
+			#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
+				indirect_access_sdram_8192f(dm->adapter,
+							    TX_PACKET_BUFFER,
+							    TRUE,
+							    (u16)addr >> 3, 0,
+							    &data_h, &data_l);
+			#else
+			odm_write_1byte(dm, R_0x0106, 0x69);
+			odm_set_bb_reg(dm, R_0x0140, MASKDWORD, addr >> 3);
+			data_l = odm_get_bb_reg(dm, R_0x0144, MASKDWORD);
+			data_h = odm_get_bb_reg(dm, R_0x0148, MASKDWORD);
+			odm_write_1byte(dm, R_0x0106, 0x0);
+			#endif
+
+			} else {
+				if (page != (addr >> 12)) {
+					/* Reg140=0x780+(addr>>12),
+					 * addr=0x30~0x3F, total 16 pages
+					 */
+					page = addr >> 12;
+				}
+				odm_set_bb_reg(dm, R_0x0140, MASKLWORD, 0x780 +
+					       page);
+
+				/*pDataL = 0x8000+(addr&0xfff);*/
+				data_l = odm_get_bb_reg(dm, 0x8000 + (addr &
+							0xfff),	MASKDWORD);
+				data_h = odm_get_bb_reg(dm, 0x8000 + (addr &
+							0xfff) + 4, MASKDWORD);
+			}
+			#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
+			buf->octet[i] = data_h;
+			buf->octet[i + 1] = data_l;
+			#endif
+			#if DBG /*WIN driver check build*/
+			pr_debug("%08x%08x\n", data_h, data_l);
+			#else	/*WIN driver free build*/
+			#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
+			RT_TRACE_EX(COMP_LA_MODE, DBG_LOUD,
+				    ("%08x%08x\n", buf->octet[i],
+				    buf->octet[i + 1]));
+			#endif
+			#endif
+			if ((addr + 8) > buf->end_pos)
+				addr = buf->start_pos;
+			else
+				addr = addr + 8;
+		}
+		pr_debug("smp_cnt = ((%d))\n", smp_cnt);
+
+		#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
+		RT_TRACE_EX(COMP_LA_MODE, DBG_LOUD,
+			    ("smp_cnt = ((%d))\n", smp_cnt));
+		#endif
+	}
+	#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
+	#if (RTL8197F_SUPPORT)
+	if (dm->support_ic_type & ODM_RTL8197F)
+		odm_set_mac_reg(dm, R_0x300, 0x7fff, backup_dma);/*Resume DMA*/
+	#endif
+	#endif
+}
+
+void phydm_la_mode_set_mac_iq_dump(void *dm_void, boolean en_fake_trig)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct rt_adcsmp *smp = &dm->adcsmp;
+	u32 reg_value = 0;
+	u32 reg1 = 0, reg2 = 0, reg3 = 0;
+
+	if (dm->support_ic_type & ODM_RTL8192F) {
+		reg1 = 0x7f0;
+		reg2 = 0x7f4;
+		reg3 = 0x7f8;
+	} else {
+		reg1 = 0x7c0;
+		reg2 = 0x7c4;
+		reg3 = 0x7c8;
+	}
+
+	odm_write_1byte(dm, reg1, 0); /*@clear all reg1*/
+	/*@Enable LA mode HW block*/
+	odm_set_mac_reg(dm, reg1, BIT(0), 1);
+
+	if (smp->la_trig_mode == PHYDM_MAC_TRIG) {
+		smp->is_bb_trigger = 0;
+		/*polling bit for MAC mode*/
+		odm_set_mac_reg(dm, reg1, BIT(2), 1);
+		/*trigger mode for MAC*/
+		odm_set_mac_reg(dm, reg1, BIT(4) | BIT(3),
+				smp->la_trigger_edge);
+		pr_debug("[MAC_trig] ref_mask = ((0x%x)), ref_value = ((0x%x)), dbg_port = ((0x%x))\n",
+			 smp->la_mac_mask_or_hdr_sel, smp->la_trig_sig_sel,
+			 smp->la_dbg_port);
+		/*@[Set MAC Debug Port]*/
+		odm_set_mac_reg(dm, R_0xf4, BIT(16), 1);
+		odm_set_mac_reg(dm, R_0x38, 0xff0000, smp->la_dbg_port);
+		odm_set_mac_reg(dm, reg2, MASKDWORD,
+				smp->la_mac_mask_or_hdr_sel);
+		odm_set_mac_reg(dm, reg3, MASKDWORD, smp->la_trig_sig_sel);
+
+	} else {
+		smp->is_bb_trigger = 1;
+		/*polling bit for BB ADC mode*/
+		odm_set_mac_reg(dm, reg1, BIT(1), 1);
+
+		if (smp->la_trig_mode == PHYDM_ADC_MAC_TRIG) {
+			/*polling bit for MAC trigger event*/
+			if (!en_fake_trig)
+				odm_set_mac_reg(dm, R_0x7c0, BIT(3), 1);
+
+			odm_set_mac_reg(dm, reg1, BIT(7) | BIT(6),
+					smp->la_trig_sig_sel);
+			if (smp->la_trig_sig_sel == ADCSMP_TRIG_REG)
+				/* @manual trigger reg1[5] = 0->1*/
+				odm_set_mac_reg(dm, reg1, BIT(5), 1);
+		}
+	}
+
+	reg_value = odm_get_bb_reg(dm, reg1, 0xff);
+	pr_debug("4. [Set MAC IQ dump] 0x%x[7:0] = ((0x%x))\n", reg1,
+		 reg_value);
+
+	#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
+	RT_TRACE_EX(COMP_LA_MODE, DBG_LOUD,
+		    ("4. [Set MAC IQ dump] 0x%x[7:0] = ((0x%x))\n", reg1,
+		    reg_value));
+	#endif
+}
+
+void phydm_adc_smp_start(void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct rt_adcsmp *smp = &dm->adcsmp;
+	u8 tmp_u1b = 0;
+	u8 while_cnt = 0;
+	u8 target_polling_bit = 0;
+	boolean polling_ok = false;
+	boolean en_fake_trig = false;
+
+	if (smp->la_dma_type >= 0 && smp->la_dma_type <= 5)
+		en_fake_trig = true;
+
+	if (en_fake_trig) {
+		smp->is_fake_trig = true;
+		phydm_la_mode_bb_setting(dm, en_fake_trig);
+	} else {
+		smp->is_fake_trig = false;
+		phydm_la_mode_bb_setting(dm, en_fake_trig);
+	}
+
+	phydm_la_mode_set_trigger_time(dm, smp->la_trigger_time);
+
+	if (dm->support_ic_type & (ODM_RTL8197F | ODM_RTL8192F))
+		odm_set_bb_reg(dm, R_0xd00, BIT(26), 0x1);
+	else if (dm->support_ic_type & (ODM_RTL8198F | ODM_RTL8822C))
+		odm_set_bb_reg(dm, R_0x1eb4, BIT(23), 0x1);
+	else	/*@for 8814A and 8822B?*/
+		odm_write_1byte(dm, 0x8b4, 0x80);
+#if 0
+		/* odm_set_bb_reg(dm, R_0x8b4, BIT(7), 1); */
+#endif
+
+	phydm_la_mode_set_mac_iq_dump(dm, en_fake_trig);
+
+	#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
+	watchdog_stop(dm->priv);
+	#endif
+
+	if (en_fake_trig) {
+		ODM_delay_ms(100);
+		if (smp->la_trig_mode == PHYDM_ADC_BB_TRIG) {
+			smp->is_fake_trig = false;
+			phydm_la_mode_bb_setting(dm, en_fake_trig);
+		}
+		if (smp->la_trig_mode == PHYDM_ADC_MAC_TRIG) {
+			if (dm->support_ic_type & ODM_RTL8192F)
+				odm_set_mac_reg(dm, 0x7f0, BIT(3), 1);
+			else
+				odm_set_mac_reg(dm, 0x7c0, BIT(3), 1);
+		}
+	}
+
+	target_polling_bit = (smp->is_bb_trigger) ? BIT(1) : BIT(2);
+	do { /*Polling time always use 100ms, when it exceed 2s, break loop*/
+		if (dm->support_ic_type & ODM_RTL8192F) {
+			tmp_u1b = odm_read_1byte(dm, 0x7F0);
+			pr_debug("[%d], 0x7F0[7:0] = ((0x%x))\n", while_cnt,
+				 tmp_u1b);
+		} else {
+			tmp_u1b = odm_read_1byte(dm, 0x7C0);
+			pr_debug("[%d], 0x7C0[7:0] = ((0x%x))\n", while_cnt,
+				 tmp_u1b);
+		}
+
+		if (smp->adc_smp_state != ADCSMP_STATE_SET) {
+			pr_debug("[state Error] adc_smp_state != ADCSMP_STATE_SET\n");
+			break;
+
+		} else if (tmp_u1b & target_polling_bit) {
+			ODM_delay_ms(100);
+			while_cnt = while_cnt + 1;
+			continue;
+		} else {
+			pr_debug("[LA Query OK] polling_bit=((0x%x))\n",
+				 target_polling_bit);
+			polling_ok = true;
+			break;
+		}
+	} while (while_cnt < 20);
+
+	if (smp->adc_smp_state == ADCSMP_STATE_SET) {
+		if (polling_ok)
+			phydm_la_get_tx_pkt_buf(dm);
+		else
+			pr_debug("[Polling timeout]\n");
+	}
+
+	#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
+	watchdog_resume(dm->priv);
+	#endif
+
+	#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
+	if (smp->adc_smp_state == ADCSMP_STATE_SET)
+		smp->adc_smp_state = ADCSMP_STATE_QUERY;
+	#endif
+
+	pr_debug("[LA mode] LA_pattern_count = ((%d))\n", smp->la_count);
+	#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
+	RT_TRACE_EX(COMP_LA_MODE, DBG_LOUD,
+		    ("[LA mode] la_count = ((%d))\n", smp->la_count));
+	#endif
+
+	adc_smp_stop(dm);
+
+	if (smp->la_count == 0) {
+		pr_debug("LA Dump finished ---------->\n\n\n");
+		phydm_release_bb_dbg_port(dm);
+
+		if ((dm->support_ic_type & ODM_RTL8821C) &&
+		    dm->cut_version >= ODM_CUT_B)
+			odm_set_bb_reg(dm, R_0x95c, BIT(23), 0);
+
+	} else {
+		smp->la_count--;
+		pr_debug("LA Dump more ---------->\n\n\n");
+		adc_smp_set(dm, smp->la_trig_mode, smp->la_trig_sig_sel,
+			    smp->la_dma_type, smp->la_trigger_time, 0);
+	}
+}
+
+#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
+void adc_smp_work_item_callback(void *context)
+{
+	void *adapter = (void *)context;
+	PHAL_DATA_TYPE hal_data = GET_HAL_DATA(((PADAPTER)adapter));
+	struct dm_struct *dm = &hal_data->DM_OutSrc;
+	struct rt_adcsmp *smp = &dm->adcsmp;
+
+	pr_debug("[WorkItem Call back] LA_State=((%d))\n", smp->adc_smp_state);
+	phydm_adc_smp_start(dm);
+}
+#endif
+
+void adc_smp_set(void *dm_void, u8 trig_mode, u32 trig_sig_sel,
+		 u8 dma_data_sig_sel, u32 trig_time, u16 polling_time)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	boolean is_set_success = true;
+	struct rt_adcsmp *smp = &dm->adcsmp;
+
+	smp->la_trig_mode = trig_mode;
+	smp->la_trig_sig_sel = trig_sig_sel;
+	smp->la_dma_type = dma_data_sig_sel;
+	smp->la_trigger_time = trig_time;
+
+	#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
+	if (smp->adc_smp_state != ADCSMP_STATE_IDLE)
+		is_set_success = false;
+	else if (smp->adc_smp_buf.length == 0)
+		is_set_success = phydm_la_buffer_allocate(dm);
+	#endif
+
+	if (is_set_success) {
+		smp->adc_smp_state = ADCSMP_STATE_SET;
+
+		pr_debug("[LA Set Success] LA_State=((%d))\n",
+			 smp->adc_smp_state);
+
+		#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
+
+		pr_debug("ADCSmp_work_item_index = ((%d))\n",
+			 smp->la_work_item_index);
+		if (smp->la_work_item_index != 0) {
+			odm_schedule_work_item(&smp->adc_smp_work_item_1);
+			smp->la_work_item_index = 0;
+		} else {
+			odm_schedule_work_item(&smp->adc_smp_work_item);
+			smp->la_work_item_index = 1;
+		}
+		#else
+		phydm_adc_smp_start(dm);
+		#endif
+	} else {
+		pr_debug("[LA Set Fail] LA_State=((%d))\n", smp->adc_smp_state);
+	}
+}
+
+#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
+enum rt_status
+adc_smp_query(void *dm_void, ULONG info_buf_length, void *info_buf,
+	      PULONG bytes_written)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct rt_adcsmp *smp = &dm->adcsmp;
+	enum rt_status ret_status = RT_STATUS_SUCCESS;
+	struct rt_adcsmp_string *buf = &smp->adc_smp_buf;
+
+	pr_debug("[%s] LA_State=((%d))", __func__, smp->adc_smp_state);
+
+	if (info_buf_length != buf->buffer_size) {
+		*bytes_written = 0;
+		ret_status = RT_STATUS_RESOURCE;
+	} else if (buf->length != buf->buffer_size) {
+		*bytes_written = 0;
+		ret_status = RT_STATUS_RESOURCE;
+	} else if (smp->adc_smp_state != ADCSMP_STATE_QUERY) {
+		*bytes_written = 0;
+		ret_status = RT_STATUS_PENDING;
+	} else {
+		odm_move_memory(dm, info_buf, buf->octet, buf->buffer_size);
+		*bytes_written = buf->buffer_size;
+
+		smp->adc_smp_state = ADCSMP_STATE_IDLE;
+	}
+
+	pr_debug("Return status %d\n", ret_status);
+
+	return ret_status;
+}
+#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
+
+void adc_smp_query(void *dm_void, void *output, u32 out_len, u32 *pused)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct rt_adcsmp *smp = &dm->adcsmp;
+	struct rt_adcsmp_string *buf = &smp->adc_smp_buf;
+	u32 used = *pused;
+	u32 i = 0;
+#if 0
+	/* struct timespec t; */
+	/* rtw_get_current_timespec(&t); */
+#endif
+
+	pr_debug("%s adc_smp_state %d", __func__, smp->adc_smp_state);
+
+	for (i = 0; i < (buf->length >> 2) - 2; i += 2) {
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "%08x%08x\n", buf->octet[i], buf->octet[i + 1]);
+	}
+
+	PDM_SNPF(out_len, used, output + used, out_len - used, "\n");
+	/* PDM_SNPF(output + used, out_len - used, "\n[%lu.%06lu]\n", */
+	/*	    t.tv_sec, t.tv_nsec); */
+	*pused = used;
+}
+
+s32 adc_smp_get_sample_counts(void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct rt_adcsmp *smp = &dm->adcsmp;
+	struct rt_adcsmp_string *buf = &smp->adc_smp_buf;
+
+	return (buf->length >> 2) - 2;
+}
+
+s32 adc_smp_query_single_data(void *dm_void, void *output, u32 out_len, u32 idx)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct rt_adcsmp *smp = &dm->adcsmp;
+	struct rt_adcsmp_string *buf = &smp->adc_smp_buf;
+	u32 used = 0;
+
+	/* @dbg_print("%s adc_smp_state %d\n", __func__,*/
+	/*	      smp->adc_smp_state);*/
+	if (smp->adc_smp_state != ADCSMP_STATE_QUERY) {
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "Error: la data is not ready yet ...\n");
+		return -1;
+	}
+
+	if (idx < ((buf->length >> 2) - 2)) {
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "%08x%08x\n", buf->octet[idx], buf->octet[idx + 1]);
+	}
+	return 0;
+}
+
+#endif
+
+void adc_smp_stop(void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct rt_adcsmp *smp = &dm->adcsmp;
+
+	smp->adc_smp_state = ADCSMP_STATE_IDLE;
+
+	PHYDM_DBG(dm, DBG_TMP, "[LA_Stop] LA_state = %d\n", smp->adc_smp_state);
+}
+
+void adc_smp_init(void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct rt_adcsmp *smp = &dm->adcsmp;
+	struct rt_adcsmp_string *buf = &smp->adc_smp_buf;
+
+	smp->adc_smp_state = ADCSMP_STATE_IDLE;
+
+	if (dm->support_ic_type & ODM_RTL8814A) {
+		buf->start_pos = 0x30000;
+		buf->buffer_size = 0x10000;
+	} else if (dm->support_ic_type & (ODM_RTL8822B | ODM_RTL8822C)) {
+		buf->start_pos = 0x20000;
+		buf->buffer_size = 0x20000;
+	} else if (dm->support_ic_type & (ODM_RTL8197F | ODM_RTL8198F)) {
+		buf->start_pos = 0x00000;
+		buf->buffer_size = 0x10000;
+	} else if (dm->support_ic_type & ODM_RTL8192F) {
+		buf->start_pos = 0x2000;
+		buf->buffer_size = 0xE000;
+	} else if (dm->support_ic_type & ODM_RTL8821C) {
+		buf->start_pos = 0x8000;
+		buf->buffer_size = 0x8000;
+	}
+
+	buf->end_pos = buf->start_pos + buf->buffer_size;
+
+	PHYDM_DBG(dm, DBG_TMP,
+		  "start_addr = ((0x%x)), end_addr = ((0x%x)), buffer_size = ((%d))\n",
+		  buf->start_pos, buf->end_pos, buf->buffer_size);
+}
+
+#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
+void adc_smp_de_init(void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct rt_adcsmp *smp = &dm->adcsmp;
+	struct rt_adcsmp_string *buf = &smp->adc_smp_buf;
+
+	adc_smp_stop(dm);
+
+	if (buf->length != 0x0) {
+		odm_free_memory(dm, buf->octet, buf->length);
+		buf->length = 0x0;
+	}
+}
+
+#endif
+
+void phydm_la_mode_bb_setting(void *dm_void, boolean en_fake_trig)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct rt_adcsmp *smp = &dm->adcsmp;
+
+	u8	trig_mode = smp->la_trig_mode;
+	u32	trig_sel = smp->la_trig_sig_sel;
+	u32	dbg_port = smp->la_dbg_port;
+	u8	edge = smp->la_trigger_edge;
+	u8	smp_rate = smp->la_smp_rate;
+	u8	dma_type = smp->la_dma_type;
+	u8	is_fake_trig = smp->is_fake_trig;
+	u32	dbg_port_hdr_sel = 0;
+	#if (RTL8198F_SUPPORT || RTL8822C_SUPPORT)
+	boolean en_new_bbtrigger = smp->la_en_new_bbtrigger;
+	boolean ori_bb_dis = smp->la_ori_bb_dis;
+	u8	and1_sel = smp->la_and1_sel;
+	u8	and1_val = smp->la_and1_val;
+	u8	and2_sel = smp->la_and2_sel;
+	u8	and2_val = smp->la_and2_val;
+	u8	and3_sel = smp->la_and3_sel;
+	u8	and3_val = smp->la_and3_val;
+	u32	and4_en = smp->la_and4_en;
+	u32	and4_val = smp->la_and4_val;
+	#endif
+
+	#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
+	RT_TRACE_EX(COMP_LA_MODE, DBG_LOUD,
+		    ("1. [LA mode bb_setting]trig_mode = ((%d)), dbg_port = ((0x%x)), Trig_Edge = ((%d)), smp_rate = ((%d)), Trig_Sel = ((0x%x)), Dma_type = ((%d))\n",
+		    trig_mode, dbg_port, edge, smp_rate, trig_sel, dma_type));
+	#endif
+
+	if (trig_mode == PHYDM_MAC_TRIG)
+		trig_sel = 0; /*@ignore this setting*/
+
+	/*set BB debug port*/
+	if (is_fake_trig) {
+		if (phydm_set_bb_dbg_port(dm, DBGPORT_PRI_3, 0xf))
+			pr_debug("Set fake dbg_port success\n");
+		if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
+			/*@0x95C[4:0], BB debug port bit*/
+			odm_set_bb_reg(dm, R_0x95c, 0x1f, 0x0);
+		#if (RTL8198F_SUPPORT || RTL8822C_SUPPORT)
+		} else if (dm->support_ic_type &
+			   (ODM_RTL8198F | ODM_RTL8822C)) {
+			if (!(en_new_bbtrigger))
+				odm_set_bb_reg(dm, R_0x1ce4, 0x3e000, 0x0);
+			else if (!(ori_bb_dis))
+				odm_set_bb_reg(dm, R_0x1ce4, 0x3e000, 0x0);
+		#endif
+		} else {
+			/*@0x9A0[4:0], BB debug port bit*/
+			odm_set_bb_reg(dm, R_0x9a0, 0x1f, 0x0);
+		}
+
+		pr_debug("1. [BB Setting] is_fake\n");
+	} else {
+		if (en_fake_trig)
+			phydm_release_bb_dbg_port(dm);
+		if (phydm_set_bb_dbg_port(dm, DBGPORT_PRI_3, dbg_port))
+			pr_debug("Set dbg_port((0x%x)) success\n", dbg_port);
+		else
+			pr_debug("Set dbg_port fail!\n");
+		if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
+			/*@0x95C[4:0], BB debug port bit*/
+			odm_set_bb_reg(dm, R_0x95c, 0x1f, trig_sel);
+		#if (RTL8198F_SUPPORT || RTL8822C_SUPPORT)
+		} else if (dm->support_ic_type &
+			   (ODM_RTL8198F | ODM_RTL8822C)) {
+			if (!(en_new_bbtrigger))
+				odm_set_bb_reg(dm, R_0x1ce4, 0x3e000, trig_sel);
+			else if (!(ori_bb_dis))
+				odm_set_bb_reg(dm, R_0x1ce4, 0x3e000, trig_sel);
+		#endif
+		} else {
+			/*@0x9A0[4:0], BB debug port bit*/
+			odm_set_bb_reg(dm, R_0x9a0, 0x1f, trig_sel);
+		}
+		pr_debug("1. [BB Setting] is_fake = ((%d)),  trig_mode = ((%d)), dbg_port = ((0x%x)), Trig_Edge = ((%d)), smp_rate = ((%d)), Trig_Sel = ((0x%x)), Dma_type = ((%d))\n",
+			 is_fake_trig, trig_mode, dbg_port, edge, smp_rate,
+			 trig_sel, dma_type);
+		if (en_fake_trig)
+			return;
+	}
+
+	if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
+		if (trig_mode == PHYDM_ADC_RF0_TRIG)
+			dbg_port_hdr_sel = 9; /*@DBGOUT_RFC_a[31:0]*/
+		else if (trig_mode == PHYDM_ADC_RF1_TRIG)
+			dbg_port_hdr_sel = 8; /*@DBGOUT_RFC_b[31:0]*/
+		else if ((trig_mode == PHYDM_ADC_BB_TRIG) ||
+			 (trig_mode == PHYDM_ADC_MAC_TRIG)) {
+			if (smp->la_mac_mask_or_hdr_sel <= 0xf)
+				dbg_port_hdr_sel = smp->la_mac_mask_or_hdr_sel;
+			else
+				dbg_port_hdr_sel = 0;
+		}
+
+		phydm_bb_dbg_port_header_sel(dm, dbg_port_hdr_sel);
+
+		/*@0x95C[11:8]*/
+		odm_set_bb_reg(dm, R_0x95c, 0xf00, dma_type);
+		/*@0: posedge, 1: negedge*/
+		odm_set_bb_reg(dm, R_0x95c, BIT(31), edge);
+		odm_set_bb_reg(dm, R_0x95c, 0xe0, smp_rate);
+		/*	@(0:) '80MHz'
+		 *	(1:) '40MHz'
+		 *	(2:) '20MHz'
+		 *	(3:) '10MHz'
+		 *	(4:) '5MHz'
+		 *	(5:) '2.5MHz'
+		 *	(6:) '1.25MHz'
+		 *	(7:) '160MHz (for BW160 ic)'
+		 */
+		if ((dm->support_ic_type & ODM_RTL8821C) &&
+		    (dm->cut_version >= ODM_CUT_B))
+			odm_set_bb_reg(dm, R_0x95c, BIT(23), 1);
+	#if (RTL8198F_SUPPORT || RTL8822C_SUPPORT)
+	} else if (dm->support_ic_type & (ODM_RTL8198F | ODM_RTL8822C)) {
+		/*@MAC-PHY timing*/
+		odm_set_bb_reg(dm, R_0x1ce4, BIT(7) | BIT(6), 0);
+		odm_set_bb_reg(dm, R_0x1cf4, BIT(23), 1); /*@LA mode on*/
+		odm_set_bb_reg(dm, R_0x1ce4, 0x3f, dma_type);
+		/*@0: posedge, 1: negedge ??*/
+		odm_set_bb_reg(dm, R_0x1ce4, BIT(26), edge);
+		odm_set_bb_reg(dm, R_0x1ce4, 0x700, smp_rate);
+
+		if (!en_new_bbtrigger) { /*normal LA mode & back to default*/
+
+			pr_debug("Set bb default setting\n");
+
+			/*path 1 default: enable ori. BB trigger*/
+			odm_set_bb_reg(dm, R_0x1ce4, BIT(27), 0);
+
+			/*@AND1~AND4 default: off*/
+			odm_set_bb_reg(dm, R_0x1ce4, MASKH4BITS, 0); /*@AND 1*/
+			odm_set_bb_reg(dm, R_0x1ce8, 0x1f, 0); /*@AND 1 val*/
+			odm_set_bb_reg(dm, R_0x1ce8, BIT(5), 0); /*@AND 1 inv*/
+
+			odm_set_bb_reg(dm, R_0x1ce8, 0x3c0, 0); /*@AND 2*/
+			odm_set_bb_reg(dm, R_0x1ce8, 0x7c00, 0); /*@AND 2 val*/
+			/*@AND 2 inv*/
+			odm_set_bb_reg(dm, R_0x1ce8, BIT(15), 0);
+
+			odm_set_bb_reg(dm, R_0x1ce8, 0xf0000, 0); /*@AND 3*/
+			/*@AND 3 val*/
+			odm_set_bb_reg(dm, R_0x1ce8, 0x1f00000, 0);
+			/*@AND 3 inv*/
+			odm_set_bb_reg(dm, R_0x1ce8, BIT(25), 0);
+
+			/*@AND 4 en*/
+			odm_set_bb_reg(dm, R_0x1cf0, MASKDWORD, 0);
+			/*@AND 4 val*/
+			odm_set_bb_reg(dm, R_0x1cec, MASKDWORD, 0);
+			/*@AND 4 inv*/
+			odm_set_bb_reg(dm, R_0x1ce8, BIT(26), 0);
+
+			pr_debug("Set bb default setting finished\n");
+
+		} else if (en_new_bbtrigger) {
+			/*path 1 default: enable ori. BB trigger*/
+			if (ori_bb_dis)
+				odm_set_bb_reg(dm, R_0x1ce4, BIT(27), 1);
+			else
+				odm_set_bb_reg(dm, R_0x1ce4, BIT(27), 0);
+
+			/* @AND1 */
+			odm_set_bb_reg(dm, R_0x1ce8, BIT(5), 0); /*@invert*/
+
+			if (and1_sel == 0x4 || and1_sel == 0x5 ||
+			    and1_sel == 0x6) {
+				/* rx_state, rx_state_freq, field */
+				odm_set_bb_reg(dm, R_0x1ce4, MASKH4BITS,
+					       and1_sel);
+				odm_set_bb_reg(dm, R_0x1ce8, 0x1f, and1_val);
+
+			} else if (and1_sel == 0x7) {
+				/* @mux state */
+				odm_set_bb_reg(dm, R_0x1ce4, MASKH4BITS,
+					       and1_sel);
+				odm_set_bb_reg(dm, R_0x1ce8, 0xf, and1_val);
+
+			} else {
+				odm_set_bb_reg(dm, R_0x1ce4, MASKH4BITS,
+					       and1_sel);
+			}
+
+			/* @AND2 */
+			odm_set_bb_reg(dm, R_0x1ce8, BIT(15), 0); /*@invert*/
+
+			if (and2_sel == 0x4 || and2_sel == 0x5 ||
+			    and2_sel == 0x6) {
+				/* rx_state, rx_state_freq, field */
+				odm_set_bb_reg(dm, R_0x1ce8, 0x3c0, and2_sel);
+				odm_set_bb_reg(dm, R_0x1ce8, 0x7c00, and2_val);
+
+			} else if (and2_sel == 0x7) {
+				/* @mux state */
+				odm_set_bb_reg(dm, R_0x1ce8, 0x3c0, and2_sel);
+				odm_set_bb_reg(dm, R_0x1ce8, 0x3c00, and2_val);
+
+			} else {
+				odm_set_bb_reg(dm, R_0x1ce8, 0x3c0, and2_sel);
+			}
+
+			/* @AND3 */
+			odm_set_bb_reg(dm, R_0x1ce8, BIT(25), 0); /*@invert*/
+
+			if (and3_sel == 0x4 || and3_sel == 0x5 ||
+			    and3_sel == 0x6) {
+				/* rx_state, rx_state_freq, field */
+				odm_set_bb_reg(dm, R_0x1ce8, 0xf0000, and3_sel);
+				odm_set_bb_reg(dm, R_0x1ce8, 0x1f00000,
+					       and3_val);
+
+			} else if (and3_sel == 0x7) {
+				/* @mux state */
+				odm_set_bb_reg(dm, R_0x1ce8, 0xf0000, and3_sel);
+				odm_set_bb_reg(dm, R_0x1ce8, 0xf00000,
+					       and3_val);
+			} else {
+				odm_set_bb_reg(dm, R_0x1ce8, 0xf0000, and3_sel);
+			}
+
+			/* @AND4 */
+			odm_set_bb_reg(dm, R_0x1ce8, BIT(26), 0); /*@invert*/
+			odm_set_bb_reg(dm, R_0x1cf0, MASKDWORD, and4_en);
+			odm_set_bb_reg(dm, R_0x1cec, MASKDWORD, and4_val);
+			}
+	#endif
+	} else {
+		#if (RTL8192F_SUPPORT)
+		if ((dm->support_ic_type & ODM_RTL8192F))
+			/*@LA reset HW block enable for true-mac asic*/
+			odm_set_bb_reg(dm, R_0x9a0, BIT(15), 1);
+		#endif
+		/*@0x9A0[11:8]*/
+		odm_set_bb_reg(dm, R_0x9a0, 0xf00, dma_type);
+		/*@0: posedge, 1: negedge*/
+		odm_set_bb_reg(dm, R_0x9a0, BIT(31), edge);
+		odm_set_bb_reg(dm, R_0x9a0, 0xe0, smp_rate);
+		/*	@(0:) '80MHz'
+		 *	(1:) '40MHz'
+		 *	(2:) '20MHz'
+		 *	(3:) '10MHz'
+		 *	(4:) '5MHz'
+		 *	(5:) '2.5MHz'
+		 *	(6:) '1.25MHz'
+		 *	(7:) '160MHz (for BW160 ic)'
+		 */
+	}
+}
+
+void phydm_la_mode_set_trigger_time(void *dm_void, u32 trigger_time_mu_sec)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	u8 time_unit_num = 0;
+	u32 unit = 0;
+
+	if (trigger_time_mu_sec < 128)
+		unit = 0; /*unit: 1mu sec*/
+	else if (trigger_time_mu_sec < 256)
+		unit = 1; /*unit: 2mu sec*/
+	else if (trigger_time_mu_sec < 512)
+		unit = 2; /*unit: 4mu sec*/
+	else if (trigger_time_mu_sec < 1024)
+		unit = 3; /*unit: 8mu sec*/
+	else if (trigger_time_mu_sec < 2048)
+		unit = 4; /*unit: 16mu sec*/
+	else if (trigger_time_mu_sec < 4096)
+		unit = 5; /*unit: 32mu sec*/
+	else if (trigger_time_mu_sec < 8192)
+		unit = 6; /*unit: 64mu sec*/
+
+	time_unit_num = (u8)(trigger_time_mu_sec >> unit);
+
+	pr_debug("2. [Set Trigger Time] Trig_Time = ((%d)) * unit = ((2^%d us))\n",
+		 time_unit_num, unit);
+	#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
+	RT_TRACE_EX(COMP_LA_MODE, DBG_LOUD, (
+		    "3. [Set Trigger Time] Trig_Time = ((%d)) * unit = ((2^%d us))\n",
+		    time_unit_num, unit));
+	#endif
+
+	if (dm->support_ic_type & ODM_RTL8192F) {
+		odm_set_mac_reg(dm, R_0x7fc, BIT(2) | BIT(1) | BIT(0), unit);
+		odm_set_mac_reg(dm, R_0x7f0, 0x7f00, (time_unit_num & 0x7f));
+	#if (RTL8198F_SUPPORT || RTL8822C_SUPPORT)
+	} else if (dm->support_ic_type & (ODM_RTL8198F | ODM_RTL8822C)) {
+		odm_set_mac_reg(dm, R_0x7cc, BIT(18) | BIT(17) | BIT(16), unit);
+		odm_set_mac_reg(dm, R_0x7c0, 0x7f00, (time_unit_num & 0x7f));
+	#endif
+	} else {
+		odm_set_mac_reg(dm, R_0x7cc, BIT(20) | BIT(19) | BIT(18), unit);
+		odm_set_mac_reg(dm, R_0x7c0, 0x7f00, (time_unit_num & 0x7f));
+	}
+}
+
+void phydm_lamode_trigger_cmd(void *dm_void, char input[][16], u32 *_used,
+			      char *output, u32 *_out_len)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct rt_adcsmp *smp = &dm->adcsmp;
+	u8 trig_mode = 0, dma_data_sig_sel = 0;
+	u32 trig_sig_sel = 0;
+	u8 enable_la_mode = 0;
+	u32 trigger_time_mu_sec = 0;
+	char help[] = "-h";
+	u32 var1[10] = {0};
+	u32 used = *_used;
+	u32 out_len = *_out_len;
+
+	if (dm->support_ic_type & PHYDM_IC_SUPPORT_LA_MODE) {
+		PHYDM_SSCANF(input[1], DCMD_DECIMAL, &var1[0]);
+		enable_la_mode = (u8)var1[0];
+#if 0
+		/*@dbg_print("echo cmd input_num = %d\n", input_num);*/
+#endif
+
+		if ((strcmp(input[1], help) == 0)) {
+			PDM_SNPF(out_len, used, output + used, out_len - used,
+				 "{En} {0:BB,1:BB_MAC,2:RF0,3:RF1,4:MAC} \n {BB:dbg_port[bit],BB_MAC:0-ok/1-fail/2-cca,MAC:ref} {DMA type} {TrigTime} \n {DbgPort_head/ref_mask} {dbg_port} {0:P_Edge, 1:N_Edge} {SpRate:0-80M,1-40M,2-20M} {Capture num}\n");
+		} else if (enable_la_mode == 1) {
+			PHYDM_SSCANF(input[2], DCMD_DECIMAL, &var1[1]);
+
+			trig_mode = (u8)var1[1];
+
+			if (trig_mode == PHYDM_MAC_TRIG)
+				PHYDM_SSCANF(input[3], DCMD_HEX, &var1[2]);
+			else
+				PHYDM_SSCANF(input[3], DCMD_DECIMAL, &var1[2]);
+			trig_sig_sel = var1[2];
+
+			PHYDM_SSCANF(input[4], DCMD_DECIMAL, &var1[3]);
+			PHYDM_SSCANF(input[5], DCMD_DECIMAL, &var1[4]);
+			PHYDM_SSCANF(input[6], DCMD_HEX, &var1[5]);
+			PHYDM_SSCANF(input[7], DCMD_HEX, &var1[6]);
+			PHYDM_SSCANF(input[8], DCMD_DECIMAL, &var1[7]);
+			PHYDM_SSCANF(input[9], DCMD_DECIMAL, &var1[8]);
+			PHYDM_SSCANF(input[10], DCMD_DECIMAL, &var1[9]);
+
+			dma_data_sig_sel = (u8)var1[3];
+			trigger_time_mu_sec = var1[4]; /*unit: us*/
+
+			smp->la_mac_mask_or_hdr_sel = var1[5];
+			smp->la_dbg_port = var1[6];
+			smp->la_trigger_edge = (u8)var1[7];
+			smp->la_smp_rate = (u8)(var1[8] & 0x7);
+			smp->la_count = var1[9];
+
+			#if (RTL8198F_SUPPORT || RTL8822C_SUPPORT)
+			smp->la_en_new_bbtrigger = false;
+			#endif
+
+			pr_debug("echo lamode %d %d %d %d %d %d %x %d %d %d\n",
+				 var1[0], var1[1], var1[2], var1[3], var1[4],
+				 var1[5], var1[6], var1[7], var1[8], var1[9]);
+			#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
+			RT_TRACE_EX(COMP_LA_MODE, DBG_LOUD, (
+				    "echo lamode %d %d %d %d %d %d %x %d %d %d\n",
+				    var1[0], var1[1], var1[2], var1[3],
+				    var1[4], var1[5], var1[6], var1[7],
+				    var1[8], var1[9]));
+			#endif
+
+			PDM_SNPF(out_len, used, output + used, out_len - used,
+				 "a.En= ((1)),  b.mode = ((%d)), c.Trig_Sel = ((0x%x)), d.Dma_type = ((%d))\n",
+				 trig_mode, trig_sig_sel, dma_data_sig_sel);
+			PDM_SNPF(out_len, used, output + used, out_len - used,
+				 "e.Trig_Time = ((%dus)), f.Dbg_head/mac_ref_mask = ((0x%x)), g.dbg_port = ((0x%x))\n",
+				 trigger_time_mu_sec,
+				 smp->la_mac_mask_or_hdr_sel, smp->la_dbg_port);
+			PDM_SNPF(out_len, used, output + used, out_len - used,
+				 "h.Trig_edge = ((%d)), i.smp rate = ((%d MHz)), j.Cap_num = ((%d))\n",
+				 smp->la_trigger_edge, (80 >> smp->la_smp_rate),
+				 smp->la_count);
+
+			#if (RTL8198F_SUPPORT || RTL8822C_SUPPORT)
+			PDM_SNPF(out_len, used, output + used, out_len - used,
+				 "k.en_new_bbtrigger = ((%d))\n",
+				 smp->la_en_new_bbtrigger);
+			#endif
+
+			adc_smp_set(dm, trig_mode, trig_sig_sel,
+				    dma_data_sig_sel, trigger_time_mu_sec, 0);
+
+		#if (RTL8198F_SUPPORT || RTL8822C_SUPPORT)
+		} else if (enable_la_mode == 100) {
+			smp->la_en_new_bbtrigger = true;
+
+			PHYDM_SSCANF(input[2], DCMD_DECIMAL, &var1[1]);
+			PHYDM_SSCANF(input[3], DCMD_DECIMAL, &var1[2]);
+			PHYDM_SSCANF(input[4], DCMD_HEX, &var1[3]);
+			PHYDM_SSCANF(input[5], DCMD_DECIMAL, &var1[4]);
+			PHYDM_SSCANF(input[6], DCMD_HEX, &var1[5]);
+			PHYDM_SSCANF(input[7], DCMD_DECIMAL, &var1[6]);
+			PHYDM_SSCANF(input[8], DCMD_HEX, &var1[7]);
+			PHYDM_SSCANF(input[9], DCMD_HEX, &var1[8]);
+			PHYDM_SSCANF(input[10], DCMD_HEX, &var1[9]);
+
+			smp->la_ori_bb_dis = (boolean)var1[1];
+			smp->la_and1_sel = (u8)var1[2];
+			smp->la_and1_val = (u8)var1[3];
+			smp->la_and2_sel = (u8)var1[4];
+			smp->la_and2_val = (u8)var1[5];
+			smp->la_and3_sel = (u8)var1[6];
+			smp->la_and3_val = (u8)var1[7];
+			smp->la_and4_en = (u32)var1[8];
+			smp->la_and4_val = (u32)var1[9];
+
+			phydm_adc_smp_start(dm);
+
+		} else if (enable_la_mode == 101) {
+			smp->la_en_new_bbtrigger = false;
+			phydm_adc_smp_start(dm);
+		#endif
+		} else {
+			adc_smp_stop(dm);
+			PDM_SNPF(out_len, used, output + used, out_len - used,
+				 "Disable LA mode\n");
+		}
+	}
+	*_used = used;
+	*_out_len = out_len;
+}
+
+#endif /*@endif PHYDM_LA_MODE_SUPPORT*/
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/phydm_adc_sampling.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/phydm_adc_sampling.h
--- linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/phydm_adc_sampling.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/phydm_adc_sampling.h	2020-04-10 16:35:06.822660348 +0300
@@ -0,0 +1,134 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017  Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * The full GNU General Public License is included in this distribution in the
+ * file called LICENSE.
+ *
+ * Contact Information:
+ * wlanfae <wlanfae@realtek.com>
+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
+ * Hsinchu 300, Taiwan.
+ *
+ * Larry Finger <Larry.Finger@lwfinger.net>
+ *
+ *****************************************************************************/
+
+#ifndef __INC_ADCSMP_H
+#define __INC_ADCSMP_H
+
+#if (PHYDM_LA_MODE_SUPPORT)
+
+#define DYNAMIC_LA_MODE "2.0"
+
+struct rt_adcsmp_string {
+	u32		*octet;
+	u32		length;
+	u32		buffer_size;
+	u32		start_pos;
+	u32		end_pos;	/*@buf addr*/
+};
+
+enum rt_adcsmp_trig_sel {
+	PHYDM_ADC_BB_TRIG	= 0,
+	PHYDM_ADC_MAC_TRIG	= 1,
+	PHYDM_ADC_RF0_TRIG	= 2,
+	PHYDM_ADC_RF1_TRIG	= 3,
+	PHYDM_MAC_TRIG		= 4
+};
+
+enum rt_adcsmp_trig_sig_sel {
+	ADCSMP_TRIG_CRCOK	= 0,
+	ADCSMP_TRIG_CRCFAIL	= 1,
+	ADCSMP_TRIG_CCA		= 2,
+	ADCSMP_TRIG_REG		= 3
+};
+
+enum rt_adcsmp_state {
+	ADCSMP_STATE_IDLE		= 0,
+	ADCSMP_STATE_SET		= 1,
+	ADCSMP_STATE_QUERY	=	2
+};
+
+struct rt_adcsmp {
+	struct rt_adcsmp_string		adc_smp_buf;
+	enum rt_adcsmp_state		adc_smp_state;
+	u8					la_trig_mode;
+	u32					la_trig_sig_sel;
+	u8					la_dma_type;
+	u32					la_trigger_time;
+	/*
+	 * @1.BB mode: for debug port header sel;
+	 * 2.MAC mode: for reference mask
+	 */
+	u32					la_mac_mask_or_hdr_sel;
+	u32					la_dbg_port;
+	u8					la_trigger_edge;
+	u8					la_smp_rate;
+	u32					la_count;
+	u8					is_bb_trigger;
+	u8					la_work_item_index;
+	boolean					la_en_new_bbtrigger;
+	boolean					la_ori_bb_dis;
+	u8					la_and1_sel;
+	u8					la_and1_val;
+	u8					la_and2_sel;
+	u8					la_and2_val;
+	u8					la_and3_sel;
+	u8					la_and3_val;
+	u32					la_and4_en;
+	u32					la_and4_val;
+	boolean					is_fake_trig;
+
+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
+	RT_WORK_ITEM	adc_smp_work_item;
+	RT_WORK_ITEM	adc_smp_work_item_1;
+#endif
+};
+
+#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
+void adc_smp_work_item_callback(
+	void *context);
+#endif
+
+void adc_smp_set(void *dm_void, u8 trig_mode, u32 trig_sig_sel,
+		 u8 dma_data_sig_sel, u32 trig_time, u16 polling_time);
+
+#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
+enum rt_status
+adc_smp_query(void *dm_void, ULONG info_buf_length, void *info_buf,
+	      PULONG bytes_written);
+#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
+void adc_smp_query(void *dm_void, void *output, u32 out_len, u32 *pused);
+
+s32 adc_smp_get_sample_counts(void *dm_void);
+
+s32 adc_smp_query_single_data(void *dm_void, void *output, u32 out_len,
+			      u32 idx);
+
+#endif
+void adc_smp_stop(void *dm_void);
+
+void adc_smp_init(void *dm_void);
+
+#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
+void adc_smp_de_init(void *dm_void);
+#endif
+
+void phydm_la_mode_bb_setting(void *dm_void, boolean en_fake_trig);
+
+void phydm_la_mode_set_trigger_time(void *dm_void, u32 trigger_time_mu_sec);
+
+void phydm_lamode_trigger_cmd(void *dm_void, char input[][16], u32 *_used,
+			      char *output, u32 *_out_len);
+#endif
+#endif
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/phydm_antdect.c linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/phydm_antdect.c
--- linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/phydm_antdect.c	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/phydm_antdect.c	2020-04-10 16:35:06.822660348 +0300
@@ -0,0 +1,891 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017  Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * The full GNU General Public License is included in this distribution in the
+ * file called LICENSE.
+ *
+ * Contact Information:
+ * wlanfae <wlanfae@realtek.com>
+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
+ * Hsinchu 300, Taiwan.
+ *
+ * Larry Finger <Larry.Finger@lwfinger.net>
+ *
+ *****************************************************************************/
+
+/* ************************************************************
+ * include files
+ * ************************************************************ */
+
+#include "mp_precomp.h"
+#include "phydm_precomp.h"
+
+#ifdef CONFIG_ANT_DETECTION
+
+/* @IS_ANT_DETECT_SUPPORT_SINGLE_TONE(adapter)
+ * IS_ANT_DETECT_SUPPORT_RSSI(adapter)
+ * IS_ANT_DETECT_SUPPORT_PSD(adapter) */
+
+/* @1 [1. Single Tone method] =================================================== */
+
+/*@
+ * Description:
+ *	Set Single/Dual Antenna default setting for products that do not do detection in advance.
+ *
+ * Added by Joseph, 2012.03.22
+ *   */
+void odm_sw_ant_div_construct_scan_chnl(
+	void *adapter,
+	u8 scan_chnl)
+{
+}
+
+u8 odm_sw_ant_div_select_scan_chnl(
+	void *adapter)
+{
+	return 0;
+}
+
+void odm_single_dual_antenna_default_setting(
+	void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct sw_antenna_switch *dm_swat_table = &dm->dm_swat_table;
+	void *adapter = dm->adapter;
+
+	u8 bt_ant_num = BT_GetPgAntNum(adapter);
+	/* Set default antenna A and B status */
+	if (bt_ant_num == 2) {
+		dm_swat_table->ANTA_ON = true;
+		dm_swat_table->ANTB_ON = true;
+
+	} else if (bt_ant_num == 1) {
+		/* Set antenna A as default */
+		dm_swat_table->ANTA_ON = true;
+		dm_swat_table->ANTB_ON = false;
+
+	} else
+		RT_ASSERT(false, ("Incorrect antenna number!!\n"));
+}
+
+/* @2 8723A ANT DETECT
+ *
+ * Description:
+ *	Implement IQK single tone for RF DPK loopback and BB PSD scanning.
+ *	This function is cooperated with BB team Neil.
+ *
+ * Added by Roger, 2011.12.15
+ *   */
+boolean
+odm_single_dual_antenna_detection(
+	void *dm_void,
+	u8 mode)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	void *adapter = dm->adapter;
+	struct sw_antenna_switch *dm_swat_table = &dm->dm_swat_table;
+	u32 current_channel, rf_loop_reg;
+	u8 n;
+	u32 reg88c, regc08, reg874, regc50, reg948, regb2c, reg92c, reg930, reg064, afe_rrx_wait_cca;
+	u8 initial_gain = 0x5a;
+	u32 PSD_report_tmp;
+	u32 ant_a_report = 0x0, ant_b_report = 0x0, ant_0_report = 0x0;
+	boolean is_result = true;
+
+	PHYDM_DBG(dm, DBG_ANT_DIV, "%s============>\n", __func__);
+
+	if (!(dm->support_ic_type & ODM_RTL8723B))
+		return is_result;
+
+	/* Retrieve antenna detection registry info, added by Roger, 2012.11.27. */
+	if (!IS_ANT_DETECT_SUPPORT_SINGLE_TONE(((PADAPTER)adapter)))
+		return is_result;
+
+	/* @1 Backup Current RF/BB Settings */
+
+	current_channel = odm_get_rf_reg(dm, RF_PATH_A, ODM_CHANNEL, RFREGOFFSETMASK);
+	rf_loop_reg = odm_get_rf_reg(dm, RF_PATH_A, RF_0x00, RFREGOFFSETMASK);
+	if (dm->support_ic_type & ODM_RTL8723B) {
+		reg92c = odm_get_bb_reg(dm, REG_DPDT_CONTROL, MASKDWORD);
+		reg930 = odm_get_bb_reg(dm, rfe_ctrl_anta_src, MASKDWORD);
+		reg948 = odm_get_bb_reg(dm, REG_S0_S1_PATH_SWITCH, MASKDWORD);
+		regb2c = odm_get_bb_reg(dm, REG_AGC_TABLE_SELECT, MASKDWORD);
+		reg064 = odm_get_mac_reg(dm, REG_SYM_WLBT_PAPE_SEL, BIT(29));
+		odm_set_bb_reg(dm, REG_DPDT_CONTROL, 0x3, 0x1);
+		odm_set_bb_reg(dm, rfe_ctrl_anta_src, 0xff, 0x77);
+		odm_set_mac_reg(dm, REG_SYM_WLBT_PAPE_SEL, BIT(29), 0x1); /* @dbg 7 */
+		odm_set_bb_reg(dm, REG_S0_S1_PATH_SWITCH, 0x3c0, 0x0); /* @dbg 8 */
+		odm_set_bb_reg(dm, REG_AGC_TABLE_SELECT, BIT(31), 0x0);
+	}
+
+	ODM_delay_us(10);
+
+	/* Store A path Register 88c, c08, 874, c50 */
+	reg88c = odm_get_bb_reg(dm, REG_FPGA0_ANALOG_PARAMETER4, MASKDWORD);
+	regc08 = odm_get_bb_reg(dm, REG_OFDM_0_TR_MUX_PAR, MASKDWORD);
+	reg874 = odm_get_bb_reg(dm, REG_FPGA0_XCD_RF_INTERFACE_SW, MASKDWORD);
+	regc50 = odm_get_bb_reg(dm, REG_OFDM_0_XA_AGC_CORE1, MASKDWORD);
+
+	/* Store AFE Registers */
+	if (dm->support_ic_type & ODM_RTL8723B)
+		afe_rrx_wait_cca = odm_get_bb_reg(dm, REG_RX_WAIT_CCA, MASKDWORD);
+
+	/* Set PSD 128 pts */
+	odm_set_bb_reg(dm, REG_FPGA0_PSD_FUNCTION, BIT(14) | BIT15, 0x0); /* @128 pts */
+
+	/* To SET CH1 to do */
+	odm_set_rf_reg(dm, RF_PATH_A, ODM_CHANNEL, RFREGOFFSETMASK, 0x7401); /* @channel 1 */
+
+	/* @AFE all on step */
+	if (dm->support_ic_type & ODM_RTL8723B)
+		odm_set_bb_reg(dm, REG_RX_WAIT_CCA, MASKDWORD, 0x01c00016);
+
+	/* @3 wire Disable */
+	odm_set_bb_reg(dm, REG_FPGA0_ANALOG_PARAMETER4, MASKDWORD, 0xCCF000C0);
+
+	/* @BB IQK setting */
+	odm_set_bb_reg(dm, REG_OFDM_0_TR_MUX_PAR, MASKDWORD, 0x000800E4);
+	odm_set_bb_reg(dm, REG_FPGA0_XCD_RF_INTERFACE_SW, MASKDWORD, 0x22208000);
+
+	/* @IQK setting tone@ 4.34Mhz */
+	odm_set_bb_reg(dm, REG_TX_IQK_TONE_A, MASKDWORD, 0x10008C1C);
+	odm_set_bb_reg(dm, REG_TX_IQK, MASKDWORD, 0x01007c00);
+
+	/* Page B init */
+	odm_set_bb_reg(dm, REG_CONFIG_ANT_A, MASKDWORD, 0x00080000);
+	odm_set_bb_reg(dm, REG_CONFIG_ANT_A, MASKDWORD, 0x0f600000);
+	odm_set_bb_reg(dm, REG_RX_IQK, MASKDWORD, 0x01004800);
+	odm_set_bb_reg(dm, REG_RX_IQK_TONE_A, MASKDWORD, 0x10008c1f);
+	if (dm->support_ic_type & ODM_RTL8723B) {
+		odm_set_bb_reg(dm, REG_TX_IQK_PI_A, MASKDWORD, 0x82150016);
+		odm_set_bb_reg(dm, REG_RX_IQK_PI_A, MASKDWORD, 0x28150016);
+	}
+	odm_set_bb_reg(dm, REG_IQK_AGC_RSP, MASKDWORD, 0x001028d0);
+	odm_set_bb_reg(dm, REG_OFDM_0_XA_AGC_CORE1, 0x7f, initial_gain);
+
+	/* @IQK Single tone start */
+	odm_set_bb_reg(dm, REG_FPGA0_IQK, 0xffffff00, 0x808000);
+	odm_set_bb_reg(dm, REG_IQK_AGC_PTS, MASKDWORD, 0xf9000000);
+	odm_set_bb_reg(dm, REG_IQK_AGC_PTS, MASKDWORD, 0xf8000000);
+
+	ODM_delay_us(10000);
+
+	/* PSD report of antenna A */
+	PSD_report_tmp = 0x0;
+	for (n = 0; n < 2; n++) {
+		PSD_report_tmp = phydm_get_psd_data(dm, 14, initial_gain);
+		if (PSD_report_tmp > ant_a_report)
+			ant_a_report = PSD_report_tmp;
+	}
+
+	/* @change to Antenna B */
+	if (dm->support_ic_type & ODM_RTL8723B) {
+#if 0
+		/* odm_set_bb_reg(dm, REG_DPDT_CONTROL, 0x3, 0x2); */
+#endif
+		odm_set_bb_reg(dm, REG_S0_S1_PATH_SWITCH, 0xfff, 0x280);
+		odm_set_bb_reg(dm, REG_AGC_TABLE_SELECT, BIT(31), 0x1);
+	}
+
+	ODM_delay_us(10);
+
+	/* PSD report of antenna B */
+	PSD_report_tmp = 0x0;
+	for (n = 0; n < 2; n++) {
+		PSD_report_tmp = phydm_get_psd_data(dm, 14, initial_gain);
+		if (PSD_report_tmp > ant_b_report)
+			ant_b_report = PSD_report_tmp;
+	}
+
+	/* @Close IQK Single Tone function */
+	odm_set_bb_reg(dm, REG_FPGA0_IQK, 0xffffff00, 0x000000);
+
+	/* @1 Return to antanna A */
+	if (dm->support_ic_type & ODM_RTL8723B) {
+		/* @external DPDT */
+		odm_set_bb_reg(dm, REG_DPDT_CONTROL, MASKDWORD, reg92c);
+
+		/* @internal S0/S1 */
+		odm_set_bb_reg(dm, REG_S0_S1_PATH_SWITCH, MASKDWORD, reg948);
+		odm_set_bb_reg(dm, REG_AGC_TABLE_SELECT, MASKDWORD, regb2c);
+		odm_set_bb_reg(dm, rfe_ctrl_anta_src, MASKDWORD, reg930);
+		odm_set_mac_reg(dm, REG_SYM_WLBT_PAPE_SEL, BIT(29), reg064);
+	}
+
+	odm_set_bb_reg(dm, REG_FPGA0_ANALOG_PARAMETER4, MASKDWORD, reg88c);
+	odm_set_bb_reg(dm, REG_OFDM_0_TR_MUX_PAR, MASKDWORD, regc08);
+	odm_set_bb_reg(dm, REG_FPGA0_XCD_RF_INTERFACE_SW, MASKDWORD, reg874);
+	odm_set_bb_reg(dm, REG_OFDM_0_XA_AGC_CORE1, 0x7F, 0x40);
+	odm_set_bb_reg(dm, REG_OFDM_0_XA_AGC_CORE1, MASKDWORD, regc50);
+	odm_set_rf_reg(dm, RF_PATH_A, RF_CHNLBW, RFREGOFFSETMASK, current_channel);
+	odm_set_rf_reg(dm, RF_PATH_A, RF_0x00, RFREGOFFSETMASK, rf_loop_reg);
+
+	/* Reload AFE Registers */
+	if (dm->support_ic_type & ODM_RTL8723B)
+		odm_set_bb_reg(dm, REG_RX_WAIT_CCA, MASKDWORD, afe_rrx_wait_cca);
+
+	if (dm->support_ic_type & ODM_RTL8723B) {
+		PHYDM_DBG(dm, DBG_ANT_DIV, "psd_report_A[%d]= %d\n", 2416,
+			  ant_a_report);
+		PHYDM_DBG(dm, DBG_ANT_DIV, "psd_report_B[%d]= %d\n", 2416,
+			  ant_b_report);
+
+		/* @2 Test ant B based on ant A is ON */
+		if (ant_a_report >= 100 && ant_b_report >= 100 && ant_a_report <= 135 && ant_b_report <= 135) {
+			u8 TH1 = 2, TH2 = 6;
+
+			if ((ant_a_report - ant_b_report < TH1) || (ant_b_report - ant_a_report < TH1)) {
+				dm_swat_table->ANTA_ON = true;
+				dm_swat_table->ANTB_ON = true;
+				PHYDM_DBG(dm, DBG_ANT_DIV, "%s: Dual Antenna\n",
+					  __func__);
+			} else if (((ant_a_report - ant_b_report >= TH1) && (ant_a_report - ant_b_report <= TH2)) ||
+				   ((ant_b_report - ant_a_report >= TH1) && (ant_b_report - ant_a_report <= TH2))) {
+				dm_swat_table->ANTA_ON = false;
+				dm_swat_table->ANTB_ON = false;
+				is_result = false;
+				PHYDM_DBG(dm, DBG_ANT_DIV,
+					  "%s: Need to check again\n",
+					  __func__);
+			} else {
+				dm_swat_table->ANTA_ON = true;
+				dm_swat_table->ANTB_ON = false;
+				PHYDM_DBG(dm, DBG_ANT_DIV,
+					  "%s: Single Antenna\n", __func__);
+			}
+			dm->ant_detected_info.is_ant_detected = true;
+			dm->ant_detected_info.db_for_ant_a = ant_a_report;
+			dm->ant_detected_info.db_for_ant_b = ant_b_report;
+			dm->ant_detected_info.db_for_ant_o = ant_0_report;
+
+		} else {
+			PHYDM_DBG(dm, DBG_ANT_DIV, "return false!!\n");
+			is_result = false;
+		}
+	}
+	return is_result;
+}
+
+/* @1 [2. Scan AP RSSI method] ================================================== */
+
+boolean
+odm_sw_ant_div_check_before_link(
+	void *dm_void)
+{
+#if (RT_MEM_SIZE_LEVEL != RT_MEM_SIZE_MINIMUM)
+
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	void *adapter = dm->adapter;
+	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter));
+	//PMGNT_INFO		mgnt_info = &adapter->MgntInfo;
+	PMGNT_INFO mgnt_info = &(((PADAPTER)(adapter))->MgntInfo);
+	struct sw_antenna_switch *dm_swat_table = &dm->dm_swat_table;
+	struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
+	s8 score = 0;
+	PRT_WLAN_BSS p_tmp_bss_desc, p_test_bss_desc;
+	u8 power_target_L = 9, power_target_H = 16;
+	u8 tmp_power_diff = 0, power_diff = 0, avg_power_diff = 0, max_power_diff = 0, min_power_diff = 0xff;
+	u16 index, counter = 0;
+	static u8 scan_channel;
+	u32 tmp_swas_no_link_bk_reg948;
+
+	PHYDM_DBG(dm, DBG_ANT_DIV, "ANTA_ON = (( %d )) , ANTB_ON = (( %d ))\n",
+		  dm->dm_swat_table.ANTA_ON, dm->dm_swat_table.ANTB_ON);
+
+	/* @if(HP id) */
+	{
+		if (dm->dm_swat_table.rssi_ant_dect_result == true && dm->support_ic_type == ODM_RTL8723B) {
+			PHYDM_DBG(dm, DBG_ANT_DIV,
+				  "8723B RSSI-based Antenna Detection is done\n");
+			return false;
+		}
+
+		if (dm->support_ic_type == ODM_RTL8723B) {
+			if (dm_swat_table->swas_no_link_bk_reg948 == 0xff)
+				dm_swat_table->swas_no_link_bk_reg948 = odm_read_4byte(dm, REG_S0_S1_PATH_SWITCH);
+		}
+	}
+
+	if (dm->adapter == NULL) { /* @For BSOD when plug/unplug fast.  //By YJ,120413 */
+		/* The ODM structure is not initialized. */
+		return false;
+	}
+
+	/* Retrieve antenna detection registry info, added by Roger, 2012.11.27. */
+	if (!IS_ANT_DETECT_SUPPORT_RSSI(((PADAPTER)adapter)))
+		return false;
+	else
+		PHYDM_DBG(dm, DBG_ANT_DIV, "Antenna Detection: RSSI method\n");
+
+	/* Since driver is going to set BB register, it shall check if there is another thread controlling BB/RF. */
+	odm_acquire_spin_lock(dm, RT_RF_STATE_SPINLOCK);
+	if (hal_data->eRFPowerState != eRfOn || mgnt_info->RFChangeInProgress || mgnt_info->bMediaConnect) {
+		odm_release_spin_lock(dm, RT_RF_STATE_SPINLOCK);
+
+		PHYDM_DBG(dm, DBG_ANT_DIV,
+			  "%s: rf_change_in_progress(%x), e_rf_power_state(%x)\n",
+			  __func__, mgnt_info->RFChangeInProgress,
+			  hal_data->eRFPowerState);
+
+		dm_swat_table->swas_no_link_state = 0;
+
+		return false;
+	} else
+		odm_release_spin_lock(dm, RT_RF_STATE_SPINLOCK);
+	PHYDM_DBG(dm, DBG_ANT_DIV, "dm_swat_table->swas_no_link_state = %d\n",
+		  dm_swat_table->swas_no_link_state);
+	/* @1 Run AntDiv mechanism "Before Link" part. */
+	if (dm_swat_table->swas_no_link_state == 0) {
+		/* @1 Prepare to do Scan again to check current antenna state. */
+
+		/* Set check state to next step. */
+		dm_swat_table->swas_no_link_state = 1;
+
+		/* @Copy Current Scan list. */
+		mgnt_info->tmpNumBssDesc = mgnt_info->NumBssDesc;
+		PlatformMoveMemory((void *)mgnt_info->tmpbssDesc, (void *)mgnt_info->bssDesc, sizeof(RT_WLAN_BSS) * MAX_BSS_DESC);
+
+		/* @Go back to scan function again. */
+		PHYDM_DBG(dm, DBG_ANT_DIV, "%s: Scan one more time\n",
+			  __func__);
+		mgnt_info->ScanStep = 0;
+		mgnt_info->bScanAntDetect = true;
+		scan_channel = odm_sw_ant_div_select_scan_chnl(adapter);
+
+		if (dm->support_ic_type & (ODM_RTL8188E | ODM_RTL8821)) {
+			if (fat_tab->rx_idle_ant == MAIN_ANT)
+				odm_update_rx_idle_ant(dm, AUX_ANT);
+			else
+				odm_update_rx_idle_ant(dm, MAIN_ANT);
+			if (scan_channel == 0) {
+				PHYDM_DBG(dm, DBG_ANT_DIV,
+					  "%s: No AP List Avaiable, Using ant(%s)\n",
+					  __func__,
+					  (fat_tab->rx_idle_ant == MAIN_ANT) ?
+					  "AUX_ANT" : "MAIN_ANT");
+
+				if (IS_5G_WIRELESS_MODE(mgnt_info->dot11CurrentWirelessMode)) {
+					dm_swat_table->ant_5g = fat_tab->rx_idle_ant;
+					PHYDM_DBG(dm, DBG_ANT_DIV, "dm_swat_table->ant_5g=%s\n", (fat_tab->rx_idle_ant == MAIN_ANT) ? "MAIN_ANT" : "AUX_ANT");
+				} else {
+					dm_swat_table->ant_2g = fat_tab->rx_idle_ant;
+					PHYDM_DBG(dm, DBG_ANT_DIV, "dm_swat_table->ant_2g=%s\n", (fat_tab->rx_idle_ant == MAIN_ANT) ? "MAIN_ANT" : "AUX_ANT");
+				}
+				return false;
+			}
+
+			PHYDM_DBG(dm, DBG_ANT_DIV,
+				  "%s: Change to %s for testing.\n", __func__,
+				  ((fat_tab->rx_idle_ant == MAIN_ANT) ?
+				  "MAIN_ANT" : "AUX_ANT"));
+		} else if (dm->support_ic_type & (ODM_RTL8723B)) {
+			/*Switch Antenna to another one.*/
+
+			tmp_swas_no_link_bk_reg948 = odm_read_4byte(dm, REG_S0_S1_PATH_SWITCH);
+
+			if (dm_swat_table->cur_antenna == MAIN_ANT && tmp_swas_no_link_bk_reg948 == 0x200) {
+				odm_set_bb_reg(dm, REG_S0_S1_PATH_SWITCH, 0xfff, 0x280);
+				odm_set_bb_reg(dm, REG_AGC_TABLE_SELECT, BIT(31), 0x1);
+				dm_swat_table->cur_antenna = AUX_ANT;
+			} else {
+				PHYDM_DBG(dm, DBG_ANT_DIV,
+					  "Reg[948]= (( %x )) was in wrong state\n",
+					  tmp_swas_no_link_bk_reg948);
+				return false;
+			}
+			ODM_delay_us(10);
+
+			PHYDM_DBG(dm, DBG_ANT_DIV,
+				  "%s: Change to (( %s-ant))  for testing.\n",
+				  __func__,
+				  (dm_swat_table->cur_antenna == MAIN_ANT) ?
+				  "MAIN" : "AUX");
+		}
+
+		odm_sw_ant_div_construct_scan_chnl(adapter, scan_channel);
+		PlatformSetTimer(adapter, &mgnt_info->ScanTimer, 5);
+
+		return true;
+	} else { /* @dm_swat_table->swas_no_link_state == 1 */
+		/* @1 ScanComple() is called after antenna swiched. */
+		/* @1 Check scan result and determine which antenna is going */
+		/* @1 to be used. */
+
+		PHYDM_DBG(dm, DBG_ANT_DIV, " tmp_num_bss_desc= (( %d ))\n",
+			  mgnt_info->tmpNumBssDesc); /* @debug for Dino */
+
+		for (index = 0; index < mgnt_info->tmpNumBssDesc; index++) {
+			p_tmp_bss_desc = &mgnt_info->tmpbssDesc[index]; /* @Antenna 1 */
+			p_test_bss_desc = &mgnt_info->bssDesc[index]; /* @Antenna 2 */
+
+			if (PlatformCompareMemory(p_test_bss_desc->bdBssIdBuf, p_tmp_bss_desc->bdBssIdBuf, 6) != 0) {
+				PHYDM_DBG(dm, DBG_ANT_DIV,
+					  "%s: ERROR!! This shall not happen.\n",
+					  __func__);
+				continue;
+			}
+
+			if (dm->support_ic_type != ODM_RTL8723B) {
+				if (p_tmp_bss_desc->ChannelNumber == scan_channel) {
+					if (p_tmp_bss_desc->RecvSignalPower > p_test_bss_desc->RecvSignalPower) {
+						PHYDM_DBG(dm, DBG_ANT_DIV, "%s: Compare scan entry: score++\n", __func__);
+						RT_PRINT_STR(COMP_SCAN, DBG_WARNING, "GetScanInfo(): new Bss SSID:", p_tmp_bss_desc->bdSsIdBuf, p_tmp_bss_desc->bdSsIdLen);
+						PHYDM_DBG(dm, DBG_ANT_DIV, "at ch %d, Original: %d, Test: %d\n\n", p_tmp_bss_desc->ChannelNumber, p_tmp_bss_desc->RecvSignalPower, p_test_bss_desc->RecvSignalPower);
+
+						score++;
+						PlatformMoveMemory(p_test_bss_desc, p_tmp_bss_desc, sizeof(RT_WLAN_BSS));
+					} else if (p_tmp_bss_desc->RecvSignalPower < p_test_bss_desc->RecvSignalPower) {
+						PHYDM_DBG(dm, DBG_ANT_DIV, "%s: Compare scan entry: score--\n", __func__);
+						RT_PRINT_STR(COMP_SCAN, DBG_WARNING, "GetScanInfo(): new Bss SSID:", p_tmp_bss_desc->bdSsIdBuf, p_tmp_bss_desc->bdSsIdLen);
+						PHYDM_DBG(dm, DBG_ANT_DIV, "at ch %d, Original: %d, Test: %d\n\n", p_tmp_bss_desc->ChannelNumber, p_tmp_bss_desc->RecvSignalPower, p_test_bss_desc->RecvSignalPower);
+						score--;
+					} else {
+						if (p_test_bss_desc->bdTstamp - p_tmp_bss_desc->bdTstamp < 5000) {
+							RT_PRINT_STR(COMP_SCAN, DBG_WARNING, "GetScanInfo(): new Bss SSID:", p_tmp_bss_desc->bdSsIdBuf, p_tmp_bss_desc->bdSsIdLen);
+							PHYDM_DBG(dm, DBG_ANT_DIV, "at ch %d, Original: %d, Test: %d\n", p_tmp_bss_desc->ChannelNumber, p_tmp_bss_desc->RecvSignalPower, p_test_bss_desc->RecvSignalPower);
+							PHYDM_DBG(dm, DBG_ANT_DIV, "The 2nd Antenna didn't get this AP\n\n");
+						}
+					}
+				}
+			} else { /* @8723B */
+				if (p_tmp_bss_desc->ChannelNumber == scan_channel) {
+					PHYDM_DBG(dm, DBG_ANT_DIV, "channel_number == scan_channel->(( %d ))\n", p_tmp_bss_desc->ChannelNumber);
+
+					if (p_tmp_bss_desc->RecvSignalPower > p_test_bss_desc->RecvSignalPower) { /* Pow(Ant1) > Pow(Ant2) */
+						counter++;
+						tmp_power_diff = (u8)(p_tmp_bss_desc->RecvSignalPower - p_test_bss_desc->RecvSignalPower);
+						power_diff = power_diff + tmp_power_diff;
+
+						PHYDM_DBG(dm, DBG_ANT_DIV, "Original: %d, Test: %d\n", p_tmp_bss_desc->RecvSignalPower, p_test_bss_desc->RecvSignalPower);
+						PHYDM_PRINT_ADDR(dm, DBG_ANT_DIV, "SSID:", p_tmp_bss_desc->bdSsIdBuf);
+						PHYDM_PRINT_ADDR(dm, DBG_ANT_DIV, "BSSID:", p_tmp_bss_desc->bdSsIdBuf);
+
+#if 0
+						/* PHYDM_DBG(dm,DBG_ANT_DIV, "tmp_power_diff: (( %d)),max_power_diff: (( %d)),min_power_diff: (( %d))\n", tmp_power_diff,max_power_diff,min_power_diff); */
+#endif
+						if (tmp_power_diff > max_power_diff)
+							max_power_diff = tmp_power_diff;
+						if (tmp_power_diff < min_power_diff)
+							min_power_diff = tmp_power_diff;
+#if 0
+						/* PHYDM_DBG(dm,DBG_ANT_DIV, "max_power_diff: (( %d)),min_power_diff: (( %d))\n",max_power_diff,min_power_diff); */
+#endif
+
+						PlatformMoveMemory(p_test_bss_desc, p_tmp_bss_desc, sizeof(RT_WLAN_BSS));
+					} else if (p_test_bss_desc->RecvSignalPower > p_tmp_bss_desc->RecvSignalPower) { /* Pow(Ant1) < Pow(Ant2) */
+						counter++;
+						tmp_power_diff = (u8)(p_test_bss_desc->RecvSignalPower - p_tmp_bss_desc->RecvSignalPower);
+						power_diff = power_diff + tmp_power_diff;
+						PHYDM_DBG(dm, DBG_ANT_DIV, "Original: %d, Test: %d\n", p_tmp_bss_desc->RecvSignalPower, p_test_bss_desc->RecvSignalPower);
+						PHYDM_PRINT_ADDR(dm, DBG_ANT_DIV, "SSID:", p_tmp_bss_desc->bdSsIdBuf);
+						PHYDM_PRINT_ADDR(dm, DBG_ANT_DIV, "BSSID:", p_tmp_bss_desc->bdSsIdBuf);
+						if (tmp_power_diff > max_power_diff)
+							max_power_diff = tmp_power_diff;
+						if (tmp_power_diff < min_power_diff)
+							min_power_diff = tmp_power_diff;
+					} else { /* Pow(Ant1) = Pow(Ant2) */
+						if (p_test_bss_desc->bdTstamp > p_tmp_bss_desc->bdTstamp) { /* Stamp(Ant1) < Stamp(Ant2) */
+							PHYDM_DBG(dm, DBG_ANT_DIV, "time_diff: %lld\n", (p_test_bss_desc->bdTstamp - p_tmp_bss_desc->bdTstamp) / 1000);
+							if (p_test_bss_desc->bdTstamp - p_tmp_bss_desc->bdTstamp > 5000) {
+								counter++;
+								PHYDM_DBG(dm, DBG_ANT_DIV, "Original: %d, Test: %d\n", p_tmp_bss_desc->RecvSignalPower, p_test_bss_desc->RecvSignalPower);
+								PHYDM_PRINT_ADDR(dm, DBG_ANT_DIV, "SSID:", p_tmp_bss_desc->bdSsIdBuf);
+								PHYDM_PRINT_ADDR(dm, DBG_ANT_DIV, "BSSID:", p_tmp_bss_desc->bdSsIdBuf);
+								min_power_diff = 0;
+							}
+						} else
+							PHYDM_DBG(dm, DBG_ANT_DIV, "[Error !!!]: Time_diff: %lld\n", (p_test_bss_desc->bdTstamp - p_tmp_bss_desc->bdTstamp) / 1000);
+					}
+				}
+			}
+		}
+
+		if (dm->support_ic_type & (ODM_RTL8188E | ODM_RTL8821)) {
+			if (mgnt_info->NumBssDesc != 0 && score < 0) {
+				PHYDM_DBG(dm, DBG_ANT_DIV,
+					  "%s: Using ant(%s)\n", __func__,
+					  (fat_tab->rx_idle_ant == MAIN_ANT) ?
+					  "MAIN_ANT" : "AUX_ANT");
+			} else {
+				PHYDM_DBG(dm, DBG_ANT_DIV,
+					  "%s: Remain ant(%s)\n", __func__,
+					  (fat_tab->rx_idle_ant == MAIN_ANT) ?
+					  "AUX_ANT" : "MAIN_ANT");
+
+				if (fat_tab->rx_idle_ant == MAIN_ANT)
+					odm_update_rx_idle_ant(dm, AUX_ANT);
+				else
+					odm_update_rx_idle_ant(dm, MAIN_ANT);
+			}
+
+			if (IS_5G_WIRELESS_MODE(mgnt_info->dot11CurrentWirelessMode)) {
+				dm_swat_table->ant_5g = fat_tab->rx_idle_ant;
+				PHYDM_DBG(dm, DBG_ANT_DIV,
+					  "dm_swat_table->ant_5g=%s\n",
+					  (fat_tab->rx_idle_ant == MAIN_ANT) ?
+					  "MAIN_ANT" : "AUX_ANT");
+			} else {
+				dm_swat_table->ant_2g = fat_tab->rx_idle_ant;
+				PHYDM_DBG(dm, DBG_ANT_DIV,
+					  "dm_swat_table->ant_2g=%s\n",
+					  (fat_tab->rx_idle_ant == MAIN_ANT) ?
+					  "MAIN_ANT" : "AUX_ANT");
+			}
+		} else if (dm->support_ic_type == ODM_RTL8723B) {
+			if (counter == 0) {
+				if (dm->dm_swat_table.pre_aux_fail_detec == false) {
+					dm->dm_swat_table.pre_aux_fail_detec = true;
+					dm->dm_swat_table.rssi_ant_dect_result = false;
+					PHYDM_DBG(dm, DBG_ANT_DIV, "counter=(( 0 )) , [[ Cannot find any AP with Aux-ant ]] ->  Scan Target-channel again\n");
+
+					/* @3 [ Scan again ] */
+					odm_sw_ant_div_construct_scan_chnl(adapter, scan_channel);
+					PlatformSetTimer(adapter, &mgnt_info->ScanTimer, 5);
+					return true;
+				} else { /* pre_aux_fail_detec == true */
+					/* @2 [ Single Antenna ] */
+					dm->dm_swat_table.pre_aux_fail_detec = false;
+					dm->dm_swat_table.rssi_ant_dect_result = true;
+					PHYDM_DBG(dm, DBG_ANT_DIV, "counter=(( 0 )) , [[  Still cannot find any AP ]]\n");
+					PHYDM_DBG(dm, DBG_ANT_DIV, "%s: Single antenna\n", __func__);
+				}
+				dm->dm_swat_table.aux_fail_detec_counter++;
+			} else {
+				dm->dm_swat_table.pre_aux_fail_detec = false;
+
+				if (counter == 3) {
+					avg_power_diff = ((power_diff - max_power_diff - min_power_diff) >> 1) + ((max_power_diff + min_power_diff) >> 2);
+					PHYDM_DBG(dm, DBG_ANT_DIV, "counter: (( %d )) ,  power_diff: (( %d ))\n", counter, power_diff);
+					PHYDM_DBG(dm, DBG_ANT_DIV, "[ counter==3 ] Modified avg_power_diff: (( %d )) , max_power_diff: (( %d )) ,  min_power_diff: (( %d ))\n", avg_power_diff, max_power_diff, min_power_diff);
+				} else if (counter >= 4) {
+					avg_power_diff = (power_diff - max_power_diff - min_power_diff) / (counter - 2);
+					PHYDM_DBG(dm, DBG_ANT_DIV, "counter: (( %d )) ,  power_diff: (( %d ))\n", counter, power_diff);
+					PHYDM_DBG(dm, DBG_ANT_DIV, "[ counter>=4 ] Modified avg_power_diff: (( %d )) , max_power_diff: (( %d )) ,  min_power_diff: (( %d ))\n", avg_power_diff, max_power_diff, min_power_diff);
+
+				} else { /* @counter==1,2 */
+					avg_power_diff = power_diff / counter;
+					PHYDM_DBG(dm, DBG_ANT_DIV, "avg_power_diff: (( %d )) , counter: (( %d )) ,  power_diff: (( %d ))\n", avg_power_diff, counter, power_diff);
+				}
+
+				/* @2 [ Retry ] */
+				if (avg_power_diff >= power_target_L && avg_power_diff <= power_target_H) {
+					dm->dm_swat_table.retry_counter++;
+
+					if (dm->dm_swat_table.retry_counter <= 3) {
+						dm->dm_swat_table.rssi_ant_dect_result = false;
+						PHYDM_DBG(dm, DBG_ANT_DIV, "[[ Low confidence result ]] avg_power_diff= (( %d ))  ->  Scan Target-channel again ]]\n", avg_power_diff);
+
+						/* @3 [ Scan again ] */
+						odm_sw_ant_div_construct_scan_chnl(adapter, scan_channel);
+						PlatformSetTimer(adapter, &mgnt_info->ScanTimer, 5);
+						return true;
+					} else {
+						dm->dm_swat_table.rssi_ant_dect_result = true;
+						PHYDM_DBG(dm, DBG_ANT_DIV, "[[ Still Low confidence result ]]  (( retry_counter > 3 ))\n");
+						PHYDM_DBG(dm, DBG_ANT_DIV, "%s: Single antenna\n", __func__);
+					}
+				}
+				/* @2 [ Dual Antenna ] */
+				else if ((mgnt_info->NumBssDesc != 0) && (avg_power_diff < power_target_L)) {
+					dm->dm_swat_table.rssi_ant_dect_result = true;
+					if (dm->dm_swat_table.ANTB_ON == false) {
+						dm->dm_swat_table.ANTA_ON = true;
+						dm->dm_swat_table.ANTB_ON = true;
+					}
+					PHYDM_DBG(dm, DBG_ANT_DIV, "%s: Dual antenna\n", __func__);
+					dm->dm_swat_table.dual_ant_counter++;
+
+					/* set bt coexDM from 1ant coexDM to 2ant coexDM */
+					BT_SetBtCoexAntNum(adapter, BT_COEX_ANT_TYPE_DETECTED, 2);
+
+					/* @3 [ Init antenna diversity ] */
+					dm->support_ability |= ODM_BB_ANT_DIV;
+					odm_ant_div_init(dm);
+				}
+				/* @2 [ Single Antenna ] */
+				else if (avg_power_diff > power_target_H) {
+					dm->dm_swat_table.rssi_ant_dect_result = true;
+					if (dm->dm_swat_table.ANTB_ON == true) {
+						dm->dm_swat_table.ANTA_ON = true;
+						dm->dm_swat_table.ANTB_ON = false;
+#if 0
+						/* @bt_set_bt_coex_ant_num(adapter, BT_COEX_ANT_TYPE_DETECTED, 1); */
+#endif
+					}
+					PHYDM_DBG(dm, DBG_ANT_DIV, "%s: Single antenna\n", __func__);
+					dm->dm_swat_table.single_ant_counter++;
+				}
+			}
+#if 0
+			/* PHYDM_DBG(dm,DBG_ANT_DIV, "is_result=(( %d ))\n",dm->dm_swat_table.rssi_ant_dect_result); */
+#endif
+			PHYDM_DBG(dm, DBG_ANT_DIV,
+				  "dual_ant_counter = (( %d )), single_ant_counter = (( %d )) , retry_counter = (( %d )) , aux_fail_detec_counter = (( %d ))\n\n\n",
+				  dm->dm_swat_table.dual_ant_counter,
+				  dm->dm_swat_table.single_ant_counter,
+				  dm->dm_swat_table.retry_counter,
+				  dm->dm_swat_table.aux_fail_detec_counter);
+
+			/* @2 recover the antenna setting */
+
+			if (dm->dm_swat_table.ANTB_ON == false)
+				odm_set_bb_reg(dm, REG_S0_S1_PATH_SWITCH, 0xfff, (dm_swat_table->swas_no_link_bk_reg948));
+
+			PHYDM_DBG(dm, DBG_ANT_DIV,
+				  "is_result=(( %d )), Recover  Reg[948]= (( %x ))\n\n",
+				  dm->dm_swat_table.rssi_ant_dect_result,
+				  dm_swat_table->swas_no_link_bk_reg948);
+		}
+
+		/* @Check state reset to default and wait for next time. */
+		dm_swat_table->swas_no_link_state = 0;
+		mgnt_info->bScanAntDetect = false;
+
+		return false;
+	}
+
+#else
+	return false;
+#endif
+
+	return false;
+}
+
+/* @1 [3. PSD method] ========================================================== */
+void odm_single_dual_antenna_detection_psd(
+	void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	u32 channel_ori;
+	u8 initial_gain = 0x36;
+	u8 tone_idx;
+	u8 tone_lenth_1 = 7, tone_lenth_2 = 4;
+	u16 tone_idx_1[7] = {88, 104, 120, 8, 24, 40, 56};
+	u16 tone_idx_2[4] = {8, 24, 40, 56};
+	u32 psd_report_main[11] = {0}, psd_report_aux[11] = {0};
+	/* u8	tone_lenth_1=4, tone_lenth_2=2; */
+	/* u16	tone_idx_1[4]={88, 120, 24, 56}; */
+	/* u16	tone_idx_2[2]={ 24,  56}; */
+	/* u32	psd_report_main[6]={0}, psd_report_aux[6]={0}; */
+
+	u32 PSD_report_temp, max_psd_report_main = 0, max_psd_report_aux = 0;
+	u32 PSD_power_threshold;
+	u32 main_psd_result = 0, aux_psd_result = 0;
+	u32 regc50, reg948, regb2c, regc14, reg908;
+	u32 i = 0, test_num = 8;
+
+	if (dm->support_ic_type != ODM_RTL8723B)
+		return;
+
+	PHYDM_DBG(dm, DBG_ANT_DIV, "%s============>\n", __func__);
+
+	/* @2 [ Backup Current RF/BB Settings ] */
+
+	channel_ori = odm_get_rf_reg(dm, RF_PATH_A, ODM_CHANNEL, RFREGOFFSETMASK);
+	reg948 = odm_get_bb_reg(dm, REG_S0_S1_PATH_SWITCH, MASKDWORD);
+	regb2c = odm_get_bb_reg(dm, REG_AGC_TABLE_SELECT, MASKDWORD);
+	regc50 = odm_get_bb_reg(dm, REG_OFDM_0_XA_AGC_CORE1, MASKDWORD);
+	regc14 = odm_get_bb_reg(dm, R_0xc14, MASKDWORD);
+	reg908 = odm_get_bb_reg(dm, R_0x908, MASKDWORD);
+
+	/* @2 [ setting for doing PSD function (CH4)] */
+	odm_set_bb_reg(dm, REG_FPGA0_RFMOD, BIT(24), 0); /* @disable whole CCK block */
+	odm_write_1byte(dm, REG_TXPAUSE, 0xFF); /* Turn off TX  ->  Pause TX Queue */
+	odm_set_bb_reg(dm, R_0xc14, MASKDWORD, 0x0); /* @[ Set IQK Matrix = 0 ] equivalent to [ Turn off CCA] */
+
+	/* PHYTXON while loop */
+	odm_set_bb_reg(dm, R_0x908, MASKDWORD, 0x803);
+	while (odm_get_bb_reg(dm, R_0xdf4, BIT(6))) {
+		i++;
+		if (i > 1000000) {
+			PHYDM_DBG(dm, DBG_ANT_DIV,
+				  "Wait in %s() more than %d times!\n",
+				  __FUNCTION__, i);
+			break;
+		}
+	}
+
+	odm_set_bb_reg(dm, R_0xc50, 0x7f, initial_gain);
+	odm_set_rf_reg(dm, RF_PATH_A, ODM_CHANNEL, 0x7ff, 0x04); /* Set RF to CH4 & 40M */
+	odm_set_bb_reg(dm, REG_FPGA0_ANALOG_PARAMETER4, 0xf00000, 0xf); /* @3 wire Disable    88c[23:20]=0xf */
+	odm_set_bb_reg(dm, REG_FPGA0_PSD_FUNCTION, BIT(14) | BIT15, 0x0); /* 128 pt	 */ /* Set PSD 128 ptss */
+	ODM_delay_us(3000);
+
+	/* @2 [ Doing PSD Function in (CH4)] */
+
+	/* @Antenna A */
+	PHYDM_DBG(dm, DBG_ANT_DIV, "Switch to Main-ant   (CH4)\n");
+	odm_set_bb_reg(dm, R_0x948, 0xfff, 0x200);
+	ODM_delay_us(10);
+	PHYDM_DBG(dm, DBG_ANT_DIV, "dbg\n");
+	for (i = 0; i < test_num; i++) {
+		for (tone_idx = 0; tone_idx < tone_lenth_1; tone_idx++) {
+			PSD_report_temp = phydm_get_psd_data(dm, tone_idx_1[tone_idx], initial_gain);
+			/* @if(  PSD_report_temp>psd_report_main[tone_idx]  ) */
+			psd_report_main[tone_idx] += PSD_report_temp;
+		}
+	}
+	/* @Antenna B */
+	PHYDM_DBG(dm, DBG_ANT_DIV, "Switch to Aux-ant   (CH4)\n");
+	odm_set_bb_reg(dm, R_0x948, 0xfff, 0x280);
+	ODM_delay_us(10);
+	for (i = 0; i < test_num; i++) {
+		for (tone_idx = 0; tone_idx < tone_lenth_1; tone_idx++) {
+			PSD_report_temp = phydm_get_psd_data(dm, tone_idx_1[tone_idx], initial_gain);
+			/* @if(  PSD_report_temp>psd_report_aux[tone_idx]  ) */
+			psd_report_aux[tone_idx] += PSD_report_temp;
+		}
+	}
+	/* @2 [ Doing PSD Function in (CH8)] */
+
+	odm_set_bb_reg(dm, REG_FPGA0_ANALOG_PARAMETER4, 0xf00000, 0x0); /* @3 wire enable    88c[23:20]=0x0 */
+	ODM_delay_us(3000);
+
+	odm_set_bb_reg(dm, R_0xc50, 0x7f, initial_gain);
+	odm_set_rf_reg(dm, RF_PATH_A, ODM_CHANNEL, 0x7ff, 0x04); /* Set RF to CH8 & 40M */
+
+	odm_set_bb_reg(dm, REG_FPGA0_ANALOG_PARAMETER4, 0xf00000, 0xf); /* @3 wire Disable    88c[23:20]=0xf */
+	ODM_delay_us(3000);
+
+	/* @Antenna A */
+	PHYDM_DBG(dm, DBG_ANT_DIV, "Switch to Main-ant   (CH8)\n");
+	odm_set_bb_reg(dm, R_0x948, 0xfff, 0x200);
+	ODM_delay_us(10);
+
+	for (i = 0; i < test_num; i++) {
+		for (tone_idx = 0; tone_idx < tone_lenth_2; tone_idx++) {
+			PSD_report_temp = phydm_get_psd_data(dm, tone_idx_2[tone_idx], initial_gain);
+			/* @if(  PSD_report_temp>psd_report_main[tone_idx]  ) */
+			psd_report_main[tone_lenth_1 + tone_idx] += PSD_report_temp;
+		}
+	}
+
+	/* @Antenna B */
+	PHYDM_DBG(dm, DBG_ANT_DIV, "Switch to Aux-ant   (CH8)\n");
+	odm_set_bb_reg(dm, R_0x948, 0xfff, 0x280);
+	ODM_delay_us(10);
+
+	for (i = 0; i < test_num; i++) {
+		for (tone_idx = 0; tone_idx < tone_lenth_2; tone_idx++) {
+			PSD_report_temp = phydm_get_psd_data(dm, tone_idx_2[tone_idx], initial_gain);
+			/* @if(  PSD_report_temp>psd_report_aux[tone_idx]  ) */
+			psd_report_aux[tone_lenth_1 + tone_idx] += PSD_report_temp;
+		}
+	}
+
+	/* @2 [ Calculate Result ] */
+
+	PHYDM_DBG(dm, DBG_ANT_DIV, "\nMain PSD Result: (ALL)\n");
+	for (tone_idx = 0; tone_idx < (tone_lenth_1 + tone_lenth_2); tone_idx++) {
+		PHYDM_DBG(dm, DBG_ANT_DIV, "[Tone-%d]: %d,\n", (tone_idx + 1),
+			  psd_report_main[tone_idx]);
+		main_psd_result += psd_report_main[tone_idx];
+		if (psd_report_main[tone_idx] > max_psd_report_main)
+			max_psd_report_main = psd_report_main[tone_idx];
+	}
+	PHYDM_DBG(dm, DBG_ANT_DIV,
+		  "--------------------------- \nTotal_Main= (( %d ))\n",
+		  main_psd_result);
+	PHYDM_DBG(dm, DBG_ANT_DIV, "MAX_Main = (( %d ))\n",
+		  max_psd_report_main);
+
+	PHYDM_DBG(dm, DBG_ANT_DIV, "\nAux PSD Result: (ALL)\n");
+	for (tone_idx = 0; tone_idx < (tone_lenth_1 + tone_lenth_2); tone_idx++) {
+		PHYDM_DBG(dm, DBG_ANT_DIV, "[Tone-%d]: %d,\n", (tone_idx + 1),
+			  psd_report_aux[tone_idx]);
+		aux_psd_result += psd_report_aux[tone_idx];
+		if (psd_report_aux[tone_idx] > max_psd_report_aux)
+			max_psd_report_aux = psd_report_aux[tone_idx];
+	}
+	PHYDM_DBG(dm, DBG_ANT_DIV,
+		  "--------------------------- \nTotal_Aux= (( %d ))\n",
+		  aux_psd_result);
+	PHYDM_DBG(dm, DBG_ANT_DIV, "MAX_Aux = (( %d ))\n\n",
+		  max_psd_report_aux);
+
+	/* @main_psd_result=main_psd_result-max_psd_report_main; */
+	/* @aux_psd_result=aux_psd_result-max_psd_report_aux; */
+	PSD_power_threshold = (main_psd_result * 7) >> 3;
+
+	PHYDM_DBG(dm, DBG_ANT_DIV,
+		  "[ Main_result, Aux_result ] = [ %d , %d ], PSD_power_threshold=(( %d ))\n",
+		  main_psd_result, aux_psd_result, PSD_power_threshold);
+
+	/* @3 [ Dual Antenna ] */
+	if (aux_psd_result >= PSD_power_threshold) {
+		if (dm->dm_swat_table.ANTB_ON == false) {
+			dm->dm_swat_table.ANTA_ON = true;
+			dm->dm_swat_table.ANTB_ON = true;
+		}
+		PHYDM_DBG(dm, DBG_ANT_DIV,
+			  "odm_sw_ant_div_check_before_link(): Dual antenna\n");
+
+#if 0
+		/* set bt coexDM from 1ant coexDM to 2ant coexDM */
+		/* @bt_set_bt_coex_ant_num(adapter, BT_COEX_ANT_TYPE_DETECTED, 2); */
+#endif
+
+		/* @Init antenna diversity */
+		dm->support_ability |= ODM_BB_ANT_DIV;
+		odm_ant_div_init(dm);
+	}
+	/* @3 [ Single Antenna ] */
+	else {
+		if (dm->dm_swat_table.ANTB_ON == true) {
+			dm->dm_swat_table.ANTA_ON = true;
+			dm->dm_swat_table.ANTB_ON = false;
+		}
+		PHYDM_DBG(dm, DBG_ANT_DIV,
+			  "odm_sw_ant_div_check_before_link(): Single antenna\n");
+	}
+
+	/* @2 [ Recover all parameters ] */
+
+	odm_set_rf_reg(dm, RF_PATH_A, RF_CHNLBW, RFREGOFFSETMASK, channel_ori);
+	odm_set_bb_reg(dm, REG_FPGA0_ANALOG_PARAMETER4, 0xf00000, 0x0); /* @3 wire enable    88c[23:20]=0x0 */
+	odm_set_bb_reg(dm, R_0xc50, 0x7f, regc50);
+
+	odm_set_bb_reg(dm, REG_S0_S1_PATH_SWITCH, MASKDWORD, reg948);
+	odm_set_bb_reg(dm, REG_AGC_TABLE_SELECT, MASKDWORD, regb2c);
+
+	odm_set_bb_reg(dm, REG_FPGA0_RFMOD, BIT(24), 1); /* @enable whole CCK block */
+	odm_write_1byte(dm, REG_TXPAUSE, 0x0); /* Turn on TX	 */ /* Resume TX Queue */
+	odm_set_bb_reg(dm, R_0xc14, MASKDWORD, regc14); /* @[ Set IQK Matrix = 0 ] equivalent to [ Turn on CCA] */
+	odm_set_bb_reg(dm, R_0x908, MASKDWORD, reg908);
+
+	return;
+}
+
+void odm_sw_ant_detect_init(void *dm_void)
+{
+#if (RTL8723B_SUPPORT == 1)
+
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct sw_antenna_switch *dm_swat_table = &dm->dm_swat_table;
+
+	if (dm->support_ic_type != ODM_RTL8723B)
+		return;
+
+	/* @dm_swat_table->pre_antenna = MAIN_ANT; */
+	/* @dm_swat_table->cur_antenna = MAIN_ANT; */
+	dm_swat_table->swas_no_link_state = 0;
+	dm_swat_table->pre_aux_fail_detec = false;
+	dm_swat_table->swas_no_link_bk_reg948 = 0xff;
+
+#ifdef CONFIG_PSD_TOOL
+	phydm_psd_init(dm);
+#endif
+#endif
+}
+#endif
+
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/phydm_antdect.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/phydm_antdect.h
--- linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/phydm_antdect.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/phydm_antdect.h	2020-04-10 16:35:06.822660348 +0300
@@ -0,0 +1,78 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017  Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * The full GNU General Public License is included in this distribution in the
+ * file called LICENSE.
+ *
+ * Contact Information:
+ * wlanfae <wlanfae@realtek.com>
+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
+ * Hsinchu 300, Taiwan.
+ *
+ * Larry Finger <Larry.Finger@lwfinger.net>
+ *
+ *****************************************************************************/
+
+#ifndef __PHYDMANTDECT_H__
+#define __PHYDMANTDECT_H__
+
+#define ANTDECT_VERSION "2.1"
+
+#if (defined(CONFIG_ANT_DETECTION))
+/* @#if( DM_ODM_SUPPORT_TYPE & (ODM_WIN |ODM_CE)) */
+/* @ANT Test */
+#define ANTTESTALL 0x00 /*@ant A or B will be Testing*/
+#define ANTTESTA 0x01 /*@ant A will be Testing*/
+#define ANTTESTB 0x02 /*@ant B will be testing*/
+
+#define MAX_ANTENNA_DETECTION_CNT 10
+
+struct _ANT_DETECTED_INFO {
+	boolean is_ant_detected;
+	u32 db_for_ant_a;
+	u32 db_for_ant_b;
+	u32 db_for_ant_o;
+};
+
+enum dm_swas {
+	antenna_a = 1,
+	antenna_b = 2,
+	antenna_max = 3,
+};
+
+/* @1 [1. Single Tone method] =================================================== */
+
+void odm_single_dual_antenna_default_setting(
+	void *dm_void);
+
+boolean
+odm_single_dual_antenna_detection(
+	void *dm_void,
+	u8 mode);
+
+/* @1 [2. Scan AP RSSI method] ================================================== */
+
+#define sw_ant_div_check_before_link odm_sw_ant_div_check_before_link
+
+boolean
+odm_sw_ant_div_check_before_link(
+	void *dm_void);
+
+/* @1 [3. PSD method] ========================================================== */
+
+void odm_single_dual_antenna_detection_psd(
+	void *dm_void);
+
+void odm_sw_ant_detect_init(void *dm_void);
+#endif
+#endif
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/phydm_antdiv.c linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/phydm_antdiv.c
--- linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/phydm_antdiv.c	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/phydm_antdiv.c	2020-04-10 16:35:06.823660394 +0300
@@ -0,0 +1,5433 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017  Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * The full GNU General Public License is included in this distribution in the
+ * file called LICENSE.
+ *
+ * Contact Information:
+ * wlanfae <wlanfae@realtek.com>
+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
+ * Hsinchu 300, Taiwan.
+ *
+ * Larry Finger <Larry.Finger@lwfinger.net>
+ *
+ *****************************************************************************/
+
+/*************************************************************
+ * include files
+ ************************************************************/
+
+#include "mp_precomp.h"
+#include "phydm_precomp.h"
+
+/*******************************************************
+ * when antenna test utility is on or some testing need to disable antenna diversity
+ * call this function to disable all ODM related mechanisms which will switch antenna.
+ *****************************************************
+ */
+#ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY
+void odm_stop_antenna_switch_dm(void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
+	/* @disable ODM antenna diversity */
+	dm->support_ability &= ~ODM_BB_ANT_DIV;
+	if (fat_tab->div_path_type == ANT_PATH_A)
+		odm_ant_div_on_off(dm, ANTDIV_OFF, ANT_PATH_A);
+	else if (fat_tab->div_path_type == ANT_PATH_B)
+		odm_ant_div_on_off(dm, ANTDIV_OFF, ANT_PATH_B);
+	else if (fat_tab->div_path_type == ANT_PATH_AB)
+		odm_ant_div_on_off(dm, ANTDIV_OFF, ANT_PATH_AB);
+	odm_tx_by_tx_desc_or_reg(dm, TX_BY_REG);
+	PHYDM_DBG(dm, DBG_ANT_DIV, "STOP Antenna Diversity\n");
+}
+
+void phydm_enable_antenna_diversity(void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+
+	dm->support_ability |= ODM_BB_ANT_DIV;
+	dm->antdiv_select = 0;
+	PHYDM_DBG(dm, DBG_ANT_DIV, "AntDiv is enabled & Re-Init AntDiv\n");
+	odm_antenna_diversity_init(dm);
+}
+
+void odm_set_ant_config(void *dm_void, u8 ant_setting /* @0=A, 1=B, 2=C, .... */)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+
+	if (dm->support_ic_type == ODM_RTL8723B) {
+		if (ant_setting == 0) /* @ant A*/
+			odm_set_bb_reg(dm, R_0x948, MASKDWORD, 0x00000000);
+		else if (ant_setting == 1)
+			odm_set_bb_reg(dm, R_0x948, MASKDWORD, 0x00000280);
+	} else if (dm->support_ic_type == ODM_RTL8723D) {
+		if (ant_setting == 0) /* @ant A*/
+			odm_set_bb_reg(dm, R_0x948, MASKLWORD, 0x0000);
+		else if (ant_setting == 1)
+			odm_set_bb_reg(dm, R_0x948, MASKLWORD, 0x0280);
+	}
+}
+
+/* ****************************************************** */
+
+void odm_sw_ant_div_rest_after_link(void *dm_void)
+{
+#if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY))
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct sw_antenna_switch *dm_swat_table = &dm->dm_swat_table;
+	struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
+	u32 i;
+
+	if (dm->ant_div_type == S0S1_SW_ANTDIV) {
+		dm_swat_table->try_flag = SWAW_STEP_INIT;
+		dm_swat_table->rssi_trying = 0;
+		dm_swat_table->double_chk_flag = 0;
+		fat_tab->rx_idle_ant = MAIN_ANT;
+
+		for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++)
+			phydm_antdiv_reset_statistic(dm, i);
+	}
+
+#endif
+}
+
+void phydm_n_on_off(void *dm_void, u8 swch, u8 path)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
+
+	if (path == ANT_PATH_A) {
+		odm_set_bb_reg(dm, R_0xc50, BIT(7), swch);
+	} else if (path == ANT_PATH_B) {
+		odm_set_bb_reg(dm, R_0xc58, BIT(7), swch);
+	} else if (path == ANT_PATH_AB) {
+		odm_set_bb_reg(dm, R_0xc50, BIT(7), swch);
+		odm_set_bb_reg(dm, R_0xc58, BIT(7), swch);
+	}
+	odm_set_bb_reg(dm, R_0xa00, BIT(15), swch);
+#if (RTL8723D_SUPPORT == 1)
+	/*@Mingzhi 2017-05-08*/
+	if (dm->support_ic_type == ODM_RTL8723D) {
+		if (swch == ANTDIV_ON) {
+			odm_set_bb_reg(dm, R_0xce0, BIT(1), 1);
+			odm_set_bb_reg(dm, R_0x948, BIT(6), 1);
+			/*@1:HW ctrl  0:SW ctrl*/
+		} else {
+			odm_set_bb_reg(dm, R_0xce0, BIT(1), 0);
+			odm_set_bb_reg(dm, R_0x948, BIT(6), 0);
+			/*@1:HW ctrl  0:SW ctrl*/
+		}
+	}
+#endif
+}
+
+void phydm_ac_on_off(void *dm_void, u8 swch, u8 path)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
+
+	if (dm->support_ic_type & ODM_RTL8812) {
+		odm_set_bb_reg(dm, R_0xc50, BIT(7), swch);
+		/* OFDM AntDiv function block enable */
+		odm_set_bb_reg(dm, R_0xa00, BIT(15), swch);
+		/* @CCK AntDiv function block enable */
+	} else if (dm->support_ic_type & ODM_RTL8822B) {
+		odm_set_bb_reg(dm, R_0x800, BIT(25), swch);
+		odm_set_bb_reg(dm, R_0xa00, BIT(15), swch);
+		if (path == ANT_PATH_A) {
+			odm_set_bb_reg(dm, R_0xc50, BIT(7), swch);
+		} else if (path == ANT_PATH_B) {
+			odm_set_bb_reg(dm, R_0xe50, BIT(7), swch);
+		} else if (path == ANT_PATH_AB) {
+			odm_set_bb_reg(dm, R_0xc50, BIT(7), swch);
+			odm_set_bb_reg(dm, R_0xe50, BIT(7), swch);
+		}
+	} else {
+		odm_set_bb_reg(dm, R_0x8d4, BIT(24), swch);
+		/* OFDM AntDiv function block enable */
+
+		if (dm->cut_version >= ODM_CUT_C &&
+		    dm->support_ic_type == ODM_RTL8821 &&
+		    dm->ant_div_type != S0S1_SW_ANTDIV) {
+			PHYDM_DBG(dm, DBG_ANT_DIV, "(Turn %s) CCK HW-AntDiv\n",
+				  (swch == ANTDIV_ON) ? "ON" : "OFF");
+			odm_set_bb_reg(dm, R_0x800, BIT(25), swch);
+			odm_set_bb_reg(dm, R_0xa00, BIT(15), swch);
+			/* @CCK AntDiv function block enable */
+		} else if (dm->support_ic_type == ODM_RTL8821C) {
+			PHYDM_DBG(dm, DBG_ANT_DIV, "(Turn %s) CCK HW-AntDiv\n",
+				  (swch == ANTDIV_ON) ? "ON" : "OFF");
+			odm_set_bb_reg(dm, R_0x800, BIT(25), swch);
+			odm_set_bb_reg(dm, R_0xa00, BIT(15), swch);
+			/* @CCK AntDiv function block enable */
+		}
+	}
+}
+
+void odm_ant_div_on_off(void *dm_void, u8 swch, u8 path)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
+
+	if (fat_tab->ant_div_on_off != swch) {
+		if (dm->ant_div_type == S0S1_SW_ANTDIV)
+			return;
+
+		if (dm->support_ic_type & ODM_N_ANTDIV_SUPPORT) {
+			PHYDM_DBG(dm, DBG_ANT_DIV,
+				  "(( Turn %s )) N-Series HW-AntDiv block\n",
+				  (swch == ANTDIV_ON) ? "ON" : "OFF");
+			phydm_n_on_off(dm, swch, path);
+
+		} else if (dm->support_ic_type & ODM_AC_ANTDIV_SUPPORT) {
+			PHYDM_DBG(dm, DBG_ANT_DIV,
+				  "(( Turn %s )) AC-Series HW-AntDiv block\n",
+				  (swch == ANTDIV_ON) ? "ON" : "OFF");
+			phydm_ac_on_off(dm, swch, path);
+		}
+	}
+	fat_tab->ant_div_on_off = swch;
+}
+
+void odm_tx_by_tx_desc_or_reg(void *dm_void, u8 swch)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
+	u8 enable;
+
+	if (fat_tab->b_fix_tx_ant == NO_FIX_TX_ANT)
+		enable = (swch == TX_BY_DESC) ? 1 : 0;
+	else
+		enable = 0; /*@Force TX by Reg*/
+
+	if (dm->ant_div_type != CGCS_RX_HW_ANTDIV) {
+		if (dm->support_ic_type & ODM_N_ANTDIV_SUPPORT)
+			odm_set_bb_reg(dm, R_0x80c, BIT(21), enable);
+		else if (dm->support_ic_type & ODM_AC_ANTDIV_SUPPORT)
+			odm_set_bb_reg(dm, R_0x900, BIT(18), enable);
+
+		PHYDM_DBG(dm, DBG_ANT_DIV, "[AntDiv] TX_Ant_BY (( %s ))\n",
+			  (enable == TX_BY_DESC) ? "DESC" : "REG");
+	}
+}
+
+void phydm_antdiv_reset_statistic(
+	void *dm_void,
+	u32 macid)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
+
+	fat_tab->main_ant_sum[macid] = 0;
+	fat_tab->aux_ant_sum[macid] = 0;
+	fat_tab->main_ant_cnt[macid] = 0;
+	fat_tab->aux_ant_cnt[macid] = 0;
+	fat_tab->main_ant_sum_cck[macid] = 0;
+	fat_tab->aux_ant_sum_cck[macid] = 0;
+	fat_tab->main_ant_cnt_cck[macid] = 0;
+	fat_tab->aux_ant_cnt_cck[macid] = 0;
+}
+
+void phydm_fast_training_enable(
+	void *dm_void,
+	u8 swch)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	u8 enable;
+
+	if (swch == FAT_ON)
+		enable = 1;
+	else
+		enable = 0;
+
+	PHYDM_DBG(dm, DBG_ANT_DIV, "Fast ant Training_en = ((%d))\n", enable);
+
+	if (dm->support_ic_type == ODM_RTL8188E) {
+		odm_set_bb_reg(dm, R_0xe08, BIT(16), enable); /*@enable fast training*/
+	} else if (dm->support_ic_type == ODM_RTL8192E) {
+		odm_set_bb_reg(dm, R_0xb34, BIT(28), enable); /*@enable fast training (path-A)*/
+#if 0
+		/*odm_set_bb_reg(dm, R_0xb34, BIT(29), enable);*/ /*enable fast training (path-B)*/
+#endif
+	} else if (dm->support_ic_type & (ODM_RTL8821 | ODM_RTL8822B)) {
+		odm_set_bb_reg(dm, R_0x900, BIT(19), enable); /*@enable fast training */
+	}
+}
+
+void phydm_keep_rx_ack_ant_by_tx_ant_time(
+	void *dm_void,
+	u32 time)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+
+	/* Timming issue: keep Rx ant after tx for ACK ( time x 3.2 mu sec)*/
+	if (dm->support_ic_type & ODM_N_ANTDIV_SUPPORT)
+		odm_set_bb_reg(dm, R_0xe20, BIT(23) | BIT(22) | BIT(21) | BIT(20), time);
+	else if (dm->support_ic_type & ODM_AC_ANTDIV_SUPPORT)
+		odm_set_bb_reg(dm, R_0x818, BIT(23) | BIT(22) | BIT(21) | BIT(20), time);
+}
+
+void odm_update_rx_idle_ant(
+	void *dm_void,
+	u8 ant)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
+	u32 default_ant, optional_ant, value32, default_tx_ant;
+
+	if (fat_tab->rx_idle_ant != ant) {
+		PHYDM_DBG(dm, DBG_ANT_DIV,
+			  "[ Update Rx-Idle-ant ] rx_idle_ant =%s\n",
+			  (ant == MAIN_ANT) ? "MAIN_ANT" : "AUX_ANT");
+
+		if (!(dm->support_ic_type & ODM_RTL8723B))
+			fat_tab->rx_idle_ant = ant;
+
+		if (ant == MAIN_ANT) {
+			default_ant = ANT1_2G;
+			optional_ant = ANT2_2G;
+		} else {
+			default_ant = ANT2_2G;
+			optional_ant = ANT1_2G;
+		}
+
+		if (fat_tab->b_fix_tx_ant != NO_FIX_TX_ANT)
+			default_tx_ant = (fat_tab->b_fix_tx_ant == FIX_TX_AT_MAIN) ? 0 : 1;
+		else
+			default_tx_ant = default_ant;
+
+		if (dm->support_ic_type & ODM_N_ANTDIV_SUPPORT) {
+			if (dm->support_ic_type & (ODM_RTL8192E | ODM_RTL8197F)) {
+				odm_set_bb_reg(dm, R_0xb38, BIT(5) | BIT(4) | BIT(3), default_ant); /* @Default RX */
+				odm_set_bb_reg(dm, R_0xb38, BIT(8) | BIT(7) | BIT(6), optional_ant); /* Optional RX */
+				odm_set_bb_reg(dm, R_0x860, BIT(14) | BIT(13) | BIT(12), default_ant); /* @Default TX */
+			}
+#if (RTL8723B_SUPPORT == 1)
+			else if (dm->support_ic_type == ODM_RTL8723B) {
+				value32 = odm_get_bb_reg(dm, R_0x948, 0xFFF);
+
+				if (value32 != 0x280)
+					odm_update_rx_idle_ant_8723b(dm, ant, default_ant, optional_ant);
+				else
+					PHYDM_DBG(dm, DBG_ANT_DIV, "[ Update Rx-Idle-ant ] 8723B: Fail to set RX antenna due to 0x948 = 0x280\n");
+			}
+#endif
+
+#if (RTL8723D_SUPPORT == 1) /*@Mingzhi 2017-05-08*/
+			else if (dm->support_ic_type == ODM_RTL8723D) {
+				phydm_set_tx_ant_pwr_8723d(dm, ant);
+				odm_update_rx_idle_ant_8723d(dm, ant, default_ant, optional_ant);
+			}
+#endif
+
+			else { /*@8188E & 8188F*/
+/*@
+				if (dm->support_ic_type == ODM_RTL8723D) {
+#if (RTL8723D_SUPPORT == 1)
+					phydm_set_tx_ant_pwr_8723d(dm, ant);
+#endif
+				}
+*/
+#if (RTL8188F_SUPPORT == 1)
+				if (dm->support_ic_type == ODM_RTL8188F)
+					phydm_update_rx_idle_antenna_8188F(dm, default_ant);
+#endif
+
+				odm_set_bb_reg(dm, R_0x864, BIT(5) | BIT(4) | BIT(3), default_ant); /*@Default RX*/
+				odm_set_bb_reg(dm, R_0x864, BIT(8) | BIT(7) | BIT(6), optional_ant); /*Optional RX*/
+				odm_set_bb_reg(dm, R_0x860, BIT(14) | BIT(13) | BIT(12), default_tx_ant); /*@Default TX*/
+			}
+		} else if (dm->support_ic_type & ODM_AC_ANTDIV_SUPPORT) {
+			u16 value16 = odm_read_2byte(dm, ODM_REG_TRMUX_11AC + 2);
+			/* @2014/01/14 MH/Luke.Lee Add direct write for register 0xc0a to prevnt */
+			/* @incorrect 0xc08 bit0-15 .We still not know why it is changed. */
+			value16 &= ~(BIT(11) | BIT(10) | BIT(9) | BIT(8) | BIT(7) | BIT(6) | BIT(5) | BIT(4) | BIT(3));
+			value16 |= ((u16)default_ant << 3);
+			value16 |= ((u16)optional_ant << 6);
+			value16 |= ((u16)default_tx_ant << 9);
+			odm_write_2byte(dm, ODM_REG_TRMUX_11AC + 2, value16);
+#if 0
+			odm_set_bb_reg(dm, ODM_REG_TRMUX_11AC, BIT(21) | BIT20 | BIT19, default_ant);	 /* @Default RX */
+			odm_set_bb_reg(dm, ODM_REG_TRMUX_11AC, BIT(24) | BIT23 | BIT22, optional_ant); /* Optional RX */
+			odm_set_bb_reg(dm, ODM_REG_TRMUX_11AC, BIT(27) | BIT26 | BIT25, default_ant);	 /* @Default TX */
+#endif
+		}
+
+		if (dm->support_ic_type & (ODM_RTL8821C | ODM_RTL8822B | ODM_RTL8814A))
+			odm_set_mac_reg(dm, R_0x6d8, 0x7, default_tx_ant); /*PathA Resp Tx*/
+		else if (dm->support_ic_type == ODM_RTL8188E)
+			odm_set_mac_reg(dm, R_0x6d8, BIT(7) | BIT(6), default_tx_ant); /*PathA Resp Tx*/
+		else
+			odm_set_mac_reg(dm, R_0x6d8, BIT(10) | BIT(9) | BIT(8), default_tx_ant); /*PathA Resp Tx*/
+
+	} else { /* @fat_tab->rx_idle_ant == ant */
+		PHYDM_DBG(dm, DBG_ANT_DIV,
+			  "[ Stay in Ori-ant ]  rx_idle_ant =%s\n",
+			  (ant == MAIN_ANT) ? "MAIN_ANT" : "AUX_ANT");
+		fat_tab->rx_idle_ant = ant;
+	}
+}
+
+void phydm_update_rx_idle_ant_pathb(void *dm_void, u8 ant)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
+	u32 default_ant, optional_ant, value32, default_tx_ant;
+
+	if (fat_tab->rx_idle_ant2 != ant) {
+		PHYDM_DBG(dm, DBG_ANT_DIV,
+			  "[ Update Rx-Idle-ant2 ] rx_idle_ant2 =%s\n",
+			  (ant == MAIN_ANT) ? "MAIN_ANT" : "AUX_ANT");
+		if (ant == MAIN_ANT) {
+			default_ant = ANT1_2G;
+			optional_ant = ANT2_2G;
+		} else {
+			default_ant = ANT2_2G;
+			optional_ant = ANT1_2G;
+		}
+
+		if (fat_tab->b_fix_tx_ant != NO_FIX_TX_ANT)
+			default_tx_ant = (fat_tab->b_fix_tx_ant ==
+					  FIX_TX_AT_MAIN) ? 0 : 1;
+		else
+			default_tx_ant = default_ant;
+		if (dm->support_ic_type & ODM_RTL8822B) {
+			u16 v16 = odm_read_2byte(dm, ODM_REG_ANT_11AC_B + 2);
+
+			v16 &= ~(0xff8);/*0xE08[11:3]*/
+			v16 |= ((u16)default_ant << 3);
+			v16 |= ((u16)optional_ant << 6);
+			v16 |= ((u16)default_tx_ant << 9);
+			odm_write_2byte(dm, ODM_REG_ANT_11AC_B + 2, v16);
+			odm_set_mac_reg(dm, R_0x6d8, 0x38, default_tx_ant);
+			/*PathB Resp Tx*/
+		}
+	} else {
+		/* fat_tab->rx_idle_ant2 == ant */
+		PHYDM_DBG(dm, DBG_ANT_DIV, "[Stay Ori Ant] rx_idle_ant2 = %s\n",
+			  (ant == MAIN_ANT) ? "MAIN_ANT" : "AUX_ANT");
+		fat_tab->rx_idle_ant2 = ant;
+	}
+}
+
+void phydm_set_antdiv_val(
+	void *dm_void,
+	u32 *val_buf,
+	u8 val_len)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+
+	if (val_len != 1) {
+		PHYDM_DBG(dm, ODM_COMP_API, "[Error][antdiv]Need val_len=1\n");
+		return;
+	}
+
+	odm_update_rx_idle_ant(dm, (u8)(*val_buf));
+}
+
+void odm_update_tx_ant(
+	void *dm_void,
+	u8 ant,
+	u32 mac_id)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
+	u8 tx_ant;
+
+	if (fat_tab->b_fix_tx_ant != NO_FIX_TX_ANT)
+		ant = (fat_tab->b_fix_tx_ant == FIX_TX_AT_MAIN) ? MAIN_ANT : AUX_ANT;
+
+	if (dm->ant_div_type == CG_TRX_SMART_ANTDIV)
+		tx_ant = ant;
+	else {
+		if (ant == MAIN_ANT)
+			tx_ant = ANT1_2G;
+		else
+			tx_ant = ANT2_2G;
+	}
+
+	fat_tab->antsel_a[mac_id] = tx_ant & BIT(0);
+	fat_tab->antsel_b[mac_id] = (tx_ant & BIT(1)) >> 1;
+	fat_tab->antsel_c[mac_id] = (tx_ant & BIT(2)) >> 2;
+
+	PHYDM_DBG(dm, DBG_ANT_DIV,
+		  "[Set TX-DESC value]: mac_id:(( %d )),  tx_ant = (( %s ))\n",
+		  mac_id, (ant == MAIN_ANT) ? "MAIN_ANT" : "AUX_ANT");
+#if 0
+	/* PHYDM_DBG(dm,DBG_ANT_DIV,"antsel_tr_mux=(( 3'b%d%d%d ))\n",fat_tab->antsel_c[mac_id] , fat_tab->antsel_b[mac_id] , fat_tab->antsel_a[mac_id] ); */
+#endif
+}
+
+#ifdef BEAMFORMING_SUPPORT
+#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
+
+void odm_bdc_init(
+	void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct _BF_DIV_COEX_ *dm_bdc_table = &dm->dm_bdc_table;
+
+	PHYDM_DBG(dm, DBG_ANT_DIV, "\n[ BDC Initialization......]\n");
+	dm_bdc_table->BDC_state = BDC_DIV_TRAIN_STATE;
+	dm_bdc_table->bdc_mode = BDC_MODE_NULL;
+	dm_bdc_table->bdc_try_flag = 0;
+	dm_bdc_table->bd_ccoex_type_wbfer = 0;
+	dm->bdc_holdstate = 0xff;
+
+	if (dm->support_ic_type == ODM_RTL8192E) {
+		odm_set_bb_reg(dm, R_0xd7c, 0x0FFFFFFF, 0x1081008);
+		odm_set_bb_reg(dm, R_0xd80, 0x0FFFFFFF, 0);
+	} else if (dm->support_ic_type == ODM_RTL8812) {
+		odm_set_bb_reg(dm, R_0x9b0, 0x0FFFFFFF, 0x1081008); /* @0x9b0[30:0] = 01081008 */
+		odm_set_bb_reg(dm, R_0x9b4, 0x0FFFFFFF, 0); /* @0x9b4[31:0] = 00000000 */
+	}
+}
+
+void odm_CSI_on_off(
+	void *dm_void,
+	u8 CSI_en)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	if (CSI_en == CSI_ON) {
+		if (dm->support_ic_type == ODM_RTL8192E)
+			odm_set_mac_reg(dm, R_0xd84, BIT(11), 1); /* @0xd84[11]=1 */
+		else if (dm->support_ic_type == ODM_RTL8812)
+			odm_set_mac_reg(dm, R_0x9b0, BIT(31), 1); /* @0x9b0[31]=1 */
+
+	} else if (CSI_en == CSI_OFF) {
+		if (dm->support_ic_type == ODM_RTL8192E)
+			odm_set_mac_reg(dm, R_0xd84, BIT(11), 0); /* @0xd84[11]=0 */
+		else if (dm->support_ic_type == ODM_RTL8812)
+			odm_set_mac_reg(dm, R_0x9b0, BIT(31), 0); /* @0x9b0[31]=0 */
+	}
+}
+
+void odm_bd_ccoex_type_with_bfer_client(
+	void *dm_void,
+	u8 swch)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct _BF_DIV_COEX_ *dm_bdc_table = &dm->dm_bdc_table;
+	u8 bd_ccoex_type_wbfer;
+
+	if (swch == DIVON_CSIOFF) {
+		PHYDM_DBG(dm, DBG_ANT_DIV,
+			  "[BDCcoexType: 1] {DIV,CSI} ={1,0}\n");
+		bd_ccoex_type_wbfer = 1;
+
+		if (bd_ccoex_type_wbfer != dm_bdc_table->bd_ccoex_type_wbfer) {
+			odm_ant_div_on_off(dm, ANTDIV_ON, ANT_PATH_A);
+			odm_CSI_on_off(dm, CSI_OFF);
+			dm_bdc_table->bd_ccoex_type_wbfer = 1;
+		}
+	} else if (swch == DIVOFF_CSION) {
+		PHYDM_DBG(dm, DBG_ANT_DIV,
+			  "[BDCcoexType: 2] {DIV,CSI} ={0,1}\n");
+		bd_ccoex_type_wbfer = 2;
+
+		if (bd_ccoex_type_wbfer != dm_bdc_table->bd_ccoex_type_wbfer) {
+			odm_ant_div_on_off(dm, ANTDIV_OFF, ANT_PATH_A);
+			odm_CSI_on_off(dm, CSI_ON);
+			dm_bdc_table->bd_ccoex_type_wbfer = 2;
+		}
+	}
+}
+
+void odm_bf_ant_div_mode_arbitration(
+	void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct _BF_DIV_COEX_ *dm_bdc_table = &dm->dm_bdc_table;
+	u8 current_bdc_mode;
+
+#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
+	PHYDM_DBG(dm, DBG_ANT_DIV, "\n");
+
+	/* @2 mode 1 */
+	if (dm_bdc_table->num_txbfee_client != 0 && dm_bdc_table->num_txbfer_client == 0) {
+		current_bdc_mode = BDC_MODE_1;
+
+		if (current_bdc_mode != dm_bdc_table->bdc_mode) {
+			dm_bdc_table->bdc_mode = BDC_MODE_1;
+			odm_bd_ccoex_type_with_bfer_client(dm, DIVON_CSIOFF);
+			dm_bdc_table->bdc_rx_idle_update_counter = 1;
+			PHYDM_DBG(dm, DBG_ANT_DIV, "Change to (( Mode1 ))\n");
+		}
+
+		PHYDM_DBG(dm, DBG_ANT_DIV,
+			  "[Antdiv + BF coextance mode] : (( Mode1 ))\n");
+	}
+	/* @2 mode 2 */
+	else if ((dm_bdc_table->num_txbfee_client == 0) && (dm_bdc_table->num_txbfer_client != 0)) {
+		current_bdc_mode = BDC_MODE_2;
+
+		if (current_bdc_mode != dm_bdc_table->bdc_mode) {
+			dm_bdc_table->bdc_mode = BDC_MODE_2;
+			dm_bdc_table->BDC_state = BDC_DIV_TRAIN_STATE;
+			dm_bdc_table->bdc_try_flag = 0;
+			PHYDM_DBG(dm, DBG_ANT_DIV, "Change to (( Mode2 ))\n");
+		}
+		PHYDM_DBG(dm, DBG_ANT_DIV,
+			  "[Antdiv + BF coextance mode] : (( Mode2 ))\n");
+	}
+	/* @2 mode 3 */
+	else if ((dm_bdc_table->num_txbfee_client != 0) && (dm_bdc_table->num_txbfer_client != 0)) {
+		current_bdc_mode = BDC_MODE_3;
+
+		if (current_bdc_mode != dm_bdc_table->bdc_mode) {
+			dm_bdc_table->bdc_mode = BDC_MODE_3;
+			dm_bdc_table->BDC_state = BDC_DIV_TRAIN_STATE;
+			dm_bdc_table->bdc_try_flag = 0;
+			dm_bdc_table->bdc_rx_idle_update_counter = 1;
+			PHYDM_DBG(dm, DBG_ANT_DIV, "Change to (( Mode3 ))\n");
+		}
+
+		PHYDM_DBG(dm, DBG_ANT_DIV,
+			  "[Antdiv + BF coextance mode] : (( Mode3 ))\n");
+	}
+	/* @2 mode 4 */
+	else if ((dm_bdc_table->num_txbfee_client == 0) && (dm_bdc_table->num_txbfer_client == 0)) {
+		current_bdc_mode = BDC_MODE_4;
+
+		if (current_bdc_mode != dm_bdc_table->bdc_mode) {
+			dm_bdc_table->bdc_mode = BDC_MODE_4;
+			odm_bd_ccoex_type_with_bfer_client(dm, DIVON_CSIOFF);
+			PHYDM_DBG(dm, DBG_ANT_DIV, "Change to (( Mode4 ))\n");
+		}
+
+		PHYDM_DBG(dm, DBG_ANT_DIV,
+			  "[Antdiv + BF coextance mode] : (( Mode4 ))\n");
+	}
+#endif
+}
+
+void odm_div_train_state_setting(
+	void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct _BF_DIV_COEX_ *dm_bdc_table = &dm->dm_bdc_table;
+
+	PHYDM_DBG(dm, DBG_ANT_DIV,
+		  "\n*****[S T A R T ]*****  [2-0. DIV_TRAIN_STATE]\n");
+	dm_bdc_table->bdc_try_counter = 2;
+	dm_bdc_table->bdc_try_flag = 1;
+	dm_bdc_table->BDC_state = bdc_bfer_train_state;
+	odm_bd_ccoex_type_with_bfer_client(dm, DIVON_CSIOFF);
+}
+
+void odm_bd_ccoex_bfee_rx_div_arbitration(
+	void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct _BF_DIV_COEX_ *dm_bdc_table = &dm->dm_bdc_table;
+	boolean stop_bf_flag;
+	u8 bdc_active_mode;
+
+#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
+
+	PHYDM_DBG(dm, DBG_ANT_DIV,
+		  "***{ num_BFee,  num_BFer, num_client}  = (( %d  ,  %d  ,  %d))\n",
+		  dm_bdc_table->num_txbfee_client,
+		  dm_bdc_table->num_txbfer_client, dm_bdc_table->num_client);
+	PHYDM_DBG(dm, DBG_ANT_DIV,
+		  "***{ num_BF_tars,  num_DIV_tars }  = ((  %d  ,  %d ))\n",
+		  dm_bdc_table->num_bf_tar, dm_bdc_table->num_div_tar);
+
+	/* @2 [ MIB control ] */
+	if (dm->bdc_holdstate == 2) {
+		odm_bd_ccoex_type_with_bfer_client(dm, DIVOFF_CSION);
+		dm_bdc_table->BDC_state = BDC_BF_HOLD_STATE;
+		PHYDM_DBG(dm, DBG_ANT_DIV, "Force in [ BF STATE]\n");
+		return;
+	} else if (dm->bdc_holdstate == 1) {
+		dm_bdc_table->BDC_state = BDC_DIV_HOLD_STATE;
+		odm_bd_ccoex_type_with_bfer_client(dm, DIVON_CSIOFF);
+		PHYDM_DBG(dm, DBG_ANT_DIV, "Force in [ DIV STATE]\n");
+		return;
+	}
+
+	/* @------------------------------------------------------------ */
+
+	/* @2 mode 2 & 3 */
+	if (dm_bdc_table->bdc_mode == BDC_MODE_2 || dm_bdc_table->bdc_mode == BDC_MODE_3) {
+		PHYDM_DBG(dm, DBG_ANT_DIV,
+			  "\n{ Try_flag,  Try_counter } = {  %d , %d  }\n",
+			  dm_bdc_table->bdc_try_flag,
+			  dm_bdc_table->bdc_try_counter);
+		PHYDM_DBG(dm, DBG_ANT_DIV, "BDCcoexType = (( %d ))\n\n",
+			  dm_bdc_table->bd_ccoex_type_wbfer);
+
+		/* @All Client have Bfer-Cap------------------------------- */
+		if (dm_bdc_table->num_txbfer_client == dm_bdc_table->num_client) { /* @BFer STA Only?: yes */
+			PHYDM_DBG(dm, DBG_ANT_DIV,
+				  "BFer STA only?  (( Yes ))\n");
+			dm_bdc_table->bdc_try_flag = 0;
+			dm_bdc_table->BDC_state = BDC_DIV_TRAIN_STATE;
+			odm_bd_ccoex_type_with_bfer_client(dm, DIVOFF_CSION);
+			return;
+		} else
+			PHYDM_DBG(dm, DBG_ANT_DIV,
+				  "BFer STA only?  (( No ))\n");
+		if (dm_bdc_table->is_all_bf_sta_idle == false && dm_bdc_table->is_all_div_sta_idle == true) {
+			PHYDM_DBG(dm, DBG_ANT_DIV,
+				  "All DIV-STA are idle, but BF-STA not\n");
+			dm_bdc_table->bdc_try_flag = 0;
+			dm_bdc_table->BDC_state = bdc_bfer_train_state;
+			odm_bd_ccoex_type_with_bfer_client(dm, DIVOFF_CSION);
+			return;
+		} else if (dm_bdc_table->is_all_bf_sta_idle == true && dm_bdc_table->is_all_div_sta_idle == false) {
+			PHYDM_DBG(dm, DBG_ANT_DIV,
+				  "All BF-STA are idle, but DIV-STA not\n");
+			dm_bdc_table->bdc_try_flag = 0;
+			dm_bdc_table->BDC_state = BDC_DIV_TRAIN_STATE;
+			odm_bd_ccoex_type_with_bfer_client(dm, DIVON_CSIOFF);
+			return;
+		}
+
+		/* Select active mode-------------------------------------- */
+		if (dm_bdc_table->num_bf_tar == 0) { /* Selsect_1,  Selsect_2 */
+			if (dm_bdc_table->num_div_tar == 0) { /* Selsect_3 */
+				PHYDM_DBG(dm, DBG_ANT_DIV,
+					  "Select active mode (( 1 ))\n");
+				dm_bdc_table->bdc_active_mode = 1;
+			} else {
+				PHYDM_DBG(dm, DBG_ANT_DIV,
+					  "Select active mode  (( 2 ))\n");
+				dm_bdc_table->bdc_active_mode = 2;
+			}
+			dm_bdc_table->bdc_try_flag = 0;
+			dm_bdc_table->BDC_state = BDC_DIV_TRAIN_STATE;
+			odm_bd_ccoex_type_with_bfer_client(dm, DIVON_CSIOFF);
+			return;
+		} else { /* num_bf_tar > 0 */
+			if (dm_bdc_table->num_div_tar == 0) { /* Selsect_3 */
+				PHYDM_DBG(dm, DBG_ANT_DIV,
+					  "Select active mode (( 3 ))\n");
+				dm_bdc_table->bdc_active_mode = 3;
+				dm_bdc_table->bdc_try_flag = 0;
+				dm_bdc_table->BDC_state = bdc_bfer_train_state;
+				odm_bd_ccoex_type_with_bfer_client(dm, DIVOFF_CSION);
+				return;
+			} else { /* Selsect_4 */
+				bdc_active_mode = 4;
+				PHYDM_DBG(dm, DBG_ANT_DIV,
+					  "Select active mode (( 4 ))\n");
+
+				if (bdc_active_mode != dm_bdc_table->bdc_active_mode) {
+					dm_bdc_table->bdc_active_mode = 4;
+					PHYDM_DBG(dm, DBG_ANT_DIV, "Change to active mode (( 4 ))  &  return!!!\n");
+					return;
+				}
+			}
+		}
+
+#if 1
+		if (dm->bdc_holdstate == 0xff) {
+			dm_bdc_table->BDC_state = BDC_DIV_HOLD_STATE;
+			odm_bd_ccoex_type_with_bfer_client(dm, DIVON_CSIOFF);
+			PHYDM_DBG(dm, DBG_ANT_DIV, "Force in [ DIV STATE]\n");
+			return;
+		}
+#endif
+
+		/* @Does Client number changed ? ------------------------------- */
+		if (dm_bdc_table->num_client != dm_bdc_table->pre_num_client) {
+			dm_bdc_table->bdc_try_flag = 0;
+			dm_bdc_table->BDC_state = BDC_DIV_TRAIN_STATE;
+			PHYDM_DBG(dm, DBG_ANT_DIV,
+				  "[  The number of client has been changed !!!]   return to (( BDC_DIV_TRAIN_STATE ))\n");
+		}
+		dm_bdc_table->pre_num_client = dm_bdc_table->num_client;
+
+		if (dm_bdc_table->bdc_try_flag == 0) {
+			/* @2 DIV_TRAIN_STATE (mode 2-0) */
+			if (dm_bdc_table->BDC_state == BDC_DIV_TRAIN_STATE)
+				odm_div_train_state_setting(dm);
+			/* @2 BFer_TRAIN_STATE (mode 2-1) */
+			else if (dm_bdc_table->BDC_state == bdc_bfer_train_state) {
+				PHYDM_DBG(dm, DBG_ANT_DIV,
+					  "*****[2-1. BFer_TRAIN_STATE ]*****\n");
+
+#if 0
+				/* @if(dm_bdc_table->num_bf_tar==0) */
+				/* @{ */
+				/*	PHYDM_DBG(dm,DBG_ANT_DIV, "BF_tars exist?  : (( No )),   [ bdc_bfer_train_state ] >> [BDC_DIV_TRAIN_STATE]\n"); */
+				/*	odm_div_train_state_setting( dm); */
+				/* @} */
+				/* else */ /* num_bf_tar != 0 */
+				/* @{ */
+#endif
+				dm_bdc_table->bdc_try_counter = 2;
+				dm_bdc_table->bdc_try_flag = 1;
+				dm_bdc_table->BDC_state = BDC_DECISION_STATE;
+				odm_bd_ccoex_type_with_bfer_client(dm, DIVOFF_CSION);
+				PHYDM_DBG(dm, DBG_ANT_DIV,
+					  "BF_tars exist?  : (( Yes )),   [ bdc_bfer_train_state ] >> [BDC_DECISION_STATE]\n");
+				/* @} */
+			}
+			/* @2 DECISION_STATE (mode 2-2) */
+			else if (dm_bdc_table->BDC_state == BDC_DECISION_STATE) {
+				PHYDM_DBG(dm, DBG_ANT_DIV,
+					  "*****[2-2. DECISION_STATE]*****\n");
+#if 0
+				/* @if(dm_bdc_table->num_bf_tar==0) */
+				/* @{ */
+				/*	ODM_AntDiv_Printk(("BF_tars exist?  : (( No )),   [ DECISION_STATE ] >> [BDC_DIV_TRAIN_STATE]\n")); */
+				/*	odm_div_train_state_setting( dm); */
+				/* @} */
+				/* else */ /* num_bf_tar != 0 */
+				/* @{ */
+#endif
+				if (dm_bdc_table->BF_pass == false || dm_bdc_table->DIV_pass == false)
+					stop_bf_flag = true;
+				else
+					stop_bf_flag = false;
+
+				PHYDM_DBG(dm, DBG_ANT_DIV,
+					  "BF_tars exist?  : (( Yes )),  {BF_pass, DIV_pass, stop_bf_flag }  = { %d, %d, %d }\n",
+					  dm_bdc_table->BF_pass,
+					  dm_bdc_table->DIV_pass, stop_bf_flag);
+
+				if (stop_bf_flag == true) { /* @DIV_en */
+					dm_bdc_table->bdc_hold_counter = 10; /* @20 */
+					odm_bd_ccoex_type_with_bfer_client(dm, DIVON_CSIOFF);
+					dm_bdc_table->BDC_state = BDC_DIV_HOLD_STATE;
+					PHYDM_DBG(dm, DBG_ANT_DIV, "[ stop_bf_flag= ((true)),   BDC_DECISION_STATE ] >> [BDC_DIV_HOLD_STATE]\n");
+				} else { /* @BF_en */
+					dm_bdc_table->bdc_hold_counter = 10; /* @20 */
+					odm_bd_ccoex_type_with_bfer_client(dm, DIVOFF_CSION);
+					dm_bdc_table->BDC_state = BDC_BF_HOLD_STATE;
+					PHYDM_DBG(dm, DBG_ANT_DIV, "[stop_bf_flag= ((false)),   BDC_DECISION_STATE ] >> [BDC_BF_HOLD_STATE]\n");
+				}
+				/* @} */
+			}
+			/* @2 BF-HOLD_STATE (mode 2-3) */
+			else if (dm_bdc_table->BDC_state == BDC_BF_HOLD_STATE) {
+				PHYDM_DBG(dm, DBG_ANT_DIV,
+					  "*****[2-3. BF_HOLD_STATE ]*****\n");
+
+				PHYDM_DBG(dm, DBG_ANT_DIV,
+					  "bdc_hold_counter = (( %d ))\n",
+					  dm_bdc_table->bdc_hold_counter);
+
+				if (dm_bdc_table->bdc_hold_counter == 1) {
+					PHYDM_DBG(dm, DBG_ANT_DIV, "[ BDC_BF_HOLD_STATE ] >> [BDC_DIV_TRAIN_STATE]\n");
+					odm_div_train_state_setting(dm);
+				} else {
+					dm_bdc_table->bdc_hold_counter--;
+
+#if 0
+					/* @if(dm_bdc_table->num_bf_tar==0) */
+					/* @{ */
+					/*	PHYDM_DBG(dm,DBG_ANT_DIV, "BF_tars exist?  : (( No )),   [ BDC_BF_HOLD_STATE ] >> [BDC_DIV_TRAIN_STATE]\n"); */
+					/*	odm_div_train_state_setting( dm); */
+					/* @} */
+					/* else */ /* num_bf_tar != 0 */
+					/* @{ */
+					/* PHYDM_DBG(dm,DBG_ANT_DIV, "BF_tars exist?  : (( Yes ))\n"); */
+#endif
+					dm_bdc_table->BDC_state = BDC_BF_HOLD_STATE;
+					odm_bd_ccoex_type_with_bfer_client(dm, DIVOFF_CSION);
+					PHYDM_DBG(dm, DBG_ANT_DIV, "[ BDC_BF_HOLD_STATE ] >> [BDC_BF_HOLD_STATE]\n");
+					/* @} */
+				}
+			}
+			/* @2 DIV-HOLD_STATE (mode 2-4) */
+			else if (dm_bdc_table->BDC_state == BDC_DIV_HOLD_STATE) {
+				PHYDM_DBG(dm, DBG_ANT_DIV,
+					  "*****[2-4. DIV_HOLD_STATE ]*****\n");
+
+				PHYDM_DBG(dm, DBG_ANT_DIV,
+					  "bdc_hold_counter = (( %d ))\n",
+					  dm_bdc_table->bdc_hold_counter);
+
+				if (dm_bdc_table->bdc_hold_counter == 1) {
+					PHYDM_DBG(dm, DBG_ANT_DIV, "[ BDC_DIV_HOLD_STATE ] >> [BDC_DIV_TRAIN_STATE]\n");
+					odm_div_train_state_setting(dm);
+				} else {
+					dm_bdc_table->bdc_hold_counter--;
+					dm_bdc_table->BDC_state = BDC_DIV_HOLD_STATE;
+					odm_bd_ccoex_type_with_bfer_client(dm, DIVON_CSIOFF);
+					PHYDM_DBG(dm, DBG_ANT_DIV, "[ BDC_DIV_HOLD_STATE ] >> [BDC_DIV_HOLD_STATE]\n");
+				}
+			}
+
+		} else if (dm_bdc_table->bdc_try_flag == 1) {
+			/* @2 Set Training counter */
+			if (dm_bdc_table->bdc_try_counter > 1) {
+				dm_bdc_table->bdc_try_counter--;
+				if (dm_bdc_table->bdc_try_counter == 1)
+					dm_bdc_table->bdc_try_flag = 0;
+
+				PHYDM_DBG(dm, DBG_ANT_DIV, "Training !!\n");
+				/* return ; */
+			}
+		}
+	}
+
+	PHYDM_DBG(dm, DBG_ANT_DIV, "\n[end]\n");
+
+#endif /* @#if(DM_ODM_SUPPORT_TYPE  == ODM_AP) */
+}
+
+#endif
+#endif /* @#ifdef BEAMFORMING_SUPPORT */
+
+#if (RTL8188E_SUPPORT == 1)
+
+void odm_rx_hw_ant_div_init_88e(
+	void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	u32 value32;
+	struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
+
+#if 0
+	if (*dm->mp_mode == true) {
+		odm_set_bb_reg(dm, ODM_REG_IGI_A_11N, BIT(7), 0); /* @disable HW AntDiv */
+		odm_set_bb_reg(dm, ODM_REG_LNA_SWITCH_11N, BIT(31), 1);  /* @1:CG, 0:CS */
+		return;
+	}
+#endif
+
+	PHYDM_DBG(dm, DBG_ANT_DIV,
+		  "***8188E AntDiv_Init =>  ant_div_type=[CGCS_RX_HW_ANTDIV]\n");
+
+	/* @MAC setting */
+	value32 = odm_get_mac_reg(dm, ODM_REG_ANTSEL_PIN_11N, MASKDWORD);
+	odm_set_mac_reg(dm, ODM_REG_ANTSEL_PIN_11N, MASKDWORD, value32 | (BIT(23) | BIT(25))); /* Reg4C[25]=1, Reg4C[23]=1 for pin output */
+	/* Pin Settings */
+	odm_set_bb_reg(dm, ODM_REG_PIN_CTRL_11N, BIT(9) | BIT(8), 0); /* reg870[8]=1'b0, reg870[9]=1'b0		 */ /* antsel antselb by HW */
+	odm_set_bb_reg(dm, ODM_REG_RX_ANT_CTRL_11N, BIT(10), 0); /* reg864[10]=1'b0	 */ /* antsel2 by HW */
+	odm_set_bb_reg(dm, ODM_REG_LNA_SWITCH_11N, BIT(22), 1); /* regb2c[22]=1'b0	 */ /* disable CS/CG switch */
+	odm_set_bb_reg(dm, ODM_REG_LNA_SWITCH_11N, BIT(31), 1); /* regb2c[31]=1'b1	 */ /* output at CG only */
+	/* OFDM Settings */
+	odm_set_bb_reg(dm, ODM_REG_ANTDIV_PARA1_11N, MASKDWORD, 0x000000a0);
+	/* @CCK Settings */
+	odm_set_bb_reg(dm, ODM_REG_BB_PWR_SAV4_11N, BIT(7), 1); /* @Fix CCK PHY status report issue */
+	odm_set_bb_reg(dm, ODM_REG_CCK_ANTDIV_PARA2_11N, BIT(4), 1); /* @CCK complete HW AntDiv within 64 samples */
+
+	odm_set_bb_reg(dm, ODM_REG_ANT_MAPPING1_11N, 0xFFFF, 0x0001); /* @antenna mapping table */
+
+	fat_tab->enable_ctrl_frame_antdiv = 1;
+}
+
+void odm_trx_hw_ant_div_init_88e(
+	void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	u32 value32;
+	struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
+
+#if 0
+	if (*dm->mp_mode == true) {
+		odm_set_bb_reg(dm, ODM_REG_IGI_A_11N, BIT(7), 0); /* @disable HW AntDiv */
+		odm_set_bb_reg(dm, ODM_REG_RX_ANT_CTRL_11N, BIT(5) | BIT4 | BIT3, 0); /* @Default RX   (0/1) */
+		return;
+	}
+#endif
+
+	PHYDM_DBG(dm, DBG_ANT_DIV,
+		  "***8188E AntDiv_Init =>  ant_div_type=[CG_TRX_HW_ANTDIV (SPDT)]\n");
+
+	/* @MAC setting */
+	value32 = odm_get_mac_reg(dm, ODM_REG_ANTSEL_PIN_11N, MASKDWORD);
+	odm_set_mac_reg(dm, ODM_REG_ANTSEL_PIN_11N, MASKDWORD, value32 | (BIT(23) | BIT(25))); /* Reg4C[25]=1, Reg4C[23]=1 for pin output */
+	/* Pin Settings */
+	odm_set_bb_reg(dm, ODM_REG_PIN_CTRL_11N, BIT(9) | BIT(8), 0); /* reg870[8]=1'b0, reg870[9]=1'b0		 */ /* antsel antselb by HW */
+	odm_set_bb_reg(dm, ODM_REG_RX_ANT_CTRL_11N, BIT(10), 0); /* reg864[10]=1'b0	 */ /* antsel2 by HW */
+	odm_set_bb_reg(dm, ODM_REG_LNA_SWITCH_11N, BIT(22), 0); /* regb2c[22]=1'b0	 */ /* disable CS/CG switch */
+	odm_set_bb_reg(dm, ODM_REG_LNA_SWITCH_11N, BIT(31), 1); /* regb2c[31]=1'b1	 */ /* output at CG only */
+	/* OFDM Settings */
+	odm_set_bb_reg(dm, ODM_REG_ANTDIV_PARA1_11N, MASKDWORD, 0x000000a0);
+	/* @CCK Settings */
+	odm_set_bb_reg(dm, ODM_REG_BB_PWR_SAV4_11N, BIT(7), 1); /* @Fix CCK PHY status report issue */
+	odm_set_bb_reg(dm, ODM_REG_CCK_ANTDIV_PARA2_11N, BIT(4), 1); /* @CCK complete HW AntDiv within 64 samples */
+
+	/* @antenna mapping table */
+	if (!dm->is_mp_chip) { /* testchip */
+		odm_set_bb_reg(dm, ODM_REG_RX_DEFAULT_A_11N, BIT(10) | BIT(9) | BIT(8), 1); /* Reg858[10:8]=3'b001 */
+		odm_set_bb_reg(dm, ODM_REG_RX_DEFAULT_A_11N, BIT(13) | BIT(12) | BIT(11), 2); /* Reg858[13:11]=3'b010 */
+	} else /* @MPchip */
+		odm_set_bb_reg(dm, ODM_REG_ANT_MAPPING1_11N, MASKDWORD, 0x0201); /*Reg914=3'b010, Reg915=3'b001*/
+
+	fat_tab->enable_ctrl_frame_antdiv = 1;
+}
+
+#if (defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY)) || (defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY))
+void odm_smart_hw_ant_div_init_88e(
+	void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	u32 value32, i;
+	struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
+
+	PHYDM_DBG(dm, DBG_ANT_DIV,
+		  "***8188E AntDiv_Init =>  ant_div_type=[CG_TRX_SMART_ANTDIV]\n");
+
+#if 0
+	if (*dm->mp_mode == true) {
+		PHYDM_DBG(dm, ODM_COMP_INIT, "dm->ant_div_type: %d\n",
+			  dm->ant_div_type);
+		return;
+	}
+#endif
+
+	fat_tab->train_idx = 0;
+	fat_tab->fat_state = FAT_PREPARE_STATE;
+
+	dm->fat_comb_a = 5;
+	dm->antdiv_intvl = 0x64; /* @100ms */
+
+	for (i = 0; i < 6; i++)
+		fat_tab->bssid[i] = 0;
+	for (i = 0; i < (dm->fat_comb_a); i++) {
+		fat_tab->ant_sum_rssi[i] = 0;
+		fat_tab->ant_rssi_cnt[i] = 0;
+		fat_tab->ant_ave_rssi[i] = 0;
+	}
+
+	/* @MAC setting */
+	value32 = odm_get_mac_reg(dm, R_0x4c, MASKDWORD);
+	odm_set_mac_reg(dm, R_0x4c, MASKDWORD, value32 | (BIT(23) | BIT(25))); /* Reg4C[25]=1, Reg4C[23]=1 for pin output */
+	value32 = odm_get_mac_reg(dm, R_0x7b4, MASKDWORD);
+	odm_set_mac_reg(dm, R_0x7b4, MASKDWORD, value32 | (BIT(16) | BIT(17))); /* Reg7B4[16]=1 enable antenna training, Reg7B4[17]=1 enable A2 match */
+	/* value32 = platform_efio_read_4byte(adapter, 0x7B4); */
+	/* platform_efio_write_4byte(adapter, 0x7b4, value32|BIT(18));	 */ /* append MACID in reponse packet */
+
+	/* @Match MAC ADDR */
+	odm_set_mac_reg(dm, R_0x7b4, 0xFFFF, 0);
+	odm_set_mac_reg(dm, R_0x7b0, MASKDWORD, 0);
+
+	odm_set_bb_reg(dm, R_0x870, BIT(9) | BIT(8), 0); /* reg870[8]=1'b0, reg870[9]=1'b0		 */ /* antsel antselb by HW */
+	odm_set_bb_reg(dm, R_0x864, BIT(10), 0); /* reg864[10]=1'b0	 */ /* antsel2 by HW */
+	odm_set_bb_reg(dm, R_0xb2c, BIT(22), 0); /* regb2c[22]=1'b0	 */ /* disable CS/CG switch */
+	odm_set_bb_reg(dm, R_0xb2c, BIT(31), 0); /* regb2c[31]=1'b1	 */ /* output at CS only */
+	odm_set_bb_reg(dm, R_0xca4, MASKDWORD, 0x000000a0);
+
+	/* @antenna mapping table */
+	if (dm->fat_comb_a == 2) {
+		if (!dm->is_mp_chip) { /* testchip */
+			odm_set_bb_reg(dm, R_0x858, BIT(10) | BIT(9) | BIT(8), 1); /* Reg858[10:8]=3'b001 */
+			odm_set_bb_reg(dm, R_0x858, BIT(13) | BIT(12) | BIT(11), 2); /* Reg858[13:11]=3'b010 */
+		} else { /* @MPchip */
+			odm_set_bb_reg(dm, R_0x914, MASKBYTE0, 1);
+			odm_set_bb_reg(dm, R_0x914, MASKBYTE1, 2);
+		}
+	} else {
+		if (!dm->is_mp_chip) { /* testchip */
+			odm_set_bb_reg(dm, R_0x858, BIT(10) | BIT(9) | BIT(8), 0); /* Reg858[10:8]=3'b000 */
+			odm_set_bb_reg(dm, R_0x858, BIT(13) | BIT(12) | BIT(11), 1); /* Reg858[13:11]=3'b001 */
+			odm_set_bb_reg(dm, R_0x878, BIT(16), 0);
+			odm_set_bb_reg(dm, R_0x858, BIT(15) | BIT(14), 2); /* @(Reg878[0],Reg858[14:15])=3'b010 */
+			odm_set_bb_reg(dm, R_0x878, BIT(19) | BIT(18) | BIT(17), 3); /* Reg878[3:1]=3b'011 */
+			odm_set_bb_reg(dm, R_0x878, BIT(22) | BIT(21) | BIT(20), 4); /* Reg878[6:4]=3b'100 */
+			odm_set_bb_reg(dm, R_0x878, BIT(25) | BIT(24) | BIT(23), 5); /* Reg878[9:7]=3b'101 */
+			odm_set_bb_reg(dm, R_0x878, BIT(28) | BIT(27) | BIT(26), 6); /* Reg878[12:10]=3b'110 */
+			odm_set_bb_reg(dm, R_0x878, BIT(31) | BIT(30) | BIT(29), 7); /* Reg878[15:13]=3b'111 */
+		} else { /* @MPchip */
+			odm_set_bb_reg(dm, R_0x914, MASKBYTE0, 4); /* @0: 3b'000 */
+			odm_set_bb_reg(dm, R_0x914, MASKBYTE1, 2); /* @1: 3b'001 */
+			odm_set_bb_reg(dm, R_0x914, MASKBYTE2, 0); /* @2: 3b'010 */
+			odm_set_bb_reg(dm, R_0x914, MASKBYTE3, 1); /* @3: 3b'011 */
+			odm_set_bb_reg(dm, R_0x918, MASKBYTE0, 3); /* @4: 3b'100 */
+			odm_set_bb_reg(dm, R_0x918, MASKBYTE1, 5); /* @5: 3b'101 */
+			odm_set_bb_reg(dm, R_0x918, MASKBYTE2, 6); /* @6: 3b'110 */
+			odm_set_bb_reg(dm, R_0x918, MASKBYTE3, 255); /* @7: 3b'111 */
+		}
+	}
+
+	/* @Default ant setting when no fast training */
+	odm_set_bb_reg(dm, R_0x864, BIT(5) | BIT(4) | BIT(3), 0); /* @Default RX */
+	odm_set_bb_reg(dm, R_0x864, BIT(8) | BIT(7) | BIT(6), 1); /* Optional RX */
+	odm_set_bb_reg(dm, R_0x860, BIT(14) | BIT(13) | BIT(12), 0); /* @Default TX */
+
+	/* @Enter Traing state */
+	odm_set_bb_reg(dm, R_0x864, BIT(2) | BIT(1) | BIT(0), (dm->fat_comb_a - 1)); /* reg864[2:0]=3'd6	 */ /* ant combination=reg864[2:0]+1 */
+
+#if 0
+	/* SW Control */
+	/* phy_set_bb_reg(adapter, 0x864, BIT10, 1); */
+	/* phy_set_bb_reg(adapter, 0x870, BIT9, 1); */
+	/* phy_set_bb_reg(adapter, 0x870, BIT8, 1); */
+	/* phy_set_bb_reg(adapter, 0x864, BIT11, 1); */
+	/* phy_set_bb_reg(adapter, 0x860, BIT9, 0); */
+	/* phy_set_bb_reg(adapter, 0x860, BIT8, 0); */
+#endif
+}
+#endif
+
+#endif /* @#if (RTL8188E_SUPPORT == 1) */
+
+#if (RTL8192E_SUPPORT == 1)
+void odm_rx_hw_ant_div_init_92e(
+	void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
+
+#if 0
+	if (*dm->mp_mode == true) {
+		odm_ant_div_on_off(dm, ANTDIV_OFF);
+		odm_set_bb_reg(dm, R_0xc50, BIT(8), 0); /* r_rxdiv_enable_anta  regc50[8]=1'b0  0: control by c50[9] */
+		odm_set_bb_reg(dm, R_0xc50, BIT(9), 1);  /* @1:CG, 0:CS */
+		return;
+	}
+#endif
+
+	PHYDM_DBG(dm, DBG_ANT_DIV,
+		  "***8192E AntDiv_Init =>  ant_div_type=[CGCS_RX_HW_ANTDIV]\n");
+
+	/* Pin Settings */
+	odm_set_bb_reg(dm, R_0x870, BIT(8), 0); /* reg870[8]=1'b0,     */ /* "antsel" is controled by HWs */
+	odm_set_bb_reg(dm, R_0xc50, BIT(8), 1); /* regc50[8]=1'b1   */ /* " CS/CG switching" is controled by HWs */
+
+	/* @Mapping table */
+	odm_set_bb_reg(dm, R_0x914, 0xFFFF, 0x0100); /* @antenna mapping table */
+
+	/* OFDM Settings */
+	odm_set_bb_reg(dm, R_0xca4, 0x7FF, 0xA0); /* thershold */
+	odm_set_bb_reg(dm, R_0xca4, 0x7FF000, 0x0); /* @bias */
+
+	/* @CCK Settings */
+	odm_set_bb_reg(dm, R_0xa04, 0xF000000, 0); /* Select which path to receive for CCK_1 & CCK_2 */
+	odm_set_bb_reg(dm, R_0xb34, BIT(30), 0); /* @(92E) ANTSEL_CCK_opt = r_en_antsel_cck? ANTSEL_CCK: 1'b0 */
+	odm_set_bb_reg(dm, R_0xa74, BIT(7), 1); /* @Fix CCK PHY status report issue */
+	odm_set_bb_reg(dm, R_0xa0c, BIT(4), 1); /* @CCK complete HW AntDiv within 64 samples */
+
+#ifdef ODM_EVM_ENHANCE_ANTDIV
+	phydm_evm_sw_antdiv_init(dm);
+#endif
+}
+
+void odm_trx_hw_ant_div_init_92e(
+	void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+
+#if 0
+	if (*dm->mp_mode == true) {
+		odm_ant_div_on_off(dm, ANTDIV_OFF);
+		odm_set_bb_reg(dm, R_0xc50, BIT(8), 0); /* r_rxdiv_enable_anta  regc50[8]=1'b0  0: control by c50[9] */
+		odm_set_bb_reg(dm, R_0xc50, BIT(9), 1);  /* @1:CG, 0:CS */
+		return;
+	}
+#endif
+
+	PHYDM_DBG(dm, DBG_ANT_DIV,
+		  "***8192E AntDiv_Init =>  ant_div_type=[ Only for DIR605, CG_TRX_HW_ANTDIV]\n");
+
+	/* @3 --RFE pin setting--------- */
+	/* @[MAC] */
+	odm_set_mac_reg(dm, R_0x38, BIT(11), 1); /* @DBG PAD Driving control (GPIO 8) */
+	odm_set_mac_reg(dm, R_0x4c, BIT(23), 0); /* path-A, RFE_CTRL_3 */
+	odm_set_mac_reg(dm, R_0x4c, BIT(29), 1); /* path-A, RFE_CTRL_8 */
+	/* @[BB] */
+	odm_set_bb_reg(dm, R_0x944, BIT(3), 1); /* RFE_buffer */
+	odm_set_bb_reg(dm, R_0x944, BIT(8), 1);
+	odm_set_bb_reg(dm, R_0x940, BIT(7) | BIT(6), 0x0); /* r_rfe_path_sel_   (RFE_CTRL_3) */
+	odm_set_bb_reg(dm, R_0x940, BIT(17) | BIT(16), 0x0); /* r_rfe_path_sel_   (RFE_CTRL_8) */
+	odm_set_bb_reg(dm, R_0x944, BIT(31), 0); /* RFE_buffer */
+	odm_set_bb_reg(dm, R_0x92c, BIT(3), 0); /* rfe_inv  (RFE_CTRL_3) */
+	odm_set_bb_reg(dm, R_0x92c, BIT(8), 1); /* rfe_inv  (RFE_CTRL_8) */
+	odm_set_bb_reg(dm, R_0x930, 0xF000, 0x8); /* path-A, RFE_CTRL_3 */
+	odm_set_bb_reg(dm, R_0x934, 0xF, 0x8); /* path-A, RFE_CTRL_8 */
+	/* @3 ------------------------- */
+
+	/* Pin Settings */
+	odm_set_bb_reg(dm, R_0xc50, BIT(8), 0); /* path-A  	 */ /* disable CS/CG switch */
+
+#if 0
+	/* @Let it follows PHY_REG for bit9 setting */
+	if (dm->priv->pshare->rf_ft_var.use_ext_pa || dm->priv->pshare->rf_ft_var.use_ext_lna)
+		odm_set_bb_reg(dm, R_0xc50, BIT(9), 1);	/* path-A 	output at CS */
+	else
+		odm_set_bb_reg(dm, R_0xc50, BIT(9), 0);	/* path-A 	output at CG ->normal power */
+#endif
+
+	odm_set_bb_reg(dm, R_0x870, BIT(9) | BIT(8), 0); /* path-A*/ /* antsel antselb by HW */
+	odm_set_bb_reg(dm, R_0xb38, BIT(10), 0); /* path-A	*/ /* antsel2 by HW */
+
+	/* @Mapping table */
+	odm_set_bb_reg(dm, R_0x914, 0xFFFF, 0x0100); /* @antenna mapping table */
+
+	/* OFDM Settings */
+	odm_set_bb_reg(dm, R_0xca4, 0x7FF, 0xA0); /* thershold */
+	odm_set_bb_reg(dm, R_0xca4, 0x7FF000, 0x0); /* @bias */
+
+	/* @CCK Settings */
+	odm_set_bb_reg(dm, R_0xa04, 0xF000000, 0); /* Select which path to receive for CCK_1 & CCK_2 */
+	odm_set_bb_reg(dm, R_0xb34, BIT(30), 0); /* @(92E) ANTSEL_CCK_opt = r_en_antsel_cck? ANTSEL_CCK: 1'b0 */
+	odm_set_bb_reg(dm, R_0xa74, BIT(7), 1); /* @Fix CCK PHY status report issue */
+	odm_set_bb_reg(dm, R_0xa0c, BIT(4), 1); /* @CCK complete HW AntDiv within 64 samples */
+
+#ifdef ODM_EVM_ENHANCE_ANTDIV
+	phydm_evm_sw_antdiv_init(dm);
+#endif
+}
+
+#if (defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY)) || (defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY))
+void odm_smart_hw_ant_div_init_92e(
+	void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+
+	PHYDM_DBG(dm, DBG_ANT_DIV,
+		  "***8192E AntDiv_Init =>  ant_div_type=[CG_TRX_SMART_ANTDIV]\n");
+}
+#endif
+
+#endif /* @#if (RTL8192E_SUPPORT == 1) */
+
+#if (RTL8192F_SUPPORT == 1)
+void odm_rx_hw_ant_div_init_92f(
+	void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
+
+	PHYDM_DBG(dm, DBG_ANT_DIV,
+		  "***8192F AntDiv_Init =>  ant_div_type=[CGCS_RX_HW_ANTDIV]\n");
+
+	/* Pin Settings */
+	odm_set_bb_reg(dm, R_0x870, BIT(8), 0); /* reg870[8]=1'b0, "antsel" is controlled by HWs */
+	odm_set_bb_reg(dm, R_0xc50, BIT(8), 1); /* regc50[8]=1'b1, " CS/CG switching" is controlled by HWs */
+
+	/* @Mapping table */
+	odm_set_bb_reg(dm, R_0x914, 0xFFFF, 0x0100); /* @antenna mapping table */
+
+	/* OFDM Settings */
+	odm_set_bb_reg(dm, R_0xca4, 0x7FF, 0xA0); /* thershold */
+	odm_set_bb_reg(dm, R_0xca4, 0x7FF000, 0x0); /* @bias */
+
+	/* @CCK Settings */
+	odm_set_bb_reg(dm, R_0xa04, 0xF000000, 0); /* Select which path to receive for CCK_1 & CCK_2 */
+	odm_set_bb_reg(dm, R_0xb34, BIT(30), 0); /* @(92E) ANTSEL_CCK_opt = r_en_antsel_cck? ANTSEL_CCK: 1'b0 */
+	odm_set_bb_reg(dm, R_0xa74, BIT(7), 1); /* @Fix CCK PHY status report issue */
+	odm_set_bb_reg(dm, R_0xa0c, BIT(4), 1); /* @CCK complete HW AntDiv within 64 samples */
+
+#ifdef ODM_EVM_ENHANCE_ANTDIV
+	phydm_evm_sw_antdiv_init(dm);
+#endif
+}
+
+void odm_trx_hw_ant_div_init_92f(
+	void *dm_void)
+
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+
+	PHYDM_DBG(dm, DBG_ANT_DIV,
+		  "***8192F AntDiv_Init =>  ant_div_type=[ Only for DIR605, CG_TRX_HW_ANTDIV]\n");
+	/* @3 --RFE pin setting--------- */
+	/* @[MAC] */
+	odm_set_mac_reg(dm, R_0x1048, BIT(0), 1); /* @DBG PAD Driving control (gpioA_0) */
+	odm_set_mac_reg(dm, R_0x1048, BIT(1), 1); /* @DBG PAD Driving control (gpioA_1) */
+	odm_set_mac_reg(dm, R_0x4c, BIT(24), 1);
+	odm_set_mac_reg(dm, R_0x1038, BIT(25) | BIT(24) | BIT(23), 0); /* @gpioA_0,gpioA_1*/
+	odm_set_mac_reg(dm, R_0x4c, BIT(23), 0);
+	/* @[BB] */
+	odm_set_bb_reg(dm, R_0x944, BIT(8), 1); /* output enable */
+	odm_set_bb_reg(dm, R_0x944, BIT(9), 1);
+	odm_set_bb_reg(dm, R_0x940, BIT(16) | BIT(17), 0x0); /* r_rfe_path_sel_   (RFE_CTRL_8) */
+	odm_set_bb_reg(dm, R_0x940, BIT(18) | BIT(19), 0x0); /* r_rfe_path_sel_   (RFE_CTRL_9) */
+	odm_set_bb_reg(dm, R_0x944, BIT(31), 0); /* RFE_buffer_en */
+	odm_set_bb_reg(dm, R_0x92c, BIT(8), 0); /* rfe_inv  (RFE_CTRL_8) */
+	odm_set_bb_reg(dm, R_0x92c, BIT(9), 1); /* rfe_inv  (RFE_CTRL_9) */
+	odm_set_bb_reg(dm, R_0x934, 0xF, 0x8); /* path-A, RFE_CTRL_8 */
+	odm_set_bb_reg(dm, R_0x934, 0xF0, 0x8); /* path-A, RFE_CTRL_9 */
+	/* @3 ------------------------- */
+
+	/* Pin Settings */
+	odm_set_bb_reg(dm, R_0xc50, BIT(8), 0);/* path-A,disable CS/CG switch */
+	odm_set_bb_reg(dm, R_0x870, BIT(9) | BIT(8), 0); /* path-A*, antsel antselb by HW */
+	odm_set_bb_reg(dm, R_0xb38, BIT(10), 0); /* path-A ,antsel2 by HW */
+
+	/* @Mapping table */
+	odm_set_bb_reg(dm, R_0x914, 0xFFFF, 0x0100); /* @antenna mapping table */
+
+	/* OFDM Settings */
+	odm_set_bb_reg(dm, R_0xca4, 0x7FF, 0xA0); /* thershold */
+	odm_set_bb_reg(dm, R_0xca4, 0x7FF000, 0x0); /* @bias */
+
+	/* @CCK Settings */
+	odm_set_bb_reg(dm, R_0xa04, 0xF000000, 0); /* Select which path to receive for CCK_1 & CCK_2 */
+	odm_set_bb_reg(dm, R_0xb34, BIT(30), 0); /* @(92E) ANTSEL_CCK_opt = r_en_antsel_cck? ANTSEL_CCK: 1'b0 */
+	odm_set_bb_reg(dm, R_0xa74, BIT(7), 1); /* @Fix CCK PHY status report issue */
+	odm_set_bb_reg(dm, R_0xa0c, BIT(4), 1); /* @CCK complete HW AntDiv within 64 samples */
+
+#ifdef ODM_EVM_ENHANCE_ANTDIV
+	phydm_evm_sw_antdiv_init(dm);
+#endif
+}
+
+#endif /* @#if (RTL8192F_SUPPORT == 1) */
+
+#if (RTL8822B_SUPPORT == 1)
+void phydm_trx_hw_ant_div_init_22b(
+	void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+
+	PHYDM_DBG(dm, DBG_ANT_DIV,
+		  "***8822B AntDiv_Init =>  ant_div_type=[CG_TRX_HW_ANTDIV]\n");
+
+	/* Pin Settings */
+	odm_set_bb_reg(dm, R_0xcb8, BIT(21) | BIT(20), 0x1);
+	odm_set_bb_reg(dm, R_0xcb8, BIT(23) | BIT(22), 0x1);
+	odm_set_bb_reg(dm, R_0xc1c, BIT(7) | BIT(6), 0x0);
+	/* @------------------------- */
+
+	/* @Mapping table */
+	/* @antenna mapping table */
+	odm_set_bb_reg(dm, R_0xca4, 0xFFFF, 0x0100);
+
+	/* OFDM Settings */
+	/* thershold */
+	odm_set_bb_reg(dm, R_0x8d4, 0x7FF, 0xA0);
+	/* @bias */
+	odm_set_bb_reg(dm, R_0x8d4, 0x7FF000, 0x0);
+	odm_set_bb_reg(dm, R_0x668, BIT(3), 0x1);
+
+	/* @CCK Settings */
+	/* Select which path to receive for CCK_1 & CCK_2 */
+	odm_set_bb_reg(dm, R_0xa04, 0xF000000, 0);
+	/* @Fix CCK PHY status report issue */
+	odm_set_bb_reg(dm, R_0xa74, BIT(7), 1);
+	/* @CCK complete HW AntDiv within 64 samples */
+	odm_set_bb_reg(dm, R_0xa0c, BIT(4), 1);
+	/* @BT Coexistence */
+	/* @keep antsel_map when GNT_BT = 1 */
+	odm_set_bb_reg(dm, R_0xcac, BIT(9), 1);
+	/* @Disable hw antsw & fast_train.antsw when GNT_BT=1 */
+	odm_set_bb_reg(dm, R_0x804, BIT(4), 1);
+	/* response TX ant by RX ant */
+	odm_set_mac_reg(dm, R_0x668, BIT(3), 1);
+#if (defined(CONFIG_2T4R_ANTENNA))
+	PHYDM_DBG(dm, DBG_ANT_DIV,
+		  "***8822B AntDiv_Init =>  2T4R case\n");
+	/* Pin Settings */
+	odm_set_bb_reg(dm, R_0xeb8, BIT(21) | BIT(20), 0x1);
+	odm_set_bb_reg(dm, R_0xeb8, BIT(23) | BIT(22), 0x1);
+	odm_set_bb_reg(dm, R_0xe1c, BIT(7) | BIT(6), 0x0);
+	/* @BT Coexistence */
+	odm_set_bb_reg(dm, R_0xeac, BIT(9), 1);
+	/* @keep antsel_map when GNT_BT = 1 */
+	/* Mapping table */
+	/* antenna mapping table */
+	odm_set_bb_reg(dm, R_0xea4, 0xFFFF, 0x0100);
+	/*odm_set_bb_reg(dm, R_0x900, 0x30000, 0x3);*/
+#endif
+
+#ifdef ODM_EVM_ENHANCE_ANTDIV
+	phydm_evm_sw_antdiv_init(dm);
+#endif
+}
+#endif /* @#if (RTL8822B_SUPPORT == 1) */
+
+#if (RTL8197F_SUPPORT == 1)
+void phydm_rx_hw_ant_div_init_97f(
+	void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
+
+#if 0
+	if (*dm->mp_mode == true) {
+		odm_ant_div_on_off(dm, ANTDIV_OFF);
+		odm_set_bb_reg(dm, R_0xc50, BIT(8), 0); /* r_rxdiv_enable_anta  regc50[8]=1'b0  0: control by c50[9] */
+		odm_set_bb_reg(dm, R_0xc50, BIT(9), 1);  /* @1:CG, 0:CS */
+		return;
+	}
+#endif
+	PHYDM_DBG(dm, DBG_ANT_DIV,
+		  "***8197F AntDiv_Init =>  ant_div_type=[CGCS_RX_HW_ANTDIV]\n");
+
+	/* Pin Settings */
+	odm_set_bb_reg(dm, R_0x870, BIT(8), 0); /* reg870[8]=1'b0,     */ /* "antsel" is controlled by HWs */
+	odm_set_bb_reg(dm, R_0xc50, BIT(8), 1); /* regc50[8]=1'b1   */ /* " CS/CG switching" is controlled by HWs */
+
+	/* @Mapping table */
+	odm_set_bb_reg(dm, R_0x914, 0xFFFF, 0x0100); /* @antenna mapping table */
+
+	/* OFDM Settings */
+	odm_set_bb_reg(dm, R_0xca4, 0x7FF, 0xA0); /* thershold */
+	odm_set_bb_reg(dm, R_0xca4, 0x7FF000, 0x0); /* @bias */
+
+	/* @CCK Settings */
+	odm_set_bb_reg(dm, R_0xa04, 0xF000000, 0); /* Select which path to receive for CCK_1 & CCK_2 */
+	odm_set_bb_reg(dm, R_0xb34, BIT(30), 0); /* @(92E) ANTSEL_CCK_opt = r_en_antsel_cck? ANTSEL_CCK: 1'b0 */
+	odm_set_bb_reg(dm, R_0xa74, BIT(7), 1); /* @Fix CCK PHY status report issue */
+	odm_set_bb_reg(dm, R_0xa0c, BIT(4), 1); /* @CCK complete HW AntDiv within 64 samples */
+
+#ifdef ODM_EVM_ENHANCE_ANTDIV
+	phydm_evm_sw_antdiv_init(dm);
+#endif
+}
+
+#endif //#if (RTL8197F_SUPPORT == 1)
+#if (RTL8723D_SUPPORT == 1)
+void odm_trx_hw_ant_div_init_8723d(
+	void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+
+	PHYDM_DBG(dm, DBG_ANT_DIV,
+		  "[8723D] AntDiv_Init =>  ant_div_type=[S0S1_HW_TRX_AntDiv]\n");
+
+	/*@BT Coexistence*/
+	/*@keep antsel_map when GNT_BT = 1*/
+	odm_set_bb_reg(dm, R_0x864, BIT(12), 1);
+	/* @Disable hw antsw & fast_train.antsw when GNT_BT=1 */
+	odm_set_bb_reg(dm, R_0x874, BIT(23), 0);
+	/* @Disable hw antsw & fast_train.antsw when BT TX/RX */
+	odm_set_bb_reg(dm, R_0xe64, 0xFFFF0000, 0x000c);
+
+	odm_set_bb_reg(dm, R_0x870, BIT(9) | BIT(8), 0);
+#if 0
+	/*PTA setting: WL_BB_SEL_BTG_TRXG_anta,  (1: HW CTRL  0: SW CTRL)*/
+	/*odm_set_bb_reg(dm, R_0x948, BIT6, 0);*/
+	/*odm_set_bb_reg(dm, R_0x948, BIT8, 0);*/
+#endif
+	/*@GNT_WL tx*/
+	odm_set_bb_reg(dm, R_0x950, BIT(29), 0);
+
+	/*@Mapping Table*/
+	odm_set_bb_reg(dm, R_0x914, MASKBYTE0, 0);
+	odm_set_bb_reg(dm, R_0x914, MASKBYTE1, 3);
+#if 0
+	/* odm_set_bb_reg(dm, R_0x864, BIT5|BIT4|BIT3, 0); */
+	/* odm_set_bb_reg(dm, R_0x864, BIT8|BIT7|BIT6, 1); */
+#endif
+
+	/* Set WLBB_SEL_RF_ON 1 if RXFIR_PWDB > 0xCcc[3:0] */
+	odm_set_bb_reg(dm, R_0xccc, BIT(12), 0);
+	/* @Low-to-High threshold for WLBB_SEL_RF_ON when OFDM enable */
+	odm_set_bb_reg(dm, R_0xccc, 0x0F, 0x01);
+	/* @High-to-Low threshold for WLBB_SEL_RF_ON when OFDM enable */
+	odm_set_bb_reg(dm, R_0xccc, 0xF0, 0x0);
+	/* @b Low-to-High threshold for WLBB_SEL_RF_ON when OFDM disable ( only CCK ) */
+	odm_set_bb_reg(dm, R_0xabc, 0xFF, 0x06);
+	/* @High-to-Low threshold for WLBB_SEL_RF_ON when OFDM disable ( only CCK ) */
+	odm_set_bb_reg(dm, R_0xabc, 0xFF00, 0x00);
+
+	/*OFDM HW AntDiv Parameters*/
+	odm_set_bb_reg(dm, R_0xca4, 0x7FF, 0xa0);
+	odm_set_bb_reg(dm, R_0xca4, 0x7FF000, 0x00);
+	odm_set_bb_reg(dm, R_0xc5c, BIT(20) | BIT(19) | BIT(18), 0x04);
+
+	/*@CCK HW AntDiv Parameters*/
+	odm_set_bb_reg(dm, R_0xa74, BIT(7), 1);
+	odm_set_bb_reg(dm, R_0xa0c, BIT(4), 1);
+	odm_set_bb_reg(dm, R_0xaa8, BIT(8), 0);
+
+	odm_set_bb_reg(dm, R_0xa0c, 0x0F, 0xf);
+	odm_set_bb_reg(dm, R_0xa14, 0x1F, 0x8);
+	odm_set_bb_reg(dm, R_0xa10, BIT(13), 0x1);
+	odm_set_bb_reg(dm, R_0xa74, BIT(8), 0x0);
+	odm_set_bb_reg(dm, R_0xb34, BIT(30), 0x1);
+
+	/*@disable antenna training	*/
+	odm_set_bb_reg(dm, R_0xe08, BIT(16), 0);
+	odm_set_bb_reg(dm, R_0xc50, BIT(8), 0);
+}
+/*@Mingzhi 2017-05-08*/
+
+void odm_s0s1_sw_ant_div_init_8723d(
+	void		*dm_void
+)
+{
+	struct dm_struct		*dm = (struct dm_struct *)dm_void;
+	struct sw_antenna_switch	*dm_swat_table = &dm->dm_swat_table;
+	struct phydm_fat_struct		*fat_tab = &dm->dm_fat_table;
+
+	PHYDM_DBG(dm, DBG_ANT_DIV,
+		  "***8723D AntDiv_Init => ant_div_type=[ S0S1_SW_AntDiv]\n");
+
+	/*@keep antsel_map when GNT_BT = 1*/
+	odm_set_bb_reg(dm, R_0x864, BIT(12), 1);
+
+	/* @Disable antsw when GNT_BT=1 */
+	odm_set_bb_reg(dm, R_0x874, BIT(23), 0);
+
+	/* @Mapping Table */
+	odm_set_bb_reg(dm, R_0x914, MASKBYTE0, 0);
+	odm_set_bb_reg(dm, R_0x914, MASKBYTE1, 1);
+
+	/* Output Pin Settings */
+#if 0
+	/* odm_set_bb_reg(dm, R_0x948, BIT6, 0x1); */
+#endif
+	odm_set_bb_reg(dm, R_0x870, BIT(8), 1);
+	odm_set_bb_reg(dm, R_0x870, BIT(9), 1);
+
+	/* Status init */
+	fat_tab->is_become_linked  = false;
+	dm_swat_table->try_flag = SWAW_STEP_INIT;
+	dm_swat_table->double_chk_flag = 0;
+	dm_swat_table->cur_antenna = MAIN_ANT;
+	dm_swat_table->pre_antenna = MAIN_ANT;
+	dm->antdiv_counter = CONFIG_ANTENNA_DIVERSITY_PERIOD;
+
+	/* @2 [--For HW Bug setting] */
+	odm_set_bb_reg(dm, R_0x80c, BIT(21), 0); /* TX ant  by Reg */
+}
+
+void odm_update_rx_idle_ant_8723d(
+	void *dm_void,
+	u8 ant,
+	u32 default_ant,
+	u32 optional_ant)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
+	void *adapter = dm->adapter;
+	u8 count = 0;
+
+#if (DM_ODM_SUPPORT_TYPE & (ODM_CE))
+	/*score board to BT ,a002:WL to do ant-div*/
+	odm_set_mac_reg(dm, R_0xa8, MASKHWORD, 0xa002);
+	ODM_delay_us(50);
+#endif
+#if 0
+	/*	odm_set_bb_reg(dm, R_0x948, BIT(6), 0x1);	*/
+#endif
+	if (dm->ant_div_type == S0S1_SW_ANTDIV) {
+	odm_set_bb_reg(dm, R_0x860, BIT(8), default_ant);
+	odm_set_bb_reg(dm, R_0x860, BIT(9), default_ant);
+	}
+	odm_set_bb_reg(dm, R_0x864, BIT(5) | BIT(4) | BIT(3), default_ant); /*@Default RX*/
+	odm_set_bb_reg(dm, R_0x864, BIT(8) | BIT(7) | BIT(6), optional_ant); /*Optional RX*/
+	odm_set_bb_reg(dm, R_0x860, BIT(14) | BIT(13) | BIT(12), default_ant); /*@Default TX*/
+	fat_tab->rx_idle_ant = ant;
+#if (DM_ODM_SUPPORT_TYPE & (ODM_CE))
+	/*score board to BT ,a000:WL@S1 a001:WL@S0*/
+	if (default_ant == ANT1_2G)
+		odm_set_mac_reg(dm, R_0xa8, MASKHWORD, 0xa000);
+	else
+		odm_set_mac_reg(dm, R_0xa8, MASKHWORD, 0xa001);
+#endif
+}
+
+void phydm_set_tx_ant_pwr_8723d(
+	void *dm_void,
+	u8 ant)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
+	void *adapter = dm->adapter;
+
+	fat_tab->rx_idle_ant = ant;
+
+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
+	((PADAPTER)adapter)->HalFunc.SetTxPowerLevelHandler(adapter, *dm->channel);
+#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
+	rtw_hal_set_tx_power_level(adapter, *dm->channel);
+#endif
+}
+#endif
+
+#if (RTL8723B_SUPPORT == 1)
+void odm_trx_hw_ant_div_init_8723b(
+	void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+
+	PHYDM_DBG(dm, DBG_ANT_DIV,
+		  "***8723B AntDiv_Init =>  ant_div_type=[CG_TRX_HW_ANTDIV(DPDT)]\n");
+
+	/* @Mapping Table */
+	odm_set_bb_reg(dm, R_0x914, MASKBYTE0, 0);
+	odm_set_bb_reg(dm, R_0x914, MASKBYTE1, 1);
+
+	/* OFDM HW AntDiv Parameters */
+	odm_set_bb_reg(dm, R_0xca4, 0x7FF, 0xa0); /* thershold */
+	odm_set_bb_reg(dm, R_0xca4, 0x7FF000, 0x00); /* @bias */
+
+	/* @CCK HW AntDiv Parameters */
+	odm_set_bb_reg(dm, R_0xa74, BIT(7), 1); /* patch for clk from 88M to 80M */
+	odm_set_bb_reg(dm, R_0xa0c, BIT(4), 1); /* @do 64 samples */
+
+	/* @BT Coexistence */
+	odm_set_bb_reg(dm, R_0x864, BIT(12), 0); /* @keep antsel_map when GNT_BT = 1 */
+	odm_set_bb_reg(dm, R_0x874, BIT(23), 0); /* @Disable hw antsw & fast_train.antsw when GNT_BT=1 */
+
+	/* Output Pin Settings */
+	odm_set_bb_reg(dm, R_0x870, BIT(8), 0);
+
+	odm_set_bb_reg(dm, R_0x948, BIT(6), 0); /* WL_BB_SEL_BTG_TRXG_anta,  (1: HW CTRL  0: SW CTRL) */
+	odm_set_bb_reg(dm, R_0x948, BIT(7), 0);
+
+	odm_set_mac_reg(dm, R_0x40, BIT(3), 1);
+	odm_set_mac_reg(dm, R_0x38, BIT(11), 1);
+	odm_set_mac_reg(dm, R_0x4c, BIT(24) | BIT(23), 2); /* select DPDT_P and DPDT_N as output pin */
+
+	odm_set_bb_reg(dm, R_0x944, BIT(0) | BIT(1), 3); /* @in/out */
+	odm_set_bb_reg(dm, R_0x944, BIT(31), 0);
+
+	odm_set_bb_reg(dm, R_0x92c, BIT(1), 0); /* @DPDT_P non-inverse */
+	odm_set_bb_reg(dm, R_0x92c, BIT(0), 1); /* @DPDT_N inverse */
+
+	odm_set_bb_reg(dm, R_0x930, 0xF0, 8); /* @DPDT_P = ANTSEL[0] */
+	odm_set_bb_reg(dm, R_0x930, 0xF, 8); /* @DPDT_N = ANTSEL[0] */
+
+	/* @2 [--For HW Bug setting] */
+	if (dm->ant_type == ODM_AUTO_ANT)
+		odm_set_bb_reg(dm, R_0xa00, BIT(15), 0); /* @CCK AntDiv function block enable */
+}
+
+void odm_s0s1_sw_ant_div_init_8723b(
+	void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct sw_antenna_switch *dm_swat_table = &dm->dm_swat_table;
+	struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
+
+	PHYDM_DBG(dm, DBG_ANT_DIV,
+		  "***8723B AntDiv_Init => ant_div_type=[ S0S1_SW_AntDiv]\n");
+
+	/* @Mapping Table */
+	odm_set_bb_reg(dm, R_0x914, MASKBYTE0, 0);
+	odm_set_bb_reg(dm, R_0x914, MASKBYTE1, 1);
+
+#if 0
+	/* Output Pin Settings */
+	/* odm_set_bb_reg(dm, R_0x948, BIT6, 0x1); */
+#endif
+	odm_set_bb_reg(dm, R_0x870, BIT(9) | BIT(8), 0);
+
+	fat_tab->is_become_linked = false;
+	dm_swat_table->try_flag = SWAW_STEP_INIT;
+	dm_swat_table->double_chk_flag = 0;
+
+	/* @2 [--For HW Bug setting] */
+	odm_set_bb_reg(dm, R_0x80c, BIT(21), 0); /* TX ant  by Reg */
+}
+
+void odm_update_rx_idle_ant_8723b(
+	void *dm_void,
+	u8 ant,
+	u32 default_ant,
+	u32 optional_ant)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
+	void *adapter = dm->adapter;
+	u8 count = 0;
+	/*u8			u1_temp;*/
+	/*u8			h2c_parameter;*/
+
+	if (!dm->is_linked && dm->ant_type == ODM_AUTO_ANT) {
+		PHYDM_DBG(dm, DBG_ANT_DIV,
+			  "[ Update Rx-Idle-ant ] 8723B: Fail to set RX antenna due to no link\n");
+		return;
+	}
+
+#if 0
+	/* Send H2C command to FW */
+	/* @Enable wifi calibration */
+	h2c_parameter = true;
+	odm_fill_h2c_cmd(dm, ODM_H2C_WIFI_CALIBRATION, 1, &h2c_parameter);
+
+	/* @Check if H2C command sucess or not (0x1e6) */
+	u1_temp = odm_read_1byte(dm, 0x1e6);
+	while ((u1_temp != 0x1) && (count < 100)) {
+		ODM_delay_us(10);
+		u1_temp = odm_read_1byte(dm, 0x1e6);
+		count++;
+	}
+	PHYDM_DBG(dm, DBG_ANT_DIV,
+		  "[ Update Rx-Idle-ant ] 8723B: H2C command status = %d, count = %d\n",
+		  u1_temp, count);
+
+	if (u1_temp == 0x1) {
+		/* @Check if BT is doing IQK (0x1e7) */
+		count = 0;
+		u1_temp = odm_read_1byte(dm, 0x1e7);
+		while ((!(u1_temp & BIT(0)))  && (count < 100)) {
+			ODM_delay_us(50);
+			u1_temp = odm_read_1byte(dm, 0x1e7);
+			count++;
+		}
+		PHYDM_DBG(dm, DBG_ANT_DIV,
+			  "[ Update Rx-Idle-ant ] 8723B: BT IQK status = %d, count = %d\n",
+			  u1_temp, count);
+
+		if (u1_temp & BIT(0)) {
+			odm_set_bb_reg(dm, R_0x948, BIT(6), 0x1);
+			odm_set_bb_reg(dm, R_0x948, BIT(9), default_ant);
+			odm_set_bb_reg(dm, R_0x864, BIT(5) | BIT4 | BIT3, default_ant);	/* @Default RX */
+			odm_set_bb_reg(dm, R_0x864, BIT(8) | BIT7 | BIT6, optional_ant);	/* Optional RX */
+			odm_set_bb_reg(dm, R_0x860, BIT(14) | BIT13 | BIT12, default_ant); /* @Default TX */
+			fat_tab->rx_idle_ant = ant;
+
+			/* Set TX AGC by S0/S1 */
+			/* Need to consider Linux driver */
+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
+			adapter->hal_func.set_tx_power_level_handler(adapter, *dm->channel);
+#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
+			rtw_hal_set_tx_power_level(adapter, *dm->channel);
+#endif
+
+			/* Set IQC by S0/S1 */
+			odm_set_iqc_by_rfpath(dm, default_ant);
+			PHYDM_DBG(dm, DBG_ANT_DIV,
+				  "[ Update Rx-Idle-ant ] 8723B: Success to set RX antenna\n");
+		} else
+			PHYDM_DBG(dm, DBG_ANT_DIV,
+				  "[ Update Rx-Idle-ant ] 8723B: Fail to set RX antenna due to BT IQK\n");
+	} else
+		PHYDM_DBG(dm, DBG_ANT_DIV,
+			  "[ Update Rx-Idle-ant ] 8723B: Fail to set RX antenna due to H2C command fail\n");
+
+	/* Send H2C command to FW */
+	/* @Disable wifi calibration */
+	h2c_parameter = false;
+	odm_fill_h2c_cmd(dm, ODM_H2C_WIFI_CALIBRATION, 1, &h2c_parameter);
+#else
+
+	odm_set_bb_reg(dm, R_0x948, BIT(6), 0x1);
+	odm_set_bb_reg(dm, R_0x948, BIT(9), default_ant);
+	odm_set_bb_reg(dm, R_0x864, BIT(5) | BIT(4) | BIT(3), default_ant); /*@Default RX*/
+	odm_set_bb_reg(dm, R_0x864, BIT(8) | BIT(7) | BIT(6), optional_ant); /*Optional RX*/
+	odm_set_bb_reg(dm, R_0x860, BIT(14) | BIT(13) | BIT(12), default_ant); /*@Default TX*/
+	fat_tab->rx_idle_ant = ant;
+
+/* Set TX AGC by S0/S1 */
+/* Need to consider Linux driver */
+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
+	((PADAPTER)adapter)->HalFunc.SetTxPowerLevelHandler(adapter, *dm->channel);
+#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
+	rtw_hal_set_tx_power_level(adapter, *dm->channel);
+#endif
+
+	/* Set IQC by S0/S1 */
+	odm_set_iqc_by_rfpath(dm, default_ant);
+	PHYDM_DBG(dm, DBG_ANT_DIV,
+		  "[ Update Rx-Idle-ant ] 8723B: Success to set RX antenna\n");
+
+#endif
+}
+
+boolean
+phydm_is_bt_enable_8723b(
+	void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	u32 bt_state;
+#if 0
+	/*u32			reg75;*/
+
+	/*reg75 = odm_get_bb_reg(dm, R_0x74, BIT8);*/
+	/*odm_set_bb_reg(dm, R_0x74, BIT8, 0x0);*/
+#endif
+	odm_set_bb_reg(dm, R_0xa0, BIT(24) | BIT(25) | BIT(26), 0x5);
+	bt_state = odm_get_bb_reg(dm, R_0xa0, (BIT(3) | BIT(2) | BIT(1) | BIT(0)));
+#if 0
+	/*odm_set_bb_reg(dm, R_0x74, BIT8, reg75);*/
+#endif
+
+	if (bt_state == 4 || bt_state == 7 || bt_state == 9 || bt_state == 13)
+		return true;
+	else
+		return false;
+}
+#endif /* @#if (RTL8723B_SUPPORT == 1) */
+
+#if (RTL8821A_SUPPORT == 1)
+
+void odm_trx_hw_ant_div_init_8821a(
+	void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+
+	PHYDM_DBG(dm, DBG_ANT_DIV,
+		  "***8821A AntDiv_Init => ant_div_type=[ CG_TRX_HW_ANTDIV (DPDT)]\n");
+
+	/* Output Pin Settings */
+	odm_set_mac_reg(dm, R_0x4c, BIT(25), 0);
+
+	odm_set_mac_reg(dm, R_0x64, BIT(29), 1); /* PAPE by WLAN control */
+	odm_set_mac_reg(dm, R_0x64, BIT(28), 1); /* @LNAON by WLAN control */
+
+	odm_set_bb_reg(dm, R_0xcb8, BIT(16), 0);
+
+	odm_set_mac_reg(dm, R_0x4c, BIT(23), 0); /* select DPDT_P and DPDT_N as output pin */
+	odm_set_mac_reg(dm, R_0x4c, BIT(24), 1); /* @by WLAN control */
+	odm_set_bb_reg(dm, R_0xcb4, 0xF, 8); /* @DPDT_P = ANTSEL[0] */
+	odm_set_bb_reg(dm, R_0xcb4, 0xF0, 8); /* @DPDT_N = ANTSEL[0] */
+	odm_set_bb_reg(dm, R_0xcb4, BIT(29), 0); /* @DPDT_P non-inverse */
+	odm_set_bb_reg(dm, R_0xcb4, BIT(28), 1); /* @DPDT_N inverse */
+
+	/* @Mapping Table */
+	odm_set_bb_reg(dm, R_0xca4, MASKBYTE0, 0);
+	odm_set_bb_reg(dm, R_0xca4, MASKBYTE1, 1);
+
+	/* OFDM HW AntDiv Parameters */
+	odm_set_bb_reg(dm, R_0x8d4, 0x7FF, 0xA0); /* thershold */
+	odm_set_bb_reg(dm, R_0x8d4, 0x7FF000, 0x10); /* @bias */
+
+	/* @CCK HW AntDiv Parameters */
+	odm_set_bb_reg(dm, R_0xa74, BIT(7), 1); /* patch for clk from 88M to 80M */
+	odm_set_bb_reg(dm, R_0xa0c, BIT(4), 1); /* @do 64 samples */
+
+	odm_set_bb_reg(dm, R_0x800, BIT(25), 0); /* @ANTSEL_CCK sent to the smart_antenna circuit */
+	odm_set_bb_reg(dm, R_0xa00, BIT(15), 0); /* @CCK AntDiv function block enable */
+
+	/* @BT Coexistence */
+	odm_set_bb_reg(dm, R_0xcac, BIT(9), 1); /* @keep antsel_map when GNT_BT = 1 */
+	odm_set_bb_reg(dm, R_0x804, BIT(4), 1); /* @Disable hw antsw & fast_train.antsw when GNT_BT=1 */
+
+	odm_set_bb_reg(dm, R_0x8cc, BIT(20) | BIT(19) | BIT(18), 3); /* settling time of antdiv by RF LNA = 100ns */
+
+	/* response TX ant by RX ant */
+	odm_set_mac_reg(dm, R_0x668, BIT(3), 1);
+}
+
+void odm_s0s1_sw_ant_div_init_8821a(
+	void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct sw_antenna_switch *dm_swat_table = &dm->dm_swat_table;
+
+	PHYDM_DBG(dm, DBG_ANT_DIV,
+		  "***8821A AntDiv_Init => ant_div_type=[ S0S1_SW_AntDiv]\n");
+
+	/* Output Pin Settings */
+	odm_set_mac_reg(dm, R_0x4c, BIT(25), 0);
+
+	odm_set_mac_reg(dm, R_0x64, BIT(29), 1); /* PAPE by WLAN control */
+	odm_set_mac_reg(dm, R_0x64, BIT(28), 1); /* @LNAON by WLAN control */
+
+	odm_set_bb_reg(dm, R_0xcb8, BIT(16), 0);
+
+	odm_set_mac_reg(dm, R_0x4c, BIT(23), 0); /* select DPDT_P and DPDT_N as output pin */
+	odm_set_mac_reg(dm, R_0x4c, BIT(24), 1); /* @by WLAN control */
+	odm_set_bb_reg(dm, R_0xcb4, 0xF, 8); /* @DPDT_P = ANTSEL[0] */
+	odm_set_bb_reg(dm, R_0xcb4, 0xF0, 8); /* @DPDT_N = ANTSEL[0] */
+	odm_set_bb_reg(dm, R_0xcb4, BIT(29), 0); /* @DPDT_P non-inverse */
+	odm_set_bb_reg(dm, R_0xcb4, BIT(28), 1); /* @DPDT_N inverse */
+
+	/* @Mapping Table */
+	odm_set_bb_reg(dm, R_0xca4, MASKBYTE0, 0);
+	odm_set_bb_reg(dm, R_0xca4, MASKBYTE1, 1);
+
+	/* OFDM HW AntDiv Parameters */
+	odm_set_bb_reg(dm, R_0x8d4, 0x7FF, 0xA0); /* thershold */
+	odm_set_bb_reg(dm, R_0x8d4, 0x7FF000, 0x10); /* @bias */
+
+	/* @CCK HW AntDiv Parameters */
+	odm_set_bb_reg(dm, R_0xa74, BIT(7), 1); /* patch for clk from 88M to 80M */
+	odm_set_bb_reg(dm, R_0xa0c, BIT(4), 1); /* @do 64 samples */
+
+	odm_set_bb_reg(dm, R_0x800, BIT(25), 0); /* @ANTSEL_CCK sent to the smart_antenna circuit */
+	odm_set_bb_reg(dm, R_0xa00, BIT(15), 0); /* @CCK AntDiv function block enable */
+
+	/* @BT Coexistence */
+	odm_set_bb_reg(dm, R_0xcac, BIT(9), 1); /* @keep antsel_map when GNT_BT = 1 */
+	odm_set_bb_reg(dm, R_0x804, BIT(4), 1); /* @Disable hw antsw & fast_train.antsw when GNT_BT=1 */
+
+	odm_set_bb_reg(dm, R_0x8cc, BIT(20) | BIT(19) | BIT(18), 3); /* settling time of antdiv by RF LNA = 100ns */
+
+	/* response TX ant by RX ant */
+	odm_set_mac_reg(dm, R_0x668, BIT(3), 1);
+
+	odm_set_bb_reg(dm, R_0x900, BIT(18), 0);
+
+	dm_swat_table->try_flag = SWAW_STEP_INIT;
+	dm_swat_table->double_chk_flag = 0;
+	dm_swat_table->cur_antenna = MAIN_ANT;
+	dm_swat_table->pre_antenna = MAIN_ANT;
+	dm_swat_table->swas_no_link_state = 0;
+}
+#endif /* @#if (RTL8821A_SUPPORT == 1) */
+
+#if (RTL8821C_SUPPORT == 1)
+void odm_trx_hw_ant_div_init_8821c(
+	void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+
+	PHYDM_DBG(dm, DBG_ANT_DIV,
+		  "***8821C AntDiv_Init => ant_div_type=[ CG_TRX_HW_ANTDIV (DPDT)]\n");
+	/* Output Pin Settings */
+	odm_set_mac_reg(dm, R_0x4c, BIT(25), 0);
+
+	odm_set_mac_reg(dm, R_0x64, BIT(29), 1); /* PAPE by WLAN control */
+	odm_set_mac_reg(dm, R_0x64, BIT(28), 1); /* @LNAON by WLAN control */
+
+	odm_set_bb_reg(dm, R_0xcb8, BIT(16), 0);
+
+	odm_set_mac_reg(dm, R_0x4c, BIT(23), 0); /* select DPDT_P and DPDT_N as output pin */
+	odm_set_mac_reg(dm, R_0x4c, BIT(24), 1); /* @by WLAN control */
+	odm_set_bb_reg(dm, R_0xcb4, 0xF, 8); /* @DPDT_P = ANTSEL[0] */
+	odm_set_bb_reg(dm, R_0xcb4, 0xF0, 8); /* @DPDT_N = ANTSEL[0] */
+	odm_set_bb_reg(dm, R_0xcb4, BIT(29), 0); /* @DPDT_P non-inverse */
+	odm_set_bb_reg(dm, R_0xcb4, BIT(28), 1); /* @DPDT_N inverse */
+
+	/* @Mapping Table */
+	odm_set_bb_reg(dm, R_0xca4, MASKBYTE0, 0);
+	odm_set_bb_reg(dm, R_0xca4, MASKBYTE1, 1);
+
+	/* OFDM HW AntDiv Parameters */
+	odm_set_bb_reg(dm, R_0x8d4, 0x7FF, 0xA0); /* thershold */
+	odm_set_bb_reg(dm, R_0x8d4, 0x7FF000, 0x10); /* @bias */
+
+	/* @CCK HW AntDiv Parameters */
+	odm_set_bb_reg(dm, R_0xa74, BIT(7), 1); /* patch for clk from 88M to 80M */
+	odm_set_bb_reg(dm, R_0xa0c, BIT(4), 1); /* @do 64 samples */
+
+	odm_set_bb_reg(dm, R_0x800, BIT(25), 0); /* @ANTSEL_CCK sent to the smart_antenna circuit */
+	odm_set_bb_reg(dm, R_0xa00, BIT(15), 0); /* @CCK AntDiv function block enable */
+
+	/* @BT Coexistence */
+	odm_set_bb_reg(dm, R_0xcac, BIT(9), 1); /* @keep antsel_map when GNT_BT = 1 */
+	odm_set_bb_reg(dm, R_0x804, BIT(4), 1); /* @Disable hw antsw & fast_train.antsw when GNT_BT=1 */
+
+	/* Timming issue */
+	odm_set_bb_reg(dm, R_0x818, BIT(23) | BIT(22) | BIT(21) | BIT(20), 0); /*@keep antidx after tx for ACK ( unit x 3.2 mu sec)*/
+	odm_set_bb_reg(dm, R_0x8cc, BIT(20) | BIT(19) | BIT(18), 3); /* settling time of antdiv by RF LNA = 100ns */
+
+	/* response TX ant by RX ant */
+	odm_set_mac_reg(dm, R_0x668, BIT(3), 1);
+}
+
+void phydm_s0s1_sw_ant_div_init_8821c(
+	void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct sw_antenna_switch *dm_swat_table = &dm->dm_swat_table;
+
+	PHYDM_DBG(dm, DBG_ANT_DIV,
+		  "***8821C AntDiv_Init => ant_div_type=[ S0S1_SW_AntDiv]\n");
+
+	/* Output Pin Settings */
+	odm_set_mac_reg(dm, R_0x4c, BIT(25), 0);
+
+	odm_set_mac_reg(dm, R_0x64, BIT(29), 1); /* PAPE by WLAN control */
+	odm_set_mac_reg(dm, R_0x64, BIT(28), 1); /* @LNAON by WLAN control */
+
+	odm_set_bb_reg(dm, R_0xcb8, BIT(16), 0);
+
+	odm_set_mac_reg(dm, R_0x4c, BIT(23), 0); /* select DPDT_P and DPDT_N as output pin */
+	odm_set_mac_reg(dm, R_0x4c, BIT(24), 1); /* @by WLAN control */
+	odm_set_bb_reg(dm, R_0xcb4, 0xF, 8); /* @DPDT_P = ANTSEL[0] */
+	odm_set_bb_reg(dm, R_0xcb4, 0xF0, 8); /* @DPDT_N = ANTSEL[0] */
+	odm_set_bb_reg(dm, R_0xcb4, BIT(29), 0); /* @DPDT_P non-inverse */
+	odm_set_bb_reg(dm, R_0xcb4, BIT(28), 1); /* @DPDT_N inverse */
+
+	/* @Mapping Table */
+	odm_set_bb_reg(dm, R_0xca4, MASKBYTE0, 0);
+	odm_set_bb_reg(dm, R_0xca4, MASKBYTE1, 1);
+
+	/* OFDM HW AntDiv Parameters */
+	odm_set_bb_reg(dm, R_0x8d4, 0x7FF, 0xA0); /* thershold */
+	odm_set_bb_reg(dm, R_0x8d4, 0x7FF000, 0x00); /* @bias */
+
+	/* @CCK HW AntDiv Parameters */
+	odm_set_bb_reg(dm, R_0xa74, BIT(7), 1); /* patch for clk from 88M to 80M */
+	odm_set_bb_reg(dm, R_0xa0c, BIT(4), 1); /* @do 64 samples */
+
+	odm_set_bb_reg(dm, R_0x800, BIT(25), 0); /* @ANTSEL_CCK sent to the smart_antenna circuit */
+	odm_set_bb_reg(dm, R_0xa00, BIT(15), 0); /* @CCK AntDiv function block enable */
+
+	/* @BT Coexistence */
+	odm_set_bb_reg(dm, R_0xcac, BIT(9), 1); /* @keep antsel_map when GNT_BT = 1 */
+	odm_set_bb_reg(dm, R_0x804, BIT(4), 1); /* @Disable hw antsw & fast_train.antsw when GNT_BT=1 */
+
+	odm_set_bb_reg(dm, R_0x8cc, BIT(20) | BIT(19) | BIT(18), 3); /* settling time of antdiv by RF LNA = 100ns */
+
+	/* response TX ant by RX ant */
+	odm_set_mac_reg(dm, R_0x668, BIT(3), 1);
+
+	odm_set_bb_reg(dm, R_0x900, BIT(18), 0);
+
+	dm_swat_table->try_flag = SWAW_STEP_INIT;
+	dm_swat_table->double_chk_flag = 0;
+	dm_swat_table->cur_antenna = MAIN_ANT;
+	dm_swat_table->pre_antenna = MAIN_ANT;
+	dm_swat_table->swas_no_link_state = 0;
+}
+#endif /* @#if (RTL8821C_SUPPORT == 1) */
+
+#if (RTL8881A_SUPPORT == 1)
+void odm_trx_hw_ant_div_init_8881a(
+	void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+
+	PHYDM_DBG(dm, DBG_ANT_DIV,
+		  "***8881A AntDiv_Init => ant_div_type=[ CG_TRX_HW_ANTDIV (SPDT)]\n");
+
+	/* Output Pin Settings */
+	/* @[SPDT related] */
+	odm_set_mac_reg(dm, R_0x4c, BIT(25), 0);
+	odm_set_mac_reg(dm, R_0x4c, BIT(26), 0);
+	odm_set_bb_reg(dm, R_0xcb4, BIT(31), 0); /* @delay buffer */
+	odm_set_bb_reg(dm, R_0xcb4, BIT(22), 0);
+	odm_set_bb_reg(dm, R_0xcb4, BIT(24), 1);
+	odm_set_bb_reg(dm, R_0xcb0, 0xF00, 8); /* @DPDT_P = ANTSEL[0] */
+	odm_set_bb_reg(dm, R_0xcb0, 0xF0000, 8); /* @DPDT_N = ANTSEL[0] */
+
+	/* @Mapping Table */
+	odm_set_bb_reg(dm, R_0xca4, MASKBYTE0, 0);
+	odm_set_bb_reg(dm, R_0xca4, MASKBYTE1, 1);
+
+	/* OFDM HW AntDiv Parameters */
+	odm_set_bb_reg(dm, R_0x8d4, 0x7FF, 0xA0); /* thershold */
+	odm_set_bb_reg(dm, R_0x8d4, 0x7FF000, 0x0); /* @bias */
+	odm_set_bb_reg(dm, R_0x8cc, BIT(20) | BIT(19) | BIT(18), 3); /* settling time of antdiv by RF LNA = 100ns */
+
+	/* @CCK HW AntDiv Parameters */
+	odm_set_bb_reg(dm, R_0xa74, BIT(7), 1); /* patch for clk from 88M to 80M */
+	odm_set_bb_reg(dm, R_0xa0c, BIT(4), 1); /* @do 64 samples */
+
+	/* @2 [--For HW Bug setting] */
+
+	odm_set_bb_reg(dm, R_0x900, BIT(18), 0); /* TX ant  by Reg */ /* A-cut bug */
+}
+
+#endif /* @#if (RTL8881A_SUPPORT == 1) */
+
+#if (RTL8812A_SUPPORT == 1)
+void odm_trx_hw_ant_div_init_8812a(
+	void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+
+	PHYDM_DBG(dm, DBG_ANT_DIV,
+		  "***8812A AntDiv_Init => ant_div_type=[ CG_TRX_HW_ANTDIV (SPDT)]\n");
+
+	/* @3 */ /* @3 --RFE pin setting--------- */
+	/* @[BB] */
+	odm_set_bb_reg(dm, R_0x900, BIT(10) | BIT(9) | BIT(8), 0x0); /* @disable SW switch */
+	odm_set_bb_reg(dm, R_0x900, BIT(17) | BIT(16), 0x0);
+	odm_set_bb_reg(dm, R_0x974, BIT(7) | BIT(6), 0x3); /* @in/out */
+	odm_set_bb_reg(dm, R_0xcb4, BIT(31), 0); /* @delay buffer */
+	odm_set_bb_reg(dm, R_0xcb4, BIT(26), 0);
+	odm_set_bb_reg(dm, R_0xcb4, BIT(27), 1);
+	odm_set_bb_reg(dm, R_0xcb0, 0xF000000, 8); /* @DPDT_P = ANTSEL[0] */
+	odm_set_bb_reg(dm, R_0xcb0, 0xF0000000, 8); /* @DPDT_N = ANTSEL[0] */
+	/* @3 ------------------------- */
+
+	/* @Mapping Table */
+	odm_set_bb_reg(dm, R_0xca4, MASKBYTE0, 0);
+	odm_set_bb_reg(dm, R_0xca4, MASKBYTE1, 1);
+
+	/* OFDM HW AntDiv Parameters */
+	odm_set_bb_reg(dm, R_0x8d4, 0x7FF, 0xA0); /* thershold */
+	odm_set_bb_reg(dm, R_0x8d4, 0x7FF000, 0x0); /* @bias */
+	odm_set_bb_reg(dm, R_0x8cc, BIT(20) | BIT(19) | BIT(18), 3); /* settling time of antdiv by RF LNA = 100ns */
+
+	/* @CCK HW AntDiv Parameters */
+	odm_set_bb_reg(dm, R_0xa74, BIT(7), 1); /* patch for clk from 88M to 80M */
+	odm_set_bb_reg(dm, R_0xa0c, BIT(4), 1); /* @do 64 samples */
+
+	/* @2 [--For HW Bug setting] */
+
+	odm_set_bb_reg(dm, R_0x900, BIT(18), 0); /* TX ant  by Reg */ /* A-cut bug */
+}
+
+#endif /* @#if (RTL8812A_SUPPORT == 1) */
+
+#if (RTL8188F_SUPPORT == 1)
+void odm_s0s1_sw_ant_div_init_8188f(
+	void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct sw_antenna_switch *dm_swat_table = &dm->dm_swat_table;
+	struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
+
+	PHYDM_DBG(dm, DBG_ANT_DIV,
+		  "***8188F AntDiv_Init => ant_div_type=[ S0S1_SW_AntDiv]\n");
+
+#if 0
+	/*@GPIO setting*/
+	/*odm_set_mac_reg(dm, R_0x64, BIT(18), 0); */
+	/*odm_set_mac_reg(dm, R_0x44, BIT(28)|BIT(27), 0);*/
+	/*odm_set_mac_reg(dm, R_0x44, BIT(20) | BIT(19), 0x3);*/ /*enable_output for P_GPIO[4:3]*/
+	/*odm_set_mac_reg(dm, R_0x44, BIT(12)|BIT(11), 0);*/ /*output value*/
+	/*odm_set_mac_reg(dm, R_0x40, BIT(1)|BIT(0), 0);*/ /*GPIO function*/
+#endif
+
+	if (dm->support_ic_type == ODM_RTL8188F) {
+		if (dm->support_interface == ODM_ITRF_USB)
+			odm_set_mac_reg(dm, R_0x44, BIT(20) | BIT(19), 0x3); /*@enable_output for P_GPIO[4:3]*/
+		else if (dm->support_interface == ODM_ITRF_SDIO)
+			odm_set_mac_reg(dm, R_0x44, BIT(18), 0x1); /*@enable_output for P_GPIO[2]*/
+	}
+
+	fat_tab->is_become_linked = false;
+	dm_swat_table->try_flag = SWAW_STEP_INIT;
+	dm_swat_table->double_chk_flag = 0;
+}
+
+void phydm_update_rx_idle_antenna_8188F(
+	void *dm_void,
+	u32 default_ant)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	u8 codeword;
+
+	if (dm->support_ic_type == ODM_RTL8188F) {
+		if (dm->support_interface == ODM_ITRF_USB) {
+			if (default_ant == ANT1_2G)
+				codeword = 1; /*@2'b01*/
+			else
+				codeword = 2; /*@2'b10*/
+			odm_set_mac_reg(dm, R_0x44, (BIT(12) | BIT(11)), codeword); /*@GPIO[4:3] output value*/
+		} else if (dm->support_interface == ODM_ITRF_SDIO) {
+			if (default_ant == ANT1_2G) {
+				codeword = 0; /*@1'b0*/
+				odm_set_bb_reg(dm, R_0x870, BIT(9) | BIT(8), 0x3);
+				odm_set_bb_reg(dm, R_0x860, BIT(9) | BIT(8), 0x1);
+			} else {
+				codeword = 1; /*@1'b1*/
+				odm_set_bb_reg(dm, R_0x870, BIT(9) | BIT(8), 0x3);
+				odm_set_bb_reg(dm, R_0x860, BIT(9) | BIT(8), 0x2);
+			}
+			odm_set_mac_reg(dm, R_0x44, BIT(10), codeword); /*@GPIO[2] output value*/
+		}
+	}
+}
+#endif
+
+#ifdef ODM_EVM_ENHANCE_ANTDIV
+void phydm_evm_sw_antdiv_init(
+	void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
+
+	/*@EVM enhance AntDiv method init----------------------------------------------------------------------*/
+	fat_tab->evm_method_enable = 0;
+	fat_tab->fat_state = NORMAL_STATE_MIAN;
+	fat_tab->fat_state_cnt = 0;
+	fat_tab->pre_antdiv_rssi = 0;
+
+	dm->antdiv_intvl = 30;
+	dm->antdiv_train_num = 2;
+	odm_set_bb_reg(dm, R_0x910, 0x3f, 0xf);
+	dm->antdiv_evm_en = 1;
+	/*@dm->antdiv_period=1;*/
+#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
+	dm->evm_antdiv_period = 1;
+#else
+	dm->evm_antdiv_period = 3;
+#endif
+	dm->stop_antdiv_rssi_th = 3;
+	dm->stop_antdiv_tp_th = 80;
+	dm->antdiv_tp_period = 3;
+	dm->stop_antdiv_tp_diff_th = 5;
+}
+
+void odm_evm_fast_ant_reset(
+	void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
+
+	fat_tab->evm_method_enable = 0;
+	if (fat_tab->div_path_type == ANT_PATH_A)
+		odm_ant_div_on_off(dm, ANTDIV_ON, ANT_PATH_A);
+	else if (fat_tab->div_path_type == ANT_PATH_B)
+		odm_ant_div_on_off(dm, ANTDIV_ON, ANT_PATH_B);
+	else if (fat_tab->div_path_type == ANT_PATH_AB)
+		odm_ant_div_on_off(dm, ANTDIV_ON, ANT_PATH_AB);
+	fat_tab->fat_state = NORMAL_STATE_MIAN;
+	fat_tab->fat_state_cnt = 0;
+	dm->antdiv_period = 0;
+	odm_set_mac_reg(dm, R_0x608, BIT(8), 0);
+}
+
+void odm_evm_enhance_ant_div(
+	void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	u32 main_rssi, aux_rssi;
+	u32 main_crc_utility = 0, aux_crc_utility = 0, utility_ratio = 1;
+	u32 main_evm, aux_evm, diff_rssi = 0, diff_EVM = 0;
+	u32 main_2ss_evm[2], aux_2ss_evm[2];
+	u32 main_1ss_evm, aux_1ss_evm;
+	u32 main_2ss_evm_sum, aux_2ss_evm_sum;
+	u8 score_EVM = 0, score_CRC = 0;
+	u8 rssi_larger_ant = 0;
+	struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
+	u32 value32, i;
+	boolean main_above1 = false, aux_above1 = false;
+	boolean force_antenna = false;
+	struct cmn_sta_info *sta;
+	u32 antdiv_tp_main_avg, antdiv_tp_aux_avg;
+	u8 curr_rssi, rssi_diff;
+	u32 tp_diff;
+	u8 tp_diff_return = 0, tp_return = 0, rssi_return = 0;
+	u8 target_ant_evm_1ss, target_ant_evm_2ss;
+	u8 decision_evm_ss;
+	u8 next_ant;
+
+	fat_tab->target_ant_enhance = 0xFF;
+
+	if ((dm->support_ic_type & ODM_EVM_ENHANCE_ANTDIV_SUPPORT_IC)) {
+		if (dm->is_one_entry_only) {
+#if 0
+			/* PHYDM_DBG(dm,DBG_ANT_DIV, "[One Client only]\n"); */
+#endif
+			i = dm->one_entry_macid;
+			sta = dm->phydm_sta_info[i];
+
+			main_rssi = (fat_tab->main_ant_cnt[i] != 0) ? (fat_tab->main_ant_sum[i] / fat_tab->main_ant_cnt[i]) : 0;
+			aux_rssi = (fat_tab->aux_ant_cnt[i] != 0) ? (fat_tab->aux_ant_sum[i] / fat_tab->aux_ant_cnt[i]) : 0;
+
+			if ((main_rssi == 0 && aux_rssi != 0 && aux_rssi >= FORCE_RSSI_DIFF) || (main_rssi != 0 && aux_rssi == 0 && main_rssi >= FORCE_RSSI_DIFF))
+				diff_rssi = FORCE_RSSI_DIFF;
+			else if (main_rssi != 0 && aux_rssi != 0)
+				diff_rssi = (main_rssi >= aux_rssi) ? (main_rssi - aux_rssi) : (aux_rssi - main_rssi);
+
+			if (main_rssi >= aux_rssi)
+				rssi_larger_ant = MAIN_ANT;
+			else
+				rssi_larger_ant = AUX_ANT;
+
+			PHYDM_DBG(dm, DBG_ANT_DIV,
+				  "Main_Cnt=(( %d )), main_rssi=(( %d ))\n",
+				  fat_tab->main_ant_cnt[i], main_rssi);
+			PHYDM_DBG(dm, DBG_ANT_DIV,
+				  "Aux_Cnt=(( %d )), aux_rssi=(( %d ))\n",
+				  fat_tab->aux_ant_cnt[i], aux_rssi);
+
+			if (((main_rssi >= evm_rssi_th_high || aux_rssi >= evm_rssi_th_high) || fat_tab->evm_method_enable == 1)
+			    /* @&& (diff_rssi <= FORCE_RSSI_DIFF + 1) */
+			    ) {
+				PHYDM_DBG(dm, DBG_ANT_DIV,
+					  "> TH_H || evm_method_enable==1\n");
+
+				if ((main_rssi >= evm_rssi_th_low || aux_rssi >= evm_rssi_th_low)) {
+					PHYDM_DBG(dm, DBG_ANT_DIV, "> TH_L, fat_state_cnt =((%d))\n", fat_tab->fat_state_cnt);
+
+					/*Traning state: 0(alt) 1(ori) 2(alt) 3(ori)============================================================*/
+					if (fat_tab->fat_state_cnt < (dm->antdiv_train_num << 1)) {
+						if (fat_tab->fat_state_cnt == 0) {
+							/*Reset EVM 1SS Method */
+							fat_tab->main_ant_evm_sum[i] = 0;
+							fat_tab->aux_ant_evm_sum[i] = 0;
+							fat_tab->main_ant_evm_cnt[i] = 0;
+							fat_tab->aux_ant_evm_cnt[i] = 0;
+							/*Reset EVM 2SS Method */
+							fat_tab->main_ant_evm_2ss_sum[i][0] = 0;
+							fat_tab->main_ant_evm_2ss_sum[i][1] = 0;
+							fat_tab->aux_ant_evm_2ss_sum[i][0] = 0;
+							fat_tab->aux_ant_evm_2ss_sum[i][1] = 0;
+							fat_tab->main_ant_evm_2ss_cnt[i] = 0;
+							fat_tab->aux_ant_evm_2ss_cnt[i] = 0;
+#if 0
+							/*Reset TP Method */
+							fat_tab->antdiv_tp_main = 0;
+							fat_tab->antdiv_tp_aux = 0;
+							fat_tab->antdiv_tp_main_cnt = 0;
+							fat_tab->antdiv_tp_aux_cnt = 0;
+#endif
+							/*Reset CRC Method */
+							fat_tab->main_crc32_ok_cnt = 0;
+							fat_tab->main_crc32_fail_cnt = 0;
+							fat_tab->aux_crc32_ok_cnt = 0;
+							fat_tab->aux_crc32_fail_cnt = 0;
+
+#ifdef SKIP_EVM_ANTDIV_TRAINING_PATCH
+							if ((*dm->band_width == CHANNEL_WIDTH_20) && sta->mimo_type == RF_2T2R) {
+								/*@1. Skip training: RSSI*/
+#if 0
+								/*PHYDM_DBG(pDM_Odm,DBG_ANT_DIV, "TargetAnt_enhance=((%d)), RxIdleAnt=((%d))\n", pDM_FatTable->TargetAnt_enhance, pDM_FatTable->RxIdleAnt);*/
+#endif
+								curr_rssi = (u8)((fat_tab->rx_idle_ant == MAIN_ANT) ? main_rssi : aux_rssi);
+								rssi_diff = (curr_rssi > fat_tab->pre_antdiv_rssi) ? (curr_rssi - fat_tab->pre_antdiv_rssi) : (fat_tab->pre_antdiv_rssi - curr_rssi);
+
+								PHYDM_DBG(dm, DBG_ANT_DIV, "[1] rssi_return, curr_rssi=((%d)), pre_rssi=((%d))\n", curr_rssi, fat_tab->pre_antdiv_rssi);
+
+								fat_tab->pre_antdiv_rssi = curr_rssi;
+								if (rssi_diff < dm->stop_antdiv_rssi_th && curr_rssi != 0)
+									rssi_return = 1;
+
+								/*@2. Skip training: TP Diff*/
+								tp_diff = (dm->rx_tp > fat_tab->pre_antdiv_tp) ? (dm->rx_tp - fat_tab->pre_antdiv_tp) : (fat_tab->pre_antdiv_tp - dm->rx_tp);
+
+								PHYDM_DBG(dm, DBG_ANT_DIV, "[2] tp_diff_return, curr_tp=((%d)), pre_tp=((%d))\n", dm->rx_tp, fat_tab->pre_antdiv_tp);
+								fat_tab->pre_antdiv_tp = dm->rx_tp;
+								if ((tp_diff < (u32)(dm->stop_antdiv_tp_diff_th) && dm->rx_tp != 0))
+									tp_diff_return = 1;
+
+								PHYDM_DBG(dm, DBG_ANT_DIV, "[3] tp_return, curr_rx_tp=((%d))\n", dm->rx_tp);
+								/*@3. Skip training: TP*/
+								if (dm->rx_tp >= (u32)(dm->stop_antdiv_tp_th))
+									tp_return = 1;
+
+								PHYDM_DBG(dm, DBG_ANT_DIV, "[4] Return {rssi, tp_diff, tp} = {%d, %d, %d}\n", rssi_return, tp_diff_return, tp_return);
+								/*@4. Joint Return Decision*/
+								if (tp_return) {
+									if (tp_diff_return || rssi_diff) {
+										PHYDM_DBG(dm, DBG_ANT_DIV, "***Return EVM SW AntDiv\n");
+										return;
+									}
+								}
+							}
+#endif
+
+							fat_tab->evm_method_enable = 1;
+							if (fat_tab->div_path_type == ANT_PATH_A)
+								odm_ant_div_on_off(dm, ANTDIV_OFF, ANT_PATH_A);
+							else if (fat_tab->div_path_type == ANT_PATH_B)
+								odm_ant_div_on_off(dm, ANTDIV_OFF, ANT_PATH_B);
+							else if (fat_tab->div_path_type == ANT_PATH_AB)
+								odm_ant_div_on_off(dm, ANTDIV_OFF, ANT_PATH_AB);
+							dm->antdiv_period = dm->evm_antdiv_period;
+							odm_set_mac_reg(dm, R_0x608, BIT(8), 1); /*RCR accepts CRC32-Error packets*/
+						}
+
+						fat_tab->fat_state_cnt++;
+						next_ant = (fat_tab->rx_idle_ant == MAIN_ANT) ? AUX_ANT : MAIN_ANT;
+						odm_update_rx_idle_ant(dm, next_ant);
+						odm_set_timer(dm, &dm->evm_fast_ant_training_timer, dm->antdiv_intvl); //ms
+					}
+					/*@Decision state: 4==============================================================*/
+					else {
+						fat_tab->fat_state_cnt = 0;
+						PHYDM_DBG(dm, DBG_ANT_DIV, "[Decisoin state ]\n");
+
+/* @3 [CRC32 statistic] */
+#if 0
+						if ((fat_tab->main_crc32_ok_cnt > (fat_tab->aux_crc32_ok_cnt << 1)) || (diff_rssi >= 40 && rssi_larger_ant == MAIN_ANT)) {
+							fat_tab->target_ant_crc32 = MAIN_ANT;
+							force_antenna = true;
+							PHYDM_DBG(dm, DBG_ANT_DIV, "CRC32 Force Main\n");
+						} else if ((fat_tab->aux_crc32_ok_cnt > ((fat_tab->main_crc32_ok_cnt) << 1)) || ((diff_rssi >= 40) && (rssi_larger_ant == AUX_ANT))) {
+							fat_tab->target_ant_crc32 = AUX_ANT;
+							force_antenna = true;
+							PHYDM_DBG(dm, DBG_ANT_DIV, "CRC32 Force Aux\n");
+						} else
+#endif
+						{
+							if (fat_tab->main_crc32_fail_cnt <= 5)
+								fat_tab->main_crc32_fail_cnt = 5;
+
+							if (fat_tab->aux_crc32_fail_cnt <= 5)
+								fat_tab->aux_crc32_fail_cnt = 5;
+
+							if (fat_tab->main_crc32_ok_cnt > fat_tab->main_crc32_fail_cnt)
+								main_above1 = true;
+
+							if (fat_tab->aux_crc32_ok_cnt > fat_tab->aux_crc32_fail_cnt)
+								aux_above1 = true;
+
+							if (main_above1 == true && aux_above1 == false) {
+								force_antenna = true;
+								fat_tab->target_ant_crc32 = MAIN_ANT;
+							} else if (main_above1 == false && aux_above1 == true) {
+								force_antenna = true;
+								fat_tab->target_ant_crc32 = AUX_ANT;
+							} else if (main_above1 == true && aux_above1 == true) {
+								main_crc_utility = ((fat_tab->main_crc32_ok_cnt) << 7) / fat_tab->main_crc32_fail_cnt;
+								aux_crc_utility = ((fat_tab->aux_crc32_ok_cnt) << 7) / fat_tab->aux_crc32_fail_cnt;
+								fat_tab->target_ant_crc32 = (main_crc_utility == aux_crc_utility) ? (fat_tab->pre_target_ant_enhance) : ((main_crc_utility >= aux_crc_utility) ? MAIN_ANT : AUX_ANT);
+
+								if (main_crc_utility != 0 && aux_crc_utility != 0) {
+									if (main_crc_utility >= aux_crc_utility)
+										utility_ratio = (main_crc_utility << 1) / aux_crc_utility;
+									else
+										utility_ratio = (aux_crc_utility << 1) / main_crc_utility;
+								}
+							} else if (main_above1 == false && aux_above1 == false) {
+								if (fat_tab->main_crc32_ok_cnt == 0)
+									fat_tab->main_crc32_ok_cnt = 1;
+								if (fat_tab->aux_crc32_ok_cnt == 0)
+									fat_tab->aux_crc32_ok_cnt = 1;
+
+								main_crc_utility = ((fat_tab->main_crc32_fail_cnt) << 7) / fat_tab->main_crc32_ok_cnt;
+								aux_crc_utility = ((fat_tab->aux_crc32_fail_cnt) << 7) / fat_tab->aux_crc32_ok_cnt;
+								fat_tab->target_ant_crc32 = (main_crc_utility == aux_crc_utility) ? (fat_tab->pre_target_ant_enhance) : ((main_crc_utility <= aux_crc_utility) ? MAIN_ANT : AUX_ANT);
+
+								if (main_crc_utility != 0 && aux_crc_utility != 0) {
+									if (main_crc_utility >= aux_crc_utility)
+										utility_ratio = (main_crc_utility << 1) / (aux_crc_utility);
+									else
+										utility_ratio = (aux_crc_utility << 1) / (main_crc_utility);
+								}
+							}
+						}
+						odm_set_mac_reg(dm, R_0x608, BIT(8), 0); /* NOT Accept CRC32 Error packets. */
+						PHYDM_DBG(dm, DBG_ANT_DIV, "MAIN_CRC: Ok=((%d)), Fail = ((%d)), Utility = ((%d))\n", fat_tab->main_crc32_ok_cnt, fat_tab->main_crc32_fail_cnt, main_crc_utility);
+						PHYDM_DBG(dm, DBG_ANT_DIV, "AUX__CRC: Ok=((%d)), Fail = ((%d)), Utility = ((%d))\n", fat_tab->aux_crc32_ok_cnt, fat_tab->aux_crc32_fail_cnt, aux_crc_utility);
+						PHYDM_DBG(dm, DBG_ANT_DIV, "***1.TargetAnt_CRC32 = ((%s))\n", (fat_tab->target_ant_crc32 == MAIN_ANT) ? "MAIN_ANT" : "AUX_ANT");
+
+						/* @3 [EVM statistic] */
+						/*@1SS EVM*/
+						main_1ss_evm = (fat_tab->main_ant_evm_cnt[i] != 0) ? (fat_tab->main_ant_evm_sum[i] / fat_tab->main_ant_evm_cnt[i]) : 0;
+						aux_1ss_evm = (fat_tab->aux_ant_evm_cnt[i] != 0) ? (fat_tab->aux_ant_evm_sum[i] / fat_tab->aux_ant_evm_cnt[i]) : 0;
+						target_ant_evm_1ss = (main_1ss_evm == aux_1ss_evm) ? (fat_tab->pre_target_ant_enhance) : ((main_1ss_evm >= aux_1ss_evm) ? MAIN_ANT : AUX_ANT);
+
+						PHYDM_DBG(dm, DBG_ANT_DIV, "Cnt = ((%d)), Main1ss_EVM= ((  %d ))\n", fat_tab->main_ant_evm_cnt[i], main_1ss_evm);
+						PHYDM_DBG(dm, DBG_ANT_DIV, "Cnt = ((%d)), Aux_1ss_EVM = ((  %d ))\n", fat_tab->main_ant_evm_cnt[i], aux_1ss_evm);
+
+						/*@2SS EVM*/
+						main_2ss_evm[0] = (fat_tab->main_ant_evm_2ss_cnt[i] != 0) ? (fat_tab->main_ant_evm_2ss_sum[i][0] / fat_tab->main_ant_evm_2ss_cnt[i]) : 0;
+						main_2ss_evm[1] = (fat_tab->main_ant_evm_2ss_cnt[i] != 0) ? (fat_tab->main_ant_evm_2ss_sum[i][1] / fat_tab->main_ant_evm_2ss_cnt[i]) : 0;
+						main_2ss_evm_sum = main_2ss_evm[0] + main_2ss_evm[1];
+
+						aux_2ss_evm[0] = (fat_tab->aux_ant_evm_2ss_cnt[i] != 0) ? (fat_tab->aux_ant_evm_2ss_sum[i][0] / fat_tab->aux_ant_evm_2ss_cnt[i]) : 0;
+						aux_2ss_evm[1] = (fat_tab->aux_ant_evm_2ss_cnt[i] != 0) ? (fat_tab->aux_ant_evm_2ss_sum[i][1] / fat_tab->aux_ant_evm_2ss_cnt[i]) : 0;
+						aux_2ss_evm_sum = aux_2ss_evm[0] + aux_2ss_evm[1];
+
+						target_ant_evm_2ss = (main_2ss_evm_sum == aux_2ss_evm_sum) ? (fat_tab->pre_target_ant_enhance) : ((main_2ss_evm_sum >= aux_2ss_evm_sum) ? MAIN_ANT : AUX_ANT);
+
+						PHYDM_DBG(dm, DBG_ANT_DIV, "Cnt = ((%d)), Main2ss_EVM{A,B,Sum} = {%d, %d, %d}\n",
+							  fat_tab->main_ant_evm_2ss_cnt[i], main_2ss_evm[0], main_2ss_evm[1], main_2ss_evm_sum);
+						PHYDM_DBG(dm, DBG_ANT_DIV, "Cnt = ((%d)), Aux_2ss_EVM{A,B,Sum} = {%d, %d, %d}\n",
+							  fat_tab->aux_ant_evm_2ss_cnt[i], aux_2ss_evm[0], aux_2ss_evm[1], aux_2ss_evm_sum);
+
+						if ((main_2ss_evm_sum + aux_2ss_evm_sum) != 0) {
+							decision_evm_ss = 2;
+							main_evm = main_2ss_evm_sum;
+							aux_evm = aux_2ss_evm_sum;
+							fat_tab->target_ant_evm = target_ant_evm_2ss;
+						} else {
+							decision_evm_ss = 1;
+							main_evm = main_1ss_evm;
+							aux_evm = aux_1ss_evm;
+							fat_tab->target_ant_evm = target_ant_evm_1ss;
+						}
+
+						if ((main_evm == 0 || aux_evm == 0))
+							diff_EVM = 100;
+						else if (main_evm >= aux_evm)
+							diff_EVM = main_evm - aux_evm;
+						else
+							diff_EVM = aux_evm - main_evm;
+
+						PHYDM_DBG(dm, DBG_ANT_DIV, "***2.TargetAnt_EVM((%d-ss)) = ((%s))\n", decision_evm_ss, (fat_tab->target_ant_evm == MAIN_ANT) ? "MAIN_ANT" : "AUX_ANT");
+
+						//3 [TP statistic]
+						antdiv_tp_main_avg = (fat_tab->antdiv_tp_main_cnt != 0) ? (fat_tab->antdiv_tp_main / fat_tab->antdiv_tp_main_cnt) : 0;
+						antdiv_tp_aux_avg = (fat_tab->antdiv_tp_aux_cnt != 0) ? (fat_tab->antdiv_tp_aux / fat_tab->antdiv_tp_aux_cnt) : 0;
+						fat_tab->target_ant_tp = (antdiv_tp_main_avg == antdiv_tp_aux_avg) ? (fat_tab->pre_target_ant_enhance) : ((antdiv_tp_main_avg >= antdiv_tp_aux_avg) ? MAIN_ANT : AUX_ANT);
+
+						PHYDM_DBG(dm, DBG_ANT_DIV, "Cnt = ((%d)), Main_TP = ((%d))\n", fat_tab->antdiv_tp_main_cnt, antdiv_tp_main_avg);
+						PHYDM_DBG(dm, DBG_ANT_DIV, "Cnt = ((%d)), Aux_TP = ((%d))\n", fat_tab->antdiv_tp_aux_cnt, antdiv_tp_aux_avg);
+						PHYDM_DBG(dm, DBG_ANT_DIV, "***3.TargetAnt_TP = ((%s))\n", (fat_tab->target_ant_tp == MAIN_ANT) ? "MAIN_ANT" : "AUX_ANT");
+
+						/*Reset TP Method */
+						fat_tab->antdiv_tp_main = 0;
+						fat_tab->antdiv_tp_aux = 0;
+						fat_tab->antdiv_tp_main_cnt = 0;
+						fat_tab->antdiv_tp_aux_cnt = 0;
+
+						/* @2 [ Decision state ] */
+						if (fat_tab->target_ant_evm == fat_tab->target_ant_crc32) {
+							PHYDM_DBG(dm, DBG_ANT_DIV, "Decision type 1, CRC_utility = ((%d)), EVM_diff = ((%d))\n", utility_ratio, diff_EVM);
+
+							if ((utility_ratio < 2 && force_antenna == false) && diff_EVM <= 30)
+								fat_tab->target_ant_enhance = fat_tab->pre_target_ant_enhance;
+							else
+								fat_tab->target_ant_enhance = fat_tab->target_ant_evm;
+						}
+						#if 0
+						else if ((diff_EVM <= 50 && (utility_ratio > 4 && force_antenna == false)) || (force_antenna == true)) {
+							PHYDM_DBG(dm, DBG_ANT_DIV, "Decision type 2, CRC_utility = ((%d)), EVM_diff = ((%d))\n", utility_ratio, diff_EVM);
+							fat_tab->target_ant_enhance = fat_tab->target_ant_crc32;
+						}
+						#endif
+						else if (diff_EVM >= 20) {
+							PHYDM_DBG(dm, DBG_ANT_DIV, "Decision type 3, CRC_utility = ((%d)), EVM_diff = ((%d))\n", utility_ratio, diff_EVM);
+							fat_tab->target_ant_enhance = fat_tab->target_ant_evm;
+						} else if (utility_ratio >= 6 && force_antenna == false) {
+							PHYDM_DBG(dm, DBG_ANT_DIV, "Decision type 4, CRC_utility = ((%d)), EVM_diff = ((%d))\n", utility_ratio, diff_EVM);
+							fat_tab->target_ant_enhance = fat_tab->target_ant_crc32;
+						} else {
+							PHYDM_DBG(dm, DBG_ANT_DIV, "Decision type 5, CRC_utility = ((%d)), EVM_diff = ((%d))\n", utility_ratio, diff_EVM);
+
+							if (force_antenna == true)
+								score_CRC = 2;
+							else if (utility_ratio >= 5) /*@>2.5*/
+								score_CRC = 2;
+							else if (utility_ratio >= 4) /*@>2*/
+								score_CRC = 1;
+							else
+								score_CRC = 0;
+
+							if (diff_EVM >= 15)
+								score_EVM = 3;
+							else if (diff_EVM >= 10)
+								score_EVM = 2;
+							else if (diff_EVM >= 5)
+								score_EVM = 1;
+							else
+								score_EVM = 0;
+
+							if (score_CRC > score_EVM)
+								fat_tab->target_ant_enhance = fat_tab->target_ant_crc32;
+							else if (score_CRC < score_EVM)
+								fat_tab->target_ant_enhance = fat_tab->target_ant_evm;
+							else
+								fat_tab->target_ant_enhance = fat_tab->pre_target_ant_enhance;
+						}
+						fat_tab->pre_target_ant_enhance = fat_tab->target_ant_enhance;
+
+						PHYDM_DBG(dm, DBG_ANT_DIV, "*** 4.TargetAnt_enhance = (( %s ))******\n", (fat_tab->target_ant_enhance == MAIN_ANT) ? "MAIN_ANT" : "AUX_ANT");
+					}
+				} else { /* RSSI< = evm_rssi_th_low */
+					PHYDM_DBG(dm, DBG_ANT_DIV, "[ <TH_L: escape from > TH_L ]\n");
+					odm_evm_fast_ant_reset(dm);
+				}
+			} else {
+				PHYDM_DBG(dm, DBG_ANT_DIV,
+					  "[escape from> TH_H || evm_method_enable==1]\n");
+				odm_evm_fast_ant_reset(dm);
+			}
+		} else {
+			PHYDM_DBG(dm, DBG_ANT_DIV, "[multi-Client]\n");
+			odm_evm_fast_ant_reset(dm);
+		}
+	}
+}
+
+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
+void phydm_evm_antdiv_callback(
+	struct phydm_timer_list *timer)
+{
+	void *adapter = (void *)timer->Adapter;
+	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter));
+	struct dm_struct *dm = &hal_data->DM_OutSrc;
+
+	#if DEV_BUS_TYPE == RT_PCI_INTERFACE
+	#if USE_WORKITEM
+	odm_schedule_work_item(&dm->phydm_evm_antdiv_workitem);
+	#else
+	{
+		odm_hw_ant_div(dm);
+	}
+	#endif
+	#else
+	odm_schedule_work_item(&dm->phydm_evm_antdiv_workitem);
+	#endif
+}
+
+void phydm_evm_antdiv_workitem_callback(
+	void *context)
+{
+	void *adapter = (void *)context;
+	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter));
+	struct dm_struct *dm = &hal_data->DM_OutSrc;
+
+	odm_hw_ant_div(dm);
+}
+
+#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
+void phydm_evm_antdiv_callback(
+	void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	void *padapter = dm->adapter;
+
+	if (*dm->is_net_closed)
+		return;
+	if (dm->support_interface == ODM_ITRF_PCIE) {
+		odm_hw_ant_div(dm);
+	} else {
+		/* @Can't do I/O in timer callback*/
+		phydm_run_in_thread_cmd(dm,
+					phydm_evm_antdiv_workitem_callback,
+					padapter);
+	}
+}
+
+void phydm_evm_antdiv_workitem_callback(
+	void *context)
+{
+	void *adapter = (void *)context;
+	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter));
+	struct dm_struct *dm = &hal_data->odmpriv;
+
+	odm_hw_ant_div(dm);
+}
+
+#else
+void phydm_evm_antdiv_callback(
+	void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+
+	PHYDM_DBG(dm, DBG_ANT_DIV, "******AntDiv_Callback******\n");
+	odm_hw_ant_div(dm);
+}
+#endif
+
+#endif
+
+void odm_hw_ant_div(
+	void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	u32 i, min_max_rssi = 0xFF, ant_div_max_rssi = 0, max_rssi = 0, local_max_rssi;
+	u32 main_rssi, aux_rssi, mian_cnt, aux_cnt;
+	struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
+	u8 rx_idle_ant = fat_tab->rx_idle_ant, target_ant = 7;
+	struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
+	struct cmn_sta_info *sta;
+
+#if (BEAMFORMING_SUPPORT == 1)
+#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
+	struct _BF_DIV_COEX_ *dm_bdc_table = &dm->dm_bdc_table;
+	u32 TH1 = 500000;
+	u32 TH2 = 10000000;
+	u32 ma_rx_temp, degrade_TP_temp, improve_TP_temp;
+	u8 monitor_rssi_threshold = 30;
+
+	dm_bdc_table->BF_pass = true;
+	dm_bdc_table->DIV_pass = true;
+	dm_bdc_table->is_all_div_sta_idle = true;
+	dm_bdc_table->is_all_bf_sta_idle = true;
+	dm_bdc_table->num_bf_tar = 0;
+	dm_bdc_table->num_div_tar = 0;
+	dm_bdc_table->num_client = 0;
+#endif
+#endif
+
+	if (!dm->is_linked) { /* @is_linked==False */
+		PHYDM_DBG(dm, DBG_ANT_DIV, "[No Link!!!]\n");
+
+		if (fat_tab->is_become_linked == true) {
+			if (fat_tab->div_path_type == ANT_PATH_A)
+				odm_ant_div_on_off(dm, ANTDIV_OFF, ANT_PATH_A);
+			else if (fat_tab->div_path_type == ANT_PATH_B)
+				odm_ant_div_on_off(dm, ANTDIV_OFF, ANT_PATH_B);
+			else if (fat_tab->div_path_type == ANT_PATH_AB)
+				odm_ant_div_on_off(dm, ANTDIV_OFF, ANT_PATH_AB);
+			odm_update_rx_idle_ant(dm, MAIN_ANT);
+			odm_tx_by_tx_desc_or_reg(dm, TX_BY_REG);
+			dm->antdiv_period = 0;
+
+			fat_tab->is_become_linked = dm->is_linked;
+		}
+		return;
+	} else {
+		if (fat_tab->is_become_linked == false) {
+			PHYDM_DBG(dm, DBG_ANT_DIV, "[Linked !!!]\n");
+			if (fat_tab->div_path_type == ANT_PATH_A)
+				odm_ant_div_on_off(dm, ANTDIV_ON, ANT_PATH_A);
+			else if (fat_tab->div_path_type == ANT_PATH_B)
+				odm_ant_div_on_off(dm, ANTDIV_ON, ANT_PATH_B);
+			else if (fat_tab->div_path_type == ANT_PATH_AB)
+				odm_ant_div_on_off(dm, ANTDIV_ON, ANT_PATH_AB);
+#if 0
+			/*odm_tx_by_tx_desc_or_reg(dm, TX_BY_DESC);*/
+#endif
+
+#if 0
+			/* @if(dm->support_ic_type == ODM_RTL8821 ) */
+			/* odm_set_bb_reg(dm, R_0x800, BIT(25), 0); */ /* CCK AntDiv function disable */
+#endif
+
+#if 0
+			/* @#if(DM_ODM_SUPPORT_TYPE  == ODM_AP) */
+			/* @else if(dm->support_ic_type == ODM_RTL8881A) */
+			/* odm_set_bb_reg(dm, R_0x800, BIT(25), 0); */ /* CCK AntDiv function disable */
+			/* @#endif */
+#endif
+
+#if 0
+			/* @else if(dm->support_ic_type == ODM_RTL8723B ||dm->support_ic_type == ODM_RTL8812) */
+			/* odm_set_bb_reg(dm, R_0xa00, BIT(15), 0); */ /* CCK AntDiv function disable */
+#endif
+
+			fat_tab->is_become_linked = dm->is_linked;
+
+			if (dm->support_ic_type == ODM_RTL8723B && dm->ant_div_type == CG_TRX_HW_ANTDIV) {
+				odm_set_bb_reg(dm, R_0x930, 0xF0, 8); /* @DPDT_P = ANTSEL[0]   */ /* @for 8723B AntDiv function patch.  BB  Dino  130412 */
+				odm_set_bb_reg(dm, R_0x930, 0xF, 8); /* @DPDT_N = ANTSEL[0] */
+			}
+
+/* @2 BDC Init */
+#if (BEAMFORMING_SUPPORT == 1)
+#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
+			odm_bdc_init(dm);
+#endif
+#endif
+
+#ifdef ODM_EVM_ENHANCE_ANTDIV
+			odm_evm_fast_ant_reset(dm);
+#endif
+		}
+	}
+
+	if (*fat_tab->p_force_tx_ant_by_desc == false) {
+		if (dm->is_one_entry_only == true)
+			odm_tx_by_tx_desc_or_reg(dm, TX_BY_REG);
+		else
+			odm_tx_by_tx_desc_or_reg(dm, TX_BY_DESC);
+	}
+
+#ifdef ODM_EVM_ENHANCE_ANTDIV
+	if (dm->antdiv_evm_en == 1) {
+		odm_evm_enhance_ant_div(dm);
+		if (fat_tab->fat_state_cnt != 0)
+			return;
+	} else
+		odm_evm_fast_ant_reset(dm);
+#endif
+
+/* @2 BDC mode Arbitration */
+#if (BEAMFORMING_SUPPORT == 1)
+#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
+	if (dm->antdiv_evm_en == 0 || fat_tab->evm_method_enable == 0)
+		odm_bf_ant_div_mode_arbitration(dm);
+#endif
+#endif
+
+	for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) {
+		sta = dm->phydm_sta_info[i];
+		if (is_sta_active(sta)) {
+			/* @2 Caculate RSSI per Antenna */
+			if (fat_tab->main_ant_cnt[i] != 0 || fat_tab->aux_ant_cnt[i] != 0) {
+				mian_cnt = fat_tab->main_ant_cnt[i];
+				aux_cnt = fat_tab->aux_ant_cnt[i];
+				main_rssi = (mian_cnt != 0) ? (fat_tab->main_ant_sum[i] / mian_cnt) : 0;
+				aux_rssi = (aux_cnt != 0) ? (fat_tab->aux_ant_sum[i] / aux_cnt) : 0;
+				target_ant = (mian_cnt == aux_cnt) ? fat_tab->rx_idle_ant : ((mian_cnt >= aux_cnt) ? MAIN_ANT : AUX_ANT); /*Use counter number for OFDM*/
+
+			} else { /*@CCK only case*/
+				mian_cnt = fat_tab->main_ant_cnt_cck[i];
+				aux_cnt = fat_tab->aux_ant_cnt_cck[i];
+				main_rssi = (mian_cnt != 0) ? (fat_tab->main_ant_sum_cck[i] / mian_cnt) : 0;
+				aux_rssi = (aux_cnt != 0) ? (fat_tab->aux_ant_sum_cck[i] / aux_cnt) : 0;
+				target_ant = (main_rssi == aux_rssi) ? fat_tab->rx_idle_ant : ((main_rssi >= aux_rssi) ? MAIN_ANT : AUX_ANT); /*Use RSSI for CCK only case*/
+			}
+
+			PHYDM_DBG(dm, DBG_ANT_DIV,
+				  "*** Client[ %d ] : Main_Cnt = (( %d ))  ,  CCK_Main_Cnt = (( %d )) ,  main_rssi= ((  %d ))\n",
+				  i, fat_tab->main_ant_cnt[i],
+				  fat_tab->main_ant_cnt_cck[i], main_rssi);
+			PHYDM_DBG(dm, DBG_ANT_DIV,
+				  "*** Client[ %d ] : Aux_Cnt   = (( %d ))  , CCK_Aux_Cnt   = (( %d )) ,  aux_rssi = ((  %d ))\n",
+				  i, fat_tab->aux_ant_cnt[i],
+				  fat_tab->aux_ant_cnt_cck[i], aux_rssi);
+#if 0
+			/* PHYDM_DBG(dm,DBG_ANT_DIV, "*** MAC ID:[ %d ] , target_ant = (( %s ))\n", i ,( target_ant ==MAIN_ANT)?"MAIN_ANT":"AUX_ANT"); */
+#endif
+
+			local_max_rssi = (main_rssi > aux_rssi) ? main_rssi : aux_rssi;
+			/* @2 Select max_rssi for DIG */
+			if (local_max_rssi > ant_div_max_rssi && local_max_rssi < 40)
+				ant_div_max_rssi = local_max_rssi;
+			if (local_max_rssi > max_rssi)
+				max_rssi = local_max_rssi;
+
+			/* @2 Select RX Idle Antenna */
+			if (local_max_rssi != 0 && local_max_rssi < min_max_rssi) {
+				rx_idle_ant = target_ant;
+				min_max_rssi = local_max_rssi;
+			}
+
+#ifdef ODM_EVM_ENHANCE_ANTDIV
+			if (dm->antdiv_evm_en == 1) {
+				if (fat_tab->target_ant_enhance != 0xFF) {
+					target_ant = fat_tab->target_ant_enhance;
+					rx_idle_ant = fat_tab->target_ant_enhance;
+				}
+			}
+#endif
+
+			/* @2 Select TX Antenna */
+			if (dm->ant_div_type != CGCS_RX_HW_ANTDIV) {
+#if (BEAMFORMING_SUPPORT == 1)
+#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
+				if (dm_bdc_table->w_bfee_client[i] == 0)
+#endif
+#endif
+				{
+					odm_update_tx_ant(dm, target_ant, i);
+				}
+			}
+
+/* @------------------------------------------------------------ */
+
+#if (BEAMFORMING_SUPPORT == 1)
+#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
+
+			dm_bdc_table->num_client++;
+
+			if (dm_bdc_table->bdc_mode == BDC_MODE_2 || dm_bdc_table->bdc_mode == BDC_MODE_3) {
+				/* @2 Byte counter */
+
+				ma_rx_temp = sta->rx_moving_average_tp; /* RX  TP   ( bit /sec) */
+
+				if (dm_bdc_table->BDC_state == bdc_bfer_train_state)
+					dm_bdc_table->MA_rx_TP_DIV[i] = ma_rx_temp;
+				else
+					dm_bdc_table->MA_rx_TP[i] = ma_rx_temp;
+
+				if (ma_rx_temp < TH2 && ma_rx_temp > TH1 && local_max_rssi <= monitor_rssi_threshold) {
+					if (dm_bdc_table->w_bfer_client[i] == 1) { /* @Bfer_Target */
+						dm_bdc_table->num_bf_tar++;
+
+						if (dm_bdc_table->BDC_state == BDC_DECISION_STATE && dm_bdc_table->bdc_try_flag == 0) {
+							improve_TP_temp = (dm_bdc_table->MA_rx_TP_DIV[i] * 9) >> 3; /* @* 1.125 */
+							dm_bdc_table->BF_pass = (dm_bdc_table->MA_rx_TP[i] > improve_TP_temp) ? true : false;
+							PHYDM_DBG(dm, DBG_ANT_DIV, "*** Client[ %d ] :  { MA_rx_TP,improve_TP_temp, MA_rx_TP_DIV,  BF_pass}={ %d,  %d, %d , %d }\n", i, dm_bdc_table->MA_rx_TP[i], improve_TP_temp, dm_bdc_table->MA_rx_TP_DIV[i], dm_bdc_table->BF_pass);
+						}
+					} else { /* @DIV_Target */
+						dm_bdc_table->num_div_tar++;
+
+						if (dm_bdc_table->BDC_state == BDC_DECISION_STATE && dm_bdc_table->bdc_try_flag == 0) {
+							degrade_TP_temp = (dm_bdc_table->MA_rx_TP_DIV[i] * 5) >> 3; /* @* 0.625 */
+							dm_bdc_table->DIV_pass = (dm_bdc_table->MA_rx_TP[i] > degrade_TP_temp) ? true : false;
+							PHYDM_DBG(dm, DBG_ANT_DIV, "*** Client[ %d ] :  { MA_rx_TP, degrade_TP_temp, MA_rx_TP_DIV,  DIV_pass}=\n{ %d,  %d, %d , %d }\n", i, dm_bdc_table->MA_rx_TP[i], degrade_TP_temp, dm_bdc_table->MA_rx_TP_DIV[i], dm_bdc_table->DIV_pass);
+						}
+					}
+				}
+
+				if (ma_rx_temp > TH1) {
+					if (dm_bdc_table->w_bfer_client[i] == 1) /* @Bfer_Target */
+						dm_bdc_table->is_all_bf_sta_idle = false;
+					else /* @DIV_Target */
+						dm_bdc_table->is_all_div_sta_idle = false;
+				}
+
+				PHYDM_DBG(dm, DBG_ANT_DIV,
+					  "*** Client[ %d ] :  { BFmeeCap, BFmerCap}  = { %d , %d }\n",
+					  i, dm_bdc_table->w_bfee_client[i],
+					  dm_bdc_table->w_bfer_client[i]);
+
+				if (dm_bdc_table->BDC_state == bdc_bfer_train_state)
+					PHYDM_DBG(dm, DBG_ANT_DIV, "*** Client[ %d ] :    MA_rx_TP_DIV = (( %d ))\n", i, dm_bdc_table->MA_rx_TP_DIV[i]);
+
+				else
+					PHYDM_DBG(dm, DBG_ANT_DIV, "*** Client[ %d ] :    MA_rx_TP = (( %d ))\n", i, dm_bdc_table->MA_rx_TP[i]);
+			}
+#endif
+#endif
+		}
+
+#if (BEAMFORMING_SUPPORT == 1)
+#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
+		if (dm_bdc_table->bdc_try_flag == 0)
+#endif
+#endif
+		{
+			phydm_antdiv_reset_statistic(dm, i);
+		}
+	}
+
+/* @2 Set RX Idle Antenna & TX Antenna(Because of HW Bug ) */
+#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
+	PHYDM_DBG(dm, DBG_ANT_DIV, "*** rx_idle_ant = (( %s ))\n",
+		  (rx_idle_ant == MAIN_ANT) ? "MAIN_ANT" : "AUX_ANT");
+
+#if (BEAMFORMING_SUPPORT == 1)
+#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
+	if (dm_bdc_table->bdc_mode == BDC_MODE_1 || dm_bdc_table->bdc_mode == BDC_MODE_3) {
+		PHYDM_DBG(dm, DBG_ANT_DIV,
+			  "*** bdc_rx_idle_update_counter = (( %d ))\n",
+			  dm_bdc_table->bdc_rx_idle_update_counter);
+
+		if (dm_bdc_table->bdc_rx_idle_update_counter == 1) {
+			PHYDM_DBG(dm, DBG_ANT_DIV,
+				  "***Update RxIdle Antenna!!!\n");
+			dm_bdc_table->bdc_rx_idle_update_counter = 30;
+			odm_update_rx_idle_ant(dm, rx_idle_ant);
+		} else {
+			dm_bdc_table->bdc_rx_idle_update_counter--;
+			PHYDM_DBG(dm, DBG_ANT_DIV,
+				  "***NOT update RxIdle Antenna because of BF  ( need to fix TX-ant)\n");
+		}
+	} else
+#endif
+#endif
+		odm_update_rx_idle_ant(dm, rx_idle_ant);
+#else
+
+	odm_update_rx_idle_ant(dm, rx_idle_ant);
+
+#endif /* @#if(DM_ODM_SUPPORT_TYPE  == ODM_AP) */
+
+/* @2 BDC Main Algorithm */
+#if (BEAMFORMING_SUPPORT == 1)
+#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
+	if (dm->antdiv_evm_en == 0 || fat_tab->evm_method_enable == 0)
+		odm_bd_ccoex_bfee_rx_div_arbitration(dm);
+
+	dm_bdc_table->num_txbfee_client = 0;
+	dm_bdc_table->num_txbfer_client = 0;
+#endif
+#endif
+
+	if (ant_div_max_rssi == 0)
+		dig_t->ant_div_rssi_max = dm->rssi_min;
+	else
+		dig_t->ant_div_rssi_max = ant_div_max_rssi;
+
+	PHYDM_DBG(dm, DBG_ANT_DIV, "***AntDiv End***\n\n");
+}
+
+#ifdef CONFIG_S0S1_SW_ANTENNA_DIVERSITY
+
+void odm_s0s1_sw_ant_div_reset(
+	void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct sw_antenna_switch *dm_swat_table = &dm->dm_swat_table;
+	struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
+
+	fat_tab->is_become_linked = false;
+	dm_swat_table->try_flag = SWAW_STEP_INIT;
+	dm_swat_table->double_chk_flag = 0;
+
+	PHYDM_DBG(dm, DBG_ANT_DIV, "%s: fat_tab->is_become_linked = %d\n",
+		  __func__, fat_tab->is_become_linked);
+}
+
+void odm_s0s1_sw_ant_div(
+	void *dm_void,
+	u8 step)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct sw_antenna_switch *dm_swat_table = &dm->dm_swat_table;
+	struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
+	u32 i, min_max_rssi = 0xFF, local_max_rssi, local_min_rssi;
+	u32 main_rssi, aux_rssi;
+	u8 high_traffic_train_time_u = 0x32, high_traffic_train_time_l = 0, train_time_temp;
+	u8 low_traffic_train_time_u = 200, low_traffic_train_time_l = 0;
+	u8 rx_idle_ant = dm_swat_table->pre_antenna, target_ant = dm_swat_table->pre_antenna, next_ant = 0;
+	struct cmn_sta_info *entry = NULL;
+	u32 value32;
+	u32 main_ant_sum = 0;
+	u32 aux_ant_sum = 0;
+	u32 main_ant_cnt = 0;
+	u32 aux_ant_cnt = 0;
+
+	if (!dm->is_linked) { /* @is_linked==False */
+		PHYDM_DBG(dm, DBG_ANT_DIV, "[No Link!!!]\n");
+		if (fat_tab->is_become_linked == true) {
+			odm_tx_by_tx_desc_or_reg(dm, TX_BY_REG);
+			if (dm->support_ic_type == ODM_RTL8723B) {
+				PHYDM_DBG(dm, DBG_ANT_DIV,
+					  "Set REG 948[9:6]=0x0\n");
+				odm_set_bb_reg(dm, R_0x948, (BIT(9) | BIT(8) | BIT(7) | BIT(6)), 0x0);
+			}
+			fat_tab->is_become_linked = dm->is_linked;
+		}
+		return;
+	} else {
+		if (fat_tab->is_become_linked == false) {
+			PHYDM_DBG(dm, DBG_ANT_DIV, "[Linked !!!]\n");
+
+			if (dm->support_ic_type == ODM_RTL8723B) {
+				value32 = odm_get_bb_reg(dm, R_0x864, BIT(5) | BIT(4) | BIT(3));
+
+#if (RTL8723B_SUPPORT == 1)
+				if (value32 == 0x0)
+					odm_update_rx_idle_ant_8723b(dm, MAIN_ANT, ANT1_2G, ANT2_2G);
+				else if (value32 == 0x1)
+					odm_update_rx_idle_ant_8723b(dm, AUX_ANT, ANT2_2G, ANT1_2G);
+#endif
+
+				PHYDM_DBG(dm, DBG_ANT_DIV,
+					  "8723B: First link! Force antenna to  %s\n",
+					  (value32 == 0x0 ? "MAIN" : "AUX"));
+			}
+
+			if (dm->support_ic_type == ODM_RTL8723D) {
+				value32 = odm_get_bb_reg(dm, R_0x864, BIT(5) | BIT(4) | BIT(3));
+#if (RTL8723D_SUPPORT == 1)
+				if (value32 == 0x0)
+					odm_update_rx_idle_ant_8723d(dm, MAIN_ANT, ANT1_2G, ANT2_2G);
+				else if (value32 == 0x1)
+					odm_update_rx_idle_ant_8723d(dm, AUX_ANT, ANT2_2G, ANT1_2G);
+				PHYDM_DBG(dm, DBG_ANT_DIV,
+					  "8723D: First link! Force antenna to  %s\n",
+					  (value32 == 0x0 ? "MAIN" : "AUX"));
+#endif
+			}
+			fat_tab->is_become_linked = dm->is_linked;
+		}
+	}
+
+	if (*fat_tab->p_force_tx_ant_by_desc == false) {
+		if (dm->is_one_entry_only == true)
+			odm_tx_by_tx_desc_or_reg(dm, TX_BY_REG);
+		else
+			odm_tx_by_tx_desc_or_reg(dm, TX_BY_DESC);
+	}
+
+	PHYDM_DBG(dm, DBG_ANT_DIV,
+		  "[%d] { try_flag=(( %d )), step=(( %d )), double_chk_flag = (( %d )) }\n",
+		  __LINE__, dm_swat_table->try_flag, step,
+		  dm_swat_table->double_chk_flag);
+
+	/* @Handling step mismatch condition. */
+	/* Peak step is not finished at last time. Recover the variable and check again. */
+	if (step != dm_swat_table->try_flag) {
+		PHYDM_DBG(dm, DBG_ANT_DIV,
+			  "[step != try_flag]    Need to Reset After Link\n");
+		odm_sw_ant_div_rest_after_link(dm);
+	}
+
+	if (dm_swat_table->try_flag == SWAW_STEP_INIT) {
+		dm_swat_table->try_flag = SWAW_STEP_PEEK;
+		dm_swat_table->train_time_flag = 0;
+		PHYDM_DBG(dm, DBG_ANT_DIV,
+			  "[set try_flag = 0]  Prepare for peek!\n\n");
+		return;
+
+	} else {
+		/* @1 Normal state (Begin Trying) */
+		if (dm_swat_table->try_flag == SWAW_STEP_PEEK) {
+			PHYDM_DBG(dm, DBG_ANT_DIV,
+				  "TxOkCnt=(( %llu )), RxOkCnt=(( %llu )), traffic_load = (%d))\n",
+				  dm->cur_tx_ok_cnt, dm->cur_rx_ok_cnt,
+				  dm->traffic_load);
+
+			if (dm->traffic_load == TRAFFIC_HIGH) {
+				train_time_temp = dm_swat_table->train_time;
+
+				if (dm_swat_table->train_time_flag == 3) {
+					high_traffic_train_time_l = 0xa;
+
+					if (train_time_temp <= 16)
+						train_time_temp = high_traffic_train_time_l;
+					else
+						train_time_temp -= 16;
+
+				} else if (dm_swat_table->train_time_flag == 2) {
+					train_time_temp -= 8;
+					high_traffic_train_time_l = 0xf;
+				} else if (dm_swat_table->train_time_flag == 1) {
+					train_time_temp -= 4;
+					high_traffic_train_time_l = 0x1e;
+				} else if (dm_swat_table->train_time_flag == 0) {
+					train_time_temp += 8;
+					high_traffic_train_time_l = 0x28;
+				}
+
+				if (dm->support_ic_type == ODM_RTL8188F) {
+					if (dm->support_interface == ODM_ITRF_SDIO)
+						high_traffic_train_time_l += 0xa;
+				}
+
+#if 0
+				/* PHYDM_DBG(dm,DBG_ANT_DIV, "*** train_time_temp = ((%d))\n",train_time_temp); */
+#endif
+
+				/* @-- */
+				if (train_time_temp > high_traffic_train_time_u)
+					train_time_temp = high_traffic_train_time_u;
+
+				else if (train_time_temp < high_traffic_train_time_l)
+					train_time_temp = high_traffic_train_time_l;
+
+				dm_swat_table->train_time = train_time_temp; /*@10ms~200ms*/
+
+				PHYDM_DBG(dm, DBG_ANT_DIV,
+					  "train_time_flag=((%d)), train_time=((%d))\n",
+					  dm_swat_table->train_time_flag,
+					  dm_swat_table->train_time);
+
+			} else if ((dm->traffic_load == TRAFFIC_MID) || (dm->traffic_load == TRAFFIC_LOW)) {
+				train_time_temp = dm_swat_table->train_time;
+
+				if (dm_swat_table->train_time_flag == 3) {
+					low_traffic_train_time_l = 10;
+					if (train_time_temp < 50)
+						train_time_temp = low_traffic_train_time_l;
+					else
+						train_time_temp -= 50;
+				} else if (dm_swat_table->train_time_flag == 2) {
+					train_time_temp -= 30;
+					low_traffic_train_time_l = 36;
+				} else if (dm_swat_table->train_time_flag == 1) {
+					train_time_temp -= 10;
+					low_traffic_train_time_l = 40;
+				} else {
+					train_time_temp += 10;
+					low_traffic_train_time_l = 50;
+				}
+
+				if (dm->support_ic_type == ODM_RTL8188F) {
+					if (dm->support_interface == ODM_ITRF_SDIO)
+						low_traffic_train_time_l += 10;
+				}
+
+				/* @-- */
+				if (train_time_temp >= low_traffic_train_time_u)
+					train_time_temp = low_traffic_train_time_u;
+
+				else if (train_time_temp <= low_traffic_train_time_l)
+					train_time_temp = low_traffic_train_time_l;
+
+				dm_swat_table->train_time = train_time_temp; /*@10ms~200ms*/
+
+				PHYDM_DBG(dm, DBG_ANT_DIV,
+					  "train_time_flag=((%d)) , train_time=((%d))\n",
+					  dm_swat_table->train_time_flag,
+					  dm_swat_table->train_time);
+
+			} else {
+				dm_swat_table->train_time = 0xc8; /*@200ms*/
+			}
+
+			/* @----------------- */
+
+			PHYDM_DBG(dm, DBG_ANT_DIV,
+				  "Current min_max_rssi is ((%d))\n",
+				  fat_tab->min_max_rssi);
+
+			/* @---reset index--- */
+			if (dm_swat_table->reset_idx >= RSSI_CHECK_RESET_PERIOD) {
+				fat_tab->min_max_rssi = 0;
+				dm_swat_table->reset_idx = 0;
+			}
+			PHYDM_DBG(dm, DBG_ANT_DIV, "reset_idx = (( %d ))\n",
+				  dm_swat_table->reset_idx);
+
+			dm_swat_table->reset_idx++;
+
+			/* @---double check flag--- */
+			if (fat_tab->min_max_rssi > RSSI_CHECK_THRESHOLD && dm_swat_table->double_chk_flag == 0) {
+				PHYDM_DBG(dm, DBG_ANT_DIV,
+					  " min_max_rssi is ((%d)), and > %d\n",
+					  fat_tab->min_max_rssi,
+					  RSSI_CHECK_THRESHOLD);
+
+				dm_swat_table->double_chk_flag = 1;
+				dm_swat_table->try_flag = SWAW_STEP_DETERMINE;
+				dm_swat_table->rssi_trying = 0;
+
+				PHYDM_DBG(dm, DBG_ANT_DIV,
+					  "Test the current ant for (( %d )) ms again\n",
+					  dm_swat_table->train_time);
+				odm_update_rx_idle_ant(dm, fat_tab->rx_idle_ant);
+			odm_set_timer(dm, &dm_swat_table->phydm_sw_antenna_switch_timer, dm_swat_table->train_time); /*@ms*/
+			return;
+			}
+
+			next_ant = (fat_tab->rx_idle_ant == MAIN_ANT) ? AUX_ANT : MAIN_ANT;
+
+			dm_swat_table->try_flag = SWAW_STEP_DETERMINE;
+
+			if (dm_swat_table->reset_idx <= 1)
+				dm_swat_table->rssi_trying = 2;
+			else
+				dm_swat_table->rssi_trying = 1;
+
+			odm_s0s1_sw_ant_div_by_ctrl_frame(dm, SWAW_STEP_PEEK);
+			PHYDM_DBG(dm, DBG_ANT_DIV,
+				  "[set try_flag=1]  Normal state:  Begin Trying!!\n");
+
+		} else if ((dm_swat_table->try_flag == SWAW_STEP_DETERMINE) && (dm_swat_table->double_chk_flag == 0)) {
+			next_ant = (fat_tab->rx_idle_ant == MAIN_ANT) ? AUX_ANT : MAIN_ANT;
+			dm_swat_table->rssi_trying--;
+		}
+
+		/* @1 Decision state */
+		if (dm_swat_table->try_flag == SWAW_STEP_DETERMINE && dm_swat_table->rssi_trying == 0) {
+			boolean is_by_ctrl_frame = false;
+			u64 pkt_cnt_total = 0;
+
+			for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) {
+				entry = dm->phydm_sta_info[i];
+				if (is_sta_active(entry)) {
+/* @2 Caculate RSSI per Antenna */
+					#if 0
+					main_ant_sum = (u32)fat_tab->main_ant_sum[i] + (u32)fat_tab->main_ant_sum_cck[i];
+					aux_ant_sum = (u32)fat_tab->aux_ant_sum[i] + (u32)fat_tab->aux_ant_sum_cck[i];
+					main_ant_cnt = (u32)fat_tab->main_ant_cnt[i] + (u32)fat_tab->main_ant_cnt_cck[i];
+					aux_ant_cnt = (u32)fat_tab->aux_ant_cnt[i] + (u32)fat_tab->aux_ant_cnt_cck[i];
+
+					main_rssi = (main_ant_cnt != 0) ? (main_ant_sum / main_ant_cnt) : 0;
+					aux_rssi = (aux_ant_cnt != 0) ? (aux_ant_sum / aux_ant_cnt) : 0;
+
+					if (fat_tab->main_ant_cnt[i] <= 1 && fat_tab->main_ant_cnt_cck[i] >= 1)
+						main_rssi = 0;
+
+					if (fat_tab->aux_ant_cnt[i] <= 1 && fat_tab->aux_ant_cnt_cck[i] >= 1)
+						aux_rssi = 0;
+					#endif
+					if (fat_tab->main_ant_cnt[i] != 0 || fat_tab->aux_ant_cnt[i] != 0) {
+						main_ant_cnt = (u32)fat_tab->main_ant_cnt[i];
+						aux_ant_cnt = (u32)fat_tab->aux_ant_cnt[i];
+						main_rssi = (main_ant_cnt != 0) ? (fat_tab->main_ant_sum[i] / main_ant_cnt) : 0;
+						aux_rssi = (aux_ant_cnt != 0) ? (fat_tab->aux_ant_sum[i] / aux_ant_cnt) : 0;
+						if (dm->support_ic_type == ODM_RTL8723D) {
+							if (dm_swat_table->pre_antenna == MAIN_ANT) {
+								if (main_ant_cnt == 0)
+									target_ant = (aux_ant_cnt != 0) ? AUX_ANT : dm_swat_table->pre_antenna;
+								else
+									target_ant = ((aux_ant_cnt > main_ant_cnt) && ((main_rssi - aux_rssi < 5) || (aux_rssi > main_rssi))) ? AUX_ANT : dm_swat_table->pre_antenna;
+							} else {
+								if (aux_ant_cnt == 0)
+									target_ant = (main_ant_cnt != 0) ? MAIN_ANT : dm_swat_table->pre_antenna;
+								else
+									target_ant = ((main_ant_cnt > aux_ant_cnt) && ((aux_rssi - main_rssi < 5) || (main_rssi > aux_rssi))) ? MAIN_ANT : dm_swat_table->pre_antenna;
+							}
+						} else {
+							if (dm_swat_table->pre_antenna == MAIN_ANT) {
+								target_ant = ((aux_ant_cnt > 20) && (aux_rssi >= main_rssi)) ? AUX_ANT : dm_swat_table->pre_antenna;
+							} else if (dm_swat_table->pre_antenna == AUX_ANT) {
+								target_ant = ((main_ant_cnt > 20) && (main_rssi >= aux_rssi)) ? MAIN_ANT : dm_swat_table->pre_antenna;
+							}
+						}
+					} else { /*@CCK only case*/
+						main_ant_cnt = fat_tab->main_ant_cnt_cck[i];
+						aux_ant_cnt = fat_tab->aux_ant_cnt_cck[i];
+						main_rssi = (main_ant_cnt != 0) ? (fat_tab->main_ant_sum_cck[i] / main_ant_cnt) : 0;
+						aux_rssi = (aux_ant_cnt != 0) ? (fat_tab->aux_ant_sum_cck[i] / aux_ant_cnt) : 0;
+						target_ant = (main_rssi == aux_rssi) ? fat_tab->rx_idle_ant : ((main_rssi >= aux_rssi) ? MAIN_ANT : AUX_ANT); /*Use RSSI for CCK only case*/
+					}
+					#if 0
+					target_ant = (main_rssi == aux_rssi) ? dm_swat_table->pre_antenna : ((main_rssi >= aux_rssi) ? MAIN_ANT : AUX_ANT);
+					#endif
+					local_max_rssi = (main_rssi >= aux_rssi) ? main_rssi : aux_rssi;
+					local_min_rssi = (main_rssi >= aux_rssi) ? aux_rssi : main_rssi;
+
+					PHYDM_DBG(dm, DBG_ANT_DIV, "***  CCK_counter_main = (( %d ))  , CCK_counter_aux= ((  %d ))\n", fat_tab->main_ant_cnt_cck[i], fat_tab->aux_ant_cnt_cck[i]);
+					PHYDM_DBG(dm, DBG_ANT_DIV, "***  OFDM_counter_main = (( %d ))  , OFDM_counter_aux= ((  %d ))\n", fat_tab->main_ant_cnt[i], fat_tab->aux_ant_cnt[i]);
+					PHYDM_DBG(dm, DBG_ANT_DIV, "***  main_Cnt = (( %d ))  , aux_Cnt   = (( %d ))\n", main_ant_cnt, aux_ant_cnt);
+					PHYDM_DBG(dm, DBG_ANT_DIV, "***  main_rssi= ((  %d )) , aux_rssi = ((  %d ))\n", main_rssi, aux_rssi);
+					PHYDM_DBG(dm, DBG_ANT_DIV, "*** MAC ID:[ %d ] , target_ant = (( %s ))\n", i, (target_ant == MAIN_ANT) ? "MAIN_ANT" : "AUX_ANT");
+
+					/* @2 Select RX Idle Antenna */
+
+					if (local_max_rssi != 0 && local_max_rssi < min_max_rssi) {
+						rx_idle_ant = target_ant;
+						min_max_rssi = local_max_rssi;
+						PHYDM_DBG(dm, DBG_ANT_DIV, "*** local_max_rssi-local_min_rssi = ((%d))\n", (local_max_rssi - local_min_rssi));
+
+						if ((local_max_rssi - local_min_rssi) > 8) {
+							if (local_min_rssi != 0)
+								dm_swat_table->train_time_flag = 3;
+							else {
+								if (min_max_rssi > RSSI_CHECK_THRESHOLD)
+									dm_swat_table->train_time_flag = 0;
+								else
+									dm_swat_table->train_time_flag = 3;
+							}
+						} else if ((local_max_rssi - local_min_rssi) > 5)
+							dm_swat_table->train_time_flag = 2;
+						else if ((local_max_rssi - local_min_rssi) > 2)
+							dm_swat_table->train_time_flag = 1;
+						else
+							dm_swat_table->train_time_flag = 0;
+					}
+
+					/* @2 Select TX Antenna */
+					if (target_ant == MAIN_ANT)
+						fat_tab->antsel_a[i] = ANT1_2G;
+					else
+						fat_tab->antsel_a[i] = ANT2_2G;
+				}
+				phydm_antdiv_reset_statistic(dm, i);
+				pkt_cnt_total += (main_ant_cnt + aux_ant_cnt);
+			}
+
+			if (dm_swat_table->is_sw_ant_div_by_ctrl_frame) {
+				odm_s0s1_sw_ant_div_by_ctrl_frame(dm, SWAW_STEP_DETERMINE);
+				is_by_ctrl_frame = true;
+			}
+
+			PHYDM_DBG(dm, DBG_ANT_DIV,
+				  "Control frame packet counter = %d, data frame packet counter = %llu\n",
+				  dm_swat_table->
+				  pkt_cnt_sw_ant_div_by_ctrl_frame,
+				  pkt_cnt_total);
+
+			if (min_max_rssi == 0xff || ((pkt_cnt_total < (dm_swat_table->pkt_cnt_sw_ant_div_by_ctrl_frame >> 1)) && dm->phy_dbg_info.num_qry_beacon_pkt < 2)) {
+				min_max_rssi = 0;
+				PHYDM_DBG(dm, DBG_ANT_DIV,
+					  "Check RSSI of control frame because min_max_rssi == 0xff\n");
+				PHYDM_DBG(dm, DBG_ANT_DIV,
+					  "is_by_ctrl_frame = %d\n",
+					  is_by_ctrl_frame);
+
+				if (is_by_ctrl_frame) {
+					main_rssi = (fat_tab->main_ant_ctrl_frame_cnt != 0) ? (fat_tab->main_ant_ctrl_frame_sum / fat_tab->main_ant_ctrl_frame_cnt) : 0;
+					aux_rssi = (fat_tab->aux_ant_ctrl_frame_cnt != 0) ? (fat_tab->aux_ant_ctrl_frame_sum / fat_tab->aux_ant_ctrl_frame_cnt) : 0;
+
+					if (fat_tab->main_ant_ctrl_frame_cnt <= 1 && fat_tab->cck_ctrl_frame_cnt_main >= 1)
+						main_rssi = 0;
+
+					if (fat_tab->aux_ant_ctrl_frame_cnt <= 1 && fat_tab->cck_ctrl_frame_cnt_aux >= 1)
+						aux_rssi = 0;
+
+					if (main_rssi != 0 || aux_rssi != 0) {
+						rx_idle_ant = (main_rssi == aux_rssi) ? dm_swat_table->pre_antenna : ((main_rssi >= aux_rssi) ? MAIN_ANT : AUX_ANT);
+						local_max_rssi = (main_rssi >= aux_rssi) ? main_rssi : aux_rssi;
+						local_min_rssi = (main_rssi >= aux_rssi) ? aux_rssi : main_rssi;
+
+						if ((local_max_rssi - local_min_rssi) > 8)
+							dm_swat_table->train_time_flag = 3;
+						else if ((local_max_rssi - local_min_rssi) > 5)
+							dm_swat_table->train_time_flag = 2;
+						else if ((local_max_rssi - local_min_rssi) > 2)
+							dm_swat_table->train_time_flag = 1;
+						else
+							dm_swat_table->train_time_flag = 0;
+
+						PHYDM_DBG(dm, DBG_ANT_DIV, "Control frame: main_rssi = %d, aux_rssi = %d\n", main_rssi, aux_rssi);
+						PHYDM_DBG(dm, DBG_ANT_DIV, "rx_idle_ant decided by control frame = %s\n", (rx_idle_ant == MAIN_ANT ? "MAIN" : "AUX"));
+					}
+				}
+			}
+
+			fat_tab->min_max_rssi = min_max_rssi;
+			dm_swat_table->try_flag = SWAW_STEP_PEEK;
+
+			if (dm_swat_table->double_chk_flag == 1) {
+				dm_swat_table->double_chk_flag = 0;
+
+				if (fat_tab->min_max_rssi > RSSI_CHECK_THRESHOLD) {
+					PHYDM_DBG(dm, DBG_ANT_DIV, " [Double check] min_max_rssi ((%d)) > %d again!!\n",
+						  fat_tab->min_max_rssi, RSSI_CHECK_THRESHOLD);
+
+					odm_update_rx_idle_ant(dm, rx_idle_ant);
+
+					PHYDM_DBG(dm, DBG_ANT_DIV, "[reset try_flag = 0] Training accomplished !!!]\n\n\n");
+					return;
+				} else {
+					PHYDM_DBG(dm, DBG_ANT_DIV, " [Double check] min_max_rssi ((%d)) <= %d !!\n",
+						  fat_tab->min_max_rssi, RSSI_CHECK_THRESHOLD);
+
+					next_ant = (fat_tab->rx_idle_ant == MAIN_ANT) ? AUX_ANT : MAIN_ANT;
+					dm_swat_table->try_flag = SWAW_STEP_PEEK;
+					dm_swat_table->reset_idx = RSSI_CHECK_RESET_PERIOD;
+					PHYDM_DBG(dm, DBG_ANT_DIV, "[set try_flag=0]  Normal state:  Need to tryg again!!\n\n\n");
+					return;
+				}
+			} else {
+				if (fat_tab->min_max_rssi < RSSI_CHECK_THRESHOLD)
+					dm_swat_table->reset_idx = RSSI_CHECK_RESET_PERIOD;
+
+				dm_swat_table->pre_antenna = rx_idle_ant;
+				odm_update_rx_idle_ant(dm, rx_idle_ant);
+				PHYDM_DBG(dm, DBG_ANT_DIV,
+					  "[reset try_flag = 0] Training accomplished !!!]\n\n\n");
+				return;
+			}
+		}
+	}
+
+	/* @1 4.Change TRX antenna */
+
+	PHYDM_DBG(dm, DBG_ANT_DIV,
+		  "rssi_trying = (( %d )),    ant: (( %s )) >>> (( %s ))\n",
+		  dm_swat_table->rssi_trying,
+		  (fat_tab->rx_idle_ant == MAIN_ANT ? "MAIN" : "AUX"),
+		  (next_ant == MAIN_ANT ? "MAIN" : "AUX"));
+
+	odm_update_rx_idle_ant(dm, next_ant);
+
+	/* @1 5.Reset Statistics */
+
+	fat_tab->rx_idle_ant = next_ant;
+
+	if (dm->support_ic_type == ODM_RTL8723D) {
+		if (fat_tab->rx_idle_ant == MAIN_ANT) {
+			fat_tab->main_ant_sum[0] = 0;
+			fat_tab->main_ant_cnt[0] = 0;
+			fat_tab->main_ant_sum_cck[0] = 0;
+			fat_tab->main_ant_cnt_cck[0] = 0;
+		} else {
+			fat_tab->aux_ant_sum[0] = 0;
+			fat_tab->aux_ant_cnt[0] = 0;
+			fat_tab->aux_ant_sum_cck[0] = 0;
+			fat_tab->aux_ant_cnt_cck[0] = 0;
+		}
+	}
+
+	if (dm->support_ic_type == ODM_RTL8188F) {
+		if (dm->support_interface == ODM_ITRF_SDIO) {
+			ODM_delay_us(200);
+
+			if (fat_tab->rx_idle_ant == MAIN_ANT) {
+				fat_tab->main_ant_sum[0] = 0;
+				fat_tab->main_ant_cnt[0] = 0;
+				fat_tab->main_ant_sum_cck[0] = 0;
+				fat_tab->main_ant_cnt_cck[0] = 0;
+			} else {
+				fat_tab->aux_ant_sum[0] = 0;
+				fat_tab->aux_ant_cnt[0] = 0;
+				fat_tab->aux_ant_sum_cck[0] = 0;
+				fat_tab->aux_ant_cnt_cck[0] = 0;
+			}
+		}
+	}
+	/* @1 6.Set next timer   (Trying state) */
+	PHYDM_DBG(dm, DBG_ANT_DIV, " Test ((%s)) ant for (( %d )) ms\n",
+		  (next_ant == MAIN_ANT ? "MAIN" : "AUX"),
+		  dm_swat_table->train_time);
+	odm_set_timer(dm, &dm_swat_table->phydm_sw_antenna_switch_timer,
+		      dm_swat_table->train_time); /*@ms*/
+}
+
+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
+void odm_sw_antdiv_callback(
+	struct phydm_timer_list *timer)
+{
+	void *adapter = (void *)timer->Adapter;
+	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter));
+	struct sw_antenna_switch *dm_swat_table = &hal_data->DM_OutSrc.dm_swat_table;
+
+#if DEV_BUS_TYPE == RT_PCI_INTERFACE
+#if USE_WORKITEM
+	odm_schedule_work_item(&dm_swat_table->phydm_sw_antenna_switch_workitem);
+#else
+	{
+#if 0
+		/* @dbg_print("SW_antdiv_Callback"); */
+#endif
+		odm_s0s1_sw_ant_div(&hal_data->DM_OutSrc, SWAW_STEP_DETERMINE);
+	}
+#endif
+#else
+	odm_schedule_work_item(&dm_swat_table->phydm_sw_antenna_switch_workitem);
+#endif
+}
+void odm_sw_antdiv_workitem_callback(
+	void *context)
+{
+	void *adapter = (void *)context;
+	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter));
+
+#if 0
+	/* @dbg_print("SW_antdiv_Workitem_Callback"); */
+#endif
+	odm_s0s1_sw_ant_div(&hal_data->DM_OutSrc, SWAW_STEP_DETERMINE);
+}
+
+#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
+
+void odm_sw_antdiv_workitem_callback(
+	void *context)
+{
+	void *
+		adapter = (void *)context;
+	HAL_DATA_TYPE
+	*hal_data = GET_HAL_DATA(((PADAPTER)adapter));
+
+#if 0
+	/*@dbg_print("SW_antdiv_Workitem_Callback");*/
+#endif
+	odm_s0s1_sw_ant_div(&hal_data->odmpriv, SWAW_STEP_DETERMINE);
+}
+
+void odm_sw_antdiv_callback(void *function_context)
+{
+	struct dm_struct *dm = (struct dm_struct *)function_context;
+	void *padapter = dm->adapter;
+	if (*dm->is_net_closed == true)
+		return;
+
+#if 0 /* @Can't do I/O in timer callback*/
+	odm_s0s1_sw_ant_div(dm, SWAW_STEP_DETERMINE);
+#else
+	rtw_run_in_thread_cmd(padapter, odm_sw_antdiv_workitem_callback, padapter);
+#endif
+}
+
+#endif
+
+void odm_s0s1_sw_ant_div_by_ctrl_frame(
+	void *dm_void,
+	u8 step)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct sw_antenna_switch *dm_swat_table = &dm->dm_swat_table;
+	struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
+
+	switch (step) {
+	case SWAW_STEP_PEEK:
+		dm_swat_table->pkt_cnt_sw_ant_div_by_ctrl_frame = 0;
+		dm_swat_table->is_sw_ant_div_by_ctrl_frame = true;
+		fat_tab->main_ant_ctrl_frame_cnt = 0;
+		fat_tab->aux_ant_ctrl_frame_cnt = 0;
+		fat_tab->main_ant_ctrl_frame_sum = 0;
+		fat_tab->aux_ant_ctrl_frame_sum = 0;
+		fat_tab->cck_ctrl_frame_cnt_main = 0;
+		fat_tab->cck_ctrl_frame_cnt_aux = 0;
+		fat_tab->ofdm_ctrl_frame_cnt_main = 0;
+		fat_tab->ofdm_ctrl_frame_cnt_aux = 0;
+		PHYDM_DBG(dm, DBG_ANT_DIV,
+			  "odm_S0S1_SwAntDivForAPMode(): Start peek and reset counter\n");
+		break;
+	case SWAW_STEP_DETERMINE:
+		dm_swat_table->is_sw_ant_div_by_ctrl_frame = false;
+		PHYDM_DBG(dm, DBG_ANT_DIV,
+			  "odm_S0S1_SwAntDivForAPMode(): Stop peek\n");
+		break;
+	default:
+		dm_swat_table->is_sw_ant_div_by_ctrl_frame = false;
+		break;
+	}
+}
+
+void odm_antsel_statistics_of_ctrl_frame(
+	void *dm_void,
+	u8 antsel_tr_mux,
+	u32 rx_pwdb_all
+
+	)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
+
+	if (antsel_tr_mux == ANT1_2G) {
+		fat_tab->main_ant_ctrl_frame_sum += rx_pwdb_all;
+		fat_tab->main_ant_ctrl_frame_cnt++;
+	} else {
+		fat_tab->aux_ant_ctrl_frame_sum += rx_pwdb_all;
+		fat_tab->aux_ant_ctrl_frame_cnt++;
+	}
+}
+
+void odm_s0s1_sw_ant_div_by_ctrl_frame_process_rssi(
+	void *dm_void,
+	void *phy_info_void,
+	void *pkt_info_void
+	/*	struct phydm_phyinfo_struct*		phy_info, */
+	/*	struct phydm_perpkt_info_struct*		pktinfo */
+	)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct phydm_phyinfo_struct *phy_info = (struct phydm_phyinfo_struct *)phy_info_void;
+	struct phydm_perpkt_info_struct *pktinfo = (struct phydm_perpkt_info_struct *)pkt_info_void;
+	struct sw_antenna_switch *dm_swat_table = &dm->dm_swat_table;
+	struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
+
+	if (!(dm->support_ability & ODM_BB_ANT_DIV))
+		return;
+
+	if (dm->ant_div_type != S0S1_SW_ANTDIV)
+		return;
+
+	/* @In try state */
+	if (!dm_swat_table->is_sw_ant_div_by_ctrl_frame)
+		return;
+
+	/* No HW error and match receiver address */
+	if (!pktinfo->is_to_self)
+		return;
+
+	dm_swat_table->pkt_cnt_sw_ant_div_by_ctrl_frame++;
+
+	if (pktinfo->is_cck_rate) {
+		fat_tab->antsel_rx_keep_0 = (fat_tab->rx_idle_ant == MAIN_ANT) ? ANT1_2G : ANT2_2G;
+
+		if (fat_tab->antsel_rx_keep_0 == ANT1_2G)
+			fat_tab->cck_ctrl_frame_cnt_main++;
+		else
+			fat_tab->cck_ctrl_frame_cnt_aux++;
+
+		odm_antsel_statistics_of_ctrl_frame(dm, fat_tab->antsel_rx_keep_0, phy_info->rx_mimo_signal_strength[RF_PATH_A]);
+	} else {
+		fat_tab->antsel_rx_keep_0 = (fat_tab->rx_idle_ant == MAIN_ANT) ? ANT1_2G : ANT2_2G;
+
+		if (fat_tab->antsel_rx_keep_0 == ANT1_2G)
+			fat_tab->ofdm_ctrl_frame_cnt_main++;
+		else
+			fat_tab->ofdm_ctrl_frame_cnt_aux++;
+
+		odm_antsel_statistics_of_ctrl_frame(dm, fat_tab->antsel_rx_keep_0, phy_info->rx_pwdb_all);
+	}
+}
+
+#endif /* @#if (RTL8723B_SUPPORT == 1) || (RTL8821A_SUPPORT == 1) */
+
+void odm_set_next_mac_addr_target(
+	void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
+	struct cmn_sta_info *entry;
+	u32 value32, i;
+
+	PHYDM_DBG(dm, DBG_ANT_DIV, "%s ==>\n", __func__);
+
+	if (dm->is_linked) {
+		for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) {
+			if ((fat_tab->train_idx + 1) == ODM_ASSOCIATE_ENTRY_NUM)
+				fat_tab->train_idx = 0;
+			else
+				fat_tab->train_idx++;
+
+			entry = dm->phydm_sta_info[fat_tab->train_idx];
+
+			if (is_sta_active(entry)) {
+				/*@Match MAC ADDR*/
+				value32 = (entry->mac_addr[5] << 8) | entry->mac_addr[4];
+
+				odm_set_mac_reg(dm, R_0x7b4, 0xFFFF, value32); /*@0x7b4~0x7b5*/
+
+				value32 = (entry->mac_addr[3] << 24) | (entry->mac_addr[2] << 16) | (entry->mac_addr[1] << 8) | entry->mac_addr[0];
+
+				odm_set_mac_reg(dm, R_0x7b0, MASKDWORD, value32); /*@0x7b0~0x7b3*/
+
+				PHYDM_DBG(dm, DBG_ANT_DIV,
+					  "fat_tab->train_idx=%d\n",
+					  fat_tab->train_idx);
+
+				PHYDM_DBG(dm, DBG_ANT_DIV,
+					  "Training MAC addr = %x:%x:%x:%x:%x:%x\n",
+					  entry->mac_addr[5],
+					  entry->mac_addr[4],
+					  entry->mac_addr[3],
+					  entry->mac_addr[2],
+					  entry->mac_addr[1],
+					  entry->mac_addr[0]);
+
+				break;
+			}
+		}
+	}
+}
+
+#if (defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY)) || (defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY))
+
+void odm_fast_ant_training(
+	void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
+
+	u32 max_rssi_path_a = 0, pckcnt_path_a = 0;
+	u8 i, target_ant_path_a = 0;
+	boolean is_pkt_filter_macth_path_a = false;
+#if (RTL8192E_SUPPORT == 1)
+	u32 max_rssi_path_b = 0, pckcnt_path_b = 0;
+	u8 target_ant_path_b = 0;
+	boolean is_pkt_filter_macth_path_b = false;
+#endif
+
+	if (!dm->is_linked) { /* @is_linked==False */
+		PHYDM_DBG(dm, DBG_ANT_DIV, "[No Link!!!]\n");
+
+		if (fat_tab->is_become_linked == true) {
+			odm_ant_div_on_off(dm, ANTDIV_OFF, ANT_PATH_A);
+			phydm_fast_training_enable(dm, FAT_OFF);
+			odm_tx_by_tx_desc_or_reg(dm, TX_BY_REG);
+			fat_tab->is_become_linked = dm->is_linked;
+		}
+		return;
+	} else {
+		if (fat_tab->is_become_linked == false) {
+			PHYDM_DBG(dm, DBG_ANT_DIV, "[Linked!!!]\n");
+			fat_tab->is_become_linked = dm->is_linked;
+		}
+	}
+
+	if (*fat_tab->p_force_tx_ant_by_desc == false) {
+		if (dm->is_one_entry_only == true)
+			odm_tx_by_tx_desc_or_reg(dm, TX_BY_REG);
+		else
+			odm_tx_by_tx_desc_or_reg(dm, TX_BY_DESC);
+	}
+
+	if (dm->support_ic_type == ODM_RTL8188E)
+		odm_set_bb_reg(dm, R_0x864, BIT(2) | BIT(1) | BIT(0), ((dm->fat_comb_a) - 1));
+#if (RTL8192E_SUPPORT == 1)
+	else if (dm->support_ic_type == ODM_RTL8192E) {
+		odm_set_bb_reg(dm, R_0xb38, BIT(2) | BIT(1) | BIT(0), ((dm->fat_comb_a) - 1)); /* path-A  */ /* ant combination=regB38[2:0]+1 */
+		odm_set_bb_reg(dm, R_0xb38, BIT(18) | BIT(17) | BIT(16), ((dm->fat_comb_b) - 1)); /* path-B  */ /* ant combination=regB38[18:16]+1 */
+	}
+#endif
+
+	PHYDM_DBG(dm, DBG_ANT_DIV, "==>%s\n", __func__);
+
+	/* @1 TRAINING STATE */
+	if (fat_tab->fat_state == FAT_TRAINING_STATE) {
+		/* @2 Caculate RSSI per Antenna */
+
+		/* @3 [path-A]--------------------------- */
+		for (i = 0; i < (dm->fat_comb_a); i++) { /* @i : antenna index */
+			if (fat_tab->ant_rssi_cnt[i] == 0)
+				fat_tab->ant_ave_rssi[i] = 0;
+			else {
+				fat_tab->ant_ave_rssi[i] = fat_tab->ant_sum_rssi[i] / fat_tab->ant_rssi_cnt[i];
+				is_pkt_filter_macth_path_a = true;
+			}
+
+			if (fat_tab->ant_ave_rssi[i] > max_rssi_path_a) {
+				max_rssi_path_a = fat_tab->ant_ave_rssi[i];
+				pckcnt_path_a = fat_tab->ant_rssi_cnt[i];
+				target_ant_path_a = i;
+			} else if (fat_tab->ant_ave_rssi[i] == max_rssi_path_a) {
+				if (fat_tab->ant_rssi_cnt[i] > pckcnt_path_a) {
+					max_rssi_path_a = fat_tab->ant_ave_rssi[i];
+					pckcnt_path_a = fat_tab->ant_rssi_cnt[i];
+					target_ant_path_a = i;
+				}
+			}
+
+			PHYDM_DBG(
+				  "*** ant-index : [ %d ],      counter = (( %d )),     Avg RSSI = (( %d ))\n",
+				  i, fat_tab->ant_rssi_cnt[i],
+				  fat_tab->ant_ave_rssi[i]);
+		}
+
+#if 0
+#if (RTL8192E_SUPPORT == 1)
+		/* @3 [path-B]--------------------------- */
+		for (i = 0; i < (dm->fat_comb_b); i++) {
+			if (fat_tab->antRSSIcnt_pathB[i] == 0)
+				fat_tab->antAveRSSI_pathB[i] = 0;
+			else { /*  @(ant_rssi_cnt[i] != 0) */
+				fat_tab->antAveRSSI_pathB[i] = fat_tab->antSumRSSI_pathB[i] / fat_tab->antRSSIcnt_pathB[i];
+				is_pkt_filter_macth_path_b = true;
+			}
+			if (fat_tab->antAveRSSI_pathB[i] > max_rssi_path_b) {
+				max_rssi_path_b = fat_tab->antAveRSSI_pathB[i];
+				pckcnt_path_b = fat_tab->antRSSIcnt_pathB[i];
+				target_ant_path_b = (u8)i;
+			}
+			if (fat_tab->antAveRSSI_pathB[i] == max_rssi_path_b) {
+				if (fat_tab->antRSSIcnt_pathB > pckcnt_path_b) {
+					max_rssi_path_b = fat_tab->antAveRSSI_pathB[i];
+					target_ant_path_b = (u8)i;
+				}
+			}
+			if (dm->fat_print_rssi == 1) {
+				PHYDM_DBG(dm, DBG_ANT_DIV,
+					  "***{path-B}: Sum RSSI[%d] = (( %d )),      cnt RSSI [%d] = (( %d )),     Avg RSSI[%d] = (( %d ))\n",
+					  i, fat_tab->antSumRSSI_pathB[i], i,
+					  fat_tab->antRSSIcnt_pathB[i], i,
+					  fat_tab->antAveRSSI_pathB[i]);
+			}
+		}
+#endif
+#endif
+
+		/* @1 DECISION STATE */
+
+		/* @2 Select TRX Antenna */
+
+		phydm_fast_training_enable(dm, FAT_OFF);
+
+		/* @3 [path-A]--------------------------- */
+		if (is_pkt_filter_macth_path_a == false) {
+#if 0
+			/* PHYDM_DBG(dm,DBG_ANT_DIV, "{path-A}: None Packet is matched\n"); */
+#endif
+			PHYDM_DBG(dm, DBG_ANT_DIV,
+				  "{path-A}: None Packet is matched\n");
+			odm_ant_div_on_off(dm, ANTDIV_OFF, ANT_PATH_A);
+		} else {
+			PHYDM_DBG(
+				  "target_ant_path_a = (( %d )) , max_rssi_path_a = (( %d ))\n",
+				  target_ant_path_a, max_rssi_path_a);
+
+			/* @3 [ update RX-optional ant ]        Default RX is Omni, Optional RX is the best decision by FAT */
+			if (dm->support_ic_type == ODM_RTL8188E)
+				odm_set_bb_reg(dm, R_0x864, BIT(8) | BIT(7) | BIT(6), target_ant_path_a);
+			else if (dm->support_ic_type == ODM_RTL8192E)
+				odm_set_bb_reg(dm, R_0xb38, BIT(8) | BIT(7) | BIT(6), target_ant_path_a); /* Optional RX [pth-A] */
+
+			/* @3 [ update TX ant ] */
+			odm_update_tx_ant(dm, target_ant_path_a, (fat_tab->train_idx));
+
+			if (target_ant_path_a == 0)
+				odm_ant_div_on_off(dm, ANTDIV_OFF, ANT_PATH_A);
+		}
+#if 0
+#if (RTL8192E_SUPPORT == 1)
+		/* @3 [path-B]--------------------------- */
+		if (is_pkt_filter_macth_path_b == false) {
+			if (dm->fat_print_rssi == 1)
+				PHYDM_DBG(dm, DBG_ANT_DIV,
+					  "***[%d]{path-B}: None Packet is matched\n\n\n",
+					  __LINE__);
+		} else {
+			if (dm->fat_print_rssi == 1) {
+				PHYDM_DBG(dm, DBG_ANT_DIV,
+					  " ***target_ant_path_b = (( %d )) *** max_rssi = (( %d ))***\n\n\n",
+					  target_ant_path_b, max_rssi_path_b);
+			}
+			odm_set_bb_reg(dm, R_0xb38, BIT(21) | BIT20 | BIT19, target_ant_path_b);	/* @Default RX is Omni, Optional RX is the best decision by FAT */
+			odm_set_bb_reg(dm, R_0x80c, BIT(21), 1); /* Reg80c[21]=1'b1		//from TX Info */
+
+			fat_tab->antsel_pathB[fat_tab->train_idx] = target_ant_path_b;
+		}
+#endif
+#endif
+
+		/* @2 Reset counter */
+		for (i = 0; i < (dm->fat_comb_a); i++) {
+			fat_tab->ant_sum_rssi[i] = 0;
+			fat_tab->ant_rssi_cnt[i] = 0;
+		}
+		/*@
+		#if (RTL8192E_SUPPORT == 1)
+		for(i=0; i<=(dm->fat_comb_b); i++)
+		{
+			fat_tab->antSumRSSI_pathB[i] = 0;
+			fat_tab->antRSSIcnt_pathB[i] = 0;
+		}
+		#endif
+		*/
+
+		fat_tab->fat_state = FAT_PREPARE_STATE;
+		return;
+	}
+
+	/* @1 NORMAL STATE */
+	if (fat_tab->fat_state == FAT_PREPARE_STATE) {
+		PHYDM_DBG(dm, DBG_ANT_DIV, "[ Start Prepare state ]\n");
+
+		odm_set_next_mac_addr_target(dm);
+
+		/* @2 Prepare Training */
+		fat_tab->fat_state = FAT_TRAINING_STATE;
+		phydm_fast_training_enable(dm, FAT_ON);
+		odm_ant_div_on_off(dm, ANTDIV_ON, ANT_PATH_A);
+		/* @enable HW AntDiv */
+		PHYDM_DBG(dm, DBG_ANT_DIV, "[Start Training state]\n");
+
+		odm_set_timer(dm, &dm->fast_ant_training_timer, dm->antdiv_intvl); /* @ms */
+	}
+}
+
+void odm_fast_ant_training_callback(
+	void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+
+#if (DM_ODM_SUPPORT_TYPE == ODM_CE)
+	if (*(dm->is_net_closed) == true)
+		return;
+#endif
+
+#if USE_WORKITEM
+	odm_schedule_work_item(&dm->fast_ant_training_workitem);
+#else
+	PHYDM_DBG(dm, DBG_ANT_DIV, "******%s******\n", __func__);
+	odm_fast_ant_training(dm);
+#endif
+}
+
+void odm_fast_ant_training_work_item_callback(
+	void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+
+	PHYDM_DBG(dm, DBG_ANT_DIV, "******%s******\n", __func__);
+	odm_fast_ant_training(dm);
+}
+
+#endif
+
+void odm_ant_div_init(
+	void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
+	struct sw_antenna_switch *dm_swat_table = &dm->dm_swat_table;
+
+	if (!(dm->support_ability & ODM_BB_ANT_DIV)) {
+		PHYDM_DBG(dm, DBG_ANT_DIV,
+			  "[Return!!!]   Not Support Antenna Diversity Function\n");
+		return;
+	}
+/* @--- */
+#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
+	if (fat_tab->ant_div_2g_5g == ODM_ANTDIV_2G) {
+		PHYDM_DBG(dm, DBG_ANT_DIV,
+			  "[2G AntDiv Init]: Only Support 2G Antenna Diversity Function\n");
+		if (!(dm->support_ic_type & ODM_ANTDIV_2G_SUPPORT_IC))
+			return;
+	} else if (fat_tab->ant_div_2g_5g == ODM_ANTDIV_5G) {
+		PHYDM_DBG(dm, DBG_ANT_DIV,
+			  "[5G AntDiv Init]: Only Support 5G Antenna Diversity Function\n");
+		if (!(dm->support_ic_type & ODM_ANTDIV_5G_SUPPORT_IC))
+			return;
+	} else if (fat_tab->ant_div_2g_5g == (ODM_ANTDIV_2G | ODM_ANTDIV_5G))
+		PHYDM_DBG(dm, DBG_ANT_DIV,
+			  "[2G & 5G AntDiv Init]:Support Both 2G & 5G Antenna Diversity Function\n");
+
+#endif
+	/* @--- */
+
+	/* @2 [--General---] */
+	dm->antdiv_period = 0;
+
+	fat_tab->is_become_linked = false;
+	fat_tab->ant_div_on_off = 0xff;
+
+/* @3       -   AP   - */
+#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
+
+#if (BEAMFORMING_SUPPORT == 1)
+#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
+	odm_bdc_init(dm);
+#endif
+#endif
+
+/* @3     -   WIN   - */
+#elif (DM_ODM_SUPPORT_TYPE == ODM_WIN)
+	dm_swat_table->ant_5g = MAIN_ANT;
+	dm_swat_table->ant_2g = MAIN_ANT;
+#endif
+
+	/* @2 [---Set MAIN_ANT as default antenna if Auto-ant enable---] */
+	if (fat_tab->div_path_type == ANT_PATH_A)
+		odm_ant_div_on_off(dm, ANTDIV_OFF, ANT_PATH_A);
+	else if (fat_tab->div_path_type == ANT_PATH_B)
+		odm_ant_div_on_off(dm, ANTDIV_OFF, ANT_PATH_B);
+	else if (fat_tab->div_path_type == ANT_PATH_AB)
+		odm_ant_div_on_off(dm, ANTDIV_OFF, ANT_PATH_AB);
+
+	dm->ant_type = ODM_AUTO_ANT;
+
+	fat_tab->rx_idle_ant = 0xff; /*to make RX-idle-antenna will be updated absolutly*/
+	odm_update_rx_idle_ant(dm, MAIN_ANT);
+	phydm_keep_rx_ack_ant_by_tx_ant_time(dm, 0); /* Timming issue: keep Rx ant after tx for ACK ( 5 x 3.2 mu = 16mu sec)*/
+
+	/* @2 [---Set TX Antenna---] */
+	if (fat_tab->p_force_tx_ant_by_desc == NULL) {
+		fat_tab->force_tx_ant_by_desc = 0;
+		fat_tab->p_force_tx_ant_by_desc = &fat_tab->force_tx_ant_by_desc;
+	}
+	PHYDM_DBG(dm, DBG_ANT_DIV, "p_force_tx_ant_by_desc = %d\n",
+		  *fat_tab->p_force_tx_ant_by_desc);
+
+	if (*fat_tab->p_force_tx_ant_by_desc == true)
+		odm_tx_by_tx_desc_or_reg(dm, TX_BY_DESC);
+	else
+		odm_tx_by_tx_desc_or_reg(dm, TX_BY_REG);
+
+	/* @2 [--88E---] */
+	if (dm->support_ic_type == ODM_RTL8188E) {
+#if (RTL8188E_SUPPORT == 1)
+		/* @dm->ant_div_type = CGCS_RX_HW_ANTDIV; */
+		/* @dm->ant_div_type = CG_TRX_HW_ANTDIV; */
+		/* @dm->ant_div_type = CG_TRX_SMART_ANTDIV; */
+
+		if (dm->ant_div_type != CGCS_RX_HW_ANTDIV && dm->ant_div_type != CG_TRX_HW_ANTDIV && dm->ant_div_type != CG_TRX_SMART_ANTDIV) {
+			PHYDM_DBG(dm, DBG_ANT_DIV,
+				  "[Return!!!]  88E Not Supprrt This AntDiv type\n");
+			dm->support_ability &= ~(ODM_BB_ANT_DIV);
+			return;
+		}
+
+		if (dm->ant_div_type == CGCS_RX_HW_ANTDIV)
+			odm_rx_hw_ant_div_init_88e(dm);
+		else if (dm->ant_div_type == CG_TRX_HW_ANTDIV)
+			odm_trx_hw_ant_div_init_88e(dm);
+#if (defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY)) || (defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY))
+		else if (dm->ant_div_type == CG_TRX_SMART_ANTDIV)
+			odm_smart_hw_ant_div_init_88e(dm);
+#endif
+#endif
+	}
+
+/* @2 [--92E---] */
+#if (RTL8192E_SUPPORT == 1)
+	else if (dm->support_ic_type == ODM_RTL8192E) {
+		/* @dm->ant_div_type = CGCS_RX_HW_ANTDIV; */
+		/* @dm->ant_div_type = CG_TRX_HW_ANTDIV; */
+		/* @dm->ant_div_type = CG_TRX_SMART_ANTDIV; */
+
+		if (dm->ant_div_type != CGCS_RX_HW_ANTDIV && dm->ant_div_type != CG_TRX_HW_ANTDIV && dm->ant_div_type != CG_TRX_SMART_ANTDIV) {
+			PHYDM_DBG(dm, DBG_ANT_DIV,
+				  "[Return!!!]  8192E Not Supprrt This AntDiv type\n");
+			dm->support_ability &= ~(ODM_BB_ANT_DIV);
+			return;
+		}
+
+		if (dm->ant_div_type == CGCS_RX_HW_ANTDIV)
+			odm_rx_hw_ant_div_init_92e(dm);
+		else if (dm->ant_div_type == CG_TRX_HW_ANTDIV)
+			odm_trx_hw_ant_div_init_92e(dm);
+#if (defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY)) || (defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY))
+		else if (dm->ant_div_type == CG_TRX_SMART_ANTDIV)
+			odm_smart_hw_ant_div_init_92e(dm);
+#endif
+	}
+#endif
+
+	/* @2 [--92F---] */
+#if (RTL8192F_SUPPORT == 1)
+	else if (dm->support_ic_type == ODM_RTL8192F) {
+	/* @dm->ant_div_type = CGCS_RX_HW_ANTDIV; */
+	/* @dm->ant_div_type = CG_TRX_HW_ANTDIV; */
+	/* @dm->ant_div_type = CG_TRX_SMART_ANTDIV; */
+
+	if (dm->ant_div_type != CGCS_RX_HW_ANTDIV) {
+		if (dm->ant_div_type != CG_TRX_HW_ANTDIV) {
+			PHYDM_DBG(dm, DBG_ANT_DIV,
+				  "[Return!!!]  8192F Not Supprrt This AntDiv type\n");
+			dm->support_ability &= ~(ODM_BB_ANT_DIV);
+			return;
+		}
+	}
+	if (dm->ant_div_type == CGCS_RX_HW_ANTDIV)
+		odm_rx_hw_ant_div_init_92f(dm);
+	else if (dm->ant_div_type == CG_TRX_HW_ANTDIV)
+	odm_trx_hw_ant_div_init_92f(dm);
+	}
+#endif
+
+#if (RTL8197F_SUPPORT == 1)
+	else if (dm->support_ic_type == ODM_RTL8197F) {
+		dm->ant_div_type = CGCS_RX_HW_ANTDIV;
+
+		if (dm->ant_div_type != CGCS_RX_HW_ANTDIV) {
+			PHYDM_DBG(dm, DBG_ANT_DIV,
+				  "[Return!!!]  8197F Not Supprrt This AntDiv type\n");
+			dm->support_ability &= ~(ODM_BB_ANT_DIV);
+			return;
+		}
+		phydm_rx_hw_ant_div_init_97f(dm);
+	}
+#endif
+/* @2 [--8723B---] */
+#if (RTL8723B_SUPPORT == 1)
+	else if (dm->support_ic_type == ODM_RTL8723B) {
+		dm->ant_div_type = S0S1_SW_ANTDIV;
+		/* @dm->ant_div_type = CG_TRX_HW_ANTDIV; */
+
+		if (dm->ant_div_type != S0S1_SW_ANTDIV && dm->ant_div_type != CG_TRX_HW_ANTDIV) {
+			PHYDM_DBG(dm, DBG_ANT_DIV,
+				  "[Return!!!] 8723B  Not Supprrt This AntDiv type\n");
+			dm->support_ability &= ~(ODM_BB_ANT_DIV);
+			return;
+		}
+
+		if (dm->ant_div_type == S0S1_SW_ANTDIV)
+			odm_s0s1_sw_ant_div_init_8723b(dm);
+		else if (dm->ant_div_type == CG_TRX_HW_ANTDIV)
+			odm_trx_hw_ant_div_init_8723b(dm);
+	}
+#endif
+/*@2 [--8723D---]*/
+#if (RTL8723D_SUPPORT == 1)
+	else if (dm->support_ic_type == ODM_RTL8723D) {
+		if (fat_tab->p_default_s0_s1 == NULL) {
+			fat_tab->default_s0_s1 = 1;
+			fat_tab->p_default_s0_s1 = &fat_tab->default_s0_s1;
+		}
+		PHYDM_DBG(dm, DBG_ANT_DIV, "default_s0_s1 = %d\n",
+			  *fat_tab->p_default_s0_s1);
+
+		if (*fat_tab->p_default_s0_s1 == true)
+			odm_update_rx_idle_ant(dm, MAIN_ANT);
+		else
+			odm_update_rx_idle_ant(dm, AUX_ANT);
+
+		if (dm->ant_div_type == S0S1_TRX_HW_ANTDIV)
+			odm_trx_hw_ant_div_init_8723d(dm);
+		else if (dm->ant_div_type == S0S1_SW_ANTDIV)
+			odm_s0s1_sw_ant_div_init_8723d(dm);
+		else {
+			PHYDM_DBG(dm, DBG_ANT_DIV,
+				  "[Return!!!] 8723D  Not Supprrt This AntDiv type\n");
+			dm->support_ability &= ~(ODM_BB_ANT_DIV);
+			return;
+		}
+	}
+#endif
+/* @2 [--8811A 8821A---] */
+#if (RTL8821A_SUPPORT == 1)
+	else if (dm->support_ic_type == ODM_RTL8821) {
+#ifdef CONFIG_HL_SMART_ANTENNA_TYPE1
+		dm->ant_div_type = HL_SW_SMART_ANT_TYPE1;
+
+		if (dm->ant_div_type == HL_SW_SMART_ANT_TYPE1) {
+			odm_trx_hw_ant_div_init_8821a(dm);
+			phydm_hl_smart_ant_type1_init_8821a(dm);
+		} else
+#endif
+		{
+#ifdef ODM_CONFIG_BT_COEXIST
+			dm->ant_div_type = S0S1_SW_ANTDIV;
+#else
+			dm->ant_div_type = CG_TRX_HW_ANTDIV;
+#endif
+
+			if (dm->ant_div_type != CG_TRX_HW_ANTDIV && dm->ant_div_type != S0S1_SW_ANTDIV) {
+				PHYDM_DBG(dm, DBG_ANT_DIV,
+					  "[Return!!!] 8821A & 8811A  Not Supprrt This AntDiv type\n");
+				dm->support_ability &= ~(ODM_BB_ANT_DIV);
+				return;
+			}
+			if (dm->ant_div_type == CG_TRX_HW_ANTDIV)
+				odm_trx_hw_ant_div_init_8821a(dm);
+			else if (dm->ant_div_type == S0S1_SW_ANTDIV)
+				odm_s0s1_sw_ant_div_init_8821a(dm);
+		}
+	}
+#endif
+
+/* @2 [--8821C---] */
+#if (RTL8821C_SUPPORT == 1)
+	else if (dm->support_ic_type == ODM_RTL8821C) {
+		dm->ant_div_type = S0S1_SW_ANTDIV;
+		if (dm->ant_div_type != S0S1_SW_ANTDIV) {
+			PHYDM_DBG(dm, DBG_ANT_DIV,
+				  "[Return!!!] 8821C  Not Supprrt This AntDiv type\n");
+			dm->support_ability &= ~(ODM_BB_ANT_DIV);
+			return;
+		}
+		phydm_s0s1_sw_ant_div_init_8821c(dm);
+		odm_trx_hw_ant_div_init_8821c(dm);
+	}
+#endif
+
+/* @2 [--8881A---] */
+#if (RTL8881A_SUPPORT == 1)
+	else if (dm->support_ic_type == ODM_RTL8881A) {
+		/* @dm->ant_div_type = CGCS_RX_HW_ANTDIV; */
+		/* @dm->ant_div_type = CG_TRX_HW_ANTDIV; */
+
+		if (dm->ant_div_type == CG_TRX_HW_ANTDIV) {
+			odm_trx_hw_ant_div_init_8881a(dm);
+		} else {
+			PHYDM_DBG(dm, DBG_ANT_DIV,
+				  "[Return!!!] 8881A  Not Supprrt This AntDiv type\n");
+			dm->support_ability &= ~(ODM_BB_ANT_DIV);
+			return;
+		}
+
+		odm_trx_hw_ant_div_init_8881a(dm);
+	}
+#endif
+
+/* @2 [--8812---] */
+#if (RTL8812A_SUPPORT == 1)
+	else if (dm->support_ic_type == ODM_RTL8812) {
+		/* @dm->ant_div_type = CG_TRX_HW_ANTDIV; */
+
+		if (dm->ant_div_type != CG_TRX_HW_ANTDIV) {
+			PHYDM_DBG(dm, DBG_ANT_DIV,
+				  "[Return!!!] 8812A  Not Supprrt This AntDiv type\n");
+			dm->support_ability &= ~(ODM_BB_ANT_DIV);
+			return;
+		}
+		odm_trx_hw_ant_div_init_8812a(dm);
+	}
+#endif
+
+/*@[--8188F---]*/
+#if (RTL8188F_SUPPORT == 1)
+	else if (dm->support_ic_type == ODM_RTL8188F) {
+		dm->ant_div_type = S0S1_SW_ANTDIV;
+		odm_s0s1_sw_ant_div_init_8188f(dm);
+	}
+#endif
+
+/*@[--8822B---]*/
+#if (RTL8822B_SUPPORT == 1)
+	else if (dm->support_ic_type == ODM_RTL8822B) {
+		dm->ant_div_type = CG_TRX_HW_ANTDIV;
+
+		if (dm->ant_div_type != CG_TRX_HW_ANTDIV) {
+			PHYDM_DBG(dm, DBG_ANT_DIV,
+				  "[Return!!!]  8822B Not Supprrt This AntDiv type\n");
+			dm->support_ability &= ~(ODM_BB_ANT_DIV);
+			return;
+		}
+		phydm_trx_hw_ant_div_init_22b(dm);
+#ifdef CONFIG_HL_SMART_ANTENNA_TYPE2
+		dm->ant_div_type = HL_SW_SMART_ANT_TYPE2;
+
+		if (dm->ant_div_type == HL_SW_SMART_ANT_TYPE2)
+			phydm_hl_smart_ant_type2_init_8822b(dm);
+#endif
+	}
+#endif
+
+	/*@
+	PHYDM_DBG(dm, DBG_ANT_DIV, "*** support_ic_type=[%lu]\n",dm->support_ic_type);
+	PHYDM_DBG(dm, DBG_ANT_DIV, "*** AntDiv support_ability=[%lu]\n",(dm->support_ability & ODM_BB_ANT_DIV)>>6);
+	PHYDM_DBG(dm, DBG_ANT_DIV, "*** AntDiv type=[%d]\n",dm->ant_div_type);
+	*/
+}
+
+void odm_ant_div(
+	void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	void *adapter = dm->adapter;
+	struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
+#if (defined(CONFIG_HL_SMART_ANTENNA))
+	struct smt_ant_honbo *sat_tab = &dm->dm_sat_table;
+#endif
+
+#ifdef ODM_EVM_ENHANCE_ANTDIV
+
+	if (dm->is_linked) {
+		PHYDM_DBG(dm, DBG_ANT_DIV,
+			  "tp_active_occur=((%d)), evm_method_enable=((%d))\n",
+			  dm->tp_active_occur, fat_tab->evm_method_enable);
+
+		if (dm->tp_active_occur == 1 && fat_tab->evm_method_enable == 1) {
+			fat_tab->idx_ant_div_counter_5g = dm->antdiv_period;
+			fat_tab->idx_ant_div_counter_2g = dm->antdiv_period;
+		}
+	}
+#endif
+
+	if (*dm->band_type == ODM_BAND_5G) {
+		if (fat_tab->idx_ant_div_counter_5g < dm->antdiv_period) {
+			fat_tab->idx_ant_div_counter_5g++;
+			return;
+		} else
+			fat_tab->idx_ant_div_counter_5g = 0;
+	} else if (*dm->band_type == ODM_BAND_2_4G) {
+		if (fat_tab->idx_ant_div_counter_2g < dm->antdiv_period) {
+			fat_tab->idx_ant_div_counter_2g++;
+			return;
+		} else
+			fat_tab->idx_ant_div_counter_2g = 0;
+	}
+
+/* @---------- */
+
+/* @---------- */
+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN || DM_ODM_SUPPORT_TYPE == ODM_CE)
+
+	if (fat_tab->enable_ctrl_frame_antdiv) {
+		if (dm->data_frame_num <= 10 && dm->is_linked)
+			fat_tab->use_ctrl_frame_antdiv = 1;
+		else
+			fat_tab->use_ctrl_frame_antdiv = 0;
+
+		PHYDM_DBG(dm, DBG_ANT_DIV,
+			  "use_ctrl_frame_antdiv = (( %d )), data_frame_num = (( %d ))\n",
+			  fat_tab->use_ctrl_frame_antdiv, dm->data_frame_num);
+		dm->data_frame_num = 0;
+	}
+
+	{
+#if (BEAMFORMING_SUPPORT == 1)
+
+		enum beamforming_cap beamform_cap = phydm_get_beamform_cap(dm);
+		PHYDM_DBG(dm, DBG_ANT_DIV, "is_bt_continuous_turn = ((%d))\n",
+			  dm->is_bt_continuous_turn);
+		PHYDM_DBG(dm, DBG_ANT_DIV,
+			  "[ AntDiv Beam Cap ]   cap= ((%d))\n", beamform_cap);
+		if (!dm->is_bt_continuous_turn) {
+			if ((beamform_cap & BEAMFORMEE_CAP) && (!(*fat_tab->is_no_csi_feedback))) { /* @BFmee On  &&   Div On->Div Off */
+				PHYDM_DBG(dm, DBG_ANT_DIV,
+					  "[ AntDiv : OFF ]   BFmee ==1; cap= ((%d))\n",
+					  beamform_cap);
+				PHYDM_DBG(dm, DBG_ANT_DIV,
+					  "[ AntDiv BF]   is_no_csi_feedback= ((%d))\n",
+					  *(fat_tab->is_no_csi_feedback));
+				if (fat_tab->fix_ant_bfee == 0) {
+					odm_ant_div_on_off(dm, ANTDIV_OFF,
+							   ANT_PATH_A);
+					fat_tab->fix_ant_bfee = 1;
+				}
+				return;
+			} else { /* @BFmee Off   &&   Div Off->Div On */
+				if (fat_tab->fix_ant_bfee == 1 && dm->is_linked) {
+					PHYDM_DBG(dm, DBG_ANT_DIV, "[ AntDiv : ON ]   BFmee ==0; cap=((%d))\n", beamform_cap);
+					PHYDM_DBG(dm, DBG_ANT_DIV, "[ AntDiv BF]   is_no_csi_feedback= ((%d))\n", *(fat_tab->is_no_csi_feedback));
+					if (dm->ant_div_type != S0S1_SW_ANTDIV)
+						odm_ant_div_on_off(dm, ANTDIV_ON
+								   , ANT_PATH_A)
+								   ;
+					fat_tab->fix_ant_bfee = 0;
+				}
+			}
+		} else {
+			if (fat_tab->div_path_type == ANT_PATH_A)
+				odm_ant_div_on_off(dm, ANTDIV_ON, ANT_PATH_A);
+			else if (fat_tab->div_path_type == ANT_PATH_B)
+				odm_ant_div_on_off(dm, ANTDIV_ON, ANT_PATH_B);
+			else if (fat_tab->div_path_type == ANT_PATH_AB)
+				odm_ant_div_on_off(dm, ANTDIV_ON, ANT_PATH_AB);
+		}
+#endif
+	}
+#elif (DM_ODM_SUPPORT_TYPE == ODM_AP)
+	/* @----------just for fool proof */
+
+	if (dm->antdiv_rssi)
+		dm->debug_components |= DBG_ANT_DIV;
+	else
+		dm->debug_components &= ~DBG_ANT_DIV;
+
+	if (fat_tab->ant_div_2g_5g == ODM_ANTDIV_2G) {
+#if 0
+		/* PHYDM_DBG(dm, DBG_ANT_DIV,"[ 2G AntDiv Running ]\n"); */
+#endif
+		if (!(dm->support_ic_type & ODM_ANTDIV_2G_SUPPORT_IC))
+			return;
+	} else if (fat_tab->ant_div_2g_5g == ODM_ANTDIV_5G) {
+#if 0
+		/* PHYDM_DBG(dm, DBG_ANT_DIV,"[ 5G AntDiv Running ]\n"); */
+#endif
+		if (!(dm->support_ic_type & ODM_ANTDIV_5G_SUPPORT_IC))
+			return;
+	}
+#if 0
+/* @else 	if(fat_tab->ant_div_2g_5g == (ODM_ANTDIV_2G|ODM_ANTDIV_5G)) */
+/* @{ */
+/* PHYDM_DBG(dm, DBG_ANT_DIV,"[ 2G & 5G AntDiv Running ]\n"); */
+/* @} */
+#endif
+#endif
+
+	/* @---------- */
+
+	if (dm->antdiv_select == 1)
+		dm->ant_type = ODM_FIX_MAIN_ANT;
+	else if (dm->antdiv_select == 2)
+		dm->ant_type = ODM_FIX_AUX_ANT;
+	else { /* @if (dm->antdiv_select==0) */
+		dm->ant_type = ODM_AUTO_ANT;
+
+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
+		/*Stop Antenna diversity for CMW500 testing case*/
+		if (dm->consecutive_idlel_time >= 10) {
+			dm->ant_type = ODM_FIX_MAIN_ANT;
+			PHYDM_DBG(dm, DBG_ANT_DIV,
+				  "[AntDiv: OFF] No TP case, consecutive_idlel_time=((%d))\n",
+				  dm->consecutive_idlel_time);
+		}
+#endif
+	}
+
+#if 0
+	/* PHYDM_DBG(dm, DBG_ANT_DIV,"ant_type= (( %d )) , pre_ant_type= (( %d ))\n",dm->ant_type,dm->pre_ant_type); */
+#endif
+
+	if (dm->ant_type != ODM_AUTO_ANT) {
+		PHYDM_DBG(dm, DBG_ANT_DIV, "Fix Antenna at (( %s ))\n",
+			  (dm->ant_type == ODM_FIX_MAIN_ANT) ? "MAIN" : "AUX");
+
+		if (dm->ant_type != dm->pre_ant_type) {
+			odm_ant_div_on_off(dm, ANTDIV_OFF, ANT_PATH_A);
+			odm_tx_by_tx_desc_or_reg(dm, TX_BY_REG);
+
+			if (dm->ant_type == ODM_FIX_MAIN_ANT)
+				odm_update_rx_idle_ant(dm, MAIN_ANT);
+			else if (dm->ant_type == ODM_FIX_AUX_ANT)
+				odm_update_rx_idle_ant(dm, AUX_ANT);
+		}
+		dm->pre_ant_type = dm->ant_type;
+		return;
+	} else {
+		if (dm->ant_type != dm->pre_ant_type) {
+			odm_ant_div_on_off(dm, ANTDIV_ON, ANT_PATH_A);
+			odm_tx_by_tx_desc_or_reg(dm, TX_BY_DESC);
+		}
+		dm->pre_ant_type = dm->ant_type;
+	}
+#if (defined(CONFIG_2T4R_ANTENNA))
+	if (dm->ant_type2 != ODM_AUTO_ANT) {
+		PHYDM_DBG(dm, DBG_ANT_DIV, "PathB Fix Ant at (( %s ))\n",
+			  (dm->ant_type2 == ODM_FIX_MAIN_ANT) ? "MAIN" : "AUX");
+
+		if (dm->ant_type2 != dm->pre_ant_type2) {
+			odm_ant_div_on_off(dm, ANTDIV_OFF, ANT_PATH_B);
+			odm_tx_by_tx_desc_or_reg(dm, TX_BY_REG);
+
+			if (dm->ant_type2 == ODM_FIX_MAIN_ANT)
+				phydm_update_rx_idle_ant_pathb(dm, MAIN_ANT);
+			else if (dm->ant_type2 == ODM_FIX_AUX_ANT)
+				phydm_update_rx_idle_ant_pathb(dm, AUX_ANT);
+		}
+		dm->pre_ant_type2 = dm->ant_type2;
+		return;
+	}
+	if (dm->ant_type2 != dm->pre_ant_type2) {
+		odm_ant_div_on_off(dm, ANTDIV_ON, ANT_PATH_B);
+		odm_tx_by_tx_desc_or_reg(dm, TX_BY_DESC);
+	}
+	dm->pre_ant_type2 = dm->ant_type2;
+
+#endif
+
+	/* @3 ----------------------------------------------------------------------------------------------------------- */
+	/* @2 [--88E---] */
+	if (dm->support_ic_type == ODM_RTL8188E) {
+#if (RTL8188E_SUPPORT == 1)
+		if (dm->ant_div_type == CG_TRX_HW_ANTDIV || dm->ant_div_type == CGCS_RX_HW_ANTDIV)
+			odm_hw_ant_div(dm);
+
+#if (defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY)) || (defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY))
+		else if (dm->ant_div_type == CG_TRX_SMART_ANTDIV)
+			odm_fast_ant_training(dm);
+#endif
+
+#endif
+	}
+/* @2 [--92E---] */
+#if (RTL8192E_SUPPORT == 1)
+	else if (dm->support_ic_type == ODM_RTL8192E) {
+		if (dm->ant_div_type == CGCS_RX_HW_ANTDIV || dm->ant_div_type == CG_TRX_HW_ANTDIV)
+			odm_hw_ant_div(dm);
+
+#if (defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY)) || (defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY))
+		else if (dm->ant_div_type == CG_TRX_SMART_ANTDIV)
+			odm_fast_ant_training(dm);
+#endif
+	}
+#endif
+/* @2 [--97F---] */
+#if (RTL8197F_SUPPORT == 1)
+	else if (dm->support_ic_type == ODM_RTL8197F) {
+		if (dm->ant_div_type == CGCS_RX_HW_ANTDIV)
+			odm_hw_ant_div(dm);
+	}
+#endif
+
+#if (RTL8723B_SUPPORT == 1)
+	/* @2 [--8723B---] */
+	else if (dm->support_ic_type == ODM_RTL8723B) {
+		if (phydm_is_bt_enable_8723b(dm)) {
+			PHYDM_DBG(dm, DBG_ANT_DIV, "[BT is enable!!!]\n");
+			if (fat_tab->is_become_linked == true) {
+				PHYDM_DBG(dm, DBG_ANT_DIV,
+					  "Set REG 948[9:6]=0x0\n");
+				if (dm->support_ic_type == ODM_RTL8723B)
+					odm_set_bb_reg(dm, R_0x948, BIT(9) | BIT(8) | BIT(7) | BIT(6), 0x0);
+
+				fat_tab->is_become_linked = false;
+			}
+		} else {
+			if (dm->ant_div_type == S0S1_SW_ANTDIV) {
+#ifdef CONFIG_S0S1_SW_ANTENNA_DIVERSITY
+				odm_s0s1_sw_ant_div(dm, SWAW_STEP_PEEK);
+#endif
+			} else if (dm->ant_div_type == CG_TRX_HW_ANTDIV)
+				odm_hw_ant_div(dm);
+		}
+	}
+#endif
+/*@8723D*/
+#if (RTL8723D_SUPPORT == 1)
+	else if (dm->support_ic_type == ODM_RTL8723D) {
+		if (dm->ant_div_type == S0S1_SW_ANTDIV) {
+#ifdef CONFIG_S0S1_SW_ANTENNA_DIVERSITY
+			if (dm->antdiv_counter ==
+				CONFIG_ANTENNA_DIVERSITY_PERIOD) {
+				odm_s0s1_sw_ant_div(dm, SWAW_STEP_PEEK);
+				dm->antdiv_counter--;
+			} else {
+				dm->antdiv_counter--;
+			}
+			if (dm->antdiv_counter == 0)
+				dm->antdiv_counter = CONFIG_ANTENNA_DIVERSITY_PERIOD;
+#endif
+		} else if (dm->ant_div_type == CG_TRX_HW_ANTDIV) {
+			odm_hw_ant_div(dm);
+		}
+	}
+#endif
+
+/* @2 [--8821A---] */
+#if (RTL8821A_SUPPORT == 1)
+	else if (dm->support_ic_type == ODM_RTL8821) {
+#ifdef CONFIG_HL_SMART_ANTENNA_TYPE1
+		if (dm->ant_div_type == HL_SW_SMART_ANT_TYPE1) {
+			if (sat_tab->fix_beam_pattern_en != 0) {
+				PHYDM_DBG(dm, DBG_ANT_DIV,
+					  " [ SmartAnt ] Fix SmartAnt Pattern = 0x%x\n",
+					  sat_tab->fix_beam_pattern_codeword);
+				/*return;*/
+			} else {
+#if 0
+				/*PHYDM_DBG(dm, DBG_ANT_DIV, "[ SmartAnt ] ant_div_type = HL_SW_SMART_ANT_TYPE1\n");*/
+#endif
+				odm_fast_ant_training_hl_smart_antenna_type1(dm);
+			}
+
+		} else
+#endif
+		{
+#ifdef ODM_CONFIG_BT_COEXIST
+			if (!dm->bt_info_table.is_bt_enabled) { /*@BT disabled*/
+				if (dm->ant_div_type == S0S1_SW_ANTDIV) {
+					dm->ant_div_type = CG_TRX_HW_ANTDIV;
+					PHYDM_DBG(dm, DBG_ANT_DIV, " [S0S1_SW_ANTDIV]  ->  [CG_TRX_HW_ANTDIV]\n");
+#if 0
+					/*odm_set_bb_reg(dm, R_0x8d4, BIT24, 1); */
+#endif
+					if (fat_tab->is_become_linked == true)
+						odm_ant_div_on_off(dm, ANTDIV_ON, ANT_PATH_A);
+				}
+
+			} else { /*@BT enabled*/
+
+				if (dm->ant_div_type == CG_TRX_HW_ANTDIV) {
+					dm->ant_div_type = S0S1_SW_ANTDIV;
+					PHYDM_DBG(dm, DBG_ANT_DIV, " [CG_TRX_HW_ANTDIV]  ->  [S0S1_SW_ANTDIV]\n");
+#if 0
+					/*odm_set_bb_reg(dm, R_0x8d4, BIT24, 0);*/
+#endif
+					odm_ant_div_on_off(dm, ANTDIV_OFF, ANT_PATH_A);
+				}
+			}
+#endif
+
+			if (dm->ant_div_type == S0S1_SW_ANTDIV) {
+#ifdef CONFIG_S0S1_SW_ANTENNA_DIVERSITY
+				odm_s0s1_sw_ant_div(dm, SWAW_STEP_PEEK);
+#endif
+			} else if (dm->ant_div_type == CG_TRX_HW_ANTDIV)
+				odm_hw_ant_div(dm);
+		}
+	}
+#endif
+
+/* @2 [--8821C---] */
+#if (RTL8821C_SUPPORT == 1)
+	else if (dm->support_ic_type == ODM_RTL8821C) {
+		if (!dm->is_bt_continuous_turn) {
+			dm->ant_div_type = S0S1_SW_ANTDIV;
+			PHYDM_DBG(dm, DBG_ANT_DIV,
+				  "is_bt_continuous_turn = ((%d))   ==> SW AntDiv\n",
+				  dm->is_bt_continuous_turn);
+
+		} else {
+			dm->ant_div_type = CG_TRX_HW_ANTDIV;
+			PHYDM_DBG(dm, DBG_ANT_DIV,
+				  "is_bt_continuous_turn = ((%d))   ==> HW AntDiv\n",
+				  dm->is_bt_continuous_turn);
+			odm_ant_div_on_off(dm, ANTDIV_ON, ANT_PATH_A);
+		}
+
+		if (fat_tab->force_antdiv_type)
+			dm->ant_div_type = fat_tab->antdiv_type_dbg;
+
+		if (dm->ant_div_type == S0S1_SW_ANTDIV) {
+#ifdef CONFIG_S0S1_SW_ANTENNA_DIVERSITY
+			odm_s0s1_sw_ant_div(dm, SWAW_STEP_PEEK);
+#endif
+		} else if (dm->ant_div_type == CG_TRX_HW_ANTDIV) {
+			odm_ant_div_on_off(dm, ANTDIV_ON, ANT_PATH_A);
+			odm_hw_ant_div(dm);
+		}
+	}
+#endif
+
+/* @2 [--8881A---] */
+#if (RTL8881A_SUPPORT == 1)
+	else if (dm->support_ic_type == ODM_RTL8881A)
+		odm_hw_ant_div(dm);
+#endif
+
+/* @2 [--8812A---] */
+#if (RTL8812A_SUPPORT == 1)
+	else if (dm->support_ic_type == ODM_RTL8812)
+		odm_hw_ant_div(dm);
+#endif
+
+#if (RTL8188F_SUPPORT == 1)
+	/* @[--8188F---]*/
+	else if (dm->support_ic_type == ODM_RTL8188F) {
+#ifdef CONFIG_S0S1_SW_ANTENNA_DIVERSITY
+		odm_s0s1_sw_ant_div(dm, SWAW_STEP_PEEK);
+#endif
+	}
+#endif
+
+/* @[--8822B---]*/
+#if (RTL8822B_SUPPORT == 1)
+	else if (dm->support_ic_type == ODM_RTL8822B) {
+		if (dm->ant_div_type == CG_TRX_HW_ANTDIV)
+			odm_hw_ant_div(dm);
+#ifdef CONFIG_HL_SMART_ANTENNA_TYPE2
+		if (dm->ant_div_type == HL_SW_SMART_ANT_TYPE2) {
+			if (sat_tab->fix_beam_pattern_en != 0)
+				PHYDM_DBG(dm, DBG_ANT_DIV,
+					  " [ SmartAnt ] Fix SmartAnt Pattern = 0x%x\n",
+					  sat_tab->fix_beam_pattern_codeword);
+			else
+				phydm_fast_ant_training_hl_smart_antenna_type2(dm);
+		}
+#endif
+	}
+#endif
+}
+
+void odm_antsel_statistics(
+	void *dm_void,
+	void *phy_info_void,
+	u8 antsel_tr_mux,
+	u32 mac_id,
+	u32 utility,
+	u8 method,
+	u8 is_cck_rate
+
+	)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
+	struct phydm_phyinfo_struct *phy_info = (struct phydm_phyinfo_struct *)phy_info_void;
+
+	if (method == RSSI_METHOD) {
+		if (is_cck_rate) {
+			if (antsel_tr_mux == ANT1_2G) {
+				if (fat_tab->main_ant_sum_cck[mac_id] > 65435) /*to prevent u16 overflow, max(RSSI)=100, 65435+100 = 65535 (u16)*/
+					return;
+
+				fat_tab->main_ant_sum_cck[mac_id] += (u16)utility;
+				fat_tab->main_ant_cnt_cck[mac_id]++;
+			} else {
+				if (fat_tab->aux_ant_sum_cck[mac_id] > 65435)
+					return;
+
+				fat_tab->aux_ant_sum_cck[mac_id] += (u16)utility;
+				fat_tab->aux_ant_cnt_cck[mac_id]++;
+			}
+
+		} else { /*ofdm rate*/
+
+			if (antsel_tr_mux == ANT1_2G) {
+				if (fat_tab->main_ant_sum[mac_id] > 65435)
+					return;
+
+				fat_tab->main_ant_sum[mac_id] += (u16)utility;
+				fat_tab->main_ant_cnt[mac_id]++;
+			} else {
+				if (fat_tab->aux_ant_sum[mac_id] > 65435)
+					return;
+
+				fat_tab->aux_ant_sum[mac_id] += (u16)utility;
+				fat_tab->aux_ant_cnt[mac_id]++;
+			}
+		}
+	}
+#ifdef ODM_EVM_ENHANCE_ANTDIV
+	else if (method == EVM_METHOD) {
+		if (dm->rate_ss == 1) {
+			if (antsel_tr_mux == ANT1_2G) {
+				fat_tab->main_ant_evm_sum[mac_id] += ((phy_info->rx_mimo_evm_dbm[0]) << 5);
+				fat_tab->main_ant_evm_cnt[mac_id]++;
+			} else {
+				fat_tab->aux_ant_evm_sum[mac_id] += ((phy_info->rx_mimo_evm_dbm[0]) << 5);
+				fat_tab->aux_ant_evm_cnt[mac_id]++;
+			}
+
+		} else { /*@>= 2SS*/
+
+			if (antsel_tr_mux == ANT1_2G) {
+				fat_tab->main_ant_evm_2ss_sum[mac_id][0] += (phy_info->rx_mimo_evm_dbm[0] << 5);
+				fat_tab->main_ant_evm_2ss_sum[mac_id][1] += (phy_info->rx_mimo_evm_dbm[1] << 5);
+				fat_tab->main_ant_evm_2ss_cnt[mac_id]++;
+
+			} else {
+				fat_tab->aux_ant_evm_2ss_sum[mac_id][0] += (phy_info->rx_mimo_evm_dbm[0] << 5);
+				fat_tab->aux_ant_evm_2ss_sum[mac_id][1] += (phy_info->rx_mimo_evm_dbm[1] << 5);
+				fat_tab->aux_ant_evm_2ss_cnt[mac_id]++;
+			}
+		}
+
+	} else if (method == CRC32_METHOD) {
+		if (antsel_tr_mux == ANT1_2G) {
+			fat_tab->main_crc32_ok_cnt += utility;
+			fat_tab->main_crc32_fail_cnt++;
+		} else {
+			fat_tab->aux_crc32_ok_cnt += utility;
+			fat_tab->aux_crc32_fail_cnt++;
+		}
+
+	} else if (method == TP_METHOD) {
+		if ((utility <= ODM_RATEMCS15 && utility >= ODM_RATEMCS0) &&
+		    fat_tab->fat_state_cnt <= dm->antdiv_tp_period) {
+			if (antsel_tr_mux == ANT1_2G) {
+				fat_tab->antdiv_tp_main += (phy_rate_table[utility]) << 5;
+				fat_tab->antdiv_tp_main_cnt++;
+			} else {
+				fat_tab->antdiv_tp_aux += (phy_rate_table[utility]) << 5;
+				fat_tab->antdiv_tp_aux_cnt++;
+			}
+		}
+	}
+#endif
+}
+
+void odm_process_rssi_for_ant_div(
+	void *dm_void,
+	void *phy_info_void,
+	void *pkt_info_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct phydm_phyinfo_struct *phy_info = (struct phydm_phyinfo_struct *)phy_info_void;
+	struct phydm_perpkt_info_struct *pktinfo = (struct phydm_perpkt_info_struct *)pkt_info_void;
+	struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
+#if (defined(CONFIG_HL_SMART_ANTENNA))
+	struct smt_ant_honbo *sat_tab = &dm->dm_sat_table;
+	u32 beam_tmp;
+	u8 next_ant;
+	u8 train_pkt_number;
+#endif
+	u8 rx_power_ant0 = phy_info->rx_mimo_signal_strength[0];
+	u8 rx_power_ant1 = phy_info->rx_mimo_signal_strength[1];
+	u8 rx_evm_ant0 = phy_info->rx_mimo_signal_quality[0];
+	u8 rx_evm_ant1 = phy_info->rx_mimo_signal_quality[1];
+	u8 rssi_avg;
+
+	if ((dm->support_ic_type & ODM_IC_2SS) && !pktinfo->is_cck_rate) {
+		if (rx_power_ant1 < 100)
+			rssi_avg = (u8)odm_convert_to_db((phydm_db_2_linear(rx_power_ant0) + phydm_db_2_linear(rx_power_ant1)) >> 1); /*@averaged PWDB*/
+
+	} else {
+		rx_power_ant0 = (u8)phy_info->rx_pwdb_all;
+		rssi_avg = rx_power_ant0;
+	}
+
+#ifdef CONFIG_HL_SMART_ANTENNA_TYPE2
+	if ((dm->ant_div_type == HL_SW_SMART_ANT_TYPE2) && (fat_tab->fat_state == FAT_TRAINING_STATE))
+		phydm_process_rssi_for_hb_smtant_type2(dm, phy_info, pktinfo, rssi_avg); /*@for 8822B*/
+	else
+#endif
+
+#ifdef CONFIG_HL_SMART_ANTENNA_TYPE1
+#ifdef CONFIG_FAT_PATCH
+		if (dm->ant_div_type == HL_SW_SMART_ANT_TYPE1 && fat_tab->fat_state == FAT_TRAINING_STATE) {
+		/*@[Beacon]*/
+		if (pktinfo->is_packet_beacon) {
+			sat_tab->beacon_counter++;
+			PHYDM_DBG(dm, DBG_ANT_DIV,
+				  "MatchBSSID_beacon_counter = ((%d))\n",
+				  sat_tab->beacon_counter);
+
+			if (sat_tab->beacon_counter >= sat_tab->pre_beacon_counter + 2) {
+				if (sat_tab->ant_num > 1) {
+					next_ant = (fat_tab->rx_idle_ant == MAIN_ANT) ? AUX_ANT : MAIN_ANT;
+					odm_update_rx_idle_ant(dm, next_ant);
+				}
+
+				sat_tab->update_beam_idx++;
+
+				PHYDM_DBG(dm, DBG_ANT_DIV,
+					  "pre_beacon_counter = ((%d)), pkt_counter = ((%d)), update_beam_idx = ((%d))\n",
+					  sat_tab->pre_beacon_counter,
+					  sat_tab->pkt_counter,
+					  sat_tab->update_beam_idx);
+
+				sat_tab->pre_beacon_counter = sat_tab->beacon_counter;
+				sat_tab->pkt_counter = 0;
+			}
+		}
+		/*@[data]*/
+		else if (pktinfo->is_packet_to_self) {
+			if (sat_tab->pkt_skip_statistic_en == 0) {
+				/*@
+				PHYDM_DBG(dm, DBG_ANT_DIV, "StaID[%d]:  antsel_pathA = ((%d)), hw_antsw_occur = ((%d)), Beam_num = ((%d)), RSSI = ((%d))\n",
+					pktinfo->station_id, fat_tab->antsel_rx_keep_0, fat_tab->hw_antsw_occur, sat_tab->fast_training_beam_num, rx_power_ant0);
+				*/
+				PHYDM_DBG(dm, DBG_ANT_DIV,
+					  "ID[%d][pkt_cnt = %d]: {ANT, Beam} = {%d, %d}, RSSI = ((%d))\n",
+					  pktinfo->station_id,
+					  sat_tab->pkt_counter,
+					  fat_tab->antsel_rx_keep_0,
+					  sat_tab->fast_training_beam_num,
+					  rx_power_ant0);
+
+				sat_tab->pkt_rssi_sum[fat_tab->antsel_rx_keep_0][sat_tab->fast_training_beam_num] += rx_power_ant0;
+				sat_tab->pkt_rssi_cnt[fat_tab->antsel_rx_keep_0][sat_tab->fast_training_beam_num]++;
+				sat_tab->pkt_counter++;
+
+#if 1
+				train_pkt_number = sat_tab->beam_train_cnt[fat_tab->rx_idle_ant - 1][sat_tab->fast_training_beam_num];
+#else
+				train_pkt_number = sat_tab->per_beam_training_pkt_num;
+#endif
+
+				/*Swich Antenna erery N pkts*/
+				if (sat_tab->pkt_counter == train_pkt_number) {
+					if (sat_tab->ant_num > 1) {
+						PHYDM_DBG(dm, DBG_ANT_DIV, "packet enugh ((%d ))pkts ---> Switch antenna\n", train_pkt_number);
+						next_ant = (fat_tab->rx_idle_ant == MAIN_ANT) ? AUX_ANT : MAIN_ANT;
+						odm_update_rx_idle_ant(dm, next_ant);
+					}
+
+					sat_tab->update_beam_idx++;
+					PHYDM_DBG(dm, DBG_ANT_DIV, "pre_beacon_counter = ((%d)), update_beam_idx_counter = ((%d))\n",
+						  sat_tab->pre_beacon_counter, sat_tab->update_beam_idx);
+
+					sat_tab->pre_beacon_counter = sat_tab->beacon_counter;
+					sat_tab->pkt_counter = 0;
+				}
+			}
+		}
+
+		/*Swich Beam after switch "sat_tab->ant_num" antennas*/
+		if (sat_tab->update_beam_idx == sat_tab->ant_num) {
+			sat_tab->update_beam_idx = 0;
+			sat_tab->pkt_counter = 0;
+			beam_tmp = sat_tab->fast_training_beam_num;
+
+			if (sat_tab->fast_training_beam_num >= (sat_tab->beam_patten_num_each_ant - 1)) {
+				fat_tab->fat_state = FAT_DECISION_STATE;
+
+#if DEV_BUS_TYPE == RT_PCI_INTERFACE
+				odm_fast_ant_training_hl_smart_antenna_type1(dm);
+#else
+				odm_schedule_work_item(&sat_tab->hl_smart_antenna_decision_workitem);
+#endif
+
+			} else {
+				sat_tab->fast_training_beam_num++;
+				PHYDM_DBG(dm, DBG_ANT_DIV,
+					  "Update Beam_num (( %d )) -> (( %d ))\n",
+					  beam_tmp,
+					  sat_tab->fast_training_beam_num);
+				phydm_set_all_ant_same_beam_num(dm);
+
+				fat_tab->fat_state = FAT_TRAINING_STATE;
+			}
+		}
+	}
+#else
+
+		if (dm->ant_div_type == HL_SW_SMART_ANT_TYPE1) {
+		if ((dm->support_ic_type & ODM_HL_SMART_ANT_TYPE1_SUPPORT) &&
+		    pktinfo->is_packet_to_self &&
+		    fat_tab->fat_state == FAT_TRAINING_STATE) {
+			if (sat_tab->pkt_skip_statistic_en == 0) {
+				/*@
+				PHYDM_DBG(dm, DBG_ANT_DIV, "StaID[%d]:  antsel_pathA = ((%d)), hw_antsw_occur = ((%d)), Beam_num = ((%d)), RSSI = ((%d))\n",
+					pktinfo->station_id, fat_tab->antsel_rx_keep_0, fat_tab->hw_antsw_occur, sat_tab->fast_training_beam_num, rx_power_ant0);
+				*/
+				PHYDM_DBG(dm, DBG_ANT_DIV,
+					  "StaID[%d]:  antsel_pathA = ((%d)), is_packet_to_self = ((%d)), Beam_num = ((%d)), RSSI = ((%d))\n",
+					  pktinfo->station_id,
+					  fat_tab->antsel_rx_keep_0,
+					  pktinfo->is_packet_to_self,
+					  sat_tab->fast_training_beam_num,
+					  rx_power_ant0);
+
+				sat_tab->pkt_rssi_sum[fat_tab->antsel_rx_keep_0][sat_tab->fast_training_beam_num] += rx_power_ant0;
+				sat_tab->pkt_rssi_cnt[fat_tab->antsel_rx_keep_0][sat_tab->fast_training_beam_num]++;
+				sat_tab->pkt_counter++;
+
+				/*swich beam every N pkt*/
+				if (sat_tab->pkt_counter >= sat_tab->per_beam_training_pkt_num) {
+					sat_tab->pkt_counter = 0;
+					beam_tmp = sat_tab->fast_training_beam_num;
+
+					if (sat_tab->fast_training_beam_num >= (sat_tab->beam_patten_num_each_ant - 1)) {
+						fat_tab->fat_state = FAT_DECISION_STATE;
+
+#if DEV_BUS_TYPE == RT_PCI_INTERFACE
+						odm_fast_ant_training_hl_smart_antenna_type1(dm);
+#else
+						odm_schedule_work_item(&sat_tab->hl_smart_antenna_decision_workitem);
+#endif
+
+					} else {
+						sat_tab->fast_training_beam_num++;
+						phydm_set_all_ant_same_beam_num(dm);
+
+						fat_tab->fat_state = FAT_TRAINING_STATE;
+						PHYDM_DBG(dm, DBG_ANT_DIV, "Update  Beam_num (( %d )) -> (( %d ))\n", beam_tmp, sat_tab->fast_training_beam_num);
+					}
+				}
+			}
+		}
+	}
+#endif
+	else
+#endif
+		if (dm->ant_div_type == CG_TRX_SMART_ANTDIV) {
+		if ((dm->support_ic_type & ODM_SMART_ANT_SUPPORT) && pktinfo->is_packet_to_self && fat_tab->fat_state == FAT_TRAINING_STATE) { /* @(pktinfo->is_packet_match_bssid && (!pktinfo->is_packet_beacon)) */
+			u8 antsel_tr_mux;
+			antsel_tr_mux = (fat_tab->antsel_rx_keep_2 << 2) | (fat_tab->antsel_rx_keep_1 << 1) | fat_tab->antsel_rx_keep_0;
+			fat_tab->ant_sum_rssi[antsel_tr_mux] += rx_power_ant0;
+			fat_tab->ant_rssi_cnt[antsel_tr_mux]++;
+		}
+	} else { /* @ant_div_type != CG_TRX_SMART_ANTDIV */
+		if ((dm->support_ic_type & ODM_ANTDIV_SUPPORT) && (pktinfo->is_packet_to_self || fat_tab->use_ctrl_frame_antdiv)) {
+			if (dm->ant_div_type == S0S1_SW_ANTDIV) {
+				if (pktinfo->is_cck_rate || dm->support_ic_type == ODM_RTL8188F)
+					fat_tab->antsel_rx_keep_0 = (fat_tab->rx_idle_ant == MAIN_ANT) ? ANT1_2G : ANT2_2G;
+
+				odm_antsel_statistics(dm, phy_info, fat_tab->antsel_rx_keep_0, pktinfo->station_id, rx_power_ant0, RSSI_METHOD, pktinfo->is_cck_rate);
+
+			} else {
+				odm_antsel_statistics(dm, phy_info, fat_tab->antsel_rx_keep_0, pktinfo->station_id, rx_power_ant0, RSSI_METHOD, pktinfo->is_cck_rate);
+
+				#ifdef ODM_EVM_ENHANCE_ANTDIV
+				if (dm->support_ic_type & ODM_EVM_ENHANCE_ANTDIV_SUPPORT_IC) {
+					if (!pktinfo->is_cck_rate) {
+						odm_antsel_statistics(dm, phy_info, fat_tab->antsel_rx_keep_0, pktinfo->station_id, rx_evm_ant0, EVM_METHOD, pktinfo->is_cck_rate);
+						odm_antsel_statistics(dm, phy_info, fat_tab->antsel_rx_keep_0, pktinfo->station_id, rx_evm_ant0, TP_METHOD, pktinfo->is_cck_rate);
+					}
+				}
+				#endif
+			}
+		}
+	}
+#if 0
+	/* PHYDM_DBG(dm,DBG_ANT_DIV,"is_cck_rate=%d, pwdb_all=%d\n",pktinfo->is_cck_rate, phy_info->rx_pwdb_all); */
+	/* PHYDM_DBG(dm,DBG_ANT_DIV,"antsel_tr_mux=3'b%d%d%d\n",fat_tab->antsel_rx_keep_2, fat_tab->antsel_rx_keep_1, fat_tab->antsel_rx_keep_0); */
+#endif
+}
+
+#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
+void odm_set_tx_ant_by_tx_info(
+	void *dm_void,
+	u8 *desc,
+	u8 mac_id
+
+	)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
+
+	if (!(dm->support_ability & ODM_BB_ANT_DIV))
+		return;
+
+	if (dm->ant_div_type == CGCS_RX_HW_ANTDIV)
+		return;
+
+	if (dm->support_ic_type == ODM_RTL8723B) {
+#if (RTL8723B_SUPPORT == 1)
+		SET_TX_DESC_ANTSEL_A_8723B(desc, fat_tab->antsel_a[mac_id]);
+		/*PHYDM_DBG(dm,DBG_ANT_DIV, "[8723B] SetTxAntByTxInfo_WIN: mac_id=%d, antsel_tr_mux=3'b%d%d%d\n",
+			mac_id, fat_tab->antsel_c[mac_id], fat_tab->antsel_b[mac_id], fat_tab->antsel_a[mac_id]);*/
+#endif
+	} else if (dm->support_ic_type == ODM_RTL8821) {
+#if (RTL8821A_SUPPORT == 1)
+		SET_TX_DESC_ANTSEL_A_8812(desc, fat_tab->antsel_a[mac_id]);
+		/*PHYDM_DBG(dm,DBG_ANT_DIV, "[8821A] SetTxAntByTxInfo_WIN: mac_id=%d, antsel_tr_mux=3'b%d%d%d\n",
+			mac_id, fat_tab->antsel_c[mac_id], fat_tab->antsel_b[mac_id], fat_tab->antsel_a[mac_id]);*/
+#endif
+	} else if (dm->support_ic_type == ODM_RTL8188E) {
+#if (RTL8188E_SUPPORT == 1)
+		SET_TX_DESC_ANTSEL_A_88E(desc, fat_tab->antsel_a[mac_id]);
+		SET_TX_DESC_ANTSEL_B_88E(desc, fat_tab->antsel_b[mac_id]);
+		SET_TX_DESC_ANTSEL_C_88E(desc, fat_tab->antsel_c[mac_id]);
+		/*PHYDM_DBG(dm,DBG_ANT_DIV, "[8188E] SetTxAntByTxInfo_WIN: mac_id=%d, antsel_tr_mux=3'b%d%d%d\n",
+			mac_id, fat_tab->antsel_c[mac_id], fat_tab->antsel_b[mac_id], fat_tab->antsel_a[mac_id]);*/
+#endif
+	} else if (dm->support_ic_type == ODM_RTL8821C) {
+#if (RTL8821C_SUPPORT == 1)
+		SET_TX_DESC_ANTSEL_A_8821C(desc, fat_tab->antsel_a[mac_id]);
+		/*PHYDM_DBG(dm,DBG_ANT_DIV, "[8821C] SetTxAntByTxInfo_WIN: mac_id=%d, antsel_tr_mux=3'b%d%d%d\n",
+			mac_id, fat_tab->antsel_c[mac_id], fat_tab->antsel_b[mac_id], fat_tab->antsel_a[mac_id]);*/
+#endif
+	} else if (dm->support_ic_type == ODM_RTL8822B) {
+#if (RTL8822B_SUPPORT == 1)
+		SET_TX_DESC_ANTSEL_A_8822B(desc, fat_tab->antsel_a[mac_id]);
+#endif
+
+	}
+}
+#elif (DM_ODM_SUPPORT_TYPE == ODM_AP)
+
+void odm_set_tx_ant_by_tx_info(
+	struct rtl8192cd_priv *priv,
+	struct tx_desc *pdesc,
+	unsigned short aid)
+{
+	struct dm_struct *dm = GET_PDM_ODM(priv); /*@&(priv->pshare->_dmODM);*/
+	struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
+
+	if (!(dm->support_ability & ODM_BB_ANT_DIV))
+		return;
+
+	if (dm->ant_div_type == CGCS_RX_HW_ANTDIV)
+		return;
+
+	if (dm->support_ic_type == ODM_RTL8881A) {
+#if 0
+		/*panic_printk("[%s] [%d]   ******ODM_SetTxAntByTxInfo_8881E******\n",__FUNCTION__,__LINE__);	*/
+#endif
+		pdesc->Dword6 &= set_desc(~(BIT(18) | BIT(17) | BIT(16)));
+		pdesc->Dword6 |= set_desc(fat_tab->antsel_a[aid] << 16);
+	} else if (dm->support_ic_type == ODM_RTL8192E) {
+#if 0
+		/*panic_printk("[%s] [%d]   ******ODM_SetTxAntByTxInfo_8192E******\n",__FUNCTION__,__LINE__);	*/
+#endif
+		pdesc->Dword6 &= set_desc(~(BIT(18) | BIT(17) | BIT(16)));
+		pdesc->Dword6 |= set_desc(fat_tab->antsel_a[aid] << 16);
+	} else if (dm->support_ic_type == ODM_RTL8197F) {
+#if 0
+		/*panic_printk("[%s] [%d]   ******ODM_SetTxAntByTxInfo_8192E******\n",__FUNCTION__,__LINE__);	*/
+#endif
+		pdesc->Dword6 &= set_desc(~(BIT(17) | BIT(16)));
+		pdesc->Dword6 |= set_desc(fat_tab->antsel_a[aid] << 16);
+	} else if (dm->support_ic_type == ODM_RTL8822B) {
+		pdesc->Dword6 &= set_desc(~(BIT(17) | BIT(16)));
+		pdesc->Dword6 |= set_desc(fat_tab->antsel_a[aid] << 16);
+	} else if (dm->support_ic_type == ODM_RTL8188E) {
+#if 0
+		/*panic_printk("[%s] [%d]   ******ODM_SetTxAntByTxInfo_8188E******\n",__FUNCTION__,__LINE__);*/
+#endif
+		pdesc->Dword2 &= set_desc(~BIT(24));
+		pdesc->Dword2 &= set_desc(~BIT(25));
+		pdesc->Dword7 &= set_desc(~BIT(29));
+
+		pdesc->Dword2 |= set_desc(fat_tab->antsel_a[aid] << 24);
+		pdesc->Dword2 |= set_desc(fat_tab->antsel_b[aid] << 25);
+		pdesc->Dword7 |= set_desc(fat_tab->antsel_c[aid] << 29);
+
+	} else if (dm->support_ic_type == ODM_RTL8812) {
+		/*@[path-A]*/
+#if 0
+		/*panic_printk("[%s] [%d]   ******ODM_SetTxAntByTxInfo_8881E******\n",__FUNCTION__,__LINE__);*/
+#endif
+
+		pdesc->Dword6 &= set_desc(~BIT(16));
+		pdesc->Dword6 &= set_desc(~BIT(17));
+		pdesc->Dword6 &= set_desc(~BIT(18));
+
+		pdesc->Dword6 |= set_desc(fat_tab->antsel_a[aid] << 16);
+		pdesc->Dword6 |= set_desc(fat_tab->antsel_b[aid] << 17);
+		pdesc->Dword6 |= set_desc(fat_tab->antsel_c[aid] << 18);
+	}
+}
+
+#if 1 /*@def CONFIG_WLAN_HAL*/
+void odm_set_tx_ant_by_tx_info_hal(
+	struct rtl8192cd_priv *priv,
+	void *pdesc_data,
+	u16 aid)
+{
+	struct dm_struct *dm = GET_PDM_ODM(priv); /*@&(priv->pshare->_dmODM);*/
+	struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
+	PTX_DESC_DATA_88XX pdescdata = (PTX_DESC_DATA_88XX)pdesc_data;
+
+	if (!(dm->support_ability & ODM_BB_ANT_DIV))
+		return;
+
+	if (dm->ant_div_type == CGCS_RX_HW_ANTDIV)
+		return;
+
+	if (dm->support_ic_type & (ODM_RTL8881A | ODM_RTL8192E | ODM_RTL8814A | ODM_RTL8197F | ODM_RTL8822B)) {
+#if 0
+		/*panic_printk("[%s] [%d] ******odm_set_tx_ant_by_tx_info_hal******\n",__FUNCTION__,__LINE__);*/
+#endif
+		pdescdata->ant_sel = 1;
+		pdescdata->ant_sel_a = fat_tab->antsel_a[aid];
+	}
+}
+#endif /*@#ifdef CONFIG_WLAN_HAL*/
+
+#endif
+
+void odm_ant_div_config(
+	void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
+#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN))
+	PHYDM_DBG(dm, DBG_ANT_DIV, "WIN Config Antenna Diversity\n");
+	/*@
+	if(dm->support_ic_type==ODM_RTL8723B)
+	{
+		if((!dm->dm_swat_table.ANTA_ON || !dm->dm_swat_table.ANTB_ON))
+			dm->support_ability &= ~(ODM_BB_ANT_DIV);
+	}
+	*/
+	#if (defined(CONFIG_2T3R_ANTENNA))
+	#if (RTL8822B_SUPPORT == 1)
+		dm->rfe_type = ANT_2T3R_RFE_TYPE;
+	#endif
+	#endif
+
+	#if (defined(CONFIG_2T4R_ANTENNA))
+	#if (RTL8822B_SUPPORT == 1)
+		dm->rfe_type = ANT_2T4R_RFE_TYPE;
+	#endif
+	#endif
+
+	if (dm->support_ic_type == ODM_RTL8723D)
+		dm->ant_div_type = S0S1_TRX_HW_ANTDIV;
+#elif (DM_ODM_SUPPORT_TYPE & (ODM_CE))
+
+	PHYDM_DBG(dm, DBG_ANT_DIV, "CE Config Antenna Diversity\n");
+
+	if (dm->support_ic_type == ODM_RTL8723B)
+		dm->ant_div_type = S0S1_SW_ANTDIV;
+
+	if (dm->support_ic_type == ODM_RTL8723D)
+		dm->ant_div_type = S0S1_SW_ANTDIV;
+
+#elif (DM_ODM_SUPPORT_TYPE & (ODM_AP))
+
+	PHYDM_DBG(dm, DBG_ANT_DIV, "AP Config Antenna Diversity\n");
+
+	/* @2 [ NOT_SUPPORT_ANTDIV ] */
+#if (defined(CONFIG_NOT_SUPPORT_ANTDIV))
+	dm->support_ability &= ~(ODM_BB_ANT_DIV);
+	PHYDM_DBG(dm, DBG_ANT_DIV,
+		  "[ Disable AntDiv function] : Not Support 2.4G & 5G Antenna Diversity\n");
+
+	/* @2 [ 2G&5G_SUPPORT_ANTDIV ] */
+#elif (defined(CONFIG_2G5G_SUPPORT_ANTDIV))
+	PHYDM_DBG(dm, DBG_ANT_DIV,
+		  "[ Enable AntDiv function] : 2.4G & 5G Support Antenna Diversity Simultaneously\n");
+	fat_tab->ant_div_2g_5g = (ODM_ANTDIV_2G | ODM_ANTDIV_5G);
+
+	if (dm->support_ic_type & ODM_ANTDIV_SUPPORT)
+		dm->support_ability |= ODM_BB_ANT_DIV;
+	if (*dm->band_type == ODM_BAND_5G) {
+#if (defined(CONFIG_5G_CGCS_RX_DIVERSITY))
+		dm->ant_div_type = CGCS_RX_HW_ANTDIV;
+		PHYDM_DBG(dm, DBG_ANT_DIV,
+			  "[ 5G] : AntDiv type = CGCS_RX_HW_ANTDIV\n");
+		panic_printk("[ 5G] : AntDiv type = CGCS_RX_HW_ANTDIV\n");
+#elif (defined(CONFIG_5G_CG_TRX_DIVERSITY) || defined(CONFIG_2G5G_CG_TRX_DIVERSITY_8881A))
+		dm->ant_div_type = CG_TRX_HW_ANTDIV;
+		PHYDM_DBG(dm, DBG_ANT_DIV,
+			  "[ 5G] : AntDiv type = CG_TRX_HW_ANTDIV\n");
+		panic_printk("[ 5G] : AntDiv type = CG_TRX_HW_ANTDIV\n");
+#elif (defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY))
+		dm->ant_div_type = CG_TRX_SMART_ANTDIV;
+		PHYDM_DBG(dm, DBG_ANT_DIV,
+			  "[ 5G] : AntDiv type = CG_SMART_ANTDIV\n");
+#elif (defined(CONFIG_5G_S0S1_SW_ANT_DIVERSITY))
+		dm->ant_div_type = S0S1_SW_ANTDIV;
+		PHYDM_DBG(dm, DBG_ANT_DIV,
+			  "[ 5G] : AntDiv type = S0S1_SW_ANTDIV\n");
+#endif
+	} else if (*dm->band_type == ODM_BAND_2_4G) {
+#if (defined(CONFIG_2G_CGCS_RX_DIVERSITY))
+		dm->ant_div_type = CGCS_RX_HW_ANTDIV;
+		PHYDM_DBG(dm, DBG_ANT_DIV,
+			  "[ 2.4G] : AntDiv type = CGCS_RX_HW_ANTDIV\n");
+#elif (defined(CONFIG_2G_CG_TRX_DIVERSITY) || defined(CONFIG_2G5G_CG_TRX_DIVERSITY_8881A))
+		dm->ant_div_type = CG_TRX_HW_ANTDIV;
+		PHYDM_DBG(dm, DBG_ANT_DIV,
+			  "[ 2.4G] : AntDiv type = CG_TRX_HW_ANTDIV\n");
+#elif (defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY))
+		dm->ant_div_type = CG_TRX_SMART_ANTDIV;
+		PHYDM_DBG(dm, DBG_ANT_DIV,
+			  "[ 2.4G] : AntDiv type = CG_SMART_ANTDIV\n");
+#elif (defined(CONFIG_2G_S0S1_SW_ANT_DIVERSITY))
+		dm->ant_div_type = S0S1_SW_ANTDIV;
+		PHYDM_DBG(dm, DBG_ANT_DIV,
+			  "[ 2.4G] : AntDiv type = S0S1_SW_ANTDIV\n");
+#endif
+	}
+
+	/* @2 [ 5G_SUPPORT_ANTDIV ] */
+#elif (defined(CONFIG_5G_SUPPORT_ANTDIV))
+	PHYDM_DBG(dm, DBG_ANT_DIV,
+		  "[ Enable AntDiv function] : Only 5G Support Antenna Diversity\n");
+	panic_printk("[ Enable AntDiv function] : Only 5G Support Antenna Diversity\n");
+	fat_tab->ant_div_2g_5g = (ODM_ANTDIV_5G);
+	if (*dm->band_type == ODM_BAND_5G) {
+		if (dm->support_ic_type & ODM_ANTDIV_5G_SUPPORT_IC)
+			dm->support_ability |= ODM_BB_ANT_DIV;
+#if (defined(CONFIG_5G_CGCS_RX_DIVERSITY))
+		dm->ant_div_type = CGCS_RX_HW_ANTDIV;
+		PHYDM_DBG(dm, DBG_ANT_DIV,
+			  "[ 5G] : AntDiv type = CGCS_RX_HW_ANTDIV\n");
+		panic_printk("[ 5G] : AntDiv type = CGCS_RX_HW_ANTDIV\n");
+#elif (defined(CONFIG_5G_CG_TRX_DIVERSITY))
+		dm->ant_div_type = CG_TRX_HW_ANTDIV;
+		panic_printk("[ 5G] : AntDiv type = CG_TRX_HW_ANTDIV\n");
+		PHYDM_DBG(dm, DBG_ANT_DIV,
+			  "[ 5G] : AntDiv type = CG_TRX_HW_ANTDIV\n");
+#elif (defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY))
+		dm->ant_div_type = CG_TRX_SMART_ANTDIV;
+		PHYDM_DBG(dm, DBG_ANT_DIV,
+			  "[ 5G] : AntDiv type = CG_SMART_ANTDIV\n");
+#elif (defined(CONFIG_5G_S0S1_SW_ANT_DIVERSITY))
+		dm->ant_div_type = S0S1_SW_ANTDIV;
+		PHYDM_DBG(dm, DBG_ANT_DIV,
+			  "[ 5G] : AntDiv type = S0S1_SW_ANTDIV\n");
+#endif
+	} else if (*dm->band_type == ODM_BAND_2_4G) {
+		PHYDM_DBG(dm, DBG_ANT_DIV, "Not Support 2G ant_div_type\n");
+		dm->support_ability &= ~(ODM_BB_ANT_DIV);
+	}
+
+	/* @2 [ 2G_SUPPORT_ANTDIV ] */
+#elif (defined(CONFIG_2G_SUPPORT_ANTDIV))
+	PHYDM_DBG(dm, DBG_ANT_DIV,
+		  "[ Enable AntDiv function] : Only 2.4G Support Antenna Diversity\n");
+	fat_tab->ant_div_2g_5g = (ODM_ANTDIV_2G);
+	if (*dm->band_type == ODM_BAND_2_4G) {
+		if (dm->support_ic_type & ODM_ANTDIV_2G_SUPPORT_IC)
+			dm->support_ability |= ODM_BB_ANT_DIV;
+#if (defined(CONFIG_2G_CGCS_RX_DIVERSITY))
+		dm->ant_div_type = CGCS_RX_HW_ANTDIV;
+		PHYDM_DBG(dm, DBG_ANT_DIV,
+			  "[ 2.4G] : AntDiv type = CGCS_RX_HW_ANTDIV\n");
+#elif (defined(CONFIG_2G_CG_TRX_DIVERSITY))
+		dm->ant_div_type = CG_TRX_HW_ANTDIV;
+		PHYDM_DBG(dm, DBG_ANT_DIV,
+			  "[ 2.4G] : AntDiv type = CG_TRX_HW_ANTDIV\n");
+#elif (defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY))
+		dm->ant_div_type = CG_TRX_SMART_ANTDIV;
+		PHYDM_DBG(dm, DBG_ANT_DIV,
+			  "[ 2.4G] : AntDiv type = CG_SMART_ANTDIV\n");
+#elif (defined(CONFIG_2G_S0S1_SW_ANT_DIVERSITY))
+		dm->ant_div_type = S0S1_SW_ANTDIV;
+		PHYDM_DBG(dm, DBG_ANT_DIV,
+			  "[ 2.4G] : AntDiv type = S0S1_SW_ANTDIV\n");
+#endif
+	} else if (*dm->band_type == ODM_BAND_5G) {
+		PHYDM_DBG(dm, DBG_ANT_DIV, "Not Support 5G ant_div_type\n");
+		dm->support_ability &= ~(ODM_BB_ANT_DIV);
+	}
+#endif
+#endif
+
+	PHYDM_DBG(dm, DBG_ANT_DIV,
+		  "[AntDiv Config Info] AntDiv_SupportAbility = (( %x ))\n",
+		  ((dm->support_ability & ODM_BB_ANT_DIV) ? 1 : 0));
+	PHYDM_DBG(dm, DBG_ANT_DIV,
+		  "[AntDiv Config Info] be_fix_tx_ant = ((%d))\n",
+		  dm->dm_fat_table.b_fix_tx_ant);
+}
+
+void odm_ant_div_timers(
+	void *dm_void,
+	u8 state)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	if (state == INIT_ANTDIV_TIMMER) {
+#ifdef CONFIG_S0S1_SW_ANTENNA_DIVERSITY
+		odm_initialize_timer(dm,
+				     &dm->dm_swat_table.phydm_sw_antenna_switch_timer,
+				     (void *)odm_sw_antdiv_callback, NULL,
+				     "phydm_sw_antenna_switch_timer");
+#elif (defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY)) || (defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY))
+		odm_initialize_timer(dm, &dm->fast_ant_training_timer,
+				     (void *)odm_fast_ant_training_callback, NULL, "fast_ant_training_timer");
+#endif
+
+#ifdef ODM_EVM_ENHANCE_ANTDIV
+		odm_initialize_timer(dm, &dm->evm_fast_ant_training_timer,
+				     (void *)phydm_evm_antdiv_callback, NULL,
+				     "evm_fast_ant_training_timer");
+#endif
+	} else if (state == CANCEL_ANTDIV_TIMMER) {
+#ifdef CONFIG_S0S1_SW_ANTENNA_DIVERSITY
+		odm_cancel_timer(dm,
+				 &dm->dm_swat_table.phydm_sw_antenna_switch_timer);
+#elif (defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY)) || (defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY))
+		odm_cancel_timer(dm, &dm->fast_ant_training_timer);
+#endif
+
+#ifdef ODM_EVM_ENHANCE_ANTDIV
+		odm_cancel_timer(dm, &dm->evm_fast_ant_training_timer);
+#endif
+	} else if (state == RELEASE_ANTDIV_TIMMER) {
+#ifdef CONFIG_S0S1_SW_ANTENNA_DIVERSITY
+		odm_release_timer(dm,
+				  &dm->dm_swat_table.phydm_sw_antenna_switch_timer);
+#elif (defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY)) || (defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY))
+		odm_release_timer(dm, &dm->fast_ant_training_timer);
+#endif
+
+#ifdef ODM_EVM_ENHANCE_ANTDIV
+		odm_release_timer(dm, &dm->evm_fast_ant_training_timer);
+#endif
+	}
+}
+
+void phydm_antdiv_debug(void *dm_void, char input[][16], u32 *_used,
+			char *output, u32 *_out_len)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct phydm_fat_struct	*fat_tab = &dm->dm_fat_table;
+	u32 used = *_used;
+	u32 out_len = *_out_len;
+	u32 dm_value[10] = {0};
+	char help[] = "-h";
+	u8 i, input_idx = 0;
+
+	for (i = 0; i < 5; i++) {
+		if (input[i + 1]) {
+			PHYDM_SSCANF(input[i + 1], DCMD_HEX, &dm_value[i]);
+			input_idx++;
+		}
+	}
+
+	if (input_idx == 0)
+		return;
+
+	if ((strcmp(input[1], help) == 0)) {
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "{1} {0:auto, 1:fix main, 2:fix auto}\n");
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "{2} {antdiv_period}\n");
+		#if (RTL8821C_SUPPORT == 1)
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "{3} {en} {0:Default, 1:HW_Div, 2:SW_Div}\n");
+		#endif
+
+	} else if (dm_value[0] == 1) {
+	/*@fixed or auto antenna*/
+		if (dm_value[1] == 0) {
+			dm->ant_type = ODM_AUTO_ANT;
+			PDM_SNPF(out_len, used, output + used, out_len - used,
+				 "AntDiv: Auto\n");
+		} else if (dm_value[1] == 1) {
+			dm->ant_type = ODM_FIX_MAIN_ANT;
+			PDM_SNPF(out_len, used, output + used, out_len - used,
+				 "AntDiv: Fix Main\n");
+		} else if (dm_value[1] == 2) {
+			dm->ant_type = ODM_FIX_AUX_ANT;
+			PDM_SNPF(out_len, used, output + used, out_len - used,
+				 "AntDiv: Fix Aux\n");
+		}
+
+		if (dm->ant_type != ODM_AUTO_ANT) {
+			odm_stop_antenna_switch_dm(dm);
+			if (dm->ant_type == ODM_FIX_MAIN_ANT)
+				odm_update_rx_idle_ant(dm, MAIN_ANT);
+			else if (dm->ant_type == ODM_FIX_AUX_ANT)
+				odm_update_rx_idle_ant(dm, AUX_ANT);
+		} else {
+			phydm_enable_antenna_diversity(dm);
+		}
+		dm->pre_ant_type = dm->ant_type;
+	} else if (dm_value[0] == 2) {
+	/*@dynamic period for AntDiv*/
+		dm->antdiv_period = (u8)dm_value[1];
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "AntDiv_period=((%d))\n", dm->antdiv_period);
+	}
+	#if (RTL8821C_SUPPORT == 1)
+	else if (dm_value[0] == 3 &&
+		 dm->support_ic_type == ODM_RTL8821C) {
+		/*Only for 8821C*/
+		if (dm_value[1] == 0) {
+			fat_tab->force_antdiv_type = false;
+			PDM_SNPF(out_len, used, output + used, out_len - used,
+				 "[8821C] AntDiv: Default\n");
+		} else if (dm_value[1] == 1) {
+			fat_tab->force_antdiv_type = true;
+			fat_tab->antdiv_type_dbg = CG_TRX_HW_ANTDIV;
+			PDM_SNPF(out_len, used, output + used, out_len - used,
+				 "[8821C] AntDiv: HW diversity\n");
+		} else if (dm_value[1] == 2) {
+			fat_tab->force_antdiv_type = true;
+			fat_tab->antdiv_type_dbg = S0S1_SW_ANTDIV;
+			PDM_SNPF(out_len, used, output + used, out_len - used,
+				 "[8821C] AntDiv: SW diversity\n");
+		}
+	}
+	#endif
+	#ifdef ODM_EVM_ENHANCE_ANTDIV
+	else if (dm_value[0] == 4) {
+		if (dm_value[1] == 0) {
+			/*@init parameters for EVM AntDiv*/
+			phydm_evm_sw_antdiv_init(dm);
+			PDM_SNPF(out_len, used, output + used, out_len - used,
+				 "init evm antdiv parameters\n");
+		} else if (dm_value[1] == 1) {
+			/*training number for EVM AntDiv*/
+			dm->antdiv_train_num = (u8)dm_value[2];
+			PDM_SNPF(out_len, used, output + used, out_len - used,
+				 "antdiv_train_num = ((%d))\n",
+				 dm->antdiv_train_num);
+		} else if (dm_value[1] == 2) {
+			/*training interval for EVM AntDiv*/
+			dm->antdiv_intvl = (u8)dm_value[2];
+			PDM_SNPF(out_len, used, output + used, out_len - used,
+				 "antdiv_intvl = ((%d))\n",
+				 dm->antdiv_intvl);
+		} else if (dm_value[1] == 3) {
+			/*@function period for EVM AntDiv*/
+			dm->evm_antdiv_period = (u8)dm_value[2];
+			PDM_SNPF(out_len, used, output + used, out_len - used,
+				 "evm_antdiv_period = ((%d))\n",
+				 dm->evm_antdiv_period);
+		} else if (dm_value[1] == 100) {/*show parameters*/
+			PDM_SNPF(out_len, used, output + used, out_len - used,
+				 "ant_type = ((%d))\n", dm->ant_type);
+			PDM_SNPF(out_len, used, output + used, out_len - used,
+				 "antdiv_train_num = ((%d))\n",
+				 dm->antdiv_train_num);
+			PDM_SNPF(out_len, used, output + used, out_len - used,
+				 "antdiv_intvl = ((%d))\n",
+				 dm->antdiv_intvl);
+			PDM_SNPF(out_len, used, output + used, out_len - used,
+				 "evm_antdiv_period = ((%d))\n",
+				 dm->evm_antdiv_period);
+		}
+	}
+	#ifdef CONFIG_2T4R_ANTENNA
+	else if (dm_value[0] == 5) { /*Only for 8822B 2T4R case*/
+
+		if (dm_value[1] == 0) {
+			dm->ant_type2 = ODM_AUTO_ANT;
+			PDM_SNPF(out_len, used, output + used, out_len - used,
+				 "AntDiv: PathB Auto\n");
+		} else if (dm_value[1] == 1) {
+			dm->ant_type2 = ODM_FIX_MAIN_ANT;
+			PDM_SNPF(out_len, used, output + used, out_len - used,
+				 "AntDiv: PathB Fix Main\n");
+		} else if (dm_value[1] == 2) {
+			dm->ant_type2 = ODM_FIX_AUX_ANT;
+			PDM_SNPF(out_len, used, output + used, out_len - used,
+				 "AntDiv: PathB Fix Aux\n");
+		}
+
+		if (dm->ant_type2 != ODM_AUTO_ANT) {
+			odm_stop_antenna_switch_dm(dm);
+			if (dm->ant_type2 == ODM_FIX_MAIN_ANT)
+				phydm_update_rx_idle_ant_pathb(dm, MAIN_ANT);
+			else if (dm->ant_type2 == ODM_FIX_AUX_ANT)
+				phydm_update_rx_idle_ant_pathb(dm, AUX_ANT);
+		} else {
+			phydm_enable_antenna_diversity(dm);
+		}
+		dm->pre_ant_type2 = dm->ant_type2;
+	}
+	#endif
+	#endif
+	*_used = used;
+	*_out_len = out_len;
+}
+
+void odm_ant_div_reset(void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+
+	#ifdef CONFIG_S0S1_SW_ANTENNA_DIVERSITY
+	if (dm->ant_div_type == S0S1_SW_ANTDIV)
+		odm_s0s1_sw_ant_div_reset(dm);
+	#endif
+}
+
+void odm_antenna_diversity_init(void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+
+	odm_ant_div_config(dm);
+	odm_ant_div_init(dm);
+}
+
+void odm_antenna_diversity(void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+
+	if (*dm->mp_mode)
+		return;
+
+	if (!(dm->support_ability & ODM_BB_ANT_DIV)) {
+		PHYDM_DBG(dm, DBG_ANT_DIV,
+			  "[Return!!!]   Not Support Antenna Diversity Function\n");
+		return;
+	}
+
+	if (dm->pause_ability & ODM_BB_ANT_DIV) {
+		PHYDM_DBG(dm, DBG_ANT_DIV, "Return: Pause AntDIv in LV=%d\n",
+			  dm->pause_lv_table.lv_antdiv);
+		return;
+	}
+
+	odm_ant_div(dm);
+}
+#endif /*@#ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY*/
+
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/phydm_antdiv.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/phydm_antdiv.h
--- linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/phydm_antdiv.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/phydm_antdiv.h	2020-04-10 16:35:06.823660394 +0300
@@ -0,0 +1,544 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017  Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * The full GNU General Public License is included in this distribution in the
+ * file called LICENSE.
+ *
+ * Contact Information:
+ * wlanfae <wlanfae@realtek.com>
+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
+ * Hsinchu 300, Taiwan.
+ *
+ * Larry Finger <Larry.Finger@lwfinger.net>
+ *
+ *****************************************************************************/
+
+#ifndef __PHYDMANTDIV_H__
+#define __PHYDMANTDIV_H__
+
+/*@#define ANTDIV_VERSION	"2.0"  //2014.11.04*/
+/*@#define ANTDIV_VERSION	"2.1"  //2015.01.13  Dino*/
+/*@#define ANTDIV_VERSION	"2.2"  2015.01.16  Dino*/
+/*@#define ANTDIV_VERSION	"3.1"  2015.07.29  YuChen, remove 92c 92d 8723a*/
+/*@#define ANTDIV_VERSION	"3.2"  2015.08.11  Stanley, disable antenna diversity when BT is enable for 8723B*/
+/*@#define ANTDIV_VERSION	"3.3"  2015.08.12  Stanley. 8723B does not need to check the antenna is control by BT, because antenna diversity only works when BT is disable or radio off*/
+/*@#define ANTDIV_VERSION	"3.4"  2015.08.28  Dino  1.Add 8821A Smart Antenna 2. Add 8188F SW S0S1 Antenna Diversity*/
+/*@#define ANTDIV_VERSION	"3.5"  2015.10.07  Stanley  Always check antenna detection result from BT-coex. for 8723B, not from PHYDM*/
+/*@#define ANTDIV_VERSION	"3.6"*/ /*@2015.11.16  Stanley  */
+/*@#define ANTDIV_VERSION	"3.7"*/ /*@2015.11.20  Dino Add SmartAnt FAT Patch */
+/*@#define ANTDIV_VERSION	"3.8"  2015.12.21  Dino, Add SmartAnt dynamic training packet num */
+/*@#define ANTDIV_VERSION	"3.9"  2016.01.05  Dino, Add SmartAnt cmd for converting single & two smtant, and add cmd for adjust truth table */
+#define ANTDIV_VERSION "4.0" /*@2017.05.25  Mark, Add SW antenna diversity for 8821c because HW transient issue */
+
+/* @1 ============================================================
+ * 1  Definition
+ * 1 ============================================================
+ */
+
+#define	ANTDIV_INIT		0xff
+#define	MAIN_ANT	1		/*@ant A or ant Main   or S1*/
+#define	AUX_ANT		2		/*@AntB or ant Aux   or S0*/
+#define	MAX_ANT		3		/* @3 for AP using*/
+
+#define ANT1_2G 0 /* @= ANT2_5G	for 8723D  BTG S1 RX S0S1 diversity for 8723D, TX fixed at S1 */
+#define ANT2_2G 1 /* @= ANT1_5G	for 8723D  BTG S0  RX S0S1 diversity for 8723D, TX fixed at S1 */
+/*smart antenna*/
+#define SUPPORT_RF_PATH_NUM 4
+#define SUPPORT_BEAM_PATTERN_NUM 4
+#define NUM_ANTENNA_8821A	2
+
+#define SUPPORT_BEAM_SET_PATTERN_NUM		16
+
+#define	NO_FIX_TX_ANT		0
+#define	FIX_TX_AT_MAIN	1
+#define	FIX_AUX_AT_MAIN	2
+
+/* @Antenna Diversty Control type */
+#define	ODM_AUTO_ANT		0
+#define	ODM_FIX_MAIN_ANT	1
+#define	ODM_FIX_AUX_ANT	2
+
+#define ODM_N_ANTDIV_SUPPORT		(ODM_RTL8188E | ODM_RTL8192E | ODM_RTL8723B | ODM_RTL8188F | ODM_RTL8723D | ODM_RTL8195A | ODM_RTL8197F)
+#define ODM_AC_ANTDIV_SUPPORT	(ODM_RTL8821 | ODM_RTL8881A | ODM_RTL8812 | ODM_RTL8821C | ODM_RTL8822B | ODM_RTL8814B)
+#define ODM_ANTDIV_SUPPORT		(ODM_N_ANTDIV_SUPPORT | ODM_AC_ANTDIV_SUPPORT)
+#define ODM_SMART_ANT_SUPPORT	(ODM_RTL8188E | ODM_RTL8192E)
+#define ODM_HL_SMART_ANT_TYPE1_SUPPORT		(ODM_RTL8821 | ODM_RTL8822B)
+
+#define ODM_ANTDIV_2G_SUPPORT_IC			(ODM_RTL8188E | ODM_RTL8192E | ODM_RTL8723B | ODM_RTL8881A | ODM_RTL8188F | ODM_RTL8723D | ODM_RTL8197F)
+#define ODM_ANTDIV_5G_SUPPORT_IC			(ODM_RTL8821 | ODM_RTL8881A | ODM_RTL8812 | ODM_RTL8821C | ODM_RTL8822B)
+
+#define ODM_EVM_ENHANCE_ANTDIV_SUPPORT_IC	(ODM_RTL8192E | ODM_RTL8197F | ODM_RTL8822B)
+
+#define ODM_ANTDIV_2G	BIT(0)
+#define ODM_ANTDIV_5G	BIT(1)
+
+#define ANTDIV_ON	1
+#define ANTDIV_OFF	0
+
+#define ANT_PATH_A	0
+#define ANT_PATH_B	1
+#define ANT_PATH_AB	2
+
+#define FAT_ON	1
+#define FAT_OFF	0
+
+#define TX_BY_DESC	1
+#define TX_BY_REG	0
+
+#define RSSI_METHOD	0
+#define EVM_METHOD		1
+#define CRC32_METHOD	2
+#define TP_METHOD		3
+
+#define INIT_ANTDIV_TIMMER		0
+#define CANCEL_ANTDIV_TIMMER	1
+#define RELEASE_ANTDIV_TIMMER	2
+
+#define CRC32_FAIL	1
+#define CRC32_OK	0
+
+#define evm_rssi_th_high	25
+#define evm_rssi_th_low	20
+
+#define NORMAL_STATE_MIAN	1
+#define NORMAL_STATE_AUX	2
+#define TRAINING_STATE		3
+
+#define FORCE_RSSI_DIFF 10
+
+#define CSI_ON	1
+#define CSI_OFF	0
+
+#define DIVON_CSIOFF 1
+#define DIVOFF_CSION 2
+
+#define BDC_DIV_TRAIN_STATE	0
+#define bdc_bfer_train_state	1
+#define BDC_DECISION_STATE		2
+#define BDC_BF_HOLD_STATE		3
+#define BDC_DIV_HOLD_STATE		4
+
+#define BDC_MODE_1 1
+#define BDC_MODE_2 2
+#define BDC_MODE_3 3
+#define BDC_MODE_4 4
+#define BDC_MODE_NULL 0xff
+
+/*SW S0S1 antenna diversity*/
+#define SWAW_STEP_INIT			0xff
+#define SWAW_STEP_PEEK		0
+#define SWAW_STEP_DETERMINE	1
+
+#define RSSI_CHECK_RESET_PERIOD	10
+#define RSSI_CHECK_THRESHOLD		50
+
+/*@Hong Lin Smart antenna*/
+#define HL_SMTANT_2WIRE_DATA_LEN 24
+
+#if (RTL8723D_SUPPORT == 1)
+	#ifndef CONFIG_ANTENNA_DIVERSITY_PERIOD
+		#define CONFIG_ANTENNA_DIVERSITY_PERIOD 1
+	#endif
+#endif
+/* @1 ============================================================
+ * 1  structure
+ * 1 ============================================================
+ */
+
+
+struct sw_antenna_switch {
+	u8		double_chk_flag;	/*@If current antenna RSSI > "RSSI_CHECK_THRESHOLD", than check this antenna again*/
+	u8		try_flag;
+	s32		pre_rssi;
+	u8		cur_antenna;
+	u8		pre_antenna;
+	u8		rssi_trying;
+	u8		reset_idx;
+	u8		train_time;
+	u8		train_time_flag; /*@base on RSSI difference between two antennas*/
+	struct phydm_timer_list	phydm_sw_antenna_switch_timer;
+	u32		pkt_cnt_sw_ant_div_by_ctrl_frame;
+	boolean		is_sw_ant_div_by_ctrl_frame;
+
+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
+#if USE_WORKITEM
+	RT_WORK_ITEM	phydm_sw_antenna_switch_workitem;
+#endif
+#endif
+
+	/* @AntDect (Before link Antenna Switch check) need to be moved*/
+	u16		single_ant_counter;
+	u16		dual_ant_counter;
+	u16		aux_fail_detec_counter;
+	u16		retry_counter;
+	u8		swas_no_link_state;
+	u32		swas_no_link_bk_reg948;
+	boolean		ANTA_ON;	/*To indicate ant A is or not*/
+	boolean		ANTB_ON;	/*@To indicate ant B is on or not*/
+	boolean		pre_aux_fail_detec;
+	boolean		rssi_ant_dect_result;
+	u8		ant_5g;
+	u8		ant_2g;
+};
+
+#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
+#if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY))
+struct _BF_DIV_COEX_ {
+	boolean w_bfer_client[ODM_ASSOCIATE_ENTRY_NUM];
+	boolean w_bfee_client[ODM_ASSOCIATE_ENTRY_NUM];
+	u32 MA_rx_TP[ODM_ASSOCIATE_ENTRY_NUM];
+	u32 MA_rx_TP_DIV[ODM_ASSOCIATE_ENTRY_NUM];
+
+	u8 bd_ccoex_type_wbfer;
+	u8 num_txbfee_client;
+	u8 num_txbfer_client;
+	u8 bdc_try_counter;
+	u8 bdc_hold_counter;
+	u8 bdc_mode;
+	u8 bdc_active_mode;
+	u8 BDC_state;
+	u8 bdc_rx_idle_update_counter;
+	u8 num_client;
+	u8 pre_num_client;
+	u8 num_bf_tar;
+	u8 num_div_tar;
+
+	boolean is_all_div_sta_idle;
+	boolean is_all_bf_sta_idle;
+	boolean bdc_try_flag;
+	boolean BF_pass;
+	boolean DIV_pass;
+};
+#endif
+#endif
+
+struct phydm_fat_struct {
+	u8	bssid[6];
+	u8	antsel_rx_keep_0;
+	u8	antsel_rx_keep_1;
+	u8	antsel_rx_keep_2;
+	u8	antsel_rx_keep_3;
+	u32	ant_sum_rssi[7];
+	u32	ant_rssi_cnt[7];
+	u32	ant_ave_rssi[7];
+	u8	fat_state;
+	u8	fat_state_cnt;
+	u32	train_idx;
+	u8	antsel_a[ODM_ASSOCIATE_ENTRY_NUM];
+	u8	antsel_b[ODM_ASSOCIATE_ENTRY_NUM];
+	u8	antsel_c[ODM_ASSOCIATE_ENTRY_NUM];
+	u16	main_ant_sum[ODM_ASSOCIATE_ENTRY_NUM];
+	u16	aux_ant_sum[ODM_ASSOCIATE_ENTRY_NUM];
+	u16	main_ant_cnt[ODM_ASSOCIATE_ENTRY_NUM];
+	u16	aux_ant_cnt[ODM_ASSOCIATE_ENTRY_NUM];
+	u16	main_ant_sum_cck[ODM_ASSOCIATE_ENTRY_NUM];
+	u16	aux_ant_sum_cck[ODM_ASSOCIATE_ENTRY_NUM];
+	u16	main_ant_cnt_cck[ODM_ASSOCIATE_ENTRY_NUM];
+	u16	aux_ant_cnt_cck[ODM_ASSOCIATE_ENTRY_NUM];
+	u8	rx_idle_ant;
+	u8	rx_idle_ant2;
+	u8	rvrt_val;
+	u8	ant_div_on_off;
+	u8	div_path_type;
+	boolean	is_become_linked;
+	u32	min_max_rssi;
+	u8	idx_ant_div_counter_2g;
+	u8	idx_ant_div_counter_5g;
+	u8	ant_div_2g_5g;
+
+#ifdef ODM_EVM_ENHANCE_ANTDIV
+	/*@For 1SS RX phy rate*/
+	u32	main_ant_evm_sum[ODM_ASSOCIATE_ENTRY_NUM];
+	u32	aux_ant_evm_sum[ODM_ASSOCIATE_ENTRY_NUM];
+	u32	main_ant_evm_cnt[ODM_ASSOCIATE_ENTRY_NUM];
+	u32	aux_ant_evm_cnt[ODM_ASSOCIATE_ENTRY_NUM];
+
+	/*@For 2SS RX phy rate*/
+	u32	main_ant_evm_2ss_sum[ODM_ASSOCIATE_ENTRY_NUM][2];	/*@2SS with A1+B*/
+	u32	aux_ant_evm_2ss_sum[ODM_ASSOCIATE_ENTRY_NUM][2];	/*@2SS with A2+B*/
+	u32	main_ant_evm_2ss_cnt[ODM_ASSOCIATE_ENTRY_NUM];
+	u32	aux_ant_evm_2ss_cnt[ODM_ASSOCIATE_ENTRY_NUM];
+
+	boolean	evm_method_enable;
+	u8	target_ant_evm;
+	u8	target_ant_crc32;
+	u8	target_ant_tp;
+	u8	target_ant_enhance;
+	u8	pre_target_ant_enhance;
+	u16	main_mpdu_ok_cnt;
+	u16	aux_mpdu_ok_cnt;
+
+	u32	crc32_ok_cnt;
+	u32	crc32_fail_cnt;
+	u32	main_crc32_ok_cnt;
+	u32	aux_crc32_ok_cnt;
+	u32	main_crc32_fail_cnt;
+	u32	aux_crc32_fail_cnt;
+
+	u32	antdiv_tp_main;
+	u32	antdiv_tp_aux;
+	u32	antdiv_tp_main_cnt;
+	u32	antdiv_tp_aux_cnt;
+
+	u8	pre_antdiv_rssi;
+	u8	pre_antdiv_tp;
+#endif
+#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
+	u32    cck_ctrl_frame_cnt_main;
+	u32    cck_ctrl_frame_cnt_aux;
+	u32    ofdm_ctrl_frame_cnt_main;
+	u32    ofdm_ctrl_frame_cnt_aux;
+	u32	main_ant_ctrl_frame_sum;
+	u32	aux_ant_ctrl_frame_sum;
+	u32	main_ant_ctrl_frame_cnt;
+	u32	aux_ant_ctrl_frame_cnt;
+#endif
+	u8	b_fix_tx_ant;
+	boolean	fix_ant_bfee;
+	boolean	enable_ctrl_frame_antdiv;
+	boolean	use_ctrl_frame_antdiv;
+	boolean	*is_no_csi_feedback;
+	boolean	force_antdiv_type;
+	u8	antdiv_type_dbg;
+	u8	hw_antsw_occur;
+	u8	*p_force_tx_ant_by_desc;
+	u8	force_tx_ant_by_desc; /*@A temp value, will hook to driver team's outer parameter later*/
+	u8	*p_default_s0_s1;
+	u8	default_s0_s1;
+};
+
+/* @1 ============================================================
+ * 1  enumeration
+ * 1 ============================================================
+ */
+
+enum fat_state /*@Fast antenna training*/
+{
+	FAT_BEFORE_LINK_STATE	= 0,
+	FAT_PREPARE_STATE			= 1,
+	FAT_TRAINING_STATE		= 2,
+	FAT_DECISION_STATE		= 3
+};
+
+enum ant_div_type {
+	NO_ANTDIV			= 0xFF,
+	CG_TRX_HW_ANTDIV			= 0x01,
+	CGCS_RX_HW_ANTDIV		= 0x02,
+	FIXED_HW_ANTDIV		= 0x03,
+	CG_TRX_SMART_ANTDIV	= 0x04,
+	CGCS_RX_SW_ANTDIV	= 0x05,
+	S0S1_SW_ANTDIV	= 0x06, /*@8723B intrnal switch S0 S1*/
+	S0S1_TRX_HW_ANTDIV	= 0x07, /*TRX S0S1 diversity for 8723D*/
+	HL_SW_SMART_ANT_TYPE1	= 0x10, /*@Hong-Lin Smart antenna use for 8821AE which is a 2 ant. entitys, and each ant. is equipped with 4 antenna patterns*/
+	HL_SW_SMART_ANT_TYPE2	= 0x11 /*@Hong-Bo Smart antenna use for 8822B which is a 2 ant. entitys*/
+};
+
+/* @1 ============================================================
+ * 1  function prototype
+ * 1 ============================================================
+ */
+
+void odm_stop_antenna_switch_dm(void *dm_void);
+
+void phydm_enable_antenna_diversity(void *dm_void);
+
+void odm_set_ant_config(void *dm_void, u8 ant_setting /* @0=A, 1=B, 2=C, .... */
+			);
+
+#define sw_ant_div_rest_after_link odm_sw_ant_div_rest_after_link
+
+void odm_sw_ant_div_rest_after_link(void *dm_void);
+
+void odm_ant_div_on_off(void *dm_void, u8 swch, u8 path);
+
+void odm_tx_by_tx_desc_or_reg(void *dm_void, u8 swch);
+
+#if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY))
+
+void phydm_antdiv_reset_statistic(
+	void *dm_void,
+	u32 macid);
+
+void odm_update_rx_idle_ant(
+	void *dm_void,
+	u8 ant);
+
+void phydm_update_rx_idle_ant_pathb(void *dm_void, u8 ant);
+
+void phydm_set_antdiv_val(
+	void *dm_void,
+	u32 *val_buf,
+	u8 val_len);
+
+#if (RTL8723B_SUPPORT == 1)
+void odm_update_rx_idle_ant_8723b(
+	void *dm_void,
+	u8 ant,
+	u32 default_ant,
+	u32 optional_ant);
+#endif
+
+#if (RTL8188F_SUPPORT == 1)
+void phydm_update_rx_idle_antenna_8188F(
+	void *dm_void,
+	u32 default_ant);
+#endif
+
+#if (RTL8723D_SUPPORT == 1)
+
+void phydm_set_tx_ant_pwr_8723d(
+	void *dm_void,
+	u8 ant);
+
+void odm_update_rx_idle_ant_8723d(
+	void *dm_void,
+	u8 ant,
+	u32 default_ant,
+	u32 optional_ant);
+
+#endif
+
+#ifdef CONFIG_S0S1_SW_ANTENNA_DIVERSITY
+
+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
+void odm_sw_antdiv_callback(
+	struct phydm_timer_list *timer);
+
+void odm_sw_antdiv_workitem_callback(
+	void *context);
+
+#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
+
+void odm_sw_antdiv_workitem_callback(
+	void *context);
+
+void odm_sw_antdiv_callback(
+	void *function_context);
+
+#endif
+
+void odm_s0s1_sw_ant_div_by_ctrl_frame(
+	void *dm_void,
+	u8 step);
+
+void odm_antsel_statistics_of_ctrl_frame(
+	void *dm_void,
+	u8 antsel_tr_mux,
+	u32 rx_pwdb_all);
+
+void odm_s0s1_sw_ant_div_by_ctrl_frame_process_rssi(
+	void *dm_void,
+	void *phy_info_void,
+	void *pkt_info_void);
+
+#endif
+
+#ifdef ODM_EVM_ENHANCE_ANTDIV
+void phydm_evm_sw_antdiv_init(
+	void *dm_void);
+
+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
+void phydm_evm_antdiv_callback(
+	struct phydm_timer_list *timer);
+
+void phydm_evm_antdiv_workitem_callback(
+	void *context);
+
+#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
+void phydm_evm_antdiv_callback(
+	void *dm_void);
+
+void phydm_evm_antdiv_workitem_callback(
+	void *context);
+
+#else
+void phydm_evm_antdiv_callback(
+	void *dm_void);
+#endif
+
+#endif
+
+void odm_hw_ant_div(
+	void *dm_void);
+
+#if (defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY)) || (defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY))
+void odm_fast_ant_training(
+	void *dm_void);
+
+void odm_fast_ant_training_callback(
+	void *dm_void);
+
+void odm_fast_ant_training_work_item_callback(
+	void *dm_void);
+#endif
+
+void odm_ant_div_init(
+	void *dm_void);
+
+void odm_ant_div(
+	void *dm_void);
+
+void odm_antsel_statistics(
+	void *dm_void,
+	void *phy_info_void,
+	u8 antsel_tr_mux,
+	u32 mac_id,
+	u32 utility,
+	u8 method,
+	u8 is_cck_rate);
+
+void odm_process_rssi_for_ant_div(
+	void *dm_void,
+	void *phy_info_void,
+	void *pkt_info_void);
+
+#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
+void odm_set_tx_ant_by_tx_info(
+	void *dm_void,
+	u8 *desc,
+	u8 mac_id);
+
+#elif (DM_ODM_SUPPORT_TYPE == ODM_AP)
+
+struct tx_desc; /*@declared tx_desc here or compile error happened when enabled 8822B*/
+
+void odm_set_tx_ant_by_tx_info(
+	struct rtl8192cd_priv *priv,
+	struct tx_desc *pdesc,
+	unsigned short aid);
+
+#if 1 /*@def def CONFIG_WLAN_HAL*/
+void odm_set_tx_ant_by_tx_info_hal(
+	struct rtl8192cd_priv *priv,
+	void *pdesc_data,
+	u16 aid);
+#endif /*@#ifdef CONFIG_WLAN_HAL*/
+#endif
+
+void odm_ant_div_config(
+	void *dm_void);
+
+void odm_ant_div_timers(
+	void *dm_void,
+	u8 state);
+
+void phydm_antdiv_debug(void *dm_void, char input[][16], u32 *_used,
+			char *output, u32 *_out_len);
+
+void odm_ant_div_reset(void *dm_void);
+
+void odm_antenna_diversity_init(void *dm_void);
+
+void odm_antenna_diversity(void *dm_void);
+#endif /*@#ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY*/
+#endif /*@#ifndef	__ODMANTDIV_H__*/
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/phydm_api.c linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/phydm_api.c
--- linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/phydm_api.c	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/phydm_api.c	2020-04-10 16:35:06.823660394 +0300
@@ -0,0 +1,2410 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017  Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * The full GNU General Public License is included in this distribution in the
+ * file called LICENSE.
+ *
+ * Contact Information:
+ * wlanfae <wlanfae@realtek.com>
+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
+ * Hsinchu 300, Taiwan.
+ *
+ * Larry Finger <Larry.Finger@lwfinger.net>
+ *
+ *****************************************************************************/
+
+/*@************************************************************
+ * include files
+ * ************************************************************
+ */
+
+#include "mp_precomp.h"
+#include "phydm_precomp.h"
+
+#if (ODM_IC_11AC_SERIES_SUPPORT)
+void phydm_reset_bb_hw_cnt_ac(void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+
+	/*@ Reset all counter when 1 (including PMAC and PHY)*/
+	/* Reset Page F counter*/
+	odm_set_bb_reg(dm, R_0xb58, BIT(0), 1);
+	odm_set_bb_reg(dm, R_0xb58, BIT(0), 0);
+}
+#endif
+
+void phydm_dynamic_ant_weighting(void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+
+#ifdef DYN_ANT_WEIGHTING_SUPPORT
+	#if (RTL8197F_SUPPORT)
+	if (dm->support_ic_type & (ODM_RTL8197F))
+		phydm_dynamic_ant_weighting_8197f(dm);
+	#endif
+
+	#if (RTL8812A_SUPPORT)
+	if (dm->support_ic_type & (ODM_RTL8812)) {
+		phydm_dynamic_ant_weighting_8812a(dm);
+	}
+	#endif
+
+	#if (RTL8822B_SUPPORT)
+	if (dm->support_ic_type & (ODM_RTL8822B))
+		phydm_dynamic_ant_weighting_8822b(dm);
+	#endif
+#endif
+}
+
+#ifdef DYN_ANT_WEIGHTING_SUPPORT
+void phydm_ant_weight_dbg(void *dm_void, char input[][16], u32 *_used,
+			  char *output, u32 *_out_len)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	char help[] = "-h";
+	u32 var1[10] = {0};
+	u32 used = *_used;
+	u32 out_len = *_out_len;
+
+	if ((strcmp(input[1], help) == 0)) {
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "echo dis_dym_ant_weighting {0/1}\n");
+
+	} else {
+		PHYDM_SSCANF(input[1], DCMD_DECIMAL, &var1[0]);
+
+		if (var1[0] == 1) {
+			dm->is_disable_dym_ant_weighting = 1;
+			PDM_SNPF(out_len, used, output + used, out_len - used,
+				 "Disable dyn-ant-weighting\n");
+		} else {
+			dm->is_disable_dym_ant_weighting = 0;
+			PDM_SNPF(out_len, used, output + used, out_len - used,
+				 "Enable dyn-ant-weighting\n");
+		}
+	}
+	*_used = used;
+	*_out_len = out_len;
+}
+#endif
+
+void phydm_iq_gen_en(void *dm_void)
+{
+#ifdef PHYDM_COMPILE_IC_2SS
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	u8 i = 0;
+	enum rf_path path = RF_PATH_A;
+
+	#if (ODM_IC_11AC_SERIES_SUPPORT)
+	if (!(dm->support_ic_type & ODM_IC_11AC_SERIES))
+		return;
+
+	for (i = RF_PATH_A; i <= RF_PATH_B; i++) {
+		path = (enum rf_path)i;
+
+		/*RF mode table write enable*/
+		odm_set_rf_reg(dm, path, RF_0xef, BIT(19), 0x1);
+		/*Select RX mode*/
+		odm_set_rf_reg(dm, path, RF_0x33, 0xF, 3);
+		/*Set Table data*/
+		odm_set_rf_reg(dm, path, RF_0x3e, 0xfffff, 0x00036);
+		/*Set Table data*/
+		odm_set_rf_reg(dm, path, RF_0x3f, 0xfffff, 0x5AFCE);
+		/*RF mode table write disable*/
+		odm_set_rf_reg(dm, path, RF_0xef, BIT(19), 0x0);
+	}
+	#endif
+	#if (ODM_IC_11N_SERIES_SUPPORT)
+	if (!(dm->support_ic_type & ODM_IC_11N_SERIES))
+		return;
+	if (dm->support_ic_type & ODM_RTL8192F) {
+		 /*RF mode table write enable*/
+		odm_set_rf_reg(dm, RF_PATH_A, RF_0xef, 0x80000, 0x1);
+		odm_set_rf_reg(dm, RF_PATH_B, RF_0xef, 0x80000, 0x1);
+		/* Path A */
+		odm_set_rf_reg(dm, RF_PATH_A, RF_0x30, 0xfffff, 0x08000);
+		odm_set_rf_reg(dm, RF_PATH_A, RF_0x31, 0xfffff, 0x0005f);
+		odm_set_rf_reg(dm, RF_PATH_A, RF_0x32, 0xfffff, 0x01042);
+		odm_set_rf_reg(dm, RF_PATH_A, RF_0x30, 0xfffff, 0x18000);
+		odm_set_rf_reg(dm, RF_PATH_A, RF_0x31, 0xfffff, 0x0004f);
+		odm_set_rf_reg(dm, RF_PATH_A, RF_0x32, 0xfffff, 0x71fc2);
+		/* Path B */
+		odm_set_rf_reg(dm, RF_PATH_B, RF_0x30, 0xfffff, 0x08000);
+		odm_set_rf_reg(dm, RF_PATH_B, RF_0x31, 0xfffff, 0x00050);
+		odm_set_rf_reg(dm, RF_PATH_B, RF_0x32, 0xfffff, 0x01042);
+		odm_set_rf_reg(dm, RF_PATH_B, RF_0x30, 0xfffff, 0x18000);
+		odm_set_rf_reg(dm, RF_PATH_B, RF_0x31, 0xfffff, 0x00040);
+		odm_set_rf_reg(dm, RF_PATH_B, RF_0x32, 0xfffff, 0x71fc2);
+		/*RF mode table write disable*/
+		odm_set_rf_reg(dm, RF_PATH_A, RF_0xef, 0x80000, 0x0);
+		odm_set_rf_reg(dm, RF_PATH_B, RF_0xef, 0x80000, 0x0);
+	}
+	#endif
+#endif
+}
+
+void phydm_dis_cdd(void *dm_void)
+{
+#ifdef PHYDM_COMPILE_IC_2SS
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+
+	#if (ODM_IC_11AC_SERIES_SUPPORT)
+	if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
+		odm_set_bb_reg(dm, R_0x808, 0x3ffff00, 0);
+		odm_set_bb_reg(dm, R_0x9ac, 0x1fff, 0);
+		odm_set_bb_reg(dm, R_0x9ac, BIT(13), 1);
+	}
+	#endif
+	#if (ODM_IC_11N_SERIES_SUPPORT)
+	if (dm->support_ic_type & ODM_IC_11N_SERIES) {
+		odm_set_bb_reg(dm, R_0x90c, 0xffffffff, 0x83321333);
+		/* Set Tx delay setting for CCK pathA,B*/
+		odm_set_bb_reg(dm, R_0xa2c, 0xf0000000, 0);
+		//Enable Tx CDD for HT-portion when spatial expansion is applied
+		odm_set_bb_reg(dm, R_0xd00, BIT(8), 0);
+		/* Tx CDD for Legacy*/
+		odm_set_bb_reg(dm, R_0xd04, 0xf0000, 0);
+		/* Tx CDD for non-HT*/
+		odm_set_bb_reg(dm, R_0xd0c, 0x3c0, 0);
+		/* Tx CDD for HT SS1*/
+		odm_set_bb_reg(dm, R_0xd0c, 0xf8000, 0);
+	}
+	#endif
+#endif
+}
+
+void phydm_pathb_q_matrix_rotate_en(void *dm_void)
+{
+#ifdef PHYDM_COMPILE_IC_2SS
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+
+	#if (ODM_IC_11AC_SERIES_SUPPORT)
+	if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
+		phydm_iq_gen_en(dm);
+
+		#ifdef PHYDM_COMMON_API_SUPPORT
+		if (!phydm_api_trx_mode(dm, BB_PATH_AB, BB_PATH_AB, true))
+			return;
+		#endif
+
+		phydm_dis_cdd(dm);
+		/*Set Q matrix r_v11 =1*/
+		odm_set_bb_reg(dm, R_0x195c, MASKDWORD, 0x40000);
+		phydm_pathb_q_matrix_rotate(dm, 0);
+		/*Set Q matrix enable*/
+		odm_set_bb_reg(dm, R_0x191c, BIT(7), 1);
+	}
+	#endif
+	#if (ODM_IC_11N_SERIES_SUPPORT)
+	if (dm->support_ic_type & ODM_IC_11N_SERIES) {
+		phydm_iq_gen_en(dm);
+
+		#ifdef PHYDM_COMMON_API_SUPPORT
+		if (!phydm_api_trx_mode(dm, BB_PATH_AB, BB_PATH_AB, true))
+			return;
+		#endif
+		phydm_dis_cdd(dm);
+		phydm_pathb_q_matrix_rotate(dm, 0);
+	}
+	#endif
+#endif
+}
+
+void phydm_pathb_q_matrix_rotate(void *dm_void, u16 idx)
+{
+#ifdef PHYDM_COMPILE_IC_2SS
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	#if (ODM_IC_11AC_SERIES_SUPPORT)
+	u32 phase_table_0[12] = {0x40000, 0x376CF, 0x20000, 0x00000,
+				 0xFE0000, 0xFC8930, 0xFC0000, 0xFC8930,
+				 0xFDFFFF, 0x000000, 0x020000, 0x0376CF};
+	u32 phase_table_1[12] = {0x00000, 0x1FFFF, 0x376CF, 0x40000,
+				 0x0376CF, 0x01FFFF, 0x000000, 0xFDFFFF,
+				 0xFC8930, 0xFC0000, 0xFC8930, 0xFDFFFF};
+	#endif
+	#if (ODM_IC_11N_SERIES_SUPPORT)
+	u32 phase_table_N_0[12] = {0x00, 0x0B, 0x02, 0x00, 0x02, 0x02, 0x04,
+				   0x02, 0x0D, 0x09, 0x04, 0x0B};
+	u32 phase_table_N_1[12] = {0x40000100, 0x377F00DD, 0x201D8880,
+				   0x00000000, 0xE01D8B80, 0xC8BF0322,
+				   0xC000FF00, 0xC8BF0322, 0xDFE2777F,
+				   0xFFC003FF, 0x20227480, 0x377F00DD};
+	u32 phase_table_N_2[12] = {0x00, 0x1E, 0x3C, 0x4C, 0x3C, 0x1E, 0x0F,
+				   0xD2, 0xC3, 0xC4, 0xC3, 0xD2};
+	#endif
+	if (idx >= 12) {
+		PHYDM_DBG(dm, ODM_COMP_API, "Phase Set Error: %d\n", idx);
+		return;
+	}
+
+	#if (ODM_IC_11AC_SERIES_SUPPORT)
+	if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
+		/*Set Q matrix r_v21*/
+		odm_set_bb_reg(dm, R_0x1954, 0xffffff, phase_table_0[idx]);
+		odm_set_bb_reg(dm, R_0x1950, 0xffffff, phase_table_1[idx]);
+	}
+	#endif
+	#if (ODM_IC_11N_SERIES_SUPPORT)
+	if (dm->support_ic_type & ODM_IC_11N_SERIES) {
+		/*Set Q matrix r_v21*/
+		odm_set_bb_reg(dm, R_0xc4c, 0xff000000, phase_table_N_0[idx]);
+		odm_set_bb_reg(dm, R_0xc88, 0xffffffff, phase_table_N_1[idx]);
+		odm_set_bb_reg(dm, R_0xc9c, 0xff000000, phase_table_N_2[idx]);
+	}
+	#endif
+#endif
+}
+
+void phydm_trx_antenna_setting_init(void *dm_void, u8 num_rf_path)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	u8 rx_ant = 0, tx_ant = 0;
+	u8 path_bitmap = 1;
+
+	path_bitmap = (u8)phydm_gen_bitmask(num_rf_path);
+#if 0
+	/*PHYDM_DBG(dm, ODM_COMP_INIT, "path_bitmap=0x%x\n", path_bitmap);*/
+#endif
+
+	dm->tx_ant_status = path_bitmap;
+	dm->rx_ant_status = path_bitmap;
+
+	if (num_rf_path == PDM_1SS)
+		return;
+
+	#if (defined(PHYDM_COMPILE_ABOVE_2SS))
+	if (dm->support_ic_type &
+		   (ODM_RTL8192F | ODM_RTL8192E | ODM_RTL8197F)) {
+		dm->rx_ant_status = (u8)odm_get_bb_reg(dm, R_0xc04, 0x3);
+		dm->tx_ant_status = (u8)odm_get_bb_reg(dm, R_0x90c, 0x3);
+	} else if (dm->support_ic_type & (ODM_RTL8812 | ODM_RTL8814A)) {
+		dm->rx_ant_status = (u8)odm_get_bb_reg(dm, R_0x808, 0xf);
+		dm->tx_ant_status = (u8)odm_get_bb_reg(dm, R_0x80c, 0xf);
+	}
+	#endif
+
+	PHYDM_DBG(dm, ODM_COMP_INIT, "[%s]ant_status{tx,rx}={0x%x, 0x%x}\n",
+		  __func__, dm->tx_ant_status, dm->rx_ant_status);
+}
+
+void phydm_config_ofdm_tx_path(void *dm_void, u32 path)
+{
+#if (RTL8192E_SUPPORT || RTL8812A_SUPPORT)
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	u8 ofdm_tx_path = 0x33;
+
+	if (dm->num_rf_path == PDM_1SS)
+		return;
+
+	switch (dm->support_ic_type) {
+	#if (RTL8192E_SUPPORT)
+	case ODM_RTL8192E:
+		if (path == BB_PATH_A)
+			odm_set_bb_reg(dm, R_0x90c, MASKDWORD, 0x81121111);
+		else if (path == BB_PATH_B)
+			odm_set_bb_reg(dm, R_0x90c, MASKDWORD, 0x82221222);
+		else if (path == BB_PATH_AB)
+			odm_set_bb_reg(dm, R_0x90c, MASKDWORD, 0x83321333);
+
+		break;
+	#endif
+
+	#if (RTL8812A_SUPPORT)
+	case ODM_RTL8812:
+		if (path == BB_PATH_A)
+			ofdm_tx_path = 0x11;
+		else if (path == BB_PATH_B)
+			ofdm_tx_path = 0x22;
+		else if (path == BB_PATH_AB)
+			ofdm_tx_path = 0x33;
+
+		odm_set_bb_reg(dm, R_0x80c, 0xff00, ofdm_tx_path);
+
+		break;
+	#endif
+
+	default:
+		break;
+	}
+#endif
+}
+
+void phydm_config_ofdm_rx_path(void *dm_void, u32 path)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	u8 val = 0;
+
+	if (dm->support_ic_type & (ODM_RTL8192E)) {
+#if (RTL8192E_SUPPORT)
+		if (path == BB_PATH_A)
+			val = 1;
+		else if (path == BB_PATH_B)
+			val = 2;
+		else if (path == BB_PATH_AB)
+			val = 3;
+
+		odm_set_bb_reg(dm, R_0xc04, 0xff, ((val << 4) | val));
+		odm_set_bb_reg(dm, R_0xd04, 0xf, val);
+#endif
+	}
+#if (RTL8812A_SUPPORT || RTL8822B_SUPPORT)
+	else if (dm->support_ic_type & (ODM_RTL8812 | ODM_RTL8822B)) {
+		if (path == BB_PATH_A)
+			val = 1;
+		else if (path == BB_PATH_B)
+			val = 2;
+		else if (path == BB_PATH_AB)
+			val = 3;
+
+		odm_set_bb_reg(dm, R_0x808, MASKBYTE0, ((val << 4) | val));
+	}
+#endif
+}
+
+void phydm_config_cck_rx_antenna_init(void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+
+#if (defined(PHYDM_COMPILE_ABOVE_2SS))
+	if (dm->support_ic_type & ODM_IC_1SS)
+		return;
+
+	/*@CCK 2R CCA parameters*/
+	odm_set_bb_reg(dm, R_0xa00, BIT(15), 0x0); /*@Disable Ant diversity*/
+	odm_set_bb_reg(dm, R_0xa70, BIT(7), 0); /*@Concurrent CCA at LSB & USB*/
+	odm_set_bb_reg(dm, R_0xa74, BIT(8), 0); /*RX path diversity enable*/
+	odm_set_bb_reg(dm, R_0xa14, BIT(7), 0); /*r_en_mrc_antsel*/
+	odm_set_bb_reg(dm, R_0xa20, (BIT(5) | BIT(4)), 1); /*@MBC weighting*/
+
+	if (dm->support_ic_type & (ODM_RTL8192E | ODM_RTL8197F | ODM_RTL8192F))
+		odm_set_bb_reg(dm, R_0xa08, BIT(28), 1); /*r_cck_2nd_sel_eco*/
+	else if (dm->support_ic_type & ODM_RTL8814A)
+		odm_set_bb_reg(dm, R_0xa84, BIT(28), 1); /*@2R CCA only*/
+#endif
+}
+
+void phydm_config_cck_rx_path(void *dm_void, enum bb_path path)
+{
+#if (defined(PHYDM_COMPILE_ABOVE_2SS))
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	u8 path_div_select = 0;
+	u8 cck_path[2] = {0};
+	u8 en_2R_path = 0;
+	u8 en_2R_mrc = 0;
+	u8 i = 0, j = 0;
+	u8 num_enable_path = 0;
+	u8 cck_mrc_max_path = 2;
+
+	if (dm->support_ic_type & ODM_IC_1SS)
+		return;
+
+	for (i = 0; i < 4; i++) {
+		if (path & BIT(i)) { /*@ex: PHYDM_ABCD*/
+			num_enable_path++;
+			cck_path[j] = i;
+			j++;
+		}
+		if (num_enable_path >= cck_mrc_max_path)
+			break;
+	}
+
+	if (num_enable_path > 1) {
+		path_div_select = 1;
+		en_2R_path = 1;
+		en_2R_mrc = 1;
+	} else {
+		path_div_select = 0;
+		en_2R_path = 0;
+		en_2R_mrc = 0;
+	}
+	/*@CCK_1 input signal path*/
+	odm_set_bb_reg(dm, R_0xa04, (BIT(27) | BIT(26)), cck_path[0]);
+	/*@CCK_2 input signal path*/
+	odm_set_bb_reg(dm, R_0xa04, (BIT(25) | BIT(24)), cck_path[1]);
+	/*@enable Rx path diversity*/
+	odm_set_bb_reg(dm, R_0xa74, BIT(8), path_div_select);
+	/*@enable 2R Rx path*/
+	odm_set_bb_reg(dm, R_0xa2c, BIT(18), en_2R_path);
+	/*@enable 2R MRC*/
+	odm_set_bb_reg(dm, R_0xa2c, BIT(22), en_2R_mrc);
+	if (dm->support_ic_type & ODM_RTL8192F) {
+		if (path == BB_PATH_A) {
+			odm_set_bb_reg(dm, R_0xa04, (BIT(27) | BIT(26)), 0);
+			odm_set_bb_reg(dm, R_0xa04, (BIT(25) | BIT(24)), 0);
+			odm_set_bb_reg(dm, R_0xa74, BIT(8), 0);
+			odm_set_bb_reg(dm, R_0xa2c, (BIT(18) | BIT(17)), 0);
+			odm_set_bb_reg(dm, R_0xa2c, (BIT(22) | BIT(21)), 0);
+		} else if (path == BB_PATH_B) {/*@for DC cancellation*/
+			odm_set_bb_reg(dm, R_0xa04, (BIT(27) | BIT(26)), 1);
+			odm_set_bb_reg(dm, R_0xa04, (BIT(25) | BIT(24)), 1);
+			odm_set_bb_reg(dm, R_0xa74, BIT(8), 0);
+			odm_set_bb_reg(dm, R_0xa2c, (BIT(18) | BIT(17)), 0);
+			odm_set_bb_reg(dm, R_0xa2c, (BIT(22) | BIT(21)), 0);
+		} else if (path == BB_PATH_AB) {
+			odm_set_bb_reg(dm, R_0xa04, (BIT(27) | BIT(26)), 0);
+			odm_set_bb_reg(dm, R_0xa04, (BIT(25) | BIT(24)), 1);
+			odm_set_bb_reg(dm, R_0xa74, BIT(8), 1);
+			odm_set_bb_reg(dm, R_0xa2c, (BIT(18) | BIT(17)), 1);
+			odm_set_bb_reg(dm, R_0xa2c, (BIT(22) | BIT(21)), 1);
+		}
+	}
+
+#endif
+}
+
+void phydm_config_cck_tx_path(void *dm_void, enum bb_path path)
+{
+#if (defined(PHYDM_COMPILE_ABOVE_2SS))
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+
+	if (path == BB_PATH_A)
+		odm_set_bb_reg(dm, R_0xa04, 0xf0000000, 0x8);
+	else if (path == BB_PATH_B)
+		odm_set_bb_reg(dm, R_0xa04, 0xf0000000, 0x4);
+	else if (path == BB_PATH_AB)
+		odm_set_bb_reg(dm, R_0xa04, 0xf0000000, 0xc);
+#endif
+}
+
+void phydm_config_trx_path_v2(void *dm_void, char input[][16], u32 *_used,
+			      char *output, u32 *_out_len)
+{
+#if (RTL8822B_SUPPORT || RTL8197F_SUPPORT || RTL8192F_SUPPORT)
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	u32 used = *_used;
+	u32 out_len = *_out_len;
+	u32 val[10] = {0};
+	char help[] = "-h";
+	u8 i = 0, input_idx = 0;
+	enum bb_path tx_path, rx_path;
+	boolean dbg_mode_en, tx2_path_en;
+
+	if (!(dm->support_ic_type &
+	    (ODM_RTL8822B | ODM_RTL8197F | ODM_RTL8192F)))
+		return;
+
+	for (i = 0; i < 5; i++) {
+		if (input[i + 1]) {
+			PHYDM_SSCANF(input[i + 1], DCMD_HEX, &val[i]);
+			input_idx++;
+		}
+	}
+
+	if (input_idx == 0)
+		return;
+
+	dbg_mode_en = (boolean)val[0];
+	tx_path = (enum bb_path)val[1];
+	rx_path = (enum bb_path)val[2];
+	tx2_path_en = (boolean)val[3];
+
+	if ((strcmp(input[1], help) == 0)) {
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "{en} {tx_path} {rx_path} {1ss_tx_2_path_en}\n");
+
+	} else if (dbg_mode_en) {
+		dm->is_disable_phy_api = false;
+		phydm_api_trx_mode(dm, tx_path, rx_path, tx2_path_en);
+		dm->is_disable_phy_api = true;
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "tx_path = 0x%x, rx_path = 0x%x, tx2_path_en = %d\n",
+			 tx_path, rx_path, tx2_path_en);
+	} else {
+		dm->is_disable_phy_api = false;
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "Disable API debug mode\n");
+	}
+#endif
+}
+
+void phydm_config_trx_path_v1(void *dm_void, char input[][16], u32 *_used,
+			      char *output, u32 *_out_len)
+{
+#if (RTL8192E_SUPPORT || RTL8812A_SUPPORT)
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	u32 used = *_used;
+	u32 out_len = *_out_len;
+	u32 val[10] = {0};
+	char help[] = "-h";
+	u8 i = 0, input_idx = 0;
+
+	if (!(dm->support_ic_type & (ODM_RTL8192E | ODM_RTL8812)))
+		return;
+
+	for (i = 0; i < 5; i++) {
+		if (input[i + 1]) {
+			PHYDM_SSCANF(input[i + 1], DCMD_HEX, &val[i]);
+			input_idx++;
+		}
+	}
+
+	if (input_idx == 0)
+		return;
+
+	if ((strcmp(input[1], help) == 0)) {
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "{0:CCK, 1:OFDM} {1:TX, 2:RX} {1:path_A, 2:path_B, 3:path_AB}\n");
+
+		*_used = used;
+		*_out_len = out_len;
+		return;
+
+	} else if (val[0] == 0) {
+	/* @CCK */
+		if (val[1] == 1) { /*TX*/
+			if (val[2] == 1)
+				phydm_config_cck_tx_path(dm, BB_PATH_A);
+			else if (val[2] == 2)
+				phydm_config_cck_tx_path(dm, BB_PATH_B);
+			else if (val[2] == 3)
+				phydm_config_cck_tx_path(dm, BB_PATH_AB);
+		} else if (val[1] == 2) { /*RX*/
+
+			phydm_config_cck_rx_antenna_init(dm);
+
+			if (val[2] == 1)
+				phydm_config_cck_rx_path(dm, BB_PATH_A);
+			else if (val[2] == 2)
+				phydm_config_cck_rx_path(dm, BB_PATH_B);
+			else if (val[2] == 3)
+				phydm_config_cck_rx_path(dm, BB_PATH_AB);
+			}
+		}
+	/* OFDM */
+	else if (val[0] == 1) {
+		if (val[1] == 1) /*TX*/
+			phydm_config_ofdm_tx_path(dm, val[2]);
+		else if (val[1] == 2) /*RX*/
+			phydm_config_ofdm_rx_path(dm, val[2]);
+	}
+
+	PDM_SNPF(out_len, used, output + used, out_len - used,
+		 "PHYDM Set path [%s] [%s] = [%s%s%s%s]\n",
+		 (val[0] == 1) ? "OFDM" : "CCK",
+		 (val[1] == 1) ? "TX" : "RX",
+		 (val[2] & 0x1) ? "A" : "", (val[2] & 0x2) ? "B" : "",
+		 (val[2] & 0x4) ? "C" : "",
+		 (val[2] & 0x8) ? "D" : "");
+
+	*_used = used;
+	*_out_len = out_len;
+#endif
+}
+
+void phydm_config_trx_path(void *dm_void, char input[][16], u32 *_used,
+			   char *output, u32 *_out_len)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+
+	if (dm->support_ic_type & (ODM_RTL8192E | ODM_RTL8812)) {
+		#if (RTL8192E_SUPPORT || RTL8812A_SUPPORT)
+		phydm_config_trx_path_v1(dm, input, _used, output, _out_len);
+		#endif
+	} else if (dm->support_ic_type &
+		   (ODM_RTL8822B | ODM_RTL8197F | ODM_RTL8192F)) {
+		#if (RTL8822B_SUPPORT || RTL8197F_SUPPORT || RTL8192F_SUPPORT)
+		phydm_config_trx_path_v2(dm, input, _used, output, _out_len);
+		#endif
+	}
+}
+
+void phydm_tx_2path(void *dm_void)
+{
+#if (defined(PHYDM_COMPILE_IC_2SS))
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	enum bb_path rx_path = (enum bb_path)dm->rx_ant_status;
+
+	PHYDM_DBG(dm, ODM_COMP_API, "%s ======>\n", __func__);
+
+
+	if (!(dm->support_ic_type & ODM_IC_2SS))
+		return;
+
+	#if (RTL8822B_SUPPORT || RTL8192F_SUPPORT || RTL8197F_SUPPORT)
+	if (dm->support_ic_type & (ODM_RTL8822B | ODM_RTL8197F | ODM_RTL8192F))
+		phydm_api_trx_mode(dm, BB_PATH_AB, rx_path, true);
+	#endif
+
+	#if (RTL8812A_SUPPORT || RTL8192E_SUPPORT)
+	if (dm->support_ic_type & (ODM_RTL8812 | ODM_RTL8192E)) {
+		phydm_config_cck_tx_path(dm, BB_PATH_AB);
+		phydm_config_ofdm_tx_path(dm, BB_PATH_AB);
+	}
+	#endif
+#endif
+}
+
+void phydm_stop_3_wire(void *dm_void, u8 set_type)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+
+	if (set_type == PHYDM_SET) {
+		/*@[Stop 3-wires]*/
+		if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
+			odm_set_bb_reg(dm, R_0xc00, 0xf, 0x4);
+			odm_set_bb_reg(dm, R_0xe00, 0xf, 0x4);
+		} else {
+			odm_set_bb_reg(dm, R_0x88c, 0xf00000, 0xf);
+		}
+
+	} else { /*@if (set_type == PHYDM_REVERT)*/
+
+		/*@[Start 3-wires]*/
+		if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
+			odm_set_bb_reg(dm, R_0xc00, 0xf, 0x7);
+			odm_set_bb_reg(dm, R_0xe00, 0xf, 0x7);
+		} else {
+			odm_set_bb_reg(dm, R_0x88c, 0xf00000, 0x0);
+		}
+	}
+}
+
+u8 phydm_stop_ic_trx(void *dm_void, u8 set_type)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct phydm_api_stuc *api = &dm->api_table;
+	u32 i;
+	u8 trx_idle_success = false;
+	u32 dbg_port_value = 0;
+
+	if (set_type == PHYDM_SET) {
+	/*@[Stop TRX]---------------------------------------------------------*/
+		/*set debug port to 0x0*/
+		if (!phydm_set_bb_dbg_port(dm, DBGPORT_PRI_3, 0x0))
+			return PHYDM_SET_FAIL;
+
+		for (i = 0; i < 10000; i++) {
+			dbg_port_value = phydm_get_bb_dbg_port_val(dm);
+			/* PHYTXON && CCA_all */
+			if ((dbg_port_value & (BIT(17) | BIT(3))) == 0) {
+				PHYDM_DBG(dm, ODM_COMP_API,
+					  "Stop trx wait for (%d) times\n", i);
+
+				trx_idle_success = true;
+				break;
+			}
+		}
+		phydm_release_bb_dbg_port(dm);
+
+		if (trx_idle_success) {
+			api->tx_queue_bitmap = odm_read_1byte(dm, R_0x522);
+
+			/*pause all TX queue*/
+			odm_set_bb_reg(dm, R_0x520, 0xff0000, 0xff);
+
+			if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
+				/*@disable CCK block*/
+				odm_set_bb_reg(dm, R_0x808, BIT(28), 0);
+				/*@disable OFDM RX CCA*/
+				odm_set_bb_reg(dm, R_0x838, BIT(1), 1);
+			} else {
+				/* @disable whole CCK block */
+				odm_set_bb_reg(dm, R_0x800, BIT(24), 0);
+
+				api->rxiqc_reg1 = odm_read_4byte(dm, R_0xc14);
+				api->rxiqc_reg2 = odm_read_4byte(dm, R_0xc1c);
+				/* @[ Set IQK Matrix = 0 ]
+				 * equivalent to [ Turn off CCA]
+				 */
+				odm_set_bb_reg(dm, R_0xc14, MASKDWORD, 0x0);
+				odm_set_bb_reg(dm, R_0xc1c, MASKDWORD, 0x0);
+			}
+
+		} else {
+			return PHYDM_SET_FAIL;
+		}
+
+		return PHYDM_SET_SUCCESS;
+
+	} else { /*@if (set_type == PHYDM_REVERT)*/
+		/*Release all TX queue*/
+		odm_write_1byte(dm, R_0x522, api->tx_queue_bitmap);
+
+		if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
+			/*@enable CCK block*/
+			odm_set_bb_reg(dm, R_0x808, BIT(28), 1);
+			/*@enable OFDM RX CCA*/
+			odm_set_bb_reg(dm, R_0x838, BIT(1), 0);
+		} else {
+			/* @enable whole CCK block */
+			odm_set_bb_reg(dm, R_0x800, BIT(24), 1);
+			/* @[Set IQK Matrix = 0] equivalent to [ Turn off CCA]*/
+			odm_write_4byte(dm, R_0xc14, api->rxiqc_reg1);
+			odm_write_4byte(dm, R_0xc1c, api->rxiqc_reg2);
+		}
+
+		return PHYDM_SET_SUCCESS;
+	}
+}
+
+void phydm_set_ext_switch(void *dm_void, u32 ext_ant_switch)
+{
+#if (RTL8821A_SUPPORT || RTL8881A_SUPPORT)
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+
+	if (!(dm->support_ic_type & (ODM_RTL8821 | ODM_RTL8881A)))
+		return;
+
+	/*Output Pin Settings*/
+
+	/*select DPDT_P and DPDT_N as output pin*/
+	odm_set_mac_reg(dm, R_0x4c, BIT(23), 0);
+
+	/*@by WLAN control*/
+	odm_set_mac_reg(dm, R_0x4c, BIT(24), 1);
+
+	/*@DPDT_N = 1b'0*/ /*@DPDT_P = 1b'0*/
+	odm_set_bb_reg(dm, R_0xcb4, 0xFF, 77);
+
+	if (ext_ant_switch == 1) { /*@2b'01*/
+		odm_set_bb_reg(dm, R_0xcb4, (BIT(29) | BIT(28)), 1);
+		PHYDM_DBG(dm, ODM_COMP_API, "8821A ant swh=2b'01\n");
+	} else if (ext_ant_switch == 2) { /*@2b'10*/
+		odm_set_bb_reg(dm, R_0xcb4, BIT(29) | BIT(28), 2);
+		PHYDM_DBG(dm, ODM_COMP_API, "*8821A ant swh=2b'10\n");
+	}
+#endif
+}
+
+void phydm_csi_mask_enable(void *dm_void, u32 enable)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	boolean en = false;
+
+	en = (enable == FUNC_ENABLE) ? true : false;
+
+	if (dm->support_ic_type & ODM_IC_11N_SERIES) {
+		odm_set_bb_reg(dm, R_0xd2c, BIT(28), en);
+		PHYDM_DBG(dm, ODM_COMP_API,
+			  "Enable CSI Mask:  Reg 0xD2C[28] = ((0x%x))\n", en);
+	#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
+	} else if (dm->support_ic_type & ODM_IC_JGR3_SERIES) {
+		if (en)
+			odm_set_bb_reg(dm, R_0x1ee8, 0x3, 0x3);
+
+		odm_set_bb_reg(dm, R_0xc0c, BIT(3), en);
+	#endif
+	} else if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
+		odm_set_bb_reg(dm, R_0x874, BIT(0), en);
+		PHYDM_DBG(dm, ODM_COMP_API,
+			  "Enable CSI Mask:  Reg 0x874[0] = ((0x%x))\n", en);
+	}
+}
+
+void phydm_clean_all_csi_mask(void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+
+	if (dm->support_ic_type & ODM_IC_11N_SERIES) {
+		odm_set_bb_reg(dm, R_0xd40, MASKDWORD, 0);
+		odm_set_bb_reg(dm, R_0xd44, MASKDWORD, 0);
+		odm_set_bb_reg(dm, R_0xd48, MASKDWORD, 0);
+		odm_set_bb_reg(dm, R_0xd4c, MASKDWORD, 0);
+	#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
+	} else if (dm->support_ic_type & ODM_IC_JGR3_SERIES) {
+		u8 i = 0, idx_lmt = 0;
+
+		if (dm->support_ic_type & ODM_RTL8822C)
+			idx_lmt = 127;
+		else/*@for IC supporting 80 + 80*/
+			idx_lmt = 255;
+
+		odm_set_bb_reg(dm, R_0x1d94, BIT(31) | BIT(30), 0x1);
+		for (i = 0; i < idx_lmt; i++) {
+			odm_set_bb_reg(dm, R_0x1d94, MASKBYTE2, i);
+			odm_set_bb_reg(dm, R_0x1d94, MASKBYTE0, 0x0);
+		}
+		odm_set_bb_reg(dm, R_0x1ee8, 0x3, 0x0);
+	#endif
+	} else if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
+		odm_set_bb_reg(dm, R_0x880, MASKDWORD, 0);
+		odm_set_bb_reg(dm, R_0x884, MASKDWORD, 0);
+		odm_set_bb_reg(dm, R_0x888, MASKDWORD, 0);
+		odm_set_bb_reg(dm, R_0x88c, MASKDWORD, 0);
+		odm_set_bb_reg(dm, R_0x890, MASKDWORD, 0);
+		odm_set_bb_reg(dm, R_0x894, MASKDWORD, 0);
+		odm_set_bb_reg(dm, R_0x898, MASKDWORD, 0);
+		odm_set_bb_reg(dm, R_0x89c, MASKDWORD, 0);
+	}
+}
+
+void phydm_set_csi_mask(void *dm_void, u32 tone_idx_tmp, u8 tone_direction)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	u8 byte_offset = 0, bit_offset = 0;
+	u32 target_reg = 0;
+	u8 reg_tmp_value = 0;
+	u32 tone_num = 64;
+	u32 tone_num_shift = 0;
+	u32 csi_mask_reg_p = 0, csi_mask_reg_n = 0;
+
+	/* @calculate real tone idx*/
+	if ((tone_idx_tmp % 10) >= 5)
+		tone_idx_tmp += 10;
+
+	tone_idx_tmp = (tone_idx_tmp / 10);
+
+	if (dm->support_ic_type & ODM_IC_11N_SERIES) {
+		tone_num = 64;
+		csi_mask_reg_p = 0xD40;
+		csi_mask_reg_n = 0xD48;
+
+	} else if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
+		tone_num = 128;
+		csi_mask_reg_p = 0x880;
+		csi_mask_reg_n = 0x890;
+	}
+
+	if (tone_direction == FREQ_POSITIVE) {
+		if (tone_idx_tmp >= (tone_num - 1))
+			tone_idx_tmp = (tone_num - 1);
+
+		byte_offset = (u8)(tone_idx_tmp >> 3);
+		bit_offset = (u8)(tone_idx_tmp & 0x7);
+		target_reg = csi_mask_reg_p + byte_offset;
+
+	} else {
+		tone_num_shift = tone_num;
+
+		if (tone_idx_tmp >= tone_num)
+			tone_idx_tmp = tone_num;
+
+		tone_idx_tmp = tone_num - tone_idx_tmp;
+
+		byte_offset = (u8)(tone_idx_tmp >> 3);
+		bit_offset = (u8)(tone_idx_tmp & 0x7);
+		target_reg = csi_mask_reg_n + byte_offset;
+	}
+
+	reg_tmp_value = odm_read_1byte(dm, target_reg);
+	PHYDM_DBG(dm, ODM_COMP_API,
+		  "Pre Mask tone idx[%d]:  Reg0x%x = ((0x%x))\n",
+		  (tone_idx_tmp + tone_num_shift), target_reg, reg_tmp_value);
+	reg_tmp_value |= BIT(bit_offset);
+	odm_write_1byte(dm, target_reg, reg_tmp_value);
+	PHYDM_DBG(dm, ODM_COMP_API,
+		  "New Mask tone idx[%d]:  Reg0x%x = ((0x%x))\n",
+		  (tone_idx_tmp + tone_num_shift), target_reg, reg_tmp_value);
+}
+
+void phydm_set_nbi_reg(void *dm_void, u32 tone_idx_tmp, u32 bw)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	/*tone_idx X 10*/
+	u32 nbi_128[NBI_128TONE] = {25, 55, 85, 115, 135,
+				    155, 185, 205, 225, 245,
+				    265, 285, 305, 335, 355,
+				    375, 395, 415, 435, 455,
+				    485, 505, 525, 555, 585, 615, 635};
+	/*tone_idx X 10*/
+	u32 nbi_256[NBI_256TONE] = {25, 55, 85, 115, 135,
+				    155, 175, 195, 225, 245,
+				    265, 285, 305, 325, 345,
+				    365, 385, 405, 425, 445,
+				    465, 485, 505, 525, 545,
+				    565, 585, 605, 625, 645,
+				    665, 695, 715, 735, 755,
+				    775, 795, 815, 835, 855,
+				    875, 895, 915, 935, 955,
+				    975, 995, 1015, 1035, 1055,
+				    1085, 1105, 1125, 1145, 1175,
+				    1195, 1225, 1255, 1275};
+	u32 reg_idx = 0;
+	u32 i;
+	u8 nbi_table_idx = FFT_128_TYPE;
+
+	if (dm->support_ic_type & ODM_IC_11N_SERIES) {
+		nbi_table_idx = FFT_128_TYPE;
+	} else if (dm->support_ic_type & ODM_IC_11AC_1_SERIES) {
+		nbi_table_idx = FFT_256_TYPE;
+	} else if (dm->support_ic_type & ODM_IC_11AC_2_SERIES) {
+		if (bw == 80)
+			nbi_table_idx = FFT_256_TYPE;
+		else /*@20M, 40M*/
+			nbi_table_idx = FFT_128_TYPE;
+	}
+
+	if (nbi_table_idx == FFT_128_TYPE) {
+		for (i = 0; i < NBI_128TONE; i++) {
+			if (tone_idx_tmp < nbi_128[i]) {
+				reg_idx = i + 1;
+				break;
+			}
+		}
+
+	} else if (nbi_table_idx == FFT_256_TYPE) {
+		for (i = 0; i < NBI_256TONE; i++) {
+			if (tone_idx_tmp < nbi_256[i]) {
+				reg_idx = i + 1;
+				break;
+			}
+		}
+	}
+
+	if (dm->support_ic_type & ODM_IC_11N_SERIES) {
+		odm_set_bb_reg(dm, R_0xc40, 0x1f000000, reg_idx);
+		PHYDM_DBG(dm, ODM_COMP_API,
+			  "Set tone idx:  Reg0xC40[28:24] = ((0x%x))\n",
+			  reg_idx);
+	} else {
+		odm_set_bb_reg(dm, R_0x87c, 0xfc000, reg_idx);
+		PHYDM_DBG(dm, ODM_COMP_API,
+			  "Set tone idx: Reg0x87C[19:14] = ((0x%x))\n",
+			  reg_idx);
+	}
+}
+
+void phydm_nbi_enable(void *dm_void, u32 enable)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	u32 val = 0;
+
+	val = (enable == FUNC_ENABLE) ? 1 : 0;
+
+	PHYDM_DBG(dm, ODM_COMP_API, "Enable NBI=%d\n", val);
+
+	if (dm->support_ic_type & ODM_IC_11N_SERIES) {
+		if (dm->support_ic_type & (ODM_RTL8192F | ODM_RTL8197F)) {
+			val = (enable == FUNC_ENABLE) ? 0xf : 0;
+			odm_set_bb_reg(dm, R_0xc50, 0xf000000, val);
+		} else {
+			odm_set_bb_reg(dm, R_0xc40, BIT(9), val);
+		}
+	} else if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
+		if (dm->support_ic_type & (ODM_RTL8822B | ODM_RTL8821C)) {
+			odm_set_bb_reg(dm, R_0x87c, BIT(13), val);
+			odm_set_bb_reg(dm, R_0xc20, BIT(28), val);
+			if (dm->rf_type > RF_1T1R)
+				odm_set_bb_reg(dm, R_0xe20, BIT(28), val);
+		} else {
+			odm_set_bb_reg(dm, R_0x87c, BIT(13), val);
+		}
+	}
+}
+
+u8 phydm_find_fc(void *dm_void, u32 channel, u32 bw, u32 second_ch, u32 *fc_in)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	u32 fc = *fc_in;
+	u32 start_ch_per_40m[NUM_START_CH_40M] = {36, 44, 52, 60, 100,
+						  108, 116, 124, 132, 140,
+						  149, 157, 165, 173};
+	u32 start_ch_per_80m[NUM_START_CH_80M] = {36, 52, 100, 116, 132,
+						  149, 165};
+	u32 *start_ch = &start_ch_per_40m[0];
+	u32 num_start_channel = NUM_START_CH_40M;
+	u32 channel_offset = 0;
+	u32 i;
+
+	/*@2.4G*/
+	if (channel <= 14 && channel > 0) {
+		if (bw == 80)
+			return PHYDM_SET_FAIL;
+
+		fc = 2412 + (channel - 1) * 5;
+
+		if (bw == 40 && second_ch == PHYDM_ABOVE) {
+			if (channel >= 10) {
+				PHYDM_DBG(dm, ODM_COMP_API,
+					  "CH = ((%d)), Scnd_CH = ((%d)) Error setting\n",
+					  channel, second_ch);
+				return PHYDM_SET_FAIL;
+			}
+			fc += 10;
+		} else if (bw == 40 && (second_ch == PHYDM_BELOW)) {
+			if (channel <= 2) {
+				PHYDM_DBG(dm, ODM_COMP_API,
+					  "CH = ((%d)), Scnd_CH = ((%d)) Error setting\n",
+					  channel, second_ch);
+				return PHYDM_SET_FAIL;
+			}
+			fc -= 10;
+		}
+	}
+	/*@5G*/
+	else if (channel >= 36 && channel <= 177) {
+		if (bw != 20) {
+			if (bw == 40) {
+				num_start_channel = NUM_START_CH_40M;
+				start_ch = &start_ch_per_40m[0];
+				channel_offset = CH_OFFSET_40M;
+			} else if (bw == 80) {
+				num_start_channel = NUM_START_CH_80M;
+				start_ch = &start_ch_per_80m[0];
+				channel_offset = CH_OFFSET_80M;
+			}
+
+			for (i = 0; i < (num_start_channel - 1); i++) {
+				if (channel < start_ch[i + 1]) {
+					channel = start_ch[i] + channel_offset;
+					break;
+				}
+			}
+			PHYDM_DBG(dm, ODM_COMP_API, "Mod_CH = ((%d))\n",
+				  channel);
+		}
+
+		fc = 5180 + (channel - 36) * 5;
+
+	} else {
+		PHYDM_DBG(dm, ODM_COMP_API, "CH = ((%d)) Error setting\n",
+			  channel);
+		return PHYDM_SET_FAIL;
+	}
+
+	*fc_in = fc;
+
+	return PHYDM_SET_SUCCESS;
+}
+
+u8 phydm_find_intf_distance(void *dm_void, u32 bw, u32 fc, u32 f_interference,
+			    u32 *tone_idx_tmp_in)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	u32 bw_up = 0, bw_low = 0;
+	u32 int_distance = 0;
+	u32 tone_idx_tmp = 0;
+	u8 set_result = PHYDM_SET_NO_NEED;
+
+	bw_up = fc + bw / 2;
+	bw_low = fc - bw / 2;
+
+	PHYDM_DBG(dm, ODM_COMP_API,
+		  "[f_l, fc, fh] = [ %d, %d, %d ], f_int = ((%d))\n", bw_low,
+		  fc, bw_up, f_interference);
+
+	if (f_interference >= bw_low && f_interference <= bw_up) {
+		int_distance = DIFF_2(fc, f_interference);
+		/*@10*(int_distance /0.3125)*/
+		tone_idx_tmp = (int_distance << 5);
+		PHYDM_DBG(dm, ODM_COMP_API,
+			  "int_distance = ((%d MHz)) Mhz, tone_idx_tmp = ((%d.%d))\n",
+			  int_distance, tone_idx_tmp / 10,
+			  tone_idx_tmp % 10);
+		*tone_idx_tmp_in = tone_idx_tmp;
+		set_result = PHYDM_SET_SUCCESS;
+	}
+
+	return set_result;
+}
+
+u8 phydm_csi_mask_setting(void *dm_void, u32 enable, u32 ch, u32 bw,
+			  u32 f_intf, u32 sec_ch)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	u32 fc = 2412;
+	u8 direction = FREQ_POSITIVE;
+	u32 tone_idx = 0;
+	u8 set_result = PHYDM_SET_SUCCESS;
+	u8 rpt = 0;
+
+	if (enable == FUNC_DISABLE) {
+		set_result = PHYDM_SET_SUCCESS;
+		phydm_clean_all_csi_mask(dm);
+
+	} else {
+		PHYDM_DBG(dm, ODM_COMP_API,
+			  "[Set CSI MASK_] CH = ((%d)), BW = ((%d)), f_intf = ((%d)), Scnd_CH = ((%s))\n",
+			  ch, bw, f_intf,
+			  (((bw == 20) || (ch > 14)) ? "Don't care" :
+			  (sec_ch == PHYDM_ABOVE) ? "H" : "L"));
+
+		/*@calculate fc*/
+		if (phydm_find_fc(dm, ch, bw, sec_ch, &fc) == PHYDM_SET_FAIL) {
+			set_result = PHYDM_SET_FAIL;
+		} else {
+			/*@calculate interference distance*/
+			rpt = phydm_find_intf_distance(dm, bw, fc, f_intf,
+						       &tone_idx);
+			if (rpt == PHYDM_SET_SUCCESS) {
+				if (f_intf >= fc)
+					direction = FREQ_POSITIVE;
+				else
+					direction = FREQ_NEGATIVE;
+
+				phydm_set_csi_mask(dm, tone_idx, direction);
+				set_result = PHYDM_SET_SUCCESS;
+			} else {
+				set_result = PHYDM_SET_NO_NEED;
+			}
+		}
+	}
+
+	if (set_result == PHYDM_SET_SUCCESS)
+		phydm_csi_mask_enable(dm, enable);
+	else
+		phydm_csi_mask_enable(dm, FUNC_DISABLE);
+
+	return set_result;
+}
+
+#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
+u8 phydm_csi_mask_setting_jgr3(void *dm_void, u32 enable, u32 ch, u32 bw,
+			       u32 f_intf, u32 sec_ch, u8 wgt)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	u32 fc = 2412;
+	u8 direction = FREQ_POSITIVE;
+	u32 tone_idx = 0;
+	u8 set_result = PHYDM_SET_SUCCESS;
+	u8 rpt = 0;
+
+	if (enable == FUNC_DISABLE) {
+		phydm_csi_mask_enable(dm, FUNC_ENABLE);
+		phydm_clean_all_csi_mask(dm);
+		phydm_csi_mask_enable(dm, FUNC_DISABLE);
+		set_result = PHYDM_SET_SUCCESS;
+	} else {
+		PHYDM_DBG(dm, ODM_COMP_API,
+			  "[Set CSI MASK] CH = ((%d)), BW = ((%d)), f_intf = ((%d)), Scnd_CH = ((%s)), wgt = ((%d))\n",
+			  ch, bw, f_intf,
+			  (((bw == 20) || (ch > 14)) ? "Don't care" :
+			  (sec_ch == PHYDM_ABOVE) ? "H" : "L"), wgt);
+
+		/*@calculate fc*/
+		if (phydm_find_fc(dm, ch, bw, sec_ch, &fc) == PHYDM_SET_FAIL) {
+			set_result = PHYDM_SET_FAIL;
+		} else {
+			/*@calculate interference distance*/
+			rpt = phydm_find_intf_distance(dm, bw, fc, f_intf,
+						       &tone_idx);
+			if (rpt == PHYDM_SET_SUCCESS) {
+				if (f_intf >= fc)
+					direction = FREQ_POSITIVE;
+				else
+					direction = FREQ_NEGATIVE;
+
+				phydm_csi_mask_enable(dm, FUNC_ENABLE);
+				phydm_set_csi_mask_jgr3(dm, tone_idx, direction,
+							wgt);
+				set_result = PHYDM_SET_SUCCESS;
+			} else {
+				set_result = PHYDM_SET_NO_NEED;
+			}
+		}
+		if (!(set_result == PHYDM_SET_SUCCESS))
+			phydm_csi_mask_enable(dm, FUNC_DISABLE);
+	}
+
+	return set_result;
+}
+
+void phydm_set_csi_mask_jgr3(void *dm_void, u32 tone_idx_tmp, u8 tone_direction,
+			     u8 wgt)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	u32 reg_tmp_value = 0;
+	u32 tone_num = 64;
+	u32 tone_num_shift = 0;
+	u32 table_addr = 0;
+	u32 addr = 0;
+	u8 rf_bw = 0;
+
+	/* @calculate real tone idx*/
+	if ((tone_idx_tmp % 10) >= 5)
+		tone_idx_tmp += 10;
+
+	tone_idx_tmp = (tone_idx_tmp / 10);
+
+	rf_bw = odm_read_1byte(dm, R_0x9b0);
+	if (((rf_bw & 0xc) >> 2) == 0x2)
+		tone_num = 128; /* RF80 : tone-1 at tone_idx=255 */
+	else
+		tone_num = 64; /* RF20/40 : tone-1 at tone_idx=127 */
+
+	if (tone_direction == FREQ_POSITIVE) {
+		if (tone_idx_tmp >= (tone_num - 1))
+			tone_idx_tmp = (tone_num - 1);
+	} else {
+		tone_num_shift = tone_num;
+		if (tone_idx_tmp >= tone_num)
+			tone_idx_tmp = tone_num;
+
+		tone_idx_tmp = (tone_num << 1) - tone_idx_tmp;
+	}
+	table_addr = tone_idx_tmp >> 1;
+
+	reg_tmp_value = odm_read_4byte(dm, R_0x1d94);
+	PHYDM_DBG(dm, ODM_COMP_API,
+		  "Pre Mask tone idx[%d]: Reg0x1d94 = ((0x%x))\n",
+		  (tone_idx_tmp + tone_num_shift), reg_tmp_value);
+	odm_set_bb_reg(dm, R_0x1d94, MASKBYTE2, (table_addr & 0xff));
+	if (tone_idx_tmp % 2)
+		addr = 0xf;
+	else
+		addr = 0xf0;
+
+	odm_set_bb_reg(dm, R_0x1d94, addr, (BIT(3) | (wgt & 0x7)));
+	reg_tmp_value = odm_read_4byte(dm, R_0x1d94);
+	PHYDM_DBG(dm, ODM_COMP_API,
+		  "New Mask tone idx[%d]: Reg0x1d94 = ((0x%x))\n",
+		  (tone_idx_tmp + tone_num_shift), reg_tmp_value);
+	odm_set_bb_reg(dm, R_0x1ee8, 0x3, 0x0);
+}
+
+u8 phydm_nbi_setting_jgr3(void *dm_void, u32 enable, u32 ch, u32 bw, u32 f_intf,
+			  u32 sec_ch, u8 path)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	u32 fc = 2412;
+	u8 direction = FREQ_POSITIVE;
+	u32 tone_idx = 0;
+	u8 set_result = PHYDM_SET_SUCCESS;
+	u8 rpt = 0;
+
+	if (enable == FUNC_DISABLE) {
+		set_result = PHYDM_SET_SUCCESS;
+	} else {
+		PHYDM_DBG(dm, ODM_COMP_API,
+			  "[Set NBI] CH = ((%d)), BW = ((%d)), f_intf = ((%d)), Scnd_CH = ((%s))\n",
+			  ch, bw, f_intf,
+			  (((sec_ch == PHYDM_DONT_CARE) || (bw == 20) ||
+			  (ch > 14)) ? "Don't care" :
+			  (sec_ch == PHYDM_ABOVE) ? "H" : "L"));
+
+		/*@calculate fc*/
+		if (phydm_find_fc(dm, ch, bw, sec_ch, &fc) == PHYDM_SET_FAIL) {
+			set_result = PHYDM_SET_FAIL;
+		} else {
+			/*@calculate interference distance*/
+			rpt = phydm_find_intf_distance(dm, bw, fc, f_intf,
+						       &tone_idx);
+			if (rpt == PHYDM_SET_SUCCESS) {
+				if (f_intf >= fc)
+					direction = FREQ_POSITIVE;
+				else
+					direction = FREQ_NEGATIVE;
+
+				phydm_set_nbi_reg_jgr3(dm, tone_idx, direction,
+						       path);
+				set_result = PHYDM_SET_SUCCESS;
+			} else {
+				set_result = PHYDM_SET_NO_NEED;
+		}
+	}
+	}
+
+	if (set_result == PHYDM_SET_SUCCESS)
+		phydm_nbi_enable_jgr3(dm, enable, path);
+	else
+		phydm_nbi_enable_jgr3(dm, FUNC_DISABLE, path);
+
+	return set_result;
+}
+
+void phydm_set_nbi_reg_jgr3(void *dm_void, u32 tone_idx_tmp, u8 tone_direction,
+			    u8 path)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	u32 reg_tmp_value = 0;
+	u32 tone_num = 64;
+	u32 tone_num_shift = 0;
+	u32 addr = 0;
+	u8 rf_bw = 0;
+
+	/* @calculate real tone idx*/
+	if ((tone_idx_tmp % 10) >= 5)
+		tone_idx_tmp += 10;
+
+	tone_idx_tmp = (tone_idx_tmp / 10);
+
+	rf_bw = odm_read_1byte(dm, R_0x9b0);
+	if (((rf_bw & 0xc) >> 2) == 0x2)
+		tone_num = 128; /* RF80 : tone-1 at tone_idx=255 */
+	else
+		tone_num = 64; /* RF20/40 : tone-1 at tone_idx=127 */
+
+	if (tone_direction == FREQ_POSITIVE) {
+		if (tone_idx_tmp >= (tone_num - 1))
+			tone_idx_tmp = (tone_num - 1);
+	} else {
+		tone_num_shift = tone_num;
+		if (tone_idx_tmp >= tone_num)
+			tone_idx_tmp = tone_num;
+
+		tone_idx_tmp = (tone_num << 1) - tone_idx_tmp;
+	}
+
+	switch (path) {
+	case RF_PATH_A:
+		odm_set_bb_reg(dm, R_0x1944, 0x001FF000, tone_idx_tmp);
+		PHYDM_DBG(dm, ODM_COMP_API,
+			  "Set tone idx[%d]:PATH-A = ((0x%x))\n",
+			  (tone_idx_tmp + tone_num_shift), tone_idx_tmp);
+		break;
+	#if (defined(PHYDM_COMPILE_ABOVE_2SS))
+	case RF_PATH_B:
+		odm_set_bb_reg(dm, R_0x4044, 0x001FF000, tone_idx_tmp);
+		PHYDM_DBG(dm, ODM_COMP_API,
+			  "Set tone idx[%d]:PATH-B = ((0x%x))\n",
+			  (tone_idx_tmp + tone_num_shift), tone_idx_tmp);
+		break;
+	#endif
+	#if (defined(PHYDM_COMPILE_ABOVE_3SS))
+	case RF_PATH_C:
+		odm_set_bb_reg(dm, R_0x5044, 0x001FF000, tone_idx_tmp);
+		PHYDM_DBG(dm, ODM_COMP_API,
+			  "Set tone idx[%d]:PATH-C = ((0x%x))\n",
+			  (tone_idx_tmp + tone_num_shift), tone_idx_tmp);
+		break;
+	#endif
+	#if (defined(PHYDM_COMPILE_ABOVE_4SS))
+	case RF_PATH_D:
+		odm_set_bb_reg(dm, R_0x5144, 0x001FF000, tone_idx_tmp);
+		PHYDM_DBG(dm, ODM_COMP_API,
+			  "Set tone idx[%d]:PATH-D = ((0x%x))\n",
+			  (tone_idx_tmp + tone_num_shift), tone_idx_tmp);
+		break;
+	#endif
+	default:
+		break;
+	}
+}
+
+void phydm_nbi_enable_jgr3(void *dm_void, u32 enable, u8 path)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	u32 val = 0;
+
+	val = (enable == FUNC_ENABLE) ? 1 : 0;
+
+	PHYDM_DBG(dm, ODM_COMP_API, "Enable NBI=%d\n", val);
+
+	odm_set_bb_reg(dm, R_0x818, BIT(11), val);
+	if (enable == FUNC_ENABLE) {
+		switch (path) {
+		case RF_PATH_A:
+			odm_set_bb_reg(dm, R_0x1940, BIT(31), val);
+			break;
+		#if (defined(PHYDM_COMPILE_ABOVE_2SS))
+		case RF_PATH_B:
+			odm_set_bb_reg(dm, R_0x4040, BIT(31), val);
+			break;
+		#endif
+		#if (defined(PHYDM_COMPILE_ABOVE_3SS))
+		case RF_PATH_C:
+			odm_set_bb_reg(dm, R_0x5040, BIT(31), val);
+			break;
+		#endif
+		#if (defined(PHYDM_COMPILE_ABOVE_4SS))
+		case RF_PATH_D:
+			odm_set_bb_reg(dm, R_0x5140, BIT(31), val);
+			break;
+		#endif
+		default:
+			break;
+		}
+	} else {
+		odm_set_bb_reg(dm, R_0x1940, BIT(31), val);
+		#if (defined(PHYDM_COMPILE_ABOVE_2SS))
+		odm_set_bb_reg(dm, R_0x4040, BIT(31), val);
+		#endif
+		#if (defined(PHYDM_COMPILE_ABOVE_3SS))
+		odm_set_bb_reg(dm, R_0x5040, BIT(31), val);
+		#endif
+		#if (defined(PHYDM_COMPILE_ABOVE_4SS))
+		odm_set_bb_reg(dm, R_0x5140, BIT(31), val);
+		#endif
+	}
+}
+
+#endif
+u8 phydm_nbi_setting(void *dm_void, u32 enable, u32 ch, u32 bw, u32 f_intf,
+		     u32 sec_ch)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	u32 fc = 2412;
+	u8 direction = FREQ_POSITIVE;
+	u32 tone_idx = 0;
+	u8 set_result = PHYDM_SET_SUCCESS;
+	u8 rpt = 0;
+
+	if (enable == FUNC_DISABLE) {
+		set_result = PHYDM_SET_SUCCESS;
+	} else {
+		PHYDM_DBG(dm, ODM_COMP_API,
+			  "[Set NBI] CH = ((%d)), BW = ((%d)), f_intf = ((%d)), Scnd_CH = ((%s))\n",
+			  ch, bw, f_intf,
+			  (((sec_ch == PHYDM_DONT_CARE) || (bw == 20) ||
+			  (ch > 14)) ? "Don't care" :
+			  (sec_ch == PHYDM_ABOVE) ? "H" : "L"));
+
+		/*@calculate fc*/
+		if (phydm_find_fc(dm, ch, bw, sec_ch, &fc) == PHYDM_SET_FAIL) {
+			set_result = PHYDM_SET_FAIL;
+		} else {
+			/*@calculate interference distance*/
+			rpt = phydm_find_intf_distance(dm, bw, fc, f_intf,
+						       &tone_idx);
+			if (rpt == PHYDM_SET_SUCCESS) {
+				if (f_intf >= fc)
+					direction = FREQ_POSITIVE;
+				else
+					direction = FREQ_NEGATIVE;
+
+				phydm_set_nbi_reg(dm, tone_idx, bw);
+
+				set_result = PHYDM_SET_SUCCESS;
+			} else {
+				set_result = PHYDM_SET_NO_NEED;
+		}
+	}
+	}
+
+	if (set_result == PHYDM_SET_SUCCESS)
+		phydm_nbi_enable(dm, enable);
+	else
+		phydm_nbi_enable(dm, FUNC_DISABLE);
+
+	return set_result;
+}
+
+void phydm_nbi_debug(void *dm_void, char input[][16], u32 *_used, char *output,
+		     u32 *_out_len)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	u32 used = *_used;
+	u32 out_len = *_out_len;
+	u32 val[10] = {0};
+	char help[] = "-h";
+	u8 i = 0, input_idx = 0, idx_lmt = 0;
+	u32 enable = 0; /*@function enable*/
+	u32 ch = 0;
+	u32 bw = 0;
+	u32 f_int = 0; /*@interference frequency*/
+	u32 sec_ch = 0; /*secondary channel*/
+	u8 rpt = 0;
+	u8 path = 0;
+
+	if (dm->support_ic_type & ODM_IC_JGR3_SERIES)
+		idx_lmt = 6;
+	else
+		idx_lmt = 5;
+	for (i = 0; i < idx_lmt; i++) {
+		if (input[i + 1]) {
+			PHYDM_SSCANF(input[i + 1], DCMD_DECIMAL, &val[i]);
+			input_idx++;
+		}
+	}
+
+	if (input_idx == 0)
+		return;
+
+	enable = val[0];
+	ch = val[1];
+	bw = val[2];
+	f_int = val[3];
+	sec_ch = val[4];
+	#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
+	path = (u8)val[5];
+	#endif
+
+	if ((strcmp(input[1], help) == 0)) {
+		#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
+		if (dm->support_ic_type & ODM_IC_JGR3_SERIES)
+			PDM_SNPF(out_len, used, output + used, out_len - used,
+				 "{en:1 Dis all path:2} {ch} {BW:20/40/80} {f_intf(Mhz)} {Scnd_CH(L=1, H=2)} {Path:A~D(0~3)}\n");
+		else
+		#endif
+			PDM_SNPF(out_len, used, output + used, out_len - used,
+				 "{en:1 Dis:2} {ch} {BW:20/40/80} {f_intf(Mhz)} {Scnd_CH(L=1, H=2)}\n");
+		*_used = used;
+		*_out_len = out_len;
+		return;
+	} else if (val[0] == FUNC_ENABLE) {
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "[Enable NBI] CH = ((%d)), BW = ((%d)), f_intf = ((%d)), Scnd_CH = ((%s))\n",
+			 ch, bw, f_int,
+			 ((sec_ch == PHYDM_DONT_CARE) ||
+			 (bw == 20) || (ch > 14)) ? "Don't care" :
+			 ((sec_ch == PHYDM_ABOVE) ? "H" : "L"));
+		#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
+		if (dm->support_ic_type & ODM_IC_JGR3_SERIES)
+			rpt = phydm_nbi_setting_jgr3(dm, enable, ch, bw, f_int,
+						     sec_ch, path);
+		else
+		#endif
+			rpt = phydm_nbi_setting(dm, enable, ch, bw, f_int,
+						sec_ch);
+	} else if (val[0] == FUNC_DISABLE) {
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "[Disable NBI]\n");
+		#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
+		if (dm->support_ic_type & ODM_IC_JGR3_SERIES)
+			rpt = phydm_nbi_setting_jgr3(dm, enable, ch, bw, f_int,
+						     sec_ch, path);
+		else
+		#endif
+			rpt = phydm_nbi_setting(dm, enable, ch, bw, f_int,
+						sec_ch);
+	} else {
+		rpt = PHYDM_SET_FAIL;
+	}
+
+	PDM_SNPF(out_len, used, output + used, out_len - used,
+		 "[NBI set result: %s]\n",
+		 (rpt == PHYDM_SET_SUCCESS) ? "Success" :
+		 ((rpt == PHYDM_SET_NO_NEED) ? "No need" : "Error"));
+
+	*_used = used;
+	*_out_len = out_len;
+}
+
+void phydm_csi_debug(void *dm_void, char input[][16], u32 *_used, char *output,
+		     u32 *_out_len)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	u32 used = *_used;
+	u32 out_len = *_out_len;
+	u32 val[10] = {0};
+	char help[] = "-h";
+	u8 i = 0, input_idx = 0, idx_lmt = 0;
+	u32 enable = 0;  /*@function enable*/
+	u32 ch = 0;
+	u32 bw = 0;
+	u32 f_int = 0; /*@interference frequency*/
+	u32 sec_ch = 0;  /*secondary channel*/
+	u8 rpt = 0;
+	u8 wgt = 0;
+
+	if (dm->support_ic_type & ODM_IC_JGR3_SERIES)
+		idx_lmt = 6;
+	else
+		idx_lmt = 5;
+
+	for (i = 0; i < idx_lmt; i++) {
+		if (input[i + 1]) {
+			PHYDM_SSCANF(input[i + 1], DCMD_DECIMAL, &val[i]);
+			input_idx++;
+		}
+	}
+
+	if (input_idx == 0)
+		return;
+
+	enable = val[0];
+	ch = val[1];
+	bw = val[2];
+	f_int = val[3];
+	sec_ch = val[4];
+	#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
+	wgt = (u8)val[5];
+	#endif
+
+	if ((strcmp(input[1], help) == 0)) {
+		#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
+		if (dm->support_ic_type & ODM_IC_JGR3_SERIES)
+			PDM_SNPF(out_len, used, output + used, out_len - used,
+				 "{en:1 Dis:2} {ch} {BW:20/40/80} {f_intf(Mhz)} {Scnd_CH(L=1, H=2)}\n{wgt:7:3/4,6:2/1,5:1/4,4:1/8,3:1/16,2:1/32,1:1/64,0:0}\n");
+		else
+		#endif
+			PDM_SNPF(out_len, used, output + used, out_len - used,
+				 "{en:1 Dis:2} {ch} {BW:20/40/80} {f_intf(Mhz)} {Scnd_CH(L=1, H=2)}\n");
+
+		*_used = used;
+		*_out_len = out_len;
+		return;
+
+	} else if (val[0] == FUNC_ENABLE) {
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "[Enable CSI MASK] CH = ((%d)), BW = ((%d)), f_intf = ((%d)), Scnd_CH = ((%s))\n",
+			 ch, bw, f_int,
+			 (ch > 14) ? "Don't care" :
+			 (((sec_ch == PHYDM_DONT_CARE) ||
+			 (bw == 20) || (ch > 14)) ? "H" : "L"));
+		#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
+		if (dm->support_ic_type & ODM_IC_JGR3_SERIES)
+			rpt = phydm_csi_mask_setting_jgr3(dm, enable, ch, bw,
+							  f_int, sec_ch, wgt);
+		else
+		#endif
+			rpt = phydm_csi_mask_setting(dm, enable, ch, bw, f_int,
+						     sec_ch);
+	} else if (val[0] == FUNC_DISABLE) {
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "[Disable CSI MASK]\n");
+		#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
+		if (dm->support_ic_type & ODM_IC_JGR3_SERIES)
+			rpt = phydm_csi_mask_setting_jgr3(dm, enable, ch, bw,
+							  f_int, sec_ch, wgt);
+		else
+		#endif
+			rpt = phydm_csi_mask_setting(dm, enable, ch, bw, f_int,
+						     sec_ch);
+	} else {
+		rpt = PHYDM_SET_FAIL;
+	}
+	PDM_SNPF(out_len, used, output + used, out_len - used,
+		 "[CSI MASK set result: %s]\n",
+		 (rpt == PHYDM_SET_SUCCESS) ? "Success" :
+		 ((rpt == PHYDM_SET_NO_NEED) ? "No need" : "Error"));
+
+	*_used = used;
+	*_out_len = out_len;
+}
+
+void phydm_stop_ck320(void *dm_void, u8 enable)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	u32 val = enable ? 1 : 0;
+
+	if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
+		odm_set_bb_reg(dm, R_0x8b4, BIT(6), val);
+	} else {
+		if (dm->support_ic_type & ODM_IC_N_2SS) /*N-2SS*/
+			odm_set_bb_reg(dm, R_0x87c, BIT(29), val);
+		else /*N-1SS*/
+			odm_set_bb_reg(dm, R_0x87c, BIT(31), val);
+	}
+}
+
+boolean
+phydm_set_bb_txagc_offset(void *dm_void, s8 power_offset, /*@(unit: dB)*/
+			  u8 add_half_db /*@(+0.5 dB)*/)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	s8 power_idx = power_offset * 2;
+	boolean set_success = false;
+
+	PHYDM_DBG(dm, ODM_COMP_API, "power_offset=%d, add_half_db =%d\n",
+		  power_offset, add_half_db);
+
+	#if ODM_IC_11AC_SERIES_SUPPORT
+	if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
+		if (power_offset > -16 || power_offset < 15) {
+			if (add_half_db)
+				power_idx += 1;
+
+			power_idx &= 0x3f;
+
+			PHYDM_DBG(dm, ODM_COMP_API, "Reg_idx =0x%x\n",
+				  power_idx);
+			odm_set_bb_reg(dm, R_0x8b4, 0x3f, power_idx);
+			set_success = true;
+		} else {
+			pr_debug("[Warning] TX AGC Offset Setting error!");
+		}
+	}
+	#endif
+
+	#if ODM_IC_11N_SERIES_SUPPORT
+	if (dm->support_ic_type & ODM_IC_11N_SERIES) {
+		if (power_offset > -8 || power_offset < 7) {
+			if (add_half_db)
+				power_idx += 1;
+
+			power_idx &= 0x1f;
+
+			PHYDM_DBG(dm, ODM_COMP_API, "Reg_idx =0x%x\n",
+				  power_idx);
+			/*r_txagc_offset_a*/
+			odm_set_bb_reg(dm, R_0x80c, 0x1f00, power_idx);
+			/*r_txagc_offset_b*/
+			odm_set_bb_reg(dm, R_0x80c, 0x3e000, power_idx);
+			set_success = true;
+		} else {
+			pr_debug("[Warning] TX AGC Offset Setting error!");
+		}
+	}
+	#endif
+
+	return set_success;
+}
+
+#ifdef PHYDM_COMMON_API_SUPPORT
+boolean
+phydm_api_shift_txagc(void *dm_void, u32 pwr_offset, enum rf_path path,
+		      boolean is_positive) {
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	boolean ret = false;
+	u32 txagc_cck = 0;
+	u32 txagc_ofdm = 0;
+	u32 r_txagc_ofdm[4] = {0x18e8, 0x41e8, 0x52e8, 0x53e8};
+	u32 r_txagc_cck[4] = {0x18a0, 0x41a0, 0x52a0, 0x53a0};
+
+	#if (RTL8822C_SUPPORT)
+	if (dm->support_ic_type & ODM_RTL8822C) {
+		if (path > RF_PATH_B) {
+			PHYDM_DBG(dm, ODM_PHY_CONFIG, "Unsupported path (%d)\n",
+				  path);
+			return false;
+		}
+		txagc_cck = (u8)odm_get_bb_reg(dm, r_txagc_cck[path],
+						   0x7F0000);
+		txagc_ofdm = (u8)odm_get_bb_reg(dm, r_txagc_ofdm[path],
+						    0x1FC00);
+		if (is_positive) {
+			if (((txagc_cck + pwr_offset) > 127) ||
+			    ((txagc_ofdm + pwr_offset) > 127))
+				return false;
+
+			txagc_cck += pwr_offset;
+			txagc_ofdm += pwr_offset;
+		} else {
+			if (pwr_offset > txagc_cck || pwr_offset > txagc_ofdm)
+				return false;
+
+			txagc_cck -= pwr_offset;
+			txagc_ofdm -= pwr_offset;
+		}
+
+		ret = config_phydm_write_txagc_ref_8822c(dm, (u8)txagc_cck,
+							 path, PDM_CCK);
+		ret &= config_phydm_write_txagc_ref_8822c(dm, (u8)txagc_ofdm,
+							 path, PDM_OFDM);
+		PHYDM_DBG(dm, ODM_PHY_CONFIG,
+			  "%s: path-%d txagc_cck_ref=%x txagc_ofdm_ref=0x%x\n",
+			  __func__, path, txagc_cck, txagc_ofdm);
+	}
+	#endif
+
+	return ret;
+}
+
+boolean
+phydm_api_set_txagc(void *dm_void, u32 pwr_idx, enum rf_path path,
+		    u8 rate, boolean is_single_rate)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	boolean ret = false;
+	#if (RTL8198F_SUPPORT || RTL8822C_SUPPORT)
+	u8 base = 0;
+	u8 txagc_tmp = 0;
+	s8 pw_by_rate_tmp = 0;
+	s8 pw_by_rate_new = 0;
+	#endif
+	#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
+	u8 i = 0;
+	#endif
+
+#if (RTL8822B_SUPPORT || RTL8821C_SUPPORT || RTL8195B_SUPPORT)
+	if (dm->support_ic_type &
+	    (ODM_RTL8822B | ODM_RTL8821C | ODM_RTL8195B)) {
+		if (is_single_rate) {
+			#if (RTL8822B_SUPPORT)
+			if (dm->support_ic_type == ODM_RTL8822B)
+				ret = phydm_write_txagc_1byte_8822b(dm, pwr_idx,
+								    path, rate);
+			#endif
+
+			#if (RTL8821C_SUPPORT)
+			if (dm->support_ic_type == ODM_RTL8821C)
+				ret = phydm_write_txagc_1byte_8821c(dm, pwr_idx,
+								    path, rate);
+			#endif
+
+			#if (RTL8195B_SUPPORT)
+			if (dm->support_ic_type == ODM_RTL8195B)
+				ret = phydm_write_txagc_1byte_8195b(dm, pwr_idx,
+								    path, rate);
+			#endif
+
+			#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
+			set_current_tx_agc(dm->priv, path, rate, (u8)pwr_idx);
+			#endif
+
+		} else {
+			#if (RTL8822B_SUPPORT)
+			if (dm->support_ic_type == ODM_RTL8822B)
+				ret = config_phydm_write_txagc_8822b(dm,
+								     pwr_idx,
+								     path,
+								     rate);
+			#endif
+
+			#if (RTL8821C_SUPPORT)
+			if (dm->support_ic_type == ODM_RTL8821C)
+				ret = config_phydm_write_txagc_8821c(dm,
+								     pwr_idx,
+								     path,
+								     rate);
+			#endif
+
+			#if (RTL8195B_SUPPORT)
+			if (dm->support_ic_type == ODM_RTL8195B)
+				ret = config_phydm_write_txagc_8195b(dm,
+								     pwr_idx,
+								     path,
+								     rate);
+			#endif
+
+			#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
+			for (i = 0; i < 4; i++)
+				set_current_tx_agc(dm->priv, path, (rate + i),
+						   (u8)pwr_idx);
+			#endif
+		}
+	}
+#endif
+
+#if (RTL8198F_SUPPORT)
+	if (dm->support_ic_type & ODM_RTL8198F) {
+		if (rate < 0x4)
+			txagc_tmp = config_phydm_read_txagc_8198f(dm, path,
+								  rate,
+								  PDM_CCK);
+		else
+			txagc_tmp = config_phydm_read_txagc_8198f(dm, path,
+								  rate,
+								  PDM_OFDM);
+
+		pw_by_rate_tmp = config_phydm_read_txagc_diff_8198f(dm, rate);
+		base = txagc_tmp -  pw_by_rate_tmp;
+		if (DIFF_2(pwr_idx, base) > 63)
+			return false;
+
+		pw_by_rate_new = (s8)(pwr_idx - base);
+		ret = phydm_write_txagc_1byte_8198f(dm, pw_by_rate_new, rate);
+		PHYDM_DBG(dm, ODM_PHY_CONFIG,
+			  "%s: path-%d rate_idx=%x base=0x%x new_diff=0x%x\n",
+			  __func__, path, rate, base, pw_by_rate_new);
+	}
+#endif
+
+#if (RTL8822C_SUPPORT)
+	if (dm->support_ic_type & ODM_RTL8822C) {
+		if (rate < 0x4)
+			txagc_tmp = config_phydm_read_txagc_8822c(dm, path,
+								  rate,
+								  PDM_CCK);
+		else
+			txagc_tmp = config_phydm_read_txagc_8822c(dm, path,
+								  rate,
+								  PDM_OFDM);
+
+		pw_by_rate_tmp = config_phydm_read_txagc_diff_8822c(dm, rate);
+		base = txagc_tmp - pw_by_rate_tmp;
+		if (DIFF_2(pwr_idx, base) > 63)
+			return false;
+
+		pw_by_rate_new = (s8)(pwr_idx - base);
+		ret = phydm_write_txagc_1byte_8822c(dm, pw_by_rate_new, rate);
+		PHYDM_DBG(dm, ODM_PHY_CONFIG,
+			  "%s: path-%d rate_idx=%x base=0x%x new_diff=0x%x\n",
+			  __func__, path, rate, base, pw_by_rate_new);
+	}
+#endif
+
+#if (RTL8197F_SUPPORT)
+	if (dm->support_ic_type & ODM_RTL8197F)
+		ret = config_phydm_write_txagc_8197f(dm, pwr_idx, path, rate);
+#endif
+
+#if (RTL8192F_SUPPORT)
+	if (dm->support_ic_type & ODM_RTL8192F)
+		ret = config_phydm_write_txagc_8192f(dm, pwr_idx, path, rate);
+#endif
+	return ret;
+}
+
+u8 phydm_api_get_txagc(void *dm_void, enum rf_path path, u8 hw_rate)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	u8 ret = 0;
+
+#if (RTL8822B_SUPPORT)
+	if (dm->support_ic_type & ODM_RTL8822B)
+		ret = config_phydm_read_txagc_8822b(dm, path, hw_rate);
+#endif
+
+#if (RTL8197F_SUPPORT)
+	if (dm->support_ic_type & ODM_RTL8197F)
+		ret = config_phydm_read_txagc_8197f(dm, path, hw_rate);
+#endif
+
+#if (RTL8821C_SUPPORT)
+	if (dm->support_ic_type & ODM_RTL8821C)
+		ret = config_phydm_read_txagc_8821c(dm, path, hw_rate);
+#endif
+
+#if (RTL8195B_SUPPORT)
+	if (dm->support_ic_type & ODM_RTL8195B)
+		ret = config_phydm_read_txagc_8195b(dm, path, hw_rate);
+#endif
+
+/*@jj add 20170822*/
+#if (RTL8192F_SUPPORT)
+	if (dm->support_ic_type & ODM_RTL8192F)
+		ret = config_phydm_read_txagc_8192f(dm, path, hw_rate);
+#endif
+
+#if (RTL8198F_SUPPORT)
+	if (dm->support_ic_type & ODM_RTL8198F) {
+		if (hw_rate < 0x4) {
+			ret = config_phydm_read_txagc_8198f(dm, path, hw_rate,
+							    PDM_CCK);
+		} else {
+			ret = config_phydm_read_txagc_8198f(dm, path, hw_rate,
+							    PDM_OFDM);
+		}
+	}
+#endif
+
+#if (RTL8822C_SUPPORT)
+	if (dm->support_ic_type & ODM_RTL8822C) {
+		if (hw_rate < 0x4) {
+			ret = config_phydm_read_txagc_8822c(dm, path, hw_rate,
+							    PDM_CCK);
+		} else {
+			ret = config_phydm_read_txagc_8822c(dm, path, hw_rate,
+							    PDM_OFDM);
+		}
+	}
+#endif
+	return ret;
+}
+
+boolean
+phydm_api_switch_bw_channel(void *dm_void, u8 ch, u8 pri_ch,
+			    enum channel_width bw)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	boolean ret = false;
+
+#if (RTL8822B_SUPPORT)
+	if (dm->support_ic_type & ODM_RTL8822B)
+		ret = config_phydm_switch_channel_bw_8822b(dm, ch, pri_ch, bw);
+#endif
+
+#if (RTL8197F_SUPPORT)
+	if (dm->support_ic_type & ODM_RTL8197F)
+		ret = config_phydm_switch_channel_bw_8197f(dm, ch, pri_ch, bw);
+#endif
+
+#if (RTL8821C_SUPPORT)
+	if (dm->support_ic_type & ODM_RTL8821C)
+		ret = config_phydm_switch_channel_bw_8821c(dm, ch, pri_ch, bw);
+#endif
+
+/*@jj add 20170822*/
+#if (RTL8192F_SUPPORT)
+	if (dm->support_ic_type & ODM_RTL8192F)
+		ret = config_phydm_switch_channel_bw_8192f(dm, ch, pri_ch, bw);
+#endif
+
+#if (RTL8198F_SUPPORT)
+	if (dm->support_ic_type & ODM_RTL8198F)
+		ret = config_phydm_switch_channel_bw_8198f(dm, ch, pri_ch, bw);
+#endif
+
+#if (RTL8822C_SUPPORT)
+	if (dm->support_ic_type & ODM_RTL8822C)
+		ret = config_phydm_switch_channel_bw_8822c(dm, ch, pri_ch, bw);
+#endif
+	return ret;
+}
+
+boolean
+phydm_api_trx_mode(void *dm_void, enum bb_path tx_path, enum bb_path rx_path,
+		   boolean is_2tx)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	boolean ret = false;
+
+#if (RTL8822B_SUPPORT)
+	if (dm->support_ic_type & ODM_RTL8822B)
+		ret = config_phydm_trx_mode_8822b(dm, tx_path, rx_path, is_2tx);
+#endif
+
+#if (RTL8197F_SUPPORT)
+	if (dm->support_ic_type & ODM_RTL8197F)
+		ret = config_phydm_trx_mode_8197f(dm, tx_path, rx_path, is_2tx);
+#endif
+
+#if (RTL8192F_SUPPORT)
+	if (dm->support_ic_type & ODM_RTL8192F)
+		ret = config_phydm_trx_mode_8192f(dm, tx_path, rx_path, is_2tx);
+#endif
+
+#if (RTL8198F_SUPPORT)
+	if (dm->support_ic_type & ODM_RTL8198F)
+		ret = config_phydm_trx_mode_8198f(dm, tx_path, rx_path, is_2tx);
+#endif
+
+#if (RTL8822C_SUPPORT)
+	if (dm->support_ic_type & ODM_RTL8822C)
+		ret = config_phydm_trx_mode_8822c(dm, tx_path, rx_path, is_2tx);
+#endif
+	return ret;
+}
+#else
+u8 config_phydm_read_txagc_n(void *dm_void, enum rf_path path, u8 hw_rate)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	u8 read_back_data = INVALID_TXAGC_DATA;
+	u32 reg_txagc;
+	u32 reg_mask;
+	/* This function is for 92E/88E etc... */
+	/* @Input need to be HW rate index, not driver rate index!!!! */
+
+	/* @Error handling */
+	if (path > RF_PATH_B || hw_rate > ODM_RATEMCS15) {
+		PHYDM_DBG(dm, ODM_PHY_CONFIG, "%s: unsupported path (%d)\n",
+			  __func__, path);
+		return INVALID_TXAGC_DATA;
+	}
+
+	if (path == RF_PATH_A) {
+		switch (hw_rate) {
+		case ODM_RATE1M:
+			reg_txagc = R_0xe08;
+			reg_mask = 0x00007f00;
+			break;
+		case ODM_RATE2M:
+			reg_txagc = R_0x86c;
+			reg_mask = 0x00007f00;
+			break;
+		case ODM_RATE5_5M:
+			reg_txagc = R_0x86c;
+			reg_mask = 0x007f0000;
+			break;
+		case ODM_RATE11M:
+			reg_txagc = R_0x86c;
+			reg_mask = 0x7f000000;
+			break;
+
+		case ODM_RATE6M:
+			reg_txagc = R_0xe00;
+			reg_mask = 0x0000007f;
+			break;
+		case ODM_RATE9M:
+			reg_txagc = R_0xe00;
+			reg_mask = 0x00007f00;
+			break;
+		case ODM_RATE12M:
+			reg_txagc = R_0xe00;
+			reg_mask = 0x007f0000;
+			break;
+		case ODM_RATE18M:
+			reg_txagc = R_0xe00;
+			reg_mask = 0x7f000000;
+			break;
+		case ODM_RATE24M:
+			reg_txagc = R_0xe04;
+			reg_mask = 0x0000007f;
+			break;
+		case ODM_RATE36M:
+			reg_txagc = R_0xe04;
+			reg_mask = 0x00007f00;
+			break;
+		case ODM_RATE48M:
+			reg_txagc = R_0xe04;
+			reg_mask = 0x007f0000;
+			break;
+		case ODM_RATE54M:
+			reg_txagc = R_0xe04;
+			reg_mask = 0x7f000000;
+			break;
+
+		case ODM_RATEMCS0:
+			reg_txagc = R_0xe10;
+			reg_mask = 0x0000007f;
+			break;
+		case ODM_RATEMCS1:
+			reg_txagc = R_0xe10;
+			reg_mask = 0x00007f00;
+			break;
+		case ODM_RATEMCS2:
+			reg_txagc = R_0xe10;
+			reg_mask = 0x007f0000;
+			break;
+		case ODM_RATEMCS3:
+			reg_txagc = R_0xe10;
+			reg_mask = 0x7f000000;
+			break;
+		case ODM_RATEMCS4:
+			reg_txagc = R_0xe14;
+			reg_mask = 0x0000007f;
+			break;
+		case ODM_RATEMCS5:
+			reg_txagc = R_0xe14;
+			reg_mask = 0x00007f00;
+			break;
+		case ODM_RATEMCS6:
+			reg_txagc = R_0xe14;
+			reg_mask = 0x007f0000;
+			break;
+		case ODM_RATEMCS7:
+			reg_txagc = R_0xe14;
+			reg_mask = 0x7f000000;
+			break;
+
+		case ODM_RATEMCS8:
+			reg_txagc = R_0xe18;
+			reg_mask = 0x0000007f;
+			break;
+		case ODM_RATEMCS9:
+			reg_txagc = R_0xe18;
+			reg_mask = 0x00007f00;
+			break;
+		case ODM_RATEMCS10:
+			reg_txagc = R_0xe18;
+			reg_mask = 0x007f0000;
+			break;
+		case ODM_RATEMCS11:
+			reg_txagc = R_0xe18;
+			reg_mask = 0x7f000000;
+			break;
+		case ODM_RATEMCS12:
+			reg_txagc = R_0xe1c;
+			reg_mask = 0x0000007f;
+			break;
+		case ODM_RATEMCS13:
+			reg_txagc = R_0xe1c;
+			reg_mask = 0x00007f00;
+			break;
+		case ODM_RATEMCS14:
+			reg_txagc = R_0xe1c;
+			reg_mask = 0x007f0000;
+			break;
+		case ODM_RATEMCS15:
+			reg_txagc = R_0xe1c;
+			reg_mask = 0x7f000000;
+			break;
+
+		default:
+			PHYDM_DBG(dm, ODM_PHY_CONFIG, "Invalid HWrate!\n");
+			break;
+		}
+	} else if (path == RF_PATH_B) {
+		switch (hw_rate) {
+		case ODM_RATE1M:
+			reg_txagc = R_0x838;
+			reg_mask = 0x00007f00;
+			break;
+		case ODM_RATE2M:
+			reg_txagc = R_0x838;
+			reg_mask = 0x007f0000;
+			break;
+		case ODM_RATE5_5M:
+			reg_txagc = R_0x838;
+			reg_mask = 0x7f000000;
+			break;
+		case ODM_RATE11M:
+			reg_txagc = R_0x86c;
+			reg_mask = 0x0000007f;
+			break;
+
+		case ODM_RATE6M:
+			reg_txagc = R_0x830;
+			reg_mask = 0x0000007f;
+			break;
+		case ODM_RATE9M:
+			reg_txagc = R_0x830;
+			reg_mask = 0x00007f00;
+			break;
+		case ODM_RATE12M:
+			reg_txagc = R_0x830;
+			reg_mask = 0x007f0000;
+			break;
+		case ODM_RATE18M:
+			reg_txagc = R_0x830;
+			reg_mask = 0x7f000000;
+			break;
+		case ODM_RATE24M:
+			reg_txagc = R_0x834;
+			reg_mask = 0x0000007f;
+			break;
+		case ODM_RATE36M:
+			reg_txagc = R_0x834;
+			reg_mask = 0x00007f00;
+			break;
+		case ODM_RATE48M:
+			reg_txagc = R_0x834;
+			reg_mask = 0x007f0000;
+			break;
+		case ODM_RATE54M:
+			reg_txagc = R_0x834;
+			reg_mask = 0x7f000000;
+			break;
+
+		case ODM_RATEMCS0:
+			reg_txagc = R_0x83c;
+			reg_mask = 0x0000007f;
+			break;
+		case ODM_RATEMCS1:
+			reg_txagc = R_0x83c;
+			reg_mask = 0x00007f00;
+			break;
+		case ODM_RATEMCS2:
+			reg_txagc = R_0x83c;
+			reg_mask = 0x007f0000;
+			break;
+		case ODM_RATEMCS3:
+			reg_txagc = R_0x83c;
+			reg_mask = 0x7f000000;
+			break;
+		case ODM_RATEMCS4:
+			reg_txagc = R_0x848;
+			reg_mask = 0x0000007f;
+			break;
+		case ODM_RATEMCS5:
+			reg_txagc = R_0x848;
+			reg_mask = 0x00007f00;
+			break;
+		case ODM_RATEMCS6:
+			reg_txagc = R_0x848;
+			reg_mask = 0x007f0000;
+			break;
+		case ODM_RATEMCS7:
+			reg_txagc = R_0x848;
+			reg_mask = 0x7f000000;
+			break;
+
+		case ODM_RATEMCS8:
+			reg_txagc = R_0x84c;
+			reg_mask = 0x0000007f;
+			break;
+		case ODM_RATEMCS9:
+			reg_txagc = R_0x84c;
+			reg_mask = 0x00007f00;
+			break;
+		case ODM_RATEMCS10:
+			reg_txagc = R_0x84c;
+			reg_mask = 0x007f0000;
+			break;
+		case ODM_RATEMCS11:
+			reg_txagc = R_0x84c;
+			reg_mask = 0x7f000000;
+			break;
+		case ODM_RATEMCS12:
+			reg_txagc = R_0x868;
+			reg_mask = 0x0000007f;
+			break;
+		case ODM_RATEMCS13:
+			reg_txagc = R_0x868;
+			reg_mask = 0x00007f00;
+			break;
+		case ODM_RATEMCS14:
+			reg_txagc = R_0x868;
+			reg_mask = 0x007f0000;
+			break;
+		case ODM_RATEMCS15:
+			reg_txagc = R_0x868;
+			reg_mask = 0x7f000000;
+			break;
+
+		default:
+			PHYDM_DBG(dm, ODM_PHY_CONFIG, "Invalid HWrate!\n");
+			break;
+		}
+	} else {
+		PHYDM_DBG(dm, ODM_PHY_CONFIG, "Invalid RF path!!\n");
+	}
+	read_back_data = (u8)odm_get_bb_reg(dm, reg_txagc, reg_mask);
+	PHYDM_DBG(dm, ODM_PHY_CONFIG, "%s: path-%d rate index 0x%x = 0x%x\n",
+		  __func__, path, hw_rate, read_back_data);
+	return read_back_data;
+}
+#endif
+
+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
+void phydm_normal_driver_rx_sniffer(
+	struct dm_struct *dm,
+	u8 *desc,
+	PRT_RFD_STATUS rt_rfd_status,
+	u8 *drv_info,
+	u8 phy_status)
+{
+#if (defined(CONFIG_PHYDM_RX_SNIFFER_PARSING))
+	u32 *msg;
+	u16 seq_num;
+
+	if (rt_rfd_status->packet_report_type != NORMAL_RX)
+		return;
+
+	if (!dm->is_linked) {
+		if (rt_rfd_status->is_hw_error)
+			return;
+	}
+
+	if (phy_status == true) {
+		if (dm->rx_pkt_type == type_block_ack ||
+		    dm->rx_pkt_type == type_rts || dm->rx_pkt_type == type_cts)
+			seq_num = 0;
+		else
+			seq_num = rt_rfd_status->seq_num;
+
+		PHYDM_DBG_F(dm, ODM_COMP_SNIFFER,
+			    "%04d , %01s, rate=0x%02x, L=%04d , %s , %s",
+			    seq_num,
+			    /*rt_rfd_status->mac_id,*/
+			    (rt_rfd_status->is_crc ? "C" :
+			    rt_rfd_status->is_ampdu ? "A" : "_"),
+			    rt_rfd_status->data_rate,
+			    rt_rfd_status->length,
+			    ((rt_rfd_status->band_width == 0) ? "20M" :
+			    ((rt_rfd_status->band_width == 1) ? "40M" : "80M")),
+			    (rt_rfd_status->is_ldpc ? "LDP" : "BCC"));
+
+		if (dm->rx_pkt_type == type_asoc_req)
+			PHYDM_DBG_F(dm, ODM_COMP_SNIFFER, " , [%s]", "AS_REQ");
+		else if (dm->rx_pkt_type == type_asoc_rsp)
+			PHYDM_DBG_F(dm, ODM_COMP_SNIFFER, " , [%s]", "AS_RSP");
+		else if (dm->rx_pkt_type == type_probe_req)
+			PHYDM_DBG_F(dm, ODM_COMP_SNIFFER, " , [%s]", "PR_REQ");
+		else if (dm->rx_pkt_type == type_probe_rsp)
+			PHYDM_DBG_F(dm, ODM_COMP_SNIFFER, " , [%s]", "PR_RSP");
+		else if (dm->rx_pkt_type == type_deauth)
+			PHYDM_DBG_F(dm, ODM_COMP_SNIFFER, " , [%s]", "DEAUTH");
+		else if (dm->rx_pkt_type == type_beacon)
+			PHYDM_DBG_F(dm, ODM_COMP_SNIFFER, " , [%s]", "BEACON");
+		else if (dm->rx_pkt_type == type_block_ack_req)
+			PHYDM_DBG_F(dm, ODM_COMP_SNIFFER, " , [%s]", "BA_REQ");
+		else if (dm->rx_pkt_type == type_rts)
+			PHYDM_DBG_F(dm, ODM_COMP_SNIFFER, " , [%s]", "__RTS_");
+		else if (dm->rx_pkt_type == type_cts)
+			PHYDM_DBG_F(dm, ODM_COMP_SNIFFER, " , [%s]", "__CTS_");
+		else if (dm->rx_pkt_type == type_ack)
+			PHYDM_DBG_F(dm, ODM_COMP_SNIFFER, " , [%s]", "__ACK_");
+		else if (dm->rx_pkt_type == type_block_ack)
+			PHYDM_DBG_F(dm, ODM_COMP_SNIFFER, " , [%s]", "__BA__");
+		else if (dm->rx_pkt_type == type_data)
+			PHYDM_DBG_F(dm, ODM_COMP_SNIFFER, " , [%s]", "_DATA_");
+		else if (dm->rx_pkt_type == type_data_ack)
+			PHYDM_DBG_F(dm, ODM_COMP_SNIFFER, " , [%s]", "Data_Ack");
+		else if (dm->rx_pkt_type == type_qos_data)
+			PHYDM_DBG_F(dm, ODM_COMP_SNIFFER, " , [%s]", "QoS_Data");
+		else
+			PHYDM_DBG_F(dm, ODM_COMP_SNIFFER, " , [0x%x]",
+				    dm->rx_pkt_type);
+
+		PHYDM_DBG_F(dm, ODM_COMP_SNIFFER, " , [RSSI=%d,%d,%d,%d ]",
+			    dm->rssi_a,
+			    dm->rssi_b,
+			    dm->rssi_c,
+			    dm->rssi_d);
+
+		msg = (u32 *)drv_info;
+
+		PHYDM_DBG_F(dm, ODM_COMP_SNIFFER,
+			    " , P-STS[28:0]=%08x-%08x-%08x-%08x-%08x-%08x-%08x\n",
+			    msg[6], msg[5], msg[4], msg[3],
+			    msg[2], msg[1], msg[1]);
+	} else {
+		PHYDM_DBG_F(dm, ODM_COMP_SNIFFER,
+			    "%04d , %01s, rate=0x%02x, L=%04d , %s , %s\n",
+			    rt_rfd_status->seq_num,
+			    /*rt_rfd_status->mac_id,*/
+			    (rt_rfd_status->is_crc ? "C" :
+			    (rt_rfd_status->is_ampdu) ? "A" : "_"),
+			    rt_rfd_status->data_rate,
+			    rt_rfd_status->length,
+			    ((rt_rfd_status->band_width == 0) ? "20M" :
+			    ((rt_rfd_status->band_width == 1) ? "40M" : "80M")),
+			    (rt_rfd_status->is_ldpc ? "LDP" : "BCC"));
+	}
+
+#endif
+}
+#endif
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/phydm_api.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/phydm_api.h
--- linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/phydm_api.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/phydm_api.h	2020-04-10 16:35:06.823660394 +0300
@@ -0,0 +1,168 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017  Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * The full GNU General Public License is included in this distribution in the
+ * file called LICENSE.
+ *
+ * Contact Information:
+ * wlanfae <wlanfae@realtek.com>
+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
+ * Hsinchu 300, Taiwan.
+ *
+ * Larry Finger <Larry.Finger@lwfinger.net>
+ *
+ *****************************************************************************/
+
+#ifndef __PHYDM_API_H__
+#define __PHYDM_API_H__
+
+#define PHYDM_API_VERSION "1.0" /* @2017.07.10  Dino, Add phydm_api.h*/
+
+/* @1 ============================================================
+ * 1  Definition
+ * 1 ============================================================
+ */
+#define CN_CNT_MAX 10 /*@max condition number threshold*/
+
+#define FUNC_ENABLE 1
+#define FUNC_DISABLE 2
+
+/*@NBI API------------------------------------*/
+#define NBI_128TONE 27 /*register table size*/
+#define NBI_256TONE 59 /*register table size*/
+
+#define NUM_START_CH_80M 7
+#define NUM_START_CH_40M 14
+
+#define CH_OFFSET_40M 2
+#define CH_OFFSET_80M 6
+
+#define FFT_128_TYPE 1
+#define FFT_256_TYPE 2
+
+#define FREQ_POSITIVE 1
+#define FREQ_NEGATIVE 2
+/*@------------------------------------------------*/
+
+#ifndef PHYDM_COMMON_API_SUPPORT
+#define INVALID_RF_DATA 0xffffffff
+#define INVALID_TXAGC_DATA 0xff
+#endif
+
+/* @1 ============================================================
+ * 1  structure
+ * 1 ============================================================
+ */
+
+struct phydm_api_stuc {
+	u32 rxiqc_reg1; /*N-mode: for pathA REG0xc14*/
+	u32 rxiqc_reg2; /*N-mode: for pathB REG0xc1c*/
+	u8 tx_queue_bitmap; /*REG0x520[23:16]*/
+};
+
+/* @1 ============================================================
+ * 1  enumeration
+ * 1 ============================================================
+ */
+
+/* @1 ============================================================
+ * 1  function prototype
+ * 1 ============================================================
+ */
+void phydm_reset_bb_hw_cnt_ac(void *dm_void);
+
+void phydm_dynamic_ant_weighting(void *dm_void);
+
+#ifdef DYN_ANT_WEIGHTING_SUPPORT
+void phydm_ant_weight_dbg(void *dm_void, char input[][16], u32 *_used,
+			  char *output, u32 *_out_len);
+#endif
+
+void phydm_pathb_q_matrix_rotate_en(void *dm_void);
+
+void phydm_pathb_q_matrix_rotate(void *dm_void, u16 phase_idx);
+
+void phydm_trx_antenna_setting_init(void *dm_void, u8 num_rf_path);
+
+void phydm_config_ofdm_rx_path(void *dm_void, u32 path);
+
+void phydm_config_cck_rx_path(void *dm_void, enum bb_path path);
+
+void phydm_config_cck_rx_antenna_init(void *dm_void);
+
+void phydm_config_trx_path(void *dm_void, char input[][16], u32 *_used,
+			   char *output, u32 *_out_len);
+
+void phydm_tx_2path(void *dm_void);
+
+void phydm_stop_3_wire(void *dm_void, u8 set_type);
+
+u8 phydm_stop_ic_trx(void *dm_void, u8 set_type);
+
+void phydm_set_ext_switch(void *dm_void, u32 ext_ant_switch);
+
+void phydm_nbi_enable(void *dm_void, u32 enable);
+
+u8 phydm_csi_mask_setting(void *dm_void, u32 enable, u32 ch, u32 bw, u32 f_intf,
+			  u32 sec_ch);
+
+u8 phydm_nbi_setting(void *dm_void, u32 enable, u32 ch, u32 bw, u32 f_intf,
+		     u32 sec_ch);
+
+void phydm_nbi_debug(void *dm_void, char input[][16], u32 *_used,
+		     char *output, u32 *_out_len);
+
+void phydm_csi_debug(void *dm_void, char input[][16], u32 *_used,
+		     char *output, u32 *_out_len);
+
+void phydm_stop_ck320(void *dm_void, u8 enable);
+
+boolean
+phydm_set_bb_txagc_offset(void *dm_void, s8 power_offset, u8 add_half_db);
+#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
+u8 phydm_csi_mask_setting_jgr3(void *dm_void, u32 enable, u32 ch, u32 bw,
+			       u32 f_intf, u32 sec_ch, u8 wgt);
+
+void phydm_set_csi_mask_jgr3(void *dm_void, u32 tone_idx_tmp, u8 tone_direction,
+			     u8 wgt);
+
+u8 phydm_nbi_setting_jgr3(void *dm_void, u32 enable, u32 ch, u32 bw, u32 f_intf,
+			  u32 sec_ch, u8 path);
+
+void phydm_set_nbi_reg_jgr3(void *dm_void, u32 tone_idx_tmp, u8 tone_direction,
+			    u8 path);
+
+void phydm_nbi_enable_jgr3(void *dm_void, u32 enable, u8 path);
+#endif
+
+#ifdef PHYDM_COMMON_API_SUPPORT
+boolean
+phydm_api_shift_txagc(void *dm_void, u32 pwr_offset, enum rf_path path,
+		      boolean is_positive);
+boolean
+phydm_api_set_txagc(void *dm_void, u32 power_index, enum rf_path path,
+		    u8 hw_rate, boolean is_single_rate);
+
+u8 phydm_api_get_txagc(void *dm_void, enum rf_path path, u8 hw_rate);
+
+boolean
+phydm_api_switch_bw_channel(void *dm_void, u8 central_ch, u8 primary_ch_idx,
+			    enum channel_width bandwidth);
+
+boolean
+phydm_api_trx_mode(void *dm_void, enum bb_path tx_path, enum bb_path rx_path,
+		   boolean is_tx2_path);
+
+#endif
+
+#endif
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/phydm_auto_dbg.c linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/phydm_auto_dbg.c
--- linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/phydm_auto_dbg.c	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/phydm_auto_dbg.c	2020-04-10 16:35:06.823660394 +0300
@@ -0,0 +1,671 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017  Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * The full GNU General Public License is included in this distribution in the
+ * file called LICENSE.
+ *
+ * Contact Information:
+ * wlanfae <wlanfae@realtek.com>
+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
+ * Hsinchu 300, Taiwan.
+ *
+ * Larry Finger <Larry.Finger@lwfinger.net>
+ *
+ *****************************************************************************/
+
+/*************************************************************
+ * include files
+ ************************************************************/
+
+#include "mp_precomp.h"
+#include "phydm_precomp.h"
+
+#ifdef PHYDM_AUTO_DEGBUG
+
+void phydm_check_hang_reset(
+	void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct phydm_auto_dbg_struct *atd_t = &dm->auto_dbg_table;
+
+	atd_t->dbg_step = 0;
+	atd_t->auto_dbg_type = AUTO_DBG_STOP;
+	phydm_pause_dm_watchdog(dm, PHYDM_RESUME);
+	dm->debug_components &= (~ODM_COMP_API);
+}
+
+void phydm_check_hang_init(
+	void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct phydm_auto_dbg_struct *atd_t = &dm->auto_dbg_table;
+
+	atd_t->dbg_step = 0;
+	atd_t->auto_dbg_type = AUTO_DBG_STOP;
+	phydm_pause_dm_watchdog(dm, PHYDM_RESUME);
+}
+
+#if (ODM_IC_11N_SERIES_SUPPORT == 1)
+void phydm_auto_check_hang_engine_n(
+	void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct phydm_auto_dbg_struct *atd_t = &dm->auto_dbg_table;
+	struct n_dbgport_803 dbgport_803 = {0};
+	u32 value32_tmp = 0, value32_tmp_2 = 0;
+	u8 i;
+	u32 curr_dbg_port_val[DBGPORT_CHK_NUM];
+	u16 curr_ofdm_t_cnt;
+	u16 curr_ofdm_r_cnt;
+	u16 curr_cck_t_cnt;
+	u16 curr_cck_r_cnt;
+	u16 curr_ofdm_crc_error_cnt;
+	u16 curr_cck_crc_error_cnt;
+	u16 diff_ofdm_t_cnt;
+	u16 diff_ofdm_r_cnt;
+	u16 diff_cck_t_cnt;
+	u16 diff_cck_r_cnt;
+	u16 diff_ofdm_crc_error_cnt;
+	u16 diff_cck_crc_error_cnt;
+	u8 rf_mode;
+
+	if (atd_t->auto_dbg_type == AUTO_DBG_STOP)
+		return;
+
+	if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
+		phydm_check_hang_reset(dm);
+		return;
+	}
+
+	if (atd_t->dbg_step == 0) {
+		pr_debug("dbg_step=0\n\n");
+
+		/*Reset all packet counter*/
+		odm_set_bb_reg(dm, R_0xf14, BIT(16), 1);
+		odm_set_bb_reg(dm, R_0xf14, BIT(16), 0);
+
+	} else if (atd_t->dbg_step == 1) {
+		pr_debug("dbg_step=1\n\n");
+
+		/*Check packet counter Register*/
+		atd_t->ofdm_t_cnt = (u16)odm_get_bb_reg(dm, R_0x9cc, MASKHWORD);
+		atd_t->ofdm_r_cnt = (u16)odm_get_bb_reg(dm, R_0xf94, MASKLWORD);
+		atd_t->ofdm_crc_error_cnt = (u16)odm_get_bb_reg(dm, R_0xf94,
+								MASKHWORD);
+
+		atd_t->cck_t_cnt = (u16)odm_get_bb_reg(dm, R_0x9d0, MASKHWORD);
+		atd_t->cck_r_cnt = (u16)odm_get_bb_reg(dm, R_0xfa0, MASKHWORD);
+		atd_t->cck_crc_error_cnt = (u16)odm_get_bb_reg(dm, R_0xf84,
+							       0x3fff);
+
+		/*Check Debug Port*/
+		for (i = 0; i < DBGPORT_CHK_NUM; i++) {
+			if (phydm_set_bb_dbg_port(dm, DBGPORT_PRI_3,
+						  (u32)atd_t->dbg_port_table[i])
+						  ) {
+				atd_t->dbg_port_val[i] =
+					phydm_get_bb_dbg_port_val(dm);
+				phydm_release_bb_dbg_port(dm);
+			}
+		}
+
+	} else if (atd_t->dbg_step == 2) {
+		pr_debug("dbg_step=2\n\n");
+
+		/*Check packet counter Register*/
+		curr_ofdm_t_cnt = (u16)odm_get_bb_reg(dm, R_0x9cc, MASKHWORD);
+		curr_ofdm_r_cnt = (u16)odm_get_bb_reg(dm, R_0xf94, MASKLWORD);
+		curr_ofdm_crc_error_cnt = (u16)odm_get_bb_reg(dm, R_0xf94,
+							      MASKHWORD);
+
+		curr_cck_t_cnt = (u16)odm_get_bb_reg(dm, R_0x9d0, MASKHWORD);
+		curr_cck_r_cnt = (u16)odm_get_bb_reg(dm, R_0xfa0, MASKHWORD);
+		curr_cck_crc_error_cnt = (u16)odm_get_bb_reg(dm, R_0xf84,
+							     0x3fff);
+
+		/*Check Debug Port*/
+		for (i = 0; i < DBGPORT_CHK_NUM; i++) {
+			if (phydm_set_bb_dbg_port(dm, DBGPORT_PRI_3,
+						  (u32)atd_t->dbg_port_table[i])
+						  ) {
+				curr_dbg_port_val[i] =
+					phydm_get_bb_dbg_port_val(dm);
+				phydm_release_bb_dbg_port(dm);
+			}
+		}
+
+		/*=== Make check hang decision ===============================*/
+		pr_debug("Check Hang Decision\n\n");
+
+		/* ----- Check RF Register -----------------------------------*/
+		for (i = 0; i < dm->num_rf_path; i++) {
+			rf_mode = (u8)odm_get_rf_reg(dm, i, RF_0x0, 0xf0000);
+			pr_debug("RF0x0[%d] = 0x%x\n", i, rf_mode);
+			if (rf_mode > 3) {
+				pr_debug("Incorrect RF mode\n");
+				pr_debug("ReasonCode:RHN-1\n");
+			}
+		}
+		value32_tmp = odm_get_rf_reg(dm, 0, RF_0xb0, 0xf0000);
+		if (dm->support_ic_type == ODM_RTL8188E) {
+			if (value32_tmp != 0xff8c8) {
+				pr_debug("ReasonCode:RHN-3\n");
+			}
+		}
+		/* ----- Check BB Register ----------------------------------*/
+		/*BB mode table*/
+		value32_tmp = odm_get_bb_reg(dm, R_0x824, 0xe);
+		value32_tmp_2 = odm_get_bb_reg(dm, R_0x82c, 0xe);
+		pr_debug("BB TX mode table {A, B}= {%d, %d}\n",
+			 value32_tmp, value32_tmp_2);
+
+		if (value32_tmp > 3 || value32_tmp_2 > 3) {
+			pr_debug("ReasonCode:RHN-2\n");
+		}
+
+		value32_tmp = odm_get_bb_reg(dm, R_0x824, 0x700000);
+		value32_tmp_2 = odm_get_bb_reg(dm, R_0x82c, 0x700000);
+		pr_debug("BB RX mode table {A, B}= {%d, %d}\n", value32_tmp,
+			 value32_tmp_2);
+
+		if (value32_tmp > 3 || value32_tmp_2 > 3) {
+			pr_debug("ReasonCode:RHN-2\n");
+		}
+
+		/*BB HW Block*/
+		value32_tmp = odm_get_bb_reg(dm, R_0x800, MASKDWORD);
+
+		if (!(value32_tmp & BIT(24))) {
+			pr_debug("Reg0x800[24] = 0, CCK BLK is disabled\n");
+			pr_debug("ReasonCode: THN-3\n");
+		}
+
+		if (!(value32_tmp & BIT(25))) {
+			pr_debug("Reg0x800[24] = 0, OFDM BLK is disabled\n");
+			pr_debug("ReasonCode:THN-3\n");
+		}
+
+		/*BB Continue TX*/
+		value32_tmp = odm_get_bb_reg(dm, R_0xd00, 0x70000000);
+		pr_debug("Continue TX=%d\n", value32_tmp);
+		if (value32_tmp != 0) {
+			pr_debug("ReasonCode: THN-4\n");
+		}
+
+		/* ----- Check Packet Counter --------------------------------*/
+		diff_ofdm_t_cnt = curr_ofdm_t_cnt - atd_t->ofdm_t_cnt;
+		diff_ofdm_r_cnt = curr_ofdm_r_cnt - atd_t->ofdm_r_cnt;
+		diff_ofdm_crc_error_cnt = curr_ofdm_crc_error_cnt -
+					  atd_t->ofdm_crc_error_cnt;
+
+		diff_cck_t_cnt = curr_cck_t_cnt - atd_t->cck_t_cnt;
+		diff_cck_r_cnt = curr_cck_r_cnt - atd_t->cck_r_cnt;
+		diff_cck_crc_error_cnt = curr_cck_crc_error_cnt -
+					 atd_t->cck_crc_error_cnt;
+
+		pr_debug("OFDM[t=0~1] {TX, RX, CRC_error} = {%d, %d, %d}\n",
+			 atd_t->ofdm_t_cnt, atd_t->ofdm_r_cnt,
+			 atd_t->ofdm_crc_error_cnt);
+		pr_debug("OFDM[t=1~2] {TX, RX, CRC_error} = {%d, %d, %d}\n",
+			 curr_ofdm_t_cnt, curr_ofdm_r_cnt,
+			 curr_ofdm_crc_error_cnt);
+		pr_debug("OFDM_diff {TX, RX, CRC_error} = {%d, %d, %d}\n",
+			 diff_ofdm_t_cnt, diff_ofdm_r_cnt,
+			 diff_ofdm_crc_error_cnt);
+
+		pr_debug("CCK[t=0~1] {TX, RX, CRC_error} = {%d, %d, %d}\n",
+			 atd_t->cck_t_cnt, atd_t->cck_r_cnt,
+			 atd_t->cck_crc_error_cnt);
+		pr_debug("CCK[t=1~2] {TX, RX, CRC_error} = {%d, %d, %d}\n",
+			 curr_cck_t_cnt, curr_cck_r_cnt,
+			 curr_cck_crc_error_cnt);
+		pr_debug("CCK_diff {TX, RX, CRC_error} = {%d, %d, %d}\n",
+			 diff_cck_t_cnt, diff_cck_r_cnt,
+			 diff_cck_crc_error_cnt);
+
+		/* ----- Check Dbg Port --------------------------------*/
+
+		for (i = 0; i < DBGPORT_CHK_NUM; i++) {
+			pr_debug("Dbg_port=((0x%x))\n",
+				 atd_t->dbg_port_table[i]);
+			pr_debug("Val{pre, curr}={0x%x, 0x%x}\n",
+				 atd_t->dbg_port_val[i], curr_dbg_port_val[i]);
+
+			if (atd_t->dbg_port_table[i] == 0) {
+				if (atd_t->dbg_port_val[i] ==
+				    curr_dbg_port_val[i]) {
+					pr_debug("BB state hang\n");
+					pr_debug("ReasonCode:\n");
+				}
+
+			} else if (atd_t->dbg_port_table[i] == 0x803) {
+				if (atd_t->dbg_port_val[i] ==
+				    curr_dbg_port_val[i]) {
+					/* dbgport_803 =  */
+					/* (struct n_dbgport_803 )   */
+					/* (atd_t->dbg_port_val[i]); */
+					odm_move_memory(dm, &dbgport_803,
+							&atd_t->dbg_port_val[i],
+							sizeof(struct n_dbgport_803));
+					pr_debug("RSTB{BB, GLB, OFDM}={%d, %d,%d}\n",
+						 dbgport_803.bb_rst_b,
+						 dbgport_803.glb_rst_b,
+						 dbgport_803.ofdm_rst_b);
+					pr_debug("{ofdm_tx_en, cck_tx_en, phy_tx_on}={%d, %d, %d}\n",
+						 dbgport_803.ofdm_tx_en,
+						 dbgport_803.cck_tx_en,
+						 dbgport_803.phy_tx_on);
+					pr_debug("CCA_PP{OFDM, CCK}={%d, %d}\n",
+						 dbgport_803.ofdm_cca_pp,
+						 dbgport_803.cck_cca_pp);
+
+					if (dbgport_803.phy_tx_on)
+						pr_debug("Maybe TX Hang\n");
+					else if (dbgport_803.ofdm_cca_pp ||
+						 dbgport_803.cck_cca_pp)
+						pr_debug("Maybe RX Hang\n");
+				}
+
+			} else if (atd_t->dbg_port_table[i] == 0x208) {
+				if ((atd_t->dbg_port_val[i] & BIT(30)) &&
+				    (curr_dbg_port_val[i] & BIT(30))) {
+					pr_debug("EDCCA Pause TX\n");
+					pr_debug("ReasonCode: THN-2\n");
+				}
+
+			} else if (atd_t->dbg_port_table[i] == 0xab0) {
+				/* atd_t->dbg_port_val[i] & 0xffffff == 0 */
+				/* curr_dbg_port_val[i] & 0xffffff == 0 */
+				if (((atd_t->dbg_port_val[i] &
+				      MASK24BITS) == 0) ||
+				    ((curr_dbg_port_val[i] &
+				      MASK24BITS) == 0)) {
+					pr_debug("Wrong L-SIG formate\n");
+					pr_debug("ReasonCode: THN-1\n");
+				}
+			}
+		}
+
+		phydm_check_hang_reset(dm);
+	}
+
+	atd_t->dbg_step++;
+}
+
+void phydm_bb_auto_check_hang_start_n(
+	void *dm_void,
+	u32 *_used,
+	char *output,
+	u32 *_out_len)
+{
+	u32 value32 = 0;
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct phydm_auto_dbg_struct *atd_t = &dm->auto_dbg_table;
+	u32 used = *_used;
+	u32 out_len = *_out_len;
+
+	if (dm->support_ic_type & ODM_IC_11AC_SERIES)
+		return;
+
+	PDM_SNPF(out_len, used, output + used, out_len - used,
+		 "PHYDM auto check hang (N-series) is started, Please check the system log\n");
+
+	dm->debug_components |= ODM_COMP_API;
+	atd_t->auto_dbg_type = AUTO_DBG_CHECK_HANG;
+	atd_t->dbg_step = 0;
+
+	phydm_pause_dm_watchdog(dm, PHYDM_PAUSE);
+
+	*_used = used;
+	*_out_len = out_len;
+}
+
+void phydm_bb_rx_hang_info_n(
+	void *dm_void,
+	u32 *_used,
+	char *output,
+	u32 *_out_len)
+{
+	u32 value32 = 0;
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	u32 used = *_used;
+	u32 out_len = *_out_len;
+
+	if (dm->support_ic_type & ODM_IC_11AC_SERIES)
+		return;
+
+	PDM_SNPF(out_len, used, output + used, out_len - used,
+		 "not support now\n");
+
+	*_used = used;
+	*_out_len = out_len;
+}
+
+#endif
+
+#if (ODM_IC_11AC_SERIES_SUPPORT == 1)
+void phydm_bb_rx_hang_info_ac(
+	void *dm_void,
+	u32 *_used,
+	char *output,
+	u32 *_out_len)
+{
+	u32 value32 = 0;
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	u32 used = *_used;
+	u32 out_len = *_out_len;
+
+	if (dm->support_ic_type & ODM_IC_11N_SERIES)
+		return;
+
+	value32 = odm_get_bb_reg(dm, R_0xf80, MASKDWORD);
+	PDM_SNPF(out_len, used, output + used, out_len - used,
+		 "\r\n %-35s = 0x%x", "rptreg of sc/bw/ht/...", value32);
+
+	if (dm->support_ic_type & ODM_RTL8822B)
+		odm_set_bb_reg(dm, R_0x198c, BIT(2) | BIT(1) | BIT(0), 7);
+
+	/* dbg_port = basic state machine */
+	{
+		odm_set_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD, 0x000);
+		value32 = odm_get_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD);
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "\r\n %-35s = 0x%x", "0x8fc", value32);
+
+		value32 = odm_get_bb_reg(dm, ODM_REG_RPT_11AC, MASKDWORD);
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "\r\n %-35s = 0x%x", "basic state machine", value32);
+	}
+
+	/* dbg_port = state machine */
+	{
+		odm_set_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD, 0x007);
+		value32 = odm_get_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD);
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "\r\n %-35s = 0x%x", "0x8fc", value32);
+
+		value32 = odm_get_bb_reg(dm, ODM_REG_RPT_11AC, MASKDWORD);
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "\r\n %-35s = 0x%x", "state machine", value32);
+	}
+
+	/* dbg_port = CCA-related*/
+	{
+		odm_set_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD, 0x204);
+		value32 = odm_get_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD);
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "\r\n %-35s = 0x%x", "0x8fc", value32);
+
+		value32 = odm_get_bb_reg(dm, ODM_REG_RPT_11AC, MASKDWORD);
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "\r\n %-35s = 0x%x", "CCA-related", value32);
+	}
+
+	/* dbg_port = edcca/rxd*/
+	{
+		odm_set_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD, 0x278);
+		value32 = odm_get_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD);
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "\r\n %-35s = 0x%x", "0x8fc", value32);
+
+		value32 = odm_get_bb_reg(dm, ODM_REG_RPT_11AC, MASKDWORD);
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "\r\n %-35s = 0x%x", "edcca/rxd", value32);
+	}
+
+	/* dbg_port = rx_state/mux_state/ADC_MASK_OFDM*/
+	{
+		odm_set_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD, 0x290);
+		value32 = odm_get_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD);
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "\r\n %-35s = 0x%x", "0x8fc", value32);
+
+		value32 = odm_get_bb_reg(dm, ODM_REG_RPT_11AC, MASKDWORD);
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "\r\n %-35s = 0x%x",
+			 "rx_state/mux_state/ADC_MASK_OFDM", value32);
+	}
+
+	/* dbg_port = bf-related*/
+	{
+		odm_set_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD, 0x2B2);
+		value32 = odm_get_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD);
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "\r\n %-35s = 0x%x", "0x8fc", value32);
+
+		value32 = odm_get_bb_reg(dm, ODM_REG_RPT_11AC, MASKDWORD);
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "\r\n %-35s = 0x%x", "bf-related", value32);
+	}
+
+	/* dbg_port = bf-related*/
+	{
+		odm_set_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD, 0x2B8);
+		value32 = odm_get_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD);
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "\r\n %-35s = 0x%x", "0x8fc", value32);
+
+		value32 = odm_get_bb_reg(dm, ODM_REG_RPT_11AC, MASKDWORD);
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "\r\n %-35s = 0x%x", "bf-related", value32);
+	}
+
+	/* dbg_port = txon/rxd*/
+	{
+		odm_set_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD, 0xA03);
+		value32 = odm_get_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD);
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "\r\n %-35s = 0x%x", "0x8fc", value32);
+
+		value32 = odm_get_bb_reg(dm, ODM_REG_RPT_11AC, MASKDWORD);
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "\r\n %-35s = 0x%x", "txon/rxd", value32);
+	}
+
+	/* dbg_port = l_rate/l_length*/
+	{
+		odm_set_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD, 0xA0B);
+		value32 = odm_get_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD);
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "\r\n %-35s = 0x%x", "0x8fc", value32);
+
+		value32 = odm_get_bb_reg(dm, ODM_REG_RPT_11AC, MASKDWORD);
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "\r\n %-35s = 0x%x", "l_rate/l_length", value32);
+	}
+
+	/* dbg_port = rxd/rxd_hit*/
+	{
+		odm_set_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD, 0xA0D);
+		value32 = odm_get_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD);
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "\r\n %-35s = 0x%x", "0x8fc", value32);
+
+		value32 = odm_get_bb_reg(dm, ODM_REG_RPT_11AC, MASKDWORD);
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "\r\n %-35s = 0x%x", "rxd/rxd_hit", value32);
+	}
+
+	/* dbg_port = dis_cca*/
+	{
+		odm_set_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD, 0xAA0);
+		value32 = odm_get_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD);
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "\r\n %-35s = 0x%x", "0x8fc", value32);
+
+		value32 = odm_get_bb_reg(dm, ODM_REG_RPT_11AC, MASKDWORD);
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "\r\n %-35s = 0x%x", "dis_cca", value32);
+	}
+
+	/* dbg_port = tx*/
+	{
+		odm_set_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD, 0xAB0);
+		value32 = odm_get_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD);
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "\r\n %-35s = 0x%x", "0x8fc", value32);
+
+		value32 = odm_get_bb_reg(dm, ODM_REG_RPT_11AC, MASKDWORD);
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "\r\n %-35s = 0x%x", "tx", value32);
+	}
+
+	/* dbg_port = rx plcp*/
+	{
+		odm_set_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD, 0xAD0);
+		value32 = odm_get_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD);
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "\r\n %-35s = 0x%x", "0x8fc", value32);
+
+		value32 = odm_get_bb_reg(dm, ODM_REG_RPT_11AC, MASKDWORD);
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "\r\n %-35s = 0x%x", "rx plcp", value32);
+
+		odm_set_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD, 0xAD1);
+		value32 = odm_get_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD);
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "\r\n %-35s = 0x%x", "0x8fc", value32);
+
+		value32 = odm_get_bb_reg(dm, ODM_REG_RPT_11AC, MASKDWORD);
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "\r\n %-35s = 0x%x", "rx plcp", value32);
+
+		odm_set_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD, 0xAD2);
+		value32 = odm_get_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD);
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "\r\n %-35s = 0x%x", "0x8fc", value32);
+
+		value32 = odm_get_bb_reg(dm, ODM_REG_RPT_11AC, MASKDWORD);
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "\r\n %-35s = 0x%x", "rx plcp", value32);
+
+		odm_set_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD, 0xAD3);
+		value32 = odm_get_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD);
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "\r\n %-35s = 0x%x", "0x8fc", value32);
+
+		value32 = odm_get_bb_reg(dm, ODM_REG_RPT_11AC, MASKDWORD);
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "\r\n %-35s = 0x%x", "rx plcp", value32);
+	}
+	*_used = used;
+	*_out_len = out_len;
+}
+#endif
+
+void phydm_auto_dbg_console(
+	void *dm_void,
+	char input[][16],
+	u32 *_used,
+	char *output,
+	u32 *_out_len)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	char help[] = "-h";
+	u32 var1[10] = {0};
+	u32 used = *_used;
+	u32 out_len = *_out_len;
+
+	PHYDM_SSCANF(input[1], DCMD_DECIMAL, &var1[0]);
+
+	if ((strcmp(input[1], help) == 0)) {
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "Show dbg port: {1} {1}\n");
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "Auto check hang: {1} {2}\n");
+		return;
+	} else if (var1[0] == 1) {
+		PHYDM_SSCANF(input[2], DCMD_DECIMAL, &var1[1]);
+
+		if (var1[1] == 1) {
+			if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
+				#if (ODM_IC_11AC_SERIES_SUPPORT == 1)
+				phydm_bb_rx_hang_info_ac(dm, &used, output,
+							 &out_len);
+				#else
+				PDM_SNPF(out_len, used, output + used,
+					 out_len - used, "Not support\n");
+				#endif
+			} else {
+				#if (ODM_IC_11N_SERIES_SUPPORT == 1)
+				phydm_bb_rx_hang_info_n(dm, &used, output,
+							&out_len);
+				#else
+				PDM_SNPF(out_len, used, output + used,
+					 out_len - used, "Not support\n");
+				#endif
+			}
+		} else if (var1[1] == 2) {
+			if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
+				PDM_SNPF(out_len, used, output + used,
+					 out_len - used, "Not support\n");
+			} else {
+				#if (ODM_IC_11N_SERIES_SUPPORT == 1)
+				phydm_bb_auto_check_hang_start_n(dm, &used,
+								 output,
+								 &out_len);
+				#else
+				PDM_SNPF(out_len, used, output + used,
+					 out_len - used, "Not support\n");
+				#endif
+			}
+		}
+	}
+
+	*_used = used;
+	*_out_len = out_len;
+}
+
+void phydm_auto_dbg_engine(void *dm_void)
+{
+	u32 value32 = 0;
+
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct phydm_auto_dbg_struct *atd_t = &dm->auto_dbg_table;
+
+	if (atd_t->auto_dbg_type == AUTO_DBG_STOP)
+		return;
+
+	pr_debug("%s ======>\n", __func__);
+
+	if (atd_t->auto_dbg_type == AUTO_DBG_CHECK_HANG) {
+		if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
+			pr_debug("Not Support\n");
+		} else {
+			#if (ODM_IC_11N_SERIES_SUPPORT == 1)
+			phydm_auto_check_hang_engine_n(dm);
+			#else
+			pr_debug("Not Support\n");
+			#endif
+		}
+
+	} else if (atd_t->auto_dbg_type == AUTO_DBG_CHECK_RA) {
+		pr_debug("Not Support\n");
+	}
+}
+
+void phydm_auto_dbg_engine_init(void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct phydm_auto_dbg_struct *atd_t = &dm->auto_dbg_table;
+	u16 dbg_port_table[DBGPORT_CHK_NUM] = {0x0, 0x803, 0x208, 0xab0,
+					       0xab1, 0xab2};
+
+	PHYDM_DBG(dm, ODM_COMP_API, "%s ======>n", __func__);
+
+	odm_move_memory(dm, &atd_t->dbg_port_table[0],
+			&dbg_port_table[0], (DBGPORT_CHK_NUM * 2));
+
+	phydm_check_hang_init(dm);
+}
+#endif
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/phydm_auto_dbg.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/phydm_auto_dbg.h
--- linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/phydm_auto_dbg.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/phydm_auto_dbg.h	2020-04-10 16:35:06.823660394 +0300
@@ -0,0 +1,113 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017  Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * The full GNU General Public License is included in this distribution in the
+ * file called LICENSE.
+ *
+ * Contact Information:
+ * wlanfae <wlanfae@realtek.com>
+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
+ * Hsinchu 300, Taiwan.
+ *
+ * Larry Finger <Larry.Finger@lwfinger.net>
+ *
+ *****************************************************************************/
+
+#ifndef __PHYDM_AUTO_DBG_H__
+#define __PHYDM_AUTO_DBG_H__
+
+#define AUTO_DBG_VERSION "1.0" /* @2017.05.015  Dino, Add phydm_auto_dbg.h*/
+
+/* @1 ============================================================
+ * 1  Definition
+ * 1 ============================================================
+ */
+
+#define AUTO_CHK_HANG_STEP_MAX 3
+#define DBGPORT_CHK_NUM 6
+
+#ifdef PHYDM_AUTO_DEGBUG
+
+/* @1 ============================================================
+ * 1  enumeration
+ * 1 ============================================================
+ */
+
+enum auto_dbg_type_e {
+	AUTO_DBG_STOP		= 0,
+	AUTO_DBG_CHECK_HANG	= 1,
+	AUTO_DBG_CHECK_RA	= 2,
+	AUTO_DBG_CHECK_DIG	= 3
+};
+
+/* @1 ============================================================
+ * 1  structure
+ * 1 ============================================================
+ */
+
+struct n_dbgport_803 {
+	/*@BYTE 3*/
+	u8 bb_rst_b : 1;
+	u8 glb_rst_b : 1;
+	u8 zero_1bit_1 : 1;
+	u8 ofdm_rst_b : 1;
+	u8 cck_txpe : 1;
+	u8 ofdm_txpe : 1;
+	u8 phy_tx_on : 1;
+	u8 tdrdy : 1;
+	/*@BYTE 2*/
+	u8 txd : 8;
+	/*@BYTE 1*/
+	u8 cck_cca_pp : 1;
+	u8 ofdm_cca_pp : 1;
+	u8 rx_rst : 1;
+	u8 rdrdy : 1;
+	u8 rxd_7_4 : 4;
+	/*@BYTE 0*/
+	u8 rxd_3_0 : 4;
+	u8 ofdm_tx_en : 1;
+	u8 cck_tx_en : 1;
+	u8 zero_1bit_2 : 1;
+	u8 clk_80m : 1;
+};
+
+struct phydm_auto_dbg_struct {
+	enum auto_dbg_type_e auto_dbg_type;
+	u8 dbg_step;
+	u16 dbg_port_table[DBGPORT_CHK_NUM];
+	u32 dbg_port_val[DBGPORT_CHK_NUM];
+	u16 ofdm_t_cnt;
+	u16 ofdm_r_cnt;
+	u16 cck_t_cnt;
+	u16 cck_r_cnt;
+	u16 ofdm_crc_error_cnt;
+	u16 cck_crc_error_cnt;
+};
+
+/* @1 ============================================================
+ * 1  function prototype
+ * 1 ============================================================
+ */
+
+void phydm_auto_dbg_console(
+	void *dm_void,
+	char input[][16],
+	u32 *_used,
+	char *output,
+	u32 *_out_len);
+
+void phydm_auto_dbg_engine(void *dm_void);
+
+void phydm_auto_dbg_engine_init(void *dm_void);
+#endif
+#endif
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/phydm_beamforming.c linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/phydm_beamforming.c
--- linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/phydm_beamforming.c	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/phydm_beamforming.c	2020-04-10 16:35:06.823660394 +0300
@@ -0,0 +1,2054 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017  Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * The full GNU General Public License is included in this distribution in the
+ * file called LICENSE.
+ *
+ * Contact Information:
+ * wlanfae <wlanfae@realtek.com>
+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
+ * Hsinchu 300, Taiwan.
+ *
+ * Larry Finger <Larry.Finger@lwfinger.net>
+ *
+ *****************************************************************************/
+
+#include "mp_precomp.h"
+#include "phydm_precomp.h"
+
+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
+	#if WPP_SOFTWARE_TRACE
+		#include "phydm_beamforming.tmh"
+	#endif
+#endif
+
+#if (BEAMFORMING_SUPPORT == 1)
+
+void phydm_get_txbf_device_num(
+	void *dm_void,
+	u8 macid)
+{
+#if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY)) /*@For BDC*/
+#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
+
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct cmn_sta_info *sta = dm->phydm_sta_info[macid];
+	struct bf_cmn_info *bf = NULL;
+	struct _BF_DIV_COEX_ *dm_bdc_table = &dm->dm_bdc_table;
+	u8 act_as_bfer = 0;
+	u8 act_as_bfee = 0;
+
+	if (is_sta_active(sta)) {
+		bf = &(sta->bf_info);
+	} else {
+		PHYDM_DBG(dm, DBG_TXBF, "[Warning] %s invalid sta_info\n",
+			  __func__);
+		return;
+	}
+
+	if (sta->support_wireless_set & WIRELESS_VHT) {
+		if (bf->vht_beamform_cap & BEAMFORMING_VHT_BEAMFORMEE_ENABLE)
+			act_as_bfer = 1;
+
+		if (bf->vht_beamform_cap & BEAMFORMING_VHT_BEAMFORMER_ENABLE)
+			act_as_bfee = 1;
+
+	} else if (sta->support_wireless_set & WIRELESS_HT) {
+		if (bf->ht_beamform_cap & BEAMFORMING_HT_BEAMFORMEE_ENABLE)
+			act_as_bfer = 1;
+
+		if (bf->ht_beamform_cap & BEAMFORMING_HT_BEAMFORMER_ENABLE)
+			act_as_bfee = 1;
+	}
+
+	if (act_as_bfer))
+		{ /* Our Device act as BFer */
+			dm_bdc_table->w_bfee_client[macid] = true;
+			dm_bdc_table->num_txbfee_client++;
+		}
+	else
+		dm_bdc_table->w_bfee_client[macid] = false;
+
+	if (act_as_bfee))
+		{ /* Our Device act as BFee */
+			dm_bdc_table->w_bfer_client[macid] = true;
+			dm_bdc_table->num_txbfer_client++;
+		}
+	else
+		dm_bdc_table->w_bfer_client[macid] = false;
+
+#endif
+#endif
+}
+
+struct _RT_BEAMFORM_STAINFO *
+phydm_sta_info_init(
+	struct dm_struct *dm,
+	u16 sta_idx)
+{
+	struct _RT_BEAMFORMING_INFO *beam_info = &dm->beamforming_info;
+	struct _RT_BEAMFORM_STAINFO *entry = &beam_info->beamform_sta_info;
+	struct sta_info *sta = dm->odm_sta_info[sta_idx];
+	struct cmn_sta_info *cmn_sta = dm->phydm_sta_info[sta_idx];
+	//void					*adapter = dm->adapter;
+	ADAPTER * adapter = dm->adapter;
+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
+	PMGNT_INFO p_MgntInfo = &((adapter)->MgntInfo);
+	PRT_HIGH_THROUGHPUT p_ht_info = GET_HT_INFO(p_MgntInfo);
+	PRT_VERY_HIGH_THROUGHPUT p_vht_info = GET_VHT_INFO(p_MgntInfo);
+#endif
+
+	if (!is_sta_active(cmn_sta)) {
+		PHYDM_DBG(dm, DBG_TXBF, "%s => sta_info(mac_id:%d) failed\n",
+			  __func__, sta_idx);
+		#if (DM_ODM_SUPPORT_TYPE == ODM_CE)
+		rtw_warn_on(1);
+		#endif
+
+		return entry;
+	}
+
+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
+	odm_move_memory(dm, (PVOID)(entry->my_mac_addr), (PVOID)(adapter->CurrentAddress), 6);
+#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
+	odm_move_memory(dm, entry->my_mac_addr, adapter_mac_addr(sta->padapter), 6);
+#endif
+
+	entry->aid = cmn_sta->aid;
+	entry->ra = cmn_sta->mac_addr;
+	entry->mac_id = cmn_sta->mac_id;
+	entry->bw = cmn_sta->bw_mode;
+	entry->cur_beamform = cmn_sta->bf_info.ht_beamform_cap;
+	entry->ht_beamform_cap = cmn_sta->bf_info.ht_beamform_cap;
+
+#if ODM_IC_11AC_SERIES_SUPPORT
+	if (cmn_sta->support_wireless_set & WIRELESS_VHT) {
+		entry->cur_beamform_vht = cmn_sta->bf_info.vht_beamform_cap;
+		entry->vht_beamform_cap = cmn_sta->bf_info.vht_beamform_cap;
+	}
+#endif
+
+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) /*To Be Removed */
+	entry->ht_beamform_cap = p_ht_info->HtBeamformCap; /*To Be Removed*/
+	entry->vht_beamform_cap = p_vht_info->VhtBeamformCap; /*To Be Removed*/
+
+	if (sta_idx == 0) { /*@client mode*/
+		#if ODM_IC_11AC_SERIES_SUPPORT
+		if (cmn_sta->support_wireless_set & WIRELESS_VHT)
+			entry->cur_beamform_vht = p_vht_info->VhtCurBeamform;
+		#endif
+	}
+#endif
+
+	PHYDM_DBG(dm, DBG_TXBF, "wireless_set = 0x%x, staidx = %d\n",
+		  cmn_sta->support_wireless_set, sta_idx);
+	PHYDM_DBG(dm, DBG_TXBF,
+		  "entry->cur_beamform = 0x%x, entry->cur_beamform_vht = 0x%x\n",
+		  entry->cur_beamform, entry->cur_beamform_vht);
+	return entry;
+}
+void phydm_sta_info_update(
+	struct dm_struct *dm,
+	u16 sta_idx,
+	struct _RT_BEAMFORMEE_ENTRY *beamform_entry)
+{
+	struct cmn_sta_info *sta = dm->phydm_sta_info[sta_idx];
+
+	if (!is_sta_active(sta))
+		return;
+
+	sta->bf_info.p_aid = beamform_entry->p_aid;
+	sta->bf_info.g_id = beamform_entry->g_id;
+}
+
+struct _RT_BEAMFORMEE_ENTRY *
+phydm_beamforming_get_bfee_entry_by_addr(
+	void *dm_void,
+	u8 *RA,
+	u8 *idx)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	u8 i = 0;
+	struct _RT_BEAMFORMING_INFO *beam_info = &dm->beamforming_info;
+
+	for (i = 0; i < BEAMFORMEE_ENTRY_NUM; i++) {
+		if (beam_info->beamformee_entry[i].is_used && (eq_mac_addr(RA, beam_info->beamformee_entry[i].mac_addr))) {
+			*idx = i;
+			return &beam_info->beamformee_entry[i];
+		}
+	}
+
+	return NULL;
+}
+
+struct _RT_BEAMFORMER_ENTRY *
+phydm_beamforming_get_bfer_entry_by_addr(
+	void *dm_void,
+	u8 *TA,
+	u8 *idx)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	u8 i = 0;
+	struct _RT_BEAMFORMING_INFO *beam_info = &dm->beamforming_info;
+
+	for (i = 0; i < BEAMFORMER_ENTRY_NUM; i++) {
+		if (beam_info->beamformer_entry[i].is_used && (eq_mac_addr(TA, beam_info->beamformer_entry[i].mac_addr))) {
+			*idx = i;
+			return &beam_info->beamformer_entry[i];
+		}
+	}
+
+	return NULL;
+}
+
+struct _RT_BEAMFORMEE_ENTRY *
+phydm_beamforming_get_entry_by_mac_id(
+	void *dm_void,
+	u8 mac_id,
+	u8 *idx)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	u8 i = 0;
+	struct _RT_BEAMFORMING_INFO *beam_info = &dm->beamforming_info;
+
+	for (i = 0; i < BEAMFORMEE_ENTRY_NUM; i++) {
+		if (beam_info->beamformee_entry[i].is_used && mac_id == beam_info->beamformee_entry[i].mac_id) {
+			*idx = i;
+			return &beam_info->beamformee_entry[i];
+		}
+	}
+
+	return NULL;
+}
+
+enum beamforming_cap
+phydm_beamforming_get_entry_beam_cap_by_mac_id(
+	void *dm_void,
+	u8 mac_id)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	u8 i = 0;
+	struct _RT_BEAMFORMING_INFO *beam_info = &dm->beamforming_info;
+	enum beamforming_cap beamform_entry_cap = BEAMFORMING_CAP_NONE;
+
+	for (i = 0; i < BEAMFORMEE_ENTRY_NUM; i++) {
+		if (beam_info->beamformee_entry[i].is_used && mac_id == beam_info->beamformee_entry[i].mac_id) {
+			beamform_entry_cap = beam_info->beamformee_entry[i].beamform_entry_cap;
+			i = BEAMFORMEE_ENTRY_NUM;
+		}
+	}
+
+	return beamform_entry_cap;
+}
+
+struct _RT_BEAMFORMEE_ENTRY *
+phydm_beamforming_get_free_bfee_entry(
+	void *dm_void,
+	u8 *idx)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	u8 i = 0;
+	struct _RT_BEAMFORMING_INFO *beam_info = &dm->beamforming_info;
+
+	for (i = 0; i < BEAMFORMEE_ENTRY_NUM; i++) {
+		if (beam_info->beamformee_entry[i].is_used == false) {
+			*idx = i;
+			return &beam_info->beamformee_entry[i];
+		}
+	}
+	return NULL;
+}
+
+struct _RT_BEAMFORMER_ENTRY *
+phydm_beamforming_get_free_bfer_entry(
+	void *dm_void,
+	u8 *idx)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	u8 i = 0;
+	struct _RT_BEAMFORMING_INFO *beam_info = &dm->beamforming_info;
+
+	PHYDM_DBG(dm, DBG_TXBF, "%s ===>\n", __func__);
+
+	for (i = 0; i < BEAMFORMER_ENTRY_NUM; i++) {
+		if (beam_info->beamformer_entry[i].is_used == false) {
+			*idx = i;
+			return &beam_info->beamformer_entry[i];
+		}
+	}
+	return NULL;
+}
+
+/*@
+ * Description: Get the first entry index of MU Beamformee.
+ *
+ * Return value: index of the first MU sta.
+ *
+ * 2015.05.25. Created by tynli.
+ *
+ */
+u8 phydm_beamforming_get_first_mu_bfee_entry_idx(
+	void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	u8 idx = 0xFF;
+	struct _RT_BEAMFORMING_INFO *beam_info = &dm->beamforming_info;
+	boolean is_found = false;
+
+	for (idx = 0; idx < BEAMFORMEE_ENTRY_NUM; idx++) {
+		if (beam_info->beamformee_entry[idx].is_used && beam_info->beamformee_entry[idx].is_mu_sta) {
+			PHYDM_DBG(dm, DBG_TXBF, "[%s] idx=%d!\n", __func__,
+				  idx);
+			is_found = true;
+			break;
+		}
+	}
+
+	if (!is_found)
+		idx = 0xFF;
+
+	return idx;
+}
+
+/*@Add SU BFee and MU BFee*/
+struct _RT_BEAMFORMEE_ENTRY *
+beamforming_add_bfee_entry(
+	void *dm_void,
+	struct _RT_BEAMFORM_STAINFO *sta,
+	enum beamforming_cap beamform_cap,
+	u8 num_of_sounding_dim,
+	u8 comp_steering_num_of_bfer,
+	u8 *idx)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct _RT_BEAMFORMEE_ENTRY *entry = phydm_beamforming_get_free_bfee_entry(dm, idx);
+
+	PHYDM_DBG(dm, DBG_TXBF, "%s Start!\n", __func__);
+
+	if (entry != NULL) {
+		entry->is_used = true;
+		entry->aid = sta->aid;
+		entry->mac_id = sta->mac_id;
+		entry->sound_bw = sta->bw;
+		odm_move_memory(dm, entry->my_mac_addr, sta->my_mac_addr, 6);
+
+		if (phydm_acting_determine(dm, phydm_acting_as_ap)) {
+			/*@BSSID[44:47] xor BSSID[40:43]*/
+			u16 bssid = ((sta->my_mac_addr[5] & 0xf0) >> 4) ^ (sta->my_mac_addr[5] & 0xf);
+			/*@(dec(A) + dec(B)*32) mod 512*/
+			entry->p_aid = (sta->aid + bssid * 32) & 0x1ff;
+			entry->g_id = 63;
+			PHYDM_DBG(dm, DBG_TXBF,
+				  "%s: BFee P_AID addressed to STA=%d\n",
+				  __func__, entry->p_aid);
+		} else if (phydm_acting_determine(dm, phydm_acting_as_ibss)) {
+			/*@ad hoc mode*/
+			entry->p_aid = 0;
+			entry->g_id = 63;
+			PHYDM_DBG(dm, DBG_TXBF, "%s: BFee P_AID as IBSS=%d\n",
+				  __func__, entry->p_aid);
+		} else {
+			/*@client mode*/
+			entry->p_aid = sta->ra[5];
+			/*@BSSID[39:47]*/
+			entry->p_aid = (entry->p_aid << 1) | (sta->ra[4] >> 7);
+			entry->g_id = 0;
+			PHYDM_DBG(dm, DBG_TXBF,
+				  "%s: BFee P_AID addressed to AP=0x%X\n",
+				  __func__, entry->p_aid);
+		}
+		cp_mac_addr(entry->mac_addr, sta->ra);
+		entry->is_txbf = false;
+		entry->is_sound = false;
+		entry->sound_period = 400;
+		entry->beamform_entry_cap = beamform_cap;
+		entry->beamform_entry_state = BEAMFORMING_ENTRY_STATE_UNINITIALIZE;
+
+		/*		@entry->log_seq = 0xff;				Move to beamforming_add_bfer_entry*/
+		/*		@entry->log_retry_cnt = 0;			Move to beamforming_add_bfer_entry*/
+		/*		@entry->LogSuccessCnt = 0;		Move to beamforming_add_bfer_entry*/
+
+		entry->log_status_fail_cnt = 0;
+
+		entry->num_of_sounding_dim = num_of_sounding_dim;
+		entry->comp_steering_num_of_bfer = comp_steering_num_of_bfer;
+
+		if (beamform_cap & BEAMFORMER_CAP_VHT_MU) {
+			dm->beamforming_info.beamformee_mu_cnt += 1;
+			entry->is_mu_sta = true;
+			dm->beamforming_info.first_mu_bfee_index = phydm_beamforming_get_first_mu_bfee_entry_idx(dm);
+		} else if (beamform_cap & (BEAMFORMER_CAP_VHT_SU | BEAMFORMER_CAP_HT_EXPLICIT)) {
+			dm->beamforming_info.beamformee_su_cnt += 1;
+			entry->is_mu_sta = false;
+		}
+
+		return entry;
+	} else
+		return NULL;
+}
+
+/*@Add SU BFee and MU BFer*/
+struct _RT_BEAMFORMER_ENTRY *
+beamforming_add_bfer_entry(
+	void *dm_void,
+	struct _RT_BEAMFORM_STAINFO *sta,
+	enum beamforming_cap beamform_cap,
+	u8 num_of_sounding_dim,
+	u8 *idx)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct _RT_BEAMFORMER_ENTRY *entry = phydm_beamforming_get_free_bfer_entry(dm, idx);
+
+	PHYDM_DBG(dm, DBG_TXBF, "%s Start!\n", __func__);
+
+	if (entry != NULL) {
+		entry->is_used = true;
+		odm_move_memory(dm, entry->my_mac_addr, sta->my_mac_addr, 6);
+		if (phydm_acting_determine(dm, phydm_acting_as_ap)) {
+			/*@BSSID[44:47] xor BSSID[40:43]*/
+			u16 bssid = ((sta->my_mac_addr[5] & 0xf0) >> 4) ^ (sta->my_mac_addr[5] & 0xf);
+
+			entry->p_aid = (sta->aid + bssid * 32) & 0x1ff;
+			entry->g_id = 63;
+			/*@(dec(A) + dec(B)*32) mod 512*/
+		} else if (phydm_acting_determine(dm, phydm_acting_as_ibss)) {
+			entry->p_aid = 0;
+			entry->g_id = 63;
+		} else {
+			entry->p_aid = sta->ra[5];
+			/*@BSSID[39:47]*/
+			entry->p_aid = (entry->p_aid << 1) | (sta->ra[4] >> 7);
+			entry->g_id = 0;
+			PHYDM_DBG(dm, DBG_TXBF,
+				  "%s: P_AID addressed to AP=0x%X\n", __func__,
+				  entry->p_aid);
+		}
+
+		cp_mac_addr(entry->mac_addr, sta->ra);
+		entry->beamform_entry_cap = beamform_cap;
+
+		entry->pre_log_seq = 0; /*@Modified by Jeffery @2015-04-13*/
+		entry->log_seq = 0; /*@Modified by Jeffery @2014-10-29*/
+		entry->log_retry_cnt = 0; /*@Modified by Jeffery @2014-10-29*/
+		entry->log_success = 0; /*@log_success is NOT needed to be accumulated, so  LogSuccessCnt->log_success, 2015-04-13, Jeffery*/
+		entry->clock_reset_times = 0; /*@Modified by Jeffery @2015-04-13*/
+
+		entry->num_of_sounding_dim = num_of_sounding_dim;
+
+		if (beamform_cap & BEAMFORMEE_CAP_VHT_MU) {
+			dm->beamforming_info.beamformer_mu_cnt += 1;
+			entry->is_mu_ap = true;
+			entry->aid = sta->aid;
+		} else if (beamform_cap & (BEAMFORMEE_CAP_VHT_SU | BEAMFORMEE_CAP_HT_EXPLICIT)) {
+			dm->beamforming_info.beamformer_su_cnt += 1;
+			entry->is_mu_ap = false;
+		}
+
+		return entry;
+	} else
+		return NULL;
+}
+
+#if 0
+boolean
+beamforming_remove_entry(
+	void			*adapter,
+	u8		*RA,
+	u8		*idx
+)
+{
+	HAL_DATA_TYPE			*hal_data = GET_HAL_DATA(((PADAPTER)adapter));
+	struct dm_struct				*dm = &hal_data->DM_OutSrc;
+
+	struct _RT_BEAMFORMER_ENTRY	*bfer_entry = phydm_beamforming_get_bfer_entry_by_addr(dm, RA, idx);
+	struct _RT_BEAMFORMEE_ENTRY	*entry = phydm_beamforming_get_bfee_entry_by_addr(dm, RA, idx);
+	boolean ret = false;
+
+	RT_DISP(FBEAM, FBEAM_FUN, ("[Beamforming]@%s Start!\n", __func__));
+	RT_DISP(FBEAM, FBEAM_FUN, ("[Beamforming]@%s, bfer_entry=0x%x\n", __func__, bfer_entry));
+	RT_DISP(FBEAM, FBEAM_FUN, ("[Beamforming]@%s, entry=0x%x\n", __func__, entry));
+
+	if (entry != NULL) {
+		entry->is_used = false;
+		entry->beamform_entry_cap = BEAMFORMING_CAP_NONE;
+		/*@entry->beamform_entry_state = BEAMFORMING_ENTRY_STATE_UNINITIALIZE;*/
+		entry->is_beamforming_in_progress = false;
+		ret = true;
+	}
+	if (bfer_entry != NULL) {
+		bfer_entry->is_used = false;
+		bfer_entry->beamform_entry_cap = BEAMFORMING_CAP_NONE;
+		ret = true;
+	}
+	return ret;
+}
+#endif
+
+/* Used for beamforming_start_v1 */
+void phydm_beamforming_ndpa_rate(
+	void *dm_void,
+	enum channel_width BW,
+	u8 rate)
+{
+	u16 ndpa_rate = rate;
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+
+	PHYDM_DBG(dm, DBG_TXBF, "%s Start!\n", __func__);
+
+	if (ndpa_rate == 0) {
+		if (dm->rssi_min > 30) /* @link RSSI > 30% */
+			ndpa_rate = ODM_RATE24M;
+		else
+			ndpa_rate = ODM_RATE6M;
+	}
+
+	if (ndpa_rate < ODM_RATEMCS0)
+		BW = (enum channel_width)CHANNEL_WIDTH_20;
+
+	ndpa_rate = (ndpa_rate << 8) | BW;
+	hal_com_txbf_set(dm, TXBF_SET_SOUNDING_RATE, (u8 *)&ndpa_rate);
+}
+
+/* Used for beamforming_start_sw and  beamforming_start_fw */
+void phydm_beamforming_dym_ndpa_rate(
+	void *dm_void)
+{
+	u16 ndpa_rate = ODM_RATE6M, BW;
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+
+	ndpa_rate = ODM_RATE6M;
+	BW = CHANNEL_WIDTH_20;
+
+	ndpa_rate = ndpa_rate << 8 | BW;
+	hal_com_txbf_set(dm, TXBF_SET_SOUNDING_RATE, (u8 *)&ndpa_rate);
+	PHYDM_DBG(dm, DBG_TXBF, "%s End, NDPA rate = 0x%X\n", __func__,
+		  ndpa_rate);
+}
+
+/*@
+*	SW Sounding : SW Timer unit 1ms
+*				 HW Timer unit (1/32000) s  32k is clock.
+*	FW Sounding : FW Timer unit 10ms
+*/
+void beamforming_dym_period(
+	void *dm_void,
+	u8 status)
+{
+	u8 idx;
+	boolean is_change_period = false;
+	u16 sound_period_sw, sound_period_fw;
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+
+	struct _RT_BEAMFORMEE_ENTRY *beamform_entry;
+	struct _RT_BEAMFORMING_INFO *beam_info = &dm->beamforming_info;
+	struct _RT_SOUNDING_INFO *sound_info = &beam_info->sounding_info;
+
+	struct _RT_BEAMFORMEE_ENTRY *entry = &beam_info->beamformee_entry[beam_info->beamformee_cur_idx];
+
+	PHYDM_DBG(dm, DBG_TXBF, "[%s] Start!\n", __func__);
+
+	/* @3 TODO  per-client throughput caculation. */
+
+	if ((*dm->current_tx_tp + *dm->current_rx_tp > 2) && (entry->log_status_fail_cnt <= 20 || status)) {
+		sound_period_sw = 40; /* @40ms */
+		sound_period_fw = 40; /* @From  H2C cmd, unit = 10ms */
+	} else {
+		sound_period_sw = 4000; /* @4s */
+		sound_period_fw = 400;
+	}
+	PHYDM_DBG(dm, DBG_TXBF, "[%s]sound_period_sw=%d, sound_period_fw=%d\n",
+		  __func__, sound_period_sw, sound_period_fw);
+
+	for (idx = 0; idx < BEAMFORMEE_ENTRY_NUM; idx++) {
+		beamform_entry = beam_info->beamformee_entry + idx;
+
+		if (beamform_entry->default_csi_cnt > 20) {
+			/*@Modified by David*/
+			sound_period_sw = 4000;
+			sound_period_fw = 400;
+		}
+
+		PHYDM_DBG(dm, DBG_TXBF, "[%s] period = %d\n", __func__,
+			  sound_period_sw);
+		if ((beamform_entry->beamform_entry_cap & (BEAMFORMER_CAP_HT_EXPLICIT | BEAMFORMER_CAP_VHT_SU)) == 0)
+			continue;
+
+		if (sound_info->sound_mode == SOUNDING_FW_VHT_TIMER || sound_info->sound_mode == SOUNDING_FW_HT_TIMER) {
+			if (beamform_entry->sound_period != sound_period_fw) {
+				beamform_entry->sound_period = sound_period_fw;
+				is_change_period = true; /*Only FW sounding need to send H2C packet to change sound period. */
+			}
+		} else if (beamform_entry->sound_period != sound_period_sw)
+			beamform_entry->sound_period = sound_period_sw;
+	}
+
+	if (is_change_period)
+		hal_com_txbf_set(dm, TXBF_SET_SOUNDING_FW_NDPA, (u8 *)&idx);
+}
+
+boolean
+beamforming_send_ht_ndpa_packet(
+	void *dm_void,
+	u8 *RA,
+	enum channel_width BW,
+	u8 q_idx)
+{
+	boolean ret = true;
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+
+	if (q_idx == BEACON_QUEUE)
+		ret = send_fw_ht_ndpa_packet(dm, RA, BW);
+	else
+		ret = send_sw_ht_ndpa_packet(dm, RA, BW);
+
+	return ret;
+}
+
+boolean
+beamforming_send_vht_ndpa_packet(
+	void *dm_void,
+	u8 *RA,
+	u16 AID,
+	enum channel_width BW,
+	u8 q_idx)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct _RT_BEAMFORMING_INFO *beam_info = &dm->beamforming_info;
+	boolean ret = true;
+
+	hal_com_txbf_set(dm, TXBF_SET_GET_TX_RATE, NULL);
+
+	if (beam_info->tx_bf_data_rate >= ODM_RATEVHTSS3MCS7 && beam_info->tx_bf_data_rate <= ODM_RATEVHTSS3MCS9 && !beam_info->snding3ss)
+		PHYDM_DBG(dm, DBG_TXBF, "@%s: 3SS VHT 789 don't sounding\n",
+			  __func__);
+
+	else {
+		if (q_idx == BEACON_QUEUE) /* Send to reserved page => FW NDPA */
+			ret = send_fw_vht_ndpa_packet(dm, RA, AID, BW);
+		else {
+#ifdef SUPPORT_MU_BF
+#if (SUPPORT_MU_BF == 1)
+			beam_info->is_mu_sounding = true;
+			ret = send_sw_vht_mu_ndpa_packet(dm, BW);
+#else
+			beam_info->is_mu_sounding = false;
+			ret = send_sw_vht_ndpa_packet(dm, RA, AID, BW);
+#endif
+#else
+			beam_info->is_mu_sounding = false;
+			ret = send_sw_vht_ndpa_packet(dm, RA, AID, BW);
+#endif
+		}
+	}
+	return ret;
+}
+
+enum beamforming_notify_state
+phydm_beamfomring_is_sounding(
+	void *dm_void,
+	struct _RT_BEAMFORMING_INFO *beam_info,
+	u8 *idx)
+{
+	enum beamforming_notify_state is_sounding = BEAMFORMING_NOTIFY_NONE;
+	struct _RT_BEAMFORMING_OID_INFO beam_oid_info = beam_info->beamforming_oid_info;
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	u8 i;
+
+	PHYDM_DBG(dm, DBG_TXBF, "%s Start!\n", __func__);
+
+	/*@if(( Beamforming_GetBeamCap(beam_info) & BEAMFORMER_CAP) == 0)*/
+	/*@is_sounding = BEAMFORMING_NOTIFY_RESET;*/
+	if (beam_oid_info.sound_oid_mode == sounding_stop_all_timer) {
+		is_sounding = BEAMFORMING_NOTIFY_RESET;
+		goto out;
+	}
+
+	for (i = 0; i < BEAMFORMEE_ENTRY_NUM; i++) {
+		PHYDM_DBG(dm, DBG_TXBF,
+			  "@%s: BFee Entry %d is_used=%d, is_sound=%d\n",
+			  __func__, i, beam_info->beamformee_entry[i].is_used,
+			  beam_info->beamformee_entry[i].is_sound);
+		if (beam_info->beamformee_entry[i].is_used && !beam_info->beamformee_entry[i].is_sound) {
+			PHYDM_DBG(dm, DBG_TXBF, "%s: Add BFee entry %d\n",
+				  __func__, i);
+			*idx = i;
+			if (beam_info->beamformee_entry[i].is_mu_sta)
+				is_sounding = BEAMFORMEE_NOTIFY_ADD_MU;
+			else
+				is_sounding = BEAMFORMEE_NOTIFY_ADD_SU;
+		}
+
+		if (!beam_info->beamformee_entry[i].is_used && beam_info->beamformee_entry[i].is_sound) {
+			PHYDM_DBG(dm, DBG_TXBF, "%s: Delete BFee entry %d\n",
+				  __func__, i);
+			*idx = i;
+			if (beam_info->beamformee_entry[i].is_mu_sta)
+				is_sounding = BEAMFORMEE_NOTIFY_DELETE_MU;
+			else
+				is_sounding = BEAMFORMEE_NOTIFY_DELETE_SU;
+		}
+	}
+
+out:
+	PHYDM_DBG(dm, DBG_TXBF, "%s End, is_sounding = %d\n", __func__,
+		  is_sounding);
+	return is_sounding;
+}
+
+/* This function is unused */
+u8 phydm_beamforming_sounding_idx(
+	void *dm_void,
+	struct _RT_BEAMFORMING_INFO *beam_info)
+{
+	u8 idx = 0;
+	struct _RT_BEAMFORMING_OID_INFO beam_oid_info = beam_info->beamforming_oid_info;
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+
+	PHYDM_DBG(dm, DBG_TXBF, "%s Start!\n", __func__);
+
+	if (beam_oid_info.sound_oid_mode == SOUNDING_SW_HT_TIMER || beam_oid_info.sound_oid_mode == SOUNDING_SW_VHT_TIMER ||
+	    beam_oid_info.sound_oid_mode == SOUNDING_HW_HT_TIMER || beam_oid_info.sound_oid_mode == SOUNDING_HW_VHT_TIMER)
+		idx = beam_oid_info.sound_oid_idx;
+	else {
+		u8 i;
+		for (i = 0; i < BEAMFORMEE_ENTRY_NUM; i++) {
+			if (beam_info->beamformee_entry[i].is_used && !beam_info->beamformee_entry[i].is_sound) {
+				idx = i;
+				break;
+			}
+		}
+	}
+
+	return idx;
+}
+
+enum sounding_mode
+phydm_beamforming_sounding_mode(
+	void *dm_void,
+	struct _RT_BEAMFORMING_INFO *beam_info,
+	u8 idx)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	u8 support_interface = dm->support_interface;
+
+	struct _RT_BEAMFORMEE_ENTRY beam_entry = beam_info->beamformee_entry[idx];
+	struct _RT_BEAMFORMING_OID_INFO beam_oid_info = beam_info->beamforming_oid_info;
+	enum sounding_mode mode = beam_oid_info.sound_oid_mode;
+
+	if (beam_oid_info.sound_oid_mode == SOUNDING_SW_VHT_TIMER || beam_oid_info.sound_oid_mode == SOUNDING_HW_VHT_TIMER) {
+		if (beam_entry.beamform_entry_cap & BEAMFORMER_CAP_VHT_SU)
+			mode = beam_oid_info.sound_oid_mode;
+		else
+			mode = sounding_stop_all_timer;
+	} else if (beam_oid_info.sound_oid_mode == SOUNDING_SW_HT_TIMER || beam_oid_info.sound_oid_mode == SOUNDING_HW_HT_TIMER) {
+		if (beam_entry.beamform_entry_cap & BEAMFORMER_CAP_HT_EXPLICIT)
+			mode = beam_oid_info.sound_oid_mode;
+		else
+			mode = sounding_stop_all_timer;
+	} else if (beam_entry.beamform_entry_cap & BEAMFORMER_CAP_VHT_SU) {
+		if (support_interface == ODM_ITRF_USB && !(dm->support_ic_type & (ODM_RTL8814A | ODM_RTL8822B)))
+			mode = SOUNDING_FW_VHT_TIMER;
+		else
+			mode = SOUNDING_SW_VHT_TIMER;
+	} else if (beam_entry.beamform_entry_cap & BEAMFORMER_CAP_HT_EXPLICIT) {
+		if (support_interface == ODM_ITRF_USB && !(dm->support_ic_type & (ODM_RTL8814A | ODM_RTL8822B)))
+			mode = SOUNDING_FW_HT_TIMER;
+		else
+			mode = SOUNDING_SW_HT_TIMER;
+	} else
+		mode = sounding_stop_all_timer;
+
+	PHYDM_DBG(dm, DBG_TXBF, "[%s] support_interface=%d, mode=%d\n",
+		  __func__, support_interface, mode);
+
+	return mode;
+}
+
+u16 phydm_beamforming_sounding_time(
+	void *dm_void,
+	struct _RT_BEAMFORMING_INFO *beam_info,
+	enum sounding_mode mode,
+	u8 idx)
+{
+	u16 sounding_time = 0xffff;
+	struct _RT_BEAMFORMEE_ENTRY beam_entry = beam_info->beamformee_entry[idx];
+	struct _RT_BEAMFORMING_OID_INFO beam_oid_info = beam_info->beamforming_oid_info;
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+
+	PHYDM_DBG(dm, DBG_TXBF, "%s Start!\n", __func__);
+
+	if (mode == SOUNDING_HW_HT_TIMER || mode == SOUNDING_HW_VHT_TIMER)
+		sounding_time = beam_oid_info.sound_oid_period * 32;
+	else if (mode == SOUNDING_SW_HT_TIMER || mode == SOUNDING_SW_VHT_TIMER)
+		/*@Modified by David*/
+		sounding_time = beam_entry.sound_period; /*@beam_oid_info.sound_oid_period;*/
+	else
+		sounding_time = beam_entry.sound_period;
+
+	return sounding_time;
+}
+
+enum channel_width
+phydm_beamforming_sounding_bw(
+	void *dm_void,
+	struct _RT_BEAMFORMING_INFO *beam_info,
+	enum sounding_mode mode,
+	u8 idx)
+{
+	enum channel_width sounding_bw = CHANNEL_WIDTH_20;
+	struct _RT_BEAMFORMEE_ENTRY beam_entry = beam_info->beamformee_entry[idx];
+	struct _RT_BEAMFORMING_OID_INFO beam_oid_info = beam_info->beamforming_oid_info;
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+
+	if (mode == SOUNDING_HW_HT_TIMER || mode == SOUNDING_HW_VHT_TIMER)
+		sounding_bw = beam_oid_info.sound_oid_bw;
+	else if (mode == SOUNDING_SW_HT_TIMER || mode == SOUNDING_SW_VHT_TIMER)
+		/*@Modified by David*/
+		sounding_bw = beam_entry.sound_bw; /*@beam_oid_info.sound_oid_bw;*/
+	else
+		sounding_bw = beam_entry.sound_bw;
+
+	PHYDM_DBG(dm, DBG_TXBF, "%s, sounding_bw=0x%X\n", __func__,
+		  sounding_bw);
+
+	return sounding_bw;
+}
+
+boolean
+phydm_beamforming_select_beam_entry(
+	void *dm_void,
+	struct _RT_BEAMFORMING_INFO *beam_info)
+{
+	struct _RT_SOUNDING_INFO *sound_info = &beam_info->sounding_info;
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+
+	/*@entry.is_sound is different between first and latter NDPA, and should not be used as BFee entry selection*/
+	/*@BTW, latter modification should sync to the selection mechanism of AP/ADSL instead of the fixed sound_idx.*/
+	sound_info->sound_idx = phydm_beamforming_sounding_idx(dm, beam_info);
+	/*sound_info->sound_idx = 0;*/
+
+	if (sound_info->sound_idx < BEAMFORMEE_ENTRY_NUM)
+		sound_info->sound_mode = phydm_beamforming_sounding_mode(dm, beam_info, sound_info->sound_idx);
+	else
+		sound_info->sound_mode = sounding_stop_all_timer;
+
+	if (sounding_stop_all_timer == sound_info->sound_mode) {
+		PHYDM_DBG(dm, DBG_TXBF,
+			  "[%s] Return because of sounding_stop_all_timer\n",
+			  __func__);
+		return false;
+	} else {
+		sound_info->sound_bw = phydm_beamforming_sounding_bw(dm, beam_info, sound_info->sound_mode, sound_info->sound_idx);
+		sound_info->sound_period = phydm_beamforming_sounding_time(dm, beam_info, sound_info->sound_mode, sound_info->sound_idx);
+		return true;
+	}
+}
+
+/*SU BFee Entry Only*/
+boolean
+phydm_beamforming_start_period(
+	void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	boolean ret = true;
+	struct _RT_BEAMFORMING_INFO *beam_info = &dm->beamforming_info;
+	struct _RT_SOUNDING_INFO *sound_info = &beam_info->sounding_info;
+
+	phydm_beamforming_dym_ndpa_rate(dm);
+
+	phydm_beamforming_select_beam_entry(dm, beam_info); /* @Modified */
+
+	if (sound_info->sound_mode == SOUNDING_SW_VHT_TIMER || sound_info->sound_mode == SOUNDING_SW_HT_TIMER)
+		odm_set_timer(dm, &beam_info->beamforming_timer, sound_info->sound_period);
+	else if (sound_info->sound_mode == SOUNDING_HW_VHT_TIMER || sound_info->sound_mode == SOUNDING_HW_HT_TIMER ||
+		 sound_info->sound_mode == SOUNDING_AUTO_VHT_TIMER || sound_info->sound_mode == SOUNDING_AUTO_HT_TIMER) {
+		HAL_HW_TIMER_TYPE timer_type = HAL_TIMER_TXBF;
+		u32 val = (sound_info->sound_period | (timer_type << 16));
+
+		/* @HW timer stop: All IC has the same setting */
+		phydm_set_hw_reg_handler_interface(dm, HW_VAR_HW_REG_TIMER_STOP, (u8 *)(&timer_type));
+		/* odm_write_1byte(dm, 0x15F, 0); */
+		/* @HW timer init: All IC has the same setting, but 92E & 8812A only write 2 bytes */
+		phydm_set_hw_reg_handler_interface(dm, HW_VAR_HW_REG_TIMER_INIT, (u8 *)(&val));
+		/* odm_write_1byte(dm, 0x164, 1); */
+		/* odm_write_4byte(dm, 0x15C, val); */
+		/* @HW timer start: All IC has the same setting */
+		phydm_set_hw_reg_handler_interface(dm, HW_VAR_HW_REG_TIMER_START, (u8 *)(&timer_type));
+		/* odm_write_1byte(dm, 0x15F, 0x5); */
+	} else if (sound_info->sound_mode == SOUNDING_FW_VHT_TIMER || sound_info->sound_mode == SOUNDING_FW_HT_TIMER)
+		ret = beamforming_start_fw(dm, sound_info->sound_idx);
+	else
+		ret = false;
+
+	PHYDM_DBG(dm, DBG_TXBF,
+		  "[%s] sound_idx=%d, sound_mode=%d, sound_bw=%d, sound_period=%d\n",
+		  __func__, sound_info->sound_idx, sound_info->sound_mode,
+		  sound_info->sound_bw, sound_info->sound_period);
+
+	return ret;
+}
+
+/* Used after beamforming_leave, and will clear the setting of the "already deleted" entry
+ *SU BFee Entry Only*/
+void phydm_beamforming_end_period_sw(
+	void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	/*void					*adapter = dm->adapter;*/
+	struct _RT_BEAMFORMING_INFO *beam_info = &dm->beamforming_info;
+	struct _RT_SOUNDING_INFO *sound_info = &beam_info->sounding_info;
+
+	HAL_HW_TIMER_TYPE timer_type = HAL_TIMER_TXBF;
+
+	PHYDM_DBG(dm, DBG_TXBF, "%s Start!\n", __func__);
+
+	if (sound_info->sound_mode == SOUNDING_SW_VHT_TIMER || sound_info->sound_mode == SOUNDING_SW_HT_TIMER)
+		odm_cancel_timer(dm, &beam_info->beamforming_timer);
+	else if (sound_info->sound_mode == SOUNDING_HW_VHT_TIMER || sound_info->sound_mode == SOUNDING_HW_HT_TIMER ||
+		 sound_info->sound_mode == SOUNDING_AUTO_VHT_TIMER || sound_info->sound_mode == SOUNDING_AUTO_HT_TIMER)
+		/*@HW timer stop: All IC has the same setting*/
+		phydm_set_hw_reg_handler_interface(dm, HW_VAR_HW_REG_TIMER_STOP, (u8 *)(&timer_type));
+	/*odm_write_1byte(dm, 0x15F, 0);*/
+}
+
+void phydm_beamforming_end_period_fw(
+	void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	u8 idx = 0;
+
+	hal_com_txbf_set(dm, TXBF_SET_SOUNDING_FW_NDPA, (u8 *)&idx);
+	PHYDM_DBG(dm, DBG_TXBF, "[%s]\n", __func__);
+}
+
+/*SU BFee Entry Only*/
+void phydm_beamforming_clear_entry_sw(
+	void *dm_void,
+	boolean is_delete,
+	u8 delete_idx)
+{
+	u8 idx = 0;
+	struct _RT_BEAMFORMEE_ENTRY *beamform_entry = NULL;
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct _RT_BEAMFORMING_INFO *beam_info = &dm->beamforming_info;
+
+	if (is_delete) {
+		if (delete_idx < BEAMFORMEE_ENTRY_NUM) {
+			beamform_entry = beam_info->beamformee_entry + delete_idx;
+			if (!(!beamform_entry->is_used && beamform_entry->is_sound)) {
+				PHYDM_DBG(dm, DBG_TXBF,
+					  "[%s] SW delete_idx is wrong!!!!!\n",
+					  __func__);
+				return;
+			}
+		}
+
+		PHYDM_DBG(dm, DBG_TXBF, "[%s] SW delete BFee entry %d\n",
+			  __func__, delete_idx);
+		if (beamform_entry->beamform_entry_state == BEAMFORMING_ENTRY_STATE_PROGRESSING) {
+			beamform_entry->is_beamforming_in_progress = false;
+			beamform_entry->beamform_entry_state = BEAMFORMING_ENTRY_STATE_UNINITIALIZE;
+		} else if (beamform_entry->beamform_entry_state == BEAMFORMING_ENTRY_STATE_PROGRESSED) {
+			beamform_entry->beamform_entry_state = BEAMFORMING_ENTRY_STATE_UNINITIALIZE;
+			hal_com_txbf_set(dm, TXBF_SET_SOUNDING_STATUS, (u8 *)&delete_idx);
+		}
+		beamform_entry->is_sound = false;
+		return;
+	}
+
+	for (idx = 0; idx < BEAMFORMEE_ENTRY_NUM; idx++) {
+		beamform_entry = beam_info->beamformee_entry + idx;
+
+		/*Used after is_sounding=RESET, and will clear the setting of "ever sounded" entry, which is not necessarily be deleted.*/
+		/*This function is mainly used in case "beam_oid_info.sound_oid_mode == sounding_stop_all_timer".*/
+		/*@However, setting oid doesn't delete entries (is_used is still true), new entries may fail to be added in.*/
+
+		if (!beamform_entry->is_sound)
+			continue;
+
+		PHYDM_DBG(dm, DBG_TXBF, "[%s] SW reset BFee entry %d\n",
+			  __func__, idx);
+		/*@
+		*	If End procedure is
+		*	1. Between (Send NDPA, C2H packet return), reset state to initialized.
+		*	After C2H packet return , status bit will be set to zero.
+		*
+		*	2. After C2H packet, then reset state to initialized and clear status bit.
+		*/
+
+		if (beamform_entry->beamform_entry_state == BEAMFORMING_ENTRY_STATE_PROGRESSING)
+			phydm_beamforming_end_sw(dm, 0);
+		else if (beamform_entry->beamform_entry_state == BEAMFORMING_ENTRY_STATE_PROGRESSED) {
+			beamform_entry->beamform_entry_state = BEAMFORMING_ENTRY_STATE_INITIALIZED;
+			hal_com_txbf_set(dm, TXBF_SET_SOUNDING_STATUS, (u8 *)&idx);
+		}
+
+		beamform_entry->is_sound = false;
+	}
+}
+
+void phydm_beamforming_clear_entry_fw(
+	void *dm_void,
+	boolean is_delete,
+	u8 delete_idx)
+{
+	u8 idx = 0;
+	struct _RT_BEAMFORMEE_ENTRY *beamform_entry = NULL;
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct _RT_BEAMFORMING_INFO *beam_info = &dm->beamforming_info;
+
+	if (is_delete) {
+		if (delete_idx < BEAMFORMEE_ENTRY_NUM) {
+			beamform_entry = beam_info->beamformee_entry + delete_idx;
+
+			if (!(!beamform_entry->is_used && beamform_entry->is_sound)) {
+				PHYDM_DBG(dm, DBG_TXBF,
+					  "[%s] FW delete_idx is wrong!!!!!\n",
+					  __func__);
+				return;
+			}
+		}
+		PHYDM_DBG(dm, DBG_TXBF, "%s: FW delete BFee entry %d\n",
+			  __func__, delete_idx);
+		beamform_entry->beamform_entry_state = BEAMFORMING_ENTRY_STATE_UNINITIALIZE;
+		beamform_entry->is_sound = false;
+	} else {
+		for (idx = 0; idx < BEAMFORMEE_ENTRY_NUM; idx++) {
+			beamform_entry = beam_info->beamformee_entry + idx;
+
+			/*Used after is_sounding=RESET, and will clear the setting of "ever sounded" entry, which is not necessarily be deleted.*/
+			/*This function is mainly used in case "beam_oid_info.sound_oid_mode == sounding_stop_all_timer".*/
+			/*@However, setting oid doesn't delete entries (is_used is still true), new entries may fail to be added in.*/
+
+			if (beamform_entry->is_sound) {
+				PHYDM_DBG(dm, DBG_TXBF,
+					  "[%s]FW reset BFee entry %d\n",
+					  __func__, idx);
+				/*@
+				*	If End procedure is
+				*	1. Between (Send NDPA, C2H packet return), reset state to initialized.
+				*	After C2H packet return , status bit will be set to zero.
+				*
+				*	2. After C2H packet, then reset state to initialized and clear status bit.
+				*/
+
+				beamform_entry->beamform_entry_state = BEAMFORMING_ENTRY_STATE_INITIALIZED;
+				beamform_entry->is_sound = false;
+			}
+		}
+	}
+}
+
+/*@
+*	Called :
+*	1. Add and delete entry : beamforming_enter/beamforming_leave
+*	2. FW trigger :  Beamforming_SetTxBFen
+*	3. Set OID_RT_BEAMFORMING_PERIOD : beamforming_control_v2
+*/
+void phydm_beamforming_notify(
+	void *dm_void)
+{
+	u8 idx = BEAMFORMEE_ENTRY_NUM;
+	enum beamforming_notify_state is_sounding = BEAMFORMING_NOTIFY_NONE;
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct _RT_BEAMFORMING_INFO *beam_info = &dm->beamforming_info;
+	struct _RT_SOUNDING_INFO *sound_info = &beam_info->sounding_info;
+
+	PHYDM_DBG(dm, DBG_TXBF, "%s Start!\n", __func__);
+
+	is_sounding = phydm_beamfomring_is_sounding(dm, beam_info, &idx);
+
+	PHYDM_DBG(dm, DBG_TXBF, "%s, Before notify, is_sounding=%d, idx=%d\n",
+		  __func__, is_sounding, idx);
+	PHYDM_DBG(dm, DBG_TXBF, "%s: beam_info->beamformee_su_cnt = %d\n",
+		  __func__, beam_info->beamformee_su_cnt);
+
+	switch (is_sounding) {
+	case BEAMFORMEE_NOTIFY_ADD_SU:
+		PHYDM_DBG(dm, DBG_TXBF, "%s: BEAMFORMEE_NOTIFY_ADD_SU\n",
+			  __func__);
+		phydm_beamforming_start_period(dm);
+		break;
+
+	case BEAMFORMEE_NOTIFY_DELETE_SU:
+		PHYDM_DBG(dm, DBG_TXBF, "%s: BEAMFORMEE_NOTIFY_DELETE_SU\n",
+			  __func__);
+		if (sound_info->sound_mode == SOUNDING_FW_HT_TIMER || sound_info->sound_mode == SOUNDING_FW_VHT_TIMER) {
+			phydm_beamforming_clear_entry_fw(dm, true, idx);
+			if (beam_info->beamformee_su_cnt == 0) { /* @For 2->1 entry, we should not cancel SW timer */
+				phydm_beamforming_end_period_fw(dm);
+				PHYDM_DBG(dm, DBG_TXBF, "%s: No BFee left\n",
+					  __func__);
+			}
+		} else {
+			phydm_beamforming_clear_entry_sw(dm, true, idx);
+			if (beam_info->beamformee_su_cnt == 0) { /* @For 2->1 entry, we should not cancel SW timer */
+				phydm_beamforming_end_period_sw(dm);
+				PHYDM_DBG(dm, DBG_TXBF, "%s: No BFee left\n",
+					  __func__);
+			}
+		}
+		break;
+
+	case BEAMFORMEE_NOTIFY_ADD_MU:
+		PHYDM_DBG(dm, DBG_TXBF, "%s: BEAMFORMEE_NOTIFY_ADD_MU\n",
+			  __func__);
+		if (beam_info->beamformee_mu_cnt == 2) {
+			/*@if (sound_info->sound_mode == SOUNDING_SW_VHT_TIMER || sound_info->sound_mode == SOUNDING_SW_HT_TIMER)
+				odm_set_timer(dm, &beam_info->beamforming_timer, sound_info->sound_period);*/
+			odm_set_timer(dm, &beam_info->beamforming_timer, 1000); /*@Do MU sounding every 1sec*/
+		} else
+			PHYDM_DBG(dm, DBG_TXBF,
+				  "%s: Less or larger than 2 MU STAs, not to set timer\n",
+				  __func__);
+		break;
+
+	case BEAMFORMEE_NOTIFY_DELETE_MU:
+		PHYDM_DBG(dm, DBG_TXBF, "%s: BEAMFORMEE_NOTIFY_DELETE_MU\n",
+			  __func__);
+		if (beam_info->beamformee_mu_cnt == 1) {
+			/*@if (sound_info->sound_mode == SOUNDING_SW_VHT_TIMER || sound_info->sound_mode == SOUNDING_SW_HT_TIMER)*/ {
+				odm_cancel_timer(dm, &beam_info->beamforming_timer);
+				PHYDM_DBG(dm, DBG_TXBF,
+					  "%s: Less than 2 MU STAs, stop sounding\n",
+					  __func__);
+			}
+		}
+		break;
+
+	case BEAMFORMING_NOTIFY_RESET:
+		if (sound_info->sound_mode == SOUNDING_FW_HT_TIMER || sound_info->sound_mode == SOUNDING_FW_VHT_TIMER) {
+			phydm_beamforming_clear_entry_fw(dm, false, idx);
+			phydm_beamforming_end_period_fw(dm);
+		} else {
+			phydm_beamforming_clear_entry_sw(dm, false, idx);
+			phydm_beamforming_end_period_sw(dm);
+		}
+
+		break;
+
+	default:
+		break;
+	}
+}
+
+boolean
+beamforming_init_entry(
+	void *dm_void,
+	u16 sta_idx,
+	u8 *bfer_bfee_idx)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct cmn_sta_info *cmn_sta = dm->phydm_sta_info[sta_idx];
+	struct _RT_BEAMFORMEE_ENTRY *beamform_entry = NULL;
+	struct _RT_BEAMFORMER_ENTRY *beamformer_entry = NULL;
+	struct _RT_BEAMFORM_STAINFO *sta = NULL;
+	enum beamforming_cap beamform_cap = BEAMFORMING_CAP_NONE;
+	u8 bfer_idx = 0xF, bfee_idx = 0xF;
+	u8 num_of_sounding_dim = 0, comp_steering_num_of_bfer = 0;
+
+	if (!is_sta_active(cmn_sta)) {
+		PHYDM_DBG(dm, DBG_TXBF, "%s => sta_info(mac_id:%d) failed\n",
+			  __func__, sta_idx);
+		#if (DM_ODM_SUPPORT_TYPE == ODM_CE)
+		rtw_warn_on(1);
+		#endif
+		return false;
+	}
+
+	sta = phydm_sta_info_init(dm, sta_idx);
+
+	/*The current setting does not support Beaforming*/
+	if (BEAMFORMING_CAP_NONE == sta->ht_beamform_cap && BEAMFORMING_CAP_NONE == sta->vht_beamform_cap) {
+		PHYDM_DBG(dm, DBG_TXBF,
+			  "The configuration disabled Beamforming! Skip...\n");
+		return false;
+	}
+
+	if (!(cmn_sta->support_wireless_set & (WIRELESS_VHT | WIRELESS_HT)))
+		return false;
+	else {
+		if (cmn_sta->support_wireless_set & WIRELESS_HT) { /*@HT*/
+			if (TEST_FLAG(sta->cur_beamform, BEAMFORMING_HT_BEAMFORMER_ENABLE)) { /*We are Beamformee because the STA is Beamformer*/
+				beamform_cap = (enum beamforming_cap)(beamform_cap | BEAMFORMEE_CAP_HT_EXPLICIT);
+				num_of_sounding_dim = (sta->cur_beamform & BEAMFORMING_HT_BEAMFORMEE_CHNL_EST_CAP) >> 6;
+			}
+			/*We are Beamformer because the STA is Beamformee*/
+			if (TEST_FLAG(sta->cur_beamform, BEAMFORMING_HT_BEAMFORMEE_ENABLE) ||
+			    TEST_FLAG(sta->ht_beamform_cap, BEAMFORMING_HT_BEAMFORMER_TEST)) {
+				beamform_cap = (enum beamforming_cap)(beamform_cap | BEAMFORMER_CAP_HT_EXPLICIT);
+				comp_steering_num_of_bfer = (sta->cur_beamform & BEAMFORMING_HT_BEAMFORMER_STEER_NUM) >> 4;
+			}
+			PHYDM_DBG(dm, DBG_TXBF,
+				  "[%s] HT cur_beamform=0x%X, beamform_cap=0x%X\n",
+				  __func__, sta->cur_beamform, beamform_cap);
+			PHYDM_DBG(dm, DBG_TXBF,
+				  "[%s] HT num_of_sounding_dim=%d, comp_steering_num_of_bfer=%d\n",
+				  __func__, num_of_sounding_dim,
+				  comp_steering_num_of_bfer);
+		}
+#if (ODM_IC_11AC_SERIES_SUPPORT == 1)
+		if (cmn_sta->support_wireless_set & WIRELESS_VHT) { /*VHT*/
+
+			/* We are Beamformee because the STA is SU Beamformer*/
+			if (TEST_FLAG(sta->cur_beamform_vht, BEAMFORMING_VHT_BEAMFORMER_ENABLE)) {
+				beamform_cap = (enum beamforming_cap)(beamform_cap | BEAMFORMEE_CAP_VHT_SU);
+				num_of_sounding_dim = (sta->cur_beamform_vht & BEAMFORMING_VHT_BEAMFORMEE_SOUND_DIM) >> 12;
+			}
+			/* We are Beamformer because the STA is SU Beamformee*/
+			if (TEST_FLAG(sta->cur_beamform_vht, BEAMFORMING_VHT_BEAMFORMEE_ENABLE) ||
+			    TEST_FLAG(sta->vht_beamform_cap, BEAMFORMING_VHT_BEAMFORMER_TEST)) {
+				beamform_cap = (enum beamforming_cap)(beamform_cap | BEAMFORMER_CAP_VHT_SU);
+				comp_steering_num_of_bfer = (sta->cur_beamform_vht & BEAMFORMING_VHT_BEAMFORMER_STS_CAP) >> 8;
+			}
+			/* We are Beamformee because the STA is MU Beamformer*/
+			if (TEST_FLAG(sta->cur_beamform_vht, BEAMFORMING_VHT_MU_MIMO_AP_ENABLE)) {
+				beamform_cap = (enum beamforming_cap)(beamform_cap | BEAMFORMEE_CAP_VHT_MU);
+				num_of_sounding_dim = (sta->cur_beamform_vht & BEAMFORMING_VHT_BEAMFORMEE_SOUND_DIM) >> 12;
+			}
+			/* We are Beamformer because the STA is MU Beamformee*/
+			if (phydm_acting_determine(dm, phydm_acting_as_ap)) { /* Only AP mode supports to act an MU beamformer */
+				if (TEST_FLAG(sta->cur_beamform_vht, BEAMFORMING_VHT_MU_MIMO_STA_ENABLE) ||
+				    TEST_FLAG(sta->vht_beamform_cap, BEAMFORMING_VHT_BEAMFORMER_TEST)) {
+					beamform_cap = (enum beamforming_cap)(beamform_cap | BEAMFORMER_CAP_VHT_MU);
+					comp_steering_num_of_bfer = (sta->cur_beamform_vht & BEAMFORMING_VHT_BEAMFORMER_STS_CAP) >> 8;
+				}
+			}
+			PHYDM_DBG(dm, DBG_TXBF,
+				  "[%s]VHT cur_beamform_vht=0x%X, beamform_cap=0x%X\n",
+				  __func__, sta->cur_beamform_vht,
+				  beamform_cap);
+			PHYDM_DBG(dm, DBG_TXBF,
+				  "[%s]VHT num_of_sounding_dim=0x%X, comp_steering_num_of_bfer=0x%X\n",
+				  __func__, num_of_sounding_dim,
+				  comp_steering_num_of_bfer);
+		}
+#endif
+	}
+
+	if (beamform_cap == BEAMFORMING_CAP_NONE)
+		return false;
+
+	PHYDM_DBG(dm, DBG_TXBF, "[%s] Self BF Entry Cap = 0x%02X\n", __func__,
+		  beamform_cap);
+
+	/*We are BFee, so the entry is BFer*/
+	if (beamform_cap & (BEAMFORMEE_CAP_VHT_MU | BEAMFORMEE_CAP_VHT_SU | BEAMFORMEE_CAP_HT_EXPLICIT)) {
+		beamformer_entry = phydm_beamforming_get_bfer_entry_by_addr(dm, sta->ra, &bfer_idx);
+
+		if (beamformer_entry == NULL) {
+			beamformer_entry = beamforming_add_bfer_entry(dm, sta, beamform_cap, num_of_sounding_dim, &bfer_idx);
+			if (beamformer_entry == NULL)
+				PHYDM_DBG(dm, DBG_TXBF,
+					  "[%s]Not enough BFer entry!!!!!\n",
+					  __func__);
+		}
+	}
+
+	/*We are BFer, so the entry is BFee*/
+	if (beamform_cap & (BEAMFORMER_CAP_VHT_MU | BEAMFORMER_CAP_VHT_SU | BEAMFORMER_CAP_HT_EXPLICIT)) {
+		beamform_entry = phydm_beamforming_get_bfee_entry_by_addr(dm, sta->ra, &bfee_idx);
+
+		/*@if BFeeIdx = 0xF, that represent for no matched MACID among all linked entrys */
+		PHYDM_DBG(dm, DBG_TXBF, "[%s] Get BFee entry 0x%X by address\n",
+			  __func__, bfee_idx);
+		if (beamform_entry == NULL) {
+			beamform_entry = beamforming_add_bfee_entry(dm, sta, beamform_cap, num_of_sounding_dim, comp_steering_num_of_bfer, &bfee_idx);
+			PHYDM_DBG(dm, DBG_TXBF,
+				  "[%s]: sta->AID=%d, sta->mac_id=%d\n",
+				  __func__, sta->aid, sta->mac_id);
+
+			PHYDM_DBG(dm, DBG_TXBF, "[%s]: Add BFee entry %d\n",
+				  __func__, bfee_idx);
+
+			if (beamform_entry == NULL)
+				return false;
+			else
+				beamform_entry->beamform_entry_state = BEAMFORMING_ENTRY_STATE_INITIALIZEING;
+		} else {
+			/*@Entry has been created. If entry is initialing or progressing then errors occur.*/
+			if (beamform_entry->beamform_entry_state != BEAMFORMING_ENTRY_STATE_INITIALIZED &&
+			    beamform_entry->beamform_entry_state != BEAMFORMING_ENTRY_STATE_PROGRESSED)
+				return false;
+			else
+				beamform_entry->beamform_entry_state = BEAMFORMING_ENTRY_STATE_INITIALIZEING;
+		}
+		beamform_entry->beamform_entry_state = BEAMFORMING_ENTRY_STATE_INITIALIZED;
+		phydm_sta_info_update(dm, sta_idx, beamform_entry);
+	}
+
+	*bfer_bfee_idx = (bfer_idx << 4) | bfee_idx;
+	PHYDM_DBG(dm, DBG_TXBF,
+		  "[%s] End: bfer_idx=0x%X, bfee_idx=0x%X, bfer_bfee_idx=0x%X\n",
+		  __func__, bfer_idx, bfee_idx, *bfer_bfee_idx);
+
+	return true;
+}
+
+void beamforming_deinit_entry(
+	void *dm_void,
+	u8 *RA)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	u8 idx = 0;
+
+	struct _RT_BEAMFORMER_ENTRY *bfer_entry = phydm_beamforming_get_bfer_entry_by_addr(dm, RA, &idx);
+	struct _RT_BEAMFORMEE_ENTRY *bfee_entry = phydm_beamforming_get_bfee_entry_by_addr(dm, RA, &idx);
+	boolean ret = false;
+
+	PHYDM_DBG(dm, DBG_TXBF, "%s Start!\n", __func__);
+
+	if (bfee_entry != NULL) {
+		PHYDM_DBG(dm, DBG_TXBF, "%s, bfee_entry\n", __func__);
+		bfee_entry->is_used = false;
+		bfee_entry->beamform_entry_cap = BEAMFORMING_CAP_NONE;
+		bfee_entry->is_beamforming_in_progress = false;
+		if (bfee_entry->is_mu_sta) {
+			dm->beamforming_info.beamformee_mu_cnt -= 1;
+			dm->beamforming_info.first_mu_bfee_index = phydm_beamforming_get_first_mu_bfee_entry_idx(dm);
+		} else
+			dm->beamforming_info.beamformee_su_cnt -= 1;
+		ret = true;
+	}
+
+	if (bfer_entry != NULL) {
+		PHYDM_DBG(dm, DBG_TXBF, "%s, bfer_entry\n", __func__);
+		bfer_entry->is_used = false;
+		bfer_entry->beamform_entry_cap = BEAMFORMING_CAP_NONE;
+		if (bfer_entry->is_mu_ap)
+			dm->beamforming_info.beamformer_mu_cnt -= 1;
+		else
+			dm->beamforming_info.beamformer_su_cnt -= 1;
+		ret = true;
+	}
+
+	if (ret == true)
+		hal_com_txbf_set(dm, TXBF_SET_SOUNDING_LEAVE, (u8 *)&idx);
+
+	PHYDM_DBG(dm, DBG_TXBF, "%s End, idx = 0x%X\n", __func__, idx);
+}
+
+boolean
+beamforming_start_v1(
+	void *dm_void,
+	u8 *RA,
+	boolean mode,
+	enum channel_width BW,
+	u8 rate)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	u8 idx = 0;
+	struct _RT_BEAMFORMEE_ENTRY *entry;
+	boolean ret = true;
+	struct _RT_BEAMFORMING_INFO *beam_info = &dm->beamforming_info;
+
+	entry = phydm_beamforming_get_bfee_entry_by_addr(dm, RA, &idx);
+
+	if (entry->is_used == false) {
+		entry->is_beamforming_in_progress = false;
+		return false;
+	} else {
+		if (entry->is_beamforming_in_progress)
+			return false;
+
+		entry->is_beamforming_in_progress = true;
+
+		if (mode == 1) {
+			if (!(entry->beamform_entry_cap & BEAMFORMER_CAP_HT_EXPLICIT)) {
+				entry->is_beamforming_in_progress = false;
+				return false;
+			}
+		} else if (mode == 0) {
+			if (!(entry->beamform_entry_cap & BEAMFORMER_CAP_VHT_SU)) {
+				entry->is_beamforming_in_progress = false;
+				return false;
+			}
+		}
+
+		if (entry->beamform_entry_state != BEAMFORMING_ENTRY_STATE_INITIALIZED && entry->beamform_entry_state != BEAMFORMING_ENTRY_STATE_PROGRESSED) {
+			entry->is_beamforming_in_progress = false;
+			return false;
+		} else {
+			entry->beamform_entry_state = BEAMFORMING_ENTRY_STATE_PROGRESSING;
+			entry->is_sound = true;
+		}
+	}
+
+	entry->sound_bw = BW;
+	beam_info->beamformee_cur_idx = idx;
+	phydm_beamforming_ndpa_rate(dm, BW, rate);
+	hal_com_txbf_set(dm, TXBF_SET_SOUNDING_STATUS, (u8 *)&idx);
+
+	if (mode == 1)
+		ret = beamforming_send_ht_ndpa_packet(dm, RA, BW, NORMAL_QUEUE);
+	else
+		ret = beamforming_send_vht_ndpa_packet(dm, RA, entry->aid, BW, NORMAL_QUEUE);
+
+	if (ret == false) {
+		beamforming_leave(dm, RA);
+		entry->is_beamforming_in_progress = false;
+		return false;
+	}
+
+	PHYDM_DBG(dm, DBG_TXBF, "%s  idx %d\n", __func__, idx);
+	return true;
+}
+
+boolean
+beamforming_start_sw(
+	void *dm_void,
+	u8 idx,
+	u8 mode,
+	enum channel_width BW)
+{
+	u8 *ra = NULL;
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct _RT_BEAMFORMEE_ENTRY *entry;
+	boolean ret = true;
+	struct _RT_BEAMFORMING_INFO *beam_info = &dm->beamforming_info;
+#ifdef SUPPORT_MU_BF
+#if (SUPPORT_MU_BF == 1)
+	u8 i, poll_sta_cnt = 0;
+	boolean is_get_first_bfee = false;
+#endif
+#endif
+
+	if (beam_info->is_mu_sounding) {
+		beam_info->is_mu_sounding_in_progress = true;
+		entry = &beam_info->beamformee_entry[idx];
+		ra = entry->mac_addr;
+
+	} else {
+		entry = &beam_info->beamformee_entry[idx];
+
+		if (entry->is_used == false) {
+			PHYDM_DBG(dm, DBG_TXBF,
+				  "Skip Beamforming, no entry for idx =%d\n",
+				  idx);
+			entry->is_beamforming_in_progress = false;
+			return false;
+		}
+
+		if (entry->is_beamforming_in_progress) {
+			PHYDM_DBG(dm, DBG_TXBF,
+				  "is_beamforming_in_progress, skip...\n");
+			return false;
+		}
+
+		entry->is_beamforming_in_progress = true;
+		ra = entry->mac_addr;
+
+		if (mode == SOUNDING_SW_HT_TIMER || mode == SOUNDING_HW_HT_TIMER || mode == SOUNDING_AUTO_HT_TIMER) {
+			if (!(entry->beamform_entry_cap & BEAMFORMER_CAP_HT_EXPLICIT)) {
+				entry->is_beamforming_in_progress = false;
+				PHYDM_DBG(dm, DBG_TXBF,
+					  "%s Return by not support BEAMFORMER_CAP_HT_EXPLICIT <==\n",
+					  __func__);
+				return false;
+			}
+		} else if (mode == SOUNDING_SW_VHT_TIMER || mode == SOUNDING_HW_VHT_TIMER || mode == SOUNDING_AUTO_VHT_TIMER) {
+			if (!(entry->beamform_entry_cap & BEAMFORMER_CAP_VHT_SU)) {
+				entry->is_beamforming_in_progress = false;
+				PHYDM_DBG(dm, DBG_TXBF,
+					  "%s Return by not support BEAMFORMER_CAP_VHT_SU <==\n",
+					  __func__);
+				return false;
+			}
+		}
+		if (entry->beamform_entry_state != BEAMFORMING_ENTRY_STATE_INITIALIZED && entry->beamform_entry_state != BEAMFORMING_ENTRY_STATE_PROGRESSED) {
+			entry->is_beamforming_in_progress = false;
+			PHYDM_DBG(dm, DBG_TXBF,
+				  "%s Return by incorrect beamform_entry_state(%d) <==\n",
+				  __func__, entry->beamform_entry_state);
+			return false;
+		} else {
+			entry->beamform_entry_state = BEAMFORMING_ENTRY_STATE_PROGRESSING;
+			entry->is_sound = true;
+		}
+
+		beam_info->beamformee_cur_idx = idx;
+	}
+
+	/*@2014.12.22 Luke: Need to be checked*/
+	/*@GET_TXBF_INFO(adapter)->fTxbfSet(adapter, TXBF_SET_SOUNDING_STATUS, (u8*)&idx);*/
+
+	if (mode == SOUNDING_SW_HT_TIMER || mode == SOUNDING_HW_HT_TIMER || mode == SOUNDING_AUTO_HT_TIMER)
+		ret = beamforming_send_ht_ndpa_packet(dm, ra, BW, NORMAL_QUEUE);
+	else
+		ret = beamforming_send_vht_ndpa_packet(dm, ra, entry->aid, BW, NORMAL_QUEUE);
+
+	if (ret == false) {
+		beamforming_leave(dm, ra);
+		entry->is_beamforming_in_progress = false;
+		return false;
+	}
+
+/*@--------------------------
+	 * Send BF Report Poll for MU BF
+	--------------------------*/
+#ifdef SUPPORT_MU_BF
+#if (SUPPORT_MU_BF == 1)
+	if (beam_info->beamformee_mu_cnt <= 1)
+		goto out;
+
+	/* @More than 1 MU STA*/
+	for (i = 0; i < BEAMFORMEE_ENTRY_NUM; i++) {
+		entry = &beam_info->beamformee_entry[i];
+		if (!entry->is_mu_sta)
+			continue;
+
+		if (!is_get_first_bfee) {
+			is_get_first_bfee = true;
+			continue;
+		}
+
+		poll_sta_cnt++;
+		if (poll_sta_cnt == (beam_info->beamformee_mu_cnt - 1)) /* The last STA*/
+			send_sw_vht_bf_report_poll(dm, entry->mac_addr, true);
+		else
+			send_sw_vht_bf_report_poll(dm, entry->mac_addr, false);
+	}
+out:
+#endif
+#endif
+	return true;
+}
+
+boolean
+beamforming_start_fw(
+	void *dm_void,
+	u8 idx)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct _RT_BEAMFORMEE_ENTRY *entry;
+	struct _RT_BEAMFORMING_INFO *beam_info = &dm->beamforming_info;
+
+	entry = &beam_info->beamformee_entry[idx];
+	if (entry->is_used == false) {
+		PHYDM_DBG(dm, DBG_TXBF,
+			  "Skip Beamforming, no entry for idx =%d\n", idx);
+		return false;
+	}
+
+	entry->beamform_entry_state = BEAMFORMING_ENTRY_STATE_PROGRESSING;
+	entry->is_sound = true;
+	hal_com_txbf_set(dm, TXBF_SET_SOUNDING_FW_NDPA, (u8 *)&idx);
+
+	PHYDM_DBG(dm, DBG_TXBF, "[%s] End, idx=0x%X\n", __func__, idx);
+	return true;
+}
+
+void beamforming_check_sounding_success(
+	void *dm_void,
+	boolean status)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct _RT_BEAMFORMING_INFO *beam_info = &dm->beamforming_info;
+	struct _RT_BEAMFORMEE_ENTRY *entry = &beam_info->beamformee_entry[beam_info->beamformee_cur_idx];
+
+	PHYDM_DBG(dm, DBG_TXBF, "[David]@%s Start!\n", __func__);
+
+	if (status == 1) {
+		if (entry->log_status_fail_cnt == 21)
+			beamforming_dym_period(dm, status);
+		entry->log_status_fail_cnt = 0;
+	} else if (entry->log_status_fail_cnt <= 20) {
+		entry->log_status_fail_cnt++;
+		PHYDM_DBG(dm, DBG_TXBF, "%s log_status_fail_cnt %d\n", __func__,
+			  entry->log_status_fail_cnt);
+	}
+	if (entry->log_status_fail_cnt > 20) {
+		entry->log_status_fail_cnt = 21;
+		PHYDM_DBG(dm, DBG_TXBF,
+			  "%s log_status_fail_cnt > 20, Stop SOUNDING\n",
+			  __func__);
+		beamforming_dym_period(dm, status);
+	}
+}
+
+void phydm_beamforming_end_sw(
+	void *dm_void,
+	boolean status)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct _RT_BEAMFORMING_INFO *beam_info = &dm->beamforming_info;
+	struct _RT_BEAMFORMEE_ENTRY *entry = &beam_info->beamformee_entry[beam_info->beamformee_cur_idx];
+
+	if (beam_info->is_mu_sounding) {
+		PHYDM_DBG(dm, DBG_TXBF, "%s: MU sounding done\n", __func__);
+		beam_info->is_mu_sounding_in_progress = false;
+		hal_com_txbf_set(dm, TXBF_SET_SOUNDING_STATUS,
+				 (u8 *)&beam_info->beamformee_cur_idx);
+	} else {
+		if (entry->beamform_entry_state != BEAMFORMING_ENTRY_STATE_PROGRESSING) {
+			PHYDM_DBG(dm, DBG_TXBF, "[%s] BeamformStatus %d\n",
+				  __func__, entry->beamform_entry_state);
+			return;
+		}
+
+		if (beam_info->tx_bf_data_rate >= ODM_RATEVHTSS3MCS7 && beam_info->tx_bf_data_rate <= ODM_RATEVHTSS3MCS9 && !beam_info->snding3ss) {
+			PHYDM_DBG(dm, DBG_TXBF,
+				  "[%s] VHT3SS 7,8,9, do not apply V matrix.\n",
+				  __func__);
+			entry->beamform_entry_state = BEAMFORMING_ENTRY_STATE_INITIALIZED;
+			hal_com_txbf_set(dm, TXBF_SET_SOUNDING_STATUS,
+					 (u8 *)&beam_info->beamformee_cur_idx);
+		} else if (status == 1) {
+			entry->log_status_fail_cnt = 0;
+			entry->beamform_entry_state = BEAMFORMING_ENTRY_STATE_PROGRESSED;
+			hal_com_txbf_set(dm, TXBF_SET_SOUNDING_STATUS,
+					 (u8 *)&beam_info->beamformee_cur_idx);
+		} else {
+			entry->log_status_fail_cnt++;
+			entry->beamform_entry_state = BEAMFORMING_ENTRY_STATE_INITIALIZED;
+			hal_com_txbf_set(dm, TXBF_SET_TX_PATH_RESET,
+					 (u8 *)&beam_info->beamformee_cur_idx);
+			PHYDM_DBG(dm, DBG_TXBF, "[%s] log_status_fail_cnt %d\n",
+				  __func__, entry->log_status_fail_cnt);
+		}
+
+		if (entry->log_status_fail_cnt > 50) {
+			PHYDM_DBG(dm, DBG_TXBF,
+				  "%s log_status_fail_cnt > 50, Stop SOUNDING\n",
+				  __func__);
+			entry->is_sound = false;
+			beamforming_deinit_entry(dm, entry->mac_addr);
+
+			/*@Modified by David - Every action of deleting entry should follow by Notify*/
+			phydm_beamforming_notify(dm);
+		}
+
+		entry->is_beamforming_in_progress = false;
+	}
+	PHYDM_DBG(dm, DBG_TXBF, "%s: status=%d\n", __func__, status);
+}
+
+void beamforming_timer_callback(
+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
+	void *dm_void
+#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
+	void *context
+#endif
+	)
+{
+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
+	void *adapter = (void *)context;
+	PHAL_DATA_TYPE hal_data = GET_HAL_DATA(((PADAPTER)adapter));
+	struct dm_struct *dm = &hal_data->odmpriv;
+#endif
+	boolean ret = false;
+	struct _RT_BEAMFORMING_INFO *beam_info = &(dm->beamforming_info);
+	struct _RT_BEAMFORMEE_ENTRY *entry = &(beam_info->beamformee_entry[beam_info->beamformee_cur_idx]);
+	struct _RT_SOUNDING_INFO *sound_info = &(beam_info->sounding_info);
+	boolean is_beamforming_in_progress;
+
+	PHYDM_DBG(dm, DBG_TXBF, "%s Start!\n", __func__);
+
+	if (beam_info->is_mu_sounding)
+		is_beamforming_in_progress = beam_info->is_mu_sounding_in_progress;
+	else
+		is_beamforming_in_progress = entry->is_beamforming_in_progress;
+
+	if (is_beamforming_in_progress) {
+		PHYDM_DBG(dm, DBG_TXBF,
+			  "is_beamforming_in_progress, reset it\n");
+		phydm_beamforming_end_sw(dm, 0);
+	}
+
+	ret = phydm_beamforming_select_beam_entry(dm, beam_info);
+#if (SUPPORT_MU_BF == 1)
+	if (ret && beam_info->beamformee_mu_cnt > 1)
+		ret = 1;
+	else
+		ret = 0;
+#endif
+	if (ret)
+		ret = beamforming_start_sw(dm, sound_info->sound_idx, sound_info->sound_mode, sound_info->sound_bw);
+	else
+		PHYDM_DBG(dm, DBG_TXBF,
+			  "%s, Error value return from BeamformingStart_V2\n",
+			  __func__);
+
+	if (beam_info->beamformee_su_cnt != 0 || beam_info->beamformee_mu_cnt > 1) {
+		if (sound_info->sound_mode == SOUNDING_SW_VHT_TIMER || sound_info->sound_mode == SOUNDING_SW_HT_TIMER)
+			odm_set_timer(dm, &beam_info->beamforming_timer, sound_info->sound_period);
+		else {
+			u32 val = (sound_info->sound_period << 16) | HAL_TIMER_TXBF;
+			phydm_set_hw_reg_handler_interface(dm, HW_VAR_HW_REG_TIMER_RESTART, (u8 *)(&val));
+		}
+	}
+}
+
+void beamforming_sw_timer_callback(
+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
+	struct phydm_timer_list *timer
+#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
+	void *function_context
+#endif
+	)
+{
+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
+	void *adapter = (void *)timer->Adapter;
+	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter));
+	struct dm_struct *dm = &hal_data->DM_OutSrc;
+
+	PHYDM_DBG(dm, DBG_TXBF, "[%s] Start!\n", __func__);
+	beamforming_timer_callback(dm);
+#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
+	struct dm_struct *dm = (struct dm_struct *)function_context;
+	void *adapter = dm->adapter;
+
+	if (*dm->is_net_closed == true)
+		return;
+	phydm_run_in_thread_cmd(dm, beamforming_timer_callback, adapter);
+#endif
+}
+
+void phydm_beamforming_init(
+	void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct _RT_BEAMFORMING_INFO *beam_info = &dm->beamforming_info;
+	struct _RT_BEAMFORMING_OID_INFO *beam_oid_info = &beam_info->beamforming_oid_info;
+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
+	void *adapter = dm->adapter;
+	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter));
+
+#ifdef BEAMFORMING_VERSION_1
+	if (hal_data->beamforming_version != BEAMFORMING_VERSION_1) {
+		return;
+	}
+#endif
+#endif
+
+	beam_oid_info->sound_oid_mode = SOUNDING_STOP_OID_TIMER;
+	PHYDM_DBG(dm, DBG_TXBF, "%s mode (%d)\n", __func__,
+		  beam_oid_info->sound_oid_mode);
+
+	beam_info->beamformee_su_cnt = 0;
+	beam_info->beamformer_su_cnt = 0;
+	beam_info->beamformee_mu_cnt = 0;
+	beam_info->beamformer_mu_cnt = 0;
+	beam_info->beamformee_mu_reg_maping = 0;
+	beam_info->mu_ap_index = 0;
+	beam_info->is_mu_sounding = false;
+	beam_info->first_mu_bfee_index = 0xFF;
+	beam_info->apply_v_matrix = true;
+	beam_info->snding3ss = false;
+
+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
+	beam_info->source_adapter = dm->adapter;
+#endif
+	hal_com_txbf_beamform_init(dm);
+}
+
+boolean
+phydm_acting_determine(
+	void *dm_void,
+	enum phydm_acting_type type)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	boolean ret = false;
+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
+	void *adapter = dm->beamforming_info.source_adapter;
+#else
+	struct _ADAPTER *adapter = dm->adapter;
+#endif
+
+#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
+	if (type == phydm_acting_as_ap)
+		ret = ACTING_AS_AP(adapter);
+	else if (type == phydm_acting_as_ibss)
+		ret = ACTING_AS_IBSS(((PADAPTER)(adapter)));
+#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
+	struct mlme_priv *pmlmepriv = &adapter->mlmepriv;
+
+	if (type == phydm_acting_as_ap)
+		ret = check_fwstate(pmlmepriv, WIFI_AP_STATE);
+	else if (type == phydm_acting_as_ibss)
+		ret = check_fwstate(pmlmepriv, WIFI_ADHOC_STATE) || check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE);
+#endif
+
+	return ret;
+}
+
+void beamforming_enter(
+	void *dm_void,
+	u16 sta_idx)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	u8 bfer_bfee_idx = 0xff;
+
+	if (beamforming_init_entry(dm, sta_idx, &bfer_bfee_idx))
+		hal_com_txbf_set(dm, TXBF_SET_SOUNDING_ENTER, (u8 *)&bfer_bfee_idx);
+
+	PHYDM_DBG(dm, DBG_TXBF, "[%s] End!\n", __func__);
+}
+
+void beamforming_leave(
+	void *dm_void,
+	u8 *RA)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+
+	if (RA != NULL) {
+		beamforming_deinit_entry(dm, RA);
+		phydm_beamforming_notify(dm);
+	}
+
+	PHYDM_DBG(dm, DBG_TXBF, "[%s] End!!\n", __func__);
+}
+
+#if 0
+/* Nobody calls this function */
+void
+phydm_beamforming_set_txbf_en(
+	void		*dm_void,
+	u8			mac_id,
+	boolean			is_txbf
+)
+{
+	struct dm_struct				*dm = (struct dm_struct *)dm_void;
+	u8					idx = 0;
+	struct _RT_BEAMFORMEE_ENTRY	*entry;
+
+	PHYDM_DBG(dm, DBG_TXBF, "%s Start!\n", __func__);
+
+	entry = phydm_beamforming_get_entry_by_mac_id(dm, mac_id, &idx);
+
+	if (entry == NULL)
+		return;
+	else
+		entry->is_txbf = is_txbf;
+
+	PHYDM_DBG(dm, DBG_TXBF, "%s mac_id %d TxBF %d\n", __func__,
+		  entry->mac_id, entry->is_txbf);
+
+	phydm_beamforming_notify(dm);
+}
+#endif
+
+enum beamforming_cap
+phydm_beamforming_get_beam_cap(
+	void *dm_void,
+	struct _RT_BEAMFORMING_INFO *beam_info)
+{
+	u8 i;
+	boolean is_self_beamformer = false;
+	boolean is_self_beamformee = false;
+	struct _RT_BEAMFORMEE_ENTRY beamformee_entry;
+	struct _RT_BEAMFORMER_ENTRY beamformer_entry;
+	enum beamforming_cap beamform_cap = BEAMFORMING_CAP_NONE;
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+
+	PHYDM_DBG(dm, DBG_TXBF, "[%s] Start!\n", __func__);
+
+	for (i = 0; i < BEAMFORMEE_ENTRY_NUM; i++) {
+		beamformee_entry = beam_info->beamformee_entry[i];
+
+		if (beamformee_entry.is_used) {
+			is_self_beamformer = true;
+			PHYDM_DBG(dm, DBG_TXBF,
+				  "[%s] BFee entry %d is_used=true\n", __func__,
+				  i);
+			break;
+		}
+	}
+
+	for (i = 0; i < BEAMFORMER_ENTRY_NUM; i++) {
+		beamformer_entry = beam_info->beamformer_entry[i];
+
+		if (beamformer_entry.is_used) {
+			is_self_beamformee = true;
+			PHYDM_DBG(dm, DBG_TXBF,
+				  "[%s]: BFer entry %d is_used=true\n",
+				  __func__, i);
+			break;
+		}
+	}
+
+	if (is_self_beamformer)
+		beamform_cap = (enum beamforming_cap)(beamform_cap | BEAMFORMER_CAP);
+	if (is_self_beamformee)
+		beamform_cap = (enum beamforming_cap)(beamform_cap | BEAMFORMEE_CAP);
+
+	return beamform_cap;
+}
+
+boolean
+beamforming_control_v1(
+	void *dm_void,
+	u8 *RA,
+	u8 AID,
+	u8 mode,
+	enum channel_width BW,
+	u8 rate)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	boolean ret = true;
+
+	PHYDM_DBG(dm, DBG_TXBF, "%s Start!\n", __func__);
+
+	PHYDM_DBG(dm, DBG_TXBF, "AID (%d), mode (%d), BW (%d)\n", AID, mode,
+		  BW);
+
+	switch (mode) {
+	case 0:
+		ret = beamforming_start_v1(dm, RA, 0, BW, rate);
+		break;
+	case 1:
+		ret = beamforming_start_v1(dm, RA, 1, BW, rate);
+		break;
+	case 2:
+		phydm_beamforming_ndpa_rate(dm, BW, rate);
+		ret = beamforming_send_vht_ndpa_packet(dm, RA, AID, BW, NORMAL_QUEUE);
+		break;
+	case 3:
+		phydm_beamforming_ndpa_rate(dm, BW, rate);
+		ret = beamforming_send_ht_ndpa_packet(dm, RA, BW, NORMAL_QUEUE);
+		break;
+	}
+	return ret;
+}
+
+/*Only OID uses this function*/
+boolean
+phydm_beamforming_control_v2(
+	void *dm_void,
+	u8 idx,
+	u8 mode,
+	enum channel_width BW,
+	u16 period)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct _RT_BEAMFORMING_INFO *beam_info = &dm->beamforming_info;
+	struct _RT_BEAMFORMING_OID_INFO *beam_oid_info = &beam_info->beamforming_oid_info;
+
+	PHYDM_DBG(dm, DBG_TXBF, "%s Start!\n", __func__);
+	PHYDM_DBG(dm, DBG_TXBF, "idx (%d), mode (%d), BW (%d), period (%d)\n",
+		  idx, mode, BW, period);
+
+	beam_oid_info->sound_oid_idx = idx;
+	beam_oid_info->sound_oid_mode = (enum sounding_mode)mode;
+	beam_oid_info->sound_oid_bw = BW;
+	beam_oid_info->sound_oid_period = period;
+
+	phydm_beamforming_notify(dm);
+
+	return true;
+}
+
+void phydm_beamforming_watchdog(
+	void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct _RT_BEAMFORMING_INFO *beam_info = &dm->beamforming_info;
+
+	PHYDM_DBG(dm, DBG_TXBF, "%s Start!\n", __func__);
+
+	if (beam_info->beamformee_su_cnt == 0)
+		return;
+
+	beamforming_dym_period(dm, 0);
+}
+enum beamforming_cap
+phydm_get_beamform_cap(
+	void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct cmn_sta_info *sta = NULL;
+	struct bf_cmn_info *bf_info = NULL;
+	struct _RT_BEAMFORMING_INFO *beam_info = &dm->beamforming_info;
+	void *adapter = dm->adapter;
+	enum beamforming_cap beamform_cap = BEAMFORMING_CAP_NONE;
+	u8 macid;
+	u8 ht_curbeamformcap = 0;
+	u16 vht_curbeamformcap = 0;
+
+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
+	PMGNT_INFO p_MgntInfo = &(((PADAPTER)(adapter))->MgntInfo);
+	PRT_VERY_HIGH_THROUGHPUT p_vht_info = GET_VHT_INFO(p_MgntInfo);
+	PRT_HIGH_THROUGHPUT p_ht_info = GET_HT_INFO(p_MgntInfo);
+
+	ht_curbeamformcap = p_ht_info->HtCurBeamform;
+	vht_curbeamformcap = p_vht_info->VhtCurBeamform;
+
+	PHYDM_DBG(dm, DBG_ANT_DIV,
+		  "[%s] WIN ht_curcap = %d ; vht_curcap = %d\n", __func__,
+		  ht_curbeamformcap, vht_curbeamformcap);
+
+	if (TEST_FLAG(ht_curbeamformcap, BEAMFORMING_HT_BEAMFORMER_ENABLE)) /*We are Beamformee because the STA is Beamformer*/
+		beamform_cap = (enum beamforming_cap)(beamform_cap | (BEAMFORMEE_CAP_HT_EXPLICIT | BEAMFORMEE_CAP));
+
+	/*We are Beamformer because the STA is Beamformee*/
+	if (TEST_FLAG(ht_curbeamformcap, BEAMFORMING_HT_BEAMFORMEE_ENABLE))
+		beamform_cap = (enum beamforming_cap)(beamform_cap | (BEAMFORMER_CAP_HT_EXPLICIT | BEAMFORMER_CAP));
+
+#if (ODM_IC_11AC_SERIES_SUPPORT == 1)
+
+	/* We are Beamformee because the STA is SU Beamformer*/
+	if (TEST_FLAG(vht_curbeamformcap, BEAMFORMING_VHT_BEAMFORMER_ENABLE))
+		beamform_cap = (enum beamforming_cap)(beamform_cap | (BEAMFORMEE_CAP_VHT_SU | BEAMFORMEE_CAP));
+
+	/* We are Beamformer because the STA is SU Beamformee*/
+	if (TEST_FLAG(vht_curbeamformcap, BEAMFORMING_VHT_BEAMFORMEE_ENABLE))
+		beamform_cap = (enum beamforming_cap)(beamform_cap | (BEAMFORMER_CAP_VHT_SU | BEAMFORMER_CAP));
+
+	/* We are Beamformee because the STA is MU Beamformer*/
+	if (TEST_FLAG(vht_curbeamformcap, BEAMFORMING_VHT_MU_MIMO_AP_ENABLE))
+		beamform_cap = (enum beamforming_cap)(beamform_cap | (BEAMFORMEE_CAP_VHT_MU | BEAMFORMEE_CAP));
+#endif
+#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
+
+	for (macid = 0; macid < ODM_ASSOCIATE_ENTRY_NUM; macid++) {
+		sta = dm->phydm_sta_info[macid];
+
+		if (!is_sta_active(sta))
+			continue;
+
+		bf_info = &sta->bf_info;
+		vht_curbeamformcap = bf_info->vht_beamform_cap;
+		ht_curbeamformcap = bf_info->ht_beamform_cap;
+
+		if (TEST_FLAG(ht_curbeamformcap, BEAMFORMING_HT_BEAMFORMER_ENABLE)) /*We are Beamformee because the STA is Beamformer*/
+			beamform_cap = (enum beamforming_cap)(beamform_cap | (BEAMFORMEE_CAP_HT_EXPLICIT | BEAMFORMEE_CAP));
+
+		/*We are Beamformer because the STA is Beamformee*/
+		if (TEST_FLAG(ht_curbeamformcap, BEAMFORMING_HT_BEAMFORMEE_ENABLE))
+			beamform_cap = (enum beamforming_cap)(beamform_cap | (BEAMFORMER_CAP_HT_EXPLICIT | BEAMFORMER_CAP));
+
+#if (ODM_IC_11AC_SERIES_SUPPORT == 1)
+		/* We are Beamformee because the STA is SU Beamformer*/
+		if (TEST_FLAG(vht_curbeamformcap, BEAMFORMING_VHT_BEAMFORMER_ENABLE))
+			beamform_cap = (enum beamforming_cap)(beamform_cap | (BEAMFORMEE_CAP_VHT_SU | BEAMFORMEE_CAP));
+
+		/* We are Beamformer because the STA is SU Beamformee*/
+		if (TEST_FLAG(vht_curbeamformcap, BEAMFORMING_VHT_BEAMFORMEE_ENABLE))
+			beamform_cap = (enum beamforming_cap)(beamform_cap | (BEAMFORMER_CAP_VHT_SU | BEAMFORMER_CAP));
+
+		/* We are Beamformee because the STA is MU Beamformer*/
+		if (TEST_FLAG(vht_curbeamformcap, BEAMFORMING_VHT_MU_MIMO_AP_ENABLE))
+			beamform_cap = (enum beamforming_cap)(beamform_cap | (BEAMFORMEE_CAP_VHT_MU | BEAMFORMEE_CAP));
+#endif
+	}
+	PHYDM_DBG(dm, DBG_ANT_DIV, "[%s] CE ht_curcap = %d ; vht_curcap = %d\n",
+		  __func__, ht_curbeamformcap, vht_curbeamformcap);
+
+#endif
+
+	return beamform_cap;
+}
+
+#endif
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/phydm_beamforming.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/phydm_beamforming.h
--- linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/phydm_beamforming.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/phydm_beamforming.h	2020-04-10 16:35:06.823660394 +0300
@@ -0,0 +1,369 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017  Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * The full GNU General Public License is included in this distribution in the
+ * file called LICENSE.
+ *
+ * Contact Information:
+ * wlanfae <wlanfae@realtek.com>
+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
+ * Hsinchu 300, Taiwan.
+ *
+ * Larry Finger <Larry.Finger@lwfinger.net>
+ *
+ *****************************************************************************/
+
+#ifndef __INC_PHYDM_BEAMFORMING_H
+#define __INC_PHYDM_BEAMFORMING_H
+
+#ifndef BEAMFORMING_SUPPORT
+#define BEAMFORMING_SUPPORT 0
+#endif
+
+/*@Beamforming Related*/
+#include "txbf/halcomtxbf.h"
+#include "txbf/haltxbfjaguar.h"
+#include "txbf/haltxbf8192e.h"
+#include "txbf/haltxbf8814a.h"
+#include "txbf/haltxbf8822b.h"
+#include "txbf/haltxbfinterface.h"
+
+#if (BEAMFORMING_SUPPORT == 1)
+
+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
+
+#define eq_mac_addr(a, b) (((a)[0] == (b)[0] && (a)[1] == (b)[1] && (a)[2] == (b)[2] && (a)[3] == (b)[3] && (a)[4] == (b)[4] && (a)[5] == (b)[5]) ? 1 : 0)
+#define cp_mac_addr(des, src) ((des)[0] = (src)[0], (des)[1] = (src)[1], (des)[2] = (src)[2], (des)[3] = (src)[3], (des)[4] = (src)[4], (des)[5] = (src)[5])
+
+#endif
+
+#define MAX_BEAMFORMEE_SU 2
+#define MAX_BEAMFORMER_SU 2
+#if (RTL8822B_SUPPORT == 1)
+#define MAX_BEAMFORMEE_MU 6
+#define MAX_BEAMFORMER_MU 1
+#else
+#define MAX_BEAMFORMEE_MU 0
+#define MAX_BEAMFORMER_MU 0
+#endif
+
+#define BEAMFORMEE_ENTRY_NUM (MAX_BEAMFORMEE_SU + MAX_BEAMFORMEE_MU)
+#define BEAMFORMER_ENTRY_NUM (MAX_BEAMFORMER_SU + MAX_BEAMFORMER_MU)
+
+#if (DM_ODM_SUPPORT_TYPE == ODM_CE)
+/*@for different naming between WIN and CE*/
+#define BEACON_QUEUE BCN_QUEUE_INX
+#define NORMAL_QUEUE MGT_QUEUE_INX
+#define RT_DISABLE_FUNC RTW_DISABLE_FUNC
+#define RT_ENABLE_FUNC RTW_ENABLE_FUNC
+#endif
+
+enum beamforming_entry_state {
+	BEAMFORMING_ENTRY_STATE_UNINITIALIZE,
+	BEAMFORMING_ENTRY_STATE_INITIALIZEING,
+	BEAMFORMING_ENTRY_STATE_INITIALIZED,
+	BEAMFORMING_ENTRY_STATE_PROGRESSING,
+	BEAMFORMING_ENTRY_STATE_PROGRESSED
+};
+
+enum beamforming_notify_state {
+	BEAMFORMING_NOTIFY_NONE,
+	BEAMFORMING_NOTIFY_ADD,
+	BEAMFORMING_NOTIFY_DELETE,
+	BEAMFORMEE_NOTIFY_ADD_SU,
+	BEAMFORMEE_NOTIFY_DELETE_SU,
+	BEAMFORMEE_NOTIFY_ADD_MU,
+	BEAMFORMEE_NOTIFY_DELETE_MU,
+	BEAMFORMING_NOTIFY_RESET
+};
+
+enum beamforming_cap {
+	BEAMFORMING_CAP_NONE = 0x0,
+	BEAMFORMER_CAP_HT_EXPLICIT = BIT(1),
+	BEAMFORMEE_CAP_HT_EXPLICIT = BIT(2),
+	BEAMFORMER_CAP_VHT_SU = BIT(5), /* @Self has er Cap, because Reg er  & peer ee */
+	BEAMFORMEE_CAP_VHT_SU = BIT(6), /* @Self has ee Cap, because Reg ee & peer er */
+	BEAMFORMER_CAP_VHT_MU = BIT(7), /* @Self has er Cap, because Reg er  & peer ee */
+	BEAMFORMEE_CAP_VHT_MU = BIT(8), /* @Self has ee Cap, because Reg ee & peer er */
+	BEAMFORMER_CAP = BIT(9),
+	BEAMFORMEE_CAP = BIT(10),
+};
+
+enum sounding_mode {
+	SOUNDING_SW_VHT_TIMER = 0x0,
+	SOUNDING_SW_HT_TIMER = 0x1,
+	sounding_stop_all_timer = 0x2,
+	SOUNDING_HW_VHT_TIMER = 0x3,
+	SOUNDING_HW_HT_TIMER = 0x4,
+	SOUNDING_STOP_OID_TIMER = 0x5,
+	SOUNDING_AUTO_VHT_TIMER = 0x6,
+	SOUNDING_AUTO_HT_TIMER = 0x7,
+	SOUNDING_FW_VHT_TIMER = 0x8,
+	SOUNDING_FW_HT_TIMER = 0x9,
+};
+
+struct _RT_BEAMFORM_STAINFO {
+	u8 *ra;
+	u16 aid;
+	u16 mac_id;
+	u8 my_mac_addr[6];
+	/*WIRELESS_MODE				wireless_mode;*/
+	enum channel_width bw;
+	enum beamforming_cap beamform_cap;
+	u8 ht_beamform_cap;
+	u16 vht_beamform_cap;
+	u8 cur_beamform;
+	u16 cur_beamform_vht;
+};
+
+struct _RT_BEAMFORMEE_ENTRY {
+	boolean is_used;
+	boolean is_txbf;
+	boolean is_sound;
+	u16 aid; /*Used to construct AID field of NDPA packet.*/
+	u16 mac_id; /*Used to Set Reg42C in IBSS mode. */
+	u16 p_aid; /*@Used to fill Reg42C & Reg714 to compare with P_AID of Tx DESC. */
+	u8 g_id; /*Used to fill Tx DESC*/
+	u8 my_mac_addr[6];
+	u8 mac_addr[6]; /*@Used to fill Reg6E4 to fill Mac address of CSI report frame.*/
+	enum channel_width sound_bw; /*Sounding band_width*/
+	u16 sound_period;
+	enum beamforming_cap beamform_entry_cap;
+	enum beamforming_entry_state beamform_entry_state;
+	boolean is_beamforming_in_progress;
+	/*@u8	log_seq;									// Move to _RT_BEAMFORMER_ENTRY*/
+	/*@u16	log_retry_cnt:3;		// 0~4				// Move to _RT_BEAMFORMER_ENTRY*/
+	/*@u16	LogSuccessCnt:2;		// 0~2				// Move to _RT_BEAMFORMER_ENTRY*/
+	u16 log_status_fail_cnt : 5; /* @0~21 */
+	u16 default_csi_cnt : 5; /* @0~21 */
+	u8 csi_matrix[327];
+	u16 csi_matrix_len;
+	u8 num_of_sounding_dim;
+	u8 comp_steering_num_of_bfer;
+	u8 su_reg_index;
+	/*@For MU-MIMO*/
+	boolean is_mu_sta;
+	u8 mu_reg_index;
+	u8 gid_valid[8];
+	u8 user_position[16];
+};
+
+struct _RT_BEAMFORMER_ENTRY {
+	boolean is_used;
+	/*P_AID of BFer entry is probably not used*/
+	u16 p_aid; /*@Used to fill Reg42C & Reg714 to compare with P_AID of Tx DESC. */
+	u8 g_id;
+	u8 my_mac_addr[6];
+	u8 mac_addr[6];
+	enum beamforming_cap beamform_entry_cap;
+	u8 num_of_sounding_dim;
+	u8 clock_reset_times; /*@Modified by Jeffery @2015-04-10*/
+	u8 pre_log_seq; /*@Modified by Jeffery @2015-03-30*/
+	u8 log_seq; /*@Modified by Jeffery @2014-10-29*/
+	u16 log_retry_cnt : 3; /*@Modified by Jeffery @2014-10-29*/
+	u16 log_success : 2; /*@Modified by Jeffery @2014-10-29*/
+	u8 su_reg_index;
+	/*@For MU-MIMO*/
+	boolean is_mu_ap;
+	u8 gid_valid[8];
+	u8 user_position[16];
+	u16 aid;
+};
+
+struct _RT_SOUNDING_INFO {
+	u8 sound_idx;
+	enum channel_width sound_bw;
+	enum sounding_mode sound_mode;
+	u16 sound_period;
+};
+
+struct _RT_BEAMFORMING_OID_INFO {
+	u8 sound_oid_idx;
+	enum channel_width sound_oid_bw;
+	enum sounding_mode sound_oid_mode;
+	u16 sound_oid_period;
+};
+
+struct _RT_BEAMFORMING_INFO {
+	enum beamforming_cap beamform_cap;
+	struct _RT_BEAMFORMEE_ENTRY beamformee_entry[BEAMFORMEE_ENTRY_NUM];
+	struct _RT_BEAMFORMER_ENTRY beamformer_entry[BEAMFORMER_ENTRY_NUM];
+	struct _RT_BEAMFORM_STAINFO beamform_sta_info;
+	u8 beamformee_cur_idx;
+	struct phydm_timer_list beamforming_timer;
+	struct phydm_timer_list mu_timer;
+	struct _RT_SOUNDING_INFO sounding_info;
+	struct _RT_BEAMFORMING_OID_INFO beamforming_oid_info;
+	struct _HAL_TXBF_INFO txbf_info;
+	u8 sounding_sequence;
+	u8 beamformee_su_cnt;
+	u8 beamformer_su_cnt;
+	u32 beamformee_su_reg_maping;
+	u32 beamformer_su_reg_maping;
+	/*@For MU-MINO*/
+	u8 beamformee_mu_cnt;
+	u8 beamformer_mu_cnt;
+	u32 beamformee_mu_reg_maping;
+	u8 mu_ap_index;
+	boolean is_mu_sounding;
+	u8 first_mu_bfee_index;
+	boolean is_mu_sounding_in_progress;
+	boolean dbg_disable_mu_tx;
+	boolean apply_v_matrix;
+	boolean snding3ss;
+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
+	void *source_adapter;
+#endif
+	/* @Control register */
+	u32 reg_mu_tx_ctrl; /* @For USB/SDIO interfaces aync I/O */
+	u8 tx_bf_data_rate;
+	u8 last_usb_hub;
+};
+
+void phydm_get_txbf_device_num(
+	void *dm_void,
+	u8 macid);
+
+struct _RT_NDPA_STA_INFO {
+	u16 aid : 12;
+	u16 feedback_type : 1;
+	u16 nc_index : 3;
+};
+
+enum phydm_acting_type {
+	phydm_acting_as_ibss = 0,
+	phydm_acting_as_ap = 1
+};
+
+enum beamforming_cap
+phydm_beamforming_get_entry_beam_cap_by_mac_id(
+	void *dm_void,
+	u8 mac_id);
+
+struct _RT_BEAMFORMEE_ENTRY *
+phydm_beamforming_get_bfee_entry_by_addr(
+	void *dm_void,
+	u8 *RA,
+	u8 *idx);
+
+struct _RT_BEAMFORMER_ENTRY *
+phydm_beamforming_get_bfer_entry_by_addr(
+	void *dm_void,
+	u8 *TA,
+	u8 *idx);
+
+void phydm_beamforming_notify(
+	void *dm_void);
+
+boolean
+phydm_acting_determine(
+	void *dm_void,
+	enum phydm_acting_type type);
+
+void beamforming_enter(
+	void *dm_void,
+	u16 sta_idx);
+
+void beamforming_leave(
+	void *dm_void,
+	u8 *RA);
+
+boolean
+beamforming_start_fw(
+	void *dm_void,
+	u8 idx);
+
+void beamforming_check_sounding_success(
+	void *dm_void,
+	boolean status);
+
+void phydm_beamforming_end_sw(
+	void *dm_void,
+	boolean status);
+
+void beamforming_timer_callback(
+	void *dm_void);
+
+void phydm_beamforming_init(
+	void *dm_void);
+
+enum beamforming_cap
+phydm_beamforming_get_beam_cap(
+	void *dm_void,
+	struct _RT_BEAMFORMING_INFO *beam_info);
+
+enum beamforming_cap
+phydm_get_beamform_cap(
+	void *dm_void);
+
+boolean
+beamforming_control_v1(
+	void *dm_void,
+	u8 *RA,
+	u8 AID,
+	u8 mode,
+	enum channel_width BW,
+	u8 rate);
+
+boolean
+phydm_beamforming_control_v2(
+	void *dm_void,
+	u8 idx,
+	u8 mode,
+	enum channel_width BW,
+	u16 period);
+
+void phydm_beamforming_watchdog(
+	void *dm_void);
+
+void beamforming_sw_timer_callback(
+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
+	struct phydm_timer_list *timer
+#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
+	void *function_context
+#endif
+	);
+
+boolean
+beamforming_send_ht_ndpa_packet(
+	void *dm_void,
+	u8 *RA,
+	enum channel_width BW,
+	u8 q_idx);
+
+boolean
+beamforming_send_vht_ndpa_packet(
+	void *dm_void,
+	u8 *RA,
+	u16 AID,
+	enum channel_width BW,
+	u8 q_idx);
+
+#else
+#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_AP))
+#define beamforming_gid_paid(adapter, tcb)
+#define phydm_acting_determine(dm, type) false
+#define beamforming_enter(dm, sta_idx)
+#define beamforming_leave(dm, RA)
+#define beamforming_end_fw(dm)
+#define beamforming_control_v1(dm, RA, AID, mode, BW, rate) true
+#define beamforming_control_v2(dm, idx, mode, BW, period) true
+#define phydm_beamforming_end_sw(dm, _status)
+#define beamforming_timer_callback(dm)
+#define phydm_beamforming_init(dm)
+#define phydm_beamforming_control_v2(dm, _idx, _mode, _BW, _period) false
+#define beamforming_watchdog(dm)
+#define phydm_beamforming_watchdog(dm)
+#endif /*@(DM_ODM_SUPPORT_TYPE & (ODM_CE | ODM_AP))*/
+#endif /*@(BEAMFORMING_SUPPORT == 1)*/
+#endif
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/phydm.c linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/phydm.c
--- linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/phydm.c	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/phydm.c	2020-04-10 16:35:06.821660301 +0300
@@ -0,0 +1,3168 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017  Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * The full GNU General Public License is included in this distribution in the
+ * file called LICENSE.
+ *
+ * Contact Information:
+ * wlanfae <wlanfae@realtek.com>
+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
+ * Hsinchu 300, Taiwan.
+ *
+ * Larry Finger <Larry.Finger@lwfinger.net>
+ *
+ *****************************************************************************/
+
+/*@************************************************************
+ * include files
+ ************************************************************/
+
+#include "mp_precomp.h"
+#include "phydm_precomp.h"
+
+const u16 phy_rate_table[] = {
+	/*@20M*/
+	1, 2, 5, 11,
+	6, 9, 12, 18, 24, 36, 48, 54,
+	6, 13, 19, 26, 39, 52, 58, 65, /*@MCS0~7*/
+	13, 26, 39, 52, 78, 104, 117, 130 /*@MCS8~15*/
+};
+
+void phydm_traffic_load_decision(void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	u8 shift = 0;
+
+	/*@---TP & Trafic-load calculation---*/
+
+	if (dm->last_tx_ok_cnt > *dm->num_tx_bytes_unicast)
+		dm->last_tx_ok_cnt = *dm->num_tx_bytes_unicast;
+
+	if (dm->last_rx_ok_cnt > *dm->num_rx_bytes_unicast)
+		dm->last_rx_ok_cnt = *dm->num_rx_bytes_unicast;
+
+	dm->cur_tx_ok_cnt = *dm->num_tx_bytes_unicast - dm->last_tx_ok_cnt;
+	dm->cur_rx_ok_cnt = *dm->num_rx_bytes_unicast - dm->last_rx_ok_cnt;
+	dm->last_tx_ok_cnt = *dm->num_tx_bytes_unicast;
+	dm->last_rx_ok_cnt = *dm->num_rx_bytes_unicast;
+
+	/*@AP:  <<3(8bit), >>20(10^6,M), >>0(1sec)*/
+	shift = 17 + (PHYDM_WATCH_DOG_PERIOD - 1);
+	/*@WIN&CE:  <<3(8bit), >>20(10^6,M), >>1(2sec)*/
+
+	dm->tx_tp = (dm->tx_tp >> 1) + (u32)((dm->cur_tx_ok_cnt >> shift) >> 1);
+	dm->rx_tp = (dm->rx_tp >> 1) + (u32)((dm->cur_rx_ok_cnt >> shift) >> 1);
+
+	dm->total_tp = dm->tx_tp + dm->rx_tp;
+
+	/*@[Calculate TX/RX state]*/
+	if (dm->tx_tp > (dm->rx_tp << 1))
+		dm->txrx_state_all = TX_STATE;
+	else if (dm->rx_tp > (dm->tx_tp << 1))
+		dm->txrx_state_all = RX_STATE;
+	else
+		dm->txrx_state_all = BI_DIRECTION_STATE;
+
+	/*@[Traffic load decision]*/
+	dm->pre_traffic_load = dm->traffic_load;
+
+	if (dm->cur_tx_ok_cnt > 1875000 || dm->cur_rx_ok_cnt > 1875000) {
+		/* @( 1.875M * 8bit ) / 2sec= 7.5M bits /sec )*/
+		dm->traffic_load = TRAFFIC_HIGH;
+	} else if (dm->cur_tx_ok_cnt > 500000 || dm->cur_rx_ok_cnt > 500000) {
+		/*@( 0.5M * 8bit ) / 2sec =  2M bits /sec )*/
+		dm->traffic_load = TRAFFIC_MID;
+	} else if (dm->cur_tx_ok_cnt > 100000 || dm->cur_rx_ok_cnt > 100000) {
+		/*@( 0.1M * 8bit ) / 2sec =  0.4M bits /sec )*/
+		dm->traffic_load = TRAFFIC_LOW;
+	} else if (dm->cur_tx_ok_cnt > 25000 || dm->cur_rx_ok_cnt > 25000) {
+		/*@( 0.025M * 8bit ) / 2sec =  0.1M bits /sec )*/
+		dm->traffic_load = TRAFFIC_ULTRA_LOW;
+	} else {
+		dm->traffic_load = TRAFFIC_NO_TP;
+	}
+
+	/*@[Calculate consecutive idlel time]*/
+	if (dm->traffic_load == 0)
+		dm->consecutive_idlel_time += PHYDM_WATCH_DOG_PERIOD;
+	else
+		dm->consecutive_idlel_time = 0;
+
+	#if 0
+	PHYDM_DBG(dm, DBG_COMMON_FLOW,
+		  "cur_tx_ok_cnt = %d, cur_rx_ok_cnt = %d, last_tx_ok_cnt = %d, last_rx_ok_cnt = %d\n",
+		  dm->cur_tx_ok_cnt, dm->cur_rx_ok_cnt, dm->last_tx_ok_cnt,
+		  dm->last_rx_ok_cnt);
+
+	PHYDM_DBG(dm, DBG_COMMON_FLOW, "tx_tp = %d, rx_tp = %d\n", dm->tx_tp,
+		  dm->rx_tp);
+	#endif
+}
+
+void phydm_cck_new_agc_chk(struct dm_struct *dm)
+{
+	dm->cck_new_agc = 0;
+
+#if ((RTL8723D_SUPPORT == 1) || (RTL8822B_SUPPORT == 1) || \
+	(RTL8821C_SUPPORT == 1) || (RTL8197F_SUPPORT == 1) || \
+	(RTL8710B_SUPPORT == 1) || (RTL8192F_SUPPORT == 1) || \
+	(RTL8195B_SUPPORT == 1) || (RTL8198F_SUPPORT == 1) || \
+	(RTL8822C_SUPPORT == 1))
+	if (dm->support_ic_type &
+	    (ODM_RTL8723D | ODM_RTL8822B | ODM_RTL8821C | ODM_RTL8197F |
+	    ODM_RTL8710B | ODM_RTL8192F | ODM_RTL8195B)) {
+		/*@1: new agc  0: old agc*/
+		dm->cck_new_agc = (boolean)odm_get_bb_reg(dm, R_0xa9c, BIT(17));
+	} else if (dm->support_ic_type & (ODM_RTL8198F | ODM_RTL8822C)) {
+		/*@1: new agc  0: old agc*/
+		dm->cck_new_agc = (boolean)odm_get_bb_reg(dm, R_0x1a9c,
+							  BIT(17));
+	}
+#endif
+}
+
+/*select 3 or 4 bit LNA */
+void phydm_cck_lna_bit_num_chk(struct dm_struct *dm)
+{
+	boolean report_type = 0;
+	#if (RTL8192E_SUPPORT == 1)
+	u32 value_824, value_82c;
+	#endif
+
+	#if (RTL8192E_SUPPORT == 1)
+	if (dm->support_ic_type & (ODM_RTL8192E)) {
+	/* @0x824[9] = 0x82C[9] = 0xA80[7] those registers setting
+	 * should be equal or CCK RSSI report may be incorrect
+	 */
+		value_824 = odm_get_bb_reg(dm, R_0x824, BIT(9));
+		value_82c = odm_get_bb_reg(dm, R_0x82c, BIT(9));
+
+		if (value_824 != value_82c)
+			odm_set_bb_reg(dm, R_0x82c, BIT(9), value_824);
+		odm_set_bb_reg(dm, R_0xa80, BIT(7), value_824);
+		report_type = (boolean)value_824;
+	}
+	#endif
+
+	#if (RTL8703B_SUPPORT || RTL8723D_SUPPORT || RTL8710B_SUPPORT)
+	if (dm->support_ic_type &
+	    (ODM_RTL8703B | ODM_RTL8723D | ODM_RTL8710B)) {
+		report_type = (boolean)odm_get_bb_reg(dm, R_0x950, BIT(11));
+
+		if (report_type != 1)
+			pr_debug("[Warning] CCK should be 4bit LNA\n");
+	}
+	#endif
+
+	#if (RTL8821C_SUPPORT == 1)
+	if (dm->support_ic_type & ODM_RTL8821C) {
+		if (dm->default_rf_set_8821c == SWITCH_TO_BTG)
+			report_type = 1;
+	}
+	#endif
+
+	dm->cck_agc_report_type = report_type;
+
+	PHYDM_DBG(dm, ODM_COMP_INIT, "cck_agc_report_type=((%d))\n",
+		  dm->cck_agc_report_type);
+}
+
+void phydm_init_cck_setting(struct dm_struct *dm)
+{
+	u32 reg_tmp = 0;
+	u32 mask_tmp = 0;
+
+	reg_tmp = ODM_REG(CCK_RPT_FORMAT, dm);
+	mask_tmp = ODM_BIT(CCK_RPT_FORMAT, dm);
+	dm->is_cck_high_power = (boolean)odm_get_bb_reg(dm, reg_tmp, mask_tmp);
+
+	PHYDM_DBG(dm, ODM_COMP_INIT, "ext_lna_gain=((%d))\n", dm->ext_lna_gain);
+
+	phydm_config_cck_rx_antenna_init(dm);
+
+	if (dm->support_ic_type & (ODM_RTL8192F))
+		phydm_config_cck_rx_path(dm, BB_PATH_AB);
+	else
+		phydm_config_cck_rx_path(dm, BB_PATH_A);
+
+	phydm_cck_new_agc_chk(dm);
+	phydm_cck_lna_bit_num_chk(dm);
+	phydm_get_cck_rssi_table_from_reg(dm);
+}
+
+void phydm_init_hw_info_by_rfe(struct dm_struct *dm)
+{
+#if (RTL8822B_SUPPORT == 1)
+	/*@if (dm->support_ic_type & ODM_RTL8822B)*/
+		/*@phydm_init_hw_info_by_rfe_type_8822b(dm);*/
+#endif
+#if (RTL8821C_SUPPORT == 1)
+	if (dm->support_ic_type & ODM_RTL8821C)
+		phydm_init_hw_info_by_rfe_type_8821c(dm);
+#endif
+#if (RTL8197F_SUPPORT == 1)
+	if (dm->support_ic_type & ODM_RTL8197F)
+		phydm_init_hw_info_by_rfe_type_8197f(dm);
+#endif
+}
+
+void phydm_common_info_self_init(struct dm_struct *dm)
+{
+	u32 reg_tmp = 0;
+	u32 mask_tmp = 0;
+
+	if (dm->support_ic_type & ODM_IC_JGR3_SERIES)
+		dm->ic_ip_series = PHYDM_IC_JGR3;
+	else if (dm->support_ic_type & ODM_IC_11AC_SERIES)
+		dm->ic_ip_series = PHYDM_IC_AC;
+	else if (dm->support_ic_type & ODM_IC_11N_SERIES)
+		dm->ic_ip_series = PHYDM_IC_N;
+
+	phydm_init_cck_setting(dm);
+
+	reg_tmp = ODM_REG(BB_RX_PATH, dm);
+	mask_tmp = ODM_BIT(BB_RX_PATH, dm);
+	dm->rf_path_rx_enable = (u8)odm_get_bb_reg(dm, reg_tmp, mask_tmp);
+#if (DM_ODM_SUPPORT_TYPE != ODM_CE)
+	dm->is_net_closed = &dm->BOOLEAN_temp;
+
+	phydm_init_debug_setting(dm);
+#endif
+
+	phydm_init_soft_ml_setting(dm);
+
+	dm->phydm_sys_up_time = 0;
+
+	if (dm->support_ic_type & ODM_IC_1SS)
+		dm->num_rf_path = 1;
+	else if (dm->support_ic_type & ODM_IC_2SS)
+		dm->num_rf_path = 2;
+	else if (dm->support_ic_type & ODM_IC_3SS)
+		dm->num_rf_path = 3;
+	else if (dm->support_ic_type & ODM_IC_4SS)
+		dm->num_rf_path = 4;
+	else
+		dm->num_rf_path = 1;
+
+	phydm_trx_antenna_setting_init(dm, dm->num_rf_path);
+
+	dm->tx_rate = 0xFF;
+	dm->rssi_min_by_path = 0xFF;
+
+	dm->number_linked_client = 0;
+	dm->pre_number_linked_client = 0;
+	dm->number_active_client = 0;
+	dm->pre_number_active_client = 0;
+
+	dm->last_tx_ok_cnt = 0;
+	dm->last_rx_ok_cnt = 0;
+	dm->tx_tp = 0;
+	dm->rx_tp = 0;
+	dm->total_tp = 0;
+	dm->traffic_load = TRAFFIC_LOW;
+
+	dm->nbi_set_result = 0;
+	dm->is_init_hw_info_by_rfe = false;
+	dm->pre_dbg_priority = DBGPORT_RELEASE;
+	dm->tp_active_th = 5;
+	dm->disable_phydm_watchdog = 0;
+
+	dm->u8_dummy = 0xf;
+	dm->u16_dummy = 0xffff;
+	dm->u32_dummy = 0xffffffff;
+
+	dm->pause_lv_table.lv_cckpd = PHYDM_PAUSE_RELEASE;
+	dm->pause_lv_table.lv_dig = PHYDM_PAUSE_RELEASE;
+}
+
+void phydm_cmn_sta_info_update(void *dm_void, u8 macid)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct cmn_sta_info *sta = dm->phydm_sta_info[macid];
+	struct ra_sta_info *ra = NULL;
+
+	if (is_sta_active(sta)) {
+		ra = &sta->ra_info;
+	} else {
+		PHYDM_DBG(dm, DBG_RA_MASK, "[Warning] %s invalid sta_info\n",
+			  __func__);
+		return;
+	}
+
+	PHYDM_DBG(dm, DBG_RA_MASK, "%s ======>\n", __func__);
+	PHYDM_DBG(dm, DBG_RA_MASK, "MACID=%d\n", sta->mac_id);
+
+	/*@[Calculate TX/RX state]*/
+	if (sta->tx_moving_average_tp > (sta->rx_moving_average_tp << 1))
+		ra->txrx_state = TX_STATE;
+	else if (sta->rx_moving_average_tp > (sta->tx_moving_average_tp << 1))
+		ra->txrx_state = RX_STATE;
+	else
+		ra->txrx_state = BI_DIRECTION_STATE;
+
+	ra->is_noisy = dm->noisy_decision;
+}
+
+void phydm_common_info_self_update(struct dm_struct *dm)
+{
+	u8 sta_cnt = 0, num_active_client = 0;
+	u32 i, one_entry_macid = 0;
+	u32 ma_rx_tp = 0;
+	u32 tp_diff = 0;
+	struct cmn_sta_info *sta;
+
+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
+
+	PADAPTER adapter = (PADAPTER)dm->adapter;
+
+	PMGNT_INFO mgnt_info = &((PADAPTER)adapter)->MgntInfo;
+
+	sta = dm->phydm_sta_info[0];
+	if (mgnt_info->mAssoc) {
+		sta->dm_ctrl |= STA_DM_CTRL_ACTIVE;
+		for (i = 0; i < 6; i++)
+			sta->mac_addr[i] = mgnt_info->Bssid[i];
+	} else if (GetFirstClientPort(adapter)) {
+		//void	*client_adapter = GetFirstClientPort(adapter);
+		struct _ADAPTER *client_adapter = GetFirstClientPort(adapter);
+
+		sta->dm_ctrl |= STA_DM_CTRL_ACTIVE;
+		for (i = 0; i < 6; i++)
+			sta->mac_addr[i] = client_adapter->MgntInfo.Bssid[i];
+	} else {
+		sta->dm_ctrl = sta->dm_ctrl & (~STA_DM_CTRL_ACTIVE);
+		for (i = 0; i < 6; i++)
+			sta->mac_addr[i] = 0;
+	}
+
+	/* STA mode is linked to AP */
+	if (is_sta_active(sta) && !ACTING_AS_AP(adapter))
+		dm->bsta_state = true;
+	else
+		dm->bsta_state = false;
+#endif
+
+	for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) {
+		sta = dm->phydm_sta_info[i];
+		if (is_sta_active(sta)) {
+			sta_cnt++;
+
+			if (sta_cnt == 1)
+				one_entry_macid = i;
+
+			phydm_cmn_sta_info_update(dm, (u8)i);
+			#if (BEAMFORMING_SUPPORT == 1)
+#if 0
+			/*phydm_get_txbf_device_num(dm, (u8)i);*/
+#endif
+			#endif
+
+			ma_rx_tp = sta->rx_moving_average_tp +
+				   sta->tx_moving_average_tp;
+
+			PHYDM_DBG(dm, DBG_COMMON_FLOW,
+				  "TP[%d]: ((%d )) bit/sec\n", i, ma_rx_tp);
+
+			if (ma_rx_tp > ACTIVE_TP_THRESHOLD)
+				num_active_client++;
+		}
+	}
+
+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
+	dm->is_linked = (sta_cnt != 0) ? true : false;
+#endif
+
+	if (sta_cnt == 1) {
+		dm->is_one_entry_only = true;
+		dm->one_entry_macid = one_entry_macid;
+		dm->one_entry_tp = ma_rx_tp;
+
+		dm->tp_active_occur = 0;
+
+		PHYDM_DBG(dm, DBG_COMMON_FLOW,
+			  "one_entry_tp=((%d)), pre_one_entry_tp=((%d))\n",
+			  dm->one_entry_tp, dm->pre_one_entry_tp);
+
+		if (dm->one_entry_tp > dm->pre_one_entry_tp &&
+		    dm->pre_one_entry_tp <= 2) {
+			tp_diff = dm->one_entry_tp - dm->pre_one_entry_tp;
+
+			if (tp_diff > dm->tp_active_th)
+				dm->tp_active_occur = 1;
+		}
+		dm->pre_one_entry_tp = dm->one_entry_tp;
+	} else {
+		dm->is_one_entry_only = false;
+	}
+
+	dm->pre_number_linked_client = dm->number_linked_client;
+	dm->pre_number_active_client = dm->number_active_client;
+
+	dm->number_linked_client = sta_cnt;
+	dm->number_active_client = num_active_client;
+
+	/*Traffic load information update*/
+	phydm_traffic_load_decision(dm);
+
+	dm->phydm_sys_up_time += PHYDM_WATCH_DOG_PERIOD;
+
+	dm->is_dfs_band = phydm_is_dfs_band(dm);
+	dm->phy_dbg_info.show_phy_sts_cnt = 0;
+}
+
+void phydm_common_info_self_reset(struct dm_struct *dm)
+{
+	struct odm_phy_dbg_info		*dbg_t = &dm->phy_dbg_info;
+
+	dbg_t->beacon_cnt_in_period = dbg_t->num_qry_beacon_pkt;
+	dbg_t->num_qry_beacon_pkt = 0;
+
+	dm->rxsc_l = 0xff;
+	dm->rxsc_20 = 0xff;
+	dm->rxsc_40 = 0xff;
+	dm->rxsc_80 = 0xff;
+}
+
+void *
+phydm_get_structure(struct dm_struct *dm, u8 structure_type)
+
+{
+	void *structure = NULL;
+
+	switch (structure_type) {
+	case PHYDM_FALSEALMCNT:
+		structure = &dm->false_alm_cnt;
+		break;
+
+	case PHYDM_CFOTRACK:
+		structure = &dm->dm_cfo_track;
+		break;
+
+	case PHYDM_ADAPTIVITY:
+		structure = &dm->adaptivity;
+		break;
+
+	case PHYDM_DFS:
+		structure = &dm->dfs;
+		break;
+
+	default:
+		break;
+	}
+
+	return structure;
+}
+
+void phydm_phy_info_update(struct dm_struct *dm)
+{
+#if (RTL8822B_SUPPORT == 1)
+	if (dm->support_ic_type == ODM_RTL8822B)
+		dm->phy_dbg_info.condi_num = phydm_get_condi_num_8822b(dm);
+#endif
+}
+
+void phydm_hw_setting(struct dm_struct *dm)
+{
+#if (RTL8821A_SUPPORT == 1)
+	if (dm->support_ic_type & ODM_RTL8821)
+		odm_hw_setting_8821a(dm);
+#endif
+
+#if (RTL8814A_SUPPORT == 1)
+	if (dm->support_ic_type & ODM_RTL8814A)
+		phydm_hwsetting_8814a(dm);
+#endif
+
+#if (RTL8822B_SUPPORT == 1)
+	if (dm->support_ic_type & ODM_RTL8822B)
+		phydm_hwsetting_8822b(dm);
+#endif
+
+#if (RTL8812A_SUPPORT == 1)
+	if (dm->support_ic_type & ODM_RTL8812)
+		phydm_hwsetting_8812a(dm);
+#endif
+
+#if (RTL8197F_SUPPORT == 1)
+	if (dm->support_ic_type & ODM_RTL8197F)
+		phydm_hwsetting_8197f(dm);
+#endif
+
+#if (RTL8192F_SUPPORT == 1)
+	if (dm->support_ic_type & ODM_RTL8192F)
+		phydm_hwsetting_8192f(dm);
+#endif
+}
+
+#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN))
+u64 phydm_supportability_init_win(
+	void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	u64 support_ability = 0;
+
+	switch (dm->support_ic_type) {
+/*@---------------N Series--------------------*/
+#if (RTL8188E_SUPPORT == 1)
+	case ODM_RTL8188E:
+		support_ability |=
+			ODM_BB_DIG |
+			ODM_BB_RA_MASK |
+			/*ODM_BB_DYNAMIC_TXPWR	|*/
+			ODM_BB_FA_CNT |
+			ODM_BB_RSSI_MONITOR |
+			ODM_BB_CCK_PD |
+			/*ODM_BB_PWR_TRAIN		|*/
+			ODM_BB_RATE_ADAPTIVE |
+			ODM_BB_CFO_TRACKING |
+			ODM_BB_ENV_MONITOR |
+			ODM_BB_PRIMARY_CCA;
+		break;
+#endif
+
+#if (RTL8192E_SUPPORT == 1)
+	case ODM_RTL8192E:
+		support_ability |=
+			ODM_BB_DIG |
+			ODM_BB_RA_MASK |
+			/*ODM_BB_DYNAMIC_TXPWR	|*/
+			ODM_BB_FA_CNT |
+			ODM_BB_RSSI_MONITOR |
+			ODM_BB_CCK_PD |
+			/*ODM_BB_PWR_TRAIN		|*/
+			ODM_BB_RATE_ADAPTIVE |
+			ODM_BB_CFO_TRACKING |
+			ODM_BB_ENV_MONITOR |
+			ODM_BB_PRIMARY_CCA;
+		break;
+#endif
+
+#if (RTL8723B_SUPPORT == 1)
+	case ODM_RTL8723B:
+		support_ability |=
+			ODM_BB_DIG |
+			ODM_BB_RA_MASK |
+			/*ODM_BB_DYNAMIC_TXPWR	|*/
+			ODM_BB_FA_CNT |
+			ODM_BB_RSSI_MONITOR |
+			ODM_BB_CCK_PD |
+			/*ODM_BB_PWR_TRAIN		|*/
+			ODM_BB_RATE_ADAPTIVE |
+			ODM_BB_CFO_TRACKING |
+			ODM_BB_ENV_MONITOR |
+			ODM_BB_PRIMARY_CCA;
+		break;
+#endif
+
+#if (RTL8703B_SUPPORT == 1)
+	case ODM_RTL8703B:
+		support_ability |=
+			ODM_BB_DIG |
+			ODM_BB_RA_MASK |
+			/*ODM_BB_DYNAMIC_TXPWR	|*/
+			ODM_BB_FA_CNT |
+			ODM_BB_RSSI_MONITOR |
+			ODM_BB_CCK_PD |
+			/*ODM_BB_PWR_TRAIN		|*/
+			ODM_BB_RATE_ADAPTIVE |
+			ODM_BB_CFO_TRACKING |
+			ODM_BB_ENV_MONITOR;
+		break;
+#endif
+
+#if (RTL8723D_SUPPORT == 1)
+	case ODM_RTL8723D:
+		support_ability |=
+			ODM_BB_DIG |
+			ODM_BB_RA_MASK |
+			/*ODM_BB_DYNAMIC_TXPWR	|*/
+			ODM_BB_FA_CNT |
+			ODM_BB_RSSI_MONITOR |
+			ODM_BB_CCK_PD |
+			ODM_BB_PWR_TRAIN	|
+			ODM_BB_RATE_ADAPTIVE |
+			ODM_BB_CFO_TRACKING |
+			ODM_BB_ENV_MONITOR;
+		break;
+#endif
+
+#if (RTL8710B_SUPPORT == 1)
+	case ODM_RTL8710B:
+		support_ability |=
+			ODM_BB_DIG |
+			ODM_BB_RA_MASK |
+			/*ODM_BB_DYNAMIC_TXPWR	|*/
+			ODM_BB_FA_CNT |
+			ODM_BB_RSSI_MONITOR |
+			ODM_BB_CCK_PD |
+			ODM_BB_PWR_TRAIN	|
+			ODM_BB_RATE_ADAPTIVE |
+			ODM_BB_CFO_TRACKING |
+			ODM_BB_ENV_MONITOR;
+		break;
+#endif
+
+#if (RTL8188F_SUPPORT == 1)
+	case ODM_RTL8188F:
+		support_ability |=
+			ODM_BB_DIG |
+			ODM_BB_RA_MASK |
+			/*ODM_BB_DYNAMIC_TXPWR	|*/
+			ODM_BB_FA_CNT |
+			ODM_BB_RSSI_MONITOR |
+			ODM_BB_CCK_PD |
+			/*ODM_BB_PWR_TRAIN	|*/
+			ODM_BB_RATE_ADAPTIVE |
+			ODM_BB_CFO_TRACKING |
+			ODM_BB_ENV_MONITOR;
+		break;
+#endif
+
+#if (RTL8192F_SUPPORT == 1)
+	case ODM_RTL8192F:
+		support_ability |=
+			ODM_BB_DIG |
+			ODM_BB_RA_MASK |
+			ODM_BB_FA_CNT |
+			ODM_BB_RSSI_MONITOR |
+			ODM_BB_CCK_PD |
+			ODM_BB_PWR_TRAIN	|
+			ODM_BB_RATE_ADAPTIVE |
+			ODM_BB_CFO_TRACKING |
+			ODM_BB_ADAPTIVE_SOML |
+			ODM_BB_ENV_MONITOR;
+		/*ODM_BB_LNA_SAT_CHK		|*/
+		/*ODM_BB_PRIMARY_CCA*/
+
+		break;
+#endif
+
+/*@---------------AC Series-------------------*/
+
+#if ((RTL8812A_SUPPORT == 1) || (RTL8821A_SUPPORT == 1))
+	case ODM_RTL8812:
+	case ODM_RTL8821:
+		support_ability |=
+			ODM_BB_DIG |
+			ODM_BB_RA_MASK |
+			ODM_BB_DYNAMIC_TXPWR |
+			ODM_BB_FA_CNT |
+			ODM_BB_RSSI_MONITOR |
+			ODM_BB_CCK_PD |
+			/*ODM_BB_PWR_TRAIN		|*/
+			ODM_BB_RATE_ADAPTIVE |
+			ODM_BB_CFO_TRACKING |
+			ODM_BB_ENV_MONITOR;
+		break;
+#endif
+
+#if (RTL8814A_SUPPORT == 1)
+	case ODM_RTL8814A:
+		support_ability |=
+			ODM_BB_DIG |
+			ODM_BB_RA_MASK |
+			ODM_BB_DYNAMIC_TXPWR |
+			ODM_BB_FA_CNT |
+			ODM_BB_RSSI_MONITOR |
+			ODM_BB_CCK_PD |
+			/*ODM_BB_PWR_TRAIN		|*/
+			ODM_BB_RATE_ADAPTIVE |
+			ODM_BB_CFO_TRACKING |
+			ODM_BB_ENV_MONITOR;
+		break;
+#endif
+
+#if (RTL8814B_SUPPORT == 1)
+	case ODM_RTL8814B:
+		support_ability |=
+			ODM_BB_DIG |
+			ODM_BB_RA_MASK |
+			/*ODM_BB_DYNAMIC_TXPWR	|*/
+			ODM_BB_FA_CNT |
+			ODM_BB_RSSI_MONITOR |
+			ODM_BB_CCK_PD |
+			/*ODM_BB_PWR_TRAIN		|*/
+			ODM_BB_RATE_ADAPTIVE |
+			ODM_BB_CFO_TRACKING |
+			ODM_BB_ENV_MONITOR;
+		break;
+#endif
+
+#if (RTL8822B_SUPPORT == 1)
+	case ODM_RTL8822B:
+		support_ability |=
+			ODM_BB_DIG |
+			ODM_BB_RA_MASK |
+			/*ODM_BB_DYNAMIC_TXPWR	|*/
+			ODM_BB_FA_CNT |
+			ODM_BB_RSSI_MONITOR |
+			ODM_BB_CCK_PD |
+			/*ODM_BB_PWR_TRAIN		|*/
+			/*ODM_BB_ADAPTIVE_SOML |*/
+			ODM_BB_RATE_ADAPTIVE |
+			ODM_BB_CFO_TRACKING |
+			ODM_BB_ENV_MONITOR;
+		break;
+#endif
+
+#if (RTL8821C_SUPPORT == 1)
+	case ODM_RTL8821C:
+		support_ability |=
+			ODM_BB_DIG |
+			ODM_BB_RA_MASK |
+			/*ODM_BB_DYNAMIC_TXPWR	|*/
+			ODM_BB_FA_CNT |
+			ODM_BB_RSSI_MONITOR |
+			ODM_BB_CCK_PD |
+			/*ODM_BB_PWR_TRAIN		|*/
+			ODM_BB_RATE_ADAPTIVE |
+			ODM_BB_CFO_TRACKING |
+			ODM_BB_ENV_MONITOR;
+		break;
+#endif
+
+	default:
+		support_ability |=
+			ODM_BB_DIG |
+			ODM_BB_RA_MASK |
+			/*ODM_BB_DYNAMIC_TXPWR	|*/
+			ODM_BB_FA_CNT |
+			ODM_BB_RSSI_MONITOR |
+			ODM_BB_CCK_PD |
+			/*ODM_BB_PWR_TRAIN		|*/
+			ODM_BB_RATE_ADAPTIVE |
+			ODM_BB_CFO_TRACKING |
+			ODM_BB_ENV_MONITOR;
+
+		pr_debug("[Warning] Supportability Init Warning !!!\n");
+		break;
+	}
+
+	return support_ability;
+}
+#endif
+
+#if (DM_ODM_SUPPORT_TYPE & (ODM_CE))
+u64 phydm_supportability_init_ce(void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	u64 support_ability = 0;
+
+	switch (dm->support_ic_type) {
+/*@---------------N Series--------------------*/
+#if (RTL8188E_SUPPORT == 1)
+	case ODM_RTL8188E:
+		support_ability |=
+			ODM_BB_DIG |
+			ODM_BB_RA_MASK |
+			/*@ODM_BB_DYNAMIC_TXPWR	|*/
+			ODM_BB_FA_CNT |
+			ODM_BB_RSSI_MONITOR |
+			ODM_BB_CCK_PD |
+			/*@ODM_BB_PWR_TRAIN		|*/
+			ODM_BB_RATE_ADAPTIVE |
+			ODM_BB_CFO_TRACKING |
+			ODM_BB_ENV_MONITOR |
+			ODM_BB_PRIMARY_CCA;
+		break;
+#endif
+
+#if (RTL8192E_SUPPORT == 1)
+	case ODM_RTL8192E:
+		support_ability |=
+			ODM_BB_DIG |
+			ODM_BB_RA_MASK |
+			/*@ODM_BB_DYNAMIC_TXPWR	|*/
+			ODM_BB_FA_CNT |
+			ODM_BB_RSSI_MONITOR |
+			ODM_BB_CCK_PD |
+			/*@ODM_BB_PWR_TRAIN		|*/
+			ODM_BB_RATE_ADAPTIVE |
+			ODM_BB_CFO_TRACKING |
+			ODM_BB_ENV_MONITOR |
+			ODM_BB_PRIMARY_CCA;
+		break;
+#endif
+
+#if (RTL8723B_SUPPORT == 1)
+	case ODM_RTL8723B:
+		support_ability |=
+			ODM_BB_DIG |
+			ODM_BB_RA_MASK |
+			/*@ODM_BB_DYNAMIC_TXPWR	|*/
+			ODM_BB_FA_CNT |
+			ODM_BB_RSSI_MONITOR |
+			ODM_BB_CCK_PD |
+			/*@ODM_BB_PWR_TRAIN		|*/
+			ODM_BB_RATE_ADAPTIVE |
+			ODM_BB_CFO_TRACKING |
+			ODM_BB_ENV_MONITOR |
+			ODM_BB_PRIMARY_CCA;
+		break;
+#endif
+
+#if (RTL8703B_SUPPORT == 1)
+	case ODM_RTL8703B:
+		support_ability |=
+			ODM_BB_DIG |
+			ODM_BB_RA_MASK |
+			/*@ODM_BB_DYNAMIC_TXPWR	|*/
+			ODM_BB_FA_CNT |
+			ODM_BB_RSSI_MONITOR |
+			ODM_BB_CCK_PD |
+			/*@ODM_BB_PWR_TRAIN		|*/
+			ODM_BB_RATE_ADAPTIVE |
+			ODM_BB_CFO_TRACKING |
+			ODM_BB_ENV_MONITOR;
+		break;
+#endif
+
+#if (RTL8723D_SUPPORT == 1)
+	case ODM_RTL8723D:
+		support_ability |=
+			ODM_BB_DIG |
+			ODM_BB_RA_MASK |
+			/*@ODM_BB_DYNAMIC_TXPWR	|*/
+			ODM_BB_FA_CNT |
+			ODM_BB_RSSI_MONITOR |
+			ODM_BB_CCK_PD |
+			ODM_BB_PWR_TRAIN	|
+			ODM_BB_RATE_ADAPTIVE |
+			ODM_BB_CFO_TRACKING |
+			ODM_BB_ENV_MONITOR;
+		break;
+#endif
+
+#if (RTL8710B_SUPPORT == 1)
+	case ODM_RTL8710B:
+		support_ability |=
+			ODM_BB_DIG |
+			ODM_BB_RA_MASK |
+			/*@ODM_BB_DYNAMIC_TXPWR	|*/
+			ODM_BB_FA_CNT |
+			ODM_BB_RSSI_MONITOR |
+			ODM_BB_CCK_PD |
+			/*@ODM_BB_PWR_TRAIN		|*/
+			ODM_BB_RATE_ADAPTIVE |
+			ODM_BB_CFO_TRACKING |
+			ODM_BB_ENV_MONITOR;
+		break;
+#endif
+
+#if (RTL8188F_SUPPORT == 1)
+	case ODM_RTL8188F:
+		support_ability |=
+			ODM_BB_DIG |
+			ODM_BB_RA_MASK |
+			/*@ODM_BB_DYNAMIC_TXPWR	|*/
+			ODM_BB_FA_CNT |
+			ODM_BB_RSSI_MONITOR |
+			ODM_BB_CCK_PD |
+			/*@ODM_BB_PWR_TRAIN		|*/
+			ODM_BB_RATE_ADAPTIVE |
+			ODM_BB_CFO_TRACKING |
+			ODM_BB_ENV_MONITOR;
+		break;
+#endif
+
+/*@jj add 20170822*/
+#if (RTL8192F_SUPPORT == 1)
+	case ODM_RTL8192F:
+		support_ability |=
+			ODM_BB_DIG |
+			ODM_BB_RA_MASK |
+			ODM_BB_FA_CNT |
+			ODM_BB_RSSI_MONITOR |
+			ODM_BB_CCK_PD |
+			ODM_BB_PWR_TRAIN		|
+			ODM_BB_RATE_ADAPTIVE |
+			ODM_BB_CFO_TRACKING |
+			/*@ODM_BB_ADAPTIVE_SOML |*/
+			ODM_BB_ENV_MONITOR;
+		/*@ODM_BB_LNA_SAT_CHK		|*/
+		/*@ODM_BB_PRIMARY_CCA*/
+		break;
+#endif
+/*@---------------AC Series-------------------*/
+
+#if ((RTL8812A_SUPPORT == 1) || (RTL8821A_SUPPORT == 1))
+	case ODM_RTL8812:
+	case ODM_RTL8821:
+		support_ability |=
+			ODM_BB_DIG |
+			ODM_BB_RA_MASK |
+			/*@ODM_BB_DYNAMIC_TXPWR	|*/
+			ODM_BB_FA_CNT |
+			ODM_BB_RSSI_MONITOR |
+			ODM_BB_CCK_PD |
+			/*@ODM_BB_PWR_TRAIN		|*/
+			ODM_BB_RATE_ADAPTIVE |
+			ODM_BB_CFO_TRACKING |
+			ODM_BB_ENV_MONITOR;
+		break;
+#endif
+
+#if (RTL8814A_SUPPORT == 1)
+	case ODM_RTL8814A:
+		support_ability |=
+			ODM_BB_DIG |
+			ODM_BB_RA_MASK |
+			/*@ODM_BB_DYNAMIC_TXPWR	|*/
+			ODM_BB_FA_CNT |
+			ODM_BB_RSSI_MONITOR |
+			ODM_BB_CCK_PD |
+			/*@ODM_BB_PWR_TRAIN		|*/
+			ODM_BB_RATE_ADAPTIVE |
+			ODM_BB_CFO_TRACKING |
+			ODM_BB_ENV_MONITOR;
+		break;
+#endif
+
+#if (RTL8814B_SUPPORT == 1)
+	case ODM_RTL8814B:
+		support_ability |=
+			ODM_BB_DIG |
+			ODM_BB_RA_MASK |
+			/*@ODM_BB_DYNAMIC_TXPWR	|*/
+			ODM_BB_FA_CNT |
+			ODM_BB_RSSI_MONITOR |
+			ODM_BB_CCK_PD |
+			/*@ODM_BB_PWR_TRAIN		|*/
+			ODM_BB_RATE_ADAPTIVE |
+			ODM_BB_CFO_TRACKING |
+			ODM_BB_ENV_MONITOR;
+		break;
+#endif
+
+#if (RTL8822B_SUPPORT == 1)
+	case ODM_RTL8822B:
+		support_ability |=
+			ODM_BB_DIG |
+			ODM_BB_RA_MASK |
+			/*@ODM_BB_DYNAMIC_TXPWR	|*/
+			ODM_BB_FA_CNT |
+			ODM_BB_RSSI_MONITOR |
+			ODM_BB_CCK_PD |
+			/*@ODM_BB_PWR_TRAIN		|*/
+			ODM_BB_RATE_ADAPTIVE |
+			ODM_BB_CFO_TRACKING |
+			ODM_BB_ENV_MONITOR;
+		break;
+#endif
+
+#if (RTL8821C_SUPPORT == 1)
+	case ODM_RTL8821C:
+		support_ability |=
+			ODM_BB_DIG |
+			ODM_BB_RA_MASK |
+			/*@ODM_BB_DYNAMIC_TXPWR	|*/
+			ODM_BB_FA_CNT |
+			ODM_BB_RSSI_MONITOR |
+			ODM_BB_CCK_PD |
+			/*@ODM_BB_PWR_TRAIN		|*/
+			ODM_BB_RATE_ADAPTIVE |
+			ODM_BB_CFO_TRACKING |
+			ODM_BB_ENV_MONITOR;
+		break;
+#endif
+
+	default:
+		support_ability |=
+			ODM_BB_DIG |
+			ODM_BB_RA_MASK |
+			/*@ODM_BB_DYNAMIC_TXPWR	|*/
+			ODM_BB_FA_CNT |
+			ODM_BB_RSSI_MONITOR |
+			ODM_BB_CCK_PD |
+			/*@ODM_BB_PWR_TRAIN		|*/
+			ODM_BB_RATE_ADAPTIVE |
+			ODM_BB_CFO_TRACKING |
+			ODM_BB_ENV_MONITOR;
+
+		pr_debug("[Warning] Supportability Init Warning !!!\n");
+		break;
+	}
+
+	return support_ability;
+}
+#endif
+
+#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
+u64 phydm_supportability_init_ap(
+	void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	u64 support_ability = 0;
+
+	switch (dm->support_ic_type) {
+/*@---------------N Series--------------------*/
+#if (RTL8188E_SUPPORT == 1)
+	case ODM_RTL8188E:
+		support_ability |=
+			ODM_BB_DIG |
+			ODM_BB_RA_MASK |
+			ODM_BB_FA_CNT |
+			ODM_BB_RSSI_MONITOR |
+			ODM_BB_CCK_PD |
+			/*ODM_BB_PWR_TRAIN		|*/
+			ODM_BB_RATE_ADAPTIVE |
+			ODM_BB_CFO_TRACKING |
+			ODM_BB_ENV_MONITOR |
+			ODM_BB_PRIMARY_CCA;
+		break;
+#endif
+
+#if (RTL8192E_SUPPORT == 1)
+	case ODM_RTL8192E:
+		support_ability |=
+			ODM_BB_DIG |
+			ODM_BB_RA_MASK |
+			ODM_BB_FA_CNT |
+			ODM_BB_RSSI_MONITOR |
+			ODM_BB_CCK_PD |
+			/*ODM_BB_PWR_TRAIN		|*/
+			ODM_BB_RATE_ADAPTIVE |
+			ODM_BB_CFO_TRACKING |
+			ODM_BB_ENV_MONITOR |
+			ODM_BB_PRIMARY_CCA;
+		break;
+#endif
+
+#if (RTL8723B_SUPPORT == 1)
+	case ODM_RTL8723B:
+		support_ability |=
+			ODM_BB_DIG |
+			ODM_BB_RA_MASK |
+			ODM_BB_FA_CNT |
+			ODM_BB_RSSI_MONITOR |
+			ODM_BB_CCK_PD |
+			/*ODM_BB_PWR_TRAIN		|*/
+			ODM_BB_RATE_ADAPTIVE |
+			ODM_BB_CFO_TRACKING |
+			ODM_BB_ENV_MONITOR;
+		break;
+#endif
+
+#if ((RTL8198F_SUPPORT == 1) || (RTL8197F_SUPPORT == 1))
+	case ODM_RTL8198F:
+		support_ability |=
+			/*ODM_BB_DIG				|*/
+			ODM_BB_RA_MASK |
+			ODM_BB_FA_CNT |
+			ODM_BB_RSSI_MONITOR;
+		/*ODM_BB_CCK_PD			|*/
+		/*ODM_BB_PWR_TRAIN		|*/
+		/*ODM_BB_RATE_ADAPTIVE	|*/
+		/*ODM_BB_CFO_TRACKING		|*/
+		/*ODM_BB_ADAPTIVE_SOML	|*/
+		/*ODM_BB_ENV_MONITOR		|*/
+		/*ODM_BB_LNA_SAT_CHK		|*/
+		/*ODM_BB_PRIMARY_CCA;*/
+		break;
+	case ODM_RTL8197F:
+		support_ability |=
+			ODM_BB_DIG |
+			ODM_BB_RA_MASK |
+			ODM_BB_FA_CNT |
+			ODM_BB_RSSI_MONITOR |
+			ODM_BB_CCK_PD |
+			/*ODM_BB_PWR_TRAIN		|*/
+			ODM_BB_RATE_ADAPTIVE |
+			ODM_BB_CFO_TRACKING |
+			ODM_BB_ADAPTIVE_SOML |
+			ODM_BB_ENV_MONITOR |
+			ODM_BB_LNA_SAT_CHK |
+			ODM_BB_PRIMARY_CCA;
+		break;
+#endif
+
+#if (RTL8192F_SUPPORT == 1)
+	case ODM_RTL8192F:
+		support_ability |=
+			ODM_BB_DIG |
+			ODM_BB_RA_MASK |
+			ODM_BB_FA_CNT |
+			ODM_BB_RSSI_MONITOR |
+			ODM_BB_CCK_PD |
+			/*ODM_BB_PWR_TRAIN		|*/
+			ODM_BB_RATE_ADAPTIVE |
+			/*ODM_BB_CFO_TRACKING		|*/
+			ODM_BB_ADAPTIVE_SOML |
+			/*ODM_BB_ENV_MONITOR		|*/
+			/*ODM_BB_LNA_SAT_CHK		|*/
+			/*ODM_BB_PRIMARY_CCA		|*/
+			0;
+		break;
+#endif
+
+/*@---------------AC Series-------------------*/
+
+#if (RTL8881A_SUPPORT == 1)
+	case ODM_RTL8881A:
+		support_ability |=
+			ODM_BB_DIG |
+			ODM_BB_RA_MASK |
+			ODM_BB_FA_CNT |
+			ODM_BB_RSSI_MONITOR |
+			ODM_BB_CCK_PD |
+			/*ODM_BB_PWR_TRAIN		|*/
+			ODM_BB_RATE_ADAPTIVE |
+			ODM_BB_CFO_TRACKING |
+			ODM_BB_ENV_MONITOR;
+		break;
+#endif
+
+#if (RTL8814A_SUPPORT == 1)
+	case ODM_RTL8814A:
+		support_ability |=
+			ODM_BB_DIG |
+			ODM_BB_RA_MASK |
+			ODM_BB_FA_CNT |
+			ODM_BB_RSSI_MONITOR |
+			ODM_BB_CCK_PD |
+			/*ODM_BB_PWR_TRAIN		|*/
+			ODM_BB_RATE_ADAPTIVE |
+			ODM_BB_CFO_TRACKING |
+			ODM_BB_ENV_MONITOR;
+		break;
+#endif
+
+#if (RTL8814B_SUPPORT == 1)
+	case ODM_RTL8814B:
+		support_ability |=
+			ODM_BB_DIG |
+			ODM_BB_RA_MASK |
+			ODM_BB_FA_CNT |
+			ODM_BB_RSSI_MONITOR |
+			ODM_BB_CCK_PD |
+			/*ODM_BB_PWR_TRAIN		|*/
+			ODM_BB_RATE_ADAPTIVE |
+			ODM_BB_CFO_TRACKING |
+			ODM_BB_ENV_MONITOR;
+		break;
+#endif
+
+#if (RTL8822B_SUPPORT == 1)
+	case ODM_RTL8822B:
+		support_ability |=
+			ODM_BB_DIG |
+			ODM_BB_RA_MASK |
+			ODM_BB_FA_CNT |
+			ODM_BB_RSSI_MONITOR |
+			ODM_BB_CCK_PD |
+			/*ODM_BB_PWR_TRAIN		|*/
+			/*ODM_BB_ADAPTIVE_SOML	|*/
+			ODM_BB_RATE_ADAPTIVE |
+			ODM_BB_CFO_TRACKING |
+			ODM_BB_ENV_MONITOR;
+		break;
+#endif
+
+#if (RTL8821C_SUPPORT == 1)
+	case ODM_RTL8821C:
+		support_ability |=
+			ODM_BB_DIG |
+			ODM_BB_RA_MASK |
+			ODM_BB_FA_CNT |
+			ODM_BB_RSSI_MONITOR |
+			ODM_BB_CCK_PD |
+			/*ODM_BB_PWR_TRAIN		|*/
+			ODM_BB_RATE_ADAPTIVE |
+			ODM_BB_CFO_TRACKING |
+			ODM_BB_ENV_MONITOR;
+
+		break;
+#endif
+
+	default:
+		support_ability |=
+			ODM_BB_DIG |
+			ODM_BB_RA_MASK |
+			ODM_BB_FA_CNT |
+			ODM_BB_RSSI_MONITOR |
+			ODM_BB_CCK_PD |
+			/*ODM_BB_PWR_TRAIN		|*/
+			ODM_BB_RATE_ADAPTIVE |
+			ODM_BB_CFO_TRACKING |
+			ODM_BB_ENV_MONITOR;
+
+		pr_debug("[Warning] Supportability Init Warning !!!\n");
+		break;
+	}
+
+#if 0
+	/*@[Config Antenna Diveristy]*/
+	if (*dm->enable_antdiv)
+		support_ability |= ODM_BB_ANT_DIV;
+
+	/*@[Config Adaptivity]*/
+	if (*dm->enable_adaptivity)
+		support_ability |= ODM_BB_ADAPTIVITY;
+#endif
+
+	return support_ability;
+}
+#endif
+
+#if (DM_ODM_SUPPORT_TYPE & (ODM_IOT))
+u64 phydm_supportability_init_iot(
+	void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	u64 support_ability = 0;
+
+	switch (dm->support_ic_type) {
+#if (RTL8710B_SUPPORT == 1)
+	case ODM_RTL8710B:
+		support_ability |=
+			ODM_BB_DIG |
+			ODM_BB_RA_MASK |
+			/*ODM_BB_DYNAMIC_TXPWR	|*/
+			ODM_BB_FA_CNT |
+			ODM_BB_RSSI_MONITOR |
+			ODM_BB_CCK_PD |
+			/*ODM_BB_PWR_TRAIN		|*/
+			ODM_BB_RATE_ADAPTIVE |
+			ODM_BB_CFO_TRACKING |
+			ODM_BB_ENV_MONITOR;
+		break;
+#endif
+
+#if (RTL8195A_SUPPORT == 1)
+	case ODM_RTL8195A:
+		support_ability |=
+			ODM_BB_DIG |
+			ODM_BB_RA_MASK |
+			/*ODM_BB_DYNAMIC_TXPWR	|*/
+			ODM_BB_FA_CNT |
+			ODM_BB_RSSI_MONITOR |
+			ODM_BB_CCK_PD |
+			/*ODM_BB_PWR_TRAIN		|*/
+			ODM_BB_RATE_ADAPTIVE |
+			ODM_BB_CFO_TRACKING |
+			ODM_BB_ENV_MONITOR;
+		break;
+#endif
+
+	default:
+		support_ability |=
+			ODM_BB_DIG |
+			ODM_BB_RA_MASK |
+			/*ODM_BB_DYNAMIC_TXPWR	|*/
+			ODM_BB_FA_CNT |
+			ODM_BB_RSSI_MONITOR |
+			ODM_BB_CCK_PD |
+			/*ODM_BB_PWR_TRAIN		|*/
+			ODM_BB_RATE_ADAPTIVE |
+			ODM_BB_CFO_TRACKING |
+			ODM_BB_ENV_MONITOR;
+
+		pr_debug("[Warning] Supportability Init Warning !!!\n");
+		break;
+	}
+
+	return support_ability;
+}
+#endif
+
+void phydm_fwoffload_ability_init(struct dm_struct *dm,
+				  enum phydm_offload_ability offload_ability)
+{
+	switch (offload_ability) {
+	case PHYDM_PHY_PARAM_OFFLOAD:
+		if (dm->support_ic_type &
+		    (ODM_RTL8814A | ODM_RTL8822B | ODM_RTL8821C))
+			dm->fw_offload_ability |= PHYDM_PHY_PARAM_OFFLOAD;
+		break;
+
+	case PHYDM_RF_IQK_OFFLOAD:
+		dm->fw_offload_ability |= PHYDM_RF_IQK_OFFLOAD;
+		break;
+
+	default:
+		PHYDM_DBG(dm, ODM_COMP_INIT, "fwofflad, wrong init type!!\n");
+		break;
+	}
+
+	PHYDM_DBG(dm, ODM_COMP_INIT, "fw_offload_ability = %x\n",
+		  dm->fw_offload_ability);
+}
+
+void phydm_fwoffload_ability_clear(struct dm_struct *dm,
+				   enum phydm_offload_ability offload_ability)
+{
+	switch (offload_ability) {
+	case PHYDM_PHY_PARAM_OFFLOAD:
+		if (dm->support_ic_type &
+		    (ODM_RTL8814A | ODM_RTL8822B | ODM_RTL8821C))
+			dm->fw_offload_ability &= (~PHYDM_PHY_PARAM_OFFLOAD);
+		break;
+
+	case PHYDM_RF_IQK_OFFLOAD:
+		dm->fw_offload_ability &= (~PHYDM_RF_IQK_OFFLOAD);
+		break;
+
+	default:
+		PHYDM_DBG(dm, ODM_COMP_INIT, "fwofflad, wrong init type!!\n");
+		break;
+	}
+
+	PHYDM_DBG(dm, ODM_COMP_INIT, "fw_offload_ability = %x\n",
+		  dm->fw_offload_ability);
+}
+
+void phydm_supportability_init(void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	u64 support_ability;
+
+	if (*dm->mp_mode) {
+		support_ability = 0;
+	} else {
+		#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN))
+		support_ability = phydm_supportability_init_win(dm);
+		#elif (DM_ODM_SUPPORT_TYPE & (ODM_AP))
+		support_ability = phydm_supportability_init_ap(dm);
+		#elif(DM_ODM_SUPPORT_TYPE & (ODM_CE))
+		support_ability = phydm_supportability_init_ce(dm);
+		#elif(DM_ODM_SUPPORT_TYPE & (ODM_IOT))
+		support_ability = phydm_supportability_init_iot(dm);
+		#endif
+
+		/*@[Config Antenna Diveristy]*/
+		if (IS_FUNC_EN(dm->enable_antdiv))
+			support_ability |= ODM_BB_ANT_DIV;
+
+		/*@[Config Adaptive SOML]*/
+		if (IS_FUNC_EN(dm->en_adap_soml))
+			support_ability |= ODM_BB_ADAPTIVE_SOML;
+
+		/*@[Config Adaptivity]*/
+		if (IS_FUNC_EN(dm->enable_adaptivity))
+			support_ability |= ODM_BB_ADAPTIVITY;
+	}
+	odm_cmn_info_init(dm, ODM_CMNINFO_ABILITY, support_ability);
+	PHYDM_DBG(dm, ODM_COMP_INIT,
+		  "IC = ((0x%x)), Supportability Init = ((0x%llx))\n",
+		  dm->support_ic_type, dm->support_ability);
+}
+
+void phydm_rfe_init(void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+
+	PHYDM_DBG(dm, ODM_COMP_INIT, "RFE_Init\n");
+#if (RTL8822B_SUPPORT == 1)
+	if (dm->support_ic_type == ODM_RTL8822B)
+		phydm_rfe_8822b_init(dm);
+#endif
+}
+
+void phydm_dm_early_init(struct dm_struct *dm)
+{
+	#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
+	halrf_init(dm);
+	#endif
+}
+
+void odm_dm_init(struct dm_struct *dm)
+{
+	halrf_init(dm);
+	phydm_supportability_init(dm);
+	phydm_rfe_init(dm);
+	phydm_common_info_self_init(dm);
+	phydm_rx_phy_status_init(dm);
+#ifdef PHYDM_AUTO_DEGBUG
+	phydm_auto_dbg_engine_init(dm);
+#endif
+	phydm_dig_init(dm);
+#ifdef PHYDM_SUPPORT_CCKPD
+	phydm_cck_pd_init(dm);
+#endif
+	phydm_env_monitor_init(dm);
+	phydm_adaptivity_init(dm);
+	phydm_ra_info_init(dm);
+	phydm_rssi_monitor_init(dm);
+	phydm_cfo_tracking_init(dm);
+	phydm_rf_init(dm);
+	phydm_dc_cancellation(dm);
+#ifdef PHYDM_TXA_CALIBRATION
+	phydm_txcurrentcalibration(dm);
+	phydm_get_pa_bias_offset(dm);
+#endif
+#ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY
+	odm_antenna_diversity_init(dm);
+#endif
+#ifdef CONFIG_ADAPTIVE_SOML
+	phydm_adaptive_soml_init(dm);
+#endif
+#ifdef CONFIG_PATH_DIVERSITY
+	phydm_path_diversity_init(dm);
+#endif
+#ifdef CONFIG_DYNAMIC_TX_TWR
+	phydm_dynamic_tx_power_init(dm);
+#endif
+#if (PHYDM_LA_MODE_SUPPORT == 1)
+	adc_smp_init(dm);
+#endif
+
+#ifdef PHYDM_BEAMFORMING_VERSION1
+	phydm_beamforming_init(dm);
+#endif
+
+#if (RTL8188E_SUPPORT == 1)
+	odm_ra_info_init_all(dm);
+#endif
+#ifdef PHYDM_PRIMARY_CCA
+	phydm_primary_cca_init(dm);
+#endif
+#ifdef CONFIG_PSD_TOOL
+	phydm_psd_init(dm);
+#endif
+
+#ifdef CONFIG_SMART_ANTENNA
+	phydm_smt_ant_init(dm);
+#endif
+#ifdef PHYDM_LNA_SAT_CHK_SUPPORT
+	phydm_lna_sat_check_init(dm);
+#endif
+#ifdef CONFIG_MCC_DM
+	#if (RTL8822B_SUPPORT == 1)
+	phydm_mcc_init(dm);
+	#endif
+#endif
+}
+
+void odm_dm_reset(struct dm_struct *dm)
+{
+	struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
+
+	#ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY
+	odm_ant_div_reset(dm);
+	#endif
+	phydm_set_edcca_threshold_api(dm, dig_t->cur_ig_value);
+}
+
+void phydm_supportability_en(void *dm_void, char input[][16], u32 *_used,
+			     char *output, u32 *_out_len)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	u32 dm_value[10] = {0};
+	u64 pre_support_ability, one = 1;
+	u64 comp = 0;
+	u32 used = *_used;
+	u32 out_len = *_out_len;
+	u8 i;
+
+	for (i = 0; i < 5; i++) {
+		if (input[i + 1])
+			PHYDM_SSCANF(input[i + 1], DCMD_DECIMAL, &dm_value[i]);
+	}
+
+	pre_support_ability = dm->support_ability;
+	comp = dm->support_ability;
+
+	PDM_SNPF(out_len, used, output + used, out_len - used,
+		 "\n================================\n");
+
+	if (dm_value[0] == 100) {
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "[Supportability] PhyDM Selection\n");
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "================================\n");
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "00. (( %s ))DIG\n",
+			 ((comp & ODM_BB_DIG) ? ("V") : (".")));
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "01. (( %s ))RA_MASK\n",
+			 ((comp & ODM_BB_RA_MASK) ? ("V") : (".")));
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "02. (( %s ))DYN_TXPWR\n",
+			 ((comp & ODM_BB_DYNAMIC_TXPWR) ? ("V") : (".")));
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "03. (( %s ))FA_CNT\n",
+			 ((comp & ODM_BB_FA_CNT) ? ("V") : (".")));
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "04. (( %s ))RSSI_MNTR\n",
+			 ((comp & ODM_BB_RSSI_MONITOR) ? ("V") : (".")));
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "05. (( %s ))CCK_PD\n",
+			 ((comp & ODM_BB_CCK_PD) ? ("V") : (".")));
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "06. (( %s ))ANT_DIV\n",
+			 ((comp & ODM_BB_ANT_DIV) ? ("V") : (".")));
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "07. (( %s ))SMT_ANT\n",
+			 ((comp & ODM_BB_SMT_ANT) ? ("V") : (".")));
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "08. (( %s ))PWR_TRAIN\n",
+			 ((comp & ODM_BB_PWR_TRAIN) ? ("V") : (".")));
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "09. (( %s ))RA\n",
+			 ((comp & ODM_BB_RATE_ADAPTIVE) ? ("V") : (".")));
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "10. (( %s ))PATH_DIV\n",
+			 ((comp & ODM_BB_PATH_DIV) ? ("V") : (".")));
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "11. (( %s ))DFS\n",
+			 ((comp & ODM_BB_DFS) ? ("V") : (".")));
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "12. (( %s ))DYN_ARFR\n",
+			 ((comp & ODM_BB_DYNAMIC_ARFR) ? ("V") : (".")));
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "13. (( %s ))ADAPTIVITY\n",
+			 ((comp & ODM_BB_ADAPTIVITY) ? ("V") : (".")));
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "14. (( %s ))CFO_TRACK\n",
+			 ((comp & ODM_BB_CFO_TRACKING) ? ("V") : (".")));
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "15. (( %s ))ENV_MONITOR\n",
+			 ((comp & ODM_BB_ENV_MONITOR) ? ("V") : (".")));
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "16. (( %s ))PRI_CCA\n",
+			 ((comp & ODM_BB_PRIMARY_CCA) ? ("V") : (".")));
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "17. (( %s ))ADPTV_SOML\n",
+			 ((comp & ODM_BB_ADAPTIVE_SOML) ? ("V") : (".")));
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "18. (( %s ))LNA_SAT_CHK\n",
+			 ((comp & ODM_BB_LNA_SAT_CHK) ? ("V") : (".")));
+
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "================================\n");
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "[Supportability] PhyDM offload ability\n");
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "================================\n");
+
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "00. (( %s ))PHY PARAM OFFLOAD\n",
+			 ((dm->fw_offload_ability & PHYDM_PHY_PARAM_OFFLOAD) ?
+			 ("V") : (".")));
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "01. (( %s ))RF IQK OFFLOAD\n",
+			 ((dm->fw_offload_ability & PHYDM_RF_IQK_OFFLOAD) ?
+			 ("V") : (".")));
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "================================\n");
+
+	} else if (dm_value[0] == 101) {
+		dm->support_ability = 0;
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "Disable all support_ability components\n");
+	} else {
+		if (dm_value[1] == 1) { /* @enable */
+			dm->support_ability |= (one << dm_value[0]);
+		} else if (dm_value[1] == 2) {/* @disable */
+			dm->support_ability &= ~(one << dm_value[0]);
+		} else {
+			PDM_SNPF(out_len, used, output + used, out_len - used,
+				 "[Warning!!!]  1:enable,  2:disable\n");
+		}
+	}
+	PDM_SNPF(out_len, used, output + used, out_len - used,
+		 "pre-supportability = 0x%llx\n", pre_support_ability);
+	PDM_SNPF(out_len, used, output + used, out_len - used,
+		 "Cur-supportability = 0x%llx\n", dm->support_ability);
+	PDM_SNPF(out_len, used, output + used, out_len - used,
+		 "================================\n");
+
+	*_used = used;
+	*_out_len = out_len;
+}
+
+void phydm_watchdog_lps_32k(struct dm_struct *dm)
+{
+	PHYDM_DBG(dm, DBG_COMMON_FLOW, "%s ======>\n", __func__);
+
+	phydm_common_info_self_update(dm);
+	phydm_rssi_monitor_check(dm);
+	phydm_dig_lps_32k(dm);
+	phydm_common_info_self_reset(dm);
+}
+
+void phydm_watchdog_lps(struct dm_struct *dm)
+{
+#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
+	PHYDM_DBG(dm, DBG_COMMON_FLOW, "%s ======>\n", __func__);
+
+	phydm_common_info_self_update(dm);
+	phydm_rssi_monitor_check(dm);
+	phydm_basic_dbg_message(dm);
+	phydm_receiver_blocking(dm);
+	phydm_false_alarm_counter_statistics(dm);
+	phydm_dig_by_rssi_lps(dm);
+	#ifdef PHYDM_SUPPORT_CCKPD
+	phydm_cck_pd_th(dm);
+	#endif
+	phydm_adaptivity(dm);
+	#if (DM_ODM_SUPPORT_TYPE & (ODM_CE))
+	#ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY
+	/*@enable AntDiv in PS mode, request from SD4 Jeff*/
+	odm_antenna_diversity(dm);
+	#endif
+	#endif
+	phydm_common_info_self_reset(dm);
+#endif
+}
+
+void phydm_watchdog_mp(struct dm_struct *dm)
+{
+}
+
+void phydm_pause_dm_watchdog(void *dm_void, enum phydm_pause_type pause_type)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+
+	if (pause_type == PHYDM_PAUSE) {
+		dm->disable_phydm_watchdog = 1;
+		PHYDM_DBG(dm, ODM_COMP_API, "PHYDM Stop\n");
+	} else {
+		dm->disable_phydm_watchdog = 0;
+		PHYDM_DBG(dm, ODM_COMP_API, "PHYDM Start\n");
+	}
+}
+
+u8 phydm_pause_func(void *dm_void, enum phydm_func_idx pause_func,
+		    enum phydm_pause_type pause_type,
+		    enum phydm_pause_level pause_lv, u8 val_lehgth,
+		    u32 *val_buf)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct phydm_func_poiner *func_t = &dm->phydm_func_handler;
+	s8 *pause_lv_pre = &dm->s8_dummy;
+	u32 *bkp_val = &dm->u32_dummy;
+	u32 ori_val[5] = {0};
+	u64 pause_func_bitmap = (u64)BIT(pause_func);
+	u8 i;
+	u8 en_2rcca;
+	u8 en_bw40m;
+	u8 pause_result = PAUSE_FAIL;
+
+	PHYDM_DBG(dm, ODM_COMP_API, "\n");
+	PHYDM_DBG(dm, ODM_COMP_API, "[%s][%s] LV=%d, Len=%d\n", __func__,
+		  ((pause_type == PHYDM_PAUSE) ? "Pause" :
+		  ((pause_type == PHYDM_RESUME) ? "Resume" : "Pause no_set")),
+		  pause_lv, val_lehgth);
+
+	if (pause_lv >= PHYDM_PAUSE_MAX_NUM) {
+		PHYDM_DBG(dm, ODM_COMP_API, "[WARNING]Wrong LV=%d\n", pause_lv);
+		return PAUSE_FAIL;
+	}
+
+	if (pause_func == F00_DIG) {
+		PHYDM_DBG(dm, ODM_COMP_API, "[DIG]\n");
+
+		if (val_lehgth != 1) {
+			PHYDM_DBG(dm, ODM_COMP_API, "[WARNING] length != 1\n");
+			return PAUSE_FAIL;
+		}
+
+		ori_val[0] = (u32)(dm->dm_dig_table.cur_ig_value); /*@0xc50*/
+		pause_lv_pre = &dm->pause_lv_table.lv_dig;
+		bkp_val = (u32 *)(&dm->dm_dig_table.rvrt_val);
+		/*@function pointer hook*/
+		func_t->pause_phydm_handler = phydm_set_dig_val;
+
+#ifdef PHYDM_SUPPORT_CCKPD
+	} else if (pause_func == F05_CCK_PD) {
+		PHYDM_DBG(dm, ODM_COMP_API, "[CCK_PD]\n");
+
+		if (val_lehgth != 1) {
+			PHYDM_DBG(dm, ODM_COMP_API, "[WARNING] length != 1\n");
+			return PAUSE_FAIL;
+		}
+
+		ori_val[0] = (u32)dm->dm_cckpd_table.cck_pd_lv;
+		pause_lv_pre = &dm->pause_lv_table.lv_cckpd;
+		bkp_val = (u32 *)(&dm->dm_cckpd_table.rvrt_val);
+		/*@function pointer hook*/
+		func_t->pause_phydm_handler = phydm_set_cckpd_val;
+#endif
+
+#ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY
+	} else if (pause_func == F06_ANT_DIV) {
+		PHYDM_DBG(dm, ODM_COMP_API, "[AntDiv]\n");
+
+		if (val_lehgth != 1) {
+			PHYDM_DBG(dm, ODM_COMP_API, "[WARNING] length != 1\n");
+			return PAUSE_FAIL;
+		}
+		/*@default antenna*/
+		ori_val[0] = (u32)(dm->dm_fat_table.rx_idle_ant);
+		pause_lv_pre = &dm->pause_lv_table.lv_antdiv;
+		bkp_val = (u32 *)(&dm->dm_fat_table.rvrt_val);
+		/*@function pointer hook*/
+		func_t->pause_phydm_handler = phydm_set_antdiv_val;
+
+#endif
+#ifdef PHYDM_SUPPORT_ADAPTIVITY
+	} else if (pause_func == F13_ADPTVTY) {
+		PHYDM_DBG(dm, ODM_COMP_API, "[Adaptivity]\n");
+
+		if (val_lehgth != 2) {
+			PHYDM_DBG(dm, ODM_COMP_API, "[WARNING] length != 2\n");
+			return PAUSE_FAIL;
+		}
+
+		ori_val[0] = (u32)(dm->adaptivity.th_l2h); /*th_l2h*/
+		ori_val[1] = (u32)(dm->adaptivity.th_h2l); /*th_h2l*/
+		pause_lv_pre = &dm->pause_lv_table.lv_adapt;
+		bkp_val = (u32 *)(&dm->adaptivity.rvrt_val);
+		/*@function pointer hook*/
+		func_t->pause_phydm_handler = phydm_set_edcca_val;
+
+#endif
+#ifdef CONFIG_ADAPTIVE_SOML
+	} else if (pause_func == F17_ADPTV_SOML) {
+		PHYDM_DBG(dm, ODM_COMP_API, "[AD-SOML]\n");
+
+		if (val_lehgth != 1) {
+			PHYDM_DBG(dm, ODM_COMP_API, "[WARNING] length != 1\n");
+			return PAUSE_FAIL;
+		}
+		/*SOML_ON/OFF*/
+		ori_val[0] = (u32)(dm->dm_soml_table.soml_on_off);
+
+		pause_lv_pre = &dm->pause_lv_table.lv_adsl;
+		bkp_val = (u32 *)(&dm->dm_soml_table.rvrt_val);
+		 /*@function pointer hook*/
+		func_t->pause_phydm_handler = phydm_set_adsl_val;
+
+#endif
+	} else {
+		PHYDM_DBG(dm, ODM_COMP_API, "[WARNING] error func idx\n");
+		return PAUSE_FAIL;
+	}
+
+	PHYDM_DBG(dm, ODM_COMP_API, "Pause_LV{new , pre} = {%d ,%d}\n",
+		  pause_lv, *pause_lv_pre);
+
+	if (pause_type == PHYDM_PAUSE || pause_type == PHYDM_PAUSE_NO_SET) {
+		if (pause_lv <= *pause_lv_pre) {
+			PHYDM_DBG(dm, ODM_COMP_API,
+				  "[PAUSE FAIL] Pre_LV >= Curr_LV\n");
+			return PAUSE_FAIL;
+		}
+
+		if (!(dm->pause_ability & pause_func_bitmap)) {
+			for (i = 0; i < val_lehgth; i++)
+				bkp_val[i] = ori_val[i];
+		}
+
+		dm->pause_ability |= pause_func_bitmap;
+		PHYDM_DBG(dm, ODM_COMP_API, "pause_ability=0x%llx\n",
+			  dm->pause_ability);
+
+		if (pause_type == PHYDM_PAUSE) {
+			for (i = 0; i < val_lehgth; i++)
+				PHYDM_DBG(dm, ODM_COMP_API,
+					  "[PAUSE SUCCESS] val_idx[%d]{New, Ori}={0x%x, 0x%x}\n",
+					  i, val_buf[i], bkp_val[i]);
+			func_t->pause_phydm_handler(dm, val_buf, val_lehgth);
+		} else {
+			for (i = 0; i < val_lehgth; i++)
+				PHYDM_DBG(dm, ODM_COMP_API,
+					  "[PAUSE NO Set: SUCCESS] val_idx[%d]{Ori}={0x%x}\n",
+					  i, bkp_val[i]);
+		}
+
+		*pause_lv_pre = pause_lv;
+		pause_result = PAUSE_SUCCESS;
+
+	} else if (pause_type == PHYDM_RESUME) {
+		if ((dm->pause_ability & pause_func_bitmap) == 0) {
+			PHYDM_DBG(dm, ODM_COMP_API,
+				  "[RESUME] No Need to Revert\n");
+			return PAUSE_SUCCESS;
+		}
+
+		dm->pause_ability &= ~pause_func_bitmap;
+		PHYDM_DBG(dm, ODM_COMP_API, "pause_ability=0x%llx\n",
+			  dm->pause_ability);
+
+		*pause_lv_pre = PHYDM_PAUSE_RELEASE;
+
+		for (i = 0; i < val_lehgth; i++) {
+			PHYDM_DBG(dm, ODM_COMP_API,
+				  "[RESUME] val_idx[%d]={0x%x}\n", i,
+				  bkp_val[i]);
+		}
+
+		func_t->pause_phydm_handler(dm, bkp_val, val_lehgth);
+
+		pause_result = PAUSE_SUCCESS;
+	} else {
+		PHYDM_DBG(dm, ODM_COMP_API, "[WARNING] error pause_type\n");
+		pause_result = PAUSE_FAIL;
+	}
+	return pause_result;
+}
+
+void phydm_pause_func_console(void *dm_void, char input[][16], u32 *_used,
+			      char *output, u32 *_out_len)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	char help[] = "-h";
+	u32 var1[10] = {0};
+	u32 used = *_used;
+	u32 out_len = *_out_len;
+	u32 i;
+	u8 length = 0;
+	u32 buf[5] = {0};
+	u8 set_result = 0;
+	enum phydm_func_idx func = 0;
+	enum phydm_pause_type type = 0;
+	enum phydm_pause_level lv = 0;
+
+	if ((strcmp(input[1], help) == 0)) {
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "{Func} {1:pause,2:pause no set 3:Resume} {lv:0~3} Val[5:0]\n");
+
+		goto out;
+	}
+
+	for (i = 0; i < 10; i++) {
+		if (input[i + 1])
+			PHYDM_SSCANF(input[i + 1], DCMD_HEX, &var1[i]);
+	}
+
+	func = (enum phydm_func_idx)var1[0];
+	type = (enum phydm_pause_type)var1[1];
+	lv = (enum phydm_pause_level)var1[2];
+
+	for (i = 0; i < 5; i++)
+		buf[i] = var1[3 + i];
+
+	if (func == F00_DIG) {
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "[DIG]\n");
+		length = 1;
+
+	} else if (func == F05_CCK_PD) {
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "[CCK_PD]\n");
+		length = 1;
+	} else if (func == F06_ANT_DIV) {
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "[Ant_Div]\n");
+		length = 1;
+	} else if (func == F13_ADPTVTY) {
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "[Adaptivity]\n");
+		length = 2;
+	} else if (func == F17_ADPTV_SOML) {
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "[ADSL]\n");
+		length = 1;
+	} else {
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "[Set Function Error]\n");
+		length = 0;
+	}
+
+	if (length != 0) {
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "{%s, lv=%d} val = %d, %d}\n",
+			 ((type == PHYDM_PAUSE) ? "Pause" :
+			 ((type == PHYDM_RESUME) ? "Resume" : "Pause no_set")),
+			 lv, var1[3], var1[4]);
+
+		set_result = phydm_pause_func(dm, func, type, lv, length, buf);
+	}
+
+	PDM_SNPF(out_len, used, output + used, out_len - used,
+		 "set_result = %d\n", set_result);
+
+out:
+	*_used = used;
+	*_out_len = out_len;
+}
+
+u8 phydm_stop_dm_watchdog_check(void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+
+	if (dm->disable_phydm_watchdog == 1) {
+		PHYDM_DBG(dm, DBG_COMMON_FLOW, "Disable phydm\n");
+		return true;
+	} else {
+		return false;
+	}
+}
+
+void phydm_watchdog(struct dm_struct *dm)
+{
+	PHYDM_DBG(dm, DBG_COMMON_FLOW, "%s ======>\n", __func__);
+
+	phydm_common_info_self_update(dm);
+	phydm_phy_info_update(dm);
+	phydm_rssi_monitor_check(dm);
+	phydm_basic_dbg_message(dm);
+	phydm_dm_summary(dm, FIRST_MACID);
+#ifdef PHYDM_AUTO_DEGBUG
+	phydm_auto_dbg_engine(dm);
+#endif
+	phydm_receiver_blocking(dm);
+
+	if (phydm_stop_dm_watchdog_check(dm) == true)
+		return;
+
+	phydm_hw_setting(dm);
+
+	#ifdef PHYDM_TDMA_DIG_SUPPORT
+	if (dm->original_dig_restore == 0)
+		phydm_tdma_dig_timer_check(dm);
+	else
+	#endif
+	{
+		phydm_false_alarm_counter_statistics(dm);
+		phydm_noisy_detection(dm);
+		phydm_dig(dm);
+		#ifdef PHYDM_SUPPORT_CCKPD
+		phydm_cck_pd_th(dm);
+		#endif
+	}
+
+#ifdef PHYDM_POWER_TRAINING_SUPPORT
+	phydm_update_power_training_state(dm);
+#endif
+	phydm_adaptivity(dm);
+	phydm_ra_info_watchdog(dm);
+#ifdef CONFIG_PATH_DIVERSITY
+	odm_path_diversity(dm);
+#endif
+	phydm_cfo_tracking(dm);
+#ifdef CONFIG_DYNAMIC_TX_TWR
+	phydm_dynamic_tx_power(dm);
+#endif
+#ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY
+	odm_antenna_diversity(dm);
+#endif
+#ifdef CONFIG_ADAPTIVE_SOML
+	phydm_adaptive_soml(dm);
+#endif
+
+#ifdef PHYDM_BEAMFORMING_VERSION1
+	phydm_beamforming_watchdog(dm);
+#endif
+
+	halrf_watchdog(dm);
+#ifdef PHYDM_PRIMARY_CCA
+	phydm_primary_cca(dm);
+#endif
+#if (DM_ODM_SUPPORT_TYPE == ODM_CE)
+	odm_dtc(dm);
+#endif
+
+	phydm_env_mntr_watchdog(dm);
+
+#ifdef PHYDM_LNA_SAT_CHK_SUPPORT
+	phydm_lna_sat_chk_watchdog(dm);
+#endif
+#ifdef CONFIG_MCC_DM
+	#if (RTL8822B_SUPPORT == 1)
+	phydm_mcc_switch(dm);
+	#endif
+#endif
+	phydm_common_info_self_reset(dm);
+}
+
+/*@
+ * Init /.. Fixed HW value. Only init time.
+ */
+void odm_cmn_info_init(struct dm_struct *dm, enum odm_cmninfo cmn_info,
+		       u64 value)
+{
+	/* This section is used for init value */
+	switch (cmn_info) {
+	/* @Fixed ODM value. */
+	case ODM_CMNINFO_ABILITY:
+		dm->support_ability = (u64)value;
+		break;
+
+	case ODM_CMNINFO_RF_TYPE:
+		dm->rf_type = (u8)value;
+		break;
+
+	case ODM_CMNINFO_PLATFORM:
+		dm->support_platform = (u8)value;
+		break;
+
+	case ODM_CMNINFO_INTERFACE:
+		dm->support_interface = (u8)value;
+		break;
+
+	case ODM_CMNINFO_MP_TEST_CHIP:
+		dm->is_mp_chip = (u8)value;
+		break;
+
+	case ODM_CMNINFO_IC_TYPE:
+		dm->support_ic_type = (u32)value;
+		break;
+
+	case ODM_CMNINFO_CUT_VER:
+		dm->cut_version = (u8)value;
+		break;
+
+	case ODM_CMNINFO_FAB_VER:
+		dm->fab_version = (u8)value;
+		break;
+	case ODM_CMNINFO_FW_VER:
+		dm->fw_version = (u8)value;
+		break;
+	case ODM_CMNINFO_FW_SUB_VER:
+		dm->fw_sub_version = (u8)value;
+		break;
+	case ODM_CMNINFO_RFE_TYPE:
+#if (RTL8821C_SUPPORT == 1)
+		if (dm->support_ic_type & ODM_RTL8821C)
+			dm->rfe_type_expand = (u8)value;
+		else
+#endif
+			dm->rfe_type = (u8)value;
+		phydm_init_hw_info_by_rfe(dm);
+		break;
+
+	case ODM_CMNINFO_RF_ANTENNA_TYPE:
+		dm->ant_div_type = (u8)value;
+		break;
+
+	case ODM_CMNINFO_WITH_EXT_ANTENNA_SWITCH:
+		dm->with_extenal_ant_switch = (u8)value;
+		break;
+
+#ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY
+	case ODM_CMNINFO_BE_FIX_TX_ANT:
+		dm->dm_fat_table.b_fix_tx_ant = (u8)value;
+		break;
+#endif
+
+	case ODM_CMNINFO_BOARD_TYPE:
+		if (!dm->is_init_hw_info_by_rfe)
+			dm->board_type = (u8)value;
+		break;
+
+	case ODM_CMNINFO_PACKAGE_TYPE:
+		if (!dm->is_init_hw_info_by_rfe)
+			dm->package_type = (u8)value;
+		break;
+
+	case ODM_CMNINFO_EXT_LNA:
+		if (!dm->is_init_hw_info_by_rfe)
+			dm->ext_lna = (u8)value;
+		break;
+
+	case ODM_CMNINFO_5G_EXT_LNA:
+		if (!dm->is_init_hw_info_by_rfe)
+			dm->ext_lna_5g = (u8)value;
+		break;
+
+	case ODM_CMNINFO_EXT_PA:
+		if (!dm->is_init_hw_info_by_rfe)
+			dm->ext_pa = (u8)value;
+		break;
+
+	case ODM_CMNINFO_5G_EXT_PA:
+		if (!dm->is_init_hw_info_by_rfe)
+			dm->ext_pa_5g = (u8)value;
+		break;
+
+	case ODM_CMNINFO_GPA:
+		if (!dm->is_init_hw_info_by_rfe)
+			dm->type_gpa = (u16)value;
+		break;
+
+	case ODM_CMNINFO_APA:
+		if (!dm->is_init_hw_info_by_rfe)
+			dm->type_apa = (u16)value;
+		break;
+
+	case ODM_CMNINFO_GLNA:
+		if (!dm->is_init_hw_info_by_rfe)
+			dm->type_glna = (u16)value;
+		break;
+
+	case ODM_CMNINFO_ALNA:
+		if (!dm->is_init_hw_info_by_rfe)
+			dm->type_alna = (u16)value;
+		break;
+
+	case ODM_CMNINFO_EXT_TRSW:
+		if (!dm->is_init_hw_info_by_rfe)
+			dm->ext_trsw = (u8)value;
+		break;
+	case ODM_CMNINFO_EXT_LNA_GAIN:
+		dm->ext_lna_gain = (u8)value;
+		break;
+	case ODM_CMNINFO_PATCH_ID:
+		dm->iot_table.win_patch_id = (u8)value;
+		break;
+	case ODM_CMNINFO_BINHCT_TEST:
+		dm->is_in_hct_test = (boolean)value;
+		break;
+	case ODM_CMNINFO_BWIFI_TEST:
+		dm->wifi_test = (u8)value;
+		break;
+	case ODM_CMNINFO_SMART_CONCURRENT:
+		dm->is_dual_mac_smart_concurrent = (boolean)value;
+		break;
+#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
+	case ODM_CMNINFO_CONFIG_BB_RF:
+		dm->config_bbrf = (boolean)value;
+		break;
+#endif
+	case ODM_CMNINFO_IQKPAOFF:
+		dm->rf_calibrate_info.is_iqk_pa_off = (boolean)value;
+		break;
+	case ODM_CMNINFO_REGRFKFREEENABLE:
+		dm->rf_calibrate_info.reg_rf_kfree_enable = (u8)value;
+		break;
+	case ODM_CMNINFO_RFKFREEENABLE:
+		dm->rf_calibrate_info.rf_kfree_enable = (u8)value;
+		break;
+	case ODM_CMNINFO_NORMAL_RX_PATH_CHANGE:
+		dm->normal_rx_path = (u8)value;
+		break;
+	case ODM_CMNINFO_EFUSE0X3D8:
+		dm->efuse0x3d8 = (u8)value;
+		break;
+	case ODM_CMNINFO_EFUSE0X3D7:
+		dm->efuse0x3d7 = (u8)value;
+		break;
+	case ODM_CMNINFO_ADVANCE_OTA:
+		dm->p_advance_ota = (u8)value;
+		break;
+
+#ifdef CONFIG_PHYDM_DFS_MASTER
+	case ODM_CMNINFO_DFS_REGION_DOMAIN:
+		dm->dfs_region_domain = (u8)value;
+		break;
+#endif
+	case ODM_CMNINFO_SOFT_AP_SPECIAL_SETTING:
+		dm->soft_ap_special_setting = (u32)value;
+		break;
+
+	case ODM_CMNINFO_X_CAP_SETTING:
+		dm->dm_cfo_track.crystal_cap_default = (u8)value;
+		break;
+
+	case ODM_CMNINFO_DPK_EN:
+		/*@dm->dpk_en = (u1Byte)value;*/
+		halrf_cmn_info_set(dm, HALRF_CMNINFO_DPK_EN, (u64)value);
+		break;
+
+	case ODM_CMNINFO_HP_HWID:
+		dm->hp_hw_id = (boolean)value;
+		break;
+	default:
+		break;
+	}
+}
+
+void odm_cmn_info_hook(struct dm_struct *dm, enum odm_cmninfo cmn_info,
+		       void *value)
+{
+	/* @Hook call by reference pointer. */
+	switch (cmn_info) {
+	/* @Dynamic call by reference pointer. */
+	case ODM_CMNINFO_TX_UNI:
+		dm->num_tx_bytes_unicast = (u64 *)value;
+		break;
+
+	case ODM_CMNINFO_RX_UNI:
+		dm->num_rx_bytes_unicast = (u64 *)value;
+		break;
+
+	case ODM_CMNINFO_BAND:
+		dm->band_type = (u8 *)value;
+		break;
+
+	case ODM_CMNINFO_SEC_CHNL_OFFSET:
+		dm->sec_ch_offset = (u8 *)value;
+		break;
+
+	case ODM_CMNINFO_SEC_MODE:
+		dm->security = (u8 *)value;
+		break;
+
+	case ODM_CMNINFO_BW:
+		dm->band_width = (u8 *)value;
+		break;
+
+	case ODM_CMNINFO_CHNL:
+		dm->channel = (u8 *)value;
+		break;
+
+	case ODM_CMNINFO_SCAN:
+		dm->is_scan_in_process = (boolean *)value;
+		break;
+
+	case ODM_CMNINFO_POWER_SAVING:
+		dm->is_power_saving = (boolean *)value;
+		break;
+
+	case ODM_CMNINFO_ONE_PATH_CCA:
+		dm->one_path_cca = (u8 *)value;
+		break;
+
+	case ODM_CMNINFO_DRV_STOP:
+		dm->is_driver_stopped = (boolean *)value;
+		break;
+	case ODM_CMNINFO_INIT_ON:
+		dm->pinit_adpt_in_progress = (boolean *)value;
+		break;
+
+	case ODM_CMNINFO_ANT_TEST:
+		dm->antenna_test = (u8 *)value;
+		break;
+
+	case ODM_CMNINFO_NET_CLOSED:
+		dm->is_net_closed = (boolean *)value;
+		break;
+
+	case ODM_CMNINFO_FORCED_RATE:
+		dm->forced_data_rate = (u16 *)value;
+		break;
+	case ODM_CMNINFO_ANT_DIV:
+		dm->enable_antdiv = (u8 *)value;
+		break;
+	case ODM_CMNINFO_ADAPTIVE_SOML:
+		dm->en_adap_soml = (u8 *)value;
+		break;
+	case ODM_CMNINFO_ADAPTIVITY:
+		dm->enable_adaptivity = (u8 *)value;
+		break;
+
+	case ODM_CMNINFO_P2P_LINK:
+		dm->dm_dig_table.is_p2p_in_process = (u8 *)value;
+		break;
+
+	case ODM_CMNINFO_IS1ANTENNA:
+		dm->is_1_antenna = (boolean *)value;
+		break;
+
+	case ODM_CMNINFO_RFDEFAULTPATH:
+		dm->rf_default_path = (u8 *)value;
+		break;
+
+	case ODM_CMNINFO_FCS_MODE:
+		dm->is_fcs_mode_enable = (boolean *)value;
+		break;
+
+	case ODM_CMNINFO_HUBUSBMODE:
+		dm->hub_usb_mode = (u8 *)value;
+		break;
+	case ODM_CMNINFO_FWDWRSVDPAGEINPROGRESS:
+		dm->is_fw_dw_rsvd_page_in_progress = (boolean *)value;
+		break;
+	case ODM_CMNINFO_TX_TP:
+		dm->current_tx_tp = (u32 *)value;
+		break;
+	case ODM_CMNINFO_RX_TP:
+		dm->current_rx_tp = (u32 *)value;
+		break;
+	case ODM_CMNINFO_SOUNDING_SEQ:
+		dm->sounding_seq = (u8 *)value;
+		break;
+#ifdef CONFIG_PHYDM_DFS_MASTER
+	case ODM_CMNINFO_DFS_MASTER_ENABLE:
+		dm->dfs_master_enabled = (u8 *)value;
+		break;
+#endif
+
+#ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY
+	case ODM_CMNINFO_FORCE_TX_ANT_BY_TXDESC:
+		dm->dm_fat_table.p_force_tx_ant_by_desc = (u8 *)value;
+		break;
+	case ODM_CMNINFO_SET_S0S1_DEFAULT_ANTENNA:
+		dm->dm_fat_table.p_default_s0_s1 = (u8 *)value;
+		break;
+	case ODM_CMNINFO_BF_ANTDIV_DECISION:
+		dm->dm_fat_table.is_no_csi_feedback = (boolean *)value;
+		break;
+#endif
+
+	case ODM_CMNINFO_SOFT_AP_MODE:
+		dm->soft_ap_mode = (u32 *)value;
+		break;
+	case ODM_CMNINFO_MP_MODE:
+		dm->mp_mode = (u8 *)value;
+		break;
+	case ODM_CMNINFO_INTERRUPT_MASK:
+		dm->interrupt_mask = (u32 *)value;
+		break;
+	case ODM_CMNINFO_BB_OPERATION_MODE:
+		dm->bb_op_mode = (u8 *)value;
+		break;
+	default:
+		/*do nothing*/
+		break;
+	}
+}
+
+/*@
+ * Update band/CHannel/.. The values are dynamic but non-per-packet.
+ */
+void odm_cmn_info_update(struct dm_struct *dm, u32 cmn_info, u64 value)
+{
+	/* This init variable may be changed in run time. */
+	switch (cmn_info) {
+	case ODM_CMNINFO_LINK_IN_PROGRESS:
+		dm->is_link_in_process = (boolean)value;
+		break;
+
+	case ODM_CMNINFO_ABILITY:
+		dm->support_ability = (u64)value;
+		break;
+
+	case ODM_CMNINFO_RF_TYPE:
+		dm->rf_type = (u8)value;
+		break;
+
+	case ODM_CMNINFO_WIFI_DIRECT:
+		dm->is_wifi_direct = (boolean)value;
+		break;
+
+	case ODM_CMNINFO_WIFI_DISPLAY:
+		dm->is_wifi_display = (boolean)value;
+		break;
+
+	case ODM_CMNINFO_LINK:
+		dm->is_linked = (boolean)value;
+		break;
+
+	case ODM_CMNINFO_CMW500LINK:
+		dm->iot_table.is_linked_cmw500 = (boolean)value;
+		break;
+
+	case ODM_CMNINFO_STATION_STATE:
+		dm->bsta_state = (boolean)value;
+		break;
+
+	case ODM_CMNINFO_RSSI_MIN:
+		dm->rssi_min = (u8)value;
+		break;
+
+	case ODM_CMNINFO_RSSI_MIN_BY_PATH:
+		dm->rssi_min_by_path = (u8)value;
+		break;
+
+	case ODM_CMNINFO_DBG_COMP:
+		dm->debug_components = (u64)value;
+		break;
+
+#ifdef ODM_CONFIG_BT_COEXIST
+	/* The following is for BT HS mode and BT coexist mechanism. */
+	case ODM_CMNINFO_BT_ENABLED:
+		dm->bt_info_table.is_bt_enabled = (boolean)value;
+		break;
+
+	case ODM_CMNINFO_BT_HS_CONNECT_PROCESS:
+		dm->bt_info_table.is_bt_connect_process = (boolean)value;
+		break;
+
+	case ODM_CMNINFO_BT_HS_RSSI:
+		dm->bt_info_table.bt_hs_rssi = (u8)value;
+		break;
+
+	case ODM_CMNINFO_BT_OPERATION:
+		dm->bt_info_table.is_bt_hs_operation = (boolean)value;
+		break;
+
+	case ODM_CMNINFO_BT_LIMITED_DIG:
+		dm->bt_info_table.is_bt_limited_dig = (boolean)value;
+		break;
+#endif
+
+	case ODM_CMNINFO_AP_TOTAL_NUM:
+		dm->ap_total_num = (u8)value;
+		break;
+
+#ifdef CONFIG_PHYDM_DFS_MASTER
+	case ODM_CMNINFO_DFS_REGION_DOMAIN:
+		dm->dfs_region_domain = (u8)value;
+		break;
+#endif
+
+	case ODM_CMNINFO_BT_CONTINUOUS_TURN:
+		dm->is_bt_continuous_turn = (boolean)value;
+		break;
+	default:
+		break;
+	}
+}
+
+u32 phydm_cmn_info_query(struct dm_struct *dm, enum phydm_info_query info_type)
+{
+	struct phydm_fa_struct *fa_t = &dm->false_alm_cnt;
+	struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
+	struct ccx_info *ccx_info = &dm->dm_ccx_info;
+
+	switch (info_type) {
+	/*@=== [FA Relative] ===========================================*/
+	case PHYDM_INFO_FA_OFDM:
+		return fa_t->cnt_ofdm_fail;
+
+	case PHYDM_INFO_FA_CCK:
+		return fa_t->cnt_cck_fail;
+
+	case PHYDM_INFO_FA_TOTAL:
+		return fa_t->cnt_all;
+
+	case PHYDM_INFO_CCA_OFDM:
+		return fa_t->cnt_ofdm_cca;
+
+	case PHYDM_INFO_CCA_CCK:
+		return fa_t->cnt_cck_cca;
+
+	case PHYDM_INFO_CCA_ALL:
+		return fa_t->cnt_cca_all;
+
+	case PHYDM_INFO_CRC32_OK_VHT:
+		return fa_t->cnt_vht_crc32_ok;
+
+	case PHYDM_INFO_CRC32_OK_HT:
+		return fa_t->cnt_ht_crc32_ok;
+
+	case PHYDM_INFO_CRC32_OK_LEGACY:
+		return fa_t->cnt_ofdm_crc32_ok;
+
+	case PHYDM_INFO_CRC32_OK_CCK:
+		return fa_t->cnt_cck_crc32_ok;
+
+	case PHYDM_INFO_CRC32_ERROR_VHT:
+		return fa_t->cnt_vht_crc32_error;
+
+	case PHYDM_INFO_CRC32_ERROR_HT:
+		return fa_t->cnt_ht_crc32_error;
+
+	case PHYDM_INFO_CRC32_ERROR_LEGACY:
+		return fa_t->cnt_ofdm_crc32_error;
+
+	case PHYDM_INFO_CRC32_ERROR_CCK:
+		return fa_t->cnt_cck_crc32_error;
+
+	case PHYDM_INFO_EDCCA_FLAG:
+		return fa_t->edcca_flag;
+
+	case PHYDM_INFO_OFDM_ENABLE:
+		return fa_t->ofdm_block_enable;
+
+	case PHYDM_INFO_CCK_ENABLE:
+		return fa_t->cck_block_enable;
+
+	case PHYDM_INFO_DBG_PORT_0:
+		return fa_t->dbg_port0;
+
+	case PHYDM_INFO_CRC32_OK_HT_AGG:
+		return fa_t->cnt_ht_crc32_ok_agg;
+
+	case PHYDM_INFO_CRC32_ERROR_HT_AGG:
+		return fa_t->cnt_ht_crc32_error_agg;
+
+	/*@=== [DIG] ================================================*/
+
+	case PHYDM_INFO_CURR_IGI:
+		return dig_t->cur_ig_value;
+
+	/*@=== [RSSI] ===============================================*/
+	case PHYDM_INFO_RSSI_MIN:
+		return (u32)dm->rssi_min;
+
+	case PHYDM_INFO_RSSI_MAX:
+		return (u32)dm->rssi_max;
+
+	case PHYDM_INFO_CLM_RATIO:
+		return (u32)ccx_info->clm_ratio;
+	case PHYDM_INFO_NHM_RATIO:
+		return (u32)ccx_info->nhm_ratio;
+	default:
+		return 0xffffffff;
+	}
+}
+
+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
+void odm_init_all_work_items(struct dm_struct *dm)
+{
+	void *adapter = dm->adapter;
+#if USE_WORKITEM
+
+#ifdef CONFIG_ADAPTIVE_SOML
+	odm_initialize_work_item(dm,
+				 &dm->dm_soml_table.phydm_adaptive_soml_workitem,
+				 (RT_WORKITEM_CALL_BACK)phydm_adaptive_soml_workitem_callback,
+				 (void *)adapter,
+				 "AdaptiveSOMLWorkitem");
+#endif
+
+#ifdef ODM_EVM_ENHANCE_ANTDIV
+	odm_initialize_work_item(dm,
+				 &dm->phydm_evm_antdiv_workitem,
+				 (RT_WORKITEM_CALL_BACK)phydm_evm_antdiv_workitem_callback,
+				 (void *)adapter,
+				 "EvmAntdivWorkitem");
+#endif
+
+#ifdef CONFIG_S0S1_SW_ANTENNA_DIVERSITY
+	odm_initialize_work_item(dm,
+				 &dm->dm_swat_table.phydm_sw_antenna_switch_workitem,
+				 (RT_WORKITEM_CALL_BACK)odm_sw_antdiv_workitem_callback,
+				 (void *)adapter,
+				 "AntennaSwitchWorkitem");
+#endif
+#if (defined(CONFIG_HL_SMART_ANTENNA))
+	odm_initialize_work_item(dm,
+				 &dm->dm_sat_table.hl_smart_antenna_workitem,
+				 (RT_WORKITEM_CALL_BACK)phydm_beam_switch_workitem_callback,
+				 (void *)adapter,
+				 "hl_smart_ant_workitem");
+
+	odm_initialize_work_item(dm,
+				 &dm->dm_sat_table.hl_smart_antenna_decision_workitem,
+				 (RT_WORKITEM_CALL_BACK)phydm_beam_decision_workitem_callback,
+				 (void *)adapter,
+				 "hl_smart_ant_decision_workitem");
+#endif
+
+	odm_initialize_work_item(
+		dm,
+		&dm->ra_rpt_workitem,
+		(RT_WORKITEM_CALL_BACK)halrf_update_init_rate_work_item_callback,
+		(void *)adapter,
+		"ra_rpt_workitem");
+
+#if (defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY)) || (defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY))
+	odm_initialize_work_item(
+		dm,
+		&dm->fast_ant_training_workitem,
+		(RT_WORKITEM_CALL_BACK)odm_fast_ant_training_work_item_callback,
+		(void *)adapter,
+		"fast_ant_training_workitem");
+#endif
+
+#endif /*#if USE_WORKITEM*/
+
+#if (BEAMFORMING_SUPPORT == 1)
+	odm_initialize_work_item(
+		dm,
+		&dm->beamforming_info.txbf_info.txbf_enter_work_item,
+		(RT_WORKITEM_CALL_BACK)hal_com_txbf_enter_work_item_callback,
+		(void *)adapter,
+		"txbf_enter_work_item");
+
+	odm_initialize_work_item(
+		dm,
+		&dm->beamforming_info.txbf_info.txbf_leave_work_item,
+		(RT_WORKITEM_CALL_BACK)hal_com_txbf_leave_work_item_callback,
+		(void *)adapter,
+		"txbf_leave_work_item");
+
+	odm_initialize_work_item(
+		dm,
+		&dm->beamforming_info.txbf_info.txbf_fw_ndpa_work_item,
+		(RT_WORKITEM_CALL_BACK)hal_com_txbf_fw_ndpa_work_item_callback,
+		(void *)adapter,
+		"txbf_fw_ndpa_work_item");
+
+	odm_initialize_work_item(
+		dm,
+		&dm->beamforming_info.txbf_info.txbf_clk_work_item,
+		(RT_WORKITEM_CALL_BACK)hal_com_txbf_clk_work_item_callback,
+		(void *)adapter,
+		"txbf_clk_work_item");
+
+	odm_initialize_work_item(
+		dm,
+		&dm->beamforming_info.txbf_info.txbf_rate_work_item,
+		(RT_WORKITEM_CALL_BACK)hal_com_txbf_rate_work_item_callback,
+		(void *)adapter,
+		"txbf_rate_work_item");
+
+	odm_initialize_work_item(
+		dm,
+		&dm->beamforming_info.txbf_info.txbf_status_work_item,
+		(RT_WORKITEM_CALL_BACK)hal_com_txbf_status_work_item_callback,
+		(void *)adapter,
+		"txbf_status_work_item");
+
+	odm_initialize_work_item(
+		dm,
+		&dm->beamforming_info.txbf_info.txbf_reset_tx_path_work_item,
+		(RT_WORKITEM_CALL_BACK)hal_com_txbf_reset_tx_path_work_item_callback,
+		(void *)adapter,
+		"txbf_reset_tx_path_work_item");
+
+	odm_initialize_work_item(
+		dm,
+		&dm->beamforming_info.txbf_info.txbf_get_tx_rate_work_item,
+		(RT_WORKITEM_CALL_BACK)hal_com_txbf_get_tx_rate_work_item_callback,
+		(void *)adapter,
+		"txbf_get_tx_rate_work_item");
+#endif
+
+	odm_initialize_work_item(
+		dm,
+		&dm->adaptivity.phydm_pause_edcca_work_item,
+		(RT_WORKITEM_CALL_BACK)phydm_pause_edcca_work_item_callback,
+		(void *)adapter,
+		"phydm_pause_edcca_work_item");
+
+	odm_initialize_work_item(
+		dm,
+		&dm->adaptivity.phydm_resume_edcca_work_item,
+		(RT_WORKITEM_CALL_BACK)phydm_resume_edcca_work_item_callback,
+		(void *)adapter,
+		"phydm_resume_edcca_work_item");
+
+#if (PHYDM_LA_MODE_SUPPORT == 1)
+	odm_initialize_work_item(
+		dm,
+		&dm->adcsmp.adc_smp_work_item,
+		(RT_WORKITEM_CALL_BACK)adc_smp_work_item_callback,
+		(void *)adapter,
+		"adc_smp_work_item");
+
+	odm_initialize_work_item(
+		dm,
+		&dm->adcsmp.adc_smp_work_item_1,
+		(RT_WORKITEM_CALL_BACK)adc_smp_work_item_callback,
+		(void *)adapter,
+		"adc_smp_work_item_1");
+#endif
+}
+
+void odm_free_all_work_items(struct dm_struct *dm)
+{
+#if USE_WORKITEM
+
+#ifdef CONFIG_S0S1_SW_ANTENNA_DIVERSITY
+	odm_free_work_item(&dm->dm_swat_table.phydm_sw_antenna_switch_workitem);
+#endif
+
+#ifdef CONFIG_ADAPTIVE_SOML
+	odm_free_work_item(&dm->dm_soml_table.phydm_adaptive_soml_workitem);
+#endif
+
+#ifdef ODM_EVM_ENHANCE_ANTDIV
+	odm_free_work_item(&dm->phydm_evm_antdiv_workitem);
+#endif
+
+#if (defined(CONFIG_HL_SMART_ANTENNA))
+	odm_free_work_item(&dm->dm_sat_table.hl_smart_antenna_workitem);
+	odm_free_work_item(&dm->dm_sat_table.hl_smart_antenna_decision_workitem);
+#endif
+
+#if (defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY)) || (defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY))
+	odm_free_work_item(&dm->fast_ant_training_workitem);
+#endif
+	odm_free_work_item(&dm->ra_rpt_workitem);
+/*odm_free_work_item((&dm->sbdcnt_workitem));*/
+#endif
+
+#if (BEAMFORMING_SUPPORT == 1)
+	odm_free_work_item((&dm->beamforming_info.txbf_info.txbf_enter_work_item));
+	odm_free_work_item((&dm->beamforming_info.txbf_info.txbf_leave_work_item));
+	odm_free_work_item((&dm->beamforming_info.txbf_info.txbf_fw_ndpa_work_item));
+	odm_free_work_item((&dm->beamforming_info.txbf_info.txbf_clk_work_item));
+	odm_free_work_item((&dm->beamforming_info.txbf_info.txbf_rate_work_item));
+	odm_free_work_item((&dm->beamforming_info.txbf_info.txbf_status_work_item));
+	odm_free_work_item((&dm->beamforming_info.txbf_info.txbf_reset_tx_path_work_item));
+	odm_free_work_item((&dm->beamforming_info.txbf_info.txbf_get_tx_rate_work_item));
+#endif
+
+	odm_free_work_item((&dm->adaptivity.phydm_pause_edcca_work_item));
+	odm_free_work_item((&dm->adaptivity.phydm_resume_edcca_work_item));
+
+#if (PHYDM_LA_MODE_SUPPORT == 1)
+	odm_free_work_item((&dm->adcsmp.adc_smp_work_item));
+	odm_free_work_item((&dm->adcsmp.adc_smp_work_item_1));
+#endif
+}
+#endif /*#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)*/
+
+void odm_init_all_timers(struct dm_struct *dm)
+{
+#if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY))
+	odm_ant_div_timers(dm, INIT_ANTDIV_TIMMER);
+#endif
+#if (defined(PHYDM_TDMA_DIG_SUPPORT))
+#ifdef IS_USE_NEW_TDMA
+	phydm_tdma_dig_timers(dm, INIT_TDMA_DIG_TIMMER);
+#endif
+#endif
+#ifdef CONFIG_ADAPTIVE_SOML
+	phydm_adaptive_soml_timers(dm, INIT_SOML_TIMMER);
+#endif
+#ifdef PHYDM_LNA_SAT_CHK_SUPPORT
+#ifdef PHYDM_LNA_SAT_CHK_TYPE1
+	phydm_lna_sat_chk_timers(dm, INIT_LNA_SAT_CHK_TIMMER);
+#endif
+#endif
+
+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
+	odm_initialize_timer(dm, &dm->sbdcnt_timer,
+			     (void *)phydm_sbd_callback, NULL, "SbdTimer");
+#if (BEAMFORMING_SUPPORT == 1)
+	odm_initialize_timer(dm, &dm->beamforming_info.txbf_info.txbf_fw_ndpa_timer,
+			     (void *)hal_com_txbf_fw_ndpa_timer_callback, NULL,
+			     "txbf_fw_ndpa_timer");
+#endif
+#endif
+
+#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
+#if (BEAMFORMING_SUPPORT == 1)
+	odm_initialize_timer(dm, &dm->beamforming_info.beamforming_timer,
+			     (void *)beamforming_sw_timer_callback, NULL,
+			     "beamforming_timer");
+#endif
+#endif
+}
+
+void odm_cancel_all_timers(struct dm_struct *dm)
+{
+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
+	/* @2012/01/12 MH Temp BSOD fix. We need to find NIC allocate mem fail reason in win7*/
+	if (dm->adapter == NULL)
+		return;
+#endif
+
+#if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY))
+	odm_ant_div_timers(dm, CANCEL_ANTDIV_TIMMER);
+#endif
+#ifdef CONFIG_ADAPTIVE_SOML
+	phydm_adaptive_soml_timers(dm, CANCEL_SOML_TIMMER);
+#endif
+#ifdef PHYDM_LNA_SAT_CHK_SUPPORT
+#ifdef PHYDM_LNA_SAT_CHK_TYPE1
+	phydm_lna_sat_chk_timers(dm, CANCEL_LNA_SAT_CHK_TIMMER);
+#endif
+#endif
+
+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
+	odm_cancel_timer(dm, &dm->sbdcnt_timer);
+#if (BEAMFORMING_SUPPORT == 1)
+	odm_cancel_timer(dm, &dm->beamforming_info.txbf_info.txbf_fw_ndpa_timer);
+#endif
+#endif
+
+#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
+#if (BEAMFORMING_SUPPORT == 1)
+	odm_cancel_timer(dm, &dm->beamforming_info.beamforming_timer);
+#endif
+#endif
+}
+
+void odm_release_all_timers(struct dm_struct *dm)
+{
+#if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY))
+	odm_ant_div_timers(dm, RELEASE_ANTDIV_TIMMER);
+#endif
+#ifdef CONFIG_ADAPTIVE_SOML
+	phydm_adaptive_soml_timers(dm, RELEASE_SOML_TIMMER);
+#endif
+#ifdef PHYDM_LNA_SAT_CHK_SUPPORT
+#ifdef PHYDM_LNA_SAT_CHK_TYPE1
+	phydm_lna_sat_chk_timers(dm, RELEASE_LNA_SAT_CHK_TIMMER);
+#endif
+#endif
+
+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
+	odm_release_timer(dm, &dm->sbdcnt_timer);
+#if (BEAMFORMING_SUPPORT == 1)
+	odm_release_timer(dm, &dm->beamforming_info.txbf_info.txbf_fw_ndpa_timer);
+#endif
+#endif
+
+#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
+#if (BEAMFORMING_SUPPORT == 1)
+	odm_release_timer(dm, &dm->beamforming_info.beamforming_timer);
+#endif
+#endif
+}
+
+#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
+void odm_init_all_threads(
+	struct dm_struct *dm)
+{
+#ifdef TPT_THREAD
+	k_tpt_task_init(dm->priv);
+#endif
+}
+
+void odm_stop_all_threads(
+	struct dm_struct *dm)
+{
+#ifdef TPT_THREAD
+	k_tpt_task_stop(dm->priv);
+#endif
+}
+#endif
+
+#if (DM_ODM_SUPPORT_TYPE == ODM_CE)
+/* @Justin: According to the current RRSI to adjust Response Frame TX power,
+ * 2012/11/05
+ */
+void odm_dtc(struct dm_struct *dm)
+{
+#ifdef CONFIG_DM_RESP_TXAGC
+/* RSSI higher than this value, start to decade TX power */
+#define DTC_BASE 35
+
+/* RSSI lower than this value, start to increase TX power */
+#define DTC_DWN_BASE (DTC_BASE - 5)
+
+	/* RSSI vs TX power step mapping: decade TX power */
+	static const u8 dtc_table_down[] = {
+		DTC_BASE,
+		(DTC_BASE + 5),
+		(DTC_BASE + 10),
+		(DTC_BASE + 15),
+		(DTC_BASE + 20),
+		(DTC_BASE + 25)};
+
+	/* RSSI vs TX power step mapping: increase TX power */
+	static const u8 dtc_table_up[] = {
+		DTC_DWN_BASE,
+		(DTC_DWN_BASE - 5),
+		(DTC_DWN_BASE - 10),
+		(DTC_DWN_BASE - 15),
+		(DTC_DWN_BASE - 15),
+		(DTC_DWN_BASE - 20),
+		(DTC_DWN_BASE - 20),
+		(DTC_DWN_BASE - 25),
+		(DTC_DWN_BASE - 25),
+		(DTC_DWN_BASE - 30),
+		(DTC_DWN_BASE - 35)};
+
+	u8 i;
+	u8 dtc_steps = 0;
+	u8 sign;
+	u8 resp_txagc = 0;
+
+#if 0
+	/* @As DIG is disabled, DTC is also disable */
+	if (!(dm->support_ability & ODM_XXXXXX))
+		return;
+#endif
+
+	if (dm->rssi_min > DTC_BASE) {
+		/* need to decade the CTS TX power */
+		sign = 1;
+		for (i = 0; i < ARRAY_SIZE(dtc_table_down); i++) {
+			if (dtc_table_down[i] >= dm->rssi_min || dtc_steps >= 6)
+				break;
+			else
+				dtc_steps++;
+		}
+	}
+#if 0
+	else if (dm->rssi_min > DTC_DWN_BASE) {
+		/* needs to increase the CTS TX power */
+		sign = 0;
+		dtc_steps = 1;
+		for (i = 0; i < ARRAY_SIZE(dtc_table_up); i++) {
+			if (dtc_table_up[i] <= dm->rssi_min || dtc_steps >= 10)
+				break;
+			else
+				dtc_steps++;
+		}
+	}
+#endif
+	else {
+		sign = 0;
+		dtc_steps = 0;
+	}
+
+	resp_txagc = dtc_steps | (sign << 4);
+	resp_txagc = resp_txagc | (resp_txagc << 5);
+	odm_write_1byte(dm, 0x06d9, resp_txagc);
+
+	PHYDM_DBG(dm, ODM_COMP_PWR_TRAIN,
+		  "%s rssi_min:%u, set RESP_TXAGC to %s %u\n", __func__,
+		  dm->rssi_min, sign ? "minus" : "plus", dtc_steps);
+#endif /* @CONFIG_RESP_TXAGC_ADJUST */
+}
+
+#endif /* @#if (DM_ODM_SUPPORT_TYPE == ODM_CE) */
+
+/*@<20170126, BB-Kevin>8188F D-CUT DC cancellation and 8821C*/
+void phydm_dc_cancellation(struct dm_struct *dm)
+{
+#ifdef PHYDM_DC_CANCELLATION
+	u32 offset_i_hex[PHYDM_MAX_RF_PATH] = {0};
+	u32 offset_q_hex[PHYDM_MAX_RF_PATH] = {0};
+	u32 reg_value32[PHYDM_MAX_RF_PATH] = {0};
+	u8 path = RF_PATH_A;
+	u8 set_result;
+
+	if (!(dm->support_ic_type & ODM_DC_CANCELLATION_SUPPORT))
+		return;
+	if ((dm->support_ic_type & ODM_RTL8188F) &&
+	    dm->cut_version < ODM_CUT_D)
+		return;
+	if ((dm->support_ic_type & ODM_RTL8192F) &&
+	    dm->cut_version == ODM_CUT_A)
+		return;
+
+	PHYDM_DBG(dm, ODM_COMP_API, "%s ======>\n", __func__);
+
+	/*@DC_Estimation (only for 2x2 ic now) */
+
+	for (path = RF_PATH_A; path < PHYDM_MAX_RF_PATH; path++) {
+		if (path > RF_PATH_A &&
+		    dm->support_ic_type & (ODM_RTL8821C | ODM_RTL8188F |
+					  ODM_RTL8710B))
+			break;
+		else if (path > RF_PATH_B &&
+			 dm->support_ic_type & (ODM_RTL8822B | ODM_RTL8192F))
+			break;
+		if (phydm_stop_ic_trx(dm, PHYDM_SET) == PHYDM_SET_FAIL) {
+			PHYDM_DBG(dm, ODM_COMP_API, "STOP_TRX_FAIL\n");
+			return;
+		}
+		odm_write_dig(dm, 0x7e);
+		/*@Disable LNA*/
+		if (dm->support_ic_type & ODM_RTL8821C)
+			halrf_rf_lna_setting(dm, HALRF_LNA_DISABLE);
+		/*Turn off 3-wire*/
+		phydm_stop_3_wire(dm, PHYDM_SET);
+		if (dm->support_ic_type & (ODM_RTL8188F | ODM_RTL8710B)) {
+			/*set debug port to 0x235*/
+			if (!phydm_set_bb_dbg_port(dm, DBGPORT_PRI_2, 0x235)) {
+				PHYDM_DBG(dm, ODM_COMP_API,
+					  "Set Debug port Fail\n");
+				return;
+			}
+		} else if (dm->support_ic_type & ODM_RTL8821C) {
+			if (!phydm_set_bb_dbg_port(dm, DBGPORT_PRI_2, 0x200)) {
+				/*set debug port to 0x200*/
+				PHYDM_DBG(dm, ODM_COMP_API,
+					  "Set Debug port Fail\n");
+				return;
+			}
+			phydm_bb_dbg_port_header_sel(dm, 0x0);
+		} else if (dm->support_ic_type & ODM_RTL8822B) {
+			if (path == RF_PATH_A &&
+			    !phydm_set_bb_dbg_port(dm, DBGPORT_PRI_2, 0x200)) {
+				/*set debug port to 0x200*/
+				PHYDM_DBG(dm, ODM_COMP_API,
+					  "Set Debug port Fail\n");
+				return;
+			}
+			if (path == RF_PATH_B &&
+			    !phydm_set_bb_dbg_port(dm, DBGPORT_PRI_2, 0x202)) {
+				/*set debug port to 0x200*/
+				PHYDM_DBG(dm, ODM_COMP_API,
+					  "Set Debug port Fail\n");
+				return;
+			}
+			phydm_bb_dbg_port_header_sel(dm, 0x0);
+		} else if (dm->support_ic_type & ODM_RTL8192F) {
+			if (path == RF_PATH_A &&
+			    !phydm_set_bb_dbg_port(dm, DBGPORT_PRI_2, 0x235)) {
+				/*set debug port to 0x235*/
+				PHYDM_DBG(dm, ODM_COMP_API,
+					  "Set Debug port Fail\n");
+				return;
+			}
+			if (path == RF_PATH_B &&
+			    !phydm_set_bb_dbg_port(dm, DBGPORT_PRI_2, 0x23d)) {
+				/*set debug port to 0x23d*/
+				PHYDM_DBG(dm, ODM_COMP_API,
+					  "Set Debug port Fail\n");
+				return;
+			}
+		}
+
+		/*@disable CCK DCNF*/
+		odm_set_bb_reg(dm, R_0xa78, MASKBYTE1, 0x0);
+
+		PHYDM_DBG(dm, ODM_COMP_API, "DC cancellation Begin!!!\n");
+
+		phydm_stop_ck320(dm, true); /*stop ck320*/
+
+		/* the same debug port both for path-a and path-b*/
+		reg_value32[path] = phydm_get_bb_dbg_port_val(dm);
+
+		phydm_stop_ck320(dm, false); /*start ck320*/
+
+		phydm_release_bb_dbg_port(dm);
+		/*Turn on 3-wire*/
+		phydm_stop_3_wire(dm, PHYDM_REVERT);
+		/*@Enable LNA*/
+		if (dm->support_ic_type & ODM_RTL8821C)
+			halrf_rf_lna_setting(dm, HALRF_LNA_ENABLE);
+
+		odm_write_dig(dm, 0x20);
+
+		set_result = phydm_stop_ic_trx(dm, PHYDM_REVERT);
+
+		PHYDM_DBG(dm, ODM_COMP_API, "DC cancellation OK!!!\n");
+	}
+
+	/*@DC_Cancellation*/
+	/*@DC compensation to CCK data path*/
+	odm_set_bb_reg(dm, R_0xa9c, BIT(20), 0x1);
+	if (dm->support_ic_type & (ODM_RTL8188F | ODM_RTL8710B)) {
+		offset_i_hex[0] = (reg_value32[0] & 0xffc0000) >> 18;
+		offset_q_hex[0] = (reg_value32[0] & 0x3ff00) >> 8;
+
+		/*@Before filling into registers,
+		 *offset should be multiplexed (-1)
+		 */
+		offset_i_hex[0] = (offset_i_hex[0] >= 0x200) ?
+				  (0x400 - offset_i_hex[0]) :
+				  (0x1ff - offset_i_hex[0]);
+		offset_q_hex[0] = (offset_q_hex[0] >= 0x200) ?
+				  (0x400 - offset_q_hex[0]) :
+				  (0x1ff - offset_q_hex[0]);
+
+		odm_set_bb_reg(dm, R_0x950, 0x1ff, offset_i_hex[0]);
+		odm_set_bb_reg(dm, R_0x950, 0x1ff0000, offset_q_hex[0]);
+	} else if (dm->support_ic_type & (ODM_RTL8821C | ODM_RTL8822B)) {
+		/* Path-a */
+		offset_i_hex[0] = (reg_value32[0] & 0xffc00) >> 10;
+		offset_q_hex[0] = reg_value32[0] & 0x3ff;
+
+		/*@Before filling into registers,
+		 *offset should be multiplexed (-1)
+		 */
+		offset_i_hex[0] = 0x400 - offset_i_hex[0];
+		offset_q_hex[0] = 0x400 - offset_q_hex[0];
+
+		odm_set_bb_reg(dm, R_0xc10, 0x3c000000,
+			       (0x3c0 & offset_i_hex[0]) >> 6);
+		odm_set_bb_reg(dm, R_0xc10, 0xfc00, 0x3f & offset_i_hex[0]);
+		odm_set_bb_reg(dm, R_0xc14, 0x3c000000,
+			       (0x3c0 & offset_q_hex[0]) >> 6);
+		odm_set_bb_reg(dm, R_0xc14, 0xfc00, 0x3f & offset_q_hex[0]);
+
+		/* Path-b */
+		if (dm->rf_type > RF_1T1R) {
+			offset_i_hex[1] = (reg_value32[1] & 0xffc00) >> 10;
+			offset_q_hex[1] = reg_value32[1] & 0x3ff;
+
+			/*@Before filling into registers,
+			 *offset should be multiplexed (-1)
+			 */
+			offset_i_hex[1] = 0x400 - offset_i_hex[1];
+			offset_q_hex[1] = 0x400 - offset_q_hex[1];
+
+			odm_set_bb_reg(dm, R_0xe10, 0x3c000000,
+				       (0x3c0 & offset_i_hex[1]) >> 6);
+			odm_set_bb_reg(dm, R_0xe10, 0xfc00,
+				       0x3f & offset_i_hex[1]);
+			odm_set_bb_reg(dm, R_0xe14, 0x3c000000,
+				       (0x3c0 & offset_q_hex[1]) >> 6);
+			odm_set_bb_reg(dm, R_0xe14, 0xfc00,
+				       0x3f & offset_q_hex[1]);
+		}
+	} else if (dm->support_ic_type & (ODM_RTL8192F)) {
+		/* Path-a I:df4[27:18],Q:df4[17:8]*/
+		offset_i_hex[0] = (reg_value32[0] & 0xffc0000) >> 18;
+		offset_q_hex[0] = (reg_value32[0] & 0x3ff00) >> 8;
+
+		/*@Before filling into registers,
+		 *offset should be multiplexed (-1)
+		 */
+		offset_i_hex[0] = (offset_i_hex[0] >= 0x200) ?
+				  (0x400 - offset_i_hex[0]) :
+				  (0xff - offset_i_hex[0]);
+		offset_q_hex[0] = (offset_q_hex[0] >= 0x200) ?
+				  (0x400 - offset_q_hex[0]) :
+				  (0xff - offset_q_hex[0]);
+		/*Path-a I:c10[7:0],Q:c10[15:8]*/
+		odm_set_bb_reg(dm, R_0xc10, 0xff, offset_i_hex[0]);
+		odm_set_bb_reg(dm, R_0xc10, 0xff00, offset_q_hex[0]);
+
+		/* Path-b */
+		if (dm->rf_type > RF_1T1R) {
+			/* @I:df4[27:18],Q:df4[17:8]*/
+			offset_i_hex[1] = (reg_value32[1] & 0xffc0000) >> 18;
+			offset_q_hex[1] = (reg_value32[1] & 0x3ff00) >> 8;
+
+			/*@Before filling into registers,
+			 *offset should be multiplexed (-1)
+			 */
+			offset_i_hex[1] = (offset_i_hex[1] >= 0x200) ?
+					  (0x400 - offset_i_hex[1]) :
+					  (0xff - offset_i_hex[1]);
+			offset_q_hex[1] = (offset_q_hex[1] >= 0x200) ?
+					  (0x400 - offset_q_hex[1]) :
+					  (0xff - offset_q_hex[1]);
+			/*Path-b I:c18[7:0],Q:c18[15:8]*/
+			odm_set_bb_reg(dm, R_0xc18, 0xff, offset_i_hex[1]);
+			odm_set_bb_reg(dm, R_0xc18, 0xff00, offset_q_hex[1]);
+		}
+	}
+#endif
+}
+
+void phydm_receiver_blocking(void *dm_void)
+{
+#ifdef CONFIG_RECEIVER_BLOCKING
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	u32 chnl = *dm->channel;
+	u8 bw = *dm->band_width;
+	u32 bb_regf0 = odm_get_bb_reg(dm, R_0xf0, 0xf000);
+
+	if (!(dm->support_ic_type & ODM_RECEIVER_BLOCKING_SUPPORT) ||
+	    !(dm->support_ability & ODM_BB_ADAPTIVITY))
+		return;
+
+	if ((dm->support_ic_type & ODM_RTL8188E && bb_regf0 < 8) ||
+	    dm->support_ic_type & ODM_RTL8192E) {
+	    /*@8188E_T version*/
+		if (dm->consecutive_idlel_time <= 10 || *dm->mp_mode)
+			goto end;
+
+		if (bw == CHANNEL_WIDTH_20 && chnl == 1) {
+			phydm_nbi_setting(dm, FUNC_ENABLE, chnl, 20, 2410,
+					  PHYDM_DONT_CARE);
+			dm->is_rx_blocking_en = true;
+		} else if ((bw == CHANNEL_WIDTH_20) && (chnl == 13)) {
+			phydm_nbi_setting(dm, FUNC_ENABLE, chnl, 20, 2473,
+					  PHYDM_DONT_CARE);
+			dm->is_rx_blocking_en = true;
+		} else if (dm->is_rx_blocking_en && chnl != 1 && chnl != 13) {
+			phydm_nbi_enable(dm, FUNC_DISABLE);
+			odm_set_bb_reg(dm, R_0xc40, 0x1f000000, 0x1f);
+			dm->is_rx_blocking_en = false;
+		}
+		return;
+	} else if ((dm->support_ic_type & ODM_RTL8188E && bb_regf0 >= 8)) {
+	/*@8188E_S version*/
+		if (dm->consecutive_idlel_time <= 10 || *dm->mp_mode)
+			goto end;
+
+		if (bw == CHANNEL_WIDTH_20 && chnl == 13) {
+			phydm_nbi_setting(dm, FUNC_ENABLE, chnl, 20, 2473,
+					  PHYDM_DONT_CARE);
+			dm->is_rx_blocking_en = true;
+		} else if (dm->is_rx_blocking_en && chnl != 13) {
+			phydm_nbi_enable(dm, FUNC_DISABLE);
+			odm_set_bb_reg(dm, R_0xc40, 0x1f000000, 0x1f);
+			dm->is_rx_blocking_en = false;
+		}
+		return;
+	}
+
+end:
+	if (dm->is_rx_blocking_en) {
+		phydm_nbi_enable(dm, FUNC_DISABLE);
+		odm_set_bb_reg(dm, R_0xc40, 0x1f000000, 0x1f);
+		dm->is_rx_blocking_en = false;
+	}
+#endif
+}
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/phydm_cck_pd.c linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/phydm_cck_pd.c
--- linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/phydm_cck_pd.c	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/phydm_cck_pd.c	2020-04-10 16:35:06.823660394 +0300
@@ -0,0 +1,1076 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017  Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * The full GNU General Public License is included in this distribution in the
+ * file called LICENSE.
+ *
+ * Contact Information:
+ * wlanfae <wlanfae@realtek.com>
+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
+ * Hsinchu 300, Taiwan.
+ *
+ * Larry Finger <Larry.Finger@lwfinger.net>
+ *
+ *****************************************************************************/
+
+/*@************************************************************
+ * include files
+ ************************************************************/
+
+#include "mp_precomp.h"
+#include "phydm_precomp.h"
+
+#ifdef PHYDM_SUPPORT_CCKPD
+#ifdef PHYDM_COMPILE_CCKPD_TYPE1
+void phydm_write_cck_pd_type1(void *dm_void, u8 cca_th)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct phydm_cckpd_struct *cckpd_t = &dm->dm_cckpd_table;
+
+	PHYDM_DBG(dm, DBG_CCKPD, "[%s] cck_cca_th=((0x%x))\n",
+		  __func__, cca_th);
+
+	odm_write_1byte(dm, R_0xa0a, cca_th);
+	cckpd_t->cur_cck_cca_thres = cca_th;
+}
+
+void phydm_set_cckpd_lv_type1(void *dm_void, enum cckpd_lv lv)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct phydm_cckpd_struct *cckpd_t = &dm->dm_cckpd_table;
+	u8 pd_th = 0;
+
+	PHYDM_DBG(dm, DBG_CCKPD, "%s ======>\n", __func__);
+	PHYDM_DBG(dm, DBG_CCKPD, "lv: (%d) -> (%d)\n", cckpd_t->cck_pd_lv, lv);
+
+	if (cckpd_t->cck_pd_lv == lv) {
+		PHYDM_DBG(dm, DBG_CCKPD, "stay in lv=%d\n", lv);
+		return;
+	}
+
+	cckpd_t->cck_pd_lv = lv;
+	cckpd_t->cck_fa_ma = CCK_FA_MA_RESET;
+
+	if (lv == CCK_PD_LV_4)
+		pd_th = 0xed;
+	else if (lv == CCK_PD_LV_3)
+		pd_th = 0xdd;
+	else if (lv == CCK_PD_LV_2)
+		pd_th = 0xcd;
+	else if (lv == CCK_PD_LV_1)
+		pd_th = 0x83;
+	else if (lv == CCK_PD_LV_0)
+		pd_th = 0x40;
+
+	phydm_write_cck_pd_type1(dm, pd_th);
+}
+
+void phydm_cckpd_type1(void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
+	struct phydm_cckpd_struct *cckpd_t = &dm->dm_cckpd_table;
+	enum cckpd_lv lv = CCK_PD_LV_INIT;
+	boolean is_update = true;
+
+	if (dm->is_linked) {
+	#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
+		if (dm->rssi_min > 60) {
+			lv = CCK_PD_LV_3;
+		} else if (dm->rssi_min > 35) {
+			lv = CCK_PD_LV_2;
+		} else if (dm->rssi_min > 20) {
+			if (cckpd_t->cck_fa_ma > 500)
+				lv = CCK_PD_LV_2;
+			else if (cckpd_t->cck_fa_ma < 250)
+				lv = CCK_PD_LV_1;
+			else
+				is_update = false;
+		} else { /*RSSI < 20*/
+			lv = CCK_PD_LV_1;
+		}
+	#else /*ODM_AP*/
+		if (dig_t->cur_ig_value > 0x32)
+			lv = CCK_PD_LV_4;
+		else if (dig_t->cur_ig_value > 0x2a)
+			lv = CCK_PD_LV_3;
+		else if (dig_t->cur_ig_value > 0x24)
+			lv = CCK_PD_LV_2;
+		else
+			lv = CCK_PD_LV_1;
+	#endif
+	} else {
+		if (cckpd_t->cck_fa_ma > 1000)
+			lv = CCK_PD_LV_1;
+		else if (cckpd_t->cck_fa_ma < 500)
+			lv = CCK_PD_LV_0;
+		else
+			is_update = false;
+	}
+
+	/*[Abnormal case] =================================================*/
+	#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
+	/*@HP 22B LPS power consumption issue & [PCIE-1596]*/
+	if (dm->hp_hw_id && dm->traffic_load == TRAFFIC_ULTRA_LOW) {
+		lv = CCK_PD_LV_0;
+		PHYDM_DBG(dm, DBG_CCKPD, "CCKPD Abnormal case1\n");
+	} else if ((dm->p_advance_ota & PHYDM_ASUS_OTA_SETTING) &&
+	    cckpd_t->cck_fa_ma > 200 && dm->rssi_min <= 20) {
+		lv = CCK_PD_LV_1;
+		cckpd_t->cck_pd_lv = lv;
+		phydm_write_cck_pd_type1(dm, 0xc3); /*@for ASUS OTA test*/
+		is_update = false;
+		PHYDM_DBG(dm, DBG_CCKPD, "CCKPD Abnormal case2\n");
+	}
+	#elif (DM_ODM_SUPPORT_TYPE & (ODM_AP))
+		#ifdef MCR_WIRELESS_EXTEND
+		lv = CCK_PD_LV_2;
+		cckpd_t->cck_pd_lv = lv;
+		phydm_write_cck_pd_type1(dm, 0x43);
+		is_update = false;
+		PHYDM_DBG(dm, DBG_CCKPD, "CCKPD Abnormal case3\n");
+		#endif
+	#endif
+	/*=================================================================*/
+
+	if (is_update)
+		phydm_set_cckpd_lv_type1(dm, lv);
+
+	PHYDM_DBG(dm, DBG_CCKPD, "is_linked=%d, lv=%d, pd_th=0x%x\n\n",
+		  dm->is_linked, cckpd_t->cck_pd_lv,
+		  cckpd_t->cur_cck_cca_thres);
+}
+#endif /*#ifdef PHYDM_COMPILE_CCKPD_TYPE1*/
+
+#ifdef PHYDM_COMPILE_CCKPD_TYPE2
+void phydm_write_cck_pd_type2(void *dm_void, u8 cca_th, u8 cca_th_aaa)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct phydm_cckpd_struct *cckpd_t = &dm->dm_cckpd_table;
+
+	PHYDM_DBG(dm, DBG_CCKPD, "[%s] pd_th=0x%x, cs_ratio=0x%x\n",
+		  __func__, cca_th, cca_th_aaa);
+
+	odm_set_bb_reg(dm, R_0xa08, 0xf0000, cca_th);
+	odm_set_bb_reg(dm, R_0xaa8, 0x1f0000, cca_th_aaa);
+	cckpd_t->cur_cck_cca_thres = cca_th;
+	cckpd_t->cck_cca_th_aaa = cca_th_aaa;
+}
+
+void phydm_set_cckpd_lv_type2(void *dm_void, enum cckpd_lv lv)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct phydm_cckpd_struct *cckpd_t = &dm->dm_cckpd_table;
+	u8 pd_th = 0, cs_ratio = 0, cs_2r_offset = 0;
+	u8 cck_n_rx = 1;
+
+	PHYDM_DBG(dm, DBG_CCKPD, "%s ======>\n", __func__);
+	PHYDM_DBG(dm, DBG_CCKPD, "lv: (%d) -> (%d)\n", cckpd_t->cck_pd_lv, lv);
+
+	/*@r_mrx & r_cca_mrc*/
+	cck_n_rx = (odm_get_bb_reg(dm, R_0xa2c, BIT(18)) &&
+		    odm_get_bb_reg(dm, R_0xa2c, BIT(22))) ? 2 : 1;
+
+	if (cckpd_t->cck_pd_lv == lv && cckpd_t->cck_n_rx == cck_n_rx) {
+		PHYDM_DBG(dm, DBG_CCKPD, "stay in lv=%d\n", lv);
+		return;
+	}
+
+	cckpd_t->cck_n_rx = cck_n_rx;
+	cckpd_t->cck_pd_lv = lv;
+	cckpd_t->cck_fa_ma = CCK_FA_MA_RESET;
+
+	if (lv == CCK_PD_LV_4) {
+		cs_ratio = cckpd_t->aaa_default + 8;
+		cs_2r_offset = 5;
+		pd_th = 0xd;
+	} else if (lv == CCK_PD_LV_3) {
+		cs_ratio = cckpd_t->aaa_default + 6;
+		cs_2r_offset = 4;
+		pd_th = 0xd;
+	} else if (lv == CCK_PD_LV_2) {
+		cs_ratio = cckpd_t->aaa_default + 4;
+		cs_2r_offset = 3;
+		pd_th = 0xd;
+	} else if (lv == CCK_PD_LV_1) {
+		cs_ratio = cckpd_t->aaa_default + 2;
+		cs_2r_offset = 1;
+		pd_th = 0x7;
+	} else if (lv == CCK_PD_LV_0) {
+		cs_ratio = cckpd_t->aaa_default;
+		cs_2r_offset = 0;
+		pd_th = 0x3;
+	}
+
+	if (cckpd_t->cck_n_rx == 2) {
+		if (cs_ratio >= cs_2r_offset)
+			cs_ratio = cs_ratio - cs_2r_offset;
+		else
+			cs_ratio = 0;
+	}
+	phydm_write_cck_pd_type2(dm, pd_th, cs_ratio);
+}
+
+void phydm_cckpd_type2(void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
+	struct phydm_cckpd_struct *cckpd_t = &dm->dm_cckpd_table;
+	enum cckpd_lv lv = CCK_PD_LV_INIT;
+	u8 igi = dig_t->cur_ig_value;
+	u8 rssi_min = dm->rssi_min;
+	boolean is_update = true;
+
+	PHYDM_DBG(dm, DBG_CCKPD, "%s ======>\n", __func__);
+
+	if (dm->is_linked) {
+		if (igi > 0x38 && rssi_min > 32) {
+			lv = CCK_PD_LV_4;
+		} else if (igi > 0x2a && rssi_min > 32) {
+			lv = CCK_PD_LV_3;
+		} else if (igi > 0x24 || (rssi_min > 24 && rssi_min <= 30)) {
+			lv = CCK_PD_LV_2;
+		} else if (igi <= 0x24 || rssi_min < 22) {
+			if (cckpd_t->cck_fa_ma > 1000) {
+				lv = CCK_PD_LV_1;
+			} else if (cckpd_t->cck_fa_ma < 500) {
+				lv = CCK_PD_LV_0;
+			} else {
+				is_update = false;
+			}
+		} else {
+			is_update = false;
+		}
+	} else {
+		if (cckpd_t->cck_fa_ma > 1000) {
+			lv = CCK_PD_LV_1;
+		} else if (cckpd_t->cck_fa_ma < 500) {
+			lv = CCK_PD_LV_0;
+		} else {
+			is_update = false;
+		}
+	}
+
+	if (is_update) {
+		phydm_set_cckpd_lv_type2(dm, lv);
+	}
+
+	PHYDM_DBG(dm, DBG_CCKPD,
+		  "is_linked=%d, lv=%d, n_rx=%d, cs_ratio=0x%x, pd_th=0x%x\n\n",
+		  dm->is_linked, cckpd_t->cck_pd_lv, cckpd_t->cck_n_rx,
+		  cckpd_t->cck_cca_th_aaa, cckpd_t->cur_cck_cca_thres);
+}
+#endif /*#ifdef PHYDM_COMPILE_CCKPD_TYPE2*/
+
+#ifdef PHYDM_COMPILE_CCKPD_TYPE3
+void phydm_write_cck_pd_type3(void *dm_void, u8 pd_th, u8 cs_ratio,
+			      enum cckpd_mode mode)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct phydm_cckpd_struct *cckpd_t = &dm->dm_cckpd_table;
+
+	PHYDM_DBG(dm, DBG_CCKPD,
+		  "[%s] mode=%d, pd_th=0x%x, cs_ratio=0x%x\n", __func__,
+		  mode, pd_th, cs_ratio);
+
+	switch (mode) {
+	case CCK_BW20_1R: /*RFBW20_1R*/
+	{
+		cckpd_t->cur_cck_pd_20m_1r = pd_th;
+		cckpd_t->cur_cck_cs_ratio_20m_1r = cs_ratio;
+		odm_set_bb_reg(dm, R_0xac8, 0xff, pd_th);
+		odm_set_bb_reg(dm, R_0xad0, 0x1f, cs_ratio);
+	} break;
+	case CCK_BW20_2R: /*RFBW20_2R*/
+	{
+		cckpd_t->cur_cck_pd_20m_2r = pd_th;
+		cckpd_t->cur_cck_cs_ratio_20m_2r = cs_ratio;
+		odm_set_bb_reg(dm, R_0xac8, 0xff00, pd_th);
+		odm_set_bb_reg(dm, R_0xad0, 0x3e0, cs_ratio);
+	} break;
+	case CCK_BW40_1R: /*RFBW40_1R*/
+	{
+		cckpd_t->cur_cck_pd_40m_1r = pd_th;
+		cckpd_t->cur_cck_cs_ratio_40m_1r = cs_ratio;
+		odm_set_bb_reg(dm, R_0xacc, 0xff, pd_th);
+		odm_set_bb_reg(dm, R_0xad0, 0x1f00000, cs_ratio);
+	} break;
+	case CCK_BW40_2R: /*RFBW40_2R*/
+	{
+		cckpd_t->cur_cck_pd_40m_2r = pd_th;
+		cckpd_t->cur_cck_cs_ratio_40m_2r = cs_ratio;
+		odm_set_bb_reg(dm, R_0xacc, 0xff00, pd_th);
+		odm_set_bb_reg(dm, R_0xad0, 0x3e000000, cs_ratio);
+	} break;
+
+	default:
+		/*@pr_debug("[%s] warning!\n", __func__);*/
+		break;
+	}
+}
+
+void phydm_set_cckpd_lv_type3(void *dm_void, enum cckpd_lv lv)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct phydm_cckpd_struct *cckpd_t = &dm->dm_cckpd_table;
+	enum cckpd_mode cck_mode = CCK_BW20_2R;
+	enum channel_width cck_bw = CHANNEL_WIDTH_20;
+	u8 cck_n_rx = 1;
+	u8 pd_th;
+	u8 cs_ratio;
+
+	PHYDM_DBG(dm, DBG_CCKPD, "%s ======>\n", __func__);
+	PHYDM_DBG(dm, DBG_CCKPD, "lv: (%d) -> (%d)\n", cckpd_t->cck_pd_lv, lv);
+
+	/*[Check Nrx]*/
+	cck_n_rx = (odm_get_bb_reg(dm, R_0xa2c, BIT(17))) ? 2 : 1;
+
+	/*[Check BW]*/
+	if (odm_get_bb_reg(dm, R_0x800, BIT(0)))
+		cck_bw = CHANNEL_WIDTH_40;
+	else
+		cck_bw = CHANNEL_WIDTH_20;
+
+	/*[Check LV]*/
+	if (cckpd_t->cck_pd_lv == lv &&
+	    cckpd_t->cck_n_rx == cck_n_rx &&
+	    cckpd_t->cck_bw == cck_bw) {
+		PHYDM_DBG(dm, DBG_CCKPD, "stay in lv=%d\n", lv);
+		return;
+	}
+
+	cckpd_t->cck_bw = cck_bw;
+	cckpd_t->cck_n_rx = cck_n_rx;
+	cckpd_t->cck_pd_lv = lv;
+	cckpd_t->cck_fa_ma = CCK_FA_MA_RESET;
+
+	if (cck_n_rx == 2) {
+		if (cck_bw == CHANNEL_WIDTH_20) {
+			pd_th = cckpd_t->cck_pd_20m_2r;
+			cs_ratio = cckpd_t->cck_cs_ratio_20m_2r;
+			cck_mode = CCK_BW20_2R;
+		} else {
+			pd_th = cckpd_t->cck_pd_40m_2r;
+			cs_ratio = cckpd_t->cck_cs_ratio_40m_2r;
+			cck_mode = CCK_BW40_2R;
+		}
+	} else {
+		if (cck_bw == CHANNEL_WIDTH_20) {
+			pd_th = cckpd_t->cck_pd_20m_1r;
+			cs_ratio = cckpd_t->cck_cs_ratio_20m_1r;
+			cck_mode = CCK_BW20_1R;
+		} else {
+			pd_th = cckpd_t->cck_pd_40m_1r;
+			cs_ratio = cckpd_t->cck_cs_ratio_40m_1r;
+			cck_mode = CCK_BW40_1R;
+		}
+	}
+
+	if (lv == CCK_PD_LV_4) {
+		if (cck_n_rx == 2) {
+			pd_th += 4;
+			cs_ratio += 2;
+		} else {
+			pd_th += 4;
+			cs_ratio += 3;
+		}
+	} else if (lv == CCK_PD_LV_3) {
+		if (cck_n_rx == 2) {
+			pd_th += 3;
+			cs_ratio += 1;
+		} else {
+			pd_th += 3;
+			cs_ratio += 2;
+		}
+	} else if (lv == CCK_PD_LV_2) {
+		pd_th += 2;
+		cs_ratio += 1;
+	} else if (lv == CCK_PD_LV_1) {
+		pd_th += 1;
+		cs_ratio += 1;
+	}
+	#if 0
+	else if (lv == CCK_PD_LV_0) {
+		pd_th += 0;
+		cs_ratio += 0;
+	}
+	#endif
+
+	phydm_write_cck_pd_type3(dm, pd_th, cs_ratio, cck_mode);
+}
+
+void phydm_cckpd_type3(void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct phydm_cckpd_struct *cckpd_t = &dm->dm_cckpd_table;
+	enum cckpd_lv lv = CCK_PD_LV_INIT;
+	u8 igi = dm->dm_dig_table.cur_ig_value;
+	boolean is_update = true;
+	u8 pd_th = 0;
+	u8 cs_ratio = 0;
+
+	PHYDM_DBG(dm, DBG_CCKPD, "%s ======>\n", __func__);
+
+	if (dm->is_linked) {
+		if (igi > 0x38 && dm->rssi_min > 32) {
+			lv = CCK_PD_LV_4;
+		} else if ((igi > 0x2a) && (dm->rssi_min > 32)) {
+			lv = CCK_PD_LV_3;
+		} else if ((igi > 0x24) ||
+			   (dm->rssi_min > 24 && dm->rssi_min <= 30)) {
+			lv = CCK_PD_LV_2;
+		} else if ((igi <= 0x24) || (dm->rssi_min < 22)) {
+			if (cckpd_t->cck_fa_ma > 1000)
+				lv = CCK_PD_LV_1;
+			else if (cckpd_t->cck_fa_ma < 500)
+				lv = CCK_PD_LV_0;
+			else
+				is_update = false;
+		}
+	} else {
+		if (cckpd_t->cck_fa_ma > 1000)
+			lv = CCK_PD_LV_1;
+		else if (cckpd_t->cck_fa_ma < 500)
+			lv = CCK_PD_LV_0;
+		else
+			is_update = false;
+	}
+
+	if (is_update)
+		phydm_set_cckpd_lv_type3(dm, lv);
+
+	if (cckpd_t->cck_n_rx == 2) {
+		if (cckpd_t->cck_bw == CHANNEL_WIDTH_20) {
+			pd_th = cckpd_t->cur_cck_pd_20m_2r;
+			cs_ratio = cckpd_t->cur_cck_cs_ratio_20m_2r;
+		} else {
+			pd_th = cckpd_t->cur_cck_pd_40m_2r;
+			cs_ratio = cckpd_t->cur_cck_cs_ratio_40m_2r;
+		}
+	} else {
+		if (cckpd_t->cck_bw == CHANNEL_WIDTH_20) {
+			pd_th = cckpd_t->cur_cck_pd_20m_1r;
+			cs_ratio = cckpd_t->cur_cck_cs_ratio_20m_1r;
+		} else {
+			pd_th = cckpd_t->cur_cck_pd_40m_1r;
+			cs_ratio = cckpd_t->cur_cck_cs_ratio_40m_1r;
+		}
+	}
+	PHYDM_DBG(dm, DBG_CCKPD,
+		  "[%dR][%dM] is_linked=%d, lv=%d, cs_ratio=0x%x, pd_th=0x%x\n\n",
+		  cckpd_t->cck_n_rx, 20 << cckpd_t->cck_bw, dm->is_linked,
+		  cckpd_t->cck_pd_lv, cs_ratio, pd_th);
+}
+
+void phydm_cck_pd_init_type3(void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct phydm_cckpd_struct *cckpd_t = &dm->dm_cckpd_table;
+	u32 reg_tmp = 0;
+
+	/*Get Default value*/
+	cckpd_t->cck_pd_20m_1r = (u8)odm_get_bb_reg(dm, R_0xac8, 0xff);
+	cckpd_t->cck_pd_20m_2r = (u8)odm_get_bb_reg(dm, R_0xac8, 0xff00);
+	cckpd_t->cck_pd_40m_1r = (u8)odm_get_bb_reg(dm, R_0xacc, 0xff);
+	cckpd_t->cck_pd_40m_2r = (u8)odm_get_bb_reg(dm, R_0xacc, 0xff00);
+
+	reg_tmp = odm_get_bb_reg(dm, R_0xad0, MASKDWORD);
+	cckpd_t->cck_cs_ratio_20m_1r = (u8)(reg_tmp & 0x1f);
+	cckpd_t->cck_cs_ratio_20m_2r = (u8)((reg_tmp & 0x3e0) >> 5);
+	cckpd_t->cck_cs_ratio_40m_1r = (u8)((reg_tmp & 0x1f00000) >> 20);
+	cckpd_t->cck_cs_ratio_40m_2r = (u8)((reg_tmp & 0x3e000000) >> 25);
+
+	phydm_set_cckpd_lv_type3(dm, CCK_PD_LV_0);
+}
+#endif /*#ifdef PHYDM_COMPILE_CCKPD_TYPE3*/
+
+#ifdef PHYDM_COMPILE_CCKPD_TYPE4
+void phydm_write_cck_pd_type4(void *dm_void, enum cckpd_lv lv,
+			      enum cckpd_mode mode)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct phydm_cckpd_struct *cckpd_t = &dm->dm_cckpd_table;
+	u32 val = 0;
+
+	PHYDM_DBG(dm, DBG_CCKPD, "write CCK CCA parameters(CS_ratio & PD)\n");
+	switch (mode) {
+	case CCK_BW20_1R: /*RFBW20_1R*/
+	{
+		val = cckpd_t->cck_pd_table_jgr3[0][0][0][lv];
+		odm_set_bb_reg(dm, R_0x1ac8, 0xff, val);
+		val = cckpd_t->cck_pd_table_jgr3[0][0][1][lv];
+		odm_set_bb_reg(dm, R_0x1ad0, 0x1f, val);
+	} break;
+	case CCK_BW40_1R: /*RFBW40_1R*/
+	{
+		val = cckpd_t->cck_pd_table_jgr3[1][0][0][lv];
+		odm_set_bb_reg(dm, R_0x1acc, 0xff, val);
+		val = cckpd_t->cck_pd_table_jgr3[1][0][1][lv];
+		odm_set_bb_reg(dm, R_0x1ad0, 0x01F00000, val);
+	} break;
+	#if (defined(PHYDM_COMPILE_ABOVE_2SS))
+	case CCK_BW20_2R: /*RFBW20_2R*/
+	{
+		val = cckpd_t->cck_pd_table_jgr3[0][1][0][lv];
+		odm_set_bb_reg(dm, R_0x1ac8, 0xff00, val);
+		val = cckpd_t->cck_pd_table_jgr3[0][1][1][lv];
+		odm_set_bb_reg(dm, R_0x1ad0, 0x3e0, val);
+	} break;
+	case CCK_BW40_2R: /*RFBW40_2R*/
+	{
+		val = cckpd_t->cck_pd_table_jgr3[1][1][0][lv];
+		odm_set_bb_reg(dm, R_0x1acc, 0xff00, val);
+		val = cckpd_t->cck_pd_table_jgr3[1][1][1][lv];
+		odm_set_bb_reg(dm, R_0x1ad0, 0x3E000000, val);
+	} break;
+	#endif
+	#if (defined(PHYDM_COMPILE_ABOVE_3SS))
+	case CCK_BW20_3R: /*RFBW20_3R*/
+	{
+		val = cckpd_t->cck_pd_table_jgr3[0][2][0][lv];
+		odm_set_bb_reg(dm, R_0x1ac8, 0xff0000, val);
+		val = cckpd_t->cck_pd_table_jgr3[0][2][1][lv];
+		odm_set_bb_reg(dm, R_0x1ad0, 0x7c00, val);
+	} break;
+	case CCK_BW40_3R: /*RFBW40_3R*/
+	{
+		val = cckpd_t->cck_pd_table_jgr3[1][2][0][lv];
+		odm_set_bb_reg(dm, R_0x1acc, 0xff0000, val);
+		val = cckpd_t->cck_pd_table_jgr3[1][2][1][lv] & 0x3;
+		odm_set_bb_reg(dm, R_0x1ad0, 0xC0000000, val);
+		val = (cckpd_t->cck_pd_table_jgr3[1][2][1][lv] & 0x1c) >> 2;
+		odm_set_bb_reg(dm, R_0x1ad4, 0x7, val);
+	} break;
+	#endif
+	#if (defined(PHYDM_COMPILE_ABOVE_4SS))
+	case CCK_BW20_4R: /*RFBW20_4R*/
+	{
+		val = cckpd_t->cck_pd_table_jgr3[0][3][0][lv];
+		odm_set_bb_reg(dm, R_0x1ac8, 0xff000000, val);
+		val = cckpd_t->cck_pd_table_jgr3[0][3][1][lv];
+		odm_set_bb_reg(dm, R_0x1ad0, 0xF8000, val);
+	} break;
+	case CCK_BW40_4R: /*RFBW40_4R*/
+	{
+		val = cckpd_t->cck_pd_table_jgr3[1][3][0][lv];
+		odm_set_bb_reg(dm, R_0x1acc, 0xff000000, val);
+		val = cckpd_t->cck_pd_table_jgr3[1][3][1][lv];
+		odm_set_bb_reg(dm, R_0x1ad4, 0xf8, val);
+	} break;
+	#endif
+	default:
+		/*@pr_debug("[%s] warning!\n", __func__);*/
+		break;
+	}
+}
+
+void phydm_set_cck_pd_lv_type4(void *dm_void, enum cckpd_lv lv)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct phydm_cckpd_struct *cckpd_t = &dm->dm_cckpd_table;
+	enum cckpd_mode cck_mode = CCK_BW20_2R;
+	enum channel_width cck_bw = CHANNEL_WIDTH_20;
+	u8 cck_n_rx;
+	u32 val;
+	/*u32 val_dbg = 0;*/
+
+	PHYDM_DBG(dm, DBG_CCKPD, "%s ======>\n", __func__);
+	PHYDM_DBG(dm, DBG_CCKPD, "lv: (%d) -> (%d)\n", cckpd_t->cck_pd_lv, lv);
+
+	/*[Check Nrx]*/
+	cck_n_rx = (u8)odm_get_bb_reg(dm, R_0x1a2c, 0x60000) + 1;
+
+	/*[Check BW]*/
+	val = odm_get_bb_reg(dm, R_0x9b0, 0xc);
+	if (val == 0)
+		cck_bw = CHANNEL_WIDTH_20;
+	else if (val == 1)
+		cck_bw = CHANNEL_WIDTH_40;
+	else
+		cck_bw = CHANNEL_WIDTH_80;
+
+	/*[Check LV]*/
+	if (cckpd_t->cck_pd_lv == lv &&
+	    cckpd_t->cck_n_rx == cck_n_rx &&
+	    cckpd_t->cck_bw == cck_bw) {
+		PHYDM_DBG(dm, DBG_CCKPD, "stay in lv=%d\n", lv);
+		return;
+	}
+
+	cckpd_t->cck_bw = cck_bw;
+	cckpd_t->cck_n_rx = cck_n_rx;
+	cckpd_t->cck_pd_lv = lv;
+	cckpd_t->cck_fa_ma = CCK_FA_MA_RESET;
+
+	switch (cck_n_rx) {
+	case 1: /*1R*/
+	{
+		if (cck_bw == CHANNEL_WIDTH_20)
+			cck_mode = CCK_BW20_1R;
+		else if (cck_bw == CHANNEL_WIDTH_40)
+			cck_mode = CCK_BW40_1R;
+	} break;
+	#if (defined(PHYDM_COMPILE_ABOVE_2SS))
+	case 2: /*2R*/
+	{
+		if (cck_bw == CHANNEL_WIDTH_20)
+			cck_mode = CCK_BW20_2R;
+		else if (cck_bw == CHANNEL_WIDTH_40)
+			cck_mode = CCK_BW40_2R;
+	} break;
+	#endif
+	#if (defined(PHYDM_COMPILE_ABOVE_3SS))
+	case 3: /*3R*/
+	{
+		if (cck_bw == CHANNEL_WIDTH_20)
+			cck_mode = CCK_BW20_3R;
+		else if (cck_bw == CHANNEL_WIDTH_40)
+			cck_mode = CCK_BW40_3R;
+	} break;
+	#endif
+	#if (defined(PHYDM_COMPILE_ABOVE_4SS))
+	case 4: /*4R*/
+	{
+		if (cck_bw == CHANNEL_WIDTH_20)
+			cck_mode = CCK_BW20_4R;
+		else if (cck_bw == CHANNEL_WIDTH_40)
+			cck_mode = CCK_BW40_4R;
+	} break;
+	#endif
+	default:
+		/*@pr_debug("[%s] warning!\n", __func__);*/
+		break;
+	}
+phydm_write_cck_pd_type4(dm, lv, cck_mode);
+}
+
+void phydm_read_cckpd_para_type4(void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct phydm_cckpd_struct *cckpd_t = &dm->dm_cckpd_table;
+	u8 bw = 0; /*r_RX_RF_BW*/
+	u8 n_rx = 0;
+	u8 curr_cck_pd_t[2][4][2];
+	u32 reg0 = 0;
+	u32 reg1 = 0;
+	u32 reg2 = 0;
+	u32 reg3 = 0;
+
+	bw = (u8)odm_get_bb_reg(dm, R_0x9b0, 0xc);
+	n_rx = (u8)odm_get_bb_reg(dm, R_0x1a2c, 0x60000) + 1;
+
+	reg0 = odm_get_bb_reg(dm, R_0x1ac8, MASKDWORD);
+	reg1 = odm_get_bb_reg(dm, R_0x1acc, MASKDWORD);
+	reg2 = odm_get_bb_reg(dm, R_0x1ad0, MASKDWORD);
+	reg3 = odm_get_bb_reg(dm, R_0x1ad4, MASKDWORD);
+	curr_cck_pd_t[0][0][0] = (u8)(reg0 & 0x000000ff);
+	curr_cck_pd_t[1][0][0] = (u8)(reg1 & 0x000000ff);
+	curr_cck_pd_t[0][0][1] = (u8)(reg2 & 0x0000001f);
+	curr_cck_pd_t[1][0][1] = (u8)((reg2 & 0x01f00000) >> 20);
+	#if (defined(PHYDM_COMPILE_ABOVE_2SS))
+	if (dm->support_ic_type & PHYDM_IC_ABOVE_2SS) {
+		curr_cck_pd_t[0][1][0] = (u8)((reg0 & 0x0000ff00) >> 8);
+		curr_cck_pd_t[1][1][0] = (u8)((reg1 & 0x0000ff00) >> 8);
+		curr_cck_pd_t[0][1][1] = (u8)((reg2 & 0x000003E0) >> 5);
+		curr_cck_pd_t[1][1][1] = (u8)((reg2 & 0x3E000000) >> 25);
+	}
+	#endif
+	#if (defined(PHYDM_COMPILE_ABOVE_3SS))
+	if (dm->support_ic_type & PHYDM_IC_ABOVE_3SS) {
+		curr_cck_pd_t[0][2][0] = (u8)((reg0 & 0x00ff0000) >> 16);
+		curr_cck_pd_t[1][2][0] = (u8)((reg1 & 0x00ff0000) >> 16);
+		curr_cck_pd_t[0][2][1] = (u8)((reg2 & 0x00007C00) >> 10);
+		curr_cck_pd_t[1][2][1] = (u8)((reg2 & 0xC0000000) >> 30) |
+					  ((reg3 & 0x7) << 3);
+	}
+	#endif
+	#if (defined(PHYDM_COMPILE_ABOVE_4SS))
+	if (dm->support_ic_type & PHYDM_IC_ABOVE_4SS) {
+		curr_cck_pd_t[0][3][0] = (u8)((reg0 & 0xff000000) >> 24);
+		curr_cck_pd_t[1][3][0] = (u8)((reg1 & 0xff000000) >> 24);
+		curr_cck_pd_t[0][3][1] = (u8)((reg2 & 0x000F8000) >> 15);
+		curr_cck_pd_t[1][3][1] = (u8)((reg3 & 0x000000F8) >> 3);
+	}
+	#endif
+
+	PHYDM_DBG(dm, DBG_CCKPD, "bw=%dM, Nrx=%d\n", 20 << bw, n_rx);
+	PHYDM_DBG(dm, DBG_CCKPD, "lv=%d, readback CS_th=%x, PD th=%x\n",
+		  cckpd_t->cck_pd_lv,
+		  curr_cck_pd_t[bw][n_rx - 1][1],
+		  curr_cck_pd_t[bw][n_rx - 1][0]);
+}
+
+void phydm_cckpd_type4(void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct phydm_cckpd_struct *cckpd_t = &dm->dm_cckpd_table;
+	u8 igi = dm->dm_dig_table.cur_ig_value;
+	enum cckpd_lv lv = 0;
+	boolean is_update = true;
+
+	PHYDM_DBG(dm, DBG_CCKPD, "%s ======>\n", __func__);
+
+	if (dm->is_linked) {
+		PHYDM_DBG(dm, DBG_CCKPD, "Linked!!!\n");
+		if (igi > 0x38 && dm->rssi_min > 32) {
+			lv = CCK_PD_LV_4;
+			PHYDM_DBG(dm, DBG_CCKPD, "Order 1\n");
+		} else if ((igi > 0x2a) && (dm->rssi_min > 32)) {
+			lv = CCK_PD_LV_3;
+			PHYDM_DBG(dm, DBG_CCKPD, "Order 2\n");
+		} else if ((igi > 0x24) ||
+			   (dm->rssi_min > 24 && dm->rssi_min <= 30)) {
+			lv = CCK_PD_LV_2;
+			PHYDM_DBG(dm, DBG_CCKPD, "Order 3\n");
+		} else if ((igi <= 0x24) || (dm->rssi_min < 22)) {
+			if (cckpd_t->cck_fa_ma > 1000) {
+				lv = CCK_PD_LV_1;
+				PHYDM_DBG(dm, DBG_CCKPD, "Order 4-1\n");
+			} else if (cckpd_t->cck_fa_ma < 500) {
+				lv = CCK_PD_LV_0;
+				PHYDM_DBG(dm, DBG_CCKPD, "Order 4-2\n");
+			} else {
+				is_update = false;
+				PHYDM_DBG(dm, DBG_CCKPD, "Order 4-3\n");
+			}
+		} else {
+			is_update = false;
+		}
+	} else {
+		PHYDM_DBG(dm, DBG_CCKPD, "UnLinked!!!\n");
+		if (cckpd_t->cck_fa_ma > 1000) {
+			lv = CCK_PD_LV_1;
+			PHYDM_DBG(dm, DBG_CCKPD, "Order 1\n");
+		} else if (cckpd_t->cck_fa_ma < 500) {
+			lv = CCK_PD_LV_0;
+			PHYDM_DBG(dm, DBG_CCKPD, "Order 2\n");
+		} else {
+			is_update = false;
+			PHYDM_DBG(dm, DBG_CCKPD, "Order 3\n");
+		}
+	}
+
+	if (is_update)
+		phydm_set_cck_pd_lv_type4(dm, lv);
+
+
+	PHYDM_DBG(dm, DBG_CCKPD, "setting CS_th = 0x%x, PD th = 0x%x\n",
+		  cckpd_t->cck_pd_table_jgr3[cckpd_t->cck_bw]
+		  [cckpd_t->cck_n_rx - 1][1][lv],
+		  cckpd_t->cck_pd_table_jgr3[cckpd_t->cck_bw]
+		  [cckpd_t->cck_n_rx - 1][0][lv]);
+
+	phydm_read_cckpd_para_type4(dm);
+}
+
+void phydm_cck_pd_init_type4(void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct phydm_cckpd_struct *cckpd_t = &dm->dm_cckpd_table;
+	u32 reg0 = 0;
+	u32 reg1 = 0;
+	u32 reg2 = 0;
+	u32 reg3 = 0;
+	u8 pd_step = 0;
+	u8 cck_bw = 0; /*r_RX_RF_BW*/
+	u8 cck_n_rx = 0;
+	u8 val = 0;
+	u8 i = 0;
+
+	PHYDM_DBG(dm, DBG_CCKPD, "[%s]======>\n", __func__);
+
+	#if 0
+	/*@
+	 *cckpd_t[0][0][0][0] =  1ac8[7:0]	r_PD_lim_RFBW20_1R
+	 *cckpd_t[0][1][0][0] =  1ac8[15:8]	r_PD_lim_RFBW20_2R
+	 *cckpd_t[0][2][0][0] =  1ac8[23:16]	r_PD_lim_RFBW20_3R
+	 *cckpd_t[0][3][0][0] =  1ac8[31:24]	r_PD_lim_RFBW20_4R
+	 *cckpd_t[1][0][0][0] =  1acc[7:0]	r_PD_lim_RFBW40_1R
+	 *cckpd_t[1][1][0][0] =  1acc[15:8]	r_PD_lim_RFBW40_2R
+	 *cckpd_t[1][2][0][0] =  1acc[23:16]	r_PD_lim_RFBW40_3R
+	 *cckpd_t[1][3][0][0] =  1acc[31:24]	r_PD_lim_RFBW40_4R
+	 *
+	 *
+	 *cckpd_t[0][0][1][0] =  1ad0[4:0]	r_CS_ratio_RFBW20_1R[4:0]
+	 *cckpd_t[0][1][1][0] =  1ad0[9:5]	r_CS_ratio_RFBW20_2R[4:0]
+	 *cckpd_t[0][2][1][0] =  1ad0[14:10]	r_CS_ratio_RFBW20_3R[4:0]
+	 *cckpd_t[0][3][1][0] =  1ad0[19:15]	r_CS_ratio_RFBW20_4R[4:0]
+	 *cckpd_t[1][0][1][0] =  1ad0[24:20]	r_CS_ratio_RFBW40_1R[4:0]
+	 *cckpd_t[1][1][1][0] =  1ad0[29:25]	r_CS_ratio_RFBW40_2R[4:0]
+	 *cckpd_t[1][2][1][0] =  1ad0[31:30]	r_CS_ratio_RFBW40_3R[1:0]
+	 *			  1ad4[2:0]	r_CS_ratio_RFBW40_3R[4:2]
+	 *cckpd_t[1][3][1][0] =  1ad4[7:3]	r_CS_ratio_RFBW40_4R[4:0]
+	 */
+	#endif
+	/*[Check Nrx]*/
+	cck_n_rx = (u8)odm_get_bb_reg(dm, R_0x1a2c, 0x60000) + 1;
+
+	/*[Check BW]*/
+	val = odm_get_bb_reg(dm, R_0x9b0, 0xc);
+	if (val == 0)
+		cck_bw = CHANNEL_WIDTH_20;
+	else if (val == 1)
+		cck_bw = CHANNEL_WIDTH_40;
+	else
+		cck_bw = CHANNEL_WIDTH_80;
+
+	cckpd_t->cck_bw = cck_bw;
+	cckpd_t->cck_n_rx = cck_n_rx;
+	reg0 = odm_get_bb_reg(dm, R_0x1ac8, MASKDWORD);
+	reg1 = odm_get_bb_reg(dm, R_0x1acc, MASKDWORD);
+	reg2 = odm_get_bb_reg(dm, R_0x1ad0, MASKDWORD);
+	reg3 = odm_get_bb_reg(dm, R_0x1ad4, MASKDWORD);
+
+	for (i = 0 ; i < CCK_PD_LV_MAX ; i++) {
+		pd_step = i * 2;
+
+		val = (u8)(reg0 & 0x000000ff) + pd_step;
+		PHYDM_DBG(dm, DBG_CCKPD, "lvl %d val = %x\n\n", i, val);
+		cckpd_t->cck_pd_table_jgr3[0][0][0][i] = val;
+
+		val = (u8)(reg1 & 0x000000ff) + pd_step;
+		cckpd_t->cck_pd_table_jgr3[1][0][0][i] = val;
+
+		val = (u8)(reg2 & 0x0000001F) + pd_step;
+		cckpd_t->cck_pd_table_jgr3[0][0][1][i] = val;
+
+		val = (u8)((reg2 & 0x01F00000) >> 20) + pd_step;
+		cckpd_t->cck_pd_table_jgr3[1][0][1][i] = val;
+
+		#ifdef PHYDM_COMPILE_ABOVE_2SS
+		if (dm->support_ic_type & PHYDM_IC_ABOVE_2SS) {
+			val = (u8)((reg0 & 0x0000ff00) >> 8) + pd_step;
+			cckpd_t->cck_pd_table_jgr3[0][1][0][i] = val;
+
+			val = (u8)((reg1 & 0x0000ff00) >> 8) + pd_step;
+			cckpd_t->cck_pd_table_jgr3[1][1][0][i] = val;
+
+			val = (u8)((reg2 & 0x000003E0) >> 5) + pd_step;
+			cckpd_t->cck_pd_table_jgr3[0][1][1][i] = val;
+
+			val = (u8)((reg2 & 0x3E000000) >> 25) + pd_step;
+			cckpd_t->cck_pd_table_jgr3[1][1][1][i] = val;
+		}
+		#endif
+
+		#ifdef PHYDM_COMPILE_ABOVE_3SS
+		if (dm->support_ic_type & PHYDM_IC_ABOVE_3SS) {
+			val = (u8)((reg0 & 0x00ff0000) >> 16) + pd_step;
+			cckpd_t->cck_pd_table_jgr3[0][2][0][i] = val;
+
+			val = (u8)((reg1 & 0x00ff0000) >> 16) + pd_step;
+			cckpd_t->cck_pd_table_jgr3[1][2][0][i] = val;
+			val = (u8)((reg2 & 0x00007C00) >> 10) + pd_step;
+			cckpd_t->cck_pd_table_jgr3[0][2][1][i] = val;
+			val = (u8)(((reg2 & 0xC0000000) >> 30) |
+			      ((reg3 & 0x7) << 3)) + pd_step;
+			cckpd_t->cck_pd_table_jgr3[1][2][1][i] = val;
+		}
+		#endif
+
+		#ifdef PHYDM_COMPILE_ABOVE_4SS
+		if (dm->support_ic_type & PHYDM_IC_ABOVE_4SS) {
+			val = (u8)((reg0 & 0xff000000) >> 24) + pd_step;
+			cckpd_t->cck_pd_table_jgr3[0][3][0][i] = val;
+
+			val = (u8)((reg1 & 0xff000000) >> 24) + pd_step;
+			cckpd_t->cck_pd_table_jgr3[1][3][0][i] = val;
+
+			val = (u8)((reg2 & 0x000F8000) >> 15) + pd_step;
+			cckpd_t->cck_pd_table_jgr3[0][3][1][i] = val;
+
+			val = (u8)((reg3 & 0x000000F8) >> 3) + pd_step;
+			cckpd_t->cck_pd_table_jgr3[1][3][1][i] = val;
+		}
+		#endif
+	}
+}
+#endif /*#ifdef PHYDM_COMPILE_CCKPD_TYPE4*/
+
+void phydm_set_cckpd_val(void *dm_void, u32 *val_buf, u8 val_len)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct phydm_cckpd_struct *cckpd_t = &dm->dm_cckpd_table;
+	enum cckpd_lv lv;
+
+	if (val_len != 1) {
+		PHYDM_DBG(dm, ODM_COMP_API, "[Error][CCKPD]Need val_len=1\n");
+		return;
+	}
+
+	lv = (enum cckpd_lv)val_buf[0];
+
+	if (lv > CCK_PD_LV_4) {
+		pr_debug("[%s] warning! lv=%d\n", __func__, lv);
+		return;
+	}
+
+	switch (cckpd_t->cckpd_hw_type) {
+	#ifdef PHYDM_COMPILE_CCKPD_TYPE1
+	case 1:
+		phydm_set_cckpd_lv_type1(dm, lv);
+		break;
+	#endif
+	#ifdef PHYDM_COMPILE_CCKPD_TYPE2
+	case 2:
+		phydm_set_cckpd_lv_type2(dm, lv);
+		break;
+	#endif
+	#ifdef PHYDM_COMPILE_CCKPD_TYPE3
+	case 3:
+		phydm_set_cckpd_lv_type3(dm, lv);
+		break;
+	#endif
+	#ifdef PHYDM_COMPILE_CCKPD_TYPE4
+	case 4:
+		phydm_set_cck_pd_lv_type4(dm, lv);
+		break;
+	#endif
+	default:
+		pr_debug("[%s]warning\n", __func__);
+		break;
+	}
+}
+
+boolean
+phydm_stop_cck_pd_th(void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+
+	if (!(dm->support_ability & (ODM_BB_CCK_PD | ODM_BB_FA_CNT))) {
+		PHYDM_DBG(dm, DBG_CCKPD, "Not Support\n");
+		return true;
+	}
+
+	if (dm->pause_ability & ODM_BB_CCK_PD) {
+		PHYDM_DBG(dm, DBG_CCKPD, "Return: Pause CCKPD in LV=%d\n",
+			  dm->pause_lv_table.lv_cckpd);
+		return true;
+	}
+
+	if (dm->is_linked && (*dm->channel > 36)) {
+		PHYDM_DBG(dm, DBG_CCKPD, "Return: 5G CH=%d\n", *dm->channel);
+		return true;
+	}
+	return false;
+}
+
+void phydm_cck_pd_th(void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct phydm_fa_struct *fa_t = &dm->false_alm_cnt;
+	struct phydm_cckpd_struct *cckpd_t = &dm->dm_cckpd_table;
+	u32 cck_fa = fa_t->cnt_cck_fail;
+	#ifdef PHYDM_TDMA_DIG_SUPPORT
+	struct phydm_fa_acc_struct *fa_acc_t = &dm->false_alm_cnt_acc;
+	#endif
+
+	PHYDM_DBG(dm, DBG_CCKPD, "[%s] ======>\n", __func__);
+
+	if (phydm_stop_cck_pd_th(dm))
+		return;
+
+	#ifdef PHYDM_TDMA_DIG_SUPPORT
+	if (dm->original_dig_restore)
+		cck_fa = fa_t->cnt_cck_fail;
+	else
+		cck_fa = fa_acc_t->cnt_cck_fail_1sec;
+	#endif
+
+	if (cckpd_t->cck_fa_ma == CCK_FA_MA_RESET)
+		cckpd_t->cck_fa_ma = cck_fa;
+	else
+		cckpd_t->cck_fa_ma = (cckpd_t->cck_fa_ma * 3 + cck_fa) >> 2;
+
+	PHYDM_DBG(dm, DBG_CCKPD,
+		  "IGI=0x%x, rssi_min=%d, cck_fa=%d, cck_fa_ma=%d\n",
+		  dm->dm_dig_table.cur_ig_value, dm->rssi_min,
+		  cck_fa, cckpd_t->cck_fa_ma);
+
+	switch (cckpd_t->cckpd_hw_type) {
+	#ifdef PHYDM_COMPILE_CCKPD_TYPE1
+	case 1:
+		phydm_cckpd_type1(dm);
+		break;
+	#endif
+	#ifdef PHYDM_COMPILE_CCKPD_TYPE2
+	case 2:
+		phydm_cckpd_type2(dm);
+		break;
+	#endif
+	#ifdef PHYDM_COMPILE_CCKPD_TYPE3
+	case 3:
+		phydm_cckpd_type3(dm);
+		break;
+	#endif
+	#ifdef PHYDM_COMPILE_CCKPD_TYPE4
+	case 4:
+		phydm_cckpd_type4(dm);
+		break;
+	#endif
+	default:
+		pr_debug("[%s]warning\n", __func__);
+		break;
+	}
+}
+
+void phydm_cck_pd_init(void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct phydm_cckpd_struct *cckpd_t = &dm->dm_cckpd_table;
+
+	if (dm->support_ic_type & CCK_PD_IC_TYPE1)
+		cckpd_t->cckpd_hw_type = 1;
+	else if (dm->support_ic_type & CCK_PD_IC_TYPE2)
+		cckpd_t->cckpd_hw_type = 2;
+	else if (dm->support_ic_type & CCK_PD_IC_TYPE3)
+		cckpd_t->cckpd_hw_type = 3;
+	else if (dm->support_ic_type & CCK_PD_IC_TYPE4)
+		cckpd_t->cckpd_hw_type = 4;
+
+	PHYDM_DBG(dm, DBG_CCKPD, "[%s] cckpd_hw_type=%d\n",
+		  __func__, cckpd_t->cckpd_hw_type);
+
+	cckpd_t->cck_pd_lv = CCK_PD_LV_INIT;
+	cckpd_t->cck_n_rx = 0xff;
+	cckpd_t->cck_bw = CHANNEL_WIDTH_MAX;
+
+	switch (cckpd_t->cckpd_hw_type) {
+	#ifdef PHYDM_COMPILE_CCKPD_TYPE1
+	case 1:
+		phydm_set_cckpd_lv_type1(dm, CCK_PD_LV_0);
+		break;
+	#endif
+	#ifdef PHYDM_COMPILE_CCKPD_TYPE2
+	case 2:
+		cckpd_t->aaa_default = odm_read_1byte(dm, 0xaaa) & 0x1f;
+		phydm_set_cckpd_lv_type2(dm, CCK_PD_LV_0);
+		break;
+	#endif
+	#ifdef PHYDM_COMPILE_CCKPD_TYPE3
+	case 3:
+		phydm_cck_pd_init_type3(dm);
+		break;
+	#endif
+	#ifdef PHYDM_COMPILE_CCKPD_TYPE4
+	case 4:
+		phydm_cck_pd_init_type4(dm);
+		break;
+	#endif
+	default:
+		pr_debug("[%s]warning\n", __func__);
+		break;
+	}
+}
+#endif /*#ifdef PHYDM_SUPPORT_CCKPD*/
+
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/phydm_cck_pd.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/phydm_cck_pd.h
--- linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/phydm_cck_pd.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/phydm_cck_pd.h	2020-04-10 16:35:06.823660394 +0300
@@ -0,0 +1,154 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017  Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * The full GNU General Public License is included in this distribution in the
+ * file called LICENSE.
+ *
+ * Contact Information:
+ * wlanfae <wlanfae@realtek.com>
+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
+ * Hsinchu 300, Taiwan.
+ *
+ * Larry Finger <Larry.Finger@lwfinger.net>
+ *
+ *****************************************************************************/
+
+#ifndef __PHYDM_CCK_PD_H__
+#define __PHYDM_CCK_PD_H__
+
+#define CCK_PD_VERSION "3.0"
+
+/*@
+ * 1 ============================================================
+ * 1  Definition
+ * 1 ============================================================
+ */
+#define CCK_FA_MA_RESET 0xffffffff
+
+/*@Run time flag of CCK_PD HW type*/
+#define CCK_PD_IC_TYPE1 (ODM_RTL8188E | ODM_RTL8812 | ODM_RTL8821 |\
+			ODM_RTL8192E | ODM_RTL8723B | ODM_RTL8814A |\
+			ODM_RTL8881A | ODM_RTL8822B | ODM_RTL8703B |\
+			ODM_RTL8195A | ODM_RTL8188F)
+
+#define CCK_PD_IC_TYPE2 (ODM_RTL8197F | ODM_RTL8821C | ODM_RTL8723D |\
+			ODM_RTL8710B | ODM_RTL8195B) /*extend 0xaaa*/
+
+#define CCK_PD_IC_TYPE3 ODM_RTL8192F /*@extend for different bw & path*/
+
+#define CCK_PD_IC_TYPE4 ODM_IC_JGR3_SERIES /*@extend for different bw & path*/
+
+/*@Compile time flag of CCK_PD HW type*/
+#if (RTL8188E_SUPPORT || RTL8812A_SUPPORT || RTL8821A_SUPPORT ||\
+	RTL8192E_SUPPORT || RTL8723B_SUPPORT || RTL8814A_SUPPORT ||\
+	RTL8881A_SUPPORT || RTL8822B_SUPPORT || RTL8703B_SUPPORT ||\
+	RTL8195A_SUPPORT || RTL8188F_SUPPORT)
+	#define PHYDM_COMPILE_CCKPD_TYPE1 /*@only 0xa0a*/
+#endif
+
+#if (RTL8197F_SUPPORT || RTL8821C_SUPPORT || RTL8723D_SUPPORT ||\
+	RTL8710B_SUPPORT || RTL8195B_SUPPORT)
+	#define PHYDM_COMPILE_CCKPD_TYPE2 /*@extend 0xaaa*/
+#endif
+
+#if (RTL8192F_SUPPORT)
+	#define PHYDM_COMPILE_CCKPD_TYPE3 /*@extend for different & path*/
+#endif
+
+#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
+	#define PHYDM_COMPILE_CCKPD_TYPE4 /*@extend for different bw & path*/
+#endif
+/*@
+ * 1 ============================================================
+ * 1  enumeration
+ * 1 ============================================================
+ */
+enum cckpd_lv {
+	CCK_PD_LV_INIT = 0xff,
+	CCK_PD_LV_0 = 0,
+	CCK_PD_LV_1 = 1,
+	CCK_PD_LV_2 = 2,
+	CCK_PD_LV_3 = 3,
+	CCK_PD_LV_4 = 4,
+	CCK_PD_LV_MAX = 5
+};
+
+enum cckpd_mode {
+	CCK_BW20_1R = 0,
+	CCK_BW20_2R = 1,
+	CCK_BW20_3R = 2,
+	CCK_BW20_4R = 3,
+	CCK_BW40_1R = 4,
+	CCK_BW40_2R = 5,
+	CCK_BW40_3R = 6,
+	CCK_BW40_4R = 7
+};
+
+/*@
+ * 1 ============================================================
+ * 1  structure
+ * 1 ============================================================
+ */
+
+#ifdef PHYDM_SUPPORT_CCKPD
+struct phydm_cckpd_struct {
+	u8		cckpd_hw_type;
+	u8		cur_cck_cca_thres; /*@current cck_pd value 0xa0a*/
+	u32		cck_fa_ma;
+	u8		rvrt_val;
+	u8		pause_lv;
+	u8		cck_n_rx;
+	enum channel_width cck_bw;
+	enum cckpd_lv	cck_pd_lv;
+	#ifdef PHYDM_COMPILE_CCKPD_TYPE2
+	u8		cck_cca_th_aaa; /*@current cs_ratio value 0xaaa*/
+	u8		aaa_default;	/*@Init cs_ratio value - 0xaaa*/
+	#endif
+	#ifdef PHYDM_COMPILE_CCKPD_TYPE3
+	/*Default value*/
+	u8		cck_pd_20m_1r;
+	u8		cck_pd_20m_2r;
+	u8		cck_pd_40m_1r;
+	u8		cck_pd_40m_2r;
+	u8		cck_cs_ratio_20m_1r;
+	u8		cck_cs_ratio_20m_2r;
+	u8		cck_cs_ratio_40m_1r;
+	u8		cck_cs_ratio_40m_2r;
+	/*Current value*/
+	u8		cur_cck_pd_20m_1r;
+	u8		cur_cck_pd_20m_2r;
+	u8		cur_cck_pd_40m_1r;
+	u8		cur_cck_pd_40m_2r;
+	u8		cur_cck_cs_ratio_20m_1r;
+	u8		cur_cck_cs_ratio_20m_2r;
+	u8		cur_cck_cs_ratio_40m_1r;
+	u8		cur_cck_cs_ratio_40m_2r;
+	#endif
+	#ifdef PHYDM_COMPILE_CCKPD_TYPE4
+	/*@[bw][nrx][0:PD/1:CS][lv]*/
+	u8		cck_pd_table_jgr3[2][4][2][CCK_PD_LV_MAX];
+	#endif
+};
+#endif
+
+/*@
+ * 1 ============================================================
+ * 1  function prototype
+ * 1 ============================================================
+ */
+void phydm_set_cckpd_val(void *dm_void, u32 *val_buf, u8 val_len);
+
+void phydm_cck_pd_th(void *dm_void);
+
+void phydm_cck_pd_init(void *dm_void);
+#endif
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/phydm_ccx.c linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/phydm_ccx.c
--- linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/phydm_ccx.c	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/phydm_ccx.c	2020-04-10 16:35:06.824660441 +0300
@@ -0,0 +1,1839 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017  Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * The full GNU General Public License is included in this distribution in the
+ * file called LICENSE.
+ *
+ * Contact Information:
+ * wlanfae <wlanfae@realtek.com>
+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
+ * Hsinchu 300, Taiwan.
+ *
+ * Larry Finger <Larry.Finger@lwfinger.net>
+ *
+ *****************************************************************************/
+
+#include "mp_precomp.h"
+#include "phydm_precomp.h"
+
+void phydm_ccx_hw_restart(void *dm_void)
+			  /*@Will Restart NHM/CLM/FAHM simultaneously*/
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	u32 reg1 = 0;
+
+	if (dm->support_ic_type & ODM_IC_11AC_SERIES)
+		reg1 = R_0x994;
+	#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
+	else if (dm->support_ic_type & ODM_IC_JGR3_SERIES)
+		reg1 = R_0x1e60;
+	#endif
+	else
+		reg1 = R_0x890;
+
+	PHYDM_DBG(dm, DBG_ENV_MNTR, "[%s]===>\n", __func__);
+	odm_set_bb_reg(dm, reg1, 0x7, 0x0); /*@disable NHM,CLM, FAHM*/
+
+	if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
+		odm_set_bb_reg(dm, R_0x994, BIT(8), 0x0);
+		odm_set_bb_reg(dm, R_0x994, BIT(8), 0x1);
+	#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
+	} else if (dm->support_ic_type & ODM_IC_JGR3_SERIES) {
+		odm_set_bb_reg(dm, R_0x1e60, BIT(8), 0x0);
+		odm_set_bb_reg(dm, R_0x1e60, BIT(8), 0x1);
+	#endif
+	} else if (dm->support_ic_type & ODM_IC_11N_SERIES) {
+		odm_set_bb_reg(dm, R_0x890, BIT(8), 0x0);
+		odm_set_bb_reg(dm, R_0x890, BIT(8), 0x1);
+	}
+}
+
+#ifdef FAHM_SUPPORT
+
+u16 phydm_hw_divider(void *dm_void, u16 numerator, u16 denumerator)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	u16 result = DEVIDER_ERROR;
+	u32 tmp_u32 = ((numerator << 16) | denumerator);
+	u32 reg_devider_input;
+	u32 reg;
+	u8 i;
+
+	PHYDM_DBG(dm, DBG_ENV_MNTR, "[%s]===>\n", __func__);
+
+	if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
+		reg_devider_input = 0x1cbc;
+		reg = 0x1f98;
+	} else {
+		reg_devider_input = 0x980;
+		reg = 0x9f0;
+	}
+
+	odm_set_bb_reg(dm, reg_devider_input, MASKDWORD, tmp_u32);
+
+	for (i = 0; i < 10; i++) {
+		ODM_delay_ms(1);
+		if (odm_get_bb_reg(dm, reg, BIT(24))) {
+		/*@Chk HW rpt is ready*/
+
+			result = (u16)odm_get_bb_reg(dm, reg, MASKBYTE2);
+			break;
+		}
+	}
+	return result;
+}
+
+void phydm_fahm_trigger(void *dm_void, u16 tgr_period)
+{ /*@unit (4us)*/
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	u32 fahm_reg1;
+
+	if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
+		odm_set_bb_reg(dm, R_0x1cf8, 0xffff00, tgr_period);
+
+		fahm_reg1 = 0x994;
+	} else {
+		odm_set_bb_reg(dm, R_0x978, 0xff000000, (tgr_period & 0xff));
+		odm_set_bb_reg(dm, R_0x97c, 0xff, (tgr_period & 0xff00) >> 8);
+
+		fahm_reg1 = 0x890;
+	}
+
+	odm_set_bb_reg(dm, fahm_reg1, BIT(2), 0);
+	odm_set_bb_reg(dm, fahm_reg1, BIT(2), 1);
+}
+
+void phydm_fahm_set_valid_cnt(void *dm_void, u8 numerator_sel,
+			      u8 denominator_sel)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct ccx_info *ccx_info = &dm->dm_ccx_info;
+	u32 fahm_reg1;
+
+	PHYDM_DBG(dm, DBG_ENV_MNTR, "[%s]===>\n", __func__);
+
+	if (ccx_info->fahm_nume_sel == numerator_sel &&
+	    ccx_info->fahm_denom_sel == denominator_sel) {
+		PHYDM_DBG(dm, DBG_ENV_MNTR, "no need to update\n");
+		return;
+	}
+
+	ccx_info->fahm_nume_sel = numerator_sel;
+	ccx_info->fahm_denom_sel = denominator_sel;
+
+	if (dm->support_ic_type & ODM_IC_11AC_SERIES)
+		fahm_reg1 = 0x994;
+	else
+		fahm_reg1 = 0x890;
+
+	odm_set_bb_reg(dm, fahm_reg1, 0xe0, numerator_sel);
+	odm_set_bb_reg(dm, fahm_reg1, 0x7000, denominator_sel);
+}
+
+void phydm_fahm_get_result(void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	u16 fahm_cnt[12]; /*packet count*/
+	u16 fahm_rpt[12]; /*percentage*/
+	u16 denominator; /*@fahm_denominator packet count*/
+	u32 reg_rpt, reg_rpt_2;
+	u32 reg_tmp;
+	boolean is_ready = false;
+	u8 i;
+
+	PHYDM_DBG(dm, DBG_ENV_MNTR, "[%s]===>\n", __func__);
+
+	if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
+		reg_rpt = 0x1f80;
+		reg_rpt_2 = 0x1f98;
+	} else {
+		reg_rpt = 0x9d8;
+		reg_rpt_2 = 0x9f0;
+	}
+
+	for (i = 0; i < 3; i++) {
+		if (odm_get_bb_reg(dm, reg_rpt_2, BIT(31))) {
+		/*@Chk HW rpt is ready*/
+			is_ready = true;
+			break;
+		}
+		ODM_delay_ms(1);
+	}
+
+	if (!is_ready)
+		return;
+
+	/*@Get FAHM Denominator*/
+	denominator = (u16)odm_get_bb_reg(dm, reg_rpt_2, MASKLWORD);
+
+	PHYDM_DBG(dm, DBG_ENV_MNTR, "Reg[0x%x] fahm_denmrtr = %d\n", reg_rpt_2,
+		  denominator);
+
+	/*@Get FAHM nemerator*/
+	for (i = 0; i < 6; i++) {
+		reg_tmp = odm_get_bb_reg(dm, reg_rpt + (i << 2), MASKDWORD);
+
+		PHYDM_DBG(dm, DBG_ENV_MNTR, "Reg[0x%x] fahm_denmrtr = %d\n",
+			  reg_rpt + (i * 4), reg_tmp);
+
+		fahm_cnt[i * 2] = (u16)(reg_tmp & MASKLWORD);
+		fahm_cnt[i * 2 + 1] = (u16)((reg_tmp & MASKHWORD) >> 16);
+	}
+
+	for (i = 0; i < 12; i++)
+		fahm_rpt[i] = phydm_hw_divider(dm, fahm_cnt[i], denominator);
+
+	PHYDM_DBG(dm, DBG_ENV_MNTR,
+		  "FAHM_RPT_cnt[10:0]=[%d, %d, %d, %d, %d(IGI), %d, %d, %d, %d, %d, %d, %d]\n",
+		  fahm_cnt[11], fahm_cnt[10], fahm_cnt[9],
+		  fahm_cnt[8], fahm_cnt[7], fahm_cnt[6],
+		  fahm_cnt[5], fahm_cnt[4], fahm_cnt[3],
+		  fahm_cnt[2], fahm_cnt[1], fahm_cnt[0]);
+
+	PHYDM_DBG(dm, DBG_ENV_MNTR,
+		  "FAHM_RPT[10:0]=[%d, %d, %d, %d, %d(IGI), %d, %d, %d, %d, %d, %d, %d]\n",
+		  fahm_rpt[11], fahm_rpt[10], fahm_rpt[9], fahm_rpt[8],
+		  fahm_rpt[7], fahm_rpt[6], fahm_rpt[5], fahm_rpt[4],
+		  fahm_rpt[3], fahm_rpt[2], fahm_rpt[1], fahm_rpt[0]);
+}
+
+void phydm_fahm_set_th_by_igi(void *dm_void, u8 igi)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct ccx_info *ccx_info = &dm->dm_ccx_info;
+	u32 val = 0;
+	u8 f_th[11]; /*@FAHM Threshold*/
+	u8 rssi_th[11]; /*@in RSSI scale*/
+	u8 th_gap = 2 * IGI_TO_NHM_TH_MULTIPLIER; /*unit is 0.5dB for FAHM*/
+	u8 i;
+
+	PHYDM_DBG(dm, DBG_ENV_MNTR, "[%s]===>\n", __func__);
+
+	if (ccx_info->env_mntr_igi == igi) {
+		PHYDM_DBG(dm, DBG_ENV_MNTR,
+			  "No need to update FAHM_th, IGI=0x%x\n",
+			  ccx_info->env_mntr_igi);
+		return;
+	}
+
+	ccx_info->env_mntr_igi = igi; /*@bkp IGI*/
+
+	if (igi >= CCA_CAP)
+		f_th[0] = (igi - CCA_CAP) * IGI_TO_NHM_TH_MULTIPLIER;
+	else
+		f_th[0] = 0;
+
+	rssi_th[0] = igi - 10 - CCA_CAP;
+
+	for (i = 1; i <= 10; i++) {
+		f_th[i] = f_th[0] + th_gap * i;
+		rssi_th[i] = rssi_th[0] + (i << 1);
+	}
+
+	PHYDM_DBG(dm, DBG_ENV_MNTR,
+		  "FAHM_RSSI_th[10:0]=[%d, %d, %d, (IGI)%d, %d, %d, %d, %d, %d, %d, %d]\n",
+		  rssi_th[10], rssi_th[9], rssi_th[8], rssi_th[7], rssi_th[6],
+		  rssi_th[5], rssi_th[4], rssi_th[3], rssi_th[2], rssi_th[1],
+		  rssi_th[0]);
+
+	if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
+		val = BYTE_2_DWORD(0, f_th[2], f_th[1], f_th[0]);
+		odm_set_bb_reg(dm, R_0x1c38, 0xffffff00, val);
+		val = BYTE_2_DWORD(0, f_th[5], f_th[4], f_th[3]);
+		odm_set_bb_reg(dm, R_0x1c78, 0xffffff00, val);
+		val = BYTE_2_DWORD(0, 0, f_th[7], f_th[6]);
+		odm_set_bb_reg(dm, R_0x1c7c, 0xffff0000, val);
+		val = BYTE_2_DWORD(0, f_th[10], f_th[9], f_th[8]);
+		odm_set_bb_reg(dm, R_0x1cb8, 0xffffff00, val);
+	} else {
+		val = BYTE_2_DWORD(f_th[3], f_th[2], f_th[1], f_th[0]);
+		odm_set_bb_reg(dm, R_0x970, MASKDWORD, val);
+		val = BYTE_2_DWORD(f_th[7], f_th[6], f_th[5], f_th[4]);
+		odm_set_bb_reg(dm, R_0x974, MASKDWORD, val);
+		BYTE_2_DWORD(0, f_th[10], f_th[9], f_th[8]);
+		odm_set_bb_reg(dm, R_0x978, 0xffffff, val);
+	}
+}
+
+void phydm_fahm_init(void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct ccx_info *ccx_info = &dm->dm_ccx_info;
+	u32 fahm_reg1;
+	u8 denumerator_sel = 0;
+
+	PHYDM_DBG(dm, DBG_ENV_MNTR, "[%s]===>\n", __func__);
+	PHYDM_DBG(dm, DBG_ENV_MNTR, "IGI=0x%x\n",
+		  dm->dm_dig_table.cur_ig_value);
+
+	if (dm->support_ic_type & ODM_IC_11AC_SERIES)
+		fahm_reg1 = 0x994;
+	else
+		fahm_reg1 = 0x890;
+
+	ccx_info->fahm_period = 65535;
+
+	odm_set_bb_reg(dm, fahm_reg1, 0x6, 3); /*@FAHM HW block enable*/
+
+	denumerator_sel = FAHM_INCLD_FA | FAHM_INCLD_CRC_OK | FAHM_INCLD_CRC_ER;
+	phydm_fahm_set_valid_cnt(dm, FAHM_INCLD_FA, denumerator_sel);
+	phydm_fahm_set_th_by_igi(dm, dm->dm_dig_table.cur_ig_value);
+}
+
+void phydm_fahm_dbg(void *dm_void, char input[][16], u32 *_used, char *output,
+		    u32 *_out_len)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct ccx_info *ccx_info = &dm->dm_ccx_info;
+	char help[] = "-h";
+	u32 var1[10] = {0};
+	u32 used = *_used;
+	u32 out_len = *_out_len;
+	u32 i;
+
+	for (i = 0; i < 2; i++) {
+		if (input[i + 1])
+			PHYDM_SSCANF(input[i + 1], DCMD_DECIMAL, &var1[i]);
+	}
+
+	if ((strcmp(input[1], help) == 0)) {
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "{1: trigger, 2:get result}\n");
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "{3: MNTR mode sel} {1: driver, 2. FW}\n");
+		return;
+	} else if (var1[0] == 1) { /* Set & trigger CLM */
+
+		phydm_fahm_set_th_by_igi(dm, dm->dm_dig_table.cur_ig_value);
+		phydm_fahm_trigger(dm, ccx_info->fahm_period);
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "Monitor FAHM for %d * 4us\n", ccx_info->fahm_period);
+
+	} else if (var1[0] == 2) { /* @Get CLM results */
+
+		phydm_fahm_get_result(dm);
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "FAHM_result=%d us\n", (ccx_info->clm_result << 2));
+
+	} else {
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "Error\n");
+	}
+
+	*_used = used;
+	*_out_len = out_len;
+}
+
+#endif /*@#ifdef FAHM_SUPPORT*/
+
+#ifdef NHM_SUPPORT
+
+void phydm_nhm_racing_release(void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct ccx_info *ccx = &dm->dm_ccx_info;
+	u32 value32;
+
+	PHYDM_DBG(dm, DBG_ENV_MNTR, "[%s]===>\n", __func__);
+	PHYDM_DBG(dm, DBG_ENV_MNTR, "lv:(%d)->(0)\n", ccx->nhm_set_lv);
+
+	ccx->nhm_ongoing = false;
+	ccx->nhm_set_lv = NHM_RELEASE;
+
+	if (!(ccx->nhm_app == NHM_BACKGROUND || ccx->nhm_app == NHM_ACS)) {
+		phydm_pause_func(dm, F00_DIG, PHYDM_RESUME,
+				 PHYDM_PAUSE_LEVEL_1, 1, &value32);
+	}
+
+	ccx->nhm_app = NHM_BACKGROUND;
+}
+
+u8 phydm_nhm_racing_ctrl(void *dm_void, enum phydm_nhm_level nhm_lv)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct ccx_info *ccx = &dm->dm_ccx_info;
+	u8 set_result = PHYDM_SET_SUCCESS;
+	/*@acquire to control NHM API*/
+
+	PHYDM_DBG(dm, DBG_ENV_MNTR, "nhm_ongoing=%d, lv:(%d)->(%d)\n",
+		  ccx->nhm_ongoing, ccx->nhm_set_lv, nhm_lv);
+	if (ccx->nhm_ongoing) {
+		if (nhm_lv <= ccx->nhm_set_lv) {
+			set_result = PHYDM_SET_FAIL;
+		} else {
+			phydm_ccx_hw_restart(dm);
+			ccx->nhm_ongoing = false;
+		}
+	}
+
+	if (set_result)
+		ccx->nhm_set_lv = nhm_lv;
+
+	PHYDM_DBG(dm, DBG_ENV_MNTR, "nhm racing success=%d\n", set_result);
+	return set_result;
+}
+
+void phydm_nhm_trigger(void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct ccx_info *ccx = &dm->dm_ccx_info;
+	u32 nhm_reg1 = 0;
+
+	if (dm->support_ic_type & ODM_IC_11AC_SERIES)
+		nhm_reg1 = R_0x994;
+	#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
+	else if (dm->support_ic_type & ODM_IC_JGR3_SERIES)
+		nhm_reg1 = R_0x1e60;
+	#endif
+	else
+		nhm_reg1 = R_0x890;
+	PHYDM_DBG(dm, DBG_ENV_MNTR, "[%s]===>\n", __func__);
+
+	/*Trigger NHM*/
+	pdm_set_reg(dm, nhm_reg1, BIT(1), 0);
+	pdm_set_reg(dm, nhm_reg1, BIT(1), 1);
+	ccx->nhm_trigger_time = dm->phydm_sys_up_time;
+	ccx->nhm_rpt_stamp++;
+	ccx->nhm_ongoing = true;
+}
+
+boolean
+phydm_nhm_check_rdy(void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	boolean is_ready = false;
+	u32 reg1 = 0, reg1_bit = 0;
+#if (ENV_MNTR_DBG || ENV_MNTR_DBG_1)
+	u16 i = 0;
+	u64 start_time, progressing_time;
+	u32 reg_val_start = 0, reg_val = 0;
+	u8 print_rpt = 0;
+#endif
+
+	if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
+		reg1 = 0xfb4;
+		reg1_bit = 16;
+	#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
+	} else if (dm->support_ic_type & ODM_IC_JGR3_SERIES) {
+		reg1 = 0x2d4c;
+		reg1_bit = 16;
+	#endif
+	} else {
+		reg1 = 0x8b4;
+		if (dm->support_ic_type == ODM_RTL8710B) {
+			reg1_bit = 25;
+		} else {
+			reg1_bit = 17;
+		}
+	}
+#if (ENV_MNTR_DBG_1)
+	start_time = odm_get_current_time(dm);
+
+	if (dm->support_ic_type & (ODM_RTL8812 | ODM_RTL8821)) {
+		PHYDM_DBG(dm, DBG_ENV_MNTR, "NHM_period = %d\n",
+			  odm_get_bb_reg(dm, R_0x990, MASKDWORD));
+
+		 /*NHM trigger bit*/
+		reg_val_start = odm_get_bb_reg(dm, R_0x994, BIT(1));
+		PHYDM_DBG(dm, DBG_ENV_MNTR, "reg_val_start = %d\n",
+			  reg_val_start);
+
+		for (i = 0; i <= 400; i++) {
+			if (print_rpt == 0) {
+				reg_val = odm_get_bb_reg(dm, R_0x994, BIT(1));
+				if (reg_val != reg_val_start) {
+					print_rpt = 1;
+					PHYDM_DBG(dm, DBG_ENV_MNTR,
+						  "Trig[%d] (%d) -> (%d)\n",
+						  i, reg_val_start, reg_val);
+				}
+			}
+
+			if (odm_get_bb_reg(dm, reg1, BIT(reg1_bit))) {
+				is_ready = true;
+				break;
+			}
+			ODM_delay_ms(1);
+		}
+	} else {
+		if (odm_get_bb_reg(dm, reg1, BIT(reg1_bit)))
+			is_ready = true;
+	}
+
+	progressing_time = odm_get_progressing_time(dm, start_time);
+	PHYDM_DBG(dm, DBG_ENV_MNTR, "NHM rdy=%d, i=%d, NHM_polling_time=%lld\n",
+		  is_ready, i, progressing_time);
+
+#elif (ENV_MNTR_DBG)
+	start_time = odm_get_current_time(dm);
+	for (i = 0; i <= 400; i++) {
+		if (odm_get_bb_reg(dm, reg1, BIT(reg1_bit))) {
+			is_ready = true;
+			break;
+		}
+		ODM_delay_ms(1);
+	}
+	progressing_time = odm_get_progressing_time(dm, start_time);
+	PHYDM_DBG(dm, DBG_ENV_MNTR, "NHM rdy=%d, i=%d, NHM_polling_time=%lld\n",
+		  is_ready, i, progressing_time);
+#else
+	if (odm_get_bb_reg(dm, reg1, BIT(reg1_bit)))
+		is_ready = true;
+
+	PHYDM_DBG(dm, DBG_ENV_MNTR, "NHM rdy=%d\n", is_ready);
+
+#endif
+	return is_ready;
+}
+
+void phydm_nhm_get_utility(void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct ccx_info *ccx = &dm->dm_ccx_info;
+	u8 nhm_rpt_non_0 = 0;
+
+	if (ccx->nhm_rpt_sum >= ccx->nhm_result[0]) {
+		nhm_rpt_non_0 = ccx->nhm_rpt_sum - ccx->nhm_result[0];
+		ccx->nhm_ratio = (nhm_rpt_non_0 * 100) >> 8;
+	} else {
+		PHYDM_DBG(dm, DBG_ENV_MNTR, "[warning] nhm_rpt_sum invalid\n");
+		ccx->nhm_ratio = 0;
+	}
+
+	PHYDM_DBG(dm, DBG_ENV_MNTR, "nhm_ratio=%d\n", ccx->nhm_ratio);
+}
+
+boolean
+phydm_nhm_get_result(void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct ccx_info *ccx = &dm->dm_ccx_info;
+	u32 value32;
+	u8 i;
+	u32 nhm_reg1 = 0;
+	u16 nhm_rpt_sum_tmp = 0;
+
+	if (dm->support_ic_type & ODM_IC_11AC_SERIES)
+		nhm_reg1 = R_0x994;
+	#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
+	else if (dm->support_ic_type & ODM_IC_JGR3_SERIES)
+		nhm_reg1 = R_0x1e60;
+	#endif
+	else
+		nhm_reg1 = R_0x890;
+	PHYDM_DBG(dm, DBG_ENV_MNTR, "[%s]===>\n", __func__);
+	pdm_set_reg(dm, nhm_reg1, BIT(1), 0);
+
+#if (ENV_MNTR_DBG_2)
+	PHYDM_DBG(dm, DBG_ENV_MNTR,
+		  "[DBG][3] 0xc50=0x%x, 0x994=0x%x, 0x998=0x%x\n",
+		  odm_get_bb_reg(dm, 0xc50, MASKDWORD),
+		  odm_get_bb_reg(dm, 0x994, MASKDWORD),
+		  odm_get_bb_reg(dm, 0x998, MASKDWORD));
+#endif
+
+	if (!(phydm_nhm_check_rdy(dm))) {
+		PHYDM_DBG(dm, DBG_ENV_MNTR, "Get NHM report Fail\n");
+		phydm_nhm_racing_release(dm);
+		return false;
+	}
+
+	if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
+		value32 = odm_read_4byte(dm, 0xfa8);
+		odm_move_memory(dm, &ccx->nhm_result[0], &value32, 4);
+
+		value32 = odm_read_4byte(dm, 0xfac);
+		odm_move_memory(dm, &ccx->nhm_result[4], &value32, 4);
+
+		value32 = odm_read_4byte(dm, 0xfb0);
+		odm_move_memory(dm, &ccx->nhm_result[8], &value32, 4);
+
+		/*@Get NHM duration*/
+		value32 = odm_read_4byte(dm, 0xfb4);
+		ccx->nhm_duration = (u16)(value32 & MASKLWORD);
+	#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
+	} else if (dm->support_ic_type & ODM_IC_JGR3_SERIES) {
+		value32 = odm_read_4byte(dm, 0x2d40);
+		odm_move_memory(dm, &ccx->nhm_result[0], &value32, 4);
+
+		value32 = odm_read_4byte(dm, 0x2d44);
+		odm_move_memory(dm, &ccx->nhm_result[4], &value32, 4);
+
+		value32 = odm_read_4byte(dm, 0x2d48);
+		odm_move_memory(dm, &ccx->nhm_result[8], &value32, 4);
+
+		/*@Get NHM duration*/
+		value32 = odm_read_4byte(dm, 0x2d4c);
+		ccx->nhm_duration = (u16)(value32 & MASKLWORD);
+	#endif
+	} else {
+		value32 = odm_read_4byte(dm, 0x8d8);
+		odm_move_memory(dm, &ccx->nhm_result[0], &value32, 4);
+
+		value32 = odm_read_4byte(dm, 0x8dc);
+		odm_move_memory(dm, &ccx->nhm_result[4], &value32, 4);
+
+		value32 = odm_get_bb_reg(dm, R_0x8d0, 0xffff0000);
+		odm_move_memory(dm, &ccx->nhm_result[8], &value32, 2);
+
+		value32 = odm_read_4byte(dm, 0x8d4);
+
+		ccx->nhm_result[10] = (u8)((value32 & MASKBYTE2) >> 16);
+		ccx->nhm_result[11] = (u8)((value32 & MASKBYTE3) >> 24);
+
+		/*@Get NHM duration*/
+		ccx->nhm_duration = (u16)(value32 & MASKLWORD);
+	}
+
+	/* sum all nhm_result */
+	if (ccx->nhm_period >= 65530) {
+		value32 = (ccx->nhm_duration * 100) >> 16;
+		PHYDM_DBG(dm, DBG_ENV_MNTR,
+			  "NHM valid time = %d, valid: %d percent\n",
+			  ccx->nhm_duration, value32);
+	}
+
+	for (i = 0; i < NHM_RPT_NUM; i++)
+		nhm_rpt_sum_tmp += (u16)ccx->nhm_result[i];
+
+	ccx->nhm_rpt_sum = (u8)nhm_rpt_sum_tmp;
+
+	PHYDM_DBG(dm, DBG_ENV_MNTR,
+		  "NHM_Rpt[%d](H->L)[%d %d %d %d %d %d %d %d %d %d %d %d]\n",
+		  ccx->nhm_rpt_stamp, ccx->nhm_result[11], ccx->nhm_result[10],
+		  ccx->nhm_result[9], ccx->nhm_result[8], ccx->nhm_result[7],
+		  ccx->nhm_result[6], ccx->nhm_result[5], ccx->nhm_result[4],
+		  ccx->nhm_result[3], ccx->nhm_result[2], ccx->nhm_result[1],
+		  ccx->nhm_result[0]);
+
+	phydm_nhm_racing_release(dm);
+
+#if (ENV_MNTR_DBG_2)
+	PHYDM_DBG(dm, DBG_ENV_MNTR,
+		  "[DBG][4] 0xc50=0x%x, 0x994=0x%x, 0x998=0x%x\n",
+		  odm_get_bb_reg(dm, 0xc50, MASKDWORD),
+		  odm_get_bb_reg(dm, 0x994, MASKDWORD),
+		  odm_get_bb_reg(dm, 0x998, MASKDWORD));
+#endif
+
+	if (nhm_rpt_sum_tmp > 255) {
+		PHYDM_DBG(dm, DBG_ENV_MNTR,
+			  "[Warning] Invalid NHM RPT, total=%d\n",
+			  nhm_rpt_sum_tmp);
+		return false;
+	}
+
+	return true;
+}
+
+void phydm_nhm_set_th_reg(void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct ccx_info *ccx = &dm->dm_ccx_info;
+	u32 reg1 = 0, reg2 = 0, reg3 = 0, reg4 = 0, reg4_bit = 0;
+	u32 val = 0;
+
+	PHYDM_DBG(dm, DBG_ENV_MNTR, "[%s]===>\n", __func__);
+
+	if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
+		reg1 = 0x994;
+		reg2 = 0x998;
+		reg3 = 0x99c;
+		reg4 = 0x9a0;
+		reg4_bit = MASKBYTE0;
+	#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
+	} else if (dm->support_ic_type & ODM_IC_JGR3_SERIES) {
+		reg1 = 0x1e60;
+		reg2 = 0x1e44;
+		reg3 = 0x1e48;
+		reg4 = 0x1e5c;
+		reg4_bit = MASKBYTE2;
+	#endif
+	} else {
+		reg1 = 0x890;
+		reg2 = 0x898;
+		reg3 = 0x89c;
+		reg4 = 0xe28;
+		reg4_bit = MASKBYTE0;
+	}
+
+	/*Set NHM threshold*/ /*Unit: PWdB U(8,1)*/
+	val = BYTE_2_DWORD(ccx->nhm_th[3], ccx->nhm_th[2],
+			   ccx->nhm_th[1], ccx->nhm_th[0]);
+	pdm_set_reg(dm, reg2, MASKDWORD, val);
+	val = BYTE_2_DWORD(ccx->nhm_th[7], ccx->nhm_th[6],
+			   ccx->nhm_th[5], ccx->nhm_th[4]);
+	pdm_set_reg(dm, reg3, MASKDWORD, val);
+	pdm_set_reg(dm, reg4, reg4_bit, ccx->nhm_th[8]);
+	val = BYTE_2_DWORD(0, 0, ccx->nhm_th[10], ccx->nhm_th[9]);
+	pdm_set_reg(dm, reg1, 0xffff0000, val);
+
+	PHYDM_DBG(dm, DBG_ENV_MNTR,
+		  "Update NHM_th[H->L]=[%d %d %d %d %d %d %d %d %d %d %d]\n",
+		  ccx->nhm_th[10], ccx->nhm_th[9], ccx->nhm_th[8],
+		  ccx->nhm_th[7], ccx->nhm_th[6], ccx->nhm_th[5],
+		  ccx->nhm_th[4], ccx->nhm_th[3], ccx->nhm_th[2],
+		  ccx->nhm_th[1], ccx->nhm_th[0]);
+}
+
+boolean
+phydm_nhm_th_update_chk(void *dm_void, enum nhm_application nhm_app, u8 *nhm_th,
+			u32 *igi_new)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct ccx_info *ccx = &dm->dm_ccx_info;
+	boolean is_update = false;
+	u8 igi_curr = phydm_get_igi(dm, BB_PATH_A);
+	u8 nhm_igi_th_11k_low[NHM_TH_NUM] = {0x12, 0x15, 0x18, 0x1b, 0x1e,
+					     0x23, 0x28, 0x2c, 0x78,
+					     0x78, 0x78};
+	u8 nhm_igi_th_11k_high[NHM_TH_NUM] = {0x1e, 0x23, 0x28, 0x2d, 0x32,
+					      0x37, 0x78, 0x78, 0x78, 0x78,
+					      0x78};
+	u8 nhm_igi_th_xbox[NHM_TH_NUM] = {0x1a, 0x2c, 0x2e, 0x30, 0x32, 0x34,
+					  0x36, 0x38, 0x3a, 0x3c, 0x3d};
+	u8 i;
+
+	PHYDM_DBG(dm, DBG_ENV_MNTR, "[%s]===>\n", __func__);
+	PHYDM_DBG(dm, DBG_ENV_MNTR, "App=%d, nhm_igi=0x%x, igi_curr=0x%x\n",
+		  nhm_app, ccx->nhm_igi, igi_curr);
+
+	if (igi_curr < 0x10) /* Protect for invalid IGI*/
+		return false;
+
+	switch (nhm_app) {
+	case NHM_BACKGROUND: /*@Get IGI form driver parameter(cur_ig_value)*/
+	case NHM_ACS:
+		if (ccx->nhm_igi != igi_curr || ccx->nhm_app != nhm_app) {
+			is_update = true;
+			*igi_new = (u32)igi_curr;
+			nhm_th[0] = (u8)IGI_2_NHM_TH(igi_curr - CCA_CAP);
+			for (i = 1; i <= 10; i++)
+				nhm_th[i] = nhm_th[0] + IGI_2_NHM_TH(2 * i);
+		}
+		break;
+
+	case IEEE_11K_HIGH:
+		is_update = true;
+		*igi_new = 0x2c;
+		for (i = 0; i < NHM_TH_NUM; i++)
+			nhm_th[i] = IGI_2_NHM_TH(nhm_igi_th_11k_high[i]);
+		break;
+
+	case IEEE_11K_LOW:
+		is_update = true;
+		*igi_new = 0x20;
+		for (i = 0; i < NHM_TH_NUM; i++)
+			nhm_th[i] = IGI_2_NHM_TH(nhm_igi_th_11k_low[i]);
+		break;
+
+	case INTEL_XBOX:
+		is_update = true;
+		*igi_new = 0x36;
+		for (i = 0; i < NHM_TH_NUM; i++)
+			nhm_th[i] = IGI_2_NHM_TH(nhm_igi_th_xbox[i]);
+		break;
+
+	case NHM_DBG: /*@Get IGI form register*/
+		igi_curr = phydm_get_igi(dm, BB_PATH_A);
+		if (ccx->nhm_igi != igi_curr || ccx->nhm_app != nhm_app) {
+			is_update = true;
+			*igi_new = (u32)igi_curr;
+			nhm_th[0] = (u8)IGI_2_NHM_TH(igi_curr - CCA_CAP);
+			for (i = 1; i <= 10; i++)
+				nhm_th[i] = nhm_th[0] + IGI_2_NHM_TH(2 * i);
+		}
+		break;
+	}
+
+	if (is_update) {
+		PHYDM_DBG(dm, DBG_ENV_MNTR, "[Update NHM_TH] igi_RSSI=%d\n",
+			  IGI_2_RSSI(*igi_new));
+
+		for (i = 0; i < NHM_TH_NUM; i++) {
+			PHYDM_DBG(dm, DBG_ENV_MNTR, "NHM_th[%d](RSSI) = %d\n",
+				  i, NTH_TH_2_RSSI(nhm_th[i]));
+		}
+	} else {
+		PHYDM_DBG(dm, DBG_ENV_MNTR, "No need to update NHM_TH\n");
+	}
+	return is_update;
+}
+
+void phydm_nhm_set(void *dm_void, enum nhm_option_txon_all include_tx,
+		   enum nhm_option_cca_all include_cca,
+		   enum nhm_divider_opt_all divi_opt,
+		   enum nhm_application nhm_app, u16 period)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct ccx_info *ccx = &dm->dm_ccx_info;
+	u8 nhm_th[NHM_TH_NUM] = {0};
+	u32 igi = 0x20;
+	u32 reg1 = 0, reg2 = 0;
+	u32 val_tmp = 0;
+
+	PHYDM_DBG(dm, DBG_ENV_MNTR, "[%s]===>\n", __func__);
+
+	PHYDM_DBG(dm, DBG_ENV_MNTR,
+		  "incld{tx, cca}={%d, %d}, divi_opt=%d, period=%d\n",
+		  include_tx, include_cca, divi_opt, period);
+
+	if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
+		reg1 = 0x994;
+		reg2 = 0x990;
+	#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
+	} else if (dm->support_ic_type & ODM_IC_JGR3_SERIES) {
+		reg1 = 0x1e60;
+		reg2 = 0x1e40;
+	#endif
+	} else {
+		reg1 = 0x890;
+		reg2 = 0x894;
+	}
+
+	/*Set disable_ignore_cca, disable_ignore_txon, ccx_en*/
+	if (include_tx != ccx->nhm_include_txon ||
+	    include_cca != ccx->nhm_include_cca ||
+	    divi_opt != ccx->nhm_divider_opt) {
+	    /* some old ic is not supported on NHM divider option */
+		if (dm->support_ic_type & (ODM_RTL8188E | ODM_RTL8723B |
+		    ODM_RTL8195A | ODM_RTL8192E)) {
+			val_tmp = (u32)((include_tx << 2) |
+				  (include_cca << 1) | 1);
+			pdm_set_reg(dm, reg1, 0x700, val_tmp);
+		} else {
+			val_tmp = (u32)BIT_2_BYTE(divi_opt, include_tx,
+				  include_cca, 1);
+			pdm_set_reg(dm, reg1, 0xf00, val_tmp);
+		}
+		ccx->nhm_include_txon = include_tx;
+		ccx->nhm_include_cca = include_cca;
+		ccx->nhm_divider_opt = divi_opt;
+		#if 0
+		PHYDM_DBG(dm, DBG_ENV_MNTR,
+			  "val_tmp=%d, incld{tx, cca}={%d, %d}, divi_opt=%d, period=%d\n",
+			  val_tmp, include_tx, include_cca, divi_opt, period);
+
+		PHYDM_DBG(dm, DBG_ENV_MNTR, "0x994=0x%x\n",
+			  odm_get_bb_reg(dm, 0x994, 0xf00));
+		#endif
+	}
+
+	/*Set NHM period*/
+	if (period != ccx->nhm_period) {
+		pdm_set_reg(dm, reg2, MASKHWORD, period);
+		PHYDM_DBG(dm, DBG_ENV_MNTR,
+			  "Update NHM period ((%d)) -> ((%d))\n",
+			  ccx->nhm_period, period);
+
+		ccx->nhm_period = period;
+	}
+
+	/*Set NHM threshold*/
+	if (phydm_nhm_th_update_chk(dm, nhm_app, &(nhm_th[0]), &igi)) {
+		/*Pause IGI*/
+		if (nhm_app == NHM_BACKGROUND || nhm_app == NHM_ACS) {
+			PHYDM_DBG(dm, DBG_ENV_MNTR, "DIG Free Run\n");
+		} else if (phydm_pause_func(dm, F00_DIG, PHYDM_PAUSE,
+					    PHYDM_PAUSE_LEVEL_1, 1, &igi)
+					    == PAUSE_FAIL) {
+			PHYDM_DBG(dm, DBG_ENV_MNTR, "pause DIG Fail\n");
+			return;
+		} else {
+			PHYDM_DBG(dm, DBG_ENV_MNTR, "pause DIG=0x%x\n", igi);
+		}
+		ccx->nhm_app = nhm_app;
+		ccx->nhm_igi = (u8)igi;
+		odm_move_memory(dm, &ccx->nhm_th[0], &nhm_th, NHM_TH_NUM);
+
+		/*Set NHM th*/
+		phydm_nhm_set_th_reg(dm);
+	}
+}
+
+u8 phydm_nhm_mntr_set(void *dm_void, struct nhm_para_info *nhm_para)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	u16 nhm_time = 0; /*unit: 4us*/
+
+	PHYDM_DBG(dm, DBG_ENV_MNTR, "[%s]===>\n", __func__);
+
+	if (nhm_para->mntr_time == 0)
+		return PHYDM_SET_FAIL;
+
+	if (nhm_para->nhm_lv >= NHM_MAX_NUM) {
+		PHYDM_DBG(dm, DBG_ENV_MNTR, "Wrong LV=%d\n", nhm_para->nhm_lv);
+		return PHYDM_SET_FAIL;
+	}
+
+	if (phydm_nhm_racing_ctrl(dm, nhm_para->nhm_lv) == PHYDM_SET_FAIL)
+		return PHYDM_SET_FAIL;
+
+	if (nhm_para->mntr_time >= 262)
+		nhm_time = NHM_PERIOD_MAX;
+	else
+		nhm_time = nhm_para->mntr_time * MS_TO_4US_RATIO;
+
+	phydm_nhm_set(dm, nhm_para->incld_txon, nhm_para->incld_cca,
+		      nhm_para->div_opt, nhm_para->nhm_app, nhm_time);
+
+	return PHYDM_SET_SUCCESS;
+}
+
+/*@Environment Monitor*/
+boolean
+phydm_nhm_mntr_chk(void *dm_void, u16 monitor_time /*unit ms*/)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct ccx_info *ccx = &dm->dm_ccx_info;
+	struct nhm_para_info nhm_para = {0};
+	boolean nhm_chk_result = false;
+	u32 sys_return_time;
+
+	PHYDM_DBG(dm, DBG_ENV_MNTR, "[%s]===>\n", __func__);
+
+	if (ccx->nhm_manual_ctrl) {
+		PHYDM_DBG(dm, DBG_ENV_MNTR, "NHM in manual ctrl\n");
+		return nhm_chk_result;
+	}
+	sys_return_time = ccx->nhm_trigger_time + MAX_ENV_MNTR_TIME;
+	if (ccx->nhm_app != NHM_BACKGROUND &&
+	    (sys_return_time > dm->phydm_sys_up_time)) {
+		PHYDM_DBG(dm, DBG_ENV_MNTR,
+			  "nhm_app=%d, trigger_time %d, sys_time=%d\n",
+			  ccx->nhm_app, ccx->nhm_trigger_time,
+			  dm->phydm_sys_up_time);
+
+		return nhm_chk_result;
+	}
+
+	/*@[NHM get result & calculate Utility----------------------------*/
+	if (phydm_nhm_get_result(dm)) {
+		PHYDM_DBG(dm, DBG_ENV_MNTR, "Get NHM_rpt success\n");
+		phydm_nhm_get_utility(dm);
+	}
+
+	/*@[NHM trigger]-------------------------------------------------*/
+	nhm_para.incld_txon = NHM_EXCLUDE_TXON;
+	nhm_para.incld_cca = NHM_EXCLUDE_CCA;
+	nhm_para.div_opt = NHM_CNT_ALL;
+	nhm_para.nhm_app = NHM_BACKGROUND;
+	nhm_para.nhm_lv = NHM_LV_1;
+	nhm_para.mntr_time = monitor_time;
+
+	nhm_chk_result = phydm_nhm_mntr_set(dm, &nhm_para);
+
+	return nhm_chk_result;
+}
+
+void phydm_nhm_init(void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct ccx_info *ccx = &dm->dm_ccx_info;
+
+	PHYDM_DBG(dm, DBG_ENV_MNTR, "[%s]===>\n", __func__);
+	PHYDM_DBG(dm, DBG_ENV_MNTR, "cur_igi=0x%x\n",
+		  dm->dm_dig_table.cur_ig_value);
+
+	ccx->nhm_app = NHM_BACKGROUND;
+	ccx->nhm_igi = 0xff;
+
+	/*Set NHM threshold*/
+	ccx->nhm_ongoing = false;
+	ccx->nhm_set_lv = NHM_RELEASE;
+
+	if (phydm_nhm_th_update_chk(dm, ccx->nhm_app, &ccx->nhm_th[0],
+				    (u32 *)&ccx->nhm_igi))
+		phydm_nhm_set_th_reg(dm);
+
+	ccx->nhm_period = 0;
+
+	ccx->nhm_include_cca = NHM_CCA_INIT;
+	ccx->nhm_include_txon = NHM_TXON_INIT;
+	ccx->nhm_divider_opt = NHM_CNT_INIT;
+
+	ccx->nhm_manual_ctrl = 0;
+	ccx->nhm_rpt_stamp = 0;
+}
+
+void phydm_nhm_dbg(void *dm_void, char input[][16], u32 *_used, char *output,
+		   u32 *_out_len)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct ccx_info *ccx = &dm->dm_ccx_info;
+	struct nhm_para_info nhm_para;
+	char help[] = "-h";
+	u32 var1[10] = {0};
+	u32 used = *_used;
+	u32 out_len = *_out_len;
+	boolean nhm_rpt_success = true;
+	u8 result_tmp = 0;
+	u8 i;
+
+	PHYDM_SSCANF(input[1], DCMD_DECIMAL, &var1[0]);
+
+	if ((strcmp(input[1], help) == 0)) {
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "NHM Basic-Trigger 262ms: {1}\n");
+		/* some old ic is not supported on NHM divider option */
+		if (dm->support_ic_type & (ODM_RTL8188E | ODM_RTL8723B |
+		    ODM_RTL8195A | ODM_RTL8192E)) {
+			PDM_SNPF(out_len, used, output + used, out_len - used,
+				 "NHM Adv-Trigger: {2} {Include TXON} {Include CCA}\n{App} {LV} {0~262ms}\n");
+		} else {
+			PDM_SNPF(out_len, used, output + used, out_len - used,
+				 "NHM Adv-Trigger: {2} {Include TXON} {Include CCA}\n{0:Cnt_all, 1:Cnt valid} {App} {LV} {0~262ms}\n");
+		}
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "NHM Get Result: {100}\n");
+	} else if (var1[0] == 100) { /*@Get NHM results*/
+
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "IGI=0x%x, rpt_stamp=%d\n", ccx->nhm_igi,
+			 ccx->nhm_rpt_stamp);
+
+		nhm_rpt_success = phydm_nhm_get_result(dm);
+
+		if (nhm_rpt_success) {
+			for (i = 0; i <= 11; i++) {
+				result_tmp = ccx->nhm_result[i];
+				PDM_SNPF(out_len, used, output + used,
+					 out_len - used,
+					 "nhm_rpt[%d] = %d (%d percent)\n",
+					 i, result_tmp,
+					 (((result_tmp * 100) + 128) >> 8));
+			}
+		} else {
+			PDM_SNPF(out_len, used, output + used, out_len - used,
+				 "Get NHM_rpt Fail\n");
+		}
+		ccx->nhm_manual_ctrl = 0;
+
+	} else { /*NMH trigger*/
+
+		ccx->nhm_manual_ctrl = 1;
+		/* some old ic is not supported on NHM divider option */
+		if (dm->support_ic_type & (ODM_RTL8188E | ODM_RTL8723B |
+		    ODM_RTL8195A | ODM_RTL8192E)) {
+			for (i = 1; i < 6; i++) {
+				if (input[i + 1]) {
+					PHYDM_SSCANF(input[i + 1], DCMD_DECIMAL,
+						     &var1[i]);
+				}
+			}
+		} else {
+			for (i = 1; i < 7; i++) {
+				if (input[i + 1]) {
+					PHYDM_SSCANF(input[i + 1], DCMD_DECIMAL,
+						     &var1[i]);
+				}
+			}
+		}
+
+		if (var1[0] == 1) {
+			nhm_para.incld_txon = NHM_EXCLUDE_TXON;
+			nhm_para.incld_cca = NHM_EXCLUDE_CCA;
+			nhm_para.div_opt = NHM_CNT_ALL;
+			nhm_para.nhm_app = NHM_DBG;
+			nhm_para.nhm_lv = NHM_LV_4;
+			nhm_para.mntr_time = 262;
+		} else {
+			nhm_para.incld_txon = (enum nhm_option_txon_all)var1[1];
+			nhm_para.incld_cca = (enum nhm_option_cca_all)var1[2];
+			/* some old ic is not supported on NHM divider option */
+			if (dm->support_ic_type & (ODM_RTL8188E | ODM_RTL8723B |
+			    ODM_RTL8195A | ODM_RTL8192E)) {
+				nhm_para.nhm_app = (enum nhm_application)
+						   var1[3];
+				nhm_para.nhm_lv = (enum phydm_nhm_level)var1[4];
+				nhm_para.mntr_time = (u16)var1[5];
+			} else {
+				nhm_para.div_opt = (enum nhm_divider_opt_all)
+						   var1[3];
+				nhm_para.nhm_app = (enum nhm_application)
+						   var1[4];
+				nhm_para.nhm_lv = (enum phydm_nhm_level)var1[5];
+				nhm_para.mntr_time = (u16)var1[6];
+			}
+		}
+		/* some old ic is not supported on NHM divider option */
+		if (dm->support_ic_type & (ODM_RTL8188E | ODM_RTL8723B |
+		    ODM_RTL8195A | ODM_RTL8192E)) {
+			PDM_SNPF(out_len, used, output + used, out_len - used,
+				 "txon=%d, cca=%d, app=%d, lv=%d, time=%d ms\n",
+				 nhm_para.incld_txon, nhm_para.incld_cca,
+				 nhm_para.nhm_app, nhm_para.nhm_lv,
+				 nhm_para.mntr_time);
+		} else {
+			PDM_SNPF(out_len, used, output + used, out_len - used,
+				 "txon=%d, cca=%d, dev=%d, app=%d, lv=%d, time=%d ms\n",
+				 nhm_para.incld_txon, nhm_para.incld_cca,
+				 nhm_para.div_opt, nhm_para.nhm_app,
+				 nhm_para.nhm_lv, nhm_para.mntr_time);
+		}
+		if (phydm_nhm_mntr_set(dm, &nhm_para) == PHYDM_SET_SUCCESS)
+			phydm_nhm_trigger(dm);
+
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "IGI=0x%x, rpt_stamp=%d\n", ccx->nhm_igi,
+			 ccx->nhm_rpt_stamp);
+
+		for (i = 0; i <= 10; i++) {
+			PDM_SNPF(out_len, used, output + used, out_len - used,
+				 "NHM_th[%d] RSSI = %d\n", i,
+				 NTH_TH_2_RSSI(ccx->nhm_th[i]));
+		}
+	}
+
+	*_used = used;
+	*_out_len = out_len;
+}
+#endif /*@#ifdef NHM_SUPPORT*/
+
+#ifdef CLM_SUPPORT
+
+void phydm_clm_racing_release(void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct ccx_info *ccx = &dm->dm_ccx_info;
+
+	PHYDM_DBG(dm, DBG_ENV_MNTR, "[%s]===>\n", __func__);
+	PHYDM_DBG(dm, DBG_ENV_MNTR, "lv:(%d)->(0)\n", ccx->clm_set_lv);
+
+	ccx->clm_ongoing = false;
+	ccx->clm_set_lv = CLM_RELEASE;
+	ccx->clm_app = CLM_BACKGROUND;
+}
+
+u8 phydm_clm_racing_ctrl(void *dm_void, enum phydm_nhm_level clm_lv)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct ccx_info *ccx = &dm->dm_ccx_info;
+	u8 set_result = PHYDM_SET_SUCCESS;
+	/*@acquire to control CLM API*/
+
+	PHYDM_DBG(dm, DBG_ENV_MNTR, "clm_ongoing=%d, lv:(%d)->(%d)\n",
+		  ccx->clm_ongoing, ccx->clm_set_lv, clm_lv);
+	if (ccx->clm_ongoing) {
+		if (clm_lv <= ccx->clm_set_lv) {
+			set_result = PHYDM_SET_FAIL;
+		} else {
+			phydm_ccx_hw_restart(dm);
+			ccx->clm_ongoing = false;
+		}
+	}
+
+	if (set_result)
+		ccx->clm_set_lv = clm_lv;
+
+	PHYDM_DBG(dm, DBG_ENV_MNTR, "clm racing success=%d\n", set_result);
+	return set_result;
+}
+
+void phydm_clm_c2h_report_handler(void *dm_void, u8 *cmd_buf, u8 cmd_len)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct ccx_info *ccx_info = &dm->dm_ccx_info;
+	u8 clm_report = cmd_buf[0];
+	/*@u8 clm_report_idx = cmd_buf[1];*/
+
+	if (cmd_len >= 12)
+		return;
+
+	ccx_info->clm_fw_result_acc += clm_report;
+	ccx_info->clm_fw_result_cnt++;
+
+	PHYDM_DBG(dm, DBG_ENV_MNTR, "[%d] clm_report= %d\n",
+		  ccx_info->clm_fw_result_cnt, clm_report);
+}
+
+void phydm_clm_h2c(void *dm_void, u16 obs_time, u8 fw_clm_en)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	u8 h2c_val[H2C_MAX_LENGTH] = {0};
+	u8 i = 0;
+	u8 obs_time_idx = 0;
+
+	PHYDM_DBG(dm, DBG_ENV_MNTR, "[%s] ======>\n", __func__);
+	PHYDM_DBG(dm, DBG_ENV_MNTR, "obs_time_index=%d *4 us\n", obs_time);
+
+	for (i = 1; i <= 16; i++) {
+		if (obs_time & BIT(16 - i)) {
+			obs_time_idx = 16 - i;
+			break;
+		}
+	}
+#if 0
+	obs_time = (2 ^ 16 - 1)~(2 ^ 15)  => obs_time_idx = 15  (65535 ~32768)
+	obs_time = (2 ^ 15 - 1)~(2 ^ 14)  => obs_time_idx = 14
+	...
+	...
+	...
+	obs_time = (2 ^ 1 - 1)~(2 ^ 0)  => obs_time_idx = 0
+
+#endif
+
+	h2c_val[0] = obs_time_idx | (((fw_clm_en) ? 1 : 0) << 7);
+	h2c_val[1] = CLM_MAX_REPORT_TIME;
+
+	PHYDM_DBG(dm, DBG_ENV_MNTR, "PHYDM h2c[0x4d]=0x%x %x %x %x %x %x %x\n",
+		  h2c_val[6], h2c_val[5], h2c_val[4], h2c_val[3], h2c_val[2],
+		  h2c_val[1], h2c_val[0]);
+
+	odm_fill_h2c_cmd(dm, PHYDM_H2C_FW_CLM_MNTR, H2C_MAX_LENGTH, h2c_val);
+}
+
+void phydm_clm_setting(void *dm_void, u16 clm_period /*@4us sample 1 time*/)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct ccx_info *ccx = &dm->dm_ccx_info;
+
+	if (ccx->clm_period != clm_period) {
+		if (dm->support_ic_type & ODM_IC_11AC_SERIES)
+			odm_set_bb_reg(dm, R_0x990, MASKLWORD, clm_period);
+		#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
+		else if (dm->support_ic_type & ODM_IC_JGR3_SERIES)
+			odm_set_bb_reg(dm, R_0x1e40, MASKLWORD, clm_period);
+		#endif
+		else if (dm->support_ic_type & ODM_IC_11N_SERIES)
+			odm_set_bb_reg(dm, R_0x894, MASKLWORD, clm_period);
+
+		ccx->clm_period = clm_period;
+		PHYDM_DBG(dm, DBG_ENV_MNTR,
+			  "Update CLM period ((%d)) -> ((%d))\n",
+			  ccx->clm_period, clm_period);
+	}
+
+	PHYDM_DBG(dm, DBG_ENV_MNTR, "Set CLM period=%d * 4us\n",
+		  ccx->clm_period);
+}
+
+void phydm_clm_trigger(void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct ccx_info *ccx = &dm->dm_ccx_info;
+	u32 reg1 = 0;
+
+	if (dm->support_ic_type & ODM_IC_11AC_SERIES)
+		reg1 = R_0x994;
+	#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
+	else if (dm->support_ic_type & ODM_IC_JGR3_SERIES)
+		reg1 = R_0x1e60;
+	#endif
+	else
+		reg1 = R_0x890;
+	PHYDM_DBG(dm, DBG_ENV_MNTR, "[%s]===>\n", __func__);
+
+	odm_set_bb_reg(dm, reg1, BIT(0), 0x0);
+	odm_set_bb_reg(dm, reg1, BIT(0), 0x1);
+
+	ccx->clm_trigger_time = dm->phydm_sys_up_time;
+	ccx->clm_rpt_stamp++;
+	ccx->clm_ongoing = true;
+}
+
+boolean
+phydm_clm_check_rdy(void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	boolean is_ready = false;
+	u32 reg1 = 0, reg1_bit = 0;
+#if (ENV_MNTR_DBG)
+	u16 i;
+	u64 start_time, progressing_time;
+#endif
+
+	if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
+		reg1 = ODM_REG_CLM_RESULT_11AC;
+		reg1_bit = 16;
+	#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
+	} else if (dm->support_ic_type & ODM_IC_JGR3_SERIES) {
+		reg1 = R_0x2d88;
+		reg1_bit = 16;
+	#endif
+	} else if (dm->support_ic_type & ODM_IC_11N_SERIES) {
+		if (dm->support_ic_type == ODM_RTL8710B) {
+			reg1 = R_0x8b4;
+			reg1_bit = 24;
+		} else {
+			reg1 = R_0x8b4;
+			reg1_bit = 16;
+		}
+	}
+#if (ENV_MNTR_DBG)
+	start_time = odm_get_current_time(dm);
+	for (i = 0; i <= 400; i++) {
+		if (odm_get_bb_reg(dm, reg1, BIT(reg1_bit))) {
+			is_ready = true;
+			break;
+		}
+		ODM_delay_ms(1);
+	}
+	progressing_time = odm_get_progressing_time(dm, start_time);
+
+	PHYDM_DBG(dm, DBG_ENV_MNTR, "CLM rdy=%d, i=%d, CLM_polling_time=%lld\n",
+		  is_ready, i, progressing_time);
+#else
+	if (odm_get_bb_reg(dm, reg1, BIT(reg1_bit)))
+		is_ready = true;
+
+	PHYDM_DBG(dm, DBG_ENV_MNTR, "CLM rdy=%d\n", is_ready);
+#endif
+	return is_ready;
+}
+
+void phydm_clm_get_utility(void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct ccx_info *ccx = &dm->dm_ccx_info;
+	u32 clm_result_tmp;
+
+	if (ccx->clm_period == 0) {
+		PHYDM_DBG(dm, DBG_ENV_MNTR, "[warning] clm_period = 0\n");
+		ccx->clm_ratio = 0;
+	} else if (ccx->clm_period >= 65530) {
+		clm_result_tmp = (u32)(ccx->clm_result * 100);
+		ccx->clm_ratio = (u8)((clm_result_tmp + (1 << 15)) >> 16);
+	} else {
+		clm_result_tmp = (u32)(ccx->clm_result * 100);
+		ccx->clm_ratio = (u8)(clm_result_tmp / (u32)ccx->clm_period);
+	}
+}
+
+boolean
+phydm_clm_get_result(void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct ccx_info *ccx_info = &dm->dm_ccx_info;
+	u32 reg1 = 0;
+	u32 val = 0;
+
+	if (dm->support_ic_type & ODM_IC_11AC_SERIES)
+		reg1 = R_0x994;
+	#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
+	else if (dm->support_ic_type & ODM_IC_JGR3_SERIES)
+		reg1 = R_0x1e60;
+	#endif
+	else
+		reg1 = R_0x890;
+	odm_set_bb_reg(dm, reg1, BIT(0), 0x0);
+	if (phydm_clm_check_rdy(dm) == false) {
+		PHYDM_DBG(dm, DBG_ENV_MNTR, "Get CLM report Fail\n");
+		phydm_clm_racing_release(dm);
+		return false;
+	}
+
+	if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
+		val = odm_get_bb_reg(dm, R_0xfa4, MASKLWORD);
+		ccx_info->clm_result = (u16)val;
+	#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
+	} else if (dm->support_ic_type & ODM_IC_JGR3_SERIES) {
+		val = odm_get_bb_reg(dm, R_0x2d88, MASKLWORD);
+		ccx_info->clm_result = (u16)val;
+	#endif
+	} else if (dm->support_ic_type & ODM_IC_11N_SERIES) {
+		val = odm_get_bb_reg(dm, R_0x8d0, MASKLWORD);
+		ccx_info->clm_result = (u16)val;
+	}
+
+	PHYDM_DBG(dm, DBG_ENV_MNTR, "CLM result = %d *4 us\n",
+		  ccx_info->clm_result);
+	phydm_clm_racing_release(dm);
+	return true;
+}
+
+void phydm_clm_mntr_fw(void *dm_void, u16 monitor_time /*unit ms*/)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct ccx_info *ccx = &dm->dm_ccx_info;
+	u32 val = 0;
+
+	/*@[Get CLM report]*/
+	if (ccx->clm_fw_result_cnt != 0) {
+		val = ccx->clm_fw_result_acc / ccx->clm_fw_result_cnt;
+		ccx->clm_ratio = (u8)val;
+	} else {
+		ccx->clm_ratio = 0;
+	}
+
+	PHYDM_DBG(dm, DBG_ENV_MNTR,
+		  "clm_fw_result_acc=%d, clm_fw_result_cnt=%d\n",
+		  ccx->clm_fw_result_acc, ccx->clm_fw_result_cnt);
+
+	ccx->clm_fw_result_acc = 0;
+	ccx->clm_fw_result_cnt = 0;
+
+	/*@[CLM trigger]*/
+	if (monitor_time >= 262)
+		ccx->clm_period = 65535;
+	else
+		ccx->clm_period = monitor_time * MS_TO_4US_RATIO;
+
+	phydm_clm_h2c(dm, monitor_time, true);
+}
+
+u8 phydm_clm_mntr_set(void *dm_void, struct clm_para_info *clm_para)
+{
+	/*@Driver Monitor CLM*/
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct ccx_info *ccx = &dm->dm_ccx_info;
+	u16 clm_period = 0;
+
+	if (clm_para->mntr_time == 0)
+		return PHYDM_SET_FAIL;
+
+	if (clm_para->clm_lv >= CLM_MAX_NUM) {
+		PHYDM_DBG(dm, DBG_ENV_MNTR, "[WARNING] Wrong LV=%d\n",
+			  clm_para->clm_lv);
+		return PHYDM_SET_FAIL;
+	}
+
+	if (phydm_clm_racing_ctrl(dm, clm_para->clm_lv) == PHYDM_SET_FAIL)
+		return PHYDM_SET_FAIL;
+
+	if (clm_para->mntr_time >= 262)
+		clm_period = CLM_PERIOD_MAX;
+	else
+		clm_period = clm_para->mntr_time * MS_TO_4US_RATIO;
+
+	ccx->clm_app = clm_para->clm_app;
+	phydm_clm_setting(dm, clm_period);
+
+	return PHYDM_SET_SUCCESS;
+}
+
+boolean
+phydm_clm_mntr_chk(void *dm_void, u16 monitor_time /*unit ms*/)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct ccx_info *ccx = &dm->dm_ccx_info;
+	struct clm_para_info clm_para = {0};
+	boolean clm_chk_result = false;
+	u32 sys_return_time = 0;
+
+	PHYDM_DBG(dm, DBG_ENV_MNTR, "[%s] ======>\n", __func__);
+	if (ccx->clm_manual_ctrl) {
+		PHYDM_DBG(dm, DBG_ENV_MNTR, "CLM in manual ctrl\n");
+		return clm_chk_result;
+	}
+
+	sys_return_time = ccx->clm_trigger_time + MAX_ENV_MNTR_TIME;
+
+	if (ccx->clm_app != CLM_BACKGROUND &&
+	    sys_return_time > dm->phydm_sys_up_time) {
+		PHYDM_DBG(dm, DBG_ENV_MNTR, "trigger_time %d, sys_time=%d\n",
+			  ccx->clm_trigger_time, dm->phydm_sys_up_time);
+
+		return clm_chk_result;
+	}
+
+	clm_para.clm_app = CLM_BACKGROUND;
+	clm_para.clm_lv = CLM_LV_1;
+	clm_para.mntr_time = monitor_time;
+	if (ccx->clm_mntr_mode == CLM_DRIVER_MNTR) {
+		/*@[Get CLM report]*/
+		if (phydm_clm_get_result(dm)) {
+			PHYDM_DBG(dm, DBG_ENV_MNTR, "Get CLM_rpt success\n");
+			phydm_clm_get_utility(dm);
+		}
+
+		/*@[CLM trigger]----------------------------------------------*/
+		if (phydm_clm_mntr_set(dm, &clm_para) == PHYDM_SET_SUCCESS)
+			clm_chk_result = true;
+	} else {
+#if 0
+		/*PHYDM_DBG(dm, DBG_ENV_MNTR, "enter clm_mntr_fw!!");*/
+#endif
+		phydm_clm_mntr_fw(dm, monitor_time);
+	}
+
+	PHYDM_DBG(dm, DBG_ENV_MNTR, "clm_ratio=%d\n", ccx->clm_ratio);
+#if 0
+	/*PHYDM_DBG(dm, DBG_ENV_MNTR, "clm_chk_result=%d\n",clm_chk_result);*/
+#endif
+	return clm_chk_result;
+}
+
+void phydm_set_clm_mntr_mode(void *dm_void, enum clm_monitor_mode mode)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct ccx_info *ccx_info = &dm->dm_ccx_info;
+
+	if (ccx_info->clm_mntr_mode != mode) {
+		ccx_info->clm_mntr_mode = mode;
+		phydm_ccx_hw_restart(dm);
+
+		if (mode == CLM_DRIVER_MNTR)
+			phydm_clm_h2c(dm, 0, 0);
+	}
+}
+
+void phydm_clm_init(void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct ccx_info *ccx = &dm->dm_ccx_info;
+
+	PHYDM_DBG(dm, DBG_ENV_MNTR, "[%s]===>\n", __func__);
+	ccx->clm_ongoing = false;
+	ccx->clm_manual_ctrl = 0;
+	ccx->clm_mntr_mode = CLM_DRIVER_MNTR;
+	ccx->clm_period = 0;
+	ccx->clm_rpt_stamp = 0;
+	phydm_clm_setting(dm, 65535);
+}
+
+void phydm_clm_dbg(void *dm_void, char input[][16], u32 *_used, char *output,
+		   u32 *_out_len)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct ccx_info *ccx = &dm->dm_ccx_info;
+	char help[] = "-h";
+	u32 var1[10] = {0};
+	u32 used = *_used;
+	u32 out_len = *_out_len;
+	struct clm_para_info clm_para = {0};
+	u32 i;
+
+	for (i = 0; i < 4; i++) {
+		if (input[i + 1])
+			PHYDM_SSCANF(input[i + 1], DCMD_DECIMAL, &var1[i]);
+	}
+
+	if ((strcmp(input[1], help) == 0)) {
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "CLM Driver Basic-Trigger 262ms: {1}\n");
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "CLM Driver Adv-Trigger: {2} {app} {LV} {0~262ms}\n");
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "CLM FW Trigger: {3}\n");
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "CLM Get Result: {100}\n");
+	} else if (var1[0] == 100) { /* @Get CLM results */
+
+		if (phydm_clm_get_result(dm))
+			phydm_clm_get_utility(dm);
+
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "clm_rpt_stamp=%d\n", ccx->clm_rpt_stamp);
+
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "clm_ratio:((%d percent)) = (%d us/ %d us)\n",
+			 ccx->clm_ratio, ccx->clm_result << 2,
+			 ccx->clm_period << 2);
+
+		ccx->clm_manual_ctrl = 0;
+
+	} else { /* Set & trigger CLM */
+		ccx->clm_manual_ctrl = 1;
+
+		if (var1[0] == 1) {
+			clm_para.clm_app = CLM_BACKGROUND;
+			clm_para.clm_lv = CLM_LV_4;
+			clm_para.mntr_time = 262;
+			ccx->clm_mntr_mode = CLM_DRIVER_MNTR;
+
+		} else if (var1[0] == 2) {
+			clm_para.clm_app = (enum clm_application)var1[1];
+			clm_para.clm_lv = (enum phydm_clm_level)var1[2];
+			ccx->clm_mntr_mode = CLM_DRIVER_MNTR;
+			clm_para.mntr_time = (u16)var1[3];
+
+		} else if (var1[0] == 3) {
+			clm_para.clm_app = CLM_BACKGROUND;
+			clm_para.clm_lv = CLM_LV_4;
+			ccx->clm_mntr_mode = CLM_FW_MNTR;
+			clm_para.mntr_time = 262;
+		}
+
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "app=%d, lv=%d, mode=%s, time=%d ms\n",
+			 clm_para.clm_app, clm_para.clm_lv,
+			 ((ccx->clm_mntr_mode == CLM_FW_MNTR) ? "FW" :
+			 "driver"), clm_para.mntr_time);
+
+		if (phydm_clm_mntr_set(dm, &clm_para) == PHYDM_SET_SUCCESS)
+			phydm_clm_trigger(dm);
+
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "clm_rpt_stamp=%d\n", ccx->clm_rpt_stamp);
+	}
+
+	*_used = used;
+	*_out_len = out_len;
+}
+
+#endif /*@#ifdef CLM_SUPPORT*/
+
+u8 phydm_env_mntr_trigger(void *dm_void, struct nhm_para_info *nhm_para,
+			  struct clm_para_info *clm_para,
+			  struct env_trig_rpt *trig_rpt)
+{
+#if (defined(NHM_SUPPORT) && defined(CLM_SUPPORT))
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct ccx_info *ccx = &dm->dm_ccx_info;
+	boolean nhm_set_ok = false;
+	boolean clm_set_ok = false;
+	u8 trigger_result = 0;
+
+	PHYDM_DBG(dm, DBG_ENV_MNTR, "[%s] ======>\n", __func__);
+
+#if (ENV_MNTR_DBG_2)
+	if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
+	PHYDM_DBG(dm, DBG_ENV_MNTR,
+		  "[DBG][2] 0xc50=0x%x, 0x994=0x%x, 0x998=0x%x\n",
+		  odm_get_bb_reg(dm, 0xc50, MASKDWORD),
+		  odm_get_bb_reg(dm, 0x994, MASKDWORD),
+		  odm_get_bb_reg(dm, 0x998, MASKDWORD));
+	#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
+	} else if (dm->support_ic_type & ODM_IC_JGR3_SERIES) {
+		PHYDM_DBG(dm, DBG_ENV_MNTR,
+			  "[DBG][2] 0x1d70=0x%x, 0x1e60=0x%x, 0x1e44=0x%x\n",
+			 odm_get_bb_reg(dm, 0x1d70, MASKDWORD),
+			 odm_get_bb_reg(dm, 0x1e60, MASKDWORD),
+			 odm_get_bb_reg(dm, 0x1e44, MASKDWORD));
+	#endif
+	}
+#endif
+
+	/*@[NHM]*/
+	nhm_set_ok = phydm_nhm_mntr_set(dm, nhm_para);
+
+	/*@[CLM]*/
+	if (ccx->clm_mntr_mode == CLM_DRIVER_MNTR) {
+		clm_set_ok = phydm_clm_mntr_set(dm, clm_para);
+	} else if (ccx->clm_mntr_mode == CLM_FW_MNTR) {
+		phydm_clm_h2c(dm, CLM_PERIOD_MAX, true);
+		trigger_result |= CLM_SUCCESS;
+	}
+
+	if (nhm_set_ok) {
+		phydm_nhm_trigger(dm);
+		trigger_result |= NHM_SUCCESS;
+	}
+
+	if (clm_set_ok) {
+		phydm_clm_trigger(dm);
+		trigger_result |= CLM_SUCCESS;
+	}
+
+	/*@monitor for the test duration*/
+	ccx->start_time = odm_get_current_time(dm);
+
+	trig_rpt->nhm_rpt_stamp = ccx->nhm_rpt_stamp;
+	trig_rpt->clm_rpt_stamp = ccx->clm_rpt_stamp;
+
+	PHYDM_DBG(dm, DBG_ENV_MNTR, "nhm_rpt_stamp=%d, clm_rpt_stamp=%d,\n\n",
+		  trig_rpt->nhm_rpt_stamp, trig_rpt->clm_rpt_stamp);
+
+	return trigger_result;
+#endif
+}
+
+u8 phydm_env_mntr_result(void *dm_void, struct env_mntr_rpt *rpt)
+{
+#if (defined(NHM_SUPPORT) && defined(CLM_SUPPORT))
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct ccx_info *ccx = &dm->dm_ccx_info;
+	u8 env_mntr_rpt = 0;
+	u64 progressing_time;
+	u32 val_tmp = 0;
+
+	/*@monitor for the test duration*/
+	progressing_time = odm_get_progressing_time(dm, ccx->start_time);
+	PHYDM_DBG(dm, DBG_ENV_MNTR, "[%s] ======>\n", __func__);
+	PHYDM_DBG(dm, DBG_ENV_MNTR, "env_time=%lld\n", progressing_time);
+
+#if (ENV_MNTR_DBG_2)
+	if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
+		PHYDM_DBG(dm, DBG_ENV_MNTR,
+			  "[DBG][2] 0xc50=0x%x, 0x994=0x%x, 0x998=0x%x\n",
+			  odm_get_bb_reg(dm, 0xc50, MASKDWORD),
+			  odm_get_bb_reg(dm, 0x994, MASKDWORD),
+			  odm_get_bb_reg(dm, 0x998, MASKDWORD));
+	#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
+	} else if (dm->support_ic_type & ODM_IC_JGR3_SERIES) {
+		PHYDM_DBG(dm, DBG_ENV_MNTR,
+			  "[DBG][2] 0x1d70=0x%x, 0x1e60=0x%x, 0x1e44=0x%x\n",
+			  odm_get_bb_reg(dm, 0x1d70, MASKDWORD),
+			  odm_get_bb_reg(dm, 0x1e60, MASKDWORD),
+			  odm_get_bb_reg(dm, 0x1e44, MASKDWORD));
+	#endif
+	}
+#endif
+
+	/*@Get NHM result*/
+	if (phydm_nhm_get_result(dm)) {
+		PHYDM_DBG(dm, DBG_ENV_MNTR, "Get NHM_rpt success\n");
+		phydm_nhm_get_utility(dm);
+		rpt->nhm_ratio = ccx->nhm_ratio;
+		env_mntr_rpt |= NHM_SUCCESS;
+
+		odm_move_memory(dm, &rpt->nhm_result[0],
+				&ccx->nhm_result[0], NHM_RPT_NUM);
+	} else {
+		rpt->nhm_ratio = ENV_MNTR_FAIL;
+	}
+
+	/*@Get CLM result*/
+	if (ccx->clm_mntr_mode == CLM_DRIVER_MNTR) {
+		if (phydm_clm_get_result(dm)) {
+			PHYDM_DBG(dm, DBG_ENV_MNTR, "Get CLM_rpt success\n");
+			phydm_clm_get_utility(dm);
+			env_mntr_rpt |= CLM_SUCCESS;
+			rpt->clm_ratio = ccx->clm_ratio;
+		} else {
+			rpt->clm_ratio = ENV_MNTR_FAIL;
+		}
+
+	} else {
+		if (ccx->clm_fw_result_cnt != 0) {
+			val_tmp = ccx->clm_fw_result_acc
+			/ ccx->clm_fw_result_cnt;
+			ccx->clm_ratio = (u8)val_tmp;
+		} else {
+			ccx->clm_ratio = 0;
+		}
+
+		rpt->clm_ratio = ccx->clm_ratio;
+		PHYDM_DBG(dm, DBG_ENV_MNTR,
+			  "clm_fw_result_acc=%d, clm_fw_result_cnt=%d\n",
+			  ccx->clm_fw_result_acc, ccx->clm_fw_result_cnt);
+
+		ccx->clm_fw_result_acc = 0;
+		ccx->clm_fw_result_cnt = 0;
+		env_mntr_rpt |= CLM_SUCCESS;
+	}
+
+	rpt->nhm_rpt_stamp = ccx->nhm_rpt_stamp;
+	rpt->clm_rpt_stamp = ccx->clm_rpt_stamp;
+
+	PHYDM_DBG(dm, DBG_ENV_MNTR,
+		  "IGI=0x%x, nhm_ratio=%d, clm_ratio=%d, nhm_rpt_stamp=%d, clm_rpt_stamp=%d\n\n",
+		  ccx->nhm_igi, rpt->nhm_ratio, rpt->clm_ratio,
+		  rpt->nhm_rpt_stamp, rpt->clm_rpt_stamp);
+
+	return env_mntr_rpt;
+#endif
+}
+
+/*@Environment Monitor*/
+void phydm_env_mntr_watchdog(void *dm_void)
+{
+#if (defined(NHM_SUPPORT) && defined(CLM_SUPPORT))
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct ccx_info *ccx = &dm->dm_ccx_info;
+	boolean nhm_chk_ok = false;
+	boolean clm_chk_ok = false;
+
+	if (!(dm->support_ability & ODM_BB_ENV_MONITOR))
+		return;
+
+	PHYDM_DBG(dm, DBG_ENV_MNTR, "[%s]===>\n", __func__);
+	nhm_chk_ok = phydm_nhm_mntr_chk(dm, 262); /*@monitor 262ms*/
+	clm_chk_ok = phydm_clm_mntr_chk(dm, 262); /*@monitor 262ms*/
+#if 0
+	/*PHYDM_DBG(dm, DBG_ENV_MNTR, "nhm_chk_ok %d\n\n",nhm_chk_ok);*/
+	/*PHYDM_DBG(dm, DBG_ENV_MNTR, "clm_chk_ok %d\n\n",clm_chk_ok);*/
+#endif
+	if (nhm_chk_ok)
+		phydm_nhm_trigger(dm);
+
+	if (clm_chk_ok)
+		phydm_clm_trigger(dm);
+
+	PHYDM_DBG(dm, DBG_ENV_MNTR,
+		  "Summary: nhm_ratio=((%d)) clm_ratio=((%d))\n\n",
+		  ccx->nhm_ratio, ccx->clm_ratio);
+#endif
+}
+
+void phydm_env_monitor_init(void *dm_void)
+{
+#if (defined(NHM_SUPPORT) && defined(CLM_SUPPORT))
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+
+	if (!(dm->support_ability & ODM_BB_ENV_MONITOR))
+		return;
+
+	PHYDM_DBG(dm, DBG_ENV_MNTR, "[%s]===>\n", __func__);
+	phydm_ccx_hw_restart(dm);
+	phydm_nhm_init(dm);
+	phydm_clm_init(dm);
+#endif
+}
+
+void phydm_env_mntr_dbg(void *dm_void, char input[][16], u32 *_used,
+			char *output, u32 *_out_len)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	char help[] = "-h";
+	u32 var1[10] = {0};
+	u32 used = *_used;
+	u32 out_len = *_out_len;
+	struct clm_para_info clm_para = {0};
+	struct nhm_para_info nhm_para = {0};
+	struct env_mntr_rpt rpt = {0};
+	struct env_trig_rpt trig_rpt = {0};
+	u8 set_result;
+	u8 i;
+
+	PHYDM_SSCANF(input[1], DCMD_DECIMAL, &var1[0]);
+
+	if ((strcmp(input[1], help) == 0)) {
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "Basic-Trigger 262ms: {1}\n");
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "Get Result: {100}\n");
+	} else if (var1[0] == 100) { /* @Get CLM results */
+
+		set_result = phydm_env_mntr_result(dm, &rpt);
+
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "Set Result=%d\n nhm_ratio=%d clm_ratio=%d\n nhm_rpt_stamp=%d, clm_rpt_stamp=%d,\n",
+			 set_result, rpt.nhm_ratio, rpt.clm_ratio,
+			 rpt.nhm_rpt_stamp, rpt.clm_rpt_stamp);
+
+		for (i = 0; i <= 11; i++) {
+			PDM_SNPF(out_len, used, output + used, out_len - used,
+				 "nhm_rpt[%d] = %d (%d percent)\n", i,
+				 rpt.nhm_result[i],
+				 (((rpt.nhm_result[i] * 100) + 128) >> 8));
+		}
+
+	} else { /* Set & trigger CLM */
+		/*nhm para*/
+		nhm_para.incld_txon = NHM_EXCLUDE_TXON;
+		nhm_para.incld_cca = NHM_EXCLUDE_CCA;
+		nhm_para.div_opt = NHM_CNT_ALL;
+		nhm_para.nhm_app = NHM_ACS;
+		nhm_para.nhm_lv = NHM_LV_2;
+		nhm_para.mntr_time = 262;
+
+		/*@clm para*/
+		clm_para.clm_app = CLM_ACS;
+		clm_para.clm_lv = CLM_LV_2;
+		clm_para.mntr_time = 262;
+
+		set_result = phydm_env_mntr_trigger(dm, &nhm_para,
+						    &clm_para, &trig_rpt);
+
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "Set Result=%d, nhm_rpt_stamp=%d, clm_rpt_stamp=%d\n",
+			 set_result, trig_rpt.nhm_rpt_stamp,
+			 trig_rpt.clm_rpt_stamp);
+	}
+
+	*_used = used;
+	*_out_len = out_len;
+}
+
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/phydm_ccx.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/phydm_ccx.h
--- linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/phydm_ccx.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/phydm_ccx.h	2020-04-10 16:35:06.824660441 +0300
@@ -0,0 +1,268 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017  Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * The full GNU General Public License is included in this distribution in the
+ * file called LICENSE.
+ *
+ * Contact Information:
+ * wlanfae <wlanfae@realtek.com>
+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
+ * Hsinchu 300, Taiwan.
+ *
+ * Larry Finger <Larry.Finger@lwfinger.net>
+ *
+ *****************************************************************************/
+
+#ifndef __PHYDMCCX_H__
+#define __PHYDMCCX_H__
+
+/* @1 ============================================================
+ * 1  Definition
+ * 1 ============================================================
+ */
+#define	ENV_MNTR_DBG	0	/*@debug for the HW processing time from NHM/CLM trigger and get result*/
+#define	ENV_MNTR_DBG_1	1	/*@debug 8812A & 8821A P2P Fail to get result*/
+#define	ENV_MNTR_DBG_2	1	/*@debug for read reister*/
+
+#define CCX_EN 1
+
+#define	MAX_ENV_MNTR_TIME	8	/*second*/
+#define	IGI_TO_NHM_TH_MULTIPLIER 2
+#define	MS_TO_4US_RATIO		250
+#define	CCA_CAP			14
+#define	CLM_MAX_REPORT_TIME	10
+#define	DEVIDER_ERROR		0xffff
+#define CLM_PERIOD_MAX		65535
+#define NHM_PERIOD_MAX		65534
+#define	NHM_TH_NUM		11	/*threshold number of NHM*/
+#define	NHM_RPT_NUM		12
+
+#define	IGI_2_NHM_TH(igi)	((igi) << 1)/*NHM_threshold = IGI * 2*/
+#define	NTH_TH_2_RSSI(th)	((th >> 1) - 10)
+
+/*@FAHM*/
+#define	FAHM_INCLD_FA		BIT(0)
+#define	FAHM_INCLD_CRC_OK	BIT(1)
+#define	FAHM_INCLD_CRC_ER	BIT(2)
+
+#define NHM_SUCCESS		BIT(0)
+#define CLM_SUCCESS		BIT(1)
+#define FAHM_SUCCESS		BIT(2)
+#define	ENV_MNTR_FAIL		0xff
+
+/* @1 ============================================================
+ * 1 enumrate
+ * 1 ============================================================
+ */
+enum phydm_clm_level {
+	CLM_RELEASE		= 0,
+	CLM_LV_1		= 1,	/* @Low Priority function */
+	CLM_LV_2		= 2,	/* @Middle Priority function */
+	CLM_LV_3		= 3,	/* @High priority function (ex: Check hang function) */
+	CLM_LV_4		= 4,	/* @Debug function (the highest priority) */
+	CLM_MAX_NUM		= 5
+};
+
+enum phydm_nhm_level {
+	NHM_RELEASE		= 0,
+	NHM_LV_1		= 1,	/* @Low Priority function */
+	NHM_LV_2		= 2,	/* @Middle Priority function */
+	NHM_LV_3		= 3,	/* @High priority function (ex: Check hang function) */
+	NHM_LV_4		= 4,	/* @Debug function (the highest priority) */
+	NHM_MAX_NUM		= 5
+};
+
+enum nhm_divider_opt_all {
+	NHM_CNT_ALL		= 0,	/*nhm SUM report <= 255*/
+	NHM_VALID		= 1,	/*nhm SUM report = 255*/
+	NHM_CNT_INIT
+};
+
+enum nhm_setting {
+	SET_NHM_SETTING,
+	STORE_NHM_SETTING,
+	RESTORE_NHM_SETTING
+};
+
+enum nhm_option_cca_all {
+	NHM_EXCLUDE_CCA		= 0,
+	NHM_INCLUDE_CCA		= 1,
+	NHM_CCA_INIT
+};
+
+enum nhm_option_txon_all {
+	NHM_EXCLUDE_TXON	= 0,
+	NHM_INCLUDE_TXON	= 1,
+	NHM_TXON_INIT
+};
+
+enum nhm_application {
+	NHM_BACKGROUND		= 0,/*@default*/
+	NHM_ACS			= 1,
+	IEEE_11K_HIGH		= 2,
+	IEEE_11K_LOW		= 3,
+	INTEL_XBOX		= 4,
+	NHM_DBG			= 5, /*@manual trigger*/
+};
+
+enum clm_application {
+	CLM_BACKGROUND		= 0,/*@default*/
+	CLM_ACS			= 1,
+};
+
+enum clm_monitor_mode {
+	CLM_DRIVER_MNTR		= 1,
+	CLM_FW_MNTR		= 2
+};
+
+/* @1 ============================================================
+ * 1  structure
+ * 1 ============================================================
+ */
+struct env_trig_rpt {
+	u8			nhm_rpt_stamp;
+	u8			clm_rpt_stamp;
+};
+
+
+struct env_mntr_rpt {
+	u8			nhm_ratio;
+	u8			nhm_result[NHM_RPT_NUM];
+	u8			clm_ratio;
+	u8			nhm_rpt_stamp;
+	u8			clm_rpt_stamp;
+};
+
+struct nhm_para_info {
+	enum nhm_option_txon_all	incld_txon;	/*@Include TX on*/
+	enum nhm_option_cca_all		incld_cca;	/*@Include CCA*/
+	enum nhm_divider_opt_all	div_opt;	/*@divider option*/
+	enum nhm_application		nhm_app;
+	enum phydm_nhm_level		nhm_lv;
+	u16				mntr_time;	/*@0~262 unit ms*/
+
+};
+
+struct clm_para_info {
+	enum clm_application		clm_app;
+	enum phydm_clm_level		clm_lv;
+	u16				mntr_time;	/*@0~262 unit ms*/
+};
+
+struct ccx_info {
+	u32			nhm_trigger_time;
+	u32			clm_trigger_time;
+	u64			start_time;	/*@monitor for the test duration*/
+#ifdef NHM_SUPPORT
+	enum nhm_application		nhm_app;
+	enum nhm_option_txon_all	nhm_include_txon;
+	enum nhm_option_cca_all		nhm_include_cca;
+	enum nhm_divider_opt_all 	nhm_divider_opt;
+	/*Report*/
+	u8			nhm_th[NHM_TH_NUM];
+	u8			nhm_result[NHM_RPT_NUM];
+	u16			nhm_period;	/* @4us per unit */
+	u8			nhm_igi;
+	u8			nhm_manual_ctrl;
+	u8			nhm_ratio;	/*@1% per nuit, it means the interference igi can't overcome.*/
+	u8			nhm_rpt_sum;
+	u16			nhm_duration;	/*@Real time of NHM_VALID */
+	u8			nhm_set_lv;
+	boolean			nhm_ongoing;
+	u8			nhm_rpt_stamp;
+#endif
+#ifdef CLM_SUPPORT
+	enum clm_application	clm_app;
+	u8			clm_manual_ctrl;
+	u8			clm_set_lv;
+	boolean			clm_ongoing;
+	u16			clm_period;	/* @4us per unit */
+	u16			clm_result;
+	u8			clm_ratio;
+	u32			clm_fw_result_acc;
+	u8			clm_fw_result_cnt;
+	enum clm_monitor_mode	clm_mntr_mode;
+	u8			clm_rpt_stamp;
+#endif
+#ifdef FAHM_SUPPORT
+	boolean			fahm_ongoing;
+	u8			env_mntr_igi;
+	u8			fahm_nume_sel;	/*@fahm_numerator_sel: select {FA, CRCOK, CRC_fail} */
+	u8			fahm_denom_sel;	/*@fahm_denominator_sel: select {FA, CRCOK, CRC_fail} */
+	u16			fahm_period;	/*unit: 4us*/
+#endif
+};
+
+/* @1 ============================================================
+ * 1 Function Prototype
+ * 1 ============================================================
+ */
+
+#ifdef FAHM_SUPPORT
+
+void phydm_fahm_init(void *dm_void);
+
+void phydm_fahm_dbg(void *dm_void, char input[][16], u32 *_used, char *output,
+		    u32 *_out_len);
+
+#endif
+
+/*@NHM*/
+#ifdef NHM_SUPPORT
+void phydm_nhm_trigger(void *dm_void);
+
+void phydm_nhm_init(void *dm_void);
+
+void phydm_nhm_dbg(void *dm_void, char input[][16], u32 *_used, char *output,
+		   u32 *_out_len);
+u8 phydm_get_igi(void *dm_void, enum bb_path path);
+#endif
+
+/*@CLM*/
+#ifdef CLM_SUPPORT
+void phydm_clm_c2h_report_handler(void *dm_void, u8 *cmd_buf, u8 cmd_len);
+
+void phydm_clm_h2c(void *dm_void, u16 obs_time, u8 fw_clm_en);
+
+void phydm_clm_setting(void *dm_void, u16 clm_period);
+
+void phydm_clm_trigger(void *dm_void);
+
+boolean phydm_clm_check_rdy(void *dm_void);
+
+void phydm_clm_get_utility(void *dm_void);
+
+boolean phydm_clm_get_result(void *dm_void);
+
+u8 phydm_clm_mntr_set(void *dm_void, struct clm_para_info *clm_para);
+
+void phydm_set_clm_mntr_mode(void *dm_void, enum clm_monitor_mode mode);
+
+void phydm_clm_dbg(void *dm_void, char input[][16], u32 *_used, char *output,
+		   u32 *_out_len);
+#endif
+
+u8 phydm_env_mntr_trigger(void *dm_void, struct nhm_para_info *nhm_para,
+			  struct clm_para_info *clm_para,
+			  struct env_trig_rpt *rpt);
+
+u8 phydm_env_mntr_result(void *dm_void, struct env_mntr_rpt *rpt);
+
+void phydm_env_mntr_watchdog(void *dm_void);
+
+void phydm_env_monitor_init(void *dm_void);
+
+void phydm_env_mntr_dbg(void *dm_void, char input[][16], u32 *_used,
+			char *output, u32 *_out_len);
+
+#endif
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/phydm_cfotracking.c linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/phydm_cfotracking.c
--- linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/phydm_cfotracking.c	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/phydm_cfotracking.c	2020-04-10 16:35:06.824660441 +0300
@@ -0,0 +1,501 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017  Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * The full GNU General Public License is included in this distribution in the
+ * file called LICENSE.
+ *
+ * Contact Information:
+ * wlanfae <wlanfae@realtek.com>
+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
+ * Hsinchu 300, Taiwan.
+ *
+ * Larry Finger <Larry.Finger@lwfinger.net>
+ *
+ *****************************************************************************/
+#include "mp_precomp.h"
+#include "phydm_precomp.h"
+
+s32 phydm_get_cfo_hz(void *dm_void, u32 val, u8 bit_num, u8 frac_num)
+{
+	s32 val_s = 0;
+
+	val_s = phydm_cnvrt_2_sign(val, bit_num);
+
+	if (frac_num == 10) /*@ (X*312500)/1024 ~= X*305*/
+		val_s *= 305;
+	else if (frac_num == 11) /*@ (X*312500)/2048 ~= X*152*/
+		val_s *= 152;
+	else if (frac_num == 12) /*@ (X*312500)/4096 ~= X*76*/
+		val_s *= 76;
+
+	return val_s;
+}
+
+#if (ODM_IC_11AC_SERIES_SUPPORT)
+void phydm_get_cfo_info_ac(void *dm_void, struct phydm_cfo_rpt *cfo)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	u8 i = 0;
+	u32 val[4] = {0};
+	u32 val_1[4] = {0};
+	u32 val_2[4] = {0};
+	u32 val_tmp = 0;
+
+	val[0] = odm_read_4byte(dm, R_0xd0c);
+	val_1[0] = odm_read_4byte(dm, R_0xd10);
+	val_2[0] = odm_get_bb_reg(dm, R_0xd14, 0x1fff0000);
+
+	#if (defined(PHYDM_COMPILE_ABOVE_2SS))
+	val[1] = odm_read_4byte(dm, R_0xd4c);
+	val_1[1] = odm_read_4byte(dm, R_0xd50);
+	val_2[1] = odm_get_bb_reg(dm, R_0xd54, 0x1fff0000);
+	#endif
+
+	#if (defined(PHYDM_COMPILE_ABOVE_3SS))
+	val[2] = odm_read_4byte(dm, R_0xd8c);
+	val_1[2] = odm_read_4byte(dm, R_0xd90);
+	val_2[2] = odm_get_bb_reg(dm, R_0xd94, 0x1fff0000);
+	#endif
+
+	#if (defined(PHYDM_COMPILE_ABOVE_4SS))
+	val[3] = odm_read_4byte(dm, R_0xdcc);
+	val_1[3] = odm_read_4byte(dm, R_0xdd0);
+	val_2[3] = odm_get_bb_reg(dm, R_0xdd4, 0x1fff0000);
+	#endif
+
+	for (i = 0; i < dm->num_rf_path; i++) {
+		val_tmp = val[i] & 0xfff;	/*@ Short CFO, S(12,11)*/
+		cfo->cfo_rpt_s[i] = phydm_get_cfo_hz(dm, val_tmp, 12, 11);
+
+		val_tmp = val[i] >> 16;		/*@ Long CFO, S(13,12)*/
+		cfo->cfo_rpt_l[i] = phydm_get_cfo_hz(dm, val_tmp, 13, 12);
+
+		val_tmp = val_1[i] & 0x7ff;	/*@ SCFO, S(11,10)*/
+		cfo->cfo_rpt_sec[i] = phydm_get_cfo_hz(dm, val_tmp, 11, 10);
+
+		val_tmp = val_1[i] >> 16;	/*@ Acq CFO, S(13,12)*/
+		cfo->cfo_rpt_acq[i] = phydm_get_cfo_hz(dm, val_tmp, 13, 12);
+
+		val_tmp = val_2[i];		/*@ End CFO, S(13,12)*/
+		cfo->cfo_rpt_end[i] = phydm_get_cfo_hz(dm, val_tmp, 13, 12);
+	}
+}
+#endif
+
+#if (ODM_IC_11N_SERIES_SUPPORT)
+void phydm_get_cfo_info_n(void *dm_void, struct phydm_cfo_rpt *cfo)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	u32 val[5] = {0};
+	u32 val_tmp = 0;
+
+	odm_set_bb_reg(dm, R_0xd00, BIT(26), 1);
+
+	val[0] = odm_read_4byte(dm, R_0xdac); /*@ Short CFO*/
+	val[1] = odm_read_4byte(dm, R_0xdb0); /*@ Long CFO*/
+	val[2] = odm_read_4byte(dm, R_0xdb8); /*@ Sec CFO*/
+	val[3] = odm_read_4byte(dm, R_0xde0); /*@ Acq CFO*/
+	val[4] = odm_read_4byte(dm, R_0xdbc); /*@ End CFO*/
+
+	/*@[path-A]*/
+	val_tmp = (val[0] & 0x0fff0000) >> 16;	/*@ Short CFO, S(12,11)*/
+	cfo->cfo_rpt_s[0] = phydm_get_cfo_hz(dm, val_tmp, 12, 11);
+	val_tmp = (val[1] & 0x1fff0000) >> 16;	/*@ Long CFO, S(13,12)*/
+	cfo->cfo_rpt_l[0] = phydm_get_cfo_hz(dm, val_tmp, 13, 12);
+	val_tmp = (val[2] & 0x7ff0000) >> 16;	/*@ Sec CFO, S(11,10)*/
+	cfo->cfo_rpt_sec[0] = phydm_get_cfo_hz(dm, val_tmp, 11, 10);
+	val_tmp = (val[3] & 0x1fff0000) >> 16;	/*@ Acq CFO, S(13,12)*/
+	cfo->cfo_rpt_acq[0] = phydm_get_cfo_hz(dm, val_tmp, 13, 12);
+	val_tmp = (val[4] & 0x1fff0000) >> 16;	/*@ Acq CFO, S(13,12)*/
+	cfo->cfo_rpt_end[0] = phydm_get_cfo_hz(dm, val_tmp, 13, 12);
+
+	#if (defined(PHYDM_COMPILE_ABOVE_2SS))
+	/*@[path-B]*/
+	val_tmp = val[0] & 0xfff;		/*@ Short CFO, S(12,11)*/
+	cfo->cfo_rpt_s[1] = phydm_get_cfo_hz(dm, val_tmp, 12, 11);
+	val_tmp = val[1] & 0x1fff;		/*@ Long CFO, S(13,12)*/
+	cfo->cfo_rpt_l[1] = phydm_get_cfo_hz(dm, val_tmp, 13, 12);
+	val_tmp = val[2] & 0x7ff;		/*@ Sec CFO, S(11,10)*/
+	cfo->cfo_rpt_sec[1] = phydm_get_cfo_hz(dm, val_tmp, 11, 10);
+	val_tmp = val[3] & 0x1fff;		/*@ Acq CFO, S(13,12)*/
+	cfo->cfo_rpt_acq[1] = phydm_get_cfo_hz(dm, val_tmp, 13, 12);
+	val_tmp = val[4] & 0x1fff;		/*@ Acq CFO, S(13,12)*/
+	cfo->cfo_rpt_end[1] = phydm_get_cfo_hz(dm, val_tmp, 13, 12);
+	#endif
+}
+
+void phydm_set_atc_status(void *dm_void, boolean atc_status)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct phydm_cfo_track_struct *cfo_track = &dm->dm_cfo_track;
+	u32 reg_tmp = 0;
+	u32 mask_tmp = 0;
+
+	PHYDM_DBG(dm, DBG_CFO_TRK, "[%s]ATC_en=%d\n", __func__, atc_status);
+
+	if (cfo_track->is_atc_status == atc_status)
+		return;
+
+	reg_tmp = ODM_REG(BB_ATC, dm);
+	mask_tmp = ODM_BIT(BB_ATC, dm);
+	odm_set_bb_reg(dm, reg_tmp, mask_tmp, atc_status);
+	cfo_track->is_atc_status = atc_status;
+}
+
+boolean
+phydm_get_atc_status(void *dm_void)
+{
+	boolean atc_status = false;
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	u32 reg_tmp = 0;
+	u32 mask_tmp = 0;
+
+	reg_tmp = ODM_REG(BB_ATC, dm);
+	mask_tmp = ODM_BIT(BB_ATC, dm);
+
+	atc_status = (boolean)odm_get_bb_reg(dm, reg_tmp, mask_tmp);
+
+	PHYDM_DBG(dm, DBG_CFO_TRK, "[%s]atc_status=%d\n", __func__, atc_status);
+	return atc_status;
+}
+#endif
+
+void phydm_get_cfo_info(void *dm_void, struct phydm_cfo_rpt *cfo)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+
+	switch (dm->ic_ip_series) {
+	#if (ODM_IC_11N_SERIES_SUPPORT)
+	case PHYDM_IC_N:
+		phydm_get_cfo_info_n(dm, cfo);
+		break;
+	#endif
+	#if (ODM_IC_11AC_SERIES_SUPPORT)
+	case PHYDM_IC_AC:
+		phydm_get_cfo_info_ac(dm, cfo);
+		break;
+	#endif
+	default:
+		break;
+	}
+}
+
+void phydm_set_crystal_cap(void *dm_void, u8 crystal_cap)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct phydm_cfo_track_struct *cfo_track = &dm->dm_cfo_track;
+	u32 reg_val = 0;
+
+	if (cfo_track->crystal_cap == crystal_cap)
+		return;
+
+	if (dm->support_ic_type & (ODM_RTL8822C | ODM_RTL8814B)) {
+		crystal_cap &= 0x7F;
+		reg_val = crystal_cap | (crystal_cap << 7);
+	} else {
+		crystal_cap &= 0x3F;
+		reg_val = crystal_cap | (crystal_cap << 6);
+	}
+
+	cfo_track->crystal_cap = crystal_cap;
+
+	if (dm->support_ic_type & (ODM_RTL8188E | ODM_RTL8188F)) {
+		#if (RTL8188E_SUPPORT || RTL8188F_SUPPORT)
+		/* write 0x24[22:17] = 0x24[16:11] = crystal_cap */
+		odm_set_mac_reg(dm, R_0x24, 0x7ff800, reg_val);
+		#endif
+	}
+	#if (RTL8812A_SUPPORT)
+	else if (dm->support_ic_type & ODM_RTL8812) {
+		/* write 0x2C[30:25] = 0x2C[24:19] = crystal_cap */
+		odm_set_mac_reg(dm, R_0x2c, 0x7FF80000, reg_val);
+	}
+	#endif
+	#if (RTL8703B_SUPPORT || RTL8723B_SUPPORT || RTL8192E_SUPPORT ||\
+	     RTL8821A_SUPPORT || RTL8723D_SUPPORT)
+	else if ((dm->support_ic_type &
+		 (ODM_RTL8703B | ODM_RTL8723B | ODM_RTL8192E | ODM_RTL8821 |
+		 ODM_RTL8723D))) {
+		/* @0x2C[23:18] = 0x2C[17:12] = crystal_cap */
+		odm_set_mac_reg(dm, R_0x2c, 0x00FFF000, reg_val);
+	}
+	#endif
+	#if (RTL8814A_SUPPORT)
+	else if (dm->support_ic_type & ODM_RTL8814A) {
+		/* write 0x2C[26:21] = 0x2C[20:15] = crystal_cap */
+		odm_set_mac_reg(dm, R_0x2c, 0x07FF8000, reg_val);
+	}
+	#endif
+	#if (RTL8822B_SUPPORT || RTL8821C_SUPPORT || RTL8197F_SUPPORT ||\
+	     RTL8192F_SUPPORT)
+	else if (dm->support_ic_type & (ODM_RTL8822B | ODM_RTL8821C |
+		 ODM_RTL8197F | ODM_RTL8192F)) {
+		/* write 0x24[30:25] = 0x28[6:1] = crystal_cap */
+		odm_set_mac_reg(dm, R_0x24, 0x7e000000, crystal_cap);
+		odm_set_mac_reg(dm, R_0x28, 0x7e, crystal_cap);
+	}
+	#endif
+	#if (RTL8710B_SUPPORT)
+	else if (dm->support_ic_type & (ODM_RTL8710B)) {
+		#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
+		/* write 0x60[29:24] = 0x60[23:18] = crystal_cap */
+		HAL_SetSYSOnReg(dm->adapter, R_0x60, 0x3FFC0000, reg_val);
+		#endif
+	}
+	#endif
+#if (RTL8822C_SUPPORT || RTL8814B_SUPPORT)
+	else if (dm->support_ic_type & (ODM_RTL8822C | ODM_RTL8814B)) {
+		/* write 0x1040[23:17] = 0x1040[16:10] = crystal_cap */
+		odm_set_mac_reg(dm, R_0x1040, 0x00FFFC00, reg_val);
+	}
+#endif
+	PHYDM_DBG(dm, DBG_CFO_TRK, "Set rystal_cap = 0x%x\n",
+		  cfo_track->crystal_cap);
+}
+
+void phydm_cfo_tracking_reset(void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct phydm_cfo_track_struct *cfo_track = &dm->dm_cfo_track;
+
+	PHYDM_DBG(dm, DBG_CFO_TRK, "%s ======>\n", __func__);
+
+	if (dm->support_ic_type & (ODM_RTL8822C | ODM_RTL8814B))
+		cfo_track->def_x_cap = cfo_track->crystal_cap_default & 0x7F;
+	else
+		cfo_track->def_x_cap = cfo_track->crystal_cap_default & 0x3f;
+
+	cfo_track->is_adjust = true;
+
+	if (cfo_track->crystal_cap > cfo_track->def_x_cap) {
+		phydm_set_crystal_cap(dm, cfo_track->crystal_cap - 1);
+		PHYDM_DBG(dm, DBG_CFO_TRK, "approch to Init-val (0x%x)\n",
+			  cfo_track->crystal_cap);
+
+	} else if (cfo_track->crystal_cap < cfo_track->def_x_cap) {
+		phydm_set_crystal_cap(dm, cfo_track->crystal_cap + 1);
+		PHYDM_DBG(dm, DBG_CFO_TRK, "approch to init-val 0x%x\n",
+			  cfo_track->crystal_cap);
+	}
+
+#if ODM_IC_11N_SERIES_SUPPORT
+#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
+	if (dm->support_ic_type & ODM_IC_11N_SERIES)
+		phydm_set_atc_status(dm, true);
+#endif
+#endif
+}
+
+void phydm_cfo_tracking_init(void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct phydm_cfo_track_struct *cfo_track = &dm->dm_cfo_track;
+
+	PHYDM_DBG(dm, DBG_CFO_TRK, "[%s]=========>\n", __func__);
+	if (dm->support_ic_type & (ODM_RTL8822C | ODM_RTL8814B))
+		cfo_track->crystal_cap = cfo_track->crystal_cap_default & 0x7F;
+	else
+		cfo_track->crystal_cap = cfo_track->crystal_cap_default & 0x3f;
+
+	cfo_track->def_x_cap = cfo_track->crystal_cap;
+	cfo_track->is_adjust = true;
+	PHYDM_DBG(dm, DBG_CFO_TRK, "crystal_cap=0x%x\n", cfo_track->def_x_cap);
+
+#if (RTL8822B_SUPPORT || RTL8821C_SUPPORT)
+	/* @Crystal cap. control by WiFi */
+	if (dm->support_ic_type & (ODM_RTL8822B | ODM_RTL8821C))
+		odm_set_mac_reg(dm, R_0x10, 0x40, 0x1);
+#endif
+}
+
+void phydm_cfo_tracking(void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct phydm_cfo_track_struct *cfo_track = &dm->dm_cfo_track;
+	s32 cfo_avg = 0, cfo_path_sum = 0, cfo_abs = 0;
+	u32 cfo_rpt_sum = 0, cfo_khz_avg[4] = {0};
+	s8 crystal_cap = cfo_track->crystal_cap;
+	u8 i = 0, valid_path_cnt = 0;
+
+	if (!(dm->support_ability & ODM_BB_CFO_TRACKING))
+		return;
+
+	PHYDM_DBG(dm, DBG_CFO_TRK, "%s ======>\n", __func__);
+
+	if (!dm->is_linked || !dm->is_one_entry_only) {
+		phydm_cfo_tracking_reset(dm);
+		PHYDM_DBG(dm, DBG_CFO_TRK, "is_linked=%d, one_entry_only=%d\n",
+			  dm->is_linked, dm->is_one_entry_only);
+
+	} else {
+		/* No new packet */
+		if (cfo_track->packet_count == cfo_track->packet_count_pre) {
+			PHYDM_DBG(dm, DBG_CFO_TRK, "Pkt cnt doesn't change\n");
+			return;
+		}
+		cfo_track->packet_count_pre = cfo_track->packet_count;
+
+		/*@Calculate CFO */
+		for (i = 0; i < dm->num_rf_path; i++) {
+			if (cfo_track->CFO_cnt[i] == 0)
+				continue;
+
+			valid_path_cnt++;
+
+			if (cfo_track->CFO_tail[i] < 0)
+				cfo_abs = 0 - cfo_track->CFO_tail[i];
+			else
+				cfo_abs = cfo_track->CFO_tail[i];
+
+			cfo_rpt_sum = (u32)CFO_HW_RPT_2_KHZ(cfo_abs);
+			cfo_khz_avg[i] = cfo_rpt_sum / cfo_track->CFO_cnt[i];
+
+			PHYDM_DBG(dm, DBG_CFO_TRK,
+				  "[Path-%d] CFO_sum=((%d)), cnt=((%d)), CFO_avg=((%s%d))kHz\n",
+				  i, cfo_rpt_sum, cfo_track->CFO_cnt[i],
+				  ((cfo_track->CFO_tail[i] < 0) ? "-" : " "),
+				  cfo_khz_avg[i]);
+		}
+
+		for (i = 0; i < valid_path_cnt; i++) {
+			if (cfo_track->CFO_tail[i] < 0)
+				cfo_path_sum += (0 - (s32)cfo_khz_avg[i]);
+			else
+				cfo_path_sum += (s32)cfo_khz_avg[i];
+		}
+
+		if (valid_path_cnt >= 2)
+			cfo_avg = cfo_path_sum / valid_path_cnt;
+		else
+			cfo_avg = cfo_path_sum;
+
+		cfo_track->CFO_ave_pre = cfo_avg;
+
+		PHYDM_DBG(dm, DBG_CFO_TRK, "path_cnt=%d, CFO_avg_path=%d kHz\n",
+			  valid_path_cnt, cfo_avg);
+
+		/*reset counter*/
+		for (i = 0; i < dm->num_rf_path; i++) {
+			cfo_track->CFO_tail[i] = 0;
+			cfo_track->CFO_cnt[i] = 0;
+		}
+
+		/* To adjust crystal cap or not */
+		if (!cfo_track->is_adjust) {
+			if (cfo_avg > CFO_TRK_ENABLE_TH ||
+			    cfo_avg < (-CFO_TRK_ENABLE_TH))
+				cfo_track->is_adjust = true;
+		} else {
+			if (cfo_avg < CFO_TRK_STOP_TH &&
+			    cfo_avg > (-CFO_TRK_STOP_TH))
+				cfo_track->is_adjust = false;
+		}
+
+		#ifdef ODM_CONFIG_BT_COEXIST
+		/*@BT case: Disable CFO tracking */
+		if (dm->bt_info_table.is_bt_enabled) {
+			cfo_track->is_adjust = false;
+			phydm_set_crystal_cap(dm, cfo_track->def_x_cap);
+			PHYDM_DBG(dm, DBG_CFO_TRK, "[BT]Disable CFO_track\n");
+		}
+		#endif
+
+		/*@Adjust Crystal Cap. */
+		if (cfo_track->is_adjust) {
+			if (cfo_avg > CFO_TRK_STOP_TH)
+				crystal_cap += 1;
+			else if (cfo_avg < (-CFO_TRK_STOP_TH))
+				crystal_cap -= 1;
+
+			if (dm->support_ic_type & (ODM_RTL8822C |
+			    ODM_RTL8814B)) {
+				if (crystal_cap > 0x7F)
+					crystal_cap = 0x7F;
+			} else {
+				if (crystal_cap > 0x3F)
+					crystal_cap = 0x3F;
+			}
+			if (crystal_cap < 0)
+				crystal_cap = 0;
+
+			phydm_set_crystal_cap(dm, (u8)crystal_cap);
+		}
+
+		PHYDM_DBG(dm, DBG_CFO_TRK, "X_cap{Curr,Default}={0x%x,0x%x}\n",
+			  cfo_track->crystal_cap, cfo_track->def_x_cap);
+
+		/* @Dynamic ATC switch */
+		#if ODM_IC_11N_SERIES_SUPPORT
+		#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
+		if (dm->support_ic_type & ODM_IC_11N_SERIES) {
+			if (cfo_avg < CFO_TH_ATC && cfo_avg > -CFO_TH_ATC)
+				phydm_set_atc_status(dm, false);
+			else
+				phydm_set_atc_status(dm, true);
+
+		}
+		#endif
+		#endif
+	}
+}
+
+void phydm_parsing_cfo(void *dm_void, void *pktinfo_void, s8 *pcfotail,
+		       u8 num_ss)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct phydm_perpkt_info_struct *pktinfo = NULL;
+	struct phydm_cfo_track_struct *cfo_track = &dm->dm_cfo_track;
+	boolean valid_info = false;
+	u8 i = 0;
+
+	if (!(dm->support_ability & ODM_BB_CFO_TRACKING))
+		return;
+
+	pktinfo = (struct phydm_perpkt_info_struct *)pktinfo_void;
+
+#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
+	if (pktinfo->is_packet_match_bssid)
+		valid_info = true;
+#else
+	if (dm->number_active_client == 1)
+		valid_info = true;
+#endif
+	if (valid_info) {
+		if (num_ss > dm->num_rf_path) /*@For fool proof*/
+			num_ss = dm->num_rf_path;
+		#if 0
+		PHYDM_DBG(dm, DBG_CFO_TRK, "num_ss=%d, num_rf_path=%d\n",
+			  num_ss, dm->num_rf_path);
+		#endif
+
+		/* @ Update CFO report for path-A & path-B */
+		/* Only paht-A and path-B have CFO tail and short CFO */
+		for (i = 0; i < num_ss; i++) {
+			cfo_track->CFO_tail[i] += pcfotail[i];
+			cfo_track->CFO_cnt[i]++;
+			#if 0
+			PHYDM_DBG(dm, DBG_CFO_TRK,
+				  "[ID %d][path %d][rate 0x%x] CFO_tail = ((%d)), CFO_tail_sum = ((%d)), CFO_cnt = ((%d))\n",
+				  pktinfo->station_id, i, pktinfo->data_rate,
+				  pcfotail[i], cfo_track->CFO_tail[i],
+				  cfo_track->CFO_cnt[i]);
+			#endif
+		}
+
+		/* @ Update packet counter */
+		if (cfo_track->packet_count == 0xffffffff)
+			cfo_track->packet_count = 0;
+		else
+			cfo_track->packet_count++;
+	}
+}
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/phydm_cfotracking.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/phydm_cfotracking.h
--- linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/phydm_cfotracking.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/phydm_cfotracking.h	2020-04-10 16:35:06.824660441 +0300
@@ -0,0 +1,67 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017  Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * The full GNU General Public License is included in this distribution in the
+ * file called LICENSE.
+ *
+ * Contact Information:
+ * wlanfae <wlanfae@realtek.com>
+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
+ * Hsinchu 300, Taiwan.
+ *
+ * Larry Finger <Larry.Finger@lwfinger.net>
+ *
+ *****************************************************************************/
+
+#ifndef __PHYDMCFOTRACK_H__
+#define __PHYDMCFOTRACK_H__
+
+#define CFO_TRACKING_VERSION "2.0"
+
+#define		CFO_TRK_ENABLE_TH	20 /* @kHz enable CFO_Track threshold*/
+#define		CFO_TRK_STOP_TH		10 /* @kHz disable CFO_Track threshold*/
+#define		CFO_TH_ATC		80 /* @kHz */
+
+struct phydm_cfo_track_struct {
+	boolean		is_atc_status;
+	boolean		is_adjust;	/*@already modify crystal cap*/
+	u8		crystal_cap;
+	u8		crystal_cap_default;
+	u8		def_x_cap;
+	s32		CFO_tail[4];
+	u32		CFO_cnt[4];
+	s32		CFO_ave_pre;
+	u32		packet_count;
+	u32		packet_count_pre;
+};
+
+struct phydm_cfo_rpt {
+	s32 cfo_rpt_s[PHYDM_MAX_RF_PATH];
+	s32 cfo_rpt_l[PHYDM_MAX_RF_PATH];
+	s32 cfo_rpt_acq[PHYDM_MAX_RF_PATH];
+	s32 cfo_rpt_sec[PHYDM_MAX_RF_PATH];
+	s32 cfo_rpt_end[PHYDM_MAX_RF_PATH];
+};
+
+void phydm_get_cfo_info(void *dm_void, struct phydm_cfo_rpt *cfo);
+
+void phydm_set_crystal_cap(void *dm_void, u8 crystal_cap);
+
+void phydm_cfo_tracking_init(void *dm_void);
+
+void phydm_cfo_tracking(void *dm_void);
+
+void phydm_parsing_cfo(void *dm_void, void *pktinfo_void, s8 *pcfotail,
+		       u8 num_ss);
+
+#endif
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/phydm_debug.c linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/phydm_debug.c
--- linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/phydm_debug.c	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/phydm_debug.c	2020-04-10 16:35:06.824660441 +0300
@@ -0,0 +1,4527 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017  Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * The full GNU General Public License is included in this distribution in the
+ * file called LICENSE.
+ *
+ * Contact Information:
+ * wlanfae <wlanfae@realtek.com>
+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
+ * Hsinchu 300, Taiwan.
+ *
+ * Larry Finger <Larry.Finger@lwfinger.net>
+ *
+ *****************************************************************************/
+
+/*@************************************************************
+ * include files
+ ************************************************************/
+
+#include "mp_precomp.h"
+#include "phydm_precomp.h"
+
+void phydm_init_debug_setting(struct dm_struct *dm)
+{
+	dm->fw_debug_components = 0;
+	dm->debug_components =
+
+#if DBG
+	/*@BB Functions*/
+	/*@DBG_DIG					|*/
+	/*@DBG_RA_MASK					|*/
+	/*@DBG_DYN_TXPWR				|*/
+	/*@DBG_FA_CNT					|*/
+	/*@DBG_RSSI_MNTR				|*/
+	/*@DBG_CCKPD					|*/
+	/*@DBG_ANT_DIV					|*/
+	/*@DBG_SMT_ANT					|*/
+	/*@DBG_PWR_TRAIN				|*/
+	/*@DBG_RA					|*/
+	/*@DBG_PATH_DIV					|*/
+	/*@DBG_DFS					|*/
+	/*@DBG_DYN_ARFR					|*/
+	/*@DBG_ADPTVTY					|*/
+	/*@DBG_CFO_TRK					|*/
+	/*@DBG_ENV_MNTR					|*/
+	/*@DBG_PRI_CCA					|*/
+	/*@DBG_ADPTV_SOML				|*/
+	/*@DBG_LNA_SAT_CHK				|*/
+	/*@DBG_PHY_STATUS				|*/
+	/*@DBG_TMP					|*/
+	/*@DBG_FW_TRACE					|*/
+	/*@DBG_TXBF					|*/
+	/*@DBG_COMMON_FLOW				|*/
+	/*@ODM_PHY_CONFIG				|*/
+	/*@ODM_COMP_INIT				|*/
+	/*@DBG_CMN					|*/
+	/*@ODM_COMP_API					|*/
+#endif
+	0;
+
+	dm->fw_buff_is_enpty = true;
+	dm->pre_c2h_seq = 0;
+	dm->c2h_cmd_start = 0;
+	dm->cmn_dbg_msg_cnt = PHYDM_WATCH_DOG_PERIOD;
+	dm->cmn_dbg_msg_period = PHYDM_WATCH_DOG_PERIOD;
+	phydm_reset_rx_rate_distribution(dm);
+}
+
+void phydm_bb_dbg_port_header_sel(void *dm_void, u32 header_idx)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+
+	if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
+		odm_set_bb_reg(dm, R_0x8f8, 0x3c00000, header_idx);
+
+		/*@
+		 * header_idx:
+		 *	(0:) '{ofdm_dbg[31:0]}'
+		 *	(1:) '{cca,crc32_fail,dbg_ofdm[29:0]}'
+		 *	(2:) '{vbon,crc32_fail,dbg_ofdm[29:0]}'
+		 *	(3:) '{cca,crc32_ok,dbg_ofdm[29:0]}'
+		 *	(4:) '{vbon,crc32_ok,dbg_ofdm[29:0]}'
+		 *	(5:) '{dbg_iqk_anta}'
+		 *	(6:) '{cca,ofdm_crc_ok,dbg_dp_anta[29:0]}'
+		 *	(7:) '{dbg_iqk_antb}'
+		 *	(8:) '{DBGOUT_RFC_b[31:0]}'
+		 *	(9:) '{DBGOUT_RFC_a[31:0]}'
+		 *	(a:) '{dbg_ofdm}'
+		 *	(b:) '{dbg_cck}'
+		 */
+	}
+}
+
+void phydm_bb_dbg_port_clock_en(void *dm_void, u8 enable)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	u32 reg_value = 0;
+
+	if (dm->support_ic_type &
+	    (ODM_RTL8822B | ODM_RTL8821C | ODM_RTL8814A | ODM_RTL8814B)) {
+		/*@enable/disable debug port clock, for power saving*/
+		reg_value = enable ? 0x7 : 0;
+		odm_set_bb_reg(dm, R_0x198c, 0x7, reg_value);
+	}
+}
+
+u8 phydm_set_bb_dbg_port(void *dm_void, u8 curr_dbg_priority, u32 debug_port)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	u8 dbg_port_result = false;
+
+	if (curr_dbg_priority > dm->pre_dbg_priority) {
+		if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
+			phydm_bb_dbg_port_clock_en(dm, true);
+
+			odm_set_bb_reg(dm, R_0x8fc, MASKDWORD, debug_port);
+		} else if (dm->support_ic_type & ODM_IC_JGR3_SERIES) {
+			odm_set_bb_reg(dm, R_0x1c3c, 0xfff00, debug_port);
+
+		} else { /*@if (dm->support_ic_type & ODM_IC_11N_SERIES)*/
+			odm_set_bb_reg(dm, R_0x908, MASKDWORD, debug_port);
+		}
+		PHYDM_DBG(dm, ODM_COMP_API,
+			  "DbgPort ((0x%x)) set success, Cur_priority=((%d)), Pre_priority=((%d))\n",
+			  debug_port, curr_dbg_priority, dm->pre_dbg_priority);
+		dm->pre_dbg_priority = curr_dbg_priority;
+		dbg_port_result = true;
+	}
+
+	return dbg_port_result;
+}
+
+void phydm_release_bb_dbg_port(void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+
+	phydm_bb_dbg_port_clock_en(dm, false);
+	phydm_bb_dbg_port_header_sel(dm, 0);
+
+	dm->pre_dbg_priority = DBGPORT_RELEASE;
+	PHYDM_DBG(dm, ODM_COMP_API, "Release BB dbg_port\n");
+}
+
+u32 phydm_get_bb_dbg_port_val(void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	u32 dbg_port_value = 0;
+
+	if (dm->support_ic_type & ODM_IC_11AC_SERIES)
+		dbg_port_value = odm_get_bb_reg(dm, R_0xfa0, MASKDWORD);
+	else if (dm->support_ic_type & ODM_IC_JGR3_SERIES)
+		dbg_port_value = odm_get_bb_reg(dm, R_0x2dbc, MASKDWORD);
+	else /*@if (dm->support_ic_type & ODM_IC_11N_SERIES)*/
+		dbg_port_value = odm_get_bb_reg(dm, R_0xdf4, MASKDWORD);
+
+	PHYDM_DBG(dm, ODM_COMP_API, "dbg_port_value = 0x%x\n", dbg_port_value);
+	return dbg_port_value;
+}
+
+#ifdef CONFIG_PHYDM_DEBUG_FUNCTION
+#if (ODM_IC_11N_SERIES_SUPPORT)
+void phydm_bb_hw_dbg_info_n(void *dm_void, u32 *_used, char *output,
+			    u32 *_out_len)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	u32 used = *_used;
+	u32 out_len = *_out_len;
+	u32 value32 = 0, value32_1 = 0;
+	u8 rf_gain_a = 0, rf_gain_b = 0, rf_gain_c = 0, rf_gain_d = 0;
+	u8 rx_snr_a = 0, rx_snr_b = 0, rx_snr_c = 0, rx_snr_d = 0;
+	s8 rxevm_0 = 0, rxevm_1 = 0;
+	#if 1
+	struct phydm_cfo_rpt cfo;
+	u8 i = 0;
+	#else
+	s32 short_cfo_a = 0, short_cfo_b = 0, long_cfo_a = 0, long_cfo_b = 0;
+	s32 scfo_a = 0, scfo_b = 0, avg_cfo_a = 0, avg_cfo_b = 0;
+	s32 cfo_end_a = 0, cfo_end_b = 0, acq_cfo_a = 0, acq_cfo_b = 0;
+	#endif
+
+	PDM_SNPF(out_len, used, output + used, out_len - used, "\r\n %-35s\n",
+		 "BB Report Info");
+
+	/*@AGC result*/
+	value32 = odm_get_bb_reg(dm, R_0xdd0, MASKDWORD);
+	rf_gain_a = (u8)(value32 & 0x3f);
+	rf_gain_a = rf_gain_a << 1;
+
+	rf_gain_b = (u8)((value32 >> 8) & 0x3f);
+	rf_gain_b = rf_gain_b << 1;
+
+	rf_gain_c = (u8)((value32 >> 16) & 0x3f);
+	rf_gain_c = rf_gain_c << 1;
+
+	rf_gain_d = (u8)((value32 >> 24) & 0x3f);
+	rf_gain_d = rf_gain_d << 1;
+
+	PDM_SNPF(out_len, used, output + used, out_len - used,
+		 "\r\n %-35s = %d / %d / %d / %d", "OFDM RX RF Gain(A/B/C/D)",
+		 rf_gain_a, rf_gain_b, rf_gain_c, rf_gain_d);
+
+	/*SNR report*/
+	value32 = odm_get_bb_reg(dm, R_0xdd4, MASKDWORD);
+	rx_snr_a = (u8)(value32 & 0xff);
+	rx_snr_a = rx_snr_a >> 1;
+
+	rx_snr_b = (u8)((value32 >> 8) & 0xff);
+	rx_snr_b = rx_snr_b >> 1;
+
+	rx_snr_c = (u8)((value32 >> 16) & 0xff);
+	rx_snr_c = rx_snr_c >> 1;
+
+	rx_snr_d = (u8)((value32 >> 24) & 0xff);
+	rx_snr_d = rx_snr_d >> 1;
+
+	PDM_SNPF(out_len, used, output + used, out_len - used,
+		 "\r\n %-35s = %d / %d / %d / %d", "RXSNR(A/B/C/D, dB)",
+		 rx_snr_a, rx_snr_b, rx_snr_c, rx_snr_d);
+
+	/* PostFFT related info*/
+	value32 = odm_get_bb_reg(dm, R_0xdd8, MASKDWORD);
+
+	rxevm_0 = (s8)((value32 & MASKBYTE2) >> 16);
+	rxevm_0 /= 2;
+	if (rxevm_0 < -63)
+		rxevm_0 = 0;
+
+	rxevm_1 = (s8)((value32 & MASKBYTE3) >> 24);
+	rxevm_1 /= 2;
+	if (rxevm_1 < -63)
+		rxevm_1 = 0;
+
+	PDM_SNPF(out_len, used, output + used, out_len - used,
+		 "\r\n %-35s = %d / %d", "RXEVM (1ss/2ss)", rxevm_0, rxevm_1);
+
+#if 1
+	phydm_get_cfo_info(dm, &cfo);
+	for (i = 0; i < dm->num_rf_path; i++) {
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "\r\n %s[%d] %-28s = {%d, %d, %d, %d, %d}",
+			 "CFO", i, "{S, L, Sec, Acq, End}",
+			 cfo.cfo_rpt_s[i], cfo.cfo_rpt_l[i], cfo.cfo_rpt_sec[i],
+			 cfo.cfo_rpt_acq[i], cfo.cfo_rpt_end[i]);
+	}
+#else
+	/*@CFO Report Info*/
+	odm_set_bb_reg(dm, R_0xd00, BIT(26), 1);
+
+	/*Short CFO*/
+	value32 = odm_get_bb_reg(dm, R_0xdac, MASKDWORD);
+	value32_1 = odm_get_bb_reg(dm, R_0xdb0, MASKDWORD);
+
+	short_cfo_b = (s32)(value32 & 0xfff); /*S(12,11)*/
+	short_cfo_a = (s32)((value32 & 0x0fff0000) >> 16);
+
+	long_cfo_b = (s32)(value32_1 & 0x1fff); /*S(13,12)*/
+	long_cfo_a = (s32)((value32_1 & 0x1fff0000) >> 16);
+
+	/*SFO 2's to dec*/
+	if (short_cfo_a > 2047)
+		short_cfo_a = short_cfo_a - 4096;
+	if (short_cfo_b > 2047)
+		short_cfo_b = short_cfo_b - 4096;
+
+	short_cfo_a = (short_cfo_a * 312500) / 2048;
+	short_cfo_b = (short_cfo_b * 312500) / 2048;
+
+	/*@LFO 2's to dec*/
+
+	if (long_cfo_a > 4095)
+		long_cfo_a = long_cfo_a - 8192;
+
+	if (long_cfo_b > 4095)
+		long_cfo_b = long_cfo_b - 8192;
+
+	long_cfo_a = long_cfo_a * 312500 / 4096;
+	long_cfo_b = long_cfo_b * 312500 / 4096;
+
+	PDM_SNPF(out_len, used, output + used, out_len - used, "\r\n %-35s",
+		 "CFO Report Info");
+	PDM_SNPF(out_len, used, output + used, out_len - used,
+		 "\r\n %-35s = %d / %d", "Short CFO(Hz) <A/B>", short_cfo_a,
+		 short_cfo_b);
+	PDM_SNPF(out_len, used, output + used, out_len - used,
+		 "\r\n %-35s = %d / %d", "Long CFO(Hz) <A/B>", long_cfo_a,
+		 long_cfo_b);
+
+	/*SCFO*/
+	value32 = odm_get_bb_reg(dm, R_0xdb8, MASKDWORD);
+	value32_1 = odm_get_bb_reg(dm, R_0xdb4, MASKDWORD);
+
+	scfo_b = (s32)(value32 & 0x7ff); /*S(11,10)*/
+	scfo_a = (s32)((value32 & 0x07ff0000) >> 16);
+
+	if (scfo_a > 1023)
+		scfo_a = scfo_a - 2048;
+
+	if (scfo_b > 1023)
+		scfo_b = scfo_b - 2048;
+
+	scfo_a = scfo_a * 312500 / 1024;
+	scfo_b = scfo_b * 312500 / 1024;
+
+	avg_cfo_b = (s32)(value32_1 & 0x1fff); /*S(13,12)*/
+	avg_cfo_a = (s32)((value32_1 & 0x1fff0000) >> 16);
+
+	if (avg_cfo_a > 4095)
+		avg_cfo_a = avg_cfo_a - 8192;
+
+	if (avg_cfo_b > 4095)
+		avg_cfo_b = avg_cfo_b - 8192;
+
+	avg_cfo_a = avg_cfo_a * 312500 / 4096;
+	avg_cfo_b = avg_cfo_b * 312500 / 4096;
+
+	PDM_SNPF(out_len, used, output + used, out_len - used,
+		 "\r\n %-35s = %d / %d", "value SCFO(Hz) <A/B>", scfo_a,
+		 scfo_b);
+	PDM_SNPF(out_len, used, output + used, out_len - used,
+		 "\r\n %-35s = %d / %d", "Avg CFO(Hz) <A/B>", avg_cfo_a,
+		 avg_cfo_b);
+
+	value32 = odm_get_bb_reg(dm, R_0xdbc, MASKDWORD);
+	value32_1 = odm_get_bb_reg(dm, R_0xde0, MASKDWORD);
+
+	cfo_end_b = (s32)(value32 & 0x1fff); /*S(13,12)*/
+	cfo_end_a = (s32)((value32 & 0x1fff0000) >> 16);
+
+	if (cfo_end_a > 4095)
+		cfo_end_a = cfo_end_a - 8192;
+
+	if (cfo_end_b > 4095)
+		cfo_end_b = cfo_end_b - 8192;
+
+	cfo_end_a = cfo_end_a * 312500 / 4096;
+	cfo_end_b = cfo_end_b * 312500 / 4096;
+
+	acq_cfo_b = (s32)(value32_1 & 0x1fff); /*S(13,12)*/
+	acq_cfo_a = (s32)((value32_1 & 0x1fff0000) >> 16);
+
+	if (acq_cfo_a > 4095)
+		acq_cfo_a = acq_cfo_a - 8192;
+
+	if (acq_cfo_b > 4095)
+		acq_cfo_b = acq_cfo_b - 8192;
+
+	acq_cfo_a = acq_cfo_a * 312500 / 4096;
+	acq_cfo_b = acq_cfo_b * 312500 / 4096;
+
+	PDM_SNPF(out_len, used, output + used, out_len - used,
+		 "\r\n %-35s = %d / %d", "End CFO(Hz) <A/B>", cfo_end_a,
+		 cfo_end_b);
+	PDM_SNPF(out_len, used, output + used, out_len - used,
+		 "\r\n %-35s = %d / %d", "ACQ CFO(Hz) <A/B>", acq_cfo_a,
+		 acq_cfo_b);
+#endif
+}
+#endif
+
+#if (ODM_IC_11AC_SERIES_SUPPORT)
+#if (RTL8822B_SUPPORT)
+void phydm_bb_hw_dbg_info_8822b(void *dm_void, u32 *_used, char *output,
+				u32 *_out_len)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	u32 used = *_used;
+	u32 out_len = *_out_len;
+	u32 condi_num = 0;
+	u8 i = 0;
+
+	if (!(dm->support_ic_type == ODM_RTL8822B))
+		return;
+
+	condi_num = phydm_get_condi_num_8822b(dm);
+	phydm_get_condi_num_acc_8822b(dm);
+
+	PDM_SNPF(out_len, used, output + used, out_len - used,
+		 "\r\n %-35s = %d.%.4d", "condi_num",
+		 condi_num >> 4, phydm_show_fraction_num(condi_num & 0xf, 4));
+
+	for (i = 0; i < CN_CNT_MAX; i++) {
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "\r\n Tone_num[CN>%d]%-21s = %d",
+			 i, " ", dm->phy_dbg_info.condi_num_cdf[i]);
+	}
+
+	*_used = used;
+	*_out_len = out_len;
+}
+#endif
+
+void phydm_bb_hw_dbg_info_ac(void *dm_void, u32 *_used, char *output,
+			     u32 *_out_len)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	u32 used = *_used;
+	u32 out_len = *_out_len;
+	char *tmp_string = NULL;
+	u8 rx_ht_bw, rx_vht_bw, rxsc, rx_ht, bw_idx = 0;
+	static u8 v_rx_bw;
+	u32 value32, value32_1, value32_2, value32_3;
+	struct phydm_cfo_rpt cfo;
+	u8 i = 0;
+	static u8 tail, parity, rsv, vrsv, smooth, htsound, agg;
+	static u8 stbc, vstbc, fec, fecext, sgi, sgiext, htltf, vgid, v_nsts;
+	static u8 vtxops, vrsv2, vbrsv, bf, vbcrc;
+	static u16 h_length, htcrc8, length;
+	static u16 vpaid;
+	static u16 v_length, vhtcrc8, v_mcss, v_tail, vb_tail;
+	static u8 hmcss, hrx_bw;
+	u8 pwdb;
+	s8 rxevm_0, rxevm_1, rxevm_2;
+	u8 rf_gain[4];
+	u8 rx_snr[4];
+	s32 sig_power;
+
+	PDM_SNPF(out_len, used, output + used, out_len - used, "\r\n %-35s\n",
+		 "BB Report Info");
+
+	/*@ [BW & Mode] =====================================================*/
+
+	value32 = odm_get_bb_reg(dm, R_0xf80, MASKDWORD);
+	rx_ht = (u8)((value32 & 0x180) >> 7);
+
+	if (rx_ht == AD_VHT_MODE) {
+		tmp_string = "VHT";
+		bw_idx = (u8)((value32 >> 1) & 0x3);
+	} else if (rx_ht == AD_HT_MODE) {
+		tmp_string = "HT";
+		bw_idx = (u8)(value32 & 0x1);
+	} else {
+		tmp_string = "Legacy";
+		bw_idx = 0;
+	}
+	PDM_SNPF(out_len, used, output + used, out_len - used,
+		 "\r\n %-35s %s %dM", "mode", tmp_string, (20 << bw_idx));
+
+	if (rx_ht != AD_LEGACY_MODE) {
+		rxsc = (u8)(value32 & 0x78);
+
+		if (rxsc == 0)
+			tmp_string = "duplicate/full bw";
+		else if (rxsc == 1)
+			tmp_string = "usc20-1";
+		else if (rxsc == 2)
+			tmp_string = "lsc20-1";
+		else if (rxsc == 3)
+			tmp_string = "usc20-2";
+		else if (rxsc == 4)
+			tmp_string = "lsc20-2";
+		else if (rxsc == 9)
+			tmp_string = "usc40";
+		else if (rxsc == 10)
+			tmp_string = "lsc40";
+
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "  %-35s", tmp_string);
+	}
+
+	/*@ [RX signal power and AGC related info] ==========================*/
+
+	pwdb = (u8)odm_get_bb_reg(dm, R_0xf90, MASKBYTE1);
+	sig_power = -110 + (pwdb >> 1);
+	PDM_SNPF(out_len, used, output + used, out_len - used,
+		 "\r\n %-35s = %d", "OFDM RX Signal Power(dB)", sig_power);
+
+	value32 = odm_get_bb_reg(dm, R_0xd14, MASKDWORD);
+	rx_snr[RF_PATH_A] = (u8)(value32 & 0xFF) >> 1; /*@ S(8,1)*/
+	rf_gain[RF_PATH_A] = (s8)(((value32 & MASKBYTE1) >> 8) * 2);
+
+	value32 = odm_get_bb_reg(dm, R_0xd54, MASKDWORD);
+	rx_snr[RF_PATH_B] = (u8)(value32 & 0xFF) >> 1; /*@ S(8,1)*/
+	rf_gain[RF_PATH_B] = (s8)(((value32 & MASKBYTE1) >> 8) * 2);
+
+	value32 = odm_get_bb_reg(dm, R_0xd94, MASKDWORD);
+	rx_snr[RF_PATH_C] = (u8)(value32 & 0xFF) >> 1; /*@ S(8,1)*/
+	rf_gain[RF_PATH_C] = (s8)(((value32 & MASKBYTE1) >> 8) * 2);
+
+	value32 = odm_get_bb_reg(dm, R_0xdd4, MASKDWORD);
+	rx_snr[RF_PATH_D] = (u8)(value32 & 0xFF) >> 1; /*@ S(8,1)*/
+	rf_gain[RF_PATH_D] = (s8)(((value32 & MASKBYTE1) >> 8) * 2);
+
+	PDM_SNPF(out_len, used, output + used, out_len - used,
+		 "\r\n %-35s = %d / %d / %d / %d", "OFDM RX RF Gain(A/B/C/D)",
+		 rf_gain[RF_PATH_A], rf_gain[RF_PATH_B],
+		 rf_gain[RF_PATH_C], rf_gain[RF_PATH_D]);
+
+	/*@ [RX counter Info] ===============================================*/
+
+	PDM_SNPF(out_len, used, output + used, out_len - used,
+		 "\r\n %-35s = %d", "OFDM CCA cnt",
+		 odm_get_bb_reg(dm, R_0xf08, 0xFFFF0000));
+
+	PDM_SNPF(out_len, used, output + used, out_len - used,
+		 "\r\n %-35s = %d", "OFDM SBD Fail cnt",
+		 odm_get_bb_reg(dm, R_0xfd0, 0xFFFF));
+
+	value32 = odm_get_bb_reg(dm, R_0xfc4, MASKDWORD);
+	PDM_SNPF(out_len, used, output + used, out_len - used,
+		 "\r\n %-35s = %d / %d", "VHT SIGA/SIGB CRC8 Fail cnt",
+		 value32 & 0xFFFF, ((value32 & 0xFFFF0000) >> 16));
+
+	PDM_SNPF(out_len, used, output + used, out_len - used,
+		 "\r\n %-35s = %d", "CCK CCA cnt",
+		 odm_get_bb_reg(dm, R_0xfcc, 0xFFFF));
+
+	value32 = odm_get_bb_reg(dm, R_0xfbc, MASKDWORD);
+	PDM_SNPF(out_len, used, output + used, out_len - used,
+		 "\r\n %-35s = %d / %d",
+		 "LSIG (parity Fail/rate Illegal) cnt", value32 & 0xFFFF,
+		 ((value32 & 0xFFFF0000) >> 16));
+
+	PDM_SNPF(out_len, used, output + used, out_len - used,
+		 "\r\n %-35s = %d / %d", "HT/VHT MCS NOT SUPPORT cnt",
+		 odm_get_bb_reg(dm, R_0xfc0, (0xFFFF0000 >> 16)),
+		 odm_get_bb_reg(dm, R_0xfc8, 0xFFFF));
+
+	/*@ [PostFFT Info] =================================================*/
+	value32 = odm_get_bb_reg(dm, R_0xf8c, MASKDWORD);
+	rxevm_0 = (s8)((value32 & MASKBYTE2) >> 16);
+	rxevm_0 /= 2;
+	if (rxevm_0 < -63)
+		rxevm_0 = 0;
+
+	rxevm_1 = (s8)((value32 & MASKBYTE3) >> 24);
+	rxevm_1 /= 2;
+	value32 = odm_get_bb_reg(dm, R_0xf88, MASKDWORD);
+	rxevm_2 = (s8)((value32 & MASKBYTE2) >> 16);
+	rxevm_2 /= 2;
+
+	if (rxevm_1 < -63)
+		rxevm_1 = 0;
+	if (rxevm_2 < -63)
+		rxevm_2 = 0;
+
+	PDM_SNPF(out_len, used, output + used, out_len - used,
+		 "\r\n %-35s = %d / %d / %d", "RXEVM (1ss/2ss/3ss)", rxevm_0,
+		 rxevm_1, rxevm_2);
+	PDM_SNPF(out_len, used, output + used, out_len - used,
+		 "\r\n %-35s = %d / %d / %d / %d", "RXSNR(A/B/C/D dB)",
+		 rx_snr[RF_PATH_A], rx_snr[RF_PATH_B],
+		 rx_snr[RF_PATH_C], rx_snr[RF_PATH_D]);
+
+	value32 = odm_get_bb_reg(dm, R_0xf8c, MASKDWORD);
+	PDM_SNPF(out_len, used, output + used, out_len - used,
+		 "\r\n %-35s = %d / %d", "CSI_1st /CSI_2nd", value32 & 0xFFFF,
+		 ((value32 & 0xFFFF0000) >> 16));
+
+	/*@ [CFO Report Info] ===============================================*/
+	phydm_get_cfo_info(dm, &cfo);
+	for (i = 0; i < dm->num_rf_path; i++) {
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "\r\n %s[%d] %-28s = {%d, %d, %d, %d, %d}",
+			 "CFO", i, "{S, L, Sec, Acq, End}",
+			 cfo.cfo_rpt_s[i], cfo.cfo_rpt_l[i], cfo.cfo_rpt_sec[i],
+			 cfo.cfo_rpt_acq[i], cfo.cfo_rpt_end[i]);
+	}
+
+	/*@ [L-SIG Content] =================================================*/
+	value32 = odm_get_bb_reg(dm, R_0xf20, MASKDWORD);
+
+	tail = (u8)((value32 & 0xfc0000) >> 18);/*@[23:18]*/
+	parity = (u8)((value32 & 0x20000) >> 17);/*@[17]*/
+	length = (u16)((value32 & 0x1ffe0) >> 5);/*@[16:5]*/
+	rsv = (u8)((value32 & 0x10) >> 4);/*@[4]*/
+
+	PDM_SNPF(out_len, used, output + used, out_len - used, "\r\n %-35s",
+		 "L-SIG");
+	PDM_SNPF(out_len, used, output + used, out_len - used,
+		 "\r\n %-35s = %d M", "rate",
+		 phydm_get_l_sig_rate(dm, (u8)(value32 & 0x0f)));
+
+	PDM_SNPF(out_len, used, output + used, out_len - used,
+		 "\r\n %-35s = %x / %d / %d", "Rsv/length/parity", rsv, length,
+		 parity);
+
+	if (rx_ht == AD_HT_MODE) {
+	/*@ [HT SIG 1] ======================================================*/
+		value32 = odm_get_bb_reg(dm, R_0xf2c, MASKDWORD);
+
+		hmcss = (u8)(value32 & 0x7F);
+		hrx_bw = (u8)((value32 & 0x80) >> 7);
+		h_length = (u16)((value32 & 0x0fff00) >> 8);
+
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "\r\n %-35s", "HT-SIG1");
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "\r\n %-35s = %d / %d / %d", "MCS/BW/length",
+			 hmcss, hrx_bw, h_length);
+	/*@ [HT SIG 2] ======================================================*/
+		value32 = odm_get_bb_reg(dm, R_0xf30, MASKDWORD);
+		smooth = (u8)(value32 & 0x01);
+		htsound = (u8)((value32 & 0x02) >> 1);
+		rsv = (u8)((value32 & 0x04) >> 2);
+		agg = (u8)((value32 & 0x08) >> 3);
+		stbc = (u8)((value32 & 0x30) >> 4);
+		fec = (u8)((value32 & 0x40) >> 6);
+		sgi = (u8)((value32 & 0x80) >> 7);
+		htltf = (u8)((value32 & 0x300) >> 8);
+		htcrc8 = (u16)((value32 & 0x3fc00) >> 10);
+		tail = (u8)((value32 & 0xfc0000) >> 18);
+
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "\r\n %-35s",
+			 "HT-SIG2");
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "\r\n %-35s = %x / %x / %x / %x / %x / %x",
+			 "Smooth/NoSound/Rsv/Aggregate/STBC/LDPC",
+			 smooth, htsound, rsv, agg, stbc, fec);
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "\r\n %-35s = %x / %x / %x / %x",
+			 "SGI/E-HT-LTFs/CRC/tail",
+			 sgi, htltf, htcrc8, tail);
+	} else if (rx_ht == AD_VHT_MODE) {
+	/*@ [VHT SIG A1] ====================================================*/
+		value32 = odm_get_bb_reg(dm, R_0xf2c, MASKDWORD);
+
+		v_rx_bw = (u8)(value32 & 0x03);
+		vrsv = (u8)((value32 & 0x04) >> 2);
+		vstbc = (u8)((value32 & 0x08) >> 3);
+		vgid = (u8)((value32 & 0x3f0) >> 4);
+		v_nsts = (u8)(((value32 & 0x1c00) >> 10) + 1);
+		vpaid = (u16)((value32 & 0x3fe000) >> 13);
+		vtxops = (u8)((value32 & 0x400000) >> 22);
+		vrsv2 = (u8)((value32 & 0x800000) >> 23);
+
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "\r\n %-35s",
+			 "VHT-SIG-A1");
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "\r\n %-35s = %x / %x / %x / %x / %x / %x / %x / %x",
+			 "BW/Rsv1/STBC/GID/Nsts/PAID/TXOPPS/Rsv2", v_rx_bw,
+			 vrsv, vstbc, vgid, v_nsts, vpaid, vtxops, vrsv2);
+
+	/*@ [VHT SIG A2] ====================================================*/
+		value32 = odm_get_bb_reg(dm, R_0xf30, MASKDWORD);
+
+		/* @sgi=(u8)(value32&0x01); */
+		sgiext = (u8)(value32 & 0x03);
+		/* @fec = (u8)(value32&0x04); */
+		fecext = (u8)((value32 & 0x0C) >> 2);
+
+		v_mcss = (u8)((value32 & 0xf0) >> 4);
+		bf = (u8)((value32 & 0x100) >> 8);
+		vrsv = (u8)((value32 & 0x200) >> 9);
+		vhtcrc8 = (u16)((value32 & 0x3fc00) >> 10);
+		v_tail = (u8)((value32 & 0xfc0000) >> 18);
+
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "\r\n %-35s", "VHT-SIG-A2");
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "\r\n %-35s = %x / %x / %x / %x / %x / %x / %x",
+			 "SGI/FEC/MCS/BF/Rsv/CRC/tail",
+			 sgiext, fecext, v_mcss, bf, vrsv, vhtcrc8, v_tail);
+
+	/*@ [VHT SIG B] ====================================================*/
+		value32 = odm_get_bb_reg(dm, R_0xf34, MASKDWORD);
+
+		#if 0
+		v_length = (u16)(value32 & 0x1fffff);
+		vbrsv = (u8)((value32 & 0x600000) >> 21);
+		vb_tail = (u16)((value32 & 0x1f800000) >> 23);
+		vbcrc = (u8)((value32 & 0x80000000) >> 31);
+		#endif
+
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "\r\n %-35s", "VHT-SIG-B");
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "\r\n %-35s = %x",
+			 "Codeword", value32);
+
+		#if 0
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "\r\n %-35s = %x / %x / %x / %x",
+			 "length/Rsv/tail/CRC",
+			 v_length, vbrsv, vb_tail, vbcrc);
+		#endif
+	}
+
+	*_used = used;
+	*_out_len = out_len;
+}
+#endif
+
+#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
+void phydm_bb_hw_dbg_info_jgr3(void *dm_void, u32 *_used, char *output,
+			       u32 *_out_len)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	u32 used = *_used;
+	u32 out_len = *_out_len;
+	char *tmp_string = NULL;
+	u8 rx_ht_bw = 0, rx_vht_bw = 0, rx_ht = 0;
+	static u8 v_rx_bw;
+	u32 value32 = 0;
+	u8 i = 0;
+	static u8 tail, parity, rsv, vrsv, smooth, htsound, agg;
+	static u8 stbc, vstbc, fec, fecext, sgi, sgiext, htltf, vgid, v_nsts;
+	static u8 vtxops, vrsv2, vbrsv, bf, vbcrc;
+	static u16 h_length, htcrc8, length;
+	static u16 vpaid;
+	static u16 v_length, vhtcrc8, v_mcss, v_tail, vb_tail;
+	static u8 hmcss, hrx_bw;
+
+	PDM_SNPF(out_len, used, output + used, out_len - used, "\r\n %-35s\n",
+		 "BB Report Info");
+
+	/*@ [Mode] =====================================================*/
+
+	value32 = odm_get_bb_reg(dm, R_0x2c20, MASKDWORD);
+	rx_ht = (u8)((value32 & 0xC0000) >> 18);
+	if (rx_ht == AD_VHT_MODE)
+		tmp_string = "VHT";
+	else if (rx_ht == AD_HT_MODE)
+		tmp_string = "HT";
+	else
+		tmp_string = "Legacy";
+
+	PDM_SNPF(out_len, used, output + used, out_len - used,
+		 "\r\n %-35s %s", "mode", tmp_string);
+	/*@ [RX counter Info] ===============================================*/
+
+	PDM_SNPF(out_len, used, output + used, out_len - used,
+		 "\r\n %-35s = %d", "OFDM CCA cnt",
+		 odm_get_bb_reg(dm, R_0x2c08, 0xFFFF0000));
+
+	PDM_SNPF(out_len, used, output + used, out_len - used,
+		 "\r\n %-35s = %d", "OFDM SBD Fail cnt",
+		 odm_get_bb_reg(dm, R_0x2d20, 0xFFFF0000));
+
+	value32 = odm_get_bb_reg(dm, R_0x2d0c, MASKDWORD);
+	PDM_SNPF(out_len, used, output + used, out_len - used,
+		 "\r\n %-35s = %d / %d", "VHT SIGA/SIGB CRC8 Fail cnt",
+		 value32 & 0xFFFF, ((value32 & 0xFFFF0000) >> 16));
+
+	PDM_SNPF(out_len, used, output + used, out_len - used,
+		 "\r\n %-35s = %d", "CCK CCA cnt",
+		 odm_get_bb_reg(dm, R_0x2c08, 0xFFFF));
+
+	PDM_SNPF(out_len, used, output + used, out_len - used,
+		 "\r\n %-35s = %d / %d",
+		 "LSIG (parity Fail/rate Illegal) cnt",
+		 odm_get_bb_reg(dm, R_0x2d04, 0xFFFF0000),
+		 odm_get_bb_reg(dm, R_0x2d08, 0xFFFF));
+
+	value32 = odm_get_bb_reg(dm, R_0x2d10, MASKDWORD);
+	PDM_SNPF(out_len, used, output + used, out_len - used,
+		 "\r\n %-35s = %d / %d", "HT/VHT MCS NOT SUPPORT cnt",
+		 value32 & 0xFFFF, ((value32 & 0xFFFF0000) >> 16));
+	/*@ [L-SIG Content] =================================================*/
+	value32 = odm_get_bb_reg(dm, R_0x2c20, MASKDWORD);
+
+	parity = (u8)((value32 & 0x20000) >> 17);/*@[17]*/
+	length = (u16)((value32 & 0x1ffe0) >> 5);/*@[16:5]*/
+	rsv = (u8)((value32 & 0x10) >> 4);/*@[4]*/
+
+	PDM_SNPF(out_len, used, output + used, out_len - used, "\r\n %-35s",
+		 "L-SIG");
+	PDM_SNPF(out_len, used, output + used, out_len - used,
+		 "\r\n %-35s = %d M", "rate",
+		 phydm_get_l_sig_rate(dm, (u8)(value32 & 0x0f)));
+
+	PDM_SNPF(out_len, used, output + used, out_len - used,
+		 "\r\n %-35s = %x / %d / %d", "Rsv/length/parity", rsv, length,
+		 parity);
+
+	if (rx_ht == AD_HT_MODE) {
+	/*@ [HT SIG 1] ======================================================*/
+		value32 = odm_get_bb_reg(dm, R_0x2c2c, MASKDWORD);
+
+		hmcss = (u8)(value32 & 0x7F);
+		hrx_bw = (u8)((value32 & 0x80) >> 7);
+		h_length = (u16)((value32 & 0x0fff00) >> 8);
+
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "\r\n %-35s", "HT-SIG1");
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "\r\n %-35s = %d / %d / %d", "MCS/BW/length",
+			 hmcss, hrx_bw, h_length);
+	/*@ [HT SIG 2] ======================================================*/
+		value32 = odm_get_bb_reg(dm, R_0x2c30, MASKDWORD);
+		smooth = (u8)(value32 & 0x01);
+		htsound = (u8)((value32 & 0x02) >> 1);
+		rsv = (u8)((value32 & 0x04) >> 2);
+		agg = (u8)((value32 & 0x08) >> 3);
+		stbc = (u8)((value32 & 0x30) >> 4);
+		fec = (u8)((value32 & 0x40) >> 6);
+		sgi = (u8)((value32 & 0x80) >> 7);
+		htltf = (u8)((value32 & 0x300) >> 8);
+		htcrc8 = (u16)((value32 & 0x3fc00) >> 10);
+		tail = (u8)((value32 & 0xfc0000) >> 18);
+
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "\r\n %-35s",
+			 "HT-SIG2");
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "\r\n %-35s = %x / %x / %x / %x / %x / %x",
+			 "Smooth/NoSound/Rsv/Aggregate/STBC/LDPC",
+			 smooth, htsound, rsv, agg, stbc, fec);
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "\r\n %-35s = %x / %x / %x / %x",
+			 "SGI/E-HT-LTFs/CRC/tail",
+			 sgi, htltf, htcrc8, tail);
+	} else if (rx_ht == AD_VHT_MODE) {
+	/*@ [VHT SIG A1] ====================================================*/
+		value32 = odm_get_bb_reg(dm, R_0x2c2c, MASKDWORD);
+
+		v_rx_bw = (u8)(value32 & 0x03);
+		vrsv = (u8)((value32 & 0x04) >> 2);
+		vstbc = (u8)((value32 & 0x08) >> 3);
+		vgid = (u8)((value32 & 0x3f0) >> 4);
+		v_nsts = (u8)(((value32 & 0x1c00) >> 10) + 1);
+		vpaid = (u16)((value32 & 0x3fe000) >> 13);
+		vtxops = (u8)((value32 & 0x400000) >> 22);
+		vrsv2 = (u8)((value32 & 0x800000) >> 23);
+
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "\r\n %-35s",
+			 "VHT-SIG-A1");
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "\r\n %-35s = %x / %x / %x / %x / %x / %x / %x / %x",
+			 "BW/Rsv1/STBC/GID/Nsts/PAID/TXOPPS/Rsv2", v_rx_bw,
+			 vrsv, vstbc, vgid, v_nsts, vpaid, vtxops, vrsv2);
+
+	/*@ [VHT SIG A2] ====================================================*/
+		value32 = odm_get_bb_reg(dm, R_0x2c30, MASKDWORD);
+
+		/* @sgi=(u8)(value32&0x01); */
+		sgiext = (u8)(value32 & 0x03);
+		/* @fec = (u8)(value32&0x04); */
+		fecext = (u8)((value32 & 0x0C) >> 2);
+
+		v_mcss = (u8)((value32 & 0xf0) >> 4);
+		bf = (u8)((value32 & 0x100) >> 8);
+		vrsv = (u8)((value32 & 0x200) >> 9);
+		vhtcrc8 = (u16)((value32 & 0x3fc00) >> 10);
+		v_tail = (u8)((value32 & 0xfc0000) >> 18);
+
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "\r\n %-35s", "VHT-SIG-A2");
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "\r\n %-35s = %x / %x / %x / %x / %x / %x / %x",
+			 "SGI/FEC/MCS/BF/Rsv/CRC/tail",
+			 sgiext, fecext, v_mcss, bf, vrsv, vhtcrc8, v_tail);
+
+	/*@ [VHT SIG B] ====================================================*/
+		value32 = odm_get_bb_reg(dm, R_0x2c34, MASKDWORD);
+
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "\r\n %-35s", "VHT-SIG-B");
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "\r\n %-35s = %x",
+			 "Codeword", value32);
+
+		if (v_rx_bw == 0) {
+			v_length = (u16)(value32 & 0x1ffff);
+			vbrsv = (u8)((value32 & 0xE0000) >> 17);
+			vb_tail = (u16)((value32 & 0x03F00000) >> 20);
+		} else if (v_rx_bw == 1) {
+			v_length = (u16)(value32 & 0x7FFFF);
+			vbrsv = (u8)((value32 & 180000) >> 19);
+			vb_tail = (u16)((value32 & 0x07E00000) >> 21);
+		} else if (v_rx_bw == 2) {
+			v_length = (u16)(value32 & 0x1fffff);
+			vbrsv = (u8)((value32 & 0x600000) >> 21);
+			vb_tail = (u16)((value32 & 0x1f800000) >> 23);
+		}
+		vbcrc = (u8)((value32 & 0x80000000) >> 31);
+
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "\r\n %-35s = %x / %x / %x / %x",
+			 "length/Rsv/tail/CRC",
+			 v_length, vbrsv, vb_tail, vbcrc);
+	}
+
+	*_used = used;
+	*_out_len = out_len;
+}
+#endif
+
+u8 phydm_get_l_sig_rate(void *dm_void, u8 rate_idx_l_sig)
+{
+	u8 rate_idx = 0xff;
+
+	switch (rate_idx_l_sig) {
+	case 0x0b:
+		rate_idx = 6;
+		break;
+	case 0x0f:
+		rate_idx = 9;
+		break;
+	case 0x0a:
+		rate_idx = 12;
+		break;
+	case 0x0e:
+		rate_idx = 18;
+		break;
+	case 0x09:
+		rate_idx = 24;
+		break;
+	case 0x0d:
+		rate_idx = 36;
+		break;
+	case 0x08:
+		rate_idx = 48;
+		break;
+	case 0x0c:
+		rate_idx = 54;
+		break;
+	default:
+		rate_idx = 0xff;
+		break;
+	}
+
+	return rate_idx;
+}
+
+void phydm_bb_hw_dbg_info(void *dm_void, char input[][16], u32 *_used,
+			  char *output, u32 *_out_len)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	u32 used = *_used;
+	u32 out_len = *_out_len;
+
+	switch (dm->ic_ip_series) {
+	#if (ODM_IC_11N_SERIES_SUPPORT)
+	case PHYDM_IC_N:
+		phydm_bb_hw_dbg_info_n(dm, &used, output, &out_len);
+		break;
+	#endif
+
+	#if (ODM_IC_11AC_SERIES_SUPPORT)
+	case PHYDM_IC_AC:
+		phydm_bb_hw_dbg_info_ac(dm, &used, output, &out_len);
+		phydm_reset_bb_hw_cnt_ac(dm);
+		#if (RTL8822B_SUPPORT)
+		phydm_bb_hw_dbg_info_8822b(dm, &used, output, &out_len);
+		#endif
+		break;
+	#endif
+
+	#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
+	case PHYDM_IC_JGR3:
+		phydm_bb_hw_dbg_info_jgr3(dm, &used, output, &out_len);
+		break;
+	#endif
+	default:
+		break;
+	}
+
+	*_used = used;
+	*_out_len = out_len;
+}
+
+#endif /*@#ifdef CONFIG_PHYDM_DEBUG_FUNCTION*/
+
+#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
+void phydm_basic_dbg_msg_cli_win(void *dm_void, char *buf)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct phydm_fa_struct *fa_t = &dm->false_alm_cnt;
+	struct phydm_cfo_track_struct *cfo_t = &dm->dm_cfo_track;
+	struct odm_phy_dbg_info *dbg = &dm->phy_dbg_info;
+	struct phydm_phystatus_statistic *dbg_s = &dbg->physts_statistic_info;
+	struct phydm_phystatus_avg *dbg_avg = &dbg->phystatus_statistic_avg;
+	u16 macid, phydm_macid, client_cnt = 0;
+	u8 i = 0;
+	u8 rate_num = dm->num_rf_path;
+	u8 ss_ofst = 0;
+	struct cmn_sta_info *entry = NULL;
+	char dbg_buf[PHYDM_SNPRINT_SIZE] = {0};
+
+	RT_SPRINTF(buf, DBGM_CLI_BUF_SIZE, "\r\n PHYDM Common Dbg Msg --------->");
+	RT_PRINT(buf);
+	RT_SPRINTF(buf, DBGM_CLI_BUF_SIZE, "\r\n System up time=%d", dm->phydm_sys_up_time);
+	RT_PRINT(buf);
+
+	if (dm->is_linked) {
+		RT_SPRINTF(buf, DBGM_CLI_BUF_SIZE, "\r\n ID=((%d)), BW=((%d)), fc=((CH-%d))",
+			   dm->curr_station_id, 20 << *dm->band_width, *dm->channel);
+		RT_PRINT(buf);
+
+		if (((*dm->channel <= 14) && (*dm->band_width == CHANNEL_WIDTH_40)) &&
+		    (dm->support_ic_type & ODM_IC_11N_SERIES)) {
+			RT_SPRINTF(buf, DBGM_CLI_BUF_SIZE, "\r\n Primary CCA at ((%s SB))",
+				   (*dm->sec_ch_offset == SECOND_CH_AT_LSB) ? "U" : "L");
+			RT_PRINT(buf);
+		}
+
+		if ((dm->support_ic_type & PHYSTS_2ND_TYPE_IC) || dm->rx_rate > ODM_RATE11M) {
+			RT_SPRINTF(buf, DBGM_CLI_BUF_SIZE, "\r\n [AGC Idx] {0x%x, 0x%x, 0x%x, 0x%x}",
+				   dm->ofdm_agc_idx[0], dm->ofdm_agc_idx[1],
+				   dm->ofdm_agc_idx[2], dm->ofdm_agc_idx[3]);
+			RT_PRINT(buf);
+		} else {
+			RT_SPRINTF(buf, DBGM_CLI_BUF_SIZE, "\r\n [CCK AGC Idx] {LNA,VGA}={0x%x, 0x%x}",
+				   dm->cck_lna_idx, dm->cck_vga_idx);
+			RT_PRINT(buf);
+		}
+
+		phydm_print_rate_2_buff(dm, dm->rx_rate, dbg_buf, PHYDM_SNPRINT_SIZE);
+		RT_SPRINTF(buf, DBGM_CLI_BUF_SIZE, "\r\n RSSI:{%d, %d, %d, %d}, RxRate:%s (0x%x)",
+			   (dm->rssi_a == 0xff) ? 0 : dm->rssi_a,
+			   (dm->rssi_b == 0xff) ? 0 : dm->rssi_b,
+			   (dm->rssi_c == 0xff) ? 0 : dm->rssi_c,
+			   (dm->rssi_d == 0xff) ? 0 : dm->rssi_d,
+			  dbg_buf, dm->rx_rate);
+		RT_PRINT(buf);
+
+		phydm_print_rate_2_buff(dm, dm->phy_dbg_info.beacon_phy_rate, dbg_buf, PHYDM_SNPRINT_SIZE);
+		RT_SPRINTF(buf, DBGM_CLI_BUF_SIZE, "\r\n Beacon_cnt=%d, rate_idx:%s (0x%x)",
+			   dm->phy_dbg_info.beacon_cnt_in_period,
+			   dbg_buf,
+			   dm->phy_dbg_info.beacon_phy_rate);
+		RT_PRINT(buf);
+
+		/*Show phydm_rx_rate_distribution;*/
+		RT_SPRINTF(buf, DBGM_CLI_BUF_SIZE, "\r\n [RxRate Cnt] =============>");
+		RT_PRINT(buf);
+
+		/*@======CCK=================================================*/
+		if (*dm->channel <= 14) {
+			RT_SPRINTF(buf, DBGM_CLI_BUF_SIZE, "\r\n * CCK = {%d, %d, %d, %d}",
+				   dbg->num_qry_legacy_pkt[0], dbg->num_qry_legacy_pkt[1],
+				   dbg->num_qry_legacy_pkt[2], dbg->num_qry_legacy_pkt[3]);
+			RT_PRINT(buf);
+		}
+		/*@======OFDM================================================*/
+		RT_SPRINTF(buf, DBGM_CLI_BUF_SIZE, "\r\n * OFDM = {%d, %d, %d, %d, %d, %d, %d, %d}",
+			   dbg->num_qry_legacy_pkt[4], dbg->num_qry_legacy_pkt[5],
+			   dbg->num_qry_legacy_pkt[6], dbg->num_qry_legacy_pkt[7],
+			   dbg->num_qry_legacy_pkt[8], dbg->num_qry_legacy_pkt[9],
+			   dbg->num_qry_legacy_pkt[10], dbg->num_qry_legacy_pkt[11]);
+		RT_PRINT(buf);
+
+		/*@======HT==================================================*/
+		if (dbg->ht_pkt_not_zero) {
+			for (i = 0; i < rate_num; i++) {
+				ss_ofst = (i << 3);
+
+				RT_SPRINTF(buf, DBGM_CLI_BUF_SIZE, "\r\n * HT MCS[%d :%d ] = {%d, %d, %d, %d, %d, %d, %d, %d}",
+					   (ss_ofst), (ss_ofst + 7),
+					   dbg->num_qry_ht_pkt[ss_ofst + 0], dbg->num_qry_ht_pkt[ss_ofst + 1],
+					   dbg->num_qry_ht_pkt[ss_ofst + 2], dbg->num_qry_ht_pkt[ss_ofst + 3],
+					   dbg->num_qry_ht_pkt[ss_ofst + 4], dbg->num_qry_ht_pkt[ss_ofst + 5],
+					   dbg->num_qry_ht_pkt[ss_ofst + 6], dbg->num_qry_ht_pkt[ss_ofst + 7]);
+				RT_PRINT(buf);
+			}
+
+			if (dbg->low_bw_20_occur) {
+				for (i = 0; i < rate_num; i++) {
+					ss_ofst = (i << 3);
+
+					RT_SPRINTF(buf, DBGM_CLI_BUF_SIZE, "\r\n * [Low BW 20M] HT MCS[%d :%d ] = {%d, %d, %d, %d, %d, %d, %d, %d}",
+						   (ss_ofst), (ss_ofst + 7),
+						   dbg->num_qry_pkt_sc_20m[ss_ofst + 0], dbg->num_qry_pkt_sc_20m[ss_ofst + 1],
+						   dbg->num_qry_pkt_sc_20m[ss_ofst + 2], dbg->num_qry_pkt_sc_20m[ss_ofst + 3],
+						   dbg->num_qry_pkt_sc_20m[ss_ofst + 4], dbg->num_qry_pkt_sc_20m[ss_ofst + 5],
+						   dbg->num_qry_pkt_sc_20m[ss_ofst + 6], dbg->num_qry_pkt_sc_20m[ss_ofst + 7]);
+					RT_PRINT(buf);
+				}
+			}
+		}
+
+		#if ODM_IC_11AC_SERIES_SUPPORT
+		/*@======VHT=================================================*/
+		if (dbg->vht_pkt_not_zero) {
+			for (i = 0; i < rate_num; i++) {
+				ss_ofst = 10 * i;
+
+				RT_SPRINTF(buf, DBGM_CLI_BUF_SIZE, "\r\n * VHT-%d ss MCS[0:9] = {%d, %d, %d, %d, %d, %d, %d, %d, %d, %d}",
+					   (i + 1),
+					   dbg->num_qry_vht_pkt[ss_ofst + 0], dbg->num_qry_vht_pkt[ss_ofst + 1],
+					   dbg->num_qry_vht_pkt[ss_ofst + 2], dbg->num_qry_vht_pkt[ss_ofst + 3],
+					   dbg->num_qry_vht_pkt[ss_ofst + 4], dbg->num_qry_vht_pkt[ss_ofst + 5],
+					   dbg->num_qry_vht_pkt[ss_ofst + 6], dbg->num_qry_vht_pkt[ss_ofst + 7],
+					   dbg->num_qry_vht_pkt[ss_ofst + 8], dbg->num_qry_vht_pkt[ss_ofst + 9]);
+				RT_PRINT(buf);
+			}
+
+			if (dbg->low_bw_20_occur) {
+				for (i = 0; i < rate_num; i++) {
+					ss_ofst = 10 * i;
+
+					RT_SPRINTF(buf, DBGM_CLI_BUF_SIZE, "\r\n *[Low BW 20M] VHT-%d ss MCS[0:9] = {%d, %d, %d, %d, %d, %d, %d, %d, %d, %d}",
+						   (i + 1),
+						   dbg->num_qry_pkt_sc_20m[ss_ofst + 0], dbg->num_qry_pkt_sc_20m[ss_ofst + 1],
+						   dbg->num_qry_pkt_sc_20m[ss_ofst + 2], dbg->num_qry_pkt_sc_20m[ss_ofst + 3],
+						   dbg->num_qry_pkt_sc_20m[ss_ofst + 4], dbg->num_qry_pkt_sc_20m[ss_ofst + 5],
+						   dbg->num_qry_pkt_sc_20m[ss_ofst + 6], dbg->num_qry_pkt_sc_20m[ss_ofst + 7],
+						   dbg->num_qry_pkt_sc_20m[ss_ofst + 8], dbg->num_qry_pkt_sc_20m[ss_ofst + 9]);
+					RT_PRINT(buf);
+				}
+			}
+
+			if (dbg->low_bw_40_occur) {
+				for (i = 0; i < rate_num; i++) {
+					ss_ofst = 10 * i;
+
+					RT_SPRINTF(buf, DBGM_CLI_BUF_SIZE, "\r\n *[Low BW 40M] VHT-%d ss MCS[0:9] = {%d, %d, %d, %d, %d, %d, %d, %d, %d, %d}",
+						   (i + 1),
+						   dbg->num_qry_pkt_sc_40m[ss_ofst + 0], dbg->num_qry_pkt_sc_40m[ss_ofst + 1],
+						   dbg->num_qry_pkt_sc_40m[ss_ofst + 2], dbg->num_qry_pkt_sc_40m[ss_ofst + 3],
+						   dbg->num_qry_pkt_sc_40m[ss_ofst + 4], dbg->num_qry_pkt_sc_40m[ss_ofst + 5],
+						   dbg->num_qry_pkt_sc_40m[ss_ofst + 6], dbg->num_qry_pkt_sc_40m[ss_ofst + 7],
+						   dbg->num_qry_pkt_sc_40m[ss_ofst + 8], dbg->num_qry_pkt_sc_40m[ss_ofst + 9]);
+					RT_PRINT(buf);
+				}
+			}
+		}
+		#endif
+
+		phydm_reset_rx_rate_distribution(dm);
+
+		//1 Show phydm_avg_phystatus_val
+		RT_SPRINTF(buf, DBGM_CLI_BUF_SIZE, "\r\n [Avg PHY Statistic] ==============>");
+		RT_PRINT(buf);
+
+		phydm_reset_phystatus_avg(dm);
+
+		/*@CCK*/
+		dbg_avg->rssi_cck_avg = (u8)((dbg_s->rssi_cck_cnt != 0) ? (dbg_s->rssi_cck_sum / dbg_s->rssi_cck_cnt) : 0);
+		RT_SPRINTF(buf, DBGM_CLI_BUF_SIZE, "\r\n * cck Cnt= ((%d)) RSSI:{%d}",
+			   dbg_s->rssi_cck_cnt, dbg_avg->rssi_cck_avg);
+		RT_PRINT(buf);
+
+		/*OFDM*/
+		if (dbg_s->rssi_ofdm_cnt != 0) {
+			dbg_avg->rssi_ofdm_avg = (u8)(dbg_s->rssi_ofdm_sum / dbg_s->rssi_ofdm_cnt);
+			dbg_avg->evm_ofdm_avg = (u8)(dbg_s->evm_ofdm_sum / dbg_s->rssi_ofdm_cnt);
+			dbg_avg->snr_ofdm_avg = (u8)(dbg_s->snr_ofdm_sum / dbg_s->rssi_ofdm_cnt);
+		}
+
+		RT_SPRINTF(buf, DBGM_CLI_BUF_SIZE, "\r\n * ofdm Cnt= ((%d)) RSSI:{%d} EVM:{%d} SNR:{%d}",
+			   dbg_s->rssi_ofdm_cnt, dbg_avg->rssi_ofdm_avg,
+			   dbg_avg->evm_ofdm_avg, dbg_avg->snr_ofdm_avg);
+		RT_PRINT(buf);
+
+		if (dbg_s->rssi_1ss_cnt != 0) {
+			dbg_avg->rssi_1ss_avg = (u8)(dbg_s->rssi_1ss_sum / dbg_s->rssi_1ss_cnt);
+			dbg_avg->evm_1ss_avg = (u8)(dbg_s->evm_1ss_sum / dbg_s->rssi_1ss_cnt);
+			dbg_avg->snr_1ss_avg = (u8)(dbg_s->snr_1ss_sum / dbg_s->rssi_1ss_cnt);
+		}
+
+		RT_SPRINTF(buf, DBGM_CLI_BUF_SIZE, "\r\n * 1-ss Cnt= ((%d)) RSSI:{%d} EVM:{%d} SNR:{%d}",
+			   dbg_s->rssi_1ss_cnt, dbg_avg->rssi_1ss_avg,
+			   dbg_avg->evm_1ss_avg, dbg_avg->snr_1ss_avg);
+		RT_PRINT(buf);
+
+#if (defined(PHYDM_COMPILE_ABOVE_2SS))
+		if (dm->support_ic_type & (PHYDM_IC_ABOVE_2SS)) {
+			if (dbg_s->rssi_2ss_cnt != 0) {
+				dbg_avg->rssi_2ss_avg[0] = (u8)(dbg_s->rssi_2ss_sum[0] / dbg_s->rssi_2ss_cnt);
+				dbg_avg->rssi_2ss_avg[1] = (u8)(dbg_s->rssi_2ss_sum[1] / dbg_s->rssi_2ss_cnt);
+
+				dbg_avg->evm_2ss_avg[0] = (u8)(dbg_s->evm_2ss_sum[0] / dbg_s->rssi_2ss_cnt);
+				dbg_avg->evm_2ss_avg[1] = (u8)(dbg_s->evm_2ss_sum[1] / dbg_s->rssi_2ss_cnt);
+
+				dbg_avg->snr_2ss_avg[0] = (u8)(dbg_s->snr_2ss_sum[0] / dbg_s->rssi_2ss_cnt);
+				dbg_avg->snr_2ss_avg[1] = (u8)(dbg_s->snr_2ss_sum[1] / dbg_s->rssi_2ss_cnt);
+			}
+
+			RT_SPRINTF(buf, DBGM_CLI_BUF_SIZE, "\r\n * 2-ss Cnt= ((%d)) RSSI:{%d, %d}, EVM:{%d, %d}, SNR:{%d, %d}",
+				   dbg_s->rssi_2ss_cnt, dbg_avg->rssi_2ss_avg[0],
+				   dbg_avg->rssi_2ss_avg[1], dbg_avg->evm_2ss_avg[0],
+				   dbg_avg->evm_2ss_avg[1], dbg_avg->snr_2ss_avg[0],
+				   dbg_avg->snr_2ss_avg[1]);
+			RT_PRINT(buf);
+		}
+#endif
+
+#if (defined(PHYDM_COMPILE_ABOVE_3SS))
+		if (dm->support_ic_type & (PHYDM_IC_ABOVE_3SS)) {
+			if (dbg_s->rssi_3ss_cnt != 0) {
+				dbg_avg->rssi_3ss_avg[0] = (u8)(dbg_s->rssi_3ss_sum[0] / dbg_s->rssi_3ss_cnt);
+				dbg_avg->rssi_3ss_avg[1] = (u8)(dbg_s->rssi_3ss_sum[1] / dbg_s->rssi_3ss_cnt);
+				dbg_avg->rssi_3ss_avg[2] = (u8)(dbg_s->rssi_3ss_sum[2] / dbg_s->rssi_3ss_cnt);
+
+				dbg_avg->evm_3ss_avg[0] = (u8)(dbg_s->evm_3ss_sum[0] / dbg_s->rssi_3ss_cnt);
+				dbg_avg->evm_3ss_avg[1] = (u8)(dbg_s->evm_3ss_sum[1] / dbg_s->rssi_3ss_cnt);
+				dbg_avg->evm_3ss_avg[2] = (u8)(dbg_s->evm_3ss_sum[2] / dbg_s->rssi_3ss_cnt);
+
+				dbg_avg->snr_3ss_avg[0] = (u8)(dbg_s->snr_3ss_sum[0] / dbg_s->rssi_3ss_cnt);
+				dbg_avg->snr_3ss_avg[1] = (u8)(dbg_s->snr_3ss_sum[1] / dbg_s->rssi_3ss_cnt);
+				dbg_avg->snr_3ss_avg[2] = (u8)(dbg_s->snr_3ss_sum[2] / dbg_s->rssi_3ss_cnt);
+			}
+
+			RT_SPRINTF(buf, DBGM_CLI_BUF_SIZE, "\r\n * 3-ss Cnt= ((%d)) RSSI:{%d, %d, %d} EVM:{%d, %d, %d} SNR:{%d, %d, %d}",
+				   dbg_s->rssi_3ss_cnt, dbg_avg->rssi_3ss_avg[0],
+				   dbg_avg->rssi_3ss_avg[1], dbg_avg->rssi_3ss_avg[2],
+				   dbg_avg->evm_3ss_avg[0], dbg_avg->evm_3ss_avg[1],
+				   dbg_avg->evm_3ss_avg[2], dbg_avg->snr_3ss_avg[0],
+				   dbg_avg->snr_3ss_avg[1], dbg_avg->snr_3ss_avg[2]);
+			RT_PRINT(buf);
+		}
+#endif
+
+#if (defined(PHYDM_COMPILE_ABOVE_4SS))
+		if (dm->support_ic_type & PHYDM_IC_ABOVE_4SS) {
+			if (dbg_s->rssi_4ss_cnt != 0) {
+				dbg_avg->rssi_4ss_avg[0] = (u8)(dbg_s->rssi_4ss_sum[0] / dbg_s->rssi_4ss_cnt);
+				dbg_avg->rssi_4ss_avg[1] = (u8)(dbg_s->rssi_4ss_sum[1] / dbg_s->rssi_4ss_cnt);
+				dbg_avg->rssi_4ss_avg[2] = (u8)(dbg_s->rssi_4ss_sum[2] / dbg_s->rssi_4ss_cnt);
+				dbg_avg->rssi_4ss_avg[3] = (u8)(dbg_s->rssi_4ss_sum[3] / dbg_s->rssi_4ss_cnt);
+
+				dbg_avg->evm_4ss_avg[0] = (u8)(dbg_s->evm_4ss_sum[0] / dbg_s->rssi_4ss_cnt);
+				dbg_avg->evm_4ss_avg[1] = (u8)(dbg_s->evm_4ss_sum[1] / dbg_s->rssi_4ss_cnt);
+				dbg_avg->evm_4ss_avg[2] = (u8)(dbg_s->evm_4ss_sum[2] / dbg_s->rssi_4ss_cnt);
+				dbg_avg->evm_4ss_avg[3] = (u8)(dbg_s->evm_4ss_sum[3] / dbg_s->rssi_4ss_cnt);
+
+				dbg_avg->snr_4ss_avg[0] = (u8)(dbg_s->snr_4ss_sum[0] / dbg_s->rssi_4ss_cnt);
+				dbg_avg->snr_4ss_avg[1] = (u8)(dbg_s->snr_4ss_sum[1] / dbg_s->rssi_4ss_cnt);
+				dbg_avg->snr_4ss_avg[2] = (u8)(dbg_s->snr_4ss_sum[2] / dbg_s->rssi_4ss_cnt);
+				dbg_avg->snr_4ss_avg[3] = (u8)(dbg_s->snr_4ss_sum[3] / dbg_s->rssi_4ss_cnt);
+			}
+
+			RT_SPRINTF(buf, DBGM_CLI_BUF_SIZE, "\r\n * 4-ss Cnt= ((%d)) RSSI:{%d, %d, %d, %d} EVM:{%d, %d, %d, %d} SNR:{%d, %d, %d, %d}",
+				   dbg_s->rssi_4ss_cnt, dbg_avg->rssi_4ss_avg[0],
+				   dbg_avg->rssi_4ss_avg[1], dbg_avg->rssi_4ss_avg[2],
+				   dbg_avg->rssi_4ss_avg[3], dbg_avg->evm_4ss_avg[0],
+				   dbg_avg->evm_4ss_avg[1], dbg_avg->evm_4ss_avg[2],
+				   dbg_avg->evm_4ss_avg[3], dbg_avg->snr_4ss_avg[0],
+				   dbg_avg->snr_4ss_avg[1], dbg_avg->snr_4ss_avg[2],
+				   dbg_avg->snr_4ss_avg[3]);
+			RT_PRINT(buf);
+		}
+#endif
+		phydm_reset_phystatus_statistic(dm);
+		/*@----------------------------------------------------------*/
+
+		/*Print TX rate*/
+		for (macid = 0; macid < ODM_ASSOCIATE_ENTRY_NUM; macid++) {
+			entry = dm->phydm_sta_info[macid];
+
+			if (!is_sta_active(entry))
+				continue;
+
+			phydm_macid = (dm->phydm_macid_table[macid]);
+			phydm_print_rate_2_buff(dm, entry->ra_info.curr_tx_rate, dbg_buf, PHYDM_SNPRINT_SIZE);
+			RT_SPRINTF(buf, DBGM_CLI_BUF_SIZE, "\r\n TxRate[%d]=%s (0x%x)", macid, dbg_buf, entry->ra_info.curr_tx_rate);
+			RT_PRINT(buf);
+
+			client_cnt++;
+
+			if (client_cnt >= dm->number_linked_client)
+				break;
+		}
+
+		RT_SPRINTF(buf, DBGM_CLI_BUF_SIZE,
+			   "\r\n TP {Tx, Rx, Total} = {%d, %d, %d}Mbps, Traffic_Load=(%d))",
+			   dm->tx_tp, dm->rx_tp, dm->total_tp, dm->traffic_load);
+		RT_PRINT(buf);
+
+		RT_SPRINTF(buf, DBGM_CLI_BUF_SIZE, "\r\n CFO_avg=((%d kHz)), CFO_traking = ((%s%d))",
+			   cfo_t->CFO_ave_pre,
+			   ((cfo_t->crystal_cap > cfo_t->def_x_cap) ? "+" : "-"),
+			   DIFF_2(cfo_t->crystal_cap, cfo_t->def_x_cap));
+		RT_PRINT(buf);
+
+		/* @Condition number */
+		#if (RTL8822B_SUPPORT)
+		if (dm->support_ic_type == ODM_RTL8822B) {
+			RT_SPRINTF(buf, DBGM_CLI_BUF_SIZE, "\r\n Condi_Num=((%d.%.4d))",
+				   dm->phy_dbg_info.condi_num >> 4,
+				   phydm_show_fraction_num(dm->phy_dbg_info.condi_num & 0xf, 4));
+			RT_PRINT(buf);
+		}
+		#endif
+
+		#if (ODM_PHY_STATUS_NEW_TYPE_SUPPORT)
+		/*STBC or LDPC pkt*/
+		if (dm->support_ic_type & PHYSTS_2ND_TYPE_IC)
+			RT_SPRINTF(buf, DBGM_CLI_BUF_SIZE, "\r\n Coding: LDPC=((%s)), STBC=((%s))",
+				   (dm->phy_dbg_info.is_ldpc_pkt) ? "Y" : "N",
+				   (dm->phy_dbg_info.is_stbc_pkt) ? "Y" : "N");
+			RT_PRINT(buf);
+		#endif
+
+	} else {
+		RT_SPRINTF(buf, DBGM_CLI_BUF_SIZE, "\r\n No Link !!!");
+		RT_PRINT(buf);
+	}
+
+	RT_SPRINTF(buf, DBGM_CLI_BUF_SIZE, "\r\n [CCA Cnt] {CCK, OFDM, Total} = {%d, %d, %d}",
+		   fa_t->cnt_cck_cca, fa_t->cnt_ofdm_cca, fa_t->cnt_cca_all);
+	RT_PRINT(buf);
+
+	RT_SPRINTF(buf, DBGM_CLI_BUF_SIZE, "\r\n [FA Cnt] {CCK, OFDM, Total} = {%d, %d, %d}",
+		   fa_t->cnt_cck_fail, fa_t->cnt_ofdm_fail, fa_t->cnt_all);
+	RT_PRINT(buf);
+
+	#if (ODM_IC_11N_SERIES_SUPPORT)
+	if (dm->support_ic_type & ODM_IC_11N_SERIES) {
+		RT_SPRINTF(buf, DBGM_CLI_BUF_SIZE,
+			   "\r\n [OFDM FA Detail] Parity_Fail=%d, Rate_Illegal=%d, CRC8=%d, MCS_fail=%d, Fast_sync=%d, SB_Search_fail=%d",
+			   fa_t->cnt_parity_fail, fa_t->cnt_rate_illegal,
+			   fa_t->cnt_crc8_fail, fa_t->cnt_mcs_fail,
+			   fa_t->cnt_fast_fsync, fa_t->cnt_sb_search_fail);
+		RT_PRINT(buf);
+	}
+	#endif
+	RT_SPRINTF(buf, DBGM_CLI_BUF_SIZE,
+		   "\r\n is_linked = %d, Num_client = %d, rssi_min = %d, IGI = 0x%x, bNoisy=%d",
+		   dm->is_linked, dm->number_linked_client, dm->rssi_min,
+		   dm->dm_dig_table.cur_ig_value, dm->noisy_decision);
+	RT_PRINT(buf);
+}
+
+#ifdef CONFIG_PHYDM_DEBUG_FUNCTION
+void phydm_sbd_check(
+	struct dm_struct *dm)
+{
+	static u32 pkt_cnt;
+	static boolean sbd_state;
+	u32 sym_count, count, value32;
+
+	if (sbd_state == 0) {
+		pkt_cnt++;
+		/*read SBD conter once every 5 packets*/
+		if (pkt_cnt % 5 == 0) {
+			odm_set_timer(dm, &dm->sbdcnt_timer, 0); /*@ms*/
+			sbd_state = 1;
+		}
+	} else { /*read counter*/
+		value32 = odm_get_bb_reg(dm, R_0xf98, MASKDWORD);
+		sym_count = (value32 & 0x7C000000) >> 26;
+		count = (value32 & 0x3F00000) >> 20;
+		pr_debug("#SBD# sym_count %d count %d\n", sym_count, count);
+		sbd_state = 0;
+	}
+}
+#endif
+
+void phydm_sbd_callback(
+	struct phydm_timer_list *timer)
+{
+#ifdef CONFIG_PHYDM_DEBUG_FUNCTION
+	void *adapter = timer->Adapter;
+	HAL_DATA_TYPE *hal_data = GET_HAL_DATA((PADAPTER)adapter);
+	struct dm_struct *dm = &hal_data->DM_OutSrc;
+
+#if USE_WORKITEM
+	odm_schedule_work_item(&dm->sbdcnt_workitem);
+#else
+	phydm_sbd_check(dm);
+#endif
+#endif
+}
+
+void phydm_sbd_workitem_callback(
+	void *context)
+{
+#ifdef CONFIG_PHYDM_DEBUG_FUNCTION
+	void *adapter = (void *)context;
+	HAL_DATA_TYPE *hal_data = GET_HAL_DATA((PADAPTER)adapter);
+	struct dm_struct *dm = &hal_data->DM_OutSrc;
+
+	phydm_sbd_check(dm);
+#endif
+}
+#endif
+
+void phydm_reset_rx_rate_distribution(struct dm_struct *dm)
+{
+	struct odm_phy_dbg_info *dbg = &dm->phy_dbg_info;
+
+	odm_memory_set(dm, &dbg->num_qry_legacy_pkt[0], 0,
+		       (LEGACY_RATE_NUM * 2));
+	odm_memory_set(dm, &dbg->num_qry_ht_pkt[0], 0,
+		       (HT_RATE_NUM * 2));
+	odm_memory_set(dm, &dbg->num_qry_pkt_sc_20m[0], 0,
+		       (LOW_BW_RATE_NUM * 2));
+
+	dbg->ht_pkt_not_zero = false;
+	dbg->low_bw_20_occur = false;
+
+#if ODM_IC_11AC_SERIES_SUPPORT
+	odm_memory_set(dm, &dbg->num_qry_vht_pkt[0], 0, VHT_RATE_NUM * 2);
+	odm_memory_set(dm, &dbg->num_qry_pkt_sc_40m[0], 0, LOW_BW_RATE_NUM * 2);
+	#if (ODM_PHY_STATUS_NEW_TYPE_SUPPORT == 1) || (defined(PHYSTS_3RD_TYPE_SUPPORT))
+	odm_memory_set(dm, &dbg->num_mu_vht_pkt[0], 0, VHT_RATE_NUM * 2);
+	#endif
+	dbg->vht_pkt_not_zero = false;
+	dbg->low_bw_40_occur = false;
+#endif
+}
+
+void phydm_rx_rate_distribution(void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct odm_phy_dbg_info *dbg = &dm->phy_dbg_info;
+	u8 i = 0;
+	u8 rate_num = dm->num_rf_path, ss_ofst = 0;
+
+	PHYDM_DBG(dm, DBG_CMN, "[RxRate Cnt] =============>\n");
+
+	/*@======CCK=========================================================*/
+	if (*dm->channel <= 14) {
+		PHYDM_DBG(dm, DBG_CMN, "* CCK = {%d, %d, %d, %d}\n",
+			  dbg->num_qry_legacy_pkt[0],
+			  dbg->num_qry_legacy_pkt[1],
+			  dbg->num_qry_legacy_pkt[2],
+			  dbg->num_qry_legacy_pkt[3]);
+	}
+	/*@======OFDM========================================================*/
+	PHYDM_DBG(dm, DBG_CMN, "* OFDM = {%d, %d, %d, %d, %d, %d, %d, %d}\n",
+		  dbg->num_qry_legacy_pkt[4], dbg->num_qry_legacy_pkt[5],
+		  dbg->num_qry_legacy_pkt[6], dbg->num_qry_legacy_pkt[7],
+		  dbg->num_qry_legacy_pkt[8], dbg->num_qry_legacy_pkt[9],
+		  dbg->num_qry_legacy_pkt[10], dbg->num_qry_legacy_pkt[11]);
+
+	/*@======HT==========================================================*/
+	if (dbg->ht_pkt_not_zero) {
+		for (i = 0; i < rate_num; i++) {
+			ss_ofst = (i << 3);
+
+			PHYDM_DBG(dm, DBG_CMN,
+				  "* HT MCS[%d :%d ] = {%d, %d, %d, %d, %d, %d, %d, %d}\n",
+				  (ss_ofst), (ss_ofst + 7),
+				  dbg->num_qry_ht_pkt[ss_ofst + 0],
+				  dbg->num_qry_ht_pkt[ss_ofst + 1],
+				  dbg->num_qry_ht_pkt[ss_ofst + 2],
+				  dbg->num_qry_ht_pkt[ss_ofst + 3],
+				  dbg->num_qry_ht_pkt[ss_ofst + 4],
+				  dbg->num_qry_ht_pkt[ss_ofst + 5],
+				  dbg->num_qry_ht_pkt[ss_ofst + 6],
+				  dbg->num_qry_ht_pkt[ss_ofst + 7]);
+		}
+
+		if (dbg->low_bw_20_occur) {
+			for (i = 0; i < rate_num; i++) {
+				ss_ofst = (i << 3);
+
+				PHYDM_DBG(dm, DBG_CMN,
+					  "* [Low BW 20M] HT MCS[%d :%d ] = {%d, %d, %d, %d, %d, %d, %d, %d}\n",
+					  (ss_ofst), (ss_ofst + 7),
+					  dbg->num_qry_pkt_sc_20m[ss_ofst + 0],
+					  dbg->num_qry_pkt_sc_20m[ss_ofst + 1],
+					  dbg->num_qry_pkt_sc_20m[ss_ofst + 2],
+					  dbg->num_qry_pkt_sc_20m[ss_ofst + 3],
+					  dbg->num_qry_pkt_sc_20m[ss_ofst + 4],
+					  dbg->num_qry_pkt_sc_20m[ss_ofst + 5],
+					  dbg->num_qry_pkt_sc_20m[ss_ofst + 6],
+					  dbg->num_qry_pkt_sc_20m[ss_ofst + 7]);
+			}
+		}
+	}
+
+#if ODM_IC_11AC_SERIES_SUPPORT
+	/*@======VHT==========================================================*/
+	if (dbg->vht_pkt_not_zero) {
+		for (i = 0; i < rate_num; i++) {
+			ss_ofst = 10 * i;
+
+			PHYDM_DBG(dm, DBG_CMN,
+				  "* VHT-%d ss MCS[0:9] = {%d, %d, %d, %d, %d, %d, %d, %d, %d, %d}\n",
+				  (i + 1),
+				  dbg->num_qry_vht_pkt[ss_ofst + 0],
+				  dbg->num_qry_vht_pkt[ss_ofst + 1],
+				  dbg->num_qry_vht_pkt[ss_ofst + 2],
+				  dbg->num_qry_vht_pkt[ss_ofst + 3],
+				  dbg->num_qry_vht_pkt[ss_ofst + 4],
+				  dbg->num_qry_vht_pkt[ss_ofst + 5],
+				  dbg->num_qry_vht_pkt[ss_ofst + 6],
+				  dbg->num_qry_vht_pkt[ss_ofst + 7],
+				  dbg->num_qry_vht_pkt[ss_ofst + 8],
+				  dbg->num_qry_vht_pkt[ss_ofst + 9]);
+		}
+
+		if (dbg->low_bw_20_occur) {
+			for (i = 0; i < rate_num; i++) {
+				ss_ofst = 10 * i;
+
+				PHYDM_DBG(dm, DBG_CMN,
+					  "*[Low BW 20M] VHT-%d ss MCS[0:9] = {%d, %d, %d, %d, %d, %d, %d, %d, %d, %d}\n",
+					  (i + 1),
+					  dbg->num_qry_pkt_sc_20m[ss_ofst + 0],
+					  dbg->num_qry_pkt_sc_20m[ss_ofst + 1],
+					  dbg->num_qry_pkt_sc_20m[ss_ofst + 2],
+					  dbg->num_qry_pkt_sc_20m[ss_ofst + 3],
+					  dbg->num_qry_pkt_sc_20m[ss_ofst + 4],
+					  dbg->num_qry_pkt_sc_20m[ss_ofst + 5],
+					  dbg->num_qry_pkt_sc_20m[ss_ofst + 6],
+					  dbg->num_qry_pkt_sc_20m[ss_ofst + 7],
+					  dbg->num_qry_pkt_sc_20m[ss_ofst + 8],
+					  dbg->num_qry_pkt_sc_20m[ss_ofst + 9]);
+			}
+		}
+
+		if (dbg->low_bw_40_occur) {
+			for (i = 0; i < rate_num; i++) {
+				ss_ofst = 10 * i;
+
+				PHYDM_DBG(dm, DBG_CMN,
+					  "*[Low BW 40M] VHT-%d ss MCS[0:9] = {%d, %d, %d, %d, %d, %d, %d, %d, %d, %d}\n",
+					  (i + 1),
+					  dbg->num_qry_pkt_sc_40m[ss_ofst + 0],
+					  dbg->num_qry_pkt_sc_40m[ss_ofst + 1],
+					  dbg->num_qry_pkt_sc_40m[ss_ofst + 2],
+					  dbg->num_qry_pkt_sc_40m[ss_ofst + 3],
+					  dbg->num_qry_pkt_sc_40m[ss_ofst + 4],
+					  dbg->num_qry_pkt_sc_40m[ss_ofst + 5],
+					  dbg->num_qry_pkt_sc_40m[ss_ofst + 6],
+					  dbg->num_qry_pkt_sc_40m[ss_ofst + 7],
+					  dbg->num_qry_pkt_sc_40m[ss_ofst + 8],
+					  dbg->num_qry_pkt_sc_40m[ss_ofst + 9]);
+			}
+		}
+	}
+#endif
+}
+
+void phydm_print_hist_2_buf(void *dm_void, u16 *val, u16 len, char *buf,
+			    u16 buf_size)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+
+	if (len == PHY_HIST_SIZE) {
+		PHYDM_SNPRINTF(buf, buf_size,
+			       "[%.2d, %.2d, %.2d, %.2d, %.2d, %.2d, %.2d, %.2d, %.2d, %.2d, %.2d, %.2d]",
+			       val[0], val[1], val[2], val[3], val[4],
+			       val[5], val[6], val[7], val[8], val[9],
+			       val[10], val[11]);
+	} else if (len == (PHY_HIST_SIZE - 1)) {
+		PHYDM_SNPRINTF(buf, buf_size,
+			       "[%.2d, %.2d, %.2d, %.2d, %.2d, %.2d, %.2d, %.2d, %.2d, %.2d, %.2d]",
+			       val[0], val[1], val[2], val[3], val[4],
+			       val[5], val[6], val[7], val[8], val[9],
+			       val[10]);
+	}
+}
+
+void phydm_nss_hitogram(void *dm_void, enum PDM_RATE_TYPE rate_type)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct odm_phy_dbg_info *dbg_i = &dm->phy_dbg_info;
+	struct phydm_phystatus_statistic *dbg_s = &dbg_i->physts_statistic_info;
+	char buf[PHYDM_SNPRINT_SIZE] = {0};
+	u16 buf_size = PHYDM_SNPRINT_SIZE;
+	u16 h_size = PHY_HIST_SIZE;
+	u16 *evm_hist = NULL, *snr_hist = NULL;
+	u8 i = 0;
+	u8 ss = phydm_rate_type_2_num_ss(dm, rate_type);
+
+	for (i = 0; i < ss; i++) {
+		if (rate_type == PDM_1SS) {
+			evm_hist = &dbg_s->evm_1ss_hist[0];
+			snr_hist = &dbg_s->snr_1ss_hist[0];
+		} else if (rate_type == PDM_2SS) {
+			#if (defined(PHYDM_COMPILE_ABOVE_2SS))
+			evm_hist = &dbg_s->evm_2ss_hist[i][0];
+			snr_hist = &dbg_s->snr_2ss_hist[i][0];
+			#endif
+		} else if (rate_type == PDM_3SS) {
+			#if (defined(PHYDM_COMPILE_ABOVE_3SS))
+			evm_hist = &dbg_s->evm_3ss_hist[i][0];
+			snr_hist = &dbg_s->snr_3ss_hist[i][0];
+			#endif
+		} else if (rate_type == PDM_4SS) {
+			#if (defined(PHYDM_COMPILE_ABOVE_4SS))
+			evm_hist = &dbg_s->evm_4ss_hist[i][0];
+			snr_hist = &dbg_s->snr_4ss_hist[i][0];
+			#endif
+		}
+
+		phydm_print_hist_2_buf(dm, evm_hist, h_size, buf, buf_size);
+		PHYDM_DBG(dm, DBG_CMN, "[%d-SS][EVM][%d]=%s\n", ss, i, buf);
+		phydm_print_hist_2_buf(dm, snr_hist, h_size, buf, buf_size);
+		PHYDM_DBG(dm, DBG_CMN, "[%d-SS][SNR][%d]=%s\n",  ss, i, buf);
+	}
+}
+
+void phydm_show_phy_hitogram(void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct odm_phy_dbg_info *dbg_i = &dm->phy_dbg_info;
+	struct phydm_phystatus_statistic *dbg_s = &dbg_i->physts_statistic_info;
+	char buf[PHYDM_SNPRINT_SIZE] = {0};
+	u16 buf_size = PHYDM_SNPRINT_SIZE;
+	u16 th_size = PHY_HIST_SIZE - 1;
+	u8 i = 0;
+
+	PHYDM_DBG(dm, DBG_CMN, "[PHY Histogram] ==============>\n");
+/*@===[Threshold]=============================================================*/
+	phydm_print_hist_2_buf(dm, dbg_i->evm_hist_th, th_size, buf, buf_size);
+	PHYDM_DBG(dm, DBG_CMN, "%-16s=%s\n", "[EVM_TH]", buf);
+
+	phydm_print_hist_2_buf(dm, dbg_i->snr_hist_th, th_size, buf, buf_size);
+	PHYDM_DBG(dm, DBG_CMN, "%-16s=%s\n", "[SNR_TH]", buf);
+/*@===[OFDM]==================================================================*/
+	if (dbg_s->rssi_ofdm_cnt) {
+		phydm_print_hist_2_buf(dm, dbg_s->evm_ofdm_hist, PHY_HIST_SIZE,
+				       buf, buf_size);
+		PHYDM_DBG(dm, DBG_CMN, "%-14s=%s\n", "[OFDM][EVM]", buf);
+
+		phydm_print_hist_2_buf(dm, dbg_s->snr_ofdm_hist, PHY_HIST_SIZE,
+				       buf, buf_size);
+		PHYDM_DBG(dm, DBG_CMN, "%-14s=%s\n", "[OFDM][SNR]", buf);
+	}
+/*@===[1-SS]==================================================================*/
+	if (dbg_s->rssi_1ss_cnt)
+		phydm_nss_hitogram(dm, PDM_1SS);
+/*@===[2-SS]==================================================================*/
+	#if (defined(PHYDM_COMPILE_ABOVE_2SS))
+	if ((dm->support_ic_type & PHYDM_IC_ABOVE_2SS) && dbg_s->rssi_2ss_cnt)
+		phydm_nss_hitogram(dm, PDM_2SS);
+	#endif
+/*@===[3-SS]==================================================================*/
+	#if (defined(PHYDM_COMPILE_ABOVE_3SS))
+	if ((dm->support_ic_type & PHYDM_IC_ABOVE_3SS) && dbg_s->rssi_3ss_cnt)
+		phydm_nss_hitogram(dm, PDM_3SS);
+	#endif
+/*@===[4-SS]==================================================================*/
+	#if (defined(PHYDM_COMPILE_ABOVE_4SS))
+	if (dm->support_ic_type & PHYDM_IC_ABOVE_4SS && dbg_s->rssi_4ss_cnt)
+		phydm_nss_hitogram(dm, PDM_4SS);
+	#endif
+}
+
+void phydm_get_avg_phystatus_val(void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct odm_phy_dbg_info *dbg_i = &dm->phy_dbg_info;
+	struct phydm_phystatus_statistic *dbg_s = &dbg_i->physts_statistic_info;
+	struct phydm_phystatus_avg *dbg_avg = &dbg_i->phystatus_statistic_avg;
+
+	PHYDM_DBG(dm, DBG_CMN, "[PHY Avg] ==============>\n");
+	phydm_reset_phystatus_avg(dm);
+
+/*@===[CCK]===================================================================*/
+	if (dbg_s->rssi_cck_cnt != 0)
+		dbg_avg->rssi_cck_avg = (u8)(dbg_s->rssi_cck_sum /
+					dbg_s->rssi_cck_cnt);
+	else
+		dbg_avg->rssi_cck_avg = 0;
+
+	PHYDM_DBG(dm, DBG_CMN, "* cck Cnt= ((%d)) RSSI:{%d}\n",
+		  dbg_s->rssi_cck_cnt, dbg_avg->rssi_cck_avg);
+
+/*@===[OFDM]==================================================================*/
+	if (dbg_s->rssi_ofdm_cnt != 0) {
+		dbg_avg->rssi_ofdm_avg = (u8)(dbg_s->rssi_ofdm_sum /
+					      dbg_s->rssi_ofdm_cnt);
+		dbg_avg->evm_ofdm_avg = (u8)(dbg_s->evm_ofdm_sum /
+					     dbg_s->rssi_ofdm_cnt);
+		dbg_avg->snr_ofdm_avg = (u8)(dbg_s->snr_ofdm_sum /
+					     dbg_s->rssi_ofdm_cnt);
+	}
+
+	PHYDM_DBG(dm, DBG_CMN,
+		  "* ofdm Cnt= ((%d)) RSSI:{%d} EVM:{%d} SNR:{%d}\n",
+		  dbg_s->rssi_ofdm_cnt, dbg_avg->rssi_ofdm_avg,
+		  dbg_avg->evm_ofdm_avg, dbg_avg->snr_ofdm_avg);
+/*@===[1-SS]==================================================================*/
+	if (dbg_s->rssi_1ss_cnt != 0) {
+		dbg_avg->rssi_1ss_avg = (u8)(dbg_s->rssi_1ss_sum /
+					     dbg_s->rssi_1ss_cnt);
+		dbg_avg->evm_1ss_avg = (u8)(dbg_s->evm_1ss_sum /
+					    dbg_s->rssi_1ss_cnt);
+		dbg_avg->snr_1ss_avg = (u8)(dbg_s->snr_1ss_sum /
+					    dbg_s->rssi_1ss_cnt);
+	}
+
+	PHYDM_DBG(dm, DBG_CMN,
+		  "* 1-ss Cnt= ((%d)) RSSI:{%d} EVM:{%d} SNR:{%d}\n",
+		  dbg_s->rssi_1ss_cnt, dbg_avg->rssi_1ss_avg,
+		  dbg_avg->evm_1ss_avg, dbg_avg->snr_1ss_avg);
+
+/*@===[2-SS]==================================================================*/
+#if (defined(PHYDM_COMPILE_ABOVE_2SS))
+	if (dm->support_ic_type & (PHYDM_IC_ABOVE_2SS)) {
+		if (dbg_s->rssi_2ss_cnt != 0) {
+			dbg_avg->rssi_2ss_avg[0] = (u8)(dbg_s->rssi_2ss_sum[0] /
+							dbg_s->rssi_2ss_cnt);
+			dbg_avg->rssi_2ss_avg[1] = (u8)(dbg_s->rssi_2ss_sum[1] /
+							dbg_s->rssi_2ss_cnt);
+
+			dbg_avg->evm_2ss_avg[0] = (u8)(dbg_s->evm_2ss_sum[0] /
+						       dbg_s->rssi_2ss_cnt);
+			dbg_avg->evm_2ss_avg[1] = (u8)(dbg_s->evm_2ss_sum[1] /
+						       dbg_s->rssi_2ss_cnt);
+
+			dbg_avg->snr_2ss_avg[0] = (u8)(dbg_s->snr_2ss_sum[0] /
+						       dbg_s->rssi_2ss_cnt);
+			dbg_avg->snr_2ss_avg[1] = (u8)(dbg_s->snr_2ss_sum[1] /
+						       dbg_s->rssi_2ss_cnt);
+		}
+
+		PHYDM_DBG(dm, DBG_CMN,
+			  "* 2-ss Cnt= ((%d)) RSSI:{%d, %d}, EVM:{%d, %d}, SNR:{%d, %d}\n",
+			  dbg_s->rssi_2ss_cnt, dbg_avg->rssi_2ss_avg[0],
+			  dbg_avg->rssi_2ss_avg[1], dbg_avg->evm_2ss_avg[0],
+			  dbg_avg->evm_2ss_avg[1], dbg_avg->snr_2ss_avg[0],
+			  dbg_avg->snr_2ss_avg[1]);
+	}
+#endif
+
+/*@===[3-SS]==================================================================*/
+#if (defined(PHYDM_COMPILE_ABOVE_3SS))
+	if (dm->support_ic_type & (PHYDM_IC_ABOVE_3SS)) {
+		if (dbg_s->rssi_3ss_cnt != 0) {
+			dbg_avg->rssi_3ss_avg[0] = (u8)(dbg_s->rssi_3ss_sum[0] /
+							dbg_s->rssi_3ss_cnt);
+			dbg_avg->rssi_3ss_avg[1] = (u8)(dbg_s->rssi_3ss_sum[1] /
+							dbg_s->rssi_3ss_cnt);
+			dbg_avg->rssi_3ss_avg[2] = (u8)(dbg_s->rssi_3ss_sum[2] /
+							dbg_s->rssi_3ss_cnt);
+
+			dbg_avg->evm_3ss_avg[0] = (u8)(dbg_s->evm_3ss_sum[0] /
+						       dbg_s->rssi_3ss_cnt);
+			dbg_avg->evm_3ss_avg[1] = (u8)(dbg_s->evm_3ss_sum[1] /
+						       dbg_s->rssi_3ss_cnt);
+			dbg_avg->evm_3ss_avg[2] = (u8)(dbg_s->evm_3ss_sum[2] /
+						       dbg_s->rssi_3ss_cnt);
+
+			dbg_avg->snr_3ss_avg[0] = (u8)(dbg_s->snr_3ss_sum[0] /
+						       dbg_s->rssi_3ss_cnt);
+			dbg_avg->snr_3ss_avg[1] = (u8)(dbg_s->snr_3ss_sum[1] /
+						       dbg_s->rssi_3ss_cnt);
+			dbg_avg->snr_3ss_avg[2] = (u8)(dbg_s->snr_3ss_sum[2] /
+						       dbg_s->rssi_3ss_cnt);
+		}
+
+		PHYDM_DBG(dm, DBG_CMN,
+			  "* 3-ss Cnt= ((%d)) RSSI:{%d, %d, %d} EVM:{%d, %d, %d} SNR:{%d, %d, %d}\n",
+			  dbg_s->rssi_3ss_cnt, dbg_avg->rssi_3ss_avg[0],
+			  dbg_avg->rssi_3ss_avg[1], dbg_avg->rssi_3ss_avg[2],
+			  dbg_avg->evm_3ss_avg[0], dbg_avg->evm_3ss_avg[1],
+			  dbg_avg->evm_3ss_avg[2], dbg_avg->snr_3ss_avg[0],
+			  dbg_avg->snr_3ss_avg[1], dbg_avg->snr_3ss_avg[2]);
+	}
+#endif
+
+/*@===[4-SS]==================================================================*/
+#if (defined(PHYDM_COMPILE_ABOVE_4SS))
+	if (dm->support_ic_type & PHYDM_IC_ABOVE_4SS) {
+		if (dbg_s->rssi_4ss_cnt != 0) {
+			dbg_avg->rssi_4ss_avg[0] = (u8)(dbg_s->rssi_4ss_sum[0] /
+							dbg_s->rssi_4ss_cnt);
+			dbg_avg->rssi_4ss_avg[1] = (u8)(dbg_s->rssi_4ss_sum[1] /
+							dbg_s->rssi_4ss_cnt);
+			dbg_avg->rssi_4ss_avg[2] = (u8)(dbg_s->rssi_4ss_sum[2] /
+							dbg_s->rssi_4ss_cnt);
+			dbg_avg->rssi_4ss_avg[3] = (u8)(dbg_s->rssi_4ss_sum[3] /
+							dbg_s->rssi_4ss_cnt);
+
+			dbg_avg->evm_4ss_avg[0] = (u8)(dbg_s->evm_4ss_sum[0] /
+						       dbg_s->rssi_4ss_cnt);
+			dbg_avg->evm_4ss_avg[1] = (u8)(dbg_s->evm_4ss_sum[1] /
+						       dbg_s->rssi_4ss_cnt);
+			dbg_avg->evm_4ss_avg[2] = (u8)(dbg_s->evm_4ss_sum[2] /
+						       dbg_s->rssi_4ss_cnt);
+			dbg_avg->evm_4ss_avg[3] = (u8)(dbg_s->evm_4ss_sum[3] /
+						       dbg_s->rssi_4ss_cnt);
+
+			dbg_avg->snr_4ss_avg[0] = (u8)(dbg_s->snr_4ss_sum[0] /
+						       dbg_s->rssi_4ss_cnt);
+			dbg_avg->snr_4ss_avg[1] = (u8)(dbg_s->snr_4ss_sum[1] /
+						       dbg_s->rssi_4ss_cnt);
+			dbg_avg->snr_4ss_avg[2] = (u8)(dbg_s->snr_4ss_sum[2] /
+						       dbg_s->rssi_4ss_cnt);
+			dbg_avg->snr_4ss_avg[3] = (u8)(dbg_s->snr_4ss_sum[3] /
+						       dbg_s->rssi_4ss_cnt);
+		}
+
+		PHYDM_DBG(dm, DBG_CMN,
+			  "* 4-ss Cnt= ((%d)) RSSI:{%d, %d, %d, %d} EVM:{%d, %d, %d, %d} SNR:{%d, %d, %d, %d}\n",
+			  dbg_s->rssi_4ss_cnt, dbg_avg->rssi_4ss_avg[0],
+			  dbg_avg->rssi_4ss_avg[1], dbg_avg->rssi_4ss_avg[2],
+			  dbg_avg->rssi_4ss_avg[3], dbg_avg->evm_4ss_avg[0],
+			  dbg_avg->evm_4ss_avg[1], dbg_avg->evm_4ss_avg[2],
+			  dbg_avg->evm_4ss_avg[3], dbg_avg->snr_4ss_avg[0],
+			  dbg_avg->snr_4ss_avg[1], dbg_avg->snr_4ss_avg[2],
+			  dbg_avg->snr_4ss_avg[3]);
+	}
+#endif
+}
+
+void phydm_get_phy_statistic(void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+
+	phydm_rx_rate_distribution(dm);
+	phydm_reset_rx_rate_distribution(dm);
+
+	phydm_show_phy_hitogram(dm);
+	phydm_get_avg_phystatus_val(dm);
+	phydm_reset_phystatus_statistic(dm);
+};
+
+void phydm_basic_dbg_msg_linked(void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct phydm_cfo_track_struct *cfo_t = &dm->dm_cfo_track;
+	struct odm_phy_dbg_info *dbg_t = &dm->phy_dbg_info;
+	u16 macid, phydm_macid, client_cnt = 0;
+	u8 rate = 0;
+	struct cmn_sta_info *entry = NULL;
+	char dbg_buf[PHYDM_SNPRINT_SIZE] = {0};
+	struct phydm_cfo_rpt cfo;
+	u8 i = 0;
+
+	PHYDM_DBG(dm, DBG_CMN, "ID=((%d)), BW=((%d)), fc=((CH-%d))\n",
+		  dm->curr_station_id, 20 << *dm->band_width, *dm->channel);
+
+	#ifdef ODM_IC_11N_SERIES_SUPPORT
+	#ifdef PHYDM_PRIMARY_CCA
+	if (((*dm->channel <= 14) && (*dm->band_width == CHANNEL_WIDTH_40)) &&
+	    (dm->support_ic_type & ODM_IC_11N_SERIES)) {
+		PHYDM_DBG(dm, DBG_CMN, "Primary CCA at ((%s SB))\n",
+			  ((*dm->sec_ch_offset == SECOND_CH_AT_LSB) ? "U" :
+			  "L"));
+	}
+	#endif
+	#endif
+
+	if ((dm->support_ic_type & PHYSTS_2ND_TYPE_IC) ||
+	    dm->rx_rate > ODM_RATE11M) {
+		PHYDM_DBG(dm, DBG_CMN, "[AGC Idx] {0x%x, 0x%x, 0x%x, 0x%x}\n",
+			  dm->ofdm_agc_idx[0], dm->ofdm_agc_idx[1],
+			  dm->ofdm_agc_idx[2], dm->ofdm_agc_idx[3]);
+	} else {
+		PHYDM_DBG(dm, DBG_CMN, "[CCK AGC Idx] {LNA,VGA}={0x%x, 0x%x}\n",
+			  dm->cck_lna_idx, dm->cck_vga_idx);
+	}
+
+	phydm_print_rate_2_buff(dm, dm->rx_rate, dbg_buf, PHYDM_SNPRINT_SIZE);
+	PHYDM_DBG(dm, DBG_CMN, "RSSI:{%d, %d, %d, %d}, RxRate:%s (0x%x)\n",
+		  (dm->rssi_a == 0xff) ? 0 : dm->rssi_a,
+		  (dm->rssi_b == 0xff) ? 0 : dm->rssi_b,
+		  (dm->rssi_c == 0xff) ? 0 : dm->rssi_c,
+		  (dm->rssi_d == 0xff) ? 0 : dm->rssi_d,
+		  dbg_buf, dm->rx_rate);
+
+	rate = dbg_t->beacon_phy_rate;
+	phydm_print_rate_2_buff(dm, rate, dbg_buf, PHYDM_SNPRINT_SIZE);
+
+	PHYDM_DBG(dm, DBG_CMN, "Beacon_cnt=%d, rate_idx=%s (0x%x)\n",
+		  dbg_t->num_qry_beacon_pkt,
+		  dbg_buf,
+		  dbg_t->beacon_phy_rate);
+
+	phydm_get_phy_statistic(dm);
+
+	PHYDM_DBG(dm, DBG_CMN,
+		  "rxsc_idx {Legacy, 20, 40, 80} = {%d, %d, %d, %d}\n",
+		  dm->rxsc_l, dm->rxsc_20, dm->rxsc_40, dm->rxsc_80);
+
+	/*Print TX rate*/
+	for (macid = 0; macid < ODM_ASSOCIATE_ENTRY_NUM; macid++) {
+		entry = dm->phydm_sta_info[macid];
+
+		if (!is_sta_active(entry))
+			continue;
+
+		phydm_macid = (dm->phydm_macid_table[macid]);
+		rate = entry->ra_info.curr_tx_rate;
+		phydm_print_rate_2_buff(dm, rate, dbg_buf, PHYDM_SNPRINT_SIZE);
+		PHYDM_DBG(dm, DBG_CMN, "TxRate[%d]=%s (0x%x)\n",
+			  macid, dbg_buf, entry->ra_info.curr_tx_rate);
+
+		client_cnt++;
+
+		if (client_cnt >= dm->number_linked_client)
+			break;
+	}
+
+	PHYDM_DBG(dm, DBG_CMN,
+		  "TP {Tx, Rx, Total} = {%d, %d, %d}Mbps, Traffic_Load=(%d))\n",
+		  dm->tx_tp, dm->rx_tp, dm->total_tp, dm->traffic_load);
+
+	PHYDM_DBG(dm, DBG_CMN, "CFO_avg=((%d kHz)), CFO_traking = ((%s%d))\n",
+		  cfo_t->CFO_ave_pre,
+		  ((cfo_t->crystal_cap > cfo_t->def_x_cap) ? "+" : "-"),
+		  DIFF_2(cfo_t->crystal_cap, cfo_t->def_x_cap));
+
+	phydm_get_cfo_info(dm, &cfo);
+	for (i = 0; i < dm->num_rf_path; i++) {
+		PHYDM_DBG(dm, DBG_CMN,
+			  "CFO[%d] {S, L, Sec, Acq, End} = {%d, %d, %d, %d, %d}\n",
+			  i, cfo.cfo_rpt_s[i], cfo.cfo_rpt_l[i],
+			  cfo.cfo_rpt_sec[i], cfo.cfo_rpt_acq[i],
+			  cfo.cfo_rpt_end[i]);
+	}
+
+/* @Condition number */
+#if (RTL8822B_SUPPORT)
+	if (dm->support_ic_type == ODM_RTL8822B) {
+		PHYDM_DBG(dm, DBG_CMN, "Condi_Num=((%d.%.4d)), %d\n",
+			  dbg_t->condi_num >> 4,
+			  phydm_show_fraction_num(dbg_t->condi_num & 0xf, 4),
+			  dbg_t->condi_num);
+	}
+#endif
+#ifdef PHYSTS_3RD_TYPE_SUPPORT
+	if (dm->support_ic_type == ODM_RTL8198F) {
+		PHYDM_DBG(dm, DBG_CMN, "Condi_Num=((%d.%4d dB))\n",
+			  dbg_t->condi_num >> 1,
+			  phydm_show_fraction_num(dbg_t->condi_num & 0x1, 1));
+	}
+#endif
+
+#if (ODM_PHY_STATUS_NEW_TYPE_SUPPORT)
+	/*STBC or LDPC pkt*/
+	if (dm->support_ic_type & PHYSTS_2ND_TYPE_IC)
+		PHYDM_DBG(dm, DBG_CMN, "Coding: LDPC=((%s)), STBC=((%s))\n",
+			  (dbg_t->is_ldpc_pkt) ? "Y" : "N",
+			  (dbg_t->is_stbc_pkt) ? "Y" : "N");
+#endif
+}
+
+void phydm_dm_summary(void *dm_void, u8 macid)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
+	struct phydm_cfo_track_struct *cfo_t = &dm->dm_cfo_track;
+	struct cmn_sta_info *sta = NULL;
+	struct ra_sta_info *ra = NULL;
+	struct dtp_info *dtp = NULL;
+	u64 comp = dm->support_ability;
+	u64 pause_comp = dm->pause_ability;
+
+	if (!(dm->debug_components & DBG_DM_SUMMARY))
+		return;
+
+	if (!dm->is_linked) {
+		pr_debug("[%s]No Link !!!\n", __func__);
+		return;
+	}
+
+	sta = dm->phydm_sta_info[macid];
+
+	if (!is_sta_active(sta)) {
+		pr_debug("[Warning] %s invalid STA, macid=%d\n",
+			 __func__, macid);
+		return;
+	}
+
+	ra = &sta->ra_info;
+	dtp = &sta->dtp_stat;
+	pr_debug("[%s]===========>\n", __func__);
+
+	pr_debug("00.(%s) %-12s: IGI=0x%x, Dyn_Rng=0x%x~0x%x, FA_th={%d,%d,%d}\n",
+		 ((comp & ODM_BB_DIG) ?
+		 ((pause_comp & ODM_BB_DIG) ? "P" : "V") : "."),
+		 "DIG",
+		 dig_t->cur_ig_value,
+		 dig_t->rx_gain_range_min, dig_t->rx_gain_range_max,
+		 dig_t->fa_th[0], dig_t->fa_th[1], dig_t->fa_th[2]);
+
+	pr_debug("01.(%s) %-12s: rssi_lv=%d, mask=0x%llx\n",
+		 ((comp & ODM_BB_RA_MASK) ?
+		 ((pause_comp & ODM_BB_RA_MASK) ? "P" : "V") : "."),
+		 "RaMask",
+		 ra->rssi_level, ra->ramask);
+
+#ifdef CONFIG_DYNAMIC_TX_TWR
+	pr_debug("02.(%s) %-12s: pwr_lv=%d\n",
+		 ((comp & ODM_BB_DYNAMIC_TXPWR) ?
+		 ((pause_comp & ODM_BB_DYNAMIC_TXPWR) ? "P" : "V") : "."),
+		 "DynTxPwr",
+		 dtp->sta_tx_high_power_lvl);
+#endif
+
+	pr_debug("05.(%s) %-12s: cck_pd_lv=%d\n",
+		 ((comp & ODM_BB_CCK_PD) ?
+		 ((pause_comp & ODM_BB_CCK_PD) ? "P" : "V") : "."),
+		 "CCK_PD", dm->dm_cckpd_table.cck_pd_lv);
+
+#ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY
+	pr_debug("06.(%s) %-12s: div_type=%d, curr_ant=%s\n",
+		 ((comp & ODM_BB_ANT_DIV) ?
+		 ((pause_comp & ODM_BB_ANT_DIV) ? "P" : "V") : "."),
+		 "ANT_DIV",
+		 dm->ant_div_type,
+		 (dm->dm_fat_table.rx_idle_ant == MAIN_ANT) ? "MAIN" : "AUX");
+#endif
+
+#ifdef PHYDM_POWER_TRAINING_SUPPORT
+	pr_debug("08.(%s) %-12s: PT_score=%d, disable_PT=%d\n",
+		 ((comp & ODM_BB_PWR_TRAIN) ?
+		 ((pause_comp & ODM_BB_PWR_TRAIN) ? "P" : "V") : "."),
+		 "PwrTrain",
+		 dm->pow_train_table.pow_train_score,
+		 dm->is_disable_power_training);
+#endif
+
+#ifdef CONFIG_PHYDM_DFS_MASTER
+	pr_debug("11.(%s) %-12s: dbg_mode=%d, region_domain=%d\n",
+		 ((comp & ODM_BB_DFS) ?
+		 ((pause_comp & ODM_BB_DFS) ? "P" : "V") : "."),
+		 "DFS",
+		 dm->dfs.dbg_mode, dm->dfs_region_domain);
+#endif
+#ifdef PHYDM_SUPPORT_ADAPTIVITY
+	pr_debug("13.(%s) %-12s: th{l2h, h2l}={%d, %d}, edcca_flag=%d\n",
+		 ((comp & ODM_BB_ADAPTIVITY) ?
+		 ((pause_comp & ODM_BB_ADAPTIVITY) ? "P" : "V") : "."),
+		 "Adaptivity",
+		 dm->adaptivity.th_l2h, dm->adaptivity.th_h2l,
+		 dm->false_alm_cnt.edcca_flag);
+#endif
+	pr_debug("14.(%s) %-12s: CFO_avg=%d kHz, CFO_traking=%s%d\n",
+		 ((comp & ODM_BB_CFO_TRACKING) ?
+		 ((pause_comp & ODM_BB_CFO_TRACKING) ? "P" : "V") : "."),
+		 "CfoTrack",
+		 cfo_t->CFO_ave_pre,
+		 ((cfo_t->crystal_cap > cfo_t->def_x_cap) ? "+" : "-"),
+		 DIFF_2(cfo_t->crystal_cap, cfo_t->def_x_cap));
+
+	pr_debug("15.(%s) %-12s: ratio{nhm, clm}={%d, %d}\n",
+		 ((comp & ODM_BB_ENV_MONITOR) ?
+		 ((pause_comp & ODM_BB_ENV_MONITOR) ? "P" : "V") : "."),
+		 "EnvMntr",
+		 dm->dm_ccx_info.nhm_ratio, dm->dm_ccx_info.clm_ratio);
+
+#ifdef PHYDM_PRIMARY_CCA
+	pr_debug("16.(%s) %-12s: CCA @ (%s SB)\n",
+		 ((comp & ODM_BB_PRIMARY_CCA) ?
+		 ((pause_comp & ODM_BB_PRIMARY_CCA) ? "P" : "V") : "."),
+		 "PriCCA",
+		 ((dm->dm_pri_cca.mf_state == MF_USC_LSC) ? "D" :
+		 ((dm->dm_pri_cca.mf_state == MF_LSC) ? "L" : "U")));
+#endif
+#ifdef CONFIG_ADAPTIVE_SOML
+	pr_debug("17.(%s) %-12s: soml_en = %s\n",
+		 ((comp & ODM_BB_ADAPTIVE_SOML) ?
+		 ((pause_comp & ODM_BB_ADAPTIVE_SOML) ? "P" : "V") : "."),
+		 "A-SOML",
+		 (dm->dm_soml_table.soml_last_state == SOML_ON) ?
+		 "ON" : "OFF");
+#endif
+#ifdef PHYDM_LNA_SAT_CHK_SUPPORT
+	pr_debug("18.(%s) %-12s:\n",
+		 ((comp & ODM_BB_LNA_SAT_CHK) ?
+		 ((pause_comp & ODM_BB_LNA_SAT_CHK) ? "P" : "V") : "."),
+		 "LNA_SAT_CHK");
+#endif
+}
+
+void phydm_basic_dbg_message(void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct phydm_fa_struct *fa_t = &dm->false_alm_cnt;
+
+	if (!(dm->debug_components & DBG_CMN))
+		return;
+
+	if (dm->cmn_dbg_msg_cnt >= dm->cmn_dbg_msg_period) {
+		dm->cmn_dbg_msg_cnt = PHYDM_WATCH_DOG_PERIOD;
+	} else {
+		dm->cmn_dbg_msg_cnt += PHYDM_WATCH_DOG_PERIOD;
+		return;
+	}
+
+	PHYDM_DBG(dm, DBG_CMN, "[%s] System up time: ((%d sec))---->\n",
+		  __func__, dm->phydm_sys_up_time);
+
+	if (dm->is_linked)
+		phydm_basic_dbg_msg_linked(dm);
+	else
+		PHYDM_DBG(dm, DBG_CMN, "No Link !!!\n");
+
+	PHYDM_DBG(dm, DBG_CMN, "[CCA Cnt] {CCK, OFDM, Total} = {%d, %d, %d}\n",
+		  fa_t->cnt_cck_cca, fa_t->cnt_ofdm_cca, fa_t->cnt_cca_all);
+
+	PHYDM_DBG(dm, DBG_CMN, "[FA Cnt] {CCK, OFDM, Total} = {%d, %d, %d}\n",
+		  fa_t->cnt_cck_fail, fa_t->cnt_ofdm_fail, fa_t->cnt_all);
+
+	PHYDM_DBG(dm, DBG_CMN,
+		  "[OFDM FA Detail] Parity_Fail=%d, Rate_Illegal=%d, CRC8=%d, MCS_fail=%d, Fast_sync=%d, SB_Search_fail=%d\n",
+		  fa_t->cnt_parity_fail, fa_t->cnt_rate_illegal,
+		  fa_t->cnt_crc8_fail, fa_t->cnt_mcs_fail,
+		  fa_t->cnt_fast_fsync, fa_t->cnt_sb_search_fail);
+
+	#if (ODM_IC_11AC_SERIES_SUPPORT)
+	if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
+		PHYDM_DBG(dm, DBG_CMN,
+			  "[OFDM FA Detail VHT] CRC8_VHT=%d, MCS_Fail_VHT=%d\n",
+			  fa_t->cnt_crc8_fail_vht, fa_t->cnt_mcs_fail_vht);
+	}
+	#endif
+
+	PHYDM_DBG(dm, DBG_CMN,
+		  "is_linked = %d, Num_client = %d, rssi_min = %d, IGI = 0x%x, bNoisy=%d\n\n",
+		  dm->is_linked, dm->number_linked_client, dm->rssi_min,
+		  dm->dm_dig_table.cur_ig_value, dm->noisy_decision);
+}
+
+void phydm_basic_profile(void *dm_void, u32 *_used, char *output, u32 *_out_len)
+{
+#ifdef CONFIG_PHYDM_DEBUG_FUNCTION
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	char *cut = NULL;
+	char *ic_type = NULL;
+	u32 used = *_used;
+	u32 out_len = *_out_len;
+	u32 date = 0;
+	char *commit_by = NULL;
+	u32 release_ver = 0;
+
+	PDM_SNPF(out_len, used, output + used, out_len - used, "%-35s\n",
+		 "% Basic Profile %");
+
+	if (dm->support_ic_type == ODM_RTL8188E) {
+#if (RTL8188E_SUPPORT)
+		ic_type = "RTL8188E";
+		date = RELEASE_DATE_8188E;
+		commit_by = COMMIT_BY_8188E;
+		release_ver = RELEASE_VERSION_8188E;
+#endif
+#if (RTL8812A_SUPPORT)
+	} else if (dm->support_ic_type == ODM_RTL8812) {
+		ic_type = "RTL8812A";
+		date = RELEASE_DATE_8812A;
+		commit_by = COMMIT_BY_8812A;
+		release_ver = RELEASE_VERSION_8812A;
+#endif
+#if (RTL8821A_SUPPORT)
+	} else if (dm->support_ic_type == ODM_RTL8821) {
+		ic_type = "RTL8821A";
+		date = RELEASE_DATE_8821A;
+		commit_by = COMMIT_BY_8821A;
+		release_ver = RELEASE_VERSION_8821A;
+#endif
+#if (RTL8192E_SUPPORT)
+	} else if (dm->support_ic_type == ODM_RTL8192E) {
+		ic_type = "RTL8192E";
+		date = RELEASE_DATE_8192E;
+		commit_by = COMMIT_BY_8192E;
+		release_ver = RELEASE_VERSION_8192E;
+#endif
+#if (RTL8723B_SUPPORT)
+	} else if (dm->support_ic_type == ODM_RTL8723B) {
+		ic_type = "RTL8723B";
+		date = RELEASE_DATE_8723B;
+		commit_by = COMMIT_BY_8723B;
+		release_ver = RELEASE_VERSION_8723B;
+#endif
+#if (RTL8814A_SUPPORT)
+	} else if (dm->support_ic_type == ODM_RTL8814A) {
+		ic_type = "RTL8814A";
+		date = RELEASE_DATE_8814A;
+		commit_by = COMMIT_BY_8814A;
+		release_ver = RELEASE_VERSION_8814A;
+#endif
+#if (RTL8881A_SUPPORT)
+	} else if (dm->support_ic_type == ODM_RTL8881A) {
+		ic_type = "RTL8881A";
+#endif
+#if (RTL8822B_SUPPORT)
+	} else if (dm->support_ic_type == ODM_RTL8822B) {
+		ic_type = "RTL8822B";
+		date = RELEASE_DATE_8822B;
+		commit_by = COMMIT_BY_8822B;
+		release_ver = RELEASE_VERSION_8822B;
+#endif
+#if (RTL8197F_SUPPORT)
+	} else if (dm->support_ic_type == ODM_RTL8197F) {
+		ic_type = "RTL8197F";
+		date = RELEASE_DATE_8197F;
+		commit_by = COMMIT_BY_8197F;
+		release_ver = RELEASE_VERSION_8197F;
+#endif
+#if (RTL8703B_SUPPORT)
+	} else if (dm->support_ic_type == ODM_RTL8703B) {
+		ic_type = "RTL8703B";
+		date = RELEASE_DATE_8703B;
+		commit_by = COMMIT_BY_8703B;
+		release_ver = RELEASE_VERSION_8703B;
+#endif
+#if (RTL8195A_SUPPORT)
+	} else if (dm->support_ic_type == ODM_RTL8195A) {
+		ic_type = "RTL8195A";
+#endif
+#if (RTL8188F_SUPPORT)
+	} else if (dm->support_ic_type == ODM_RTL8188F) {
+		ic_type = "RTL8188F";
+		date = RELEASE_DATE_8188F;
+		commit_by = COMMIT_BY_8188F;
+		release_ver = RELEASE_VERSION_8188F;
+#endif
+#if (RTL8723D_SUPPORT)
+	} else if (dm->support_ic_type == ODM_RTL8723D) {
+		ic_type = "RTL8723D";
+		date = RELEASE_DATE_8723D;
+		commit_by = COMMIT_BY_8723D;
+		release_ver = RELEASE_VERSION_8723D;
+#endif
+	}
+
+/* @JJ ADD 20161014 */
+#if (RTL8710B_SUPPORT)
+	else if (dm->support_ic_type == ODM_RTL8710B) {
+		ic_type = "RTL8710B";
+		date = RELEASE_DATE_8710B;
+		commit_by = COMMIT_BY_8710B;
+		release_ver = RELEASE_VERSION_8710B;
+	}
+#endif
+
+#if (RTL8821C_SUPPORT)
+	else if (dm->support_ic_type == ODM_RTL8821C) {
+		ic_type = "RTL8821C";
+		date = RELEASE_DATE_8821C;
+		commit_by = COMMIT_BY_8821C;
+		release_ver = RELEASE_VERSION_8821C;
+	}
+#endif
+
+/*@jj add 20170822*/
+#if (RTL8192F_SUPPORT)
+	else if (dm->support_ic_type == ODM_RTL8192F) {
+		ic_type = "RTL8192F";
+		date = RELEASE_DATE_8192F;
+		commit_by = COMMIT_BY_8192F;
+		release_ver = RELEASE_VERSION_8192F;
+	}
+#endif
+
+#if (RTL8198F_SUPPORT)
+	else if (dm->support_ic_type == ODM_RTL8198F) {
+		ic_type = "RTL8198F";
+		date = RELEASE_DATE_8198F;
+		commit_by = COMMIT_BY_8198F;
+		release_ver = RELEASE_VERSION_8198F;
+	}
+#endif
+
+#if (RTL8822C_SUPPORT)
+	else if (dm->support_ic_type == ODM_RTL8822C) {
+		ic_type = "RTL8822C";
+		date = RELEASE_DATE_8822C;
+		commit_by = COMMIT_BY_8822C;
+		release_ver = RELEASE_VERSION_8822C;
+	}
+#endif
+
+	PDM_SNPF(out_len, used, output + used, out_len - used,
+		 "  %-35s: %s (MP Chip: %s)\n", "IC type", ic_type,
+		 dm->is_mp_chip ? "Yes" : "No");
+
+	if (dm->cut_version == ODM_CUT_A)
+		cut = "A";
+	else if (dm->cut_version == ODM_CUT_B)
+		cut = "B";
+	else if (dm->cut_version == ODM_CUT_C)
+		cut = "C";
+	else if (dm->cut_version == ODM_CUT_D)
+		cut = "D";
+	else if (dm->cut_version == ODM_CUT_E)
+		cut = "E";
+	else if (dm->cut_version == ODM_CUT_F)
+		cut = "F";
+	else if (dm->cut_version == ODM_CUT_I)
+		cut = "I";
+
+	PDM_SNPF(out_len, used, output + used, out_len - used, "  %-35s: %d\n",
+		 "RFE type", dm->rfe_type);
+	PDM_SNPF(out_len, used, output + used, out_len - used, "  %-35s: %s\n",
+		 "Cut Ver", cut);
+	PDM_SNPF(out_len, used, output + used, out_len - used, "  %-35s: %d\n",
+		 "PHY Para Ver", odm_get_hw_img_version(dm));
+	PDM_SNPF(out_len, used, output + used, out_len - used, "  %-35s: %d\n",
+		 "PHY Para Commit date", date);
+	PDM_SNPF(out_len, used, output + used, out_len - used, "  %-35s: %s\n",
+		 "PHY Para Commit by", commit_by);
+	PDM_SNPF(out_len, used, output + used, out_len - used, "  %-35s: %d\n",
+		 "PHY Para Release Ver", release_ver);
+
+	PDM_SNPF(out_len, used, output + used, out_len - used,
+		 "  %-35s: %d (Subversion: %d)\n", "FW Ver", dm->fw_version,
+		 dm->fw_sub_version);
+
+	/* @1 PHY DM version List */
+	PDM_SNPF(out_len, used, output + used, out_len - used, "%-35s\n",
+		 "% PHYDM version %");
+	PDM_SNPF(out_len, used, output + used, out_len - used, "  %-35s: %s\n",
+		 "Code base", PHYDM_CODE_BASE);
+	PDM_SNPF(out_len, used, output + used, out_len - used, "  %-35s: %s\n",
+		 "Release Date", PHYDM_RELEASE_DATE);
+	PDM_SNPF(out_len, used, output + used, out_len - used, "  %-35s: %s\n",
+		 "Adaptivity", ADAPTIVITY_VERSION);
+	PDM_SNPF(out_len, used, output + used, out_len - used, "  %-35s: %s\n",
+		 "DIG", DIG_VERSION);
+	PDM_SNPF(out_len, used, output + used, out_len - used, "  %-35s: %s\n",
+		 "CFO Tracking", CFO_TRACKING_VERSION);
+#ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY
+	PDM_SNPF(out_len, used, output + used, out_len - used, "  %-35s: %s\n",
+		 "AntDiv", ANTDIV_VERSION);
+#endif
+#ifdef CONFIG_DYNAMIC_TX_TWR
+	PDM_SNPF(out_len, used, output + used, out_len - used, "  %-35s: %s\n",
+		 "Dynamic TxPower", DYNAMIC_TXPWR_VERSION);
+#endif
+	PDM_SNPF(out_len, used, output + used, out_len - used, "  %-35s: %s\n",
+		 "RA Info", RAINFO_VERSION);
+#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
+	PDM_SNPF(out_len, used, output + used, out_len - used, "  %-35s: %s\n",
+		 "AntDetect", ANTDECT_VERSION);
+#endif
+#ifdef CONFIG_PATH_DIVERSITY
+	PDM_SNPF(out_len, used, output + used, out_len - used, "  %-35s: %s\n",
+		 "PathDiv", PATHDIV_VERSION);
+#endif
+#ifdef CONFIG_ADAPTIVE_SOML
+	PDM_SNPF(out_len, used, output + used, out_len - used, "  %-35s: %s\n",
+		 "Adaptive SOML", ADAPTIVE_SOML_VERSION);
+#endif
+#if (PHYDM_LA_MODE_SUPPORT)
+	PDM_SNPF(out_len, used, output + used, out_len - used, "  %-35s: %s\n",
+		 "LA mode", DYNAMIC_LA_MODE);
+#endif
+#ifdef PHYDM_PRIMARY_CCA
+	PDM_SNPF(out_len, used, output + used, out_len - used, "  %-35s: %s\n",
+		 "Primary CCA", PRIMARYCCA_VERSION);
+#endif
+	PDM_SNPF(out_len, used, output + used, out_len - used, "  %-35s: %s\n",
+		 "DFS", DFS_VERSION);
+
+#if (RTL8822B_SUPPORT)
+	if (dm->support_ic_type & ODM_RTL8822B)
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "  %-35s: %s\n", "PHY config 8822B",
+			 PHY_CONFIG_VERSION_8822B);
+
+#endif
+#if (RTL8197F_SUPPORT)
+	if (dm->support_ic_type & ODM_RTL8197F)
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "  %-35s: %s\n", "PHY config 8197F",
+			 PHY_CONFIG_VERSION_8197F);
+#endif
+
+/*@jj add 20170822*/
+#if (RTL8192F_SUPPORT)
+	if (dm->support_ic_type & ODM_RTL8192F)
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "  %-35s: %s\n", "PHY config 8192F",
+			 PHY_CONFIG_VERSION_8192F);
+#endif
+
+	*_used = used;
+	*_out_len = out_len;
+
+#endif /*@#if CONFIG_PHYDM_DEBUG_FUNCTION*/
+}
+
+#ifdef CONFIG_PHYDM_DEBUG_FUNCTION
+void phydm_fw_trace_en_h2c(void *dm_void, boolean enable,
+			   u32 fw_dbg_comp, u32 monitor_mode, u32 macid)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	u8 h2c_parameter[7] = {0};
+	u8 cmd_length;
+
+	if (dm->support_ic_type & PHYDM_IC_3081_SERIES) {
+		h2c_parameter[0] = enable;
+		h2c_parameter[1] = (u8)(fw_dbg_comp & MASKBYTE0);
+		h2c_parameter[2] = (u8)((fw_dbg_comp & MASKBYTE1) >> 8);
+		h2c_parameter[3] = (u8)((fw_dbg_comp & MASKBYTE2) >> 16);
+		h2c_parameter[4] = (u8)((fw_dbg_comp & MASKBYTE3) >> 24);
+		h2c_parameter[5] = (u8)monitor_mode;
+		h2c_parameter[6] = (u8)macid;
+		cmd_length = 7;
+
+	} else {
+		h2c_parameter[0] = enable;
+		h2c_parameter[1] = (u8)monitor_mode;
+		h2c_parameter[2] = (u8)macid;
+		cmd_length = 3;
+	}
+
+	PHYDM_DBG(dm, DBG_FW_TRACE, "---->\n");
+	if (monitor_mode == 0)
+		PHYDM_DBG(dm, DBG_FW_TRACE, "[H2C] FW_debug_en: (( %d ))\n",
+			  enable);
+	else
+		PHYDM_DBG(dm, DBG_FW_TRACE,
+			  "[H2C] FW_debug_en: (( %d )), mode: (( %d )), macid: (( %d ))\n",
+			  enable, monitor_mode, macid);
+	odm_fill_h2c_cmd(dm, PHYDM_H2C_FW_TRACE_EN, cmd_length, h2c_parameter);
+}
+
+void phydm_get_per_path_txagc(void *dm_void, u8 path, u32 *_used, char *output,
+			      u32 *_out_len)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	u8 rate_idx;
+	u8 txagc;
+	u32 used = *_used;
+	u32 out_len = *_out_len;
+
+#ifdef PHYDM_COMMON_API_SUPPORT
+	if (!(dm->support_ic_type & CMN_API_SUPPORT_IC))
+		return;
+
+	if (dm->num_rf_path == 1 && path > RF_PATH_A)
+		return;
+	else if (dm->num_rf_path == 2 && path > RF_PATH_B)
+		return;
+	else if (dm->num_rf_path == 3 && path > RF_PATH_C)
+		return;
+	else if (dm->num_rf_path == 4 && path > RF_PATH_D)
+		return;
+
+	for (rate_idx = 0; rate_idx <= 0x53; rate_idx++) {
+		if (rate_idx == ODM_RATE1M)
+			PDM_SNPF(out_len, used, output + used, out_len - used,
+				 "  %-35s\n", "CCK====>");
+		else if (rate_idx == ODM_RATE6M)
+			PDM_SNPF(out_len, used, output + used, out_len - used,
+				 "\n  %-35s\n", "OFDM====>");
+		else if (rate_idx == ODM_RATEMCS0)
+			PDM_SNPF(out_len, used, output + used, out_len - used,
+				 "\n  %-35s\n", "HT 1ss====>");
+		else if (rate_idx == ODM_RATEMCS8)
+			PDM_SNPF(out_len, used, output + used, out_len - used,
+				 "\n  %-35s\n", "HT 2ss====>");
+		else if (rate_idx == ODM_RATEMCS16)
+			PDM_SNPF(out_len, used, output + used, out_len - used,
+				 "\n  %-35s\n", "HT 3ss====>");
+		else if (rate_idx == ODM_RATEMCS24)
+			PDM_SNPF(out_len, used, output + used, out_len - used,
+				 "\n  %-35s\n", "HT 4ss====>");
+		else if (rate_idx == ODM_RATEVHTSS1MCS0)
+			PDM_SNPF(out_len, used, output + used, out_len - used,
+				 "\n  %-35s\n", "VHT 1ss====>");
+		else if (rate_idx == ODM_RATEVHTSS2MCS0)
+			PDM_SNPF(out_len, used, output + used, out_len - used,
+				 "\n  %-35s\n", "VHT 2ss====>");
+		else if (rate_idx == ODM_RATEVHTSS3MCS0)
+			PDM_SNPF(out_len, used, output + used, out_len - used,
+				 "\n  %-35s\n", "VHT 3ss====>");
+		else if (rate_idx == ODM_RATEVHTSS4MCS0)
+			PDM_SNPF(out_len, used, output + used, out_len - used,
+				 "\n  %-35s\n", "VHT 4ss====>");
+
+		txagc = phydm_api_get_txagc(dm, (enum rf_path)path, rate_idx);
+		if (config_phydm_read_txagc_check(txagc))
+			PDM_SNPF(out_len, used, output + used,
+				 out_len - used, "  0x%02x    ", txagc);
+		else
+			PDM_SNPF(out_len, used, output + used,
+				 out_len - used, "  0x%s    ", "xx");
+	}
+#endif
+
+	*_used = used;
+	*_out_len = out_len;
+}
+
+void phydm_get_txagc(void *dm_void, u32 *_used, char *output, u32 *_out_len)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	u32 used = *_used;
+	u32 out_len = *_out_len;
+
+	/* path-A */
+	PDM_SNPF(out_len, used, output + used, out_len - used, "%-35s\n",
+		 "path-A====================");
+	phydm_get_per_path_txagc(dm, RF_PATH_A, &used, output, &out_len);
+
+	/* path-B */
+	PDM_SNPF(out_len, used, output + used, out_len - used, "\n%-35s\n",
+		 "path-B====================");
+	phydm_get_per_path_txagc(dm, RF_PATH_B, &used, output, &out_len);
+
+	/* path-C */
+	PDM_SNPF(out_len, used, output + used, out_len - used, "\n%-35s\n",
+		 "path-C====================");
+	phydm_get_per_path_txagc(dm, RF_PATH_C, &used, output, &out_len);
+
+	/* path-D */
+	PDM_SNPF(out_len, used, output + used, out_len - used, "\n%-35s\n",
+		 "path-D====================");
+	phydm_get_per_path_txagc(dm, RF_PATH_D, &used, output, &out_len);
+
+	*_used = used;
+	*_out_len = out_len;
+}
+
+void phydm_set_txagc(void *dm_void, u32 *const val, u32 *_used,
+		     char *output, u32 *_out_len)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	u32 used = *_used;
+	u32 out_len = *_out_len;
+	u8 i = 0;
+	u32 pow = 0; /*power index*/
+	u8 vht_start_rate = ODM_RATEVHTSS1MCS0;
+	boolean rpt = true;
+	enum rf_path path = RF_PATH_A;
+
+/*@val[1] = path*/
+/*@val[2] = hw_rate*/
+/*@val[3] = power_index*/
+
+#ifdef PHYDM_COMMON_API_SUPPORT
+	if (!(dm->support_ic_type & CMN_API_SUPPORT_IC))
+		return;
+
+	path = (enum rf_path)val[1];
+
+	if (val[1] >= dm->num_rf_path) {
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "Write path-%d rate_idx-0x%x fail\n", val[1], val[2]);
+	} else if ((u8)val[2] != 0xff) {
+		if (phydm_api_set_txagc(dm, val[3], path, (u8)val[2], true))
+			PDM_SNPF(out_len, used, output + used, out_len - used,
+				 "Write path-%d rate_idx-0x%x = 0x%x\n",
+				 val[1], val[2], val[3]);
+		else
+			PDM_SNPF(out_len, used, output + used, out_len - used,
+				 "Write path-%d rate index-0x%x fail\n",
+				 val[1], val[2]);
+	} else {
+
+		if (dm->support_ic_type &
+		    (ODM_RTL8822B | ODM_RTL8821C | ODM_RTL8195B)) {
+			pow = (val[3] & 0x3f);
+			pow = BYTE_DUPLICATE_2_DWORD(pow);
+
+			for (i = 0; i < ODM_RATEVHTSS2MCS9; i += 4)
+				rpt &= phydm_api_set_txagc(dm, pow, path, i, 0);
+		} else if (dm->support_ic_type &
+			   (ODM_RTL8197F | ODM_RTL8192F)) {
+			pow = (val[3] & 0x3f);
+			for (i = 0; i <= ODM_RATEMCS15; i++)
+				rpt &= phydm_api_set_txagc(dm, pow, path, i, 0);
+		} else if (dm->support_ic_type & ODM_RTL8198F) {
+			pow = (val[3] & 0x7f);
+			for (i = 0; i <= ODM_RATEVHTSS4MCS9; i++)
+				rpt &= phydm_api_set_txagc(dm, pow, path, i, 0);
+		} else if (dm->support_ic_type & ODM_RTL8822C) {
+			pow = (val[3] & 0x7f);
+			for (i = 0; i <= ODM_RATEMCS15; i++)
+				rpt &= phydm_api_set_txagc(dm, pow, path, i, 0);
+			for (i = vht_start_rate; i <= ODM_RATEVHTSS2MCS9; i++)
+				rpt &= phydm_api_set_txagc(dm, pow, path, i, 0);
+		}
+
+		if (rpt)
+			PDM_SNPF(out_len, used, output + used, out_len - used,
+				 "Write all TXAGC of path-%d = 0x%x\n",
+				 val[1], val[3]);
+		else
+			PDM_SNPF(out_len, used, output + used, out_len - used,
+				 "Write all TXAGC of path-%d fail\n", val[1]);
+	}
+
+#endif
+	*_used = used;
+	*_out_len = out_len;
+}
+
+void phydm_shift_txagc(void *dm_void, u32 *const val, u32 *_used, char *output,
+		       u32 *_out_len)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	u32 used = *_used;
+	u32 out_len = *_out_len;
+	u8 i = 0;
+	u32 pow = 0; /*Power index*/
+	boolean rpt = true;
+	u8 vht_start_rate = ODM_RATEVHTSS1MCS0;
+	enum rf_path path = RF_PATH_A;
+
+#ifdef PHYDM_COMMON_API_SUPPORT
+	if (!(dm->support_ic_type & CMN_API_SUPPORT_IC))
+		return;
+
+	if (val[1] >= dm->num_rf_path) {
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "Write path-%d fail\n", val[1]);
+		return;
+	}
+
+	path = (enum rf_path)val[1];
+
+	if ((u8)val[2] == 0) {
+	/*@{0:-, 1:+} {Pwr Offset}*/
+		if (dm->support_ic_type & (ODM_RTL8195B | ODM_RTL8821C)) {
+			for (i = 0; i <= ODM_RATEMCS7; i++) {
+				pow = phydm_api_get_txagc(dm, path, i) - val[3];
+				rpt &= phydm_api_set_txagc(dm, pow, path, i, 1);
+			}
+			for (i = vht_start_rate; i <= ODM_RATEVHTSS1MCS9; i++) {
+				pow = phydm_api_get_txagc(dm, path, i) - val[3];
+				rpt &= phydm_api_set_txagc(dm, pow, path, i, 1);
+			}
+		} else if (dm->support_ic_type & (ODM_RTL8822B)) {
+			for (i = 0; i <= ODM_RATEMCS15; i++) {
+				pow = phydm_api_get_txagc(dm, path, i) - val[3];
+				rpt &= phydm_api_set_txagc(dm, pow, path, i, 1);
+			}
+			for (i = vht_start_rate; i <= ODM_RATEVHTSS2MCS9; i++) {
+				pow = phydm_api_get_txagc(dm, path, i) - val[3];
+				rpt &= phydm_api_set_txagc(dm, pow, path, i, 1);
+			}
+		} else if (dm->support_ic_type &
+			   (ODM_RTL8197F | ODM_RTL8192F)) {
+			for (i = 0; i <= ODM_RATEMCS15; i++) {
+				pow = phydm_api_get_txagc(dm, path, i) - val[3];
+				rpt &= phydm_api_set_txagc(dm, pow, path, i, 1);
+			}
+		} else if (dm->support_ic_type & (ODM_RTL8822C)) {
+			rpt &= phydm_api_shift_txagc(dm, val[3], path, 0);
+		}
+	} else if ((u8)val[2] == 1) {
+	/*@{0:-, 1:+} {Pwr Offset}*/
+		if (dm->support_ic_type & (ODM_RTL8195B | ODM_RTL8821C)) {
+			for (i = 0; i <= ODM_RATEMCS7; i++) {
+				pow = phydm_api_get_txagc(dm, path, i) + val[3];
+				rpt &= phydm_api_set_txagc(dm, pow, path, i, 1);
+			}
+			for (i = vht_start_rate; i <= ODM_RATEVHTSS1MCS9; i++) {
+				pow = phydm_api_get_txagc(dm, path, i) + val[3];
+				rpt &= phydm_api_set_txagc(dm, pow, path, i, 1);
+			}
+		} else if (dm->support_ic_type & (ODM_RTL8822B)) {
+			for (i = 0; i <= ODM_RATEMCS15; i++) {
+				pow = phydm_api_get_txagc(dm, path, i) + val[3];
+				rpt &= phydm_api_set_txagc(dm, pow, path, i, 1);
+			}
+			for (i = vht_start_rate; i <= ODM_RATEVHTSS2MCS9; i++) {
+				pow = phydm_api_get_txagc(dm, path, i) + val[3];
+				rpt &= phydm_api_set_txagc(dm, pow, path, i, 1);
+			}
+		} else if (dm->support_ic_type &
+			   (ODM_RTL8197F | ODM_RTL8192F)) {
+			for (i = 0; i <= ODM_RATEMCS15; i++) {
+				pow = phydm_api_get_txagc(dm, path, i) + val[3];
+				rpt &= phydm_api_set_txagc(dm, pow, path, i, 1);
+			}
+		} else if (dm->support_ic_type & (ODM_RTL8822C)) {
+			rpt &= phydm_api_shift_txagc(dm, val[3], path, 1);
+		}
+	}
+	PDM_SNPF(out_len, used, output + used, out_len - used,
+		 "[All rate] Set Path-%d Pow_idx: %s %d(%d.%s dB)\n",
+		 val[1], (val[2] ? "+" : "-"), val[3], val[3] >> 1,
+		 ((val[3] & 1) ? "5" : "0"));
+
+#endif
+	*_used = used;
+	*_out_len = out_len;
+}
+
+void phydm_set_txagc_dbg(void *dm_void, char input[][16], u32 *_used,
+			 char *output, u32 *_out_len)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	u32 used = *_used;
+	u32 out_len = *_out_len;
+	u32 var1[10] = {0};
+	char help[] = "-h";
+	u8 i = 0, input_idx = 0;
+
+	for (i = 0; i < 5; i++) {
+		if (input[i + 1]) {
+			PHYDM_SSCANF(input[i + 1], DCMD_HEX, &var1[i]);
+			input_idx++;
+		}
+	}
+
+	if ((strcmp(input[1], help) == 0)) {
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "{Dis:0, En:1} {pathA~D(0~3)} {rate_idx(Hex), All_rate:0xff} {txagc_idx (Hex)}\n");
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "{Pwr Shift(All rate):2} {pathA~D(0~3)} {0:-, 1:+} {Pwr Offset(dec)}\n");
+	} else if (var1[0] == 0) {
+		dm->is_disable_phy_api = true;
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "Disable API debug mode\n");
+	} else if (var1[0] == 1) {
+		dm->is_disable_phy_api = false;
+		phydm_set_txagc(dm, (u32 *)var1, &used, output, &out_len);
+		dm->is_disable_phy_api = true;
+	} else if (var1[0] == 2) {
+		PHYDM_SSCANF(input[4], DCMD_HEX, &var1[3]);
+		dm->is_disable_phy_api = false;
+		phydm_shift_txagc(dm, (u32 *)var1, &used, output, &out_len);
+		dm->is_disable_phy_api = true;
+	}
+
+	*_used = used;
+	*_out_len = out_len;
+}
+
+void phydm_debug_trace(void *dm_void, char input[][16], u32 *_used,
+		       char *output, u32 *_out_len)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	u64 pre_debug_components, one = 1;
+	u64 comp = 0;
+	u32 used = *_used;
+	u32 out_len = *_out_len;
+	u32 val[10] = {0};
+	u8 i;
+
+	for (i = 0; i < 5; i++) {
+		if (input[i + 1])
+			PHYDM_SSCANF(input[i + 1], DCMD_DECIMAL, &val[i]);
+	}
+	comp = dm->debug_components;
+	pre_debug_components = dm->debug_components;
+
+	PDM_SNPF(out_len, used, output + used, out_len - used,
+		 "\n================================\n");
+	if (val[0] == 100) {
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "[DBG MSG] Component Selection\n");
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "================================\n");
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "00. (( %s ))DIG\n",
+			 ((comp & DBG_DIG) ? ("V") : (".")));
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "01. (( %s ))RA_MASK\n",
+			 ((comp & DBG_RA_MASK) ? ("V") : (".")));
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "02. (( %s ))DYN_TXPWR\n",
+			 ((comp & DBG_DYN_TXPWR) ? ("V") : (".")));
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "03. (( %s ))FA_CNT\n",
+			 ((comp & DBG_FA_CNT) ? ("V") : (".")));
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "04. (( %s ))RSSI_MNTR\n",
+			 ((comp & DBG_RSSI_MNTR) ? ("V") : (".")));
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "05. (( %s ))CCKPD\n",
+			 ((comp & DBG_CCKPD) ? ("V") : (".")));
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "06. (( %s ))ANT_DIV\n",
+			 ((comp & DBG_ANT_DIV) ? ("V") : (".")));
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "07. (( %s ))SMT_ANT\n",
+			 ((comp & DBG_SMT_ANT) ? ("V") : (".")));
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "08. (( %s ))PWR_TRAIN\n",
+			 ((comp & DBG_PWR_TRAIN) ? ("V") : (".")));
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "09. (( %s ))RA\n",
+			 ((comp & DBG_RA) ? ("V") : (".")));
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "10. (( %s ))PATH_DIV\n",
+			 ((comp & DBG_PATH_DIV) ? ("V") : (".")));
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "11. (( %s ))DFS\n",
+			 ((comp & DBG_DFS) ? ("V") : (".")));
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "12. (( %s ))DYN_ARFR\n",
+			 ((comp & DBG_DYN_ARFR) ? ("V") : (".")));
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "13. (( %s ))ADAPTIVITY\n",
+			 ((comp & DBG_ADPTVTY) ? ("V") : (".")));
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "14. (( %s ))CFO_TRK\n",
+			 ((comp & DBG_CFO_TRK) ? ("V") : (".")));
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "15. (( %s ))ENV_MNTR\n",
+			 ((comp & DBG_ENV_MNTR) ? ("V") : (".")));
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "16. (( %s ))PRI_CCA\n",
+			 ((comp & DBG_PRI_CCA) ? ("V") : (".")));
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "17. (( %s ))ADPTV_SOML\n",
+			 ((comp & DBG_ADPTV_SOML) ? ("V") : (".")));
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "18. (( %s ))LNA_SAT_CHK\n",
+			 ((comp & DBG_LNA_SAT_CHK) ? ("V") : (".")));
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "20. (( %s ))PHY_STATUS\n",
+			 ((comp & DBG_PHY_STATUS) ? ("V") : (".")));
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "21. (( %s ))TMP\n",
+			 ((comp & DBG_TMP) ? ("V") : (".")));
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "22. (( %s ))FW_DBG_TRACE\n",
+			 ((comp & DBG_FW_TRACE) ? ("V") : (".")));
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "23. (( %s ))TXBF\n",
+			 ((comp & DBG_TXBF) ? ("V") : (".")));
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "24. (( %s ))COMMON_FLOW\n",
+			 ((comp & DBG_COMMON_FLOW) ? ("V") : (".")));
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "28. (( %s ))PHY_CONFIG\n",
+			 ((comp & ODM_PHY_CONFIG) ? ("V") : (".")));
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "29. (( %s ))INIT\n",
+			 ((comp & ODM_COMP_INIT) ? ("V") : (".")));
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "30. (( %s ))COMMON\n",
+			 ((comp & DBG_CMN) ? ("V") : (".")));
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "31. (( %s ))API\n",
+			 ((comp & ODM_COMP_API) ? ("V") : (".")));
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "================================\n");
+
+	} else if (val[0] == 101) {
+		dm->debug_components = 0;
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "Disable all debug components\n");
+	} else {
+		if (val[1] == 1) /*@enable*/
+			dm->debug_components |= (one << val[0]);
+		else if (val[1] == 2) /*@disable*/
+			dm->debug_components &= ~(one << val[0]);
+		else
+			PDM_SNPF(out_len, used, output + used, out_len - used,
+				 "[Warning]  1:on,  2:off\n");
+
+		if ((BIT(val[0]) == DBG_PHY_STATUS) && val[1] == 1) {
+			dm->phy_dbg_info.show_phy_sts_all_pkt = (u8)val[2];
+			dm->phy_dbg_info.show_phy_sts_max_cnt = (u16)val[3];
+
+			PDM_SNPF(out_len, used, output + used, out_len - used,
+				 "show_all_pkt=%d, show_max_num=%d\n\n",
+				 dm->phy_dbg_info.show_phy_sts_all_pkt,
+				 dm->phy_dbg_info.show_phy_sts_max_cnt);
+
+		} else if ((BIT(val[0]) == DBG_CMN) && (val[1] == 1)) {
+			dm->cmn_dbg_msg_period = (u8)val[2];
+
+			if (dm->cmn_dbg_msg_period < PHYDM_WATCH_DOG_PERIOD)
+				dm->cmn_dbg_msg_period = PHYDM_WATCH_DOG_PERIOD;
+
+			PDM_SNPF(out_len, used, output + used, out_len - used,
+				 "cmn_dbg_msg_period=%d\n",
+				 dm->cmn_dbg_msg_period);
+		}
+	}
+	PDM_SNPF(out_len, used, output + used, out_len - used,
+		 "pre-DbgComponents = 0x%llx\n", pre_debug_components);
+	PDM_SNPF(out_len, used, output + used, out_len - used,
+		 "Curr-DbgComponents = 0x%llx\n", dm->debug_components);
+	PDM_SNPF(out_len, used, output + used, out_len - used,
+		 "================================\n");
+
+	*_used = used;
+	*_out_len = out_len;
+}
+
+void phydm_fw_debug_trace(void *dm_void, char input[][16], u32 *_used,
+			  char *output, u32 *_out_len)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	u32 used = *_used;
+	u32 out_len = *_out_len;
+	u32 val[10] = {0};
+	u8 i, input_idx = 0;
+	u32 pre_fw_debug_components = 0, one = 1;
+	u32 comp = 0;
+
+	for (i = 0; i < 5; i++) {
+		if (input[i + 1]) {
+			PHYDM_SSCANF(input[i + 1], DCMD_DECIMAL, &val[i]);
+			input_idx++;
+		}
+	}
+
+	if (input_idx == 0)
+		return;
+
+	pre_fw_debug_components = dm->fw_debug_components;
+	comp = dm->fw_debug_components;
+
+	PDM_SNPF(out_len, used, output + used, out_len - used, "\n%s\n",
+		 "================================");
+	if (val[0] == 100) {
+		PDM_SNPF(out_len, used, output + used, out_len - used, "%s\n",
+			 "[FW Debug Component]");
+		PDM_SNPF(out_len, used, output + used, out_len - used, "%s\n",
+			 "================================");
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "00. (( %s ))RA\n",
+			 ((comp & PHYDM_FW_COMP_RA) ? ("V") : (".")));
+
+		if (dm->support_ic_type & PHYDM_IC_3081_SERIES) {
+			PDM_SNPF(out_len, used, output + used, out_len - used,
+				 "01. (( %s ))MU\n",
+				 ((comp & PHYDM_FW_COMP_MU) ? ("V") : (".")));
+			PDM_SNPF(out_len, used, output + used, out_len - used,
+				 "02. (( %s ))path Div\n",
+				 ((comp &
+				 PHYDM_FW_COMP_PATH_DIV) ? ("V") : (".")));
+			PDM_SNPF(out_len, used, output + used, out_len - used,
+				 "03. (( %s ))Power training\n",
+				 ((comp & PHYDM_FW_COMP_PT) ? ("V") : (".")));
+		}
+		PDM_SNPF(out_len, used, output + used, out_len - used, "%s\n",
+			 "================================");
+
+	} else {
+		if (val[0] == 101) {
+			dm->fw_debug_components = 0;
+			PDM_SNPF(out_len, used, output + used, out_len - used,
+				 "%s\n", "Clear all fw debug components");
+		} else {
+			if (val[1] == 1) /*@enable*/
+				dm->fw_debug_components |= (one << val[0]);
+			else if (val[1] == 2) /*@disable*/
+				dm->fw_debug_components &= ~(one << val[0]);
+			else
+				PDM_SNPF(out_len, used, output + used,
+					 out_len - used, "%s\n",
+					 "[Warning!!!]  1:enable,  2:disable");
+		}
+
+		comp = dm->fw_debug_components;
+
+		if (comp == 0) {
+			dm->debug_components &= ~DBG_FW_TRACE;
+			/*@H2C to enable C2H Msg*/
+			phydm_fw_trace_en_h2c(dm, false, comp, val[2], val[3]);
+		} else {
+			dm->debug_components |= DBG_FW_TRACE;
+			/*@H2C to enable C2H Msg*/
+			phydm_fw_trace_en_h2c(dm, true, comp, val[2], val[3]);
+		}
+	}
+}
+
+#if (ODM_IC_11N_SERIES_SUPPORT)
+void phydm_dump_bb_reg_n(void *dm_void, u32 *_used, char *output, u32 *_out_len)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	u32 addr = 0;
+	u32 used = *_used;
+	u32 out_len = *_out_len;
+
+	/*@For Nseries IC we only need to dump page8 to pageF using 3 digits*/
+	for (addr = 0x800; addr < 0xfff; addr += 4) {
+		PDM_VAST_SNPF(out_len, used, output + used, out_len - used,
+			      "0x%03x 0x%08x\n",
+			      addr, odm_get_bb_reg(dm, addr, MASKDWORD));
+	}
+
+	*_used = used;
+	*_out_len = out_len;
+}
+#endif
+
+#if (ODM_IC_11AC_SERIES_SUPPORT)
+void phydm_dump_bb_reg_ac(void *dm_void, u32 *_used, char *output,
+			  u32 *_out_len)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	u32 addr = 0;
+	u32 used = *_used;
+	u32 out_len = *_out_len;
+
+	for (addr = 0x800; addr < 0xfff; addr += 4) {
+		PDM_VAST_SNPF(out_len, used, output + used, out_len - used,
+			      "0x%04x 0x%08x\n",
+			      addr, odm_get_bb_reg(dm, addr, MASKDWORD));
+	}
+
+	if (!(dm->support_ic_type &
+	    (ODM_RTL8822B | ODM_RTL8814A | ODM_RTL8821C)))
+		goto rpt_reg;
+
+	if (dm->rf_type > RF_2T2R) {
+		for (addr = 0x1800; addr < 0x18ff; addr += 4)
+			PDM_VAST_SNPF(out_len, used, output + used,
+				      out_len - used, "0x%04x 0x%08x\n",
+				      addr,
+				      odm_get_bb_reg(dm, addr, MASKDWORD));
+	}
+
+	if (dm->rf_type > RF_3T3R) {
+		for (addr = 0x1a00; addr < 0x1aff; addr += 4)
+			PDM_VAST_SNPF(out_len, used, output + used,
+				      out_len - used, "0x%04x 0x%08x\n",
+				      addr,
+				      odm_get_bb_reg(dm, addr, MASKDWORD));
+	}
+
+	for (addr = 0x1900; addr < 0x19ff; addr += 4)
+		PDM_VAST_SNPF(out_len, used, output + used, out_len - used,
+			      "0x%04x 0x%08x\n",
+			      addr, odm_get_bb_reg(dm, addr, MASKDWORD));
+
+	for (addr = 0x1c00; addr < 0x1cff; addr += 4)
+		PDM_VAST_SNPF(out_len, used, output + used, out_len - used,
+			      "0x%04x 0x%08x\n",
+			      addr, odm_get_bb_reg(dm, addr, MASKDWORD));
+
+	for (addr = 0x1f00; addr < 0x1fff; addr += 4)
+		PDM_VAST_SNPF(out_len, used, output + used, out_len - used,
+			      "0x%04x 0x%08x\n",
+			      addr, odm_get_bb_reg(dm, addr, MASKDWORD));
+
+rpt_reg:
+
+	*_used = used;
+	*_out_len = out_len;
+}
+
+#endif
+
+void phydm_dump_bb_reg(void *dm_void, u32 *_used, char *output, u32 *_out_len)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	u32 used = *_used;
+	u32 out_len = *_out_len;
+
+	PDM_VAST_SNPF(out_len, used, output + used, out_len - used,
+		      "BB==========\n");
+
+	if (dm->support_ic_type & ODM_IC_11N_SERIES)
+#if (ODM_IC_11N_SERIES_SUPPORT)
+		phydm_dump_bb_reg_n(dm, &used, output, &out_len);
+#else
+		;
+#endif
+	else
+#if (ODM_IC_11AC_SERIES_SUPPORT)
+		phydm_dump_bb_reg_ac(dm, &used, output, &out_len);
+#else
+		;
+#endif
+
+	*_used = used;
+	*_out_len = out_len;
+}
+
+void phydm_dump_rf_reg(void *dm_void, u32 *_used, char *output, u32 *_out_len)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	u32 addr = 0;
+	u32 used = *_used;
+	u32 out_len = *_out_len;
+	u32 reg = 0;
+
+	/* @dump RF register */
+	PDM_VAST_SNPF(out_len, used, output + used, out_len - used,
+		      "RF-A==========\n");
+
+	for (addr = 0; addr < 0xFF; addr++) {
+		reg = odm_get_rf_reg(dm, RF_PATH_A, addr, RFREG_MASK);
+		PDM_VAST_SNPF(out_len, used, output + used, out_len - used,
+			      "0x%02x 0x%05x\n", addr, reg);
+		}
+
+#ifdef PHYDM_COMPILE_ABOVE_2SS
+	if (dm->rf_type > RF_1T1R) {
+		PDM_VAST_SNPF(out_len, used, output + used, out_len - used,
+			      "RF-B==========\n");
+
+		for (addr = 0; addr < 0xFF; addr++) {
+			reg = odm_get_rf_reg(dm, RF_PATH_B, addr, RFREG_MASK);
+			PDM_VAST_SNPF(out_len, used, output + used,
+				      out_len - used, "0x%02x 0x%05x\n",
+				      addr, reg);
+		}
+	}
+#endif
+
+#ifdef PHYDM_COMPILE_ABOVE_3SS
+	if (dm->rf_type > RF_2T2R) {
+		PDM_VAST_SNPF(out_len, used, output + used, out_len - used,
+			      "RF-C==========\n");
+
+		for (addr = 0; addr < 0xFF; addr++) {
+			reg = odm_get_rf_reg(dm, RF_PATH_C, addr, RFREG_MASK);
+			PDM_VAST_SNPF(out_len, used, output + used,
+				      out_len - used, "0x%02x 0x%05x\n",
+				      addr, reg);
+		}
+	}
+#endif
+
+#ifdef PHYDM_COMPILE_ABOVE_4SS
+	if (dm->rf_type > RF_3T3R) {
+		PDM_VAST_SNPF(out_len, used, output + used, out_len - used,
+			      "RF-D==========\n");
+
+		for (addr = 0; addr < 0xFF; addr++) {
+			reg = odm_get_rf_reg(dm, RF_PATH_D, addr, RFREG_MASK);
+			PDM_VAST_SNPF(out_len, used, output + used,
+				      out_len - used, "0x%02x 0x%05x\n",
+				      addr, reg);
+		}
+	}
+#endif
+
+	*_used = used;
+	*_out_len = out_len;
+}
+
+void phydm_dump_mac_reg(void *dm_void, u32 *_used, char *output, u32 *_out_len)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	u32 addr = 0;
+	u32 used = *_used;
+	u32 out_len = *_out_len;
+
+	/* @dump MAC register */
+	PDM_VAST_SNPF(out_len, used, output + used, out_len - used,
+		      "MAC==========\n");
+
+	for (addr = 0; addr < 0x7ff; addr += 4)
+		PDM_VAST_SNPF(out_len, used, output + used, out_len - used,
+			      "0x%04x 0x%08x\n",
+			      addr, odm_get_bb_reg(dm, addr, MASKDWORD));
+
+	for (addr = 0x1000; addr < 0x17ff; addr += 4)
+		PDM_VAST_SNPF(out_len, used, output + used, out_len - used,
+			      "0x%04x 0x%08x\n",
+			      addr, odm_get_bb_reg(dm, addr, MASKDWORD));
+
+	*_used = used;
+	*_out_len = out_len;
+}
+
+void phydm_dump_reg(void *dm_void, char input[][16], u32 *_used, char *output,
+		    u32 *_out_len)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	char help[] = "-h";
+	u32 var1[10] = {0};
+	u32 used = *_used;
+	u32 out_len = *_out_len;
+
+	if (input[1])
+		PHYDM_SSCANF(input[1], DCMD_DECIMAL, &var1[0]);
+
+	PHYDM_SSCANF(input[1], DCMD_DECIMAL, &var1[0]);
+
+	if ((strcmp(input[1], help) == 0)) {
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "dumpreg {0:all, 1:BB, 2:RF, 3:MAC}\n");
+	} else if (var1[0] == 0) {
+		phydm_dump_mac_reg(dm, &used, output, &out_len);
+		phydm_dump_bb_reg(dm, &used, output, &out_len);
+		phydm_dump_rf_reg(dm, &used, output, &out_len);
+	} else if (var1[0] == 1) {
+		phydm_dump_bb_reg(dm, &used, output, &out_len);
+	} else if (var1[0] == 2) {
+		phydm_dump_rf_reg(dm, &used, output, &out_len);
+	} else if (var1[0] == 3) {
+		phydm_dump_mac_reg(dm, &used, output, &out_len);
+	}
+
+	*_used = used;
+	*_out_len = out_len;
+}
+
+void phydm_enable_big_jump(void *dm_void, char input[][16], u32 *_used,
+			   char *output, u32 *_out_len)
+{
+#if (RTL8822B_SUPPORT)
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
+	u32 dm_value[10] = {0};
+	u8 i, input_idx = 0;
+	u32 val;
+
+	if (!(dm->support_ic_type & ODM_RTL8822B))
+		return;
+
+	for (i = 0; i < 5; i++) {
+		if (input[i + 1]) {
+			PHYDM_SSCANF(input[i + 1], DCMD_HEX, &dm_value[i]);
+			input_idx++;
+		}
+	}
+
+	if (input_idx == 0)
+		return;
+
+	if (dm_value[0] == 0) {
+		dm->dm_dig_table.enable_adjust_big_jump = false;
+
+		val = (dig_t->big_jump_step3 << 5) |
+		      (dig_t->big_jump_step2 << 3) |
+		      dig_t->big_jump_step1;
+
+		odm_set_bb_reg(dm, R_0x8c8, 0xfe, val);
+	} else {
+		dm->dm_dig_table.enable_adjust_big_jump = true;
+	}
+#endif
+}
+
+void phydm_show_rx_rate(void *dm_void, char input[][16], u32 *_used,
+			char *output, u32 *_out_len)
+{
+#if (RTL8822B_SUPPORT | RTL8821C_SUPPORT | RTL8814B_SUPPORT | RTL8195B_SUPPORT)
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct odm_phy_dbg_info *dbg = &dm->phy_dbg_info;
+	u32 used = *_used;
+	u32 out_len = *_out_len;
+	u32 var1[10] = {0};
+	char help[] = "-h";
+	u8 i, input_idx = 0;
+
+	for (i = 0; i < 5; i++) {
+		if (input[i + 1]) {
+			PHYDM_SSCANF(input[i + 1], DCMD_HEX, &var1[i]);
+			input_idx++;
+		}
+	}
+
+	if (input_idx == 0)
+		return;
+
+	if ((strcmp(input[1], help) == 0)) {
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "{1: show Rx rate, 0:reset counter}\n");
+		*_used = used;
+		*_out_len = out_len;
+		return;
+
+	} else if (var1[0] == 0) {
+		phydm_reset_rx_rate_distribution(dm);
+		*_used = used;
+		*_out_len = out_len;
+		return;
+	}
+
+	/* @==Show SU Rate====================================================*/
+	PDM_SNPF(out_len, used, output + used, out_len - used,
+		 "=====Rx SU rate Statistics=====\n");
+	PDM_SNPF(out_len, used, output + used, out_len - used,
+		 "[SU][1SS] {%d, %d, %d, %d | %d, %d, %d, %d | %d, %d}\n",
+		 dbg->num_qry_vht_pkt[0], dbg->num_qry_vht_pkt[1],
+		 dbg->num_qry_vht_pkt[2], dbg->num_qry_vht_pkt[3],
+		 dbg->num_qry_vht_pkt[4], dbg->num_qry_vht_pkt[5],
+		 dbg->num_qry_vht_pkt[6], dbg->num_qry_vht_pkt[7],
+		 dbg->num_qry_vht_pkt[8], dbg->num_qry_vht_pkt[9]);
+
+	#if (defined(PHYDM_COMPILE_ABOVE_2SS))
+	if (dm->support_ic_type & (PHYDM_IC_ABOVE_2SS)) {
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "[SU][2SS] {%d, %d, %d, %d | %d, %d, %d, %d | %d, %d}\n",
+			 dbg->num_qry_vht_pkt[10], dbg->num_qry_vht_pkt[11],
+			 dbg->num_qry_vht_pkt[12], dbg->num_qry_vht_pkt[13],
+			 dbg->num_qry_vht_pkt[14], dbg->num_qry_vht_pkt[15],
+			 dbg->num_qry_vht_pkt[16], dbg->num_qry_vht_pkt[17],
+			 dbg->num_qry_vht_pkt[18], dbg->num_qry_vht_pkt[19]);
+	}
+	#endif
+	/* @==Show MU Rate====================================================*/
+#if (ODM_PHY_STATUS_NEW_TYPE_SUPPORT) || (defined(PHYSTS_3RD_TYPE_SUPPORT))
+	PDM_SNPF(out_len, used, output + used, out_len - used,
+		 "=====Rx MU rate Statistics=====\n");
+	PDM_SNPF(out_len, used, output + used, out_len - used,
+		 "[MU][1SS] {%d, %d, %d, %d | %d, %d, %d, %d | %d, %d}\n",
+		 dbg->num_mu_vht_pkt[0], dbg->num_mu_vht_pkt[1],
+		 dbg->num_mu_vht_pkt[2], dbg->num_mu_vht_pkt[3],
+		 dbg->num_mu_vht_pkt[4], dbg->num_mu_vht_pkt[5],
+		 dbg->num_mu_vht_pkt[6], dbg->num_mu_vht_pkt[7],
+		 dbg->num_mu_vht_pkt[8], dbg->num_mu_vht_pkt[9]);
+
+	#if (defined(PHYDM_COMPILE_ABOVE_2SS))
+	if (dm->support_ic_type & (PHYDM_IC_ABOVE_2SS)) {
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "[MU][2SS] {%d, %d, %d, %d | %d, %d, %d, %d | %d, %d}\n",
+			 dbg->num_mu_vht_pkt[10], dbg->num_mu_vht_pkt[11],
+			 dbg->num_mu_vht_pkt[12], dbg->num_mu_vht_pkt[13],
+			 dbg->num_mu_vht_pkt[14], dbg->num_mu_vht_pkt[15],
+			 dbg->num_mu_vht_pkt[16], dbg->num_mu_vht_pkt[17],
+			 dbg->num_mu_vht_pkt[18], dbg->num_mu_vht_pkt[19]);
+	}
+	#endif
+#endif
+	*_used = used;
+	*_out_len = out_len;
+#endif
+}
+
+void phydm_per_tone_evm(void *dm_void, char input[][16], u32 *_used,
+			char *output, u32 *_out_len)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	u8 i, j;
+	u32 used = *_used;
+	u32 out_len = *_out_len;
+	u32 var1[4] = {0};
+	u32 val, tone_num, round;
+	s8 rxevm_0, rxevm_1;
+	s32 avg_num, evm_tone_0[256] = {0}, evm_tone_1[256] = {0};
+	s32 rxevm_sum_0, rxevm_sum_1;
+
+	if (dm->support_ic_type & ODM_IC_11N_SERIES) {
+		pr_debug("n series not support yet !\n");
+		return;
+	}
+
+	for (i = 0; i < 4; i++) {
+		if (input[i + 1])
+			PHYDM_SSCANF(input[i + 1], DCMD_DECIMAL, &var1[i]);
+	}
+
+	avg_num = var1[0];
+	round = var1[1];
+
+	if (!dm->is_linked) {
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "No Link !!\n");
+
+		*_used = used;
+		*_out_len = out_len;
+
+		return;
+	}
+
+	pr_debug("ID=((%d)), BW=((%d)), fc=((CH-%d))\n", dm->curr_station_id,
+		 20 << *dm->band_width, *dm->channel);
+	pr_debug("avg_num =((%d)), round =((%d))\n", avg_num, round);
+#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
+	watchdog_stop(dm->priv);
+#endif
+	for (j = 0; j < round; j++) {
+		pr_debug("\nround((%d))\n", (j + 1));
+		if (*dm->band_width == CHANNEL_WIDTH_20) {
+			for (tone_num = 228; tone_num <= 255; tone_num++) {
+				odm_set_bb_reg(dm, R_0x8c4, 0xff8, tone_num);
+				rxevm_sum_0 = 0;
+				rxevm_sum_1 = 0;
+				for (i = 0; i < avg_num; i++) {
+					val = odm_read_4byte(dm, R_0xf8c);
+
+					rxevm_0 = (s8)((val & MASKBYTE2) >> 16);
+					rxevm_0 = (rxevm_0 / 2);
+					if (rxevm_0 < -63)
+						rxevm_0 = 0;
+
+					rxevm_1 = (s8)((val & MASKBYTE3) >> 24);
+					rxevm_1 = (rxevm_1 / 2);
+					if (rxevm_1 < -63)
+						rxevm_1 = 0;
+					rxevm_sum_0 += rxevm_0;
+					rxevm_sum_1 += rxevm_1;
+					ODM_delay_ms(1);
+				}
+				evm_tone_0[tone_num] = (rxevm_sum_0 / avg_num);
+				evm_tone_1[tone_num] = (rxevm_sum_1 / avg_num);
+				pr_debug("Tone(-%-3d) RXEVM(1ss/2ss)=%d, %d\n",
+					 (256 - tone_num), evm_tone_0[tone_num],
+					 evm_tone_1[tone_num]);
+			}
+
+			for (tone_num = 1; tone_num <= 28; tone_num++) {
+				odm_set_bb_reg(dm, R_0x8c4, 0xff8, tone_num);
+				rxevm_sum_0 = 0;
+				rxevm_sum_1 = 0;
+				for (i = 0; i < avg_num; i++) {
+					val = odm_read_4byte(dm, R_0xf8c);
+
+					rxevm_0 = (s8)((val & MASKBYTE2) >> 16);
+					rxevm_0 = (rxevm_0 / 2);
+					if (rxevm_0 < -63)
+						rxevm_0 = 0;
+
+					rxevm_1 = (s8)((val & MASKBYTE3) >> 24);
+					rxevm_1 = (rxevm_1 / 2);
+					if (rxevm_1 < -63)
+						rxevm_1 = 0;
+					rxevm_sum_0 += rxevm_0;
+					rxevm_sum_1 += rxevm_1;
+					ODM_delay_ms(1);
+				}
+				evm_tone_0[tone_num] = (rxevm_sum_0 / avg_num);
+				evm_tone_1[tone_num] = (rxevm_sum_1 / avg_num);
+				pr_debug("Tone(%-3d) RXEVM(1ss/2ss)=%d, %d\n",
+					 tone_num, evm_tone_0[tone_num],
+					 evm_tone_1[tone_num]);
+			}
+		} else if (*dm->band_width == CHANNEL_WIDTH_40) {
+			for (tone_num = 198; tone_num <= 254; tone_num++) {
+				odm_set_bb_reg(dm, R_0x8c4, 0xff8, tone_num);
+				rxevm_sum_0 = 0;
+				rxevm_sum_1 = 0;
+				for (i = 0; i < avg_num; i++) {
+					val = odm_read_4byte(dm, R_0xf8c);
+
+					rxevm_0 = (s8)((val & MASKBYTE2) >> 16);
+					rxevm_0 = (rxevm_0 / 2);
+					if (rxevm_0 < -63)
+						rxevm_0 = 0;
+
+					rxevm_1 = (s8)((val & MASKBYTE3) >> 24);
+					rxevm_1 = (rxevm_1 / 2);
+					if (rxevm_1 < -63)
+						rxevm_1 = 0;
+
+					rxevm_sum_0 += rxevm_0;
+					rxevm_sum_1 += rxevm_1;
+					ODM_delay_ms(1);
+				}
+				evm_tone_0[tone_num] = (rxevm_sum_0 / avg_num);
+				evm_tone_1[tone_num] = (rxevm_sum_1 / avg_num);
+				pr_debug("Tone(-%-3d) RXEVM(1ss/2ss)=%d, %d\n",
+					 (256 - tone_num), evm_tone_0[tone_num],
+					 evm_tone_1[tone_num]);
+			}
+
+			for (tone_num = 2; tone_num <= 58; tone_num++) {
+				odm_set_bb_reg(dm, R_0x8c4, 0xff8, tone_num);
+				rxevm_sum_0 = 0;
+				rxevm_sum_1 = 0;
+				for (i = 0; i < avg_num; i++) {
+					val = odm_read_4byte(dm, R_0xf8c);
+
+					rxevm_0 = (s8)((val & MASKBYTE2) >> 16);
+					rxevm_0 = (rxevm_0 / 2);
+					if (rxevm_0 < -63)
+						rxevm_0 = 0;
+
+					rxevm_1 = (s8)((val & MASKBYTE3) >> 24);
+					rxevm_1 = (rxevm_1 / 2);
+					if (rxevm_1 < -63)
+						rxevm_1 = 0;
+					rxevm_sum_0 += rxevm_0;
+					rxevm_sum_1 += rxevm_1;
+					ODM_delay_ms(1);
+				}
+				evm_tone_0[tone_num] = (rxevm_sum_0 / avg_num);
+				evm_tone_1[tone_num] = (rxevm_sum_1 / avg_num);
+				pr_debug("Tone(%-3d) RXEVM(1ss/2ss)=%d, %d\n",
+					 tone_num, evm_tone_0[tone_num],
+					 evm_tone_1[tone_num]);
+			}
+		} else if (*dm->band_width == CHANNEL_WIDTH_80) {
+			for (tone_num = 134; tone_num <= 254; tone_num++) {
+				odm_set_bb_reg(dm, R_0x8c4, 0xff8, tone_num);
+				rxevm_sum_0 = 0;
+				rxevm_sum_1 = 0;
+				for (i = 0; i < avg_num; i++) {
+					val = odm_read_4byte(dm, R_0xf8c);
+
+					rxevm_0 = (s8)((val & MASKBYTE2) >> 16);
+					rxevm_0 = (rxevm_0 / 2);
+					if (rxevm_0 < -63)
+						rxevm_0 = 0;
+
+					rxevm_1 = (s8)((val & MASKBYTE3) >> 24);
+					rxevm_1 = (rxevm_1 / 2);
+					if (rxevm_1 < -63)
+						rxevm_1 = 0;
+					rxevm_sum_0 += rxevm_0;
+					rxevm_sum_1 += rxevm_1;
+					ODM_delay_ms(1);
+				}
+				evm_tone_0[tone_num] = (rxevm_sum_0 / avg_num);
+				evm_tone_1[tone_num] = (rxevm_sum_1 / avg_num);
+				pr_debug("Tone(-%-3d) RXEVM(1ss/2ss)=%d, %d\n",
+					 (256 - tone_num), evm_tone_0[tone_num],
+					 evm_tone_1[tone_num]);
+			}
+
+			for (tone_num = 2; tone_num <= 122; tone_num++) {
+				odm_set_bb_reg(dm, R_0x8c4, 0xff8, tone_num);
+				rxevm_sum_0 = 0;
+				rxevm_sum_1 = 0;
+				for (i = 0; i < avg_num; i++) {
+					val = odm_read_4byte(dm, R_0xf8c);
+
+					rxevm_0 = (s8)((val & MASKBYTE2) >> 16);
+					rxevm_0 = (rxevm_0 / 2);
+					if (rxevm_0 < -63)
+						rxevm_0 = 0;
+
+					rxevm_1 = (s8)((val & MASKBYTE3) >> 24);
+					rxevm_1 = (rxevm_1 / 2);
+					if (rxevm_1 < -63)
+						rxevm_1 = 0;
+					rxevm_sum_0 += rxevm_0;
+					rxevm_sum_1 += rxevm_1;
+					ODM_delay_ms(1);
+				}
+				evm_tone_0[tone_num] = (rxevm_sum_0 / avg_num);
+				evm_tone_1[tone_num] = (rxevm_sum_1 / avg_num);
+				pr_debug("Tone(%-3d) RXEVM (1ss/2ss)=%d, %d\n",
+					 tone_num, evm_tone_0[tone_num],
+					 evm_tone_1[tone_num]);
+			}
+		}
+	}
+	*_used = used;
+	*_out_len = out_len;
+}
+
+void phydm_api_adjust(void *dm_void, char input[][16], u32 *_used, char *output,
+		      u32 *_out_len)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	char help[] = "-h";
+	u32 var1[10] = {0};
+	u32 used = *_used;
+	u32 out_len = *_out_len;
+	u8 i;
+	boolean is_enable_dbg_mode;
+	u8 central_ch, primary_ch_idx;
+	enum channel_width bw;
+
+#ifdef PHYDM_COMMON_API_SUPPORT
+
+	if ((strcmp(input[1], help) == 0)) {
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "{en} {CH} {pr_ch 1/2/3/4/9/10} {0:20M,1:40M,2:80M}\n");
+		goto out;
+	}
+
+	if (!(dm->support_ic_type & CMN_API_SUPPORT_IC)) {
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "This IC doesn't support PHYDM API function\n");
+		goto out;
+	}
+
+	for (i = 0; i < 4; i++) {
+		if (input[i + 1])
+			PHYDM_SSCANF(input[i + 1], DCMD_DECIMAL, &var1[i]);
+	}
+
+	is_enable_dbg_mode = (boolean)var1[0];
+	central_ch = (u8)var1[1];
+	primary_ch_idx = (u8)var1[2];
+	bw = (enum channel_width)var1[3];
+
+	if (is_enable_dbg_mode) {
+		dm->is_disable_phy_api = false;
+		phydm_api_switch_bw_channel(dm, central_ch, primary_ch_idx, bw);
+		dm->is_disable_phy_api = true;
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "central_ch = %d, primary_ch_idx = %d, bw = %d\n",
+			 central_ch, primary_ch_idx, bw);
+	} else {
+		dm->is_disable_phy_api = false;
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "Disable API debug mode\n");
+	}
+out:
+#else
+	PDM_SNPF(out_len, used, output + used, out_len - used,
+		 "This IC doesn't support PHYDM API function\n");
+#endif
+
+	*_used = used;
+	*_out_len = out_len;
+}
+
+void phydm_parameter_adjust(void *dm_void, char input[][16], u32 *_used,
+			    char *output, u32 *_out_len)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct phydm_cfo_track_struct *cfo_track = &dm->dm_cfo_track;
+	char help[] = "-h";
+	u32 var1[10] = {0};
+	u32 used = *_used;
+	u32 out_len = *_out_len;
+
+	if ((strcmp(input[1], help) == 0)) {
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "1. X_cap = ((0x%x))\n", cfo_track->crystal_cap);
+
+	} else {
+		PHYDM_SSCANF(input[1], DCMD_DECIMAL, &var1[0]);
+
+		if (var1[0] == 0) {
+			PHYDM_SSCANF(input[2], DCMD_HEX, &var1[1]);
+			phydm_set_crystal_cap(dm, (u8)var1[1]);
+			PDM_SNPF(out_len, used, output + used, out_len - used,
+				 "X_cap = ((0x%x))\n", cfo_track->crystal_cap);
+		}
+	}
+	*_used = used;
+	*_out_len = out_len;
+}
+
+void phydm_ext_rf_element_ctrl(void *dm_void, char input[][16], u32 *_used,
+			       char *output, u32 *_out_len)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	u32 val[10] = {0};
+	u8 i = 0, input_idx = 0;
+
+	for (i = 0; i < 5; i++) {
+		if (input[i + 1]) {
+			PHYDM_SSCANF(input[i + 1], DCMD_DECIMAL, &val[i]);
+			input_idx++;
+		}
+	}
+
+	if (input_idx == 0)
+		return;
+
+	if (val[0] == 1) /*@ext switch*/ {
+		phydm_set_ext_switch(dm, val[1]);
+	}
+}
+
+void phydm_print_dbgport(void *dm_void, char input[][16], u32 *_used,
+			 char *output, u32 *_out_len)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	char help[] = "-h";
+	u32 var1[10] = {0};
+	u32 used = *_used;
+	u32 out_len = *_out_len;
+	u32 dbg_port_value = 0;
+	u8 val[32];
+	u8 tmp = 0;
+	u8 i;
+
+	if (strcmp(input[1], help) == 0) {
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "{dbg_port_idx}\n");
+		goto out;
+	}
+
+	PHYDM_SSCANF(input[1], DCMD_HEX, &var1[0]);
+
+	dm->debug_components |= ODM_COMP_API;
+	if (phydm_set_bb_dbg_port(dm, DBGPORT_PRI_3, var1[0])) {
+		dbg_port_value = phydm_get_bb_dbg_port_val(dm);
+		phydm_release_bb_dbg_port(dm);
+
+		for (i = 0; i < 32; i++)
+			val[i] = (u8)((dbg_port_value & BIT(i)) >> i);
+
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "Dbg Port[0x%x] = ((0x%x))\n", var1[0],
+			 dbg_port_value);
+
+		for (i = 4; i != 0; i--) {
+			tmp = 8 * (i - 1);
+			PDM_SNPF(out_len, used, output + used, out_len - used,
+				 "val[%d:%d] = 8b'%d %d %d %d %d %d %d %d\n",
+				 tmp + 7, tmp, val[tmp + 7], val[tmp + 6],
+				 val[tmp + 5], val[tmp + 4], val[tmp + 3],
+				 val[tmp + 2], val[tmp + 1], val[tmp + 0]);
+		}
+	}
+	dm->debug_components &= (~ODM_COMP_API);
+out:
+	*_used = used;
+	*_out_len = out_len;
+}
+
+struct phydm_command {
+	char name[16];
+	u8 id;
+};
+
+enum PHYDM_CMD_ID {
+	PHYDM_HELP,
+	PHYDM_DEMO,
+	PHYDM_RF_CMD,
+	PHYDM_DIG,
+	PHYDM_RA,
+	PHYDM_PROFILE,
+	PHYDM_ANTDIV,
+	PHYDM_PATHDIV,
+	PHYDM_DEBUG,
+	PHYDM_FW_DEBUG,
+	PHYDM_SUPPORT_ABILITY,
+	PHYDM_GET_TXAGC,
+	PHYDM_SET_TXAGC,
+	PHYDM_SMART_ANT,
+	PHYDM_API,
+	PHYDM_TRX_PATH,
+	PHYDM_LA_MODE,
+	PHYDM_DUMP_REG,
+	PHYDM_AUTO_DBG,
+	PHYDM_BIG_JUMP,
+	PHYDM_SHOW_RXRATE,
+	PHYDM_NBI_EN,
+	PHYDM_CSI_MASK_EN,
+	PHYDM_DFS_DEBUG,
+	PHYDM_NHM,
+	PHYDM_CLM,
+	PHYDM_FAHM,
+	PHYDM_ENV_MNTR,
+	PHYDM_BB_INFO,
+	PHYDM_TXBF,
+	PHYDM_H2C,
+	PHYDM_EXT_RF_E_CTRL,
+	PHYDM_ADAPTIVE_SOML,
+	PHYDM_PSD,
+	PHYDM_DEBUG_PORT,
+	PHYDM_DIS_HTSTF_CONTROL,
+	PHYDM_TUNE_PARAMETER,
+	PHYDM_ADAPTIVITY_DEBUG,
+	PHYDM_DIS_DYM_ANT_WEIGHTING,
+	PHYDM_FORECE_PT_STATE,
+	PHYDM_DIS_RXHP_CTR,
+	PHYDM_STA_INFO,
+	PHYDM_PAUSE_FUNC,
+	PHYDM_PER_TONE_EVM,
+	PHYDM_DYN_TXPWR,
+	PHYDM_LNA_SAT
+};
+
+struct phydm_command phy_dm_ary[] = {
+	{"-h", PHYDM_HELP}, /*@do not move this element to other position*/
+	{"demo", PHYDM_DEMO}, /*@do not move this element to other position*/
+	{"rf", PHYDM_RF_CMD},
+	{"dig", PHYDM_DIG},
+	{"ra", PHYDM_RA},
+	{"profile", PHYDM_PROFILE},
+	{"antdiv", PHYDM_ANTDIV},
+	{"pathdiv", PHYDM_PATHDIV},
+	{"dbg", PHYDM_DEBUG},
+	{"fw_dbg", PHYDM_FW_DEBUG},
+	{"ability", PHYDM_SUPPORT_ABILITY},
+	{"get_txagc", PHYDM_GET_TXAGC},
+	{"set_txagc", PHYDM_SET_TXAGC},
+	{"smtant", PHYDM_SMART_ANT},
+	{"api", PHYDM_API},
+	{"trxpath", PHYDM_TRX_PATH},
+	{"lamode", PHYDM_LA_MODE},
+	{"dumpreg", PHYDM_DUMP_REG},
+	{"auto_dbg", PHYDM_AUTO_DBG},
+	{"bigjump", PHYDM_BIG_JUMP},
+	{"rxrate", PHYDM_SHOW_RXRATE},
+	{"nbi", PHYDM_NBI_EN},
+	{"csi_mask", PHYDM_CSI_MASK_EN},
+	{"dfs", PHYDM_DFS_DEBUG},
+	{"nhm", PHYDM_NHM},
+	{"clm", PHYDM_CLM},
+	{"fahm", PHYDM_FAHM},
+	{"env_mntr", PHYDM_ENV_MNTR},
+	{"bbinfo", PHYDM_BB_INFO},
+	{"txbf", PHYDM_TXBF},
+	{"h2c", PHYDM_H2C},
+	{"ext_rfe", PHYDM_EXT_RF_E_CTRL},
+	{"soml", PHYDM_ADAPTIVE_SOML},
+	{"psd", PHYDM_PSD},
+	{"dbgport", PHYDM_DEBUG_PORT},
+	{"dis_htstf", PHYDM_DIS_HTSTF_CONTROL},
+	{"tune_para", PHYDM_TUNE_PARAMETER},
+	{"adapt_debug", PHYDM_ADAPTIVITY_DEBUG},
+	{"dis_dym_ant_wgt", PHYDM_DIS_DYM_ANT_WEIGHTING},
+	{"force_pt_state", PHYDM_FORECE_PT_STATE},
+	{"dis_drxhp", PHYDM_DIS_RXHP_CTR},
+	{"sta_info", PHYDM_STA_INFO},
+	{"pause", PHYDM_PAUSE_FUNC},
+	{"evm", PHYDM_PER_TONE_EVM},
+	{"dyn_txpwr", PHYDM_DYN_TXPWR},
+	{"lna_sat", PHYDM_LNA_SAT} };
+
+#endif /*@#ifdef CONFIG_PHYDM_DEBUG_FUNCTION*/
+
+void phydm_cmd_parser(struct dm_struct *dm, char input[][MAX_ARGV],
+		      u32 input_num, u8 flag, char *output, u32 out_len)
+{
+#ifdef CONFIG_PHYDM_DEBUG_FUNCTION
+	u32 used = 0;
+	u8 id = 0;
+	u32 var1[10] = {0};
+	u32 i;
+	u32 phydm_ary_size = sizeof(phy_dm_ary) / sizeof(struct phydm_command);
+
+	if (flag == 0) {
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "GET, nothing to print\n");
+		return;
+	}
+
+	PDM_SNPF(out_len, used, output + used, out_len - used, "\n");
+
+	/* Parsing Cmd ID */
+	if (input_num) {
+		for (i = 0; i < phydm_ary_size; i++) {
+			if (strcmp(phy_dm_ary[i].name, input[0]) == 0) {
+				id = phy_dm_ary[i].id;
+				break;
+			}
+		}
+		if (i == phydm_ary_size) {
+			PDM_SNPF(out_len, used, output + used, out_len - used,
+				 "PHYDM command not found!\n");
+			return;
+		}
+	}
+
+	switch (id) {
+	case PHYDM_HELP: {
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "BB cmd ==>\n");
+
+		for (i = 0; i < phydm_ary_size - 2; i++)
+			PDM_SNPF(out_len, used, output + used, out_len - used,
+				 "  %-5d: %s\n", i, phy_dm_ary[i + 2].name);
+	} break;
+
+	case PHYDM_DEMO: { /*@echo demo 10 0x3a z abcde >cmd*/
+		u32 directory = 0;
+
+		#if (DM_ODM_SUPPORT_TYPE & (ODM_CE | ODM_AP))
+		char char_temp;
+		#else
+		u32 char_temp = ' ';
+		#endif
+
+		PHYDM_SSCANF(input[1], DCMD_DECIMAL, &directory);
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "Decimal value = %d\n", directory);
+		PHYDM_SSCANF(input[2], DCMD_HEX, &directory);
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "Hex value = 0x%x\n", directory);
+		PHYDM_SSCANF(input[3], DCMD_CHAR, &char_temp);
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "Char = %c\n", char_temp);
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "String = %s\n", input[4]);
+	} break;
+	case PHYDM_RF_CMD:
+		halrf_cmd_parser(dm, input, &used, output, &out_len, input_num);
+		break;
+
+	case PHYDM_DIG:
+		phydm_dig_debug(dm, input, &used, output, &out_len);
+		break;
+
+	case PHYDM_RA:
+		phydm_ra_debug(dm, input, &used, output, &out_len);
+		break;
+
+	case PHYDM_ANTDIV:
+		#if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY))
+		phydm_antdiv_debug(dm, input, &used, output, &out_len);
+		#endif
+		break;
+
+	case PHYDM_PATHDIV:
+		#if (defined(CONFIG_PATH_DIVERSITY))
+		phydm_pathdiv_debug(dm, input, &used, output, &out_len);
+		#endif
+		break;
+
+	case PHYDM_DEBUG:
+		phydm_debug_trace(dm, input, &used, output, &out_len);
+		break;
+
+	case PHYDM_FW_DEBUG:
+		phydm_fw_debug_trace(dm, input, &used, output, &out_len);
+		break;
+
+	case PHYDM_SUPPORT_ABILITY:
+		phydm_supportability_en(dm, input, &used, output, &out_len);
+		break;
+
+	case PHYDM_SMART_ANT:
+		#if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY))
+
+		#ifdef CONFIG_HL_SMART_ANTENNA_TYPE2
+		phydm_hl_smt_ant_dbg_type2(dm, input, &used, output, &out_len);
+		#elif (defined(CONFIG_HL_SMART_ANTENNA_TYPE1))
+		phydm_hl_smart_ant_debug(dm, input, &used, output, &out_len);
+		#endif
+
+		#elif (defined(CONFIG_CUMITEK_SMART_ANTENNA))
+		phydm_cumitek_smt_ant_debug(dm, input, &used, output, &out_len);
+		#endif
+
+		break;
+
+	case PHYDM_API:
+		phydm_api_adjust(dm, input, &used, output, &out_len);
+		break;
+
+	case PHYDM_PROFILE:
+		phydm_basic_profile(dm, &used, output, &out_len);
+		break;
+
+	case PHYDM_GET_TXAGC:
+		phydm_get_txagc(dm, &used, output, &out_len);
+		break;
+
+	case PHYDM_SET_TXAGC:
+		phydm_set_txagc_dbg(dm, input, &used, output, &out_len);
+		break;
+
+	case PHYDM_TRX_PATH:
+		phydm_config_trx_path(dm, input, &used, output, &out_len);
+		break;
+
+	case PHYDM_LA_MODE:
+		#if (PHYDM_LA_MODE_SUPPORT)
+		phydm_lamode_trigger_cmd(dm, input, &used, output, &out_len);
+		#endif
+		break;
+
+	case PHYDM_DUMP_REG:
+		phydm_dump_reg(dm, input, &used, output, &out_len);
+		break;
+
+	case PHYDM_BIG_JUMP:
+		phydm_enable_big_jump(dm, input, &used, output, &out_len);
+		break;
+
+	case PHYDM_AUTO_DBG:
+		#ifdef PHYDM_AUTO_DEGBUG
+		phydm_auto_dbg_console(dm, input, &used, output, &out_len);
+		#endif
+		break;
+
+	case PHYDM_SHOW_RXRATE:
+		phydm_show_rx_rate(dm, input, &used, output, &out_len);
+		break;
+
+	case PHYDM_NBI_EN:
+		phydm_nbi_debug(dm, input, &used, output, &out_len);
+		break;
+
+	case PHYDM_CSI_MASK_EN:
+		phydm_csi_debug(dm, input, &used, output, &out_len);
+		break;
+
+	case PHYDM_DFS_DEBUG: {
+		#ifdef CONFIG_PHYDM_DFS_MASTER
+		phydm_dfs_debug(dm, input, &used, output, &out_len);
+		#endif
+		break;
+	}
+
+	case PHYDM_NHM:
+		#ifdef NHM_SUPPORT
+		phydm_nhm_dbg(dm, input, &used, output, &out_len);
+		#endif
+		break;
+
+	case PHYDM_CLM:
+		#ifdef CLM_SUPPORT
+		phydm_clm_dbg(dm, input, &used, output, &out_len);
+		#endif
+		break;
+
+	#ifdef FAHM_SUPPORT
+	case PHYDM_FAHM:
+		phydm_fahm_dbg(dm, input, &used, output, &out_len);
+		break;
+	#endif
+
+	case PHYDM_ENV_MNTR:
+		phydm_env_mntr_dbg(dm, input, &used, output, &out_len);
+		break;
+
+	case PHYDM_BB_INFO:
+		phydm_bb_hw_dbg_info(dm, input, &used, output, &out_len);
+		break;
+
+	case PHYDM_TXBF: {
+	#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
+	#if (BEAMFORMING_SUPPORT)
+		struct _RT_BEAMFORMING_INFO *beamforming_info = NULL;
+
+		beamforming_info = &dm->beamforming_info;
+
+		PHYDM_SSCANF(input[1], DCMD_DECIMAL, &var1[0]);
+		if (var1[0] == 0) {
+			beamforming_info->apply_v_matrix = false;
+			beamforming_info->snding3ss = true;
+			PDM_SNPF(out_len, used, output + used, out_len - used,
+				 "\r\n dont apply V matrix and 3SS 789 snding\n");
+		} else if (var1[0] == 1) {
+			beamforming_info->apply_v_matrix = true;
+			beamforming_info->snding3ss = true;
+			PDM_SNPF(out_len, used, output + used, out_len - used,
+				 "\r\n apply V matrix and 3SS 789 snding\n");
+		} else if (var1[0] == 2) {
+			beamforming_info->apply_v_matrix = true;
+			beamforming_info->snding3ss = false;
+			PDM_SNPF(out_len, used, output + used, out_len - used,
+				 "\r\n default txbf setting\n");
+		} else
+			PDM_SNPF(out_len, used, output + used, out_len - used,
+				 "\r\n unknown cmd!!\n");
+	#endif
+	#endif
+	} break;
+
+	case PHYDM_H2C:
+		phydm_h2C_debug(dm, input, &used, output, &out_len);
+		break;
+
+	case PHYDM_EXT_RF_E_CTRL:
+		phydm_ext_rf_element_ctrl(dm, input, &used, output, &out_len);
+		break;
+
+	case PHYDM_ADAPTIVE_SOML:
+		#ifdef CONFIG_ADAPTIVE_SOML
+		phydm_soml_debug(dm, input, &used, output, &out_len);
+		#endif
+		break;
+
+	case PHYDM_PSD:
+
+		#ifdef CONFIG_PSD_TOOL
+		phydm_psd_debug(dm, input, &used, output, &out_len);
+		#endif
+
+		break;
+
+	case PHYDM_DEBUG_PORT:
+		phydm_print_dbgport(dm, input, &used, output, &out_len);
+		break;
+
+	case PHYDM_DIS_HTSTF_CONTROL: {
+		if (input[1])
+			PHYDM_SSCANF(input[1], DCMD_DECIMAL, &var1[0]);
+
+		if (var1[0] == 1) {
+			/* setting being false is for debug */
+			dm->bhtstfdisabled = true;
+			PDM_SNPF(out_len, used, output + used, out_len - used,
+				 "Dynamic HT-STF Gain Control is Disable\n");
+		} else {
+			/* @default setting should be true,
+			 * always be dynamic control
+			 */
+			dm->bhtstfdisabled = false;
+			PDM_SNPF(out_len, used, output + used, out_len - used,
+				 "Dynamic HT-STF Gain Control is Enable\n");
+		}
+	} break;
+
+	case PHYDM_TUNE_PARAMETER:
+		phydm_parameter_adjust(dm, input, &used, output, &out_len);
+		break;
+
+	case PHYDM_ADAPTIVITY_DEBUG:
+		#ifdef PHYDM_SUPPORT_ADAPTIVITY
+		phydm_adaptivity_debug(dm, input, &used, output, &out_len);
+		#endif
+		break;
+
+	case PHYDM_DIS_DYM_ANT_WEIGHTING:
+		#ifdef DYN_ANT_WEIGHTING_SUPPORT
+		phydm_ant_weight_dbg(dm, input, &used, output, &out_len);
+		#endif
+		break;
+
+	case PHYDM_FORECE_PT_STATE: {
+		#ifdef PHYDM_POWER_TRAINING_SUPPORT
+		phydm_pow_train_debug(dm, input, &used, output, &out_len);
+		#endif
+		break;
+	}
+
+	case PHYDM_DIS_RXHP_CTR: {
+		if (input[1])
+			PHYDM_SSCANF(input[1], DCMD_DECIMAL, &var1[0]);
+
+		if (var1[0] == 1) {
+			/* the setting being on is at debug mode to disconnect
+			 * RxHP seeting with SoML on/odd
+			 */
+			dm->disrxhpsoml = true;
+			PDM_SNPF(out_len, used, output + used, out_len - used,
+				 "Dynamic RxHP Control with SoML on/off is Disable\n");
+		} else if (var1[0] == 0) {
+			/* @default setting,
+			 * RxHP setting will follow SoML on/off setting
+			 */
+			dm->disrxhpsoml = false;
+			PDM_SNPF(out_len, used, output + used, out_len - used,
+				 "Dynamic RxHP Control with SoML on/off is Enable\n");
+		} else {
+			dm->disrxhpsoml = false;
+			PDM_SNPF(out_len, used, output + used, out_len - used,
+				 "Default Setting, Dynamic RxHP Control with SoML on/off is Enable\n");
+		}
+	} break;
+
+	case PHYDM_STA_INFO:
+		phydm_show_sta_info(dm, input, &used, output, &out_len);
+		break;
+
+	case PHYDM_PAUSE_FUNC:
+		phydm_pause_func_console(dm, input, &used, output, &out_len);
+		break;
+
+	case PHYDM_PER_TONE_EVM:
+		phydm_per_tone_evm(dm, input, &used, output, &out_len);
+		break;
+
+	#ifdef CONFIG_DYNAMIC_TX_TWR
+	case PHYDM_DYN_TXPWR:
+		phydm_dtp_debug(dm, input, &used, output, &out_len);
+		break;
+	#endif
+
+	case PHYDM_LNA_SAT:
+		#ifdef PHYDM_LNA_SAT_CHK_SUPPORT
+		phydm_lna_sat_debug(dm, input, &used, output, &out_len);
+		#endif
+		break;
+
+	default:
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "Do not support this command\n");
+		break;
+	}
+#endif /*@#ifdef CONFIG_PHYDM_DEBUG_FUNCTION*/
+}
+
+#if defined __ECOS || defined __ICCARM__
+char *strsep(char **s, const char *ct)
+{
+	char *sbegin = *s;
+	char *end;
+
+	if (!sbegin)
+		return NULL;
+
+	end = strpbrk(sbegin, ct);
+	if (end)
+		*end++ = '\0';
+	*s = end;
+	return sbegin;
+}
+#endif
+
+#if (DM_ODM_SUPPORT_TYPE & (ODM_CE | ODM_AP | ODM_IOT))
+s32 phydm_cmd(struct dm_struct *dm, char *input, u32 in_len, u8 flag,
+	      char *output, u32 out_len)
+{
+	char *token;
+	u32 argc = 0;
+	char argv[MAX_ARGC][MAX_ARGV];
+
+	do {
+		token = strsep(&input, ", ");
+		if (token) {
+			strcpy(argv[argc], token);
+			argc++;
+		} else {
+			break;
+		}
+	} while (argc < MAX_ARGC);
+
+	if (argc == 1)
+		argv[0][strlen(argv[0]) - 1] = '\0';
+
+	phydm_cmd_parser(dm, argv, argc, flag, output, out_len);
+
+	return 0;
+}
+#endif
+
+void phydm_fw_trace_handler(void *dm_void, u8 *cmd_buf, u8 cmd_len)
+{
+#ifdef CONFIG_PHYDM_DEBUG_FUNCTION
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+
+	/*@u8	debug_trace_11byte[60];*/
+	u8 freg_num, c2h_seq, buf_0 = 0;
+
+	if (!(dm->support_ic_type & PHYDM_IC_3081_SERIES))
+		return;
+
+	if (cmd_len > 12 || cmd_len == 0) {
+		pr_debug("[Warning] Error C2H cmd_len=%d\n", cmd_len);
+		return;
+	}
+
+	buf_0 = cmd_buf[0];
+	freg_num = (buf_0 & 0xf);
+	c2h_seq = (buf_0 & 0xf0) >> 4;
+
+	#if 0
+	PHYDM_DBG(dm, DBG_FW_TRACE,
+		  "[FW debug message] freg_num = (( %d )), c2h_seq=(( %d ))\n",
+		  freg_num, c2h_seq);
+
+	strncpy(debug_trace_11byte, &cmd_buf[1], (cmd_len - 1));
+	debug_trace_11byte[cmd_len - 1] = '\0';
+	PHYDM_DBG(dm, DBG_FW_TRACE, "[FW debug message] %s\n",
+		  debug_trace_11byte);
+	PHYDM_DBG(dm, DBG_FW_TRACE, "[FW debug message] cmd_len = (( %d ))\n",
+		  cmd_len);
+	PHYDM_DBG(dm, DBG_FW_TRACE, "[FW debug message] c2h_cmd_start=((%d))\n",
+		  dm->c2h_cmd_start);
+
+	PHYDM_DBG(dm, DBG_FW_TRACE, "pre_seq = (( %d )), current_seq=((%d))\n",
+		  dm->pre_c2h_seq, c2h_seq);
+	PHYDM_DBG(dm, DBG_FW_TRACE, "fw_buff_is_enpty = (( %d ))\n",
+		  dm->fw_buff_is_enpty);
+	#endif
+
+	if (c2h_seq != dm->pre_c2h_seq && dm->fw_buff_is_enpty == false) {
+		dm->fw_debug_trace[dm->c2h_cmd_start] = '\0';
+		PHYDM_DBG(dm, DBG_FW_TRACE, "[FW Dbg Queue Overflow] %s\n",
+			  dm->fw_debug_trace);
+		dm->c2h_cmd_start = 0;
+	}
+
+	if ((cmd_len - 1) > (60 - dm->c2h_cmd_start)) {
+		dm->fw_debug_trace[dm->c2h_cmd_start] = '\0';
+		PHYDM_DBG(dm, DBG_FW_TRACE,
+			  "[FW Dbg Queue error: wrong C2H length] %s\n",
+			  dm->fw_debug_trace);
+		dm->c2h_cmd_start = 0;
+		return;
+	}
+
+	strncpy((char *)&dm->fw_debug_trace[dm->c2h_cmd_start],
+		(char *)&cmd_buf[1], (cmd_len - 1));
+	dm->c2h_cmd_start += (cmd_len - 1);
+	dm->fw_buff_is_enpty = false;
+
+	if (freg_num == 0 || dm->c2h_cmd_start >= 60) {
+		if (dm->c2h_cmd_start < 60)
+			dm->fw_debug_trace[dm->c2h_cmd_start] = '\0';
+		else
+			dm->fw_debug_trace[59] = '\0';
+
+		PHYDM_DBG(dm, DBG_FW_TRACE, "[FW DBG Msg] %s\n",
+			  dm->fw_debug_trace);
+#if 0
+		/*@dbg_print("[FW DBG Msg] %s\n", dm->fw_debug_trace);*/
+#endif
+		dm->c2h_cmd_start = 0;
+		dm->fw_buff_is_enpty = true;
+	}
+
+	dm->pre_c2h_seq = c2h_seq;
+#endif /*@#ifdef CONFIG_PHYDM_DEBUG_FUNCTION*/
+}
+
+void phydm_fw_trace_handler_code(void *dm_void, u8 *buffer, u8 cmd_len)
+{
+#ifdef CONFIG_PHYDM_DEBUG_FUNCTION
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	u8 function = buffer[0];
+	u8 dbg_num = buffer[1];
+	u16 content_0 = (((u16)buffer[3]) << 8) | ((u16)buffer[2]);
+	u16 content_1 = (((u16)buffer[5]) << 8) | ((u16)buffer[4]);
+	u16 content_2 = (((u16)buffer[7]) << 8) | ((u16)buffer[6]);
+	u16 content_3 = (((u16)buffer[9]) << 8) | ((u16)buffer[8]);
+	u16 content_4 = (((u16)buffer[11]) << 8) | ((u16)buffer[10]);
+
+	if (cmd_len > 12)
+		PHYDM_DBG(dm, DBG_FW_TRACE,
+			  "[FW Msg] Invalid cmd length (( %d )) >12\n",
+			  cmd_len);
+/*@--------------------------------------------*/
+#ifdef CONFIG_RA_FW_DBG_CODE
+	if (function == RATE_DECISION) {
+		if (dbg_num == 0) {
+			if (content_0 == 1)
+				PHYDM_DBG(dm, DBG_FW_TRACE,
+					  "[FW] RA_CNT=((%d))  Max_device=((%d))--------------------------->\n",
+					  content_1, content_2);
+			else if (content_0 == 2)
+				PHYDM_DBG(dm, DBG_FW_TRACE,
+					  "[FW] Check RA macid= ((%d)), MediaStatus=((%d)), Dis_RA=((%d)),  try_bit=((0x%x))\n",
+					  content_1, content_2, content_3,
+					  content_4);
+			else if (content_0 == 3)
+				PHYDM_DBG(dm, DBG_FW_TRACE,
+					  "[FW] Check RA  total=((%d)),  drop=((0x%x)), TXRPT_TRY_bit=((%x)), bNoisy=((%x))\n",
+					  content_1, content_2, content_3,
+					  content_4);
+		} else if (dbg_num == 1) {
+			if (content_0 == 1)
+				PHYDM_DBG(dm, DBG_FW_TRACE,
+					  "[FW] RTY[0,1,2,3]=[ %d , %d , %d , %d ]\n",
+					  content_1, content_2, content_3,
+					  content_4);
+			else if (content_0 == 2) {
+				PHYDM_DBG(dm, DBG_FW_TRACE,
+					  "[FW] RTY[4]=[ %d ], drop=(( %d )), total=(( %d )), current_rate=((0x %x ))",
+					  content_1, content_2, content_3,
+					  content_4);
+				phydm_print_rate(dm, (u8)content_4,
+						 DBG_FW_TRACE);
+			} else if (content_0 == 3)
+				PHYDM_DBG(dm, DBG_FW_TRACE,
+					  "[FW] penality_idx=(( %d ))\n",
+					  content_1);
+			else if (content_0 == 4)
+				PHYDM_DBG(dm, DBG_FW_TRACE,
+					  "[FW] RSSI=(( %d )), ra_stage = (( %d ))\n",
+					  content_1, content_2);
+		} else if (dbg_num == 3) {
+			if (content_0 == 1)
+				PHYDM_DBG(dm, DBG_FW_TRACE,
+					  "[FW] Fast_RA (( DOWN ))  total=((%d)),  total>>1=((%d)), R4+R3+R2 = ((%d)), RateDownHold = ((%d))\n",
+					  content_1, content_2, content_3,
+					  content_4);
+			else if (content_0 == 2)
+				PHYDM_DBG(dm, DBG_FW_TRACE,
+					  "[FW] Fast_RA (( UP ))  total_acc=((%d)),  total_acc>>1=((%d)), R4+R3+R2 = ((%d)), RateDownHold = ((%d))\n",
+					  content_1, content_2, content_3,
+					  content_4);
+			else if (content_0 == 3)
+				PHYDM_DBG(dm, DBG_FW_TRACE,
+					  "[FW] Fast_RA (( UP )) ((rate Down Hold))  RA_CNT=((%d))\n",
+					  content_1);
+			else if (content_0 == 4)
+				PHYDM_DBG(dm, DBG_FW_TRACE,
+					  "[FW] Fast_RA (( UP )) ((tota_accl<5 skip))  RA_CNT=((%d))\n",
+					  content_1);
+			else if (content_0 == 8)
+				PHYDM_DBG(dm, DBG_FW_TRACE,
+					  "[FW] Fast_RA (( Reset Tx Rpt )) RA_CNT=((%d))\n",
+					  content_1);
+		} else if (dbg_num == 4) {
+			if (content_0 == 3)
+				PHYDM_DBG(dm, DBG_FW_TRACE,
+					  "[FW] RER_CNT   PCR_ori =(( %d )),  ratio_ori =(( %d )), pcr_updown_bitmap =(( 0x%x )), pcr_var_diff =(( %d ))\n",
+					  content_1, content_2, content_3,
+					  content_4);
+			else if (content_0 == 4)
+				PHYDM_DBG(dm, DBG_FW_TRACE,
+					  "[FW] pcr_shift_value =(( %s%d )), rate_down_threshold =(( %d )), rate_up_threshold =(( %d ))\n",
+					  ((content_1) ? "+" : "-"), content_2,
+					  content_3, content_4);
+			else if (content_0 == 5)
+				PHYDM_DBG(dm, DBG_FW_TRACE,
+					  "[FW] pcr_mean =(( %d )), PCR_VAR =(( %d )), offset =(( %d )), decision_offset_p =(( %d ))\n",
+					  content_1, content_2, content_3,
+					  content_4);
+		} else if (dbg_num == 5) {
+			if (content_0 == 1)
+				PHYDM_DBG(dm, DBG_FW_TRACE,
+					  "[FW] (( UP))  Nsc=(( %d )), N_High=(( %d )), RateUp_Waiting=(( %d )), RateUp_Fail=(( %d ))\n",
+					  content_1, content_2, content_3,
+					  content_4);
+			else if (content_0 == 2)
+				PHYDM_DBG(dm, DBG_FW_TRACE,
+					  "[FW] ((DOWN))  Nsc=(( %d )), N_Low=(( %d ))\n",
+					  content_1, content_2);
+			else if (content_0 == 3)
+				PHYDM_DBG(dm, DBG_FW_TRACE,
+					  "[FW] ((HOLD))  Nsc=((%d)), N_High=((%d)), N_Low=((%d)), Reset_CNT=((%d))\n",
+					  content_1, content_2, content_3,
+					  content_4);
+		} else if (dbg_num == 0x60) {
+			if (content_0 == 1)
+				PHYDM_DBG(dm, DBG_FW_TRACE,
+					  "[FW] ((AP RPT))  macid=((%d)), BUPDATE[macid]=((%d))\n",
+					  content_1, content_2);
+			else if (content_0 == 4)
+				PHYDM_DBG(dm, DBG_FW_TRACE,
+					  "[FW] ((AP RPT))  pass=((%d)), rty_num=((%d)), drop=((%d)), total=((%d))\n",
+					  content_1, content_2, content_3,
+					  content_4);
+			else if (content_0 == 5)
+				PHYDM_DBG(dm, DBG_FW_TRACE,
+					  "[FW] ((AP RPT))  PASS=((%d)), RTY_NUM=((%d)), DROP=((%d)), TOTAL=((%d))\n",
+					  content_1, content_2, content_3,
+					  content_4);
+		}
+	} else if (function == INIT_RA_TABLE) {
+		if (dbg_num == 3)
+			PHYDM_DBG(dm, DBG_FW_TRACE,
+				  "[FW][INIT_RA_INFO] Ra_init, RA_SKIP_CNT = (( %d ))\n",
+				  content_0);
+	} else if (function == RATE_UP) {
+		if (dbg_num == 2) {
+			if (content_0 == 1)
+				PHYDM_DBG(dm, DBG_FW_TRACE,
+					  "[FW][RateUp]  ((Highest rate->return)), macid=((%d))  Nsc=((%d))\n",
+					  content_1, content_2);
+		} else if (dbg_num == 5) {
+			if (content_0 == 0)
+				PHYDM_DBG(dm, DBG_FW_TRACE,
+					  "[FW][RateUp]  ((rate UP)), up_rate_tmp=((0x%x)), rate_idx=((0x%x)), SGI_en=((%d)),  SGI=((%d))\n",
+					  content_1, content_2, content_3,
+					  content_4);
+			else if (content_0 == 1)
+				PHYDM_DBG(dm, DBG_FW_TRACE,
+					  "[FW][RateUp]  ((rate UP)), rate_1=((0x%x)), rate_2=((0x%x)), BW=((%d)), Try_Bit=((%d))\n",
+					  content_1, content_2, content_3,
+					  content_4);
+		}
+	} else if (function == RATE_DOWN) {
+		if (dbg_num == 5) {
+			if (content_0 == 1)
+				PHYDM_DBG(dm, DBG_FW_TRACE,
+					  "[FW][RateDownStep]  ((rate Down)), macid=((%d)), rate1=((0x%x)),  rate2=((0x%x)), BW=((%d))\n",
+					  content_1, content_2, content_3,
+					  content_4);
+		}
+	} else if (function == TRY_DONE) {
+		if (dbg_num == 1) {
+			if (content_0 == 1)
+				PHYDM_DBG(dm, DBG_FW_TRACE,
+					  "[FW][Try Done]  ((try succsess )) macid=((%d)), Try_Done_cnt=((%d))\n",
+					  content_1, content_2);
+		} else if (dbg_num == 2) {
+			if (content_0 == 1)
+				PHYDM_DBG(dm, DBG_FW_TRACE,
+					  "[FW][Try Done]  ((try)) macid=((%d)), Try_Done_cnt=((%d)),  rate_2=((%d)),  try_succes=((%d))\n",
+					  content_1, content_2, content_3,
+					  content_4);
+		}
+	} else if (function == RA_H2C) {
+		if (dbg_num == 1) {
+			if (content_0 == 0)
+				PHYDM_DBG(dm, DBG_FW_TRACE,
+					  "[FW][H2C=0x49]  fw_trace_en=((%d)), mode =((%d)),  macid=((%d))\n",
+					  content_1, content_2, content_3);
+		}
+	} else if (function == F_RATE_AP_RPT) {
+		if (dbg_num == 1) {
+			if (content_0 == 1)
+				PHYDM_DBG(dm, DBG_FW_TRACE,
+					  "[FW][AP RPT]  ((1)), SPE_STATIS=((0x%x))---------->\n",
+					  content_3);
+		} else if (dbg_num == 2) {
+			if (content_0 == 1)
+				PHYDM_DBG(dm, DBG_FW_TRACE,
+					  "[FW][AP RPT]  RTY_all=((%d))\n",
+					  content_1);
+		} else if (dbg_num == 3) {
+			if (content_0 == 1)
+				PHYDM_DBG(dm, DBG_FW_TRACE,
+					  "[FW][AP RPT]  MACID1[%d], TOTAL=((%d)),  RTY=((%d))\n",
+					  content_3, content_1, content_2);
+		} else if (dbg_num == 4) {
+			if (content_0 == 1)
+				PHYDM_DBG(dm, DBG_FW_TRACE,
+					  "[FW][AP RPT]  MACID2[%d], TOTAL=((%d)),  RTY=((%d))\n",
+					  content_3, content_1, content_2);
+		} else if (dbg_num == 5) {
+			if (content_0 == 1)
+				PHYDM_DBG(dm, DBG_FW_TRACE,
+					  "[FW][AP RPT]  MACID1[%d], PASS=((%d)),  DROP=((%d))\n",
+					  content_3, content_1, content_2);
+		} else if (dbg_num == 6) {
+			if (content_0 == 1)
+				PHYDM_DBG(dm, DBG_FW_TRACE,
+					  "[FW][AP RPT]  MACID2[%d],, PASS=((%d)),  DROP=((%d))\n",
+					  content_3, content_1, content_2);
+		}
+	} else if (function == DBC_FW_CLM) {
+		PHYDM_DBG(dm, DBG_FW_TRACE,
+			  "[FW][CLM][%d, %d] = {%d, %d, %d, %d}\n", dbg_num,
+			  content_0, content_1, content_2, content_3,
+			  content_4);
+	} else {
+		PHYDM_DBG(dm, DBG_FW_TRACE,
+			  "[FW][general][%d, %d, %d] = {%d, %d, %d, %d}\n",
+			  function, dbg_num, content_0, content_1, content_2,
+			  content_3, content_4);
+	}
+#else
+	PHYDM_DBG(dm, DBG_FW_TRACE,
+		  "[FW][general][%d, %d, %d] = {%d, %d, %d, %d}\n", function,
+		  dbg_num, content_0, content_1, content_2, content_3,
+		  content_4);
+#endif
+/*@--------------------------------------------*/
+
+#endif /*@#ifdef CONFIG_PHYDM_DEBUG_FUNCTION*/
+}
+
+void phydm_fw_trace_handler_8051(void *dm_void, u8 *buffer, u8 cmd_len)
+{
+#ifdef CONFIG_PHYDM_DEBUG_FUNCTION
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+#if 0
+	if (cmd_len >= 3)
+		cmd_buf[cmd_len - 1] = '\0';
+	PHYDM_DBG(dm, DBG_FW_TRACE, "[FW DBG Msg] %s\n", &cmd_buf[3]);
+#else
+
+	int i = 0;
+	u8 extend_c2h_sub_id = 0, extend_c2h_dbg_len = 0;
+	u8 extend_c2h_dbg_seq = 0;
+	u8 fw_debug_trace[128];
+	u8 *extend_c2h_dbg_content = 0;
+
+	if (cmd_len > 127)
+		return;
+
+	extend_c2h_sub_id = buffer[0];
+	extend_c2h_dbg_len = buffer[1];
+	extend_c2h_dbg_content = buffer + 2; /*@DbgSeq+DbgContent for show HEX*/
+
+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
+	RT_DISP(FC2H, C2H_Summary, ("[Extend C2H packet], Extend_c2hSubId=0x%x, extend_c2h_dbg_len=%d\n",
+				    extend_c2h_sub_id, extend_c2h_dbg_len));
+
+	RT_DISP_DATA(FC2H, C2H_Summary, "[Extend C2H packet], Content Hex:", extend_c2h_dbg_content, cmd_len - 2);
+#endif
+
+go_backfor_aggre_dbg_pkt:
+	i = 0;
+	extend_c2h_dbg_seq = buffer[2];
+	extend_c2h_dbg_content = buffer + 3;
+
+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
+	RT_DISP(FC2H, C2H_Summary, ("[RTKFW, SEQ= %d] :", extend_c2h_dbg_seq));
+#endif
+
+	for (;; i++) {
+		fw_debug_trace[i] = extend_c2h_dbg_content[i];
+		if (extend_c2h_dbg_content[i + 1] == '\0') {
+			fw_debug_trace[i + 1] = '\0';
+			PHYDM_DBG(dm, DBG_FW_TRACE, "[FW DBG Msg] %s",
+				  &fw_debug_trace[0]);
+			break;
+		} else if (extend_c2h_dbg_content[i] == '\n') {
+			fw_debug_trace[i + 1] = '\0';
+			PHYDM_DBG(dm, DBG_FW_TRACE, "[FW DBG Msg] %s",
+				  &fw_debug_trace[0]);
+			buffer = extend_c2h_dbg_content + i + 3;
+			goto go_backfor_aggre_dbg_pkt;
+		}
+	}
+
+#endif
+#endif /*@#ifdef CONFIG_PHYDM_DEBUG_FUNCTION*/
+}
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/phydm_debug.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/phydm_debug.h
--- linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/phydm_debug.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/phydm_debug.h	2020-04-10 16:35:06.824660441 +0300
@@ -0,0 +1,444 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017  Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * The full GNU General Public License is included in this distribution in the
+ * file called LICENSE.
+ *
+ * Contact Information:
+ * wlanfae <wlanfae@realtek.com>
+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
+ * Hsinchu 300, Taiwan.
+ *
+ * Larry Finger <Larry.Finger@lwfinger.net>
+ *
+ *****************************************************************************/
+
+#ifndef __ODM_DBG_H__
+#define __ODM_DBG_H__
+
+/*@#define DEBUG_VERSION	"1.1"*/ /*@2015.07.29 YuChen*/
+/*@#define DEBUG_VERSION	"1.2"*/ /*@2015.08.28 Dino*/
+/*@#define DEBUG_VERSION	"1.3"*/ /*@2016.04.28 YuChen*/
+/*@#define DEBUG_VERSION	"1.4"*/ /*@2017.03.13 Dino*/
+#define DEBUG_VERSION "2.0" /*@2018.01.10 Dino*/
+
+/*@
+ * ============================================================
+ *  Definition
+ * ============================================================
+ */
+
+/*@FW DBG MSG*/
+#define	RATE_DECISION		1
+#define	INIT_RA_TABLE		2
+#define	RATE_UP			4
+#define	RATE_DOWN		8
+#define	TRY_DONE		16
+#define	RA_H2C			32
+#define	F_RATE_AP_RPT		64
+#define	DBC_FW_CLM		9
+
+#define PHYDM_SNPRINT_SIZE	64
+/* @----------------------------------------------------------------------------
+ * Define the tracing components
+ *
+ * -----------------------------------------------------------------------------
+ * BB FW Functions
+ */
+#define	PHYDM_FW_COMP_RA	BIT(0)
+#define	PHYDM_FW_COMP_MU	BIT(1)
+#define	PHYDM_FW_COMP_PATH_DIV	BIT(2)
+#define	PHYDM_FW_COMP_PT	BIT(3)
+
+/*@------------------------Export Marco Definition---------------------------*/
+
+#define config_phydm_read_txagc_check(data) (data != INVALID_TXAGC_DATA)
+
+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
+	#if (DBG_CMD_SUPPORT == 1)
+		extern	VOID DCMD_Printf(const char *pMsg);
+	#else
+		#define DCMD_Printf(_pMsg)
+	#endif
+
+	#define	pr_debug		DbgPrint
+	#define	dcmd_printf		DCMD_Printf
+	#define	dcmd_scanf		DCMD_Scanf
+	#define	RT_PRINTK		pr_debug
+	#define	PRINT_MAX_SIZE		512
+	#define PHYDM_SNPRINTF		RT_SPRINTF
+#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) && defined(DM_ODM_CE_MAC80211)
+	#define PHYDM_SNPRINTF		snprintf
+#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
+	#undef	pr_debug
+	#define pr_debug		printk
+	#define RT_PRINTK(fmt, args...)	pr_debug(fmt, ## args)
+	#define	RT_DISP(dbgtype, dbgflag, printstr)
+	#define RT_TRACE(adapter, comp, drv_level, fmt, args...)	\
+		RTW_INFO(fmt, ## args)
+	#define PHYDM_SNPRINTF		snprintf
+#elif (DM_ODM_SUPPORT_TYPE == ODM_IOT)
+	#define pr_debug(fmt, args...)		RTW_PRINT_MSG(fmt, ## args)
+	#define RT_DEBUG(comp, drv_level, fmt, args...)	\
+		RTW_PRINT_MSG(fmt, ## args)
+	#define PHYDM_SNPRINTF		snprintf
+#else
+	#define pr_debug	panic_printk
+	/*@#define RT_PRINTK(fmt, args...)	pr_debug("%s(): " fmt, __FUNCTION__, ## args);*/
+	#define RT_PRINTK(fmt, args...)	pr_debug(fmt, ## args)
+	#define PHYDM_SNPRINTF		snprintf
+#endif
+
+#ifndef ASSERT
+	#define ASSERT(expr)
+#endif
+
+#if DBG
+#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
+#define PHYDM_DBG(dm, comp, fmt, args...)			\
+	do {							\
+		if ((comp) & dm->debug_components) {          \
+			pr_debug("[PHYDM] ");			\
+			RT_PRINTK(fmt, ## args);		\
+		}						\
+	} while (0)
+
+#define PHYDM_DBG_F(dm, comp, fmt, args...)			\
+	do {							\
+		if ((comp) & dm->debug_components) {		\
+			RT_PRINTK(fmt, ## args);		\
+		}						\
+	} while (0)
+
+#define PHYDM_PRINT_ADDR(dm, comp, title_str, addr)		\
+	do {							\
+		if ((comp) & dm->debug_components) {		\
+			int __i;				\
+			u8 *__ptr = (u8 *)addr;			\
+			pr_debug("[PHYDM] ");			\
+			pr_debug(title_str);			\
+			pr_debug(" ");				\
+			for (__i = 0; __i < 6; __i++)		\
+				pr_debug("%02X%s", __ptr[__i], (__i == 5) ? "" : "-");\
+			pr_debug("\n");				\
+		}						\
+	} while (0)
+#elif (DM_ODM_SUPPORT_TYPE == ODM_WIN)
+
+static __inline void PHYDM_DBG(PDM_ODM_T dm, int comp, char *fmt, ...)
+{
+	RT_STATUS rt_status;
+	va_list args;
+	char buf[PRINT_MAX_SIZE] = {0};
+
+	if ((comp & dm->debug_components) == 0)
+		return;
+
+	if (fmt == NULL)
+		return;
+
+	va_start(args, fmt);
+	rt_status = (RT_STATUS)RtlStringCbVPrintfA(buf, PRINT_MAX_SIZE, fmt, args);
+	va_end(args);
+
+	if (rt_status != RT_STATUS_SUCCESS) {
+		DbgPrint("Failed (%d) to print message to buffer\n", rt_status);
+		return;
+	}
+
+	DbgPrint("[PHYDM] %s", buf);
+}
+
+static __inline void PHYDM_DBG_F(PDM_ODM_T dm, int comp, char *fmt, ...)
+{
+	RT_STATUS rt_status;
+	va_list args;
+	char buf[PRINT_MAX_SIZE] = {0};
+
+	if ((comp & dm->debug_components) == 0)
+		return;
+
+	if (fmt == NULL)
+		return;
+
+	va_start(args, fmt);
+	rt_status = (RT_STATUS)RtlStringCbVPrintfA(buf, PRINT_MAX_SIZE, fmt, args);
+	va_end(args);
+
+	if (rt_status != RT_STATUS_SUCCESS) {
+		/*@DbgPrint("DM Print Fail\n");*/
+		return;
+	}
+
+	DbgPrint("%s", buf);
+}
+
+#define PHYDM_PRINT_ADDR(p_dm, comp, title_str, ptr)		\
+	do {							\
+		if ((comp) & p_dm->debug_components) {		\
+								\
+			int __i;				\
+			u8 *__ptr = (u8 *)ptr;			\
+			pr_debug("[PHYDM] ");			\
+			pr_debug(title_str);			\
+			pr_debug(" ");				\
+			for (__i = 0; __i < 6; __i++)		\
+				pr_debug("%02X%s", __ptr[__i], (__i == 5) ? "" : "-");	\
+			pr_debug("\n");				\
+		}	\
+	} while (0)
+#elif (DM_ODM_SUPPORT_TYPE == ODM_IOT)
+
+#define PHYDM_DBG(dm, comp, fmt, args...)			\
+	do {							\
+		if ((comp) & dm->debug_components) {		\
+			RT_DEBUG(COMP_PHYDM, \
+				 DBG_DMESG, "[PHYDM] " fmt, ##args);	\
+		}						\
+	} while (0)
+
+#define PHYDM_DBG_F(dm, comp, fmt, args...)			\
+	do {							\
+		if ((comp) & dm->debug_components) {		\
+			RT_DEBUG(COMP_PHYDM, \
+				 DBG_DMESG, fmt, ##args);	\
+		}	\
+	} while (0)
+
+#define PHYDM_PRINT_ADDR(dm, comp, title_str, addr)		\
+	do {							\
+		if ((comp) & dm->debug_components) {		\
+			RT_DEBUG(COMP_PHYDM, \
+				 DBG_DMESG, "[PHYDM] " title_str "%pM\n",	\
+				 addr);				\
+		}						\
+	} while (0)
+
+#elif defined(DM_ODM_CE_MAC80211_V2)
+
+#define PHYDM_DBG(dm, comp, fmt, args...)
+#define PHYDM_DBG_F(dm, comp, fmt, args...)
+#define PHYDM_PRINT_ADDR(dm, comp, title_str, addr)
+
+#else
+
+#define PHYDM_DBG(dm, comp, fmt, args...)			\
+	do {							\
+		struct dm_struct *__dm = (dm);			\
+		if ((comp) & __dm->debug_components) {		\
+			RT_TRACE(((struct rtl_priv *)__dm->adapter),\
+				 COMP_PHYDM, DBG_DMESG,		\
+				 "[PHYDM] " fmt, ##args);	\
+		}						\
+	} while (0)
+
+#define PHYDM_DBG_F(dm, comp, fmt, args...)			\
+	do {							\
+		struct dm_struct *__dm = (dm);			\
+		if ((comp) & __dm->debug_components) {		\
+			RT_TRACE(((struct rtl_priv *)__dm->adapter),\
+				 COMP_PHYDM, DBG_DMESG, fmt, ##args);	\
+		}	\
+	} while (0)
+
+#define PHYDM_PRINT_ADDR(dm, comp, title_str, addr)		\
+	do {							\
+		struct dm_struct *__dm = (dm);			\
+		if ((comp) & __dm->debug_components) {		\
+			RT_TRACE(((struct rtl_priv *)__dm->adapter),\
+				 COMP_PHYDM, DBG_DMESG,		\
+				 "[PHYDM] " title_str "%pM\n", addr);\
+		}						\
+	} while (0)
+#endif
+
+#else /*@#if DBG*/
+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
+static __inline void PHYDM_DBG(struct dm_struct *dm, int comp, char *fmt, ...)
+{
+}
+static __inline void PHYDM_DBG_F(struct dm_struct *dm, int comp, char *fmt, ...)
+{
+}
+#else
+#define PHYDM_DBG(dm, comp, fmt, args...)
+#define PHYDM_DBG_F(dm, comp, fmt, args...)
+#endif
+#define PHYDM_PRINT_ADDR(dm, comp, title_str, ptr)
+
+#endif
+
+#define	DBGPORT_PRI_3	3	/*@Debug function (the highest priority)*/
+#define	DBGPORT_PRI_2	2	/*@Check hang function & Strong function*/
+#define	DBGPORT_PRI_1	1	/*Watch dog function*/
+#define	DBGPORT_RELEASE	0	/*@Init value (the lowest priority)*/
+
+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
+#define	PHYDM_DBGPRINT		0
+#define	PHYDM_SSCANF(x, y, z)	dcmd_scanf(x, y, z)
+#define	PDM_VAST_SNPF		PDM_SNPF
+#if (PHYDM_DBGPRINT == 1)
+#define	PDM_SNPF(msg)	\
+	do {\
+		rsprintf msg;\
+		pr_debug("%s", output);\
+	} while (0)
+#else
+
+static __inline void PDM_SNPF(u32 out_len, u32 used, char *buff, int len,
+			      char *fmt, ...)
+{
+	RT_STATUS rt_status;
+	va_list args;
+	char buf[PRINT_MAX_SIZE] = {0};
+
+	if (fmt == NULL)
+		return;
+
+	va_start(args, fmt);
+	rt_status = (RT_STATUS)RtlStringCbVPrintfA(buf, PRINT_MAX_SIZE, fmt, args);
+	va_end(args);
+
+	if (rt_status != RT_STATUS_SUCCESS) {
+		/*@DbgPrint("DM Print Fail\n");*/
+		return;
+	}
+
+	DCMD_Printf(buf);
+}
+
+
+
+#endif	/*@#if (PHYDM_DBGPRINT == 1)*/
+#else	/*@(DM_ODM_SUPPORT_TYPE & (ODM_CE | ODM_AP))*/
+	#if (DM_ODM_SUPPORT_TYPE == ODM_CE) || defined(__OSK__)
+	#define	PHYDM_DBGPRINT	0
+	#else
+	#define	PHYDM_DBGPRINT	1
+	#endif
+#define	MAX_ARGC		20
+#define	MAX_ARGV		16
+#define	DCMD_DECIMAL		"%d"
+#define	DCMD_CHAR		"%c"
+#define	DCMD_HEX		"%x"
+
+#define	PHYDM_SSCANF(x, y, z)	sscanf(x, y, z)
+
+#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
+#define PDM_VAST_SNPF(out_len, used, buff, len, fmt, args...) RT_PRINTK(fmt, ## args)
+
+#elif (DM_ODM_SUPPORT_TYPE & ODM_IOT)
+#define	PDM_VAST_SNPF(out_len, used, buff, len, fmt, args...)	\
+	do {								\
+		RT_DEBUG(COMP_PHYDM, DBG_DMESG, fmt, ##args);		\
+	} while (0)
+#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) && defined(DM_ODM_CE_MAC80211_V2)
+#define	PDM_VAST_SNPF(out_len, used, buff, len, fmt, args...)
+#else
+#define	PDM_VAST_SNPF(out_len, used, buff, len, fmt, args...)	\
+		RT_TRACE(((struct rtl_priv *)dm->adapter), COMP_PHYDM, \
+			DBG_DMESG, fmt, ##args)
+#endif
+
+#if (PHYDM_DBGPRINT == 1)
+#define	PDM_SNPF(out_len, used, buff, len, fmt, args...)		\
+	do {								\
+		snprintf(buff, len, fmt, ##args);			\
+		pr_debug("%s", output);					\
+	} while (0)
+#else
+#define	PDM_SNPF(out_len, used, buff, len, fmt, args...)		\
+	do {								\
+		u32 *__pdm_snpf_u = &(used);				\
+		if (out_len > *__pdm_snpf_u)				\
+			*__pdm_snpf_u += snprintf(buff, len, fmt, ##args);\
+	} while (0)
+#endif
+#endif
+/* @1 ============================================================
+ * 1  enumeration
+ * 1 ============================================================
+ */
+
+enum auto_detection_state { /*@Fast antenna training*/
+	AD_LEGACY_MODE	= 0,
+	AD_HT_MODE	= 1,
+	AD_VHT_MODE	= 2
+};
+
+/*@
+ * ============================================================
+ * 1  structure
+ * ============================================================
+ */
+
+#ifdef CONFIG_PHYDM_DEBUG_FUNCTION
+u8 phydm_get_l_sig_rate(void *dm_void, u8 rate_idx_l_sig);
+#endif
+
+void phydm_init_debug_setting(struct dm_struct *dm);
+
+void phydm_bb_dbg_port_header_sel(void *dm_void, u32 header_idx);
+
+u8 phydm_set_bb_dbg_port(void *dm_void, u8 curr_dbg_priority, u32 debug_port);
+
+void phydm_release_bb_dbg_port(void *dm_void);
+
+u32 phydm_get_bb_dbg_port_val(void *dm_void);
+
+void phydm_reset_rx_rate_distribution(struct dm_struct *dm);
+
+void phydm_rx_rate_distribution(void *dm_void);
+
+void phydm_show_phy_hitogram(void *dm_void);
+
+void phydm_get_avg_phystatus_val(void *dm_void);
+
+void phydm_get_phy_statistic(void *dm_void);
+
+void phydm_dm_summary(void *dm_void, u8 macid);
+
+void phydm_basic_dbg_message(void *dm_void);
+
+void phydm_basic_profile(void *dm_void, u32 *_used, char *output,
+			 u32 *_out_len);
+#if (DM_ODM_SUPPORT_TYPE & (ODM_CE | ODM_AP))
+s32 phydm_cmd(struct dm_struct *dm, char *input, u32 in_len, u8 flag,
+	      char *output, u32 out_len);
+#endif
+void phydm_cmd_parser(struct dm_struct *dm, char input[][16], u32 input_num,
+		      u8 flag, char *output, u32 out_len);
+
+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
+void phydm_basic_dbg_msg_cli_win(void *dm_void, char *buf);
+
+void phydm_sbd_check(
+	struct dm_struct *dm);
+
+void phydm_sbd_callback(
+	struct phydm_timer_list *timer);
+
+void phydm_sbd_workitem_callback(
+	void *context);
+#endif
+
+void phydm_fw_trace_en_h2c(void *dm_void, boolean enable,
+			   u32 fw_debug_component, u32 monitor_mode, u32 macid);
+
+void phydm_fw_trace_handler(void *dm_void, u8 *cmd_buf, u8 cmd_len);
+
+void phydm_fw_trace_handler_code(void *dm_void, u8 *buffer, u8 cmd_len);
+
+void phydm_fw_trace_handler_8051(void *dm_void, u8 *cmd_buf, u8 cmd_len);
+
+#endif /* @__ODM_DBG_H__ */
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/phydm_dfs.c linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/phydm_dfs.c
--- linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/phydm_dfs.c	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/phydm_dfs.c	2020-04-10 16:35:06.824660441 +0300
@@ -0,0 +1,1700 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017  Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * The full GNU General Public License is included in this distribution in the
+ * file called LICENSE.
+ *
+ * Contact Information:
+ * wlanfae <wlanfae@realtek.com>
+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
+ * Hsinchu 300, Taiwan.
+ *
+ * Larry Finger <Larry.Finger@lwfinger.net>
+ *
+ *****************************************************************************/
+
+/*@
+ * ============================================================
+ * include files
+ * ============================================================
+ */
+
+#include "mp_precomp.h"
+#include "phydm_precomp.h"
+
+#if defined(CONFIG_PHYDM_DFS_MASTER)
+
+boolean phydm_dfs_is_meteorology_channel(void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+
+	u8 ch = *dm->channel;
+	u8 bw = *dm->band_width;
+
+	return ((bw  == CHANNEL_WIDTH_80 && (ch) >= 116 && (ch) <= 128) ||
+		(bw  == CHANNEL_WIDTH_40 && (ch) >= 116 && (ch) <= 128) ||
+		(bw  == CHANNEL_WIDTH_20 && (ch) >= 120 && (ch) <= 128));
+}
+
+void phydm_radar_detect_reset(void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+
+	odm_set_bb_reg(dm, R_0x924, BIT(15), 0);
+	odm_set_bb_reg(dm, R_0x924, BIT(15), 1);
+}
+
+void phydm_radar_detect_disable(void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+
+	odm_set_bb_reg(dm, R_0x924, BIT(15), 0);
+	PHYDM_DBG(dm, DBG_DFS, "\n");
+}
+
+static void phydm_radar_detect_with_dbg_parm(void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+
+	odm_set_bb_reg(dm, R_0x918, MASKDWORD, dm->radar_detect_reg_918);
+	odm_set_bb_reg(dm, R_0x91c, MASKDWORD, dm->radar_detect_reg_91c);
+	odm_set_bb_reg(dm, R_0x920, MASKDWORD, dm->radar_detect_reg_920);
+	odm_set_bb_reg(dm, R_0x924, MASKDWORD, dm->radar_detect_reg_924);
+}
+
+/* @Init radar detection parameters, called after ch, bw is set */
+
+void phydm_radar_detect_enable(void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct _DFS_STATISTICS *dfs = &dm->dfs;
+	u8 region_domain = dm->dfs_region_domain;
+	u8 c_channel = *dm->channel;
+	u8 band_width = *dm->band_width;
+	u8 enable = 0;
+	u8 short_pw_upperbound = 0;
+
+	PHYDM_DBG(dm, DBG_DFS, "test, region_domain = %d\n", region_domain);
+	if (region_domain == PHYDM_DFS_DOMAIN_UNKNOWN) {
+		PHYDM_DBG(dm, DBG_DFS, "PHYDM_DFS_DOMAIN_UNKNOWN\n");
+		goto exit;
+	}
+
+	if (dm->support_ic_type & (ODM_RTL8821 | ODM_RTL8812 | ODM_RTL8881A)) {
+		odm_set_bb_reg(dm, R_0x814, 0x3fffffff, 0x04cc4d10);
+		odm_set_bb_reg(dm, R_0x834, MASKBYTE0, 0x06);
+
+		if (dm->radar_detect_dbg_parm_en) {
+			phydm_radar_detect_with_dbg_parm(dm);
+			enable = 1;
+			goto exit;
+		}
+
+		if (region_domain == PHYDM_DFS_DOMAIN_ETSI) {
+			odm_set_bb_reg(dm, R_0x918, MASKDWORD, 0x1c17ecdf);
+			odm_set_bb_reg(dm, R_0x924, MASKDWORD, 0x01528500);
+			odm_set_bb_reg(dm, R_0x91c, MASKDWORD, 0x0fa21a20);
+			odm_set_bb_reg(dm, R_0x920, MASKDWORD, 0xe0f69204);
+
+		} else if (region_domain == PHYDM_DFS_DOMAIN_MKK) {
+			odm_set_bb_reg(dm, R_0x924, MASKDWORD, 0x01528500);
+			odm_set_bb_reg(dm, R_0x920, MASKDWORD, 0xe0d67234);
+
+			if (c_channel >= 52 && c_channel <= 64) {
+				odm_set_bb_reg(dm, R_0x918, MASKDWORD,
+					       0x1c16ecdf);
+				odm_set_bb_reg(dm, R_0x91c, MASKDWORD,
+					       0x0f141a20);
+			} else {
+				odm_set_bb_reg(dm, R_0x918, MASKDWORD,
+					       0x1c16acdf);
+				if (band_width == CHANNEL_WIDTH_20)
+					odm_set_bb_reg(dm, R_0x91c, MASKDWORD,
+						       0x64721a20);
+				else
+					odm_set_bb_reg(dm, R_0x91c, MASKDWORD,
+						       0x68721a20);
+			}
+
+		} else if (region_domain == PHYDM_DFS_DOMAIN_FCC) {
+			odm_set_bb_reg(dm, R_0x918, MASKDWORD, 0x1c16acdf);
+			odm_set_bb_reg(dm, R_0x924, MASKDWORD, 0x01528500);
+			odm_set_bb_reg(dm, R_0x920, MASKDWORD, 0xe0d67231);
+			if (band_width == CHANNEL_WIDTH_20)
+				odm_set_bb_reg(dm, R_0x91c, MASKDWORD,
+					       0x64741a20);
+			else
+				odm_set_bb_reg(dm, R_0x91c, MASKDWORD,
+					       0x68741a20);
+
+		} else {
+			/* not supported */
+			PHYDM_DBG(dm, DBG_DFS,
+				  "Unsupported dfs_region_domain:%d\n",
+				  region_domain);
+			goto exit;
+		}
+
+	} else if (dm->support_ic_type &
+		   (ODM_RTL8814A | ODM_RTL8822B | ODM_RTL8821C)) {
+		/*@for 8822B RXHP H2L, since L will always cause DFS FRD
+		if (dm->support_ic_type & (ODM_RTL8822B)) {
+			odm_set_bb_reg(dm, 0x8d8, MASKDWORD, 0x29035612);
+			odm_set_bb_reg(dm, 0x8cc, MASKDWORD, 0x08108492);
+		}
+		 */
+
+		odm_set_bb_reg(dm, R_0x814, 0x3fffffff, 0x04cc4d10);
+		odm_set_bb_reg(dm, R_0x834, MASKBYTE0, 0x06);
+
+		/* @8822B only, when BW = 20M, DFIR output is 40Mhz,
+		 * but DFS input is 80MMHz, so it need to upgrade to 80MHz
+		 */
+		if (dm->support_ic_type & (ODM_RTL8822B | ODM_RTL8821C)) {
+			if (band_width == CHANNEL_WIDTH_20)
+				odm_set_bb_reg(dm, R_0x1984, BIT(26), 1);
+			else
+				odm_set_bb_reg(dm, R_0x1984, BIT(26), 0);
+		}
+
+		if (dm->radar_detect_dbg_parm_en) {
+			phydm_radar_detect_with_dbg_parm(dm);
+			enable = 1;
+			goto exit;
+		}
+
+		if (region_domain == PHYDM_DFS_DOMAIN_ETSI) {
+			odm_set_bb_reg(dm, R_0x918, MASKDWORD, 0x1c16acdf);
+			odm_set_bb_reg(dm, R_0x924, MASKDWORD, 0x095a8500);
+			odm_set_bb_reg(dm, R_0x91c, MASKDWORD, 0x0fa21a20);
+			odm_set_bb_reg(dm, R_0x920, MASKDWORD, 0xe0f57204);
+
+		} else if (region_domain == PHYDM_DFS_DOMAIN_MKK) {
+			odm_set_bb_reg(dm, R_0x924, MASKDWORD, 0x095a8500);
+			odm_set_bb_reg(dm, R_0x920, MASKDWORD, 0xe0d67234);
+
+			if (c_channel >= 52 && c_channel <= 64) {
+				odm_set_bb_reg(dm, R_0x918, MASKDWORD,
+					       0x1c16ecdf);
+				odm_set_bb_reg(dm, R_0x91c, MASKDWORD,
+					       0x0f141a20);
+			} else {
+				odm_set_bb_reg(dm, R_0x918, MASKDWORD,
+					       0x1c166cdf);
+				if (band_width == CHANNEL_WIDTH_20)
+					odm_set_bb_reg(dm, R_0x91c, MASKDWORD,
+						       0x64721a20);
+				else
+					odm_set_bb_reg(dm, R_0x91c, MASKDWORD,
+						       0x68721a20);
+			}
+
+		} else if (region_domain == PHYDM_DFS_DOMAIN_FCC) {
+			odm_set_bb_reg(dm, R_0x918, MASKDWORD, 0x1c176cdf);
+			odm_set_bb_reg(dm, R_0x924, MASKDWORD, 0x095a8400);
+			odm_set_bb_reg(dm, R_0x920, MASKDWORD, 0xe076d231);
+			if (band_width == CHANNEL_WIDTH_20)
+				odm_set_bb_reg(dm, R_0x91c, MASKDWORD,
+					       0x64901a20);
+			else
+				odm_set_bb_reg(dm, R_0x91c, MASKDWORD,
+					       0x62901a20);
+
+		} else {
+			/* not supported */
+			PHYDM_DBG(dm, DBG_DFS,
+				  "Unsupported dfs_region_domain:%d\n",
+				  region_domain);
+			goto exit;
+		}
+		/*RXHP low corner will extend the pulse width,
+		 *so we need to increase the upper bound.
+		 */
+		if (dm->support_ic_type & (ODM_RTL8822B | ODM_RTL8821C)) {
+			if (odm_get_bb_reg(dm, 0x8d8,
+					   BIT28 | BIT27 | BIT26) == 0) {
+				short_pw_upperbound =
+					(u8)odm_get_bb_reg(dm, 0x91c,
+						       BIT23 | BIT22 |
+						       BIT21 | BIT20);
+				if ((short_pw_upperbound + 4) > 15)
+					odm_set_bb_reg(dm, 0x91c,
+						       BIT23 | BIT22 |
+						       BIT21 | BIT20, 15);
+				else
+					odm_set_bb_reg(dm, 0x91c,
+						       BIT23 | BIT22 |
+						       BIT21 | BIT20,
+						       short_pw_upperbound + 4);
+			}
+			/*@if peak index -1~+1, use original NB method*/
+			odm_set_bb_reg(dm, 0x19e4, 0x003C0000, 13);
+			odm_set_bb_reg(dm, 0x924, 0x70000, 0);
+		}
+
+		if (dm->support_ic_type & (ODM_RTL8881A))
+			odm_set_bb_reg(dm, 0xb00, 0xc0000000, 3);
+
+		/*@for 8814 new dfs mechanism setting*/
+		if (dm->support_ic_type &
+		    (ODM_RTL8814A | ODM_RTL8822B | ODM_RTL8821C)) {
+			/*Turn off dfs scaling factor*/
+			odm_set_bb_reg(dm, 0x19e4, 0x1fff, 0x0c00);
+			/*NonDC peak_th = 2times DC peak_th*/
+			odm_set_bb_reg(dm, 0x19e4, 0x30000, 1);
+			/*power for debug and auto test flow latch after ST*/
+			odm_set_bb_reg(dm, 0x9f8, 0xc0000000, 3);
+
+			/*@low pulse width radar pattern will cause wrong drop*/
+			/*@disable peak index should the same
+			 *during the same short pulse (new mechan)
+			 */
+			odm_set_bb_reg(dm, 0x9f4, 0x80000000, 0);
+
+			/*@disable peak index should the same
+			 *during the same short pulse (old mechan)
+			 */
+			odm_set_bb_reg(dm, 0x924, 0x20000000, 0);
+
+			/*@if peak index diff >=2, then drop the result*/
+			odm_set_bb_reg(dm, 0x19e4, 0xe000, 2);
+			if (region_domain == 2) {
+				if ((c_channel >= 52) && (c_channel <= 64)) {
+					/*pulse width hist th setting*/
+					/*th1=2*04us*/
+					odm_set_bb_reg(dm, 0x19e4,
+						       0xff000000, 2);
+					/*th2 = 3*0.4us, th3 = 4*0.4us
+					 *th4 = 7*0.4, th5 = 34*0.4
+					 */
+					odm_set_bb_reg(dm, 0x19e8,
+						       MASKDWORD, 0x22070403);
+
+					/*PRI hist th setting*/
+					/*th1=42*32us*/
+					odm_set_bb_reg(dm, 0x19b8,
+						       0x00007f80, 42);
+					/*th2=47*32us, th3=115*32us,
+					 *th4=123*32us, th5=130*32us
+					 */
+					odm_set_bb_reg(dm, 0x19ec,
+						       MASKDWORD, 0x827b732f);
+				} else{
+					/*pulse width hist th setting*/
+					/*th1=2*04us*/
+					odm_set_bb_reg(dm, 0x19e4,
+						       0xff000000, 1);
+					/*th2 = 13*0.4us, th3 = 26*0.4us
+					 *th4 = 75*0.4us, th5 = 255*0.4us
+					 */
+					odm_set_bb_reg(dm, 0x19e8,
+						       MASKDWORD, 0xff4b1a0d);
+					/*PRI hist th setting*/
+					/*th1=4*32us*/
+
+					odm_set_bb_reg(dm, 0x19b8,
+						       0x00007f80, 4);
+					/*th2=8*32us, th3=16*32us,
+					 *th4=32*32us, th5=128*32=4096us
+					 */
+					odm_set_bb_reg(dm, 0x19ec,
+						       MASKDWORD, 0x80201008);
+				}
+			}
+			/*@ETSI*/
+			else if (region_domain == 3) {
+				/*pulse width hist th setting*/
+				/*th1=2*04us*/
+				odm_set_bb_reg(dm, 0x19e4, 0xff000000, 1);
+				odm_set_bb_reg(dm, 0x19e8,
+					       MASKDWORD, 0x68260d06);
+				/*PRI hist th setting*/
+				/*th1=7*32us*/
+				odm_set_bb_reg(dm, 0x19b8, 0x00007f80, 7);
+				/*th2=40*32us, th3=80*32us,
+				 *th4=110*32us, th5=157*32=5024
+				 */
+				odm_set_bb_reg(dm, 0x19ec,
+					       MASKDWORD, 0x9d6e2010);
+			}
+			/*@FCC*/
+			else if (region_domain == 1) {
+				/*pulse width hist th setting*/
+				/*th1=2*04us*/
+				odm_set_bb_reg(dm, 0x19e4, 0xff000000, 2);
+				/*th2 = 13*0.4us, th3 = 26*0.4us,
+				 *th4 = 75*0.4us, th5 = 255*0.4us
+				 */
+				odm_set_bb_reg(dm, 0x19e8,
+					       MASKDWORD, 0xff4b1a0d);
+
+				/*PRI hist th setting*/
+				/*th1=4*32us*/
+				odm_set_bb_reg(dm, 0x19b8, 0x00007f80, 4);
+				/*th2=8*32us, th3=21*32us,
+				 *th4=32*32us, th5=96*32=3072
+				 */
+				if (band_width == CHANNEL_WIDTH_20)
+					odm_set_bb_reg(dm, 0x19ec,
+						       MASKDWORD, 0x60282010);
+				else
+					odm_set_bb_reg(dm, 0x19ec,
+						       MASKDWORD, 0x60282420);
+			} else {
+			}
+		}
+	} else {
+		/*not supported IC type*/
+		PHYDM_DBG(dm, DBG_DFS, "Unsupported IC type:%d\n",
+			  dm->support_ic_type);
+		goto exit;
+	}
+
+	enable = 1;
+
+	dfs->st_l2h_cur = (u8)odm_get_bb_reg(dm, R_0x91c, 0x000000ff);
+	dfs->pwdb_th_cur = (u8)odm_get_bb_reg(dm, R_0x918, 0x00001f00);
+	dfs->peak_th = (u8)odm_get_bb_reg(dm, R_0x918, 0x00030000);
+	dfs->short_pulse_cnt_th = (u8)odm_get_bb_reg(dm, R_0x920, 0x000f0000);
+	dfs->long_pulse_cnt_th = (u8)odm_get_bb_reg(dm, R_0x920, 0x00f00000);
+	dfs->peak_window = (u8)odm_get_bb_reg(dm, R_0x920, 0x00000300);
+	dfs->three_peak_opt = (u8)odm_get_bb_reg(dm, 0x924, 0x00000180);
+	dfs->three_peak_th2 = (u8)odm_get_bb_reg(dm, 0x924, 0x00007000);
+
+	phydm_dfs_parameter_init(dm);
+
+exit:
+	if (enable) {
+		phydm_radar_detect_reset(dm);
+		PHYDM_DBG(dm, DBG_DFS, "on cch:%u, bw:%u\n", c_channel,
+			  band_width);
+	} else
+		phydm_radar_detect_disable(dm);
+}
+
+void phydm_dfs_parameter_init(void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct _DFS_STATISTICS *dfs = &dm->dfs;
+
+	u8 i;
+
+	dfs->fa_mask_th = 30;
+	dfs->force_TP_mode = 0;
+	dfs->det_print = 0;
+	dfs->det_print2 = 0;
+	dfs->print_hist_rpt = 0;
+	dfs->hist_cond_on = 1;
+	dfs->st_l2h_min = 0x20;
+	dfs->st_l2h_max = 0x4e;
+	dfs->pwdb_scalar_factor = 12;
+	dfs->pwdb_th = 8;
+	for (i = 0; i < 5; i++) {
+		dfs->pulse_flag_hist[i] = 0;
+		dfs->pulse_type_hist[i] = 0;
+		dfs->radar_det_mask_hist[i] = 0;
+		dfs->fa_inc_hist[i] = 0;
+	}
+
+	/*@for dfs histogram*/
+	dfs->pri_hist_th = 5;
+	dfs->pri_sum_g1_th = 9;
+	dfs->pri_sum_g5_th = 4;
+	dfs->pri_sum_g1_fcc_th = 4;		/*@FCC Type6*/
+	dfs->pri_sum_g3_fcc_th = 6;
+	dfs->pri_sum_safe_th = 50;
+	dfs->pri_sum_safe_fcc_th = 110;		/*@30 for AP*/
+	dfs->pri_sum_type4_th = 16;
+	dfs->pri_sum_type6_th = 12;
+	dfs->pri_sum_g5_under_g1_th = 0;
+	dfs->pri_pw_diff_th = 4;
+	dfs->pri_pw_diff_fcc_th = 8;
+	dfs->pri_pw_diff_fcc_idle_th = 2;
+	dfs->pri_pw_diff_w53_th = 10;
+	dfs->pw_std_th = 7;			/*@FCC Type4*/
+	dfs->pw_std_idle_th = 10;
+	dfs->pri_std_th = 6;			/*@FCC Type3,4,6*/
+	dfs->pri_std_idle_th = 10;
+	dfs->pri_type1_upp_fcc_th = 110;
+	dfs->pri_type1_low_fcc_th = 50;
+	dfs->pri_type1_cen_fcc_th = 70;
+	dfs->pw_g0_th = 8;
+	dfs->pw_long_lower_th = 6;		/*@7->6*/
+	dfs->pri_long_upper_th = 30;
+	dfs->pw_long_lower_20m_th = 7;		/*@7 for AP*/
+	dfs->pw_long_sum_upper_th = 60;
+	dfs->type4_pw_max_cnt = 7;
+	dfs->type4_safe_pri_sum_th = 5;
+}
+
+void phydm_dfs_dynamic_setting(
+	void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct _DFS_STATISTICS *dfs = &dm->dfs;
+
+	u8 peak_th_cur = 0, short_pulse_cnt_th_cur = 0;
+	u8 long_pulse_cnt_th_cur = 0, three_peak_opt_cur = 0;
+	u8 three_peak_th2_cur = 0;
+	u8 peak_window_cur = 0;
+	u8 region_domain = dm->dfs_region_domain;
+	u8 c_channel = *dm->channel;
+
+	if (dm->rx_tp + dm->tx_tp <= 2) {
+		dfs->idle_mode = 1;
+		if (dfs->force_TP_mode)
+			dfs->idle_mode = 0;
+	} else {
+		dfs->idle_mode = 0;
+	}
+
+	if (dfs->idle_mode == 1) { /*@idle (no traffic)*/
+		peak_th_cur = 3;
+		short_pulse_cnt_th_cur = 6;
+		long_pulse_cnt_th_cur = 9;
+		peak_window_cur = 2;
+		three_peak_opt_cur = 0;
+		three_peak_th2_cur = 2;
+		if (region_domain == PHYDM_DFS_DOMAIN_MKK) {
+			if (c_channel >= 52 && c_channel <= 64) {
+				short_pulse_cnt_th_cur = 14;
+				long_pulse_cnt_th_cur = 15;
+				three_peak_th2_cur = 0;
+			} else {
+				short_pulse_cnt_th_cur = 6;
+				three_peak_th2_cur = 0;
+				long_pulse_cnt_th_cur = 10;
+			}
+		} else if (region_domain == PHYDM_DFS_DOMAIN_FCC) {
+			three_peak_th2_cur = 0;
+		} else if (region_domain == PHYDM_DFS_DOMAIN_ETSI) {
+			long_pulse_cnt_th_cur = 15;
+			if (phydm_dfs_is_meteorology_channel(dm)) {
+			/*need to add check cac end condition*/
+				peak_th_cur = 2;
+				three_peak_opt_cur = 0;
+				three_peak_th2_cur = 0;
+				short_pulse_cnt_th_cur = 7;
+			} else {
+				three_peak_opt_cur = 0;
+				three_peak_th2_cur = 0;
+				short_pulse_cnt_th_cur = 7;
+			}
+		} else /*@default: FCC*/
+			three_peak_th2_cur = 0;
+
+	} else { /*@in service (with TP)*/
+		peak_th_cur = 2;
+		short_pulse_cnt_th_cur = 6;
+		long_pulse_cnt_th_cur = 7;
+		peak_window_cur = 2;
+		three_peak_opt_cur = 0;
+		three_peak_th2_cur = 2;
+		if (region_domain == PHYDM_DFS_DOMAIN_MKK) {
+			if (c_channel >= 52 && c_channel <= 64) {
+				long_pulse_cnt_th_cur = 15;
+				/*@for high duty cycle*/
+				short_pulse_cnt_th_cur = 5;
+				three_peak_th2_cur = 0;
+			} else {
+				three_peak_opt_cur = 0;
+				three_peak_th2_cur = 0;
+				long_pulse_cnt_th_cur = 8;
+			}
+		} else if (region_domain == PHYDM_DFS_DOMAIN_FCC) {
+			long_pulse_cnt_th_cur = 5;	/*for 80M FCC*/
+			short_pulse_cnt_th_cur = 5;	/*for 80M FCC*/
+		} else if (region_domain == PHYDM_DFS_DOMAIN_ETSI) {
+			long_pulse_cnt_th_cur = 15;
+			short_pulse_cnt_th_cur = 5;
+			three_peak_opt_cur = 0;
+		}
+	}
+	if (dfs->peak_th != peak_th_cur)
+		odm_set_bb_reg(dm, 0x918, 0x00030000, peak_th_cur);
+	if (dfs->short_pulse_cnt_th != short_pulse_cnt_th_cur)
+		odm_set_bb_reg(dm, 0x920, 0x000f0000, short_pulse_cnt_th_cur);
+	if (dfs->long_pulse_cnt_th != long_pulse_cnt_th_cur)
+		odm_set_bb_reg(dm, 0x920, 0x00f00000, long_pulse_cnt_th_cur);
+	if (dfs->peak_window != peak_window_cur)
+		odm_set_bb_reg(dm, 0x920, 0x00000300, peak_window_cur);
+	if (dfs->three_peak_opt != three_peak_opt_cur)
+		odm_set_bb_reg(dm, 0x924, 0x00000180, three_peak_opt_cur);
+	if (dfs->three_peak_th2 != three_peak_th2_cur)
+		odm_set_bb_reg(dm, 0x924, 0x00007000, three_peak_th2_cur);
+
+	dfs->peak_th = peak_th_cur;
+	dfs->short_pulse_cnt_th = short_pulse_cnt_th_cur;
+	dfs->long_pulse_cnt_th = long_pulse_cnt_th_cur;
+	dfs->peak_window = peak_window_cur;
+	dfs->three_peak_opt = three_peak_opt_cur;
+	dfs->three_peak_th2 = three_peak_th2_cur;
+}
+
+boolean
+phydm_radar_detect_dm_check(
+	void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct _DFS_STATISTICS *dfs = &dm->dfs;
+	u8 region_domain = dm->dfs_region_domain, index = 0;
+
+	u16 i = 0, j = 0, k = 0, fa_count_cur = 0, fa_count_inc = 0;
+	u16 total_fa_in_hist = 0, pre_post_now_acc_fa_in_hist = 0;
+	u16 max_fa_in_hist = 0, vht_crc_ok_cnt_cur = 0;
+	u16 vht_crc_ok_cnt_inc = 0, ht_crc_ok_cnt_cur = 0;
+	u16 ht_crc_ok_cnt_inc = 0, leg_crc_ok_cnt_cur = 0;
+	u16 leg_crc_ok_cnt_inc = 0;
+	u16 total_crc_ok_cnt_inc = 0, short_pulse_cnt_cur = 0;
+	u16 short_pulse_cnt_inc = 0, long_pulse_cnt_cur = 0;
+	u16 long_pulse_cnt_inc = 0, total_pulse_count_inc = 0;
+	u32 regf98_value = 0, reg918_value = 0, reg91c_value = 0;
+	u32 reg920_value = 0, reg924_value = 0;
+	boolean tri_short_pulse = 0, tri_long_pulse = 0, radar_type = 0;
+	boolean fault_flag_det = 0, fault_flag_psd = 0, fa_flag = 0;
+	boolean radar_detected = 0;
+	u8 st_l2h_new = 0, fa_mask_th = 0, sum = 0;
+	u8 c_channel = *dm->channel;
+
+	/*@Get FA count during past 100ms*/
+	fa_count_cur = (u16)odm_get_bb_reg(dm, R_0xf48, 0x0000ffff);
+
+	if (dfs->fa_count_pre == 0)
+		fa_count_inc = 0;
+	else if (fa_count_cur >= dfs->fa_count_pre)
+		fa_count_inc = fa_count_cur - dfs->fa_count_pre;
+	else
+		fa_count_inc = fa_count_cur;
+	dfs->fa_count_pre = fa_count_cur;
+
+	dfs->fa_inc_hist[dfs->mask_idx] = fa_count_inc;
+
+	for (i = 0; i < 5; i++) {
+		total_fa_in_hist = total_fa_in_hist + dfs->fa_inc_hist[i];
+		if (dfs->fa_inc_hist[i] > max_fa_in_hist)
+			max_fa_in_hist = dfs->fa_inc_hist[i];
+	}
+	if (dfs->mask_idx >= 2)
+		index = dfs->mask_idx - 2;
+	else
+		index = 5 + dfs->mask_idx - 2;
+	if (index == 0) {
+		pre_post_now_acc_fa_in_hist = dfs->fa_inc_hist[index] +
+					      dfs->fa_inc_hist[index + 1] +
+					      dfs->fa_inc_hist[4];
+	} else if (index == 4) {
+		pre_post_now_acc_fa_in_hist = dfs->fa_inc_hist[index] +
+					      dfs->fa_inc_hist[0] +
+					      dfs->fa_inc_hist[index - 1];
+	} else {
+		pre_post_now_acc_fa_in_hist = dfs->fa_inc_hist[index] +
+					      dfs->fa_inc_hist[index + 1] +
+					      dfs->fa_inc_hist[index - 1];
+	}
+
+	/*@Get VHT CRC32 ok count during past 100ms*/
+	vht_crc_ok_cnt_cur = (u16)odm_get_bb_reg(dm, R_0xf0c, 0x00003fff);
+	if (vht_crc_ok_cnt_cur >= dfs->vht_crc_ok_cnt_pre) {
+		vht_crc_ok_cnt_inc = vht_crc_ok_cnt_cur -
+				     dfs->vht_crc_ok_cnt_pre;
+	} else {
+		vht_crc_ok_cnt_inc = vht_crc_ok_cnt_cur;
+	}
+	dfs->vht_crc_ok_cnt_pre = vht_crc_ok_cnt_cur;
+
+	/*@Get HT CRC32 ok count during past 100ms*/
+	ht_crc_ok_cnt_cur = (u16)odm_get_bb_reg(dm, R_0xf10, 0x00003fff);
+	if (ht_crc_ok_cnt_cur >= dfs->ht_crc_ok_cnt_pre)
+		ht_crc_ok_cnt_inc = ht_crc_ok_cnt_cur - dfs->ht_crc_ok_cnt_pre;
+	else
+		ht_crc_ok_cnt_inc = ht_crc_ok_cnt_cur;
+	dfs->ht_crc_ok_cnt_pre = ht_crc_ok_cnt_cur;
+
+	/*@Get Legacy CRC32 ok count during past 100ms*/
+	leg_crc_ok_cnt_cur = (u16)odm_get_bb_reg(dm, R_0xf14, 0x00003fff);
+	if (leg_crc_ok_cnt_cur >= dfs->leg_crc_ok_cnt_pre)
+		leg_crc_ok_cnt_inc = leg_crc_ok_cnt_cur - dfs->leg_crc_ok_cnt_pre;
+	else
+		leg_crc_ok_cnt_inc = leg_crc_ok_cnt_cur;
+	dfs->leg_crc_ok_cnt_pre = leg_crc_ok_cnt_cur;
+
+	if (vht_crc_ok_cnt_cur == 0x3fff ||
+	    ht_crc_ok_cnt_cur == 0x3fff ||
+	    leg_crc_ok_cnt_cur == 0x3fff) {
+		phydm_reset_bb_hw_cnt_ac(dm);
+		/*@*/
+	}
+
+	total_crc_ok_cnt_inc = vht_crc_ok_cnt_inc +
+			       ht_crc_ok_cnt_inc +
+			       leg_crc_ok_cnt_inc;
+
+	/*@Get short pulse count, need carefully handle the counter overflow*/
+	regf98_value = odm_get_bb_reg(dm, R_0xf98, 0xffffffff);
+	short_pulse_cnt_cur = (u16)(regf98_value & 0x000000ff);
+	if (short_pulse_cnt_cur >= dfs->short_pulse_cnt_pre) {
+		short_pulse_cnt_inc = short_pulse_cnt_cur -
+				      dfs->short_pulse_cnt_pre;
+	} else {
+		short_pulse_cnt_inc = short_pulse_cnt_cur;
+	}
+	dfs->short_pulse_cnt_pre = short_pulse_cnt_cur;
+
+	/*@Get long pulse count, need carefully handle the counter overflow*/
+	long_pulse_cnt_cur = (u16)((regf98_value & 0x0000ff00) >> 8);
+	if (long_pulse_cnt_cur >= dfs->long_pulse_cnt_pre) {
+		long_pulse_cnt_inc = long_pulse_cnt_cur -
+				     dfs->long_pulse_cnt_pre;
+	} else {
+		long_pulse_cnt_inc = long_pulse_cnt_cur;
+	}
+	dfs->long_pulse_cnt_pre = long_pulse_cnt_cur;
+
+	total_pulse_count_inc = short_pulse_cnt_inc + long_pulse_cnt_inc;
+
+	if (dfs->det_print) {
+		PHYDM_DBG(dm, DBG_DFS,
+			  "===============================================\n");
+		PHYDM_DBG(dm, DBG_DFS,
+			  "Total_CRC_OK_cnt_inc[%d] VHT_CRC_ok_cnt_inc[%d] HT_CRC_ok_cnt_inc[%d] LEG_CRC_ok_cnt_inc[%d] FA_count_inc[%d]\n",
+			  total_crc_ok_cnt_inc, vht_crc_ok_cnt_inc,
+			  ht_crc_ok_cnt_inc, leg_crc_ok_cnt_inc, fa_count_inc);
+		PHYDM_DBG(dm, DBG_DFS,
+			  "Init_Gain[%x] 0x91c[%x] 0xf98[%08x] short_pulse_cnt_inc[%d] long_pulse_cnt_inc[%d]\n",
+			  dfs->igi_cur, dfs->st_l2h_cur, regf98_value,
+			  short_pulse_cnt_inc, long_pulse_cnt_inc);
+		PHYDM_DBG(dm, DBG_DFS, "Throughput: %dMbps\n",
+			  dm->rx_tp + dm->tx_tp);
+			  reg918_value = odm_get_bb_reg(dm, R_0x918,
+							0xffffffff);
+			  reg91c_value = odm_get_bb_reg(dm, R_0x91c,
+							0xffffffff);
+			  reg920_value = odm_get_bb_reg(dm, R_0x920,
+							0xffffffff);
+			  reg924_value = odm_get_bb_reg(dm, R_0x924,
+							0xffffffff);
+		PHYDM_DBG(dm, DBG_DFS,
+			  "0x918[%08x] 0x91c[%08x] 0x920[%08x] 0x924[%08x]\n",
+			  reg918_value, reg91c_value,
+			  reg920_value, reg924_value);
+		PHYDM_DBG(dm, DBG_DFS,
+			  "dfs_regdomain = %d, dbg_mode = %d, idle_mode = %d, print_hist_rpt = %d, hist_cond_on = %d\n",
+			  region_domain, dfs->dbg_mode,
+			  dfs->idle_mode, dfs->print_hist_rpt,
+			  dfs->hist_cond_on);
+	}
+	tri_short_pulse = (regf98_value & BIT(17)) ? 1 : 0;
+	tri_long_pulse = (regf98_value & BIT(19)) ? 1 : 0;
+
+	if (tri_short_pulse) {
+		odm_set_bb_reg(dm, R_0x924, BIT(15), 0);
+		odm_set_bb_reg(dm, R_0x924, BIT(15), 1);
+	}
+	if (tri_long_pulse) {
+		odm_set_bb_reg(dm, R_0x924, BIT(15), 0);
+		odm_set_bb_reg(dm, R_0x924, BIT(15), 1);
+		if (region_domain == PHYDM_DFS_DOMAIN_MKK) {
+			if (c_channel >= 52 && c_channel <= 64) {
+				tri_long_pulse = 0;
+			}
+		}
+		if (region_domain == PHYDM_DFS_DOMAIN_ETSI) {
+			tri_long_pulse = 0;
+		}
+	}
+
+	st_l2h_new = dfs->st_l2h_cur;
+	dfs->pulse_flag_hist[dfs->mask_idx] = tri_short_pulse | tri_long_pulse;
+	dfs->pulse_type_hist[dfs->mask_idx] = (tri_long_pulse) ? 1 : 0;
+
+	/* PSD(not ready) */
+
+	fault_flag_det = 0;
+	fault_flag_psd = 0;
+	fa_flag = 0;
+	if (region_domain == PHYDM_DFS_DOMAIN_ETSI) {
+		fa_mask_th = dfs->fa_mask_th + 20;
+	} else {
+		fa_mask_th = dfs->fa_mask_th;
+	}
+	if (max_fa_in_hist >= fa_mask_th ||
+	    total_fa_in_hist >= fa_mask_th ||
+	    pre_post_now_acc_fa_in_hist >= fa_mask_th ||
+	    dfs->igi_cur >= 0x30) {
+		st_l2h_new = dfs->st_l2h_max;
+		dfs->radar_det_mask_hist[index] = 1;
+		if (dfs->pulse_flag_hist[index] == 1) {
+			dfs->pulse_flag_hist[index] = 0;
+			if (dfs->det_print2) {
+				PHYDM_DBG(dm, DBG_DFS,
+					  "Radar is masked : FA mask\n");
+			}
+		}
+		fa_flag = 1;
+	} else {
+		dfs->radar_det_mask_hist[index] = 0;
+	}
+
+	if (dfs->det_print) {
+		PHYDM_DBG(dm, DBG_DFS, "mask_idx: %d\n", dfs->mask_idx);
+		PHYDM_DBG(dm, DBG_DFS, "radar_det_mask_hist: ");
+		for (i = 0; i < 5; i++)
+			PHYDM_DBG(dm, DBG_DFS, "%d ",
+				  dfs->radar_det_mask_hist[i]);
+		PHYDM_DBG(dm, DBG_DFS, "pulse_flag_hist: ");
+		for (i = 0; i < 5; i++)
+			PHYDM_DBG(dm, DBG_DFS, "%d ", dfs->pulse_flag_hist[i]);
+		PHYDM_DBG(dm, DBG_DFS, "fa_inc_hist: ");
+		for (i = 0; i < 5; i++)
+			PHYDM_DBG(dm, DBG_DFS, "%d ", dfs->fa_inc_hist[i]);
+		PHYDM_DBG(dm, DBG_DFS,
+			  "\nfa_mask_th: %d max_fa_in_hist: %d total_fa_in_hist: %d pre_post_now_acc_fa_in_hist: %d ",
+			  fa_mask_th, max_fa_in_hist, total_fa_in_hist,
+			  pre_post_now_acc_fa_in_hist);
+	}
+
+	sum = 0;
+	for (k = 0; k < 5; k++) {
+		if (dfs->radar_det_mask_hist[k] == 1)
+			sum++;
+	}
+
+	if (dfs->mask_hist_checked <= 5)
+		dfs->mask_hist_checked++;
+
+	if (dfs->mask_hist_checked >= 5 && dfs->pulse_flag_hist[index]) {
+		if (sum <= 2) {
+			if (dfs->hist_cond_on) {
+				/*return the value from hist_radar_detected*/
+				radar_detected = phydm_dfs_hist_log(dm, index);
+			} else {
+				if (dfs->pulse_type_hist[index] == 0)
+					dfs->radar_type = 0;
+				else if (dfs->pulse_type_hist[index] == 1)
+					dfs->radar_type = 1;
+				radar_detected = 1;
+				PHYDM_DBG(dm, DBG_DFS,
+					  "Detected type %d radar signal!\n",
+					  dfs->radar_type);
+			}
+		} else {
+			fault_flag_det = 1;
+			if (dfs->det_print2) {
+				PHYDM_DBG(dm, DBG_DFS,
+					  "Radar is masked : mask_hist large than thd\n");
+			}
+		}
+	}
+
+	dfs->mask_idx++;
+	if (dfs->mask_idx == 5)
+		dfs->mask_idx = 0;
+
+	if (fault_flag_det == 0 && fault_flag_psd == 0 && fa_flag == 0) {
+		if (dfs->igi_cur < 0x30) {
+			st_l2h_new = dfs->st_l2h_min;
+		}
+	}
+
+	if (st_l2h_new != dfs->st_l2h_cur) {
+		if (st_l2h_new < dfs->st_l2h_min) {
+			dfs->st_l2h_cur = dfs->st_l2h_min;
+		} else if (st_l2h_new > dfs->st_l2h_max)
+			dfs->st_l2h_cur = dfs->st_l2h_max;
+		else
+			dfs->st_l2h_cur = st_l2h_new;
+		/*odm_set_bb_reg(dm, R_0x91c, 0xff, dfs->st_l2h_cur);*/
+
+		dfs->pwdb_th_cur = ((int)dfs->st_l2h_cur - (int)dfs->igi_cur)
+				    / 2 + dfs->pwdb_scalar_factor;
+
+		/*@limit the pwdb value to absolute lower bound 8*/
+		dfs->pwdb_th_cur = MAX_2(dfs->pwdb_th_cur, (int)dfs->pwdb_th);
+
+		/*@limit the pwdb value to absolute upper bound 0x1f*/
+		dfs->pwdb_th_cur = MIN_2(dfs->pwdb_th_cur, 0x1f);
+		odm_set_bb_reg(dm, R_0x918, 0x00001f00, dfs->pwdb_th_cur);
+	}
+
+	if (dfs->det_print) {
+		PHYDM_DBG(dm, DBG_DFS,
+			  "fault_flag_det[%d], fault_flag_psd[%d], DFS_detected [%d]\n",
+			  fault_flag_det, fault_flag_psd, radar_detected);
+	}
+
+	return radar_detected;
+}
+
+void phydm_dfs_histogram_radar_distinguish(
+	void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct _DFS_STATISTICS *dfs = &dm->dfs;
+	u8 region_domain = dm->dfs_region_domain;
+	u8 c_channel = *dm->channel;
+	u8 band_width = *dm->band_width;
+
+	u8 dfs_pw_thd1 = 0, dfs_pw_thd2 = 0, dfs_pw_thd3 = 0;
+	u8 dfs_pw_thd4 = 0, dfs_pw_thd5 = 0;
+	u8 dfs_pri_thd1 = 0, dfs_pri_thd2 = 0, dfs_pri_thd3 = 0;
+	u8 dfs_pri_thd4 = 0, dfs_pri_thd5 = 0;
+	u8 pri_th = 0, i = 0;
+	u8 max_pri_idx = 0, max_pw_idx = 0, max_pri_cnt_th = 0;
+	u8 max_pri_cnt_fcc_g1_th = 0, max_pri_cnt_fcc_g3_th = 0;
+	u8 safe_pri_pw_diff_th = 0, safe_pri_pw_diff_fcc_th = 0;
+	u8 safe_pri_pw_diff_w53_th = 0, safe_pri_pw_diff_fcc_idle_th = 0;
+	u16 j = 0;
+	u32 dfs_hist1_peak_index = 0, dfs_hist2_peak_index = 0;
+	u32 dfs_hist1_pw = 0, dfs_hist2_pw = 0, g_pw[6] = {0};
+	u32 g_peakindex[16] = {0}, g_mask_32 = 0, false_peak_hist1 = 0;
+	u32 false_peak_hist2_above10 = 0, false_peak_hist2_above0 = 0;
+	u32 dfs_hist1_pri = 0, dfs_hist2_pri = 0, g_pri[6] = {0};
+	u32 pw_sum_g0g5 = 0, pw_sum_g1g2g3g4 = 0;
+	u32 pri_sum_g0g5 = 0, pri_sum_g1g2g3g4 = 0;
+	u32 pw_sum_ss_g1g2g3g4 = 0, pri_sum_ss_g1g2g3g4 = 0;
+	u32 max_pri_cnt = 0, max_pw_cnt = 0;
+
+	/*read peak index hist report*/
+	odm_set_bb_reg(dm, 0x19e4, BIT(22) | BIT(23), 0x0);
+	dfs_hist1_peak_index = odm_get_bb_reg(dm, 0xf5c, 0xffffffff);
+	dfs_hist2_peak_index = odm_get_bb_reg(dm, 0xf74, 0xffffffff);
+
+	g_peakindex[15] = ((dfs_hist1_peak_index & 0x0000000f) >> 0);
+	g_peakindex[14] = ((dfs_hist1_peak_index & 0x000000f0) >> 4);
+	g_peakindex[13] = ((dfs_hist1_peak_index & 0x00000f00) >> 8);
+	g_peakindex[12] = ((dfs_hist1_peak_index & 0x0000f000) >> 12);
+	g_peakindex[11] = ((dfs_hist1_peak_index & 0x000f0000) >> 16);
+	g_peakindex[10] = ((dfs_hist1_peak_index & 0x00f00000) >> 20);
+	g_peakindex[9] = ((dfs_hist1_peak_index & 0x0f000000) >> 24);
+	g_peakindex[8] = ((dfs_hist1_peak_index & 0xf0000000) >> 28);
+	g_peakindex[7] = ((dfs_hist2_peak_index & 0x0000000f) >> 0);
+	g_peakindex[6] = ((dfs_hist2_peak_index & 0x000000f0) >> 4);
+	g_peakindex[5] = ((dfs_hist2_peak_index & 0x00000f00) >> 8);
+	g_peakindex[4] = ((dfs_hist2_peak_index & 0x0000f000) >> 12);
+	g_peakindex[3] = ((dfs_hist2_peak_index & 0x000f0000) >> 16);
+	g_peakindex[2] = ((dfs_hist2_peak_index & 0x00f00000) >> 20);
+	g_peakindex[1] = ((dfs_hist2_peak_index & 0x0f000000) >> 24);
+	g_peakindex[0] = ((dfs_hist2_peak_index & 0xf0000000) >> 28);
+
+	/*read pulse width hist report*/
+	odm_set_bb_reg(dm, 0x19e4, BIT(22) | BIT(23), 0x1);
+	dfs_hist1_pw = odm_get_bb_reg(dm, 0xf5c, 0xffffffff);
+	dfs_hist2_pw = odm_get_bb_reg(dm, 0xf74, 0xffffffff);
+
+	g_pw[0] = (unsigned int)((dfs_hist2_pw & 0xff000000) >> 24);
+	g_pw[1] = (unsigned int)((dfs_hist2_pw & 0x00ff0000) >> 16);
+	g_pw[2] = (unsigned int)((dfs_hist2_pw & 0x0000ff00) >> 8);
+	g_pw[3] = (unsigned int)dfs_hist2_pw & 0x000000ff;
+	g_pw[4] = (unsigned int)((dfs_hist1_pw & 0xff000000) >> 24);
+	g_pw[5] = (unsigned int)((dfs_hist1_pw & 0x00ff0000) >> 16);
+
+	/*read pulse repetition interval hist report*/
+	odm_set_bb_reg(dm, 0x19e4, BIT(22) | BIT(23), 0x3);
+	dfs_hist1_pri = odm_get_bb_reg(dm, 0xf5c, 0xffffffff);
+	dfs_hist2_pri = odm_get_bb_reg(dm, 0xf74, 0xffffffff);
+	odm_set_bb_reg(dm, 0x19b4, 0x10000000, 1); /*reset histo report*/
+	odm_set_bb_reg(dm, 0x19b4, 0x10000000, 0); /*@continue histo report*/
+
+	g_pri[0] = (unsigned int)((dfs_hist2_pri & 0xff000000) >> 24);
+	g_pri[1] = (unsigned int)((dfs_hist2_pri & 0x00ff0000) >> 16);
+	g_pri[2] = (unsigned int)((dfs_hist2_pri & 0x0000ff00) >> 8);
+	g_pri[3] = (unsigned int)dfs_hist2_pri & 0x000000ff;
+	g_pri[4] = (unsigned int)((dfs_hist1_pri & 0xff000000) >> 24);
+	g_pri[5] = (unsigned int)((dfs_hist1_pri & 0x00ff0000) >> 16);
+
+	dfs->pri_cond1 = 0;
+	dfs->pri_cond2 = 0;
+	dfs->pri_cond3 = 0;
+	dfs->pri_cond4 = 0;
+	dfs->pri_cond5 = 0;
+	dfs->pw_cond1 = 0;
+	dfs->pw_cond2 = 0;
+	dfs->pw_cond3 = 0;
+	dfs->pri_type3_4_cond1 = 0;	/*@for ETSI*/
+	dfs->pri_type3_4_cond2 = 0;	/*@for ETSI*/
+	dfs->pw_long_cond1 = 0;		/*@for long radar*/
+	dfs->pw_long_cond2 = 0;		/*@for long radar*/
+	dfs->pri_long_cond1 = 0;	/*@for long radar*/
+	dfs->pw_flag = 0;
+	dfs->pri_flag = 0;
+	dfs->pri_type3_4_flag = 0;	/*@for ETSI*/
+	dfs->long_radar_flag = 0;
+	dfs->pw_std = 0;	/*The std(var) of reasonable num of pw group*/
+	dfs->pri_std = 0;	/*The std(var) of reasonable num of pri group*/
+
+	for (i = 0; i < 6; i++) {
+		dfs->pw_hold_sum[i] = 0;
+		dfs->pri_hold_sum[i] = 0;
+		dfs->pw_long_hold_sum[i] = 0;
+		dfs->pri_long_hold_sum[i] = 0;
+	}
+
+	if (dfs->idle_mode == 1)
+		pri_th = dfs->pri_hist_th;
+	else
+		pri_th = dfs->pri_hist_th - 1;
+
+	for (i = 0; i < 6; i++) {
+		dfs->pw_hold[dfs->hist_idx][i] = (u8)g_pw[i];
+		dfs->pri_hold[dfs->hist_idx][i] = (u8)g_pri[i];
+		/*@collect whole histogram report may take some time
+		 *so we add the counter of 2 time slots in FCC and ETSI
+		 */
+		if (region_domain == 1 || region_domain == 3) {
+			dfs->pw_hold_sum[i] = dfs->pw_hold_sum[i] +
+				dfs->pw_hold[(dfs->hist_idx + 1) % 3][i] +
+				dfs->pw_hold[(dfs->hist_idx + 2) % 3][i];
+			dfs->pri_hold_sum[i] = dfs->pri_hold_sum[i] +
+				dfs->pri_hold[(dfs->hist_idx + 1) % 3][i] +
+				dfs->pri_hold[(dfs->hist_idx + 2) % 3][i];
+		} else{
+		/*@collect whole histogram report may take some time,
+		 *so we add the counter of 3 time slots in MKK or else
+		 */
+			dfs->pw_hold_sum[i] = dfs->pw_hold_sum[i] +
+				dfs->pw_hold[(dfs->hist_idx + 1) % 4][i] +
+				dfs->pw_hold[(dfs->hist_idx + 2) % 4][i] +
+				dfs->pw_hold[(dfs->hist_idx + 3) % 4][i];
+			dfs->pri_hold_sum[i] = dfs->pri_hold_sum[i] +
+				dfs->pri_hold[(dfs->hist_idx + 1) % 4][i] +
+				dfs->pri_hold[(dfs->hist_idx + 2) % 4][i] +
+				dfs->pri_hold[(dfs->hist_idx + 3) % 4][i];
+		}
+	}
+	/*@For long radar type*/
+	for (i = 0; i < 6; i++) {
+		dfs->pw_long_hold[dfs->hist_long_idx][i] = (u8)g_pw[i];
+		dfs->pri_long_hold[dfs->hist_long_idx][i] = (u8)g_pri[i];
+		/*@collect whole histogram report may take some time,
+		 *so we add the counter of 299 time slots for long radar
+		 */
+		for (j = 1; j < 300; j++) {
+		dfs->pw_long_hold_sum[i] = dfs->pw_long_hold_sum[i] +
+			dfs->pw_long_hold[(dfs->hist_long_idx + j) % 300][i];
+		dfs->pri_long_hold_sum[i] = dfs->pri_long_hold_sum[i] +
+			dfs->pri_long_hold[(dfs->hist_long_idx + j) % 300][i];
+		}
+	}
+	dfs->hist_idx++;
+	dfs->hist_long_idx++;
+	if (dfs->hist_long_idx == 300)
+		dfs->hist_long_idx = 0;
+	if (region_domain == 1 || region_domain == 3) {
+		if (dfs->hist_idx == 3)
+			dfs->hist_idx = 0;
+	} else if (dfs->hist_idx == 4) {
+		dfs->hist_idx = 0;
+	}
+
+	max_pri_cnt = 0;
+	max_pri_idx = 0;
+	max_pw_cnt = 0;
+	max_pw_idx = 0;
+	max_pri_cnt_th = dfs->pri_sum_g1_th;
+	max_pri_cnt_fcc_g1_th = dfs->pri_sum_g1_fcc_th;
+	max_pri_cnt_fcc_g3_th = dfs->pri_sum_g3_fcc_th;
+	safe_pri_pw_diff_th = dfs->pri_pw_diff_th;
+	safe_pri_pw_diff_fcc_th = dfs->pri_pw_diff_fcc_th;
+	safe_pri_pw_diff_fcc_idle_th = dfs->pri_pw_diff_fcc_idle_th;
+	safe_pri_pw_diff_w53_th = dfs->pri_pw_diff_w53_th;
+
+	/*@g1 to g4 is the reseasonable range of pri and pw*/
+	for (i = 1; i <= 4; i++) {
+		if (dfs->pri_hold_sum[i] > max_pri_cnt) {
+			max_pri_cnt = dfs->pri_hold_sum[i];
+			max_pri_idx = i;
+		}
+		if (dfs->pw_hold_sum[i] > max_pw_cnt) {
+			max_pw_cnt = dfs->pw_hold_sum[i];
+			max_pw_idx = i;
+		}
+		if (dfs->pri_hold_sum[i] >= pri_th)
+			dfs->pri_cond1 = 1;
+	}
+
+	pri_sum_g0g5 = dfs->pri_hold_sum[0];
+	if (pri_sum_g0g5 == 0)
+		pri_sum_g0g5 = 1;
+	pri_sum_g1g2g3g4 = dfs->pri_hold_sum[1] + dfs->pri_hold_sum[2]
+			 + dfs->pri_hold_sum[3] + dfs->pri_hold_sum[4];
+
+	/*pw will reduce because of dc, so we do not treat g0 as illegal group*/
+	pw_sum_g0g5 = dfs->pw_hold_sum[5];
+	if (pw_sum_g0g5 == 0)
+		pw_sum_g0g5 = 1;
+	pw_sum_g1g2g3g4 = dfs->pw_hold_sum[1] + dfs->pw_hold_sum[2] +
+				dfs->pw_hold_sum[3] + dfs->pw_hold_sum[4];
+
+	/*@Calculate the variation from g1 to g4*/
+	for (i = 1; i < 5; i++) {
+		/*Sum of square*/
+		pw_sum_ss_g1g2g3g4 = pw_sum_ss_g1g2g3g4 +
+		(dfs->pw_hold_sum[i] - (pw_sum_g1g2g3g4 / 4)) *
+		(dfs->pw_hold_sum[i] - (pw_sum_g1g2g3g4 / 4));
+		pri_sum_ss_g1g2g3g4 = pri_sum_ss_g1g2g3g4 +
+		(dfs->pri_hold_sum[i] - (pri_sum_g1g2g3g4 / 4)) *
+		(dfs->pri_hold_sum[i] - (pri_sum_g1g2g3g4 / 4));
+	}
+	/*The value may less than the normal variance,
+	 *since the variable type is int (not float)
+	 */
+		dfs->pw_std = (u16)(pw_sum_ss_g1g2g3g4 / 4);
+		dfs->pri_std = (u16)(pri_sum_ss_g1g2g3g4 / 4);
+
+	if (region_domain == 1) {
+		dfs->pri_type3_4_flag = 1;	/*@ETSI flag*/
+
+		/*PRI judgment conditions for short radar type*/
+		/*ratio of reasonable group and illegal group &&
+		 *pri variation of short radar should be large (=6)
+		 */
+		if (max_pri_idx != 4 && dfs->pri_hold_sum[5] > 0)
+			dfs->pri_cond2 = 0;
+		else
+			dfs->pri_cond2 = 1;
+
+		/*reasonable group shouldn't large*/
+		if ((pri_sum_g0g5 + pri_sum_g1g2g3g4) / pri_sum_g0g5 > 2 &&
+		    pri_sum_g1g2g3g4 <= dfs->pri_sum_safe_fcc_th)
+			dfs->pri_cond3 = 1;
+
+		/*@Cancel the condition that the abs between pri and pw*/
+		if (dfs->pri_std >= dfs->pri_std_th)
+			dfs->pri_cond4 = 1;
+		else if (max_pri_idx == 1 &&
+			 max_pri_cnt >= max_pri_cnt_fcc_g1_th)
+			dfs->pri_cond4 = 1;
+
+		/*we set threshold = 7 (>4) for distinguishing type 3,4 (g3)*/
+		if (max_pri_idx == 1 && dfs->pri_hold_sum[3] +
+		    dfs->pri_hold_sum[4] + dfs->pri_hold_sum[5] > 0)
+			dfs->pri_cond5 = 0;
+		else
+			dfs->pri_cond5 = 1;
+
+		if (dfs->pri_cond1 && dfs->pri_cond2 && dfs->pri_cond3 &&
+		    dfs->pri_cond4 && dfs->pri_cond5)
+			dfs->pri_flag = 1;
+
+		/* PW judgment conditions for short radar type */
+		/*ratio of reasonable and illegal group && g5 should be zero*/
+		if (((pw_sum_g0g5 + pw_sum_g1g2g3g4) / pw_sum_g0g5 > 2) &&
+		    (dfs->pw_hold_sum[5] <= 1))
+			dfs->pw_cond1 = 1;
+		/*unreasonable group*/
+		if (dfs->pw_hold_sum[4] == 0 && dfs->pw_hold_sum[5] == 0)
+			dfs->pw_cond2 = 1;
+		/*pw's std (short radar) should be large(=7)*/
+		if (dfs->pw_std >= dfs->pw_std_th)
+			dfs->pw_cond3 = 1;
+		if (dfs->pw_cond1 && dfs->pw_cond2 && dfs->pw_cond3)
+			dfs->pw_flag = 1;
+
+		/* @Judgment conditions of long radar type */
+		if (band_width == CHANNEL_WIDTH_20) {
+			if (dfs->pw_long_hold_sum[4] >=
+			    dfs->pw_long_lower_20m_th)
+				dfs->pw_long_cond1 = 1;
+		} else{
+			if (dfs->pw_long_hold_sum[4] >= dfs->pw_long_lower_th)
+				dfs->pw_long_cond1 = 1;
+		}
+		/* @Disable the condition that dfs->pw_long_hold_sum[1] */
+		if (dfs->pw_long_hold_sum[2] + dfs->pw_long_hold_sum[3] +
+		    dfs->pw_long_hold_sum[4] <= dfs->pw_long_sum_upper_th &&
+		    dfs->pw_long_hold_sum[2] <= dfs->pw_long_hold_sum[4] &&
+		    dfs->pw_long_hold_sum[3] <= dfs->pw_long_hold_sum[4])
+			dfs->pw_long_cond2 = 1;
+		/*@g4 should be large for long radar*/
+		if (dfs->pri_long_hold_sum[4] <= dfs->pri_long_upper_th)
+			dfs->pri_long_cond1 = 1;
+		if (dfs->pw_long_cond1 && dfs->pw_long_cond2 &&
+		    dfs->pri_long_cond1)
+			dfs->long_radar_flag = 1;
+	} else if (region_domain == 2) {
+		dfs->pri_type3_4_flag = 1;	/*@ETSI flag*/
+
+		/*PRI judgment conditions for short radar type*/
+		if ((pri_sum_g0g5 + pri_sum_g1g2g3g4) / pri_sum_g0g5 > 2)
+			dfs->pri_cond2 = 1;
+
+		/*reasonable group shouldn't too large*/
+		if (pri_sum_g1g2g3g4 <= dfs->pri_sum_safe_fcc_th)
+			dfs->pri_cond3 = 1;
+
+		/*the difference between pri and pw for idle mode (thr=2)*/
+		if (dfs->idle_mode == 1) {
+			if (abs(pw_sum_g1g2g3g4 - pri_sum_g1g2g3g4) <=
+			    safe_pri_pw_diff_fcc_idle_th)
+				dfs->pri_cond4 = 1;
+		} else{
+			if ((c_channel >= 52) && (c_channel <= 64)) {
+		/*the difference between pri and pw for w53 TP mode (thr=15)*/
+			if (abs(pw_sum_g1g2g3g4 - pri_sum_g1g2g3g4) <=
+			    safe_pri_pw_diff_w53_th)
+				dfs->pri_cond4 = 1;
+			} else {
+		/*the difference between pri and pw for TP mode (thr=8)*/
+				if (abs(pw_sum_g1g2g3g4 - pri_sum_g1g2g3g4) <=
+				    safe_pri_pw_diff_fcc_th)
+					dfs->pri_cond4 = 1;
+			}
+		}
+
+		if (dfs->idle_mode == 1) {
+			if (dfs->pri_std >= dfs->pri_std_idle_th) {
+				if (max_pw_idx == 3 &&
+				    pri_sum_g1g2g3g4 <= dfs->pri_sum_type4_th){
+		/*To distinguish between type 4 radar and false detection*/
+					dfs->pri_cond5 = 1;
+				} else if (max_pw_idx == 1 &&
+					   pri_sum_g1g2g3g4 >=
+					   dfs->pri_sum_type6_th) {
+		/*To distinguish between type 6 radar and false detection*/
+					dfs->pri_cond5 = 1;
+				} else {
+		/*pri variation of short radar should be large (idle mode)*/
+					dfs->pri_cond5 = 1;
+				}
+			}
+		} else {
+		/*pri variation of short radar should be large (TP mode)*/
+			if (dfs->pri_std >= dfs->pri_std_th)
+				dfs->pri_cond5 = 1;
+		}
+
+		if (dfs->pri_cond1 && dfs->pri_cond2 && dfs->pri_cond3 &&
+		    dfs->pri_cond4 && dfs->pri_cond5)
+			dfs->pri_flag = 1;
+
+		/* PW judgment conditions for short radar type */
+		if (((pw_sum_g0g5 + pw_sum_g1g2g3g4) / pw_sum_g0g5 > 2) &&
+		    (dfs->pw_hold_sum[5] <= 1))
+		/*ratio of reasonable and illegal group && g5 should be zero*/
+			dfs->pw_cond1 = 1;
+
+		if ((c_channel >= 52) && (c_channel <= 64))
+			dfs->pw_cond2 = 1;
+		/*unreasonable group shouldn't too large*/
+		else if (dfs->pw_hold_sum[0] <= dfs->pw_g0_th)
+			dfs->pw_cond2 = 1;
+
+		if (dfs->idle_mode == 1) {
+		/*pw variation of short radar should be large (idle mode)*/
+			if (dfs->pw_std >= dfs->pw_std_idle_th)
+				dfs->pw_cond3 = 1;
+		} else {
+		/*pw variation of short radar should be large (TP mode)*/
+			if (dfs->pw_std >= dfs->pw_std_th)
+				dfs->pw_cond3 = 1;
+		}
+		if (dfs->pw_cond1 && dfs->pw_cond2 && dfs->pw_cond3)
+			dfs->pw_flag = 1;
+
+		/* @Judgment conditions of long radar type */
+		if (band_width == CHANNEL_WIDTH_20) {
+			if (dfs->pw_long_hold_sum[4] >=
+			    dfs->pw_long_lower_20m_th)
+				dfs->pw_long_cond1 = 1;
+		} else{
+			if (dfs->pw_long_hold_sum[4] >= dfs->pw_long_lower_th)
+				dfs->pw_long_cond1 = 1;
+		}
+		if (dfs->pw_long_hold_sum[1] + dfs->pw_long_hold_sum[2] +
+		    dfs->pw_long_hold_sum[3] + dfs->pw_long_hold_sum[4]
+		    <= dfs->pw_long_sum_upper_th)
+			dfs->pw_long_cond2 = 1;
+		/*@g4 should be large for long radar*/
+		if (dfs->pri_long_hold_sum[4] <= dfs->pri_long_upper_th)
+			dfs->pri_long_cond1 = 1;
+		if (dfs->pw_long_cond1 &&
+		    dfs->pw_long_cond2 && dfs->pri_long_cond1)
+			dfs->long_radar_flag = 1;
+	} else if (region_domain == 3) {
+		/*ratio of reasonable group and illegal group */
+		if ((pri_sum_g0g5 + pri_sum_g1g2g3g4) / pri_sum_g0g5 > 2)
+			dfs->pri_cond2 = 1;
+
+		if (pri_sum_g1g2g3g4 <= dfs->pri_sum_safe_th)
+			dfs->pri_cond3 = 1;
+
+		/*@Cancel the condition that the abs between pri and pw*/
+			dfs->pri_cond4 = 1;
+
+		if (dfs->pri_hold_sum[5] <= dfs->pri_sum_g5_th)
+			dfs->pri_cond5 = 1;
+
+		if (band_width == CHANNEL_WIDTH_40) {
+			if (max_pw_idx == 4) {
+				if (max_pw_cnt >= dfs->type4_pw_max_cnt &&
+				    pri_sum_g1g2g3g4 >=
+				    dfs->type4_safe_pri_sum_th) {
+					dfs->pri_cond1 = 1;
+					dfs->pri_cond4 = 1;
+					dfs->pri_type3_4_cond1 = 1;
+				}
+			}
+		}
+
+		if (dfs->pri_cond1 && dfs->pri_cond2 &&
+		    dfs->pri_cond3 && dfs->pri_cond4 && dfs->pri_cond5)
+			dfs->pri_flag = 1;
+
+		if (((pw_sum_g0g5 + pw_sum_g1g2g3g4) / pw_sum_g0g5 > 2) &&
+		    (dfs->pw_hold_sum[5] == 0))
+			dfs->pw_flag = 1;
+
+		/*@max num pri group is g1 means radar type3 or type4*/
+		if (max_pri_idx == 1) {
+			if (max_pri_cnt >= max_pri_cnt_th)
+				dfs->pri_type3_4_cond1 = 1;
+			if (dfs->pri_hold_sum[4] <=
+			    dfs->pri_sum_g5_under_g1_th &&
+			    dfs->pri_hold_sum[5] <= dfs->pri_sum_g5_under_g1_th)
+				dfs->pri_type3_4_cond2 = 1;
+		} else {
+			dfs->pri_type3_4_cond1 = 1;
+			dfs->pri_type3_4_cond2 = 1;
+		}
+		if (dfs->pri_type3_4_cond1 && dfs->pri_type3_4_cond2)
+			dfs->pri_type3_4_flag = 1;
+	} else {
+	}
+
+	if (dfs->print_hist_rpt) {
+		dfs_pw_thd1 = (u8)odm_get_bb_reg(dm, 0x19e4, 0xff000000);
+		dfs_pw_thd2 = (u8)odm_get_bb_reg(dm, 0x19e8, 0x000000ff);
+		dfs_pw_thd3 = (u8)odm_get_bb_reg(dm, 0x19e8, 0x0000ff00);
+		dfs_pw_thd4 = (u8)odm_get_bb_reg(dm, 0x19e8, 0x00ff0000);
+		dfs_pw_thd5 = (u8)odm_get_bb_reg(dm, 0x19e8, 0xff000000);
+
+		dfs_pri_thd1 = (u8)odm_get_bb_reg(dm, 0x19b8, 0x7F80);
+		dfs_pri_thd2 = (u8)odm_get_bb_reg(dm, 0x19ec, 0x000000ff);
+		dfs_pri_thd3 = (u8)odm_get_bb_reg(dm, 0x19ec, 0x0000ff00);
+		dfs_pri_thd4 = (u8)odm_get_bb_reg(dm, 0x19ec, 0x00ff0000);
+		dfs_pri_thd5 = (u8)odm_get_bb_reg(dm, 0x19ec, 0xff000000);
+
+		PHYDM_DBG(dm, DBG_DFS, "peak index hist\n");
+		PHYDM_DBG(dm, DBG_DFS, "dfs_hist_peak_index=%x %x\n",
+			  dfs_hist1_peak_index, dfs_hist2_peak_index);
+		PHYDM_DBG(dm, DBG_DFS, "g_peak_index_hist = ");
+		for (i = 0; i < 16; i++)
+			PHYDM_DBG(dm, DBG_DFS, " %x", g_peakindex[i]);
+		PHYDM_DBG(dm, DBG_DFS, "\ndfs_pw_thd=%d %d %d %d %d\n",
+			  dfs_pw_thd1, dfs_pw_thd2, dfs_pw_thd3,
+			  dfs_pw_thd4, dfs_pw_thd5);
+		PHYDM_DBG(dm, DBG_DFS, "-----pulse width hist-----\n");
+		PHYDM_DBG(dm, DBG_DFS, "dfs_hist_pw=%x %x\n",
+			  dfs_hist1_pw, dfs_hist2_pw);
+		PHYDM_DBG(dm, DBG_DFS, "g_pw_hist = %x %x %x %x %x %x\n",
+			  g_pw[0], g_pw[1], g_pw[2], g_pw[3],
+			  g_pw[4], g_pw[5]);
+		PHYDM_DBG(dm, DBG_DFS, "dfs_pri_thd=%d %d %d %d %d\n",
+			  dfs_pri_thd1, dfs_pri_thd2, dfs_pri_thd3,
+			  dfs_pri_thd4, dfs_pri_thd5);
+		PHYDM_DBG(dm, DBG_DFS, "-----pulse interval hist-----\n");
+		PHYDM_DBG(dm, DBG_DFS, "dfs_hist_pri=%x %x\n",
+			  dfs_hist1_pri, dfs_hist2_pri);
+		PHYDM_DBG(dm, DBG_DFS,
+			  "g_pri_hist = %x %x %x %x %x %x, pw_flag = %d, pri_flag = %d\n",
+			  g_pri[0], g_pri[1], g_pri[2], g_pri[3], g_pri[4],
+			  g_pri[5], dfs->pw_flag, dfs->pri_flag);
+		if (region_domain == 1 || region_domain == 3) {
+			PHYDM_DBG(dm, DBG_DFS, "hist_idx= %d\n",
+				  (dfs->hist_idx + 2) % 3);
+		} else {
+			PHYDM_DBG(dm, DBG_DFS, "hist_idx= %d\n",
+				  (dfs->hist_idx + 3) % 4);
+		}
+		PHYDM_DBG(dm, DBG_DFS, "hist_long_idx= %d\n",
+			  (dfs->hist_long_idx + 299) % 300);
+		PHYDM_DBG(dm, DBG_DFS,
+			  "pw_sum_g0g5 = %d, pw_sum_g1g2g3g4 = %d\n",
+			  pw_sum_g0g5, pw_sum_g1g2g3g4);
+		PHYDM_DBG(dm, DBG_DFS,
+			  "pri_sum_g0g5 = %d, pri_sum_g1g2g3g4 = %d\n",
+			  pri_sum_g0g5, pri_sum_g1g2g3g4);
+		PHYDM_DBG(dm, DBG_DFS, "pw_hold_sum = %d %d %d %d %d %d\n",
+			  dfs->pw_hold_sum[0], dfs->pw_hold_sum[1],
+			  dfs->pw_hold_sum[2], dfs->pw_hold_sum[3],
+			  dfs->pw_hold_sum[4], dfs->pw_hold_sum[5]);
+		PHYDM_DBG(dm, DBG_DFS, "pri_hold_sum = %d %d %d %d %d %d\n",
+			  dfs->pri_hold_sum[0], dfs->pri_hold_sum[1],
+			  dfs->pri_hold_sum[2], dfs->pri_hold_sum[3],
+			  dfs->pri_hold_sum[4], dfs->pri_hold_sum[5]);
+		PHYDM_DBG(dm, DBG_DFS, "pw_long_hold_sum = %d %d %d %d %d %d\n",
+			  dfs->pw_long_hold_sum[0], dfs->pw_long_hold_sum[1],
+			  dfs->pw_long_hold_sum[2], dfs->pw_long_hold_sum[3],
+			  dfs->pw_long_hold_sum[4], dfs->pw_long_hold_sum[5]);
+		PHYDM_DBG(dm, DBG_DFS,
+			  "pri_long_hold_sum = %d %d %d %d %d %d\n",
+			  dfs->pri_long_hold_sum[0], dfs->pri_long_hold_sum[1],
+			  dfs->pri_long_hold_sum[2], dfs->pri_long_hold_sum[3],
+			  dfs->pri_long_hold_sum[4], dfs->pri_long_hold_sum[5]);
+		PHYDM_DBG(dm, DBG_DFS, "idle_mode = %d\n", dfs->idle_mode);
+		PHYDM_DBG(dm, DBG_DFS, "pw_standard = %d\n", dfs->pw_std);
+		PHYDM_DBG(dm, DBG_DFS, "pri_standard = %d\n", dfs->pri_std);
+		for (j = 0; j < 4; j++) {
+			for (i = 0; i < 6; i++) {
+				PHYDM_DBG(dm, DBG_DFS, "pri_hold = %d ",
+					  dfs->pri_hold[j][i]);
+			}
+			PHYDM_DBG(dm, DBG_DFS, "\n");
+		}
+		PHYDM_DBG(dm, DBG_DFS, "\n");
+		PHYDM_DBG(dm, DBG_DFS,
+			  "pri_cond1 = %d, pri_cond2 = %d, pri_cond3 = %d, pri_cond4 = %d, pri_cond5 = %d\n",
+			  dfs->pri_cond1, dfs->pri_cond2, dfs->pri_cond3,
+			  dfs->pri_cond4, dfs->pri_cond5);
+		PHYDM_DBG(dm, DBG_DFS,
+			  "bandwidth = %d, pri_th = %d, max_pri_cnt_th = %d, safe_pri_pw_diff_th = %d\n",
+			  band_width, pri_th, max_pri_cnt_th,
+			  safe_pri_pw_diff_th);
+	}
+}
+
+boolean phydm_dfs_hist_log(void *dm_void, u8 index)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct _DFS_STATISTICS *dfs = &dm->dfs;
+	u8 i = 0, j = 0;
+	boolean hist_radar_detected = 0;
+
+	if (dfs->pulse_type_hist[index] == 0) {
+		dfs->radar_type = 0;
+		if (dfs->pw_flag && dfs->pri_flag &&
+		    dfs->pri_type3_4_flag) {
+			hist_radar_detected = 1;
+			PHYDM_DBG(dm, DBG_DFS,
+				  "Detected type %d radar signal!\n",
+				  dfs->radar_type);
+			if (dfs->det_print2) {
+				PHYDM_DBG(dm, DBG_DFS,
+					  "hist_idx= %d\n",
+					  (dfs->hist_idx + 3) % 4);
+				for (j = 0; j < 4; j++) {
+				for (i = 0; i < 6; i++) {
+					PHYDM_DBG(dm, DBG_DFS,
+						  "pri_hold = %d ",
+						  dfs->pri_hold[j][i]);
+				}
+				PHYDM_DBG(dm, DBG_DFS, "\n");
+				}
+				PHYDM_DBG(dm, DBG_DFS, "\n");
+				for (j = 0; j < 4; j++) {
+				for (i = 0; i < 6; i++) {
+					PHYDM_DBG(dm, DBG_DFS, "pw_hold = %d ",
+						  dfs->pw_hold[j][i]);
+				}
+					PHYDM_DBG(dm, DBG_DFS, "\n");
+				}
+				PHYDM_DBG(dm, DBG_DFS, "\n");
+				PHYDM_DBG(dm, DBG_DFS, "idle_mode = %d\n",
+					  dfs->idle_mode);
+				PHYDM_DBG(dm, DBG_DFS,
+					  "pw_hold_sum = %d %d %d %d %d %d\n",
+					  dfs->pw_hold_sum[0],
+					  dfs->pw_hold_sum[1],
+					  dfs->pw_hold_sum[2],
+					  dfs->pw_hold_sum[3],
+					  dfs->pw_hold_sum[4],
+					  dfs->pw_hold_sum[5]);
+				PHYDM_DBG(dm, DBG_DFS,
+					  "pri_hold_sum = %d %d %d %d %d %d\n",
+					  dfs->pri_hold_sum[0],
+					  dfs->pri_hold_sum[1],
+					  dfs->pri_hold_sum[2],
+					  dfs->pri_hold_sum[3],
+					  dfs->pri_hold_sum[4],
+					  dfs->pri_hold_sum[5]);
+			}
+		} else {
+		if (dfs->det_print2) {
+			if (dfs->pulse_flag_hist[index] &&
+			    dfs->pri_flag == 0) {
+				PHYDM_DBG(dm, DBG_DFS, "pri_variation = %d\n",
+					  dfs->pri_std);
+				PHYDM_DBG(dm, DBG_DFS,
+					  "PRI criterion is not satisfied!\n");
+				if (dfs->pri_cond1 == 0)
+					PHYDM_DBG(dm, DBG_DFS,
+						  "pri_cond1 is not satisfied!\n");
+				if (dfs->pri_cond2 == 0)
+					PHYDM_DBG(dm, DBG_DFS,
+						  "pri_cond2 is not satisfied!\n");
+				if (dfs->pri_cond3 == 0)
+					PHYDM_DBG(dm, DBG_DFS,
+						  "pri_cond3 is not satisfied!\n");
+				if (dfs->pri_cond4 == 0)
+					PHYDM_DBG(dm, DBG_DFS,
+						  "pri_cond4 is not satisfied!\n");
+				if (dfs->pri_cond5 == 0)
+					PHYDM_DBG(dm, DBG_DFS,
+						  "pri_cond5 is not satisfied!\n");
+			}
+			if (dfs->pulse_flag_hist[index] &&
+			    dfs->pw_flag == 0) {
+				PHYDM_DBG(dm, DBG_DFS, "pw_variation = %d\n",
+					  dfs->pw_std);
+				PHYDM_DBG(dm, DBG_DFS,
+					  "PW criterion is not satisfied!\n");
+				if (dfs->pw_cond1 == 0)
+					PHYDM_DBG(dm, DBG_DFS,
+						  "pw_cond1 is not satisfied!\n");
+				if (dfs->pw_cond2 == 0)
+					PHYDM_DBG(dm, DBG_DFS,
+						  "pw_cond2 is not satisfied!\n");
+				if (dfs->pw_cond3 == 0)
+					PHYDM_DBG(dm, DBG_DFS,
+						  "pw_cond3 is not satisfied!\n");
+			}
+			if (dfs->pulse_flag_hist[index] &&
+			    (dfs->pri_type3_4_flag == 0)) {
+				PHYDM_DBG(dm, DBG_DFS,
+					  "pri_type3_4 criterion is not satisfied!\n");
+				if (dfs->pri_type3_4_cond1 == 0)
+					PHYDM_DBG(dm, DBG_DFS,
+						  "pri_type3_4_cond1 is not satisfied!\n");
+				if (dfs->pri_type3_4_cond2 == 0)
+					PHYDM_DBG(dm, DBG_DFS,
+						  "pri_type3_4_cond2 is not satisfied!\n");
+			}
+			PHYDM_DBG(dm, DBG_DFS, "hist_idx= %d\n",
+				  (dfs->hist_idx + 3) % 4);
+			for (j = 0; j < 4; j++) {
+				for (i = 0; i < 6; i++) {
+					PHYDM_DBG(dm, DBG_DFS,
+						  "pri_hold = %d ",
+						  dfs->pri_hold[j][i]);
+				}
+				PHYDM_DBG(dm, DBG_DFS, "\n");
+			}
+			PHYDM_DBG(dm, DBG_DFS, "\n");
+			for (j = 0; j < 4; j++) {
+				for (i = 0; i < 6; i++)
+					PHYDM_DBG(dm, DBG_DFS,
+						  "pw_hold = %d ",
+						  dfs->pw_hold[j][i]);
+				PHYDM_DBG(dm, DBG_DFS, "\n");
+			}
+			PHYDM_DBG(dm, DBG_DFS, "\n");
+			PHYDM_DBG(dm, DBG_DFS, "idle_mode = %d\n",
+				  dfs->idle_mode);
+			PHYDM_DBG(dm, DBG_DFS,
+				  "pw_hold_sum = %d %d %d %d %d %d\n",
+				  dfs->pw_hold_sum[0], dfs->pw_hold_sum[1],
+				  dfs->pw_hold_sum[2], dfs->pw_hold_sum[3],
+				  dfs->pw_hold_sum[4], dfs->pw_hold_sum[5]);
+			PHYDM_DBG(dm, DBG_DFS,
+				  "pri_hold_sum = %d %d %d %d %d %d\n",
+				  dfs->pri_hold_sum[0], dfs->pri_hold_sum[1],
+				  dfs->pri_hold_sum[2], dfs->pri_hold_sum[3],
+				  dfs->pri_hold_sum[4], dfs->pri_hold_sum[5]);
+		}
+		}
+	} else {
+		dfs->radar_type = 1;
+		if (dfs->det_print2) {
+			PHYDM_DBG(dm, DBG_DFS, "\n");
+			PHYDM_DBG(dm, DBG_DFS, "idle_mode = %d\n",
+				  dfs->idle_mode);
+			PHYDM_DBG(dm, DBG_DFS,
+				  "long_radar_pw_hold_sum = %d %d %d %d %d %d\n",
+				  dfs->pw_long_hold_sum[0],
+				  dfs->pw_long_hold_sum[1],
+				  dfs->pw_long_hold_sum[2],
+				  dfs->pw_long_hold_sum[3],
+				  dfs->pw_long_hold_sum[4],
+				  dfs->pw_long_hold_sum[5]);
+			PHYDM_DBG(dm, DBG_DFS,
+				  "long_radar_pri_hold_sum = %d %d %d %d %d %d\n",
+				  dfs->pri_long_hold_sum[0],
+				  dfs->pri_long_hold_sum[1],
+				  dfs->pri_long_hold_sum[2],
+				  dfs->pri_long_hold_sum[3],
+				  dfs->pri_long_hold_sum[4],
+				  dfs->pri_long_hold_sum[5]);
+		}
+		/* @Long radar should satisfy three conditions */
+		if (dfs->long_radar_flag == 1) {
+			hist_radar_detected = 1;
+			PHYDM_DBG(dm, DBG_DFS,
+				  "Detected type %d radar signal!\n",
+				  dfs->radar_type);
+		} else {
+			if (dfs->det_print2) {
+				if (dfs->pw_long_cond1 == 0)
+					PHYDM_DBG(dm, DBG_DFS,
+						  "--pw_long_cond1 is not satisfied!--\n");
+				if (dfs->pw_long_cond2 == 0)
+					PHYDM_DBG(dm, DBG_DFS,
+						  "--pw_long_cond2 is not satisfied!--\n");
+				if (dfs->pri_long_cond1 == 0)
+					PHYDM_DBG(dm, DBG_DFS,
+						  "--pri_long_cond1 is not satisfied!--\n");
+			}
+		}
+	}
+	return hist_radar_detected;
+}
+
+boolean phydm_radar_detect(void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct _DFS_STATISTICS *dfs = &dm->dfs;
+	boolean enable_DFS = false;
+	boolean radar_detected = false;
+
+	dfs->igi_cur = (u8)odm_get_bb_reg(dm, R_0xc50, 0x0000007f);
+
+	dfs->st_l2h_cur = (u8)odm_get_bb_reg(dm, R_0x91c, 0x000000ff);
+
+	/* @dynamic pwdb calibration */
+	if (dfs->igi_pre != dfs->igi_cur) {
+		dfs->pwdb_th_cur = ((int)dfs->st_l2h_cur - (int)dfs->igi_cur)
+				    / 2 + dfs->pwdb_scalar_factor;
+
+		/* @limit the pwdb value to absolute lower bound 0xa */
+		dfs->pwdb_th_cur = MAX_2(dfs->pwdb_th_cur, (int)dfs->pwdb_th);
+		/* @limit the pwdb value to absolute upper bound 0x1f */
+		dfs->pwdb_th_cur = MIN_2(dfs->pwdb_th_cur, 0x1f);
+		odm_set_bb_reg(dm, R_0x918, 0x00001f00, dfs->pwdb_th_cur);
+	}
+
+	dfs->igi_pre = dfs->igi_cur;
+
+	phydm_dfs_dynamic_setting(dm);
+	phydm_dfs_histogram_radar_distinguish(dm);
+	radar_detected = phydm_radar_detect_dm_check(dm);
+
+	if (odm_get_bb_reg(dm, R_0x924, BIT(15)))
+		enable_DFS = true;
+
+	if (enable_DFS && radar_detected) {
+		PHYDM_DBG(dm, DBG_DFS,
+			  "Radar detect: enable_DFS:%d, radar_detected:%d\n",
+			  enable_DFS, radar_detected);
+		phydm_radar_detect_reset(dm);
+		if (dfs->dbg_mode == 1) {
+			PHYDM_DBG(dm, DBG_DFS,
+				  "Radar is detected in DFS dbg mode.\n");
+			radar_detected = 0;
+		}
+	}
+
+	return enable_DFS && radar_detected;
+}
+
+void phydm_dfs_debug(void *dm_void, char input[][16], u32 *_used,
+		     char *output, u32 *_out_len)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct _DFS_STATISTICS *dfs = &dm->dfs;
+	u32 used = *_used;
+	u32 out_len = *_out_len;
+	u32 argv[10] = {0};
+	u8 i, input_idx = 0;
+
+	for (i = 0; i < 6; i++) {
+		if (input[i + 1]) {
+			PHYDM_SSCANF(input[i + 1], DCMD_HEX, &argv[i]);
+			input_idx++;
+		}
+	}
+
+	if (input_idx == 0)
+		return;
+
+	dfs->dbg_mode = (boolean)argv[0];
+	dfs->force_TP_mode = (boolean)argv[1];
+	dfs->det_print = (boolean)argv[2];
+	dfs->det_print2 = (boolean)argv[3];
+	dfs->print_hist_rpt = (boolean)argv[4];
+	dfs->hist_cond_on = (boolean)argv[5];
+
+	PDM_SNPF(out_len, used, output + used, out_len - used,
+		 "dbg_mode: %d, force_TP_mode: %d, det_print: %d,det_print2: %d, print_hist_rpt: %d, hist_cond_on: %d\n",
+		 dfs->dbg_mode, dfs->force_TP_mode, dfs->det_print,
+		 dfs->det_print2, dfs->print_hist_rpt, dfs->hist_cond_on);
+
+	/*switch (argv[0]) {
+	case 1:
+#if defined(CONFIG_PHYDM_DFS_MASTER)
+		 set dbg parameters for radar detection instead of the default value
+		if (argv[1] == 1) {
+			dm->radar_detect_reg_918 = argv[2];
+			dm->radar_detect_reg_91c = argv[3];
+			dm->radar_detect_reg_920 = argv[4];
+			dm->radar_detect_reg_924 = argv[5];
+			dm->radar_detect_dbg_parm_en = 1;
+
+			PDM_SNPF((output + used, out_len - used, "Radar detection with dbg parameter\n"));
+			PDM_SNPF((output + used, out_len - used, "reg918:0x%08X\n", dm->radar_detect_reg_918));
+			PDM_SNPF((output + used, out_len - used, "reg91c:0x%08X\n", dm->radar_detect_reg_91c));
+			PDM_SNPF((output + used, out_len - used, "reg920:0x%08X\n", dm->radar_detect_reg_920));
+			PDM_SNPF((output + used, out_len - used, "reg924:0x%08X\n", dm->radar_detect_reg_924));
+		} else {
+			dm->radar_detect_dbg_parm_en = 0;
+			PDM_SNPF((output + used, out_len - used, "Radar detection with default parameter\n"));
+		}
+		phydm_radar_detect_enable(dm);
+#endif  defined(CONFIG_PHYDM_DFS_MASTER)
+
+		break;
+	default:
+		break;
+	}*/
+}
+
+u8 phydm_dfs_polling_time(void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	u8 dfs_polling_time = 0;
+
+	if (dm->support_ic_type & (ODM_RTL8814A | ODM_RTL8822B | ODM_RTL8821C))
+		dfs_polling_time = 40;
+	else
+		dfs_polling_time = 100;
+
+	return dfs_polling_time;
+}
+
+#endif /* @defined(CONFIG_PHYDM_DFS_MASTER) */
+
+boolean
+phydm_is_dfs_band(void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+
+	if (((*dm->channel >= 52) && (*dm->channel <= 64)) ||
+	    ((*dm->channel >= 100) && (*dm->channel <= 144)))
+		return true;
+	else
+		return false;
+}
+
+boolean
+phydm_dfs_master_enabled(void *dm_void)
+{
+#ifdef CONFIG_PHYDM_DFS_MASTER
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	boolean ret_val = false;
+
+	if (dm->dfs_master_enabled) /*pointer protection*/
+		ret_val = *dm->dfs_master_enabled ? true : false;
+
+	return ret_val;
+#else
+	return false;
+#endif
+}
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/phydm_dfs.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/phydm_dfs.h
--- linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/phydm_dfs.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/phydm_dfs.h	2020-04-10 16:35:06.824660441 +0300
@@ -0,0 +1,181 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017  Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * The full GNU General Public License is included in this distribution in the
+ * file called LICENSE.
+ *
+ * Contact Information:
+ * wlanfae <wlanfae@realtek.com>
+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
+ * Hsinchu 300, Taiwan.
+ *
+ * Larry Finger <Larry.Finger@lwfinger.net>
+ *
+ *****************************************************************************/
+
+#ifndef __PHYDM_DFS_H__
+#define __PHYDM_DFS_H__
+
+#define DFS_VERSION "1.1"
+
+/*@
+ * ============================================================
+ *  Definition
+ * ============================================================
+ */
+
+/*@
+ * ============================================================
+ * 1  structure
+ * ============================================================
+ */
+
+struct _DFS_STATISTICS {
+	u8		mask_idx;
+	u8		igi_cur;
+	u8		igi_pre;
+	u8		st_l2h_cur;
+	u16		fa_count_pre;
+	u16		fa_inc_hist[5];
+	u16		vht_crc_ok_cnt_pre;
+	u16		ht_crc_ok_cnt_pre;
+	u16		leg_crc_ok_cnt_pre;
+	u16		short_pulse_cnt_pre;
+	u16		long_pulse_cnt_pre;
+	u8		pwdb_th;
+	u8		pwdb_th_cur;
+	u8		pwdb_scalar_factor;
+	u8		peak_th;
+	u8		short_pulse_cnt_th;
+	u8		long_pulse_cnt_th;
+	u8		peak_window;
+	u8		three_peak_opt;
+	u8		three_peak_th2;
+	u8		fa_mask_th;
+	u8		det_flag_offset;
+	u8		st_l2h_max;
+	u8		st_l2h_min;
+	u8		mask_hist_checked;
+	boolean		pulse_flag_hist[5];
+	boolean		pulse_type_hist[5];
+	boolean		radar_det_mask_hist[5];
+	boolean		idle_mode;
+	boolean		force_TP_mode;
+	boolean		dbg_mode;
+	boolean		det_print;
+	boolean		det_print2;
+	boolean		radar_type;
+	/*@dfs histogram*/
+	boolean		print_hist_rpt;
+	boolean		hist_cond_on;
+	boolean		pri_cond1;
+	boolean		pri_cond2;
+	boolean		pri_cond3;
+	boolean		pri_cond4;
+	boolean		pri_cond5;
+	boolean		pw_cond1;
+	boolean		pw_cond2;
+	boolean		pw_cond3;
+	boolean		pri_type3_4_cond1;	/*@for ETSI*/
+	boolean		pri_type3_4_cond2;	/*@for ETSI*/
+	boolean		pw_long_cond1;	/*@for long radar*/
+	boolean		pw_long_cond2;	/*@for long radar*/
+	boolean		pri_long_cond1;	/*@for long radar*/
+	boolean		pw_flag;
+	boolean		pri_flag;
+	boolean		pri_type3_4_flag;	/*@for ETSI*/
+	boolean		long_radar_flag;
+	u16		pri_hold_sum[6];
+	u16		pw_hold_sum[6];
+	u16		pri_long_hold_sum[6];
+	u16		pw_long_hold_sum[6];
+	u8		pri_hist_th;
+	u8		hist_idx;
+	u8		hist_long_idx;
+	u8		pw_hold[4][6];
+	u8		pri_hold[4][6];
+	u8		pw_long_hold[300][6];
+	u8		pri_long_hold[300][6];
+	u16		pw_std;	/*@The std(var) of reasonable num of pw group*/
+	u16		pri_std;/*@The std(var) of reasonable num of pri group*/
+	/*@dfs histogram threshold*/
+	u8		pri_sum_g1_th;
+	u8		pri_sum_g5_th;
+	u8		pri_sum_g1_fcc_th;
+	u8		pri_sum_g3_fcc_th;
+	u8		pri_sum_safe_fcc_th;
+	u8		pri_sum_type4_th;
+	u8		pri_sum_type6_th;
+	u8		pri_sum_safe_th;
+	u8		pri_sum_g5_under_g1_th;
+	u8		pri_pw_diff_th;
+	u8		pri_pw_diff_fcc_th;
+	u8		pri_pw_diff_fcc_idle_th;
+	u8		pri_pw_diff_w53_th;
+	u8		pri_type1_low_fcc_th;
+	u8		pri_type1_upp_fcc_th;
+	u8		pri_type1_cen_fcc_th;
+	u8		pw_g0_th;
+	u8		pw_long_lower_20m_th;
+	u8		pw_long_lower_th;
+	u8		pri_long_upper_th;
+	u8		pw_long_sum_upper_th;
+	u8		pw_std_th;
+	u8		pw_std_idle_th;
+	u8		pri_std_th;
+	u8		pri_std_idle_th;
+	u8		type4_pw_max_cnt;
+	u8		type4_safe_pri_sum_th;
+};
+
+/*@
+ * ============================================================
+ * enumeration
+ * ============================================================
+ */
+
+enum phydm_dfs_region_domain {
+	PHYDM_DFS_DOMAIN_UNKNOWN =	0,
+	PHYDM_DFS_DOMAIN_FCC =		1,
+	PHYDM_DFS_DOMAIN_MKK =		2,
+	PHYDM_DFS_DOMAIN_ETSI =		3,
+};
+
+/*@
+ * ============================================================
+ * function prototype
+ * ============================================================
+ */
+#if defined(CONFIG_PHYDM_DFS_MASTER)
+void phydm_radar_detect_reset(void *dm_void);
+void phydm_radar_detect_disable(void *dm_void);
+void phydm_radar_detect_enable(void *dm_void);
+boolean phydm_radar_detect(void *dm_void);
+void phydm_dfs_histogram_radar_distinguish(void *dm_void);
+boolean phydm_dfs_hist_log(void *dm_void, u8 index);
+void phydm_dfs_parameter_init(void *dm_void);
+void phydm_dfs_debug(void *dm_void, char input[][16], u32 *_used,
+		     char *output, u32 *_out_len);
+u8 phydm_dfs_polling_time(void *dm_void);
+#endif /* @defined(CONFIG_PHYDM_DFS_MASTER) */
+
+boolean
+phydm_dfs_is_meteorology_channel(void *dm_void);
+
+boolean
+phydm_is_dfs_band(void *dm_void);
+
+boolean
+phydm_dfs_master_enabled(void *dm_void);
+
+#endif /*@#ifndef __PHYDM_DFS_H__ */
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/phydm_dig.c linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/phydm_dig.c
--- linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/phydm_dig.c	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/phydm_dig.c	2020-04-10 16:35:06.824660441 +0300
@@ -0,0 +1,2729 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017  Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * The full GNU General Public License is included in this distribution in the
+ * file called LICENSE.
+ *
+ * Contact Information:
+ * wlanfae <wlanfae@realtek.com>
+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
+ * Hsinchu 300, Taiwan.
+ *
+ * Larry Finger <Larry.Finger@lwfinger.net>
+ *
+ *****************************************************************************/
+
+/*@************************************************************
+ * include files
+ * ************************************************************
+ */
+#include "mp_precomp.h"
+#include "phydm_precomp.h"
+
+#ifdef CFG_DIG_DAMPING_CHK
+void phydm_dig_recorder_reset(void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
+	struct phydm_dig_recorder_strcut *dig_rc = &dig_t->dig_recorder_t;
+
+	PHYDM_DBG(dm, DBG_DIG, "%s ======>\n", __func__);
+
+	odm_memory_set(dm, &dig_rc->igi_bitmap, 0,
+		       sizeof(struct phydm_dig_recorder_strcut));
+}
+
+void phydm_dig_recorder(void *dm_void, boolean first_connect, u8 igi_curr,
+			u32 fa_cnt)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
+	struct phydm_dig_recorder_strcut *dig_rc = &dig_t->dig_recorder_t;
+	u8 igi_pre = dig_rc->igi_history[0];
+	u8 igi_up = 0;
+
+	if (!dm->is_linked)
+		return;
+
+	PHYDM_DBG(dm, DBG_DIG, "%s ======>\n", __func__);
+
+	if (first_connect) {
+		phydm_dig_recorder_reset(dm);
+		dig_rc->igi_history[0] = igi_curr;
+		dig_rc->fa_history[0] = fa_cnt;
+		return;
+	}
+
+	igi_pre = dig_rc->igi_history[0];
+	igi_up = (igi_curr > igi_pre) ? 1 : 0;
+	dig_rc->igi_bitmap = ((dig_rc->igi_bitmap << 1) & 0xfe) | igi_up;
+
+	dig_rc->igi_history[3] = dig_rc->igi_history[2];
+	dig_rc->igi_history[2] = dig_rc->igi_history[1];
+	dig_rc->igi_history[1] = dig_rc->igi_history[0];
+	dig_rc->igi_history[0] = igi_curr;
+
+	dig_rc->fa_history[3] = dig_rc->fa_history[2];
+	dig_rc->fa_history[2] = dig_rc->fa_history[1];
+	dig_rc->fa_history[1] = dig_rc->fa_history[0];
+	dig_rc->fa_history[0] = fa_cnt;
+
+	PHYDM_DBG(dm, DBG_DIG, "igi_history[3:0] = {0x%x, 0x%x, 0x%x, 0x%x}\n",
+		  dig_rc->igi_history[3], dig_rc->igi_history[2],
+		  dig_rc->igi_history[1], dig_rc->igi_history[0]);
+	PHYDM_DBG(dm, DBG_DIG, "fa_history[3:0] = {%d, %d, %d, %d}\n",
+		  dig_rc->fa_history[3], dig_rc->fa_history[2],
+		  dig_rc->fa_history[1], dig_rc->fa_history[0]);
+	PHYDM_DBG(dm, DBG_DIG, "igi_bitmap = {%d, %d, %d, %d} = 0x%x\n",
+		  (u8)((dig_rc->igi_bitmap & BIT(3)) >> 3),
+		  (u8)((dig_rc->igi_bitmap & BIT(2)) >> 2),
+		  (u8)((dig_rc->igi_bitmap & BIT(1)) >> 1),
+		  (u8)(dig_rc->igi_bitmap & BIT(0)),
+		  dig_rc->igi_bitmap);
+}
+
+void phydm_dig_damping_chk(void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
+	struct phydm_dig_recorder_strcut *dig_rc = &dig_t->dig_recorder_t;
+	u8 igi_bitmap_4bit = dig_rc->igi_bitmap & 0xf;
+	u8 diff1 = 0, diff2 = 0;
+	u32 fa_low_th = dig_t->fa_th[0];
+	u32 fa_high_th = dig_t->fa_th[1];
+	u8 fa_pattern_match = 0;
+	u32 time_tmp;
+
+	if (!dm->is_linked)
+		return;
+
+	PHYDM_DBG(dm, DBG_DIG, "%s ======>\n", __func__);
+
+	/*@== Release Damping ================================================*/
+	if (dig_rc->damping_limit_en) {
+		PHYDM_DBG(dm, DBG_DIG,
+			  "[Damping Limit!] limit_time=%d, phydm_sys_up_time=%d\n",
+			  dig_rc->limit_time, dm->phydm_sys_up_time);
+
+		time_tmp = dig_rc->limit_time + DIG_LIMIT_PERIOD;
+
+		if (DIFF_2(dm->rssi_min, dig_rc->limit_rssi) > 3 ||
+		    time_tmp < dm->phydm_sys_up_time) {
+			dig_rc->damping_limit_en = 0;
+			PHYDM_DBG(dm, DBG_DIG, "rssi_min=%d, limit_rssi=%d\n",
+				  dm->rssi_min, dig_rc->limit_rssi);
+		}
+		return;
+	}
+
+	/*@== Damping Pattern Check===========================================*/
+	PHYDM_DBG(dm, DBG_DIG, "fa_th{H, L}= {%d,%d}\n", fa_high_th, fa_low_th);
+
+	switch (igi_bitmap_4bit) {
+	case 0x5: /*@4b'0101 ex:down(0x24)->up(0x28)->down(0x24)->up(0x28)*/
+		if (dig_rc->igi_history[0] > dig_rc->igi_history[1])
+			diff1 = dig_rc->igi_history[0] - dig_rc->igi_history[1];
+
+		if (dig_rc->igi_history[2] > dig_rc->igi_history[3])
+			diff2 = dig_rc->igi_history[2] - dig_rc->igi_history[3];
+
+		if (dig_rc->fa_history[0] < fa_low_th &&
+		    dig_rc->fa_history[1] > fa_high_th &&
+		    dig_rc->fa_history[2] < fa_low_th &&
+		    dig_rc->fa_history[3] > fa_high_th) {
+		    /*@Check each fa element*/
+			fa_pattern_match = 1;
+		}
+		break;
+	case 0x9: /*@4b'1001 ex:up(0x28)->down(0x26)->down(0x24)->up(0x28)*/
+		if (dig_rc->igi_history[0] > dig_rc->igi_history[1])
+			diff1 = dig_rc->igi_history[0] - dig_rc->igi_history[1];
+
+		if (dig_rc->igi_history[2] < dig_rc->igi_history[3])
+			diff2 = dig_rc->igi_history[3] - dig_rc->igi_history[2];
+
+		if (dig_rc->fa_history[0] < fa_low_th &&
+		    dig_rc->fa_history[1] > fa_high_th &&
+		    dig_rc->fa_history[2] > fa_low_th &&
+		    dig_rc->fa_history[3] < fa_high_th) {
+		    /*@Check each fa element*/
+			fa_pattern_match = 1;
+		}
+		break;
+	default:
+		break;
+	}
+
+	if (diff1 >= 2 && diff2 >= 2 && fa_pattern_match) {
+		dig_rc->damping_limit_en = 1;
+		dig_rc->damping_limit_val = dig_rc->igi_history[0];
+		dig_rc->limit_time = dm->phydm_sys_up_time;
+		dig_rc->limit_rssi = dm->rssi_min;
+
+		PHYDM_DBG(dm, DBG_DIG,
+			  "[Start damping_limit!] IGI_dyn_min=0x%x, limit_time=%d, limit_rssi=%d\n",
+			  dig_rc->damping_limit_val,
+			  dig_rc->limit_time, dig_rc->limit_rssi);
+	}
+
+	PHYDM_DBG(dm, DBG_DIG, "damping_limit=%d\n", dig_rc->damping_limit_en);
+}
+#endif
+
+boolean
+phydm_dig_go_up_check(void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct ccx_info *ccx_info = &dm->dm_ccx_info;
+	struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
+	u8 cur_ig_value = dig_t->cur_ig_value;
+	u8 max_cover_bond = 0;
+	u8 rx_gain_range_max = dig_t->rx_gain_range_max;
+	u8 i = 0, j = 0;
+	u8 total_nhm_cnt = ccx_info->nhm_rpt_sum;
+	u32 dig_cnt = 0;
+	u32 over_dig_cnt = 0;
+	boolean ret = true;
+
+	if (*dm->bb_op_mode == PHYDM_PERFORMANCE_MODE)
+		return ret;
+
+	max_cover_bond = DIG_MAX_BALANCE_MODE - dig_t->upcheck_init_val;
+
+	if (cur_ig_value < max_cover_bond - 6)
+		dig_t->go_up_chk_lv = DIG_GOUPCHECK_LEVEL_0;
+	else if (cur_ig_value <= DIG_MAX_BALANCE_MODE)
+		dig_t->go_up_chk_lv = DIG_GOUPCHECK_LEVEL_1;
+	else /* @cur_ig_value > DM_DIG_MAX_AP, foolproof */
+		dig_t->go_up_chk_lv = DIG_GOUPCHECK_LEVEL_2;
+
+	PHYDM_DBG(dm, DBG_DIG, "check_lv = %d, max_cover_bond = 0x%x\n",
+		  dig_t->go_up_chk_lv, max_cover_bond);
+
+	if (total_nhm_cnt == 0)
+		return true;
+
+	if (dig_t->go_up_chk_lv == DIG_GOUPCHECK_LEVEL_0) {
+		for (i = 3; i <= 11; i++)
+			dig_cnt += ccx_info->nhm_result[i];
+
+		if ((dig_t->lv0_ratio_reciprocal * dig_cnt) >= total_nhm_cnt)
+			ret = true;
+		else
+			ret = false;
+
+	} else if (dig_t->go_up_chk_lv == DIG_GOUPCHECK_LEVEL_1) {
+		/* search index */
+		for (i = 0; i <= 10; i++) {
+			if ((max_cover_bond * 2) == ccx_info->nhm_th[i]) {
+				for (j = (i + 1); j <= 11; j++)
+					over_dig_cnt += ccx_info->nhm_result[j];
+				break;
+			}
+		}
+
+		if (dig_t->lv1_ratio_reciprocal * over_dig_cnt < total_nhm_cnt)
+			ret = true;
+		else
+			ret = false;
+
+		if (!ret) {
+			/* update dig_t->rx_gain_range_max */
+			if (rx_gain_range_max + 6 >= max_cover_bond)
+				dig_t->rx_gain_range_max =  max_cover_bond - 6;
+			else
+				dig_t->rx_gain_range_max =  rx_gain_range_max;
+
+			PHYDM_DBG(dm, DBG_DIG,
+				  "Noise pwr over DIG can filter, lock rx_gain_range_max to 0x%x\n",
+				  dig_t->rx_gain_range_max);
+		}
+	} else if (dig_t->go_up_chk_lv == DIG_GOUPCHECK_LEVEL_2) {
+		/* @cur_ig_value > DM_DIG_MAX_AP, foolproof */
+		ret = true;
+	}
+
+	return ret;
+}
+
+void phydm_fa_threshold_check(void *dm_void, boolean is_dfs_band)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
+
+	if (dig_t->is_dbg_fa_th) {
+		PHYDM_DBG(dm, DBG_DIG, "Manual Fix FA_th\n");
+	} else if (dm->is_linked) {
+		if (dm->rssi_min < 20) { /*@[PHYDM-252]*/
+			dig_t->fa_th[0] = 500;
+			dig_t->fa_th[1] = 750;
+			dig_t->fa_th[2] = 1000;
+		} else if (((dm->rx_tp >> 2) > dm->tx_tp) && /*Test RX TP*/
+			   (dm->rx_tp < 10) && (dm->rx_tp > 1)) { /*TP=1~10Mb*/
+			dig_t->fa_th[0] = 125;
+			dig_t->fa_th[1] = 250;
+			dig_t->fa_th[2] = 500;
+		} else {
+			dig_t->fa_th[0] = 250;
+			dig_t->fa_th[1] = 500;
+			dig_t->fa_th[2] = 750;
+		}
+	} else {
+		if (is_dfs_band) { /* @For DFS band and no link */
+
+			dig_t->fa_th[0] = 250;
+			dig_t->fa_th[1] = 1000;
+			dig_t->fa_th[2] = 2000;
+		} else {
+			dig_t->fa_th[0] = 2000;
+			dig_t->fa_th[1] = 4000;
+			dig_t->fa_th[2] = 5000;
+		}
+	}
+
+	PHYDM_DBG(dm, DBG_DIG, "FA_th={%d,%d,%d}\n", dig_t->fa_th[0],
+		  dig_t->fa_th[1], dig_t->fa_th[2]);
+}
+
+void phydm_set_big_jump_step(void *dm_void, u8 curr_igi)
+{
+#if (RTL8822B_SUPPORT || RTL8197F_SUPPORT || RTL8192F_SUPPORT)
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
+	u8 step1[8] = {24, 30, 40, 50, 60, 70, 80, 90};
+	u8 big_jump_lmt = dig_t->big_jump_lmt[dig_t->agc_table_idx];
+	u8 i;
+
+	if (dig_t->enable_adjust_big_jump == 0)
+		return;
+
+	for (i = 0; i <= dig_t->big_jump_step1; i++) {
+		if ((curr_igi + step1[i]) > big_jump_lmt) {
+			if (i != 0)
+				i = i - 1;
+			break;
+		} else if (i == dig_t->big_jump_step1) {
+			break;
+		}
+	}
+	if (dm->support_ic_type & ODM_RTL8822B)
+		odm_set_bb_reg(dm, R_0x8c8, 0xe, i);
+	else if (dm->support_ic_type & (ODM_RTL8197F | ODM_RTL8192F))
+		odm_set_bb_reg(dm, ODM_REG_BB_AGC_SET_2_11N, 0xe, i);
+
+	PHYDM_DBG(dm, DBG_DIG, "Bigjump = %d (ori = 0x%x), LMT=0x%x\n", i,
+		  dig_t->big_jump_step1, big_jump_lmt);
+#endif
+}
+
+#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
+void phydm_write_dig_reg_jgr3(void *dm_void, u8 igi)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
+
+	PHYDM_DBG(dm, DBG_DIG, "%s===>\n", __func__);
+
+	/* Set IGI value */
+	if (!(dm->support_ic_type & ODM_IC_JGR3_SERIES))
+		return;
+
+	odm_set_bb_reg(dm, R_0x1d70, ODM_BIT_IGI_11AC, igi);
+
+	#if (defined(PHYDM_COMPILE_ABOVE_2SS))
+	if (dm->support_ic_type & PHYDM_IC_ABOVE_2SS)
+		odm_set_bb_reg(dm, R_0x1d70, ODM_BIT_IGI_B_11AC3, igi);
+	#endif
+
+	#if (defined(PHYDM_COMPILE_ABOVE_4SS))
+	if (dm->support_ic_type & PHYDM_IC_ABOVE_4SS) {
+		odm_set_bb_reg(dm, R_0x1d70, ODM_BIT_IGI_C_11AC3, igi);
+		odm_set_bb_reg(dm, R_0x1d70, ODM_BIT_IGI_D_11AC3, igi);
+	}
+	#endif
+}
+
+u8 phydm_get_igi_reg_val_jgr3(void *dm_void, enum bb_path path)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	u32 val = 0;
+
+	PHYDM_DBG(dm, DBG_DIG, "%s===>\n", __func__);
+
+	/* Set IGI value */
+	if (!(dm->support_ic_type & ODM_IC_JGR3_SERIES))
+		return (u8)val;
+
+	if (path == BB_PATH_A)
+		val = odm_get_bb_reg(dm, R_0x1d70, ODM_BIT_IGI_11AC);
+	else if (path == BB_PATH_B)
+		#if (defined(PHYDM_COMPILE_ABOVE_2SS))
+		val = odm_get_bb_reg(dm, R_0x1d70, ODM_BIT_IGI_B_11AC3);
+		#else
+		;
+		#endif
+	else if (path == BB_PATH_C)
+		#if (defined(PHYDM_COMPILE_ABOVE_3SS))
+		val = odm_get_bb_reg(dm, R_0x1d70, ODM_BIT_IGI_C_11AC3);
+		#else
+		;
+		#endif
+	else if (path == BB_PATH_D)
+		#if (defined(PHYDM_COMPILE_ABOVE_4SS))
+		val = odm_get_bb_reg(dm, R_0x1d70, ODM_BIT_IGI_D_11AC3);
+		#else
+		;
+		#endif
+
+	return (u8)val;
+}
+
+void phydm_fa_cnt_statistics_jgr3(void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct phydm_fa_struct *fa_t = &dm->false_alm_cnt;
+	u32 ret_value = 0;
+	u32 cck_enable = 0;
+	u16 ofdm_tx_counter = 0;
+	u16 cck_tx_counter = 0;
+
+	if (!(dm->support_ic_type & ODM_IC_JGR3_SERIES))
+		return;
+
+	ofdm_tx_counter = (u16)odm_get_bb_reg(dm, R_0x2de0, MASKLWORD);
+	cck_tx_counter = (u16)odm_get_bb_reg(dm, R_0x2de4, MASKLWORD);
+
+	ret_value = odm_get_bb_reg(dm, R_0x2d20, MASKDWORD);
+	fa_t->cnt_fast_fsync = (ret_value & 0xffff);
+	fa_t->cnt_sb_search_fail = ((ret_value & 0xffff0000) >> 16);
+
+	ret_value = odm_get_bb_reg(dm, R_0x2d04, MASKDWORD);
+	fa_t->cnt_parity_fail = ((ret_value & 0xffff0000) >> 16);
+
+	ret_value = odm_get_bb_reg(dm, R_0x2d08, MASKDWORD);
+	fa_t->cnt_rate_illegal = (ret_value & 0xffff);
+	fa_t->cnt_crc8_fail = ((ret_value & 0xffff0000) >> 16);
+
+	ret_value = odm_get_bb_reg(dm, R_0x2d10, MASKDWORD);
+	fa_t->cnt_mcs_fail = (ret_value & 0xffff);
+
+	/* read OFDM FA counter */
+	fa_t->cnt_ofdm_fail = odm_get_bb_reg(dm, R_0x2d00, MASKLWORD);
+
+	/* Read CCK FA counter */
+	fa_t->cnt_cck_fail = odm_get_bb_reg(dm, R_0x1a5c, MASKLWORD);
+
+	/* read CCK/OFDM CCA counter */
+	ret_value = odm_get_bb_reg(dm, R_0x2c08, MASKDWORD);
+	fa_t->cnt_ofdm_cca = ((ret_value & 0xffff0000) >> 16);
+	fa_t->cnt_cck_cca = ret_value & 0xffff;
+
+	/* read CCK CRC32 counter */
+	ret_value = odm_get_bb_reg(dm, R_0x2c04, MASKDWORD);
+	fa_t->cnt_cck_crc32_error = ((ret_value & 0xffff0000) >> 16);
+	fa_t->cnt_cck_crc32_ok = ret_value & 0xffff;
+
+	/* read OFDM CRC32 counter */
+	ret_value = odm_get_bb_reg(dm, R_0x2c14, MASKDWORD);
+	fa_t->cnt_ofdm_crc32_error = ((ret_value & 0xffff0000) >> 16);
+	fa_t->cnt_ofdm_crc32_ok = ret_value & 0xffff;
+
+	/* read HT CRC32 counter */
+	ret_value = odm_get_bb_reg(dm, R_0x2c10, MASKDWORD);
+	fa_t->cnt_ht_crc32_error = ((ret_value & 0xffff0000) >> 16);
+	fa_t->cnt_ht_crc32_ok = ret_value & 0xffff;
+
+	/* @for VHT part */
+	if (dm->support_ic_type & ODM_RTL8822C) {
+		/* read VHT CRC32 counter */
+		ret_value = odm_get_bb_reg(dm, R_0x2c0c, MASKDWORD);
+		fa_t->cnt_vht_crc32_error = ((ret_value & 0xffff0000) >> 16);
+		fa_t->cnt_vht_crc32_ok = ret_value & 0xffff;
+
+		ret_value = odm_get_bb_reg(dm, R_0x2d10, MASKDWORD);
+		fa_t->cnt_mcs_fail_vht = ((ret_value & 0xffff0000) >> 16);
+
+		ret_value = odm_get_bb_reg(dm, R_0x2d0c, MASKDWORD);
+		fa_t->cnt_crc8_fail_vht = ret_value & 0xffff +
+					  ((ret_value & 0xffff0000) >> 16);
+	} else {
+		fa_t->cnt_vht_crc32_error = 0;
+		fa_t->cnt_vht_crc32_ok = 0;
+		fa_t->cnt_mcs_fail_vht = 0;
+		fa_t->cnt_crc8_fail_vht = 0;
+	}
+
+	cck_enable = odm_get_bb_reg(dm, R_0x1c3c, BIT(1)); /* @98f 1C3c[1] */
+	if (cck_enable) { /* @if(*dm->band_type == ODM_BAND_2_4G) */
+		fa_t->cnt_all = fa_t->cnt_ofdm_fail + fa_t->cnt_cck_fail
+				- ofdm_tx_counter;
+		fa_t->cnt_cca_all = fa_t->cnt_cck_cca + fa_t->cnt_ofdm_cca;
+		PHYDM_DBG(dm, DBG_FA_CNT, "ac3 OFDM FA = %d, CCK FA = %d\n",
+			  fa_t->cnt_ofdm_fail - ofdm_tx_counter,
+			  fa_t->cnt_cck_fail);
+	} else {
+		fa_t->cnt_all = fa_t->cnt_ofdm_fail - ofdm_tx_counter;
+		fa_t->cnt_cca_all = fa_t->cnt_ofdm_cca;
+		PHYDM_DBG(dm, DBG_FA_CNT, "ac3 CCK disable OFDM FA = %d\n",
+			  fa_t->cnt_ofdm_fail - ofdm_tx_counter);
+	}
+
+	PHYDM_DBG(dm, DBG_FA_CNT,
+		  "ac3 [OFDM FA Detail] Parity_fail=((%d)), Rate_Illegal=((%d)), CRC8_fail=((%d)), Mcs_fail=((%d)), Fast_Fsync=((%d)), SBD_fail=((%d))\n",
+		  fa_t->cnt_parity_fail, fa_t->cnt_rate_illegal,
+		  fa_t->cnt_crc8_fail, fa_t->cnt_mcs_fail, fa_t->cnt_fast_fsync,
+		  fa_t->cnt_sb_search_fail);
+}
+
+#endif
+
+void phydm_write_dig_reg(void *dm_void, u8 igi)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+
+	PHYDM_DBG(dm, DBG_DIG, "%s===>\n", __func__);
+
+	odm_set_bb_reg(dm, ODM_REG(IGI_A, dm), ODM_BIT(IGI, dm), igi);
+
+	#if (defined(PHYDM_COMPILE_ABOVE_2SS))
+	if (dm->support_ic_type & PHYDM_IC_ABOVE_2SS)
+		odm_set_bb_reg(dm, ODM_REG(IGI_B, dm), ODM_BIT(IGI, dm), igi);
+	#endif
+
+	#if (defined(PHYDM_COMPILE_ABOVE_4SS))
+	if (dm->support_ic_type & PHYDM_IC_ABOVE_4SS) {
+		odm_set_bb_reg(dm, ODM_REG(IGI_C, dm), ODM_BIT(IGI, dm), igi);
+		odm_set_bb_reg(dm, ODM_REG(IGI_D, dm), ODM_BIT(IGI, dm), igi);
+	}
+	#endif
+}
+
+void odm_write_dig(void *dm_void, u8 new_igi)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
+	struct phydm_adaptivity_struct *adaptivity = &dm->adaptivity;
+
+	PHYDM_DBG(dm, DBG_DIG, "%s===>\n", __func__);
+
+	/* @1 Check IGI by upper bound */
+	if (adaptivity->igi_lmt_en &&
+	    new_igi > adaptivity->adapt_igi_up && dm->is_linked) {
+		new_igi = adaptivity->adapt_igi_up;
+
+		PHYDM_DBG(dm, DBG_DIG, "Force Adaptivity Up-bound=((0x%x))\n",
+			  new_igi);
+	}
+
+	#if (RTL8192F_SUPPORT)
+	if ((dm->support_ic_type & ODM_RTL8192F) &&
+	    dm->cut_version == ODM_CUT_A &&
+	    new_igi > 0x38) {
+		new_igi = 0x38;
+		PHYDM_DBG(dm, DBG_DIG,
+			  "Force 92F Adaptivity Up-bound=((0x%x))\n", new_igi);
+	}
+	#endif
+
+	if (dig_t->cur_ig_value != new_igi) {
+		#if (RTL8822B_SUPPORT || RTL8197F_SUPPORT || RTL8192F_SUPPORT)
+		/* @Modify big jump step for 8822B and 8197F */
+		if (dm->support_ic_type &
+		    (ODM_RTL8822B | ODM_RTL8197F | ODM_RTL8192F))
+			phydm_set_big_jump_step(dm, new_igi);
+		#endif
+
+		#if (ODM_PHY_STATUS_NEW_TYPE_SUPPORT)
+		/* Set IGI value of CCK for new CCK AGC */
+		if (dm->cck_new_agc &&
+		    (dm->support_ic_type & PHYSTS_2ND_TYPE_IC))
+			odm_set_bb_reg(dm, R_0xa0c, 0x3f00, (new_igi >> 1));
+		#endif
+
+		/*@Add by YuChen for USB IO too slow issue*/
+		if (!(dm->support_ic_type & ODM_IC_PWDB_EDCCA)) {
+			if (dm->support_ability & ODM_BB_ADAPTIVITY &&
+			    new_igi < dig_t->cur_ig_value) {
+				dig_t->cur_ig_value = new_igi;
+				phydm_adaptivity(dm);
+			}
+		} else {
+			if (dm->support_ability & ODM_BB_ADAPTIVITY &&
+			    new_igi > dig_t->cur_ig_value) {
+				dig_t->cur_ig_value = new_igi;
+				phydm_adaptivity(dm);
+			}
+		}
+
+		#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
+		if (dm->support_ic_type & ODM_IC_JGR3_SERIES)
+			phydm_write_dig_reg_jgr3(dm, new_igi);
+		else
+		#endif
+			phydm_write_dig_reg(dm, new_igi);
+
+		dig_t->cur_ig_value = new_igi;
+	}
+
+	PHYDM_DBG(dm, DBG_DIG, "New_igi=((0x%x))\n\n", new_igi);
+}
+
+u8 phydm_get_igi_reg_val(void *dm_void, enum bb_path path)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	u32 val = 0;
+	u32 bit_map = ODM_BIT(IGI, dm);
+
+	switch (path) {
+	case BB_PATH_A:
+		val = odm_get_bb_reg(dm, ODM_REG(IGI_A, dm), bit_map);
+		break;
+	#if (defined(PHYDM_COMPILE_ABOVE_2SS))
+	case BB_PATH_B:
+		val = odm_get_bb_reg(dm, ODM_REG(IGI_B, dm), bit_map);
+		break;
+	#endif
+
+	#if (defined(PHYDM_COMPILE_ABOVE_3SS))
+	case BB_PATH_C:
+		val = odm_get_bb_reg(dm, ODM_REG(IGI_C, dm), bit_map);
+		break;
+	#endif
+
+	#if (defined(PHYDM_COMPILE_ABOVE_4SS))
+	case BB_PATH_D:
+		val = odm_get_bb_reg(dm, ODM_REG(IGI_D, dm), bit_map);
+		break;
+	#endif
+
+	default:
+		break;
+	}
+
+	return (u8)val;
+}
+
+u8 phydm_get_igi(void *dm_void, enum bb_path path)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	u8 val;
+
+	#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
+	if (dm->support_ic_type & ODM_IC_JGR3_SERIES)
+		val = phydm_get_igi_reg_val_jgr3(dm, path);
+	else
+	#endif
+		val = phydm_get_igi_reg_val(dm, path);
+
+	return val;
+}
+
+void phydm_set_dig_val(void *dm_void, u32 *val_buf, u8 val_len)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+
+	if (val_len != 1) {
+		PHYDM_DBG(dm, ODM_COMP_API, "[Error][DIG]Need val_len=1\n");
+		return;
+	}
+
+	odm_write_dig(dm, (u8)(*val_buf));
+}
+
+void odm_pause_dig(void *dm_void, enum phydm_pause_type type,
+		   enum phydm_pause_level lv, u8 igi_input)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	u8 rpt = false;
+	u32 igi = (u32)igi_input;
+
+	PHYDM_DBG(dm, DBG_DIG, "[%s]type=%d, LV=%d, igi=0x%x\n", __func__, type,
+		  lv, igi);
+
+	switch (type) {
+	case PHYDM_PAUSE:
+	case PHYDM_PAUSE_NO_SET: {
+		rpt = phydm_pause_func(dm, F00_DIG, PHYDM_PAUSE, lv, 1, &igi);
+		break;
+	}
+
+	case PHYDM_RESUME: {
+		rpt = phydm_pause_func(dm, F00_DIG, PHYDM_RESUME, lv, 1, &igi);
+		break;
+	}
+	default:
+		PHYDM_DBG(dm, DBG_DIG, "Wrong type\n");
+		break;
+	}
+
+	PHYDM_DBG(dm, DBG_DIG, "pause_result=%d\n", rpt);
+}
+
+boolean
+phydm_dig_abort(void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
+	void *adapter = dm->adapter;
+#endif
+
+	/* support_ability */
+	if ((!(dm->support_ability & ODM_BB_FA_CNT)) ||
+	    (!(dm->support_ability & ODM_BB_DIG)) ||
+	    *dm->is_scan_in_process) {
+		PHYDM_DBG(dm, DBG_DIG, "Not Support\n");
+		return true;
+	}
+
+	if (dm->pause_ability & ODM_BB_DIG) {
+		PHYDM_DBG(dm, DBG_DIG, "Return: Pause DIG in LV=%d\n",
+			  dm->pause_lv_table.lv_dig);
+		return true;
+	}
+
+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
+#if OS_WIN_FROM_WIN7(OS_VERSION)
+	if (IsAPModeExist(adapter) && ((PADAPTER)(adapter))->bInHctTest) {
+		PHYDM_DBG(dm, DBG_DIG, " Return: Is AP mode or In HCT Test\n");
+		return true;
+	}
+#endif
+#endif
+
+	return false;
+}
+
+void phydm_dig_init(void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
+#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
+	struct phydm_fa_struct *false_alm_cnt = &dm->false_alm_cnt;
+#endif
+	u32 ret_value = 0;
+	u8 i;
+
+	dig_t->dm_dig_max = DIG_MAX_BALANCE_MODE;
+	dig_t->dm_dig_min = DIG_MIN_PERFORMANCE;
+	dig_t->dig_max_of_min = DIG_MAX_OF_MIN_BALANCE_MODE;
+
+	dig_t->cur_ig_value = phydm_get_igi(dm, BB_PATH_A);
+
+	dig_t->is_media_connect = false;
+
+	dig_t->fa_th[0] = 250;
+	dig_t->fa_th[1] = 500;
+	dig_t->fa_th[2] = 750;
+	dig_t->is_dbg_fa_th = false;
+#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
+	/* @For RTL8881A */
+	false_alm_cnt->cnt_ofdm_fail_pre = 0;
+#endif
+
+	dig_t->rx_gain_range_max = DIG_MAX_BALANCE_MODE;
+	dig_t->rx_gain_range_min = dig_t->cur_ig_value;
+
+#if (RTL8822B_SUPPORT || RTL8197F_SUPPORT || RTL8192F_SUPPORT)
+	dig_t->enable_adjust_big_jump = 1;
+	if (dm->support_ic_type & ODM_RTL8822B)
+		ret_value = odm_get_bb_reg(dm, R_0x8c8, MASKLWORD);
+	else if (dm->support_ic_type & (ODM_RTL8197F | ODM_RTL8192F))
+		ret_value = odm_get_bb_reg(dm, R_0xc74, MASKLWORD);
+
+	dig_t->big_jump_step1 = (u8)(ret_value & 0xe) >> 1;
+	dig_t->big_jump_step2 = (u8)(ret_value & 0x30) >> 4;
+	dig_t->big_jump_step3 = (u8)(ret_value & 0xc0) >> 6;
+
+	if (dm->support_ic_type &
+	    (ODM_RTL8822B | ODM_RTL8197F | ODM_RTL8192F)) {
+		for (i = 0; i < sizeof(dig_t->big_jump_lmt); i++) {
+			if (dig_t->big_jump_lmt[i] == 0)
+				dig_t->big_jump_lmt[i] = 0x64;
+				/* Set -10dBm as default value */
+		}
+	}
+#endif
+
+#ifdef PHYDM_TDMA_DIG_SUPPORT
+	dm->original_dig_restore = true;
+#endif
+#ifdef CFG_DIG_DAMPING_CHK
+	phydm_dig_recorder_reset(dm);
+	dig_t->dig_dl_en = 1;
+#endif
+}
+
+void phydm_dig_abs_boundary_decision(struct dm_struct *dm, boolean is_dfs_band)
+{
+	struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
+
+	if (!dm->is_linked) {
+		dig_t->dm_dig_max = DIG_MAX_COVERAGR;
+		dig_t->dm_dig_min = DIG_MIN_COVERAGE;
+	} else if (is_dfs_band) {
+		if (*dm->band_width == CHANNEL_WIDTH_20)
+			dig_t->dm_dig_min = DIG_MIN_DFS + 2;
+		else
+			dig_t->dm_dig_min = DIG_MIN_DFS;
+
+		dig_t->dig_max_of_min = DIG_MAX_OF_MIN_BALANCE_MODE;
+		dig_t->dm_dig_max = DIG_MAX_BALANCE_MODE;
+	} else {
+		if (*dm->bb_op_mode == PHYDM_BALANCE_MODE) {
+		/*service > 2 devices*/
+			dig_t->dm_dig_max = DIG_MAX_BALANCE_MODE;
+			#if (DIG_HW == 1)
+			dig_t->dig_max_of_min = DIG_MIN_COVERAGE;
+			#else
+			dig_t->dig_max_of_min = DIG_MAX_OF_MIN_BALANCE_MODE;
+			#endif
+		} else if (*dm->bb_op_mode == PHYDM_PERFORMANCE_MODE) {
+		/*service 1 devices*/
+			dig_t->dm_dig_max = DIG_MAX_PERFORMANCE_MODE;
+			dig_t->dig_max_of_min = DIG_MAX_OF_MIN_PERFORMANCE_MODE;
+		}
+
+		if (dm->support_ic_type &
+		    (ODM_RTL8814A | ODM_RTL8812 | ODM_RTL8821 | ODM_RTL8822B))
+			dig_t->dm_dig_min = 0x1c;
+		else if (dm->support_ic_type & ODM_RTL8197F)
+			dig_t->dm_dig_min = 0x1e; /*@For HW setting*/
+		else
+			dig_t->dm_dig_min = DIG_MIN_PERFORMANCE;
+	}
+
+	PHYDM_DBG(dm, DBG_DIG, "Abs{Max, Min}={0x%x, 0x%x}, Max_of_min=0x%x\n",
+		  dig_t->dm_dig_max, dig_t->dm_dig_min, dig_t->dig_max_of_min);
+}
+
+void phydm_dig_dym_boundary_decision(struct dm_struct *dm)
+{
+	struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
+#ifdef CFG_DIG_DAMPING_CHK
+	struct phydm_dig_recorder_strcut *dig_rc = &dig_t->dig_recorder_t;
+#endif
+	u8 offset = 15, tmp_max = 0;
+	u8 max_of_rssi_min = 0;
+
+	PHYDM_DBG(dm, DBG_DIG, "%s ======>\n", __func__);
+
+	if (!dm->is_linked) {
+		/*@if no link, always stay at lower bound*/
+		dig_t->rx_gain_range_max = dig_t->dig_max_of_min;
+		dig_t->rx_gain_range_min = dig_t->dm_dig_min;
+
+		PHYDM_DBG(dm, DBG_DIG, "No-Link, Dyn{Max, Min}={0x%x, 0x%x}\n",
+			  dig_t->rx_gain_range_max, dig_t->rx_gain_range_min);
+		return;
+	}
+
+	PHYDM_DBG(dm, DBG_DIG, "rssi_min=%d, ofst=%d\n", dm->rssi_min, offset);
+
+	/* @DIG lower bound */
+	if (dm->rssi_min > dig_t->dig_max_of_min)
+		dig_t->rx_gain_range_min = dig_t->dig_max_of_min;
+	else if (dm->rssi_min < dig_t->dm_dig_min)
+		dig_t->rx_gain_range_min = dig_t->dm_dig_min;
+	else
+		dig_t->rx_gain_range_min = dm->rssi_min;
+
+#ifdef CFG_DIG_DAMPING_CHK
+	/*@Limit Dyn min by damping*/
+	if (dig_t->dig_dl_en &&
+	    dig_rc->damping_limit_en &&
+	    dig_t->rx_gain_range_min < dig_rc->damping_limit_val) {
+		PHYDM_DBG(dm, DBG_DIG,
+			  "[Limit by Damping] Dig_dyn_min=0x%x -> 0x%x\n",
+			  dig_t->rx_gain_range_min, dig_rc->damping_limit_val);
+
+		dig_t->rx_gain_range_min = dig_rc->damping_limit_val;
+	}
+#endif
+
+	/* @DIG upper bound */
+	tmp_max = dig_t->rx_gain_range_min + offset;
+	if (dig_t->rx_gain_range_min != dm->rssi_min) {
+		max_of_rssi_min = dm->rssi_min + offset;
+		if (tmp_max > max_of_rssi_min)
+			tmp_max = max_of_rssi_min;
+	}
+
+	if (tmp_max > dig_t->dm_dig_max)
+		dig_t->rx_gain_range_max = dig_t->dm_dig_max;
+	else if (tmp_max < dig_t->dm_dig_min)
+		dig_t->rx_gain_range_max = dig_t->dm_dig_min;
+	else
+		dig_t->rx_gain_range_max = tmp_max;
+
+	#ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY
+	/* @1 Force Lower Bound for AntDiv */
+	if (!dm->is_one_entry_only &&
+	    (dm->support_ability & ODM_BB_ANT_DIV) &&
+	    (dm->ant_div_type == CG_TRX_HW_ANTDIV ||
+	     dm->ant_div_type == CG_TRX_SMART_ANTDIV)) {
+		if (dig_t->ant_div_rssi_max > dig_t->dig_max_of_min)
+			dig_t->rx_gain_range_min = dig_t->dig_max_of_min;
+		else
+			dig_t->rx_gain_range_min = (u8)dig_t->ant_div_rssi_max;
+
+		PHYDM_DBG(dm, DBG_DIG, "Force Dyn-Min=0x%x, RSSI_max=0x%x\n",
+			  dig_t->rx_gain_range_min, dig_t->ant_div_rssi_max);
+	}
+	#endif
+
+	PHYDM_DBG(dm, DBG_DIG, "Dyn{Max, Min}={0x%x, 0x%x}\n",
+		  dig_t->rx_gain_range_max, dig_t->rx_gain_range_min);
+}
+
+void phydm_dig_abnormal_case(struct dm_struct *dm)
+{
+	struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
+
+	/* @Abnormal lower bound case */
+	if (dig_t->rx_gain_range_min > dig_t->rx_gain_range_max)
+		dig_t->rx_gain_range_min = dig_t->rx_gain_range_max;
+
+	PHYDM_DBG(dm, DBG_DIG, "Abnoraml checked {Max, Min}={0x%x, 0x%x}\n",
+		  dig_t->rx_gain_range_max, dig_t->rx_gain_range_min);
+}
+
+u8 phydm_new_igi_by_fa(struct dm_struct *dm, u8 igi, u32 fa_cnt, u8 *step_size)
+{
+	boolean dig_go_up_check = true;
+	struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
+
+#if 0
+	/*@dig_go_up_check = phydm_dig_go_up_check(dm);*/
+#endif
+
+	if (fa_cnt > dig_t->fa_th[2] && dig_go_up_check)
+		igi = igi + step_size[0];
+	else if ((fa_cnt > dig_t->fa_th[1]) && dig_go_up_check)
+		igi = igi + step_size[1];
+	else if (fa_cnt < dig_t->fa_th[0])
+		igi = igi - step_size[2];
+
+	return igi;
+}
+
+u8 phydm_get_new_igi(struct dm_struct *dm, u8 igi, u32 fa_cnt,
+		     boolean is_dfs_band)
+{
+	struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
+	u8 step[3] = {0};
+	boolean first_connect = false, first_dis_connect = false;
+
+	first_connect = (dm->is_linked) && !dig_t->is_media_connect;
+	first_dis_connect = (!dm->is_linked) && dig_t->is_media_connect;
+
+	if (dm->is_linked) {
+		if (dm->pre_rssi_min <= dm->rssi_min) {
+			PHYDM_DBG(dm, DBG_DIG, "pre_rssi_min <= rssi_min\n");
+			step[0] = 2;
+			step[1] = 1;
+			step[2] = 2;
+		} else {
+			step[0] = 4;
+			step[1] = 2;
+			step[2] = 2;
+		}
+	} else {
+		step[0] = 2;
+		step[1] = 1;
+		step[2] = 2;
+	}
+
+	PHYDM_DBG(dm, DBG_DIG, "step = {-%d, +%d, +%d}\n", step[2], step[1],
+		  step[0]);
+
+	if (first_connect) {
+		if (is_dfs_band) {
+			if (dm->rssi_min > DIG_MAX_DFS)
+				igi = DIG_MAX_DFS;
+			else
+				igi = dm->rssi_min;
+			PHYDM_DBG(dm, DBG_DIG, "DFS band:IgiMax=0x%x\n",
+				  dig_t->rx_gain_range_max);
+		} else {
+			igi = dig_t->rx_gain_range_min;
+		}
+
+		#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
+		#if (RTL8812A_SUPPORT)
+		if (dm->support_ic_type == ODM_RTL8812)
+			odm_config_bb_with_header_file(dm,
+						       CONFIG_BB_AGC_TAB_DIFF);
+		#endif
+		#endif
+		PHYDM_DBG(dm, DBG_DIG, "First connect: foce IGI=0x%x\n", igi);
+	} else if (dm->is_linked) {
+		PHYDM_DBG(dm, DBG_DIG, "Adjust IGI @ linked\n");
+		/* @4 Abnormal # beacon case */
+		#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
+		if (dm->phy_dbg_info.num_qry_beacon_pkt < 5 &&
+		    fa_cnt < DM_DIG_FA_TH1 && dm->bsta_state &&
+		    dm->support_ic_type != ODM_RTL8723D) {
+			dig_t->rx_gain_range_min = 0x1c;
+			igi = dig_t->rx_gain_range_min;
+			PHYDM_DBG(dm, DBG_DIG, "Beacon_num=%d,force igi=0x%x\n",
+				  dm->phy_dbg_info.num_qry_beacon_pkt, igi);
+		} else {
+			igi = phydm_new_igi_by_fa(dm, igi, fa_cnt, step);
+		}
+		#else
+		igi = phydm_new_igi_by_fa(dm, igi, fa_cnt, step);
+		#endif
+	} else {
+		/* @2 Before link */
+		PHYDM_DBG(dm, DBG_DIG, "Adjust IGI before link\n");
+
+		if (first_dis_connect) {
+			igi = dig_t->dm_dig_min;
+			PHYDM_DBG(dm, DBG_DIG,
+				  "First disconnect:foce IGI to lower bound\n");
+		} else {
+			PHYDM_DBG(dm, DBG_DIG, "Pre_IGI=((0x%x)), FA=((%d))\n",
+				  igi, fa_cnt);
+
+			igi = phydm_new_igi_by_fa(dm, igi, fa_cnt, step);
+		}
+	}
+
+	/*@Check IGI by dyn-upper/lower bound */
+	if (igi < dig_t->rx_gain_range_min)
+		igi = dig_t->rx_gain_range_min;
+
+	if (igi > dig_t->rx_gain_range_max)
+		igi = dig_t->rx_gain_range_max;
+
+	PHYDM_DBG(dm, DBG_DIG, "fa_cnt = %d, IGI: 0x%x -> 0x%x\n",
+		  fa_cnt, dig_t->cur_ig_value, igi);
+
+	return igi;
+}
+
+boolean phydm_dig_dfs_mode_en(void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	boolean dfs_mode_en = false;
+
+	/* @Modify lower bound for DFS band */
+	if (dm->is_dfs_band) {
+		#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
+		dfs_mode_en = true;
+		#else
+		if (phydm_dfs_master_enabled(dm))
+			dfs_mode_en = true;
+		#endif
+		PHYDM_DBG(dm, DBG_DIG, "In DFS band\n");
+	}
+	return dfs_mode_en;
+}
+
+void phydm_dig(void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
+	struct phydm_fa_struct *falm_cnt = &dm->false_alm_cnt;
+#ifdef PHYDM_TDMA_DIG_SUPPORT
+	struct phydm_fa_acc_struct *falm_cnt_acc = &dm->false_alm_cnt_acc;
+#endif
+	boolean first_connect, first_disconnect;
+	u8 igi = dig_t->cur_ig_value;
+	u8 new_igi = 0x20;
+	u32 fa_cnt = falm_cnt->cnt_all;
+	boolean dfs_mode_en = false;
+
+#ifdef PHYDM_TDMA_DIG_SUPPORT
+	if (!(dm->original_dig_restore)) {
+		if (dig_t->cur_ig_value_tdma == 0)
+			dig_t->cur_ig_value_tdma = dig_t->cur_ig_value;
+
+		igi = dig_t->cur_ig_value_tdma;
+		fa_cnt = falm_cnt_acc->cnt_all_1sec;
+	}
+#endif
+
+	if (phydm_dig_abort(dm)) {
+		dig_t->cur_ig_value = phydm_get_igi(dm, BB_PATH_A);
+		return;
+	}
+
+	PHYDM_DBG(dm, DBG_DIG, "%s Start===>\n", __func__);
+
+	/* @1 Update status */
+	first_connect = (dm->is_linked) && !dig_t->is_media_connect;
+	first_disconnect = (!dm->is_linked) && dig_t->is_media_connect;
+
+	PHYDM_DBG(dm, DBG_DIG,
+		  "is_linked=%d, RSSI=%d, 1stConnect=%d, 1stDisconnect=%d\n",
+		  dm->is_linked, dm->rssi_min, first_connect, first_disconnect);
+
+	PHYDM_DBG(dm, DBG_DIG, "DIG ((%s)) mode\n",
+		  (*dm->bb_op_mode ? "Balance" : "Performance"));
+
+	/*@DFS mode enable check*/
+	dfs_mode_en = phydm_dig_dfs_mode_en(dm);
+
+#ifdef CFG_DIG_DAMPING_CHK
+	/*Record IGI History*/
+	phydm_dig_recorder(dm, first_connect, igi, fa_cnt);
+
+	/*@DIG Damping Check*/
+	phydm_dig_damping_chk(dm);
+#endif
+
+	/*@Absolute Boundary Decision */
+	phydm_dig_abs_boundary_decision(dm, dfs_mode_en);
+
+	/*@Dynamic Boundary Decision*/
+	phydm_dig_dym_boundary_decision(dm);
+
+	/*@Abnormal case check*/
+	phydm_dig_abnormal_case(dm);
+
+	/*@FA threshold decision */
+	phydm_fa_threshold_check(dm, dfs_mode_en);
+
+	/*Select new IGI by FA */
+	new_igi = phydm_get_new_igi(dm, igi, fa_cnt, dfs_mode_en);
+
+	/* @1 Update status */
+	#ifdef PHYDM_TDMA_DIG_SUPPORT
+	if (!(dm->original_dig_restore)) {
+		dig_t->cur_ig_value_tdma = new_igi;
+		/*@It is possible fa_acc_1sec_tsf >= */
+		/*@1sec while tdma_dig_state == 0*/
+		if (dig_t->tdma_dig_state != 0)
+			odm_write_dig(dm, dig_t->cur_ig_value_tdma);
+	} else
+	#endif
+		odm_write_dig(dm, new_igi);
+
+	dig_t->is_media_connect = dm->is_linked;
+}
+
+void phydm_dig_lps_32k(void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	u8 current_igi = dm->rssi_min;
+
+	odm_write_dig(dm, current_igi);
+}
+
+void phydm_dig_by_rssi_lps(void *dm_void)
+{
+#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct phydm_fa_struct *falm_cnt;
+
+	u8 rssi_lower = DIG_MIN_LPS; /* @0x1E or 0x1C */
+	u8 current_igi = dm->rssi_min;
+
+	falm_cnt = &dm->false_alm_cnt;
+	if (phydm_dig_abort(dm))
+		return;
+
+	current_igi = current_igi + RSSI_OFFSET_DIG_LPS;
+	PHYDM_DBG(dm, DBG_DIG, "%s==>\n", __func__);
+
+	/* Using FW PS mode to make IGI */
+	/* @Adjust by  FA in LPS MODE */
+	if (falm_cnt->cnt_all > DM_DIG_FA_TH2_LPS)
+		current_igi = current_igi + 4;
+	else if (falm_cnt->cnt_all > DM_DIG_FA_TH1_LPS)
+		current_igi = current_igi + 2;
+	else if (falm_cnt->cnt_all < DM_DIG_FA_TH0_LPS)
+		current_igi = current_igi - 2;
+
+	/* @Lower bound checking */
+
+	/* RSSI Lower bound check */
+	if ((dm->rssi_min - 10) > DIG_MIN_LPS)
+		rssi_lower = (dm->rssi_min - 10);
+	else
+		rssi_lower = DIG_MIN_LPS;
+
+	/* Upper and Lower Bound checking */
+	if (current_igi > DIG_MAX_LPS)
+		current_igi = DIG_MAX_LPS;
+	else if (current_igi < rssi_lower)
+		current_igi = rssi_lower;
+
+	PHYDM_DBG(dm, DBG_DIG, "fa_cnt_all=%d, rssi_min=%d, curr_igi=0x%x\n",
+		  falm_cnt->cnt_all, dm->rssi_min, current_igi);
+	odm_write_dig(dm, current_igi);
+#endif
+}
+
+/* @3============================================================
+ * 3 FASLE ALARM CHECK
+ * 3============================================================
+ */
+void phydm_false_alarm_counter_reg_reset(void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct phydm_fa_struct *falm_cnt = &dm->false_alm_cnt;
+#ifdef PHYDM_TDMA_DIG_SUPPORT
+	struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
+	struct phydm_fa_acc_struct *falm_cnt_acc = &dm->false_alm_cnt_acc;
+#endif
+	u32 false_alm_cnt;
+
+#ifdef PHYDM_TDMA_DIG_SUPPORT
+	if (!(dm->original_dig_restore)) {
+		if (dig_t->cur_ig_value_tdma == 0)
+			dig_t->cur_ig_value_tdma = dig_t->cur_ig_value;
+
+		false_alm_cnt = falm_cnt_acc->cnt_all_1sec;
+	} else
+#endif
+	{
+		false_alm_cnt = falm_cnt->cnt_all;
+	}
+
+#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
+	if (dm->support_ic_type & ODM_IC_JGR3_SERIES) {
+		/* reset CCK FA counter */
+		odm_set_bb_reg(dm, R_0x1a2c, BIT(15) | BIT(14), 0);
+		odm_set_bb_reg(dm, R_0x1a2c, BIT(15) | BIT(14), 2);
+
+		/* reset CCK CCA counter */
+		odm_set_bb_reg(dm, R_0x1a2c, BIT(13) | BIT(12), 0);
+		odm_set_bb_reg(dm, R_0x1a2c, BIT(13) | BIT(12), 2);
+
+		/* reset OFDM CCA counter, OFDM FA counter*/
+		odm_set_bb_reg(dm, R_0x1eb4, BIT(25), 1);
+		odm_set_bb_reg(dm, R_0x1eb4, BIT(25), 0);
+	}
+#endif
+#if (ODM_IC_11N_SERIES_SUPPORT)
+	if (dm->support_ic_type & ODM_IC_11N_SERIES) {
+		/*reset false alarm counter registers*/
+		odm_set_bb_reg(dm, R_0xc0c, BIT(31), 1);
+		odm_set_bb_reg(dm, R_0xc0c, BIT(31), 0);
+		odm_set_bb_reg(dm, R_0xd00, BIT(27), 1);
+		odm_set_bb_reg(dm, R_0xd00, BIT(27), 0);
+
+		/*update ofdm counter*/
+		/*update page C counter*/
+		odm_set_bb_reg(dm, R_0xc00, BIT(31), 0);
+		/*update page D counter*/
+		odm_set_bb_reg(dm, R_0xd00, BIT(31), 0);
+
+		/*reset CCK CCA counter*/
+		odm_set_bb_reg(dm, R_0xa2c, BIT(13) | BIT(12), 0);
+		odm_set_bb_reg(dm, R_0xa2c, BIT(13) | BIT(12), 2);
+
+		/*reset CCK FA counter*/
+		odm_set_bb_reg(dm, R_0xa2c, BIT(15) | BIT(14), 0);
+		odm_set_bb_reg(dm, R_0xa2c, BIT(15) | BIT(14), 2);
+
+		/*reset CRC32 counter*/
+		odm_set_bb_reg(dm, R_0xf14, BIT(16), 1);
+		odm_set_bb_reg(dm, R_0xf14, BIT(16), 0);
+	}
+#endif /* @#if (ODM_IC_11N_SERIES_SUPPORT) */
+
+#if (ODM_IC_11AC_SERIES_SUPPORT)
+	if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
+		#if (RTL8881A_SUPPORT)
+		/* Reset FA counter by enable/disable OFDM */
+		if ((dm->support_ic_type == ODM_RTL8881A) &&
+		    false_alm_cnt->cnt_ofdm_fail_pre >= 0x7fff) {
+			/* reset OFDM */
+			odm_set_bb_reg(dm, R_0x808, BIT(29), 0);
+			odm_set_bb_reg(dm, R_0x808, BIT(29), 1);
+			false_alm_cnt->cnt_ofdm_fail_pre = 0;
+			PHYDM_DBG(dm, DBG_FA_CNT, "Reset FA_cnt\n");
+		}
+		#endif /* @#if (RTL8881A_SUPPORT) */
+
+		/* reset OFDM FA countner */
+		odm_set_bb_reg(dm, R_0x9a4, BIT(17), 1);
+		odm_set_bb_reg(dm, R_0x9a4, BIT(17), 0);
+
+		/* reset CCK FA counter */
+		odm_set_bb_reg(dm, R_0xa2c, BIT(15), 0);
+		odm_set_bb_reg(dm, R_0xa2c, BIT(15), 1);
+
+		/* reset CCA counter */
+		phydm_reset_bb_hw_cnt_ac(dm);
+	}
+#endif /* @#if (ODM_IC_11AC_SERIES_SUPPORT) */
+}
+
+void phydm_false_alarm_counter_reg_hold(void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+
+	if (dm->support_ic_type & ODM_IC_JGR3_SERIES) {
+		/* @hold cck counter */
+		odm_set_bb_reg(dm, R_0x1a2c, BIT(12), 1);
+		odm_set_bb_reg(dm, R_0x1a2c, BIT(14), 1);
+	} else if (dm->support_ic_type & ODM_IC_11N_SERIES) {
+		/*@hold ofdm counter*/
+		/*@hold page C counter*/
+		odm_set_bb_reg(dm, R_0xc00, BIT(31), 1);
+		/*@hold page D counter*/
+		odm_set_bb_reg(dm, R_0xd00, BIT(31), 1);
+
+		/*@hold cck counter*/
+		odm_set_bb_reg(dm, R_0xa2c, BIT(12), 1);
+		odm_set_bb_reg(dm, R_0xa2c, BIT(14), 1);
+	}
+}
+
+#if (ODM_IC_11N_SERIES_SUPPORT)
+void phydm_fa_cnt_statistics_n(void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct phydm_fa_struct *fa_t = &dm->false_alm_cnt;
+	u32 reg = 0;
+
+	if (!(dm->support_ic_type & ODM_IC_11N_SERIES))
+		return;
+
+	/* @hold ofdm & cck counter */
+	phydm_false_alarm_counter_reg_hold(dm);
+
+	reg = odm_get_bb_reg(dm, ODM_REG_OFDM_FA_TYPE1_11N, MASKDWORD);
+	fa_t->cnt_fast_fsync = (reg & 0xffff);
+	fa_t->cnt_sb_search_fail = ((reg & 0xffff0000) >> 16);
+
+	reg = odm_get_bb_reg(dm, ODM_REG_OFDM_FA_TYPE2_11N, MASKDWORD);
+	fa_t->cnt_ofdm_cca = (reg & 0xffff);
+	fa_t->cnt_parity_fail = ((reg & 0xffff0000) >> 16);
+
+	reg = odm_get_bb_reg(dm, ODM_REG_OFDM_FA_TYPE3_11N, MASKDWORD);
+	fa_t->cnt_rate_illegal = (reg & 0xffff);
+	fa_t->cnt_crc8_fail = ((reg & 0xffff0000) >> 16);
+
+	reg = odm_get_bb_reg(dm, ODM_REG_OFDM_FA_TYPE4_11N, MASKDWORD);
+	fa_t->cnt_mcs_fail = (reg & 0xffff);
+
+	fa_t->cnt_ofdm_fail =
+		fa_t->cnt_parity_fail + fa_t->cnt_rate_illegal +
+		fa_t->cnt_crc8_fail + fa_t->cnt_mcs_fail +
+		fa_t->cnt_fast_fsync + fa_t->cnt_sb_search_fail;
+
+	/* read CCK CRC32 counter */
+	fa_t->cnt_cck_crc32_error = odm_get_bb_reg(dm, R_0xf84, MASKDWORD);
+	fa_t->cnt_cck_crc32_ok = odm_get_bb_reg(dm, R_0xf88, MASKDWORD);
+
+	/* read OFDM CRC32 counter */
+	reg = odm_get_bb_reg(dm, ODM_REG_OFDM_CRC32_CNT_11N, MASKDWORD);
+	fa_t->cnt_ofdm_crc32_error = (reg & 0xffff0000) >> 16;
+	fa_t->cnt_ofdm_crc32_ok = reg & 0xffff;
+
+	/* read HT CRC32 counter */
+	reg = odm_get_bb_reg(dm, ODM_REG_HT_CRC32_CNT_11N, MASKDWORD);
+	fa_t->cnt_ht_crc32_error = (reg & 0xffff0000) >> 16;
+	fa_t->cnt_ht_crc32_ok = reg & 0xffff;
+
+	/* read VHT CRC32 counter */
+	fa_t->cnt_vht_crc32_error = 0;
+	fa_t->cnt_vht_crc32_ok = 0;
+
+	#if (RTL8723D_SUPPORT)
+	if (dm->support_ic_type == ODM_RTL8723D) {
+		/* read HT CRC32 agg counter */
+		reg = odm_get_bb_reg(dm, R_0xfb8, MASKDWORD);
+		fa_t->cnt_ht_crc32_error_agg = (reg & 0xffff0000) >> 16;
+		fa_t->cnt_ht_crc32_ok_agg = reg & 0xffff;
+	}
+	#endif
+
+	#if (RTL8188E_SUPPORT)
+	if (dm->support_ic_type == ODM_RTL8188E) {
+		reg = odm_get_bb_reg(dm, ODM_REG_SC_CNT_11N, MASKDWORD);
+		fa_t->cnt_bw_lsc = (reg & 0xffff);
+		fa_t->cnt_bw_usc = ((reg & 0xffff0000) >> 16);
+	}
+	#endif
+
+	reg = odm_get_bb_reg(dm, ODM_REG_CCK_FA_LSB_11N, MASKBYTE0);
+	fa_t->cnt_cck_fail = reg;
+
+	reg = odm_get_bb_reg(dm, ODM_REG_CCK_FA_MSB_11N, MASKBYTE3);
+	fa_t->cnt_cck_fail += (reg & 0xff) << 8;
+
+	reg = odm_get_bb_reg(dm, ODM_REG_CCK_CCA_CNT_11N, MASKDWORD);
+	fa_t->cnt_cck_cca = ((reg & 0xFF) << 8) | ((reg & 0xFF00) >> 8);
+
+	fa_t->cnt_all_pre = fa_t->cnt_all;
+
+	fa_t->cnt_all = fa_t->cnt_fast_fsync +
+			fa_t->cnt_sb_search_fail +
+			fa_t->cnt_parity_fail +
+			fa_t->cnt_rate_illegal +
+			fa_t->cnt_crc8_fail +
+			fa_t->cnt_mcs_fail +
+			fa_t->cnt_cck_fail;
+
+	fa_t->cnt_cca_all = fa_t->cnt_ofdm_cca + fa_t->cnt_cck_cca;
+
+	PHYDM_DBG(dm, DBG_FA_CNT,
+		  "[OFDM FA Detail] Parity_Fail=((%d)), Rate_Illegal=((%d)), CRC8_fail=((%d)), Mcs_fail=((%d)), Fast_Fsync=(( %d )), SBD_fail=((%d))\n",
+		  fa_t->cnt_parity_fail, fa_t->cnt_rate_illegal,
+		  fa_t->cnt_crc8_fail, fa_t->cnt_mcs_fail, fa_t->cnt_fast_fsync,
+		  fa_t->cnt_sb_search_fail);
+}
+#endif
+
+#if (ODM_IC_11AC_SERIES_SUPPORT == 1)
+void phydm_fa_cnt_statistics_ac(void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct phydm_fa_struct *fa_t = &dm->false_alm_cnt;
+	u32 ret_value = 0;
+	u32 cck_enable;
+
+	if (!(dm->support_ic_type & ODM_IC_11AC_SERIES))
+		return;
+
+	ret_value = odm_get_bb_reg(dm, ODM_REG_OFDM_FA_TYPE1_11AC, MASKDWORD);
+	fa_t->cnt_fast_fsync = ((ret_value & 0xffff0000) >> 16);
+
+	ret_value = odm_get_bb_reg(dm, ODM_REG_OFDM_FA_TYPE2_11AC, MASKDWORD);
+	fa_t->cnt_sb_search_fail = (ret_value & 0xffff);
+
+	ret_value = odm_get_bb_reg(dm, ODM_REG_OFDM_FA_TYPE3_11AC, MASKDWORD);
+	fa_t->cnt_parity_fail = (ret_value & 0xffff);
+	fa_t->cnt_rate_illegal = ((ret_value & 0xffff0000) >> 16);
+
+	ret_value = odm_get_bb_reg(dm, ODM_REG_OFDM_FA_TYPE4_11AC, MASKDWORD);
+	fa_t->cnt_crc8_fail = (ret_value & 0xffff);
+	fa_t->cnt_mcs_fail = ((ret_value & 0xffff0000) >> 16);
+
+	ret_value = odm_get_bb_reg(dm, ODM_REG_OFDM_FA_TYPE5_11AC, MASKDWORD);
+	fa_t->cnt_crc8_fail_vht = (ret_value & 0xffff) +
+				  (ret_value & 0xffff0000 >> 16);
+
+	ret_value = odm_get_bb_reg(dm, ODM_REG_OFDM_FA_TYPE6_11AC, MASKDWORD);
+	fa_t->cnt_mcs_fail_vht = (ret_value & 0xffff);
+
+	/* read OFDM FA counter */
+	fa_t->cnt_ofdm_fail = odm_get_bb_reg(dm, R_0xf48, MASKLWORD);
+
+	/* Read CCK FA counter */
+	fa_t->cnt_cck_fail = odm_get_bb_reg(dm, ODM_REG_CCK_FA_11AC, MASKLWORD);
+
+	/* read CCK/OFDM CCA counter */
+	ret_value = odm_get_bb_reg(dm, ODM_REG_CCK_CCA_CNT_11AC, MASKDWORD);
+	fa_t->cnt_ofdm_cca = (ret_value & 0xffff0000) >> 16;
+	fa_t->cnt_cck_cca = ret_value & 0xffff;
+
+	/* read CCK CRC32 counter */
+	ret_value = odm_get_bb_reg(dm, ODM_REG_CCK_CRC32_CNT_11AC, MASKDWORD);
+	fa_t->cnt_cck_crc32_error = (ret_value & 0xffff0000) >> 16;
+	fa_t->cnt_cck_crc32_ok = ret_value & 0xffff;
+
+	/* read OFDM CRC32 counter */
+	ret_value = odm_get_bb_reg(dm, ODM_REG_OFDM_CRC32_CNT_11AC, MASKDWORD);
+	fa_t->cnt_ofdm_crc32_error = (ret_value & 0xffff0000) >> 16;
+	fa_t->cnt_ofdm_crc32_ok = ret_value & 0xffff;
+
+	/* read HT CRC32 counter */
+	ret_value = odm_get_bb_reg(dm, ODM_REG_HT_CRC32_CNT_11AC, MASKDWORD);
+	fa_t->cnt_ht_crc32_error = (ret_value & 0xffff0000) >> 16;
+	fa_t->cnt_ht_crc32_ok = ret_value & 0xffff;
+
+	/* read VHT CRC32 counter */
+	ret_value = odm_get_bb_reg(dm, ODM_REG_VHT_CRC32_CNT_11AC, MASKDWORD);
+	fa_t->cnt_vht_crc32_error = (ret_value & 0xffff0000) >> 16;
+	fa_t->cnt_vht_crc32_ok = ret_value & 0xffff;
+
+	#if (RTL8881A_SUPPORT)
+	if (dm->support_ic_type == ODM_RTL8881A) {
+		u32 tmp = 0;
+
+		if (fa_t->cnt_ofdm_fail >= fa_t->cnt_ofdm_fail_pre) {
+			tmp = fa_t->cnt_ofdm_fail_pre;
+			fa_t->cnt_ofdm_fail_pre = fa_t->cnt_ofdm_fail;
+			fa_t->cnt_ofdm_fail = fa_t->cnt_ofdm_fail - tmp;
+		} else {
+			fa_t->cnt_ofdm_fail_pre = fa_t->cnt_ofdm_fail;
+		}
+
+		PHYDM_DBG(dm, DBG_FA_CNT,
+			  "[8881]cnt_ofdm_fail{curr,pre}={%d,%d}\n",
+			  fa_t->cnt_ofdm_fail_pre, tmp);
+	}
+	#endif
+
+	cck_enable = odm_get_bb_reg(dm, ODM_REG_BB_RX_PATH_11AC, BIT(28));
+
+	if (cck_enable) { /* @if(*dm->band_type == ODM_BAND_2_4G) */
+		fa_t->cnt_all = fa_t->cnt_ofdm_fail + fa_t->cnt_cck_fail;
+		fa_t->cnt_cca_all = fa_t->cnt_cck_cca + fa_t->cnt_ofdm_cca;
+	} else {
+		fa_t->cnt_all = fa_t->cnt_ofdm_fail;
+		fa_t->cnt_cca_all = fa_t->cnt_ofdm_cca;
+	}
+}
+#endif
+
+void phydm_get_dbg_port_info(void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct phydm_fa_struct *fa_t = &dm->false_alm_cnt;
+	u32 dbg_port = dm->adaptivity.adaptivity_dbg_port;
+	u32 val = 0;
+
+	/*set debug port to 0x0*/
+	if (phydm_set_bb_dbg_port(dm, DBGPORT_PRI_1, 0x0)) {
+		fa_t->dbg_port0 = phydm_get_bb_dbg_port_val(dm);
+		phydm_release_bb_dbg_port(dm);
+	}
+
+	if (dm->support_ic_type & ODM_RTL8723D) {
+		val = odm_get_bb_reg(dm, R_0x9a0, BIT(29));
+	} else if (dm->support_ic_type & ODM_IC_JGR3_SERIES) {
+		val = odm_get_bb_reg(dm, R_0x2d38, BIT(24));
+	} else if (phydm_set_bb_dbg_port(dm, DBGPORT_PRI_1, dbg_port)) {
+		if (dm->support_ic_type & (ODM_RTL8723B | ODM_RTL8188E))
+			val = (phydm_get_bb_dbg_port_val(dm) & BIT(30)) >> 30;
+		else
+			val = (phydm_get_bb_dbg_port_val(dm) & BIT(29)) >> 29;
+		phydm_release_bb_dbg_port(dm);
+	}
+
+	fa_t->edcca_flag = (boolean)val;
+
+	PHYDM_DBG(dm, DBG_FA_CNT, "FA_Cnt: Dbg port 0x0 = 0x%x, EDCCA = %d\n\n",
+		  fa_t->dbg_port0, fa_t->edcca_flag);
+}
+
+void phydm_false_alarm_counter_statistics(void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct phydm_fa_struct *fa_t = &dm->false_alm_cnt;
+
+	if (!(dm->support_ability & ODM_BB_FA_CNT))
+		return;
+
+	PHYDM_DBG(dm, DBG_FA_CNT, "%s======>\n", __func__);
+
+	if (dm->support_ic_type & ODM_IC_JGR3_SERIES) {
+		#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
+		phydm_fa_cnt_statistics_jgr3(dm);
+		#endif
+	} else if (dm->support_ic_type & ODM_IC_11N_SERIES) {
+		#if (ODM_IC_11N_SERIES_SUPPORT)
+		phydm_fa_cnt_statistics_n(dm);
+		#endif
+	} else if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
+		#if (ODM_IC_11AC_SERIES_SUPPORT)
+		phydm_fa_cnt_statistics_ac(dm);
+		#endif
+	}
+
+	phydm_get_dbg_port_info(dm);
+	phydm_false_alarm_counter_reg_reset(dm_void);
+
+	fa_t->time_fa_all = fa_t->cnt_fast_fsync * 12 +
+			    fa_t->cnt_sb_search_fail * 12 +
+			    fa_t->cnt_parity_fail * 28 +
+			    fa_t->cnt_rate_illegal * 28 +
+			    fa_t->cnt_crc8_fail * 36 +
+			    fa_t->cnt_crc8_fail_vht * 36 +
+			    fa_t->cnt_mcs_fail_vht * 36 +
+			    fa_t->cnt_mcs_fail * 32 +
+			    fa_t->cnt_cck_fail * 80;
+
+	fa_t->cnt_crc32_error_all = fa_t->cnt_vht_crc32_error +
+				    fa_t->cnt_ht_crc32_error +
+				    fa_t->cnt_ofdm_crc32_error +
+				    fa_t->cnt_cck_crc32_error;
+
+	fa_t->cnt_crc32_ok_all = fa_t->cnt_vht_crc32_ok +
+				 fa_t->cnt_ht_crc32_ok +
+				 fa_t->cnt_ofdm_crc32_ok +
+				 fa_t->cnt_cck_crc32_ok;
+
+	PHYDM_DBG(dm, DBG_FA_CNT,
+		  "[OFDM FA Detail-1] Parity=((%d)), Rate_Illegal=((%d)), HT_CRC8=((%d)), HT_MCS=((%d))\n",
+		  fa_t->cnt_parity_fail, fa_t->cnt_rate_illegal,
+		  fa_t->cnt_crc8_fail, fa_t->cnt_mcs_fail);
+	PHYDM_DBG(dm, DBG_FA_CNT,
+		  "[OFDM FA Detail-2] Fast_Fsync=((%d)), SBD=((%d)), VHT_CRC8=((%d)), VHT_MCS=((%d))\n",
+		  fa_t->cnt_fast_fsync, fa_t->cnt_sb_search_fail,
+		  fa_t->cnt_crc8_fail_vht, fa_t->cnt_mcs_fail_vht);
+	PHYDM_DBG(dm, DBG_FA_CNT,
+		  "[CCA Cnt] {CCK, OFDM, Total} = {%d, %d, %d}\n",
+		  fa_t->cnt_cck_cca, fa_t->cnt_ofdm_cca, fa_t->cnt_cca_all);
+	PHYDM_DBG(dm, DBG_FA_CNT,
+		  "[FA Cnt] {CCK, OFDM, Total} = {%d, %d, %d}\n",
+		  fa_t->cnt_cck_fail, fa_t->cnt_ofdm_fail, fa_t->cnt_all);
+	PHYDM_DBG(dm, DBG_FA_CNT, "[CCK]  CRC32 {error, ok}= {%d, %d}\n",
+		  fa_t->cnt_cck_crc32_error, fa_t->cnt_cck_crc32_ok);
+	PHYDM_DBG(dm, DBG_FA_CNT, "[OFDM]CRC32 {error, ok}= {%d, %d}\n",
+		  fa_t->cnt_ofdm_crc32_error, fa_t->cnt_ofdm_crc32_ok);
+	PHYDM_DBG(dm, DBG_FA_CNT, "[ HT ]  CRC32 {error, ok}= {%d, %d}\n",
+		  fa_t->cnt_ht_crc32_error, fa_t->cnt_ht_crc32_ok);
+	PHYDM_DBG(dm, DBG_FA_CNT, "[VHT]  CRC32 {error, ok}= {%d, %d}\n",
+		  fa_t->cnt_vht_crc32_error, fa_t->cnt_vht_crc32_ok);
+	PHYDM_DBG(dm, DBG_FA_CNT, "[TOTAL]  CRC32 {error, ok}= {%d, %d}\n",
+		  fa_t->cnt_crc32_error_all, fa_t->cnt_crc32_ok_all);
+}
+
+#ifdef PHYDM_TDMA_DIG_SUPPORT
+void phydm_set_tdma_dig_timer(void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	u32 delta_time_us = dm->tdma_dig_timer_ms * 1000;
+	struct phydm_dig_struct *dig_t;
+	u32 timeout;
+	u32 current_time_stamp, diff_time_stamp, regb0;
+
+	dig_t = &dm->dm_dig_table;
+	/*some IC has no FREERUN_CUNT register, like 92E*/
+	if (dm->support_ic_type & ODM_RTL8197F)
+		current_time_stamp = odm_get_bb_reg(dm, R_0x568, 0xffffffff);
+	else
+		return;
+
+	timeout = current_time_stamp + delta_time_us;
+
+	diff_time_stamp = current_time_stamp - dig_t->cur_timestamp;
+	dig_t->pre_timestamp = dig_t->cur_timestamp;
+	dig_t->cur_timestamp = current_time_stamp;
+
+	/*@HIMR0, it shows HW interrupt mask*/
+	regb0 = odm_get_bb_reg(dm, R_0xb0, 0xffffffff);
+
+	PHYDM_DBG(dm, DBG_DIG, "Set next timer\n");
+	PHYDM_DBG(dm, DBG_DIG,
+		  "curr_time_stamp=%d, delta_time_us=%d\n",
+		  current_time_stamp, delta_time_us);
+	PHYDM_DBG(dm, DBG_DIG,
+		  "timeout=%d, diff_time_stamp=%d, Reg0xb0 = 0x%x\n",
+		  timeout, diff_time_stamp, regb0);
+
+	if (dm->support_ic_type & ODM_RTL8197F) /*REG_PS_TIMER2*/
+		odm_set_bb_reg(dm, R_0x588, 0xffffffff, timeout);
+	else {
+		PHYDM_DBG(dm, DBG_DIG, "NOT 97F, NOT start\n");
+		return;
+	}
+}
+
+void phydm_tdma_dig_timer_check(void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct phydm_dig_struct *dig_t;
+
+	dig_t = &dm->dm_dig_table;
+
+	PHYDM_DBG(dm, DBG_DIG, "tdma_dig_cnt=%d, pre_tdma_dig_cnt=%d\n",
+		  dig_t->tdma_dig_cnt, dig_t->pre_tdma_dig_cnt);
+
+	if (dig_t->tdma_dig_cnt == 0 ||
+	    dig_t->tdma_dig_cnt == dig_t->pre_tdma_dig_cnt) {
+		if (dm->support_ability & ODM_BB_DIG) {
+#ifdef IS_USE_NEW_TDMA
+			if (dm->support_ic_type &
+			    (ODM_RTL8198F | ODM_RTL8822C | ODM_RTL8814B)) {
+				PHYDM_DBG(dm, DBG_DIG,
+					  "Check fail, Restart timer\n\n");
+				phydm_false_alarm_counter_reset(dm);
+				odm_set_timer(dm, &dm->tdma_dig_timer,
+					      dm->tdma_dig_timer_ms);
+			} else {
+				PHYDM_DBG(dm, DBG_DIG,
+					  "Not 98F/22C/14B no SW timer\n");
+			}
+#else
+			/*@if interrupt mask info is got.*/
+			/*Reg0xb0 is no longer needed*/
+#if 0
+			/*regb0 = odm_get_bb_reg(dm, R_0xb0, bMaskDWord);*/
+#endif
+			PHYDM_DBG(dm, DBG_DIG,
+				  "Check fail, Mask[0]=0x%x, restart timer\n",
+				  *dm->interrupt_mask);
+
+			phydm_tdma_dig_add_interrupt_mask_handler(dm);
+			phydm_enable_rx_related_interrupt_handler(dm);
+			phydm_set_tdma_dig_timer(dm);
+#endif
+		}
+	} else {
+		PHYDM_DBG(dm, DBG_DIG, "Check pass, update pre_tdma_dig_cnt\n");
+	}
+
+	dig_t->pre_tdma_dig_cnt = dig_t->tdma_dig_cnt;
+}
+
+/*@different IC/team may use different timer for tdma-dig*/
+void phydm_tdma_dig_add_interrupt_mask_handler(void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+
+#if (DM_ODM_SUPPORT_TYPE == (ODM_AP))
+	if (dm->support_ic_type & ODM_RTL8197F) {
+		/*@HAL_INT_TYPE_PSTIMEOUT2*/
+		phydm_add_interrupt_mask_handler(dm, HAL_INT_TYPE_PSTIMEOUT2);
+	}
+#elif (DM_ODM_SUPPORT_TYPE == (ODM_WIN))
+#elif (DM_ODM_SUPPORT_TYPE == (ODM_CE))
+#endif
+}
+
+/* will be triggered by HW timer*/
+void phydm_tdma_dig(void *dm_void)
+{
+	struct dm_struct *dm;
+	struct phydm_dig_struct *dig_t;
+	struct phydm_fa_struct *falm_cnt;
+	u32 reg_c50;
+
+#if (RTL8198F_SUPPORT || RTL8822C_SUPPORT || RTL8814B_SUPPORT)
+#ifdef IS_USE_NEW_TDMA
+	if (dm->support_ic_type &
+	    (ODM_RTL8198F | ODM_RTL8822C | ODM_RTL8814B)) {
+		PHYDM_DBG(dm, DBG_DIG, "98F/22C/14B, new tdma\n");
+		return;
+	}
+#endif
+#endif
+
+	dm = (struct dm_struct *)dm_void;
+	dig_t = &dm->dm_dig_table;
+	falm_cnt = &dm->false_alm_cnt;
+	reg_c50 = odm_get_bb_reg(dm, R_0xc50, MASKBYTE0);
+
+	dig_t->tdma_dig_state =
+		dig_t->tdma_dig_cnt % dm->tdma_dig_state_number;
+
+	PHYDM_DBG(dm, DBG_DIG, "tdma_dig_state=%d, regc50=0x%x\n",
+		  dig_t->tdma_dig_state, reg_c50);
+
+	dig_t->tdma_dig_cnt++;
+
+	if (dig_t->tdma_dig_state == 1) {
+		/* update IGI from tdma_dig_state == 0*/
+		if (dig_t->cur_ig_value_tdma == 0)
+			dig_t->cur_ig_value_tdma = dig_t->cur_ig_value;
+
+		odm_write_dig(dm, dig_t->cur_ig_value_tdma);
+		phydm_tdma_false_alarm_counter_check(dm);
+		PHYDM_DBG(dm, DBG_DIG, "tdma_dig_state=%d, reset FA counter\n",
+			  dig_t->tdma_dig_state);
+
+	} else if (dig_t->tdma_dig_state == 0) {
+		/* update dig_t->CurIGValue,*/
+		/* @it may different from dig_t->cur_ig_value_tdma */
+		/* TDMA IGI upperbond @ L-state = */
+		/* rf_ft_var.tdma_dig_low_upper_bond = 0x26 */
+
+		if (dig_t->cur_ig_value >= dm->tdma_dig_low_upper_bond)
+			dig_t->low_ig_value = dm->tdma_dig_low_upper_bond;
+		else
+			dig_t->low_ig_value = dig_t->cur_ig_value;
+
+		odm_write_dig(dm, dig_t->low_ig_value);
+		phydm_tdma_false_alarm_counter_check(dm);
+	} else {
+		phydm_tdma_false_alarm_counter_check(dm);
+	}
+}
+
+/*@============================================================*/
+/*@FASLE ALARM CHECK*/
+/*@============================================================*/
+void phydm_tdma_false_alarm_counter_check(void *dm_void)
+{
+	struct dm_struct *dm;
+	struct phydm_fa_struct *falm_cnt;
+	struct phydm_fa_acc_struct *falm_cnt_acc;
+	struct phydm_dig_struct *dig_t;
+	boolean rssi_dump_en = 0;
+	u32 timestamp;
+	u8 tdma_dig_state_number;
+	u32 start_th = 0;
+
+	dm = (struct dm_struct *)dm_void;
+	falm_cnt = &dm->false_alm_cnt;
+	falm_cnt_acc = &dm->false_alm_cnt_acc;
+	dig_t = &dm->dm_dig_table;
+
+	if (dig_t->tdma_dig_state == 1)
+		phydm_false_alarm_counter_reset(dm);
+	/* Reset FalseAlarmCounterStatistics */
+	/* @fa_acc_1sec_tsf = fa_acc_1sec_tsf, keep */
+	/* @fa_end_tsf = fa_start_tsf = TSF */
+	else {
+		phydm_false_alarm_counter_statistics(dm);
+		if (dm->support_ic_type & ODM_RTL8197F) /*REG_FREERUN_CNT*/
+			timestamp = odm_get_bb_reg(dm, R_0x568, bMaskDWord);
+		else {
+			PHYDM_DBG(dm, DBG_DIG, "NOT 97F! NOT start\n");
+			return;
+		}
+		dig_t->fa_end_timestamp = timestamp;
+		dig_t->fa_acc_1sec_timestamp +=
+			(dig_t->fa_end_timestamp - dig_t->fa_start_timestamp);
+
+		/*prevent dumb*/
+		if (dm->tdma_dig_state_number == 1)
+			dm->tdma_dig_state_number = 2;
+
+		tdma_dig_state_number = dm->tdma_dig_state_number;
+		dig_t->sec_factor =
+			tdma_dig_state_number / (tdma_dig_state_number - 1);
+
+		/*@1sec = 1000000us*/
+		if (dig_t->sec_factor)
+			start_th = (u32)(1000000 / dig_t->sec_factor);
+
+		if (dig_t->fa_acc_1sec_timestamp >= start_th) {
+			rssi_dump_en = 1;
+			phydm_false_alarm_counter_acc(dm, rssi_dump_en);
+			PHYDM_DBG(dm, DBG_DIG,
+				  "sec_factor=%d, total FA=%d, is_linked=%d\n",
+				  dig_t->sec_factor, falm_cnt_acc->cnt_all,
+				  dm->is_linked);
+
+			phydm_noisy_detection(dm);
+			#ifdef PHYDM_SUPPORT_CCKPD
+			phydm_cck_pd_th(dm);
+			#endif
+			phydm_dig(dm);
+			phydm_false_alarm_counter_acc_reset(dm);
+
+			/* Reset FalseAlarmCounterStatistics */
+			/* @fa_end_tsf = fa_start_tsf = TSF, keep */
+			/* @fa_acc_1sec_tsf = 0 */
+			phydm_false_alarm_counter_reset(dm);
+		} else {
+			phydm_false_alarm_counter_acc(dm, rssi_dump_en);
+		}
+	}
+}
+
+void phydm_false_alarm_counter_acc(void *dm_void, boolean rssi_dump_en)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct phydm_fa_struct *falm_cnt;
+	struct phydm_fa_acc_struct *falm_cnt_acc;
+	struct phydm_dig_struct *dig_t;
+
+	falm_cnt = &dm->false_alm_cnt;
+	falm_cnt_acc = &dm->false_alm_cnt_acc;
+	dig_t = &dm->dm_dig_table;
+
+	falm_cnt_acc->cnt_parity_fail += falm_cnt->cnt_parity_fail;
+	falm_cnt_acc->cnt_rate_illegal += falm_cnt->cnt_rate_illegal;
+	falm_cnt_acc->cnt_crc8_fail += falm_cnt->cnt_crc8_fail;
+	falm_cnt_acc->cnt_mcs_fail += falm_cnt->cnt_mcs_fail;
+	falm_cnt_acc->cnt_ofdm_fail += falm_cnt->cnt_ofdm_fail;
+	falm_cnt_acc->cnt_cck_fail += falm_cnt->cnt_cck_fail;
+	falm_cnt_acc->cnt_all += falm_cnt->cnt_all;
+	falm_cnt_acc->cnt_fast_fsync += falm_cnt->cnt_fast_fsync;
+	falm_cnt_acc->cnt_sb_search_fail += falm_cnt->cnt_sb_search_fail;
+	falm_cnt_acc->cnt_ofdm_cca += falm_cnt->cnt_ofdm_cca;
+	falm_cnt_acc->cnt_cck_cca += falm_cnt->cnt_cck_cca;
+	falm_cnt_acc->cnt_cca_all += falm_cnt->cnt_cca_all;
+	falm_cnt_acc->cnt_cck_crc32_error += falm_cnt->cnt_cck_crc32_error;
+	falm_cnt_acc->cnt_cck_crc32_ok += falm_cnt->cnt_cck_crc32_ok;
+	falm_cnt_acc->cnt_ofdm_crc32_error += falm_cnt->cnt_ofdm_crc32_error;
+	falm_cnt_acc->cnt_ofdm_crc32_ok += falm_cnt->cnt_ofdm_crc32_ok;
+	falm_cnt_acc->cnt_ht_crc32_error += falm_cnt->cnt_ht_crc32_error;
+	falm_cnt_acc->cnt_ht_crc32_ok += falm_cnt->cnt_ht_crc32_ok;
+	falm_cnt_acc->cnt_vht_crc32_error += falm_cnt->cnt_vht_crc32_error;
+	falm_cnt_acc->cnt_vht_crc32_ok += falm_cnt->cnt_vht_crc32_ok;
+	falm_cnt_acc->cnt_crc32_error_all += falm_cnt->cnt_crc32_error_all;
+	falm_cnt_acc->cnt_crc32_ok_all += falm_cnt->cnt_crc32_ok_all;
+
+	if (rssi_dump_en == 1) {
+		falm_cnt_acc->cnt_all_1sec =
+			falm_cnt_acc->cnt_all * dig_t->sec_factor;
+		falm_cnt_acc->cnt_cca_all_1sec =
+			falm_cnt_acc->cnt_cca_all * dig_t->sec_factor;
+		falm_cnt_acc->cnt_cck_fail_1sec =
+			falm_cnt_acc->cnt_cck_fail * dig_t->sec_factor;
+	}
+}
+
+void phydm_false_alarm_counter_acc_reset(void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct phydm_fa_acc_struct *falm_cnt_acc = NULL;
+
+#ifdef IS_USE_NEW_TDMA
+	struct phydm_fa_acc_struct *falm_cnt_acc_low = NULL;
+	u32 tmp_cca_1sec = 0;
+	u32 tmp_fa_1sec = 0;
+
+	/*@clear L-fa_acc struct*/
+	falm_cnt_acc_low = &dm->false_alm_cnt_acc_low;
+	tmp_cca_1sec = falm_cnt_acc_low->cnt_cca_all_1sec;
+	tmp_fa_1sec = falm_cnt_acc_low->cnt_all_1sec;
+	odm_memory_set(dm, falm_cnt_acc_low, 0, sizeof(dm->false_alm_cnt_acc));
+	falm_cnt_acc_low->cnt_cca_all_1sec = tmp_cca_1sec;
+	falm_cnt_acc_low->cnt_all_1sec = tmp_fa_1sec;
+
+	/*@clear H-fa_acc struct*/
+	falm_cnt_acc = &dm->false_alm_cnt_acc;
+	tmp_cca_1sec = falm_cnt_acc->cnt_cca_all_1sec;
+	tmp_fa_1sec = falm_cnt_acc->cnt_all_1sec;
+	odm_memory_set(dm, falm_cnt_acc, 0, sizeof(dm->false_alm_cnt_acc));
+	falm_cnt_acc->cnt_cca_all_1sec = tmp_cca_1sec;
+	falm_cnt_acc->cnt_all_1sec = tmp_fa_1sec;
+#else
+	falm_cnt_acc = &dm->false_alm_cnt_acc;
+	/* @Cnt_all_for_rssi_dump & Cnt_CCA_all_for_rssi_dump */
+	/* @do NOT need to be reset */
+	odm_memory_set(dm, falm_cnt_acc, 0, sizeof(falm_cnt_acc));
+#endif
+}
+
+void phydm_false_alarm_counter_reset(void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct phydm_fa_struct *falm_cnt;
+	struct phydm_dig_struct *dig_t;
+	u32 timestamp;
+
+	falm_cnt = &dm->false_alm_cnt;
+	dig_t = &dm->dm_dig_table;
+
+	memset(falm_cnt, 0, sizeof(dm->false_alm_cnt));
+	phydm_false_alarm_counter_reg_reset(dm);
+
+#ifdef IS_USE_NEW_TDMA
+	return;
+#endif
+	if (dig_t->tdma_dig_state != 1)
+		dig_t->fa_acc_1sec_timestamp = 0;
+	else
+		dig_t->fa_acc_1sec_timestamp = dig_t->fa_acc_1sec_timestamp;
+
+	/*REG_FREERUN_CNT*/
+	timestamp = odm_get_bb_reg(dm, R_0x568, bMaskDWord);
+	dig_t->fa_start_timestamp = timestamp;
+	dig_t->fa_end_timestamp = timestamp;
+}
+
+#ifdef IS_USE_NEW_TDMA
+void phydm_tdma_dig_timers(void *dm_void, u8 state)
+{
+#if (RTL8198F_SUPPORT || RTL8822C_SUPPORT || RTL8814B_SUPPORT)
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
+
+	if (dm->support_ic_type &
+	    (ODM_RTL8198F | ODM_RTL8822C | ODM_RTL8814B)) {
+		if (state == INIT_TDMA_DIG_TIMMER)
+			odm_initialize_timer(dm, &dm->tdma_dig_timer,
+					     (void *)phydm_tdma_dig_cbk,
+					     NULL, "phydm_tdma_dig_timer");
+		else if (state == CANCEL_TDMA_DIG_TIMMER)
+			odm_cancel_timer(dm, &dm->tdma_dig_timer);
+		else if (state == RELEASE_TDMA_DIG_TIMMER)
+			odm_release_timer(dm, &dm->tdma_dig_timer);
+	}
+#endif
+}
+
+u8 get_new_igi_bound(struct dm_struct *dm, u8 igi, u32 fa_cnt, u8 *rx_gain_max,
+		     u8 *rx_gain_min, boolean is_dfs_band)
+{
+	struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
+	u8 step[3] = {0};
+	u8 cur_igi = igi;
+	boolean first_connect = false, first_dis_connect = false;
+
+	first_connect = (dm->is_linked) && !dig_t->is_media_connect;
+	first_dis_connect = (!dm->is_linked) && dig_t->is_media_connect;
+
+	if (dm->is_linked) {
+		if (dm->pre_rssi_min <= dm->rssi_min) {
+			PHYDM_DBG(dm, DBG_DIG, "pre_rssi_min <= rssi_min\n");
+			step[0] = 2;
+			step[1] = 1;
+			step[2] = 2;
+		} else {
+			step[0] = 4;
+			step[1] = 2;
+			step[2] = 2;
+		}
+	} else {
+		step[0] = 2;
+		step[1] = 1;
+		step[2] = 2;
+	}
+
+	PHYDM_DBG(dm, DBG_DIG, "step = {-%d, +%d, +%d}\n", step[2], step[1],
+		  step[0]);
+
+	if (first_connect) {
+		if (is_dfs_band) {
+			if (dm->rssi_min > DIG_MAX_DFS)
+				igi = DIG_MAX_DFS;
+			else
+				igi = dm->rssi_min;
+			PHYDM_DBG(dm, DBG_DIG, "DFS band:IgiMax=0x%x\n",
+				  *rx_gain_max);
+		} else {
+			igi = *rx_gain_min;
+		}
+
+		#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
+		#if (RTL8812A_SUPPORT)
+		if (dm->support_ic_type == ODM_RTL8812)
+			odm_config_bb_with_header_file(dm,
+						       CONFIG_BB_AGC_TAB_DIFF);
+		#endif
+		#endif
+		PHYDM_DBG(dm, DBG_DIG, "First connect: foce IGI=0x%x\n", igi);
+	} else if (dm->is_linked) {
+		PHYDM_DBG(dm, DBG_DIG, "Adjust IGI @ linked\n");
+		/* @4 Abnormal # beacon case */
+		#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
+		if (dm->phy_dbg_info.num_qry_beacon_pkt < 5 &&
+		    fa_cnt < DM_DIG_FA_TH1 && dm->bsta_state &&
+		    dm->support_ic_type != ODM_RTL8723D) {
+			*rx_gain_min = 0x1c;
+			igi = *rx_gain_min;
+			PHYDM_DBG(dm, DBG_DIG, "Beacon_num=%d,force igi=0x%x\n",
+				  dm->phy_dbg_info.num_qry_beacon_pkt, igi);
+		} else {
+			igi = phydm_new_igi_by_fa(dm, igi, fa_cnt, step);
+		}
+		#else
+		igi = phydm_new_igi_by_fa(dm, igi, fa_cnt, step);
+		#endif
+	} else {
+		/* @2 Before link */
+		PHYDM_DBG(dm, DBG_DIG, "Adjust IGI before link\n");
+
+		if (first_dis_connect) {
+			igi = dig_t->dm_dig_min;
+			PHYDM_DBG(dm, DBG_DIG,
+				  "First disconnect:foce IGI to lower bound\n");
+		} else {
+			PHYDM_DBG(dm, DBG_DIG, "Pre_IGI=((0x%x)), FA=((%d))\n",
+				  igi, fa_cnt);
+
+			igi = phydm_new_igi_by_fa(dm, igi, fa_cnt, step);
+		}
+	}
+	/*@Check IGI by dyn-upper/lower bound */
+	if (igi < *rx_gain_min)
+		igi = *rx_gain_min;
+
+	if (igi > *rx_gain_max)
+		igi = *rx_gain_max;
+
+	PHYDM_DBG(dm, DBG_DIG, "fa_cnt = %d, IGI: 0x%x -> 0x%x\n",
+		  fa_cnt, cur_igi, igi);
+
+	return igi;
+}
+
+/*@callback function triggered by SW timer*/
+void phydm_tdma_dig_cbk(void *dm_void)
+{
+#if (RTL8198F_SUPPORT || RTL8822C_SUPPORT || RTL8814B_SUPPORT)
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
+
+	if (phydm_dig_abort(dm) || (dm->original_dig_restore))
+		return;
+	/*@
+	 *PHYDM_DBG(dm, DBG_DIG, "timer callback =======> tdma_dig_state=%d\n");
+	 *	  dig_t->tdma_dig_state);
+	 *PHYDM_DBG(dm, DBG_DIG, "tdma_h_igi=0x%x, tdma_l_igi=0x%x\n",
+	 *	  dig_t->cur_ig_value_tdma,
+	 *	  dig_t->low_ig_value);
+	 */
+	phydm_tdma_fa_cnt_chk(dm);
+
+	/*@prevent dumb*/
+	if (dm->tdma_dig_state_number < 2)
+		dm->tdma_dig_state_number = 2;
+
+	/*@update state*/
+	dig_t->tdma_dig_cnt++;
+	dig_t->tdma_dig_state = dig_t->tdma_dig_cnt % dm->tdma_dig_state_number;
+
+	/*@
+	 *PHYDM_DBG(dm, DBG_DIG, "enter state %d, dig count %d\n",
+	 *	  dig_t->tdma_dig_state, dig_t->tdma_dig_cnt);
+	 */
+
+	if (dig_t->tdma_dig_state == TDMA_DIG_LOW_STATE)
+		odm_write_dig(dm, dig_t->low_ig_value);
+	else if (dig_t->tdma_dig_state >= TDMA_DIG_HIGH_STATE)
+		odm_write_dig(dm, dig_t->cur_ig_value_tdma);
+
+	odm_set_timer(dm, &dm->tdma_dig_timer, dm->tdma_dig_timer_ms);
+#endif
+}
+
+/*@============================================================*/
+/*@FASLE ALARM CHECK*/
+/*@============================================================*/
+void phydm_tdma_fa_cnt_chk(void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct phydm_fa_struct *falm_cnt = &dm->false_alm_cnt;
+	struct phydm_fa_acc_struct *fa_t_acc, *fa_t_acc_low;
+	struct phydm_dig_struct *dig_t = NULL;
+	boolean rssi_dump_en = false;
+	u32 timestamp = 0;
+	u8 states_per_block = 0;
+	u8 cur_tdma_dig_state = 0;
+	u32 start_th = 0;
+	u8 state_diff = 0;
+	u32 tdma_dig_block_period_ms = 0;
+	u32 tdma_dig_block_cnt_thd = 0;
+	u32 timestamp_diff = 0;
+
+	if (!(dm->support_ic_type &
+	    (ODM_RTL8198F | ODM_RTL8822C | ODM_RTL8814B))) {
+		PHYDM_DBG(dm, DBG_DIG, "Not 98F/22C/14B\n");
+		return;
+	}
+
+	fa_t_acc = &dm->false_alm_cnt_acc;
+	fa_t_acc_low = &dm->false_alm_cnt_acc_low;
+	dig_t = &dm->dm_dig_table;
+	states_per_block = dm->tdma_dig_state_number;
+
+	/*@calculate duration of a tdma block*/
+	tdma_dig_block_period_ms = dm->tdma_dig_timer_ms * states_per_block;
+
+	/*@
+	 *caution!ONE_SEC_MS must be divisible by tdma_dig_block_period_ms,
+	 *or FA will be fewer.
+	 */
+	tdma_dig_block_cnt_thd = ONE_SEC_MS / tdma_dig_block_period_ms;
+
+	/*@tdma_dig_state == 0, collect H-state FA, else, collect L-state FA*/
+	if (dig_t->tdma_dig_state == TDMA_DIG_LOW_STATE)
+		cur_tdma_dig_state = TDMA_DIG_LOW_STATE;
+	else if (dig_t->tdma_dig_state >= TDMA_DIG_HIGH_STATE)
+		cur_tdma_dig_state = TDMA_DIG_HIGH_STATE;
+	/*@
+	 *PHYDM_DBG(dm, DBG_DIG, "in state %d, dig count %d\n",
+	 *	  cur_tdma_dig_state, dig_t->tdma_dig_cnt);
+	 */
+	if (cur_tdma_dig_state == 0) {
+		/*@L-state indicates next block*/
+		dig_t->tdma_dig_block_cnt++;
+
+		/*@1sec dump check*/
+		if (dig_t->tdma_dig_block_cnt >= tdma_dig_block_cnt_thd)
+			rssi_dump_en = true;
+
+		/*@
+		 *PHYDM_DBG(dm, DBG_DIG,"[L-state] tdma_dig_block_cnt=%d\n",
+		 *	  dig_t->tdma_dig_block_cnt);
+		 */
+
+		/*@collect FA till this block end*/
+		phydm_false_alarm_counter_statistics(dm);
+		phydm_fa_cnt_acc(dm, rssi_dump_en, cur_tdma_dig_state);
+		/*@1s L-FA collect end*/
+
+		/*@1sec dump reached*/
+		if (rssi_dump_en) {
+			/*@L-DIG*/
+			phydm_noisy_detection(dm);
+			#ifdef PHYDM_SUPPORT_CCKPD
+			phydm_cck_pd_th(dm);
+			#endif
+			PHYDM_DBG(dm, DBG_DIG, "run tdma L-state dig ====>\n");
+			phydm_tdma_low_dig(dm);
+			PHYDM_DBG(dm, DBG_DIG, "\n\n");
+		}
+	} else if (cur_tdma_dig_state == 1) {
+		/*@1sec dump check*/
+		if (dig_t->tdma_dig_block_cnt >= tdma_dig_block_cnt_thd)
+			rssi_dump_en = true;
+
+		/*@
+		 *PHYDM_DBG(dm, DBG_DIG,"[H-state] tdma_dig_block_cnt=%d\n",
+		 *	  dig_t->tdma_dig_block_cnt);
+		 */
+
+		/*@collect FA till this block end*/
+		phydm_false_alarm_counter_statistics(dm);
+		phydm_fa_cnt_acc(dm, rssi_dump_en, cur_tdma_dig_state);
+		/*@1s H-FA collect end*/
+
+		/*@1sec dump reached*/
+		state_diff = dm->tdma_dig_state_number - dig_t->tdma_dig_state;
+		if (rssi_dump_en && (state_diff == 1)) {
+			/*@H-DIG*/
+			phydm_noisy_detection(dm);
+			#ifdef PHYDM_SUPPORT_CCKPD
+			phydm_cck_pd_th(dm);
+			#endif
+			PHYDM_DBG(dm, DBG_DIG, "run tdma H-state dig ====>\n");
+			phydm_tdma_high_dig(dm);
+			PHYDM_DBG(dm, DBG_DIG, "\n\n");
+			PHYDM_DBG(dm, DBG_DIG, "1 sec reached, is_linked=%d\n",
+				  dm->is_linked);
+			PHYDM_DBG(dm, DBG_DIG, "1 sec L-CCA=%d, L-FA=%d\n",
+				  fa_t_acc_low->cnt_cca_all_1sec,
+				  fa_t_acc_low->cnt_all_1sec);
+			PHYDM_DBG(dm, DBG_DIG, "1 sec H-CCA=%d, H-FA=%d\n",
+				  fa_t_acc->cnt_cca_all_1sec,
+				  fa_t_acc->cnt_all_1sec);
+			PHYDM_DBG(dm, DBG_DIG,
+				  "1 sec TOTAL-CCA=%d, TOTAL-FA=%d\n\n",
+				  fa_t_acc->cnt_cca_all +
+				  fa_t_acc_low->cnt_cca_all,
+				  fa_t_acc->cnt_all + fa_t_acc_low->cnt_all);
+
+			/*@Reset AccFalseAlarmCounterStatistics */
+			phydm_false_alarm_counter_acc_reset(dm);
+			dig_t->tdma_dig_block_cnt = 0;
+		}
+	}
+	/*@Reset FalseAlarmCounterStatistics */
+	phydm_false_alarm_counter_reset(dm);
+}
+
+void phydm_tdma_low_dig(void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
+	struct phydm_fa_struct *falm_cnt = &dm->false_alm_cnt;
+	struct phydm_fa_acc_struct *falm_cnt_acc = &dm->false_alm_cnt_acc_low;
+#ifdef CFG_DIG_DAMPING_CHK
+	struct phydm_dig_recorder_strcut *dig_rc = &dig_t->dig_recorder_t;
+#endif
+	boolean first_connect, first_disconnect;
+	u8 igi = dig_t->cur_ig_value;
+	u8 new_igi = 0x20;
+	u8 tdma_l_igi = dig_t->low_ig_value;
+	u8 tdma_l_dym_min = dig_t->tdma_rx_gain_min[TDMA_DIG_LOW_STATE];
+	u8 tdma_l_dym_max = dig_t->tdma_rx_gain_max[TDMA_DIG_LOW_STATE];
+	u32 fa_cnt = falm_cnt->cnt_all;
+	boolean dfs_mode_en = false, is_performance = true;
+	u8 rssi_min = dm->rssi_min;
+	u8 igi_upper_rssi_min = 0;
+	u8 offset = 15;
+
+	if (!(dm->original_dig_restore)) {
+		if (tdma_l_igi == 0)
+			tdma_l_igi = igi;
+
+		fa_cnt = falm_cnt_acc->cnt_all_1sec;
+	}
+
+	if (phydm_dig_abort(dm)) {
+		dig_t->low_ig_value = phydm_get_igi(dm, BB_PATH_A);
+		return;
+	}
+
+	/*@Mode Decision*/
+	dfs_mode_en = false;
+	is_performance = true;
+
+	/* @Abs Boundary Decision*/
+	dig_t->dm_dig_max = DIG_MAX_COVERAGR; //0x26
+	dig_t->dm_dig_min = DIG_MIN_PERFORMANCE; //0x20
+	dig_t->dig_max_of_min = DIG_MAX_OF_MIN_COVERAGE; //0x22
+
+	if (dfs_mode_en) {
+		if (*dm->band_width == CHANNEL_WIDTH_20)
+			dig_t->dm_dig_min = DIG_MIN_DFS + 2;
+		else
+			dig_t->dm_dig_min = DIG_MIN_DFS;
+
+	} else {
+		if (dm->support_ic_type &
+		    (ODM_RTL8814A | ODM_RTL8812 | ODM_RTL8821 | ODM_RTL8822B))
+			dig_t->dm_dig_min = 0x1c;
+		else if (dm->support_ic_type & ODM_RTL8197F)
+			dig_t->dm_dig_min = 0x1e; /*@For HW setting*/
+	}
+
+	PHYDM_DBG(dm, DBG_DIG, "Abs{Max, Min}={0x%x, 0x%x}, Max_of_min=0x%x\n",
+		  dig_t->dm_dig_max, dig_t->dm_dig_min, dig_t->dig_max_of_min);
+
+	/* @Dyn Boundary by RSSI*/
+	if (!dm->is_linked) {
+		/*@if no link, always stay at lower bound*/
+		tdma_l_dym_max = 0x26;
+		tdma_l_dym_min = dig_t->dm_dig_min;
+
+		PHYDM_DBG(dm, DBG_DIG, "No-Link, Dyn{Max, Min}={0x%x, 0x%x}\n",
+			  tdma_l_dym_max, tdma_l_dym_min);
+	} else {
+		PHYDM_DBG(dm, DBG_DIG, "rssi_min=%d, ofst=%d\n",
+			  dm->rssi_min, offset);
+
+		/* @DIG lower bound in L-state*/
+		tdma_l_dym_min = dig_t->dm_dig_min;
+
+#ifdef CFG_DIG_DAMPING_CHK
+		/*@Limit Dyn min by damping*/
+		if (dig_t->dig_dl_en &&
+		    dig_rc->damping_limit_en &&
+		    tdma_l_dym_min < dig_rc->damping_limit_val) {
+			PHYDM_DBG(dm, DBG_DIG,
+				  "[Limit by Damping] dyn_min=0x%x -> 0x%x\n",
+				  tdma_l_dym_min, dig_rc->damping_limit_val);
+
+			tdma_l_dym_min = dig_rc->damping_limit_val;
+		}
+#endif
+
+		/*@DIG upper bound in L-state*/
+		igi_upper_rssi_min = rssi_min + offset;
+		if (igi_upper_rssi_min > dig_t->dm_dig_max)
+			tdma_l_dym_max = dig_t->dm_dig_max;
+		else if (igi_upper_rssi_min < dig_t->dm_dig_min)
+			tdma_l_dym_max = dig_t->dm_dig_min;
+		else
+			tdma_l_dym_max = igi_upper_rssi_min;
+
+		/* @1 Force Lower Bound for AntDiv */
+		/*@
+		 *if (!dm->is_one_entry_only &&
+		 *(dm->support_ability & ODM_BB_ANT_DIV) &&
+		 *(dm->ant_div_type == CG_TRX_HW_ANTDIV ||
+		 *dm->ant_div_type == CG_TRX_SMART_ANTDIV)) {
+		 *if (dig_t->ant_div_rssi_max > dig_t->dig_max_of_min)
+		 *	dig_t->rx_gain_range_min = dig_t->dig_max_of_min;
+		 *else
+		 *	dig_t->rx_gain_range_min = (u8)dig_t->ant_div_rssi_max;
+		 *
+		 *PHYDM_DBG(dm, DBG_DIG, "Force Dyn-Min=0x%x, RSSI_max=0x%x\n",
+		 *	  dig_t->rx_gain_range_min, dig_t->ant_div_rssi_max);
+		 *}
+		 */
+
+		PHYDM_DBG(dm, DBG_DIG, "Dyn{Max, Min}={0x%x, 0x%x}\n",
+			  tdma_l_dym_max, tdma_l_dym_min);
+	}
+
+	/*@Abnormal Case Check*/
+	/*@Abnormal lower bound case*/
+	if (tdma_l_dym_min > tdma_l_dym_max)
+		tdma_l_dym_min = tdma_l_dym_max;
+
+	PHYDM_DBG(dm, DBG_DIG,
+		  "Abnoraml chk, force {Max, Min}={0x%x, 0x%x}\n",
+		  tdma_l_dym_max, tdma_l_dym_min);
+
+	/*@False Alarm Threshold Decision*/
+	phydm_fa_threshold_check(dm, dfs_mode_en);
+
+	/*@Adjust Initial Gain by False Alarm*/
+	/*Select new IGI by FA */
+	if (!(dm->original_dig_restore)) {
+		tdma_l_igi = get_new_igi_bound(dm, tdma_l_igi, fa_cnt,
+					       &tdma_l_dym_max,
+					       &tdma_l_dym_min,
+					       dfs_mode_en);
+	} else {
+		new_igi = phydm_get_new_igi(dm, igi, fa_cnt, dfs_mode_en);
+	}
+
+	/*Update status*/
+	if (!(dm->original_dig_restore)) {
+		dig_t->low_ig_value = tdma_l_igi;
+		dig_t->tdma_rx_gain_min[TDMA_DIG_LOW_STATE] = tdma_l_dym_min;
+		dig_t->tdma_rx_gain_max[TDMA_DIG_LOW_STATE] = tdma_l_dym_max;
+#if 0
+		/*odm_write_dig(dm, tdma_l_igi);*/
+#endif
+	} else {
+		odm_write_dig(dm, new_igi);
+	}
+
+	dig_t->is_media_connect = dm->is_linked;
+}
+
+void phydm_tdma_high_dig(void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
+	struct phydm_fa_struct *falm_cnt = &dm->false_alm_cnt;
+	struct phydm_fa_acc_struct *falm_cnt_acc = &dm->false_alm_cnt_acc;
+#ifdef CFG_DIG_DAMPING_CHK
+	struct phydm_dig_recorder_strcut *dig_rc = &dig_t->dig_recorder_t;
+#endif
+	boolean first_connect, first_disconnect;
+	u8 igi = dig_t->cur_ig_value;
+	u8 new_igi = 0x20;
+	u8 tdma_h_igi = dig_t->cur_ig_value_tdma;
+	u8 tdma_h_dym_min = dig_t->tdma_rx_gain_min[TDMA_DIG_HIGH_STATE];
+	u8 tdma_h_dym_max = dig_t->tdma_rx_gain_max[TDMA_DIG_HIGH_STATE];
+	u32 fa_cnt = falm_cnt->cnt_all;
+	boolean dfs_mode_en = false, is_performance = true;
+	u8 rssi_min = dm->rssi_min;
+	u8 igi_upper_rssi_min = 0;
+	u8 offset = 15;
+
+	if (!(dm->original_dig_restore)) {
+		if (tdma_h_igi == 0)
+			tdma_h_igi = igi;
+
+		fa_cnt = falm_cnt_acc->cnt_all_1sec;
+	}
+
+	if (phydm_dig_abort(dm)) {
+		dig_t->cur_ig_value_tdma = phydm_get_igi(dm, BB_PATH_A);
+		return;
+	}
+
+	/*@Mode Decision*/
+	dfs_mode_en = false;
+	is_performance = true;
+
+	/*@Abs Boundary Decision*/
+	dig_t->dig_max_of_min = DIG_MAX_OF_MIN_BALANCE_MODE; // 0x2a
+
+	if (!dm->is_linked) {
+		dig_t->dm_dig_max = DIG_MAX_COVERAGR;
+		dig_t->dm_dig_min = DIG_MIN_PERFORMANCE; // 0x20
+	} else if (dfs_mode_en) {
+		if (*dm->band_width == CHANNEL_WIDTH_20)
+			dig_t->dm_dig_min = DIG_MIN_DFS + 2;
+		else
+			dig_t->dm_dig_min = DIG_MIN_DFS;
+
+		dig_t->dig_max_of_min = DIG_MAX_OF_MIN_BALANCE_MODE;
+		dig_t->dm_dig_max = DIG_MAX_BALANCE_MODE;
+	} else {
+		if (*dm->bb_op_mode == PHYDM_BALANCE_MODE) {
+		/*service > 2 devices*/
+			dig_t->dm_dig_max = DIG_MAX_BALANCE_MODE;
+			#if (DIG_HW == 1)
+			dig_t->dig_max_of_min = DIG_MIN_COVERAGE;
+			#else
+			dig_t->dig_max_of_min = DIG_MAX_OF_MIN_BALANCE_MODE;
+			#endif
+		} else if (*dm->bb_op_mode == PHYDM_PERFORMANCE_MODE) {
+		/*service 1 devices*/
+			dig_t->dm_dig_max = DIG_MAX_PERFORMANCE_MODE;
+			dig_t->dig_max_of_min = DIG_MAX_OF_MIN_PERFORMANCE_MODE;
+		}
+
+		if (dm->support_ic_type &
+		    (ODM_RTL8814A | ODM_RTL8812 | ODM_RTL8821 | ODM_RTL8822B))
+			dig_t->dm_dig_min = 0x1c;
+		else if (dm->support_ic_type & ODM_RTL8197F)
+			dig_t->dm_dig_min = 0x1e; /*@For HW setting*/
+		else
+			dig_t->dm_dig_min = DIG_MIN_PERFORMANCE;
+	}
+	PHYDM_DBG(dm, DBG_DIG, "Abs{Max, Min}={0x%x, 0x%x}, Max_of_min=0x%x\n",
+		  dig_t->dm_dig_max, dig_t->dm_dig_min, dig_t->dig_max_of_min);
+
+	/*@Dyn Boundary by RSSI*/
+	if (!dm->is_linked) {
+		/*@if no link, always stay at lower bound*/
+		tdma_h_dym_max = dig_t->dig_max_of_min;
+		tdma_h_dym_min = dig_t->dm_dig_min;
+
+		PHYDM_DBG(dm, DBG_DIG, "No-Link, Dyn{Max, Min}={0x%x, 0x%x}\n",
+			  tdma_h_dym_max, tdma_h_dym_min);
+	} else {
+		PHYDM_DBG(dm, DBG_DIG, "rssi_min=%d, ofst=%d\n",
+			  dm->rssi_min, offset);
+
+		/* @DIG lower bound in H-state*/
+		if (rssi_min < dig_t->dm_dig_min)
+			tdma_h_dym_min = dig_t->dm_dig_min;
+		else
+			tdma_h_dym_min = rssi_min; // turbo not considered yet
+
+#ifdef CFG_DIG_DAMPING_CHK
+		/*@Limit Dyn min by damping*/
+		if (dig_t->dig_dl_en &&
+		    dig_rc->damping_limit_en &&
+		    tdma_h_dym_min < dig_rc->damping_limit_val) {
+			PHYDM_DBG(dm, DBG_DIG,
+				  "[Limit by Damping] dyn_min=0x%x -> 0x%x\n",
+				  tdma_h_dym_min, dig_rc->damping_limit_val);
+
+			tdma_h_dym_min = dig_rc->damping_limit_val;
+		}
+#endif
+
+		/*@DIG upper bound in H-state*/
+		igi_upper_rssi_min = rssi_min + offset;
+		if (igi_upper_rssi_min > dig_t->dm_dig_max)
+			tdma_h_dym_max = dig_t->dm_dig_max;
+		else
+			tdma_h_dym_max = igi_upper_rssi_min;
+
+		/* @1 Force Lower Bound for AntDiv */
+		/*@
+		 *if (!dm->is_one_entry_only &&
+		 *(dm->support_ability & ODM_BB_ANT_DIV) &&
+		 *(dm->ant_div_type == CG_TRX_HW_ANTDIV ||
+		 *dm->ant_div_type == CG_TRX_SMART_ANTDIV)) {
+		 *	if (dig_t->ant_div_rssi_max > dig_t->dig_max_of_min)
+		 *	dig_t->rx_gain_range_min = dig_t->dig_max_of_min;
+		 *	else
+		 *	dig_t->rx_gain_range_min = (u8)dig_t->ant_div_rssi_max;
+		 */
+		/*@
+		 *PHYDM_DBG(dm, DBG_DIG, "Force Dyn-Min=0x%x, RSSI_max=0x%x\n",
+		 *	  dig_t->rx_gain_range_min, dig_t->ant_div_rssi_max);
+		 *}
+		 */
+		PHYDM_DBG(dm, DBG_DIG, "Dyn{Max, Min}={0x%x, 0x%x}\n",
+			  tdma_h_dym_max, tdma_h_dym_min);
+	}
+
+	/*@Abnormal Case Check*/
+	/*@Abnormal low higher bound case*/
+	if (tdma_h_dym_max < dig_t->dm_dig_min)
+		tdma_h_dym_max = dig_t->dm_dig_min;
+	/*@Abnormal lower bound case*/
+	if (tdma_h_dym_min > tdma_h_dym_max)
+		tdma_h_dym_min = tdma_h_dym_max;
+
+	PHYDM_DBG(dm, DBG_DIG, "Abnoraml chk, force {Max, Min}={0x%x, 0x%x}\n",
+		  tdma_h_dym_max, tdma_h_dym_min);
+
+	/*@False Alarm Threshold Decision*/
+	phydm_fa_threshold_check(dm, dfs_mode_en);
+
+	/*@Adjust Initial Gain by False Alarm*/
+	/*Select new IGI by FA */
+	if (!(dm->original_dig_restore)) {
+		tdma_h_igi = get_new_igi_bound(dm, tdma_h_igi, fa_cnt,
+					       &tdma_h_dym_max,
+					       &tdma_h_dym_min,
+					       dfs_mode_en);
+	} else {
+		new_igi = phydm_get_new_igi(dm, igi, fa_cnt, dfs_mode_en);
+	}
+
+	/*Update status*/
+	if (!(dm->original_dig_restore)) {
+		dig_t->cur_ig_value_tdma = tdma_h_igi;
+		dig_t->tdma_rx_gain_min[TDMA_DIG_HIGH_STATE] = tdma_h_dym_min;
+		dig_t->tdma_rx_gain_max[TDMA_DIG_HIGH_STATE] = tdma_h_dym_max;
+#if 0
+		/*odm_write_dig(dm, tdma_h_igi);*/
+#endif
+	} else {
+		odm_write_dig(dm, new_igi);
+	}
+
+	dig_t->is_media_connect = dm->is_linked;
+}
+
+void phydm_fa_cnt_acc(void *dm_void, boolean rssi_dump_en,
+		      u8 cur_tdma_dig_state)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct phydm_fa_struct *falm_cnt = NULL;
+	struct phydm_fa_acc_struct *falm_cnt_acc = NULL;
+	struct phydm_dig_struct *dig_t = NULL;
+	u8 factor_num = 0;
+	u8 factor_denum = 1;
+	u8 total_state_number;
+
+	dig_t = &dm->dm_dig_table;
+	falm_cnt = &dm->false_alm_cnt;
+#ifdef IS_USE_NEW_TDMA
+	if (cur_tdma_dig_state == TDMA_DIG_LOW_STATE)
+		falm_cnt_acc = &dm->false_alm_cnt_acc_low;
+	else if (cur_tdma_dig_state == TDMA_DIG_HIGH_STATE)
+#endif
+		falm_cnt_acc = &dm->false_alm_cnt_acc;
+	/*@
+	 *PHYDM_DBG(dm, DBG_DIG,
+	 *	  "[%s] ==> dig_state=%d, one_sec=%d\n", __func__,
+	 *	  cur_tdma_dig_state, rssi_dump_en);
+	 */
+	falm_cnt_acc->cnt_parity_fail += falm_cnt->cnt_parity_fail;
+	falm_cnt_acc->cnt_rate_illegal += falm_cnt->cnt_rate_illegal;
+	falm_cnt_acc->cnt_crc8_fail += falm_cnt->cnt_crc8_fail;
+	falm_cnt_acc->cnt_mcs_fail += falm_cnt->cnt_mcs_fail;
+	falm_cnt_acc->cnt_ofdm_fail += falm_cnt->cnt_ofdm_fail;
+	falm_cnt_acc->cnt_cck_fail += falm_cnt->cnt_cck_fail;
+	falm_cnt_acc->cnt_all += falm_cnt->cnt_all;
+	falm_cnt_acc->cnt_fast_fsync += falm_cnt->cnt_fast_fsync;
+	falm_cnt_acc->cnt_sb_search_fail += falm_cnt->cnt_sb_search_fail;
+	falm_cnt_acc->cnt_ofdm_cca += falm_cnt->cnt_ofdm_cca;
+	falm_cnt_acc->cnt_cck_cca += falm_cnt->cnt_cck_cca;
+	falm_cnt_acc->cnt_cca_all += falm_cnt->cnt_cca_all;
+	falm_cnt_acc->cnt_cck_crc32_error += falm_cnt->cnt_cck_crc32_error;
+	falm_cnt_acc->cnt_cck_crc32_ok += falm_cnt->cnt_cck_crc32_ok;
+	falm_cnt_acc->cnt_ofdm_crc32_error += falm_cnt->cnt_ofdm_crc32_error;
+	falm_cnt_acc->cnt_ofdm_crc32_ok += falm_cnt->cnt_ofdm_crc32_ok;
+	falm_cnt_acc->cnt_ht_crc32_error += falm_cnt->cnt_ht_crc32_error;
+	falm_cnt_acc->cnt_ht_crc32_ok += falm_cnt->cnt_ht_crc32_ok;
+	falm_cnt_acc->cnt_vht_crc32_error += falm_cnt->cnt_vht_crc32_error;
+	falm_cnt_acc->cnt_vht_crc32_ok += falm_cnt->cnt_vht_crc32_ok;
+	falm_cnt_acc->cnt_crc32_error_all += falm_cnt->cnt_crc32_error_all;
+	falm_cnt_acc->cnt_crc32_ok_all += falm_cnt->cnt_crc32_ok_all;
+
+	/*@
+	 *PHYDM_DBG(dm, DBG_DIG,
+	 *	"[CCA Cnt]     {CCK, OFDM, Total} = {%d, %d, %d}\n",
+	 *	falm_cnt->cnt_cck_cca,
+	 *	falm_cnt->cnt_ofdm_cca,
+	 *	falm_cnt->cnt_cca_all);
+	 *PHYDM_DBG(dm, DBG_DIG,
+	 *	"[FA Cnt]      {CCK, OFDM, Total} = {%d, %d, %d}\n",
+	 *	falm_cnt->cnt_cck_fail,
+	 *	falm_cnt->cnt_ofdm_fail,
+	 *	falm_cnt->cnt_all);
+	 */
+	if (rssi_dump_en == 1) {
+		total_state_number = dm->tdma_dig_state_number;
+
+		if (cur_tdma_dig_state == TDMA_DIG_HIGH_STATE) {
+			factor_num = total_state_number;
+			factor_denum = total_state_number - 1;
+		} else if (cur_tdma_dig_state == TDMA_DIG_LOW_STATE) {
+			factor_num = total_state_number;
+			factor_denum = 1;
+		}
+
+		falm_cnt_acc->cnt_all_1sec =
+			falm_cnt_acc->cnt_all * factor_num / factor_denum;
+		falm_cnt_acc->cnt_cca_all_1sec =
+			falm_cnt_acc->cnt_cca_all * factor_num / factor_denum;
+		falm_cnt_acc->cnt_cck_fail_1sec =
+			falm_cnt_acc->cnt_cck_fail * factor_num / factor_denum;
+		/*@
+		 *PHYDM_DBG(dm, DBG_DIG,
+		 *	"[ACC CCA Cnt] {CCK, OFDM, Total} = {%d, %d, %d}\n",
+		 *	falm_cnt_acc->cnt_cck_cca,
+		 *	falm_cnt_acc->cnt_ofdm_cca,
+		 *	falm_cnt_acc->cnt_cca_all);
+		 *PHYDM_DBG(dm, DBG_DIG,
+		 *	"[ACC FA Cnt]  {CCK, OFDM, Total} = {%d, %d, %d}\n\n",
+		 *	falm_cnt_acc->cnt_cck_fail,
+		 *	falm_cnt_acc->cnt_ofdm_fail,
+		 *	falm_cnt_acc->cnt_all);
+		 */
+	}
+}
+#endif /*@#ifdef IS_USE_NEW_TDMA*/
+#endif /*@#ifdef PHYDM_TDMA_DIG_SUPPORT*/
+
+void phydm_dig_debug(void *dm_void, char input[][16], u32 *_used, char *output,
+		     u32 *_out_len)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
+	char help[] = "-h";
+	char monitor[] = "-m";
+	u32 var1[10] = {0};
+	u32 used = *_used;
+	u32 out_len = *_out_len;
+	u8 i;
+
+	if ((strcmp(input[1], help) == 0)) {
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "{0} {en} fa_th[0] fa_th[1] fa_th[2]\n");
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "{1} {Damping Limit en}\n");
+	} else if ((strcmp(input[1], monitor) == 0)) {
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "Read DIG fa_th[0:2]= {%d, %d, %d}\n", dig_t->fa_th[0],
+			 dig_t->fa_th[1], dig_t->fa_th[2]);
+
+	} else {
+		PHYDM_SSCANF(input[1], DCMD_DECIMAL, &var1[0]);
+
+		for (i = 1; i < 10; i++)
+			PHYDM_SSCANF(input[i + 1], DCMD_DECIMAL, &var1[i]);
+
+		if (var1[0] == 0) {
+			if (var1[1] == 1) {
+				dig_t->is_dbg_fa_th = true;
+				dig_t->fa_th[0] = (u16)var1[2];
+				dig_t->fa_th[1] = (u16)var1[3];
+				dig_t->fa_th[2] = (u16)var1[4];
+
+				PDM_SNPF(out_len, used, output + used,
+					 out_len - used,
+					 "Set DIG fa_th[0:2]= {%d, %d, %d}\n",
+					 dig_t->fa_th[0], dig_t->fa_th[1],
+					 dig_t->fa_th[2]);
+			} else {
+				dig_t->is_dbg_fa_th = false;
+			}
+		}
+		#ifdef CFG_DIG_DAMPING_CHK
+		else if (var1[0] == 1) {
+			dig_t->dig_dl_en = (u8)var1[1];
+			/*@*/
+		}
+		#endif
+	}
+	*_used = used;
+	*_out_len = out_len;
+}
+
+#ifdef CONFIG_MCC_DM
+#if (RTL8822B_SUPPORT)
+void phydm_mcc_igi_clr(void *dm_void, u8 clr_port)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct _phydm_mcc_dm_ *mcc_dm = &dm->mcc_dm;
+	mcc_dm->mcc_rssi[clr_port] = 0xff;
+	mcc_dm->mcc_dm_val[0][clr_port] = 0xff; /* 0xc50 clr */
+	mcc_dm->mcc_dm_val[1][clr_port] = 0xff; /* 0xe50 clr */
+}
+
+void phydm_mcc_igi_chk(void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct _phydm_mcc_dm_ *mcc_dm = &dm->mcc_dm;
+
+	if (mcc_dm->mcc_dm_val[0][0] == 0xff &&
+	    mcc_dm->mcc_dm_val[0][1] == 0xff) {
+		mcc_dm->mcc_dm_reg[0] = 0xffff;
+		mcc_dm->mcc_reg_id[0] = 0xff;
+	}
+	if (mcc_dm->mcc_dm_val[1][0] == 0xff &&
+	    mcc_dm->mcc_dm_val[1][1] == 0xff) {
+		mcc_dm->mcc_dm_reg[1] = 0xffff;
+		mcc_dm->mcc_reg_id[1] = 0xff;
+	}
+}
+
+void phydm_mcc_igi_cal(void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct _phydm_mcc_dm_ *mcc_dm = &dm->mcc_dm;
+	struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
+	u8	shift = 0;
+	u8	igi_val0, igi_val1;
+	if (mcc_dm->mcc_rssi[0] == 0xff)
+		phydm_mcc_igi_clr(dm, 0);
+	if (mcc_dm->mcc_rssi[1] == 0xff)
+		phydm_mcc_igi_clr(dm, 1);
+	phydm_mcc_igi_chk(dm);
+	igi_val0 = mcc_dm->mcc_rssi[0] - shift;
+	igi_val1 = mcc_dm->mcc_rssi[1] - shift;
+	phydm_fill_mcccmd(dm, 0, 0xc50, igi_val0, igi_val1);
+	phydm_fill_mcccmd(dm, 1, 0xe50, igi_val0, igi_val1);
+	PHYDM_DBG(dm, DBG_COMP_MCC, "RSSI_min: %d %d, MCC_igi: %d %d\n",
+		  mcc_dm->mcc_rssi[0], mcc_dm->mcc_rssi[1],
+		  mcc_dm->mcc_dm_val[0][0], mcc_dm->mcc_dm_val[0][1]);
+}
+#endif /*#if (RTL8822B_SUPPORT)*/
+#endif /*#ifdef CONFIG_MCC_DM*/
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/phydm_dig.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/phydm_dig.h
--- linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/phydm_dig.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/phydm_dig.h	2020-04-10 16:35:06.824660441 +0300
@@ -0,0 +1,315 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017  Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * The full GNU General Public License is included in this distribution in the
+ * file called LICENSE.
+ *
+ * Contact Information:
+ * wlanfae <wlanfae@realtek.com>
+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
+ * Hsinchu 300, Taiwan.
+ *
+ * Larry Finger <Larry.Finger@lwfinger.net>
+ *
+ *****************************************************************************/
+
+#ifndef __PHYDMDIG_H__
+#define __PHYDMDIG_H__
+
+#define DIG_VERSION "2.3"
+
+#define	DIG_HW		0
+#define DIG_LIMIT_PERIOD 60 /*@60 sec*/
+
+/*@--------------------Define ---------------------------------------*/
+
+/*@=== [DIG Boundary] ========================================*/
+/*@DIG coverage mode*/
+#define	DIG_MAX_COVERAGR		0x26
+#define	DIG_MIN_COVERAGE		0x1c
+#define	DIG_MAX_OF_MIN_COVERAGE		0x22
+
+/*@[DIG Balance mode]*/
+#if (DIG_HW == 1)
+#define	DIG_MAX_BALANCE_MODE		0x32
+#else
+#define	DIG_MAX_BALANCE_MODE		0x3e
+#endif
+#define	DIG_MAX_OF_MIN_BALANCE_MODE	0x2a
+
+/*@[DIG Performance mode]*/
+#define	DIG_MAX_PERFORMANCE_MODE	0x5a
+#define	DIG_MAX_OF_MIN_PERFORMANCE_MODE	0x40	/*@[WLANBB-871]*/
+#define	DIG_MIN_PERFORMANCE		0x20
+
+/*@DIG DFS function*/
+#define	DIG_MAX_DFS			0x28
+#define	DIG_MIN_DFS			0x20
+
+/*@DIG LPS function*/
+#define	DIG_MAX_LPS			0x3e
+#define	DIG_MIN_LPS			0x20
+
+#ifdef PHYDM_TDMA_DIG_SUPPORT
+#define DIG_NUM_OF_TDMA_STATES	2 /*@L, H state*/
+#endif
+
+/*@=== [DIG FA Threshold] ======================================*/
+
+/*Normal*/
+#define	DM_DIG_FA_TH0			500
+#define	DM_DIG_FA_TH1			750
+
+/*@LPS*/
+#define	DM_DIG_FA_TH0_LPS		4	/* @-> 4 lps */
+#define	DM_DIG_FA_TH1_LPS		15	/* @-> 15 lps */
+#define	DM_DIG_FA_TH2_LPS		30	/* @-> 30 lps */
+
+#define	RSSI_OFFSET_DIG_LPS		5
+#define DIG_RECORD_NUM			4
+
+/*@--------------------Enum-----------------------------------*/
+enum dig_goupcheck_level {
+	DIG_GOUPCHECK_LEVEL_0,
+	DIG_GOUPCHECK_LEVEL_1,
+	DIG_GOUPCHECK_LEVEL_2
+};
+
+enum phydm_dig_mode {
+	PHYDM_DIG_PERFORAMNCE_MODE	= 0,
+	PHYDM_DIG_COVERAGE_MODE		= 1,
+};
+
+#ifdef IS_USE_NEW_TDMA
+enum tdma_dig_timer {
+	INIT_TDMA_DIG_TIMMER,
+	CANCEL_TDMA_DIG_TIMMER,
+	RELEASE_TDMA_DIG_TIMMER
+};
+
+enum tdma_dig_state {
+	TDMA_DIG_LOW_STATE = 0,
+	TDMA_DIG_HIGH_STATE = 1,
+	NORMAL_DIG = 2
+};
+#endif
+
+/*@--------------------Define Struct-----------------------------------*/
+#ifdef CFG_DIG_DAMPING_CHK
+struct phydm_dig_recorder_strcut {
+	u8		igi_bitmap; /*@Don't add any new parameter before this*/
+	u8		igi_history[DIG_RECORD_NUM];
+	u32		fa_history[DIG_RECORD_NUM];
+	u8		damping_limit_en;
+	u8		damping_limit_val; /*@Limit IGI_dyn_min*/
+	u32		limit_time;
+	u8		limit_rssi;
+};
+#endif
+
+struct phydm_mcc_dig {
+	u8		mcc_rssi_A;
+	u8		mcc_rssi_B;
+};
+
+struct phydm_dig_struct {
+#ifdef CFG_DIG_DAMPING_CHK
+	struct phydm_dig_recorder_strcut dig_recorder_t;
+	u8		dig_dl_en; /*@damping limit function enable*/
+#endif
+	boolean		is_dbg_fa_th;
+	u8		cur_ig_value;
+	u8		rvrt_val;
+	u8		igi_backup;
+	u8		rx_gain_range_max;	/*@dig_dynamic_max*/
+	u8		rx_gain_range_min;	/*@dig_dynamic_min*/
+	u8		dm_dig_max;		/*@Absolutly upper bound*/
+	u8		dm_dig_min;		/*@Absolutly lower bound*/
+	u8		dig_max_of_min;		/*@Absolutly max of min*/
+	boolean		is_media_connect;
+	u32		ant_div_rssi_max;
+	u8		*is_p2p_in_process;
+	enum dig_goupcheck_level	go_up_chk_lv;
+	u16		fa_th[3];
+#if (RTL8822B_SUPPORT || RTL8197F_SUPPORT || RTL8821C_SUPPORT ||\
+	RTL8198F_SUPPORT || RTL8192F_SUPPORT || RTL8195B_SUPPORT ||\
+	RTL8822C_SUPPORT || RTL8814B_SUPPORT)
+	u8		rf_gain_idx;
+	u8		agc_table_idx;
+	u8		big_jump_lmt[16];
+	u8		enable_adjust_big_jump:1;
+	u8		big_jump_step1:3;
+	u8		big_jump_step2:2;
+	u8		big_jump_step3:2;
+#endif
+	u8		upcheck_init_val;
+	u8		lv0_ratio_reciprocal;
+	u8		lv1_ratio_reciprocal;
+#ifdef PHYDM_TDMA_DIG_SUPPORT
+	u8		cur_ig_value_tdma;
+	u8		low_ig_value;
+	u8		tdma_dig_state;	/*@To distinguish which state is now.(L-sate or H-state)*/
+	u8		tdma_dig_cnt;	/*@for phydm_tdma_dig_timer_check use*/
+	u8		pre_tdma_dig_cnt;
+	u8		sec_factor;
+	u32		cur_timestamp;
+	u32		pre_timestamp;
+	u32		fa_start_timestamp;
+	u32		fa_end_timestamp;
+	u32		fa_acc_1sec_timestamp;
+#ifdef IS_USE_NEW_TDMA
+	u8		tdma_dig_block_cnt;/*@for 1 second dump indicator use*/
+			/*@dynamic upper bound for L/H state*/
+	u8		tdma_rx_gain_max[DIG_NUM_OF_TDMA_STATES];
+			/*@dynamic lower bound for L/H state*/
+	u8		tdma_rx_gain_min[DIG_NUM_OF_TDMA_STATES];
+			/*To distinguish current state(L-sate or H-state)*/
+#endif
+#endif
+};
+
+struct phydm_fa_struct {
+	u32		cnt_parity_fail;
+	u32		cnt_rate_illegal;
+	u32		cnt_crc8_fail;
+	u32		cnt_crc8_fail_vht;
+	u32		cnt_mcs_fail;
+	u32		cnt_mcs_fail_vht;
+	u32		cnt_ofdm_fail;
+	u32		cnt_ofdm_fail_pre;	/* @For RTL8881A */
+	u32		cnt_cck_fail;
+	u32		cnt_all;
+	u32		cnt_all_pre;
+	u32		cnt_fast_fsync;
+	u32		cnt_sb_search_fail;
+	u32		cnt_ofdm_cca;
+	u32		cnt_cck_cca;
+	u32		cnt_cca_all;
+	u32		cnt_bw_usc;
+	u32		cnt_bw_lsc;
+	u32		cnt_cck_crc32_error;
+	u32		cnt_cck_crc32_ok;
+	u32		cnt_ofdm_crc32_error;
+	u32		cnt_ofdm_crc32_ok;
+	u32		cnt_ht_crc32_error;
+	u32		cnt_ht_crc32_ok;
+	u32		cnt_ht_crc32_error_agg;
+	u32		cnt_ht_crc32_ok_agg;
+	u32		cnt_vht_crc32_error;
+	u32		cnt_vht_crc32_ok;
+	u32		cnt_crc32_error_all;
+	u32		cnt_crc32_ok_all;
+	u32		time_fa_all;
+	boolean		cck_block_enable;
+	boolean		ofdm_block_enable;
+	u32		dbg_port0;
+	boolean		edcca_flag;
+};
+
+#ifdef PHYDM_TDMA_DIG_SUPPORT
+struct phydm_fa_acc_struct {
+	u32		cnt_parity_fail;
+	u32		cnt_rate_illegal;
+	u32		cnt_crc8_fail;
+	u32		cnt_mcs_fail;
+	u32		cnt_ofdm_fail;
+	u32		cnt_ofdm_fail_pre;	/*@For RTL8881A*/
+	u32		cnt_cck_fail;
+	u32		cnt_all;
+	u32		cnt_all_pre;
+	u32		cnt_fast_fsync;
+	u32		cnt_sb_search_fail;
+	u32		cnt_ofdm_cca;
+	u32		cnt_cck_cca;
+	u32		cnt_cca_all;
+	u32		cnt_cck_crc32_error;
+	u32		cnt_cck_crc32_ok;
+	u32		cnt_ofdm_crc32_error;
+	u32		cnt_ofdm_crc32_ok;
+	u32		cnt_ht_crc32_error;
+	u32		cnt_ht_crc32_ok;
+	u32		cnt_vht_crc32_error;
+	u32		cnt_vht_crc32_ok;
+	u32		cnt_crc32_error_all;
+	u32		cnt_crc32_ok_all;
+	u32		cnt_all_1sec;
+	u32		cnt_cca_all_1sec;
+	u32		cnt_cck_fail_1sec;
+};
+
+#endif	/*@#ifdef PHYDM_TDMA_DIG_SUPPORT*/
+
+/*@--------------------Function declaration-----------------------------*/
+void odm_write_dig(void *dm_void, u8 current_igi);
+
+u8 phydm_get_igi(void *dm_void, enum bb_path path);
+
+void phydm_set_dig_val(void *dm_void, u32 *val_buf, u8 val_len);
+
+void odm_pause_dig(void *dm_void, enum phydm_pause_type pause_type,
+		   enum phydm_pause_level pause_level, u8 igi_value);
+
+void phydm_dig_init(void *dm_void);
+
+void phydm_dig(void *dm_void);
+
+void phydm_dig_lps_32k(void *dm_void);
+
+void phydm_dig_by_rssi_lps(void *dm_void);
+
+void phydm_false_alarm_counter_statistics(void *dm_void);
+
+#ifdef PHYDM_TDMA_DIG_SUPPORT
+void phydm_set_tdma_dig_timer(void *dm_void);
+
+void phydm_tdma_dig_timer_check(void *dm_void);
+
+void phydm_tdma_dig(void *dm_void);
+
+void phydm_tdma_false_alarm_counter_check(void *dm_void);
+
+void phydm_tdma_dig_add_interrupt_mask_handler(void *dm_void);
+
+void phydm_false_alarm_counter_reset(void *dm_void);
+
+void phydm_false_alarm_counter_acc(void *dm_void, boolean rssi_dump_en);
+
+void phydm_false_alarm_counter_acc_reset(void *dm_void);
+
+#ifdef IS_USE_NEW_TDMA
+void phydm_tdma_dig_timers(void *dm_void, u8 state);
+
+void phydm_tdma_dig_cbk(void *dm_void);
+
+void phydm_tdma_fa_cnt_chk(void *dm_void);
+
+void phydm_tdma_low_dig(void *dm_void);
+
+void phydm_tdma_high_dig(void *dm_void);
+
+void phydm_fa_cnt_acc(void *dm_void, boolean rssi_dump_en,
+		      u8 cur_tdma_dig_state);
+#endif /*@#ifdef IS_USE_NEW_TDMA*/
+#endif /*@#ifdef PHYDM_TDMA_DIG_SUPPORT*/
+
+void phydm_set_ofdm_agc_tab(void *dm_void, u8 tab_sel);
+
+void phydm_dig_debug(void *dm_void, char input[][16], u32 *_used, char *output,
+		     u32 *_out_len);
+
+#ifdef CONFIG_MCC_DM
+void phydm_mcc_igi_cal(void *dm_void);
+#endif
+
+
+#endif
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/phydm_dynamicbbpowersaving.c linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/phydm_dynamicbbpowersaving.c
--- linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/phydm_dynamicbbpowersaving.c	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/phydm_dynamicbbpowersaving.c	2020-04-10 16:35:06.824660441 +0300
@@ -0,0 +1,111 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
+ *
+ *
+ ******************************************************************************/
+
+/* ************************************************************
+ * include files
+ * ************************************************************ */
+#include "mp_precomp.h"
+#include "phydm_precomp.h"
+
+#if (defined(CONFIG_BB_POWER_SAVING))
+
+void
+odm_dynamic_bb_power_saving_init(
+	void					*p_dm_void
+)
+{
+	struct PHY_DM_STRUCT		*p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
+	struct _dynamic_power_saving	*p_dm_ps_table = &p_dm_odm->dm_ps_table;
+
+	p_dm_ps_table->pre_cca_state = CCA_MAX;
+	p_dm_ps_table->cur_cca_state = CCA_MAX;
+	p_dm_ps_table->pre_rf_state = RF_MAX;
+	p_dm_ps_table->cur_rf_state = RF_MAX;
+	p_dm_ps_table->rssi_val_min = 0;
+	p_dm_ps_table->initialize = 0;
+}
+
+void
+odm_rf_saving(
+	void					*p_dm_void,
+	u8		is_force_in_normal
+)
+{
+	struct PHY_DM_STRUCT		*p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
+#if (DM_ODM_SUPPORT_TYPE != ODM_AP)
+	struct _dynamic_power_saving	*p_dm_ps_table = &p_dm_odm->dm_ps_table;
+	u8	rssi_up_bound = 30 ;
+	u8	rssi_low_bound = 25;
+#if (DM_ODM_SUPPORT_TYPE == ODM_CE)
+	if (p_dm_odm->patch_id == 40) { /* RT_CID_819x_FUNAI_TV */
+		rssi_up_bound = 50 ;
+		rssi_low_bound = 45;
+	}
+#endif
+	if (p_dm_ps_table->initialize == 0) {
+
+		p_dm_ps_table->reg874 = (odm_get_bb_reg(p_dm_odm, 0x874, MASKDWORD) & 0x1CC000) >> 14;
+		p_dm_ps_table->regc70 = (odm_get_bb_reg(p_dm_odm, 0xc70, MASKDWORD) & BIT(3)) >> 3;
+		p_dm_ps_table->reg85c = (odm_get_bb_reg(p_dm_odm, 0x85c, MASKDWORD) & 0xFF000000) >> 24;
+		p_dm_ps_table->rega74 = (odm_get_bb_reg(p_dm_odm, 0xa74, MASKDWORD) & 0xF000) >> 12;
+		/* Reg818 = phy_query_bb_reg(p_adapter, 0x818, MASKDWORD); */
+		p_dm_ps_table->initialize = 1;
+	}
+
+	if (!is_force_in_normal) {
+		if (p_dm_odm->rssi_min != 0xFF) {
+			if (p_dm_ps_table->pre_rf_state == rf_normal) {
+				if (p_dm_odm->rssi_min >= rssi_up_bound)
+					p_dm_ps_table->cur_rf_state = rf_save;
+				else
+					p_dm_ps_table->cur_rf_state = rf_normal;
+			} else {
+				if (p_dm_odm->rssi_min <= rssi_low_bound)
+					p_dm_ps_table->cur_rf_state = rf_normal;
+				else
+					p_dm_ps_table->cur_rf_state = rf_save;
+			}
+		} else
+			p_dm_ps_table->cur_rf_state = RF_MAX;
+	} else
+		p_dm_ps_table->cur_rf_state = rf_normal;
+
+	if (p_dm_ps_table->pre_rf_state != p_dm_ps_table->cur_rf_state) {
+		if (p_dm_ps_table->cur_rf_state == rf_save) {
+			odm_set_bb_reg(p_dm_odm, 0x874, 0x1C0000, 0x2); /* reg874[20:18]=3'b010 */
+			odm_set_bb_reg(p_dm_odm, 0xc70, BIT(3), 0); /* regc70[3]=1'b0 */
+			odm_set_bb_reg(p_dm_odm, 0x85c, 0xFF000000, 0x63); /* reg85c[31:24]=0x63 */
+			odm_set_bb_reg(p_dm_odm, 0x874, 0xC000, 0x2); /* reg874[15:14]=2'b10 */
+			odm_set_bb_reg(p_dm_odm, 0xa74, 0xF000, 0x3); /* RegA75[7:4]=0x3 */
+			odm_set_bb_reg(p_dm_odm, 0x818, BIT(28), 0x0); /* Reg818[28]=1'b0 */
+			odm_set_bb_reg(p_dm_odm, 0x818, BIT(28), 0x1); /* Reg818[28]=1'b1 */
+		} else {
+			odm_set_bb_reg(p_dm_odm, 0x874, 0x1CC000, p_dm_ps_table->reg874);
+			odm_set_bb_reg(p_dm_odm, 0xc70, BIT(3), p_dm_ps_table->regc70);
+			odm_set_bb_reg(p_dm_odm, 0x85c, 0xFF000000, p_dm_ps_table->reg85c);
+			odm_set_bb_reg(p_dm_odm, 0xa74, 0xF000, p_dm_ps_table->rega74);
+			odm_set_bb_reg(p_dm_odm, 0x818, BIT(28), 0x0);
+		}
+		p_dm_ps_table->pre_rf_state = p_dm_ps_table->cur_rf_state;
+	}
+#endif
+}
+
+#endif
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/phydm_dynamicbbpowersaving.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/phydm_dynamicbbpowersaving.h
--- linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/phydm_dynamicbbpowersaving.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/phydm_dynamicbbpowersaving.h	2020-04-10 16:35:06.824660441 +0300
@@ -0,0 +1,57 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
+ *
+ *
+ ******************************************************************************/
+
+#ifndef	__PHYDMDYNAMICBBPOWERSAVING_H__
+#define    __PHYDMDYNAMICBBPOWERSAVING_H__
+
+#define DYNAMIC_BBPWRSAV_VERSION	"1.1"
+
+#if (defined(CONFIG_BB_POWER_SAVING))
+
+struct _dynamic_power_saving {
+	u8		pre_cca_state;
+	u8		cur_cca_state;
+
+	u8		pre_rf_state;
+	u8		cur_rf_state;
+
+	int		    rssi_val_min;
+
+	u8		initialize;
+	u32		reg874, regc70, reg85c, rega74;
+
+};
+
+#define dm_rf_saving	odm_rf_saving
+
+void odm_rf_saving(
+	void					*p_dm_void,
+	u8		is_force_in_normal
+);
+
+void
+odm_dynamic_bb_power_saving_init(
+	void					*p_dm_void
+);
+#else
+#define dm_rf_saving(p_dm_void, is_force_in_normal)
+#endif
+
+#endif
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/phydm_dynamic_rx_path.c linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/phydm_dynamic_rx_path.c
--- linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/phydm_dynamic_rx_path.c	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/phydm_dynamic_rx_path.c	2020-04-10 16:35:06.824660441 +0300
@@ -0,0 +1,357 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
+ *
+ *
+ ******************************************************************************/
+
+/* ************************************************************
+ * include files
+ * ************************************************************ */
+#include "mp_precomp.h"
+#include "phydm_precomp.h"
+
+#if (CONFIG_DYNAMIC_RX_PATH == 1)
+
+void
+phydm_process_phy_status_for_dynamic_rx_path(
+	void			*p_dm_void,
+	void			*p_phy_info_void,
+	void			*p_pkt_info_void
+)
+{
+	struct PHY_DM_STRUCT				*p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
+	struct _odm_phy_status_info_		*p_phy_info = (struct _odm_phy_status_info_ *)p_phy_info_void;
+	struct _odm_per_pkt_info_		*p_pktinfo = (struct _odm_per_pkt_info_ *)p_pkt_info_void;
+	struct _DYNAMIC_RX_PATH_					*p_dm_drp_table	= &(p_dm_odm->dm_drp_table);
+	/*u8					is_cck_rate=0;*/
+
+
+
+}
+
+void
+phydm_drp_get_statistic(
+	void			*p_dm_void
+)
+{
+	struct PHY_DM_STRUCT					*p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
+	struct _DYNAMIC_RX_PATH_						*p_dm_drp_table = &(p_dm_odm->dm_drp_table);
+	struct _FALSE_ALARM_STATISTICS		*false_alm_cnt = (struct _FALSE_ALARM_STATISTICS *)phydm_get_structure(p_dm_odm, PHYDM_FALSEALMCNT);
+
+	odm_false_alarm_counter_statistics(p_dm_odm);
+
+	ODM_RT_TRACE(p_dm_odm, ODM_COMP_DYNAMIC_RX_PATH, ODM_DBG_LOUD, ("[CCA Cnt] {CCK, OFDM, Total} = {%d, %d, %d}\n",
+		false_alm_cnt->cnt_cck_cca, false_alm_cnt->cnt_ofdm_cca, false_alm_cnt->cnt_cca_all));
+
+	ODM_RT_TRACE(p_dm_odm, ODM_COMP_DYNAMIC_RX_PATH, ODM_DBG_LOUD, ("[FA Cnt] {CCK, OFDM, Total} = {%d, %d, %d}\n",
+		false_alm_cnt->cnt_cck_fail, false_alm_cnt->cnt_ofdm_fail, false_alm_cnt->cnt_all));
+}
+
+void
+phydm_dynamic_rx_path(
+	void			*p_dm_void
+)
+{
+	struct PHY_DM_STRUCT				*p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
+	struct _DYNAMIC_RX_PATH_					*p_dm_drp_table	= &(p_dm_odm->dm_drp_table);
+	u8		training_set_timmer_en;
+	u8		curr_drp_state;
+	u32		rx_ok_cal;
+	u32		RSSI = 0;
+	struct _FALSE_ALARM_STATISTICS		*false_alm_cnt = (struct _FALSE_ALARM_STATISTICS *)phydm_get_structure(p_dm_odm, PHYDM_FALSEALMCNT);
+
+	if (!(p_dm_odm->support_ability & ODM_BB_DYNAMIC_RX_PATH)) {
+		ODM_RT_TRACE(p_dm_odm, ODM_COMP_DYNAMIC_RX_PATH, ODM_DBG_LOUD, ("[Return Init]   Not Support Dynamic RX PAth\n"));
+		return;
+	}
+
+	ODM_RT_TRACE(p_dm_odm, ODM_COMP_DYNAMIC_RX_PATH, ODM_DBG_LOUD, ("Current drp_state = ((%d))\n", p_dm_drp_table->drp_state));
+
+	curr_drp_state = p_dm_drp_table->drp_state;
+
+	if (p_dm_drp_table->drp_state == DRP_INIT_STATE) {
+
+		phydm_drp_get_statistic(p_dm_odm);
+
+		if (false_alm_cnt->cnt_crc32_ok_all > 20) {
+			ODM_RT_TRACE(p_dm_odm, ODM_COMP_DYNAMIC_RX_PATH, ODM_DBG_LOUD, ("[Stop DRP Training] cnt_crc32_ok_all = ((%d))\n", false_alm_cnt->cnt_crc32_ok_all));
+			p_dm_drp_table->drp_state  = DRP_INIT_STATE;
+			training_set_timmer_en = false;
+		} else {
+			ODM_RT_TRACE(p_dm_odm, ODM_COMP_DYNAMIC_RX_PATH, ODM_DBG_LOUD, ("[Start DRP Training] cnt_crc32_ok_all = ((%d))\n", false_alm_cnt->cnt_crc32_ok_all));
+			p_dm_drp_table->drp_state  = DRP_TRAINING_STATE_0;
+			p_dm_drp_table->curr_rx_path = PHYDM_AB;
+			training_set_timmer_en = true;
+		}
+
+	} else if (p_dm_drp_table->drp_state == DRP_TRAINING_STATE_0) {
+
+		phydm_drp_get_statistic(p_dm_odm);
+
+		p_dm_drp_table->curr_cca_all_cnt_0 = false_alm_cnt->cnt_cca_all;
+		p_dm_drp_table->curr_fa_all_cnt_0 = false_alm_cnt->cnt_all;
+
+		p_dm_drp_table->drp_state  = DRP_TRAINING_STATE_1;
+		p_dm_drp_table->curr_rx_path = PHYDM_B;
+		training_set_timmer_en = true;
+
+	} else if (p_dm_drp_table->drp_state == DRP_TRAINING_STATE_1) {
+
+		phydm_drp_get_statistic(p_dm_odm);
+
+		p_dm_drp_table->curr_cca_all_cnt_1 = false_alm_cnt->cnt_cca_all;
+		p_dm_drp_table->curr_fa_all_cnt_1 = false_alm_cnt->cnt_all;
+
+#if 1
+		p_dm_drp_table->drp_state  = DRP_DECISION_STATE;
+#else
+
+		if (p_dm_odm->mp_mode) {
+			rx_ok_cal = p_dm_odm->phy_dbg_info.num_qry_phy_status_cck + p_dm_odm->phy_dbg_info.num_qry_phy_status_ofdm;
+			RSSI = (rx_ok_cal != 0) ? p_dm_odm->rx_pwdb_ave / rx_ok_cal : 0;
+			ODM_RT_TRACE(p_dm_odm, ODM_COMP_DYNAMIC_RX_PATH, ODM_DBG_LOUD, ("MP RSSI = ((%d))\n", RSSI));
+		}
+
+		if (RSSI > p_dm_drp_table->rssi_threshold)
+
+			p_dm_drp_table->drp_state  = DRP_DECISION_STATE;
+
+		else  {
+
+			p_dm_drp_table->drp_state  = DRP_TRAINING_STATE_2;
+			p_dm_drp_table->curr_rx_path = PHYDM_A;
+			training_set_timmer_en = true;
+		}
+#endif
+	} else if (p_dm_drp_table->drp_state == DRP_TRAINING_STATE_2) {
+
+		phydm_drp_get_statistic(p_dm_odm);
+
+		p_dm_drp_table->curr_cca_all_cnt_2 = false_alm_cnt->cnt_cca_all;
+		p_dm_drp_table->curr_fa_all_cnt_2 = false_alm_cnt->cnt_all;
+		p_dm_drp_table->drp_state  = DRP_DECISION_STATE;
+	}
+
+	if (p_dm_drp_table->drp_state == DRP_DECISION_STATE) {
+
+		ODM_RT_TRACE(p_dm_odm, ODM_COMP_DYNAMIC_RX_PATH, ODM_DBG_LOUD, ("Current drp_state = ((%d))\n", p_dm_drp_table->drp_state));
+
+		ODM_RT_TRACE(p_dm_odm, ODM_COMP_DYNAMIC_RX_PATH, ODM_DBG_LOUD, ("[0] {CCA, FA} = {%d, %d}\n", p_dm_drp_table->curr_cca_all_cnt_0, p_dm_drp_table->curr_fa_all_cnt_0));
+		ODM_RT_TRACE(p_dm_odm, ODM_COMP_DYNAMIC_RX_PATH, ODM_DBG_LOUD, ("[1] {CCA, FA} = {%d, %d}\n", p_dm_drp_table->curr_cca_all_cnt_1, p_dm_drp_table->curr_fa_all_cnt_1));
+		ODM_RT_TRACE(p_dm_odm, ODM_COMP_DYNAMIC_RX_PATH, ODM_DBG_LOUD, ("[2] {CCA, FA} = {%d, %d}\n", p_dm_drp_table->curr_cca_all_cnt_2, p_dm_drp_table->curr_fa_all_cnt_2));
+
+		if (p_dm_drp_table->curr_fa_all_cnt_1 < p_dm_drp_table->curr_fa_all_cnt_0) {
+
+			if ((p_dm_drp_table->curr_fa_all_cnt_0 - p_dm_drp_table->curr_fa_all_cnt_1) > p_dm_drp_table->fa_diff_threshold)
+				p_dm_drp_table->curr_rx_path = PHYDM_B;
+			else
+				p_dm_drp_table->curr_rx_path = PHYDM_AB;
+		} else
+			p_dm_drp_table->curr_rx_path = PHYDM_AB;
+
+		phydm_config_ofdm_rx_path(p_dm_odm, p_dm_drp_table->curr_rx_path);
+		ODM_RT_TRACE(p_dm_odm, ODM_COMP_DYNAMIC_RX_PATH, ODM_DBG_LOUD, ("[Training Result]  curr_rx_path = ((%s%s)),\n",
+			((p_dm_drp_table->curr_rx_path & PHYDM_A)  ? "A"  : " "), ((p_dm_drp_table->curr_rx_path & PHYDM_B)  ? "B"  : " ")));
+
+		p_dm_drp_table->drp_state = DRP_INIT_STATE;
+		training_set_timmer_en = false;
+	}
+
+	ODM_RT_TRACE(p_dm_odm, ODM_COMP_DYNAMIC_RX_PATH, ODM_DBG_LOUD, ("DRP_state: ((%d)) -> ((%d))\n", curr_drp_state, p_dm_drp_table->drp_state));
+
+	if (training_set_timmer_en) {
+
+		ODM_RT_TRACE(p_dm_odm, ODM_COMP_DYNAMIC_RX_PATH, ODM_DBG_LOUD, ("[Training en]  curr_rx_path = ((%s%s)), training_time = ((%d ms))\n",
+			((p_dm_drp_table->curr_rx_path & PHYDM_A)  ? "A"  : " "), ((p_dm_drp_table->curr_rx_path & PHYDM_B)  ? "B"  : " "), p_dm_drp_table->training_time));
+
+		phydm_config_ofdm_rx_path(p_dm_odm, p_dm_drp_table->curr_rx_path);
+		odm_set_timer(p_dm_odm, &(p_dm_drp_table->phydm_dynamic_rx_path_timer), p_dm_drp_table->training_time); /*ms*/
+	} else
+		ODM_RT_TRACE(p_dm_odm, ODM_COMP_DYNAMIC_RX_PATH, ODM_DBG_LOUD, ("DRP period end\n\n", curr_drp_state, p_dm_drp_table->drp_state));
+
+}
+
+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
+void
+phydm_dynamic_rx_path_callback(
+	struct timer_list		*p_timer
+)
+{
+	struct _ADAPTER		*adapter = (struct _ADAPTER *)p_timer->adapter;
+	HAL_DATA_TYPE	*p_hal_data = GET_HAL_DATA(adapter);
+	struct PHY_DM_STRUCT		*p_dm_odm = &(p_hal_data->DM_OutSrc);
+	struct _DYNAMIC_RX_PATH_			*p_dm_drp_table = &(p_dm_odm->dm_drp_table);
+
+#if DEV_BUS_TYPE == RT_PCI_INTERFACE
+#if USE_WORKITEM
+	odm_schedule_work_item(&(p_dm_drp_table->phydm_dynamic_rx_path_workitem));
+#else
+	{
+		/* dbg_print("phydm_dynamic_rx_path\n"); */
+		phydm_dynamic_rx_path(p_dm_odm);
+	}
+#endif
+#else
+	odm_schedule_work_item(&(p_dm_drp_table->phydm_dynamic_rx_path_workitem));
+#endif
+}
+
+void
+phydm_dynamic_rx_path_workitem_callback(
+	void		*p_context
+)
+{
+	struct _ADAPTER		*p_adapter = (struct _ADAPTER *)p_context;
+	HAL_DATA_TYPE	*p_hal_data = GET_HAL_DATA(p_adapter);
+	struct PHY_DM_STRUCT		*p_dm_odm = &(p_hal_data->DM_OutSrc);
+
+	/* dbg_print("phydm_dynamic_rx_path\n"); */
+	phydm_dynamic_rx_path(p_dm_odm);
+}
+#else if (DM_ODM_SUPPORT_TYPE == ODM_CE)
+
+void
+phydm_dynamic_rx_path_callback(
+	void *function_context
+)
+{
+	struct PHY_DM_STRUCT	*p_dm_odm = (struct PHY_DM_STRUCT *)function_context;
+	struct _ADAPTER	*padapter = p_dm_odm->adapter;
+
+	if (padapter->net_closed == _TRUE)
+		return;
+
+#if 0 /* Can't do I/O in timer callback*/
+	odm_s0s1_sw_ant_div(p_dm_odm, SWAW_STEP_DETERMINE);
+#else
+	/*rtw_run_in_thread_cmd(padapter, odm_sw_antdiv_workitem_callback, padapter);*/
+#endif
+}
+
+#endif
+
+void
+phydm_dynamic_rx_path_timers(
+	void		*p_dm_void,
+	u8		state
+)
+{
+	struct PHY_DM_STRUCT		*p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
+	struct _DYNAMIC_RX_PATH_			*p_dm_drp_table	= &(p_dm_odm->dm_drp_table);
+
+	if (state == INIT_DRP_TIMMER) {
+
+		odm_initialize_timer(p_dm_odm, &(p_dm_drp_table->phydm_dynamic_rx_path_timer),
+			(void *)phydm_dynamic_rx_path_callback, NULL, "phydm_sw_antenna_switch_timer");
+	} else if (state == CANCEL_DRP_TIMMER)
+
+		odm_cancel_timer(p_dm_odm, &(p_dm_drp_table->phydm_dynamic_rx_path_timer));
+
+	else if (state == RELEASE_DRP_TIMMER)
+
+		odm_release_timer(p_dm_odm, &(p_dm_drp_table->phydm_dynamic_rx_path_timer));
+
+}
+
+void
+phydm_dynamic_rx_path_init(
+	void			*p_dm_void
+)
+{
+	struct PHY_DM_STRUCT				*p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
+	struct _DYNAMIC_RX_PATH_					*p_dm_drp_table	= &(p_dm_odm->dm_drp_table);
+	boolean			ret_value;
+
+	if (!(p_dm_odm->support_ability & ODM_BB_DYNAMIC_RX_PATH)) {
+		ODM_RT_TRACE(p_dm_odm, ODM_COMP_DYNAMIC_RX_PATH, ODM_DBG_LOUD, ("[Return]   Not Support Dynamic RX PAth\n"));
+		return;
+	}
+	ODM_RT_TRACE(p_dm_odm, ODM_COMP_DYNAMIC_RX_PATH, ODM_DBG_LOUD, ("phydm_dynamic_rx_path_init\n"));
+
+	p_dm_drp_table->drp_state = DRP_INIT_STATE;
+	p_dm_drp_table->rssi_threshold = DRP_RSSI_TH;
+	p_dm_drp_table->fa_count_thresold = 50;
+	p_dm_drp_table->fa_diff_threshold = 50;
+	p_dm_drp_table->training_time = 100; /*ms*/
+	p_dm_drp_table->drp_skip_counter = 0;
+	p_dm_drp_table->drp_period  = 0;
+	p_dm_drp_table->drp_init_finished = true;
+
+	ret_value = phydm_api_trx_mode(p_dm_odm, (enum odm_rf_path_e)(ODM_RF_A | ODM_RF_B), (enum odm_rf_path_e)(ODM_RF_A | ODM_RF_B), true);
+
+}
+
+void
+phydm_drp_debug(
+	void		*p_dm_void,
+	u32		*const dm_value,
+	u32		*_used,
+	char			*output,
+	u32		*_out_len
+)
+{
+	struct PHY_DM_STRUCT		*p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
+	u32			used = *_used;
+	u32			out_len = *_out_len;
+	struct _DYNAMIC_RX_PATH_			*p_dm_drp_table = &(p_dm_odm->dm_drp_table);
+
+	switch (dm_value[0])	{
+
+	case DRP_TRAINING_TIME:
+		p_dm_drp_table->training_time = (u16)dm_value[1];
+		break;
+	case DRP_TRAINING_PERIOD:
+		p_dm_drp_table->drp_period = (u8)dm_value[1];
+		break;
+	case DRP_RSSI_THRESHOLD:
+		p_dm_drp_table->rssi_threshold = (u8)dm_value[1];
+		break;
+	case DRP_FA_THRESHOLD:
+		p_dm_drp_table->fa_count_thresold = dm_value[1];
+		break;
+	case DRP_FA_DIFF_THRESHOLD:
+		p_dm_drp_table->fa_diff_threshold = dm_value[1];
+		break;
+	default:
+		PHYDM_SNPRINTF((output + used, out_len - used, "[DRP] unknown command\n"));
+		break;
+}
+}
+
+void
+phydm_dynamic_rx_path_caller(
+	void			*p_dm_void
+)
+{
+	struct PHY_DM_STRUCT		*p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
+	struct _DYNAMIC_RX_PATH_			*p_dm_drp_table	= &(p_dm_odm->dm_drp_table);
+
+	if (p_dm_drp_table->drp_skip_counter <  p_dm_drp_table->drp_period)
+		p_dm_drp_table->drp_skip_counter++;
+	else
+		p_dm_drp_table->drp_skip_counter = 0;
+
+	if (p_dm_drp_table->drp_skip_counter != 0)
+		return;
+
+	if (p_dm_drp_table->drp_init_finished != true)
+		return;
+
+	phydm_dynamic_rx_path(p_dm_odm);
+
+}
+#endif
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/phydm_dynamic_rx_path.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/phydm_dynamic_rx_path.h
--- linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/phydm_dynamic_rx_path.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/phydm_dynamic_rx_path.h	2020-04-10 16:35:06.824660441 +0300
@@ -0,0 +1,137 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
+ *
+ *
+ ******************************************************************************/
+
+#ifndef	__PHYDMDYMICRXPATH_H__
+#define    __PHYDMDYMICRXPATH_H__
+
+#define DYNAMIC_RX_PATH_VERSION	"1.0"  /*2016.07.15  Dino */
+
+
+#define	DRP_RSSI_TH	35
+
+#define INIT_DRP_TIMMER		0
+#define CANCEL_DRP_TIMMER		1
+#define RELEASE_DRP_TIMMER		2
+
+#if (CONFIG_DYNAMIC_RX_PATH == 1)
+
+enum drp_state_e {
+	DRP_INIT_STATE				= 0,
+	DRP_TRAINING_STATE_0	= 1,
+	DRP_TRAINING_STATE_1		= 2,
+	DRP_TRAINING_STATE_2		= 3,
+	DRP_DECISION_STATE		= 4
+};
+
+enum adjustable_value_e {
+	DRP_TRAINING_TIME		= 0,
+	DRP_TRAINING_PERIOD	= 1,
+	DRP_RSSI_THRESHOLD	= 2,
+	DRP_FA_THRESHOLD		= 3,
+	DRP_FA_DIFF_THRESHOLD = 4
+};
+
+struct _DYNAMIC_RX_PATH_ {
+	u8			curr_rx_path;
+	u8			drp_state;
+	u16			training_time;
+	u8			rssi_threshold;
+	u32			fa_count_thresold;
+	u32			fa_diff_threshold;
+	u32			curr_cca_all_cnt_0;
+	u32			curr_fa_all_cnt_0;
+	u32			curr_cca_all_cnt_1;
+	u32			curr_fa_all_cnt_1;
+	u32			curr_cca_all_cnt_2;
+	u32			curr_fa_all_cnt_2;
+	u8			drp_skip_counter;
+	u8			drp_period;
+	u8			drp_init_finished;
+
+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
+#if USE_WORKITEM
+	RT_WORK_ITEM	phydm_dynamic_rx_path_workitem;
+#endif
+#endif
+	struct timer_list		phydm_dynamic_rx_path_timer;
+
+};
+
+
+
+void
+phydm_process_phy_status_for_dynamic_rx_path(
+	void			*p_dm_void,
+	void			*p_phy_info_void,
+	void			*p_pkt_info_void
+);
+
+void
+phydm_dynamic_rx_path(
+	void			*p_dm_void
+);
+
+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
+void
+phydm_dynamic_rx_path_callback(
+	struct timer_list		*p_timer
+);
+
+void
+phydm_dynamic_rx_path_workitem_callback(
+	void		*p_context
+);
+
+#else if (DM_ODM_SUPPORT_TYPE == ODM_CE)
+
+void
+phydm_dynamic_rx_path_callback(
+	void *function_context
+);
+
+#endif
+
+void
+phydm_dynamic_rx_path_timers(
+	void		*p_dm_void,
+	u8		state
+);
+
+void
+phydm_dynamic_rx_path_init(
+	void			*p_dm_void
+);
+
+void
+phydm_drp_debug(
+	void		*p_dm_void,
+	u32		*const dm_value,
+	u32		*_used,
+	char			*output,
+	u32		*_out_len
+);
+
+void
+phydm_dynamic_rx_path_caller(
+	void			*p_dm_void
+);
+
+#endif
+#endif
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/phydm_dynamictxpower.c linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/phydm_dynamictxpower.c
--- linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/phydm_dynamictxpower.c	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/phydm_dynamictxpower.c	2020-04-10 16:35:06.824660441 +0300
@@ -0,0 +1,507 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017  Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * The full GNU General Public License is included in this distribution in the
+ * file called LICENSE.
+ *
+ * Contact Information:
+ * wlanfae <wlanfae@realtek.com>
+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
+ * Hsinchu 300, Taiwan.
+ *
+ * Larry Finger <Larry.Finger@lwfinger.net>
+ *
+ *****************************************************************************/
+
+/*************************************************************
+ * include files
+ ************************************************************/
+#include "mp_precomp.h"
+#include "phydm_precomp.h"
+
+#ifdef CONFIG_DYNAMIC_TX_TWR
+
+#ifdef BB_RAM_SUPPORT
+void
+phydm_2ndtype_dtp_init(void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	u8	pwr_offset_minus3, pwr_offset_minus7;
+	/*@ 2's com, for offset 3dB and 7dB, which 1 step will be 0.25dB*/
+	pwr_offset_minus3 = BIT(7) | 0x74;
+	pwr_offset_minus7 = BIT(7) | 0x64;
+	odm_set_bb_reg(dm, 0x1e70, 0x00ff0000, pwr_offset_minus3);
+	odm_set_bb_reg(dm, 0x1e70, 0xff000000, pwr_offset_minus7);
+};
+
+void
+phdm_2ndtype_rd_ram_pwr(void *dm_void,	u8	macid)
+{
+};
+
+void
+phdm_2ndtype_wt_ram_pwr(void *dm_void, u8	macid, boolean pwr_offset0_en,
+			     boolean	pwr_offset1_en, s8 pwr_offset0, s8 pwr_offset1)
+{
+	u32 reg_io_0x1e84 = 0;
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct phydm_bb_ram_per_sta *dm_ram_per_sta = NULL;
+	dm_ram_per_sta = &dm->p_bb_ram_ctrl.pram_sta_ctrl[macid];
+	dm_ram_per_sta->tx_pwr_offset0_en = pwr_offset0_en;
+	dm_ram_per_sta->tx_pwr_offset1_en = pwr_offset1_en;
+	dm_ram_per_sta->tx_pwr_offset0 = pwr_offset0;
+	dm_ram_per_sta->tx_pwr_offset1 = pwr_offset1;
+	reg_io_0x1e84 = (dm_ram_per_sta->hw_igi_en<<7) + dm_ram_per_sta->hw_igi;
+	reg_io_0x1e84 |= (pwr_offset0_en<<15) + ((pwr_offset0&0x7f)<<8);
+	reg_io_0x1e84 |= (pwr_offset1_en<<23) + ((pwr_offset1&0x7f)<<16);
+	reg_io_0x1e84 |= (macid&0x3f)<<24;
+	reg_io_0x1e84 |= BIT(30);
+	odm_set_bb_reg(dm, 0x1e84, 0xffffffff, reg_io_0x1e84);
+};
+
+u8 phydm_pwr_lv_mapping_2ndtype(u8 tx_pwr_lv)
+{
+	if (tx_pwr_lv == tx_high_pwr_level_level3)
+		/*PHYDM_2ND_OFFSET_MINUS_11DB;*/
+		return PHYDM_2ND_OFFSET_MINUS_7DB;
+	else if (tx_pwr_lv == tx_high_pwr_level_level2)
+		return PHYDM_2ND_OFFSET_MINUS_7DB;
+	else if (tx_pwr_lv == tx_high_pwr_level_level1)
+		return PHYDM_2ND_OFFSET_MINUS_3DB;
+	else
+		return PHYDM_2ND_OFFSET_ZERO;
+}
+
+void phydm_dtp_fill_cmninfo_2ndtype(void *dm_void, u8 macid, u8 dtp_lvl)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct dtp_info *dtp = NULL;
+	dtp = &dm->phydm_sta_info[macid]->dtp_stat;
+	if (!(dm->support_ability & ODM_BB_DYNAMIC_TXPWR))
+		return;
+	dtp->dyn_tx_power = phydm_pwr_lv_mapping_2ndtype(dtp_lvl);
+	PHYDM_DBG(dm, DBG_DYN_TXPWR,
+		  "Fill cmninfo TxPwr: macid=(%d), PwrLv (%d)\n", macid,
+		  dtp->dyn_tx_power);
+	/* dyn_tx_power is 2 bit at 8822C/14B/98F/12F*/
+}
+
+#endif
+
+boolean
+phydm_check_rates(void *dm_void, u8 rate_idx)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	u32 check_rate_bitmap0 = 0x08080808; /* @check CCK11M, OFDM54M, MCS7, MCS15*/
+	u32 check_rate_bitmap1 = 0x80200808; /* @check MCS23, MCS31, VHT1SS M9, VHT2SS M9*/
+	u32 check_rate_bitmap2 = 0x00080200; /* @check VHT3SS M9, VHT4SS M9*/
+	u32 bitmap_result;
+
+#if (RTL8822B_SUPPORT == 1)
+	if (dm->support_ic_type & ODM_RTL8822B) {
+		check_rate_bitmap2 &= 0;
+		check_rate_bitmap1 &= 0xfffff000;
+		check_rate_bitmap0 &= 0x0fffffff;
+	}
+#endif
+
+#if (RTL8197F_SUPPORT == 1)
+	if (dm->support_ic_type & ODM_RTL8197F) {
+		check_rate_bitmap2 &= 0;
+		check_rate_bitmap1 &= 0;
+		check_rate_bitmap0 &= 0x0fffffff;
+	}
+#endif
+
+#if (RTL8192E_SUPPORT == 1)
+	if (dm->support_ic_type & ODM_RTL8192E) {
+		check_rate_bitmap2 &= 0;
+		check_rate_bitmap1 &= 0;
+		check_rate_bitmap0 &= 0x0fffffff;
+	}
+#endif
+
+/*@jj add 20170822*/
+#if (RTL8192F_SUPPORT == 1)
+	if (dm->support_ic_type & ODM_RTL8192F) {
+		check_rate_bitmap2 &= 0;
+		check_rate_bitmap1 &= 0;
+		check_rate_bitmap0 &= 0x0fffffff;
+	}
+#endif
+#if (RTL8821C_SUPPORT == 1)
+	if (dm->support_ic_type & ODM_RTL8821C) {
+		check_rate_bitmap2 &= 0;
+		check_rate_bitmap1 &= 0x003ff000;
+		check_rate_bitmap0 &= 0x000fffff;
+	}
+#endif
+
+	if (rate_idx >= 64)
+		bitmap_result = BIT(rate_idx - 64) & check_rate_bitmap2;
+	else if (rate_idx >= 32)
+		bitmap_result = BIT(rate_idx - 32) & check_rate_bitmap1;
+	else if (rate_idx <= 31)
+		bitmap_result = BIT(rate_idx) & check_rate_bitmap0;
+
+	if (bitmap_result != 0)
+		return true;
+	else
+		return false;
+}
+
+enum rf_path
+phydm_check_paths(void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	enum rf_path max_path = RF_PATH_A;
+
+	if (dm->num_rf_path == 1)
+		max_path = RF_PATH_A;
+	if (dm->num_rf_path == 2)
+		max_path = RF_PATH_B;
+	if (dm->num_rf_path == 3)
+		max_path = RF_PATH_C;
+	if (dm->num_rf_path == 4)
+		max_path = RF_PATH_D;
+
+	return max_path;
+}
+
+#ifndef PHYDM_COMMON_API_SUPPORT
+u8 phydm_dtp_get_txagc(void *dm_void, enum rf_path path, u8 hw_rate)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	u8 ret = 0xff;
+
+#if (RTL8192E_SUPPORT == 1)
+	ret = config_phydm_read_txagc_n(dm, path, hw_rate);
+#endif
+	return ret;
+}
+#endif
+
+u8 phydm_search_min_power_index(void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	enum rf_path path;
+	enum rf_path max_path;
+	u8 min_gain_index = 0x3f;
+	u8 gain_index;
+	u8 rate_idx;
+
+	PHYDM_DBG(dm, DBG_DYN_TXPWR, "%s\n", __func__);
+	max_path = phydm_check_paths(dm);
+	for (path = 0; path <= max_path; path++)
+		for (rate_idx = 0; rate_idx < 84; rate_idx++)
+			if (phydm_check_rates(dm, rate_idx)) {
+#ifdef PHYDM_COMMON_API_SUPPORT
+				/*This is for API support IC : 97F,8822B,92F,8821C*/
+				gain_index = phydm_api_get_txagc(dm, path, rate_idx);
+#else
+				/*This is for API non-support IC : 92E */
+				gain_index = phydm_dtp_get_txagc(dm, path, rate_idx);
+#endif
+				if (gain_index == 0xff) {
+					min_gain_index = 0x20;
+					PHYDM_DBG(dm, DBG_DYN_TXPWR, 
+						"Error Gain idx!! Rewite to: ((%d))\n", min_gain_index);
+					break;
+				}
+				PHYDM_DBG(dm, DBG_DYN_TXPWR,
+					  "Support Rate: ((%d)) -> Gain idx: ((%d))\n",
+					  rate_idx, gain_index);
+				if (gain_index < min_gain_index)
+					min_gain_index = gain_index;
+			}
+
+	return min_gain_index;
+}
+
+void phydm_dynamic_tx_power_init(void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	u8 i;
+	dm->last_dtp_lvl = tx_high_pwr_level_normal;
+	dm->dynamic_tx_high_power_lvl = tx_high_pwr_level_normal;
+	for (i = 0; i < 3; i++) {
+		dm->enhance_pwr_th[i] = 0xff;
+	}
+	dm->set_pwr_th[0] = TX_POWER_NEAR_FIELD_THRESH_LVL1;
+	dm->set_pwr_th[1] = TX_POWER_NEAR_FIELD_THRESH_LVL2;
+	dm->set_pwr_th[2] = 0xff;
+	dm->min_power_index = phydm_search_min_power_index(dm);
+	PHYDM_DBG(dm, DBG_DYN_TXPWR, "DTP init: Min Gain idx: ((%d))\n",
+		  dm->min_power_index);
+}
+
+void phydm_noisy_enhance_hp_th(void *dm_void, u8 noisy_state)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	if (noisy_state == 0) {
+		dm->enhance_pwr_th[0] = dm->set_pwr_th[0];
+		dm->enhance_pwr_th[1] = dm->set_pwr_th[1];
+		dm->enhance_pwr_th[2] = dm->set_pwr_th[2];
+	} else {
+		dm->enhance_pwr_th[0] = dm->set_pwr_th[0] + 8;
+		dm->enhance_pwr_th[1] = dm->set_pwr_th[1] + 5;
+		dm->enhance_pwr_th[2] = dm->set_pwr_th[2];
+	}
+	PHYDM_DBG(dm, DBG_DYN_TXPWR,
+		  "DTP hp_th: Lv1_th =%d ,Lv2_th = %d ,Lv3_th = %d\n",
+		  dm->enhance_pwr_th[0], dm->enhance_pwr_th[1],
+		  dm->enhance_pwr_th[2]);
+}
+
+u8 phydm_pwr_lvl_check(void *dm_void, u8 input_rssi)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	u8 th0,th1,th2;
+	th2 = dm->enhance_pwr_th[2];
+	th1 = dm->enhance_pwr_th[1];
+	th0 = dm->enhance_pwr_th[0];
+	if (input_rssi >= th2)
+		return tx_high_pwr_level_level3;
+	else if (input_rssi < (th2 - 3) && input_rssi >= th1)
+		return tx_high_pwr_level_level2;
+	else if (input_rssi < (th1 - 3) && input_rssi >= th0)
+		return tx_high_pwr_level_level1;
+	else if (input_rssi < (th0 - 3))
+		return tx_high_pwr_level_normal;
+	else
+		return tx_high_pwr_level_unchange;
+}
+
+u8 phydm_pwr_lv_mapping(u8 tx_pwr_lv)
+{
+	if (tx_pwr_lv == tx_high_pwr_level_level3)
+		return PHYDM_OFFSET_MINUS_11DB;
+	else if (tx_pwr_lv == tx_high_pwr_level_level2)
+		return PHYDM_OFFSET_MINUS_7DB;
+	else if (tx_pwr_lv == tx_high_pwr_level_level1)
+		return PHYDM_OFFSET_MINUS_3DB;
+	else
+		return PHYDM_OFFSET_ZERO;
+}
+
+void phydm_dynamic_response_power(void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	u8 rpwr;
+	if (!(dm->support_ability & ODM_BB_DYNAMIC_TXPWR))
+		return;
+	if (dm->dynamic_tx_high_power_lvl == tx_high_pwr_level_unchange) {
+		dm->dynamic_tx_high_power_lvl = dm->last_dtp_lvl;
+		PHYDM_DBG(dm, DBG_DYN_TXPWR, "RespPwr not change\n");
+		return;
+	}
+
+	PHYDM_DBG(dm, DBG_DYN_TXPWR,
+		  "RespPwr update_DTP_lv: ((%d)) -> ((%d))\n", dm->last_dtp_lvl,
+		  dm->dynamic_tx_high_power_lvl);
+	dm->last_dtp_lvl = dm->dynamic_tx_high_power_lvl;
+	rpwr = phydm_pwr_lv_mapping(dm->dynamic_tx_high_power_lvl);
+	odm_set_mac_reg(dm, ODM_REG_RESP_TX_11AC, BIT(20) | BIT(19) | BIT(18), rpwr);
+	PHYDM_DBG(dm, DBG_DYN_TXPWR, "RespPwr Set TxPwr: Lv (%d)\n",
+		  dm->dynamic_tx_high_power_lvl);
+}
+
+void phydm_dtp_fill_cmninfo(void *dm_void, u8 macid, u8 dtp_lvl)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct dtp_info *dtp = NULL;
+	dtp = &dm->phydm_sta_info[macid]->dtp_stat;
+	if (!(dm->support_ability & ODM_BB_DYNAMIC_TXPWR))
+		return;
+	dtp->dyn_tx_power = phydm_pwr_lv_mapping(dtp_lvl);
+	PHYDM_DBG(dm, DBG_DYN_TXPWR,
+		  "Fill cmninfo TxPwr: macid=(%d), PwrLv (%d)\n", macid,
+		  dtp->dyn_tx_power);
+}
+
+void phydm_dtp_per_sta(void *dm_void, u8 macid)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct cmn_sta_info *sta = dm->phydm_sta_info[macid];
+	struct dtp_info *dtp = NULL;
+	struct rssi_info *rssi = NULL;
+	if (is_sta_active(sta)) {
+		dtp = &sta->dtp_stat;
+		rssi = &sta->rssi_stat;
+		dtp->sta_tx_high_power_lvl = phydm_pwr_lvl_check(dm, rssi->rssi);
+		PHYDM_DBG(dm, DBG_DYN_TXPWR,
+			  "STA=%d , RSSI: %d , GetPwrLv: %d\n", macid,
+			  rssi->rssi, dtp->sta_tx_high_power_lvl);
+		if (dtp->sta_tx_high_power_lvl == tx_high_pwr_level_unchange 
+			|| dtp->sta_tx_high_power_lvl == dtp->sta_last_dtp_lvl) {
+			dtp->sta_tx_high_power_lvl = dtp->sta_last_dtp_lvl;
+			PHYDM_DBG(dm, DBG_DYN_TXPWR,
+				  "DTP_lv not change: ((%d))\n",
+				  dtp->sta_tx_high_power_lvl);
+			return;
+		}
+
+		PHYDM_DBG(dm, DBG_DYN_TXPWR,
+			  "DTP_lv update: ((%d)) -> ((%d))\n", dm->last_dtp_lvl,
+			  dm->dynamic_tx_high_power_lvl);
+		dtp->sta_last_dtp_lvl = dtp->sta_tx_high_power_lvl;
+#ifdef BB_RAM_SUPPORT
+		phydm_dtp_fill_cmninfo_2ndtype(dm, macid, dtp->sta_tx_high_power_lvl);
+#else
+		phydm_dtp_fill_cmninfo(dm, macid, dtp->sta_tx_high_power_lvl);
+#endif
+	}
+}
+
+
+void odm_set_dyntxpwr(void *dm_void, u8 *desc, u8 macid)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct dtp_info *dtp = NULL;
+	dtp = &dm->phydm_sta_info[macid]->dtp_stat;
+	if (!(dm->support_ability & ODM_BB_DYNAMIC_TXPWR))
+		return;
+	if (dm->fill_desc_dyntxpwr)
+		dm->fill_desc_dyntxpwr(dm, desc, dtp->dyn_tx_power);
+	else
+		PHYDM_DBG(dm, DBG_DYN_TXPWR,
+			  "%s: fill_desc_dyntxpwr is null!\n", __func__);
+	if (dtp->last_tx_power != dtp->dyn_tx_power) {
+		PHYDM_DBG(dm, DBG_DYN_TXPWR,
+			  "%s: last_offset=%d, txpwr_offset=%d\n", __func__,
+			  dtp->last_tx_power, dtp->dyn_tx_power);
+		dtp->last_tx_power = dtp->dyn_tx_power;
+	}
+}
+
+void phydm_dtp_debug(void *dm_void, char input[][16], u32 *_used, char *output,
+			     u32 *_out_len)
+{
+	u32 used = *_used;
+	u32 out_len = *_out_len;
+
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	char help[] = "-h";
+	u32 var1[3] = {0};
+	u8 set_pwr_th1, set_pwr_th2, set_pwr_th3;
+	u8 i;
+
+	if ((strcmp(input[1], help) == 0)) {
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "{DynTxPwr} {TH1 TH2 TH3}\n");
+	} else {
+		for (i = 0; i < 3; i++) {
+			if (input[i + 1])
+				PHYDM_SSCANF(input[i + 1], DCMD_HEX, &var1[i]);
+		}
+		for (i = 0; i < 3; i++)
+			if (var1[i] == 0 || var1[i] > 100)
+				dm->set_pwr_th[i] = 0xff;
+			else
+				dm->set_pwr_th[i] = (u8)var1[i];
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "Phydm Set DTP : TH1 = (( 0x%x)), TH2 = (( 0x%x)), TH3 = (( 0x%x))\n",
+			 dm->set_pwr_th[0], dm->set_pwr_th[1],
+			 dm->set_pwr_th[2]);
+	}
+	*_used = used;
+	*_out_len = out_len;
+}
+
+
+void phydm_dynamic_tx_power(void *dm_void)
+{
+
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct cmn_sta_info *sta = NULL;
+	u8 i;
+	u8 cnt = 0;
+	u8 rssi_min = dm->rssi_min;
+	u8 rssi_tmp = 0;
+
+	if (!(dm->support_ability & ODM_BB_DYNAMIC_TXPWR))
+		return;
+
+	PHYDM_DBG(dm, DBG_DYN_TXPWR,
+		  "[%s] RSSI_min = %d, Noisy_dec = %d\n", __func__, rssi_min,
+		  dm->noisy_decision);
+	phydm_noisy_enhance_hp_th(dm, dm->noisy_decision);
+#ifndef BB_RAM_SUPPORT
+	/* Response Power */
+	dm->dynamic_tx_high_power_lvl = phydm_pwr_lvl_check(dm, rssi_min);
+	phydm_dynamic_response_power(dm);
+#endif /* #ifndef BB_RAM_SUPPORT */
+	/* Per STA Tx power */
+	for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) {
+		phydm_dtp_per_sta(dm, i);
+		cnt++;
+		if (cnt >= dm->number_linked_client)
+			break;
+	}
+}
+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
+
+void phydm_dynamic_tx_power_init_win(void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	void *adapter = dm->adapter;
+	PMGNT_INFO mgnt_info = &((PADAPTER)adapter)->MgntInfo;
+	HAL_DATA_TYPE *hal_data = GET_HAL_DATA((PADAPTER)adapter);
+
+	mgnt_info->bDynamicTxPowerEnable = false;
+
+	#if DEV_BUS_TYPE == RT_USB_INTERFACE
+	if (RT_GetInterfaceSelection((PADAPTER)adapter) ==
+	    INTF_SEL1_USB_High_Power) {
+		mgnt_info->bDynamicTxPowerEnable = true;
+	}
+	#endif
+
+	hal_data->LastDTPLvl = tx_high_pwr_level_normal;
+	hal_data->DynamicTxHighPowerLvl = tx_high_pwr_level_normal;
+
+	PHYDM_DBG(dm, DBG_DYN_TXPWR, "[%s] DTP=%d\n", __func__,
+		  mgnt_info->bDynamicTxPowerEnable);
+}
+
+void phydm_dynamic_tx_power_win(void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+
+	if (!(dm->support_ability & ODM_BB_DYNAMIC_TXPWR))
+		return;
+
+	#if (RTL8814A_SUPPORT == 1)
+	if (dm->support_ic_type == ODM_RTL8814A)
+		odm_dynamic_tx_power_8814a(dm);
+	#endif
+
+	#if (RTL8821A_SUPPORT == 1)
+	if (dm->support_ic_type & ODM_RTL8821) {
+		void *adapter = dm->adapter;
+		PMGNT_INFO mgnt_info = GetDefaultMgntInfo((PADAPTER)adapter);
+
+		if (mgnt_info->RegRspPwr == 1) {
+			if (dm->rssi_min > 60) {
+				/*Resp TXAGC offset = -3dB*/
+				odm_set_mac_reg(dm, 0x6d8, 0x1C0000, 1);
+			} else if (dm->rssi_min < 55) {
+				/*Resp TXAGC offset = 0dB*/
+				odm_set_mac_reg(dm, 0x6d8, 0x1C0000, 0);
+			}
+		}
+	}
+	#endif
+}
+#endif /*@#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)*/
+#endif /* @#ifdef CONFIG_DYNAMIC_TX_TWR */
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/phydm_dynamictxpower.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/phydm_dynamictxpower.h
--- linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/phydm_dynamictxpower.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/phydm_dynamictxpower.h	2020-04-10 16:35:06.824660441 +0300
@@ -0,0 +1,103 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017  Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * The full GNU General Public License is included in this distribution in the
+ * file called LICENSE.
+ *
+ * Contact Information:
+ * wlanfae <wlanfae@realtek.com>
+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
+ * Hsinchu 300, Taiwan.
+ *
+ * Larry Finger <Larry.Finger@lwfinger.net>
+ *
+ *****************************************************************************/
+
+#ifndef __PHYDMDYNAMICTXPOWER_H__
+#define __PHYDMDYNAMICTXPOWER_H__
+
+#ifdef CONFIG_DYNAMIC_TX_TWR
+/* @============================================================
+ *  Definition
+ * ============================================================
+ */
+
+/*@#define DYNAMIC_TXPWR_VERSION	"1.0"*/
+/*@#define DYNAMIC_TXPWR_VERSION	"1.3" */ /*@2015.08.26, Add 8814 Dynamic TX power*/
+#define DYNAMIC_TXPWR_VERSION "1.4" /*@2015.11.06, Add CE 8821A Dynamic TX power*/
+
+#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
+#define TX_POWER_NEAR_FIELD_THRESH_LVL2 74
+#define TX_POWER_NEAR_FIELD_THRESH_LVL1 60
+#define TX_POWER_NEAR_FIELD_THRESH_AP 0x3F
+#elif (DM_ODM_SUPPORT_TYPE == ODM_WIN)
+#define TX_POWER_NEAR_FIELD_THRESH_LVL2 74
+#define TX_POWER_NEAR_FIELD_THRESH_LVL1 67
+#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
+#define TX_POWER_NEAR_FIELD_THRESH_LVL2 74
+#define TX_POWER_NEAR_FIELD_THRESH_LVL1 60
+#endif
+
+#define tx_high_pwr_level_normal 0
+#define tx_high_pwr_level_level1 1
+#define tx_high_pwr_level_level2 2
+#define tx_high_pwr_level_level3 3
+#define tx_high_pwr_level_unchange 4
+
+/* @============================================================
+ * enumrate
+ * ============================================================
+ */
+enum phydm_dtp_power_offset {
+	PHYDM_OFFSET_ZERO = 0,
+	PHYDM_OFFSET_MINUS_3DB = 1,
+	PHYDM_OFFSET_MINUS_7DB = 2,
+	PHYDM_OFFSET_MINUS_11DB = 3,
+	PHYDM_OFFSET_ADD_3DB = 4,
+	PHYDM_OFFSET_ADD_6DB = 5
+};
+
+enum phydm_dtp_power_offset_2ndtype {
+	PHYDM_2ND_OFFSET_ZERO = 0,
+	PHYDM_2ND_OFFSET_MINUS_3DB = 2,
+	PHYDM_2ND_OFFSET_MINUS_7DB = 3,
+	PHYDM_2ND_OFFSET_MINUS_11DB = 1
+};
+
+
+/* @============================================================
+ *  structure
+ * ============================================================
+ */
+
+/* @============================================================
+ *  Function Prototype
+ * ============================================================
+ */
+
+extern void
+odm_set_dyntxpwr(void *dm_void, u8 *desc, u8 mac_id);
+
+void phydm_dynamic_tx_power(void *dm_void);
+
+void phydm_dynamic_tx_power_init(void *dm_void);
+
+void phydm_dtp_debug(void *dm_void, char input[][16], u32 *_used, char *output,
+			     u32 *_out_len);
+
+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
+void odm_dynamic_tx_power_win(void *dm_void);
+#endif
+
+#endif
+#endif
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/phydm_edcaturbocheck.c linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/phydm_edcaturbocheck.c
--- linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/phydm_edcaturbocheck.c	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/phydm_edcaturbocheck.c	2020-04-10 16:35:06.824660441 +0300
@@ -0,0 +1,698 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
+ *
+ *
+ ******************************************************************************/
+
+/* ************************************************************
+ * include files
+ * ************************************************************ */
+#include "mp_precomp.h"
+#include "phydm_precomp.h"
+
+#if PHYDM_SUPPORT_EDCA
+
+void
+odm_edca_turbo_init(
+	void		*p_dm_void)
+{
+	struct PHY_DM_STRUCT		*p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
+
+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
+	struct _ADAPTER	*adapter = NULL;
+	HAL_DATA_TYPE	*p_hal_data = NULL;
+
+	if (p_dm_odm->adapter == NULL)	{
+		ODM_RT_TRACE(p_dm_odm, ODM_COMP_EDCA_TURBO, ODM_DBG_LOUD, ("EdcaTurboInit fail!!!\n"));
+		return;
+	}
+
+	adapter = p_dm_odm->adapter;
+	p_hal_data = GET_HAL_DATA(adapter);
+
+	p_dm_odm->dm_edca_table.is_current_turbo_edca = false;
+	p_dm_odm->dm_edca_table.is_cur_rdl_state = false;
+	p_hal_data->is_any_non_be_pkts = false;
+
+#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
+	struct _ADAPTER	*adapter = p_dm_odm->adapter;
+	p_dm_odm->dm_edca_table.is_current_turbo_edca = false;
+	p_dm_odm->dm_edca_table.is_cur_rdl_state = false;
+	adapter->recvpriv.is_any_non_be_pkts = false;
+
+#endif
+	ODM_RT_TRACE(p_dm_odm, ODM_COMP_EDCA_TURBO, ODM_DBG_LOUD, ("Orginial VO PARAM: 0x%x\n", odm_read_4byte(p_dm_odm, ODM_EDCA_VO_PARAM)));
+	ODM_RT_TRACE(p_dm_odm, ODM_COMP_EDCA_TURBO, ODM_DBG_LOUD, ("Orginial VI PARAM: 0x%x\n", odm_read_4byte(p_dm_odm, ODM_EDCA_VI_PARAM)));
+	ODM_RT_TRACE(p_dm_odm, ODM_COMP_EDCA_TURBO, ODM_DBG_LOUD, ("Orginial BE PARAM: 0x%x\n", odm_read_4byte(p_dm_odm, ODM_EDCA_BE_PARAM)));
+	ODM_RT_TRACE(p_dm_odm, ODM_COMP_EDCA_TURBO, ODM_DBG_LOUD, ("Orginial BK PARAM: 0x%x\n", odm_read_4byte(p_dm_odm, ODM_EDCA_BK_PARAM)));
+
+
+}	/* ODM_InitEdcaTurbo */
+
+void
+odm_edca_turbo_check(
+	void		*p_dm_void
+)
+{
+	/*  */
+	/* For AP/ADSL use struct rtl8192cd_priv* */
+	/* For CE/NIC use struct _ADAPTER* */
+	/*  */
+
+	/*  */
+	/* 2011/09/29 MH In HW integration first stage, we provide 4 different handle to operate */
+	/* at the same time. In the stage2/3, we need to prive universal interface and merge all */
+	/* HW dynamic mechanism. */
+	/*  */
+	struct PHY_DM_STRUCT		*p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
+	ODM_RT_TRACE(p_dm_odm, ODM_COMP_EDCA_TURBO, ODM_DBG_LOUD, ("odm_edca_turbo_check========================>\n"));
+
+	if (!(p_dm_odm->support_ability & ODM_MAC_EDCA_TURBO))
+		return;
+
+	switch	(p_dm_odm->support_platform) {
+	case	ODM_WIN:
+
+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
+		odm_edca_turbo_check_mp(p_dm_odm);
+#endif
+		break;
+
+	case	ODM_CE:
+#if (DM_ODM_SUPPORT_TYPE == ODM_CE)
+		odm_edca_turbo_check_ce(p_dm_odm);
+#endif
+		break;
+	}
+	ODM_RT_TRACE(p_dm_odm, ODM_COMP_EDCA_TURBO, ODM_DBG_LOUD, ("<========================odm_edca_turbo_check\n"));
+
+}	/* odm_CheckEdcaTurbo */
+
+#if (DM_ODM_SUPPORT_TYPE == ODM_CE)
+
+
+void
+odm_edca_turbo_check_ce(
+	void		*p_dm_void
+)
+{
+	struct PHY_DM_STRUCT		*p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
+	struct _ADAPTER		*adapter = p_dm_odm->adapter;
+	u32	EDCA_BE_UL = 0x5ea42b;/* Parameter suggested by Scott  */ /* edca_setting_UL[p_mgnt_info->iot_peer]; */
+	u32	EDCA_BE_DL = 0x00a42b;/* Parameter suggested by Scott  */ /* edca_setting_DL[p_mgnt_info->iot_peer]; */
+	u32	ic_type = p_dm_odm->support_ic_type;
+	u32	iot_peer = 0;
+	u8	wireless_mode = 0xFF;                 /* invalid value */
+	u32	traffic_index;
+	u32	edca_param;
+	u64	cur_tx_bytes = 0;
+	u64	cur_rx_bytes = 0;
+	u8	bbtchange = _TRUE;
+	u8	is_bias_on_rx = _FALSE;
+	HAL_DATA_TYPE		*p_hal_data = GET_HAL_DATA(adapter);
+	struct dvobj_priv		*pdvobjpriv = adapter_to_dvobj(adapter);
+	struct xmit_priv		*pxmitpriv = &(adapter->xmitpriv);
+	struct recv_priv		*precvpriv = &(adapter->recvpriv);
+	struct registry_priv	*pregpriv = &adapter->registrypriv;
+	struct mlme_ext_priv	*pmlmeext = &(adapter->mlmeextpriv);
+	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
+
+	if (p_dm_odm->is_linked != _TRUE) {
+		precvpriv->is_any_non_be_pkts = _FALSE;
+		return;
+	}
+
+	if ((pregpriv->wifi_spec == 1)) { /* || (pmlmeinfo->HT_enable == 0)) */
+		precvpriv->is_any_non_be_pkts = _FALSE;
+		return;
+	}
+
+	if (p_dm_odm->p_wireless_mode != NULL)
+		wireless_mode = *(p_dm_odm->p_wireless_mode);
+
+	iot_peer = pmlmeinfo->assoc_AP_vendor;
+
+	if (iot_peer >=  HT_IOT_PEER_MAX) {
+		precvpriv->is_any_non_be_pkts = _FALSE;
+		return;
+	}
+
+	if (p_dm_odm->support_ic_type & ODM_RTL8188E) {
+		if ((iot_peer == HT_IOT_PEER_RALINK) || (iot_peer == HT_IOT_PEER_ATHEROS))
+			is_bias_on_rx = _TRUE;
+	}
+
+	/* Check if the status needs to be changed. */
+	if ((bbtchange) || (!precvpriv->is_any_non_be_pkts)) {
+		cur_tx_bytes = pdvobjpriv->traffic_stat.cur_tx_bytes;
+		cur_rx_bytes = pdvobjpriv->traffic_stat.cur_rx_bytes;
+
+		/* traffic, TX or RX */
+		if (is_bias_on_rx) {
+			if (cur_tx_bytes > (cur_rx_bytes << 2)) {
+				/* Uplink TP is present. */
+				traffic_index = UP_LINK;
+			} else {
+				/* Balance TP is present. */
+				traffic_index = DOWN_LINK;
+			}
+		} else {
+			if (cur_rx_bytes > (cur_tx_bytes << 2)) {
+				/* Downlink TP is present. */
+				traffic_index = DOWN_LINK;
+			} else {
+				/* Balance TP is present. */
+				traffic_index = UP_LINK;
+			}
+		}
+
+		/* if ((p_dm_odm->dm_edca_table.prv_traffic_idx != traffic_index) || (!p_dm_odm->dm_edca_table.is_current_turbo_edca)) */
+		{
+			if (p_dm_odm->support_interface == ODM_ITRF_PCIE) {
+				EDCA_BE_UL = 0x6ea42b;
+				EDCA_BE_DL = 0x6ea42b;
+			}
+
+			/* 92D txop can't be set to 0x3e for cisco1250 */
+			if ((iot_peer == HT_IOT_PEER_CISCO) && (wireless_mode == ODM_WM_N24G)) {
+				EDCA_BE_DL = edca_setting_DL[iot_peer];
+				EDCA_BE_UL = edca_setting_UL[iot_peer];
+			}
+			/* merge from 92s_92c_merge temp brunch v2445    20120215 */
+			else if ((iot_peer == HT_IOT_PEER_CISCO) && ((wireless_mode == ODM_WM_G) || (wireless_mode == (ODM_WM_B | ODM_WM_G)) || (wireless_mode == ODM_WM_A) || (wireless_mode == ODM_WM_B)))
+				EDCA_BE_DL = edca_setting_dl_g_mode[iot_peer];
+			else if ((iot_peer == HT_IOT_PEER_AIRGO) && ((wireless_mode == ODM_WM_G) || (wireless_mode == ODM_WM_A)))
+				EDCA_BE_DL = 0xa630;
+			else if (iot_peer == HT_IOT_PEER_MARVELL) {
+				EDCA_BE_DL = edca_setting_DL[iot_peer];
+				EDCA_BE_UL = edca_setting_UL[iot_peer];
+			} else if (iot_peer == HT_IOT_PEER_ATHEROS) {
+				/* Set DL EDCA for Atheros peer to 0x3ea42b. Suggested by SD3 Wilson for ASUS TP issue. */
+				EDCA_BE_DL = edca_setting_DL[iot_peer];
+			}
+
+			if ((ic_type == ODM_RTL8812) || (ic_type == ODM_RTL8821) || (ic_type == ODM_RTL8192E)) { /* add 8812AU/8812AE */
+				EDCA_BE_UL = 0x5ea42b;
+				EDCA_BE_DL = 0x5ea42b;
+
+				ODM_RT_TRACE(p_dm_odm, ODM_COMP_EDCA_TURBO, ODM_DBG_LOUD, ("8812A: EDCA_BE_UL=0x%x EDCA_BE_DL =0x%x", EDCA_BE_UL, EDCA_BE_DL));
+			}
+
+			if (traffic_index == DOWN_LINK)
+				edca_param = EDCA_BE_DL;
+			else
+				edca_param = EDCA_BE_UL;
+
+			rtw_write32(adapter, REG_EDCA_BE_PARAM, edca_param);
+
+			p_dm_odm->dm_edca_table.prv_traffic_idx = traffic_index;
+		}
+
+		p_dm_odm->dm_edca_table.is_current_turbo_edca = _TRUE;
+	} else {
+		/*  */
+		/* Turn Off EDCA turbo here. */
+		/* Restore original EDCA according to the declaration of AP. */
+		/*  */
+		if (p_dm_odm->dm_edca_table.is_current_turbo_edca) {
+			rtw_write32(adapter, REG_EDCA_BE_PARAM, p_hal_data->ac_param_be);
+			p_dm_odm->dm_edca_table.is_current_turbo_edca = _FALSE;
+		}
+	}
+
+}
+
+
+#elif (DM_ODM_SUPPORT_TYPE == ODM_WIN)
+void
+odm_edca_turbo_check_mp(
+	void		*p_dm_void
+)
+{
+
+	struct PHY_DM_STRUCT		*p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
+	struct _ADAPTER		*adapter = p_dm_odm->adapter;
+	HAL_DATA_TYPE		*p_hal_data = GET_HAL_DATA(adapter);
+
+	struct _ADAPTER			*p_default_adapter = get_default_adapter(adapter);
+	struct _ADAPTER			*p_ext_adapter = get_first_ext_adapter(adapter); /* NULL; */
+	PMGNT_INFO			p_mgnt_info = &adapter->MgntInfo;
+	PSTA_QOS			p_sta_qos = adapter->MgntInfo.p_sta_qos;
+	/* [Win7 count Tx/Rx statistic for Extension Port] odm_CheckEdcaTurbo's adapter is always Default. 2009.08.20, by Bohn */
+	u64				ext_cur_tx_ok_cnt = 0;
+	u64				ext_cur_rx_ok_cnt = 0;
+	/* For future Win7  Enable Default Port to modify AMPDU size dynamically, 2009.08.20, Bohn. */
+	u8 two_port_status = (u8)TWO_PORT_STATUS__WITHOUT_ANY_ASSOCIATE;
+
+	/* Keep past Tx/Rx packet count for RT-to-RT EDCA turbo. */
+	u64				cur_tx_ok_cnt = 0;
+	u64				cur_rx_ok_cnt = 0;
+	u32				EDCA_BE_UL = 0x5ea42b;/* Parameter suggested by Scott  */ /* edca_setting_UL[p_mgnt_info->iot_peer]; */
+	u32				EDCA_BE_DL = 0x5ea42b;/* Parameter suggested by Scott  */ /* edca_setting_DL[p_mgnt_info->iot_peer]; */
+	u32                         EDCA_BE = 0x5ea42b;
+	u8                         iot_peer = 0;
+	boolean                      *p_is_cur_rdl_state = NULL;
+	boolean                      is_last_is_cur_rdl_state = false;
+	boolean				 is_bias_on_rx = false;
+	boolean				is_edca_turbo_on = false;
+	u8				tx_rate = 0xFF;
+	u64				value64;
+
+	ODM_RT_TRACE(p_dm_odm, ODM_COMP_EDCA_TURBO, ODM_DBG_LOUD, ("odm_edca_turbo_check_mp========================>"));
+	ODM_RT_TRACE(p_dm_odm, ODM_COMP_EDCA_TURBO, ODM_DBG_LOUD, ("Orginial BE PARAM: 0x%x\n", odm_read_4byte(p_dm_odm, ODM_EDCA_BE_PARAM)));
+
+	/* *******************************
+	 * list paramter for different platform
+	 * ******************************* */
+	is_last_is_cur_rdl_state = p_dm_odm->dm_edca_table.is_cur_rdl_state;
+	p_is_cur_rdl_state = &(p_dm_odm->dm_edca_table.is_cur_rdl_state);
+
+	/* 2012/09/14 MH Add */
+	if (p_mgnt_info->num_non_be_pkt > p_mgnt_info->reg_edca_thresh && !(adapter->MgntInfo.wifi_confg & RT_WIFI_LOGO))
+		p_hal_data->is_any_non_be_pkts = true;
+
+	p_mgnt_info->num_non_be_pkt = 0;
+
+	/* Caculate TX/RX TP: */
+	cur_tx_ok_cnt = p_dm_odm->cur_tx_ok_cnt;
+	cur_rx_ok_cnt = p_dm_odm->cur_rx_ok_cnt;
+
+
+	if (p_ext_adapter == NULL)
+		p_ext_adapter = p_default_adapter;
+
+	ext_cur_tx_ok_cnt = p_ext_adapter->tx_stats.num_tx_bytes_unicast - p_mgnt_info->ext_last_tx_ok_cnt;
+	ext_cur_rx_ok_cnt = p_ext_adapter->rx_stats.num_rx_bytes_unicast - p_mgnt_info->ext_last_rx_ok_cnt;
+	get_two_port_shared_resource(adapter, TWO_PORT_SHARED_OBJECT__STATUS, NULL, &two_port_status);
+	/* For future Win7  Enable Default Port to modify AMPDU size dynamically, 2009.08.20, Bohn. */
+	if (two_port_status == TWO_PORT_STATUS__EXTENSION_ONLY) {
+		cur_tx_ok_cnt = ext_cur_tx_ok_cnt ;
+		cur_rx_ok_cnt = ext_cur_rx_ok_cnt ;
+	}
+	/*  */
+	iot_peer = p_mgnt_info->iot_peer;
+	is_bias_on_rx = (p_mgnt_info->iot_action & HT_IOT_ACT_EDCA_BIAS_ON_RX) ? true : false;
+	is_edca_turbo_on = ((!p_hal_data->is_any_non_be_pkts)) ? true : false;
+	ODM_RT_TRACE(p_dm_odm, ODM_COMP_EDCA_TURBO, ODM_DBG_LOUD, ("is_any_non_be_pkts : 0x%lx\n", p_hal_data->is_any_non_be_pkts));
+
+
+	/* *******************************
+	 * check if edca turbo is disabled
+	 * ******************************* */
+	if (odm_is_edca_turbo_disable(p_dm_odm)) {
+		p_hal_data->is_any_non_be_pkts = false;
+		p_mgnt_info->last_tx_ok_cnt = adapter->tx_stats.num_tx_bytes_unicast;
+		p_mgnt_info->last_rx_ok_cnt = adapter->rx_stats.num_rx_bytes_unicast;
+		p_mgnt_info->ext_last_tx_ok_cnt = p_ext_adapter->tx_stats.num_tx_bytes_unicast;
+		p_mgnt_info->ext_last_rx_ok_cnt = p_ext_adapter->rx_stats.num_rx_bytes_unicast;
+
+	}
+
+	/* *******************************
+	 * remove iot case out
+	 * ******************************* */
+	odm_edca_para_sel_by_iot(p_dm_odm, &EDCA_BE_UL, &EDCA_BE_DL);
+
+
+	/* *******************************
+	 * Check if the status needs to be changed.
+	 * ******************************* */
+	if (is_edca_turbo_on) {
+		ODM_RT_TRACE(p_dm_odm, ODM_COMP_EDCA_TURBO, ODM_DBG_LOUD, ("is_edca_turbo_on : 0x%x is_bias_on_rx : 0x%x\n", is_edca_turbo_on, is_bias_on_rx));
+		ODM_RT_TRACE(p_dm_odm, ODM_COMP_EDCA_TURBO, ODM_DBG_LOUD, ("cur_tx_ok_cnt : 0x%lx\n", cur_tx_ok_cnt));
+		ODM_RT_TRACE(p_dm_odm, ODM_COMP_EDCA_TURBO, ODM_DBG_LOUD, ("cur_rx_ok_cnt : 0x%lx\n", cur_rx_ok_cnt));
+		if (is_bias_on_rx)
+			odm_edca_choose_traffic_idx(p_dm_odm, cur_tx_ok_cnt, cur_rx_ok_cnt,   true,  p_is_cur_rdl_state);
+		else
+			odm_edca_choose_traffic_idx(p_dm_odm, cur_tx_ok_cnt, cur_rx_ok_cnt,   false,  p_is_cur_rdl_state);
+
+		/* modify by Guo.Mingzhi 2011-12-29 */
+		if (adapter->AP_EDCA_PARAM[0] != EDCA_BE)
+			EDCA_BE = adapter->AP_EDCA_PARAM[0];
+		else
+			EDCA_BE = ((*p_is_cur_rdl_state) == true) ? EDCA_BE_DL : EDCA_BE_UL;
+
+		/*For TPLINK 8188EU test*/
+		if ((IS_HARDWARE_TYPE_8188EU(adapter)) && (p_hal_data->UndecoratedSmoothedPWDB < 28)) { /* Set to origimal EDCA 0x5EA42B now need to update.*/
+
+		} else { /*Use TPLINK preferred EDCA parameters.*/
+			EDCA_BE = p_mgnt_info->EDCABEPara;
+		}
+
+		if (IS_HARDWARE_TYPE_8821U(adapter)) {
+			if (p_mgnt_info->reg_tx_duty_enable) {
+				/* 2013.01.23 LukeLee: debug for 8811AU thermal issue (reduce Tx duty cycle) */
+				if (!p_mgnt_info->forced_data_rate) { /* auto rate */
+					if (p_dm_odm->tx_rate != 0xFF)
+						tx_rate = adapter->HalFunc.GetHwRateFromMRateHandler(p_dm_odm->tx_rate);
+				} else /* force rate */
+					tx_rate = (u8) p_mgnt_info->forced_data_rate;
+
+				value64 = (cur_rx_ok_cnt << 2);
+				if (cur_tx_ok_cnt < value64) /* Downlink */
+					odm_write_4byte(p_dm_odm, ODM_EDCA_BE_PARAM, EDCA_BE);
+				else { /* Uplink */
+					/*dbg_print("p_rf_calibrate_info->thermal_value = 0x%X\n", p_rf_calibrate_info->thermal_value);*/
+					/*if(p_rf_calibrate_info->thermal_value < p_hal_data->eeprom_thermal_meter)*/
+					if ((p_dm_odm->rf_calibrate_info.thermal_value < 0x2c) || (*p_dm_odm->p_band_type == BAND_ON_2_4G))
+						odm_write_4byte(p_dm_odm, ODM_EDCA_BE_PARAM, EDCA_BE);
+					else {
+						switch (tx_rate) {
+						case MGN_VHT1SS_MCS6:
+						case MGN_VHT1SS_MCS5:
+						case MGN_MCS6:
+						case MGN_MCS5:
+						case MGN_48M:
+						case MGN_54M:
+							odm_write_4byte(p_dm_odm, ODM_EDCA_BE_PARAM, 0x1ea42b);
+							break;
+						case MGN_VHT1SS_MCS4:
+						case MGN_MCS4:
+						case MGN_36M:
+							odm_write_4byte(p_dm_odm, ODM_EDCA_BE_PARAM, 0xa42b);
+							break;
+						case MGN_VHT1SS_MCS3:
+						case MGN_MCS3:
+						case MGN_24M:
+							odm_write_4byte(p_dm_odm, ODM_EDCA_BE_PARAM, 0xa47f);
+							break;
+						case MGN_VHT1SS_MCS2:
+						case MGN_MCS2:
+						case MGN_18M:
+							odm_write_4byte(p_dm_odm, ODM_EDCA_BE_PARAM, 0xa57f);
+							break;
+						case MGN_VHT1SS_MCS1:
+						case MGN_MCS1:
+						case MGN_9M:
+						case MGN_12M:
+							odm_write_4byte(p_dm_odm, ODM_EDCA_BE_PARAM, 0xa77f);
+							break;
+						case MGN_VHT1SS_MCS0:
+						case MGN_MCS0:
+						case MGN_6M:
+							odm_write_4byte(p_dm_odm, ODM_EDCA_BE_PARAM, 0xa87f);
+							break;
+						default:
+							odm_write_4byte(p_dm_odm, ODM_EDCA_BE_PARAM, EDCA_BE);
+							break;
+						}
+					}
+				}
+			} else
+				odm_write_4byte(p_dm_odm, ODM_EDCA_BE_PARAM, EDCA_BE);
+
+		} else if (IS_HARDWARE_TYPE_8812AU(adapter)) {
+			if (p_mgnt_info->reg_tx_duty_enable) {
+				/* 2013.07.26 Wilson: debug for 8812AU thermal issue (reduce Tx duty cycle) */
+				/* it;s the same issue as 8811AU */
+				if (!p_mgnt_info->forced_data_rate) { /* auto rate */
+					if (p_dm_odm->tx_rate != 0xFF)
+						tx_rate = adapter->HalFunc.GetHwRateFromMRateHandler(p_dm_odm->tx_rate);
+				} else /* force rate */
+					tx_rate = (u8) p_mgnt_info->forced_data_rate;
+
+				value64 = (cur_rx_ok_cnt << 2);
+				if (cur_tx_ok_cnt < value64) /* Downlink */
+					odm_write_4byte(p_dm_odm, ODM_EDCA_BE_PARAM, EDCA_BE);
+				else { /* Uplink */
+					/*dbg_print("p_rf_calibrate_info->thermal_value = 0x%X\n", p_rf_calibrate_info->thermal_value);*/
+					/*if(p_rf_calibrate_info->thermal_value < p_hal_data->eeprom_thermal_meter)*/
+					if ((p_dm_odm->rf_calibrate_info.thermal_value < 0x2c) || (*p_dm_odm->p_band_type == BAND_ON_2_4G))
+						odm_write_4byte(p_dm_odm, ODM_EDCA_BE_PARAM, EDCA_BE);
+					else {
+						switch (tx_rate) {
+						case MGN_VHT2SS_MCS9:
+						case MGN_VHT1SS_MCS9:
+						case MGN_VHT1SS_MCS8:
+						case MGN_MCS15:
+						case MGN_MCS7:
+							odm_write_4byte(p_dm_odm, ODM_EDCA_BE_PARAM, 0x1ea44f);
+						case MGN_VHT2SS_MCS8:
+						case MGN_VHT1SS_MCS7:
+						case MGN_MCS14:
+						case MGN_MCS6:
+						case MGN_54M:
+							odm_write_4byte(p_dm_odm, ODM_EDCA_BE_PARAM, 0xa44f);
+						case MGN_VHT2SS_MCS7:
+						case MGN_VHT2SS_MCS6:
+						case MGN_VHT1SS_MCS6:
+						case MGN_VHT1SS_MCS5:
+						case MGN_MCS13:
+						case MGN_MCS5:
+						case MGN_48M:
+							odm_write_4byte(p_dm_odm, ODM_EDCA_BE_PARAM, 0xa630);
+							break;
+						case MGN_VHT2SS_MCS5:
+						case MGN_VHT2SS_MCS4:
+						case MGN_VHT1SS_MCS4:
+						case MGN_VHT1SS_MCS3:
+						case MGN_MCS12:
+						case MGN_MCS4:
+						case MGN_MCS3:
+						case MGN_36M:
+						case MGN_24M:
+							odm_write_4byte(p_dm_odm, ODM_EDCA_BE_PARAM, 0xa730);
+							break;
+						case MGN_VHT2SS_MCS3:
+						case MGN_VHT2SS_MCS2:
+						case MGN_VHT2SS_MCS1:
+						case MGN_VHT1SS_MCS2:
+						case MGN_VHT1SS_MCS1:
+						case MGN_MCS11:
+						case MGN_MCS10:
+						case MGN_MCS9:
+						case MGN_MCS2:
+						case MGN_MCS1:
+						case MGN_18M:
+						case MGN_12M:
+							odm_write_4byte(p_dm_odm, ODM_EDCA_BE_PARAM, 0xa830);
+							break;
+						case MGN_VHT2SS_MCS0:
+						case MGN_VHT1SS_MCS0:
+						case MGN_MCS0:
+						case MGN_MCS8:
+						case MGN_9M:
+						case MGN_6M:
+							odm_write_4byte(p_dm_odm, ODM_EDCA_BE_PARAM, 0xa87f);
+							break;
+						default:
+							odm_write_4byte(p_dm_odm, ODM_EDCA_BE_PARAM, EDCA_BE);
+							break;
+						}
+					}
+				}
+			} else
+				odm_write_4byte(p_dm_odm, ODM_EDCA_BE_PARAM, EDCA_BE);
+		} else
+			odm_write_4byte(p_dm_odm, ODM_EDCA_BE_PARAM, EDCA_BE);
+
+		ODM_RT_TRACE(p_dm_odm, ODM_COMP_EDCA_TURBO, ODM_DBG_LOUD, ("EDCA Turbo on: EDCA_BE:0x%lx\n", EDCA_BE));
+
+		p_dm_odm->dm_edca_table.is_current_turbo_edca = true;
+
+		ODM_RT_TRACE(p_dm_odm, ODM_COMP_EDCA_TURBO, ODM_DBG_LOUD, ("EDCA_BE_DL : 0x%lx  EDCA_BE_UL : 0x%lx  EDCA_BE : 0x%lx\n", EDCA_BE_DL, EDCA_BE_UL, EDCA_BE));
+
+	} else {
+		/* Turn Off EDCA turbo here. */
+		/* Restore original EDCA according to the declaration of AP. */
+		if (p_dm_odm->dm_edca_table.is_current_turbo_edca) {
+			phydm_set_hw_reg_handler_interface(p_dm_odm, HW_VAR_AC_PARAM, GET_WMM_PARAM_ELE_SINGLE_AC_PARAM(p_sta_qos->wmm_param_ele, AC0_BE));
+
+			p_dm_odm->dm_edca_table.is_current_turbo_edca = false;
+			ODM_RT_TRACE(p_dm_odm, ODM_COMP_EDCA_TURBO, ODM_DBG_LOUD, ("Restore EDCA BE: 0x%lx\n", p_dm_odm->WMMEDCA_BE));
+
+		}
+	}
+
+}
+
+
+/* check if edca turbo is disabled */
+boolean
+odm_is_edca_turbo_disable(
+	void		*p_dm_void
+)
+{
+	struct PHY_DM_STRUCT		*p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
+	struct _ADAPTER		*adapter = p_dm_odm->adapter;
+	PMGNT_INFO			p_mgnt_info = &adapter->MgntInfo;
+	u32				iot_peer = p_mgnt_info->iot_peer;
+
+	if (p_dm_odm->is_bt_disable_edca_turbo) {
+		ODM_RT_TRACE(p_dm_odm, ODM_COMP_EDCA_TURBO, ODM_DBG_LOUD, ("EdcaTurboDisable for BT!!\n"));
+		return true;
+	}
+
+	if ((!(p_dm_odm->support_ability & ODM_MAC_EDCA_TURBO)) ||
+	    (p_dm_odm->wifi_test & RT_WIFI_LOGO) ||
+	    (iot_peer >= HT_IOT_PEER_MAX)) {
+		ODM_RT_TRACE(p_dm_odm, ODM_COMP_EDCA_TURBO, ODM_DBG_LOUD, ("EdcaTurboDisable\n"));
+		return true;
+	}
+
+
+	/* 1. We do not turn on EDCA turbo mode for some AP that has IOT issue */
+	/* 2. User may disable EDCA Turbo mode with OID settings. */
+	if (p_mgnt_info->iot_action & HT_IOT_ACT_DISABLE_EDCA_TURBO) {
+		ODM_RT_TRACE(p_dm_odm, ODM_COMP_EDCA_TURBO, ODM_DBG_LOUD, ("iot_action:EdcaTurboDisable\n"));
+		return	true;
+	}
+
+	return	false;
+
+
+}
+
+/* add iot case here: for MP/CE */
+void
+odm_edca_para_sel_by_iot(
+	void		*p_dm_void,
+	u32		*EDCA_BE_UL,
+	u32		*EDCA_BE_DL
+)
+{
+	struct PHY_DM_STRUCT		*p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
+	struct _ADAPTER		*adapter = p_dm_odm->adapter;
+	u32                         iot_peer = 0;
+	u32                         ic_type = p_dm_odm->support_ic_type;
+	u8                         wireless_mode = 0xFF;                 /* invalid value */
+	u32                         iot_peer_sub_type = 0;
+
+	PMGNT_INFO			p_mgnt_info = &adapter->MgntInfo;
+	u8				two_port_status = (u8)TWO_PORT_STATUS__WITHOUT_ANY_ASSOCIATE;
+
+	if (p_dm_odm->p_wireless_mode != NULL)
+		wireless_mode = *(p_dm_odm->p_wireless_mode);
+
+	/* ========================================================= */
+	/* list paramter for different platform */
+
+	iot_peer = p_mgnt_info->iot_peer;
+	iot_peer_sub_type = p_mgnt_info->iot_peer_subtype;
+	get_two_port_shared_resource(adapter, TWO_PORT_SHARED_OBJECT__STATUS, NULL, &two_port_status);
+
+	/* ****************************
+	 * / IOT case for MP
+	 * **************************** */
+	if (p_dm_odm->support_interface == ODM_ITRF_PCIE) {
+		(*EDCA_BE_UL) = 0x6ea42b;
+		(*EDCA_BE_DL) = 0x6ea42b;
+	}
+
+	if (two_port_status == TWO_PORT_STATUS__EXTENSION_ONLY) {
+		(*EDCA_BE_UL) = 0x5ea42b;/* Parameter suggested by Scott  */ /* edca_setting_UL[ExtAdapter->mgnt_info.iot_peer]; */
+		(*EDCA_BE_DL) = 0x5ea42b;/* Parameter suggested by Scott  */ /* edca_setting_DL[ExtAdapter->mgnt_info.iot_peer]; */
+	}
+
+#if (INTEL_PROXIMITY_SUPPORT == 1)
+	if (p_mgnt_info->intel_class_mode_info.is_enable_ca == true)
+		(*EDCA_BE_UL) = (*EDCA_BE_DL) = 0xa44f;
+	else
+#endif
+	{
+		if ((p_mgnt_info->iot_action & (HT_IOT_ACT_FORCED_ENABLE_BE_TXOP | HT_IOT_ACT_AMSDU_ENABLE))) {
+			/* To check whether we shall force turn on TXOP configuration. */
+			if (!((*EDCA_BE_UL) & 0xffff0000))
+				(*EDCA_BE_UL) |= 0x005e0000; /* Force TxOP limit to 0x005e for UL. */
+			if (!((*EDCA_BE_DL) & 0xffff0000))
+				(*EDCA_BE_DL) |= 0x005e0000; /* Force TxOP limit to 0x005e for DL. */
+		}
+
+		/* 92D txop can't be set to 0x3e for cisco1250 */
+		if ((iot_peer == HT_IOT_PEER_CISCO) && (wireless_mode == ODM_WM_N24G)) {
+			(*EDCA_BE_DL) = edca_setting_DL[iot_peer];
+			(*EDCA_BE_UL) = edca_setting_UL[iot_peer];
+		}
+		/* merge from 92s_92c_merge temp brunch v2445    20120215 */
+		else if ((iot_peer == HT_IOT_PEER_CISCO) && ((wireless_mode == ODM_WM_G) || (wireless_mode == (ODM_WM_B | ODM_WM_G)) || (wireless_mode == ODM_WM_A) || (wireless_mode == ODM_WM_B)))
+			(*EDCA_BE_DL) = edca_setting_dl_g_mode[iot_peer];
+		else if ((iot_peer == HT_IOT_PEER_AIRGO) && ((wireless_mode == ODM_WM_G) || (wireless_mode == ODM_WM_A)))
+			(*EDCA_BE_DL) = 0xa630;
+
+		else if (iot_peer == HT_IOT_PEER_MARVELL) {
+			(*EDCA_BE_DL) = edca_setting_DL[iot_peer];
+			(*EDCA_BE_UL) = edca_setting_UL[iot_peer];
+		} else if (iot_peer == HT_IOT_PEER_ATHEROS && iot_peer_sub_type != HT_IOT_PEER_TPLINK_AC1750) {
+			/* Set DL EDCA for Atheros peer to 0x3ea42b. Suggested by SD3 Wilson for ASUS TP issue. */
+			if (wireless_mode == ODM_WM_G)
+				(*EDCA_BE_DL) = edca_setting_dl_g_mode[iot_peer];
+			else
+				(*EDCA_BE_DL) = edca_setting_DL[iot_peer];
+
+			if (ic_type == ODM_RTL8821)
+				(*EDCA_BE_DL) = 0x5ea630;
+
+		}
+	}
+
+	if ((ic_type == ODM_RTL8812) || (ic_type == ODM_RTL8192E)) {  /* add 8812AU/8812AE */
+		(*EDCA_BE_UL) = 0x5ea42b;
+		(*EDCA_BE_DL) = 0x5ea42b;
+
+		ODM_RT_TRACE(p_dm_odm, ODM_COMP_EDCA_TURBO, ODM_DBG_LOUD, ("8812A: EDCA_BE_UL=0x%lx EDCA_BE_DL =0x%lx\n", (*EDCA_BE_UL), (*EDCA_BE_DL)));
+	}
+
+	if ((ic_type == ODM_RTL8814A) && (iot_peer == HT_IOT_PEER_REALTEK)) {      /*8814AU and 8814AR*/
+		(*EDCA_BE_UL) = 0x5ea42b;
+		(*EDCA_BE_DL) = 0xa42b;
+
+		ODM_RT_TRACE(p_dm_odm, ODM_COMP_EDCA_TURBO, ODM_DBG_LOUD, ("8814A: EDCA_BE_UL=0x%lx EDCA_BE_DL =0x%lx\n", (*EDCA_BE_UL), (*EDCA_BE_DL)));
+	}
+
+	ODM_RT_TRACE(p_dm_odm, ODM_COMP_EDCA_TURBO, ODM_DBG_LOUD, ("Special: EDCA_BE_UL=0x%lx EDCA_BE_DL =0x%lx, iot_peer = %d\n", (*EDCA_BE_UL), (*EDCA_BE_DL), iot_peer));
+
+}
+
+
+void
+odm_edca_choose_traffic_idx(
+	void		*p_dm_void,
+	u64			cur_tx_bytes,
+	u64			cur_rx_bytes,
+	boolean		is_bias_on_rx,
+	boolean		*p_is_cur_rdl_state
+)
+{
+	struct PHY_DM_STRUCT		*p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
+
+	if (is_bias_on_rx) {
+
+		if (cur_tx_bytes > (cur_rx_bytes * 4)) {
+			*p_is_cur_rdl_state = false;
+			ODM_RT_TRACE(p_dm_odm, ODM_COMP_EDCA_TURBO, ODM_DBG_LOUD, ("Uplink Traffic\n "));
+
+		} else {
+			*p_is_cur_rdl_state = true;
+			ODM_RT_TRACE(p_dm_odm, ODM_COMP_EDCA_TURBO, ODM_DBG_LOUD, ("Balance Traffic\n"));
+
+		}
+	} else {
+		if (cur_rx_bytes > (cur_tx_bytes * 4)) {
+			*p_is_cur_rdl_state = true;
+			ODM_RT_TRACE(p_dm_odm, ODM_COMP_EDCA_TURBO, ODM_DBG_LOUD, ("Downlink	Traffic\n"));
+
+		} else {
+			*p_is_cur_rdl_state = false;
+			ODM_RT_TRACE(p_dm_odm, ODM_COMP_EDCA_TURBO, ODM_DBG_LOUD, ("Balance Traffic\n"));
+		}
+	}
+
+	return ;
+}
+
+#endif
+#endif /*PHYDM_SUPPORT_EDCA*/
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/phydm_edcaturbocheck.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/phydm_edcaturbocheck.h
--- linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/phydm_edcaturbocheck.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/phydm_edcaturbocheck.h	2020-04-10 16:35:06.824660441 +0300
@@ -0,0 +1,102 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
+ *
+ *
+ ******************************************************************************/
+
+#ifndef	__PHYDMEDCATURBOCHECK_H__
+#define    __PHYDMEDCATURBOCHECK_H__
+
+#if PHYDM_SUPPORT_EDCA
+/*#define EDCATURBO_VERSION	"2.1"*/
+#define EDCATURBO_VERSION	"2.3"	/*2015.07.29 by YuChen*/
+
+struct _EDCA_TURBO_ {
+	boolean is_current_turbo_edca;
+	boolean is_cur_rdl_state;
+
+#if (DM_ODM_SUPPORT_TYPE == ODM_CE)
+	u32	prv_traffic_idx; /* edca turbo */
+#endif
+
+};
+
+#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
+static u32 edca_setting_UL[HT_IOT_PEER_MAX] =
+	/* UNKNOWN		REALTEK_90	REALTEK_92SE	BROADCOM		RALINK		ATHEROS		CISCO		MERU        MARVELL	92U_AP		SELF_AP(DownLink/Tx) */
+{ 0x5e4322,		0xa44f,		0x5e4322,		0x5ea32b,		0x5ea422,	0x5ea322,	0x3ea430,	0x5ea42b, 0x5ea44f,	0x5e4322,	0x5e4322};
+
+
+static u32 edca_setting_DL[HT_IOT_PEER_MAX] =
+	/* UNKNOWN		REALTEK_90	REALTEK_92SE	BROADCOM		RALINK		ATHEROS		CISCO		MERU,       MARVELL	92U_AP		SELF_AP(UpLink/Rx) */
+{ 0xa44f,		0x5ea44f,	0x5e4322,		0x5ea42b,		0xa44f,		0xa630,		0x5ea630,	0x5ea42b, 0xa44f,		0xa42b,		0xa42b};
+
+static u32 edca_setting_dl_g_mode[HT_IOT_PEER_MAX] =
+	/* UNKNOWN		REALTEK_90	REALTEK_92SE	BROADCOM		RALINK		ATHEROS		CISCO		MERU,       MARVELL	92U_AP		SELF_AP */
+{ 0x4322,		0xa44f,		0x5e4322,		0xa42b,			0x5e4322,	0x4322,		0xa42b,		0x5ea42b, 0xa44f,		0x5e4322,	0x5ea42b};
+
+#endif
+
+
+
+void
+odm_edca_turbo_check(
+	void		*p_dm_void
+);
+void
+odm_edca_turbo_init(
+	void		*p_dm_void
+);
+
+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
+void
+odm_edca_turbo_check_mp(
+	void		*p_dm_void
+);
+
+/* check if edca turbo is disabled */
+boolean
+odm_is_edca_turbo_disable(
+	void		*p_dm_void
+);
+/* choose edca paramter for special IOT case */
+void
+odm_edca_para_sel_by_iot(
+	void					*p_dm_void,
+	u32		*EDCA_BE_UL,
+	u32		*EDCA_BE_DL
+);
+/* check if it is UL or DL */
+void
+odm_edca_choose_traffic_idx(
+	void		*p_dm_void,
+	u64			cur_tx_bytes,
+	u64			cur_rx_bytes,
+	boolean		is_bias_on_rx,
+	boolean		*p_is_cur_rdl_state
+);
+
+#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
+void
+odm_edca_turbo_check_ce(
+	void		*p_dm_void
+);
+#endif
+
+#endif /*PHYDM_SUPPORT_EDCA*/
+
+#endif
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/phydm_features_ap.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/phydm_features_ap.h
--- linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/phydm_features_ap.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/phydm_features_ap.h	2020-04-10 16:35:06.824660441 +0300
@@ -0,0 +1,196 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+
+#ifndef	__PHYDM_FEATURES_AP_H__
+#define __PHYDM_FEATURES_AP_H__
+
+#if (RTL8814A_SUPPORT || RTL8821C_SUPPORT || RTL8822B_SUPPORT ||\
+	RTL8197F_SUPPORT || RTL8192F_SUPPORT || RTL8198F_SUPPORT ||\
+	RTL8822C_SUPPORT)
+	#define PHYDM_LA_MODE_SUPPORT			1
+#else
+	#define PHYDM_LA_MODE_SUPPORT			0
+#endif
+
+#if (RTL8822B_SUPPORT || RTL8812A_SUPPORT || RTL8197F_SUPPORT ||\
+	RTL8192F_SUPPORT)
+	#define DYN_ANT_WEIGHTING_SUPPORT
+#endif
+
+#if (RTL8822B_SUPPORT || RTL8821C_SUPPORT)
+	#define FAHM_SUPPORT
+#endif
+	#define NHM_SUPPORT
+	#define CLM_SUPPORT
+
+#if (RTL8822B_SUPPORT)
+	/*#define PHYDM_PHYSTAUS_SMP_MODE*/
+#endif
+
+#if (RTL8197F_SUPPORT)
+	/*#define PHYDM_TDMA_DIG_SUPPORT*/
+#endif
+
+#if (RTL8198F_SUPPORT || RTL8814B_SUPPORT)
+	/*#define PHYDM_TDMA_DIG_SUPPORT 1*/
+	#ifdef PHYDM_TDMA_DIG_SUPPORT
+	/*#define IS_USE_NEW_TDMA*/ /*new tdma dig test*/
+	#endif
+#endif
+
+#if (RTL8197F_SUPPORT || RTL8822B_SUPPORT ||\
+	RTL8198F_SUPPORT || RTL8814B_SUPPORT)
+	/*#define PHYDM_LNA_SAT_CHK_SUPPORT*/
+	#ifdef PHYDM_LNA_SAT_CHK_SUPPORT
+
+		#if (RTL8197F_SUPPORT)
+		/*#define PHYDM_LNA_SAT_CHK_SUPPORT_TYPE1*/
+		#endif
+
+		#if (RTL8822B_SUPPORT)
+		/*#define PHYDM_LNA_SAT_CHK_TYPE2*/
+		#endif
+
+		#if (RTL8198F_SUPPORT || RTL8814B_SUPPORT)
+		/*#define PHYDM_LNA_SAT_CHK_TYPE1*/
+		#endif
+	#endif
+#endif
+
+#if (RTL8822B_SUPPORT)
+	/*#define PHYDM_POWER_TRAINING_SUPPORT*/
+#endif
+
+#if (RTL8822C_SUPPORT)
+	/* #define PHYDM_PMAC_TX_SETTING_SUPPORT */
+#endif
+
+#if (RTL8822C_SUPPORT)
+	/* #define PHYDM_MP_SUPPORT */
+#endif
+
+#if (RTL8822B_SUPPORT)
+	#define PHYDM_TXA_CALIBRATION
+#endif
+
+#if (RTL8188E_SUPPORT || RTL8197F_SUPPORT || RTL8192F_SUPPORT)
+	#define	PHYDM_PRIMARY_CCA
+#endif
+
+#if (RTL8188F_SUPPORT || RTL8710B_SUPPORT || RTL8821C_SUPPORT ||\
+	RTL8822B_SUPPORT || RTL8192F_SUPPORT)
+	#define	PHYDM_DC_CANCELLATION
+#endif
+
+#if (RTL8822B_SUPPORT || RTL8197F_SUPPORT || RTL8192F_SUPPORT)
+	#define	CONFIG_ADAPTIVE_SOML
+#endif
+
+#if (RTL8812A_SUPPORT || RTL8821A_SUPPORT || RTL8881A_SUPPORT ||\
+	RTL8192E_SUPPORT || RTL8723B_SUPPORT)
+	/*#define	CONFIG_RA_FW_DBG_CODE*/
+#endif
+
+#if (RTL8192F_SUPPORT == 1)
+	/*#define	CONFIG_8912F_SPUR_CALIBRATION*/
+#endif
+
+#if (RTL8822B_SUPPORT == 1)
+	/* #define	CONFIG_8822B_SPUR_CALIBRATION */
+#endif
+
+#ifdef CONFIG_SUPPORT_DYNAMIC_TXPWR
+#define CONFIG_DYNAMIC_TX_TWR
+#endif
+/*#define	CONFIG_PSD_TOOL*/
+#define PHYDM_SUPPORT_CCKPD
+#define PHYDM_SUPPORT_ADAPTIVITY
+/*#define	CONFIG_PATH_DIVERSITY*/
+/*#define	CONFIG_RA_DYNAMIC_RTY_LIMIT*/
+/*#define	CONFIG_RA_DYNAMIC_RATE_ID*/
+#define	CONFIG_BB_TXBF_API
+/*#define	ODM_CONFIG_BT_COEXIST*/
+#define	PHYDM_SUPPORT_RSSI_MONITOR
+#if !defined(CONFIG_DISABLE_PHYDM_DEBUG_FUNCTION)
+	#define CONFIG_PHYDM_DEBUG_FUNCTION
+#endif
+
+/* [ Configure Antenna Diversity ] */
+#if (RTL8188F_SUPPORT)
+	#ifdef CONFIG_ANTENNA_DIVERSITY
+		#define CONFIG_PHYDM_ANTENNA_DIVERSITY
+		#define CONFIG_S0S1_SW_ANTENNA_DIVERSITY
+	#endif
+#endif
+
+#if defined(CONFIG_RTL_8881A_ANT_SWITCH) || defined(CONFIG_SLOT_0_ANT_SWITCH) || defined(CONFIG_SLOT_1_ANT_SWITCH) || defined(CONFIG_RTL_8197F_ANT_SWITCH)
+	#define CONFIG_PHYDM_ANTENNA_DIVERSITY
+	#define ODM_EVM_ENHANCE_ANTDIV
+	#define SKIP_EVM_ANTDIV_TRAINING_PATCH
+
+	/*----------*/
+	#ifdef CONFIG_NO_2G_DIVERSITY_8197F
+		#define CONFIG_NO_2G_DIVERSITY
+	#elif defined(CONFIG_2G_CGCS_RX_DIVERSITY_8197F)
+		#define CONFIG_2G_CGCS_RX_DIVERSITY
+	#elif defined(CONFIG_2G_CG_TRX_DIVERSITY_8197F)
+		#define CONFIG_2G_CG_TRX_DIVERSITY
+	#endif
+
+	#if (!defined(CONFIG_NO_2G_DIVERSITY) && !defined(CONFIG_2G5G_CG_TRX_DIVERSITY_8881A) && !defined(CONFIG_2G_CGCS_RX_DIVERSITY) && !defined(CONFIG_2G_CG_TRX_DIVERSITY) && !defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY))
+		#define CONFIG_NO_2G_DIVERSITY
+	#endif
+
+	#ifdef CONFIG_NO_5G_DIVERSITY_8881A
+		#define CONFIG_NO_5G_DIVERSITY
+	#elif defined(CONFIG_5G_CGCS_RX_DIVERSITY_8881A)
+		#define CONFIG_5G_CGCS_RX_DIVERSITY
+	#elif defined(CONFIG_5G_CG_TRX_DIVERSITY_8881A)
+		#define CONFIG_5G_CG_TRX_DIVERSITY
+	#elif defined(CONFIG_2G5G_CG_TRX_DIVERSITY_8881A)
+		#define CONFIG_2G5G_CG_TRX_DIVERSITY
+	#endif
+	#if (!defined(CONFIG_NO_5G_DIVERSITY) && !defined(CONFIG_5G_CGCS_RX_DIVERSITY) && !defined(CONFIG_5G_CG_TRX_DIVERSITY) && !defined(CONFIG_2G5G_CG_TRX_DIVERSITY) && !defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY))
+		#define CONFIG_NO_5G_DIVERSITY
+	#endif
+	/*----------*/
+	#if (defined(CONFIG_NO_2G_DIVERSITY) && defined(CONFIG_NO_5G_DIVERSITY))
+		#define CONFIG_NOT_SUPPORT_ANTDIV
+	#elif (!defined(CONFIG_NO_2G_DIVERSITY) && defined(CONFIG_NO_5G_DIVERSITY))
+		#define CONFIG_2G_SUPPORT_ANTDIV
+	#elif (defined(CONFIG_NO_2G_DIVERSITY) && !defined(CONFIG_NO_5G_DIVERSITY))
+		#define CONFIG_5G_SUPPORT_ANTDIV
+	#elif ((!defined(CONFIG_NO_2G_DIVERSITY) && !defined(CONFIG_NO_5G_DIVERSITY)) || defined(CONFIG_2G5G_CG_TRX_DIVERSITY))
+			#define CONFIG_2G5G_SUPPORT_ANTDIV
+	#endif
+		/*----------*/
+#endif /*Antenna Diveristy*/
+
+/*[SmartAntenna]*/
+/*#define	CONFIG_SMART_ANTENNA*/
+#ifdef CONFIG_SMART_ANTENNA
+	/*#define	CONFIG_CUMITEK_SMART_ANTENNA*/
+#endif
+#define CFG_DIG_DAMPING_CHK
+/* --------------------------------------------------*/
+#ifdef BEAMFORMING_SUPPORT
+	#if (RTL8192F_SUPPORT || RTL8195B_SUPPORT || RTL8821C_SUPPORT ||\
+	     RTL8822B_SUPPORT || RTL8197F_SUPPORT || RTL8198F_SUPPORT ||\
+	     RTL8822C_SUPPORT || RTL8814B_SUPPORT)
+		#define	DRIVER_BEAMFORMING_VERSION2
+	#endif
+#endif
+
+#endif
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/phydm_features_ce2_kernel.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/phydm_features_ce2_kernel.h
--- linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/phydm_features_ce2_kernel.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/phydm_features_ce2_kernel.h	2020-04-10 16:35:06.825660488 +0300
@@ -0,0 +1,84 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017  Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * The full GNU General Public License is included in this distribution in the
+ * file called LICENSE.
+ *
+ * Contact Information:
+ * wlanfae <wlanfae@realtek.com>
+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
+ * Hsinchu 300, Taiwan.
+ *
+ * Larry Finger <Larry.Finger@lwfinger.net>
+ *
+ *****************************************************************************/
+
+#ifndef __PHYDM_FEATURES_CE_H__
+#define __PHYDM_FEATURES_CE_H__
+
+#define PHYDM_LA_MODE_SUPPORT			0
+
+#if (RTL8822B_SUPPORT || RTL8812A_SUPPORT || RTL8197F_SUPPORT ||\
+	RTL8192F_SUPPORT)
+	#define DYN_ANT_WEIGHTING_SUPPORT
+#endif
+
+#if (RTL8822B_SUPPORT || RTL8821C_SUPPORT)
+	#define FAHM_SUPPORT
+#endif
+	#define NHM_SUPPORT
+	#define CLM_SUPPORT
+
+#if (RTL8822B_SUPPORT)
+	#define PHYDM_TXA_CALIBRATION
+#endif
+
+#if (RTL8188F_SUPPORT || RTL8710B_SUPPORT || RTL8821C_SUPPORT ||\
+	RTL8822B_SUPPORT || RTL8192F_SUPPORT)
+	#define	PHYDM_DC_CANCELLATION
+#endif
+
+#if (RTL8192F_SUPPORT == 1)
+	/*#define	CONFIG_8912F_SPUR_CALIBRATION*/
+#endif
+
+#if (RTL8822B_SUPPORT == 1)
+	/* #define	CONFIG_8822B_SPUR_CALIBRATION */
+#endif
+
+#define PHYDM_SUPPORT_CCKPD
+#define PHYDM_SUPPORT_ADAPTIVITY
+
+#ifdef CONFIG_DFS_MASTER
+	#define CONFIG_PHYDM_DFS_MASTER
+#endif
+
+#define	CONFIG_BB_TXBF_API
+#define	CONFIG_PHYDM_DEBUG_FUNCTION
+
+#ifdef CONFIG_BT_COEXIST
+	#define	ODM_CONFIG_BT_COEXIST
+#endif
+#define	PHYDM_SUPPORT_RSSI_MONITOR
+#define CFG_DIG_DAMPING_CHK
+
+
+#ifdef BEAMFORMING_SUPPORT
+	#if (RTL8192F_SUPPORT || RTL8195B_SUPPORT || RTL8821C_SUPPORT ||\
+	     RTL8822B_SUPPORT || RTL8197F_SUPPORT || RTL8198F_SUPPORT ||\
+	     RTL8822C_SUPPORT || RTL8814B_SUPPORT)
+		#define	DRIVER_BEAMFORMING_VERSION2
+	#endif
+#endif
+
+#endif
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/phydm_features_ce.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/phydm_features_ce.h
--- linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/phydm_features_ce.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/phydm_features_ce.h	2020-04-10 16:35:06.824660441 +0300
@@ -0,0 +1,205 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017  Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * The full GNU General Public License is included in this distribution in the
+ * file called LICENSE.
+ *
+ * Contact Information:
+ * wlanfae <wlanfae@realtek.com>
+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
+ * Hsinchu 300, Taiwan.
+ *
+ * Larry Finger <Larry.Finger@lwfinger.net>
+ *
+ *****************************************************************************/
+
+#ifndef __PHYDM_FEATURES_CE_H__
+#define __PHYDM_FEATURES_CE_H__
+
+#if (RTL8814A_SUPPORT || RTL8821C_SUPPORT || RTL8822B_SUPPORT ||\
+	RTL8197F_SUPPORT || RTL8192F_SUPPORT || RTL8198F_SUPPORT ||\
+	RTL8822C_SUPPORT)
+	#define PHYDM_LA_MODE_SUPPORT			1
+#else
+	#define PHYDM_LA_MODE_SUPPORT			0
+#endif
+
+#if (RTL8822B_SUPPORT || RTL8812A_SUPPORT || RTL8197F_SUPPORT ||\
+	RTL8192F_SUPPORT)
+	#define DYN_ANT_WEIGHTING_SUPPORT
+#endif
+
+#if (RTL8822B_SUPPORT || RTL8821C_SUPPORT)
+	#define FAHM_SUPPORT
+#endif
+	#define NHM_SUPPORT
+	#define CLM_SUPPORT
+
+#if (RTL8822B_SUPPORT)
+	/*@#define PHYDM_PHYSTAUS_SMP_MODE*/
+#endif
+
+/*@#define PHYDM_TDMA_DIG_SUPPORT*/
+
+#if (RTL8814B_SUPPORT || RTL8822C_SUPPORT)
+	/*@#define PHYDM_TDMA_DIG_SUPPORT*/
+	#ifdef PHYDM_TDMA_DIG_SUPPORT
+	/*@#define IS_USE_NEW_TDMA*/ /*new tdma dig test*/
+	#endif
+#endif
+
+#if (RTL8197F_SUPPORT || RTL8822B_SUPPORT || RTL8814B_SUPPORT)
+	/*@#define PHYDM_LNA_SAT_CHK_SUPPORT*/
+	#ifdef PHYDM_LNA_SAT_CHK_SUPPORT
+
+		#if (RTL8197F_SUPPORT)
+		/*@#define PHYDM_LNA_SAT_CHK_SUPPORT_TYPE1*/
+		#endif
+
+		#if (RTL8822B_SUPPORT)
+		/*@#define PHYDM_LNA_SAT_CHK_TYPE2*/
+		#endif
+
+		#if (RTL8814B_SUPPORT)
+		/*@#define PHYDM_LNA_SAT_CHK_TYPE1*/
+		#endif
+	#endif
+#endif
+
+#if (RTL8822B_SUPPORT || RTL8192F_SUPPORT)
+	#define PHYDM_POWER_TRAINING_SUPPORT
+#endif
+
+#if (RTL8822C_SUPPORT)
+	/* #define PHYDM_PMAC_TX_SETTING_SUPPORT */
+#endif
+
+#if (RTL8822C_SUPPORT)
+	/* #define PHYDM_MP_SUPPORT */
+#endif
+
+#if (RTL8822B_SUPPORT)
+	#define PHYDM_TXA_CALIBRATION
+#endif
+
+#if (RTL8188E_SUPPORT)
+	#define	PHYDM_PRIMARY_CCA
+#endif
+
+#if (RTL8188F_SUPPORT || RTL8710B_SUPPORT || RTL8821C_SUPPORT ||\
+	RTL8822B_SUPPORT || RTL8192F_SUPPORT)
+	#define	PHYDM_DC_CANCELLATION
+#endif
+
+#if (RTL8822B_SUPPORT || RTL8197F_SUPPORT || RTL8192F_SUPPORT)
+	#define	CONFIG_ADAPTIVE_SOML
+#endif
+
+#if (RTL8188E_SUPPORT || RTL8192E_SUPPORT)
+	#define	CONFIG_RECEIVER_BLOCKING
+#endif
+
+#if (RTL8192F_SUPPORT == 1)
+	/*#define	CONFIG_8912F_SPUR_CALIBRATION*/
+#endif
+
+#if (RTL8822B_SUPPORT == 1)
+	#define	CONFIG_8822B_SPUR_CALIBRATION
+#endif
+
+#ifdef CONFIG_SUPPORT_DYNAMIC_TXPWR
+#define CONFIG_DYNAMIC_TX_TWR
+#endif
+#define PHYDM_SUPPORT_CCKPD
+#define PHYDM_SUPPORT_ADAPTIVITY
+
+/*@Antenna Diversity*/
+#ifdef CONFIG_ANTENNA_DIVERSITY
+	#define CONFIG_PHYDM_ANTENNA_DIVERSITY
+
+	#ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY
+
+		#if (RTL8723B_SUPPORT || RTL8821A_SUPPORT ||\
+		     RTL8188F_SUPPORT || RTL8821C_SUPPORT ||\
+		     RTL8723D_SUPPORT)
+			#define	CONFIG_S0S1_SW_ANTENNA_DIVERSITY
+		#endif
+
+		#if (RTL8821A_SUPPORT)
+			/*@#define CONFIG_HL_SMART_ANTENNA_TYPE1*/
+		#endif
+
+		#if (RTL8822B_SUPPORT)
+			/*@#define CONFIG_HL_SMART_ANTENNA_TYPE2*/
+		#endif
+
+	#endif
+#endif
+
+/*@[SmartAntenna]*/
+/*@#define	CONFIG_SMART_ANTENNA*/
+#ifdef CONFIG_SMART_ANTENNA
+	/*@#define	CONFIG_CUMITEK_SMART_ANTENNA*/
+#endif
+/* @--------------------------------------------------*/
+
+#ifdef CONFIG_DFS_MASTER
+	#define CONFIG_PHYDM_DFS_MASTER
+#endif
+
+#if (RTL8812A_SUPPORT || RTL8821A_SUPPORT || RTL8881A_SUPPORT ||\
+	RTL8192E_SUPPORT || RTL8723B_SUPPORT)
+	/*@#define	CONFIG_RA_FW_DBG_CODE*/
+#endif
+
+#define	CONFIG_PSD_TOOL
+/*@#define	CONFIG_ANT_DETECTION*/
+/*@#define	CONFIG_PATH_DIVERSITY*/
+/*@#define	CONFIG_RA_DYNAMIC_RTY_LIMIT*/
+#define	CONFIG_BB_TXBF_API
+#define	CONFIG_PHYDM_DEBUG_FUNCTION
+
+#ifdef CONFIG_BT_COEXIST
+	#define	ODM_CONFIG_BT_COEXIST
+#endif
+#define	PHYDM_SUPPORT_RSSI_MONITOR
+/*@#define	PHYDM_AUTO_DEGBUG*/
+#define CFG_DIG_DAMPING_CHK
+
+
+#ifdef BEAMFORMING_SUPPORT
+	#if (RTL8812A_SUPPORT || RTL8821A_SUPPORT || RTL8192E_SUPPORT ||\
+	     RTL8814A_SUPPORT || RTL8881A_SUPPORT)
+		#define	PHYDM_BEAMFORMING_VERSION1
+	#endif
+	#if (RTL8192F_SUPPORT || RTL8195B_SUPPORT || RTL8821C_SUPPORT ||\
+	     RTL8822B_SUPPORT || RTL8197F_SUPPORT || RTL8198F_SUPPORT ||\
+	     RTL8822C_SUPPORT || RTL8814B_SUPPORT)
+		#define	DRIVER_BEAMFORMING_VERSION2
+	#endif
+#endif
+
+#if (RTL8822B_SUPPORT)
+	#ifdef CONFIG_MCC_MODE
+	#define	CONFIG_MCC_DM
+	#endif
+#endif
+
+#if (RTL8822B_SUPPORT)
+	#ifdef CONFIG_DYNAMIC_BYPASS_MODE
+	#define	CONFIG_DYNAMIC_BYPASS
+	#endif
+#endif
+
+
+#endif
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/phydm_features.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/phydm_features.h
--- linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/phydm_features.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/phydm_features.h	2020-04-10 16:35:06.824660441 +0300
@@ -0,0 +1,58 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017  Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * The full GNU General Public License is included in this distribution in the
+ * file called LICENSE.
+ *
+ * Contact Information:
+ * wlanfae <wlanfae@realtek.com>
+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
+ * Hsinchu 300, Taiwan.
+ *
+ * Larry Finger <Larry.Finger@lwfinger.net>
+ *
+ *****************************************************************************/
+
+#ifndef __PHYDM_FEATURES_H__
+#define __PHYDM_FEATURES_H__
+
+#define CONFIG_RUN_IN_DRV
+#define ODM_DC_CANCELLATION_SUPPORT		(ODM_RTL8188F | ODM_RTL8710B | ODM_RTL8192F | ODM_RTL8821C)
+#define ODM_RECEIVER_BLOCKING_SUPPORT	(ODM_RTL8188E | ODM_RTL8192E)
+
+/*@20170103 YuChen add for FW API*/
+#define PHYDM_FW_API_ENABLE_8822B		1
+#define PHYDM_FW_API_FUNC_ENABLE_8822B		1
+#define PHYDM_FW_API_ENABLE_8821C		1
+#define PHYDM_FW_API_FUNC_ENABLE_8821C		1
+#define PHYDM_FW_API_ENABLE_8195B		1
+#define PHYDM_FW_API_FUNC_ENABLE_8195B		1
+#define PHYDM_FW_API_ENABLE_8198F		1
+#define PHYDM_FW_API_FUNC_ENABLE_8198F		1
+#define PHYDM_FW_API_ENABLE_8822C 1
+#define PHYDM_FW_API_FUNC_ENABLE_8822C 1
+#define PHYDM_FW_API_ENABLE_8814B 1
+#define PHYDM_FW_API_FUNC_ENABLE_8814B 1
+
+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
+	#include	"phydm_features_win.h"
+#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
+	#include	"phydm_features_ce.h"
+	/*@#include	"phydm_features_ce2_kernel.h"*/
+#elif (DM_ODM_SUPPORT_TYPE == ODM_AP)
+	#include	"phydm_features_ap.h"
+#elif (DM_ODM_SUPPORT_TYPE == ODM_IOT)
+	#include	"phydm_features_iot.h"
+#endif
+
+#endif
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/phydm_features_iot.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/phydm_features_iot.h
--- linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/phydm_features_iot.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/phydm_features_iot.h	2020-04-10 16:35:06.825660488 +0300
@@ -0,0 +1,174 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017  Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * The full GNU General Public License is included in this distribution in the
+ * file called LICENSE.
+ *
+ * Contact Information:
+ * wlanfae <wlanfae@realtek.com>
+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
+ * Hsinchu 300, Taiwan.
+ *
+ * Larry Finger <Larry.Finger@lwfinger.net>
+ *
+ *****************************************************************************/
+
+#ifndef	__PHYDM_FEATURES_IOT_H__
+#define __PHYDM_FEATURES_IOT_H__
+
+#if (RTL8814A_SUPPORT || RTL8821C_SUPPORT || RTL8822B_SUPPORT ||\
+	RTL8197F_SUPPORT || RTL8192F_SUPPORT || RTL8198F_SUPPORT ||\
+	RTL8822C_SUPPORT)
+	#define PHYDM_LA_MODE_SUPPORT			1
+#else
+	#define PHYDM_LA_MODE_SUPPORT			0
+#endif
+
+#if (RTL8822B_SUPPORT || RTL8812A_SUPPORT || RTL8197F_SUPPORT ||\
+	RTL8192F_SUPPORT)
+	#define DYN_ANT_WEIGHTING_SUPPORT
+#endif
+
+#if (RTL8822B_SUPPORT || RTL8821C_SUPPORT)
+	#define FAHM_SUPPORT
+#endif
+	#define NHM_SUPPORT
+	#define CLM_SUPPORT
+
+#if (RTL8822B_SUPPORT)
+	/*#define PHYDM_PHYSTAUS_SMP_MODE*/
+#endif
+
+/*#define PHYDM_TDMA_DIG_SUPPORT*/
+
+#if (RTL8197F_SUPPORT || RTL8822B_SUPPORT)
+	/*#define PHYDM_LNA_SAT_CHK_SUPPORT*/
+	#ifdef PHYDM_LNA_SAT_CHK_SUPPORT
+		#if (RTL8197F_SUPPORT)
+		/*#define PHYDM_LNA_SAT_CHK_SUPPORT_TYPE1*/
+		#endif
+
+		#if (RTL8822B_SUPPORT)
+		/*#define PHYDM_LNA_SAT_CHK_TYPE2*/
+		#endif
+	#endif
+#endif
+
+#if (RTL8822B_SUPPORT)
+	#define PHYDM_POWER_TRAINING_SUPPORT
+#endif
+
+#if (RTL8822C_SUPPORT)
+	/* #define PHYDM_PMAC_TX_SETTING_SUPPORT */
+#endif
+
+#if (RTL8822C_SUPPORT)
+	/* #define PHYDM_MP_SUPPORT */
+#endif
+
+#if (RTL8822B_SUPPORT)
+	#define PHYDM_TXA_CALIBRATION
+#endif
+
+#if (RTL8188E_SUPPORT)
+	#define	PHYDM_PRIMARY_CCA
+#endif
+
+#if (RTL8188F_SUPPORT || RTL8710B_SUPPORT || RTL8821C_SUPPORT ||\
+	RTL8822B_SUPPORT)
+	#define	PHYDM_DC_CANCELLATION
+#endif
+
+#if (RTL8822B_SUPPORT || RTL8197F_SUPPORT || RTL8192F_SUPPORT)
+	#define	CONFIG_ADAPTIVE_SOML
+#endif
+
+#if (RTL8822B_SUPPORT)
+	/*#define	CONFIG_DYNAMIC_RX_PATH*/
+#endif
+
+#if (RTL8822B_SUPPORT == 1)
+	/* #define	CONFIG_8822B_SPUR_CALIBRATION */
+#endif
+
+#if (RTL8188E_SUPPORT || RTL8192E_SUPPORT)
+	#define	CONFIG_RECEIVER_BLOCKING
+#endif
+
+#ifdef CONFIG_SUPPORT_DYNAMIC_TXPWR
+#define CONFIG_DYNAMIC_TX_TWR
+#endif
+#define PHYDM_SUPPORT_CCKPD
+#define PHYDM_SUPPORT_ADAPTIVITY
+
+/*Antenna Diversity*/
+#ifdef CONFIG_ANTENNA_DIVERSITY
+	#define CONFIG_PHYDM_ANTENNA_DIVERSITY
+
+	#ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY
+
+		#if (RTL8723B_SUPPORT || RTL8821A_SUPPORT ||\
+		     RTL8188F_SUPPORT || RTL8821C_SUPPORT)
+			#define	CONFIG_S0S1_SW_ANTENNA_DIVERSITY
+		#endif
+
+		#if (RTL8821A_SUPPORT)
+			/*#define CONFIG_HL_SMART_ANTENNA_TYPE1*/
+		#endif
+
+		#if (RTL8822B_SUPPORT)
+			/*#define CONFIG_HL_SMART_ANTENNA_TYPE2*/
+		#endif
+	#endif
+#endif
+
+/*[SmartAntenna]*/
+/*#define	CONFIG_SMART_ANTENNA*/
+#ifdef CONFIG_SMART_ANTENNA
+	/*#define	CONFIG_CUMITEK_SMART_ANTENNA*/
+#endif
+/* --------------------------------------------------*/
+
+#ifdef CONFIG_DFS_MASTER
+	#define CONFIG_PHYDM_DFS_MASTER
+#endif
+
+#if (RTL8812A_SUPPORT || RTL8821A_SUPPORT || RTL8881A_SUPPORT ||\
+	RTL8192E_SUPPORT || RTL8723B_SUPPORT)
+	/*#define	CONFIG_RA_FW_DBG_CODE*/
+#endif
+
+#define	CONFIG_PSD_TOOL
+/*#define	CONFIG_RA_DBG_CMD*/
+/*#define	CONFIG_ANT_DETECTION*/
+/*#define	CONFIG_PATH_DIVERSITY*/
+/*#define	CONFIG_RA_DYNAMIC_RTY_LIMIT*/
+#define	CONFIG_BB_TXBF_API
+#define	CONFIG_PHYDM_DEBUG_FUNCTION
+
+#ifdef CONFIG_BT_COEXIST
+	#define	ODM_CONFIG_BT_COEXIST
+#endif
+#define	PHYDM_SUPPORT_RSSI_MONITOR
+/*#define	PHYDM_AUTO_DEGBUG*/
+#define CFG_DIG_DAMPING_CHK
+
+#ifdef BEAMFORMING_SUPPORT
+	#if (RTL8192F_SUPPORT || RTL8195B_SUPPORT || RTL8821C_SUPPORT ||\
+	     RTL8822B_SUPPORT || RTL8197F_SUPPORT || RTL8198F_SUPPORT ||\
+	     RTL8822C_SUPPORT || RTL8814B_SUPPORT)
+		#define	DRIVER_BEAMFORMING_VERSION2
+	#endif
+#endif
+
+#endif
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/phydm_features_win.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/phydm_features_win.h
--- linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/phydm_features_win.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/phydm_features_win.h	2020-04-10 16:35:06.825660488 +0300
@@ -0,0 +1,185 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+
+#ifndef	__PHYDM_FEATURES_WIN_H__
+#define __PHYDM_FEATURES_WIN_H__
+
+#if (RTL8814A_SUPPORT || RTL8821C_SUPPORT || RTL8822B_SUPPORT ||\
+	RTL8197F_SUPPORT || RTL8192F_SUPPORT || RTL8198F_SUPPORT ||\
+	RTL8822C_SUPPORT)
+	#define PHYDM_LA_MODE_SUPPORT			1
+#else
+	#define PHYDM_LA_MODE_SUPPORT			0
+#endif
+
+#if (RTL8822B_SUPPORT || RTL8812A_SUPPORT || RTL8197F_SUPPORT ||\
+	RTL8192F_SUPPORT)
+	#define DYN_ANT_WEIGHTING_SUPPORT
+#endif
+
+#if (RTL8822B_SUPPORT || RTL8821C_SUPPORT)
+	#define FAHM_SUPPORT
+#endif
+	#define NHM_SUPPORT
+	#define CLM_SUPPORT
+
+#if (RTL8822B_SUPPORT)
+	/*#define PHYDM_PHYSTAUS_SMP_MODE*/
+#endif
+
+/*#define PHYDM_TDMA_DIG_SUPPORT*/
+
+#if (RTL8814B_SUPPORT || RTL8822C_SUPPORT)
+	/*#define PHYDM_TDMA_DIG_SUPPORT*/
+	#ifdef PHYDM_TDMA_DIG_SUPPORT
+	/*#define IS_USE_NEW_TDMA*/ /*new tdma dig test*/
+	#endif
+#endif
+
+#if (RTL8197F_SUPPORT || RTL8822B_SUPPORT || RTL8814B_SUPPORT)
+	/*#define PHYDM_LNA_SAT_CHK_SUPPORT*/
+	#ifdef PHYDM_LNA_SAT_CHK_SUPPORT
+
+		#if (RTL8197F_SUPPORT)
+		/*#define PHYDM_LNA_SAT_CHK_SUPPORT_TYPE1*/
+		#endif
+
+		#if (RTL8822B_SUPPORT)
+		/*#define PHYDM_LNA_SAT_CHK_TYPE2*/
+		#endif
+
+		#if (RTL8814B_SUPPORT)
+		/*#define PHYDM_LNA_SAT_CHK_TYPE1*/
+		#endif
+	#endif
+#endif
+
+#if (RTL8822B_SUPPORT || RTL8710B_SUPPORT || RTL8723D_SUPPORT ||\
+	RTL8192F_SUPPORT)
+	#define	PHYDM_POWER_TRAINING_SUPPORT
+#endif
+
+#if (RTL8822C_SUPPORT)
+	#define	PHYDM_PMAC_TX_SETTING_SUPPORT
+#endif
+
+#if (RTL8822C_SUPPORT)
+	#define	PHYDM_MP_SUPPORT
+#endif
+
+#if (RTL8822B_SUPPORT)
+	#define	PHYDM_TXA_CALIBRATION
+#endif
+
+#if (RTL8188E_SUPPORT || RTL8192E_SUPPORT)
+	#define	PHYDM_PRIMARY_CCA
+#endif
+
+#if (RTL8188F_SUPPORT || RTL8710B_SUPPORT || RTL8821C_SUPPORT ||\
+	RTL8822B_SUPPORT || RTL8192F_SUPPORT)
+	#define	PHYDM_DC_CANCELLATION
+#endif
+
+#if (RTL8822B_SUPPORT || RTL8197F_SUPPORT || RTL8192F_SUPPORT)
+	#define	CONFIG_ADAPTIVE_SOML
+#endif
+
+#if (RTL8192F_SUPPORT == 1)
+	#define	CONFIG_8912F_SPUR_CALIBRATION
+#endif
+
+#if (RTL8822B_SUPPORT == 1)
+	/* #define	CONFIG_8822B_SPUR_CALIBRATION */
+#endif
+
+/*Antenna Diversity*/
+#define	CONFIG_PHYDM_ANTENNA_DIVERSITY
+#ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY
+
+	#if (RTL8723B_SUPPORT || RTL8821A_SUPPORT || RTL8188F_SUPPORT ||\
+	     RTL8821C_SUPPORT)
+		#define	CONFIG_S0S1_SW_ANTENNA_DIVERSITY
+	#endif
+
+	#if (RTL8822B_SUPPORT)
+		/*#define	ODM_EVM_ENHANCE_ANTDIV*/
+		/*#define	CONFIG_2T3R_ANTENNA*/
+		/*#define	CONFIG_2T4R_ANTENNA*/
+	#endif
+
+	/* --[SmtAnt]-----------------------------------------*/
+	#if (RTL8821A_SUPPORT)
+		/*#define	CONFIG_HL_SMART_ANTENNA_TYPE1*/
+		#define	CONFIG_FAT_PATCH
+	#endif
+	
+	#if (RTL8822B_SUPPORT)
+		/*#define CONFIG_HL_SMART_ANTENNA_TYPE2*/
+	#endif
+	
+	#if (defined(CONFIG_HL_SMART_ANTENNA_TYPE1) || defined(CONFIG_HL_SMART_ANTENNA_TYPE2))
+		#define	CONFIG_HL_SMART_ANTENNA
+	#endif
+
+	/* --------------------------------------------------*/
+
+#endif
+
+/*[SmartAntenna]*/
+#define	CONFIG_SMART_ANTENNA
+#ifdef CONFIG_SMART_ANTENNA
+		/*#define	CONFIG_CUMITEK_SMART_ANTENNA*/
+#endif
+	/* --------------------------------------------------*/
+
+#if (RTL8188E_SUPPORT || RTL8192E_SUPPORT)
+	#define	CONFIG_RECEIVER_BLOCKING
+#endif
+
+#if (RTL8812A_SUPPORT || RTL8821A_SUPPORT || RTL8881A_SUPPORT ||\
+	RTL8192E_SUPPORT || RTL8723B_SUPPORT)
+	#define	CONFIG_RA_FW_DBG_CODE
+#endif
+
+/* #ifdef CONFIG_SUPPORT_DYNAMIC_TXPWR */
+#define CONFIG_DYNAMIC_TX_TWR
+/* #endif */
+#define	CONFIG_PSD_TOOL
+#define PHYDM_SUPPORT_ADAPTIVITY
+#define	PHYDM_SUPPORT_CCKPD
+/*#define	CONFIG_PATH_DIVERSITY*/
+/*#define	CONFIG_RA_DYNAMIC_RTY_LIMIT*/
+#define CONFIG_ANT_DETECTION
+#define	CONFIG_BB_TXBF_API
+#define	ODM_CONFIG_BT_COEXIST
+#define	CONFIG_PHYDM_DFS_MASTER
+#define	PHYDM_SUPPORT_RSSI_MONITOR
+#define	PHYDM_AUTO_DEGBUG
+#define CONFIG_PHYDM_DEBUG_FUNCTION
+#define CFG_DIG_DAMPING_CHK
+
+#ifdef BEAMFORMING_SUPPORT
+	#if (RTL8812A_SUPPORT || RTL8821A_SUPPORT ||  RTL8192E_SUPPORT ||\
+	     RTL8814A_SUPPORT || RTL8881A_SUPPORT)
+		#define	PHYDM_BEAMFORMING_VERSION1
+	#endif
+	#if (RTL8192F_SUPPORT || RTL8195B_SUPPORT || RTL8821C_SUPPORT ||\
+	     RTL8822B_SUPPORT || RTL8197F_SUPPORT || RTL8198F_SUPPORT ||\
+	     RTL8822C_SUPPORT || RTL8814B_SUPPORT)
+		#define	DRIVER_BEAMFORMING_VERSION2
+	#endif
+#endif
+
+#endif
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/phydm.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/phydm.h
--- linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/phydm.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/phydm.h	2020-04-10 16:35:06.821660301 +0300
@@ -0,0 +1,1340 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017  Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * The full GNU General Public License is included in this distribution in the
+ * file called LICENSE.
+ *
+ * Contact Information:
+ * wlanfae <wlanfae@realtek.com>
+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
+ * Hsinchu 300, Taiwan.
+ *
+ * Larry Finger <Larry.Finger@lwfinger.net>
+ *
+ *****************************************************************************/
+
+#ifndef __HALDMOUTSRC_H__
+#define __HALDMOUTSRC_H__
+
+/*@============================================================*/
+/*@include files*/
+/*@============================================================*/
+/*PHYDM header*/
+#include "phydm_pre_define.h"
+#include "phydm_features.h"
+#include "phydm_dig.h"
+#include "phydm_pathdiv.h"
+#ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY
+#include "phydm_antdiv.h"
+#endif
+
+#include "phydm_soml.h"
+
+#ifdef CONFIG_SMART_ANTENNA
+#include "phydm_smt_ant.h"
+#endif
+#ifdef CONFIG_ANT_DETECTION
+#include "phydm_antdect.h"
+#endif
+#include "phydm_rainfo.h"
+#ifdef CONFIG_DYNAMIC_TX_TWR
+#include "phydm_dynamictxpower.h"
+#endif
+#include "phydm_cfotracking.h"
+#include "phydm_adaptivity.h"
+#include "phydm_dfs.h"
+#include "phydm_ccx.h"
+#include "txbf/phydm_hal_txbf_api.h"
+#if (PHYDM_LA_MODE_SUPPORT == 1)
+#include "phydm_adc_sampling.h"
+#endif
+#ifdef CONFIG_PSD_TOOL
+#include "phydm_psd.h"
+#endif
+#ifdef PHYDM_PRIMARY_CCA
+#include "phydm_primary_cca.h"
+#endif
+#include "phydm_cck_pd.h"
+#include "phydm_rssi_monitor.h"
+#ifdef PHYDM_AUTO_DEGBUG
+#include "phydm_auto_dbg.h"
+#endif
+#include "phydm_math_lib.h"
+#include "phydm_noisemonitor.h"
+#include "phydm_api.h"
+#ifdef PHYDM_POWER_TRAINING_SUPPORT
+#include "phydm_pow_train.h"
+#endif
+#ifdef PHYDM_LNA_SAT_CHK_SUPPORT
+#include "phydm_lna_sat.h"
+#endif
+#ifdef PHYDM_PMAC_TX_SETTING_SUPPORT
+#include "phydm_pmac_tx_setting.h"
+#endif
+#ifdef PHYDM_MP_SUPPORT
+#include "phydm_mp.h"
+#endif
+#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
+	#include "phydm_beamforming.h"
+#endif
+
+#include "phydm_regtable.h"
+
+/*@HALRF header*/
+#include "halrf/halrf_iqk.h"
+#include "halrf/halrf_dpk.h"
+#include "halrf/halrf.h"
+#include "halrf/halrf_powertracking.h"
+#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
+	#include "halrf/halphyrf_ap.h"
+#elif(DM_ODM_SUPPORT_TYPE & (ODM_CE))
+	#include "halrf/halphyrf_ce.h"
+#elif (DM_ODM_SUPPORT_TYPE & (ODM_WIN))
+	#include "halrf/halphyrf_win.h"
+#elif(DM_ODM_SUPPORT_TYPE & (ODM_IOT))
+	#include "halrf/halphyrf_iot.h"
+#endif
+
+extern const u16	phy_rate_table[28];
+
+/*@============================================================*/
+/*@Definition */
+/*@============================================================*/
+
+/* Traffic load decision */
+#define TRAFFIC_NO_TP			0
+#define	TRAFFIC_ULTRA_LOW		1
+#define	TRAFFIC_LOW			2
+#define	TRAFFIC_MID			3
+#define	TRAFFIC_HIGH			4
+
+#define	NONE				0
+
+#if defined(DM_ODM_CE_MAC80211)
+#define MAX_2(x, y)					\
+	__max2(typeof(x), typeof(y),			\
+	      x, y)
+#define __max2(t1, t2, x, y) ({		\
+	t1 m80211_max1 = (x);					\
+	t2 m80211_max2 = (y);					\
+	m80211_max1 > m80211_max2 ? m80211_max1 : m80211_max2; })
+
+#define MIN_2(x, y)					\
+	__min2(typeof(x), typeof(y),			\
+	      x, y)
+#define __min2(t1, t2, x, y) ({		\
+	t1 m80211_min1 = (x);					\
+	t2 m80211_min2 = (y);					\
+	m80211_min1 < m80211_min2 ? m80211_min1 : m80211_min2; })
+
+#define DIFF_2(x, y)					\
+	__diff2(typeof(x), typeof(y),			\
+	      x, y)
+#define __diff2(t1, t2, x, y) ({		\
+	t1 __d1 = (x);					\
+	t2 __d2 = (y);					\
+	(__d1 >= __d2) ? (__d1 - __d2) : (__d2 - __d1); })
+#else
+#define MAX_2(_x_, _y_)	(((_x_) > (_y_)) ? (_x_) : (_y_))
+#define MIN_2(_x_, _y_)	(((_x_) < (_y_)) ? (_x_) : (_y_))
+#define DIFF_2(_x_, _y_)	((_x_ >= _y_) ? (_x_ - _y_) : (_y_ - _x_))
+#endif
+
+#define IS_GREATER(_x_, _y_)	(((_x_) >= (_y_)) ? true : false)
+#define IS_LESS(_x_, _y_)	(((_x_) < (_y_)) ? true : false)
+
+#if defined(DM_ODM_CE_MAC80211)
+#define BYTE_DUPLICATE_2_DWORD(B0) ({	\
+	u32 __b_dup = (B0);\
+	(((__b_dup) << 24) | ((__b_dup) << 16) | ((__b_dup) << 8) | (__b_dup));\
+	})
+#else
+#define BYTE_DUPLICATE_2_DWORD(B0)	\
+	(((B0) << 24) | ((B0) << 16) | ((B0) << 8) | (B0))
+#endif
+#define BYTE_2_DWORD(B3, B2, B1, B0)	\
+	(((B3) << 24) | ((B2) << 16) | ((B1) << 8) | (B0))
+#define BIT_2_BYTE(B3, B2, B1, B0)	\
+	(((B3) << 3) | ((B2) << 2) | ((B1) << 1) | (B0))
+
+/*@For cmn sta info*/
+#if defined(DM_ODM_CE_MAC80211)
+#define is_sta_active(sta) ({	\
+	struct cmn_sta_info *__sta = (sta);	\
+	((__sta) && (__sta->dm_ctrl & STA_DM_CTRL_ACTIVE));	\
+	})
+
+#define IS_FUNC_EN(name) ({	\
+	u8 *__is_func_name = (name);	\
+	(__is_func_name) && (*__is_func_name);	\
+	})
+#else
+#define is_sta_active(sta)	((sta) && (sta->dm_ctrl & STA_DM_CTRL_ACTIVE))
+
+#define IS_FUNC_EN(name)	((name) && (*name))
+#endif
+
+#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
+	#define PHYDM_WATCH_DOG_PERIOD	1 /*second*/
+#else
+	#define PHYDM_WATCH_DOG_PERIOD	2 /*second*/
+#endif
+
+#define PHY_HIST_SIZE		12
+
+/*@============================================================*/
+/*structure and define*/
+/*@============================================================*/
+
+#define		dm_type_by_fw		0
+#define		dm_type_by_driver	1
+
+#ifdef BB_RAM_SUPPORT
+
+struct phydm_bb_ram_per_sta {
+	/* @Reg0x1E84 for RAM I/O*/
+	boolean			hw_igi_en;
+	boolean			tx_pwr_offset0_en;
+	boolean			tx_pwr_offset1_en;
+	/* @ macid from 0 to 63, above 63 => mapping to 63*/
+	u8			macid_addr;
+	/* @hw_igi value for paths after packet Tx in a period of time*/
+	u8			hw_igi;
+	/* @tx_pwr_offset0 offset for Tx power index*/
+	s8			tx_pwr_offset0;
+	s8			tx_pwr_offset1;
+
+};
+
+struct phydm_bb_ram_ctrl {
+	/*@ For 98F/14B/22C/12F, each TxAGC step will be 0.25dB*/
+	struct phydm_bb_ram_per_sta pram_sta_ctrl[ODM_ASSOCIATE_ENTRY_NUM];
+	/*------------ For table2 do not set power offset by macid --------*/
+	/* For type == 2'b10, 0x1e70[22:16] = tx_pwr_offset_reg0, 0x1e70[23] = enable */
+	boolean			tx_pwr_offset_reg0_en;
+	u8			tx_pwr_offset_reg0;
+	/* For type == 2'b11, 0x1e70[30:24] = tx_pwr_offset_reg1, 0x1e70[31] = enable */
+	boolean			tx_pwr_offset_reg1_en;
+	u8			tx_pwr_offset_reg1;
+};
+
+#endif
+
+struct phydm_phystatus_statistic {
+	/*@[CCK]*/
+	u32			rssi_cck_sum;
+	u32			rssi_cck_cnt;
+	/*@[OFDM]*/
+	u32			rssi_ofdm_sum;
+	u32			rssi_ofdm_cnt;
+	u32			evm_ofdm_sum;
+	u32			snr_ofdm_sum;
+	u16			evm_ofdm_hist[PHY_HIST_SIZE];
+	u16			snr_ofdm_hist[PHY_HIST_SIZE];
+	/*@[1SS]*/
+	u32			rssi_1ss_cnt;
+	u32			rssi_1ss_sum;
+	u32			evm_1ss_sum;
+	u32			snr_1ss_sum;
+	u16			evm_1ss_hist[PHY_HIST_SIZE];
+	u16			snr_1ss_hist[PHY_HIST_SIZE];
+	/*@[2SS]*/
+	#if (defined(PHYDM_COMPILE_ABOVE_2SS))
+	u32			rssi_2ss_cnt;
+	u32			rssi_2ss_sum[2];
+	u32			evm_2ss_sum[2];
+	u32			snr_2ss_sum[2];
+	u16			evm_2ss_hist[2][PHY_HIST_SIZE];
+	u16			snr_2ss_hist[2][PHY_HIST_SIZE];
+	#endif
+	/*@[3SS]*/
+	#if (defined(PHYDM_COMPILE_ABOVE_3SS))
+	u32			rssi_3ss_cnt;
+	u32			rssi_3ss_sum[3];
+	u32			evm_3ss_sum[3];
+	u32			snr_3ss_sum[3];
+	u16			evm_3ss_hist[3][PHY_HIST_SIZE];
+	u16			snr_3ss_hist[3][PHY_HIST_SIZE];
+	#endif
+	/*@[4SS]*/
+	#if (defined(PHYDM_COMPILE_ABOVE_4SS))
+	u32			rssi_4ss_cnt;
+	u32			rssi_4ss_sum[4];
+	u32			evm_4ss_sum[4];
+	u32			snr_4ss_sum[4];
+	u16			evm_4ss_hist[4][PHY_HIST_SIZE];
+	u16			snr_4ss_hist[4][PHY_HIST_SIZE];
+	#endif
+};
+
+struct phydm_phystatus_avg {
+	/*@[CCK]*/
+	u8			rssi_cck_avg;
+	/*@[OFDM]*/
+	u8			rssi_ofdm_avg;
+	u8			evm_ofdm_avg;
+	u8			snr_ofdm_avg;
+	/*@[1SS]*/
+	u8			rssi_1ss_avg;
+	u8			evm_1ss_avg;
+	u8			snr_1ss_avg;
+	/*@[2SS]*/
+	#if (defined(PHYDM_COMPILE_ABOVE_2SS))
+	u8			rssi_2ss_avg[2];
+	u8			evm_2ss_avg[2];
+	u8			snr_2ss_avg[2];
+	#endif
+	/*@[3SS]*/
+	#if (defined(PHYDM_COMPILE_ABOVE_3SS))
+	u8			rssi_3ss_avg[3];
+	u8			evm_3ss_avg[3];
+	u8			snr_3ss_avg[3];
+	#endif
+	/*@[4SS]*/
+	#if (defined(PHYDM_COMPILE_ABOVE_4SS))
+	u8			rssi_4ss_avg[4];
+	u8			evm_4ss_avg[4];
+	u8			snr_4ss_avg[4];
+	#endif
+};
+
+struct odm_phy_dbg_info {
+	/*@ODM Write,debug info*/
+	u32			num_qry_phy_status_cck;
+	u32			num_qry_phy_status_ofdm;
+#if (ODM_PHY_STATUS_NEW_TYPE_SUPPORT == 1) || (defined(PHYSTS_3RD_TYPE_SUPPORT))
+	u32			num_qry_mu_pkt;
+	u32			num_qry_bf_pkt;
+	u16			num_mu_vht_pkt[VHT_RATE_NUM];
+	boolean			is_ldpc_pkt;
+	boolean			is_stbc_pkt;
+	u8			num_of_ppdu[4];
+	u8			gid_num[4];
+#endif
+	u32			condi_num; /*@condition number U(18,4)*/
+	u8			condi_num_cdf[CN_CNT_MAX];
+	u8			num_qry_beacon_pkt;
+	u8			beacon_cnt_in_period; /*@beacon cnt within watchdog period*/
+	u8			beacon_phy_rate;
+	u8			show_phy_sts_all_pkt;	/*@Show phy status witch not match BSSID*/
+	u16			show_phy_sts_max_cnt;	/*@show number of phy-status row data per PHYDM watchdog*/
+	u16			show_phy_sts_cnt;
+	u16			num_qry_legacy_pkt[LEGACY_RATE_NUM];
+	u16			num_qry_ht_pkt[HT_RATE_NUM];
+	u16			num_qry_pkt_sc_20m[LOW_BW_RATE_NUM]; /*@20M SC*/
+	boolean			ht_pkt_not_zero;
+	boolean			low_bw_20_occur;
+	#if	ODM_IC_11AC_SERIES_SUPPORT
+	u16			num_qry_vht_pkt[VHT_RATE_NUM];
+	u16			num_qry_pkt_sc_40m[LOW_BW_RATE_NUM]; /*@40M SC*/
+	boolean			vht_pkt_not_zero;
+	boolean			low_bw_40_occur;
+	#endif
+	u16			snr_hist_th[PHY_HIST_SIZE - 1];
+	u16			evm_hist_th[PHY_HIST_SIZE - 1];
+	struct phydm_phystatus_statistic	physts_statistic_info;
+	struct phydm_phystatus_avg	phystatus_statistic_avg;
+};
+
+enum odm_cmninfo {
+	/*@Fixed value*/
+	/*@-----------HOOK BEFORE REG INIT-----------*/
+	ODM_CMNINFO_PLATFORM = 0,
+	ODM_CMNINFO_ABILITY,
+	ODM_CMNINFO_INTERFACE,
+	ODM_CMNINFO_MP_TEST_CHIP,
+	ODM_CMNINFO_IC_TYPE,
+	ODM_CMNINFO_CUT_VER,
+	ODM_CMNINFO_FAB_VER,
+	ODM_CMNINFO_FW_VER,
+	ODM_CMNINFO_FW_SUB_VER,
+	ODM_CMNINFO_RF_TYPE,
+	ODM_CMNINFO_RFE_TYPE,
+	ODM_CMNINFO_DPK_EN,
+	ODM_CMNINFO_BOARD_TYPE,
+	ODM_CMNINFO_PACKAGE_TYPE,
+	ODM_CMNINFO_EXT_LNA,
+	ODM_CMNINFO_5G_EXT_LNA,
+	ODM_CMNINFO_EXT_PA,
+	ODM_CMNINFO_5G_EXT_PA,
+	ODM_CMNINFO_GPA,
+	ODM_CMNINFO_APA,
+	ODM_CMNINFO_GLNA,
+	ODM_CMNINFO_ALNA,
+	ODM_CMNINFO_EXT_TRSW,
+	ODM_CMNINFO_EXT_LNA_GAIN,
+	ODM_CMNINFO_PATCH_ID,
+	ODM_CMNINFO_BINHCT_TEST,
+	ODM_CMNINFO_BWIFI_TEST,
+	ODM_CMNINFO_SMART_CONCURRENT,
+	ODM_CMNINFO_CONFIG_BB_RF,
+	ODM_CMNINFO_IQKPAOFF,
+	ODM_CMNINFO_HUBUSBMODE,
+	ODM_CMNINFO_FWDWRSVDPAGEINPROGRESS,
+	ODM_CMNINFO_TX_TP,
+	ODM_CMNINFO_RX_TP,
+	ODM_CMNINFO_SOUNDING_SEQ,
+	ODM_CMNINFO_REGRFKFREEENABLE,
+	ODM_CMNINFO_RFKFREEENABLE,
+	ODM_CMNINFO_NORMAL_RX_PATH_CHANGE,
+	ODM_CMNINFO_EFUSE0X3D8,
+	ODM_CMNINFO_EFUSE0X3D7,
+	ODM_CMNINFO_SOFT_AP_SPECIAL_SETTING,
+	ODM_CMNINFO_X_CAP_SETTING,
+	ODM_CMNINFO_ADVANCE_OTA,
+	ODM_CMNINFO_HP_HWID,
+	/*@-----------HOOK BEFORE REG INIT-----------*/
+
+	/*@Dynamic value:*/
+
+	/*@--------- POINTER REFERENCE-----------*/
+	ODM_CMNINFO_TX_UNI,
+	ODM_CMNINFO_RX_UNI,
+	ODM_CMNINFO_BAND,
+	ODM_CMNINFO_SEC_CHNL_OFFSET,
+	ODM_CMNINFO_SEC_MODE,
+	ODM_CMNINFO_BW,
+	ODM_CMNINFO_CHNL,
+	ODM_CMNINFO_FORCED_RATE,
+	ODM_CMNINFO_ANT_DIV,
+	ODM_CMNINFO_ADAPTIVE_SOML,
+	ODM_CMNINFO_ADAPTIVITY,
+	ODM_CMNINFO_SCAN,
+	ODM_CMNINFO_POWER_SAVING,
+	ODM_CMNINFO_ONE_PATH_CCA,
+	ODM_CMNINFO_DRV_STOP,
+	ODM_CMNINFO_PNP_IN,
+	ODM_CMNINFO_INIT_ON,
+	ODM_CMNINFO_ANT_TEST,
+	ODM_CMNINFO_NET_CLOSED,
+	ODM_CMNINFO_P2P_LINK,
+	ODM_CMNINFO_FCS_MODE,
+	ODM_CMNINFO_IS1ANTENNA,
+	ODM_CMNINFO_RFDEFAULTPATH,
+	ODM_CMNINFO_DFS_MASTER_ENABLE,
+	ODM_CMNINFO_FORCE_TX_ANT_BY_TXDESC,
+	ODM_CMNINFO_SET_S0S1_DEFAULT_ANTENNA,
+	ODM_CMNINFO_SOFT_AP_MODE,
+	ODM_CMNINFO_MP_MODE,
+	ODM_CMNINFO_INTERRUPT_MASK,
+	ODM_CMNINFO_BB_OPERATION_MODE,
+	ODM_CMNINFO_BF_ANTDIV_DECISION,
+	/*@--------- POINTER REFERENCE-----------*/
+
+	/*@------------CALL BY VALUE-------------*/
+	ODM_CMNINFO_WIFI_DIRECT,
+	ODM_CMNINFO_WIFI_DISPLAY,
+	ODM_CMNINFO_LINK_IN_PROGRESS,
+	ODM_CMNINFO_LINK,
+	ODM_CMNINFO_CMW500LINK,
+	ODM_CMNINFO_STATION_STATE,
+	ODM_CMNINFO_RSSI_MIN,
+	ODM_CMNINFO_RSSI_MIN_BY_PATH,
+	ODM_CMNINFO_DBG_COMP,
+	ODM_CMNINFO_RA_THRESHOLD_HIGH,	/*to be removed*/
+	ODM_CMNINFO_RA_THRESHOLD_LOW,	/*to be removed*/
+	ODM_CMNINFO_RF_ANTENNA_TYPE,
+	ODM_CMNINFO_WITH_EXT_ANTENNA_SWITCH,
+	ODM_CMNINFO_BE_FIX_TX_ANT,
+	ODM_CMNINFO_BT_ENABLED,
+	ODM_CMNINFO_BT_HS_CONNECT_PROCESS,
+	ODM_CMNINFO_BT_HS_RSSI,
+	ODM_CMNINFO_BT_OPERATION,
+	ODM_CMNINFO_BT_LIMITED_DIG,
+	ODM_CMNINFO_AP_TOTAL_NUM,
+	ODM_CMNINFO_POWER_TRAINING,
+	ODM_CMNINFO_DFS_REGION_DOMAIN,
+	ODM_CMNINFO_BT_CONTINUOUS_TURN,
+	/*@------------CALL BY VALUE-------------*/
+
+	/*@Dynamic ptr array hook itms.*/
+	ODM_CMNINFO_STA_STATUS,
+	ODM_CMNINFO_MAX,
+
+};
+
+enum phydm_rfe_bb_source_sel {
+	PAPE_2G			= 0,
+	PAPE_5G			= 1,
+	LNA0N_2G		= 2,
+	LNAON_5G		= 3,
+	TRSW			= 4,
+	TRSW_B			= 5,
+	GNT_BT			= 6,
+	ZERO			= 7,
+	ANTSEL_0		= 8,
+	ANTSEL_1		= 9,
+	ANTSEL_2		= 0xa,
+	ANTSEL_3		= 0xb,
+	ANTSEL_4		= 0xc,
+	ANTSEL_5		= 0xd,
+	ANTSEL_6		= 0xe,
+	ANTSEL_7		= 0xf
+};
+
+enum phydm_info_query {
+	PHYDM_INFO_FA_OFDM,
+	PHYDM_INFO_FA_CCK,
+	PHYDM_INFO_FA_TOTAL,
+	PHYDM_INFO_CCA_OFDM,
+	PHYDM_INFO_CCA_CCK,
+	PHYDM_INFO_CCA_ALL,
+	PHYDM_INFO_CRC32_OK_VHT,
+	PHYDM_INFO_CRC32_OK_HT,
+	PHYDM_INFO_CRC32_OK_LEGACY,
+	PHYDM_INFO_CRC32_OK_CCK,
+	PHYDM_INFO_CRC32_ERROR_VHT,
+	PHYDM_INFO_CRC32_ERROR_HT,
+	PHYDM_INFO_CRC32_ERROR_LEGACY,
+	PHYDM_INFO_CRC32_ERROR_CCK,
+	PHYDM_INFO_EDCCA_FLAG,
+	PHYDM_INFO_OFDM_ENABLE,
+	PHYDM_INFO_CCK_ENABLE,
+	PHYDM_INFO_CRC32_OK_HT_AGG,
+	PHYDM_INFO_CRC32_ERROR_HT_AGG,
+	PHYDM_INFO_DBG_PORT_0,
+	PHYDM_INFO_CURR_IGI,
+	PHYDM_INFO_RSSI_MIN,
+	PHYDM_INFO_RSSI_MAX,
+	PHYDM_INFO_CLM_RATIO,
+	PHYDM_INFO_NHM_RATIO,
+};
+
+enum phydm_api {
+	PHYDM_API_NBI		= 1,
+	PHYDM_API_CSI_MASK	= 2,
+};
+
+enum phydm_func_idx { /*@F_XXX = PHYDM XXX function*/
+
+	F00_DIG			= 0,
+	F01_RA_MASK		= 1,
+	F02_DYN_TXPWR		= 2,
+	F03_FA_CNT		= 3,
+	F04_RSSI_MNTR		= 4,
+	F05_CCK_PD		= 5,
+	F06_ANT_DIV		= 6,
+	F07_SMT_ANT		= 7,
+	F08_PWR_TRAIN		= 8,
+	F09_RA			= 9,
+	F10_PATH_DIV		= 10,
+	F11_DFS			= 11,
+	F12_DYN_ARFR		= 12,
+	F13_ADPTVTY		= 13,
+	F14_CFO_TRK		= 14,
+	F15_ENV_MNTR		= 15,
+	F16_PRI_CCA		= 16,
+	F17_ADPTV_SOML		= 17,
+	F18_LNA_SAT_CHK		= 18,
+};
+
+/*@=[PHYDM supportability]==========================================*/
+enum odm_ability {
+	ODM_BB_DIG		= BIT(F00_DIG),
+	ODM_BB_RA_MASK		= BIT(F01_RA_MASK),
+	ODM_BB_DYNAMIC_TXPWR	= BIT(F02_DYN_TXPWR),
+	ODM_BB_FA_CNT		= BIT(F03_FA_CNT),
+	ODM_BB_RSSI_MONITOR	= BIT(F04_RSSI_MNTR),
+	ODM_BB_CCK_PD		= BIT(F05_CCK_PD),
+	ODM_BB_ANT_DIV		= BIT(F06_ANT_DIV),
+	ODM_BB_SMT_ANT		= BIT(F07_SMT_ANT),
+	ODM_BB_PWR_TRAIN	= BIT(F08_PWR_TRAIN),
+	ODM_BB_RATE_ADAPTIVE	= BIT(F09_RA),
+	ODM_BB_PATH_DIV		= BIT(F10_PATH_DIV),
+	ODM_BB_DFS		= BIT(F11_DFS),
+	ODM_BB_DYNAMIC_ARFR	= BIT(F12_DYN_ARFR),
+	ODM_BB_ADAPTIVITY	= BIT(F13_ADPTVTY),
+	ODM_BB_CFO_TRACKING	= BIT(F14_CFO_TRK),
+	ODM_BB_ENV_MONITOR	= BIT(F15_ENV_MNTR),
+	ODM_BB_PRIMARY_CCA	= BIT(F16_PRI_CCA),
+	ODM_BB_ADAPTIVE_SOML	= BIT(F17_ADPTV_SOML),
+	ODM_BB_LNA_SAT_CHK	= BIT(F18_LNA_SAT_CHK),
+};
+
+/*@=[PHYDM Debug Component]=====================================*/
+enum phydm_dbg_comp {
+	/*@BB Driver Functions*/
+	DBG_DIG			= BIT(F00_DIG),
+	DBG_RA_MASK		= BIT(F01_RA_MASK),
+	DBG_DYN_TXPWR		= BIT(F02_DYN_TXPWR),
+	DBG_FA_CNT		= BIT(F03_FA_CNT),
+	DBG_RSSI_MNTR		= BIT(F04_RSSI_MNTR),
+	DBG_CCKPD		= BIT(F05_CCK_PD),
+	DBG_ANT_DIV		= BIT(F06_ANT_DIV),
+	DBG_SMT_ANT		= BIT(F07_SMT_ANT),
+	DBG_PWR_TRAIN		= BIT(F08_PWR_TRAIN),
+	DBG_RA			= BIT(F09_RA),
+	DBG_PATH_DIV		= BIT(F10_PATH_DIV),
+	DBG_DFS			= BIT(F11_DFS),
+	DBG_DYN_ARFR		= BIT(F12_DYN_ARFR),
+	DBG_ADPTVTY		= BIT(F13_ADPTVTY),
+	DBG_CFO_TRK		= BIT(F14_CFO_TRK),
+	DBG_ENV_MNTR		= BIT(F15_ENV_MNTR),
+	DBG_PRI_CCA		= BIT(F16_PRI_CCA),
+	DBG_ADPTV_SOML		= BIT(F17_ADPTV_SOML),
+	DBG_LNA_SAT_CHK		= BIT(F18_LNA_SAT_CHK),
+	/*BIT(19)*/
+	/*Neet to re-arrange*/
+	DBG_PHY_STATUS		= BIT(20),
+	DBG_TMP			= BIT(21),
+	DBG_FW_TRACE		= BIT(22),
+	DBG_TXBF		= BIT(23),
+	DBG_COMMON_FLOW		= BIT(24),
+	DBG_COMP_MCC		= BIT(25),
+	/*BIT(26)*/
+	DBG_DM_SUMMARY		= BIT(27),
+	ODM_PHY_CONFIG		= BIT(28),
+	ODM_COMP_INIT		= BIT(29),
+	DBG_CMN			= BIT(30),/*@common*/
+	ODM_COMP_API		= BIT(31)
+};
+
+/*@=========================================================*/
+
+/*@ODM_CMNINFO_ONE_PATH_CCA*/
+enum odm_cca_path {
+	ODM_CCA_2R		= 0,
+	ODM_CCA_1R_A		= 1,
+	ODM_CCA_1R_B		= 2,
+};
+
+enum phy_reg_pg_type {
+	PHY_REG_PG_RELATIVE_VALUE = 0,
+	PHY_REG_PG_EXACT_VALUE	= 1
+};
+
+enum phydm_offload_ability {
+	PHYDM_PHY_PARAM_OFFLOAD = BIT(0),
+	PHYDM_RF_IQK_OFFLOAD	= BIT(1),
+};
+
+struct phydm_pause_lv {
+	s8			lv_dig;
+	s8			lv_cckpd;
+	s8			lv_antdiv;
+	s8			lv_adapt;
+	s8			lv_adsl;
+};
+
+struct phydm_func_poiner {
+	void (*pause_phydm_handler)(void *dm_void, u32 *val_buf, u8 val_len);
+};
+
+struct pkt_process_info {
+	u8			phystatus_smp_mode_en; /*@send phystatus every sampling time*/
+	u8			pre_ppdu_cnt;
+	u8			lna_idx;
+	u8			vga_idx;
+};
+
+#ifdef ODM_CONFIG_BT_COEXIST
+struct	phydm_bt_info {
+	boolean			is_bt_enabled;		/*@BT is enabled*/
+	boolean			is_bt_connect_process;	/*@BT HS is under connection progress.*/
+	u8			bt_hs_rssi;		/*@BT HS mode wifi rssi value.*/
+	boolean			is_bt_hs_operation;	/*@BT HS mode is under progress*/
+	boolean			is_bt_limited_dig;	/*@BT is busy.*/
+};
+#endif
+
+struct	phydm_iot_center {
+	boolean			is_linked_cmw500;
+	u8			win_patch_id;		/*@Customer ID*/
+	u32			phydm_patch_id;
+
+};
+
+#if (RTL8822B_SUPPORT == 1)
+struct drp_rtl8822b_struct {
+	enum bb_path path_judge;
+	u16 path_a_cck_fa;
+	u16 path_b_cck_fa;
+};
+#endif
+
+#ifdef CONFIG_MCC_DM
+#define MCC_DM_REG_NUM	32
+struct _phydm_mcc_dm_ {
+	u8		mcc_status;
+	u8		mcc_pre_status;
+	u8		mcc_reg_id[MCC_DM_REG_NUM];
+	u16		mcc_dm_reg[MCC_DM_REG_NUM];
+	u8		mcc_dm_val[MCC_DM_REG_NUM][2];
+	/*mcc DIG*/
+	u8		mcc_rssi[2];
+	/*u8		mcc_igi[2];*/
+	u8 port[2][NUM_STA];
+
+};
+#endif
+
+
+#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
+	#if (RT_PLATFORM != PLATFORM_LINUX)
+		typedef
+	#endif
+
+struct dm_struct {
+#else/*for AP, CE Team*/
+struct dm_struct {
+#endif
+	/*@Add for different team use temporarily*/
+	void			*adapter;		/*@For CE/NIC team*/
+	struct rtl8192cd_priv	*priv;			/*@For AP team*/
+	boolean			odm_ready;
+	enum phy_reg_pg_type	phy_reg_pg_value_type;
+	u8			phy_reg_pg_version;
+	u64			support_ability;	/*@PHYDM function Supportability*/
+	u64			pause_ability;		/*@PHYDM function pause Supportability*/
+	u64			debug_components;
+	u8			cmn_dbg_msg_period;
+	u8			cmn_dbg_msg_cnt;
+	u32			fw_debug_components;
+	u32			num_qry_phy_status_all;	/*@CCK + OFDM*/
+	u32			last_num_qry_phy_status_all;
+	u32			rx_pwdb_ave;
+	boolean			is_init_hw_info_by_rfe;
+
+	/*@------ ODM HANDLE, DRIVER NEEDS NOT TO HOOK------*/
+	boolean			is_cck_high_power;
+	u8			rf_path_rx_enable;
+	/*@------ ODM HANDLE, DRIVER NEEDS NOT TO HOOK------*/
+
+	/* @COMMON INFORMATION */
+
+	/*@Init value*/
+	/*@-----------HOOK BEFORE REG INIT-----------*/
+
+	u8			support_platform;	/*@PHYDM Platform info WIN/AP/CE = 1/2/3 */
+	u8			normal_rx_path;
+	boolean			brxagcswitch;		/* @for rx AGC table switch in Microsoft case */
+	u8			support_interface;	/*@PHYDM PCIE/USB/SDIO = 1/2/3*/
+	u32			support_ic_type;	/*@PHYDM supported IC*/
+	u8			ic_ip_series;		/*N/AC/JGR3*/
+	u8			cut_version;		/*@cut version TestChip/A-cut/B-cut... = 0/1/2/3/...*/
+	u8			fab_version;		/*@Fab version TSMC/UMC = 0/1*/
+	u8			fw_version;
+	u8			fw_sub_version;
+	u8			rf_type;		/*@RF type 4T4R/3T3R/2T2R/1T2R/1T1R/...*/
+	u8			rfe_type;
+	u8			board_type;
+	u8			package_type;
+	u16			type_glna;
+	u16			type_gpa;
+	u16			type_alna;
+	u16			type_apa;
+	u8			ext_lna;		/*@with 2G external LNA  NO/Yes = 0/1*/
+	u8			ext_lna_5g;		/*@with 5G external LNA  NO/Yes = 0/1*/
+	u8			ext_pa;			/*@with 2G external PNA  NO/Yes = 0/1*/
+	u8			ext_pa_5g;		/*@with 5G external PNA  NO/Yes = 0/1*/
+	u8			efuse0x3d7;		/*@with Efuse number*/
+	u8			efuse0x3d8;
+	u8			ext_trsw;		/*@with external TRSW  NO/Yes = 0/1*/
+	u8			ext_lna_gain;		/*@gain of external lna*/
+	boolean			is_in_hct_test;
+	u8			wifi_test;
+	boolean			is_dual_mac_smart_concurrent;
+	u32			bk_support_ability;	/*SD4 only*/
+	u8			with_extenal_ant_switch;
+	/*@cck agc relative*/
+	boolean			cck_new_agc;
+	s8			cck_lna_gain_table[8];
+	/*@-------------------------------------*/
+	u32			phydm_sys_up_time;
+	u8			num_rf_path;		/*@ex: 8821C=1, 8192E=2, 8814B=4*/
+	u32			soft_ap_special_setting;
+	s8			s8_dummy;
+	u8			u8_dummy;
+	u16			u16_dummy;
+	u32			u32_dummy;
+	u8			rfe_hwsetting_band;
+	u8			p_advance_ota;
+	boolean			hp_hw_id;
+	boolean			BOOLEAN_temp;
+	boolean			is_dfs_band;
+	u8			is_rx_blocking_en;
+	u16			fw_offload_ability;
+/*@-----------HOOK BEFORE REG INIT-----------*/
+/*@===========================================================*/
+/*@====[ CALL BY Reference ]=========================================*/
+/*@===========================================================*/
+
+	u64			*num_tx_bytes_unicast;	/*@TX Unicast byte cnt*/
+	u64			*num_rx_bytes_unicast;	/*@RX Unicast byte cnt*/
+	u8			*band_type;		/*@2.4G/5G = 0/1*/
+	u8			*sec_ch_offset;		/*@Secondary channel offset don't_care/below/above = 0/1/2*/
+	u8			*security;		/*@security mode Open/WEP/AES/TKIP = 0/1/2/3*/
+	u8			*band_width;		/*@20M/40M/80M = 0/1/2*/
+	u8			*channel;		/*@central CH number*/
+	boolean			*is_scan_in_process;
+	boolean			*is_power_saving;
+	u8			*one_path_cca;		/*@CCA path 2-path/path-A/path-B = 0/1/2; using enum odm_cca_path.*/
+	u8			*antenna_test;
+	boolean			*is_net_closed;
+	boolean			*is_fcs_mode_enable;
+	/*@--------- For 8723B IQK-------------------------------------*/
+	boolean			*is_1_antenna;
+	u8			*rf_default_path;	/* @0:S1, 1:S0 */
+	/*@-----------------------------------------------------------*/
+
+	u16			*forced_data_rate;
+	u8			*enable_antdiv;
+	u8			*en_adap_soml;
+	u8			*enable_adaptivity;
+	u8			*hub_usb_mode;		/*@1:USB2.0, 2:USB3.0*/
+	boolean			*is_fw_dw_rsvd_page_in_progress;
+	u32			*current_tx_tp;
+	u32			*current_rx_tp;
+	u8			*sounding_seq;
+	u32			*soft_ap_mode;
+	u8			*mp_mode;
+	u32			*interrupt_mask;
+	u8			*bb_op_mode;
+/*@===========================================================*/
+/*@====[ CALL BY VALUE ]===========================================*/
+/*@===========================================================*/
+
+	u8			disable_phydm_watchdog;
+	boolean			is_link_in_process;
+	boolean			is_wifi_direct;
+	boolean			is_wifi_display;
+	boolean			is_linked;
+	boolean			bsta_state;
+	u8			rssi_min;
+	u8			rssi_min_macid;
+	u8			pre_rssi_min;
+	u8			rssi_max;
+	u8			rssi_max_macid;
+	u8			rssi_min_by_path;
+	boolean			is_mp_chip;
+	boolean			is_one_entry_only;
+	u32			one_entry_macid;
+	u32			one_entry_tp;
+	u32			pre_one_entry_tp;
+	u8			pre_number_linked_client;
+	u8			number_linked_client;
+	u8			pre_number_active_client;
+	u8			number_active_client;
+	boolean			is_disable_phy_api;
+	u8			rssi_a;
+	u8			rssi_b;
+	u8			rssi_c;
+	u8			rssi_d;
+	s8			rxsc_80;
+	s8			rxsc_40;
+	s8			rxsc_20;
+	s8			rxsc_l;
+	u64			rssi_trsw;
+	u64			rssi_trsw_h;
+	u64			rssi_trsw_l;
+	u64			rssi_trsw_iso;
+	u8			tx_ant_status;
+	u8			rx_ant_status;
+	u8			cck_lna_idx;
+	u8			cck_vga_idx;
+	u8			curr_station_id;
+	u8			ofdm_agc_idx[4];
+	u8			rx_rate;
+	u8			rate_ss;
+	u8			tx_rate;
+	u8			linked_interval;
+	u8			pre_channel;
+	u32			txagc_offset_value_a;
+	boolean			is_txagc_offset_positive_a;
+	u32			txagc_offset_value_b;
+	boolean			is_txagc_offset_positive_b;
+	u8			ap_total_num;
+	/*@[traffic]*/
+	u8			traffic_load;
+	u8			pre_traffic_load;
+	u32			tx_tp;			/*@Mbps*/
+	u32			rx_tp;			/*@Mbps*/
+	u32			total_tp;		/*@Mbps*/
+	u8			txrx_state_all;		/*@0:tx, 1:rx, 2:bi-dir*/
+	u64			cur_tx_ok_cnt;
+	u64			cur_rx_ok_cnt;
+	u64			last_tx_ok_cnt;
+	u64			last_rx_ok_cnt;
+	u16			consecutive_idlel_time;	/*@unit: second*/
+	/*@---------------------------*/
+	boolean			is_bb_swing_offset_positive_a;
+	boolean			is_bb_swing_offset_positive_b;
+
+	/*@[DIG]*/
+	boolean			MPDIG_2G;		/*off MPDIG*/
+	u8			times_2g;		/*@for MP DIG*/
+	u8			force_igi;		/*@for debug*/
+
+	/*@[TDMA-DIG]*/
+	u8			tdma_dig_timer_ms;
+	u8			tdma_dig_state_number;
+	u8			tdma_dig_low_upper_bond;
+	u8			force_tdma_low_igi;
+	u8			force_tdma_high_igi;
+	u8			fix_expire_to_zero;
+	boolean			original_dig_restore;
+	/*@---------------------------*/
+
+	/*@[AntDiv]*/
+	u8			ant_div_type;
+	u8			antdiv_rssi;
+	u8			fat_comb_a;
+	u8			fat_comb_b;
+	u8			antdiv_intvl;
+	u8			ant_type;
+	u8			ant_type2;
+	u8			pre_ant_type;
+	u8			pre_ant_type2;
+	u8			antdiv_period;
+	u8			evm_antdiv_period;
+	u8			antdiv_select;
+	u8			antdiv_train_num; /*@training time for each antenna in EVM method*/
+	u8			stop_antdiv_rssi_th;
+	u16			stop_antdiv_tp_diff_th;
+	u16			stop_antdiv_tp_th;
+	u8			antdiv_tp_period;
+	u16			tp_active_th;
+	u8			tp_active_occur;
+	u8			path_select;
+	u8			antdiv_evm_en;
+	u8			bdc_holdstate;
+	u8			antdiv_counter;
+	/*@---------------------------*/
+
+	u8			ndpa_period;
+	boolean			h2c_rarpt_connect;
+	boolean			cck_agc_report_type; /*@1:4bit LNA, 0:3bit LNA */
+	u8			print_agc;
+	u8			la_mode;
+	/*@---8821C Antenna and RF Set BTG/WLG/WLA Select---------------*/
+	u8			current_rf_set_8821c;
+	u8			default_rf_set_8821c;
+	u8			current_ant_num_8821c;
+	u8			default_ant_num_8821c;
+	u8			rfe_type_expand;
+	/*@-----------------------------------------------------------*/
+	/*@---For Adaptivtiy---------------------------------------------*/
+	s8			TH_L2H_default;
+	s8			th_edcca_hl_diff_default;
+	s8			th_l2h_ini;
+	s8			th_edcca_hl_diff;
+	boolean			carrier_sense_enable;
+	/*@-----------------------------------------------------------*/
+
+	u8			pre_dbg_priority;
+	u8			nbi_set_result;
+	u8			c2h_cmd_start;
+	u8			fw_debug_trace[60];
+	u8			pre_c2h_seq;
+	boolean			fw_buff_is_enpty;
+	u32			data_frame_num;
+
+	/*@--- for noise detection ---------------------------------------*/
+	boolean			is_noisy_state;
+	boolean			noisy_decision; /*@b_noisy*/
+	boolean			pre_b_noisy;
+	u32			noisy_decision_smooth;
+	/*@-----------------------------------------------------------*/
+
+	/*@--- for MCC ant weighting ------------------------------------*/
+	boolean			is_stop_dym_ant_weighting;
+	/*@-----------------------------------------------------------*/
+
+	boolean			is_disable_dym_ecs;
+	boolean			is_disable_dym_ant_weighting;
+	struct sta_info		*odm_sta_info[ODM_ASSOCIATE_ENTRY_NUM];
+	struct cmn_sta_info	*phydm_sta_info[ODM_ASSOCIATE_ENTRY_NUM];
+	u8			phydm_macid_table[ODM_ASSOCIATE_ENTRY_NUM];/*@sta_idx = phydm_macid_table[HW_macid]*/
+
+#if (RATE_ADAPTIVE_SUPPORT == 1)
+	u16			currmin_rpt_time;
+	struct _phydm_txstatistic_ hw_stats;
+	struct _odm_ra_info_	ra_info[ODM_ASSOCIATE_ENTRY_NUM];
+/*Use mac_id as array index. STA mac_id=0*/
+/*VWiFi Client mac_id={1, ODM_ASSOCIATE_ENTRY_NUM-1} //YJ,add,120119*/
+#endif
+	/*@2012/02/14 MH Add to share 88E ra with other SW team*/
+	/*We need to colelct all support abilit to a proper area.*/
+	boolean			ra_support88e;
+	boolean			*is_driver_stopped;
+	boolean			*is_driver_is_going_to_pnp_set_power_sleep;
+	boolean			*pinit_adpt_in_progress;
+	boolean			is_user_assign_level;
+	u8			RSSI_BT;		/*@come from BT*/
+
+	/*@---PSD Relative ---------------------------------------------*/
+	boolean			is_psd_in_process;
+	boolean			is_psd_active;
+	/*@-----------------------------------------------------------*/
+
+	boolean			bsomlenabled;	/* @D-SoML control */
+	boolean			bhtstfdisabled;	/* @dynamic HTSTF gain control*/
+	boolean			disrxhpsoml;	/* @RxHP control with D-SoML*/
+	u32			n_iqk_cnt;
+	u32			n_iqk_ok_cnt;
+	u32			n_iqk_fail_cnt;
+
+#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
+	boolean			config_bbrf;
+#endif
+	boolean			is_disable_power_training;
+	boolean			is_bt_continuous_turn;
+	u8			enhance_pwr_th[3];
+	u8			set_pwr_th[3];
+	/*@----------Dyn Tx Pwr ---------------------------------------*/
+#ifdef BB_RAM_SUPPORT
+	struct phydm_bb_ram_ctrl p_bb_ram_ctrl;
+#endif
+	u8			dynamic_tx_high_power_lvl;
+	void	(*fill_desc_dyntxpwr)(void *dm, u8 *desc, u8 dyn_tx_power);
+	u8			last_dtp_lvl;
+	u8			min_power_index;
+	u32			tx_agc_ofdm_18_6;
+	/*-------------------------------------------------------------*/
+	u8			rx_pkt_type;
+
+#ifdef CONFIG_PHYDM_DFS_MASTER
+	u8			dfs_region_domain;
+	u8			*dfs_master_enabled;
+	/*@---phydm_radar_detect_with_dbg_parm start --------------------*/
+	u8			radar_detect_dbg_parm_en;
+	u32			radar_detect_reg_918;
+	u32			radar_detect_reg_91c;
+	u32			radar_detect_reg_920;
+	u32			radar_detect_reg_924;
+/*@-----------------------------------------------------------*/
+#endif
+
+/*@=== PHYDM Timer ========================================== (start)*/
+
+	struct phydm_timer_list	mpt_dig_timer;
+	struct phydm_timer_list	fast_ant_training_timer;
+#ifdef ODM_EVM_ENHANCE_ANTDIV
+	struct phydm_timer_list	evm_fast_ant_training_timer;
+#endif
+#ifdef PHYDM_TDMA_DIG_SUPPORT
+	struct phydm_timer_list tdma_dig_timer;
+#endif
+	struct phydm_timer_list	sbdcnt_timer;
+
+/*@=== PHYDM Workitem ======================================= (start)*/
+
+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
+#if USE_WORKITEM
+	RT_WORK_ITEM		fast_ant_training_workitem;
+	RT_WORK_ITEM		ra_rpt_workitem;
+	RT_WORK_ITEM		sbdcnt_workitem;
+	RT_WORK_ITEM		phydm_evm_antdiv_workitem;
+#endif
+#endif
+
+/*@=== PHYDM Structure ======================================== (start)*/
+	struct	phydm_func_poiner	phydm_func_handler;
+	struct	phydm_iot_center	iot_table;
+
+#ifdef ODM_CONFIG_BT_COEXIST
+	struct	phydm_bt_info		bt_info_table;
+#endif
+
+	struct	pkt_process_info	pkt_proc_struct;
+	struct phydm_adaptivity_struct	adaptivity;
+	struct _DFS_STATISTICS		dfs;
+	struct odm_noise_monitor	noise_level;
+	struct odm_phy_dbg_info		phy_dbg_info;
+
+#ifdef CONFIG_ADAPTIVE_SOML
+	struct adaptive_soml		dm_soml_table;
+#endif
+
+#if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY))
+	#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
+	struct _BF_DIV_COEX_		dm_bdc_table;
+	#endif
+
+	#if (defined(CONFIG_HL_SMART_ANTENNA))
+	struct smt_ant_honbo		dm_sat_table;
+	#endif
+#endif
+
+#if (defined(CONFIG_SMART_ANTENNA))
+	struct smt_ant			smtant_table;
+#endif
+
+	struct _hal_rf_			rf_table;	/*@for HALRF function*/
+	struct dm_rf_calibration_struct	rf_calibrate_info;
+	struct dm_iqk_info		IQK_info;
+	struct dm_dpk_info		dpk_info;
+
+#ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY
+	struct phydm_fat_struct		dm_fat_table;
+	struct sw_antenna_switch	dm_swat_table;
+#endif
+	struct phydm_dig_struct		dm_dig_table;
+#ifdef PHYDM_LNA_SAT_CHK_SUPPORT
+	struct phydm_lna_sat_t		dm_lna_sat_info;
+#endif
+
+#ifdef CONFIG_MCC_DM
+	struct _phydm_mcc_dm_ mcc_dm;
+#endif
+
+#ifdef PHYDM_SUPPORT_CCKPD
+	struct phydm_cckpd_struct	dm_cckpd_table;
+#endif
+
+#ifdef PHYDM_PRIMARY_CCA
+	struct phydm_pricca_struct	dm_pri_cca;
+#endif
+
+	struct ra_table			dm_ra_table;
+	struct phydm_fa_struct		false_alm_cnt;
+#ifdef PHYDM_TDMA_DIG_SUPPORT
+	struct phydm_fa_acc_struct	false_alm_cnt_acc;
+#ifdef IS_USE_NEW_TDMA
+	struct phydm_fa_acc_struct	false_alm_cnt_acc_low;
+#endif
+#endif
+	struct phydm_cfo_track_struct	dm_cfo_track;
+	struct ccx_info			dm_ccx_info;
+
+	struct odm_power_trim_data	power_trim_data;
+#if (RTL8822B_SUPPORT == 1)
+	struct drp_rtl8822b_struct	phydm_rtl8822b;
+#endif
+
+#ifdef CONFIG_PSD_TOOL
+	struct psd_info			dm_psd_table;
+#endif
+
+#if (PHYDM_LA_MODE_SUPPORT == 1)
+	struct rt_adcsmp		adcsmp;
+#endif
+
+#if (defined(CONFIG_PATH_DIVERSITY))
+	struct _ODM_PATH_DIVERSITY_	dm_path_div;
+#endif
+
+#if (defined(CONFIG_ANT_DETECTION))
+	struct _ANT_DETECTED_INFO	ant_detected_info;
+#endif
+
+#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
+#if (BEAMFORMING_SUPPORT == 1)
+	struct _RT_BEAMFORMING_INFO 	beamforming_info;
+#endif
+#endif
+#ifdef PHYDM_AUTO_DEGBUG
+	struct	phydm_auto_dbg_struct	auto_dbg_table;
+#endif
+
+	struct	phydm_pause_lv		pause_lv_table;
+	struct	phydm_api_stuc		api_table;
+#ifdef PHYDM_POWER_TRAINING_SUPPORT
+	struct	phydm_pow_train_stuc	pow_train_table;
+#endif
+
+#ifdef PHYDM_PMAC_TX_SETTING_SUPPORT
+	struct phydm_pmac_tx dm_pmac_tx_table;
+#endif
+
+#ifdef PHYDM_MP_SUPPORT
+	struct phydm_mp dm_mp_table;
+#endif
+/*@==========================================================*/
+
+#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
+
+#if (RT_PLATFORM != PLATFORM_LINUX)
+} dm_struct;	/*@DM_Dynamic_Mechanism_Structure*/
+#else
+};
+#endif
+
+#else	/*@for AP,CE Team*/
+};
+#endif
+
+enum phydm_adv_ota {
+	PHYDM_PATHB_1RCCA		= BIT(0),
+	PHYDM_HP_OTA_SETTING_A		= BIT(1),
+	PHYDM_HP_OTA_SETTING_B		= BIT(2),
+	PHYDM_ASUS_OTA_SETTING		= BIT(3),
+	PHYDM_ASUS_OTA_SETTING_CCK_PATH = BIT(4),
+	PHYDM_HP_OTA_SETTING_CCK_PATH	= BIT(5),
+	PHYDM_LENOVO_OTA_SETTING_NBI_CSI = BIT(6),
+
+};
+
+enum phydm_bb_op_mode {
+	PHYDM_PERFORMANCE_MODE	= 0,		/*Service one device*/
+	PHYDM_BALANCE_MODE	= 1,		/*@Service more than one device*/
+};
+
+enum phydm_structure_type {
+	PHYDM_FALSEALMCNT,
+	PHYDM_CFOTRACK,
+	PHYDM_ADAPTIVITY,
+	PHYDM_DFS,
+	PHYDM_ROMINFO,
+
+};
+
+enum odm_bb_config_type {
+	CONFIG_BB_PHY_REG,
+	CONFIG_BB_AGC_TAB,
+	CONFIG_BB_AGC_TAB_2G,
+	CONFIG_BB_AGC_TAB_5G,
+	CONFIG_BB_PHY_REG_PG,
+	CONFIG_BB_PHY_REG_MP,
+	CONFIG_BB_AGC_TAB_DIFF,
+	CONFIG_BB_RF_CAL_INIT,
+};
+
+enum odm_rf_config_type {
+	CONFIG_RF_RADIO,
+	CONFIG_RF_TXPWR_LMT,
+};
+
+enum odm_fw_config_type {
+	CONFIG_FW_NIC,
+	CONFIG_FW_NIC_2,
+	CONFIG_FW_AP,
+	CONFIG_FW_AP_2,
+	CONFIG_FW_MP,
+	CONFIG_FW_WOWLAN,
+	CONFIG_FW_WOWLAN_2,
+	CONFIG_FW_AP_WOWLAN,
+	CONFIG_FW_BT,
+};
+
+/*status code*/
+#if (DM_ODM_SUPPORT_TYPE != ODM_WIN)
+enum rt_status {
+	RT_STATUS_SUCCESS,
+	RT_STATUS_FAILURE,
+	RT_STATUS_PENDING,
+	RT_STATUS_RESOURCE,
+	RT_STATUS_INVALID_CONTEXT,
+	RT_STATUS_INVALID_PARAMETER,
+	RT_STATUS_NOT_SUPPORT,
+	RT_STATUS_OS_API_FAILED,
+};
+#endif	/*@end of enum rt_status definition*/
+
+void
+phydm_watchdog_lps(struct dm_struct *dm);
+
+void
+phydm_watchdog_lps_32k(struct dm_struct *dm);
+
+void
+phydm_txcurrentcalibration(struct dm_struct *dm);
+
+void
+phydm_dm_early_init(struct dm_struct *dm);
+
+void
+odm_dm_init(struct dm_struct *dm);
+
+void
+odm_dm_reset(struct dm_struct *dm);
+
+void
+phydm_fwoffload_ability_init(struct dm_struct *dm,
+			     enum phydm_offload_ability offload_ability);
+
+void
+phydm_fwoffload_ability_clear(struct dm_struct *dm,
+			      enum phydm_offload_ability offload_ability);
+
+void
+phydm_supportability_en(void *dm_void, char input[][16], u32 *_used,
+			char *output, u32 *_out_len);
+
+void
+phydm_pause_dm_watchdog(void *dm_void, enum phydm_pause_type pause_type);
+
+void
+phydm_watchdog(struct dm_struct *dm);
+
+void
+phydm_watchdog_mp(struct dm_struct *dm);
+
+u8
+phydm_pause_func(void *dm_void, enum phydm_func_idx pause_func,
+		 enum phydm_pause_type pause_type,
+		 enum phydm_pause_level pause_lv, u8 val_lehgth, u32 *val_buf);
+
+void
+phydm_pause_func_console(void *dm_void, char input[][16], u32 *_used,
+			 char *output, u32 *_out_len);
+
+void
+odm_cmn_info_init(struct dm_struct *dm, enum odm_cmninfo cmn_info, u64 value);
+
+void
+odm_cmn_info_hook(struct dm_struct *dm, enum odm_cmninfo cmn_info, void *value);
+
+void
+odm_cmn_info_update(struct dm_struct *dm, u32 cmn_info, u64 value);
+
+u32
+phydm_cmn_info_query(struct dm_struct *dm, enum phydm_info_query info_type);
+
+void
+odm_init_all_timers(struct dm_struct *dm);
+
+void
+odm_cancel_all_timers(struct dm_struct *dm);
+
+void
+odm_release_all_timers(struct dm_struct *dm);
+
+void *
+phydm_get_structure(struct dm_struct *dm, u8 structure_type);
+
+void
+phydm_dc_cancellation(struct dm_struct *dm);
+
+void
+phydm_receiver_blocking(void *dm_void);
+
+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
+void
+odm_init_all_work_items(
+	struct dm_struct	*dm
+);
+void
+odm_free_all_work_items(
+	struct dm_struct	*dm
+);
+#endif	/*@#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)*/
+
+#if (DM_ODM_SUPPORT_TYPE == ODM_CE)
+void
+odm_dtc(struct dm_struct *dm);
+#endif
+
+#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
+void
+odm_init_all_threads(
+	struct dm_struct	*dm
+);
+
+void
+odm_stop_all_threads(
+	struct dm_struct	*dm
+);
+#endif
+
+#endif
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/phydm_hwconfig.c linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/phydm_hwconfig.c
--- linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/phydm_hwconfig.c	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/phydm_hwconfig.c	2020-04-10 16:35:06.825660488 +0300
@@ -0,0 +1,1315 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017  Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * The full GNU General Public License is included in this distribution in the
+ * file called LICENSE.
+ *
+ * Contact Information:
+ * wlanfae <wlanfae@realtek.com>
+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
+ * Hsinchu 300, Taiwan.
+ *
+ * Larry Finger <Larry.Finger@lwfinger.net>
+ *
+ *****************************************************************************/
+
+/*@************************************************************
+ * include files
+ ************************************************************/
+
+#include "mp_precomp.h"
+#include "phydm_precomp.h"
+
+#define READ_AND_CONFIG_MP(ic, txt) (odm_read_and_config_mp_##ic##txt(dm))
+#define READ_AND_CONFIG_TC(ic, txt) (odm_read_and_config_tc_##ic##txt(dm))
+
+#if (PHYDM_TESTCHIP_SUPPORT == 1)
+#define READ_AND_CONFIG(ic, txt)                     \
+	do {                                         \
+		if (dm->is_mp_chip)                  \
+			READ_AND_CONFIG_MP(ic, txt); \
+		else                                 \
+			READ_AND_CONFIG_TC(ic, txt); \
+	} while (0)
+#else
+#define READ_AND_CONFIG READ_AND_CONFIG_MP
+#endif
+
+#define GET_VERSION_MP(ic, txt) (odm_get_version_mp_##ic##txt())
+#define GET_VERSION_TC(ic, txt) (odm_get_version_tc_##ic##txt())
+
+#if (PHYDM_TESTCHIP_SUPPORT == 1)
+#define GET_VERSION(ic, txt) (dm->is_mp_chip ? GET_VERSION_MP(ic, txt) : GET_VERSION_TC(ic, txt))
+#else
+#define GET_VERSION(ic, txt) GET_VERSION_MP(ic, txt)
+#endif
+
+enum hal_status
+odm_config_rf_with_header_file(struct dm_struct *dm,
+			       enum odm_rf_config_type config_type,
+			       u8 e_rf_path)
+{
+#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
+	void *adapter = dm->adapter;
+	PMGNT_INFO mgnt_info = &((PADAPTER)adapter)->MgntInfo;
+#endif
+	enum hal_status result = HAL_STATUS_SUCCESS;
+
+	PHYDM_DBG(dm, ODM_COMP_INIT, "===>%s (%s)\n", __func__,
+		  (dm->is_mp_chip) ? "MPChip" : "TestChip");
+	PHYDM_DBG(dm, ODM_COMP_INIT,
+		  "support_platform: 0x%X, support_interface: 0x%X, board_type: 0x%X\n",
+		  dm->support_platform, dm->support_interface, dm->board_type);
+
+/* @1 AP doesn't use PHYDM power tracking table in these ICs */
+#if (DM_ODM_SUPPORT_TYPE != ODM_AP)
+#if (RTL8812A_SUPPORT == 1)
+	if (dm->support_ic_type == ODM_RTL8812) {
+		if (config_type == CONFIG_RF_RADIO) {
+			if (e_rf_path == RF_PATH_A)
+				READ_AND_CONFIG_MP(8812a, _radioa);
+			else if (e_rf_path == RF_PATH_B)
+				READ_AND_CONFIG_MP(8812a, _radiob);
+		} else if (config_type == CONFIG_RF_TXPWR_LMT) {
+#if (DM_ODM_SUPPORT_TYPE & ODM_WIN) && (DEV_BUS_TYPE == RT_PCI_INTERFACE)
+			HAL_DATA_TYPE * hal_data = GET_HAL_DATA(((PADAPTER)adapter));
+			if ((hal_data->EEPROMSVID == 0x17AA && hal_data->EEPROMSMID == 0xA811) ||
+			    (hal_data->EEPROMSVID == 0x10EC && hal_data->EEPROMSMID == 0xA812) ||
+			    (hal_data->EEPROMSVID == 0x10EC && hal_data->EEPROMSMID == 0x8812))
+				READ_AND_CONFIG_MP(8812a, _txpwr_lmt_hm812a03);
+			else
+#endif
+				READ_AND_CONFIG_MP(8812a, _txpwr_lmt);
+		}
+	}
+#endif
+#if (RTL8821A_SUPPORT == 1)
+	if (dm->support_ic_type == ODM_RTL8821) {
+		if (config_type == CONFIG_RF_RADIO) {
+			if (e_rf_path == RF_PATH_A)
+				READ_AND_CONFIG_MP(8821a, _radioa);
+		} else if (config_type == CONFIG_RF_TXPWR_LMT) {
+			if (dm->support_interface == ODM_ITRF_USB) {
+				if (dm->ext_pa_5g || dm->ext_lna_5g)
+					READ_AND_CONFIG_MP(8821a, _txpwr_lmt_8811a_u_fem);
+				else
+					READ_AND_CONFIG_MP(8821a, _txpwr_lmt_8811a_u_ipa);
+			} else {
+#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
+				if (mgnt_info->CustomerID == RT_CID_8821AE_ASUS_MB)
+					READ_AND_CONFIG_MP(8821a, _txpwr_lmt_8821a_sar_8mm);
+				else if (mgnt_info->CustomerID == RT_CID_ASUS_NB)
+					READ_AND_CONFIG_MP(8821a, _txpwr_lmt_8821a_sar_5mm);
+				else
+#endif
+					READ_AND_CONFIG_MP(8821a, _txpwr_lmt_8821a);
+			}
+		}
+	}
+#endif
+#if (RTL8192E_SUPPORT == 1)
+	if (dm->support_ic_type == ODM_RTL8192E) {
+		if (config_type == CONFIG_RF_RADIO) {
+			if (e_rf_path == RF_PATH_A)
+				READ_AND_CONFIG_MP(8192e, _radioa);
+			else if (e_rf_path == RF_PATH_B)
+				READ_AND_CONFIG_MP(8192e, _radiob);
+		} else if (config_type == CONFIG_RF_TXPWR_LMT) {
+#if (DM_ODM_SUPPORT_TYPE & ODM_WIN) && (DEV_BUS_TYPE == RT_PCI_INTERFACE) /*Refine by Vincent Lan for 5mm SAR pwr limit*/
+			HAL_DATA_TYPE * hal_data = GET_HAL_DATA(((PADAPTER)adapter));
+
+			if ((hal_data->EEPROMSVID == 0x11AD && hal_data->EEPROMSMID == 0x8192) ||
+			    (hal_data->EEPROMSVID == 0x11AD && hal_data->EEPROMSMID == 0x8193))
+				READ_AND_CONFIG_MP(8192e, _txpwr_lmt_8192e_sar_5mm);
+			else
+#endif
+				READ_AND_CONFIG_MP(8192e, _txpwr_lmt);
+		}
+	}
+#endif
+#if (RTL8723D_SUPPORT == 1)
+	if (dm->support_ic_type == ODM_RTL8723D) {
+		if (config_type == CONFIG_RF_RADIO) {
+			if (e_rf_path == RF_PATH_A)
+				READ_AND_CONFIG_MP(8723d, _radioa);
+		} else if (config_type == CONFIG_RF_TXPWR_LMT) {
+			READ_AND_CONFIG_MP(8723d, _txpwr_lmt);
+		}
+	}
+#endif
+/* @JJ ADD 20161014 */
+#if (RTL8710B_SUPPORT == 1)
+	if (dm->support_ic_type == ODM_RTL8710B) {
+		if (config_type == CONFIG_RF_RADIO) {
+			if (e_rf_path == RF_PATH_A)
+				READ_AND_CONFIG_MP(8710b, _radioa);
+		} else if (config_type == CONFIG_RF_TXPWR_LMT)
+			READ_AND_CONFIG_MP(8710b, _txpwr_lmt);
+	}
+#endif
+
+#endif /* @(DM_ODM_SUPPORT_TYPE !=  ODM_AP) */
+/* @1 All platforms support */
+#if (RTL8188E_SUPPORT == 1)
+	if (dm->support_ic_type == ODM_RTL8188E) {
+		if (config_type == CONFIG_RF_RADIO) {
+			if (e_rf_path == RF_PATH_A)
+				READ_AND_CONFIG_MP(8188e, _radioa);
+		} else if (config_type == CONFIG_RF_TXPWR_LMT)
+			READ_AND_CONFIG_MP(8188e, _txpwr_lmt);
+	}
+#endif
+#if (RTL8723B_SUPPORT == 1)
+	if (dm->support_ic_type == ODM_RTL8723B) {
+		if (config_type == CONFIG_RF_RADIO)
+			READ_AND_CONFIG_MP(8723b, _radioa);
+		else if (config_type == CONFIG_RF_TXPWR_LMT)
+			READ_AND_CONFIG_MP(8723b, _txpwr_lmt);
+	}
+#endif
+#if (RTL8814A_SUPPORT == 1)
+	if (dm->support_ic_type == ODM_RTL8814A) {
+		if (config_type == CONFIG_RF_RADIO) {
+			if (e_rf_path == RF_PATH_A)
+				READ_AND_CONFIG_MP(8814a, _radioa);
+			else if (e_rf_path == RF_PATH_B)
+				READ_AND_CONFIG_MP(8814a, _radiob);
+			else if (e_rf_path == RF_PATH_C)
+				READ_AND_CONFIG_MP(8814a, _radioc);
+			else if (e_rf_path == RF_PATH_D)
+				READ_AND_CONFIG_MP(8814a, _radiod);
+		} else if (config_type == CONFIG_RF_TXPWR_LMT) {
+			if (dm->rfe_type == 0)
+				READ_AND_CONFIG_MP(8814a, _txpwr_lmt_type0);
+			else if (dm->rfe_type == 1)
+				READ_AND_CONFIG_MP(8814a, _txpwr_lmt_type1);
+			else if (dm->rfe_type == 2)
+				READ_AND_CONFIG_MP(8814a, _txpwr_lmt_type2);
+			else if (dm->rfe_type == 3)
+				READ_AND_CONFIG_MP(8814a, _txpwr_lmt_type3);
+			else if (dm->rfe_type == 5)
+				READ_AND_CONFIG_MP(8814a, _txpwr_lmt_type5);
+			else if (dm->rfe_type == 7)
+				READ_AND_CONFIG_MP(8814a, _txpwr_lmt_type7);
+			else if (dm->rfe_type == 8)
+				READ_AND_CONFIG_MP(8814a, _txpwr_lmt_type8);
+			else
+				READ_AND_CONFIG_MP(8814a, _txpwr_lmt);
+		}
+	}
+#endif
+#if (RTL8703B_SUPPORT == 1)
+	if (dm->support_ic_type == ODM_RTL8703B) {
+		if (config_type == CONFIG_RF_RADIO) {
+			if (e_rf_path == RF_PATH_A)
+				READ_AND_CONFIG_MP(8703b, _radioa);
+		}
+	}
+#endif
+#if (RTL8188F_SUPPORT == 1)
+	if (dm->support_ic_type == ODM_RTL8188F) {
+		if (config_type == CONFIG_RF_RADIO) {
+			if (e_rf_path == RF_PATH_A)
+				READ_AND_CONFIG_MP(8188f, _radioa);
+		} else if (config_type == CONFIG_RF_TXPWR_LMT)
+			READ_AND_CONFIG_MP(8188f, _txpwr_lmt);
+	}
+#endif
+#if (RTL8822B_SUPPORT == 1)
+	if (dm->support_ic_type == ODM_RTL8822B) {
+		if (config_type == CONFIG_RF_RADIO) {
+			if (e_rf_path == RF_PATH_A)
+				READ_AND_CONFIG_MP(8822b, _radioa);
+			else if (e_rf_path == RF_PATH_B)
+				READ_AND_CONFIG_MP(8822b, _radiob);
+		} else if (config_type == CONFIG_RF_TXPWR_LMT) {
+			if (dm->rfe_type == 5)
+				READ_AND_CONFIG_MP(8822b, _txpwr_lmt_type5);
+			else if (dm->rfe_type == 2)
+				READ_AND_CONFIG_MP(8822b, _txpwr_lmt_type2);
+			else if (dm->rfe_type == 3)
+				READ_AND_CONFIG_MP(8822b, _txpwr_lmt_type3);
+			else if (dm->rfe_type == 4)
+				READ_AND_CONFIG_MP(8822b, _txpwr_lmt_type4);
+			else if (dm->rfe_type == 12)
+				READ_AND_CONFIG_MP(8822b, _txpwr_lmt_type12);
+			else if (dm->rfe_type == 15)
+				READ_AND_CONFIG_MP(8822b, _txpwr_lmt_type15);
+			else if (dm->rfe_type == 16)
+				READ_AND_CONFIG_MP(8822b, _txpwr_lmt_type16);
+			else if (dm->rfe_type == 17)
+				READ_AND_CONFIG_MP(8822b, _txpwr_lmt_type17);
+			else if (dm->rfe_type == 18)
+				READ_AND_CONFIG_MP(8822b, _txpwr_lmt_type18);
+			else
+				READ_AND_CONFIG_MP(8822b, _txpwr_lmt);
+		}
+	}
+#endif
+
+#if (RTL8197F_SUPPORT == 1)
+	if (dm->support_ic_type == ODM_RTL8197F) {
+		if (config_type == CONFIG_RF_RADIO) {
+			if (e_rf_path == RF_PATH_A)
+				READ_AND_CONFIG_MP(8197f, _radioa);
+			else if (e_rf_path == RF_PATH_B)
+				READ_AND_CONFIG_MP(8197f, _radiob);
+		}
+	}
+#endif
+/*@jj add 20170822*/
+#if (RTL8192F_SUPPORT == 1)
+	if (dm->support_ic_type == ODM_RTL8192F) {
+		if (config_type == CONFIG_RF_RADIO) {
+			if (e_rf_path == RF_PATH_A)
+				READ_AND_CONFIG_MP(8192f, _radioa);
+			else if (e_rf_path == RF_PATH_B)
+				READ_AND_CONFIG_MP(8192f, _radiob);
+		} else if (config_type == CONFIG_RF_TXPWR_LMT) {
+			if (dm->rfe_type == 0)
+				READ_AND_CONFIG_MP(8192f, _txpwr_lmt_type0);
+			else if (dm->rfe_type == 1)
+				READ_AND_CONFIG_MP(8192f, _txpwr_lmt_type1);
+			else if (dm->rfe_type == 2)
+				READ_AND_CONFIG_MP(8192f, _txpwr_lmt_type2);
+			else if (dm->rfe_type == 3)
+				READ_AND_CONFIG_MP(8192f, _txpwr_lmt_type3);
+			else if (dm->rfe_type == 4)
+				READ_AND_CONFIG_MP(8192f, _txpwr_lmt_type4);
+			else if (dm->rfe_type == 5)
+				READ_AND_CONFIG_MP(8192f, _txpwr_lmt_type5);
+			else if (dm->rfe_type == 6)
+				READ_AND_CONFIG_MP(8192f, _txpwr_lmt_type6);
+			else if (dm->rfe_type == 7)
+				READ_AND_CONFIG_MP(8192f, _txpwr_lmt_type7);
+			else if (dm->rfe_type == 8)
+				READ_AND_CONFIG_MP(8192f, _txpwr_lmt_type8);
+			else if (dm->rfe_type == 9)
+				READ_AND_CONFIG_MP(8192f, _txpwr_lmt_type9);
+			else if (dm->rfe_type == 10)
+				READ_AND_CONFIG_MP(8192f, _txpwr_lmt_type10);
+			else if (dm->rfe_type == 11)
+				READ_AND_CONFIG_MP(8192f, _txpwr_lmt_type11);
+			else if (dm->rfe_type == 12)
+				READ_AND_CONFIG_MP(8192f, _txpwr_lmt_type12);
+			else if (dm->rfe_type == 13)
+				READ_AND_CONFIG_MP(8192f, _txpwr_lmt_type13);
+			else if (dm->rfe_type == 14)
+				READ_AND_CONFIG_MP(8192f, _txpwr_lmt_type14);
+			else if (dm->rfe_type == 15)
+				READ_AND_CONFIG_MP(8192f, _txpwr_lmt_type15);
+			else if (dm->rfe_type == 16)
+				READ_AND_CONFIG_MP(8192f, _txpwr_lmt_type16);
+			else if (dm->rfe_type == 17)
+				READ_AND_CONFIG_MP(8192f, _txpwr_lmt_type17);
+			else if (dm->rfe_type == 18)
+				READ_AND_CONFIG_MP(8192f, _txpwr_lmt_type18);
+			else if (dm->rfe_type == 19)
+				READ_AND_CONFIG_MP(8192f, _txpwr_lmt_type19);
+			else if (dm->rfe_type == 20)
+				READ_AND_CONFIG_MP(8192f, _txpwr_lmt_type20);
+			else if (dm->rfe_type == 21)
+				READ_AND_CONFIG_MP(8192f, _txpwr_lmt_type21);
+			else if (dm->rfe_type == 22)
+				READ_AND_CONFIG_MP(8192f, _txpwr_lmt_type22);
+			else if (dm->rfe_type == 23)
+				READ_AND_CONFIG_MP(8192f, _txpwr_lmt_type23);
+			else if (dm->rfe_type == 24)
+				READ_AND_CONFIG_MP(8192f, _txpwr_lmt_type24);
+			else if (dm->rfe_type == 25)
+				READ_AND_CONFIG_MP(8192f, _txpwr_lmt_type25);
+			else if (dm->rfe_type == 26)
+				READ_AND_CONFIG_MP(8192f, _txpwr_lmt_type26);
+			else if (dm->rfe_type == 27)
+				READ_AND_CONFIG_MP(8192f, _txpwr_lmt_type27);
+			else if (dm->rfe_type == 28)
+				READ_AND_CONFIG_MP(8192f, _txpwr_lmt_type28);
+			else if (dm->rfe_type == 29)
+				READ_AND_CONFIG_MP(8192f, _txpwr_lmt_type29);
+			else if (dm->rfe_type == 30)
+				READ_AND_CONFIG_MP(8192f, _txpwr_lmt_type30);
+			else if (dm->rfe_type == 31)
+				READ_AND_CONFIG_MP(8192f, _txpwr_lmt_type31);
+			else
+				READ_AND_CONFIG_MP(8192f, _txpwr_lmt);
+		}
+	}
+#endif
+#if (RTL8821C_SUPPORT == 1)
+	if (dm->support_ic_type == ODM_RTL8821C) {
+		if (config_type == CONFIG_RF_RADIO) {
+			if (e_rf_path == RF_PATH_A)
+				READ_AND_CONFIG(8821c, _radioa);
+		} else if (config_type == CONFIG_RF_TXPWR_LMT) {
+			READ_AND_CONFIG(8821c, _txpwr_lmt);
+		}
+	}
+#endif
+#if (RTL8195B_SUPPORT == 1)
+	if (dm->support_ic_type == ODM_RTL8195B) {
+		if (config_type == CONFIG_RF_RADIO) {
+			if (e_rf_path == RF_PATH_A)
+				READ_AND_CONFIG(8195b, _radioa);
+		}
+		#if 0
+		else if (config_type == CONFIG_RF_TXPWR_LMT) {
+			READ_AND_CONFIG(8821c, _txpwr_lmt);
+			/*@*/
+		}
+		#endif
+	}
+#endif
+#if (RTL8198F_SUPPORT == 1)
+	if (dm->support_ic_type == ODM_RTL8198F) {
+		if (config_type == CONFIG_RF_RADIO) {
+			if (e_rf_path == RF_PATH_A)
+				READ_AND_CONFIG_MP(8198f, _radioa);
+			else if (e_rf_path == RF_PATH_B)
+				READ_AND_CONFIG_MP(8198f, _radiob);
+			else if (e_rf_path == RF_PATH_C)
+				READ_AND_CONFIG_MP(8198f, _radioc);
+			else if (e_rf_path == RF_PATH_D)
+				READ_AND_CONFIG_MP(8198f, _radiod);
+		}
+	}
+#endif
+
+	if (config_type == CONFIG_RF_RADIO) {
+		if (dm->fw_offload_ability & PHYDM_PHY_PARAM_OFFLOAD) {
+			result = phydm_set_reg_by_fw(dm,
+						     PHYDM_HALMAC_CMD_END,
+						     0,
+						     0,
+						     0,
+						     (enum rf_path)0,
+						     0);
+			PHYDM_DBG(dm, ODM_COMP_INIT,
+				  "rf param offload end!result = %d", result);
+		}
+	}
+
+	return result;
+}
+
+enum hal_status
+odm_config_rf_with_tx_pwr_track_header_file(struct dm_struct *dm)
+{
+	PHYDM_DBG(dm, ODM_COMP_INIT, "===>%s (%s)\n", __func__,
+		  (dm->is_mp_chip) ? "MPChip" : "TestChip");
+	PHYDM_DBG(dm, ODM_COMP_INIT,
+		  "support_platform: 0x%X, support_interface: 0x%X, board_type: 0x%X\n",
+		  dm->support_platform, dm->support_interface, dm->board_type);
+
+/* @1 AP doesn't use PHYDM power tracking table in these ICs */
+#if (DM_ODM_SUPPORT_TYPE != ODM_AP)
+#if RTL8821A_SUPPORT
+	if (dm->support_ic_type == ODM_RTL8821) {
+		if (dm->support_interface == ODM_ITRF_PCIE)
+			READ_AND_CONFIG_MP(8821a, _txpowertrack_pcie);
+		else if (dm->support_interface == ODM_ITRF_USB)
+			READ_AND_CONFIG_MP(8821a, _txpowertrack_usb);
+		else if (dm->support_interface == ODM_ITRF_SDIO)
+			READ_AND_CONFIG_MP(8821a, _txpowertrack_sdio);
+	}
+#endif
+#if RTL8812A_SUPPORT
+	if (dm->support_ic_type == ODM_RTL8812) {
+		if (dm->support_interface == ODM_ITRF_PCIE)
+			READ_AND_CONFIG_MP(8812a, _txpowertrack_pcie);
+		else if (dm->support_interface == ODM_ITRF_USB) {
+			if (dm->rfe_type == 3 && dm->is_mp_chip)
+				READ_AND_CONFIG_MP(8812a, _txpowertrack_rfe3);
+			else
+				READ_AND_CONFIG_MP(8812a, _txpowertrack_usb);
+		}
+	}
+#endif
+#if RTL8192E_SUPPORT
+	if (dm->support_ic_type == ODM_RTL8192E) {
+		if (dm->support_interface == ODM_ITRF_PCIE)
+			READ_AND_CONFIG_MP(8192e, _txpowertrack_pcie);
+		else if (dm->support_interface == ODM_ITRF_USB)
+			READ_AND_CONFIG_MP(8192e, _txpowertrack_usb);
+		else if (dm->support_interface == ODM_ITRF_SDIO)
+			READ_AND_CONFIG_MP(8192e, _txpowertrack_sdio);
+	}
+#endif
+#if RTL8723D_SUPPORT
+	if (dm->support_ic_type == ODM_RTL8723D) {
+		if (dm->support_interface == ODM_ITRF_PCIE)
+			READ_AND_CONFIG_MP(8723d, _txpowertrack_pcie);
+		else if (dm->support_interface == ODM_ITRF_USB)
+			READ_AND_CONFIG_MP(8723d, _txpowertrack_usb);
+		else if (dm->support_interface == ODM_ITRF_SDIO)
+			READ_AND_CONFIG_MP(8723d, _txpowertrack_sdio);
+
+		READ_AND_CONFIG_MP(8723d, _txxtaltrack);
+	}
+#endif
+/* @JJ ADD 20161014 */
+#if RTL8710B_SUPPORT
+	if (dm->support_ic_type == ODM_RTL8710B) {
+		if (dm->package_type == 1)
+			READ_AND_CONFIG_MP(8710b, _txpowertrack_qfn48m_smic);
+		else if (dm->package_type == 5)
+			READ_AND_CONFIG_MP(8710b, _txpowertrack_qfn48m_umc);
+
+		READ_AND_CONFIG_MP(8710b, _txxtaltrack);
+	}
+#endif
+#if RTL8188E_SUPPORT
+	if (dm->support_ic_type == ODM_RTL8188E) {
+		if (odm_get_mac_reg(dm, R_0xf0, 0xF000) >= 8) { /*@if 0xF0[15:12] >= 8, SMIC*/
+			if (dm->support_interface == ODM_ITRF_PCIE)
+				READ_AND_CONFIG_MP(8188e, _txpowertrack_pcie_icut);
+			else if (dm->support_interface == ODM_ITRF_USB)
+				READ_AND_CONFIG_MP(8188e, _txpowertrack_usb_icut);
+			else if (dm->support_interface == ODM_ITRF_SDIO)
+				READ_AND_CONFIG_MP(8188e, _txpowertrack_sdio_icut);
+		} else { /*@else 0xF0[15:12] < 8, TSMC*/
+			if (dm->support_interface == ODM_ITRF_PCIE)
+				READ_AND_CONFIG_MP(8188e, _txpowertrack_pcie);
+			else if (dm->support_interface == ODM_ITRF_USB)
+				READ_AND_CONFIG_MP(8188e, _txpowertrack_usb);
+			else if (dm->support_interface == ODM_ITRF_SDIO)
+				READ_AND_CONFIG_MP(8188e, _txpowertrack_sdio);
+		}
+	}
+#endif
+#endif /* @(DM_ODM_SUPPORT_TYPE !=  ODM_AP) */
+/* @1 All platforms support */
+#if RTL8723B_SUPPORT
+	if (dm->support_ic_type == ODM_RTL8723B) {
+		if (dm->support_interface == ODM_ITRF_PCIE)
+			READ_AND_CONFIG_MP(8723b, _txpowertrack_pcie);
+		else if (dm->support_interface == ODM_ITRF_USB)
+			READ_AND_CONFIG_MP(8723b, _txpowertrack_usb);
+		else if (dm->support_interface == ODM_ITRF_SDIO)
+			READ_AND_CONFIG_MP(8723b, _txpowertrack_sdio);
+	}
+#endif
+#if RTL8814A_SUPPORT
+	if (dm->support_ic_type == ODM_RTL8814A) {
+		if (dm->rfe_type == 0)
+			READ_AND_CONFIG_MP(8814a, _txpowertrack_type0);
+		else if (dm->rfe_type == 2)
+			READ_AND_CONFIG_MP(8814a, _txpowertrack_type2);
+		else if (dm->rfe_type == 5)
+			READ_AND_CONFIG_MP(8814a, _txpowertrack_type5);
+		else if (dm->rfe_type == 7)
+			READ_AND_CONFIG_MP(8814a, _txpowertrack_type7);
+		else if (dm->rfe_type == 8)
+			READ_AND_CONFIG_MP(8814a, _txpowertrack_type8);
+		else
+			READ_AND_CONFIG_MP(8814a, _txpowertrack);
+
+		READ_AND_CONFIG_MP(8814a, _txpowertssi);
+	}
+#endif
+#if RTL8703B_SUPPORT
+	if (dm->support_ic_type == ODM_RTL8703B) {
+		if (dm->support_interface == ODM_ITRF_USB)
+			READ_AND_CONFIG_MP(8703b, _txpowertrack_usb);
+		else if (dm->support_interface == ODM_ITRF_SDIO)
+			READ_AND_CONFIG_MP(8703b, _txpowertrack_sdio);
+
+		READ_AND_CONFIG_MP(8703b, _txxtaltrack);
+	}
+#endif
+#if RTL8188F_SUPPORT
+	if (dm->support_ic_type == ODM_RTL8188F) {
+		if (dm->support_interface == ODM_ITRF_USB)
+			READ_AND_CONFIG_MP(8188f, _txpowertrack_usb);
+		else if (dm->support_interface == ODM_ITRF_SDIO)
+			READ_AND_CONFIG_MP(8188f, _txpowertrack_sdio);
+	}
+#endif
+#if RTL8822B_SUPPORT
+	if (dm->support_ic_type == ODM_RTL8822B) {
+		if (dm->rfe_type == 0)
+			READ_AND_CONFIG_MP(8822b, _txpowertrack_type0);
+		else if (dm->rfe_type == 1)
+			READ_AND_CONFIG_MP(8822b, _txpowertrack_type1);
+		else if (dm->rfe_type == 2)
+			READ_AND_CONFIG_MP(8822b, _txpowertrack_type2);
+		else if ((dm->rfe_type == 3) || (dm->rfe_type == 5))
+			READ_AND_CONFIG_MP(8822b, _txpowertrack_type3_type5);
+		else if (dm->rfe_type == 4)
+			READ_AND_CONFIG_MP(8822b, _txpowertrack_type4);
+		else if (dm->rfe_type == 6)
+			READ_AND_CONFIG_MP(8822b, _txpowertrack_type6);
+		else if (dm->rfe_type == 7)
+			READ_AND_CONFIG_MP(8822b, _txpowertrack_type7);
+		else if (dm->rfe_type == 8)
+			READ_AND_CONFIG_MP(8822b, _txpowertrack_type8);
+		else if (dm->rfe_type == 9)
+			READ_AND_CONFIG_MP(8822b, _txpowertrack_type9);
+		else if (dm->rfe_type == 10)
+			READ_AND_CONFIG_MP(8822b, _txpowertrack_type10);
+		else if (dm->rfe_type == 11)
+			READ_AND_CONFIG_MP(8822b, _txpowertrack_type11);
+		else if (dm->rfe_type == 12)
+			READ_AND_CONFIG_MP(8822b, _txpowertrack_type12);
+		else if (dm->rfe_type == 13)
+			READ_AND_CONFIG_MP(8822b, _txpowertrack_type13);
+		else if (dm->rfe_type == 14)
+			READ_AND_CONFIG_MP(8822b, _txpowertrack_type14);
+		else if (dm->rfe_type == 15)
+			READ_AND_CONFIG_MP(8822b, _txpowertrack_type15);
+		else if (dm->rfe_type == 16)
+			READ_AND_CONFIG_MP(8822b, _txpowertrack_type16);
+		else if (dm->rfe_type == 17)
+			READ_AND_CONFIG_MP(8822b, _txpowertrack_type17);
+		else if (dm->rfe_type == 18)
+			READ_AND_CONFIG_MP(8822b, _txpowertrack_type18);
+		else
+			READ_AND_CONFIG_MP(8822b, _txpowertrack);
+	}
+#endif
+#if RTL8197F_SUPPORT
+	if (dm->support_ic_type == ODM_RTL8197F) {
+		if (dm->rfe_type == 0)
+			READ_AND_CONFIG_MP(8197f, _txpowertrack_type0);
+		else if (dm->rfe_type == 1)
+			READ_AND_CONFIG_MP(8197f, _txpowertrack_type1);
+		else
+			READ_AND_CONFIG_MP(8197f, _txpowertrack);
+	}
+#endif
+/*@jj add 20170822*/
+#if RTL8192F_SUPPORT
+	if (dm->support_ic_type == ODM_RTL8192F) {
+		if (dm->rfe_type == 0)
+			READ_AND_CONFIG_MP(8192f, _txpowertrack_type0);
+		else if (dm->rfe_type == 1)
+			READ_AND_CONFIG_MP(8192f, _txpowertrack_type1);
+		else if (dm->rfe_type == 2)
+			READ_AND_CONFIG_MP(8192f, _txpowertrack_type2);
+		else if (dm->rfe_type == 3)
+			READ_AND_CONFIG_MP(8192f, _txpowertrack_type3);
+		else if (dm->rfe_type == 4)
+			READ_AND_CONFIG_MP(8192f, _txpowertrack_type4);
+		else if (dm->rfe_type == 5)
+			READ_AND_CONFIG_MP(8192f, _txpowertrack_type5);
+		else if (dm->rfe_type == 6)
+			READ_AND_CONFIG_MP(8192f, _txpowertrack_type6);
+		else if (dm->rfe_type == 7)
+			READ_AND_CONFIG_MP(8192f, _txpowertrack_type7);
+		else if (dm->rfe_type == 8)
+			READ_AND_CONFIG_MP(8192f, _txpowertrack_type8);
+		else if (dm->rfe_type == 9)
+			READ_AND_CONFIG_MP(8192f, _txpowertrack_type9);
+		else if (dm->rfe_type == 10)
+			READ_AND_CONFIG_MP(8192f, _txpowertrack_type10);
+		else if (dm->rfe_type == 11)
+			READ_AND_CONFIG_MP(8192f, _txpowertrack_type11);
+		else if (dm->rfe_type == 12)
+			READ_AND_CONFIG_MP(8192f, _txpowertrack_type12);
+		else if (dm->rfe_type == 13)
+			READ_AND_CONFIG_MP(8192f, _txpowertrack_type13);
+		else if (dm->rfe_type == 14)
+			READ_AND_CONFIG_MP(8192f, _txpowertrack_type14);
+		else if (dm->rfe_type == 15)
+			READ_AND_CONFIG_MP(8192f, _txpowertrack_type15);
+		else if (dm->rfe_type == 16)
+			READ_AND_CONFIG_MP(8192f, _txpowertrack_type16);
+		else if (dm->rfe_type == 17)
+			READ_AND_CONFIG_MP(8192f, _txpowertrack_type17);
+		else if (dm->rfe_type == 18)
+			READ_AND_CONFIG_MP(8192f, _txpowertrack_type18);
+		else if (dm->rfe_type == 19)
+			READ_AND_CONFIG_MP(8192f, _txpowertrack_type19);
+		else if (dm->rfe_type == 20)
+			READ_AND_CONFIG_MP(8192f, _txpowertrack_type20);
+		else if (dm->rfe_type == 21)
+			READ_AND_CONFIG_MP(8192f, _txpowertrack_type21);
+		else if (dm->rfe_type == 22)
+			READ_AND_CONFIG_MP(8192f, _txpowertrack_type22);
+		else if (dm->rfe_type == 23)
+			READ_AND_CONFIG_MP(8192f, _txpowertrack_type23);
+		else if (dm->rfe_type == 24)
+			READ_AND_CONFIG_MP(8192f, _txpowertrack_type24);
+		else if (dm->rfe_type == 25)
+			READ_AND_CONFIG_MP(8192f, _txpowertrack_type25);
+		else if (dm->rfe_type == 26)
+			READ_AND_CONFIG_MP(8192f, _txpowertrack_type26);
+		else if (dm->rfe_type == 27)
+			READ_AND_CONFIG_MP(8192f, _txpowertrack_type27);
+		else if (dm->rfe_type == 28)
+			READ_AND_CONFIG_MP(8192f, _txpowertrack_type28);
+		else if (dm->rfe_type == 29)
+			READ_AND_CONFIG_MP(8192f, _txpowertrack_type29);
+		else if (dm->rfe_type == 30)
+			READ_AND_CONFIG_MP(8192f, _txpowertrack_type30);
+		else if (dm->rfe_type == 31)
+			READ_AND_CONFIG_MP(8192f, _txpowertrack_type31);
+		else
+			READ_AND_CONFIG_MP(8192f, _txpowertrack);
+
+		READ_AND_CONFIG_MP(8192f, _txxtaltrack);
+	}
+#endif
+#if RTL8821C_SUPPORT
+	if (dm->support_ic_type == ODM_RTL8821C) {
+		if (dm->rfe_type == 0x5)
+			READ_AND_CONFIG(8821c, _txpowertrack_type0x28);
+		else if (dm->rfe_type == 0x4)
+			READ_AND_CONFIG(8821c, _txpowertrack_type0x20);
+		else
+			READ_AND_CONFIG(8821c, _txpowertrack);
+	}
+#endif
+
+#if RTL8198F_SUPPORT
+	if (dm->support_ic_type == ODM_RTL8198F)
+		READ_AND_CONFIG_MP(8198f, _txpowertrack);
+#endif
+
+#if RTL8195B_SUPPORT
+	if (dm->support_ic_type == ODM_RTL8195B) {
+		READ_AND_CONFIG_MP(8195b, _txpowertrack);
+		READ_AND_CONFIG_MP(8195b, _txxtaltrack);
+	}
+#endif
+
+	return HAL_STATUS_SUCCESS;
+}
+
+enum hal_status
+odm_config_bb_with_header_file(struct dm_struct *dm,
+			       enum odm_bb_config_type config_type)
+{
+#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
+	void *adapter = dm->adapter;
+	PMGNT_INFO mgnt_info = &((PADAPTER)adapter)->MgntInfo;
+#endif
+	enum hal_status result = HAL_STATUS_SUCCESS;
+
+/* @1 AP doesn't use PHYDM initialization in these ICs */
+#if (DM_ODM_SUPPORT_TYPE != ODM_AP)
+#if (RTL8812A_SUPPORT == 1)
+	if (dm->support_ic_type == ODM_RTL8812) {
+		if (config_type == CONFIG_BB_PHY_REG)
+			READ_AND_CONFIG_MP(8812a, _phy_reg);
+		else if (config_type == CONFIG_BB_AGC_TAB)
+			READ_AND_CONFIG_MP(8812a, _agc_tab);
+		else if (config_type == CONFIG_BB_PHY_REG_PG) {
+			if (dm->rfe_type == 3 && dm->is_mp_chip)
+				READ_AND_CONFIG_MP(8812a, _phy_reg_pg_asus);
+#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
+			else if (mgnt_info->CustomerID == RT_CID_WNC_NEC && dm->is_mp_chip)
+				READ_AND_CONFIG_MP(8812a, _phy_reg_pg_nec);
+#if RT_PLATFORM == PLATFORM_MACOSX
+			/*@{1827}{1024} for BUFFALO power by rate table. Isaiah 2013-11-29*/
+			else if (mgnt_info->CustomerID == RT_CID_DNI_BUFFALO)
+				READ_AND_CONFIG_MP(8812a, _phy_reg_pg_dni);
+			/* TP-Link T4UH, Isaiah 2015-03-16*/
+			else if (mgnt_info->CustomerID == RT_CID_TPLINK_HPWR) {
+				pr_debug("RT_CID_TPLINK_HPWR:: _PHY_REG_PG_TPLINK\n");
+				READ_AND_CONFIG_MP(8812a, _phy_reg_pg_tplink);
+			}
+#endif
+#endif
+			else
+				READ_AND_CONFIG_MP(8812a, _phy_reg_pg);
+		} else if (config_type == CONFIG_BB_PHY_REG_MP)
+			READ_AND_CONFIG_MP(8812a, _phy_reg_mp);
+		else if (config_type == CONFIG_BB_AGC_TAB_DIFF) {
+			dm->fw_offload_ability &= ~PHYDM_PHY_PARAM_OFFLOAD;
+			/*@AGC_TAB DIFF dont support FW offload*/
+			if ((*dm->channel >= 36) && (*dm->channel <= 64))
+				AGC_DIFF_CONFIG_MP(8812a, lb);
+			else if (*dm->channel >= 100)
+				AGC_DIFF_CONFIG_MP(8812a, hb);
+		}
+	}
+#endif
+#if (RTL8821A_SUPPORT == 1)
+	if (dm->support_ic_type == ODM_RTL8821) {
+		if (config_type == CONFIG_BB_PHY_REG)
+			READ_AND_CONFIG_MP(8821a, _phy_reg);
+		else if (config_type == CONFIG_BB_AGC_TAB)
+			READ_AND_CONFIG_MP(8821a, _agc_tab);
+		else if (config_type == CONFIG_BB_PHY_REG_PG) {
+#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
+#if (DEV_BUS_TYPE == RT_PCI_INTERFACE)
+			HAL_DATA_TYPE * hal_data = GET_HAL_DATA(((PADAPTER)adapter));
+
+			if ((hal_data->EEPROMSVID == 0x1043 && hal_data->EEPROMSMID == 0x207F))
+				READ_AND_CONFIG_MP(8821a, _phy_reg_pg_e202_sa);
+			else
+#endif
+#if (RT_PLATFORM == PLATFORM_MACOSX)
+				/*@  for BUFFALO pwr by rate table */
+				if (mgnt_info->CustomerID == RT_CID_DNI_BUFFALO) {
+				/*@  for BUFFALO pwr by rate table (JP/US)*/
+				if (mgnt_info->ChannelPlan == RT_CHANNEL_DOMAIN_US_2G_CANADA_5G)
+					READ_AND_CONFIG_MP(8821a, _phy_reg_pg_dni_us);
+				else
+					READ_AND_CONFIG_MP(8821a, _phy_reg_pg_dni_jp);
+			} else
+#endif
+#endif
+				READ_AND_CONFIG_MP(8821a, _phy_reg_pg);
+		}
+	}
+#endif
+#if (RTL8192E_SUPPORT == 1)
+	if (dm->support_ic_type == ODM_RTL8192E) {
+		if (config_type == CONFIG_BB_PHY_REG)
+			READ_AND_CONFIG_MP(8192e, _phy_reg);
+		else if (config_type == CONFIG_BB_AGC_TAB)
+			READ_AND_CONFIG_MP(8192e, _agc_tab);
+		else if (config_type == CONFIG_BB_PHY_REG_PG)
+			READ_AND_CONFIG_MP(8192e, _phy_reg_pg);
+	}
+#endif
+#if (RTL8723D_SUPPORT == 1)
+	if (dm->support_ic_type == ODM_RTL8723D) {
+		if (config_type == CONFIG_BB_PHY_REG)
+			READ_AND_CONFIG_MP(8723d, _phy_reg);
+		else if (config_type == CONFIG_BB_AGC_TAB)
+			READ_AND_CONFIG_MP(8723d, _agc_tab);
+		else if (config_type == CONFIG_BB_PHY_REG_PG)
+			READ_AND_CONFIG_MP(8723d, _phy_reg_pg);
+	}
+#endif
+/* @JJ ADD 20161014 */
+#if (RTL8710B_SUPPORT == 1)
+	if (dm->support_ic_type == ODM_RTL8710B) {
+		if (config_type == CONFIG_BB_PHY_REG)
+			READ_AND_CONFIG_MP(8710b, _phy_reg);
+		else if (config_type == CONFIG_BB_AGC_TAB)
+			READ_AND_CONFIG_MP(8710b, _agc_tab);
+		else if (config_type == CONFIG_BB_PHY_REG_PG)
+			READ_AND_CONFIG_MP(8710b, _phy_reg_pg);
+	}
+#endif
+
+#endif /* @(DM_ODM_SUPPORT_TYPE !=  ODM_AP) */
+/* @1 All platforms support */
+#if (RTL8188E_SUPPORT == 1)
+	if (dm->support_ic_type == ODM_RTL8188E) {
+		if (config_type == CONFIG_BB_PHY_REG)
+			READ_AND_CONFIG_MP(8188e, _phy_reg);
+		else if (config_type == CONFIG_BB_AGC_TAB)
+			READ_AND_CONFIG_MP(8188e, _agc_tab);
+		else if (config_type == CONFIG_BB_PHY_REG_PG)
+			READ_AND_CONFIG_MP(8188e, _phy_reg_pg);
+	}
+#endif
+#if (RTL8723B_SUPPORT == 1)
+	if (dm->support_ic_type == ODM_RTL8723B) {
+		if (config_type == CONFIG_BB_PHY_REG)
+			READ_AND_CONFIG_MP(8723b, _phy_reg);
+		else if (config_type == CONFIG_BB_AGC_TAB)
+			READ_AND_CONFIG_MP(8723b, _agc_tab);
+		else if (config_type == CONFIG_BB_PHY_REG_PG)
+			READ_AND_CONFIG_MP(8723b, _phy_reg_pg);
+	}
+#endif
+#if (RTL8814A_SUPPORT == 1)
+	if (dm->support_ic_type == ODM_RTL8814A) {
+		if (config_type == CONFIG_BB_PHY_REG)
+			READ_AND_CONFIG_MP(8814a, _phy_reg);
+		else if (config_type == CONFIG_BB_AGC_TAB)
+			READ_AND_CONFIG_MP(8814a, _agc_tab);
+		else if (config_type == CONFIG_BB_PHY_REG_PG) {
+			if (dm->rfe_type == 0)
+				READ_AND_CONFIG_MP(8814a, _phy_reg_pg_type0);
+			else if (dm->rfe_type == 2)
+				READ_AND_CONFIG_MP(8814a, _phy_reg_pg_type2);
+			else if (dm->rfe_type == 3)
+				READ_AND_CONFIG_MP(8814a, _phy_reg_pg_type3);
+			else if (dm->rfe_type == 4)
+				READ_AND_CONFIG_MP(8814a, _phy_reg_pg_type4);
+			else if (dm->rfe_type == 5)
+				READ_AND_CONFIG_MP(8814a, _phy_reg_pg_type5);
+			else if (dm->rfe_type == 7)
+				READ_AND_CONFIG_MP(8814a, _phy_reg_pg_type7);
+			else if (dm->rfe_type == 8)
+				READ_AND_CONFIG_MP(8814a, _phy_reg_pg_type8);
+			else
+				READ_AND_CONFIG_MP(8814a, _phy_reg_pg);
+		} else if (config_type == CONFIG_BB_PHY_REG_MP)
+			READ_AND_CONFIG_MP(8814a, _phy_reg_mp);
+	}
+#endif
+#if (RTL8703B_SUPPORT == 1)
+	if (dm->support_ic_type == ODM_RTL8703B) {
+		if (config_type == CONFIG_BB_PHY_REG)
+			READ_AND_CONFIG_MP(8703b, _phy_reg);
+		else if (config_type == CONFIG_BB_AGC_TAB)
+			READ_AND_CONFIG_MP(8703b, _agc_tab);
+		else if (config_type == CONFIG_BB_PHY_REG_PG)
+			READ_AND_CONFIG_MP(8703b, _phy_reg_pg);
+	}
+#endif
+#if (RTL8188F_SUPPORT == 1)
+	if (dm->support_ic_type == ODM_RTL8188F) {
+		if (config_type == CONFIG_BB_PHY_REG)
+			READ_AND_CONFIG_MP(8188f, _phy_reg);
+		else if (config_type == CONFIG_BB_AGC_TAB)
+			READ_AND_CONFIG_MP(8188f, _agc_tab);
+		else if (config_type == CONFIG_BB_PHY_REG_PG)
+			READ_AND_CONFIG_MP(8188f, _phy_reg_pg);
+	}
+#endif
+#if (RTL8822B_SUPPORT == 1)
+	if (dm->support_ic_type == ODM_RTL8822B) {
+		if (config_type == CONFIG_BB_PHY_REG) {
+			READ_AND_CONFIG_MP(8822b, _phy_reg);
+		} else if (config_type == CONFIG_BB_AGC_TAB) {
+			READ_AND_CONFIG_MP(8822b, _agc_tab);
+		} else if (config_type == CONFIG_BB_PHY_REG_PG) {
+			if (dm->rfe_type == 2)
+				READ_AND_CONFIG_MP(8822b, _phy_reg_pg_type2);
+			else if (dm->rfe_type == 3)
+				READ_AND_CONFIG_MP(8822b, _phy_reg_pg_type3);
+			else if (dm->rfe_type == 4)
+				READ_AND_CONFIG_MP(8822b, _phy_reg_pg_type4);
+			else if (dm->rfe_type == 5)
+				READ_AND_CONFIG_MP(8822b, _phy_reg_pg_type5);
+			else if (dm->rfe_type == 12)
+				READ_AND_CONFIG_MP(8822b, _phy_reg_pg_type12);
+			else if (dm->rfe_type == 15)
+				READ_AND_CONFIG_MP(8822b, _phy_reg_pg_type15);
+			else if (dm->rfe_type == 16)
+				READ_AND_CONFIG_MP(8822b, _phy_reg_pg_type16);
+			else if (dm->rfe_type == 17)
+				READ_AND_CONFIG_MP(8822b, _phy_reg_pg_type17);
+			else if (dm->rfe_type == 18)
+				READ_AND_CONFIG_MP(8822b, _phy_reg_pg_type18);
+			else
+				READ_AND_CONFIG_MP(8822b, _phy_reg_pg);
+		}
+	}
+#endif
+
+#if (RTL8197F_SUPPORT == 1)
+	if (dm->support_ic_type == ODM_RTL8197F) {
+		if (config_type == CONFIG_BB_PHY_REG) {
+			READ_AND_CONFIG_MP(8197f, _phy_reg);
+			if (dm->cut_version == ODM_CUT_A)
+				phydm_phypara_a_cut(dm);
+		} else if (config_type == CONFIG_BB_AGC_TAB)
+			READ_AND_CONFIG_MP(8197f, _agc_tab);
+	}
+#endif
+/*@jj add 20170822*/
+#if (RTL8192F_SUPPORT == 1)
+	if (dm->support_ic_type == ODM_RTL8192F) {
+		if (config_type == CONFIG_BB_PHY_REG) {
+			READ_AND_CONFIG_MP(8192f, _phy_reg);
+		} else if (config_type == CONFIG_BB_AGC_TAB) {
+			READ_AND_CONFIG_MP(8192f, _agc_tab);
+		} else if (config_type == CONFIG_BB_PHY_REG_PG) {
+			if (dm->rfe_type == 0)
+				READ_AND_CONFIG_MP(8192f, _phy_reg_pg_type0);
+			else if (dm->rfe_type == 1)
+				READ_AND_CONFIG_MP(8192f, _phy_reg_pg_type1);
+			else if (dm->rfe_type == 2)
+				READ_AND_CONFIG_MP(8192f, _phy_reg_pg_type2);
+			else if (dm->rfe_type == 3)
+				READ_AND_CONFIG_MP(8192f, _phy_reg_pg_type3);
+			else if (dm->rfe_type == 4)
+				READ_AND_CONFIG_MP(8192f, _phy_reg_pg_type4);
+			else if (dm->rfe_type == 5)
+				READ_AND_CONFIG_MP(8192f, _phy_reg_pg_type5);
+			else if (dm->rfe_type == 6)
+				READ_AND_CONFIG_MP(8192f, _phy_reg_pg_type6);
+			else if (dm->rfe_type == 7)
+				READ_AND_CONFIG_MP(8192f, _phy_reg_pg_type7);
+			else if (dm->rfe_type == 8)
+				READ_AND_CONFIG_MP(8192f, _phy_reg_pg_type8);
+			else if (dm->rfe_type == 9)
+				READ_AND_CONFIG_MP(8192f, _phy_reg_pg_type9);
+			else if (dm->rfe_type == 10)
+				READ_AND_CONFIG_MP(8192f, _phy_reg_pg_type10);
+			else if (dm->rfe_type == 11)
+				READ_AND_CONFIG_MP(8192f, _phy_reg_pg_type11);
+			else if (dm->rfe_type == 12)
+				READ_AND_CONFIG_MP(8192f, _phy_reg_pg_type12);
+			else if (dm->rfe_type == 13)
+				READ_AND_CONFIG_MP(8192f, _phy_reg_pg_type13);
+			else if (dm->rfe_type == 14)
+				READ_AND_CONFIG_MP(8192f, _phy_reg_pg_type14);
+			else if (dm->rfe_type == 15)
+				READ_AND_CONFIG_MP(8192f, _phy_reg_pg_type15);
+			else if (dm->rfe_type == 16)
+				READ_AND_CONFIG_MP(8192f, _phy_reg_pg_type16);
+			else if (dm->rfe_type == 17)
+				READ_AND_CONFIG_MP(8192f, _phy_reg_pg_type17);
+			else if (dm->rfe_type == 18)
+				READ_AND_CONFIG_MP(8192f, _phy_reg_pg_type18);
+			else if (dm->rfe_type == 19)
+				READ_AND_CONFIG_MP(8192f, _phy_reg_pg_type19);
+			else if (dm->rfe_type == 20)
+				READ_AND_CONFIG_MP(8192f, _phy_reg_pg_type20);
+			else if (dm->rfe_type == 21)
+				READ_AND_CONFIG_MP(8192f, _phy_reg_pg_type21);
+			else if (dm->rfe_type == 22)
+				READ_AND_CONFIG_MP(8192f, _phy_reg_pg_type22);
+			else if (dm->rfe_type == 23)
+				READ_AND_CONFIG_MP(8192f, _phy_reg_pg_type23);
+			else if (dm->rfe_type == 24)
+				READ_AND_CONFIG_MP(8192f, _phy_reg_pg_type24);
+			else if (dm->rfe_type == 25)
+				READ_AND_CONFIG_MP(8192f, _phy_reg_pg_type25);
+			else if (dm->rfe_type == 26)
+				READ_AND_CONFIG_MP(8192f, _phy_reg_pg_type26);
+			else if (dm->rfe_type == 27)
+				READ_AND_CONFIG_MP(8192f, _phy_reg_pg_type27);
+			else if (dm->rfe_type == 28)
+				READ_AND_CONFIG_MP(8192f, _phy_reg_pg_type28);
+			else if (dm->rfe_type == 29)
+				READ_AND_CONFIG_MP(8192f, _phy_reg_pg_type29);
+			else if (dm->rfe_type == 30)
+				READ_AND_CONFIG_MP(8192f, _phy_reg_pg_type30);
+			else if (dm->rfe_type == 31)
+				READ_AND_CONFIG_MP(8192f, _phy_reg_pg_type31);
+			else
+				READ_AND_CONFIG_MP(8192f, _phy_reg_pg);
+		}
+	}
+#endif
+#if (RTL8821C_SUPPORT == 1)
+	if (dm->support_ic_type == ODM_RTL8821C) {
+		if (config_type == CONFIG_BB_PHY_REG) {
+			READ_AND_CONFIG(8821c, _phy_reg);
+		} else if (config_type == CONFIG_BB_AGC_TAB) {
+			READ_AND_CONFIG(8821c, _agc_tab);
+			/* @According to RFEtype, choosing correct AGC table*/
+			if (dm->default_rf_set_8821c == SWITCH_TO_BTG)
+				AGC_DIFF_CONFIG_MP(8821c, btg);
+		} else if (config_type == CONFIG_BB_PHY_REG_PG) {
+			if (dm->rfe_type == 0x5)
+				READ_AND_CONFIG(8821c, _phy_reg_pg_type0x28);
+			else
+				READ_AND_CONFIG(8821c, _phy_reg_pg);
+		} else if (config_type == CONFIG_BB_AGC_TAB_DIFF) {
+			dm->fw_offload_ability &= ~PHYDM_PHY_PARAM_OFFLOAD;
+			/*@AGC_TAB DIFF dont support FW offload*/
+			if (dm->current_rf_set_8821c == SWITCH_TO_BTG)
+				AGC_DIFF_CONFIG_MP(8821c, btg);
+			else if (dm->current_rf_set_8821c == SWITCH_TO_WLG)
+				AGC_DIFF_CONFIG_MP(8821c, wlg);
+		} else if (config_type == CONFIG_BB_PHY_REG_MP) {
+			READ_AND_CONFIG(8821c, _phy_reg_mp);
+		}
+	}
+#endif
+
+#if (RTL8195A_SUPPORT == 1)
+	if (dm->support_ic_type == ODM_RTL8195A) {
+		if (config_type == CONFIG_BB_PHY_REG)
+			READ_AND_CONFIG(8195a, _phy_reg);
+		else if (config_type == CONFIG_BB_AGC_TAB)
+			READ_AND_CONFIG(8195a, _agc_tab);
+		else if (config_type == CONFIG_BB_PHY_REG_PG)
+			READ_AND_CONFIG(8195a, _phy_reg_pg);
+	}
+#endif
+#if (RTL8195B_SUPPORT == 1)
+	if (dm->support_ic_type == ODM_RTL8195B) {
+		if (config_type == CONFIG_BB_PHY_REG)
+			READ_AND_CONFIG(8195b, _phy_reg);
+		else if (config_type == CONFIG_BB_AGC_TAB)
+			READ_AND_CONFIG(8195b, _agc_tab);
+		/*@else if (config_type == CONFIG_BB_PHY_REG_PG)*/
+		/*	READ_AND_CONFIG(8195b, _phy_reg_pg);*/
+	}
+#endif
+#if (RTL8198F_SUPPORT == 1)
+	if (dm->support_ic_type == ODM_RTL8198F) {
+		if (config_type == CONFIG_BB_PHY_REG)
+			READ_AND_CONFIG_MP(8198f, _phy_reg);
+		else if (config_type == CONFIG_BB_AGC_TAB)
+			READ_AND_CONFIG_MP(8198f, _agc_tab);
+	}
+#endif
+
+	if (config_type == CONFIG_BB_PHY_REG ||
+	    config_type == CONFIG_BB_AGC_TAB)
+		if (dm->fw_offload_ability & PHYDM_PHY_PARAM_OFFLOAD) {
+			result = phydm_set_reg_by_fw(dm,
+						     PHYDM_HALMAC_CMD_END,
+						     0,
+						     0,
+						     0,
+						     (enum rf_path)0,
+						     0);
+			PHYDM_DBG(dm, ODM_COMP_INIT,
+				  "phy param offload end!result = %d", result);
+		}
+
+	return result;
+}
+
+enum hal_status
+odm_config_mac_with_header_file(struct dm_struct *dm)
+{
+	enum hal_status result = HAL_STATUS_SUCCESS;
+
+	PHYDM_DBG(dm, ODM_COMP_INIT, "===>%s (%s)\n", __func__,
+		  (dm->is_mp_chip) ? "MPChip" : "TestChip");
+	PHYDM_DBG(dm, ODM_COMP_INIT,
+		  "support_platform: 0x%X, support_interface: 0x%X, board_type: 0x%X\n",
+		  dm->support_platform, dm->support_interface, dm->board_type);
+
+/* @1 AP doesn't use PHYDM initialization in these ICs */
+#if (DM_ODM_SUPPORT_TYPE != ODM_AP)
+#if (RTL8812A_SUPPORT == 1)
+	if (dm->support_ic_type == ODM_RTL8812)
+		READ_AND_CONFIG_MP(8812a, _mac_reg);
+#endif
+#if (RTL8821A_SUPPORT == 1)
+	if (dm->support_ic_type == ODM_RTL8821)
+		READ_AND_CONFIG_MP(8821a, _mac_reg);
+#endif
+#if (RTL8192E_SUPPORT == 1)
+	if (dm->support_ic_type == ODM_RTL8192E)
+		READ_AND_CONFIG_MP(8192e, _mac_reg);
+#endif
+#if (RTL8723D_SUPPORT == 1)
+	if (dm->support_ic_type == ODM_RTL8723D)
+		READ_AND_CONFIG_MP(8723d, _mac_reg);
+#endif
+/* @JJ ADD 20161014 */
+#if (RTL8710B_SUPPORT == 1)
+	if (dm->support_ic_type == ODM_RTL8710B)
+		READ_AND_CONFIG_MP(8710b, _mac_reg);
+#endif
+#endif /* @(DM_ODM_SUPPORT_TYPE !=  ODM_AP) */
+/* @1 All platforms support */
+#if (RTL8188E_SUPPORT == 1)
+	if (dm->support_ic_type == ODM_RTL8188E)
+		READ_AND_CONFIG_MP(8188e, _mac_reg);
+#endif
+#if (RTL8723B_SUPPORT == 1)
+	if (dm->support_ic_type == ODM_RTL8723B)
+		READ_AND_CONFIG_MP(8723b, _mac_reg);
+#endif
+#if (RTL8814A_SUPPORT == 1)
+	if (dm->support_ic_type == ODM_RTL8814A)
+		READ_AND_CONFIG_MP(8814a, _mac_reg);
+#endif
+#if (RTL8703B_SUPPORT == 1)
+	if (dm->support_ic_type == ODM_RTL8703B)
+		READ_AND_CONFIG_MP(8703b, _mac_reg);
+#endif
+#if (RTL8188F_SUPPORT == 1)
+	if (dm->support_ic_type == ODM_RTL8188F)
+		READ_AND_CONFIG_MP(8188f, _mac_reg);
+#endif
+#if (RTL8822B_SUPPORT == 1)
+	if (dm->support_ic_type == ODM_RTL8822B)
+		READ_AND_CONFIG_MP(8822b, _mac_reg);
+#endif
+#if (RTL8197F_SUPPORT == 1)
+	if (dm->support_ic_type == ODM_RTL8197F)
+		READ_AND_CONFIG_MP(8197f, _mac_reg);
+#endif
+
+/*@jj add 20170822*/
+#if (RTL8192F_SUPPORT == 1)
+	if (dm->support_ic_type == ODM_RTL8192F)
+		READ_AND_CONFIG_MP(8192f, _mac_reg);
+#endif
+#if (RTL8821C_SUPPORT == 1)
+	if (dm->support_ic_type == ODM_RTL8821C)
+		READ_AND_CONFIG(8821c, _mac_reg);
+#endif
+#if (RTL8195A_SUPPORT == 1)
+	if (dm->support_ic_type == ODM_RTL8195A)
+		READ_AND_CONFIG_MP(8195a, _mac_reg);
+#endif
+#if (RTL8195B_SUPPORT == 1)
+	if (dm->support_ic_type == ODM_RTL8195B)
+		READ_AND_CONFIG_MP(8195b, _mac_reg);
+#endif
+#if (RTL8198F_SUPPORT == 1)
+	if (dm->support_ic_type == ODM_RTL8198F)
+		READ_AND_CONFIG_MP(8198f, _mac_reg);
+#endif
+
+	if (dm->fw_offload_ability & PHYDM_PHY_PARAM_OFFLOAD) {
+		result = phydm_set_reg_by_fw(dm,
+					     PHYDM_HALMAC_CMD_END,
+					     0,
+					     0,
+					     0,
+					     (enum rf_path)0,
+					     0);
+		PHYDM_DBG(dm, ODM_COMP_INIT,
+			  "mac param offload end!result = %d", result);
+	}
+
+	return result;
+}
+
+u32 odm_get_hw_img_version(struct dm_struct *dm)
+{
+	u32 version = 0;
+
+/* @1 AP doesn't use PHYDM initialization in these ICs */
+#if (DM_ODM_SUPPORT_TYPE != ODM_AP)
+#if (RTL8821A_SUPPORT == 1)
+	if (dm->support_ic_type == ODM_RTL8821)
+		version = GET_VERSION_MP(8821a, _mac_reg);
+#endif
+#if (RTL8192E_SUPPORT == 1)
+	if (dm->support_ic_type == ODM_RTL8192E)
+		version = GET_VERSION_MP(8192e, _mac_reg);
+#endif
+#if (RTL8812A_SUPPORT == 1)
+	if (dm->support_ic_type == ODM_RTL8812)
+		version = GET_VERSION_MP(8812a, _mac_reg);
+#endif
+#if (RTL8723D_SUPPORT == 1)
+	if (dm->support_ic_type == ODM_RTL8723D)
+		version = GET_VERSION_MP(8723d, _mac_reg);
+#endif
+/* @JJ ADD 20161014 */
+#if (RTL8710B_SUPPORT == 1)
+	if (dm->support_ic_type == ODM_RTL8710B)
+		version = GET_VERSION_MP(8710b, _mac_reg);
+#endif
+#endif /* @(DM_ODM_SUPPORT_TYPE != ODM_AP) */
+
+/*@1 All platforms support*/
+#if (RTL8188E_SUPPORT == 1)
+	if (dm->support_ic_type == ODM_RTL8188E)
+		version = GET_VERSION_MP(8188e, _mac_reg);
+#endif
+#if (RTL8723B_SUPPORT == 1)
+	if (dm->support_ic_type == ODM_RTL8723B)
+		version = GET_VERSION_MP(8723b, _mac_reg);
+#endif
+#if (RTL8814A_SUPPORT == 1)
+	if (dm->support_ic_type == ODM_RTL8814A)
+		version = GET_VERSION_MP(8814a, _mac_reg);
+#endif
+#if (RTL8703B_SUPPORT == 1)
+	if (dm->support_ic_type == ODM_RTL8703B)
+		version = GET_VERSION_MP(8703b, _mac_reg);
+#endif
+#if (RTL8188F_SUPPORT == 1)
+	if (dm->support_ic_type == ODM_RTL8188F)
+		version = GET_VERSION_MP(8188f, _mac_reg);
+#endif
+#if (RTL8822B_SUPPORT == 1)
+	if (dm->support_ic_type == ODM_RTL8822B)
+		version = GET_VERSION_MP(8822b, _mac_reg);
+#endif
+#if (RTL8197F_SUPPORT == 1)
+	if (dm->support_ic_type == ODM_RTL8197F)
+		version = GET_VERSION_MP(8197f, _mac_reg);
+#endif
+
+/*@jj add 20170822*/
+#if (RTL8192F_SUPPORT == 1)
+	if (dm->support_ic_type == ODM_RTL8192F)
+		version = GET_VERSION_MP(8192f, _mac_reg);
+#endif
+#if (RTL8821C_SUPPORT == 1)
+	if (dm->support_ic_type == ODM_RTL8821C)
+		version = GET_VERSION(8821c, _mac_reg);
+#endif
+#if (RTL8195B_SUPPORT == 1)
+	if (dm->support_ic_type == ODM_RTL8195B)
+		version = GET_VERSION(8195b, _mac_reg);
+#endif
+#if (RTL8198F_SUPPORT == 1)
+	if (dm->support_ic_type == ODM_RTL8198F)
+		version = GET_VERSION_MP(8198f, _mac_reg);
+#endif
+
+	return version;
+}
+
+u32 query_phydm_trx_capability(struct dm_struct *dm)
+{
+	u32 value32 = 0xFFFFFFFF;
+
+#if (RTL8821C_SUPPORT == 1)
+	if (dm->support_ic_type == ODM_RTL8821C)
+		value32 = query_phydm_trx_capability_8821c(dm);
+#endif
+#if (RTL8195B_SUPPORT == 1)
+	if (dm->support_ic_type == ODM_RTL8195B)
+		value32 = query_phydm_trx_capability_8195b(dm);
+#endif
+	return value32;
+}
+
+u32 query_phydm_stbc_capability(struct dm_struct *dm)
+{
+	u32 value32 = 0xFFFFFFFF;
+
+#if (RTL8821C_SUPPORT == 1)
+	if (dm->support_ic_type == ODM_RTL8821C)
+		value32 = query_phydm_stbc_capability_8821c(dm);
+#endif
+#if (RTL8195B_SUPPORT == 1)
+	if (dm->support_ic_type == ODM_RTL8195B)
+		value32 = query_phydm_stbc_capability_8195b(dm);
+#endif
+
+	return value32;
+}
+
+u32 query_phydm_ldpc_capability(struct dm_struct *dm)
+{
+	u32 value32 = 0xFFFFFFFF;
+
+#if (RTL8821C_SUPPORT == 1)
+	if (dm->support_ic_type == ODM_RTL8821C)
+		value32 = query_phydm_ldpc_capability_8821c(dm);
+#endif
+#if (RTL8195B_SUPPORT == 1)
+	if (dm->support_ic_type == ODM_RTL8195B)
+		value32 = query_phydm_ldpc_capability_8195b(dm);
+#endif
+	return value32;
+}
+
+u32 query_phydm_txbf_parameters(struct dm_struct *dm)
+{
+	u32 value32 = 0xFFFFFFFF;
+
+#if (RTL8821C_SUPPORT == 1)
+	if (dm->support_ic_type == ODM_RTL8821C)
+		value32 = query_phydm_txbf_parameters_8821c(dm);
+#endif
+#if (RTL8195B_SUPPORT == 1)
+	if (dm->support_ic_type == ODM_RTL8195B)
+		value32 = query_phydm_txbf_parameters_8195b(dm);
+#endif
+	return value32;
+}
+
+u32 query_phydm_txbf_capability(struct dm_struct *dm)
+{
+	u32 value32 = 0xFFFFFFFF;
+
+#if (RTL8821C_SUPPORT == 1)
+	if (dm->support_ic_type == ODM_RTL8821C)
+		value32 = query_phydm_txbf_capability_8821c(dm);
+#endif
+#if (RTL8195B_SUPPORT == 1)
+	if (dm->support_ic_type == ODM_RTL8195B)
+		value32 = query_phydm_txbf_capability_8195b(dm);
+#endif
+	return value32;
+}
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/phydm_hwconfig.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/phydm_hwconfig.h
--- linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/phydm_hwconfig.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/phydm_hwconfig.h	2020-04-10 16:35:06.825660488 +0300
@@ -0,0 +1,79 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017  Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * The full GNU General Public License is included in this distribution in the
+ * file called LICENSE.
+ *
+ * Contact Information:
+ * wlanfae <wlanfae@realtek.com>
+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
+ * Hsinchu 300, Taiwan.
+ *
+ * Larry Finger <Larry.Finger@lwfinger.net>
+ *
+ *****************************************************************************/
+
+#ifndef __HALHWOUTSRC_H__
+#define __HALHWOUTSRC_H__
+
+/*@--------------------------Define -------------------------------------------*/
+#define AGC_DIFF_CONFIG_MP(ic, band)				\
+	(odm_read_and_config_mp_##ic##_agc_tab_diff(dm,		\
+	array_mp_##ic##_agc_tab_diff_##band,			\
+	sizeof(array_mp_##ic##_agc_tab_diff_##band) / sizeof(u32)))
+#define AGC_DIFF_CONFIG_TC(ic, band)				\
+	(odm_read_and_config_tc_##ic##_agc_tab_diff(dm,		\
+	array_tc_##ic##_agc_tab_diff_##band,			\
+	sizeof(array_tc_##ic##_agc_tab_diff_##band) / sizeof(u32)))
+#if defined(DM_ODM_CE_MAC80211)
+#else
+#define AGC_DIFF_CONFIG(ic, band)                     \
+	do {                                          \
+		if (dm->is_mp_chip)                   \
+			AGC_DIFF_CONFIG_MP(ic, band); \
+		else                                  \
+			AGC_DIFF_CONFIG_TC(ic, band); \
+	} while (0)
+#endif
+/*@************************************************************
+ * structure and define
+ ************************************************************/
+
+enum hal_status
+odm_config_rf_with_tx_pwr_track_header_file(struct dm_struct *dm);
+
+enum hal_status
+odm_config_rf_with_header_file(struct dm_struct *dm,
+			       enum odm_rf_config_type config_type,
+			       u8 e_rf_path);
+
+enum hal_status
+odm_config_bb_with_header_file(struct dm_struct *dm,
+			       enum odm_bb_config_type config_type);
+
+enum hal_status
+odm_config_mac_with_header_file(struct dm_struct *dm);
+
+u32 odm_get_hw_img_version(struct dm_struct *dm);
+
+u32 query_phydm_trx_capability(struct dm_struct *dm);
+
+u32 query_phydm_stbc_capability(struct dm_struct *dm);
+
+u32 query_phydm_ldpc_capability(struct dm_struct *dm);
+
+u32 query_phydm_txbf_parameters(struct dm_struct *dm);
+
+u32 query_phydm_txbf_capability(struct dm_struct *dm);
+
+#endif /*@#ifndef	__HALHWOUTSRC_H__*/
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/phydm_interface.c linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/phydm_interface.c
--- linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/phydm_interface.c	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/phydm_interface.c	2020-04-10 16:35:06.825660488 +0300
@@ -0,0 +1,1425 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017  Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * The full GNU General Public License is included in this distribution in the
+ * file called LICENSE.
+ *
+ * Contact Information:
+ * wlanfae <wlanfae@realtek.com>
+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
+ * Hsinchu 300, Taiwan.
+ *
+ * Larry Finger <Larry.Finger@lwfinger.net>
+ *
+ *****************************************************************************/
+
+/*@************************************************************
+ * include files
+ ************************************************************/
+
+#include "mp_precomp.h"
+#include "phydm_precomp.h"
+
+/*@
+ * ODM IO Relative API.
+ */
+
+u8 odm_read_1byte(struct dm_struct *dm, u32 reg_addr)
+{
+#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
+	struct rtl8192cd_priv *priv = dm->priv;
+	return RTL_R8(reg_addr);
+#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211)
+	struct rtl_priv *rtlpriv = (struct rtl_priv *)dm->adapter;
+
+	return rtl_read_byte(rtlpriv, reg_addr);
+#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211_V2)
+	struct rtw_dev *rtwdev = dm->adapter;
+
+	return rtw_read8(rtwdev, reg_addr);
+#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
+	void *adapter = dm->adapter;
+	return rtw_read8(adapter, reg_addr);
+#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)
+	void *adapter = dm->adapter;
+	return PlatformEFIORead1Byte(adapter, reg_addr);
+#elif (DM_ODM_SUPPORT_TYPE & ODM_IOT)
+	void *adapter = dm->adapter;
+
+	return rtw_read8(adapter, reg_addr);
+#endif
+}
+
+u16 odm_read_2byte(struct dm_struct *dm, u32 reg_addr)
+{
+#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
+	struct rtl8192cd_priv *priv = dm->priv;
+	return RTL_R16(reg_addr);
+#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211)
+	struct rtl_priv *rtlpriv = (struct rtl_priv *)dm->adapter;
+
+	return rtl_read_word(rtlpriv, reg_addr);
+#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211_V2)
+	struct rtw_dev *rtwdev = dm->adapter;
+
+	return rtw_read16(rtwdev, reg_addr);
+#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
+	void *adapter = dm->adapter;
+	return rtw_read16(adapter, reg_addr);
+#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)
+	void *adapter = dm->adapter;
+	return PlatformEFIORead2Byte(adapter, reg_addr);
+#elif (DM_ODM_SUPPORT_TYPE & ODM_IOT)
+	void *adapter = dm->adapter;
+
+	return rtw_read16(adapter, reg_addr);
+#endif
+}
+
+u32 odm_read_4byte(struct dm_struct *dm, u32 reg_addr)
+{
+#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
+	struct rtl8192cd_priv *priv = dm->priv;
+	return RTL_R32(reg_addr);
+#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211)
+	struct rtl_priv *rtlpriv = (struct rtl_priv *)dm->adapter;
+
+	return rtl_read_dword(rtlpriv, reg_addr);
+#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211_V2)
+	struct rtw_dev *rtwdev = dm->adapter;
+
+	return rtw_read32(rtwdev, reg_addr);
+#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
+	void *adapter = dm->adapter;
+	return rtw_read32(adapter, reg_addr);
+#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)
+	void *adapter = dm->adapter;
+	return PlatformEFIORead4Byte(adapter, reg_addr);
+#elif (DM_ODM_SUPPORT_TYPE & ODM_IOT)
+	void *adapter = dm->adapter;
+
+	return rtw_read32(adapter, reg_addr);
+#endif
+}
+
+void odm_write_1byte(struct dm_struct *dm, u32 reg_addr, u8 data)
+{
+#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
+	struct rtl8192cd_priv *priv = dm->priv;
+	RTL_W8(reg_addr, data);
+#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211)
+	struct rtl_priv *rtlpriv = (struct rtl_priv *)dm->adapter;
+
+	rtl_write_byte(rtlpriv, reg_addr, data);
+#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211_V2)
+	struct rtw_dev *rtwdev = dm->adapter;
+
+	rtw_write8(rtwdev, reg_addr, data);
+#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
+	void *adapter = dm->adapter;
+	rtw_write8(adapter, reg_addr, data);
+#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)
+	void *adapter = dm->adapter;
+	PlatformEFIOWrite1Byte(adapter, reg_addr, data);
+#elif (DM_ODM_SUPPORT_TYPE & ODM_IOT)
+	void *adapter = dm->adapter;
+
+	rtw_write8(adapter, reg_addr, data);
+#endif
+}
+
+void odm_write_2byte(struct dm_struct *dm, u32 reg_addr, u16 data)
+{
+#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
+	struct rtl8192cd_priv *priv = dm->priv;
+	RTL_W16(reg_addr, data);
+#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211)
+	struct rtl_priv *rtlpriv = (struct rtl_priv *)dm->adapter;
+
+	rtl_write_word(rtlpriv, reg_addr, data);
+#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211_V2)
+	struct rtw_dev *rtwdev = dm->adapter;
+
+	rtw_write16(rtwdev, reg_addr, data);
+#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
+	void *adapter = dm->adapter;
+	rtw_write16(adapter, reg_addr, data);
+#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)
+	void *adapter = dm->adapter;
+	PlatformEFIOWrite2Byte(adapter, reg_addr, data);
+#elif (DM_ODM_SUPPORT_TYPE & ODM_IOT)
+	void *adapter = dm->adapter;
+
+	rtw_write16(adapter, reg_addr, data);
+#endif
+}
+
+void odm_write_4byte(struct dm_struct *dm, u32 reg_addr, u32 data)
+{
+#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
+	struct rtl8192cd_priv *priv = dm->priv;
+	RTL_W32(reg_addr, data);
+#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211)
+	struct rtl_priv *rtlpriv = (struct rtl_priv *)dm->adapter;
+
+	rtl_write_dword(rtlpriv, reg_addr, data);
+#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211_V2)
+	struct rtw_dev *rtwdev = dm->adapter;
+
+	rtw_write32(rtwdev, reg_addr, data);
+#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
+	void *adapter = dm->adapter;
+	rtw_write32(adapter, reg_addr, data);
+#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)
+	void *adapter = dm->adapter;
+	PlatformEFIOWrite4Byte(adapter, reg_addr, data);
+#elif (DM_ODM_SUPPORT_TYPE & ODM_IOT)
+	void *adapter = dm->adapter;
+
+	rtw_write32(adapter, reg_addr, data);
+#endif
+}
+
+void odm_set_mac_reg(struct dm_struct *dm, u32 reg_addr, u32 bit_mask, u32 data)
+{
+#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
+	phy_set_bb_reg(dm->priv, reg_addr, bit_mask, data);
+#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)
+	void *adapter = dm->adapter;
+	PHY_SetBBReg(adapter, reg_addr, bit_mask, data);
+#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211)
+	struct rtl_priv *rtlpriv = (struct rtl_priv *)dm->adapter;
+
+	rtl_set_bbreg(rtlpriv->hw, reg_addr, bit_mask, data);
+#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211_V2)
+	struct rtw_dev *rtwdev = dm->adapter;
+
+	rtw_set_reg_with_mask(rtwdev, reg_addr, bit_mask, data);
+#elif (DM_ODM_SUPPORT_TYPE & ODM_IOT)
+	phy_set_bb_reg(dm->adapter, reg_addr, bit_mask, data);
+#else
+	phy_set_bb_reg(dm->adapter, reg_addr, bit_mask, data);
+#endif
+}
+
+u32 odm_get_mac_reg(struct dm_struct *dm, u32 reg_addr, u32 bit_mask)
+{
+#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
+	return phy_query_bb_reg(dm->priv, reg_addr, bit_mask);
+#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)
+	return PHY_QueryMacReg(dm->adapter, reg_addr, bit_mask);
+#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211)
+	struct rtl_priv *rtlpriv = (struct rtl_priv *)dm->adapter;
+
+	return rtl_get_bbreg(rtlpriv->hw, reg_addr, bit_mask);
+#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211_V2)
+	struct rtw_dev *rtwdev = dm->adapter;
+
+	return rtw_get_reg_with_mask(rtwdev, reg_addr, bit_mask);
+#elif (DM_ODM_SUPPORT_TYPE & ODM_IOT)
+	return phy_query_bb_reg(dm->adapter, reg_addr, bit_mask);
+#else
+	return phy_query_mac_reg(dm->adapter, reg_addr, bit_mask);
+#endif
+}
+
+void odm_set_bb_reg(struct dm_struct *dm, u32 reg_addr, u32 bit_mask, u32 data)
+{
+#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
+	phy_set_bb_reg(dm->priv, reg_addr, bit_mask, data);
+#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)
+	void *adapter = dm->adapter;
+	PHY_SetBBReg(adapter, reg_addr, bit_mask, data);
+#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211)
+	struct rtl_priv *rtlpriv = (struct rtl_priv *)dm->adapter;
+
+	rtl_set_bbreg(rtlpriv->hw, reg_addr, bit_mask, data);
+#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211_V2)
+	struct rtw_dev *rtwdev = dm->adapter;
+
+	rtw_set_reg_with_mask(rtwdev, reg_addr, bit_mask, data);
+#elif (DM_ODM_SUPPORT_TYPE & ODM_IOT)
+	phy_set_bb_reg(dm->adapter, reg_addr, bit_mask, data);
+#else
+	phy_set_bb_reg(dm->adapter, reg_addr, bit_mask, data);
+#endif
+}
+
+u32 odm_get_bb_reg(struct dm_struct *dm, u32 reg_addr, u32 bit_mask)
+{
+#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
+	return phy_query_bb_reg(dm->priv, reg_addr, bit_mask);
+#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)
+	void *adapter = dm->adapter;
+	return PHY_QueryBBReg(adapter, reg_addr, bit_mask);
+#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211)
+	struct rtl_priv *rtlpriv = (struct rtl_priv *)dm->adapter;
+
+	return rtl_get_bbreg(rtlpriv->hw, reg_addr, bit_mask);
+#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211_V2)
+	struct rtw_dev *rtwdev = dm->adapter;
+
+	return rtw_get_reg_with_mask(rtwdev, reg_addr, bit_mask);
+#elif (DM_ODM_SUPPORT_TYPE & ODM_IOT)
+	return phy_query_bb_reg(dm->adapter, reg_addr, bit_mask);
+#else
+	return phy_query_bb_reg(dm->adapter, reg_addr, bit_mask);
+#endif
+}
+
+void odm_set_rf_reg(struct dm_struct *dm, u8 e_rf_path, u32 reg_addr,
+		    u32 bit_mask, u32 data)
+{
+#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
+	phy_set_rf_reg(dm->priv, e_rf_path, reg_addr, bit_mask, data);
+#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)
+	void *adapter = dm->adapter;
+	PHY_SetRFReg(adapter, e_rf_path, reg_addr, bit_mask, data);
+	ODM_delay_us(2);
+
+#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211)
+	struct rtl_priv *rtlpriv = (struct rtl_priv *)dm->adapter;
+
+	rtl_set_rfreg(rtlpriv->hw, e_rf_path, reg_addr, bit_mask, data);
+#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211_V2)
+	struct rtw_dev *rtwdev = dm->adapter;
+
+	rtw_write_rf(rtwdev, e_rf_path, reg_addr, bit_mask, data);
+#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
+	phy_set_rf_reg(dm->adapter, e_rf_path, reg_addr, bit_mask, data);
+#elif (DM_ODM_SUPPORT_TYPE & ODM_IOT)
+	phy_set_rf_reg(dm->adapter, e_rf_path, reg_addr, bit_mask, data);
+#endif
+}
+
+u32 odm_get_rf_reg(struct dm_struct *dm, u8 e_rf_path, u32 reg_addr,
+		   u32 bit_mask)
+{
+#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
+	return phy_query_rf_reg(dm->priv, e_rf_path, reg_addr, bit_mask, 1);
+#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)
+	void *adapter = dm->adapter;
+	return PHY_QueryRFReg(adapter, e_rf_path, reg_addr, bit_mask);
+#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211)
+	struct rtl_priv *rtlpriv = (struct rtl_priv *)dm->adapter;
+
+	return rtl_get_rfreg(rtlpriv->hw, e_rf_path, reg_addr, bit_mask);
+#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211_V2)
+	struct rtw_dev *rtwdev = dm->adapter;
+
+	return rtw_read_rf(rtwdev, e_rf_path, reg_addr, bit_mask);
+#elif (DM_ODM_SUPPORT_TYPE & ODM_IOT)
+	return phy_query_rf_reg(dm->adapter, e_rf_path, reg_addr, bit_mask);
+#else
+	return phy_query_rf_reg(dm->adapter, e_rf_path, reg_addr, bit_mask);
+#endif
+}
+
+enum hal_status
+phydm_set_reg_by_fw(struct dm_struct *dm, enum phydm_halmac_param config_type,
+		    u32 offset, u32 data, u32 mask, enum rf_path e_rf_path,
+		    u32 delay_time)
+{
+#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN))
+	return HAL_MAC_Config_PHY_WriteNByte(dm,
+					     config_type,
+					     offset,
+					     data,
+					     mask,
+					     e_rf_path,
+					     delay_time);
+#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
+#if (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211)
+	PHYDM_DBG(dm, DBG_CMN, "Not support for CE MAC80211 driver!\n");
+#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211_V2)
+	return -ENOTSUPP;
+#else
+	return rtw_phydm_cfg_phy_para(dm,
+				      config_type,
+				      offset,
+				      data,
+				      mask,
+				      e_rf_path,
+				      delay_time);
+#endif
+#elif (DM_ODM_SUPPORT_TYPE & ODM_IOT)
+	PHYDM_DBG(dm, DBG_CMN, "Not support for CE MAC80211 driver!\n");
+#endif
+}
+
+/*@
+ * ODM Memory relative API.
+ */
+void odm_allocate_memory(struct dm_struct *dm, void **ptr, u32 length)
+{
+#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
+	*ptr = kmalloc(length, GFP_ATOMIC);
+#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211)
+	*ptr = kmalloc(length, GFP_ATOMIC);
+#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211_V2)
+	*ptr = kmalloc(length, GFP_ATOMIC);
+#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
+	*ptr = rtw_zvmalloc(length);
+#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)
+	void *adapter = dm->adapter;
+	PlatformAllocateMemory(adapter, ptr, length);
+#elif (DM_ODM_SUPPORT_TYPE & ODM_IOT)
+	*ptr = rtw_zvmalloc(length);
+#endif
+}
+
+/* @length could be ignored, used to detect memory leakage. */
+void odm_free_memory(struct dm_struct *dm, void *ptr, u32 length)
+{
+#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
+	kfree(ptr);
+#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211)
+	kfree(ptr);
+#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211_V2)
+	kfree(ptr);
+#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
+	rtw_vmfree(ptr, length);
+#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)
+	/* struct void*    adapter = dm->adapter; */
+	PlatformFreeMemory(ptr, length);
+#elif (DM_ODM_SUPPORT_TYPE & ODM_IOT)
+	rtw_vmfree(ptr, length);
+#endif
+}
+
+void odm_move_memory(struct dm_struct *dm, void *dest, void *src, u32 length)
+{
+#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
+	memcpy(dest, src, length);
+#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211)
+	memcpy(dest, src, length);
+#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211_V2)
+	memcpy(dest, src, length);
+#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
+	_rtw_memcpy(dest, src, length);
+#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)
+	PlatformMoveMemory(dest, src, length);
+#elif (DM_ODM_SUPPORT_TYPE & ODM_IOT)
+	rtw_memcpy(dest, src, length);
+#endif
+}
+
+void odm_memory_set(struct dm_struct *dm, void *pbuf, s8 value, u32 length)
+{
+#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
+	memset(pbuf, value, length);
+#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211)
+	memset(pbuf, value, length);
+#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211_V2)
+	memset(pbuf, value, length);
+#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
+	_rtw_memset(pbuf, value, length);
+#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)
+	PlatformFillMemory(pbuf, length, value);
+#elif (DM_ODM_SUPPORT_TYPE & ODM_IOT)
+	rtw_memset(pbuf, value, length);
+#endif
+}
+
+s32 odm_compare_memory(struct dm_struct *dm, void *buf1, void *buf2, u32 length)
+{
+#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
+	return memcmp(buf1, buf2, length);
+#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211)
+	return memcmp(buf1, buf2, length);
+#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211_V2)
+	return memcmp(buf1, buf2, length);
+#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
+	return _rtw_memcmp(buf1, buf2, length);
+#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)
+	return PlatformCompareMemory(buf1, buf2, length);
+#elif (DM_ODM_SUPPORT_TYPE & ODM_IOT)
+	return rtw_memcmp(buf1, buf2, length);
+#endif
+}
+
+/*@
+ * ODM MISC relative API.
+ */
+void odm_acquire_spin_lock(struct dm_struct *dm, enum rt_spinlock_type type)
+{
+#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
+
+#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211)
+	struct rtl_priv *rtlpriv = (struct rtl_priv *)dm->adapter;
+
+	rtl_odm_acquirespinlock(rtlpriv, type);
+#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211_V2)
+	struct rtw_dev *rtwdev = dm->adapter;
+
+	spin_lock(&rtwdev->hal.dm_lock);
+#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
+	void *adapter = dm->adapter;
+	rtw_odm_acquirespinlock(adapter, type);
+#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)
+	void *adapter = dm->adapter;
+	PlatformAcquireSpinLock(adapter, type);
+#elif (DM_ODM_SUPPORT_TYPE & ODM_IOT)
+	void *adapter = dm->adapter;
+
+	rtw_odm_acquirespinlock(adapter, type);
+#endif
+}
+
+void odm_release_spin_lock(struct dm_struct *dm, enum rt_spinlock_type type)
+{
+#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
+
+#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211)
+	struct rtl_priv *rtlpriv = (struct rtl_priv *)dm->adapter;
+
+	rtl_odm_releasespinlock(rtlpriv, type);
+#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211_V2)
+	struct rtw_dev *rtwdev = dm->adapter;
+
+	spin_unlock(&rtwdev->hal.dm_lock);
+#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
+	void *adapter = dm->adapter;
+	rtw_odm_releasespinlock(adapter, type);
+#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)
+	void *adapter = dm->adapter;
+	PlatformReleaseSpinLock(adapter, type);
+#elif (DM_ODM_SUPPORT_TYPE & ODM_IOT)
+	void *adapter = dm->adapter;
+
+	rtw_odm_releasespinlock(adapter, type);
+#endif
+}
+
+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
+/*@
+ * Work item relative API. FOr MP driver only~!
+ *   */
+void odm_initialize_work_item(
+	struct dm_struct *dm,
+	PRT_WORK_ITEM work_item,
+	RT_WORKITEM_CALL_BACK callback,
+	void *context,
+	const char *id)
+{
+#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
+
+#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
+
+#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)
+	void *adapter = dm->adapter;
+	PlatformInitializeWorkItem(adapter, work_item, callback, context, id);
+#endif
+}
+
+void odm_start_work_item(
+	PRT_WORK_ITEM p_rt_work_item)
+{
+#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
+
+#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
+
+#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)
+	PlatformStartWorkItem(p_rt_work_item);
+#endif
+}
+
+void odm_stop_work_item(
+	PRT_WORK_ITEM p_rt_work_item)
+{
+#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
+
+#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
+
+#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)
+	PlatformStopWorkItem(p_rt_work_item);
+#endif
+}
+
+void odm_free_work_item(
+	PRT_WORK_ITEM p_rt_work_item)
+{
+#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
+
+#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
+
+#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)
+	PlatformFreeWorkItem(p_rt_work_item);
+#endif
+}
+
+void odm_schedule_work_item(
+	PRT_WORK_ITEM p_rt_work_item)
+{
+#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
+
+#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
+
+#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)
+	PlatformScheduleWorkItem(p_rt_work_item);
+#endif
+}
+
+boolean
+odm_is_work_item_scheduled(
+	PRT_WORK_ITEM p_rt_work_item)
+{
+#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
+
+#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
+
+#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)
+	return PlatformIsWorkItemScheduled(p_rt_work_item);
+#endif
+}
+#endif
+
+/*@
+ * ODM Timer relative API.
+ */
+
+void ODM_delay_ms(u32 ms)
+{
+#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
+	delay_ms(ms);
+#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211)
+	mdelay(ms);
+#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211_V2)
+	mdelay(ms);
+#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
+	rtw_mdelay_os(ms);
+#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)
+	delay_ms(ms);
+#elif (DM_ODM_SUPPORT_TYPE & ODM_IOT)
+	rtw_mdelay_os(ms);
+#endif
+}
+
+void ODM_delay_us(u32 us)
+{
+#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
+	delay_us(us);
+#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211)
+	udelay(us);
+#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211_V2)
+	udelay(us);
+#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
+	rtw_udelay_os(us);
+#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)
+	PlatformStallExecution(us);
+#elif (DM_ODM_SUPPORT_TYPE & ODM_IOT)
+	rtw_udelay_os(us);
+#endif
+}
+
+void ODM_sleep_ms(u32 ms)
+{
+#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
+	delay_ms(ms);
+#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211)
+	msleep(ms);
+#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211_V2)
+	msleep(ms);
+#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
+	rtw_msleep_os(ms);
+#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)
+	delay_ms(ms);
+#elif (DM_ODM_SUPPORT_TYPE & ODM_IOT)
+	rtw_msleep_os(ms);
+#endif
+}
+
+void ODM_sleep_us(u32 us)
+{
+#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
+	delay_us(us);
+#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211)
+	usleep_range(us, us + 1);
+#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211_V2)
+	usleep_range(us, us + 1);
+#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
+	rtw_usleep_os(us);
+#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)
+	PlatformStallExecution(us);
+#elif (DM_ODM_SUPPORT_TYPE & ODM_IOT)
+	rtw_usleep_os(us);
+#endif
+}
+
+void odm_set_timer(struct dm_struct *dm, struct phydm_timer_list *timer,
+		   u32 ms_delay)
+{
+#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
+	mod_timer(timer, jiffies + RTL_MILISECONDS_TO_JIFFIES(ms_delay));
+#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211)
+	mod_timer(timer, jiffies + msecs_to_jiffies(ms_delay));
+#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211_V2)
+	mod_timer(&timer->timer, jiffies + msecs_to_jiffies(ms_delay));
+#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
+	_set_timer(timer, ms_delay); /* @ms */
+#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)
+	void *adapter = dm->adapter;
+	PlatformSetTimer(adapter, timer, ms_delay);
+#elif (DM_ODM_SUPPORT_TYPE & ODM_IOT)
+	rtw_set_timer(timer, ms_delay); /* @ms */
+#endif
+}
+
+void odm_initialize_timer(struct dm_struct *dm, struct phydm_timer_list *timer,
+			  void *call_back_func, void *context,
+			  const char *sz_id)
+{
+#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
+	init_timer(timer);
+	timer->function = call_back_func;
+	timer->data = (unsigned long)dm;
+#if 0
+	/*@mod_timer(timer, jiffies+RTL_MILISECONDS_TO_JIFFIES(10));	*/
+#endif
+#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211)
+	timer_setup(timer, call_back_func, 0);
+#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
+	struct _ADAPTER *adapter = dm->adapter;
+
+	_init_timer(timer, adapter->pnetdev, call_back_func, dm);
+#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)
+	void *adapter = dm->adapter;
+
+	PlatformInitializeTimer(adapter, timer, (RT_TIMER_CALL_BACK)call_back_func, context, sz_id);
+#elif (DM_ODM_SUPPORT_TYPE & ODM_IOT)
+	struct _ADAPTER *adapter = dm->adapter;
+
+	rtw_init_timer(timer, adapter->pnetdev, (TIMER_FUN)call_back_func, dm, NULL);
+#endif
+}
+
+void odm_cancel_timer(struct dm_struct *dm, struct phydm_timer_list *timer)
+{
+#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
+	del_timer(timer);
+#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211)
+	del_timer(timer);
+#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211_V2)
+	del_timer(&timer->timer);
+#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
+	_cancel_timer_ex(timer);
+#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)
+	void *adapter = dm->adapter;
+	PlatformCancelTimer(adapter, timer);
+#elif (DM_ODM_SUPPORT_TYPE & ODM_IOT)
+	rtw_cancel_timer(timer);
+#endif
+}
+
+void odm_release_timer(struct dm_struct *dm, struct phydm_timer_list *timer)
+{
+#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
+
+#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
+
+#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)
+
+	void *adapter = dm->adapter;
+
+	/* @<20120301, Kordan> If the initilization fails,
+	 * InitializeAdapterXxx will return regardless of InitHalDm.
+	 * Hence, uninitialized timers cause BSOD when the driver
+	 * releases resources since the init fail.
+	 */
+	if (timer == 0) {
+		PHYDM_DBG(dm, ODM_COMP_INIT,
+			  "[%s] Timer is NULL! Please check!\n", __func__);
+		return;
+	}
+
+	PlatformReleaseTimer(adapter, timer);
+#elif (DM_ODM_SUPPORT_TYPE & ODM_IOT)
+	rtw_del_timer(timer);
+#endif
+}
+
+u8 phydm_trans_h2c_id(struct dm_struct *dm, u8 phydm_h2c_id)
+{
+	u8 platform_h2c_id = phydm_h2c_id;
+
+	switch (phydm_h2c_id) {
+	/* @1 [0] */
+	case ODM_H2C_RSSI_REPORT:
+
+#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
+		#if (RTL8188E_SUPPORT == 1)
+		if (dm->support_ic_type == ODM_RTL8188E)
+			platform_h2c_id = H2C_88E_RSSI_REPORT;
+		else
+		#endif
+			platform_h2c_id = H2C_RSSI_REPORT;
+
+#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211)
+#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211_V2)
+#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
+		platform_h2c_id = H2C_RSSI_SETTING;
+
+#elif (DM_ODM_SUPPORT_TYPE & ODM_AP)
+#if ((RTL8881A_SUPPORT == 1) || (RTL8192E_SUPPORT == 1) || (RTL8814A_SUPPORT == 1) || (RTL8822B_SUPPORT == 1) || (RTL8197F_SUPPORT == 1) || (RTL8192F_SUPPORT == 1)) /*@jj add 20170822*/
+		if (dm->support_ic_type == ODM_RTL8881A || dm->support_ic_type == ODM_RTL8192E || dm->support_ic_type & PHYDM_IC_3081_SERIES)
+			platform_h2c_id = H2C_88XX_RSSI_REPORT;
+		else
+#endif
+#if (RTL8812A_SUPPORT == 1)
+			if (dm->support_ic_type == ODM_RTL8812)
+			platform_h2c_id = H2C_8812_RSSI_REPORT;
+		else
+#endif
+		{
+		}
+#endif
+
+		break;
+
+	/* @1 [3] */
+	case ODM_H2C_WIFI_CALIBRATION:
+#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
+		platform_h2c_id = H2C_WIFI_CALIBRATION;
+
+#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
+#if (RTL8723B_SUPPORT == 1)
+		platform_h2c_id = H2C_8723B_BT_WLAN_CALIBRATION;
+#endif
+
+#elif (DM_ODM_SUPPORT_TYPE & ODM_AP)
+#endif
+		break;
+
+	/* @1 [4] */
+	case ODM_H2C_IQ_CALIBRATION:
+#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
+		platform_h2c_id = H2C_IQ_CALIBRATION;
+
+#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
+#if ((RTL8812A_SUPPORT == 1) || (RTL8821A_SUPPORT == 1))
+		platform_h2c_id = H2C_8812_IQ_CALIBRATION;
+#endif
+#elif (DM_ODM_SUPPORT_TYPE & ODM_AP)
+#endif
+
+		break;
+	/* @1 [5] */
+	case ODM_H2C_RA_PARA_ADJUST:
+
+#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
+		platform_h2c_id = H2C_RA_PARA_ADJUST;
+#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211)
+#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211_V2)
+#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
+#if ((RTL8812A_SUPPORT == 1) || (RTL8821A_SUPPORT == 1))
+		platform_h2c_id = H2C_8812_RA_PARA_ADJUST;
+#elif ((RTL8814A_SUPPORT == 1) || (RTL8822B_SUPPORT == 1))
+		platform_h2c_id = H2C_RA_PARA_ADJUST;
+#elif (RTL8192E_SUPPORT == 1)
+		platform_h2c_id = H2C_8192E_RA_PARA_ADJUST;
+#elif (RTL8723B_SUPPORT == 1)
+		platform_h2c_id = H2C_8723B_RA_PARA_ADJUST;
+#endif
+
+#elif (DM_ODM_SUPPORT_TYPE & ODM_AP)
+#if ((RTL8881A_SUPPORT == 1) || (RTL8192E_SUPPORT == 1) || (RTL8814A_SUPPORT == 1) || (RTL8822B_SUPPORT == 1) || (RTL8197F_SUPPORT == 1) || (RTL8192F_SUPPORT == 1)) /*@jj add 20170822*/
+		if (dm->support_ic_type == ODM_RTL8881A || dm->support_ic_type == ODM_RTL8192E || dm->support_ic_type & PHYDM_IC_3081_SERIES)
+			platform_h2c_id = H2C_88XX_RA_PARA_ADJUST;
+		else
+#endif
+#if (RTL8812A_SUPPORT == 1)
+			if (dm->support_ic_type == ODM_RTL8812)
+			platform_h2c_id = H2C_8812_RA_PARA_ADJUST;
+		else
+#endif
+		{
+		}
+#endif
+
+		break;
+
+	/* @1 [6] */
+	case PHYDM_H2C_DYNAMIC_TX_PATH:
+
+#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
+	#if (RTL8814A_SUPPORT == 1)
+		if (dm->support_ic_type == ODM_RTL8814A)
+			platform_h2c_id = H2C_8814A_DYNAMIC_TX_PATH;
+	#endif
+#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
+#if (RTL8814A_SUPPORT == 1)
+		if (dm->support_ic_type == ODM_RTL8814A)
+			platform_h2c_id = H2C_DYNAMIC_TX_PATH;
+#endif
+#elif (DM_ODM_SUPPORT_TYPE & ODM_AP)
+#if (RTL8814A_SUPPORT == 1)
+		if (dm->support_ic_type == ODM_RTL8814A)
+			platform_h2c_id = H2C_88XX_DYNAMIC_TX_PATH;
+#endif
+
+#endif
+
+		break;
+
+	/* @[7]*/
+	case PHYDM_H2C_FW_TRACE_EN:
+
+#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
+
+		platform_h2c_id = H2C_FW_TRACE_EN;
+
+#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
+
+		platform_h2c_id = 0x49;
+
+#elif (DM_ODM_SUPPORT_TYPE & ODM_AP)
+#if ((RTL8881A_SUPPORT == 1) || (RTL8192E_SUPPORT == 1) || (RTL8814A_SUPPORT == 1) || (RTL8822B_SUPPORT == 1) || (RTL8197F_SUPPORT == 1) || (RTL8192F_SUPPORT == 1)) /*@jj add 20170822*/
+		if (dm->support_ic_type == ODM_RTL8881A || dm->support_ic_type == ODM_RTL8192E || dm->support_ic_type & PHYDM_IC_3081_SERIES)
+			platform_h2c_id = H2C_88XX_FW_TRACE_EN;
+		else
+#endif
+#if (RTL8812A_SUPPORT == 1)
+		if (dm->support_ic_type == ODM_RTL8812)
+			platform_h2c_id = H2C_8812_FW_TRACE_EN;
+		else
+#endif
+		{
+		}
+
+#endif
+
+		break;
+
+	case PHYDM_H2C_TXBF:
+#if ((RTL8192E_SUPPORT == 1) || (RTL8812A_SUPPORT == 1))
+		platform_h2c_id = 0x41; /*@H2C_TxBF*/
+#endif
+		break;
+
+	case PHYDM_H2C_MU:
+#if (RTL8822B_SUPPORT == 1)
+		platform_h2c_id = 0x4a; /*@H2C_MU*/
+#endif
+		break;
+
+	default:
+		platform_h2c_id = phydm_h2c_id;
+		break;
+	}
+
+	return platform_h2c_id;
+}
+
+/*@ODM FW relative API.*/
+
+void odm_fill_h2c_cmd(struct dm_struct *dm, u8 phydm_h2c_id, u32 cmd_len,
+		      u8 *cmd_buf)
+{
+#if (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211)
+	struct rtl_priv *rtlpriv = (struct rtl_priv *)dm->adapter;
+#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211_V2)
+	struct rtw_dev *rtwdev = dm->adapter;
+	u8 cmd_id, cmd_class;
+	u8 h2c_pkt[8];
+#else
+	void *adapter = dm->adapter;
+#endif
+	u8 h2c_id = phydm_trans_h2c_id(dm, phydm_h2c_id);
+
+	PHYDM_DBG(dm, DBG_RA, "[H2C]  h2c_id=((0x%x))\n", h2c_id);
+
+#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
+	if (dm->support_ic_type == ODM_RTL8188E) {
+		if (!dm->ra_support88e)
+			FillH2CCmd88E(adapter, h2c_id, cmd_len, cmd_buf);
+	} else if (dm->support_ic_type == ODM_RTL8814A)
+		FillH2CCmd8814A(adapter, h2c_id, cmd_len, cmd_buf);
+	else if (dm->support_ic_type == ODM_RTL8822B)
+		FillH2CCmd8822B(adapter, h2c_id, cmd_len, cmd_buf);
+	else
+		FillH2CCmd(adapter, h2c_id, cmd_len, cmd_buf);
+
+#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
+
+	#ifdef DM_ODM_CE_MAC80211
+	rtlpriv->cfg->ops->fill_h2c_cmd(rtlpriv->hw, h2c_id, cmd_len, cmd_buf);
+	#elif defined(DM_ODM_CE_MAC80211_V2)
+	cmd_id = phydm_h2c_id & 0x1f;
+	cmd_class = (phydm_h2c_id >> RTW_H2C_CLASS_OFFSET) & 0x7;
+	memcpy(h2c_pkt + 1, cmd_buf, 7);
+	h2c_pkt[0] = phydm_h2c_id;
+	rtw_fw_send_h2c_packet(rtwdev, h2c_pkt, cmd_id, cmd_class);
+	/* TODO: implement fill h2c command for rtwlan */
+	#else
+	rtw_hal_fill_h2c_cmd(adapter, h2c_id, cmd_len, cmd_buf);
+	#endif
+
+#elif (DM_ODM_SUPPORT_TYPE & ODM_AP)
+
+	#if (RTL8812A_SUPPORT == 1)
+	if (dm->support_ic_type == ODM_RTL8812) {
+		fill_h2c_cmd8812(dm->priv, h2c_id, cmd_len, cmd_buf);
+	} else
+	#endif
+	{
+		GET_HAL_INTERFACE(dm->priv)->fill_h2c_cmd_handler(dm->priv, h2c_id, cmd_len, cmd_buf);
+	}
+
+#elif (DM_ODM_SUPPORT_TYPE & ODM_IOT)
+	rtw_hal_fill_h2c_cmd(adapter, h2c_id, cmd_len, cmd_buf);
+
+#endif
+}
+
+u8 phydm_c2H_content_parsing(void *dm_void, u8 c2h_cmd_id, u8 c2h_cmd_len,
+			     u8 *tmp_buf)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
+	void *adapter = dm->adapter;
+#endif
+	u8 extend_c2h_sub_id = 0;
+	u8 find_c2h_cmd = true;
+
+	if (c2h_cmd_len > 12 || c2h_cmd_len == 0) {
+		pr_debug("[Warning] Error C2H ID=%d, len=%d\n",
+			 c2h_cmd_id, c2h_cmd_len);
+
+		find_c2h_cmd = false;
+		return find_c2h_cmd;
+	}
+
+	switch (c2h_cmd_id) {
+	case PHYDM_C2H_DBG:
+		phydm_fw_trace_handler(dm, tmp_buf, c2h_cmd_len);
+		break;
+
+	case PHYDM_C2H_RA_RPT:
+		phydm_c2h_ra_report_handler(dm, tmp_buf, c2h_cmd_len);
+		break;
+
+	case PHYDM_C2H_RA_PARA_RPT:
+		odm_c2h_ra_para_report_handler(dm, tmp_buf, c2h_cmd_len);
+		break;
+#ifdef CONFIG_PATH_DIVERSITY
+	case PHYDM_C2H_DYNAMIC_TX_PATH_RPT:
+		if (dm->support_ic_type & (ODM_RTL8814A))
+			phydm_c2h_dtp_handler(dm, tmp_buf, c2h_cmd_len);
+		break;
+#endif
+
+	case PHYDM_C2H_IQK_FINISH:
+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
+
+		if (dm->support_ic_type & (ODM_RTL8812 | ODM_RTL8821)) {
+			RT_TRACE(COMP_MP, DBG_LOUD, ("== FW IQK Finish ==\n"));
+			odm_acquire_spin_lock(dm, RT_IQK_SPINLOCK);
+			dm->rf_calibrate_info.is_iqk_in_progress = false;
+			odm_release_spin_lock(dm, RT_IQK_SPINLOCK);
+			dm->rf_calibrate_info.iqk_progressing_time = 0;
+			dm->rf_calibrate_info.iqk_progressing_time = odm_get_progressing_time(dm, dm->rf_calibrate_info.iqk_start_time);
+		}
+
+#endif
+		break;
+
+	case PHYDM_C2H_CLM_MONITOR:
+		phydm_clm_c2h_report_handler(dm, tmp_buf, c2h_cmd_len);
+		break;
+
+	case PHYDM_C2H_DBG_CODE:
+		phydm_fw_trace_handler_code(dm, tmp_buf, c2h_cmd_len);
+		break;
+
+	case PHYDM_C2H_EXTEND:
+		extend_c2h_sub_id = tmp_buf[0];
+		if (extend_c2h_sub_id == PHYDM_EXTEND_C2H_DBG_PRINT)
+			phydm_fw_trace_handler_8051(dm, tmp_buf, c2h_cmd_len);
+
+		break;
+
+	default:
+		find_c2h_cmd = false;
+		break;
+	}
+
+	return find_c2h_cmd;
+}
+
+u64 odm_get_current_time(struct dm_struct *dm)
+{
+#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
+	return (u64)rtw_get_current_time();
+#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211)
+	return jiffies;
+#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211_V2)
+	return jiffies;
+#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
+	return rtw_get_current_time();
+#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)
+	return PlatformGetCurrentTime();
+#elif (DM_ODM_SUPPORT_TYPE & ODM_IOT)
+	return rtw_get_current_time();
+#endif
+}
+
+u64 odm_get_progressing_time(struct dm_struct *dm, u64 start_time)
+{
+#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
+	return rtw_get_passing_time_ms((u32)start_time);
+#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211)
+	return jiffies_to_msecs(jiffies - start_time);
+#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211_V2)
+	return jiffies_to_msecs(jiffies - start_time);
+#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
+	return rtw_get_passing_time_ms((systime)start_time);
+#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)
+	return ((PlatformGetCurrentTime() - start_time) >> 10);
+#elif (DM_ODM_SUPPORT_TYPE & ODM_IOT)
+	return rtw_get_passing_time_ms(start_time);
+#endif
+}
+
+#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) && \
+	(!defined(DM_ODM_CE_MAC80211) && !defined(DM_ODM_CE_MAC80211_V2))
+
+void phydm_set_hw_reg_handler_interface(struct dm_struct *dm, u8 RegName,
+					u8 *val)
+{
+#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
+	struct _ADAPTER *adapter = dm->adapter;
+
+#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
+	((PADAPTER)adapter)->HalFunc.SetHwRegHandler(adapter, RegName, val);
+#else
+	adapter->hal_func.set_hw_reg_handler(adapter, RegName, val);
+#endif
+
+#endif
+}
+
+void phydm_get_hal_def_var_handler_interface(struct dm_struct *dm,
+					     enum _HAL_DEF_VARIABLE e_variable,
+					     void *value)
+{
+#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
+	struct _ADAPTER *adapter = dm->adapter;
+
+#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
+	((PADAPTER)adapter)->HalFunc.GetHalDefVarHandler(adapter, e_variable, value);
+#else
+	adapter->hal_func.get_hal_def_var_handler(adapter, e_variable, value);
+#endif
+
+#endif
+}
+
+#endif
+
+void odm_set_tx_power_index_by_rate_section(struct dm_struct *dm,
+					    enum rf_path path, u8 ch,
+					    u8 section)
+{
+#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
+	void *adapter = dm->adapter;
+	PHY_SetTxPowerIndexByRateSection(adapter, path, ch, section);
+#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) && defined(DM_ODM_CE_MAC80211)
+	void *adapter = dm->adapter;
+
+	phy_set_tx_power_index_by_rs(adapter, ch, path, section);
+#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) && defined(DM_ODM_CE_MAC80211_V2)
+#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
+	phy_set_tx_power_index_by_rate_section(dm->adapter, path, ch, section);
+#elif (DM_ODM_SUPPORT_TYPE & ODM_IOT)
+	void *adapter = dm->adapter;
+
+	PHY_SetTxPowerIndexByRateSection(adapter, path, ch, section);
+#endif
+}
+
+u8 odm_get_tx_power_index(struct dm_struct *dm, enum rf_path path, u8 rate,
+			  u8 bw, u8 ch)
+{
+#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
+	void *adapter = dm->adapter;
+
+	return PHY_GetTxPowerIndex(dm->adapter, path, rate, (CHANNEL_WIDTH)bw, ch);
+#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211)
+	void *adapter = dm->adapter;
+
+	return phy_get_tx_power_index(adapter, path, rate, bw, ch);
+#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211_V2)
+	void *adapter = dm->adapter;
+
+	return phy_get_tx_power_index(adapter, path, rate, bw, ch);
+#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
+	return phy_get_tx_power_index(dm->adapter, path, rate, bw, ch);
+#elif (DM_ODM_SUPPORT_TYPE & ODM_IOT)
+	void *adapter = dm->adapter;
+
+	return PHY_GetTxPowerIndex(dm->adapter, path, rate, bw, ch);
+#endif
+}
+
+u8 odm_efuse_one_byte_read(struct dm_struct *dm, u16 addr, u8 *data,
+			   boolean b_pseu_do_test)
+{
+#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
+	void *adapter = dm->adapter;
+
+	return (u8)EFUSE_OneByteRead(adapter, addr, data, b_pseu_do_test);
+#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211)
+	void *adapter = dm->adapter;
+
+	return rtl_efuse_onebyte_read(adapter, addr, data, b_pseu_do_test);
+#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211_V2)
+	return -1;
+#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
+	return efuse_onebyte_read(dm->adapter, addr, data, b_pseu_do_test);
+#elif (DM_ODM_SUPPORT_TYPE & ODM_AP)
+/*ReadEFuseByte(dm->priv, addr, data);*/
+/*return true;*/
+#elif (DM_ODM_SUPPORT_TYPE & ODM_IOT)
+	void *adapter = dm->adapter;
+
+	return (u8)efuse_OneByteRead(adapter, addr, data, b_pseu_do_test);
+#endif
+}
+
+void odm_efuse_logical_map_read(struct dm_struct *dm, u8 type, u16 offset,
+				u32 *data)
+{
+#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
+	void *adapter = dm->adapter;
+
+	EFUSE_ShadowRead(adapter, type, offset, data);
+#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211)
+	void *adapter = dm->adapter;
+
+	rtl_efuse_logical_map_read(adapter, type, offset, data);
+#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211_V2)
+#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
+	efuse_logical_map_read(dm->adapter, type, offset, data);
+#elif (DM_ODM_SUPPORT_TYPE & ODM_IOT)
+	void *adapter = dm->adapter;
+
+	EFUSE_ShadowRead(adapter, type, offset, data);
+#endif
+}
+
+enum hal_status
+odm_iq_calibrate_by_fw(struct dm_struct *dm, u8 clear, u8 segment)
+{
+	enum hal_status iqk_result = HAL_STATUS_FAILURE;
+
+#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
+	struct _ADAPTER *adapter = dm->adapter;
+
+	if (HAL_MAC_FWIQK_Trigger(&GET_HAL_MAC_INFO(adapter), clear, segment) == 0)
+		iqk_result = HAL_STATUS_SUCCESS;
+#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
+#if (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211)
+	void *adapter = dm->adapter;
+
+	iqk_result = rtl_phydm_fw_iqk(adapter, clear, segment);
+#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211_V2)
+#else
+	iqk_result = rtw_phydm_fw_iqk(dm, clear, segment);
+#endif
+#elif (DM_ODM_SUPPORT_TYPE & ODM_IOT)
+	iqk_result = rtw_phydm_fw_iqk(dm, clear, segment);
+#endif
+	return iqk_result;
+}
+
+void odm_cmn_info_ptr_array_hook(struct dm_struct *dm,
+				 enum odm_cmninfo cmn_info, u16 index,
+				 void *value)
+{
+	switch (cmn_info) {
+	/*@Dynamic call by reference pointer.	*/
+	case ODM_CMNINFO_STA_STATUS:
+		dm->odm_sta_info[index] = (struct sta_info *)value;
+		break;
+	/* To remove the compiler warning,
+	 * must add an empty default statement to handle the other values.
+	 */
+	default:
+		/* @do nothing */
+		break;
+	}
+}
+
+void phydm_cmn_sta_info_hook(struct dm_struct *dm, u8 mac_id,
+			     struct cmn_sta_info *pcmn_sta_info)
+{
+	dm->phydm_sta_info[mac_id] = pcmn_sta_info;
+
+	if (is_sta_active(pcmn_sta_info))
+		dm->phydm_macid_table[pcmn_sta_info->mac_id] = mac_id;
+}
+
+void phydm_macid2sta_idx_table(struct dm_struct *dm, u8 entry_idx,
+			       struct cmn_sta_info *pcmn_sta_info)
+{
+	if (is_sta_active(pcmn_sta_info))
+		dm->phydm_macid_table[pcmn_sta_info->mac_id] = entry_idx;
+}
+
+void phydm_add_interrupt_mask_handler(struct dm_struct *dm, u8 interrupt_type)
+{
+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
+#elif (DM_ODM_SUPPORT_TYPE == ODM_AP)
+
+	struct rtl8192cd_priv *priv = dm->priv;
+
+	#if IS_EXIST_PCI || IS_EXIST_EMBEDDED
+	GET_HAL_INTERFACE(priv)->AddInterruptMaskHandler(priv, interrupt_type);
+	#endif
+
+#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
+#endif
+}
+
+void phydm_enable_rx_related_interrupt_handler(struct dm_struct *dm)
+{
+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
+#elif (DM_ODM_SUPPORT_TYPE == ODM_AP)
+
+	struct rtl8192cd_priv *priv = dm->priv;
+
+	#if IS_EXIST_PCI || IS_EXIST_EMBEDDED
+	GET_HAL_INTERFACE(priv)->EnableRxRelatedInterruptHandler(priv);
+	#endif
+
+#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
+#endif
+}
+
+#if 0
+boolean
+phydm_get_txbf_en(
+	struct dm_struct		*dm,
+	u16							mac_id,
+	u8							i
+)
+{
+	boolean txbf_en = false;
+
+#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
+#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && !defined(DM_ODM_CE_MAC80211)
+
+#ifdef CONFIG_BEAMFORMING
+	enum beamforming_cap beamform_cap;
+	void *adapter = dm->adapter;
+	#if (BEAMFORMING_SUPPORT == 1)
+	beamform_cap =
+	phydm_beamforming_get_entry_beam_cap_by_mac_id(dm, mac_id);
+	#else/*@for drv beamforming*/
+	beamform_cap =
+	beamforming_get_entry_beam_cap_by_mac_id(&adapter->mlmepriv, mac_id);
+	#endif
+	if (beamform_cap & (BEAMFORMER_CAP_HT_EXPLICIT | BEAMFORMER_CAP_VHT_SU))
+		txbf_en = true;
+	else
+		txbf_en = false;
+#endif /*@#ifdef CONFIG_BEAMFORMING*/
+
+#elif (DM_ODM_SUPPORT_TYPE & ODM_AP)
+
+#if (BEAMFORMING_SUPPORT == 1)
+	u8 idx = 0xff;
+	boolean act_bfer = false;
+	BEAMFORMING_CAP beamform_cap = BEAMFORMING_CAP_NONE;
+	PRT_BEAMFORMING_ENTRY	entry = NULL;
+	struct rtl8192cd_priv *priv			= dm->priv;
+	#if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY))
+	struct _BF_DIV_COEX_	*dm_bdc_table = &dm->dm_bdc_table;
+
+	dm_bdc_table->num_txbfee_client = 0;
+	dm_bdc_table->num_txbfer_client = 0;
+	#endif
+#endif
+
+#if (BEAMFORMING_SUPPORT == 1)
+	beamform_cap = Beamforming_GetEntryBeamCapByMacId(priv, mac_id);
+	entry = Beamforming_GetEntryByMacId(priv, mac_id, &idx);
+	if (beamform_cap & (BEAMFORMER_CAP_HT_EXPLICIT | BEAMFORMER_CAP_VHT_SU)) {
+		if (entry->Sounding_En)
+			txbf_en = true;
+		else
+			txbf_en = false;
+		act_bfer = true;
+	}
+	#if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY)) /*@BDC*/
+	if (act_bfer == true) {
+		dm_bdc_table->w_bfee_client[i] = true; /* @AP act as BFer */
+		dm_bdc_table->num_txbfee_client++;
+	} else
+		dm_bdc_table->w_bfee_client[i] = false; /* @AP act as BFer */
+
+	if (beamform_cap & (BEAMFORMEE_CAP_HT_EXPLICIT | BEAMFORMEE_CAP_VHT_SU)) {
+		dm_bdc_table->w_bfer_client[i] = true; /* @AP act as BFee */
+		dm_bdc_table->num_txbfer_client++;
+	} else
+		dm_bdc_table->w_bfer_client[i] = false; /* @AP act as BFer */
+
+	#endif
+#endif
+
+#endif
+	return txbf_en;
+}
+#endif
+
+void phydm_iqk_wait(struct dm_struct *dm, u32 timeout)
+{
+#if (DM_ODM_SUPPORT_TYPE == ODM_CE)
+#if (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211)
+	PHYDM_DBG(dm, DBG_CMN, "Not support for CE MAC80211 driver!\n");
+#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211_V2)
+#else
+	void *adapter = dm->adapter;
+
+	rtl8812_iqk_wait(adapter, timeout);
+#endif
+#endif
+}
+
+u8 phydm_get_hwrate_to_mrate(struct dm_struct *dm, u8 rate)
+{
+#if (DM_ODM_SUPPORT_TYPE == ODM_IOT)
+	return HwRateToMRate(rate);
+#endif
+	return 0;
+}
+
+void phydm_set_crystalcap(struct dm_struct *dm, u8 crystal_cap)
+{
+#if (DM_ODM_SUPPORT_TYPE == ODM_IOT)
+	ROM_odm_SetCrystalCap(dm, crystal_cap);
+#endif
+}
+
+void phydm_run_in_thread_cmd(struct dm_struct *dm, void (*func)(void *),
+			     void *context)
+{
+#if (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211)
+	PHYDM_DBG(dm, DBG_CMN, "Not support for CE MAC80211 driver!\n");
+#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
+	void *adapter = dm->adapter;
+
+	rtw_run_in_thread_cmd(adapter, func, context);
+#endif
+}
+
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/phydm_interface.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/phydm_interface.h
--- linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/phydm_interface.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/phydm_interface.h	2020-04-10 16:35:06.825660488 +0300
@@ -0,0 +1,340 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017  Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * The full GNU General Public License is included in this distribution in the
+ * file called LICENSE.
+ *
+ * Contact Information:
+ * wlanfae <wlanfae@realtek.com>
+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
+ * Hsinchu 300, Taiwan.
+ *
+ * Larry Finger <Larry.Finger@lwfinger.net>
+ *
+ *****************************************************************************/
+
+#ifndef __ODM_INTERFACE_H__
+#define __ODM_INTERFACE_H__
+
+#define INTERFACE_VERSION "1.2"
+
+#define pdm_set_reg odm_set_bb_reg
+
+/*@=========== Constant/Structure/Enum/... Define*/
+
+enum phydm_h2c_cmd {
+	PHYDM_H2C_RA_MASK		= 0x40,
+	PHYDM_H2C_TXBF			= 0x41,
+	ODM_H2C_RSSI_REPORT		= 0x42,
+	ODM_H2C_IQ_CALIBRATION		= 0x45,
+	PHYDM_RA_MASK_ABOVE_3SS		= 0x46,
+	ODM_H2C_RA_PARA_ADJUST		= 0x47,
+	PHYDM_H2C_DYNAMIC_TX_PATH	= 0x48,
+	PHYDM_H2C_FW_TRACE_EN		= 0x49,
+	ODM_H2C_WIFI_CALIBRATION	= 0x6d,
+	PHYDM_H2C_MU			= 0x4a,
+	PHYDM_H2C_FW_GENERAL_INIT	= 0x4c,
+	PHYDM_H2C_FW_CLM_MNTR		= 0x4d,
+	PHYDM_H2C_MCC			= 0x4f,
+	ODM_MAX_H2CCMD
+};
+
+enum phydm_c2h_evt {
+	PHYDM_C2H_DBG =		0,
+	PHYDM_C2H_LB =		1,
+	PHYDM_C2H_XBF =		2,
+	PHYDM_C2H_TX_REPORT =	3,
+	PHYDM_C2H_INFO =	9,
+	PHYDM_C2H_BT_MP =	11,
+	PHYDM_C2H_RA_RPT =	12,
+	PHYDM_C2H_RA_PARA_RPT = 14,
+	PHYDM_C2H_DYNAMIC_TX_PATH_RPT = 15,
+	PHYDM_C2H_IQK_FINISH =	17, /*@0x11*/
+	PHYDM_C2H_CLM_MONITOR =	0x2a,
+	PHYDM_C2H_DBG_CODE =	0xFE,
+	PHYDM_C2H_EXTEND =	0xFF,
+};
+
+enum phydm_extend_c2h_evt {
+	PHYDM_EXTEND_C2H_DBG_PRINT = 0
+
+};
+
+enum phydm_halmac_param {
+	PHYDM_HALMAC_CMD_MAC_W8 = 0,
+	PHYDM_HALMAC_CMD_MAC_W16 = 1,
+	PHYDM_HALMAC_CMD_MAC_W32 = 2,
+	PHYDM_HALMAC_CMD_BB_W8,
+	PHYDM_HALMAC_CMD_BB_W16,
+	PHYDM_HALMAC_CMD_BB_W32,
+	PHYDM_HALMAC_CMD_RF_W,
+	PHYDM_HALMAC_CMD_DELAY_US,
+	PHYDM_HALMAC_CMD_DELAY_MS,
+	PHYDM_HALMAC_CMD_END = 0XFF,
+};
+
+/*@=========== Macro Define*/
+
+#define _reg_all(_name)			ODM_##_name
+#define _reg_ic(_name, _ic)		ODM_##_name##_ic
+#define _bit_all(_name)			BIT_##_name
+#define _bit_ic(_name, _ic)		BIT_##_name##_ic
+
+/* @_cat: implemented by Token-Pasting Operator. */
+#if 0
+#define _cat(_name, _ic_type, _func) \
+	(                            \
+		_func##_all(_name))
+#endif
+
+#if 0
+
+#define ODM_REG_DIG_11N		0xC50
+#define ODM_REG_DIG_11AC	0xDDD
+
+ODM_REG(DIG,_pdm_odm)
+#endif
+
+#if defined(DM_ODM_CE_MAC80211)
+#define ODM_BIT(name, dm)				\
+	((dm->support_ic_type & ODM_IC_11N_SERIES) ?	\
+	 ODM_BIT_##name##_11N : ODM_BIT_##name##_11AC)
+
+#define ODM_REG(name, dm)				\
+	((dm->support_ic_type & ODM_IC_11N_SERIES) ?	\
+	 ODM_REG_##name##_11N : ODM_REG_##name##_11AC)
+#else
+#define _reg_11N(_name)			ODM_REG_##_name##_11N
+#define _reg_11AC(_name)		ODM_REG_##_name##_11AC
+#define _bit_11N(_name)			ODM_BIT_##_name##_11N
+#define _bit_11AC(_name)		ODM_BIT_##_name##_11AC
+
+#ifdef __ECOS
+#define _rtk_cat(_name, _ic_type, _func)                                \
+	(                                                               \
+		((_ic_type) & ODM_IC_11N_SERIES) ? _func##_11N(_name) : \
+						   _func##_11AC(_name))
+#else
+
+#define _cat(_name, _ic_type, _func)                                    \
+	(                                                               \
+		((_ic_type) & ODM_IC_11N_SERIES) ? _func##_11N(_name) : \
+						   _func##_11AC(_name))
+#endif
+/*@
+ * only sample code
+ *#define _cat(_name, _ic_type, _func)					\
+ *	(								\
+ *		((_ic_type) & ODM_RTL8188E) ? _func##_ic(_name, _8188E) :\
+ *		_func##_ic(_name, _8195)				\
+ *	)
+ */
+
+/* @_name: name of register or bit.
+ * Example: "ODM_REG(R_A_AGC_CORE1, dm)"
+ * gets "ODM_R_A_AGC_CORE1" or "ODM_R_A_AGC_CORE1_8192C",
+ * depends on support_ic_type.
+ */
+#ifdef __ECOS
+	#define ODM_REG(_name, _pdm_odm)	\
+		_rtk_cat(_name, _pdm_odm->support_ic_type, _reg)
+	#define ODM_BIT(_name, _pdm_odm)	\
+		_rtk_cat(_name, _pdm_odm->support_ic_type, _bit)
+#else
+	#define ODM_REG(_name, _pdm_odm)	\
+		_cat(_name, _pdm_odm->support_ic_type, _reg)
+	#define ODM_BIT(_name, _pdm_odm)	\
+		_cat(_name, _pdm_odm->support_ic_type, _bit)
+#endif
+
+#endif
+/*@
+ * =========== Extern Variable ??? It should be forbidden.
+ */
+
+/*@
+ * =========== EXtern Function Prototype
+ */
+
+u8 odm_read_1byte(struct dm_struct *dm, u32 reg_addr);
+
+u16 odm_read_2byte(struct dm_struct *dm, u32 reg_addr);
+
+u32 odm_read_4byte(struct dm_struct *dm, u32 reg_addr);
+
+void odm_write_1byte(struct dm_struct *dm, u32 reg_addr, u8 data);
+
+void odm_write_2byte(struct dm_struct *dm, u32 reg_addr, u16 data);
+
+void odm_write_4byte(struct dm_struct *dm, u32 reg_addr, u32 data);
+
+void odm_set_mac_reg(struct dm_struct *dm, u32 reg_addr, u32 bit_mask,
+		     u32 data);
+
+u32 odm_get_mac_reg(struct dm_struct *dm, u32 reg_addr, u32 bit_mask);
+
+void odm_set_bb_reg(struct dm_struct *dm, u32 reg_addr, u32 bit_mask, u32 data);
+
+u32 odm_get_bb_reg(struct dm_struct *dm, u32 reg_addr, u32 bit_mask);
+
+void odm_set_rf_reg(struct dm_struct *dm, u8 e_rf_path, u32 reg_addr,
+		    u32 bit_mask, u32 data);
+
+u32 odm_get_rf_reg(struct dm_struct *dm, u8 e_rf_path, u32 reg_addr,
+		   u32 bit_mask);
+
+/*@
+ * Memory Relative Function.
+ */
+void odm_allocate_memory(struct dm_struct *dm, void **ptr, u32 length);
+void odm_free_memory(struct dm_struct *dm, void *ptr, u32 length);
+
+void odm_move_memory(struct dm_struct *dm, void *dest, void *src, u32 length);
+
+s32 odm_compare_memory(struct dm_struct *dm, void *buf1, void *buf2,
+		       u32 length);
+
+void odm_memory_set(struct dm_struct *dm, void *pbuf, s8 value, u32 length);
+
+/*@
+ * ODM MISC-spin lock relative API.
+ */
+void odm_acquire_spin_lock(struct dm_struct *dm, enum rt_spinlock_type type);
+
+void odm_release_spin_lock(struct dm_struct *dm, enum rt_spinlock_type type);
+
+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
+/*@
+ * ODM MISC-workitem relative API.
+ */
+void odm_initialize_work_item(
+	struct dm_struct *dm,
+	PRT_WORK_ITEM p_rt_work_item,
+	RT_WORKITEM_CALL_BACK rt_work_item_callback,
+	void *context,
+	const char *sz_id);
+
+void odm_start_work_item(
+	PRT_WORK_ITEM p_rt_work_item);
+
+void odm_stop_work_item(
+	PRT_WORK_ITEM p_rt_work_item);
+
+void odm_free_work_item(
+	PRT_WORK_ITEM p_rt_work_item);
+
+void odm_schedule_work_item(
+	PRT_WORK_ITEM p_rt_work_item);
+
+boolean
+odm_is_work_item_scheduled(
+	PRT_WORK_ITEM p_rt_work_item);
+#endif
+
+/*@
+ * ODM Timer relative API.
+ */
+void ODM_delay_ms(u32 ms);
+
+void ODM_delay_us(u32 us);
+
+void ODM_sleep_ms(u32 ms);
+
+void ODM_sleep_us(u32 us);
+
+void odm_set_timer(struct dm_struct *dm, struct phydm_timer_list *timer,
+		   u32 ms_delay);
+
+void odm_initialize_timer(struct dm_struct *dm, struct phydm_timer_list *timer,
+			  void *call_back_func, void *context,
+			  const char *sz_id);
+
+void odm_cancel_timer(struct dm_struct *dm, struct phydm_timer_list *timer);
+
+void odm_release_timer(struct dm_struct *dm, struct phydm_timer_list *timer);
+
+/*ODM FW relative API.*/
+
+enum hal_status
+phydm_set_reg_by_fw(struct dm_struct *dm, enum phydm_halmac_param config_type,
+		    u32 offset, u32 data, u32 mask, enum rf_path e_rf_path,
+		    u32 delay_time);
+
+void odm_fill_h2c_cmd(struct dm_struct *dm, u8 element_id, u32 cmd_len,
+		      u8 *cmd_buffer);
+
+u8 phydm_c2H_content_parsing(void *dm_void, u8 c2h_cmd_id, u8 c2h_cmd_len,
+			     u8 *tmp_buf);
+
+u64 odm_get_current_time(struct dm_struct *dm);
+u64 odm_get_progressing_time(struct dm_struct *dm, u64 start_time);
+
+#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) && \
+	(!defined(DM_ODM_CE_MAC80211) && !defined(DM_ODM_CE_MAC80211_V2))
+
+void phydm_set_hw_reg_handler_interface(struct dm_struct *dm, u8 reg_Name,
+					u8 *val);
+
+void phydm_get_hal_def_var_handler_interface(struct dm_struct *dm,
+					     enum _HAL_DEF_VARIABLE e_variable,
+					     void *value);
+
+#endif
+
+void odm_set_tx_power_index_by_rate_section(struct dm_struct *dm,
+					    enum rf_path path, u8 channel,
+					    u8 rate_section);
+
+u8 odm_get_tx_power_index(struct dm_struct *dm, enum rf_path path, u8 tx_rate,
+			  u8 band_width, u8 channel);
+
+u8 odm_efuse_one_byte_read(struct dm_struct *dm, u16 addr, u8 *data,
+			   boolean b_pseu_do_test);
+
+void odm_efuse_logical_map_read(struct dm_struct *dm, u8 type, u16 offset,
+				u32 *data);
+
+enum hal_status
+odm_iq_calibrate_by_fw(struct dm_struct *dm, u8 clear, u8 segment);
+
+void odm_cmn_info_ptr_array_hook(struct dm_struct *dm,
+				 enum odm_cmninfo cmn_info, u16 index,
+				 void *value);
+
+void phydm_cmn_sta_info_hook(struct dm_struct *dm, u8 index,
+			     struct cmn_sta_info *pcmn_sta_info);
+
+void phydm_macid2sta_idx_table(struct dm_struct *dm, u8 entry_idx,
+			       struct cmn_sta_info *pcmn_sta_info);
+
+void phydm_add_interrupt_mask_handler(struct dm_struct *dm, u8 interrupt_type);
+
+void phydm_enable_rx_related_interrupt_handler(struct dm_struct *dm);
+
+#if 0
+boolean
+phydm_get_txbf_en(
+	struct dm_struct		*dm,
+	u16		mac_id,
+	u8		i
+);
+#endif
+
+void phydm_iqk_wait(struct dm_struct *dm, u32 timeout);
+
+u8 phydm_get_hwrate_to_mrate(struct dm_struct *dm, u8 rate);
+
+void phydm_set_crystalcap(struct dm_struct *dm, u8 crystal_cap);
+void phydm_run_in_thread_cmd(struct dm_struct *dm, void (*func)(void *),
+			     void *context);
+#endif /* @__ODM_INTERFACE_H__ */
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/phydm_iqk.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/phydm_iqk.h
--- linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/phydm_iqk.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/phydm_iqk.h	2020-04-10 16:35:06.825660488 +0300
@@ -0,0 +1,65 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
+ *
+ *
+ ******************************************************************************/
+
+#ifndef	__PHYDMIQK_H__
+#define __PHYDMIQK_H__
+
+/*--------------------------Define Parameters-------------------------------*/
+#define	LOK_delay 1
+#define	WBIQK_delay 10
+#define	TX_IQK 0
+#define	RX_IQK 1
+#define	TXIQK 0
+#define	RXIQK1 1
+#define	RXIQK2 2
+#define kcount_limit_80m 2
+#define kcount_limit_others 4
+#define rxiqk_gs_limit 4
+
+#define	NUM 4
+/*---------------------------End Define Parameters-------------------------------*/
+
+struct _IQK_INFORMATION {
+	boolean		LOK_fail[NUM];
+	boolean		IQK_fail[2][NUM];
+	u32		iqc_matrix[2][NUM];
+	u8      iqk_times;
+	u32		rf_reg18;
+	u32		lna_idx;
+	u8		rxiqk_step;
+	u8		tmp1bcc;
+	u8		kcount;
+
+	u32		iqk_channel[2];
+	boolean		IQK_fail_report[2][4][2]; /*channel/path/TRX(TX:0, RX:1) */
+	u32		IQK_CFIR_real[2][4][2][8]; /*channel / path / TRX(TX:0, RX:1) / CFIR_real*/
+	u32		IQK_CFIR_imag[2][4][2][8]; /*channel / path / TRX(TX:0, RX:1) / CFIR_imag*/
+	u8		retry_count[2][4][3]; /* channel / path / (TXK:0, RXK1:1, RXK2:2) */
+	u8		gs_retry_count[2][4][2]; /* channel / path / (GSRXK1:0, GSRXK2:1) */
+	u8		RXIQK_fail_code[2][4]; /* channel / path 0:SRXK1 fail, 1:RXK1 fail 2:RXK2 fail */
+	u32		LOK_IDAC[2][4];		/*channel / path*/
+	u16		RXIQK_AGC[2][4];	 /*channel / path*/
+	u32		bypass_iqk[2][4];	/*channel / 0xc94/0xe94*/
+	u32		tmp_GNTWL;
+	boolean		is_BTG;
+	boolean		isbnd;
+};
+
+#endif
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/phydm_kfree.c linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/phydm_kfree.c
--- linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/phydm_kfree.c	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/phydm_kfree.c	2020-04-10 16:35:06.825660488 +0300
@@ -0,0 +1,373 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
+ *
+ *
+ ******************************************************************************/
+
+/*============================================================*/
+/*include files*/
+/*============================================================*/
+#include "mp_precomp.h"
+#include "phydm_precomp.h"
+
+
+/*<YuChen, 150720> Add for KFree Feature Requested by RF David.*/
+/*This is a phydm API*/
+
+
+
+void
+phydm_set_kfree_to_rf_8814a(
+	void		*p_dm_void,
+	u8		e_rf_path,
+	u8		data
+)
+{
+	struct PHY_DM_STRUCT		*p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
+	struct odm_rf_calibration_structure	*p_rf_calibrate_info = &(p_dm_odm->rf_calibrate_info);
+	boolean is_odd;
+
+	if ((data % 2) != 0) {	/*odd->positive*/
+		data = data - 1;
+		odm_set_rf_reg(p_dm_odm, e_rf_path, REG_RF_TX_GAIN_OFFSET, BIT(19), 1);
+		is_odd = true;
+	} else {		/*even->negative*/
+		odm_set_rf_reg(p_dm_odm, e_rf_path, REG_RF_TX_GAIN_OFFSET, BIT(19), 0);
+		is_odd = false;
+	}
+	ODM_RT_TRACE(p_dm_odm, ODM_COMP_MP, ODM_DBG_LOUD, ("phy_ConfigKFree8814A(): RF_0x55[19]= %d\n", is_odd));
+	switch (data) {
+	case 0:
+		odm_set_rf_reg(p_dm_odm, e_rf_path, REG_RF_TX_GAIN_OFFSET, BIT(14), 0);
+		odm_set_rf_reg(p_dm_odm, e_rf_path, REG_RF_TX_GAIN_OFFSET, BIT(17) | BIT(16) | BIT(15), 0);
+		p_rf_calibrate_info->kfree_offset[e_rf_path] = 0;
+		break;
+	case 2:
+		odm_set_rf_reg(p_dm_odm, e_rf_path, REG_RF_TX_GAIN_OFFSET, BIT(14), 1);
+		odm_set_rf_reg(p_dm_odm, e_rf_path, REG_RF_TX_GAIN_OFFSET, BIT(17) | BIT(16) | BIT(15), 0);
+		p_rf_calibrate_info->kfree_offset[e_rf_path] = 0;
+		break;
+	case 4:
+		odm_set_rf_reg(p_dm_odm, e_rf_path, REG_RF_TX_GAIN_OFFSET, BIT(14), 0);
+		odm_set_rf_reg(p_dm_odm, e_rf_path, REG_RF_TX_GAIN_OFFSET, BIT(17) | BIT(16) | BIT(15), 1);
+		p_rf_calibrate_info->kfree_offset[e_rf_path] = 1;
+		break;
+	case 6:
+		odm_set_rf_reg(p_dm_odm, e_rf_path, REG_RF_TX_GAIN_OFFSET, BIT(14), 1);
+		odm_set_rf_reg(p_dm_odm, e_rf_path, REG_RF_TX_GAIN_OFFSET, BIT(17) | BIT(16) | BIT(15), 1);
+		p_rf_calibrate_info->kfree_offset[e_rf_path] = 1;
+		break;
+	case 8:
+		odm_set_rf_reg(p_dm_odm, e_rf_path, REG_RF_TX_GAIN_OFFSET, BIT(14), 0);
+		odm_set_rf_reg(p_dm_odm, e_rf_path, REG_RF_TX_GAIN_OFFSET, BIT(17) | BIT(16) | BIT(15), 2);
+		p_rf_calibrate_info->kfree_offset[e_rf_path] = 2;
+		break;
+	case 10:
+		odm_set_rf_reg(p_dm_odm, e_rf_path, REG_RF_TX_GAIN_OFFSET, BIT(14), 1);
+		odm_set_rf_reg(p_dm_odm, e_rf_path, REG_RF_TX_GAIN_OFFSET, BIT(17) | BIT(16) | BIT(15), 2);
+		p_rf_calibrate_info->kfree_offset[e_rf_path] = 2;
+		break;
+	case 12:
+		odm_set_rf_reg(p_dm_odm, e_rf_path, REG_RF_TX_GAIN_OFFSET, BIT(14), 0);
+		odm_set_rf_reg(p_dm_odm, e_rf_path, REG_RF_TX_GAIN_OFFSET, BIT(17) | BIT(16) | BIT(15), 3);
+		p_rf_calibrate_info->kfree_offset[e_rf_path] = 3;
+		break;
+	case 14:
+		odm_set_rf_reg(p_dm_odm, e_rf_path, REG_RF_TX_GAIN_OFFSET, BIT(14), 1);
+		odm_set_rf_reg(p_dm_odm, e_rf_path, REG_RF_TX_GAIN_OFFSET, BIT(17) | BIT(16) | BIT(15), 3);
+		p_rf_calibrate_info->kfree_offset[e_rf_path] = 3;
+		break;
+	case 16:
+		odm_set_rf_reg(p_dm_odm, e_rf_path, REG_RF_TX_GAIN_OFFSET, BIT(14), 0);
+		odm_set_rf_reg(p_dm_odm, e_rf_path, REG_RF_TX_GAIN_OFFSET, BIT(17) | BIT(16) | BIT(15), 4);
+		p_rf_calibrate_info->kfree_offset[e_rf_path] = 4;
+		break;
+	case 18:
+		odm_set_rf_reg(p_dm_odm, e_rf_path, REG_RF_TX_GAIN_OFFSET, BIT(14), 1);
+		odm_set_rf_reg(p_dm_odm, e_rf_path, REG_RF_TX_GAIN_OFFSET, BIT(17) | BIT(16) | BIT(15), 4);
+		p_rf_calibrate_info->kfree_offset[e_rf_path] = 4;
+		break;
+	case 20:
+		odm_set_rf_reg(p_dm_odm, e_rf_path, REG_RF_TX_GAIN_OFFSET, BIT(14), 0);
+		odm_set_rf_reg(p_dm_odm, e_rf_path, REG_RF_TX_GAIN_OFFSET, BIT(17) | BIT(16) | BIT(15), 5);
+		p_rf_calibrate_info->kfree_offset[e_rf_path] = 5;
+		break;
+
+	default:
+		break;
+	}
+
+	if (is_odd == false) {
+		/*that means Kfree offset is negative, we need to record it.*/
+		p_rf_calibrate_info->kfree_offset[e_rf_path] = (-1) * p_rf_calibrate_info->kfree_offset[e_rf_path];
+		ODM_RT_TRACE(p_dm_odm, ODM_COMP_MP, ODM_DBG_LOUD, ("phy_ConfigKFree8814A(): kfree_offset = %d\n", p_rf_calibrate_info->kfree_offset[e_rf_path]));
+	} else
+		ODM_RT_TRACE(p_dm_odm, ODM_COMP_MP, ODM_DBG_LOUD, ("phy_ConfigKFree8814A(): kfree_offset = %d\n", p_rf_calibrate_info->kfree_offset[e_rf_path]));
+
+}
+
+
+
+void
+phydm_get_thermal_trim_offset_8821c(
+	void	*p_dm_void
+)
+{
+	struct PHY_DM_STRUCT		*p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
+	struct odm_power_trim_data	*p_power_trim_info = &(p_dm_odm->power_trim_data);
+
+	u8 pg_therm = 0xff;
+
+	odm_efuse_one_byte_read(p_dm_odm, PPG_THERMAL_OFFSET_8821C, &pg_therm, false);
+
+	if (pg_therm != 0xff) {
+		pg_therm = pg_therm & 0x1f;
+		if ((pg_therm & BIT0) == 0)
+			p_power_trim_info->thermal = (-1 * (pg_therm >> 1));
+		else
+			p_power_trim_info->thermal = (pg_therm >> 1);
+
+		p_power_trim_info->flag |= KFREE_FLAG_THERMAL_K_ON;
+	}
+
+	ODM_RT_TRACE(p_dm_odm, ODM_COMP_MP, ODM_DBG_LOUD, ("[kfree] power trim flag:0x%02x\n", p_power_trim_info->flag));
+
+	if (p_power_trim_info->flag & KFREE_FLAG_THERMAL_K_ON)
+		ODM_RT_TRACE(p_dm_odm, ODM_COMP_MP, ODM_DBG_LOUD, ("[kfree] thermal:%d\n", p_power_trim_info->thermal));
+}
+
+
+
+void
+phydm_get_power_trim_offset_8821c(
+	void	*p_dm_void
+)
+{
+	struct PHY_DM_STRUCT		*p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
+	struct odm_power_trim_data	*p_power_trim_info = &(p_dm_odm->power_trim_data);
+
+	u8 pg_power = 0xff, i;
+
+	odm_efuse_one_byte_read(p_dm_odm, PPG_BB_GAIN_2G_TXA_OFFSET_8821C, &pg_power, false);
+
+	if (pg_power != 0xff) {
+		p_power_trim_info->bb_gain[0][0] = pg_power;
+		odm_efuse_one_byte_read(p_dm_odm, PPG_BB_GAIN_5GL1_TXA_OFFSET_8821C, &pg_power, false);
+		p_power_trim_info->bb_gain[1][0] = pg_power;
+		odm_efuse_one_byte_read(p_dm_odm, PPG_BB_GAIN_5GL2_TXA_OFFSET_8821C, &pg_power, false);
+		p_power_trim_info->bb_gain[2][0] = pg_power;
+		odm_efuse_one_byte_read(p_dm_odm, PPG_BB_GAIN_5GM1_TXA_OFFSET_8821C, &pg_power, false);
+		p_power_trim_info->bb_gain[3][0] = pg_power;
+		odm_efuse_one_byte_read(p_dm_odm, PPG_BB_GAIN_5GM2_TXA_OFFSET_8821C, &pg_power, false);
+		p_power_trim_info->bb_gain[4][0] = pg_power;
+		odm_efuse_one_byte_read(p_dm_odm, PPG_BB_GAIN_5GH1_TXA_OFFSET_8821C, &pg_power, false);
+		p_power_trim_info->bb_gain[5][0] = pg_power;
+		p_power_trim_info->flag |= KFREE_FLAG_ON;
+	}
+
+	ODM_RT_TRACE(p_dm_odm, ODM_COMP_MP, ODM_DBG_LOUD, ("[kfree] power trim flag:0x%02x\n", p_power_trim_info->flag));
+
+	if (p_power_trim_info->flag & KFREE_FLAG_ON) {
+		for (i = 0; i < 6; i++)
+			ODM_RT_TRACE(p_dm_odm, ODM_COMP_MP, ODM_DBG_LOUD, ("[kfree]  power_trim_data->bb_gain[%d][0]=0x%X\n", i, p_power_trim_info->bb_gain[i][0]));
+	}
+}
+
+
+
+void
+phydm_set_kfree_to_rf_8821c(
+	void		*p_dm_void,
+	u8		e_rf_path,
+	boolean		wlg_btg,
+	u8		data
+)
+{
+	struct PHY_DM_STRUCT		*p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
+	struct odm_rf_calibration_structure	*p_rf_calibrate_info = &(p_dm_odm->rf_calibrate_info);
+	boolean is_odd;
+	u8	wlg, btg;
+
+	odm_set_rf_reg(p_dm_odm, e_rf_path, 0xde, BIT(0), 1);
+	odm_set_rf_reg(p_dm_odm, e_rf_path, 0xde, BIT(5), 1);
+	odm_set_rf_reg(p_dm_odm, e_rf_path, 0x55, BIT(6), 1);
+	odm_set_rf_reg(p_dm_odm, e_rf_path, 0x65, BIT(6), 1);
+
+	if (wlg_btg == true) {
+		wlg = data & 0xf;
+		btg = (data & 0xf0) >> 4;
+
+		odm_set_rf_reg(p_dm_odm, e_rf_path, 0x55, BIT(19), (wlg & BIT(0)));
+		odm_set_rf_reg(p_dm_odm, e_rf_path, 0x55, (BIT(18) | BIT(17) | BIT(16) | BIT(15) | BIT(14)), (wlg >> 1));
+
+		odm_set_rf_reg(p_dm_odm, e_rf_path, 0x65, BIT(19), (btg & BIT(0)));
+		odm_set_rf_reg(p_dm_odm, e_rf_path, 0x65, (BIT(18) | BIT(17) | BIT(16) | BIT(15) | BIT(14)), (btg >> 1));
+	} else {
+		odm_set_rf_reg(p_dm_odm, e_rf_path, 0x55, BIT(19), (data & BIT(0)));
+		odm_set_rf_reg(p_dm_odm, e_rf_path, 0x55, (BIT(18) | BIT(17) | BIT(16) | BIT(15) | BIT(14)), ((data & 0x1f) >> 1));
+	}
+
+	ODM_RT_TRACE(p_dm_odm, ODM_COMP_MP, ODM_DBG_LOUD,
+		("[kfree] 0x55[19:14]=0x%X 0x65[19:14]=0x%X\n",
+		odm_get_rf_reg(p_dm_odm, e_rf_path, 0x55, (BIT(19) | BIT(18) | BIT(17) | BIT(16) | BIT(15) | BIT(14))),
+		odm_get_rf_reg(p_dm_odm, e_rf_path, 0x65, (BIT(19) | BIT(18) | BIT(17) | BIT(16) | BIT(15) | BIT(14)))
+		));
+}
+
+void
+phydm_set_kfree_to_rf(
+	void		*p_dm_void,
+	u8		e_rf_path,
+	u8		data
+)
+{
+	struct PHY_DM_STRUCT	*p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
+
+	if (p_dm_odm->support_ic_type & ODM_RTL8814A)
+		phydm_set_kfree_to_rf_8814a(p_dm_odm, e_rf_path, data);
+
+	if ((p_dm_odm->support_ic_type & ODM_RTL8821C) && (*p_dm_odm->p_band_type == ODM_BAND_2_4G))
+		phydm_set_kfree_to_rf_8821c(p_dm_odm, e_rf_path, true, data);
+	else if (p_dm_odm->support_ic_type & ODM_RTL8821C)
+		phydm_set_kfree_to_rf_8821c(p_dm_odm, e_rf_path, false, data);
+}
+
+
+
+void
+phydm_get_thermal_trim_offset(
+	void	*p_dm_void
+)
+{
+	struct PHY_DM_STRUCT	*p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
+
+#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
+	struct _ADAPTER		*adapter = p_dm_odm->adapter;
+	HAL_DATA_TYPE	*p_hal_data = GET_HAL_DATA(adapter);
+	PEFUSE_HAL		pEfuseHal = &(p_hal_data->EfuseHal);
+	u1Byte			eFuseContent[DCMD_EFUSE_MAX_SECTION_NUM * EFUSE_MAX_WORD_UNIT * 2];
+
+	if (HAL_MAC_Dump_EFUSE(&GET_HAL_MAC_INFO(adapter), EFUSE_WIFI, eFuseContent, pEfuseHal->PhysicalLen_WiFi, HAL_MAC_EFUSE_PHYSICAL, HAL_MAC_EFUSE_PARSE_DRV) != RT_STATUS_SUCCESS)
+		ODM_RT_TRACE(p_dm_odm, ODM_COMP_MP, ODM_DBG_LOUD, ("[kfree] dump efuse fail !!!\n"));
+#endif
+
+	if (p_dm_odm->support_ic_type & ODM_RTL8821C)
+		phydm_get_thermal_trim_offset_8821c(p_dm_void);
+}
+
+
+
+void
+phydm_get_power_trim_offset(
+	void	*p_dm_void
+)
+{
+	struct PHY_DM_STRUCT	*p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
+
+#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
+	struct _ADAPTER		*adapter = p_dm_odm->adapter;
+	HAL_DATA_TYPE	*p_hal_data = GET_HAL_DATA(adapter);
+	PEFUSE_HAL		pEfuseHal = &(p_hal_data->EfuseHal);
+	u1Byte			eFuseContent[DCMD_EFUSE_MAX_SECTION_NUM * EFUSE_MAX_WORD_UNIT * 2];
+
+	if (HAL_MAC_Dump_EFUSE(&GET_HAL_MAC_INFO(adapter), EFUSE_WIFI, eFuseContent, pEfuseHal->PhysicalLen_WiFi, HAL_MAC_EFUSE_PHYSICAL, HAL_MAC_EFUSE_PARSE_DRV) != RT_STATUS_SUCCESS)
+		ODM_RT_TRACE(p_dm_odm, ODM_COMP_MP, ODM_DBG_LOUD, ("[kfree] dump efuse fail !!!\n"));
+#endif
+
+	if (p_dm_odm->support_ic_type & ODM_RTL8821C)
+		phydm_get_power_trim_offset_8821c(p_dm_void);
+}
+
+
+
+s8
+phydm_get_thermal_offset(
+	void	*p_dm_void
+)
+{
+	struct PHY_DM_STRUCT		*p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
+	struct odm_power_trim_data	*p_power_trim_info = &(p_dm_odm->power_trim_data);
+
+	if (p_power_trim_info->flag & KFREE_FLAG_THERMAL_K_ON)
+		return p_power_trim_info->thermal;
+	else
+		return 0;
+}
+
+
+
+void
+phydm_config_kfree(
+	void	*p_dm_void,
+	u8	channel_to_sw
+)
+{
+	struct PHY_DM_STRUCT		*p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
+	struct odm_rf_calibration_structure	*p_rf_calibrate_info = &(p_dm_odm->rf_calibrate_info);
+	struct odm_power_trim_data	*p_power_trim_info = &(p_dm_odm->power_trim_data);
+
+	u8			rfpath = 0, max_rf_path = 0;
+	u8			channel_idx = 0, i;
+
+	if (p_dm_odm->support_ic_type & ODM_RTL8814A)
+		max_rf_path = 4;	/*0~3*/
+	else if (p_dm_odm->support_ic_type & (ODM_RTL8812 | ODM_RTL8192E | ODM_RTL8822B))
+		max_rf_path = 2;	/*0~1*/
+	else if (p_dm_odm->support_ic_type & ODM_RTL8821C)
+		max_rf_path = 1;
+
+	ODM_RT_TRACE(p_dm_odm, ODM_COMP_MP, ODM_DBG_LOUD, ("===>[kfree] phy_ConfigKFree()\n"));
+
+	if (p_rf_calibrate_info->reg_rf_kfree_enable == 2) {
+		ODM_RT_TRACE(p_dm_odm, ODM_COMP_MP, ODM_DBG_LOUD, ("[kfree] phy_ConfigKFree(): reg_rf_kfree_enable == 2, Disable\n"));
+		return;
+	} else if (p_rf_calibrate_info->reg_rf_kfree_enable == 1 || p_rf_calibrate_info->reg_rf_kfree_enable == 0) {
+		ODM_RT_TRACE(p_dm_odm, ODM_COMP_MP, ODM_DBG_LOUD, ("[kfree] phy_ConfigKFree(): reg_rf_kfree_enable == true\n"));
+		/*Make sure the targetval is defined*/
+		if (p_power_trim_info->flag & KFREE_FLAG_ON) {
+			/*if kfree_table[0] == 0xff, means no Kfree*/
+			if (*p_dm_odm->p_band_type == ODM_BAND_2_4G) {
+				if (channel_to_sw >= 1 && channel_to_sw <= 14)
+					channel_idx = PHYDM_2G;
+			} else if (*p_dm_odm->p_band_type == ODM_BAND_5G) {
+				if (channel_to_sw >= 36 && channel_to_sw <= 48)
+					channel_idx = PHYDM_5GLB1;
+				if (channel_to_sw >= 52 && channel_to_sw <= 64)
+					channel_idx = PHYDM_5GLB2;
+				if (channel_to_sw >= 100 && channel_to_sw <= 120)
+					channel_idx = PHYDM_5GMB1;
+				if (channel_to_sw >= 122 && channel_to_sw <= 144)
+					channel_idx = PHYDM_5GMB2;
+				if (channel_to_sw >= 149 && channel_to_sw <= 177)
+					channel_idx = PHYDM_5GHB;
+			}
+
+			for (i = 0; i < (max_rf_path * BB_GAIN_NUM); i++)
+				ODM_RT_TRACE(p_dm_odm, ODM_COMP_MP, ODM_DBG_LOUD, ("[kfree] p_power_trim_info->bb_gain[%d][%d]=0x%X\n", i, max_rf_path - 1, p_power_trim_info->bb_gain[i][max_rf_path - 1]));
+
+			for (rfpath = ODM_RF_PATH_A;  rfpath < max_rf_path; rfpath++) {
+				ODM_RT_TRACE(p_dm_odm, ODM_COMP_MP, ODM_DBG_LOUD, ("[kfree] phydm_kfree(): channel_to_sw=%d PATH_%d: 0x%X\n", channel_to_sw, rfpath, p_power_trim_info->bb_gain[channel_idx][rfpath]));
+
+				phydm_set_kfree_to_rf(p_dm_odm, rfpath, p_power_trim_info->bb_gain[channel_idx][rfpath]);
+			}
+		} else {
+			ODM_RT_TRACE(p_dm_odm, ODM_COMP_MP, ODM_DBG_LOUD, ("[kfree] phy_ConfigKFree(): targetval not defined, Don't execute KFree Process.\n"));
+			return;
+		}
+	}
+	ODM_RT_TRACE(p_dm_odm, ODM_COMP_MP, ODM_DBG_LOUD, ("<===[kfree] phy_ConfigKFree()\n"));
+}
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/phydm_kfree.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/phydm_kfree.h
--- linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/phydm_kfree.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/phydm_kfree.h	2020-04-10 16:35:06.825660488 +0300
@@ -0,0 +1,87 @@
+
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
+ *
+ *
+ ******************************************************************************/
+
+#ifndef	__PHYDMKFREE_H__
+#define    __PHYDKFREE_H__
+
+#define KFREE_VERSION	"1.0"
+
+#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
+
+#define	BB_GAIN_NUM		6
+#define KFREE_FLAG_ON				BIT(0)
+#define KFREE_FLAG_THERMAL_K_ON		BIT(1)
+
+#endif
+
+#define PPG_BB_GAIN_2G_TXA_OFFSET_8821C		0x1EE
+#define PPG_BB_GAIN_5GL1_TXA_OFFSET_8821C		0x1EC
+#define PPG_BB_GAIN_5GL2_TXA_OFFSET_8821C		0x1E8
+#define PPG_BB_GAIN_5GM1_TXA_OFFSET_8821C		0x1E4
+#define PPG_BB_GAIN_5GM2_TXA_OFFSET_8821C		0x1E0
+#define PPG_BB_GAIN_5GH1_TXA_OFFSET_8821C		0x1DC
+
+#define PPG_THERMAL_OFFSET_8821C		0x1EF
+
+
+
+struct odm_power_trim_data {
+	u8 flag;
+	s8 bb_gain[BB_GAIN_NUM][MAX_RF_PATH];
+	s8 thermal;
+};
+
+
+
+enum phydm_kfree_channeltosw {
+	PHYDM_2G = 0,
+	PHYDM_5GLB1 = 1,
+	PHYDM_5GLB2 = 2,
+	PHYDM_5GMB1 = 3,
+	PHYDM_5GMB2 = 4,
+	PHYDM_5GHB = 5,
+};
+
+
+
+void
+phydm_get_thermal_trim_offset(
+	void	*p_dm_void
+);
+
+void
+phydm_get_power_trim_offset(
+	void	*p_dm_void
+);
+
+s8
+phydm_get_thermal_offset(
+	void	*p_dm_void
+);
+
+void
+phydm_config_kfree(
+	void	*p_dm_void,
+	u8	channel_to_sw
+);
+
+
+#endif
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/phydm_lna_sat.c linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/phydm_lna_sat.c
--- linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/phydm_lna_sat.c	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/phydm_lna_sat.c	2020-04-10 16:35:06.825660488 +0300
@@ -0,0 +1,1354 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017  Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * The full GNU General Public License is included in this distribution in the
+ * file called LICENSE.
+ *
+ * Contact Information:
+ * wlanfae <wlanfae@realtek.com>
+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
+ * Hsinchu 300, Taiwan.
+ *
+ * Larry Finger <Larry.Finger@lwfinger.net>
+ *
+ *****************************************************************************/
+
+/*************************************************************
+ * include files
+ * *************************************************************/
+#include "mp_precomp.h"
+#include "phydm_precomp.h"
+
+#ifdef PHYDM_LNA_SAT_CHK_SUPPORT
+
+#ifdef PHYDM_LNA_SAT_CHK_TYPE1
+void phydm_lna_sat_chk_init(
+	void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct phydm_lna_sat_t *lna_info = &dm->dm_lna_sat_info;
+
+	PHYDM_DBG(dm, DBG_LNA_SAT_CHK, "%s ==>\n", __func__);
+
+	lna_info->check_time = 0;
+	lna_info->sat_cnt_acc_patha = 0;
+	lna_info->sat_cnt_acc_pathb = 0;
+	#ifdef PHYDM_IC_ABOVE_3SS
+	lna_info->sat_cnt_acc_pathc = 0;
+	#endif
+	#ifdef PHYDM_IC_ABOVE_4SS
+	lna_info->sat_cnt_acc_pathd = 0;
+	#endif
+	lna_info->cur_sat_status = 0;
+	lna_info->pre_sat_status = 0;
+	lna_info->cur_timer_check_cnt = 0;
+	lna_info->pre_timer_check_cnt = 0;
+
+	#if (RTL8198F_SUPPORT || RTL8814B_SUPPORT)
+	if (dm->support_ic_type &
+	    (ODM_RTL8198F | ODM_RTL8814B))
+		phydm_lna_sat_chk_bb_init(dm);
+	#endif
+}
+
+#if (RTL8198F_SUPPORT || RTL8814B_SUPPORT)
+void phydm_lna_sat_chk_bb_init(void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct phydm_lna_sat_t *lna_info = &dm->dm_lna_sat_info;
+
+	boolean disable_bb_switch_tab = false;
+
+	PHYDM_DBG(dm, DBG_LNA_SAT_CHK, "%s ==>\n", __func__);
+
+	/*@set table switch mux r_6table_sel_anten*/
+	odm_set_bb_reg(dm, 0x18ac, BIT(8), 0);
+
+	/*@tab decision when idle*/
+	odm_set_bb_reg(dm, 0x18ac, BIT(16), disable_bb_switch_tab);
+	odm_set_bb_reg(dm, 0x41ac, BIT(16), disable_bb_switch_tab);
+	odm_set_bb_reg(dm, 0x52ac, BIT(16), disable_bb_switch_tab);
+	odm_set_bb_reg(dm, 0x53ac, BIT(16), disable_bb_switch_tab);
+	/*@tab decision when ofdmcca*/
+	odm_set_bb_reg(dm, 0x18ac, BIT(17), disable_bb_switch_tab);
+	odm_set_bb_reg(dm, 0x41ac, BIT(17), disable_bb_switch_tab);
+	odm_set_bb_reg(dm, 0x52ac, BIT(17), disable_bb_switch_tab);
+	odm_set_bb_reg(dm, 0x53ac, BIT(17), disable_bb_switch_tab);
+}
+
+void phydm_set_ofdm_agc_tab_path(
+	void *dm_void,
+	u8 tab_sel,
+	enum rf_path path)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+
+	PHYDM_DBG(dm, DBG_LNA_SAT_CHK, "%s ==>\n", __func__);
+	if (dm->support_ic_type & (ODM_RTL8198F | ODM_RTL8814B)) {
+		PHYDM_DBG(dm, DBG_LNA_SAT_CHK, "set AGC Tab%d\n", tab_sel);
+		PHYDM_DBG(dm, DBG_LNA_SAT_CHK, "r_6table_sel_anten = 0x%x\n",
+			  odm_get_bb_reg(dm, 0x18ac, BIT(8)));
+	}
+
+	if (dm->support_ic_type & ODM_RTL8198F) {
+		/*@table sel:0/2, mapping 2 to 1 */
+		if (tab_sel == OFDM_AGC_TAB_0) {
+			odm_set_bb_reg(dm, 0x18ac, BIT(4), 0);
+			odm_set_bb_reg(dm, 0x41ac, BIT(4), 0);
+			odm_set_bb_reg(dm, 0x52ac, BIT(4), 0);
+			odm_set_bb_reg(dm, 0x53ac, BIT(4), 0);
+		} else if (tab_sel == OFDM_AGC_TAB_2) {
+			odm_set_bb_reg(dm, 0x18ac, BIT(4), 1);
+			odm_set_bb_reg(dm, 0x41ac, BIT(4), 1);
+			odm_set_bb_reg(dm, 0x52ac, BIT(4), 1);
+			odm_set_bb_reg(dm, 0x53ac, BIT(4), 1);
+		} else {
+			odm_set_bb_reg(dm, 0x18ac, BIT(4), 0);
+			odm_set_bb_reg(dm, 0x41ac, BIT(4), 0);
+			odm_set_bb_reg(dm, 0x52ac, BIT(4), 0);
+			odm_set_bb_reg(dm, 0x53ac, BIT(4), 0);
+		}
+	} else if (dm->support_ic_type & ODM_RTL8814B) {
+		if (tab_sel == OFDM_AGC_TAB_0) {
+			odm_set_bb_reg(dm, 0x18ac, 0xf0, 0);
+			odm_set_bb_reg(dm, 0x41ac, 0xf0, 0);
+			odm_set_bb_reg(dm, 0x52ac, 0xf0, 0);
+			odm_set_bb_reg(dm, 0x53ac, 0xf0, 0);
+		} else if (tab_sel == OFDM_AGC_TAB_2) {
+			odm_set_bb_reg(dm, 0x18ac, 0xf0, 2);
+			odm_set_bb_reg(dm, 0x41ac, 0xf0, 2);
+			odm_set_bb_reg(dm, 0x52ac, 0xf0, 2);
+			odm_set_bb_reg(dm, 0x53ac, 0xf0, 2);
+		} else {
+			odm_set_bb_reg(dm, 0x18ac, 0xf0, 0);
+			odm_set_bb_reg(dm, 0x41ac, 0xf0, 0);
+			odm_set_bb_reg(dm, 0x52ac, 0xf0, 0);
+			odm_set_bb_reg(dm, 0x53ac, 0xf0, 0);
+		}
+	}
+}
+
+u8 phydm_get_ofdm_agc_tab_path(
+	void *dm_void,
+	enum rf_path path)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	u8 tab_sel = 0;
+
+	if (dm->support_ic_type & ODM_RTL8198F) {
+		tab_sel = (u8)odm_get_bb_reg(dm, R_0x18ac, BIT(4));
+		if (tab_sel == 0)
+			tab_sel = OFDM_AGC_TAB_0;
+		else if (tab_sel == 1)
+			tab_sel = OFDM_AGC_TAB_2;
+	} else if (dm->support_ic_type & ODM_RTL8814B) {
+		tab_sel = (u8)odm_get_bb_reg(dm, R_0x18ac, 0xf0);
+		if (tab_sel == 0)
+			tab_sel = OFDM_AGC_TAB_0;
+		else if (tab_sel == 2)
+			tab_sel = OFDM_AGC_TAB_2;
+	}
+	PHYDM_DBG(dm, DBG_LNA_SAT_CHK, "get path %d AGC Tab %d\n",
+		  path, tab_sel);
+	return tab_sel;
+}
+#endif /*@#if (RTL8198F_SUPPORT || RTL8814B_SUPPORT)*/
+
+void phydm_set_ofdm_agc_tab(
+	void *dm_void,
+	u8 tab_sel)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+
+	/*@table sel:0/2, 1 is used for CCK */
+	if (tab_sel == OFDM_AGC_TAB_0)
+		odm_set_bb_reg(dm, R_0xc70, 0x1e00, OFDM_AGC_TAB_0);
+	else if (tab_sel == OFDM_AGC_TAB_2)
+		odm_set_bb_reg(dm, R_0xc70, 0x1e00, OFDM_AGC_TAB_2);
+	else
+		odm_set_bb_reg(dm, R_0xc70, 0x1e00, OFDM_AGC_TAB_0);
+}
+
+u8 phydm_get_ofdm_agc_tab(
+	void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+
+	return (u8)odm_get_bb_reg(dm, R_0xc70, 0x1e00);
+}
+
+void phydm_lna_sat_chk(
+	void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
+	struct phydm_lna_sat_t *lna_info = &dm->dm_lna_sat_info;
+	u8 igi_rssi_min;
+	u8 rssi_min = dm->rssi_min;
+	u32 sat_status_a, sat_status_b;
+	#ifdef PHYDM_IC_ABOVE_3SS
+	u32 sat_status_c;
+	#endif
+	#ifdef PHYDM_IC_ABOVE_4SS
+	u32 sat_status_d;
+	#endif
+	u8 igi_restore = dig_t->cur_ig_value;
+	u8 i, chk_cnt = lna_info->chk_cnt;
+	u32 lna_sat_cnt_thd = 0;
+	u8 agc_tab;
+	u32 max_check_time = 0;
+	/*@use rssi_max if rssi_min is not stable;*/
+	/*@rssi_min = dm->rssi_max;*/
+
+	PHYDM_DBG(dm, DBG_LNA_SAT_CHK, "\n%s ==>\n", __func__);
+
+	if (!(dm->support_ability & ODM_BB_LNA_SAT_CHK)) {
+		PHYDM_DBG(dm, DBG_LNA_SAT_CHK, "Func disable\n");
+		return;
+	}
+
+	if (lna_info->is_disable_lna_sat_chk) {
+		phydm_lna_sat_chk_init(dm);
+		PHYDM_DBG(dm, DBG_LNA_SAT_CHK, "disable_lna_sat_chk\n");
+		return;
+	}
+
+	/*@move igi to target pin of rssi_min */
+	if (rssi_min == 0 || rssi_min == 0xff) {
+		PHYDM_DBG(dm, DBG_LNA_SAT_CHK,
+			  "rssi_min=%d, set AGC Tab0\n", rssi_min);
+		/*@adapt agc table 0*/
+		phydm_set_ofdm_agc_tab(dm, OFDM_AGC_TAB_0);
+		phydm_lna_sat_chk_init(dm);
+		return;
+	} else if (rssi_min % 2 != 0) {
+		igi_rssi_min = rssi_min + DIFF_RSSI_TO_IGI - 1;
+	} else {
+		igi_rssi_min = rssi_min + DIFF_RSSI_TO_IGI;
+	}
+
+	if ((lna_info->chk_period > 0) && (lna_info->chk_period <= ONE_SEC_MS))
+		max_check_time = chk_cnt * (ONE_SEC_MS / (lna_info->chk_period)) * 5;
+	else
+		max_check_time = chk_cnt * 5;
+
+	lna_sat_cnt_thd = (max_check_time * lna_info->chk_duty_cycle) / 100;
+
+	PHYDM_DBG(dm, DBG_LNA_SAT_CHK,
+		  "check_time=%d, rssi_min=%d, igi_rssi_min=0x%x\nchk_cnt=%d, chk_period=%d, max_check_time=%d, lna_sat_cnt_thd=%d\n",
+		  lna_info->check_time,
+		  rssi_min,
+		  igi_rssi_min,
+		  chk_cnt,
+		  lna_info->chk_period,
+		  max_check_time,
+		  lna_sat_cnt_thd);
+
+	odm_write_dig(dm, igi_rssi_min);
+
+	/*@adapt agc table 0 check saturation status*/
+	#if (RTL8198F_SUPPORT || RTL8814B_SUPPORT)
+	if (dm->support_ic_type & (ODM_RTL8198F | ODM_RTL8814B))
+		phydm_set_ofdm_agc_tab_path(dm, OFDM_AGC_TAB_0, RF_PATH_A);
+	else
+	#endif
+		phydm_set_ofdm_agc_tab(dm, OFDM_AGC_TAB_0);
+	/*@open rf power detection ckt & set detection range */
+	#if (RTL8198F_SUPPORT || RTL8814B_SUPPORT)
+	if (dm->support_ic_type & ODM_RTL8198F) {
+		/*@set rf detection range (threshold)*/
+		config_phydm_write_rf_reg_8198f(dm, RF_PATH_A, 0x85,
+						0x3f, 0x3f);
+		config_phydm_write_rf_reg_8198f(dm, RF_PATH_B, 0x85,
+						0x3f, 0x3f);
+		config_phydm_write_rf_reg_8198f(dm, RF_PATH_C, 0x85,
+						0x3f, 0x3f);
+		config_phydm_write_rf_reg_8198f(dm, RF_PATH_D, 0x85,
+						0x3f, 0x3f);
+		/*@open rf power detection ckt*/
+		config_phydm_write_rf_reg_8198f(dm, RF_PATH_A, 0x86, 0x10, 1);
+		config_phydm_write_rf_reg_8198f(dm, RF_PATH_B, 0x86, 0x10, 1);
+		config_phydm_write_rf_reg_8198f(dm, RF_PATH_C, 0x86, 0x10, 1);
+		config_phydm_write_rf_reg_8198f(dm, RF_PATH_D, 0x86, 0x10, 1);
+	} else if (dm->support_ic_type & ODM_RTL8814B) {
+		/*@set rf detection range (threshold)*/
+#if 0
+		config_phydm_write_rf_reg_8814b(dm, RF_PATH_A, 0x85,
+						0x3f, 0x3f);
+		config_phydm_write_rf_reg_8814b(dm, RF_PATH_B, 0x85,
+						0x3f, 0x3f);
+		config_phydm_write_rf_reg_8814b(dm, RF_PATH_C, 0x85,
+						0x3f, 0x3f);
+		config_phydm_write_rf_reg_8814b(dm, RF_PATH_D, 0x85,
+						0x3f, 0x3f);
+#endif
+		/*@open rf power detection ckt*/
+#if 0
+		config_phydm_write_rf_reg_8814b(dm, RF_PATH_A, 0x86, 0x10, 1);
+		config_phydm_write_rf_reg_8814b(dm, RF_PATH_B, 0x86, 0x10, 1);
+		config_phydm_write_rf_reg_8814b(dm, RF_PATH_C, 0x86, 0x10, 1);
+		config_phydm_write_rf_reg_8814b(dm, RF_PATH_D, 0x86, 0x10, 1);
+#endif
+	} else
+	#endif
+	{
+		odm_set_rf_reg(dm, RF_PATH_A, RF_0x86, 0x1f, 0x10);
+		odm_set_rf_reg(dm, RF_PATH_B, RF_0x86, 0x1f, 0x10);
+		#ifdef PHYDM_IC_ABOVE_3SS
+		odm_set_rf_reg(dm, RF_PATH_C, RF_0x86, 0x1f, 0x10);
+		#endif
+		#ifdef PHYDM_IC_ABOVE_4SS
+		odm_set_rf_reg(dm, RF_PATH_D, RF_0x86, 0x1f, 0x10);
+		#endif
+	}
+
+	/*@check saturation status*/
+	for (i = 0; i < chk_cnt; i++) {
+	#if (RTL8198F_SUPPORT || RTL8814B_SUPPORT)
+	if (dm->support_ic_type & ODM_RTL8198F) {
+		sat_status_a = config_phydm_read_rf_reg_8198f(dm, RF_PATH_A,
+							      RF_0xae,
+							      0xe0000);
+		sat_status_b = config_phydm_read_rf_reg_8198f(dm, RF_PATH_B,
+							      RF_0xae,
+							      0xe0000);
+		sat_status_c = config_phydm_read_rf_reg_8198f(dm, RF_PATH_C,
+							      RF_0xae,
+							      0xe0000);
+		sat_status_d = config_phydm_read_rf_reg_8198f(dm, RF_PATH_D,
+							      RF_0xae,
+							      0xe0000);
+	} else if (dm->support_ic_type & ODM_RTL8814B) {
+	/*@read peak detector info from 8814B rf reg*/
+#if 0
+		sat_status_a = config_phydm_read_rf_reg_8814b(dm, RF_PATH_A,
+							      RF_0xae,
+							      0xe0000);
+		sat_status_b = config_phydm_read_rf_reg_8814b(dm, RF_PATH_B,
+							      RF_0xae,
+							      0xe0000);
+		sat_status_c = config_phydm_read_rf_reg_8814b(dm, RF_PATH_C,
+							      RF_0xae,
+							      0xe0000);
+		sat_status_d = config_phydm_read_rf_reg_8814b(dm, RF_PATH_D,
+							      RF_0xae,
+							      0xe0000);
+#endif
+	} else
+	#endif
+	{
+		sat_status_a = odm_get_rf_reg(dm, RF_PATH_A, RF_0xae, 0xc0000);
+		sat_status_b = odm_get_rf_reg(dm, RF_PATH_B, RF_0xae, 0xc0000);
+		#ifdef PHYDM_IC_ABOVE_3SS
+		sat_status_c = odm_get_rf_reg(dm, RF_PATH_C, RF_0xae, 0xc0000);
+		#endif
+		#ifdef PHYDM_IC_ABOVE_4SS
+		sat_status_d = odm_get_rf_reg(dm, RF_PATH_D, RF_0xae, 0xc0000);
+		#endif
+	}
+
+		if (sat_status_a != 0)
+			lna_info->sat_cnt_acc_patha++;
+		if (sat_status_b != 0)
+			lna_info->sat_cnt_acc_pathb++;
+		#ifdef PHYDM_IC_ABOVE_3SS
+		if (sat_status_c != 0)
+			lna_info->sat_cnt_acc_pathc++;
+		#endif
+		#ifdef PHYDM_IC_ABOVE_4SS
+		if (sat_status_d != 0)
+			lna_info->sat_cnt_acc_pathd++;
+		#endif
+
+		if (lna_info->sat_cnt_acc_patha >= lna_sat_cnt_thd ||
+		    lna_info->sat_cnt_acc_pathb >= lna_sat_cnt_thd ||
+		    #ifdef PHYDM_IC_ABOVE_3SS
+		    lna_info->sat_cnt_acc_pathc >= lna_sat_cnt_thd ||
+		    #endif
+		    #ifdef PHYDM_IC_ABOVE_4SS
+		    lna_info->sat_cnt_acc_pathd >= lna_sat_cnt_thd ||
+		    #endif
+		    0) {
+			lna_info->cur_sat_status = 1;
+			PHYDM_DBG(dm, DBG_LNA_SAT_CHK,
+				  "cur_sat_status=%d, check_time=%d\n",
+				  lna_info->cur_sat_status,
+				  lna_info->check_time);
+			break;
+		}
+		lna_info->cur_sat_status = 0;
+	}
+
+	PHYDM_DBG(dm, DBG_LNA_SAT_CHK,
+		  "cur_sat_status=%d, pre_sat_status=%d, sat_cnt_acc_patha=%d, sat_cnt_acc_pathb=%d\n",
+		  lna_info->cur_sat_status,
+		  lna_info->pre_sat_status,
+		  lna_info->sat_cnt_acc_patha,
+		  lna_info->sat_cnt_acc_pathb);
+
+	#ifdef PHYDM_IC_ABOVE_4SS
+	PHYDM_DBG(dm, DBG_LNA_SAT_CHK,
+		  "cur_sat_status=%d, pre_sat_status=%d, sat_cnt_acc_pathc=%d, sat_cnt_acc_pathd=%d\n",
+		  lna_info->cur_sat_status,
+		  lna_info->pre_sat_status,
+		  lna_info->sat_cnt_acc_pathc,
+		  lna_info->sat_cnt_acc_pathd);
+	#endif
+	/*@agc table decision*/
+	if (lna_info->cur_sat_status) {
+		if (!lna_info->dis_agc_table_swh)
+			#if (RTL8198F_SUPPORT || RTL8814B_SUPPORT)
+			if (dm->support_ic_type & (ODM_RTL8198F | ODM_RTL8814B))
+				phydm_set_ofdm_agc_tab_path(dm,
+							    OFDM_AGC_TAB_2,
+							    RF_PATH_A);
+			else
+			#endif
+				phydm_set_ofdm_agc_tab(dm, OFDM_AGC_TAB_2);
+		else
+			PHYDM_DBG(dm, DBG_LNA_SAT_CHK,
+				  "disable set to AGC Tab%d\n", OFDM_AGC_TAB_2);
+		lna_info->check_time = 0;
+		lna_info->sat_cnt_acc_patha = 0;
+		lna_info->sat_cnt_acc_pathb = 0;
+		#ifdef PHYDM_IC_ABOVE_3SS
+		lna_info->sat_cnt_acc_pathc = 0;
+		#endif
+		#ifdef PHYDM_IC_ABOVE_4SS
+		lna_info->sat_cnt_acc_pathd = 0;
+		#endif
+		lna_info->pre_sat_status = lna_info->cur_sat_status;
+
+	} else if (lna_info->check_time <= (max_check_time - 1)) {
+		if (lna_info->pre_sat_status && !lna_info->dis_agc_table_swh)
+			#if (RTL8198F_SUPPORT || RTL8814B_SUPPORT)
+			if (dm->support_ic_type & (ODM_RTL8198F | ODM_RTL8814B))
+				phydm_set_ofdm_agc_tab_path(dm,
+							    OFDM_AGC_TAB_2,
+							    RF_PATH_A);
+			else
+			#endif
+				phydm_set_ofdm_agc_tab(dm, OFDM_AGC_TAB_2);
+
+		PHYDM_DBG(dm, DBG_LNA_SAT_CHK, "ckeck time not reached\n");
+		if (lna_info->dis_agc_table_swh)
+			PHYDM_DBG(dm, DBG_LNA_SAT_CHK,
+				  "disable set to AGC Tab%d\n", OFDM_AGC_TAB_2);
+		lna_info->check_time++;
+
+	} else if (lna_info->check_time >= max_check_time) {
+		if (!lna_info->dis_agc_table_swh)
+			#if (RTL8198F_SUPPORT || RTL8814B_SUPPORT)
+			if (dm->support_ic_type & (ODM_RTL8198F | ODM_RTL8814B))
+				phydm_set_ofdm_agc_tab_path(dm,
+							    OFDM_AGC_TAB_0,
+							    RF_PATH_A);
+			else
+			#endif
+				phydm_set_ofdm_agc_tab(dm, OFDM_AGC_TAB_0);
+
+		PHYDM_DBG(dm, DBG_LNA_SAT_CHK, "ckeck time reached\n");
+		if (lna_info->dis_agc_table_swh)
+			PHYDM_DBG(dm, DBG_LNA_SAT_CHK,
+				  "disable set to AGC Tab%d\n", OFDM_AGC_TAB_0);
+		lna_info->check_time = 0;
+		lna_info->sat_cnt_acc_patha = 0;
+		lna_info->sat_cnt_acc_pathb = 0;
+		#ifdef PHYDM_IC_ABOVE_3SS
+		lna_info->sat_cnt_acc_pathc = 0;
+		#endif
+		#ifdef PHYDM_IC_ABOVE_4SS
+		lna_info->sat_cnt_acc_pathd = 0;
+		#endif
+		lna_info->pre_sat_status = lna_info->cur_sat_status;
+	}
+
+	#if (RTL8198F_SUPPORT || RTL8814B_SUPPORT)
+	if (dm->support_ic_type & (ODM_RTL8198F | ODM_RTL8814B))
+		agc_tab = phydm_get_ofdm_agc_tab_path(dm, RF_PATH_A);
+	else
+	#endif
+		agc_tab = phydm_get_ofdm_agc_tab(dm);
+
+	PHYDM_DBG(dm, DBG_LNA_SAT_CHK, "use AGC tab %d\n", agc_tab);
+
+	/*@restore previous igi*/
+	odm_write_dig(dm, igi_restore);
+	lna_info->cur_timer_check_cnt++;
+	odm_set_timer(dm, &lna_info->phydm_lna_sat_chk_timer,
+		      lna_info->chk_period);
+}
+
+void phydm_lna_sat_chk_callback(
+	void *dm_void
+
+	)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+
+	PHYDM_DBG(dm, DBG_LNA_SAT_CHK, "\n%s ==>\n", __func__);
+	phydm_lna_sat_chk(dm);
+}
+
+void phydm_lna_sat_chk_timers(
+	void *dm_void,
+	u8 state)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct phydm_lna_sat_t *lna_info = &dm->dm_lna_sat_info;
+
+	if (state == INIT_LNA_SAT_CHK_TIMMER) {
+		odm_initialize_timer(dm,
+				     &lna_info->phydm_lna_sat_chk_timer,
+				     (void *)phydm_lna_sat_chk_callback, NULL,
+				     "phydm_lna_sat_chk_timer");
+	} else if (state == CANCEL_LNA_SAT_CHK_TIMMER) {
+		odm_cancel_timer(dm, &lna_info->phydm_lna_sat_chk_timer);
+	} else if (state == RELEASE_LNA_SAT_CHK_TIMMER) {
+		odm_release_timer(dm, &lna_info->phydm_lna_sat_chk_timer);
+	}
+}
+
+void phydm_lna_sat_chk_watchdog_type1(
+	void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct phydm_lna_sat_t *lna_info = &dm->dm_lna_sat_info;
+
+	u8 rssi_min = dm->rssi_min;
+
+	PHYDM_DBG(dm, DBG_LNA_SAT_CHK, "\n%s ==>\n", __func__);
+
+	if (!(dm->support_ability & ODM_BB_LNA_SAT_CHK)) {
+		PHYDM_DBG(dm, DBG_LNA_SAT_CHK,
+			  "func disable\n");
+		return;
+	}
+
+	PHYDM_DBG(dm, DBG_LNA_SAT_CHK,
+		  "pre_timer_check_cnt=%d, cur_timer_check_cnt=%d\n",
+		  lna_info->pre_timer_check_cnt,
+		  lna_info->cur_timer_check_cnt);
+
+	if (lna_info->is_disable_lna_sat_chk) {
+		phydm_lna_sat_chk_init(dm);
+		PHYDM_DBG(dm, DBG_LNA_SAT_CHK,
+			  "is_disable_lna_sat_chk=%d, return\n",
+			  lna_info->is_disable_lna_sat_chk);
+		return;
+	}
+
+	if (!(dm->support_ic_type &
+	    (ODM_RTL8197F | ODM_RTL8198F | ODM_RTL8814B))) {
+		PHYDM_DBG(dm, DBG_LNA_SAT_CHK,
+			  "support_ic_type not 97F/98F/14B, return\n");
+		return;
+	}
+
+	if (rssi_min == 0 || rssi_min == 0xff) {
+		/*@adapt agc table 0 */
+		phydm_set_ofdm_agc_tab(dm, OFDM_AGC_TAB_0);
+		phydm_lna_sat_chk_init(dm);
+		PHYDM_DBG(dm, DBG_LNA_SAT_CHK,
+			  "rssi_min=%d, return\n", rssi_min);
+		return;
+	}
+
+	if (lna_info->cur_timer_check_cnt == lna_info->pre_timer_check_cnt) {
+		PHYDM_DBG(dm, DBG_LNA_SAT_CHK, "fail, restart timer\n");
+		odm_set_timer(dm, &lna_info->phydm_lna_sat_chk_timer,
+			      lna_info->chk_period);
+	} else {
+		PHYDM_DBG(dm, DBG_LNA_SAT_CHK, "Timer check pass\n");
+	}
+	lna_info->pre_timer_check_cnt = lna_info->cur_timer_check_cnt;
+}
+
+#endif /*@#ifdef PHYDM_LNA_SAT_CHK_TYPE1*/
+
+#ifdef PHYDM_LNA_SAT_CHK_TYPE2
+
+void phydm_bubble_sort(
+	void *dm_void,
+	u8 *array,
+	u16 array_length)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	u16 i, j;
+	u8 temp;
+
+	PHYDM_DBG(dm, DBG_LNA_SAT_CHK, "%s ==>\n", __func__);
+	for (i = 0; i < (array_length - 1); i++) {
+		for (j = (i + 1); j < (array_length); j++) {
+			if (array[i] > array[j]) {
+				temp = array[i];
+				array[i] = array[j];
+				array[j] = temp;
+			}
+		}
+	}
+}
+
+void phydm_lna_sat_chk_type2_init(
+	void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct phydm_lna_sat_t	*pinfo = &dm->dm_lna_sat_info;
+	u8 real_shift = pinfo->total_bit_shift;
+
+	PHYDM_DBG(dm, DBG_LNA_SAT_CHK, "%s ==>\n", __func__);
+
+	pinfo->total_cnt_snr = 1 << real_shift;
+	pinfo->is_sm_done = TRUE;
+	pinfo->is_snr_done = FALSE;
+	pinfo->cur_snr_mean = 0;
+	pinfo->cur_snr_var = 0;
+	pinfo->cur_lower_snr_mean = 0;
+	pinfo->pre_snr_mean = 0;
+	pinfo->pre_snr_var = 0;
+	pinfo->pre_lower_snr_mean = 0;
+	pinfo->nxt_state = ORI_TABLE_MONITOR;
+	pinfo->pre_state = ORI_TABLE_MONITOR;
+}
+
+void phydm_snr_collect(
+	void *dm_void,
+	u8 rx_snr)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct phydm_lna_sat_t	*pinfo = &dm->dm_lna_sat_info;
+
+	if (pinfo->is_sm_done) {
+#if 0
+		/*PHYDM_DBG(dm, DBG_LNA_SAT_CHK, "%s ==>\n", __func__);*/
+#endif
+
+		/* @adapt only path-A for calculation */
+		pinfo->snr_statistic[pinfo->cnt_snr_statistic] = rx_snr;
+
+		if (pinfo->cnt_snr_statistic == (pinfo->total_cnt_snr - 1)) {
+			pinfo->is_snr_done = TRUE;
+			pinfo->cnt_snr_statistic = 0;
+		} else {
+			pinfo->cnt_snr_statistic++;
+		}
+	} else {
+		return;
+	}
+}
+
+void phydm_parsing_snr(void *dm_void, void *pktinfo_void, s8 *rx_snr)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct phydm_lna_sat_t	*lna_t = &dm->dm_lna_sat_info;
+	struct phydm_perpkt_info_struct *pktinfo = NULL;
+	u8 target_macid = dm->rssi_min_macid;
+
+	if (!(dm->support_ability & ODM_BB_LNA_SAT_CHK))
+		return;
+
+	pktinfo = (struct phydm_perpkt_info_struct *)pktinfo_void;
+
+	if (!pktinfo->is_packet_match_bssid)
+		return;
+
+	if (lna_t->force_traget_macid != 0)
+		target_macid = lna_t->force_traget_macid;
+
+	if (target_macid != pktinfo->station_id)
+		return;
+
+	phydm_snr_collect(dm, rx_snr[0]); /*path-A B C D???*/
+}
+
+void phydm_snr_data_processing(
+	void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct phydm_lna_sat_t	*pinfo = &dm->dm_lna_sat_info;
+	u8 real_shift = pinfo->total_bit_shift;
+	u16 total_snr_cnt = pinfo->total_cnt_snr;
+	u16 total_loop_cnt = (total_snr_cnt - 1), i;
+	u32 temp;
+	u32 sum_snr_statistic = 0;
+
+	PHYDM_DBG(dm, DBG_LNA_SAT_CHK, "%s ==>\n", __func__);
+	PHYDM_DBG(dm, DBG_LNA_SAT_CHK,
+		  "total_loop_cnt=%d\n", total_loop_cnt);
+
+	for (i = 0; (i <= total_loop_cnt); i++) {
+		if (pinfo->is_snr_detail_en) {
+			PHYDM_DBG(dm, DBG_LNA_SAT_CHK,
+				  "snr[%d]=%d\n", i, pinfo->snr_statistic[i]);
+		}
+
+		sum_snr_statistic += (u32)(pinfo->snr_statistic[i]);
+
+		pinfo->snr_statistic_sqr[i] = (u16)(pinfo->snr_statistic[i] * pinfo->snr_statistic[i]);
+	}
+
+	phydm_bubble_sort(dm, pinfo->snr_statistic, pinfo->total_cnt_snr);
+
+	/*update SNR's cur mean*/
+	pinfo->cur_snr_mean = (sum_snr_statistic >> real_shift);
+
+	for (i = 0; (i <= total_loop_cnt); i++) {
+		if (pinfo->snr_statistic[i] >= pinfo->cur_snr_mean)
+			temp = pinfo->snr_statistic[i] - pinfo->cur_snr_mean;
+		else
+			temp = pinfo->cur_snr_mean - pinfo->snr_statistic[i];
+
+		pinfo->cur_snr_var += (temp * temp);
+	}
+
+	/*update SNR's VAR*/
+	pinfo->cur_snr_var = (pinfo->cur_snr_var >> real_shift);
+
+	/*@acquire lower SNR's statistics*/
+	temp = 0;
+	pinfo->cnt_lower_snr_statistic = (total_snr_cnt >> pinfo->lwr_snr_ratio_bit_shift);
+	pinfo->cnt_lower_snr_statistic = MAX_2(pinfo->cnt_lower_snr_statistic, SNR_RPT_MAX);
+
+	for (i = 0; i < pinfo->cnt_lower_snr_statistic; i++)
+		temp += pinfo->snr_statistic[i];
+
+	pinfo->cur_lower_snr_mean = temp >> (real_shift - pinfo->lwr_snr_ratio_bit_shift);
+}
+
+boolean phydm_is_snr_improve(
+	void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct phydm_lna_sat_t	*pinfo = &dm->dm_lna_sat_info;
+	boolean is_snr_improve;
+	u8 cur_state = pinfo->nxt_state;
+	u32 cur_mean = pinfo->cur_snr_mean;
+	u32 pre_mean = pinfo->pre_snr_mean;
+	u32 cur_lower_mean = pinfo->cur_lower_snr_mean;
+	u32 pre_lower_mean = pinfo->pre_lower_snr_mean;
+	u32 cur_var = pinfo->cur_snr_var;
+
+	/*special case, zero VAR, interference is gone*/
+	 /*@make sure pre_var is larger enough*/
+	if (cur_state == SAT_TABLE_MONITOR ||
+	    cur_state == ORI_TABLE_TRAINING) {
+		if (cur_mean >= pre_mean) {
+			if (cur_var == 0)
+				return true;
+		}
+	}
+#if 0
+	/*special case, mean degrade less than VAR improvement*/
+	/*@make sure pre_var is larger enough*/
+	if (cur_state == ORI_TABLE_MONITOR &&
+	    cur_mean < pre_mean &&
+	    cur_var < pre_var) {
+		diff_mean = pre_mean - cur_mean;
+		diff_var = pre_var - cur_var;
+		return (diff_var > (2 * diff_mean * diff_mean)) ? true : false;
+	}
+
+#endif
+	if (cur_lower_mean >= (pre_lower_mean + pinfo->delta_snr_mean))
+		is_snr_improve = true;
+	else
+		is_snr_improve = false;
+#if 0
+/* @condition refine, mean is bigger enough or VAR is smaller enough*/
+/* @1. from mean's view, mean improve delta_snr_mean(2), VAR not degrade lot*/
+	if (cur_mean > (pre_mean + pinfo->delta_snr_mean)) {
+		is_mean_improve = TRUE;
+		is_var_improve = (cur_var <= pre_var + dm->delta_snr_var)
+				 ? TRUE : FALSE;
+
+	} else if (cur_var + dm->delta_snr_var <= pre_var) {
+		is_var_improve = TRUE;
+		is_mean_improve = ((cur_mean + 1) >= pre_mean) ? TRUE : FALSE;
+	} else {
+		return false;
+	}
+#endif
+	return is_snr_improve;
+}
+
+boolean phydm_is_snr_degrade(
+	void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct phydm_lna_sat_t	*pinfo = &dm->dm_lna_sat_info;
+	u32 cur_lower_mean = pinfo->cur_lower_snr_mean;
+	u32 pre_lower_mean = pinfo->pre_lower_snr_mean;
+	boolean is_degrade;
+
+	if (cur_lower_mean <= (pre_lower_mean - pinfo->delta_snr_mean))
+		is_degrade = TRUE;
+	else
+		is_degrade = FALSE;
+#if 0
+	is_mean_dgrade = (pinfo->cur_snr_mean + pinfo->delta_snr_mean <= pinfo->pre_snr_mean) ? TRUE : FALSE;
+	is_var_degrade = (pinfo->cur_snr_var > (pinfo->pre_snr_var + pinfo->delta_snr_mean)) ? TRUE : FALSE;
+
+	PHYDM_DBG(dm, DBG_LNA_SAT_CHK, "%s: cur_mean=%d, pre_mean=%d, cur_var=%d, pre_var=%d\n",
+		  __func__,
+		  pinfo->cur_snr_mean,
+		  pinfo->pre_snr_mean,
+		  pinfo->cur_snr_var,
+		  pinfo->pre_snr_var);
+
+	return (is_mean_dgrade & is_var_degrade);
+#endif
+	return is_degrade;
+}
+
+boolean phydm_is_large_var(
+	void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct phydm_lna_sat_t	*pinfo = &dm->dm_lna_sat_info;
+	boolean is_large_var = (pinfo->cur_snr_var >= pinfo->snr_var_thd) ? TRUE : FALSE;
+
+	return is_large_var;
+}
+
+void phydm_update_pre_status(
+	void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct phydm_lna_sat_t	*pinfo = &dm->dm_lna_sat_info;
+
+	pinfo->pre_lower_snr_mean = pinfo->cur_lower_snr_mean;
+	pinfo->pre_snr_mean = pinfo->cur_snr_mean;
+	pinfo->pre_snr_var = pinfo->cur_snr_var;
+}
+
+void phydm_ori_table_monitor(
+	void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct phydm_lna_sat_t	*pinfo = &dm->dm_lna_sat_info;
+
+	if (phydm_is_large_var(dm)) {
+		pinfo->nxt_state = SAT_TABLE_TRAINING;
+		config_phydm_switch_agc_tab_8822b(dm, *dm->channel, LNA_SAT_AGC_TABLE);
+	} else {
+		pinfo->nxt_state = ORI_TABLE_MONITOR;
+		/*switch to anti-sat table*/
+		config_phydm_switch_agc_tab_8822b(dm, *dm->channel, DEFAULT_AGC_TABLE);
+	}
+	phydm_update_pre_status(dm);
+	pinfo->pre_state = ORI_TABLE_MONITOR;
+}
+
+void phydm_sat_table_training(
+	void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct phydm_lna_sat_t	*pinfo = &dm->dm_lna_sat_info;
+
+	#if 0
+	if pre_state = ORI_TABLE_MONITOR || SAT_TABLE_TRY_FAIL,
+	/*@"pre" adapt ori-table, "cur" adapt sat-table*/
+	/*@adapt ori table*/
+	if (pinfo->pre_state == ORI_TABLE_MONITOR) {
+		pinfo->nxt_state = SAT_TABLE_TRAINING;
+		config_phydm_switch_agc_tab_8822b(dm, *dm->channel, LNA_SAT_AGC_TABLE);
+	} else {
+	#endif
+	if (phydm_is_snr_improve(dm)) {
+		pinfo->nxt_state = SAT_TABLE_MONITOR;
+	} else {
+		pinfo->nxt_state = SAT_TABLE_TRY_FAIL;
+		config_phydm_switch_agc_tab_8822b(dm, *dm->channel, DEFAULT_AGC_TABLE);
+	}
+	/*@}*/
+
+	phydm_update_pre_status(dm);
+	pinfo->pre_state = SAT_TABLE_TRAINING;
+}
+
+void phydm_sat_table_try_fail(
+	void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct phydm_lna_sat_t	*pinfo = &dm->dm_lna_sat_info;
+
+	/* @if pre_state = SAT_TABLE_TRAINING, "pre" adapt sat-table, "cur" adapt ori-table */
+	/* @if pre_state = SAT_TABLE_TRY_FAIL, "pre" adapt ori-table, "cur" adapt ori-table */
+
+	if (phydm_is_large_var(dm)) {
+		if (phydm_is_snr_degrade(dm)) {
+			pinfo->nxt_state = SAT_TABLE_TRAINING;
+			config_phydm_switch_agc_tab_8822b(dm, *dm->channel, LNA_SAT_AGC_TABLE);
+		} else {
+			pinfo->nxt_state = SAT_TABLE_TRY_FAIL;
+		}
+	} else {
+		pinfo->nxt_state = ORI_TABLE_MONITOR;
+	}
+	phydm_update_pre_status(dm);
+	pinfo->pre_state = SAT_TABLE_TRY_FAIL;
+}
+
+void phydm_sat_table_monitor(
+	void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct phydm_lna_sat_t	*pinfo = &dm->dm_lna_sat_info;
+
+	if (phydm_is_snr_improve(dm)) {
+		pinfo->sat_table_monitor_times = 0;
+
+		/* @if pre_state = SAT_TABLE_MONITOR, "pre" adapt sat-table, "cur" adapt sat-table */
+		if (pinfo->pre_state == SAT_TABLE_MONITOR) {
+			pinfo->nxt_state = ORI_TABLE_TRAINING;
+			config_phydm_switch_agc_tab_8822b(dm, *dm->channel, DEFAULT_AGC_TABLE);
+			//phydm_update_pre_status(dm);
+		} else {
+			pinfo->nxt_state = SAT_TABLE_MONITOR;
+		}
+
+		/* @if pre_state = SAT_TABLE_TRAINING, "pre" adapt sat-table, "cur" adapt sat-table */
+		/* @if pre_state = ORI_TABLE_TRAINING, "pre" adapt ori-table, "cur" adapt sat-table */
+		/*pre_state above is no need to update*/
+	} else {
+		if (pinfo->sat_table_monitor_times == pinfo->force_change_period) {
+			PHYDM_DBG(dm, DBG_LNA_SAT_CHK, "%s: sat_table_monitor_times=%d\n",
+				  __func__, pinfo->sat_table_monitor_times);
+
+			pinfo->nxt_state = ORI_TABLE_TRAINING;
+			pinfo->sat_table_monitor_times = 0;
+			config_phydm_switch_agc_tab_8822b(dm, *dm->channel, DEFAULT_AGC_TABLE);
+		} else {
+			pinfo->nxt_state = SAT_TABLE_MONITOR;
+			pinfo->sat_table_monitor_times++;
+		}
+	}
+	phydm_update_pre_status(dm);
+	pinfo->pre_state = SAT_TABLE_MONITOR;
+}
+
+void phydm_ori_table_training(
+	void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct phydm_lna_sat_t	*pinfo = &dm->dm_lna_sat_info;
+
+	/* pre_state = SAT_TABLE_MONITOR, "pre" adapt sat-table, "cur" adapt ori-table */
+
+	if (phydm_is_snr_degrade(dm) == FALSE) {
+		pinfo->nxt_state = ORI_TABLE_MONITOR;
+	} else {
+		if (pinfo->pre_snr_var == 0)
+			pinfo->nxt_state = ORI_TABLE_TRY_FAIL;
+		else
+			pinfo->nxt_state = SAT_TABLE_MONITOR;
+
+		config_phydm_switch_agc_tab_8822b(dm, *dm->channel, LNA_SAT_AGC_TABLE);
+	}
+	phydm_update_pre_status(dm);
+	pinfo->pre_state = ORI_TABLE_TRAINING;
+}
+
+void phydm_ori_table_try_fail(
+	void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct phydm_lna_sat_t	*pinfo = &dm->dm_lna_sat_info;
+
+	if (pinfo->pre_state == ORI_TABLE_TRY_FAIL) {
+		if (phydm_is_snr_improve(dm)) {
+			pinfo->nxt_state = ORI_TABLE_TRAINING;
+			pinfo->ori_table_try_fail_times = 0;
+			config_phydm_switch_agc_tab_8822b(dm, *dm->channel, DEFAULT_AGC_TABLE);
+		} else {
+			if (pinfo->ori_table_try_fail_times == pinfo->force_change_period) {
+				PHYDM_DBG(dm, DBG_LNA_SAT_CHK,
+					  "%s: ori_table_try_fail_times=%d\n", __func__, pinfo->ori_table_try_fail_times);
+
+				pinfo->nxt_state = ORI_TABLE_TRY_FAIL;
+				pinfo->ori_table_try_fail_times = 0;
+				phydm_update_pre_status(dm);
+			} else {
+				pinfo->nxt_state = ORI_TABLE_TRY_FAIL;
+				pinfo->ori_table_try_fail_times++;
+				phydm_update_pre_status(dm);
+				//config_phydm_switch_agc_tab_8822b(dm, *dm->channel, LNA_SAT_AGC_TABLE);
+			}
+		}
+	} else {
+		pinfo->nxt_state = ORI_TABLE_TRY_FAIL;
+		pinfo->ori_table_try_fail_times = 0;
+		phydm_update_pre_status(dm);
+		//config_phydm_switch_agc_tab_8822b(dm, *dm->channel, LNA_SAT_AGC_TABLE);
+	}
+
+#if 0
+	if (phydm_is_large_var(dm)) {
+		if (phydm_is_snr_degrade(dm)) {
+			pinfo->nxt_state = SAT_TABLE_TRAINING;
+			config_phydm_switch_agc_tab_8822b(dm, *dm->channel, LNA_SAT_AGC_TABLE);
+		} else {
+			pinfo->nxt_state = SAT_TABLE_TRY_FAIL;
+		}
+	} else {
+		pinfo->nxt_state = ORI_TABLE_MONITOR;
+	}
+
+	phydm_update_pre_status(dm);
+#endif
+	pinfo->pre_state = ORI_TABLE_TRY_FAIL;
+}
+
+char *phydm_lna_sat_state_msg(
+	void *dm_void,
+	IN u8 state)
+{
+	char *dbg_message;
+
+	switch (state) {
+	case ORI_TABLE_MONITOR:
+		dbg_message = "ORI_TABLE_MONITOR";
+		break;
+
+	case SAT_TABLE_TRAINING:
+		dbg_message = "SAT_TABLE_TRAINING";
+		break;
+
+	case SAT_TABLE_TRY_FAIL:
+		dbg_message = "SAT_TABLE_TRY_FAIL";
+		break;
+
+	case SAT_TABLE_MONITOR:
+		dbg_message = "SAT_TABLE_MONITOR";
+		break;
+
+	case ORI_TABLE_TRAINING:
+		dbg_message = "ORI_TABLE_TRAINING";
+		break;
+
+	case ORI_TABLE_TRY_FAIL:
+		dbg_message = "ORI_TABLE_TRY_FAIL";
+		break;
+
+	default:
+		dbg_message = "ORI_TABLE_MONITOR";
+		break;
+	}
+
+	return dbg_message;
+}
+
+void phydm_lna_sat_type2_sm(
+	void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct phydm_lna_sat_t	*pinfo = &dm->dm_lna_sat_info;
+	u8 state = pinfo->nxt_state;
+	u8 agc_tab = (u8)odm_get_bb_reg(dm, 0x958, 0x1f);
+	char *dbg_message, *nxt_dbg_message;
+	u8 real_shift = pinfo->total_bit_shift;
+
+	PHYDM_DBG(dm, DBG_LNA_SAT_CHK, "\n\n%s ==>\n", __func__);
+
+	if ((dm->support_ic_type & ODM_RTL8822B) == FALSE) {
+		PHYDM_DBG(dm, DBG_LNA_SAT_CHK, "ODM_BB_LNA_SAT_CHK_TYPE2 only support 22B.\n");
+		return;
+	}
+
+	if ((dm->support_ability & ODM_BB_LNA_SAT_CHK) == FALSE) {
+		phydm_lna_sat_chk_type2_init(dm);
+		PHYDM_DBG(dm, DBG_LNA_SAT_CHK, "ODM_BB_LNA_SAT_CHK_TYPE2 is NOT supported, cur table=%d\n", agc_tab);
+		return;
+	}
+
+	if (pinfo->is_snr_done)
+		phydm_snr_data_processing(dm);
+	else
+		return;
+
+	PHYDM_DBG(dm, DBG_LNA_SAT_CHK, "cur agc table %d\n", agc_tab);
+
+	if (pinfo->is_force_lna_sat_table != AUTO_AGC_TABLE) {
+		/*reset state machine*/
+		pinfo->nxt_state = ORI_TABLE_MONITOR;
+		if (pinfo->is_snr_done) {
+			if (pinfo->is_force_lna_sat_table == DEFAULT_AGC_TABLE)
+				config_phydm_switch_agc_tab_8822b(dm, *dm->channel, DEFAULT_AGC_TABLE);
+			else if (pinfo->is_force_lna_sat_table == LNA_SAT_AGC_TABLE)
+				config_phydm_switch_agc_tab_8822b(dm, *dm->channel, LNA_SAT_AGC_TABLE);
+			else
+				config_phydm_switch_agc_tab_8822b(dm, *dm->channel, DEFAULT_AGC_TABLE);
+
+			PHYDM_DBG(dm, DBG_LNA_SAT_CHK,
+				  "%s: cur_mean=%d, pre_mean=%d, cur_var=%d, pre_var=%d,cur_lower_mean=%d, pre_lower_mean=%d, cnt_lower_snr=%d\n",
+				  __func__,
+				  pinfo->cur_snr_mean,
+				  pinfo->pre_snr_mean,
+				  pinfo->cur_snr_var,
+				  pinfo->pre_snr_var,
+				  pinfo->cur_lower_snr_mean,
+				  pinfo->pre_lower_snr_mean,
+				  pinfo->cnt_lower_snr_statistic);
+
+			pinfo->is_snr_done = FALSE;
+			pinfo->is_sm_done = TRUE;
+			phydm_update_pre_status(dm);
+		} else {
+			return;
+		}
+	} else if (pinfo->is_snr_done) {
+		PHYDM_DBG(dm, DBG_LNA_SAT_CHK,
+			  "%s: cur_mean=%d, pre_mean=%d, cur_var=%d, pre_var=%d,cur_lower_mean=%d, pre_lower_mean=%d, cnt_lower_snr=%d\n",
+			  __func__,
+			  pinfo->cur_snr_mean,
+			  pinfo->pre_snr_mean,
+			  pinfo->cur_snr_var,
+			  pinfo->pre_snr_var,
+			  pinfo->cur_lower_snr_mean,
+			  pinfo->pre_lower_snr_mean,
+			  pinfo->cnt_lower_snr_statistic);
+
+		switch (state) {
+		case ORI_TABLE_MONITOR:
+			dbg_message = "ORI_TABLE_MONITOR";
+			phydm_ori_table_monitor(dm);
+			break;
+
+		case SAT_TABLE_TRAINING:
+			dbg_message = "SAT_TABLE_TRAINING";
+			phydm_sat_table_training(dm);
+			break;
+
+		case SAT_TABLE_TRY_FAIL:
+			dbg_message = "SAT_TABLE_TRY_FAIL";
+			phydm_sat_table_try_fail(dm);
+			break;
+
+		case SAT_TABLE_MONITOR:
+			dbg_message = "SAT_TABLE_MONITOR";
+			phydm_sat_table_monitor(dm);
+			break;
+
+		case ORI_TABLE_TRAINING:
+			dbg_message = "ORI_TABLE_TRAINING";
+			phydm_ori_table_training(dm);
+			break;
+
+		case ORI_TABLE_TRY_FAIL:
+			dbg_message = "ORI_TABLE_TRAINING";
+			phydm_ori_table_try_fail(dm);
+			break;
+
+		default:
+			dbg_message = "ORI_TABLE_MONITOR";
+			phydm_ori_table_monitor(dm);
+			break;
+		}
+
+		dbg_message = phydm_lna_sat_state_msg(dm, state);
+		nxt_dbg_message = phydm_lna_sat_state_msg(dm, pinfo->nxt_state);
+		PHYDM_DBG(dm, DBG_LNA_SAT_CHK, "state: [%s]->[%s]\n",
+			  dbg_message, nxt_dbg_message);
+
+		pinfo->is_snr_done = FALSE;
+		pinfo->is_sm_done = TRUE;
+		pinfo->total_cnt_snr = 1 << real_shift;
+
+	} else {
+		return;
+	}
+}
+
+
+#endif /*@#ifdef PHYDM_LNA_SAT_CHK_TYPE2*/
+
+void phydm_lna_sat_debug(
+	void *dm_void,
+	char input[][16],
+	u32 *_used,
+	char *output,
+	u32 *_out_len)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct phydm_lna_sat_t	*lna_t = &dm->dm_lna_sat_info;
+	char help[] = "-h";
+	char monitor[] = "-m";
+	u32 var1[10] = {0};
+	u32 used = *_used;
+	u32 out_len = *_out_len;
+	u8 i;
+	u8 agc_tab = 0;
+
+	if ((strcmp(input[1], help) == 0)) {
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "help content:\n");
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "monitor: -m\n");
+		#ifdef PHYDM_LNA_SAT_CHK_TYPE1
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "{0} {lna_sat_chk_en}\n");
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "{1} {agc_table_switch_en}\n");
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "{2} {chk_cnt per callback}\n");
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "{3} {chk_period(ms)}\n");
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "{4} {chk_duty_cycle(percentage)}\n");
+		#endif
+	} else if ((strcmp(input[1], monitor) == 0)) {
+#ifdef PHYDM_LNA_SAT_CHK_TYPE1
+		#if (RTL8198F_SUPPORT || RTL8814B_SUPPORT)
+		if (dm->support_ic_type & (ODM_RTL8198F | ODM_RTL8814B))
+			agc_tab = phydm_get_ofdm_agc_tab_path(dm, RF_PATH_A);
+		else
+		#endif
+			agc_tab = phydm_get_ofdm_agc_tab(dm);
+
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "%s%d, %s%d, %s%d, %s%d\n",
+			 "check_time = ", lna_t->check_time,
+			 "pre_sat_status = ", lna_t->pre_sat_status,
+			 "cur_sat_status = ", lna_t->cur_sat_status,
+			 "current AGC tab = ", agc_tab);
+#endif
+	} else {
+		PHYDM_SSCANF(input[1], DCMD_DECIMAL, &var1[0]);
+
+		for (i = 1; i < 10; i++) {
+			if (input[i + 1])
+				PHYDM_SSCANF(input[i + 1], DCMD_DECIMAL,
+					     &var1[i]);
+		}
+		#ifdef PHYDM_LNA_SAT_CHK_TYPE1
+		if (var1[0] == 0) {
+			if (var1[1] == 1) {
+				lna_t->is_disable_lna_sat_chk = false;
+				PDM_SNPF(out_len, used, output + used,
+					 out_len - used,
+					 "enable lna_sat_chk\n");
+			} else if (var1[1] == 0) {
+				lna_t->is_disable_lna_sat_chk = true;
+				PDM_SNPF(out_len, used, output + used,
+					 out_len - used,
+					 "disable lna_sat_chk\n");
+			}
+		} else if (var1[0] == 1) {
+			if (var1[1] == 1) {
+				lna_t->dis_agc_table_swh = false;
+				PDM_SNPF(out_len, used, output + used,
+					 out_len - used,
+					 "enable agc_table_switch\n");
+			} else if (var1[1] == 0) {
+				lna_t->dis_agc_table_swh = true;
+				PDM_SNPF(out_len, used, output + used,
+					 out_len - used,
+					 "disable agc_table_switch\n");
+			}
+		} else if (var1[0] == 2) {
+			lna_t->chk_cnt = (u8)var1[1];
+			PDM_SNPF(out_len, used, output + used, out_len - used,
+				 "set chk_cnt to %d\n", lna_t->chk_cnt);
+		} else if (var1[0] == 3) {
+			lna_t->chk_period = var1[1];
+			PDM_SNPF(out_len, used, output + used, out_len - used,
+				 "set chk_period to %d\n", lna_t->chk_period);
+		} else if (var1[0] == 4) {
+			lna_t->chk_duty_cycle = (u8)var1[1];
+			PDM_SNPF(out_len, used, output + used, out_len - used,
+				 "set chk_duty_cycle to %d\n",
+				 lna_t->chk_duty_cycle);
+		}
+		#endif
+		#ifdef PHYDM_LNA_SAT_CHK_TYPE2
+		if (var1[0] == 1)
+			lna_t->force_traget_macid = var1[1];
+		#endif
+	}
+	*_used = used;
+	*_out_len = out_len;
+}
+
+void phydm_lna_sat_chk_watchdog(
+	void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct phydm_lna_sat_t *lna_sat = &dm->dm_lna_sat_info;
+
+	PHYDM_DBG(dm, DBG_LNA_SAT_CHK, "%s ==>\n", __func__);
+
+	if (lna_sat->lna_sat_type == LNA_SAT_WITH_PEAK_DET) {
+		#ifdef PHYDM_LNA_SAT_CHK_TYPE1
+		phydm_lna_sat_chk_watchdog_type1(dm);
+		#endif
+	} else if (lna_sat->lna_sat_type == LNA_SAT_WITH_TRAIN) {
+		#ifdef PHYDM_LNA_SAT_CHK_TYPE2
+
+		#endif
+	}
+
+}
+
+void phydm_lna_sat_config(
+	void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct phydm_lna_sat_t	*lna_sat = &dm->dm_lna_sat_info;
+
+	#if (RTL8822B_SUPPORT == 1)
+	if (dm->support_ic_type & (ODM_RTL8822B))
+		lna_sat->lna_sat_type = LNA_SAT_WITH_TRAIN;
+	#endif
+
+	#if (RTL8197F_SUPPORT || RTL8192F_SUPPORT ||\
+	     RTL8198F_SUPPORT || RTL8814B_SUPPORT)
+	if (dm->support_ic_type &
+	    (ODM_RTL8197F | ODM_RTL8192F | ODM_RTL8198F | ODM_RTL8814B))
+		lna_sat->lna_sat_type = LNA_SAT_WITH_PEAK_DET;
+	#endif
+
+	PHYDM_DBG(dm, DBG_LNA_SAT_CHK, "[%s] lna_sat_type=%d\n",
+		  __func__, lna_sat->lna_sat_type);
+}
+
+void phydm_lna_sat_check_init(
+	void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct phydm_lna_sat_t	*lna_sat = &dm->dm_lna_sat_info;
+
+	if ((dm->support_ability & ODM_BB_LNA_SAT_CHK))
+		return;
+
+	/*@2018.04.17 Johnson*/
+	phydm_lna_sat_config(dm);
+	#ifdef PHYDM_LNA_SAT_CHK_TYPE1
+	lna_sat->chk_period = LNA_CHK_PERIOD;
+	lna_sat->chk_cnt = LNA_CHK_CNT;
+	lna_sat->chk_duty_cycle = LNA_CHK_DUTY_CYCLE;
+	lna_sat->dis_agc_table_swh = false;
+	#endif
+	/*@2018.04.17 Johnson end*/
+
+	if (lna_sat->lna_sat_type == LNA_SAT_WITH_PEAK_DET) {
+		#ifdef PHYDM_LNA_SAT_CHK_TYPE1
+		phydm_lna_sat_chk_init(dm);
+		#endif
+	} else if (lna_sat->lna_sat_type == LNA_SAT_WITH_TRAIN) {
+		#ifdef PHYDM_LNA_SAT_CHK_TYPE2
+		phydm_lna_sat_chk_type2_init(dm);
+		#endif
+	}
+}
+
+#endif /*@#ifdef PHYDM_LNA_SAT_CHK_SUPPORT*/
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/phydm_lna_sat.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/phydm_lna_sat.h
--- linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/phydm_lna_sat.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/phydm_lna_sat.h	2020-04-10 16:35:06.825660488 +0300
@@ -0,0 +1,173 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017  Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * The full GNU General Public License is included in this distribution in the
+ * file called LICENSE.
+ *
+ * Contact Information:
+ * wlanfae <wlanfae@realtek.com>
+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
+ * Hsinchu 300, Taiwan.
+ *
+ * Larry Finger <Larry.Finger@lwfinger.net>
+ *
+ *****************************************************************************/
+
+#ifndef __PHYDM_LNA_SAT_H__
+#define __PHYDM_LNA_SAT_H__
+#ifdef PHYDM_LNA_SAT_CHK_SUPPORT
+/* @1 ============================================================
+ * 1  Definition
+ * 1 ============================================================
+ */
+
+#define LNA_SAT_VERSION "1.0"
+
+/*@LNA saturation check*/
+#define	OFDM_AGC_TAB_0			0
+#define	OFDM_AGC_TAB_2			2
+
+#define	DIFF_RSSI_TO_IGI		10
+#define	ONE_SEC_MS			1000
+
+#define LNA_CHK_PERIOD			100 /*@ms*/
+#define LNA_CHK_CNT			10 /*@checks per callback*/
+#define LNA_CHK_DUTY_CYCLE		5 /*@percentage*/
+
+#define	DELTA_STD	2
+#define	DELTA_MEAN	2
+#define	SNR_STATISTIC_SHIFT	8
+#define	SNR_RPT_MAX	256
+
+/* @1 ============================================================
+ * 1 enumrate
+ * 1 ============================================================
+ */
+
+enum lna_sat_timer_state {
+	INIT_LNA_SAT_CHK_TIMMER,
+	CANCEL_LNA_SAT_CHK_TIMMER,
+	RELEASE_LNA_SAT_CHK_TIMMER
+};
+
+#ifdef PHYDM_LNA_SAT_CHK_TYPE2
+enum lna_sat_chk_type2_status {
+	ORI_TABLE_MONITOR,
+	ORI_TABLE_TRAINING,
+	SAT_TABLE_MONITOR,
+	SAT_TABLE_TRAINING,
+	SAT_TABLE_TRY_FAIL,
+	ORI_TABLE_TRY_FAIL
+};
+
+#endif
+
+enum lna_sat_type {
+	LNA_SAT_WITH_PEAK_DET	= 1,	/*type1*/
+	LNA_SAT_WITH_TRAIN	= 2,	/*type2*/
+};
+
+/* @1 ============================================================
+ * 1  structure
+ * 1 ============================================================
+ */
+
+struct phydm_lna_sat_t {
+#ifdef PHYDM_LNA_SAT_CHK_TYPE1
+	u8			chk_cnt;
+	u8			chk_duty_cycle;
+	u32			chk_period;/*@ms*/
+	boolean			is_disable_lna_sat_chk;
+	boolean			dis_agc_table_swh;
+#endif
+#ifdef PHYDM_LNA_SAT_CHK_TYPE2
+	u8			force_traget_macid;
+	u32			snr_var_thd;
+	u32			delta_snr_mean;
+	u16			ori_table_try_fail_times;
+	u16			cnt_lower_snr_statistic;
+	u16			sat_table_monitor_times;
+	u16			force_change_period;
+	u8			is_snr_detail_en;
+	u8			is_force_lna_sat_table;
+	u8			lwr_snr_ratio_bit_shift;
+	u8			cnt_snr_statistic;
+	u16			snr_statistic_sqr[SNR_RPT_MAX];
+	u8			snr_statistic[SNR_RPT_MAX];
+	u8			is_sm_done;
+	u8			is_snr_done;
+	u32			cur_snr_var;
+	u8			total_bit_shift;
+	u8			total_cnt_snr;
+	u32			cur_snr_mean;
+	u8			cur_snr_var0;
+	u32			cur_lower_snr_mean;
+	u32			pre_snr_mean;
+	u32			pre_snr_var;
+	u32			pre_lower_snr_mean;
+	u8			nxt_state;
+	u8			pre_state;
+#endif
+	enum lna_sat_type	lna_sat_type;
+	u32			sat_cnt_acc_patha;
+	u32			sat_cnt_acc_pathb;
+#ifdef PHYDM_IC_ABOVE_3SS
+	u32			sat_cnt_acc_pathc;
+#endif
+#ifdef PHYDM_IC_ABOVE_4SS
+	u32			sat_cnt_acc_pathd;
+#endif
+	u32			check_time;
+	boolean			pre_sat_status;
+	boolean			cur_sat_status;
+	struct phydm_timer_list	phydm_lna_sat_chk_timer;
+	u32			cur_timer_check_cnt;
+	u32			pre_timer_check_cnt;
+};
+
+/* @1 ============================================================
+ * 1 function prototype
+ * 1 ============================================================
+ */
+void phydm_lna_sat_chk_init(void *dm_void);
+
+u8 phydm_get_ofdm_agc_tab(void *dm_void);
+
+void phydm_lna_sat_chk(void *dm_void);
+
+void phydm_lna_sat_chk_timers(void *dm_void, u8 state);
+
+#ifdef PHYDM_LNA_SAT_CHK_TYPE1
+#if (RTL8198F_SUPPORT || RTL8814B_SUPPORT)
+void phydm_lna_sat_chk_bb_init(void *dm_void);
+
+void phydm_set_ofdm_agc_tab_path(void *dm_void,
+				 u8 tab_sel, enum rf_path path);
+
+u8 phydm_get_ofdm_agc_tab_path(void *dm_void, enum rf_path path);
+#endif /*@#if (RTL8198F_SUPPORT || RTL8814B_SUPPORT)*/
+#endif
+
+#ifdef PHYDM_LNA_SAT_CHK_TYPE2
+void phydm_parsing_snr(void *dm_void, void *pktinfo_void, s8 *rx_snr);
+#endif
+
+void phydm_lna_sat_debug(void *dm_void, char input[][16], u32 *_used,
+			 char *output, u32 *_out_len);
+
+void phydm_lna_sat_chk_watchdog(void *dm_void);
+
+void phydm_lna_sat_check_init(void *dm_void);
+
+#endif /*@#if (PHYDM_LNA_SAT_CHK_SUPPORT == 1)*/
+#endif
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/phydm_math_lib.c linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/phydm_math_lib.c
--- linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/phydm_math_lib.c	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/phydm_math_lib.c	2020-04-10 16:35:06.825660488 +0300
@@ -0,0 +1,211 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017  Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * The full GNU General Public License is included in this distribution in the
+ * file called LICENSE.
+ *
+ * Contact Information:
+ * wlanfae <wlanfae@realtek.com>
+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
+ * Hsinchu 300, Taiwan.
+ *
+ * Larry Finger <Larry.Finger@lwfinger.net>
+ *
+ *****************************************************************************/
+
+/*@************************************************************
+ * include files
+ ************************************************************/
+
+#include "mp_precomp.h"
+#include "phydm_precomp.h"
+
+const u16 db_invert_table[12][8] = {
+	{1, 1, 1, 2, 2, 2, 2, 3},
+	{3, 3, 4, 4, 4, 5, 6, 6},
+	{7, 8, 9, 10, 11, 13, 14, 16},
+	{18, 20, 22, 25, 28, 32, 35, 40},
+	{45, 50, 56, 63, 71, 79, 89, 100},
+	{112, 126, 141, 158, 178, 200, 224, 251},
+	{282, 316, 355, 398, 447, 501, 562, 631},
+	{708, 794, 891, 1000, 1122, 1259, 1413, 1585},
+	{1778, 1995, 2239, 2512, 2818, 3162, 3548, 3981},
+	{4467, 5012, 5623, 6310, 7079, 7943, 8913, 10000},
+	{11220, 12589, 14125, 15849, 17783, 19953, 22387, 25119},
+	{28184, 31623, 35481, 39811, 44668, 50119, 56234, 65535} };
+
+/*Y = 10*log(X)*/
+s32 odm_pwdb_conversion(s32 X, u32 total_bit, u32 decimal_bit)
+{
+	s32 Y, integer = 0, decimal = 0;
+	u32 i;
+
+	if (X == 0)
+		X = 1; /* @log2(x), x can't be 0 */
+
+	for (i = (total_bit - 1); i > 0; i--) {
+		if (X & BIT(i)) {
+			integer = i;
+			if (i > 0) {
+				/*decimal is 0.5dB*3=1.5dB~=2dB */
+				decimal = (X & BIT(i - 1)) ? 2 : 0;
+			}
+			break;
+		}
+	}
+
+	Y = 3 * (integer - decimal_bit) + decimal; /* @10*log(x)=3*log2(x), */
+
+	return Y;
+}
+
+s32 odm_sign_conversion(s32 value, u32 total_bit)
+{
+	if (value & BIT(total_bit - 1))
+		value -= BIT(total_bit);
+
+	return value;
+}
+
+/*threshold must form low to high*/
+u16 phydm_find_intrvl(void *dm_void, u16 val, u16 *threshold, u16 th_len)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	u16 i = 0;
+	u16 ret_val = 0;
+	u16 max_th = threshold[th_len - 1];
+
+	for (i = 0; i < th_len; i++) {
+		if (val < threshold[i]) {
+			ret_val = i;
+			break;
+		} else if (val >= max_th) {
+			ret_val = th_len;
+			break;
+		}
+	}
+
+	return ret_val;
+}
+
+void phydm_seq_sorting(void *dm_void, u32 *value, u32 *rank_idx, u32 *idx_out,
+		       u8 seq_length)
+{
+	u8 i = 0, j = 0;
+	u32 tmp_a, tmp_b;
+	u32 tmp_idx_a, tmp_idx_b;
+
+	for (i = 0; i < seq_length; i++)
+		rank_idx[i] = i;
+
+	for (i = 0; i < (seq_length - 1); i++) {
+		for (j = 0; j < (seq_length - 1 - i); j++) {
+			tmp_a = value[j];
+			tmp_b = value[j + 1];
+
+			tmp_idx_a = rank_idx[j];
+			tmp_idx_b = rank_idx[j + 1];
+
+			if (tmp_a < tmp_b) {
+				value[j] = tmp_b;
+				value[j + 1] = tmp_a;
+
+				rank_idx[j] = tmp_idx_b;
+				rank_idx[j + 1] = tmp_idx_a;
+			}
+		}
+	}
+
+	for (i = 0; i < seq_length; i++)
+		idx_out[rank_idx[i]] = i + 1;
+}
+
+u32 odm_convert_to_db(u32 value)
+{
+	u8 i;
+	u8 j;
+	u32 dB;
+
+	value = value & 0xFFFF;
+
+	for (i = 0; i < 12; i++) {
+		if (value <= db_invert_table[i][7])
+			break;
+	}
+
+	if (i >= 12)
+		return 96; /* @maximum 96 dB */
+
+	for (j = 0; j < 8; j++) {
+		if (value <= db_invert_table[i][j])
+			break;
+	}
+
+	dB = (i << 3) + j + 1;
+
+	return dB;
+}
+
+u32 phydm_db_2_linear(u32 value)
+{
+	u8 i;
+	u8 j;
+	u32 linear;
+
+	/* @1dB~96dB */
+
+	value = value & 0xFF;
+
+	i = (u8)((value - 1) >> 3);
+	j = (u8)(value - 1) - (i << 3);
+
+	linear = db_invert_table[i][j];
+
+	return linear;
+}
+
+u16 phydm_show_fraction_num(u32 frac_val, u8 bit_num)
+{
+	u8 i = 0;
+	u16 val = 0;
+	u16 base = 5000;
+
+	for (i = bit_num; i > 0; i--) {
+		if (frac_val & BIT(i - 1))
+			val += (base >> (bit_num - i));
+	}
+	return val;
+}
+
+u32 phydm_gen_bitmask(u8 mask_num)
+{
+	u8 i = 0;
+	u32 bitmask = 0;
+
+	if (mask_num > 32)
+		return 1;
+
+	for (i = 0; i < mask_num; i++)
+		bitmask = (bitmask << 1) | BIT(0);
+
+	return bitmask;
+}
+
+s32 phydm_cnvrt_2_sign(u32 val, u8 bit_num)
+{
+	if (val & BIT(bit_num - 1)) /*Sign BIT*/
+		val -= (1 << bit_num); /*@2's*/
+
+	return val;
+}
+
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/phydm_math_lib.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/phydm_math_lib.h
--- linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/phydm_math_lib.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/phydm_math_lib.h	2020-04-10 16:35:06.825660488 +0300
@@ -0,0 +1,114 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017  Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * The full GNU General Public License is included in this distribution in the
+ * file called LICENSE.
+ *
+ * Contact Information:
+ * wlanfae <wlanfae@realtek.com>
+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
+ * Hsinchu 300, Taiwan.
+ *
+ * Larry Finger <Larry.Finger@lwfinger.net>
+ *
+ *****************************************************************************/
+
+#ifndef __PHYDM_MATH_LIB_H__
+#define __PHYDM_MATH_LIB_H__
+
+#define AUTO_MATH_LIB_VERSION "1.0" /* @2017.06.06*/
+
+/*@
+ * 1 ============================================================
+ * 1  Definition
+ * 1 ============================================================
+ */
+
+#define DIVIDED_2(X) ((X) >> 1)
+/*@1/3 ~ 11/32*/
+#if defined(DM_ODM_CE_MAC80211)
+#define DIVIDED_3(X) ({	\
+	u32 div_3_tmp = (X);	\
+	(((div_3_tmp) + ((div_3_tmp) << 1) + ((div_3_tmp) << 3)) >> 5); })
+#else
+#define DIVIDED_3(X) (((X) + ((X) << 1) + ((X) << 3)) >> 5)
+#endif
+#define DIVIDED_4(X) ((X) >> 2)
+
+/*Store Ori Value*/
+#if defined(DM_ODM_CE_MAC80211)
+#define WEIGHTING_AVG(v1, w1, v2, w2)	\
+	__WEIGHTING_AVG(v1, w1, v2, w2, typeof(v1), typeof(w1), typeof(v2), \
+			typeof(w2))
+#define __WEIGHTING_AVG(v1, w1, v2, w2, t1, t2, t3, t4)	({	\
+	t1 __w_a_v1 = (v1);	\
+	t2 __w_a_w1 = (w1);	\
+	t3 __w_a_v2 = (v2);	\
+	t4 __w_a_w2 = (w2);	\
+	((__w_a_v1) * (__w_a_w1) + (__w_a_v2) * (__w_a_w2))	\
+	/ ((__w_a_w2) + (__w_a_w1)); })
+#else
+#define WEIGHTING_AVG(v1, w1, v2, w2) \
+	(((v1) * (w1) + (v2) * (w2)) / ((w2) + (w1)))
+#endif
+
+/*Store 2^ma x Value*/
+#if defined(DM_ODM_CE_MAC80211)
+#define MA_ACC(old, new_val, ma) ({	\
+	s16 __ma_acc_o = (old);		\
+	(__ma_acc_o) - ((__ma_acc_o) >> (ma)) + (new_val); })
+#define GET_MA_VAL(val, ma) ({	\
+	s16 __get_ma_tmp = (ma);\
+	((val) + (1 << ((__get_ma_tmp) - 1))) >> (__get_ma_tmp); })
+#else
+#define MA_ACC(old, new_val, ma) ((old) - ((old) >> (ma)) + (new_val))
+#define GET_MA_VAL(val, ma) (((val) + (1 << ((ma) - 1))) >> (ma))
+#endif
+
+/*@
+ * 1 ============================================================
+ * 1  enumeration
+ * 1 ============================================================
+ */
+
+/*@
+ * 1 ============================================================
+ * 1  structure
+ * 1 ============================================================
+ */
+
+/*@
+ * 1 ============================================================
+ * 1  function prototype
+ * 1 ============================================================
+ */
+
+s32 odm_pwdb_conversion(s32 X, u32 total_bit, u32 decimal_bit);
+
+s32 odm_sign_conversion(s32 value, u32 total_bit);
+
+u16 phydm_find_intrvl(void *dm_void, u16 val, u16 *threshold, u16 th_len);
+
+void phydm_seq_sorting(void *dm_void, u32 *value, u32 *rank_idx, u32 *idx_out,
+		       u8 seq_length);
+
+u32 odm_convert_to_db(u32 value);
+
+u32 phydm_db_2_linear(u32 value);
+
+u16 phydm_show_fraction_num(u32 frac_val, u8 bit_num);
+
+u32 phydm_gen_bitmask(u8 mask_num);
+
+s32 phydm_cnvrt_2_sign(u32 val, u8 bit_num);
+#endif
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/phydm.mk linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/phydm.mk
--- linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/phydm.mk	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/phydm.mk	2020-04-10 16:35:06.821660301 +0300
@@ -0,0 +1,217 @@
+EXTRA_CFLAGS += -I$(TopDIR)/hal/phydm
+
+_PHYDM_FILES := hal/phydm/phydm_debug.o	\
+								hal/phydm/phydm_antdiv.o\
+								hal/phydm/phydm_soml.o\
+								hal/phydm/phydm_smt_ant.o\
+								hal/phydm/phydm_antdect.o\
+								hal/phydm/phydm_interface.o\
+								hal/phydm/phydm_phystatus.o\
+								hal/phydm/phydm_hwconfig.o\
+								hal/phydm/phydm.o\
+								hal/phydm/phydm_dig.o\
+								hal/phydm/phydm_pathdiv.o\
+								hal/phydm/phydm_rainfo.o\
+								hal/phydm/phydm_dynamictxpower.o\
+								hal/phydm/phydm_adaptivity.o\
+								hal/phydm/phydm_cfotracking.o\
+								hal/phydm/phydm_noisemonitor.o\
+								hal/phydm/phydm_beamforming.o\
+								hal/phydm/phydm_dfs.o\
+								hal/phydm/txbf/halcomtxbf.o\
+								hal/phydm/txbf/haltxbfinterface.o\
+								hal/phydm/txbf/phydm_hal_txbf_api.o\
+								hal/phydm/phydm_adc_sampling.o\
+								hal/phydm/phydm_ccx.o\
+								hal/phydm/phydm_psd.o\
+								hal/phydm/phydm_primary_cca.o\
+								hal/phydm/phydm_cck_pd.o\
+								hal/phydm/phydm_rssi_monitor.o\
+								hal/phydm/phydm_auto_dbg.o\
+								hal/phydm/phydm_math_lib.o\
+								hal/phydm/phydm_api.o\
+								hal/phydm/phydm_pow_train.o\
+								hal/phydm/phydm_lna_sat.o\
+								hal/phydm/phydm_pmac_tx_setting.o\
+								hal/phydm/phydm_mp.o\
+								hal/phydm/halrf/halrf.o\
+								hal/phydm/halrf/halrf_debug.o\
+								hal/phydm/halrf/halphyrf_ce.o\
+								hal/phydm/halrf/halrf_powertracking_ce.o\
+								hal/phydm/halrf/halrf_powertracking.o\
+								hal/phydm/halrf/halrf_kfree.o
+
+ifeq ($(CONFIG_RTL8188E), y)
+RTL871X = rtl8188e
+_PHYDM_FILES += hal/phydm/$(RTL871X)/halhwimg8188e_mac.o\
+								hal/phydm/$(RTL871X)/halhwimg8188e_bb.o\
+								hal/phydm/$(RTL871X)/halhwimg8188e_rf.o\
+								hal/phydm/halrf/$(RTL871X)/halrf_8188e_ce.o\
+								hal/phydm/$(RTL871X)/phydm_regconfig8188e.o\
+								hal/phydm/$(RTL871X)/hal8188erateadaptive.o\
+								hal/phydm/$(RTL871X)/phydm_rtl8188e.o
+endif
+
+ifeq ($(CONFIG_RTL8192E), y)
+RTL871X = rtl8192e
+_PHYDM_FILES += hal/phydm/$(RTL871X)/halhwimg8192e_mac.o\
+								hal/phydm/$(RTL871X)/halhwimg8192e_bb.o\
+								hal/phydm/$(RTL871X)/halhwimg8192e_rf.o\
+								hal/phydm/halrf/$(RTL871X)/halrf_8192e_ce.o\
+								hal/phydm/$(RTL871X)/phydm_regconfig8192e.o\
+								hal/phydm/$(RTL871X)/phydm_rtl8192e.o
+endif
+
+
+ifeq ($(CONFIG_RTL8812A), y)
+RTL871X = rtl8812a
+_PHYDM_FILES += hal/phydm/$(RTL871X)/halhwimg8812a_mac.o\
+								hal/phydm/$(RTL871X)/halhwimg8812a_bb.o\
+								hal/phydm/$(RTL871X)/halhwimg8812a_rf.o\
+								hal/phydm/halrf/$(RTL871X)/halrf_8812a_ce.o\
+								hal/phydm/$(RTL871X)/phydm_regconfig8812a.o\
+								hal/phydm/$(RTL871X)/phydm_rtl8812a.o\
+								hal/phydm/txbf/haltxbfjaguar.o
+endif
+
+ifeq ($(CONFIG_RTL8821A), y)
+RTL871X = rtl8821a
+_PHYDM_FILES += hal/phydm/rtl8821a/halhwimg8821a_mac.o\
+								hal/phydm/rtl8821a/halhwimg8821a_bb.o\
+								hal/phydm/rtl8821a/halhwimg8821a_rf.o\
+								hal/phydm/halrf/rtl8812a/halrf_8812a_ce.o\
+								hal/phydm/halrf/rtl8821a/halrf_8821a_ce.o\
+								hal/phydm/rtl8821a/phydm_regconfig8821a.o\
+								hal/phydm/rtl8821a/phydm_rtl8821a.o\
+								hal/phydm/halrf/rtl8821a/halrf_iqk_8821a_ce.o\
+								hal/phydm/txbf/haltxbfjaguar.o
+endif
+
+
+ifeq ($(CONFIG_RTL8723B), y)
+RTL871X = rtl8723b
+_PHYDM_FILES += hal/phydm/$(RTL871X)/halhwimg8723b_bb.o\
+								hal/phydm/$(RTL871X)/halhwimg8723b_mac.o\
+								hal/phydm/$(RTL871X)/halhwimg8723b_rf.o\
+								hal/phydm/$(RTL871X)/halhwimg8723b_mp.o\
+								hal/phydm/$(RTL871X)/phydm_regconfig8723b.o\
+								hal/phydm/halrf/$(RTL871X)/halrf_8723b_ce.o\
+								hal/phydm/$(RTL871X)/phydm_rtl8723b.o
+endif
+
+
+ifeq ($(CONFIG_RTL8814A), y)
+RTL871X = rtl8814a
+_PHYDM_FILES += hal/phydm/$(RTL871X)/halhwimg8814a_bb.o\
+								hal/phydm/$(RTL871X)/halhwimg8814a_mac.o\
+								hal/phydm/$(RTL871X)/halhwimg8814a_rf.o\
+								hal/phydm/halrf/$(RTL871X)/halrf_iqk_8814a.o\
+								hal/phydm/$(RTL871X)/phydm_regconfig8814a.o\
+								hal/phydm/halrf/$(RTL871X)/halrf_8814a_ce.o\
+								hal/phydm/$(RTL871X)/phydm_rtl8814a.o\
+								hal/phydm/txbf/haltxbf8814a.o
+endif
+
+
+ifeq ($(CONFIG_RTL8723C), y)
+RTL871X = rtl8703b
+_PHYDM_FILES += hal/phydm/$(RTL871X)/halhwimg8703b_bb.o\
+								hal/phydm/$(RTL871X)/halhwimg8703b_mac.o\
+								hal/phydm/$(RTL871X)/halhwimg8703b_rf.o\
+								hal/phydm/$(RTL871X)/phydm_regconfig8703b.o\
+								hal/phydm/$(RTL871X)/phydm_rtl8703b.o\
+								hal/phydm/halrf/$(RTL871X)/halrf_8703b.o
+endif
+
+ifeq ($(CONFIG_RTL8723D), y)
+RTL871X = rtl8723d
+_PHYDM_FILES += hal/phydm/$(RTL871X)/halhwimg8723d_bb.o\
+								hal/phydm/$(RTL871X)/halhwimg8723d_mac.o\
+								hal/phydm/$(RTL871X)/halhwimg8723d_rf.o\
+								hal/phydm/$(RTL871X)/phydm_regconfig8723d.o\
+								hal/phydm/$(RTL871X)/phydm_rtl8723d.o\
+								hal/phydm/halrf/$(RTL871X)/halrf_8723d.o
+endif
+
+
+ifeq ($(CONFIG_RTL8710B), y)
+RTL871X = rtl8710b
+_PHYDM_FILES += hal/phydm/$(RTL871X)/halhwimg8710b_bb.o\
+								hal/phydm/$(RTL871X)/halhwimg8710b_mac.o\
+								hal/phydm/$(RTL871X)/halhwimg8710b_rf.o\
+								hal/phydm/$(RTL871X)/phydm_regconfig8710b.o\
+								hal/phydm/$(RTL871X)/phydm_rtl8710b.o\
+								hal/phydm/halrf/$(RTL871X)/halrf_8710b.o
+endif
+
+
+ifeq ($(CONFIG_RTL8188F), y)
+RTL871X = rtl8188f
+_PHYDM_FILES += hal/phydm/$(RTL871X)/halhwimg8188f_bb.o\
+								hal/phydm/$(RTL871X)/halhwimg8188f_mac.o\
+								hal/phydm/$(RTL871X)/halhwimg8188f_rf.o\
+								hal/phydm/$(RTL871X)/phydm_regconfig8188f.o\
+								hal/phydm/halrf/$(RTL871X)/halrf_8188f.o \
+								hal/phydm/$(RTL871X)/phydm_rtl8188f.o
+endif
+
+ifeq ($(CONFIG_RTL8822B), y)
+RTL871X = rtl8822b
+_PHYDM_FILES +=	hal/phydm/$(RTL871X)/halhwimg8822b_bb.o \
+								hal/phydm/$(RTL871X)/halhwimg8822b_mac.o \
+								hal/phydm/$(RTL871X)/halhwimg8822b_rf.o \
+								hal/phydm/halrf/$(RTL871X)/halrf_8822b.o \
+								hal/phydm/$(RTL871X)/phydm_hal_api8822b.o \
+								hal/phydm/halrf/$(RTL871X)/halrf_iqk_8822b.o \
+								hal/phydm/halrf/$(RTL871X)/halrf_rfk_init_8822b.o \
+								hal/phydm/$(RTL871X)/phydm_regconfig8822b.o \
+								hal/phydm/$(RTL871X)/phydm_rtl8822b.o
+
+_PHYDM_FILES +=	hal/phydm/txbf/haltxbf8822b.o
+endif
+
+
+ifeq ($(CONFIG_RTL8821C), y)
+RTL871X = rtl8821c
+_PHYDM_FILES +=	hal/phydm/$(RTL871X)/halhwimg8821c_bb.o \
+								hal/phydm/$(RTL871X)/halhwimg8821c_mac.o \
+								hal/phydm/$(RTL871X)/halhwimg8821c_rf.o \
+								hal/phydm/$(RTL871X)/phydm_hal_api8821c.o \
+								hal/phydm/$(RTL871X)/phydm_regconfig8821c.o\
+								hal/phydm/halrf/$(RTL871X)/halrf_8821c.o\
+								hal/phydm/halrf/$(RTL871X)/halrf_iqk_8821c.o
+endif
+ifeq ($(CONFIG_RTL8192F), y)
+RTL871X = rtl8192f
+_PHYDM_FILES += hal/phydm/$(RTL871X)/halhwimg8192f_bb.o\
+								hal/phydm/$(RTL871X)/halhwimg8192f_mac.o\
+								hal/phydm/$(RTL871X)/halhwimg8192f_rf.o\
+								hal/phydm/$(RTL871X)/phydm_hal_api8192f.o\
+								hal/phydm/$(RTL871X)/phydm_regconfig8192f.o\
+								hal/phydm/$(RTL871X)/phydm_rtl8192f.o\
+								hal/phydm/halrf/$(RTL871X)/halrf_8192f.o
+endif
+
+ifeq ($(CONFIG_RTL8198F), y)
+RTL871X = rtl8198f
+_PHYDM_FILES += hal/phydm/$(RTL871X)/halhwimg8198f_bb.o\
+								hal/phydm/$(RTL871X)/halhwimg8198f_mac.o\
+								hal/phydm/$(RTL871X)/halhwimg8198f_rf.o\
+								hal/phydm/$(RTL871X)/phydm_hal_api8198f.o\
+								hal/phydm/$(RTL871X)/phydm_regconfig8198f.o
+endif
+
+ifeq ($(CONFIG_RTL8822C), y)
+RTL871X = rtl8822c
+_PHYDM_FILES += hal/phydm/$(RTL871X)/halhwimg8822c_bb.o\
+								hal/phydm/$(RTL871X)/halhwimg8822c_mac.o\
+								hal/phydm/$(RTL871X)/halhwimg8822c_rf.o\
+								hal/phydm/$(RTL871X)/phydm_hal_api8822c.o\
+								hal/phydm/$(RTL871X)/phydm_regconfig8822c.o
+endif
+
+ifeq ($(CONFIG_RTL8814B), y)
+RTL871X = rtl8814b
+_PHYDM_FILES += hal/phydm/$(RTL871X)/halhwimg8814b_bb.o\
+								hal/phydm/$(RTL871X)/phydm_regconfig8814b.o
+endif
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/phydm_mp.c linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/phydm_mp.c
--- linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/phydm_mp.c	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/phydm_mp.c	2020-04-10 16:35:06.825660488 +0300
@@ -0,0 +1,317 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017  Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * The full GNU General Public License is included in this distribution in the
+ * file called LICENSE.
+ *
+ * Contact Information:
+ * wlanfae <wlanfae@realtek.com>
+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
+ * Hsinchu 300, Taiwan.
+ *
+ * Larry Finger <Larry.Finger@lwfinger.net>
+ *
+ *****************************************************************************/
+
+/*@************************************************************
+ * include files
+ ************************************************************/
+
+#include "mp_precomp.h"
+#include "phydm_precomp.h"
+
+#ifdef PHYDM_MP_SUPPORT
+#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
+
+void phydm_mp_set_single_tone_jgr3(void *dm_void, boolean is_single_tone,
+				   u8 path)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct phydm_mp *mp = &dm->dm_mp_table;
+	u8 start = RF_PATH_A, end = RF_PATH_A;
+
+	switch (path) {
+	case RF_PATH_A:
+	case RF_PATH_B:
+	case RF_PATH_C:
+	case RF_PATH_D:
+		start = path;
+		end = path;
+		break;
+	case RF_PATH_AB:
+		start = RF_PATH_A;
+		end = RF_PATH_B;
+		break;
+	case RF_PATH_BC:
+		start = RF_PATH_B;
+		end = RF_PATH_C;
+		break;
+	case RF_PATH_ABC:
+		start = RF_PATH_A;
+		end = RF_PATH_C;
+		break;
+	case RF_PATH_BCD:
+		start = RF_PATH_B;
+		end = RF_PATH_D;
+		break;
+	case RF_PATH_ABCD:
+		start = RF_PATH_A;
+		end = RF_PATH_D;
+		break;
+	}
+	if (is_single_tone) {
+		mp->rf_reg0 = odm_get_rf_reg(dm, RF_PATH_A, RF_0x00, 0xfffff);
+#if 0
+		mp->rfe_sel_a_0 = odm_get_bb_reg(dm, R_0x1840, MASKDWORD);
+		mp->rfe_sel_b_0 = odm_get_bb_reg(dm, R_0x4140, MASKDWORD);
+		mp->rfe_sel_c_0 = odm_get_bb_reg(dm, R_0x5240, MASKDWORD);
+		mp->rfe_sel_d_0 = odm_get_bb_reg(dm, R_0x5340, MASKDWORD);
+		mp->rfe_sel_a_1 = odm_get_bb_reg(dm, R_0x1844, MASKDWORD);
+		mp->rfe_sel_b_1 = odm_get_bb_reg(dm, R_0x4144, MASKDWORD);
+		mp->rfe_sel_c_1 = odm_get_bb_reg(dm, R_0x5244, MASKDWORD);
+		mp->rfe_sel_d_1 = odm_get_bb_reg(dm, R_0x5344, MASKDWORD);
+#endif
+		/* Disable CCK and OFDM */
+		odm_set_bb_reg(dm, R_0x1c3c, 0x3, 0x0);
+		if (!(dm->support_ic_type & ODM_RTL8814B)) {
+			for (start; start <= end; start++) {
+				/* Tx mode: RF0x00[19:16]=4'b0010 */
+				odm_set_rf_reg(dm, start, RF_0x00, 0xF0000,
+					       0x2);
+				/* Lowest RF gain idx: RF_0x0[4:0] = 0 */
+				odm_set_rf_reg(dm, start, RF_0x00, 0x1F, 0x0);
+				/* RF LO enabled */
+				odm_set_rf_reg(dm, start, RF_0x58, BIT(1),
+					       0x1);
+			}
+		}
+	} else {
+		/* Eable CCK and OFDM */
+		odm_set_bb_reg(dm, R_0x1c3c, 0x3, 0x3);
+		if (!(dm->support_ic_type & ODM_RTL8814B)) {
+			for (start; start <= end; start++) {
+				odm_set_rf_reg(dm, start, RF_0x00, 0xfffff,
+					       mp->rf_reg0);
+				/* RF LO disabled */
+				odm_set_rf_reg(dm, start, RF_0x58, BIT(1),
+					       0x0);
+			}
+		}
+#if 0
+		odm_set_bb_reg(dm, R_0x1840, MASKDWORD, mp->rfe_sel_a_0);
+		odm_set_bb_reg(dm, R_0x4140, MASKDWORD, mp->rfe_sel_b_0);
+		odm_set_bb_reg(dm, R_0x5240, MASKDWORD, mp->rfe_sel_c_0);
+		odm_set_bb_reg(dm, R_0x5340, MASKDWORD, mp->rfe_sel_d_0);
+		odm_set_bb_reg(dm, R_0x1844, MASKDWORD, mp->rfe_sel_a_1);
+		odm_set_bb_reg(dm, R_0x4144, MASKDWORD, mp->rfe_sel_b_1);
+		odm_set_bb_reg(dm, R_0x5244, MASKDWORD, mp->rfe_sel_c_1);
+		odm_set_bb_reg(dm, R_0x5344, MASKDWORD, mp->rfe_sel_d_1);
+#endif
+	}
+}
+
+void phydm_mp_set_carrier_supp_jgr3(void *dm_void, boolean is_carrier_supp,
+				    u32 rate_index)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct phydm_mp *mp = &dm->dm_mp_table;
+
+	if (is_carrier_supp) {
+		if (phydm_is_cck_rate(dm, (u8)rate_index)) {
+			/* @if CCK block on? */
+			if (!odm_get_bb_reg(dm, R_0x1c3c, BIT(1)))
+				odm_set_bb_reg(dm, R_0x1c3c, BIT(1), 1);
+
+			/* @Turn Off All Test mode */
+			odm_set_bb_reg(dm, R_0x1ca4, 0x7, 0x0);
+
+			/* @transmit mode */
+			odm_set_bb_reg(dm, R_0x1a00, 0x3, 0x2);
+			/* @turn off scramble setting */
+			odm_set_bb_reg(dm, R_0x1a00, 0x8, 0x0);
+			/* @Set CCK Tx Test Rate, set FTxRate to 1Mbps */
+			odm_set_bb_reg(dm, R_0x1a00, 0x3000, 0x0);
+		}
+	} else { /* @Stop Carrier Suppression. */
+		if (phydm_is_cck_rate(dm, (u8)rate_index)) {
+			/* @normal mode */
+			odm_set_bb_reg(dm, R_0x1a00, 0x3, 0x0);
+			/* @turn on scramble setting */
+			odm_set_bb_reg(dm, R_0x1a00, 0x8, 0x1);
+			/* @BB Reset */
+			odm_set_bb_reg(dm, R_0x1d0c, 0x10000, 0x0);
+			odm_set_bb_reg(dm, R_0x1d0c, 0x10000, 0x1);
+		}
+	}
+}
+#endif
+
+void phydm_mp_set_crystal_cap(void *dm_void, u8 crystal_cap)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+
+	phydm_set_crystal_cap(dm, crystal_cap);
+}
+
+void phydm_mp_set_single_tone(void *dm_void, boolean is_single_tone, u8 path)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+
+	if (dm->support_ic_type & ODM_IC_JGR3_SERIES)
+		phydm_mp_set_single_tone_jgr3(dm, is_single_tone, path);
+}
+
+void phydm_mp_set_carrier_supp(void *dm_void, boolean is_carrier_supp,
+			       u32 rate_index)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+
+	if (dm->support_ic_type & ODM_IC_JGR3_SERIES)
+		phydm_mp_set_carrier_supp_jgr3(dm, is_carrier_supp, rate_index);
+}
+
+void phydm_mp_set_single_carrier(void *dm_void, boolean is_single_carrier)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct phydm_mp *mp = &dm->dm_mp_table;
+
+	if (is_single_carrier) {
+		if (dm->support_ic_type & ODM_IC_JGR3_SERIES) {
+			/* @1. if OFDM block on? */
+			if (!odm_get_bb_reg(dm, R_0x1c3c, BIT(0)))
+				odm_set_bb_reg(dm, R_0x1c3c, BIT(0), 1);
+
+			/* @2. set CCK test mode off, set to CCK normal mode */
+			odm_set_bb_reg(dm, R_0x1a00, 0x3, 0);
+
+			/* @3. turn on scramble setting */
+			odm_set_bb_reg(dm, R_0x1a00, 0x8, 1);
+
+			/* @4. Turn On single carrier. */
+			odm_set_bb_reg(dm, R_0x1ca4, 0x7, OFDM_SINGLE_CARRIER);
+		} else {
+			/* @1. if OFDM block on? */
+			if (!odm_get_bb_reg(dm, R_0x800, 0x2000000))
+				odm_set_bb_reg(dm, R_0x800, 0x2000000, 1);
+
+			/* @2. set CCK test mode off, set to CCK normal mode */
+			odm_set_bb_reg(dm, R_0xa00, 0x3, 0);
+
+			/* @3. turn on scramble setting */
+			odm_set_bb_reg(dm, R_0xa00, 0x8, 1);
+
+			/* @4. Turn On single carrier. */
+			if (dm->support_ic_type & ODM_IC_11AC_SERIES)
+				odm_set_bb_reg(dm, R_0x914, 0x70000,
+					       OFDM_SINGLE_CARRIER);
+			else if (dm->support_ic_type & ODM_IC_11N_SERIES)
+				odm_set_bb_reg(dm, R_0xd00, 0x70000000,
+					       OFDM_SINGLE_CARRIER);
+		}
+	} else { /* @Stop Single Carrier. */
+	    /* @Turn off all test modes. */
+		if (dm->support_ic_type & ODM_IC_JGR3_SERIES)
+			odm_set_bb_reg(dm, R_0x1ca4, 0x7, OFDM_OFF);
+		else if (dm->support_ic_type & ODM_IC_11AC_SERIES)
+			odm_set_bb_reg(dm, R_0x914, 0x70000, OFDM_OFF);
+		else if (dm->support_ic_type & ODM_IC_11N_SERIES)
+			odm_set_bb_reg(dm, R_0xd00, 0x70000000, OFDM_OFF);
+		/* @Delay 10 ms */
+		ODM_delay_ms(10);
+
+		/* @BB Reset */
+		if (dm->support_ic_type & ODM_IC_JGR3_SERIES) {
+			odm_set_bb_reg(dm, R_0x1d0c, 0x10000, 0x0);
+			odm_set_bb_reg(dm, R_0x1d0c, 0x10000, 0x1);
+		} else {
+			odm_set_bb_reg(dm, R_0x100, 0x100, 0x0);
+			odm_set_bb_reg(dm, R_0x100, 0x100, 0x1);
+		}
+	} 
+}
+void phydm_mp_reset_rx_counters_phy(void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+
+	if (dm->support_ic_type & ODM_IC_JGR3_SERIES) {
+		odm_set_bb_reg(dm, R_0x1eb4, BIT(25), 0x1); 
+		odm_set_bb_reg(dm, R_0x1eb4, BIT(25), 0x0);
+	} else if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
+		odm_set_bb_reg(dm, R_0xb58, BIT(0), 0x1); 
+		odm_set_bb_reg(dm, R_0xb58, BIT(0), 0x0);
+	} else if (dm->support_ic_type & ODM_IC_11N_SERIES){
+		odm_set_bb_reg(dm, R_0xf14, BIT(16), 0x1); 
+		odm_set_bb_reg(dm, R_0xf14, BIT(16), 0x0);		
+	}	
+}
+
+void phydm_mp_get_tx_ok(void *dm_void, u32 rate_index)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct phydm_mp *mp = &dm->dm_mp_table;
+	u32 reg = 0;
+
+	if (dm->support_ic_type & ODM_IC_JGR3_SERIES)
+		reg = R_0x2de4;
+	else
+		reg = R_0xf50;
+
+	if (phydm_is_cck_rate(dm, (u8)rate_index))
+		mp->tx_phy_ok_cnt = odm_get_bb_reg(dm, reg, 0xffff);
+	else
+		mp->tx_phy_ok_cnt = odm_get_bb_reg(dm, reg, 0xffff0000);
+}
+
+void phydm_mp_get_rx_ok(void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct phydm_mp *mp = &dm->dm_mp_table;	
+
+	u32 cck_ok = 0, ofdm_ok = 0, ht_ok = 0, vht_ok = 0;	
+	u32 cck_err = 0, ofdm_err = 0, ht_err = 0, vht_err = 0;
+
+	if (dm->support_ic_type & ODM_IC_JGR3_SERIES) {
+		cck_ok = odm_get_bb_reg(dm, R_0x2c04, 0xffff);
+		ofdm_ok = odm_get_bb_reg(dm, R_0x2c14, 0xffff);
+		ht_ok = odm_get_bb_reg(dm, R_0x2c10, 0xffff);
+		vht_ok = odm_get_bb_reg(dm, R_0x2c0c, 0xffff);
+  
+		cck_err = odm_get_bb_reg(dm, R_0x2c04, 0xffff0000);
+		ofdm_err = odm_get_bb_reg(dm, R_0x2c14, 0xffff0000);
+		ht_err = odm_get_bb_reg(dm, R_0x2c10, 0xffff0000);
+		vht_err = odm_get_bb_reg(dm, R_0x2c0c, 0xffff0000);
+	} else if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
+		cck_ok = odm_get_bb_reg(dm, R_0xf04, 0x3FFF);
+		ofdm_ok = odm_get_bb_reg(dm, R_0xf14, 0x3FFF);
+		ht_ok = odm_get_bb_reg(dm, R_0xf10, 0x3FFF);
+		vht_ok = odm_get_bb_reg(dm, R_0xf0c, 0x3FFF);
+  
+		cck_err = odm_get_bb_reg(dm, R_0xf04, 0x3FFF0000);
+		ofdm_err = odm_get_bb_reg(dm, R_0xf14, 0x3FFF0000);
+		ht_err = odm_get_bb_reg(dm, R_0xf10, 0x3FFF0000);
+		vht_err = odm_get_bb_reg(dm, R_0xf0c, 0x3FFF0000);
+	} else if (dm->support_ic_type & ODM_IC_11N_SERIES) {
+		cck_ok = odm_get_bb_reg(dm, R_0xf88, MASKDWORD);
+		ofdm_ok = odm_get_bb_reg(dm, R_0xf94, 0xffff);
+		ht_ok = odm_get_bb_reg(dm, R_0xf90, 0xffff);
+	    
+		cck_err = odm_get_bb_reg(dm, R_0xf84, MASKDWORD);
+		ofdm_err = odm_get_bb_reg(dm, R_0xf94, 0xffff0000);
+		ht_err = odm_get_bb_reg(dm, R_0xf90, 0xffff0000);
+	}
+
+	mp->rx_phy_ok_cnt = cck_ok + ofdm_ok + ht_ok + vht_ok;
+	mp->rx_phy_crc_err_cnt = cck_err + ofdm_err + ht_err + vht_err;
+	mp->io_value = (u32)mp->rx_phy_ok_cnt;
+}
+#endif
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/phydm_mp.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/phydm_mp.h
--- linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/phydm_mp.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/phydm_mp.h	2020-04-10 16:35:06.825660488 +0300
@@ -0,0 +1,94 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017  Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * The full GNU General Public License is included in this distribution in the
+ * file called LICENSE.
+ *
+ * Contact Information:
+ * wlanfae <wlanfae@realtek.com>
+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
+ * Hsinchu 300, Taiwan.
+ *
+ * Larry Finger <Larry.Finger@lwfinger.net>
+ *
+ *****************************************************************************/
+
+#ifndef __PHYDM_MP_H__
+#define __PHYDM_MP_H__
+
+#define MP_VERSION "1.0"
+
+/* @1 ============================================================
+ * 1  Definition
+ * 1 ============================================================
+ */
+/* @1 ============================================================
+ * 1  structure
+ * 1 ============================================================
+ */
+struct phydm_mp {
+	/* @Rx OK count, statistics used in Mass Production Test.*/
+	u64 tx_phy_ok_cnt;
+	u64 rx_phy_ok_cnt;
+	/* @Rx CRC32 error count, statistics used in Mass Production Test.*/
+	u64 rx_phy_crc_err_cnt;
+	/* @The Value of IO operation is depend of MptActType.*/
+	u32 io_value;
+	u32 rf_reg0;
+	/* @u32 rfe_sel_a_0;*/
+	/* @u32 rfe_sel_b_0;*/
+	/* @u32 rfe_sel_c_0;*/
+	/* @u32 rfe_sel_d_0;*/
+	/* @u32 rfe_sel_a_1;*/
+	/* @u32 rfe_sel_b_1;*/
+	/* @u32 rfe_sel_c_1;*/
+	/* @u32 rfe_sel_d_1;*/
+};
+
+/* @1 ============================================================
+ * 1  enumeration
+ * 1 ============================================================
+ */
+enum TX_MODE_OFDM {
+	OFDM_OFF = 0,	
+	OFDM_CONT_TX = 1,
+	OFDM_SINGLE_CARRIER = 2,
+	OFDM_SINGLE_TONE = 4,
+};
+/* @1 ============================================================
+ * 1  function prototype
+ * 1 ============================================================
+ */
+#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
+void phydm_mp_set_single_tone_jgr3(void *dm_void, boolean is_single_tone,
+				   u8 path);
+
+void phydm_mp_set_carrier_supp_jgr3(void *dm_void, boolean is_carrier_supp,
+				    u32 rate_index);
+#endif
+
+void phydm_mp_set_crystal_cap(void *dm_void, u8 crystal_cap);
+
+void phydm_mp_set_single_tone(void *dm_void, boolean is_single_tone, u8 path);
+
+void phydm_mp_set_carrier_supp(void *dm_void, boolean is_carrier_supp,
+			       u32 rate_index);
+
+void phydm_mp_set_single_carrier(void *dm_void, boolean is_single_carrier);
+
+void phydm_mp_reset_rx_counters_phy(void *dm_void);
+
+void phydm_mp_get_tx_ok(void *dm_void, u32 rate_index);
+
+void phydm_mp_get_rx_ok(void *dm_void);
+#endif
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/phydm_noisemonitor.c linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/phydm_noisemonitor.c
--- linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/phydm_noisemonitor.c	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/phydm_noisemonitor.c	2020-04-10 16:35:06.825660488 +0300
@@ -0,0 +1,457 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017  Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * The full GNU General Public License is included in this distribution in the
+ * file called LICENSE.
+ *
+ * Contact Information:
+ * wlanfae <wlanfae@realtek.com>
+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
+ * Hsinchu 300, Taiwan.
+ *
+ * Larry Finger <Larry.Finger@lwfinger.net>
+ *
+ *****************************************************************************/
+
+/*************************************************************
+ * include files
+ ************************************************************/
+#include "mp_precomp.h"
+#include "phydm_precomp.h"
+
+/**************************************************
+ * This function is for inband noise test utility only
+ * To obtain the inband noise level(dbm), do the following.
+ * 1. disable DIG and Power Saving
+ * 2. Set initial gain = 0x1a
+ * 3. Stop updating idle time pwer report (for driver read)
+ *	- 0x80c[25]
+ *
+ *************************************************/
+
+void phydm_set_noise_data_sum(struct noise_level *noise_data, u8 max_rf_path)
+{
+	u8 i = 0;
+
+	for (i = RF_PATH_A; i < max_rf_path; i++) {
+		if (noise_data->valid_cnt[i])
+			noise_data->sum[i] /= noise_data->valid_cnt[i];
+		else
+			noise_data->sum[i] = 0;
+	}
+}
+
+#if (ODM_IC_11N_SERIES_SUPPORT)
+s16 odm_inband_noise_monitor_n(struct dm_struct *dm, u8 is_pause_dig, u8 igi,
+			       u32 max_time)
+{
+	u32 tmp4b;
+	u8 max_rf_path = 0, i = 0;
+	u8 reg_c50, reg_c58, valid_done = 0;
+	struct noise_level noise_data;
+	u64 start = 0, func_start = 0, func_end = 0;
+	s8 val_s8 = 0;
+
+	func_start = odm_get_current_time(dm);
+	dm->noise_level.noise_all = 0;
+
+	if (dm->rf_type == RF_1T2R || dm->rf_type == RF_2T2R)
+		max_rf_path = 2;
+	else
+		max_rf_path = 1;
+
+	PHYDM_DBG(dm, DBG_ENV_MNTR,
+		  "odm_DebugControlInbandNoise_Nseries() ==>\n");
+
+	odm_memory_set(dm, &noise_data, 0, sizeof(struct noise_level));
+	/* step 1. Disable DIG && Set initial gain. */
+
+	if (is_pause_dig)
+		odm_pause_dig(dm, PHYDM_PAUSE, PHYDM_PAUSE_LEVEL_1, igi);
+
+	/* step 3. Get noise power level */
+	start = odm_get_current_time(dm);
+	while (1) {
+		/* Stop updating idle time pwer report (for driver read) */
+		odm_set_bb_reg(dm, REG_FPGA0_TX_GAIN_STAGE, BIT(25), 1);
+
+		/* Read Noise Floor Report */
+		tmp4b = odm_get_bb_reg(dm, R_0x8f8, MASKDWORD);
+
+		/* update idle time pwer report per 5us */
+		odm_set_bb_reg(dm, REG_FPGA0_TX_GAIN_STAGE, BIT(25), 0);
+
+		ODM_delay_us(5);
+
+		noise_data.value[RF_PATH_A] = (u8)(tmp4b & 0xff);
+		noise_data.value[RF_PATH_B] = (u8)((tmp4b & 0xff00) >> 8);
+
+		for (i = RF_PATH_A; i < max_rf_path; i++) {
+			noise_data.sval[i] = (s8)noise_data.value[i];
+			noise_data.sval[i] /= 2;
+		}
+
+		for (i = RF_PATH_A; i < max_rf_path; i++) {
+			if (noise_data.valid_cnt[i] >= VALID_CNT)
+				continue;
+
+			noise_data.valid_cnt[i]++;
+			noise_data.sum[i] += noise_data.sval[i];
+			PHYDM_DBG(dm, DBG_ENV_MNTR,
+				  "rf_path:%d Valid sval=%d\n", i,
+				  noise_data.sval[i]);
+			PHYDM_DBG(dm, DBG_ENV_MNTR, "Sum of sval = %d,\n",
+				  noise_data.sum[i]);
+			if (noise_data.valid_cnt[i] == VALID_CNT)
+				valid_done++;
+		}
+		if (valid_done == max_rf_path ||
+		    (odm_get_progressing_time(dm, start) > max_time)) {
+			phydm_set_noise_data_sum(&noise_data, max_rf_path);
+			break;
+		}
+	}
+	reg_c50 = (u8)odm_get_bb_reg(dm, REG_OFDM_0_XA_AGC_CORE1, MASKBYTE0);
+	reg_c50 &= ~BIT(7);
+	val_s8 = (s8)(-110 + reg_c50 + noise_data.sum[RF_PATH_A]);
+	dm->noise_level.noise[RF_PATH_A] = val_s8;
+	dm->noise_level.noise_all += dm->noise_level.noise[RF_PATH_A];
+
+	if (max_rf_path == 2) {
+		reg_c58 = (u8)odm_get_bb_reg(dm, R_0xc58, MASKBYTE0);
+		reg_c58 &= ~BIT(7);
+		val_s8 = (s8)(-110 + reg_c58 + noise_data.sum[RF_PATH_B]);
+		dm->noise_level.noise[RF_PATH_B] = val_s8;
+		dm->noise_level.noise_all += dm->noise_level.noise[RF_PATH_B];
+	}
+	dm->noise_level.noise_all /= max_rf_path;
+
+	PHYDM_DBG(dm, DBG_ENV_MNTR,
+		  "noise_a = %d, noise_b = %d, noise_all = %d\n",
+		  dm->noise_level.noise[RF_PATH_A],
+		  dm->noise_level.noise[RF_PATH_B], dm->noise_level.noise_all);
+
+	/* step 4. Recover the Dig */
+	if (is_pause_dig)
+		odm_pause_dig(dm, PHYDM_RESUME, PHYDM_PAUSE_LEVEL_1, igi);
+	func_end = odm_get_progressing_time(dm, func_start);
+
+	PHYDM_DBG(dm, DBG_ENV_MNTR, "end\n");
+	return dm->noise_level.noise_all;
+}
+#endif
+
+#if (ODM_IC_11AC_SERIES_SUPPORT)
+s16 phydm_idle_noise_measure_ac(struct dm_struct *dm, u8 pause_dig,
+				u8 igi, u32 max_time)
+{
+	u32 tmp4b;
+	u8 max_rf_path = 0, i = 0;
+	u8 reg_c50, reg_e50, valid_done = 0;
+	u64 start = 0, func_start = 0, func_end = 0;
+	struct noise_level noise_data;
+	s8 val_s8 = 0;
+
+	func_start = odm_get_current_time(dm);
+	dm->noise_level.noise_all = 0;
+
+	if (dm->rf_type == RF_1T2R || dm->rf_type == RF_2T2R)
+		max_rf_path = 2;
+	else
+		max_rf_path = 1;
+
+	PHYDM_DBG(dm, DBG_ENV_MNTR, "%s==>\n", __func__);
+
+	odm_memory_set(dm, &noise_data, 0, sizeof(struct noise_level));
+
+	/*Step 1. Disable DIG && Set initial gain.*/
+
+	if (pause_dig)
+		odm_pause_dig(dm, PHYDM_PAUSE, PHYDM_PAUSE_LEVEL_1, igi);
+
+	/*Step 2. Get noise power level*/
+	start = odm_get_current_time(dm);
+
+	while (1) {
+		/*Stop updating idle time pwer report (for driver read)*/
+		odm_set_bb_reg(dm, R_0x9e4, BIT(30), 0x1);
+
+		/*Read Noise Floor Report*/
+		tmp4b = odm_get_bb_reg(dm, R_0xff0, MASKDWORD);
+
+		/*update idle time pwer report per 5us*/
+		odm_set_bb_reg(dm, R_0x9e4, BIT(30), 0x0);
+
+		ODM_delay_us(5);
+
+		noise_data.value[RF_PATH_A] = (u8)(tmp4b & 0xff);
+		noise_data.value[RF_PATH_B] = (u8)((tmp4b & 0xff00) >> 8);
+
+		for (i = RF_PATH_A; i < max_rf_path; i++) {
+			noise_data.sval[i] = (s8)noise_data.value[i];
+			noise_data.sval[i] = noise_data.sval[i] >> 1;
+		}
+
+		for (i = RF_PATH_A; i < max_rf_path; i++) {
+			if (noise_data.valid_cnt[i] >= VALID_CNT)
+				continue;
+
+			noise_data.valid_cnt[i]++;
+			noise_data.sum[i] += noise_data.sval[i];
+			PHYDM_DBG(dm, DBG_ENV_MNTR, "Path:%d Valid sval = %d\n",
+				  i, noise_data.sval[i]);
+			PHYDM_DBG(dm, DBG_ENV_MNTR, "Sum of sval = %d\n",
+				  noise_data.sum[i]);
+			if (noise_data.valid_cnt[i] == VALID_CNT)
+				valid_done++;
+		}
+
+		if (valid_done == max_rf_path ||
+		    (odm_get_progressing_time(dm, start) > max_time)) {
+			phydm_set_noise_data_sum(&noise_data, max_rf_path);
+			break;
+		}
+	}
+	reg_c50 = (u8)odm_get_bb_reg(dm, R_0xc50, MASKBYTE0);
+	reg_c50 &= ~BIT(7);
+	val_s8 = (s8)(-110 + reg_c50 + noise_data.sum[RF_PATH_A]);
+	dm->noise_level.noise[RF_PATH_A] = val_s8;
+	dm->noise_level.noise_all += dm->noise_level.noise[RF_PATH_A];
+
+	if (max_rf_path == 2) {
+		reg_e50 = (u8)odm_get_bb_reg(dm, R_0xe50, MASKBYTE0);
+		reg_e50 &= ~BIT(7);
+		val_s8 = (s8)(-110 + reg_e50 + noise_data.sum[RF_PATH_B]);
+		dm->noise_level.noise[RF_PATH_B] = val_s8;
+		dm->noise_level.noise_all += dm->noise_level.noise[RF_PATH_B];
+	}
+	dm->noise_level.noise_all /= max_rf_path;
+
+	PHYDM_DBG(dm, DBG_ENV_MNTR,
+		  "noise_a = %d, noise_b = %d, noise_all = %d\n",
+		  dm->noise_level.noise[RF_PATH_A],
+		  dm->noise_level.noise[RF_PATH_B], dm->noise_level.noise_all);
+
+	/*Step 3. Recover the Dig*/
+	if (pause_dig)
+		odm_pause_dig(dm, PHYDM_RESUME, PHYDM_PAUSE_LEVEL_1, igi);
+	func_end = odm_get_progressing_time(dm, func_start);
+
+	PHYDM_DBG(dm, DBG_ENV_MNTR, "end\n");
+	return dm->noise_level.noise_all;
+}
+
+s16 odm_inband_noise_monitor_ac(struct dm_struct *dm, u8 pause_dig, u8 igi,
+				u32 max_time)
+{
+	s32 rxi_buf_anta, rxq_buf_anta; /*rxi_buf_antb, rxq_buf_antb;*/
+	s32 value32, pwdb_A = 0, sval, noise, sum = 0;
+	boolean pd_flag;
+	u8 valid_cnt = 0;
+	u64 start = 0, func_start = 0, func_end = 0;
+	s32 val_s32 = 0;
+	s16 rpt = 0;
+	u8 val_u8 = 0;
+
+	if (dm->support_ic_type & (ODM_RTL8822B | ODM_RTL8821C)) {
+		rpt = phydm_idle_noise_measure_ac(dm, pause_dig, igi, max_time);
+		return rpt;
+	}
+
+	if (!(dm->support_ic_type & (ODM_RTL8812 | ODM_RTL8821 | ODM_RTL8814A)))
+		return 0;
+
+	func_start = odm_get_current_time(dm);
+	dm->noise_level.noise_all = 0;
+
+	PHYDM_DBG(dm, DBG_ENV_MNTR, "%s ==>\n", __func__);
+
+	/* step 1. Disable DIG && Set initial gain. */
+	if (pause_dig)
+		odm_pause_dig(dm, PHYDM_PAUSE, PHYDM_PAUSE_LEVEL_1, igi);
+
+	/* step 3. Get noise power level */
+	start = odm_get_current_time(dm);
+
+	/* step 3. Get noise power level */
+	while (1) {
+		/*Set IGI=0x1C */
+		odm_write_dig(dm, 0x1C);
+		/*stop CK320&CK88 */
+		odm_set_bb_reg(dm, R_0x8b4, BIT(6), 1);
+		/*Read path-A */
+		/*set debug port*/
+		odm_set_bb_reg(dm, R_0x8fc, MASKDWORD, 0x200);
+		/*read debug port*/
+		value32 = odm_get_bb_reg(dm, R_0xfa0, MASKDWORD);
+		/*rxi_buf_anta=RegFA0[19:10]*/
+		rxi_buf_anta = (value32 & 0xFFC00) >> 10;
+		rxq_buf_anta = value32 & 0x3FF; /*rxq_buf_anta=RegFA0[19:10]*/
+
+		pd_flag = (boolean)((value32 & BIT(31)) >> 31);
+
+		/*Not in packet detection period or Tx state */
+		if (!pd_flag || rxi_buf_anta != 0x200) {
+			/*sign conversion*/
+			rxi_buf_anta = odm_sign_conversion(rxi_buf_anta, 10);
+			rxq_buf_anta = odm_sign_conversion(rxq_buf_anta, 10);
+
+			val_s32 = rxi_buf_anta * rxi_buf_anta +
+				  rxq_buf_anta * rxq_buf_anta;
+			/*S(10,9)*S(10,9)=S(20,18)*/
+			pwdb_A = odm_pwdb_conversion(val_s32, 20, 18);
+
+			PHYDM_DBG(dm, DBG_ENV_MNTR,
+				  "pwdb_A= %d dB, rxi_buf_anta= 0x%x, rxq_buf_anta= 0x%x\n",
+				  pwdb_A, rxi_buf_anta & 0x3FF,
+				  rxq_buf_anta & 0x3FF);
+		}
+		/*Start CK320&CK88*/
+		odm_set_bb_reg(dm, R_0x8b4, BIT(6), 0);
+		/*@BB Reset*/
+		val_u8 = odm_read_1byte(dm, 0x02) & (~BIT(0));
+		odm_write_1byte(dm, 0x02, val_u8);
+		val_u8 = odm_read_1byte(dm, 0x02) | BIT(0);
+		odm_write_1byte(dm, 0x02, val_u8);
+		/*PMAC Reset*/
+		val_u8 = odm_read_1byte(dm, 0xB03) & (~BIT(0));
+		odm_write_1byte(dm, 0xB03, val_u8);
+		val_u8 = odm_read_1byte(dm, 0xB03) | BIT(0);
+		odm_write_1byte(dm, 0xB03, val_u8);
+		/*@CCK Reset*/
+		if (odm_read_1byte(dm, 0x80B) & BIT(4)) {
+			val_u8 = odm_read_1byte(dm, 0x80B) & (~BIT(4));
+			odm_write_1byte(dm, 0x80B, val_u8);
+			val_u8 = odm_read_1byte(dm, 0x80B) | BIT(4);
+			odm_write_1byte(dm, 0x80B, val_u8);
+		}
+
+		sval = pwdb_A;
+
+		if ((sval < 0 && sval >= -27) && valid_cnt < VALID_CNT) {
+			valid_cnt++;
+			sum += sval;
+			PHYDM_DBG(dm, DBG_ENV_MNTR, "Valid sval = %d\n", sval);
+			PHYDM_DBG(dm, DBG_ENV_MNTR, "Sum of sval = %d,\n", sum);
+			if (valid_cnt >= VALID_CNT ||
+			    (odm_get_progressing_time(dm, start) > max_time)) {
+				sum /= VALID_CNT;
+				PHYDM_DBG(dm, DBG_ENV_MNTR,
+					  "After divided, sum = %d\n", sum);
+				break;
+			}
+		}
+	}
+
+	/*@ADC backoff is 12dB,*/
+	/*Ptarget=0x1C-110=-82dBm*/
+	noise = sum + 12 + 0x1C - 110;
+
+	/*Offset*/
+	noise = noise - 3;
+	PHYDM_DBG(dm, DBG_ENV_MNTR, "noise = %d\n", noise);
+	dm->noise_level.noise_all = (s16)noise;
+
+	/* step 4. Recover the Dig*/
+	if (pause_dig)
+		odm_pause_dig(dm, PHYDM_RESUME, PHYDM_PAUSE_LEVEL_1, igi);
+
+	func_end = odm_get_progressing_time(dm, func_start);
+
+	PHYDM_DBG(dm, DBG_ENV_MNTR, "%s <==\n", __func__);
+
+	return dm->noise_level.noise_all;
+}
+#endif
+
+s16 odm_inband_noise_monitor(void *dm_void, u8 pause_dig, u8 igi,
+			     u32 max_time)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	s16 val = 0;
+
+	igi = 0x32;
+
+	/* since HW ability is about +15~-35,
+	 * we fix IGI = -60 for maximum coverage
+	 */
+	#if (ODM_IC_11AC_SERIES_SUPPORT)
+	if (dm->support_ic_type & ODM_IC_11AC_SERIES)
+		val = odm_inband_noise_monitor_ac(dm, pause_dig, igi, max_time);
+	#endif
+
+	#if (ODM_IC_11N_SERIES_SUPPORT)
+	if (dm->support_ic_type & ODM_IC_11N_SERIES)
+		val = odm_inband_noise_monitor_n(dm, pause_dig, igi, max_time);
+	#endif
+
+	return val;
+}
+
+void phydm_noisy_detection(void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	u32 total_fa_cnt, total_cca_cnt;
+	u32 score = 0, i, score_smooth;
+
+	total_cca_cnt = dm->false_alm_cnt.cnt_cca_all;
+	total_fa_cnt = dm->false_alm_cnt.cnt_all;
+
+#if 0
+	if (total_fa_cnt * 16 >= total_cca_cnt * 14)    /*  @87.5 */
+		;
+	else if (total_fa_cnt * 16 >= total_cca_cnt * 12) /*  @75 */
+		;
+	else if (total_fa_cnt * 16 >= total_cca_cnt * 10) /*  @56.25 */
+		;
+	else if (total_fa_cnt * 16 >= total_cca_cnt * 8) /*  @50 */
+		;
+	else if (total_fa_cnt * 16 >= total_cca_cnt * 7) /*  @43.75 */
+		;
+	else if (total_fa_cnt * 16 >= total_cca_cnt * 6) /*  @37.5 */
+		;
+	else if (total_fa_cnt * 16 >= total_cca_cnt * 5) /*  @31.25% */
+		;
+	else if (total_fa_cnt * 16 >= total_cca_cnt * 4) /*  @25% */
+		;
+	else if (total_fa_cnt * 16 >= total_cca_cnt * 3) /*  @18.75% */
+		;
+	else if (total_fa_cnt * 16 >= total_cca_cnt * 2) /*  @12.5% */
+		;
+	else if (total_fa_cnt * 16 >= total_cca_cnt * 1) /*  @6.25% */
+		;
+#endif
+	for (i = 0; i <= 16; i++) {
+		if (total_fa_cnt * 16 >= total_cca_cnt * (16 - i)) {
+			score = 16 - i;
+			break;
+		}
+	}
+
+	/* noisy_decision_smooth = noisy_decision_smooth>>1 + (score<<3)>>1; */
+	dm->noisy_decision_smooth = (dm->noisy_decision_smooth >> 1) +
+				    (score << 2);
+
+	/* Round the noisy_decision_smooth: +"3" comes from (2^3)/2-1 */
+	if (total_cca_cnt >= 300)
+		score_smooth = (dm->noisy_decision_smooth + 3) >> 3;
+	else
+		score_smooth = 0;
+
+	dm->noisy_decision = (score_smooth >= 3) ? 1 : 0;
+
+	PHYDM_DBG(dm, DBG_ENV_MNTR,
+		  "[NoisyDetection] CCA_cnt=%d,FA_cnt=%d, noisy_dec_smooth=%d, score=%d, score_smooth=%d, noisy_dec=%d\n",
+		  total_cca_cnt, total_fa_cnt, dm->noisy_decision_smooth, score,
+		  score_smooth, dm->noisy_decision);
+}
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/phydm_noisemonitor.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/phydm_noisemonitor.h
--- linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/phydm_noisemonitor.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/phydm_noisemonitor.h	2020-04-10 16:35:06.825660488 +0300
@@ -0,0 +1,48 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017  Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * The full GNU General Public License is included in this distribution in the
+ * file called LICENSE.
+ *
+ * Contact Information:
+ * wlanfae <wlanfae@realtek.com>
+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
+ * Hsinchu 300, Taiwan.
+ *
+ * Larry Finger <Larry.Finger@lwfinger.net>
+ *
+ *****************************************************************************/
+#ifndef __ODMNOISEMONITOR_H__
+#define __ODMNOISEMONITOR_H__
+
+#define VALID_CNT 5
+
+struct noise_level {
+	u8 value[PHYDM_MAX_RF_PATH];
+	s8 sval[PHYDM_MAX_RF_PATH];
+	s32 sum[PHYDM_MAX_RF_PATH];
+	u8 valid[PHYDM_MAX_RF_PATH];
+	u8 valid_cnt[PHYDM_MAX_RF_PATH];
+};
+
+struct odm_noise_monitor {
+	s8 noise[PHYDM_MAX_RF_PATH];
+	s16 noise_all;
+};
+
+s16 odm_inband_noise_monitor(void *dm_void, u8 is_pause_dig, u8 igi_value,
+			     u32 max_time);
+
+void phydm_noisy_detection(void *dm_void);
+
+#endif
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/phydm_pathdiv.c linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/phydm_pathdiv.c
--- linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/phydm_pathdiv.c	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/phydm_pathdiv.c	2020-04-10 16:35:06.825660488 +0300
@@ -0,0 +1,628 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017  Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * The full GNU General Public License is included in this distribution in the
+ * file called LICENSE.
+ *
+ * Contact Information:
+ * wlanfae <wlanfae@realtek.com>
+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
+ * Hsinchu 300, Taiwan.
+ *
+ * Larry Finger <Larry.Finger@lwfinger.net>
+ *
+ *****************************************************************************/
+
+/*************************************************************
+ * include files
+ ************************************************************/
+#include "mp_precomp.h"
+#include "phydm_precomp.h"
+
+#ifdef CONFIG_PATH_DIVERSITY
+#if RTL8814A_SUPPORT
+void phydm_dtp_fix_tx_path(
+	void *dm_void,
+	u8 path)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct _ODM_PATH_DIVERSITY_ *dm_path_div = &dm->dm_path_div;
+	u8 i, num_enable_path = 0;
+
+	if (path == dm_path_div->pre_tx_path)
+		return;
+	else
+		dm_path_div->pre_tx_path = path;
+
+	odm_set_bb_reg(dm, R_0x93c, BIT(18) | BIT(19), 3);
+
+	for (i = 0; i < 4; i++) {
+		if (path & BIT(i))
+			num_enable_path++;
+	}
+	PHYDM_DBG(dm, DBG_PATH_DIV, " number of turn-on path : (( %d ))\n",
+		  num_enable_path);
+
+	if (num_enable_path == 1) {
+		odm_set_bb_reg(dm, R_0x93c, 0xf00000, path);
+
+		if (path == BB_PATH_A) { /* @1-1 */
+			PHYDM_DBG(dm, DBG_PATH_DIV, " Turn on path (( A ))\n");
+			odm_set_bb_reg(dm, R_0x93c, BIT(25) | BIT(24), 0);
+		} else if (path == BB_PATH_B) { /* @1-2 */
+			PHYDM_DBG(dm, DBG_PATH_DIV, " Turn on path (( B ))\n");
+			odm_set_bb_reg(dm, R_0x93c, BIT(27) | BIT(26), 0);
+		} else if (path == BB_PATH_C) { /* @1-3 */
+			PHYDM_DBG(dm, DBG_PATH_DIV, " Turn on path (( C ))\n");
+			odm_set_bb_reg(dm, R_0x93c, BIT(29) | BIT(28), 0);
+
+		} else if (path == BB_PATH_D) { /* @1-4 */
+			PHYDM_DBG(dm, DBG_PATH_DIV, " Turn on path (( D ))\n");
+			odm_set_bb_reg(dm, R_0x93c, BIT(31) | BIT(30), 0);
+		}
+
+	} else if (num_enable_path == 2) {
+		odm_set_bb_reg(dm, R_0x93c, 0xf00000, path);
+		odm_set_bb_reg(dm, R_0x940, 0xf0, path);
+
+		if (path == (BB_PATH_AB)) { /* @2-1 */
+			PHYDM_DBG(dm, DBG_PATH_DIV,
+				  " Turn on path (( A B ))\n");
+			/* set for 1ss */
+			odm_set_bb_reg(dm, R_0x93c, BIT(25) | BIT(24), 0);
+			odm_set_bb_reg(dm, R_0x93c, BIT(27) | BIT(26), 1);
+			/* set for 2ss */
+			odm_set_bb_reg(dm, R_0x940, BIT(9) | BIT(8), 0);
+			odm_set_bb_reg(dm, R_0x940, BIT(11) | BIT(10), 1);
+		} else if (path == BB_PATH_AC) { /* @2-2 */
+			PHYDM_DBG(dm, DBG_PATH_DIV,
+				  " Turn on path (( A C ))\n");
+			/* set for 1ss */
+			odm_set_bb_reg(dm, R_0x93c, BIT(25) | BIT(24), 0);
+			odm_set_bb_reg(dm, R_0x93c, BIT(29) | BIT(28), 1);
+			/* set for 2ss */
+			odm_set_bb_reg(dm, R_0x940, BIT(9) | BIT(8), 0);
+			odm_set_bb_reg(dm, R_0x940, BIT(13) | BIT(12), 1);
+		} else if (path == BB_PATH_AD) { /* @2-3 */
+			PHYDM_DBG(dm, DBG_PATH_DIV,
+				  " Turn on path (( A D ))\n");
+			/* set for 1ss */
+			odm_set_bb_reg(dm, R_0x93c, BIT(25) | BIT(24), 0);
+			odm_set_bb_reg(dm, R_0x93c, BIT(31) | BIT(30), 1);
+			/* set for 2ss */
+			odm_set_bb_reg(dm, R_0x940, BIT(9) | BIT(8), 0);
+			odm_set_bb_reg(dm, R_0x940, BIT(15) | BIT(14), 1);
+		} else if (path == BB_PATH_BC) { /* @2-4 */
+			PHYDM_DBG(dm, DBG_PATH_DIV,
+				  " Turn on path (( B C ))\n");
+			/* set for 1ss */
+			odm_set_bb_reg(dm, R_0x93c, BIT(27) | BIT(26), 0);
+			odm_set_bb_reg(dm, R_0x93c, BIT(29) | BIT(28), 1);
+			/* set for 2ss */
+			odm_set_bb_reg(dm, R_0x940, BIT(11) | BIT(10), 0);
+			odm_set_bb_reg(dm, R_0x940, BIT(13) | BIT(12), 1);
+		} else if (path == BB_PATH_BD) { /* @2-5 */
+			PHYDM_DBG(dm, DBG_PATH_DIV,
+				  " Turn on path (( B D ))\n");
+			/* set for 1ss */
+			odm_set_bb_reg(dm, R_0x93c, BIT(27) | BIT(26), 0);
+			odm_set_bb_reg(dm, R_0x93c, BIT(31) | BIT(30), 1);
+			/* set for 2ss */
+			odm_set_bb_reg(dm, R_0x940, BIT(11) | BIT(10), 0);
+			odm_set_bb_reg(dm, R_0x940, BIT(15) | BIT(14), 1);
+		} else if (path == BB_PATH_CD) { /* @2-6 */
+			PHYDM_DBG(dm, DBG_PATH_DIV,
+				  " Turn on path (( C D ))\n");
+			/* set for 1ss */
+			odm_set_bb_reg(dm, R_0x93c, BIT(29) | BIT(28), 0);
+			odm_set_bb_reg(dm, R_0x93c, BIT(31) | BIT(30), 1);
+			/* set for 2ss */
+			odm_set_bb_reg(dm, R_0x940, BIT(13) | BIT(12), 0);
+			odm_set_bb_reg(dm, R_0x940, BIT(15) | BIT(14), 1);
+		}
+
+	} else if (num_enable_path == 3) {
+		odm_set_bb_reg(dm, R_0x93c, 0xf00000, path);
+		odm_set_bb_reg(dm, R_0x940, 0xf0, path);
+		odm_set_bb_reg(dm, R_0x940, 0xf0000, path);
+
+		if (path == BB_PATH_ABC) { /* @3-1 */
+			PHYDM_DBG(dm, DBG_PATH_DIV,
+				  " Turn on path (( A B C))\n");
+			/* set for 1ss */
+			odm_set_bb_reg(dm, R_0x93c, BIT(25) | BIT(24), 0);
+			odm_set_bb_reg(dm, R_0x93c, BIT(27) | BIT(26), 1);
+			odm_set_bb_reg(dm, R_0x93c, BIT(29) | BIT(28), 2);
+			/* set for 2ss */
+			odm_set_bb_reg(dm, R_0x940, BIT(9) | BIT(8), 0);
+			odm_set_bb_reg(dm, R_0x940, BIT(11) | BIT(10), 1);
+			odm_set_bb_reg(dm, R_0x940, BIT(13) | BIT(12), 2);
+			/* set for 3ss */
+			odm_set_bb_reg(dm, R_0x940, BIT(21) | BIT(20), 0);
+			odm_set_bb_reg(dm, R_0x940, BIT(23) | BIT(22), 1);
+			odm_set_bb_reg(dm, R_0x940, BIT(25) | BIT(24), 2);
+		} else if (path == BB_PATH_ABD) { /* @3-2 */
+			PHYDM_DBG(dm, DBG_PATH_DIV,
+				  " Turn on path (( A B D ))\n");
+			/* set for 1ss */
+			odm_set_bb_reg(dm, R_0x93c, BIT(25) | BIT(24), 0);
+			odm_set_bb_reg(dm, R_0x93c, BIT(27) | BIT(26), 1);
+			odm_set_bb_reg(dm, R_0x93c, BIT(31) | BIT(30), 2);
+			/* set for 2ss */
+			odm_set_bb_reg(dm, R_0x940, BIT(9) | BIT(8), 0);
+			odm_set_bb_reg(dm, R_0x940, BIT(11) | BIT(10), 1);
+			odm_set_bb_reg(dm, R_0x940, BIT(15) | BIT(14), 2);
+			/* set for 3ss */
+			odm_set_bb_reg(dm, R_0x940, BIT(21) | BIT(20), 0);
+			odm_set_bb_reg(dm, R_0x940, BIT(23) | BIT(22), 1);
+			odm_set_bb_reg(dm, R_0x940, BIT(27) | BIT(26), 2);
+
+		} else if (path == BB_PATH_ACD) { /* @3-3 */
+			PHYDM_DBG(dm, DBG_PATH_DIV,
+				  " Turn on path (( A C D ))\n");
+			/* set for 1ss */
+			odm_set_bb_reg(dm, R_0x93c, BIT(25) | BIT(24), 0);
+			odm_set_bb_reg(dm, R_0x93c, BIT(29) | BIT(28), 1);
+			odm_set_bb_reg(dm, R_0x93c, BIT(31) | BIT(30), 2);
+			/* set for 2ss */
+			odm_set_bb_reg(dm, R_0x940, BIT(9) | BIT(8), 0);
+			odm_set_bb_reg(dm, R_0x940, BIT(13) | BIT(12), 1);
+			odm_set_bb_reg(dm, R_0x940, BIT(15) | BIT(14), 2);
+			/* set for 3ss */
+			odm_set_bb_reg(dm, R_0x940, BIT(21) | BIT(20), 0);
+			odm_set_bb_reg(dm, R_0x940, BIT(25) | BIT(24), 1);
+			odm_set_bb_reg(dm, R_0x940, BIT(27) | BIT(26), 2);
+		} else if (path == BB_PATH_BCD) { /* @3-4 */
+			PHYDM_DBG(dm, DBG_PATH_DIV,
+				  " Turn on path (( B C D))\n");
+			/* set for 1ss */
+			odm_set_bb_reg(dm, R_0x93c, BIT(27) | BIT(26), 0);
+			odm_set_bb_reg(dm, R_0x93c, BIT(29) | BIT(28), 1);
+			odm_set_bb_reg(dm, R_0x93c, BIT(31) | BIT(30), 2);
+			/* set for 2ss */
+			odm_set_bb_reg(dm, R_0x940, BIT(11) | BIT(10), 0);
+			odm_set_bb_reg(dm, R_0x940, BIT(13) | BIT(12), 1);
+			odm_set_bb_reg(dm, R_0x940, BIT(15) | BIT(14), 2);
+			/* set for 3ss */
+			odm_set_bb_reg(dm, R_0x940, BIT(23) | BIT(22), 0);
+			odm_set_bb_reg(dm, R_0x940, BIT(25) | BIT(24), 1);
+			odm_set_bb_reg(dm, R_0x940, BIT(27) | BIT(26), 2);
+		}
+	} else if (num_enable_path == 4)
+		PHYDM_DBG(dm, DBG_PATH_DIV, " Turn on path ((A  B C D))\n");
+}
+
+void phydm_find_default_path(
+	void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct _ODM_PATH_DIVERSITY_ *dm_path_div = &dm->dm_path_div;
+	u32 rssi_avg_a = 0, rssi_avg_b = 0, rssi_avg_c = 0, rssi_avg_d = 0, rssi_avg_bcd = 0;
+	u32 rssi_total_a = 0, rssi_total_b = 0, rssi_total_c = 0, rssi_total_d = 0;
+
+	/* @2 Default path Selection By RSSI */
+
+	rssi_avg_a = (dm_path_div->path_a_cnt_all > 0) ? (dm_path_div->path_a_sum_all / dm_path_div->path_a_cnt_all) : 0;
+	rssi_avg_b = (dm_path_div->path_b_cnt_all > 0) ? (dm_path_div->path_b_sum_all / dm_path_div->path_b_cnt_all) : 0;
+	rssi_avg_c = (dm_path_div->path_c_cnt_all > 0) ? (dm_path_div->path_c_sum_all / dm_path_div->path_c_cnt_all) : 0;
+	rssi_avg_d = (dm_path_div->path_d_cnt_all > 0) ? (dm_path_div->path_d_sum_all / dm_path_div->path_d_cnt_all) : 0;
+
+	dm_path_div->path_a_sum_all = 0;
+	dm_path_div->path_a_cnt_all = 0;
+	dm_path_div->path_b_sum_all = 0;
+	dm_path_div->path_b_cnt_all = 0;
+	dm_path_div->path_c_sum_all = 0;
+	dm_path_div->path_c_cnt_all = 0;
+	dm_path_div->path_d_sum_all = 0;
+	dm_path_div->path_d_cnt_all = 0;
+
+	if (dm_path_div->use_path_a_as_default_ant == 1) {
+		rssi_avg_bcd = (rssi_avg_b + rssi_avg_c + rssi_avg_d) / 3;
+
+		if ((rssi_avg_a + ANT_DECT_RSSI_TH) > rssi_avg_bcd) {
+			dm_path_div->is_path_a_exist = true;
+			dm_path_div->default_path = PATH_A;
+		} else
+			dm_path_div->is_path_a_exist = false;
+	} else {
+		if (rssi_avg_a >= rssi_avg_b && rssi_avg_a >= rssi_avg_c && rssi_avg_a >= rssi_avg_d)
+			dm_path_div->default_path = PATH_A;
+		else if ((rssi_avg_b >= rssi_avg_c) && (rssi_avg_b >= rssi_avg_d))
+			dm_path_div->default_path = PATH_B;
+		else if (rssi_avg_c >= rssi_avg_d)
+			dm_path_div->default_path = PATH_C;
+		else
+			dm_path_div->default_path = PATH_D;
+	}
+}
+
+void phydm_candidate_dtp_update(
+	void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct _ODM_PATH_DIVERSITY_ *dm_path_div = &dm->dm_path_div;
+
+	dm_path_div->num_candidate = 3;
+
+	if (dm_path_div->use_path_a_as_default_ant == 1) {
+		if (dm_path_div->num_tx_path == 3) {
+			if (dm_path_div->is_path_a_exist) {
+				dm_path_div->ant_candidate_1 = BB_PATH_ABC;
+				dm_path_div->ant_candidate_2 = BB_PATH_ABD;
+				dm_path_div->ant_candidate_3 = BB_PATH_ACD;
+			} else { /* use path BCD */
+				dm_path_div->num_candidate = 1;
+				phydm_dtp_fix_tx_path(dm, BB_PATH_BCD);
+				return;
+			}
+		} else if (dm_path_div->num_tx_path == 2) {
+			if (dm_path_div->is_path_a_exist) {
+				dm_path_div->ant_candidate_1 = BB_PATH_AB;
+				dm_path_div->ant_candidate_2 = BB_PATH_AC;
+				dm_path_div->ant_candidate_3 = BB_PATH_AD;
+			} else {
+				dm_path_div->ant_candidate_1 = BB_PATH_BC;
+				dm_path_div->ant_candidate_2 = BB_PATH_BD;
+				dm_path_div->ant_candidate_3 = BB_PATH_CD;
+			}
+		}
+	} else {
+		/* @2 3 TX mode */
+		if (dm_path_div->num_tx_path == 3) { /* @choose 3 ant form 4 */
+			if (dm_path_div->default_path == PATH_A) { /* @choose 2 ant form 3 */
+				dm_path_div->ant_candidate_1 = BB_PATH_ABC;
+				dm_path_div->ant_candidate_2 = BB_PATH_ABD;
+				dm_path_div->ant_candidate_3 = BB_PATH_ACD;
+			} else if (dm_path_div->default_path == PATH_B) {
+				dm_path_div->ant_candidate_1 = BB_PATH_ABC;
+				dm_path_div->ant_candidate_2 = BB_PATH_ABD;
+				dm_path_div->ant_candidate_3 = BB_PATH_BCD;
+			} else if (dm_path_div->default_path == PATH_C) {
+				dm_path_div->ant_candidate_1 = BB_PATH_ABC;
+				dm_path_div->ant_candidate_2 = BB_PATH_ACD;
+				dm_path_div->ant_candidate_3 = BB_PATH_BCD;
+			} else if (dm_path_div->default_path == PATH_D) {
+				dm_path_div->ant_candidate_1 = BB_PATH_ABD;
+				dm_path_div->ant_candidate_2 = BB_PATH_ACD;
+				dm_path_div->ant_candidate_3 = BB_PATH_BCD;
+			}
+		}
+
+		/* @2 2 TX mode */
+		else if (dm_path_div->num_tx_path == 2) { /* @choose 2 ant form 4 */
+			if (dm_path_div->default_path == PATH_A) { /* @choose 2 ant form 3 */
+				dm_path_div->ant_candidate_1 = BB_PATH_AB;
+				dm_path_div->ant_candidate_2 = BB_PATH_AC;
+				dm_path_div->ant_candidate_3 = BB_PATH_AD;
+			} else if (dm_path_div->default_path == PATH_B) {
+				dm_path_div->ant_candidate_1 = BB_PATH_AB;
+				dm_path_div->ant_candidate_2 = BB_PATH_BC;
+				dm_path_div->ant_candidate_3 = BB_PATH_BD;
+			} else if (dm_path_div->default_path == PATH_C) {
+				dm_path_div->ant_candidate_1 = BB_PATH_AC;
+				dm_path_div->ant_candidate_2 = BB_PATH_BC;
+				dm_path_div->ant_candidate_3 = BB_PATH_CD;
+			} else if (dm_path_div->default_path == PATH_D) {
+				dm_path_div->ant_candidate_1 = BB_PATH_AD;
+				dm_path_div->ant_candidate_2 = BB_PATH_BD;
+				dm_path_div->ant_candidate_3 = BB_PATH_CD;
+			}
+		}
+	}
+}
+
+void phydm_dynamic_tx_path(
+	void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct _ODM_PATH_DIVERSITY_ *dm_path_div = &dm->dm_path_div;
+
+	struct sta_info *entry;
+	u32 i;
+	u8 num_client = 0;
+	u8 h2c_parameter[6] = {0};
+
+	if (!dm->is_linked) { /* @is_linked==False */
+		PHYDM_DBG(dm, DBG_PATH_DIV, "DTP_8814 [No Link!!!]\n");
+
+		if (dm_path_div->is_become_linked == true) {
+			PHYDM_DBG(dm, DBG_PATH_DIV,
+				  " [Be disconnected]----->\n");
+			dm_path_div->is_become_linked = dm->is_linked;
+		}
+		return;
+	} else {
+		if (dm_path_div->is_become_linked == false) {
+			PHYDM_DBG(dm, DBG_PATH_DIV, " [Be Linked !!!]----->\n");
+			dm_path_div->is_become_linked = dm->is_linked;
+		}
+	}
+
+	/* @2 [period CTRL] */
+	if (dm_path_div->dtp_period >= 2)
+		dm_path_div->dtp_period = 0;
+	else {
+#if 0
+		/* PHYDM_DBG(dm,DBG_PATH_DIV, "Phydm_Dynamic_Tx_Path_8814A()  Stay = (( %d ))\n",dm_path_div->dtp_period); */
+#endif
+		dm_path_div->dtp_period++;
+		return;
+	}
+
+	/* @2 [Fix path] */
+	if (dm->path_select != PHYDM_AUTO_PATH)
+		return;
+
+/* @2 [Check Bfer] */
+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
+#if (BEAMFORMING_SUPPORT == 1)
+	{
+		enum beamforming_cap beamform_cap = (dm->beamforming_info.beamform_cap);
+
+		if (beamform_cap & BEAMFORMER_CAP) { /* @BFmer On  &&   Div On->Div Off */
+			if (dm_path_div->fix_path_bfer == 0) {
+				PHYDM_DBG(dm, DBG_PATH_DIV,
+					  "[ PathDiv : OFF ]   BFmer ==1\n");
+				dm_path_div->fix_path_bfer = 1;
+			}
+			return;
+		} else { /* @BFmer Off   &&   Div Off->Div On */
+			if (dm_path_div->fix_path_bfer == 1) {
+				PHYDM_DBG(dm, DBG_PATH_DIV,
+					  "[ PathDiv : ON ]   BFmer ==0\n");
+				dm_path_div->fix_path_bfer = 0;
+			}
+		}
+	}
+#endif
+#endif
+
+	if (dm_path_div->use_path_a_as_default_ant == 1) {
+		phydm_find_default_path(dm);
+		phydm_candidate_dtp_update(dm);
+	} else {
+		if (dm_path_div->phydm_dtp_state == PHYDM_DTP_INIT) {
+			phydm_find_default_path(dm);
+			phydm_candidate_dtp_update(dm);
+			dm_path_div->phydm_dtp_state = PHYDM_DTP_RUNNING_1;
+		}
+
+		else if (dm_path_div->phydm_dtp_state == PHYDM_DTP_RUNNING_1) {
+			dm_path_div->dtp_check_patha_counter++;
+
+			if (dm_path_div->dtp_check_patha_counter >= NUM_RESET_DTP_PERIOD) {
+				dm_path_div->dtp_check_patha_counter = 0;
+				dm_path_div->phydm_dtp_state = PHYDM_DTP_INIT;
+			}
+#if 0
+			/* @2 Search space update */
+			else {
+				/* @1.  find the worst candidate */
+
+
+				/* @2. repalce the worst candidate */
+			}
+#endif
+		}
+	}
+
+	/* @2 Dynamic path Selection H2C */
+
+	if (dm_path_div->num_candidate == 1)
+		return;
+	else {
+		h2c_parameter[0] = dm_path_div->num_candidate;
+		h2c_parameter[1] = dm_path_div->num_tx_path;
+		h2c_parameter[2] = dm_path_div->ant_candidate_1;
+		h2c_parameter[3] = dm_path_div->ant_candidate_2;
+		h2c_parameter[4] = dm_path_div->ant_candidate_3;
+
+		odm_fill_h2c_cmd(dm, PHYDM_H2C_DYNAMIC_TX_PATH, 6, h2c_parameter);
+	}
+}
+
+void phydm_dynamic_tx_path_init(
+	void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct _ODM_PATH_DIVERSITY_ *dm_path_div = &dm->dm_path_div;
+	void *adapter = dm->adapter;
+	u8 search_space_2[NUM_CHOOSE2_FROM4] = {BB_PATH_AB, BB_PATH_AC, BB_PATH_AD, BB_PATH_BC, BB_PATH_BD, BB_PATH_CD};
+	u8 search_space_3[NUM_CHOOSE3_FROM4] = {BB_PATH_BCD, BB_PATH_ACD, BB_PATH_ABD, BB_PATH_ABC};
+
+#if ((DM_ODM_SUPPORT_TYPE == ODM_WIN) && USB_SWITCH_SUPPORT)
+	dm_path_div->is_u3_mode = (*dm->hub_usb_mode == 2) ? 1 : 0;
+	PHYDM_DBG(dm, DBG_PATH_DIV, "[WIN USB] is_u3_mode = (( %d ))\n",
+		  dm_path_div->is_u3_mode);
+#else
+	dm_path_div->is_u3_mode = 1;
+#endif
+	PHYDM_DBG(dm, DBG_PATH_DIV, "Dynamic TX path Init 8814\n");
+
+	memcpy(&dm_path_div->search_space_2[0], &search_space_2[0],
+	       NUM_CHOOSE2_FROM4);
+	memcpy(&dm_path_div->search_space_3[0], &search_space_3[0],
+	       NUM_CHOOSE3_FROM4);
+
+	dm_path_div->use_path_a_as_default_ant = 1;
+	dm_path_div->phydm_dtp_state = PHYDM_DTP_INIT;
+	dm->path_select = PHYDM_AUTO_PATH;
+	dm_path_div->phydm_path_div_type = PHYDM_4R_PATH_DIV;
+
+	if (dm_path_div->is_u3_mode) {
+		dm_path_div->num_tx_path = 3;
+		phydm_dtp_fix_tx_path(dm, BB_PATH_BCD); /* @3TX  Set Init TX path*/
+
+	} else {
+		dm_path_div->num_tx_path = 2;
+		phydm_dtp_fix_tx_path(dm, BB_PATH_BC); /* @2TX // Set Init TX path*/
+	}
+}
+
+void phydm_process_rssi_for_path_div(
+	void *dm_void,
+	void *phy_info_void,
+	void *pkt_info_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct phydm_phyinfo_struct *phy_info = (struct phydm_phyinfo_struct *)phy_info_void;
+	struct phydm_perpkt_info_struct *pktinfo = (struct phydm_perpkt_info_struct *)pkt_info_void;
+	struct _ODM_PATH_DIVERSITY_ *dm_path_div = &dm->dm_path_div;
+
+	if (!(pktinfo->is_packet_to_self || pktinfo->is_packet_match_bssid))
+		return;
+
+	if (pktinfo->data_rate <= ODM_RATE11M)
+		return;
+
+	if (dm_path_div->phydm_path_div_type == PHYDM_4R_PATH_DIV) {
+#if RTL8814A_SUPPORT
+		if (dm->support_ic_type & ODM_RTL8814A) {
+			dm_path_div->path_a_sum_all += phy_info->rx_mimo_signal_strength[0];
+			dm_path_div->path_a_cnt_all++;
+
+			dm_path_div->path_b_sum_all += phy_info->rx_mimo_signal_strength[1];
+			dm_path_div->path_b_cnt_all++;
+
+			dm_path_div->path_c_sum_all += phy_info->rx_mimo_signal_strength[2];
+			dm_path_div->path_c_cnt_all++;
+
+			dm_path_div->path_d_sum_all += phy_info->rx_mimo_signal_strength[3];
+			dm_path_div->path_d_cnt_all++;
+		}
+#endif
+	} else {
+		dm_path_div->path_a_sum[pktinfo->station_id] += phy_info->rx_mimo_signal_strength[0];
+		dm_path_div->path_a_cnt[pktinfo->station_id]++;
+
+		dm_path_div->path_b_sum[pktinfo->station_id] += phy_info->rx_mimo_signal_strength[1];
+		dm_path_div->path_b_cnt[pktinfo->station_id]++;
+	}
+}
+
+#endif /* @#if RTL8814A_SUPPORT */
+
+void phydm_pathdiv_debug(void *dm_void, char input[][16], u32 *_used,
+			 char *output, u32 *_out_len)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct _ODM_PATH_DIVERSITY_ *dm_path_div = &dm->dm_path_div;
+	u32 used = *_used;
+	u32 out_len = *_out_len;
+	u32 dm_value[10] = {0};
+	u8 i, input_idx = 0;
+
+	for (i = 0; i < 5; i++) {
+		if (input[i + 1]) {
+			PHYDM_SSCANF(input[i + 1], DCMD_HEX, &dm_value[i]);
+			input_idx++;
+		}
+	}
+
+	if (input_idx == 0)
+		return;
+
+	dm->path_select = (dm_value[0] & 0xf);
+	PDM_SNPF(out_len, used, output + used, out_len - used,
+		 "Path_select = (( 0x%x ))\n", dm->path_select);
+
+	/* @2 [Fix path] */
+	if (dm->path_select != PHYDM_AUTO_PATH) {
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "Trun on path  [%s%s%s%s]\n",
+			 ((dm->path_select) & 0x1) ? "A" : "",
+			 ((dm->path_select) & 0x2) ? "B" : "",
+			 ((dm->path_select) & 0x4) ? "C" : "",
+			 ((dm->path_select) & 0x8) ? "D" : "");
+
+		phydm_dtp_fix_tx_path(dm, dm->path_select);
+	} else
+		PDM_SNPF(out_len, used, output + used, out_len - used, "%s\n",
+			 "Auto path");
+
+	*_used = used;
+	*_out_len = out_len;
+}
+
+void phydm_c2h_dtp_handler(void *dm_void, u8 *cmd_buf, u8 cmd_len)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct _ODM_PATH_DIVERSITY_ *dm_path_div = &dm->dm_path_div;
+
+	u8 macid = cmd_buf[0];
+	u8 target = cmd_buf[1];
+	u8 nsc_1 = cmd_buf[2];
+	u8 nsc_2 = cmd_buf[3];
+	u8 nsc_3 = cmd_buf[4];
+
+	PHYDM_DBG(dm, DBG_PATH_DIV, "Target_candidate = (( %d ))\n", target);
+/*@
+	if( (nsc_1 >= nsc_2) &&  (nsc_1 >= nsc_3))
+	{
+		phydm_dtp_fix_tx_path(dm, dm_path_div->ant_candidate_1);
+	}
+	else	if( nsc_2 >= nsc_3)
+	{
+		phydm_dtp_fix_tx_path(dm, dm_path_div->ant_candidate_2);
+	}
+	else
+	{
+		phydm_dtp_fix_tx_path(dm, dm_path_div->ant_candidate_3);
+	}
+	*/
+}
+
+void odm_path_diversity(void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+
+	if (!(dm->support_ability & ODM_BB_PATH_DIV)) {
+		PHYDM_DBG(dm, DBG_PATH_DIV, "Return: Not Support PathDiv\n");
+		return;
+	}
+
+	#if RTL8812A_SUPPORT
+	if (dm->support_ic_type & ODM_RTL8812)
+		odm_path_diversity_8812a(dm);
+	#endif
+
+	#if RTL8814A_SUPPORT
+	if (dm->support_ic_type & ODM_RTL8814A)
+		phydm_dynamic_tx_path(dm);
+	#endif
+
+}
+
+void phydm_path_diversity_init(void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+
+	if (*dm->mp_mode)
+		return;
+
+	if (!(dm->support_ability & ODM_BB_PATH_DIV)) {
+		PHYDM_DBG(dm, DBG_PATH_DIV, "Return: Not Support PathDiv\n");
+		return;
+	}
+
+	#if RTL8812A_SUPPORT
+	if (dm->support_ic_type & ODM_RTL8812)
+		odm_path_diversity_init_8812a(dm);
+	#endif
+
+	#if RTL8814A_SUPPORT
+	if (dm->support_ic_type & ODM_RTL8814A)
+		phydm_dynamic_tx_path_init(dm);
+	#endif
+}
+#endif /*  @#ifdef CONFIG_PATH_DIVERSITY */
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/phydm_pathdiv.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/phydm_pathdiv.h
--- linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/phydm_pathdiv.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/phydm_pathdiv.h	2020-04-10 16:35:06.826660535 +0300
@@ -0,0 +1,117 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017  Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * The full GNU General Public License is included in this distribution in the
+ * file called LICENSE.
+ *
+ * Contact Information:
+ * wlanfae <wlanfae@realtek.com>
+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
+ * Hsinchu 300, Taiwan.
+ *
+ * Larry Finger <Larry.Finger@lwfinger.net>
+ *
+ *****************************************************************************/
+
+#ifndef __PHYDMPATHDIV_H__
+#define __PHYDMPATHDIV_H__
+
+#ifdef CONFIG_PATH_DIVERSITY
+#define PATHDIV_VERSION "3.1"
+
+#define USE_PATH_A_AS_DEFAULT_ANT /* @for 8814 dynamic TX path selection */
+
+#define NUM_RESET_DTP_PERIOD 5
+#define ANT_DECT_RSSI_TH 3
+
+#define PATH_A 1
+#define PATH_B 2
+#define PATH_C 3
+#define PATH_D 4
+
+#define PHYDM_AUTO_PATH 0
+#define PHYDM_FIX_PATH 1
+
+#define NUM_CHOOSE2_FROM4 6
+#define NUM_CHOOSE3_FROM4 4
+
+enum phydm_dtp_state {
+	PHYDM_DTP_INIT = 1,
+	PHYDM_DTP_RUNNING_1
+
+};
+
+enum phydm_path_div_type {
+	PHYDM_2R_PATH_DIV = 1,
+	PHYDM_4R_PATH_DIV = 2
+};
+
+void phydm_process_rssi_for_path_div(
+	void *dm_void,
+	void *phy_info_void,
+	void *pkt_info_void);
+
+struct _ODM_PATH_DIVERSITY_ {
+	u8	resp_tx_path;
+	u8	path_sel[ODM_ASSOCIATE_ENTRY_NUM];
+	u32	path_a_sum[ODM_ASSOCIATE_ENTRY_NUM];
+	u32	path_b_sum[ODM_ASSOCIATE_ENTRY_NUM];
+	u16	path_a_cnt[ODM_ASSOCIATE_ENTRY_NUM];
+	u16	path_b_cnt[ODM_ASSOCIATE_ENTRY_NUM];
+	u8	phydm_path_div_type;
+#if RTL8814A_SUPPORT
+
+	u32	path_a_sum_all;
+	u32	path_b_sum_all;
+	u32	path_c_sum_all;
+	u32	path_d_sum_all;
+
+	u32	path_a_cnt_all;
+	u32	path_b_cnt_all;
+	u32	path_c_cnt_all;
+	u32	path_d_cnt_all;
+
+	u8	dtp_period;
+	boolean	is_become_linked;
+	boolean	is_u3_mode;
+	u8	num_tx_path;
+	u8	default_path;
+	u8	num_candidate;
+	u8	ant_candidate_1;
+	u8	ant_candidate_2;
+	u8	ant_candidate_3;
+	u8     phydm_dtp_state;
+	u8	dtp_check_patha_counter;
+	boolean	fix_path_bfer;
+	u8	search_space_2[NUM_CHOOSE2_FROM4];
+	u8	search_space_3[NUM_CHOOSE3_FROM4];
+
+	u8	pre_tx_path;
+	u8	use_path_a_as_default_ant;
+	boolean	is_path_a_exist;
+
+#endif
+};
+
+void phydm_c2h_dtp_handler(void *dm_void, u8 *cmd_buf, u8 cmd_len);
+
+void phydm_path_diversity_init(void *dm_void);
+
+void odm_path_diversity(void *dm_void);
+
+void phydm_pathdiv_debug(void *dm_void, char input[][16], u32 *_used,
+			 char *output, u32 *_out_len);
+
+#endif /* @#ifdef CONFIG_PATH_DIVERSITY */
+#endif /* @#ifndef  __ODMPATHDIV_H__ */
+
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/phydm_phystatus.c linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/phydm_phystatus.c
--- linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/phydm_phystatus.c	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/phydm_phystatus.c	2020-04-10 16:35:06.826660535 +0300
@@ -0,0 +1,3089 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017  Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * The full GNU General Public License is included in this distribution in the
+ * file called LICENSE.
+ *
+ * Contact Information:
+ * wlanfae <wlanfae@realtek.com>
+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
+ * Hsinchu 300, Taiwan.
+ *
+ * Larry Finger <Larry.Finger@lwfinger.net>
+ *
+ *****************************************************************************/
+
+/*@************************************************************
+ * include files
+ ************************************************************/
+
+#include "mp_precomp.h"
+#include "phydm_precomp.h"
+
+void phydm_rx_statistic_cal(struct dm_struct *dm,
+			    struct phydm_phyinfo_struct *phy_info,
+			    u8 *phy_status_inf,
+			    struct phydm_perpkt_info_struct *pktinfo)
+{
+#if (ODM_PHY_STATUS_NEW_TYPE_SUPPORT == 1)
+	struct phy_status_rpt_jaguar2_type1 *phy_sts = NULL;
+	u8 phy_status_type = 0;
+	u8 val = 0;
+#endif
+	u8 is_mu_pkt = 0;
+	struct odm_phy_dbg_info *dbg_i = &dm->phy_dbg_info;
+	u8 rate = (pktinfo->data_rate & 0x7f);
+	u8 bw_idx = phy_info->band_width;
+	u8 offset = 0;
+
+#if (ODM_PHY_STATUS_NEW_TYPE_SUPPORT == 1)
+	phy_sts = (struct phy_status_rpt_jaguar2_type1 *)phy_status_inf;
+	phy_status_type = (*phy_status_inf & 0xf);
+#endif
+	if (rate <= ODM_RATE54M) {
+		dbg_i->num_qry_legacy_pkt[rate]++;
+	} else if (rate <= ODM_RATEMCS31) {
+		dbg_i->ht_pkt_not_zero = true;
+		offset = rate - ODM_RATEMCS0;
+
+		if (dm->support_ic_type & PHYSTS_2ND_TYPE_IC) {
+			if (bw_idx == *dm->band_width) {
+				dbg_i->num_qry_ht_pkt[offset]++;
+
+			} else if (bw_idx == CHANNEL_WIDTH_20) {
+				dbg_i->num_qry_pkt_sc_20m[offset]++;
+				dbg_i->low_bw_20_occur = true;
+			}
+		} else {
+			dbg_i->num_qry_ht_pkt[offset]++;
+		}
+	}
+#if ODM_IC_11AC_SERIES_SUPPORT
+	else if (rate <= ODM_RATEVHTSS4MCS9) {
+		offset = rate - ODM_RATEVHTSS1MCS0;
+
+		#if (ODM_PHY_STATUS_NEW_TYPE_SUPPORT == 1)
+		if ((dm->support_ic_type & PHYSTS_2ND_TYPE_IC) &&
+		    phy_status_type == 1 &&
+		    phy_sts->gid != 0 &&
+		    phy_sts->gid != 63) {
+			is_mu_pkt = 1;
+			/*@*/
+		}
+		#endif
+
+		if (is_mu_pkt) {
+			#if (ODM_PHY_STATUS_NEW_TYPE_SUPPORT == 1)
+			dbg_i->num_mu_vht_pkt[offset]++;
+			#else
+			dbg_i->num_qry_vht_pkt[offset]++; /*@for debug*/
+			#endif
+		} else {
+			dbg_i->vht_pkt_not_zero = true;
+
+			if (dm->support_ic_type & PHYSTS_2ND_TYPE_IC) {
+				if (bw_idx == *dm->band_width) {
+					dbg_i->num_qry_vht_pkt[offset]++;
+
+				} else if (bw_idx == CHANNEL_WIDTH_20) {
+					dbg_i->num_qry_pkt_sc_20m[offset]++;
+					dbg_i->low_bw_20_occur = true;
+				} else {/*@if (bw_idx == CHANNEL_WIDTH_40)*/
+					dbg_i->num_qry_pkt_sc_40m[offset]++;
+					dbg_i->low_bw_40_occur = true;
+				}
+			} else {
+				dbg_i->num_qry_vht_pkt[offset]++;
+			}
+		}
+
+		#if (ODM_PHY_STATUS_NEW_TYPE_SUPPORT == 1)
+		if (pktinfo->ppdu_cnt < 4) {
+			if (is_mu_pkt)
+				val = rate | BIT(7);
+			else
+				val = rate;
+
+			dbg_i->num_of_ppdu[pktinfo->ppdu_cnt] = val;
+			dbg_i->gid_num[pktinfo->ppdu_cnt] = phy_sts->gid;
+		}
+		#endif
+	}
+#endif
+}
+
+void phydm_reset_phystatus_avg(struct dm_struct *dm)
+{
+	struct phydm_phystatus_avg *dbg_avg = NULL;
+
+	dbg_avg = &dm->phy_dbg_info.phystatus_statistic_avg;
+	odm_memory_set(dm, &dbg_avg->rssi_cck_avg, 0,
+		       sizeof(struct phydm_phystatus_avg));
+}
+
+void phydm_reset_phystatus_statistic(struct dm_struct *dm)
+{
+	struct phydm_phystatus_statistic *dbg_s = NULL;
+
+	dbg_s = &dm->phy_dbg_info.physts_statistic_info;
+
+	odm_memory_set(dm, &dbg_s->rssi_cck_sum, 0,
+		       sizeof(struct phydm_phystatus_statistic));
+}
+
+void phydm_avg_phystatus_index(void *dm_void,
+			       struct phydm_phyinfo_struct *phy_info,
+			       struct phydm_perpkt_info_struct *pktinfo)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct odm_phy_dbg_info *dbg_i = &dm->phy_dbg_info;
+	struct phydm_phystatus_statistic *dbg_s = &dbg_i->physts_statistic_info;
+	u8 rssi[PHYSTS_PATH_NUM] = {0};
+	u8 evm[PHYSTS_PATH_NUM] = {0};
+	s8 snr[PHYSTS_PATH_NUM] = {0};
+	u32 size = PHYSTS_PATH_NUM; /*size of path=4*/
+	u16 size_th = PHY_HIST_SIZE - 1; /*size of threshold*/
+	u16 val = 0, intvl = 0;
+	u8 i = 0;
+
+	odm_move_memory(dm, rssi, phy_info->rx_mimo_signal_strength, size);
+	odm_move_memory(dm, evm, phy_info->rx_mimo_evm_dbm, size);
+	odm_move_memory(dm, snr, phy_info->rx_snr, size);
+
+	if (pktinfo->data_rate <= ODM_RATE11M) {
+		/*RSSI*/
+		dbg_s->rssi_cck_sum += rssi[0];
+		dbg_s->rssi_cck_cnt++;
+		return;
+	} else if (pktinfo->data_rate <= ODM_RATE54M) {
+		/*@evm*/
+		dbg_s->evm_ofdm_sum += evm[0];
+
+		/*SNR*/
+		dbg_s->snr_ofdm_sum += snr[0];
+
+		/*RSSI*/
+		dbg_s->rssi_ofdm_sum += rssi[0];
+		dbg_s->rssi_ofdm_cnt++;
+
+		val = (u16)evm[0];
+		intvl = phydm_find_intrvl(dm, val, dbg_i->evm_hist_th, size_th);
+		dbg_s->evm_ofdm_hist[intvl]++;
+
+		val = (u16)snr[0];
+		intvl = phydm_find_intrvl(dm, val, dbg_i->snr_hist_th, size_th);
+		dbg_s->snr_ofdm_hist[intvl]++;
+
+	} else if (pktinfo->rate_ss == 1) {
+/*@===[1-SS]==================================================================*/
+		/*@evm*/
+		dbg_s->evm_1ss_sum += evm[0];
+
+		/*SNR*/
+		dbg_s->snr_1ss_sum += snr[0];
+
+		/*RSSI*/
+		dbg_s->rssi_1ss_sum += rssi[0];
+
+		/*@EVM Histogram*/
+		val = (u16)evm[0];
+		intvl = phydm_find_intrvl(dm, val, dbg_i->evm_hist_th, size_th);
+		dbg_s->evm_1ss_hist[intvl]++;
+
+		/*SNR Histogram*/
+		val = (u16)snr[0];
+		intvl = phydm_find_intrvl(dm, val, dbg_i->snr_hist_th, size_th);
+		dbg_s->snr_1ss_hist[intvl]++;
+
+		dbg_s->rssi_1ss_cnt++;
+	} else if (pktinfo->rate_ss == 2) {
+/*@===[2-SS]==================================================================*/
+		#if (defined(PHYDM_COMPILE_ABOVE_2SS))
+		for (i = 0; i < pktinfo->rate_ss; i++) {
+			/*@evm*/
+			dbg_s->evm_2ss_sum[i] += evm[i];
+			/*SNR*/
+			dbg_s->snr_2ss_sum[i] += snr[i];
+			/*RSSI*/
+			dbg_s->rssi_2ss_sum[i] += rssi[i];
+			/*@EVM Histogram*/
+			val = (u16)evm[i];
+			intvl = phydm_find_intrvl(dm, val, dbg_i->evm_hist_th,
+						  size_th);
+			dbg_s->evm_2ss_hist[i][intvl]++;
+
+			/*SNR Histogram*/
+			val = (u16)snr[i];
+			intvl = phydm_find_intrvl(dm, val, dbg_i->snr_hist_th,
+						  size_th);
+			dbg_s->snr_2ss_hist[i][intvl]++;
+		}
+		dbg_s->rssi_2ss_cnt++;
+		#endif
+	} else if (pktinfo->rate_ss == 3) {
+/*@===[3-SS]==================================================================*/
+		#if (defined(PHYDM_COMPILE_ABOVE_3SS))
+		for (i = 0; i < pktinfo->rate_ss; i++) {
+			/*@evm*/
+			dbg_s->evm_3ss_sum[i] += evm[i];
+			/*SNR*/
+			dbg_s->snr_3ss_sum[i] += snr[i];
+			/*RSSI*/
+			dbg_s->rssi_3ss_sum[i] += rssi[i];
+			/*@EVM Histogram*/
+			val = (u16)evm[i];
+			intvl = phydm_find_intrvl(dm, val, dbg_i->evm_hist_th,
+						  size_th);
+			dbg_s->evm_3ss_hist[i][intvl]++;
+
+			/*SNR Histogram*/
+			val = (u16)snr[i];
+			intvl = phydm_find_intrvl(dm, val, dbg_i->snr_hist_th,
+						  size_th);
+			dbg_s->snr_3ss_hist[i][intvl]++;
+		}
+		dbg_s->rssi_3ss_cnt++;
+		#endif
+	} else if (pktinfo->rate_ss == 4) {
+/*@===[4-SS]==================================================================*/
+		#if (defined(PHYDM_COMPILE_ABOVE_4SS))
+		for (i = 0; i < pktinfo->rate_ss; i++) {
+			/*@evm*/
+			dbg_s->evm_4ss_sum[i] += evm[i];
+			/*SNR*/
+			dbg_s->snr_4ss_sum[i] += snr[i];
+			/*RSSI*/
+			dbg_s->rssi_4ss_sum[i] += rssi[i];
+			/*@EVM Histogram*/
+			val = (u16)evm[i];
+			intvl = phydm_find_intrvl(dm, val, dbg_i->evm_hist_th,
+						  size_th);
+			dbg_s->evm_4ss_hist[i][intvl]++;
+
+			/*SNR Histogram*/
+			val = (u16)snr[i];
+			intvl = phydm_find_intrvl(dm, val, dbg_i->snr_hist_th,
+						  size_th);
+			dbg_s->snr_4ss_hist[i][intvl]++;
+		}
+		dbg_s->rssi_4ss_cnt++;
+		#endif
+	}
+}
+
+void phydm_avg_phystatus_init(void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct odm_phy_dbg_info *dbg_i = &dm->phy_dbg_info;
+	u16 snr_hist_th[PHY_HIST_SIZE - 1] = {5, 8, 11, 14, 17, 20, 23, 26,
+					      29, 32, 35};
+	u16 evm_hist_th[PHY_HIST_SIZE - 1] = {5, 8, 11, 14, 17, 20, 23, 26,
+					      29, 32, 35};
+	u32 size = (PHY_HIST_SIZE - 1) * 2;
+
+	odm_move_memory(dm, dbg_i->snr_hist_th, snr_hist_th, size);
+	odm_move_memory(dm, dbg_i->evm_hist_th, evm_hist_th, size);
+}
+
+u8 phydm_get_signal_quality(struct phydm_phyinfo_struct *phy_info,
+			    struct dm_struct *dm,
+			    struct phy_status_rpt_8192cd *phy_sts)
+{
+	u8 sq_rpt;
+	u8 result = 0;
+
+	if (phy_info->rx_pwdb_all > 40 && !dm->is_in_hct_test) {
+		result = 100;
+	} else {
+		sq_rpt = phy_sts->cck_sig_qual_ofdm_pwdb_all;
+
+		if (sq_rpt > 64)
+			result = 0;
+		else if (sq_rpt < 20)
+			result = 100;
+		else
+			result = ((64 - sq_rpt) * 100) / 44;
+	}
+
+	return result;
+}
+
+u8 phydm_pwr_2_percent(s8 ant_power)
+{
+	if ((ant_power <= -100) || ant_power >= 20)
+		return 0;
+	else if (ant_power >= 0)
+		return 100;
+	else
+		return 100 + ant_power;
+}
+
+#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
+
+#if 0 /*(DM_ODM_SUPPORT_TYPE == ODM_CE)*/
+s32 phydm_signal_scale_mapping_92c_series(struct dm_struct *dm, s32 curr_sig)
+{
+	s32 ret_sig = 0;
+
+#if (DEV_BUS_TYPE == RT_PCI_INTERFACE)
+	if (dm->support_interface == ODM_ITRF_PCIE) {
+		/* step 1. Scale mapping. */
+		if (curr_sig >= 61 && curr_sig <= 100)
+			ret_sig = 90 + ((curr_sig - 60) / 4);
+		else if (curr_sig >= 41 && curr_sig <= 60)
+			ret_sig = 78 + ((curr_sig - 40) / 2);
+		else if (curr_sig >= 31 && curr_sig <= 40)
+			ret_sig = 66 + (curr_sig - 30);
+		else if (curr_sig >= 21 && curr_sig <= 30)
+			ret_sig = 54 + (curr_sig - 20);
+		else if (curr_sig >= 5 && curr_sig <= 20)
+			ret_sig = 42 + (((curr_sig - 5) * 2) / 3);
+		else if (curr_sig == 4)
+			ret_sig = 36;
+		else if (curr_sig == 3)
+			ret_sig = 27;
+		else if (curr_sig == 2)
+			ret_sig = 18;
+		else if (curr_sig == 1)
+			ret_sig = 9;
+		else
+			ret_sig = curr_sig;
+	}
+#endif
+
+#if ((DEV_BUS_TYPE == RT_USB_INTERFACE) || (DEV_BUS_TYPE == RT_SDIO_INTERFACE))
+	if (dm->support_interface == ODM_ITRF_USB ||
+	    dm->support_interface == ODM_ITRF_SDIO) {
+		if (curr_sig >= 51 && curr_sig <= 100)
+			ret_sig = 100;
+		else if (curr_sig >= 41 && curr_sig <= 50)
+			ret_sig = 80 + ((curr_sig - 40) * 2);
+		else if (curr_sig >= 31 && curr_sig <= 40)
+			ret_sig = 66 + (curr_sig - 30);
+		else if (curr_sig >= 21 && curr_sig <= 30)
+			ret_sig = 54 + (curr_sig - 20);
+		else if (curr_sig >= 10 && curr_sig <= 20)
+			ret_sig = 42 + (((curr_sig - 10) * 2) / 3);
+		else if (curr_sig >= 5 && curr_sig <= 9)
+			ret_sig = 22 + (((curr_sig - 5) * 3) / 2);
+		else if (curr_sig >= 1 && curr_sig <= 4)
+			ret_sig = 6 + (((curr_sig - 1) * 3) / 2);
+		else
+			ret_sig = curr_sig;
+	}
+
+#endif
+	return ret_sig;
+}
+
+s32 phydm_signal_scale_mapping(struct dm_struct *dm, s32 curr_sig)
+{
+#ifdef CONFIG_SIGNAL_SCALE_MAPPING
+	return phydm_signal_scale_mapping_92c_series(dm, curr_sig);
+#else
+	return curr_sig;
+#endif
+}
+#endif
+
+void phydm_process_signal_strength(struct dm_struct *dm,
+				   struct phydm_phyinfo_struct *phy_info,
+				   struct phydm_perpkt_info_struct *pktinfo)
+{
+	u8 avg_rssi = 0, tmp_rssi = 0, best_rssi = 0, second_rssi = 0;
+	u8 ss = 0; /*signal strenth after scale mapping*/
+	u8 pwdb = phy_info->rx_pwdb_all;
+	u8 i;
+
+	/*use the best two RSSI only*/
+	for (i = RF_PATH_A; i < PHYDM_MAX_RF_PATH; i++) {
+		tmp_rssi = phy_info->rx_mimo_signal_strength[i];
+
+		/*@Get the best two RSSI*/
+		if (tmp_rssi > best_rssi && tmp_rssi > second_rssi) {
+			second_rssi = best_rssi;
+			best_rssi = tmp_rssi;
+		} else if (tmp_rssi > second_rssi && tmp_rssi <= best_rssi) {
+			second_rssi = tmp_rssi;
+		}
+	}
+
+	if (best_rssi == 0)
+		return;
+
+	if (pktinfo->rate_ss == 1)
+		avg_rssi = best_rssi;
+	else
+		avg_rssi = (best_rssi + second_rssi) >> 1;
+
+	if (dm->support_ic_type & PHYSTS_2ND_TYPE_IC) {
+	#if (ODM_PHY_STATUS_NEW_TYPE_SUPPORT == 1)
+		/* Update signal strength to UI,
+		 * and phy_info->rx_pwdb_all is the maximum RSSI of all path
+		 */
+		#if 1 /*(DM_ODM_SUPPORT_TYPE == ODM_WIN)*/
+		ss = SignalScaleProc(dm->adapter, pwdb, false, false);
+		#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
+		ss = (u8)phydm_signal_scale_mapping(dm, pwdb);
+		#endif
+
+	#endif
+	} else if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
+	#if ODM_IC_11AC_SERIES_SUPPORT
+		if (pktinfo->is_cck_rate)
+			#if 1/*(DM_ODM_SUPPORT_TYPE == ODM_WIN)*/
+			ss = SignalScaleProc(dm->adapter, pwdb, 0, 1);
+			#else
+			ss = (u8)phydm_signal_scale_mapping(dm, pwdb);
+			#endif
+		else
+			#if 1 /*(DM_ODM_SUPPORT_TYPE == ODM_WIN)*/
+			ss = SignalScaleProc(dm->adapter, avg_rssi, 0, 1);
+			#else
+			ss = (u8)phydm_signal_scale_mapping(dm, avg_rssi);
+			#endif
+	#endif
+	} else if (dm->support_ic_type & ODM_IC_11N_SERIES) {
+	#if ODM_IC_11N_SERIES_SUPPORT
+		if (pktinfo->is_cck_rate)
+			#if 1/*(DM_ODM_SUPPORT_TYPE == ODM_WIN)*/
+			ss = SignalScaleProc(dm->adapter, pwdb, 1, 1);
+			#else
+			ss = (u8)phydm_signal_scale_mapping(dm, pwdb);
+			#endif
+		else
+			#if 1 /*(DM_ODM_SUPPORT_TYPE == ODM_WIN)*/
+			ss = SignalScaleProc(dm->adapter, avg_rssi, 1, 0);
+			#else
+			ss = (u8)phydm_signal_scale_mapping(dm, avg_rssi);
+			#endif
+	#endif
+	}
+	phy_info->signal_strength = ss;
+}
+#endif
+
+#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
+static u8 phydm_sq_patch_lenovo(
+	struct dm_struct *dm,
+	u8 is_cck_rate,
+	u8 pwdb_all,
+	u8 path,
+	u8 RSSI)
+{
+	u8 sq = 0;
+
+	if (is_cck_rate) {
+		if (dm->support_ic_type & ODM_RTL8192E) {
+/*@
+ * <Roger_Notes>
+ * Expected signal strength and bars indication at Lenovo lab. 2013.04.11
+ * 802.11n, 802.11b, 802.11g only at channel 6
+ *
+ *	Attenuation (dB)	OS Signal Bars	RSSI by Xirrus (dBm)
+ *		50				5			-49
+ *		55				5			-49
+ *		60				5			-50
+ *		65				5			-51
+ *		70				5			-52
+ *		75				5			-54
+ *		80				5			-55
+ *		85				4			-60
+ *		90				3			-63
+ *		95				3			-65
+ *		100				2			-67
+ *		102				2			-67
+ *		104				1			-70
+ */
+			if (pwdb_all >= 50)
+				sq = 100;
+			else if (pwdb_all >= 35 && pwdb_all < 50)
+				sq = 80;
+			else if (pwdb_all >= 31 && pwdb_all < 35)
+				sq = 60;
+			else if (pwdb_all >= 22 && pwdb_all < 31)
+				sq = 40;
+			else if (pwdb_all >= 18 && pwdb_all < 22)
+				sq = 20;
+			else
+				sq = 10;
+		} else {
+			if (pwdb_all >= 50)
+				sq = 100;
+			else if (pwdb_all >= 35 && pwdb_all < 50)
+				sq = 80;
+			else if (pwdb_all >= 22 && pwdb_all < 35)
+				sq = 60;
+			else if (pwdb_all >= 18 && pwdb_all < 22)
+				sq = 40;
+			else
+				sq = 10;
+		}
+
+	} else {
+		/* OFDM rate */
+
+		if (dm->support_ic_type & ODM_RTL8192E) {
+			if (RSSI >= 45)
+				sq = 100;
+			else if (RSSI >= 22 && RSSI < 45)
+				sq = 80;
+			else if (RSSI >= 18 && RSSI < 22)
+				sq = 40;
+			else
+				sq = 20;
+		} else {
+			if (RSSI >= 45)
+				sq = 100;
+			else if (RSSI >= 22 && RSSI < 45)
+				sq = 80;
+			else if (RSSI >= 18 && RSSI < 22)
+				sq = 40;
+			else
+				sq = 20;
+		}
+	}
+	return sq;
+}
+
+static u8 phydm_sq_patch_rt_cid_819x_acer(
+	struct dm_struct *dm,
+	u8 is_cck_rate,
+	u8 pwdb_all,
+	u8 path,
+	u8 RSSI)
+{
+	u8 sq = 0;
+
+	if (is_cck_rate) {
+#if OS_WIN_FROM_WIN8(OS_VERSION)
+		if (pwdb_all >= 50)
+			sq = 100;
+		else if (pwdb_all >= 35 && pwdb_all < 50)
+			sq = 80;
+		else if (pwdb_all >= 30 && pwdb_all < 35)
+			sq = 60;
+		else if (pwdb_all >= 25 && pwdb_all < 30)
+			sq = 40;
+		else if (pwdb_all >= 20 && pwdb_all < 25)
+			sq = 20;
+		else
+			sq = 10;
+#else
+		if (pwdb_all >= 50)
+			sq = 100;
+		else if (pwdb_all >= 35 && pwdb_all < 50)
+			sq = 80;
+		else if (pwdb_all >= 30 && pwdb_all < 35)
+			sq = 60;
+		else if (pwdb_all >= 25 && pwdb_all < 30)
+			sq = 40;
+		else if (pwdb_all >= 20 && pwdb_all < 25)
+			sq = 20;
+		else
+			sq = 10;
+
+		/* @Abnormal case, do not indicate the value above 20 on Win7 */
+		if (pwdb_all == 0)
+			sq = 20;
+#endif
+
+	} else {
+		/* OFDM rate */
+		if (dm->support_ic_type & ODM_RTL8192E) {
+			if (RSSI >= 45)
+				sq = 100;
+			else if (RSSI >= 22 && RSSI < 45)
+				sq = 80;
+			else if (RSSI >= 18 && RSSI < 22)
+				sq = 40;
+			else
+				sq = 20;
+		} else {
+			if (RSSI >= 35)
+				sq = 100;
+			else if (RSSI >= 30 && RSSI < 35)
+				sq = 80;
+			else if (RSSI >= 25 && RSSI < 30)
+				sq = 40;
+			else
+				sq = 20;
+		}
+	}
+	return sq;
+}
+#endif
+
+static u8
+phydm_evm_2_percent(s8 value)
+{
+	/* @-33dB~0dB to 0%~99% */
+	s8 ret_val;
+
+	ret_val = value;
+	ret_val /= 2;
+
+/*@dbg_print("value=%d\n", value);*/
+#ifdef ODM_EVM_ENHANCE_ANTDIV
+	if (ret_val >= 0)
+		ret_val = 0;
+
+	if (ret_val <= -40)
+		ret_val = -40;
+
+	ret_val = 0 - ret_val;
+	ret_val *= 3;
+#else
+	if (ret_val >= 0)
+		ret_val = 0;
+
+	if (ret_val <= -33)
+		ret_val = -33;
+
+	ret_val = 0 - ret_val;
+	ret_val *= 3;
+
+	if (ret_val == 99)
+		ret_val = 100;
+#endif
+
+	return (u8)ret_val;
+}
+
+static u8
+phydm_evm_dbm(s8 value)
+{
+	s8 ret_val = value;
+
+	/* @-33dB~0dB to 33dB ~ 0dB */
+	if (ret_val == -128)
+		ret_val = 127;
+	else if (ret_val < 0)
+		ret_val = 0 - ret_val;
+
+	ret_val = ret_val >> 1;
+	return (u8)ret_val;
+}
+
+static s16
+phydm_cfo(s8 value)
+{
+	s16 ret_val;
+
+	if (value < 0) {
+		ret_val = 0 - value;
+		ret_val = (ret_val << 1) + (ret_val >> 1); /*@2.5~=312.5/2^7 */
+		ret_val = ret_val | BIT(12); /*set bit12 as 1 for negative cfo*/
+	} else {
+		ret_val = value;
+		ret_val = (ret_val << 1) + (ret_val >> 1); /* @*2.5~=312.5/2^7*/
+	}
+	return ret_val;
+}
+
+s8 phydm_cck_rssi_convert(struct dm_struct *dm, u16 lna_idx, u8 vga_idx)
+{
+	/*@phydm_get_cck_rssi_table_from_reg*/
+	return (dm->cck_lna_gain_table[lna_idx] - (vga_idx << 1));
+}
+
+void phydm_get_cck_rssi_table_from_reg(struct dm_struct *dm)
+{
+	u8 used_lna_idx_tmp;
+	u32 reg_0xa80 = 0x7431, reg_0xabc = 0xcbe5edfd;
+	u32 val = 0;
+	u8 i;
+
+	/*@example: {-53, -43, -33, -27, -19, -13, -3, 1}*/
+	/*@{0xCB, 0xD5, 0xDF, 0xE5, 0xED, 0xF3, 0xFD, 0x2}*/
+
+	PHYDM_DBG(dm, ODM_COMP_INIT, "CCK LNA Gain table init\n");
+
+	if (!(dm->support_ic_type & (ODM_RTL8197F)))
+		return;
+
+	reg_0xa80 = odm_get_bb_reg(dm, R_0xa80, 0xFFFF);
+	reg_0xabc = odm_get_bb_reg(dm, R_0xabc, MASKDWORD);
+
+	PHYDM_DBG(dm, ODM_COMP_INIT, "reg_0xa80 = 0x%x\n", reg_0xa80);
+	PHYDM_DBG(dm, ODM_COMP_INIT, "reg_0xabc = 0x%x\n", reg_0xabc);
+
+	for (i = 0; i <= 3; i++) {
+		used_lna_idx_tmp = (u8)((reg_0xa80 >> (4 * i)) & 0x7);
+		val = (reg_0xabc >> (8 * i)) & 0xff;
+		dm->cck_lna_gain_table[used_lna_idx_tmp] = (s8)val;
+	}
+
+	PHYDM_DBG(dm, ODM_COMP_INIT,
+		  "cck_lna_gain_table = {%d,%d,%d,%d,%d,%d,%d,%d}\n",
+		  dm->cck_lna_gain_table[0], dm->cck_lna_gain_table[1],
+		  dm->cck_lna_gain_table[2], dm->cck_lna_gain_table[3],
+		  dm->cck_lna_gain_table[4], dm->cck_lna_gain_table[5],
+		  dm->cck_lna_gain_table[6], dm->cck_lna_gain_table[7]);
+}
+
+s8 phydm_get_cck_rssi(void *dm_void, u8 lna_idx, u8 vga_idx)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	s8 rx_pow = 0;
+
+	switch (dm->support_ic_type) {
+	#if (RTL8197F_SUPPORT == 1)
+	case ODM_RTL8197F:
+		rx_pow = phydm_cck_rssi_convert(dm, lna_idx, vga_idx);
+		break;
+	#endif
+
+	#if (RTL8723D_SUPPORT == 1)
+	case ODM_RTL8723D:
+		rx_pow = phydm_cckrssi_8723d(dm, lna_idx, vga_idx);
+		break;
+	#endif
+
+	#if (RTL8710B_SUPPORT == 1)
+	case ODM_RTL8710B:
+		rx_pow = phydm_cckrssi_8710b(dm, lna_idx, vga_idx);
+		break;
+	#endif
+
+	#if (RTL8192F_SUPPORT == 1)
+	case ODM_RTL8192F:
+		rx_pow = phydm_cckrssi_8192f(dm, lna_idx, vga_idx);
+		break;
+	#endif
+
+	#if (RTL8821C_SUPPORT == 1)
+	case ODM_RTL8821C:
+		rx_pow = phydm_cck_rssi_8821c(dm, lna_idx, vga_idx);
+		break;
+	#endif
+
+	#if (RTL8195B_SUPPORT == 1)
+	case ODM_RTL8195B:
+		rx_pow = phydm_cck_rssi_8195B(dm, lna_idx, vga_idx);
+		break;
+	#endif
+
+	#if (RTL8188E_SUPPORT == 1)
+	case ODM_RTL8188E:
+		rx_pow = phydm_cck_rssi_8188e(dm, lna_idx, vga_idx);
+		break;
+	#endif
+
+	#if (RTL8192E_SUPPORT == 1)
+	case ODM_RTL8192E:
+		rx_pow = phydm_cck_rssi_8192e(dm, lna_idx, vga_idx);
+		break;
+	#endif
+
+	#if (RTL8723B_SUPPORT == 1)
+	case ODM_RTL8723B:
+		rx_pow = phydm_cck_rssi_8723b(dm, lna_idx, vga_idx);
+		break;
+	#endif
+
+	#if (RTL8703B_SUPPORT == 1)
+	case ODM_RTL8703B:
+		rx_pow = phydm_cck_rssi_8703b(dm, lna_idx, vga_idx);
+		break;
+	#endif
+
+	#if (RTL8188F_SUPPORT == 1)
+	case ODM_RTL8188F:
+		rx_pow = phydm_cck_rssi_8188f(dm, lna_idx, vga_idx);
+		break;
+	#endif
+
+	#if (RTL8195A_SUPPORT == 1)
+	case ODM_RTL8195A:
+		rx_pow = phydm_cck_rssi_8195a(dm, lna_idx, vga_idx);
+		break;
+	#endif
+
+	#if (RTL8812A_SUPPORT == 1)
+	case ODM_RTL8812:
+		rx_pow = phydm_cck_rssi_8812a(dm, lna_idx, vga_idx);
+		break;
+	#endif
+
+	#if (RTL8821A_SUPPORT == 1) || (RTL8881A_SUPPORT == 1)
+	case ODM_RTL8821:
+	case ODM_RTL8881A:
+		rx_pow = phydm_cck_rssi_8821a(dm, lna_idx, vga_idx);
+		break;
+	#endif
+
+	#if (RTL8814A_SUPPORT == 1)
+	case ODM_RTL8814A:
+		rx_pow = phydm_cck_rssi_8814a(dm, lna_idx, vga_idx);
+		break;
+	#endif
+
+	default:
+		break;
+	}
+
+	return rx_pow;
+}
+
+#if (ODM_IC_11N_SERIES_SUPPORT == 1)
+void phydm_phy_sts_n_parsing(struct dm_struct *dm,
+			     struct phydm_phyinfo_struct *phy_info,
+			     u8 *phy_status_inf,
+			     struct phydm_perpkt_info_struct *pktinfo)
+{
+	u8 i = 0;
+	s8 rx_pwr[4], rx_pwr_all = 0;
+	u8 EVM, pwdb_all = 0, pwdb_all_bt = 0;
+	u8 RSSI, total_rssi = 0;
+	u8 rf_rx_num = 0;
+	u8 lna_idx = 0;
+	u8 vga_idx = 0;
+	u8 cck_agc_rpt;
+	s8 evm_tmp = 0;
+	u8 sq = 0;
+	u8 val_tmp = 0;
+	s8 val_s8 = 0;
+	struct phy_status_rpt_8192cd *phy_sts = NULL;
+
+	phy_sts = (struct phy_status_rpt_8192cd *)phy_status_inf;
+
+	if (pktinfo->is_cck_rate) {
+		cck_agc_rpt = phy_sts->cck_agc_rpt_ofdm_cfosho_a;
+
+		/*@3 bit LNA*/
+		lna_idx = ((cck_agc_rpt & 0xE0) >> 5);
+		vga_idx = (cck_agc_rpt & 0x1F);
+
+		#if (RTL8703B_SUPPORT == 1)
+		if (dm->support_ic_type & (ODM_RTL8703B) &&
+		    dm->cck_agc_report_type == 1) {
+			/*@4 bit LNA*/
+			if (phy_sts->cck_rpt_b_ofdm_cfosho_b & BIT(7))
+				val_tmp = 1;
+			else
+				val_tmp = 0;
+			lna_idx = (val_tmp << 3) | lna_idx;
+		}
+		#endif
+
+		rx_pwr_all = phydm_get_cck_rssi(dm, lna_idx, vga_idx);
+
+		PHYDM_DBG(dm, DBG_RSSI_MNTR,
+			  "ext_lna_gain (( %d )), lna_idx: (( 0x%x )), vga_idx: (( 0x%x )), rx_pwr_all: (( %d ))\n",
+			  dm->ext_lna_gain, lna_idx, vga_idx, rx_pwr_all);
+
+		if (dm->board_type & ODM_BOARD_EXT_LNA)
+			rx_pwr_all -= dm->ext_lna_gain;
+
+		pwdb_all = phydm_pwr_2_percent(rx_pwr_all);
+
+		if (pktinfo->is_to_self) {
+			dm->cck_lna_idx = lna_idx;
+			dm->cck_vga_idx = vga_idx;
+		}
+
+		phy_info->rx_pwdb_all = pwdb_all;
+		phy_info->bt_rx_rssi_percentage = pwdb_all;
+		phy_info->recv_signal_power = rx_pwr_all;
+
+		/* @(3) Get Signal Quality (EVM) */
+		#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
+		if (dm->iot_table.win_patch_id == RT_CID_819X_LENOVO)
+			sq = phydm_sq_patch_lenovo(dm, pktinfo->is_cck_rate, pwdb_all, 0, 0);
+		else if (dm->iot_table.win_patch_id == RT_CID_819X_ACER)
+			sq = phydm_sq_patch_rt_cid_819x_acer(dm, pktinfo->is_cck_rate, pwdb_all, 0, 0);
+		else
+		#endif
+			sq = phydm_get_signal_quality(phy_info, dm, phy_sts);
+
+#if 0
+		/* @dbg_print("cck sq = %d\n", sq); */
+#endif
+		phy_info->signal_quality = sq;
+		phy_info->rx_mimo_signal_quality[RF_PATH_A] = sq;
+		phy_info->rx_mimo_signal_quality[RF_PATH_B] = -1;
+
+		for (i = RF_PATH_A; i < PHYDM_MAX_RF_PATH; i++) {
+			if (i == 0)
+				phy_info->rx_mimo_signal_strength[0] = pwdb_all;
+			else
+				phy_info->rx_mimo_signal_strength[i] = 0;
+		}
+	} else { /* @2 is OFDM rate */
+
+		/* @(1)Get RSSI for HT rate */
+
+		for (i = RF_PATH_A; i < dm->num_rf_path; i++) {
+			if (dm->rf_path_rx_enable & BIT(i))
+				rf_rx_num++;
+
+			val_s8 = phy_sts->path_agc[i].gain & 0x3F;
+			rx_pwr[i] = (val_s8 * 2) - 110;
+
+			if (pktinfo->is_to_self)
+				dm->ofdm_agc_idx[i] = val_s8;
+
+			phy_info->rx_pwr[i] = rx_pwr[i];
+			RSSI = phydm_pwr_2_percent(rx_pwr[i]);
+			total_rssi += RSSI;
+
+			phy_info->rx_mimo_signal_strength[i] = (u8)RSSI;
+
+			/* @Get Rx snr value in DB */
+			val_s8 = (s8)(phy_sts->path_rxsnr[i] / 2);
+			phy_info->rx_snr[i] = val_s8;
+
+			/* Record Signal Strength for next packet */
+
+			#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
+			if (i == RF_PATH_A) {
+				if (dm->iot_table.win_patch_id == RT_CID_819X_LENOVO) {
+					phy_info->signal_quality = phydm_sq_patch_lenovo(dm, pktinfo->is_cck_rate, pwdb_all, i, RSSI);
+				} else if (dm->iot_table.win_patch_id == RT_CID_819X_ACER)
+					phy_info->signal_quality = phydm_sq_patch_rt_cid_819x_acer(dm, pktinfo->is_cck_rate, pwdb_all, 0, RSSI);
+			}
+			#endif
+		}
+
+		/* @(2)PWDB, Average PWDB calculated by hardware (for RA) */
+		val_s8 = phy_sts->cck_sig_qual_ofdm_pwdb_all >> 1;
+		rx_pwr_all = (val_s8  & 0x7f) - 110;
+
+		pwdb_all = phydm_pwr_2_percent(rx_pwr_all);
+		pwdb_all_bt = pwdb_all;
+
+		phy_info->rx_pwdb_all = pwdb_all;
+		phy_info->bt_rx_rssi_percentage = pwdb_all_bt;
+		phy_info->rx_power = rx_pwr_all;
+		phy_info->recv_signal_power = rx_pwr_all;
+
+		/* @(3)EVM of HT rate */
+		for (i = 0; i < pktinfo->rate_ss; i++) {
+		/* @Do not use shift operation like "rx_evmX >>= 1"
+		 * because the compilor of free build environment
+		 * fill most significant bit to "zero" when doing shifting
+		 * operation which may change a negative
+		 * value to positive one, then the dbm value
+		 * (which is supposed to be negative) is not correct anymore.
+		 */
+			EVM = phydm_evm_2_percent(phy_sts->stream_rxevm[i]);
+
+			/*@Fill value in RFD, Get the 1st spatial stream only*/
+			if (i == RF_PATH_A)
+				phy_info->signal_quality = (u8)(EVM & 0xff);
+
+			phy_info->rx_mimo_signal_quality[i] = (u8)(EVM & 0xff);
+
+			if (phy_sts->stream_rxevm[i] < 0)
+				evm_tmp = 0 - phy_sts->stream_rxevm[i];
+
+			if (evm_tmp == 64)
+				evm_tmp = 0;
+
+			phy_info->rx_mimo_evm_dbm[i] = (u8)evm_tmp;
+		}
+		phydm_parsing_cfo(dm, pktinfo,
+				  phy_sts->path_cfotail, pktinfo->rate_ss);
+	}
+
+	#ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY
+	dm->dm_fat_table.antsel_rx_keep_0 = phy_sts->ant_sel;
+	dm->dm_fat_table.antsel_rx_keep_1 = phy_sts->ant_sel_b;
+	dm->dm_fat_table.antsel_rx_keep_2 = phy_sts->antsel_rx_keep_2;
+	#endif
+}
+#endif
+
+#if ODM_IC_11AC_SERIES_SUPPORT
+
+void phydm_rx_physts_bw_parsing(struct phydm_phyinfo_struct *phy_info,
+				struct phydm_perpkt_info_struct *
+				pktinfo,
+				struct phy_status_rpt_8812 *
+				phy_sts)
+{
+	if (pktinfo->data_rate <= ODM_RATE54M) {
+		switch (phy_sts->r_RFMOD) {
+		case 1:
+			if (phy_sts->sub_chnl == 0)
+				phy_info->band_width = 1;
+			else
+				phy_info->band_width = 0;
+			break;
+
+		case 2:
+			if (phy_sts->sub_chnl == 0)
+				phy_info->band_width = 2;
+			else if (phy_sts->sub_chnl == 9 ||
+				 phy_sts->sub_chnl == 10)
+				phy_info->band_width = 1;
+			else
+				phy_info->band_width = 0;
+			break;
+
+		default:
+		case 0:
+			phy_info->band_width = 0;
+			break;
+		}
+	}
+}
+
+void phydm_get_sq(struct dm_struct *dm, struct phydm_phyinfo_struct *phy_info,
+		  u8 is_cck_rate)
+{
+	u8 sq = 0;
+	u8 pwdb_all = phy_info->rx_pwdb_all; /*precentage*/
+	#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
+	u8 rssi = phy_info->rx_mimo_signal_strength[0];
+	#endif
+
+	#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
+	if (dm->iot_table.win_patch_id == RT_CID_819X_LENOVO) {
+		if (is_cck_rate)
+			sq = phydm_sq_patch_lenovo(dm, 1, pwdb_all, 0, 0);
+		else
+			sq = phydm_sq_patch_lenovo(dm, 0, pwdb_all, 0, rssi);
+	} else
+	#endif
+	{
+		if (is_cck_rate) {
+			if (pwdb_all > 40 && !dm->is_in_hct_test) {
+				sq = 100;
+			} else {
+				if (pwdb_all > 64)
+					sq = 0;
+				else if (pwdb_all < 20)
+					sq = 100;
+				else
+					sq = ((64 - pwdb_all) * 100) / 44;
+			}
+		} else {
+			sq = phy_info->rx_mimo_signal_quality[0];
+		}
+	}
+
+#if 0
+	/* @dbg_print("cck sq = %d\n", sq); */
+#endif
+	phy_info->signal_quality = sq;
+}
+
+void phydm_rx_physts_1st_type(struct dm_struct *dm,
+			      struct phydm_phyinfo_struct *phy_info,
+			      u8 *phy_status_inf,
+			      struct phydm_perpkt_info_struct *pktinfo)
+{
+	u8 i = 0;
+	s8 rx_pwr_db = 0;
+	u8 val = 0; /*tmp value*/
+	s8 val_s8 = 0; /*tmp value*/
+	u8 rssi = 0; /*pre path RSSI*/
+	u8 rf_rx_num = 0;
+	u8 lna_idx = 0, vga_idx = 0;
+	u8 cck_agc_rpt = 0;
+	struct phy_status_rpt_8812 *phy_sts = NULL;
+	#ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY
+	struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
+	#endif
+
+	phy_sts = (struct phy_status_rpt_8812 *)phy_status_inf;
+	phydm_rx_physts_bw_parsing(phy_info, pktinfo, phy_sts);
+
+	/* @== [CCK rate] ====================================================*/
+	if (pktinfo->is_cck_rate) {
+		cck_agc_rpt = phy_sts->cfosho[0];
+		lna_idx = (cck_agc_rpt & 0xE0) >> 5;
+		vga_idx = cck_agc_rpt & 0x1F;
+
+		rx_pwr_db = phydm_get_cck_rssi(dm, lna_idx, vga_idx);
+		rssi = phydm_pwr_2_percent(rx_pwr_db);
+
+		if (dm->support_ic_type == ODM_RTL8812 &&
+		    !dm->is_cck_high_power) {
+			if (rssi >= 80) {
+				rssi = ((rssi - 80) << 1) +
+					   ((rssi - 80) >> 1) + 80;
+			} else if ((rssi <= 78) && (rssi >= 20)) {
+				rssi += 3;
+			}
+		}
+		dm->cck_lna_idx = lna_idx;
+		dm->cck_vga_idx = vga_idx;
+
+		phy_info->rx_pwdb_all = rssi;
+		phy_info->rx_mimo_signal_strength[0] = rssi;
+	} else {
+	/* @== [OFDM rate] ===================================================*/
+		for (i = RF_PATH_A; i < dm->num_rf_path; i++) {
+			/*@[RSSI]*/
+			if (dm->rf_path_rx_enable & BIT(i))
+				rf_rx_num++;
+
+			if (i < RF_PATH_C)
+				val = phy_sts->gain_trsw[i];
+			else
+				val = phy_sts->gain_trsw_cd[i - 2];
+
+			phy_info->rx_pwr[i] = (val & 0x7F) - 110;
+			rssi = phydm_pwr_2_percent(phy_info->rx_pwr[i]);
+			phy_info->rx_mimo_signal_strength[i] = rssi;
+
+			/*@[SNR]*/
+			if (i < RF_PATH_C)
+				val_s8 = phy_sts->rxsnr[i];
+			else if (dm->support_ic_type & (ODM_RTL8814A))
+				val_s8 = (s8)phy_sts->csi_current[i - 2];
+
+			phy_info->rx_snr[i] = val_s8 >> 1;
+
+			/*@[CFO_short  & CFO_tail]*/
+			if (i < RF_PATH_C) {
+				val_s8 = phy_sts->cfosho[i];
+				phy_info->cfo_short[i] = phydm_cfo(val_s8);
+				val_s8 = phy_sts->cfotail[i];
+				phy_info->cfo_tail[i] = phydm_cfo(val_s8);
+			}
+
+			if (i < RF_PATH_C && pktinfo->is_to_self)
+				dm->ofdm_agc_idx[i] = phy_sts->gain_trsw[i];
+		}
+
+	/* @== [PWDB] ========================================================*/
+
+		/*@(Avg PWDB calculated by hardware*/
+		if (!dm->is_mp_chip) /*@8812, 8821*/
+			val = phy_sts->pwdb_all;
+		else
+			val = phy_sts->pwdb_all >> 1; /*old fomula*/
+
+		rx_pwr_db = (val & 0x7f) - 110;
+		phy_info->rx_pwdb_all = phydm_pwr_2_percent(rx_pwr_db);
+
+		/*@(4)EVM of OFDM rate*/
+		for (i = 0; i < pktinfo->rate_ss; i++) {
+			if (!pktinfo->is_cck_rate &&
+			    pktinfo->data_rate <= ODM_RATE54M) {
+				val_s8 = phy_sts->sigevm;
+			} else if (i < RF_PATH_C) {
+				if (phy_sts->rxevm[i] == -128)
+					phy_sts->rxevm[i] = -25;
+
+				val_s8 = phy_sts->rxevm[i];
+			} else {
+				if (phy_sts->rxevm_cd[i - 2] == -128)
+					phy_sts->rxevm_cd[i - 2] = -25;
+
+				val_s8 = phy_sts->rxevm_cd[i - 2];
+			}
+			/*@[EVM to 0~100%]*/
+			val = phydm_evm_2_percent(val_s8);
+			phy_info->rx_mimo_signal_quality[i] = val;
+			/*@[EVM dBm]*/
+			phy_info->rx_mimo_evm_dbm[i] = phydm_evm_dbm(val_s8);
+		}
+		phydm_parsing_cfo(dm, pktinfo,
+				  phy_sts->cfotail, pktinfo->rate_ss);
+	}
+
+	/* @== [General Info] ================================================*/
+
+	phy_info->rx_power = rx_pwr_db;
+	phy_info->bt_rx_rssi_percentage = phy_info->rx_pwdb_all;
+	phy_info->recv_signal_power = phy_info->rx_power;
+	phydm_get_sq(dm, phy_info, pktinfo->is_cck_rate);
+
+	dm->rx_pwdb_ave = dm->rx_pwdb_ave + phy_info->rx_pwdb_all;
+
+	#ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY
+	fat_tab->hw_antsw_occur = phy_sts->hw_antsw_occur;
+	dm->dm_fat_table.antsel_rx_keep_0 = phy_sts->antidx_anta;
+	dm->dm_fat_table.antsel_rx_keep_1 = phy_sts->antidx_antb;
+	dm->dm_fat_table.antsel_rx_keep_2 = phy_sts->antidx_antc;
+	dm->dm_fat_table.antsel_rx_keep_3 = phy_sts->antidx_antd;
+	#endif
+}
+
+#endif
+
+void phydm_reset_rssi_for_dm(struct dm_struct *dm, u8 station_id)
+{
+	struct cmn_sta_info *sta;
+
+	sta = dm->phydm_sta_info[station_id];
+
+	if (!is_sta_active(sta))
+		return;
+	PHYDM_DBG(dm, DBG_RSSI_MNTR, "Reset RSSI for macid = (( %d ))\n",
+		  station_id);
+
+	sta->rssi_stat.rssi_cck = -1;
+	sta->rssi_stat.rssi_ofdm = -1;
+	sta->rssi_stat.rssi = -1;
+	sta->rssi_stat.ofdm_pkt_cnt = 0;
+	sta->rssi_stat.cck_pkt_cnt = 0;
+	sta->rssi_stat.cck_sum_power = 0;
+	sta->rssi_stat.is_send_rssi = RA_RSSI_STATE_INIT;
+	sta->rssi_stat.packet_map = 0;
+	sta->rssi_stat.valid_bit = 0;
+}
+
+#if (ODM_IC_11N_SERIES_SUPPORT || ODM_IC_11AC_SERIES_SUPPORT)
+
+s32 phydm_get_rssi_8814_ofdm(struct dm_struct *dm, u8 *rssi_in)
+{
+	s32 rssi_avg;
+	u8 rx_count = 0;
+	u32 rssi_linear = 0;
+
+	if (dm->rx_ant_status & BB_PATH_A) {
+		rx_count++;
+		rssi_linear += phydm_db_2_linear(rssi_in[RF_PATH_A]);
+	}
+
+	if (dm->rx_ant_status & BB_PATH_B) {
+		rx_count++;
+		rssi_linear += phydm_db_2_linear(rssi_in[RF_PATH_B]);
+	}
+
+	if (dm->rx_ant_status & BB_PATH_C) {
+		rx_count++;
+		rssi_linear += phydm_db_2_linear(rssi_in[RF_PATH_C]);
+	}
+
+	if (dm->rx_ant_status & BB_PATH_D) {
+		rx_count++;
+		rssi_linear += phydm_db_2_linear(rssi_in[RF_PATH_D]);
+	}
+
+	/* @Calculate average RSSI */
+	switch (rx_count) {
+	case 2:
+		rssi_linear = DIVIDED_2(rssi_linear);
+		break;
+	case 3:
+		rssi_linear = DIVIDED_3(rssi_linear);
+		break;
+	case 4:
+		rssi_linear = DIVIDED_4(rssi_linear);
+		break;
+	}
+	rssi_avg = odm_convert_to_db(rssi_linear);
+
+	return rssi_avg;
+}
+
+void phydm_process_rssi_for_dm(struct dm_struct *dm,
+			       struct phydm_phyinfo_struct *phy_info,
+			       struct phydm_perpkt_info_struct *pktinfo)
+{
+	s32 rssi_ave = 0; /*@average among all paths*/
+	s8 rssi_all = 0; /*@average value of CCK & OFDM*/
+	s8 rssi_cck_tmp = 0, rssi_ofdm_tmp = 0;
+	u8 i = 0;
+	u8 rssi_max = 0, rssi_min = 0;
+	u32 w1 = 0, w2 = 0; /*weighting*/
+	u8 send_rssi_2_fw = 0;
+	u8 *rssi_tmp = NULL;
+	u8 val_tmp = 0;
+	struct cmn_sta_info *sta = NULL;
+	struct rssi_info *rssi_t = NULL;
+	#ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY
+	#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN))
+	struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
+	#endif
+	#endif
+
+	if (pktinfo->station_id >= ODM_ASSOCIATE_ENTRY_NUM)
+		return;
+
+	#ifdef CONFIG_S0S1_SW_ANTENNA_DIVERSITY
+	odm_s0s1_sw_ant_div_by_ctrl_frame_process_rssi(dm, phy_info, pktinfo);
+	#endif
+
+	sta = dm->phydm_sta_info[pktinfo->station_id];
+
+	if (!is_sta_active(sta))
+		return;
+
+	rssi_t = &sta->rssi_stat;
+
+	#ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY
+	#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN))
+	if ((dm->support_ability & ODM_BB_ANT_DIV) &&
+	    fat_tab->enable_ctrl_frame_antdiv) {
+		if (pktinfo->is_packet_match_bssid)
+			dm->data_frame_num++;
+
+		if (fat_tab->use_ctrl_frame_antdiv) {
+			if (!pktinfo->is_to_self) /*@data frame + CTRL frame*/
+				return;
+		} else {
+			/*@data frame only*/
+			if (!pktinfo->is_packet_match_bssid)
+				return;
+		}
+	} else
+	#endif
+	#endif
+	{
+		if (!pktinfo->is_packet_match_bssid) /*@data frame only*/
+			return;
+	}
+
+	if (pktinfo->is_packet_beacon) {
+		dm->phy_dbg_info.num_qry_beacon_pkt++;
+		dm->phy_dbg_info.beacon_phy_rate = pktinfo->data_rate;
+	}
+
+	/* @--------------Statistic for antenna/path diversity--------------- */
+	#if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY))
+	if (dm->support_ability & ODM_BB_ANT_DIV)
+		odm_process_rssi_for_ant_div(dm, phy_info, pktinfo);
+	#endif
+
+	#if (defined(CONFIG_PATH_DIVERSITY))
+	if (dm->support_ability & ODM_BB_PATH_DIV)
+		phydm_process_rssi_for_path_div(dm, phy_info, pktinfo);
+	#endif
+	/* @----------------------------------------------------------------- */
+
+	rssi_cck_tmp = rssi_t->rssi_cck;
+	rssi_ofdm_tmp = rssi_t->rssi_ofdm;
+	rssi_all = rssi_t->rssi;
+
+	if (!(pktinfo->is_packet_to_self || pktinfo->is_packet_beacon))
+		return;
+
+	if (!pktinfo->is_cck_rate) {
+/* @=== [ofdm RSSI] ======================================================== */
+		rssi_tmp = phy_info->rx_mimo_signal_strength;
+
+		#if (RTL8814A_SUPPORT == 1)
+		if (dm->support_ic_type & (ODM_RTL8814A)) {
+			rssi_ave = phydm_get_rssi_8814_ofdm(dm, rssi_tmp);
+		} else
+		#endif
+		{
+			if (rssi_tmp[RF_PATH_B] == 0) {
+				rssi_ave = rssi_tmp[RF_PATH_A];
+			} else {
+				if (rssi_tmp[RF_PATH_A] > rssi_tmp[RF_PATH_B]) {
+					rssi_max = rssi_tmp[RF_PATH_A];
+					rssi_min = rssi_tmp[RF_PATH_B];
+				} else {
+					rssi_max = rssi_tmp[RF_PATH_B];
+					rssi_min = rssi_tmp[RF_PATH_A];
+				}
+				if ((rssi_max - rssi_min) < 3)
+					rssi_ave = rssi_max;
+				else if ((rssi_max - rssi_min) < 6)
+					rssi_ave = rssi_max - 1;
+				else if ((rssi_max - rssi_min) < 10)
+					rssi_ave = rssi_max - 2;
+				else
+					rssi_ave = rssi_max - 3;
+			}
+		}
+
+		/* OFDM MA RSSI */
+		if (rssi_ofdm_tmp <= 0) { /* @initialize */
+			rssi_ofdm_tmp = (s8)phy_info->rx_pwdb_all;
+		} else {
+			rssi_ofdm_tmp = (s8)WEIGHTING_AVG(rssi_ofdm_tmp,
+							  RX_SMOOTH_FACTOR - 1,
+							  rssi_ave, 1);
+			if (phy_info->rx_pwdb_all > (u32)rssi_ofdm_tmp)
+				rssi_ofdm_tmp++;
+		}
+
+		PHYDM_DBG(dm, DBG_RSSI_MNTR, "rssi_ofdm=%d\n", rssi_ofdm_tmp);
+
+		if (rssi_t->ofdm_pkt_cnt != 64) {
+			i = 63;
+			val_tmp = (u8)((rssi_t->packet_map >> i) & BIT(0));
+			rssi_t->ofdm_pkt_cnt -= val_tmp - 1;
+		}
+		rssi_t->packet_map = (rssi_t->packet_map << 1) | BIT(0);
+
+	} else {
+/* @=== [cck RSSI] ========================================================= */
+		rssi_ave = phy_info->rx_pwdb_all;
+
+		if (rssi_t->cck_pkt_cnt <= 63)
+			rssi_t->cck_pkt_cnt++;
+
+		/* @1 Process CCK RSSI */
+		if (rssi_cck_tmp <= 0) { /* @initialize */
+			rssi_cck_tmp = (s8)phy_info->rx_pwdb_all;
+			rssi_t->cck_sum_power = (u16)phy_info->rx_pwdb_all;
+			rssi_t->cck_pkt_cnt = 1; /*reset*/
+			PHYDM_DBG(dm, DBG_RSSI_MNTR, "[1]CCK_INIT\n");
+		} else if (rssi_t->cck_pkt_cnt <= CCK_RSSI_INIT_COUNT) {
+			rssi_t->cck_sum_power = rssi_t->cck_sum_power +
+						(u16)phy_info->rx_pwdb_all;
+
+			rssi_cck_tmp = rssi_t->cck_sum_power /
+				       rssi_t->cck_pkt_cnt;
+
+			PHYDM_DBG(dm, DBG_RSSI_MNTR,
+				  "[2]SumPow=%d, cck_pkt=%d\n",
+				  rssi_t->cck_sum_power, rssi_t->cck_pkt_cnt);
+		} else {
+			rssi_cck_tmp = (s8)WEIGHTING_AVG(rssi_cck_tmp,
+							 RX_SMOOTH_FACTOR - 1,
+							 phy_info->rx_pwdb_all,
+							 1);
+			if (phy_info->rx_pwdb_all > (u32)rssi_cck_tmp)
+				rssi_cck_tmp++;
+		}
+		PHYDM_DBG(dm, DBG_RSSI_MNTR, "rssi_cck=%d\n", rssi_cck_tmp);
+		i = 63;
+		val_tmp = (u8)((rssi_t->packet_map >> i) & BIT(0));
+		rssi_t->ofdm_pkt_cnt -= val_tmp;
+		rssi_t->packet_map = rssi_t->packet_map << 1;
+	}
+/* @=== [ofdm + cck weighting RSSI] ========================================= */
+	if (rssi_t->ofdm_pkt_cnt == 64) {
+		rssi_all = rssi_ofdm_tmp;
+	} else {
+		if (rssi_t->valid_bit < 64)
+			rssi_t->valid_bit++;
+
+		if (rssi_t->valid_bit == 64) {
+			if (rssi_t->ofdm_pkt_cnt > 4)
+				w1 = 64;
+			else
+				w1 = (u32)(rssi_t->ofdm_pkt_cnt << 4);
+
+			w2 = 64 - w1;
+
+			rssi_all = (s8)((w1 * (u32)rssi_ofdm_tmp +
+					 w2 * (u32)rssi_cck_tmp) >> 6);
+		} else if (rssi_t->valid_bit != 0) { /*@(valid_bit > 64)*/
+			w1 = (u32)rssi_t->ofdm_pkt_cnt;
+			w2 = (u32)(rssi_t->valid_bit - rssi_t->ofdm_pkt_cnt);
+			rssi_all = (s8)WEIGHTING_AVG((u32)rssi_ofdm_tmp, w1,
+						     (u32)rssi_cck_tmp, w2);
+		} else {
+			rssi_all = 0;
+		}
+	}
+	PHYDM_DBG(dm, DBG_RSSI_MNTR, "rssi=%d,w1=%d,w2=%d\n", rssi_all, w1, w2);
+
+	if ((rssi_t->ofdm_pkt_cnt >= 1 || rssi_t->cck_pkt_cnt >= 5) &&
+	    rssi_t->is_send_rssi == RA_RSSI_STATE_INIT) {
+		send_rssi_2_fw = 1;
+		rssi_t->is_send_rssi = RA_RSSI_STATE_SEND;
+	}
+
+	rssi_t->rssi_cck = rssi_cck_tmp;
+	rssi_t->rssi_ofdm = rssi_ofdm_tmp;
+	rssi_t->rssi = rssi_all;
+
+	if (send_rssi_2_fw) { /* Trigger init rate by RSSI */
+		if (rssi_t->ofdm_pkt_cnt != 0)
+			rssi_t->rssi = rssi_ofdm_tmp;
+
+		PHYDM_DBG(dm, DBG_RSSI_MNTR,
+			  "[Send to FW] PWDB=%d, ofdm_pkt=%d, cck_pkt=%d\n",
+			  rssi_all, rssi_t->ofdm_pkt_cnt, rssi_t->cck_pkt_cnt);
+	}
+
+#if 0
+	/* @dbg_print("ofdm_pkt=%d, weighting=%d\n", ofdm_pkt_cnt, weighting);*/
+	/* @dbg_print("rssi_ofdm_tmp=%d, rssi_all=%d, rssi_cck_tmp=%d\n", */
+	/*	rssi_ofdm_tmp, rssi_all, rssi_cck_tmp); */
+#endif
+}
+#endif
+
+#ifdef PHYSTS_3RD_TYPE_SUPPORT
+void phydm_print_phystat_jaguar3(struct dm_struct *dm, u8 *phy_sts,
+				 struct phydm_perpkt_info_struct *pktinfo,
+				 struct phydm_phyinfo_struct *phy_info)
+{
+	struct phy_status_rpt_jaguar3_type0 *rpt0 = NULL;
+	struct phy_status_rpt_jaguar3_type1 *rpt1 = NULL;
+	struct phy_status_rpt_jaguar3_type2_type3 *rpt2 = NULL;
+	struct phy_status_rpt_jaguar3_type4 *rpt3 = NULL;
+	struct phy_status_rpt_jaguar3_type5 *rpt4 = NULL;
+	struct odm_phy_dbg_info *dbg = &dm->phy_dbg_info;
+	u8 phy_status_page_num = (*phy_sts & 0xf);
+	u32 phy_status_tmp[PHY_STATUS_JRGUAR3_DW_LEN] = {0};
+	u8 i;
+	u32 size = PHY_STATUS_JRGUAR3_DW_LEN << 2;
+
+	rpt0 = (struct phy_status_rpt_jaguar3_type0 *)phy_sts;
+	rpt1 = (struct phy_status_rpt_jaguar3_type1 *)phy_sts;
+	rpt2 = (struct phy_status_rpt_jaguar3_type2_type3 *)phy_sts;
+	rpt3 = (struct phy_status_rpt_jaguar3_type4 *)phy_sts;
+	rpt4 = (struct phy_status_rpt_jaguar3_type5 *)phy_sts;
+
+	odm_move_memory(dm, phy_status_tmp, phy_sts, size);
+	if (!(dm->debug_components & DBG_PHY_STATUS))
+		return;
+
+	if (dbg->show_phy_sts_all_pkt == 0) {
+		if (!pktinfo->is_packet_match_bssid)
+			return;
+	}
+
+	dbg->show_phy_sts_cnt++;
+
+	if (dbg->show_phy_sts_max_cnt != SHOW_PHY_STATUS_UNLIMITED) {
+		if (dbg->show_phy_sts_cnt > dbg->show_phy_sts_max_cnt)
+			return;
+	}
+
+	pr_debug("Phy Status Rpt: OFDM_%d\n", phy_status_page_num);
+	pr_debug("StaID=%d, RxRate = 0x%x match_bssid=%d\n",
+		 pktinfo->station_id, pktinfo->data_rate,
+		 pktinfo->is_packet_match_bssid);
+
+	for (i = 0; i < PHY_STATUS_JRGUAR3_DW_LEN; i++)
+		pr_debug("Offset[%d:%d] = 0x%x\n",
+			 ((4 * i) + 3), (4 * i), phy_status_tmp[i]);
+
+	if (phy_status_page_num == 0) { /* @CCK(default) */
+		pr_debug("[0] Pkt_cnt=%d, Channel_msb=%d, Pwdb_a=%d, Gain_a=%d, TRSW=%d, AGC_table_b=%d, AGC_table_c=%d,\n",
+			 rpt0->pkt_cnt, rpt0->channel_msb, rpt0->pwdb_a,
+			 rpt0->gain_a, rpt0->trsw, rpt0->agc_table_b,
+			 rpt0->agc_table_c);
+		pr_debug("[4] Path_Sel_o=%d, Gnt_BT_keep_cnt=%d, HW_AntSW_occur_keep_cck=%d,\n Band=%d, Channel=%d, AGC_table_a=%d, l_RXSC=%d, AGC_table_d=%d\n",
+			 rpt0->path_sel_o, rpt0->gnt_bt_keep_cck,
+			 rpt0->hw_antsw_occur_keep_cck, rpt0->band,
+			 rpt0->channel, rpt0->agc_table_a, rpt0->l_rxsc,
+			 rpt0->agc_table_d);
+		pr_debug("[8] AntIdx={%d, %d, %d, %d}, Length=%d\n",
+			 rpt0->antidx_d, rpt0->antidx_c, rpt0->antidx_b,
+			 rpt0->antidx_a, rpt0->length);
+		pr_debug("[12] MF_off=%d, SQloss=%d, lockbit=%d, raterr=%d, rxrate=%d, lna_h_a=%d, CCK_BB_power_a=%d, lna_l_a=%d, vga_a=%d, sq=%d\n",
+			 rpt0->mf_off, rpt0->sqloss, rpt0->lockbit,
+			 rpt0->raterr, rpt0->rxrate, rpt0->lna_h_a,
+			 rpt0->bb_power_a, rpt0->lna_l_a, rpt0->vga_a,
+			 rpt0->signal_quality);
+		pr_debug("[16] Gain_b=%d, lna_h_b=%d, CCK_BB_power_b=%d, lna_l_b=%d, vga_b=%d, Pwdb_b=%d\n",
+			 rpt0->gain_b, rpt0->lna_h_b, rpt0->bb_power_b,
+			 rpt0->lna_l_b, rpt0->vga_b, rpt0->pwdb_b);
+		pr_debug("[20] Gain_c=%d, lna_h_c=%d, CCK_BB_power_c=%d, lna_l_c=%d, vga_c=%d, Pwdb_c=%d\n",
+			 rpt0->gain_c, rpt0->lna_h_c, rpt0->bb_power_c,
+			 rpt0->lna_l_c, rpt0->vga_c, rpt0->pwdb_c);
+		pr_debug("[24] Gain_d=%d, lna_h_d=%d, CCK_BB_power_d=%d, lna_l_d=%d, vga_d=%d, Pwdb_d=%d\n",
+			 rpt0->gain_c, rpt0->lna_h_c, rpt0->bb_power_c,
+			 rpt0->lna_l_c, rpt0->vga_c, rpt0->pwdb_c);
+	} else if (phy_status_page_num == 1) {
+		pr_debug("[0] pwdb[C:A]={%d, %d, %d}, Channel_pri_msb=%d, Pkt_cnt=%d,\n",
+			 rpt1->pwdb_c, rpt1->pwdb_b, rpt1->pwdb_a,
+			 rpt1->channel_pri_msb, rpt1->pkt_cnt);
+		pr_debug("[4] BF: %d, stbc=%d, ldpc=%d, gnt_bt=%d, band=%d, Ch_pri_lsb=%d, rxsc[ht, l]={%d, %d}, pwdb[D]=%d\n",
+			 rpt1->beamformed, rpt1->stbc, rpt1->ldpc, rpt1->gnt_bt,
+			 rpt1->band, rpt1->channel_pri_lsb, rpt1->ht_rxsc,
+			 rpt1->l_rxsc, rpt1->pwdb_d);
+		pr_debug("[8] AntIdx[D:A]={%d, %d, %d, %d}, HW_AntSW_occur[D:A]={%d, %d, %d,%d}, Channel_sec[msb,lsb]={%d, %d}\n",
+			 rpt1->antidx_d, rpt1->antidx_c,
+			 rpt1->antidx_b, rpt1->antidx_a,
+			 rpt1->hw_antsw_occur_d, rpt1->hw_antsw_occur_c,
+			 rpt1->hw_antsw_occur_b, rpt1->hw_antsw_occur_a,
+			 rpt1->channel_sec_msb, rpt1->channel_sec_lsb);
+		pr_debug("[12] GID=%d, PAID[msb,lsb]={%d,%d}\n",
+			 rpt1->gid, rpt1->paid_msb, rpt1->paid);
+		pr_debug("[16] RX_EVM[D:A]={%d, %d, %d, %d}\n",
+			 rpt1->rxevm[3], rpt1->rxevm[2],
+			 rpt1->rxevm[1], rpt1->rxevm[0]);
+		pr_debug("[20] CFO_tail[D:A]={%d, %d, %d, %d}\n",
+			 rpt1->cfo_tail[3], rpt1->cfo_tail[2],
+			 rpt1->cfo_tail[1], rpt1->cfo_tail[0]);
+		pr_debug("[24] RX_SNR[D:A]={%d, %d, %d, %d}\n\n",
+			 rpt1->rxsnr[3], rpt1->rxsnr[2],
+			 rpt1->rxsnr[1], rpt1->rxsnr[0]);
+	} else if (phy_status_page_num == 2 || phy_status_page_num == 3) {
+		pr_debug("[0] pwdb[C:A]={%d, %d, %d}, Channel_mdb=%d, Pkt_cnt=%d\n",
+			 rpt2->pwdb[2], rpt2->pwdb[1], rpt2->pwdb[0],
+			 rpt2->channel_msb, rpt2->pkt_cnt);
+		pr_debug("[4] BF=%d, STBC=%d, LDPC=%d, Gnt_BT=%d, band=%d, CH_lsb=%d, rxsc[ht, l]={%d, %d}, pwdb_D=%d\n",
+			 rpt2->beamformed, rpt2->stbc, rpt2->ldpc, rpt2->gnt_bt,
+			 rpt2->band, rpt2->channel_lsb,
+			 rpt2->ht_rxsc, rpt2->l_rxsc, rpt2->pwdb[3]);
+		pr_debug("[8] AgcTab[D:A]={%d, %d, %d, %d}, pwed_th=%d, shift_l_map=%d\n",
+			 rpt2->agc_table_d, rpt2->agc_table_c,
+			 rpt2->agc_table_b, rpt2->agc_table_a,
+			 rpt2->pwed_th, rpt2->shift_l_map);
+		pr_debug("[12] AvgNoisePowerdB=%d, mp_gain_c[msb, lsb]={%d, %d}, mp_gain_b[msb, lsb]={%d, %d}, mp_gain_a=%d, cnt_cca2agc_rdy=%d\n",
+			 rpt2->avg_noise_pwr_lsb, rpt2->mp_gain_c_msb,
+			 rpt2->mp_gain_c_lsb, rpt2->mp_gain_b_msb,
+			 rpt2->mp_gain_b_lsb, rpt2->mp_gain_a,
+			 rpt2->cnt_cca2agc_rdy);
+		pr_debug("[16] HT AAGC gain[B:A]={%d, %d}, AAGC step[D:A]={%d, %d, %d, %d}, IsFreqSelectFadimg=%d, mp_gain_d=%d\n",
+			 rpt2->ht_aagc_gain[1], rpt2->ht_aagc_gain[0],
+			 rpt2->aagc_step_d, rpt2->aagc_step_c,
+			 rpt2->aagc_step_b, rpt2->aagc_step_a,
+			 rpt2->is_freq_select_fading, rpt2->mp_gain_d);
+		pr_debug("[20] DAGC gain ant[B:A]={%d, %d}, HT AAGC gain[D:C]={%d, %d}\n",
+			 rpt2->dagc_gain[1], rpt2->dagc_gain[0],
+			 rpt2->ht_aagc_gain[3], rpt2->ht_aagc_gain[2]);
+		pr_debug("[24] AvgNoisePwerdB=%d, syn_count[msb, lsb]={%d, %d}, counter=%d, DAGC gain ant[D:C]={%d, %d}\n",
+			 rpt2->avg_noise_pwr_msb, rpt2->syn_count_msb,
+			 rpt2->syn_count_lsb, rpt2->counter,
+			 rpt2->dagc_gain[3], rpt2->dagc_gain[2]);
+	} else if (phy_status_page_num == 4) { /*type 4*/
+		pr_debug("[0] pwdb[C:A]={%d, %d, %d}, Channel_mdb=%d, Pkt_cnt=%d\n",
+			 rpt3->pwdb[2], rpt3->pwdb[1], rpt3->pwdb[0],
+			 rpt3->channel_msb, rpt3->pkt_cnt);
+		pr_debug("[4] BF=%d, STBC=%d, LDPC=%d, GNT_BT=%d, band=%d, CH_pri=%d, rxsc[ht, l]={%d, %d}, pwdb_D=%d\n",
+			 rpt3->beamformed, rpt3->stbc, rpt3->ldpc, rpt3->gnt_bt,
+			 rpt3->band, rpt3->channel_lsb, rpt3->ht_rxsc,
+			 rpt3->l_rxsc, rpt3->pwdb[3]);
+		pr_debug("[8] AntIdx[D:A]={%d, %d, %d, %d}, HW_AntSW_occur[D:A]={%d, %d, %d, %d}, Training_done[D:A]={%d, %d, %d, %d},\n    BadToneCnt_CN_excess_0=%d, BadToneCnt_min_eign_0=%d\n",
+			 rpt3->antidx_d, rpt3->antidx_c,
+			 rpt3->antidx_b, rpt3->antidx_a,
+			 rpt3->hw_antsw_occur_d, rpt3->hw_antsw_occur_c,
+			 rpt3->hw_antsw_occur_b, rpt3->hw_antsw_occur_a,
+			 rpt3->training_done_d, rpt3->training_done_c,
+			 rpt3->training_done_b, rpt3->training_done_a,
+			 rpt3->bad_tone_cnt_cn_excess_0,
+			 rpt3->bad_tone_cnt_min_eign_0);
+		pr_debug("[12] avg_cond_num_1_msb=%d, avg_cond_num_1_lsb=%d, avg_cond_num_0=%d, bad_tone_cnt_cn_excess_1=%d, bad_tone_cnt_min_eign_1=%d, Tx_pkt_cnt=%d\n",
+			 rpt3->avg_cond_num_1_msb, rpt3->avg_cond_num_1_lsb,
+			 rpt3->avg_cond_num_0, rpt3->bad_tone_cnt_cn_excess_1,
+			 rpt3->bad_tone_cnt_min_eign_1, rpt3->tx_pkt_cnt);
+		pr_debug("[16] Stream RXEVM[D:A]={%d, %d, %d, %d}\n",
+			 rpt3->rxevm[3], rpt3->rxevm[2],
+			 rpt3->rxevm[1], rpt3->rxevm[0]);
+		pr_debug("[20] Eigenvalue[D:A]={%d, %d, %d, %d}\n",
+			 rpt3->eigenvalue[3], rpt3->eigenvalue[2],
+			 rpt3->eigenvalue[1], rpt3->eigenvalue[0]);
+		pr_debug("[24] RX SNR[D:A]={%d, %d, %d, %d}\n",
+			 rpt3->rxsnr[3], rpt3->rxsnr[2],
+			 rpt3->rxsnr[1], rpt3->rxsnr[0]);
+	} else if (phy_status_page_num == 5) { /*type 5*/
+		pr_debug("[0] pwdb[C:A]={%d, %d, %d}, Channel_mdb=%d, Pkt_cnt=%d\n",
+			 rpt4->pwdb[2], rpt4->pwdb[1], rpt4->pwdb[0],
+			 rpt4->channel_msb, rpt4->pkt_cnt);
+		pr_debug("[4] BF=%d, STBC=%d, LDPC=%d, GNT_BT=%d, band=%d, CH_pri=%d, rxsc[ht, l]={%d, %d}, pwdb_D=%d\n",
+			 rpt4->beamformed, rpt4->stbc, rpt4->ldpc, rpt4->gnt_bt,
+			 rpt4->band, rpt4->channel_lsb, rpt4->ht_rxsc,
+			 rpt4->l_rxsc, rpt4->pwdb[3]);
+		pr_debug("[8] AntIdx[D:A]={%d, %d, %d, %d}, HW_AntSW_occur[D:A]={%d, %d, %d, %d}\n",
+			 rpt4->antidx_d, rpt4->antidx_c,
+			 rpt4->antidx_b, rpt4->antidx_a,
+			 rpt4->hw_antsw_occur_d, rpt4->hw_antsw_occur_c,
+			 rpt4->hw_antsw_occur_b, rpt4->hw_antsw_occur_a);
+		pr_debug("[12] Inf_posD[1,0]={%d, %d}, Inf_posC[1,0]={%d, %d}, Inf_posB[1,0]={%d, %d}, Inf_posA[1,0]={%d, %d}, Tx_pkt_cnt=%d\n",
+			 rpt4->inf_pos_1_D_flg, rpt4->inf_pos_0_D_flg,
+			 rpt4->inf_pos_1_C_flg, rpt4->inf_pos_0_C_flg,
+			 rpt4->inf_pos_1_B_flg, rpt4->inf_pos_0_B_flg,
+			 rpt4->inf_pos_1_A_flg, rpt4->inf_pos_0_A_flg,
+			 rpt4->tx_pkt_cnt);
+		pr_debug("[16] Inf_pos_B[1,0]={%d, %d}, Inf_pos_A[1,0]={%d, %d}\n",
+			 rpt4->inf_pos_1_b, rpt4->inf_pos_0_b,
+			 rpt4->inf_pos_1_a, rpt4->inf_pos_0_a);
+		pr_debug("[20] Inf_pos_D[1,0]={%d, %d}, Inf_pos_C[1,0]={%d, %d}\n",
+			 rpt4->inf_pos_1_d, rpt4->inf_pos_0_d,
+			 rpt4->inf_pos_1_c, rpt4->inf_pos_0_c);
+	}
+}
+
+void phydm_reset_phy_info_3rd(struct dm_struct *phydm,
+			      struct phydm_phyinfo_struct *phy_info)
+{
+	phy_info->rx_pwdb_all = 0;
+	phy_info->signal_quality = 0;
+	phy_info->band_width = 0;
+	phy_info->rx_count = 0;
+	odm_memory_set(phydm, phy_info->rx_mimo_signal_quality, 0, 4);
+	odm_memory_set(phydm, phy_info->rx_mimo_signal_strength, 0, 4);
+	odm_memory_set(phydm, phy_info->rx_snr, 0, 4);
+
+	phy_info->rx_power = -110;
+	phy_info->recv_signal_power = -110;
+	phy_info->bt_rx_rssi_percentage = 0;
+	phy_info->signal_strength = 0;
+	phy_info->channel = 0;
+	phy_info->is_mu_packet = 0;
+	phy_info->is_beamformed = 0;
+	phy_info->rxsc = 0;
+	odm_memory_set(phydm, phy_info->rx_pwr, -110, 4);
+	odm_memory_set(phydm, phy_info->cfo_short, 0, 8);
+	odm_memory_set(phydm, phy_info->cfo_tail, 0, 8);
+
+	odm_memory_set(phydm, phy_info->rx_mimo_evm_dbm, 0, 4);
+}
+
+phydm_per_path_info_3rd(u8 rx_path, s8 pwr, s8 rx_evm, s8 cfo_tail, s8 rx_snr,
+			struct phydm_phyinfo_struct *phy_info)
+{
+	u8 evm_dbm = 0;
+	u8 evm_percentage = 0;
+
+	/* SNR is S(8,1), EVM is S(8,1), CFO is S(8,7) */
+
+	if (rx_evm < 0) {
+		/* @Calculate EVM in dBm */
+		evm_dbm = ((u8)(0 - rx_evm) >> 1);
+
+		if (evm_dbm == 64)
+			evm_dbm = 0; /*@if 1SS rate, evm_dbm [2nd stream] =64*/
+
+		if (evm_dbm != 0) {
+			/* @Convert EVM to 0%~100% percentage */
+			if (evm_dbm >= 34)
+				evm_percentage = 100;
+			else
+				evm_percentage = (evm_dbm << 1) + (evm_dbm);
+		}
+	}
+
+	phy_info->rx_pwr[rx_path] = pwr;
+
+	/*@CFO(kHz) = CFO_tail * 312.5(kHz) / 2^7 ~= CFO tail * 5/2 (kHz)*/
+	phy_info->cfo_tail[rx_path] = (cfo_tail * 5) >> 1;
+	phy_info->rx_mimo_evm_dbm[rx_path] = evm_dbm;
+	phy_info->rx_mimo_signal_strength[rx_path] = phydm_pwr_2_percent(pwr);
+	phy_info->rx_mimo_signal_quality[rx_path] = evm_percentage;
+	phy_info->rx_snr[rx_path] = rx_snr >> 1;
+}
+
+void phydm_common_phy_info_3rd(s8 rx_power, u8 channel, boolean is_beamformed,
+			       boolean is_mu_packet, u8 bandwidth,
+			       u8 signal_quality, u8 rxsc,
+			       struct phydm_phyinfo_struct *phy_info)
+{
+	phy_info->rx_power = rx_power; /* RSSI in dB */
+	phy_info->recv_signal_power = rx_power; /* RSSI in dB */
+	phy_info->channel = channel; /* @channel number */
+	phy_info->is_beamformed = is_beamformed; /* @apply BF */
+	phy_info->is_mu_packet = is_mu_packet; /* @MU packet */
+	phy_info->rxsc = rxsc;
+
+	phy_info->rx_pwdb_all = phydm_pwr_2_percent(rx_power); /*percentage */
+	phy_info->signal_quality = signal_quality; /* signal quality */
+	phy_info->band_width = bandwidth; /* @bandwidth */
+
+#if 0
+	/* @if (pktinfo->is_packet_match_bssid) */
+	{
+		dbg_print("rx_pwdb_all = %d, rx_power = %d, recv_signal_power = %d\n", phy_info->rx_pwdb_all, phy_info->rx_power, phy_info->recv_signal_power);
+		dbg_print("signal_quality = %d\n", phy_info->signal_quality);
+		dbg_print("is_beamformed = %d, is_mu_packet = %d, rx_count = %d\n", phy_info->is_beamformed, phy_info->is_mu_packet, phy_info->rx_count + 1);
+		dbg_print("channel = %d, rxsc = %d, band_width = %d\n", channel, rxsc, bandwidth);
+	}
+#endif
+}
+
+void phydm_get_physts_jarguar3_0(struct dm_struct *dm, u8 *phy_status_inf,
+				 struct phydm_perpkt_info_struct *pktinfo,
+				 struct phydm_phyinfo_struct *phy_info)
+{
+	/* type 0 is used for cck packet */
+	struct phy_status_rpt_jaguar3_type0 *phy_sts = NULL;
+	u8 sq = 0, i;
+	s8 rx_power[4];
+	s8 rx_pwr_db_max = -120;
+
+	phy_sts = (struct phy_status_rpt_jaguar3_type0 *)phy_status_inf;
+
+	/* Setting the RX power: agc_idx -110 dBm*/
+	rx_power[0] = phy_sts->pwdb_a - 110;
+	rx_power[1] = phy_sts->pwdb_b - 110;
+	rx_power[2] = phy_sts->pwdb_c - 110;
+	rx_power[3] = phy_sts->pwdb_d - 110;
+
+	for (i = RF_PATH_A; i < PHYDM_MAX_RF_PATH; i++) {
+		if (rx_power[i] > rx_pwr_db_max)
+			rx_pwr_db_max = rx_power[0];   /*only one path*/
+	}
+	if (pktinfo->is_to_self) {
+		dm->ofdm_agc_idx[0] = phy_sts->pwdb_a;
+		dm->ofdm_agc_idx[1] = phy_sts->pwdb_b;
+		dm->ofdm_agc_idx[2] = phy_sts->pwdb_c;
+		dm->ofdm_agc_idx[3] = phy_sts->pwdb_d;
+	}
+
+	/* @Calculate Signal Quality*/
+	if (phy_sts->signal_quality >= 64) {
+		sq = 0;
+	} else if (phy_sts->signal_quality <= 20) {
+		sq = 100;
+	} else {
+		/* @mapping to 2~99% */
+		sq = 64 - phy_sts->signal_quality;
+		sq = ((sq << 3) + sq) >> 2;
+	}
+
+	/* @Modify CCK PWDB if old AGC */
+	if (!dm->cck_new_agc) {
+		u8 lna_idx[4], vga_idx[4];
+
+		lna_idx[0] = ((phy_sts->lna_h_a << 3) | phy_sts->lna_l_a);
+		vga_idx[0] = phy_sts->vga_a;
+		lna_idx[1] = ((phy_sts->lna_h_b << 3) | phy_sts->lna_l_b);
+		vga_idx[1] = phy_sts->vga_b;
+		lna_idx[2] = ((phy_sts->lna_h_c << 3) | phy_sts->lna_l_c);
+		vga_idx[2] = phy_sts->vga_c;
+		lna_idx[3] = ((phy_sts->lna_h_d << 3) | phy_sts->lna_l_d);
+		vga_idx[3] = phy_sts->vga_d;
+		#if (RTL8198F_SUPPORT)
+			/*phydm_cck_rssi_8198f*/
+		#endif
+	}
+
+	/*@CCK no STBC and LDPC*/
+	dm->phy_dbg_info.is_ldpc_pkt = false;
+	dm->phy_dbg_info.is_stbc_pkt = false;
+
+	/* Update Common information */
+	phydm_common_phy_info_3rd(rx_pwr_db_max, phy_sts->channel, false,
+				  false, CHANNEL_WIDTH_20, sq,
+				  phy_sts->l_rxsc, phy_info);
+
+	/* Update CCK pwdb */
+	/* Update per-path information */
+	phydm_per_path_info_3rd(RF_PATH_A, rx_power[0], 0, 0, 0, phy_info);
+	phydm_per_path_info_3rd(RF_PATH_B, rx_power[1], 0, 0, 0, phy_info);
+	phydm_per_path_info_3rd(RF_PATH_C, rx_power[2], 0, 0, 0, phy_info);
+	phydm_per_path_info_3rd(RF_PATH_D, rx_power[3], 0, 0, 0, phy_info);
+
+	#ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY
+	dm->dm_fat_table.antsel_rx_keep_0 = phy_sts->antidx_a;
+	dm->dm_fat_table.antsel_rx_keep_1 = phy_sts->antidx_b;
+	dm->dm_fat_table.antsel_rx_keep_2 = phy_sts->antidx_c;
+	dm->dm_fat_table.antsel_rx_keep_3 = phy_sts->antidx_d;
+	#endif
+}
+
+void phydm_get_physts_jarguar3_1(struct dm_struct *dm, u8 *phy_status_inf,
+				 struct phydm_perpkt_info_struct *pktinfo,
+				 struct phydm_phyinfo_struct *phy_info)
+{
+	/* type 1 is used for ofdm packet */
+	struct phy_status_rpt_jaguar3_type1 *phy_sts = NULL;
+	struct odm_phy_dbg_info *dbg_i = &dm->phy_dbg_info;
+	s8 rx_pwr_db = -120;
+	s8 rx_path_pwr_db;
+	u8 i, rxsc, bw = CHANNEL_WIDTH_20, rx_cnt = 0;
+	u8 pwdb[4];
+	boolean is_mu;
+
+	phy_sts = (struct phy_status_rpt_jaguar3_type1 *)phy_status_inf;
+
+	pwdb[0] = phy_sts->pwdb_a;
+	pwdb[1] = phy_sts->pwdb_b;
+	pwdb[2] = phy_sts->pwdb_c;
+	pwdb[3] = phy_sts->pwdb_d;
+
+	/* Update per-path information */
+	for (i = RF_PATH_A; i < PHYDM_MAX_RF_PATH; i++) {
+		if (dm->rx_ant_status & BIT(i)) {
+			rx_cnt++; /* @check the number of the ant */
+
+			if (rx_cnt > dm->num_rf_path)
+				break;
+
+			/* Update per-path information
+			 * (RSSI_dB RSSI_percentage EVM SNR CFO sq)
+			 */
+			/* @EVM report is reported by stream, not path */
+			rx_path_pwr_db = pwdb[i] - 110; /* per-path pw (dB)*/
+
+			if (pktinfo->is_to_self)
+				dm->ofdm_agc_idx[i] = pwdb[i];
+
+			phydm_per_path_info_3rd(i, rx_path_pwr_db,
+						phy_sts->rxevm[rx_cnt - 1],
+						phy_sts->cfo_tail[i],
+						phy_sts->rxsnr[i], phy_info);
+
+			/* search maximum pwdb */
+			if (rx_path_pwr_db > rx_pwr_db)
+				rx_pwr_db = rx_path_pwr_db;
+		}
+	}
+
+	/* @mapping RX counter from 1~4 to 0~3 */
+	if (rx_cnt > 0)
+		phy_info->rx_count = rx_cnt - 1;
+
+	/* @Check if MU packet or not */
+	if (phy_sts->gid != 0 && phy_sts->gid != 63) {
+		is_mu = true;
+		dbg_i->num_qry_mu_pkt++;
+	} else {
+		is_mu = false;
+	}
+
+	/* @count BF packet */
+	dbg_i->num_qry_bf_pkt = dbg_i->num_qry_bf_pkt + phy_sts->beamformed;
+
+	/*STBC or LDPC pkt*/
+	dbg_i->is_ldpc_pkt = phy_sts->ldpc;
+	dbg_i->is_stbc_pkt = phy_sts->stbc;
+
+	/* @Check sub-channel */
+	if (pktinfo->data_rate > ODM_RATE11M &&
+	    pktinfo->data_rate < ODM_RATEMCS0)
+		rxsc = phy_sts->l_rxsc; /*@Legacy*/
+	else
+		rxsc = phy_sts->ht_rxsc; /* @HT and VHT */
+
+	/* @Check RX bandwidth */
+	if (dm->support_ic_type & ODM_IC_JGR3_SERIES) {
+		if (rxsc >= 1 && rxsc <= 8)
+			bw = CHANNEL_WIDTH_20;
+		else if ((rxsc >= 9) && (rxsc <= 12))
+			bw = CHANNEL_WIDTH_40;
+		else if (rxsc >= 13)
+			bw = CHANNEL_WIDTH_80;
+	}
+
+	/* Update packet information */
+	/* RX power choose the path with the maximum power */
+	phydm_common_phy_info_3rd(rx_pwr_db, phy_sts->channel_pri_lsb,
+				  (boolean)phy_sts->beamformed, is_mu,
+				  bw, phy_info->rx_mimo_signal_quality[0],
+				  rxsc, phy_info);
+
+	phydm_parsing_cfo(dm, pktinfo, phy_sts->cfo_tail, pktinfo->rate_ss);
+
+#if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY))
+	dm->dm_fat_table.antsel_rx_keep_0 = phy_sts->antidx_a;
+	dm->dm_fat_table.antsel_rx_keep_1 = phy_sts->antidx_b;
+	dm->dm_fat_table.antsel_rx_keep_2 = phy_sts->antidx_c;
+	dm->dm_fat_table.antsel_rx_keep_3 = phy_sts->antidx_d;
+#endif
+}
+
+void phydm_get_physts_jarguar3_2_3(struct dm_struct *dm, u8 *phy_status_inf,
+				   struct phydm_perpkt_info_struct *pktinfo,
+				   struct phydm_phyinfo_struct *phy_info)
+{
+	/* type 2 & 3 is used for ofdm packet */
+	struct phy_status_rpt_jaguar3_type2_type3 *phy_sts = NULL;
+	s8 rx_pwr_db_max = -120;
+	s8 rx_path_pwr_db;
+	u8 i, rxsc, bw = CHANNEL_WIDTH_20, rx_count = 0;
+
+	phy_sts = (struct phy_status_rpt_jaguar3_type2_type3 *)phy_status_inf;
+
+	/* Update per-path information */
+	for (i = RF_PATH_A; i < PHYDM_MAX_RF_PATH; i++) {
+		if (dm->rx_ant_status & BIT(i)) {
+			rx_count++; /* @check the number of the ant */
+
+			if (rx_count > dm->num_rf_path)
+				break;
+
+			/* Update per-path information
+			 * (RSSI_dB RSSI_percentage EVM SNR CFO sq)
+			 */
+			/* @EVM report is reported by stream, not path */
+			rx_path_pwr_db = phy_sts->pwdb[i] - 110; /*@dB*/
+
+			if (pktinfo->is_to_self)
+				dm->ofdm_agc_idx[i] = phy_sts->pwdb[i];
+
+			phydm_per_path_info_3rd(i, rx_path_pwr_db, 0,
+						0, 0, phy_info);
+
+			/* search maximum pwdb */
+			if (rx_path_pwr_db > rx_pwr_db_max)
+				rx_pwr_db_max = rx_path_pwr_db;
+		}
+	}
+
+	/* @mapping RX counter from 1~4 to 0~3 */
+	if (rx_count > 0)
+		phy_info->rx_count = rx_count - 1;
+
+	/* @count BF packet */
+	dm->phy_dbg_info.num_qry_bf_pkt = dm->phy_dbg_info.num_qry_bf_pkt +
+					  phy_sts->beamformed;
+
+	/*STBC or LDPC pkt*/
+	dm->phy_dbg_info.is_ldpc_pkt = phy_sts->ldpc;
+	dm->phy_dbg_info.is_stbc_pkt = phy_sts->stbc;
+
+	/* @Check sub-channel */
+	if (pktinfo->data_rate > ODM_RATE11M &&
+	    pktinfo->data_rate < ODM_RATEMCS0)
+		rxsc = phy_sts->l_rxsc; /*@Legacy*/
+	else
+		rxsc = phy_sts->ht_rxsc; /* @HT and VHT */
+
+	/* @Check RX bandwidth */
+	if (dm->support_ic_type & ODM_IC_JGR3_SERIES) {
+		if (rxsc >= 1 && rxsc <= 8)
+			bw = CHANNEL_WIDTH_20;
+		else if ((rxsc >= 9) && (rxsc <= 12))
+			bw = CHANNEL_WIDTH_40;
+		else if (rxsc >= 13)
+			bw = CHANNEL_WIDTH_80;
+	}
+
+	/* Update packet information */
+	/* RX power choose the path with the maximum power */
+	phydm_common_phy_info_3rd(rx_pwr_db_max, phy_sts->channel_lsb,
+				  (boolean)phy_sts->beamformed,
+				  false, bw, 0, rxsc, phy_info);
+}
+
+void phydm_get_physts_jarguar3_4(struct dm_struct *dm, u8 *phy_status_inf,
+				 struct phydm_perpkt_info_struct *pktinfo,
+				 struct phydm_phyinfo_struct *phy_info)
+{
+	/* type 4 is used for ofdm packet */
+	struct phy_status_rpt_jaguar3_type4 *phy_sts = NULL;
+	s8 rx_pwr_db_max = -120;
+	s8 rx_path_pwr_db;
+	u8 i, rxsc, bw = CHANNEL_WIDTH_20, rx_cnt = 0;
+
+	phy_sts = (struct phy_status_rpt_jaguar3_type4 *)phy_status_inf;
+
+	/* Update per-path information */
+	for (i = RF_PATH_A; i < PHYDM_MAX_RF_PATH; i++) {
+		if (dm->rx_ant_status & BIT(i)) {
+			rx_cnt++; /* @check the number of the ant */
+
+			if (rx_cnt > dm->num_rf_path)
+				break;
+
+			/* Update per-path information
+			 * (RSSI_dB RSSI_percentage EVM SNR CFO sq)
+			 */
+			/* @EVM report is reported by stream, not path */
+			rx_path_pwr_db = phy_sts->pwdb[i] - 110; /*@dB*/
+
+			if (pktinfo->is_to_self)
+				dm->ofdm_agc_idx[i] = phy_sts->pwdb[i];
+
+			phydm_per_path_info_3rd(i, rx_path_pwr_db,
+						phy_sts->rxevm[rx_cnt - 1],
+						0, phy_sts->rxsnr[i],
+						phy_info);
+
+			/* search maximum pwdb */
+			if (rx_path_pwr_db > rx_pwr_db_max)
+				rx_pwr_db_max = rx_path_pwr_db;
+		}
+	}
+
+	/* @mapping RX counter from 1~4 to 0~3 */
+	if (rx_cnt > 0)
+		phy_info->rx_count = rx_cnt - 1;
+
+	/* @count BF packet */
+	dm->phy_dbg_info.num_qry_bf_pkt = dm->phy_dbg_info.num_qry_bf_pkt +
+					  phy_sts->beamformed;
+
+	/*STBC or LDPC pkt*/
+	dm->phy_dbg_info.is_ldpc_pkt = phy_sts->ldpc;
+	dm->phy_dbg_info.is_stbc_pkt = phy_sts->stbc;
+
+	/* @Check sub-channel */
+	if (pktinfo->data_rate > ODM_RATE11M &&
+	    pktinfo->data_rate < ODM_RATEMCS0)
+		rxsc = phy_sts->l_rxsc; /*@Legacy*/
+	else
+		rxsc = phy_sts->ht_rxsc; /* @HT and VHT */
+
+	/* @Check RX bandwidth */
+	if (dm->support_ic_type & ODM_IC_JGR3_SERIES) {
+		if (rxsc >= 1 && rxsc <= 8)
+			bw = CHANNEL_WIDTH_20;
+		else if ((rxsc >= 9) && (rxsc <= 12))
+			bw = CHANNEL_WIDTH_40;
+		else if (rxsc >= 13)
+			bw = CHANNEL_WIDTH_80;
+	}
+
+	/* @Conditional number */
+	if (dm->support_ic_type & PHYSTS_3RD_TYPE_IC) {
+		dm->phy_dbg_info.condi_num = (u32)phy_sts->avg_cond_num_0;
+	}
+
+	/* Update packet information */
+	/* RX power choose the path with the maximum power */
+	phydm_common_phy_info_3rd(rx_pwr_db_max, phy_sts->channel_lsb,
+				  (boolean)phy_sts->beamformed,
+				  false, bw, 0, rxsc, phy_info);
+}
+
+void phydm_get_physts_jarguar3_5(struct dm_struct *dm, u8 *phy_status_inf,
+				 struct phydm_perpkt_info_struct *pktinfo,
+				 struct phydm_phyinfo_struct *phy_info)
+{
+	/* type 5 is used for ofdm packet */
+	struct phy_status_rpt_jaguar3_type5 *phy_sts = NULL;
+	s8 rx_pwr_db_max = -120;
+	s8 rx_path_pwr_db;
+	u8 i, rxsc, bw = CHANNEL_WIDTH_20, rx_count = 0;
+
+	phy_sts = (struct phy_status_rpt_jaguar3_type5 *)phy_status_inf;
+
+	/* Update per-path information */
+	for (i = RF_PATH_A; i < PHYDM_MAX_RF_PATH; i++) {
+		if (dm->rx_ant_status & BIT(i)) {
+			rx_count++; /* @check the number of the ant */
+
+			if (rx_count > dm->num_rf_path)
+				break;
+
+			/* Update per-path information
+			 * (RSSI_dB RSSI_percentage EVM SNR CFO sq)
+			 */
+			/* @EVM report is reported by stream, not path */
+			rx_path_pwr_db = phy_sts->pwdb[i] - 110; /*@dB*/
+
+			if (pktinfo->is_to_self)
+				dm->ofdm_agc_idx[i] = phy_sts->pwdb[i];
+
+			phydm_per_path_info_3rd(i, rx_path_pwr_db,
+						0, 0, 0, phy_info);
+
+			/* search maximum pwdb */
+			if (rx_path_pwr_db > rx_pwr_db_max)
+				rx_pwr_db_max = rx_path_pwr_db;
+		}
+	}
+
+	/* @mapping RX counter from 1~4 to 0~3 */
+	if (rx_count > 0)
+		phy_info->rx_count = rx_count - 1;
+
+	/* @count BF packet */
+	dm->phy_dbg_info.num_qry_bf_pkt = dm->phy_dbg_info.num_qry_bf_pkt +
+					  phy_sts->beamformed;
+
+	/*STBC or LDPC pkt*/
+	dm->phy_dbg_info.is_ldpc_pkt = phy_sts->ldpc;
+	dm->phy_dbg_info.is_stbc_pkt = phy_sts->stbc;
+
+	/* @Check sub-channel */
+	if (pktinfo->data_rate > ODM_RATE11M &&
+	    pktinfo->data_rate < ODM_RATEMCS0)
+		rxsc = phy_sts->l_rxsc; /*@Legacy*/
+	else
+		rxsc = phy_sts->ht_rxsc; /* @HT and VHT */
+
+	/* @Check RX bandwidth */
+	if (dm->support_ic_type & ODM_IC_JGR3_SERIES) {
+		if (rxsc >= 1 && rxsc <= 8)
+			bw = CHANNEL_WIDTH_20;
+		else if ((rxsc >= 9) && (rxsc <= 12))
+			bw = CHANNEL_WIDTH_40;
+		else if (rxsc >= 13)
+			bw = CHANNEL_WIDTH_80;
+	}
+
+	/* Update packet information */
+	/* RX power choose the path with the maximum power */
+	phydm_common_phy_info_3rd(rx_pwr_db_max, phy_sts->channel_lsb,
+				  (boolean)phy_sts->beamformed,
+				  false, bw, 0, rxsc, phy_info);
+}
+
+void phydm_process_dm_rssi_3rd_type(struct dm_struct *dm,
+				    struct phydm_phyinfo_struct *phy_info,
+				    struct phydm_perpkt_info_struct *pktinfo)
+{
+	struct cmn_sta_info *sta = NULL;
+	struct rssi_info *rssi_t = NULL;
+	u8 rssi_tmp = 0;
+	u32 rssi_linear = 0;
+	s16 rssi_db = 0;
+	u8 i = 0;
+
+	/*@[Step4]*/
+
+	if (pktinfo->station_id >= ODM_ASSOCIATE_ENTRY_NUM)
+		return;
+
+	sta = dm->phydm_sta_info[pktinfo->station_id];
+
+	if (!is_sta_active(sta))
+		return;
+
+	if (!pktinfo->is_packet_match_bssid) /*@data frame only*/
+		return;
+
+	if (!(pktinfo->is_packet_to_self) && !(pktinfo->is_packet_beacon))
+		return;
+
+	if (pktinfo->is_packet_beacon) {
+		dm->phy_dbg_info.num_qry_beacon_pkt++;
+		dm->phy_dbg_info.beacon_phy_rate = pktinfo->data_rate;
+	}
+
+	rssi_t = &sta->rssi_stat;
+
+	if (pktinfo->is_cck_rate) {
+		rssi_db = phy_info->rx_mimo_signal_strength[0]; /*Path-A*/
+		if (rssi_t->rssi_acc == 0) {
+			rssi_t->rssi_acc = (s16)(rssi_db << RSSI_MA);
+			rssi_t->rssi = (s8)(rssi_db);
+		} else {
+			rssi_t->rssi_acc = MA_ACC(rssi_t->rssi_acc,
+						  rssi_db, RSSI_MA);
+			rssi_t->rssi = (s8)GET_MA_VAL(rssi_t->rssi_acc,
+						      RSSI_MA);
+		}
+		rssi_t->rssi_cck = (s8)rssi_db;
+	} else {
+		for (i = RF_PATH_A; i < PHYDM_MAX_RF_PATH; i++) {
+			rssi_tmp = phy_info->rx_mimo_signal_strength[i];
+			if (rssi_tmp != 0)
+				rssi_linear += phydm_db_2_linear(rssi_tmp);
+		}
+		switch (phy_info->rx_count + 1) {
+		case 2:
+			rssi_linear = DIVIDED_2(rssi_linear);
+			break;
+		case 3:
+			rssi_linear = DIVIDED_3(rssi_linear);
+			break;
+		case 4:
+			rssi_linear = DIVIDED_4(rssi_linear);
+			break;
+		}
+		rssi_db = (s16)odm_convert_to_db(rssi_linear);
+
+		if (rssi_t->rssi_acc == 0) {
+			rssi_t->rssi_acc = (s16)(rssi_db << RSSI_MA);
+			rssi_t->rssi = (s8)(rssi_db);
+		} else {
+			rssi_t->rssi_acc = MA_ACC(rssi_t->rssi_acc,
+						  rssi_db, RSSI_MA);
+			rssi_t->rssi = (s8)GET_MA_VAL(rssi_t->rssi_acc,
+						      RSSI_MA);
+		}
+		rssi_t->rssi_ofdm = (s8)rssi_db;
+	}
+}
+
+void phydm_rx_physts_3rd_type(void *dm_void, u8 *phy_sts,
+			      struct phydm_perpkt_info_struct *pktinfo,
+			      struct phydm_phyinfo_struct *phy_info)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+#ifdef PHYDM_PHYSTAUS_SMP_MODE
+	struct pkt_process_info *pkt_process = &dm->pkt_proc_struct;
+#endif
+	u8 phy_status_type = (*phy_sts & 0xf);
+
+#ifdef PHYDM_PHYSTAUS_SMP_MODE
+	if (pkt_process->phystatus_smp_mode_en && phy_status_type != 0) {
+		if (pkt_process->pre_ppdu_cnt == pktinfo->ppdu_cnt)
+			return;
+		pkt_process->pre_ppdu_cnt = pktinfo->ppdu_cnt;
+	}
+#endif
+
+	/*@[Step 2]*/
+	phydm_reset_phy_info_3rd(dm, phy_info); /* @Memory reset */
+
+	/* Phy status parsing */
+	switch (phy_status_type) {
+	case 0: /*@CCK*/
+		phydm_get_physts_jarguar3_0(dm, phy_sts, pktinfo, phy_info);
+		break;
+	case 1:
+		phydm_get_physts_jarguar3_1(dm, phy_sts, pktinfo, phy_info);
+		break;
+	case 2:
+	case 3:
+		phydm_get_physts_jarguar3_2_3(dm, phy_sts, pktinfo, phy_info);
+		break;
+	case 4:
+		phydm_get_physts_jarguar3_4(dm, phy_sts, pktinfo, phy_info);
+		break;
+	case 5:
+		phydm_get_physts_jarguar3_5(dm, phy_sts, pktinfo, phy_info);
+		break;
+	default:
+		break;
+	}
+
+
+	/*@[Step 1]*/
+	#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
+	if (dm->support_ic_type & ODM_IC_JGR3_SERIES)
+		phydm_print_phystat_jaguar3(dm, phy_sts, pktinfo, phy_info);
+	#endif
+}
+
+#endif
+
+#if (ODM_PHY_STATUS_NEW_TYPE_SUPPORT)
+/* @For 8822B only!! need to move to FW finally */
+/*@==============================================*/
+
+boolean
+phydm_query_is_mu_api(struct dm_struct *phydm, u8 ppdu_idx, u8 *p_data_rate,
+		      u8 *p_gid)
+{
+	u8 data_rate = 0, gid = 0;
+	boolean is_mu = false;
+
+	data_rate = phydm->phy_dbg_info.num_of_ppdu[ppdu_idx];
+	gid = phydm->phy_dbg_info.gid_num[ppdu_idx];
+
+	if (data_rate & BIT(7)) {
+		is_mu = true;
+		data_rate = data_rate & ~(BIT(7));
+	} else {
+		is_mu = false;
+	}
+
+	*p_data_rate = data_rate;
+	*p_gid = gid;
+
+	return is_mu;
+}
+
+void phydm_reset_phy_info(struct dm_struct *phydm,
+			  struct phydm_phyinfo_struct *phy_info)
+{
+	phy_info->rx_pwdb_all = 0;
+	phy_info->signal_quality = 0;
+	phy_info->band_width = 0;
+	phy_info->rx_count = 0;
+	odm_memory_set(phydm, phy_info->rx_mimo_signal_quality, 0, 4);
+	odm_memory_set(phydm, phy_info->rx_mimo_signal_strength, 0, 4);
+	odm_memory_set(phydm, phy_info->rx_snr, 0, 4);
+
+	phy_info->rx_power = -110;
+	phy_info->recv_signal_power = -110;
+	phy_info->bt_rx_rssi_percentage = 0;
+	phy_info->signal_strength = 0;
+	phy_info->channel = 0;
+	phy_info->is_mu_packet = 0;
+	phy_info->is_beamformed = 0;
+	phy_info->rxsc = 0;
+	odm_memory_set(phydm, phy_info->rx_pwr, -110, 4);
+	odm_memory_set(phydm, phy_info->cfo_short, 0, 8);
+	odm_memory_set(phydm, phy_info->cfo_tail, 0, 8);
+
+	odm_memory_set(phydm, phy_info->rx_mimo_evm_dbm, 0, 4);
+}
+
+void phydm_print_phy_sts_jgr2(struct dm_struct *dm, u8 *phy_status_inf,
+			      struct phydm_perpkt_info_struct *pktinfo,
+			      struct phydm_phyinfo_struct *phy_info)
+{
+	struct phy_status_rpt_jaguar2_type0 *rpt0 = NULL;
+	struct phy_status_rpt_jaguar2_type1 *rpt = NULL;
+	struct phy_status_rpt_jaguar2_type2 *rpt2 = NULL;
+	struct odm_phy_dbg_info *dbg = &dm->phy_dbg_info;
+	u8 phy_status_page_num = (*phy_status_inf & 0xf);
+	u32 phy_status[PHY_STATUS_JRGUAR2_DW_LEN] = {0};
+	u8 i;
+	u32 size = PHY_STATUS_JRGUAR2_DW_LEN << 2;
+
+	rpt0 = (struct phy_status_rpt_jaguar2_type0 *)phy_status_inf;
+	rpt = (struct phy_status_rpt_jaguar2_type1 *)phy_status_inf;
+	rpt2 = (struct phy_status_rpt_jaguar2_type2 *)phy_status_inf;
+
+	odm_move_memory(dm, phy_status, phy_status_inf, size);
+
+	if (!(dm->debug_components & DBG_PHY_STATUS))
+		return;
+
+	if (dbg->show_phy_sts_all_pkt == 0) {
+		if (!pktinfo->is_packet_match_bssid)
+			return;
+	}
+
+	dbg->show_phy_sts_cnt++;
+	#if 0
+	dbg_print("cnt=%d, max=%d\n",
+		  dbg->show_phy_sts_cnt, dbg->show_phy_sts_max_cnt);
+	#endif
+
+	if (dbg->show_phy_sts_max_cnt != SHOW_PHY_STATUS_UNLIMITED) {
+		if (dbg->show_phy_sts_cnt > dbg->show_phy_sts_max_cnt)
+			return;
+	}
+
+	pr_debug("Phy Status Rpt: OFDM_%d\n", phy_status_page_num);
+	pr_debug("StaID=%d, RxRate = 0x%x match_bssid=%d\n",
+		 pktinfo->station_id, pktinfo->data_rate,
+		 pktinfo->is_packet_match_bssid);
+
+	for (i = 0; i < PHY_STATUS_JRGUAR2_DW_LEN; i++)
+		pr_debug("Offset[%d:%d] = 0x%x\n",
+			 ((4 * i) + 3), (4 * i), phy_status[i]);
+
+	if (phy_status_page_num == 0) {
+		pr_debug("[0] TRSW=%d, MP_gain_idx=%d, pwdb=%d\n",
+			 rpt0->trsw, rpt0->gain, rpt0->pwdb);
+		pr_debug("[4] band=%d, CH=%d, agc_table = %d, rxsc = %d\n",
+			 rpt0->band, rpt0->channel,
+			 rpt0->agc_table, rpt0->rxsc);
+		pr_debug("[8] AntIdx[D:A]={%d, %d, %d, %d}, LSIG_len=%d\n",
+			 rpt0->antidx_d, rpt0->antidx_c, rpt0->antidx_b,
+			 rpt0->antidx_a, rpt0->length);
+		pr_debug("[12] lna_h=%d, bb_pwr=%d, lna_l=%d, vga=%d, sq=%d\n",
+			 rpt0->lna_h, rpt0->bb_power, rpt0->lna_l,
+			 rpt0->vga, rpt0->signal_quality);
+
+	} else if (phy_status_page_num == 1) {
+		pr_debug("[0] pwdb[D:A]={%d, %d, %d, %d}\n",
+			 rpt->pwdb[3], rpt->pwdb[2],
+			 rpt->pwdb[1], rpt->pwdb[0]);
+		pr_debug("[4] BF: %d, ldpc=%d, stbc=%d, g_bt=%d, antsw=%d, band=%d, CH=%d, rxsc[ht, l]={%d, %d}\n",
+			 rpt->beamformed, rpt->ldpc, rpt->stbc, rpt->gnt_bt,
+			 rpt->hw_antsw_occu, rpt->band, rpt->channel,
+			 rpt->ht_rxsc, rpt->l_rxsc);
+		pr_debug("[8] AntIdx[D:A]={%d, %d, %d, %d}, LSIG_len=%d\n",
+			 rpt->antidx_d, rpt->antidx_c, rpt->antidx_b,
+			 rpt->antidx_a, rpt->lsig_length);
+		pr_debug("[12] rf_mode=%d, NBI=%d, Intf_pos=%d, GID=%d, PAID=%d\n",
+			 rpt->rf_mode, rpt->nb_intf_flag,
+			 (rpt->intf_pos + (rpt->intf_pos_msb << 8)), rpt->gid,
+			 (rpt->paid + (rpt->paid_msb << 8)));
+		pr_debug("[16] EVM[D:A]={%d, %d, %d, %d}\n",
+			 rpt->rxevm[3], rpt->rxevm[2],
+			 rpt->rxevm[1], rpt->rxevm[0]);
+		pr_debug("[20] CFO[D:A]={%d, %d, %d, %d}\n",
+			 rpt->cfo_tail[3], rpt->cfo_tail[2], rpt->cfo_tail[1],
+			 rpt->cfo_tail[0]);
+		pr_debug("[24] SNR[D:A]={%d, %d, %d, %d}\n\n",
+			 rpt->rxsnr[3], rpt->rxsnr[2], rpt->rxsnr[1],
+			 rpt->rxsnr[0]);
+
+	} else if (phy_status_page_num == 2) {
+		pr_debug("[0] pwdb[D:A]={%d, %d, %d, %d}\n",
+			 rpt2->pwdb[3], rpt2->pwdb[2], rpt2->pwdb[1],
+			 rpt2->pwdb[0]);
+		pr_debug("[4] BF: %d, ldpc=%d, stbc=%d, g_bt=%d, antsw=%d, band=%d, CH=%d, rxsc[ht,l]={%d, %d}\n",
+			 rpt2->beamformed, rpt2->ldpc, rpt2->stbc, rpt2->gnt_bt,
+			 rpt2->hw_antsw_occu, rpt2->band, rpt2->channel,
+			 rpt2->ht_rxsc, rpt2->l_rxsc);
+		pr_debug("[8] AgcTab[D:A]={%d, %d, %d, %d}, cnt_pw2cca=%d, shift_l_map=%d\n",
+			 rpt2->agc_table_d, rpt2->agc_table_c,
+			 rpt2->agc_table_b, rpt2->agc_table_a,
+			 rpt2->cnt_pw2cca, rpt2->shift_l_map);
+		pr_debug("[12] (TRSW|Gain)[D:A]={%d %d, %d %d, %d %d, %d %d}, cnt_cca2agc_rdy=%d\n",
+			 rpt2->trsw_d, rpt2->gain_d, rpt2->trsw_c, rpt2->gain_c,
+			 rpt2->trsw_b, rpt2->gain_b, rpt2->trsw_a,
+			 rpt2->gain_a, rpt2->cnt_cca2agc_rdy);
+		pr_debug("[16] AAGC step[D:A]={%d, %d, %d, %d} HT AAGC gain[D:A]={%d, %d, %d, %d}\n",
+			 rpt2->aagc_step_d, rpt2->aagc_step_c,
+			 rpt2->aagc_step_b, rpt2->aagc_step_a,
+			 rpt2->ht_aagc_gain[3], rpt2->ht_aagc_gain[2],
+			 rpt2->ht_aagc_gain[1], rpt2->ht_aagc_gain[0]);
+		pr_debug("[20] DAGC gain[D:A]={%d, %d, %d, %d}\n",
+			 rpt2->dagc_gain[3],
+			 rpt2->dagc_gain[2], rpt2->dagc_gain[1],
+			 rpt2->dagc_gain[0]);
+		pr_debug("[24] syn_cnt: %d, Cnt=%d\n\n",
+			 rpt2->syn_count, rpt2->counter);
+	}
+}
+
+void phydm_set_per_path_phy_info(u8 rx_path, s8 pwr, s8 rx_evm, s8 cfo_tail,
+				 s8 rx_snr,
+				 struct phydm_phyinfo_struct *phy_info)
+{
+	u8 evm_dbm = 0;
+	u8 evm_percentage = 0;
+
+	/* SNR is S(8,1), EVM is S(8,1), CFO is S(8,7) */
+
+	if (rx_evm < 0) {
+		/* @Calculate EVM in dBm */
+		evm_dbm = ((u8)(0 - rx_evm) >> 1);
+
+		if (evm_dbm == 64)
+			evm_dbm = 0; /*@if 1SS rate, evm_dbm [2nd stream] =64*/
+
+		if (evm_dbm != 0) {
+			/* @Convert EVM to 0%~100% percentage */
+			if (evm_dbm >= 34)
+				evm_percentage = 100;
+			else
+				evm_percentage = (evm_dbm << 1) + (evm_dbm);
+		}
+	}
+
+	phy_info->rx_pwr[rx_path] = pwr;
+
+	/*@CFO(kHz) = CFO_tail * 312.5(kHz) / 2^7 ~= CFO tail * 5/2 (kHz)*/
+	phy_info->cfo_tail[rx_path] = (cfo_tail * 5) >> 1;
+	phy_info->rx_mimo_evm_dbm[rx_path] = evm_dbm;
+	phy_info->rx_mimo_signal_strength[rx_path] = phydm_pwr_2_percent(pwr);
+	phy_info->rx_mimo_signal_quality[rx_path] = evm_percentage;
+	phy_info->rx_snr[rx_path] = rx_snr >> 1;
+
+#if 0
+	if (!pktinfo->is_packet_match_bssid)
+		return;
+
+	dbg_print("path (%d)--------\n", rx_path);
+	dbg_print("rx_pwr = %d, Signal strength = %d\n",
+		  phy_info->rx_pwr[rx_path],
+		  phy_info->rx_mimo_signal_strength[rx_path]);
+	dbg_print("evm_dbm = %d, Signal quality = %d\n",
+		  phy_info->rx_mimo_evm_dbm[rx_path],
+		  phy_info->rx_mimo_signal_quality[rx_path]);
+	dbg_print("CFO = %d, SNR = %d\n",
+		  phy_info->cfo_tail[rx_path], phy_info->rx_snr[rx_path]);
+
+#endif
+}
+
+void phydm_set_common_phy_info(s8 rx_power, u8 channel, boolean is_beamformed,
+			       boolean is_mu_packet, u8 bandwidth,
+			       u8 signal_quality, u8 rxsc,
+			       struct phydm_phyinfo_struct *phy_info)
+{
+	phy_info->rx_power = rx_power; /* RSSI in dB */
+	phy_info->recv_signal_power = rx_power; /* RSSI in dB */
+	phy_info->channel = channel; /* @channel number */
+	phy_info->is_beamformed = is_beamformed; /* @apply BF */
+	phy_info->is_mu_packet = is_mu_packet; /* @MU packet */
+	phy_info->rxsc = rxsc;
+
+	/* RSSI in percentage */
+	phy_info->rx_pwdb_all = phydm_pwr_2_percent(rx_power);
+	phy_info->signal_quality = signal_quality; /* signal quality */
+	phy_info->band_width = bandwidth; /* @bandwidth */
+
+#if 0
+	if (!pktinfo->is_packet_match_bssid)
+		return;
+
+	dbg_print("rx_pwdb_all = %d, rx_power = %d, recv_signal_power = %d\n",
+		  phy_info->rx_pwdb_all, phy_info->rx_power,
+		  phy_info->recv_signal_power);
+	dbg_print("signal_quality = %d\n", phy_info->signal_quality);
+	dbg_print("is_beamformed = %d, is_mu_packet = %d, rx_count = %d\n",
+		  phy_info->is_beamformed, phy_info->is_mu_packet,
+		  phy_info->rx_count + 1);
+	dbg_print("channel = %d, rxsc = %d, band_width = %d\n", channel,
+		  rxsc, bandwidth);
+
+#endif
+}
+
+void phydm_get_phy_sts_type0(struct dm_struct *dm, u8 *phy_status_inf,
+			     struct phydm_perpkt_info_struct *pktinfo,
+			     struct phydm_phyinfo_struct *phy_info)
+{
+	/* type 0 is used for cck packet */
+	struct phy_status_rpt_jaguar2_type0 *phy_sts = NULL;
+	u8 sq = 0;
+	s8 rx_pow = 0;
+	u8 lna_idx = 0, vga_idx = 0;
+
+	phy_sts = (struct phy_status_rpt_jaguar2_type0 *)phy_status_inf;
+	rx_pow = phy_sts->pwdb - 110;
+
+	if (dm->support_ic_type & ODM_RTL8723D) {
+		#if (RTL8723D_SUPPORT)
+		rx_pow = phy_sts->pwdb - 97;
+		#endif
+	}
+	#if (RTL8821C_SUPPORT)
+	else if (dm->support_ic_type & ODM_RTL8821C) {
+		if (phy_sts->pwdb >= -57)
+			rx_pow = phy_sts->pwdb - 100;
+		else
+			rx_pow = phy_sts->pwdb - 102;
+	}
+	#endif
+
+	if (pktinfo->is_to_self) {
+		dm->ofdm_agc_idx[0] = phy_sts->pwdb;
+		dm->ofdm_agc_idx[1] = 0;
+		dm->ofdm_agc_idx[2] = 0;
+		dm->ofdm_agc_idx[3] = 0;
+	}
+
+	/* @Calculate Signal Quality*/
+	if (phy_sts->signal_quality >= 64) {
+		sq = 0;
+	} else if (phy_sts->signal_quality <= 20) {
+		sq = 100;
+	} else {
+		/* @mapping to 2~99% */
+		sq = 64 - phy_sts->signal_quality;
+		sq = ((sq << 3) + sq) >> 2;
+	}
+
+	/* @Get RSSI for old CCK AGC */
+	if (!dm->cck_new_agc) {
+		vga_idx = phy_sts->vga;
+
+		if (dm->support_ic_type & ODM_RTL8197F) {
+			/*@3bit LNA*/
+			lna_idx = phy_sts->lna_l;
+		} else {
+			/*@4bit LNA*/
+			lna_idx = (phy_sts->lna_h << 3) | phy_sts->lna_l;
+		}
+		rx_pow = phydm_get_cck_rssi(dm, lna_idx, vga_idx);
+	}
+
+	/* @Confirm CCK RSSI */
+	#if (RTL8197F_SUPPORT)
+	if (dm->support_ic_type & ODM_RTL8197F) {
+		u8 bb_pwr_th_l = 5; /* round( 31*0.15 ) */
+		u8 bb_pwr_th_h = 27; /* round( 31*0.85 ) */
+
+		if (phy_sts->bb_power < bb_pwr_th_l ||
+		    phy_sts->bb_power > bb_pwr_th_h)
+			rx_pow = 0; /* @Error RSSI for CCK ; set 100*/
+	}
+	#endif
+
+	/*@CCK no STBC and LDPC*/
+	dm->phy_dbg_info.is_ldpc_pkt = false;
+	dm->phy_dbg_info.is_stbc_pkt = false;
+
+	/* Update Common information */
+	phydm_set_common_phy_info(rx_pow, phy_sts->channel, false,
+				  false, CHANNEL_WIDTH_20, sq,
+				  phy_sts->rxsc, phy_info);
+	/* Update CCK pwdb */
+	phydm_set_per_path_phy_info(RF_PATH_A, rx_pow, 0, 0, 0, phy_info);
+
+	#ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY
+	dm->dm_fat_table.antsel_rx_keep_0 = phy_sts->antidx_a;
+	dm->dm_fat_table.antsel_rx_keep_1 = phy_sts->antidx_b;
+	dm->dm_fat_table.antsel_rx_keep_2 = phy_sts->antidx_c;
+	dm->dm_fat_table.antsel_rx_keep_3 = phy_sts->antidx_d;
+	#endif
+}
+
+void phydm_get_phy_sts_type1(struct dm_struct *dm, u8 *phy_status_inf,
+			     struct phydm_perpkt_info_struct *pktinfo,
+			     struct phydm_phyinfo_struct *phy_info)
+{
+	/* type 1 is used for ofdm packet */
+	struct phy_status_rpt_jaguar2_type1 *phy_sts = NULL;
+	struct odm_phy_dbg_info *dbg_i = &dm->phy_dbg_info;
+	s8 rx_pwr_db = -120;
+	s8 rx_pwr = 0;
+	u8 i, rxsc, bw = CHANNEL_WIDTH_20, rx_count = 0;
+	boolean is_mu;
+
+	phy_sts = (struct phy_status_rpt_jaguar2_type1 *)phy_status_inf;
+
+	/* Update per-path information */
+	for (i = RF_PATH_A; i < PHYDM_MAX_RF_PATH; i++) {
+		if (!(dm->rx_ant_status & BIT(i)))
+			continue;
+		rx_count++;
+
+		if (rx_count > dm->num_rf_path)
+			break;
+
+		/* Update per-path information
+		 * (RSSI_dB RSSI_percentage EVM SNR CFO sq)
+		 */
+		/* @EVM report is reported by stream, not path */
+		rx_pwr = phy_sts->pwdb[i] - 110; /* per-path pwdb(dB)*/
+
+		if (pktinfo->is_to_self)
+			dm->ofdm_agc_idx[i] = phy_sts->pwdb[i];
+
+		phydm_set_per_path_phy_info(i, rx_pwr,
+					    phy_sts->rxevm[rx_count - 1],
+					    phy_sts->cfo_tail[i],
+					    phy_sts->rxsnr[i], phy_info);
+		/* search maximum pwdb */
+		if (rx_pwr > rx_pwr_db)
+			rx_pwr_db = rx_pwr;
+	}
+
+	/* @mapping RX counter from 1~4 to 0~3 */
+	if (rx_count > 0)
+		phy_info->rx_count = rx_count - 1;
+
+	/* @Check if MU packet or not */
+	if (phy_sts->gid != 0 && phy_sts->gid != 63) {
+		is_mu = true;
+		dbg_i->num_qry_mu_pkt++;
+	} else {
+		is_mu = false;
+	}
+
+	/* @count BF packet */
+	dbg_i->num_qry_bf_pkt = dbg_i->num_qry_bf_pkt + phy_sts->beamformed;
+
+	/*STBC or LDPC pkt*/
+	dbg_i->is_ldpc_pkt = phy_sts->ldpc;
+	dbg_i->is_stbc_pkt = phy_sts->stbc;
+
+	/* @Check sub-channel */
+	if (pktinfo->data_rate > ODM_RATE11M &&
+	    pktinfo->data_rate < ODM_RATEMCS0)
+		rxsc = phy_sts->l_rxsc;
+	else
+		rxsc = phy_sts->ht_rxsc;
+
+	/* @Check RX bandwidth */
+	if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
+		if (rxsc >= 1 && rxsc <= 8)
+			bw = CHANNEL_WIDTH_20;
+		else if ((rxsc >= 9) && (rxsc <= 12))
+			bw = CHANNEL_WIDTH_40;
+		else if (rxsc >= 13)
+			bw = CHANNEL_WIDTH_80;
+		else
+			bw = phy_sts->rf_mode;
+
+	} else if (dm->support_ic_type & ODM_IC_11N_SERIES) {
+		if (phy_sts->rf_mode == 0)
+			bw = CHANNEL_WIDTH_20;
+		else if ((rxsc == 1) || (rxsc == 2))
+			bw = CHANNEL_WIDTH_20;
+		else
+			bw = CHANNEL_WIDTH_40;
+	}
+
+	/* Update packet information */
+	phydm_set_common_phy_info(rx_pwr_db, phy_sts->channel,
+				  (boolean)phy_sts->beamformed, is_mu, bw,
+				  phy_info->rx_mimo_signal_quality[0],
+				  rxsc, phy_info);
+
+	phydm_parsing_cfo(dm, pktinfo, phy_sts->cfo_tail, pktinfo->rate_ss);
+	#ifdef PHYDM_LNA_SAT_CHK_TYPE2
+	phydm_parsing_snr(dm, pktinfo, phy_sts->rxsnr);
+	#endif
+
+	#if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY))
+	dm->dm_fat_table.antsel_rx_keep_0 = phy_sts->antidx_a;
+	dm->dm_fat_table.antsel_rx_keep_1 = phy_sts->antidx_b;
+	dm->dm_fat_table.antsel_rx_keep_2 = phy_sts->antidx_c;
+	dm->dm_fat_table.antsel_rx_keep_3 = phy_sts->antidx_d;
+	#endif
+}
+
+void phydm_get_phy_sts_type2(struct dm_struct *dm, u8 *phy_status_inf,
+			     struct phydm_perpkt_info_struct *pktinfo,
+			     struct phydm_phyinfo_struct *phy_info)
+{
+	struct phy_status_rpt_jaguar2_type2 *phy_sts = NULL;
+	s8 rx_pwr_db_max = -120;
+	s8 rx_pwr = 0;
+	u8 i, rxsc, bw = CHANNEL_WIDTH_20, rx_count = 0;
+
+	phy_sts = (struct phy_status_rpt_jaguar2_type2 *)phy_status_inf;
+
+	for (i = RF_PATH_A; i < PHYDM_MAX_RF_PATH; i++) {
+		if (!(dm->rx_ant_status & BIT(i)))
+			continue;
+		rx_count++;
+
+		if (rx_count > dm->num_rf_path)
+			break;
+
+		/* Update per-path information*/
+		/* RSSI_dB, RSSI_percentage, EVM, SNR, CFO, sq */
+		#if (RTL8197F_SUPPORT)
+		if ((dm->support_ic_type & ODM_RTL8197F) &&
+		    phy_sts->pwdb[i] == 0x7f) { /*@97f workaround*/
+
+			if (i == RF_PATH_A) {
+				rx_pwr = (phy_sts->gain_a) << 1;
+				rx_pwr = rx_pwr - 110;
+			} else if (i == RF_PATH_B) {
+				rx_pwr = (phy_sts->gain_b) << 1;
+				rx_pwr = rx_pwr - 110;
+			} else {
+				rx_pwr = 0;
+			}
+		} else
+		#endif
+			rx_pwr = phy_sts->pwdb[i] - 110; /*@dBm*/
+
+		phydm_set_per_path_phy_info(i, rx_pwr, 0, 0, 0, phy_info);
+
+		if (rx_pwr > rx_pwr_db_max) /* search max pwdb */
+			rx_pwr_db_max = rx_pwr;
+	}
+
+	/* @mapping RX counter from 1~4 to 0~3 */
+	if (rx_count > 0)
+		phy_info->rx_count = rx_count - 1;
+
+	/* @Check RX sub-channel */
+	if (pktinfo->data_rate > ODM_RATE11M &&
+	    pktinfo->data_rate < ODM_RATEMCS0)
+		rxsc = phy_sts->l_rxsc;
+	else
+		rxsc = phy_sts->ht_rxsc;
+
+	/*STBC or LDPC pkt*/
+	dm->phy_dbg_info.is_ldpc_pkt = phy_sts->ldpc;
+	dm->phy_dbg_info.is_stbc_pkt = phy_sts->stbc;
+
+	/* @Check RX bandwidth */
+	/* @BW information of sc=0 is useless,
+	 *because there is no information of RF mode
+	 */
+	if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
+		if (rxsc >= 1 && rxsc <= 8)
+			bw = CHANNEL_WIDTH_20;
+		else if ((rxsc >= 9) && (rxsc <= 12))
+			bw = CHANNEL_WIDTH_40;
+		else if (rxsc >= 13)
+			bw = CHANNEL_WIDTH_80;
+
+	} else if (dm->support_ic_type & ODM_IC_11N_SERIES) {
+		if (rxsc == 3)
+			bw = CHANNEL_WIDTH_40;
+		else if ((rxsc == 1) || (rxsc == 2))
+			bw = CHANNEL_WIDTH_20;
+	}
+
+	/* Update packet information */
+	phydm_set_common_phy_info(rx_pwr_db_max, phy_sts->channel,
+				  (boolean)phy_sts->beamformed,
+				  false, bw, 0, rxsc, phy_info);
+}
+
+void phydm_process_rssi_for_dm_2nd_type(struct dm_struct *dm,
+					struct phydm_phyinfo_struct *phy_info,
+					struct phydm_perpkt_info_struct *pktinfo
+					)
+{
+	struct cmn_sta_info *sta = NULL;
+	struct rssi_info *rssi_t = NULL;
+	u8 rssi_tmp = 0;
+	u32 rssi_linear = 0;
+	s16 rssi_db = 0;
+	u8 i = 0;
+
+	if (pktinfo->station_id >= ODM_ASSOCIATE_ENTRY_NUM)
+		return;
+
+	sta = dm->phydm_sta_info[pktinfo->station_id];
+
+	if (!is_sta_active(sta))
+		return;
+
+	if (!pktinfo->is_packet_match_bssid) /*@data frame only*/
+		return;
+
+#if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY))
+	if (dm->support_ability & ODM_BB_ANT_DIV)
+		odm_process_rssi_for_ant_div(dm, phy_info, pktinfo);
+#endif
+
+#ifdef CONFIG_ADAPTIVE_SOML
+	phydm_rx_qam_for_soml(dm, pktinfo);
+	phydm_rx_rate_for_soml(dm, pktinfo);
+#endif
+
+	if (!(pktinfo->is_packet_to_self) && !(pktinfo->is_packet_beacon))
+		return;
+
+	if (pktinfo->is_packet_beacon) {
+		dm->phy_dbg_info.num_qry_beacon_pkt++;
+		dm->phy_dbg_info.beacon_phy_rate = pktinfo->data_rate;
+	}
+
+	rssi_t = &sta->rssi_stat;
+
+	for (i = RF_PATH_A; i < PHYDM_MAX_RF_PATH; i++) {
+		rssi_tmp = phy_info->rx_mimo_signal_strength[i];
+		if (rssi_tmp != 0)
+			rssi_linear += phydm_db_2_linear(rssi_tmp);
+	}
+
+	switch (phy_info->rx_count + 1) {
+	case 2:
+		rssi_linear = DIVIDED_2(rssi_linear);
+		break;
+	case 3:
+		rssi_linear = DIVIDED_3(rssi_linear);
+		break;
+	case 4:
+		rssi_linear = DIVIDED_4(rssi_linear);
+		break;
+	}
+
+	rssi_db = (s16)odm_convert_to_db(rssi_linear);
+
+	if (rssi_t->rssi_acc == 0) {
+		rssi_t->rssi_acc = (s16)(rssi_db << RSSI_MA);
+		rssi_t->rssi = (s8)(rssi_db);
+	} else {
+		rssi_t->rssi_acc = MA_ACC(rssi_t->rssi_acc, rssi_db, RSSI_MA);
+		rssi_t->rssi = (s8)GET_MA_VAL(rssi_t->rssi_acc, RSSI_MA);
+	}
+
+	#if 0
+	PHYDM_DBG(dm, DBG_TMP, "RSSI[%d]{A,B,C,D}={%d, %d, %d, %d} AVG=%d\n",
+		  pktinfo->station_id,
+		  phy_info->rx_mimo_signal_strength[0],
+		  phy_info->rx_mimo_signal_strength[1],
+		  phy_info->rx_mimo_signal_strength[2],
+		  phy_info->rx_mimo_signal_strength[3], rssi_db);
+	PHYDM_DBG(dm, DBG_TMP, "rssi_acc = %d, rssi=%d\n",
+		  rssi_t->rssi_acc, rssi_t->rssi);
+	#endif
+
+	if (pktinfo->is_cck_rate)
+		rssi_t->rssi_cck = (s8)rssi_db;
+	else
+		rssi_t->rssi_ofdm = (s8)rssi_db;
+}
+
+void phydm_rx_physts_2nd_type(void *dm_void, u8 *phy_sts,
+			      struct phydm_perpkt_info_struct *pktinfo,
+			      struct phydm_phyinfo_struct *phy_info)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+#ifdef PHYDM_PHYSTAUS_SMP_MODE
+	struct pkt_process_info *pkt_process = &dm->pkt_proc_struct;
+#endif
+	u8 page = (*phy_sts & 0xf);
+
+#ifdef PHYDM_PHYSTAUS_SMP_MODE
+	if (pkt_process->phystatus_smp_mode_en && page != 0) {
+		if (pkt_process->pre_ppdu_cnt == pktinfo->ppdu_cnt)
+			return;
+
+		pkt_process->pre_ppdu_cnt = pktinfo->ppdu_cnt;
+	}
+#endif
+
+	phydm_reset_phy_info(dm, phy_info); /* @Memory reset */
+
+	/* Phy status parsing */
+	switch (page) {
+	case 0: /*@CCK*/
+		phydm_get_phy_sts_type0(dm, phy_sts, pktinfo, phy_info);
+		break;
+	case 1:
+		phydm_get_phy_sts_type1(dm, phy_sts, pktinfo, phy_info);
+		break;
+	case 2:
+		phydm_get_phy_sts_type2(dm, phy_sts, pktinfo, phy_info);
+		break;
+	default:
+		break;
+	}
+
+#if (RTL8822B_SUPPORT || RTL8821C_SUPPORT || RTL8195B_SUPPORT)
+	if (dm->support_ic_type & (ODM_RTL8822B | ODM_RTL8821C | ODM_RTL8195B))
+		phydm_print_phy_sts_jgr2(dm, phy_sts, pktinfo, phy_info);
+#endif
+}
+
+/*@==============================================*/
+#endif
+
+void odm_phy_status_query(struct dm_struct *dm,
+			  struct phydm_phyinfo_struct *phy_info,
+			  u8 *phy_status_inf,
+			  struct phydm_perpkt_info_struct *pktinfo)
+{
+	u8 rate = pktinfo->data_rate;
+
+	pktinfo->is_cck_rate = (rate <= ODM_RATE11M) ? true : false;
+	pktinfo->rate_ss = phydm_rate_to_num_ss(dm, rate);
+	dm->rate_ss = pktinfo->rate_ss; /*@For AP EVM SW antenna diversity use*/
+
+	if (pktinfo->is_cck_rate)
+		dm->phy_dbg_info.num_qry_phy_status_cck++;
+	else
+		dm->phy_dbg_info.num_qry_phy_status_ofdm++;
+
+	/*Reset phy_info*/
+	odm_memory_set(dm, phy_info->rx_mimo_signal_strength, 0, 4);
+	odm_memory_set(dm, phy_info->rx_mimo_signal_quality, 0, 4);
+	if (dm->support_ic_type & PHYSTS_3RD_TYPE_IC) {
+		#ifdef PHYSTS_3RD_TYPE_SUPPORT
+		phydm_rx_physts_3rd_type(dm, phy_status_inf, pktinfo, phy_info);
+		phydm_process_dm_rssi_3rd_type(dm, phy_info, pktinfo);
+		#endif
+	} else if (dm->support_ic_type & PHYSTS_2ND_TYPE_IC) {
+		#if (ODM_PHY_STATUS_NEW_TYPE_SUPPORT == 1)
+		phydm_rx_physts_2nd_type(dm, phy_status_inf, pktinfo, phy_info);
+		phydm_process_rssi_for_dm_2nd_type(dm, phy_info, pktinfo);
+		#endif
+	} else if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
+		#if ODM_IC_11AC_SERIES_SUPPORT
+		phydm_rx_physts_1st_type(dm, phy_info, phy_status_inf, pktinfo);
+		phydm_process_rssi_for_dm(dm, phy_info, pktinfo);
+		#endif
+	} else if (dm->support_ic_type & ODM_IC_11N_SERIES) {
+		#if ODM_IC_11N_SERIES_SUPPORT
+		phydm_phy_sts_n_parsing(dm, phy_info, phy_status_inf, pktinfo);
+		phydm_process_rssi_for_dm(dm, phy_info, pktinfo);
+		#endif
+	}
+	phy_info->signal_strength = phy_info->rx_pwdb_all;
+	#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
+	phydm_process_signal_strength(dm, phy_info, pktinfo);
+	#endif
+
+	if (pktinfo->is_packet_match_bssid) {
+		dm->curr_station_id = pktinfo->station_id;
+		dm->rx_rate = rate;
+		dm->rssi_a = phy_info->rx_mimo_signal_strength[RF_PATH_A];
+		dm->rssi_b = phy_info->rx_mimo_signal_strength[RF_PATH_B];
+		dm->rssi_c = phy_info->rx_mimo_signal_strength[RF_PATH_C];
+		dm->rssi_d = phy_info->rx_mimo_signal_strength[RF_PATH_D];
+
+		if (rate >= ODM_RATE6M && rate <= ODM_RATE54M)
+			dm->rxsc_l = (s8)phy_info->rxsc;
+		else if (phy_info->band_width == CHANNEL_WIDTH_20)
+			dm->rxsc_20 = (s8)phy_info->rxsc;
+		else if (phy_info->band_width == CHANNEL_WIDTH_40)
+			dm->rxsc_40 = (s8)phy_info->rxsc;
+		else if (phy_info->band_width == CHANNEL_WIDTH_80)
+			dm->rxsc_80 = (s8)phy_info->rxsc;
+
+		phydm_avg_phystatus_index(dm, phy_info, pktinfo);
+		phydm_rx_statistic_cal(dm, phy_info, phy_status_inf, pktinfo);
+	}
+}
+
+void phydm_rx_phy_status_init(void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct odm_phy_dbg_info *dbg = &dm->phy_dbg_info;
+#ifdef PHYDM_PHYSTAUS_SMP_MODE
+	struct pkt_process_info *pkt_process = &dm->pkt_proc_struct;
+
+	if (dm->support_ic_type & ODM_RTL8822B) {
+		pkt_process->phystatus_smp_mode_en = 1;
+		pkt_process->pre_ppdu_cnt = 0xff;
+		/*phystatus sampling mode enable*/
+		odm_set_mac_reg(dm, R_0x60f, BIT(7), 1);
+		/*@First update timming*/
+		odm_set_bb_reg(dm, R_0x9e4, 0x3ff, 0x0);
+		/*Update Sampling time*/
+		odm_set_bb_reg(dm, R_0x9e4, 0xfc00, 0x0);
+	} else if (dm->support_ic_type & ODM_IC_JGR3_SERIES) {
+		/*@First update timming*/
+		odm_set_bb_reg(dm, R_0x8c0, 0x3ff0, 0x0);
+		/*Update Sampling time*/
+		odm_set_bb_reg(dm, R_0x8c0, 0xfc000, 0x0);
+	}
+#endif
+
+	dbg->show_phy_sts_all_pkt = 0;
+	dbg->show_phy_sts_max_cnt = 1;
+	dbg->show_phy_sts_cnt = 0;
+
+	phydm_avg_phystatus_init(dm);
+}
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/phydm_phystatus.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/phydm_phystatus.h
--- linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/phydm_phystatus.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/phydm_phystatus.h	2020-04-10 16:35:06.826660535 +0300
@@ -0,0 +1,1137 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017  Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * The full GNU General Public License is included in this distribution in the
+ * file called LICENSE.
+ *
+ * Contact Information:
+ * wlanfae <wlanfae@realtek.com>
+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
+ * Hsinchu 300, Taiwan.
+ *
+ * Larry Finger <Larry.Finger@lwfinger.net>
+ *
+ *****************************************************************************/
+
+#ifndef __PHYDM_PHYSTATUS_H__
+#define __PHYDM_PHYSTATUS_H__
+
+/*@--------------------------Define ------------------------------------------*/
+#define CCK_RSSI_INIT_COUNT 5
+
+#define RA_RSSI_STATE_INIT 0
+#define RA_RSSI_STATE_SEND 1
+#define RA_RSSI_STATE_HOLD 2
+
+#if defined(DM_ODM_CE_MAC80211)
+#define CFO_HW_RPT_2_KHZ(val) ({		\
+	s32 cfo_hw_rpt_2_khz_tmp = (val);	\
+	(cfo_hw_rpt_2_khz_tmp << 1) + (cfo_hw_rpt_2_khz_tmp >> 1);	\
+	})
+#else
+#define CFO_HW_RPT_2_KHZ(val) ((val << 1) + (val >> 1))
+#endif
+
+/* @(X* 312.5 Khz)>>7 ~=  X*2.5 Khz= (X<<1 + X>>1)Khz  */
+
+#define IGI_2_RSSI(igi) (igi - 10)
+
+#define PHY_STATUS_JRGUAR2_DW_LEN 7 /* @7*4 = 28 Byte */
+#define PHY_STATUS_JRGUAR3_DW_LEN 7 /* @7*4 = 28 Byte */
+#define SHOW_PHY_STATUS_UNLIMITED 0
+#define RSSI_MA 4
+
+#define PHYSTS_PATH_NUM 4
+
+/*@************************************************************
+ * structure and define
+ ************************************************************/
+
+__PACK struct phy_rx_agc_info {
+#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
+	u8 gain : 7, trsw : 1;
+#else
+	u8 trsw : 1, gain : 7;
+#endif
+};
+
+__PACK struct phy_status_rpt_8192cd {
+	struct phy_rx_agc_info path_agc[2];
+	u8	ch_corr[2];
+	u8	cck_sig_qual_ofdm_pwdb_all;
+	u8	cck_agc_rpt_ofdm_cfosho_a;
+	u8	cck_rpt_b_ofdm_cfosho_b;
+	u8	rsvd_1;/*@ch_corr_msb;*/
+	u8	noise_power_db_msb;
+	s8	path_cfotail[2];
+	u8	pcts_mask[2];
+	s8	stream_rxevm[2];
+	u8	path_rxsnr[2];
+	u8	noise_power_db_lsb;
+	u8	rsvd_2[3];
+	u8	stream_csi[2];
+	u8	stream_target_csi[2];
+	s8	sig_evm;
+	u8	rsvd_3;
+
+#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
+	u8	antsel_rx_keep_2: 1;	/*@ex_intf_flg:1;*/
+	u8	sgi_en: 1;
+	u8	rxsc: 2;
+	u8	idle_long: 1;
+	u8	r_ant_train_en: 1;
+	u8	ant_sel_b: 1;
+	u8	ant_sel: 1;
+#else	/*@_BIG_ENDIAN_	*/
+	u8	ant_sel: 1;
+	u8	ant_sel_b: 1;
+	u8	r_ant_train_en: 1;
+	u8	idle_long: 1;
+	u8	rxsc: 2;
+	u8	sgi_en: 1;
+	u8	antsel_rx_keep_2: 1;/*@ex_intf_flg:1;*/
+#endif
+};
+
+struct phy_status_rpt_8812 {
+	/*	@DWORD 0*/
+	u8 gain_trsw[2]; /*path-A and path-B {TRSW, gain[6:0] }*/
+	u8 chl_num_LSB; /*@channel number[7:0]*/
+#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
+	u8 chl_num_MSB : 2; /*@channel number[9:8]*/
+	u8 sub_chnl : 4; /*sub-channel location[3:0]*/
+	u8 r_RFMOD : 2; /*RF mode[1:0]*/
+#else /*@_BIG_ENDIAN_	*/
+	u8 r_RFMOD : 2;
+	u8 sub_chnl : 4;
+	u8 chl_num_MSB : 2;
+#endif
+
+	/*	@DWORD 1*/
+	u8 pwdb_all; /*@CCK signal quality / OFDM pwdb all*/
+	s8 cfosho[2]; /*@CCK AGC report and CCK_BB_Power*/
+		      /*OFDM path-A and path-B short CFO*/
+#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
+	u8 resvd_0 : 6;
+	u8 bt_RF_ch_MSB : 2; /*@8812A:2'b0  8814A: bt rf channel keep[7:6]*/
+#else /*@_BIG_ENDIAN_*/
+	u8 bt_RF_ch_MSB : 2;
+	u8 resvd_0 : 6;
+#endif
+
+/*	@DWORD 2*/
+#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
+	u8 ant_div_sw_a : 1; /*@8812A: ant_div_sw_a    8814A: 1'b0*/
+	u8 ant_div_sw_b : 1; /*@8812A: ant_div_sw_b    8814A: 1'b0*/
+	u8 bt_RF_ch_LSB : 6; /*@8812A: 6'b0     8814A: bt rf channel keep[5:0]*/
+#else /*@_BIG_ENDIAN_	*/
+	u8 bt_RF_ch_LSB : 6;
+	u8 ant_div_sw_b : 1;
+	u8 ant_div_sw_a : 1;
+#endif
+	s8 cfotail[2]; /*@DW2 byte 1 DW2 byte 2	path-A and path-B CFO tail*/
+	u8 PCTS_MSK_RPT_0; /*PCTS mask report[7:0]*/
+	u8 PCTS_MSK_RPT_1; /*PCTS mask report[15:8]*/
+
+	/*	@DWORD 3*/
+	s8 rxevm[2]; /*@DW3 byte 1 DW3 byte 2	stream 1 and stream 2 RX EVM*/
+	s8 rxsnr[2]; /*@DW3 byte 3 DW4 byte 0	path-A and path-B RX SNR*/
+
+	/*	@DWORD 4*/
+	u8 PCTS_MSK_RPT_2; /*PCTS mask report[23:16]*/
+#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
+	u8 PCTS_MSK_RPT_3 : 6; /*PCTS mask report[29:24]*/
+	u8 pcts_rpt_valid : 1; /*pcts_rpt_valid*/
+	u8 resvd_1 : 1; /*@1'b0*/
+#else /*@_BIG_ENDIAN_*/
+	u8 resvd_1 : 1;
+	u8 pcts_rpt_valid : 1;
+	u8 PCTS_MSK_RPT_3 : 6;
+#endif
+	s8 rxevm_cd[2]; /*@8812A: 16'b0*/
+			/*@8814A: stream 3 and stream 4 RX EVM*/
+	/*	@DWORD 5*/
+	u8 csi_current[2]; /*@8812A: stream 1 and 2 CSI*/
+			   /*@8814A:  path-C and path-D RX SNR*/
+	u8 gain_trsw_cd[2]; /*path-C and path-D {TRSW, gain[6:0] }*/
+
+	/*	@DWORD 6*/
+	s8 sigevm; /*signal field EVM*/
+#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
+	u8 antidx_antc : 3;	/*@8812A: 3'b0	8814A: antidx_antc[2:0]*/
+	u8 antidx_antd : 3;	/*@8812A: 3'b0	8814A: antidx_antd[2:0]*/
+	u8 dpdt_ctrl_keep : 1;	/*@8812A: 1'b0	8814A: dpdt_ctrl_keep*/
+	u8 GNT_BT_keep : 1;	/*@8812A: 1'b0	8814A: GNT_BT_keep*/
+#else /*@_BIG_ENDIAN_*/
+	u8 GNT_BT_keep : 1;
+	u8 dpdt_ctrl_keep : 1;
+	u8 antidx_antd : 3;
+	u8 antidx_antc : 3;
+#endif
+#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
+	u8 antidx_anta : 3; /*@antidx_anta[2:0]*/
+	u8 antidx_antb : 3; /*@antidx_antb[2:0]*/
+	u8 hw_antsw_occur : 2; /*@1'b0*/
+#else /*@_BIG_ENDIAN_*/
+	u8 hw_antsw_occur : 2;
+	u8 antidx_antb : 3;
+	u8 antidx_anta : 3;
+#endif
+};
+
+#if (ODM_PHY_STATUS_NEW_TYPE_SUPPORT == 1)
+
+__PACK struct phy_status_rpt_jaguar2_type0 {
+	/* @DW0 */
+	u8 page_num;
+	u8 pwdb;
+#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
+	u8 gain : 6;
+	u8 rsvd_0 : 1;
+	u8 trsw : 1;
+#else
+	u8 trsw : 1;
+	u8 rsvd_0 : 1;
+	u8 gain : 6;
+#endif
+	u8 rsvd_1;
+
+	/* @DW1 */
+	u8 rsvd_2;
+#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
+	u8 rxsc : 4;
+	u8 agc_table : 4;
+#else
+	u8 agc_table : 4;
+	u8 rxsc : 4;
+#endif
+	u8 channel;
+	u8 band;
+
+	/* @DW2 */
+	u16 length;
+#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
+	u8 antidx_a : 3;
+	u8 antidx_b : 3;
+	u8 rsvd_3 : 2;
+	u8 antidx_c : 3;
+	u8 antidx_d : 3;
+	u8 rsvd_4 : 2;
+#else
+	u8 rsvd_3 : 2;
+	u8 antidx_b : 3;
+	u8 antidx_a : 3;
+	u8 rsvd_4 : 2;
+	u8 antidx_d : 3;
+	u8 antidx_c : 3;
+#endif
+
+	/* @DW3 */
+	u8 signal_quality;
+#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
+	u8 vga : 5;
+	u8 lna_l : 3;
+	u8 bb_power : 6;
+	u8 rsvd_9 : 1;
+	u8 lna_h : 1;
+#else
+	u8 lna_l : 3;
+	u8 vga : 5;
+	u8 lna_h : 1;
+	u8 rsvd_9 : 1;
+	u8 bb_power : 6;
+#endif
+	u8 rsvd_5;
+
+	/* @DW4 */
+	u32 rsvd_6;
+
+	/* @DW5 */
+	u32 rsvd_7;
+
+	/* @DW6 */
+	u32 rsvd_8;
+};
+
+__PACK struct phy_status_rpt_jaguar2_type1 {
+	/* @DW0 and DW1 */
+	u8 page_num;
+	u8 pwdb[4];
+#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
+	u8 l_rxsc : 4;
+	u8 ht_rxsc : 4;
+#else
+	u8 ht_rxsc : 4;
+	u8 l_rxsc : 4;
+#endif
+	u8 channel;
+#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
+	u8 band : 2;
+	u8 rsvd_0 : 1;
+	u8 hw_antsw_occu : 1;
+	u8 gnt_bt : 1;
+	u8 ldpc : 1;
+	u8 stbc : 1;
+	u8 beamformed : 1;
+#else
+	u8 beamformed : 1;
+	u8 stbc : 1;
+	u8 ldpc : 1;
+	u8 gnt_bt : 1;
+	u8 hw_antsw_occu : 1;
+	u8 rsvd_0 : 1;
+	u8 band : 2;
+#endif
+
+	/* @DW2 */
+	u16 lsig_length;
+#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
+	u8 antidx_a : 3;
+	u8 antidx_b : 3;
+	u8 rsvd_1 : 2;
+	u8 antidx_c : 3;
+	u8 antidx_d : 3;
+	u8 rsvd_2 : 2;
+#else
+	u8 rsvd_1 : 2;
+	u8 antidx_b : 3;
+	u8 antidx_a : 3;
+	u8 rsvd_2 : 2;
+	u8 antidx_d : 3;
+	u8 antidx_c : 3;
+#endif
+
+	/* @DW3 */
+	u8 paid;
+#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
+	u8 paid_msb : 1;
+	u8 gid : 6;
+	u8 rsvd_3 : 1;
+#else
+	u8 rsvd_3 : 1;
+	u8 gid : 6;
+	u8 paid_msb : 1;
+#endif
+	u8 intf_pos;
+#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
+	u8 intf_pos_msb : 1;
+	u8 rsvd_4 : 2;
+	u8 nb_intf_flag : 1;
+	u8 rf_mode : 2;
+	u8 rsvd_5 : 2;
+#else
+	u8 rsvd_5 : 2;
+	u8 rf_mode : 2;
+	u8 nb_intf_flag : 1;
+	u8 rsvd_4 : 2;
+	u8 intf_pos_msb : 1;
+#endif
+
+	/* @DW4 */
+	s8 rxevm[4]; /* s(8,1) */
+
+	/* @DW5 */
+	s8 cfo_tail[4]; /* s(8,7) */
+
+	/* @DW6 */
+	s8 rxsnr[4]; /* s(8,1) */
+};
+
+__PACK struct phy_status_rpt_jaguar2_type2 {
+	/* @DW0 ane DW1 */
+	u8 page_num;
+	u8 pwdb[4];
+#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
+	u8 l_rxsc : 4;
+	u8 ht_rxsc : 4;
+#else
+	u8 ht_rxsc : 4;
+	u8 l_rxsc : 4;
+#endif
+	u8 channel;
+#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
+	u8 band : 2;
+	u8 rsvd_0 : 1;
+	u8 hw_antsw_occu : 1;
+	u8 gnt_bt : 1;
+	u8 ldpc : 1;
+	u8 stbc : 1;
+	u8 beamformed : 1;
+#else
+	u8 beamformed : 1;
+	u8 stbc : 1;
+	u8 ldpc : 1;
+	u8 gnt_bt : 1;
+	u8 hw_antsw_occu : 1;
+	u8 rsvd_0 : 1;
+	u8 band : 2;
+#endif
+
+/* @DW2 */
+#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
+	u8 shift_l_map : 6;
+	u8 rsvd_1 : 2;
+#else
+	u8 rsvd_1 : 2;
+	u8 shift_l_map : 6;
+#endif
+	u8 cnt_pw2cca;
+#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
+	u8 agc_table_a : 4;
+	u8 agc_table_b : 4;
+	u8 agc_table_c : 4;
+	u8 agc_table_d : 4;
+#else
+	u8 agc_table_b : 4;
+	u8 agc_table_a : 4;
+	u8 agc_table_d : 4;
+	u8 agc_table_c : 4;
+#endif
+
+	/* @DW3 ~ DW6*/
+	u8 cnt_cca2agc_rdy;
+#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
+	u8 gain_a : 6;
+	u8 rsvd_2 : 1;
+	u8 trsw_a : 1;
+	u8 gain_b : 6;
+	u8 rsvd_3 : 1;
+	u8 trsw_b : 1;
+	u8 gain_c : 6;
+	u8 rsvd_4 : 1;
+	u8 trsw_c : 1;
+	u8 gain_d : 6;
+	u8 rsvd_5 : 1;
+	u8 trsw_d : 1;
+	u8 aagc_step_a : 2;
+	u8 aagc_step_b : 2;
+	u8 aagc_step_c : 2;
+	u8 aagc_step_d : 2;
+#else
+	u8 trsw_a : 1;
+	u8 rsvd_2 : 1;
+	u8 gain_a : 6;
+	u8 trsw_b : 1;
+	u8 rsvd_3 : 1;
+	u8 gain_b : 6;
+	u8 trsw_c : 1;
+	u8 rsvd_4 : 1;
+	u8 gain_c : 6;
+	u8 trsw_d : 1;
+	u8 rsvd_5 : 1;
+	u8 gain_d : 6;
+	u8 aagc_step_d : 2;
+	u8 aagc_step_c : 2;
+	u8 aagc_step_b : 2;
+	u8 aagc_step_a : 2;
+#endif
+	u8 ht_aagc_gain[4];
+	u8 dagc_gain[4];
+#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
+	u8 counter : 6;
+	u8 rsvd_6 : 2;
+	u8 syn_count : 5;
+	u8 rsvd_7 : 3;
+#else
+	u8 rsvd_6 : 2;
+	u8 counter : 6;
+	u8 rsvd_7 : 3;
+	u8 syn_count : 5;
+#endif
+};
+#endif
+
+/*@==============================================*/
+#ifdef PHYSTS_3RD_TYPE_SUPPORT
+__PACK struct phy_status_rpt_jaguar3_type0 {
+/* @DW0 : Offset 0 */
+#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
+	u8 page_num : 4;
+	u8 pkt_cnt : 2;
+	u8 channel_msb : 2;
+#else
+	u8 channel_msb : 2;
+	u8 pkt_cnt : 2;
+	u8 page_num : 4;
+#endif
+	u8 pwdb_a;
+#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
+	u8 gain_a : 6;
+	u8 rsvd_0 : 1;
+	u8 trsw : 1;
+#else
+	u8 trsw : 1;
+	u8 rsvd_0 : 1;
+	u8 gain_a : 6;
+#endif
+
+#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
+	u8 agc_table_b : 4;
+	u8 agc_table_c : 4;
+#else
+	u8 agc_table_c : 4;
+	u8 agc_table_b : 4;
+#endif
+
+/* @DW1 : Offset 4 */
+#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
+	u8 rsvd_1 : 4;
+	u8 agc_table_d : 4;
+#else
+	u8 agc_table_d : 4;
+	u8 rsvd_1 : 4;
+#endif
+#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
+	u8 l_rxsc : 4;
+	u8 agc_table_a : 4;
+#else
+	u8 agc_table_a : 4;
+	u8 l_rxsc : 4;
+#endif
+	u8 channel;
+#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
+	u8 band : 2;
+	u8 rsvd_2_1 : 1;
+	u8 hw_antsw_occur_keep_cck : 1;
+	u8 gnt_bt_keep_cck : 1;
+	u8 rsvd_2_2 : 1;
+	u8 path_sel_o : 2;
+#else
+	u8 path_sel_o : 2;
+	u8 rsvd_2_2 : 1;
+	u8 gnt_bt_keep_cck : 1;
+	u8 hw_antsw_occur_keep_cck : 1;
+	u8 rsvd_2_1 : 1;
+	u8 band : 2;
+#endif
+
+	/* @DW2 : Offset 8 */
+	u16 length;
+#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
+	u8 antidx_a : 4;
+	u8 antidx_b : 4;
+#else
+	u8 antidx_b : 4;
+	u8 antidx_a : 4;
+#endif
+#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
+	u8 antidx_c : 4;
+	u8 antidx_d : 4;
+#else
+	u8 antidx_d : 4;
+	u8 antidx_c : 4;
+#endif
+
+	/* @DW3 : Offset 12 */
+	u8 signal_quality;
+#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
+	u8 vga_a : 5;
+	u8 lna_l_a : 3;
+#else
+	u8 lna_l_a : 3;
+	u8 vga_a : 5;
+#endif
+#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
+	u8 bb_power_a : 6;
+	u8 rsvd_3_1 : 1;
+	u8 lna_h_a : 1;
+#else
+
+	u8 lna_h_a : 1;
+	u8 rsvd_3_1 : 1;
+	u8 bb_power_a : 6;
+#endif
+#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
+	u8 rxrate : 2;
+	u8 raterr : 1;
+	u8 lockbit : 1;
+	u8 sqloss : 1;
+	u8 mf_off : 1;
+	u8 rsvd_3_2 : 2;
+#else
+	u8 rsvd_3_2 : 2;
+	u8 mf_off : 1;
+	u8 sqloss : 1;
+	u8 lockbit : 1;
+	u8 raterr : 1;
+	u8 rxrate : 2;
+#endif
+
+	/* @DW4 : Offset 16 */
+	u8 pwdb_b;
+#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
+	u8 vga_b : 5;
+	u8 lna_l_b : 3;
+#else
+	u8 lna_l_b : 3;
+	u8 vga_b : 5;
+#endif
+#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
+	u8 bb_power_b : 6;
+	u8 rsvd_4_1 : 1;
+	u8 lna_h_b : 1;
+#else
+	u8 lna_h_b : 1;
+	u8 rsvd_4_1 : 1;
+	u8 bb_power_b : 6;
+#endif
+#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
+	u8 gain_b : 6;
+	u8 rsvd_4_2 : 2;
+#else
+	u8 rsvd_4_2 : 2;
+	u8 gain_b : 6;
+#endif
+
+	/* @DW5 : Offset 20 */
+	u8 pwdb_c;
+#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
+	u8 vga_c : 5;
+	u8 lna_l_c : 3;
+#else
+	u8 lna_l_c : 3;
+	u8 vga_c : 5;
+#endif
+#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
+	u8 bb_power_c : 6;
+	u8 rsvd_5_1 : 1;
+	u8 lna_h_c : 1;
+#else
+	u8 lna_h_c : 1;
+	u8 rsvd_5_1 : 1;
+	u8 bb_power_c : 6;
+#endif
+#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
+	u8 gain_c : 6;
+	u8 rsvd_5_2 : 2;
+#else
+	u8 rsvd_5_2 : 2;
+	u8 gain_c : 6;
+#endif
+
+	/* @DW6 : Offset 24 */
+	u8 pwdb_d;
+#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
+	u8 vga_d : 5;
+	u8 lna_l_d : 3;
+#else
+	u8 lna_l_d : 3;
+	u8 vga_d : 5;
+#endif
+#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
+	u8 bb_power_d : 6;
+	u8 rsvd_6_1 : 1;
+	u8 lna_h_d : 1;
+#else
+	u8 lna_h_d : 1;
+	u8 rsvd_6_1 : 1;
+	u8 bb_power_d : 6;
+#endif
+#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
+	u8 gain_d : 6;
+	u8 rsvd_6_2 : 2;
+#else
+	u8 rsvd_6_2 : 2;
+	u8 gain_d : 6;
+#endif
+};
+
+__PACK struct phy_status_rpt_jaguar3_type1 {
+/* @DW0 : Offset 0 */
+#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
+	u8 page_num : 4;
+	u8 pkt_cnt : 2;
+	u8 channel_pri_msb : 2;
+#else
+	u8 channel_pri_msb : 2;
+	u8 pkt_cnt : 2;
+	u8 page_num : 4;
+#endif
+	u8 pwdb_a;
+	u8 pwdb_b;
+	u8 pwdb_c;
+
+	/* @DW1 : Offset 4 */
+	u8 pwdb_d;
+#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
+	u8 l_rxsc : 4;
+	u8 ht_rxsc : 4;
+#else
+	u8 ht_rxsc : 4;
+	u8 l_rxsc : 4;
+#endif
+	u8 channel_pri_lsb;
+#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
+	u8 band : 2;
+	u8 rsvd_0 : 2;
+	u8 gnt_bt : 1;
+	u8 ldpc : 1;
+	u8 stbc : 1;
+	u8 beamformed : 1;
+#else
+	u8 beamformed : 1;
+	u8 stbc : 1;
+	u8 ldpc : 1;
+	u8 gnt_bt : 1;
+	u8 rsvd_0 : 2;
+	u8 band : 2;
+#endif
+
+	/* @DW2 : Offset 8 */
+	u8 channel_sec_lsb;
+#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
+	u8 channel_sec_msb : 2;
+	u8 rsvd_1 : 2;
+	u8 hw_antsw_occur_a : 1;
+	u8 hw_antsw_occur_b : 1;
+	u8 hw_antsw_occur_c : 1;
+	u8 hw_antsw_occur_d : 1;
+#else
+	u8 hw_antsw_occur_d : 1;
+	u8 hw_antsw_occur_c : 1;
+	u8 hw_antsw_occur_b : 1;
+	u8 hw_antsw_occur_a : 1;
+	u8 rsvd_1 : 2;
+	u8 channel_sec_msb : 2;
+
+#endif
+#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
+	u8 antidx_a : 4;
+	u8 antidx_b : 4;
+#else
+	u8 antidx_b : 4;
+	u8 antidx_a : 4;
+#endif
+#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
+	u8 antidx_c : 4;
+	u8 antidx_d : 4;
+#else
+	u8 antidx_d : 4;
+	u8 antidx_c : 4;
+#endif
+
+	/* @DW3 : Offset 12 */
+	u8 paid;
+#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
+	u8 paid_msb : 1;
+	u8 gid : 6;
+	u8 rsvd_3 : 1;
+#else
+	u8 rsvd_3 : 1;
+	u8 gid : 6;
+	u8 paid_msb : 1;
+#endif
+	u16 rsvd_4;
+#if 0
+	/*@
+	u8		rsvd_4;
+#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
+	u8		rsvd_5: 6;
+	u8		rf_mode: 2;
+#else
+	u8		rf_mode: 2;
+	u8		rsvd_5: 6;
+#endif
+*/
+#endif
+	/* @DW4 : Offset 16 */
+	s8 rxevm[4]; /* s(8,1) */
+
+	/* @DW5 : Offset 20 */
+	s8 cfo_tail[4]; /* s(8,7) */
+
+	/* @DW6 : Offset 24 */
+	s8 rxsnr[4]; /* s(8,1) */
+};
+
+__PACK struct phy_status_rpt_jaguar3_type2_type3 {
+/* Type2 is primary channel & type3 is secondary channel */
+/* @DW0 and DW1: Offest 0 and Offset 4 */
+#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
+	u8 page_num : 4;
+	u8 pkt_cnt : 2;
+	u8 channel_msb : 2;
+#else
+	u8 channel_msb : 2;
+	u8 pkt_cnt : 2;
+	u8 page_num : 4;
+#endif
+	u8 pwdb[4];
+#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
+	u8 l_rxsc : 4;
+	u8 ht_rxsc : 4;
+#else
+	u8 ht_rxsc : 4;
+	u8 l_rxsc : 4;
+#endif
+	u8 channel_lsb;
+#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
+	u8 band : 2;
+	u8 rsvd_0 : 2;
+	u8 gnt_bt : 1;
+	u8 ldpc : 1;
+	u8 stbc : 1;
+	u8 beamformed : 1;
+#else
+	u8 beamformed : 1;
+	u8 stbc : 1;
+	u8 ldpc : 1;
+	u8 gnt_bt : 1;
+	u8 rsvd_0 : 2;
+	u8 band : 2;
+#endif
+
+/* @DW2 : Offset 8 */
+#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
+	u8 shift_l_map : 6;
+	u8 rsvd_1 : 2;
+#else
+	u8 rsvd_1 : 2;
+	u8 shift_l_map : 6;
+#endif
+	s8 pwed_th; /* @dynamic energy threshold S(8,2) */
+#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
+	u8 agc_table_a : 4;
+	u8 agc_table_b : 4;
+#else
+	u8 agc_table_b : 4;
+	u8 agc_table_a : 4;
+#endif
+#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
+	u8 agc_table_c : 4;
+	u8 agc_table_d : 4;
+#else
+	u8 agc_table_d : 4;
+	u8 agc_table_c : 4;
+#endif
+
+	/* @DW3 : Offset 12 */
+	u8 cnt_cca2agc_rdy; /* Time(ns) = cnt_cca2agc_ready*25 */
+#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
+	u8 mp_gain_a : 6;
+	u8 mp_gain_b_lsb : 2;
+#else
+	u8 mp_gain_b_lsb : 2;
+	u8 mp_gain_a : 6;
+#endif
+#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
+	u8 mp_gain_b_msb : 4;
+	u8 mp_gain_c_lsb : 4;
+#else
+	u8 mp_gain_c_lsb : 4;
+	u8 mp_gain_b_msb : 4;
+#endif
+#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
+	u8 mp_gain_c_msb : 2;
+	u8 avg_noise_pwr_lsb : 4;
+	u8 rsvd_3 : 2;
+	/* u8		r_rfmod:2; */
+#else
+	/* u8		r_rfmod:2; */
+	u8 rsvd_3 : 2;
+	u8 avg_noise_pwr_lsb : 4;
+	u8 mp_gain_c_msb : 2;
+#endif
+	/* @DW4 ~ 5: offset 16 ~20 */
+#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
+	u8 mp_gain_d : 6;
+	u8 is_freq_select_fading : 1;
+	u8 rsvd_2 : 1;
+#else
+	u8 rsvd_2 : 1;
+	u8 is_freq_select_fading : 1;
+	u8 mp_gain_d : 6;
+#endif
+#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
+	u8 aagc_step_a : 2;
+	u8 aagc_step_b : 2;
+	u8 aagc_step_c : 2;
+	u8 aagc_step_d : 2;
+#else
+	u8 aagc_step_d : 2;
+	u8 aagc_step_c : 2;
+	u8 aagc_step_b : 2;
+	u8 aagc_step_a : 2;
+#endif
+	u8 ht_aagc_gain[4];
+	u8 dagc_gain[4];
+#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
+	u8 counter : 6;
+	u8 syn_count_lsb : 2;
+#else
+	u8 syn_count_lsb : 2;
+	u8 counter : 6;
+#endif
+#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
+	u8 syn_count_msb : 3;
+	u8 avg_noise_pwr_msb : 5;
+#else
+	u8 avg_noise_pwr_msb : 5;
+	u8 syn_count_msb : 3;
+#endif
+};
+
+__PACK struct phy_status_rpt_jaguar3_type4 {
+/* smart antenna */
+/* @DW0 and DW1 : offset 0 and 4  */
+#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
+	u8 page_num : 4;
+	u8 pkt_cnt : 2;
+	u8 channel_msb : 2;
+#else
+	u8 channel_msb : 2;
+	u8 pkt_cnt : 2;
+	u8 page_num : 4;
+#endif
+	u8 pwdb[4];
+#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
+	u8 l_rxsc : 4;
+	u8 ht_rxsc : 4;
+#else
+	u8 ht_rxsc : 4;
+	u8 l_rxsc : 4;
+#endif
+	u8 channel_lsb;
+#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
+	u8 band : 2;
+	u8 rsvd_0 : 2;
+	u8 gnt_bt : 1;
+	u8 ldpc : 1;
+	u8 stbc : 1;
+	u8 beamformed : 1;
+#else
+	u8 beamformed : 1;
+	u8 stbc : 1;
+	u8 ldpc : 1;
+	u8 gnt_bt : 1;
+	u8 rsvd_0 : 1;
+	u8 band : 2;
+#endif
+
+/* @DW2 : offset 8 */
+#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
+	u8 bad_tone_cnt_min_eign_0 : 4;
+	u8 bad_tone_cnt_cn_excess_0 : 4;
+#else
+	u8 bad_tone_cnt_cn_excess_0 : 4;
+	u8 bad_tone_cnt_min_eign_0 : 4;
+#endif
+#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
+	u8 training_done_a : 1;
+	u8 training_done_b : 1;
+	u8 training_done_c : 1;
+	u8 training_done_d : 1;
+	u8 hw_antsw_occur_a : 1;
+	u8 hw_antsw_occur_b : 1;
+	u8 hw_antsw_occur_c : 1;
+	u8 hw_antsw_occur_d : 1;
+#else
+	u8 hw_antsw_occur_d : 1;
+	u8 hw_antsw_occur_c : 1;
+	u8 hw_antsw_occur_b : 1;
+	u8 hw_antsw_occur_a : 1;
+	u8 training_done_d : 1;
+	u8 training_done_c : 1;
+	u8 training_done_b : 1;
+	u8 training_done_a : 1;
+#endif
+#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
+	u8 antidx_a : 4;
+	u8 antidx_b : 4;
+#else
+	u8 antidx_b : 4;
+	u8 antidx_a : 4;
+#endif
+#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
+	u8 antidx_c : 4;
+	u8 antidx_d : 4;
+#else
+	u8 antidx_d : 4;
+	u8 antidx_c : 4;
+#endif
+/* @DW3 : offset 12 */
+	u8 tx_pkt_cnt;
+#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
+	u8 bad_tone_cnt_min_eign_1 : 4;
+	u8 bad_tone_cnt_cn_excess_1 : 4;
+#else
+	u8 bad_tone_cnt_cn_excess_1 : 4;
+	u8 bad_tone_cnt_min_eign_1 : 4;
+#endif
+#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
+	u8 avg_cond_num_0 : 7;
+	u8 avg_cond_num_1_lsb : 1;
+#else
+	u8 avg_cond_num_1_lsb : 1;
+	u8 avg_cond_num_0 : 7;
+#endif
+#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
+	u8 avg_cond_num_1_msb : 6;
+	u8 rsvd_1 : 2;
+#else
+	u8 rsvd_1 : 2;
+	u8 avg_cond_num_1_msb : 6;
+#endif
+
+	/* @DW4 : offset 16 */
+	s8 rxevm[4]; /* s(8,1) */
+
+	/* @DW5 : offset 20 */
+	u8 eigenvalue[4]; /* @eigenvalue or eigenvalue of seg0 (in dB) */
+
+	/* @DW6 : ofset 24 */
+	s8 rxsnr[4]; /* s(8,1) */
+};
+
+__PACK struct phy_status_rpt_jaguar3_type5 {
+/* @Debug */
+/* @DW0 ane DW1 : offset 0 and 4 */
+#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
+	u8 page_num : 4;
+	u8 pkt_cnt : 2;
+	u8 channel_msb : 2;
+#else
+	u8 channel_msb : 2;
+	u8 pkt_cnt : 2;
+	u8 page_num : 4;
+#endif
+	u8 pwdb[4];
+#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
+	u8 l_rxsc : 4;
+	u8 ht_rxsc : 4;
+#else
+	u8 ht_rxsc : 4;
+	u8 l_rxsc : 4;
+#endif
+	u8 channel_lsb;
+#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
+	u8 band : 2;
+	u8 rsvd_0 : 2;
+	u8 gnt_bt : 1;
+	u8 ldpc : 1;
+	u8 stbc : 1;
+	u8 beamformed : 1;
+#else
+	u8 beamformed : 1;
+	u8 stbc : 1;
+	u8 ldpc : 1;
+	u8 gnt_bt : 1;
+	u8 rsvd_0 : 2;
+	u8 band : 2;
+#endif
+	/* @DW2 : offset 8 */
+	u8 rsvd_1;
+#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
+	u8 rsvd_2 : 4;
+	u8 hw_antsw_occur_a : 1;
+	u8 hw_antsw_occur_b : 1;
+	u8 hw_antsw_occur_c : 1;
+	u8 hw_antsw_occur_d : 1;
+#else
+	u8 hw_antsw_occur_d : 1;
+	u8 hw_antsw_occur_c : 1;
+	u8 hw_antsw_occur_b : 1;
+	u8 hw_antsw_occur_a : 1;
+	u8 rsvd_2 : 4;
+#endif
+#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
+	u8 antidx_a : 4;
+	u8 antidx_b : 4;
+#else
+	u8 antidx_b : 4;
+	u8 antidx_a : 4;
+#endif
+#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
+	u8 antidx_c : 4;
+	u8 antidx_d : 4;
+#else
+	u8 antidx_d : 4;
+	u8 antidx_c : 4;
+#endif
+	/* @DW3 : offset 12 */
+	u8 tx_pkt_cnt;
+#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
+	u8 inf_pos_0_A_flg : 1;
+	u8 inf_pos_1_A_flg : 1;
+	u8 inf_pos_0_B_flg : 1;
+	u8 inf_pos_1_B_flg : 1;
+	u8 inf_pos_0_C_flg : 1;
+	u8 inf_pos_1_C_flg : 1;
+	u8 inf_pos_0_D_flg : 1;
+	u8 inf_pos_1_D_flg : 1;
+#else
+	u8 inf_pos_1_D_flg : 1;
+	u8 inf_pos_0_D_flg : 1;
+	u8 inf_pos_1_C_flg : 1;
+	u8 inf_pos_0_C_flg : 1;
+	u8 inf_pos_1_B_flg : 1;
+	u8 inf_pos_0_B_flg : 1;
+	u8 inf_pos_1_A_flg : 1;
+	u8 inf_pos_0_A_flg : 1;
+#endif
+	u8 rsvd_3;
+	u8 rsvd_4;
+	/* @DW4 : offset 16 */
+	u8 inf_pos_0_a;
+	u8 inf_pos_1_a;
+	u8 inf_pos_0_b;
+	u8 inf_pos_1_b;
+	/* @DW5 : offset 20 */
+	u8 inf_pos_0_c;
+	u8 inf_pos_1_c;
+	u8 inf_pos_0_d;
+	u8 inf_pos_1_d;
+};
+#endif /*@#ifdef PHYSTS_3RD_TYPE_SUPPORT*/
+
+#if (ODM_PHY_STATUS_NEW_TYPE_SUPPORT == 1)
+boolean
+phydm_query_is_mu_api(struct dm_struct *phydm, u8 ppdu_idx, u8 *p_data_rate,
+		      u8 *p_gid);
+#endif
+
+#ifdef PHYSTS_3RD_TYPE_SUPPORT
+void phydm_rx_physts_3rd_type(void *dm_void, u8 *phy_sts,
+			      struct phydm_perpkt_info_struct *pktinfo,
+			      struct phydm_phyinfo_struct *phy_info);
+#endif
+
+void phydm_reset_phystatus_avg(struct dm_struct *dm);
+
+void phydm_reset_phystatus_statistic(struct dm_struct *dm);
+
+void phydm_reset_rssi_for_dm(struct dm_struct *dm, u8 station_id);
+
+void phydm_get_cck_rssi_table_from_reg(struct dm_struct *dm);
+
+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
+void phydm_normal_driver_rx_sniffer(
+	struct dm_struct *dm,
+	u8 *desc,
+	PRT_RFD_STATUS rt_rfd_status,
+	u8 *drv_info,
+	u8 phy_status);
+#endif
+
+#if (DM_ODM_SUPPORT_TYPE == ODM_CE)
+s32 phydm_signal_scale_mapping(struct dm_struct *dm, s32 curr_sig);
+#endif
+
+void odm_phy_status_query(struct dm_struct *dm,
+			  struct phydm_phyinfo_struct *phy_info,
+			  u8 *phy_status_inf,
+			  struct phydm_perpkt_info_struct *pktinfo);
+
+void phydm_rx_phy_status_init(void *dm_void);
+
+#endif /*@#ifndef	__HALHWOUTSRC_H__*/
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/phydm_pmac_tx_setting.c linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/phydm_pmac_tx_setting.c
--- linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/phydm_pmac_tx_setting.c	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/phydm_pmac_tx_setting.c	2020-04-10 16:35:06.826660535 +0300
@@ -0,0 +1,522 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017  Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * The full GNU General Public License is included in this distribution in the
+ * file called LICENSE.
+ *
+ * Contact Information:
+ * wlanfae <wlanfae@realtek.com>
+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
+ * Hsinchu 300, Taiwan.
+ *
+ * Larry Finger <Larry.Finger@lwfinger.net>
+ *
+ *****************************************************************************/
+
+/*@************************************************************
+ * include files
+ ************************************************************/
+
+#include "mp_precomp.h"
+#include "phydm_precomp.h"
+
+#ifdef PHYDM_PMAC_TX_SETTING_SUPPORT
+#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
+
+void phydm_start_cck_cont_tx_jgr3(void *dm_void,
+				  struct phydm_pmac_info *tx_info)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct phydm_pmac_tx *pmac_tx = &dm->dm_pmac_tx_table;
+	u8 rate = tx_info->tx_rate; /* @HW rate */
+
+	/* @if CCK block on? */
+	if (!odm_get_bb_reg(dm, R_0x1c3c, BIT(1)))
+		odm_set_bb_reg(dm, R_0x1c3c, BIT(1), 1);
+
+	/* @Turn Off All Test mode */
+	odm_set_bb_reg(dm, R_0x1ca4, 0x7, 0x0);
+
+	odm_set_bb_reg(dm, R_0x1a00, 0x3000, rate);
+	odm_set_bb_reg(dm, R_0x1a00, 0x3, 0x2); /* @transmit mode */
+	odm_set_bb_reg(dm, R_0x1a00, 0x8, 0x1); /* @turn on scramble setting */
+
+	/* @Fix rate selection issue */
+	odm_set_bb_reg(dm, R_0x1a70, 0x4000, 0x1);
+	/* @set RX weighting for path I & Q to 0 */
+	odm_set_bb_reg(dm, R_0x1a14, 0x300, 0x3);
+	/* @set loopback mode */
+	odm_set_bb_reg(dm, R_0x1c3c, 0x10, 0x1);
+
+	pmac_tx->cck_cont_tx = true;
+	pmac_tx->ofdm_cont_tx = false;
+}
+
+void phydm_stop_cck_cont_tx_jgr3(void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct phydm_pmac_tx *pmac_tx = &dm->dm_pmac_tx_table;
+
+	pmac_tx->cck_cont_tx = false;
+	pmac_tx->ofdm_cont_tx = false;
+
+	odm_set_bb_reg(dm, R_0x1a00, 0x3, 0x0); /* @normal mode */
+	odm_set_bb_reg(dm, R_0x1a00, 0x8, 0x1); /* @turn on scramble setting */
+
+	/* @back to default */
+	odm_set_bb_reg(dm, R_0x1a70, 0x4000, 0x0);
+	odm_set_bb_reg(dm, R_0x1a14, 0x300, 0x0);
+	odm_set_bb_reg(dm, R_0x1c3c, 0x10, 0x0);
+	/* @BB Reset */
+	odm_set_bb_reg(dm, R_0x1d0c, 0x10000, 0x0);
+	odm_set_bb_reg(dm, R_0x1d0c, 0x10000, 0x1);
+}
+
+void phydm_start_ofdm_cont_tx_jgr3(void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct phydm_pmac_tx *pmac_tx = &dm->dm_pmac_tx_table;
+
+	/* @1. if OFDM block on */
+	if (!odm_get_bb_reg(dm, R_0x1c3c, BIT(0)))
+		odm_set_bb_reg(dm, R_0x1c3c, BIT(0), 1);
+
+	/* @2. set CCK test mode off, set to CCK normal mode */
+	odm_set_bb_reg(dm, R_0x1a00, 0x3, 0);
+
+	/* @3. turn on scramble setting */
+	odm_set_bb_reg(dm, R_0x1a00, 0x8, 1);
+
+	/* @4. Turn On Continue Tx and turn off the other test modes. */
+	odm_set_bb_reg(dm, R_0x1ca4, 0x7, 0x1);
+
+	pmac_tx->cck_cont_tx = false;
+	pmac_tx->ofdm_cont_tx = true;
+}
+
+void phydm_stop_ofdm_cont_tx_jgr3(void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct phydm_pmac_tx *pmac_tx = &dm->dm_pmac_tx_table;
+
+	pmac_tx->cck_cont_tx = false;
+	pmac_tx->ofdm_cont_tx = false;
+
+	/* @Turn Off All Test mode */
+	odm_set_bb_reg(dm, R_0x1ca4, 0x7, 0x0);
+
+	/* @Delay 10 ms */
+	ODM_delay_ms(10);
+
+	/* @BB Reset */
+	odm_set_bb_reg(dm, R_0x1d0c, 0x10000, 0x0);
+	odm_set_bb_reg(dm, R_0x1d0c, 0x10000, 0x1);
+}
+
+void phydm_set_single_tone_jgr3(void *dm_void, boolean is_single_tone,
+				boolean en_pmac_tx, u8 path)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct phydm_pmac_tx *pmac_tx = &dm->dm_pmac_tx_table;
+	u8 start = RF_PATH_A, end = RF_PATH_A;
+
+	switch (path) {
+	case RF_PATH_A:
+	case RF_PATH_B:
+	case RF_PATH_C:
+	case RF_PATH_D:
+		start = path;
+		end = path;
+		break;
+	case RF_PATH_AB:
+		start = RF_PATH_A;
+		end = RF_PATH_B;
+		break;
+	case RF_PATH_BC:
+		start = RF_PATH_B;
+		end = RF_PATH_C;
+		break;
+	case RF_PATH_ABC:
+		start = RF_PATH_A;
+		end = RF_PATH_C;
+		break;
+	case RF_PATH_BCD:
+		start = RF_PATH_B;
+		end = RF_PATH_D;
+		break;
+	case RF_PATH_ABCD:
+		start = RF_PATH_A;
+		end = RF_PATH_D;
+		break;
+	}
+
+	if (is_single_tone) {
+		pmac_tx->tx_scailing = odm_get_bb_reg(dm, R_0x81c, MASKDWORD);
+
+		if (!en_pmac_tx) {
+			phydm_start_ofdm_cont_tx_jgr3(dm);
+			/*SendPSPoll(pAdapter);*/
+		}
+
+		odm_set_bb_reg(dm, R_0x1c68, BIT(24), 0x1); /* @Disable CCA */
+
+		if (!(dm->support_ic_type & ODM_RTL8814B)) {
+			for (start; start <= end; start++) {
+				/* @Tx mode: RF0x00[19:16]=4'b0010 */
+				odm_set_rf_reg(dm, start, RF_0x0, 0xF0000, 0x2);
+				/* @Lowest RF gain index: RF_0x0[4:0] = 0*/
+				odm_set_rf_reg(dm, start, RF_0x0, 0x1F, 0x0);
+				/* @RF LO enabled */
+				odm_set_rf_reg(dm, start, RF_0x58, BIT(1), 0x1);
+			}
+		}
+		odm_set_bb_reg(dm, R_0x81c, 0x001FC000, 0);
+	} else {
+		for (start; start <= end; start++)
+			/* @RF LO disabled */
+			if (!(dm->support_ic_type & ODM_RTL8814B))
+				odm_set_rf_reg(dm, start, RF_0x58, BIT(1), 0x0);
+
+		odm_set_bb_reg(dm, R_0x1c68, BIT(24), 0x0); /* @Enable CCA */
+
+		if (!en_pmac_tx)
+			phydm_stop_ofdm_cont_tx_jgr3(dm);
+
+		odm_set_bb_reg(dm, R_0x81c, MASKDWORD, pmac_tx->tx_scailing);
+	}
+}
+
+void phydm_stop_pmac_tx_jgr3(void *dm_void, struct phydm_pmac_info *tx_info)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct phydm_pmac_tx *pmac_tx = &dm->dm_pmac_tx_table;
+	u32 tmp = 0;
+
+	if (tx_info->mode == CONT_TX) {
+		odm_set_bb_reg(dm, R_0x1e70, 0xf, 2); /* TX Stop */
+		if (pmac_tx->is_cck_rate)
+			phydm_stop_cck_cont_tx_jgr3(dm);
+		else
+			phydm_stop_ofdm_cont_tx_jgr3(dm);
+	} else {
+		if (pmac_tx->is_cck_rate) {
+			tmp = odm_get_bb_reg(dm, R_0x2de4, MASKLWORD);
+			odm_set_bb_reg(dm, R_0x1e64, MASKLWORD, tmp + 50);
+		}
+		odm_set_bb_reg(dm, R_0x1e70, 0xf, 2); /* TX Stop */
+	}
+
+	if (tx_info->mode == OFDM_SINGLE_TONE_TX) {
+		/* Stop HW TX -> Stop Continuous TX -> Stop RF Setting */
+		if (pmac_tx->is_cck_rate)
+			phydm_stop_cck_cont_tx_jgr3(dm);
+		else
+			phydm_stop_ofdm_cont_tx_jgr3(dm);
+
+		phydm_set_single_tone_jgr3(dm, false, true, pmac_tx->path);
+	}
+}
+
+void phydm_set_mac_phy_txinfo_jgr3(void *dm_void,
+				   struct phydm_pmac_info *tx_info)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct phydm_pmac_tx *pmac_tx = &dm->dm_pmac_tx_table;
+	u32 tmp = 0;
+
+	odm_set_bb_reg(dm, R_0xa58, 0x003F8000, tx_info->tx_rate);
+
+	/* @0x900[1] ndp_sound */
+	odm_set_bb_reg(dm, R_0x900, 0x2, tx_info->ndp_sound);
+	/* @0x900[27:24] txsc [29:28] bw [31:30] m_stbc */
+	tmp = (tx_info->tx_sc) | ((tx_info->bw) << 4) |
+	      ((tx_info->m_stbc - 1) << 6);
+	odm_set_bb_reg(dm, R_0x900, 0xFF000000, tmp);
+
+	if (pmac_tx->is_ofdm_rate) {
+		odm_set_bb_reg(dm, R_0x900, 0x1, 0);
+		odm_set_bb_reg(dm, R_0x900, 0x4, 0);
+	} else if (pmac_tx->is_ht_rate) {
+		odm_set_bb_reg(dm, R_0x900, 0x1, 1);
+		odm_set_bb_reg(dm, R_0x900, 0x4, 0);
+	} else if (pmac_tx->is_vht_rate) {
+		odm_set_bb_reg(dm, R_0x900, 0x1, 0);
+		odm_set_bb_reg(dm, R_0x900, 0x4, 1);
+	}
+
+	tmp = tx_info->packet_period; /* @for TX interval */
+	odm_set_bb_reg(dm, R_0x9b8, 0xffff0000, tmp);
+}
+
+void phydm_set_mac_hdr_jgr3(void *dm_void, struct phydm_pmac_info *tx_info)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct phydm_pmac_tx *pmac_tx = &dm->dm_pmac_tx_table;
+	u32 tmp = 0;
+	u32 tmp1 = 0;
+
+	if (pmac_tx->is_vht_rate) {
+		tmp = BYTE_2_DWORD(tx_info->vht_delimiter[3],
+				   tx_info->vht_delimiter[2],
+				   tx_info->vht_delimiter[1],
+				   tx_info->vht_delimiter[0]);
+		odm_set_bb_reg(dm, R_0x950, MASKDWORD, tmp);
+
+		/* 0x954 - 0x960 24 byte Probe Request MAC Header */
+		/* & Duration & Frame control */
+		odm_set_bb_reg(dm, R_0x954, MASKDWORD, 0x00000040);
+
+		/* MAC_Addr1[5:0] , the value has no meaning */
+		tmp = BYTE_2_DWORD(0x33, 0x22, 0x11, 0x00);
+		tmp1 = BYTE_2_DWORD(0, 0, 0x55, 0x44);
+		odm_set_bb_reg(dm, R_0x958, MASKDWORD, tmp);
+		odm_set_bb_reg(dm, R_0x95c, 0xffff, tmp1);
+
+		/* MAC_Addr3[3:0], [5:4] drop for DD design*/
+		odm_set_bb_reg(dm, R_0x964, MASKDWORD, tmp);
+
+		/* MAC_Addr2[5:0] */
+		tmp = BYTE_2_DWORD(0, 0, 0x11, 0x00);
+		tmp1 = BYTE_2_DWORD(0x55, 0x44, 0x33, 0x22);
+		odm_set_bb_reg(dm, R_0x95c, 0xffff0000, tmp);
+		odm_set_bb_reg(dm, R_0x960, MASKDWORD, tmp1);
+
+	} else {
+		/* 0x950 - 0x964 24 byte Probe Request MAC Header */
+		/* & Duration & Frame control */
+		odm_set_bb_reg(dm, R_0x950, MASKDWORD, 0x00000040);
+
+		/* MAC_Addr1[5:0] , the value has no meaning */
+		tmp = BYTE_2_DWORD(0x33, 0x22, 0x11, 0x00);
+		tmp1 = BYTE_2_DWORD(0, 0, 0x55, 0x44);
+		odm_set_bb_reg(dm, R_0x954, MASKDWORD, tmp);
+		odm_set_bb_reg(dm, R_0x958, 0xffff, tmp1);
+
+		/* Sequence Control & Address3[5:0] */
+		odm_set_bb_reg(dm, R_0x960, MASKDWORD, tmp);
+		odm_set_bb_reg(dm, R_0x964, MASKDWORD, tmp1);
+
+		/* MAC_Addr2[5:0] */
+		tmp = BYTE_2_DWORD(0, 0, 0x11, 0x00);
+		tmp1 = BYTE_2_DWORD(0x55, 0x44, 0x33, 0x22);
+		odm_set_bb_reg(dm, R_0x958, 0xffff0000, tmp);
+		odm_set_bb_reg(dm, R_0x95c, MASKDWORD, tmp1);
+	}
+}
+
+void phydm_set_sig_jgr3(void *dm_void, struct phydm_pmac_info *tx_info)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct phydm_pmac_tx *pmac_tx = &dm->dm_pmac_tx_table;
+	u32 tmp = 0;
+
+	if (pmac_tx->is_cck_rate)
+		return;
+
+	/* @L-SIG */
+	odm_set_bb_reg(dm, R_0x1eb4, 0xfffff, tx_info->packet_count);
+
+	tmp = BYTE_2_DWORD(0, tx_info->lsig[2], tx_info->lsig[1],
+			   tx_info->lsig[0]);
+	odm_set_bb_reg(dm, R_0x908, 0xffffff, tmp);
+
+	/* @0x924[7:0] = Data init octet */
+	tmp = tx_info->packet_pattern;
+	odm_set_bb_reg(dm, R_0x924, 0xff, tmp);
+
+	if (tx_info->packet_pattern == RANDOM_BY_PN32)
+		tmp = 0x3;
+	else
+		tmp = 0;
+
+	odm_set_bb_reg(dm, R_0x914, 0xE0000000, tmp);
+
+	if (pmac_tx->is_ht_rate) {
+	/* @HT SIG */
+		tmp = BYTE_2_DWORD(0, tx_info->ht_sig[2], tx_info->ht_sig[1],
+				   tx_info->ht_sig[0]);
+		odm_set_bb_reg(dm, 0x90c, 0xffffff, tmp);
+		tmp = BYTE_2_DWORD(0, tx_info->ht_sig[5], tx_info->ht_sig[4],
+				   tx_info->ht_sig[3]);
+		odm_set_bb_reg(dm, 0x910, 0xffffff, tmp);
+	} else if (pmac_tx->is_vht_rate) {
+	/* @VHT SIG A/B/serv_field */
+		tmp = BYTE_2_DWORD(0, tx_info->vht_sig_a[2],
+				   tx_info->vht_sig_a[1],
+				   tx_info->vht_sig_a[0]);
+		odm_set_bb_reg(dm, 0x90c, 0xffffff, tmp);
+		tmp = BYTE_2_DWORD(0, tx_info->vht_sig_a[5],
+				   tx_info->vht_sig_a[4],
+				   tx_info->vht_sig_a[3]);
+		odm_set_bb_reg(dm, 0x910, 0xffffff, tmp);
+		tmp = BYTE_2_DWORD(tx_info->vht_sig_b[3], tx_info->vht_sig_b[2],
+				   tx_info->vht_sig_b[1],
+				   tx_info->vht_sig_b[0]);
+		odm_set_bb_reg(dm, 0x914, 0x1FFFFFFF, tmp);
+
+		tmp = tx_info->vht_sig_b_crc << 8;
+		odm_set_bb_reg(dm, R_0x938, 0xffff, tmp);
+	}
+}
+
+void phydm_set_cck_preamble_hdr_jgr3(void *dm_void,
+				     struct phydm_pmac_info *tx_info)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct phydm_pmac_tx *pmac_tx = &dm->dm_pmac_tx_table;
+	u32 tmp = 0;
+
+	if (!pmac_tx->is_cck_rate)
+		return;
+
+	tmp = tx_info->packet_count | (tx_info->sfd << 16);
+	odm_set_bb_reg(dm, R_0x1e64, MASKDWORD, tmp);
+	tmp = tx_info->signal_field | (tx_info->service_field << 8) |
+	      (tx_info->length << 16);
+	odm_set_bb_reg(dm, R_0x1e68, MASKDWORD, tmp);
+	tmp = BYTE_2_DWORD(0, 0, tx_info->crc16[1], tx_info->crc16[0]);
+	odm_set_bb_reg(dm, R_0x1e6c, 0xffff, tmp);
+
+	if (tx_info->is_short_preamble)
+		odm_set_bb_reg(dm, R_0x1e6c, BIT(16), 0);
+	else
+		odm_set_bb_reg(dm, R_0x1e6c, BIT(16), 1);
+}
+
+void phydm_set_mode_jgr3(void *dm_void, struct phydm_pmac_info *tx_info,
+			 enum phydm_pmac_mode mode)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct phydm_pmac_tx *pmac_tx = &dm->dm_pmac_tx_table;
+
+	if (mode == CONT_TX) {
+		tx_info->packet_count = 1;
+
+		if (pmac_tx->is_cck_rate)
+			phydm_start_cck_cont_tx_jgr3(dm, tx_info);
+		else
+			phydm_start_ofdm_cont_tx_jgr3(dm);
+	} else if (mode == OFDM_SINGLE_TONE_TX) {
+		/* Continuous TX -> HW TX -> RF Setting */
+		tx_info->packet_count = 1;
+
+		if (pmac_tx->is_cck_rate)
+			phydm_start_cck_cont_tx_jgr3(dm, tx_info);
+		else
+			phydm_start_ofdm_cont_tx_jgr3(dm);
+	} else if (mode == PKTS_TX) {
+		if (pmac_tx->is_cck_rate && tx_info->packet_count == 0)
+			tx_info->packet_count = 0xffff;
+	}
+}
+
+void phydm_set_pmac_txon_jgr3(void *dm_void, struct phydm_pmac_info *tx_info)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct phydm_pmac_tx *pmac_tx = &dm->dm_pmac_tx_table;
+
+	odm_set_bb_reg(dm, R_0x1d08, BIT(0), 1); /* Turn on PMAC */
+
+	if (pmac_tx->is_cck_rate) {
+		odm_set_bb_reg(dm, R_0x1e70, 0xf, 8); /* TX CCK ON */
+		odm_set_bb_reg(dm, R_0x1a84, BIT(31), 0);
+	} else {
+		odm_set_bb_reg(dm, R_0x1e70, 0xf, 4); /* TX Ofdm ON */
+	}
+
+	if (tx_info->mode == OFDM_SINGLE_TONE_TX)
+		phydm_set_single_tone_jgr3(dm, true, true, pmac_tx->path);
+}
+
+void phydm_set_pmac_tx_jgr3(void *dm_void, struct phydm_pmac_info *tx_info,
+			    enum rf_path mpt_rf_path)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct phydm_pmac_tx *pmac_tx = &dm->dm_pmac_tx_table;
+
+	pmac_tx->is_cck_rate = phydm_is_cck_rate(dm, tx_info->tx_rate);
+	pmac_tx->is_ofdm_rate = phydm_is_ofdm_rate(dm, tx_info->tx_rate);
+	pmac_tx->is_ht_rate = phydm_is_ht_rate(dm, tx_info->tx_rate);
+	pmac_tx->is_vht_rate = phydm_is_vht_rate(dm, tx_info->tx_rate);
+	pmac_tx->path = mpt_rf_path;
+
+	if (!tx_info->en_pmac_tx) {
+		phydm_stop_pmac_tx_jgr3(dm, tx_info);
+		return;
+	}
+
+	phydm_set_mode_jgr3(dm, tx_info, tx_info->mode);
+
+	if (pmac_tx->is_cck_rate)
+		phydm_set_cck_preamble_hdr_jgr3(dm, tx_info);
+	else
+		phydm_set_sig_jgr3(dm, tx_info);
+
+	phydm_set_mac_phy_txinfo_jgr3(dm, tx_info);
+	phydm_set_mac_hdr_jgr3(dm, tx_info);
+	phydm_set_pmac_txon_jgr3(dm, tx_info);
+}
+#endif
+
+void phydm_start_cck_cont_tx(void *dm_void, struct phydm_pmac_info *tx_info)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+
+	if (dm->support_ic_type & ODM_IC_JGR3_SERIES)
+		phydm_start_cck_cont_tx_jgr3(dm, tx_info);
+}
+
+void phydm_stop_cck_cont_tx(void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+
+	if (dm->support_ic_type & ODM_IC_JGR3_SERIES)
+		phydm_stop_cck_cont_tx_jgr3(dm);
+}
+
+void phydm_start_ofdm_cont_tx(void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+
+	if (dm->support_ic_type & ODM_IC_JGR3_SERIES)
+		phydm_start_ofdm_cont_tx_jgr3(dm);
+}
+
+void phydm_stop_ofdm_cont_tx(void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+
+	if (dm->support_ic_type & ODM_IC_JGR3_SERIES)
+		phydm_stop_ofdm_cont_tx_jgr3(dm);
+}
+
+void phydm_set_single_tone(void *dm_void, boolean is_single_tone,
+			   boolean en_pmac_tx, u8 path)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+
+	if (dm->support_ic_type & ODM_IC_JGR3_SERIES)
+		phydm_set_single_tone_jgr3(dm, is_single_tone,
+					   en_pmac_tx, path);
+}
+
+void phydm_set_pmac_tx(void *dm_void, struct phydm_pmac_info *tx_info,
+		       enum rf_path mpt_rf_path)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+
+	if (dm->support_ic_type & ODM_IC_JGR3_SERIES)
+		phydm_set_pmac_tx_jgr3(dm, tx_info, mpt_rf_path);
+}
+
+#endif
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/phydm_pmac_tx_setting.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/phydm_pmac_tx_setting.h
--- linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/phydm_pmac_tx_setting.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/phydm_pmac_tx_setting.h	2020-04-10 16:35:06.826660535 +0300
@@ -0,0 +1,149 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017  Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * The full GNU General Public License is included in this distribution in the
+ * file called LICENSE.
+ *
+ * Contact Information:
+ * wlanfae <wlanfae@realtek.com>
+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
+ * Hsinchu 300, Taiwan.
+ *
+ * Larry Finger <Larry.Finger@lwfinger.net>
+ *
+ *****************************************************************************/
+
+#ifndef __PHYDM_PMAC_TX_SETTING_H__
+#define __PHYDM_PMAC_TX_SETTING_H__
+
+#define PMAC_TX_SETTING_VERSION "1.0"
+
+/* @1 ============================================================
+ * 1  Definition
+ * 1 ============================================================
+ */
+#define RANDOM_BY_PN32 0x12
+/* @1 ============================================================
+ * 1  structure
+ * 1 ============================================================
+ */
+struct phydm_pmac_info {
+	u8 en_pmac_tx:1; /*@ disable pmac 1: enable pmac */
+	u8 mode:3; /*@ 0: Packet TX 3:Continuous TX */
+	/* @u8 Ntx:4; */
+	u8 tx_rate; /* @should be HW rate*/
+	/* @u8 TX_RATE_HEX; */
+	u8 tx_sc;
+	/* @u8 bSGI:1; */
+	u8 is_short_preamble:1;
+	/* @u8 bSTBC:1; */
+	/* @u8 bLDPC:1; */
+	u8 ndp_sound:1;
+	u8 bw:3; /* @0:20 1:40 2:80Mhz */
+	u8 m_stbc; /* @bSTBC + 1 */
+	u16 packet_period;
+	u32 packet_count;
+	/* @u32 PacketLength; */
+	u8 packet_pattern;
+	u16 sfd;
+	u8 signal_field;
+	u8 service_field;
+	u16 length;
+	u8 crc16[2];
+	u8 lsig[3];
+	u8 ht_sig[6];
+	u8 vht_sig_a[6];
+	u8 vht_sig_b[4];
+	u8 vht_sig_b_crc;
+	u8 vht_delimiter[4];
+	/* @u8 mac_addr[6]; */
+};
+
+struct phydm_pmac_tx {
+	boolean is_cck_rate;
+	boolean is_ofdm_rate;
+	boolean is_ht_rate;
+	boolean is_vht_rate;
+	boolean cck_cont_tx;
+	boolean ofdm_cont_tx;
+	u8 path;
+	u32 tx_scailing;
+};
+
+/* @1 ============================================================
+ * 1  enumeration
+ * 1 ============================================================
+ */
+
+enum phydm_pmac_mode {
+	NONE_TEST,
+	PKTS_TX,
+	PKTS_RX,
+	CONT_TX,
+	OFDM_SINGLE_TONE_TX,
+	CCK_CARRIER_SIPPRESSION_TX
+};
+
+/* @1 ============================================================
+ * 1  function prototype
+ * 1 ============================================================
+ */
+#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
+void phydm_start_cck_cont_tx_jgr3(void *dm_void,
+				  struct phydm_pmac_info *tx_info);
+
+void phydm_stop_cck_cont_tx_jgr3(void *dm_void);
+
+void phydm_start_ofdm_cont_tx_jgr3(void *dm_void);
+
+void phydm_stop_ofdm_cont_tx_jgr3(void *dm_void);
+
+void phydm_set_single_tone_jgr3(void *dm_void, boolean is_single_tone,
+				boolean en_pmac_tx, u8 path);
+
+void phydm_stop_pmac_tx_jgr3(void *dm_void, struct phydm_pmac_info *tx_info);
+
+void phydm_set_mac_phy_txinfo_jgr3(void *dm_void,
+				   struct phydm_pmac_info *tx_info);
+
+void phydm_set_mac_hdr_jgr3(void *dm_void, struct phydm_pmac_info *tx_info);
+
+void phydm_set_sig_jgr3(void *dm_void, struct phydm_pmac_info *tx_info);
+
+void phydm_set_cck_preamble_hdr_jgr3(void *dm_void,
+				     struct phydm_pmac_info *tx_info);
+
+void phydm_set_mode_jgr3(void *dm_void, struct phydm_pmac_info *tx_info,
+			 enum phydm_pmac_mode mode);
+
+void phydm_set_pmac_txon_jgr3(void *dm_void, struct phydm_pmac_info *tx_info);
+
+void phydm_set_pmac_tx_jgr3(void *dm_void, struct phydm_pmac_info *tx_info,
+			    enum rf_path mpt_rf_path);
+#endif
+
+void phydm_start_cck_cont_tx(void *dm_void, struct phydm_pmac_info *tx_info);
+
+void phydm_stop_cck_cont_tx(void *dm_void);
+
+void phydm_start_ofdm_cont_tx(void *dm_void);
+
+void phydm_stop_ofdm_cont_tx(void *dm_void);
+
+void phydm_set_single_tone(void *dm_void, boolean is_single_tone,
+			   boolean en_pmac_tx, u8 path);
+
+void phydm_set_pmac_tx(void *dm_void, struct phydm_pmac_info *tx_info,
+		       enum rf_path mpt_rf_path);
+
+#endif
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/phydm_powertracking_ap.c linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/phydm_powertracking_ap.c
--- linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/phydm_powertracking_ap.c	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/phydm_powertracking_ap.c	2020-04-10 16:35:06.826660535 +0300
@@ -0,0 +1,1249 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
+ *
+ *
+ ******************************************************************************/
+
+/* ************************************************************
+ * include files
+ * ************************************************************ */
+#include "mp_precomp.h"
+#include "phydm_precomp.h"
+
+#if !defined(_OUTSRC_COEXIST)
+/* ************************************************************
+ * Global var
+ * ************************************************************ */
+
+
+u32 ofdm_swing_table_new[OFDM_TABLE_SIZE_92D] = {
+	0x0b40002d, /* 0,  -15.0dB */
+	0x0c000030, /* 1,  -14.5dB */
+	0x0cc00033, /* 2,  -14.0dB */
+	0x0d800036, /* 3,  -13.5dB */
+	0x0e400039, /* 4,  -13.0dB */
+	0x0f00003c, /* 5,  -12.5dB */
+	0x10000040, /* 6,  -12.0dB */
+	0x11000044, /* 7,  -11.5dB */
+	0x12000048, /* 8,  -11.0dB */
+	0x1300004c, /* 9,  -10.5dB */
+	0x14400051, /* 10, -10.0dB */
+	0x15800056, /* 11, -9.5dB */
+	0x16c0005b, /* 12, -9.0dB */
+	0x18000060, /* 13, -8.5dB */
+	0x19800066, /* 14, -8.0dB */
+	0x1b00006c, /* 15, -7.5dB */
+	0x1c800072, /* 16, -7.0dB */
+	0x1e400079, /* 17, -6.5dB */
+	0x20000080, /* 18, -6.0dB */
+	0x22000088, /* 19, -5.5dB */
+	0x24000090, /* 20, -5.0dB */
+	0x26000098, /* 21, -4.5dB */
+	0x288000a2, /* 22, -4.0dB */
+	0x2ac000ab, /* 23, -3.5dB */
+	0x2d4000b5, /* 24, -3.0dB */
+	0x300000c0, /* 25, -2.5dB */
+	0x32c000cb, /* 26, -2.0dB */
+	0x35c000d7, /* 27, -1.5dB */
+	0x390000e4, /* 28, -1.0dB */
+	0x3c8000f2, /* 29, -0.5dB */
+	0x40000100, /* 30, +0dB */
+	0x43c0010f, /* 31, +0.5dB */
+	0x47c0011f, /* 32, +1.0dB */
+	0x4c000130, /* 33, +1.5dB */
+	0x50800142, /* 34, +2.0dB */
+	0x55400155, /* 35, +2.5dB */
+	0x5a400169, /* 36, +3.0dB */
+	0x5fc0017f, /* 37, +3.5dB */
+	0x65400195, /* 38, +4.0dB */
+	0x6b8001ae, /* 39, +4.5dB */
+	0x71c001c7, /* 40, +5.0dB */
+	0x788001e2, /* 41, +5.5dB */
+	0x7f8001fe  /* 42, +6.0dB */
+};
+
+u8 cck_swing_table_ch1_ch13_new[CCK_TABLE_SIZE][8] = {
+	{0x09, 0x08, 0x07, 0x06, 0x04, 0x03, 0x01, 0x01},	/* 0, -16.0dB */
+	{0x09, 0x09, 0x08, 0x06, 0x05, 0x03, 0x01, 0x01},	/* 1, -15.5dB */
+	{0x0a, 0x09, 0x08, 0x07, 0x05, 0x03, 0x02, 0x01},	/* 2, -15.0dB */
+	{0x0a, 0x0a, 0x09, 0x07, 0x05, 0x03, 0x02, 0x01},	/* 3, -14.5dB */
+	{0x0b, 0x0a, 0x09, 0x08, 0x06, 0x04, 0x02, 0x01},	/* 4, -14.0dB */
+	{0x0b, 0x0b, 0x0a, 0x08, 0x06, 0x04, 0x02, 0x01},	/* 5, -13.5dB */
+	{0x0c, 0x0c, 0x0a, 0x09, 0x06, 0x04, 0x02, 0x01},	/* 6, -13.0dB */
+	{0x0d, 0x0c, 0x0b, 0x09, 0x07, 0x04, 0x02, 0x01},	/* 7, -12.5dB */
+	{0x0d, 0x0d, 0x0c, 0x0a, 0x07, 0x05, 0x02, 0x01},	/* 8, -12.0dB */
+	{0x0e, 0x0e, 0x0c, 0x0a, 0x08, 0x05, 0x02, 0x01},	/* 9, -11.5dB */
+	{0x0f, 0x0f, 0x0d, 0x0b, 0x08, 0x05, 0x03, 0x01},	/* 10, -11.0dB */
+	{0x10, 0x10, 0x0e, 0x0b, 0x08, 0x05, 0x03, 0x01},	/* 11, -10.5dB */
+	{0x11, 0x11, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01},	/* 12, -10.0dB */
+	{0x12, 0x12, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01},	/* 13, -9.5dB */
+	{0x13, 0x13, 0x10, 0x0d, 0x0a, 0x06, 0x03, 0x01},	/* 14, -9.0dB */
+	{0x14, 0x14, 0x11, 0x0e, 0x0b, 0x07, 0x03, 0x02},	/* 15, -8.5dB */
+	{0x16, 0x15, 0x12, 0x0f, 0x0b, 0x07, 0x04, 0x01},	/* 16, -8.0dB */
+	{0x17, 0x16, 0x13, 0x10, 0x0c, 0x08, 0x04, 0x02},	/* 17, -7.5dB */
+	{0x18, 0x17, 0x15, 0x11, 0x0c, 0x08, 0x04, 0x02},	/* 18, -7.0dB */
+	{0x1a, 0x19, 0x16, 0x12, 0x0d, 0x09, 0x04, 0x02},	/* 19, -6.5dB */
+	{0x1c, 0x1a, 0x18, 0x12, 0x0e, 0x08, 0x04, 0x02},	/* 20, -6.0dB */
+	{0x1d, 0x1c, 0x18, 0x14, 0x0f, 0x0a, 0x05, 0x02},	/* 21, -5.5dB */
+	{0x1f, 0x1e, 0x1a, 0x15, 0x10, 0x0a, 0x05, 0x02},	/* 22, -5.0dB */
+	{0x20, 0x20, 0x1b, 0x16, 0x11, 0x08, 0x05, 0x02},	/* 23, -4.5dB */
+	{0x22, 0x21, 0x1d, 0x18, 0x11, 0x0b, 0x06, 0x02},	/* 24, -4.0dB */
+	{0x24, 0x23, 0x1f, 0x19, 0x13, 0x0c, 0x06, 0x03},	/* 25, -3.5dB */
+	{0x26, 0x25, 0x21, 0x1b, 0x14, 0x0d, 0x06, 0x03},	/* 26, -3.0dB */
+	{0x28, 0x28, 0x22, 0x1c, 0x15, 0x0d, 0x07, 0x03},	/* 27, -2.5dB */
+	{0x2b, 0x2a, 0x25, 0x1e, 0x16, 0x0e, 0x07, 0x03},	/* 28, -2.0dB */
+	{0x2d, 0x2d, 0x27, 0x1f, 0x18, 0x0f, 0x08, 0x03},	/* 29, -1.5dB */
+	{0x30, 0x2f, 0x29, 0x21, 0x19, 0x10, 0x08, 0x03},	/* 30, -1.0dB */
+	{0x33, 0x32, 0x2b, 0x23, 0x1a, 0x11, 0x08, 0x04},	/* 31, -0.5dB */
+	{0x36, 0x35, 0x2e, 0x25, 0x1c, 0x12, 0x09, 0x04}	/* 32, +0dB */
+};
+
+
+u8 cck_swing_table_ch14_new[CCK_TABLE_SIZE][8] = {
+	{0x09, 0x08, 0x07, 0x04, 0x00, 0x00, 0x00, 0x00},	/* 0, -16.0dB */
+	{0x09, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00},	/* 1, -15.5dB */
+	{0x0a, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00},	/* 2, -15.0dB */
+	{0x0a, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00},	/* 3, -14.5dB */
+	{0x0b, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00},	/* 4, -14.0dB */
+	{0x0b, 0x0b, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00},	/* 5, -13.5dB */
+	{0x0c, 0x0c, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00},	/* 6, -13.0dB */
+	{0x0d, 0x0c, 0x0b, 0x06, 0x00, 0x00, 0x00, 0x00},	/* 7, -12.5dB */
+	{0x0d, 0x0d, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00},	/* 8, -12.0dB */
+	{0x0e, 0x0e, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00},	/* 9, -11.5dB */
+	{0x0f, 0x0f, 0x0d, 0x08, 0x00, 0x00, 0x00, 0x00},	/* 10, -11.0dB */
+	{0x10, 0x10, 0x0e, 0x08, 0x00, 0x00, 0x00, 0x00},	/* 11, -10.5dB */
+	{0x11, 0x11, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00},	/* 12, -10.0dB */
+	{0x12, 0x12, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00},	/* 13, -9.5dB */
+	{0x13, 0x13, 0x10, 0x0a, 0x00, 0x00, 0x00, 0x00},	/* 14, -9.0dB */
+	{0x14, 0x14, 0x11, 0x0a, 0x00, 0x00, 0x00, 0x00},	/* 15, -8.5dB */
+	{0x16, 0x15, 0x12, 0x0b, 0x00, 0x00, 0x00, 0x00},	/* 16, -8.0dB */
+	{0x17, 0x16, 0x13, 0x0b, 0x00, 0x00, 0x00, 0x00},	/* 17, -7.5dB */
+	{0x18, 0x17, 0x15, 0x0c, 0x00, 0x00, 0x00, 0x00},	/* 18, -7.0dB */
+	{0x1a, 0x19, 0x16, 0x0d, 0x00, 0x00, 0x00, 0x00},	/* 19, -6.5dB */
+	{0x1c, 0x1a, 0x18, 0x0e, 0x00, 0x00, 0x00, 0x00},	/* 20, -6.0dB */
+	{0x1d, 0x1c, 0x18, 0x0e, 0x00, 0x00, 0x00, 0x00},	/* 21, -5.5dB */
+	{0x1f, 0x1e, 0x1a, 0x0f, 0x00, 0x00, 0x00, 0x00},	/* 22, -5.0dB */
+	{0x20, 0x20, 0x1b, 0x10, 0x00, 0x00, 0x00, 0x00},	/* 23, -4.5dB */
+	{0x22, 0x21, 0x1d, 0x11, 0x00, 0x00, 0x00, 0x00},	/* 24, -4.0dB */
+	{0x24, 0x23, 0x1f, 0x12, 0x00, 0x00, 0x00, 0x00},	/* 25, -3.5dB */
+	{0x26, 0x25, 0x21, 0x13, 0x00, 0x00, 0x00, 0x00},	/* 26, -3.0dB */
+	{0x28, 0x28, 0x24, 0x14, 0x00, 0x00, 0x00, 0x00},	/* 27, -2.5dB */
+	{0x2b, 0x2a, 0x25, 0x15, 0x00, 0x00, 0x00, 0x00},	/* 28, -2.0dB */
+	{0x2d, 0x2d, 0x17, 0x17, 0x00, 0x00, 0x00, 0x00},	/* 29, -1.5dB */
+	{0x30, 0x2f, 0x29, 0x18, 0x00, 0x00, 0x00, 0x00},	/* 30, -1.0dB */
+	{0x33, 0x32, 0x2b, 0x19, 0x00, 0x00, 0x00, 0x00},	/* 31, -0.5dB */
+	{0x36, 0x35, 0x2e, 0x1b, 0x00, 0x00, 0x00, 0x00}	/* 32, +0dB */
+};
+
+u32 ofdm_swing_table[OFDM_TABLE_SIZE_92D] = {
+	0x0b40002d, /* 0,  -15.0dB */
+	0x0c000030, /* 1,  -14.5dB */
+	0x0cc00033, /* 2,  -14.0dB */
+	0x0d800036, /* 3,  -13.5dB */
+	0x0e400039, /* 4,  -13.0dB */
+	0x0f00003c, /* 5,  -12.5dB */
+	0x10000040, /* 6,  -12.0dB */
+	0x11000044, /* 7,  -11.5dB */
+	0x12000048, /* 8,  -11.0dB */
+	0x1300004c, /* 9,  -10.5dB */
+	0x14400051, /* 10, -10.0dB */
+	0x15800056, /* 11, -9.5dB */
+	0x16c0005b, /* 12, -9.0dB */
+	0x18000060, /* 13, -8.5dB */
+	0x19800066, /* 14, -8.0dB */
+	0x1b00006c, /* 15, -7.5dB */
+	0x1c800072, /* 16, -7.0dB */
+	0x1e400079, /* 17, -6.5dB */
+	0x20000080, /* 18, -6.0dB */
+	0x22000088, /* 19, -5.5dB */
+	0x24000090, /* 20, -5.0dB */
+	0x26000098, /* 21, -4.5dB */
+	0x288000a2, /* 22, -4.0dB */
+	0x2ac000ab, /* 23, -3.5dB */
+	0x2d4000b5, /* 24, -3.0dB */
+	0x300000c0, /* 25, -2.5dB */
+	0x32c000cb, /* 26, -2.0dB */
+	0x35c000d7, /* 27, -1.5dB */
+	0x390000e4, /* 28, -1.0dB */
+	0x3c8000f2, /* 29, -0.5dB */
+	0x40000100, /* 30, +0dB */
+	0x43c0010f, /* 31, +0.5dB */
+	0x47c0011f, /* 32, +1.0dB */
+	0x4c000130, /* 33, +1.5dB */
+	0x50800142, /* 34, +2.0dB */
+	0x55400155, /* 35, +2.5dB */
+	0x5a400169, /* 36, +3.0dB */
+	0x5fc0017f, /* 37, +3.5dB */
+	0x65400195, /* 38, +4.0dB */
+	0x6b8001ae, /* 39, +4.5dB */
+	0x71c001c7, /* 40, +5.0dB */
+	0x788001e2, /* 41, +5.5dB */
+	0x7f8001fe  /* 42, +6.0dB */
+};
+
+
+u8 cck_swing_table_ch1_ch13[CCK_TABLE_SIZE][8] = {
+	{0x09, 0x08, 0x07, 0x06, 0x04, 0x03, 0x01, 0x01},	/* 0, -16.0dB */
+	{0x09, 0x09, 0x08, 0x06, 0x05, 0x03, 0x01, 0x01},	/* 1, -15.5dB */
+	{0x0a, 0x09, 0x08, 0x07, 0x05, 0x03, 0x02, 0x01},	/* 2, -15.0dB */
+	{0x0a, 0x0a, 0x09, 0x07, 0x05, 0x03, 0x02, 0x01},	/* 3, -14.5dB */
+	{0x0b, 0x0a, 0x09, 0x08, 0x06, 0x04, 0x02, 0x01},	/* 4, -14.0dB */
+	{0x0b, 0x0b, 0x0a, 0x08, 0x06, 0x04, 0x02, 0x01},	/* 5, -13.5dB */
+	{0x0c, 0x0c, 0x0a, 0x09, 0x06, 0x04, 0x02, 0x01},	/* 6, -13.0dB */
+	{0x0d, 0x0c, 0x0b, 0x09, 0x07, 0x04, 0x02, 0x01},	/* 7, -12.5dB */
+	{0x0d, 0x0d, 0x0c, 0x0a, 0x07, 0x05, 0x02, 0x01},	/* 8, -12.0dB */
+	{0x0e, 0x0e, 0x0c, 0x0a, 0x08, 0x05, 0x02, 0x01},	/* 9, -11.5dB */
+	{0x0f, 0x0f, 0x0d, 0x0b, 0x08, 0x05, 0x03, 0x01},	/* 10, -11.0dB */
+	{0x10, 0x10, 0x0e, 0x0b, 0x08, 0x05, 0x03, 0x01},	/* 11, -10.5dB */
+	{0x11, 0x11, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01},	/* 12, -10.0dB */
+	{0x12, 0x12, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01},	/* 13, -9.5dB */
+	{0x13, 0x13, 0x10, 0x0d, 0x0a, 0x06, 0x03, 0x01},	/* 14, -9.0dB */
+	{0x14, 0x14, 0x11, 0x0e, 0x0b, 0x07, 0x03, 0x02},	/* 15, -8.5dB */
+	{0x16, 0x15, 0x12, 0x0f, 0x0b, 0x07, 0x04, 0x01},	/* 16, -8.0dB */
+	{0x17, 0x16, 0x13, 0x10, 0x0c, 0x08, 0x04, 0x02},	/* 17, -7.5dB */
+	{0x18, 0x17, 0x15, 0x11, 0x0c, 0x08, 0x04, 0x02},	/* 18, -7.0dB */
+	{0x1a, 0x19, 0x16, 0x12, 0x0d, 0x09, 0x04, 0x02},	/* 19, -6.5dB */
+	{0x1c, 0x1a, 0x18, 0x12, 0x0e, 0x08, 0x04, 0x02},	/* 20, -6.0dB */
+	{0x1d, 0x1c, 0x18, 0x14, 0x0f, 0x0a, 0x05, 0x02},	/* 21, -5.5dB */
+	{0x1f, 0x1e, 0x1a, 0x15, 0x10, 0x0a, 0x05, 0x02},	/* 22, -5.0dB */
+	{0x20, 0x20, 0x1b, 0x16, 0x11, 0x08, 0x05, 0x02},	/* 23, -4.5dB */
+	{0x22, 0x21, 0x1d, 0x18, 0x11, 0x0b, 0x06, 0x02},	/* 24, -4.0dB */
+	{0x24, 0x23, 0x1f, 0x19, 0x13, 0x0c, 0x06, 0x03},	/* 25, -3.5dB */
+	{0x26, 0x25, 0x21, 0x1b, 0x14, 0x0d, 0x06, 0x03},	/* 26, -3.0dB */
+	{0x28, 0x28, 0x22, 0x1c, 0x15, 0x0d, 0x07, 0x03},	/* 27, -2.5dB */
+	{0x2b, 0x2a, 0x25, 0x1e, 0x16, 0x0e, 0x07, 0x03},	/* 28, -2.0dB */
+	{0x2d, 0x2d, 0x27, 0x1f, 0x18, 0x0f, 0x08, 0x03},	/* 29, -1.5dB */
+	{0x30, 0x2f, 0x29, 0x21, 0x19, 0x10, 0x08, 0x03},	/* 30, -1.0dB */
+	{0x33, 0x32, 0x2b, 0x23, 0x1a, 0x11, 0x08, 0x04},	/* 31, -0.5dB */
+	{0x36, 0x35, 0x2e, 0x25, 0x1c, 0x12, 0x09, 0x04}	/* 32, +0dB */
+};
+
+
+u8 cck_swing_table_ch14[CCK_TABLE_SIZE][8] = {
+	{0x09, 0x08, 0x07, 0x04, 0x00, 0x00, 0x00, 0x00},	/* 0, -16.0dB */
+	{0x09, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00},	/* 1, -15.5dB */
+	{0x0a, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00},	/* 2, -15.0dB */
+	{0x0a, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00},	/* 3, -14.5dB */
+	{0x0b, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00},	/* 4, -14.0dB */
+	{0x0b, 0x0b, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00},	/* 5, -13.5dB */
+	{0x0c, 0x0c, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00},	/* 6, -13.0dB */
+	{0x0d, 0x0c, 0x0b, 0x06, 0x00, 0x00, 0x00, 0x00},	/* 7, -12.5dB */
+	{0x0d, 0x0d, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00},	/* 8, -12.0dB */
+	{0x0e, 0x0e, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00},	/* 9, -11.5dB */
+	{0x0f, 0x0f, 0x0d, 0x08, 0x00, 0x00, 0x00, 0x00},	/* 10, -11.0dB */
+	{0x10, 0x10, 0x0e, 0x08, 0x00, 0x00, 0x00, 0x00},	/* 11, -10.5dB */
+	{0x11, 0x11, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00},	/* 12, -10.0dB */
+	{0x12, 0x12, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00},	/* 13, -9.5dB */
+	{0x13, 0x13, 0x10, 0x0a, 0x00, 0x00, 0x00, 0x00},	/* 14, -9.0dB */
+	{0x14, 0x14, 0x11, 0x0a, 0x00, 0x00, 0x00, 0x00},	/* 15, -8.5dB */
+	{0x16, 0x15, 0x12, 0x0b, 0x00, 0x00, 0x00, 0x00},	/* 16, -8.0dB */
+	{0x17, 0x16, 0x13, 0x0b, 0x00, 0x00, 0x00, 0x00},	/* 17, -7.5dB */
+	{0x18, 0x17, 0x15, 0x0c, 0x00, 0x00, 0x00, 0x00},	/* 18, -7.0dB */
+	{0x1a, 0x19, 0x16, 0x0d, 0x00, 0x00, 0x00, 0x00},	/* 19, -6.5dB */
+	{0x1c, 0x1a, 0x18, 0x0e, 0x00, 0x00, 0x00, 0x00},	/* 20, -6.0dB */
+	{0x1d, 0x1c, 0x18, 0x0e, 0x00, 0x00, 0x00, 0x00},	/* 21, -5.5dB */
+	{0x1f, 0x1e, 0x1a, 0x0f, 0x00, 0x00, 0x00, 0x00},	/* 22, -5.0dB */
+	{0x20, 0x20, 0x1b, 0x10, 0x00, 0x00, 0x00, 0x00},	/* 23, -4.5dB */
+	{0x22, 0x21, 0x1d, 0x11, 0x00, 0x00, 0x00, 0x00},	/* 24, -4.0dB */
+	{0x24, 0x23, 0x1f, 0x12, 0x00, 0x00, 0x00, 0x00},	/* 25, -3.5dB */
+	{0x26, 0x25, 0x21, 0x13, 0x00, 0x00, 0x00, 0x00},	/* 26, -3.0dB */
+	{0x28, 0x28, 0x24, 0x14, 0x00, 0x00, 0x00, 0x00},	/* 27, -2.5dB */
+	{0x2b, 0x2a, 0x25, 0x15, 0x00, 0x00, 0x00, 0x00},	/* 28, -2.0dB */
+	{0x2d, 0x2d, 0x17, 0x17, 0x00, 0x00, 0x00, 0x00},	/* 29, -1.5dB */
+	{0x30, 0x2f, 0x29, 0x18, 0x00, 0x00, 0x00, 0x00},	/* 30, -1.0dB */
+	{0x33, 0x32, 0x2b, 0x19, 0x00, 0x00, 0x00, 0x00},	/* 31, -0.5dB */
+	{0x36, 0x35, 0x2e, 0x1b, 0x00, 0x00, 0x00, 0x00}	/* 32, +0dB */
+};
+
+u8 cck_swing_table_ch1_ch14_88f[CCK_TABLE_SIZE_88F][16] = {
+	{0x16, 0x15, 0x13, 0x10, 0xD, 0x9, 0x6, 0x3, 0x2, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},        /* 0  -16dB */
+	{0x18, 0x17, 0x15, 0x12, 0xE, 0xA, 0x7, 0x4, 0x2, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},        /* 1  -15.5dB */
+	{0x1B, 0x1A, 0x18, 0x14, 0x10, 0xB, 0x7, 0x4, 0x2, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},        /* 2  -15dB */
+	{0x1F, 0x1E, 0x1B, 0x17, 0x12, 0xD, 0x8, 0x5, 0x2, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},        /* 3  -14.5dB */
+	{0x22, 0x21, 0x1E, 0x19, 0x14, 0xE, 0x9, 0x5, 0x3, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},        /* 4  -14dB */
+	{0x26, 0x25, 0x22, 0x1C, 0x16, 0x10, 0xA, 0x6, 0x3, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},        /* 5  -13.5dB */
+	{0x2B, 0x2A, 0x26, 0x20, 0x19, 0x12, 0xC, 0x7, 0x3, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},        /* 6  -13dB */
+	{0x30, 0x2F, 0x2A, 0x24, 0x1C, 0x14, 0xD, 0x8, 0x4, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},        /* 7  -12.5dB */
+	{0x36, 0x34, 0x2F, 0x28, 0x1F, 0x17, 0xF, 0x9, 0x4, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},        /* 8  -12dB */
+	{0x3D, 0x3B, 0x35, 0x2D, 0x23, 0x19, 0x11, 0xA, 0x5, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},        /* 9  -11.5dB */
+	{0x44, 0x42, 0x3C, 0x33, 0x28, 0x1C, 0x13, 0xB, 0x5, 0x2, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},        /* 10  -11dB */
+	{0x4D, 0x4A, 0x43, 0x39, 0x2C, 0x20, 0x15, 0xC, 0x6, 0x2, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},        /* 11  -10.5dB */
+	{0x56, 0x53, 0x4B, 0x40, 0x32, 0x24, 0x17, 0xE, 0x6, 0x2, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},        /* 12  -10dB */
+	{0x60, 0x5D, 0x54, 0x47, 0x38, 0x28, 0x1A, 0xF, 0x7, 0x2, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},        /* 13  -9.5dB */
+	{0x6C, 0x69, 0x5F, 0x50, 0x3F, 0x2D, 0x1E, 0x11, 0x8, 0x3, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},        /* 14  -9dB */
+	{0x79, 0x76, 0x6A, 0x5A, 0x46, 0x33, 0x21, 0x13, 0x9, 0x3, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},        /* 15  -8.5dB */
+	{0x88, 0x84, 0x77, 0x65, 0x4F, 0x39, 0x25, 0x15, 0xA, 0x3, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},        /* 16  -8dB */
+	{0x99, 0x94, 0x86, 0x71, 0x58, 0x40, 0x2A, 0x18, 0xB, 0x4, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},        /* 17  -7.5dB */
+	{0xAC, 0xA6, 0x96, 0x7F, 0x63, 0x47, 0x2F, 0x1B, 0xD, 0x4, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},        /* 18  -7dB */
+	{0xC1, 0xBA, 0xA8, 0x8F, 0x6F, 0x50, 0x35, 0x1E, 0xE, 0x4, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},        /* 19  -6.5dB */
+	{0xD8, 0xD1, 0xBD, 0xA0, 0x7D, 0x5A, 0x3B, 0x22, 0x10, 0x5, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}      /* 20  -6dB */
+};
+
+
+u8 cck_swing_table_ch1_ch13_88f[CCK_TABLE_SIZE_88F][16] = {
+	{0x16, 0x15, 0x13, 0x10, 0xD, 0x9, 0x6, 0x3, 0x2, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},        /* 0  -16dB */
+	{0x18, 0x17, 0x15, 0x12, 0xE, 0xA, 0x7, 0x4, 0x2, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},        /* 1  -15.5dB */
+	{0x1B, 0x1A, 0x18, 0x14, 0x10, 0xB, 0x7, 0x4, 0x2, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},        /* 2  -15dB */
+	{0x1F, 0x1E, 0x1B, 0x17, 0x12, 0xD, 0x8, 0x5, 0x2, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},        /* 3  -14.5dB */
+	{0x22, 0x21, 0x1E, 0x19, 0x14, 0xE, 0x9, 0x5, 0x3, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},        /* 4  -14dB */
+	{0x26, 0x25, 0x22, 0x1C, 0x16, 0x10, 0xA, 0x6, 0x3, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},        /* 5  -13.5dB */
+	{0x2B, 0x2A, 0x26, 0x20, 0x19, 0x12, 0xC, 0x7, 0x3, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},        /* 6  -13dB */
+	{0x30, 0x2F, 0x2A, 0x24, 0x1C, 0x14, 0xD, 0x8, 0x4, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},        /* 7  -12.5dB */
+	{0x36, 0x34, 0x2F, 0x28, 0x1F, 0x17, 0xF, 0x9, 0x4, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},        /* 8  -12dB */
+	{0x3D, 0x3B, 0x35, 0x2D, 0x23, 0x19, 0x11, 0xA, 0x5, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},        /* 9  -11.5dB */
+	{0x44, 0x42, 0x3C, 0x33, 0x28, 0x1C, 0x13, 0xB, 0x5, 0x2, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},        /* 10  -11dB */
+	{0x4D, 0x4A, 0x43, 0x39, 0x2C, 0x20, 0x15, 0xC, 0x6, 0x2, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},        /* 11  -10.5dB */
+	{0x56, 0x53, 0x4B, 0x40, 0x32, 0x24, 0x17, 0xE, 0x6, 0x2, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},        /* 12  -10dB */
+	{0x60, 0x5D, 0x54, 0x47, 0x38, 0x28, 0x1A, 0xF, 0x7, 0x2, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},        /* 13  -9.5dB */
+	{0x6C, 0x69, 0x5F, 0x50, 0x3F, 0x2D, 0x1E, 0x11, 0x8, 0x3, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},        /* 14  -9dB */
+	{0x79, 0x76, 0x6A, 0x5A, 0x46, 0x33, 0x21, 0x13, 0x9, 0x3, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},        /* 15  -8.5dB */
+	{0x88, 0x84, 0x77, 0x65, 0x4F, 0x39, 0x25, 0x15, 0xA, 0x3, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},        /* 16  -8dB */
+	{0x99, 0x94, 0x86, 0x71, 0x58, 0x40, 0x2A, 0x18, 0xB, 0x4, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},        /* 17  -7.5dB */
+	{0xAC, 0xA6, 0x96, 0x7F, 0x63, 0x47, 0x2F, 0x1B, 0xD, 0x4, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},        /* 18  -7dB */
+	{0xC1, 0xBA, 0xA8, 0x8F, 0x6F, 0x50, 0x35, 0x1E, 0xE, 0x4, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},        /* 19  -6.5dB */
+	{0xD8, 0xD1, 0xBD, 0xA0, 0x7D, 0x5A, 0x3B, 0x22, 0x10, 0x5, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}      /* 20  -6dB */
+};
+
+
+u8 cck_swing_table_ch14_88f[CCK_TABLE_SIZE_88F][16] = {
+	{0x44,	 0x42, 0x3C, 0x28, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-16dB*/
+	{0x48, 0x46, 0x3F, 0x2A, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-15.5dB*/
+	{0x4D, 0x4A, 0x43, 0x2C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-15dB*/
+	{0x51, 0x4F, 0x47, 0x2F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},	    /*-14.5dB*/
+	{0x56, 0x53, 0x4B, 0x32, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-14dB*/
+	{0x5B, 0x58, 0x50, 0x35, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-13.5dB*/
+	{0x60, 0x5D, 0x54, 0x38, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-13dB*/
+	{0x66, 0x63, 0x59, 0x3B, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-12.5dB*/
+	{0x6C, 0x69, 0x5F, 0x3F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-12dB*/
+	{0x73, 0x6F, 0x64, 0x42, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-11.5dB*/
+	{0x79, 0x76, 0x6A, 0x46, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-11dB*/
+	{0x81, 0x7C, 0x71, 0x4A, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-10.5dB*/
+	{0x88, 0x84, 0x77, 0x4F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-10dB*/
+	{0x90, 0x8C, 0x7E, 0x54, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-9.5dB*/
+	{0x99, 0x94, 0x86, 0x58, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-9dB*/
+	{0xA2, 0x9D, 0x8E, 0x5E, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-8.5dB*/
+	{0xAC, 0xA6, 0x96, 0x63, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-8dB*/
+	{0xB6, 0xB0, 0x9F, 0x69, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-7.5dB*/
+	{0xC1, 0xBA, 0xA8, 0x6F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-7dB*/
+	{0xCC, 0xC5, 0xB2, 0x76, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-6.5dB*/
+	{0xD8, 0xD1, 0xBD, 0x7D, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}     /*-6dB*/
+};
+
+
+
+#if 0
+u32 ofdm_swing_table_92e[OFDM_TABLE_SIZE_92E] = {
+	/* Index0   6  dB */ 0x7fc001ff,
+	/* Index1   5.7dB */ 0x7b4001ed,
+	/* Index2   5.4dB */ 0x774001dd,
+	/* Index3   5.1dB */ 0x734001cd,
+	/* Index4   4.8dB */ 0x6f4001bd,
+	/* Index5   4.5dB */ 0x6b8001ae,
+	/* Index6   4.2dB */ 0x67c0019f,
+	/* Index7   3.9dB */ 0x64400191,
+	/* Index8   3.6dB */ 0x60c00183,
+	/* Index9   3.3dB */ 0x5d800176,
+	/* Index10  3  dB */ 0x5a80016a,
+	/* Index11  2.7dB */ 0x5740015d,
+	/* Index12  2.4dB */ 0x54400151,
+	/* Index13  2.1dB */ 0x51800146,
+	/* Index14  1.8dB */ 0x4ec0013b,
+	/* Index15  1.5dB */ 0x4c000130,
+	/* Index16  1.2dB */ 0x49800126,
+	/* Index17  0.9dB */ 0x4700011c,
+	/* Index18  0.6dB */ 0x44800112,
+	/* Index19  0.3dB */ 0x42000108,
+	/* Index20  0  dB */ 0x40000100, /* 20 This is OFDM base index */
+	/* Index21 -0.3dB */ 0x3dc000f7,
+	/* Index22 -0.6dB */ 0x3bc000ef,
+	/* Index23 -0.9dB */ 0x39c000e7,
+	/* Index24 -1.2dB */ 0x37c000df,
+	/* Index25 -1.5dB */ 0x35c000d7,
+	/* Index26 -1.8dB */ 0x340000d0,
+	/* Index27 -2.1dB */ 0x324000c9,
+	/* Index28 -2.4dB */ 0x308000c2,
+	/* Index29 -2.7dB */ 0x2f0000bc,
+	/* Index30 -3  dB */ 0x2d4000b5,
+	/* Index31 -3.3dB */ 0x2bc000af,
+	/* Index32 -3.6dB */ 0x2a4000a9,
+	/* Index33 -3.9dB */ 0x28c000a3,
+	/* Index34 -4.2dB */ 0x2780009e,
+	/* Index35 -4.5dB */ 0x26000098,
+	/* Index36 -4.8dB */ 0x24c00093,
+	/* Index37 -5.1dB */ 0x2380008e,
+	/* Index38 -5.4dB */ 0x22400089,
+	/* Index39 -5.7dB */ 0x21400085,
+	/* Index40 -6  dB */ 0x20000080,
+	/* Index41 -6.3dB */ 0x1f00007c,
+	/* Index42 -6.6dB */ 0x1e000078,
+	/* Index43 -6.9dB */ 0x1d000074,
+	/* Index44 -7.2dB */ 0x1c000070,
+	/* Index45 -7.5dB */ 0x1b00006c,
+	/* Index46 -7.8dB */ 0x1a000068,
+	/* Index47 -8.1dB */ 0x19400065,
+	/* Index48 -8.4dB */ 0x18400061,
+	/* Index49 -8.7dB */ 0x1780005e,
+	/* Index50 -9  dB */ 0x16c0005b,
+	/* Index51 -9.3dB */ 0x16000058,
+	/* Index52 -9.6dB */ 0x15400055,
+	/* Index53 -9.9dB */ 0x14800052
+};
+u8 cck_swing_table_ch1_ch13_92e[CCK_TABLE_SIZE_92E][8] = {
+	/* Index0    0  dB */    {0x36, 0x34, 0x2E, 0x26, 0x1C, 0x12, 0x08, 0x04},
+	/* Index1   -0.3dB */    {0x34, 0x32, 0x2C, 0x25, 0x1B, 0x11, 0x08, 0x04},
+	/* Index2   -0.6dB */    {0x32, 0x30, 0x2B, 0x23, 0x1A, 0x11, 0x07, 0x04},
+	/* Index3   -0.9dB */    {0x31, 0x2F, 0x29, 0x22, 0x19, 0x10, 0x07, 0x04},
+	/* Index4   -1.2dB */    {0x2F, 0x2D, 0x28, 0x21, 0x18, 0x10, 0x07, 0x03},
+	/* Index5   -1.5dB */    {0x2D, 0x2C, 0x27, 0x20, 0x18, 0x0F, 0x07, 0x03},
+	/* Index6   -1.8dB */    {0x2C, 0x2A, 0x25, 0x1F, 0x17, 0x0F, 0x06, 0x03},
+	/* Index7   -2.1dB */    {0x2A, 0x29, 0x24, 0x1E, 0x16, 0x0E, 0x06, 0x03},
+	/* Index8   -2.4dB */    {0x29, 0x27, 0x23, 0x1D, 0x15, 0x0E, 0x06, 0x03},
+	/* Index9   -2.7dB */    {0x27, 0x26, 0x22, 0x1C, 0x14, 0x0D, 0x06, 0x03},
+	/* Index10  -3  dB */    {0x26, 0x25, 0x20, 0x1B, 0x14, 0x0D, 0x06, 0x03},
+	/* Index11  -3.3dB */    {0x25, 0x23, 0x1F, 0x1A, 0x13, 0x0C, 0x05, 0x03},
+	/* Index12  -3.6dB */    {0x24, 0x22, 0x1E, 0x19, 0x12, 0x0C, 0x05, 0x03},
+	/* Index13  -3.9dB */    {0x22, 0x21, 0x1D, 0x18, 0x12, 0x0B, 0x05, 0x03},
+	/* Index14  -4.2dB */    {0x21, 0x20, 0x1C, 0x17, 0x11, 0x0B, 0x05, 0x02},
+	/* Index15  -4.5dB */    {0x20, 0x1F, 0x1B, 0x17, 0x11, 0x0B, 0x05, 0x02},
+	/* Index16  -4.8dB */    {0x1F, 0x1E, 0x1A, 0x16, 0x10, 0x0A, 0x05, 0x02},
+	/* Index17  -5.1dB */    {0x1E, 0x1D, 0x1A, 0x15, 0x10, 0x0A, 0x04, 0x02},
+	/* Index18  -5.4dB */    {0x1D, 0x1C, 0x19, 0x14, 0x0F, 0x0A, 0x04, 0x02},
+	/* Index19  -5.7dB */    {0x1C, 0x1B, 0x18, 0x14, 0x0E, 0x09, 0x04, 0x02},
+	/* Index20  -6.0dB */    {0x1B, 0x1A, 0x17, 0x13, 0x0E, 0x09, 0x04, 0x02}, /* 20 This is CCK base index */
+	/* Index21  -6.3dB */    {0x1A, 0x19, 0x16, 0x12, 0x0E, 0x09, 0x04, 0x02},
+	/* Index22  -6.6dB */    {0x19, 0x18, 0x15, 0x12, 0x0D, 0x08, 0x04, 0x02},
+	/* Index23  -6.9dB */    {0x18, 0x17, 0x15, 0x11, 0x0D, 0x08, 0x04, 0x02},
+	/* Index24  -7.2dB */    {0x18, 0x17, 0x14, 0x11, 0x0C, 0x08, 0x03, 0x02},
+	/* Index25  -7.5dB */    {0x17, 0x16, 0x13, 0x10, 0x0C, 0x08, 0x03, 0x02},
+	/* Index26  -7.8dB */    {0x16, 0x15, 0x13, 0x0F, 0x0B, 0x07, 0x03, 0x02},
+	/* Index27  -8.1dB */    {0x15, 0x14, 0x12, 0x0F, 0x0B, 0x07, 0x03, 0x02},
+	/* Index28  -8.4dB */    {0x14, 0x14, 0x11, 0x0E, 0x0B, 0x07, 0x03, 0x02},
+	/* Index29  -8.7dB */    {0x14, 0x13, 0x11, 0x0E, 0x0A, 0x07, 0x03, 0x01},
+	/* Index30  -9.0dB */    {0x13, 0x12, 0x10, 0x0D, 0x0A, 0x06, 0x03, 0x01}, /* 30 This is hp CCK base index */
+	/* Index31  -9.3dB */    {0x12, 0x12, 0x0F, 0x0D, 0x0A, 0x06, 0x03, 0x01},
+	/* Index32  -9.6dB */    {0x12, 0x11, 0x0F, 0x0D, 0x09, 0x06, 0x03, 0x01},
+	/* Index33  -9.9dB */    {0x11, 0x11, 0x0F, 0x0C, 0x09, 0x06, 0x03, 0x01},
+	/* Index34 -10.2dB */    {0x11, 0x11, 0x0E, 0x0C, 0x09, 0x06, 0x02, 0x01},
+	/* Index35 -10.5dB */    {0x10, 0x0F, 0x0E, 0x0B, 0x08, 0x05, 0x02, 0x01},
+	/* Index36 -10.8dB */    {0x10, 0x0F, 0x0D, 0x0B, 0x08, 0x05, 0x02, 0x01},
+	/* Index37 -11.1dB */    {0x0F, 0x0E, 0x0D, 0x0A, 0x08, 0x05, 0x02, 0x01},
+	/* Index38 -11.4dB */    {0x0E, 0x0E, 0x0C, 0x0A, 0x07, 0x05, 0x02, 0x01},
+	/* Index39 -11.7dB */    {0x0E, 0x0D, 0x0C, 0x0A, 0x07, 0x05, 0x02, 0x01},
+	/* Index40 -12  dB */    {0x0E, 0x0D, 0x0C, 0x0A, 0x07, 0x05, 0x02, 0x01},
+	/* Index41 -12.3dB */    {0x0D, 0x0D, 0x0B, 0x09, 0x07, 0x04, 0x02, 0x01},
+	/* Index42 -12.6dB */    {0x0D, 0x0C, 0x0B, 0x09, 0x07, 0x04, 0x02, 0x01},
+	/* Index43 -12.9dB */    {0x0C, 0x0C, 0x0A, 0x09, 0x06, 0x04, 0x02, 0x01},
+	/* Index44 -13.2dB */    {0x0C, 0x0B, 0x0A, 0x08, 0x06, 0x04, 0x02, 0x01},
+	/* Index45 -13.5dB */    {0x0B, 0x0B, 0x0A, 0x08, 0x06, 0x04, 0x02, 0x01},
+	/* Index46 -13.8dB */    {0x0B, 0x0B, 0x09, 0x08, 0x06, 0x04, 0x02, 0x01},
+	/* Index47 -14.1dB */    {0x0B, 0x0A, 0x09, 0x07, 0x06, 0x04, 0x02, 0x01},
+	/* Index48 -14.4dB */    {0x0A, 0x0A, 0x09, 0x07, 0x05, 0x03, 0x02, 0x01},
+	/* Index49 -14.7dB */    {0x0A, 0x0A, 0x08, 0x07, 0x05, 0x03, 0x01, 0x01},
+	/* Index50 -15  dB */    {0x0A, 0x09, 0x08, 0x07, 0x05, 0x03, 0x01, 0x01},
+	/* Index51 -15.3dB */    {0x09, 0x09, 0x08, 0x06, 0x05, 0x03, 0x01, 0x01},
+	/* Index52 -15.6dB */    {0x09, 0x09, 0x08, 0x06, 0x05, 0x03, 0x01, 0x01},
+	/* Index53 -15.9dB */    {0x09, 0x08, 0x07, 0x06, 0x04, 0x03, 0x01, 0x01}
+};
+u8 cck_swing_table_ch14_92e[CCK_TABLE_SIZE_92E][8] = {
+	/* Index0    0  dB */    {0x36, 0x34, 0x2E, 0x26, 0x00, 0x00, 0x00, 0x00},
+	/* Index1   -0.3dB */    {0x34, 0x32, 0x2C, 0x25, 0x00, 0x00, 0x00, 0x00},
+	/* Index2   -0.6dB */    {0x32, 0x30, 0x2B, 0x23, 0x00, 0x00, 0x00, 0x00},
+	/* Index3   -0.9dB */    {0x31, 0x2F, 0x29, 0x22, 0x00, 0x00, 0x00, 0x00},
+	/* Index4   -1.2dB */    {0x2F, 0x2D, 0x28, 0x21, 0x00, 0x00, 0x00, 0x00},
+	/* Index5   -1.5dB */    {0x2D, 0x2C, 0x27, 0x20, 0x00, 0x00, 0x00, 0x00},
+	/* Index6   -1.8dB */    {0x2C, 0x2A, 0x25, 0x1F, 0x00, 0x00, 0x00, 0x00},
+	/* Index7   -2.1dB */    {0x2A, 0x29, 0x24, 0x1E, 0x00, 0x00, 0x00, 0x00},
+	/* Index8   -2.4dB */    {0x29, 0x27, 0x23, 0x1D, 0x00, 0x00, 0x00, 0x00},
+	/* Index9   -2.7dB */    {0x27, 0x26, 0x22, 0x1C, 0x00, 0x00, 0x00, 0x00},
+	/* Index10  -3  dB */    {0x26, 0x25, 0x20, 0x1B, 0x00, 0x00, 0x00, 0x00},
+	/* Index11  -3.3dB */    {0x25, 0x23, 0x1F, 0x1A, 0x00, 0x00, 0x00, 0x00},
+	/* Index12  -3.6dB */    {0x24, 0x22, 0x1E, 0x19, 0x00, 0x00, 0x00, 0x00},
+	/* Index13  -3.9dB */    {0x22, 0x21, 0x1D, 0x18, 0x00, 0x00, 0x00, 0x00},
+	/* Index14  -4.2dB */    {0x21, 0x20, 0x1C, 0x17, 0x00, 0x00, 0x00, 0x00},
+	/* Index15  -4.5dB */    {0x20, 0x1F, 0x1B, 0x17, 0x00, 0x00, 0x00, 0x00},
+	/* Index16  -4.8dB */    {0x1F, 0x1E, 0x1A, 0x16, 0x00, 0x00, 0x00, 0x00},
+	/* Index17  -5.1dB */    {0x1E, 0x1D, 0x1A, 0x15, 0x00, 0x00, 0x00, 0x00},
+	/* Index18  -5.4dB */    {0x1D, 0x1C, 0x19, 0x14, 0x00, 0x00, 0x00, 0x00},
+	/* Index19  -5.7dB */    {0x1C, 0x1B, 0x18, 0x14, 0x00, 0x00, 0x00, 0x00},
+	/* Index20  -6  dB */     {0x1B, 0x1A, 0x17, 0x13, 0x00, 0x00, 0x00, 0x00},
+	/* Index21  -6.3dB */    {0x1A, 0x19, 0x16, 0x12, 0x00, 0x00, 0x00, 0x00},
+	/* Index22  -6.6dB */    {0x19, 0x18, 0x15, 0x12, 0x00, 0x00, 0x00, 0x00},
+	/* Index23  -6.9dB */    {0x18, 0x17, 0x15, 0x11, 0x00, 0x00, 0x00, 0x00},
+	/* Index24  -7.2dB */    {0x18, 0x17, 0x14, 0x11, 0x00, 0x00, 0x00, 0x00},
+	/* Index25  -7.5dB */    {0x17, 0x16, 0x13, 0x10, 0x00, 0x00, 0x00, 0x00},
+	/* Index26  -7.8dB */    {0x16, 0x15, 0x13, 0x0F, 0x00, 0x00, 0x00, 0x00},
+	/* Index27  -8.1dB */    {0x15, 0x14, 0x12, 0x0F, 0x00, 0x00, 0x00, 0x00},
+	/* Index28  -8.4dB */    {0x14, 0x14, 0x11, 0x0E, 0x00, 0x00, 0x00, 0x00},
+	/* Index29  -8.7dB */    {0x14, 0x13, 0x11, 0x0E, 0x00, 0x00, 0x00, 0x00},
+	/* Index30  -9  dB */    {0x13, 0x12, 0x10, 0x0D, 0x00, 0x00, 0x00, 0x00},
+	/* Index31  -9.3dB */    {0x12, 0x12, 0x0F, 0x0D, 0x00, 0x00, 0x00, 0x00},
+	/* Index32  -9.6dB */    {0x12, 0x11, 0x0F, 0x0D, 0x00, 0x00, 0x00, 0x00},
+	/* Index33  -9.9dB */    {0x11, 0x11, 0x0F, 0x0C, 0x00, 0x00, 0x00, 0x00},
+	/* Index34 -10.2dB */    {0x11, 0x11, 0x0E, 0x0C, 0x00, 0x00, 0x00, 0x00},
+	/* Index35 -10.5dB */    {0x10, 0x0F, 0x0E, 0x0B, 0x00, 0x00, 0x00, 0x00},
+	/* Index36 -10.8dB */    {0x10, 0x0F, 0x0D, 0x0B, 0x00, 0x00, 0x00, 0x00},
+	/* Index37 -11.1dB */    {0x0F, 0x0E, 0x0D, 0x0A, 0x00, 0x00, 0x00, 0x00},
+	/* Index38 -11.4dB */    {0x0E, 0x0E, 0x0C, 0x0A, 0x00, 0x00, 0x00, 0x00},
+	/* Index39 -11.7dB */    {0x0E, 0x0D, 0x0C, 0x0A, 0x00, 0x00, 0x00, 0x00},
+	/* Index40 -12  dB */    {0x0E, 0x0D, 0x0C, 0x0A, 0x00, 0x00, 0x00, 0x00},
+	/* Index41 -12.3dB */    {0x0D, 0x0D, 0x0B, 0x09, 0x00, 0x00, 0x00, 0x00},
+	/* Index42 -12.6dB */    {0x0D, 0x0C, 0x0B, 0x09, 0x00, 0x00, 0x00, 0x00},
+	/* Index43 -12.9dB */    {0x0C, 0x0C, 0x0A, 0x09, 0x00, 0x00, 0x00, 0x00},
+	/* Index44 -13.2dB */    {0x0C, 0x0B, 0x0A, 0x08, 0x00, 0x00, 0x00, 0x00},
+	/* Index45 -13.5dB */    {0x0B, 0x0B, 0x0A, 0x08, 0x00, 0x00, 0x00, 0x00},
+	/* Index46 -13.8dB */    {0x0B, 0x0B, 0x09, 0x08, 0x00, 0x00, 0x00, 0x00},
+	/* Index47 -14.1dB */    {0x0B, 0x0A, 0x09, 0x07, 0x00, 0x00, 0x00, 0x00},
+	/* Index48 -14.4dB */    {0x0A, 0x0A, 0x09, 0x07, 0x00, 0x00, 0x00, 0x00},
+	/* Index49 -14.7dB */    {0x0A, 0x0A, 0x08, 0x07, 0x00, 0x00, 0x00, 0x00},
+	/* Index50 -15  dB */    {0x0A, 0x09, 0x08, 0x07, 0x00, 0x00, 0x00, 0x00},
+	/* Index51 -15.3dB */    {0x09, 0x09, 0x08, 0x06, 0x00, 0x00, 0x00, 0x00},
+	/* Index52 -15.6dB */    {0x09, 0x09, 0x08, 0x06, 0x00, 0x00, 0x00, 0x00},
+	/* Index53 -15.9dB */    {0x09, 0x08, 0x07, 0x06, 0x00, 0x00, 0x00, 0x00}
+};
+#endif
+
+#ifdef AP_BUILD_WORKAROUND
+
+unsigned int tx_pwr_trk_ofdm_swing_tbl[tx_pwr_trk_ofdm_swing_tbl_len] = {
+	/*  +6.0dB */ 0x7f8001fe,
+	/*  +5.5dB */ 0x788001e2,
+	/*  +5.0dB */ 0x71c001c7,
+	/*  +4.5dB */ 0x6b8001ae,
+	/*  +4.0dB */ 0x65400195,
+	/*  +3.5dB */ 0x5fc0017f,
+	/*  +3.0dB */ 0x5a400169,
+	/*  +2.5dB */ 0x55400155,
+	/*  +2.0dB */ 0x50800142,
+	/*  +1.5dB */ 0x4c000130,
+	/*  +1.0dB */ 0x47c0011f,
+	/*  +0.5dB */ 0x43c0010f,
+	/*   0.0dB */ 0x40000100,
+	/*  -0.5dB */ 0x3c8000f2,
+	/*  -1.0dB */ 0x390000e4,
+	/*  -1.5dB */ 0x35c000d7,
+	/*  -2.0dB */ 0x32c000cb,
+	/*  -2.5dB */ 0x300000c0,
+	/*  -3.0dB */ 0x2d4000b5,
+	/*  -3.5dB */ 0x2ac000ab,
+	/*  -4.0dB */ 0x288000a2,
+	/*  -4.5dB */ 0x26000098,
+	/*  -5.0dB */ 0x24000090,
+	/*  -5.5dB */ 0x22000088,
+	/*  -6.0dB */ 0x20000080,
+	/*  -6.5dB */ 0x1a00006c,
+	/*  -7.0dB */ 0x1c800072,
+	/*  -7.5dB */ 0x18000060,
+	/*  -8.0dB */ 0x19800066,
+	/*  -8.5dB */ 0x15800056,
+	/*  -9.0dB */ 0x26c0005b,
+	/*  -9.5dB */ 0x14400051,
+	/* -10.0dB */ 0x24400051,
+	/* -10.5dB */ 0x1300004c,
+	/* -11.0dB */ 0x12000048,
+	/* -11.5dB */ 0x11000044,
+	/* -12.0dB */ 0x10000040
+};
+#endif
+
+#endif
+
+
+u8 delta_swing_table_idx_2ga_p_default[DELTA_SWINGIDX_SIZE] = {0, 0, 0, 0, 1, 1, 2, 2, 3, 3
+	, 4, 4, 4,  4,  4,  4,  4,  4,  5,  5,  7,  7,  8,  8,  8,  9,  9,  9,  9,  9
+							      };
+u8 delta_swing_table_idx_2ga_n_default[DELTA_SWINGIDX_SIZE] = {0, 0, 0, 2, 2, 3, 3, 4, 4, 4
+	, 4, 5, 5,  6,  6,  7,  7,  7,  7,  8,  8,  9,  9, 10, 10, 10, 11, 11, 11, 11
+							      };
+
+
+#ifdef CONFIG_WLAN_HAL_8192EE
+u32 ofdm_swing_table_92e[OFDM_TABLE_SIZE_92E] = {
+	/* Index0   6  dB */ 0x7fc001ff,
+	/* Index1   5.7dB */ 0x7b4001ed,
+	/* Index2   5.4dB */ 0x774001dd,
+	/* Index3   5.1dB */ 0x734001cd,
+	/* Index4   4.8dB */ 0x6f4001bd,
+	/* Index5   4.5dB */ 0x6b8001ae,
+	/* Index6   4.2dB */ 0x67c0019f,
+	/* Index7   3.9dB */ 0x64400191,
+	/* Index8   3.6dB */ 0x60c00183,
+	/* Index9   3.3dB */ 0x5d800176,
+	/* Index10  3  dB */ 0x5a80016a,
+	/* Index11  2.7dB */ 0x5740015d,
+	/* Index12  2.4dB */ 0x54400151,
+	/* Index13  2.1dB */ 0x51800146,
+	/* Index14  1.8dB */ 0x4ec0013b,
+	/* Index15  1.5dB */ 0x4c000130,
+	/* Index16  1.2dB */ 0x49800126,
+	/* Index17  0.9dB */ 0x4700011c,
+	/* Index18  0.6dB */ 0x44800112,
+	/* Index19  0.3dB */ 0x42000108,
+	/* Index20  0  dB */ 0x40000100, /* 20 This is OFDM base index */
+	/* Index21 -0.3dB */ 0x3dc000f7,
+	/* Index22 -0.6dB */ 0x3bc000ef,
+	/* Index23 -0.9dB */ 0x39c000e7,
+	/* Index24 -1.2dB */ 0x37c000df,
+	/* Index25 -1.5dB */ 0x35c000d7,
+	/* Index26 -1.8dB */ 0x340000d0,
+	/* Index27 -2.1dB */ 0x324000c9,
+	/* Index28 -2.4dB */ 0x308000c2,
+	/* Index29 -2.7dB */ 0x2f0000bc,
+	/* Index30 -3  dB */ 0x2d4000b5,
+	/* Index31 -3.3dB */ 0x2bc000af,
+	/* Index32 -3.6dB */ 0x2a4000a9,
+	/* Index33 -3.9dB */ 0x28c000a3,
+	/* Index34 -4.2dB */ 0x2780009e,
+	/* Index35 -4.5dB */ 0x26000098,
+	/* Index36 -4.8dB */ 0x24c00093,
+	/* Index37 -5.1dB */ 0x2380008e,
+	/* Index38 -5.4dB */ 0x22400089,
+	/* Index39 -5.7dB */ 0x21400085,
+	/* Index40 -6  dB */ 0x20000080,
+	/* Index41 -6.3dB */ 0x1f00007c,
+	/* Index42 -6.6dB */ 0x1e000078,
+	/* Index43 -6.9dB */ 0x1d000074,
+	/* Index44 -7.2dB */ 0x1c000070,
+	/* Index45 -7.5dB */ 0x1b00006c,
+	/* Index46 -7.8dB */ 0x1a000068,
+	/* Index47 -8.1dB */ 0x19400065,
+	/* Index48 -8.4dB */ 0x18400061,
+	/* Index49 -8.7dB */ 0x1780005e,
+	/* Index50 -9  dB */ 0x16c0005b,
+	/* Index51 -9.3dB */ 0x16000058,
+	/* Index52 -9.6dB */ 0x15400055,
+	/* Index53 -9.9dB */ 0x14800052
+};
+u8 cck_swing_table_ch1_ch13_92e[CCK_TABLE_SIZE_92E][8] = {
+	/* Index0    0  dB */    {0x36, 0x34, 0x2E, 0x26, 0x1C, 0x12, 0x08, 0x04},
+	/* Index1   -0.3dB */    {0x34, 0x32, 0x2C, 0x25, 0x1B, 0x11, 0x08, 0x04},
+	/* Index2   -0.6dB */    {0x32, 0x30, 0x2B, 0x23, 0x1A, 0x11, 0x07, 0x04},
+	/* Index3   -0.9dB */    {0x31, 0x2F, 0x29, 0x22, 0x19, 0x10, 0x07, 0x04},
+	/* Index4   -1.2dB */    {0x2F, 0x2D, 0x28, 0x21, 0x18, 0x10, 0x07, 0x03},
+	/* Index5   -1.5dB */    {0x2D, 0x2C, 0x27, 0x20, 0x18, 0x0F, 0x07, 0x03},
+	/* Index6   -1.8dB */    {0x2C, 0x2A, 0x25, 0x1F, 0x17, 0x0F, 0x06, 0x03},
+	/* Index7   -2.1dB */    {0x2A, 0x29, 0x24, 0x1E, 0x16, 0x0E, 0x06, 0x03},
+	/* Index8   -2.4dB */    {0x29, 0x27, 0x23, 0x1D, 0x15, 0x0E, 0x06, 0x03},
+	/* Index9   -2.7dB */    {0x27, 0x26, 0x22, 0x1C, 0x14, 0x0D, 0x06, 0x03},
+	/* Index10  -3  dB */    {0x26, 0x25, 0x20, 0x1B, 0x14, 0x0D, 0x06, 0x03},
+	/* Index11  -3.3dB */    {0x25, 0x23, 0x1F, 0x1A, 0x13, 0x0C, 0x05, 0x03},
+	/* Index12  -3.6dB */    {0x24, 0x22, 0x1E, 0x19, 0x12, 0x0C, 0x05, 0x03},
+	/* Index13  -3.9dB */    {0x22, 0x21, 0x1D, 0x18, 0x12, 0x0B, 0x05, 0x03},
+	/* Index14  -4.2dB */    {0x21, 0x20, 0x1C, 0x17, 0x11, 0x0B, 0x05, 0x02},
+	/* Index15  -4.5dB */    {0x20, 0x1F, 0x1B, 0x17, 0x11, 0x0B, 0x05, 0x02},
+	/* Index16  -4.8dB */    {0x1F, 0x1E, 0x1A, 0x16, 0x10, 0x0A, 0x05, 0x02},
+	/* Index17  -5.1dB */    {0x1E, 0x1D, 0x1A, 0x15, 0x10, 0x0A, 0x04, 0x02},
+	/* Index18  -5.4dB */    {0x1D, 0x1C, 0x19, 0x14, 0x0F, 0x0A, 0x04, 0x02},
+	/* Index19  -5.7dB */    {0x1C, 0x1B, 0x18, 0x14, 0x0E, 0x09, 0x04, 0x02},
+	/* Index20  -6.0dB */    {0x1B, 0x1A, 0x17, 0x13, 0x0E, 0x09, 0x04, 0x02}, /* 20 This is CCK base index */
+	/* Index21  -6.3dB */    {0x1A, 0x19, 0x16, 0x12, 0x0E, 0x09, 0x04, 0x02},
+	/* Index22  -6.6dB */    {0x19, 0x18, 0x15, 0x12, 0x0D, 0x08, 0x04, 0x02},
+	/* Index23  -6.9dB */    {0x18, 0x17, 0x15, 0x11, 0x0D, 0x08, 0x04, 0x02},
+	/* Index24  -7.2dB */    {0x18, 0x17, 0x14, 0x11, 0x0C, 0x08, 0x03, 0x02},
+	/* Index25  -7.5dB */    {0x17, 0x16, 0x13, 0x10, 0x0C, 0x08, 0x03, 0x02},
+	/* Index26  -7.8dB */    {0x16, 0x15, 0x13, 0x0F, 0x0B, 0x07, 0x03, 0x02},
+	/* Index27  -8.1dB */    {0x15, 0x14, 0x12, 0x0F, 0x0B, 0x07, 0x03, 0x02},
+	/* Index28  -8.4dB */    {0x14, 0x14, 0x11, 0x0E, 0x0B, 0x07, 0x03, 0x02},
+	/* Index29  -8.7dB */    {0x14, 0x13, 0x11, 0x0E, 0x0A, 0x07, 0x03, 0x01},
+	/* Index30  -9.0dB */    {0x13, 0x12, 0x10, 0x0D, 0x0A, 0x06, 0x03, 0x01}, /* 30 This is hp CCK base index */
+	/* Index31  -9.3dB */    {0x12, 0x12, 0x0F, 0x0D, 0x0A, 0x06, 0x03, 0x01},
+	/* Index32  -9.6dB */    {0x12, 0x11, 0x0F, 0x0D, 0x09, 0x06, 0x03, 0x01},
+	/* Index33  -9.9dB */    {0x11, 0x11, 0x0F, 0x0C, 0x09, 0x06, 0x03, 0x01},
+	/* Index34 -10.2dB */    {0x11, 0x11, 0x0E, 0x0C, 0x09, 0x06, 0x02, 0x01},
+	/* Index35 -10.5dB */    {0x10, 0x0F, 0x0E, 0x0B, 0x08, 0x05, 0x02, 0x01},
+	/* Index36 -10.8dB */    {0x10, 0x0F, 0x0D, 0x0B, 0x08, 0x05, 0x02, 0x01},
+	/* Index37 -11.1dB */    {0x0F, 0x0E, 0x0D, 0x0A, 0x08, 0x05, 0x02, 0x01},
+	/* Index38 -11.4dB */    {0x0E, 0x0E, 0x0C, 0x0A, 0x07, 0x05, 0x02, 0x01},
+	/* Index39 -11.7dB */    {0x0E, 0x0D, 0x0C, 0x0A, 0x07, 0x05, 0x02, 0x01},
+	/* Index40 -12  dB */    {0x0E, 0x0D, 0x0C, 0x0A, 0x07, 0x05, 0x02, 0x01},
+	/* Index41 -12.3dB */    {0x0D, 0x0D, 0x0B, 0x09, 0x07, 0x04, 0x02, 0x01},
+	/* Index42 -12.6dB */    {0x0D, 0x0C, 0x0B, 0x09, 0x07, 0x04, 0x02, 0x01},
+	/* Index43 -12.9dB */    {0x0C, 0x0C, 0x0A, 0x09, 0x06, 0x04, 0x02, 0x01},
+	/* Index44 -13.2dB */    {0x0C, 0x0B, 0x0A, 0x08, 0x06, 0x04, 0x02, 0x01},
+	/* Index45 -13.5dB */    {0x0B, 0x0B, 0x0A, 0x08, 0x06, 0x04, 0x02, 0x01},
+	/* Index46 -13.8dB */    {0x0B, 0x0B, 0x09, 0x08, 0x06, 0x04, 0x02, 0x01},
+	/* Index47 -14.1dB */    {0x0B, 0x0A, 0x09, 0x07, 0x06, 0x04, 0x02, 0x01},
+	/* Index48 -14.4dB */    {0x0A, 0x0A, 0x09, 0x07, 0x05, 0x03, 0x02, 0x01},
+	/* Index49 -14.7dB */    {0x0A, 0x0A, 0x08, 0x07, 0x05, 0x03, 0x01, 0x01},
+	/* Index50 -15  dB */    {0x0A, 0x09, 0x08, 0x07, 0x05, 0x03, 0x01, 0x01},
+	/* Index51 -15.3dB */    {0x09, 0x09, 0x08, 0x06, 0x05, 0x03, 0x01, 0x01},
+	/* Index52 -15.6dB */    {0x09, 0x09, 0x08, 0x06, 0x05, 0x03, 0x01, 0x01},
+	/* Index53 -15.9dB */    {0x09, 0x08, 0x07, 0x06, 0x04, 0x03, 0x01, 0x01}
+};
+u8 cck_swing_table_ch14_92e[CCK_TABLE_SIZE_92E][8] = {
+	/* Index0    0  dB */    {0x36, 0x34, 0x2E, 0x26, 0x00, 0x00, 0x00, 0x00},
+	/* Index1   -0.3dB */    {0x34, 0x32, 0x2C, 0x25, 0x00, 0x00, 0x00, 0x00},
+	/* Index2   -0.6dB */    {0x32, 0x30, 0x2B, 0x23, 0x00, 0x00, 0x00, 0x00},
+	/* Index3   -0.9dB */    {0x31, 0x2F, 0x29, 0x22, 0x00, 0x00, 0x00, 0x00},
+	/* Index4   -1.2dB */    {0x2F, 0x2D, 0x28, 0x21, 0x00, 0x00, 0x00, 0x00},
+	/* Index5   -1.5dB */    {0x2D, 0x2C, 0x27, 0x20, 0x00, 0x00, 0x00, 0x00},
+	/* Index6   -1.8dB */    {0x2C, 0x2A, 0x25, 0x1F, 0x00, 0x00, 0x00, 0x00},
+	/* Index7   -2.1dB */    {0x2A, 0x29, 0x24, 0x1E, 0x00, 0x00, 0x00, 0x00},
+	/* Index8   -2.4dB */    {0x29, 0x27, 0x23, 0x1D, 0x00, 0x00, 0x00, 0x00},
+	/* Index9   -2.7dB */    {0x27, 0x26, 0x22, 0x1C, 0x00, 0x00, 0x00, 0x00},
+	/* Index10  -3  dB */    {0x26, 0x25, 0x20, 0x1B, 0x00, 0x00, 0x00, 0x00},
+	/* Index11  -3.3dB */    {0x25, 0x23, 0x1F, 0x1A, 0x00, 0x00, 0x00, 0x00},
+	/* Index12  -3.6dB */    {0x24, 0x22, 0x1E, 0x19, 0x00, 0x00, 0x00, 0x00},
+	/* Index13  -3.9dB */    {0x22, 0x21, 0x1D, 0x18, 0x00, 0x00, 0x00, 0x00},
+	/* Index14  -4.2dB */    {0x21, 0x20, 0x1C, 0x17, 0x00, 0x00, 0x00, 0x00},
+	/* Index15  -4.5dB */    {0x20, 0x1F, 0x1B, 0x17, 0x00, 0x00, 0x00, 0x00},
+	/* Index16  -4.8dB */    {0x1F, 0x1E, 0x1A, 0x16, 0x00, 0x00, 0x00, 0x00},
+	/* Index17  -5.1dB */    {0x1E, 0x1D, 0x1A, 0x15, 0x00, 0x00, 0x00, 0x00},
+	/* Index18  -5.4dB */    {0x1D, 0x1C, 0x19, 0x14, 0x00, 0x00, 0x00, 0x00},
+	/* Index19  -5.7dB */    {0x1C, 0x1B, 0x18, 0x14, 0x00, 0x00, 0x00, 0x00},
+	/* Index20  -6  dB */     {0x1B, 0x1A, 0x17, 0x13, 0x00, 0x00, 0x00, 0x00},
+	/* Index21  -6.3dB */    {0x1A, 0x19, 0x16, 0x12, 0x00, 0x00, 0x00, 0x00},
+	/* Index22  -6.6dB */    {0x19, 0x18, 0x15, 0x12, 0x00, 0x00, 0x00, 0x00},
+	/* Index23  -6.9dB */    {0x18, 0x17, 0x15, 0x11, 0x00, 0x00, 0x00, 0x00},
+	/* Index24  -7.2dB */    {0x18, 0x17, 0x14, 0x11, 0x00, 0x00, 0x00, 0x00},
+	/* Index25  -7.5dB */    {0x17, 0x16, 0x13, 0x10, 0x00, 0x00, 0x00, 0x00},
+	/* Index26  -7.8dB */    {0x16, 0x15, 0x13, 0x0F, 0x00, 0x00, 0x00, 0x00},
+	/* Index27  -8.1dB */    {0x15, 0x14, 0x12, 0x0F, 0x00, 0x00, 0x00, 0x00},
+	/* Index28  -8.4dB */    {0x14, 0x14, 0x11, 0x0E, 0x00, 0x00, 0x00, 0x00},
+	/* Index29  -8.7dB */    {0x14, 0x13, 0x11, 0x0E, 0x00, 0x00, 0x00, 0x00},
+	/* Index30  -9  dB */    {0x13, 0x12, 0x10, 0x0D, 0x00, 0x00, 0x00, 0x00},
+	/* Index31  -9.3dB */    {0x12, 0x12, 0x0F, 0x0D, 0x00, 0x00, 0x00, 0x00},
+	/* Index32  -9.6dB */    {0x12, 0x11, 0x0F, 0x0D, 0x00, 0x00, 0x00, 0x00},
+	/* Index33  -9.9dB */    {0x11, 0x11, 0x0F, 0x0C, 0x00, 0x00, 0x00, 0x00},
+	/* Index34 -10.2dB */    {0x11, 0x11, 0x0E, 0x0C, 0x00, 0x00, 0x00, 0x00},
+	/* Index35 -10.5dB */    {0x10, 0x0F, 0x0E, 0x0B, 0x00, 0x00, 0x00, 0x00},
+	/* Index36 -10.8dB */    {0x10, 0x0F, 0x0D, 0x0B, 0x00, 0x00, 0x00, 0x00},
+	/* Index37 -11.1dB */    {0x0F, 0x0E, 0x0D, 0x0A, 0x00, 0x00, 0x00, 0x00},
+	/* Index38 -11.4dB */    {0x0E, 0x0E, 0x0C, 0x0A, 0x00, 0x00, 0x00, 0x00},
+	/* Index39 -11.7dB */    {0x0E, 0x0D, 0x0C, 0x0A, 0x00, 0x00, 0x00, 0x00},
+	/* Index40 -12  dB */    {0x0E, 0x0D, 0x0C, 0x0A, 0x00, 0x00, 0x00, 0x00},
+	/* Index41 -12.3dB */    {0x0D, 0x0D, 0x0B, 0x09, 0x00, 0x00, 0x00, 0x00},
+	/* Index42 -12.6dB */    {0x0D, 0x0C, 0x0B, 0x09, 0x00, 0x00, 0x00, 0x00},
+	/* Index43 -12.9dB */    {0x0C, 0x0C, 0x0A, 0x09, 0x00, 0x00, 0x00, 0x00},
+	/* Index44 -13.2dB */    {0x0C, 0x0B, 0x0A, 0x08, 0x00, 0x00, 0x00, 0x00},
+	/* Index45 -13.5dB */    {0x0B, 0x0B, 0x0A, 0x08, 0x00, 0x00, 0x00, 0x00},
+	/* Index46 -13.8dB */    {0x0B, 0x0B, 0x09, 0x08, 0x00, 0x00, 0x00, 0x00},
+	/* Index47 -14.1dB */    {0x0B, 0x0A, 0x09, 0x07, 0x00, 0x00, 0x00, 0x00},
+	/* Index48 -14.4dB */    {0x0A, 0x0A, 0x09, 0x07, 0x00, 0x00, 0x00, 0x00},
+	/* Index49 -14.7dB */    {0x0A, 0x0A, 0x08, 0x07, 0x00, 0x00, 0x00, 0x00},
+	/* Index50 -15  dB */    {0x0A, 0x09, 0x08, 0x07, 0x00, 0x00, 0x00, 0x00},
+	/* Index51 -15.3dB */    {0x09, 0x09, 0x08, 0x06, 0x00, 0x00, 0x00, 0x00},
+	/* Index52 -15.6dB */    {0x09, 0x09, 0x08, 0x06, 0x00, 0x00, 0x00, 0x00},
+	/* Index53 -15.9dB */    {0x09, 0x08, 0x07, 0x06, 0x00, 0x00, 0x00, 0x00}
+};
+#endif
+
+#if (RTL8814A_SUPPORT == 1 || RTL8822B_SUPPORT == 1)
+u32 tx_scaling_table_jaguar[TXSCALE_TABLE_SIZE] = {
+	0x081, /* 0,  -12.0dB */
+	0x088, /* 1,  -11.5dB */
+	0x090, /* 2,  -11.0dB */
+	0x099, /* 3,  -10.5dB */
+	0x0A2, /* 4,  -10.0dB */
+	0x0AC, /* 5,  -9.5dB */
+	0x0B6, /* 6,  -9.0dB */
+	0x0C0, /* 7,  -8.5dB */
+	0x0CC, /* 8,  -8.0dB */
+	0x0D8, /* 9,  -7.5dB */
+	0x0E5, /* 10, -7.0dB */
+	0x0F2, /* 11, -6.5dB */
+	0x101, /* 12, -6.0dB */
+	0x110, /* 13, -5.5dB */
+	0x120, /* 14, -5.0dB */
+	0x131, /* 15, -4.5dB */
+	0x143, /* 16, -4.0dB */
+	0x156, /* 17, -3.5dB */
+	0x16A, /* 18, -3.0dB */
+	0x180, /* 19, -2.5dB */
+	0x197, /* 20, -2.0dB */
+	0x1AF, /* 21, -1.5dB */
+	0x1C8, /* 22, -1.0dB */
+	0x1E3, /* 23, -0.5dB */
+	0x200, /* 24, +0  dB */
+	0x21E, /* 25, +0.5dB */
+	0x23E, /* 26, +1.0dB */
+	0x261, /* 27, +1.5dB */
+	0x285, /* 28, +2.0dB */
+	0x2AB, /* 29, +2.5dB */
+	0x2D3, /* 30, +3.0dB */
+	0x2FE, /* 31, +3.5dB */
+	0x32B, /* 32, +4.0dB */
+	0x35C, /* 33, +4.5dB */
+	0x38E, /* 34, +5.0dB */
+	0x3C4, /* 35, +5.5dB */
+	0x3FE  /* 36, +6.0dB */
+};
+#elif(ODM_IC_11AC_SERIES_SUPPORT)
+u32 ofdm_swing_table_8812[OFDM_TABLE_SIZE_8812] = {
+	0x3FE, /* 0,  (6dB) */
+	0x3C4, /* 1,  (5.5dB) */
+	0x38E, /* 2,  (5dB) */
+	0x35C, /* 3,  (4.5dB) */
+	0x32B, /* 4,  (4dB) */
+	0x2FE, /* 5,  (3.5dB) */
+	0x2D3, /* 6,  (3dB) */
+	0x2AB, /* 7,  (2.5dB) */
+	0x285, /* 8,  (2dB) */
+	0x261, /* 9,  (1.5dB */
+	0x23E, /* 10, (1dB) */
+	0x21E, /* 11, (0.5dB) */
+	0x200, /* 12, (0dB)		8814 int PA 2G default */
+	0x1E3, /* 13, (-0.5dB) */
+	0x1C8, /* 14, (-1dB) */
+	0x1AF, /* 15, (-1.5dB) */
+	0x197, /* 16, (-2dB) */
+	0x180, /* 17, (-2.5dB) */
+	0x16A, /* 18, (-3dB)		8812 / 8814 int PA 5G / 8814 ext PA 2G5G default */
+	0x156, /* 19, (-3.5dB) */
+	0x143, /* 20, (-4dB)		8812 HP default */
+	0x131, /* 21, (-4.5dB) */
+	0x120, /* 22, (-5dB) */
+	0x110, /* 23, (-5.5dB) */
+	0x101, /* 24, (-6dB) */
+	0x0F2, /* 25, (-6.5dB) */
+	0x0E5, /* 26, (-7dB) */
+	0x0D8, /* 27, (-7.5dB) */
+	0x0CC, /* 28, (-8dB) */
+	0x0C0, /* 29, (-8.5dB) */
+	0x0B6, /* 30, (-9dB) */
+	0x0AC, /* 31, (-9.5dB) */
+	0x0A2, /* 32, (-10dB) */
+	0x099, /* 33, (-10.5dB) */
+	0x090, /* 34, (-11dB) */
+	0x088, /* 35, (-11.5dB) */
+	0x081, /* 36, (-12dB) */
+	0x079, /* 37, (-12.5dB) */
+	0x072, /* 38, (-13dB) */
+	0x06c, /* 39, (-13.5dB) */
+	0x066, /* 40, (-14dB) */
+	0x060, /* 41, (-14.5dB) */
+	0x05B  /* 42, (-15dB) */
+};
+#endif
+
+u32 cck_swing_table_ch1_ch14_8723d[CCK_TABLE_SIZE_8723D] = {
+	0x0CD,
+	0x0D9,
+	0x0E6,
+	0x0F3,
+	0x102,
+	0x111,
+	0x121,
+	0x132,
+	0x144,
+	0x158,
+	0x16C,
+	0x182,
+	0x198,
+	0x1B1,
+	0x1CA,
+	0x1E5,
+	0x202,
+	0x221,
+	0x241,
+	0x263,
+	0x287,
+	0x2AE,
+	0x2D6,
+	0x301,
+	0x32F,
+	0x35F,
+	0x392,
+	0x3C9,
+	0x402,
+	0x43F,
+	0x47F,
+	0x4C3,
+	0x50C,
+	0x558,
+	0x5A9,
+	0x5FF,
+	0x65A,
+	0x6BA,
+	0x720,
+	0x78C,
+	0x7FF,
+};
+/* JJ ADD 20161014 */
+u32 cck_swing_table_ch1_ch14_8710b[CCK_TABLE_SIZE_8710B] = {
+	0x0CD,
+	0x0D9,
+	0x0E6,
+	0x0F3,
+	0x102,
+	0x111,
+	0x121,
+	0x132,
+	0x144,
+	0x158,
+	0x16C,
+	0x182,
+	0x198,
+	0x1B1,
+	0x1CA,
+	0x1E5,
+	0x202,
+	0x221,
+	0x241,
+	0x263,
+	0x287,
+	0x2AE,
+	0x2D6,
+	0x301,
+	0x32F,
+	0x35F,
+	0x392,
+	0x3C9,
+	0x402,
+	0x43F,
+	0x47F,
+	0x4C3,
+	0x50C,
+	0x558,
+	0x5A9,
+	0x5FF,
+	0x65A,
+	0x6BA,
+	0x720,
+	0x78C,
+	0x7FF,
+};
+
+
+/* #endif */
+/* 3============================================================
+ * 3 Tx Power Tracking
+ * 3============================================================ */
+
+void
+odm_txpowertracking_init(
+	void		*p_dm_void
+)
+{
+	struct PHY_DM_STRUCT		*p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
+#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
+	if (!(p_dm_odm->support_ic_type & (ODM_RTL8814A | ODM_RTL8822B | ODM_IC_11N_SERIES)))
+		return;
+#endif
+
+	odm_txpowertracking_thermal_meter_init(p_dm_odm);
+}
+
+
+u8
+get_swing_index(
+	void		*p_dm_void
+)
+{
+	struct PHY_DM_STRUCT		*p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
+	u8			i = 0, bb_swing_mask = 0;
+	u32			bb_swing = 0;
+	u32			swing_table_size = 0;
+	u32			*p_swing_table = 0;
+	struct rtl8192cd_priv	*priv = p_dm_odm->priv;
+
+#if (RTL8197F_SUPPORT == 1)
+	if (GET_CHIP_VER(priv) == VERSION_8197F) {
+		bb_swing = phy_query_bb_reg(priv, REG_OFDM_0_XA_TX_IQ_IMBALANCE, MASKOFDM_D);
+		p_swing_table = ofdm_swing_table_new;
+		swing_table_size = OFDM_TABLE_SIZE_92D;
+		bb_swing_mask = 22;
+	}
+#endif
+
+#if (RTL8822B_SUPPORT == 1)
+	if (GET_CHIP_VER(priv) == VERSION_8822B) {
+		bb_swing = phy_query_bb_reg(priv, REG_A_TX_SCALE_JAGUAR, 0xFFE00000);
+		p_swing_table = tx_scaling_table_jaguar;
+		swing_table_size = TXSCALE_TABLE_SIZE;
+		bb_swing_mask = 0;
+	}
+#endif
+
+	for (i = 0; i < swing_table_size - 1; i++) {
+		u32 table_value = p_swing_table[i] >> bb_swing_mask;
+
+		if (bb_swing == table_value)
+			break;
+	}
+
+	ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("bb_swing=0x%x bbswing_index=%d\n", bb_swing, i));
+
+
+	return i;
+}
+
+
+void
+odm_txpowertracking_thermal_meter_init(
+	void		*p_dm_void
+)
+{
+	struct PHY_DM_STRUCT		*p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
+	struct odm_rf_calibration_structure	*p_rf_calibrate_info = &(p_dm_odm->rf_calibrate_info);
+	struct rtl8192cd_priv		*priv = p_dm_odm->priv;
+	u8 p;
+	u8 default_swing_index;
+#if (RTL8197F_SUPPORT == 1 || RTL8822B_SUPPORT == 1)
+	if ((GET_CHIP_VER(priv) == VERSION_8197F) || (GET_CHIP_VER(priv) == VERSION_8822B))
+		default_swing_index = get_swing_index(p_dm_odm);
+#endif
+
+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
+	struct _ADAPTER		*adapter = p_dm_odm->adapter;
+	PMGNT_INFO	p_mgnt_info = &adapter->MgntInfo;
+	HAL_DATA_TYPE		*p_hal_data = GET_HAL_DATA(adapter);
+
+	p_mgnt_info->is_txpowertracking = true;
+	p_hal_data->tx_powercount       = 0;
+	p_hal_data->is_txpowertracking_init = false;
+
+	if (p_dm_odm->mp_mode == false)
+		p_hal_data->txpowertrack_control = true;
+	ODM_RT_TRACE(p_dm_odm, COMP_POWER_TRACKING, DBG_LOUD, ("p_mgnt_info->is_txpowertracking = %d\n", p_mgnt_info->is_txpowertracking));
+#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
+#ifdef CONFIG_RTL8188E
+	{
+		p_dm_odm->rf_calibrate_info.is_txpowertracking = _TRUE;
+		p_dm_odm->rf_calibrate_info.tx_powercount = 0;
+		p_dm_odm->rf_calibrate_info.is_txpowertracking_init = _FALSE;
+
+		if (p_dm_odm->mp_mode == false)
+			p_dm_odm->rf_calibrate_info.txpowertrack_control = _TRUE;
+
+		MSG_8192C("p_dm_odm txpowertrack_control = %d\n", p_dm_odm->rf_calibrate_info.txpowertrack_control);
+	}
+#else
+	{
+		struct _ADAPTER		*adapter = p_dm_odm->adapter;
+		HAL_DATA_TYPE	*p_hal_data = GET_HAL_DATA(adapter);
+		struct dm_priv	*pdmpriv = &p_hal_data->dmpriv;
+
+		/* if(IS_HARDWARE_TYPE_8192C(p_hal_data)) */
+		{
+			pdmpriv->is_txpowertracking = _TRUE;
+			pdmpriv->tx_powercount = 0;
+			pdmpriv->is_txpowertracking_init = _FALSE;
+
+			if (p_dm_odm->mp_mode == false)		/* for mp driver, turn off txpwrtracking as default */
+				pdmpriv->txpowertrack_control = _TRUE;
+
+		}
+		MSG_8192C("pdmpriv->txpowertrack_control = %d\n", pdmpriv->txpowertrack_control);
+
+	}
+#endif/* endif (CONFIG_RTL8188E==1) */
+#elif (DM_ODM_SUPPORT_TYPE & (ODM_AP))
+
+#ifdef RTL8188E_SUPPORT
+	{
+		p_dm_odm->rf_calibrate_info.is_txpowertracking = _TRUE;
+		p_dm_odm->rf_calibrate_info.tx_powercount = 0;
+		p_dm_odm->rf_calibrate_info.is_txpowertracking_init = _FALSE;
+		p_dm_odm->rf_calibrate_info.txpowertrack_control = _TRUE;
+		p_dm_odm->rf_calibrate_info.tm_trigger = 0;
+	}
+#endif
+#endif
+
+	p_dm_odm->rf_calibrate_info.txpowertrack_control = true;
+	p_dm_odm->rf_calibrate_info.delta_power_index = 0;
+	p_dm_odm->rf_calibrate_info.delta_power_index_last = 0;
+	p_dm_odm->rf_calibrate_info.power_index_offset = 0;
+	p_dm_odm->rf_calibrate_info.thermal_value = 0;
+	p_rf_calibrate_info->default_ofdm_index = 28;
+
+#if (RTL8197F_SUPPORT == 1)
+	if (GET_CHIP_VER(priv) == VERSION_8197F) {
+		p_rf_calibrate_info->default_ofdm_index = (default_swing_index >= (OFDM_TABLE_SIZE_92D - 1)) ? 30 : default_swing_index;
+		p_rf_calibrate_info->default_cck_index = 28;
+	}
+#endif
+
+#if (RTL8822B_SUPPORT == 1)
+	if (GET_CHIP_VER(priv) == VERSION_8822B) {
+		p_rf_calibrate_info->default_ofdm_index = (default_swing_index >= (TXSCALE_TABLE_SIZE - 1)) ? 24 : default_swing_index;
+		p_rf_calibrate_info->default_cck_index = 20;
+	}
+#endif
+
+
+#if RTL8188E_SUPPORT
+	p_rf_calibrate_info->default_cck_index = 20;	/* -6 dB */
+#elif RTL8192E_SUPPORT
+	p_rf_calibrate_info->default_cck_index = 8;	/* -12 dB */
+#endif
+	p_rf_calibrate_info->bb_swing_idx_ofdm_base = p_rf_calibrate_info->default_ofdm_index;
+	p_rf_calibrate_info->bb_swing_idx_cck_base = p_rf_calibrate_info->default_cck_index;
+	p_dm_odm->rf_calibrate_info.CCK_index = p_rf_calibrate_info->default_cck_index;
+
+	for (p = 0; p < MAX_RF_PATH; p++) {
+		p_dm_odm->rf_calibrate_info.OFDM_index[p] = p_rf_calibrate_info->default_ofdm_index;
+		p_rf_calibrate_info->bb_swing_idx_ofdm[p] = p_rf_calibrate_info->default_ofdm_index;
+		p_rf_calibrate_info->kfree_offset[p] = 0;	/* for 8814 kfree*/
+	}
+	p_rf_calibrate_info->bb_swing_idx_cck = p_rf_calibrate_info->default_cck_index;
+
+	ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("p_rf_calibrate_info->default_ofdm_index=%d p_rf_calibrate_info->default_cck_index=%d\n", p_rf_calibrate_info->default_ofdm_index, p_rf_calibrate_info->default_cck_index));
+
+
+}
+
+
+void
+odm_txpowertracking_check(
+	void		*p_dm_void
+)
+{
+	/*  */
+	/* For AP/ADSL use struct rtl8192cd_priv* */
+	/* For CE/NIC use struct _ADAPTER* */
+	/*  */
+	struct PHY_DM_STRUCT		*p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
+
+
+
+	if (!(p_dm_odm->support_ability & ODM_RF_TX_PWR_TRACK))
+		return;
+
+	/*  */
+	/* 2011/09/29 MH In HW integration first stage, we provide 4 different handle to operate */
+	/* at the same time. In the stage2/3, we need to prive universal interface and merge all */
+	/* HW dynamic mechanism. */
+	/*  */
+	switch	(p_dm_odm->support_platform) {
+	case	ODM_WIN:
+		odm_txpowertracking_check_mp(p_dm_odm);
+		break;
+
+	case	ODM_CE:
+		odm_txpowertracking_check_ce(p_dm_odm);
+		break;
+
+	case	ODM_AP:
+		odm_txpowertracking_check_ap(p_dm_odm);
+		break;
+
+	case	ODM_ADSL:
+		/*odm_DIGAP(p_dm_odm);*/
+		break;
+	}
+
+}
+
+void
+odm_txpowertracking_check_ce(
+	void		*p_dm_void
+)
+{
+#if (DM_ODM_SUPPORT_TYPE == ODM_CE)
+	struct PHY_DM_STRUCT		*p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
+	struct _ADAPTER	*adapter = p_dm_odm->adapter;
+
+#if (RTL8188E_SUPPORT == 1)
+
+	/* if(!p_mgnt_info->is_txpowertracking || (!pdmpriv->txpowertrack_control && pdmpriv->is_ap_kdone)) */
+	if (!(p_dm_odm->support_ability & ODM_RF_TX_PWR_TRACK))
+		return;
+
+	if (!p_dm_odm->rf_calibrate_info.tm_trigger) {	/* at least delay 1 sec */
+		/* p_hal_data->TxPowerCheckCnt++;	 */ /* cosa add for debug */
+		odm_set_rf_reg(p_dm_odm, RF_PATH_A, RF_T_METER, RFREGOFFSETMASK, 0x60);
+		/* DBG_8192C("Trigger 92C Thermal Meter!!\n"); */
+
+		p_dm_odm->rf_calibrate_info.tm_trigger = 1;
+		return;
+
+	} else {
+		/* DBG_8192C("Schedule TxPowerTracking direct call!!\n"); */
+		odm_txpowertracking_callback_thermal_meter_8188e(adapter);
+		p_dm_odm->rf_calibrate_info.tm_trigger = 0;
+	}
+#endif
+
+#endif
+}
+
+void
+odm_txpowertracking_check_mp(
+	void		*p_dm_void
+)
+{
+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
+	struct PHY_DM_STRUCT		*p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
+	struct _ADAPTER	*adapter = p_dm_odm->adapter;
+
+	if (odm_check_power_status(adapter) == false)
+		return;
+
+	if (!adapter->is_slave_of_dmsp || adapter->dual_mac_smart_concurrent == false)
+		odm_txpowertracking_thermal_meter_check(adapter);
+#endif
+
+}
+
+
+void
+odm_txpowertracking_check_ap(
+	void		*p_dm_void
+)
+{
+	struct PHY_DM_STRUCT		*p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
+#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
+	struct rtl8192cd_priv	*priv		= p_dm_odm->priv;
+
+#if ((RTL8188E_SUPPORT == 1) || (RTL8192E_SUPPORT == 1) || (RTL8812A_SUPPORT == 1) || (RTL8881A_SUPPORT == 1) || (RTL8814A_SUPPORT == 1) || (RTL8197F_SUPPORT == 1))
+	if (p_dm_odm->support_ic_type & (ODM_RTL8188E | ODM_RTL8192E | ODM_RTL8812 | ODM_RTL8881A | ODM_RTL8814A | ODM_RTL8197F | ODM_RTL8822B))
+		odm_txpowertracking_callback_thermal_meter(p_dm_odm);
+	else
+#endif
+	{
+	}
+#endif
+
+}
+
+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
+
+void
+odm_txpowertracking_thermal_meter_check(
+	struct _ADAPTER		*adapter
+)
+{
+#ifndef AP_BUILD_WORKAROUND
+#if (HAL_CODE_BASE == RTL8192_C)
+	PMGNT_INFO		p_mgnt_info = &adapter->MgntInfo;
+	/* HAL_DATA_TYPE			*p_hal_data = GET_HAL_DATA(adapter); */
+	static u8			tm_trigger = 0;
+	/* u8					TxPowerCheckCnt = 5;	 */ /* 10 sec */
+
+	if (!p_mgnt_info->is_txpowertracking /*|| (!p_hal_data->txpowertrack_control && p_hal_data->is_ap_kdone)*/)
+		return;
+
+	if (!tm_trigger) {	/* at least delay 1 sec */
+		if (IS_HARDWARE_TYPE_8188E(adapter) || IS_HARDWARE_TYPE_8812(adapter))
+			phy_set_rf_reg(adapter, RF_PATH_A, RF_T_METER_88E, BIT(17) | BIT(16), 0x03);
+		else
+			phy_set_rf_reg(adapter, RF_PATH_A, RF_T_METER, RFREGOFFSETMASK, 0x60);
+		RT_TRACE(COMP_POWER_TRACKING, DBG_LOUD, ("Trigger 92C Thermal Meter!!\n"));
+
+		tm_trigger = 1;
+		return;
+	} else {
+		RT_TRACE(COMP_POWER_TRACKING, DBG_LOUD, ("Schedule TxPowerTracking direct call!!\n"));
+		odm_txpowertracking_direct_call(adapter); /* Using direct call is instead, added by Roger, 2009.06.18. */
+		tm_trigger = 0;
+	}
+#endif
+#endif
+}
+
+#endif
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/phydm_powertracking_ap.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/phydm_powertracking_ap.h
--- linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/phydm_powertracking_ap.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/phydm_powertracking_ap.h	2020-04-10 16:35:06.826660535 +0300
@@ -0,0 +1,355 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
+ *
+ *
+ ******************************************************************************/
+
+#ifndef	__PHYDMPOWERTRACKING_H__
+#define    __PHYDMPOWERTRACKING_H__
+
+#define POWRTRACKING_VERSION	"1.1"
+
+#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
+	#ifdef RTK_AC_SUPPORT
+		#define ODM_IC_11AC_SERIES_SUPPORT		1
+	#else
+		#define ODM_IC_11AC_SERIES_SUPPORT		0
+	#endif
+#else
+	#define ODM_IC_11AC_SERIES_SUPPORT		1
+#endif
+
+#define		DPK_DELTA_MAPPING_NUM	13
+#define		index_mapping_HP_NUM	15
+#define		DELTA_SWINGIDX_SIZE     30
+#define		DELTA_SWINTSSI_SIZE     61
+#define		BAND_NUM				3
+#define		MAX_RF_PATH	4
+#define		TXSCALE_TABLE_SIZE		37
+#define		CCK_TABLE_SIZE_8723D		41
+/* JJ ADD 20161014 */
+#define		CCK_TABLE_SIZE_8710B		41
+
+#define IQK_MAC_REG_NUM		4
+#define IQK_ADDA_REG_NUM		16
+#define IQK_BB_REG_NUM_MAX	10
+
+#define IQK_BB_REG_NUM		9
+
+#define HP_THERMAL_NUM		8
+
+#define AVG_THERMAL_NUM		8
+#define iqk_matrix_reg_num	8
+/* #define IQK_MATRIX_SETTINGS_NUM	1+24+21 */
+#define IQK_MATRIX_SETTINGS_NUM	(14+24+21) /* Channels_2_4G_NUM + Channels_5G_20M_NUM + Channels_5G */
+
+#if !defined(_OUTSRC_COEXIST)
+	#define	OFDM_TABLE_SIZE_92D	43
+	#define	OFDM_TABLE_SIZE	37
+	#define	CCK_TABLE_SIZE		33
+	#define	CCK_TABLE_SIZE_88F	21
+
+
+
+	/* #define	OFDM_TABLE_SIZE_92E	54 */
+	/* #define	CCK_TABLE_SIZE_92E	54 */
+	extern	u32 ofdm_swing_table[OFDM_TABLE_SIZE_92D];
+	extern	u8 cck_swing_table_ch1_ch13[CCK_TABLE_SIZE][8];
+	extern	u8 cck_swing_table_ch14[CCK_TABLE_SIZE][8];
+
+
+	extern	u32 ofdm_swing_table_new[OFDM_TABLE_SIZE_92D];
+	extern	u8 cck_swing_table_ch1_ch13_new[CCK_TABLE_SIZE][8];
+	extern	u8 cck_swing_table_ch14_new[CCK_TABLE_SIZE][8];
+	extern	u8 cck_swing_table_ch1_ch14_88f[CCK_TABLE_SIZE_88F][16];
+	extern	u8 cck_swing_table_ch1_ch13_88f[CCK_TABLE_SIZE_88F][16];
+	extern	u8 cck_swing_table_ch14_88f[CCK_TABLE_SIZE_88F][16];
+
+#endif
+
+#define	ODM_OFDM_TABLE_SIZE	37
+#define	ODM_CCK_TABLE_SIZE		33
+/* <20140613, YuChen> In case fail to read TxPowerTrack.txt, we use the table of 88E as the default table. */
+extern u8 delta_swing_table_idx_2ga_p_default[DELTA_SWINGIDX_SIZE];
+extern u8 delta_swing_table_idx_2ga_n_default[DELTA_SWINGIDX_SIZE];
+
+static u8 delta_swing_table_idx_2ga_p_8188e[] = {0, 0, 0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 4,  4,  4,  4,  4,  4,  5,  5,  7,  7,  8,  8,  8,  9,  9,  9,  9,  9};
+static u8 delta_swing_table_idx_2ga_n_8188e[] = {0, 0, 0, 2, 2, 3, 3, 4, 4, 4, 4, 5, 5,  6,  6,  7,  7,  7,  7,  8,  8,  9,  9, 10, 10, 10, 11, 11, 11, 11};
+
+/* extern	u32 ofdm_swing_table_92e[OFDM_TABLE_SIZE_92E];
+ * extern	u8 cck_swing_table_ch1_ch13_92e[CCK_TABLE_SIZE_92E][8];
+ * extern	u8 cck_swing_table_ch14_92e[CCK_TABLE_SIZE_92E][8]; */
+
+#ifdef CONFIG_WLAN_HAL_8192EE
+	#define	OFDM_TABLE_SIZE_92E	54
+	#define	CCK_TABLE_SIZE_92E	54
+	extern	u32 ofdm_swing_table_92e[OFDM_TABLE_SIZE_92E];
+	extern	u8 cck_swing_table_ch1_ch13_92e[CCK_TABLE_SIZE_92E][8];
+	extern	u8 cck_swing_table_ch14_92e[CCK_TABLE_SIZE_92E][8];
+#endif
+
+#define	OFDM_TABLE_SIZE_8812	43
+#define	AVG_THERMAL_NUM_8812	4
+
+#if (RTL8814A_SUPPORT == 1 || RTL8822B_SUPPORT == 1)
+	extern u32 tx_scaling_table_jaguar[TXSCALE_TABLE_SIZE];
+	#elif(ODM_IC_11AC_SERIES_SUPPORT)
+	extern unsigned int ofdm_swing_table_8812[OFDM_TABLE_SIZE_8812];
+#endif
+
+extern u32 cck_swing_table_ch1_ch14_8723d[CCK_TABLE_SIZE_8723D];
+/* JJ ADD 20161014 */
+extern u32 cck_swing_table_ch1_ch14_8710b[CCK_TABLE_SIZE_8710B];
+
+#define dm_check_txpowertracking	odm_txpowertracking_check
+
+struct _IQK_MATRIX_REGS_SETTING {
+	boolean	is_iqk_done;
+	s32		value[1][iqk_matrix_reg_num];
+};
+
+struct odm_rf_calibration_structure {
+	/* for tx power tracking */
+
+	u32	rega24; /* for TempCCK */
+	s32	rege94;
+	s32	rege9c;
+	s32	regeb4;
+	s32	regebc;
+
+	/* u8 is_txpowertracking; */
+	u8	tx_powercount;
+	boolean is_txpowertracking_init;
+	boolean is_txpowertracking;
+	u8  	txpowertrack_control; /* for mp mode, turn off txpwrtracking as default */
+	u8	tm_trigger;
+	u8  	internal_pa_5g[2];	/* pathA / pathB */
+
+	u8  	thermal_meter[2];    /* thermal_meter, index 0 for RFIC0, and 1 for RFIC1 */
+	u8	thermal_value;
+	u8	thermal_value_lck;
+	u8	thermal_value_iqk;
+	s8  	thermal_value_delta; /* delta of thermal_value and efuse thermal */
+	u8	thermal_value_dpk;
+	u8	thermal_value_avg[AVG_THERMAL_NUM];
+	u8	thermal_value_avg_index;
+	u8	thermal_value_rx_gain;
+	u8	thermal_value_crystal;
+	u8	thermal_value_dpk_store;
+	u8	thermal_value_dpk_track;
+	boolean	txpowertracking_in_progress;
+	boolean	is_dpk_enable;
+
+	boolean	is_reloadtxpowerindex;
+	u8	is_rf_pi_enable;
+	u32 	txpowertracking_callback_cnt; /* cosa add for debug */
+
+	u8	is_cck_in_ch14;
+	u8	CCK_index;
+	u8	OFDM_index[MAX_RF_PATH];
+	s8	power_index_offset;
+	s8	delta_power_index;
+	s8	delta_power_index_last;
+	boolean is_tx_power_changed;
+
+	u8	thermal_value_hp[HP_THERMAL_NUM];
+	u8	thermal_value_hp_index;
+	struct _IQK_MATRIX_REGS_SETTING iqk_matrix_reg_setting[IQK_MATRIX_SETTINGS_NUM];
+	u8	delta_lck;
+	u8  delta_swing_table_idx_2g_cck_a_p[DELTA_SWINGIDX_SIZE];
+	u8  delta_swing_table_idx_2g_cck_a_n[DELTA_SWINGIDX_SIZE];
+	u8  delta_swing_table_idx_2g_cck_b_p[DELTA_SWINGIDX_SIZE];
+	u8  delta_swing_table_idx_2g_cck_b_n[DELTA_SWINGIDX_SIZE];
+	u8  delta_swing_table_idx_2g_cck_c_p[DELTA_SWINGIDX_SIZE];
+	u8  delta_swing_table_idx_2g_cck_c_n[DELTA_SWINGIDX_SIZE];
+	u8  delta_swing_table_idx_2g_cck_d_p[DELTA_SWINGIDX_SIZE];
+	u8  delta_swing_table_idx_2g_cck_d_n[DELTA_SWINGIDX_SIZE];
+	u8  delta_swing_table_idx_2ga_p[DELTA_SWINGIDX_SIZE];
+	u8  delta_swing_table_idx_2ga_n[DELTA_SWINGIDX_SIZE];
+	u8  delta_swing_table_idx_2gb_p[DELTA_SWINGIDX_SIZE];
+	u8  delta_swing_table_idx_2gb_n[DELTA_SWINGIDX_SIZE];
+	u8  delta_swing_table_idx_2gc_p[DELTA_SWINGIDX_SIZE];
+	u8  delta_swing_table_idx_2gc_n[DELTA_SWINGIDX_SIZE];
+	u8  delta_swing_table_idx_2gd_p[DELTA_SWINGIDX_SIZE];
+	u8  delta_swing_table_idx_2gd_n[DELTA_SWINGIDX_SIZE];
+	u8  delta_swing_table_idx_5ga_p[BAND_NUM][DELTA_SWINGIDX_SIZE];
+	u8  delta_swing_table_idx_5ga_n[BAND_NUM][DELTA_SWINGIDX_SIZE];
+	u8  delta_swing_table_idx_5gb_p[BAND_NUM][DELTA_SWINGIDX_SIZE];
+	u8  delta_swing_table_idx_5gb_n[BAND_NUM][DELTA_SWINGIDX_SIZE];
+	u8  delta_swing_table_idx_5gc_p[BAND_NUM][DELTA_SWINGIDX_SIZE];
+	u8  delta_swing_table_idx_5gc_n[BAND_NUM][DELTA_SWINGIDX_SIZE];
+	u8  delta_swing_table_idx_5gd_p[BAND_NUM][DELTA_SWINGIDX_SIZE];
+	u8  delta_swing_table_idx_5gd_n[BAND_NUM][DELTA_SWINGIDX_SIZE];
+	u8  delta_swing_tssi_table_2g_cck_a[DELTA_SWINTSSI_SIZE];
+	u8  delta_swing_tssi_table_2g_cck_b[DELTA_SWINTSSI_SIZE];
+	u8  delta_swing_tssi_table_2g_cck_c[DELTA_SWINTSSI_SIZE];
+	u8  delta_swing_tssi_table_2g_cck_d[DELTA_SWINTSSI_SIZE];
+	u8  delta_swing_tssi_table_2ga[DELTA_SWINTSSI_SIZE];
+	u8  delta_swing_tssi_table_2gb[DELTA_SWINTSSI_SIZE];
+	u8  delta_swing_tssi_table_2gc[DELTA_SWINTSSI_SIZE];
+	u8  delta_swing_tssi_table_2gd[DELTA_SWINTSSI_SIZE];
+	u8  delta_swing_tssi_table_5ga[BAND_NUM][DELTA_SWINTSSI_SIZE];
+	u8  delta_swing_tssi_table_5gb[BAND_NUM][DELTA_SWINTSSI_SIZE];
+	u8  delta_swing_tssi_table_5gc[BAND_NUM][DELTA_SWINTSSI_SIZE];
+	u8  delta_swing_tssi_table_5gd[BAND_NUM][DELTA_SWINTSSI_SIZE];
+	u8  delta_swing_table_idx_2ga_p_8188e[DELTA_SWINGIDX_SIZE];
+	u8  delta_swing_table_idx_2ga_n_8188e[DELTA_SWINGIDX_SIZE];
+
+	u8			bb_swing_idx_ofdm[MAX_RF_PATH];
+	u8			bb_swing_idx_ofdm_current;
+#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
+	u8			bb_swing_idx_ofdm_base[MAX_RF_PATH];
+#else
+	u8			bb_swing_idx_ofdm_base;
+#endif
+	boolean			bb_swing_flag_ofdm;
+	u8			bb_swing_idx_cck;
+	u8			bb_swing_idx_cck_current;
+	u8			bb_swing_idx_cck_base;
+	u8			default_ofdm_index;
+	u8			default_cck_index;
+	boolean			bb_swing_flag_cck;
+
+	s8			absolute_ofdm_swing_idx[MAX_RF_PATH];
+	s8			remnant_ofdm_swing_idx[MAX_RF_PATH];
+	s8			absolute_cck_swing_idx[MAX_RF_PATH];
+	s8			remnant_cck_swing_idx;
+	s8			modify_tx_agc_value;       /*Remnat compensate value at tx_agc */
+	boolean			modify_tx_agc_flag_path_a;
+	boolean			modify_tx_agc_flag_path_b;
+	boolean			modify_tx_agc_flag_path_c;
+	boolean			modify_tx_agc_flag_path_d;
+	boolean			modify_tx_agc_flag_path_a_cck;
+
+	s8			kfree_offset[MAX_RF_PATH];
+
+	/* -------------------------------------------------------------------- */
+
+	/* for IQK */
+	u32	regc04;
+	u32	reg874;
+	u32	regc08;
+	u32	regb68;
+	u32	regb6c;
+	u32	reg870;
+	u32	reg860;
+	u32	reg864;
+
+	boolean	is_iqk_initialized;
+	boolean is_lck_in_progress;
+	boolean	is_antenna_detected;
+	boolean	is_need_iqk;
+	boolean	is_iqk_in_progress;
+	boolean	is_iqk_pa_off;
+	u8	delta_iqk;
+	u32	ADDA_backup[IQK_ADDA_REG_NUM];
+	u32	IQK_MAC_backup[IQK_MAC_REG_NUM];
+	u32	IQK_BB_backup_recover[9];
+	u32	IQK_BB_backup[IQK_BB_REG_NUM];
+	u32	tx_iqc_8723b[2][3][2]; /* { {S1: 0xc94, 0xc80, 0xc4c} , {S0: 0xc9c, 0xc88, 0xc4c}} */
+	u32	rx_iqc_8723b[2][2][2]; /* { {S1: 0xc14, 0xca0} ,           {S0: 0xc14, 0xca0}} */
+	u32	tx_iqc_8703b[3][2];	/* { {S1: 0xc94, 0xc80, 0xc4c} , {S0: 0xc9c, 0xc88, 0xc4c}}*/
+	u32	rx_iqc_8703b[2][2];	/* { {S1: 0xc14, 0xca0} ,           {S0: 0xc14, 0xca0}}*/
+
+	u64	iqk_start_time;
+	u64	iqk_total_progressing_time;
+	u64	iqk_progressing_time;
+	u32  lok_result;
+	u8	iqk_step;
+	u8	kcount;
+	u8	retry_count[4][2]; /* [4]: path ABCD, [2] TXK, RXK */
+	boolean	is_mp_mode;
+
+	/* for APK */
+	u32 	ap_koutput[2][2]; /* path A/B; output1_1a/output1_2a */
+	u8	is_ap_kdone;
+	u8	is_apk_thermal_meter_ignore;
+	u8	is_dp_done;
+	u8	is_dp_path_aok;
+	u8	is_dp_path_bok;
+
+	/*Add by Yuchen for Kfree Phydm*/
+	u8			reg_rf_kfree_enable;	/*for registry*/
+	u8			rf_kfree_enable;		/*for efuse enable check*/
+	u32	tx_lok[2];
+};
+
+void
+odm_txpowertracking_check_ap(
+	void		*p_dm_void
+);
+
+void
+odm_txpowertracking_check(
+	void		*p_dm_void
+);
+
+
+void
+odm_txpowertracking_thermal_meter_init(
+	void		*p_dm_void
+);
+
+void
+odm_txpowertracking_init(
+	void		*p_dm_void
+);
+
+void
+odm_txpowertracking_check_mp(
+	void		*p_dm_void
+);
+
+
+void
+odm_txpowertracking_check_ce(
+	void		*p_dm_void
+);
+
+
+#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN))
+
+void
+odm_txpowertracking_callback_thermal_meter92c(
+	struct _ADAPTER	*adapter
+);
+
+void
+odm_txpowertracking_callback_rx_gain_thermal_meter92d(
+	struct _ADAPTER	*adapter
+);
+
+void
+odm_txpowertracking_callback_thermal_meter92d(
+	struct _ADAPTER	*adapter
+);
+
+void
+odm_txpowertracking_direct_call92c(
+	struct _ADAPTER		*adapter
+);
+
+void
+odm_txpowertracking_thermal_meter_check(
+	struct _ADAPTER		*adapter
+);
+
+#endif
+
+
+
+#endif
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/phydm_powertracking_ce.c linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/phydm_powertracking_ce.c
--- linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/phydm_powertracking_ce.c	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/phydm_powertracking_ce.c	2020-04-10 16:35:06.826660535 +0300
@@ -0,0 +1,824 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
+ *
+ *
+ ******************************************************************************/
+
+/*============================================================	*/
+/* include files												*/
+/*============================================================	*/
+#include "mp_precomp.h"
+#include "phydm_precomp.h"
+
+/* ************************************************************
+ * Global var
+ * ************************************************************ */
+
+u32	ofdm_swing_table[OFDM_TABLE_SIZE] = {
+	0x7f8001fe,	/* 0, +6.0dB */
+	0x788001e2,	/* 1, +5.5dB */
+	0x71c001c7,	/* 2, +5.0dB*/
+	0x6b8001ae,	/* 3, +4.5dB*/
+	0x65400195,	/* 4, +4.0dB*/
+	0x5fc0017f,	/* 5, +3.5dB*/
+	0x5a400169,	/* 6, +3.0dB*/
+	0x55400155,	/* 7, +2.5dB*/
+	0x50800142,	/* 8, +2.0dB*/
+	0x4c000130,	/* 9, +1.5dB*/
+	0x47c0011f,	/* 10, +1.0dB*/
+	0x43c0010f,	/* 11, +0.5dB*/
+	0x40000100,	/* 12, +0dB*/
+	0x3c8000f2,	/* 13, -0.5dB*/
+	0x390000e4,	/* 14, -1.0dB*/
+	0x35c000d7,	/* 15, -1.5dB*/
+	0x32c000cb,	/* 16, -2.0dB*/
+	0x300000c0,	/* 17, -2.5dB*/
+	0x2d4000b5,	/* 18, -3.0dB*/
+	0x2ac000ab,	/* 19, -3.5dB*/
+	0x288000a2,	/* 20, -4.0dB*/
+	0x26000098,	/* 21, -4.5dB*/
+	0x24000090,	/* 22, -5.0dB*/
+	0x22000088,	/* 23, -5.5dB*/
+	0x20000080,	/* 24, -6.0dB*/
+	0x1e400079,	/* 25, -6.5dB*/
+	0x1c800072,	/* 26, -7.0dB*/
+	0x1b00006c,	/* 27. -7.5dB*/
+	0x19800066,	/* 28, -8.0dB*/
+	0x18000060,	/* 29, -8.5dB*/
+	0x16c0005b,	/* 30, -9.0dB*/
+	0x15800056,	/* 31, -9.5dB*/
+	0x14400051,	/* 32, -10.0dB*/
+	0x1300004c,	/* 33, -10.5dB*/
+	0x12000048,	/* 34, -11.0dB*/
+	0x11000044,	/* 35, -11.5dB*/
+	0x10000040,	/* 36, -12.0dB*/
+};
+
+u8	cck_swing_table_ch1_ch13[CCK_TABLE_SIZE][8] = {
+	{0x36, 0x35, 0x2e, 0x25, 0x1c, 0x12, 0x09, 0x04},	/* 0, +0dB */
+	{0x33, 0x32, 0x2b, 0x23, 0x1a, 0x11, 0x08, 0x04},	/* 1, -0.5dB */
+	{0x30, 0x2f, 0x29, 0x21, 0x19, 0x10, 0x08, 0x03},	/* 2, -1.0dB*/
+	{0x2d, 0x2d, 0x27, 0x1f, 0x18, 0x0f, 0x08, 0x03},	/* 3, -1.5dB*/
+	{0x2b, 0x2a, 0x25, 0x1e, 0x16, 0x0e, 0x07, 0x03},	/* 4, -2.0dB */
+	{0x28, 0x28, 0x22, 0x1c, 0x15, 0x0d, 0x07, 0x03},	/* 5, -2.5dB*/
+	{0x26, 0x25, 0x21, 0x1b, 0x14, 0x0d, 0x06, 0x03},	/* 6, -3.0dB*/
+	{0x24, 0x23, 0x1f, 0x19, 0x13, 0x0c, 0x06, 0x03},	/* 7, -3.5dB*/
+	{0x22, 0x21, 0x1d, 0x18, 0x11, 0x0b, 0x06, 0x02},	/* 8, -4.0dB */
+	{0x20, 0x20, 0x1b, 0x16, 0x11, 0x08, 0x05, 0x02},	/* 9, -4.5dB*/
+	{0x1f, 0x1e, 0x1a, 0x15, 0x10, 0x0a, 0x05, 0x02},	/* 10, -5.0dB */
+	{0x1d, 0x1c, 0x18, 0x14, 0x0f, 0x0a, 0x05, 0x02},	/* 11, -5.5dB*/
+	{0x1b, 0x1a, 0x17, 0x13, 0x0e, 0x09, 0x04, 0x02},	/* 12, -6.0dB <== default */
+	{0x1a, 0x19, 0x16, 0x12, 0x0d, 0x09, 0x04, 0x02},	/* 13, -6.5dB*/
+	{0x18, 0x17, 0x15, 0x11, 0x0c, 0x08, 0x04, 0x02},	/* 14, -7.0dB */
+	{0x17, 0x16, 0x13, 0x10, 0x0c, 0x08, 0x04, 0x02},	/* 15, -7.5dB*/
+	{0x16, 0x15, 0x12, 0x0f, 0x0b, 0x07, 0x04, 0x01},	/* 16, -8.0dB */
+	{0x14, 0x14, 0x11, 0x0e, 0x0b, 0x07, 0x03, 0x02},	/* 17, -8.5dB*/
+	{0x13, 0x13, 0x10, 0x0d, 0x0a, 0x06, 0x03, 0x01},	/* 18, -9.0dB */
+	{0x12, 0x12, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01},	/* 19, -9.5dB*/
+	{0x11, 0x11, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01},	/* 20, -10.0dB*/
+	{0x10, 0x10, 0x0e, 0x0b, 0x08, 0x05, 0x03, 0x01},	/* 21, -10.5dB*/
+	{0x0f, 0x0f, 0x0d, 0x0b, 0x08, 0x05, 0x03, 0x01},	/* 22, -11.0dB*/
+	{0x0e, 0x0e, 0x0c, 0x0a, 0x08, 0x05, 0x02, 0x01},	/* 23, -11.5dB*/
+	{0x0d, 0x0d, 0x0c, 0x0a, 0x07, 0x05, 0x02, 0x01},	/* 24, -12.0dB*/
+	{0x0d, 0x0c, 0x0b, 0x09, 0x07, 0x04, 0x02, 0x01},	/* 25, -12.5dB*/
+	{0x0c, 0x0c, 0x0a, 0x09, 0x06, 0x04, 0x02, 0x01},	/* 26, -13.0dB*/
+	{0x0b, 0x0b, 0x0a, 0x08, 0x06, 0x04, 0x02, 0x01},	/* 27, -13.5dB*/
+	{0x0b, 0x0a, 0x09, 0x08, 0x06, 0x04, 0x02, 0x01},	/* 28, -14.0dB*/
+	{0x0a, 0x0a, 0x09, 0x07, 0x05, 0x03, 0x02, 0x01},	/* 29, -14.5dB*/
+	{0x0a, 0x09, 0x08, 0x07, 0x05, 0x03, 0x02, 0x01},	/* 30, -15.0dB*/
+	{0x09, 0x09, 0x08, 0x06, 0x05, 0x03, 0x01, 0x01},	/* 31, -15.5dB*/
+	{0x09, 0x08, 0x07, 0x06, 0x04, 0x03, 0x01, 0x01}	/* 32, -16.0dB*/
+};
+
+
+u8	cck_swing_table_ch14[CCK_TABLE_SIZE][8] = {
+	{0x36, 0x35, 0x2e, 0x1b, 0x00, 0x00, 0x00, 0x00},	/* 0, +0dB */
+	{0x33, 0x32, 0x2b, 0x19, 0x00, 0x00, 0x00, 0x00},	/* 1, -0.5dB */
+	{0x30, 0x2f, 0x29, 0x18, 0x00, 0x00, 0x00, 0x00},	/* 2, -1.0dB */
+	{0x2d, 0x2d, 0x17, 0x17, 0x00, 0x00, 0x00, 0x00},	/* 3, -1.5dB*/
+	{0x2b, 0x2a, 0x25, 0x15, 0x00, 0x00, 0x00, 0x00},	/* 4, -2.0dB */
+	{0x28, 0x28, 0x24, 0x14, 0x00, 0x00, 0x00, 0x00},	/* 5, -2.5dB*/
+	{0x26, 0x25, 0x21, 0x13, 0x00, 0x00, 0x00, 0x00},	/* 6, -3.0dB */
+	{0x24, 0x23, 0x1f, 0x12, 0x00, 0x00, 0x00, 0x00},	/* 7, -3.5dB */
+	{0x22, 0x21, 0x1d, 0x11, 0x00, 0x00, 0x00, 0x00},	/* 8, -4.0dB */
+	{0x20, 0x20, 0x1b, 0x10, 0x00, 0x00, 0x00, 0x00},	/* 9, -4.5dB*/
+	{0x1f, 0x1e, 0x1a, 0x0f, 0x00, 0x00, 0x00, 0x00},	/* 10, -5.0dB */
+	{0x1d, 0x1c, 0x18, 0x0e, 0x00, 0x00, 0x00, 0x00},	/* 11, -5.5dB*/
+	{0x1b, 0x1a, 0x17, 0x0e, 0x00, 0x00, 0x00, 0x00},	/* 12, -6.0dB  <== default*/
+	{0x1a, 0x19, 0x16, 0x0d, 0x00, 0x00, 0x00, 0x00},	/* 13, -6.5dB */
+	{0x18, 0x17, 0x15, 0x0c, 0x00, 0x00, 0x00, 0x00},	/* 14, -7.0dB */
+	{0x17, 0x16, 0x13, 0x0b, 0x00, 0x00, 0x00, 0x00},	/* 15, -7.5dB*/
+	{0x16, 0x15, 0x12, 0x0b, 0x00, 0x00, 0x00, 0x00},	/* 16, -8.0dB */
+	{0x14, 0x14, 0x11, 0x0a, 0x00, 0x00, 0x00, 0x00},	/* 17, -8.5dB*/
+	{0x13, 0x13, 0x10, 0x0a, 0x00, 0x00, 0x00, 0x00},	/* 18, -9.0dB */
+	{0x12, 0x12, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00},	/* 19, -9.5dB*/
+	{0x11, 0x11, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00},	/* 20, -10.0dB*/
+	{0x10, 0x10, 0x0e, 0x08, 0x00, 0x00, 0x00, 0x00},	/* 21, -10.5dB*/
+	{0x0f, 0x0f, 0x0d, 0x08, 0x00, 0x00, 0x00, 0x00},	/* 22, -11.0dB*/
+	{0x0e, 0x0e, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00},	/* 23, -11.5dB*/
+	{0x0d, 0x0d, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00},	/* 24, -12.0dB*/
+	{0x0d, 0x0c, 0x0b, 0x06, 0x00, 0x00, 0x00, 0x00},	/* 25, -12.5dB*/
+	{0x0c, 0x0c, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00},	/* 26, -13.0dB*/
+	{0x0b, 0x0b, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00},	/* 27, -13.5dB*/
+	{0x0b, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00},	/* 28, -14.0dB*/
+	{0x0a, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00},	/* 29, -14.5dB*/
+	{0x0a, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00},	/* 30, -15.0dB*/
+	{0x09, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00},	/* 31, -15.5dB*/
+	{0x09, 0x08, 0x07, 0x04, 0x00, 0x00, 0x00, 0x00}	/* 32, -16.0dB*/
+};
+
+
+u32 ofdm_swing_table_new[OFDM_TABLE_SIZE] = {
+	0x0b40002d, /* 0,  -15.0dB	*/
+	0x0c000030, /* 1,  -14.5dB*/
+	0x0cc00033, /* 2,  -14.0dB*/
+	0x0d800036, /* 3,  -13.5dB*/
+	0x0e400039, /* 4,  -13.0dB */
+	0x0f00003c, /* 5,  -12.5dB*/
+	0x10000040, /* 6,  -12.0dB*/
+	0x11000044, /* 7,  -11.5dB*/
+	0x12000048, /* 8,  -11.0dB*/
+	0x1300004c, /* 9,  -10.5dB*/
+	0x14400051, /* 10, -10.0dB*/
+	0x15800056, /* 11, -9.5dB*/
+	0x16c0005b, /* 12, -9.0dB*/
+	0x18000060, /* 13, -8.5dB*/
+	0x19800066, /* 14, -8.0dB*/
+	0x1b00006c, /* 15, -7.5dB*/
+	0x1c800072, /* 16, -7.0dB*/
+	0x1e400079, /* 17, -6.5dB*/
+	0x20000080, /* 18, -6.0dB*/
+	0x22000088, /* 19, -5.5dB*/
+	0x24000090, /* 20, -5.0dB*/
+	0x26000098, /* 21, -4.5dB*/
+	0x288000a2, /* 22, -4.0dB*/
+	0x2ac000ab, /* 23, -3.5dB*/
+	0x2d4000b5, /* 24, -3.0dB*/
+	0x300000c0, /* 25, -2.5dB*/
+	0x32c000cb, /* 26, -2.0dB*/
+	0x35c000d7, /* 27, -1.5dB*/
+	0x390000e4, /* 28, -1.0dB*/
+	0x3c8000f2, /* 29, -0.5dB*/
+	0x40000100, /* 30, +0dB*/
+	0x43c0010f, /* 31, +0.5dB*/
+	0x47c0011f, /* 32, +1.0dB*/
+	0x4c000130, /* 33, +1.5dB*/
+	0x50800142, /* 34, +2.0dB*/
+	0x55400155, /* 35, +2.5dB*/
+	0x5a400169, /* 36, +3.0dB*/
+	0x5fc0017f, /* 37, +3.5dB*/
+	0x65400195, /* 38, +4.0dB*/
+	0x6b8001ae, /* 39, +4.5dB*/
+	0x71c001c7, /* 40, +5.0dB*/
+	0x788001e2, /* 41, +5.5dB*/
+	0x7f8001fe  /* 42, +6.0dB*/
+};
+
+
+u8 cck_swing_table_ch1_ch14_88f[CCK_TABLE_SIZE_88F][16] = {
+	{0x44, 0x42, 0x3C, 0x33, 0x28, 0x1C, 0x13, 0x0B, 0x05, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-16dB*/
+	{0x48, 0x46, 0x3F, 0x36, 0x2A, 0x1E, 0x14, 0x0B, 0x05, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-15.5dB*/
+	{0x4D, 0x4A, 0x43, 0x39, 0x2C, 0x20, 0x15, 0x0C, 0x06, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-15dB*/
+	{0x51, 0x4F, 0x47, 0x3C, 0x2F, 0x22, 0x16, 0x0D, 0x06, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-14.5dB*/
+	{0x56, 0x53, 0x4B, 0x40, 0x32, 0x24, 0x17, 0x0E, 0x06, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-14dB*/
+	{0x5B, 0x58, 0x50, 0x43, 0x35, 0x26, 0x19, 0x0E, 0x07, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-13.5dB*/
+	{0x60, 0x5D, 0x54, 0x47, 0x38, 0x28, 0x1A, 0x0F, 0x07, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-13dB*/
+	{0x66, 0x63, 0x59, 0x4C, 0x3B, 0x2B, 0x1C, 0x10, 0x08, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-12.5dB*/
+	{0x6C, 0x69, 0x5F, 0x50, 0x3F, 0x2D, 0x1E, 0x11, 0x08, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-12dB*/
+	{0x73, 0x6F, 0x64, 0x55, 0x42, 0x30, 0x1F, 0x12, 0x08, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-11.5dB*/
+	{0x79, 0x76, 0x6A, 0x5A, 0x46, 0x33, 0x21, 0x13, 0x09, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-11dB*/
+	{0x81, 0x7C, 0x71, 0x5F, 0x4A, 0x36, 0x23, 0x14, 0x0A, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-10.5dB*/
+	{0x88, 0x84, 0x77, 0x65, 0x4F, 0x39, 0x25, 0x15, 0x0A, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-10dB*/
+	{0x90, 0x8C, 0x7E, 0x6B, 0x54, 0x3C, 0x27, 0x17, 0x0B, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-9.5dB*/
+	{0x99, 0x94, 0x86, 0x71, 0x58, 0x40, 0x2A, 0x18, 0x0B, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-9dB*/
+	{0xA2, 0x9D, 0x8E, 0x78, 0x5E, 0x43, 0x2C, 0x19, 0x0C, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-8.5dB*/
+	{0xAC, 0xA6, 0x96, 0x7F, 0x63, 0x47, 0x2F, 0x1B, 0x0D, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-8dB*/
+	{0xB6, 0xB0, 0x9F, 0x87, 0x69, 0x4C, 0x32, 0x1D, 0x0D, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-7.5dB*/
+	{0xC1, 0xBA, 0xA8, 0x8F, 0x6F, 0x50, 0x35, 0x1E, 0x0E, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-7dB*/
+	{0xCC, 0xC5, 0xB2, 0x97, 0x76, 0x55, 0x38, 0x20, 0x0F, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-6.5dB*/
+	{0xD8, 0xD1, 0xBD, 0xA0, 0x7D, 0x5A, 0x3B, 0x22, 0x10, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}     /*-6dB*/
+};
+
+
+u8 cck_swing_table_ch1_ch13_88f[CCK_TABLE_SIZE_88F][16] = {
+	{0x44, 0x42, 0x3C, 0x33, 0x28, 0x1C, 0x13, 0x0B, 0x05, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-16dB*/
+	{0x48, 0x46, 0x3F, 0x36, 0x2A, 0x1E, 0x14, 0x0B, 0x05, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-15.5dB*/
+	{0x4D, 0x4A, 0x43, 0x39, 0x2C, 0x20, 0x15, 0x0C, 0x06, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-15dB*/
+	{0x51, 0x4F, 0x47, 0x3C, 0x2F, 0x22, 0x16, 0x0D, 0x06, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-14.5dB*/
+	{0x56, 0x53, 0x4B, 0x40, 0x32, 0x24, 0x17, 0x0E, 0x06, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-14dB*/
+	{0x5B, 0x58, 0x50, 0x43, 0x35, 0x26, 0x19, 0x0E, 0x07, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-13.5dB*/
+	{0x60, 0x5D, 0x54, 0x47, 0x38, 0x28, 0x1A, 0x0F, 0x07, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-13dB*/
+	{0x66, 0x63, 0x59, 0x4C, 0x3B, 0x2B, 0x1C, 0x10, 0x08, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-12.5dB*/
+	{0x6C, 0x69, 0x5F, 0x50, 0x3F, 0x2D, 0x1E, 0x11, 0x08, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-12dB*/
+	{0x73, 0x6F, 0x64, 0x55, 0x42, 0x30, 0x1F, 0x12, 0x08, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-11.5dB*/
+	{0x79, 0x76, 0x6A, 0x5A, 0x46, 0x33, 0x21, 0x13, 0x09, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-11dB*/
+	{0x81, 0x7C, 0x71, 0x5F, 0x4A, 0x36, 0x23, 0x14, 0x0A, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-10.5dB*/
+	{0x88, 0x84, 0x77, 0x65, 0x4F, 0x39, 0x25, 0x15, 0x0A, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-10dB*/
+	{0x90, 0x8C, 0x7E, 0x6B, 0x54, 0x3C, 0x27, 0x17, 0x0B, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-9.5dB*/
+	{0x99, 0x94, 0x86, 0x71, 0x58, 0x40, 0x2A, 0x18, 0x0B, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-9dB*/
+	{0xA2, 0x9D, 0x8E, 0x78, 0x5E, 0x43, 0x2C, 0x19, 0x0C, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-8.5dB*/
+	{0xAC, 0xA6, 0x96, 0x7F, 0x63, 0x47, 0x2F, 0x1B, 0x0D, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-8dB*/
+	{0xB6, 0xB0, 0x9F, 0x87, 0x69, 0x4C, 0x32, 0x1D, 0x0D, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-7.5dB*/
+	{0xC1, 0xBA, 0xA8, 0x8F, 0x6F, 0x50, 0x35, 0x1E, 0x0E, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-7dB*/
+	{0xCC, 0xC5, 0xB2, 0x97, 0x76, 0x55, 0x38, 0x20, 0x0F, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-6.5dB*/
+	{0xD8, 0xD1, 0xBD, 0xA0, 0x7D, 0x5A, 0x3B, 0x22, 0x10, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}     /*-6dB*/
+};
+
+
+u8 cck_swing_table_ch14_88f[CCK_TABLE_SIZE_88F][16] = {
+	{0x44,	 0x42, 0x3C, 0x28, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-16dB*/
+	{0x48, 0x46, 0x3F, 0x2A, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-15.5dB*/
+	{0x4D, 0x4A, 0x43, 0x2C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-15dB*/
+	{0x51, 0x4F, 0x47, 0x2F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},	    /*-14.5dB*/
+	{0x56, 0x53, 0x4B, 0x32, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-14dB*/
+	{0x5B, 0x58, 0x50, 0x35, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-13.5dB*/
+	{0x60, 0x5D, 0x54, 0x38, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-13dB*/
+	{0x66, 0x63, 0x59, 0x3B, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-12.5dB*/
+	{0x6C, 0x69, 0x5F, 0x3F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-12dB*/
+	{0x73, 0x6F, 0x64, 0x42, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-11.5dB*/
+	{0x79, 0x76, 0x6A, 0x46, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-11dB*/
+	{0x81, 0x7C, 0x71, 0x4A, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-10.5dB*/
+	{0x88, 0x84, 0x77, 0x4F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-10dB*/
+	{0x90, 0x8C, 0x7E, 0x54, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-9.5dB*/
+	{0x99, 0x94, 0x86, 0x58, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-9dB*/
+	{0xA2, 0x9D, 0x8E, 0x5E, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-8.5dB*/
+	{0xAC, 0xA6, 0x96, 0x63, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-8dB*/
+	{0xB6, 0xB0, 0x9F, 0x69, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-7.5dB*/
+	{0xC1, 0xBA, 0xA8, 0x6F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-7dB*/
+	{0xCC, 0xC5, 0xB2, 0x76, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-6.5dB*/
+	{0xD8, 0xD1, 0xBD, 0x7D, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}     /*-6dB*/
+};
+
+
+u8 cck_swing_table_ch1_ch13_new[CCK_TABLE_SIZE][8] = {
+	{0x09, 0x08, 0x07, 0x06, 0x04, 0x03, 0x01, 0x01},	/*  0, -16.0dB*/
+	{0x09, 0x09, 0x08, 0x06, 0x05, 0x03, 0x01, 0x01},	/*   1, -15.5dB*/
+	{0x0a, 0x09, 0x08, 0x07, 0x05, 0x03, 0x02, 0x01},	/*  2, -15.0dB*/
+	{0x0a, 0x0a, 0x09, 0x07, 0x05, 0x03, 0x02, 0x01},	/*   3, -14.5dB*/
+	{0x0b, 0x0a, 0x09, 0x08, 0x06, 0x04, 0x02, 0x01},	/*   4, -14.0dB*/
+	{0x0b, 0x0b, 0x0a, 0x08, 0x06, 0x04, 0x02, 0x01},	/*   5, -13.5dB*/
+	{0x0c, 0x0c, 0x0a, 0x09, 0x06, 0x04, 0x02, 0x01},	/*   6, -13.0dB*/
+	{0x0d, 0x0c, 0x0b, 0x09, 0x07, 0x04, 0x02, 0x01},	/*   7, -12.5dB*/
+	{0x0d, 0x0d, 0x0c, 0x0a, 0x07, 0x05, 0x02, 0x01},	/*  8, -12.0dB*/
+	{0x0e, 0x0e, 0x0c, 0x0a, 0x08, 0x05, 0x02, 0x01},	/*   9, -11.5dB*/
+	{0x0f, 0x0f, 0x0d, 0x0b, 0x08, 0x05, 0x03, 0x01},	/*  10, -11.0dB*/
+	{0x10, 0x10, 0x0e, 0x0b, 0x08, 0x05, 0x03, 0x01},	/*  11, -10.5dB*/
+	{0x11, 0x11, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01},	/*  12, -10.0dB*/
+	{0x12, 0x12, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01},	/*  13, -9.5dB*/
+	{0x13, 0x13, 0x10, 0x0d, 0x0a, 0x06, 0x03, 0x01},	/*  14, -9.0dB */
+	{0x14, 0x14, 0x11, 0x0e, 0x0b, 0x07, 0x03, 0x02},	/*  15, -8.5dB*/
+	{0x16, 0x15, 0x12, 0x0f, 0x0b, 0x07, 0x04, 0x01},	/*  16, -8.0dB */
+	{0x17, 0x16, 0x13, 0x10, 0x0c, 0x08, 0x04, 0x02},	/*  17, -7.5dB*/
+	{0x18, 0x17, 0x15, 0x11, 0x0c, 0x08, 0x04, 0x02},	/*  18, -7.0dB */
+	{0x1a, 0x19, 0x16, 0x12, 0x0d, 0x09, 0x04, 0x02},	/*  19, -6.5dB*/
+	{0x1b, 0x1a, 0x17, 0x13, 0x0e, 0x09, 0x04, 0x02},	/*20, -6.0dB */
+	{0x1d, 0x1c, 0x18, 0x14, 0x0f, 0x0a, 0x05, 0x02},	/*  21, -5.5dB*/
+	{0x1f, 0x1e, 0x1a, 0x15, 0x10, 0x0a, 0x05, 0x02},	/* 22, -5.0dB */
+	{0x20, 0x20, 0x1b, 0x16, 0x11, 0x08, 0x05, 0x02},	/*  23, -4.5dB*/
+	{0x22, 0x21, 0x1d, 0x18, 0x11, 0x0b, 0x06, 0x02},	/*  24, -4.0dB */
+	{0x24, 0x23, 0x1f, 0x19, 0x13, 0x0c, 0x06, 0x03},	/*  25, -3.5dB*/
+	{0x26, 0x25, 0x21, 0x1b, 0x14, 0x0d, 0x06, 0x03},	/*  26, -3.0dB*/
+	{0x28, 0x28, 0x22, 0x1c, 0x15, 0x0d, 0x07, 0x03},	/*  27, -2.5dB*/
+	{0x2b, 0x2a, 0x25, 0x1e, 0x16, 0x0e, 0x07, 0x03},	/*  28, -2.0dB */
+	{0x2d, 0x2d, 0x27, 0x1f, 0x18, 0x0f, 0x08, 0x03},	/*  29, -1.5dB*/
+	{0x30, 0x2f, 0x29, 0x21, 0x19, 0x10, 0x08, 0x03},	/*  30, -1.0dB*/
+	{0x33, 0x32, 0x2b, 0x23, 0x1a, 0x11, 0x08, 0x04},	/*  31, -0.5dB*/
+	{0x36, 0x35, 0x2e, 0x25, 0x1c, 0x12, 0x09, 0x04}	/*  32, +0dB*/
+};
+
+
+u8 cck_swing_table_ch14_new[CCK_TABLE_SIZE][8] = {
+	{0x09, 0x08, 0x07, 0x04, 0x00, 0x00, 0x00, 0x00},	/*  0, -16.0dB*/
+	{0x09, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00},	/* 1, -15.5dB*/
+	{0x0a, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00},	/*  2, -15.0dB*/
+	{0x0a, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00},	/* 3, -14.5dB*/
+	{0x0b, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00},	/*  4, -14.0dB*/
+	{0x0b, 0x0b, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00},	/*5, -13.5dB*/
+	{0x0c, 0x0c, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00},	/* 6, -13.0dB*/
+	{0x0d, 0x0c, 0x0b, 0x06, 0x00, 0x00, 0x00, 0x00},	/*  7, -12.5dB*/
+	{0x0d, 0x0d, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00},	/* 8, -12.0dB*/
+	{0x0e, 0x0e, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00},	/* 9, -11.5dB*/
+	{0x0f, 0x0f, 0x0d, 0x08, 0x00, 0x00, 0x00, 0x00},	/* 10, -11.0dB*/
+	{0x10, 0x10, 0x0e, 0x08, 0x00, 0x00, 0x00, 0x00},	/*11, -10.5dB*/
+	{0x11, 0x11, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00},	/* 12, -10.0dB*/
+	{0x12, 0x12, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00},	/* 13, -9.5dB*/
+	{0x13, 0x13, 0x10, 0x0a, 0x00, 0x00, 0x00, 0x00},	/*14, -9.0dB */
+	{0x14, 0x14, 0x11, 0x0a, 0x00, 0x00, 0x00, 0x00},	/* 15, -8.5dB*/
+	{0x16, 0x15, 0x12, 0x0b, 0x00, 0x00, 0x00, 0x00},	/* 16, -8.0dB */
+	{0x17, 0x16, 0x13, 0x0b, 0x00, 0x00, 0x00, 0x00},	/* 17, -7.5dB*/
+	{0x18, 0x17, 0x15, 0x0c, 0x00, 0x00, 0x00, 0x00},	/* 18, -7.0dB */
+	{0x1a, 0x19, 0x16, 0x0d, 0x00, 0x00, 0x00, 0x00},	/* 19, -6.5dB */
+	{0x1b, 0x1a, 0x17, 0x0e, 0x00, 0x00, 0x00, 0x00},	/* 20, -6.0dB */
+	{0x1d, 0x1c, 0x18, 0x0e, 0x00, 0x00, 0x00, 0x00},	/* 21, -5.5dB*/
+	{0x1f, 0x1e, 0x1a, 0x0f, 0x00, 0x00, 0x00, 0x00},	/* 22, -5.0dB */
+	{0x20, 0x20, 0x1b, 0x10, 0x00, 0x00, 0x00, 0x00},	/*23, -4.5dB*/
+	{0x22, 0x21, 0x1d, 0x11, 0x00, 0x00, 0x00, 0x00},	/* 24, -4.0dB */
+	{0x24, 0x23, 0x1f, 0x12, 0x00, 0x00, 0x00, 0x00},	/* 25, -3.5dB */
+	{0x26, 0x25, 0x21, 0x13, 0x00, 0x00, 0x00, 0x00},	/* 26, -3.0dB */
+	{0x28, 0x28, 0x24, 0x14, 0x00, 0x00, 0x00, 0x00},	/*27, -2.5dB*/
+	{0x2b, 0x2a, 0x25, 0x15, 0x00, 0x00, 0x00, 0x00},	/* 28, -2.0dB */
+	{0x2d, 0x2d, 0x17, 0x17, 0x00, 0x00, 0x00, 0x00},	/*29, -1.5dB*/
+	{0x30, 0x2f, 0x29, 0x18, 0x00, 0x00, 0x00, 0x00},	/* 30, -1.0dB */
+	{0x33, 0x32, 0x2b, 0x19, 0x00, 0x00, 0x00, 0x00},	/* 31, -0.5dB */
+	{0x36, 0x35, 0x2e, 0x1b, 0x00, 0x00, 0x00, 0x00}	/* 32, +0dB	*/
+};
+u32 cck_swing_table_ch1_ch14_8723d[CCK_TABLE_SIZE_8723D] = {
+	0x0CD,          /*0 ,    -20dB*/
+	0x0D9,
+	0x0E6,
+	0x0F3,
+	0x102,
+	0x111,
+	0x121,
+	0x132,
+	0x144,
+	0x158,
+	0x16C,
+	0x182,
+	0x198,
+	0x1B1,
+	0x1CA,
+	0x1E5,
+	0x202,
+	0x221,
+	0x241,
+	0x263,
+	0x287,
+	0x2AE,
+	0x2D6,
+	0x301,
+	0x32F,
+	0x35F,
+	0x392,
+	0x3C9,
+	0x402,
+	0x43F,
+	0x47F,
+	0x4C3,
+	0x50C,
+	0x558,
+	0x5A9,
+	0x5FF,
+	0x65A,
+	0x6BA,
+	0x720,
+	0x78C,
+	0x7FF,
+};
+/* JJ ADD 20161014 */
+u32 cck_swing_table_ch1_ch14_8710b[CCK_TABLE_SIZE_8710B] = {
+	0x0CD,          /*0 ,    -20dB*/
+	0x0D9,
+	0x0E6,
+	0x0F3,
+	0x102,
+	0x111,
+	0x121,
+	0x132,
+	0x144,
+	0x158,
+	0x16C,
+	0x182,
+	0x198,
+	0x1B1,
+	0x1CA,
+	0x1E5,
+	0x202,
+	0x221,
+	0x241,
+	0x263,
+	0x287,
+	0x2AE,
+	0x2D6,
+	0x301,
+	0x32F,
+	0x35F,
+	0x392,
+	0x3C9,
+	0x402,
+	0x43F,
+	0x47F,
+	0x4C3,
+	0x50C,
+	0x558,
+	0x5A9,
+	0x5FF,
+	0x65A,
+	0x6BA,
+	0x720,
+	0x78C,
+	0x7FF,
+};
+
+
+u32 tx_scaling_table_jaguar[TXSCALE_TABLE_SIZE] = {
+	0x081, /* 0,  -12.0dB*/
+	0x088, /* 1,  -11.5dB*/
+	0x090, /* 2,  -11.0dB*/
+	0x099, /* 3,  -10.5dB*/
+	0x0A2, /* 4,  -10.0dB*/
+	0x0AC, /* 5,  -9.5dB*/
+	0x0B6, /* 6,  -9.0dB*/
+	0x0C0, /*7,  -8.5dB*/
+	0x0CC, /* 8,  -8.0dB*/
+	0x0D8, /* 9,  -7.5dB*/
+	0x0E5, /* 10, -7.0dB*/
+	0x0F2, /* 11, -6.5dB*/
+	0x101, /* 12, -6.0dB*/
+	0x110, /* 13, -5.5dB*/
+	0x120, /* 14, -5.0dB*/
+	0x131, /* 15, -4.5dB*/
+	0x143, /* 16, -4.0dB*/
+	0x156, /* 17, -3.5dB*/
+	0x16A, /* 18, -3.0dB*/
+	0x180, /* 19, -2.5dB*/
+	0x197, /* 20, -2.0dB*/
+	0x1AF, /* 21, -1.5dB*/
+	0x1C8, /* 22, -1.0dB*/
+	0x1E3, /* 23, -0.5dB*/
+	0x200, /* 24, +0  dB*/
+	0x21E, /* 25, +0.5dB*/
+	0x23E, /* 26, +1.0dB*/
+	0x261, /* 27, +1.5dB*/
+	0x285,/* 28, +2.0dB*/
+	0x2AB, /* 29, +2.5dB*/
+	0x2D3, /*30, +3.0dB*/
+	0x2FE, /* 31, +3.5dB*/
+	0x32B, /* 32, +4.0dB*/
+	0x35C, /* 33, +4.5dB*/
+	0x38E, /* 34, +5.0dB*/
+	0x3C4, /* 35, +5.5dB*/
+	0x3FE  /* 36, +6.0dB	*/
+};
+
+#ifdef AP_BUILD_WORKAROUND
+
+unsigned int tx_pwr_trk_ofdm_swing_tbl[tx_pwr_trk_ofdm_swing_tbl_len] = {
+	/*  +6.0dB */ 0x7f8001fe,
+	/*  +5.5dB */ 0x788001e2,
+	/*  +5.0dB */ 0x71c001c7,
+	/*  +4.5dB */ 0x6b8001ae,
+	/*  +4.0dB */ 0x65400195,
+	/*  +3.5dB */ 0x5fc0017f,
+	/*  +3.0dB */ 0x5a400169,
+	/*  +2.5dB */ 0x55400155,
+	/*  +2.0dB */ 0x50800142,
+	/*  +1.5dB */ 0x4c000130,
+	/*  +1.0dB */ 0x47c0011f,
+	/*  +0.5dB */ 0x43c0010f,
+	/*   0.0dB */ 0x40000100,
+	/*  -0.5dB */ 0x3c8000f2,
+	/*  -1.0dB */ 0x390000e4,
+	/*  -1.5dB */ 0x35c000d7,
+	/*  -2.0dB */ 0x32c000cb,
+	/*  -2.5dB */ 0x300000c0,
+	/*  -3.0dB */ 0x2d4000b5,
+	/*  -3.5dB */ 0x2ac000ab,
+	/*  -4.0dB */ 0x288000a2,
+	/*  -4.5dB */ 0x26000098,
+	/*  -5.0dB */ 0x24000090,
+	/*  -5.5dB */ 0x22000088,
+	/*  -6.0dB */ 0x20000080,
+	/*  -6.5dB */ 0x1a00006c,
+	/*  -7.0dB */ 0x1c800072,
+	/*  -7.5dB */ 0x18000060,
+	/*  -8.0dB */ 0x19800066,
+	/*  -8.5dB */ 0x15800056,
+	/*  -9.0dB */ 0x26c0005b,
+	/*  -9.5dB */ 0x14400051,
+	/* -10.0dB */ 0x24400051,
+	/* -10.5dB */ 0x1300004c,
+	/* -11.0dB */ 0x12000048,
+	/* -11.5dB */ 0x11000044,
+	/* -12.0dB */ 0x10000040
+};
+#endif
+
+
+
+void
+odm_txpowertracking_init(
+	void	*p_dm_void
+)
+{
+	struct PHY_DM_STRUCT		*p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
+#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
+	if (!(p_dm_odm->support_ic_type & (ODM_RTL8814A | ODM_IC_11N_SERIES | ODM_RTL8822B)))
+		return;
+#endif
+
+	odm_txpowertracking_thermal_meter_init(p_dm_odm);
+}
+
+u8
+get_swing_index(
+	void	*p_dm_void
+)
+{
+	struct PHY_DM_STRUCT		*p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
+	struct _ADAPTER		*adapter = p_dm_odm->adapter;
+	HAL_DATA_TYPE	*p_hal_data = GET_HAL_DATA(adapter);
+	u8			i = 0;
+	u32			bb_swing;
+	u32			swing_table_size;
+	u32			*p_swing_table;
+
+	if (p_dm_odm->support_ic_type == ODM_RTL8188E || p_dm_odm->support_ic_type == ODM_RTL8723B
+	    || p_dm_odm->support_ic_type == ODM_RTL8192E || p_dm_odm->support_ic_type == ODM_RTL8188F || p_dm_odm->support_ic_type == ODM_RTL8703B
+	   ) {
+		bb_swing = odm_get_bb_reg(p_dm_odm, REG_OFDM_0_XA_TX_IQ_IMBALANCE, 0xFFC00000);
+
+		p_swing_table = ofdm_swing_table_new;
+		swing_table_size = OFDM_TABLE_SIZE;
+	} else {
+#if ((RTL8812A_SUPPORT == 1) || (RTL8821A_SUPPORT == 1))
+		if (p_dm_odm->support_ic_type == ODM_RTL8812 || p_dm_odm->support_ic_type == ODM_RTL8821) {
+			bb_swing = phy_get_tx_bb_swing_8812a(adapter, p_hal_data->current_band_type, ODM_RF_PATH_A);
+			p_swing_table = tx_scaling_table_jaguar;
+			swing_table_size = TXSCALE_TABLE_SIZE;
+		} else
+#endif
+		{
+			bb_swing = 0;
+			p_swing_table = ofdm_swing_table;
+			swing_table_size = OFDM_TABLE_SIZE;
+		}
+	}
+
+	for (i = 0; i < swing_table_size; ++i) {
+		u32 table_value = p_swing_table[i];
+
+		if (table_value >= 0x100000)
+			table_value >>= 22;
+		if (bb_swing == table_value)
+			break;
+	}
+	return i;
+}
+
+u8
+get_cck_swing_index(
+	void		*p_dm_void
+)
+{
+	struct PHY_DM_STRUCT		*p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
+
+	u8			i = 0;
+	u32			bb_cck_swing;
+
+	if (p_dm_odm->support_ic_type == ODM_RTL8188E || p_dm_odm->support_ic_type == ODM_RTL8723B ||
+	    p_dm_odm->support_ic_type == ODM_RTL8192E) {
+		bb_cck_swing = odm_read_1byte(p_dm_odm, 0xa22);
+
+		for (i = 0; i < CCK_TABLE_SIZE; i++) {
+			if (bb_cck_swing == cck_swing_table_ch1_ch13_new[i][0])
+				break;
+		}
+	} else if (p_dm_odm->support_ic_type == ODM_RTL8703B) {
+		bb_cck_swing = odm_read_1byte(p_dm_odm, 0xa22);
+
+		for (i = 0; i < CCK_TABLE_SIZE_88F; i++) {
+			if (bb_cck_swing == cck_swing_table_ch1_ch14_88f[i][0])
+				break;
+		}
+	}
+
+	return i;
+}
+
+
+void
+odm_txpowertracking_thermal_meter_init(
+	void	*p_dm_void
+)
+{
+	struct PHY_DM_STRUCT		*p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
+	u8 default_swing_index = get_swing_index(p_dm_odm);
+	u8 default_cck_swing_index = get_cck_swing_index(p_dm_odm);
+	u8			p = 0;
+	struct odm_rf_calibration_structure	*p_rf_calibrate_info = &(p_dm_odm->rf_calibrate_info);
+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
+	struct _ADAPTER		*adapter = p_dm_odm->adapter;
+	HAL_DATA_TYPE	*p_hal_data = GET_HAL_DATA(adapter);
+
+	if (p_dm_odm->mp_mode == false)
+		p_hal_data->txpowertrack_control = true;
+#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
+	struct _ADAPTER		*adapter = p_dm_odm->adapter;
+	HAL_DATA_TYPE	*p_hal_data = GET_HAL_DATA(adapter);
+
+	p_rf_calibrate_info->is_txpowertracking = _TRUE;
+	p_rf_calibrate_info->tx_powercount = 0;
+	p_rf_calibrate_info->is_txpowertracking_init = _FALSE;
+
+	if (p_dm_odm->mp_mode == false)
+		p_rf_calibrate_info->txpowertrack_control = _TRUE;
+	else
+		p_rf_calibrate_info->txpowertrack_control = _FALSE;
+
+	if (p_dm_odm->mp_mode == false)
+		p_rf_calibrate_info->txpowertrack_control = _TRUE;
+
+	ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("p_dm_odm txpowertrack_control = %d\n", p_rf_calibrate_info->txpowertrack_control));
+
+#elif (DM_ODM_SUPPORT_TYPE & (ODM_AP))
+#ifdef RTL8188E_SUPPORT
+	{
+		p_rf_calibrate_info->is_txpowertracking = _TRUE;
+		p_rf_calibrate_info->tx_powercount = 0;
+		p_rf_calibrate_info->is_txpowertracking_init = _FALSE;
+		p_rf_calibrate_info->txpowertrack_control = _TRUE;
+	}
+#endif
+#endif
+
+	/* p_dm_odm->rf_calibrate_info.txpowertrack_control = true; */
+	p_rf_calibrate_info->thermal_value = p_hal_data->eeprom_thermal_meter;
+	p_rf_calibrate_info->thermal_value_iqk = p_hal_data->eeprom_thermal_meter;
+	p_rf_calibrate_info->thermal_value_lck = p_hal_data->eeprom_thermal_meter;
+
+	if (p_rf_calibrate_info->default_bb_swing_index_flag != true) {
+		/*The index of "0 dB" in SwingTable.*/
+		if (p_dm_odm->support_ic_type == ODM_RTL8188E || p_dm_odm->support_ic_type == ODM_RTL8723B ||
+		    p_dm_odm->support_ic_type == ODM_RTL8192E || p_dm_odm->support_ic_type == ODM_RTL8703B) {
+			p_rf_calibrate_info->default_ofdm_index = (default_swing_index >= OFDM_TABLE_SIZE) ? 30 : default_swing_index;
+			p_rf_calibrate_info->default_cck_index = (default_cck_swing_index >= CCK_TABLE_SIZE) ? 20 : default_cck_swing_index;
+		} else if (p_dm_odm->support_ic_type == ODM_RTL8188F) {          /*add by Mingzhi.Guo  2015-03-23*/
+			p_rf_calibrate_info->default_ofdm_index = 28;							/*OFDM: -1dB*/
+			p_rf_calibrate_info->default_cck_index = 20;							/*CCK:-6dB*/
+		} else if (p_dm_odm->support_ic_type == ODM_RTL8723D) {			 /*add by zhaohe  2015-10-27*/
+			p_rf_calibrate_info->default_ofdm_index = 28;						 	   /*OFDM: -1dB*/
+			p_rf_calibrate_info->default_cck_index = 28;							/*CCK:   -6dB*/
+		} else if (p_dm_odm->support_ic_type == ODM_RTL8710B) {		/* JJ ADD 20161014 */
+			p_rf_calibrate_info->default_ofdm_index = 28;						 	   /*OFDM: -1dB*/
+			p_rf_calibrate_info->default_cck_index = 28;							   /*CCK:   -6dB*/
+		} else {
+			p_rf_calibrate_info->default_ofdm_index = (default_swing_index >= TXSCALE_TABLE_SIZE) ? 24 : default_swing_index;
+			p_rf_calibrate_info->default_cck_index = 24;
+		}
+		p_rf_calibrate_info->default_bb_swing_index_flag = true;
+	}
+
+	p_rf_calibrate_info->bb_swing_idx_cck_base = p_rf_calibrate_info->default_cck_index;
+	p_rf_calibrate_info->CCK_index = p_rf_calibrate_info->default_cck_index;
+
+	for (p = ODM_RF_PATH_A; p < MAX_RF_PATH; ++p) {
+		p_rf_calibrate_info->bb_swing_idx_ofdm_base[p] = p_rf_calibrate_info->default_ofdm_index;
+		p_rf_calibrate_info->OFDM_index[p] = p_rf_calibrate_info->default_ofdm_index;
+		p_rf_calibrate_info->delta_power_index[p] = 0;
+		p_rf_calibrate_info->delta_power_index_last[p] = 0;
+		p_rf_calibrate_info->power_index_offset[p] = 0;
+	}
+	p_rf_calibrate_info->modify_tx_agc_value_ofdm = 0;
+	p_rf_calibrate_info->modify_tx_agc_value_cck = 0;
+
+}
+
+
+void
+odm_txpowertracking_check(
+	void	*p_dm_void
+)
+{
+	/* 2011/09/29 MH In HW integration first stage, we provide 4 different handle to operate
+	at the same time. In the stage2/3, we need to prive universal interface and merge all
+	HW dynamic mechanism. */
+	struct PHY_DM_STRUCT		*p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
+	switch	(p_dm_odm->support_platform) {
+	case	ODM_WIN:
+		odm_txpowertracking_check_mp(p_dm_odm);
+		break;
+
+	case	ODM_CE:
+		odm_txpowertracking_check_ce(p_dm_odm);
+		break;
+
+	case	ODM_AP:
+		odm_txpowertracking_check_ap(p_dm_odm);
+		break;
+
+	default:
+		break;
+	}
+
+}
+
+void
+odm_txpowertracking_check_ce(
+	void	*p_dm_void
+)
+{
+	struct PHY_DM_STRUCT		*p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
+#if (DM_ODM_SUPPORT_TYPE == ODM_CE)
+	struct _ADAPTER	*adapter = p_dm_odm->adapter;
+
+	if (!(p_dm_odm->support_ability & ODM_RF_TX_PWR_TRACK))
+		return;
+
+	if (!p_dm_odm->rf_calibrate_info.tm_trigger) {
+
+		if (IS_HARDWARE_TYPE_8188E(adapter) || IS_HARDWARE_TYPE_8188F(adapter) || IS_HARDWARE_TYPE_8192E(adapter)
+		    || IS_HARDWARE_TYPE_8723B(adapter) || IS_HARDWARE_TYPE_JAGUAR(adapter) || IS_HARDWARE_TYPE_8814A(adapter)
+		    || IS_HARDWARE_TYPE_8703B(adapter) || IS_HARDWARE_TYPE_8723D(adapter) || IS_HARDWARE_TYPE_8822B(adapter)
+		    || IS_HARDWARE_TYPE_8821C(adapter)  || (p_dm_odm->support_ic_type == ODM_RTL8710B)
+		   )/* JJ ADD 20161014 */
+			odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, RF_T_METER_NEW, (BIT(17) | BIT(16)), 0x03);
+		else
+			odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, RF_T_METER_OLD, RFREGOFFSETMASK, 0x60);
+
+
+
+		p_dm_odm->rf_calibrate_info.tm_trigger = 1;
+		return;
+	} else {
+
+		odm_txpowertracking_callback_thermal_meter(adapter);
+		p_dm_odm->rf_calibrate_info.tm_trigger = 0;
+	}
+
+#endif
+}
+
+void
+odm_txpowertracking_check_mp(
+	void	*p_dm_void
+)
+{
+	struct PHY_DM_STRUCT		*p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
+	struct _ADAPTER	*adapter = p_dm_odm->adapter;
+
+	if (odm_check_power_status(adapter) == false) {
+		RT_TRACE(COMP_POWER_TRACKING, DBG_LOUD, ("===>odm_check_power_status() return false\n"));
+		return;
+	}
+
+	odm_txpowertracking_thermal_meter_check(adapter);
+#endif
+
+}
+
+
+void
+odm_txpowertracking_check_ap(
+	void	*p_dm_void
+)
+{
+	struct PHY_DM_STRUCT		*p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
+#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
+	struct rtl8192cd_priv	*priv		= p_dm_odm->priv;
+
+	return;
+
+#endif
+}
+
+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
+void
+odm_txpowertracking_thermal_meter_check(
+	struct _ADAPTER		*adapter
+)
+{
+#ifndef AP_BUILD_WORKAROUND
+	static u8			tm_trigger = 0;
+
+	if (!(GET_HAL_DATA(adapter)->DM_OutSrc.support_ability & ODM_RF_TX_PWR_TRACK)) {
+		RT_TRACE(COMP_POWER_TRACKING, DBG_LOUD,
+			("===>odm_txpowertracking_thermal_meter_check(),p_mgnt_info->is_txpowertracking is false, return!!\n"));
+		return;
+	}
+
+	if (!tm_trigger) {
+		if (IS_HARDWARE_TYPE_8188E(adapter) || IS_HARDWARE_TYPE_JAGUAR(adapter) || IS_HARDWARE_TYPE_8192E(adapter) ||
+		    IS_HARDWARE_TYPE_8723B(adapter) || IS_HARDWARE_TYPE_8814A(adapter) || IS_HARDWARE_TYPE_8188F(adapter)
+		    || IS_HARDWARE_TYPE_8703B(adapter) || IS_HARDWARE_TYPE_8723D(adapter) || IS_HARDWARE_TYPE_8710B(adapter))/* JJ ADD 20161014 */
+			phy_set_rf_reg(adapter, ODM_RF_PATH_A, RF_T_METER_88E, BIT(17) | BIT(16), 0x03);
+		else
+			phy_set_rf_reg(adapter, ODM_RF_PATH_A, RF_T_METER, RFREGOFFSETMASK, 0x60);
+
+		RT_TRACE(COMP_POWER_TRACKING, DBG_LOUD, ("Trigger Thermal Meter!!\n"));
+
+		tm_trigger = 1;
+		return;
+	} else {
+		RT_TRACE(COMP_POWER_TRACKING, DBG_LOUD, ("Schedule TxPowerTracking direct call!!\n"));
+		odm_txpowertracking_direct_call(adapter);
+		tm_trigger = 0;
+	}
+#endif
+}
+#endif
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/phydm_powertracking_ce.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/phydm_powertracking_ce.h
--- linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/phydm_powertracking_ce.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/phydm_powertracking_ce.h	2020-04-10 16:35:06.826660535 +0300
@@ -0,0 +1,341 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
+ *
+ *
+ ******************************************************************************/
+
+#ifndef	__PHYDMPOWERTRACKING_H__
+#define    __PHYDMPOWERTRACKING_H__
+
+#define POWRTRACKING_VERSION	"1.1"
+
+#define		DPK_DELTA_MAPPING_NUM	13
+#define		index_mapping_HP_NUM	15
+#define	OFDM_TABLE_SIZE	43
+#define	CCK_TABLE_SIZE			33
+#define	CCK_TABLE_SIZE_88F	21
+#define TXSCALE_TABLE_SIZE		37
+#define CCK_TABLE_SIZE_8723D	41
+/* JJ ADD 20161014 */
+#define CCK_TABLE_SIZE_8710B	41
+
+#define TXPWR_TRACK_TABLE_SIZE	30
+#define DELTA_SWINGIDX_SIZE     30
+#define DELTA_SWINTSSI_SIZE     61
+#define BAND_NUM				4
+
+#define AVG_THERMAL_NUM		8
+#define HP_THERMAL_NUM		8
+#define IQK_MAC_REG_NUM		4
+#define IQK_ADDA_REG_NUM		16
+#define IQK_BB_REG_NUM_MAX	10
+
+#define IQK_BB_REG_NUM		9
+
+
+
+#define iqk_matrix_reg_num	8
+#define IQK_MATRIX_SETTINGS_NUM	(14+24+21) /* Channels_2_4G_NUM + Channels_5G_20M_NUM + Channels_5G */
+
+extern	u32 ofdm_swing_table[OFDM_TABLE_SIZE];
+extern	u8 cck_swing_table_ch1_ch13[CCK_TABLE_SIZE][8];
+extern	u8 cck_swing_table_ch14[CCK_TABLE_SIZE][8];
+
+extern	u32 ofdm_swing_table_new[OFDM_TABLE_SIZE];
+extern	u8 cck_swing_table_ch1_ch13_new[CCK_TABLE_SIZE][8];
+extern	u8 cck_swing_table_ch14_new[CCK_TABLE_SIZE][8];
+extern	u8 cck_swing_table_ch1_ch14_88f[CCK_TABLE_SIZE_88F][16];
+extern	u8 cck_swing_table_ch1_ch13_88f[CCK_TABLE_SIZE_88F][16];
+extern	u8 cck_swing_table_ch14_88f[CCK_TABLE_SIZE_88F][16];
+extern	u32 cck_swing_table_ch1_ch14_8723d[CCK_TABLE_SIZE_8723D];
+/* JJ ADD 20161014 */
+extern	u32 cck_swing_table_ch1_ch14_8710b[CCK_TABLE_SIZE_8710B];
+
+extern  u32 tx_scaling_table_jaguar[TXSCALE_TABLE_SIZE];
+
+/* <20121018, Kordan> In case fail to read TxPowerTrack.txt, we use the table of 88E as the default table. */
+static u8 delta_swing_table_idx_2ga_p_8188e[] = {0, 0, 0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 4,  4,  4,  4,  4,  4,  5,  5,  7,  7,  8,  8,  8,  9,  9,  9,  9,  9};
+static u8 delta_swing_table_idx_2ga_n_8188e[] = {0, 0, 0, 2, 2, 3, 3, 4, 4, 4, 4, 5, 5,  6,  6,  7,  7,  7,  7,  8,  8,  9,  9, 10, 10, 10, 11, 11, 11, 11};
+
+#define dm_check_txpowertracking	odm_txpowertracking_check
+
+struct _IQK_MATRIX_REGS_SETTING {
+	boolean	is_iqk_done;
+	s32		value[3][iqk_matrix_reg_num];
+	boolean	is_bw_iqk_result_saved[3];
+};
+
+struct odm_rf_calibration_structure {
+	/* for tx power tracking */
+
+	u32	rega24; /* for TempCCK */
+	s32	rege94;
+	s32	rege9c;
+	s32	regeb4;
+	s32	regebc;
+
+	u8	tx_powercount;
+	boolean is_txpowertracking_init;
+	boolean is_txpowertracking;
+	u8  	txpowertrack_control; /* for mp mode, turn off txpwrtracking as default */
+	u8	tm_trigger;
+	u8  	internal_pa_5g[2];	/* pathA / pathB */
+
+	u8  	thermal_meter[2];    /* thermal_meter, index 0 for RFIC0, and 1 for RFIC1 */
+	u8	thermal_value;
+	u8	thermal_value_lck;
+	u8	thermal_value_iqk;
+	s8  	thermal_value_delta; /* delta of thermal_value and efuse thermal */
+	u8	thermal_value_dpk;
+	u8	thermal_value_avg[AVG_THERMAL_NUM];
+	u8	thermal_value_avg_index;
+	u8	thermal_value_rx_gain;
+	u8	thermal_value_crystal;
+	u8	thermal_value_dpk_store;
+	u8	thermal_value_dpk_track;
+	boolean	txpowertracking_in_progress;
+
+	boolean	is_reloadtxpowerindex;
+	u8	is_rf_pi_enable;
+	u32 	txpowertracking_callback_cnt; /* cosa add for debug */
+
+
+	/* ------------------------- Tx power Tracking ------------------------- */
+	u8	is_cck_in_ch14;
+	u8	CCK_index;
+	u8	OFDM_index[MAX_RF_PATH];
+	s8	power_index_offset[MAX_RF_PATH];
+	s8	delta_power_index[MAX_RF_PATH];
+	s8	delta_power_index_last[MAX_RF_PATH];
+	boolean is_tx_power_changed;
+	s8	xtal_offset;
+	s8	xtal_offset_last;
+
+	u8	thermal_value_hp[HP_THERMAL_NUM];
+	u8	thermal_value_hp_index;
+	struct _IQK_MATRIX_REGS_SETTING iqk_matrix_reg_setting[IQK_MATRIX_SETTINGS_NUM];
+	u8	delta_lck;
+	s8  bb_swing_diff_2g, bb_swing_diff_5g; /* Unit: dB */
+	u8  delta_swing_table_idx_2g_cck_a_p[DELTA_SWINGIDX_SIZE];
+	u8  delta_swing_table_idx_2g_cck_a_n[DELTA_SWINGIDX_SIZE];
+	u8  delta_swing_table_idx_2g_cck_b_p[DELTA_SWINGIDX_SIZE];
+	u8  delta_swing_table_idx_2g_cck_b_n[DELTA_SWINGIDX_SIZE];
+	u8  delta_swing_table_idx_2g_cck_c_p[DELTA_SWINGIDX_SIZE];
+	u8  delta_swing_table_idx_2g_cck_c_n[DELTA_SWINGIDX_SIZE];
+	u8  delta_swing_table_idx_2g_cck_d_p[DELTA_SWINGIDX_SIZE];
+	u8  delta_swing_table_idx_2g_cck_d_n[DELTA_SWINGIDX_SIZE];
+	u8  delta_swing_table_idx_2ga_p[DELTA_SWINGIDX_SIZE];
+	u8  delta_swing_table_idx_2ga_n[DELTA_SWINGIDX_SIZE];
+	u8  delta_swing_table_idx_2gb_p[DELTA_SWINGIDX_SIZE];
+	u8  delta_swing_table_idx_2gb_n[DELTA_SWINGIDX_SIZE];
+	u8  delta_swing_table_idx_2gc_p[DELTA_SWINGIDX_SIZE];
+	u8  delta_swing_table_idx_2gc_n[DELTA_SWINGIDX_SIZE];
+	u8  delta_swing_table_idx_2gd_p[DELTA_SWINGIDX_SIZE];
+	u8  delta_swing_table_idx_2gd_n[DELTA_SWINGIDX_SIZE];
+	u8  delta_swing_table_idx_5ga_p[BAND_NUM][DELTA_SWINGIDX_SIZE];
+	u8  delta_swing_table_idx_5ga_n[BAND_NUM][DELTA_SWINGIDX_SIZE];
+	u8  delta_swing_table_idx_5gb_p[BAND_NUM][DELTA_SWINGIDX_SIZE];
+	u8  delta_swing_table_idx_5gb_n[BAND_NUM][DELTA_SWINGIDX_SIZE];
+	u8  delta_swing_table_idx_5gc_p[BAND_NUM][DELTA_SWINGIDX_SIZE];
+	u8  delta_swing_table_idx_5gc_n[BAND_NUM][DELTA_SWINGIDX_SIZE];
+	u8  delta_swing_table_idx_5gd_p[BAND_NUM][DELTA_SWINGIDX_SIZE];
+	u8  delta_swing_table_idx_5gd_n[BAND_NUM][DELTA_SWINGIDX_SIZE];
+	u8  delta_swing_tssi_table_2g_cck_a[DELTA_SWINTSSI_SIZE];
+	u8  delta_swing_tssi_table_2g_cck_b[DELTA_SWINTSSI_SIZE];
+	u8  delta_swing_tssi_table_2g_cck_c[DELTA_SWINTSSI_SIZE];
+	u8  delta_swing_tssi_table_2g_cck_d[DELTA_SWINTSSI_SIZE];
+	u8  delta_swing_tssi_table_2ga[DELTA_SWINTSSI_SIZE];
+	u8  delta_swing_tssi_table_2gb[DELTA_SWINTSSI_SIZE];
+	u8  delta_swing_tssi_table_2gc[DELTA_SWINTSSI_SIZE];
+	u8  delta_swing_tssi_table_2gd[DELTA_SWINTSSI_SIZE];
+	u8  delta_swing_tssi_table_5ga[BAND_NUM][DELTA_SWINTSSI_SIZE];
+	u8  delta_swing_tssi_table_5gb[BAND_NUM][DELTA_SWINTSSI_SIZE];
+	u8  delta_swing_tssi_table_5gc[BAND_NUM][DELTA_SWINTSSI_SIZE];
+	u8  delta_swing_tssi_table_5gd[BAND_NUM][DELTA_SWINTSSI_SIZE];
+	s8  delta_swing_table_xtal_p[DELTA_SWINGIDX_SIZE];
+	s8  delta_swing_table_xtal_n[DELTA_SWINGIDX_SIZE];
+	u8  delta_swing_table_idx_2ga_p_8188e[DELTA_SWINGIDX_SIZE];
+	u8  delta_swing_table_idx_2ga_n_8188e[DELTA_SWINGIDX_SIZE];
+
+	u8			bb_swing_idx_ofdm[MAX_RF_PATH];
+	u8			bb_swing_idx_ofdm_current;
+#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
+	u8			bb_swing_idx_ofdm_base[MAX_RF_PATH];
+#else
+	u8			bb_swing_idx_ofdm_base;
+#endif
+	boolean		default_bb_swing_index_flag;
+	boolean			bb_swing_flag_ofdm;
+	u8			bb_swing_idx_cck;
+	u8			bb_swing_idx_cck_current;
+	u8			bb_swing_idx_cck_base;
+	u8			default_ofdm_index;
+	u8			default_cck_index;
+	boolean			bb_swing_flag_cck;
+
+	s8			absolute_ofdm_swing_idx[MAX_RF_PATH];
+	s8			remnant_ofdm_swing_idx[MAX_RF_PATH];
+	s8			absolute_cck_swing_idx[MAX_RF_PATH];
+	s8			remnant_cck_swing_idx;
+	s8			modify_tx_agc_value;       /*Remnat compensate value at tx_agc */
+	boolean			modify_tx_agc_flag_path_a;
+	boolean			modify_tx_agc_flag_path_b;
+	boolean			modify_tx_agc_flag_path_c;
+	boolean			modify_tx_agc_flag_path_d;
+	boolean			modify_tx_agc_flag_path_a_cck;
+
+	s8			kfree_offset[MAX_RF_PATH];
+
+	/* -------------------------------------------------------------------- */
+
+	/* for IQK */
+	u32	regc04;
+	u32	reg874;
+	u32	regc08;
+	u32	regb68;
+	u32	regb6c;
+	u32	reg870;
+	u32	reg860;
+	u32	reg864;
+
+	boolean	is_iqk_initialized;
+	boolean is_lck_in_progress;
+	boolean	is_antenna_detected;
+	boolean	is_need_iqk;
+	boolean	is_iqk_in_progress;
+	boolean is_iqk_pa_off;
+	u8	delta_iqk;
+	u32	ADDA_backup[IQK_ADDA_REG_NUM];
+	u32	IQK_MAC_backup[IQK_MAC_REG_NUM];
+	u32	IQK_BB_backup_recover[9];
+	u32	IQK_BB_backup[IQK_BB_REG_NUM];
+	u32 	tx_iqc_8723b[2][3][2]; /* { {S1: 0xc94, 0xc80, 0xc4c} , {S0: 0xc9c, 0xc88, 0xc4c}} */
+	u32 	rx_iqc_8723b[2][2][2]; /* { {S1: 0xc14, 0xca0} ,           {S0: 0xc14, 0xca0}} */
+	u32	tx_iqc_8703b[3][2];	/* { {S1: 0xc94, 0xc80, 0xc4c} , {S0: 0xc9c, 0xc88, 0xc4c}}*/
+	u32	rx_iqc_8703b[2][2];	/* { {S1: 0xc14, 0xca0} ,           {S0: 0xc14, 0xca0}}*/
+	u32	tx_iqc_8723d[2][3][2];	/* { {S1: 0xc94, 0xc80, 0xc4c} , {S0: 0xc9c, 0xc88, 0xc4c}}*/
+	u32	rx_iqc_8723d[2][2][2];	/* { {S1: 0xc14, 0xca0} ,           {S0: 0xc14, 0xca0}}*/
+	/* JJ ADD 20161014 */
+	u32	tx_iqc_8710b[2][3][2];	/* { {S1: 0xc94, 0xc80, 0xc4c} , {S0: 0xc9c, 0xc88, 0xc4c}}*/
+	u32	rx_iqc_8710b[2][2][2];	/* { {S1: 0xc14, 0xca0} ,           {S0: 0xc14, 0xca0}}*/
+
+	u8	iqk_step;
+	u8	kcount;
+	u8	retry_count[4][2]; /* [4]: path ABCD, [2] TXK, RXK */
+	boolean	is_mp_mode;
+
+
+
+	/* <James> IQK time measurement */
+	u64	iqk_start_time;
+	u64	iqk_progressing_time;
+	u64	iqk_total_progressing_time;
+
+	u32  lok_result;
+
+	/* for APK */
+	u32 	ap_koutput[2][2]; /* path A/B; output1_1a/output1_2a */
+	u8	is_ap_kdone;
+	u8	is_apk_thermal_meter_ignore;
+
+	/* DPK */
+	boolean is_dpk_fail;
+	u8	is_dp_done;
+	u8	is_dp_path_aok;
+	u8	is_dp_path_bok;
+
+	u32	tx_lok[2];
+	u32  dpk_tx_agc;
+	s32  dpk_gain;
+	u32  dpk_thermal[4];
+	s8 modify_tx_agc_value_ofdm;
+	s8 modify_tx_agc_value_cck;
+
+	/*Add by Yuchen for Kfree Phydm*/
+	u8			reg_rf_kfree_enable;	/*for registry*/
+	u8			rf_kfree_enable;		/*for efuse enable check*/
+
+};
+
+
+void
+odm_txpowertracking_check(
+	void		*p_dm_void
+);
+
+
+void
+odm_txpowertracking_init(
+	void		*p_dm_void
+);
+
+void
+odm_txpowertracking_check_ap(
+	void		*p_dm_void
+);
+
+void
+odm_txpowertracking_thermal_meter_init(
+	void		*p_dm_void
+);
+
+void
+odm_txpowertracking_init(
+	void		*p_dm_void
+);
+
+void
+odm_txpowertracking_check_mp(
+	void		*p_dm_void
+);
+
+
+void
+odm_txpowertracking_check_ce(
+	void		*p_dm_void
+);
+
+#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN))
+
+void
+odm_txpowertracking_callback_thermal_meter92c(
+	struct _ADAPTER	*adapter
+);
+
+void
+odm_txpowertracking_callback_rx_gain_thermal_meter92d(
+	struct _ADAPTER	*adapter
+);
+
+void
+odm_txpowertracking_callback_thermal_meter92d(
+	struct _ADAPTER	*adapter
+);
+
+void
+odm_txpowertracking_direct_call92c(
+	struct _ADAPTER		*adapter
+);
+
+void
+odm_txpowertracking_thermal_meter_check(
+	struct _ADAPTER		*adapter
+);
+
+#endif
+
+#endif
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/phydm_powertracking_win.c linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/phydm_powertracking_win.c
--- linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/phydm_powertracking_win.c	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/phydm_powertracking_win.c	2020-04-10 16:35:06.826660535 +0300
@@ -0,0 +1,854 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
+ *
+ *
+ ******************************************************************************/
+
+/* ************************************************************
+ * include files
+ * ************************************************************ */
+#include "mp_precomp.h"
+#include "phydm_precomp.h"
+
+/* ************************************************************
+ * Global var
+ * ************************************************************ */
+
+u32	ofdm_swing_table[OFDM_TABLE_SIZE] = {
+	0x7f8001fe,	/* 0, +6.0dB */
+	0x788001e2,	/* 1, +5.5dB */
+	0x71c001c7,	/* 2, +5.0dB */
+	0x6b8001ae,	/* 3, +4.5dB */
+	0x65400195,	/* 4, +4.0dB */
+	0x5fc0017f,	/* 5, +3.5dB */
+	0x5a400169,	/* 6, +3.0dB */
+	0x55400155,	/* 7, +2.5dB */
+	0x50800142,	/* 8, +2.0dB */
+	0x4c000130,	/* 9, +1.5dB */
+	0x47c0011f,	/* 10, +1.0dB */
+	0x43c0010f,	/* 11, +0.5dB */
+	0x40000100,	/* 12, +0dB */
+	0x3c8000f2,	/* 13, -0.5dB */
+	0x390000e4,	/* 14, -1.0dB */
+	0x35c000d7,	/* 15, -1.5dB */
+	0x32c000cb,	/* 16, -2.0dB */
+	0x300000c0,	/* 17, -2.5dB */
+	0x2d4000b5,	/* 18, -3.0dB */
+	0x2ac000ab,	/* 19, -3.5dB */
+	0x288000a2,	/* 20, -4.0dB */
+	0x26000098,	/* 21, -4.5dB */
+	0x24000090,	/* 22, -5.0dB */
+	0x22000088,	/* 23, -5.5dB */
+	0x20000080,	/* 24, -6.0dB */
+	0x1e400079,	/* 25, -6.5dB */
+	0x1c800072,	/* 26, -7.0dB */
+	0x1b00006c,	/* 27. -7.5dB */
+	0x19800066,	/* 28, -8.0dB */
+	0x18000060,	/* 29, -8.5dB */
+	0x16c0005b,	/* 30, -9.0dB */
+	0x15800056,	/* 31, -9.5dB */
+	0x14400051,	/* 32, -10.0dB */
+	0x1300004c,	/* 33, -10.5dB */
+	0x12000048,	/* 34, -11.0dB */
+	0x11000044,	/* 35, -11.5dB */
+	0x10000040,	/* 36, -12.0dB */
+};
+
+u8	cck_swing_table_ch1_ch13[CCK_TABLE_SIZE][8] = {
+	{0x36, 0x35, 0x2e, 0x25, 0x1c, 0x12, 0x09, 0x04},	/* 0, +0dB */
+	{0x33, 0x32, 0x2b, 0x23, 0x1a, 0x11, 0x08, 0x04},	/* 1, -0.5dB */
+	{0x30, 0x2f, 0x29, 0x21, 0x19, 0x10, 0x08, 0x03},	/* 2, -1.0dB */
+	{0x2d, 0x2d, 0x27, 0x1f, 0x18, 0x0f, 0x08, 0x03},	/* 3, -1.5dB */
+	{0x2b, 0x2a, 0x25, 0x1e, 0x16, 0x0e, 0x07, 0x03},	/* 4, -2.0dB */
+	{0x28, 0x28, 0x22, 0x1c, 0x15, 0x0d, 0x07, 0x03},	/* 5, -2.5dB */
+	{0x26, 0x25, 0x21, 0x1b, 0x14, 0x0d, 0x06, 0x03},	/* 6, -3.0dB */
+	{0x24, 0x23, 0x1f, 0x19, 0x13, 0x0c, 0x06, 0x03},	/* 7, -3.5dB */
+	{0x22, 0x21, 0x1d, 0x18, 0x11, 0x0b, 0x06, 0x02},	/* 8, -4.0dB */
+	{0x20, 0x20, 0x1b, 0x16, 0x11, 0x08, 0x05, 0x02},	/* 9, -4.5dB */
+	{0x1f, 0x1e, 0x1a, 0x15, 0x10, 0x0a, 0x05, 0x02},	/* 10, -5.0dB */
+	{0x1d, 0x1c, 0x18, 0x14, 0x0f, 0x0a, 0x05, 0x02},	/* 11, -5.5dB */
+	{0x1b, 0x1a, 0x17, 0x13, 0x0e, 0x09, 0x04, 0x02},	/* 12, -6.0dB <== default */
+	{0x1a, 0x19, 0x16, 0x12, 0x0d, 0x09, 0x04, 0x02},	/* 13, -6.5dB */
+	{0x18, 0x17, 0x15, 0x11, 0x0c, 0x08, 0x04, 0x02},	/* 14, -7.0dB */
+	{0x17, 0x16, 0x13, 0x10, 0x0c, 0x08, 0x04, 0x02},	/* 15, -7.5dB */
+	{0x16, 0x15, 0x12, 0x0f, 0x0b, 0x07, 0x04, 0x01},	/* 16, -8.0dB */
+	{0x14, 0x14, 0x11, 0x0e, 0x0b, 0x07, 0x03, 0x02},	/* 17, -8.5dB */
+	{0x13, 0x13, 0x10, 0x0d, 0x0a, 0x06, 0x03, 0x01},	/* 18, -9.0dB */
+	{0x12, 0x12, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01},	/* 19, -9.5dB */
+	{0x11, 0x11, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01},	/* 20, -10.0dB */
+	{0x10, 0x10, 0x0e, 0x0b, 0x08, 0x05, 0x03, 0x01},	/* 21, -10.5dB */
+	{0x0f, 0x0f, 0x0d, 0x0b, 0x08, 0x05, 0x03, 0x01},	/* 22, -11.0dB */
+	{0x0e, 0x0e, 0x0c, 0x0a, 0x08, 0x05, 0x02, 0x01},	/* 23, -11.5dB */
+	{0x0d, 0x0d, 0x0c, 0x0a, 0x07, 0x05, 0x02, 0x01},	/* 24, -12.0dB */
+	{0x0d, 0x0c, 0x0b, 0x09, 0x07, 0x04, 0x02, 0x01},	/* 25, -12.5dB */
+	{0x0c, 0x0c, 0x0a, 0x09, 0x06, 0x04, 0x02, 0x01},	/* 26, -13.0dB */
+	{0x0b, 0x0b, 0x0a, 0x08, 0x06, 0x04, 0x02, 0x01},	/* 27, -13.5dB */
+	{0x0b, 0x0a, 0x09, 0x08, 0x06, 0x04, 0x02, 0x01},	/* 28, -14.0dB */
+	{0x0a, 0x0a, 0x09, 0x07, 0x05, 0x03, 0x02, 0x01},	/* 29, -14.5dB */
+	{0x0a, 0x09, 0x08, 0x07, 0x05, 0x03, 0x02, 0x01},	/* 30, -15.0dB */
+	{0x09, 0x09, 0x08, 0x06, 0x05, 0x03, 0x01, 0x01},	/* 31, -15.5dB */
+	{0x09, 0x08, 0x07, 0x06, 0x04, 0x03, 0x01, 0x01}	/* 32, -16.0dB */
+};
+
+
+u8	cck_swing_table_ch14[CCK_TABLE_SIZE][8] = {
+	{0x36, 0x35, 0x2e, 0x1b, 0x00, 0x00, 0x00, 0x00},	/* 0, +0dB */
+	{0x33, 0x32, 0x2b, 0x19, 0x00, 0x00, 0x00, 0x00},	/* 1, -0.5dB */
+	{0x30, 0x2f, 0x29, 0x18, 0x00, 0x00, 0x00, 0x00},	/* 2, -1.0dB */
+	{0x2d, 0x2d, 0x17, 0x17, 0x00, 0x00, 0x00, 0x00},	/* 3, -1.5dB */
+	{0x2b, 0x2a, 0x25, 0x15, 0x00, 0x00, 0x00, 0x00},	/* 4, -2.0dB */
+	{0x28, 0x28, 0x24, 0x14, 0x00, 0x00, 0x00, 0x00},	/* 5, -2.5dB */
+	{0x26, 0x25, 0x21, 0x13, 0x00, 0x00, 0x00, 0x00},	/* 6, -3.0dB */
+	{0x24, 0x23, 0x1f, 0x12, 0x00, 0x00, 0x00, 0x00},	/* 7, -3.5dB */
+	{0x22, 0x21, 0x1d, 0x11, 0x00, 0x00, 0x00, 0x00},	/* 8, -4.0dB */
+	{0x20, 0x20, 0x1b, 0x10, 0x00, 0x00, 0x00, 0x00},	/* 9, -4.5dB */
+	{0x1f, 0x1e, 0x1a, 0x0f, 0x00, 0x00, 0x00, 0x00},	/* 10, -5.0dB */
+	{0x1d, 0x1c, 0x18, 0x0e, 0x00, 0x00, 0x00, 0x00},	/* 11, -5.5dB */
+	{0x1b, 0x1a, 0x17, 0x0e, 0x00, 0x00, 0x00, 0x00},	/* 12, -6.0dB  <== default */
+	{0x1a, 0x19, 0x16, 0x0d, 0x00, 0x00, 0x00, 0x00},	/* 13, -6.5dB */
+	{0x18, 0x17, 0x15, 0x0c, 0x00, 0x00, 0x00, 0x00},	/* 14, -7.0dB */
+	{0x17, 0x16, 0x13, 0x0b, 0x00, 0x00, 0x00, 0x00},	/* 15, -7.5dB */
+	{0x16, 0x15, 0x12, 0x0b, 0x00, 0x00, 0x00, 0x00},	/* 16, -8.0dB */
+	{0x14, 0x14, 0x11, 0x0a, 0x00, 0x00, 0x00, 0x00},	/* 17, -8.5dB */
+	{0x13, 0x13, 0x10, 0x0a, 0x00, 0x00, 0x00, 0x00},	/* 18, -9.0dB */
+	{0x12, 0x12, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00},	/* 19, -9.5dB */
+	{0x11, 0x11, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00},	/* 20, -10.0dB */
+	{0x10, 0x10, 0x0e, 0x08, 0x00, 0x00, 0x00, 0x00},	/* 21, -10.5dB */
+	{0x0f, 0x0f, 0x0d, 0x08, 0x00, 0x00, 0x00, 0x00},	/* 22, -11.0dB */
+	{0x0e, 0x0e, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00},	/* 23, -11.5dB */
+	{0x0d, 0x0d, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00},	/* 24, -12.0dB */
+	{0x0d, 0x0c, 0x0b, 0x06, 0x00, 0x00, 0x00, 0x00},	/* 25, -12.5dB */
+	{0x0c, 0x0c, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00},	/* 26, -13.0dB */
+	{0x0b, 0x0b, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00},	/* 27, -13.5dB */
+	{0x0b, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00},	/* 28, -14.0dB */
+	{0x0a, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00},	/* 29, -14.5dB */
+	{0x0a, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00},	/* 30, -15.0dB */
+	{0x09, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00},	/* 31, -15.5dB */
+	{0x09, 0x08, 0x07, 0x04, 0x00, 0x00, 0x00, 0x00}	/* 32, -16.0dB */
+};
+
+
+u32 ofdm_swing_table_new[OFDM_TABLE_SIZE] = {
+	0x0b40002d, /* 0,  -15.0dB */
+	0x0c000030, /* 1,  -14.5dB */
+	0x0cc00033, /* 2,  -14.0dB */
+	0x0d800036, /* 3,  -13.5dB */
+	0x0e400039, /* 4,  -13.0dB */
+	0x0f00003c, /* 5,  -12.5dB */
+	0x10000040, /* 6,  -12.0dB */
+	0x11000044, /* 7,  -11.5dB */
+	0x12000048, /* 8,  -11.0dB */
+	0x1300004c, /* 9,  -10.5dB */
+	0x14400051, /* 10, -10.0dB */
+	0x15800056, /* 11, -9.5dB */
+	0x16c0005b, /* 12, -9.0dB */
+	0x18000060, /* 13, -8.5dB */
+	0x19800066, /* 14, -8.0dB */
+	0x1b00006c, /* 15, -7.5dB */
+	0x1c800072, /* 16, -7.0dB */
+	0x1e400079, /* 17, -6.5dB */
+	0x20000080, /* 18, -6.0dB */
+	0x22000088, /* 19, -5.5dB */
+	0x24000090, /* 20, -5.0dB */
+	0x26000098, /* 21, -4.5dB */
+	0x288000a2, /* 22, -4.0dB */
+	0x2ac000ab, /* 23, -3.5dB */
+	0x2d4000b5, /* 24, -3.0dB */
+	0x300000c0, /* 25, -2.5dB */
+	0x32c000cb, /* 26, -2.0dB */
+	0x35c000d7, /* 27, -1.5dB */
+	0x390000e4, /* 28, -1.0dB */
+	0x3c8000f2, /* 29, -0.5dB */
+	0x40000100, /* 30, +0dB */
+	0x43c0010f, /* 31, +0.5dB */
+	0x47c0011f, /* 32, +1.0dB */
+	0x4c000130, /* 33, +1.5dB */
+	0x50800142, /* 34, +2.0dB */
+	0x55400155, /* 35, +2.5dB */
+	0x5a400169, /* 36, +3.0dB */
+	0x5fc0017f, /* 37, +3.5dB */
+	0x65400195, /* 38, +4.0dB */
+	0x6b8001ae, /* 39, +4.5dB */
+	0x71c001c7, /* 40, +5.0dB */
+	0x788001e2, /* 41, +5.5dB */
+	0x7f8001fe  /* 42, +6.0dB */
+};
+
+
+u8 cck_swing_table_ch1_ch14_88f[CCK_TABLE_SIZE_88F][16] = {
+	{0x44, 0x42, 0x3C, 0x33, 0x28, 0x1C, 0x13, 0x0B, 0x05, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-16dB*/
+	{0x48, 0x46, 0x3F, 0x36, 0x2A, 0x1E, 0x14, 0x0B, 0x05, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-15.5dB*/
+	{0x4D, 0x4A, 0x43, 0x39, 0x2C, 0x20, 0x15, 0x0C, 0x06, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-15dB*/
+	{0x51, 0x4F, 0x47, 0x3C, 0x2F, 0x22, 0x16, 0x0D, 0x06, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-14.5dB*/
+	{0x56, 0x53, 0x4B, 0x40, 0x32, 0x24, 0x17, 0x0E, 0x06, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-14dB*/
+	{0x5B, 0x58, 0x50, 0x43, 0x35, 0x26, 0x19, 0x0E, 0x07, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-13.5dB*/
+	{0x60, 0x5D, 0x54, 0x47, 0x38, 0x28, 0x1A, 0x0F, 0x07, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-13dB*/
+	{0x66, 0x63, 0x59, 0x4C, 0x3B, 0x2B, 0x1C, 0x10, 0x08, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-12.5dB*/
+	{0x6C, 0x69, 0x5F, 0x50, 0x3F, 0x2D, 0x1E, 0x11, 0x08, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-12dB*/
+	{0x73, 0x6F, 0x64, 0x55, 0x42, 0x30, 0x1F, 0x12, 0x08, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-11.5dB*/
+	{0x79, 0x76, 0x6A, 0x5A, 0x46, 0x33, 0x21, 0x13, 0x09, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-11dB*/
+	{0x81, 0x7C, 0x71, 0x5F, 0x4A, 0x36, 0x23, 0x14, 0x0A, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-10.5dB*/
+	{0x88, 0x84, 0x77, 0x65, 0x4F, 0x39, 0x25, 0x15, 0x0A, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-10dB*/
+	{0x90, 0x8C, 0x7E, 0x6B, 0x54, 0x3C, 0x27, 0x17, 0x0B, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-9.5dB*/
+	{0x99, 0x94, 0x86, 0x71, 0x58, 0x40, 0x2A, 0x18, 0x0B, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-9dB*/
+	{0xA2, 0x9D, 0x8E, 0x78, 0x5E, 0x43, 0x2C, 0x19, 0x0C, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-8.5dB*/
+	{0xAC, 0xA6, 0x96, 0x7F, 0x63, 0x47, 0x2F, 0x1B, 0x0D, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-8dB*/
+	{0xB6, 0xB0, 0x9F, 0x87, 0x69, 0x4C, 0x32, 0x1D, 0x0D, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-7.5dB*/
+	{0xC1, 0xBA, 0xA8, 0x8F, 0x6F, 0x50, 0x35, 0x1E, 0x0E, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-7dB*/
+	{0xCC, 0xC5, 0xB2, 0x97, 0x76, 0x55, 0x38, 0x20, 0x0F, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-6.5dB*/
+	{0xD8, 0xD1, 0xBD, 0xA0, 0x7D, 0x5A, 0x3B, 0x22, 0x10, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}     /*-6dB*/
+};
+
+
+u8 cck_swing_table_ch1_ch13_88f[CCK_TABLE_SIZE_88F][16] = {
+	{0x44, 0x42, 0x3C, 0x33, 0x28, 0x1C, 0x13, 0x0B, 0x05, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-16dB*/
+	{0x48, 0x46, 0x3F, 0x36, 0x2A, 0x1E, 0x14, 0x0B, 0x05, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-15.5dB*/
+	{0x4D, 0x4A, 0x43, 0x39, 0x2C, 0x20, 0x15, 0x0C, 0x06, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-15dB*/
+	{0x51, 0x4F, 0x47, 0x3C, 0x2F, 0x22, 0x16, 0x0D, 0x06, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-14.5dB*/
+	{0x56, 0x53, 0x4B, 0x40, 0x32, 0x24, 0x17, 0x0E, 0x06, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-14dB*/
+	{0x5B, 0x58, 0x50, 0x43, 0x35, 0x26, 0x19, 0x0E, 0x07, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-13.5dB*/
+	{0x60, 0x5D, 0x54, 0x47, 0x38, 0x28, 0x1A, 0x0F, 0x07, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-13dB*/
+	{0x66, 0x63, 0x59, 0x4C, 0x3B, 0x2B, 0x1C, 0x10, 0x08, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-12.5dB*/
+	{0x6C, 0x69, 0x5F, 0x50, 0x3F, 0x2D, 0x1E, 0x11, 0x08, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-12dB*/
+	{0x73, 0x6F, 0x64, 0x55, 0x42, 0x30, 0x1F, 0x12, 0x08, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-11.5dB*/
+	{0x79, 0x76, 0x6A, 0x5A, 0x46, 0x33, 0x21, 0x13, 0x09, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-11dB*/
+	{0x81, 0x7C, 0x71, 0x5F, 0x4A, 0x36, 0x23, 0x14, 0x0A, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-10.5dB*/
+	{0x88, 0x84, 0x77, 0x65, 0x4F, 0x39, 0x25, 0x15, 0x0A, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-10dB*/
+	{0x90, 0x8C, 0x7E, 0x6B, 0x54, 0x3C, 0x27, 0x17, 0x0B, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-9.5dB*/
+	{0x99, 0x94, 0x86, 0x71, 0x58, 0x40, 0x2A, 0x18, 0x0B, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-9dB*/
+	{0xA2, 0x9D, 0x8E, 0x78, 0x5E, 0x43, 0x2C, 0x19, 0x0C, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-8.5dB*/
+	{0xAC, 0xA6, 0x96, 0x7F, 0x63, 0x47, 0x2F, 0x1B, 0x0D, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-8dB*/
+	{0xB6, 0xB0, 0x9F, 0x87, 0x69, 0x4C, 0x32, 0x1D, 0x0D, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-7.5dB*/
+	{0xC1, 0xBA, 0xA8, 0x8F, 0x6F, 0x50, 0x35, 0x1E, 0x0E, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-7dB*/
+	{0xCC, 0xC5, 0xB2, 0x97, 0x76, 0x55, 0x38, 0x20, 0x0F, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-6.5dB*/
+	{0xD8, 0xD1, 0xBD, 0xA0, 0x7D, 0x5A, 0x3B, 0x22, 0x10, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}     /*-6dB*/
+};
+
+
+u8 cck_swing_table_ch14_88f[CCK_TABLE_SIZE_88F][16] = {
+	{0x44,	 0x42, 0x3C, 0x28, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-16dB*/
+	{0x48, 0x46, 0x3F, 0x2A, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-15.5dB*/
+	{0x4D, 0x4A, 0x43, 0x2C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-15dB*/
+	{0x51, 0x4F, 0x47, 0x2F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},	    /*-14.5dB*/
+	{0x56, 0x53, 0x4B, 0x32, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-14dB*/
+	{0x5B, 0x58, 0x50, 0x35, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-13.5dB*/
+	{0x60, 0x5D, 0x54, 0x38, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-13dB*/
+	{0x66, 0x63, 0x59, 0x3B, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-12.5dB*/
+	{0x6C, 0x69, 0x5F, 0x3F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-12dB*/
+	{0x73, 0x6F, 0x64, 0x42, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-11.5dB*/
+	{0x79, 0x76, 0x6A, 0x46, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-11dB*/
+	{0x81, 0x7C, 0x71, 0x4A, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-10.5dB*/
+	{0x88, 0x84, 0x77, 0x4F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-10dB*/
+	{0x90, 0x8C, 0x7E, 0x54, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-9.5dB*/
+	{0x99, 0x94, 0x86, 0x58, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-9dB*/
+	{0xA2, 0x9D, 0x8E, 0x5E, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-8.5dB*/
+	{0xAC, 0xA6, 0x96, 0x63, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-8dB*/
+	{0xB6, 0xB0, 0x9F, 0x69, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-7.5dB*/
+	{0xC1, 0xBA, 0xA8, 0x6F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-7dB*/
+	{0xCC, 0xC5, 0xB2, 0x76, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-6.5dB*/
+	{0xD8, 0xD1, 0xBD, 0x7D, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}     /*-6dB*/
+};
+
+
+u8 cck_swing_table_ch1_ch13_new[CCK_TABLE_SIZE][8] = {
+	{0x09, 0x08, 0x07, 0x06, 0x04, 0x03, 0x01, 0x01},	/* 0, -16.0dB */
+	{0x09, 0x09, 0x08, 0x06, 0x05, 0x03, 0x01, 0x01},	/* 1, -15.5dB */
+	{0x0a, 0x09, 0x08, 0x07, 0x05, 0x03, 0x02, 0x01},	/* 2, -15.0dB */
+	{0x0a, 0x0a, 0x09, 0x07, 0x05, 0x03, 0x02, 0x01},	/* 3, -14.5dB */
+	{0x0b, 0x0a, 0x09, 0x08, 0x06, 0x04, 0x02, 0x01},	/* 4, -14.0dB */
+	{0x0b, 0x0b, 0x0a, 0x08, 0x06, 0x04, 0x02, 0x01},	/* 5, -13.5dB */
+	{0x0c, 0x0c, 0x0a, 0x09, 0x06, 0x04, 0x02, 0x01},	/* 6, -13.0dB */
+	{0x0d, 0x0c, 0x0b, 0x09, 0x07, 0x04, 0x02, 0x01},	/* 7, -12.5dB */
+	{0x0d, 0x0d, 0x0c, 0x0a, 0x07, 0x05, 0x02, 0x01},	/* 8, -12.0dB */
+	{0x0e, 0x0e, 0x0c, 0x0a, 0x08, 0x05, 0x02, 0x01},	/* 9, -11.5dB */
+	{0x0f, 0x0f, 0x0d, 0x0b, 0x08, 0x05, 0x03, 0x01},	/* 10, -11.0dB */
+	{0x10, 0x10, 0x0e, 0x0b, 0x08, 0x05, 0x03, 0x01},	/* 11, -10.5dB */
+	{0x11, 0x11, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01},	/* 12, -10.0dB */
+	{0x12, 0x12, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01},	/* 13, -9.5dB */
+	{0x13, 0x13, 0x10, 0x0d, 0x0a, 0x06, 0x03, 0x01},	/* 14, -9.0dB */
+	{0x14, 0x14, 0x11, 0x0e, 0x0b, 0x07, 0x03, 0x02},	/* 15, -8.5dB */
+	{0x16, 0x15, 0x12, 0x0f, 0x0b, 0x07, 0x04, 0x01},	/* 16, -8.0dB */
+	{0x17, 0x16, 0x13, 0x10, 0x0c, 0x08, 0x04, 0x02},	/* 17, -7.5dB */
+	{0x18, 0x17, 0x15, 0x11, 0x0c, 0x08, 0x04, 0x02},	/* 18, -7.0dB */
+	{0x1a, 0x19, 0x16, 0x12, 0x0d, 0x09, 0x04, 0x02},	/* 19, -6.5dB */
+	{0x1b, 0x1a, 0x17, 0x13, 0x0e, 0x09, 0x04, 0x02},	/* 20, -6.0dB */
+	{0x1d, 0x1c, 0x18, 0x14, 0x0f, 0x0a, 0x05, 0x02},	/* 21, -5.5dB */
+	{0x1f, 0x1e, 0x1a, 0x15, 0x10, 0x0a, 0x05, 0x02},	/* 22, -5.0dB */
+	{0x20, 0x20, 0x1b, 0x16, 0x11, 0x08, 0x05, 0x02},	/* 23, -4.5dB */
+	{0x22, 0x21, 0x1d, 0x18, 0x11, 0x0b, 0x06, 0x02},	/* 24, -4.0dB */
+	{0x24, 0x23, 0x1f, 0x19, 0x13, 0x0c, 0x06, 0x03},	/* 25, -3.5dB */
+	{0x26, 0x25, 0x21, 0x1b, 0x14, 0x0d, 0x06, 0x03},	/* 26, -3.0dB */
+	{0x28, 0x28, 0x22, 0x1c, 0x15, 0x0d, 0x07, 0x03},	/* 27, -2.5dB */
+	{0x2b, 0x2a, 0x25, 0x1e, 0x16, 0x0e, 0x07, 0x03},	/* 28, -2.0dB */
+	{0x2d, 0x2d, 0x27, 0x1f, 0x18, 0x0f, 0x08, 0x03},	/* 29, -1.5dB */
+	{0x30, 0x2f, 0x29, 0x21, 0x19, 0x10, 0x08, 0x03},	/* 30, -1.0dB */
+	{0x33, 0x32, 0x2b, 0x23, 0x1a, 0x11, 0x08, 0x04},	/* 31, -0.5dB */
+	{0x36, 0x35, 0x2e, 0x25, 0x1c, 0x12, 0x09, 0x04}	/* 32, +0dB */
+};
+
+
+u8 cck_swing_table_ch14_new[CCK_TABLE_SIZE][8] = {
+	{0x09, 0x08, 0x07, 0x04, 0x00, 0x00, 0x00, 0x00},	/* 0, -16.0dB */
+	{0x09, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00},	/* 1, -15.5dB */
+	{0x0a, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00},	/* 2, -15.0dB */
+	{0x0a, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00},	/* 3, -14.5dB */
+	{0x0b, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00},	/* 4, -14.0dB */
+	{0x0b, 0x0b, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00},	/* 5, -13.5dB */
+	{0x0c, 0x0c, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00},	/* 6, -13.0dB */
+	{0x0d, 0x0c, 0x0b, 0x06, 0x00, 0x00, 0x00, 0x00},	/* 7, -12.5dB */
+	{0x0d, 0x0d, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00},	/* 8, -12.0dB */
+	{0x0e, 0x0e, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00},	/* 9, -11.5dB */
+	{0x0f, 0x0f, 0x0d, 0x08, 0x00, 0x00, 0x00, 0x00},	/* 10, -11.0dB */
+	{0x10, 0x10, 0x0e, 0x08, 0x00, 0x00, 0x00, 0x00},	/* 11, -10.5dB */
+	{0x11, 0x11, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00},	/* 12, -10.0dB */
+	{0x12, 0x12, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00},	/* 13, -9.5dB */
+	{0x13, 0x13, 0x10, 0x0a, 0x00, 0x00, 0x00, 0x00},	/* 14, -9.0dB */
+	{0x14, 0x14, 0x11, 0x0a, 0x00, 0x00, 0x00, 0x00},	/* 15, -8.5dB */
+	{0x16, 0x15, 0x12, 0x0b, 0x00, 0x00, 0x00, 0x00},	/* 16, -8.0dB */
+	{0x17, 0x16, 0x13, 0x0b, 0x00, 0x00, 0x00, 0x00},	/* 17, -7.5dB */
+	{0x18, 0x17, 0x15, 0x0c, 0x00, 0x00, 0x00, 0x00},	/* 18, -7.0dB */
+	{0x1a, 0x19, 0x16, 0x0d, 0x00, 0x00, 0x00, 0x00},	/* 19, -6.5dB */
+	{0x1b, 0x1a, 0x17, 0x0e, 0x00, 0x00, 0x00, 0x00},	/* 20, -6.0dB */
+	{0x1d, 0x1c, 0x18, 0x0e, 0x00, 0x00, 0x00, 0x00},	/* 21, -5.5dB */
+	{0x1f, 0x1e, 0x1a, 0x0f, 0x00, 0x00, 0x00, 0x00},	/* 22, -5.0dB */
+	{0x20, 0x20, 0x1b, 0x10, 0x00, 0x00, 0x00, 0x00},	/* 23, -4.5dB */
+	{0x22, 0x21, 0x1d, 0x11, 0x00, 0x00, 0x00, 0x00},	/* 24, -4.0dB */
+	{0x24, 0x23, 0x1f, 0x12, 0x00, 0x00, 0x00, 0x00},	/* 25, -3.5dB */
+	{0x26, 0x25, 0x21, 0x13, 0x00, 0x00, 0x00, 0x00},	/* 26, -3.0dB */
+	{0x28, 0x28, 0x24, 0x14, 0x00, 0x00, 0x00, 0x00},	/* 27, -2.5dB */
+	{0x2b, 0x2a, 0x25, 0x15, 0x00, 0x00, 0x00, 0x00},	/* 28, -2.0dB */
+	{0x2d, 0x2d, 0x17, 0x17, 0x00, 0x00, 0x00, 0x00},	/* 29, -1.5dB */
+	{0x30, 0x2f, 0x29, 0x18, 0x00, 0x00, 0x00, 0x00},	/* 30, -1.0dB */
+	{0x33, 0x32, 0x2b, 0x19, 0x00, 0x00, 0x00, 0x00},	/* 31, -0.5dB */
+	{0x36, 0x35, 0x2e, 0x1b, 0x00, 0x00, 0x00, 0x00}	/* 32, +0dB */
+};
+u32 cck_swing_table_ch1_ch14_8723d[CCK_TABLE_SIZE_8723D] = {
+	0x0CD,
+	0x0D9,
+	0x0E6,
+	0x0F3,
+	0x102,
+	0x111,
+	0x121,
+	0x132,
+	0x144,
+	0x158,
+	0x16C,
+	0x182,
+	0x198,
+	0x1B1,
+	0x1CA,
+	0x1E5,
+	0x202,
+	0x221,
+	0x241,
+	0x263,
+	0x287,
+	0x2AE,
+	0x2D6,
+	0x301,
+	0x32F,
+	0x35F,
+	0x392,
+	0x3C9,
+	0x402,
+	0x43F,
+	0x47F,
+	0x4C3,
+	0x50C,
+	0x558,
+	0x5A9,
+	0x5FF,
+	0x65A,
+	0x6BA,
+	0x720,
+	0x78C,
+	0x7FF,
+};
+/* JJ ADD 20161014 */
+u32 cck_swing_table_ch1_ch14_8710b[CCK_TABLE_SIZE_8710B] = {
+	0x0CD,			 /*0 ,    -20dB*/
+	0x0D9,
+	0x0E6,
+	0x0F3,
+	0x102,
+	0x111,
+	0x121,
+	0x132,
+	0x144,
+	0x158,
+	0x16C,
+	0x182,
+	0x198,
+	0x1B1,
+	0x1CA,
+	0x1E5,
+	0x202,
+	0x221,
+	0x241,
+	0x263,		/*19*/
+	0x287,		/*20*/
+	0x2AE,		/*21*/
+	0x2D6,		/*22*/
+	0x301,		/*23*/
+	0x32F,		/*24*/
+	0x35F,		/*25*/
+	0x392,		/*26*/
+	0x3C9,		/*27*/
+	0x402,		/*28*/
+	0x43F,		/*29*/
+	0x47F,		/*30*/
+	0x4C3,		/*31*/
+	0x50C,		/*32*/
+	0x558,		/*33*/
+	0x5A9,		/*34*/
+	0x5FF,		/*35*/
+	0x65A,		/*36*/
+	0x6BA,
+	0x720,
+	0x78C,
+	0x7FF,
+};
+
+
+u32 tx_scaling_table_jaguar[TXSCALE_TABLE_SIZE] = {
+	0x081, /* 0,  -12.0dB */
+	0x088, /* 1,  -11.5dB */
+	0x090, /* 2,  -11.0dB */
+	0x099, /* 3,  -10.5dB */
+	0x0A2, /* 4,  -10.0dB */
+	0x0AC, /* 5,  -9.5dB */
+	0x0B6, /* 6,  -9.0dB */
+	0x0C0, /* 7,  -8.5dB */
+	0x0CC, /* 8,  -8.0dB */
+	0x0D8, /* 9,  -7.5dB */
+	0x0E5, /* 10, -7.0dB */
+	0x0F2, /* 11, -6.5dB */
+	0x101, /* 12, -6.0dB */
+	0x110, /* 13, -5.5dB */
+	0x120, /* 14, -5.0dB */
+	0x131, /* 15, -4.5dB */
+	0x143, /* 16, -4.0dB */
+	0x156, /* 17, -3.5dB */
+	0x16A, /* 18, -3.0dB */
+	0x180, /* 19, -2.5dB */
+	0x197, /* 20, -2.0dB */
+	0x1AF, /* 21, -1.5dB */
+	0x1C8, /* 22, -1.0dB */
+	0x1E3, /* 23, -0.5dB */
+	0x200, /* 24, +0  dB */
+	0x21E, /* 25, +0.5dB */
+	0x23E, /* 26, +1.0dB */
+	0x261, /* 27, +1.5dB */
+	0x285, /* 28, +2.0dB */
+	0x2AB, /* 29, +2.5dB */
+	0x2D3, /* 30, +3.0dB */
+	0x2FE, /* 31, +3.5dB */
+	0x32B, /* 32, +4.0dB */
+	0x35C, /* 33, +4.5dB */
+	0x38E, /* 34, +5.0dB */
+	0x3C4, /* 35, +5.5dB */
+	0x3FE  /* 36, +6.0dB */
+};
+
+
+#ifdef AP_BUILD_WORKAROUND
+
+unsigned int tx_pwr_trk_ofdm_swing_tbl[tx_pwr_trk_ofdm_swing_tbl_len] = {
+	/*  +6.0dB */ 0x7f8001fe,
+	/*  +5.5dB */ 0x788001e2,
+	/*  +5.0dB */ 0x71c001c7,
+	/*  +4.5dB */ 0x6b8001ae,
+	/*  +4.0dB */ 0x65400195,
+	/*  +3.5dB */ 0x5fc0017f,
+	/*  +3.0dB */ 0x5a400169,
+	/*  +2.5dB */ 0x55400155,
+	/*  +2.0dB */ 0x50800142,
+	/*  +1.5dB */ 0x4c000130,
+	/*  +1.0dB */ 0x47c0011f,
+	/*  +0.5dB */ 0x43c0010f,
+	/*   0.0dB */ 0x40000100,
+	/*  -0.5dB */ 0x3c8000f2,
+	/*  -1.0dB */ 0x390000e4,
+	/*  -1.5dB */ 0x35c000d7,
+	/*  -2.0dB */ 0x32c000cb,
+	/*  -2.5dB */ 0x300000c0,
+	/*  -3.0dB */ 0x2d4000b5,
+	/*  -3.5dB */ 0x2ac000ab,
+	/*  -4.0dB */ 0x288000a2,
+	/*  -4.5dB */ 0x26000098,
+	/*  -5.0dB */ 0x24000090,
+	/*  -5.5dB */ 0x22000088,
+	/*  -6.0dB */ 0x20000080,
+	/*  -6.5dB */ 0x1a00006c,
+	/*  -7.0dB */ 0x1c800072,
+	/*  -7.5dB */ 0x18000060,
+	/*  -8.0dB */ 0x19800066,
+	/*  -8.5dB */ 0x15800056,
+	/*  -9.0dB */ 0x26c0005b,
+	/*  -9.5dB */ 0x14400051,
+	/* -10.0dB */ 0x24400051,
+	/* -10.5dB */ 0x1300004c,
+	/* -11.0dB */ 0x12000048,
+	/* -11.5dB */ 0x11000044,
+	/* -12.0dB */ 0x10000040
+};
+
+#endif
+
+void
+odm_txpowertracking_init(
+	void		*p_dm_void
+)
+{
+	struct PHY_DM_STRUCT		*p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
+#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
+	if (!(p_dm_odm->support_ic_type & (ODM_RTL8814A | ODM_IC_11N_SERIES | ODM_RTL8822B)))
+		return;
+#endif
+
+	odm_txpowertracking_thermal_meter_init(p_dm_odm);
+}
+
+u8
+get_swing_index(
+	void		*p_dm_void
+)
+{
+	struct PHY_DM_STRUCT		*p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
+	struct _ADAPTER		*adapter = p_dm_odm->adapter;
+	HAL_DATA_TYPE	*p_hal_data = GET_HAL_DATA(adapter);
+	u8			i = 0;
+	u32			bb_swing;
+	u32			swing_table_size;
+	u32			*p_swing_table;
+
+	if (p_dm_odm->support_ic_type == ODM_RTL8188E || p_dm_odm->support_ic_type == ODM_RTL8723B ||
+	    p_dm_odm->support_ic_type == ODM_RTL8192E || p_dm_odm->support_ic_type == ODM_RTL8188F || p_dm_odm->support_ic_type == ODM_RTL8703B) {
+		bb_swing = odm_get_bb_reg(p_dm_odm, REG_OFDM_0_XA_TX_IQ_IMBALANCE, 0xFFC00000);
+
+		p_swing_table = ofdm_swing_table_new;
+		swing_table_size = OFDM_TABLE_SIZE;
+	} else {
+		bb_swing = PHY_GetTxBBSwing_8812A(adapter, p_hal_data->CurrentBandType, ODM_RF_PATH_A);
+		p_swing_table = tx_scaling_table_jaguar;
+		swing_table_size = TXSCALE_TABLE_SIZE;
+	}
+
+	for (i = 0; i < swing_table_size; ++i) {
+		u32 table_value = p_swing_table[i];
+
+		if (table_value >= 0x100000)
+			table_value >>= 22;
+		if (bb_swing == table_value)
+			break;
+	}
+	return i;
+}
+
+u8
+get_cck_swing_index(
+	void		*p_dm_void
+)
+{
+	struct PHY_DM_STRUCT		*p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
+
+	u8			i = 0;
+	u32			bb_cck_swing;
+
+	if (p_dm_odm->support_ic_type == ODM_RTL8188E || p_dm_odm->support_ic_type == ODM_RTL8723B ||
+	    p_dm_odm->support_ic_type == ODM_RTL8192E) {
+		bb_cck_swing = odm_read_1byte(p_dm_odm, 0xa22);
+
+		for (i = 0; i < CCK_TABLE_SIZE; i++) {
+			if (bb_cck_swing == cck_swing_table_ch1_ch13_new[i][0])
+				break;
+		}
+	} else if (p_dm_odm->support_ic_type == ODM_RTL8703B) {
+		bb_cck_swing = odm_read_1byte(p_dm_odm, 0xa22);
+
+		for (i = 0; i < CCK_TABLE_SIZE_88F; i++) {
+			if (bb_cck_swing == cck_swing_table_ch1_ch14_88f[i][0])
+				break;
+		}
+	}
+
+	return i;
+}
+
+
+void
+odm_txpowertracking_thermal_meter_init(
+	void		*p_dm_void
+)
+{
+	struct PHY_DM_STRUCT		*p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
+	u8 default_swing_index = get_swing_index(p_dm_odm);
+	u8 default_cck_swing_index = get_cck_swing_index(p_dm_odm);
+	struct odm_rf_calibration_structure	*p_rf_calibrate_info = &(p_dm_odm->rf_calibrate_info);
+
+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
+	struct _ADAPTER		*adapter = p_dm_odm->adapter;
+	HAL_DATA_TYPE	*p_hal_data = GET_HAL_DATA(adapter);
+	u8			p = 0;
+
+	if (p_dm_odm->mp_mode == false)
+		p_rf_calibrate_info->txpowertrack_control = true;
+#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
+#ifdef CONFIG_RTL8188E
+	{
+		p_rf_calibrate_info->is_txpowertracking = _TRUE;
+		p_rf_calibrate_info->tx_powercount = 0;
+		p_rf_calibrate_info->is_txpowertracking_init = _FALSE;
+
+		if (p_dm_odm->mp_mode == false)
+			p_rf_calibrate_info->txpowertrack_control = _TRUE;
+
+		MSG_8192C("p_dm_odm txpowertrack_control = %d\n", p_rf_calibrate_info->txpowertrack_control);
+	}
+#else
+	{
+		struct _ADAPTER		*adapter = p_dm_odm->adapter;
+		HAL_DATA_TYPE	*p_hal_data = GET_HAL_DATA(adapter);
+		struct dm_priv	*pdmpriv = &p_hal_data->dmpriv;
+
+		pdmpriv->is_txpowertracking = _TRUE;
+		pdmpriv->tx_powercount = 0;
+		pdmpriv->is_txpowertracking_init = _FALSE;
+
+		if (p_dm_odm->mp_mode == false)
+			pdmpriv->txpowertrack_control = _TRUE;
+
+		MSG_8192C("pdmpriv->txpowertrack_control = %d\n", pdmpriv->txpowertrack_control);
+
+	}
+#endif
+#elif (DM_ODM_SUPPORT_TYPE & (ODM_AP))
+#ifdef RTL8188E_SUPPORT
+	{
+		p_rf_calibrate_info->is_txpowertracking = _TRUE;
+		p_rf_calibrate_info->tx_powercount = 0;
+		p_rf_calibrate_info->is_txpowertracking_init = _FALSE;
+		p_rf_calibrate_info->txpowertrack_control = _TRUE;
+	}
+#endif
+#endif
+
+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
+#if (MP_DRIVER == 1)
+	p_rf_calibrate_info->txpowertrack_control = false;
+#else
+	p_rf_calibrate_info->txpowertrack_control = true;
+#endif
+#else
+	p_rf_calibrate_info->txpowertrack_control = true;
+#endif
+
+	p_rf_calibrate_info->thermal_value		= p_hal_data->eeprom_thermal_meter;
+	p_rf_calibrate_info->thermal_value_iqk	= p_hal_data->eeprom_thermal_meter;
+	p_rf_calibrate_info->thermal_value_lck	= p_hal_data->eeprom_thermal_meter;
+
+	if (p_rf_calibrate_info->default_bb_swing_index_flag != true) {
+		/*The index of "0 dB" in SwingTable.*/
+		if (p_dm_odm->support_ic_type == ODM_RTL8188E || p_dm_odm->support_ic_type == ODM_RTL8723B ||
+		    p_dm_odm->support_ic_type == ODM_RTL8192E || p_dm_odm->support_ic_type == ODM_RTL8703B) {
+			p_rf_calibrate_info->default_ofdm_index = (default_swing_index >= OFDM_TABLE_SIZE) ? 30 : default_swing_index;
+			p_rf_calibrate_info->default_cck_index = (default_cck_swing_index >= CCK_TABLE_SIZE) ? 20 : default_cck_swing_index;
+		} else if (p_dm_odm->support_ic_type == ODM_RTL8188F) {          /*add by Mingzhi.Guo  2015-03-23*/
+			p_rf_calibrate_info->default_ofdm_index = 28;							/*OFDM: -1dB*/
+			p_rf_calibrate_info->default_cck_index = 20;							/*CCK:-6dB*/
+		} else if (p_dm_odm->support_ic_type == ODM_RTL8723D) {			 /*add by zhaohe  2015-10-27*/
+			p_rf_calibrate_info->default_ofdm_index = 28;						 	   /*OFDM: -1dB*/
+			p_rf_calibrate_info->default_cck_index = 28;							/*CCK:   -6dB*/
+			/* JJ ADD 20161014 */
+		} else if (p_dm_odm->support_ic_type == ODM_RTL8710B) {			
+			p_rf_calibrate_info->default_ofdm_index = 28;					/*OFDM: -1dB*/
+			p_rf_calibrate_info->default_cck_index = 28;					/*CCK:   -6dB*/
+		} else {
+			p_rf_calibrate_info->default_ofdm_index = (default_swing_index >= TXSCALE_TABLE_SIZE) ? 24 : default_swing_index;
+			p_rf_calibrate_info->default_cck_index = 24;
+		}
+		p_rf_calibrate_info->default_bb_swing_index_flag = true;
+	}
+
+	p_rf_calibrate_info->bb_swing_idx_cck_base = p_rf_calibrate_info->default_cck_index;
+	p_rf_calibrate_info->CCK_index = p_rf_calibrate_info->default_cck_index;
+
+	for (p = ODM_RF_PATH_A; p < MAX_RF_PATH; ++p) {
+		p_rf_calibrate_info->bb_swing_idx_ofdm_base[p] = p_rf_calibrate_info->default_ofdm_index;
+		p_rf_calibrate_info->OFDM_index[p] = p_rf_calibrate_info->default_ofdm_index;
+		p_rf_calibrate_info->delta_power_index[p] = 0;
+		p_rf_calibrate_info->delta_power_index_last[p] = 0;
+		p_rf_calibrate_info->power_index_offset[p] = 0;
+		p_rf_calibrate_info->kfree_offset[p] = 0;
+	}
+	p_rf_calibrate_info->modify_tx_agc_value_ofdm = 0;
+	p_rf_calibrate_info->modify_tx_agc_value_cck = 0;
+
+}
+
+
+void
+odm_txpowertracking_check(
+	void		*p_dm_void
+)
+{
+
+#if 0
+	/* 2011/09/29 MH In HW integration first stage, we provide 4 different handle to operate */
+	/*  at the same time. In the stage2/3, we need to prive universal interface and merge all */
+	/* HW dynamic mechanism. */
+#endif
+
+	struct PHY_DM_STRUCT		*p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
+	switch	(p_dm_odm->support_platform) {
+	case	ODM_WIN:
+		odm_txpowertracking_check_mp(p_dm_odm);
+		break;
+
+	case	ODM_CE:
+		odm_txpowertracking_check_ce(p_dm_odm);
+		break;
+
+	case	ODM_AP:
+		odm_txpowertracking_check_ap(p_dm_odm);
+		break;
+
+	default:
+		break;
+	}
+
+}
+
+void
+odm_txpowertracking_check_ce(
+	void		*p_dm_void
+)
+{
+	struct PHY_DM_STRUCT		*p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
+#if (DM_ODM_SUPPORT_TYPE == ODM_CE)
+	struct _ADAPTER	*adapter = p_dm_odm->adapter;
+#if ((RTL8188F_SUPPORT == 1))
+	rtl8192c_odm_check_txpowertracking(adapter);
+#endif
+
+#if (RTL8188E_SUPPORT == 1)
+
+	if (!(p_dm_odm->support_ability & ODM_RF_TX_PWR_TRACK))
+		return;
+
+	if (!p_rf_calibrate_info->tm_trigger) {
+		odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, RF_T_METER, RFREGOFFSETMASK, 0x60);
+		/*DBG_8192C("Trigger 92C Thermal Meter!!\n");*/
+
+		p_rf_calibrate_info->tm_trigger = 1;
+		return;
+
+	} else {
+		/*DBG_8192C("Schedule TxPowerTracking direct call!!\n");*/
+		odm_txpowertracking_callback_thermal_meter_8188e(adapter);
+		p_rf_calibrate_info->tm_trigger = 0;
+	}
+#endif
+#endif
+}
+
+void
+odm_txpowertracking_check_mp(
+	void		*p_dm_void
+)
+{
+	struct PHY_DM_STRUCT		*p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
+	struct _ADAPTER	*adapter = p_dm_odm->adapter;
+
+	if (*p_dm_odm->p_is_fcs_mode_enable)
+		return;
+
+	if (odm_check_power_status(adapter) == false) {
+		RT_TRACE(COMP_POWER_TRACKING, DBG_LOUD, ("===>odm_check_power_status() return false\n"));
+		return;
+	}
+
+	if (IS_HARDWARE_TYPE_8821B(adapter)) /* TODO: Don't Do PowerTracking*/
+		return;
+
+	odm_txpowertracking_thermal_meter_check(adapter);
+
+
+#endif
+
+}
+
+
+void
+odm_txpowertracking_check_ap(
+	void		*p_dm_void
+)
+{
+	return;
+
+}
+
+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
+
+void
+odm_txpowertracking_direct_call(
+	struct _ADAPTER		*adapter
+)
+{
+	HAL_DATA_TYPE		*p_hal_data	= GET_HAL_DATA(adapter);
+	struct PHY_DM_STRUCT			*p_dm_odm = &p_hal_data->DM_OutSrc;
+
+	odm_txpowertracking_callback_thermal_meter(adapter);
+}
+
+void
+odm_txpowertracking_thermal_meter_check(
+	struct _ADAPTER		*adapter
+)
+{
+#ifndef AP_BUILD_WORKAROUND
+	static u8			tm_trigger = 0;
+
+	if (!(GET_HAL_DATA(adapter)->DM_OutSrc.support_ability & ODM_RF_TX_PWR_TRACK)) {
+		RT_TRACE(COMP_POWER_TRACKING, DBG_LOUD,
+			("===>odm_txpowertracking_thermal_meter_check(),p_mgnt_info->is_txpowertracking is false, return!!\n"));
+		return;
+	}
+
+	if (!tm_trigger) {
+		if (IS_HARDWARE_TYPE_8188E(adapter) || IS_HARDWARE_TYPE_JAGUAR(adapter) || IS_HARDWARE_TYPE_8192E(adapter) ||
+		    IS_HARDWARE_TYPE_8723B(adapter) || IS_HARDWARE_TYPE_8814A(adapter) || IS_HARDWARE_TYPE_8188F(adapter) || IS_HARDWARE_TYPE_8703B(adapter)
+		    || IS_HARDWARE_TYPE_8822B(adapter) || IS_HARDWARE_TYPE_8723D(adapter) || IS_HARDWARE_TYPE_8821C(adapter) || IS_HARDWARE_TYPE_8710B(adapter))/* JJ ADD 20161014 */
+			PHY_SetRFReg(adapter, ODM_RF_PATH_A, RF_T_METER_88E, BIT(17) | BIT(16), 0x03);
+		else
+			PHY_SetRFReg(adapter, ODM_RF_PATH_A, RF_T_METER, RFREGOFFSETMASK, 0x60);
+
+		RT_TRACE(COMP_POWER_TRACKING, DBG_LOUD, ("Trigger Thermal Meter!!\n"));
+
+		tm_trigger = 1;
+		return;
+	} else {
+		RT_TRACE(COMP_POWER_TRACKING, DBG_LOUD, ("Schedule TxPowerTracking direct call!!\n"));
+		odm_txpowertracking_direct_call(adapter);
+		tm_trigger = 0;
+	}
+#endif
+}
+
+#endif
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/phydm_powertracking_win.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/phydm_powertracking_win.h
--- linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/phydm_powertracking_win.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/phydm_powertracking_win.h	2020-04-10 16:35:06.826660535 +0300
@@ -0,0 +1,308 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
+ *
+ *
+ ******************************************************************************/
+
+#ifndef	__PHYDMPOWERTRACKING_H__
+#define    __PHYDMPOWERTRACKING_H__
+
+#define POWRTRACKING_VERSION	"1.1"
+
+#define	DPK_DELTA_MAPPING_NUM	13
+#define	index_mapping_HP_NUM	15
+#define	TXSCALE_TABLE_SIZE		37
+#define	CCK_TABLE_SIZE_8723D    41
+#define	TXPWR_TRACK_TABLE_SIZE	30
+#define	DELTA_SWINGIDX_SIZE     30
+#define DELTA_SWINTSSI_SIZE     61
+#define	BAND_NUM				3
+#define	MAX_RF_PATH	4
+#define	CCK_TABLE_SIZE_88F	21
+/* JJ ADD 20161014 */
+#define	CCK_TABLE_SIZE_8710B   41
+
+
+#define	dm_check_txpowertracking	odm_txpowertracking_check
+
+#define IQK_MATRIX_SETTINGS_NUM	(14+24+21) /* Channels_2_4G_NUM + Channels_5G_20M_NUM + Channels_5G */
+#define	AVG_THERMAL_NUM		8
+#define	HP_THERMAL_NUM		8
+#define	iqk_matrix_reg_num	8
+#define	IQK_MAC_REG_NUM		4
+#define	IQK_ADDA_REG_NUM		16
+
+#define	IQK_BB_REG_NUM		9
+
+
+extern	u32 ofdm_swing_table[OFDM_TABLE_SIZE];
+extern	u8 cck_swing_table_ch1_ch13[CCK_TABLE_SIZE][8];
+extern	u8 cck_swing_table_ch14[CCK_TABLE_SIZE][8];
+
+extern	u32 ofdm_swing_table_new[OFDM_TABLE_SIZE];
+extern	u8 cck_swing_table_ch1_ch13_new[CCK_TABLE_SIZE][8];
+extern	u8 cck_swing_table_ch14_new[CCK_TABLE_SIZE][8];
+extern	u8 cck_swing_table_ch1_ch14_88f[CCK_TABLE_SIZE_88F][16];
+extern	u8 cck_swing_table_ch1_ch13_88f[CCK_TABLE_SIZE_88F][16];
+extern	u8 cck_swing_table_ch14_88f[CCK_TABLE_SIZE_88F][16];
+extern	u32 cck_swing_table_ch1_ch14_8723d[CCK_TABLE_SIZE_8723D];
+/* JJ ADD 20161014 */
+extern	u32 cck_swing_table_ch1_ch14_8710b[CCK_TABLE_SIZE_8710B];
+
+extern  u32 tx_scaling_table_jaguar[TXSCALE_TABLE_SIZE];
+
+/* <20121018, Kordan> In case fail to read TxPowerTrack.txt, we use the table of 88E as the default table. */
+static u8 delta_swing_table_idx_2ga_p_8188e[] = {0, 0, 0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 4,  4,  4,  4,  4,  4,  5,  5,  7,  7,  8,  8,  8,  9,  9,  9,  9,  9};
+static u8 delta_swing_table_idx_2ga_n_8188e[] = {0, 0, 0, 2, 2, 3, 3, 4, 4, 4, 4, 5, 5,  6,  6,  7,  7,  7,  7,  8,  8,  9,  9, 10, 10, 10, 11, 11, 11, 11};
+
+void
+odm_txpowertracking_check(
+	void		*p_dm_void
+);
+
+void
+odm_txpowertracking_check_ap(
+	void		*p_dm_void
+);
+
+void
+odm_txpowertracking_thermal_meter_init(
+	void		*p_dm_void
+);
+
+void
+odm_txpowertracking_init(
+	void		*p_dm_void
+);
+
+void
+odm_txpowertracking_check_mp(
+	void		*p_dm_void
+);
+
+
+void
+odm_txpowertracking_check_ce(
+	void		*p_dm_void
+);
+
+#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN))
+
+
+void
+odm_txpowertracking_thermal_meter_check(
+	struct _ADAPTER		*adapter
+);
+
+#endif
+
+struct _IQK_MATRIX_REGS_SETTING {
+	boolean	is_iqk_done;
+	s32		value[3][iqk_matrix_reg_num];
+	boolean	is_bw_iqk_result_saved[3];
+};
+
+struct odm_rf_calibration_structure {
+	/* for tx power tracking */
+
+	u32	rega24; /* for TempCCK */
+	s32	rege94;
+	s32	rege9c;
+	s32	regeb4;
+	s32	regebc;
+	/* u8 is_txpowertracking; */
+	u8	tx_powercount;
+	boolean is_txpowertracking_init;
+	boolean is_txpowertracking;
+	u8  	txpowertrack_control; /* for mp mode, turn off txpwrtracking as default */
+	u8	tm_trigger;
+	u8  	internal_pa_5g[2];	/* pathA / pathB */
+
+	u8  	thermal_meter[2];    /* thermal_meter, index 0 for RFIC0, and 1 for RFIC1 */
+	u8	thermal_value;
+	u8	thermal_value_lck;
+	u8	thermal_value_iqk;
+	u8  thermal_value_dpk;
+	s8  	thermal_value_delta; /* delta of thermal_value and efuse thermal */
+	u8	thermal_value_avg[AVG_THERMAL_NUM];
+	u8	thermal_value_avg_index;
+	u8	thermal_value_rx_gain;
+
+
+	boolean	is_reloadtxpowerindex;
+	u8	is_rf_pi_enable;
+	u32 	txpowertracking_callback_cnt; /* cosa add for debug */
+
+
+	/* ------------------------- Tx power Tracking ------------------------- */
+	u8	is_cck_in_ch14;
+	u8	CCK_index;
+	u8	OFDM_index[MAX_RF_PATH];
+	s8	power_index_offset[MAX_RF_PATH];
+	s8	delta_power_index[MAX_RF_PATH];
+	s8	delta_power_index_last[MAX_RF_PATH];
+	boolean is_tx_power_changed;
+	s8	xtal_offset;
+	s8	xtal_offset_last;
+
+	u8	thermal_value_hp[HP_THERMAL_NUM];
+	u8	thermal_value_hp_index;
+	struct _IQK_MATRIX_REGS_SETTING iqk_matrix_reg_setting[IQK_MATRIX_SETTINGS_NUM];
+	u8	delta_lck;
+	s8  bb_swing_diff_2g, bb_swing_diff_5g; /* Unit: dB */
+	u8  delta_swing_table_idx_2g_cck_a_p[DELTA_SWINGIDX_SIZE];
+	u8  delta_swing_table_idx_2g_cck_a_n[DELTA_SWINGIDX_SIZE];
+	u8  delta_swing_table_idx_2g_cck_b_p[DELTA_SWINGIDX_SIZE];
+	u8  delta_swing_table_idx_2g_cck_b_n[DELTA_SWINGIDX_SIZE];
+	u8  delta_swing_table_idx_2g_cck_c_p[DELTA_SWINGIDX_SIZE];
+	u8  delta_swing_table_idx_2g_cck_c_n[DELTA_SWINGIDX_SIZE];
+	u8  delta_swing_table_idx_2g_cck_d_p[DELTA_SWINGIDX_SIZE];
+	u8  delta_swing_table_idx_2g_cck_d_n[DELTA_SWINGIDX_SIZE];
+	u8  delta_swing_table_idx_2ga_p[DELTA_SWINGIDX_SIZE];
+	u8  delta_swing_table_idx_2ga_n[DELTA_SWINGIDX_SIZE];
+	u8  delta_swing_table_idx_2gb_p[DELTA_SWINGIDX_SIZE];
+	u8  delta_swing_table_idx_2gb_n[DELTA_SWINGIDX_SIZE];
+	u8  delta_swing_table_idx_2gc_p[DELTA_SWINGIDX_SIZE];
+	u8  delta_swing_table_idx_2gc_n[DELTA_SWINGIDX_SIZE];
+	u8  delta_swing_table_idx_2gd_p[DELTA_SWINGIDX_SIZE];
+	u8  delta_swing_table_idx_2gd_n[DELTA_SWINGIDX_SIZE];
+	u8  delta_swing_table_idx_5ga_p[BAND_NUM][DELTA_SWINGIDX_SIZE];
+	u8  delta_swing_table_idx_5ga_n[BAND_NUM][DELTA_SWINGIDX_SIZE];
+	u8  delta_swing_table_idx_5gb_p[BAND_NUM][DELTA_SWINGIDX_SIZE];
+	u8  delta_swing_table_idx_5gb_n[BAND_NUM][DELTA_SWINGIDX_SIZE];
+	u8  delta_swing_table_idx_5gc_p[BAND_NUM][DELTA_SWINGIDX_SIZE];
+	u8  delta_swing_table_idx_5gc_n[BAND_NUM][DELTA_SWINGIDX_SIZE];
+	u8  delta_swing_table_idx_5gd_p[BAND_NUM][DELTA_SWINGIDX_SIZE];
+	u8  delta_swing_table_idx_5gd_n[BAND_NUM][DELTA_SWINGIDX_SIZE];
+	u8  delta_swing_tssi_table_2g_cck_a[DELTA_SWINTSSI_SIZE];
+	u8  delta_swing_tssi_table_2g_cck_b[DELTA_SWINTSSI_SIZE];
+	u8  delta_swing_tssi_table_2g_cck_c[DELTA_SWINTSSI_SIZE];
+	u8  delta_swing_tssi_table_2g_cck_d[DELTA_SWINTSSI_SIZE];
+	u8  delta_swing_tssi_table_2ga[DELTA_SWINTSSI_SIZE];
+	u8  delta_swing_tssi_table_2gb[DELTA_SWINTSSI_SIZE];
+	u8  delta_swing_tssi_table_2gc[DELTA_SWINTSSI_SIZE];
+	u8  delta_swing_tssi_table_2gd[DELTA_SWINTSSI_SIZE];
+	u8  delta_swing_tssi_table_5ga[BAND_NUM][DELTA_SWINTSSI_SIZE];
+	u8  delta_swing_tssi_table_5gb[BAND_NUM][DELTA_SWINTSSI_SIZE];
+	u8  delta_swing_tssi_table_5gc[BAND_NUM][DELTA_SWINTSSI_SIZE];
+	u8  delta_swing_tssi_table_5gd[BAND_NUM][DELTA_SWINTSSI_SIZE];
+	s8  delta_swing_table_xtal_p[DELTA_SWINGIDX_SIZE];
+	s8  delta_swing_table_xtal_n[DELTA_SWINGIDX_SIZE];
+	u8  delta_swing_table_idx_2ga_p_8188e[DELTA_SWINGIDX_SIZE];
+	u8  delta_swing_table_idx_2ga_n_8188e[DELTA_SWINGIDX_SIZE];
+
+	u8			bb_swing_idx_ofdm[MAX_RF_PATH];
+	u8			bb_swing_idx_ofdm_current;
+#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
+	u8			bb_swing_idx_ofdm_base[MAX_RF_PATH];
+#else
+	u8			bb_swing_idx_ofdm_base;
+#endif
+	boolean		default_bb_swing_index_flag;
+	boolean			bb_swing_flag_ofdm;
+	u8			bb_swing_idx_cck;
+	u8			bb_swing_idx_cck_current;
+	u8			bb_swing_idx_cck_base;
+	u8			default_ofdm_index;
+	u8			default_cck_index;
+	boolean			bb_swing_flag_cck;
+
+	s8			absolute_ofdm_swing_idx[MAX_RF_PATH];
+	s8			remnant_ofdm_swing_idx[MAX_RF_PATH];
+	s8			absolute_cck_swing_idx[MAX_RF_PATH];
+	s8			remnant_cck_swing_idx;
+	s8			modify_tx_agc_value;       /*Remnat compensate value at tx_agc */
+	boolean			modify_tx_agc_flag_path_a;
+	boolean			modify_tx_agc_flag_path_b;
+	boolean			modify_tx_agc_flag_path_c;
+	boolean			modify_tx_agc_flag_path_d;
+	boolean			modify_tx_agc_flag_path_a_cck;
+
+	s8			kfree_offset[MAX_RF_PATH];
+
+	/* -------------------------------------------------------------------- */
+
+	/* for IQK */
+	u32	regc04;
+	u32	reg874;
+	u32	regc08;
+	u32	regb68;
+	u32	regb6c;
+	u32	reg870;
+	u32	reg860;
+	u32	reg864;
+
+	boolean	is_iqk_initialized;
+	boolean is_lck_in_progress;
+	boolean	is_antenna_detected;
+	boolean	is_need_iqk;
+	boolean	is_iqk_in_progress;
+	boolean	is_iqk_pa_off;
+	u8	delta_iqk;
+	u32	ADDA_backup[IQK_ADDA_REG_NUM];
+	u32	IQK_MAC_backup[IQK_MAC_REG_NUM];
+	u32	IQK_BB_backup_recover[9];
+	u32	IQK_BB_backup[IQK_BB_REG_NUM];
+	u32	tx_iqc_8723b[2][3][2]; /* { {S1: 0xc94, 0xc80, 0xc4c} , {S0: 0xc9c, 0xc88, 0xc4c}} */
+	u32	rx_iqc_8723b[2][2][2]; /* { {S1: 0xc14, 0xca0} ,           {S0: 0xc14, 0xca0}} */
+	u32	tx_iqc_8703b[3][2];	/* { {S1: 0xc94, 0xc80, 0xc4c} , {S0: 0xc9c, 0xc88, 0xc4c}}*/
+	u32	rx_iqc_8703b[2][2];	/* { {S1: 0xc14, 0xca0} ,           {S0: 0xc14, 0xca0}}*/
+	u32	tx_iqc_8723d[2][3][2];	/* { {S1: 0xc94, 0xc80, 0xc4c} , {S0: 0xc9c, 0xc88, 0xc4c}}*/
+	u32	rx_iqc_8723d[2][2][2];	/* { {S1: 0xc14, 0xca0} ,           {S0: 0xc14, 0xca0}}*/
+	/* JJ ADD 20161014 */
+	u32	tx_iqc_8710b[2][3][2];	/* { {S1: 0xc94, 0xc80, 0xc4c} , {S0: 0xc9c, 0xc88, 0xc4c}}*/
+	u32	rx_iqc_8710b[2][2][2];	/* { {S1: 0xc14, 0xca0} ,           {S0: 0xc14, 0xca0}}*/
+
+	u64	iqk_start_time;
+	u64	iqk_total_progressing_time;
+	u64	iqk_progressing_time;
+	u32  lok_result;
+	u8	iqk_step;
+	u8	kcount;
+	u8	retry_count[4][2]; /* [4]: path ABCD, [2] TXK, RXK */
+	boolean	is_mp_mode;
+
+	/* for APK */
+	u32 	ap_koutput[2][2]; /* path A/B; output1_1a/output1_2a */
+	u8	is_ap_kdone;
+	u8	is_apk_thermal_meter_ignore;
+
+	/* DPK */
+	boolean is_dpk_fail;
+	u8	is_dp_done;
+	u8	is_dp_path_aok;
+	u8	is_dp_path_bok;
+
+	u32	tx_lok[2];
+	u32  dpk_tx_agc;
+	s32  dpk_gain;
+	u32  dpk_thermal[4];
+
+	s8 modify_tx_agc_value_ofdm;
+	s8 modify_tx_agc_value_cck;
+
+	/*Add by Yuchen for Kfree Phydm*/
+	u8			reg_rf_kfree_enable;	/*for registry*/
+	u8			rf_kfree_enable;		/*for efuse enable check*/
+
+	HALMAC_PWR_TRACKING_OPTION	HALMAC_PWR_TRACKING_INFO;
+};
+
+
+
+
+#endif
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/phydm_pow_train.c linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/phydm_pow_train.c
--- linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/phydm_pow_train.c	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/phydm_pow_train.c	2020-04-10 16:35:06.826660535 +0300
@@ -0,0 +1,183 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017  Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * The full GNU General Public License is included in this distribution in the
+ * file called LICENSE.
+ *
+ * Contact Information:
+ * wlanfae <wlanfae@realtek.com>
+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
+ * Hsinchu 300, Taiwan.
+ *
+ * Larry Finger <Larry.Finger@lwfinger.net>
+ *
+ *****************************************************************************/
+
+/*************************************************************
+ * include files
+ ************************************************************/
+
+#include "mp_precomp.h"
+#include "phydm_precomp.h"
+
+#ifdef PHYDM_POWER_TRAINING_SUPPORT
+void phydm_reset_pt_para(void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct phydm_pow_train_stuc *pt_t = &dm->pow_train_table;
+
+	pt_t->pow_train_score = 0;
+}
+
+void phydm_update_power_training_state(void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct phydm_pow_train_stuc *pt_t = &dm->pow_train_table;
+	struct phydm_fa_struct *fa_cnt = &dm->false_alm_cnt;
+	struct ccx_info *ccx = &dm->dm_ccx_info;
+	u32 pt_score_tmp = ENABLE_PT_SCORE;
+	u32 crc_ok_cnt = 0;
+	u32 cca_cnt = 0;
+
+	/*@is_disable_power_training is the key to H2C to disable/enable PT*/
+	/*@if is_disable_power_training == 1, it will use largest power*/
+	if (!(dm->support_ability & ODM_BB_PWR_TRAIN) || !dm->is_linked) {
+		dm->is_disable_power_training = true;
+		phydm_reset_pt_para(dm);
+		return;
+	}
+
+	PHYDM_DBG(dm, DBG_PWR_TRAIN, "%s ======>\n", __func__);
+
+	if (pt_t->pt_state == DISABLE_POW_TRAIN) {
+		dm->is_disable_power_training = true;
+		phydm_reset_pt_para(dm);
+		PHYDM_DBG(dm, DBG_PWR_TRAIN, "Disable PT\n");
+		return;
+
+	} else if (pt_t->pt_state == ENABLE_POW_TRAIN) {
+		dm->is_disable_power_training = false;
+		phydm_reset_pt_para(dm);
+		PHYDM_DBG(dm, DBG_PWR_TRAIN, "Enable PT\n");
+		return;
+
+	} else if (pt_t->pt_state == DYNAMIC_POW_TRAIN) {
+		PHYDM_DBG(dm, DBG_PWR_TRAIN, "Dynamic PT\n");
+
+		/* @Compute score */
+		crc_ok_cnt = dm->phy_dbg_info.num_qry_phy_status_ofdm +
+			     dm->phy_dbg_info.num_qry_phy_status_cck;
+		cca_cnt = fa_cnt->cnt_cca_all;
+#if 0
+		if (crc_ok_cnt > cca_cnt) { /*invalid situation*/
+			pt_score_tmp = KEEP_PRE_PT_SCORE;
+			return;
+		} else if ((crc_ok_cnt + (crc_ok_cnt >> 1)) <= cca_cnt) {
+		/* @???crc_ok <= (2/3)*cca */
+			pt_score_tmp = DISABLE_PT_SCORE;
+			dm->is_disable_power_training = true;
+		} else if ((crc_ok_cnt + (crc_ok_cnt >> 2)) <= cca_cnt) {
+		/* @???crc_ok <= (4/5)*cca */
+			pt_score_tmp = KEEP_PRE_PT_SCORE;
+		} else {
+		/* @???crc_ok > (4/5)*cca */
+			pt_score_tmp = ENABLE_PT_SCORE;
+			dm->is_disable_power_training = false;
+		}
+#endif
+		if (ccx->nhm_ratio > 10) {
+			pt_score_tmp = DISABLE_PT_SCORE;
+			dm->is_disable_power_training = true;
+		} else if (ccx->nhm_ratio < 5) {
+			pt_score_tmp = ENABLE_PT_SCORE;
+			dm->is_disable_power_training = false;
+		} else {
+			pt_score_tmp = KEEP_PRE_PT_SCORE;
+		}
+
+		PHYDM_DBG(dm, DBG_PWR_TRAIN,
+			  "pkt_cnt{ofdm,cck,all} = {%d, %d, %d}, cnt_cca_all=%d\n",
+			  dm->phy_dbg_info.num_qry_phy_status_ofdm,
+			  dm->phy_dbg_info.num_qry_phy_status_cck,
+			  crc_ok_cnt, cca_cnt);
+
+		PHYDM_DBG(dm, DBG_PWR_TRAIN, "pt_score_tmp=%d\n", pt_score_tmp);
+
+		/* smoothing */
+		pt_t->pow_train_score = (pt_score_tmp << 4) +
+					(pt_t->pow_train_score >> 1) +
+					(pt_t->pow_train_score >> 2);
+
+		pt_score_tmp = (pt_t->pow_train_score + 32) >> 6;
+
+		PHYDM_DBG(dm, DBG_PWR_TRAIN,
+			  "pow_train_score = %d, score after smoothing = %d, is_disable_PT = %d\n",
+			  pt_t->pow_train_score, pt_score_tmp,
+			  dm->is_disable_power_training);
+	} else {
+		PHYDM_DBG(dm, DBG_PWR_TRAIN, "[%s]warning\n", __func__);
+	}
+}
+
+void phydm_pow_train_debug(
+	void *dm_void,
+	char input[][16],
+	u32 *_used,
+	char *output,
+	u32 *_out_len)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct phydm_pow_train_stuc *pt_t = &dm->pow_train_table;
+	char help[] = "-h";
+	u32 var1[10] = {0};
+	u32 used = *_used;
+	u32 out_len = *_out_len;
+	u32 i;
+
+	if ((strcmp(input[1], help) == 0)) {
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "0: Dynamic state\n");
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "1: Enable PT\n");
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "2: Disable PT\n");
+
+	} else {
+		for (i = 0; i < 10; i++) {
+			if (input[i + 1])
+				PHYDM_SSCANF(input[i + 1], DCMD_HEX, &var1[i]);
+		}
+
+		if (var1[0] == 0) {
+			pt_t->pt_state = DYNAMIC_POW_TRAIN;
+			PDM_SNPF(out_len, used, output + used, out_len - used,
+				 "Dynamic state\n");
+		} else if (var1[0] == 1) {
+			pt_t->pt_state = ENABLE_POW_TRAIN;
+			PDM_SNPF(out_len, used, output + used, out_len - used,
+				 "Enable PT\n");
+		} else if (var1[0] == 2) {
+			pt_t->pt_state = DISABLE_POW_TRAIN;
+			PDM_SNPF(out_len, used, output + used, out_len - used,
+				 "Disable PT\n");
+		} else {
+			PDM_SNPF(out_len, used, output + used, out_len - used,
+				 "Set Error\n");
+		}
+	}
+
+	*_used = used;
+	*_out_len = out_len;
+}
+
+#endif
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/phydm_pow_train.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/phydm_pow_train.h
--- linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/phydm_pow_train.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/phydm_pow_train.h	2020-04-10 16:35:06.826660535 +0300
@@ -0,0 +1,84 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017  Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * The full GNU General Public License is included in this distribution in the
+ * file called LICENSE.
+ *
+ * Contact Information:
+ * wlanfae <wlanfae@realtek.com>
+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
+ * Hsinchu 300, Taiwan.
+ *
+ * Larry Finger <Larry.Finger@lwfinger.net>
+ *
+ *****************************************************************************/
+
+#ifndef __PHYDM_POW_TRAIN_H__
+#define __PHYDM_POW_TRAIN_H__
+
+#define POW_TRAIN_VERSION "1.0" /* @2017.07.0141  Dino, Add phydm_pow_train.h*/
+
+/****************************************************************
+ * 1 ============================================================
+ * 1  Definition
+ * 1 ============================================================
+ ***************************************************************/
+
+#ifdef PHYDM_POWER_TRAINING_SUPPORT
+/****************************************************************
+ * 1 ============================================================
+ * 1  structure
+ * 1 ============================================================
+ ***************************************************************/
+
+struct phydm_pow_train_stuc {
+	u8 pt_state;
+	u32 pow_train_score;
+};
+
+/****************************************************************
+ * 1 ============================================================
+ * 1  enumeration
+ * 1 ============================================================
+ ***************************************************************/
+
+enum pow_train_state {
+	DYNAMIC_POW_TRAIN = 0,
+	ENABLE_POW_TRAIN = 1,
+	DISABLE_POW_TRAIN = 2
+};
+
+enum power_training_score {
+	DISABLE_PT_SCORE = 0,
+	KEEP_PRE_PT_SCORE = 1,
+	ENABLE_PT_SCORE = 2
+};
+
+/****************************************************************
+ * 1 ============================================================
+ * 1  function prototype
+ * 1 ============================================================
+ ***************************************************************/
+
+void phydm_update_power_training_state(
+	void *dm_void);
+
+void phydm_pow_train_debug(
+	void *dm_void,
+	char input[][16],
+	u32 *_used,
+	char *output,
+	u32 *_out_len);
+
+#endif
+#endif
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/phydm_precomp.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/phydm_precomp.h
--- linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/phydm_precomp.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/phydm_precomp.h	2020-04-10 16:35:06.826660535 +0300
@@ -0,0 +1,469 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017  Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * The full GNU General Public License is included in this distribution in the
+ * file called LICENSE.
+ *
+ * Contact Information:
+ * wlanfae <wlanfae@realtek.com>
+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
+ * Hsinchu 300, Taiwan.
+ *
+ * Larry Finger <Larry.Finger@lwfinger.net>
+ *
+ *****************************************************************************/
+
+#ifndef __ODM_PRECOMP_H__
+#define __ODM_PRECOMP_H__
+
+#include "phydm_types.h"
+#include "halrf/halrf_features.h"
+
+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
+	#include "Precomp.h"		/* @We need to include mp_precomp.h due to batch file setting. */
+#else
+	#define		TEST_FALG___		1
+#endif
+
+/* @2 Config Flags and Structs - defined by each ODM type */
+
+#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
+	#include "../8192cd_cfg.h"
+	#include "../odm_inc.h"
+
+	#include "../8192cd.h"
+	#include "../8192cd_util.h"
+	#include "../8192cd_hw.h"
+	#ifdef _BIG_ENDIAN_
+		#define	ODM_ENDIAN_TYPE				ODM_ENDIAN_BIG
+	#else
+		#define	ODM_ENDIAN_TYPE				ODM_ENDIAN_LITTLE
+	#endif
+
+	#include "../8192cd_headers.h"
+	#include "../8192cd_debug.h"
+
+#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
+	#ifdef DM_ODM_CE_MAC80211
+		#include "../wifi.h"
+		#include "rtl_phydm.h"
+	#elif defined(DM_ODM_CE_MAC80211_V2)
+		#include "../main.h"
+		#include "../hw.h"
+		#include "../fw.h"
+	#endif
+	#define __PACK
+	#define __WLAN_ATTRIB_PACK__
+#elif (DM_ODM_SUPPORT_TYPE == ODM_WIN)
+	#include "mp_precomp.h"
+	#define	ODM_ENDIAN_TYPE				ODM_ENDIAN_LITTLE
+	#define __PACK
+	#define __WLAN_ATTRIB_PACK__
+#elif (DM_ODM_SUPPORT_TYPE == ODM_IOT)
+	#include <drv_types.h>
+	#include <wifi.h>
+	#define	ODM_ENDIAN_TYPE				ODM_ENDIAN_LITTLE
+	#define __PACK
+#endif
+
+/* @2 OutSrc Header Files */
+
+#include "phydm.h"
+#include "phydm_hwconfig.h"
+#include "phydm_phystatus.h"
+#include "phydm_debug.h"
+#include "phydm_regdefine11ac.h"
+#include "phydm_regdefine11n.h"
+#include "phydm_interface.h"
+#include "phydm_reg.h"
+#include "halrf/halrf_debug.h"
+
+#if (DM_ODM_SUPPORT_TYPE & ODM_CE) && \
+	(!defined(DM_ODM_CE_MAC80211) && !defined(DM_ODM_CE_MAC80211_V2))
+
+void phy_set_tx_power_limit(
+	struct dm_struct *dm,
+	u8 *regulation,
+	u8 *band,
+	u8 *bandwidth,
+	u8 *rate_section,
+	u8 *rf_path,
+	u8 *channel,
+	u8 *power_limit);
+
+enum hal_status
+rtw_phydm_fw_iqk(
+	struct dm_struct *dm,
+	u8 clear,
+	u8 segment);
+
+enum hal_status
+rtw_phydm_cfg_phy_para(
+	struct dm_struct *dm,
+	enum phydm_halmac_param config_type,
+	u32 offset,
+	u32 data,
+	u32 mask,
+	enum rf_path e_rf_path,
+	u32 delay_time);
+
+#endif
+
+/* @Judy ADD 20180125 */
+#if (DM_ODM_SUPPORT_TYPE & (ODM_AP | ODM_IOT))
+#define RTL8710B_SUPPORT		0
+#endif
+
+#if RTL8188E_SUPPORT == 1
+	#define RTL8188E_T_SUPPORT 1
+	#ifdef CONFIG_SFW_SUPPORTED
+		#define RTL8188E_S_SUPPORT 1
+	#else
+		#define RTL8188E_S_SUPPORT 0
+	#endif
+#endif
+
+#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
+#define RTL8197F_SUPPORT 0	/*@Just for PHYDM API development*/
+#define	RTL8195B_SUPPORT 0	/*@Just for PHYDM API development*/
+#define	RTL8198F_SUPPORT 0	/*@Just for PHYDM API development*/
+#endif
+
+#if (RTL8188E_SUPPORT == 1)
+	#include "rtl8188e/hal8188erateadaptive.h" /* @for  RA,Power training */
+	#include "rtl8188e/halhwimg8188e_mac.h"
+	#include "rtl8188e/halhwimg8188e_rf.h"
+	#include "rtl8188e/halhwimg8188e_bb.h"
+	#include "rtl8188e/phydm_regconfig8188e.h"
+	#include "rtl8188e/phydm_rtl8188e.h"
+	#include "rtl8188e/hal8188ereg.h"
+	#include "rtl8188e/version_rtl8188e.h"
+	#if (DM_ODM_SUPPORT_TYPE == ODM_CE)
+		#include "rtl8188e_hal.h"
+		#include "halrf/rtl8188e/halrf_8188e_ce.h"
+	#endif
+	#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
+		#include "halrf/rtl8188e/halrf_8188e_win.h"
+	#endif
+	#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
+		#include "halrf/rtl8188e/halrf_8188e_ap.h"
+	#endif
+#endif /* @88E END */
+
+#if (RTL8192E_SUPPORT == 1)
+
+	#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
+		#include "halrf/rtl8192e/halrf_8192e_win.h" /*@FOR_8192E_IQK*/
+	#elif (DM_ODM_SUPPORT_TYPE == ODM_AP)
+		#include "halrf/rtl8192e/halrf_8192e_ap.h" /*@FOR_8192E_IQK*/
+	#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
+		#include "halrf/rtl8192e/halrf_8192e_ce.h" /*@FOR_8192E_IQK*/
+	#endif
+
+	#include "rtl8192e/phydm_rtl8192e.h" /* @FOR_8192E_IQK */
+	#include "rtl8192e/version_rtl8192e.h"
+	#if (DM_ODM_SUPPORT_TYPE != ODM_AP)
+		#include "rtl8192e/halhwimg8192e_bb.h"
+		#include "rtl8192e/halhwimg8192e_mac.h"
+		#include "rtl8192e/halhwimg8192e_rf.h"
+		#include "rtl8192e/phydm_regconfig8192e.h"
+		#include "rtl8192e/hal8192ereg.h"
+	#endif
+	#if (DM_ODM_SUPPORT_TYPE == ODM_CE)
+		#include "rtl8192e_hal.h"
+	#endif
+#endif /* @92E END */
+
+#if (RTL8812A_SUPPORT == 1)
+
+	#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
+		#include "halrf/rtl8812a/halrf_8812a_win.h"
+	#elif (DM_ODM_SUPPORT_TYPE == ODM_AP)
+		#include "halrf/rtl8812a/halrf_8812a_ap.h"
+	#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
+		#include "halrf/rtl8812a/halrf_8812a_ce.h"
+	#endif
+
+	/* @#include "halrf/rtl8812a/halrf_8812a.h"  */ /* @FOR_8812_IQK */
+	#if (DM_ODM_SUPPORT_TYPE != ODM_AP)
+		#include "rtl8812a/halhwimg8812a_bb.h"
+		#include "rtl8812a/halhwimg8812a_mac.h"
+		#include "rtl8812a/halhwimg8812a_rf.h"
+		#include "rtl8812a/phydm_regconfig8812a.h"
+	#endif
+	#include "rtl8812a/phydm_rtl8812a.h"
+
+	#if (DM_ODM_SUPPORT_TYPE == ODM_CE)
+		#include "rtl8812a_hal.h"
+	#endif
+	#include "rtl8812a/version_rtl8812a.h"
+
+#endif /* @8812 END */
+
+#if (RTL8814A_SUPPORT == 1)
+
+	#include "rtl8814a/halhwimg8814a_mac.h"
+	#include "rtl8814a/halhwimg8814a_rf.h"
+	#include "rtl8814a/halhwimg8814a_bb.h"
+	#include "rtl8814a/version_rtl8814a.h"
+	#include "rtl8814a/phydm_rtl8814a.h"
+	#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
+		#include "halrf/rtl8814a/halrf_8814a_win.h"
+	#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
+		#include "halrf/rtl8814a/halrf_8814a_ce.h"
+	#elif (DM_ODM_SUPPORT_TYPE == ODM_AP)
+		#include "halrf/rtl8814a/halrf_8814a_ap.h"
+	#endif
+	#include "rtl8814a/phydm_regconfig8814a.h"
+	#if (DM_ODM_SUPPORT_TYPE == ODM_CE)
+		#include "rtl8814a_hal.h"
+		#include "halrf/rtl8814a/halrf_iqk_8814a.h"
+	#endif
+#endif /* @8814 END */
+
+#if (RTL8881A_SUPPORT == 1)/* @FOR_8881_IQK */
+	#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
+		#include "halrf/rtl8821a/halrf_iqk_8821a_win.h"
+	#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
+		#include "halrf/rtl8821a/halrf_iqk_8821a_ce.h"
+	#else
+		#include "halrf/rtl8821a/halrf_iqk_8821a_ap.h"
+	#endif
+	/* @#include "rtl8881a/HalHWImg8881A_BB.h" */
+	/* @#include "rtl8881a/HalHWImg8881A_MAC.h" */
+	/* @#include "rtl8881a/HalHWImg8881A_RF.h" */
+	/* @#include "rtl8881a/odm_RegConfig8881A.h" */
+#endif
+
+#if (RTL8723B_SUPPORT == 1)
+	#include "rtl8723b/halhwimg8723b_mac.h"
+	#include "rtl8723b/halhwimg8723b_rf.h"
+	#include "rtl8723b/halhwimg8723b_bb.h"
+	#include "rtl8723b/phydm_regconfig8723b.h"
+	#include "rtl8723b/phydm_rtl8723b.h"
+	#include "rtl8723b/hal8723breg.h"
+	#include "rtl8723b/version_rtl8723b.h"
+	#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
+		#include "halrf/rtl8723b/halrf_8723b_win.h"
+	#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
+		#include "halrf/rtl8723b/halrf_8723b_ce.h"
+		#include "rtl8723b/halhwimg8723b_mp.h"
+		#include "rtl8723b_hal.h"
+	#else
+		#include "halrf/rtl8723b/halrf_8723b_ap.h"
+	#endif
+#endif
+
+#if (RTL8821A_SUPPORT == 1)
+	#include "rtl8821a/halhwimg8821a_mac.h"
+	#include "rtl8821a/halhwimg8821a_rf.h"
+	#include "rtl8821a/halhwimg8821a_bb.h"
+	#include "rtl8821a/phydm_regconfig8821a.h"
+	#include "rtl8821a/phydm_rtl8821a.h"
+	#include "rtl8821a/version_rtl8821a.h"
+	#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
+		#include "halrf/rtl8821a/halrf_8821a_win.h"
+	#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
+		#include "halrf/rtl8821a/halrf_8821a_ce.h"
+		#include "halrf/rtl8821a/halrf_iqk_8821a_ce.h"/*@for IQK*/
+		#include "halrf/rtl8812a/halrf_8812a_ce.h"/*@for IQK,LCK,Power-tracking*/
+		#include "rtl8812a_hal.h"
+	#else
+	#endif
+#endif
+
+#if (DM_ODM_SUPPORT_TYPE == ODM_CE) && defined(DM_ODM_CE_MAC80211)
+#include "../halmac/halmac_reg2.h"
+#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) && defined(DM_ODM_CE_MAC80211_V2)
+#include "../halmac/halmac_reg2.h"
+#endif
+
+
+#if (RTL8822B_SUPPORT == 1)
+	#include "rtl8822b/halhwimg8822b_mac.h"
+	#include "rtl8822b/halhwimg8822b_rf.h"
+	#include "rtl8822b/halhwimg8822b_bb.h"
+	#include "rtl8822b/phydm_regconfig8822b.h"
+	#include "halrf/rtl8822b/halrf_8822b.h"
+	#include "rtl8822b/phydm_rtl8822b.h"
+	#include "rtl8822b/phydm_hal_api8822b.h"
+	#include "rtl8822b/version_rtl8822b.h"
+
+	#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
+	#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
+		#ifdef DM_ODM_CE_MAC80211
+			#include "../halmac/halmac_reg_8822b.h"
+		#elif defined(DM_ODM_CE_MAC80211_V2)
+			#include "../halmac/halmac_reg_8822b.h"
+		#else
+			#include <hal_data.h>		/* @struct HAL_DATA_TYPE */
+			#include <rtl8822b_hal.h>	/* @RX_SMOOTH_FACTOR, reg definition and etc.*/
+		#endif
+	#elif (DM_ODM_SUPPORT_TYPE == ODM_AP)
+	#endif
+
+#endif
+
+#if (RTL8703B_SUPPORT == 1)
+	#include "rtl8703b/phydm_rtl8703b.h"
+	#include "rtl8703b/phydm_regconfig8703b.h"
+	#include "rtl8703b/halhwimg8703b_mac.h"
+	#include "rtl8703b/halhwimg8703b_rf.h"
+	#include "rtl8703b/halhwimg8703b_bb.h"
+	#include "halrf/rtl8703b/halrf_8703b.h"
+	#include "rtl8703b/version_rtl8703b.h"
+	#if (DM_ODM_SUPPORT_TYPE == ODM_CE)
+		#include "rtl8703b_hal.h"
+	#endif
+#endif
+
+#if (RTL8188F_SUPPORT == 1)
+	#include "rtl8188f/halhwimg8188f_mac.h"
+	#include "rtl8188f/halhwimg8188f_rf.h"
+	#include "rtl8188f/halhwimg8188f_bb.h"
+	#include "rtl8188f/hal8188freg.h"
+	#include "rtl8188f/phydm_rtl8188f.h"
+	#include "rtl8188f/phydm_regconfig8188f.h"
+	#include "halrf/rtl8188f/halrf_8188f.h" /*@for IQK,LCK,Power-tracking*/
+	#include "rtl8188f/version_rtl8188f.h"
+	#if (DM_ODM_SUPPORT_TYPE == ODM_CE)
+		#include "rtl8188f_hal.h"
+	#endif
+#endif
+
+#if (RTL8723D_SUPPORT == 1)
+	#if (DM_ODM_SUPPORT_TYPE != ODM_AP)
+
+		#include "rtl8723d/halhwimg8723d_bb.h"
+		#include "rtl8723d/halhwimg8723d_mac.h"
+		#include "rtl8723d/halhwimg8723d_rf.h"
+		#include "rtl8723d/phydm_regconfig8723d.h"
+		#include "rtl8723d/hal8723dreg.h"
+		#include "rtl8723d/phydm_rtl8723d.h"
+		#include "halrf/rtl8723d/halrf_8723d.h"
+		#include "rtl8723d/version_rtl8723d.h"
+	#endif
+	#if (DM_ODM_SUPPORT_TYPE == ODM_CE)
+		#ifdef DM_ODM_CE_MAC80211
+		#else
+		#include "rtl8723d_hal.h"
+		#endif
+	#endif
+#endif /* @8723D End */
+
+#if (RTL8710B_SUPPORT == 1)
+	#if (DM_ODM_SUPPORT_TYPE != ODM_AP)
+
+		#include "rtl8710b/halhwimg8710b_bb.h"
+		#include "rtl8710b/halhwimg8710b_mac.h"
+		#include "rtl8710b/halhwimg8710b_rf.h"
+		#include "rtl8710b/phydm_regconfig8710b.h"
+		#include "rtl8710b/hal8710breg.h"
+		#include "rtl8710b/phydm_rtl8710b.h"
+		#include "halrf/rtl8710b/halrf_8710b.h"
+		#include "rtl8710b/version_rtl8710b.h"
+	#endif
+	#if (DM_ODM_SUPPORT_TYPE == ODM_CE)
+		#include "rtl8710b_hal.h"
+	#endif
+#endif /* @8710B End */
+
+#if (RTL8197F_SUPPORT == 1)
+	#include "rtl8197f/halhwimg8197f_mac.h"
+	#include "rtl8197f/halhwimg8197f_rf.h"
+	#include "rtl8197f/halhwimg8197f_bb.h"
+	#include "rtl8197f/phydm_hal_api8197f.h"
+	#include "rtl8197f/version_rtl8197f.h"
+	#include "rtl8197f/phydm_rtl8197f.h"
+	#include "rtl8197f/phydm_regconfig8197f.h"
+	#include "halrf/rtl8197f/halrf_8197f.h"
+	#include "halrf/rtl8197f/halrf_iqk_8197f.h"
+	#include "halrf/rtl8197f/halrf_dpk_8197f.h"
+#endif
+
+#if (RTL8821C_SUPPORT == 1)
+	#include "rtl8821c/phydm_hal_api8821c.h"
+	#include "rtl8821c/halhwimg8821c_mac.h"
+	#include "rtl8821c/halhwimg8821c_rf.h"
+	#include "rtl8821c/halhwimg8821c_bb.h"
+	#include "rtl8821c/phydm_regconfig8821c.h"
+	#include "halrf/rtl8821c/halrf_8821c.h"
+	#include "rtl8821c/version_rtl8821c.h"
+	#if (DM_ODM_SUPPORT_TYPE == ODM_CE)
+		#ifdef DM_ODM_CE_MAC80211
+		#include "../halmac/halmac_reg_8821c.h"
+		#else
+		#include "rtl8821c_hal.h"
+		#endif
+	#endif
+#endif
+
+#if (RTL8192F_SUPPORT == 1)
+	#include "rtl8192f/halhwimg8192f_mac.h"
+	#include "rtl8192f/halhwimg8192f_rf.h"
+	#include "rtl8192f/halhwimg8192f_bb.h"
+	#include "rtl8192f/phydm_hal_api8192f.h"
+	#include "rtl8192f/version_rtl8192f.h"
+	#include "rtl8192f/phydm_rtl8192f.h"
+	#include "rtl8192f/phydm_regconfig8192f.h"
+	#include "halrf/rtl8192f/halrf_8192f.h"
+	#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
+		#include "halrf/rtl8192f/halrf_dpk_8192f.h"
+	#endif
+	#if (DM_ODM_SUPPORT_TYPE == ODM_CE)
+		#include "rtl8192f_hal.h"
+	#endif
+#endif
+
+#if (RTL8195B_SUPPORT == 1)
+	#include "halrf/rtl8195b/halrf_8195b.h"
+	#include "rtl8195b/phydm_hal_api8195b.h"
+	#include "rtl8195b/phydm_regconfig8195b.h"
+	#include "rtl8195b/halhwimg8195b_mac.h"
+	#include "rtl8195b/halhwimg8195b_rf.h"
+	#include "rtl8195b/halhwimg8195b_bb.h"
+	#include "rtl8195b/version_rtl8195b.h"
+	#include <hal_data.h> /*@HAL_DATA_TYPE*/
+#endif
+
+#if (RTL8198F_SUPPORT == 1)
+	#include "rtl8198f/phydm_regconfig8198f.h"
+	#include "rtl8198f/phydm_hal_api8198f.h"
+	#include "rtl8198f/halhwimg8198f_mac.h"
+	#include "rtl8198f/halhwimg8198f_rf.h"
+	#include "rtl8198f/halhwimg8198f_bb.h"
+	#include "rtl8198f/version_rtl8198f.h"
+	#include "halrf/rtl8198f/halrf_8198f.h"
+	#include "halrf/rtl8198f/halrf_iqk_8198f.h"
+#endif
+
+#if (RTL8822C_SUPPORT)
+	#include "rtl8822c/halhwimg8822c_mac.h"
+	#include "rtl8822c/halhwimg8822c_rf.h"
+	#include "rtl8822c/halhwimg8822c_bb.h"
+	#include "rtl8822c/phydm_regconfig8822c.h"
+	/*@#include "halrf/rtl8822c/halrf_8822c.h"*/
+	#include "rtl8822c/phydm_hal_api8822c.h"
+	#include "rtl8822c/version_rtl8822c.h"
+#endif
+#if (RTL8814B_SUPPORT == 1)
+	/*#include "rtl8814b/halhwimg8814b_mac.h"*/
+	/*#include "rtl8814b/halhwimg8814b_rf.h"*/
+	/*#include "rtl8814b/halhwimg8814b_bb.h"*/
+	/*#include "rtl8814b/phydm_regconfig8814b.h"*/
+	/*@#include "halrf/rtl8814b/halrf_8814b.h"*/
+	#include "rtl8814b/phydm_hal_api8814b.h"
+	/*#include "rtl8814b/version_rtl8814b.h"*/
+#endif
+
+#endif /* @__ODM_PRECOMP_H__ */
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/phydm_pre_define.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/phydm_pre_define.h
--- linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/phydm_pre_define.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/phydm_pre_define.h	2020-04-10 16:35:06.826660535 +0300
@@ -0,0 +1,817 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017  Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * The full GNU General Public License is included in this distribution in the
+ * file called LICENSE.
+ *
+ * Contact Information:
+ * wlanfae <wlanfae@realtek.com>
+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
+ * Hsinchu 300, Taiwan.
+ *
+ * Larry Finger <Larry.Finger@lwfinger.net>
+ *
+ *****************************************************************************/
+
+#ifndef __PHYDMPREDEFINE_H__
+#define __PHYDMPREDEFINE_H__
+
+/****************************************************************
+ * 1 ============================================================
+ * 1  Definition
+ * 1 ============================================================
+ ***************************************************************/
+
+#define PHYDM_CODE_BASE			"PHYDM_V030"
+#define PHYDM_RELEASE_DATE		"20180605.0"
+
+/*PHYDM API status*/
+#define	PHYDM_SET_FAIL			0
+#define	PHYDM_SET_SUCCESS		1
+#define	PHYDM_SET_NO_NEED		3
+
+/*PHYDM Set/Revert*/
+#define	PHYDM_SET			1
+#define	PHYDM_REVERT			2
+
+/* @Max path of IC */
+/*N-IC*/
+#define MAX_PATH_NUM_8188E		1
+#define MAX_PATH_NUM_8188F		1
+#define MAX_PATH_NUM_8710B		1
+#define MAX_PATH_NUM_8723B		1
+#define MAX_PATH_NUM_8723D		1
+#define MAX_PATH_NUM_8703B		1
+#define MAX_PATH_NUM_8192E		2
+#define MAX_PATH_NUM_8192F		2
+#define MAX_PATH_NUM_8197F		2
+#define MAX_PATH_NUM_8198F		4
+/*@AC-IC*/
+#define MAX_PATH_NUM_8821A		1
+#define MAX_PATH_NUM_8881A		1
+#define MAX_PATH_NUM_8821C		1
+#define MAX_PATH_NUM_8195B		1
+#define MAX_PATH_NUM_8812A		2
+#define MAX_PATH_NUM_8822B		2
+#define MAX_PATH_NUM_8822C		2
+#define MAX_PATH_NUM_8814A		4
+#define MAX_PATH_NUM_8814B		4
+#define MAX_PATH_NUM_8814C		4
+#define MAX_PATH_NUM_8195B		1
+
+/* @Max RF path */
+#define PHYDM_MAX_RF_PATH_N		2	/*@For old N-series IC*/
+#define PHYDM_MAX_RF_PATH		4
+
+/* number of entry */
+#if (DM_ODM_SUPPORT_TYPE & (ODM_CE))
+	#ifdef DM_ODM_CE_MAC80211
+		/* @defined in wifi.h (32+1) */
+	#else
+		#define	ASSOCIATE_ENTRY_NUM	MACID_NUM_SW_LIMIT  /* @Max size of asoc_entry[].*/
+	#endif
+	#define	ODM_ASSOCIATE_ENTRY_NUM	ASSOCIATE_ENTRY_NUM
+#elif(DM_ODM_SUPPORT_TYPE & (ODM_AP))
+	#define ASSOCIATE_ENTRY_NUM	NUM_STAT
+	#define	ODM_ASSOCIATE_ENTRY_NUM	(ASSOCIATE_ENTRY_NUM + 1)
+#elif(DM_ODM_SUPPORT_TYPE & (ODM_IOT))
+	#ifdef CONFIG_CONCURRENT_MODE
+		#define ASSOCIATE_ENTRY_NUM	NUM_STA + 2 /*@2 is for station mod*/
+	#else
+		#define ASSOCIATE_ENTRY_NUM	NUM_STA /*@8 is for max size of asoc_entry[].*/
+	#endif
+	#define	ODM_ASSOCIATE_ENTRY_NUM	ASSOCIATE_ENTRY_NUM
+#else
+	#define ODM_ASSOCIATE_ENTRY_NUM	(((ASSOCIATE_ENTRY_NUM + 1) * 3) + 1)
+#endif
+
+/* @-----MGN rate--------------------------------- */
+
+enum PDM_RATE_TYPE {
+	PDM_1SS			= 1,	/*VHT/HT 1SS*/
+	PDM_2SS			= 2,	/*VHT/HT 2SS*/
+	PDM_3SS			= 3,	/*VHT/HT 3SS*/
+	PDM_4SS			= 4,	/*VHT/HT 4SS*/
+	PDM_CCK			= 11,	/*@B*/
+	PDM_OFDM		= 12	/*@G*/
+};
+
+enum ODM_MGN_RATE {
+	ODM_MGN_1M		= 0x02,
+	ODM_MGN_2M		= 0x04,
+	ODM_MGN_5_5M		= 0x0B,
+	ODM_MGN_6M		= 0x0C,
+	ODM_MGN_9M		= 0x12,
+	ODM_MGN_11M		= 0x16,
+	ODM_MGN_12M		= 0x18,
+	ODM_MGN_18M		= 0x24,
+	ODM_MGN_24M		= 0x30,
+	ODM_MGN_36M		= 0x48,
+	ODM_MGN_48M		= 0x60,
+	ODM_MGN_54M		= 0x6C,
+	ODM_MGN_MCS32		= 0x7F,
+	ODM_MGN_MCS0		= 0x80,
+	ODM_MGN_MCS1,
+	ODM_MGN_MCS2,
+	ODM_MGN_MCS3,
+	ODM_MGN_MCS4,
+	ODM_MGN_MCS5,
+	ODM_MGN_MCS6,
+	ODM_MGN_MCS7		= 0x87,
+	ODM_MGN_MCS8,
+	ODM_MGN_MCS9,
+	ODM_MGN_MCS10,
+	ODM_MGN_MCS11,
+	ODM_MGN_MCS12,
+	ODM_MGN_MCS13,
+	ODM_MGN_MCS14,
+	ODM_MGN_MCS15,
+	ODM_MGN_MCS16		= 0x90,
+	ODM_MGN_MCS17,
+	ODM_MGN_MCS18,
+	ODM_MGN_MCS19,
+	ODM_MGN_MCS20,
+	ODM_MGN_MCS21,
+	ODM_MGN_MCS22,
+	ODM_MGN_MCS23,
+	ODM_MGN_MCS24		= 0x98,
+	ODM_MGN_MCS25,
+	ODM_MGN_MCS26,
+	ODM_MGN_MCS27,
+	ODM_MGN_MCS28,
+	ODM_MGN_MCS29,
+	ODM_MGN_MCS30,
+	ODM_MGN_MCS31,
+	ODM_MGN_VHT1SS_MCS0	= 0xa0,
+	ODM_MGN_VHT1SS_MCS1,
+	ODM_MGN_VHT1SS_MCS2,
+	ODM_MGN_VHT1SS_MCS3,
+	ODM_MGN_VHT1SS_MCS4,
+	ODM_MGN_VHT1SS_MCS5,
+	ODM_MGN_VHT1SS_MCS6,
+	ODM_MGN_VHT1SS_MCS7,
+	ODM_MGN_VHT1SS_MCS8,
+	ODM_MGN_VHT1SS_MCS9,
+	ODM_MGN_VHT2SS_MCS0	= 0xaa,
+	ODM_MGN_VHT2SS_MCS1	= 0xab,
+	ODM_MGN_VHT2SS_MCS2,
+	ODM_MGN_VHT2SS_MCS3,
+	ODM_MGN_VHT2SS_MCS4,
+	ODM_MGN_VHT2SS_MCS5	= 0xaf,
+	ODM_MGN_VHT2SS_MCS6	= 0xb0,
+	ODM_MGN_VHT2SS_MCS7,
+	ODM_MGN_VHT2SS_MCS8,
+	ODM_MGN_VHT2SS_MCS9	= 0xb3,
+	ODM_MGN_VHT3SS_MCS0	= 0xb4,
+	ODM_MGN_VHT3SS_MCS1,
+	ODM_MGN_VHT3SS_MCS2,
+	ODM_MGN_VHT3SS_MCS3,
+	ODM_MGN_VHT3SS_MCS4,
+	ODM_MGN_VHT3SS_MCS5,
+	ODM_MGN_VHT3SS_MCS6,
+	ODM_MGN_VHT3SS_MCS7	= 0xbb,
+	ODM_MGN_VHT3SS_MCS8	= 0xbc,
+	ODM_MGN_VHT3SS_MCS9	= 0xbd,
+	ODM_MGN_VHT4SS_MCS0	= 0xbe,
+	ODM_MGN_VHT4SS_MCS1,
+	ODM_MGN_VHT4SS_MCS2,
+	ODM_MGN_VHT4SS_MCS3,
+	ODM_MGN_VHT4SS_MCS4,
+	ODM_MGN_VHT4SS_MCS5,
+	ODM_MGN_VHT4SS_MCS6,
+	ODM_MGN_VHT4SS_MCS7,
+	ODM_MGN_VHT4SS_MCS8,
+	ODM_MGN_VHT4SS_MCS9	= 0xc7,
+	ODM_MGN_UNKNOWN
+};
+
+#define	ODM_MGN_MCS0_SG		0xc0
+#define	ODM_MGN_MCS1_SG		0xc1
+#define	ODM_MGN_MCS2_SG		0xc2
+#define	ODM_MGN_MCS3_SG		0xc3
+#define	ODM_MGN_MCS4_SG		0xc4
+#define	ODM_MGN_MCS5_SG		0xc5
+#define	ODM_MGN_MCS6_SG		0xc6
+#define	ODM_MGN_MCS7_SG		0xc7
+#define	ODM_MGN_MCS8_SG		0xc8
+#define	ODM_MGN_MCS9_SG		0xc9
+#define	ODM_MGN_MCS10_SG	0xca
+#define	ODM_MGN_MCS11_SG	0xcb
+#define	ODM_MGN_MCS12_SG	0xcc
+#define	ODM_MGN_MCS13_SG	0xcd
+#define	ODM_MGN_MCS14_SG	0xce
+#define	ODM_MGN_MCS15_SG	0xcf
+
+/* @-----DESC rate--------------------------------- */
+
+#define ODM_RATEMCS15_SG	0x1c
+#define ODM_RATEMCS32		0x20
+
+enum phydm_ctrl_info_rate {
+	ODM_RATE1M		= 0x00,
+	ODM_RATE2M		= 0x01,
+	ODM_RATE5_5M		= 0x02,
+	ODM_RATE11M		= 0x03,
+/* OFDM Rates, TxHT = 0 */
+	ODM_RATE6M		= 0x04,
+	ODM_RATE9M		= 0x05,
+	ODM_RATE12M		= 0x06,
+	ODM_RATE18M		= 0x07,
+	ODM_RATE24M		= 0x08,
+	ODM_RATE36M		= 0x09,
+	ODM_RATE48M		= 0x0A,
+	ODM_RATE54M		= 0x0B,
+/* @MCS Rates, TxHT = 1 */
+	ODM_RATEMCS0		= 0x0C,
+	ODM_RATEMCS1		= 0x0D,
+	ODM_RATEMCS2		= 0x0E,
+	ODM_RATEMCS3		= 0x0F,
+	ODM_RATEMCS4		= 0x10,
+	ODM_RATEMCS5		= 0x11,
+	ODM_RATEMCS6		= 0x12,
+	ODM_RATEMCS7		= 0x13,
+	ODM_RATEMCS8		= 0x14,
+	ODM_RATEMCS9		= 0x15,
+	ODM_RATEMCS10		= 0x16,
+	ODM_RATEMCS11		= 0x17,
+	ODM_RATEMCS12		= 0x18,
+	ODM_RATEMCS13		= 0x19,
+	ODM_RATEMCS14		= 0x1A,
+	ODM_RATEMCS15		= 0x1B,
+	ODM_RATEMCS16		= 0x1C,
+	ODM_RATEMCS17		= 0x1D,
+	ODM_RATEMCS18		= 0x1E,
+	ODM_RATEMCS19		= 0x1F,
+	ODM_RATEMCS20		= 0x20,
+	ODM_RATEMCS21		= 0x21,
+	ODM_RATEMCS22		= 0x22,
+	ODM_RATEMCS23		= 0x23,
+	ODM_RATEMCS24		= 0x24,
+	ODM_RATEMCS25		= 0x25,
+	ODM_RATEMCS26		= 0x26,
+	ODM_RATEMCS27		= 0x27,
+	ODM_RATEMCS28		= 0x28,
+	ODM_RATEMCS29		= 0x29,
+	ODM_RATEMCS30		= 0x2A,
+	ODM_RATEMCS31		= 0x2B,
+	ODM_RATEVHTSS1MCS0	= 0x2C,
+	ODM_RATEVHTSS1MCS1	= 0x2D,
+	ODM_RATEVHTSS1MCS2	= 0x2E,
+	ODM_RATEVHTSS1MCS3	= 0x2F,
+	ODM_RATEVHTSS1MCS4	= 0x30,
+	ODM_RATEVHTSS1MCS5	= 0x31,
+	ODM_RATEVHTSS1MCS6	= 0x32,
+	ODM_RATEVHTSS1MCS7	= 0x33,
+	ODM_RATEVHTSS1MCS8	= 0x34,
+	ODM_RATEVHTSS1MCS9	= 0x35,
+	ODM_RATEVHTSS2MCS0	= 0x36,
+	ODM_RATEVHTSS2MCS1	= 0x37,
+	ODM_RATEVHTSS2MCS2	= 0x38,
+	ODM_RATEVHTSS2MCS3	= 0x39,
+	ODM_RATEVHTSS2MCS4	= 0x3A,
+	ODM_RATEVHTSS2MCS5	= 0x3B,
+	ODM_RATEVHTSS2MCS6	= 0x3C,
+	ODM_RATEVHTSS2MCS7	= 0x3D,
+	ODM_RATEVHTSS2MCS8	= 0x3E,
+	ODM_RATEVHTSS2MCS9	= 0x3F,
+	ODM_RATEVHTSS3MCS0	= 0x40,
+	ODM_RATEVHTSS3MCS1	= 0x41,
+	ODM_RATEVHTSS3MCS2	= 0x42,
+	ODM_RATEVHTSS3MCS3	= 0x43,
+	ODM_RATEVHTSS3MCS4	= 0x44,
+	ODM_RATEVHTSS3MCS5	= 0x45,
+	ODM_RATEVHTSS3MCS6	= 0x46,
+	ODM_RATEVHTSS3MCS7	= 0x47,
+	ODM_RATEVHTSS3MCS8	= 0x48,
+	ODM_RATEVHTSS3MCS9	= 0x49,
+	ODM_RATEVHTSS4MCS0	= 0x4A,
+	ODM_RATEVHTSS4MCS1	= 0x4B,
+	ODM_RATEVHTSS4MCS2	= 0x4C,
+	ODM_RATEVHTSS4MCS3	= 0x4D,
+	ODM_RATEVHTSS4MCS4	= 0x4E,
+	ODM_RATEVHTSS4MCS5	= 0x4F,
+	ODM_RATEVHTSS4MCS6	= 0x50,
+	ODM_RATEVHTSS4MCS7	= 0x51,
+	ODM_RATEVHTSS4MCS8	= 0x52,
+	ODM_RATEVHTSS4MCS9	= 0x53,
+};
+
+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
+	#define ODM_NUM_RATE_IDX (ODM_RATEVHTSS4MCS9 + 1)
+#else
+	#if (RTL8192E_SUPPORT || RTL8197F_SUPPORT || RTL8192F_SUPPORT)
+		#define ODM_NUM_RATE_IDX (ODM_RATEMCS15 + 1)
+	#elif (RTL8723B_SUPPORT || RTL8188E_SUPPORT || RTL8188F_SUPPORT)
+		#define ODM_NUM_RATE_IDX (ODM_RATEMCS7 + 1)
+	#elif (RTL8821A_SUPPORT || RTL8881A_SUPPORT)
+		#define ODM_NUM_RATE_IDX (ODM_RATEVHTSS1MCS9 + 1)
+	#elif (RTL8812A_SUPPORT)
+		#define ODM_NUM_RATE_IDX (ODM_RATEVHTSS2MCS9 + 1)
+	#elif (RTL8814A_SUPPORT)
+		#define ODM_NUM_RATE_IDX (ODM_RATEVHTSS3MCS9 + 1)
+	#else
+		#define ODM_NUM_RATE_IDX (ODM_RATEVHTSS4MCS9 + 1)
+	#endif
+#endif
+
+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
+	#define CONFIG_SFW_SUPPORTED
+#endif
+
+/****************************************************************
+ * 1 ============================================================
+ * 1  enumeration
+ * 1 ============================================================
+ ***************************************************************/
+
+/*	ODM_CMNINFO_INTERFACE */
+enum odm_interface {
+	ODM_ITRF_PCIE	=	0x1,
+	ODM_ITRF_USB	=	0x2,
+	ODM_ITRF_SDIO	=	0x4,
+	ODM_ITRF_ALL	=	0x7,
+};
+
+/*@========[Run time IC flag] ===================================*/
+
+enum phydm_ic {
+	ODM_RTL8188E	=	BIT(0),
+	ODM_RTL8812	=	BIT(1),
+	ODM_RTL8821	=	BIT(2),
+	ODM_RTL8192E	=	BIT(3),
+	ODM_RTL8723B	=	BIT(4),
+	ODM_RTL8814A	=	BIT(5),
+	ODM_RTL8881A	=	BIT(6),
+	ODM_RTL8822B	=	BIT(7),
+	ODM_RTL8703B	=	BIT(8),
+	ODM_RTL8195A	=	BIT(9),
+	ODM_RTL8188F	=	BIT(10),
+	ODM_RTL8723D	=	BIT(11),
+	ODM_RTL8197F	=	BIT(12),
+	ODM_RTL8821C	=	BIT(13),
+	ODM_RTL8814B	=	BIT(14),
+	ODM_RTL8198F	=	BIT(15),
+	ODM_RTL8710B	=	BIT(16),
+	ODM_RTL8192F	=	BIT(17),
+	ODM_RTL8822C	=	BIT(18),
+	ODM_RTL8195B	=	BIT(19)
+};
+
+#define ODM_IC_N_1SS		(ODM_RTL8188E | ODM_RTL8188F | ODM_RTL8723B |\
+				 ODM_RTL8703B | ODM_RTL8723D | ODM_RTL8195A |\
+				 ODM_RTL8710B)
+#define ODM_IC_N_2SS		(ODM_RTL8192E | ODM_RTL8197F | ODM_RTL8192F)
+#define ODM_IC_N_3SS		0
+#define ODM_IC_N_4SS		0
+
+#define ODM_IC_AC_1SS		(ODM_RTL8881A | ODM_RTL8821 | ODM_RTL8821C |\
+				 ODM_RTL8195B)
+#define ODM_IC_AC_2SS		(ODM_RTL8812 | ODM_RTL8822B)
+#define ODM_IC_AC_3SS		0
+#define ODM_IC_AC_4SS		(ODM_RTL8814A)
+
+#define ODM_IC_JGR3_1SS		0
+#define ODM_IC_JGR3_2SS		(ODM_RTL8822C)
+#define ODM_IC_JGR3_3SS		0
+#define ODM_IC_JGR3_4SS		(ODM_RTL8198F | ODM_RTL8814B)
+
+/*@====the following macro DO NOT need to update when adding a new IC======= */
+#define ODM_IC_1SS		(ODM_IC_N_1SS | ODM_IC_AC_1SS | ODM_IC_JGR3_1SS)
+#define ODM_IC_2SS		(ODM_IC_N_2SS | ODM_IC_AC_2SS | ODM_IC_JGR3_2SS)
+#define ODM_IC_3SS		(ODM_IC_N_3SS | ODM_IC_AC_3SS | ODM_IC_JGR3_3SS)
+#define ODM_IC_4SS		(ODM_IC_N_4SS | ODM_IC_AC_4SS | ODM_IC_JGR3_4SS)
+
+#define PHYDM_IC_ABOVE_1SS	(ODM_IC_1SS | ODM_IC_2SS | ODM_IC_3SS |\
+				 ODM_IC_4SS)
+#define PHYDM_IC_ABOVE_2SS	(ODM_IC_2SS | ODM_IC_3SS | ODM_IC_4SS)
+#define PHYDM_IC_ABOVE_3SS	(ODM_IC_3SS | ODM_IC_4SS)
+#define PHYDM_IC_ABOVE_4SS	ODM_IC_4SS
+
+#define ODM_IC_11N_SERIES	(ODM_IC_N_1SS | ODM_IC_N_2SS | ODM_IC_N_3SS |\
+				 ODM_IC_N_4SS)
+#define ODM_IC_11AC_SERIES	(ODM_IC_AC_1SS | ODM_IC_AC_2SS |\
+				 ODM_IC_AC_3SS | ODM_IC_AC_4SS)
+#define ODM_IC_JGR3_SERIES	(ODM_IC_JGR3_1SS | ODM_IC_JGR3_2SS |\
+				 ODM_IC_JGR3_3SS | ODM_IC_JGR3_4SS)
+/*@====================================================*/
+
+#define ODM_IC_11AC_1_SERIES	(ODM_RTL8812 | ODM_RTL8821 | ODM_RTL8881A)
+#define ODM_IC_11AC_2_SERIES	(ODM_RTL8814A | ODM_RTL8822B | ODM_RTL8821C |\
+				 ODM_RTL8195B)
+
+/*@[Phy status type]*/
+#define PHYSTS_2ND_TYPE_IC	(ODM_RTL8197F | ODM_RTL8822B | ODM_RTL8723D |\
+				 ODM_RTL8821C | ODM_RTL8710B | ODM_RTL8195B |\
+				 ODM_RTL8192F)
+#define PHYSTS_3RD_TYPE_IC	(ODM_RTL8198F | ODM_RTL8814B | ODM_RTL8822C)
+/*@[FW Type]*/
+#define PHYDM_IC_8051_SERIES	(ODM_RTL8881A | ODM_RTL8812 | ODM_RTL8821 |\
+				 ODM_RTL8192E | ODM_RTL8723B | ODM_RTL8703B |\
+				 ODM_RTL8188F | ODM_RTL8192F)
+#define PHYDM_IC_3081_SERIES	(ODM_RTL8814A | ODM_RTL8822B | ODM_RTL8197F |\
+				 ODM_RTL8821C | ODM_RTL8195B | ODM_RTL8198F |\
+				 ODM_RTL8822C)
+/*@[LA mode]*/
+#define PHYDM_IC_SUPPORT_LA_MODE (ODM_RTL8814A | ODM_RTL8822B | ODM_RTL8197F |\
+				  ODM_RTL8821C | ODM_RTL8195B | ODM_RTL8198F |\
+				  ODM_RTL8192F | ODM_RTL8822C)
+/*@[BF]*/
+#define ODM_IC_TXBF_SUPPORT	(ODM_RTL8192E | ODM_RTL8812 | ODM_RTL8821 |\
+				 ODM_RTL8814A | ODM_RTL8881A | ODM_RTL8822B |\
+				 ODM_RTL8197F | ODM_RTL8821C | ODM_RTL8195B |\
+				 ODM_RTL8198F | ODM_RTL8822C)
+#define PHYDM_IC_SUPPORT_MU_BFEE (ODM_RTL8822B | ODM_RTL8821C | ODM_RTL8814B |\
+				  ODM_RTL8195B | ODM_RTL8198F | ODM_RTL8822C)
+#define PHYDM_IC_SUPPORT_MU_BFER (ODM_RTL8822B | ODM_RTL8814B | ODM_RTL8198F |\
+				  ODM_RTL8822C)
+/*@[PHYDM API]*/
+#define CMN_API_SUPPORT_IC (ODM_RTL8822B | ODM_RTL8197F | ODM_RTL8192F |\
+			    ODM_RTL8821C | ODM_RTL8195B | ODM_RTL8822C |\
+			    ODM_RTL8198F)
+
+/*@========[Compile time IC flag] ========================*/
+/*@========[AC-3/AC/N Support] ===========================*/
+
+#if (RTL8814B_SUPPORT || RTL8198F_SUPPORT || RTL8822C_SUPPORT)
+	#define PHYDM_IC_JGR3_SERIES_SUPPORT
+	#if (RTL8814B_SUPPORT || RTL8822C_SUPPORT)
+		#define PHYDM_IC_JGR3_80M_SUPPORT
+	#endif
+#endif
+
+#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
+
+	#ifdef RTK_AC_SUPPORT
+	#define ODM_IC_11AC_SERIES_SUPPORT	1
+	#else
+	#define ODM_IC_11AC_SERIES_SUPPORT	0
+	#endif
+
+	#define ODM_IC_11N_SERIES_SUPPORT	1
+
+#elif (DM_ODM_SUPPORT_TYPE == ODM_WIN)
+
+	#define ODM_IC_11AC_SERIES_SUPPORT	1
+	#define ODM_IC_11N_SERIES_SUPPORT	1
+
+#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) && defined(DM_ODM_CE_MAC80211)
+
+	#define ODM_IC_11AC_SERIES_SUPPORT	1
+	#define ODM_IC_11N_SERIES_SUPPORT	1
+
+#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) && defined(DM_ODM_CE_MAC80211_V2)
+
+	#define ODM_IC_11AC_SERIES_SUPPORT		1
+	#define ODM_IC_11N_SERIES_SUPPORT			1
+
+#else /*ODM_CE*/
+
+	#if (RTL8188E_SUPPORT || RTL8723B_SUPPORT || RTL8192E_SUPPORT ||\
+	     RTL8195A_SUPPORT || RTL8703B_SUPPORT || RTL8188F_SUPPORT ||\
+	     RTL8723D_SUPPORT || RTL8197F_SUPPORT || RTL8710B_SUPPORT ||\
+	     RTL8192F_SUPPORT)
+		#define ODM_IC_11N_SERIES_SUPPORT	1
+		#define ODM_IC_11AC_SERIES_SUPPORT	0
+	#else
+		#define ODM_IC_11N_SERIES_SUPPORT	0
+		#define ODM_IC_11AC_SERIES_SUPPORT	1
+	#endif
+#endif
+
+/*@===IC SS Compile Flag, prepare for code size reduction==============*/
+#if (RTL8188E_SUPPORT || RTL8188F_SUPPORT || RTL8723B_SUPPORT ||\
+	RTL8703B_SUPPORT || RTL8723D_SUPPORT || RTL8881A_SUPPORT ||\
+	RTL8821A_SUPPORT || RTL8821C_SUPPORT || RTL8195A_SUPPORT ||\
+	RTL8710B_SUPPORT || RTL8195B_SUPPORT)
+
+	#define PHYDM_COMPILE_IC_1SS
+#endif
+
+#if (RTL8192E_SUPPORT || RTL8197F_SUPPORT || RTL8812A_SUPPORT ||\
+	RTL8822B_SUPPORT || RTL8192F_SUPPORT || RTL8822C_SUPPORT)
+	#define PHYDM_COMPILE_IC_2SS
+#endif
+
+/*@#define PHYDM_COMPILE_IC_3SS*/
+
+#if ((RTL8814B_SUPPORT) || (RTL8814A_SUPPORT) || (RTL8198F_SUPPORT))
+	#define PHYDM_COMPILE_IC_4SS
+#endif
+
+/*@==[ABOVE N-SS COMPILE FLAG]=================================================*/
+#if (defined(PHYDM_COMPILE_IC_1SS) || defined(PHYDM_COMPILE_IC_2SS) ||\
+	defined(PHYDM_COMPILE_IC_3SS) || defined(PHYDM_COMPILE_IC_4SS))
+	#define PHYDM_COMPILE_ABOVE_1SS
+#endif
+
+#if (defined(PHYDM_COMPILE_IC_2SS) || defined(PHYDM_COMPILE_IC_3SS) ||\
+	defined(PHYDM_COMPILE_IC_4SS))
+	#define PHYDM_COMPILE_ABOVE_2SS
+#endif
+
+#if (defined(PHYDM_COMPILE_IC_3SS) || defined(PHYDM_COMPILE_IC_4SS))
+	#define PHYDM_COMPILE_ABOVE_3SS
+#endif
+
+#if (defined(PHYDM_COMPILE_IC_4SS))
+	#define PHYDM_COMPILE_ABOVE_4SS
+#endif
+
+/*@========[New Phy-Status Support] ========================*/
+#if (RTL8197F_SUPPORT || RTL8723D_SUPPORT || RTL8822B_SUPPORT ||\
+	RTL8821C_SUPPORT || RTL8710B_SUPPORT || RTL8195B_SUPPORT ||\
+	RTL8192F_SUPPORT)
+	#define ODM_PHY_STATUS_NEW_TYPE_SUPPORT			1
+#else
+	#define ODM_PHY_STATUS_NEW_TYPE_SUPPORT			0
+#endif
+
+#if (RTL8198F_SUPPORT) || (RTL8814B_SUPPORT) || (RTL8822C_SUPPORT)
+	#define PHYSTS_3RD_TYPE_SUPPORT
+#endif
+
+#if (RTL8198F_SUPPORT || RTL8814B_SUPPORT || RTL8822C_SUPPORT) 
+	#define BB_RAM_SUPPORT
+#endif
+
+/*@============================================================================*/
+
+#if (RTL8822B_SUPPORT || RTL8197F_SUPPORT || RTL8821C_SUPPORT ||\
+	RTL8192F_SUPPORT || RTL8195B_SUPPORT || RTL8822C_SUPPORT ||\
+	RTL8198F_SUPPORT)
+#define PHYDM_COMMON_API_SUPPORT
+#endif
+
+
+#define	CCK_RATE_NUM		4
+#define	OFDM_RATE_NUM		8
+
+#define	LEGACY_RATE_NUM		12
+
+#define	HT_RATE_NUM_4SS		32
+#define	VHT_RATE_NUM_4SS	40
+
+#define	HT_RATE_NUM_3SS		24
+#define	VHT_RATE_NUM_3SS	30
+
+#define	HT_RATE_NUM_2SS		16
+#define	VHT_RATE_NUM_2SS	20
+
+#define	HT_RATE_NUM_1SS		8
+#define	VHT_RATE_NUM_1SS	10
+#if (defined(PHYDM_COMPILE_ABOVE_4SS))
+	#define	HT_RATE_NUM	HT_RATE_NUM_4SS
+	#define	VHT_RATE_NUM	VHT_RATE_NUM_4SS
+#elif (defined(PHYDM_COMPILE_ABOVE_3SS))
+	#define	HT_RATE_NUM	HT_RATE_NUM_3SS
+	#define	VHT_RATE_NUM	VHT_RATE_NUM_3SS
+#elif (defined(PHYDM_COMPILE_ABOVE_2SS))
+	#define	HT_RATE_NUM	HT_RATE_NUM_2SS
+	#define	VHT_RATE_NUM	VHT_RATE_NUM_2SS
+#else
+	#define	HT_RATE_NUM	HT_RATE_NUM_1SS
+	#define	VHT_RATE_NUM	VHT_RATE_NUM_1SS
+#endif
+
+#define	LOW_BW_RATE_NUM		VHT_RATE_NUM
+
+enum phydm_ic_ip {
+	PHYDM_IC_N		= 0,
+	PHYDM_IC_AC		= 1,
+	PHYDM_IC_JGR3		= 2
+};
+
+/* ODM_CMNINFO_CUT_VER */
+enum odm_cut_version {
+	ODM_CUT_A		= 0,
+	ODM_CUT_B		= 1,
+	ODM_CUT_C		= 2,
+	ODM_CUT_D		= 3,
+	ODM_CUT_E		= 4,
+	ODM_CUT_F		= 5,
+	ODM_CUT_G		= 6,
+	ODM_CUT_H		= 7,
+	ODM_CUT_I		= 8,
+	ODM_CUT_J		= 9,
+	ODM_CUT_K		= 10,
+	ODM_CUT_TEST		= 15,
+};
+
+/* ODM_CMNINFO_FAB_VER */
+enum odm_fab {
+	ODM_TSMC		= 0,
+	ODM_UMC			= 1,
+};
+
+/* ODM_CMNINFO_OP_MODE */
+enum odm_operation_mode {
+	ODM_NO_LINK		= BIT(0),
+	ODM_LINK		= BIT(1),
+	ODM_SCAN		= BIT(2),
+	ODM_POWERSAVE		= BIT(3),
+	ODM_AP_MODE		= BIT(4),
+	ODM_CLIENT_MODE		= BIT(5),
+	ODM_AD_HOC		= BIT(6),
+	ODM_WIFI_DIRECT		= BIT(7),
+	ODM_WIFI_DISPLAY	= BIT(8),
+};
+
+/* ODM_CMNINFO_WM_MODE */
+#if (DM_ODM_SUPPORT_TYPE & (ODM_CE))
+enum odm_wireless_mode {
+	ODM_WM_UNKNOW		= 0x0,
+	ODM_WM_B		= BIT(0),
+	ODM_WM_G		= BIT(1),
+	ODM_WM_A		= BIT(2),
+	ODM_WM_N24G		= BIT(3),
+	ODM_WM_N5G		= BIT(4),
+	ODM_WM_AUTO		= BIT(5),
+	ODM_WM_AC		= BIT(6),
+};
+#else
+enum odm_wireless_mode {
+	ODM_WM_UNKNOWN		= 0x00,/*@0x0*/
+	ODM_WM_A		= BIT(0), /* @0x1*/
+	ODM_WM_B		= BIT(1), /* @0x2*/
+	ODM_WM_G		= BIT(2),/* @0x4*/
+	ODM_WM_AUTO		= BIT(3),/* @0x8*/
+	ODM_WM_N24G		= BIT(4),/* @0x10*/
+	ODM_WM_N5G		= BIT(5),/* @0x20*/
+	ODM_WM_AC_5G		= BIT(6),/* @0x40*/
+	ODM_WM_AC_24G		= BIT(7),/* @0x80*/
+	ODM_WM_AC_ONLY		= BIT(8),/* @0x100*/
+	ODM_WM_MAX		= BIT(11)/* @0x800*/
+
+};
+#endif
+
+/* ODM_CMNINFO_BAND */
+enum odm_band_type {
+#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
+	ODM_BAND_2_4G		= BIT(0),
+	ODM_BAND_5G		= BIT(1),
+#else
+	ODM_BAND_2_4G		= 0,
+	ODM_BAND_5G,
+	ODM_BAND_ON_BOTH,
+	ODM_BANDMAX
+#endif
+};
+
+/* ODM_CMNINFO_SEC_CHNL_OFFSET */
+enum phydm_sec_chnl_offset {
+	PHYDM_DONT_CARE		= 0,
+	PHYDM_BELOW		= 1,
+	PHYDM_ABOVE		= 2
+};
+
+/* ODM_CMNINFO_SEC_MODE */
+enum odm_security {
+	ODM_SEC_OPEN		= 0,
+	ODM_SEC_WEP40		= 1,
+	ODM_SEC_TKIP		= 2,
+	ODM_SEC_RESERVE		= 3,
+	ODM_SEC_AESCCMP		= 4,
+	ODM_SEC_WEP104		= 5,
+	ODM_WEP_WPA_MIXED	= 6, /* WEP + WPA */
+	ODM_SEC_SMS4		= 7,
+};
+
+/* ODM_CMNINFO_CHNL */
+
+/* ODM_CMNINFO_BOARD_TYPE */
+enum odm_board_type {
+	ODM_BOARD_DEFAULT	= 0,	  /* The DEFAULT case. */
+	ODM_BOARD_MINICARD	= BIT(0), /* @0 = non-mini card, 1= mini card. */
+	ODM_BOARD_SLIM		= BIT(1), /* @0 = non-slim card, 1 = slim card */
+	ODM_BOARD_BT		= BIT(2), /* @0 = without BT card, 1 = with BT */
+	ODM_BOARD_EXT_PA	= BIT(3), /* @0 = no 2G ext-PA, 1 = existing 2G ext-PA */
+	ODM_BOARD_EXT_LNA	= BIT(4), /* @0 = no 2G ext-LNA, 1 = existing 2G ext-LNA */
+	ODM_BOARD_EXT_TRSW	= BIT(5), /* @0 = no ext-TRSW, 1 = existing ext-TRSW */
+	ODM_BOARD_EXT_PA_5G	= BIT(6), /* @0 = no 5G ext-PA, 1 = existing 5G ext-PA */
+	ODM_BOARD_EXT_LNA_5G	= BIT(7), /* @0 = no 5G ext-LNA, 1 = existing 5G ext-LNA */
+};
+
+enum odm_package_type {
+	ODM_PACKAGE_DEFAULT	= 0,
+	ODM_PACKAGE_QFN68	= BIT(0),
+	ODM_PACKAGE_TFBGA90	= BIT(1),
+	ODM_PACKAGE_TFBGA79	= BIT(2),
+};
+
+enum odm_type_gpa {
+	TYPE_GPA0		= 0x0000,
+	TYPE_GPA1		= 0x0055,
+	TYPE_GPA2		= 0x00AA,
+	TYPE_GPA3		= 0x00FF,
+	TYPE_GPA4		= 0x5500,
+	TYPE_GPA5		= 0x5555,
+	TYPE_GPA6		= 0x55AA,
+	TYPE_GPA7		= 0x55FF,
+	TYPE_GPA8		= 0xAA00,
+	TYPE_GPA9		= 0xAA55,
+	TYPE_GPA10		= 0xAAAA,
+	TYPE_GPA11		= 0xAAFF,
+	TYPE_GPA12		= 0xFF00,
+	TYPE_GPA13		= 0xFF55,
+	TYPE_GPA14		= 0xFFAA,
+	TYPE_GPA15		= 0xFFFF,
+};
+
+enum odm_type_apa {
+	TYPE_APA0		= 0x0000,
+	TYPE_APA1		= 0x0055,
+	TYPE_APA2		= 0x00AA,
+	TYPE_APA3		= 0x00FF,
+	TYPE_APA4		= 0x5500,
+	TYPE_APA5		= 0x5555,
+	TYPE_APA6		= 0x55AA,
+	TYPE_APA7		= 0x55FF,
+	TYPE_APA8		= 0xAA00,
+	TYPE_APA9		= 0xAA55,
+	TYPE_APA10		= 0xAAAA,
+	TYPE_APA11		= 0xAAFF,
+	TYPE_APA12		= 0xFF00,
+	TYPE_APA13		= 0xFF55,
+	TYPE_APA14		= 0xFFAA,
+	TYPE_APA15		= 0xFFFF,
+};
+
+enum odm_type_glna {
+	TYPE_GLNA0		= 0x0000,
+	TYPE_GLNA1		= 0x0055,
+	TYPE_GLNA2		= 0x00AA,
+	TYPE_GLNA3		= 0x00FF,
+	TYPE_GLNA4		= 0x5500,
+	TYPE_GLNA5		= 0x5555,
+	TYPE_GLNA6		= 0x55AA,
+	TYPE_GLNA7		= 0x55FF,
+	TYPE_GLNA8		= 0xAA00,
+	TYPE_GLNA9		= 0xAA55,
+	TYPE_GLNA10		= 0xAAAA,
+	TYPE_GLNA11		= 0xAAFF,
+	TYPE_GLNA12		= 0xFF00,
+	TYPE_GLNA13		= 0xFF55,
+	TYPE_GLNA14		= 0xFFAA,
+	TYPE_GLNA15		= 0xFFFF,
+};
+
+enum odm_type_alna {
+	TYPE_ALNA0		= 0x0000,
+	TYPE_ALNA1		= 0x0055,
+	TYPE_ALNA2		= 0x00AA,
+	TYPE_ALNA3		= 0x00FF,
+	TYPE_ALNA4		= 0x5500,
+	TYPE_ALNA5		= 0x5555,
+	TYPE_ALNA6		= 0x55AA,
+	TYPE_ALNA7		= 0x55FF,
+	TYPE_ALNA8		= 0xAA00,
+	TYPE_ALNA9		= 0xAA55,
+	TYPE_ALNA10		= 0xAAAA,
+	TYPE_ALNA11		= 0xAAFF,
+	TYPE_ALNA12		= 0xFF00,
+	TYPE_ALNA13		= 0xFF55,
+	TYPE_ALNA14		= 0xFFAA,
+	TYPE_ALNA15		= 0xFFFF,
+};
+
+#define	PAUSE_FAIL		0
+#define	PAUSE_SUCCESS		1
+
+enum odm_parameter_init {
+	ODM_PRE_SETTING		= 0,
+	ODM_POST_SETTING	= 1,
+	ODM_INIT_FW_SETTING
+};
+
+enum phydm_pause_type {
+	PHYDM_PAUSE		= 1,	/*Pause & Set new value*/
+	PHYDM_PAUSE_NO_SET	= 2,	/*Pause & Stay in current value*/
+	PHYDM_RESUME		= 3
+};
+
+enum phydm_pause_level {
+	PHYDM_PAUSE_RELEASE	= -1,
+	PHYDM_PAUSE_LEVEL_0	= 0,	/* @Low Priority function */
+	PHYDM_PAUSE_LEVEL_1	= 1,	/* @Middle Priority function */
+	PHYDM_PAUSE_LEVEL_2	= 2,	/* @High priority function (ex: Check hang function) */
+	PHYDM_PAUSE_LEVEL_3	= 3,	/* @Debug function (the highest priority) */
+	PHYDM_PAUSE_MAX_NUM	= 4
+};
+
+enum phydm_dis_hw_fun {
+	HW_FUN_DIS		= 0,	/*@Disable a cetain HW function & backup the original value*/
+	HW_FUN_RESUME		= 1	/*Revert */
+};
+
+#endif
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/phydm_primary_cca.c linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/phydm_primary_cca.c
--- linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/phydm_primary_cca.c	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/phydm_primary_cca.c	2020-04-10 16:35:06.826660535 +0300
@@ -0,0 +1,173 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017  Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * The full GNU General Public License is included in this distribution in the
+ * file called LICENSE.
+ *
+ * Contact Information:
+ * wlanfae <wlanfae@realtek.com>
+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
+ * Hsinchu 300, Taiwan.
+ *
+ * Larry Finger <Larry.Finger@lwfinger.net>
+ *
+ *****************************************************************************/
+
+/*************************************************************
+ * include files
+ ************************************************************/
+#include "mp_precomp.h"
+#include "phydm_precomp.h"
+#ifdef PHYDM_PRIMARY_CCA
+
+void phydm_write_dynamic_cca(
+	void *dm_void,
+	u8 curr_mf_state
+
+	)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct phydm_pricca_struct *pri_cca = &dm->dm_pri_cca;
+
+	if (pri_cca->mf_state == curr_mf_state)
+		return;
+
+	if (dm->support_ic_type & ODM_IC_11N_SERIES) {
+		if (curr_mf_state == MF_USC_LSC) {
+			odm_set_bb_reg(dm, R_0xc6c, 0x180, MF_USC_LSC);
+			/*@40M OFDM MF CCA threshold*/
+			odm_set_bb_reg(dm, R_0xc84, 0xf0000000,
+				       pri_cca->cca_th_40m_bkp);
+		} else {
+			odm_set_bb_reg(dm, R_0xc6c, 0x180, curr_mf_state);
+			/*@40M OFDM MF CCA threshold*/
+			odm_set_bb_reg(dm, R_0xc84, 0xf0000000, 0);
+		}
+	}
+
+	pri_cca->mf_state = curr_mf_state;
+	PHYDM_DBG(dm, DBG_PRI_CCA, "Set CCA at ((%s SB)), 0xc6c[8:7]=((%d))\n",
+		  ((curr_mf_state == MF_USC_LSC) ? "D" :
+		  ((curr_mf_state == MF_LSC) ? "L" : "U")), curr_mf_state);
+}
+
+void phydm_primary_cca_reset(
+	void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct phydm_pricca_struct *pri_cca = &dm->dm_pri_cca;
+
+	PHYDM_DBG(dm, DBG_PRI_CCA, "[PriCCA] Reset\n");
+	pri_cca->mf_state = 0xff;
+	pri_cca->pre_bw = (enum channel_width)0xff;
+	phydm_write_dynamic_cca(dm, MF_USC_LSC);
+}
+
+void phydm_primary_cca_11n(
+	void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct phydm_pricca_struct *pri_cca = &dm->dm_pri_cca;
+	enum channel_width curr_bw = (enum channel_width)*dm->band_width;
+
+	if (!(dm->support_ability & ODM_BB_PRIMARY_CCA))
+		return;
+
+	if (!dm->is_linked) {
+		PHYDM_DBG(dm, DBG_PRI_CCA, "[PriCCA][No Link!!!]\n");
+
+		if (pri_cca->pri_cca_is_become_linked) {
+			phydm_primary_cca_reset(dm);
+			pri_cca->pri_cca_is_become_linked = dm->is_linked;
+		}
+		return;
+	} else {
+		if (!pri_cca->pri_cca_is_become_linked) {
+			PHYDM_DBG(dm, DBG_PRI_CCA, "[PriCCA][Linked !!!]\n");
+			pri_cca->pri_cca_is_become_linked = dm->is_linked;
+		}
+	}
+
+	if (curr_bw != pri_cca->pre_bw) {
+		PHYDM_DBG(dm, DBG_PRI_CCA, "[Primary CCA] start ==>\n");
+		pri_cca->pre_bw = curr_bw;
+
+		if (curr_bw == CHANNEL_WIDTH_40) {
+			if (*dm->sec_ch_offset == SECOND_CH_AT_LSB) {
+			/* Primary CH @ upper sideband*/
+				PHYDM_DBG(dm, DBG_PRI_CCA,
+					  "BW40M, Primary CH at USB\n");
+				phydm_write_dynamic_cca(dm, MF_USC);
+			} else {
+			/*Primary CH @ lower sideband*/
+				PHYDM_DBG(dm, DBG_PRI_CCA,
+					  "BW40M, Primary CH at LSB\n");
+				phydm_write_dynamic_cca(dm, MF_LSC);
+			}
+		} else {
+			PHYDM_DBG(dm, DBG_PRI_CCA, "Not BW40M, USB + LSB\n");
+			phydm_primary_cca_reset(dm);
+		}
+	}
+}
+
+boolean
+odm_dynamic_primary_cca_dup_rts(void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct phydm_pricca_struct *pri_cca = &dm->dm_pri_cca;
+
+	return pri_cca->dup_rts_flag;
+}
+
+void phydm_primary_cca_init(void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct phydm_pricca_struct *pri_cca = &dm->dm_pri_cca;
+
+	if (!(dm->support_ability & ODM_BB_PRIMARY_CCA))
+		return;
+
+	if (!(dm->support_ic_type & ODM_IC_11N_SERIES))
+		return;
+
+	PHYDM_DBG(dm, DBG_PRI_CCA, "[PriCCA] Init ==>\n");
+#if (RTL8188E_SUPPORT == 1) || (RTL8192E_SUPPORT == 1)
+	pri_cca->dup_rts_flag = 0;
+	pri_cca->intf_flag = 0;
+	pri_cca->intf_type = 0;
+	pri_cca->monitor_flag = 0;
+	pri_cca->pri_cca_flag = 0;
+	pri_cca->ch_offset = 0;
+#endif
+	pri_cca->mf_state = 0xff;
+	pri_cca->pre_bw = (enum channel_width)0xff;
+	pri_cca->cca_th_40m_bkp = (u8)odm_get_bb_reg(dm, R_0xc84, 0xf0000000);
+}
+
+void phydm_primary_cca(void *dm_void)
+{
+#ifdef PHYDM_PRIMARY_CCA
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+
+	if (!(dm->support_ic_type & ODM_IC_11N_SERIES))
+		return;
+
+	if (!(dm->support_ability & ODM_BB_PRIMARY_CCA))
+		return;
+
+	phydm_primary_cca_11n(dm);
+
+#endif
+}
+#endif
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/phydm_primary_cca.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/phydm_primary_cca.h
--- linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/phydm_primary_cca.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/phydm_primary_cca.h	2020-04-10 16:35:06.826660535 +0300
@@ -0,0 +1,87 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017  Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * The full GNU General Public License is included in this distribution in the
+ * file called LICENSE.
+ *
+ * Contact Information:
+ * wlanfae <wlanfae@realtek.com>
+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
+ * Hsinchu 300, Taiwan.
+ *
+ * Larry Finger <Larry.Finger@lwfinger.net>
+ *
+ *****************************************************************************/
+
+#ifndef __PHYDM_PRIMARYCCA_H__
+#define __PHYDM_PRIMARYCCA_H__
+
+#ifdef PHYDM_PRIMARY_CCA
+#define PRIMARYCCA_VERSION "2.0"
+
+/*@============================================================*/
+/*@Definition */
+/*@============================================================*/
+
+#if (DM_ODM_SUPPORT_TYPE == ODM_CE)
+#define	SECOND_CH_AT_LSB	2	/*@primary CH @ MSB,  SD4: HAL_PRIME_CHNL_OFFSET_UPPER*/
+#define	SECOND_CH_AT_USB	1	/*@primary CH @ LSB,   SD4: HAL_PRIME_CHNL_OFFSET_LOWER*/
+#elif (DM_ODM_SUPPORT_TYPE == ODM_WIN)
+#define	SECOND_CH_AT_LSB	2	/*@primary CH @ MSB,  SD7: HAL_PRIME_CHNL_OFFSET_UPPER*/
+#define	SECOND_CH_AT_USB	1	/*@primary CH @ LSB,   SD7: HAL_PRIME_CHNL_OFFSET_LOWER*/
+#else /*if (DM_ODM_SUPPORT_TYPE == ODM_AP)*/
+#define	SECOND_CH_AT_LSB	1	/*@primary CH @ MSB,  SD8: HT_2NDCH_OFFSET_BELOW*/
+#define	SECOND_CH_AT_USB	2	/*@primary CH @ LSB,   SD8: HT_2NDCH_OFFSET_ABOVE*/
+#endif
+
+#define	OFDMCCA_TH		500
+#define	bw_ind_bias		500
+#define	PRI_CCA_MONITOR_TIME	30
+
+/*@============================================================*/
+/*structure and define*/
+/*@============================================================*/
+enum primary_cca_ch_position { /*N-series REG0xc6c[8:7]*/
+	MF_USC_LSC	= 0,
+	MF_LSC		= 1,
+	MF_USC		= 2
+};
+
+struct phydm_pricca_struct {
+	#if (RTL8188E_SUPPORT == 1) || (RTL8192E_SUPPORT == 1)
+	u8	pri_cca_flag;
+	u8	intf_flag;
+	u8	intf_type;
+	u8	monitor_flag;
+	u8	ch_offset;
+	#endif
+	u8	dup_rts_flag;
+	u8	cca_th_40m_bkp; /*@c84[31:28]*/
+	enum channel_width	pre_bw;
+	u8	pri_cca_is_become_linked;
+	u8	mf_state;
+};
+
+/*@============================================================*/
+/*@function prototype*/
+/*@============================================================*/
+void phydm_write_dynamic_cca(void *dm_void, u8 curr_mf_state);
+
+boolean odm_dynamic_primary_cca_dup_rts(void *dm_void);
+
+void phydm_primary_cca_init(void *dm_void);
+
+void phydm_primary_cca(void *dm_void);
+#endif /*@#ifdef PHYDM_PRIMARY_CCA*/
+#endif /*@#ifndef	__PHYDM_PRIMARYCCA_H__*/
+
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/phydm_psd.c linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/phydm_psd.c
--- linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/phydm_psd.c	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/phydm_psd.c	2020-04-10 16:35:06.826660535 +0300
@@ -0,0 +1,380 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017  Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * The full GNU General Public License is included in this distribution in the
+ * file called LICENSE.
+ *
+ * Contact Information:
+ * wlanfae <wlanfae@realtek.com>
+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
+ * Hsinchu 300, Taiwan.
+ *
+ * Larry Finger <Larry.Finger@lwfinger.net>
+ *
+ *****************************************************************************/
+
+/******************************************************************************
+ * include files
+ *****************************************************************************/
+#include "mp_precomp.h"
+#include "phydm_precomp.h"
+
+#ifdef CONFIG_PSD_TOOL
+u32 phydm_get_psd_data(void *dm_void, u32 psd_tone_idx, u32 igi)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct psd_info *dm_psd_table = &dm->dm_psd_table;
+	u32 psd_report = 0;
+
+	odm_set_bb_reg(dm, dm_psd_table->psd_reg, 0x3ff, psd_tone_idx);
+
+	odm_set_bb_reg(dm, dm_psd_table->psd_reg, BIT(22), 1); /*PSD trigger start*/
+	ODM_delay_us(10);
+	odm_set_bb_reg(dm, dm_psd_table->psd_reg, BIT(22), 0); /*PSD trigger stop*/
+
+	if (dm->support_ic_type & ODM_RTL8821C) {
+		psd_report = odm_get_bb_reg(dm, dm_psd_table->psd_report_reg,
+					    0xffffff);
+		psd_report = psd_report >> 5;
+	} else {
+		psd_report = odm_get_bb_reg(dm, dm_psd_table->psd_report_reg,
+					    0xffff);
+	}
+	psd_report = odm_convert_to_db(psd_report) + igi;
+
+	return psd_report;
+}
+
+u8 psd_result_cali_tone_8821[7] = {21, 28, 33, 93, 98, 105, 127};
+u8 psd_result_cali_val_8821[7] = {67, 69, 71, 72, 71, 69, 67};
+
+void phydm_psd(void *dm_void, u32 igi, u16 start_point, u16 stop_point)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct psd_info *dm_psd_table = &dm->dm_psd_table;
+	u32 i = 0, mod_tone_idx;
+	u32 t = 0;
+	u16 fft_max_half_bw;
+	u32 psd_igi_a_reg;
+	u32 psd_igi_b_reg;
+	u16 psd_fc_channel = dm_psd_table->psd_fc_channel;
+	u8 ag_rf_mode_reg = 0;
+	u8 rf_reg18_9_8 = 0;
+	u32 psd_result_tmp = 0;
+	u8 psd_result = 0;
+	u8 psd_result_cali_tone[7] = {0};
+	u8 psd_result_cali_val[7] = {0};
+	u8 noise_table_idx = 0;
+	u8 set_result;
+
+	if (dm->support_ic_type == ODM_RTL8821) {
+		odm_move_memory(dm, psd_result_cali_tone,
+				psd_result_cali_tone_8821, 7);
+		odm_move_memory(dm, psd_result_cali_val,
+				psd_result_cali_val_8821, 7);
+	}
+
+	dm_psd_table->psd_in_progress = 1;
+
+	/*@[Stop DIG]*/
+	dm->support_ability &= ~(ODM_BB_DIG);
+	dm->support_ability &= ~(ODM_BB_FA_CNT);
+
+	PHYDM_DBG(dm, ODM_COMP_API, "PSD Start =>\n");
+
+	if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
+		psd_igi_a_reg = 0xc50;
+		psd_igi_b_reg = 0xe50;
+	} else {
+		psd_igi_a_reg = 0xc50;
+		psd_igi_b_reg = 0xc58;
+	}
+
+	/*@[back up IGI]*/
+	dm_psd_table->initial_gain_backup = odm_get_bb_reg(dm, psd_igi_a_reg,
+							   0xff);
+	odm_set_bb_reg(dm, psd_igi_a_reg, 0xff, 0x6e); /*@IGI target at 0dBm & make it can't CCA*/
+	odm_set_bb_reg(dm, psd_igi_b_reg, 0xff, 0x6e); /*@IGI target at 0dBm & make it can't CCA*/
+	ODM_delay_us(10);
+
+	if (phydm_stop_ic_trx(dm, PHYDM_SET) == PHYDM_SET_FAIL) {
+		PHYDM_DBG(dm, ODM_COMP_API, "STOP_TRX_FAIL\n");
+		return;
+	}
+
+	/*@[Set IGI]*/
+	odm_set_bb_reg(dm, psd_igi_a_reg, 0xff, igi);
+	odm_set_bb_reg(dm, psd_igi_b_reg, 0xff, igi);
+
+	/*@[Backup RF Reg]*/
+	dm_psd_table->rf_0x18_bkp = odm_get_rf_reg(dm, RF_PATH_A, RF_0x18,
+						   RFREGOFFSETMASK);
+	dm_psd_table->rf_0x18_bkp_b = odm_get_rf_reg(dm, RF_PATH_B, RF_0x18,
+						     RFREGOFFSETMASK);
+
+	if (psd_fc_channel > 14) {
+		rf_reg18_9_8 = 1;
+		if (psd_fc_channel >= 36 && psd_fc_channel <= 64)
+			ag_rf_mode_reg = 0x1;
+		else if (psd_fc_channel >= 100 && psd_fc_channel <= 140)
+			ag_rf_mode_reg = 0x3;
+		else if (psd_fc_channel > 140)
+			ag_rf_mode_reg = 0x5;
+	}
+
+	/* RF path-a */
+	odm_set_rf_reg(dm, RF_PATH_A, RF_0x18, 0xff, psd_fc_channel); /* Set RF fc*/
+	odm_set_rf_reg(dm, RF_PATH_A, RF_0x18, 0x300, rf_reg18_9_8);
+	/*@2b'11: 20MHz, 2b'10: 40MHz, 2b'01: 80MHz */
+	odm_set_rf_reg(dm, RF_PATH_A, RF_0x18, 0xc00,
+		       dm_psd_table->psd_bw_rf_reg);
+	/* Set RF ag fc mode*/
+	odm_set_rf_reg(dm, RF_PATH_A, RF_0x18, 0xf0000, ag_rf_mode_reg);
+
+	/* RF path-b */
+	odm_set_rf_reg(dm, RF_PATH_B, RF_0x18, 0xff, psd_fc_channel); /* Set RF fc*/
+	odm_set_rf_reg(dm, RF_PATH_B, RF_0x18, 0x300, rf_reg18_9_8);
+	/*@2b'11: 20MHz, 2b'10: 40MHz, 2b'01: 80MHz */
+	odm_set_rf_reg(dm, RF_PATH_B, RF_0x18, 0xc00,
+		       dm_psd_table->psd_bw_rf_reg);
+	odm_set_rf_reg(dm, RF_PATH_B, RF_0x18, 0xf0000, ag_rf_mode_reg); /* Set RF ag fc mode*/
+
+	PHYDM_DBG(dm, ODM_COMP_API, "0xc50=((0x%x))\n",
+		  odm_get_bb_reg(dm, R_0xc50, MASKDWORD));
+#if 0
+	/*PHYDM_DBG(dm, ODM_COMP_API, "RF0x0=((0x%x))\n", odm_get_rf_reg(dm, RF_PATH_A, RF_0x0, RFREGOFFSETMASK));*/
+#endif
+	PHYDM_DBG(dm, ODM_COMP_API, "RF0x18=((0x%x))\n",
+		  odm_get_rf_reg(dm, RF_PATH_A, RF_0x18, RFREGOFFSETMASK));
+
+	/*@[Stop 3-wires]*/
+	phydm_stop_3_wire(dm, PHYDM_SET);
+
+	ODM_delay_us(10);
+
+	if (stop_point > (dm_psd_table->fft_smp_point - 1))
+		stop_point = (dm_psd_table->fft_smp_point - 1);
+
+	if (start_point > (dm_psd_table->fft_smp_point - 1))
+		start_point = (dm_psd_table->fft_smp_point - 1);
+
+	if (start_point > stop_point)
+		stop_point = start_point;
+
+	for (i = start_point; i <= stop_point; i++) {
+		fft_max_half_bw = (dm_psd_table->fft_smp_point) >> 1;
+
+		if (i < fft_max_half_bw)
+			mod_tone_idx = i + fft_max_half_bw;
+		else
+			mod_tone_idx = i - fft_max_half_bw;
+
+		psd_result_tmp = 0;
+		for (t = 0; t < dm_psd_table->sw_avg_time; t++)
+			psd_result_tmp += phydm_get_psd_data(dm, mod_tone_idx,
+							     igi);
+		psd_result =
+			(u8)((psd_result_tmp / dm_psd_table->sw_avg_time)) -
+			dm_psd_table->psd_pwr_common_offset;
+
+		if (dm_psd_table->fft_smp_point == 128 &&
+		    dm_psd_table->noise_k_en) {
+			if (i > psd_result_cali_tone[noise_table_idx])
+				noise_table_idx++;
+
+			if (noise_table_idx > 6)
+				noise_table_idx = 6;
+
+			if (psd_result >= psd_result_cali_val[noise_table_idx])
+				psd_result =
+					psd_result -
+					psd_result_cali_val[noise_table_idx];
+			else
+				psd_result = 0;
+
+			dm_psd_table->psd_result[i] = psd_result;
+		}
+
+		PHYDM_DBG(dm, ODM_COMP_API, "[%d] N_cali = %d, PSD = %d\n",
+			  mod_tone_idx, psd_result_cali_val[noise_table_idx],
+			  psd_result);
+	}
+
+	/*@[Start 3-wires]*/
+	phydm_stop_3_wire(dm, PHYDM_REVERT);
+
+	ODM_delay_us(10);
+
+	/*@[Revert Reg]*/
+	set_result = phydm_stop_ic_trx(dm, PHYDM_REVERT);
+
+	odm_set_bb_reg(dm, psd_igi_a_reg, 0xff,
+		       dm_psd_table->initial_gain_backup);
+	odm_set_bb_reg(dm, psd_igi_b_reg, 0xff,
+		       dm_psd_table->initial_gain_backup);
+
+	odm_set_rf_reg(dm, RF_PATH_A, RF_0x18, RFREGOFFSETMASK,
+		       dm_psd_table->rf_0x18_bkp);
+	odm_set_rf_reg(dm, RF_PATH_B, RF_0x18, RFREGOFFSETMASK,
+		       dm_psd_table->rf_0x18_bkp_b);
+
+	PHYDM_DBG(dm, ODM_COMP_API, "PSD finished\n\n");
+
+	dm->support_ability |= ODM_BB_DIG;
+	dm->support_ability |= ODM_BB_FA_CNT;
+	dm_psd_table->psd_in_progress = 0;
+}
+
+void phydm_psd_para_setting(void *dm_void, u8 sw_avg_time,
+			    u8 hw_avg_time, u8 i_q_setting,
+			    u16 fft_smp_point, u8 ant_sel,
+			    u8 psd_input, u8 channel, u8 noise_k_en)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct psd_info *dm_psd_table = &dm->dm_psd_table;
+	u8 fft_smp_point_idx = 0;
+
+	dm_psd_table->fft_smp_point = fft_smp_point;
+
+	if (sw_avg_time == 0)
+		sw_avg_time = 1;
+
+	dm_psd_table->sw_avg_time = sw_avg_time;
+	dm_psd_table->psd_fc_channel = channel;
+	dm_psd_table->noise_k_en = noise_k_en;
+
+	if (fft_smp_point == 128)
+		fft_smp_point_idx = 0;
+	else if (fft_smp_point == 256)
+		fft_smp_point_idx = 1;
+	else if (fft_smp_point == 512)
+		fft_smp_point_idx = 2;
+	else if (fft_smp_point == 1024)
+		fft_smp_point_idx = 3;
+
+	if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
+		odm_set_bb_reg(dm, R_0x910, BIT(11) | BIT(10), i_q_setting);
+		odm_set_bb_reg(dm, R_0x910, BIT(13) | BIT(12), hw_avg_time);
+		odm_set_bb_reg(dm, R_0x910, BIT(15) | BIT(14),
+			       fft_smp_point_idx);
+		odm_set_bb_reg(dm, R_0x910, BIT(17) | BIT(16), ant_sel);
+		odm_set_bb_reg(dm, R_0x910, BIT(23), psd_input);
+#if 0
+	} else {	/*ODM_IC_11N_SERIES*/
+#endif
+	}
+
+	/*@bw = (*dm->band_width); //ODM_BW20M */
+	/*@channel = *(dm->channel);*/
+}
+
+void phydm_psd_init(void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct psd_info *dm_psd_table = &dm->dm_psd_table;
+
+	PHYDM_DBG(dm, ODM_COMP_API, "PSD para init\n");
+
+	dm_psd_table->psd_in_progress = false;
+
+	if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
+		dm_psd_table->psd_reg = 0x910;
+		dm_psd_table->psd_report_reg = 0xF44;
+
+		if (ODM_IC_11AC_2_SERIES)
+			/*@2b'11: 20MHz, 2b'10: 40MHz, 2b'01: 80MHz */
+			dm_psd_table->psd_bw_rf_reg = 1;
+		else
+			/*@2b'11: 20MHz, 2b'10: 40MHz, 2b'01: 80MHz */
+			dm_psd_table->psd_bw_rf_reg = 2;
+
+	} else {
+		dm_psd_table->psd_reg = 0x808;
+		dm_psd_table->psd_report_reg = 0x8B4;
+		/*@2b'11: 20MHz, 2b'10: 40MHz, 2b'01: 80MHz */
+		dm_psd_table->psd_bw_rf_reg = 2;
+	}
+
+	dm_psd_table->psd_pwr_common_offset = 0;
+
+	phydm_psd_para_setting(dm, 1, 2, 3, 128, 0, 0, 7, 0);
+#if 0
+	/*phydm_psd(dm, 0x3c, 0, 127);*/ /* target at -50dBm */
+#endif
+}
+
+void phydm_psd_debug(void *dm_void, char input[][16], u32 *_used,
+		     char *output, u32 *_out_len)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	char help[] = "-h";
+	u32 var1[10] = {0};
+	u32 used = *_used;
+	u32 out_len = *_out_len;
+	u8 i;
+
+	if ((strcmp(input[1], help) == 0)) {
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "{0} {sw_avg} {hw_avg 0:3} {1:I,2:Q,3:IQ} {fft_point: 128*(1:4)} {path_sel 0~3} {0:ADC, 1:RXIQC} {CH} {noise_k}\n");
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "{1} {IGI(hex)} {start_point} {stop_point}\n");
+		goto out;
+	}
+
+	PHYDM_SSCANF(input[1], DCMD_DECIMAL, &var1[0]);
+
+	if (var1[0] == 0) {
+		for (i = 1; i < 10; i++) {
+			if (input[i + 1])
+				PHYDM_SSCANF(input[i + 1], DCMD_DECIMAL,
+					     &var1[i]);
+		}
+
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "sw_avg_time=((%d)), hw_avg_time=((%d)), IQ=((%d)), fft=((%d)), path=((%d)), input =((%d)) ch=((%d)), noise_k=((%d))\n",
+			 var1[1], var1[2], var1[3], var1[4], var1[5], var1[6],
+			 (u8)var1[7], (u8)var1[8]);
+		phydm_psd_para_setting(dm, (u8)var1[1], (u8)var1[2],
+				       (u8)var1[3], (u16)var1[4], (u8)var1[5],
+				       (u8)var1[6], (u8)var1[7], (u8)var1[8]);
+
+	} else if (var1[0] == 1) {
+		PHYDM_SSCANF(input[2], DCMD_HEX, &var1[1]);
+		PHYDM_SSCANF(input[3], DCMD_DECIMAL, &var1[2]);
+		PHYDM_SSCANF(input[4], DCMD_DECIMAL, &var1[3]);
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "IGI=((0x%x)), start_point=((%d)), stop_point=((%d))\n",
+			 var1[1], var1[2], var1[3]);
+		dm->debug_components |= ODM_COMP_API;
+		phydm_psd(dm, var1[1], (u16)var1[2], (u16)var1[3]);
+		dm->debug_components &= (~ODM_COMP_API);
+	}
+
+out:
+	*_used = used;
+	*_out_len = out_len;
+}
+
+u8 phydm_get_psd_result_table(void *dm_void, int index)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct psd_info *dm_psd_table = &dm->dm_psd_table;
+	u8 result = 0;
+
+	if (index < 128)
+		result = dm_psd_table->psd_result[index];
+
+	return result;
+}
+
+#endif
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/phydm_psd.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/phydm_psd.h
--- linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/phydm_psd.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/phydm_psd.h	2020-04-10 16:35:06.826660535 +0300
@@ -0,0 +1,68 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017  Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * The full GNU General Public License is included in this distribution in the
+ * file called LICENSE.
+ *
+ * Contact Information:
+ * wlanfae <wlanfae@realtek.com>
+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
+ * Hsinchu 300, Taiwan.
+ *
+ * Larry Finger <Larry.Finger@lwfinger.net>
+ *
+ *****************************************************************************/
+
+#ifndef __PHYDMPSD_H__
+#define __PHYDMPSD_H__
+
+/*@#define PSD_VERSION	"1.0"*/ /*@2016.09.22  Dino*/
+#define PSD_VERSION "1.1" /*@2016.10.07  Dino, Add Option for PSD Tone index Selection */
+
+#ifdef CONFIG_PSD_TOOL
+
+
+struct psd_info {
+	u8	psd_in_progress;
+	u32	psd_reg;
+	u32	psd_report_reg;
+	u8	psd_pwr_common_offset;
+	u16	sw_avg_time;
+	u16	fft_smp_point;
+	u32	initial_gain_backup;
+	u32	rf_0x18_bkp;
+	u32	rf_0x18_bkp_b;
+	u16	psd_fc_channel;
+	u32	psd_bw_rf_reg;
+	u8	psd_result[128];
+	u8	noise_k_en;
+};
+
+u32 phydm_get_psd_data(void *dm_void, u32 psd_tone_idx, u32 igi);
+
+void phydm_psd_debug(void *dm_void, char input[][16], u32 *_used,
+		     char *output, u32 *_out_len);
+
+void phydm_psd(void *dm_void, u32 igi, u16 start_point, u16 stop_point);
+
+void phydm_psd_para_setting(void *dm_void, u8 sw_avg_time,
+			    u8 hw_avg_time, u8 i_q_setting,
+			    u16 fft_smp_point, u8 ant_sel,
+			    u8 psd_input, u8 channel, u8 noise_k_en);
+
+void phydm_psd_init(void *dm_void);
+
+u8 phydm_get_psd_result_table(void *dm_void, int index);
+
+#endif
+#endif
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/phydm_rainfo.c linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/phydm_rainfo.c
--- linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/phydm_rainfo.c	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/phydm_rainfo.c	2020-04-10 16:35:06.827660581 +0300
@@ -0,0 +1,2134 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017  Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * The full GNU General Public License is included in this distribution in the
+ * file called LICENSE.
+ *
+ * Contact Information:
+ * wlanfae <wlanfae@realtek.com>
+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
+ * Hsinchu 300, Taiwan.
+ *
+ * Larry Finger <Larry.Finger@lwfinger.net>
+ *
+ *****************************************************************************/
+
+/*@************************************************************
+ * include files
+ ************************************************************/
+#include "mp_precomp.h"
+#include "phydm_precomp.h"
+
+boolean phydm_is_vht_rate(void *dm_void, u8 rate)
+{
+	return ((rate & 0x7f) >= ODM_RATEVHTSS1MCS0) ? true : false;
+}
+
+boolean phydm_is_ht_rate(void *dm_void, u8 rate)
+{
+	return (((rate & 0x7f) >= ODM_RATEMCS0) &&
+		((rate & 0x7f) <= ODM_RATEMCS31)) ? true : false;
+}
+
+boolean phydm_is_ofdm_rate(void *dm_void, u8 rate)
+{
+	return (((rate & 0x7f) >= ODM_RATE6M) &&
+		((rate & 0x7f) <= ODM_RATE54M)) ? true : false;
+}
+
+boolean phydm_is_cck_rate(void *dm_void, u8 rate)
+{
+	return ((rate & 0x7f) <= ODM_RATE11M) ? true : false;
+}
+
+u8 phydm_rate_2_rate_digit(void *dm_void, u8 rate)
+{
+	u8 legacy_table[12] = {1, 2, 5, 11, 6, 9, 12, 18, 24, 36, 48, 54};
+	u8 rate_idx = rate & 0x7f; /*remove bit7 SGI*/
+	u8 rate_digit = 0;
+
+	if (rate_idx >= ODM_RATEVHTSS1MCS0)
+		rate_digit = (rate_idx - ODM_RATEVHTSS1MCS0) % 10;
+	else if (rate_idx >= ODM_RATEMCS0)
+		rate_digit = (rate_idx - ODM_RATEMCS0);
+	else if (rate_idx <= ODM_RATE54M)
+		rate_digit = legacy_table[rate_idx];
+
+	return rate_digit;
+}
+
+u8 phydm_rate_type_2_num_ss(void *dm_void, enum PDM_RATE_TYPE type)
+{
+	u8 num_ss = 1;
+
+	switch (type) {
+	case PDM_CCK:
+	case PDM_OFDM:
+	case PDM_1SS:
+		num_ss = 1;
+		break;
+	case PDM_2SS:
+		num_ss = 2;
+		break;
+	case PDM_3SS:
+		num_ss = 3;
+		break;
+	case PDM_4SS:
+		num_ss = 4;
+		break;
+	default:
+		break;
+	}
+
+	return num_ss;
+}
+
+u8 phydm_rate_to_num_ss(void *dm_void, u8 data_rate)
+{
+	u8 num_ss = 1;
+
+	if (data_rate <= ODM_RATE54M)
+		num_ss = 1;
+	else if (data_rate <= ODM_RATEMCS31)
+		num_ss = ((data_rate - ODM_RATEMCS0) >> 3) + 1;
+	else if (data_rate <= ODM_RATEVHTSS1MCS9)
+		num_ss = 1;
+	else if (data_rate <= ODM_RATEVHTSS2MCS9)
+		num_ss = 2;
+	else if (data_rate <= ODM_RATEVHTSS3MCS9)
+		num_ss = 3;
+	else if (data_rate <= ODM_RATEVHTSS4MCS9)
+		num_ss = 4;
+
+	return num_ss;
+}
+
+void phydm_h2C_debug(void *dm_void, char input[][16], u32 *_used,
+		     char *output, u32 *_out_len)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	u32 used = *_used;
+	u32 out_len = *_out_len;
+	u32 dm_value[10] = {0};
+	u8 i = 0, input_idx = 0;
+	u8 h2c_parameter[H2C_MAX_LENGTH] = {0};
+	u8 phydm_h2c_id = 0;
+
+	for (i = 0; i < 8; i++) {
+		if (input[i + 1]) {
+			PHYDM_SSCANF(input[i + 1], DCMD_HEX, &dm_value[i]);
+			input_idx++;
+		}
+	}
+
+	if (input_idx == 0)
+		return;
+
+	phydm_h2c_id = (u8)dm_value[0];
+
+	PDM_SNPF(out_len, used, output + used, out_len - used,
+		 "Phydm Send H2C_ID (( 0x%x))\n", phydm_h2c_id);
+
+	for (i = 0; i < H2C_MAX_LENGTH; i++) {
+		h2c_parameter[i] = (u8)dm_value[i + 1];
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "H2C: Byte[%d] = ((0x%x))\n", i, h2c_parameter[i]);
+	}
+
+	odm_fill_h2c_cmd(dm, phydm_h2c_id, H2C_MAX_LENGTH, h2c_parameter);
+
+	*_used = used;
+	*_out_len = out_len;
+}
+
+void phydm_fw_fix_rate(void *dm_void, u8 en, u8 macid, u8 bw, u8 rate)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	u32 reg_u32_tmp;
+
+	if (dm->support_ic_type & PHYDM_IC_8051_SERIES) {
+		reg_u32_tmp = (bw << 24) | (rate << 16) | (macid << 8) | en;
+		odm_set_bb_reg(dm, R_0x4a0, MASKDWORD, reg_u32_tmp);
+
+	} else {
+		if (en == 1)
+			reg_u32_tmp = BYTE_2_DWORD(0x60, macid, bw, rate);
+		else
+			reg_u32_tmp = 0x40000000;
+
+		odm_set_bb_reg(dm, R_0x450, MASKDWORD, reg_u32_tmp);
+	}
+	if (en == 1) {
+		PHYDM_DBG(dm, ODM_COMP_API,
+			  "FW fix TX rate[id =%d], %dM, Rate(%d)=", macid,
+			  (20 << bw), rate);
+		phydm_print_rate(dm, rate, ODM_COMP_API);
+	} else {
+		PHYDM_DBG(dm, ODM_COMP_API, "Auto Rate\n");
+	}
+}
+
+void phydm_ra_debug(void *dm_void, char input[][16], u32 *_used, char *output,
+		    u32 *_out_len)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct ra_table *ra_tab = &dm->dm_ra_table;
+	u32 used = *_used;
+	u32 out_len = *_out_len;
+	char help[] = "-h";
+	u32 var[5] = {0};
+	u8 macid = 0, bw = 0, rate = 0;
+	u8 i = 0;
+
+	for (i = 0; i < 5; i++) {
+		if (input[i + 1])
+			PHYDM_SSCANF(input[i + 1], DCMD_DECIMAL, &var[i]);
+	}
+
+	if ((strcmp(input[1], help) == 0)) {
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "{1} {0:-,1:+} {ofst}: set offset\n");
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "{1} {100}: show offset\n");
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "{2} {en} {macid} {bw} {rate}: fw fix rate\n");
+
+	} else if (var[0] == 1) { /*@Adjust PCR offset*/
+
+		if (var[1] == 100) {
+			PDM_SNPF(out_len, used, output + used, out_len - used,
+				 "[Get] RA_ofst=((%s%d))\n",
+				 ((ra_tab->ra_ofst_direc) ? "+" : "-"),
+				 ra_tab->ra_th_ofst);
+
+		} else if (var[1] == 0) {
+			ra_tab->ra_ofst_direc = 0;
+			ra_tab->ra_th_ofst = (u8)var[2];
+			PDM_SNPF(out_len, used, output + used, out_len - used,
+				 "[Set] RA_ofst=((-%d))\n", ra_tab->ra_th_ofst);
+		} else if (var[1] == 1) {
+			ra_tab->ra_ofst_direc = 1;
+			ra_tab->ra_th_ofst = (u8)var[2];
+			PDM_SNPF(out_len, used, output + used, out_len - used,
+				 "[Set] RA_ofst=((+%d))\n", ra_tab->ra_th_ofst);
+		}
+
+	} else if (var[0] == 2) { /*@FW fix rate*/
+		macid = (u8)var[2];
+		bw = (u8)var[3];
+		rate = (u8)var[4];
+
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "[FW fix TX Rate] {en, macid,bw,rate}={%d, %d, %d, 0x%x}",
+			 var[1], macid, bw, rate);
+
+		phydm_fw_fix_rate(dm, (u8)var[1], macid, bw, rate);
+
+	} else {
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "[Set] Error\n");
+	}
+	*_used = used;
+	*_out_len = out_len;
+}
+
+void odm_c2h_ra_para_report_handler(void *dm_void, u8 *cmd_buf, u8 cmd_len)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	u8 mode = cmd_buf[0]; /*Retry Penalty, NH, NL*/
+	u8 i;
+
+	PHYDM_DBG(dm, DBG_FW_TRACE, "[%s] [mode: %d]----------------------->\n",
+		  __func__, mode);
+
+	if (mode == RADBG_DEBUG_MONITOR1) {
+		if (dm->support_ic_type & PHYDM_IC_3081_SERIES) {
+			PHYDM_DBG(dm, DBG_FW_TRACE, "%5s  %d\n", "RSSI =",
+				  cmd_buf[1]);
+			PHYDM_DBG(dm, DBG_FW_TRACE, "%5s  0x%x\n", "rate =",
+				  cmd_buf[2] & 0x7f);
+			PHYDM_DBG(dm, DBG_FW_TRACE, "%5s  %d\n", "SGI =",
+				  (cmd_buf[2] & 0x80) >> 7);
+			PHYDM_DBG(dm, DBG_FW_TRACE, "%5s  %d\n", "BW =",
+				  cmd_buf[3]);
+			PHYDM_DBG(dm, DBG_FW_TRACE, "%5s  %d\n", "BW_max =",
+				  cmd_buf[4]);
+			PHYDM_DBG(dm, DBG_FW_TRACE, "%5s  0x%x\n",
+				  "multi_rate0 =", cmd_buf[5]);
+			PHYDM_DBG(dm, DBG_FW_TRACE, "%5s  0x%x\n",
+				  "multi_rate1 =", cmd_buf[6]);
+			PHYDM_DBG(dm, DBG_FW_TRACE, "%5s  %d\n", "DISRA =",
+				  cmd_buf[7]);
+			PHYDM_DBG(dm, DBG_FW_TRACE, "%5s  %d\n", "VHT_EN =",
+				  cmd_buf[8]);
+			PHYDM_DBG(dm, DBG_FW_TRACE, "%5s  %d\n",
+				  "SGI_support =", cmd_buf[9]);
+			PHYDM_DBG(dm, DBG_FW_TRACE, "%5s  %d\n", "try_ness =",
+				  cmd_buf[10]);
+			PHYDM_DBG(dm, DBG_FW_TRACE, "%5s  0x%x\n", "pre_rate =",
+				  cmd_buf[11]);
+		} else {
+			PHYDM_DBG(dm, DBG_FW_TRACE, "%5s  %d\n", "RSSI =",
+				  cmd_buf[1]);
+			PHYDM_DBG(dm, DBG_FW_TRACE, "%5s  %x\n", "BW =",
+				  cmd_buf[2]);
+			PHYDM_DBG(dm, DBG_FW_TRACE, "%5s  %d\n", "DISRA =",
+				  cmd_buf[3]);
+			PHYDM_DBG(dm, DBG_FW_TRACE, "%5s  %d\n", "VHT_EN =",
+				  cmd_buf[4]);
+			PHYDM_DBG(dm, DBG_FW_TRACE, "%5s  %d\n",
+				  "Hightest rate =", cmd_buf[5]);
+			PHYDM_DBG(dm, DBG_FW_TRACE, "%5s  0x%x\n",
+				  "Lowest rate =", cmd_buf[6]);
+			PHYDM_DBG(dm, DBG_FW_TRACE, "%5s  0x%x\n",
+				  "SGI_support =", cmd_buf[7]);
+			PHYDM_DBG(dm, DBG_FW_TRACE, "%5s  %d\n", "Rate_ID =",
+				  cmd_buf[8]);
+		}
+	} else if (mode == RADBG_DEBUG_MONITOR2) {
+		if (dm->support_ic_type & PHYDM_IC_3081_SERIES) {
+			PHYDM_DBG(dm, DBG_FW_TRACE, "%5s  %d\n", "rate_id =",
+				  cmd_buf[1]);
+			PHYDM_DBG(dm, DBG_FW_TRACE, "%5s  0x%x\n",
+				  "highest_rate =", cmd_buf[2]);
+			PHYDM_DBG(dm, DBG_FW_TRACE, "%5s  0x%x\n",
+				  "lowest_rate =", cmd_buf[3]);
+
+			for (i = 4; i <= 11; i++)
+				PHYDM_DBG(dm, DBG_FW_TRACE, "RAMASK =  0x%x\n",
+					  cmd_buf[i]);
+		} else {
+			PHYDM_DBG(dm, DBG_FW_TRACE,
+				  "%5s  %x%x  %x%x  %x%x  %x%x\n", "RA Mask:",
+				  cmd_buf[8], cmd_buf[7], cmd_buf[6],
+				  cmd_buf[5], cmd_buf[4], cmd_buf[3],
+				  cmd_buf[2], cmd_buf[1]);
+		}
+	} else if (mode == RADBG_DEBUG_MONITOR3) {
+		for (i = 0; i < (cmd_len - 1); i++)
+			PHYDM_DBG(dm, DBG_FW_TRACE, "content[%d] = %d\n", i,
+				  cmd_buf[1 + i]);
+	} else if (mode == RADBG_DEBUG_MONITOR4)
+		PHYDM_DBG(dm, DBG_FW_TRACE, "%5s  {%d.%d}\n", "RA version =",
+			  cmd_buf[1], cmd_buf[2]);
+	else if (mode == RADBG_DEBUG_MONITOR5) {
+		PHYDM_DBG(dm, DBG_FW_TRACE, "%5s  0x%x\n", "Current rate =",
+			  cmd_buf[1]);
+		PHYDM_DBG(dm, DBG_FW_TRACE, "%5s  %d\n", "Retry ratio =",
+			  cmd_buf[2]);
+		PHYDM_DBG(dm, DBG_FW_TRACE, "%5s  %d\n", "rate down ratio =",
+			  cmd_buf[3]);
+		PHYDM_DBG(dm, DBG_FW_TRACE, "%5s  0x%x\n", "highest rate =",
+			  cmd_buf[4]);
+		PHYDM_DBG(dm, DBG_FW_TRACE, "%5s  {0x%x 0x%x}\n", "Muti-try =",
+			  cmd_buf[5], cmd_buf[6]);
+		PHYDM_DBG(dm, DBG_FW_TRACE, "%5s  0x%x%x%x%x%x\n", "RA mask =",
+			  cmd_buf[11], cmd_buf[10], cmd_buf[9], cmd_buf[8],
+			  cmd_buf[7]);
+	}
+	PHYDM_DBG(dm, DBG_FW_TRACE, "-------------------------------\n");
+}
+
+void phydm_ra_dynamic_retry_count(void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+
+	if (!(dm->support_ability & ODM_BB_DYNAMIC_ARFR))
+		return;
+
+#if 0
+	/*PHYDM_DBG(dm, DBG_RA, "dm->pre_b_noisy = %d\n", dm->pre_b_noisy );*/
+#endif
+	if (dm->pre_b_noisy != dm->noisy_decision) {
+		if (dm->noisy_decision) {
+			PHYDM_DBG(dm, DBG_DYN_ARFR, "Noisy Env. RA fallback\n");
+			odm_set_mac_reg(dm, R_0x430, MASKDWORD, 0x0);
+			odm_set_mac_reg(dm, R_0x434, MASKDWORD, 0x04030201);
+		} else {
+			PHYDM_DBG(dm, DBG_DYN_ARFR, "Clean Env. RA fallback\n");
+			odm_set_mac_reg(dm, R_0x430, MASKDWORD, 0x01000000);
+			odm_set_mac_reg(dm, R_0x434, MASKDWORD, 0x06050402);
+		}
+		dm->pre_b_noisy = dm->noisy_decision;
+	}
+}
+
+void phydm_print_rate(void *dm_void, u8 rate, u32 dbg_component)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	u8 rate_idx = rate & 0x7f; /*remove bit7 SGI*/
+	boolean vht_en = phydm_is_vht_rate(dm, rate_idx);
+	u8 b_sgi = (rate & 0x80) >> 7;
+	u8 rate_ss = phydm_rate_to_num_ss(dm, rate_idx);
+	u8 rate_digit = phydm_rate_2_rate_digit(dm, rate_idx);
+
+	PHYDM_DBG_F(dm, dbg_component, "( %s%s%s%s%d%s%s)\n",
+		    (vht_en && (rate_ss == 1)) ? "VHT 1ss " : "",
+		    (vht_en && (rate_ss == 2)) ? "VHT 2ss " : "",
+		    (vht_en && (rate_ss == 3)) ? "VHT 3ss " : "",
+		    (rate_idx >= ODM_RATEMCS0) ? "MCS " : "",
+		    rate_digit,
+		    (b_sgi) ? "-S" : " ",
+		    (rate_idx >= ODM_RATEMCS0) ? "" : "M");
+}
+
+void phydm_print_rate_2_buff(void *dm_void, u8 rate, char *buf, u16 buf_size)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	u8 rate_idx = rate & 0x7f; /*remove bit7 SGI*/
+	boolean vht_en = phydm_is_vht_rate(dm, rate_idx);
+	u8 b_sgi = (rate & 0x80) >> 7;
+	u8 rate_ss = phydm_rate_to_num_ss(dm, rate_idx);
+	u8 rate_digit = phydm_rate_2_rate_digit(dm, rate_idx);
+
+	PHYDM_SNPRINTF(buf, buf_size, "( %s%s%s%s%d%s%s)",
+		       (vht_en && (rate_ss == 1)) ? "VHT 1ss " : "",
+		       (vht_en && (rate_ss == 2)) ? "VHT 2ss " : "",
+		       (vht_en && (rate_ss == 3)) ? "VHT 3ss " : "",
+		       (rate_idx >= ODM_RATEMCS0) ? "MCS " : "",
+		       rate_digit,
+		       (b_sgi) ? "-S" : " ",
+		       (rate_idx >= ODM_RATEMCS0) ? "" : "M");
+}
+
+void phydm_c2h_ra_report_handler(void *dm_void, u8 *cmd_buf, u8 cmd_len)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct ra_table *ra_tab = &dm->dm_ra_table;
+	struct cmn_sta_info *sta = NULL;
+	u8 macid = cmd_buf[1];
+	u8 rate = cmd_buf[0];
+	u8 curr_ra_ratio = 0xff;
+	u8 curr_bw = 0xff;
+	u8 rate_idx = rate & 0x7f; /*remove bit7 SGI*/
+	u8 rate_order;
+
+	#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
+	sta = dm->phydm_sta_info[dm->phydm_macid_table[macid]];
+	#else
+	sta = dm->phydm_sta_info[macid];
+	#endif
+
+	if (cmd_len >= 7) {
+		curr_ra_ratio = cmd_buf[5];
+		curr_bw = cmd_buf[6];
+		PHYDM_DBG(dm, DBG_RA, "RA retry ratio: [%d]:", curr_ra_ratio);
+	}
+
+	if (cmd_buf[3] != 0) {
+		if (cmd_buf[3] == 0xff)
+			PHYDM_DBG(dm, DBG_RA, "FW Level: Fix rate[%d]:", macid);
+		else if (cmd_buf[3] == 1)
+			PHYDM_DBG(dm, DBG_RA, "Try Success[%d]:", macid);
+		else if (cmd_buf[3] == 2)
+			PHYDM_DBG(dm, DBG_RA, "Try Fail & Again[%d]:", macid);
+		else if (cmd_buf[3] == 3)
+			PHYDM_DBG(dm, DBG_RA, "rate Back[%d]:", macid);
+		else if (cmd_buf[3] == 4)
+			PHYDM_DBG(dm, DBG_RA, "start rate by RSSI[%d]:", macid);
+		else if (cmd_buf[3] == 5)
+			PHYDM_DBG(dm, DBG_RA, "Try rate[%d]:", macid);
+	}
+
+	PHYDM_DBG(dm, DBG_RA, "Tx rate Update[%d]:", macid);
+	phydm_print_rate(dm, rate, DBG_RA);
+
+	if (macid >= 128) {
+		u8 gid_index = macid - 128;
+
+		ra_tab->mu1_rate[gid_index] = rate;
+	}
+
+	/*@ra_tab->link_tx_rate[macid] = rate;*/
+
+	if (is_sta_active(sta)) {
+		sta->ra_info.curr_tx_rate = rate;
+		sta->ra_info.curr_tx_bw = (enum channel_width)curr_bw;
+		sta->ra_info.curr_retry_ratio = curr_ra_ratio;
+	}
+
+	/*trigger power training*/
+#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
+
+	rate_order = phydm_rate_order_compute(dm, rate_idx);
+
+	if (dm->is_one_entry_only ||
+	    (rate_order > ra_tab->highest_client_tx_order &&
+	    ra_tab->power_tracking_flag == 1)) {
+		halrf_update_pwr_track(dm, rate_idx);
+		ra_tab->power_tracking_flag = 0;
+	}
+
+#endif
+
+#if 0
+	/*trigger dynamic rate ID*/
+	if (dm->support_ic_type & (ODM_RTL8812 | ODM_RTL8192E))
+		phydm_update_rate_id(dm, rate, macid);
+#endif
+}
+
+void odm_ra_post_action_on_assoc(void *dm_void)
+{
+#if 0
+	struct dm_struct	*dm = (struct dm_struct *)dm_void;
+
+	dm->h2c_rarpt_connect = 1;
+	phydm_rssi_monitor_check(dm);
+	dm->h2c_rarpt_connect = 0;
+#endif
+}
+
+void phydm_modify_RA_PCR_threshold(void *dm_void, u8 ra_ofst_direc,
+				   u8 ra_th_ofst)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct ra_table *ra_tab = &dm->dm_ra_table;
+
+	ra_tab->ra_ofst_direc = ra_ofst_direc;
+	ra_tab->ra_th_ofst = ra_th_ofst;
+	PHYDM_DBG(dm, DBG_RA_MASK, "Set ra_th_offset=(( %s%d ))\n",
+		  ((ra_ofst_direc) ? "+" : "-"), ra_th_ofst);
+}
+
+#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
+
+void phydm_gen_ramask_h2c_AP(
+	void *dm_void,
+	struct rtl8192cd_priv *priv,
+	struct sta_info *entry,
+	u8 rssi_level)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+
+	if (dm->support_ic_type == ODM_RTL8812) {
+		#if (RTL8812A_SUPPORT == 1)
+		UpdateHalRAMask8812(priv, entry, rssi_level);
+		#endif
+	} else if (dm->support_ic_type == ODM_RTL8188E) {
+		#if (RTL8188E_SUPPORT == 1)
+		#ifdef TXREPORT
+		add_RATid(priv, entry);
+		#endif
+		#endif
+	} else {
+		#ifdef CONFIG_WLAN_HAL
+		GET_HAL_INTERFACE(priv)->UpdateHalRAMaskHandler(priv, entry, rssi_level);
+		#endif
+	}
+}
+
+void phydm_update_hal_ra_mask(
+	void *dm_void,
+	u32 wireless_mode,
+	u8 rf_type,
+	u8 bw,
+	u8 mimo_ps_enable,
+	u8 disable_cck_rate,
+	u32 *ratr_bitmap_msb_in,
+	u32 *ratr_bitmap_lsb_in,
+	u8 tx_rate_level)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	u32 ratr_bitmap = *ratr_bitmap_lsb_in;
+	u32 ratr_bitmap_msb = *ratr_bitmap_msb_in;
+
+#if 0
+	/*PHYDM_DBG(dm, DBG_RA_MASK, "phydm_rf_type = (( %x )), rf_type = (( %x ))\n", phydm_rf_type, rf_type);*/
+#endif
+	PHYDM_DBG(dm, DBG_RA_MASK,
+		  "Platfoem original RA Mask = (( 0x %x | %x ))\n",
+		  ratr_bitmap_msb, ratr_bitmap);
+
+	switch (wireless_mode) {
+	case PHYDM_WIRELESS_MODE_B: {
+		ratr_bitmap &= 0x0000000f;
+	} break;
+
+	case PHYDM_WIRELESS_MODE_G: {
+		ratr_bitmap &= 0x00000ff5;
+	} break;
+
+	case PHYDM_WIRELESS_MODE_A: {
+		ratr_bitmap &= 0x00000ff0;
+	} break;
+
+	case PHYDM_WIRELESS_MODE_N_24G:
+	case PHYDM_WIRELESS_MODE_N_5G: {
+		if (mimo_ps_enable)
+			rf_type = RF_1T1R;
+
+		if (rf_type == RF_1T1R) {
+			if (bw == CHANNEL_WIDTH_40)
+				ratr_bitmap &= 0x000ff015;
+			else
+				ratr_bitmap &= 0x000ff005;
+		} else if (rf_type == RF_2T2R || rf_type == RF_2T4R || rf_type == RF_2T3R) {
+			if (bw == CHANNEL_WIDTH_40)
+				ratr_bitmap &= 0x0ffff015;
+			else
+				ratr_bitmap &= 0x0ffff005;
+		} else { /*@3T*/
+
+			ratr_bitmap &= 0xfffff015;
+			ratr_bitmap_msb &= 0xf;
+		}
+	} break;
+
+	case PHYDM_WIRELESS_MODE_AC_24G: {
+		if (rf_type == RF_1T1R) {
+			ratr_bitmap &= 0x003ff015;
+		} else if (rf_type == RF_2T2R || rf_type == RF_2T4R || rf_type == RF_2T3R) {
+			ratr_bitmap &= 0xfffff015;
+		} else { /*@3T*/
+
+			ratr_bitmap &= 0xfffff010;
+			ratr_bitmap_msb &= 0x3ff;
+		}
+
+		if (bw == CHANNEL_WIDTH_20) { /*@AC 20MHz not support MCS9*/
+			ratr_bitmap &= 0x7fdfffff;
+			ratr_bitmap_msb &= 0x1ff;
+		}
+	} break;
+
+	case PHYDM_WIRELESS_MODE_AC_5G: {
+		if (rf_type == RF_1T1R) {
+			ratr_bitmap &= 0x003ff010;
+		} else if (rf_type == RF_2T2R || rf_type == RF_2T4R || rf_type == RF_2T3R) {
+			ratr_bitmap &= 0xfffff010;
+		} else { /*@3T*/
+
+			ratr_bitmap &= 0xfffff010;
+			ratr_bitmap_msb &= 0x3ff;
+		}
+
+		if (bw == CHANNEL_WIDTH_20) { /*@AC 20MHz not support MCS9*/
+			ratr_bitmap &= 0x7fdfffff;
+			ratr_bitmap_msb &= 0x1ff;
+		}
+	} break;
+
+	default:
+		break;
+	}
+
+	if (wireless_mode != PHYDM_WIRELESS_MODE_B) {
+		if (tx_rate_level == 0)
+			ratr_bitmap &= 0xffffffff;
+		else if (tx_rate_level == 1)
+			ratr_bitmap &= 0xfffffff0;
+		else if (tx_rate_level == 2)
+			ratr_bitmap &= 0xffffefe0;
+		else if (tx_rate_level == 3)
+			ratr_bitmap &= 0xffffcfc0;
+		else if (tx_rate_level == 4)
+			ratr_bitmap &= 0xffff8f80;
+		else if (tx_rate_level >= 5)
+			ratr_bitmap &= 0xffff0f00;
+	}
+
+	if (disable_cck_rate)
+		ratr_bitmap &= 0xfffffff0;
+
+	PHYDM_DBG(dm, DBG_RA_MASK,
+		  "wireless_mode= (( 0x%x )), rf_type = (( 0x%x )), BW = (( 0x%x )), MimoPs_en = (( %d )), tx_rate_level= (( 0x%x ))\n",
+		  wireless_mode, rf_type, bw, mimo_ps_enable, tx_rate_level);
+
+#if 0
+	/*PHYDM_DBG(dm, DBG_RA_MASK, "111 Phydm modified RA Mask = (( 0x %x | %x ))\n", ratr_bitmap_msb, ratr_bitmap);*/
+#endif
+
+	*ratr_bitmap_lsb_in = ratr_bitmap;
+	*ratr_bitmap_msb_in = ratr_bitmap_msb;
+	PHYDM_DBG(dm, DBG_RA_MASK,
+		  "Phydm modified RA Mask = (( 0x %x | %x ))\n",
+		  *ratr_bitmap_msb_in, *ratr_bitmap_lsb_in);
+}
+
+#if 0
+void odm_refresh_rate_adaptive_mask_ap(
+	void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct ra_table *ra_tab = &dm->dm_ra_table;
+	struct rtl8192cd_priv *priv = dm->priv;
+	struct aid_obj *aidarray;
+	u32 i;
+	struct sta_info *entry;
+	struct cmn_sta_info *sta;
+	u8 ratr_state_new;
+
+	if (priv->up_time % 2)
+		return;
+
+	for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) {
+		entry = dm->odm_sta_info[i];
+		sta = dm->phydm_sta_info[i];
+
+		if (!is_sta_active(sta))
+			continue;
+
+		#if defined(UNIVERSAL_REPEATER) || defined(MBSSID)
+		aidarray = container_of(entry, struct aid_obj, station);
+		priv = aidarray->priv;
+		#endif
+
+		if (!priv->pmib->dot11StationConfigEntry.autoRate)
+			continue;
+
+		ratr_state_new = phydm_rssi_lv_dec(dm, (u32)sta->rssi_stat.rssi, sta->ra_info.rssi_level);
+
+		if (sta->ra_info.rssi_level != ratr_state_new || ra_tab->up_ramask_cnt >= FORCED_UPDATE_RAMASK_PERIOD) {
+			ra_tab->up_ramask_cnt = 0;
+			PHYDM_PRINT_ADDR(dm, DBG_RA_MASK, "Target AP addr :", sta->mac_addr);
+			PHYDM_DBG(dm, DBG_RA_MASK,
+				  "Update Tx RA Level: ((%x)) -> ((%x)),  RSSI = ((%d))\n",
+				  sta->ra_info.rssi_level, ratr_state_new,
+				  sta->rssi_stat.rssi);
+
+			sta->ra_info.rssi_level = ratr_state_new;
+			phydm_gen_ramask_h2c_AP(dm, priv, entry, sta->ra_info.rssi_level);
+		} else {
+			PHYDM_DBG(dm, DBG_RA_MASK,
+				  "Stay in RA level  = (( %d ))\n\n",
+				  ratr_state_new);
+		}
+	}
+}
+#endif
+#endif
+
+void phydm_rate_adaptive_mask_init(void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct ra_table *ra_t = &dm->dm_ra_table;
+
+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
+	PADAPTER adapter = dm->adapter;
+	PMGNT_INFO mgnt_info = &(adapter->MgntInfo);
+	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)dm->adapter));
+
+	if (mgnt_info->DM_Type == dm_type_by_driver)
+		hal_data->bUseRAMask = true;
+	else
+		hal_data->bUseRAMask = false;
+
+#endif
+
+	ra_t->ldpc_thres = 35;
+	ra_t->up_ramask_cnt = 0;
+	ra_t->up_ramask_cnt_tmp = 0;
+}
+
+void phydm_refresh_rate_adaptive_mask(void *dm_void)
+{
+/*@Will be removed*/
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+
+	phydm_ra_mask_watchdog(dm);
+}
+
+void phydm_show_sta_info(void *dm_void, char input[][16], u32 *_used,
+			 char *output, u32 *_out_len)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct cmn_sta_info *sta = NULL;
+	struct ra_sta_info *ra = NULL;
+#ifdef CONFIG_BEAMFORMING
+	struct bf_cmn_info *bf = NULL;
+#endif
+	char help[] = "-h";
+	u32 var[10] = {0};
+	u32 used = *_used;
+	u32 out_len = *_out_len;
+	u32 i, sta_idx_start, sta_idx_end;
+	u8 tatal_sta_num = 0;
+
+	PHYDM_SSCANF(input[1], DCMD_DECIMAL, &var[0]);
+
+	if ((strcmp(input[1], help) == 0)) {
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "All STA: {1}\n");
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "STA[macid]: {2} {macid}\n");
+		return;
+	} else if (var[0] == 1) {
+		sta_idx_start = 0;
+		sta_idx_end = ODM_ASSOCIATE_ENTRY_NUM;
+	} else if (var[0] == 2) {
+		sta_idx_start = var[1];
+		sta_idx_end = var[1];
+	} else {
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "Warning input value!\n");
+		return;
+	}
+
+	for (i = sta_idx_start; i < sta_idx_end; i++) {
+		sta = dm->phydm_sta_info[i];
+
+		if (!is_sta_active(sta))
+			continue;
+
+		ra = &sta->ra_info;
+		#ifdef CONFIG_BEAMFORMING
+		bf = &sta->bf_info;
+		#endif
+
+		tatal_sta_num++;
+
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "==[sta_idx: %d][MACID: %d]============>\n", i,
+			 sta->mac_id);
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "AID:%d\n", sta->aid);
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "ADDR:%x-%x-%x-%x-%x-%x\n", sta->mac_addr[5],
+			 sta->mac_addr[4], sta->mac_addr[3], sta->mac_addr[2],
+			 sta->mac_addr[1], sta->mac_addr[0]);
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "DM_ctrl:0x%x\n", sta->dm_ctrl);
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "BW:%d, MIMO_Type:0x%x\n", sta->bw_mode,
+			 sta->mimo_type);
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "STBC_en:%d, LDPC_en=%d\n", sta->stbc_en,
+			 sta->ldpc_en);
+
+		/*@[RSSI Info]*/
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "RSSI{All, OFDM, CCK}={%d, %d, %d}\n",
+			 sta->rssi_stat.rssi, sta->rssi_stat.rssi_ofdm,
+			 sta->rssi_stat.rssi_cck);
+
+		/*@[RA Info]*/
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "Rate_ID:%d, RSSI_LV:%d, ra_bw:%d, SGI_en:%d\n",
+			 ra->rate_id, ra->rssi_level, ra->ra_bw_mode,
+			 ra->is_support_sgi);
+
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "VHT_en:%d, Wireless_set=0x%x, sm_ps=%d\n",
+			 ra->is_vht_enable, sta->support_wireless_set,
+			 sta->sm_ps);
+
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "Dis{RA, PT}={%d, %d}, TxRx:%d, Noisy:%d\n",
+			 ra->disable_ra, ra->disable_pt, ra->txrx_state,
+			 ra->is_noisy);
+
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "TX{Rate, BW}={0x%x, %d}, RTY:%d\n", ra->curr_tx_rate,
+			 ra->curr_tx_bw, ra->curr_retry_ratio);
+
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "RA_Mask:0x%llx\n", ra->ramask);
+
+		/*@[TP]*/
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "TP{TX,RX}={%d, %d}\n", sta->tx_moving_average_tp,
+			 sta->rx_moving_average_tp);
+
+#ifdef CONFIG_BEAMFORMING
+		/*@[Beamforming]*/
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "BF CAP{HT,VHT}={0x%x, 0x%x}\n", bf->ht_beamform_cap,
+			 bf->vht_beamform_cap);
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "BF {p_aid,g_id}={0x%x, 0x%x}\n\n", bf->p_aid,
+			 bf->g_id);
+#endif
+	}
+
+	if (tatal_sta_num == 0) {
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "No Linked STA\n");
+	}
+
+	*_used = used;
+	*_out_len = out_len;
+}
+
+u8 phydm_get_tx_stream_num(void *dm_void, enum rf_type type)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	u8 tx_num = 1;
+
+	if (type == RF_1T1R || type == RF_1T2R)
+		tx_num = 1;
+	else if (type == RF_2T2R || type == RF_2T3R || type == RF_2T4R)
+		tx_num = 2;
+	else if (type == RF_3T3R || type == RF_3T4R)
+		tx_num = 3;
+	else if (type == RF_4T4R)
+		tx_num = 4;
+	else
+		PHYDM_DBG(dm, DBG_RA, "[Warrning] no mimo_type is found\n");
+
+	return tx_num;
+}
+
+u64 phydm_get_bb_mod_ra_mask(void *dm_void, u8 sta_idx)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct cmn_sta_info *sta = dm->phydm_sta_info[sta_idx];
+	struct ra_sta_info *ra = NULL;
+	enum channel_width bw = 0;
+	enum wireless_set wrls_mode = 0;
+	u8 tx_stream_num = 1;
+	u8 rssi_lv = 0;
+	u64 ra_mask_bitmap = 0;
+
+	if (is_sta_active(sta)) {
+		ra = &sta->ra_info;
+		bw = ra->ra_bw_mode;
+		wrls_mode = sta->support_wireless_set;
+		tx_stream_num = phydm_get_tx_stream_num(dm, sta->mimo_type);
+		rssi_lv = ra->rssi_level;
+		ra_mask_bitmap = ra->ramask;
+	} else {
+		PHYDM_DBG(dm, DBG_RA, "[Warning] %s invalid STA\n", __func__);
+		return 0;
+	}
+
+	PHYDM_DBG(dm, DBG_RA, "macid=%d ori_RA_Mask= 0x%llx\n", sta->mac_id,
+		  ra_mask_bitmap);
+	PHYDM_DBG(dm, DBG_RA,
+		  "wireless_mode=0x%x, tx_ss=%d, BW=%d, MimoPs=%d, rssi_lv=%d\n",
+		  wrls_mode, tx_stream_num, bw, sta->sm_ps, rssi_lv);
+
+	if (sta->sm_ps == SM_PS_STATIC) /*@mimo_ps_enable*/
+		tx_stream_num = 1;
+
+	/*@[Modify RA Mask by Wireless Mode]*/
+
+	if (wrls_mode == WIRELESS_CCK) { /*@B mode*/
+		ra_mask_bitmap &= 0x0000000f;
+	} else if (wrls_mode == WIRELESS_OFDM) { /*@G mode*/
+		ra_mask_bitmap &= 0x00000ff0;
+	} else if (wrls_mode == (WIRELESS_CCK | WIRELESS_OFDM)) { /*@BG mode*/
+		ra_mask_bitmap &= 0x00000ff5;
+	} else if (wrls_mode == (WIRELESS_CCK | WIRELESS_OFDM | WIRELESS_HT)) {
+		/*N_2G*/
+		if (tx_stream_num == 1) {
+			if (bw == CHANNEL_WIDTH_40)
+				ra_mask_bitmap &= 0x000ff015;
+			else
+				ra_mask_bitmap &= 0x000ff005;
+		} else if (tx_stream_num == 2) {
+			if (bw == CHANNEL_WIDTH_40)
+				ra_mask_bitmap &= 0x0ffff015;
+			else
+				ra_mask_bitmap &= 0x0ffff005;
+		} else if (tx_stream_num == 3) {
+			ra_mask_bitmap &= 0xffffff015;
+		} else {
+			ra_mask_bitmap &= 0xffffffff015;
+		}
+	} else if (wrls_mode == (WIRELESS_OFDM | WIRELESS_HT)) { /*N_5G*/
+
+		if (tx_stream_num == 1) {
+			if (bw == CHANNEL_WIDTH_40)
+				ra_mask_bitmap &= 0x000ff030;
+			else
+				ra_mask_bitmap &= 0x000ff010;
+		} else if (tx_stream_num == 2) {
+			if (bw == CHANNEL_WIDTH_40)
+				ra_mask_bitmap &= 0x0ffff030;
+			else
+				ra_mask_bitmap &= 0x0ffff010;
+		} else if (tx_stream_num == 3) {
+			ra_mask_bitmap &= 0xffffff010;
+		} else {
+			ra_mask_bitmap &= 0xffffffff010;
+		}
+	} else if (wrls_mode == (WIRELESS_CCK | WIRELESS_OFDM | WIRELESS_VHT)) {
+		/*@AC_2G*/
+		if (tx_stream_num == 1)
+			ra_mask_bitmap &= 0x003ff015;
+		else if (tx_stream_num == 2)
+			ra_mask_bitmap &= 0xfffff015;
+		else if (tx_stream_num == 3)
+			ra_mask_bitmap &= 0x3fffffff015;
+		else /*@AC_4SS 2G*/
+			ra_mask_bitmap &= 0x000ffffffffff015;
+		if (bw == CHANNEL_WIDTH_20) {
+		/* @AC 20MHz doesn't support MCS9 except 3SS & 6SS*/
+			ra_mask_bitmap &= 0x0007ffff7fdff015;
+		} else if (bw == CHANNEL_WIDTH_80) {
+		/* @AC 80MHz doesn't support 3SS MCS6*/
+			ra_mask_bitmap &= 0x000fffbffffff015;
+		}
+	} else if (wrls_mode == (WIRELESS_OFDM | WIRELESS_VHT)) { /*@AC_5G*/
+
+		if (tx_stream_num == 1)
+			ra_mask_bitmap &= 0x003ff010;
+		else if (tx_stream_num == 2)
+			ra_mask_bitmap &= 0xfffff010;
+		else if (tx_stream_num == 3)
+			ra_mask_bitmap &= 0x3fffffff010;
+		else /*@AC_4SS 5G*/
+			ra_mask_bitmap &= 0x000ffffffffff010;
+
+		if (bw == CHANNEL_WIDTH_20) {
+		/* @AC 20MHz doesn't support MCS9 except 3SS & 6SS*/
+			ra_mask_bitmap &= 0x0007ffff7fdff010;
+		} else if (bw == CHANNEL_WIDTH_80) {
+		/* @AC 80MHz doesn't support 3SS MCS6*/
+			ra_mask_bitmap &= 0x000fffbffffff010;
+		}
+	} else {
+		PHYDM_DBG(dm, DBG_RA, "[Warrning] RA mask is Not found\n");
+	}
+
+	PHYDM_DBG(dm, DBG_RA, "Mod by mode=0x%llx\n", ra_mask_bitmap);
+
+	/*@[Modify RA Mask by RSSI level]*/
+	if (wrls_mode != WIRELESS_CCK) {
+		if (rssi_lv == 0)
+			ra_mask_bitmap &= 0xffffffffffffffff;
+		else if (rssi_lv == 1)
+			ra_mask_bitmap &= 0xfffffffffffffff0;
+		else if (rssi_lv == 2)
+			ra_mask_bitmap &= 0xffffffffffffefe0;
+		else if (rssi_lv == 3)
+			ra_mask_bitmap &= 0xffffffffffffcfc0;
+		else if (rssi_lv == 4)
+			ra_mask_bitmap &= 0xffffffffffff8f80;
+		else if (rssi_lv >= 5)
+			ra_mask_bitmap &= 0xffffffffffff0f00;
+	}
+	PHYDM_DBG(dm, DBG_RA, "Mod by RSSI=0x%llx\n", ra_mask_bitmap);
+
+	return ra_mask_bitmap;
+}
+
+u8 phydm_get_rate_from_rssi_lv(void *dm_void, u8 sta_idx)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct cmn_sta_info *sta = dm->phydm_sta_info[sta_idx];
+	struct ra_sta_info *ra = NULL;
+	enum wireless_set wrls_set = 0;
+	u8 rssi_lv = 0;
+	u8 rate_idx = 0;
+	u8 rate_ofst = 0;
+
+	if (is_sta_active(sta)) {
+		ra = &sta->ra_info;
+		wrls_set = sta->support_wireless_set;
+		rssi_lv = ra->rssi_level;
+	} else {
+		pr_debug("[Warning] %s: invalid STA\n", __func__);
+		return 0;
+	}
+
+	PHYDM_DBG(dm, DBG_RA, "[%s]macid=%d, wireless_set=0x%x, rssi_lv=%d\n",
+		  __func__, sta->mac_id, wrls_set, rssi_lv);
+
+	rate_ofst = (rssi_lv <= 1) ? 0 : (rssi_lv - 1);
+
+	if (wrls_set & WIRELESS_VHT) {
+		rate_idx = ODM_RATEVHTSS1MCS0 + rate_ofst;
+	} else if (wrls_set & WIRELESS_HT) {
+		rate_idx = ODM_RATEMCS0 + rate_ofst;
+	} else if (wrls_set & WIRELESS_OFDM) {
+		rate_idx = ODM_RATE6M + rate_ofst;
+	} else {
+		rate_idx = ODM_RATE1M + rate_ofst;
+
+		if (rate_idx > ODM_RATE11M)
+			rate_idx = ODM_RATE11M;
+	}
+	return rate_idx;
+}
+
+u8 phydm_get_rate_id(void *dm_void, u8 sta_idx)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct cmn_sta_info *sta = dm->phydm_sta_info[sta_idx];
+	struct ra_sta_info *ra = NULL;
+	enum channel_width bw = 0;
+	enum wireless_set wrls_mode = 0;
+	u8 tx_stream_num = 1;
+	u8 rate_id_idx = PHYDM_BGN_20M_1SS;
+
+	if (is_sta_active(sta)) {
+		ra = &sta->ra_info;
+		bw = ra->ra_bw_mode;
+		wrls_mode = sta->support_wireless_set;
+		tx_stream_num = phydm_get_tx_stream_num(dm, sta->mimo_type);
+
+	} else {
+		PHYDM_DBG(dm, DBG_RA, "[Warning] %s: invalid STA\n", __func__);
+		return 0;
+	}
+
+	PHYDM_DBG(dm, DBG_RA, "macid=%d,wireless_set=0x%x,tx_SS_num=%d,BW=%d\n",
+		  sta->mac_id, wrls_mode, tx_stream_num, bw);
+
+	if (wrls_mode == WIRELESS_CCK) {
+	/*@B mode*/
+		rate_id_idx = PHYDM_B_20M;
+	} else if (wrls_mode == WIRELESS_OFDM) {
+	/*@G mode*/
+		rate_id_idx = PHYDM_G;
+	} else if (wrls_mode == (WIRELESS_CCK | WIRELESS_OFDM)) {
+	/*@BG mode*/
+		rate_id_idx = PHYDM_BG;
+	} else if (wrls_mode == (WIRELESS_OFDM | WIRELESS_HT)) {
+	/*@GN mode*/
+		if (tx_stream_num == 1)
+			rate_id_idx = PHYDM_GN_N1SS;
+		else if (tx_stream_num == 2)
+			rate_id_idx = PHYDM_GN_N2SS;
+		else if (tx_stream_num == 3)
+			rate_id_idx = PHYDM_ARFR5_N_3SS;
+	} else if (wrls_mode == (WIRELESS_CCK | WIRELESS_OFDM | WIRELESS_HT)) {
+	 /*@BGN mode*/
+		if (bw == CHANNEL_WIDTH_40) {
+			if (tx_stream_num == 1)
+				rate_id_idx = PHYDM_BGN_40M_1SS;
+			else if (tx_stream_num == 2)
+				rate_id_idx = PHYDM_BGN_40M_2SS;
+			else if (tx_stream_num == 3)
+				rate_id_idx = PHYDM_ARFR5_N_3SS;
+			else if (tx_stream_num == 4)
+				rate_id_idx = PHYDM_ARFR7_N_4SS;
+
+		} else {
+			if (tx_stream_num == 1)
+				rate_id_idx = PHYDM_BGN_20M_1SS;
+			else if (tx_stream_num == 2)
+				rate_id_idx = PHYDM_BGN_20M_2SS;
+			else if (tx_stream_num == 3)
+				rate_id_idx = PHYDM_ARFR5_N_3SS;
+			else if (tx_stream_num == 4)
+				rate_id_idx = PHYDM_ARFR7_N_4SS;
+		}
+	} else if (wrls_mode == (WIRELESS_OFDM | WIRELESS_VHT)) {
+	/*@AC mode*/
+		if (tx_stream_num == 1)
+			rate_id_idx = PHYDM_ARFR1_AC_1SS;
+		else if (tx_stream_num == 2)
+			rate_id_idx = PHYDM_ARFR0_AC_2SS;
+		else if (tx_stream_num == 3)
+			rate_id_idx = PHYDM_ARFR4_AC_3SS;
+		else if (tx_stream_num == 4)
+			rate_id_idx = PHYDM_ARFR6_AC_4SS;
+	} else if (wrls_mode == (WIRELESS_CCK | WIRELESS_OFDM | WIRELESS_VHT)) {
+	/*@AC 2.4G mode*/
+		if (bw >= CHANNEL_WIDTH_80) {
+			if (tx_stream_num == 1)
+				rate_id_idx = PHYDM_ARFR1_AC_1SS;
+			else if (tx_stream_num == 2)
+				rate_id_idx = PHYDM_ARFR0_AC_2SS;
+			else if (tx_stream_num == 3)
+				rate_id_idx = PHYDM_ARFR4_AC_3SS;
+			else if (tx_stream_num == 4)
+				rate_id_idx = PHYDM_ARFR6_AC_4SS;
+		} else {
+			if (tx_stream_num == 1)
+				rate_id_idx = PHYDM_ARFR2_AC_2G_1SS;
+			else if (tx_stream_num == 2)
+				rate_id_idx = PHYDM_ARFR3_AC_2G_2SS;
+			else if (tx_stream_num == 3)
+				rate_id_idx = PHYDM_ARFR4_AC_3SS;
+			else if (tx_stream_num == 4)
+				rate_id_idx = PHYDM_ARFR6_AC_4SS;
+		}
+	} else {
+		PHYDM_DBG(dm, DBG_RA, "[Warrning] No rate_id is found\n");
+		rate_id_idx = 0;
+	}
+
+	PHYDM_DBG(dm, DBG_RA, "Rate_ID=((0x%x))\n", rate_id_idx);
+
+	return rate_id_idx;
+}
+
+void phydm_ra_h2c(void *dm_void, u8 sta_idx, u8 dis_ra, u8 dis_pt,
+		  u8 no_update_bw, u8 init_ra_lv, u64 ra_mask)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct cmn_sta_info *sta = dm->phydm_sta_info[sta_idx];
+	struct ra_sta_info *ra = NULL;
+	u8 h2c_val[H2C_MAX_LENGTH] = {0};
+
+	if (is_sta_active(sta)) {
+		ra = &sta->ra_info;
+	} else {
+		PHYDM_DBG(dm, DBG_RA, "[Warning] %s invalid sta_info\n",
+			  __func__);
+		return;
+	}
+
+	PHYDM_DBG(dm, DBG_RA, "%s ======>\n", __func__);
+	PHYDM_DBG(dm, DBG_RA, "MACID=%d\n", sta->mac_id);
+
+	if (dm->is_disable_power_training)
+		dis_pt = true;
+	else if (!dm->is_disable_power_training)
+		dis_pt = false;
+
+	h2c_val[0] = sta->mac_id;
+	h2c_val[1] = (ra->rate_id & 0x1f) | ((init_ra_lv & 0x3) << 5) |
+		     (ra->is_support_sgi << 7);
+	h2c_val[2] = (u8)((ra->ra_bw_mode) | (((sta->ldpc_en) ? 1 : 0) << 2) |
+			  ((no_update_bw & 0x1) << 3) |
+			  (ra->is_vht_enable << 4) |
+			  ((dis_pt & 0x1) << 6) | ((dis_ra & 0x1) << 7));
+
+	h2c_val[3] = (u8)(ra_mask & 0xff);
+	h2c_val[4] = (u8)((ra_mask & 0xff00) >> 8);
+	h2c_val[5] = (u8)((ra_mask & 0xff0000) >> 16);
+	h2c_val[6] = (u8)((ra_mask & 0xff000000) >> 24);
+
+	PHYDM_DBG(dm, DBG_RA, "PHYDM h2c[0x40]=0x%x %x %x %x %x %x %x\n",
+		  h2c_val[6], h2c_val[5], h2c_val[4], h2c_val[3], h2c_val[2],
+		  h2c_val[1], h2c_val[0]);
+
+	odm_fill_h2c_cmd(dm, PHYDM_H2C_RA_MASK, H2C_MAX_LENGTH, h2c_val);
+
+	#if (defined(PHYDM_COMPILE_ABOVE_3SS))
+	if (dm->support_ic_type & (PHYDM_IC_ABOVE_3SS)) {
+		h2c_val[3] = (u8)((ra_mask >> 32) & 0x000000ff);
+		h2c_val[4] = (u8)(((ra_mask >> 32) & 0x0000ff00) >> 8);
+		h2c_val[5] = (u8)(((ra_mask >> 32) & 0x00ff0000) >> 16);
+		h2c_val[6] = (u8)(((ra_mask >> 32) & 0xff000000) >> 24);
+
+		PHYDM_DBG(dm, DBG_RA, "h2c[0x46]=0x%x %x %x %x %x %x %x\n",
+			  h2c_val[6], h2c_val[5], h2c_val[4], h2c_val[3],
+			  h2c_val[2], h2c_val[1], h2c_val[0]);
+
+		odm_fill_h2c_cmd(dm, PHYDM_RA_MASK_ABOVE_3SS, 5, h2c_val);
+	}
+	#endif
+}
+
+void phydm_ra_registed(void *dm_void, u8 sta_idx,
+		       /*@index of sta_info array, not MACID*/
+		       u8 rssi_from_assoc)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct ra_table *ra_t = &dm->dm_ra_table;
+	struct cmn_sta_info *sta = dm->phydm_sta_info[sta_idx];
+	struct ra_sta_info *ra = NULL;
+	u8 init_ra_lv = 0;
+	u64 ra_mask = 0;
+	/*@SD7 STA_idx != macid*/
+	/*@SD4,8 STA_idx == macid, */
+
+	PHYDM_DBG(dm, DBG_RA_MASK, "%s ======>\n", __func__);
+
+	if (is_sta_active(sta)) {
+		ra = &sta->ra_info;
+		PHYDM_DBG(dm, DBG_RA_MASK, "sta_idx=%d, macid=%d\n", sta_idx,
+			  sta->mac_id);
+	} else {
+		PHYDM_DBG(dm, DBG_RA_MASK, "[Warning] %s invalid STA\n",
+			  __func__);
+		PHYDM_DBG(dm, DBG_RA_MASK, "sta_idx=%d\n", sta_idx);
+		return;
+	}
+
+	#if (RTL8188E_SUPPORT == 1) && (RATE_ADAPTIVE_SUPPORT == 1)
+	if (dm->support_ic_type == ODM_RTL8188E)
+		ra->rate_id = phydm_get_rate_id_88e(dm, sta_idx);
+	else
+	#endif
+	{
+		ra->rate_id = phydm_get_rate_id(dm, sta_idx);
+	}
+
+	ra_mask = phydm_get_bb_mod_ra_mask(dm, sta_idx);
+
+	PHYDM_DBG(dm, DBG_RA_MASK, "rssi_assoc=%d\n", rssi_from_assoc);
+
+	if (rssi_from_assoc > 40)
+		init_ra_lv = 1;
+	else if (rssi_from_assoc > 20)
+		init_ra_lv = 2;
+	else if (rssi_from_assoc > 1)
+		init_ra_lv = 3;
+	else
+		init_ra_lv = 0;
+
+	if (ra_t->record_ra_info)
+		ra_t->record_ra_info(dm, sta_idx, sta, ra_mask);
+
+	#if (RTL8188E_SUPPORT == 1) && (RATE_ADAPTIVE_SUPPORT == 1)
+	if (dm->support_ic_type == ODM_RTL8188E)
+		/*@Driver RA*/
+		phydm_ra_update_8188e(dm, sta_idx, ra->rate_id,
+				      (u32)ra_mask, ra->is_support_sgi);
+	else
+	#endif
+	{
+		/*@FW RA*/
+		phydm_ra_h2c(dm, sta_idx, ra->disable_ra, ra->disable_pt, 0,
+			     init_ra_lv, ra_mask);
+	}
+}
+
+void phydm_ra_offline(void *dm_void, u8 sta_idx)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct ra_table *ra_t = &dm->dm_ra_table;
+	struct cmn_sta_info *sta = dm->phydm_sta_info[sta_idx];
+	struct ra_sta_info *ra = NULL;
+
+	if (is_sta_active(sta)) {
+		ra = &sta->ra_info;
+	} else {
+		PHYDM_DBG(dm, DBG_RA, "[Warning] %s invalid STA\n", __func__);
+		return;
+	}
+
+	PHYDM_DBG(dm, DBG_RA, "%s ======>\n", __func__);
+	PHYDM_DBG(dm, DBG_RA, "MACID=%d\n", sta->mac_id);
+
+	odm_memory_set(dm, &ra->rate_id, 0, sizeof(struct ra_sta_info));
+	ra->disable_ra = 1;
+	ra->disable_pt = 1;
+
+	if (ra_t->record_ra_info)
+		ra_t->record_ra_info(dm, sta->mac_id, sta, 0);
+
+	if (dm->support_ic_type != ODM_RTL8188E)
+		phydm_ra_h2c(dm, sta->mac_id, 1, 1, 0, 0, 0);
+}
+
+void phydm_ra_mask_watchdog(void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct ra_table *ra_t = &dm->dm_ra_table;
+	struct cmn_sta_info *sta = NULL;
+	struct ra_sta_info *ra = NULL;
+	u8 sta_idx;
+	u64 ra_mask;
+	u8 rssi_lv_new;
+	u8 rssi = 0;
+
+	if (!(dm->support_ability & ODM_BB_RA_MASK))
+		return;
+
+	if (!dm->is_linked || (dm->phydm_sys_up_time % 2) == 1)
+		return;
+
+	PHYDM_DBG(dm, DBG_RA_MASK, "%s ======>\n", __func__);
+
+	ra_t->up_ramask_cnt++;
+
+	for (sta_idx = 0; sta_idx < ODM_ASSOCIATE_ENTRY_NUM; sta_idx++) {
+		sta = dm->phydm_sta_info[sta_idx];
+
+		if (!is_sta_active(sta))
+			continue;
+
+		ra = &sta->ra_info;
+
+		if (ra->disable_ra)
+			continue;
+
+		PHYDM_DBG(dm, DBG_RA_MASK, "sta_idx=%d, macid=%d\n", sta_idx,
+			  sta->mac_id);
+
+		rssi = (u8)(sta->rssi_stat.rssi);
+
+		/*@to be modified*/
+		#if ((RTL8812A_SUPPORT == 1) || (RTL8821A_SUPPORT == 1))
+		if (dm->support_ic_type == ODM_RTL8812 ||
+			(dm->support_ic_type == ODM_RTL8821 &&
+			 dm->cut_version == ODM_CUT_A)
+			) {
+			if (rssi < ra_t->ldpc_thres) {
+				/*@LDPC TX enable*/
+				#if (DM_ODM_SUPPORT_TYPE == ODM_CE)
+				set_ra_ldpc_8812(sta, true);
+				#elif (DM_ODM_SUPPORT_TYPE == ODM_WIN)
+				MgntSet_TX_LDPC(sta->mac_id, true);
+				#elif (DM_ODM_SUPPORT_TYPE == ODM_AP)
+				/*to be added*/
+				#endif
+				PHYDM_DBG(dm, DBG_RA_MASK,
+					  "RSSI=%d, ldpc_en =TRUE\n", rssi);
+
+			} else if (rssi > (ra_t->ldpc_thres + 3)) {
+				/*@LDPC TX disable*/
+				#if (DM_ODM_SUPPORT_TYPE == ODM_CE)
+				set_ra_ldpc_8812(sta, false);
+				#elif (DM_ODM_SUPPORT_TYPE == ODM_WIN)
+				MgntSet_TX_LDPC(sta->mac_id, false);
+				#elif (DM_ODM_SUPPORT_TYPE == ODM_AP)
+				/*to be added*/
+				#endif
+				PHYDM_DBG(dm, DBG_RA_MASK,
+					  "RSSI=%d, ldpc_en =FALSE\n", rssi);
+			}
+		}
+		#endif
+
+		rssi_lv_new = phydm_rssi_lv_dec(dm, (u32)rssi, ra->rssi_level);
+
+		if (ra->rssi_level != rssi_lv_new ||
+		    ra_t->up_ramask_cnt >= FORCED_UPDATE_RAMASK_PERIOD) {
+			PHYDM_DBG(dm, DBG_RA_MASK, "RSSI LV:((%d))->((%d))\n",
+				  ra->rssi_level, rssi_lv_new);
+
+			ra->rssi_level = rssi_lv_new;
+			ra_t->up_ramask_cnt = 0;
+
+			ra_mask = phydm_get_bb_mod_ra_mask(dm, sta_idx);
+
+			if (ra_t->record_ra_info)
+				ra_t->record_ra_info(dm, sta_idx, sta, ra_mask);
+
+			#if (RTL8188E_SUPPORT) && (RATE_ADAPTIVE_SUPPORT)
+			if (dm->support_ic_type == ODM_RTL8188E)
+				/*@Driver RA*/
+				phydm_ra_update_8188e(dm, sta_idx, ra->rate_id,
+						      (u32)ra_mask,
+						      ra->is_support_sgi);
+			else
+			#endif
+			{
+				/*@FW RA*/
+				phydm_ra_h2c(dm, sta_idx, ra->disable_ra,
+					     ra->disable_pt, 1, 0, ra_mask);
+			}
+		}
+	}
+}
+
+u8 phydm_vht_en_mapping(void *dm_void, u32 wireless_mode)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	u8 vht_en_out = 0;
+
+	if (wireless_mode == PHYDM_WIRELESS_MODE_AC_5G ||
+	    wireless_mode == PHYDM_WIRELESS_MODE_AC_24G ||
+	    wireless_mode == PHYDM_WIRELESS_MODE_AC_ONLY)
+		vht_en_out = 1;
+
+	PHYDM_DBG(dm, DBG_RA, "wireless_mode= (( 0x%x )), VHT_EN= (( %d ))\n",
+		  wireless_mode, vht_en_out);
+	return vht_en_out;
+}
+
+u8 phydm_rftype2rateid_2g_n20(void *dm_void, u8 rf_type)
+{
+	u8 rate_id_idx = 0;
+
+	if (rf_type == RF_1T1R)
+		rate_id_idx = PHYDM_BGN_20M_1SS;
+	else if (rf_type == RF_2T2R)
+		rate_id_idx = PHYDM_BGN_20M_2SS;
+	else if (rf_type == RF_3T3R)
+		rate_id_idx = PHYDM_ARFR5_N_3SS;
+	else
+		rate_id_idx = PHYDM_ARFR7_N_4SS;
+	return rate_id_idx;
+}
+
+u8 phydm_rftype2rateid_2g_n40(void *dm_void, u8 rf_type)
+{
+	u8 rate_id_idx = 0;
+
+	if (rf_type == RF_1T1R)
+		rate_id_idx = PHYDM_BGN_40M_1SS;
+	else if (rf_type == RF_2T2R)
+		rate_id_idx = PHYDM_BGN_40M_2SS;
+	else if (rf_type == RF_3T3R)
+		rate_id_idx = PHYDM_ARFR5_N_3SS;
+	else
+		rate_id_idx = PHYDM_ARFR7_N_4SS;
+	return rate_id_idx;
+}
+
+u8 phydm_rftype2rateid_5g_n(void *dm_void, u8 rf_type)
+{
+	u8 rate_id_idx = 0;
+
+	if (rf_type == RF_1T1R)
+		rate_id_idx = PHYDM_GN_N1SS;
+	else if (rf_type == RF_2T2R)
+		rate_id_idx = PHYDM_GN_N2SS;
+	else if (rf_type == RF_3T3R)
+		rate_id_idx = PHYDM_ARFR5_N_3SS;
+	else
+		rate_id_idx = PHYDM_ARFR7_N_4SS;
+	return rate_id_idx;
+}
+
+u8 phydm_rftype2rateid_ac80(void *dm_void, u8 rf_type)
+{
+	u8 rate_id_idx = 0;
+
+	if (rf_type == RF_1T1R)
+		rate_id_idx = PHYDM_ARFR1_AC_1SS;
+	else if (rf_type == RF_2T2R)
+		rate_id_idx = PHYDM_ARFR0_AC_2SS;
+	else if (rf_type == RF_3T3R)
+		rate_id_idx = PHYDM_ARFR4_AC_3SS;
+	else
+		rate_id_idx = PHYDM_ARFR6_AC_4SS;
+	return rate_id_idx;
+}
+
+u8 phydm_rftype2rateid_ac40(void *dm_void, u8 rf_type)
+{
+	u8 rate_id_idx = 0;
+
+	if (rf_type == RF_1T1R)
+		rate_id_idx = PHYDM_ARFR2_AC_2G_1SS;
+	else if (rf_type == RF_2T2R)
+		rate_id_idx = PHYDM_ARFR3_AC_2G_2SS;
+	else if (rf_type == RF_3T3R)
+		rate_id_idx = PHYDM_ARFR4_AC_3SS;
+	else
+		rate_id_idx = PHYDM_ARFR6_AC_4SS;
+	return rate_id_idx;
+}
+
+u8 phydm_rate_id_mapping(void *dm_void, u32 wireless_mode, u8 rf_type, u8 bw)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	u8 rate_id_idx = 0;
+
+	PHYDM_DBG(dm, DBG_RA,
+		  "wireless_mode= (( 0x%x )), rf_type = (( 0x%x )), BW = (( 0x%x ))\n",
+		  wireless_mode, rf_type, bw);
+
+	switch (wireless_mode) {
+	case PHYDM_WIRELESS_MODE_N_24G:
+		if (bw == CHANNEL_WIDTH_40)
+			rate_id_idx = phydm_rftype2rateid_2g_n40(dm, rf_type);
+		else
+			rate_id_idx = phydm_rftype2rateid_2g_n20(dm, rf_type);
+		break;
+
+	case PHYDM_WIRELESS_MODE_N_5G:
+		rate_id_idx = phydm_rftype2rateid_5g_n(dm, rf_type);
+		break;
+
+	case PHYDM_WIRELESS_MODE_G:
+		rate_id_idx = PHYDM_BG;
+		break;
+
+	case PHYDM_WIRELESS_MODE_A:
+		rate_id_idx = PHYDM_G;
+		break;
+
+	case PHYDM_WIRELESS_MODE_B:
+		rate_id_idx = PHYDM_B_20M;
+		break;
+
+	case PHYDM_WIRELESS_MODE_AC_5G:
+	case PHYDM_WIRELESS_MODE_AC_ONLY:
+		rate_id_idx = phydm_rftype2rateid_ac80(dm, rf_type);
+		break;
+
+	case PHYDM_WIRELESS_MODE_AC_24G:
+/*@Becareful to set "Lowest rate" while using PHYDM_ARFR4_AC_3SS in 2.4G/5G*/
+		if (bw >= CHANNEL_WIDTH_80)
+			rate_id_idx = phydm_rftype2rateid_ac80(dm, rf_type);
+		else
+			rate_id_idx = phydm_rftype2rateid_ac40(dm, rf_type);
+		break;
+
+	default:
+		rate_id_idx = 0;
+		break;
+	}
+
+	PHYDM_DBG(dm, DBG_RA, "RA rate ID = (( 0x%x ))\n", rate_id_idx);
+
+	return rate_id_idx;
+}
+
+u8 phydm_rssi_lv_dec(void *dm_void, u32 rssi, u8 ratr_state)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	/*@MCS0 ~ MCS4 , VHT1SS MCS0 ~ MCS4 , G 6M~24M*/
+	u8 rssi_lv_t[RA_FLOOR_TABLE_SIZE] = {20, 34, 38, 42, 46, 50, 100};
+	u8 new_rssi_lv = 0;
+	u8 i;
+
+	PHYDM_DBG(dm, DBG_RA_MASK,
+		  "curr RA level=(%d), Table_ori=[%d, %d, %d, %d, %d, %d]\n",
+		  ratr_state, rssi_lv_t[0], rssi_lv_t[1], rssi_lv_t[2],
+		  rssi_lv_t[3], rssi_lv_t[4], rssi_lv_t[5]);
+
+	for (i = 0; i < RA_FLOOR_TABLE_SIZE; i++) {
+		if (i >= (ratr_state))
+			rssi_lv_t[i] += RA_FLOOR_UP_GAP;
+	}
+
+	PHYDM_DBG(dm, DBG_RA_MASK,
+		  "RSSI=(%d), Table_mod=[%d, %d, %d, %d, %d, %d]\n", rssi,
+		  rssi_lv_t[0], rssi_lv_t[1], rssi_lv_t[2], rssi_lv_t[3],
+		  rssi_lv_t[4], rssi_lv_t[5]);
+
+	for (i = 0; i < RA_FLOOR_TABLE_SIZE; i++) {
+		if (rssi < rssi_lv_t[i]) {
+			new_rssi_lv = i;
+			break;
+		}
+	}
+	return new_rssi_lv;
+}
+
+u8 phydm_rate_order_compute(void *dm_void, u8 rate_idx)
+{
+	u8 rate_order = 0;
+
+	if (rate_idx >= ODM_RATEVHTSS4MCS0)
+		rate_idx -= ODM_RATEVHTSS4MCS0;
+	else if (rate_idx >= ODM_RATEVHTSS3MCS0)
+		rate_idx -= ODM_RATEVHTSS3MCS0;
+	else if (rate_idx >= ODM_RATEVHTSS2MCS0)
+		rate_idx -= ODM_RATEVHTSS2MCS0;
+	else if (rate_idx >= ODM_RATEVHTSS1MCS0)
+		rate_idx -= ODM_RATEVHTSS1MCS0;
+	else if (rate_idx >= ODM_RATEMCS24)
+		rate_idx -= ODM_RATEMCS24;
+	else if (rate_idx >= ODM_RATEMCS16)
+		rate_idx -= ODM_RATEMCS16;
+	else if (rate_idx >= ODM_RATEMCS8)
+		rate_idx -= ODM_RATEMCS8;
+	rate_order = rate_idx;
+
+	return rate_order;
+}
+
+#if (DM_ODM_SUPPORT_TYPE == ODM_CE)
+u8 phydm_rate2ss(void *dm_void, u8 rate_idx)
+{
+	u8 ret = 0xff;
+	u8 i, j;
+	u8 search_idx;
+	u32 ss_mapping_tab[4][3] = {{0x00000000, 0x003ff000, 0x000ff000},
+				    {0x00000000, 0xffc00000, 0x0ff00000},
+				    {0x000003ff, 0x0000000f, 0xf0000000},
+				    {0x000ffc00, 0x00000ff0, 0x00000000} };
+	if (rate_idx < 32) {
+		search_idx = rate_idx;
+		j = 0;
+	} else if (rate_idx < 64) {
+		search_idx = rate_idx - 32;
+		j = 1;
+	} else {
+		search_idx = rate_idx - 64;
+		j = 2;
+	}
+	for (i = 0; i < 4; i++)
+		if (ss_mapping_tab[i][j] & BIT(search_idx))
+			ret = i;
+	return ret;
+}
+
+u8 phydm_rate2plcp(void *dm_void, u8 rate_idx)
+{
+	u8 rate2ss = 0;
+	u8 ltftime = 0;
+	u8 plcptime = 0xff;
+
+	if (rate_idx < ODM_RATE6M) {
+		plcptime = 192;
+		/* @CCK PLCP = 192us (long preamble) */
+	} else if (rate_idx < ODM_RATEMCS0) {
+		plcptime = 20;
+		/* @LegOFDM PLCP = 20us */
+	} else {
+		if (rate_idx < ODM_RATEVHTSS1MCS0)
+			plcptime = 32;
+		/* @HT mode PLCP = 20us + 12us + 4us x Nss */
+		else
+			plcptime = 36;
+		/* VHT mode PLCP = 20us + 16us + 4us x Nss */
+		rate2ss = phydm_rate2ss(dm_void, rate_idx);
+		if (rate2ss != 0xff)
+			ltftime = (rate2ss + 1) * 4;
+		else
+			return 0xff;
+
+		plcptime += ltftime;
+	}
+	return plcptime;
+}
+
+u8 phydm_get_plcp(void *dm_void, u16 macid)
+{
+	u8 plcp_time = 0;
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct cmn_sta_info *sta = NULL;
+	struct ra_sta_info *ra = NULL;
+
+	sta = dm->phydm_sta_info[macid];
+	ra = &sta->ra_info;
+	plcp_time = phydm_rate2plcp(dm, ra->curr_tx_rate);
+	return plcp_time;
+}
+#endif
+
+void phydm_ra_common_info_update(void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct ra_table *ra_tab = &dm->dm_ra_table;
+	struct cmn_sta_info *sta = NULL;
+	u16 macid;
+	u8 rate_order_tmp;
+	u8 rate_idx = 0;
+	u8 cnt = 0;
+
+	ra_tab->highest_client_tx_order = 0;
+	ra_tab->power_tracking_flag = 1;
+
+	if (!dm->number_linked_client)
+		return;
+
+	for (macid = 0; macid < ODM_ASSOCIATE_ENTRY_NUM; macid++) {
+		sta = dm->phydm_sta_info[macid];
+
+		if (!is_sta_active(sta))
+			continue;
+
+		rate_idx = sta->ra_info.curr_tx_rate & 0x7f;
+		rate_order_tmp = phydm_rate_order_compute(dm, rate_idx);
+
+		if (rate_order_tmp >= ra_tab->highest_client_tx_order) {
+			ra_tab->highest_client_tx_order = rate_order_tmp;
+			ra_tab->highest_client_tx_rate_order = macid;
+		}
+
+		cnt++;
+
+		if (cnt == dm->number_linked_client)
+			break;
+	}
+	PHYDM_DBG(dm, DBG_RA,
+		  "MACID[%d], Highest Tx order Update for power traking: %d\n",
+		  ra_tab->highest_client_tx_rate_order,
+		  ra_tab->highest_client_tx_order);
+}
+
+void phydm_ra_info_watchdog(void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+
+	phydm_ra_common_info_update(dm);
+	phydm_ra_dynamic_retry_count(dm);
+	phydm_ra_mask_watchdog(dm);
+
+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
+	odm_refresh_basic_rate_mask(dm);
+#endif
+}
+
+void phydm_ra_info_init(void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct ra_table *ra_tab = &dm->dm_ra_table;
+
+	ra_tab->highest_client_tx_rate_order = 0;
+	ra_tab->highest_client_tx_order = 0;
+	ra_tab->ra_th_ofst = 0;
+	ra_tab->ra_ofst_direc = 0;
+
+#if (RTL8822B_SUPPORT == 1)
+	if (dm->support_ic_type == ODM_RTL8822B) {
+		u32 ret_value;
+
+		ret_value = odm_get_bb_reg(dm, R_0x4c8, MASKBYTE2);
+		odm_set_bb_reg(dm, R_0x4cc, MASKBYTE3, (ret_value - 1));
+	}
+#endif
+
+	#if 0 /*@CONFIG_RA_DYNAMIC_RTY_LIMIT*/
+	phydm_ra_dynamic_retry_limit_init(dm);
+	#endif
+
+	#if 0 /*@CONFIG_RA_DYNAMIC_RATE_ID*/
+	phydm_ra_dynamic_rate_id_init(dm);
+	#endif
+
+	phydm_rate_adaptive_mask_init(dm);
+}
+
+u8 odm_find_rts_rate(void *dm_void, u8 tx_rate, boolean is_erp_protect)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	u8 rts_ini_rate = ODM_RATE6M;
+
+	if (is_erp_protect) { /* use CCK rate as RTS*/
+		rts_ini_rate = ODM_RATE1M;
+	} else {
+		switch (tx_rate) {
+		case ODM_RATEVHTSS4MCS9:
+		case ODM_RATEVHTSS4MCS8:
+		case ODM_RATEVHTSS4MCS7:
+		case ODM_RATEVHTSS4MCS6:
+		case ODM_RATEVHTSS4MCS5:
+		case ODM_RATEVHTSS4MCS4:
+		case ODM_RATEVHTSS4MCS3:
+		case ODM_RATEVHTSS3MCS9:
+		case ODM_RATEVHTSS3MCS8:
+		case ODM_RATEVHTSS3MCS7:
+		case ODM_RATEVHTSS3MCS6:
+		case ODM_RATEVHTSS3MCS5:
+		case ODM_RATEVHTSS3MCS4:
+		case ODM_RATEVHTSS3MCS3:
+		case ODM_RATEVHTSS2MCS9:
+		case ODM_RATEVHTSS2MCS8:
+		case ODM_RATEVHTSS2MCS7:
+		case ODM_RATEVHTSS2MCS6:
+		case ODM_RATEVHTSS2MCS5:
+		case ODM_RATEVHTSS2MCS4:
+		case ODM_RATEVHTSS2MCS3:
+		case ODM_RATEVHTSS1MCS9:
+		case ODM_RATEVHTSS1MCS8:
+		case ODM_RATEVHTSS1MCS7:
+		case ODM_RATEVHTSS1MCS6:
+		case ODM_RATEVHTSS1MCS5:
+		case ODM_RATEVHTSS1MCS4:
+		case ODM_RATEVHTSS1MCS3:
+		case ODM_RATEMCS31:
+		case ODM_RATEMCS30:
+		case ODM_RATEMCS29:
+		case ODM_RATEMCS28:
+		case ODM_RATEMCS27:
+		case ODM_RATEMCS23:
+		case ODM_RATEMCS22:
+		case ODM_RATEMCS21:
+		case ODM_RATEMCS20:
+		case ODM_RATEMCS19:
+		case ODM_RATEMCS15:
+		case ODM_RATEMCS14:
+		case ODM_RATEMCS13:
+		case ODM_RATEMCS12:
+		case ODM_RATEMCS11:
+		case ODM_RATEMCS7:
+		case ODM_RATEMCS6:
+		case ODM_RATEMCS5:
+		case ODM_RATEMCS4:
+		case ODM_RATEMCS3:
+		case ODM_RATE54M:
+		case ODM_RATE48M:
+		case ODM_RATE36M:
+		case ODM_RATE24M:
+			rts_ini_rate = ODM_RATE24M;
+			break;
+		case ODM_RATEVHTSS4MCS2:
+		case ODM_RATEVHTSS4MCS1:
+		case ODM_RATEVHTSS3MCS2:
+		case ODM_RATEVHTSS3MCS1:
+		case ODM_RATEVHTSS2MCS2:
+		case ODM_RATEVHTSS2MCS1:
+		case ODM_RATEVHTSS1MCS2:
+		case ODM_RATEVHTSS1MCS1:
+		case ODM_RATEMCS26:
+		case ODM_RATEMCS25:
+		case ODM_RATEMCS18:
+		case ODM_RATEMCS17:
+		case ODM_RATEMCS10:
+		case ODM_RATEMCS9:
+		case ODM_RATEMCS2:
+		case ODM_RATEMCS1:
+		case ODM_RATE18M:
+		case ODM_RATE12M:
+			rts_ini_rate = ODM_RATE12M;
+			break;
+		case ODM_RATEVHTSS4MCS0:
+		case ODM_RATEVHTSS3MCS0:
+		case ODM_RATEVHTSS2MCS0:
+		case ODM_RATEVHTSS1MCS0:
+		case ODM_RATEMCS24:
+		case ODM_RATEMCS16:
+		case ODM_RATEMCS8:
+		case ODM_RATEMCS0:
+		case ODM_RATE9M:
+		case ODM_RATE6M:
+			rts_ini_rate = ODM_RATE6M;
+			break;
+		case ODM_RATE11M:
+		case ODM_RATE5_5M:
+		case ODM_RATE2M:
+		case ODM_RATE1M:
+			rts_ini_rate = ODM_RATE1M;
+			break;
+		default:
+			rts_ini_rate = ODM_RATE6M;
+			break;
+		}
+	}
+
+	if (*dm->band_type == ODM_BAND_5G) {
+		if (rts_ini_rate < ODM_RATE6M)
+			rts_ini_rate = ODM_RATE6M;
+	}
+	return rts_ini_rate;
+}
+
+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
+
+void odm_refresh_basic_rate_mask(
+	void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	void *adapter = dm->adapter;
+	static u8 stage = 0;
+	u8 cur_stage = 0;
+	OCTET_STRING os_rate_set;
+	PMGNT_INFO mgnt_info = GetDefaultMgntInfo(((PADAPTER)adapter));
+	u8 rate_set[5] = {MGN_1M, MGN_2M, MGN_5_5M, MGN_11M, MGN_6M};
+
+	if (dm->support_ic_type != ODM_RTL8812 && dm->support_ic_type != ODM_RTL8821)
+		return;
+
+	if (dm->is_linked == false) /* unlink Default port information */
+		cur_stage = 0;
+	else if (dm->rssi_min < 40) /* @link RSSI  < 40% */
+		cur_stage = 1;
+	else if (dm->rssi_min > 45) /* @link RSSI > 45% */
+		cur_stage = 3;
+	else
+		cur_stage = 2; /* @link  25% <= RSSI <= 30% */
+
+	if (cur_stage != stage) {
+		if (cur_stage == 1) {
+			FillOctetString(os_rate_set, rate_set, 5);
+			FilterSupportRate(mgnt_info->mBrates, &os_rate_set, false);
+			phydm_set_hw_reg_handler_interface(dm, HW_VAR_BASIC_RATE, (u8 *)&os_rate_set);
+		} else if (cur_stage == 3 && (stage == 1 || stage == 2))
+			phydm_set_hw_reg_handler_interface(dm, HW_VAR_BASIC_RATE, (u8 *)(&mgnt_info->mBrates));
+	}
+
+	stage = cur_stage;
+}
+
+#endif
+
+#if 0 /*@CONFIG_RA_DYNAMIC_RTY_LIMIT*/
+
+void phydm_retry_limit_table_bound(
+	void *dm_void,
+	u8 *retry_limit,
+	u8 offset)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct ra_table *ra_tab = &dm->dm_ra_table;
+
+	if (*retry_limit > offset) {
+		*retry_limit -= offset;
+
+		if (*retry_limit < ra_tab->retrylimit_low)
+			*retry_limit = ra_tab->retrylimit_low;
+		else if (*retry_limit > ra_tab->retrylimit_high)
+			*retry_limit = ra_tab->retrylimit_high;
+	} else
+		*retry_limit = ra_tab->retrylimit_low;
+}
+
+void phydm_reset_retry_limit_table(
+	void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct ra_table *ra_t = &dm->dm_ra_table;
+	u8 i;
+
+	u8 per_rate_retrylimit_table_20M[ODM_RATEMCS15 + 1] = {
+		1, 1, 2, 4, /*@CCK*/
+		2, 2, 4, 6, 8, 12, 16, 18, /*OFDM*/
+		2, 4, 6, 8, 12, 18, 20, 22, /*@20M HT-1SS*/
+		2, 4, 6, 8, 12, 18, 20, 22 /*@20M HT-2SS*/
+	};
+	u8 per_rate_retrylimit_table_40M[ODM_RATEMCS15 + 1] = {
+		1, 1, 2, 4, /*@CCK*/
+		2, 2, 4, 6, 8, 12, 16, 18, /*OFDM*/
+		4, 8, 12, 16, 24, 32, 32, 32, /*@40M HT-1SS*/
+		4, 8, 12, 16, 24, 32, 32, 32 /*@40M HT-2SS*/
+	};
+
+	memcpy(&ra_t->per_rate_retrylimit_20M[0],
+	       &per_rate_retrylimit_table_20M[0], ODM_NUM_RATE_IDX);
+	memcpy(&ra_t->per_rate_retrylimit_40M[0],
+	       &per_rate_retrylimit_table_40M[0], ODM_NUM_RATE_IDX);
+
+	for (i = 0; i < ODM_NUM_RATE_IDX; i++) {
+		phydm_retry_limit_table_bound(dm,
+					      &ra_t->per_rate_retrylimit_20M[i],
+					      0);
+		phydm_retry_limit_table_bound(dm,
+					      &ra_t->per_rate_retrylimit_40M[i],
+					      0);
+	}
+}
+
+void phydm_ra_dynamic_retry_limit_init(
+	void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct ra_table *ra_tab = &dm->dm_ra_table;
+
+	ra_tab->retry_descend_num = RA_RETRY_DESCEND_NUM;
+	ra_tab->retrylimit_low = RA_RETRY_LIMIT_LOW;
+	ra_tab->retrylimit_high = RA_RETRY_LIMIT_HIGH;
+
+	phydm_reset_retry_limit_table(dm);
+}
+
+void phydm_ra_dynamic_retry_limit(
+	void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct ra_table *ra_tab = &dm->dm_ra_table;
+	u8 i, retry_offset;
+	u32 ma_rx_tp;
+
+	if (dm->pre_number_active_client == dm->number_active_client) {
+		PHYDM_DBG(dm, DBG_RA,
+			  "pre_number_active_client ==  number_active_client\n");
+		return;
+
+	} else {
+		if (dm->number_active_client == 1) {
+			phydm_reset_retry_limit_table(dm);
+			PHYDM_DBG(dm, DBG_RA,
+				  "one client only->reset to default value\n");
+		} else {
+			retry_offset = dm->number_active_client * ra_tab->retry_descend_num;
+
+			for (i = 0; i < ODM_NUM_RATE_IDX; i++) {
+				phydm_retry_limit_table_bound(dm,
+							      &ra_tab->per_rate_retrylimit_20M[i],
+							      retry_offset);
+				phydm_retry_limit_table_bound(dm,
+							      &ra_tab->per_rate_retrylimit_40M[i],
+							      retry_offset);
+			}
+		}
+	}
+}
+#endif
+
+#if 0 /*@CONFIG_RA_DYNAMIC_RATE_ID*/
+void phydm_ra_dynamic_rate_id_on_assoc(
+	void *dm_void,
+	u8 wireless_mode,
+	u8 init_rate_id)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+
+	PHYDM_DBG(dm, DBG_RA,
+		  "[ON ASSOC] rf_mode = ((0x%x)), wireless_mode = ((0x%x)), init_rate_id = ((0x%x))\n",
+		  dm->rf_type, wireless_mode, init_rate_id);
+
+	if (dm->rf_type == RF_2T2R || dm->rf_type == RF_2T3R || dm->rf_type == RF_2T4R) {
+		if ((dm->support_ic_type & (ODM_RTL8812 | ODM_RTL8192E)) &&
+		    (wireless_mode & (ODM_WM_N24G | ODM_WM_N5G))) {
+			PHYDM_DBG(dm, DBG_RA,
+				  "[ON ASSOC] set N-2SS ARFR5 table\n");
+			odm_set_mac_reg(dm, R_0x4a4, MASKDWORD, 0xfc1ffff); /*N-2SS, ARFR5, rate_id = 0xe*/
+			odm_set_mac_reg(dm, R_0x4a8, MASKDWORD, 0x0); /*N-2SS, ARFR5, rate_id = 0xe*/
+		} else if ((dm->support_ic_type & (ODM_RTL8812)) &&
+			   (wireless_mode & (ODM_WM_AC_5G | ODM_WM_AC_24G | ODM_WM_AC_ONLY))) {
+			PHYDM_DBG(dm, DBG_RA,
+				  "[ON ASSOC] set AC-2SS ARFR0 table\n");
+			odm_set_mac_reg(dm, R_0x444, MASKDWORD, 0x0fff); /*@AC-2SS, ARFR0, rate_id = 0x9*/
+			odm_set_mac_reg(dm, R_0x448, MASKDWORD, 0xff01f000); /*@AC-2SS, ARFR0, rate_id = 0x9*/
+		}
+	}
+}
+
+void phydm_ra_dynamic_rate_id_init(
+	void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+
+	if (dm->support_ic_type & (ODM_RTL8812 | ODM_RTL8192E)) {
+		odm_set_mac_reg(dm, R_0x4a4, MASKDWORD, 0xfc1ffff); /*N-2SS, ARFR5, rate_id = 0xe*/
+		odm_set_mac_reg(dm, R_0x4a8, MASKDWORD, 0x0); /*N-2SS, ARFR5, rate_id = 0xe*/
+
+		odm_set_mac_reg(dm, R_0x444, MASKDWORD, 0x0fff); /*@AC-2SS, ARFR0, rate_id = 0x9*/
+		odm_set_mac_reg(dm, R_0x448, MASKDWORD, 0xff01f000); /*@AC-2SS, ARFR0, rate_id = 0x9*/
+	}
+}
+
+void phydm_update_rate_id(
+	void *dm_void,
+	u8 rate,
+	u8 platform_macid)
+{
+#if 0
+
+	struct dm_struct	*dm = (struct dm_struct *)dm_void;
+	struct ra_table		*ra_tab = &dm->dm_ra_table;
+	u8		current_tx_ss;
+	u8		rate_idx = rate & 0x7f; /*remove bit7 SGI*/
+	u8		wireless_mode;
+	u8		phydm_macid;
+	struct sta_info	*entry;
+	struct cmn_sta_info	*sta;
+
+#if 0
+	if (rate_idx >= ODM_RATEVHTSS2MCS0) {
+		PHYDM_DBG(dm, DBG_RA, "rate[%d]: (( VHT2SS-MCS%d ))\n",
+			  platform_macid, (rate_idx - ODM_RATEVHTSS2MCS0));
+		/*@dummy for SD4 check patch*/
+	} else if (rate_idx >= ODM_RATEVHTSS1MCS0) {
+		PHYDM_DBG(dm, DBG_RA, "rate[%d]: (( VHT1SS-MCS%d ))\n",
+			  platform_macid, (rate_idx - ODM_RATEVHTSS1MCS0));
+		/*@dummy for SD4 check patch*/
+	} else if (rate_idx >= ODM_RATEMCS0) {
+		PHYDM_DBG(dm, DBG_RA, "rate[%d]: (( HT-MCS%d ))\n",
+			  platform_macid, (rate_idx - ODM_RATEMCS0));
+		/*@dummy for SD4 check patch*/
+	} else {
+		PHYDM_DBG(dm, DBG_RA, "rate[%d]: (( HT-MCS%d ))\n",
+			  platform_macid, rate_idx);
+		/*@dummy for SD4 check patch*/
+	}
+#endif
+
+	phydm_macid = dm->phydm_macid_table[platform_macid];
+	entry = dm->odm_sta_info[phydm_macid];
+	sta = dm->phydm_sta_info[phydm_macid];
+
+	if (is_sta_active(sta)) {
+		wireless_mode = entry->wireless_mode;
+
+		if (dm->rf_type == RF_2T2R || dm->rf_type == RF_2T3R || dm->rf_type == RF_2T4R) {
+			if (wireless_mode & (ODM_WM_N24G | ODM_WM_N5G)) { /*N mode*/
+				if (rate_idx >= ODM_RATEMCS8 && rate_idx <= ODM_RATEMCS15) { /*@2SS mode*/
+
+					sta->ra_info.rate_id  = ARFR_5_RATE_ID;
+					PHYDM_DBG(dm, DBG_RA, "ARFR_5\n");
+				}
+			} else if (wireless_mode & (ODM_WM_AC_5G | ODM_WM_AC_24G | ODM_WM_AC_ONLY)) {/*@AC mode*/
+				if (rate_idx >= ODM_RATEVHTSS2MCS0 && rate_idx <= ODM_RATEVHTSS2MCS9) {/*@2SS mode*/
+
+					sta->ra_info.rate_id  = ARFR_0_RATE_ID;
+					PHYDM_DBG(dm, DBG_RA, "ARFR_0\n");
+				}
+			} else
+				sta->ra_info.rate_id  = ARFR_0_RATE_ID;
+
+			PHYDM_DBG(dm, DBG_RA, "UPdate_RateID[%d]: (( 0x%x ))\n",
+				  platform_macid, sta->ra_info.rate_id);
+		}
+	}
+#endif
+}
+
+#endif
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/phydm_rainfo.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/phydm_rainfo.h
--- linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/phydm_rainfo.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/phydm_rainfo.h	2020-04-10 16:35:06.827660581 +0300
@@ -0,0 +1,276 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017  Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * The full GNU General Public License is included in this distribution in the
+ * file called LICENSE.
+ *
+ * Contact Information:
+ * wlanfae <wlanfae@realtek.com>
+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
+ * Hsinchu 300, Taiwan.
+ *
+ * Larry Finger <Larry.Finger@lwfinger.net>
+ *
+ *****************************************************************************/
+
+#ifndef __PHYDMRAINFO_H__
+#define __PHYDMRAINFO_H__
+
+#define RAINFO_VERSION "8.0"
+
+#define	FORCED_UPDATE_RAMASK_PERIOD	5
+
+#define	H2C_MAX_LENGTH		7
+
+#define	RA_FLOOR_UP_GAP		3
+#define	RA_FLOOR_TABLE_SIZE	7
+
+#define	ACTIVE_TP_THRESHOLD	1
+#define	RA_RETRY_DESCEND_NUM	2
+#define	RA_RETRY_LIMIT_LOW	4
+#define	RA_RETRY_LIMIT_HIGH	32
+
+#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
+	#define	FIRST_MACID	1
+#else
+	#define	FIRST_MACID	0
+#endif
+
+/* @1 ============================================================
+ * 1 enumrate
+ * 1 ============================================================
+ */
+
+enum phydm_ra_dbg_para {
+	RADBG_PCR_TH_OFFSET	= 0,
+	RADBG_RTY_PENALTY	= 1,
+	RADBG_N_HIGH		= 2,
+	RADBG_N_LOW		= 3,
+	RADBG_TRATE_UP_TABLE	= 4,
+	RADBG_TRATE_DOWN_TABLE	= 5,
+	RADBG_TRYING_NECESSARY	= 6,
+	RADBG_TDROPING_NECESSARY = 7,
+	RADBG_RATE_UP_RTY_RATIO	= 8,
+	RADBG_RATE_DOWN_RTY_RATIO = 9, /* u8 */
+
+	RADBG_DEBUG_MONITOR1	= 0xc,
+	RADBG_DEBUG_MONITOR2	= 0xd,
+	RADBG_DEBUG_MONITOR3	= 0xe,
+	RADBG_DEBUG_MONITOR4	= 0xf,
+	RADBG_DEBUG_MONITOR5	= 0x10,
+	NUM_RA_PARA
+};
+
+enum phydm_wireless_mode {
+	PHYDM_WIRELESS_MODE_UNKNOWN	= 0x00,
+	PHYDM_WIRELESS_MODE_A		= 0x01,
+	PHYDM_WIRELESS_MODE_B		= 0x02,
+	PHYDM_WIRELESS_MODE_G		= 0x04,
+	PHYDM_WIRELESS_MODE_AUTO	= 0x08,
+	PHYDM_WIRELESS_MODE_N_24G	= 0x10,
+	PHYDM_WIRELESS_MODE_N_5G	= 0x20,
+	PHYDM_WIRELESS_MODE_AC_5G	= 0x40,
+	PHYDM_WIRELESS_MODE_AC_24G	= 0x80,
+	PHYDM_WIRELESS_MODE_AC_ONLY	= 0x100,
+	PHYDM_WIRELESS_MODE_MAX		= 0x800,
+	PHYDM_WIRELESS_MODE_ALL		= 0xFFFF
+};
+
+enum phydm_rateid_idx {
+	PHYDM_BGN_40M_2SS	= 0,
+	PHYDM_BGN_40M_1SS	= 1,
+	PHYDM_BGN_20M_2SS	= 2,
+	PHYDM_BGN_20M_1SS	= 3,
+	PHYDM_GN_N2SS		= 4,
+	PHYDM_GN_N1SS		= 5,
+	PHYDM_BG		= 6,
+	PHYDM_G			= 7,
+	PHYDM_B_20M		= 8,
+	PHYDM_ARFR0_AC_2SS	= 9,
+	PHYDM_ARFR1_AC_1SS	= 10,
+	PHYDM_ARFR2_AC_2G_1SS	= 11,
+	PHYDM_ARFR3_AC_2G_2SS	= 12,
+	PHYDM_ARFR4_AC_3SS	= 13,
+	PHYDM_ARFR5_N_3SS	= 14,
+	PHYDM_ARFR7_N_4SS	= 15,
+	PHYDM_ARFR6_AC_4SS	= 16
+};
+
+#if (RATE_ADAPTIVE_SUPPORT == 1)/* @88E RA */
+
+struct _phydm_txstatistic_ {
+	u32	hw_total_tx;
+	u32	hw_tx_success;
+	u32	hw_tx_rty;
+	u32	hw_tx_drop;
+};
+
+/* @1 ============================================================
+ * 1  structure
+ * 1 ============================================================
+ */
+struct _odm_ra_info_ {
+	u8	rate_id;
+	u32	rate_mask;
+	u32	ra_use_rate;
+	u8	rate_sgi;
+	u8	rssi_sta_ra;
+	u8	pre_rssi_sta_ra;
+	u8	sgi_enable;
+	u8	decision_rate;
+	u8	pre_rate;
+	u8	highest_rate;
+	u8	lowest_rate;
+	u32	nsc_up;
+	u32	nsc_down;
+	u16	RTY[5];
+	u32	TOTAL;
+	u16	DROP;
+	u8	active;
+	u16	rpt_time;
+	u8	ra_waiting_counter;
+	u8	ra_pending_counter;
+	u8	ra_drop_after_down;
+#if 1 /* POWER_TRAINING_ACTIVE == 1 */ /* For compile  pass only~! */
+	u8	pt_active;	/* on or off */
+	u8	pt_try_state;	/* @0 trying state, 1 for decision state */
+	u8	pt_stage;	/* @0~6 */
+	u8	pt_stop_count;	/* Stop PT counter */
+	u8	pt_pre_rate;	/* @if rate change do PT */
+	u8	pt_pre_rssi;	/* @if RSSI change 5% do PT */
+	u8	pt_mode_ss;	/* @decide whitch rate should do PT */
+	u8	ra_stage;	/* @StageRA, decide how many times RA will be done between PT */
+	u8	pt_smooth_factor;
+#endif
+#if (DM_ODM_SUPPORT_TYPE == ODM_AP) &&	((DEV_BUS_TYPE == RT_USB_INTERFACE) || (DEV_BUS_TYPE == RT_SDIO_INTERFACE))
+	u8	rate_down_counter;
+	u8	rate_up_counter;
+	u8	rate_direction;
+	u8	bounding_type;
+	u8	bounding_counter;
+	u8	bounding_learning_time;
+	u8	rate_down_start_time;
+#endif
+};
+#endif
+
+
+struct ra_table {
+	u8	firstconnect;
+	/*@u8	link_tx_rate[ODM_ASSOCIATE_ENTRY_NUM];*/
+	u8	mu1_rate[30];
+	u8	highest_client_tx_order;
+	u16	highest_client_tx_rate_order;
+	u8	power_tracking_flag;
+	u8	ra_th_ofst; /*RA_threshold_offset*/
+	u8	ra_ofst_direc; /*RA_offset_direction*/
+	u8	up_ramask_cnt; /*@force update_ra_mask counter*/
+	u8	up_ramask_cnt_tmp; /*@Just for debug, should be removed latter*/
+#if 0	/*@CONFIG_RA_DYNAMIC_RTY_LIMIT*/
+	u8	per_rate_retrylimit_20M[ODM_NUM_RATE_IDX];
+	u8	per_rate_retrylimit_40M[ODM_NUM_RATE_IDX];
+	u8	retry_descend_num;
+	u8	retrylimit_low;
+	u8	retrylimit_high;
+#endif
+	u8	ldpc_thres; /* @if RSSI > ldpc_th => switch from LPDC to BCC */
+	void (*record_ra_info)(void *dm_void, u8 macid,
+			       struct cmn_sta_info *sta, u64 ra_mask);
+};
+
+/* @1 ============================================================
+ * 1  Function Prototype
+ * 1 ============================================================
+ */
+boolean phydm_is_cck_rate(void *dm_void, u8 rate);
+
+boolean phydm_is_ofdm_rate(void *dm_void, u8 rate);
+
+boolean phydm_is_ht_rate(void *dm_void, u8 rate);
+
+boolean phydm_is_vht_rate(void *dm_void, u8 rate);
+
+u8 phydm_rate_type_2_num_ss(void *dm_void, enum PDM_RATE_TYPE type);
+
+u8 phydm_rate_to_num_ss(void *dm_void, u8 data_rate);
+
+void phydm_h2C_debug(void *dm_void, char input[][16], u32 *_used,
+		     char *output, u32 *_out_len);
+
+void phydm_ra_debug(void *dm_void, char input[][16], u32 *_used, char *output,
+		    u32 *_out_len);
+
+void odm_c2h_ra_para_report_handler(void *dm_void, u8 *cmd_buf, u8 cmd_len);
+
+void phydm_ra_dynamic_retry_count(void *dm_void);
+
+
+void phydm_print_rate(void *dm_void, u8 rate, u32 dbg_component);
+
+void phydm_print_rate_2_buff(void *dm_void, u8 rate, char *buf, u16 buf_size);
+
+void phydm_c2h_ra_report_handler(void *dm_void, u8 *cmd_buf, u8 cmd_len);
+
+u8 phydm_rate_order_compute(void *dm_void, u8 rate_idx);
+
+void phydm_ra_info_watchdog(void *dm_void);
+
+void phydm_ra_info_init(void *dm_void);
+
+void phydm_modify_RA_PCR_threshold(void *dm_void, u8 ra_ofst_direc,
+				   u8 ra_th_ofst);
+
+u8 phydm_vht_en_mapping(void *dm_void, u32 wireless_mode);
+
+u8 phydm_rate_id_mapping(void *dm_void, u32 wireless_mode, u8 rf_type, u8 bw);
+#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
+void phydm_update_hal_ra_mask(
+	void *dm_void,
+	u32 wireless_mode,
+	u8 rf_type,
+	u8 BW,
+	u8 mimo_ps_enable,
+	u8 disable_cck_rate,
+	u32 *ratr_bitmap_msb_in,
+	u32 *ratr_bitmap_in,
+	u8 tx_rate_level);
+#endif
+
+#if (DM_ODM_SUPPORT_TYPE == ODM_CE)
+u8 phydm_get_plcp(void *dm_void, u16 macid);
+#endif
+
+void phydm_refresh_rate_adaptive_mask(void *dm_void);
+
+u8 phydm_rssi_lv_dec(void *dm_void, u32 rssi, u8 ratr_state);
+
+void odm_ra_post_action_on_assoc(void *dm);
+
+u8 odm_find_rts_rate(void *dm_void, u8 tx_rate, boolean is_erp_protect);
+
+void phydm_show_sta_info(void *dm_void, char input[][16], u32 *_used,
+			 char *output, u32 *_out_len);
+
+u8 phydm_get_rate_from_rssi_lv(void *dm_void, u8 sta_idx);
+
+void phydm_ra_registed(void *dm_void, u8 macid, u8 rssi_from_assoc);
+
+void phydm_ra_offline(void *dm_void, u8 macid);
+
+void phydm_ra_mask_watchdog(void *dm_void);
+
+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
+void odm_refresh_basic_rate_mask(
+	void *dm_void);
+#endif
+#endif /*@#ifndef __PHYDMRAINFO_H__*/
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/phydm_regdefine11ac.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/phydm_regdefine11ac.h
--- linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/phydm_regdefine11ac.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/phydm_regdefine11ac.h	2020-04-10 16:35:06.827660581 +0300
@@ -0,0 +1,109 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017  Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * The full GNU General Public License is included in this distribution in the
+ * file called LICENSE.
+ *
+ * Contact Information:
+ * wlanfae <wlanfae@realtek.com>
+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
+ * Hsinchu 300, Taiwan.
+ *
+ * Larry Finger <Larry.Finger@lwfinger.net>
+ *
+ *****************************************************************************/
+
+#ifndef __ODM_REGDEFINE11AC_H__
+#define __ODM_REGDEFINE11AC_H__
+
+/* @2 RF REG LIST */
+
+
+
+/* @2 BB REG LIST */
+/* PAGE 8 */
+#define	ODM_REG_CCK_RPT_FORMAT_11AC		0x804
+#define	ODM_REG_BB_RX_PATH_11AC			0x808
+#define	ODM_REG_BB_TX_PATH_11AC			0x80c
+#define	ODM_REG_BB_ATC_11AC			0x860
+#define	ODM_REG_EDCCA_POWER_CAL			0x8dc
+#define	ODM_REG_DBG_RPT_11AC			0x8fc
+/* PAGE 9 */
+#define	ODM_REG_EDCCA_DOWN_OPT			0x900
+#define	ODM_REG_ACBB_EDCCA_ENHANCE		0x944
+#define	odm_adc_trigger_jaguar2			0x95C	/*@ADC sample mode*/
+#define	ODM_REG_OFDM_FA_RST_11AC		0x9A4
+#define	ODM_REG_CCX_PERIOD_11AC			0x990
+#define	ODM_REG_NHM_TH9_TH10_11AC		0x994
+#define	ODM_REG_CLM_11AC			0x994
+#define	ODM_REG_NHM_TH3_TO_TH0_11AC		0x998
+#define	ODM_REG_NHM_TH7_TO_TH4_11AC		0x99c
+#define	ODM_REG_NHM_TH8_11AC			0x9a0
+#define	ODM_REG_NHM_9E8_11AC			0x9e8
+#define	ODM_REG_CSI_CONTENT_VALUE		0x9b4
+/* PAGE A */
+#define	ODM_REG_CCK_CCA_11AC			0xA0A
+#define	ODM_REG_CCK_FA_RST_11AC			0xA2C
+#define	ODM_REG_CCK_FA_11AC			0xA5C
+/* PAGE B */
+#define	ODM_REG_RST_RPT_11AC			0xB58
+/* PAGE C */
+#define	ODM_REG_TRMUX_11AC			0xC08
+#define	ODM_REG_IGI_A_11AC			0xC50
+/* PAGE E */
+#define	ODM_REG_IGI_B_11AC			0xE50
+#define	ODM_REG_ANT_11AC_B			0xE08
+/* PAGE F */
+#define	ODM_REG_CCK_CRC32_CNT_11AC		0xF04
+#define	ODM_REG_CCK_CCA_CNT_11AC		0xF08
+#define	ODM_REG_VHT_CRC32_CNT_11AC		0xF0c
+#define	ODM_REG_HT_CRC32_CNT_11AC		0xF10
+#define	ODM_REG_OFDM_CRC32_CNT_11AC		0xF14
+#define	ODM_REG_OFDM_FA_11AC			0xF48
+#define	ODM_REG_OFDM_FA_TYPE1_11AC		0xFCC
+#define	ODM_REG_OFDM_FA_TYPE2_11AC		0xFD0
+#define	ODM_REG_OFDM_FA_TYPE3_11AC		0xFBC
+#define	ODM_REG_OFDM_FA_TYPE4_11AC		0xFC0
+#define	ODM_REG_OFDM_FA_TYPE5_11AC		0xFC4
+#define	ODM_REG_OFDM_FA_TYPE6_11AC		0xFC8
+#define	ODM_REG_RPT_11AC			0xfa0
+#define	ODM_REG_CLM_RESULT_11AC			0xfa4
+#define	ODM_REG_NHM_CNT_11AC			0xfa8
+#define ODM_REG_NHM_DUR_READY_11AC		0xfb4
+
+#define	ODM_REG_NHM_CNT7_TO_CNT4_11AC		0xfac
+#define	ODM_REG_NHM_CNT11_TO_CNT8_11AC		0xfb0
+/* PAGE 18 */
+#define	ODM_REG_IGI_C_11AC			0x1850
+/* PAGE 1A */
+#define	ODM_REG_IGI_D_11AC			0x1A50
+
+/* PAGE 1D */
+#define	ODM_REG_IGI_11AC3			0x1D70
+
+/* @2 MAC REG LIST */
+#define	ODM_REG_RESP_TX_11AC			0x6D8
+
+
+
+/* @DIG Related */
+#define	ODM_BIT_IGI_11AC			0x0000007F
+#define	ODM_BIT_IGI_B_11AC3			0x00007F00
+#define	ODM_BIT_IGI_C_11AC3			0x007F0000
+#define	ODM_BIT_IGI_D_11AC3			0x7F000000
+#define	ODM_BIT_CCK_RPT_FORMAT_11AC		BIT(16)
+#define	ODM_BIT_BB_RX_PATH_11AC			0xF
+#define	ODM_BIT_BB_TX_PATH_11AC			0xF
+#define	ODM_BIT_BB_ATC_11AC			BIT(14)
+
+#endif
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/phydm_regdefine11n.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/phydm_regdefine11n.h
--- linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/phydm_regdefine11n.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/phydm_regdefine11n.h	2020-04-10 16:35:06.827660581 +0300
@@ -0,0 +1,219 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017  Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * The full GNU General Public License is included in this distribution in the
+ * file called LICENSE.
+ *
+ * Contact Information:
+ * wlanfae <wlanfae@realtek.com>
+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
+ * Hsinchu 300, Taiwan.
+ *
+ * Larry Finger <Larry.Finger@lwfinger.net>
+ *
+ *****************************************************************************/
+
+#ifndef __ODM_REGDEFINE11N_H__
+#define __ODM_REGDEFINE11N_H__
+
+/* @2 RF REG LIST */
+#define	ODM_REG_RF_MODE_11N			0x00
+#define	ODM_REG_RF_0B_11N			0x0B
+#define	ODM_REG_CHNBW_11N			0x18
+#define	ODM_REG_T_METER_11N			0x24
+#define	ODM_REG_RF_25_11N			0x25
+#define	ODM_REG_RF_26_11N			0x26
+#define	ODM_REG_RF_27_11N			0x27
+#define	ODM_REG_RF_2B_11N			0x2B
+#define	ODM_REG_RF_2C_11N			0x2C
+#define	ODM_REG_RXRF_A3_11N			0x3C
+#define	ODM_REG_T_METER_92D_11N			0x42
+#define	ODM_REG_T_METER_88E_11N			0x42
+
+
+
+/* @2 BB REG LIST
+ * PAGE 8
+ */
+#define	ODM_REG_BB_CTRL_11N			0x800
+#define	ODM_REG_RF_PIN_11N			0x804
+#define	ODM_REG_PSD_CTRL_11N			0x808
+#define	ODM_REG_TX_ANT_CTRL_11N			0x80C
+#define	ODM_REG_BB_PWR_SAV5_11N			0x818
+#define	ODM_REG_CCK_RPT_FORMAT_11N		0x824
+#define	ODM_REG_CCK_RPT_FORMAT_11N_B		0x82C
+#define	ODM_REG_RX_DEFAULT_A_11N		0x858
+#define	ODM_REG_RX_DEFAULT_B_11N		0x85A
+#define	ODM_REG_BB_PWR_SAV3_11N			0x85C
+#define	ODM_REG_ANTSEL_CTRL_11N			0x860
+#define	ODM_REG_RX_ANT_CTRL_11N			0x864
+#define	ODM_REG_PIN_CTRL_11N			0x870
+#define	ODM_REG_BB_PWR_SAV1_11N			0x874
+#define	ODM_REG_ANTSEL_PATH_11N			0x878
+#define	ODM_REG_BB_3WIRE_11N			0x88C
+#define	ODM_REG_SC_CNT_11N			0x8C4
+#define	ODM_REG_PSD_DATA_11N			0x8B4
+#define	ODM_REG_CCX_PERIOD_11N			0x894
+#define	ODM_REG_NHM_TH9_TH10_11N		0x890
+#define	ODM_REG_CLM_11N				0x890
+#define	ODM_REG_NHM_TH3_TO_TH0_11N		0x898
+#define	ODM_REG_NHM_TH7_TO_TH4_11N		0x89c
+#define ODM_REG_NHM_TH8_11N			0xe28
+#define	ODM_REG_CLM_READY_11N			0x8b4
+#define	ODM_REG_CLM_RESULT_11N			0x8d0
+#define	ODM_REG_NHM_CNT_11N			0x8d8
+
+/* @For struct acs_info, Jeffery, 2014-12-26 */
+#define	ODM_REG_NHM_CNT7_TO_CNT4_11N		0x8dc
+#define	ODM_REG_NHM_CNT9_TO_CNT8_11N		0x8d0
+#define	ODM_REG_NHM_CNT10_TO_CNT11_11N		0x8d4
+
+/* PAGE 9 */
+#define	ODM_REG_BB_CTRL_PAGE9_11N		0x900
+#define	ODM_REG_DBG_RPT_11N			0x908
+#define	ODM_REG_BB_TX_PATH_11N			0x90c
+#define	ODM_REG_ANT_MAPPING1_11N		0x914
+#define	ODM_REG_ANT_MAPPING2_11N		0x918
+#define	ODM_REG_EDCCA_DOWN_OPT_11N		0x948
+#define	ODM_REG_RX_DFIR_MOD_97F			0x948
+#define	ODM_REG_SOML_97F			0x998
+
+/* PAGE A */
+#define	ODM_REG_CCK_ANTDIV_PARA1_11N		0xA00
+#define	ODM_REG_CCK_ANT_SEL_11N			0xA04
+#define	ODM_REG_CCK_CCA_11N			0xA0A
+#define	ODM_REG_CCK_ANTDIV_PARA2_11N		0xA0C
+#define	ODM_REG_CCK_ANTDIV_PARA3_11N		0xA10
+#define	ODM_REG_CCK_ANTDIV_PARA4_11N		0xA14
+#define	ODM_REG_CCK_FILTER_PARA1_11N		0xA22
+#define	ODM_REG_CCK_FILTER_PARA2_11N		0xA23
+#define	ODM_REG_CCK_FILTER_PARA3_11N		0xA24
+#define	ODM_REG_CCK_FILTER_PARA4_11N		0xA25
+#define	ODM_REG_CCK_FILTER_PARA5_11N		0xA26
+#define	ODM_REG_CCK_FILTER_PARA6_11N		0xA27
+#define	ODM_REG_CCK_FILTER_PARA7_11N		0xA28
+#define	ODM_REG_CCK_FILTER_PARA8_11N		0xA29
+#define	ODM_REG_CCK_FA_RST_11N			0xA2C
+#define	ODM_REG_CCK_FA_MSB_11N			0xA58
+#define	ODM_REG_CCK_FA_LSB_11N			0xA5C
+#define	ODM_REG_CCK_CCA_CNT_11N			0xA60
+#define	ODM_REG_BB_PWR_SAV4_11N			0xA74
+/* PAGE B */
+#define	ODM_REG_LNA_SWITCH_11N			0xB2C
+#define	ODM_REG_PATH_SWITCH_11N			0xB30
+#define	ODM_REG_RSSI_CTRL_11N			0xB38
+#define	ODM_REG_CONFIG_ANTA_11N			0xB68
+#define	ODM_REG_RSSI_BT_11N			0xB9C
+#define	ODM_REG_RXCK_RFMOD			0xBB0
+#define	ODM_REG_EDCCA_DCNF_97F			0xBC0
+
+/* PAGE C */
+#define	ODM_REG_OFDM_FA_HOLDC_11N		0xC00
+#define	ODM_REG_BB_RX_PATH_11N			0xC04
+#define	ODM_REG_TRMUX_11N			0xC08
+#define	ODM_REG_OFDM_FA_RSTC_11N		0xC0C
+#define	ODM_REG_DOWNSAM_FACTOR_11N		0xC10
+#define	ODM_REG_RXIQI_MATRIX_11N		0xC14
+#define	ODM_REG_TXIQK_MATRIX_LSB1_11N		0xC4C
+#define	ODM_REG_IGI_A_11N			0xC50
+#define	ODM_REG_ANTDIV_PARA2_11N		0xC54
+#define	ODM_REG_IGI_B_11N			0xC58
+#define	ODM_REG_ANTDIV_PARA3_11N		0xC5C
+#define   ODM_REG_L1SBD_PD_CH_11N		0XC6C
+#define	ODM_REG_BB_PWR_SAV2_11N			0xC70
+#define	ODM_REG_BB_AGC_SET_2_11N		0xc74
+#define	ODM_REG_RX_OFF_11N			0xC7C
+#define	ODM_REG_TXIQK_MATRIXA_11N		0xC80
+#define	ODM_REG_TXIQK_MATRIXB_11N		0xC88
+#define	ODM_REG_TXIQK_MATRIXA_LSB2_11N		0xC94
+#define	ODM_REG_TXIQK_MATRIXB_LSB2_11N		0xC9C
+#define	ODM_REG_RXIQK_MATRIX_LSB_11N		0xCA0
+#define	ODM_REG_ANTDIV_PARA1_11N		0xCA4
+#define	ODM_REG_SMALL_BANDWIDTH_11N		0xCE4
+#define	ODM_REG_OFDM_FA_TYPE1_11N		0xCF0
+/* PAGE D */
+#define	ODM_REG_OFDM_FA_RSTD_11N		0xD00
+#define	ODM_REG_BB_RX_ANT_11N			0xD04
+#define	ODM_REG_BB_ATC_11N			0xD2C
+#define	ODM_REG_OFDM_FA_TYPE2_11N		0xDA0
+#define	ODM_REG_OFDM_FA_TYPE3_11N		0xDA4
+#define	ODM_REG_OFDM_FA_TYPE4_11N		0xDA8
+#define	ODM_REG_RPT_11N				0xDF4
+/* PAGE E */
+#define	ODM_REG_TXAGC_A_6_18_11N		0xE00
+#define	ODM_REG_TXAGC_A_24_54_11N		0xE04
+#define	ODM_REG_TXAGC_A_1_MCS32_11N		0xE08
+#define	ODM_REG_TXAGC_A_MCS0_3_11N		0xE10
+#define	ODM_REG_TXAGC_A_MCS4_7_11N		0xE14
+#define	ODM_REG_TXAGC_A_MCS8_11_11N		0xE18
+#define	ODM_REG_TXAGC_A_MCS12_15_11N		0xE1C
+#define	ODM_REG_EDCCA_DCNF_11N			0xE24
+#define	ODM_REG_TAP_UPD_97F			0xE24
+#define	ODM_REG_FPGA0_IQK_11N			0xE28
+#define	ODM_REG_PAGE_B1_97F			0xE28
+#define	ODM_REG_TXIQK_TONE_A_11N		0xE30
+#define	ODM_REG_RXIQK_TONE_A_11N		0xE34
+#define	ODM_REG_TXIQK_PI_A_11N			0xE38
+#define	ODM_REG_RXIQK_PI_A_11N			0xE3C
+#define	ODM_REG_TXIQK_11N			0xE40
+#define	ODM_REG_RXIQK_11N			0xE44
+#define	ODM_REG_IQK_AGC_PTS_11N			0xE48
+#define	ODM_REG_IQK_AGC_RSP_11N			0xE4C
+#define	ODM_REG_BLUETOOTH_11N			0xE6C
+#define	ODM_REG_RX_WAIT_CCA_11N			0xE70
+#define	ODM_REG_TX_CCK_RFON_11N			0xE74
+#define	ODM_REG_TX_CCK_BBON_11N			0xE78
+#define	ODM_REG_OFDM_RFON_11N			0xE7C
+#define	ODM_REG_OFDM_BBON_11N			0xE80
+#define	ODM_REG_TX2RX_11N			0xE84
+#define	ODM_REG_TX2TX_11N			0xE88
+#define	ODM_REG_RX_CCK_11N			0xE8C
+#define	ODM_REG_RX_OFDM_11N			0xED0
+#define	ODM_REG_RX_WAIT_RIFS_11N		0xED4
+#define	ODM_REG_RX2RX_11N			0xED8
+#define	ODM_REG_STANDBY_11N			0xEDC
+#define	ODM_REG_SLEEP_11N			0xEE0
+#define	ODM_REG_PMPD_ANAEN_11N			0xEEC
+/* PAGE F */
+#define	ODM_REG_PAGE_F_RST_11N			0xF14
+#define	ODM_REG_IGI_C_11N			0xF84
+#define	ODM_REG_IGI_D_11N			0xF88
+#define	ODM_REG_CCK_CRC32_ERROR_CNT_11N		0xF84
+#define	ODM_REG_CCK_CRC32_OK_CNT_11N		0xF88
+#define	ODM_REG_HT_CRC32_CNT_11N		0xF90
+#define	ODM_REG_OFDM_CRC32_CNT_11N		0xF94
+#define	ODM_REG_HT_CRC32_CNT_11N_AGG		0xFB8
+
+/* @2 MAC REG LIST */
+#define	ODM_REG_BB_RST_11N			0x02
+#define	ODM_REG_ANTSEL_PIN_11N			0x4C
+#define	ODM_REG_EARLY_MODE_11N			0x4D0
+#define	ODM_REG_RSSI_MONITOR_11N		0x4FE
+#define	ODM_REG_EDCA_VO_11N			0x500
+#define	ODM_REG_EDCA_VI_11N			0x504
+#define	ODM_REG_EDCA_BE_11N			0x508
+#define	ODM_REG_EDCA_BK_11N			0x50C
+#define	ODM_REG_TXPAUSE_11N			0x522
+#define	ODM_REG_RESP_TX_11N			0x6D8
+#define	ODM_REG_ANT_TRAIN_PARA1_11N		0x7b0
+#define	ODM_REG_ANT_TRAIN_PARA2_11N		0x7b4
+
+
+/* @DIG Related */
+#define	ODM_BIT_IGI_11N				0x0000007F
+#define	ODM_BIT_CCK_RPT_FORMAT_11N		BIT(9)
+#define	ODM_BIT_BB_RX_PATH_11N			0xF
+#define	ODM_BIT_BB_TX_PATH_11N			0xF
+#define	ODM_BIT_BB_ATC_11N			BIT(11)
+#endif
+
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/phydm_reg.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/phydm_reg.h
--- linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/phydm_reg.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/phydm_reg.h	2020-04-10 16:35:06.827660581 +0300
@@ -0,0 +1,241 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017  Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * The full GNU General Public License is included in this distribution in the
+ * file called LICENSE.
+ *
+ * Contact Information:
+ * wlanfae <wlanfae@realtek.com>
+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
+ * Hsinchu 300, Taiwan.
+ *
+ * Larry Finger <Larry.Finger@lwfinger.net>
+ *
+ *****************************************************************************/
+/*************************************************************
+ * File Name: odm_reg.h
+ *
+ * Description:
+ *
+ * This file is for general register definition.
+ *
+ *
+ ************************************************************/
+#ifndef __HAL_ODM_REG_H__
+#define __HAL_ODM_REG_H__
+
+/*@
+ * Register Definition
+ *
+ */
+
+/* @MAC REG */
+#define	ODM_BB_RESET				0x002
+#define	ODM_DUMMY				0x4fe
+#define	RF_T_METER_OLD				0x24
+#define	RF_T_METER_NEW				0x42
+
+#define	ODM_EDCA_VO_PARAM			0x500
+#define	ODM_EDCA_VI_PARAM			0x504
+#define	ODM_EDCA_BE_PARAM			0x508
+#define	ODM_EDCA_BK_PARAM			0x50C
+#define	ODM_TXPAUSE				0x522
+
+/* @LTE_COEX */
+#define REG_LTECOEX_CTRL			0x07C0
+#define REG_LTECOEX_WRITE_DATA			0x07C4
+#define REG_LTECOEX_READ_DATA			0x07C8
+#define REG_LTECOEX_PATH_CONTROL		0x70
+
+/* @BB REG */
+#define	ODM_FPGA_PHY0_PAGE8			0x800
+#define	ODM_PSD_SETTING				0x808
+#define	ODM_AFE_SETTING				0x818
+#define	ODM_TXAGC_B_6_18			0x830
+#define	ODM_TXAGC_B_24_54			0x834
+#define	ODM_TXAGC_B_MCS32_5			0x838
+#define	ODM_TXAGC_B_MCS0_MCS3			0x83c
+#define	ODM_TXAGC_B_MCS4_MCS7			0x848
+#define	ODM_TXAGC_B_MCS8_MCS11			0x84c
+#define	ODM_ANALOG_REGISTER			0x85c
+#define	ODM_RF_INTERFACE_OUTPUT			0x860
+#define	ODM_TXAGC_B_MCS12_MCS15			0x868
+#define	ODM_TXAGC_B_11_A_2_11			0x86c
+#define	ODM_AD_DA_LSB_MASK			0x874
+#define	ODM_ENABLE_3_WIRE			0x88c
+#define	ODM_PSD_REPORT				0x8b4
+#define	ODM_R_ANT_SELECT			0x90c
+#define	ODM_CCK_ANT_SELECT			0xa07
+#define	ODM_CCK_PD_THRESH			0xa0a
+#define	ODM_CCK_RF_REG1				0xa11
+#define	ODM_CCK_MATCH_FILTER			0xa20
+#define	ODM_CCK_RAKE_MAC			0xa2e
+#define	ODM_CCK_CNT_RESET			0xa2d
+#define	ODM_CCK_TX_DIVERSITY			0xa2f
+#define	ODM_CCK_FA_CNT_MSB			0xa5b
+#define	ODM_CCK_FA_CNT_LSB			0xa5c
+#define	ODM_CCK_NEW_FUNCTION			0xa75
+#define	ODM_OFDM_PHY0_PAGE_C			0xc00
+#define	ODM_OFDM_RX_ANT				0xc04
+#define	ODM_R_A_RXIQI				0xc14
+#define	ODM_R_A_AGC_CORE1			0xc50
+#define	ODM_R_A_AGC_CORE2			0xc54
+#define	ODM_R_B_AGC_CORE1			0xc58
+#define	ODM_R_AGC_PAR				0xc70
+#define	ODM_R_HTSTF_AGC_PAR			0xc7c
+#define	ODM_TX_PWR_TRAINING_A			0xc90
+#define	ODM_TX_PWR_TRAINING_B			0xc98
+#define	ODM_OFDM_FA_CNT1			0xcf0
+#define	ODM_OFDM_PHY0_PAGE_D			0xd00
+#define	ODM_OFDM_FA_CNT2			0xda0
+#define	ODM_OFDM_FA_CNT3			0xda4
+#define	ODM_OFDM_FA_CNT4			0xda8
+#define	ODM_TXAGC_A_6_18			0xe00
+#define	ODM_TXAGC_A_24_54			0xe04
+#define	ODM_TXAGC_A_1_MCS32			0xe08
+#define	ODM_TXAGC_A_MCS0_MCS3			0xe10
+#define	ODM_TXAGC_A_MCS4_MCS7			0xe14
+#define	ODM_TXAGC_A_MCS8_MCS11			0xe18
+#define	ODM_TXAGC_A_MCS12_MCS15			0xe1c
+
+/* RF REG */
+#define	ODM_GAIN_SETTING			0x00
+#define	ODM_CHANNEL				0x18
+#define	ODM_RF_T_METER				0x24
+#define	ODM_RF_T_METER_92D			0x42
+#define	ODM_RF_T_METER_88E			0x42
+#define	ODM_RF_T_METER_92E			0x42
+#define	ODM_RF_T_METER_8812			0x42
+#define	REG_RF_TX_GAIN_OFFSET			0x55
+
+/* @ant Detect Reg */
+#define	ODM_DPDT				0x300
+
+/* PSD Init */
+#define	ODM_PSDREG				0x808
+
+/* @92D path Div */
+#define	PATHDIV_REG				0xB30
+#define	PATHDIV_TRI				0xBA0
+
+
+/*@
+ * Bitmap Definition
+ */
+#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
+	/* TX AGC */
+	#define		REG_TX_AGC_A_CCK_11_CCK_1_JAGUAR		0xc20
+	#define		REG_TX_AGC_A_OFDM18_OFDM6_JAGUAR		0xc24
+	#define		REG_TX_AGC_A_OFDM54_OFDM24_JAGUAR		0xc28
+	#define		REG_TX_AGC_A_MCS3_MCS0_JAGUAR			0xc2c
+	#define		REG_TX_AGC_A_MCS7_MCS4_JAGUAR			0xc30
+	#define		REG_TX_AGC_A_MCS11_MCS8_JAGUAR			0xc34
+	#define		REG_TX_AGC_A_MCS15_MCS12_JAGUAR			0xc38
+	#define		REG_TX_AGC_A_NSS1_INDEX3_NSS1_INDEX0_JAGUAR	0xc3c
+	#define		REG_TX_AGC_A_NSS1_INDEX7_NSS1_INDEX4_JAGUAR	0xc40
+	#define		REG_TX_AGC_A_NSS2_INDEX1_NSS1_INDEX8_JAGUAR	0xc44
+	#define		REG_TX_AGC_A_NSS2_INDEX5_NSS2_INDEX2_JAGUAR	0xc48
+	#define		REG_TX_AGC_A_NSS2_INDEX9_NSS2_INDEX6_JAGUAR	0xc4c
+	#if defined(CONFIG_WLAN_HAL_8814AE)
+		#define		REG_TX_AGC_A_MCS19_MCS16_JAGUAR		0xcd8
+		#define		REG_TX_AGC_A_MCS23_MCS20_JAGUAR		0xcdc
+		#define		REG_TX_AGC_A_NSS3_INDEX3_NSS3_INDEX0_JAGUAR	0xce0
+		#define		REG_TX_AGC_A_NSS3_INDEX7_NSS3_INDEX4_JAGUAR	0xce4
+		#define		REG_TX_AGC_A_NSS3_INDEX9_NSS3_INDEX8_JAGUAR	0xce8
+	#endif
+	#define		REG_TX_AGC_B_CCK_11_CCK_1_JAGUAR		0xe20
+	#define		REG_TX_AGC_B_OFDM18_OFDM6_JAGUAR		0xe24
+	#define		REG_TX_AGC_B_OFDM54_OFDM24_JAGUAR		0xe28
+	#define		REG_TX_AGC_B_MCS3_MCS0_JAGUAR			0xe2c
+	#define		REG_TX_AGC_B_MCS7_MCS4_JAGUAR			0xe30
+	#define		REG_TX_AGC_B_MCS11_MCS8_JAGUAR			0xe34
+	#define		REG_TX_AGC_B_MCS15_MCS12_JAGUAR			0xe38
+	#define		REG_TX_AGC_B_NSS1_INDEX3_NSS1_INDEX0_JAGUAR	0xe3c
+	#define		REG_TX_AGC_B_NSS1_INDEX7_NSS1_INDEX4_JAGUAR	0xe40
+	#define		REG_TX_AGC_B_NSS2_INDEX1_NSS1_INDEX8_JAGUAR	0xe44
+	#define		REG_TX_AGC_B_NSS2_INDEX5_NSS2_INDEX2_JAGUAR	0xe48
+	#define		REG_TX_AGC_B_NSS2_INDEX9_NSS2_INDEX6_JAGUAR	0xe4c
+	#if defined(CONFIG_WLAN_HAL_8814AE)
+		#define		REG_TX_AGC_B_MCS19_MCS16_JAGUAR		0xed8
+		#define		REG_TX_AGC_B_MCS23_MCS20_JAGUAR		0xedc
+		#define		REG_TX_AGC_B_NSS3_INDEX3_NSS3_INDEX0_JAGUAR	0xee0
+		#define		REG_TX_AGC_B_NSS3_INDEX7_NSS3_INDEX4_JAGUAR	0xee4
+		#define		REG_TX_AGC_B_NSS3_INDEX9_NSS3_INDEX8_JAGUAR	0xee8
+		#define		REG_TX_AGC_C_CCK_11_CCK_1_JAGUAR	0x1820
+		#define		REG_TX_AGC_C_OFDM18_OFDM6_JAGUAR	0x1824
+		#define		REG_TX_AGC_C_OFDM54_OFDM24_JAGUAR	0x1828
+		#define		REG_TX_AGC_C_MCS3_MCS0_JAGUAR		0x182c
+		#define		REG_TX_AGC_C_MCS7_MCS4_JAGUAR		0x1830
+		#define		REG_TX_AGC_C_MCS11_MCS8_JAGUAR		0x1834
+		#define		REG_TX_AGC_C_MCS15_MCS12_JAGUAR		0x1838
+		#define		REG_TX_AGC_C_NSS1_INDEX3_NSS1_INDEX0_JAGUAR	0x183c
+		#define		REG_TX_AGC_C_NSS1_INDEX7_NSS1_INDEX4_JAGUAR	0x1840
+		#define		REG_TX_AGC_C_NSS2_INDEX1_NSS1_INDEX8_JAGUAR	0x1844
+		#define		REG_TX_AGC_C_NSS2_INDEX5_NSS2_INDEX2_JAGUAR	0x1848
+		#define		REG_TX_AGC_C_NSS2_INDEX9_NSS2_INDEX6_JAGUAR	0x184c
+		#define		REG_TX_AGC_C_MCS19_MCS16_JAGUAR		0x18d8
+		#define		REG_TX_AGC_C_MCS23_MCS20_JAGUAR		0x18dc
+		#define		REG_TX_AGC_C_NSS3_INDEX3_NSS3_INDEX0_JAGUAR	0x18e0
+		#define		REG_TX_AGC_C_NSS3_INDEX7_NSS3_INDEX4_JAGUAR	0x18e4
+		#define		REG_TX_AGC_C_NSS3_INDEX9_NSS3_INDEX8_JAGUAR	0x18e8
+		#define		REG_TX_AGC_D_CCK_11_CCK_1_JAGUAR	0x1a20
+		#define		REG_TX_AGC_D_OFDM18_OFDM6_JAGUAR	0x1a24
+		#define		REG_TX_AGC_D_OFDM54_OFDM24_JAGUAR	0x1a28
+		#define		REG_TX_AGC_D_MCS3_MCS0_JAGUAR		0x1a2c
+		#define		REG_TX_AGC_D_MCS7_MCS4_JAGUAR		0x1a30
+		#define		REG_TX_AGC_D_MCS11_MCS8_JAGUAR		0x1a34
+		#define		REG_TX_AGC_D_MCS15_MCS12_JAGUAR		0x1a38
+		#define		REG_TX_AGC_D_NSS1_INDEX3_NSS1_INDEX0_JAGUAR	0x1a3c
+		#define		REG_TX_AGC_D_NSS1_INDEX7_NSS1_INDEX4_JAGUAR	0x1a40
+		#define		REG_TX_AGC_D_NSS2_INDEX1_NSS1_INDEX8_JAGUAR	0x1a44
+		#define		REG_TX_AGC_D_NSS2_INDEX5_NSS2_INDEX2_JAGUAR	0x1a48
+		#define		REG_TX_AGC_D_NSS2_INDEX9_NSS2_INDEX6_JAGUAR	0x1a4c
+		#define		REG_TX_AGC_D_MCS19_MCS16_JAGUAR		0x1ad8
+		#define		REG_TX_AGC_D_MCS23_MCS20_JAGUAR		0x1adc
+		#define		REG_TX_AGC_D_NSS3_INDEX3_NSS3_INDEX0_JAGUAR	0x1ae0
+		#define		REG_TX_AGC_D_NSS3_INDEX7_NSS3_INDEX4_JAGUAR	0x1ae4
+		#define		REG_TX_AGC_D_NSS3_INDEX9_NSS3_INDEX8_JAGUAR	0x1ae8
+	#endif
+
+	#define		is_tx_agc_byte0_jaguar	0xff
+	#define		is_tx_agc_byte1_jaguar	0xff00
+	#define		is_tx_agc_byte2_jaguar	0xff0000
+	#define		is_tx_agc_byte3_jaguar	0xff000000
+	#if defined(CONFIG_WLAN_HAL_8198F)
+		#define REG_TX_AGC_CCK_11_CCK_1_JAGUAR3		0x3a00
+		#define REG_TX_AGC_OFDM_18_CCK_6_JAGUAR3	0x3a04
+		#define	REG_TX_AGC_OFDM_54_CCK_24_JAGUAR3	0x3a08
+		#define	REG_TX_AGC_MCS3_0_JAGUAR3		0x3a0c
+		#define	REG_TX_AGC_MCS7_4_JAGUAR3		0x3a10
+		#define	REG_TX_AGC_MCS11_8_JAGUAR3		0x3a14
+		#define	REG_TX_AGC_MCS15_12_JAGUAR3		0x3a18
+		#define	REG_TX_AGC_MCS19_16_JAGUAR3		0x3a1c
+		#define	REG_TX_AGC_MCS23_20_JAGUAR3		0x3a20
+		#define	REG_TX_AGC_MCS27_24_JAGUAR3		0x3a24
+		#define	REG_TX_AGC_MCS31_28_JAGUAR3		0x3a28
+		#define	REG_TX_AGC_VHT_Nss1_MCS3_0_JAGUAR3	0x3a2c
+		#define	REG_TX_AGC_VHT_Nss1_MCS7_4_JAGUAR3	0x3a30
+		#define	REG_TX_AGC_VHT_NSS2_MCS1_NSS1_MCS8_JAGUAR3	0x3a34
+		#define	REG_TX_AGC_VHT_Nss2_MCS5_2_JAGUAR3	0x3a38
+		#define	REG_TX_AGC_VHT_Nss2_MCS9_6_JAGUAR3	0x3a3c
+		#define	REG_TX_AGC_VHT_Nss3_MCS3_0_JAGUAR3	0x3a40
+		#define	REG_TX_AGC_VHT_Nss3_MCS7_4_JAGUAR3	0x3a44
+		#define	REG_TX_AGC_VHT_Nss4_MCS1_Nss3_MCS8_JAGUAR3	0x3a48
+		#define	REG_TX_AGC_VHT_Nss4_MCS5_2_JAGUAR3	0x3a4c
+		#define	REG_TX_AGC_VHT_Nss4_MCS9_6_JAGUAR3	0x3a50
+	#endif
+#endif
+
+#define	BIT_FA_RESET					BIT(0)
+
+#endif
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/phydm_regtable.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/phydm_regtable.h
--- linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/phydm_regtable.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/phydm_regtable.h	2020-04-10 16:35:06.827660581 +0300
@@ -0,0 +1,725 @@
+#define R_0x0 0x0
+#define R_0x00 0x00
+#define R_0x0106 0x0106
+#define R_0x0140 0x0140
+#define R_0x0144 0x0144
+#define R_0x0148 0x0148
+#define R_0x040 0x040
+#define R_0x10 0x10
+#define R_0x100 0x100
+#define R_0x1038 0x1038
+#define R_0x103c 0x103c
+#define R_0x1040 0x1040
+#define R_0x1048 0x1048
+#define R_0x1080 0x1080
+#define R_0x14c0 0x14c0
+#define R_0x14c4 0x14c4
+#define R_0x14c8 0x14c8
+#define R_0x14cc 0x14cc
+#define R_0x1518 0x1518
+#define R_0x1684 0x1684
+#define R_0x1688 0x1688
+#define R_0x168c 0x168c
+#define R_0x1700 0x1700
+#define R_0x1704 0x1704
+#define R_0x1800 0x1800
+#define R_0x1830 0x1830
+#define R_0x1838 0x1838
+#define R_0x183c 0x183c
+#define R_0x1840 0x1840
+#define R_0x1844 0x1844
+#define R_0x1848 0x1848
+#define R_0x186c 0x186c
+#define R_0x1870 0x1870
+#define R_0x1884 0x1884
+#define R_0x188c 0x188c
+#define R_0x1894 0x1894
+#define R_0x18a0 0x18a0
+#define R_0x18a4 0x18a4
+#define R_0x18ac 0x18ac
+#define R_0x1900 0x1900
+#define R_0x1904 0x1904
+#define R_0x1908 0x1908
+#define R_0x1918 0x1918
+#define R_0x191c 0x191c
+#define R_0x1928 0x1928
+#define R_0x1940 0x1940
+#define R_0x1944 0x1944
+#define R_0x1950 0x1950
+#define R_0x1954 0x1954
+#define R_0x195c 0x195c
+#define R_0x1970 0x1970
+#define R_0x1984 0x1984
+#define R_0x1988 0x1988
+#define R_0x198c 0x198c
+#define R_0x1990 0x1990
+#define R_0x1991 0x1991
+#define R_0x1998 0x1998
+#define R_0x19a8 0x19a8
+#define R_0x19d4 0x19d4
+#define R_0x19d8 0x19d8
+#define R_0x19e0 0x19e0
+#define R_0x19f0 0x19f0
+#define R_0x19f8 0x19f8
+#define R_0x1a00 0x1a00
+#define R_0x1a04 0x1a04
+#define R_0x1a14 0x1a14
+#define R_0x1a24 0x1a24
+#define R_0x1a28 0x1a28
+#define R_0x1a2c 0x1a2c
+#define R_0x1a5c 0x1a5c
+#define R_0x1a70 0x1a70
+#define R_0x1a80 0x1a80
+#define R_0x1a84 0x1a84
+#define R_0x1a8c 0x1a8c
+#define R_0x1a94 0x1a94
+#define R_0x1a9c 0x1a9c
+#define R_0x1aac 0x1aac
+#define R_0x1abc 0x1abc
+#define R_0x1ac0 0x1ac0
+#define R_0x1ac8 0x1ac8
+#define R_0x1acc 0x1acc
+#define R_0x1ad0 0x1ad0
+#define R_0x1ad4 0x1ad4
+#define R_0x1b00 0x1b00
+#define R_0x1b08 0x1b08
+#define R_0x1b0c 0x1b0c
+#define R_0x1b20 0x1b20
+#define R_0x1b2c 0x1b2c
+#define R_0x1b38 0x1b38
+#define R_0x1b3c 0x1b3c
+#define R_0x1b40 0x1b40
+#define R_0x1b44 0x1b44
+#define R_0x1b48 0x1b48
+#define R_0x1b4c 0x1b4c
+#define R_0x1b50 0x1b50
+#define R_0x1b54 0x1b54
+#define R_0x1b58 0x1b58
+#define R_0x1b5c 0x1b5c
+#define R_0x1b60 0x1b60
+#define R_0x1b64 0x1b64
+#define R_0x1b68 0x1b68
+#define R_0x1b6c 0x1b6c
+#define R_0x1b70 0x1b70
+#define R_0x1b74 0x1b74
+#define R_0x1b78 0x1b78
+#define R_0x1b7c 0x1b7c
+#define R_0x1b80 0x1b80
+#define R_0x1b8c 0x1b8c
+#define R_0x1b90 0x1b90
+#define R_0x1b92 0x1b92
+#define R_0x1b94 0x1b94
+#define R_0x1b98 0x1b98
+#define R_0x1b9c 0x1b9c
+#define R_0x1ba0 0x1ba0
+#define R_0x1ba4 0x1ba4
+#define R_0x1ba8 0x1ba8
+#define R_0x1bac 0x1bac
+#define R_0x1bb0 0x1bb0
+#define R_0x1bb4 0x1bb4
+#define R_0x1bb8 0x1bb8
+#define R_0x1bbc 0x1bbc
+#define R_0x1bc8 0x1bc8
+#define R_0x1bcc 0x1bcc
+#define R_0x1bd0 0x1bd0
+#define R_0x1bd4 0x1bd4
+#define R_0x1bd8 0x1bd8
+#define R_0x1bdc 0x1bdc
+#define R_0x1bf0 0x1bf0
+#define R_0x1bfc 0x1bfc
+#define R_0x1c28 0x1c28
+#define R_0x1c2c 0x1c2c
+#define R_0x1c30 0x1c30
+#define R_0x1c38 0x1c38
+#define R_0x1c3c 0x1c3c
+#define R_0x1c68 0x1c68
+#define R_0x1c74 0x1c74
+#define R_0x1c78 0x1c78
+#define R_0x1c7c 0x1c7c
+#define R_0x1c80 0x1c80
+#define R_0x1c90 0x1c90
+#define R_0x1c94 0x1c94
+#define R_0x1c98 0x1c98
+#define R_0x1c9c 0x1c9c
+#define R_0x1ca0 0x1ca0
+#define R_0x1ca4 0x1ca4
+#define R_0x1cb8 0x1cb8
+#define R_0x1cd0 0x1cd0
+#define R_0x1ce4 0x1ce4
+#define R_0x1ce8 0x1ce8
+#define R_0x1cec 0x1cec
+#define R_0x1cf0 0x1cf0
+#define R_0x1cf4 0x1cf4
+#define R_0x1cf8 0x1cf8
+#define R_0x1d08 0x1d08
+#define R_0x1d0c 0x1d0c
+#define R_0x1d30 0x1d30
+#define R_0x1d44 0x1d44
+#define R_0x1d48 0x1d48
+#define R_0x1d60 0x1d60
+#define R_0x1d6c 0x1d6c
+#define R_0x1d70 0x1d70
+#define R_0x1d94 0x1d94
+#define R_0x1d9c 0x1d9c
+#define R_0x1da4 0x1da4
+#define R_0x1da8 0x1da8
+#define R_0x1e14 0x1e14
+#define R_0x1e18 0x1e18
+#define R_0x1e24 0x1e24
+#define R_0x1e2c 0x1e2c
+#define R_0x1e30 0x1e30
+#define R_0x1e40 0x1e40
+#define R_0x1e44 0x1e44
+#define R_0x1e48 0x1e48
+#define R_0x1e5c 0x1e5c
+#define R_0x1e60 0x1e60
+#define R_0x1e64 0x1e64
+#define R_0x1e68 0x1e68
+#define R_0x1e6c 0x1e6c
+#define R_0x1e70 0x1e70
+#define R_0x1ea4 0x1ea4
+#define R_0x1eb4 0x1eb4
+#define R_0x1ee8 0x1ee8
+#define R_0x24 0x24
+#define R_0x28 0x28
+#define R_0x2c 0x2c
+#define R_0x2c04 0x2c04
+#define R_0x2c08 0x2c08
+#define R_0x2c0c 0x2c0c
+#define R_0x2c10 0x2c10
+#define R_0x2c14 0x2c14
+#define R_0x2c20 0x2c20
+#define R_0x2c2c 0x2c2c
+#define R_0x2c30 0x2c30
+#define R_0x2c34 0x2c34
+#define R_0x2d00 0x2d00
+#define R_0x2d04 0x2d04
+#define R_0x2d08 0x2d08
+#define R_0x2d0c 0x2d0c
+#define R_0x2d10 0x2d10
+#define R_0x2d20 0x2d20
+#define R_0x2d38 0x2d38
+#define R_0x2d40 0x2d40
+#define R_0x2d44 0x2d44
+#define R_0x2d48 0x2d48
+#define R_0x2d4c 0x2d4c
+#define R_0x2d88 0x2d88
+#define R_0x2dbc 0x2dbc
+#define R_0x2de0 0x2de0
+#define R_0x2de4 0x2de4
+#define R_0x2de8 0x2de8
+#define R_0x300 0x300
+#define R_0x38 0x38
+#define R_0x40 0x40
+#define R_0x4000 0x4000
+#define R_0x4008 0x4008
+#define R_0x4018 0x4018
+#define R_0x401c 0x401c
+#define R_0x4028 0x4028
+#define R_0x4040 0x4040
+#define R_0x4044 0x4044
+#define R_0x4100 0x4100
+#define R_0x4130 0x4130
+#define R_0x413c 0x413c
+#define R_0x4140 0x4140
+#define R_0x4144 0x4144
+#define R_0x4148 0x4148
+#define R_0x41a0 0x41a0
+#define R_0x41a4 0x41a4
+#define R_0x41ac 0x41ac
+#define R_0x42 0x42
+#define R_0x430 0x430
+#define R_0x434 0x434
+#define R_0x44 0x44
+#define R_0x444 0x444
+#define R_0x448 0x448
+#define R_0x450 0x450
+#define R_0x454 0x454
+#define R_0x49c 0x49c
+#define R_0x4a0 0x4a0
+#define R_0x4a4 0x4a4
+#define R_0x4a8 0x4a8
+#define R_0x4c 0x4c
+#define R_0x4c8 0x4c8
+#define R_0x4cc 0x4cc
+#define R_0x5000 0x5000
+#define R_0x5008 0x5008
+#define R_0x5018 0x5018
+#define R_0x501c 0x501c
+#define R_0x5028 0x5028
+#define R_0x5040 0x5040
+#define R_0x5044 0x5044
+#define R_0x5100 0x5100
+#define R_0x5108 0x5108
+#define R_0x5118 0x5118
+#define R_0x511c 0x511c
+#define R_0x5128 0x5128
+#define R_0x5140 0x5140
+#define R_0x5144 0x5144
+#define R_0x520 0x520
+#define R_0x5200 0x5200
+#define R_0x522 0x522
+#define R_0x5230 0x5230
+#define R_0x523c 0x523c
+#define R_0x5240 0x5240
+#define R_0x5244 0x5244
+#define R_0x5248 0x5248
+#define R_0x52a0 0x52a0
+#define R_0x52a4 0x52a4
+#define R_0x52ac 0x52ac
+#define R_0x5300 0x5300
+#define R_0x5330 0x5330
+#define R_0x533c 0x533c
+#define R_0x5340 0x5340
+#define R_0x5344 0x5344
+#define R_0x5348 0x5348
+#define R_0x53a0 0x53a0
+#define R_0x53a4 0x53a4
+#define R_0x53ac 0x53ac
+#define R_0x550 0x550
+#define R_0x551 0x551
+#define R_0x568 0x568
+#define R_0x588 0x588
+#define R_0x60 0x60
+#define R_0x604 0x604
+#define R_0x608 0x608
+#define R_0x60f 0x60f
+#define R_0x64 0x64
+#define R_0x66 0x66
+#define R_0x660 0x660
+#define R_0x668 0x668
+#define R_0x688 0x688
+#define R_0x6a0 0x6a0
+#define R_0x6d8 0x6d8
+#define R_0x6dc 0x6dc
+#define R_0x70 0x70
+#define R_0x74 0x74
+#define R_0x764 0x764
+#define R_0x7b0 0x7b0
+#define R_0x7b4 0x7b4
+#define R_0x7c0 0x7c0
+#define R_0x7c4 0x7c4
+#define R_0x7c8 0x7c8
+#define R_0x7cc 0x7cc
+#define R_0x7f0 0x7f0
+#define R_0x7f4 0x7f4
+#define R_0x7f8 0x7f8
+#define R_0x7fc 0x7fc
+#define R_0x800 0x800
+#define R_0x804 0x804
+#define R_0x808 0x808
+#define R_0x80c 0x80c
+#define R_0x810 0x810
+#define R_0x814 0x814
+#define R_0x818 0x818
+#define R_0x81c 0x81c
+#define R_0x820 0x820
+#define R_0x824 0x824
+#define R_0x828 0x828
+#define R_0x82c 0x82c
+#define R_0x830 0x830
+#define R_0x834 0x834
+#define R_0x838 0x838
+#define R_0x83c 0x83c
+#define R_0x840 0x840
+#define R_0x844 0x840
+#define R_0x848 0x848
+#define R_0x84c 0x84c
+#define R_0x850 0x850
+#define R_0x854 0x854
+#define R_0x858 0x858
+#define R_0x85c 0x85c
+#define R_0x860 0x860
+#define R_0x864 0x864
+#define R_0x868 0x868
+#define R_0x86c 0x86c
+#define R_0x870 0x870
+#define R_0x874 0x874
+#define R_0x878 0x878
+#define R_0x87c 0x87c
+#define R_0x880 0x880
+#define R_0x884 0x884
+#define R_0x888 0x888
+#define R_0x88c 0x88c
+#define R_0x890 0x890
+#define R_0x894 0x894
+#define R_0x898 0x898
+#define R_0x89c 0x89c
+#define R_0x8a0 0x8a0
+#define R_0x8a4 0x8a4
+#define R_0x8ac 0x8ac
+#define R_0x8b4 0x8b4
+#define R_0x8c0 0x8c0
+#define R_0x8c4 0x8c4
+#define R_0x8c8 0x8c8
+#define R_0x8cc 0x8cc
+#define R_0x8d0 0x8d0
+#define R_0x8d4 0x8d4
+#define R_0x8d8 0x8d8
+#define R_0x8dc 0x8dc
+#define R_0x8f0 0x8f0
+#define R_0x8f8 0x8f8
+#define R_0x8fc 0x8fc
+#define R_0x900 0x900
+#define R_0x908 0x908
+#define R_0x90c 0x90c
+#define R_0x910 0x910
+#define R_0x914 0x914
+#define R_0x918 0x918
+#define R_0x91c 0x91c
+#define R_0x920 0x920
+#define R_0x924 0x924
+#define R_0x92c 0x92c
+#define R_0x930 0x930
+#define R_0x934 0x934
+#define R_0x938 0x938
+#define R_0x93c 0x93c
+#define R_0x940 0x940
+#define R_0x944 0x944
+#define R_0x948 0x948
+#define R_0x94c 0x94c
+#define R_0x950 0x950
+#define R_0x954 0x954
+#define R_0x958 0x958
+#define R_0x95c 0x95c
+#define R_0x960 0x960
+#define R_0x964 0x964
+#define R_0x968 0x968
+#define R_0x970 0x970
+#define R_0x974 0x974
+#define R_0x978 0x978
+#define R_0x97c 0x97c
+#define R_0x98c 0x98c
+#define R_0x990 0x990
+#define R_0x994 0x994
+#define R_0x998 0x998
+#define R_0x9a0 0x9a0
+#define R_0x9a4 0x9a4
+#define R_0x9ac 0x9ac
+#define R_0x9b0 0x9b0
+#define R_0x9b4 0x9b4
+#define R_0x9b8 0x9b8
+#define R_0x9cc 0x9cc
+#define R_0x9d0 0x9d0
+#define R_0x9e4 0x9e4
+#define R_0xa0 0xa0
+#define R_0xa00 0xa00
+#define R_0xa04 0xa04
+#define R_0xa08 0xa08
+#define R_0xa0a 0xa0a
+#define R_0xa0c 0xa0c
+#define R_0xa10 0xa10
+#define R_0xa14 0xa14
+#define R_0xa20 0xa20
+#define R_0xa24 0xa24
+#define R_0xa28 0xa28
+#define R_0xa2c 0xa2c
+#define R_0xa58 0xa58
+#define R_0xa70 0xa70
+#define R_0xa74 0xa74
+#define R_0xa78 0xa78
+#define R_0xa8 0xa8
+#define R_0xa80 0xa80
+#define R_0xa84 0xa84
+#define R_0xa98 0xa98
+#define R_0xa9c 0xa9c
+#define R_0xaa8 0xaa8
+#define R_0xaac 0xaac
+#define R_0xab4 0xab4
+#define R_0xabc 0xabc
+#define R_0xac8 0xac8
+#define R_0xacc 0xacc
+#define R_0xad0 0xad0
+#define R_0xb0 0xb0
+#define R_0xb00 0xb00
+#define R_0xb04 0xb04
+#define R_0xb07 0xb07
+#define R_0xb08 0xb08
+#define R_0xb0c 0xb0c
+#define R_0xb10 0xb10
+#define R_0xb14 0xb14
+#define R_0xb18 0xb18
+#define R_0xb1c 0xb1c
+#define R_0xb20 0xb20
+#define R_0xb24 0xb24
+#define R_0xb28 0xb28
+#define R_0xb2b 0xb2b
+#define R_0xb2c 0xb2c
+#define R_0xb30 0xb30
+#define R_0xb34 0xb34
+#define R_0xb38 0xb38
+#define R_0xb3c 0xb3c
+#define R_0xb40 0xb40
+#define R_0xb44 0xb44
+#define R_0xb48 0xb48
+#define R_0xb54 0xb54
+#define R_0xb58 0xb58
+#define R_0xb60 0xb60
+#define R_0xb64 0xb64
+#define R_0xb68 0xb68
+#define R_0xb6a 0xb6a
+#define R_0xb6c 0xb6c
+#define R_0xb6e 0xb6e
+#define R_0xb70 0xb70
+#define R_0xb74 0xb74
+#define R_0xb77 0xb77
+#define R_0xb78 0xb78
+#define R_0xb7c 0xb7c
+#define R_0xb80 0xb80
+#define R_0xb84 0xb84
+#define R_0xb88 0xb88
+#define R_0xb8c 0xb8c
+#define R_0xb90 0xb90
+#define R_0xb94 0xb94
+#define R_0xb98 0xb98
+#define R_0xb9b 0xb9b
+#define R_0xb9c 0xb9c
+#define R_0xba0 0xba0
+#define R_0xba4 0xba4
+#define R_0xba8 0xba8
+#define R_0xbac 0xbac
+#define R_0xbad 0xbad
+#define R_0xbc0 0xbc0
+#define R_0xbc4 0xbc4
+#define R_0xbc8 0xbc8
+#define R_0xbcc 0xbcc
+#define R_0xbd8 0xbd8
+#define R_0xbdc 0xbdc
+#define R_0xbe0 0xbe0
+#define R_0xbe4 0xbe4
+#define R_0xbe8 0xbe8
+#define R_0xbec 0xbec
+#define R_0xbf0 0xbf0
+#define R_0xbf4 0xbf4
+#define R_0xbf8 0xbf8
+#define R_0xc00 0xc00
+#define R_0xc04 0xc04
+#define R_0xc08 0xc08
+#define R_0xc0c 0xc0c
+#define R_0xc10 0xc10
+#define R_0xc14 0xc14
+#define R_0xc18 0xc18
+#define R_0xc1c 0xc1c
+#define R_0xc20 0xc20
+#define R_0xc24 0xc24
+#define R_0xc30 0xc30
+#define R_0xc38 0xc38
+#define R_0xc3c 0xc3c
+#define R_0xc40 0xc40
+#define R_0xc44 0xc44
+#define R_0xc4c 0xc4c
+#define R_0xc50 0xc50
+#define R_0xc54 0xc54
+#define R_0xc58 0xc58
+#define R_0xc5c 0xc5c
+#define R_0xc6c 0xc6c
+#define R_0xc70 0xc70
+#define R_0xc74 0xc74
+#define R_0xc78 0xc78
+#define R_0xc7c 0xc7c
+#define R_0xc80 0xc80
+#define R_0xc84 0xc84
+#define R_0xc88 0xc88
+#define R_0xc8c 0xc8c
+#define R_0xc90 0xc90
+#define R_0xc94 0xc94
+#define R_0xc9c 0xc9c
+#define R_0xca0 0xca0
+#define R_0xca4 0xca4
+#define R_0xca8 0xca8
+#define R_0xcac 0xcac
+#define R_0xcb0 0xcb0
+#define R_0xcb4 0xcb4
+#define R_0xcb8 0xcb8
+#define R_0xcbc 0xcbc
+#define R_0xcbd 0xcbd
+#define R_0xcbe 0xcbe
+#define R_0xcc4 0xcc4
+#define R_0xcc8 0xcc8
+#define R_0xccc 0xccc
+#define R_0xcd0 0xcd0
+#define R_0xcd4 0xcd4
+#define R_0xcd8 0xcd8
+#define R_0xce0 0xce0
+#define R_0xce4 0xce4
+#define R_0xce8 0xce8
+#define R_0xd00 0xd00
+#define R_0xd04 0xd04
+#define R_0xd08 0xd08
+#define R_0xd0c 0xd0c
+#define R_0xd10 0xd10
+#define R_0xd14 0xd14
+#define R_0xd2c 0xd2c
+#define R_0xd30 0xd30
+#define R_0xd40 0xd40
+#define R_0xd44 0xd44
+#define R_0xd48 0xd48
+#define R_0xd4c 0xd4c
+#define R_0xd50 0xd50
+#define R_0xd54 0xd54
+#define R_0xd5c 0xd5c
+#define R_0xd6c 0xd6c
+#define R_0xd7c 0xd7c
+#define R_0xd80 0xd80
+#define R_0xd84 0xd84
+#define R_0xd8c 0xd8c
+#define R_0xd90 0xd90
+#define R_0xd94 0xd94
+#define R_0xdac 0xdac
+#define R_0xdb0 0xdb0
+#define R_0xdb4 0xdb4
+#define R_0xdb8 0xdb8
+#define R_0xdbc 0xdbc
+#define R_0xdcc 0xdcc
+#define R_0xdd0 0xdd0
+#define R_0xdd4 0xdd4
+#define R_0xdd8 0xdd8
+#define R_0xde0 0xde0
+#define R_0xdec 0xdec
+#define R_0xdf4 0xdf4
+#define R_0xe00 0xe00
+#define R_0xe04 0xe04
+#define R_0xe08 0xe08
+#define R_0xe10 0xe10
+#define R_0xe14 0xe14
+#define R_0xe18 0xe18
+#define R_0xe1c 0xe1c
+#define R_0xe20 0xe20
+#define R_0xe24 0xe24
+#define R_0xe28 0xe28
+#define R_0xe30 0xe30
+#define R_0xe34 0xe34
+#define R_0xe38 0xe38
+#define R_0xe3c 0xe3c
+#define R_0xe40 0xe40
+#define R_0xe44 0xe44
+#define R_0xe48 0xe48
+#define R_0xe4c 0xe4c
+#define R_0xe50 0xe50
+#define R_0xe54 0xe54
+#define R_0xe5c 0xe5c
+#define R_0xe64 0xe64
+#define R_0xe6c 0xe6c
+#define R_0xe70 0xe70
+#define R_0xe74 0xe74
+#define R_0xe78 0xe78
+#define R_0xe7c 0xe7c
+#define R_0xe80 0xe80
+#define R_0xe84 0xe84
+#define R_0xe88 0xe88
+#define R_0xe8c 0xe8c
+#define R_0xe90 0xe90
+#define R_0xe94 0xe94
+#define R_0xe98 0xe98
+#define R_0xe9c 0xe9c
+#define R_0xea0 0xea0
+#define R_0xea4 0xea4
+#define R_0xea8 0xea8
+#define R_0xeac 0xeac
+#define R_0xeb0 0xeb0
+#define R_0xeb4 0xeb4
+#define R_0xeb8 0xeb8
+#define R_0xebc 0xebc
+#define R_0xec0 0xec0
+#define R_0xec4 0xec4
+#define R_0xec8 0xec8
+#define R_0xecc 0xecc
+#define R_0xed0 0xed0
+#define R_0xed4 0xed4
+#define R_0xed8 0xed8
+#define R_0xedc 0xedc
+#define R_0xee0 0xee0
+#define R_0xee8 0xee8
+#define R_0xeec 0xeec
+#define R_0xf0 0xf0
+#define R_0xf04 0xf04
+#define R_0xf08 0xf08
+#define R_0xf0c 0xf0c
+#define R_0xf10 0xf10
+#define R_0xf14 0xf14
+#define R_0xf20 0xf20
+#define R_0xf2c 0xf2c
+#define R_0xf30 0xf30
+#define R_0xf34 0xf34
+#define R_0xf4 0xf4
+#define R_0xf44 0xf44
+#define R_0xf48 0xf48
+#define R_0xf4c 0xf4c
+#define R_0xf50 0xf50
+#define R_0xf80 0xf80
+#define R_0xf84 0xf84
+#define R_0xf87 0xf87
+#define R_0xf88 0xf88
+#define R_0xf8c 0xf8c
+#define R_0xf90 0xf90
+#define R_0xf94 0xf94
+#define R_0xf98 0xf98
+#define R_0xfa0 0xfa0
+#define R_0xfa4 0xfa4
+#define R_0xfb8 0xfb8
+#define R_0xfbc 0xfbc
+#define R_0xfc0 0xfc0
+#define R_0xfc4 0xfc4
+#define R_0xfc8 0xfc8
+#define R_0xfcc 0xfcc
+#define R_0xfd0 0xfd0
+#define R_0xff0 0xff0
+#define RF_0x0 0x0
+#define RF_0x00 0x00
+#define RF_0x08 0x08
+#define RF_0x0c 0x0c
+#define RF_0x0d 0x0d
+#define RF_0x1 0x1
+#define RF_0x18 0x18
+#define RF_0x1bf0 0x1bf0
+#define RF_0x2 0x2
+#define RF_0x3 0x3
+#define RF_0x30 0x30
+#define RF_0x31 0x31
+#define RF_0x32 0x32
+#define RF_0x33 0x33
+#define RF_0x35 0x35
+#define RF_0x3e 0x3e
+#define RF_0x3f 0x3f
+#define RF_0x4 0x4
+#define RF_0x42 0x42
+#define RF_0x43 0x43
+#define RF_0x51 0x51
+#define RF_0x52 0x52
+#define RF_0x54 0x54
+#define RF_0x55 0x55
+#define RF_0x56 0x56
+#define RF_0x58 0x58
+#define RF_0x5c 0x5c
+#define RF_0x61 0x61
+#define RF_0x64 0x64
+#define RF_0x65 0x65
+#define RF_0x66 0x66
+#define RF_0x75 0x75
+#define RF_0x76 0x76
+#define RF_0x78 0x78
+#define RF_0x7f 0x7f
+#define RF_0x8 0x8
+#define RF_0x80 0x80
+#define RF_0x81 0x81
+#define RF_0x86 0x86
+#define RF_0x8d 0x8d
+#define RF_0x8f 0x8f
+#define RF_0xae 0xae
+#define RF_0xb0 0xb0
+#define RF_0xb3 0xb3
+#define RF_0xb8 0xb8
+#define RF_0xbc 0xbc
+#define RF_0xbe 0xbe
+#define RF_0xc4 0xc4
+#define RF_0xc9 0xc9
+#define RF_0xca 0xca
+#define RF_0xcc 0xcc
+#define RF_0xd 0xd
+#define RF_0xdd 0xdd
+#define RF_0xde 0xde
+#define RF_0xdf 0xdf
+#define RF_0xed 0xed
+#define RF_0xee 0xee
+#define RF_0xef 0xef
+#define RF_0xf5 0xf5
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/phydm_rssi_monitor.c linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/phydm_rssi_monitor.c
--- linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/phydm_rssi_monitor.c	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/phydm_rssi_monitor.c	2020-04-10 16:35:06.827660581 +0300
@@ -0,0 +1,170 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017  Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * The full GNU General Public License is included in this distribution in the
+ * file called LICENSE.
+ *
+ * Contact Information:
+ * wlanfae <wlanfae@realtek.com>
+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
+ * Hsinchu 300, Taiwan.
+ *
+ * Larry Finger <Larry.Finger@lwfinger.net>
+ *
+ *****************************************************************************/
+
+/*@************************************************************
+ * include files
+ ************************************************************/
+
+#include "mp_precomp.h"
+#include "phydm_precomp.h"
+
+#ifdef PHYDM_SUPPORT_RSSI_MONITOR
+
+void phydm_rssi_monitor_h2c(void *dm_void, u8 macid)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct ra_table *ra_t = &dm->dm_ra_table;
+	struct cmn_sta_info *sta = dm->phydm_sta_info[macid];
+	struct ra_sta_info *ra = NULL;
+	#ifdef CONFIG_BEAMFORMING
+	struct bf_cmn_info *bf = NULL;
+	#endif
+	u8 h2c[H2C_MAX_LENGTH] = {0};
+	u8 stbc_en, ldpc_en;
+	u8 bf_en = 0;
+	u8 is_rx, is_tx;
+
+	if (is_sta_active(sta)) {
+		ra = &sta->ra_info;
+	} else {
+		PHYDM_DBG(dm, DBG_RSSI_MNTR, "[Warning] %s\n", __func__);
+		return;
+	}
+
+	PHYDM_DBG(dm, DBG_RSSI_MNTR, "%s ======>\n", __func__);
+	PHYDM_DBG(dm, DBG_RSSI_MNTR, "MACID=%d\n", sta->mac_id);
+
+	is_rx = (ra->txrx_state == RX_STATE) ? 1 : 0;
+	is_tx = (ra->txrx_state == TX_STATE) ? 1 : 0;
+	stbc_en = (sta->stbc_en) ? 1 : 0;
+	ldpc_en = (sta->ldpc_en) ? 1 : 0;
+
+	#ifdef CONFIG_BEAMFORMING
+	bf = &sta->bf_info;
+
+	if ((bf->ht_beamform_cap & BEAMFORMING_HT_BEAMFORMEE_ENABLE) ||
+	    (bf->vht_beamform_cap & BEAMFORMING_VHT_BEAMFORMEE_ENABLE))
+		bf_en = 1;
+	#endif
+
+	PHYDM_DBG(dm, DBG_RSSI_MNTR, "RA_th_ofst=(( %s%d ))\n",
+		  ((ra_t->ra_ofst_direc) ? "+" : "-"), ra_t->ra_th_ofst);
+
+	h2c[0] = sta->mac_id;
+	h2c[1] = 0;
+	h2c[2] = sta->rssi_stat.rssi;
+	h2c[3] = is_rx | (stbc_en << 1) |
+		     ((dm->noisy_decision & 0x1) << 2) | (bf_en << 6);
+	h2c[4] = (ra_t->ra_th_ofst & 0x7f) |
+		     ((ra_t->ra_ofst_direc & 0x1) << 7);
+	h2c[5] = 0;
+	h2c[6] = 0;
+
+	PHYDM_DBG(dm, DBG_RSSI_MNTR, "PHYDM h2c[0x42]=0x%x %x %x %x %x %x %x\n",
+		  h2c[6], h2c[5], h2c[4], h2c[3], h2c[2], h2c[1], h2c[0]);
+
+	#if (RTL8188E_SUPPORT)
+	if (dm->support_ic_type == ODM_RTL8188E)
+		odm_ra_set_rssi_8188e(dm, sta->mac_id, sta->rssi_stat.rssi);
+	else
+	#endif
+	{
+		odm_fill_h2c_cmd(dm, ODM_H2C_RSSI_REPORT, H2C_MAX_LENGTH, h2c);
+	}
+}
+
+void phydm_calculate_rssi_min_max(void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct cmn_sta_info *sta;
+	s8 rssi_max_tmp = 0, rssi_min_tmp = 100;
+	u8 i;
+	u8 sta_cnt = 0;
+
+	if (!dm->is_linked)
+		return;
+
+	PHYDM_DBG(dm, DBG_RSSI_MNTR, "%s ======>\n", __func__);
+
+	for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) {
+		sta = dm->phydm_sta_info[i];
+		if (is_sta_active(sta)) {
+			sta_cnt++;
+
+			if (sta->rssi_stat.rssi < rssi_min_tmp) {
+				rssi_min_tmp = sta->rssi_stat.rssi;
+				dm->rssi_min_macid = i;
+			}
+
+			if (sta->rssi_stat.rssi > rssi_max_tmp) {
+				rssi_max_tmp = sta->rssi_stat.rssi;
+				dm->rssi_max_macid = i;
+			}
+
+			/*@[Send RSSI to FW]*/
+			if (!sta->ra_info.disable_ra)
+				phydm_rssi_monitor_h2c(dm, i);
+
+			if (sta_cnt == dm->number_linked_client)
+				break;
+		}
+	}
+	dm->pre_rssi_min = dm->rssi_min;
+
+	dm->rssi_max = (u8)rssi_max_tmp;
+	dm->rssi_min = (u8)rssi_min_tmp;
+}
+
+void phydm_rssi_monitor_check(void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+
+	if (!(dm->support_ability & ODM_BB_RSSI_MONITOR))
+		return;
+
+	/*@for AP watchdog period = 1 sec*/
+	if ((dm->phydm_sys_up_time % 2) == 1)
+		return;
+
+	PHYDM_DBG(dm, DBG_RSSI_MNTR, "%s ======>\n", __func__);
+
+	phydm_calculate_rssi_min_max(dm);
+
+	PHYDM_DBG(dm, DBG_RSSI_MNTR, "RSSI {max, min} = {%d, %d}\n",
+		  dm->rssi_max, dm->rssi_min);
+}
+
+void phydm_rssi_monitor_init(void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct ra_table *ra_tab = &dm->dm_ra_table;
+
+	ra_tab->firstconnect = false;
+	dm->pre_rssi_min = 0;
+	dm->rssi_max = 0;
+	dm->rssi_min = 0;
+}
+
+#endif
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/phydm_rssi_monitor.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/phydm_rssi_monitor.h
--- linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/phydm_rssi_monitor.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/phydm_rssi_monitor.h	2020-04-10 16:35:06.827660581 +0300
@@ -0,0 +1,55 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017  Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * The full GNU General Public License is included in this distribution in the
+ * file called LICENSE.
+ *
+ * Contact Information:
+ * wlanfae <wlanfae@realtek.com>
+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
+ * Hsinchu 300, Taiwan.
+ *
+ * Larry Finger <Larry.Finger@lwfinger.net>
+ *
+ *****************************************************************************/
+
+#ifndef __PHYDM_RSSI_MONITOR_H__
+#define __PHYDM_RSSI_MONITOR_H__
+
+#define RSSI_MONITOR_VERSION "2.0"
+
+/* @1 ============================================================
+ * 1  Definition
+ * 1 ============================================================
+ */
+
+/* @1 ============================================================
+ * 1  structure
+ * 1 ============================================================
+ */
+
+/* @1 ============================================================
+ * 1  enumeration
+ * 1 ============================================================
+ */
+
+/* @1 ============================================================
+ * 1  function prototype
+ * 1 ============================================================
+ */
+
+void phydm_rssi_monitor_check(void *dm_void);
+
+void phydm_rssi_monitor_init(void *dm_void);
+
+#endif
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/phydm_smt_ant.c linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/phydm_smt_ant.c
--- linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/phydm_smt_ant.c	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/phydm_smt_ant.c	2020-04-10 16:35:06.827660581 +0300
@@ -0,0 +1,2253 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017  Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * The full GNU General Public License is included in this distribution in the
+ * file called LICENSE.
+ *
+ * Contact Information:
+ * wlanfae <wlanfae@realtek.com>
+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
+ * Hsinchu 300, Taiwan.
+ *
+ * Larry Finger <Larry.Finger@lwfinger.net>
+ *
+ *****************************************************************************/
+
+/* ************************************************************
+ * include files
+ * ************************************************************ */
+
+#include "mp_precomp.h"
+#include "phydm_precomp.h"
+
+/*******************************************************
+ * when antenna test utility is on or some testing need to disable antenna diversity
+ * call this function to disable all ODM related mechanisms which will switch antenna.
+ ******************************************************/
+#if (defined(CONFIG_SMART_ANTENNA))
+
+#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
+#if (RTL8198F_SUPPORT == 1)
+void phydm_smt_ant_init_98f(void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	u32 val = 0;
+
+	#if 0
+	odm_set_bb_reg(dm, R_0x1da4, 0x3c, 4); /*6.25*4 = 25ms*/
+	odm_set_bb_reg(dm, R_0x1da4, BIT(6), 1);
+	odm_set_bb_reg(dm, R_0x1da4, BIT(7), 1);
+	#endif
+}
+#endif
+#endif
+
+#if (defined(CONFIG_CUMITEK_SMART_ANTENNA))
+void phydm_cumitek_smt_ant_mapping_table_8822b(
+	void *dm_void,
+	u8 *table_path_a,
+	u8 *table_path_b)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	u32 path_a_0to3_idx = 0;
+	u32 path_b_0to3_idx = 0;
+	u32 path_a_4to7_idx = 0;
+	u32 path_b_4to7_idx = 0;
+
+	path_a_0to3_idx = ((table_path_a[3] & 0xf) << 24) | ((table_path_a[2] & 0xf) << 16) | ((table_path_a[1] & 0xf) << 8) | (table_path_a[0] & 0xf);
+
+	path_b_0to3_idx = ((table_path_b[3] & 0xf) << 28) | ((table_path_b[2] & 0xf) << 20) | ((table_path_b[1] & 0xf) << 12) | ((table_path_b[0] & 0xf) << 4);
+
+	path_a_4to7_idx = ((table_path_a[7] & 0xf) << 24) | ((table_path_a[6] & 0xf) << 16) | ((table_path_a[5] & 0xf) << 8) | (table_path_a[4] & 0xf);
+
+	path_b_4to7_idx = ((table_path_b[7] & 0xf) << 28) | ((table_path_b[6] & 0xf) << 20) | ((table_path_b[5] & 0xf) << 12) | ((table_path_b[4] & 0xf) << 4);
+
+#if 0
+	/*PHYDM_DBG(dm, DBG_SMT_ANT, "mapping table{A, B} = {0x%x, 0x%x}\n", path_a_0to3_idx, path_b_0to3_idx);*/
+#endif
+
+	/*pathA*/
+	odm_set_bb_reg(dm, R_0xca4, MASKDWORD, path_a_0to3_idx); /*@ant map 1*/
+	odm_set_bb_reg(dm, R_0xca8, MASKDWORD, path_a_4to7_idx); /*@ant map 2*/
+
+	/*pathB*/
+	odm_set_bb_reg(dm, R_0xea4, MASKDWORD, path_b_0to3_idx); /*@ant map 1*/
+	odm_set_bb_reg(dm, R_0xea8, MASKDWORD, path_b_4to7_idx); /*@ant map 2*/
+}
+
+void phydm_cumitek_smt_ant_init_8822b(
+	void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct smt_ant *smtant_table = &dm->smtant_table;
+	struct smt_ant_cumitek *cumi_smtant_table = &dm->smtant_table.cumi_smtant_table;
+	u32 value32;
+
+	PHYDM_DBG(dm, DBG_SMT_ANT, "[8822B Cumitek SmtAnt Int]\n");
+
+	/*@========= MAC GPIO setting =================================*/
+
+	/* Pin, pin_name, RFE_CTRL_NUM*/
+
+	/* @A0, 55, 5G_TRSW, 3*/
+	/* @A1, 52, 5G_TRSW, 0*/
+	/* @A2, 25, 5G_TRSW, 8*/
+
+	/* @B0, 16, 5G_TRSW, 4*/
+	/* @B1, 13, 5G_TRSW, 11*/
+	/* @B2, 24, 5G_TRSW, 9*/
+
+	/*@for RFE_CTRL 8 & 9*/
+	odm_set_mac_reg(dm, R_0x4c, BIT(24) | BIT(23), 2);
+	odm_set_mac_reg(dm, R_0x44, BIT(27) | BIT(26), 0);
+
+	/*@for RFE_CTRL 0*/
+	odm_set_mac_reg(dm, R_0x4c, BIT(25), 0);
+	odm_set_mac_reg(dm, R_0x64, BIT(29), 1);
+
+	/*@for RFE_CTRL 2 & 3*/
+	odm_set_mac_reg(dm, R_0x4c, BIT(26), 0);
+	odm_set_mac_reg(dm, R_0x64, BIT(28), 1);
+
+	/*@for RFE_CTRL 11*/
+	odm_set_mac_reg(dm, R_0x40, BIT(3), 1);
+
+	/*@0x604[25]=1 : 2bit mode for pathA&B&C&D*/
+	/*@0x604[25]=0 : 3bit mode for pathA&B*/
+	smtant_table->tx_desc_mode = 0;
+	odm_set_mac_reg(dm, R_0x604, BIT(25), (u32)smtant_table->tx_desc_mode);
+
+	/*@========= BB RFE setting =================================*/
+#if 0
+	/*path A*/
+	odm_set_bb_reg(dm, R_0x1990, BIT(3), 0);		/*RFE_CTRL_3*/ /*A_0*/
+	odm_set_bb_reg(dm, R_0xcbc, BIT(3), 0);		/*@inv*/
+	odm_set_bb_reg(dm, R_0xcb0, 0xf000, 8);
+
+	odm_set_bb_reg(dm, R_0x1990, BIT(0), 0);		/*RFE_CTRL_0*/ /*A_1*/
+	odm_set_bb_reg(dm, R_0xcbc, BIT(0), 0);		/*@inv*/
+	odm_set_bb_reg(dm, R_0xcb0, 0xf, 0x9);
+
+	odm_set_bb_reg(dm, R_0x1990, BIT(8), 0);		/*RFE_CTRL_8*/ /*A_2*/
+	odm_set_bb_reg(dm, R_0xcbc, BIT(8), 0);		/*@inv*/
+	odm_set_bb_reg(dm, R_0xcb4, 0xf, 0xa);
+
+
+	/*path B*/
+	odm_set_bb_reg(dm, R_0x1990, BIT(4), 1);		/*RFE_CTRL_4*/	/*B_0*/
+	odm_set_bb_reg(dm, R_0xdbc, BIT(4), 0);		/*@inv*/
+	odm_set_bb_reg(dm, R_0xdb0, 0xf0000, 0xb);
+
+	odm_set_bb_reg(dm, R_0x1990, BIT(11), 1);	/*RFE_CTRL_11*/	/*B_1*/
+	odm_set_bb_reg(dm, R_0xdbc, BIT(11), 0);		/*@inv*/
+	odm_set_bb_reg(dm, R_0xdb4, 0xf000, 0xc);
+
+	odm_set_bb_reg(dm, R_0x1990, BIT(9), 1);		/*RFE_CTRL_9*/	/*B_2*/
+	odm_set_bb_reg(dm, R_0xdbc, BIT(9), 0);		/*@inv*/
+	odm_set_bb_reg(dm, R_0xdb4, 0xf0, 0xd);
+#endif
+	/*@========= BB SmtAnt setting =================================*/
+	odm_set_mac_reg(dm, R_0x6d8, BIT(22) | BIT(21), 2); /*resp tx by register*/
+	odm_set_mac_reg(dm, R_0x668, BIT(3), 1);
+	odm_set_bb_reg(dm, R_0x804, BIT(4), 0); /*@lathch antsel*/
+	odm_set_bb_reg(dm, R_0x818, 0xf00000, 0); /*@keep tx by rx*/
+	odm_set_bb_reg(dm, R_0x900, BIT(19), 0); /*@fast train*/
+	odm_set_bb_reg(dm, R_0x900, BIT(18), 1); /*@1: by TXDESC*/
+
+	/*pathA*/
+	odm_set_bb_reg(dm, R_0xca4, MASKDWORD, 0x03020100); /*@ant map 1*/
+	odm_set_bb_reg(dm, R_0xca8, MASKDWORD, 0x07060504); /*@ant map 2*/
+	odm_set_bb_reg(dm, R_0xcac, BIT(9), 0); /*@keep antsel map by GNT_BT*/
+
+	/*pathB*/
+	odm_set_bb_reg(dm, R_0xea4, MASKDWORD, 0x30201000); /*@ant map 1*/
+	odm_set_bb_reg(dm, R_0xea8, MASKDWORD, 0x70605040); /*@ant map 2*/
+	odm_set_bb_reg(dm, R_0xeac, BIT(9), 0); /*@keep antsel map by GNT_BT*/
+}
+
+void phydm_cumitek_smt_ant_init_8197f(
+	void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct smt_ant *smtant_table = &dm->smtant_table;
+	struct smt_ant_cumitek *cumi_smtant_table = &dm->smtant_table.cumi_smtant_table;
+	u32 value32;
+
+	PHYDM_DBG(dm, DBG_SMT_ANT, "[8197F Cumitek SmtAnt Int]\n");
+
+	/*@GPIO setting*/
+}
+
+void phydm_cumitek_smt_ant_init_8192f(
+	void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct smt_ant *smtant_table = &dm->smtant_table;
+	struct smt_ant_cumitek *cumi_smtant_table = &dm->smtant_table.cumi_smtant_table;
+	u32 value32;
+	PHYDM_DBG(dm, DBG_SMT_ANT, "[8192F Cumitek SmtAnt Int]\n");
+
+	/*@GPIO setting*/
+}
+
+void phydm_cumitek_smt_tx_ant_update(
+	void *dm_void,
+	u8 tx_ant_idx_path_a,
+	u8 tx_ant_idx_path_b,
+	u32 mac_id)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct smt_ant *smtant_table = &dm->smtant_table;
+	struct smt_ant_cumitek *cumi_smtant_table = &dm->smtant_table.cumi_smtant_table;
+
+	PHYDM_DBG(dm, DBG_ANT_DIV,
+		  "[Cumitek] Set TX-ANT[%d] = (( A:0x%x ,  B:0x%x ))\n", mac_id,
+		  tx_ant_idx_path_a, tx_ant_idx_path_b);
+
+	/*path-A*/
+	cumi_smtant_table->tx_ant_idx[0][mac_id] = tx_ant_idx_path_a; /*@fill this value into TXDESC*/
+
+	/*path-B*/
+	cumi_smtant_table->tx_ant_idx[1][mac_id] = tx_ant_idx_path_b; /*@fill this value into TXDESC*/
+}
+
+void phydm_cumitek_smt_rx_default_ant_update(
+	void *dm_void,
+	u8 rx_ant_idx_path_a,
+	u8 rx_ant_idx_path_b)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct smt_ant *smtant_table = &dm->smtant_table;
+	struct smt_ant_cumitek *cumi_smtant_table = &dm->smtant_table.cumi_smtant_table;
+
+	PHYDM_DBG(dm, DBG_ANT_DIV,
+		  "[Cumitek] Set RX-ANT = (( A:0x%x, B:0x%x ))\n",
+		  rx_ant_idx_path_a, rx_ant_idx_path_b);
+
+	/*path-A*/
+	if (cumi_smtant_table->rx_default_ant_idx[0] != rx_ant_idx_path_a) {
+		#if (RTL8822B_SUPPORT == 1)
+		if (dm->support_ic_type == ODM_RTL8822B) {
+			odm_set_bb_reg(dm, R_0xc08, BIT(21) | BIT(20) | BIT(19), rx_ant_idx_path_a); /*@default RX antenna*/
+			odm_set_mac_reg(dm, R_0x6d8, BIT(2) | BIT(1) | BIT(0), rx_ant_idx_path_a); /*@default response TX antenna*/
+		}
+		#endif
+
+		#if (RTL8197F_SUPPORT == 1)
+		if (dm->support_ic_type == ODM_RTL8197F) {
+		}
+		#endif
+
+		/*@jj add 20170822*/
+		#if (RTL8192F_SUPPORT == 1)
+		if (dm->support_ic_type == ODM_RTL8192F) {
+		}
+		#endif
+		cumi_smtant_table->rx_default_ant_idx[0] = rx_ant_idx_path_a;
+	}
+
+	/*path-B*/
+	if (cumi_smtant_table->rx_default_ant_idx[1] != rx_ant_idx_path_b) {
+		#if (RTL8822B_SUPPORT == 1)
+		if (dm->support_ic_type == ODM_RTL8822B) {
+			odm_set_bb_reg(dm, R_0xe08, BIT(21) | BIT(20) | BIT(19), rx_ant_idx_path_b); /*@default antenna*/
+			odm_set_mac_reg(dm, R_0x6d8, BIT(5) | BIT(4) | BIT(3), rx_ant_idx_path_b); /*@default response TX antenna*/
+		}
+		#endif
+
+		#if (RTL8197F_SUPPORT == 1)
+		if (dm->support_ic_type == ODM_RTL8197F) {
+		}
+		#endif
+
+		/*@jj add 20170822*/
+		#if (RTL8192F_SUPPORT == 1)
+		if (dm->support_ic_type == ODM_RTL8192F) {
+		}
+		#endif
+		cumi_smtant_table->rx_default_ant_idx[1] = rx_ant_idx_path_b;
+	}
+}
+
+void phydm_cumitek_smt_ant_debug(
+	void *dm_void,
+	char input[][16],
+	u32 *_used,
+	char *output,
+	u32 *_out_len)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct smt_ant *smtant_table = &dm->smtant_table;
+	struct smt_ant_cumitek *cumi_smtant_table = &dm->smtant_table.cumi_smtant_table;
+	u32 used = *_used;
+	u32 out_len = *_out_len;
+	char help[] = "-h";
+	u32 dm_value[10] = {0};
+	u8 i;
+
+	PHYDM_SSCANF(input[1], DCMD_DECIMAL, &dm_value[0]);
+
+	if (strcmp(input[1], help) == 0) {
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "{1} {PathA rx_ant_idx} {pathB rx_ant_idx}\n");
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "{2} {PathA tx_ant_idx} {pathB tx_ant_idx} {macid}\n");
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "{3} {PathA mapping table} {PathB mapping table}\n");
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "{4} {txdesc_mode 0:3bit, 1:2bit}\n");
+
+	} else if (dm_value[0] == 1) { /*@fix rx_idle pattern*/
+
+		PHYDM_SSCANF(input[2], DCMD_DECIMAL, &dm_value[1]);
+		PHYDM_SSCANF(input[3], DCMD_DECIMAL, &dm_value[2]);
+
+		phydm_cumitek_smt_rx_default_ant_update(dm, (u8)dm_value[1], (u8)dm_value[2]);
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "RX Ant{A, B}={%d, %d}\n", dm_value[1], dm_value[2]);
+
+	} else if (dm_value[0] == 2) { /*@fix tx pattern*/
+
+		for (i = 1; i < 4; i++) {
+			if (input[i + 1])
+				PHYDM_SSCANF(input[i + 1], DCMD_DECIMAL, &dm_value[i]);
+		}
+
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "STA[%d] TX Ant{A, B}={%d, %d}\n", dm_value[3],
+			 dm_value[1], dm_value[2]);
+		phydm_cumitek_smt_tx_ant_update(dm, (u8)dm_value[1], (u8)dm_value[2], (u8)dm_value[3]);
+
+	} else if (dm_value[0] == 3) {
+		u8 table_path_a[8] = {0};
+		u8 table_path_b[8] = {0};
+
+		for (i = 1; i < 4; i++) {
+			if (input[i + 1])
+				PHYDM_SSCANF(input[i + 1], DCMD_HEX, &dm_value[i]);
+		}
+
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "Set Path-AB mapping table={%d, %d}\n", dm_value[1],
+			 dm_value[2]);
+
+		for (i = 0; i < 8; i++) {
+			table_path_a[i] = (u8)((dm_value[1] >> (4 * i)) & 0xf);
+			table_path_b[i] = (u8)((dm_value[2] >> (4 * i)) & 0xf);
+		}
+
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "Ant_Table_A[7:0]={0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x}\n",
+			 table_path_a[7], table_path_a[6], table_path_a[5],
+			 table_path_a[4], table_path_a[3], table_path_a[2],
+			 table_path_a[1], table_path_a[0]);
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "Ant_Table_B[7:0]={0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x}\n",
+			 table_path_b[7], table_path_b[6], table_path_b[5],
+			 table_path_b[4], table_path_b[3], table_path_b[2],
+			 table_path_b[1], table_path_b[0]);
+
+		phydm_cumitek_smt_ant_mapping_table_8822b(dm, &table_path_a[0], &table_path_b[0]);
+
+	} else if (dm_value[0] == 4) {
+		smtant_table->tx_desc_mode = (u8)dm_value[1];
+		odm_set_mac_reg(dm, R_0x604, BIT(25), (u32)smtant_table->tx_desc_mode);
+	}
+	*_used = used;
+	*_out_len = out_len;
+}
+
+#endif
+
+#if (defined(CONFIG_HL_SMART_ANTENNA))
+#ifdef CONFIG_HL_SMART_ANTENNA_TYPE2
+
+#if (RTL8822B_SUPPORT == 1)
+void phydm_hl_smart_ant_type2_init_8822b(
+	void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct smt_ant_honbo *sat_tab = &dm->dm_sat_table;
+	struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
+	u8 j;
+	u8 rfu_codeword_table_init_2g[SUPPORT_BEAM_SET_PATTERN_NUM][MAX_PATH_NUM_8822B] = {
+		{1, 1}, /*@0*/
+		{1, 2},
+		{2, 1},
+		{2, 2},
+		{4, 0},
+		{5, 0},
+		{6, 0},
+		{7, 0},
+		{8, 0}, /*@8*/
+		{9, 0},
+		{0xa, 0},
+		{0xb, 0},
+		{0xc, 0},
+		{0xd, 0},
+		{0xe, 0},
+		{0xf, 0}};
+	u8 rfu_codeword_table_init_5g[SUPPORT_BEAM_SET_PATTERN_NUM][MAX_PATH_NUM_8822B] = {
+#if 1
+		{9, 1}, /*@0*/
+		{9, 9},
+		{1, 9},
+		{9, 6},
+		{2, 1},
+		{2, 9},
+		{9, 2},
+		{2, 2}, /*@8*/
+		{6, 1},
+		{6, 9},
+		{2, 9},
+		{2, 2},
+		{6, 2},
+		{6, 6},
+		{2, 6},
+		{1, 1}
+#else
+		{1, 1}, /*@0*/
+		{9, 1},
+		{9, 9},
+		{1, 9},
+		{1, 2},
+		{9, 2},
+		{9, 6},
+		{1, 6},
+		{2, 1}, /*@8*/
+		{6, 1},
+		{6, 9},
+		{2, 9},
+		{2, 2},
+		{6, 2},
+		{6, 6},
+		{2, 6}
+#endif
+	};
+
+	PHYDM_DBG(dm, DBG_ANT_DIV,
+		  "***RTK 8822B SmartAnt_Init: Hong-Bo SmrtAnt Type2]\n");
+
+	/* @---------------------------------------- */
+	/* @GPIO 0-1 for Beam control */
+	/* reg0x66[2:0]=0 */
+	/* reg0x44[25:24] = 0 */
+	/* reg0x44[23:16]  enable_output for P_GPIO[7:0] */
+	/* reg0x44[15:8]  output_value for P_GPIO[7:0] */
+	/* reg0x40[1:0] = 0  GPIO function */
+	/* @------------------------------------------ */
+
+	odm_move_memory(dm, sat_tab->rfu_codeword_table_2g, rfu_codeword_table_init_2g, (SUPPORT_BEAM_SET_PATTERN_NUM * MAX_PATH_NUM_8822B));
+	odm_move_memory(dm, sat_tab->rfu_codeword_table_5g, rfu_codeword_table_init_5g, (SUPPORT_BEAM_SET_PATTERN_NUM * MAX_PATH_NUM_8822B));
+
+	/*@GPIO setting*/
+	odm_set_mac_reg(dm, R_0x64, (BIT(18) | BIT(17) | BIT(16)), 0);
+	odm_set_mac_reg(dm, R_0x44, BIT(25) | BIT(24), 0); /*@config P_GPIO[3:2] to data port*/
+	odm_set_mac_reg(dm, R_0x44, BIT(17) | BIT(16), 0x3); /*@enable_output for P_GPIO[3:2]*/
+#if 0
+	/*odm_set_mac_reg(dm, R_0x44, BIT(9)|BIT(8), 0);*/ /*P_GPIO[3:2] output value*/
+#endif
+	odm_set_mac_reg(dm, R_0x40, BIT(1) | BIT(0), 0); /*@GPIO function*/
+
+	/*@Hong_lin smart antenna HW setting*/
+	sat_tab->rfu_protocol_type = 2;
+	sat_tab->rfu_protocol_delay_time = 45;
+
+	sat_tab->rfu_codeword_total_bit_num = 16; /*@max=32bit*/
+	sat_tab->rfu_each_ant_bit_num = 4;
+
+	sat_tab->total_beam_set_num = 4;
+	sat_tab->total_beam_set_num_2g = 4;
+	sat_tab->total_beam_set_num_5g = 8;
+
+#if DEV_BUS_TYPE == RT_SDIO_INTERFACE
+	sat_tab->latch_time = 100; /*@mu sec*/
+#elif DEV_BUS_TYPE == RT_USB_INTERFACE
+	sat_tab->latch_time = 100; /*@mu sec*/
+#endif
+	sat_tab->pkt_skip_statistic_en = 0;
+
+	sat_tab->ant_num = 2;
+	sat_tab->ant_num_total = MAX_PATH_NUM_8822B;
+	sat_tab->first_train_ant = MAIN_ANT;
+
+	sat_tab->fix_beam_pattern_en = 0;
+	sat_tab->decision_holding_period = 0;
+
+	/*@beam training setting*/
+	sat_tab->pkt_counter = 0;
+	sat_tab->per_beam_training_pkt_num = 10;
+
+	/*set default beam*/
+	sat_tab->fast_training_beam_num = 0;
+	sat_tab->pre_fast_training_beam_num = sat_tab->fast_training_beam_num;
+
+	for (j = 0; j < SUPPORT_BEAM_SET_PATTERN_NUM; j++) {
+		sat_tab->beam_set_avg_rssi_pre[j] = 0;
+		sat_tab->beam_set_train_val_diff[j] = 0;
+		sat_tab->beam_set_train_cnt[j] = 0;
+	}
+	phydm_set_rfu_beam_pattern_type2(dm);
+	fat_tab->fat_state = FAT_BEFORE_LINK_STATE;
+}
+#endif
+
+u32 phydm_construct_hb_rfu_codeword_type2(
+	void *dm_void,
+	u32 beam_set_idx)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct smt_ant_honbo *sat_tab = &dm->dm_sat_table;
+	u32 sync_codeword = 0x7f;
+	u32 codeword = 0;
+	u32 data_tmp = 0;
+	u32 i;
+
+	for (i = 0; i < sat_tab->ant_num_total; i++) {
+		if (*dm->band_type == ODM_BAND_5G)
+			data_tmp = sat_tab->rfu_codeword_table_5g[beam_set_idx][i];
+		else
+			data_tmp = sat_tab->rfu_codeword_table_2g[beam_set_idx][i];
+
+		codeword |= (data_tmp << (i * sat_tab->rfu_each_ant_bit_num));
+	}
+
+	codeword = (codeword << 8) | sync_codeword;
+
+	return codeword;
+}
+
+void phydm_update_beam_pattern_type2(
+	void *dm_void,
+	u32 codeword,
+	u32 codeword_length)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct smt_ant_honbo *sat_tab = &dm->dm_sat_table;
+	u8 i;
+	boolean beam_ctrl_signal;
+	u32 one = 0x1;
+	u32 reg44_tmp_p, reg44_tmp_n, reg44_ori;
+	u8 devide_num = 4;
+
+	PHYDM_DBG(dm, DBG_ANT_DIV, "Set codeword = ((0x%x))\n", codeword);
+
+	reg44_ori = odm_get_mac_reg(dm, R_0x44, MASKDWORD);
+	reg44_tmp_p = reg44_ori;
+#if 0
+	/*PHYDM_DBG(dm, DBG_ANT_DIV, "reg44_ori =0x%x\n", reg44_ori);*/
+#endif
+
+	/*@devide_num = (sat_tab->rfu_protocol_type == 2) ? 8 : 4;*/
+
+	for (i = 0; i <= (codeword_length - 1); i++) {
+		beam_ctrl_signal = (boolean)((codeword & BIT(i)) >> i);
+
+		#if 1
+		if (dm->debug_components & DBG_ANT_DIV) {
+			if (i == (codeword_length - 1))
+				pr_debug("%d ]\n", beam_ctrl_signal);
+			else if (i == 0)
+				pr_debug("Start sending codeword[1:%d] ---> [ %d ", codeword_length, beam_ctrl_signal);
+			else if ((i % devide_num) == (devide_num - 1))
+				pr_debug("%d  |  ", beam_ctrl_signal);
+			else
+				pr_debug("%d ", beam_ctrl_signal);
+		}
+		#endif
+
+		if (dm->support_ic_type == ODM_RTL8821) {
+			#if (RTL8821A_SUPPORT == 1)
+			reg44_tmp_p = reg44_ori & (~(BIT(11) | BIT(10))); /*@clean bit 10 & 11*/
+			reg44_tmp_p |= ((1 << 11) | (beam_ctrl_signal << 10));
+			reg44_tmp_n = reg44_ori & (~(BIT(11) | BIT(10)));
+
+#if 0
+			/*PHYDM_DBG(dm, DBG_ANT_DIV, "reg44_tmp_p =(( 0x%x )), reg44_tmp_n = (( 0x%x ))\n", reg44_tmp_p, reg44_tmp_n);*/
+#endif
+			odm_set_mac_reg(dm, R_0x44, MASKDWORD, reg44_tmp_p);
+			odm_set_mac_reg(dm, R_0x44, MASKDWORD, reg44_tmp_n);
+			#endif
+		}
+		#if (RTL8822B_SUPPORT == 1)
+		else if (dm->support_ic_type == ODM_RTL8822B) {
+			if (sat_tab->rfu_protocol_type == 2) {
+				reg44_tmp_p = reg44_tmp_p & ~(BIT(8)); /*@clean bit 8*/
+				reg44_tmp_p = reg44_tmp_p ^ BIT(9); /*@get new clk high/low, exclusive-or*/
+
+				reg44_tmp_p |= (beam_ctrl_signal << 8);
+
+				odm_set_mac_reg(dm, R_0x44, MASKDWORD, reg44_tmp_p);
+				ODM_delay_us(sat_tab->rfu_protocol_delay_time);
+#if 0
+				/*PHYDM_DBG(dm, DBG_ANT_DIV, "reg44 =(( 0x%x )), reg44[9:8] = ((%x)), beam_ctrl_signal =((%x))\n", reg44_tmp_p, ((reg44_tmp_p & 0x300)>>8), beam_ctrl_signal);*/
+#endif
+
+			} else {
+				reg44_tmp_p = reg44_ori & (~(BIT(9) | BIT(8))); /*@clean bit 9 & 8*/
+				reg44_tmp_p |= ((1 << 9) | (beam_ctrl_signal << 8));
+				reg44_tmp_n = reg44_ori & (~(BIT(9) | BIT(8)));
+
+#if 0
+				/*PHYDM_DBG(dm, DBG_ANT_DIV, "reg44_tmp_p =(( 0x%x )), reg44_tmp_n = (( 0x%x ))\n", reg44_tmp_p, reg44_tmp_n); */
+#endif
+				odm_set_mac_reg(dm, R_0x44, MASKDWORD, reg44_tmp_p);
+				ODM_delay_us(10);
+				odm_set_mac_reg(dm, R_0x44, MASKDWORD, reg44_tmp_n);
+				ODM_delay_us(10);
+			}
+		}
+		#endif
+	}
+}
+
+void phydm_update_rx_idle_beam_type2(
+	void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
+	struct smt_ant_honbo *sat_tab = &dm->dm_sat_table;
+	u32 i;
+
+	sat_tab->update_beam_codeword = phydm_construct_hb_rfu_codeword_type2(dm, sat_tab->rx_idle_beam_set_idx);
+	PHYDM_DBG(dm, DBG_ANT_DIV,
+		  "[ Update Rx-Idle-Beam ] BeamSet idx = ((%d))\n",
+		  sat_tab->rx_idle_beam_set_idx);
+
+#if DEV_BUS_TYPE == RT_PCI_INTERFACE
+	phydm_update_beam_pattern_type2(dm, sat_tab->update_beam_codeword, sat_tab->rfu_codeword_total_bit_num);
+#else
+	odm_schedule_work_item(&sat_tab->hl_smart_antenna_workitem);
+#if 0
+	/*odm_stall_execution(1);*/
+#endif
+#endif
+
+	sat_tab->pre_codeword = sat_tab->update_beam_codeword;
+}
+
+void phydm_hl_smt_ant_dbg_type2(
+	void *dm_void,
+	char input[][16],
+	u32 *_used,
+	char *output,
+	u32 *_out_len
+)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct smt_ant_honbo *sat_tab = &dm->dm_sat_table;
+	u32 used = *_used;
+	u32 out_len = *_out_len;
+	u32 one = 0x1;
+	u32 codeword_length = sat_tab->rfu_codeword_total_bit_num;
+	u32 beam_ctrl_signal, i;
+	u8 devide_num = 4;
+	char help[] = "-h";
+	u32 dm_value[10] = {0};
+
+	PHYDM_SSCANF(input[1], DCMD_DECIMAL, &dm_value[0]);
+	PHYDM_SSCANF(input[2], DCMD_DECIMAL, &dm_value[1]);
+	PHYDM_SSCANF(input[3], DCMD_DECIMAL, &dm_value[2]);
+	PHYDM_SSCANF(input[4], DCMD_DECIMAL, &dm_value[3]);
+	PHYDM_SSCANF(input[5], DCMD_DECIMAL, &dm_value[4]);
+
+	if (strcmp(input[1], help) == 0) {
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 " 1 {fix_en} {codeword(Hex)}\n");
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 " 3 {Fix_training_num_en} {Per_beam_training_pkt_num} {Decision_holding_period}\n");
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 " 5 {0:show, 1:2G, 2:5G} {beam_num} {idxA(Hex)} {idxB(Hex)}\n");
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 " 7 {0:show, 1:2G, 2:5G} {total_beam_set_num}\n");
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 " 8 {0:show, 1:set} {RFU delay time(us)}\n");
+
+	} else if (dm_value[0] == 1) { /*@fix beam pattern*/
+
+		sat_tab->fix_beam_pattern_en = dm_value[1];
+
+		if (sat_tab->fix_beam_pattern_en == 1) {
+			PHYDM_SSCANF(input[3], DCMD_HEX, &dm_value[2]);
+			sat_tab->fix_beam_pattern_codeword = dm_value[2];
+
+			if (sat_tab->fix_beam_pattern_codeword > (one << codeword_length)) {
+				PHYDM_DBG(dm, DBG_ANT_DIV,
+					  "[ SmartAnt ] Codeword overflow, Current codeword is ((0x%x)), and should be less than ((%d))bit\n",
+					  sat_tab->fix_beam_pattern_codeword,
+					  codeword_length);
+
+				(sat_tab->fix_beam_pattern_codeword) &= 0xffffff;
+
+				PHYDM_DBG(dm, DBG_ANT_DIV,
+					  "[ SmartAnt ] Auto modify to (0x%x)\n",
+					  sat_tab->fix_beam_pattern_codeword);
+			}
+
+			sat_tab->update_beam_codeword = sat_tab->fix_beam_pattern_codeword;
+
+			/*@---------------------------------------------------------*/
+			PDM_SNPF(out_len, used, output + used, out_len - used,
+				 "Fix Beam Pattern\n");
+
+			/*@devide_num = (sat_tab->rfu_protocol_type == 2) ? 8 : 4;*/
+
+			for (i = 0; i <= (codeword_length - 1); i++) {
+				beam_ctrl_signal = (boolean)((sat_tab->update_beam_codeword & BIT(i)) >> i);
+
+				if (i == (codeword_length - 1))
+					PDM_SNPF(out_len, used,
+						 output + used,
+						 out_len - used,
+						 "%d]\n",
+						 beam_ctrl_signal);
+				else if (i == 0)
+					PDM_SNPF(out_len, used,
+						 output + used,
+						 out_len - used,
+						 "Send Codeword[1:%d] to RFU -> [%d",
+						 sat_tab->rfu_codeword_total_bit_num,
+						 beam_ctrl_signal);
+				else if ((i % devide_num) == (devide_num - 1))
+					PDM_SNPF(out_len, used,
+						 output + used,
+						 out_len - used, "%d|",
+						 beam_ctrl_signal);
+				else
+					PDM_SNPF(out_len, used,
+						 output + used,
+						 out_len - used, "%d",
+						 beam_ctrl_signal);
+			}
+/*@---------------------------------------------------------*/
+
+#if DEV_BUS_TYPE == RT_PCI_INTERFACE
+			phydm_update_beam_pattern_type2(dm, sat_tab->update_beam_codeword, sat_tab->rfu_codeword_total_bit_num);
+			#else
+			odm_schedule_work_item(&sat_tab->hl_smart_antenna_workitem);
+#if 0
+			/*odm_stall_execution(1);*/
+#endif
+			#endif
+		} else if (sat_tab->fix_beam_pattern_en == 0)
+			PDM_SNPF(out_len, used, output + used, out_len - used,
+				 "[ SmartAnt ] Smart Antenna: Enable\n");
+
+	} else if (dm_value[0] == 2) { /*set latch time*/
+
+		sat_tab->latch_time = dm_value[1];
+		PHYDM_DBG(dm, DBG_ANT_DIV, "[ SmartAnt ]  latch_time =0x%x\n",
+			  sat_tab->latch_time);
+	} else if (dm_value[0] == 3) {
+		sat_tab->fix_training_num_en = dm_value[1];
+
+		if (sat_tab->fix_training_num_en == 1) {
+			sat_tab->per_beam_training_pkt_num = (u8)dm_value[2];
+			sat_tab->decision_holding_period = (u8)dm_value[3];
+
+			PDM_SNPF(out_len, used, output + used, out_len - used,
+				 "[SmtAnt] Fix_train_en = (( %d )), train_pkt_num = (( %d )), holding_period = (( %d )),\n",
+				 sat_tab->fix_training_num_en,
+				 sat_tab->per_beam_training_pkt_num,
+				 sat_tab->decision_holding_period);
+
+		} else if (sat_tab->fix_training_num_en == 0) {
+			PDM_SNPF(out_len, used, output + used, out_len - used,
+				 "[ SmartAnt ]  AUTO per_beam_training_pkt_num\n");
+		}
+	} else if (dm_value[0] == 4) {
+		#if 0
+		if (dm_value[1] == 1) {
+			sat_tab->ant_num = 1;
+			sat_tab->first_train_ant = MAIN_ANT;
+
+		} else if (dm_value[1] == 2) {
+			sat_tab->ant_num = 1;
+			sat_tab->first_train_ant = AUX_ANT;
+
+		} else if (dm_value[1] == 3) {
+			sat_tab->ant_num = 2;
+			sat_tab->first_train_ant = MAIN_ANT;
+		}
+
+		PDM_SNPF((output + used, out_len - used,
+			 "[ SmartAnt ]  Set ant Num = (( %d )), first_train_ant = (( %d ))\n",
+			 sat_tab->ant_num, (sat_tab->first_train_ant - 1)));
+		#endif
+	} else if (dm_value[0] == 5) { /*set beam set table*/
+
+		PHYDM_SSCANF(input[4], DCMD_HEX, &dm_value[3]);
+		PHYDM_SSCANF(input[5], DCMD_HEX, &dm_value[4]);
+
+		if (dm_value[1] == 1) { /*@2G*/
+			if (dm_value[2] < SUPPORT_BEAM_SET_PATTERN_NUM) {
+				sat_tab->rfu_codeword_table_2g[dm_value[2]][0] = (u8)dm_value[3];
+				sat_tab->rfu_codeword_table_2g[dm_value[2]][1] = (u8)dm_value[4];
+				PDM_SNPF(out_len, used, output + used,
+					 out_len - used,
+					 "[SmtAnt] Set 2G Table[%d] = [A:0x%x, B:0x%x]\n",
+					 dm_value[2], dm_value[3], dm_value[4]);
+			}
+
+		} else if (dm_value[1] == 2) { /*@5G*/
+			if (dm_value[2] < SUPPORT_BEAM_SET_PATTERN_NUM) {
+				sat_tab->rfu_codeword_table_5g[dm_value[2]][0] = (u8)dm_value[3];
+				sat_tab->rfu_codeword_table_5g[dm_value[2]][1] = (u8)dm_value[4];
+				PDM_SNPF(out_len, used, output + used,
+					 out_len - used,
+					 "[SmtAnt] Set5G Table[%d] = [A:0x%x, B:0x%x]\n",
+					 dm_value[2], dm_value[3], dm_value[4]);
+			}
+		} else if (dm_value[1] == 0) {
+			PDM_SNPF(out_len, used, output + used, out_len - used,
+				 "[SmtAnt] 2G Beam Table==============>\n");
+			for (i = 0; i < sat_tab->total_beam_set_num_2g; i++) {
+				PDM_SNPF(out_len, used, output + used,
+					 out_len - used,
+					 "2G Table[%d] = [A:0x%x, B:0x%x]\n", i,
+					 sat_tab->rfu_codeword_table_2g[i][0],
+					 sat_tab->rfu_codeword_table_2g[i][1]);
+			}
+			PDM_SNPF(out_len, used, output + used, out_len - used,
+				 "[SmtAnt] 5G Beam Table==============>\n");
+			for (i = 0; i < sat_tab->total_beam_set_num_5g; i++) {
+				PDM_SNPF(out_len, used, output + used,
+					 out_len - used,
+					 "5G Table[%d] = [A:0x%x, B:0x%x]\n", i,
+					 sat_tab->rfu_codeword_table_5g[i][0],
+					 sat_tab->rfu_codeword_table_5g[i][1]);
+			}
+		}
+
+	} else if (dm_value[0] == 6) {
+#if 0
+		if (dm_value[1] == 0) {
+			if (dm_value[2] < SUPPORT_BEAM_SET_PATTERN_NUM) {
+				sat_tab->rfu_codeword_table_5g[dm_value[2] ][0] = (u8)dm_value[3];
+				sat_tab->rfu_codeword_table_5g[dm_value[2] ][1] = (u8)dm_value[4];
+				PDM_SNPF((output + used, out_len - used,
+					 "[SmtAnt] Set5G Table[%d] = [A:0x%x, B:0x%x]\n",
+					 dm_value[2], dm_value[3],
+					 dm_value[4]));
+			}
+		} else {
+			for (i = 0; i < sat_tab->total_beam_set_num_5g; i++) {
+				PDM_SNPF((output + used, out_len - used,
+					 "[SmtAnt] Read 5G Table[%d] = [A:0x%x, B:0x%x]\n",
+					 i,
+					 sat_tab->rfu_codeword_table_5g[i][0],
+					 sat_tab->rfu_codeword_table_5g[i][1]));
+			}
+		}
+#endif
+	} else if (dm_value[0] == 7) {
+		if (dm_value[1] == 1) {
+			sat_tab->total_beam_set_num_2g = (u8)(dm_value[2]);
+			PDM_SNPF(out_len, used, output + used, out_len - used,
+				 "[ SmartAnt ] total_beam_set_num_2g = ((%d))\n",
+				 sat_tab->total_beam_set_num_2g);
+
+		} else if (dm_value[1] == 2) {
+			sat_tab->total_beam_set_num_5g = (u8)(dm_value[2]);
+			PDM_SNPF(out_len, used, output + used, out_len - used,
+				 "[ SmartAnt ] total_beam_set_num_5g = ((%d))\n",
+				 sat_tab->total_beam_set_num_5g);
+		} else if (dm_value[1] == 0) {
+			PDM_SNPF(out_len, used, output + used, out_len - used,
+				 "[ SmartAnt ] Show total_beam_set_num{2g,5g} = {%d,%d}\n",
+				 sat_tab->total_beam_set_num_2g,
+				 sat_tab->total_beam_set_num_5g);
+		}
+
+	} else if (dm_value[0] == 8) {
+		if (dm_value[1] == 1) {
+			sat_tab->rfu_protocol_delay_time = (u16)(dm_value[2]);
+			PDM_SNPF(out_len, used, output + used, out_len - used,
+				 "[SmtAnt] Set rfu_protocol_delay_time = ((%d))\n",
+				 sat_tab->rfu_protocol_delay_time);
+		} else if (dm_value[1] == 0) {
+			PDM_SNPF(out_len, used, output + used, out_len - used,
+				 "[SmtAnt] Read rfu_protocol_delay_time = ((%d))\n",
+				 sat_tab->rfu_protocol_delay_time);
+		}
+	}
+
+	*_used = used;
+	*_out_len = out_len;
+}
+
+void phydm_set_rfu_beam_pattern_type2(
+	void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct smt_ant_honbo *sat_tab = &dm->dm_sat_table;
+
+	if (dm->ant_div_type != HL_SW_SMART_ANT_TYPE2)
+		return;
+
+	PHYDM_DBG(dm, DBG_ANT_DIV, "Training beam_set index = (( 0x%x ))\n",
+		  sat_tab->fast_training_beam_num);
+	sat_tab->update_beam_codeword = phydm_construct_hb_rfu_codeword_type2(dm, sat_tab->fast_training_beam_num);
+
+	#if DEV_BUS_TYPE == RT_PCI_INTERFACE
+	phydm_update_beam_pattern_type2(dm, sat_tab->update_beam_codeword, sat_tab->rfu_codeword_total_bit_num);
+	#else
+	odm_schedule_work_item(&sat_tab->hl_smart_antenna_workitem);
+#if 0
+	/*odm_stall_execution(1);*/
+#endif
+	#endif
+}
+
+void phydm_fast_ant_training_hl_smart_antenna_type2(
+	void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct smt_ant_honbo *sat_tab = &dm->dm_sat_table;
+	struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
+	struct sw_antenna_switch *dm_swat_table = &dm->dm_swat_table;
+	u32 codeword = 0;
+	u8 i = 0, j = 0;
+	u8 avg_rssi_tmp;
+	u8 avg_rssi_tmp_ma;
+	u8 max_beam_ant_rssi = 0;
+	u8 rssi_target_beam = 0, target_beam_max_rssi = 0;
+	u8 evm1ss_target_beam = 0, evm2ss_target_beam = 0;
+	u32 target_beam_max_evm1ss = 0, target_beam_max_evm2ss = 0;
+	u32 beam_tmp;
+	u8 per_beam_val_diff_tmp = 0, training_pkt_num_offset;
+	u32 avg_evm2ss[2] = {0}, avg_evm2ss_sum = 0;
+	u32 avg_evm1ss = 0;
+	u32 beam_path_evm_2ss_cnt_all = 0; /*sum of all 2SS-pattern cnt*/
+	u32 beam_path_evm_1ss_cnt_all = 0; /*sum of all 1SS-pattern cnt*/
+	u8 decision_type;
+
+	if (!dm->is_linked) {
+		PHYDM_DBG(dm, DBG_ANT_DIV, "[No Link!!!]\n");
+
+		if (fat_tab->is_become_linked == true) {
+			sat_tab->decision_holding_period = 0;
+			PHYDM_DBG(dm, DBG_ANT_DIV, "Link->no Link\n");
+			fat_tab->fat_state = FAT_BEFORE_LINK_STATE;
+			PHYDM_DBG(dm, DBG_ANT_DIV,
+				  "change to (( %d )) FAT_state\n",
+				  fat_tab->fat_state);
+			fat_tab->is_become_linked = dm->is_linked;
+		}
+		return;
+
+	} else {
+		if (fat_tab->is_become_linked == false) {
+			PHYDM_DBG(dm, DBG_ANT_DIV, "[Linked !!!]\n");
+
+			fat_tab->fat_state = FAT_PREPARE_STATE;
+			PHYDM_DBG(dm, DBG_ANT_DIV,
+				  "change to (( %d )) FAT_state\n",
+				  fat_tab->fat_state);
+
+			/*sat_tab->fast_training_beam_num = 0;*/
+			/*phydm_set_rfu_beam_pattern_type2(dm);*/
+
+			fat_tab->is_become_linked = dm->is_linked;
+		}
+	}
+
+#if 0
+	/*PHYDM_DBG(dm, DBG_ANT_DIV, "HL Smart ant Training: state (( %d ))\n", fat_tab->fat_state);*/
+#endif
+
+	/* @[DECISION STATE] */
+	/*@=======================================================================================*/
+	if (fat_tab->fat_state == FAT_DECISION_STATE) {
+		PHYDM_DBG(dm, DBG_ANT_DIV, "[ 3. In Decision state]\n");
+
+		/*@compute target beam in each antenna*/
+
+		for (j = 0; j < (sat_tab->total_beam_set_num); j++) {
+			/*@[Decision1: RSSI]-------------------------------------------------------------------*/
+			if (sat_tab->statistic_pkt_cnt[j] == 0) { /*@if new RSSI = 0 -> MA_RSSI-=2*/
+				avg_rssi_tmp = sat_tab->beam_set_avg_rssi_pre[j];
+				avg_rssi_tmp = (avg_rssi_tmp >= 2) ? (avg_rssi_tmp - 2) : avg_rssi_tmp;
+				avg_rssi_tmp_ma = avg_rssi_tmp;
+			} else {
+				avg_rssi_tmp = (u8)((sat_tab->beam_set_rssi_avg_sum[j]) / (sat_tab->statistic_pkt_cnt[j]));
+				avg_rssi_tmp_ma = (avg_rssi_tmp + sat_tab->beam_set_avg_rssi_pre[j]) >> 1;
+			}
+
+			sat_tab->beam_set_avg_rssi_pre[j] = avg_rssi_tmp;
+
+			if (avg_rssi_tmp > target_beam_max_rssi) {
+				rssi_target_beam = j;
+				target_beam_max_rssi = avg_rssi_tmp;
+			}
+
+			/*@[Decision2: EVM 2ss]-------------------------------------------------------------------*/
+			if (sat_tab->beam_path_evm_2ss_cnt[j] != 0) {
+				avg_evm2ss[0] = sat_tab->beam_path_evm_2ss_sum[j][0] / sat_tab->beam_path_evm_2ss_cnt[j];
+				avg_evm2ss[1] = sat_tab->beam_path_evm_2ss_sum[j][1] / sat_tab->beam_path_evm_2ss_cnt[j];
+				avg_evm2ss_sum = avg_evm2ss[0] + avg_evm2ss[1];
+				beam_path_evm_2ss_cnt_all += sat_tab->beam_path_evm_2ss_cnt[j];
+
+				sat_tab->beam_set_avg_evm_2ss_pre[j] = (u8)avg_evm2ss_sum;
+			}
+
+			if (avg_evm2ss_sum > target_beam_max_evm2ss) {
+				evm2ss_target_beam = j;
+				target_beam_max_evm2ss = avg_evm2ss_sum;
+			}
+
+			/*@[Decision3: EVM 1ss]-------------------------------------------------------------------*/
+			if (sat_tab->beam_path_evm_1ss_cnt[j] != 0) {
+				avg_evm1ss = sat_tab->beam_path_evm_1ss_sum[j] / sat_tab->beam_path_evm_1ss_cnt[j];
+				beam_path_evm_1ss_cnt_all += sat_tab->beam_path_evm_1ss_cnt[j];
+
+				sat_tab->beam_set_avg_evm_1ss_pre[j] = (u8)avg_evm1ss;
+			}
+
+			if (avg_evm1ss > target_beam_max_evm1ss) {
+				evm1ss_target_beam = j;
+				target_beam_max_evm1ss = avg_evm1ss;
+			}
+
+			PHYDM_DBG(dm, DBG_ANT_DIV,
+				  "Beam[%d] Pkt_cnt=(( %d )), avg{MA,rssi}={%d, %d}, EVM1={%d}, EVM2={%d, %d, %d}\n",
+				  j, sat_tab->statistic_pkt_cnt[j],
+				  avg_rssi_tmp_ma, avg_rssi_tmp, avg_evm1ss,
+				  avg_evm2ss[0], avg_evm2ss[1], avg_evm2ss_sum);
+
+			/*reset counter value*/
+			sat_tab->beam_set_rssi_avg_sum[j] = 0;
+			sat_tab->beam_path_rssi_sum[j][0] = 0;
+			sat_tab->beam_path_rssi_sum[j][1] = 0;
+			sat_tab->statistic_pkt_cnt[j] = 0;
+
+			sat_tab->beam_path_evm_2ss_sum[j][0] = 0;
+			sat_tab->beam_path_evm_2ss_sum[j][1] = 0;
+			sat_tab->beam_path_evm_2ss_cnt[j] = 0;
+
+			sat_tab->beam_path_evm_1ss_sum[j] = 0;
+			sat_tab->beam_path_evm_1ss_cnt[j] = 0;
+		}
+
+		/*@[Joint Decision]-------------------------------------------------------------------*/
+		PHYDM_DBG(dm, DBG_ANT_DIV,
+			  "--->1.[RSSI]      Target Beam(( %d )) RSSI_max=((%d))\n",
+			  rssi_target_beam, target_beam_max_rssi);
+		PHYDM_DBG(dm, DBG_ANT_DIV,
+			  "--->2.[Evm2SS] Target Beam(( %d )) EVM2SS_max=((%d))\n",
+			  evm2ss_target_beam, target_beam_max_evm2ss);
+		PHYDM_DBG(dm, DBG_ANT_DIV,
+			  "--->3.[Evm1SS] Target Beam(( %d )) EVM1SS_max=((%d))\n",
+			  evm1ss_target_beam, target_beam_max_evm1ss);
+
+		if (target_beam_max_rssi <= 10) {
+			sat_tab->rx_idle_beam_set_idx = rssi_target_beam;
+			decision_type = 1;
+		} else {
+			if (beam_path_evm_2ss_cnt_all != 0) {
+				sat_tab->rx_idle_beam_set_idx = evm2ss_target_beam;
+				decision_type = 2;
+			} else if (beam_path_evm_1ss_cnt_all != 0) {
+				sat_tab->rx_idle_beam_set_idx = evm1ss_target_beam;
+				decision_type = 3;
+			} else {
+				sat_tab->rx_idle_beam_set_idx = rssi_target_beam;
+				decision_type = 1;
+			}
+		}
+
+		PHYDM_DBG(dm, DBG_ANT_DIV,
+			  "---> Decision_type=((%d)), Final Target Beam(( %d ))\n",
+			  decision_type, sat_tab->rx_idle_beam_set_idx);
+
+		/*@Calculate packet counter offset*/
+		for (j = 0; j < (sat_tab->total_beam_set_num); j++) {
+			if (decision_type == 1) {
+				per_beam_val_diff_tmp = target_beam_max_rssi - sat_tab->beam_set_avg_rssi_pre[j];
+
+			} else if (decision_type == 2) {
+				per_beam_val_diff_tmp = ((u8)target_beam_max_evm2ss - sat_tab->beam_set_avg_evm_2ss_pre[j]) >> 1;
+			} else if (decision_type == 3) {
+				per_beam_val_diff_tmp = (u8)target_beam_max_evm1ss - sat_tab->beam_set_avg_evm_1ss_pre[j];
+			}
+			sat_tab->beam_set_train_val_diff[j] = per_beam_val_diff_tmp;
+			PHYDM_DBG(dm, DBG_ANT_DIV,
+				  "Beam_Set[%d]: diff= ((%d))\n", j,
+				  per_beam_val_diff_tmp);
+		}
+
+		/*set beam in each antenna*/
+		phydm_update_rx_idle_beam_type2(dm);
+		fat_tab->fat_state = FAT_PREPARE_STATE;
+	}
+	/* @[TRAINING STATE] */
+	else if (fat_tab->fat_state == FAT_TRAINING_STATE) {
+		PHYDM_DBG(dm, DBG_ANT_DIV, "[ 2. In Training state]\n");
+
+		PHYDM_DBG(dm, DBG_ANT_DIV,
+			  "curr_beam_idx = (( %d )), pre_beam_idx = (( %d ))\n",
+			  sat_tab->fast_training_beam_num,
+			  sat_tab->pre_fast_training_beam_num);
+
+		if (sat_tab->fast_training_beam_num > sat_tab->pre_fast_training_beam_num)
+
+			sat_tab->force_update_beam_en = 0;
+
+		else {
+			sat_tab->force_update_beam_en = 1;
+
+			sat_tab->pkt_counter = 0;
+			beam_tmp = sat_tab->fast_training_beam_num;
+			if (sat_tab->fast_training_beam_num >= ((u32)sat_tab->total_beam_set_num - 1)) {
+				PHYDM_DBG(dm, DBG_ANT_DIV,
+					  "[Timeout Update]  Beam_num (( %d )) -> (( decision ))\n",
+					  sat_tab->fast_training_beam_num);
+				fat_tab->fat_state = FAT_DECISION_STATE;
+				phydm_fast_ant_training_hl_smart_antenna_type2(dm);
+
+			} else {
+				sat_tab->fast_training_beam_num++;
+
+				PHYDM_DBG(dm, DBG_ANT_DIV,
+					  "[Timeout Update]  Beam_num (( %d )) -> (( %d ))\n",
+					  beam_tmp,
+					  sat_tab->fast_training_beam_num);
+				phydm_set_rfu_beam_pattern_type2(dm);
+				fat_tab->fat_state = FAT_TRAINING_STATE;
+			}
+		}
+		sat_tab->pre_fast_training_beam_num = sat_tab->fast_training_beam_num;
+		PHYDM_DBG(dm, DBG_ANT_DIV, "Update Pre_Beam =(( %d ))\n",
+			  sat_tab->pre_fast_training_beam_num);
+	}
+	/*  @[Prepare state] */
+	/*@=======================================================================================*/
+	else if (fat_tab->fat_state == FAT_PREPARE_STATE) {
+		PHYDM_DBG(dm, DBG_ANT_DIV, "\n\n[ 1. In Prepare state]\n");
+
+		if (dm->pre_traffic_load == dm->traffic_load) {
+			if (sat_tab->decision_holding_period != 0) {
+				PHYDM_DBG(dm, DBG_ANT_DIV,
+					  "Holding_period = (( %d )), return!!!\n",
+					  sat_tab->decision_holding_period);
+				sat_tab->decision_holding_period--;
+				return;
+			}
+		}
+
+		/* Set training packet number*/
+		if (sat_tab->fix_training_num_en == 0) {
+			switch (dm->traffic_load) {
+			case TRAFFIC_HIGH:
+				sat_tab->per_beam_training_pkt_num = 8;
+				sat_tab->decision_holding_period = 2;
+				break;
+			case TRAFFIC_MID:
+				sat_tab->per_beam_training_pkt_num = 6;
+				sat_tab->decision_holding_period = 3;
+				break;
+			case TRAFFIC_LOW:
+				sat_tab->per_beam_training_pkt_num = 3; /*ping 60000*/
+				sat_tab->decision_holding_period = 4;
+				break;
+			case TRAFFIC_ULTRA_LOW:
+				sat_tab->per_beam_training_pkt_num = 1;
+				sat_tab->decision_holding_period = 6;
+				break;
+			default:
+				break;
+			}
+		}
+
+		PHYDM_DBG(dm, DBG_ANT_DIV,
+			  "TrafficLoad = (( %d )), Fix_beam = (( %d )), per_beam_training_pkt_num = (( %d )), decision_holding_period = ((%d))\n",
+			  dm->traffic_load, sat_tab->fix_training_num_en,
+			  sat_tab->per_beam_training_pkt_num,
+			  sat_tab->decision_holding_period);
+
+		/*@Beam_set number*/
+		if (*dm->band_type == ODM_BAND_5G) {
+			sat_tab->total_beam_set_num = sat_tab->total_beam_set_num_5g;
+			PHYDM_DBG(dm, DBG_ANT_DIV, "5G beam_set num = ((%d))\n",
+				  sat_tab->total_beam_set_num);
+		} else {
+			sat_tab->total_beam_set_num = sat_tab->total_beam_set_num_2g;
+			PHYDM_DBG(dm, DBG_ANT_DIV, "2G beam_set num = ((%d))\n",
+				  sat_tab->total_beam_set_num);
+		}
+
+		for (j = 0; j < (sat_tab->total_beam_set_num); j++) {
+			training_pkt_num_offset = sat_tab->beam_set_train_val_diff[j];
+
+			if (sat_tab->per_beam_training_pkt_num > training_pkt_num_offset)
+				sat_tab->beam_set_train_cnt[j] = sat_tab->per_beam_training_pkt_num - training_pkt_num_offset;
+			else
+				sat_tab->beam_set_train_cnt[j] = 1;
+
+			PHYDM_DBG(dm, DBG_ANT_DIV,
+				  "Beam_Set[ %d ] training_pkt_offset = ((%d)), training_pkt_num = ((%d))\n",
+				  j, sat_tab->beam_set_train_val_diff[j],
+				  sat_tab->beam_set_train_cnt[j]);
+		}
+
+		sat_tab->pre_beacon_counter = sat_tab->beacon_counter;
+		sat_tab->update_beam_idx = 0;
+		sat_tab->pkt_counter = 0;
+
+		sat_tab->fast_training_beam_num = 0;
+		phydm_set_rfu_beam_pattern_type2(dm);
+		sat_tab->pre_fast_training_beam_num = sat_tab->fast_training_beam_num;
+		fat_tab->fat_state = FAT_TRAINING_STATE;
+	}
+}
+
+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
+
+void phydm_beam_switch_workitem_callback(
+	void *context)
+{
+	void *adapter = (void *)context;
+	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter));
+	struct dm_struct *dm = &hal_data->DM_OutSrc;
+	struct smt_ant_honbo *sat_tab = &dm->dm_sat_table;
+
+#if DEV_BUS_TYPE != RT_PCI_INTERFACE
+	sat_tab->pkt_skip_statistic_en = 1;
+#endif
+	PHYDM_DBG(dm, DBG_ANT_DIV,
+		  "[ SmartAnt ] Beam Switch Workitem Callback, pkt_skip_statistic_en = (( %d ))\n",
+		  sat_tab->pkt_skip_statistic_en);
+
+	phydm_update_beam_pattern_type2(dm, sat_tab->update_beam_codeword, sat_tab->rfu_codeword_total_bit_num);
+
+#if DEV_BUS_TYPE != RT_PCI_INTERFACE
+#if 0
+	/*odm_stall_execution(sat_tab->latch_time);*/
+#endif
+	sat_tab->pkt_skip_statistic_en = 0;
+#endif
+	PHYDM_DBG(dm, DBG_ANT_DIV,
+		  "pkt_skip_statistic_en = (( %d )), latch_time = (( %d ))\n",
+		  sat_tab->pkt_skip_statistic_en, sat_tab->latch_time);
+}
+
+void phydm_beam_decision_workitem_callback(
+	void *context)
+{
+	void *adapter = (void *)context;
+	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter));
+	struct dm_struct *dm = &hal_data->DM_OutSrc;
+
+	PHYDM_DBG(dm, DBG_ANT_DIV,
+		  "[ SmartAnt ] Beam decision Workitem Callback\n");
+	phydm_fast_ant_training_hl_smart_antenna_type2(dm);
+}
+#endif
+
+void phydm_process_rssi_for_hb_smtant_type2(
+	void *dm_void,
+	void *phy_info_void,
+	void *pkt_info_void,
+	u8 rssi_avg)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct phydm_phyinfo_struct *phy_info = (struct phydm_phyinfo_struct *)phy_info_void;
+	struct phydm_perpkt_info_struct *pktinfo = (struct phydm_perpkt_info_struct *)pkt_info_void;
+	struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
+	struct smt_ant_honbo *sat_tab = &dm->dm_sat_table;
+	u8 train_pkt_number;
+	u32 beam_tmp;
+	u8 rx_power_ant0 = phy_info->rx_mimo_signal_strength[0];
+	u8 rx_power_ant1 = phy_info->rx_mimo_signal_strength[1];
+	u8 rx_evm_ant0 = phy_info->rx_mimo_evm_dbm[0];
+	u8 rx_evm_ant1 = phy_info->rx_mimo_evm_dbm[1];
+
+	/*@[Beacon]*/
+	if (pktinfo->is_packet_beacon) {
+		sat_tab->beacon_counter++;
+		PHYDM_DBG(dm, DBG_ANT_DIV,
+			  "MatchBSSID_beacon_counter = ((%d))\n",
+			  sat_tab->beacon_counter);
+
+		if (sat_tab->beacon_counter >= sat_tab->pre_beacon_counter + 2) {
+			sat_tab->update_beam_idx++;
+			PHYDM_DBG(dm, DBG_ANT_DIV,
+				  "pre_beacon_counter = ((%d)), pkt_counter = ((%d)), update_beam_idx = ((%d))\n",
+				  sat_tab->pre_beacon_counter,
+				  sat_tab->pkt_counter,
+				  sat_tab->update_beam_idx);
+
+			sat_tab->pre_beacon_counter = sat_tab->beacon_counter;
+			sat_tab->pkt_counter = 0;
+		}
+	}
+	/*@[data]*/
+	else if (pktinfo->is_packet_to_self) {
+		if (sat_tab->pkt_skip_statistic_en == 0) {
+			PHYDM_DBG(dm, DBG_ANT_DIV,
+				  "ID[%d] pkt_cnt=((%d)): Beam_set = ((%d)), RSSI{A,B,avg} = {%d, %d, %d}\n",
+				  pktinfo->station_id, sat_tab->pkt_counter,
+				  sat_tab->fast_training_beam_num,
+				  rx_power_ant0, rx_power_ant1, rssi_avg);
+
+			PHYDM_DBG(dm, DBG_ANT_DIV,
+				  "Rate_ss = ((%d)), EVM{A,B} = {%d, %d}, RX Rate =",
+				  pktinfo->rate_ss, rx_evm_ant0, rx_evm_ant1);
+			phydm_print_rate(dm, dm->rx_rate, DBG_ANT_DIV);
+
+			if (sat_tab->pkt_counter >= 1) /*packet skip count*/
+			{
+				sat_tab->beam_set_rssi_avg_sum[sat_tab->fast_training_beam_num] += rssi_avg;
+				sat_tab->statistic_pkt_cnt[sat_tab->fast_training_beam_num]++;
+
+				sat_tab->beam_path_rssi_sum[sat_tab->fast_training_beam_num][0] += rx_power_ant0;
+				sat_tab->beam_path_rssi_sum[sat_tab->fast_training_beam_num][1] += rx_power_ant1;
+
+				if (pktinfo->rate_ss == 2) {
+					sat_tab->beam_path_evm_2ss_sum[sat_tab->fast_training_beam_num][0] += rx_evm_ant0;
+					sat_tab->beam_path_evm_2ss_sum[sat_tab->fast_training_beam_num][1] += rx_evm_ant1;
+					sat_tab->beam_path_evm_2ss_cnt[sat_tab->fast_training_beam_num]++;
+				} else {
+					sat_tab->beam_path_evm_1ss_sum[sat_tab->fast_training_beam_num] += rx_evm_ant0;
+					sat_tab->beam_path_evm_1ss_cnt[sat_tab->fast_training_beam_num]++;
+				}
+			}
+
+			sat_tab->pkt_counter++;
+
+			train_pkt_number = sat_tab->beam_set_train_cnt[sat_tab->fast_training_beam_num];
+
+			if (sat_tab->pkt_counter >= train_pkt_number) {
+				sat_tab->update_beam_idx++;
+				PHYDM_DBG(dm, DBG_ANT_DIV,
+					  "pre_beacon_counter = ((%d)), Update_new_beam = ((%d))\n",
+					  sat_tab->pre_beacon_counter,
+					  sat_tab->update_beam_idx);
+
+				sat_tab->pre_beacon_counter = sat_tab->beacon_counter;
+				sat_tab->pkt_counter = 0;
+			}
+		}
+	}
+
+	if (sat_tab->update_beam_idx > 0) {
+		sat_tab->update_beam_idx = 0;
+
+		if (sat_tab->fast_training_beam_num >= ((u32)sat_tab->total_beam_set_num - 1)) {
+			fat_tab->fat_state = FAT_DECISION_STATE;
+
+			#if DEV_BUS_TYPE == RT_PCI_INTERFACE
+			phydm_fast_ant_training_hl_smart_antenna_type2(dm); /*@go to make decision*/
+			#else
+			odm_schedule_work_item(&sat_tab->hl_smart_antenna_decision_workitem);
+			#endif
+
+		} else {
+			beam_tmp = sat_tab->fast_training_beam_num;
+			sat_tab->fast_training_beam_num++;
+			PHYDM_DBG(dm, DBG_ANT_DIV,
+				  "Update Beam_num (( %d )) -> (( %d ))\n",
+				  beam_tmp, sat_tab->fast_training_beam_num);
+			phydm_set_rfu_beam_pattern_type2(dm);
+			sat_tab->pre_fast_training_beam_num = sat_tab->fast_training_beam_num;
+
+			fat_tab->fat_state = FAT_TRAINING_STATE;
+		}
+	}
+}
+#endif
+
+#if (defined(CONFIG_HL_SMART_ANTENNA_TYPE1))
+
+void phydm_hl_smart_ant_type1_init_8821a(
+	void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct smt_ant_honbo *sat_tab = &dm->dm_sat_table;
+	struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
+	u32 value32;
+
+	PHYDM_DBG(dm, DBG_ANT_DIV,
+		  "***8821A SmartAnt_Init => ant_div_type=[Hong-Lin Smart ant Type1]\n");
+
+#if 0
+	/* @---------------------------------------- */
+	/* @GPIO 2-3 for Beam control */
+	/* reg0x66[2]=0 */
+	/* reg0x44[27:26] = 0 */
+	/* reg0x44[23:16]  enable_output for P_GPIO[7:0] */
+	/* reg0x44[15:8]  output_value for P_GPIO[7:0] */
+	/* reg0x40[1:0] = 0  GPIO function */
+	/* @------------------------------------------ */
+#endif
+
+	/*@GPIO setting*/
+	odm_set_mac_reg(dm, R_0x64, BIT(18), 0);
+	odm_set_mac_reg(dm, R_0x44, BIT(27) | BIT(26), 0);
+	odm_set_mac_reg(dm, R_0x44, BIT(19) | BIT(18), 0x3); /*@enable_output for P_GPIO[3:2]*/
+#if 0
+	/*odm_set_mac_reg(dm, R_0x44, BIT(11)|BIT(10), 0);*/ /*output value*/
+#endif
+	odm_set_mac_reg(dm, R_0x40, BIT(1) | BIT(0), 0); /*@GPIO function*/
+
+	/*@Hong_lin smart antenna HW setting*/
+	sat_tab->rfu_codeword_total_bit_num = 24; /*@max=32*/
+	sat_tab->rfu_each_ant_bit_num = 4;
+	sat_tab->beam_patten_num_each_ant = 4;
+
+#if DEV_BUS_TYPE == RT_SDIO_INTERFACE
+	sat_tab->latch_time = 100; /*@mu sec*/
+#elif DEV_BUS_TYPE == RT_USB_INTERFACE
+	sat_tab->latch_time = 100; /*@mu sec*/
+#endif
+	sat_tab->pkt_skip_statistic_en = 0;
+
+	sat_tab->ant_num = 1; /*@max=8*/
+	sat_tab->ant_num_total = NUM_ANTENNA_8821A;
+	sat_tab->first_train_ant = MAIN_ANT;
+
+	sat_tab->rfu_codeword_table[0] = 0x0;
+	sat_tab->rfu_codeword_table[1] = 0x4;
+	sat_tab->rfu_codeword_table[2] = 0x8;
+	sat_tab->rfu_codeword_table[3] = 0xc;
+
+	sat_tab->rfu_codeword_table_5g[0] = 0x1;
+	sat_tab->rfu_codeword_table_5g[1] = 0x2;
+	sat_tab->rfu_codeword_table_5g[2] = 0x4;
+	sat_tab->rfu_codeword_table_5g[3] = 0x8;
+
+	sat_tab->fix_beam_pattern_en = 0;
+	sat_tab->decision_holding_period = 0;
+
+	/*@beam training setting*/
+	sat_tab->pkt_counter = 0;
+	sat_tab->per_beam_training_pkt_num = 10;
+
+	/*set default beam*/
+	sat_tab->fast_training_beam_num = 0;
+	sat_tab->pre_fast_training_beam_num = sat_tab->fast_training_beam_num;
+	phydm_set_all_ant_same_beam_num(dm);
+
+	fat_tab->fat_state = FAT_BEFORE_LINK_STATE;
+
+	odm_set_bb_reg(dm, R_0xca4, MASKDWORD, 0x01000100);
+	odm_set_bb_reg(dm, R_0xca8, MASKDWORD, 0x01000100);
+
+	/*@[BB] FAT setting*/
+	odm_set_bb_reg(dm, R_0xc08, BIT(18) | BIT(17) | BIT(16), sat_tab->ant_num);
+	odm_set_bb_reg(dm, R_0xc08, BIT(31), 0); /*@increase ant num every FAT period 0:+1, 1+2*/
+	odm_set_bb_reg(dm, R_0x8c4, BIT(2) | BIT(1), 1); /*@change cca antenna timming threshold if no CCA occurred: 0:200ms / 1:100ms / 2:no use / 3: 300*/
+	odm_set_bb_reg(dm, R_0x8c4, BIT(0), 1); /*@FAT_watchdog_en*/
+
+	value32 = odm_get_mac_reg(dm, R_0x7b4, MASKDWORD);
+	odm_set_mac_reg(dm, R_0x7b4, MASKDWORD, value32 | (BIT(16) | BIT(17))); /*Reg7B4[16]=1 enable antenna training */
+	/*Reg7B4[17]=1 enable  match MAC addr*/
+	odm_set_mac_reg(dm, R_0x7b4, 0xFFFF, 0); /*@Match MAC ADDR*/
+	odm_set_mac_reg(dm, R_0x7b0, MASKDWORD, 0);
+}
+
+u32 phydm_construct_hl_beam_codeword(
+	void *dm_void,
+	u32 *beam_pattern_idx,
+	u32 ant_num)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct smt_ant_honbo *sat_tab = &dm->dm_sat_table;
+	u32 codeword = 0;
+	u32 data_tmp;
+	u32 i;
+	u32 break_counter = 0;
+
+	if (ant_num < 8) {
+		for (i = 0; i < (sat_tab->ant_num_total); i++) {
+#if 0
+			/*PHYDM_DBG(dm,DBG_ANT_DIV, "beam_pattern_num[%x] = %x\n",i,beam_pattern_num[i] );*/
+#endif
+			if ((i < (sat_tab->first_train_ant - 1)) || break_counter >= sat_tab->ant_num) {
+				data_tmp = 0;
+			} else {
+				break_counter++;
+
+				if (beam_pattern_idx[i] == 0) {
+					if (*dm->band_type == ODM_BAND_5G)
+						data_tmp = sat_tab->rfu_codeword_table_5g[0];
+					else
+						data_tmp = sat_tab->rfu_codeword_table[0];
+
+				} else if (beam_pattern_idx[i] == 1) {
+					if (*dm->band_type == ODM_BAND_5G)
+						data_tmp = sat_tab->rfu_codeword_table_5g[1];
+					else
+						data_tmp = sat_tab->rfu_codeword_table[1];
+
+				} else if (beam_pattern_idx[i] == 2) {
+					if (*dm->band_type == ODM_BAND_5G)
+						data_tmp = sat_tab->rfu_codeword_table_5g[2];
+					else
+						data_tmp = sat_tab->rfu_codeword_table[2];
+
+				} else if (beam_pattern_idx[i] == 3) {
+					if (*dm->band_type == ODM_BAND_5G)
+						data_tmp = sat_tab->rfu_codeword_table_5g[3];
+					else
+						data_tmp = sat_tab->rfu_codeword_table[3];
+				}
+			}
+
+			codeword |= (data_tmp << (i * 4));
+		}
+	}
+
+	return codeword;
+}
+
+void phydm_update_beam_pattern(
+	void *dm_void,
+	u32 codeword,
+	u32 codeword_length)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct smt_ant_honbo *sat_tab = &dm->dm_sat_table;
+	u8 i;
+	boolean beam_ctrl_signal;
+	u32 one = 0x1;
+	u32 reg44_tmp_p, reg44_tmp_n, reg44_ori;
+	u8 devide_num = 4;
+
+	PHYDM_DBG(dm, DBG_ANT_DIV, "[ SmartAnt ] Set Beam Pattern =0x%x\n",
+		  codeword);
+
+	reg44_ori = odm_get_mac_reg(dm, R_0x44, MASKDWORD);
+	reg44_tmp_p = reg44_ori;
+#if 0
+	/*PHYDM_DBG(dm, DBG_ANT_DIV, "reg44_ori =0x%x\n", reg44_ori);*/
+#endif
+
+	devide_num = (sat_tab->rfu_protocol_type == 2) ? 6 : 4;
+
+	for (i = 0; i <= (codeword_length - 1); i++) {
+		beam_ctrl_signal = (boolean)((codeword & BIT(i)) >> i);
+
+		if (dm->debug_components & DBG_ANT_DIV) {
+			if (i == (codeword_length - 1))
+				pr_debug("%d ]\n", beam_ctrl_signal);
+			else if (i == 0)
+				pr_debug("Send codeword[1:%d] ---> [ %d ", codeword_length, beam_ctrl_signal);
+			else if ((i % devide_num) == (devide_num - 1))
+				pr_debug("%d  |  ", beam_ctrl_signal);
+			else
+				pr_debug("%d ", beam_ctrl_signal);
+		}
+
+		if (dm->support_ic_type == ODM_RTL8821) {
+			#if (RTL8821A_SUPPORT == 1)
+			reg44_tmp_p = reg44_ori & (~(BIT(11) | BIT(10))); /*@clean bit 10 & 11*/
+			reg44_tmp_p |= ((1 << 11) | (beam_ctrl_signal << 10));
+			reg44_tmp_n = reg44_ori & (~(BIT(11) | BIT(10)));
+
+#if 0
+			/*PHYDM_DBG(dm, DBG_ANT_DIV, "reg44_tmp_p =(( 0x%x )), reg44_tmp_n = (( 0x%x ))\n", reg44_tmp_p, reg44_tmp_n);*/
+#endif
+			odm_set_mac_reg(dm, R_0x44, MASKDWORD, reg44_tmp_p);
+			odm_set_mac_reg(dm, R_0x44, MASKDWORD, reg44_tmp_n);
+			#endif
+		}
+		#if (RTL8822B_SUPPORT == 1)
+		else if (dm->support_ic_type == ODM_RTL8822B) {
+			if (sat_tab->rfu_protocol_type == 2) {
+				reg44_tmp_p = reg44_tmp_p & ~(BIT(8)); /*@clean bit 8*/
+				reg44_tmp_p = reg44_tmp_p ^ BIT(9); /*@get new clk high/low, exclusive-or*/
+
+				reg44_tmp_p |= (beam_ctrl_signal << 8);
+
+				odm_set_mac_reg(dm, R_0x44, MASKDWORD, reg44_tmp_p);
+				ODM_delay_us(10);
+#if 0
+				/*PHYDM_DBG(dm, DBG_ANT_DIV, "reg44 =(( 0x%x )), reg44[9:8] = ((%x)), beam_ctrl_signal =((%x))\n", reg44_tmp_p, ((reg44_tmp_p & 0x300)>>8), beam_ctrl_signal);*/
+#endif
+
+			} else {
+				reg44_tmp_p = reg44_ori & (~(BIT(9) | BIT(8))); /*@clean bit 9 & 8*/
+				reg44_tmp_p |= ((1 << 9) | (beam_ctrl_signal << 8));
+				reg44_tmp_n = reg44_ori & (~(BIT(9) | BIT(8)));
+
+#if 0
+				/*PHYDM_DBG(dm, DBG_ANT_DIV, "reg44_tmp_p =(( 0x%x )), reg44_tmp_n = (( 0x%x ))\n", reg44_tmp_p, reg44_tmp_n); */
+#endif
+				odm_set_mac_reg(dm, R_0x44, MASKDWORD, reg44_tmp_p);
+				ODM_delay_us(10);
+				odm_set_mac_reg(dm, R_0x44, MASKDWORD, reg44_tmp_n);
+				ODM_delay_us(10);
+			}
+		}
+		#endif
+	}
+}
+
+void phydm_update_rx_idle_beam(
+	void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
+	struct smt_ant_honbo *sat_tab = &dm->dm_sat_table;
+	u32 i;
+
+	sat_tab->update_beam_codeword = phydm_construct_hl_beam_codeword(dm,
+									 &sat_tab->rx_idle_beam[0],
+									 sat_tab->ant_num);
+	PHYDM_DBG(dm, DBG_ANT_DIV,
+		  "Set target beam_pattern codeword = (( 0x%x ))\n",
+		  sat_tab->update_beam_codeword);
+
+	for (i = 0; i < (sat_tab->ant_num); i++)
+		PHYDM_DBG(dm, DBG_ANT_DIV,
+			  "[ Update Rx-Idle-Beam ] RxIdleBeam[%d] =%d\n", i,
+			  sat_tab->rx_idle_beam[i]);
+
+#if DEV_BUS_TYPE == RT_PCI_INTERFACE
+	phydm_update_beam_pattern(dm, sat_tab->update_beam_codeword, sat_tab->rfu_codeword_total_bit_num);
+#else
+	odm_schedule_work_item(&sat_tab->hl_smart_antenna_workitem);
+#if 0
+	/*odm_stall_execution(1);*/
+#endif
+#endif
+
+	sat_tab->pre_codeword = sat_tab->update_beam_codeword;
+}
+
+void phydm_hl_smart_ant_debug(
+	void *dm_void,
+	char input[][16],
+	u32 *_used,
+	char *output,
+	u32 *_out_len)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct smt_ant_honbo *sat_tab = &dm->dm_sat_table;
+	u32 used = *_used;
+	u32 out_len = *_out_len;
+	u32 one = 0x1;
+	u32 codeword_length = sat_tab->rfu_codeword_total_bit_num;
+	u32 beam_ctrl_signal, i;
+	u8 devide_num = 4;
+
+	if (dm_value[0] == 1) { /*@fix beam pattern*/
+
+		sat_tab->fix_beam_pattern_en = dm_value[1];
+
+		if (sat_tab->fix_beam_pattern_en == 1) {
+			sat_tab->fix_beam_pattern_codeword = dm_value[2];
+
+			if (sat_tab->fix_beam_pattern_codeword > (one << codeword_length)) {
+				PHYDM_DBG(dm, DBG_ANT_DIV,
+					  "[ SmartAnt ] Codeword overflow, Current codeword is ((0x%x)), and should be less than ((%d))bit\n",
+					  sat_tab->fix_beam_pattern_codeword,
+					  codeword_length);
+
+				(sat_tab->fix_beam_pattern_codeword) &= 0xffffff;
+
+				PHYDM_DBG(dm, DBG_ANT_DIV,
+					  "[ SmartAnt ] Auto modify to (0x%x)\n",
+					  sat_tab->fix_beam_pattern_codeword);
+			}
+
+			sat_tab->update_beam_codeword = sat_tab->fix_beam_pattern_codeword;
+
+			/*@---------------------------------------------------------*/
+			PDM_SNPF(out_len, used, output + used, out_len - used,
+				 "Fix Beam Pattern\n");
+
+			devide_num = (sat_tab->rfu_protocol_type == 2) ? 6 : 4;
+
+			for (i = 0; i <= (codeword_length - 1); i++) {
+				beam_ctrl_signal = (boolean)((sat_tab->update_beam_codeword & BIT(i)) >> i);
+
+				if (i == (codeword_length - 1))
+					PDM_SNPF(out_len, used,
+						 output + used,
+						 out_len - used,
+						 "%d]\n",
+						 beam_ctrl_signal);
+				else if (i == 0)
+					PDM_SNPF(out_len, used,
+						 output + used,
+						 out_len - used,
+						 "Send Codeword[1:24] to RFU -> [%d",
+						 beam_ctrl_signal);
+				else if ((i % devide_num) == (devide_num - 1))
+					PDM_SNPF(out_len, used,
+						 output + used,
+						 out_len - used, "%d|",
+						 beam_ctrl_signal);
+				else
+					PDM_SNPF(out_len, used,
+						 output + used,
+						 out_len - used, "%d",
+						 beam_ctrl_signal);
+			}
+/*@---------------------------------------------------------*/
+
+			#if DEV_BUS_TYPE == RT_PCI_INTERFACE
+			phydm_update_beam_pattern(dm, sat_tab->update_beam_codeword, sat_tab->rfu_codeword_total_bit_num);
+			#else
+			odm_schedule_work_item(&sat_tab->hl_smart_antenna_workitem);
+#if 0
+			/*odm_stall_execution(1);*/
+#endif
+			#endif
+		} else if (sat_tab->fix_beam_pattern_en == 0)
+			PDM_SNPF(out_len, used, output + used, out_len - used,
+				 "[ SmartAnt ] Smart Antenna: Enable\n");
+
+	} else if (dm_value[0] == 2) { /*set latch time*/
+
+		sat_tab->latch_time = dm_value[1];
+		PHYDM_DBG(dm, DBG_ANT_DIV, "[ SmartAnt ]  latch_time =0x%x\n",
+			  sat_tab->latch_time);
+	} else if (dm_value[0] == 3) {
+		sat_tab->fix_training_num_en = dm_value[1];
+
+		if (sat_tab->fix_training_num_en == 1) {
+			sat_tab->per_beam_training_pkt_num = (u8)dm_value[2];
+			sat_tab->decision_holding_period = (u8)dm_value[3];
+
+			PDM_SNPF(out_len, used, output + used, out_len - used,
+				 "[SmartAnt][Dbg] Fix_train_en = (( %d )), train_pkt_num = (( %d )), holding_period = (( %d )),\n",
+				 sat_tab->fix_training_num_en,
+				 sat_tab->per_beam_training_pkt_num,
+				 sat_tab->decision_holding_period);
+
+		} else if (sat_tab->fix_training_num_en == 0) {
+			PDM_SNPF(out_len, used, output + used, out_len - used,
+				 "[ SmartAnt ]  AUTO per_beam_training_pkt_num\n");
+		}
+	} else if (dm_value[0] == 4) {
+		if (dm_value[1] == 1) {
+			sat_tab->ant_num = 1;
+			sat_tab->first_train_ant = MAIN_ANT;
+
+		} else if (dm_value[1] == 2) {
+			sat_tab->ant_num = 1;
+			sat_tab->first_train_ant = AUX_ANT;
+
+		} else if (dm_value[1] == 3) {
+			sat_tab->ant_num = 2;
+			sat_tab->first_train_ant = MAIN_ANT;
+		}
+
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "[ SmartAnt ]  Set ant Num = (( %d )), first_train_ant = (( %d ))\n",
+			 sat_tab->ant_num, (sat_tab->first_train_ant - 1));
+	} else if (dm_value[0] == 5) {
+		if (dm_value[1] <= 3) {
+			sat_tab->rfu_codeword_table[dm_value[1]] = dm_value[2];
+			PDM_SNPF(out_len, used, output + used, out_len - used,
+				 "[ SmartAnt ] Set Beam_2G: (( %d )), RFU codeword table = (( 0x%x ))\n",
+				 dm_value[1], dm_value[2]);
+		} else {
+			for (i = 0; i < 4; i++) {
+				PDM_SNPF(out_len, used, output + used,
+					 out_len - used,
+					 "[ SmartAnt ] Show Beam_2G: (( %d )), RFU codeword table = (( 0x%x ))\n",
+					 i, sat_tab->rfu_codeword_table[i]);
+			}
+		}
+	} else if (dm_value[0] == 6) {
+		if (dm_value[1] <= 3) {
+			sat_tab->rfu_codeword_table_5g[dm_value[1]] = dm_value[2];
+			PDM_SNPF(out_len, used, output + used, out_len - used,
+				 "[ SmartAnt ] Set Beam_5G: (( %d )), RFU codeword table = (( 0x%x ))\n",
+				 dm_value[1], dm_value[2]);
+		} else {
+			for (i = 0; i < 4; i++) {
+				PDM_SNPF(out_len, used, output + used,
+					 out_len - used,
+					 "[ SmartAnt ] Show Beam_5G: (( %d )), RFU codeword table = (( 0x%x ))\n",
+					 i, sat_tab->rfu_codeword_table_5g[i]);
+			}
+		}
+	} else if (dm_value[0] == 7) {
+		if (dm_value[1] <= 4) {
+			sat_tab->beam_patten_num_each_ant = dm_value[1];
+			PDM_SNPF(out_len, used, output + used, out_len - used,
+				 "[ SmartAnt ] Set Beam number = (( %d ))\n",
+				 sat_tab->beam_patten_num_each_ant);
+		} else {
+			PDM_SNPF(out_len, used, output + used, out_len - used,
+				 "[ SmartAnt ] Show Beam number = (( %d ))\n",
+				 sat_tab->beam_patten_num_each_ant);
+		}
+	}
+	*_used = used;
+	*_out_len = out_len;
+}
+
+void phydm_set_all_ant_same_beam_num(
+	void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct smt_ant_honbo *sat_tab = &dm->dm_sat_table;
+
+	if (dm->ant_div_type == HL_SW_SMART_ANT_TYPE1) { /*@2ant for 8821A*/
+
+		sat_tab->rx_idle_beam[0] = sat_tab->fast_training_beam_num;
+		sat_tab->rx_idle_beam[1] = sat_tab->fast_training_beam_num;
+	}
+
+	sat_tab->update_beam_codeword = phydm_construct_hl_beam_codeword(dm,
+									 &sat_tab->rx_idle_beam[0],
+									 sat_tab->ant_num);
+
+	PHYDM_DBG(dm, DBG_ANT_DIV,
+		  "[ SmartAnt ] Set all ant beam_pattern: codeword = (( 0x%x ))\n",
+		  sat_tab->update_beam_codeword);
+
+#if DEV_BUS_TYPE == RT_PCI_INTERFACE
+	phydm_update_beam_pattern(dm, sat_tab->update_beam_codeword, sat_tab->rfu_codeword_total_bit_num);
+#else
+	odm_schedule_work_item(&sat_tab->hl_smart_antenna_workitem);
+/*odm_stall_execution(1);*/
+#endif
+}
+
+void odm_fast_ant_training_hl_smart_antenna_type1(
+	void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct smt_ant_honbo *sat_tab = &dm->dm_sat_table;
+	struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
+	struct sw_antenna_switch *dm_swat_table = &dm->dm_swat_table;
+	u32 codeword = 0, i, j;
+	u32 target_ant;
+	u32 avg_rssi_tmp, avg_rssi_tmp_ma;
+	u32 target_ant_beam_max_rssi[SUPPORT_RF_PATH_NUM] = {0};
+	u32 max_beam_ant_rssi = 0;
+	u32 target_ant_beam[SUPPORT_RF_PATH_NUM] = {0};
+	u32 beam_tmp;
+	u8 next_ant;
+	u32 rssi_sorting_seq[SUPPORT_BEAM_PATTERN_NUM] = {0};
+	u32 rank_idx_seq[SUPPORT_BEAM_PATTERN_NUM] = {0};
+	u32 rank_idx_out[SUPPORT_BEAM_PATTERN_NUM] = {0};
+	u8 per_beam_rssi_diff_tmp = 0, training_pkt_num_offset;
+	u32 break_counter = 0;
+	u32 used_ant;
+
+	if (!dm->is_linked) {
+		PHYDM_DBG(dm, DBG_ANT_DIV, "[No Link!!!]\n");
+
+		if (fat_tab->is_become_linked == true) {
+			PHYDM_DBG(dm, DBG_ANT_DIV, "Link->no Link\n");
+			fat_tab->fat_state = FAT_BEFORE_LINK_STATE;
+			odm_ant_div_on_off(dm, ANTDIV_OFF, ANT_PATH_A);
+			odm_tx_by_tx_desc_or_reg(dm, TX_BY_REG);
+			PHYDM_DBG(dm, DBG_ANT_DIV,
+				  "change to (( %d )) FAT_state\n",
+				  fat_tab->fat_state);
+
+			fat_tab->is_become_linked = dm->is_linked;
+		}
+		return;
+
+	} else {
+		if (fat_tab->is_become_linked == false) {
+			PHYDM_DBG(dm, DBG_ANT_DIV, "[Linked !!!]\n");
+
+			fat_tab->fat_state = FAT_PREPARE_STATE;
+			PHYDM_DBG(dm, DBG_ANT_DIV,
+				  "change to (( %d )) FAT_state\n",
+				  fat_tab->fat_state);
+
+#if 0
+			/*sat_tab->fast_training_beam_num = 0;*/
+			/*phydm_set_all_ant_same_beam_num(dm);*/
+#endif
+
+			fat_tab->is_become_linked = dm->is_linked;
+		}
+	}
+
+	if (*fat_tab->p_force_tx_ant_by_desc == false) {
+		if (dm->is_one_entry_only == true)
+			odm_tx_by_tx_desc_or_reg(dm, TX_BY_REG);
+		else
+			odm_tx_by_tx_desc_or_reg(dm, TX_BY_DESC);
+	}
+
+#if 0
+	/*PHYDM_DBG(dm, DBG_ANT_DIV, "HL Smart ant Training: state (( %d ))\n", fat_tab->fat_state);*/
+#endif
+
+	/* @[DECISION STATE] */
+	/*@=======================================================================================*/
+	if (fat_tab->fat_state == FAT_DECISION_STATE) {
+		PHYDM_DBG(dm, DBG_ANT_DIV, "[ 3. In Decision state]\n");
+		phydm_fast_training_enable(dm, FAT_OFF);
+
+		break_counter = 0;
+		/*@compute target beam in each antenna*/
+		for (i = (sat_tab->first_train_ant - 1); i < sat_tab->ant_num_total; i++) {
+			for (j = 0; j < (sat_tab->beam_patten_num_each_ant); j++) {
+				if (sat_tab->pkt_rssi_cnt[i][j] == 0) {
+					avg_rssi_tmp = sat_tab->pkt_rssi_pre[i][j];
+					avg_rssi_tmp = (avg_rssi_tmp >= 2) ? (avg_rssi_tmp - 2) : avg_rssi_tmp;
+					avg_rssi_tmp_ma = avg_rssi_tmp;
+				} else {
+					avg_rssi_tmp = (sat_tab->pkt_rssi_sum[i][j]) / (sat_tab->pkt_rssi_cnt[i][j]);
+					avg_rssi_tmp_ma = (avg_rssi_tmp + sat_tab->pkt_rssi_pre[i][j]) >> 1;
+				}
+
+				rssi_sorting_seq[j] = avg_rssi_tmp;
+				sat_tab->pkt_rssi_pre[i][j] = avg_rssi_tmp;
+
+				PHYDM_DBG(dm, DBG_ANT_DIV,
+					  "ant[%d], Beam[%d]: pkt_cnt=(( %d )), avg_rssi_MA=(( %d )), avg_rssi=(( %d ))\n",
+					  i, j, sat_tab->pkt_rssi_cnt[i][j],
+					  avg_rssi_tmp_ma, avg_rssi_tmp);
+
+				if (avg_rssi_tmp > target_ant_beam_max_rssi[i]) {
+					target_ant_beam[i] = j;
+					target_ant_beam_max_rssi[i] = avg_rssi_tmp;
+				}
+
+				/*reset counter value*/
+				sat_tab->pkt_rssi_sum[i][j] = 0;
+				sat_tab->pkt_rssi_cnt[i][j] = 0;
+			}
+			sat_tab->rx_idle_beam[i] = target_ant_beam[i];
+			PHYDM_DBG(dm, DBG_ANT_DIV,
+				  "---------> Target of ant[%d]: Beam_num-(( %d )) RSSI= ((%d))\n",
+				  i, target_ant_beam[i],
+				  target_ant_beam_max_rssi[i]);
+
+#if 0
+			/*sorting*/
+			/*@
+			PHYDM_DBG(dm, DBG_ANT_DIV, "[Pre]rssi_sorting_seq = [%d, %d, %d, %d]\n", rssi_sorting_seq[0], rssi_sorting_seq[1], rssi_sorting_seq[2], rssi_sorting_seq[3]);
+			*/
+
+			/*phydm_seq_sorting(dm, &rssi_sorting_seq[0], &rank_idx_seq[0], &rank_idx_out[0], SUPPORT_BEAM_PATTERN_NUM);*/
+
+			/*@
+			PHYDM_DBG(dm, DBG_ANT_DIV, "[Post]rssi_sorting_seq = [%d, %d, %d, %d]\n", rssi_sorting_seq[0], rssi_sorting_seq[1], rssi_sorting_seq[2], rssi_sorting_seq[3]);
+			PHYDM_DBG(dm, DBG_ANT_DIV, "[Post]rank_idx_seq = [%d, %d, %d, %d]\n", rank_idx_seq[0], rank_idx_seq[1], rank_idx_seq[2], rank_idx_seq[3]);
+			PHYDM_DBG(dm, DBG_ANT_DIV, "[Post]rank_idx_out = [%d, %d, %d, %d]\n", rank_idx_out[0], rank_idx_out[1], rank_idx_out[2], rank_idx_out[3]);
+			*/
+#endif
+
+			if (target_ant_beam_max_rssi[i] > max_beam_ant_rssi) {
+				target_ant = i;
+				max_beam_ant_rssi = target_ant_beam_max_rssi[i];
+#if
+				/*PHYDM_DBG(dm, DBG_ANT_DIV, "Target of ant = (( %d )) max_beam_ant_rssi = (( %d ))\n",
+					target_ant,  max_beam_ant_rssi);*/
+#endif
+			}
+			break_counter++;
+			if (break_counter >= sat_tab->ant_num)
+				break;
+		}
+
+#ifdef CONFIG_FAT_PATCH
+		break_counter = 0;
+		for (i = (sat_tab->first_train_ant - 1); i < sat_tab->ant_num_total; i++) {
+			for (j = 0; j < (sat_tab->beam_patten_num_each_ant); j++) {
+				per_beam_rssi_diff_tmp = (u8)(max_beam_ant_rssi - sat_tab->pkt_rssi_pre[i][j]);
+				sat_tab->beam_train_rssi_diff[i][j] = per_beam_rssi_diff_tmp;
+
+				PHYDM_DBG(dm, DBG_ANT_DIV,
+					  "ant[%d], Beam[%d]: RSSI_diff= ((%d))\n",
+					  i, j, per_beam_rssi_diff_tmp);
+			}
+			break_counter++;
+			if (break_counter >= sat_tab->ant_num)
+				break;
+		}
+#endif
+
+		if (target_ant == 0)
+			target_ant = MAIN_ANT;
+		else if (target_ant == 1)
+			target_ant = AUX_ANT;
+
+		if (sat_tab->ant_num > 1) {
+			/* @[ update RX ant ]*/
+			odm_update_rx_idle_ant(dm, (u8)target_ant);
+
+			/* @[ update TX ant ]*/
+			odm_update_tx_ant(dm, (u8)target_ant, (fat_tab->train_idx));
+		}
+
+		/*set beam in each antenna*/
+		phydm_update_rx_idle_beam(dm);
+
+		odm_ant_div_on_off(dm, ANTDIV_ON, ANT_PATH_A);
+		fat_tab->fat_state = FAT_PREPARE_STATE;
+		return;
+	}
+	/* @[TRAINING STATE] */
+	else if (fat_tab->fat_state == FAT_TRAINING_STATE) {
+		PHYDM_DBG(dm, DBG_ANT_DIV, "[ 2. In Training state]\n");
+
+		PHYDM_DBG(dm, DBG_ANT_DIV,
+			  "fat_beam_n = (( %d )), pre_fat_beam_n = (( %d ))\n",
+			  sat_tab->fast_training_beam_num,
+			  sat_tab->pre_fast_training_beam_num);
+
+		if (sat_tab->fast_training_beam_num > sat_tab->pre_fast_training_beam_num)
+
+			sat_tab->force_update_beam_en = 0;
+
+		else {
+			sat_tab->force_update_beam_en = 1;
+
+			sat_tab->pkt_counter = 0;
+			beam_tmp = sat_tab->fast_training_beam_num;
+			if (sat_tab->fast_training_beam_num >= (sat_tab->beam_patten_num_each_ant - 1)) {
+				PHYDM_DBG(dm, DBG_ANT_DIV,
+					  "[Timeout Update]  Beam_num (( %d )) -> (( decision ))\n",
+					  sat_tab->fast_training_beam_num);
+				fat_tab->fat_state = FAT_DECISION_STATE;
+				odm_fast_ant_training_hl_smart_antenna_type1(dm);
+
+			} else {
+				sat_tab->fast_training_beam_num++;
+
+				PHYDM_DBG(dm, DBG_ANT_DIV,
+					  "[Timeout Update]  Beam_num (( %d )) -> (( %d ))\n",
+					  beam_tmp,
+					  sat_tab->fast_training_beam_num);
+				phydm_set_all_ant_same_beam_num(dm);
+				fat_tab->fat_state = FAT_TRAINING_STATE;
+			}
+		}
+		sat_tab->pre_fast_training_beam_num = sat_tab->fast_training_beam_num;
+		PHYDM_DBG(dm, DBG_ANT_DIV,
+			  "[prepare state] Update Pre_Beam =(( %d ))\n",
+			  sat_tab->pre_fast_training_beam_num);
+	}
+	/*  @[Prepare state] */
+	/*@=======================================================================================*/
+	else if (fat_tab->fat_state == FAT_PREPARE_STATE) {
+		PHYDM_DBG(dm, DBG_ANT_DIV, "\n\n[ 1. In Prepare state]\n");
+
+		if (dm->pre_traffic_load == dm->traffic_load) {
+			if (sat_tab->decision_holding_period != 0) {
+				PHYDM_DBG(dm, DBG_ANT_DIV,
+					  "Holding_period = (( %d )), return!!!\n",
+					  sat_tab->decision_holding_period);
+				sat_tab->decision_holding_period--;
+				return;
+			}
+		}
+
+		/* Set training packet number*/
+		if (sat_tab->fix_training_num_en == 0) {
+			switch (dm->traffic_load) {
+			case TRAFFIC_HIGH:
+				sat_tab->per_beam_training_pkt_num = 8;
+				sat_tab->decision_holding_period = 2;
+				break;
+			case TRAFFIC_MID:
+				sat_tab->per_beam_training_pkt_num = 6;
+				sat_tab->decision_holding_period = 3;
+				break;
+			case TRAFFIC_LOW:
+				sat_tab->per_beam_training_pkt_num = 3; /*ping 60000*/
+				sat_tab->decision_holding_period = 4;
+				break;
+			case TRAFFIC_ULTRA_LOW:
+				sat_tab->per_beam_training_pkt_num = 1;
+				sat_tab->decision_holding_period = 6;
+				break;
+			default:
+				break;
+			}
+		}
+		PHYDM_DBG(dm, DBG_ANT_DIV,
+			  "Fix_training_en = (( %d )), training_pkt_num_base = (( %d )), holding_period = ((%d))\n",
+			  sat_tab->fix_training_num_en,
+			  sat_tab->per_beam_training_pkt_num,
+			  sat_tab->decision_holding_period);
+
+#ifdef CONFIG_FAT_PATCH
+		break_counter = 0;
+		for (i = (sat_tab->first_train_ant - 1); i < sat_tab->ant_num_total; i++) {
+			for (j = 0; j < (sat_tab->beam_patten_num_each_ant); j++) {
+				per_beam_rssi_diff_tmp = sat_tab->beam_train_rssi_diff[i][j];
+				training_pkt_num_offset = per_beam_rssi_diff_tmp;
+
+				if (sat_tab->per_beam_training_pkt_num > training_pkt_num_offset)
+					sat_tab->beam_train_cnt[i][j] = sat_tab->per_beam_training_pkt_num - training_pkt_num_offset;
+				else
+					sat_tab->beam_train_cnt[i][j] = 1;
+
+				PHYDM_DBG(dm, DBG_ANT_DIV,
+					  "ant[%d]: Beam_num-(( %d ))  training_pkt_num = ((%d))\n",
+					  i, j, sat_tab->beam_train_cnt[i][j]);
+			}
+			break_counter++;
+			if (break_counter >= sat_tab->ant_num)
+				break;
+		}
+
+		phydm_fast_training_enable(dm, FAT_OFF);
+		sat_tab->pre_beacon_counter = sat_tab->beacon_counter;
+		sat_tab->update_beam_idx = 0;
+
+		if (*dm->band_type == ODM_BAND_5G) {
+			PHYDM_DBG(dm, DBG_ANT_DIV, "Set 5G ant\n");
+			/*used_ant = (sat_tab->first_train_ant == MAIN_ANT) ? AUX_ANT : MAIN_ANT;*/
+			used_ant = sat_tab->first_train_ant;
+		} else {
+			PHYDM_DBG(dm, DBG_ANT_DIV, "Set 2.4G ant\n");
+			used_ant = sat_tab->first_train_ant;
+		}
+
+		odm_update_rx_idle_ant(dm, (u8)used_ant);
+
+#else
+		/* Set training MAC addr. of target */
+		odm_set_next_mac_addr_target(dm);
+		phydm_fast_training_enable(dm, FAT_ON);
+#endif
+
+		odm_ant_div_on_off(dm, ANTDIV_OFF, ANT_PATH_A);
+		sat_tab->pkt_counter = 0;
+		sat_tab->fast_training_beam_num = 0;
+		phydm_set_all_ant_same_beam_num(dm);
+		sat_tab->pre_fast_training_beam_num = sat_tab->fast_training_beam_num;
+		fat_tab->fat_state = FAT_TRAINING_STATE;
+	}
+}
+
+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
+
+void phydm_beam_switch_workitem_callback(
+	void *context)
+{
+	void *adapter = (void *)context;
+	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter));
+	struct dm_struct *dm = &hal_data->DM_OutSrc;
+	struct smt_ant_honbo *sat_tab = &dm->dm_sat_table;
+
+#if DEV_BUS_TYPE != RT_PCI_INTERFACE
+	sat_tab->pkt_skip_statistic_en = 1;
+#endif
+	PHYDM_DBG(dm, DBG_ANT_DIV,
+		  "[ SmartAnt ] Beam Switch Workitem Callback, pkt_skip_statistic_en = (( %d ))\n",
+		  sat_tab->pkt_skip_statistic_en);
+
+	phydm_update_beam_pattern(dm, sat_tab->update_beam_codeword, sat_tab->rfu_codeword_total_bit_num);
+
+#if DEV_BUS_TYPE != RT_PCI_INTERFACE
+#if 0
+	/*odm_stall_execution(sat_tab->latch_time);*/
+#endif
+	sat_tab->pkt_skip_statistic_en = 0;
+#endif
+	PHYDM_DBG(dm, DBG_ANT_DIV,
+		  "pkt_skip_statistic_en = (( %d )), latch_time = (( %d ))\n",
+		  sat_tab->pkt_skip_statistic_en, sat_tab->latch_time);
+}
+
+void phydm_beam_decision_workitem_callback(
+	void *context)
+{
+	void *adapter = (void *)context;
+	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter));
+	struct dm_struct *dm = &hal_data->DM_OutSrc;
+
+	PHYDM_DBG(dm, DBG_ANT_DIV,
+		  "[ SmartAnt ] Beam decision Workitem Callback\n");
+	odm_fast_ant_training_hl_smart_antenna_type1(dm);
+}
+#endif
+
+#endif /*@#ifdef CONFIG_HL_SMART_ANTENNA_TYPE1*/
+
+#endif /*@#ifdef CONFIG_HL_SMART_ANTENNA*/
+
+void phydm_smt_ant_config(
+	void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct smt_ant *smtant_table = &dm->smtant_table;
+
+#if (defined(CONFIG_CUMITEK_SMART_ANTENNA))
+
+	dm->support_ability |= ODM_BB_SMT_ANT;
+	smtant_table->smt_ant_vendor = SMTANT_CUMITEK;
+	smtant_table->smt_ant_type = 1;
+#if (RTL8822B_SUPPORT == 1)
+	dm->rfe_type = SMTANT_TMP_RFE_TYPE;
+#endif
+#elif (defined(CONFIG_HL_SMART_ANTENNA))
+
+	dm->support_ability |= ODM_BB_SMT_ANT;
+	smtant_table->smt_ant_vendor = SMTANT_HON_BO;
+
+#ifdef CONFIG_HL_SMART_ANTENNA_TYPE1
+	smtant_table->smt_ant_type = 1;
+#endif
+
+#ifdef CONFIG_HL_SMART_ANTENNA_TYPE2
+	smtant_table->smt_ant_type = 2;
+#endif
+#endif
+
+	PHYDM_DBG(dm, DBG_SMT_ANT,
+		  "[SmtAnt Config] Vendor=((%d)), Smt_ant_type =((%d))\n",
+		  smtant_table->smt_ant_vendor, smtant_table->smt_ant_type);
+}
+
+void phydm_smt_ant_init(void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct smt_ant *smtant_table = &dm->smtant_table;
+
+	phydm_smt_ant_config(dm);
+
+	if (smtant_table->smt_ant_vendor == SMTANT_CUMITEK) {
+#if (defined(CONFIG_CUMITEK_SMART_ANTENNA))
+#if (RTL8822B_SUPPORT == 1)
+		if (dm->support_ic_type == ODM_RTL8822B)
+			phydm_cumitek_smt_ant_init_8822b(dm);
+#endif
+
+#if (RTL8197F_SUPPORT == 1)
+		if (dm->support_ic_type == ODM_RTL8197F)
+			phydm_cumitek_smt_ant_init_8197f(dm);
+#endif
+/*@jj add 20170822*/
+#if (RTL8192F_SUPPORT == 1)
+		if (dm->support_ic_type == ODM_RTL8192F)
+			phydm_cumitek_smt_ant_init_8192f(dm);
+#endif
+#endif /*@#if (defined(CONFIG_CUMITEK_SMART_ANTENNA))*/
+
+	} else if (smtant_table->smt_ant_vendor == SMTANT_HON_BO) {
+#if (defined(CONFIG_HL_SMART_ANTENNA))
+#ifdef CONFIG_HL_SMART_ANTENNA_TYPE1
+		if (dm->support_ic_type == ODM_RTL8821)
+			phydm_hl_smart_ant_type1_init_8821a(dm);
+#endif
+
+#ifdef CONFIG_HL_SMART_ANTENNA_TYPE2
+		if (dm->support_ic_type == ODM_RTL8822B)
+			phydm_hl_smart_ant_type2_init_8822b(dm);
+#endif
+#endif /*@#if (defined(CONFIG_HL_SMART_ANTENNA))*/
+	}
+}
+#endif
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/phydm_smt_ant.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/phydm_smt_ant.h
--- linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/phydm_smt_ant.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/phydm_smt_ant.h	2020-04-10 16:35:06.827660581 +0300
@@ -0,0 +1,210 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017  Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * The full GNU General Public License is included in this distribution in the
+ * file called LICENSE.
+ *
+ * Contact Information:
+ * wlanfae <wlanfae@realtek.com>
+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
+ * Hsinchu 300, Taiwan.
+ *
+ * Larry Finger <Larry.Finger@lwfinger.net>
+ *
+ *****************************************************************************/
+
+#ifndef __PHYDMSMTANT_H__
+#define __PHYDMSMTANT_H__
+
+/*@#define SMT_ANT_VERSION	"1.1"*/ /*@2017.03.13*/
+/*@#define SMT_ANT_VERSION	"1.2"*/ /*@2017.03.28*/
+#define SMT_ANT_VERSION "2.0" /* @Add Cumitek SmtAnt 2017.05.25*/
+
+#define	SMTANT_RTK		1
+#define	SMTANT_HON_BO	2
+#define	SMTANT_CUMITEK	3
+
+#if (defined(CONFIG_SMART_ANTENNA))
+
+#if (defined(CONFIG_CUMITEK_SMART_ANTENNA))
+struct smt_ant_cumitek {
+	u8	tx_ant_idx[2][ODM_ASSOCIATE_ENTRY_NUM]; /*@[pathA~B] [MACID 0~128]*/
+	u8	rx_default_ant_idx[2]; /*@[pathA~B]*/
+};
+#endif
+
+#if (defined(CONFIG_HL_SMART_ANTENNA))
+struct smt_ant_honbo {
+	u32	latch_time;
+	boolean	pkt_skip_statistic_en;
+	u32	fix_beam_pattern_en;
+	u32	fix_training_num_en;
+	u32	fix_beam_pattern_codeword;
+	u32	update_beam_codeword;
+	u32	ant_num; /*number of "used" smart beam antenna*/
+	u32	ant_num_total;/*number of "total" smart beam antenna*/
+	u32	first_train_ant; /*@decide witch antenna to train first*/
+
+	#ifdef CONFIG_HL_SMART_ANTENNA_TYPE1
+	u32	pkt_rssi_pre[SUPPORT_RF_PATH_NUM][SUPPORT_BEAM_PATTERN_NUM];/*@rssi of each path with a certain beam pattern*/
+	u8	beam_train_rssi_diff[SUPPORT_RF_PATH_NUM][SUPPORT_BEAM_PATTERN_NUM];
+	u8	beam_train_cnt[SUPPORT_RF_PATH_NUM][SUPPORT_BEAM_PATTERN_NUM];
+	u32	rfu_codeword_table[4]; /*@2G beam truth table*/
+	u32	rfu_codeword_table_5g[4]; /*@5G beam truth table*/
+	u32	beam_patten_num_each_ant;/*@number of  beam can be switched in each antenna*/
+	u32	rx_idle_beam[SUPPORT_RF_PATH_NUM];
+	u32	pkt_rssi_sum[8][SUPPORT_BEAM_PATTERN_NUM];
+	u32	pkt_rssi_cnt[8][SUPPORT_BEAM_PATTERN_NUM];
+	#endif
+
+	u32	fast_training_beam_num;/*@current training beam_set index*/
+	u32	pre_fast_training_beam_num;/*pre training beam_set index*/
+	u32	rfu_codeword_total_bit_num; /* @total bit number of RFU protocol*/
+	u32	rfu_each_ant_bit_num; /* @bit number of RFU protocol for each ant*/
+	u8	per_beam_training_pkt_num;
+	u8	decision_holding_period;
+
+
+	u32	pre_codeword;
+	boolean	force_update_beam_en;
+	u32	beacon_counter;
+	u32	pre_beacon_counter;
+	u8	pkt_counter;		/*@packet number that each beam-set should be colected in training state*/
+	u8	update_beam_idx;	/*@the index announce that the beam can be updated*/
+	u8	rfu_protocol_type;
+	u16	rfu_protocol_delay_time;
+
+	#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
+	RT_WORK_ITEM	hl_smart_antenna_workitem;
+	RT_WORK_ITEM	hl_smart_antenna_decision_workitem;
+	#endif
+
+
+	#ifdef CONFIG_HL_SMART_ANTENNA_TYPE2
+	u8	beam_set_avg_rssi_pre[SUPPORT_BEAM_SET_PATTERN_NUM];		/*@avg pre_rssi of each beam set*/
+	u8	beam_set_train_val_diff[SUPPORT_BEAM_SET_PATTERN_NUM];	/*@rssi of a beam pattern set, ex: a set = {ant1_beam=1, ant2_beam=3}*/
+	u8	beam_set_train_cnt[SUPPORT_BEAM_SET_PATTERN_NUM];			/*@training pkt num of each beam set*/
+	u32	beam_set_rssi_avg_sum[SUPPORT_BEAM_SET_PATTERN_NUM];			/*@RSSI_sum of avg(pathA,pathB) for each beam-set)*/
+	u32	beam_path_rssi_sum[SUPPORT_BEAM_SET_PATTERN_NUM][MAX_PATH_NUM_8822B];/*@RSSI_sum of each path for each beam-set)*/
+
+	u8	beam_set_avg_evm_2ss_pre[SUPPORT_BEAM_SET_PATTERN_NUM];
+	u32	beam_path_evm_2ss_sum[SUPPORT_BEAM_SET_PATTERN_NUM][MAX_PATH_NUM_8822B];/*@2SS evm_sum of each path for each beam-set)*/
+	u32	beam_path_evm_2ss_cnt[SUPPORT_BEAM_SET_PATTERN_NUM];
+
+	u8	beam_set_avg_evm_1ss_pre[SUPPORT_BEAM_SET_PATTERN_NUM];
+	u32	beam_path_evm_1ss_sum[SUPPORT_BEAM_SET_PATTERN_NUM];/*@1SS evm_sum of each path for each beam-set)*/
+	u32	beam_path_evm_1ss_cnt[SUPPORT_BEAM_SET_PATTERN_NUM];
+
+	u32	statistic_pkt_cnt[SUPPORT_BEAM_SET_PATTERN_NUM];				/*@statistic_pkt_cnt for SmtAnt make decision*/
+
+	u8	total_beam_set_num;	/*@number of  beam set can be switched*/
+	u8	total_beam_set_num_2g;/*@number of  beam set can be switched in 2G*/
+	u8	total_beam_set_num_5g;/*@number of  beam set can be switched in 5G*/
+
+	u8	rfu_codeword_table_2g[SUPPORT_BEAM_SET_PATTERN_NUM][MAX_PATH_NUM_8822B]; /*@2G beam truth table*/
+	u8	rfu_codeword_table_5g[SUPPORT_BEAM_SET_PATTERN_NUM][MAX_PATH_NUM_8822B]; /*@5G beam truth table*/
+	u8	rx_idle_beam_set_idx;	/*the filanl decsion result*/
+	#endif
+
+
+};
+#endif /*@#if (defined(CONFIG_HL_SMART_ANTENNA))*/
+
+struct smt_ant {
+	u8	smt_ant_vendor;
+	u8	smt_ant_type;
+	u8	tx_desc_mode; /*@0:3 bit mode, 1:2 bit mode*/
+	#if (defined(CONFIG_CUMITEK_SMART_ANTENNA))
+	struct	smt_ant_cumitek	cumi_smtant_table;
+	#endif
+};
+
+#if (defined(CONFIG_CUMITEK_SMART_ANTENNA))
+void phydm_cumitek_smt_tx_ant_update(
+	void *dm_void,
+	u8 tx_ant_idx_path_a,
+	u8 tx_ant_idx_path_b,
+	u32 mac_id);
+
+void phydm_cumitek_smt_rx_default_ant_update(
+	void *dm_void,
+	u8 rx_ant_idx_path_a,
+	u8 rx_ant_idx_path_b);
+
+void phydm_cumitek_smt_ant_debug(
+	void *dm_void,
+	char input[][16],
+	u32 *_used,
+	char *output,
+	u32 *_out_len);
+
+#endif
+
+#if (defined(CONFIG_HL_SMART_ANTENNA))
+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
+void phydm_beam_switch_workitem_callback(
+	void *context);
+
+void phydm_beam_decision_workitem_callback(
+	void *context);
+#endif /*@#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)*/
+
+#ifdef CONFIG_HL_SMART_ANTENNA_TYPE2
+void phydm_hl_smart_ant_type2_init_8822b(
+	void *dm_void);
+
+void phydm_update_beam_pattern_type2(
+	void *dm_void,
+	u32 codeword,
+	u32 codeword_length);
+
+void phydm_set_rfu_beam_pattern_type2(
+	void *dm_void);
+
+void phydm_hl_smt_ant_dbg_type2(
+	void *dm_void,
+	char input[][16],
+	u32 *_used,
+	char *output,
+	u32 *_out_len);
+
+void phydm_process_rssi_for_hb_smtant_type2(
+	void *dm_void,
+	void *phy_info_void,
+	void *pkt_info_void,
+	u8 rssi_avg);
+
+#endif /*@#if (defined(CONFIG_HL_SMART_ANTENNA_TYPE2))*/
+
+#if (defined(CONFIG_HL_SMART_ANTENNA_TYPE1))
+
+void phydm_update_beam_pattern(
+	void *dm_void,
+	u32 codeword,
+	u32 codeword_length);
+
+void phydm_set_all_ant_same_beam_num(
+	void *dm_void);
+
+void phydm_hl_smart_ant_debug(
+	void *dm_void,
+	char input[][16],
+	u32 *_used,
+	char *output,
+	u32 *_out_len);
+
+#endif /*@#if (defined(CONFIG_HL_SMART_ANTENNA_TYPE1))*/
+#endif /*@#if (defined(CONFIG_HL_SMART_ANTENNA))*/
+void phydm_smt_ant_init(void *dm_void);
+#endif /*@#if (defined(CONFIG_SMART_ANTENNA))*/
+#endif
\ Ingen nyrad vid filslut
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/phydm_soml.c linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/phydm_soml.c
--- linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/phydm_soml.c	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/phydm_soml.c	2020-04-10 16:35:06.827660581 +0300
@@ -0,0 +1,963 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017  Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * The full GNU General Public License is included in this distribution in the
+ * file called LICENSE.
+ *
+ * Contact Information:
+ * wlanfae <wlanfae@realtek.com>
+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
+ * Hsinchu 300, Taiwan.
+ *
+ * Larry Finger <Larry.Finger@lwfinger.net>
+ *
+ *****************************************************************************/
+
+/*************************************************************
+ * include files
+ ************************************************************/
+
+#include "mp_precomp.h"
+#include "phydm_precomp.h"
+
+#ifdef CONFIG_ADAPTIVE_SOML
+
+void phydm_dynamicsoftmletting(void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	u32 ret_val;
+
+#if (RTL8822B_SUPPORT == 1)
+	if (!*dm->mp_mode) {
+		if (dm->support_ic_type & ODM_RTL8822B) {
+			if (!dm->is_linked | dm->iot_table.is_linked_cmw500)
+				return;
+
+			if (dm->bsomlenabled) {
+				PHYDM_DBG(dm, ODM_COMP_API,
+					  "PHYDM_DynamicSoftMLSetting(): SoML has been enable, skip dynamic SoML switch\n");
+				return;
+			}
+
+			ret_val = odm_get_bb_reg(dm, R_0xf8c, MASKBYTE0);
+			PHYDM_DBG(dm, ODM_COMP_API,
+				  "PHYDM_DynamicSoftMLSetting(): Read 0xF8C = 0x%08X\n",
+				  ret_val);
+
+			if (ret_val < 0x16) {
+				PHYDM_DBG(dm, ODM_COMP_API,
+					  "PHYDM_DynamicSoftMLSetting(): 0xF8C(== 0x%08X) < 0x16, enable SoML\n",
+					  ret_val);
+				phydm_somlrxhp_setting(dm, true);
+#if 0
+				/*odm_set_bb_reg(dm, R_0x19a8, MASKDWORD, 0xc10a0000);*/
+#endif
+				dm->bsomlenabled = true;
+			}
+		}
+	}
+#endif
+}
+
+void phydm_soml_on_off(
+	void *dm_void,
+	u8 swch)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct adaptive_soml *dm_soml_table = &dm->dm_soml_table;
+
+	if (swch == SOML_ON) {
+		PHYDM_DBG(dm, DBG_ADPTV_SOML, "(( Turn on )) SOML\n");
+
+		if (dm->support_ic_type & (ODM_RTL8197F | ODM_RTL8192F))
+			odm_set_bb_reg(dm, R_0x998, BIT(6), swch);
+#if (RTL8822B_SUPPORT == 1)
+		else if (dm->support_ic_type == ODM_RTL8822B)
+			phydm_somlrxhp_setting(dm, true);
+#endif
+
+	} else if (swch == SOML_OFF) {
+		PHYDM_DBG(dm, DBG_ADPTV_SOML, "(( Turn off )) SOML\n");
+
+		if (dm->support_ic_type & (ODM_RTL8197F | ODM_RTL8192F))
+			odm_set_bb_reg(dm, R_0x998, BIT(6), swch);
+#if (RTL8822B_SUPPORT == 1)
+		else if (dm->support_ic_type == ODM_RTL8822B)
+			phydm_somlrxhp_setting(dm, false);
+#endif
+	}
+	dm_soml_table->soml_on_off = swch;
+}
+
+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
+void phydm_adaptive_soml_callback(
+	struct phydm_timer_list *timer)
+{
+	void *adapter = (void *)timer->Adapter;
+	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter));
+	struct dm_struct *dm = &hal_data->DM_OutSrc;
+	struct adaptive_soml *dm_soml_table = &dm->dm_soml_table;
+
+	#if DEV_BUS_TYPE == RT_PCI_INTERFACE
+	#if USE_WORKITEM
+	odm_schedule_work_item(&dm_soml_table->phydm_adaptive_soml_workitem);
+	#else
+	{
+#if 0
+		/*@dbg_print("%s\n",__func__);*/
+#endif
+		phydm_adsl(dm);
+	}
+	#endif
+	#else
+	odm_schedule_work_item(&dm_soml_table->phydm_adaptive_soml_workitem);
+	#endif
+}
+
+void phydm_adaptive_soml_workitem_callback(
+	void *context)
+{
+#ifdef CONFIG_ADAPTIVE_SOML
+	void *adapter = (void *)context;
+	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter));
+	struct dm_struct *dm = &hal_data->DM_OutSrc;
+
+#if 0
+	/*@dbg_print("%s\n",__func__);*/
+#endif
+	phydm_adsl(dm);
+#endif
+}
+
+#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
+void phydm_adaptive_soml_callback(
+	void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	void *padapter = dm->adapter;
+
+	if (*dm->is_net_closed == true)
+		return;
+	if (dm->support_interface == ODM_ITRF_PCIE)
+		phydm_adsl(dm);
+	else {
+		/* @Can't do I/O in timer callback*/
+		phydm_run_in_thread_cmd(dm,
+					phydm_adaptive_soml_workitem_callback,
+					dm);
+	}
+}
+
+void phydm_adaptive_soml_workitem_callback(
+	void *context)
+{
+	struct dm_struct *dm = (void *)context;
+
+#if 0
+	/*@dbg_print("%s\n",__func__);*/
+#endif
+	phydm_adsl(dm);
+}
+
+#else
+void phydm_adaptive_soml_callback(
+	void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+
+	PHYDM_DBG(dm, DBG_ADPTV_SOML, "******SOML_Callback******\n");
+	phydm_adsl(dm);
+}
+#endif
+
+void phydm_rx_rate_for_soml(
+	void *dm_void,
+	void *pkt_info_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct adaptive_soml *dm_soml_table = &dm->dm_soml_table;
+	struct phydm_perpkt_info_struct *pktinfo = (struct phydm_perpkt_info_struct *)pkt_info_void;
+	u8 data_rate = (pktinfo->data_rate & 0x7f);
+
+	if (pktinfo->data_rate >= ODM_RATEMCS0 && pktinfo->data_rate <= ODM_RATEMCS31)
+		dm_soml_table->num_ht_cnt[data_rate - ODM_RATEMCS0]++;
+	else if ((pktinfo->data_rate >= ODM_RATEVHTSS1MCS0) && (pktinfo->data_rate <= ODM_RATEVHTSS4MCS9))
+		dm_soml_table->num_vht_cnt[data_rate - ODM_RATEVHTSS1MCS0]++;
+}
+
+void phydm_rx_qam_for_soml(
+	void *dm_void,
+	void *pkt_info_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct adaptive_soml *dm_soml_table = &dm->dm_soml_table;
+	struct phydm_perpkt_info_struct *pktinfo = (struct phydm_perpkt_info_struct *)pkt_info_void;
+	u8 date_rate = (pktinfo->data_rate & 0x7f);
+
+	if (dm_soml_table->soml_state_cnt < (dm_soml_table->soml_train_num << 1)) {
+		if (dm_soml_table->soml_on_off == SOML_ON)
+			return;
+		else if (dm_soml_table->soml_on_off == SOML_OFF) {
+			if (date_rate >= ODM_RATEMCS8 && date_rate <= ODM_RATEMCS10)
+				dm_soml_table->num_ht_qam[BPSK_QPSK]++;
+
+			else if ((date_rate >= ODM_RATEMCS11) && (date_rate <= ODM_RATEMCS12))
+				dm_soml_table->num_ht_qam[QAM16]++;
+
+			else if ((date_rate >= ODM_RATEMCS13) && (date_rate <= ODM_RATEMCS15))
+				dm_soml_table->num_ht_qam[QAM64]++;
+
+			else if ((date_rate >= ODM_RATEVHTSS2MCS0) && (date_rate <= ODM_RATEVHTSS2MCS2))
+				dm_soml_table->num_vht_qam[BPSK_QPSK]++;
+
+			else if ((date_rate >= ODM_RATEVHTSS2MCS3) && (date_rate <= ODM_RATEVHTSS2MCS4))
+				dm_soml_table->num_vht_qam[QAM16]++;
+
+			else if ((date_rate >= ODM_RATEVHTSS2MCS5) && (date_rate <= ODM_RATEVHTSS2MCS5))
+				dm_soml_table->num_vht_qam[QAM64]++;
+
+			else if ((date_rate >= ODM_RATEVHTSS2MCS8) && (date_rate <= ODM_RATEVHTSS2MCS9))
+				dm_soml_table->num_vht_qam[QAM256]++;
+		}
+	}
+}
+
+void phydm_soml_reset_rx_rate(
+	void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct adaptive_soml *dm_soml_table = &dm->dm_soml_table;
+	u8 order;
+
+	for (order = 0; order < HT_RATE_IDX; order++)
+		dm_soml_table->num_ht_cnt[order] = 0;
+
+	for (order = 0; order < VHT_RATE_IDX; order++)
+		dm_soml_table->num_vht_cnt[order] = 0;
+}
+
+void phydm_soml_reset_qam(
+	void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct adaptive_soml *dm_soml_table = &dm->dm_soml_table;
+	u8 order;
+
+	for (order = 0; order < HT_ORDER_TYPE; order++)
+		dm_soml_table->num_ht_qam[order] = 0;
+
+	for (order = 0; order < VHT_ORDER_TYPE; order++)
+		dm_soml_table->num_vht_qam[order] = 0;
+}
+
+void phydm_soml_cfo_process(
+	void *dm_void,
+	s32 *diff_a,
+	s32 *diff_b)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	u32 value32, value32_1, value32_2, value32_3;
+	s32 cfo_acq_a, cfo_acq_b, cfo_end_a, cfo_end_b;
+
+	value32 = odm_get_bb_reg(dm, R_0xd10, MASKDWORD);
+	value32_1 = odm_get_bb_reg(dm, R_0xd14, MASKDWORD);
+	value32_2 = odm_get_bb_reg(dm, R_0xd50, MASKDWORD);
+	value32_3 = odm_get_bb_reg(dm, R_0xd54, MASKDWORD);
+
+	cfo_acq_a = (s32)((value32 & 0x1fff0000) >> 16);
+	cfo_end_a = (s32)((value32_1 & 0x1fff0000) >> 16);
+	cfo_acq_b = (s32)((value32_2 & 0x1fff0000) >> 16);
+	cfo_end_b = (s32)((value32_3 & 0x1fff0000) >> 16);
+
+	*diff_a = ((cfo_acq_a >= cfo_end_a) ? (cfo_acq_a - cfo_end_a) : (cfo_end_a - cfo_acq_a));
+	*diff_b = ((cfo_acq_b >= cfo_end_b) ? (cfo_acq_b - cfo_end_b) : (cfo_end_b - cfo_acq_b));
+
+	*diff_a = ((*diff_a * 312) + (*diff_a >> 1)) >> 12; /* @312.5/2^12 */
+	*diff_b = ((*diff_b * 312) + (*diff_b >> 1)) >> 12; /* @312.5/2^12 */
+}
+
+void phydm_soml_debug(void *dm_void, char input[][16], u32 *_used,
+		      char *output, u32 *_out_len)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct adaptive_soml *dm_soml_table = &dm->dm_soml_table;
+	u32 used = *_used;
+	u32 out_len = *_out_len;
+	u32 dm_value[10] = {0};
+	u8 i = 0, input_idx = 0;
+
+	for (i = 0; i < 5; i++) {
+		if (input[i + 1]) {
+			PHYDM_SSCANF(input[i + 1], DCMD_DECIMAL, &dm_value[i]);
+			input_idx++;
+		}
+	}
+
+	if (input_idx == 0)
+		return;
+
+	if (dm_value[0] == 1) { /*Turn on/off SOML*/
+		dm_soml_table->soml_select = (u8)dm_value[1];
+
+	} else if (dm_value[0] == 2) { /*training number for SOML*/
+
+		dm_soml_table->soml_train_num = (u8)dm_value[1];
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "soml_train_num = ((%d))\n",
+			 dm_soml_table->soml_train_num);
+	} else if (dm_value[0] == 3) { /*training interval for SOML*/
+
+		dm_soml_table->soml_intvl = (u8)dm_value[1];
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "soml_intvl = ((%d))\n", dm_soml_table->soml_intvl);
+	} else if (dm_value[0] == 4) { /*@function period for SOML*/
+
+		dm_soml_table->soml_period = (u8)dm_value[1];
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "soml_period = ((%d))\n", dm_soml_table->soml_period);
+	} else if (dm_value[0] == 5) { /*@delay_time for SOML*/
+
+		dm_soml_table->soml_delay_time = (u8)dm_value[1];
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "soml_delay_time = ((%d))\n",
+			 dm_soml_table->soml_delay_time);
+	} else if (dm_value[0] == 6) { /* @for SOML Rx QAM distribution th*/
+		if (dm_value[1] == 256) {
+			dm_soml_table->qam256_dist_th = (u8)dm_value[2];
+			PDM_SNPF(out_len, used, output + used, out_len - used,
+				 "qam256_dist_th = ((%d))\n",
+				 dm_soml_table->qam256_dist_th);
+		} else if (dm_value[1] == 64) {
+			dm_soml_table->qam64_dist_th = (u8)dm_value[2];
+			PDM_SNPF(out_len, used, output + used, out_len - used,
+				 "qam64_dist_th = ((%d))\n",
+				 dm_soml_table->qam64_dist_th);
+		} else if (dm_value[1] == 16) {
+			dm_soml_table->qam16_dist_th = (u8)dm_value[2];
+			PDM_SNPF(out_len, used, output + used, out_len - used,
+				 "qam16_dist_th = ((%d))\n",
+				 dm_soml_table->qam16_dist_th);
+		} else if (dm_value[1] == 4) {
+			dm_soml_table->bpsk_qpsk_dist_th = (u8)dm_value[2];
+			PDM_SNPF(out_len, used, output + used, out_len - used,
+				 "bpsk_qpsk_dist_th = ((%d))\n",
+				 dm_soml_table->bpsk_qpsk_dist_th);
+		}
+	} else if (dm_value[0] == 7) { /* @for SOML cfo th*/
+		if (dm_value[1] == 256) {
+			dm_soml_table->cfo_qam256_th = (u8)dm_value[2];
+			PDM_SNPF(out_len, used, output + used, out_len - used,
+				 "cfo_qam256_th = ((%d KHz))\n",
+				 dm_soml_table->cfo_qam256_th);
+		} else if (dm_value[1] == 64) {
+			dm_soml_table->cfo_qam64_th = (u8)dm_value[2];
+			PDM_SNPF(out_len, used, output + used, out_len - used,
+				 "cfo_qam64_th = ((%d KHz))\n",
+				 dm_soml_table->cfo_qam64_th);
+		} else if (dm_value[1] == 16) {
+			dm_soml_table->cfo_qam16_th = (u8)dm_value[2];
+			PDM_SNPF(out_len, used, output + used, out_len - used,
+				 "cfo_qam16_th = ((%d KHz))\n",
+				 dm_soml_table->cfo_qam16_th);
+		} else if (dm_value[1] == 4) {
+			dm_soml_table->cfo_qpsk_th = (u8)dm_value[2];
+			PDM_SNPF(out_len, used, output + used, out_len - used,
+				 "cfo_qpsk_th = ((%d KHz))\n",
+				 dm_soml_table->cfo_qpsk_th);
+		}
+	} else if (dm_value[0] == 100) { /*show parameters*/
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "soml_select = ((%d))\n", dm_soml_table->soml_select);
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "soml_train_num = ((%d))\n",
+			 dm_soml_table->soml_train_num);
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "soml_intvl = ((%d))\n", dm_soml_table->soml_intvl);
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "soml_period = ((%d))\n", dm_soml_table->soml_period);
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "soml_delay_time = ((%d))\n\n",
+			 dm_soml_table->soml_delay_time);
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "qam256_dist_th = ((%d)),  qam64_dist_th = ((%d)), ",
+			 dm_soml_table->qam256_dist_th,
+			 dm_soml_table->qam64_dist_th);
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "qam16_dist_th = ((%d)),  bpsk_qpsk_dist_th = ((%d))\n",
+			 dm_soml_table->qam16_dist_th,
+			 dm_soml_table->bpsk_qpsk_dist_th);
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "cfo_qam256_th = ((%d KHz)),  cfo_qam64_th = ((%d KHz)), ",
+			 dm_soml_table->cfo_qam256_th,
+			 dm_soml_table->cfo_qam64_th);
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "cfo_qam16_th = ((%d KHz)),  cfo_qpsk_th  = ((%d KHz))\n",
+			 dm_soml_table->cfo_qam16_th,
+			 dm_soml_table->cfo_qpsk_th);
+	}
+	*_used = used;
+	*_out_len = out_len;
+}
+
+void phydm_soml_statistics(
+	void *dm_void,
+	u8 on_off_state
+
+	)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct adaptive_soml *dm_soml_table = &dm->dm_soml_table;
+
+	u8 i, j;
+	u32 num_bytes_diff, num_rate_diff;
+
+	if (on_off_state == SOML_ON) {
+		if (*dm->channel <= 14) {
+			for (i = ODM_RATEMCS0; i <= ODM_RATEMCS15; i++) {
+				num_rate_diff = dm_soml_table->num_ht_cnt[i - ODM_RATEMCS0] - dm_soml_table->pre_num_ht_cnt[i - ODM_RATEMCS0];
+				dm_soml_table->num_ht_cnt_on[i - ODM_RATEMCS0] += num_rate_diff;
+				dm_soml_table->pre_num_ht_cnt[i - ODM_RATEMCS0] = dm_soml_table->num_ht_cnt[i - ODM_RATEMCS0];
+				num_bytes_diff = dm_soml_table->num_ht_bytes[i - ODM_RATEMCS0] - dm_soml_table->pre_num_ht_bytes[i - ODM_RATEMCS0];
+				dm_soml_table->num_ht_bytes_on[i - ODM_RATEMCS0] += num_bytes_diff;
+				dm_soml_table->pre_num_ht_bytes[i - ODM_RATEMCS0] = dm_soml_table->num_ht_bytes[i - ODM_RATEMCS0];
+			}
+		}
+		if (dm->support_ic_type == ODM_RTL8822B) {
+			for (j = ODM_RATEVHTSS1MCS0; j <= ODM_RATEVHTSS2MCS9; j++) {
+				num_rate_diff = dm_soml_table->num_vht_cnt[j - ODM_RATEVHTSS1MCS0] - dm_soml_table->pre_num_vht_cnt[j - ODM_RATEVHTSS1MCS0];
+				dm_soml_table->num_vht_cnt_on[j - ODM_RATEVHTSS1MCS0] += num_rate_diff;
+				dm_soml_table->pre_num_vht_cnt[j - ODM_RATEVHTSS1MCS0] = dm_soml_table->num_vht_cnt[j - ODM_RATEVHTSS1MCS0];
+				num_bytes_diff = dm_soml_table->num_vht_bytes[j - ODM_RATEVHTSS1MCS0] - dm_soml_table->pre_num_vht_bytes[j - ODM_RATEVHTSS1MCS0];
+				dm_soml_table->num_vht_bytes_on[j - ODM_RATEVHTSS1MCS0] += num_bytes_diff;
+				dm_soml_table->pre_num_vht_bytes[j - ODM_RATEVHTSS1MCS0] = dm_soml_table->num_vht_bytes[j - ODM_RATEVHTSS1MCS0];
+			}
+		}
+	} else if (on_off_state == SOML_OFF) {
+		if (*dm->channel <= 14) {
+			for (i = ODM_RATEMCS0; i <= ODM_RATEMCS15; i++) {
+				num_rate_diff = dm_soml_table->num_ht_cnt[i - ODM_RATEMCS0] - dm_soml_table->pre_num_ht_cnt[i - ODM_RATEMCS0];
+				dm_soml_table->num_ht_cnt_off[i - ODM_RATEMCS0] += num_rate_diff;
+				dm_soml_table->pre_num_ht_cnt[i - ODM_RATEMCS0] = dm_soml_table->num_ht_cnt[i - ODM_RATEMCS0];
+				num_bytes_diff = dm_soml_table->num_ht_bytes[i - ODM_RATEMCS0] - dm_soml_table->pre_num_ht_bytes[i - ODM_RATEMCS0];
+				dm_soml_table->num_ht_bytes_off[i - ODM_RATEMCS0] += num_bytes_diff;
+				dm_soml_table->pre_num_ht_bytes[i - ODM_RATEMCS0] = dm_soml_table->num_ht_bytes[i - ODM_RATEMCS0];
+			}
+		}
+		if (dm->support_ic_type == ODM_RTL8822B) {
+			for (j = ODM_RATEVHTSS1MCS0; j <= ODM_RATEVHTSS2MCS9; j++) {
+				num_rate_diff = dm_soml_table->num_vht_cnt[j - ODM_RATEVHTSS1MCS0] - dm_soml_table->pre_num_vht_cnt[j - ODM_RATEVHTSS1MCS0];
+				dm_soml_table->num_vht_cnt_off[j - ODM_RATEVHTSS1MCS0] += num_rate_diff;
+				dm_soml_table->pre_num_vht_cnt[j - ODM_RATEVHTSS1MCS0] = dm_soml_table->num_vht_cnt[j - ODM_RATEVHTSS1MCS0];
+				num_bytes_diff = dm_soml_table->num_vht_bytes[j - ODM_RATEVHTSS1MCS0] - dm_soml_table->pre_num_vht_bytes[j - ODM_RATEVHTSS1MCS0];
+				dm_soml_table->num_vht_bytes_off[j - ODM_RATEVHTSS1MCS0] += num_bytes_diff;
+				dm_soml_table->pre_num_vht_bytes[j - ODM_RATEVHTSS1MCS0] = dm_soml_table->num_vht_bytes[j - ODM_RATEVHTSS1MCS0];
+			}
+		}
+	}
+}
+
+void phydm_adsl(
+	void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct adaptive_soml *dm_soml_table = &dm->dm_soml_table;
+
+	u8 i;
+	u8 next_on_off;
+	u8 rate_num = 1, rate_ss_shift = 0;
+	u32 num_total_qam = 0;
+	u32 num_ht_total_cnt_on = 0, num_ht_total_cnt_off = 0, total_ht_rate_on = 0, total_ht_rate_off = 0;
+	u32 num_vht_total_cnt_on = 0, num_vht_total_cnt_off = 0, total_vht_rate_on = 0, total_vht_rate_off = 0;
+	u32 rate_per_pkt_on = 0, rate_per_pkt_off = 0;
+	u32 ht_reset[HT_RATE_IDX] = {0}, vht_reset[VHT_RATE_IDX] = {0};
+	u8 size = sizeof(ht_reset[0]);
+	u16 vht_phy_rate_table[] = {
+		/*@20M*/
+		6, 13, 19, 26, 39, 52, 58, 65, 78, 90, /*@1SS MCS0~9*/
+		13, 26, 39, 52, 78, 104, 117, 130, 156, 180 /*@2SSMCS0~9*/
+	};
+
+	if (dm->support_ic_type & ODM_IC_4SS)
+		rate_num = 4;
+	else if (dm->support_ic_type & ODM_IC_3SS)
+		rate_num = 3;
+	else if (dm->support_ic_type & ODM_IC_2SS)
+		rate_num = 2;
+
+	if (dm->support_ic_type & ODM_ADAPTIVE_SOML_SUPPORT_IC) {
+		PHYDM_DBG(dm, DBG_ADPTV_SOML, "soml_state_cnt =((%d))\n",
+			  dm_soml_table->soml_state_cnt);
+		/*Traning state: 0(alt) 1(ori) 2(alt) 3(ori)============================================================*/
+		if (dm_soml_table->soml_state_cnt < (dm_soml_table->soml_train_num << 1)) {
+			if (dm_soml_table->soml_state_cnt == 0) {
+				phydm_soml_reset_rx_rate(dm);
+				odm_move_memory(dm, dm_soml_table->num_ht_bytes, ht_reset, HT_RATE_IDX * size);
+				odm_move_memory(dm, dm_soml_table->num_ht_bytes_on, ht_reset, HT_RATE_IDX * size);
+				odm_move_memory(dm, dm_soml_table->num_ht_bytes_off, ht_reset, HT_RATE_IDX * size);
+				odm_move_memory(dm, dm_soml_table->num_vht_bytes, vht_reset, VHT_RATE_IDX * size);
+				odm_move_memory(dm, dm_soml_table->num_vht_bytes_on, vht_reset, VHT_RATE_IDX * size);
+				odm_move_memory(dm, dm_soml_table->num_vht_bytes_off, vht_reset, VHT_RATE_IDX * size);
+				if (dm->support_ic_type == ODM_RTL8822B) {
+					dm_soml_table->cfo_counter++;
+					phydm_soml_cfo_process(dm,
+							       &dm_soml_table->cfo_diff_a,
+							       &dm_soml_table->cfo_diff_b);
+					PHYDM_DBG(dm, DBG_ADPTV_SOML, "[ (%d) cfo_diff_a = %d KHz; cfo_diff_b = %d KHz ]\n", dm_soml_table->cfo_counter, dm_soml_table->cfo_diff_a, dm_soml_table->cfo_diff_b);
+					dm_soml_table->cfo_diff_sum_a += dm_soml_table->cfo_diff_a;
+					dm_soml_table->cfo_diff_sum_b += dm_soml_table->cfo_diff_b;
+				}
+
+				dm_soml_table->is_soml_method_enable = 1;
+				dm_soml_table->soml_state_cnt++;
+				next_on_off = (dm_soml_table->soml_on_off == SOML_ON) ? SOML_ON : SOML_OFF;
+				phydm_soml_on_off(dm, next_on_off);
+				odm_set_timer(dm, &dm_soml_table->phydm_adaptive_soml_timer, dm_soml_table->soml_delay_time); /*@ms*/
+			} else if ((dm_soml_table->soml_state_cnt % 2) != 0) {
+				dm_soml_table->soml_state_cnt++;
+				odm_move_memory(dm, dm_soml_table->pre_num_ht_cnt, dm_soml_table->num_ht_cnt, HT_RATE_IDX * size);
+				odm_move_memory(dm, dm_soml_table->pre_num_vht_cnt, dm_soml_table->num_vht_cnt, VHT_RATE_IDX * size);
+				odm_move_memory(dm, dm_soml_table->pre_num_ht_bytes, dm_soml_table->num_ht_bytes, HT_RATE_IDX * size);
+				odm_move_memory(dm, dm_soml_table->pre_num_vht_bytes, dm_soml_table->num_vht_bytes, VHT_RATE_IDX * size);
+
+				if (dm->support_ic_type == ODM_RTL8822B) {
+					dm_soml_table->cfo_counter++;
+					phydm_soml_cfo_process(dm,
+							       &dm_soml_table->cfo_diff_a,
+							       &dm_soml_table->cfo_diff_b);
+					PHYDM_DBG(dm, DBG_ADPTV_SOML, "[ (%d) cfo_diff_a = %d KHz; cfo_diff_b = %d KHz ]\n", dm_soml_table->cfo_counter, dm_soml_table->cfo_diff_a, dm_soml_table->cfo_diff_b);
+					dm_soml_table->cfo_diff_sum_a += dm_soml_table->cfo_diff_a;
+					dm_soml_table->cfo_diff_sum_b += dm_soml_table->cfo_diff_b;
+				}
+				odm_set_timer(dm, &dm_soml_table->phydm_adaptive_soml_timer, dm_soml_table->soml_intvl); /*@ms*/
+			} else if ((dm_soml_table->soml_state_cnt % 2) == 0) {
+				if (dm->support_ic_type == ODM_RTL8822B) {
+					dm_soml_table->cfo_counter++;
+					phydm_soml_cfo_process(dm,
+							       &dm_soml_table->cfo_diff_a,
+							       &dm_soml_table->cfo_diff_b);
+					PHYDM_DBG(dm, DBG_ADPTV_SOML, "[ (%d) cfo_diff_a = %d KHz; cfo_diff_b = %d KHz ]\n", dm_soml_table->cfo_counter, dm_soml_table->cfo_diff_a, dm_soml_table->cfo_diff_b);
+					dm_soml_table->cfo_diff_sum_a += dm_soml_table->cfo_diff_a;
+					dm_soml_table->cfo_diff_sum_b += dm_soml_table->cfo_diff_b;
+				}
+				dm_soml_table->soml_state_cnt++;
+				phydm_soml_statistics(dm, dm_soml_table->soml_on_off);
+				next_on_off = (dm_soml_table->soml_on_off == SOML_ON) ? SOML_OFF : SOML_ON;
+				phydm_soml_on_off(dm, next_on_off);
+				odm_set_timer(dm, &dm_soml_table->phydm_adaptive_soml_timer, dm_soml_table->soml_delay_time); /*@ms*/
+			}
+		}
+		/*@Decision state: ==============================================================*/
+		else {
+			PHYDM_DBG(dm, DBG_ADPTV_SOML, "[Decisoin state ]\n");
+			phydm_soml_statistics(dm, dm_soml_table->soml_on_off);
+			if (*dm->channel <= 14) {
+				/* @[Search 1st and 2nd rate by counter] */
+				for (i = 0; i < rate_num; i++) {
+					rate_ss_shift = (i << 3);
+					PHYDM_DBG(dm, DBG_ADPTV_SOML, "*num_ht_cnt_on  HT MCS[%d :%d ] = {%d, %d, %d, %d, %d, %d, %d, %d}\n",
+						  (rate_ss_shift), (rate_ss_shift + 7),
+						  dm_soml_table->num_ht_cnt_on[rate_ss_shift + 0], dm_soml_table->num_ht_cnt_on[rate_ss_shift + 1],
+						  dm_soml_table->num_ht_cnt_on[rate_ss_shift + 2], dm_soml_table->num_ht_cnt_on[rate_ss_shift + 3],
+						  dm_soml_table->num_ht_cnt_on[rate_ss_shift + 4], dm_soml_table->num_ht_cnt_on[rate_ss_shift + 5],
+						  dm_soml_table->num_ht_cnt_on[rate_ss_shift + 6], dm_soml_table->num_ht_cnt_on[rate_ss_shift + 7]);
+				}
+
+				for (i = 0; i < rate_num; i++) {
+					rate_ss_shift = (i << 3);
+					PHYDM_DBG(dm, DBG_ADPTV_SOML, "*num_ht_bytes_off  HT MCS[%d :%d ] = {%d, %d, %d, %d, %d, %d, %d, %d}\n",
+						  (rate_ss_shift), (rate_ss_shift + 7),
+						  dm_soml_table->num_ht_cnt_off[rate_ss_shift + 0], dm_soml_table->num_ht_cnt_off[rate_ss_shift + 1],
+						  dm_soml_table->num_ht_cnt_off[rate_ss_shift + 2], dm_soml_table->num_ht_cnt_off[rate_ss_shift + 3],
+						  dm_soml_table->num_ht_cnt_off[rate_ss_shift + 4], dm_soml_table->num_ht_cnt_off[rate_ss_shift + 5],
+						  dm_soml_table->num_ht_cnt_off[rate_ss_shift + 6], dm_soml_table->num_ht_cnt_off[rate_ss_shift + 7]);
+				}
+
+				for (i = ODM_RATEMCS8; i <= ODM_RATEMCS15; i++) {
+					num_ht_total_cnt_on += dm_soml_table->num_ht_cnt_on[i - ODM_RATEMCS0];
+					num_ht_total_cnt_off += dm_soml_table->num_ht_cnt_off[i - ODM_RATEMCS0];
+					total_ht_rate_on += (dm_soml_table->num_ht_cnt_on[i - ODM_RATEMCS0] * phy_rate_table[i]);
+					total_ht_rate_off += (dm_soml_table->num_ht_cnt_off[i - ODM_RATEMCS0] * phy_rate_table[i]);
+				}
+				rate_per_pkt_on = (num_ht_total_cnt_on != 0) ? ((total_ht_rate_on << 3) / num_ht_total_cnt_on) : 0;
+				rate_per_pkt_off = (num_ht_total_cnt_off != 0) ? ((total_ht_rate_off << 3) / num_ht_total_cnt_off) : 0;
+			}
+#if 0
+			if (*dm->channel <= 14) {
+			/* @[Search 1st and 2ed rate by counter] */
+				for (i = 0; i < rate_num; i++) {
+					rate_ss_shift = (i << 3);
+					PHYDM_DBG(dm, DBG_ADPTV_SOML, "*num_ht_bytes_on  HT MCS[%d :%d ] = {%d, %d, %d, %d, %d, %d, %d, %d}\n",
+						(rate_ss_shift), (rate_ss_shift + 7),
+						dm_soml_table->num_ht_bytes_on[rate_ss_shift + 0], dm_soml_table->num_ht_bytes_on[rate_ss_shift + 1],
+						dm_soml_table->num_ht_bytes_on[rate_ss_shift + 2], dm_soml_table->num_ht_bytes_on[rate_ss_shift + 3],
+						dm_soml_table->num_ht_bytes_on[rate_ss_shift + 4], dm_soml_table->num_ht_bytes_on[rate_ss_shift + 5],
+						dm_soml_table->num_ht_bytes_on[rate_ss_shift + 6], dm_soml_table->num_ht_bytes_on[rate_ss_shift + 7]);
+				}
+
+				for (i = 0; i < rate_num; i++) {
+					rate_ss_shift = (i << 3);
+					PHYDM_DBG(dm, DBG_ADPTV_SOML, "*num_ht_bytes_off  HT MCS[%d :%d ] = {%d, %d, %d, %d, %d, %d, %d, %d}\n",
+						(rate_ss_shift), (rate_ss_shift + 7),
+						dm_soml_table->num_ht_bytes_off[rate_ss_shift + 0], dm_soml_table->num_ht_bytes_off[rate_ss_shift + 1],
+						dm_soml_table->num_ht_bytes_off[rate_ss_shift + 2], dm_soml_table->num_ht_bytes_off[rate_ss_shift + 3],
+						dm_soml_table->num_ht_bytes_off[rate_ss_shift + 4], dm_soml_table->num_ht_bytes_off[rate_ss_shift + 5],
+						dm_soml_table->num_ht_bytes_off[rate_ss_shift + 6], dm_soml_table->num_ht_bytes_off[rate_ss_shift + 7]);
+				}
+
+				for (i = ODM_RATEMCS8; i <= ODM_RATEMCS15; i++) {
+					byte_total_on += dm_soml_table->num_ht_bytes_on[i - ODM_RATEMCS0];
+					byte_total_off += dm_soml_table->num_ht_bytes_off[i - ODM_RATEMCS0];
+				}
+			}
+#endif
+
+			if (dm->support_ic_type == ODM_RTL8822B) {
+				dm_soml_table->cfo_diff_avg_a = (dm_soml_table->cfo_counter != 0) ? (dm_soml_table->cfo_diff_sum_a / dm_soml_table->cfo_counter) : 0;
+				dm_soml_table->cfo_diff_avg_b = (dm_soml_table->cfo_counter != 0) ? (dm_soml_table->cfo_diff_sum_b / dm_soml_table->cfo_counter) : 0;
+				PHYDM_DBG(dm, DBG_ADPTV_SOML,
+					  "[ cfo_diff_avg_a = %d KHz; cfo_diff_avg_b = %d KHz]\n",
+					  dm_soml_table->cfo_diff_avg_a,
+					  dm_soml_table->cfo_diff_avg_b);
+				for (i = 0; i < VHT_ORDER_TYPE; i++)
+					num_total_qam += dm_soml_table->num_vht_qam[i];
+
+				PHYDM_DBG(dm, DBG_ADPTV_SOML,
+					  "[ ((2SS)) BPSK_QPSK_count = %d ; 16QAM_count = %d ; 64QAM_count = %d ; 256QAM_count = %d ; num_total_qam = %d]\n",
+					  dm_soml_table->num_vht_qam[BPSK_QPSK],
+					  dm_soml_table->num_vht_qam[QAM16],
+					  dm_soml_table->num_vht_qam[QAM64],
+					  dm_soml_table->num_vht_qam[QAM256],
+					  num_total_qam);
+				if (((dm_soml_table->num_vht_qam[QAM256] * 100) > (num_total_qam * dm_soml_table->qam256_dist_th)) && dm_soml_table->cfo_diff_avg_a > dm_soml_table->cfo_qam256_th && dm_soml_table->cfo_diff_avg_b > dm_soml_table->cfo_qam256_th) {
+					PHYDM_DBG(dm, DBG_ADPTV_SOML, "[  QAM256_ratio > %d ; cfo_diff_avg_a > %d KHz ==> SOML_OFF]\n", dm_soml_table->qam256_dist_th, dm_soml_table->cfo_qam256_th);
+					PHYDM_DBG(dm, DBG_ADPTV_SOML, "[ Final decisoin ] : ");
+					phydm_soml_on_off(dm, SOML_OFF);
+					return;
+				} else if (((dm_soml_table->num_vht_qam[QAM64] * 100) > (num_total_qam * dm_soml_table->qam64_dist_th)) && (dm_soml_table->cfo_diff_avg_a > dm_soml_table->cfo_qam64_th) && (dm_soml_table->cfo_diff_avg_b > dm_soml_table->cfo_qam64_th)) {
+					PHYDM_DBG(dm, DBG_ADPTV_SOML, "[  QAM64_ratio > %d ; cfo_diff_avg_a > %d KHz ==> SOML_OFF]\n", dm_soml_table->qam64_dist_th, dm_soml_table->cfo_qam64_th);
+					PHYDM_DBG(dm, DBG_ADPTV_SOML, "[ Final decisoin ] : ");
+					phydm_soml_on_off(dm, SOML_OFF);
+					return;
+				} else if (((dm_soml_table->num_vht_qam[QAM16] * 100) > (num_total_qam * dm_soml_table->qam16_dist_th)) && (dm_soml_table->cfo_diff_avg_a > dm_soml_table->cfo_qam16_th) && (dm_soml_table->cfo_diff_avg_b > dm_soml_table->cfo_qam16_th)) {
+					PHYDM_DBG(dm, DBG_ADPTV_SOML, "[  QAM16_ratio > %d ; cfo_diff_avg_a > %d KHz ==> SOML_OFF]\n", dm_soml_table->qam16_dist_th, dm_soml_table->cfo_qam16_th);
+					PHYDM_DBG(dm, DBG_ADPTV_SOML, "[ Final decisoin ] : ");
+					phydm_soml_on_off(dm, SOML_OFF);
+					return;
+				} else if (((dm_soml_table->num_vht_qam[BPSK_QPSK] * 100) > (num_total_qam * dm_soml_table->bpsk_qpsk_dist_th)) && (dm_soml_table->cfo_diff_avg_a > dm_soml_table->cfo_qpsk_th) && (dm_soml_table->cfo_diff_avg_b > dm_soml_table->cfo_qpsk_th)) {
+					PHYDM_DBG(dm, DBG_ADPTV_SOML, "[  BPSK_QPSK_ratio > %d ; cfo_diff_avg_a > %d KHz ==> SOML_OFF]\n", dm_soml_table->bpsk_qpsk_dist_th, dm_soml_table->cfo_qpsk_th);
+					PHYDM_DBG(dm, DBG_ADPTV_SOML, "[ Final decisoin ] : ");
+					phydm_soml_on_off(dm, SOML_OFF);
+					return;
+				}
+
+				for (i = 0; i < rate_num; i++) {
+					rate_ss_shift = 10 * i;
+					PHYDM_DBG(dm, DBG_ADPTV_SOML, "[  num_vht_cnt_on  VHT-%d ss MCS[0:9] = {%d, %d, %d, %d, %d, %d, %d, %d, %d, %d} ]\n",
+						  (i + 1),
+						  dm_soml_table->num_vht_cnt_on[rate_ss_shift + 0], dm_soml_table->num_vht_cnt_on[rate_ss_shift + 1],
+						  dm_soml_table->num_vht_cnt_on[rate_ss_shift + 2], dm_soml_table->num_vht_cnt_on[rate_ss_shift + 3],
+						  dm_soml_table->num_vht_cnt_on[rate_ss_shift + 4], dm_soml_table->num_vht_cnt_on[rate_ss_shift + 5],
+						  dm_soml_table->num_vht_cnt_on[rate_ss_shift + 6], dm_soml_table->num_vht_cnt_on[rate_ss_shift + 7],
+						  dm_soml_table->num_vht_cnt_on[rate_ss_shift + 8], dm_soml_table->num_vht_cnt_on[rate_ss_shift + 9]);
+				}
+
+				for (i = 0; i < rate_num; i++) {
+					rate_ss_shift = 10 * i;
+					PHYDM_DBG(dm, DBG_ADPTV_SOML, "[  num_vht_cnt_off  VHT-%d ss MCS[0:9] = {%d, %d, %d, %d, %d, %d, %d, %d, %d, %d} ]\n",
+						  (i + 1),
+						  dm_soml_table->num_vht_cnt_off[rate_ss_shift + 0], dm_soml_table->num_vht_cnt_off[rate_ss_shift + 1],
+						  dm_soml_table->num_vht_cnt_off[rate_ss_shift + 2], dm_soml_table->num_vht_cnt_off[rate_ss_shift + 3],
+						  dm_soml_table->num_vht_cnt_off[rate_ss_shift + 4], dm_soml_table->num_vht_cnt_off[rate_ss_shift + 5],
+						  dm_soml_table->num_vht_cnt_off[rate_ss_shift + 6], dm_soml_table->num_vht_cnt_off[rate_ss_shift + 7],
+						  dm_soml_table->num_vht_cnt_off[rate_ss_shift + 8], dm_soml_table->num_vht_cnt_off[rate_ss_shift + 9]);
+				}
+
+				for (i = ODM_RATEVHTSS2MCS0; i <= ODM_RATEVHTSS2MCS9; i++) {
+					num_vht_total_cnt_on += dm_soml_table->num_vht_cnt_on[i - ODM_RATEVHTSS1MCS0];
+					num_vht_total_cnt_off += dm_soml_table->num_vht_cnt_off[i - ODM_RATEVHTSS1MCS0];
+					total_vht_rate_on += (dm_soml_table->num_vht_cnt_on[i - ODM_RATEVHTSS1MCS0] * vht_phy_rate_table[i - ODM_RATEVHTSS1MCS0]);
+					total_vht_rate_off += (dm_soml_table->num_vht_cnt_off[i - ODM_RATEVHTSS1MCS0] * vht_phy_rate_table[i - ODM_RATEVHTSS1MCS0]);
+				}
+				rate_per_pkt_on = (num_vht_total_cnt_on != 0) ? ((total_vht_rate_on << 3) / num_vht_total_cnt_on) : 0;
+				rate_per_pkt_off = (num_vht_total_cnt_off != 0) ? ((total_vht_rate_off << 3) / num_vht_total_cnt_off) : 0;
+
+				#if 0
+				for (i = 0; i < rate_num; i++) {
+					rate_ss_shift = 10 * i;
+					PHYDM_DBG(dm, DBG_ADPTV_SOML, "[  num_vht_bytes_on  VHT-%d ss MCS[0:9] = {%d, %d, %d, %d, %d, %d, %d, %d, %d, %d} ]\n",
+						(i + 1),
+						dm_soml_table->num_vht_bytes_on[rate_ss_shift + 0], dm_soml_table->num_vht_bytes_on[rate_ss_shift + 1],
+						dm_soml_table->num_vht_bytes_on[rate_ss_shift + 2], dm_soml_table->num_vht_bytes_on[rate_ss_shift + 3],
+						dm_soml_table->num_vht_bytes_on[rate_ss_shift + 4], dm_soml_table->num_vht_bytes_on[rate_ss_shift + 5],
+						dm_soml_table->num_vht_bytes_on[rate_ss_shift + 6], dm_soml_table->num_vht_bytes_on[rate_ss_shift + 7],
+						dm_soml_table->num_vht_bytes_on[rate_ss_shift + 8], dm_soml_table->num_vht_bytes_on[rate_ss_shift + 9]);
+				}
+
+				for (i = 0; i < rate_num; i++) {
+					rate_ss_shift = 10 * i;
+					PHYDM_DBG(dm, DBG_ADPTV_SOML, "[  num_vht_bytes_off  VHT-%d ss MCS[0:9] = {%d, %d, %d, %d, %d, %d, %d, %d, %d, %d} ]\n",
+						(i + 1),
+						dm_soml_table->num_vht_bytes_off[rate_ss_shift + 0], dm_soml_table->num_vht_bytes_off[rate_ss_shift + 1],
+						dm_soml_table->num_vht_bytes_off[rate_ss_shift + 2], dm_soml_table->num_vht_bytes_off[rate_ss_shift + 3],
+						dm_soml_table->num_vht_bytes_off[rate_ss_shift + 4], dm_soml_table->num_vht_bytes_off[rate_ss_shift + 5],
+						dm_soml_table->num_vht_bytes_off[rate_ss_shift + 6], dm_soml_table->num_vht_bytes_off[rate_ss_shift + 7],
+						dm_soml_table->num_vht_bytes_off[rate_ss_shift + 8], dm_soml_table->num_vht_bytes_off[rate_ss_shift + 9]);
+				}
+
+				for (i = ODM_RATEVHTSS2MCS0; i <= ODM_RATEVHTSS2MCS9; i++) {
+					byte_total_on += dm_soml_table->num_vht_bytes_on[i - ODM_RATEVHTSS1MCS0];
+					byte_total_off += dm_soml_table->num_vht_bytes_off[i - ODM_RATEVHTSS1MCS0];
+				}
+				#endif
+			}
+
+			/* @[Decision] */
+			PHYDM_DBG(dm, DBG_ADPTV_SOML,
+				  "[  rate_per_pkt_on = %d ; rate_per_pkt_off = %d ]\n",
+				  rate_per_pkt_on, rate_per_pkt_off);
+			if (rate_per_pkt_on > rate_per_pkt_off) {
+				next_on_off = SOML_ON;
+				PHYDM_DBG(dm, DBG_ADPTV_SOML,
+					  "[ rate_per_pkt_on > rate_per_pkt_off ==> SOML_ON ]\n");
+			} else if (rate_per_pkt_on < rate_per_pkt_off) {
+				next_on_off = SOML_OFF;
+				PHYDM_DBG(dm, DBG_ADPTV_SOML,
+					  "[ rate_per_pkt_on < rate_per_pkt_off ==> SOML_OFF ]\n");
+			} else {
+				PHYDM_DBG(dm, DBG_ADPTV_SOML,
+					  "[ stay at soml_last_state ]\n");
+				next_on_off = dm_soml_table->soml_last_state;
+			}
+			#if 0
+			PHYDM_DBG(dm, DBG_ADPTV_SOML,
+				  "[  byte_total_on = %d ; byte_total_off = %d ]\n",
+				  byte_total_on, byte_total_off);
+			if (byte_total_on > byte_total_off) {
+				next_on_off = SOML_ON;
+				PHYDM_DBG(dm, DBG_ADPTV_SOML,
+					  "[ byte_total_on > byte_total_off ==> SOML_ON ]\n");
+			} else if (byte_total_on < byte_total_off) {
+				next_on_off = SOML_OFF;
+				PHYDM_DBG(dm, DBG_ADPTV_SOML,
+					  "[ byte_total_on < byte_total_off ==> SOML_OFF ]\n");
+			} else {
+				PHYDM_DBG(dm, DBG_ADPTV_SOML,
+					  "[ stay at soml_last_state ]\n");
+				next_on_off = dm_soml_table->soml_last_state;
+			}
+			#endif
+
+			PHYDM_DBG(dm, DBG_ADPTV_SOML, "[ Final decisoin ] : ");
+			phydm_soml_on_off(dm, next_on_off);
+			dm_soml_table->soml_last_state = next_on_off;
+		}
+	}
+}
+void phydm_adaptive_soml_reset(
+	void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct adaptive_soml *dm_soml_table = &dm->dm_soml_table;
+
+	dm_soml_table->soml_state_cnt = 0;
+	dm_soml_table->is_soml_method_enable = 0;
+	dm_soml_table->soml_counter = 0;
+}
+
+void phydm_set_adsl_val(
+	void *dm_void,
+	u32 *val_buf,
+	u8 val_len)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+
+	if (val_len != 1) {
+		PHYDM_DBG(dm, ODM_COMP_API, "[Error][ADSL]Need val_len=1\n");
+		return;
+	}
+
+	phydm_soml_on_off(dm, (u8)val_buf[1]);
+}
+
+void phydm_soml_bytes_acq(void *dm_void, u8 rate_id, u32 length)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct adaptive_soml *dm_soml_table = &dm->dm_soml_table;
+
+	if (rate_id >= ODM_RATEMCS0 && rate_id <= ODM_RATEMCS31)
+		dm_soml_table->num_ht_bytes[rate_id - ODM_RATEMCS0] += length;
+	else if ((rate_id >= ODM_RATEVHTSS1MCS0) && (rate_id <= ODM_RATEVHTSS4MCS9))
+		dm_soml_table->num_vht_bytes[rate_id - ODM_RATEVHTSS1MCS0] += length;
+
+}
+
+void phydm_adaptive_soml_timers(void *dm_void, u8 state)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct adaptive_soml *dm_soml_table = &dm->dm_soml_table;
+
+	if (state == INIT_SOML_TIMMER) {
+		odm_initialize_timer(dm, &dm_soml_table->phydm_adaptive_soml_timer,
+				     (void *)phydm_adaptive_soml_callback, NULL, "phydm_adaptive_soml_timer");
+	} else if (state == CANCEL_SOML_TIMMER) {
+		odm_cancel_timer(dm, &dm_soml_table->phydm_adaptive_soml_timer);
+	} else if (state == RELEASE_SOML_TIMMER) {
+		odm_release_timer(dm, &dm_soml_table->phydm_adaptive_soml_timer);
+	}
+}
+
+void phydm_adaptive_soml_init(void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct adaptive_soml *dm_soml_table = &dm->dm_soml_table;
+#if 0
+	if (!(dm->support_ability & ODM_BB_ADAPTIVE_SOML)) {
+		PHYDM_DBG(dm, DBG_ADPTV_SOML,
+			  "[Return]   Not Support Adaptive SOML\n");
+		return;
+	}
+#endif
+	PHYDM_DBG(dm, DBG_ADPTV_SOML, "%s\n", __func__);
+
+	dm_soml_table->soml_state_cnt = 0;
+	dm_soml_table->soml_delay_time = 40;
+	dm_soml_table->soml_intvl = 150;
+	dm_soml_table->soml_train_num = 4;
+	dm_soml_table->is_soml_method_enable = 0;
+	dm_soml_table->soml_counter = 0;
+	dm_soml_table->soml_period = 1;
+	dm_soml_table->soml_select = 0;
+	dm_soml_table->cfo_counter = 0;
+	dm_soml_table->cfo_diff_sum_a = 0;
+	dm_soml_table->cfo_diff_sum_b = 0;
+
+	dm_soml_table->cfo_qpsk_th = 94;
+	dm_soml_table->cfo_qam16_th = 38;
+	dm_soml_table->cfo_qam64_th = 17;
+	dm_soml_table->cfo_qam256_th = 7;
+
+	dm_soml_table->bpsk_qpsk_dist_th = 20;
+	dm_soml_table->qam16_dist_th = 20;
+	dm_soml_table->qam64_dist_th = 20;
+	dm_soml_table->qam256_dist_th = 20;
+
+	if (dm->support_ic_type & (ODM_RTL8197F | ODM_RTL8192F))
+		odm_set_bb_reg(dm, 0x988, BIT(25), 1);
+}
+
+void phydm_adaptive_soml(void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct adaptive_soml *dm_soml_table = &dm->dm_soml_table;
+
+	if (!(dm->support_ability & ODM_BB_ADAPTIVE_SOML)) {
+		PHYDM_DBG(dm, DBG_ADPTV_SOML,
+			  "[Return!!!] Not Support Adaptive SOML Function\n");
+		return;
+	}
+
+	if (dm->pause_ability & ODM_BB_ADAPTIVE_SOML) {
+		PHYDM_DBG(dm, DBG_ADPTV_SOML, "Return: Pause ADSL in LV=%d\n",
+			  dm->pause_lv_table.lv_adsl);
+		return;
+	}
+
+	if (dm_soml_table->soml_counter < dm_soml_table->soml_period) {
+		dm_soml_table->soml_counter++;
+		return;
+	}
+	dm_soml_table->soml_counter = 0;
+	dm_soml_table->soml_state_cnt = 0;
+	dm_soml_table->cfo_counter = 0;
+	dm_soml_table->cfo_diff_sum_a = 0;
+	dm_soml_table->cfo_diff_sum_b = 0;
+
+	phydm_soml_reset_qam(dm);
+
+	if (dm_soml_table->soml_select == 0) {
+		PHYDM_DBG(dm, DBG_ADPTV_SOML,
+			  "[ Adaptive SOML Training !!!]\n");
+	} else if (dm_soml_table->soml_select == 1) {
+		PHYDM_DBG(dm, DBG_ADPTV_SOML, "[ Stop Adaptive SOML !!!]\n");
+		phydm_soml_on_off(dm, SOML_ON);
+		return;
+	} else if (dm_soml_table->soml_select == 2) {
+		PHYDM_DBG(dm, DBG_ADPTV_SOML, "[ Stop Adaptive SOML !!!]\n");
+		phydm_soml_on_off(dm, SOML_OFF);
+		return;
+	}
+
+	if (dm->support_ic_type & ODM_ADAPTIVE_SOML_SUPPORT_IC)
+		phydm_adsl(dm);
+}
+
+void phydm_enable_adaptive_soml(void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+
+	PHYDM_DBG(dm, DBG_ADPTV_SOML, "[%s]\n", __func__);
+	dm->support_ability |= ODM_BB_ADAPTIVE_SOML;
+	phydm_soml_on_off(dm, SOML_ON);
+}
+
+void phydm_stop_adaptive_soml(void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+
+	PHYDM_DBG(dm, DBG_ADPTV_SOML, "[%s]\n", __func__);
+	dm->support_ability &= ~ODM_BB_ADAPTIVE_SOML;
+	phydm_soml_on_off(dm, SOML_ON);
+}
+
+void phydm_adaptive_soml_para_set(void *dm_void, u8 train_num, u8 intvl,
+				  u8 period, u8 delay_time)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct adaptive_soml *dm_soml_table = &dm->dm_soml_table;
+
+	dm_soml_table->soml_train_num = train_num;
+	dm_soml_table->soml_intvl = intvl;
+	dm_soml_table->soml_period = period;
+	dm_soml_table->soml_delay_time = delay_time;
+}
+#endif /* @end of CONFIG_ADAPTIVE_SOML*/
+
+void phydm_init_soft_ml_setting(void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	u32 soml_mask = BIT(31) | BIT(30) | BIT(29) | BIT(28);
+
+#if (RTL8822B_SUPPORT == 1)
+	if (!*dm->mp_mode) {
+		if (dm->support_ic_type & ODM_RTL8822B) {
+#if 0
+			/*odm_set_bb_reg(dm, R_0x19a8, MASKDWORD, 0xd10a0000);*/
+#endif
+			phydm_somlrxhp_setting(dm, true);
+			dm->bsomlenabled = true;
+		}
+	}
+#endif
+#if (RTL8821C_SUPPORT == 1)
+	if (!*dm->mp_mode) {
+		if (dm->support_ic_type & ODM_RTL8821C)
+			odm_set_bb_reg(dm, R_0x19a8, soml_mask, 0xd);
+	}
+#endif
+#if (RTL8195B_SUPPORT == 1)
+	if (!*dm->mp_mode) {
+		if (dm->support_ic_type & ODM_RTL8195B)
+			odm_set_bb_reg(dm, R_0x19a8, soml_mask, 0xd);
+	}
+#endif
+}
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/phydm_soml.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/phydm_soml.h
--- linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/phydm_soml.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/phydm_soml.h	2020-04-10 16:35:06.827660581 +0300
@@ -0,0 +1,210 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017  Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * The full GNU General Public License is included in this distribution in the
+ * file called LICENSE.
+ *
+ * Contact Information:
+ * wlanfae <wlanfae@realtek.com>
+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
+ * Hsinchu 300, Taiwan.
+ *
+ * Larry Finger <Larry.Finger@lwfinger.net>
+ *
+ *****************************************************************************/
+#ifndef __PHYDMSOML_H__
+#define __PHYDMSOML_H__
+
+/*@#define ADAPTIVE_SOML_VERSION	"1.0" Byte counter version*/
+#define ADAPTIVE_SOML_VERSION "2.0" /*@add avg. phy rate decision 20180126*/
+
+#define ODM_ADAPTIVE_SOML_SUPPORT_IC	(ODM_RTL8822B | ODM_RTL8197F | ODM_RTL8192F)/*@jj add 20170822*/
+
+#define INIT_SOML_TIMMER			0
+#define CANCEL_SOML_TIMMER			1
+#define RELEASE_SOML_TIMMER		2
+
+#define SOML_RSSI_TH_HIGH	25
+#define SOML_RSSI_TH_LOW	20
+
+#define HT_RATE_IDX			32
+#define VHT_RATE_IDX		40
+
+#define HT_ORDER_TYPE		3
+#define VHT_ORDER_TYPE		4
+
+#if 0
+#define CFO_QPSK_TH			20
+#define CFO_QAM16_TH		20
+#define CFO_QAM64_TH		20
+#define CFO_QAM256_TH		20
+
+#define BPSK_QPSK_DIST		20
+#define QAM16_DIST			30
+#define QAM64_DIST			30
+#define QAM256_DIST			20
+#endif
+#define HT_TYPE		1
+#define VHT_TYPE		2
+
+#define SOML_ON		1
+#define SOML_OFF		0
+
+#ifdef CONFIG_ADAPTIVE_SOML
+
+struct adaptive_soml {
+	u8			rvrt_val;
+	boolean			is_soml_method_enable;
+	u8			soml_on_off;
+	u8			soml_state_cnt;
+	u8			soml_delay_time;
+	u8			soml_intvl;
+	u8			soml_train_num;
+	u8			soml_counter;
+	u8			soml_period;
+	u8			soml_select;
+	u8			soml_last_state;
+	u8			cfo_qpsk_th;
+	u8			cfo_qam16_th;
+	u8			cfo_qam64_th;
+	u8			cfo_qam256_th;
+	u8			bpsk_qpsk_dist_th;
+	u8			qam16_dist_th;
+	u8			qam64_dist_th;
+	u8			qam256_dist_th;
+	u8			cfo_counter;
+	s32			cfo_diff_a;
+	s32			cfo_diff_b;
+	s32			cfo_diff_sum_a;
+	s32			cfo_diff_sum_b;
+	s32			cfo_diff_avg_a;
+	s32			cfo_diff_avg_b;
+	u32			num_ht_cnt[HT_RATE_IDX];
+	u32			pre_num_ht_cnt[HT_RATE_IDX];
+	u32			num_ht_cnt_on[HT_RATE_IDX];
+	u32			num_ht_cnt_off[HT_RATE_IDX];
+
+	u32			num_vht_cnt[VHT_RATE_IDX];
+	u32			pre_num_vht_cnt[VHT_RATE_IDX];
+	u32			num_vht_cnt_on[VHT_RATE_IDX];
+	u32			num_vht_cnt_off[VHT_RATE_IDX];
+
+	u32			num_ht_qam[HT_ORDER_TYPE];
+	u32			num_ht_bytes[HT_RATE_IDX];
+	u32			pre_num_ht_bytes[HT_RATE_IDX];
+	u32			num_ht_bytes_on[HT_RATE_IDX];
+	u32			num_ht_bytes_off[HT_RATE_IDX];
+	u32			num_vht_qam[VHT_ORDER_TYPE];
+	u32			num_qry_mu_vht_pkt[VHT_RATE_IDX];
+	u32			num_vht_bytes[VHT_RATE_IDX];
+	u32			pre_num_vht_bytes[VHT_RATE_IDX];
+	u32			num_vht_bytes_on[VHT_RATE_IDX];
+	u32			num_vht_bytes_off[VHT_RATE_IDX];
+
+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
+#if USE_WORKITEM
+	RT_WORK_ITEM	phydm_adaptive_soml_workitem;
+#endif
+#endif
+	struct phydm_timer_list		phydm_adaptive_soml_timer;
+
+};
+
+enum qam_order {
+	BPSK_QPSK	= 0,
+	QAM16		= 1,
+	QAM64		= 2,
+	QAM256		= 3
+};
+
+void phydm_dynamicsoftmletting(void *dm_void);
+
+void phydm_soml_on_off(
+	void *dm_void,
+	u8 swch);
+
+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
+void phydm_adaptive_soml_callback(
+	struct phydm_timer_list *timer);
+
+void phydm_adaptive_soml_workitem_callback(
+	void *context);
+
+#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
+void phydm_adaptive_soml_callback(
+	void *dm_void);
+
+void phydm_adaptive_soml_workitem_callback(
+	void *context);
+
+#else
+void phydm_adaptive_soml_callback(
+	void *dm_void);
+#endif
+
+void phydm_rx_rate_for_soml(
+	void *dm_void,
+	void *pkt_info_void);
+
+void phydm_rx_qam_for_soml(
+	void *dm_void,
+	void *pkt_info_void);
+
+void phydm_soml_reset_rx_rate(
+	void *dm_void);
+
+void phydm_soml_reset_qam(
+	void *dm_void);
+
+void phydm_soml_cfo_process(
+	void *dm_void,
+	s32 *diff_a,
+	s32 *diff_b);
+
+void phydm_soml_debug(void *dm_void, char input[][16], u32 *_used,
+		      char *output, u32 *_out_len);
+
+void phydm_soml_statistics(
+	void *dm_void,
+	u8 on_off_state
+
+	);
+
+void phydm_adsl(
+	void *dm_void);
+
+void phydm_adaptive_soml_reset(
+	void *dm_void);
+
+void phydm_set_adsl_val(
+	void *dm_void,
+	u32 *val_buf,
+	u8 val_len);
+
+void phydm_soml_bytes_acq(void *dm_void, u8 rate_id, u32 length);
+
+void phydm_adaptive_soml_timers(void *dm_void, u8 state);
+
+void phydm_adaptive_soml_init(void *dm_void);
+
+void phydm_adaptive_soml(void *dm_void);
+
+void phydm_enable_adaptive_soml(void *dm_void);
+
+void phydm_stop_adaptive_soml(void *dm_void);
+
+void phydm_adaptive_soml_para_set(void *dm_void, u8 train_num, u8 intvl,
+				  u8 period, u8 delay_time);
+#endif
+void phydm_init_soft_ml_setting(void *dm_void);
+#endif /*@#ifndef	__PHYDMSOML_H__*/
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/phydm_types.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/phydm_types.h
--- linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/phydm_types.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/phydm_types.h	2020-04-10 16:35:06.827660581 +0300
@@ -0,0 +1,316 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017  Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * The full GNU General Public License is included in this distribution in the
+ * file called LICENSE.
+ *
+ * Contact Information:
+ * wlanfae <wlanfae@realtek.com>
+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
+ * Hsinchu 300, Taiwan.
+ *
+ * Larry Finger <Larry.Finger@lwfinger.net>
+ *
+ *****************************************************************************/
+#ifndef __ODM_TYPES_H__
+#define __ODM_TYPES_H__
+
+/*Define Different SW team support*/
+#define	ODM_AP			0x01	/*BIT(0)*/
+#define	ODM_CE			0x04	/*BIT(2)*/
+#define	ODM_WIN		0x08	/*BIT(3)*/
+#define	ODM_ADSL		0x10
+/*BIT(4)*/		/*already combine with ODM_AP, and is nouse now*/
+#define	ODM_IOT		0x20	/*BIT(5)*/
+
+/*For FW API*/
+#define	__iram_odm_func__
+
+/*Deifne HW endian support*/
+#define	ODM_ENDIAN_BIG	0
+#define	ODM_ENDIAN_LITTLE	1
+
+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
+	#define GET_PDM_ODM(__padapter)	((struct dm_struct*)(&(GET_HAL_DATA(__padapter))->DM_OutSrc))
+#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
+	#define GET_PDM_ODM(__padapter)	((struct dm_struct *)(&(GET_HAL_DATA(__padapter))->odmpriv))
+#elif (DM_ODM_SUPPORT_TYPE == ODM_AP)
+	#define GET_PDM_ODM(__padapter)	((struct dm_struct*)(&__padapter->pshare->_dmODM))
+#endif
+
+#if (DM_ODM_SUPPORT_TYPE != ODM_WIN)
+	#define	RT_PCI_INTERFACE				1
+	#define	RT_USB_INTERFACE				2
+	#define	RT_SDIO_INTERFACE				3
+#endif
+
+enum hal_status {
+	HAL_STATUS_SUCCESS,
+	HAL_STATUS_FAILURE,
+#if 0
+	RT_STATUS_PENDING,
+	RT_STATUS_RESOURCE,
+	RT_STATUS_INVALID_CONTEXT,
+	RT_STATUS_INVALID_PARAMETER,
+	RT_STATUS_NOT_SUPPORT,
+	RT_STATUS_OS_API_FAILED,
+#endif
+};
+
+#if (DM_ODM_SUPPORT_TYPE != ODM_WIN)
+
+#define		VISTA_USB_RX_REVISE			0
+
+/*
+ * Declare for ODM spin lock definition temporarily fro compile pass.
+ */
+enum rt_spinlock_type {
+	RT_TX_SPINLOCK = 1,
+	RT_RX_SPINLOCK = 2,
+	RT_RM_SPINLOCK = 3,
+	RT_CAM_SPINLOCK = 4,
+	RT_SCAN_SPINLOCK = 5,
+	RT_LOG_SPINLOCK = 7,
+	RT_BW_SPINLOCK = 8,
+	RT_CHNLOP_SPINLOCK = 9,
+	RT_RF_OPERATE_SPINLOCK = 10,
+	RT_INITIAL_SPINLOCK = 11,
+	RT_RF_STATE_SPINLOCK = 12,
+	/* For RF state. Added by Bruce, 2007-10-30. */
+#if VISTA_USB_RX_REVISE
+	RT_USBRX_CONTEXT_SPINLOCK = 13,
+	RT_USBRX_POSTPROC_SPINLOCK = 14,
+	/* protect data of adapter->IndicateW/ IndicateR */
+#endif
+	/* Shall we define Ndis 6.2 SpinLock Here ? */
+	RT_PORT_SPINLOCK = 16,
+	RT_VNIC_SPINLOCK = 17,
+	RT_HVL_SPINLOCK = 18,
+	RT_H2C_SPINLOCK = 20,
+	/* For H2C cmd. Added by tynli. 2009.11.09. */
+
+	rt_bt_data_spinlock = 25,
+
+	RT_WAPI_OPTION_SPINLOCK = 26,
+	RT_WAPI_RX_SPINLOCK = 27,
+
+	/* add for 92D CCK control issue */
+	RT_CCK_PAGEA_SPINLOCK = 28,
+	RT_BUFFER_SPINLOCK = 29,
+	RT_CHANNEL_AND_BANDWIDTH_SPINLOCK = 30,
+	RT_GEN_TEMP_BUF_SPINLOCK = 31,
+	RT_AWB_SPINLOCK = 32,
+	RT_FW_PS_SPINLOCK = 33,
+	RT_HW_TIMER_SPIN_LOCK = 34,
+	RT_MPT_WI_SPINLOCK = 35,
+	RT_P2P_SPIN_LOCK = 36,	/* Protect P2P context */
+	RT_DBG_SPIN_LOCK = 37,
+	RT_IQK_SPINLOCK = 38,
+	RT_PENDED_OID_SPINLOCK = 39,
+	RT_CHNLLIST_SPINLOCK = 40,
+	RT_INDIC_SPINLOCK = 41,	/* protect indication */
+	RT_RFD_SPINLOCK = 42,
+	RT_SYNC_IO_CNT_SPINLOCK = 43,
+	RT_LAST_SPINLOCK,
+};
+
+#endif
+
+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
+	#define sta_info 	_RT_WLAN_STA
+	#define	__func__		__FUNCTION__
+	#define	PHYDM_TESTCHIP_SUPPORT	TESTCHIP_SUPPORT
+	#define MASKH3BYTES			0xffffff00
+	#define SUCCESS	0
+	#define FAIL	(-1)
+
+	#define	u8 		u1Byte
+	#define	s8 		s1Byte
+
+	#define	u16		u2Byte
+	#define	s16		s2Byte
+
+	#define	u32 	u4Byte
+	#define	s32 		s4Byte
+
+	#define	u64		u8Byte
+	#define	s64		s8Byte
+
+	#define	phydm_timer_list	_RT_TIMER
+
+
+#elif (DM_ODM_SUPPORT_TYPE == ODM_AP)
+	#include "../typedef.h"
+
+	#ifdef CONFIG_PCI_HCI
+		#define DEV_BUS_TYPE		RT_PCI_INTERFACE
+	#endif
+
+	#if (defined(TESTCHIP_SUPPORT))
+		#define	PHYDM_TESTCHIP_SUPPORT 1
+	#else
+		#define	PHYDM_TESTCHIP_SUPPORT 0
+	#endif
+
+	#define	sta_info stat_info
+	#define	boolean	bool
+
+	#define	phydm_timer_list	timer_list
+
+#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) && defined(DM_ODM_CE_MAC80211)
+
+	#include <asm/byteorder.h>
+
+	#define DEV_BUS_TYPE	RT_PCI_INTERFACE
+
+	#if defined(__LITTLE_ENDIAN)
+		#define	ODM_ENDIAN_TYPE			ODM_ENDIAN_LITTLE
+	#elif defined(__BIG_ENDIAN)
+		#define	ODM_ENDIAN_TYPE			ODM_ENDIAN_BIG
+	#else
+		#error
+	#endif
+
+	/* define useless flag to avoid compile warning */
+	#define	USE_WORKITEM 0
+	#define	FOR_BRAZIL_PRETEST 0
+	#define	FPGA_TWO_MAC_VERIFICATION	0
+	#define	RTL8881A_SUPPORT	0
+	#define	PHYDM_TESTCHIP_SUPPORT 0
+
+
+	#define RATE_ADAPTIVE_SUPPORT			0
+	#define POWER_TRAINING_ACTIVE			0
+
+	#define sta_info	rtl_sta_info
+	#define	boolean		bool
+
+	#define	phydm_timer_list	timer_list
+
+#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
+	#include <drv_types.h>
+
+	#ifdef CONFIG_USB_HCI
+		#define DEV_BUS_TYPE	RT_USB_INTERFACE
+	#elif defined(CONFIG_PCI_HCI)
+		#define DEV_BUS_TYPE	RT_PCI_INTERFACE
+	#elif defined(CONFIG_SDIO_HCI)
+		#define DEV_BUS_TYPE	RT_SDIO_INTERFACE
+	#elif defined(CONFIG_GSPI_HCI)
+		#define DEV_BUS_TYPE	RT_SDIO_INTERFACE
+	#endif
+
+
+	#if defined(CONFIG_LITTLE_ENDIAN)
+		#define	ODM_ENDIAN_TYPE			ODM_ENDIAN_LITTLE
+	#elif defined(CONFIG_BIG_ENDIAN)
+		#define	ODM_ENDIAN_TYPE			ODM_ENDIAN_BIG
+	#endif
+
+	#define	boolean	bool
+
+	#define SET_TX_DESC_ANTSEL_A_88E(__ptx_desc, __value) SET_BITS_TO_LE_4BYTE(__ptx_desc + 8, 24, 1, __value)
+	#define SET_TX_DESC_ANTSEL_B_88E(__ptx_desc, __value) SET_BITS_TO_LE_4BYTE(__ptx_desc + 8, 25, 1, __value)
+	#define SET_TX_DESC_ANTSEL_C_88E(__ptx_desc, __value) SET_BITS_TO_LE_4BYTE(__ptx_desc + 28, 29, 1, __value)
+
+	/* define useless flag to avoid compile warning */
+	#define	USE_WORKITEM 0
+	#define	FOR_BRAZIL_PRETEST 0
+	#define	FPGA_TWO_MAC_VERIFICATION	0
+	#define	RTL8881A_SUPPORT	0
+
+	#if (defined(TESTCHIP_SUPPORT))
+		#define	PHYDM_TESTCHIP_SUPPORT 1
+	#else
+		#define	PHYDM_TESTCHIP_SUPPORT 0
+	#endif
+
+	#define	phydm_timer_list	rtw_timer_list
+
+#elif (DM_ODM_SUPPORT_TYPE == ODM_IOT)
+	#define	boolean	bool
+	#define true	_TRUE
+	#define false	_FALSE
+
+	// for power limit table
+	enum odm_pw_lmt_regulation_type {
+		PW_LMT_REGU_NULL = 0,
+		PW_LMT_REGU_FCC = 1,
+		PW_LMT_REGU_ETSI = 2,
+		PW_LMT_REGU_MKK = 3,
+		PW_LMT_REGU_WW13 = 4
+	};
+
+	enum odm_pw_lmt_band_type {
+		PW_LMT_BAND_NULL = 0,
+		PW_LMT_BAND_2_4G = 1,
+		PW_LMT_BAND_5G = 2
+	};
+
+	enum odm_pw_lmt_bandwidth_type {
+		PW_LMT_BW_NULL = 0,
+		PW_LMT_BW_20M = 1,
+		PW_LMT_BW_40M = 2,
+		PW_LMT_BW_80M = 3
+	};
+
+	enum odm_pw_lmt_ratesection_type {
+		PW_LMT_RS_NULL = 0,
+		PW_LMT_RS_CCK = 1,
+		PW_LMT_RS_OFDM = 2,
+		PW_LMT_RS_HT = 3,
+		PW_LMT_RS_VHT = 4
+	};
+
+	enum odm_pw_lmt_rfpath_type {
+		PW_LMT_PH_NULL = 0,
+		PW_LMT_PH_1T = 1,
+		PW_LMT_PH_2T = 2,
+		PW_LMT_PH_3T = 3,
+		PW_LMT_PH_4T = 4
+	};
+
+	#define	phydm_timer_list	timer_list
+
+#endif
+
+#define READ_NEXT_PAIR(v1, v2, i) do { if (i + 2 >= array_len) break; i += 2; v1 = array[i]; v2 = array[i + 1]; } while (0)
+#define COND_ELSE  2
+#define COND_ENDIF 3
+
+#define	MASKBYTE0		0xff
+#define	MASKBYTE1		0xff00
+#define	MASKBYTE2		0xff0000
+#define	MASKBYTE3		0xff000000
+#define	MASKHWORD		0xffff0000
+#define	MASKLWORD		0x0000ffff
+#define	MASKDWORD		0xffffffff
+
+#define	MASK7BITS		0x7f
+#define	MASK12BITS		0xfff
+#define	MASKH4BITS		0xf0000000
+#define	MASK20BITS		0xfffff
+#define	MASK24BITS		0xffffff
+#define	MASKOFDM_D		0xffc00000
+#define	MASKCCK			0x3f3f3f3f
+
+#define RFREGOFFSETMASK		0xfffff
+#define RFREG_MASK		0xfffff
+
+#define MASKH3BYTES		0xffffff00
+#define MASKL3BYTES		0x00ffffff
+#define MASKBYTE2HIGHNIBBLE	0x00f00000
+#define MASKBYTE3LOWNIBBLE	0x0f000000
+#define	MASKL3BYTES		0x00ffffff
+
+#endif /* __ODM_TYPES_H__ */
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/rtchnlplan.c linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/rtchnlplan.c
--- linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/rtchnlplan.c	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/rtchnlplan.c	2020-04-10 16:35:06.827660581 +0300
@@ -0,0 +1,475 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
+ *
+ *
+ ******************************************************************************/
+
+/******************************************************************************
+
+ History:
+	data		Who		Remark (Internal History)
+
+	05/14/2012	MH		Collect RTK inernal infromation and generate channel plan draft.
+
+******************************************************************************/
+
+/* ************************************************************
+ * include files
+ * ************************************************************ */
+#include "mp_precomp.h"
+#include "phydm_precomp.h"
+#include "rtchnlplan.h"
+
+
+
+/*
+ *	channel Plan Domain Code
+ *   */
+
+/*
+	channel Plan Contents
+	Domain Code		EEPROM	Countries in Specific Domain
+			2G RD		5G RD		Bit[6:0]	2G	5G
+	Case	Old Define				00h~1Fh	Old Define	Old Define
+	1		2G_WORLD	5G_NULL		20h		Worldwird 13	NA
+	2		2G_ETSI1	5G_NULL		21h		Europe 2G		NA
+	3		2G_FCC1		5G_NULL		22h		US 2G			NA
+	4		2G_MKK1		5G_NULL		23h		Japan 2G		NA
+	5		2G_ETSI2	5G_NULL		24h		France 2G		NA
+	6		2G_FCC1		5G_FCC1		25h		US 2G			US 5G					�K�j��{��
+	7		2G_WORLD	5G_ETSI1	26h		Worldwird 13	Europe					�K�j��{��
+	8		2G_MKK1		5G_MKK1		27h		Japan 2G		Japan 5G				�K�j��{��
+	9		2G_WORLD	5G_KCC1		28h		Worldwird 13	Korea					�K�j��{��
+	10		2G_WORLD	5G_FCC2		29h		Worldwird 13	US o/w DFS Channels
+	11		2G_WORLD	5G_FCC3		30h		Worldwird 13	India, Mexico
+	12		2G_WORLD	5G_FCC4		31h		Worldwird 13	Venezuela
+	13		2G_WORLD	5G_FCC5		32h		Worldwird 13	China
+	14		2G_WORLD	5G_FCC6		33h		Worldwird 13	Israel
+	15		2G_FCC1		5G_FCC7		34h		US 2G			US/Canada				�K�j��{��
+	16		2G_WORLD	5G_ETSI2	35h		Worldwird 13	Australia, New Zealand	�K�j��{��
+	17		2G_WORLD	5G_ETSI3	36h		Worldwird 13	Russia
+	18		2G_MKK1		5G_MKK2		37h		Japan 2G		Japan (W52, W53)
+	19		2G_MKK1		5G_MKK3		38h		Japan 2G		Japan (W56)
+	20		2G_FCC1		5G_NCC1		39h		US 2G			Taiwan					�K�j��{��
+
+	NA		2G_WORLD	5G_FCC1		7F		FCC	FCC DFS Channels	Realtek Define
+
+
+
+
+
+	2.4G	Regulatory	Domains
+	Case	2G RD		regulation	Channels	Frequencyes		Note					Countries in Specific Domain
+	1		2G_WORLD	ETSI		1~13		2412~2472		Passive scan CH 12, 13	Worldwird 13
+	2		2G_ETSI1	ETSI		1~13		2412~2472								Europe
+	3		2G_FCC1		FCC			1~11		2412~2462								US
+	4		2G_MKK1		MKK			1~13, 14	2412~2472, 2484							Japan
+	5		2G_ETSI2	ETSI		10~13		2457~2472								France
+
+
+
+
+	5G Regulatory Domains
+	Case	5G RD		regulation	Channels			Frequencyes					Note											Countries in Specific Domain
+	1		5G_NULL		NA			NA					NA							Do not support 5GHz
+	2		5G_ETSI1	ETSI		"36~48, 52~64,
+									100~140"			"5180~5240, 5260~5230
+														5500~5700"					Band1, Ban2, Band3								Europe
+	3		5G_ETSI2	ETSI		"36~48, 52~64,
+									100~140, 149~165"	"5180~5240, 5260~5230
+														5500~5700, 5745~5825"		Band1, Ban2, Band3, Band4						Australia, New Zealand
+	4		5G_ETSI3	ETSI		"36~48, 52~64,
+														100~132, 149~165"
+														"5180~5240, 5260~5230
+														5500~5660, 5745~5825"		Band1, Ban2, Band3(except CH 136, 140), Band4"	Russia
+	5		5G_FCC1		FCC			"36~48, 52~64,
+									100~140, 149~165"
+														"5180~5240, 5260~5230
+														5500~5700, 5745~5825"		Band1(5150~5250MHz),
+																					Band2(5250~5350MHz),
+																					Band3(5470~5725MHz),
+																					Band4(5725~5850MHz)"							US
+	6		5G_FCC2		FCC			36~48, 149~165		5180~5240, 5745~5825		Band1, Band4	FCC o/w DFS Channels
+	7		5G_FCC3		FCC			"36~48, 52~64,
+									149~165"			"5180~5240, 5260~5230
+														5745~5825"					Band1, Ban2, Band4								India, Mexico
+	8		5G_FCC4		FCC			"36~48, 52~64,
+									149~161"			"5180~5240, 5260~5230
+														5745~5805"					Band1, Ban2,
+																					Band4(except CH 165)"							Venezuela
+	9		5G_FCC5		FCC			149~165				5745~5825					Band4											China
+	10		5G_FCC6		FCC			36~48, 52~64		5180~5240, 5260~5230		Band1, Band2									Israel
+	11		5G_FCC7
+			5G_IC1		FCC
+						IC"			"36~48, 52~64,
+									100~116, 136, 140,
+									149~165"			"5180~5240, 5260~5230
+														5500~5580, 5680, 5700,
+														5745~5825"					"Band1, Band2,
+																					Band3(except 5600~5650MHz),
+																					Band4"											"US
+																																	Canada"
+	12		5G_KCC1		KCC			"36~48, 52~64,
+									100~124, 149~165"	"5180~5240, 5260~5230
+														5500~5620, 5745~5825"		"Band1, Ban2,
+																					Band3(5470~5650MHz),
+																					Band4"											Korea
+	13		5G_MKK1		MKK			"36~48, 52~64,
+									100~140"			"5180~5240, 5260~5230
+														5500~5700"					W52, W53, W56									Japan
+	14		5G_MKK2		MKK			36~48, 52~64		5180~5240, 5260~5230		W52, W53										Japan (W52, W53)
+	15		5G_MKK3		MKK			100~140				5500~5700					W56	Japan (W56)
+	16		5G_NCC1		NCC			"56~64,
+									100~116, 136, 140,
+									149~165"			"5260~5320
+														5500~5580, 5680, 5700,
+														5745~5825"					"Band2(except CH 52),
+																					Band3(except 5600~5650MHz),
+																					Band4"											Taiwan
+
+
+*/
+
+/*
+ * 2.4G CHannel
+ *
+ *
+
+	2.4G band		Regulatory Domains																RTL8192D
+	channel number	channel Frequency	US		Canada	Europe	Spain	France	Japan	Japan		20M		40M
+					(MHz)				(FCC)	(IC)	(ETSI)							(MPHPT)
+	1				2412				v		v		v								v			v
+	2				2417				v		v		v								v			v
+	3				2422				v		v		v								v			v		v
+	4				2427				v		v		v								v			v		v
+	5				2432				v		v		v								v			v		v
+	6				2437				v		v		v								v			v		v
+	7				2442				v		v		v								v			v		v
+	8				2447				v		v		v								v			v		v
+	9				2452				v		v		v								v			v		v
+	10				2457				v		v		v		v		v				v			v		v
+	11				2462				v		v		v		v		v				v			v		v
+	12				2467								v				v				v			v		v
+	13				2472								v				v				v			v
+	14				2484														v					v
+
+
+*/
+
+
+/*
+ * 5G Operating channel
+ *
+ *
+
+	5G band		RTL8192D	RTL8195 (Jaguar)				Jaguar 2	Regulatory Domains
+	channel number	channel Frequency	Global	Global				Global	"US
+(FCC 15.407)"	"Canada
+(FCC, except 5.6~5.65GHz)"	Argentina, Australia, New Zealand, Brazil, S. Africa (FCC/ETSI)	"Europe
+(CE 301 893)"	China	India, Mexico, Singapore	Israel, Turkey	"Japan
+(MIC Item 19-3, 19-3-2)"	Korea	Russia, Ukraine	"Taiwan
+(NCC)"	Venezuela
+		(MHz)	(20MHz)	(20MHz)	(40MHz)	(80MHz)	(160MHz)	(20MHz)	(20MHz)	(20MHz)	(20MHz)	(20MHz)	(20MHz)	(20MHz)	(20MHz)	(20MHz)	(20MHz)	(20MHz)	(20MHz)	(20MHz)
+"band 1
+5.15GHz
+~
+5.25GHz"	36	5180	v	v	v	v		v	Indoor	Indoor	v	Indoor		v	Indoor	Indoor	v	v		v
+	40	5200	v	v				v	Indoor	Indoor	v	Indoor		v	Indoor	Indoor	v	v		v
+	44	5220	v	v	v			v	Indoor	Indoor	v	Indoor		v	Indoor	Indoor	v	v		v
+	48	5240	v	v				v	Indoor	Indoor	v	Indoor		v	Indoor	Indoor	v	v		v
+"band 2
+5.25GHz
+~
+5.35GHz
+(DFS)"	52	5260	v	v	v	v		v	v	v	v	Indoor		v	Indoor	Indoor	v	v		v
+	56	5280	v	v				v	v	v	v	Indoor		v	Indoor	Indoor	v	v	Indoor	v
+	60	5300	v	v	v			v	v	v	v	Indoor		v	Indoor	Indoor	v	v	Indoor	v
+	64	5320	v	v				v	v	v	v	Indoor		v	Indoor	Indoor	v	v	Indoor	v
+
+"band 3
+5.47GHz
+~
+5.725GHz
+(DFS)"	100	5500	v	v	v	v		v	v	v	v	v				v	v	v	v
+	104	5520	v	v				v	v	v	v	v				v	v	v	v
+	108	5540	v	v	v			v	v	v	v	v				v	v	v	v
+	112	5560	v	v				v	v	v	v	v				v	v	v	v
+	116	5580	v	v	v	v		v	v	v	v	v				v	v	v	v
+	120	5600	v	v				v	Indoor		v	Indoor				v	v	v
+	124	5620	v	v	v			v	Indoor		v	Indoor				v	v	v
+	128	5640	v	v				v	Indoor		v	Indoor				v		v
+	132	5660	v	v	v	E		v	Indoor		v	Indoor				v		v
+	136	5680	v	v				v	v	v	v	v				v			v
+	140	5700	v	v	E			v	v	v	v	v				v			v
+	144	5720	E	E				E
+"band 4
+5.725GHz
+~
+5.85GHz
+(~5.9GHz)"	149	5745	v	v	v	v		v	v	v	v		v	v			v	v	v	v
+	153	5765	v	v				v	v	v	v		v	v			v	v	v	v
+	157	5785	v	v	v			v	v	v	v		v	v			v	v	v	v
+	161	5805	v	v				v	v	v	v		v	v			v	v	v	v
+	165	5825	v	v	P	P		v	v	v	v		v	v			v	v	v
+	169	5845	P	P				P
+	173	5865	P	P	P			P
+	177	5885	P	P				P
+channel count			28	28	14	7	0	28	24	20	24	19	5	13	8	19	20	22	15	12
+			E: FCC accepted the ask for CH144 from Accord.					PS: 160MHz �� 80MHz+80MHz��{�H			Argentina	Belgium (��Q��)		India	Israel			Russia
+			P: Customer's requirement from James.								Australia	The Netherlands (����)		Mexico	Turkey			Ukraine
+											New Zealand	UK (�^��)		Singapore
+											Brazil	Switzerland (��h)
+
+
+*/
+
+/*---------------------------Define Local Constant---------------------------*/
+
+
+/* define Maximum Power v.s each band for each region
+ * ISRAEL
+ * Format:
+ * RT_CHANNEL_DOMAIN_Region ={{{chnl_start, chnl_end, Pwr_dB_Max}, {Chn2_Start, Chn2_end, Pwr_dB_Max}, {Chn3_Start, Chn3_end, Pwr_dB_Max}, {Chn4_Start, Chn4_end, Pwr_dB_Max}, {Chn5_Start, Chn5_end, Pwr_dB_Max}}, Limit_Num}
+ * RT_CHANNEL_DOMAIN_FCC ={{{01,11,30}, {36,48,17}, {52,64,24}, {100,140,24}, {149,165,30}}, 5}
+ * "NR" is non-release channle.
+ * Issue--- Israel--Russia--New Zealand
+ * DOMAIN_01= (2G_WORLD, 5G_NULL)
+ * DOMAIN_02= (2G_ETSI1, 5G_NULL)
+ * DOMAIN_03= (2G_FCC1, 5G_NULL)
+ * DOMAIN_04= (2G_MKK1, 5G_NULL)
+ * DOMAIN_05= (2G_ETSI2, 5G_NULL)
+ * DOMAIN_06= (2G_FCC1, 5G_FCC1)
+ * DOMAIN_07= (2G_WORLD, 5G_ETSI1)
+ * DOMAIN_08= (2G_MKK1, 5G_MKK1)
+ * DOMAIN_09= (2G_WORLD, 5G_KCC1)
+ * DOMAIN_10= (2G_WORLD, 5G_FCC2)
+ * DOMAIN_11= (2G_WORLD, 5G_FCC3)----india
+ * DOMAIN_12= (2G_WORLD, 5G_FCC4)----Venezuela
+ * DOMAIN_13= (2G_WORLD, 5G_FCC5)----China
+ * DOMAIN_14= (2G_WORLD, 5G_FCC6)----Israel
+ * DOMAIN_15= (2G_FCC1, 5G_FCC7)-----Canada
+ * DOMAIN_16= (2G_WORLD, 5G_ETSI2)---Australia
+ * DOMAIN_17= (2G_WORLD, 5G_ETSI3)---Russia
+ * DOMAIN_18= (2G_MKK1, 5G_MKK2)-----Japan
+ * DOMAIN_19= (2G_MKK1, 5G_MKK3)-----Japan
+ * DOMAIN_20= (2G_FCC1, 5G_NCC1)-----Taiwan
+ * DOMAIN_21= (2G_FCC1, 5G_NCC1)-----Taiwan */
+
+
+static	struct _RT_CHANNEL_PLAN_MAXPWR	chnl_plan_pwr_max_2g[] = {
+
+	/* 2G_WORLD, */
+	{{1, 13, 20}, 1},
+
+	/* 2G_ETSI1 */
+	{{1, 13, 20}, 1},
+
+	/* RT_CHANNEL_DOMAIN_ETSI */
+	{{{1, 11, 17}, {40, 56, 17}, {60, 128, 17}, {0, 0, 0}, {149, 165, 17}}, 4},
+
+	/* RT_CHANNEL_DOMAIN_MKK */
+	{{{1, 11, 17}, {0, 0, 0}, {0, 0, 0}, {0, 0, 0}, {0, 0, 0}}, 1},
+
+	/* Add new channel plan mex power table. */
+	/* ...... */
+};
+
+
+#if 0
+/* ===========================================1:(2G_WORLD, 5G_NULL) */
+
+struct _RT_CHANNEL_PLAN_MAXPWR	RT_DOMAIN_01 = {{{01, 13, 20}, {NR, NR, 0}, {NR, NR, 0}, {NR, NR, 0}, {NR, NR, 0}}, 1}
+
+/* ===========================================2:(2G_ETSI1, 5G_NULL) */
+
+RT_DOMAIN_02 = {{{01, 13, 20}, {NR, NR, 0}, {NR, NR, 0}, {NR, NR, 0}, {NR, NR, 0}}, 1}
+
+/* ===========================================3:(2G_FCC1, 5G_NULL) */
+
+RT_DOMAIN_03 = {{{01, 11, 30}, {NR, NR, 0}, {NR, NR, 0}, {NR, NR, 0}, {NR, NR, 0}}, 1}
+
+/* ===========================================4:(2G_MKK1, 5G_NULL) */
+
+RT_DOMAIN_04 = {{{01, 14, 23}, {NR, NR, 0}, {NR, NR, 0}, {NR, NR, 0}, {NR, NR, 0}}, 1}
+
+/* ===========================================5:(2G_ETSI2, 5G_NULL) */
+
+RT_DOMAIN_05 = {{{10, 13, 20}, {NR, NR, 0}, {NR, NR, 0}, {NR, NR, 0}, {NR, NR, 0}}, 1}
+
+/* ===========================================6:(2G_FCC1, 5G_FCC1) */
+
+RT_DOMAIN_06 = {{{01, 13, 30}, {36, 48, 17}, {52, 64, 24}, {100, 140, 24}, {149, 165, 30}}, 5}
+
+/* ===========================================7:(2G_WORLD, 5G_ETSI1) */
+
+RT_DOMAIN_07 = {{{01, 13, 20}, {36, 48, 23}, {52, 64, 23}, {100, 140, 30}, {NR, NR, 0}}, 4}
+
+/* ===========================================8:(2G_MKK1, 5G_MKK1) */
+
+RT_DOMAIN_08 = {{{01, 14, 23}, {36, 48, 23}, {52, 64, 23}, {100, 140, 23}, {NR, NR, 0}}, 4}
+
+/* ===========================================9:(2G_WORLD, 5G_KCC1) */
+
+RT_DOMAIN_09 = {{{01, 13, 20}, {36, 48, 17}, {52, 64, 23}, {100, 124, 23}, {149, 165, 23}}, 5}
+
+/* ===========================================10:(2G_WORLD, 5G_FCC2) */
+
+RT_DOMAIN_10 = {{{01, 13, 20}, {36, 48, 17}, {NR, NR, 0}, {NR, NR, 0}, {149, 165, 30}}, 3}
+
+/* ===========================================11:(2G_WORLD, 5G_FCC3) */
+RT_DOMAIN_11 = {{{01, 13, 20}, {36, 48, 23}, {52, 64, 23}, {NR, NR, 0}, {149, 165, 23}}, 4}
+
+/* ===========================================12:(2G_WORLD, 5G_FCC4) */
+RT_DOMAIN_12 = {{{01, 13, 20}, {36, 48, 24}, {52, 64, 24}, {NR, NR, 0}, {149, 161, 27}}, 4}
+
+/* ===========================================13:(2G_WORLD, 5G_FCC5) */
+RT_DOMAIN_13 = {{{01, 13, 20}, {NR, NR, 0}, {NR, NR, 0}, {NR, NR, 0}, {149, 165, 27}}, 2}
+
+/* ===========================================14:(2G_WORLD, 5G_FCC6) */
+RT_DOMAIN_14 = {{{01, 13, 20}, {36, 48, 17}, {52, 64, 17}, {NR, NR, 0}, {NR, NR, 0}}, 3}
+
+/* ===========================================15:(2G_FCC1, 5G_FCC7) */
+RT_DOMAIN_15 = {{{01, 11, 30}, {36, 48, 23}, {52, 64, 24}, {100, 140, 24}, {149, 165, 30}}, 5}
+
+/* ===========================================16:(2G_WORLD, 5G_ETSI2) */
+RT_DOMAIN_16 = {{{01, 13, 20}, {36, 48, 23}, {52, 64, 23}, {100, 140, 30}, {149, 165, 30}}, 5}
+
+/* ===========================================17:(2G_WORLD, 5G_ETSI3) */
+RT_DOMAIN_17 = {{{01, 13, 20}, {36, 48, 23}, {52, 64, 23}, {100, 132, 30}, {149, 165, 20}}, 5}
+
+/* ===========================================18:(2G_MKK1, 5G_MKK2) */
+RT_DOMAIN_18 = {{{01, 14, 23}, {36, 48, 23}, {52, 64, 23}, {NR, NR, 0}, {NR, NR, 0}}, 3}
+
+/* ===========================================19:(2G_MKK1, 5G_MKK3) */
+RT_DOMAIN_19 = {{{01, 14, 23}, {NR, NR, 0}, {NR, NR, 0}, {100, 140, 23}, {NR, NR, 0}}, 2}
+
+/* ===========================================20:(2G_FCC1, 5G_NCC1) */
+RT_DOMAIN_20 = {{{01, 11, 30}, {NR, NR, 0}, {56, 64, 23}, {100, 140, 24}, {149, 165, 30}}, 4}
+
+/* ===========================================21:(2G_FCC1, 5G_NCC2) */
+RT_DOMAIN_21 = {{{01, 11, 30}, {NR, NR, 0}, {56, 64, 23}, {NR, NR, 0}, {149, 165, 30}}, 3}
+
+/* ===========================================22:(2G_WORLD, 5G_FCC3) */
+RT_DOMAIN_22 = {{{01, 13, 24}, {36, 48, 20}, {52, 64, 24}, {NR, NR, 0}, {149, 165, 30}}, 4}
+
+/* ===========================================23:(2G_WORLD, 5G_ETSI2) */
+RT_DOMAIN_23 = {{{01, 13, 20}, {36, 48, 23}, {52, 64, 23}, {100, 140, 30}, {149, 165, 30}}, 5}
+
+#endif
+
+/*
+ * counter & Realtek channel plan transfer table.
+ *   */
+struct _RT_CHANNEL_PLAN_COUNTRY_TRANSFER_TABLE	rt_ctry_chnl_tbl[] = {
+
+	{
+		RT_CTRY_AL,							/*	"Albania�����ڥ���" */
+		"AL",
+		RT_2G_WORLD,
+		RT_5G_WORLD,
+		RT_CHANNEL_DOMAIN_UNDEFINED			/* 2G/5G world. */
+	},
+#if 0
+	{
+		RT_CTRY_BB,							/* "Barbados�ڤڦh��" */
+		"BB",
+		RT_2G_WORLD,
+		RT_5G_NULL,
+		RT_CHANNEL_DOMAIN_EFUSE_0x20		/* 2G world. 5G_NULL */
+	},
+
+	{
+		RT_CTRY_DE,							/* "Germany�w��" */
+		"DE",
+		RT_2G_WORLD,
+		RT_5G_ETSI1,
+		RT_CHANNEL_DOMAIN_EFUSE_0x26
+	},
+
+	{
+		RT_CTRY_US,							/* "Germany�w��" */
+		"US",
+		RT_2G_FCC1,
+		RT_5G_FCC7,
+		RT_CHANNEL_DOMAIN_EFUSE_0x34
+	},
+
+	{
+		RT_CTRY_JP,							/* "Germany�w��" */
+		"JP",
+		RT_2G_MKK1,
+		RT_5G_MKK1,
+		RT_CHANNEL_DOMAIN_EFUSE_0x34
+	},
+
+	{
+		RT_CTRY_TW,							/* "Germany�w��" */
+		"TW",
+		RT_2G_FCC1,
+		RT_5G_NCC1,
+		RT_CHANNEL_DOMAIN_EFUSE_0x39
+	},
+#endif
+
+};	/* rt_ctry_chnl_tbl */
+
+/*
+ * Realtek Defined channel plan.
+ *   */
+#if 0
+
+static	struct _RT_CHANNEL_PLAN_NEW		rt_chnl_plan[] = {
+	/* channel Plan   0x20. */
+	{
+		&rt_ctry_chnl_tbl[1],					/* struct _RT_CHANNEL_PLAN_COUNTRY_TRANSFER_TABLE Country & channel plan transfer table. */
+		RT_CHANNEL_DOMAIN_EFUSE_0x20,		/* RT_CHANNEL_DOMAIN RT channel Plan Define */
+		RT_2G_WORLD,						/* enum rt_regulation_2g */
+		RT_5G_NULL,							/* enum rt_regulation_5g */
+		RT_WORLD,							/* enum rt_regulation_cmn RT Regulatory domain definition. */
+		RT_SREQ_NA,							/* RT channel plan special & customerize requirement. */
+
+		CHNL_RT_2G_WORLD,
+		CHNL_RT_2G_WORLD_SCAN_TYPE,
+		&chnl_plan_pwr_max_2g[0],
+
+		CHNL_RT_5G_NULL,
+		CHNL_RT_5G_NULL_SCAN_TYPE,
+
+
+	},
+
+	/* channel Plan   0x26. */
+	{
+		&rt_ctry_chnl_tbl[1],					/* struct _RT_CHANNEL_PLAN_COUNTRY_TRANSFER_TABLE Country & channel plan transfer table. */
+		RT_CHANNEL_DOMAIN_EFUSE_0x26,		/* RT_CHANNEL_DOMAIN RT channel Plan Define */
+		RT_2G_WORLD,						/* enum rt_regulation_2g */
+		RT_5G_ETSI1,						/* enum rt_regulation_5g */
+		RT_WORLD,							/* enum rt_regulation_cmn RT Regulatory domain definition. */
+		RT_SREQ_NA,							/* RT channel plan special & customerize requirement. */
+
+		CHNL_RT_2G_WORLD,					/* 2G workd cannel */
+		CHNL_RT_2G_WORLD_SCAN_TYPE,
+		&chnl_plan_pwr_max_2g[1],
+
+		CHNL_RT_5G_ETSI1,
+		CHNL_RT_5G_ETSI1_SCAN_TYPE,
+
+	}
+
+
+};
+#endif
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/rtchnlplan.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/rtchnlplan.h
--- linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/rtchnlplan.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/rtchnlplan.h	2020-04-10 16:35:06.827660581 +0300
@@ -0,0 +1,682 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
+ *
+ *
+ ******************************************************************************/
+
+
+#ifndef	__RT_CHANNELPLAN_H__
+#define __RT_CHANNELPLAN_H__
+
+enum rt_channel_domain_new {
+
+	/* ===== Add new channel plan above this line =============== */
+
+	/* For new architecture we define different 2G/5G CH area for all country. */
+	/* 2.4 G only */
+	RT_CHANNEL_DOMAIN_2G_WORLD_5G_NULL				= 0x20,
+	RT_CHANNEL_DOMAIN_2G_ETSI1_5G_NULL				= 0x21,
+	RT_CHANNEL_DOMAIN_2G_FCC1_5G_NULL				= 0x22,
+	RT_CHANNEL_DOMAIN_2G_MKK1_5G_NULL				= 0x23,
+	RT_CHANNEL_DOMAIN_2G_ETSI2_5G_NULL				= 0x24,
+	/* 2.4 G + 5G type 1 */
+	RT_CHANNEL_DOMAIN_2G_FCC1_5G_FCC1				= 0x25,
+	RT_CHANNEL_DOMAIN_2G_WORLD_5G_ETSI1				= 0x26,
+	/* RT_CHANNEL_DOMAIN_2G_WORLD_5G_ETSI1				= 0x27, */
+	/* ..... */
+
+	RT_CHANNEL_DOMAIN_MAX_NEW,
+
+};
+
+
+#if 0
+#define DOMAIN_CODE_2G_WORLD \
+	{1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13}, 13
+#define DOMAIN_CODE_2G_ETSI1 \
+	{1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13}, 13
+#define DOMAIN_CODE_2G_ETSI2 \
+	{1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11}, 11
+#define DOMAIN_CODE_2G_FCC1 \
+	{1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14}, 14
+#define DOMAIN_CODE_2G_MKK1 \
+	{10, 11, 12, 13}, 4
+
+#define DOMAIN_CODE_5G_ETSI1 \
+	{36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140}, 19
+#define DOMAIN_CODE_5G_ETSI2 \
+	{36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 149, 153, 157, 161, 165}, 24
+#define DOMAIN_CODE_5G_ETSI3 \
+	{36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 128, 132, 149, 153, 157, 161, 165}, 22
+#define DOMAIN_CODE_5G_FCC1 \
+	{36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 149, 153, 157, 161, 165}, 24
+#define DOMAIN_CODE_5G_FCC2 \
+	{36, 40, 44, 48, 149, 153, 157, 161, 165}, 9
+#define DOMAIN_CODE_5G_FCC3 \
+	{36, 40, 44, 48, 52, 56, 60, 64, 149, 153, 157, 161, 165}, 13
+#define DOMAIN_CODE_5G_FCC4 \
+	{36, 40, 44, 48, 52, 56, 60, 64, 149, 153, 157, 161}, 12
+#define DOMAIN_CODE_5G_FCC5 \
+	{149, 153, 157, 161, 165}, 5
+#define DOMAIN_CODE_5G_FCC6 \
+	{36, 40, 44, 48, 52, 56, 60, 64}, 8
+#define DOMAIN_CODE_5G_FCC7 \
+	{36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 136, 140, 149, 153, 157, 161, 165}, 20
+#define DOMAIN_CODE_5G_IC1 \
+	{36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 136, 140, 149, 153, 157, 161, 165}, 20
+#define DOMAIN_CODE_5G_KCC1 \
+	{36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 149, 153, 157, 161, 165}, 20
+#define DOMAIN_CODE_5G_MKK1 \
+	{36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140}, 19
+#define DOMAIN_CODE_5G_MKK2 \
+	{36, 40, 44, 48, 52, 56, 60, 64}, 8
+#define DOMAIN_CODE_5G_MKK3 \
+	{100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140}, 11
+#define DOMAIN_CODE_5G_NCC1 \
+	{56, 60, 64, 100, 104, 108, 112, 116, 136, 140, 149, 153, 157, 161, 165}, 24
+#define DOMAIN_CODE_5G_NCC2 \
+	{56, 60, 64, 149, 153, 157, 161, 165}, 8
+#define UNDEFINED \
+	{0}, 0
+#endif
+
+/*
+ *
+ *
+ *
+
+Countries							"Country Abbreviation"	Domain Code					SKU's	Ch# of 20MHz
+															2G			5G						Ch# of 40MHz
+"Albania�����ڥ���"					AL													Local Test
+
+"Algeria�����ΧQ��"					DZ									CE TCF
+
+"Antigua & Barbuda�w���ʮq&�ڥ��F"	AG						2G_WORLD					FCC TCF
+
+"Argentina���ڧ�"					AR						2G_WORLD					Local Test
+
+"Armenia�Ȭ�����"					AM						2G_WORLD					ETSI
+
+"Aruba���|�ڮq"						AW						2G_WORLD					FCC TCF
+
+"Australia�D�w"						AU						2G_WORLD		5G_ETSI2
+
+"Austria���a�Q"						AT						2G_WORLD		5G_ETSI1	CE
+
+"Azerbaijan�������"				AZ						2G_WORLD					CE TCF
+
+"Bahamas�ګ���"						BS						2G_WORLD
+
+"Barbados�ڤڦh��"					BB						2G_WORLD					FCC TCF
+
+"Belgium��Q��"						BE						2G_WORLD		5G_ETSI1	CE
+
+"Bermuda�ʼ}�F"						BM						2G_WORLD					FCC TCF
+
+"Brazil�ڦ�"						BR						2G_WORLD					Local Test
+
+"Bulgaria�O�[�Q��"					BG						2G_WORLD		5G_ETSI1	CE
+
+"Canada�[���j"						CA						2G_FCC1			5G_FCC7		IC / FCC	IC / FCC
+
+"Cayman Islands�}�Ҹs�q"			KY						2G_WORLD		5G_ETSI1	CE
+
+"Chile���Q"							CL						2G_WORLD					FCC TCF
+
+"China����"							CN						2G_WORLD		5G_FCC5		�H��?�i2002�j353?
+
+"Columbia���ۤ��"					CO						2G_WORLD					Voluntary
+
+"Costa Rica�����F���["				CR						2G_WORLD					FCC TCF
+
+"Cyprus�������"					CY						2G_WORLD		5G_ETSI1	CE
+
+"Czech ���J"						CZ						2G_WORLD		5G_ETSI1	CE
+
+"Denmark����"						DK						2G_WORLD		5G_ETSI1	CE
+
+"Dominican Republic�h�����[�@�M��"	DO						2G_WORLD					FCC TCF
+
+"Egypt�J��"	EG	2G_WORLD			CE T												CF
+
+"El Salvador�ĺ��˦h"				SV						2G_WORLD					Voluntary
+
+"Estonia�R�F����"					EE						2G_WORLD		5G_ETSI1	CE
+
+"Finland����"						FI						2G_WORLD		5G_ETSI1	CE
+
+"France�k��"						FR										5G_E		TSI1	CE
+
+"Germany�w��"						DE						2G_WORLD		5G_ETSI1	CE
+
+"Greece ��þ"						GR						2G_WORLD		5G_ETSI1	CE
+
+"Guam���q"							GU						2G_WORLD
+
+"Guatemala�ʦa����"					GT						2G_WORLD
+
+"Haiti���a"							HT						2G_WORLD					FCC TCF
+
+"Honduras�����Դ�"					HN						2G_WORLD					FCC TCF
+
+"Hungary�I���Q"						HU						2G_WORLD		5G_ETSI1	CE
+
+"Iceland�B�q"						IS						2G_WORLD		5G_ETSI1	CE
+
+"India�L��"												2G_WORLD		5G_FCC3		FCC/CE TCF
+
+"Ireland�R����"						IE						2G_WORLD		5G_ETSI1	CE
+
+"Israel�H��C"						IL										5G_F		CC6	CE TCF
+
+"Italy�q�j�Q"						IT						2G_WORLD		5G_ETSI1	CE
+
+"Japan�饻"							JP						2G_MKK1			5G_MKK1		MKK	MKK
+
+"Korea����"							KR						2G_WORLD		5G_KCC1		KCC	KCC
+
+"Latvia�Բ����"					LV						2G_WORLD		5G_ETSI1	CE
+
+"Lithuania�߳��{"					LT						2G_WORLD		5G_ETSI1	CE
+
+"Luxembourg�c�˳�"					LU						2G_WORLD		5G_ETSI1	CE
+
+"Malaysia���Ӧ��"					MY						2G_WORLD					Local Test
+
+"Malta�����L"						MT						2G_WORLD		5G_ETSI1	CE
+
+"Mexico�����"						MX						2G_WORLD		5G_FCC3		Local Test
+
+"Morocco������"						MA													CE TCF
+
+"Netherlands����"					NL						2G_WORLD		5G_ETSI1	CE
+
+"New Zealand�æ���"					NZ						2G_WORLD		5G_ETSI2
+
+"Norway����"						NO						2G_WORLD		5G_ETSI1	CE
+
+"Panama�ڮ��� "						PA						2G_FCC1						Voluntary
+
+"Philippines��߻�"					PH						2G_WORLD					FCC TCF
+
+"Poland�i��"						PL						2G_WORLD		5G_ETSI1	CE
+
+"Portugal�����"					PT						2G_WORLD		5G_ETSI1	CE
+
+"Romaniaù������"					RO						2G_WORLD		5G_ETSI1	CE
+
+"Russia�Xù��"						RU						2G_WORLD		5G_ETSI3	CE TCF
+
+"Saudi Arabia�F�a���ԧB"			SA						2G_WORLD					CE TCF
+
+"Singapore�s�[�Y"					SG						2G_WORLD
+
+"Slovakia������J"					SK						2G_WORLD		5G_ETSI1	CE
+
+"Slovenia����������"				SI						2G_WORLD		5G_ETSI1	CE
+
+"South Africa�n�D"					ZA						2G_WORLD					CE TCF
+
+"Spain��Z��"						ES										5G_ETSI1	CE
+
+"Sweden���"						SE						2G_WORLD		5G_ETSI1	CE
+
+"Switzerland��h"					CH						2G_WORLD		5G_ETSI1	CE
+
+"Taiwan�O�W"						TW						2G_FCC1			5G_NCC1	NCC
+
+"Thailand����"						TH						2G_WORLD					FCC/CE TCF
+
+"Turkey�g�ը�"						TR						2G_WORLD
+
+"Ukraine�Q�J��"						UA						2G_WORLD					Local Test
+
+"United Kingdom�^��"				GB						2G_WORLD		5G_ETSI1	CE	ETSI
+
+"United States����"					US						2G_FCC1			5G_FCC7		FCC	FCC
+
+"Venezuela�e�����"					VE						2G_WORLD		5G_FCC4		FCC TCF
+
+"Vietnam�V�n"						VN						2G_WORLD					FCC/CE TCF
+
+
+
+*/
+
+/* counter abbervation. */
+enum rt_country_name {
+	RT_CTRY_AL,				/*	"Albania�����ڥ���" */
+	RT_CTRY_DZ,             /* "Algeria�����ΧQ��" */
+	RT_CTRY_AG,             /* "Antigua & Barbuda�w���ʮq&�ڥ��F" */
+	RT_CTRY_AR,             /* "Argentina���ڧ�" */
+	RT_CTRY_AM,             /* "Armenia�Ȭ�����" */
+	RT_CTRY_AW,             /* "Aruba���|�ڮq" */
+	RT_CTRY_AU,             /* "Australia�D�w" */
+	RT_CTRY_AT,             /* "Austria���a�Q" */
+	RT_CTRY_AZ,             /* "Azerbaijan�������" */
+	RT_CTRY_BS,             /* "Bahamas�ګ���" */
+	RT_CTRY_BB,             /* "Barbados�ڤڦh��" */
+	RT_CTRY_BE,             /* "Belgium��Q��" */
+	RT_CTRY_BM,             /* "Bermuda�ʼ}�F" */
+	RT_CTRY_BR,             /* "Brazil�ڦ�" */
+	RT_CTRY_BG,             /* "Bulgaria�O�[�Q��" */
+	RT_CTRY_CA,             /* "Canada�[���j" */
+	RT_CTRY_KY,             /* "Cayman Islands�}�Ҹs�q" */
+	RT_CTRY_CL,             /* "Chile���Q" */
+	RT_CTRY_CN,             /* "China����" */
+	RT_CTRY_CO,             /* "Columbia���ۤ��" */
+	RT_CTRY_CR,             /* "Costa Rica�����F���[" */
+	RT_CTRY_CY,             /* "Cyprus�������" */
+	RT_CTRY_CZ,             /* "Czech ���J" */
+	RT_CTRY_DK,             /* "Denmark����" */
+	RT_CTRY_DO,             /* "Dominican Republic�h�����[�@�M��" */
+	RT_CTRY_CE,             /* "Egypt�J��"	EG	2G_WORLD */
+	RT_CTRY_SV,             /* "El Salvador�ĺ��˦h" */
+	RT_CTRY_EE,             /* "Estonia�R�F����" */
+	RT_CTRY_FI,             /* "Finland����" */
+	RT_CTRY_FR,             /* "France�k��" */
+	RT_CTRY_DE,             /* "Germany�w��" */
+	RT_CTRY_GR,             /* "Greece ��þ" */
+	RT_CTRY_GU,             /* "Guam���q" */
+	RT_CTRY_GT,             /* "Guatemala�ʦa����" */
+	RT_CTRY_HT,             /* "Haiti���a" */
+	RT_CTRY_HN,             /* "Honduras�����Դ�" */
+	RT_CTRY_HU,             /* "Hungary�I���Q" */
+	RT_CTRY_IS,             /* "Iceland�B�q" */
+	RT_CTRY_IN,             /* "India�L��" */
+	RT_CTRY_IE,             /* "Ireland�R����" */
+	RT_CTRY_IL,             /* "Israel�H��C" */
+	RT_CTRY_IT,             /* "Italy�q�j�Q" */
+	RT_CTRY_JP,             /* "Japan�饻" */
+	RT_CTRY_KR,             /* "Korea����" */
+	RT_CTRY_LV,             /* "Latvia�Բ����" */
+	RT_CTRY_LT,             /* "Lithuania�߳��{" */
+	RT_CTRY_LU,             /* "Luxembourg�c�˳�" */
+	RT_CTRY_MY,             /* "Malaysia���Ӧ��" */
+	RT_CTRY_MT,             /* "Malta�����L" */
+	RT_CTRY_MX,             /* "Mexico�����" */
+	RT_CTRY_MA,             /* "Morocco������" */
+	RT_CTRY_NL,             /* "Netherlands����" */
+	RT_CTRY_NZ,             /* "New Zealand�æ���" */
+	RT_CTRY_NO,             /* "Norway����" */
+	RT_CTRY_PA,             /* "Panama�ڮ��� " */
+	RT_CTRY_PH,             /* "Philippines��߻�" */
+	RT_CTRY_PL,             /* "Poland�i��" */
+	RT_CTRY_PT,             /* "Portugal�����" */
+	RT_CTRY_RO,             /* "Romaniaù������" */
+	RT_CTRY_RU,             /* "Russia�Xù��" */
+	RT_CTRY_SA,             /* "Saudi Arabia�F�a���ԧB" */
+	RT_CTRY_SG,             /* "Singapore�s�[�Y" */
+	RT_CTRY_SK,             /* "Slovakia������J" */
+	RT_CTRY_SI,             /* "Slovenia����������" */
+	RT_CTRY_ZA,             /* "South Africa�n�D" */
+	RT_CTRY_ES,             /* "Spain��Z��" */
+	RT_CTRY_SE,             /* "Sweden���" */
+	RT_CTRY_CH,             /* "Switzerland��h" */
+	RT_CTRY_TW,             /* "Taiwan�O�W" */
+	RT_CTRY_TH,             /* "Thailand����" */
+	RT_CTRY_TR,             /* "Turkey�g�ը�" */
+	RT_CTRY_UA,             /* "Ukraine�Q�J��" */
+	RT_CTRY_GB,             /* "United Kingdom�^��" */
+	RT_CTRY_US,             /* "United States����" */
+	RT_CTRY_VE,             /* "Venezuela�e�����" */
+	RT_CTRY_VN,             /* "Vietnam�V�n" */
+	RT_CTRY_MAX,
+
+};
+
+/* Scan type including active and passive scan. */
+enum rt_scan_type_new {
+	SCAN_NULL,
+	SCAN_ACT,
+	SCAN_PAS,
+	SCAN_BOTH,
+};
+
+
+/* Power table sample. */
+
+struct _RT_CHNL_PLAN_LIMIT {
+	u16	chnl_start;
+	u16	chnl_end;
+
+	u16	freq_start;
+	u16	freq_end;
+};
+
+
+/*
+ * 2.4G Regulatory Domains
+ *   */
+enum rt_regulation_2g {
+	RT_2G_NULL,
+	RT_2G_WORLD,
+	RT_2G_ETSI1,
+	RT_2G_FCC1,
+	RT_2G_MKK1,
+	RT_2G_ETSI2
+
+};
+
+
+/* typedef struct _RT_CHANNEL_BEHAVIOR
+ * {
+ *	u8	chnl;
+ *	enum rt_scan_type_new
+ *
+ * }RT_CHANNEL_BEHAVIOR, *PRT_CHANNEL_BEHAVIOR; */
+
+/* typedef struct _RT_CHANNEL_PLAN_TYPE
+ * {
+ *	RT_CHANNEL_BEHAVIOR
+ *	u8					Chnl_num;
+ * }RT_CHNL_PLAN_TYPE, *PRT_CHNL_PLAN_TYPE; */
+
+/*
+ * 2.4G channel number
+ * channel definition & number
+ *   */
+#define CHNL_RT_2G_NULL \
+	{0}, 0
+#define CHNL_RT_2G_WORLD \
+	{1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13}, 13
+#define CHNL_RT_2G_WORLD_TEST \
+	{1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13}, 13
+
+#define CHNL_RT_2G_EFSI1 \
+	{1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13}, 13
+#define CHNL_RT_2G_FCC1 \
+	{1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11}, 11
+#define CHNL_RT_2G_MKK1 \
+	{1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14}, 14
+#define CHNL_RT_2G_ETSI2 \
+	{10, 11, 12, 13}, 4
+
+/*
+ * 2.4G channel active or passive scan.
+ *   */
+#define CHNL_RT_2G_NULL_SCAN_TYPE \
+	{SCAN_NULL}
+#define CHNL_RT_2G_WORLD_SCAN_TYPE \
+	{1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0}
+#define CHNL_RT_2G_EFSI1_SCAN_TYPE \
+	{1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1}
+#define CHNL_RT_2G_FCC1_SCAN_TYPE \
+	{1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1}
+#define CHNL_RT_2G_MKK1_SCAN_TYPE \
+	{1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1}
+#define CHNL_RT_2G_ETSI2_SCAN_TYPE \
+	{1, 1, 1, 1}
+
+
+/*
+ * 2.4G band & Frequency Section
+ * Freqency start & end / band number
+ *   */
+#define FREQ_RT_2G_NULL \
+	{0}, 0
+/* Passive scan CH 12, 13 */
+#define FREQ_RT_2G_WORLD \
+	{2412, 2472}, 1
+#define FREQ_RT_2G_EFSI1 \
+	{2412, 2472}, 1
+#define FREQ_RT_2G_FCC1 \
+	{2412, 2462}, 1
+#define FREQ_RT_2G_MKK1 \
+	{2412, 2484}, 1
+#define FREQ_RT_2G_ETSI2 \
+	{2457, 2472}, 1
+
+
+/*
+ * 5G Regulatory Domains
+ *   */
+enum rt_regulation_5g {
+	RT_5G_NULL,
+	RT_5G_WORLD,
+	RT_5G_ETSI1,
+	RT_5G_ETSI2,
+	RT_5G_ETSI3,
+	RT_5G_FCC1,
+	RT_5G_FCC2,
+	RT_5G_FCC3,
+	RT_5G_FCC4,
+	RT_5G_FCC5,
+	RT_5G_FCC6,
+	RT_5G_FCC7,
+	RT_5G_IC1,
+	RT_5G_KCC1,
+	RT_5G_MKK1,
+	RT_5G_MKK2,
+	RT_5G_MKK3,
+	RT_5G_NCC1,
+
+};
+
+/*
+ * 5G channel number
+ *   */
+#define CHNL_RT_5G_NULL \
+	{0}, 0
+#define CHNL_RT_5G_WORLD \
+	{36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140}, 19
+#define CHNL_RT_5G_ETSI1 \
+	{36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 149, 153, 157, 161, 165}, 24
+#define CHNL_RT_5G_ETSI2 \
+	{36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 128, 132, 149, 153, 157, 161, 165}, 22
+#define CHNL_RT_5G_ETSI3 \
+	{36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 149, 153, 157, 161, 165}, 24
+#define CHNL_RT_5G_FCC1 \
+	{36, 40, 44, 48, 149, 153, 157, 161, 165}, 9
+#define CHNL_RT_5G_FCC2 \
+	{36, 40, 44, 48, 52, 56, 60, 64, 149, 153, 157, 161, 165}, 13
+#define CHNL_RT_5G_FCC3 \
+	{36, 40, 44, 48, 52, 56, 60, 64, 149, 153, 157, 161}, 12
+#define CHNL_RT_5G_FCC4 \
+	{149, 153, 157, 161, 165}, 5
+#define CHNL_RT_5G_FCC5 \
+	{36, 40, 44, 48, 52, 56, 60, 64}, 8
+#define CHNL_RT_5G_FCC6 \
+	{36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 136, 140, 149, 153, 157, 161, 165}, 20
+#define CHNL_RT_5G_FCC7 \
+	{36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 136, 140, 149, 153, 157, 161, 165}, 20
+#define CHNL_RT_5G_IC1 \
+	{36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 149, 153, 157, 161, 165}, 20
+#define CHNL_RT_5G_KCC1 \
+	{36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140}, 19
+#define CHNL_RT_5G_MKK1 \
+	{36, 40, 44, 48, 52, 56, 60, 64}, 8
+#define CHNL_RT_5G_MKK2 \
+	{100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140}, 11
+#define CHNL_RT_5G_MKK3 \
+	{56, 60, 64, 100, 104, 108, 112, 116, 136, 140, 149, 153, 157, 161, 165}, 24
+#define CHNL_RT_5G_NCC1 \
+	{56, 60, 64, 149, 153, 157, 161, 165}, 8
+
+/*
+ * 5G channel active or passive scan.
+ *   */
+#define CHNL_RT_5G_NULL_SCAN_TYPE \
+	{SCAN_NULL}
+#define CHNL_RT_5G_WORLD_SCAN_TYPE \
+	{1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1}
+#define CHNL_RT_5G_ETSI1_SCAN_TYPE \
+	{1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1}
+#define CHNL_RT_5G_ETSI2_SCAN_TYPE \
+	{36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 128, 132, 149, 153, 157, 161, 165}, 22
+#define CHNL_RT_5G_ETSI3_SCAN_TYPE \
+	{36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 149, 153, 157, 161, 165}, 24
+#define CHNL_RT_5G_FCC1_SCAN_TYPE \
+	{36, 40, 44, 48, 149, 153, 157, 161, 165}, 9
+#define CHNL_RT_5G_FCC2_SCAN_TYPE \
+	{36, 40, 44, 48, 52, 56, 60, 64, 149, 153, 157, 161, 165}, 13
+#define CHNL_RT_5G_FCC3_SCAN_TYPE \
+	{36, 40, 44, 48, 52, 56, 60, 64, 149, 153, 157, 161}, 12
+#define CHNL_RT_5G_FCC4_SCAN_TYPE \
+	{149, 153, 157, 161, 165}, 5
+#define CHNL_RT_5G_FCC5_SCAN_TYPE \
+	{36, 40, 44, 48, 52, 56, 60, 64}, 8
+#define CHNL_RT_5G_FCC6_SCAN_TYPE \
+	{36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 136, 140, 149, 153, 157, 161, 165}, 20
+#define CHNL_RT_5G_FCC7_SCAN_TYPE \
+	{36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 136, 140, 149, 153, 157, 161, 165}, 20
+#define CHNL_RT_5G_IC1_SCAN_TYPE \
+	{36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 149, 153, 157, 161, 165}, 20
+#define CHNL_RT_5G_KCC1_SCAN_TYPE \
+	{36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140}, 19
+#define CHNL_RT_5G_MKK1_SCAN_TYPE \
+	{36, 40, 44, 48, 52, 56, 60, 64}, 8
+#define CHNL_RT_5G_MKK2_SCAN_TYPE \
+	{100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140}, 11
+#define CHNL_RT_5G_MKK3_SCAN_TYPE \
+	{56, 60, 64, 100, 104, 108, 112, 116, 136, 140, 149, 153, 157, 161, 165}, 24
+#define CHNL_RT_5G_NCC1_SCAN_TYPE \
+	{56, 60, 64, 149, 153, 157, 161, 165}, 8
+
+/*
+ * Global regulation
+ *   */
+enum rt_regulation_cmn {
+	RT_WORLD,
+	RT_FCC,
+	RT_MKK,
+	RT_ETSI,
+	RT_IC,
+	RT_CE,
+	RT_NCC,
+
+};
+
+
+
+/*
+ * Special requirement for different regulation domain.
+ * For internal test or customerize special request.
+ *   */
+enum rt_chnlplan_sreq {
+	RT_SREQ_NA						= 0x0,
+	RT_SREQ_2G_ADHOC_11N			= 0x00000001,
+	RT_SREQ_2G_ADHOC_11B			= 0x00000002,
+	RT_SREQ_2G_ALL_PASS				= 0x00000004,
+	RT_SREQ_2G_ALL_ACT				= 0x00000008,
+	RT_SREQ_5G_ADHOC_11N			= 0x00000010,
+	RT_SREQ_5G_ADHOC_11AC			= 0x00000020,
+	RT_SREQ_5G_ALL_PASS				= 0x00000040,
+	RT_SREQ_5G_ALL_ACT				= 0x00000080,
+	RT_SREQ_C1_PLAN					= 0x00000100,
+	RT_SREQ_C2_PLAN					= 0x00000200,
+	RT_SREQ_C3_PLAN					= 0x00000400,
+	RT_SREQ_C4_PLAN					= 0x00000800,
+	RT_SREQ_NFC_ON					= 0x00001000,
+	RT_SREQ_MASK					= 0x0000FFFF,   /* Requirements bit mask */
+
+};
+
+
+/*
+ * enum rt_country_name & enum rt_regulation_2g & enum rt_regulation_5g transfer table
+ *
+ *   */
+struct _RT_CHANNEL_PLAN_COUNTRY_TRANSFER_TABLE {
+	/*  */
+	/* Define countery domain and corresponding */
+	/*  */
+	enum rt_country_name		country_enum;
+	char				country_name[3];
+
+	/* char		Domain_Name[12]; */
+	enum rt_regulation_2g	domain_2g;
+
+	enum rt_regulation_5g	domain_5g;
+
+	RT_CHANNEL_DOMAIN	rt_ch_domain;
+	/* u8		Country_Area; */
+
+};
+
+
+#define		RT_MAX_CHNL_NUM_2G		13
+#define		RT_MAX_CHNL_NUM_5G		44
+
+/* Power table sample. */
+
+struct _RT_CHNL_PLAN_PWR_LIMIT {
+	u16	chnl_start;
+	u16	chnl_end;
+	u8	db_max;
+	u16	m_w_max;
+};
+
+
+#define		RT_MAX_BAND_NUM			5
+
+struct _RT_CHANNEL_PLAN_MAXPWR {
+	/*	STRING_T */
+	struct _RT_CHNL_PLAN_PWR_LIMIT	chnl[RT_MAX_BAND_NUM];
+	u8				band_useful_num;
+
+
+};
+
+
+/*
+ * Power By rate Table.
+ *   */
+
+
+
+struct _RT_CHANNEL_PLAN_NEW {
+	/*  */
+	/* Define countery domain and corresponding */
+	/*  */
+	/* char		country_name[36]; */
+	/* u8		country_enum; */
+
+	/* char		Domain_Name[12]; */
+
+
+	struct _RT_CHANNEL_PLAN_COUNTRY_TRANSFER_TABLE		*p_ctry_transfer;
+
+	RT_CHANNEL_DOMAIN		rt_ch_domain;
+
+	enum rt_regulation_2g		domain_2g;
+
+	enum rt_regulation_5g		domain_5g;
+
+	enum rt_regulation_cmn		regulator;
+
+	enum rt_chnlplan_sreq		chnl_sreq;
+
+	/* struct _RT_CHNL_PLAN_LIMIT		RtChnl; */
+
+	u8	chnl_2g[MAX_CHANNEL_NUM];				/* CHNL_RT_2G_WORLD */
+	u8	len_2g;
+	u8	chnl_2g_scan_tp[MAX_CHANNEL_NUM];			/* CHNL_RT_2G_WORLD_SCAN_TYPE */
+	/* u8	Freq2G[2];								 */ /* FREQ_RT_2G_WORLD */
+
+	u8	chnl_5g[MAX_CHANNEL_NUM];
+	u8	len_5g;
+	u8	chnl_5g_scan_tp[MAX_CHANNEL_NUM];
+	/* u8	Freq2G[2];								 */ /* FREQ_RT_2G_WORLD */
+
+	struct _RT_CHANNEL_PLAN_MAXPWR	chnl_max_pwr;
+
+
+};
+
+
+#endif /* __RT_CHANNELPLAN_H__ */
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/rtl8821c/halhwimg8821c_bb.c linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/rtl8821c/halhwimg8821c_bb.c
--- linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/rtl8821c/halhwimg8821c_bb.c	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/rtl8821c/halhwimg8821c_bb.c	2020-04-10 16:35:06.828660628 +0300
@@ -0,0 +1,4149 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * The full GNU General Public License is included in this distribution in the
+ * file called LICENSE.
+ *
+ * Contact Information:
+ * wlanfae <wlanfae@realtek.com>
+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
+ * Hsinchu 300, Taiwan.
+ *
+ * Larry Finger <Larry.Finger@lwfinger.net>
+ *
+ *****************************************************************************/
+
+/*Image2HeaderVersion: R3 1.0*/
+#include "mp_precomp.h"
+#include "../phydm_precomp.h"
+
+#if (RTL8821C_SUPPORT == 1)
+static boolean
+check_positive(
+	struct dm_struct *dm,
+	const u32	condition1,
+	const u32	condition2,
+	const u32	condition3,
+	const u32	condition4
+)
+{
+	u32	cond1 = condition1, cond2 = condition2, cond3 = condition3, cond4 = condition4;
+
+	u8	cut_version_for_para = (dm->cut_version ==  ODM_CUT_A) ? 15 : dm->cut_version;
+	u8	pkg_type_for_para = (dm->package_type == 0) ? 15 : dm->package_type;
+
+	u32	driver1 = cut_version_for_para << 24 |
+			(dm->support_interface & 0xF0) << 16 |
+			dm->support_platform << 16 |
+			pkg_type_for_para << 12 |
+			(dm->support_interface & 0x0F) << 8  |
+			dm->rfe_type;
+
+	u32	driver2 = (dm->type_glna & 0xFF) <<  0 |
+			(dm->type_gpa & 0xFF)  <<  8 |
+			(dm->type_alna & 0xFF) << 16 |
+			(dm->type_apa & 0xFF)  << 24;
+
+	u32	driver3 = 0;
+
+	u32	driver4 = (dm->type_glna & 0xFF00) >>  8 |
+			(dm->type_gpa & 0xFF00) |
+			(dm->type_alna & 0xFF00) << 8 |
+			(dm->type_apa & 0xFF00)  << 16;
+
+	PHYDM_DBG(dm, ODM_COMP_INIT,
+		  "===> %s (cond1, cond2, cond3, cond4) = (0x%X 0x%X 0x%X 0x%X)\n",
+		  __func__, cond1, cond2, cond3, cond4);
+	PHYDM_DBG(dm, ODM_COMP_INIT,
+		  "===> %s (driver1, driver2, driver3, driver4) = (0x%X 0x%X 0x%X 0x%X)\n",
+		  __func__, driver1, driver2, driver3, driver4);
+
+	PHYDM_DBG(dm, ODM_COMP_INIT,
+		  "	(Platform, Interface) = (0x%X, 0x%X)\n",
+		  dm->support_platform, dm->support_interface);
+	PHYDM_DBG(dm, ODM_COMP_INIT, "	(RFE, Package) = (0x%X, 0x%X)\n",
+		  dm->rfe_type, dm->package_type);
+
+
+	/*============== value Defined Check ===============*/
+	/*cut version [27:24] need to do value check*/
+	if (((cond1 & 0x0F000000) != 0) && ((cond1 & 0x0F000000) != (driver1 & 0x0F000000)))
+		return false;
+
+	/*pkg type [15:12] need to do value check*/
+	if (((cond1 & 0x0000F000) != 0) && ((cond1 & 0x0000F000) != (driver1 & 0x0000F000)))
+		return false;
+
+	/*interface [11:8] need to do value check*/
+	if (((cond1 & 0x00000F00) != 0) && ((cond1 & 0x00000F00) != (driver1 & 0x00000F00)))
+		return false;
+	/*=============== Bit Defined Check ================*/
+	/* We don't care [31:28] */
+
+	cond1 &= 0x000000FF;
+	driver1 &= 0x000000FF;
+
+	if (cond1 == driver1)
+		return true;
+	else
+		return false;
+}
+static boolean
+check_negative(
+	struct dm_struct *dm,
+	const u32	condition1,
+	const u32	condition2
+)
+{
+	return true;
+}
+
+/******************************************************************************
+*                           agc_tab.TXT
+******************************************************************************/
+
+u32 array_mp_8821c_agc_tab[] = {
+	0x80001004,	0x00000000,	0x40000000,	0x00000000,
+		0x81C, 0xFB000003,
+		0x81C, 0xFA020003,
+		0x81C, 0xF9040003,
+		0x81C, 0xF8060003,
+		0x81C, 0xF7080003,
+		0x81C, 0xF60A0003,
+		0x81C, 0xF50C0003,
+		0x81C, 0xF40E0003,
+		0x81C, 0xF3100003,
+		0x81C, 0xF2120003,
+		0x81C, 0xF1140003,
+		0x81C, 0xF0160003,
+		0x81C, 0xEF180003,
+		0x81C, 0xEE1A0003,
+		0x81C, 0xED1C0003,
+		0x81C, 0xEC1E0003,
+		0x81C, 0xEB200003,
+		0x81C, 0xEA220003,
+		0x81C, 0xE9240003,
+		0x81C, 0xE8260003,
+		0x81C, 0xE7280003,
+		0x81C, 0xE62A0003,
+		0x81C, 0xE52C0003,
+		0x81C, 0xE42E0003,
+		0x81C, 0xE3300003,
+		0x81C, 0xE2320003,
+		0x81C, 0xE1340003,
+		0x81C, 0xC4360003,
+		0x81C, 0xC3380003,
+		0x81C, 0xC23A0003,
+		0x81C, 0xC13C0003,
+		0x81C, 0x883E0003,
+		0x81C, 0x87400003,
+		0x81C, 0x86420003,
+		0x81C, 0x85440003,
+		0x81C, 0x84460003,
+		0x81C, 0x83480003,
+		0x81C, 0x824A0003,
+		0x81C, 0x814C0003,
+		0x81C, 0x804E0003,
+		0x81C, 0x64500003,
+		0x81C, 0x63520003,
+		0x81C, 0x62540003,
+		0x81C, 0x61560003,
+		0x81C, 0x60580003,
+		0x81C, 0x475A0003,
+		0x81C, 0x465C0003,
+		0x81C, 0x455E0003,
+		0x81C, 0x44600003,
+		0x81C, 0x43620003,
+		0x81C, 0x42640003,
+		0x81C, 0x41660003,
+		0x81C, 0x40680003,
+		0x81C, 0x236A0003,
+		0x81C, 0x226C0003,
+		0x81C, 0x056E0003,
+		0x81C, 0x04700003,
+		0x81C, 0x03720003,
+		0x81C, 0x02740003,
+		0x81C, 0x01760003,
+		0x81C, 0x01780003,
+		0x81C, 0x017A0003,
+		0x81C, 0x017C0003,
+		0x81C, 0x017E0003,
+	0x90001005,	0x00000000,	0x40000000,	0x00000000,
+		0x81C, 0xFB000003,
+		0x81C, 0xFA020003,
+		0x81C, 0xF9040003,
+		0x81C, 0xF8060003,
+		0x81C, 0xF7080003,
+		0x81C, 0xF60A0003,
+		0x81C, 0xF50C0003,
+		0x81C, 0xF40E0003,
+		0x81C, 0xF3100003,
+		0x81C, 0xF2120003,
+		0x81C, 0xF1140003,
+		0x81C, 0xF0160003,
+		0x81C, 0xEF180003,
+		0x81C, 0xEE1A0003,
+		0x81C, 0xED1C0003,
+		0x81C, 0xEC1E0003,
+		0x81C, 0xEB200003,
+		0x81C, 0xEA220003,
+		0x81C, 0xE9240003,
+		0x81C, 0xE8260003,
+		0x81C, 0xE7280003,
+		0x81C, 0xE62A0003,
+		0x81C, 0xE52C0003,
+		0x81C, 0xE42E0003,
+		0x81C, 0xE3300003,
+		0x81C, 0xE2320003,
+		0x81C, 0xE1340003,
+		0x81C, 0xC4360003,
+		0x81C, 0xC3380003,
+		0x81C, 0xC23A0003,
+		0x81C, 0xC13C0003,
+		0x81C, 0x883E0003,
+		0x81C, 0x87400003,
+		0x81C, 0x86420003,
+		0x81C, 0x85440003,
+		0x81C, 0x84460003,
+		0x81C, 0x83480003,
+		0x81C, 0x824A0003,
+		0x81C, 0x814C0003,
+		0x81C, 0x804E0003,
+		0x81C, 0x64500003,
+		0x81C, 0x63520003,
+		0x81C, 0x62540003,
+		0x81C, 0x61560003,
+		0x81C, 0x60580003,
+		0x81C, 0x475A0003,
+		0x81C, 0x465C0003,
+		0x81C, 0x455E0003,
+		0x81C, 0x44600003,
+		0x81C, 0x43620003,
+		0x81C, 0x42640003,
+		0x81C, 0x41660003,
+		0x81C, 0x40680003,
+		0x81C, 0x236A0003,
+		0x81C, 0x226C0003,
+		0x81C, 0x056E0003,
+		0x81C, 0x04700003,
+		0x81C, 0x03720003,
+		0x81C, 0x02740003,
+		0x81C, 0x01760003,
+		0x81C, 0x01780003,
+		0x81C, 0x017A0003,
+		0x81C, 0x017C0003,
+		0x81C, 0x017E0003,
+	0xA0000000,	0x00000000,
+		0x81C, 0xFB000003,
+		0x81C, 0xFA020003,
+		0x81C, 0xF9040003,
+		0x81C, 0xF8060003,
+		0x81C, 0xF7080003,
+		0x81C, 0xF60A0003,
+		0x81C, 0xF50C0003,
+		0x81C, 0xF40E0003,
+		0x81C, 0xF3100003,
+		0x81C, 0xF2120003,
+		0x81C, 0xF1140003,
+		0x81C, 0xF0160003,
+		0x81C, 0xEF180003,
+		0x81C, 0xEE1A0003,
+		0x81C, 0xED1C0003,
+		0x81C, 0xEC1E0003,
+		0x81C, 0xEB200003,
+		0x81C, 0xEA220003,
+		0x81C, 0xE9240003,
+		0x81C, 0xE8260003,
+		0x81C, 0xE7280003,
+		0x81C, 0xE62A0003,
+		0x81C, 0xCA2C0003,
+		0x81C, 0xC92E0003,
+		0x81C, 0xC8300003,
+		0x81C, 0xC7320003,
+		0x81C, 0xC6340003,
+		0x81C, 0xC5360003,
+		0x81C, 0xC4380003,
+		0x81C, 0xC33A0003,
+		0x81C, 0xC23C0003,
+		0x81C, 0xC13E0003,
+		0x81C, 0x88400003,
+		0x81C, 0x87420003,
+		0x81C, 0x86440003,
+		0x81C, 0x85460003,
+		0x81C, 0x84480003,
+		0x81C, 0x834A0003,
+		0x81C, 0x674C0003,
+		0x81C, 0x664E0003,
+		0x81C, 0x65500003,
+		0x81C, 0x64520003,
+		0x81C, 0x63540003,
+		0x81C, 0x62560003,
+		0x81C, 0x61580003,
+		0x81C, 0x455A0003,
+		0x81C, 0x445C0003,
+		0x81C, 0x435E0003,
+		0x81C, 0x42600003,
+		0x81C, 0x41620003,
+		0x81C, 0x25640003,
+		0x81C, 0x24660003,
+		0x81C, 0x23680003,
+		0x81C, 0x226A0003,
+		0x81C, 0x216C0003,
+		0x81C, 0x016E0003,
+		0x81C, 0x01700003,
+		0x81C, 0x01720003,
+		0x81C, 0x01740003,
+		0x81C, 0x01760003,
+		0x81C, 0x01780003,
+		0x81C, 0x017A0003,
+		0x81C, 0x017C0003,
+		0x81C, 0x017E0003,
+	0xB0000000,	0x00000000,
+	0x80001004,	0x00000000,	0x40000000,	0x00000000,
+		0x81C, 0xFD000103,
+		0x81C, 0xFC020103,
+		0x81C, 0xFB040103,
+		0x81C, 0xFA060103,
+		0x81C, 0xF9080103,
+		0x81C, 0xF80A0103,
+		0x81C, 0xF70C0103,
+		0x81C, 0xF60E0103,
+		0x81C, 0xF5100103,
+		0x81C, 0xF4120103,
+		0x81C, 0xF3140103,
+		0x81C, 0xF2160103,
+		0x81C, 0xF1180103,
+		0x81C, 0xF01A0103,
+		0x81C, 0xEF1C0103,
+		0x81C, 0xEE1E0103,
+		0x81C, 0xED200103,
+		0x81C, 0xEC220103,
+		0x81C, 0xEB240103,
+		0x81C, 0xEA260103,
+		0x81C, 0xE9280103,
+		0x81C, 0xE82A0103,
+		0x81C, 0xE72C0103,
+		0x81C, 0xE62E0103,
+		0x81C, 0xE5300103,
+		0x81C, 0xE4320103,
+		0x81C, 0xE3340103,
+		0x81C, 0xE2360103,
+		0x81C, 0xE1380103,
+		0x81C, 0xE03A0103,
+		0x81C, 0xC33C0103,
+		0x81C, 0xC23E0103,
+		0x81C, 0xC1400103,
+		0x81C, 0xC0420103,
+		0x81C, 0xA3440103,
+		0x81C, 0xA2460103,
+		0x81C, 0xA1480103,
+		0x81C, 0xA04A0103,
+		0x81C, 0x824C0103,
+		0x81C, 0x814E0103,
+		0x81C, 0x80500103,
+		0x81C, 0x62520103,
+		0x81C, 0x61540103,
+		0x81C, 0x60560103,
+		0x81C, 0x24580103,
+		0x81C, 0x235A0103,
+		0x81C, 0x225C0103,
+		0x81C, 0x215E0103,
+		0x81C, 0x20600103,
+		0x81C, 0x03620103,
+		0x81C, 0x02640103,
+		0x81C, 0x01660103,
+		0x81C, 0x01680103,
+		0x81C, 0x016A0103,
+		0x81C, 0x016C0103,
+		0x81C, 0x016E0103,
+		0x81C, 0x01700103,
+		0x81C, 0x01720103,
+		0x81C, 0x01740103,
+		0x81C, 0x01760103,
+		0x81C, 0x01780103,
+		0x81C, 0x017A0103,
+		0x81C, 0x017C0103,
+		0x81C, 0x017E0103,
+	0x90001005,	0x00000000,	0x40000000,	0x00000000,
+		0x81C, 0xF6000103,
+		0x81C, 0xF5020103,
+		0x81C, 0xF4040103,
+		0x81C, 0xF3060103,
+		0x81C, 0xF2080103,
+		0x81C, 0xF10A0103,
+		0x81C, 0xF00C0103,
+		0x81C, 0xEF0E0103,
+		0x81C, 0xEE100103,
+		0x81C, 0xED120103,
+		0x81C, 0xEC140103,
+		0x81C, 0xCE160103,
+		0x81C, 0xEA180103,
+		0x81C, 0xE91A0103,
+		0x81C, 0xE81C0103,
+		0x81C, 0xE71E0103,
+		0x81C, 0xE6200103,
+		0x81C, 0xE5220103,
+		0x81C, 0xE4240103,
+		0x81C, 0xE3260103,
+		0x81C, 0xE2280103,
+		0x81C, 0xE12A0103,
+		0x81C, 0xC32C0103,
+		0x81C, 0xA62E0103,
+		0x81C, 0xC1300103,
+		0x81C, 0xA4320103,
+		0x81C, 0xA3340103,
+		0x81C, 0xA2360103,
+		0x81C, 0xA1380103,
+		0x81C, 0x833A0103,
+		0x81C, 0x823C0103,
+		0x81C, 0x813E0103,
+		0x81C, 0x63400103,
+		0x81C, 0x62420103,
+		0x81C, 0x61440103,
+		0x81C, 0x60460103,
+		0x81C, 0x25480103,
+		0x81C, 0x244A0103,
+		0x81C, 0x234C0103,
+		0x81C, 0x064E0103,
+		0x81C, 0x21500103,
+		0x81C, 0x04520103,
+		0x81C, 0x03540103,
+		0x81C, 0x02560103,
+		0x81C, 0x01580103,
+		0x81C, 0x005A0103,
+		0x81C, 0x005C0103,
+		0x81C, 0x005E0103,
+		0x81C, 0x00600103,
+		0x81C, 0x00620103,
+		0x81C, 0x00640103,
+		0x81C, 0x00660103,
+		0x81C, 0x00680103,
+		0x81C, 0x006A0103,
+		0x81C, 0x006C0103,
+		0x81C, 0x006E0103,
+		0x81C, 0x00700103,
+		0x81C, 0x00720103,
+		0x81C, 0x00740103,
+		0x81C, 0x00760103,
+		0x81C, 0x00780103,
+		0x81C, 0x007A0103,
+		0x81C, 0x007C0103,
+		0x81C, 0x007E0103,
+	0xA0000000,	0x00000000,
+		0x81C, 0xFD000103,
+		0x81C, 0xFC020103,
+		0x81C, 0xFB040103,
+		0x81C, 0xFA060103,
+		0x81C, 0xF9080103,
+		0x81C, 0xF80A0103,
+		0x81C, 0xF70C0103,
+		0x81C, 0xF60E0103,
+		0x81C, 0xF5100103,
+		0x81C, 0xF4120103,
+		0x81C, 0xF3140103,
+		0x81C, 0xF2160103,
+		0x81C, 0xF1180103,
+		0x81C, 0xF01A0103,
+		0x81C, 0xEF1C0103,
+		0x81C, 0xEE1E0103,
+		0x81C, 0xED200103,
+		0x81C, 0xEC220103,
+		0x81C, 0xEB240103,
+		0x81C, 0xEA260103,
+		0x81C, 0xE9280103,
+		0x81C, 0xE82A0103,
+		0x81C, 0xE72C0103,
+		0x81C, 0xE62E0103,
+		0x81C, 0xE5300103,
+		0x81C, 0xE4320103,
+		0x81C, 0xE3340103,
+		0x81C, 0xE2360103,
+		0x81C, 0xE1380103,
+		0x81C, 0xE03A0103,
+		0x81C, 0xA83C0103,
+		0x81C, 0xA73E0103,
+		0x81C, 0xA6400103,
+		0x81C, 0xA5420103,
+		0x81C, 0xA4440103,
+		0x81C, 0xA3460103,
+		0x81C, 0xA2480103,
+		0x81C, 0xA14A0103,
+		0x81C, 0x834C0103,
+		0x81C, 0x824E0103,
+		0x81C, 0x81500103,
+		0x81C, 0x63520103,
+		0x81C, 0x62540103,
+		0x81C, 0x61560103,
+		0x81C, 0x25580103,
+		0x81C, 0x245A0103,
+		0x81C, 0x235C0103,
+		0x81C, 0x225E0103,
+		0x81C, 0x04600103,
+		0x81C, 0x03620103,
+		0x81C, 0x02640103,
+		0x81C, 0x01660103,
+		0x81C, 0x01680103,
+		0x81C, 0x016A0103,
+		0x81C, 0x016C0103,
+		0x81C, 0x016E0103,
+		0x81C, 0x01700103,
+		0x81C, 0x01720103,
+		0x81C, 0x01740103,
+		0x81C, 0x01760103,
+		0x81C, 0x01780103,
+		0x81C, 0x017A0103,
+		0x81C, 0x017C0103,
+		0x81C, 0x017E0103,
+	0xB0000000,	0x00000000,
+	0x80001004,	0x00000000,	0x40000000,	0x00000000,
+		0x81C, 0xFB000203,
+		0x81C, 0xFA020203,
+		0x81C, 0xF9040203,
+		0x81C, 0xF8060203,
+		0x81C, 0xF7080203,
+		0x81C, 0xF60A0203,
+		0x81C, 0xF50C0203,
+		0x81C, 0xF40E0203,
+		0x81C, 0xF3100203,
+		0x81C, 0xF2120203,
+		0x81C, 0xF1140203,
+		0x81C, 0xF0160203,
+		0x81C, 0xEF180203,
+		0x81C, 0xEE1A0203,
+		0x81C, 0xED1C0203,
+		0x81C, 0xEC1E0203,
+		0x81C, 0xEB200203,
+		0x81C, 0xEA220203,
+		0x81C, 0xE9240203,
+		0x81C, 0xE8260203,
+		0x81C, 0xE7280203,
+		0x81C, 0xE62A0203,
+		0x81C, 0xE52C0203,
+		0x81C, 0xE42E0203,
+		0x81C, 0xE3300203,
+		0x81C, 0xE2320203,
+		0x81C, 0xE1340203,
+		0x81C, 0xC5360203,
+		0x81C, 0xC4380203,
+		0x81C, 0xC33A0203,
+		0x81C, 0xC23C0203,
+		0x81C, 0xC13E0203,
+		0x81C, 0xA4400203,
+		0x81C, 0xA3420203,
+		0x81C, 0xA2440203,
+		0x81C, 0xA1460203,
+		0x81C, 0xA0480203,
+		0x81C, 0x834A0203,
+		0x81C, 0x824C0203,
+		0x81C, 0x814E0203,
+		0x81C, 0x63500203,
+		0x81C, 0x62520203,
+		0x81C, 0x61540203,
+		0x81C, 0x60560203,
+		0x81C, 0x23580203,
+		0x81C, 0x225A0203,
+		0x81C, 0x215C0203,
+		0x81C, 0x205E0203,
+		0x81C, 0x04600203,
+		0x81C, 0x03620203,
+		0x81C, 0x02640203,
+		0x81C, 0x01660203,
+		0x81C, 0x01680203,
+		0x81C, 0x016A0203,
+		0x81C, 0x016C0203,
+		0x81C, 0x016E0203,
+		0x81C, 0x01700203,
+		0x81C, 0x01720203,
+		0x81C, 0x01740203,
+		0x81C, 0x01760203,
+		0x81C, 0x01780203,
+		0x81C, 0x017A0203,
+		0x81C, 0x017C0203,
+		0x81C, 0x017E0203,
+	0x90001005,	0x00000000,	0x40000000,	0x00000000,
+		0x81C, 0xF6000203,
+		0x81C, 0xF5020203,
+		0x81C, 0xF4040203,
+		0x81C, 0xF3060203,
+		0x81C, 0xF2080203,
+		0x81C, 0xF10A0203,
+		0x81C, 0xF00C0203,
+		0x81C, 0xEF0E0203,
+		0x81C, 0xEE100203,
+		0x81C, 0xED120203,
+		0x81C, 0xEC140203,
+		0x81C, 0xEB160203,
+		0x81C, 0xEA180203,
+		0x81C, 0xE91A0203,
+		0x81C, 0xE81C0203,
+		0x81C, 0xE71E0203,
+		0x81C, 0xE6200203,
+		0x81C, 0xE5220203,
+		0x81C, 0xE4240203,
+		0x81C, 0xE3260203,
+		0x81C, 0xE2280203,
+		0x81C, 0xE12A0203,
+		0x81C, 0xE02C0203,
+		0x81C, 0xC22E0203,
+		0x81C, 0xC1300203,
+		0x81C, 0xC0320203,
+		0x81C, 0xA3340203,
+		0x81C, 0xA2360203,
+		0x81C, 0xA1380203,
+		0x81C, 0xA03A0203,
+		0x81C, 0x833C0203,
+		0x81C, 0x823E0203,
+		0x81C, 0x81400203,
+		0x81C, 0x80420203,
+		0x81C, 0x62440203,
+		0x81C, 0x61460203,
+		0x81C, 0x42480203,
+		0x81C, 0x414A0203,
+		0x81C, 0x234C0203,
+		0x81C, 0x224E0203,
+		0x81C, 0x21500203,
+		0x81C, 0x20520203,
+		0x81C, 0x03540203,
+		0x81C, 0x02560203,
+		0x81C, 0x01580203,
+		0x81C, 0x005A0203,
+		0x81C, 0x005C0203,
+		0x81C, 0x005E0203,
+		0x81C, 0x00600203,
+		0x81C, 0x00620203,
+		0x81C, 0x00640203,
+		0x81C, 0x00660203,
+		0x81C, 0x00680203,
+		0x81C, 0x006A0203,
+		0x81C, 0x006C0203,
+		0x81C, 0x006E0203,
+		0x81C, 0x00700203,
+		0x81C, 0x00720203,
+		0x81C, 0x00740203,
+		0x81C, 0x00760203,
+		0x81C, 0x00780203,
+		0x81C, 0x007A0203,
+		0x81C, 0x007C0203,
+		0x81C, 0x007E0203,
+	0xA0000000,	0x00000000,
+		0x81C, 0xFC000203,
+		0x81C, 0xFB020203,
+		0x81C, 0xFA040203,
+		0x81C, 0xF9060203,
+		0x81C, 0xF8080203,
+		0x81C, 0xF70A0203,
+		0x81C, 0xF60C0203,
+		0x81C, 0xF50E0203,
+		0x81C, 0xF4100203,
+		0x81C, 0xF3120203,
+		0x81C, 0xF2140203,
+		0x81C, 0xF1160203,
+		0x81C, 0xF0180203,
+		0x81C, 0xEF1A0203,
+		0x81C, 0xEE1C0203,
+		0x81C, 0xED1E0203,
+		0x81C, 0xEC200203,
+		0x81C, 0xEB220203,
+		0x81C, 0xEA240203,
+		0x81C, 0xE9260203,
+		0x81C, 0xE8280203,
+		0x81C, 0xE72A0203,
+		0x81C, 0xE62C0203,
+		0x81C, 0xE52E0203,
+		0x81C, 0xE4300203,
+		0x81C, 0xE3320203,
+		0x81C, 0xE2340203,
+		0x81C, 0xE1360203,
+		0x81C, 0xC5380203,
+		0x81C, 0xC43A0203,
+		0x81C, 0xC33C0203,
+		0x81C, 0xC23E0203,
+		0x81C, 0xA6400203,
+		0x81C, 0xA5420203,
+		0x81C, 0xA4440203,
+		0x81C, 0xA3460203,
+		0x81C, 0xA2480203,
+		0x81C, 0x844A0203,
+		0x81C, 0x834C0203,
+		0x81C, 0x824E0203,
+		0x81C, 0x64500203,
+		0x81C, 0x63520203,
+		0x81C, 0x62540203,
+		0x81C, 0x61560203,
+		0x81C, 0x60580203,
+		0x81C, 0x235A0203,
+		0x81C, 0x225C0203,
+		0x81C, 0x215E0203,
+		0x81C, 0x04600203,
+		0x81C, 0x03620203,
+		0x81C, 0x02640203,
+		0x81C, 0x01660203,
+		0x81C, 0x01680203,
+		0x81C, 0x016A0203,
+		0x81C, 0x016C0203,
+		0x81C, 0x016E0203,
+		0x81C, 0x01700203,
+		0x81C, 0x01720203,
+		0x81C, 0x01740203,
+		0x81C, 0x01760203,
+		0x81C, 0x01780203,
+		0x81C, 0x017A0203,
+		0x81C, 0x017C0203,
+		0x81C, 0x017E0203,
+	0xB0000000,	0x00000000,
+	0x80001004,	0x00000000,	0x40000000,	0x00000000,
+		0x81C, 0xFB000303,
+		0x81C, 0xFA020303,
+		0x81C, 0xF9040303,
+		0x81C, 0xF8060303,
+		0x81C, 0xF7080303,
+		0x81C, 0xF60A0303,
+		0x81C, 0xF50C0303,
+		0x81C, 0xF40E0303,
+		0x81C, 0xF3100303,
+		0x81C, 0xF2120303,
+		0x81C, 0xF1140303,
+		0x81C, 0xF0160303,
+		0x81C, 0xEF180303,
+		0x81C, 0xEE1A0303,
+		0x81C, 0xED1C0303,
+		0x81C, 0xEC1E0303,
+		0x81C, 0xEB200303,
+		0x81C, 0xEA220303,
+		0x81C, 0xE9240303,
+		0x81C, 0xE8260303,
+		0x81C, 0xE7280303,
+		0x81C, 0xE62A0303,
+		0x81C, 0xE52C0303,
+		0x81C, 0xE42E0303,
+		0x81C, 0xE3300303,
+		0x81C, 0xE2320303,
+		0x81C, 0xE1340303,
+		0x81C, 0xC4360303,
+		0x81C, 0xC3380303,
+		0x81C, 0xC23A0303,
+		0x81C, 0xC13C0303,
+		0x81C, 0xA53E0303,
+		0x81C, 0xA4400303,
+		0x81C, 0xA3420303,
+		0x81C, 0xA2440303,
+		0x81C, 0xA1460303,
+		0x81C, 0x83480303,
+		0x81C, 0x824A0303,
+		0x81C, 0x814C0303,
+		0x81C, 0x644E0303,
+		0x81C, 0x63500303,
+		0x81C, 0x62520303,
+		0x81C, 0x61540303,
+		0x81C, 0x60560303,
+		0x81C, 0x23580303,
+		0x81C, 0x225A0303,
+		0x81C, 0x215C0303,
+		0x81C, 0x045E0303,
+		0x81C, 0x03600303,
+		0x81C, 0x02620303,
+		0x81C, 0x01640303,
+		0x81C, 0x01660303,
+		0x81C, 0x01680303,
+		0x81C, 0x016A0303,
+		0x81C, 0x016C0303,
+		0x81C, 0x016E0303,
+		0x81C, 0x01700303,
+		0x81C, 0x01720303,
+		0x81C, 0x01740303,
+		0x81C, 0x01760303,
+		0x81C, 0x01780303,
+		0x81C, 0x017A0303,
+		0x81C, 0x017C0303,
+		0x81C, 0x017E0303,
+	0x90001005,	0x00000000,	0x40000000,	0x00000000,
+		0x81C, 0xF5000303,
+		0x81C, 0xF4020303,
+		0x81C, 0xF3040303,
+		0x81C, 0xF2060303,
+		0x81C, 0xF1080303,
+		0x81C, 0xF00A0303,
+		0x81C, 0xEF0C0303,
+		0x81C, 0xEE0E0303,
+		0x81C, 0xED100303,
+		0x81C, 0xEC120303,
+		0x81C, 0xEB140303,
+		0x81C, 0xEA160303,
+		0x81C, 0xE9180303,
+		0x81C, 0xE81A0303,
+		0x81C, 0xE71C0303,
+		0x81C, 0xE61E0303,
+		0x81C, 0xE5200303,
+		0x81C, 0xE4220303,
+		0x81C, 0xE3240303,
+		0x81C, 0xE2260303,
+		0x81C, 0xE1280303,
+		0x81C, 0xE02A0303,
+		0x81C, 0xA72C0303,
+		0x81C, 0xA62E0303,
+		0x81C, 0xA5300303,
+		0x81C, 0xA4320303,
+		0x81C, 0xA3340303,
+		0x81C, 0xA2360303,
+		0x81C, 0xA1380303,
+		0x81C, 0xA03A0303,
+		0x81C, 0x823C0303,
+		0x81C, 0x643E0303,
+		0x81C, 0x63400303,
+		0x81C, 0x62420303,
+		0x81C, 0x61440303,
+		0x81C, 0x60460303,
+		0x81C, 0x24480303,
+		0x81C, 0x234A0303,
+		0x81C, 0x224C0303,
+		0x81C, 0x054E0303,
+		0x81C, 0x04500303,
+		0x81C, 0x03520303,
+		0x81C, 0x02540303,
+		0x81C, 0x01560303,
+		0x81C, 0x00580303,
+		0x81C, 0x005A0303,
+		0x81C, 0x005C0303,
+		0x81C, 0x005E0303,
+		0x81C, 0x00600303,
+		0x81C, 0x00620303,
+		0x81C, 0x00640303,
+		0x81C, 0x00660303,
+		0x81C, 0x00680303,
+		0x81C, 0x006A0303,
+		0x81C, 0x006C0303,
+		0x81C, 0x006E0303,
+		0x81C, 0x00700303,
+		0x81C, 0x00720303,
+		0x81C, 0x00740303,
+		0x81C, 0x00760303,
+		0x81C, 0x00780303,
+		0x81C, 0x007A0303,
+		0x81C, 0x007C0303,
+		0x81C, 0x007E0303,
+	0xA0000000,	0x00000000,
+		0x81C, 0xFC000303,
+		0x81C, 0xFB020303,
+		0x81C, 0xFA040303,
+		0x81C, 0xF9060303,
+		0x81C, 0xF8080303,
+		0x81C, 0xF70A0303,
+		0x81C, 0xF60C0303,
+		0x81C, 0xF50E0303,
+		0x81C, 0xF4100303,
+		0x81C, 0xF3120303,
+		0x81C, 0xF2140303,
+		0x81C, 0xF1160303,
+		0x81C, 0xF0180303,
+		0x81C, 0xEF1A0303,
+		0x81C, 0xEE1C0303,
+		0x81C, 0xED1E0303,
+		0x81C, 0xEC200303,
+		0x81C, 0xEB220303,
+		0x81C, 0xEA240303,
+		0x81C, 0xE9260303,
+		0x81C, 0xE8280303,
+		0x81C, 0xE72A0303,
+		0x81C, 0xE62C0303,
+		0x81C, 0xE52E0303,
+		0x81C, 0xE4300303,
+		0x81C, 0xE3320303,
+		0x81C, 0xE2340303,
+		0x81C, 0xE1360303,
+		0x81C, 0xC4380303,
+		0x81C, 0xC33A0303,
+		0x81C, 0xC23C0303,
+		0x81C, 0xC13E0303,
+		0x81C, 0xA5400303,
+		0x81C, 0xA4420303,
+		0x81C, 0xA3440303,
+		0x81C, 0xA2460303,
+		0x81C, 0xA1480303,
+		0x81C, 0x834A0303,
+		0x81C, 0x824C0303,
+		0x81C, 0x814E0303,
+		0x81C, 0x64500303,
+		0x81C, 0x63520303,
+		0x81C, 0x62540303,
+		0x81C, 0x61560303,
+		0x81C, 0x24580303,
+		0x81C, 0x235A0303,
+		0x81C, 0x225C0303,
+		0x81C, 0x215E0303,
+		0x81C, 0x04600303,
+		0x81C, 0x03620303,
+		0x81C, 0x02640303,
+		0x81C, 0x01660303,
+		0x81C, 0x01680303,
+		0x81C, 0x016A0303,
+		0x81C, 0x016C0303,
+		0x81C, 0x016E0303,
+		0x81C, 0x01700303,
+		0x81C, 0x01720303,
+		0x81C, 0x01740303,
+		0x81C, 0x01760303,
+		0x81C, 0x01780303,
+		0x81C, 0x017A0303,
+		0x81C, 0x017C0303,
+		0x81C, 0x017E0303,
+	0xB0000000,	0x00000000,
+	0x80001004,	0x00000000,	0x40000000,	0x00000000,
+		0x81C, 0xFC000803,
+		0x81C, 0xFB020803,
+		0x81C, 0xFA040803,
+		0x81C, 0xF9060803,
+		0x81C, 0xF8080803,
+		0x81C, 0xF70A0803,
+		0x81C, 0xF60C0803,
+		0x81C, 0xF50E0803,
+		0x81C, 0xF4100803,
+		0x81C, 0xF3120803,
+		0x81C, 0xF2140803,
+		0x81C, 0xF1160803,
+		0x81C, 0xF0180803,
+		0x81C, 0xEF1A0803,
+		0x81C, 0xEE1C0803,
+		0x81C, 0xED1E0803,
+		0x81C, 0xB5200803,
+		0x81C, 0xB4220803,
+		0x81C, 0xB3240803,
+		0x81C, 0xB2260803,
+		0x81C, 0xB1280803,
+		0x81C, 0xB02A0803,
+		0x81C, 0xAF2C0803,
+		0x81C, 0xAE2E0803,
+		0x81C, 0xAD300803,
+		0x81C, 0xAC320803,
+		0x81C, 0xAB340803,
+		0x81C, 0xAA360803,
+		0x81C, 0xA9380803,
+		0x81C, 0xA83A0803,
+		0x81C, 0xA73C0803,
+		0x81C, 0xA63E0803,
+		0x81C, 0x88400803,
+		0x81C, 0x87420803,
+		0x81C, 0x86440803,
+		0x81C, 0x85460803,
+		0x81C, 0x84480803,
+		0x81C, 0x834A0803,
+		0x81C, 0x674C0803,
+		0x81C, 0x664E0803,
+		0x81C, 0x65500803,
+		0x81C, 0x64520803,
+		0x81C, 0x63540803,
+		0x81C, 0x62560803,
+		0x81C, 0x61580803,
+		0x81C, 0x455A0803,
+		0x81C, 0x445C0803,
+		0x81C, 0x435E0803,
+		0x81C, 0x42600803,
+		0x81C, 0x41620803,
+		0x81C, 0x25640803,
+		0x81C, 0x24660803,
+		0x81C, 0x23680803,
+		0x81C, 0x226A0803,
+		0x81C, 0x216C0803,
+		0x81C, 0x016E0803,
+		0x81C, 0x01700803,
+		0x81C, 0x01720803,
+		0x81C, 0x01740803,
+		0x81C, 0x01760803,
+		0x81C, 0x01780803,
+		0x81C, 0x017A0803,
+		0x81C, 0x017C0803,
+		0x81C, 0x017E0803,
+	0x90001005,	0x00000000,	0x40000000,	0x00000000,
+		0x81C, 0xFC000803,
+		0x81C, 0xFB020803,
+		0x81C, 0xFA040803,
+		0x81C, 0xF9060803,
+		0x81C, 0xF8080803,
+		0x81C, 0xF70A0803,
+		0x81C, 0xF60C0803,
+		0x81C, 0xF50E0803,
+		0x81C, 0xF4100803,
+		0x81C, 0xF3120803,
+		0x81C, 0xF2140803,
+		0x81C, 0xF1160803,
+		0x81C, 0xF0180803,
+		0x81C, 0xEF1A0803,
+		0x81C, 0xEE1C0803,
+		0x81C, 0xED1E0803,
+		0x81C, 0xB5200803,
+		0x81C, 0xB4220803,
+		0x81C, 0xB3240803,
+		0x81C, 0xB2260803,
+		0x81C, 0xB1280803,
+		0x81C, 0xB02A0803,
+		0x81C, 0xAF2C0803,
+		0x81C, 0xAE2E0803,
+		0x81C, 0xAD300803,
+		0x81C, 0xAC320803,
+		0x81C, 0xAB340803,
+		0x81C, 0xAA360803,
+		0x81C, 0xA9380803,
+		0x81C, 0xA83A0803,
+		0x81C, 0xA73C0803,
+		0x81C, 0xA63E0803,
+		0x81C, 0x88400803,
+		0x81C, 0x87420803,
+		0x81C, 0x86440803,
+		0x81C, 0x85460803,
+		0x81C, 0x84480803,
+		0x81C, 0x834A0803,
+		0x81C, 0x674C0803,
+		0x81C, 0x664E0803,
+		0x81C, 0x65500803,
+		0x81C, 0x64520803,
+		0x81C, 0x63540803,
+		0x81C, 0x62560803,
+		0x81C, 0x61580803,
+		0x81C, 0x455A0803,
+		0x81C, 0x445C0803,
+		0x81C, 0x435E0803,
+		0x81C, 0x42600803,
+		0x81C, 0x41620803,
+		0x81C, 0x25640803,
+		0x81C, 0x24660803,
+		0x81C, 0x23680803,
+		0x81C, 0x226A0803,
+		0x81C, 0x216C0803,
+		0x81C, 0x016E0803,
+		0x81C, 0x01700803,
+		0x81C, 0x01720803,
+		0x81C, 0x01740803,
+		0x81C, 0x01760803,
+		0x81C, 0x01780803,
+		0x81C, 0x017A0803,
+		0x81C, 0x017C0803,
+		0x81C, 0x017E0803,
+	0xA0000000,	0x00000000,
+		0x81C, 0xFC000803,
+		0x81C, 0xFB020803,
+		0x81C, 0xFA040803,
+		0x81C, 0xF9060803,
+		0x81C, 0xF8080803,
+		0x81C, 0xF70A0803,
+		0x81C, 0xF60C0803,
+		0x81C, 0xF50E0803,
+		0x81C, 0xF4100803,
+		0x81C, 0xF3120803,
+		0x81C, 0xF2140803,
+		0x81C, 0xF1160803,
+		0x81C, 0xF0180803,
+		0x81C, 0xEF1A0803,
+		0x81C, 0xEE1C0803,
+		0x81C, 0xED1E0803,
+		0x81C, 0xB5200803,
+		0x81C, 0xB4220803,
+		0x81C, 0xB3240803,
+		0x81C, 0xB2260803,
+		0x81C, 0xB1280803,
+		0x81C, 0xB02A0803,
+		0x81C, 0xAF2C0803,
+		0x81C, 0xAE2E0803,
+		0x81C, 0xAD300803,
+		0x81C, 0xAC320803,
+		0x81C, 0xAB340803,
+		0x81C, 0xAA360803,
+		0x81C, 0xA9380803,
+		0x81C, 0xA83A0803,
+		0x81C, 0xA73C0803,
+		0x81C, 0xA63E0803,
+		0x81C, 0x88400803,
+		0x81C, 0x87420803,
+		0x81C, 0x86440803,
+		0x81C, 0x85460803,
+		0x81C, 0x84480803,
+		0x81C, 0x834A0803,
+		0x81C, 0x674C0803,
+		0x81C, 0x664E0803,
+		0x81C, 0x65500803,
+		0x81C, 0x64520803,
+		0x81C, 0x63540803,
+		0x81C, 0x62560803,
+		0x81C, 0x61580803,
+		0x81C, 0x455A0803,
+		0x81C, 0x445C0803,
+		0x81C, 0x435E0803,
+		0x81C, 0x42600803,
+		0x81C, 0x41620803,
+		0x81C, 0x25640803,
+		0x81C, 0x24660803,
+		0x81C, 0x23680803,
+		0x81C, 0x226A0803,
+		0x81C, 0x216C0803,
+		0x81C, 0x016E0803,
+		0x81C, 0x01700803,
+		0x81C, 0x01720803,
+		0x81C, 0x01740803,
+		0x81C, 0x01760803,
+		0x81C, 0x01780803,
+		0x81C, 0x017A0803,
+		0x81C, 0x017C0803,
+		0x81C, 0x017E0803,
+	0xB0000000,	0x00000000,
+	0x80001004,	0x00000000,	0x40000000,	0x00000000,
+		0x81C, 0xFF000913,
+		0x81C, 0xFE020913,
+		0x81C, 0xFD040913,
+		0x81C, 0xFC060913,
+		0x81C, 0xFB080913,
+		0x81C, 0xFA0A0913,
+		0x81C, 0xF90C0913,
+		0x81C, 0xF80E0913,
+		0x81C, 0xF7100913,
+		0x81C, 0xF6120913,
+		0x81C, 0xF5140913,
+		0x81C, 0xF4160913,
+		0x81C, 0xF3180913,
+		0x81C, 0xF21A0913,
+		0x81C, 0xF11C0913,
+		0x81C, 0x941E0913,
+		0x81C, 0x93200913,
+		0x81C, 0x92220913,
+		0x81C, 0x91240913,
+		0x81C, 0x90260913,
+		0x81C, 0x8F280913,
+		0x81C, 0x8E2A0913,
+		0x81C, 0x8D2C0913,
+		0x81C, 0x8C2E0913,
+		0x81C, 0x8B300913,
+		0x81C, 0x8A320913,
+		0x81C, 0x89340913,
+		0x81C, 0x88360913,
+		0x81C, 0x87380913,
+		0x81C, 0x863A0913,
+		0x81C, 0x853C0913,
+		0x81C, 0x843E0913,
+		0x81C, 0x83400913,
+		0x81C, 0x82420913,
+		0x81C, 0x81440913,
+		0x81C, 0x07460913,
+		0x81C, 0x06480913,
+		0x81C, 0x054A0913,
+		0x81C, 0x044C0913,
+		0x81C, 0x034E0913,
+		0x81C, 0x02500913,
+		0x81C, 0x01520913,
+		0x81C, 0x88540903,
+		0x81C, 0x87560903,
+		0x81C, 0x86580903,
+		0x81C, 0x855A0903,
+		0x81C, 0x845C0903,
+		0x81C, 0x835E0903,
+		0x81C, 0x82600903,
+		0x81C, 0x81620903,
+		0x81C, 0x07640903,
+		0x81C, 0x06660903,
+		0x81C, 0x05680903,
+		0x81C, 0x046A0903,
+		0x81C, 0x036C0903,
+		0x81C, 0x026E0903,
+		0x81C, 0x01700903,
+		0x81C, 0x01720903,
+		0x81C, 0x01740903,
+		0x81C, 0x01760903,
+		0x81C, 0x01780903,
+		0x81C, 0x017A0903,
+		0x81C, 0x017C0903,
+		0x81C, 0x017E0903,
+	0x90001005,	0x00000000,	0x40000000,	0x00000000,
+		0x81C, 0xFF000913,
+		0x81C, 0xFE020913,
+		0x81C, 0xFD040913,
+		0x81C, 0xFC060913,
+		0x81C, 0xFB080913,
+		0x81C, 0xFA0A0913,
+		0x81C, 0xF90C0913,
+		0x81C, 0xF80E0913,
+		0x81C, 0xF7100913,
+		0x81C, 0xF6120913,
+		0x81C, 0xF5140913,
+		0x81C, 0xF4160913,
+		0x81C, 0xF3180913,
+		0x81C, 0xF21A0913,
+		0x81C, 0xF11C0913,
+		0x81C, 0x941E0913,
+		0x81C, 0x93200913,
+		0x81C, 0x92220913,
+		0x81C, 0x91240913,
+		0x81C, 0x90260913,
+		0x81C, 0x8F280913,
+		0x81C, 0x8E2A0913,
+		0x81C, 0x8D2C0913,
+		0x81C, 0x8C2E0913,
+		0x81C, 0x8B300913,
+		0x81C, 0x8A320913,
+		0x81C, 0x89340913,
+		0x81C, 0x88360913,
+		0x81C, 0x87380913,
+		0x81C, 0x863A0913,
+		0x81C, 0x853C0913,
+		0x81C, 0x843E0913,
+		0x81C, 0x83400913,
+		0x81C, 0x82420913,
+		0x81C, 0x81440913,
+		0x81C, 0x07460913,
+		0x81C, 0x06480913,
+		0x81C, 0x054A0913,
+		0x81C, 0x044C0913,
+		0x81C, 0x034E0913,
+		0x81C, 0x02500913,
+		0x81C, 0x01520913,
+		0x81C, 0x88540903,
+		0x81C, 0x87560903,
+		0x81C, 0x86580903,
+		0x81C, 0x855A0903,
+		0x81C, 0x845C0903,
+		0x81C, 0x835E0903,
+		0x81C, 0x82600903,
+		0x81C, 0x81620903,
+		0x81C, 0x07640903,
+		0x81C, 0x06660903,
+		0x81C, 0x05680903,
+		0x81C, 0x046A0903,
+		0x81C, 0x036C0903,
+		0x81C, 0x026E0903,
+		0x81C, 0x01700903,
+		0x81C, 0x01720903,
+		0x81C, 0x01740903,
+		0x81C, 0x01760903,
+		0x81C, 0x01780903,
+		0x81C, 0x017A0903,
+		0x81C, 0x017C0903,
+		0x81C, 0x017E0903,
+	0xA0000000,	0x00000000,
+		0x81C, 0xFF000913,
+		0x81C, 0xFE020913,
+		0x81C, 0xFD040913,
+		0x81C, 0xFC060913,
+		0x81C, 0xFB080913,
+		0x81C, 0xFA0A0913,
+		0x81C, 0xF90C0913,
+		0x81C, 0xF80E0913,
+		0x81C, 0xF7100913,
+		0x81C, 0xF6120913,
+		0x81C, 0xF5140913,
+		0x81C, 0xF4160913,
+		0x81C, 0xF3180913,
+		0x81C, 0xF21A0913,
+		0x81C, 0xF11C0913,
+		0x81C, 0x941E0913,
+		0x81C, 0x93200913,
+		0x81C, 0x92220913,
+		0x81C, 0x91240913,
+		0x81C, 0x90260913,
+		0x81C, 0x8F280913,
+		0x81C, 0x8E2A0913,
+		0x81C, 0x8D2C0913,
+		0x81C, 0x8C2E0913,
+		0x81C, 0x8B300913,
+		0x81C, 0x8A320913,
+		0x81C, 0x89340913,
+		0x81C, 0x88360913,
+		0x81C, 0x87380913,
+		0x81C, 0x863A0913,
+		0x81C, 0x853C0913,
+		0x81C, 0x843E0913,
+		0x81C, 0x83400913,
+		0x81C, 0x82420913,
+		0x81C, 0x81440913,
+		0x81C, 0x07460913,
+		0x81C, 0x06480913,
+		0x81C, 0x054A0913,
+		0x81C, 0x044C0913,
+		0x81C, 0x034E0913,
+		0x81C, 0x02500913,
+		0x81C, 0x01520913,
+		0x81C, 0x88540903,
+		0x81C, 0x87560903,
+		0x81C, 0x86580903,
+		0x81C, 0x855A0903,
+		0x81C, 0x845C0903,
+		0x81C, 0x835E0903,
+		0x81C, 0x82600903,
+		0x81C, 0x81620903,
+		0x81C, 0x07640903,
+		0x81C, 0x06660903,
+		0x81C, 0x05680903,
+		0x81C, 0x046A0903,
+		0x81C, 0x036C0903,
+		0x81C, 0x026E0903,
+		0x81C, 0x01700903,
+		0x81C, 0x01720903,
+		0x81C, 0x01740903,
+		0x81C, 0x01760903,
+		0x81C, 0x01780903,
+		0x81C, 0x017A0903,
+		0x81C, 0x017C0903,
+		0x81C, 0x017E0903,
+	0xB0000000,	0x00000000,
+	0x80001004,	0x00000000,	0x40000000,	0x00000000,
+		0xC50, 0x00000022,
+		0xC50, 0x00000020,
+	0x90001005,	0x00000000,	0x40000000,	0x00000000,
+		0xC50, 0x00000022,
+		0xC50, 0x00000022,
+	0xA0000000,	0x00000000,
+		0xC50, 0x00000022,
+		0xC50, 0x00000020,
+	0xB0000000,	0x00000000,
+
+};
+
+void
+odm_read_and_config_mp_8821c_agc_tab(struct dm_struct *dm)
+{
+	u32	i = 0;
+	u8	c_cond;
+	boolean	is_matched = true, is_skipped = false;
+	u32	array_len = sizeof(array_mp_8821c_agc_tab) / sizeof(u32);
+	u32	*array = array_mp_8821c_agc_tab;
+
+	u32	v1 = 0, v2 = 0, pre_v1 = 0, pre_v2 = 0;
+
+	PHYDM_DBG(dm, ODM_COMP_INIT, "===> %s\n", __func__);
+
+	while ((i + 1) < array_len) {
+		v1 = array[i];
+		v2 = array[i + 1];
+
+		if (v1 & (BIT(31) | BIT(30))) {/*positive & negative condition*/
+			if (v1 & BIT(31)) {/* positive condition*/
+				c_cond  = (u8)((v1 & (BIT(29) | BIT(28))) >> 28);
+				if (c_cond == COND_ENDIF) {/*end*/
+					is_matched = true;
+					is_skipped = false;
+					PHYDM_DBG(dm, ODM_COMP_INIT, "ENDIF\n");
+				} else if (c_cond == COND_ELSE) { /*else*/
+					is_matched = is_skipped ? false : true;
+					PHYDM_DBG(dm, ODM_COMP_INIT, "ELSE\n");
+				} else {/*if , else if*/
+					pre_v1 = v1;
+					pre_v2 = v2;
+					PHYDM_DBG(dm, ODM_COMP_INIT, "IF or ELSE IF\n");
+				}
+			} else if (v1 & BIT(30)) { /*negative condition*/
+				if (is_skipped == false) {
+					if (check_positive(dm, pre_v1, pre_v2, v1, v2)) {
+						is_matched = true;
+						is_skipped = true;
+					} else {
+						is_matched = false;
+						is_skipped = false;
+					}
+				} else
+					is_matched = false;
+			}
+		} else {
+			if (is_matched)
+				odm_config_bb_agc_8821c(dm, v1, MASKDWORD, v2);
+		}
+		i = i + 2;
+	}
+}
+
+u32
+odm_get_version_mp_8821c_agc_tab(void)
+{
+		return 49;
+}
+
+/******************************************************************************
+*                           agc_tab_diff.TXT
+******************************************************************************/
+
+u32 array_mp_8821c_agc_tab_diff_wlg[] = {
+	0x80001004,	0x00000000,	0x40000000,	0x00000000,
+		0x81C, 0xFB000003,
+		0x81C, 0xFA020003,
+		0x81C, 0xF9040003,
+		0x81C, 0xF8060003,
+		0x81C, 0xF7080003,
+		0x81C, 0xF60A0003,
+		0x81C, 0xF50C0003,
+		0x81C, 0xF40E0003,
+		0x81C, 0xF3100003,
+		0x81C, 0xF2120003,
+		0x81C, 0xF1140003,
+		0x81C, 0xF0160003,
+		0x81C, 0xEF180003,
+		0x81C, 0xEE1A0003,
+		0x81C, 0xED1C0003,
+		0x81C, 0xEC1E0003,
+		0x81C, 0xEB200003,
+		0x81C, 0xEA220003,
+		0x81C, 0xE9240003,
+		0x81C, 0xE8260003,
+		0x81C, 0xE7280003,
+		0x81C, 0xE62A0003,
+		0x81C, 0xE52C0003,
+		0x81C, 0xE42E0003,
+		0x81C, 0xE3300003,
+		0x81C, 0xE2320003,
+		0x81C, 0xE1340003,
+		0x81C, 0xC4360003,
+		0x81C, 0xC3380003,
+		0x81C, 0xC23A0003,
+		0x81C, 0xC13C0003,
+		0x81C, 0x883E0003,
+		0x81C, 0x87400003,
+		0x81C, 0x86420003,
+		0x81C, 0x85440003,
+		0x81C, 0x84460003,
+		0x81C, 0x83480003,
+		0x81C, 0x824A0003,
+		0x81C, 0x814C0003,
+		0x81C, 0x804E0003,
+		0x81C, 0x64500003,
+		0x81C, 0x63520003,
+		0x81C, 0x62540003,
+		0x81C, 0x61560003,
+		0x81C, 0x60580003,
+		0x81C, 0x475A0003,
+		0x81C, 0x465C0003,
+		0x81C, 0x455E0003,
+		0x81C, 0x44600003,
+		0x81C, 0x43620003,
+		0x81C, 0x42640003,
+		0x81C, 0x41660003,
+		0x81C, 0x40680003,
+		0x81C, 0x236A0003,
+		0x81C, 0x226C0003,
+		0x81C, 0x056E0003,
+		0x81C, 0x04700003,
+		0x81C, 0x03720003,
+		0x81C, 0x02740003,
+		0x81C, 0x01760003,
+		0x81C, 0x01780003,
+		0x81C, 0x017A0003,
+		0x81C, 0x017C0003,
+		0x81C, 0x017E0003,
+		0x81C, 0xFF000803,
+		0x81C, 0xFE020803,
+		0x81C, 0xFD040803,
+		0x81C, 0xFC060803,
+		0x81C, 0xFB080803,
+		0x81C, 0xFA0A0803,
+		0x81C, 0xF90C0803,
+		0x81C, 0xF80E0803,
+		0x81C, 0xF7100803,
+		0x81C, 0xF6120803,
+		0x81C, 0xF5140803,
+		0x81C, 0xF4160803,
+		0x81C, 0xF3180803,
+		0x81C, 0xF21A0803,
+		0x81C, 0xF11C0803,
+		0x81C, 0xF01E0803,
+		0x81C, 0xB7200803,
+		0x81C, 0xB6220803,
+		0x81C, 0xB5240803,
+		0x81C, 0xB4260803,
+		0x81C, 0xB3280803,
+		0x81C, 0xB22A0803,
+		0x81C, 0xB12C0803,
+		0x81C, 0xAF2E0803,
+		0x81C, 0xAE300803,
+		0x81C, 0xAD320803,
+		0x81C, 0xAC340803,
+		0x81C, 0xAB360803,
+		0x81C, 0xAA380803,
+		0x81C, 0xA93A0803,
+		0x81C, 0xA83C0803,
+		0x81C, 0xA73E0803,
+		0x81C, 0x88400803,
+		0x81C, 0x87420803,
+		0x81C, 0x86440803,
+		0x81C, 0x85460803,
+		0x81C, 0x84480803,
+		0x81C, 0x834A0803,
+		0x81C, 0x674C0803,
+		0x81C, 0x664E0803,
+		0x81C, 0x65500803,
+		0x81C, 0x64520803,
+		0x81C, 0x63540803,
+		0x81C, 0x62560803,
+		0x81C, 0x61580803,
+		0x81C, 0x455A0803,
+		0x81C, 0x445C0803,
+		0x81C, 0x435E0803,
+		0x81C, 0x42600803,
+		0x81C, 0x41620803,
+		0x81C, 0x25640803,
+		0x81C, 0x24660803,
+		0x81C, 0x23680803,
+		0x81C, 0x226A0803,
+		0x81C, 0x216C0803,
+		0x81C, 0x016E0803,
+		0x81C, 0x01700803,
+		0x81C, 0x01720803,
+		0x81C, 0x01740803,
+		0x81C, 0x01760803,
+		0x81C, 0x01780803,
+		0x81C, 0x017A0803,
+		0x81C, 0x017C0803,
+		0x81C, 0x017E0803,
+	0x90001005,	0x00000000,	0x40000000,	0x00000000,
+		0x81C, 0xFB000003,
+		0x81C, 0xFA020003,
+		0x81C, 0xF9040003,
+		0x81C, 0xF8060003,
+		0x81C, 0xF7080003,
+		0x81C, 0xF60A0003,
+		0x81C, 0xF50C0003,
+		0x81C, 0xF40E0003,
+		0x81C, 0xF3100003,
+		0x81C, 0xF2120003,
+		0x81C, 0xF1140003,
+		0x81C, 0xF0160003,
+		0x81C, 0xEF180003,
+		0x81C, 0xEE1A0003,
+		0x81C, 0xED1C0003,
+		0x81C, 0xEC1E0003,
+		0x81C, 0xEB200003,
+		0x81C, 0xEA220003,
+		0x81C, 0xE9240003,
+		0x81C, 0xE8260003,
+		0x81C, 0xE7280003,
+		0x81C, 0xE62A0003,
+		0x81C, 0xE52C0003,
+		0x81C, 0xE42E0003,
+		0x81C, 0xE3300003,
+		0x81C, 0xE2320003,
+		0x81C, 0xE1340003,
+		0x81C, 0xC4360003,
+		0x81C, 0xC3380003,
+		0x81C, 0xC23A0003,
+		0x81C, 0xC13C0003,
+		0x81C, 0x883E0003,
+		0x81C, 0x87400003,
+		0x81C, 0x86420003,
+		0x81C, 0x85440003,
+		0x81C, 0x84460003,
+		0x81C, 0x83480003,
+		0x81C, 0x824A0003,
+		0x81C, 0x814C0003,
+		0x81C, 0x804E0003,
+		0x81C, 0x64500003,
+		0x81C, 0x63520003,
+		0x81C, 0x62540003,
+		0x81C, 0x61560003,
+		0x81C, 0x60580003,
+		0x81C, 0x475A0003,
+		0x81C, 0x465C0003,
+		0x81C, 0x455E0003,
+		0x81C, 0x44600003,
+		0x81C, 0x43620003,
+		0x81C, 0x42640003,
+		0x81C, 0x41660003,
+		0x81C, 0x40680003,
+		0x81C, 0x236A0003,
+		0x81C, 0x226C0003,
+		0x81C, 0x056E0003,
+		0x81C, 0x04700003,
+		0x81C, 0x03720003,
+		0x81C, 0x02740003,
+		0x81C, 0x01760003,
+		0x81C, 0x01780003,
+		0x81C, 0x017A0003,
+		0x81C, 0x017C0003,
+		0x81C, 0x017E0003,
+		0x81C, 0xFF000803,
+		0x81C, 0xFE020803,
+		0x81C, 0xFD040803,
+		0x81C, 0xFC060803,
+		0x81C, 0xFB080803,
+		0x81C, 0xFA0A0803,
+		0x81C, 0xF90C0803,
+		0x81C, 0xF80E0803,
+		0x81C, 0xF7100803,
+		0x81C, 0xF6120803,
+		0x81C, 0xF5140803,
+		0x81C, 0xF4160803,
+		0x81C, 0xF3180803,
+		0x81C, 0xF21A0803,
+		0x81C, 0xF11C0803,
+		0x81C, 0xF01E0803,
+		0x81C, 0xB7200803,
+		0x81C, 0xB6220803,
+		0x81C, 0xB5240803,
+		0x81C, 0xB4260803,
+		0x81C, 0xB3280803,
+		0x81C, 0xB22A0803,
+		0x81C, 0xB12C0803,
+		0x81C, 0xAF2E0803,
+		0x81C, 0xAE300803,
+		0x81C, 0xAD320803,
+		0x81C, 0xAC340803,
+		0x81C, 0xAB360803,
+		0x81C, 0xAA380803,
+		0x81C, 0xA93A0803,
+		0x81C, 0xA83C0803,
+		0x81C, 0xA73E0803,
+		0x81C, 0x88400803,
+		0x81C, 0x87420803,
+		0x81C, 0x86440803,
+		0x81C, 0x85460803,
+		0x81C, 0x84480803,
+		0x81C, 0x834A0803,
+		0x81C, 0x674C0803,
+		0x81C, 0x664E0803,
+		0x81C, 0x65500803,
+		0x81C, 0x64520803,
+		0x81C, 0x63540803,
+		0x81C, 0x62560803,
+		0x81C, 0x61580803,
+		0x81C, 0x455A0803,
+		0x81C, 0x445C0803,
+		0x81C, 0x435E0803,
+		0x81C, 0x42600803,
+		0x81C, 0x41620803,
+		0x81C, 0x25640803,
+		0x81C, 0x24660803,
+		0x81C, 0x23680803,
+		0x81C, 0x226A0803,
+		0x81C, 0x216C0803,
+		0x81C, 0x016E0803,
+		0x81C, 0x01700803,
+		0x81C, 0x01720803,
+		0x81C, 0x01740803,
+		0x81C, 0x01760803,
+		0x81C, 0x01780803,
+		0x81C, 0x017A0803,
+		0x81C, 0x017C0803,
+		0x81C, 0x017E0803,
+	0xA0000000,	0x00000000,
+		0x81C, 0xFB000003,
+		0x81C, 0xFA020003,
+		0x81C, 0xF9040003,
+		0x81C, 0xF8060003,
+		0x81C, 0xF7080003,
+		0x81C, 0xF60A0003,
+		0x81C, 0xF50C0003,
+		0x81C, 0xF40E0003,
+		0x81C, 0xF3100003,
+		0x81C, 0xF2120003,
+		0x81C, 0xF1140003,
+		0x81C, 0xF0160003,
+		0x81C, 0xEF180003,
+		0x81C, 0xEE1A0003,
+		0x81C, 0xED1C0003,
+		0x81C, 0xEC1E0003,
+		0x81C, 0xEB200003,
+		0x81C, 0xEA220003,
+		0x81C, 0xE9240003,
+		0x81C, 0xE8260003,
+		0x81C, 0xE7280003,
+		0x81C, 0xE62A0003,
+		0x81C, 0xCA2C0003,
+		0x81C, 0xC92E0003,
+		0x81C, 0xC8300003,
+		0x81C, 0xC7320003,
+		0x81C, 0xC6340003,
+		0x81C, 0xC5360003,
+		0x81C, 0xC4380003,
+		0x81C, 0xC33A0003,
+		0x81C, 0xC23C0003,
+		0x81C, 0xC13E0003,
+		0x81C, 0x88400003,
+		0x81C, 0x87420003,
+		0x81C, 0x86440003,
+		0x81C, 0x85460003,
+		0x81C, 0x84480003,
+		0x81C, 0x834A0003,
+		0x81C, 0x674C0003,
+		0x81C, 0x664E0003,
+		0x81C, 0x65500003,
+		0x81C, 0x64520003,
+		0x81C, 0x63540003,
+		0x81C, 0x62560003,
+		0x81C, 0x61580003,
+		0x81C, 0x455A0003,
+		0x81C, 0x445C0003,
+		0x81C, 0x435E0003,
+		0x81C, 0x42600003,
+		0x81C, 0x41620003,
+		0x81C, 0x25640003,
+		0x81C, 0x24660003,
+		0x81C, 0x23680003,
+		0x81C, 0x226A0003,
+		0x81C, 0x216C0003,
+		0x81C, 0x016E0003,
+		0x81C, 0x01700003,
+		0x81C, 0x01720003,
+		0x81C, 0x01740003,
+		0x81C, 0x01760003,
+		0x81C, 0x01780003,
+		0x81C, 0x017A0003,
+		0x81C, 0x017C0003,
+		0x81C, 0x017E0003,
+		0x81C, 0xFF000803,
+		0x81C, 0xFE020803,
+		0x81C, 0xFD040803,
+		0x81C, 0xFC060803,
+		0x81C, 0xFB080803,
+		0x81C, 0xFA0A0803,
+		0x81C, 0xF90C0803,
+		0x81C, 0xF80E0803,
+		0x81C, 0xF7100803,
+		0x81C, 0xF6120803,
+		0x81C, 0xF5140803,
+		0x81C, 0xF4160803,
+		0x81C, 0xF3180803,
+		0x81C, 0xF21A0803,
+		0x81C, 0xF11C0803,
+		0x81C, 0xF01E0803,
+		0x81C, 0xB7200803,
+		0x81C, 0xB6220803,
+		0x81C, 0xB5240803,
+		0x81C, 0xB4260803,
+		0x81C, 0xB3280803,
+		0x81C, 0xB22A0803,
+		0x81C, 0xB12C0803,
+		0x81C, 0xAF2E0803,
+		0x81C, 0xAE300803,
+		0x81C, 0xAD320803,
+		0x81C, 0xAC340803,
+		0x81C, 0xAB360803,
+		0x81C, 0xAA380803,
+		0x81C, 0xA93A0803,
+		0x81C, 0xA83C0803,
+		0x81C, 0xA73E0803,
+		0x81C, 0x88400803,
+		0x81C, 0x87420803,
+		0x81C, 0x86440803,
+		0x81C, 0x85460803,
+		0x81C, 0x84480803,
+		0x81C, 0x834A0803,
+		0x81C, 0x674C0803,
+		0x81C, 0x664E0803,
+		0x81C, 0x65500803,
+		0x81C, 0x64520803,
+		0x81C, 0x63540803,
+		0x81C, 0x62560803,
+		0x81C, 0x61580803,
+		0x81C, 0x455A0803,
+		0x81C, 0x445C0803,
+		0x81C, 0x435E0803,
+		0x81C, 0x42600803,
+		0x81C, 0x41620803,
+		0x81C, 0x25640803,
+		0x81C, 0x24660803,
+		0x81C, 0x23680803,
+		0x81C, 0x226A0803,
+		0x81C, 0x216C0803,
+		0x81C, 0x016E0803,
+		0x81C, 0x01700803,
+		0x81C, 0x01720803,
+		0x81C, 0x01740803,
+		0x81C, 0x01760803,
+		0x81C, 0x01780803,
+		0x81C, 0x017A0803,
+		0x81C, 0x017C0803,
+		0x81C, 0x017E0803,
+	0xB0000000,	0x00000000,
+};
+
+u32 array_mp_8821c_agc_tab_diff_btg[] = {
+	0x80001004,	0x00000000,	0x40000000,	0x00000000,
+		0x81C, 0xFF000013,
+		0x81C, 0xFE020013,
+		0x81C, 0xFD040013,
+		0x81C, 0xFC060013,
+		0x81C, 0xFB080013,
+		0x81C, 0xFA0A0013,
+		0x81C, 0xF90C0013,
+		0x81C, 0xF80E0013,
+		0x81C, 0xF7100013,
+		0x81C, 0xF6120013,
+		0x81C, 0xF5140013,
+		0x81C, 0xF4160013,
+		0x81C, 0xF3180013,
+		0x81C, 0xF21A0013,
+		0x81C, 0xF11C0013,
+		0x81C, 0xF01E0013,
+		0x81C, 0xEF200013,
+		0x81C, 0xEE220013,
+		0x81C, 0xED240013,
+		0x81C, 0xEC260013,
+		0x81C, 0xEB280013,
+		0x81C, 0xEA2A0013,
+		0x81C, 0xE92C0013,
+		0x81C, 0xE82E0013,
+		0x81C, 0xE7300013,
+		0x81C, 0x8B320013,
+		0x81C, 0x8A340013,
+		0x81C, 0x89360013,
+		0x81C, 0x88380013,
+		0x81C, 0x873A0013,
+		0x81C, 0x863C0013,
+		0x81C, 0x853E0013,
+		0x81C, 0x84400013,
+		0x81C, 0x83420013,
+		0x81C, 0x82440013,
+		0x81C, 0x81460013,
+		0x81C, 0x08480013,
+		0x81C, 0x074A0013,
+		0x81C, 0x064C0013,
+		0x81C, 0x054E0013,
+		0x81C, 0x04500013,
+		0x81C, 0x03520013,
+		0x81C, 0x88540003,
+		0x81C, 0x87560003,
+		0x81C, 0x86580003,
+		0x81C, 0x855A0003,
+		0x81C, 0x845C0003,
+		0x81C, 0x835E0003,
+		0x81C, 0x82600003,
+		0x81C, 0x81620003,
+		0x81C, 0x07640003,
+		0x81C, 0x06660003,
+		0x81C, 0x05680003,
+		0x81C, 0x046A0003,
+		0x81C, 0x036C0003,
+		0x81C, 0x026E0003,
+		0x81C, 0x01700003,
+		0x81C, 0x01720003,
+		0x81C, 0x01740003,
+		0x81C, 0x01760003,
+		0x81C, 0x01780003,
+		0x81C, 0x017A0003,
+		0x81C, 0x017C0003,
+		0x81C, 0x017E0003,
+		0x81C, 0xFF000813,
+		0x81C, 0xFE020813,
+		0x81C, 0xFD040813,
+		0x81C, 0xFC060813,
+		0x81C, 0xFB080813,
+		0x81C, 0xFA0A0813,
+		0x81C, 0xF90C0813,
+		0x81C, 0xF80E0813,
+		0x81C, 0xF7100813,
+		0x81C, 0xF6120813,
+		0x81C, 0xF5140813,
+		0x81C, 0xF4160813,
+		0x81C, 0xF3180813,
+		0x81C, 0xF21A0813,
+		0x81C, 0xF11C0813,
+		0x81C, 0x941E0813,
+		0x81C, 0x93200813,
+		0x81C, 0x92220813,
+		0x81C, 0x91240813,
+		0x81C, 0x90260813,
+		0x81C, 0x8F280813,
+		0x81C, 0x8E2A0813,
+		0x81C, 0x8D2C0813,
+		0x81C, 0x8C2E0813,
+		0x81C, 0x8B300813,
+		0x81C, 0x8A320813,
+		0x81C, 0x89340813,
+		0x81C, 0x88360813,
+		0x81C, 0x87380813,
+		0x81C, 0x863A0813,
+		0x81C, 0x853C0813,
+		0x81C, 0x843E0813,
+		0x81C, 0x83400813,
+		0x81C, 0x82420813,
+		0x81C, 0x81440813,
+		0x81C, 0x07460813,
+		0x81C, 0x06480813,
+		0x81C, 0x054A0813,
+		0x81C, 0x044C0813,
+		0x81C, 0x034E0813,
+		0x81C, 0x02500813,
+		0x81C, 0x01520813,
+		0x81C, 0x88540803,
+		0x81C, 0x87560803,
+		0x81C, 0x86580803,
+		0x81C, 0x855A0803,
+		0x81C, 0x845C0803,
+		0x81C, 0x835E0803,
+		0x81C, 0x82600803,
+		0x81C, 0x81620803,
+		0x81C, 0x07640803,
+		0x81C, 0x06660803,
+		0x81C, 0x05680803,
+		0x81C, 0x046A0803,
+		0x81C, 0x036C0803,
+		0x81C, 0x026E0803,
+		0x81C, 0x01700803,
+		0x81C, 0x01720803,
+		0x81C, 0x01740803,
+		0x81C, 0x01760803,
+		0x81C, 0x01780803,
+		0x81C, 0x017A0803,
+		0x81C, 0x017C0803,
+		0x81C, 0x017E0803,
+	0x90001005,	0x00000000,	0x40000000,	0x00000000,
+		0x81C, 0xFF000013,
+		0x81C, 0xFE020013,
+		0x81C, 0xFD040013,
+		0x81C, 0xFC060013,
+		0x81C, 0xFB080013,
+		0x81C, 0xFA0A0013,
+		0x81C, 0xF90C0013,
+		0x81C, 0xF80E0013,
+		0x81C, 0xF7100013,
+		0x81C, 0xF6120013,
+		0x81C, 0xF5140013,
+		0x81C, 0xF4160013,
+		0x81C, 0xF3180013,
+		0x81C, 0xF21A0013,
+		0x81C, 0xF11C0013,
+		0x81C, 0xF01E0013,
+		0x81C, 0xEF200013,
+		0x81C, 0xEE220013,
+		0x81C, 0xED240013,
+		0x81C, 0xEC260013,
+		0x81C, 0xEB280013,
+		0x81C, 0xEA2A0013,
+		0x81C, 0xE92C0013,
+		0x81C, 0xE82E0013,
+		0x81C, 0xE7300013,
+		0x81C, 0x8B320013,
+		0x81C, 0x8A340013,
+		0x81C, 0x89360013,
+		0x81C, 0x88380013,
+		0x81C, 0x873A0013,
+		0x81C, 0x863C0013,
+		0x81C, 0x853E0013,
+		0x81C, 0x84400013,
+		0x81C, 0x83420013,
+		0x81C, 0x82440013,
+		0x81C, 0x81460013,
+		0x81C, 0x08480013,
+		0x81C, 0x074A0013,
+		0x81C, 0x064C0013,
+		0x81C, 0x054E0013,
+		0x81C, 0x04500013,
+		0x81C, 0x03520013,
+		0x81C, 0x88540003,
+		0x81C, 0x87560003,
+		0x81C, 0x86580003,
+		0x81C, 0x855A0003,
+		0x81C, 0x845C0003,
+		0x81C, 0x835E0003,
+		0x81C, 0x82600003,
+		0x81C, 0x81620003,
+		0x81C, 0x07640003,
+		0x81C, 0x06660003,
+		0x81C, 0x05680003,
+		0x81C, 0x046A0003,
+		0x81C, 0x036C0003,
+		0x81C, 0x026E0003,
+		0x81C, 0x01700003,
+		0x81C, 0x01720003,
+		0x81C, 0x01740003,
+		0x81C, 0x01760003,
+		0x81C, 0x01780003,
+		0x81C, 0x017A0003,
+		0x81C, 0x017C0003,
+		0x81C, 0x017E0003,
+		0x81C, 0xFF000813,
+		0x81C, 0xFE020813,
+		0x81C, 0xFD040813,
+		0x81C, 0xFC060813,
+		0x81C, 0xFB080813,
+		0x81C, 0xFA0A0813,
+		0x81C, 0xF90C0813,
+		0x81C, 0xF80E0813,
+		0x81C, 0xF7100813,
+		0x81C, 0xF6120813,
+		0x81C, 0xF5140813,
+		0x81C, 0xF4160813,
+		0x81C, 0xF3180813,
+		0x81C, 0xF21A0813,
+		0x81C, 0xF11C0813,
+		0x81C, 0x941E0813,
+		0x81C, 0x93200813,
+		0x81C, 0x92220813,
+		0x81C, 0x91240813,
+		0x81C, 0x90260813,
+		0x81C, 0x8F280813,
+		0x81C, 0x8E2A0813,
+		0x81C, 0x8D2C0813,
+		0x81C, 0x8C2E0813,
+		0x81C, 0x8B300813,
+		0x81C, 0x8A320813,
+		0x81C, 0x89340813,
+		0x81C, 0x88360813,
+		0x81C, 0x87380813,
+		0x81C, 0x863A0813,
+		0x81C, 0x853C0813,
+		0x81C, 0x843E0813,
+		0x81C, 0x83400813,
+		0x81C, 0x82420813,
+		0x81C, 0x81440813,
+		0x81C, 0x07460813,
+		0x81C, 0x06480813,
+		0x81C, 0x054A0813,
+		0x81C, 0x044C0813,
+		0x81C, 0x034E0813,
+		0x81C, 0x02500813,
+		0x81C, 0x01520813,
+		0x81C, 0x88540803,
+		0x81C, 0x87560803,
+		0x81C, 0x86580803,
+		0x81C, 0x855A0803,
+		0x81C, 0x845C0803,
+		0x81C, 0x835E0803,
+		0x81C, 0x82600803,
+		0x81C, 0x81620803,
+		0x81C, 0x07640803,
+		0x81C, 0x06660803,
+		0x81C, 0x05680803,
+		0x81C, 0x046A0803,
+		0x81C, 0x036C0803,
+		0x81C, 0x026E0803,
+		0x81C, 0x01700803,
+		0x81C, 0x01720803,
+		0x81C, 0x01740803,
+		0x81C, 0x01760803,
+		0x81C, 0x01780803,
+		0x81C, 0x017A0803,
+		0x81C, 0x017C0803,
+		0x81C, 0x017E0803,
+	0xA0000000,	0x00000000,
+		0x81C, 0xFF000013,
+		0x81C, 0xFE020013,
+		0x81C, 0xFD040013,
+		0x81C, 0xFC060013,
+		0x81C, 0xFB080013,
+		0x81C, 0xFA0A0013,
+		0x81C, 0xF90C0013,
+		0x81C, 0xF80E0013,
+		0x81C, 0xF7100013,
+		0x81C, 0xF6120013,
+		0x81C, 0xF5140013,
+		0x81C, 0xF4160013,
+		0x81C, 0xF3180013,
+		0x81C, 0xF21A0013,
+		0x81C, 0xF11C0013,
+		0x81C, 0xF01E0013,
+		0x81C, 0xEF200013,
+		0x81C, 0xEE220013,
+		0x81C, 0xED240013,
+		0x81C, 0xEC260013,
+		0x81C, 0xEB280013,
+		0x81C, 0xEA2A0013,
+		0x81C, 0xE92C0013,
+		0x81C, 0xE82E0013,
+		0x81C, 0xE7300013,
+		0x81C, 0x8A320013,
+		0x81C, 0x89340013,
+		0x81C, 0x88360013,
+		0x81C, 0x87380013,
+		0x81C, 0x863A0013,
+		0x81C, 0x853C0013,
+		0x81C, 0x843E0013,
+		0x81C, 0x83400013,
+		0x81C, 0x82420013,
+		0x81C, 0x81440013,
+		0x81C, 0x07460013,
+		0x81C, 0x06480013,
+		0x81C, 0x054A0013,
+		0x81C, 0x044C0013,
+		0x81C, 0x034E0013,
+		0x81C, 0x02500013,
+		0x81C, 0x01520013,
+		0x81C, 0x88540003,
+		0x81C, 0x87560003,
+		0x81C, 0x86580003,
+		0x81C, 0x855A0003,
+		0x81C, 0x845C0003,
+		0x81C, 0x835E0003,
+		0x81C, 0x82600003,
+		0x81C, 0x81620003,
+		0x81C, 0x07640003,
+		0x81C, 0x06660003,
+		0x81C, 0x05680003,
+		0x81C, 0x046A0003,
+		0x81C, 0x036C0003,
+		0x81C, 0x026E0003,
+		0x81C, 0x01700003,
+		0x81C, 0x01720003,
+		0x81C, 0x01740003,
+		0x81C, 0x01760003,
+		0x81C, 0x01780003,
+		0x81C, 0x017A0003,
+		0x81C, 0x017C0003,
+		0x81C, 0x017E0003,
+		0x81C, 0xFF000813,
+		0x81C, 0xFE020813,
+		0x81C, 0xFD040813,
+		0x81C, 0xFC060813,
+		0x81C, 0xFB080813,
+		0x81C, 0xFA0A0813,
+		0x81C, 0xF90C0813,
+		0x81C, 0xF80E0813,
+		0x81C, 0xF7100813,
+		0x81C, 0xF6120813,
+		0x81C, 0xF5140813,
+		0x81C, 0xF4160813,
+		0x81C, 0xF3180813,
+		0x81C, 0xF21A0813,
+		0x81C, 0xF11C0813,
+		0x81C, 0x961E0813,
+		0x81C, 0x95200813,
+		0x81C, 0x94220813,
+		0x81C, 0x93240813,
+		0x81C, 0x92260813,
+		0x81C, 0x91280813,
+		0x81C, 0x8F2A0813,
+		0x81C, 0x8E2C0813,
+		0x81C, 0x8D2E0813,
+		0x81C, 0x8C300813,
+		0x81C, 0x8B320813,
+		0x81C, 0x8A340813,
+		0x81C, 0x89360813,
+		0x81C, 0x88380813,
+		0x81C, 0x873A0813,
+		0x81C, 0x863C0813,
+		0x81C, 0x853E0813,
+		0x81C, 0x84400813,
+		0x81C, 0x83420813,
+		0x81C, 0x82440813,
+		0x81C, 0x08460813,
+		0x81C, 0x07480813,
+		0x81C, 0x064A0813,
+		0x81C, 0x054C0813,
+		0x81C, 0x044E0813,
+		0x81C, 0x03500813,
+		0x81C, 0x02520813,
+		0x81C, 0x89540803,
+		0x81C, 0x88560803,
+		0x81C, 0x87580803,
+		0x81C, 0x865A0803,
+		0x81C, 0x855C0803,
+		0x81C, 0x845E0803,
+		0x81C, 0x83600803,
+		0x81C, 0x82620803,
+		0x81C, 0x07640803,
+		0x81C, 0x06660803,
+		0x81C, 0x05680803,
+		0x81C, 0x046A0803,
+		0x81C, 0x036C0803,
+		0x81C, 0x026E0803,
+		0x81C, 0x01700803,
+		0x81C, 0x01720803,
+		0x81C, 0x01740803,
+		0x81C, 0x01760803,
+		0x81C, 0x01780803,
+		0x81C, 0x017A0803,
+		0x81C, 0x017C0803,
+		0x81C, 0x017E0803,
+	0xB0000000,	0x00000000,
+};
+
+void
+odm_read_and_config_mp_8821c_agc_tab_diff(struct dm_struct *dm, u32 array[],
+					  u32 array_len)
+{
+	u32	i = 0;
+	u8	c_cond;
+	boolean	is_matched = true, is_skipped = false;
+
+	u32	v1 = 0, v2 = 0, pre_v1 = 0, pre_v2 = 0;
+
+	PHYDM_DBG(dm, ODM_COMP_INIT, "===> %s\n", __func__);
+
+	while ((i + 1) < array_len) {
+		v1 = array[i];
+		v2 = array[i + 1];
+
+		if (v1 & (BIT(31) | BIT(30))) {/*positive & negative condition*/
+			if (v1 & BIT(31)) {/* positive condition*/
+				c_cond  = (u8)((v1 & (BIT(29) | BIT(28))) >> 28);
+				if (c_cond == COND_ENDIF) {/*end*/
+					is_matched = true;
+					is_skipped = false;
+					PHYDM_DBG(dm, ODM_COMP_INIT, "ENDIF\n");
+				} else if (c_cond == COND_ELSE) { /*else*/
+					is_matched = is_skipped ? false : true;
+					PHYDM_DBG(dm, ODM_COMP_INIT, "ELSE\n");
+				} else {/*if , else if*/
+					pre_v1 = v1;
+					pre_v2 = v2;
+					PHYDM_DBG(dm, ODM_COMP_INIT, "IF or ELSE IF\n");
+				}
+			} else if (v1 & BIT(30)) { /*negative condition*/
+				if (is_skipped == false) {
+					if (check_positive(dm, pre_v1, pre_v2, v1, v2)) {
+						is_matched = true;
+						is_skipped = true;
+					} else {
+						is_matched = false;
+						is_skipped = false;
+					}
+				} else
+					is_matched = false;
+			}
+		} else {
+			if (is_matched)
+				odm_config_bb_agc_8821c(dm, v1, MASKDWORD, v2);
+		}
+		i = i + 2;
+	}
+}
+
+u32
+odm_get_version_mp_8821c_agc_tab_diff(void)
+{
+		return 49;
+}
+
+/******************************************************************************
+*                           phy_reg.TXT
+******************************************************************************/
+
+u32 array_mp_8821c_phy_reg[] = {
+		0x800, 0x9020D010,
+		0x804, 0x80018180,
+		0x808, 0x04028211,
+		0x80C, 0x13D10011,
+		0x810, 0x21104255,
+		0x814, 0x020C3D10,
+		0x818, 0x84A10385,
+		0x81C, 0x1E1E081F,
+		0x820, 0x0001AAAA,
+		0x824, 0x00030FE0,
+		0x828, 0x0000CCCC,
+		0x82C, 0x75CB7010,
+		0x830, 0x79A0EAAA,
+		0x834, 0x072E698A,
+		0x838, 0x87766461,
+		0x83C, 0x9194B2B6,
+		0x840, 0x171740E0,
+		0x844, 0x4D3D7CDB,
+		0x848, 0x4AD0408B,
+		0x84C, 0x6AFBF7A5,
+		0x850, 0x28A74706,
+		0x854, 0x0001520C,
+		0x858, 0x4060C000,
+		0x85C, 0x74010160,
+		0x860, 0x68A7C321,
+		0x864, 0x79F27432,
+		0x868, 0x8CA7A314,
+		0x86C, 0x558C2878,
+		0x870, 0x55555555,
+		0x874, 0x27612C2E,
+		0x878, 0xC0003152,
+		0x87C, 0x5C8FC000,
+		0x880, 0x00000000,
+		0x884, 0x00000000,
+		0x888, 0x00000000,
+		0x88C, 0x00000000,
+		0x890, 0x00000000,
+		0x894, 0x00000000,
+		0x898, 0x00000000,
+		0x89C, 0x00000000,
+		0x8A0, 0x00000013,
+		0x8A4, 0x7F7F7F7F,
+		0x8A8, 0x2202033E,
+		0x8AC, 0xF00F000A,
+		0x8B0, 0x00000600,
+		0x8B4, 0x000FC080,
+		0x8B8, 0xEC0057FF,
+		0x8BC, 0x2CB520A3,
+		0x8C0, 0xFFE04020,
+		0x8C4, 0x47C00000,
+		0x8C8, 0x00025165,
+		0x8CC, 0x08108492,
+		0x8D0, 0x0000B800,
+		0x8D4, 0x860308A0,
+		0x8D8, 0x290B5612,
+		0x8DC, 0x00000000,
+		0x8E0, 0x32D16777,
+		0x8E4, 0x49092925,
+		0x8E8, 0xFFFFC42C,
+		0x8EC, 0x99999999,
+		0x8F0, 0x00009999,
+		0x8F4, 0x00D80FA1,
+		0x8F8, 0x400000C0,
+		0x8FC, 0x00000130,
+		0x900, 0x00C00000,
+		0x904, 0x0FFF0FFF,
+		0x908, 0x00000000,
+		0x90C, 0x13000000,
+		0x910, 0x0000FC00,
+		0x914, 0xC6380000,
+		0x918, 0x1C1028C0,
+		0x91C, 0x64B11A1C,
+		0x920, 0xE0767233,
+		0x924, 0x855A2500,
+		0x928, 0x4AB0E4E4,
+		0x92C, 0xFFFEB200,
+		0x930, 0xFFFFFFFE,
+		0x934, 0x001FFFFF,
+		0x938, 0x00008480,
+		0x93C, 0xE41C0642,
+		0x940, 0x0E470430,
+		0x944, 0x00000000,
+		0x948, 0xAC000000,
+		0x94C, 0x10000083,
+		0x950, 0xB2010080,
+		0x954, 0x86510080,
+		0x958, 0x00000181,
+		0x95C, 0x04248000,
+		0x960, 0x00000000,
+		0x964, 0x00000000,
+		0x968, 0x00000000,
+		0x96C, 0x00000000,
+		0x970, 0x00001FFF,
+		0x974, 0x04000FFF,
+		0x978, 0x00000000,
+		0x97C, 0x00000000,
+		0x980, 0x00000000,
+		0x984, 0x00000000,
+		0x988, 0x00000000,
+		0x98C, 0x23440000,
+		0x990, 0x27100000,
+		0x994, 0xFFFF0100,
+		0x998, 0xFFFFFF5C,
+		0x99C, 0xFFFFFFFF,
+		0x9A0, 0x000000FF,
+		0x9A4, 0x80000088,
+		0x9A8, 0x0C2F0000,
+		0x9AC, 0x01560000,
+		0x9B0, 0x70000000,
+		0x9B4, 0x00000000,
+		0x9B8, 0x00000000,
+		0x9BC, 0x00000000,
+		0x9C0, 0x00000000,
+		0x9C4, 0x00000000,
+		0x9C8, 0x00000000,
+		0x9CC, 0x00000000,
+		0x9D0, 0x00000000,
+		0x9D4, 0x00000000,
+		0x9D8, 0x00000000,
+		0x9DC, 0x00000000,
+		0x9E0, 0x00000000,
+		0x9E4, 0x02000402,
+		0x9E8, 0x000022D4,
+		0x9EC, 0x00000000,
+		0x9F0, 0x00000000,
+		0x9F4, 0x00000000,
+		0x9F8, 0x00000000,
+		0x9FC, 0xEFFFF7FF,
+		0xA00, 0x00D040C8,
+		0xA04, 0x80FF800C,
+		0xA08, 0x9C838300,
+		0xA0C, 0x297E000F,
+		0xA10, 0x9500BB78,
+		0xA14, 0x1114D028,
+		0xA18, 0x00881117,
+		0xA1C, 0x89140F00,
+		0xA20, 0xE82C0000,
+		0xA24, 0x64B80C1C,
+		0xA28, 0x00008810,
+		0xA2C, 0x00D20000,
+		0xA70, 0x101FBF00,
+		0xA74, 0x00000107,
+		0xA78, 0x00008900,
+		0xA7C, 0x225B0606,
+		0xA80, 0x21807532,
+		0xA84, 0x80120000,
+		0xA88, 0x048C0000,
+		0xA8C, 0x12345678,
+		0xA90, 0xABCDEF00,
+		0xA94, 0x001B1B89,
+		0xA98, 0x00000000,
+		0xA9C, 0x3F000000,
+		0xAA0, 0x00000000,
+		0xAA4, 0x00080000,
+		0xAA8, 0xEACF0004,
+		0xAAC, 0x01235667,
+		0xAB0, 0x00000000,
+		0xB00, 0xE1000440,
+		0xB04, 0x00800000,
+		0xB08, 0xFF02030B,
+		0xB0C, 0x01EAA406,
+		0xB10, 0x00030690,
+		0xB14, 0x006000FA,
+		0xB18, 0x00000002,
+		0xB1C, 0x00000002,
+		0xB20, 0x4B00001F,
+		0xB24, 0x4E8E3E40,
+		0xB28, 0x03020100,
+		0xB2C, 0x07060504,
+		0xB30, 0x0B0A0908,
+		0xB34, 0x0F0E0D0C,
+		0xB38, 0x13121110,
+		0xB3C, 0x0000003A,
+		0xB40, 0x00000000,
+		0xB44, 0x80000000,
+		0xB48, 0x3F0000FA,
+		0xB4C, 0x88C80020,
+		0xB50, 0x00000000,
+		0xB54, 0x00004241,
+		0xB58, 0xE0008208,
+		0xB5C, 0x41EFFFF9,
+		0xB60, 0x00000000,
+		0xB64, 0x00200063,
+		0xB68, 0x0000003A,
+		0xB6C, 0x00000102,
+		0xB70, 0x4E6D1870,
+		0xB74, 0x03020100,
+		0xB78, 0x07060504,
+		0xB7C, 0x0B0A0908,
+		0xB80, 0x0F0E0D0C,
+		0xB84, 0x13121110,
+		0xB88, 0x00000000,
+		0xB8C, 0x00000000,
+		0xC00, 0x00000007,
+		0xC04, 0x03010020,
+		0xC08, 0x60403231,
+		0xC0C, 0x00012345,
+		0xC10, 0x00000100,
+		0xC14, 0x01000000,
+		0xC18, 0x00000000,
+		0xC1C, 0x40040053,
+		0xC20, 0x400503A3,
+		0xC24, 0x00000000,
+		0xC28, 0x00000000,
+		0xC2C, 0x00000000,
+		0xC30, 0x00000000,
+		0xC34, 0x00000000,
+		0xC38, 0x00000000,
+		0xC3C, 0x00000000,
+		0xC40, 0x00000000,
+		0xC44, 0x00000000,
+		0xC48, 0x00000000,
+		0xC4C, 0x00000000,
+		0xC50, 0x00000020,
+		0xC54, 0x00000000,
+		0xC58, 0xD8020402,
+		0xC5C, 0xDE000120,
+		0xC68, 0x0000003F,
+		0xC6C, 0x0000122A,
+		0xC70, 0x00000000,
+		0xC74, 0x00000000,
+		0xC78, 0x00000000,
+		0xC7C, 0x00000000,
+		0xC80, 0x00000000,
+		0xC84, 0x00000000,
+		0xC88, 0x00000000,
+		0xC8C, 0x07000000,
+		0xC94, 0x01000100,
+		0xC98, 0x201C8000,
+		0xC9C, 0x00000000,
+		0xCA0, 0x0000A555,
+		0xCA4, 0x08040201,
+		0xCA8, 0x80402010,
+		0xCAC, 0x00000000,
+	0x80001005,	0x00000000,	0x40000000,	0x00000000,
+		0xCB0, 0x77777717,
+		0xCB4, 0x00000073,
+	0xA0000000,	0x00000000,
+		0xCB0, 0x77775747,
+		0xCB4, 0x10000077,
+	0xB0000000,	0x00000000,
+		0xCB8, 0x00000000,
+		0xCBC, 0x00000000,
+		0xCC0, 0x00000000,
+		0xCC4, 0x00000000,
+		0xCC8, 0x00000000,
+		0xCCC, 0x00000000,
+		0xCD0, 0x00000000,
+		0xCD4, 0x00000000,
+		0xCD8, 0x00000000,
+		0xCDC, 0x00000000,
+		0xCE0, 0x00000000,
+		0xCE4, 0x00000000,
+		0xCE8, 0x00000000,
+		0xCEC, 0x00000000,
+		0xE00, 0x00000007,
+		0xE04, 0x00000020,
+		0xE08, 0x60403231,
+		0xE0C, 0x00012345,
+		0xE10, 0x00000100,
+		0xE14, 0x01000000,
+		0xE18, 0x00000000,
+		0xE1C, 0x40040053,
+		0xE20, 0x00020103,
+		0xE24, 0x00000000,
+		0xE28, 0x00000000,
+		0xE2C, 0x00000000,
+		0xE30, 0x00000000,
+		0xE34, 0x00000000,
+		0xE38, 0x00000000,
+		0xE3C, 0x00000000,
+		0xE40, 0x00000000,
+		0xE44, 0x00000000,
+		0xE48, 0x00000000,
+		0xE4C, 0x00000000,
+		0xE50, 0x00000020,
+		0xE54, 0x00000000,
+		0xE58, 0xD8020402,
+		0xE5C, 0xDE000120,
+		0xE68, 0x59799979,
+		0xE6C, 0x0000122A,
+		0xE70, 0x99795979,
+		0xE74, 0x99795979,
+		0xE78, 0x99799979,
+		0xE7C, 0x99791979,
+		0xE80, 0x19791979,
+		0xE84, 0x19791979,
+		0xE88, 0x00000000,
+		0xE8C, 0x07000000,
+		0xE94, 0x01000100,
+		0xE98, 0x201C8000,
+		0xE9C, 0x00000000,
+		0xEA0, 0x0000A555,
+		0xEA4, 0x08040201,
+		0xEA8, 0x80402010,
+		0xEAC, 0x00000000,
+		0xEB0, 0x98543210,
+		0xEB4, 0x000000BA,
+		0xEB8, 0x00000000,
+		0xEBC, 0x00000000,
+		0xEC0, 0x00000000,
+		0xEC4, 0x00000000,
+		0xEC8, 0x00000000,
+		0xECC, 0x00000000,
+		0xED0, 0x00000000,
+		0xED4, 0x00000000,
+		0xED8, 0x00000000,
+		0xEDC, 0x00000000,
+		0xEE0, 0x00000000,
+		0xEE4, 0x00000000,
+		0xEE8, 0x00000000,
+		0xEEC, 0x00000000,
+		0x1900, 0x00000000,
+		0x1904, 0x00238000,
+		0x1908, 0x00000000,
+		0x190C, 0x00000000,
+		0x1910, 0x00001800,
+		0x1914, 0x00000000,
+		0x1918, 0x00000000,
+		0x191C, 0x00000000,
+		0x1920, 0x00000000,
+		0x1924, 0x00000000,
+		0x1928, 0x00000000,
+		0x192C, 0x00000000,
+		0x1930, 0x00000000,
+		0x1934, 0x00000000,
+		0x1938, 0x00000000,
+		0x193C, 0x00000000,
+		0x1940, 0x00000000,
+		0x1944, 0x00000000,
+		0x1948, 0x00000000,
+		0x194C, 0x00000000,
+		0x1950, 0x00000000,
+		0x1954, 0x00000000,
+		0x1958, 0x00000000,
+		0x195C, 0x00000000,
+		0x1960, 0x00000000,
+		0x1964, 0x00000000,
+		0x1968, 0x00000000,
+		0x196C, 0x00000000,
+		0x1970, 0x00000000,
+		0x1974, 0x00000000,
+		0x1978, 0x00000000,
+		0x197C, 0x00000000,
+		0x1980, 0x00000000,
+		0x1984, 0x03000000,
+		0x1988, 0x21401E88,
+		0x198C, 0x00004000,
+		0x1990, 0x00000000,
+		0x1994, 0x00000000,
+		0x1998, 0x00000053,
+		0x199C, 0x00000000,
+		0x19A0, 0x00000000,
+		0x19A4, 0x00000000,
+		0x19A8, 0x010A0000,
+		0x19AC, 0x0E47E47F,
+		0x19B0, 0x00008000,
+		0x19B4, 0x0E47E47F,
+		0x19B8, 0x00000000,
+		0x19BC, 0x00000000,
+		0x19C0, 0x00000000,
+		0x19C4, 0x00000000,
+		0x19C8, 0x00000000,
+		0x19CC, 0x00000000,
+		0x19D0, 0x00000000,
+		0x19D4, 0x77777777,
+		0x19D8, 0x00000777,
+		0x19DC, 0x133E0F37,
+		0x19E0, 0x00000000,
+		0x19E4, 0x00000000,
+		0x19E8, 0x00000000,
+		0x19EC, 0x00000000,
+		0x19F0, 0x00000000,
+		0x19F4, 0x00000000,
+		0x19F8, 0x01A00000,
+		0x19FC, 0x00000000,
+		0x1C00, 0x00000100,
+		0x1C04, 0x01000000,
+		0x1C08, 0x00000100,
+		0x1C0C, 0x01000000,
+		0x1C10, 0x00000100,
+		0x1C14, 0x01000000,
+		0x1C18, 0x00000100,
+		0x1C1C, 0x01000000,
+		0x1C20, 0x00000100,
+		0x1C24, 0x01000000,
+		0x1C28, 0x00000100,
+		0x1C2C, 0x01000000,
+		0x1C30, 0x00000100,
+		0x1C34, 0x01000000,
+		0x1C38, 0x00000000,
+		0x1C3C, 0x00008000,
+		0x1C40, 0x000C0100,
+		0x1C44, 0x000000F3,
+		0x1C48, 0x1A8249A8,
+		0x1C4C, 0x1461C826,
+		0x1C50, 0x0001469E,
+		0x1C54, 0x58D158D1,
+		0x1C58, 0x04490088,
+		0x1C5C, 0x04004400,
+		0x1C60, 0x00000000,
+		0x1C64, 0x04004400,
+		0x1C68, 0x0B7B7B75,
+		0x1C6C, 0x01000000,
+		0x1C70, 0x00A08145,
+		0x1C74, 0x2080E0E0,
+		0x1C78, 0x00000000,
+		0x1C7C, 0x00000010,
+		0x1C80, 0x00000100,
+		0x1C84, 0x01000000,
+		0x1C88, 0x00000100,
+		0x1C8C, 0x01000000,
+		0x1C90, 0x00000100,
+		0x1C94, 0x01000000,
+		0x1C98, 0x00000100,
+		0x1C9C, 0x01000000,
+		0x1CA0, 0x00000100,
+		0x1CA4, 0x01000000,
+		0x1CA8, 0x00000100,
+		0x1CAC, 0x01000000,
+		0x1CB0, 0x00000100,
+		0x1CB4, 0x01000000,
+		0x1CB8, 0x00000000,
+		0x1CBC, 0x00000000,
+		0x1CC0, 0x201B0100,
+		0x1CC4, 0x00308000,
+		0x1CC8, 0x5B74B6E9,
+		0x1CCC, 0x01000000,
+		0x1CD0, 0x00000400,
+		0x1CD4, 0x01000000,
+		0x1CD8, 0x01B8ADEB,
+		0x1CDC, 0x01000000,
+		0x1CE0, 0x00030003,
+		0x1CE4, 0x4E4A0306,
+		0x1CE8, 0x00000100,
+		0x1CEC, 0x01000000,
+		0x1CF0, 0x00000100,
+		0x1CF4, 0x01000000,
+		0x1CF8, 0x01B8ADEB,
+		0x1CFC, 0x00000000,
+		0xC60, 0x700B8040,
+		0xC60, 0x700B8040,
+		0xC60, 0x70146040,
+		0xC60, 0x70246040,
+		0xC60, 0x70346040,
+		0xC60, 0x70446040,
+		0xC60, 0x705B2040,
+		0xC60, 0x70646040,
+		0xC60, 0x707B8040,
+		0xC60, 0x708B8040,
+		0xC60, 0x709B8040,
+		0xC60, 0x70AB8040,
+		0xC60, 0x70BB6040,
+		0xC60, 0x70C06040,
+		0xC60, 0x70D06040,
+		0xC60, 0x70EF6040,
+		0xC60, 0x70F06040,
+		0xE60, 0x700B8040,
+		0xE60, 0x700B8040,
+		0xE60, 0x70146040,
+		0xE60, 0x70246040,
+		0xE60, 0x70346040,
+		0xE60, 0x70446040,
+		0xE60, 0x705B2040,
+		0xE60, 0x70646040,
+		0xE60, 0x707B8040,
+		0xE60, 0x708B8040,
+		0xE60, 0x709B8040,
+		0xE60, 0x70AB8040,
+		0xE60, 0x70BB6040,
+		0xE60, 0x70C06040,
+		0xE60, 0x70D06040,
+		0xE60, 0x70EF6040,
+		0xE60, 0x70F06040,
+		0xC64, 0x00800000,
+		0xC64, 0x08800001,
+		0xC64, 0x00800002,
+		0xC64, 0x00800003,
+		0xC64, 0x00800004,
+		0xC64, 0x00800005,
+		0xC64, 0x00800006,
+		0xC64, 0x08800007,
+		0xC64, 0x00004000,
+		0xE64, 0x00800000,
+		0xE64, 0x08800001,
+		0xE64, 0x00800002,
+		0xE64, 0x00800003,
+		0xE64, 0x00800004,
+		0xE64, 0x00800005,
+		0xE64, 0x00800006,
+		0xE64, 0x08800007,
+		0xE64, 0x00004000,
+		0x1B00, 0xF8000008,
+		0x1B00, 0xF80A7008,
+		0x1B00, 0xF8015008,
+		0x1B00, 0xF8000008,
+		0x1B04, 0xE24629D2,
+		0x1B08, 0x00000080,
+		0x1B0C, 0x00000000,
+		0x1B10, 0x00011C00,
+		0x1B14, 0x00000000,
+		0x1B18, 0x00292903,
+		0x1B1C, 0xA2193C32,
+		0x1B20, 0x01840008,
+		0x1B24, 0x01860008,
+		0x1B28, 0x80060300,
+		0x1B2C, 0x00000003,
+		0x1B30, 0x20000000,
+		0x1B34, 0x00000800,
+		0x1B3C, 0x20000000,
+		0x1BC0, 0x01000000,
+		0x1BCC, 0x00000000,
+		0x1B90, 0x0001E018,
+		0x1B94, 0xF76D9F84,
+		0x1BC8, 0x000C44AA,
+		0x1BCC, 0x11978200,
+		0x1B8C, 0x00002000,
+		0x1B9C, 0x5B554F48,
+		0x1BA0, 0x6F6B6661,
+		0x1BA4, 0x817D7874,
+		0x1BA8, 0x908C8884,
+		0x1BAC, 0x9D9A9793,
+		0x1BB0, 0xAAA7A4A1,
+		0x1BB4, 0xB6B3B0AD,
+		0x1B40, 0x02CE03E8,
+		0x1B44, 0x01FD024C,
+		0x1B48, 0x01A101C9,
+		0x1B4C, 0x016A0183,
+		0x1B50, 0x01430153,
+		0x1B54, 0x01280134,
+		0x1B58, 0x0112011C,
+		0x1B5C, 0x01000107,
+		0x1B60, 0x00F200F9,
+		0x1B64, 0x00E500EB,
+		0x1B68, 0x00DA00E0,
+		0x1B6C, 0x00D200D6,
+		0x1B70, 0x00C900CD,
+		0x1B74, 0x00C200C5,
+		0x1B78, 0x00BB00BE,
+		0x1B7C, 0x00B500B8,
+		0x1BDC, 0x40CAFFE1,
+		0x1BDC, 0x4080A1E3,
+		0x1BDC, 0x405165E5,
+		0x1BDC, 0x403340E7,
+		0x1BDC, 0x402028E9,
+		0x1BDC, 0x401419EB,
+		0x1BDC, 0x400D10ED,
+		0x1BDC, 0x40080AEF,
+		0x1BDC, 0x400506F1,
+		0x1BDC, 0x400304F3,
+		0x1BDC, 0x400203F5,
+		0x1BDC, 0x400102F7,
+		0x1BDC, 0x400101F9,
+		0x1BDC, 0x400101FB,
+		0x1BDC, 0x400101FD,
+		0x1BDC, 0x400101FF,
+		0x1BDC, 0x40CAFF81,
+		0x1BDC, 0x4080A183,
+		0x1BDC, 0x40516585,
+		0x1BDC, 0x40334087,
+		0x1BDC, 0x40202889,
+		0x1BDC, 0x4014198B,
+		0x1BDC, 0x400D108D,
+		0x1BDC, 0x40080A8F,
+		0x1BDC, 0x40050691,
+		0x1BDC, 0x40030493,
+		0x1BDC, 0x40020395,
+		0x1BDC, 0x40010297,
+		0x1BDC, 0x40010199,
+		0x1BDC, 0x4001019B,
+		0x1BDC, 0x4001019D,
+		0x1BDC, 0x4001019F,
+		0x1BDC, 0x00000000,
+		0x1BDC, 0xD0000001,
+		0x1BDC, 0xD0000003,
+		0x1BDC, 0xD0000005,
+		0x1BDC, 0xD0000007,
+		0x1BDC, 0xD0000009,
+		0x1BDC, 0xD000000B,
+		0x1BDC, 0xD000000D,
+		0x1BDC, 0xD000000F,
+		0x1BDC, 0xD0000011,
+		0x1BDC, 0xD0000013,
+		0x1BDC, 0xD0000015,
+		0x1BDC, 0xD0000017,
+		0x1BDC, 0xD0000019,
+		0x1BDC, 0xD000001B,
+		0x1BDC, 0xD000001D,
+		0x1BDC, 0xD000001F,
+		0x1BDC, 0xD0000021,
+		0x1BDC, 0xD0000023,
+		0x1BDC, 0xD0000025,
+		0x1BDC, 0xD0000027,
+		0x1BDC, 0xD0000029,
+		0x1BDC, 0xD000002B,
+		0x1BDC, 0xD000002D,
+		0x1BDC, 0xD000002F,
+		0x1BDC, 0xD0000031,
+		0x1BDC, 0xD0000033,
+		0x1BDC, 0xD0000035,
+		0x1BDC, 0xD0000037,
+		0x1BDC, 0xD0000039,
+		0x1BDC, 0xD000003B,
+		0x1BDC, 0xD000003D,
+		0x1BDC, 0xD000003F,
+		0x1BDC, 0xD0000041,
+		0x1BDC, 0xD0000043,
+		0x1BDC, 0xD0000045,
+		0x1BDC, 0xD0000047,
+		0x1BDC, 0xD0000049,
+		0x1BDC, 0xD000004B,
+		0x1BDC, 0xD000004D,
+		0x1BDC, 0xD000004F,
+		0x1BDC, 0xD0000051,
+		0x1BDC, 0xD0000053,
+		0x1BDC, 0xD0000055,
+		0x1BDC, 0xD0000057,
+		0x1BDC, 0xD0000059,
+		0x1BDC, 0xD000005B,
+		0x1BDC, 0xD000005D,
+		0x1BDC, 0xD000005F,
+		0x1BDC, 0xD0000061,
+		0x1BDC, 0xD0000063,
+		0x1BDC, 0xD0000065,
+		0x1BDC, 0xD0000067,
+		0x1BDC, 0xD0000069,
+		0x1BDC, 0xD000006B,
+		0x1BDC, 0xD000006D,
+		0x1BDC, 0xD000006F,
+		0x1BDC, 0xD0000071,
+		0x1BDC, 0xD0000073,
+		0x1BDC, 0xD0000075,
+		0x1BDC, 0xD0000077,
+		0x1BDC, 0xD0000079,
+		0x1BDC, 0xD000007B,
+		0x1BDC, 0xD000007D,
+		0x1BDC, 0xD000007F,
+		0x1BDC, 0x90000081,
+		0x1BDC, 0x90000083,
+		0x1BDC, 0x90000085,
+		0x1BDC, 0x90000087,
+		0x1BDC, 0x90000089,
+		0x1BDC, 0x9000008B,
+		0x1BDC, 0x9000008D,
+		0x1BDC, 0x9000008F,
+		0x1BDC, 0x90000091,
+		0x1BDC, 0x90000093,
+		0x1BDC, 0x90000095,
+		0x1BDC, 0x90000097,
+		0x1BDC, 0x90000099,
+		0x1BDC, 0x9000009B,
+		0x1BDC, 0x9000009D,
+		0x1BDC, 0x9000009F,
+		0x1BDC, 0x900000A1,
+		0x1BDC, 0x900000A3,
+		0x1BDC, 0x900000A5,
+		0x1BDC, 0x900000A7,
+		0x1BDC, 0x900000A9,
+		0x1BDC, 0x900000AB,
+		0x1BDC, 0x900000AD,
+		0x1BDC, 0x900000AF,
+		0x1BDC, 0x900000B1,
+		0x1BDC, 0x900000B3,
+		0x1BDC, 0x900000B5,
+		0x1BDC, 0x900000B7,
+		0x1BDC, 0x900000B9,
+		0x1BDC, 0x900000BB,
+		0x1BDC, 0x900000BD,
+		0x1BDC, 0x900000BF,
+		0x1BDC, 0x900000C1,
+		0x1BDC, 0x900000C3,
+		0x1BDC, 0x900000C5,
+		0x1BDC, 0x900000C7,
+		0x1BDC, 0x900000C9,
+		0x1BDC, 0x900000CB,
+		0x1BDC, 0x900000CD,
+		0x1BDC, 0x900000CF,
+		0x1BDC, 0x900000D1,
+		0x1BDC, 0x900000D3,
+		0x1BDC, 0x900000D5,
+		0x1BDC, 0x900000D7,
+		0x1BDC, 0x900000D9,
+		0x1BDC, 0x900000DB,
+		0x1BDC, 0x900000DD,
+		0x1BDC, 0x900000DF,
+		0x1BDC, 0x900000E1,
+		0x1BDC, 0x900000E3,
+		0x1BDC, 0x900000E5,
+		0x1BDC, 0x900000E7,
+		0x1BDC, 0x900000E9,
+		0x1BDC, 0x900000EB,
+		0x1BDC, 0x900000ED,
+		0x1BDC, 0x900000EF,
+		0x1BDC, 0x900000F1,
+		0x1BDC, 0x900000F3,
+		0x1BDC, 0x900000F5,
+		0x1BDC, 0x900000F7,
+		0x1BDC, 0x900000F9,
+		0x1BDC, 0x900000FB,
+		0x1BDC, 0x900000FD,
+		0x1BDC, 0x900000FF,
+		0x1BDC, 0x00000000,
+		0x1B00, 0xF8000000,
+		0x1B80, 0x00000007,
+		0x1B80, 0x090A0005,
+		0x1B80, 0x090A0007,
+		0x1B80, 0x0FFE0015,
+		0x1B80, 0x0FFE0017,
+		0x1B80, 0x00220025,
+		0x1B80, 0x00220027,
+		0x1B80, 0x00040035,
+		0x1B80, 0x00040037,
+		0x1B80, 0x05C00045,
+		0x1B80, 0x05C00047,
+		0x1B80, 0x00070055,
+		0x1B80, 0x00070057,
+		0x1B80, 0x64000065,
+		0x1B80, 0x64000067,
+		0x1B80, 0x00020075,
+		0x1B80, 0x00020077,
+		0x1B80, 0x00080085,
+		0x1B80, 0x00080087,
+		0x1B80, 0x80000095,
+		0x1B80, 0x80000097,
+		0x1B80, 0x090800A5,
+		0x1B80, 0x090800A7,
+		0x1B80, 0x0F0200B5,
+		0x1B80, 0x0F0200B7,
+		0x1B80, 0x002200C5,
+		0x1B80, 0x002200C7,
+		0x1B80, 0x000400D5,
+		0x1B80, 0x000400D7,
+		0x1B80, 0x05C000E5,
+		0x1B80, 0x05C000E7,
+		0x1B80, 0x000700F5,
+		0x1B80, 0x000700F7,
+		0x1B80, 0x64020105,
+		0x1B80, 0x64020107,
+		0x1B80, 0x00020115,
+		0x1B80, 0x00020117,
+		0x1B80, 0x00040125,
+		0x1B80, 0x00040127,
+		0x1B80, 0x4A000135,
+		0x1B80, 0x4A000137,
+		0x1B80, 0x4B040145,
+		0x1B80, 0x4B040147,
+		0x1B80, 0x85030155,
+		0x1B80, 0x85030157,
+		0x1B80, 0x40090165,
+		0x1B80, 0x40090167,
+		0x1B80, 0xE02A0175,
+		0x1B80, 0xE02A0177,
+		0x1B80, 0x4B050185,
+		0x1B80, 0x4B050187,
+		0x1B80, 0x86030195,
+		0x1B80, 0x86030197,
+		0x1B80, 0x400B01A5,
+		0x1B80, 0x400B01A7,
+		0x1B80, 0xE02A01B5,
+		0x1B80, 0xE02A01B7,
+		0x1B80, 0x4B0001C5,
+		0x1B80, 0x4B0001C7,
+		0x1B80, 0x000701D5,
+		0x1B80, 0x000701D7,
+		0x1B80, 0x4C0001E5,
+		0x1B80, 0x4C0001E7,
+		0x1B80, 0x000401F5,
+		0x1B80, 0x000401F7,
+		0x1B80, 0x4D040205,
+		0x1B80, 0x4D040207,
+		0x1B80, 0x2EE00215,
+		0x1B80, 0x2EE00217,
+		0x1B80, 0x00000225,
+		0x1B80, 0x00000227,
+		0x1B80, 0x2EF00235,
+		0x1B80, 0x2EF00237,
+		0x1B80, 0x00000245,
+		0x1B80, 0x00000247,
+		0x1B80, 0x20810255,
+		0x1B80, 0x20810257,
+		0x1B80, 0x23450265,
+		0x1B80, 0x23450267,
+		0x1B80, 0x4D000275,
+		0x1B80, 0x4D000277,
+		0x1B80, 0x00040285,
+		0x1B80, 0x00040287,
+		0x1B80, 0x30000295,
+		0x1B80, 0x30000297,
+		0x1B80, 0xE1DC02A5,
+		0x1B80, 0xE1DC02A7,
+		0x1B80, 0xF01102B5,
+		0x1B80, 0xF01102B7,
+		0x1B80, 0xF11102C5,
+		0x1B80, 0xF11102C7,
+		0x1B80, 0xF21102D5,
+		0x1B80, 0xF21102D7,
+		0x1B80, 0xF31102E5,
+		0x1B80, 0xF31102E7,
+		0x1B80, 0xF41102F5,
+		0x1B80, 0xF41102F7,
+		0x1B80, 0xF5110305,
+		0x1B80, 0xF5110307,
+		0x1B80, 0xF6110315,
+		0x1B80, 0xF6110317,
+		0x1B80, 0xF7110325,
+		0x1B80, 0xF7110327,
+		0x1B80, 0xF8110335,
+		0x1B80, 0xF8110337,
+		0x1B80, 0xF9110345,
+		0x1B80, 0xF9110347,
+		0x1B80, 0xFA110355,
+		0x1B80, 0xFA110357,
+		0x1B80, 0xFB110365,
+		0x1B80, 0xFB110367,
+		0x1B80, 0xFC110375,
+		0x1B80, 0xFC110377,
+		0x1B80, 0xFD110385,
+		0x1B80, 0xFD110387,
+		0x1B80, 0xFE110395,
+		0x1B80, 0xFE110397,
+		0x1B80, 0xFF1103A5,
+		0x1B80, 0xFF1103A7,
+		0x1B80, 0x000103B5,
+		0x1B80, 0x000103B7,
+		0x1B80, 0x305503C5,
+		0x1B80, 0x305503C7,
+		0x1B80, 0x306D03D5,
+		0x1B80, 0x306D03D7,
+		0x1B80, 0x30B803E5,
+		0x1B80, 0x30B803E7,
+		0x1B80, 0x30BB03F5,
+		0x1B80, 0x30BB03F7,
+		0x1B80, 0x306F0405,
+		0x1B80, 0x306F0407,
+		0x1B80, 0x307A0415,
+		0x1B80, 0x307A0417,
+		0x1B80, 0x30850425,
+		0x1B80, 0x30850427,
+		0x1B80, 0x30C50435,
+		0x1B80, 0x30C50437,
+		0x1B80, 0x30BF0445,
+		0x1B80, 0x30BF0447,
+		0x1B80, 0x30D30455,
+		0x1B80, 0x30D30457,
+		0x1B80, 0x30DE0465,
+		0x1B80, 0x30DE0467,
+		0x1B80, 0x30E90475,
+		0x1B80, 0x30E90477,
+		0x1B80, 0x304C0485,
+		0x1B80, 0x304C0487,
+		0x1B80, 0x31180495,
+		0x1B80, 0x31180497,
+		0x1B80, 0x312904A5,
+		0x1B80, 0x312904A7,
+		0x1B80, 0x313E04B5,
+		0x1B80, 0x313E04B7,
+		0x1B80, 0x4D0404C5,
+		0x1B80, 0x4D0404C7,
+		0x1B80, 0x2EE004D5,
+		0x1B80, 0x2EE004D7,
+		0x1B80, 0x000004E5,
+		0x1B80, 0x000004E7,
+		0x1B80, 0x2EF004F5,
+		0x1B80, 0x2EF004F7,
+		0x1B80, 0x00000505,
+		0x1B80, 0x00000507,
+		0x1B80, 0x20810515,
+		0x1B80, 0x20810517,
+		0x1B80, 0xA3B50525,
+		0x1B80, 0xA3B50527,
+		0x1B80, 0x4D000535,
+		0x1B80, 0x4D000537,
+		0x1B80, 0x30000545,
+		0x1B80, 0x30000547,
+		0x1B80, 0xE1690555,
+		0x1B80, 0xE1690557,
+		0x1B80, 0x4D040565,
+		0x1B80, 0x4D040567,
+		0x1B80, 0x20800575,
+		0x1B80, 0x20800577,
+		0x1B80, 0x00000585,
+		0x1B80, 0x00000587,
+		0x1B80, 0x4D000595,
+		0x1B80, 0x4D000597,
+		0x1B80, 0x550705A5,
+		0x1B80, 0x550705A7,
+		0x1B80, 0xE16105B5,
+		0x1B80, 0xE16105B7,
+		0x1B80, 0xE16105C5,
+		0x1B80, 0xE16105C7,
+		0x1B80, 0x4D0405D5,
+		0x1B80, 0x4D0405D7,
+		0x1B80, 0x208805E5,
+		0x1B80, 0x208805E7,
+		0x1B80, 0x020005F5,
+		0x1B80, 0x020005F7,
+		0x1B80, 0x4D000605,
+		0x1B80, 0x4D000607,
+		0x1B80, 0x550F0615,
+		0x1B80, 0x550F0617,
+		0x1B80, 0xE1610625,
+		0x1B80, 0xE1610627,
+		0x1B80, 0x4F020635,
+		0x1B80, 0x4F020637,
+		0x1B80, 0x4E000645,
+		0x1B80, 0x4E000647,
+		0x1B80, 0x53020655,
+		0x1B80, 0x53020657,
+		0x1B80, 0x52010665,
+		0x1B80, 0x52010667,
+		0x1B80, 0xE1650675,
+		0x1B80, 0xE1650677,
+		0x1B80, 0x4D080685,
+		0x1B80, 0x4D080687,
+		0x1B80, 0x57100695,
+		0x1B80, 0x57100697,
+		0x1B80, 0x570006A5,
+		0x1B80, 0x570006A7,
+		0x1B80, 0x4D0006B5,
+		0x1B80, 0x4D0006B7,
+		0x1B80, 0x000106C5,
+		0x1B80, 0x000106C7,
+		0x1B80, 0xE16906D5,
+		0x1B80, 0xE16906D7,
+		0x1B80, 0x000106E5,
+		0x1B80, 0x000106E7,
+		0x1B80, 0x308F06F5,
+		0x1B80, 0x308F06F7,
+		0x1B80, 0x00230705,
+		0x1B80, 0x00230707,
+		0x1B80, 0xE1CF0715,
+		0x1B80, 0xE1CF0717,
+		0x1B80, 0x00020725,
+		0x1B80, 0x00020727,
+		0x1B80, 0x54E90735,
+		0x1B80, 0x54E90737,
+		0x1B80, 0x0BA60745,
+		0x1B80, 0x0BA60747,
+		0x1B80, 0x00230755,
+		0x1B80, 0x00230757,
+		0x1B80, 0xE1CF0765,
+		0x1B80, 0xE1CF0767,
+		0x1B80, 0x00020775,
+		0x1B80, 0x00020777,
+		0x1B80, 0x4D300785,
+		0x1B80, 0x4D300787,
+		0x1B80, 0x30A80795,
+		0x1B80, 0x30A80797,
+		0x1B80, 0x308B07A5,
+		0x1B80, 0x308B07A7,
+		0x1B80, 0x002207B5,
+		0x1B80, 0x002207B7,
+		0x1B80, 0xE1CF07C5,
+		0x1B80, 0xE1CF07C7,
+		0x1B80, 0x000207D5,
+		0x1B80, 0x000207D7,
+		0x1B80, 0x54E807E5,
+		0x1B80, 0x54E807E7,
+		0x1B80, 0x0BA607F5,
+		0x1B80, 0x0BA607F7,
+		0x1B80, 0x00220805,
+		0x1B80, 0x00220807,
+		0x1B80, 0xE1CF0815,
+		0x1B80, 0xE1CF0817,
+		0x1B80, 0x00020825,
+		0x1B80, 0x00020827,
+		0x1B80, 0x4D300835,
+		0x1B80, 0x4D300837,
+		0x1B80, 0x30A80845,
+		0x1B80, 0x30A80847,
+		0x1B80, 0x63F10855,
+		0x1B80, 0x63F10857,
+		0x1B80, 0xE1690865,
+		0x1B80, 0xE1690867,
+		0x1B80, 0xE1CF0875,
+		0x1B80, 0xE1CF0877,
+		0x1B80, 0x63F40885,
+		0x1B80, 0x63F40887,
+		0x1B80, 0xE1690895,
+		0x1B80, 0xE1690897,
+		0x1B80, 0xE1CF08A5,
+		0x1B80, 0xE1CF08A7,
+		0x1B80, 0x0BA808B5,
+		0x1B80, 0x0BA808B7,
+		0x1B80, 0x63F808C5,
+		0x1B80, 0x63F808C7,
+		0x1B80, 0xE16908D5,
+		0x1B80, 0xE16908D7,
+		0x1B80, 0xE1CF08E5,
+		0x1B80, 0xE1CF08E7,
+		0x1B80, 0x0BA908F5,
+		0x1B80, 0x0BA908F7,
+		0x1B80, 0x63FC0905,
+		0x1B80, 0x63FC0907,
+		0x1B80, 0xE1690915,
+		0x1B80, 0xE1690917,
+		0x1B80, 0xE1CF0925,
+		0x1B80, 0xE1CF0927,
+		0x1B80, 0x63FF0935,
+		0x1B80, 0x63FF0937,
+		0x1B80, 0xE1690945,
+		0x1B80, 0xE1690947,
+		0x1B80, 0xE1CF0955,
+		0x1B80, 0xE1CF0957,
+		0x1B80, 0x63000965,
+		0x1B80, 0x63000967,
+		0x1B80, 0xE1690975,
+		0x1B80, 0xE1690977,
+		0x1B80, 0xE1CF0985,
+		0x1B80, 0xE1CF0987,
+		0x1B80, 0x63030995,
+		0x1B80, 0x63030997,
+		0x1B80, 0xE16909A5,
+		0x1B80, 0xE16909A7,
+		0x1B80, 0xE1CF09B5,
+		0x1B80, 0xE1CF09B7,
+		0x1B80, 0xF4D409C5,
+		0x1B80, 0xF4D409C7,
+		0x1B80, 0x630709D5,
+		0x1B80, 0x630709D7,
+		0x1B80, 0xE16909E5,
+		0x1B80, 0xE16909E7,
+		0x1B80, 0xE1CF09F5,
+		0x1B80, 0xE1CF09F7,
+		0x1B80, 0xF5DB0A05,
+		0x1B80, 0xF5DB0A07,
+		0x1B80, 0x630B0A15,
+		0x1B80, 0x630B0A17,
+		0x1B80, 0xE1690A25,
+		0x1B80, 0xE1690A27,
+		0x1B80, 0xE1CF0A35,
+		0x1B80, 0xE1CF0A37,
+		0x1B80, 0x630E0A45,
+		0x1B80, 0x630E0A47,
+		0x1B80, 0xE1690A55,
+		0x1B80, 0xE1690A57,
+		0x1B80, 0xE1CF0A65,
+		0x1B80, 0xE1CF0A67,
+		0x1B80, 0x4D300A75,
+		0x1B80, 0x4D300A77,
+		0x1B80, 0x55010A85,
+		0x1B80, 0x55010A87,
+		0x1B80, 0x57040A95,
+		0x1B80, 0x57040A97,
+		0x1B80, 0x57000AA5,
+		0x1B80, 0x57000AA7,
+		0x1B80, 0x96000AB5,
+		0x1B80, 0x96000AB7,
+		0x1B80, 0x57080AC5,
+		0x1B80, 0x57080AC7,
+		0x1B80, 0x57000AD5,
+		0x1B80, 0x57000AD7,
+		0x1B80, 0x95000AE5,
+		0x1B80, 0x95000AE7,
+		0x1B80, 0x4D000AF5,
+		0x1B80, 0x4D000AF7,
+		0x1B80, 0x6C070B05,
+		0x1B80, 0x6C070B07,
+		0x1B80, 0x7B200B15,
+		0x1B80, 0x7B200B17,
+		0x1B80, 0x7A000B25,
+		0x1B80, 0x7A000B27,
+		0x1B80, 0x79000B35,
+		0x1B80, 0x79000B37,
+		0x1B80, 0x7F200B45,
+		0x1B80, 0x7F200B47,
+		0x1B80, 0x7E000B55,
+		0x1B80, 0x7E000B57,
+		0x1B80, 0x7D000B65,
+		0x1B80, 0x7D000B67,
+		0x1B80, 0x00010B75,
+		0x1B80, 0x00010B77,
+		0x1B80, 0x62850B85,
+		0x1B80, 0x62850B87,
+		0x1B80, 0xE1690B95,
+		0x1B80, 0xE1690B97,
+		0x1B80, 0x00010BA5,
+		0x1B80, 0x00010BA7,
+		0x1B80, 0x5C320BB5,
+		0x1B80, 0x5C320BB7,
+		0x1B80, 0xE1CB0BC5,
+		0x1B80, 0xE1CB0BC7,
+		0x1B80, 0xE1970BD5,
+		0x1B80, 0xE1970BD7,
+		0x1B80, 0x00010BE5,
+		0x1B80, 0x00010BE7,
+		0x1B80, 0x5C320BF5,
+		0x1B80, 0x5C320BF7,
+		0x1B80, 0x63F40C05,
+		0x1B80, 0x63F40C07,
+		0x1B80, 0x62850C15,
+		0x1B80, 0x62850C17,
+		0x1B80, 0x0BB00C25,
+		0x1B80, 0x0BB00C27,
+		0x1B80, 0xE1690C35,
+		0x1B80, 0xE1690C37,
+		0x1B80, 0xE1CF0C45,
+		0x1B80, 0xE1CF0C47,
+		0x1B80, 0x5C320C55,
+		0x1B80, 0x5C320C57,
+		0x1B80, 0x63FC0C65,
+		0x1B80, 0x63FC0C67,
+		0x1B80, 0x62850C75,
+		0x1B80, 0x62850C77,
+		0x1B80, 0x0BB10C85,
+		0x1B80, 0x0BB10C87,
+		0x1B80, 0xE1690C95,
+		0x1B80, 0xE1690C97,
+		0x1B80, 0xE1CF0CA5,
+		0x1B80, 0xE1CF0CA7,
+		0x1B80, 0x63030CB5,
+		0x1B80, 0x63030CB7,
+		0x1B80, 0xE1690CC5,
+		0x1B80, 0xE1690CC7,
+		0x1B80, 0xE1CF0CD5,
+		0x1B80, 0xE1CF0CD7,
+		0x1B80, 0xF7040CE5,
+		0x1B80, 0xF7040CE7,
+		0x1B80, 0x630B0CF5,
+		0x1B80, 0x630B0CF7,
+		0x1B80, 0xE1690D05,
+		0x1B80, 0xE1690D07,
+		0x1B80, 0xE1CF0D15,
+		0x1B80, 0xE1CF0D17,
+		0x1B80, 0x00010D25,
+		0x1B80, 0x00010D27,
+		0x1B80, 0x30F70D35,
+		0x1B80, 0x30F70D37,
+		0x1B80, 0x00230D45,
+		0x1B80, 0x00230D47,
+		0x1B80, 0xE1D40D55,
+		0x1B80, 0xE1D40D57,
+		0x1B80, 0x00020D65,
+		0x1B80, 0x00020D67,
+		0x1B80, 0x54E90D75,
+		0x1B80, 0x54E90D77,
+		0x1B80, 0x0BA60D85,
+		0x1B80, 0x0BA60D87,
+		0x1B80, 0x00230D95,
+		0x1B80, 0x00230D97,
+		0x1B80, 0xE1D40DA5,
+		0x1B80, 0xE1D40DA7,
+		0x1B80, 0x00020DB5,
+		0x1B80, 0x00020DB7,
+		0x1B80, 0x4D100DC5,
+		0x1B80, 0x4D100DC7,
+		0x1B80, 0x30A80DD5,
+		0x1B80, 0x30A80DD7,
+		0x1B80, 0x30F10DE5,
+		0x1B80, 0x30F10DE7,
+		0x1B80, 0x00220DF5,
+		0x1B80, 0x00220DF7,
+		0x1B80, 0xE1D40E05,
+		0x1B80, 0xE1D40E07,
+		0x1B80, 0x00020E15,
+		0x1B80, 0x00020E17,
+		0x1B80, 0x54E80E25,
+		0x1B80, 0x54E80E27,
+		0x1B80, 0x0BA60E35,
+		0x1B80, 0x0BA60E37,
+		0x1B80, 0x00220E45,
+		0x1B80, 0x00220E47,
+		0x1B80, 0xE1D40E55,
+		0x1B80, 0xE1D40E57,
+		0x1B80, 0x00020E65,
+		0x1B80, 0x00020E67,
+		0x1B80, 0x4D100E75,
+		0x1B80, 0x4D100E77,
+		0x1B80, 0x30A80E85,
+		0x1B80, 0x30A80E87,
+		0x1B80, 0x5C320E95,
+		0x1B80, 0x5C320E97,
+		0x1B80, 0x54F00EA5,
+		0x1B80, 0x54F00EA7,
+		0x1B80, 0x67F10EB5,
+		0x1B80, 0x67F10EB7,
+		0x1B80, 0xE1970EC5,
+		0x1B80, 0xE1970EC7,
+		0x1B80, 0xE1D40ED5,
+		0x1B80, 0xE1D40ED7,
+		0x1B80, 0x67F40EE5,
+		0x1B80, 0x67F40EE7,
+		0x1B80, 0xE1970EF5,
+		0x1B80, 0xE1970EF7,
+		0x1B80, 0xE1D40F05,
+		0x1B80, 0xE1D40F07,
+		0x1B80, 0x5C320F15,
+		0x1B80, 0x5C320F17,
+		0x1B80, 0x54F10F25,
+		0x1B80, 0x54F10F27,
+		0x1B80, 0x0BA80F35,
+		0x1B80, 0x0BA80F37,
+		0x1B80, 0x67F80F45,
+		0x1B80, 0x67F80F47,
+		0x1B80, 0xE1970F55,
+		0x1B80, 0xE1970F57,
+		0x1B80, 0xE1D40F65,
+		0x1B80, 0xE1D40F67,
+		0x1B80, 0x5C320F75,
+		0x1B80, 0x5C320F77,
+		0x1B80, 0x54F10F85,
+		0x1B80, 0x54F10F87,
+		0x1B80, 0x0BA90F95,
+		0x1B80, 0x0BA90F97,
+		0x1B80, 0x67FC0FA5,
+		0x1B80, 0x67FC0FA7,
+		0x1B80, 0xE1970FB5,
+		0x1B80, 0xE1970FB7,
+		0x1B80, 0xE1D40FC5,
+		0x1B80, 0xE1D40FC7,
+		0x1B80, 0x67FF0FD5,
+		0x1B80, 0x67FF0FD7,
+		0x1B80, 0xE1970FE5,
+		0x1B80, 0xE1970FE7,
+		0x1B80, 0xE1D40FF5,
+		0x1B80, 0xE1D40FF7,
+		0x1B80, 0x5C321005,
+		0x1B80, 0x5C321007,
+		0x1B80, 0x54F21015,
+		0x1B80, 0x54F21017,
+		0x1B80, 0x67001025,
+		0x1B80, 0x67001027,
+		0x1B80, 0xE1971035,
+		0x1B80, 0xE1971037,
+		0x1B80, 0xE1D41045,
+		0x1B80, 0xE1D41047,
+		0x1B80, 0x67031055,
+		0x1B80, 0x67031057,
+		0x1B80, 0xE1971065,
+		0x1B80, 0xE1971067,
+		0x1B80, 0xE1D41075,
+		0x1B80, 0xE1D41077,
+		0x1B80, 0xF9CC1085,
+		0x1B80, 0xF9CC1087,
+		0x1B80, 0x67071095,
+		0x1B80, 0x67071097,
+		0x1B80, 0xE19710A5,
+		0x1B80, 0xE19710A7,
+		0x1B80, 0xE1D410B5,
+		0x1B80, 0xE1D410B7,
+		0x1B80, 0xFAD310C5,
+		0x1B80, 0xFAD310C7,
+		0x1B80, 0x5C3210D5,
+		0x1B80, 0x5C3210D7,
+		0x1B80, 0x54F310E5,
+		0x1B80, 0x54F310E7,
+		0x1B80, 0x670B10F5,
+		0x1B80, 0x670B10F7,
+		0x1B80, 0xE1971105,
+		0x1B80, 0xE1971107,
+		0x1B80, 0xE1D41115,
+		0x1B80, 0xE1D41117,
+		0x1B80, 0x670E1125,
+		0x1B80, 0x670E1127,
+		0x1B80, 0xE1971135,
+		0x1B80, 0xE1971137,
+		0x1B80, 0xE1D41145,
+		0x1B80, 0xE1D41147,
+		0x1B80, 0x4D101155,
+		0x1B80, 0x4D101157,
+		0x1B80, 0x30A81165,
+		0x1B80, 0x30A81167,
+		0x1B80, 0x00011175,
+		0x1B80, 0x00011177,
+		0x1B80, 0x6C001185,
+		0x1B80, 0x6C001187,
+		0x1B80, 0x00061195,
+		0x1B80, 0x00061197,
+		0x1B80, 0x530011A5,
+		0x1B80, 0x530011A7,
+		0x1B80, 0x57F711B5,
+		0x1B80, 0x57F711B7,
+		0x1B80, 0x582111C5,
+		0x1B80, 0x582111C7,
+		0x1B80, 0x592E11D5,
+		0x1B80, 0x592E11D7,
+		0x1B80, 0x5A3811E5,
+		0x1B80, 0x5A3811E7,
+		0x1B80, 0x5B4111F5,
+		0x1B80, 0x5B4111F7,
+		0x1B80, 0x00071205,
+		0x1B80, 0x00071207,
+		0x1B80, 0x5C001215,
+		0x1B80, 0x5C001217,
+		0x1B80, 0x4B001225,
+		0x1B80, 0x4B001227,
+		0x1B80, 0x4E8F1235,
+		0x1B80, 0x4E8F1237,
+		0x1B80, 0x4F151245,
+		0x1B80, 0x4F151247,
+		0x1B80, 0x00041255,
+		0x1B80, 0x00041257,
+		0x1B80, 0xE1B91265,
+		0x1B80, 0xE1B91267,
+		0x1B80, 0xAB001275,
+		0x1B80, 0xAB001277,
+		0x1B80, 0x00011285,
+		0x1B80, 0x00011287,
+		0x1B80, 0x6C001295,
+		0x1B80, 0x6C001297,
+		0x1B80, 0x000612A5,
+		0x1B80, 0x000612A7,
+		0x1B80, 0x530012B5,
+		0x1B80, 0x530012B7,
+		0x1B80, 0x57F712C5,
+		0x1B80, 0x57F712C7,
+		0x1B80, 0x582112D5,
+		0x1B80, 0x582112D7,
+		0x1B80, 0x592E12E5,
+		0x1B80, 0x592E12E7,
+		0x1B80, 0x5A3812F5,
+		0x1B80, 0x5A3812F7,
+		0x1B80, 0x5B411305,
+		0x1B80, 0x5B411307,
+		0x1B80, 0x00071315,
+		0x1B80, 0x00071317,
+		0x1B80, 0x5C001325,
+		0x1B80, 0x5C001327,
+		0x1B80, 0x4B401335,
+		0x1B80, 0x4B401337,
+		0x1B80, 0x4E971345,
+		0x1B80, 0x4E971347,
+		0x1B80, 0x4F111355,
+		0x1B80, 0x4F111357,
+		0x1B80, 0x00041365,
+		0x1B80, 0x00041367,
+		0x1B80, 0xE1B91375,
+		0x1B80, 0xE1B91377,
+		0x1B80, 0xAB001385,
+		0x1B80, 0xAB001387,
+		0x1B80, 0x8B001395,
+		0x1B80, 0x8B001397,
+		0x1B80, 0xAB0013A5,
+		0x1B80, 0xAB0013A7,
+		0x1B80, 0x8A1913B5,
+		0x1B80, 0x8A1913B7,
+		0x1B80, 0x301D13C5,
+		0x1B80, 0x301D13C7,
+		0x1B80, 0x000113D5,
+		0x1B80, 0x000113D7,
+		0x1B80, 0x6C0113E5,
+		0x1B80, 0x6C0113E7,
+		0x1B80, 0x000613F5,
+		0x1B80, 0x000613F7,
+		0x1B80, 0x53011405,
+		0x1B80, 0x53011407,
+		0x1B80, 0x57F71415,
+		0x1B80, 0x57F71417,
+		0x1B80, 0x58211425,
+		0x1B80, 0x58211427,
+		0x1B80, 0x592E1435,
+		0x1B80, 0x592E1437,
+		0x1B80, 0x5A381445,
+		0x1B80, 0x5A381447,
+		0x1B80, 0x5B411455,
+		0x1B80, 0x5B411457,
+		0x1B80, 0x00071465,
+		0x1B80, 0x00071467,
+		0x1B80, 0x5C001475,
+		0x1B80, 0x5C001477,
+		0x1B80, 0x4B001485,
+		0x1B80, 0x4B001487,
+		0x1B80, 0x4E871495,
+		0x1B80, 0x4E871497,
+		0x1B80, 0x4F1114A5,
+		0x1B80, 0x4F1114A7,
+		0x1B80, 0x000414B5,
+		0x1B80, 0x000414B7,
+		0x1B80, 0xE1B914C5,
+		0x1B80, 0xE1B914C7,
+		0x1B80, 0xAB0014D5,
+		0x1B80, 0xAB0014D7,
+		0x1B80, 0x000614E5,
+		0x1B80, 0x000614E7,
+		0x1B80, 0x577714F5,
+		0x1B80, 0x577714F7,
+		0x1B80, 0x00071505,
+		0x1B80, 0x00071507,
+		0x1B80, 0x4E861515,
+		0x1B80, 0x4E861517,
+		0x1B80, 0x00041525,
+		0x1B80, 0x00041527,
+		0x1B80, 0x00011535,
+		0x1B80, 0x00011537,
+		0x1B80, 0x00011545,
+		0x1B80, 0x00011547,
+		0x1B80, 0x7B241555,
+		0x1B80, 0x7B241557,
+		0x1B80, 0x7A401565,
+		0x1B80, 0x7A401567,
+		0x1B80, 0x79001575,
+		0x1B80, 0x79001577,
+		0x1B80, 0x55031585,
+		0x1B80, 0x55031587,
+		0x1B80, 0x31611595,
+		0x1B80, 0x31611597,
+		0x1B80, 0x7B1C15A5,
+		0x1B80, 0x7B1C15A7,
+		0x1B80, 0x7A4015B5,
+		0x1B80, 0x7A4015B7,
+		0x1B80, 0x550B15C5,
+		0x1B80, 0x550B15C7,
+		0x1B80, 0x316115D5,
+		0x1B80, 0x316115D7,
+		0x1B80, 0x7B2015E5,
+		0x1B80, 0x7B2015E7,
+		0x1B80, 0x7A0015F5,
+		0x1B80, 0x7A0015F7,
+		0x1B80, 0x55131605,
+		0x1B80, 0x55131607,
+		0x1B80, 0x74011615,
+		0x1B80, 0x74011617,
+		0x1B80, 0x74001625,
+		0x1B80, 0x74001627,
+		0x1B80, 0x8E001635,
+		0x1B80, 0x8E001637,
+		0x1B80, 0x00011645,
+		0x1B80, 0x00011647,
+		0x1B80, 0x57021655,
+		0x1B80, 0x57021657,
+		0x1B80, 0x57001665,
+		0x1B80, 0x57001667,
+		0x1B80, 0x97001675,
+		0x1B80, 0x97001677,
+		0x1B80, 0x00011685,
+		0x1B80, 0x00011687,
+		0x1B80, 0x4F781695,
+		0x1B80, 0x4F781697,
+		0x1B80, 0x538816A5,
+		0x1B80, 0x538816A7,
+		0x1B80, 0xE17716B5,
+		0x1B80, 0xE17716B7,
+		0x1B80, 0x548016C5,
+		0x1B80, 0x548016C7,
+		0x1B80, 0x540016D5,
+		0x1B80, 0x540016D7,
+		0x1B80, 0xE17716E5,
+		0x1B80, 0xE17716E7,
+		0x1B80, 0x548116F5,
+		0x1B80, 0x548116F7,
+		0x1B80, 0x54001705,
+		0x1B80, 0x54001707,
+		0x1B80, 0xE1771715,
+		0x1B80, 0xE1771717,
+		0x1B80, 0x54821725,
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+		0x1B80, 0x54001735,
+		0x1B80, 0x54001737,
+		0x1B80, 0xE1821745,
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+		0x1B80, 0xBF1D1755,
+		0x1B80, 0xBF1D1757,
+		0x1B80, 0x301D1765,
+		0x1B80, 0x301D1767,
+		0x1B80, 0xE1551775,
+		0x1B80, 0xE1551777,
+		0x1B80, 0xE15A1785,
+		0x1B80, 0xE15A1787,
+		0x1B80, 0xE15E1795,
+		0x1B80, 0xE15E1797,
+		0x1B80, 0xE16517A5,
+		0x1B80, 0xE16517A7,
+		0x1B80, 0xE1CB17B5,
+		0x1B80, 0xE1CB17B7,
+		0x1B80, 0x551317C5,
+		0x1B80, 0x551317C7,
+		0x1B80, 0xE16117D5,
+		0x1B80, 0xE16117D7,
+		0x1B80, 0x551517E5,
+		0x1B80, 0x551517E7,
+		0x1B80, 0xE16517F5,
+		0x1B80, 0xE16517F7,
+		0x1B80, 0xE1CB1805,
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+		0x1B80, 0x00011817,
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+		0x1B80, 0x54E51935,
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+		0x1B80, 0x050A1945,
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+		0x1B80, 0x00011965,
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+		0x1B80, 0x7F201975,
+		0x1B80, 0x7F201977,
+		0x1B80, 0x7E001985,
+		0x1B80, 0x7E001987,
+		0x1B80, 0x7D001995,
+		0x1B80, 0x7D001997,
+		0x1B80, 0x550119A5,
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+		0x1B80, 0x5C3119B5,
+		0x1B80, 0x5C3119B7,
+		0x1B80, 0xE16119C5,
+		0x1B80, 0xE16119C7,
+		0x1B80, 0xE16519D5,
+		0x1B80, 0xE16519D7,
+		0x1B80, 0x548019E5,
+		0x1B80, 0x548019E7,
+		0x1B80, 0x540019F5,
+		0x1B80, 0x540019F7,
+		0x1B80, 0xE1611A05,
+		0x1B80, 0xE1611A07,
+		0x1B80, 0xE1651A15,
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+		0x1B80, 0x54811A25,
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+		0x1B80, 0x54001A35,
+		0x1B80, 0x54001A37,
+		0x1B80, 0xE1611A45,
+		0x1B80, 0xE1611A47,
+		0x1B80, 0xE1651A55,
+		0x1B80, 0xE1651A57,
+		0x1B80, 0x54821A65,
+		0x1B80, 0x54821A67,
+		0x1B80, 0x54001A75,
+		0x1B80, 0x54001A77,
+		0x1B80, 0xE1821A85,
+		0x1B80, 0xE1821A87,
+		0x1B80, 0xBFE91A95,
+		0x1B80, 0xBFE91A97,
+		0x1B80, 0x301D1AA5,
+		0x1B80, 0x301D1AA7,
+		0x1B80, 0x00231AB5,
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+		0x1B80, 0x7A001AD5,
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+		0x1B80, 0x79001AE5,
+		0x1B80, 0x79001AE7,
+		0x1B80, 0xE1CF1AF5,
+		0x1B80, 0xE1CF1AF7,
+		0x1B80, 0x00021B05,
+		0x1B80, 0x00021B07,
+		0x1B80, 0x00011B15,
+		0x1B80, 0x00011B17,
+		0x1B80, 0x00221B25,
+		0x1B80, 0x00221B27,
+		0x1B80, 0x7B201B35,
+		0x1B80, 0x7B201B37,
+		0x1B80, 0x7A001B45,
+		0x1B80, 0x7A001B47,
+		0x1B80, 0x79001B55,
+		0x1B80, 0x79001B57,
+		0x1B80, 0xE1CF1B65,
+		0x1B80, 0xE1CF1B67,
+		0x1B80, 0x00021B75,
+		0x1B80, 0x00021B77,
+		0x1B80, 0x00011B85,
+		0x1B80, 0x00011B87,
+		0x1B80, 0x74021B95,
+		0x1B80, 0x74021B97,
+		0x1B80, 0x003F1BA5,
+		0x1B80, 0x003F1BA7,
+		0x1B80, 0x74001BB5,
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+		0x1B80, 0x00021BC5,
+		0x1B80, 0x00021BC7,
+		0x1B80, 0x00011BD5,
+		0x1B80, 0x00011BD7,
+		0x1B80, 0x4D041BE5,
+		0x1B80, 0x4D041BE7,
+		0x1B80, 0x2EF81BF5,
+		0x1B80, 0x2EF81BF7,
+		0x1B80, 0x00001C05,
+		0x1B80, 0x00001C07,
+		0x1B80, 0x23301C15,
+		0x1B80, 0x23301C17,
+		0x1B80, 0x00241C25,
+		0x1B80, 0x00241C27,
+		0x1B80, 0x23E01C35,
+		0x1B80, 0x23E01C37,
+		0x1B80, 0x003F1C45,
+		0x1B80, 0x003F1C47,
+		0x1B80, 0x23FC1C55,
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+		0x1B80, 0x2EF01C75,
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+		0x1B80, 0x00001C85,
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+		0x1B80, 0x00011CA5,
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+		0x1B80, 0x549F1CB5,
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+		0x1B80, 0x54001CD5,
+		0x1B80, 0x54001CD7,
+		0x1B80, 0x00011CE5,
+		0x1B80, 0x00011CE7,
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+		0x1B80, 0x5C311CF7,
+		0x1B80, 0x07141D05,
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+		0x1B80, 0x54001D15,
+		0x1B80, 0x54001D17,
+		0x1B80, 0x5C321D25,
+		0x1B80, 0x5C321D27,
+		0x1B80, 0x00011D35,
+		0x1B80, 0x00011D37,
+		0x1B80, 0x5C321D45,
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+		0x1B80, 0x07141D55,
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+		0x1B80, 0x54001D65,
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+		0x1B80, 0x5C311D75,
+		0x1B80, 0x5C311D77,
+		0x1B80, 0x00011D85,
+		0x1B80, 0x00011D87,
+		0x1B80, 0x4C981D95,
+		0x1B80, 0x4C981D97,
+		0x1B80, 0x4C181DA5,
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+		0x1B80, 0x00011DB5,
+		0x1B80, 0x00011DB7,
+		0x1B80, 0x5C321DC5,
+		0x1B80, 0x5C321DC7,
+		0x1B80, 0x62841DD5,
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+		0x1B80, 0x66861DE5,
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+		0x1B80, 0x6C031DF5,
+		0x1B80, 0x6C031DF7,
+		0x1B80, 0x7B201E05,
+		0x1B80, 0x7B201E07,
+		0x1B80, 0x7A001E15,
+		0x1B80, 0x7A001E17,
+		0x1B80, 0x79001E25,
+		0x1B80, 0x79001E27,
+		0x1B80, 0x7F201E35,
+		0x1B80, 0x7F201E37,
+		0x1B80, 0x7E001E45,
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+		0x1B80, 0x7D001E55,
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+		0x1B80, 0x09011E65,
+		0x1B80, 0x09011E67,
+		0x1B80, 0x0C011E75,
+		0x1B80, 0x0C011E77,
+		0x1B80, 0x0BA61E85,
+		0x1B80, 0x0BA61E87,
+		0x1B80, 0x00011E95,
+		0x1B80, 0x00011E97,
+		0x1B80, 0x00000006,
+		0x1B80, 0x00000002,
+
+};
+
+void
+odm_read_and_config_mp_8821c_phy_reg(struct dm_struct *dm)
+{
+	u32	i = 0;
+	u8	c_cond;
+	boolean	is_matched = true, is_skipped = false;
+	u32	array_len = sizeof(array_mp_8821c_phy_reg) / sizeof(u32);
+	u32	*array = array_mp_8821c_phy_reg;
+
+	u32	v1 = 0, v2 = 0, pre_v1 = 0, pre_v2 = 0;
+
+	PHYDM_DBG(dm, ODM_COMP_INIT, "===> %s\n", __func__);
+
+	while ((i + 1) < array_len) {
+		v1 = array[i];
+		v2 = array[i + 1];
+
+		if (v1 & (BIT(31) | BIT(30))) {/*positive & negative condition*/
+			if (v1 & BIT(31)) {/* positive condition*/
+				c_cond  = (u8)((v1 & (BIT(29) | BIT(28))) >> 28);
+				if (c_cond == COND_ENDIF) {/*end*/
+					is_matched = true;
+					is_skipped = false;
+					PHYDM_DBG(dm, ODM_COMP_INIT, "ENDIF\n");
+				} else if (c_cond == COND_ELSE) { /*else*/
+					is_matched = is_skipped ? false : true;
+					PHYDM_DBG(dm, ODM_COMP_INIT, "ELSE\n");
+				} else {/*if , else if*/
+					pre_v1 = v1;
+					pre_v2 = v2;
+					PHYDM_DBG(dm, ODM_COMP_INIT, "IF or ELSE IF\n");
+				}
+			} else if (v1 & BIT(30)) { /*negative condition*/
+				if (is_skipped == false) {
+					if (check_positive(dm, pre_v1, pre_v2, v1, v2)) {
+						is_matched = true;
+						is_skipped = true;
+					} else {
+						is_matched = false;
+						is_skipped = false;
+					}
+				} else
+					is_matched = false;
+			}
+		} else {
+			if (is_matched)
+				odm_config_bb_phy_8821c(dm, v1, MASKDWORD, v2);
+		}
+		i = i + 2;
+	}
+}
+
+u32
+odm_get_version_mp_8821c_phy_reg(void)
+{
+		return 49;
+}
+
+/******************************************************************************
+*                           phy_reg_mp.TXT
+******************************************************************************/
+
+u32 array_mp_8821c_phy_reg_mp[] = {
+		0x810, 0x21104285,
+		0xAA8, 0xEAD30004,
+
+};
+
+void
+odm_read_and_config_mp_8821c_phy_reg_mp(struct dm_struct *dm)
+{
+	u32	i = 0;
+	u8	c_cond;
+	boolean	is_matched = true, is_skipped = false;
+	u32	array_len = sizeof(array_mp_8821c_phy_reg_mp) / sizeof(u32);
+	u32	*array = array_mp_8821c_phy_reg_mp;
+
+	u32	v1 = 0, v2 = 0, pre_v1 = 0, pre_v2 = 0;
+
+	PHYDM_DBG(dm, ODM_COMP_INIT, "===> %s\n", __func__);
+
+	while ((i + 1) < array_len) {
+		v1 = array[i];
+		v2 = array[i + 1];
+
+		if (v1 & (BIT(31) | BIT(30))) {/*positive & negative condition*/
+			if (v1 & BIT(31)) {/* positive condition*/
+				c_cond  = (u8)((v1 & (BIT(29) | BIT(28))) >> 28);
+				if (c_cond == COND_ENDIF) {/*end*/
+					is_matched = true;
+					is_skipped = false;
+					PHYDM_DBG(dm, ODM_COMP_INIT, "ENDIF\n");
+				} else if (c_cond == COND_ELSE) { /*else*/
+					is_matched = is_skipped ? false : true;
+					PHYDM_DBG(dm, ODM_COMP_INIT, "ELSE\n");
+				} else {/*if , else if*/
+					pre_v1 = v1;
+					pre_v2 = v2;
+					PHYDM_DBG(dm, ODM_COMP_INIT, "IF or ELSE IF\n");
+				}
+			} else if (v1 & BIT(30)) { /*negative condition*/
+				if (is_skipped == false) {
+					if (check_positive(dm, pre_v1, pre_v2, v1, v2)) {
+						is_matched = true;
+						is_skipped = true;
+					} else {
+						is_matched = false;
+						is_skipped = false;
+					}
+				} else
+					is_matched = false;
+			}
+		} else {
+			if (is_matched)
+				odm_config_bb_phy_8821c(dm, v1, MASKDWORD, v2);
+		}
+		i = i + 2;
+	}
+}
+
+u32
+odm_get_version_mp_8821c_phy_reg_mp(void)
+{
+		return 49;
+}
+
+/******************************************************************************
+*                           phy_reg_pg.TXT
+******************************************************************************/
+
+u32 array_mp_8821c_phy_reg_pg[] = {
+	0, 0, 0, 0x00000c20, 0xffffffff, 0x32343638,
+	0, 0, 0, 0x00000c24, 0xffffffff, 0x36363636,
+	0, 0, 0, 0x00000c28, 0xffffffff, 0x28303234,
+	0, 0, 0, 0x00000c2c, 0xffffffff, 0x34363636,
+	0, 0, 0, 0x00000c30, 0xffffffff, 0x26283032,
+	0, 0, 0, 0x00000c3c, 0xffffffff, 0x34363636,
+	0, 0, 0, 0x00000c40, 0xffffffff, 0x26283032,
+	0, 0, 0, 0x00000c44, 0xffffffff, 0x22222224,
+	1, 0, 0, 0x00000c24, 0xffffffff, 0x34343434,
+	1, 0, 0, 0x00000c28, 0xffffffff, 0x26283032,
+	1, 0, 0, 0x00000c2c, 0xffffffff, 0x32343434,
+	1, 0, 0, 0x00000c30, 0xffffffff, 0x24262830,
+	1, 0, 0, 0x00000c3c, 0xffffffff, 0x32343434,
+	1, 0, 0, 0x00000c40, 0xffffffff, 0x24262830,
+	1, 0, 0, 0x00000c44, 0xffffffff, 0x20202022
+};
+
+void
+odm_read_and_config_mp_8821c_phy_reg_pg(struct dm_struct *dm)
+{
+	u32	i = 0;
+	u32	array_len = sizeof(array_mp_8821c_phy_reg_pg) / sizeof(u32);
+	u32	*array = array_mp_8821c_phy_reg_pg;
+
+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
+	void	*adapter = dm->adapter;
+	HAL_DATA_TYPE	*hal_data = GET_HAL_DATA(((PADAPTER)adapter));
+
+	PlatformZeroMemory(hal_data->BufOfLinesPwrByRate, MAX_LINES_HWCONFIG_TXT * MAX_BYTES_LINE_HWCONFIG_TXT);
+	hal_data->nLinesReadPwrByRate = array_len / 6;
+#endif
+
+	PHYDM_DBG(dm, ODM_COMP_INIT, "===> %s\n", __func__);
+
+	dm->phy_reg_pg_version = 1;
+	dm->phy_reg_pg_value_type = PHY_REG_PG_EXACT_VALUE;
+
+	for (i = 0; i < array_len; i += 6) {
+		u32	v1 = array[i];
+		u32	v2 = array[i + 1];
+		u32	v3 = array[i + 2];
+		u32	v4 = array[i + 3];
+		u32	v5 = array[i + 4];
+		u32	v6 = array[i + 5];
+
+		odm_config_bb_phy_reg_pg_8821c(dm, v1, v2, v3, v4, v5, v6);
+
+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
+	rsprintf((char *)hal_data->BufOfLinesPwrByRate[i / 6], 100, "%s, %s, %s, 0x%X, 0x%08X, 0x%08X,",
+		(v1 == 0 ? "2.4G" : "  5G"), (v2 == 0 ? "A" : "B"), (v3 == 0 ? "1Tx" : "2Tx"), v4, v5, v6);
+#endif
+	}
+}
+
+
+
+/******************************************************************************
+*                           phy_reg_pg_type0x28.TXT
+******************************************************************************/
+
+u32 array_mp_8821c_phy_reg_pg_type0x28[] = {
+	0, 0, 0, 0x00000c20, 0xffffffff, 0x32343638,
+	0, 0, 0, 0x00000c24, 0xffffffff, 0x36363636,
+	0, 0, 0, 0x00000c28, 0xffffffff, 0x28303234,
+	0, 0, 0, 0x00000c2c, 0xffffffff, 0x34363636,
+	0, 0, 0, 0x00000c30, 0xffffffff, 0x26283032,
+	0, 0, 0, 0x00000c3c, 0xffffffff, 0x34363636,
+	0, 0, 0, 0x00000c40, 0xffffffff, 0x26283032,
+	0, 0, 0, 0x00000c44, 0xffffffff, 0x22222224,
+	1, 0, 0, 0x00000c24, 0xffffffff, 0x40404040,
+	1, 0, 0, 0x00000c28, 0xffffffff, 0x32343638,
+	1, 0, 0, 0x00000c2c, 0xffffffff, 0x38383838,
+	1, 0, 0, 0x00000c30, 0xffffffff, 0x30323436,
+	1, 0, 0, 0x00000c3c, 0xffffffff, 0x36363636,
+	1, 0, 0, 0x00000c40, 0xffffffff, 0x30323436,
+	1, 0, 0, 0x00000c44, 0xffffffff, 0x26262628
+};
+
+void
+odm_read_and_config_mp_8821c_phy_reg_pg_type0x28(struct dm_struct *dm)
+{
+	u32	i = 0;
+	u32	array_len = sizeof(array_mp_8821c_phy_reg_pg_type0x28) / sizeof(u32);
+	u32	*array = array_mp_8821c_phy_reg_pg_type0x28;
+
+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
+	void	*adapter = dm->adapter;
+	HAL_DATA_TYPE	*hal_data = GET_HAL_DATA(((PADAPTER)adapter));
+
+	PlatformZeroMemory(hal_data->BufOfLinesPwrByRate, MAX_LINES_HWCONFIG_TXT * MAX_BYTES_LINE_HWCONFIG_TXT);
+	hal_data->nLinesReadPwrByRate = array_len / 6;
+#endif
+
+	PHYDM_DBG(dm, ODM_COMP_INIT, "===> %s\n", __func__);
+
+	dm->phy_reg_pg_version = 1;
+	dm->phy_reg_pg_value_type = PHY_REG_PG_EXACT_VALUE;
+
+	for (i = 0; i < array_len; i += 6) {
+		u32	v1 = array[i];
+		u32	v2 = array[i + 1];
+		u32	v3 = array[i + 2];
+		u32	v4 = array[i + 3];
+		u32	v5 = array[i + 4];
+		u32	v6 = array[i + 5];
+
+		odm_config_bb_phy_reg_pg_8821c(dm, v1, v2, v3, v4, v5, v6);
+
+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
+	rsprintf((char *)hal_data->BufOfLinesPwrByRate[i / 6], 100, "%s, %s, %s, 0x%X, 0x%08X, 0x%08X,",
+		(v1 == 0 ? "2.4G" : "  5G"), (v2 == 0 ? "A" : "B"), (v3 == 0 ? "1Tx" : "2Tx"), v4, v5, v6);
+#endif
+	}
+}
+
+
+
+#endif /* end of HWIMG_SUPPORT*/
+
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/rtl8821c/halhwimg8821c_bb.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/rtl8821c/halhwimg8821c_bb.h
--- linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/rtl8821c/halhwimg8821c_bb.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/rtl8821c/halhwimg8821c_bb.h	2020-04-10 16:35:06.828660628 +0300
@@ -0,0 +1,91 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * The full GNU General Public License is included in this distribution in the
+ * file called LICENSE.
+ *
+ * Contact Information:
+ * wlanfae <wlanfae@realtek.com>
+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
+ * Hsinchu 300, Taiwan.
+ *
+ * Larry Finger <Larry.Finger@lwfinger.net>
+ *
+ *****************************************************************************/
+
+/*Image2HeaderVersion: R3 1.0*/
+#if (RTL8821C_SUPPORT == 1)
+#ifndef __INC_MP_BB_HW_IMG_8821C_H
+#define __INC_MP_BB_HW_IMG_8821C_H
+
+
+/******************************************************************************
+*                           agc_tab.TXT
+******************************************************************************/
+
+void
+odm_read_and_config_mp_8821c_agc_tab( /* tc: Test Chip, mp: mp Chip*/
+				     struct dm_struct *dm);
+u32 odm_get_version_mp_8821c_agc_tab(void);
+
+/******************************************************************************
+*                           agc_tab_diff.TXT
+******************************************************************************/
+
+extern u32	array_mp_8821c_agc_tab_diff_wlg[780];
+extern u32	array_mp_8821c_agc_tab_diff_btg[780];
+void
+odm_read_and_config_mp_8821c_agc_tab_diff(struct dm_struct *dm, u32 array[],
+					  u32 array_len);
+u32 odm_get_version_mp_8821c_agc_tab_diff(void);
+
+/******************************************************************************
+*                           phy_reg.TXT
+******************************************************************************/
+
+void
+odm_read_and_config_mp_8821c_phy_reg( /* tc: Test Chip, mp: mp Chip*/
+				     struct dm_struct *dm);
+u32 odm_get_version_mp_8821c_phy_reg(void);
+
+/******************************************************************************
+*                           phy_reg_mp.TXT
+******************************************************************************/
+
+void
+odm_read_and_config_mp_8821c_phy_reg_mp( /* tc: Test Chip, mp: mp Chip*/
+					struct dm_struct *dm);
+u32 odm_get_version_mp_8821c_phy_reg_mp(void);
+
+/******************************************************************************
+*                           phy_reg_pg.TXT
+******************************************************************************/
+
+void
+odm_read_and_config_mp_8821c_phy_reg_pg( /* tc: Test Chip, mp: mp Chip*/
+					struct dm_struct *dm);
+u32	odm_get_version_mp_8821c_phy_reg_pg(void);
+
+/******************************************************************************
+*                           phy_reg_pg_type0x28.TXT
+******************************************************************************/
+
+void
+odm_read_and_config_mp_8821c_phy_reg_pg_type0x28(
+						 /* tc: Test Chip, mp: mp Chip*/
+						 struct dm_struct *dm);
+u32	odm_get_version_mp_8821c_phy_reg_pg_type0x28(void);
+
+#endif
+#endif /* end of HWIMG_SUPPORT*/
+
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/rtl8821c/halhwimg8821c_fw.c linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/rtl8821c/halhwimg8821c_fw.c
--- linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/rtl8821c/halhwimg8821c_fw.c	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/rtl8821c/halhwimg8821c_fw.c	2020-04-10 16:35:06.833660861 +0300
@@ -0,0 +1,18444 @@
+/******************************************************************************
+*
+* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
+*
+* This program is free software; you can redistribute it and/or modify it
+* under the terms of version 2 of the GNU General Public License as
+* published by the Free Software Foundation.
+*
+* This program is distributed in the hope that it will be useful, but WITHOUT
+* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+* more details.
+*
+* You should have received a copy of the GNU General Public License along with
+* this program; if not, write to the Free Software Foundation, Inc.,
+* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
+*
+*
+******************************************************************************/
+
+/*Image2HeaderVersion: 2.16*/
+#include "mp_precomp.h"
+#include "../phydm_precomp.h"
+
+#ifdef LOAD_FW_HEADER_FROM_DRIVER
+	#include "../../rtl8821c/hal8821c_fw.h"
+#endif
+
+
+#if (RTL8821C_SUPPORT == 1)
+#if (defined(CONFIG_AP_WOWLAN) || (DM_ODM_SUPPORT_TYPE & (ODM_AP)))
+
+
+#ifndef LOAD_FW_HEADER_FROM_DRIVER
+u8 array_mp_8821c_fw_ap[] = {
+	0x21, 0x88, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x74, 0x34, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x06, 0x15, 0x12, 0x0B, 0xE0, 0x07, 0x00, 0x00, 0x18, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x20, 0x80, 0xD0, 0x92, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0xE8, 0x66, 0x00, 0x00, 0x00, 0x50, 0x00, 0x00, 0x00, 0x00, 0x10, 0x80, 0x00, 0x00, 0x03, 0x80,
+	0x00, 0x00, 0x04, 0x04, 0x08, 0x08, 0x08, 0x08, 0x0C, 0x0C, 0x0C, 0x0C, 0x0C, 0x0C, 0x0C, 0x0C,
+	0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10,
+	0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14,
+	0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14,
+	0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18,
+	0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18,
+	0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18,
+	0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18,
+	0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C,
+	0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C,
+	0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C,
+	0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C,
+	0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C,
+	0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C,
+	0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C,
+	0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x01, 0xFE, 0x03, 0x01, 0x01, 0xFE,
+	0x03, 0x02, 0x01, 0xFE, 0x03, 0x03, 0x01, 0xFE, 0x03, 0x04, 0x01, 0xFE, 0x03, 0x05, 0x01, 0xFE,
+	0x03, 0x06, 0x01, 0xFE, 0x03, 0x07, 0x01, 0xFE, 0x06, 0x00, 0x00, 0x00, 0x05, 0x00, 0x00, 0x00,
+	0x01, 0x00, 0x00, 0x01, 0x40, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x01, 0x00, 0x03, 0x80,
+	0x7D, 0x01, 0x03, 0x80, 0x7D, 0x01, 0x03, 0x80, 0xFD, 0x32, 0x03, 0x80, 0x00, 0x00, 0x00, 0x00,
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+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x42, 0xAB, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+
+};
+u32 array_length_mp_8821c_fw_ap = 84496;
+
+#endif
+
+void
+odm_read_firmware_mp_8821c_fw_ap(
+	struct PHY_DM_STRUCT    *p_dm_odm,
+	u8       *p_firmware,
+	u32       *p_firmware_size
+)
+{
+#if (DM_ODM_SUPPORT_TYPE & (ODM_CE))
+	*((SIZE_PTR *)p_firmware) = (SIZE_PTR)array_mp_8821c_fw_ap;
+#else
+	odm_move_memory(p_dm_odm, p_firmware, array_mp_8821c_fw_ap, array_length_mp_8821c_fw_ap);
+#endif
+	*p_firmware_size = array_length_mp_8821c_fw_ap;
+}
+
+
+#endif /* #if (defined(CONFIG_AP_WOWLAN) || (DM_ODM_SUPPORT_TYPE & (ODM_AP)) */
+
+
+#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN)) || (DM_ODM_SUPPORT_TYPE & (ODM_CE))
+
+#ifndef LOAD_FW_HEADER_FROM_DRIVER
+u8 array_mp_8821c_fw_nic[] = {
+	0x21, 0x88, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x74, 0x34, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x06, 0x15, 0x12, 0x0B, 0xE0, 0x07, 0x00, 0x00, 0x18, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x20, 0x80, 0x18, 0x96, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x38, 0xBB, 0x00, 0x00, 0x00, 0x50, 0x00, 0x00, 0x00, 0x00, 0x10, 0x80, 0x00, 0x00, 0x03, 0x80,
+	0x00, 0x00, 0x04, 0x04, 0x08, 0x08, 0x08, 0x08, 0x0C, 0x0C, 0x0C, 0x0C, 0x0C, 0x0C, 0x0C, 0x0C,
+	0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10,
+	0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14,
+	0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14,
+	0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18,
+	0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18,
+	0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18,
+	0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18,
+	0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C,
+	0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C,
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+	0x00, 0x68, 0x62, 0x67, 0x30, 0xF0, 0x21, 0x6A, 0x11, 0xF2, 0x44, 0x9A, 0x8C, 0xEB, 0x04, 0xD3,
+	0x40, 0xA2, 0x4C, 0xE9, 0x30, 0xF0, 0x21, 0x6A, 0x71, 0xF5, 0x70, 0x9A, 0xEE, 0xF1, 0x1F, 0x6A,
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+	0xE5, 0xF0, 0x9C, 0x9A, 0x00, 0xF4, 0x00, 0x6B, 0x8C, 0xEB, 0x0A, 0x23, 0x05, 0xF1, 0x40, 0x9A,
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+	0x12, 0xEA, 0x49, 0xE3, 0x20, 0xF0, 0x85, 0xA2, 0x80, 0x6B, 0x6B, 0xEB, 0x8C, 0xEB, 0xFF, 0x6C,
+	0x8C, 0xEB, 0x43, 0x2B, 0x40, 0xF0, 0x84, 0xA2, 0xFF, 0x74, 0x0E, 0x60, 0x40, 0xF0, 0x86, 0xA2,
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+	0x01, 0x6B, 0x6B, 0xEB, 0x40, 0xF0, 0x64, 0xC2, 0x40, 0xF0, 0x65, 0xA2, 0xFF, 0x73, 0x0F, 0x60,
+	0x40, 0xF0, 0x67, 0xA2, 0x63, 0x5B, 0x08, 0x61, 0x00, 0x6B, 0x40, 0xF0, 0x67, 0xC2, 0x01, 0x6B,
+	0x6B, 0xEB, 0x40, 0xF0, 0x65, 0xC2, 0x03, 0x10, 0x01, 0x4B, 0x40, 0xF0, 0x67, 0xC2, 0x1D, 0x28,
+	0x30, 0xF0, 0x20, 0x6B, 0xC0, 0xF1, 0x08, 0x4B, 0xE5, 0xF0, 0xBC, 0x9B, 0x00, 0xF4, 0x00, 0x6C,
+	0xAC, 0xEC, 0x13, 0x24, 0x05, 0xF1, 0x60, 0x9B, 0x05, 0x5B, 0x0F, 0x61, 0x40, 0xF0, 0xA4, 0xA2,
+	0x40, 0xF0, 0xC5, 0xA2, 0x40, 0xF0, 0xE6, 0xA2, 0x40, 0xF0, 0x47, 0xA2, 0x30, 0xF0, 0x21, 0x6C,
+	0xF1, 0xF6, 0x14, 0x4C, 0x04, 0xD2, 0x80, 0x18, 0x77, 0xC2, 0x01, 0x48, 0xFF, 0x6A, 0x4C, 0xE8,
+	0x80, 0x70, 0xA8, 0x61, 0x07, 0x97, 0x06, 0x90, 0x04, 0x63, 0x00, 0xEF, 0xFA, 0x63, 0x0B, 0x62,
+	0x0A, 0xD1, 0x09, 0xD0, 0xFF, 0x6B, 0x6C, 0xEE, 0x50, 0x68, 0x18, 0xEE, 0x10, 0x92, 0x27, 0x67,
+	0x6C, 0xE9, 0x6C, 0xEA, 0x30, 0xF0, 0x20, 0x6B, 0x20, 0xF2, 0x18, 0x4B, 0x12, 0xE8, 0x01, 0xE3,
+	0x20, 0xF0, 0x73, 0xA0, 0x2E, 0xEB, 0x14, 0x23, 0x7D, 0x67, 0x55, 0xC3, 0x00, 0x6A, 0xD3, 0xC3,
+	0x32, 0xC3, 0x56, 0xC3, 0x56, 0xA8, 0x06, 0x96, 0x57, 0xC3, 0x0C, 0x6A, 0x50, 0xC3, 0x06, 0x6A,
+	0x5E, 0xC3, 0x04, 0x94, 0x05, 0x95, 0x07, 0x97, 0x80, 0x18, 0x72, 0xC0, 0x20, 0xF0, 0x33, 0xC0,
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+	0x0E, 0xD1, 0x0D, 0xD0, 0xFF, 0x6A, 0x8C, 0xEA, 0x06, 0xD2, 0xFF, 0x6C, 0xFF, 0x6A, 0x8C, 0xED,
+	0xEC, 0xEA, 0xCC, 0xEC, 0x0B, 0xD2, 0x0A, 0xD4, 0x80, 0x6A, 0x7F, 0x6C, 0xAC, 0xEC, 0xAC, 0xEA,
+	0x07, 0xD4, 0x09, 0xD2, 0x06, 0x94, 0x30, 0xF0, 0x21, 0x6A, 0x71, 0xF2, 0x58, 0x9A, 0x94, 0x33,
+	0x07, 0x95, 0x49, 0xE3, 0x40, 0xA2, 0x30, 0xF0, 0x20, 0x6A, 0xAF, 0xF6, 0x54, 0x9A, 0x09, 0x96,
+	0x0B, 0x97, 0x40, 0xEA, 0xFF, 0x72, 0x02, 0x67, 0x80, 0xF0, 0x0B, 0x60, 0x06, 0x92, 0x50, 0x69,
+	0x06, 0x95, 0x38, 0xEA, 0x05, 0x6B, 0x30, 0xF0, 0x20, 0x6A, 0x20, 0xF2, 0x18, 0x4A, 0x12, 0xE9,
+	0x25, 0xE2, 0x78, 0xED, 0xFF, 0x6D, 0x12, 0xEC, 0x89, 0xE2, 0x27, 0xF0, 0x58, 0xA2, 0x07, 0x6C,
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+	0x03, 0xC1, 0x6C, 0xEA, 0x20, 0xF0, 0x46, 0xC1, 0x0A, 0x94, 0x06, 0x96, 0xF0, 0x67, 0x04, 0xD4,
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+	0x86, 0xA1, 0x40, 0x6A, 0x03, 0xC1, 0x8D, 0xEA, 0x20, 0xF0, 0x46, 0xC1, 0x06, 0x96, 0x00, 0x6C,
+	0xA4, 0x67, 0xF0, 0x67, 0x04, 0xD3, 0x80, 0x18, 0xEF, 0xC4, 0x07, 0x94, 0x80, 0x18, 0x6D, 0xC3,
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+	0xFF, 0x6C, 0x00, 0xF6, 0x63, 0x33, 0x8C, 0xEB, 0x06, 0x94, 0x03, 0x5C, 0x0A, 0x60, 0x30, 0xF0,
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+	0x21, 0x6D, 0x91, 0xF2, 0xA0, 0x9D, 0xB5, 0xE4, 0x00, 0xC5, 0x30, 0xF0, 0x21, 0x6D, 0x71, 0xF2,
+	0xB8, 0x9D, 0xB5, 0xE4, 0x60, 0xC5, 0x30, 0xF0, 0x21, 0x6B, 0xB1, 0xF2, 0x70, 0x9B, 0x71, 0xE4,
+	0x40, 0xC4, 0x0F, 0x97, 0x0E, 0x91, 0x0D, 0x90, 0x08, 0x63, 0x00, 0xEF, 0xFA, 0x63, 0x0B, 0x62,
+	0x0A, 0xD1, 0x09, 0xD0, 0xFF, 0x6A, 0x8C, 0xEA, 0x50, 0x68, 0x18, 0xEA, 0x04, 0xD2, 0x30, 0xF0,
+	0x20, 0x6A, 0x20, 0xF2, 0x18, 0x4A, 0x12, 0xE8, 0x01, 0xE2, 0x84, 0xA0, 0x0F, 0x5C, 0x35, 0x60,
+	0x30, 0xF0, 0x21, 0x6A, 0x88, 0x33, 0x50, 0xF5, 0x00, 0x4A, 0x69, 0xE2, 0x40, 0x9A, 0x00, 0xEA,
+	0x1B, 0x6A, 0x1D, 0x10, 0x20, 0xF0, 0x60, 0xA0, 0x3D, 0x6A, 0x47, 0xC0, 0x08, 0x6A, 0x4B, 0xEA,
+	0x6C, 0xEA, 0x02, 0x6B, 0x6D, 0xEA, 0x20, 0xF0, 0x40, 0xC0, 0x03, 0x69, 0x26, 0x10, 0x13, 0x6A,
+	0x01, 0x10, 0x33, 0x6A, 0x20, 0xF0, 0x60, 0xA0, 0x47, 0xC0, 0x08, 0x6A, 0x4B, 0xEA, 0x6C, 0xEA,
+	0x01, 0x6B, 0x6D, 0xEA, 0x17, 0x10, 0x0B, 0x6A, 0x47, 0xC0, 0x0F, 0x10, 0x47, 0x6A, 0x20, 0xF0,
+	0x60, 0xA0, 0x47, 0xC0, 0x08, 0x6A, 0x4B, 0xEA, 0x6C, 0xEA, 0x03, 0x6B, 0x6D, 0xEA, 0x20, 0xF0,
+	0x40, 0xC0, 0x23, 0x67, 0x0A, 0x10, 0x23, 0x6A, 0xF2, 0x17, 0x20, 0xF0, 0x60, 0xA0, 0x08, 0x6A,
+	0x4B, 0xEA, 0x6C, 0xEA, 0x20, 0xF0, 0x40, 0xC0, 0x02, 0x69, 0x04, 0x92, 0x8C, 0x34, 0x4C, 0x35,
+	0x30, 0xF0, 0x21, 0x6A, 0x91, 0xF2, 0x54, 0x9A, 0x55, 0xE5, 0x30, 0xF0, 0x21, 0x6A, 0x90, 0xF5,
+	0x10, 0x4A, 0x91, 0xE2, 0xE5, 0x67, 0xFD, 0x65, 0x00, 0x6A, 0x06, 0xD5, 0x06, 0x95, 0x48, 0x33,
+	0xC0, 0x9C, 0xAD, 0xE3, 0x60, 0x9B, 0xCC, 0xEB, 0x20, 0xF0, 0xC5, 0xA0, 0x1E, 0x65, 0xB8, 0x67,
+	0x03, 0x6E, 0xAC, 0xEE, 0x02, 0x76, 0x07, 0x61, 0xFF, 0x6E, 0x4C, 0xEE, 0x01, 0x76, 0x03, 0x61,
+	0x41, 0x6E, 0xCB, 0xEE, 0xCC, 0xEB, 0x48, 0x36, 0xF5, 0xE6, 0x60, 0xDD, 0x01, 0x4A, 0x7F, 0x67,
+	0x79, 0xE6, 0x02, 0x72, 0x60, 0x9E, 0x04, 0x4C, 0xE1, 0x61, 0x04, 0x95, 0x30, 0xF0, 0x21, 0x6B,
+	0x91, 0xF2, 0x74, 0x9B, 0xAC, 0x32, 0x04, 0x94, 0x6D, 0xE2, 0xA0, 0x9B, 0x30, 0xF0, 0x21, 0x6B,
+	0x91, 0xF2, 0x68, 0x9B, 0x69, 0xE2, 0xC0, 0x9A, 0x30, 0xF0, 0x20, 0x6A, 0xCF, 0xF6, 0x48, 0x9A,
+	0x40, 0xEA, 0x20, 0xF0, 0x65, 0xA0, 0x04, 0x94, 0x03, 0x6F, 0x6A, 0x33, 0xA2, 0x67, 0x6C, 0xEF,
+	0x00, 0x6E, 0x80, 0x18, 0x07, 0xC5, 0x22, 0xC0, 0x30, 0xF0, 0x20, 0x6A, 0x04, 0x94, 0xCF, 0xF6,
+	0x4C, 0x9A, 0x40, 0xEA, 0x30, 0xF0, 0x20, 0x6A, 0xAF, 0xF6, 0x50, 0x9A, 0x40, 0xEA, 0x30, 0xF0,
+	0x20, 0x6A, 0xC0, 0xF1, 0x08, 0x4A, 0xE5, 0xF0, 0x7C, 0x9A, 0x01, 0x6C, 0x8C, 0xEB, 0x0D, 0x23,
+	0x05, 0xF1, 0x40, 0x9A, 0x05, 0x5A, 0x09, 0x61, 0xA0, 0xA0, 0xC1, 0xA0, 0xE2, 0xA0, 0x30, 0xF0,
+	0x21, 0x6C, 0x11, 0xF7, 0x08, 0x4C, 0x80, 0x18, 0x77, 0xC2, 0x0B, 0x97, 0x0A, 0x91, 0x09, 0x90,
+	0x06, 0x63, 0x00, 0xEF, 0xFB, 0x63, 0x09, 0x62, 0x08, 0xD1, 0x07, 0xD0, 0x30, 0xF0, 0x21, 0x6A,
+	0x91, 0xF2, 0x5C, 0x9A, 0xFF, 0x6C, 0x60, 0xA2, 0x20, 0x6A, 0x6C, 0xEA, 0x3F, 0x22, 0x30, 0xF0,
+	0x20, 0x6A, 0xC0, 0xF1, 0x08, 0x4A, 0xE5, 0xF0, 0xB3, 0xA2, 0x04, 0x6B, 0x00, 0x68, 0xAD, 0xEB,
+	0xE5, 0xF0, 0x73, 0xC2, 0x30, 0xF0, 0x21, 0x6A, 0xB1, 0xF2, 0x54, 0x9A, 0x20, 0xA2, 0x30, 0xF0,
+	0x21, 0x6A, 0xF1, 0xF0, 0x50, 0x9A, 0x8C, 0xE9, 0x40, 0xA2, 0x4C, 0xEC, 0x04, 0xD4, 0x03, 0x6B,
+	0x78, 0xE8, 0x30, 0xF0, 0x21, 0x6A, 0x32, 0xF6, 0x04, 0x4A, 0x12, 0xEB, 0x4D, 0xE3, 0x80, 0xA3,
+	0x01, 0x6A, 0x8C, 0xEA, 0x03, 0x22, 0x02, 0x6A, 0x8D, 0xEA, 0x40, 0xC3, 0x03, 0x6B, 0x78, 0xE8,
+	0x30, 0xF0, 0x21, 0x6A, 0x32, 0xF6, 0x04, 0x4A, 0x00, 0x6E, 0xF1, 0x67, 0x12, 0xEB, 0x4D, 0xE3,
+	0x80, 0xA3, 0x01, 0x6A, 0x8D, 0xEA, 0x40, 0xC3, 0x04, 0x95, 0x90, 0x67, 0x01, 0x48, 0x80, 0x18,
+	0x07, 0xC5, 0xFF, 0x6A, 0x4C, 0xE8, 0x80, 0x70, 0xDA, 0x61, 0x0B, 0x10, 0x30, 0xF0, 0x20, 0x6A,
+	0xC0, 0xF1, 0x08, 0x4A, 0xE5, 0xF0, 0x93, 0xA2, 0x05, 0x6B, 0x6B, 0xEB, 0x8C, 0xEB, 0xE5, 0xF0,
+	0x73, 0xC2, 0x80, 0x18, 0xBF, 0xC4, 0x30, 0xF0, 0x20, 0x6A, 0xAF, 0xF6, 0x50, 0x9A, 0x40, 0xEA,
+	0x09, 0x97, 0x08, 0x91, 0x07, 0x90, 0x05, 0x63, 0x00, 0xEF, 0x00, 0x65, 0xFD, 0x63, 0x05, 0x62,
+	0x04, 0xD0, 0xFF, 0x6A, 0x8C, 0xEA, 0x50, 0x6B, 0x78, 0xEA, 0x30, 0xF0, 0x20, 0x6C, 0x20, 0xF2,
+	0x18, 0x4C, 0x03, 0x6E, 0x12, 0xEB, 0x6D, 0xE4, 0x20, 0xF0, 0xE6, 0xA3, 0x20, 0xF0, 0x05, 0xA3,
+	0x9F, 0xA3, 0xEC, 0xEE, 0xC8, 0x37, 0x0D, 0x6E, 0xCB, 0xEE, 0x0C, 0xEE, 0xED, 0xEE, 0xA0, 0xA3,
+	0x20, 0xF0, 0xC5, 0xC3, 0x7F, 0x6E, 0x8C, 0xEE, 0xC3, 0xED, 0x01, 0x60, 0x85, 0x67, 0xDF, 0xA3,
+	0x80, 0x6D, 0xAB, 0xED, 0xCC, 0xED, 0x20, 0xF0, 0xE5, 0xA3, 0x8D, 0xED, 0x00, 0xF6, 0xA0, 0x35,
+	0x82, 0x67, 0x00, 0xF6, 0xA3, 0x35, 0xFF, 0x6A, 0x4C, 0xED, 0xEA, 0x37, 0x03, 0x6A, 0x4C, 0xEF,
+	0x00, 0x6E, 0x80, 0x18, 0x07, 0xC5, 0x05, 0x97, 0x04, 0x90, 0x03, 0x63, 0x00, 0xEF, 0x00, 0x65,
+	0xF8, 0x63, 0x0F, 0x62, 0x0E, 0xD1, 0x0D, 0xD0, 0xFF, 0x6A, 0x4C, 0xEC, 0x50, 0x68, 0x18, 0xEC,
+	0x4C, 0xED, 0x08, 0xD4, 0x0A, 0xD5, 0x94, 0x35, 0x30, 0xF0, 0x21, 0x6C, 0x91, 0xF2, 0x80, 0x9C,
+	0x7F, 0x6E, 0x30, 0xF0, 0x20, 0x6B, 0x91, 0xE5, 0x80, 0xA4, 0x20, 0xF2, 0x18, 0x4B, 0xA4, 0x67,
+	0x4C, 0xED, 0x04, 0xD5, 0xCC, 0xED, 0x05, 0xD5, 0x12, 0xE8, 0x01, 0xE3, 0x80, 0xA0, 0x90, 0x4B,
+	0x06, 0xD4, 0x20, 0xF0, 0x85, 0xA0, 0x92, 0x35, 0x09, 0xD5, 0x09, 0x96, 0x03, 0x6D, 0x8A, 0x34,
+	0xAC, 0xEC, 0xAC, 0xEE, 0x4C, 0xEE, 0x8C, 0xEA, 0x07, 0xD2, 0x5D, 0x67, 0xA7, 0x42, 0x09, 0x4D,
+	0x40, 0xA5, 0x09, 0xD6, 0x20, 0xF0, 0xA6, 0xA0, 0x5F, 0xC0, 0x04, 0x6A, 0x4B, 0xEA, 0xAC, 0xEA,
+	0x8D, 0xEA, 0x01, 0x6C, 0x8B, 0xEC, 0x20, 0xF0, 0xA7, 0xA0, 0x85, 0xC0, 0x86, 0xC0, 0x11, 0x6C,
+	0x8B, 0xEC, 0xAC, 0xEC, 0x20, 0xF0, 0x87, 0xC0, 0x80, 0x6C, 0x8B, 0xEC, 0x8D, 0xEA, 0x67, 0x4C,
+	0x8C, 0xEA, 0x20, 0xF0, 0x46, 0xC0, 0xE5, 0xF0, 0x5C, 0x9B, 0x04, 0x6C, 0x8C, 0xEA, 0x0B, 0x22,
+	0x05, 0xF1, 0x40, 0x9B, 0x05, 0x5A, 0x07, 0x61, 0x04, 0x95, 0x30, 0xF0, 0x21, 0x6C, 0x31, 0xF7,
+	0x00, 0x4C, 0x80, 0x18, 0x77, 0xC2, 0x05, 0x93, 0x06, 0x94, 0x83, 0xEB, 0x6D, 0x60, 0x2D, 0x73,
+	0x16, 0x61, 0x20, 0xF0, 0x45, 0xA0, 0x03, 0x6B, 0x07, 0x95, 0x83, 0x67, 0x4C, 0xEC, 0x82, 0xED,
+	0x13, 0x60, 0xFF, 0x6C, 0x01, 0x4D, 0x8C, 0xED, 0xAC, 0xEB, 0xFF, 0xF6, 0x14, 0x4C, 0x68, 0x33,
+	0x4C, 0xEC, 0x6D, 0xEC, 0x07, 0xD5, 0x2C, 0x69, 0x20, 0xF0, 0x85, 0xC0, 0x0B, 0x11, 0x05, 0x96,
+	0x2D, 0x69, 0x2C, 0x76, 0x00, 0xF1, 0x06, 0x60, 0x08, 0x94, 0x04, 0x95, 0x80, 0x18, 0xB4, 0xC3,
+	0xFF, 0x72, 0x22, 0x67, 0x09, 0x61, 0x05, 0x92, 0x05, 0x91, 0x1D, 0x4A, 0x04, 0xD2, 0x04, 0x93,
+	0xFF, 0x6A, 0x4C, 0xEB, 0x04, 0xD3, 0x15, 0x10, 0x30, 0xF0, 0x20, 0x6A, 0xC0, 0xF1, 0x08, 0x4A,
+	0xE5, 0xF0, 0x7C, 0x9A, 0x04, 0x6C, 0x8C, 0xEB, 0x33, 0x23, 0x05, 0xF1, 0x40, 0x9A, 0x05, 0x5A,
+	0x2F, 0x61, 0x30, 0xF0, 0x21, 0x6C, 0x31, 0xF7, 0x0C, 0x4C, 0x27, 0x10, 0x01, 0x49, 0xFF, 0x6A,
+	0x4C, 0xE9, 0x08, 0x96, 0x09, 0x97, 0x91, 0x67, 0x00, 0x6D, 0x80, 0x18, 0x00, 0xC4, 0xFF, 0x72,
+	0x0A, 0x61, 0x06, 0x94, 0x83, 0xE9, 0x02, 0x61, 0x24, 0x67, 0x06, 0x10, 0x04, 0x95, 0xAA, 0xE9,
+	0xED, 0x61, 0xFF, 0x69, 0x01, 0x10, 0x22, 0x67, 0x30, 0xF0, 0x20, 0x6A, 0xC0, 0xF1, 0x08, 0x4A,
+	0xE5, 0xF0, 0x7C, 0x9A, 0x04, 0x6C, 0x8C, 0xEB, 0x0B, 0x23, 0x05, 0xF1, 0x40, 0x9A, 0x05, 0x5A,
+	0x07, 0x61, 0x30, 0xF0, 0x21, 0x6C, 0x31, 0xF7, 0x1C, 0x4C, 0xB1, 0x67, 0x80, 0x18, 0x77, 0xC2,
+	0x00, 0x6E, 0x04, 0xD0, 0x05, 0xD6, 0x45, 0x10, 0x05, 0x92, 0x06, 0x93, 0x6E, 0xEA, 0x26, 0x2A,
+	0x30, 0xF0, 0x20, 0x6A, 0xC0, 0xF1, 0x08, 0x4A, 0xE5, 0xF0, 0x7C, 0x9A, 0x04, 0x6C, 0x8C, 0xEB,
+	0x0B, 0x23, 0x05, 0xF1, 0x40, 0x9A, 0x05, 0x5A, 0x07, 0x61, 0x04, 0x95, 0x30, 0xF0, 0x21, 0x6C,
+	0x51, 0xF7, 0x0C, 0x4C, 0x80, 0x18, 0x77, 0xC2, 0x20, 0xF0, 0x86, 0xA0, 0x04, 0x6A, 0xFF, 0x6B,
+	0x8C, 0xEA, 0xA0, 0xF0, 0x10, 0x22, 0x04, 0x92, 0x80, 0x69, 0x2B, 0xE9, 0x2C, 0xEA, 0x6C, 0xEA,
+	0xA0, 0xF0, 0x09, 0x2A, 0x06, 0x94, 0x8D, 0xE9, 0x6C, 0xE9, 0x8C, 0x10, 0x30, 0xF0, 0x20, 0x6A,
+	0xC0, 0xF1, 0x08, 0x4A, 0xE5, 0xF0, 0x7C, 0x9A, 0x04, 0x6C, 0x8C, 0xEB, 0x0B, 0x23, 0x05, 0xF1,
+	0x40, 0x9A, 0x05, 0x5A, 0x07, 0x61, 0x04, 0x95, 0x30, 0xF0, 0x21, 0x6C, 0x51, 0xF7, 0x1C, 0x4C,
+	0x80, 0x18, 0x77, 0xC2, 0xBD, 0x67, 0xC7, 0x45, 0x11, 0x4E, 0xA0, 0xA6, 0xBF, 0xC0, 0x06, 0x91,
+	0xB7, 0x17, 0x05, 0x96, 0x06, 0x2E, 0x08, 0x94, 0xB1, 0x67, 0x80, 0x18, 0x6E, 0xC4, 0x22, 0x67,
+	0x07, 0x10, 0x04, 0x92, 0x08, 0x94, 0xA4, 0xA2, 0x80, 0x18, 0x6E, 0xC4, 0x04, 0x93, 0x44, 0xC3,
+	0x05, 0x94, 0x04, 0x95, 0xFF, 0x6B, 0x01, 0x4C, 0x6C, 0xEC, 0x01, 0x4D, 0x03, 0x74, 0x05, 0xD4,
+	0x04, 0xD5, 0xE7, 0x61, 0x86, 0xA0, 0x43, 0x67, 0xA5, 0xA0, 0x8E, 0xEA, 0x4B, 0xEA, 0xC0, 0xF7,
+	0x42, 0x32, 0xFF, 0x75, 0x02, 0x4A, 0x06, 0x61, 0x85, 0xC0, 0x01, 0x6C, 0x8B, 0xEC, 0xFF, 0x4A,
+	0x86, 0xC0, 0x6C, 0xEA, 0xFF, 0x71, 0x07, 0x61, 0x01, 0x6B, 0x6B, 0xEB, 0x25, 0xA0, 0xFF, 0x4A,
+	0x65, 0xC0, 0xFF, 0x6B, 0x6C, 0xEA, 0x20, 0xF0, 0x86, 0xA0, 0x03, 0x6B, 0xFF, 0x4A, 0x6C, 0xEA,
+	0xE4, 0x4B, 0x4C, 0x32, 0x8C, 0xEB, 0x4D, 0xEB, 0x30, 0xF0, 0x20, 0x6A, 0x20, 0xF0, 0x66, 0xC0,
+	0xC0, 0xF1, 0x08, 0x4A, 0xE5, 0xF0, 0x7C, 0x9A, 0x04, 0x6C, 0x8C, 0xEB, 0x0D, 0x23, 0x05, 0xF1,
+	0x40, 0x9A, 0x05, 0x5A, 0x09, 0x61, 0xC5, 0xA0, 0xE6, 0xA0, 0x30, 0xF0, 0x21, 0x6C, 0x71, 0xF7,
+	0x08, 0x4C, 0xB1, 0x67, 0x80, 0x18, 0x77, 0xC2, 0x30, 0xF0, 0x20, 0x6A, 0xC0, 0xF1, 0x08, 0x4A,
+	0xE5, 0xF0, 0x7C, 0x9A, 0x04, 0x6C, 0x8C, 0xEB, 0x13, 0x23, 0x05, 0xF1, 0x40, 0x9A, 0x05, 0x5A,
+	0x0F, 0x61, 0x20, 0xF0, 0x46, 0xA0, 0x40, 0xF0, 0xA4, 0xA0, 0x40, 0xF0, 0xC5, 0xA0, 0x4E, 0x32,
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+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x06, 0x24, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+};
+u32 array_length_mp_8821c_fw_nic = 106920;
+
+
+#endif
+
+void
+odm_read_firmware_mp_8821c_fw_nic(
+	struct PHY_DM_STRUCT    *p_dm_odm,
+	u8       *p_firmware,
+	u32       *p_firmware_size
+)
+{
+#if (DM_ODM_SUPPORT_TYPE & (ODM_CE))
+	*((SIZE_PTR *)p_firmware) = (SIZE_PTR)array_mp_8821c_fw_nic;
+#else
+	odm_move_memory(p_dm_odm, p_firmware, array_mp_8821c_fw_nic, array_length_mp_8821c_fw_nic);
+#endif
+	*p_firmware_size = array_length_mp_8821c_fw_nic;
+}
+
+#ifndef LOAD_FW_HEADER_FROM_DRIVER
+u8 array_mp_8821c_fw_wowlan[] = {
+	0x21, 0x88, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x74, 0x34, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x06, 0x15, 0x12, 0x0B, 0xE0, 0x07, 0x00, 0x00, 0x18, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x20, 0x80, 0xC8, 0x8A, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0xD8, 0xB2, 0x00, 0x00, 0x00, 0x50, 0x00, 0x00, 0x00, 0x00, 0x10, 0x80, 0x00, 0x00, 0x03, 0x80,
+	0x00, 0x00, 0x04, 0x04, 0x08, 0x08, 0x08, 0x08, 0x0C, 0x0C, 0x0C, 0x0C, 0x0C, 0x0C, 0x0C, 0x0C,
+	0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10,
+	0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14,
+	0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14,
+	0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18,
+	0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18,
+	0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18,
+	0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18,
+	0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C,
+	0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C,
+	0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C,
+	0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C,
+	0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C,
+	0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C,
+	0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C,
+	0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x01, 0xFE, 0x03, 0x01, 0x01, 0xFE,
+	0x03, 0x02, 0x01, 0xFE, 0x03, 0x03, 0x01, 0xFE, 0x03, 0x04, 0x01, 0xFE, 0x03, 0x05, 0x01, 0xFE,
+	0x03, 0x06, 0x01, 0xFE, 0x03, 0x07, 0x01, 0xFE, 0x06, 0x00, 0x00, 0x00, 0x05, 0x00, 0x00, 0x00,
+	0x01, 0x00, 0x00, 0x01, 0x40, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x01, 0x00, 0x03, 0x80,
+	0x7D, 0x01, 0x03, 0x80, 0x7D, 0x01, 0x03, 0x80, 0x45, 0x74, 0x03, 0x80, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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+	0x0A, 0x16, 0x64, 0xB8, 0x7B, 0x05, 0x64, 0xB8, 0x60, 0x16, 0x64, 0xB8, 0x0D, 0x00, 0x78, 0xB8,
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+	0x24, 0x01, 0x64, 0xB8, 0x18, 0x06, 0x60, 0xB8, 0x18, 0x06, 0x64, 0xB8, 0x10, 0x06, 0x60, 0xB8,
+	0x10, 0x06, 0x64, 0xB8, 0x04, 0x00, 0x78, 0xB8, 0x38, 0x00, 0x78, 0xB8, 0x7A, 0x00, 0x78, 0xB8,
+	0x60, 0x00, 0x78, 0xB8, 0xE3, 0x10, 0x60, 0xB8, 0x54, 0x00, 0x78, 0xB8, 0xE0, 0x10, 0x60, 0xB8,
+	0x4D, 0x01, 0x64, 0xB8, 0x00, 0x01, 0x64, 0xB8, 0xE0, 0x04, 0x64, 0xB8, 0x18, 0x11, 0x64, 0xB8,
+	0xFF, 0xFF, 0x03, 0x00, 0x00, 0x00, 0x70, 0x18, 0x1C, 0x01, 0x64, 0xB8, 0x09, 0x06, 0x64, 0xB8,
+	0x70, 0x00, 0x78, 0xB8, 0xC8, 0x01, 0x64, 0xB8, 0xA5, 0xA5, 0xA5, 0xA5, 0x88, 0x00, 0x60, 0xB8,
+	0x89, 0x00, 0x60, 0xB8, 0x8A, 0x00, 0x60, 0xB8, 0x8B, 0x00, 0x60, 0xB8, 0x00, 0x00, 0x00, 0x03,
+	0x00, 0x00, 0x00, 0x60, 0xE0, 0x00, 0x60, 0xB8, 0xFF, 0xFF, 0xFF, 0xFD, 0xE3, 0x00, 0x60, 0xB8,
+	0x00, 0x00, 0x00, 0x01, 0xE1, 0x00, 0x60, 0xB8, 0x00, 0x00, 0x00, 0x04, 0xFF, 0xFF, 0xFF, 0xFB,
+	0xFF, 0xFF, 0xFF, 0xDF, 0xFF, 0xFF, 0xFF, 0x1F, 0x04, 0x00, 0x60, 0xB8, 0x04, 0x00, 0x64, 0xB8,
+	0x08, 0x00, 0x60, 0xB8, 0x08, 0x00, 0x64, 0xB8, 0xF8, 0x10, 0x60, 0xB8, 0xE8, 0x12, 0x64, 0xB8,
+	0x00, 0x0C, 0x01, 0x00, 0x01, 0x00, 0x66, 0xB8, 0x00, 0x00, 0x7F, 0x00, 0x00, 0x00, 0x00, 0xFF,
+	0xFF, 0xFF, 0x0F, 0x00, 0xFF, 0xFF, 0xFF, 0x0F, 0x00, 0x00, 0x30, 0x00, 0x00, 0x00, 0xC0, 0x00,
+	0x00, 0xFF, 0xF9, 0xFF, 0x00, 0x00, 0xFE, 0x1F, 0xFF, 0xFF, 0xF7, 0xFF, 0xFF, 0xFC, 0xFE, 0xFF,
+	0x00, 0x01, 0x01, 0x00, 0x96, 0x02, 0x64, 0xB8, 0x00, 0x00, 0x70, 0xB8, 0x18, 0x00, 0x70, 0xB8,
+	0x0B, 0x00, 0x70, 0xB8, 0x02, 0x00, 0x70, 0xB8, 0x94, 0x02, 0x64, 0xB8, 0x97, 0x02, 0x64, 0xB8,
+	0x00, 0x00, 0x78, 0x18, 0x30, 0x00, 0x78, 0x18, 0x54, 0x02, 0x64, 0xB8, 0x50, 0x02, 0x64, 0xB8,
+	0x4C, 0x02, 0x64, 0xB8, 0x48, 0x02, 0x64, 0xB8, 0x44, 0x02, 0x64, 0xB8, 0xCC, 0x01, 0x64, 0xB8,
+	0x64, 0x05, 0x64, 0xB8, 0x30, 0x01, 0x64, 0xB8, 0x1F, 0x00, 0x60, 0xB8, 0xC9, 0x01, 0x64, 0xB8,
+	0xA0, 0x01, 0x64, 0xB8, 0x44, 0x00, 0x60, 0xB8, 0x60, 0x00, 0x60, 0xB8, 0xFF, 0xFF, 0xFF, 0x00,
+	0x00, 0x00, 0x00, 0x05, 0x64, 0x01, 0x64, 0xB8, 0x53, 0x05, 0x64, 0xB8, 0x77, 0x05, 0x64, 0xB8,
+	0x68, 0x05, 0x64, 0xB8, 0x94, 0x01, 0x64, 0xB8, 0x00, 0x00, 0x66, 0xB8, 0x00, 0x10, 0x66, 0xB8,
+	0x00, 0x1C, 0x66, 0xB8, 0x9A, 0x01, 0x64, 0xB8, 0x99, 0x01, 0x64, 0xB8, 0xC6, 0x01, 0x64, 0xB8,
+	0x20, 0x01, 0x64, 0xB8, 0x24, 0x11, 0x64, 0xB8, 0x20, 0x11, 0x64, 0xB8, 0x2C, 0x11, 0x64, 0xB8,
+	0x28, 0x11, 0x64, 0xB8, 0x34, 0x11, 0x64, 0xB8, 0x30, 0x11, 0x64, 0xB8, 0x38, 0x01, 0x64, 0xB8,
+	0x3C, 0x11, 0x64, 0xB8, 0x38, 0x11, 0x64, 0xB8, 0xE4, 0x11, 0x64, 0xB8, 0xE0, 0x11, 0x64, 0xB8,
+	0x50, 0x00, 0x60, 0xB8, 0x54, 0x00, 0x60, 0xB8, 0x00, 0x40, 0xE0, 0x03, 0x01, 0x60, 0x00, 0x03,
+	0xE0, 0x12, 0x64, 0xB8, 0xE3, 0x04, 0x64, 0xB8, 0x2F, 0x01, 0x64, 0xB8, 0x00, 0x28, 0x64, 0xB8,
+	0x00, 0x2C, 0x64, 0xB8, 0x00, 0x38, 0x64, 0xB8, 0x00, 0x3C, 0x64, 0xB8, 0x00, 0x03, 0x07, 0x00,
+	0xFF, 0x03, 0x07, 0x00, 0x54, 0x04, 0x64, 0xB8, 0x68, 0x06, 0x64, 0xB8, 0x69, 0x06, 0x64, 0xB8,
+	0xC3, 0x03, 0x30, 0x00, 0x00, 0x02, 0x30, 0x00, 0x00, 0x00, 0x1C, 0x00, 0x00, 0x00, 0x10, 0x00,
+	0x01, 0x02, 0x30, 0x00, 0x00, 0x00, 0x00, 0xF0, 0x00, 0x00, 0xC0, 0x03, 0x00, 0x00, 0x80, 0x01,
+	0x02, 0x02, 0x30, 0x00, 0x00, 0x00, 0x40, 0x01, 0x77, 0x77, 0x77, 0x77, 0x00, 0x00, 0xF0, 0x3F,
+	0x70, 0x77, 0x33, 0x54, 0x17, 0x77, 0x33, 0x77, 0x77, 0x77, 0x33, 0x77, 0x17, 0x77, 0x33, 0x54,
+	0x00, 0x00, 0xFF, 0x00, 0x00, 0x00, 0x33, 0x00, 0x83, 0x04, 0x64, 0xB8, 0xF8, 0x05, 0x64, 0xB8,
+	0xF9, 0x05, 0x64, 0xB8, 0xFA, 0x05, 0x64, 0xB8, 0xFB, 0x05, 0x64, 0xB8, 0x83, 0x00, 0x60, 0xB8,
+	0x08, 0x01, 0x64, 0xB8, 0x90, 0x00, 0x60, 0xB8, 0x92, 0x00, 0x60, 0xB8, 0x92, 0x06, 0x64, 0xB8,
+	0xFF, 0xFF, 0xFF, 0x7F, 0x20, 0x00, 0x78, 0xB8, 0x10, 0x00, 0x78, 0xB8, 0x03, 0x00, 0x78, 0xB8,
+	0xFF, 0xFF, 0x01, 0xFF, 0x1F, 0x07, 0x64, 0xB8, 0x1C, 0x07, 0x64, 0xB8, 0x40, 0x00, 0x00, 0xB5,
+	0x44, 0x00, 0x00, 0xB5, 0x48, 0x00, 0x00, 0xB5, 0x4C, 0x00, 0x00, 0xB5, 0xE4, 0x10, 0x60, 0xB8,
+	0xE8, 0x10, 0x60, 0xB8, 0xEC, 0x10, 0x60, 0xB8, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x20, 0x00,
+	0x00, 0x00, 0x40, 0x00, 0x00, 0x00, 0x80, 0x00, 0xF4, 0x00, 0x60, 0xB8, 0x98, 0x01, 0x64, 0xB8,
+	0xFF, 0xFF, 0xC0, 0xFF, 0x40, 0x01, 0x00, 0x80, 0xFF, 0x17, 0xC0, 0xFF, 0x00, 0x88, 0x00, 0x80,
+	0x02, 0x00, 0x60, 0xB8, 0x01, 0x01, 0x64, 0xB8, 0xB7, 0x06, 0x64, 0xB8, 0xB4, 0x06, 0x64, 0xB8,
+	0xF0, 0xFF, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7E, 0x28, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x30, 0xF0, 0x21, 0x6C, 0x18, 0xF0, 0x00, 0x4C, 0xBC, 0x65, 0x1F, 0xF7, 0x00, 0x6C, 0x8C, 0xB9,
+	0x00, 0x65, 0x00, 0x65, 0x00, 0x65, 0x30, 0xF0, 0x20, 0x6C, 0xC0, 0xF1, 0x08, 0x4C, 0x00, 0x6E,
+	0x30, 0xF0, 0x21, 0x6F, 0x70, 0xF0, 0x05, 0x4F, 0xC0, 0xDC, 0x04, 0x4C, 0xE3, 0xEC, 0xB8, 0x67,
+	0xFB, 0x2D, 0x30, 0xF0, 0x21, 0x6C, 0x51, 0xF4, 0x14, 0x4C, 0x00, 0x6E, 0x30, 0xF0, 0x21, 0x6F,
+	0x91, 0xF4, 0x18, 0x4F, 0xC0, 0xDC, 0x04, 0x4C, 0xE3, 0xEC, 0xB8, 0x67, 0xFB, 0x2D, 0x10, 0xF0,
+	0x23, 0x6C, 0x40, 0xF0, 0x19, 0x4C, 0x00, 0xEC, 0xFD, 0x63, 0x05, 0x62, 0x30, 0xF0, 0x21, 0x6A,
+	0xD0, 0xF4, 0x58, 0x9A, 0x10, 0xF0, 0x23, 0x6B, 0x40, 0xF0, 0x19, 0x4B, 0x60, 0xDA, 0x00, 0x18,
+	0x72, 0xC7, 0x00, 0x18, 0xA6, 0xC7, 0x00, 0x18, 0xEC, 0xC9, 0x00, 0x18, 0xDA, 0xC7, 0x00, 0x18,
+	0x08, 0xCA, 0x00, 0x18, 0x9A, 0xCA, 0x30, 0xF0, 0x21, 0x6A, 0x10, 0xF0, 0x48, 0x9A, 0x40, 0xEA,
+	0x30, 0xF0, 0x20, 0x6A, 0x80, 0xF1, 0x08, 0x4A, 0x30, 0xF0, 0x21, 0x6B, 0x15, 0xF0, 0x00, 0x4B,
+	0x63, 0xDA, 0x30, 0xF0, 0x21, 0x6A, 0x10, 0xF0, 0x54, 0x9A, 0x30, 0xF0, 0x20, 0x6B, 0x80, 0xF1,
+	0x08, 0x4B, 0x83, 0x67, 0x00, 0x6D, 0x40, 0xEA, 0x62, 0x67, 0x30, 0xF0, 0x20, 0x6A, 0x4F, 0xF3,
+	0x68, 0xDA, 0x30, 0xF0, 0x21, 0x6A, 0x50, 0xF0, 0x44, 0x9A, 0x30, 0xF0, 0x21, 0x6B, 0x70, 0xF3,
+	0x14, 0x4B, 0x83, 0x67, 0x01, 0x6D, 0x40, 0xEA, 0x62, 0x67, 0x30, 0xF0, 0x21, 0x6A, 0x91, 0xF4,
+	0x70, 0xDA, 0x30, 0xF0, 0x21, 0x6A, 0x70, 0xF0, 0x08, 0x4A, 0x30, 0xF0, 0x21, 0x6B, 0x15, 0xF4,
+	0x00, 0x4B, 0x63, 0xDA, 0x30, 0xF0, 0x21, 0x6A, 0x10, 0xF0, 0x54, 0x9A, 0x30, 0xF0, 0x21, 0x6B,
+	0x70, 0xF0, 0x08, 0x4B, 0x83, 0x67, 0x00, 0x6D, 0x40, 0xEA, 0x62, 0x67, 0x30, 0xF0, 0x21, 0x6A,
+	0x91, 0xF4, 0x6C, 0xDA, 0x30, 0xF0, 0x21, 0x6A, 0xD0, 0xF4, 0x4C, 0x9A, 0x30, 0xF0, 0x21, 0x6B,
+	0xD0, 0xF4, 0x6C, 0x9B, 0x80, 0xAB, 0xFF, 0xF7, 0x1F, 0x6B, 0x6C, 0xEC, 0x10, 0xF0, 0x00, 0x6B,
+	0x6B, 0xEB, 0x6D, 0xEC, 0xFF, 0xF7, 0x1F, 0x6B, 0x8C, 0xEB, 0x60, 0xCA, 0x00, 0x1C, 0x8B, 0x2C,
+	0x30, 0xF0, 0x21, 0x6A, 0x10, 0xF0, 0x4C, 0x9A, 0x40, 0xEA, 0xFF, 0x17, 0xFD, 0x63, 0x05, 0x62,
+	0x30, 0xF0, 0x20, 0x6B, 0x2F, 0xF3, 0x58, 0x9B, 0x01, 0x4A, 0x10, 0x72, 0x2F, 0xF3, 0x58, 0xDB,
+	0x09, 0x61, 0x30, 0xF0, 0x21, 0x6A, 0x30, 0xF0, 0x21, 0x6B, 0x50, 0xF0, 0x4C, 0x9A, 0xD1, 0xF2,
+	0x8C, 0x9B, 0x40, 0xEA, 0x05, 0x97, 0x03, 0x63, 0x00, 0xEF, 0x00, 0x65, 0x2D, 0xB8, 0x7C, 0x68,
+	0x2C, 0xE8, 0x07, 0x28, 0x00, 0x65, 0x10, 0xF0, 0x23, 0x68, 0x80, 0xF1, 0x1F, 0x48, 0x00, 0xE8,
+	0x00, 0x65, 0x10, 0xF0, 0x23, 0x68, 0x25, 0xF2, 0x01, 0x48, 0x00, 0xE8, 0x00, 0x65, 0x0C, 0xB8,
+	0x2C, 0xE8, 0x02, 0x30, 0x00, 0xF0, 0x20, 0x69, 0x01, 0x49, 0x0C, 0xE9, 0x08, 0x21, 0x00, 0x65,
+	0x30, 0xF0, 0x20, 0x68, 0x0F, 0xF7, 0x18, 0x48, 0x00, 0x98, 0x00, 0xE8, 0x00, 0x65, 0x30, 0xF0,
+	0x20, 0x69, 0xCF, 0xF3, 0x04, 0x49, 0x20, 0x99, 0x07, 0x29, 0x00, 0x65, 0x10, 0xF0, 0x23, 0x69,
+	0xE0, 0xF2, 0x0F, 0x49, 0x00, 0xE9, 0x00, 0x65, 0x30, 0xF0, 0x20, 0x69, 0x0F, 0xF7, 0x1C, 0x49,
+	0x20, 0x99, 0x00, 0xE9, 0x00, 0x65, 0x30, 0xF0, 0x20, 0x68, 0x2F, 0xF3, 0x14, 0x48, 0x00, 0xF0,
+	0x20, 0x69, 0x01, 0x49, 0x20, 0xD8, 0x2D, 0xB8, 0x00, 0xF0, 0x20, 0x68, 0x00, 0xF1, 0x00, 0x48,
+	0x0F, 0xE8, 0x0C, 0xE9, 0xA9, 0xB9, 0x00, 0x65, 0x00, 0x65, 0x00, 0x65, 0x40, 0xEB, 0x00, 0x65,
+	0x30, 0xF0, 0x20, 0x68, 0x4F, 0xF3, 0x10, 0x48, 0x20, 0x98, 0x01, 0x98, 0x2A, 0xE8, 0x0C, 0x61,
+	0x00, 0x65, 0x30, 0xF0, 0x20, 0x68, 0x2F, 0xF3, 0x14, 0x48, 0x00, 0xF0, 0x20, 0x69, 0x20, 0xD8,
+	0x1A, 0xB8, 0x3B, 0xB8, 0x00, 0xBA, 0x00, 0x65, 0x33, 0x21, 0x00, 0x65, 0x1D, 0x67, 0x00, 0xF0,
+	0x20, 0x69, 0x34, 0x49, 0x23, 0xE0, 0xB8, 0x65, 0x30, 0xF0, 0x20, 0x69, 0x4F, 0xF3, 0x10, 0x49,
+	0x20, 0x99, 0x09, 0xD9, 0x2A, 0x99, 0x22, 0xE8, 0x07, 0x60, 0x30, 0xF0, 0x20, 0x68, 0x2F, 0xF7,
+	0x0C, 0x48, 0x00, 0x98, 0x00, 0xE8, 0x00, 0x65, 0x30, 0xF0, 0x20, 0x68, 0x4F, 0xF3, 0x10, 0x48,
+	0x01, 0x98, 0x04, 0xD2, 0x05, 0xD3, 0x06, 0xD4, 0x07, 0xD5, 0x08, 0xD6, 0x09, 0xD7, 0x3A, 0xB8,
+	0x0A, 0xD1, 0x3B, 0xB8, 0x0B, 0xD1, 0x38, 0x67, 0x0C, 0xD1, 0x3F, 0x67, 0x0D, 0xD1, 0x12, 0xE9,
+	0x02, 0xD1, 0x10, 0xE9, 0x03, 0xD1, 0x2E, 0xB8, 0x02, 0x49, 0x01, 0xD1, 0x2C, 0xB8, 0x00, 0xD1,
+	0x30, 0xF0, 0x20, 0x69, 0x4F, 0xF3, 0x10, 0x49, 0x00, 0xD9, 0x29, 0x98, 0xB9, 0x65, 0x02, 0x91,
+	0x32, 0xE9, 0x03, 0x91, 0x30, 0xE9, 0x0D, 0x91, 0xF9, 0x65, 0x0C, 0x91, 0x19, 0x65, 0x0B, 0x91,
+	0x09, 0x97, 0x08, 0x96, 0x07, 0x95, 0x06, 0x94, 0x05, 0x93, 0x04, 0x92, 0x01, 0x90, 0xC8, 0xB9,
+	0x00, 0x65, 0x00, 0x65, 0x00, 0x65, 0x0A, 0x90, 0x20, 0xF0, 0x14, 0x63, 0x30, 0xF0, 0x20, 0x68,
+	0x2F, 0xF3, 0x14, 0x48, 0x00, 0xF0, 0x20, 0x69, 0x20, 0xD8, 0x00, 0xBA, 0x00, 0x65, 0x00, 0xF0,
+	0x20, 0x69, 0x03, 0x49, 0x2F, 0xE9, 0x2C, 0xE8, 0x30, 0xF0, 0x20, 0x69, 0x00, 0xF0, 0x00, 0x49,
+	0x21, 0xE0, 0x00, 0xA0, 0x30, 0xF0, 0x20, 0x69, 0x40, 0xF1, 0x08, 0x49, 0x21, 0xE0, 0x00, 0x98,
+	0xDF, 0xF7, 0x0C, 0x63, 0x3D, 0x67, 0x59, 0xB9, 0x00, 0x65, 0x00, 0x65, 0x00, 0x65, 0x04, 0xD2,
+	0x05, 0xD3, 0x06, 0xD4, 0x07, 0xD5, 0x08, 0xD6, 0x09, 0xD7, 0x3A, 0xB8, 0x0A, 0xD1, 0x3B, 0xB8,
+	0x0B, 0xD1, 0x38, 0x67, 0x0C, 0xD1, 0x3F, 0x67, 0x0D, 0xD1, 0x12, 0xE9, 0x02, 0xD1, 0x10, 0xE9,
+	0x03, 0xD1, 0x30, 0xF0, 0x20, 0x6C, 0x2E, 0xF3, 0x14, 0x4C, 0x00, 0xF4, 0x00, 0x4C, 0xBC, 0x65,
+	0x90, 0x67, 0x40, 0xE8, 0x00, 0x65, 0x1A, 0xB8, 0xB8, 0x65, 0x02, 0x91, 0x32, 0xE9, 0x03, 0x91,
+	0x30, 0xE9, 0x0D, 0x91, 0xF9, 0x65, 0x0C, 0x91, 0x19, 0x65, 0x0B, 0x91, 0x09, 0x97, 0x08, 0x96,
+	0x07, 0x95, 0x06, 0x94, 0x05, 0x93, 0x04, 0x92, 0x20, 0xF0, 0x14, 0x63, 0x00, 0xBA, 0x00, 0x65,
+	0x00, 0xF0, 0x20, 0x69, 0x01, 0x49, 0x2F, 0xE9, 0x2C, 0xE8, 0x30, 0xF0, 0x20, 0x69, 0x00, 0xF0,
+	0x00, 0x49, 0x21, 0xE0, 0x00, 0xA0, 0x30, 0xF0, 0x20, 0x69, 0x40, 0xF1, 0x08, 0x49, 0x21, 0xE0,
+	0x30, 0xF0, 0x20, 0x69, 0x2F, 0xF3, 0x14, 0x49, 0x00, 0xD9, 0xDF, 0xF7, 0x0C, 0x63, 0x30, 0xF0,
+	0x20, 0x69, 0x4F, 0xF3, 0x10, 0x49, 0x20, 0x99, 0x1D, 0x67, 0x09, 0xD9, 0x2A, 0x99, 0x22, 0xE8,
+	0x07, 0x60, 0x30, 0xF0, 0x20, 0x68, 0x2F, 0xF7, 0x0C, 0x48, 0x00, 0x98, 0x00, 0xE8, 0x00, 0x65,
+	0x04, 0xD2, 0x05, 0xD3, 0x06, 0xD4, 0x07, 0xD5, 0x08, 0xD6, 0x09, 0xD7, 0x3A, 0xB8, 0x0A, 0xD1,
+	0x3B, 0xB8, 0x0B, 0xD1, 0x38, 0x67, 0x0C, 0xD1, 0x3F, 0x67, 0x0D, 0xD1, 0x12, 0xE9, 0x02, 0xD1,
+	0x10, 0xE9, 0x03, 0xD1, 0x30, 0xF0, 0x20, 0x69, 0x2F, 0xF3, 0x14, 0x49, 0x00, 0x99, 0x2E, 0xB8,
+	0x01, 0xD1, 0x2C, 0xB8, 0x00, 0xD1, 0x00, 0x98, 0x30, 0xF0, 0x20, 0x6C, 0x2E, 0xF3, 0x14, 0x4C,
+	0x00, 0xF4, 0x00, 0x4C, 0xBC, 0x65, 0x90, 0x67, 0x40, 0xE8, 0x00, 0x65, 0x30, 0xF0, 0x20, 0x68,
+	0x4F, 0xF3, 0x10, 0x48, 0x30, 0xF0, 0x20, 0x69, 0x2F, 0xF7, 0x00, 0x49, 0x20, 0x99, 0x00, 0xE9,
+	0x00, 0x65, 0x21, 0x98, 0x20, 0xD8, 0x09, 0x99, 0xB8, 0x65, 0x02, 0x91, 0x32, 0xE9, 0x03, 0x91,
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+	0x07, 0x95, 0x06, 0x94, 0x05, 0x93, 0x04, 0x92, 0x01, 0x90, 0xC8, 0xB9, 0x00, 0x65, 0x00, 0x65,
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+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0xD9, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+};
+u32 array_length_mp_8821c_fw_wowlan = 101880;
+
+#endif
+
+void
+odm_read_firmware_mp_8821c_fw_wowlan(
+	struct PHY_DM_STRUCT    *p_dm_odm,
+	u8       *p_firmware,
+	u32       *p_firmware_size
+)
+{
+#if (DM_ODM_SUPPORT_TYPE & (ODM_CE))
+	*((SIZE_PTR *)p_firmware) = (SIZE_PTR)array_mp_8821c_fw_wowlan;
+#else
+	odm_move_memory(p_dm_odm, p_firmware, array_mp_8821c_fw_wowlan, array_length_mp_8821c_fw_wowlan);
+#endif
+	*p_firmware_size = array_length_mp_8821c_fw_wowlan;
+}
+
+
+
+#endif /* end of (defined(CONFIG_AP_WOWLAN) || (DM_ODM_SUPPORT_TYPE & (ODM_AP)))*/
+
+#endif /* end of HWIMG_SUPPORT*/
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/rtl8821c/halhwimg8821c_fw.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/rtl8821c/halhwimg8821c_fw.h
--- linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/rtl8821c/halhwimg8821c_fw.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/rtl8821c/halhwimg8821c_fw.h	2020-04-10 16:35:06.833660861 +0300
@@ -0,0 +1,61 @@
+/******************************************************************************
+*
+* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
+*
+* This program is free software; you can redistribute it and/or modify it
+* under the terms of version 2 of the GNU General Public License as
+* published by the Free Software Foundation.
+*
+* This program is distributed in the hope that it will be useful, but WITHOUT
+* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+* more details.
+*
+* You should have received a copy of the GNU General Public License along with
+* this program; if not, write to the Free Software Foundation, Inc.,
+* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
+*
+*
+******************************************************************************/
+
+/*Image2HeaderVersion: 2.16*/
+#if (RTL8821C_SUPPORT == 1)
+#ifndef __INC_MP_FW_HW_IMG_8821C_H
+#define __INC_MP_FW_HW_IMG_8821C_H
+
+
+/******************************************************************************
+*                           FW_AP.TXT
+******************************************************************************/
+
+void
+odm_read_firmware_mp_8821c_fw_ap(
+	struct PHY_DM_STRUCT    *p_dm_odm,
+	u8       *p_firmware,
+	u32       *p_firmware_size
+);
+
+/******************************************************************************
+*                           FW_NIC.TXT
+******************************************************************************/
+
+void
+odm_read_firmware_mp_8821c_fw_nic(
+	struct PHY_DM_STRUCT    *p_dm_odm,
+	u8       *p_firmware,
+	u32       *p_firmware_size
+);
+
+/******************************************************************************
+*                           FW_WoWLAN.TXT
+******************************************************************************/
+
+void
+odm_read_firmware_mp_8821c_fw_wowlan(
+	struct PHY_DM_STRUCT    *p_dm_odm,
+	u8       *p_firmware,
+	u32       *p_firmware_size
+);
+
+#endif
+#endif /* end of HWIMG_SUPPORT*/
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/rtl8821c/halhwimg8821c_mac.c linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/rtl8821c/halhwimg8821c_mac.c
--- linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/rtl8821c/halhwimg8821c_mac.c	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/rtl8821c/halhwimg8821c_mac.c	2020-04-10 16:35:06.833660861 +0300
@@ -0,0 +1,316 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * The full GNU General Public License is included in this distribution in the
+ * file called LICENSE.
+ *
+ * Contact Information:
+ * wlanfae <wlanfae@realtek.com>
+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
+ * Hsinchu 300, Taiwan.
+ *
+ * Larry Finger <Larry.Finger@lwfinger.net>
+ *
+ *****************************************************************************/
+
+/*Image2HeaderVersion: R3 1.0*/
+#include "mp_precomp.h"
+#include "../phydm_precomp.h"
+
+#if (RTL8821C_SUPPORT == 1)
+static boolean
+check_positive(
+	struct dm_struct *dm,
+	const u32	condition1,
+	const u32	condition2,
+	const u32	condition3,
+	const u32	condition4
+)
+{
+	u32	cond1 = condition1, cond2 = condition2, cond3 = condition3, cond4 = condition4;
+
+	u8	cut_version_for_para = (dm->cut_version ==  ODM_CUT_A) ? 15 : dm->cut_version;
+	u8	pkg_type_for_para = (dm->package_type == 0) ? 15 : dm->package_type;
+
+	u32	driver1 = cut_version_for_para << 24 |
+			(dm->support_interface & 0xF0) << 16 |
+			dm->support_platform << 16 |
+			pkg_type_for_para << 12 |
+			(dm->support_interface & 0x0F) << 8  |
+			dm->rfe_type;
+
+	u32	driver2 = (dm->type_glna & 0xFF) <<  0 |
+			(dm->type_gpa & 0xFF)  <<  8 |
+			(dm->type_alna & 0xFF) << 16 |
+			(dm->type_apa & 0xFF)  << 24;
+
+	u32	driver3 = 0;
+
+	u32	driver4 = (dm->type_glna & 0xFF00) >>  8 |
+			(dm->type_gpa & 0xFF00) |
+			(dm->type_alna & 0xFF00) << 8 |
+			(dm->type_apa & 0xFF00)  << 16;
+
+	PHYDM_DBG(dm, ODM_COMP_INIT,
+		  "===> %s (cond1, cond2, cond3, cond4) = (0x%X 0x%X 0x%X 0x%X)\n",
+		  __func__, cond1, cond2, cond3, cond4);
+	PHYDM_DBG(dm, ODM_COMP_INIT,
+		  "===> %s (driver1, driver2, driver3, driver4) = (0x%X 0x%X 0x%X 0x%X)\n",
+		  __func__, driver1, driver2, driver3, driver4);
+
+	PHYDM_DBG(dm, ODM_COMP_INIT,
+		  "	(Platform, Interface) = (0x%X, 0x%X)\n",
+		  dm->support_platform, dm->support_interface);
+	PHYDM_DBG(dm, ODM_COMP_INIT, "	(RFE, Package) = (0x%X, 0x%X)\n",
+		  dm->rfe_type, dm->package_type);
+
+
+	/*============== value Defined Check ===============*/
+	/*cut version [27:24] need to do value check*/
+	if (((cond1 & 0x0F000000) != 0) && ((cond1 & 0x0F000000) != (driver1 & 0x0F000000)))
+		return false;
+
+	/*pkg type [15:12] need to do value check*/
+	if (((cond1 & 0x0000F000) != 0) && ((cond1 & 0x0000F000) != (driver1 & 0x0000F000)))
+		return false;
+
+	/*interface [11:8] need to do value check*/
+	if (((cond1 & 0x00000F00) != 0) && ((cond1 & 0x00000F00) != (driver1 & 0x00000F00)))
+		return false;
+	/*=============== Bit Defined Check ================*/
+	/* We don't care [31:28] */
+
+	cond1 &= 0x000000FF;
+	driver1 &= 0x000000FF;
+
+	if (cond1 == driver1)
+		return true;
+	else
+		return false;
+}
+static boolean
+check_negative(
+	struct dm_struct *dm,
+	const u32	condition1,
+	const u32	condition2
+)
+{
+	return true;
+}
+
+/******************************************************************************
+*                           mac_reg.TXT
+******************************************************************************/
+
+u32 array_mp_8821c_mac_reg[] = {
+		0x010, 0x00000043,
+		0x025, 0x0000001D,
+		0x026, 0x000000CE,
+		0x04F, 0x00000001,
+		0x029, 0x000000F9,
+		0x420, 0x00000080,
+		0x421, 0x0000000F,
+		0x428, 0x0000000A,
+		0x429, 0x00000010,
+		0x430, 0x00000000,
+		0x431, 0x00000000,
+		0x432, 0x00000000,
+		0x433, 0x00000001,
+		0x434, 0x00000004,
+		0x435, 0x00000005,
+		0x436, 0x00000007,
+		0x437, 0x00000008,
+		0x43C, 0x00000004,
+		0x43D, 0x00000005,
+		0x43E, 0x00000007,
+		0x43F, 0x00000008,
+		0x440, 0x0000005D,
+		0x441, 0x00000001,
+		0x442, 0x00000000,
+		0x444, 0x00000010,
+		0x445, 0x000000F0,
+		0x446, 0x00000001,
+		0x447, 0x000000FE,
+		0x448, 0x00000000,
+		0x449, 0x00000000,
+		0x44A, 0x00000000,
+		0x44B, 0x00000040,
+		0x44C, 0x00000010,
+		0x44D, 0x000000F0,
+		0x44E, 0x0000003F,
+		0x44F, 0x00000000,
+		0x450, 0x00000000,
+		0x451, 0x00000000,
+		0x452, 0x00000000,
+		0x453, 0x00000040,
+		0x455, 0x00000070,
+		0x45E, 0x00000004,
+		0x49C, 0x00000010,
+		0x49D, 0x000000F0,
+		0x49E, 0x00000000,
+		0x49F, 0x00000006,
+		0x4A0, 0x000000E0,
+		0x4A1, 0x00000003,
+		0x4A2, 0x00000000,
+		0x4A3, 0x00000040,
+		0x4A4, 0x00000015,
+		0x4A5, 0x000000F0,
+		0x4A6, 0x00000000,
+		0x4A7, 0x00000006,
+		0x4A8, 0x000000E0,
+		0x4A9, 0x00000000,
+		0x4AA, 0x00000000,
+		0x4AB, 0x00000000,
+		0x7DA, 0x00000008,
+		0x1448, 0x00000006,
+		0x144A, 0x00000006,
+		0x144C, 0x00000006,
+		0x144E, 0x00000006,
+		0x4C8, 0x000000FF,
+		0x4C9, 0x00000008,
+		0x4CC, 0x000000FF,
+		0x4CD, 0x000000FF,
+		0x4CE, 0x00000001,
+		0x4CF, 0x00000008,
+		0x500, 0x00000026,
+		0x501, 0x000000A2,
+		0x502, 0x0000002F,
+		0x503, 0x00000000,
+		0x504, 0x00000028,
+		0x505, 0x000000A3,
+		0x506, 0x0000005E,
+		0x507, 0x00000000,
+		0x508, 0x0000002B,
+		0x509, 0x000000A4,
+		0x50A, 0x0000005E,
+		0x50B, 0x00000000,
+		0x50C, 0x0000004F,
+		0x50D, 0x000000A4,
+		0x50E, 0x00000000,
+		0x50F, 0x00000000,
+		0x512, 0x0000001C,
+		0x514, 0x0000000A,
+		0x516, 0x0000000A,
+		0x521, 0x0000002F,
+		0x525, 0x0000004F,
+		0x551, 0x00000010,
+		0x559, 0x00000002,
+		0x55C, 0x00000050,
+		0x55D, 0x000000FF,
+		0x577, 0x0000000B,
+		0x578, 0x00000014,
+		0x579, 0x00000014,
+		0x57A, 0x00000014,
+		0x5BE, 0x00000064,
+		0x605, 0x00000030,
+		0x608, 0x0000000E,
+		0x609, 0x00000022,
+		0x60C, 0x00000018,
+		0x6A0, 0x000000FF,
+		0x6A1, 0x000000FF,
+		0x6A2, 0x000000FF,
+		0x6A3, 0x000000FF,
+		0x6A4, 0x000000FF,
+		0x6A5, 0x000000FF,
+		0x6DE, 0x00000084,
+		0x620, 0x000000FF,
+		0x621, 0x000000FF,
+		0x622, 0x000000FF,
+		0x623, 0x000000FF,
+		0x624, 0x000000FF,
+		0x625, 0x000000FF,
+		0x626, 0x000000FF,
+		0x627, 0x000000FF,
+		0x638, 0x00000050,
+		0x63C, 0x0000000A,
+		0x63D, 0x0000000A,
+		0x63E, 0x0000000E,
+		0x63F, 0x0000000E,
+		0x640, 0x00000040,
+		0x642, 0x00000040,
+		0x643, 0x00000000,
+		0x652, 0x000000C8,
+		0x66E, 0x00000005,
+		0x700, 0x00000021,
+		0x701, 0x00000043,
+		0x702, 0x00000065,
+		0x703, 0x00000087,
+		0x708, 0x00000021,
+		0x709, 0x00000043,
+		0x70A, 0x00000065,
+		0x70B, 0x00000087,
+		0x718, 0x00000040,
+		0x7D4, 0x00000098,
+
+};
+
+void
+odm_read_and_config_mp_8821c_mac_reg(struct dm_struct *dm)
+{
+	u32	i = 0;
+	u8	c_cond;
+	boolean	is_matched = true, is_skipped = false;
+	u32	array_len = sizeof(array_mp_8821c_mac_reg) / sizeof(u32);
+	u32	*array = array_mp_8821c_mac_reg;
+
+	u32	v1 = 0, v2 = 0, pre_v1 = 0, pre_v2 = 0;
+
+	PHYDM_DBG(dm, ODM_COMP_INIT, "===> %s\n", __func__);
+
+	while ((i + 1) < array_len) {
+		v1 = array[i];
+		v2 = array[i + 1];
+
+		if (v1 & (BIT(31) | BIT(30))) {/*positive & negative condition*/
+			if (v1 & BIT(31)) {/* positive condition*/
+				c_cond  = (u8)((v1 & (BIT(29) | BIT(28))) >> 28);
+				if (c_cond == COND_ENDIF) {/*end*/
+					is_matched = true;
+					is_skipped = false;
+					PHYDM_DBG(dm, ODM_COMP_INIT, "ENDIF\n");
+				} else if (c_cond == COND_ELSE) { /*else*/
+					is_matched = is_skipped ? false : true;
+					PHYDM_DBG(dm, ODM_COMP_INIT, "ELSE\n");
+				} else {/*if , else if*/
+					pre_v1 = v1;
+					pre_v2 = v2;
+					PHYDM_DBG(dm, ODM_COMP_INIT, "IF or ELSE IF\n");
+				}
+			} else if (v1 & BIT(30)) { /*negative condition*/
+				if (is_skipped == false) {
+					if (check_positive(dm, pre_v1, pre_v2, v1, v2)) {
+						is_matched = true;
+						is_skipped = true;
+					} else {
+						is_matched = false;
+						is_skipped = false;
+					}
+				} else
+					is_matched = false;
+			}
+		} else {
+			if (is_matched)
+				odm_config_mac_8821c(dm, v1, (u8)v2);
+		}
+		i = i + 2;
+	}
+}
+
+u32
+odm_get_version_mp_8821c_mac_reg(void)
+{
+		return 49;
+}
+
+#endif /* end of HWIMG_SUPPORT*/
+
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/rtl8821c/halhwimg8821c_mac.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/rtl8821c/halhwimg8821c_mac.h
--- linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/rtl8821c/halhwimg8821c_mac.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/rtl8821c/halhwimg8821c_mac.h	2020-04-10 16:35:06.833660861 +0300
@@ -0,0 +1,43 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * The full GNU General Public License is included in this distribution in the
+ * file called LICENSE.
+ *
+ * Contact Information:
+ * wlanfae <wlanfae@realtek.com>
+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
+ * Hsinchu 300, Taiwan.
+ *
+ * Larry Finger <Larry.Finger@lwfinger.net>
+ *
+ *****************************************************************************/
+
+/*Image2HeaderVersion: R3 1.0*/
+#if (RTL8821C_SUPPORT == 1)
+#ifndef __INC_MP_MAC_HW_IMG_8821C_H
+#define __INC_MP_MAC_HW_IMG_8821C_H
+
+
+/******************************************************************************
+*                           mac_reg.TXT
+******************************************************************************/
+
+void
+odm_read_and_config_mp_8821c_mac_reg( /* tc: Test Chip, mp: mp Chip*/
+				     struct dm_struct *dm);
+u32 odm_get_version_mp_8821c_mac_reg(void);
+
+#endif
+#endif /* end of HWIMG_SUPPORT*/
+
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/rtl8821c/halhwimg8821c_rf.c linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/rtl8821c/halhwimg8821c_rf.c
--- linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/rtl8821c/halhwimg8821c_rf.c	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/rtl8821c/halhwimg8821c_rf.c	2020-04-10 16:35:06.833660861 +0300
@@ -0,0 +1,4762 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * The full GNU General Public License is included in this distribution in the
+ * file called LICENSE.
+ *
+ * Contact Information:
+ * wlanfae <wlanfae@realtek.com>
+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
+ * Hsinchu 300, Taiwan.
+ *
+ * Larry Finger <Larry.Finger@lwfinger.net>
+ *
+ *****************************************************************************/
+
+/*Image2HeaderVersion: R3 1.0*/
+#include "mp_precomp.h"
+#include "../phydm_precomp.h"
+
+#if (RTL8821C_SUPPORT == 1)
+static boolean
+check_positive(
+	struct dm_struct *dm,
+	const u32	condition1,
+	const u32	condition2,
+	const u32	condition3,
+	const u32	condition4
+)
+{
+	u32	cond1 = condition1, cond2 = condition2, cond3 = condition3, cond4 = condition4;
+
+	u8	cut_version_for_para = (dm->cut_version ==  ODM_CUT_A) ? 15 : dm->cut_version;
+	u8	pkg_type_for_para = (dm->package_type == 0) ? 15 : dm->package_type;
+
+	u32	driver1 = cut_version_for_para << 24 |
+			(dm->support_interface & 0xF0) << 16 |
+			dm->support_platform << 16 |
+			pkg_type_for_para << 12 |
+			(dm->support_interface & 0x0F) << 8  |
+			dm->rfe_type;
+
+	u32	driver2 = (dm->type_glna & 0xFF) <<  0 |
+			(dm->type_gpa & 0xFF)  <<  8 |
+			(dm->type_alna & 0xFF) << 16 |
+			(dm->type_apa & 0xFF)  << 24;
+
+	u32	driver3 = 0;
+
+	u32	driver4 = (dm->type_glna & 0xFF00) >>  8 |
+			(dm->type_gpa & 0xFF00) |
+			(dm->type_alna & 0xFF00) << 8 |
+			(dm->type_apa & 0xFF00)  << 16;
+
+	PHYDM_DBG(dm, ODM_COMP_INIT,
+		  "===> %s (cond1, cond2, cond3, cond4) = (0x%X 0x%X 0x%X 0x%X)\n",
+		  __func__, cond1, cond2, cond3, cond4);
+	PHYDM_DBG(dm, ODM_COMP_INIT,
+		  "===> %s (driver1, driver2, driver3, driver4) = (0x%X 0x%X 0x%X 0x%X)\n",
+		  __func__, driver1, driver2, driver3, driver4);
+
+	PHYDM_DBG(dm, ODM_COMP_INIT,
+		  "	(Platform, Interface) = (0x%X, 0x%X)\n",
+		  dm->support_platform, dm->support_interface);
+	PHYDM_DBG(dm, ODM_COMP_INIT, "	(RFE, Package) = (0x%X, 0x%X)\n",
+		  dm->rfe_type, dm->package_type);
+
+
+	/*============== value Defined Check ===============*/
+	/*cut version [27:24] need to do value check*/
+	if (((cond1 & 0x0F000000) != 0) && ((cond1 & 0x0F000000) != (driver1 & 0x0F000000)))
+		return false;
+
+	/*pkg type [15:12] need to do value check*/
+	if (((cond1 & 0x0000F000) != 0) && ((cond1 & 0x0000F000) != (driver1 & 0x0000F000)))
+		return false;
+
+	/*interface [11:8] need to do value check*/
+	if (((cond1 & 0x00000F00) != 0) && ((cond1 & 0x00000F00) != (driver1 & 0x00000F00)))
+		return false;
+	/*=============== Bit Defined Check ================*/
+	/* We don't care [31:28] */
+
+	cond1 &= 0x000000FF;
+	driver1 &= 0x000000FF;
+
+	if (cond1 == driver1)
+		return true;
+	else
+		return false;
+}
+static boolean
+check_negative(
+	struct dm_struct *dm,
+	const u32	condition1,
+	const u32	condition2
+)
+{
+	return true;
+}
+
+/******************************************************************************
+*                           radioa.TXT
+******************************************************************************/
+
+u32 array_mp_8821c_radioa[] = {
+	0x80001005,	0x00000000,	0x40000000,	0x00000000,
+		0x000, 0x00010000,
+		0x018, 0x00010D24,
+	0x90001004,	0x00000000,	0x40000000,	0x00000000,
+		0x000, 0x00010000,
+		0x018, 0x00010D24,
+	0x90000400,	0x00000000,	0x40000000,	0x00000000,
+		0x000, 0x00010000,
+		0x018, 0x00010D24,
+	0xA0000000,	0x00000000,
+		0x000, 0x00010000,
+		0x018, 0x00010D24,
+	0xB0000000,	0x00000000,
+	0x80001005,	0x00000000,	0x40000000,	0x00000000,
+		0x0EF, 0x00080000,
+		0x033, 0x00000002,
+		0x03E, 0x0000003F,
+		0x03F, 0x000C0F4E,
+		0x033, 0x00000001,
+		0x03E, 0x00000034,
+		0x03F, 0x0004080E,
+	0x90001004,	0x00000000,	0x40000000,	0x00000000,
+		0x0EF, 0x00080000,
+		0x033, 0x00000002,
+		0x03E, 0x0000003F,
+		0x03F, 0x000C0F4E,
+		0x033, 0x00000001,
+		0x03E, 0x00000034,
+		0x03F, 0x0004080E,
+	0x90000400,	0x00000000,	0x40000000,	0x00000000,
+		0x0EF, 0x00080000,
+		0x033, 0x00000002,
+		0x03E, 0x0000003F,
+		0x03F, 0x000C0F4E,
+		0x033, 0x00000001,
+		0x03E, 0x00000034,
+		0x03F, 0x0004080E,
+	0xA0000000,	0x00000000,
+		0x0EF, 0x00080000,
+		0x033, 0x00000002,
+		0x03E, 0x0000003F,
+		0x03F, 0x000C0F4E,
+		0x033, 0x00000001,
+		0x03E, 0x00000034,
+		0x03F, 0x0004080E,
+	0xB0000000,	0x00000000,
+	0x80001005,	0x00000000,	0x40000000,	0x00000000,
+		0x0EF, 0x00002000,
+		0x033, 0x00000000,
+		0x03F, 0x000005DF,
+		0x0EF, 0x00000000,
+	0x90001004,	0x00000000,	0x40000000,	0x00000000,
+		0x0EF, 0x00002000,
+		0x033, 0x00000000,
+		0x03F, 0x000005DF,
+		0x0EF, 0x00000000,
+	0x90000400,	0x00000000,	0x40000000,	0x00000000,
+		0x0EF, 0x00002000,
+		0x033, 0x00000000,
+		0x03F, 0x000005DF,
+		0x0EF, 0x00000000,
+	0xA0000000,	0x00000000,
+		0x0EF, 0x00002000,
+		0x033, 0x00000000,
+		0x03F, 0x000005DF,
+		0x0EF, 0x00000000,
+	0xB0000000,	0x00000000,
+	0x80001005,	0x00000000,	0x40000000,	0x00000000,
+		0x0EE, 0x00000400,
+		0x033, 0x00000000,
+		0x03F, 0x000005DF,
+		0x0EE, 0x00000000,
+	0x90001004,	0x00000000,	0x40000000,	0x00000000,
+		0x0EE, 0x00000400,
+		0x033, 0x00000000,
+		0x03F, 0x000005DF,
+		0x0EE, 0x00000000,
+	0x90000400,	0x00000000,	0x40000000,	0x00000000,
+		0x0EE, 0x00000400,
+		0x033, 0x00000000,
+		0x03F, 0x000005DF,
+		0x0EE, 0x00000000,
+	0xA0000000,	0x00000000,
+		0x0EE, 0x00000400,
+		0x033, 0x00000000,
+		0x03F, 0x000005DF,
+		0x0EE, 0x00000000,
+	0xB0000000,	0x00000000,
+	0x80001005,	0x00000000,	0x40000000,	0x00000000,
+		0x0B0, 0x000FF0F8,
+		0x0B1, 0x0007DBE4,
+		0x0B2, 0x000225D1,
+		0x0B3, 0x000FC760,
+		0x0B4, 0x00099DD0,
+		0x0B5, 0x000400FC,
+		0x0B6, 0x000187F0,
+		0x0B7, 0x00030018,
+		0x0B8, 0x00080800,
+		0x0B9, 0x00000000,
+		0x0BA, 0x00008000,
+		0x0BB, 0x00000004,
+		0x0BC, 0x00040000,
+		0x0BD, 0x00000000,
+		0x0BE, 0x00000000,
+		0x0BF, 0x00000000,
+		0x0C0, 0x00000000,
+		0x0C1, 0x00000000,
+		0x0C2, 0x00000000,
+		0x0C3, 0x00000000,
+		0x0C4, 0x00002402,
+		0x0C5, 0x00000009,
+		0x0C6, 0x00040299,
+		0x0C7, 0x00055555,
+		0x0C8, 0x0000C16C,
+		0x0C9, 0x0001C140,
+		0x0CA, 0x00000000,
+		0x0CB, 0x00000000,
+		0x0CC, 0x00000000,
+		0x0CD, 0x00000000,
+		0x0CE, 0x00090C00,
+		0x0CF, 0x0006D200,
+		0x0DF, 0x00000009,
+	0x90001004,	0x00000000,	0x40000000,	0x00000000,
+		0x0B0, 0x000FF0F8,
+		0x0B1, 0x0007DBE4,
+		0x0B2, 0x000225D1,
+		0x0B3, 0x000FC760,
+		0x0B4, 0x00099DD0,
+		0x0B5, 0x000400FC,
+		0x0B6, 0x000187F0,
+		0x0B7, 0x00030018,
+		0x0B8, 0x00080800,
+		0x0B9, 0x00000000,
+		0x0BA, 0x00008000,
+		0x0BB, 0x00000004,
+		0x0BC, 0x00040000,
+		0x0BD, 0x00000000,
+		0x0BE, 0x00000000,
+		0x0BF, 0x00000000,
+		0x0C0, 0x00000000,
+		0x0C1, 0x00000000,
+		0x0C2, 0x00000000,
+		0x0C3, 0x00000000,
+		0x0C4, 0x00002402,
+		0x0C5, 0x00000009,
+		0x0C6, 0x00040299,
+		0x0C7, 0x00055555,
+		0x0C8, 0x0000C16C,
+		0x0C9, 0x0001C140,
+		0x0CA, 0x00000000,
+		0x0CB, 0x00000000,
+		0x0CC, 0x00000000,
+		0x0CD, 0x00000000,
+		0x0CE, 0x00090C00,
+		0x0CF, 0x0006D200,
+		0x0DF, 0x00000009,
+	0x90000400,	0x00000000,	0x40000000,	0x00000000,
+		0x0B0, 0x000FF0F8,
+		0x0B1, 0x0007DBE4,
+		0x0B2, 0x000225D1,
+		0x0B3, 0x000FC760,
+		0x0B4, 0x00099DD0,
+		0x0B5, 0x000400FC,
+		0x0B6, 0x000187F0,
+		0x0B7, 0x00030018,
+		0x0B8, 0x00080800,
+		0x0B9, 0x00000000,
+		0x0BA, 0x00008000,
+		0x0BB, 0x00000004,
+		0x0BC, 0x00040000,
+		0x0BD, 0x00000000,
+		0x0BE, 0x00000000,
+		0x0BF, 0x00000000,
+		0x0C0, 0x00000000,
+		0x0C1, 0x00000000,
+		0x0C2, 0x00000000,
+		0x0C3, 0x00000000,
+		0x0C4, 0x00002402,
+		0x0C5, 0x00000009,
+		0x0C6, 0x00040299,
+		0x0C7, 0x00055555,
+		0x0C8, 0x0000C16C,
+		0x0C9, 0x0001C140,
+		0x0CA, 0x00000000,
+		0x0CB, 0x00000000,
+		0x0CC, 0x00000000,
+		0x0CD, 0x00000000,
+		0x0CE, 0x00090C00,
+		0x0CF, 0x0006D200,
+		0x0DF, 0x00000009,
+	0xA0000000,	0x00000000,
+		0x0B0, 0x000FF0F8,
+		0x0B1, 0x0007DBE4,
+		0x0B2, 0x000225D1,
+		0x0B3, 0x000FC760,
+		0x0B4, 0x00099DD0,
+		0x0B5, 0x000400FC,
+		0x0B6, 0x000187F0,
+		0x0B7, 0x00030018,
+		0x0B8, 0x00080800,
+		0x0B9, 0x00000000,
+		0x0BA, 0x00008000,
+		0x0BB, 0x00000004,
+		0x0BC, 0x00040000,
+		0x0BD, 0x00000000,
+		0x0BE, 0x00000000,
+		0x0BF, 0x00000000,
+		0x0C0, 0x00000000,
+		0x0C1, 0x00000000,
+		0x0C2, 0x00000000,
+		0x0C3, 0x00000000,
+		0x0C4, 0x00002402,
+		0x0C5, 0x00000009,
+		0x0C6, 0x00040299,
+		0x0C7, 0x00055555,
+		0x0C8, 0x0000C16C,
+		0x0C9, 0x0001C140,
+		0x0CA, 0x00000000,
+		0x0CB, 0x00000000,
+		0x0CC, 0x00000000,
+		0x0CD, 0x00000000,
+		0x0CE, 0x00090C00,
+		0x0CF, 0x0006D200,
+		0x0DF, 0x00000009,
+	0xB0000000,	0x00000000,
+	0x80001005,	0x00000000,	0x40000000,	0x00000000,
+		0x0EE, 0x00010000,
+		0x033, 0x00000058,
+		0x03F, 0x0000001C,
+		0x0EE, 0x00000000,
+	0x90001004,	0x00000000,	0x40000000,	0x00000000,
+		0x0EE, 0x00010000,
+		0x033, 0x00000058,
+		0x03F, 0x0000001C,
+		0x0EE, 0x00000000,
+	0x90000400,	0x00000000,	0x40000000,	0x00000000,
+		0x0EE, 0x00010000,
+		0x033, 0x00000058,
+		0x03F, 0x0000001C,
+		0x0EE, 0x00000000,
+	0xA0000000,	0x00000000,
+		0x0EE, 0x00010000,
+		0x033, 0x00000058,
+		0x03F, 0x0000001C,
+		0x0EE, 0x00000000,
+	0xB0000000,	0x00000000,
+	0x80001005,	0x00000000,	0x40000000,	0x00000000,
+		0x018, 0x00010524,
+		0x081, 0x0000FCC1,
+		0x089, 0x00000004,
+		0x08A, 0x0008A186,
+		0x08B, 0x0006FFFC,
+		0x08C, 0x000312C7,
+		0x08D, 0x00020888,
+		0x08E, 0x00064140,
+		0x08F, 0x000A8010,
+	0x90001004,	0x00000000,	0x40000000,	0x00000000,
+		0x018, 0x00010524,
+		0x081, 0x0000FCC1,
+		0x089, 0x00000004,
+		0x08A, 0x0008A186,
+		0x08B, 0x0006FFFC,
+		0x08C, 0x000312C7,
+		0x08D, 0x00020888,
+		0x08E, 0x00064140,
+		0x08F, 0x000A8010,
+	0x90000400,	0x00000000,	0x40000000,	0x00000000,
+		0x018, 0x00010524,
+		0x081, 0x0000FCC1,
+		0x089, 0x00000004,
+		0x08A, 0x0008A186,
+		0x08B, 0x0007060C,
+		0x08C, 0x000312C7,
+		0x08D, 0x00020888,
+		0x08E, 0x00064140,
+		0x08F, 0x000A8010,
+	0xA0000000,	0x00000000,
+		0x018, 0x00010524,
+		0x081, 0x0000FCC1,
+		0x089, 0x00000004,
+		0x08A, 0x0008A186,
+		0x08B, 0x0007060C,
+		0x08C, 0x000312C7,
+		0x08D, 0x00020888,
+		0x08E, 0x00064140,
+		0x08F, 0x000A8010,
+	0xB0000000,	0x00000000,
+	0x80001005,	0x00000000,	0x40000000,	0x00000000,
+		0x0DD, 0x00000020,
+	0x90001004,	0x00000000,	0x40000000,	0x00000000,
+		0x0DD, 0x00000020,
+	0x90000400,	0x00000000,	0x40000000,	0x00000000,
+		0x0DD, 0x00000020,
+	0xA0000000,	0x00000000,
+		0x0DD, 0x00000020,
+	0xB0000000,	0x00000000,
+	0x80001005,	0x00000000,	0x40000000,	0x00000000,
+		0x0EF, 0x00020000,
+	0x90001004,	0x00000000,	0x40000000,	0x00000000,
+		0x0EF, 0x00020000,
+	0x90000400,	0x00000000,	0x40000000,	0x00000000,
+		0x0EF, 0x00020000,
+	0xA0000000,	0x00000000,
+		0x0EF, 0x00020000,
+	0xB0000000,	0x00000000,
+	0x80001005,	0x00000000,	0x40000000,	0x00000000,
+		0x033, 0x00000007,
+		0x03E, 0x00038000,
+		0x03F, 0x000C3186,
+		0x033, 0x00000006,
+		0x03E, 0x00038080,
+		0x03F, 0x000C3186,
+		0x033, 0x00000005,
+		0x03E, 0x000380C8,
+		0x03F, 0x000C3186,
+		0x033, 0x00000004,
+		0x03E, 0x00038190,
+		0x03F, 0x000C3186,
+		0x033, 0x00000003,
+		0x03E, 0x00038998,
+		0x03F, 0x000C3186,
+		0x033, 0x00000002,
+		0x03E, 0x00039840,
+		0x03F, 0x000C3186,
+		0x033, 0x00000001,
+		0x03E, 0x000398C4,
+		0x03F, 0x000C3186,
+		0x033, 0x00000000,
+		0x03E, 0x00039930,
+		0x03F, 0x000C3186,
+	0x90001004,	0x00000000,	0x40000000,	0x00000000,
+		0x033, 0x00000007,
+		0x03E, 0x00038000,
+		0x03F, 0x000C3186,
+		0x033, 0x00000006,
+		0x03E, 0x00038080,
+		0x03F, 0x000C3186,
+		0x033, 0x00000005,
+		0x03E, 0x000380C8,
+		0x03F, 0x000C3186,
+		0x033, 0x00000004,
+		0x03E, 0x00038190,
+		0x03F, 0x000C3186,
+		0x033, 0x00000003,
+		0x03E, 0x00038998,
+		0x03F, 0x000C3186,
+		0x033, 0x00000002,
+		0x03E, 0x00039840,
+		0x03F, 0x000C3186,
+		0x033, 0x00000001,
+		0x03E, 0x000398C4,
+		0x03F, 0x000C3186,
+		0x033, 0x00000000,
+		0x03E, 0x00039930,
+		0x03F, 0x000C3186,
+	0x90000400,	0x00000000,	0x40000000,	0x00000000,
+		0x033, 0x00000007,
+		0x03E, 0x00038000,
+		0x03F, 0x000C3186,
+		0x033, 0x00000006,
+		0x03E, 0x00038080,
+		0x03F, 0x000C3186,
+		0x033, 0x00000005,
+		0x03E, 0x000380C8,
+		0x03F, 0x000C3186,
+		0x033, 0x00000004,
+		0x03E, 0x00038190,
+		0x03F, 0x000C3186,
+		0x033, 0x00000003,
+		0x03E, 0x00038998,
+		0x03F, 0x000C3186,
+		0x033, 0x00000002,
+		0x03E, 0x00039840,
+		0x03F, 0x000C3186,
+		0x033, 0x00000001,
+		0x03E, 0x000398C4,
+		0x03F, 0x000C3186,
+		0x033, 0x00000000,
+		0x03E, 0x00039930,
+		0x03F, 0x000C3186,
+	0xA0000000,	0x00000000,
+		0x033, 0x00000007,
+		0x03E, 0x00038000,
+		0x03F, 0x000C3186,
+		0x033, 0x00000006,
+		0x03E, 0x00038080,
+		0x03F, 0x000C3186,
+		0x033, 0x00000005,
+		0x03E, 0x000380C8,
+		0x03F, 0x000C3186,
+		0x033, 0x00000004,
+		0x03E, 0x00038190,
+		0x03F, 0x000C3186,
+		0x033, 0x00000003,
+		0x03E, 0x00038998,
+		0x03F, 0x000C3186,
+		0x033, 0x00000002,
+		0x03E, 0x00039840,
+		0x03F, 0x000C3186,
+		0x033, 0x00000001,
+		0x03E, 0x000398C4,
+		0x03F, 0x000C3186,
+		0x033, 0x00000000,
+		0x03E, 0x00039930,
+		0x03F, 0x000C3186,
+	0xB0000000,	0x00000000,
+	0x80001005,	0x00000000,	0x40000000,	0x00000000,
+		0x033, 0x0000000F,
+		0x03E, 0x00038000,
+		0x03F, 0x000C3186,
+		0x033, 0x0000000E,
+		0x03E, 0x00038080,
+		0x03F, 0x000C3186,
+		0x033, 0x0000000D,
+		0x03E, 0x000380C8,
+		0x03F, 0x000C3186,
+		0x033, 0x0000000C,
+		0x03E, 0x00038190,
+		0x03F, 0x000C3186,
+		0x033, 0x0000000B,
+		0x03E, 0x00038998,
+		0x03F, 0x000C3186,
+		0x033, 0x0000000A,
+		0x03E, 0x00039840,
+		0x03F, 0x000C3186,
+		0x033, 0x00000009,
+		0x03E, 0x000398C4,
+		0x03F, 0x000C3186,
+		0x033, 0x00000008,
+		0x03E, 0x00039930,
+		0x03F, 0x000C3186,
+	0x90001004,	0x00000000,	0x40000000,	0x00000000,
+		0x033, 0x0000000F,
+		0x03E, 0x00038000,
+		0x03F, 0x000C3186,
+		0x033, 0x0000000E,
+		0x03E, 0x00038080,
+		0x03F, 0x000C3186,
+		0x033, 0x0000000D,
+		0x03E, 0x000380C8,
+		0x03F, 0x000C3186,
+		0x033, 0x0000000C,
+		0x03E, 0x00038190,
+		0x03F, 0x000C3186,
+		0x033, 0x0000000B,
+		0x03E, 0x00038998,
+		0x03F, 0x000C3186,
+		0x033, 0x0000000A,
+		0x03E, 0x00039840,
+		0x03F, 0x000C3186,
+		0x033, 0x00000009,
+		0x03E, 0x000398C4,
+		0x03F, 0x000C3186,
+		0x033, 0x00000008,
+		0x03E, 0x00039930,
+		0x03F, 0x000C3186,
+	0x90000400,	0x00000000,	0x40000000,	0x00000000,
+		0x033, 0x0000000F,
+		0x03E, 0x00038000,
+		0x03F, 0x000C3186,
+		0x033, 0x0000000E,
+		0x03E, 0x00038080,
+		0x03F, 0x000C3186,
+		0x033, 0x0000000D,
+		0x03E, 0x000380C8,
+		0x03F, 0x000C3186,
+		0x033, 0x0000000C,
+		0x03E, 0x00038190,
+		0x03F, 0x000C3186,
+		0x033, 0x0000000B,
+		0x03E, 0x00038998,
+		0x03F, 0x000C3186,
+		0x033, 0x0000000A,
+		0x03E, 0x00039840,
+		0x03F, 0x000C3186,
+		0x033, 0x00000009,
+		0x03E, 0x000398C4,
+		0x03F, 0x000C3186,
+		0x033, 0x00000008,
+		0x03E, 0x00039930,
+		0x03F, 0x000C3186,
+	0xA0000000,	0x00000000,
+		0x033, 0x0000000F,
+		0x03E, 0x00038000,
+		0x03F, 0x000C3186,
+		0x033, 0x0000000E,
+		0x03E, 0x00038080,
+		0x03F, 0x000C3186,
+		0x033, 0x0000000D,
+		0x03E, 0x000380C8,
+		0x03F, 0x000C3186,
+		0x033, 0x0000000C,
+		0x03E, 0x00038190,
+		0x03F, 0x000C3186,
+		0x033, 0x0000000B,
+		0x03E, 0x00038998,
+		0x03F, 0x000C3186,
+		0x033, 0x0000000A,
+		0x03E, 0x00039840,
+		0x03F, 0x000C3186,
+		0x033, 0x00000009,
+		0x03E, 0x000398C4,
+		0x03F, 0x000C3186,
+		0x033, 0x00000008,
+		0x03E, 0x00039930,
+		0x03F, 0x000C3186,
+	0xB0000000,	0x00000000,
+	0x80001005,	0x00000000,	0x40000000,	0x00000000,
+		0x033, 0x00000017,
+		0x03E, 0x00038000,
+		0x03F, 0x000C3186,
+		0x033, 0x00000016,
+		0x03E, 0x00038080,
+		0x03F, 0x000C3186,
+		0x033, 0x00000015,
+		0x03E, 0x000380C8,
+		0x03F, 0x000C3186,
+		0x033, 0x00000014,
+		0x03E, 0x00038190,
+		0x03F, 0x000C3186,
+		0x033, 0x00000013,
+		0x03E, 0x00038998,
+		0x03F, 0x000C3186,
+		0x033, 0x00000012,
+		0x03E, 0x00039840,
+		0x03F, 0x000C3186,
+		0x033, 0x00000011,
+		0x03E, 0x000398C4,
+		0x03F, 0x000C3186,
+		0x033, 0x00000010,
+		0x03E, 0x00039930,
+		0x03F, 0x000C3186,
+		0x0EF, 0x00000000,
+	0x90001004,	0x00000000,	0x40000000,	0x00000000,
+		0x033, 0x00000017,
+		0x03E, 0x00038000,
+		0x03F, 0x000C3186,
+		0x033, 0x00000016,
+		0x03E, 0x00038080,
+		0x03F, 0x000C3186,
+		0x033, 0x00000015,
+		0x03E, 0x000380C8,
+		0x03F, 0x000C3186,
+		0x033, 0x00000014,
+		0x03E, 0x00038190,
+		0x03F, 0x000C3186,
+		0x033, 0x00000013,
+		0x03E, 0x00038998,
+		0x03F, 0x000C3186,
+		0x033, 0x00000012,
+		0x03E, 0x00039840,
+		0x03F, 0x000C3186,
+		0x033, 0x00000011,
+		0x03E, 0x000398C4,
+		0x03F, 0x000C3186,
+		0x033, 0x00000010,
+		0x03E, 0x00039930,
+		0x03F, 0x000C3186,
+		0x0EF, 0x00000000,
+	0x90000400,	0x00000000,	0x40000000,	0x00000000,
+		0x033, 0x00000017,
+		0x03E, 0x00038000,
+		0x03F, 0x000C3186,
+		0x033, 0x00000016,
+		0x03E, 0x00038080,
+		0x03F, 0x000C3186,
+		0x033, 0x00000015,
+		0x03E, 0x000380C8,
+		0x03F, 0x000C3186,
+		0x033, 0x00000014,
+		0x03E, 0x00038190,
+		0x03F, 0x000C3186,
+		0x033, 0x00000013,
+		0x03E, 0x00038998,
+		0x03F, 0x000C3186,
+		0x033, 0x00000012,
+		0x03E, 0x00039840,
+		0x03F, 0x000C3186,
+		0x033, 0x00000011,
+		0x03E, 0x000398C4,
+		0x03F, 0x000C3186,
+		0x033, 0x00000010,
+		0x03E, 0x00039930,
+		0x03F, 0x000C3186,
+		0x0EF, 0x00000000,
+	0xA0000000,	0x00000000,
+		0x033, 0x00000017,
+		0x03E, 0x00038000,
+		0x03F, 0x000C3186,
+		0x033, 0x00000016,
+		0x03E, 0x00038080,
+		0x03F, 0x000C3186,
+		0x033, 0x00000015,
+		0x03E, 0x000380C8,
+		0x03F, 0x000C3186,
+		0x033, 0x00000014,
+		0x03E, 0x00038190,
+		0x03F, 0x000C3186,
+		0x033, 0x00000013,
+		0x03E, 0x00038998,
+		0x03F, 0x000C3186,
+		0x033, 0x00000012,
+		0x03E, 0x00039840,
+		0x03F, 0x000C3186,
+		0x033, 0x00000011,
+		0x03E, 0x000398C4,
+		0x03F, 0x000C3186,
+		0x033, 0x00000010,
+		0x03E, 0x00039930,
+		0x03F, 0x000C3186,
+		0x0EF, 0x00000000,
+	0xB0000000,	0x00000000,
+	0x80001005,	0x00000000,	0x40000000,	0x00000000,
+		0x0EF, 0x00004000,
+		0x033, 0x00000000,
+		0x03F, 0x0000000F,
+		0x033, 0x00000001,
+		0x03F, 0x0000000A,
+		0x033, 0x00000002,
+		0x03F, 0x00000005,
+		0x0EF, 0x00000000,
+	0x90001004,	0x00000000,	0x40000000,	0x00000000,
+		0x0EF, 0x00004000,
+		0x033, 0x00000000,
+		0x03F, 0x0000000F,
+		0x033, 0x00000001,
+		0x03F, 0x0000000A,
+		0x033, 0x00000002,
+		0x03F, 0x00000005,
+		0x0EF, 0x00000000,
+	0x90000400,	0x00000000,	0x40000000,	0x00000000,
+		0x0EF, 0x00004000,
+		0x033, 0x00000000,
+		0x03F, 0x0000000F,
+		0x033, 0x00000001,
+		0x03F, 0x0000000A,
+		0x033, 0x00000002,
+		0x03F, 0x00000005,
+		0x0EF, 0x00000000,
+	0xA0000000,	0x00000000,
+		0x0EF, 0x00004000,
+		0x033, 0x00000000,
+		0x03F, 0x0000000F,
+		0x033, 0x00000001,
+		0x03F, 0x0000000A,
+		0x033, 0x00000002,
+		0x03F, 0x00000005,
+		0x0EF, 0x00000000,
+	0xB0000000,	0x00000000,
+	0x80001005,	0x00000000,	0x40000000,	0x00000000,
+		0x018, 0x00000401,
+		0x084, 0x00001209,
+		0x086, 0x000001A0,
+		0x087, 0x000E8180,
+		0x088, 0x00006020,
+		0x0DF, 0x00008009,
+	0x90001004,	0x00000000,	0x40000000,	0x00000000,
+		0x018, 0x00000401,
+		0x084, 0x00001209,
+		0x086, 0x000001A0,
+		0x087, 0x000E8180,
+		0x088, 0x00006020,
+		0x0DF, 0x00008009,
+	0x90000400,	0x00000000,	0x40000000,	0x00000000,
+		0x018, 0x00000401,
+		0x084, 0x00001209,
+		0x086, 0x000001A0,
+		0x087, 0x000E8180,
+		0x088, 0x00006020,
+		0x0DF, 0x00008009,
+	0xA0000000,	0x00000000,
+		0x018, 0x00000401,
+		0x084, 0x00001209,
+		0x086, 0x000001A0,
+		0x087, 0x000E8180,
+		0x088, 0x00006020,
+		0x0DF, 0x00008009,
+	0xB0000000,	0x00000000,
+	0x80001005,	0x00000000,	0x40000000,	0x00000000,
+		0x0EF, 0x00008000,
+		0x033, 0x0000000F,
+		0x03F, 0x0000003C,
+		0x033, 0x0000000E,
+		0x03F, 0x00000038,
+		0x033, 0x0000000D,
+		0x03F, 0x00000030,
+		0x033, 0x0000000C,
+		0x03F, 0x00000028,
+		0x033, 0x0000000B,
+		0x03F, 0x00000020,
+		0x033, 0x0000000A,
+		0x03F, 0x00000018,
+		0x033, 0x00000009,
+		0x03F, 0x00000010,
+		0x033, 0x00000008,
+		0x03F, 0x00000008,
+		0x033, 0x00000007,
+		0x03F, 0x0000003C,
+		0x033, 0x00000006,
+		0x03F, 0x00000038,
+		0x033, 0x00000005,
+		0x03F, 0x00000030,
+		0x033, 0x00000004,
+		0x03F, 0x00000028,
+		0x033, 0x00000003,
+		0x03F, 0x00000020,
+		0x033, 0x00000002,
+		0x03F, 0x00000018,
+		0x033, 0x00000001,
+		0x03F, 0x00000010,
+		0x033, 0x00000000,
+		0x03F, 0x00000008,
+		0x0EF, 0x00000000,
+	0x90001004,	0x00000000,	0x40000000,	0x00000000,
+		0x0EF, 0x00008000,
+		0x033, 0x0000000F,
+		0x03F, 0x0000003C,
+		0x033, 0x0000000E,
+		0x03F, 0x00000038,
+		0x033, 0x0000000D,
+		0x03F, 0x00000030,
+		0x033, 0x0000000C,
+		0x03F, 0x00000028,
+		0x033, 0x0000000B,
+		0x03F, 0x00000020,
+		0x033, 0x0000000A,
+		0x03F, 0x00000018,
+		0x033, 0x00000009,
+		0x03F, 0x00000010,
+		0x033, 0x00000008,
+		0x03F, 0x00000008,
+		0x033, 0x00000007,
+		0x03F, 0x0000003C,
+		0x033, 0x00000006,
+		0x03F, 0x00000038,
+		0x033, 0x00000005,
+		0x03F, 0x00000030,
+		0x033, 0x00000004,
+		0x03F, 0x00000028,
+		0x033, 0x00000003,
+		0x03F, 0x00000020,
+		0x033, 0x00000002,
+		0x03F, 0x00000018,
+		0x033, 0x00000001,
+		0x03F, 0x00000010,
+		0x033, 0x00000000,
+		0x03F, 0x00000008,
+		0x0EF, 0x00000000,
+	0x90000400,	0x00000000,	0x40000000,	0x00000000,
+		0x0EF, 0x00008000,
+		0x033, 0x0000000F,
+		0x03F, 0x0000003C,
+		0x033, 0x0000000E,
+		0x03F, 0x00000038,
+		0x033, 0x0000000D,
+		0x03F, 0x00000030,
+		0x033, 0x0000000C,
+		0x03F, 0x00000028,
+		0x033, 0x0000000B,
+		0x03F, 0x00000020,
+		0x033, 0x0000000A,
+		0x03F, 0x00000018,
+		0x033, 0x00000009,
+		0x03F, 0x00000010,
+		0x033, 0x00000008,
+		0x03F, 0x00000008,
+		0x033, 0x00000007,
+		0x03F, 0x0000003C,
+		0x033, 0x00000006,
+		0x03F, 0x00000038,
+		0x033, 0x00000005,
+		0x03F, 0x00000030,
+		0x033, 0x00000004,
+		0x03F, 0x00000028,
+		0x033, 0x00000003,
+		0x03F, 0x00000020,
+		0x033, 0x00000002,
+		0x03F, 0x00000018,
+		0x033, 0x00000001,
+		0x03F, 0x00000010,
+		0x033, 0x00000000,
+		0x03F, 0x00000008,
+		0x0EF, 0x00000000,
+	0xA0000000,	0x00000000,
+		0x0EF, 0x00008000,
+		0x033, 0x0000000F,
+		0x03F, 0x0000003C,
+		0x033, 0x0000000E,
+		0x03F, 0x00000038,
+		0x033, 0x0000000D,
+		0x03F, 0x00000030,
+		0x033, 0x0000000C,
+		0x03F, 0x00000028,
+		0x033, 0x0000000B,
+		0x03F, 0x00000020,
+		0x033, 0x0000000A,
+		0x03F, 0x00000018,
+		0x033, 0x00000009,
+		0x03F, 0x00000010,
+		0x033, 0x00000008,
+		0x03F, 0x00000008,
+		0x033, 0x00000007,
+		0x03F, 0x0000003C,
+		0x033, 0x00000006,
+		0x03F, 0x00000038,
+		0x033, 0x00000005,
+		0x03F, 0x00000030,
+		0x033, 0x00000004,
+		0x03F, 0x00000028,
+		0x033, 0x00000003,
+		0x03F, 0x00000020,
+		0x033, 0x00000002,
+		0x03F, 0x00000018,
+		0x033, 0x00000001,
+		0x03F, 0x00000010,
+		0x033, 0x00000000,
+		0x03F, 0x00000008,
+		0x0EF, 0x00000000,
+	0xB0000000,	0x00000000,
+	0x80001005,	0x00000000,	0x40000000,	0x00000000,
+		0x0EE, 0x00000002,
+		0x033, 0x0000001E,
+		0x03F, 0x00000000,
+		0x033, 0x0000001C,
+		0x03F, 0x00000000,
+		0x033, 0x0000000E,
+		0x03F, 0x00000000,
+		0x033, 0x0000000C,
+		0x03F, 0x00000000,
+		0x033, 0x0000000A,
+		0x03F, 0x00000002,
+		0x033, 0x00000008,
+		0x03F, 0x00000000,
+		0x033, 0x00000036,
+		0x03F, 0x00000000,
+		0x033, 0x00000037,
+		0x03F, 0x00000000,
+		0x033, 0x00000034,
+		0x03F, 0x00000000,
+		0x033, 0x00000026,
+		0x03F, 0x00000006,
+		0x033, 0x00000027,
+		0x03F, 0x00000006,
+		0x033, 0x00000024,
+		0x03F, 0x00000006,
+		0x033, 0x00000022,
+		0x03F, 0x00000006,
+		0x033, 0x00000020,
+		0x03F, 0x00000006,
+		0x033, 0x00000006,
+		0x03F, 0x00000000,
+		0x033, 0x00000007,
+		0x03F, 0x00000006,
+		0x033, 0x00000004,
+		0x03F, 0x00000006,
+		0x033, 0x00000002,
+		0x03F, 0x00000006,
+		0x033, 0x00000000,
+		0x03F, 0x00000006,
+		0x0EE, 0x00000000,
+	0x90001004,	0x00000000,	0x40000000,	0x00000000,
+		0x0EE, 0x00000002,
+		0x033, 0x0000001E,
+		0x03F, 0x00000000,
+		0x033, 0x0000001C,
+		0x03F, 0x00000000,
+		0x033, 0x0000000E,
+		0x03F, 0x00000000,
+		0x033, 0x0000000C,
+		0x03F, 0x00000000,
+		0x033, 0x0000000A,
+		0x03F, 0x00000002,
+		0x033, 0x00000008,
+		0x03F, 0x00000000,
+		0x033, 0x00000036,
+		0x03F, 0x00000000,
+		0x033, 0x00000037,
+		0x03F, 0x00000000,
+		0x033, 0x00000034,
+		0x03F, 0x00000000,
+		0x033, 0x00000026,
+		0x03F, 0x00000006,
+		0x033, 0x00000027,
+		0x03F, 0x00000006,
+		0x033, 0x00000024,
+		0x03F, 0x00000006,
+		0x033, 0x00000022,
+		0x03F, 0x00000006,
+		0x033, 0x00000020,
+		0x03F, 0x00000006,
+		0x033, 0x00000006,
+		0x03F, 0x00000000,
+		0x033, 0x00000007,
+		0x03F, 0x00000006,
+		0x033, 0x00000004,
+		0x03F, 0x00000006,
+		0x033, 0x00000002,
+		0x03F, 0x00000006,
+		0x033, 0x00000000,
+		0x03F, 0x00000006,
+		0x0EE, 0x00000000,
+	0x90000400,	0x00000000,	0x40000000,	0x00000000,
+		0x0EE, 0x00000002,
+		0x033, 0x0000001E,
+		0x03F, 0x00000000,
+		0x033, 0x0000001C,
+		0x03F, 0x00000000,
+		0x033, 0x0000000E,
+		0x03F, 0x00000000,
+		0x033, 0x0000000C,
+		0x03F, 0x00000000,
+		0x033, 0x0000000A,
+		0x03F, 0x00000002,
+		0x033, 0x00000008,
+		0x03F, 0x00000000,
+		0x033, 0x00000036,
+		0x03F, 0x00000000,
+		0x033, 0x00000037,
+		0x03F, 0x00000000,
+		0x033, 0x00000034,
+		0x03F, 0x00000000,
+		0x033, 0x00000026,
+		0x03F, 0x00000006,
+		0x033, 0x00000027,
+		0x03F, 0x00000006,
+		0x033, 0x00000024,
+		0x03F, 0x00000006,
+		0x033, 0x00000022,
+		0x03F, 0x00000006,
+		0x033, 0x00000020,
+		0x03F, 0x00000006,
+		0x033, 0x00000006,
+		0x03F, 0x00000000,
+		0x033, 0x00000007,
+		0x03F, 0x00000006,
+		0x033, 0x00000004,
+		0x03F, 0x00000006,
+		0x033, 0x00000002,
+		0x03F, 0x00000006,
+		0x033, 0x00000000,
+		0x03F, 0x00000006,
+		0x0EE, 0x00000000,
+	0xA0000000,	0x00000000,
+		0x0EE, 0x00000002,
+		0x033, 0x0000001E,
+		0x03F, 0x00000000,
+		0x033, 0x0000001C,
+		0x03F, 0x00000000,
+		0x033, 0x0000000E,
+		0x03F, 0x00000000,
+		0x033, 0x0000000C,
+		0x03F, 0x00000000,
+		0x033, 0x0000000A,
+		0x03F, 0x00000002,
+		0x033, 0x00000008,
+		0x03F, 0x00000000,
+		0x033, 0x00000036,
+		0x03F, 0x00000000,
+		0x033, 0x00000037,
+		0x03F, 0x00000000,
+		0x033, 0x00000034,
+		0x03F, 0x00000000,
+		0x033, 0x00000026,
+		0x03F, 0x00000006,
+		0x033, 0x00000027,
+		0x03F, 0x00000006,
+		0x033, 0x00000024,
+		0x03F, 0x00000006,
+		0x033, 0x00000022,
+		0x03F, 0x00000006,
+		0x033, 0x00000020,
+		0x03F, 0x00000006,
+		0x033, 0x00000006,
+		0x03F, 0x00000000,
+		0x033, 0x00000007,
+		0x03F, 0x00000006,
+		0x033, 0x00000004,
+		0x03F, 0x00000006,
+		0x033, 0x00000002,
+		0x03F, 0x00000006,
+		0x033, 0x00000000,
+		0x03F, 0x00000006,
+		0x0EE, 0x00000000,
+	0xB0000000,	0x00000000,
+	0x80001005,	0x00000000,	0x40000000,	0x00000000,
+		0x0A0, 0x000F0005,
+		0x0A1, 0x0006C000,
+		0x0A2, 0x0000161B,
+		0x0A3, 0x000B9CBD,
+		0x0AF, 0x00070000,
+	0x90001004,	0x00000000,	0x40000000,	0x00000000,
+		0x0A0, 0x000F0005,
+		0x0A1, 0x0006C000,
+		0x0A2, 0x0000161B,
+		0x0A3, 0x000B9CBD,
+		0x0AF, 0x00070000,
+	0x90000400,	0x00000000,	0x40000000,	0x00000000,
+		0x0A0, 0x000F0005,
+		0x0A1, 0x0006C000,
+		0x0A2, 0x0000161B,
+		0x0A3, 0x000B9CBD,
+		0x0AF, 0x00070000,
+	0xA0000000,	0x00000000,
+		0x0A0, 0x000F0005,
+		0x0A1, 0x0006C000,
+		0x0A2, 0x0000161B,
+		0x0A3, 0x000B9CBD,
+		0x0AF, 0x00070000,
+	0xB0000000,	0x00000000,
+	0x80001005,	0x00000000,	0x40000000,	0x00000000,
+		0x0DE, 0x00000200,
+		0x0EE, 0x00000100,
+		0x033, 0x00000007,
+		0x03F, 0x00000043,
+		0x033, 0x00000006,
+		0x03F, 0x0000007A,
+		0x033, 0x00000005,
+		0x03F, 0x00000041,
+		0x033, 0x00000004,
+		0x03F, 0x00000079,
+		0x033, 0x00000003,
+		0x03F, 0x00000043,
+		0x033, 0x00000002,
+		0x03F, 0x0000007A,
+		0x033, 0x00000001,
+		0x03F, 0x00000041,
+		0x033, 0x00000000,
+		0x03F, 0x00000079,
+		0x0EE, 0x00000000,
+	0x90001004,	0x00000000,	0x40000000,	0x00000000,
+		0x0DE, 0x00000200,
+		0x0EE, 0x00000100,
+		0x033, 0x00000007,
+		0x03F, 0x00000043,
+		0x033, 0x00000006,
+		0x03F, 0x0000007A,
+		0x033, 0x00000005,
+		0x03F, 0x00000041,
+		0x033, 0x00000004,
+		0x03F, 0x00000079,
+		0x033, 0x00000003,
+		0x03F, 0x00000043,
+		0x033, 0x00000002,
+		0x03F, 0x0000007A,
+		0x033, 0x00000001,
+		0x03F, 0x00000041,
+		0x033, 0x00000000,
+		0x03F, 0x00000079,
+		0x0EE, 0x00000000,
+	0x90000400,	0x00000000,	0x40000000,	0x00000000,
+		0x0DE, 0x00000200,
+		0x0EE, 0x00000100,
+		0x033, 0x00000007,
+		0x03F, 0x00000043,
+		0x033, 0x00000006,
+		0x03F, 0x0000007A,
+		0x033, 0x00000005,
+		0x03F, 0x00000041,
+		0x033, 0x00000004,
+		0x03F, 0x00000079,
+		0x033, 0x00000003,
+		0x03F, 0x00000043,
+		0x033, 0x00000002,
+		0x03F, 0x0000007A,
+		0x033, 0x00000001,
+		0x03F, 0x00000041,
+		0x033, 0x00000000,
+		0x03F, 0x00000079,
+		0x0EE, 0x00000000,
+	0xA0000000,	0x00000000,
+		0x0DE, 0x00000200,
+		0x0EE, 0x00000100,
+		0x033, 0x00000007,
+		0x03F, 0x00000043,
+		0x033, 0x00000006,
+		0x03F, 0x0000007A,
+		0x033, 0x00000005,
+		0x03F, 0x00000041,
+		0x033, 0x00000004,
+		0x03F, 0x00000079,
+		0x033, 0x00000003,
+		0x03F, 0x00000043,
+		0x033, 0x00000002,
+		0x03F, 0x0000007A,
+		0x033, 0x00000001,
+		0x03F, 0x00000041,
+		0x033, 0x00000000,
+		0x03F, 0x00000079,
+		0x0EE, 0x00000000,
+	0xB0000000,	0x00000000,
+	0x80001005,	0x00000000,	0x40000000,	0x00000000,
+		0x0B8, 0x00080A00,
+		0x0B0, 0x000FF0FA,
+	0x90001004,	0x00000000,	0x40000000,	0x00000000,
+		0x0B8, 0x00080A00,
+		0x0B0, 0x000FF0FA,
+	0x90000400,	0x00000000,	0x40000000,	0x00000000,
+		0x0B8, 0x00080A00,
+		0x0B0, 0x000FF0FA,
+	0xA0000000,	0x00000000,
+		0x0B8, 0x00080A00,
+		0x0B0, 0x000FF0FA,
+	0xB0000000,	0x00000000,
+		0xFFE, 0x00000000,
+	0x80001005,	0x00000000,	0x40000000,	0x00000000,
+		0x0CA, 0x00080000,
+		0x0C9, 0x0001C141,
+	0x90001004,	0x00000000,	0x40000000,	0x00000000,
+		0x0CA, 0x00080000,
+		0x0C9, 0x0001C141,
+	0x90000400,	0x00000000,	0x40000000,	0x00000000,
+		0x0CA, 0x00080000,
+		0x0C9, 0x0001C141,
+	0xA0000000,	0x00000000,
+		0x0CA, 0x00080000,
+		0x0C9, 0x0001C141,
+	0xB0000000,	0x00000000,
+		0xFFE, 0x00000000,
+	0x80001005,	0x00000000,	0x40000000,	0x00000000,
+		0x0B0, 0x000FF0F8,
+	0x90001004,	0x00000000,	0x40000000,	0x00000000,
+		0x0B0, 0x000FF0F8,
+	0x90000400,	0x00000000,	0x40000000,	0x00000000,
+		0x0B0, 0x000FF0F8,
+	0xA0000000,	0x00000000,
+		0x0B0, 0x000FF0F8,
+	0xB0000000,	0x00000000,
+	0x80001005,	0x00000000,	0x40000000,	0x00000000,
+		0x018, 0x00018D24,
+	0x90001004,	0x00000000,	0x40000000,	0x00000000,
+		0x018, 0x00018D24,
+	0x90000400,	0x00000000,	0x40000000,	0x00000000,
+		0x018, 0x00018D24,
+	0xA0000000,	0x00000000,
+		0x018, 0x00018D24,
+	0xB0000000,	0x00000000,
+		0xFFE, 0x00000000,
+		0xFFE, 0x00000000,
+		0xFFE, 0x00000000,
+		0xFFE, 0x00000000,
+		0xFFE, 0x00000000,
+		0xFFE, 0x00000000,
+	0x80001005,	0x00000000,	0x40000000,	0x00000000,
+		0x018, 0x00010D24,
+	0x90001004,	0x00000000,	0x40000000,	0x00000000,
+		0x018, 0x00010D24,
+	0x90000400,	0x00000000,	0x40000000,	0x00000000,
+		0x018, 0x00010D24,
+	0xA0000000,	0x00000000,
+		0x018, 0x00010D24,
+	0xB0000000,	0x00000000,
+	0x80001005,	0x00000000,	0x40000000,	0x00000000,
+		0x01B, 0x00003A40,
+	0x90001004,	0x00000000,	0x40000000,	0x00000000,
+		0x01B, 0x00003A40,
+	0x90000400,	0x00000000,	0x40000000,	0x00000000,
+		0x01B, 0x00003A40,
+	0xA0000000,	0x00000000,
+		0x01B, 0x00003A40,
+	0xB0000000,	0x00000000,
+	0x80001005,	0x00000000,	0x40000000,	0x00000000,
+		0x061, 0x0004D3A3,
+		0x062, 0x0000D303,
+		0x063, 0x00000002,
+	0x90001004,	0x00000000,	0x40000000,	0x00000000,
+		0x061, 0x0004D3A3,
+		0x062, 0x0000D303,
+		0x063, 0x00000002,
+	0x90000400,	0x00000000,	0x40000000,	0x00000000,
+		0x061, 0x0004D3A1,
+		0x062, 0x0000D3A3,
+		0x063, 0x00000002,
+	0xA0000000,	0x00000000,
+		0x061, 0x0004D3A1,
+		0x062, 0x0000D3A3,
+		0x063, 0x00000002,
+	0xB0000000,	0x00000000,
+	0x80001005,	0x00000000,	0x40000000,	0x00000000,
+		0x0EF, 0x00000200,
+		0x030, 0x00000000,
+		0x03F, 0x00033303,
+		0x030, 0x00001000,
+		0x03F, 0x00033303,
+		0x030, 0x00002000,
+		0x03F, 0x00033303,
+		0x030, 0x00003000,
+		0x03F, 0x00033303,
+		0x030, 0x00004000,
+		0x03F, 0x00033303,
+		0x030, 0x00005000,
+		0x03F, 0x00033303,
+		0x030, 0x00006000,
+		0x03F, 0x00033303,
+		0x030, 0x00007000,
+		0x03F, 0x00033303,
+		0x030, 0x00008000,
+		0x03F, 0x00033303,
+		0x030, 0x00009000,
+		0x03F, 0x00033303,
+		0x030, 0x0000A000,
+		0x03F, 0x00033303,
+		0x030, 0x0000B000,
+		0x03F, 0x00033303,
+		0x0EF, 0x00000000,
+	0x90001004,	0x00000000,	0x40000000,	0x00000000,
+		0x0EF, 0x00000200,
+		0x030, 0x00000000,
+		0x03F, 0x00033303,
+		0x030, 0x00001000,
+		0x03F, 0x00033303,
+		0x030, 0x00002000,
+		0x03F, 0x00033303,
+		0x030, 0x00003000,
+		0x03F, 0x00033303,
+		0x030, 0x00004000,
+		0x03F, 0x000313A3,
+		0x030, 0x00005000,
+		0x03F, 0x000313A3,
+		0x030, 0x00006000,
+		0x03F, 0x000313A3,
+		0x030, 0x00007000,
+		0x03F, 0x000313A3,
+		0x030, 0x00008000,
+		0x03F, 0x000333A3,
+		0x030, 0x00009000,
+		0x03F, 0x000333A3,
+		0x030, 0x0000A000,
+		0x03F, 0x000333A3,
+		0x030, 0x0000B000,
+		0x03F, 0x000333A3,
+		0x0EF, 0x00000000,
+	0x90000400,	0x00000000,	0x40000000,	0x00000000,
+		0x0EF, 0x00000200,
+		0x030, 0x00000000,
+		0x03F, 0x000335A3,
+		0x030, 0x00001000,
+		0x03F, 0x000335A3,
+		0x030, 0x00002000,
+		0x03F, 0x000335A3,
+		0x030, 0x00003000,
+		0x03F, 0x000335A3,
+		0x030, 0x00004000,
+		0x03F, 0x000335A3,
+		0x030, 0x00005000,
+		0x03F, 0x000335A3,
+		0x030, 0x00006000,
+		0x03F, 0x000335A3,
+		0x030, 0x00007000,
+		0x03F, 0x000335A3,
+		0x030, 0x00008000,
+		0x03F, 0x000335A3,
+		0x030, 0x00009000,
+		0x03F, 0x000335A3,
+		0x030, 0x0000A000,
+		0x03F, 0x000335A3,
+		0x030, 0x0000B000,
+		0x03F, 0x000335A3,
+		0x0EF, 0x00000000,
+	0xA0000000,	0x00000000,
+		0x0EF, 0x00000200,
+		0x030, 0x00000000,
+		0x03F, 0x000335A3,
+		0x030, 0x00001000,
+		0x03F, 0x000335A3,
+		0x030, 0x00002000,
+		0x03F, 0x000335A3,
+		0x030, 0x00003000,
+		0x03F, 0x000335A3,
+		0x030, 0x00004000,
+		0x03F, 0x000335A3,
+		0x030, 0x00005000,
+		0x03F, 0x000335A3,
+		0x030, 0x00006000,
+		0x03F, 0x000335A3,
+		0x030, 0x00007000,
+		0x03F, 0x000335A3,
+		0x030, 0x00008000,
+		0x03F, 0x000335A3,
+		0x030, 0x00009000,
+		0x03F, 0x000335A3,
+		0x030, 0x0000A000,
+		0x03F, 0x000335A3,
+		0x030, 0x0000B000,
+		0x03F, 0x000335A3,
+		0x0EF, 0x00000000,
+	0xB0000000,	0x00000000,
+	0x80001005,	0x00000000,	0x40000000,	0x00000000,
+		0x0EF, 0x00000080,
+		0x033, 0x00000000,
+		0x03F, 0x00033303,
+		0x033, 0x00000001,
+		0x03F, 0x00033303,
+		0x033, 0x00000002,
+		0x03F, 0x00033303,
+		0x033, 0x00000003,
+		0x03F, 0x00033303,
+		0x033, 0x00000004,
+		0x03F, 0x00033303,
+		0x033, 0x00000005,
+		0x03F, 0x00033303,
+		0x033, 0x00000006,
+		0x03F, 0x00033303,
+		0x033, 0x00000007,
+		0x03F, 0x00033303,
+		0x033, 0x00000008,
+		0x03F, 0x00033303,
+		0x033, 0x00000009,
+		0x03F, 0x00033303,
+		0x033, 0x0000000A,
+		0x03F, 0x00033303,
+		0x033, 0x0000000B,
+		0x03F, 0x00033303,
+		0x033, 0x0000000C,
+		0x03F, 0x00033303,
+		0x033, 0x0000000D,
+		0x03F, 0x00033303,
+		0x033, 0x0000000E,
+		0x03F, 0x00033303,
+		0x033, 0x0000000F,
+		0x03F, 0x00033303,
+		0x033, 0x00000010,
+		0x03F, 0x00033303,
+		0x033, 0x00000011,
+		0x03F, 0x00033303,
+		0x033, 0x00000012,
+		0x03F, 0x00033303,
+		0x0EF, 0x00000000,
+	0x90001004,	0x00000000,	0x40000000,	0x00000000,
+		0x0EF, 0x00000080,
+		0x033, 0x00000000,
+		0x03F, 0x00033303,
+		0x033, 0x00000001,
+		0x03F, 0x00033303,
+		0x033, 0x00000002,
+		0x03F, 0x00033303,
+		0x033, 0x00000003,
+		0x03F, 0x00033303,
+		0x033, 0x00000004,
+		0x03F, 0x00033303,
+		0x033, 0x00000005,
+		0x03F, 0x00033303,
+		0x033, 0x00000006,
+		0x03F, 0x00033303,
+		0x033, 0x00000007,
+		0x03F, 0x00033303,
+		0x033, 0x00000008,
+		0x03F, 0x000313A3,
+		0x033, 0x00000009,
+		0x03F, 0x000313A3,
+		0x033, 0x0000000A,
+		0x03F, 0x000313A3,
+		0x033, 0x0000000B,
+		0x03F, 0x000313A3,
+		0x033, 0x0000000C,
+		0x03F, 0x000313A3,
+		0x033, 0x0000000D,
+		0x03F, 0x000333A3,
+		0x033, 0x0000000E,
+		0x03F, 0x000333A3,
+		0x033, 0x0000000F,
+		0x03F, 0x000333A3,
+		0x033, 0x00000010,
+		0x03F, 0x000333A3,
+		0x033, 0x00000011,
+		0x03F, 0x000333A3,
+		0x033, 0x00000012,
+		0x03F, 0x000333A3,
+		0x0EF, 0x00000000,
+	0x90000400,	0x00000000,	0x40000000,	0x00000000,
+		0x0EF, 0x00000080,
+		0x033, 0x00000000,
+		0x03F, 0x000335A3,
+		0x033, 0x00000001,
+		0x03F, 0x000335A3,
+		0x033, 0x00000002,
+		0x03F, 0x000335A3,
+		0x033, 0x00000003,
+		0x03F, 0x000335A3,
+		0x033, 0x00000004,
+		0x03F, 0x000335A3,
+		0x033, 0x00000005,
+		0x03F, 0x000335A3,
+		0x033, 0x00000006,
+		0x03F, 0x000335A3,
+		0x033, 0x00000007,
+		0x03F, 0x000335A3,
+		0x033, 0x00000008,
+		0x03F, 0x000335A3,
+		0x033, 0x00000009,
+		0x03F, 0x000335A3,
+		0x033, 0x0000000A,
+		0x03F, 0x000335A3,
+		0x033, 0x0000000B,
+		0x03F, 0x000335A3,
+		0x033, 0x0000000C,
+		0x03F, 0x000335A3,
+		0x033, 0x0000000D,
+		0x03F, 0x000335A3,
+		0x033, 0x0000000E,
+		0x03F, 0x000335A3,
+		0x033, 0x0000000F,
+		0x03F, 0x000335A3,
+		0x033, 0x00000010,
+		0x03F, 0x000335A3,
+		0x033, 0x00000011,
+		0x03F, 0x000335A3,
+		0x033, 0x00000012,
+		0x03F, 0x000335A3,
+		0x0EF, 0x00000000,
+	0xA0000000,	0x00000000,
+		0x0EF, 0x00000080,
+		0x033, 0x00000000,
+		0x03F, 0x000335A3,
+		0x033, 0x00000001,
+		0x03F, 0x000335A3,
+		0x033, 0x00000002,
+		0x03F, 0x000335A3,
+		0x033, 0x00000003,
+		0x03F, 0x000335A3,
+		0x033, 0x00000004,
+		0x03F, 0x000335A3,
+		0x033, 0x00000005,
+		0x03F, 0x000335A3,
+		0x033, 0x00000006,
+		0x03F, 0x000335A3,
+		0x033, 0x00000007,
+		0x03F, 0x000335A3,
+		0x033, 0x00000008,
+		0x03F, 0x000335A3,
+		0x033, 0x00000009,
+		0x03F, 0x000335A3,
+		0x033, 0x0000000A,
+		0x03F, 0x000335A3,
+		0x033, 0x0000000B,
+		0x03F, 0x000335A3,
+		0x033, 0x0000000C,
+		0x03F, 0x000335A3,
+		0x033, 0x0000000D,
+		0x03F, 0x000335A3,
+		0x033, 0x0000000E,
+		0x03F, 0x000335A3,
+		0x033, 0x0000000F,
+		0x03F, 0x000335A3,
+		0x033, 0x00000010,
+		0x03F, 0x000335A3,
+		0x033, 0x00000011,
+		0x03F, 0x000335A3,
+		0x033, 0x00000012,
+		0x03F, 0x000335A3,
+		0x0EF, 0x00000000,
+	0xB0000000,	0x00000000,
+	0x80001005,	0x00000000,	0x40000000,	0x00000000,
+		0x0EF, 0x00000040,
+		0x030, 0x00000644,
+		0x030, 0x00001135,
+		0x030, 0x00002133,
+		0x030, 0x00004000,
+		0x030, 0x00005000,
+		0x030, 0x00006000,
+		0x0EF, 0x00000000,
+	0x90001004,	0x00000000,	0x40000000,	0x00000000,
+		0x0EF, 0x00000040,
+		0x030, 0x00000644,
+		0x030, 0x00001412,
+		0x030, 0x00002202,
+		0x030, 0x00004000,
+		0x030, 0x00005000,
+		0x030, 0x00006000,
+		0x0EF, 0x00000000,
+	0x90000400,	0x00000000,	0x40000000,	0x00000000,
+		0x0EF, 0x00000040,
+		0x030, 0x00000640,
+		0x030, 0x00001512,
+		0x030, 0x00002202,
+		0x030, 0x00004000,
+		0x030, 0x00005000,
+		0x030, 0x00006000,
+		0x0EF, 0x00000000,
+	0xA0000000,	0x00000000,
+		0x0EF, 0x00000040,
+		0x030, 0x00000640,
+		0x030, 0x00001512,
+		0x030, 0x00002202,
+		0x030, 0x00004000,
+		0x030, 0x00005000,
+		0x030, 0x00006000,
+		0x0EF, 0x00000000,
+	0xB0000000,	0x00000000,
+	0x80001005,	0x00000000,	0x40000000,	0x00000000,
+		0x0EF, 0x00000800,
+	0x90001004,	0x00000000,	0x40000000,	0x00000000,
+		0x0EF, 0x00000800,
+	0x90000400,	0x00000000,	0x40000000,	0x00000000,
+		0x0EF, 0x00000800,
+	0xA0000000,	0x00000000,
+		0x0EF, 0x00000800,
+	0xB0000000,	0x00000000,
+	0x80001005,	0x00000000,	0x40000000,	0x00000000,
+		0x033, 0x00000020,
+		0x03F, 0x00000001,
+		0x033, 0x00000021,
+		0x03F, 0x00000004,
+		0x033, 0x00000022,
+		0x03F, 0x00000007,
+		0x033, 0x00000023,
+		0x03F, 0x00000024,
+		0x033, 0x00000024,
+		0x03F, 0x00000027,
+		0x033, 0x00000025,
+		0x03F, 0x0000002A,
+		0x033, 0x00000026,
+		0x03F, 0x0000002D,
+		0x033, 0x00000027,
+		0x03F, 0x00000030,
+		0x033, 0x00000028,
+		0x03F, 0x00000033,
+		0x033, 0x00000029,
+		0x03F, 0x00000036,
+		0x033, 0x0000002A,
+		0x03F, 0x00000039,
+	0x90001004,	0x00000000,	0x40000000,	0x00000000,
+		0x033, 0x00000020,
+		0x03F, 0x00000E42,
+		0x033, 0x00000021,
+		0x03F, 0x00000E45,
+		0x033, 0x00000022,
+		0x03F, 0x00000E65,
+		0x033, 0x00000023,
+		0x03F, 0x00000E68,
+		0x033, 0x00000024,
+		0x03F, 0x00000EE4,
+		0x033, 0x00000025,
+		0x03F, 0x00000EE7,
+		0x033, 0x00000026,
+		0x03F, 0x00000EEA,
+		0x033, 0x00000027,
+		0x03F, 0x00000EED,
+		0x033, 0x00000028,
+		0x03F, 0x00000EF0,
+		0x033, 0x00000029,
+		0x03F, 0x00000EF3,
+		0x033, 0x0000002A,
+		0x03F, 0x00000EF6,
+	0x90000400,	0x00000000,	0x40000000,	0x00000000,
+		0x033, 0x00000020,
+		0x03F, 0x00000E42,
+		0x033, 0x00000021,
+		0x03F, 0x00000E45,
+		0x033, 0x00000022,
+		0x03F, 0x00000E48,
+		0x033, 0x00000023,
+		0x03F, 0x00000E68,
+		0x033, 0x00000024,
+		0x03F, 0x00000E6B,
+		0x033, 0x00000025,
+		0x03F, 0x00000EAA,
+		0x033, 0x00000026,
+		0x03F, 0x00000EEA,
+		0x033, 0x00000027,
+		0x03F, 0x00000EED,
+		0x033, 0x00000028,
+		0x03F, 0x00000EF0,
+		0x033, 0x00000029,
+		0x03F, 0x00000EF3,
+		0x033, 0x0000002A,
+		0x03F, 0x00000EF6,
+	0xA0000000,	0x00000000,
+		0x033, 0x00000020,
+		0x03F, 0x00000E42,
+		0x033, 0x00000021,
+		0x03F, 0x00000E45,
+		0x033, 0x00000022,
+		0x03F, 0x00000E65,
+		0x033, 0x00000023,
+		0x03F, 0x00000E68,
+		0x033, 0x00000024,
+		0x03F, 0x00000EE4,
+		0x033, 0x00000025,
+		0x03F, 0x00000EE7,
+		0x033, 0x00000026,
+		0x03F, 0x00000EEA,
+		0x033, 0x00000027,
+		0x03F, 0x00000EED,
+		0x033, 0x00000028,
+		0x03F, 0x00000EF0,
+		0x033, 0x00000029,
+		0x03F, 0x00000EF3,
+		0x033, 0x0000002A,
+		0x03F, 0x00000EF6,
+	0xB0000000,	0x00000000,
+	0x80001005,	0x00000000,	0x40000000,	0x00000000,
+		0x033, 0x00000060,
+		0x03F, 0x00000001,
+		0x033, 0x00000061,
+		0x03F, 0x00000004,
+		0x033, 0x00000062,
+		0x03F, 0x00000007,
+		0x033, 0x00000063,
+		0x03F, 0x00000024,
+		0x033, 0x00000064,
+		0x03F, 0x00000027,
+		0x033, 0x00000065,
+		0x03F, 0x0000002A,
+		0x033, 0x00000066,
+		0x03F, 0x0000002D,
+		0x033, 0x00000067,
+		0x03F, 0x00000030,
+		0x033, 0x00000068,
+		0x03F, 0x00000033,
+		0x033, 0x00000069,
+		0x03F, 0x00000036,
+		0x033, 0x0000006A,
+		0x03F, 0x00000039,
+	0x90001004,	0x00000000,	0x40000000,	0x00000000,
+		0x033, 0x00000060,
+		0x03F, 0x00000E42,
+		0x033, 0x00000061,
+		0x03F, 0x00000E45,
+		0x033, 0x00000062,
+		0x03F, 0x00000E65,
+		0x033, 0x00000063,
+		0x03F, 0x00000E68,
+		0x033, 0x00000064,
+		0x03F, 0x00000EE5,
+		0x033, 0x00000065,
+		0x03F, 0x00000EE8,
+		0x033, 0x00000066,
+		0x03F, 0x00000EEB,
+		0x033, 0x00000067,
+		0x03F, 0x00000EEE,
+		0x033, 0x00000068,
+		0x03F, 0x00000EF1,
+		0x033, 0x00000069,
+		0x03F, 0x00000EF4,
+		0x033, 0x0000006A,
+		0x03F, 0x00000EF7,
+	0x90000400,	0x00000000,	0x40000000,	0x00000000,
+		0x033, 0x00000060,
+		0x03F, 0x00000E09,
+		0x033, 0x00000061,
+		0x03F, 0x00000E43,
+		0x033, 0x00000062,
+		0x03F, 0x00000E46,
+		0x033, 0x00000063,
+		0x03F, 0x00000E49,
+		0x033, 0x00000064,
+		0x03F, 0x00000E88,
+		0x033, 0x00000065,
+		0x03F, 0x00000E8B,
+		0x033, 0x00000066,
+		0x03F, 0x00000ECB,
+		0x033, 0x00000067,
+		0x03F, 0x00000ECE,
+		0x033, 0x00000068,
+		0x03F, 0x00000EF0,
+		0x033, 0x00000069,
+		0x03F, 0x00000EF3,
+		0x033, 0x0000006A,
+		0x03F, 0x00000EF6,
+	0xA0000000,	0x00000000,
+		0x033, 0x00000060,
+		0x03F, 0x00000E42,
+		0x033, 0x00000061,
+		0x03F, 0x00000E45,
+		0x033, 0x00000062,
+		0x03F, 0x00000E65,
+		0x033, 0x00000063,
+		0x03F, 0x00000E68,
+		0x033, 0x00000064,
+		0x03F, 0x00000EE5,
+		0x033, 0x00000065,
+		0x03F, 0x00000EE8,
+		0x033, 0x00000066,
+		0x03F, 0x00000EEB,
+		0x033, 0x00000067,
+		0x03F, 0x00000EEE,
+		0x033, 0x00000068,
+		0x03F, 0x00000EF1,
+		0x033, 0x00000069,
+		0x03F, 0x00000EF4,
+		0x033, 0x0000006A,
+		0x03F, 0x00000EF7,
+	0xB0000000,	0x00000000,
+	0x80001005,	0x00000000,	0x40000000,	0x00000000,
+		0x033, 0x000000A0,
+		0x03F, 0x00000001,
+		0x033, 0x000000A1,
+		0x03F, 0x00000004,
+		0x033, 0x000000A2,
+		0x03F, 0x00000007,
+		0x033, 0x000000A3,
+		0x03F, 0x00000025,
+		0x033, 0x000000A4,
+		0x03F, 0x00000028,
+		0x033, 0x000000A5,
+		0x03F, 0x0000002B,
+		0x033, 0x000000A6,
+		0x03F, 0x0000002E,
+		0x033, 0x000000A7,
+		0x03F, 0x00000031,
+		0x033, 0x000000A8,
+		0x03F, 0x00000034,
+		0x033, 0x000000A9,
+		0x03F, 0x00000037,
+		0x033, 0x000000AA,
+		0x03F, 0x0000003A,
+		0x0EF, 0x00000000,
+	0x90001004,	0x00000000,	0x40000000,	0x00000000,
+		0x033, 0x000000A0,
+		0x03F, 0x00000E09,
+		0x033, 0x000000A1,
+		0x03F, 0x00000E43,
+		0x033, 0x000000A2,
+		0x03F, 0x00000E64,
+		0x033, 0x000000A3,
+		0x03F, 0x00000E67,
+		0x033, 0x000000A4,
+		0x03F, 0x00000EE4,
+		0x033, 0x000000A5,
+		0x03F, 0x00000EE7,
+		0x033, 0x000000A6,
+		0x03F, 0x00000EEA,
+		0x033, 0x000000A7,
+		0x03F, 0x00000EED,
+		0x033, 0x000000A8,
+		0x03F, 0x00000EF0,
+		0x033, 0x000000A9,
+		0x03F, 0x00000EF3,
+		0x033, 0x000000AA,
+		0x03F, 0x00000EF6,
+		0x0EF, 0x00000000,
+	0x90000400,	0x00000000,	0x40000000,	0x00000000,
+		0x033, 0x000000A0,
+		0x03F, 0x00000E08,
+		0x033, 0x000000A1,
+		0x03F, 0x00000E42,
+		0x033, 0x000000A2,
+		0x03F, 0x00000E45,
+		0x033, 0x000000A3,
+		0x03F, 0x00000E48,
+		0x033, 0x000000A4,
+		0x03F, 0x00000EA5,
+		0x033, 0x000000A5,
+		0x03F, 0x00000EA8,
+		0x033, 0x000000A6,
+		0x03F, 0x00000ECA,
+		0x033, 0x000000A7,
+		0x03F, 0x00000ECD,
+		0x033, 0x000000A8,
+		0x03F, 0x00000EEF,
+		0x033, 0x000000A9,
+		0x03F, 0x00000EF2,
+		0x033, 0x000000AA,
+		0x03F, 0x00000EF5,
+		0x0EF, 0x00000000,
+	0xA0000000,	0x00000000,
+		0x033, 0x000000A0,
+		0x03F, 0x00000E09,
+		0x033, 0x000000A1,
+		0x03F, 0x00000E43,
+		0x033, 0x000000A2,
+		0x03F, 0x00000E64,
+		0x033, 0x000000A3,
+		0x03F, 0x00000E67,
+		0x033, 0x000000A4,
+		0x03F, 0x00000EE4,
+		0x033, 0x000000A5,
+		0x03F, 0x00000EE7,
+		0x033, 0x000000A6,
+		0x03F, 0x00000EEA,
+		0x033, 0x000000A7,
+		0x03F, 0x00000EED,
+		0x033, 0x000000A8,
+		0x03F, 0x00000EF0,
+		0x033, 0x000000A9,
+		0x03F, 0x00000EF3,
+		0x033, 0x000000AA,
+		0x03F, 0x00000EF6,
+		0x0EF, 0x00000000,
+	0xB0000000,	0x00000000,
+	0x80001005,	0x00000000,	0x40000000,	0x00000000,
+		0x0EF, 0x00000400,
+		0x033, 0x00000000,
+		0x03F, 0x0006AC00,
+		0x033, 0x00000001,
+		0x03F, 0x00060C00,
+		0x033, 0x00000002,
+		0x03F, 0x0006AC00,
+		0x033, 0x00000003,
+		0x03F, 0x00086A00,
+		0x0EF, 0x00000000,
+	0x90001004,	0x00000000,	0x40000000,	0x00000000,
+		0x0EF, 0x00000400,
+		0x033, 0x00000000,
+		0x03F, 0x0006AC00,
+		0x033, 0x00000001,
+		0x03F, 0x00060C00,
+		0x033, 0x00000002,
+		0x03F, 0x0006AC00,
+		0x033, 0x00000003,
+		0x03F, 0x00086A00,
+		0x0EF, 0x00000000,
+	0x90000400,	0x00000000,	0x40000000,	0x00000000,
+		0x0EF, 0x00000400,
+		0x033, 0x00000000,
+		0x03F, 0x0006AC00,
+		0x033, 0x00000001,
+		0x03F, 0x00060C00,
+		0x033, 0x00000002,
+		0x03F, 0x0006AC00,
+		0x033, 0x00000003,
+		0x03F, 0x00086A00,
+		0x0EF, 0x00000000,
+	0xA0000000,	0x00000000,
+		0x0EF, 0x00000400,
+		0x033, 0x00000000,
+		0x03F, 0x0006AC00,
+		0x033, 0x00000001,
+		0x03F, 0x00060C00,
+		0x033, 0x00000002,
+		0x03F, 0x0006AC00,
+		0x033, 0x00000003,
+		0x03F, 0x00086A00,
+		0x0EF, 0x00000000,
+	0xB0000000,	0x00000000,
+	0x80001005,	0x00000000,	0x40000000,	0x00000000,
+		0x0EF, 0x00000100,
+		0x033, 0x00000000,
+		0x03F, 0x00000040,
+		0x033, 0x00000001,
+		0x03F, 0x00000040,
+		0x033, 0x00000002,
+		0x03F, 0x00000040,
+		0x033, 0x00000003,
+		0x03F, 0x00000040,
+		0x0EF, 0x00000000,
+	0x90001004,	0x00000000,	0x40000000,	0x00000000,
+		0x0EF, 0x00000100,
+		0x033, 0x00000000,
+		0x03F, 0x00000040,
+		0x033, 0x00000001,
+		0x03F, 0x00000040,
+		0x033, 0x00000002,
+		0x03F, 0x00000040,
+		0x033, 0x00000003,
+		0x03F, 0x00000040,
+		0x0EF, 0x00000000,
+	0x90000400,	0x00000000,	0x40000000,	0x00000000,
+		0x0EF, 0x00000100,
+		0x033, 0x00000000,
+		0x03F, 0x00000040,
+		0x033, 0x00000001,
+		0x03F, 0x00000040,
+		0x033, 0x00000002,
+		0x03F, 0x00000040,
+		0x033, 0x00000003,
+		0x03F, 0x00000040,
+		0x0EF, 0x00000000,
+	0xA0000000,	0x00000000,
+		0x0EF, 0x00000100,
+		0x033, 0x00000000,
+		0x03F, 0x00000040,
+		0x033, 0x00000001,
+		0x03F, 0x00000040,
+		0x033, 0x00000002,
+		0x03F, 0x00000040,
+		0x033, 0x00000003,
+		0x03F, 0x00000040,
+		0x0EF, 0x00000000,
+	0xB0000000,	0x00000000,
+	0x80001005,	0x00000000,	0x40000000,	0x00000000,
+		0x0EF, 0x00040000,
+		0x033, 0x00000000,
+		0x03F, 0x00086A40,
+		0x033, 0x00000001,
+		0x03F, 0x00086A40,
+		0x033, 0x00000002,
+		0x03F, 0x00086A40,
+		0x033, 0x00000003,
+		0x03F, 0x00086A40,
+		0x033, 0x00000004,
+		0x03F, 0x00086A40,
+		0x033, 0x00000005,
+		0x03F, 0x00086A40,
+		0x033, 0x00000006,
+		0x03F, 0x00084A40,
+		0x033, 0x00000007,
+		0x03F, 0x00084A40,
+		0x0EF, 0x00000000,
+	0x90001004,	0x00000000,	0x40000000,	0x00000000,
+		0x0EF, 0x00040000,
+		0x033, 0x00000000,
+		0x03F, 0x00086A40,
+		0x033, 0x00000001,
+		0x03F, 0x00086A40,
+		0x033, 0x00000002,
+		0x03F, 0x00086A40,
+		0x033, 0x00000003,
+		0x03F, 0x00086A40,
+		0x033, 0x00000004,
+		0x03F, 0x00086A40,
+		0x033, 0x00000005,
+		0x03F, 0x00086A40,
+		0x033, 0x00000006,
+		0x03F, 0x00084A40,
+		0x033, 0x00000007,
+		0x03F, 0x00084A40,
+		0x0EF, 0x00000000,
+	0x90000400,	0x00000000,	0x40000000,	0x00000000,
+		0x0EF, 0x00040000,
+		0x033, 0x00000000,
+		0x03F, 0x00086A40,
+		0x033, 0x00000001,
+		0x03F, 0x00086A40,
+		0x033, 0x00000002,
+		0x03F, 0x00086A40,
+		0x033, 0x00000003,
+		0x03F, 0x00086A40,
+		0x033, 0x00000004,
+		0x03F, 0x00086A40,
+		0x033, 0x00000005,
+		0x03F, 0x00086A40,
+		0x033, 0x00000006,
+		0x03F, 0x00084A40,
+		0x033, 0x00000007,
+		0x03F, 0x00084A40,
+		0x0EF, 0x00000000,
+	0xA0000000,	0x00000000,
+		0x0EF, 0x00040000,
+		0x033, 0x00000000,
+		0x03F, 0x00086A40,
+		0x033, 0x00000001,
+		0x03F, 0x00086A40,
+		0x033, 0x00000002,
+		0x03F, 0x00086A40,
+		0x033, 0x00000003,
+		0x03F, 0x00086A40,
+		0x033, 0x00000004,
+		0x03F, 0x00086A40,
+		0x033, 0x00000005,
+		0x03F, 0x00086A40,
+		0x033, 0x00000006,
+		0x03F, 0x00084A40,
+		0x033, 0x00000007,
+		0x03F, 0x00084A40,
+		0x0EF, 0x00000000,
+	0xB0000000,	0x00000000,
+	0x80001005,	0x00000000,	0x40000000,	0x00000000,
+		0x051, 0x000801A8,
+		0x052, 0x000972E3,
+		0x053, 0x00008069,
+		0x054, 0x00030032,
+		0x055, 0x00082003,
+		0x056, 0x00051CCB,
+		0x057, 0x0000CFC2,
+		0x058, 0x00000010,
+		0x059, 0x00030000,
+	0x90001004,	0x00000000,	0x40000000,	0x00000000,
+		0x051, 0x000801A8,
+		0x052, 0x000972E3,
+		0x053, 0x00008069,
+		0x054, 0x00030032,
+		0x055, 0x00082003,
+		0x056, 0x00051CCB,
+		0x057, 0x0000CFC2,
+		0x058, 0x00000010,
+		0x059, 0x00030000,
+	0x90000400,	0x00000000,	0x40000000,	0x00000000,
+		0x051, 0x000801A8,
+		0x052, 0x000972E3,
+		0x053, 0x00008069,
+		0x054, 0x00030032,
+		0x055, 0x00082003,
+		0x056, 0x00051CCB,
+		0x057, 0x0000CFC2,
+		0x058, 0x00000010,
+		0x059, 0x00030000,
+	0xA0000000,	0x00000000,
+		0x051, 0x000801A8,
+		0x052, 0x000972E3,
+		0x053, 0x00008069,
+		0x054, 0x00030032,
+		0x055, 0x00082003,
+		0x056, 0x00051CCB,
+		0x057, 0x0000CFC2,
+		0x058, 0x00000010,
+		0x059, 0x00030000,
+	0xB0000000,	0x00000000,
+	0x80001005,	0x00000000,	0x40000000,	0x00000000,
+		0x0EF, 0x00000800,
+		0x033, 0x00000000,
+		0x03F, 0x00051429,
+		0x033, 0x00000001,
+		0x03F, 0x00051449,
+		0x033, 0x00000002,
+		0x03F, 0x0005144C,
+		0x033, 0x00000003,
+		0x03F, 0x00051C66,
+		0x033, 0x00000004,
+		0x03F, 0x00051C69,
+		0x033, 0x00000005,
+		0x03F, 0x00051C6C,
+		0x033, 0x00000006,
+		0x03F, 0x00051CE8,
+		0x033, 0x00000007,
+		0x03F, 0x00051CEB,
+		0x033, 0x00000008,
+		0x03F, 0x00051CEE,
+		0x033, 0x00000009,
+		0x03F, 0x00051CF1,
+		0x033, 0x0000000A,
+		0x03F, 0x00051CF4,
+		0x0EF, 0x00000000,
+	0x90001004,	0x00000000,	0x40000000,	0x00000000,
+		0x0EF, 0x00000800,
+		0x033, 0x00000000,
+		0x03F, 0x00051429,
+		0x033, 0x00000001,
+		0x03F, 0x00051449,
+		0x033, 0x00000002,
+		0x03F, 0x0005144C,
+		0x033, 0x00000003,
+		0x03F, 0x00051C66,
+		0x033, 0x00000004,
+		0x03F, 0x00051C69,
+		0x033, 0x00000005,
+		0x03F, 0x00051C6C,
+		0x033, 0x00000006,
+		0x03F, 0x00051CE8,
+		0x033, 0x00000007,
+		0x03F, 0x00051CEB,
+		0x033, 0x00000008,
+		0x03F, 0x00051CEE,
+		0x033, 0x00000009,
+		0x03F, 0x00051CF1,
+		0x033, 0x0000000A,
+		0x03F, 0x00051CF4,
+		0x0EF, 0x00000000,
+	0x90000400,	0x00000000,	0x40000000,	0x00000000,
+		0x0EF, 0x00000800,
+		0x033, 0x00000000,
+		0x03F, 0x00051427,
+		0x033, 0x00000001,
+		0x03F, 0x00051446,
+		0x033, 0x00000002,
+		0x03F, 0x00051449,
+		0x033, 0x00000003,
+		0x03F, 0x0005144C,
+		0x033, 0x00000004,
+		0x03F, 0x00051C67,
+		0x033, 0x00000005,
+		0x03F, 0x00051C6A,
+		0x033, 0x00000006,
+		0x03F, 0x00051C8B,
+		0x033, 0x00000007,
+		0x03F, 0x00051CE9,
+		0x033, 0x00000008,
+		0x03F, 0x00051CEC,
+		0x033, 0x00000009,
+		0x03F, 0x00051CEF,
+		0x033, 0x0000000A,
+		0x03F, 0x00051CF2,
+		0x0EF, 0x00000000,
+	0xA0000000,	0x00000000,
+		0x0EF, 0x00000800,
+		0x033, 0x00000000,
+		0x03F, 0x00051427,
+		0x033, 0x00000001,
+		0x03F, 0x00051446,
+		0x033, 0x00000002,
+		0x03F, 0x00051449,
+		0x033, 0x00000003,
+		0x03F, 0x0005144C,
+		0x033, 0x00000004,
+		0x03F, 0x00051C67,
+		0x033, 0x00000005,
+		0x03F, 0x00051C6A,
+		0x033, 0x00000006,
+		0x03F, 0x00051C8B,
+		0x033, 0x00000007,
+		0x03F, 0x00051CE9,
+		0x033, 0x00000008,
+		0x03F, 0x00051CEC,
+		0x033, 0x00000009,
+		0x03F, 0x00051CEF,
+		0x033, 0x0000000A,
+		0x03F, 0x00051CF2,
+		0x0EF, 0x00000000,
+	0xB0000000,	0x00000000,
+	0x80001005,	0x00000000,	0x40000000,	0x00000000,
+		0x0EE, 0x00004000,
+		0x033, 0x00000000,
+		0x03F, 0x00048400,
+		0x033, 0x00000001,
+		0x03F, 0x00086E00,
+		0x033, 0x00000002,
+		0x03F, 0x00048400,
+		0x033, 0x00000003,
+		0x03F, 0x00048400,
+		0x0EE, 0x00000000,
+	0x90001004,	0x00000000,	0x40000000,	0x00000000,
+		0x0EE, 0x00004000,
+		0x033, 0x00000000,
+		0x03F, 0x00048400,
+		0x033, 0x00000001,
+		0x03F, 0x00086E00,
+		0x033, 0x00000002,
+		0x03F, 0x00048400,
+		0x033, 0x00000003,
+		0x03F, 0x00048400,
+		0x0EE, 0x00000000,
+	0x90000400,	0x00000000,	0x40000000,	0x00000000,
+		0x0EE, 0x00004000,
+		0x033, 0x00000000,
+		0x03F, 0x00048400,
+		0x033, 0x00000001,
+		0x03F, 0x00086E00,
+		0x033, 0x00000002,
+		0x03F, 0x00048400,
+		0x033, 0x00000003,
+		0x03F, 0x00048400,
+		0x0EE, 0x00000000,
+	0xA0000000,	0x00000000,
+		0x0EE, 0x00004000,
+		0x033, 0x00000000,
+		0x03F, 0x00048400,
+		0x033, 0x00000001,
+		0x03F, 0x00086E00,
+		0x033, 0x00000002,
+		0x03F, 0x00048400,
+		0x033, 0x00000003,
+		0x03F, 0x00048400,
+		0x0EE, 0x00000000,
+	0xB0000000,	0x00000000,
+	0x80001005,	0x00000000,	0x40000000,	0x00000000,
+		0x0EE, 0x00002000,
+		0x033, 0x00000000,
+		0x03F, 0x00000000,
+		0x033, 0x00000001,
+		0x03F, 0x00000000,
+		0x033, 0x00000002,
+		0x03F, 0x00000000,
+		0x033, 0x00000003,
+		0x03F, 0x00000000,
+		0x0EE, 0x00000000,
+	0x90001004,	0x00000000,	0x40000000,	0x00000000,
+		0x0EE, 0x00002000,
+		0x033, 0x00000000,
+		0x03F, 0x00000000,
+		0x033, 0x00000001,
+		0x03F, 0x00000000,
+		0x033, 0x00000002,
+		0x03F, 0x00000000,
+		0x033, 0x00000003,
+		0x03F, 0x00000000,
+		0x0EE, 0x00000000,
+	0x90000400,	0x00000000,	0x40000000,	0x00000000,
+		0x0EE, 0x00002000,
+		0x033, 0x00000000,
+		0x03F, 0x00000000,
+		0x033, 0x00000001,
+		0x03F, 0x00000000,
+		0x033, 0x00000002,
+		0x03F, 0x00000000,
+		0x033, 0x00000003,
+		0x03F, 0x00000000,
+		0x0EE, 0x00000000,
+	0xA0000000,	0x00000000,
+		0x0EE, 0x00002000,
+		0x033, 0x00000000,
+		0x03F, 0x00000000,
+		0x033, 0x00000001,
+		0x03F, 0x00000000,
+		0x033, 0x00000002,
+		0x03F, 0x00000000,
+		0x033, 0x00000003,
+		0x03F, 0x00000000,
+		0x0EE, 0x00000000,
+	0xB0000000,	0x00000000,
+	0x80001005,	0x00000000,	0x40000000,	0x00000000,
+		0x0EE, 0x00080000,
+		0x033, 0x00000000,
+		0x03F, 0x00048400,
+		0x033, 0x00000001,
+		0x03F, 0x00048400,
+		0x033, 0x00000002,
+		0x03F, 0x00048400,
+		0x033, 0x00000003,
+		0x03F, 0x00048400,
+		0x033, 0x00000004,
+		0x03F, 0x00048400,
+		0x033, 0x00000005,
+		0x03F, 0x00048400,
+		0x033, 0x00000006,
+		0x03F, 0x00048400,
+		0x033, 0x00000007,
+		0x03F, 0x00048400,
+		0x0EE, 0x00000000,
+	0x90001004,	0x00000000,	0x40000000,	0x00000000,
+		0x0EE, 0x00080000,
+		0x033, 0x00000000,
+		0x03F, 0x00048400,
+		0x033, 0x00000001,
+		0x03F, 0x00048400,
+		0x033, 0x00000002,
+		0x03F, 0x00048400,
+		0x033, 0x00000003,
+		0x03F, 0x00048400,
+		0x033, 0x00000004,
+		0x03F, 0x00048400,
+		0x033, 0x00000005,
+		0x03F, 0x00048400,
+		0x033, 0x00000006,
+		0x03F, 0x00048400,
+		0x033, 0x00000007,
+		0x03F, 0x00048400,
+		0x0EE, 0x00000000,
+	0x90000400,	0x00000000,	0x40000000,	0x00000000,
+		0x0EE, 0x00080000,
+		0x033, 0x00000000,
+		0x03F, 0x00048400,
+		0x033, 0x00000001,
+		0x03F, 0x00048400,
+		0x033, 0x00000002,
+		0x03F, 0x00048400,
+		0x033, 0x00000003,
+		0x03F, 0x00048400,
+		0x033, 0x00000004,
+		0x03F, 0x00048400,
+		0x033, 0x00000005,
+		0x03F, 0x00048400,
+		0x033, 0x00000006,
+		0x03F, 0x00048400,
+		0x033, 0x00000007,
+		0x03F, 0x00048400,
+		0x0EE, 0x00000000,
+	0xA0000000,	0x00000000,
+		0x0EE, 0x00080000,
+		0x033, 0x00000000,
+		0x03F, 0x00048400,
+		0x033, 0x00000001,
+		0x03F, 0x00048400,
+		0x033, 0x00000002,
+		0x03F, 0x00048400,
+		0x033, 0x00000003,
+		0x03F, 0x00048400,
+		0x033, 0x00000004,
+		0x03F, 0x00048400,
+		0x033, 0x00000005,
+		0x03F, 0x00048400,
+		0x033, 0x00000006,
+		0x03F, 0x00048400,
+		0x033, 0x00000007,
+		0x03F, 0x00048400,
+		0x0EE, 0x00000000,
+	0xB0000000,	0x00000000,
+	0x80001005,	0x00000000,	0x40000000,	0x00000000,
+		0x070, 0x00008000,
+		0x075, 0x000027DA,
+		0x076, 0x00006997,
+		0x077, 0x00070418,
+		0x078, 0x000BB000,
+		0x07D, 0x00007600,
+		0x07F, 0x00000000,
+		0x06A, 0x000F4C00,
+		0x065, 0x00082030,
+	0x90001004,	0x00000000,	0x40000000,	0x00000000,
+		0x070, 0x00008000,
+		0x075, 0x000027DA,
+		0x076, 0x00006997,
+		0x077, 0x00070418,
+		0x078, 0x000BB000,
+		0x07D, 0x00007600,
+		0x07F, 0x00000000,
+		0x06A, 0x000F4C00,
+		0x065, 0x00082030,
+	0x90000400,	0x00000000,	0x40000000,	0x00000000,
+		0x070, 0x00008000,
+		0x075, 0x000027DA,
+		0x076, 0x00006997,
+		0x077, 0x00070418,
+		0x078, 0x000BB000,
+		0x07D, 0x00007600,
+		0x07F, 0x00000000,
+		0x06A, 0x000F4C00,
+		0x065, 0x00082030,
+	0xA0000000,	0x00000000,
+		0x070, 0x00008000,
+		0x075, 0x000027DA,
+		0x076, 0x00006997,
+		0x077, 0x00070418,
+		0x078, 0x000BB000,
+		0x07D, 0x00007600,
+		0x07F, 0x00000000,
+		0x06A, 0x000F4C00,
+		0x065, 0x00082030,
+	0xB0000000,	0x00000000,
+	0x80001005,	0x00000000,	0x40000000,	0x00000000,
+		0x0EE, 0x00008000,
+		0x033, 0x00000000,
+		0x03F, 0x00051427,
+		0x033, 0x00000001,
+		0x03F, 0x00051446,
+		0x033, 0x00000002,
+		0x03F, 0x00051449,
+		0x033, 0x00000003,
+		0x03F, 0x0005144C,
+		0x033, 0x00000004,
+		0x03F, 0x00051C69,
+		0x033, 0x00000005,
+		0x03F, 0x00051C6C,
+		0x033, 0x00000006,
+		0x03F, 0x00051C8D,
+		0x033, 0x00000007,
+		0x03F, 0x00051CEB,
+		0x033, 0x00000008,
+		0x03F, 0x00051CEE,
+		0x033, 0x00000009,
+		0x03F, 0x00051CF1,
+		0x033, 0x0000000A,
+		0x03F, 0x00051CF4,
+		0x0EE, 0x00000000,
+	0x90001004,	0x00000000,	0x40000000,	0x00000000,
+		0x0EE, 0x00008000,
+		0x033, 0x00000000,
+		0x03F, 0x00051427,
+		0x033, 0x00000001,
+		0x03F, 0x00051446,
+		0x033, 0x00000002,
+		0x03F, 0x00051449,
+		0x033, 0x00000003,
+		0x03F, 0x0005144C,
+		0x033, 0x00000004,
+		0x03F, 0x00051C69,
+		0x033, 0x00000005,
+		0x03F, 0x00051C6C,
+		0x033, 0x00000006,
+		0x03F, 0x00051C8D,
+		0x033, 0x00000007,
+		0x03F, 0x00051CEB,
+		0x033, 0x00000008,
+		0x03F, 0x00051CEE,
+		0x033, 0x00000009,
+		0x03F, 0x00051CF1,
+		0x033, 0x0000000A,
+		0x03F, 0x00051CF4,
+		0x0EE, 0x00000000,
+	0x90000400,	0x00000000,	0x40000000,	0x00000000,
+		0x0EE, 0x00008000,
+		0x033, 0x00000000,
+		0x03F, 0x00051427,
+		0x033, 0x00000001,
+		0x03F, 0x00051446,
+		0x033, 0x00000002,
+		0x03F, 0x00051449,
+		0x033, 0x00000003,
+		0x03F, 0x0005144C,
+		0x033, 0x00000004,
+		0x03F, 0x00051C69,
+		0x033, 0x00000005,
+		0x03F, 0x00051C6C,
+		0x033, 0x00000006,
+		0x03F, 0x00051C8D,
+		0x033, 0x00000007,
+		0x03F, 0x00051CEB,
+		0x033, 0x00000008,
+		0x03F, 0x00051CEE,
+		0x033, 0x00000009,
+		0x03F, 0x00051CF1,
+		0x033, 0x0000000A,
+		0x03F, 0x00051CF4,
+		0x0EE, 0x00000000,
+	0xA0000000,	0x00000000,
+		0x0EE, 0x00008000,
+		0x033, 0x00000000,
+		0x03F, 0x00051427,
+		0x033, 0x00000001,
+		0x03F, 0x00051446,
+		0x033, 0x00000002,
+		0x03F, 0x00051449,
+		0x033, 0x00000003,
+		0x03F, 0x0005144C,
+		0x033, 0x00000004,
+		0x03F, 0x00051C69,
+		0x033, 0x00000005,
+		0x03F, 0x00051C6C,
+		0x033, 0x00000006,
+		0x03F, 0x00051C8D,
+		0x033, 0x00000007,
+		0x03F, 0x00051CEB,
+		0x033, 0x00000008,
+		0x03F, 0x00051CEE,
+		0x033, 0x00000009,
+		0x03F, 0x00051CF1,
+		0x033, 0x0000000A,
+		0x03F, 0x00051CF4,
+		0x0EE, 0x00000000,
+	0xB0000000,	0x00000000,
+	0x80001005,	0x00000000,	0x40000000,	0x00000000,
+		0x0EF, 0x00000010,
+		0x033, 0x00000000,
+		0x008, 0x0009C060,
+		0x033, 0x00000001,
+		0x008, 0x0009C060,
+		0x0EF, 0x00000000,
+	0x90001004,	0x00000000,	0x40000000,	0x00000000,
+		0x0EF, 0x00000010,
+		0x033, 0x00000000,
+		0x008, 0x0009C060,
+		0x033, 0x00000001,
+		0x008, 0x0009C060,
+		0x0EF, 0x00000000,
+	0x90000400,	0x00000000,	0x40000000,	0x00000000,
+		0x0EF, 0x00000010,
+		0x033, 0x00000000,
+		0x008, 0x0009C060,
+		0x033, 0x00000001,
+		0x008, 0x0009C060,
+		0x0EF, 0x00000000,
+	0xA0000000,	0x00000000,
+		0x0EF, 0x00000010,
+		0x033, 0x00000000,
+		0x008, 0x0009C060,
+		0x033, 0x00000001,
+		0x008, 0x0009C060,
+		0x0EF, 0x00000000,
+	0xB0000000,	0x00000000,
+	0x80001005,	0x00000000,	0x40000000,	0x00000000,
+		0x0EF, 0x00080000,
+		0x033, 0x00000024,
+		0x03E, 0x0000003F,
+		0x03F, 0x00060FDE,
+		0x0EF, 0x00000000,
+	0x90001004,	0x00000000,	0x40000000,	0x00000000,
+		0x0EF, 0x00080000,
+		0x033, 0x00000024,
+		0x03E, 0x0000003F,
+		0x03F, 0x00060FDE,
+		0x0EF, 0x00000000,
+	0x90000400,	0x00000000,	0x40000000,	0x00000000,
+		0x0EF, 0x00080000,
+		0x033, 0x00000024,
+		0x03E, 0x0000003F,
+		0x03F, 0x00060FDE,
+		0x0EF, 0x00000000,
+	0xA0000000,	0x00000000,
+		0x0EF, 0x00080000,
+		0x033, 0x00000024,
+		0x03E, 0x0000003F,
+		0x03F, 0x00060FDE,
+		0x0EF, 0x00000000,
+	0xB0000000,	0x00000000,
+	0x80001005,	0x00000000,	0x40000000,	0x00000000,
+		0x0EF, 0x00080000,
+		0x033, 0x00000025,
+		0x03E, 0x00000037,
+		0x03F, 0x0007EFCE,
+		0x0EF, 0x00000000,
+	0x90001004,	0x00000000,	0x40000000,	0x00000000,
+		0x0EF, 0x00080000,
+		0x033, 0x00000025,
+		0x03E, 0x00000037,
+		0x03F, 0x0007EFCE,
+		0x0EF, 0x00000000,
+	0x90000400,	0x00000000,	0x40000000,	0x00000000,
+		0x0EF, 0x00080000,
+		0x033, 0x00000025,
+		0x03E, 0x00000037,
+		0x03F, 0x0007EFCE,
+		0x0EF, 0x00000000,
+	0xA0000000,	0x00000000,
+		0x0EF, 0x00080000,
+		0x033, 0x00000025,
+		0x03E, 0x00000037,
+		0x03F, 0x0007EFCE,
+		0x0EF, 0x00000000,
+	0xB0000000,	0x00000000,
+	0x80001005,	0x00000000,	0x40000000,	0x00000000,
+		0x0EF, 0x00080000,
+		0x033, 0x00000026,
+		0x03E, 0x00000037,
+		0x03F, 0x0005EFCE,
+		0x0EF, 0x00000000,
+	0x90001004,	0x00000000,	0x40000000,	0x00000000,
+		0x0EF, 0x00080000,
+		0x033, 0x00000026,
+		0x03E, 0x00000037,
+		0x03F, 0x0005EFCE,
+		0x0EF, 0x00000000,
+	0x90000400,	0x00000000,	0x40000000,	0x00000000,
+		0x0EF, 0x00080000,
+		0x033, 0x00000026,
+		0x03E, 0x00000037,
+		0x03F, 0x0005EFCE,
+		0x0EF, 0x00000000,
+	0xA0000000,	0x00000000,
+		0x0EF, 0x00080000,
+		0x033, 0x00000026,
+		0x03E, 0x00000037,
+		0x03F, 0x0005EFCE,
+		0x0EF, 0x00000000,
+	0xB0000000,	0x00000000,
+	0x80001005,	0x00000000,	0x40000000,	0x00000000,
+		0x0EE, 0x00001000,
+		0x033, 0x00000004,
+		0x03F, 0x00001EC1,
+		0x0EE, 0x00000000,
+	0x90001004,	0x00000000,	0x40000000,	0x00000000,
+		0x0EE, 0x00001000,
+		0x033, 0x00000004,
+		0x03F, 0x00001EC1,
+		0x0EE, 0x00000000,
+	0x90000400,	0x00000000,	0x40000000,	0x00000000,
+		0x0EE, 0x00001000,
+		0x033, 0x00000004,
+		0x03F, 0x00001EC1,
+		0x0EE, 0x00000000,
+	0xA0000000,	0x00000000,
+		0x0EE, 0x00001000,
+		0x033, 0x00000004,
+		0x03F, 0x00001EC1,
+		0x0EE, 0x00000000,
+	0xB0000000,	0x00000000,
+	0x80001005,	0x00000000,	0x40000000,	0x00000000,
+		0x0EE, 0x00001000,
+		0x033, 0x00000005,
+		0x03F, 0x00001ECF,
+		0x0EE, 0x00000000,
+	0x90001004,	0x00000000,	0x40000000,	0x00000000,
+		0x0EE, 0x00001000,
+		0x033, 0x00000005,
+		0x03F, 0x00001ECF,
+		0x0EE, 0x00000000,
+	0x90000400,	0x00000000,	0x40000000,	0x00000000,
+		0x0EE, 0x00001000,
+		0x033, 0x00000005,
+		0x03F, 0x00001ECF,
+		0x0EE, 0x00000000,
+	0xA0000000,	0x00000000,
+		0x0EE, 0x00001000,
+		0x033, 0x00000005,
+		0x03F, 0x00001ECF,
+		0x0EE, 0x00000000,
+	0xB0000000,	0x00000000,
+	0x80001005,	0x00000000,	0x40000000,	0x00000000,
+		0x0EE, 0x00001000,
+		0x033, 0x00000006,
+		0x03F, 0x00001F9D,
+		0x0EE, 0x00000000,
+	0x90001004,	0x00000000,	0x40000000,	0x00000000,
+		0x0EE, 0x00001000,
+		0x033, 0x00000006,
+		0x03F, 0x00001F9D,
+		0x0EE, 0x00000000,
+	0x90000400,	0x00000000,	0x40000000,	0x00000000,
+		0x0EE, 0x00001000,
+		0x033, 0x00000006,
+		0x03F, 0x00001F9D,
+		0x0EE, 0x00000000,
+	0xA0000000,	0x00000000,
+		0x0EE, 0x00001000,
+		0x033, 0x00000006,
+		0x03F, 0x00001F9D,
+		0x0EE, 0x00000000,
+	0xB0000000,	0x00000000,
+
+};
+
+void
+odm_read_and_config_mp_8821c_radioa(struct dm_struct *dm)
+{
+	u32	i = 0;
+	u8	c_cond;
+	boolean	is_matched = true, is_skipped = false;
+	u32	array_len = sizeof(array_mp_8821c_radioa) / sizeof(u32);
+	u32	*array = array_mp_8821c_radioa;
+
+	u32	v1 = 0, v2 = 0, pre_v1 = 0, pre_v2 = 0;
+
+	PHYDM_DBG(dm, ODM_COMP_INIT, "===> %s\n", __func__);
+
+	while ((i + 1) < array_len) {
+		v1 = array[i];
+		v2 = array[i + 1];
+
+		if (v1 & (BIT(31) | BIT(30))) {/*positive & negative condition*/
+			if (v1 & BIT(31)) {/* positive condition*/
+				c_cond  = (u8)((v1 & (BIT(29) | BIT(28))) >> 28);
+				if (c_cond == COND_ENDIF) {/*end*/
+					is_matched = true;
+					is_skipped = false;
+					PHYDM_DBG(dm, ODM_COMP_INIT, "ENDIF\n");
+				} else if (c_cond == COND_ELSE) { /*else*/
+					is_matched = is_skipped ? false : true;
+					PHYDM_DBG(dm, ODM_COMP_INIT, "ELSE\n");
+				} else {/*if , else if*/
+					pre_v1 = v1;
+					pre_v2 = v2;
+					PHYDM_DBG(dm, ODM_COMP_INIT, "IF or ELSE IF\n");
+				}
+			} else if (v1 & BIT(30)) { /*negative condition*/
+				if (is_skipped == false) {
+					if (check_positive(dm, pre_v1, pre_v2, v1, v2)) {
+						is_matched = true;
+						is_skipped = true;
+					} else {
+						is_matched = false;
+						is_skipped = false;
+					}
+				} else
+					is_matched = false;
+			}
+		} else {
+			if (is_matched)
+				odm_config_rf_radio_a_8821c(dm, v1, v2);
+		}
+		i = i + 2;
+	}
+}
+
+u32
+odm_get_version_mp_8821c_radioa(void)
+{
+		return 49;
+}
+
+/******************************************************************************
+*                           txpowertrack.TXT
+******************************************************************************/
+
+u8 delta_swingidx_mp_5gb_n_txpwrtrk_8821c[][DELTA_SWINGIDX_SIZE] = {
+	{0, 1, 1, 2, 3, 3, 3, 4, 4, 5, 5, 6, 6, 6, 7, 8, 8, 8, 9, 9, 9, 10, 10, 11, 11, 12, 12, 12, 12, 12},
+	{0, 1, 1, 1, 2, 3, 3, 4, 4, 5, 5, 5, 6, 6, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 12, 12, 12, 12, 12},
+	{0, 1, 2, 2, 3, 4, 4, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 9, 10, 10, 11, 11, 12, 12, 12, 12, 12, 12},
+};
+u8 delta_swingidx_mp_5gb_p_txpwrtrk_8821c[][DELTA_SWINGIDX_SIZE] = {
+	{0, 1, 1, 2, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 11, 11, 12, 12, 12, 12, 12, 12, 12},
+	{0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 5, 6, 7, 7, 8, 8, 9, 10, 10, 11, 11, 12, 12, 12, 12, 12, 12, 12, 12},
+	{0, 1, 1, 1, 2, 3, 3, 3, 4, 4, 4, 5, 6, 6, 7, 7, 8, 8, 9, 10, 10, 11, 11, 12, 12, 12, 12, 12, 12, 12},
+};
+u8 delta_swingidx_mp_5ga_n_txpwrtrk_8821c[][DELTA_SWINGIDX_SIZE] = {
+	{0, 1, 1, 2, 3, 3, 3, 4, 4, 5, 5, 6, 6, 6, 7, 8, 8, 8, 9, 9, 9, 10, 10, 11, 11, 12, 12, 12, 12, 12},
+	{0, 1, 1, 1, 2, 3, 3, 4, 4, 5, 5, 5, 6, 6, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 12, 12, 12, 12, 12},
+	{0, 1, 2, 2, 3, 4, 4, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 9, 10, 10, 11, 11, 12, 12, 12, 12, 12, 12},
+};
+u8 delta_swingidx_mp_5ga_p_txpwrtrk_8821c[][DELTA_SWINGIDX_SIZE] = {
+	{0, 1, 1, 2, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 11, 11, 12, 12, 12, 12, 12, 12, 12},
+	{0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 5, 6, 7, 7, 8, 8, 9, 10, 10, 11, 11, 12, 12, 12, 12, 12, 12, 12, 12},
+	{0, 1, 1, 1, 2, 3, 3, 3, 4, 4, 4, 5, 6, 6, 7, 7, 8, 8, 9, 10, 10, 11, 11, 12, 12, 12, 12, 12, 12, 12},
+};
+u8 delta_swingidx_mp_2gb_n_txpwrtrk_8821c[]    = {0, 0, 0, 1, 1, 1, 2, 2, 2, 3, 3, 3, 3, 3, 4, 4, 4, 4, 5, 5, 5, 5, 6, 6, 6, 7, 7, 8, 8, 9};
+u8 delta_swingidx_mp_2gb_p_txpwrtrk_8821c[]    = {0, 1, 1, 1, 1, 2, 2, 2, 3, 3, 3, 3, 4, 4, 5, 5, 5, 5, 6, 6, 6, 7, 7, 7, 8, 8, 9, 9, 9, 9};
+u8 delta_swingidx_mp_2ga_n_txpwrtrk_8821c[]    = {0, 0, 0, 1, 1, 1, 2, 2, 2, 3, 3, 3, 3, 3, 4, 4, 4, 4, 5, 5, 5, 5, 6, 6, 6, 7, 7, 8, 8, 9};
+u8 delta_swingidx_mp_2ga_p_txpwrtrk_8821c[]    = {0, 1, 1, 1, 1, 2, 2, 2, 3, 3, 3, 3, 4, 4, 5, 5, 5, 5, 6, 6, 6, 7, 7, 7, 8, 8, 9, 9, 9, 9};
+u8 delta_swingidx_mp_2g_cck_b_n_txpwrtrk_8821c[] = {0, 0, 1, 1, 1, 1, 2, 2, 2, 2, 3, 3, 3, 3, 4, 4, 4, 5, 5, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 9};
+u8 delta_swingidx_mp_2g_cck_b_p_txpwrtrk_8821c[] = {0, 1, 1, 1, 1, 2, 2, 2, 3, 3, 3, 4, 4, 4, 5, 5, 5, 6, 6, 7, 7, 7, 8, 8, 9, 9, 9, 9, 9, 9};
+u8 delta_swingidx_mp_2g_cck_a_n_txpwrtrk_8821c[] = {0, 0, 1, 1, 1, 1, 2, 2, 2, 2, 3, 3, 3, 3, 4, 4, 4, 5, 5, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 9};
+u8 delta_swingidx_mp_2g_cck_a_p_txpwrtrk_8821c[] = {0, 1, 1, 1, 1, 2, 2, 2, 3, 3, 3, 4, 4, 4, 5, 5, 5, 6, 6, 7, 7, 7, 8, 8, 9, 9, 9, 9, 9, 9};
+
+void
+odm_read_and_config_mp_8821c_txpowertrack(struct dm_struct *dm)
+{
+	struct dm_rf_calibration_struct  *cali_info = &dm->rf_calibrate_info;
+
+	PHYDM_DBG(dm, ODM_COMP_INIT, "===> ODM_ReadAndConfig_MP_mp_8821c\n");
+
+
+	odm_move_memory(dm, cali_info->delta_swing_table_idx_2ga_p, delta_swingidx_mp_2ga_p_txpwrtrk_8821c, DELTA_SWINGIDX_SIZE);
+	odm_move_memory(dm, cali_info->delta_swing_table_idx_2ga_n, delta_swingidx_mp_2ga_n_txpwrtrk_8821c, DELTA_SWINGIDX_SIZE);
+	odm_move_memory(dm, cali_info->delta_swing_table_idx_2gb_p, delta_swingidx_mp_2gb_p_txpwrtrk_8821c, DELTA_SWINGIDX_SIZE);
+	odm_move_memory(dm, cali_info->delta_swing_table_idx_2gb_n, delta_swingidx_mp_2gb_n_txpwrtrk_8821c, DELTA_SWINGIDX_SIZE);
+
+	odm_move_memory(dm, cali_info->delta_swing_table_idx_2g_cck_a_p, delta_swingidx_mp_2g_cck_a_p_txpwrtrk_8821c, DELTA_SWINGIDX_SIZE);
+	odm_move_memory(dm, cali_info->delta_swing_table_idx_2g_cck_a_n, delta_swingidx_mp_2g_cck_a_n_txpwrtrk_8821c, DELTA_SWINGIDX_SIZE);
+	odm_move_memory(dm, cali_info->delta_swing_table_idx_2g_cck_b_p, delta_swingidx_mp_2g_cck_b_p_txpwrtrk_8821c, DELTA_SWINGIDX_SIZE);
+	odm_move_memory(dm, cali_info->delta_swing_table_idx_2g_cck_b_n, delta_swingidx_mp_2g_cck_b_n_txpwrtrk_8821c, DELTA_SWINGIDX_SIZE);
+
+	odm_move_memory(dm, cali_info->delta_swing_table_idx_5ga_p, delta_swingidx_mp_5ga_p_txpwrtrk_8821c, DELTA_SWINGIDX_SIZE * 3);
+	odm_move_memory(dm, cali_info->delta_swing_table_idx_5ga_n, delta_swingidx_mp_5ga_n_txpwrtrk_8821c, DELTA_SWINGIDX_SIZE * 3);
+	odm_move_memory(dm, cali_info->delta_swing_table_idx_5gb_p, delta_swingidx_mp_5gb_p_txpwrtrk_8821c, DELTA_SWINGIDX_SIZE * 3);
+	odm_move_memory(dm, cali_info->delta_swing_table_idx_5gb_n, delta_swingidx_mp_5gb_n_txpwrtrk_8821c, DELTA_SWINGIDX_SIZE * 3);
+}
+
+/******************************************************************************
+*                           txpowertrack_type0x20.TXT
+******************************************************************************/
+
+u8 delta_swingidx_mp_5gb_n_txpwrtrk_type0x20_8821c[][DELTA_SWINGIDX_SIZE] = {
+	{0, 1, 1, 2, 3, 3, 3, 4, 4, 5, 5, 6, 6, 6, 7, 8, 8, 8, 9, 9, 9, 10, 10, 11, 11, 12, 12, 12, 12, 12},
+	{0, 1, 1, 1, 2, 3, 3, 4, 4, 5, 5, 5, 6, 6, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 12, 12, 12, 12, 12},
+	{0, 1, 2, 2, 3, 4, 4, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 9, 10, 10, 11, 11, 12, 12, 12, 12, 12, 12},
+};
+u8 delta_swingidx_mp_5gb_p_txpwrtrk_type0x20_8821c[][DELTA_SWINGIDX_SIZE] = {
+	{0, 1, 1, 2, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 11, 11, 12, 12, 12, 12, 12, 12, 12},
+	{0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 5, 6, 7, 7, 8, 8, 9, 10, 10, 11, 11, 12, 12, 12, 12, 12, 12, 12, 12},
+	{0, 1, 1, 1, 2, 3, 3, 3, 4, 4, 4, 5, 6, 6, 7, 7, 8, 8, 9, 10, 10, 11, 11, 12, 12, 12, 12, 12, 12, 12},
+};
+u8 delta_swingidx_mp_5ga_n_txpwrtrk_type0x20_8821c[][DELTA_SWINGIDX_SIZE] = {
+	{0, 0, 1, 1, 2, 3, 3, 4, 4, 5, 5, 6, 6, 6, 7, 8, 8, 8, 9, 9, 9, 10, 10, 11, 11, 12, 12, 12, 12, 12},
+	{0, 0, 1, 1, 2, 2, 3, 3, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 12, 12, 12, 12, 12},
+	{0, 1, 2, 3, 4, 4, 4, 5, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 9, 10, 10, 11, 11, 12, 12, 12, 12, 12, 12, 12},
+};
+u8 delta_swingidx_mp_5ga_p_txpwrtrk_type0x20_8821c[][DELTA_SWINGIDX_SIZE] = {
+	{1, 1, 2, 2, 2, 3, 3, 4, 5, 5, 5, 6, 6, 7, 8, 8, 8, 9, 9, 10, 11, 11, 12, 12, 12, 12, 12, 12, 12, 12},
+	{0, 1, 2, 2, 3, 4, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 8, 9, 10, 10, 11, 11, 12, 12, 12, 12, 12, 12, 12, 12},
+	{0, 1, 1, 1, 2, 3, 3, 3, 4, 4, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 12, 12, 12, 12, 12},
+};
+u8 delta_swingidx_mp_2gb_n_txpwrtrk_type0x20_8821c[]    = {0, 0, 0, 1, 1, 1, 2, 2, 2, 3, 3, 3, 3, 3, 4, 4, 4, 4, 5, 5, 5, 5, 6, 6, 6, 7, 7, 8, 8, 9};
+u8 delta_swingidx_mp_2gb_p_txpwrtrk_type0x20_8821c[]    = {0, 1, 1, 1, 1, 2, 2, 2, 3, 3, 3, 3, 4, 4, 5, 5, 5, 5, 6, 6, 6, 7, 7, 7, 8, 8, 9, 9, 9, 9};
+u8 delta_swingidx_mp_2ga_n_txpwrtrk_type0x20_8821c[]    = {0, 0, 0, 1, 1, 1, 2, 2, 2, 3, 3, 3, 3, 3, 4, 4, 4, 4, 5, 5, 5, 5, 6, 6, 6, 7, 7, 8, 8, 9};
+u8 delta_swingidx_mp_2ga_p_txpwrtrk_type0x20_8821c[]    = {0, 1, 1, 1, 1, 2, 2, 2, 3, 3, 3, 3, 4, 4, 5, 5, 5, 5, 6, 6, 6, 7, 7, 7, 8, 8, 9, 9, 9, 9};
+u8 delta_swingidx_mp_2g_cck_b_n_txpwrtrk_type0x20_8821c[] = {0, 0, 1, 1, 1, 1, 2, 2, 2, 2, 3, 3, 3, 3, 4, 4, 4, 5, 5, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 9};
+u8 delta_swingidx_mp_2g_cck_b_p_txpwrtrk_type0x20_8821c[] = {0, 1, 1, 1, 1, 2, 2, 2, 3, 3, 3, 4, 4, 4, 5, 5, 5, 6, 6, 7, 7, 7, 8, 8, 9, 9, 9, 9, 9, 9};
+u8 delta_swingidx_mp_2g_cck_a_n_txpwrtrk_type0x20_8821c[] = {0, 0, 1, 1, 1, 1, 2, 2, 2, 2, 3, 3, 3, 3, 4, 4, 4, 5, 5, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 9};
+u8 delta_swingidx_mp_2g_cck_a_p_txpwrtrk_type0x20_8821c[] = {0, 1, 1, 1, 1, 2, 2, 2, 3, 3, 3, 4, 4, 4, 5, 5, 5, 6, 6, 7, 7, 7, 8, 8, 9, 9, 9, 9, 9, 9};
+
+void
+odm_read_and_config_mp_8821c_txpowertrack_type0x20(struct dm_struct *dm)
+{
+	struct dm_rf_calibration_struct  *cali_info = &dm->rf_calibrate_info;
+
+	PHYDM_DBG(dm, ODM_COMP_INIT, "===> ODM_ReadAndConfig_MP_mp_8821c\n");
+
+
+	odm_move_memory(dm, cali_info->delta_swing_table_idx_2ga_p, delta_swingidx_mp_2ga_p_txpwrtrk_type0x20_8821c, DELTA_SWINGIDX_SIZE);
+	odm_move_memory(dm, cali_info->delta_swing_table_idx_2ga_n, delta_swingidx_mp_2ga_n_txpwrtrk_type0x20_8821c, DELTA_SWINGIDX_SIZE);
+	odm_move_memory(dm, cali_info->delta_swing_table_idx_2gb_p, delta_swingidx_mp_2gb_p_txpwrtrk_type0x20_8821c, DELTA_SWINGIDX_SIZE);
+	odm_move_memory(dm, cali_info->delta_swing_table_idx_2gb_n, delta_swingidx_mp_2gb_n_txpwrtrk_type0x20_8821c, DELTA_SWINGIDX_SIZE);
+
+	odm_move_memory(dm, cali_info->delta_swing_table_idx_2g_cck_a_p, delta_swingidx_mp_2g_cck_a_p_txpwrtrk_type0x20_8821c, DELTA_SWINGIDX_SIZE);
+	odm_move_memory(dm, cali_info->delta_swing_table_idx_2g_cck_a_n, delta_swingidx_mp_2g_cck_a_n_txpwrtrk_type0x20_8821c, DELTA_SWINGIDX_SIZE);
+	odm_move_memory(dm, cali_info->delta_swing_table_idx_2g_cck_b_p, delta_swingidx_mp_2g_cck_b_p_txpwrtrk_type0x20_8821c, DELTA_SWINGIDX_SIZE);
+	odm_move_memory(dm, cali_info->delta_swing_table_idx_2g_cck_b_n, delta_swingidx_mp_2g_cck_b_n_txpwrtrk_type0x20_8821c, DELTA_SWINGIDX_SIZE);
+
+	odm_move_memory(dm, cali_info->delta_swing_table_idx_5ga_p, delta_swingidx_mp_5ga_p_txpwrtrk_type0x20_8821c, DELTA_SWINGIDX_SIZE * 3);
+	odm_move_memory(dm, cali_info->delta_swing_table_idx_5ga_n, delta_swingidx_mp_5ga_n_txpwrtrk_type0x20_8821c, DELTA_SWINGIDX_SIZE * 3);
+	odm_move_memory(dm, cali_info->delta_swing_table_idx_5gb_p, delta_swingidx_mp_5gb_p_txpwrtrk_type0x20_8821c, DELTA_SWINGIDX_SIZE * 3);
+	odm_move_memory(dm, cali_info->delta_swing_table_idx_5gb_n, delta_swingidx_mp_5gb_n_txpwrtrk_type0x20_8821c, DELTA_SWINGIDX_SIZE * 3);
+}
+
+/******************************************************************************
+*                           txpowertrack_type0x28.TXT
+******************************************************************************/
+
+u8 delta_swingidx_mp_5gb_n_txpwrtrk_type0x28_8821c[][DELTA_SWINGIDX_SIZE] = {
+	{0, 1, 1, 2, 3, 3, 3, 4, 4, 5, 5, 6, 6, 6, 7, 8, 8, 8, 9, 9, 9, 10, 10, 11, 11, 12, 12, 12, 12, 12},
+	{0, 1, 1, 1, 2, 3, 3, 4, 4, 5, 5, 5, 6, 6, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 12, 12, 12, 12, 12},
+	{0, 1, 2, 2, 3, 4, 4, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 9, 10, 10, 11, 11, 12, 12, 12, 12, 12, 12},
+};
+u8 delta_swingidx_mp_5gb_p_txpwrtrk_type0x28_8821c[][DELTA_SWINGIDX_SIZE] = {
+	{0, 1, 1, 2, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 11, 11, 12, 12, 12, 12, 12, 12, 12},
+	{0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 5, 6, 7, 7, 8, 8, 9, 10, 10, 11, 11, 12, 12, 12, 12, 12, 12, 12, 12},
+	{0, 1, 1, 1, 2, 3, 3, 3, 4, 4, 4, 5, 6, 6, 7, 7, 8, 8, 9, 10, 10, 11, 11, 12, 12, 12, 12, 12, 12, 12},
+};
+u8 delta_swingidx_mp_5ga_n_txpwrtrk_type0x28_8821c[][DELTA_SWINGIDX_SIZE] = {
+	{0, 1, 3, 3, 4, 5, 5, 6, 7, 8, 8, 9, 10, 10, 11, 12, 12, 12, 14, 15, 15, 16, 16, 17, 18, 18, 18, 18, 18, 18},
+	{0, 1, 2, 3, 4, 4, 5, 7, 7, 8, 8, 9, 10, 10, 11, 12, 12, 13, 14, 14, 15, 16, 16, 17, 18, 18, 18, 18, 18, 18},
+	{0, 1, 2, 3, 4, 6, 6, 6, 6, 7, 8, 9, 10, 11, 11, 12, 12, 13, 14, 14, 15, 16, 16, 17, 18, 18, 18, 18, 18, 18},
+};
+u8 delta_swingidx_mp_5ga_p_txpwrtrk_type0x28_8821c[][DELTA_SWINGIDX_SIZE] = {
+	{0, 1, 2, 3, 3, 3, 4, 5, 7, 7, 8, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 16, 16, 17, 17, 17, 17, 17, 17, 17},
+	{0, 1, 2, 3, 3, 4, 4, 5, 6, 7, 8, 9, 10, 10, 11, 13, 13, 14, 15, 15, 16, 16, 17, 17, 17, 17, 17, 17, 17, 17},
+	{0, 1, 2, 2, 3, 4, 4, 5, 6, 7, 7, 8, 8, 9, 10, 10, 11, 12, 13, 14, 14, 14, 14, 15, 16, 16, 16, 16, 16, 16},
+};
+u8 delta_swingidx_mp_2gb_n_txpwrtrk_type0x28_8821c[]    = {0, 0, 0, 1, 1, 1, 2, 2, 2, 3, 3, 3, 3, 3, 4, 4, 4, 4, 5, 5, 5, 5, 6, 6, 6, 7, 7, 8, 8, 9};
+u8 delta_swingidx_mp_2gb_p_txpwrtrk_type0x28_8821c[]    = {0, 1, 1, 1, 1, 2, 2, 2, 3, 3, 3, 3, 4, 4, 5, 5, 5, 5, 6, 6, 6, 7, 7, 7, 8, 8, 9, 9, 9, 9};
+u8 delta_swingidx_mp_2ga_n_txpwrtrk_type0x28_8821c[]    = {0, 0, 0, 1, 1, 1, 2, 2, 2, 3, 3, 3, 3, 3, 4, 4, 4, 4, 5, 5, 5, 5, 6, 6, 6, 7, 7, 8, 8, 9};
+u8 delta_swingidx_mp_2ga_p_txpwrtrk_type0x28_8821c[]    = {0, 1, 1, 1, 1, 2, 2, 2, 3, 3, 3, 3, 4, 4, 5, 5, 5, 5, 6, 6, 6, 7, 7, 7, 8, 8, 9, 9, 9, 9};
+u8 delta_swingidx_mp_2g_cck_b_n_txpwrtrk_type0x28_8821c[] = {0, 0, 1, 1, 1, 1, 2, 2, 2, 2, 3, 3, 3, 3, 4, 4, 4, 5, 5, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 9};
+u8 delta_swingidx_mp_2g_cck_b_p_txpwrtrk_type0x28_8821c[] = {0, 1, 1, 1, 1, 2, 2, 2, 3, 3, 3, 4, 4, 4, 5, 5, 5, 6, 6, 7, 7, 7, 8, 8, 9, 9, 9, 9, 9, 9};
+u8 delta_swingidx_mp_2g_cck_a_n_txpwrtrk_type0x28_8821c[] = {0, 0, 1, 1, 1, 1, 2, 2, 2, 2, 3, 3, 3, 3, 4, 4, 4, 5, 5, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 9};
+u8 delta_swingidx_mp_2g_cck_a_p_txpwrtrk_type0x28_8821c[] = {0, 1, 1, 1, 1, 2, 2, 2, 3, 3, 3, 4, 4, 4, 5, 5, 5, 6, 6, 7, 7, 7, 8, 8, 9, 9, 9, 9, 9, 9};
+
+void
+odm_read_and_config_mp_8821c_txpowertrack_type0x28(struct dm_struct *dm)
+{
+	struct dm_rf_calibration_struct  *cali_info = &dm->rf_calibrate_info;
+
+	PHYDM_DBG(dm, ODM_COMP_INIT, "===> ODM_ReadAndConfig_MP_mp_8821c\n");
+
+
+	odm_move_memory(dm, cali_info->delta_swing_table_idx_2ga_p, delta_swingidx_mp_2ga_p_txpwrtrk_type0x28_8821c, DELTA_SWINGIDX_SIZE);
+	odm_move_memory(dm, cali_info->delta_swing_table_idx_2ga_n, delta_swingidx_mp_2ga_n_txpwrtrk_type0x28_8821c, DELTA_SWINGIDX_SIZE);
+	odm_move_memory(dm, cali_info->delta_swing_table_idx_2gb_p, delta_swingidx_mp_2gb_p_txpwrtrk_type0x28_8821c, DELTA_SWINGIDX_SIZE);
+	odm_move_memory(dm, cali_info->delta_swing_table_idx_2gb_n, delta_swingidx_mp_2gb_n_txpwrtrk_type0x28_8821c, DELTA_SWINGIDX_SIZE);
+
+	odm_move_memory(dm, cali_info->delta_swing_table_idx_2g_cck_a_p, delta_swingidx_mp_2g_cck_a_p_txpwrtrk_type0x28_8821c, DELTA_SWINGIDX_SIZE);
+	odm_move_memory(dm, cali_info->delta_swing_table_idx_2g_cck_a_n, delta_swingidx_mp_2g_cck_a_n_txpwrtrk_type0x28_8821c, DELTA_SWINGIDX_SIZE);
+	odm_move_memory(dm, cali_info->delta_swing_table_idx_2g_cck_b_p, delta_swingidx_mp_2g_cck_b_p_txpwrtrk_type0x28_8821c, DELTA_SWINGIDX_SIZE);
+	odm_move_memory(dm, cali_info->delta_swing_table_idx_2g_cck_b_n, delta_swingidx_mp_2g_cck_b_n_txpwrtrk_type0x28_8821c, DELTA_SWINGIDX_SIZE);
+
+	odm_move_memory(dm, cali_info->delta_swing_table_idx_5ga_p, delta_swingidx_mp_5ga_p_txpwrtrk_type0x28_8821c, DELTA_SWINGIDX_SIZE * 3);
+	odm_move_memory(dm, cali_info->delta_swing_table_idx_5ga_n, delta_swingidx_mp_5ga_n_txpwrtrk_type0x28_8821c, DELTA_SWINGIDX_SIZE * 3);
+	odm_move_memory(dm, cali_info->delta_swing_table_idx_5gb_p, delta_swingidx_mp_5gb_p_txpwrtrk_type0x28_8821c, DELTA_SWINGIDX_SIZE * 3);
+	odm_move_memory(dm, cali_info->delta_swing_table_idx_5gb_n, delta_swingidx_mp_5gb_n_txpwrtrk_type0x28_8821c, DELTA_SWINGIDX_SIZE * 3);
+}
+
+/******************************************************************************
+*                           txpwr_lmt.TXT
+******************************************************************************/
+
+const char *array_mp_8821c_txpwr_lmt[] = {
+	"FCC", "2.4G", "20M", "CCK", "1T", "01", "30",
+	"ETSI", "2.4G", "20M", "CCK", "1T", "01", "30",
+	"MKK", "2.4G", "20M", "CCK", "1T", "01", "34",
+	"IC", "2.4G", "20M", "CCK", "1T", "01", "30",
+	"KCC", "2.4G", "20M", "CCK", "1T", "01", "34",
+	"ACMA", "2.4G", "20M", "CCK", "1T", "01", "30",
+	"CHILE", "2.4G", "20M", "CCK", "1T", "01", "30",
+	"FCC", "2.4G", "20M", "CCK", "1T", "02", "32",
+	"ETSI", "2.4G", "20M", "CCK", "1T", "02", "30",
+	"MKK", "2.4G", "20M", "CCK", "1T", "02", "34",
+	"IC", "2.4G", "20M", "CCK", "1T", "02", "32",
+	"KCC", "2.4G", "20M", "CCK", "1T", "02", "34",
+	"ACMA", "2.4G", "20M", "CCK", "1T", "02", "30",
+	"CHILE", "2.4G", "20M", "CCK", "1T", "02", "32",
+	"FCC", "2.4G", "20M", "CCK", "1T", "03", "32",
+	"ETSI", "2.4G", "20M", "CCK", "1T", "03", "30",
+	"MKK", "2.4G", "20M", "CCK", "1T", "03", "34",
+	"IC", "2.4G", "20M", "CCK", "1T", "03", "32",
+	"KCC", "2.4G", "20M", "CCK", "1T", "03", "34",
+	"ACMA", "2.4G", "20M", "CCK", "1T", "03", "30",
+	"CHILE", "2.4G", "20M", "CCK", "1T", "03", "32",
+	"FCC", "2.4G", "20M", "CCK", "1T", "04", "32",
+	"ETSI", "2.4G", "20M", "CCK", "1T", "04", "30",
+	"MKK", "2.4G", "20M", "CCK", "1T", "04", "34",
+	"IC", "2.4G", "20M", "CCK", "1T", "04", "32",
+	"KCC", "2.4G", "20M", "CCK", "1T", "04", "34",
+	"ACMA", "2.4G", "20M", "CCK", "1T", "04", "30",
+	"CHILE", "2.4G", "20M", "CCK", "1T", "04", "32",
+	"FCC", "2.4G", "20M", "CCK", "1T", "05", "32",
+	"ETSI", "2.4G", "20M", "CCK", "1T", "05", "30",
+	"MKK", "2.4G", "20M", "CCK", "1T", "05", "34",
+	"IC", "2.4G", "20M", "CCK", "1T", "05", "32",
+	"KCC", "2.4G", "20M", "CCK", "1T", "05", "34",
+	"ACMA", "2.4G", "20M", "CCK", "1T", "05", "30",
+	"CHILE", "2.4G", "20M", "CCK", "1T", "05", "32",
+	"FCC", "2.4G", "20M", "CCK", "1T", "06", "32",
+	"ETSI", "2.4G", "20M", "CCK", "1T", "06", "30",
+	"MKK", "2.4G", "20M", "CCK", "1T", "06", "34",
+	"IC", "2.4G", "20M", "CCK", "1T", "06", "32",
+	"KCC", "2.4G", "20M", "CCK", "1T", "06", "34",
+	"ACMA", "2.4G", "20M", "CCK", "1T", "06", "30",
+	"CHILE", "2.4G", "20M", "CCK", "1T", "06", "32",
+	"FCC", "2.4G", "20M", "CCK", "1T", "07", "32",
+	"ETSI", "2.4G", "20M", "CCK", "1T", "07", "30",
+	"MKK", "2.4G", "20M", "CCK", "1T", "07", "34",
+	"IC", "2.4G", "20M", "CCK", "1T", "07", "32",
+	"KCC", "2.4G", "20M", "CCK", "1T", "07", "34",
+	"ACMA", "2.4G", "20M", "CCK", "1T", "07", "30",
+	"CHILE", "2.4G", "20M", "CCK", "1T", "07", "32",
+	"FCC", "2.4G", "20M", "CCK", "1T", "08", "32",
+	"ETSI", "2.4G", "20M", "CCK", "1T", "08", "30",
+	"MKK", "2.4G", "20M", "CCK", "1T", "08", "34",
+	"IC", "2.4G", "20M", "CCK", "1T", "08", "32",
+	"KCC", "2.4G", "20M", "CCK", "1T", "08", "34",
+	"ACMA", "2.4G", "20M", "CCK", "1T", "08", "30",
+	"CHILE", "2.4G", "20M", "CCK", "1T", "08", "32",
+	"FCC", "2.4G", "20M", "CCK", "1T", "09", "32",
+	"ETSI", "2.4G", "20M", "CCK", "1T", "09", "30",
+	"MKK", "2.4G", "20M", "CCK", "1T", "09", "34",
+	"IC", "2.4G", "20M", "CCK", "1T", "09", "32",
+	"KCC", "2.4G", "20M", "CCK", "1T", "09", "34",
+	"ACMA", "2.4G", "20M", "CCK", "1T", "09", "30",
+	"CHILE", "2.4G", "20M", "CCK", "1T", "09", "32",
+	"FCC", "2.4G", "20M", "CCK", "1T", "10", "32",
+	"ETSI", "2.4G", "20M", "CCK", "1T", "10", "30",
+	"MKK", "2.4G", "20M", "CCK", "1T", "10", "34",
+	"IC", "2.4G", "20M", "CCK", "1T", "10", "32",
+	"KCC", "2.4G", "20M", "CCK", "1T", "10", "34",
+	"ACMA", "2.4G", "20M", "CCK", "1T", "10", "30",
+	"CHILE", "2.4G", "20M", "CCK", "1T", "10", "32",
+	"FCC", "2.4G", "20M", "CCK", "1T", "11", "32",
+	"ETSI", "2.4G", "20M", "CCK", "1T", "11", "30",
+	"MKK", "2.4G", "20M", "CCK", "1T", "11", "34",
+	"IC", "2.4G", "20M", "CCK", "1T", "11", "32",
+	"KCC", "2.4G", "20M", "CCK", "1T", "11", "34",
+	"ACMA", "2.4G", "20M", "CCK", "1T", "11", "30",
+	"CHILE", "2.4G", "20M", "CCK", "1T", "11", "32",
+	"FCC", "2.4G", "20M", "CCK", "1T", "12", "24",
+	"ETSI", "2.4G", "20M", "CCK", "1T", "12", "30",
+	"MKK", "2.4G", "20M", "CCK", "1T", "12", "34",
+	"IC", "2.4G", "20M", "CCK", "1T", "12", "24",
+	"KCC", "2.4G", "20M", "CCK", "1T", "12", "34",
+	"ACMA", "2.4G", "20M", "CCK", "1T", "12", "30",
+	"CHILE", "2.4G", "20M", "CCK", "1T", "12", "24",
+	"FCC", "2.4G", "20M", "CCK", "1T", "13", "16",
+	"ETSI", "2.4G", "20M", "CCK", "1T", "13", "30",
+	"MKK", "2.4G", "20M", "CCK", "1T", "13", "34",
+	"IC", "2.4G", "20M", "CCK", "1T", "13", "16",
+	"KCC", "2.4G", "20M", "CCK", "1T", "13", "34",
+	"ACMA", "2.4G", "20M", "CCK", "1T", "13", "30",
+	"CHILE", "2.4G", "20M", "CCK", "1T", "13", "16",
+	"FCC", "2.4G", "20M", "CCK", "1T", "14", "63",
+	"ETSI", "2.4G", "20M", "CCK", "1T", "14", "63",
+	"MKK", "2.4G", "20M", "CCK", "1T", "14", "34",
+	"IC", "2.4G", "20M", "CCK", "1T", "14", "63",
+	"KCC", "2.4G", "20M", "CCK", "1T", "14", "63",
+	"ACMA", "2.4G", "20M", "CCK", "1T", "14", "63",
+	"CHILE", "2.4G", "20M", "CCK", "1T", "14", "63",
+	"FCC", "2.4G", "20M", "OFDM", "1T", "01", "30",
+	"ETSI", "2.4G", "20M", "OFDM", "1T", "01", "30",
+	"MKK", "2.4G", "20M", "OFDM", "1T", "01", "34",
+	"IC", "2.4G", "20M", "OFDM", "1T", "01", "30",
+	"KCC", "2.4G", "20M", "OFDM", "1T", "01", "32",
+	"ACMA", "2.4G", "20M", "OFDM", "1T", "01", "30",
+	"CHILE", "2.4G", "20M", "OFDM", "1T", "01", "30",
+	"FCC", "2.4G", "20M", "OFDM", "1T", "02", "32",
+	"ETSI", "2.4G", "20M", "OFDM", "1T", "02", "30",
+	"MKK", "2.4G", "20M", "OFDM", "1T", "02", "34",
+	"IC", "2.4G", "20M", "OFDM", "1T", "02", "32",
+	"KCC", "2.4G", "20M", "OFDM", "1T", "02", "34",
+	"ACMA", "2.4G", "20M", "OFDM", "1T", "02", "30",
+	"CHILE", "2.4G", "20M", "OFDM", "1T", "02", "32",
+	"FCC", "2.4G", "20M", "OFDM", "1T", "03", "34",
+	"ETSI", "2.4G", "20M", "OFDM", "1T", "03", "30",
+	"MKK", "2.4G", "20M", "OFDM", "1T", "03", "34",
+	"IC", "2.4G", "20M", "OFDM", "1T", "03", "34",
+	"KCC", "2.4G", "20M", "OFDM", "1T", "03", "34",
+	"ACMA", "2.4G", "20M", "OFDM", "1T", "03", "30",
+	"CHILE", "2.4G", "20M", "OFDM", "1T", "03", "34",
+	"FCC", "2.4G", "20M", "OFDM", "1T", "04", "34",
+	"ETSI", "2.4G", "20M", "OFDM", "1T", "04", "30",
+	"MKK", "2.4G", "20M", "OFDM", "1T", "04", "34",
+	"IC", "2.4G", "20M", "OFDM", "1T", "04", "34",
+	"KCC", "2.4G", "20M", "OFDM", "1T", "04", "34",
+	"ACMA", "2.4G", "20M", "OFDM", "1T", "04", "30",
+	"CHILE", "2.4G", "20M", "OFDM", "1T", "04", "34",
+	"FCC", "2.4G", "20M", "OFDM", "1T", "05", "34",
+	"ETSI", "2.4G", "20M", "OFDM", "1T", "05", "30",
+	"MKK", "2.4G", "20M", "OFDM", "1T", "05", "34",
+	"IC", "2.4G", "20M", "OFDM", "1T", "05", "34",
+	"KCC", "2.4G", "20M", "OFDM", "1T", "05", "34",
+	"ACMA", "2.4G", "20M", "OFDM", "1T", "05", "30",
+	"CHILE", "2.4G", "20M", "OFDM", "1T", "05", "34",
+	"FCC", "2.4G", "20M", "OFDM", "1T", "06", "34",
+	"ETSI", "2.4G", "20M", "OFDM", "1T", "06", "30",
+	"MKK", "2.4G", "20M", "OFDM", "1T", "06", "34",
+	"IC", "2.4G", "20M", "OFDM", "1T", "06", "34",
+	"KCC", "2.4G", "20M", "OFDM", "1T", "06", "34",
+	"ACMA", "2.4G", "20M", "OFDM", "1T", "06", "30",
+	"CHILE", "2.4G", "20M", "OFDM", "1T", "06", "34",
+	"FCC", "2.4G", "20M", "OFDM", "1T", "07", "34",
+	"ETSI", "2.4G", "20M", "OFDM", "1T", "07", "30",
+	"MKK", "2.4G", "20M", "OFDM", "1T", "07", "34",
+	"IC", "2.4G", "20M", "OFDM", "1T", "07", "34",
+	"KCC", "2.4G", "20M", "OFDM", "1T", "07", "34",
+	"ACMA", "2.4G", "20M", "OFDM", "1T", "07", "30",
+	"CHILE", "2.4G", "20M", "OFDM", "1T", "07", "34",
+	"FCC", "2.4G", "20M", "OFDM", "1T", "08", "34",
+	"ETSI", "2.4G", "20M", "OFDM", "1T", "08", "30",
+	"MKK", "2.4G", "20M", "OFDM", "1T", "08", "34",
+	"IC", "2.4G", "20M", "OFDM", "1T", "08", "34",
+	"KCC", "2.4G", "20M", "OFDM", "1T", "08", "34",
+	"ACMA", "2.4G", "20M", "OFDM", "1T", "08", "30",
+	"CHILE", "2.4G", "20M", "OFDM", "1T", "08", "34",
+	"FCC", "2.4G", "20M", "OFDM", "1T", "09", "34",
+	"ETSI", "2.4G", "20M", "OFDM", "1T", "09", "30",
+	"MKK", "2.4G", "20M", "OFDM", "1T", "09", "34",
+	"IC", "2.4G", "20M", "OFDM", "1T", "09", "34",
+	"KCC", "2.4G", "20M", "OFDM", "1T", "09", "34",
+	"ACMA", "2.4G", "20M", "OFDM", "1T", "09", "30",
+	"CHILE", "2.4G", "20M", "OFDM", "1T", "09", "34",
+	"FCC", "2.4G", "20M", "OFDM", "1T", "10", "32",
+	"ETSI", "2.4G", "20M", "OFDM", "1T", "10", "30",
+	"MKK", "2.4G", "20M", "OFDM", "1T", "10", "34",
+	"IC", "2.4G", "20M", "OFDM", "1T", "10", "32",
+	"KCC", "2.4G", "20M", "OFDM", "1T", "10", "34",
+	"ACMA", "2.4G", "20M", "OFDM", "1T", "10", "30",
+	"CHILE", "2.4G", "20M", "OFDM", "1T", "10", "32",
+	"FCC", "2.4G", "20M", "OFDM", "1T", "11", "30",
+	"ETSI", "2.4G", "20M", "OFDM", "1T", "11", "30",
+	"MKK", "2.4G", "20M", "OFDM", "1T", "11", "34",
+	"IC", "2.4G", "20M", "OFDM", "1T", "11", "30",
+	"KCC", "2.4G", "20M", "OFDM", "1T", "11", "34",
+	"ACMA", "2.4G", "20M", "OFDM", "1T", "11", "30",
+	"CHILE", "2.4G", "20M", "OFDM", "1T", "11", "30",
+	"FCC", "2.4G", "20M", "OFDM", "1T", "12", "28",
+	"ETSI", "2.4G", "20M", "OFDM", "1T", "12", "30",
+	"MKK", "2.4G", "20M", "OFDM", "1T", "12", "34",
+	"IC", "2.4G", "20M", "OFDM", "1T", "12", "28",
+	"KCC", "2.4G", "20M", "OFDM", "1T", "12", "34",
+	"ACMA", "2.4G", "20M", "OFDM", "1T", "12", "30",
+	"CHILE", "2.4G", "20M", "OFDM", "1T", "12", "28",
+	"FCC", "2.4G", "20M", "OFDM", "1T", "13", "16",
+	"ETSI", "2.4G", "20M", "OFDM", "1T", "13", "30",
+	"MKK", "2.4G", "20M", "OFDM", "1T", "13", "34",
+	"IC", "2.4G", "20M", "OFDM", "1T", "13", "16",
+	"KCC", "2.4G", "20M", "OFDM", "1T", "13", "32",
+	"ACMA", "2.4G", "20M", "OFDM", "1T", "13", "30",
+	"CHILE", "2.4G", "20M", "OFDM", "1T", "13", "16",
+	"FCC", "2.4G", "20M", "OFDM", "1T", "14", "63",
+	"ETSI", "2.4G", "20M", "OFDM", "1T", "14", "63",
+	"MKK", "2.4G", "20M", "OFDM", "1T", "14", "63",
+	"IC", "2.4G", "20M", "OFDM", "1T", "14", "63",
+	"KCC", "2.4G", "20M", "OFDM", "1T", "14", "63",
+	"ACMA", "2.4G", "20M", "OFDM", "1T", "14", "63",
+	"CHILE", "2.4G", "20M", "OFDM", "1T", "14", "63",
+	"FCC", "2.4G", "20M", "HT", "1T", "01", "26",
+	"ETSI", "2.4G", "20M", "HT", "1T", "01", "30",
+	"MKK", "2.4G", "20M", "HT", "1T", "01", "34",
+	"IC", "2.4G", "20M", "HT", "1T", "01", "26",
+	"KCC", "2.4G", "20M", "HT", "1T", "01", "32",
+	"ACMA", "2.4G", "20M", "HT", "1T", "01", "30",
+	"CHILE", "2.4G", "20M", "HT", "1T", "01", "26",
+	"FCC", "2.4G", "20M", "HT", "1T", "02", "30",
+	"ETSI", "2.4G", "20M", "HT", "1T", "02", "30",
+	"MKK", "2.4G", "20M", "HT", "1T", "02", "34",
+	"IC", "2.4G", "20M", "HT", "1T", "02", "30",
+	"KCC", "2.4G", "20M", "HT", "1T", "02", "34",
+	"ACMA", "2.4G", "20M", "HT", "1T", "02", "30",
+	"CHILE", "2.4G", "20M", "HT", "1T", "02", "30",
+	"FCC", "2.4G", "20M", "HT", "1T", "03", "32",
+	"ETSI", "2.4G", "20M", "HT", "1T", "03", "30",
+	"MKK", "2.4G", "20M", "HT", "1T", "03", "34",
+	"IC", "2.4G", "20M", "HT", "1T", "03", "32",
+	"KCC", "2.4G", "20M", "HT", "1T", "03", "34",
+	"ACMA", "2.4G", "20M", "HT", "1T", "03", "30",
+	"CHILE", "2.4G", "20M", "HT", "1T", "03", "32",
+	"FCC", "2.4G", "20M", "HT", "1T", "04", "34",
+	"ETSI", "2.4G", "20M", "HT", "1T", "04", "30",
+	"MKK", "2.4G", "20M", "HT", "1T", "04", "34",
+	"IC", "2.4G", "20M", "HT", "1T", "04", "34",
+	"KCC", "2.4G", "20M", "HT", "1T", "04", "34",
+	"ACMA", "2.4G", "20M", "HT", "1T", "04", "30",
+	"CHILE", "2.4G", "20M", "HT", "1T", "04", "34",
+	"FCC", "2.4G", "20M", "HT", "1T", "05", "34",
+	"ETSI", "2.4G", "20M", "HT", "1T", "05", "30",
+	"MKK", "2.4G", "20M", "HT", "1T", "05", "34",
+	"IC", "2.4G", "20M", "HT", "1T", "05", "34",
+	"KCC", "2.4G", "20M", "HT", "1T", "05", "34",
+	"ACMA", "2.4G", "20M", "HT", "1T", "05", "30",
+	"CHILE", "2.4G", "20M", "HT", "1T", "05", "34",
+	"FCC", "2.4G", "20M", "HT", "1T", "06", "34",
+	"ETSI", "2.4G", "20M", "HT", "1T", "06", "30",
+	"MKK", "2.4G", "20M", "HT", "1T", "06", "34",
+	"IC", "2.4G", "20M", "HT", "1T", "06", "34",
+	"KCC", "2.4G", "20M", "HT", "1T", "06", "34",
+	"ACMA", "2.4G", "20M", "HT", "1T", "06", "30",
+	"CHILE", "2.4G", "20M", "HT", "1T", "06", "34",
+	"FCC", "2.4G", "20M", "HT", "1T", "07", "34",
+	"ETSI", "2.4G", "20M", "HT", "1T", "07", "30",
+	"MKK", "2.4G", "20M", "HT", "1T", "07", "34",
+	"IC", "2.4G", "20M", "HT", "1T", "07", "34",
+	"KCC", "2.4G", "20M", "HT", "1T", "07", "34",
+	"ACMA", "2.4G", "20M", "HT", "1T", "07", "30",
+	"CHILE", "2.4G", "20M", "HT", "1T", "07", "34",
+	"FCC", "2.4G", "20M", "HT", "1T", "08", "34",
+	"ETSI", "2.4G", "20M", "HT", "1T", "08", "30",
+	"MKK", "2.4G", "20M", "HT", "1T", "08", "34",
+	"IC", "2.4G", "20M", "HT", "1T", "08", "34",
+	"KCC", "2.4G", "20M", "HT", "1T", "08", "34",
+	"ACMA", "2.4G", "20M", "HT", "1T", "08", "30",
+	"CHILE", "2.4G", "20M", "HT", "1T", "08", "34",
+	"FCC", "2.4G", "20M", "HT", "1T", "09", "32",
+	"ETSI", "2.4G", "20M", "HT", "1T", "09", "30",
+	"MKK", "2.4G", "20M", "HT", "1T", "09", "34",
+	"IC", "2.4G", "20M", "HT", "1T", "09", "32",
+	"KCC", "2.4G", "20M", "HT", "1T", "09", "34",
+	"ACMA", "2.4G", "20M", "HT", "1T", "09", "30",
+	"CHILE", "2.4G", "20M", "HT", "1T", "09", "32",
+	"FCC", "2.4G", "20M", "HT", "1T", "10", "30",
+	"ETSI", "2.4G", "20M", "HT", "1T", "10", "30",
+	"MKK", "2.4G", "20M", "HT", "1T", "10", "34",
+	"IC", "2.4G", "20M", "HT", "1T", "10", "30",
+	"KCC", "2.4G", "20M", "HT", "1T", "10", "34",
+	"ACMA", "2.4G", "20M", "HT", "1T", "10", "30",
+	"CHILE", "2.4G", "20M", "HT", "1T", "10", "30",
+	"FCC", "2.4G", "20M", "HT", "1T", "11", "28",
+	"ETSI", "2.4G", "20M", "HT", "1T", "11", "30",
+	"MKK", "2.4G", "20M", "HT", "1T", "11", "34",
+	"IC", "2.4G", "20M", "HT", "1T", "11", "28",
+	"KCC", "2.4G", "20M", "HT", "1T", "11", "34",
+	"ACMA", "2.4G", "20M", "HT", "1T", "11", "30",
+	"CHILE", "2.4G", "20M", "HT", "1T", "11", "28",
+	"FCC", "2.4G", "20M", "HT", "1T", "12", "26",
+	"ETSI", "2.4G", "20M", "HT", "1T", "12", "30",
+	"MKK", "2.4G", "20M", "HT", "1T", "12", "34",
+	"IC", "2.4G", "20M", "HT", "1T", "12", "26",
+	"KCC", "2.4G", "20M", "HT", "1T", "12", "34",
+	"ACMA", "2.4G", "20M", "HT", "1T", "12", "30",
+	"CHILE", "2.4G", "20M", "HT", "1T", "12", "26",
+	"FCC", "2.4G", "20M", "HT", "1T", "13", "12",
+	"ETSI", "2.4G", "20M", "HT", "1T", "13", "30",
+	"MKK", "2.4G", "20M", "HT", "1T", "13", "34",
+	"IC", "2.4G", "20M", "HT", "1T", "13", "12",
+	"KCC", "2.4G", "20M", "HT", "1T", "13", "32",
+	"ACMA", "2.4G", "20M", "HT", "1T", "13", "30",
+	"CHILE", "2.4G", "20M", "HT", "1T", "13", "12",
+	"FCC", "2.4G", "20M", "HT", "1T", "14", "63",
+	"ETSI", "2.4G", "20M", "HT", "1T", "14", "63",
+	"MKK", "2.4G", "20M", "HT", "1T", "14", "63",
+	"IC", "2.4G", "20M", "HT", "1T", "14", "63",
+	"KCC", "2.4G", "20M", "HT", "1T", "14", "63",
+	"ACMA", "2.4G", "20M", "HT", "1T", "14", "63",
+	"CHILE", "2.4G", "20M", "HT", "1T", "14", "63",
+	"FCC", "2.4G", "40M", "HT", "1T", "01", "63",
+	"ETSI", "2.4G", "40M", "HT", "1T", "01", "63",
+	"MKK", "2.4G", "40M", "HT", "1T", "01", "63",
+	"IC", "2.4G", "40M", "HT", "1T", "01", "63",
+	"KCC", "2.4G", "40M", "HT", "1T", "01", "63",
+	"ACMA", "2.4G", "40M", "HT", "1T", "01", "63",
+	"CHILE", "2.4G", "40M", "HT", "1T", "01", "63",
+	"FCC", "2.4G", "40M", "HT", "1T", "02", "63",
+	"ETSI", "2.4G", "40M", "HT", "1T", "02", "63",
+	"MKK", "2.4G", "40M", "HT", "1T", "02", "63",
+	"IC", "2.4G", "40M", "HT", "1T", "02", "63",
+	"KCC", "2.4G", "40M", "HT", "1T", "02", "63",
+	"ACMA", "2.4G", "40M", "HT", "1T", "02", "63",
+	"CHILE", "2.4G", "40M", "HT", "1T", "02", "63",
+	"FCC", "2.4G", "40M", "HT", "1T", "03", "26",
+	"ETSI", "2.4G", "40M", "HT", "1T", "03", "30",
+	"MKK", "2.4G", "40M", "HT", "1T", "03", "30",
+	"IC", "2.4G", "40M", "HT", "1T", "03", "26",
+	"KCC", "2.4G", "40M", "HT", "1T", "03", "30",
+	"ACMA", "2.4G", "40M", "HT", "1T", "03", "30",
+	"CHILE", "2.4G", "40M", "HT", "1T", "03", "26",
+	"FCC", "2.4G", "40M", "HT", "1T", "04", "26",
+	"ETSI", "2.4G", "40M", "HT", "1T", "04", "30",
+	"MKK", "2.4G", "40M", "HT", "1T", "04", "30",
+	"IC", "2.4G", "40M", "HT", "1T", "04", "26",
+	"KCC", "2.4G", "40M", "HT", "1T", "04", "30",
+	"ACMA", "2.4G", "40M", "HT", "1T", "04", "30",
+	"CHILE", "2.4G", "40M", "HT", "1T", "04", "26",
+	"FCC", "2.4G", "40M", "HT", "1T", "05", "30",
+	"ETSI", "2.4G", "40M", "HT", "1T", "05", "30",
+	"MKK", "2.4G", "40M", "HT", "1T", "05", "30",
+	"IC", "2.4G", "40M", "HT", "1T", "05", "30",
+	"KCC", "2.4G", "40M", "HT", "1T", "05", "30",
+	"ACMA", "2.4G", "40M", "HT", "1T", "05", "30",
+	"CHILE", "2.4G", "40M", "HT", "1T", "05", "30",
+	"FCC", "2.4G", "40M", "HT", "1T", "06", "30",
+	"ETSI", "2.4G", "40M", "HT", "1T", "06", "30",
+	"MKK", "2.4G", "40M", "HT", "1T", "06", "30",
+	"IC", "2.4G", "40M", "HT", "1T", "06", "30",
+	"KCC", "2.4G", "40M", "HT", "1T", "06", "30",
+	"ACMA", "2.4G", "40M", "HT", "1T", "06", "30",
+	"CHILE", "2.4G", "40M", "HT", "1T", "06", "30",
+	"FCC", "2.4G", "40M", "HT", "1T", "07", "30",
+	"ETSI", "2.4G", "40M", "HT", "1T", "07", "30",
+	"MKK", "2.4G", "40M", "HT", "1T", "07", "30",
+	"IC", "2.4G", "40M", "HT", "1T", "07", "30",
+	"KCC", "2.4G", "40M", "HT", "1T", "07", "30",
+	"ACMA", "2.4G", "40M", "HT", "1T", "07", "30",
+	"CHILE", "2.4G", "40M", "HT", "1T", "07", "30",
+	"FCC", "2.4G", "40M", "HT", "1T", "08", "26",
+	"ETSI", "2.4G", "40M", "HT", "1T", "08", "30",
+	"MKK", "2.4G", "40M", "HT", "1T", "08", "30",
+	"IC", "2.4G", "40M", "HT", "1T", "08", "26",
+	"KCC", "2.4G", "40M", "HT", "1T", "08", "30",
+	"ACMA", "2.4G", "40M", "HT", "1T", "08", "30",
+	"CHILE", "2.4G", "40M", "HT", "1T", "08", "26",
+	"FCC", "2.4G", "40M", "HT", "1T", "09", "26",
+	"ETSI", "2.4G", "40M", "HT", "1T", "09", "30",
+	"MKK", "2.4G", "40M", "HT", "1T", "09", "30",
+	"IC", "2.4G", "40M", "HT", "1T", "09", "26",
+	"KCC", "2.4G", "40M", "HT", "1T", "09", "30",
+	"ACMA", "2.4G", "40M", "HT", "1T", "09", "30",
+	"CHILE", "2.4G", "40M", "HT", "1T", "09", "26",
+	"FCC", "2.4G", "40M", "HT", "1T", "10", "28",
+	"ETSI", "2.4G", "40M", "HT", "1T", "10", "30",
+	"MKK", "2.4G", "40M", "HT", "1T", "10", "30",
+	"IC", "2.4G", "40M", "HT", "1T", "10", "28",
+	"KCC", "2.4G", "40M", "HT", "1T", "10", "30",
+	"ACMA", "2.4G", "40M", "HT", "1T", "10", "30",
+	"CHILE", "2.4G", "40M", "HT", "1T", "10", "28",
+	"FCC", "2.4G", "40M", "HT", "1T", "11", "20",
+	"ETSI", "2.4G", "40M", "HT", "1T", "11", "30",
+	"MKK", "2.4G", "40M", "HT", "1T", "11", "30",
+	"IC", "2.4G", "40M", "HT", "1T", "11", "20",
+	"KCC", "2.4G", "40M", "HT", "1T", "11", "30",
+	"ACMA", "2.4G", "40M", "HT", "1T", "11", "30",
+	"CHILE", "2.4G", "40M", "HT", "1T", "11", "20",
+	"FCC", "2.4G", "40M", "HT", "1T", "12", "63",
+	"ETSI", "2.4G", "40M", "HT", "1T", "12", "63",
+	"MKK", "2.4G", "40M", "HT", "1T", "12", "63",
+	"IC", "2.4G", "40M", "HT", "1T", "12", "63",
+	"KCC", "2.4G", "40M", "HT", "1T", "12", "63",
+	"ACMA", "2.4G", "40M", "HT", "1T", "12", "63",
+	"CHILE", "2.4G", "40M", "HT", "1T", "12", "63",
+	"FCC", "2.4G", "40M", "HT", "1T", "13", "63",
+	"ETSI", "2.4G", "40M", "HT", "1T", "13", "63",
+	"MKK", "2.4G", "40M", "HT", "1T", "13", "63",
+	"IC", "2.4G", "40M", "HT", "1T", "13", "63",
+	"KCC", "2.4G", "40M", "HT", "1T", "13", "63",
+	"ACMA", "2.4G", "40M", "HT", "1T", "13", "63",
+	"CHILE", "2.4G", "40M", "HT", "1T", "13", "63",
+	"FCC", "2.4G", "40M", "HT", "1T", "14", "63",
+	"ETSI", "2.4G", "40M", "HT", "1T", "14", "63",
+	"MKK", "2.4G", "40M", "HT", "1T", "14", "63",
+	"IC", "2.4G", "40M", "HT", "1T", "14", "63",
+	"KCC", "2.4G", "40M", "HT", "1T", "14", "63",
+	"ACMA", "2.4G", "40M", "HT", "1T", "14", "63",
+	"CHILE", "2.4G", "40M", "HT", "1T", "14", "63",
+	"FCC", "5G", "20M", "OFDM", "1T", "36", "31",
+	"ETSI", "5G", "20M", "OFDM", "1T", "36", "32",
+	"MKK", "5G", "20M", "OFDM", "1T", "36", "33",
+	"IC", "5G", "20M", "OFDM", "1T", "36", "31",
+	"KCC", "5G", "20M", "OFDM", "1T", "36", "29",
+	"ACMA", "5G", "20M", "OFDM", "1T", "36", "32",
+	"CHILE", "5G", "20M", "OFDM", "1T", "36", "29",
+	"FCC", "5G", "20M", "OFDM", "1T", "40", "33",
+	"ETSI", "5G", "20M", "OFDM", "1T", "40", "32",
+	"MKK", "5G", "20M", "OFDM", "1T", "40", "33",
+	"IC", "5G", "20M", "OFDM", "1T", "40", "31",
+	"KCC", "5G", "20M", "OFDM", "1T", "40", "28",
+	"ACMA", "5G", "20M", "OFDM", "1T", "40", "32",
+	"CHILE", "5G", "20M", "OFDM", "1T", "40", "29",
+	"FCC", "5G", "20M", "OFDM", "1T", "44", "33",
+	"ETSI", "5G", "20M", "OFDM", "1T", "44", "32",
+	"MKK", "5G", "20M", "OFDM", "1T", "44", "33",
+	"IC", "5G", "20M", "OFDM", "1T", "44", "31",
+	"KCC", "5G", "20M", "OFDM", "1T", "44", "28",
+	"ACMA", "5G", "20M", "OFDM", "1T", "44", "32",
+	"CHILE", "5G", "20M", "OFDM", "1T", "44", "30",
+	"FCC", "5G", "20M", "OFDM", "1T", "48", "31",
+	"ETSI", "5G", "20M", "OFDM", "1T", "48", "32",
+	"MKK", "5G", "20M", "OFDM", "1T", "48", "33",
+	"IC", "5G", "20M", "OFDM", "1T", "48", "31",
+	"KCC", "5G", "20M", "OFDM", "1T", "48", "27",
+	"ACMA", "5G", "20M", "OFDM", "1T", "48", "32",
+	"CHILE", "5G", "20M", "OFDM", "1T", "48", "30",
+	"FCC", "5G", "20M", "OFDM", "1T", "52", "33",
+	"ETSI", "5G", "20M", "OFDM", "1T", "52", "32",
+	"MKK", "5G", "20M", "OFDM", "1T", "52", "33",
+	"IC", "5G", "20M", "OFDM", "1T", "52", "32",
+	"KCC", "5G", "20M", "OFDM", "1T", "52", "16",
+	"ACMA", "5G", "20M", "OFDM", "1T", "52", "32",
+	"CHILE", "5G", "20M", "OFDM", "1T", "52", "30",
+	"FCC", "5G", "20M", "OFDM", "1T", "56", "33",
+	"ETSI", "5G", "20M", "OFDM", "1T", "56", "32",
+	"MKK", "5G", "20M", "OFDM", "1T", "56", "33",
+	"IC", "5G", "20M", "OFDM", "1T", "56", "32",
+	"KCC", "5G", "20M", "OFDM", "1T", "56", "33",
+	"ACMA", "5G", "20M", "OFDM", "1T", "56", "32",
+	"CHILE", "5G", "20M", "OFDM", "1T", "56", "30",
+	"FCC", "5G", "20M", "OFDM", "1T", "60", "33",
+	"ETSI", "5G", "20M", "OFDM", "1T", "60", "32",
+	"MKK", "5G", "20M", "OFDM", "1T", "60", "33",
+	"IC", "5G", "20M", "OFDM", "1T", "60", "32",
+	"KCC", "5G", "20M", "OFDM", "1T", "60", "33",
+	"ACMA", "5G", "20M", "OFDM", "1T", "60", "32",
+	"CHILE", "5G", "20M", "OFDM", "1T", "60", "30",
+	"FCC", "5G", "20M", "OFDM", "1T", "64", "30",
+	"ETSI", "5G", "20M", "OFDM", "1T", "64", "32",
+	"MKK", "5G", "20M", "OFDM", "1T", "64", "33",
+	"IC", "5G", "20M", "OFDM", "1T", "64", "30",
+	"KCC", "5G", "20M", "OFDM", "1T", "64", "33",
+	"ACMA", "5G", "20M", "OFDM", "1T", "64", "32",
+	"CHILE", "5G", "20M", "OFDM", "1T", "64", "29",
+	"FCC", "5G", "20M", "OFDM", "1T", "100", "30",
+	"ETSI", "5G", "20M", "OFDM", "1T", "100", "32",
+	"MKK", "5G", "20M", "OFDM", "1T", "100", "33",
+	"IC", "5G", "20M", "OFDM", "1T", "100", "30",
+	"KCC", "5G", "20M", "OFDM", "1T", "100", "33",
+	"ACMA", "5G", "20M", "OFDM", "1T", "100", "32",
+	"CHILE", "5G", "20M", "OFDM", "1T", "100", "30",
+	"FCC", "5G", "20M", "OFDM", "1T", "104", "33",
+	"ETSI", "5G", "20M", "OFDM", "1T", "104", "32",
+	"MKK", "5G", "20M", "OFDM", "1T", "104", "33",
+	"IC", "5G", "20M", "OFDM", "1T", "104", "33",
+	"KCC", "5G", "20M", "OFDM", "1T", "104", "33",
+	"ACMA", "5G", "20M", "OFDM", "1T", "104", "32",
+	"CHILE", "5G", "20M", "OFDM", "1T", "104", "30",
+	"FCC", "5G", "20M", "OFDM", "1T", "108", "33",
+	"ETSI", "5G", "20M", "OFDM", "1T", "108", "32",
+	"MKK", "5G", "20M", "OFDM", "1T", "108", "33",
+	"IC", "5G", "20M", "OFDM", "1T", "108", "33",
+	"KCC", "5G", "20M", "OFDM", "1T", "108", "33",
+	"ACMA", "5G", "20M", "OFDM", "1T", "108", "32",
+	"CHILE", "5G", "20M", "OFDM", "1T", "108", "30",
+	"FCC", "5G", "20M", "OFDM", "1T", "112", "33",
+	"ETSI", "5G", "20M", "OFDM", "1T", "112", "32",
+	"MKK", "5G", "20M", "OFDM", "1T", "112", "33",
+	"IC", "5G", "20M", "OFDM", "1T", "112", "33",
+	"KCC", "5G", "20M", "OFDM", "1T", "112", "33",
+	"ACMA", "5G", "20M", "OFDM", "1T", "112", "32",
+	"CHILE", "5G", "20M", "OFDM", "1T", "112", "30",
+	"FCC", "5G", "20M", "OFDM", "1T", "116", "33",
+	"ETSI", "5G", "20M", "OFDM", "1T", "116", "32",
+	"MKK", "5G", "20M", "OFDM", "1T", "116", "33",
+	"IC", "5G", "20M", "OFDM", "1T", "116", "33",
+	"KCC", "5G", "20M", "OFDM", "1T", "116", "33",
+	"ACMA", "5G", "20M", "OFDM", "1T", "116", "32",
+	"CHILE", "5G", "20M", "OFDM", "1T", "116", "30",
+	"FCC", "5G", "20M", "OFDM", "1T", "120", "33",
+	"ETSI", "5G", "20M", "OFDM", "1T", "120", "32",
+	"MKK", "5G", "20M", "OFDM", "1T", "120", "33",
+	"IC", "5G", "20M", "OFDM", "1T", "120", "63",
+	"KCC", "5G", "20M", "OFDM", "1T", "120", "33",
+	"ACMA", "5G", "20M", "OFDM", "1T", "120", "32",
+	"CHILE", "5G", "20M", "OFDM", "1T", "120", "30",
+	"FCC", "5G", "20M", "OFDM", "1T", "124", "33",
+	"ETSI", "5G", "20M", "OFDM", "1T", "124", "32",
+	"MKK", "5G", "20M", "OFDM", "1T", "124", "33",
+	"IC", "5G", "20M", "OFDM", "1T", "124", "63",
+	"KCC", "5G", "20M", "OFDM", "1T", "124", "33",
+	"ACMA", "5G", "20M", "OFDM", "1T", "124", "32",
+	"CHILE", "5G", "20M", "OFDM", "1T", "124", "30",
+	"FCC", "5G", "20M", "OFDM", "1T", "128", "33",
+	"ETSI", "5G", "20M", "OFDM", "1T", "128", "32",
+	"MKK", "5G", "20M", "OFDM", "1T", "128", "33",
+	"IC", "5G", "20M", "OFDM", "1T", "128", "63",
+	"KCC", "5G", "20M", "OFDM", "1T", "128", "63",
+	"ACMA", "5G", "20M", "OFDM", "1T", "128", "32",
+	"CHILE", "5G", "20M", "OFDM", "1T", "128", "30",
+	"FCC", "5G", "20M", "OFDM", "1T", "132", "33",
+	"ETSI", "5G", "20M", "OFDM", "1T", "132", "32",
+	"MKK", "5G", "20M", "OFDM", "1T", "132", "33",
+	"IC", "5G", "20M", "OFDM", "1T", "132", "33",
+	"KCC", "5G", "20M", "OFDM", "1T", "132", "63",
+	"ACMA", "5G", "20M", "OFDM", "1T", "132", "32",
+	"CHILE", "5G", "20M", "OFDM", "1T", "132", "30",
+	"FCC", "5G", "20M", "OFDM", "1T", "136", "33",
+	"ETSI", "5G", "20M", "OFDM", "1T", "136", "32",
+	"MKK", "5G", "20M", "OFDM", "1T", "136", "33",
+	"IC", "5G", "20M", "OFDM", "1T", "136", "33",
+	"KCC", "5G", "20M", "OFDM", "1T", "136", "63",
+	"ACMA", "5G", "20M", "OFDM", "1T", "136", "32",
+	"CHILE", "5G", "20M", "OFDM", "1T", "136", "30",
+	"FCC", "5G", "20M", "OFDM", "1T", "140", "31",
+	"ETSI", "5G", "20M", "OFDM", "1T", "140", "32",
+	"MKK", "5G", "20M", "OFDM", "1T", "140", "33",
+	"IC", "5G", "20M", "OFDM", "1T", "140", "31",
+	"KCC", "5G", "20M", "OFDM", "1T", "140", "63",
+	"ACMA", "5G", "20M", "OFDM", "1T", "140", "32",
+	"CHILE", "5G", "20M", "OFDM", "1T", "140", "30",
+	"FCC", "5G", "20M", "OFDM", "1T", "144", "30",
+	"ETSI", "5G", "20M", "OFDM", "1T", "144", "63",
+	"MKK", "5G", "20M", "OFDM", "1T", "144", "63",
+	"IC", "5G", "20M", "OFDM", "1T", "144", "30",
+	"KCC", "5G", "20M", "OFDM", "1T", "144", "63",
+	"ACMA", "5G", "20M", "OFDM", "1T", "144", "63",
+	"CHILE", "5G", "20M", "OFDM", "1T", "144", "30",
+	"FCC", "5G", "20M", "OFDM", "1T", "149", "33",
+	"ETSI", "5G", "20M", "OFDM", "1T", "149", "63",
+	"MKK", "5G", "20M", "OFDM", "1T", "149", "63",
+	"IC", "5G", "20M", "OFDM", "1T", "149", "30",
+	"KCC", "5G", "20M", "OFDM", "1T", "149", "33",
+	"ACMA", "5G", "20M", "OFDM", "1T", "149", "33",
+	"CHILE", "5G", "20M", "OFDM", "1T", "149", "30",
+	"FCC", "5G", "20M", "OFDM", "1T", "153", "33",
+	"ETSI", "5G", "20M", "OFDM", "1T", "153", "63",
+	"MKK", "5G", "20M", "OFDM", "1T", "153", "63",
+	"IC", "5G", "20M", "OFDM", "1T", "153", "33",
+	"KCC", "5G", "20M", "OFDM", "1T", "153", "33",
+	"ACMA", "5G", "20M", "OFDM", "1T", "153", "33",
+	"CHILE", "5G", "20M", "OFDM", "1T", "153", "30",
+	"FCC", "5G", "20M", "OFDM", "1T", "157", "33",
+	"ETSI", "5G", "20M", "OFDM", "1T", "157", "63",
+	"MKK", "5G", "20M", "OFDM", "1T", "157", "63",
+	"IC", "5G", "20M", "OFDM", "1T", "157", "33",
+	"KCC", "5G", "20M", "OFDM", "1T", "157", "33",
+	"ACMA", "5G", "20M", "OFDM", "1T", "157", "33",
+	"CHILE", "5G", "20M", "OFDM", "1T", "157", "30",
+	"FCC", "5G", "20M", "OFDM", "1T", "161", "33",
+	"ETSI", "5G", "20M", "OFDM", "1T", "161", "63",
+	"MKK", "5G", "20M", "OFDM", "1T", "161", "63",
+	"IC", "5G", "20M", "OFDM", "1T", "161", "33",
+	"KCC", "5G", "20M", "OFDM", "1T", "161", "31",
+	"ACMA", "5G", "20M", "OFDM", "1T", "161", "33",
+	"CHILE", "5G", "20M", "OFDM", "1T", "161", "30",
+	"FCC", "5G", "20M", "OFDM", "1T", "165", "33",
+	"ETSI", "5G", "20M", "OFDM", "1T", "165", "63",
+	"MKK", "5G", "20M", "OFDM", "1T", "165", "63",
+	"IC", "5G", "20M", "OFDM", "1T", "165", "33",
+	"KCC", "5G", "20M", "OFDM", "1T", "165", "63",
+	"ACMA", "5G", "20M", "OFDM", "1T", "165", "33",
+	"CHILE", "5G", "20M", "OFDM", "1T", "165", "30",
+	"FCC", "5G", "20M", "HT", "1T", "36", "30",
+	"ETSI", "5G", "20M", "HT", "1T", "36", "32",
+	"MKK", "5G", "20M", "HT", "1T", "36", "33",
+	"IC", "5G", "20M", "HT", "1T", "36", "30",
+	"KCC", "5G", "20M", "HT", "1T", "36", "27",
+	"ACMA", "5G", "20M", "HT", "1T", "36", "32",
+	"CHILE", "5G", "20M", "HT", "1T", "36", "30",
+	"FCC", "5G", "20M", "HT", "1T", "40", "33",
+	"ETSI", "5G", "20M", "HT", "1T", "40", "32",
+	"MKK", "5G", "20M", "HT", "1T", "40", "33",
+	"IC", "5G", "20M", "HT", "1T", "40", "31",
+	"KCC", "5G", "20M", "HT", "1T", "40", "29",
+	"ACMA", "5G", "20M", "HT", "1T", "40", "32",
+	"CHILE", "5G", "20M", "HT", "1T", "40", "30",
+	"FCC", "5G", "20M", "HT", "1T", "44", "33",
+	"ETSI", "5G", "20M", "HT", "1T", "44", "32",
+	"MKK", "5G", "20M", "HT", "1T", "44", "33",
+	"IC", "5G", "20M", "HT", "1T", "44", "31",
+	"KCC", "5G", "20M", "HT", "1T", "44", "29",
+	"ACMA", "5G", "20M", "HT", "1T", "44", "32",
+	"CHILE", "5G", "20M", "HT", "1T", "44", "30",
+	"FCC", "5G", "20M", "HT", "1T", "48", "33",
+	"ETSI", "5G", "20M", "HT", "1T", "48", "32",
+	"MKK", "5G", "20M", "HT", "1T", "48", "33",
+	"IC", "5G", "20M", "HT", "1T", "48", "31",
+	"KCC", "5G", "20M", "HT", "1T", "48", "26",
+	"ACMA", "5G", "20M", "HT", "1T", "48", "32",
+	"CHILE", "5G", "20M", "HT", "1T", "48", "30",
+	"FCC", "5G", "20M", "HT", "1T", "52", "33",
+	"ETSI", "5G", "20M", "HT", "1T", "52", "32",
+	"MKK", "5G", "20M", "HT", "1T", "52", "33",
+	"IC", "5G", "20M", "HT", "1T", "52", "32",
+	"KCC", "5G", "20M", "HT", "1T", "52", "7",
+	"ACMA", "5G", "20M", "HT", "1T", "52", "32",
+	"CHILE", "5G", "20M", "HT", "1T", "52", "30",
+	"FCC", "5G", "20M", "HT", "1T", "56", "33",
+	"ETSI", "5G", "20M", "HT", "1T", "56", "32",
+	"MKK", "5G", "20M", "HT", "1T", "56", "33",
+	"IC", "5G", "20M", "HT", "1T", "56", "32",
+	"KCC", "5G", "20M", "HT", "1T", "56", "33",
+	"ACMA", "5G", "20M", "HT", "1T", "56", "32",
+	"CHILE", "5G", "20M", "HT", "1T", "56", "30",
+	"FCC", "5G", "20M", "HT", "1T", "60", "33",
+	"ETSI", "5G", "20M", "HT", "1T", "60", "32",
+	"MKK", "5G", "20M", "HT", "1T", "60", "33",
+	"IC", "5G", "20M", "HT", "1T", "60", "32",
+	"KCC", "5G", "20M", "HT", "1T", "60", "33",
+	"ACMA", "5G", "20M", "HT", "1T", "60", "32",
+	"CHILE", "5G", "20M", "HT", "1T", "60", "30",
+	"FCC", "5G", "20M", "HT", "1T", "64", "30",
+	"ETSI", "5G", "20M", "HT", "1T", "64", "32",
+	"MKK", "5G", "20M", "HT", "1T", "64", "33",
+	"IC", "5G", "20M", "HT", "1T", "64", "30",
+	"KCC", "5G", "20M", "HT", "1T", "64", "33",
+	"ACMA", "5G", "20M", "HT", "1T", "64", "32",
+	"CHILE", "5G", "20M", "HT", "1T", "64", "30",
+	"FCC", "5G", "20M", "HT", "1T", "100", "30",
+	"ETSI", "5G", "20M", "HT", "1T", "100", "32",
+	"MKK", "5G", "20M", "HT", "1T", "100", "33",
+	"IC", "5G", "20M", "HT", "1T", "100", "30",
+	"KCC", "5G", "20M", "HT", "1T", "100", "33",
+	"ACMA", "5G", "20M", "HT", "1T", "100", "32",
+	"CHILE", "5G", "20M", "HT", "1T", "100", "30",
+	"FCC", "5G", "20M", "HT", "1T", "104", "33",
+	"ETSI", "5G", "20M", "HT", "1T", "104", "32",
+	"MKK", "5G", "20M", "HT", "1T", "104", "33",
+	"IC", "5G", "20M", "HT", "1T", "104", "33",
+	"KCC", "5G", "20M", "HT", "1T", "104", "33",
+	"ACMA", "5G", "20M", "HT", "1T", "104", "32",
+	"CHILE", "5G", "20M", "HT", "1T", "104", "30",
+	"FCC", "5G", "20M", "HT", "1T", "108", "33",
+	"ETSI", "5G", "20M", "HT", "1T", "108", "32",
+	"MKK", "5G", "20M", "HT", "1T", "108", "33",
+	"IC", "5G", "20M", "HT", "1T", "108", "33",
+	"KCC", "5G", "20M", "HT", "1T", "108", "33",
+	"ACMA", "5G", "20M", "HT", "1T", "108", "32",
+	"CHILE", "5G", "20M", "HT", "1T", "108", "30",
+	"FCC", "5G", "20M", "HT", "1T", "112", "33",
+	"ETSI", "5G", "20M", "HT", "1T", "112", "32",
+	"MKK", "5G", "20M", "HT", "1T", "112", "33",
+	"IC", "5G", "20M", "HT", "1T", "112", "33",
+	"KCC", "5G", "20M", "HT", "1T", "112", "33",
+	"ACMA", "5G", "20M", "HT", "1T", "112", "32",
+	"CHILE", "5G", "20M", "HT", "1T", "112", "30",
+	"FCC", "5G", "20M", "HT", "1T", "116", "33",
+	"ETSI", "5G", "20M", "HT", "1T", "116", "32",
+	"MKK", "5G", "20M", "HT", "1T", "116", "33",
+	"IC", "5G", "20M", "HT", "1T", "116", "33",
+	"KCC", "5G", "20M", "HT", "1T", "116", "33",
+	"ACMA", "5G", "20M", "HT", "1T", "116", "32",
+	"CHILE", "5G", "20M", "HT", "1T", "116", "30",
+	"FCC", "5G", "20M", "HT", "1T", "120", "33",
+	"ETSI", "5G", "20M", "HT", "1T", "120", "32",
+	"MKK", "5G", "20M", "HT", "1T", "120", "33",
+	"IC", "5G", "20M", "HT", "1T", "120", "63",
+	"KCC", "5G", "20M", "HT", "1T", "120", "33",
+	"ACMA", "5G", "20M", "HT", "1T", "120", "32",
+	"CHILE", "5G", "20M", "HT", "1T", "120", "30",
+	"FCC", "5G", "20M", "HT", "1T", "124", "33",
+	"ETSI", "5G", "20M", "HT", "1T", "124", "32",
+	"MKK", "5G", "20M", "HT", "1T", "124", "33",
+	"IC", "5G", "20M", "HT", "1T", "124", "63",
+	"KCC", "5G", "20M", "HT", "1T", "124", "33",
+	"ACMA", "5G", "20M", "HT", "1T", "124", "32",
+	"CHILE", "5G", "20M", "HT", "1T", "124", "30",
+	"FCC", "5G", "20M", "HT", "1T", "128", "33",
+	"ETSI", "5G", "20M", "HT", "1T", "128", "32",
+	"MKK", "5G", "20M", "HT", "1T", "128", "33",
+	"IC", "5G", "20M", "HT", "1T", "128", "63",
+	"KCC", "5G", "20M", "HT", "1T", "128", "63",
+	"ACMA", "5G", "20M", "HT", "1T", "128", "32",
+	"CHILE", "5G", "20M", "HT", "1T", "128", "30",
+	"FCC", "5G", "20M", "HT", "1T", "132", "33",
+	"ETSI", "5G", "20M", "HT", "1T", "132", "32",
+	"MKK", "5G", "20M", "HT", "1T", "132", "33",
+	"IC", "5G", "20M", "HT", "1T", "132", "33",
+	"KCC", "5G", "20M", "HT", "1T", "132", "63",
+	"ACMA", "5G", "20M", "HT", "1T", "132", "32",
+	"CHILE", "5G", "20M", "HT", "1T", "132", "30",
+	"FCC", "5G", "20M", "HT", "1T", "136", "33",
+	"ETSI", "5G", "20M", "HT", "1T", "136", "32",
+	"MKK", "5G", "20M", "HT", "1T", "136", "33",
+	"IC", "5G", "20M", "HT", "1T", "136", "33",
+	"KCC", "5G", "20M", "HT", "1T", "136", "63",
+	"ACMA", "5G", "20M", "HT", "1T", "136", "32",
+	"CHILE", "5G", "20M", "HT", "1T", "136", "30",
+	"FCC", "5G", "20M", "HT", "1T", "140", "29",
+	"ETSI", "5G", "20M", "HT", "1T", "140", "32",
+	"MKK", "5G", "20M", "HT", "1T", "140", "33",
+	"IC", "5G", "20M", "HT", "1T", "140", "29",
+	"KCC", "5G", "20M", "HT", "1T", "140", "63",
+	"ACMA", "5G", "20M", "HT", "1T", "140", "32",
+	"CHILE", "5G", "20M", "HT", "1T", "140", "30",
+	"FCC", "5G", "20M", "HT", "1T", "144", "27",
+	"ETSI", "5G", "20M", "HT", "1T", "144", "63",
+	"MKK", "5G", "20M", "HT", "1T", "144", "63",
+	"IC", "5G", "20M", "HT", "1T", "144", "27",
+	"KCC", "5G", "20M", "HT", "1T", "144", "63",
+	"ACMA", "5G", "20M", "HT", "1T", "144", "63",
+	"CHILE", "5G", "20M", "HT", "1T", "144", "30",
+	"FCC", "5G", "20M", "HT", "1T", "149", "33",
+	"ETSI", "5G", "20M", "HT", "1T", "149", "63",
+	"MKK", "5G", "20M", "HT", "1T", "149", "63",
+	"IC", "5G", "20M", "HT", "1T", "149", "33",
+	"KCC", "5G", "20M", "HT", "1T", "149", "33",
+	"ACMA", "5G", "20M", "HT", "1T", "149", "33",
+	"CHILE", "5G", "20M", "HT", "1T", "149", "30",
+	"FCC", "5G", "20M", "HT", "1T", "153", "33",
+	"ETSI", "5G", "20M", "HT", "1T", "153", "63",
+	"MKK", "5G", "20M", "HT", "1T", "153", "63",
+	"IC", "5G", "20M", "HT", "1T", "153", "33",
+	"KCC", "5G", "20M", "HT", "1T", "153", "33",
+	"ACMA", "5G", "20M", "HT", "1T", "153", "33",
+	"CHILE", "5G", "20M", "HT", "1T", "153", "30",
+	"FCC", "5G", "20M", "HT", "1T", "157", "33",
+	"ETSI", "5G", "20M", "HT", "1T", "157", "63",
+	"MKK", "5G", "20M", "HT", "1T", "157", "63",
+	"IC", "5G", "20M", "HT", "1T", "157", "33",
+	"KCC", "5G", "20M", "HT", "1T", "157", "33",
+	"ACMA", "5G", "20M", "HT", "1T", "157", "33",
+	"CHILE", "5G", "20M", "HT", "1T", "157", "30",
+	"FCC", "5G", "20M", "HT", "1T", "161", "33",
+	"ETSI", "5G", "20M", "HT", "1T", "161", "63",
+	"MKK", "5G", "20M", "HT", "1T", "161", "63",
+	"IC", "5G", "20M", "HT", "1T", "161", "33",
+	"KCC", "5G", "20M", "HT", "1T", "161", "31",
+	"ACMA", "5G", "20M", "HT", "1T", "161", "33",
+	"CHILE", "5G", "20M", "HT", "1T", "161", "30",
+	"FCC", "5G", "20M", "HT", "1T", "165", "33",
+	"ETSI", "5G", "20M", "HT", "1T", "165", "63",
+	"MKK", "5G", "20M", "HT", "1T", "165", "63",
+	"IC", "5G", "20M", "HT", "1T", "165", "33",
+	"KCC", "5G", "20M", "HT", "1T", "165", "63",
+	"ACMA", "5G", "20M", "HT", "1T", "165", "33",
+	"CHILE", "5G", "20M", "HT", "1T", "165", "30",
+	"FCC", "5G", "40M", "HT", "1T", "38", "22",
+	"ETSI", "5G", "40M", "HT", "1T", "38", "32",
+	"MKK", "5G", "40M", "HT", "1T", "38", "32",
+	"IC", "5G", "40M", "HT", "1T", "38", "22",
+	"KCC", "5G", "40M", "HT", "1T", "38", "26",
+	"ACMA", "5G", "40M", "HT", "1T", "38", "32",
+	"CHILE", "5G", "40M", "HT", "1T", "38", "22",
+	"FCC", "5G", "40M", "HT", "1T", "46", "32",
+	"ETSI", "5G", "40M", "HT", "1T", "46", "32",
+	"MKK", "5G", "40M", "HT", "1T", "46", "32",
+	"IC", "5G", "40M", "HT", "1T", "46", "32",
+	"KCC", "5G", "40M", "HT", "1T", "46", "28",
+	"ACMA", "5G", "40M", "HT", "1T", "46", "32",
+	"CHILE", "5G", "40M", "HT", "1T", "46", "30",
+	"FCC", "5G", "40M", "HT", "1T", "54", "32",
+	"ETSI", "5G", "40M", "HT", "1T", "54", "32",
+	"MKK", "5G", "40M", "HT", "1T", "54", "32",
+	"IC", "5G", "40M", "HT", "1T", "54", "32",
+	"KCC", "5G", "40M", "HT", "1T", "54", "22",
+	"ACMA", "5G", "40M", "HT", "1T", "54", "32",
+	"CHILE", "5G", "40M", "HT", "1T", "54", "30",
+	"FCC", "5G", "40M", "HT", "1T", "62", "23",
+	"ETSI", "5G", "40M", "HT", "1T", "62", "32",
+	"MKK", "5G", "40M", "HT", "1T", "62", "32",
+	"IC", "5G", "40M", "HT", "1T", "62", "23",
+	"KCC", "5G", "40M", "HT", "1T", "62", "31",
+	"ACMA", "5G", "40M", "HT", "1T", "62", "32",
+	"CHILE", "5G", "40M", "HT", "1T", "62", "23",
+	"FCC", "5G", "40M", "HT", "1T", "102", "21",
+	"ETSI", "5G", "40M", "HT", "1T", "102", "32",
+	"MKK", "5G", "40M", "HT", "1T", "102", "32",
+	"IC", "5G", "40M", "HT", "1T", "102", "21",
+	"KCC", "5G", "40M", "HT", "1T", "102", "31",
+	"ACMA", "5G", "40M", "HT", "1T", "102", "32",
+	"CHILE", "5G", "40M", "HT", "1T", "102", "30",
+	"FCC", "5G", "40M", "HT", "1T", "110", "32",
+	"ETSI", "5G", "40M", "HT", "1T", "110", "32",
+	"MKK", "5G", "40M", "HT", "1T", "110", "32",
+	"IC", "5G", "40M", "HT", "1T", "110", "32",
+	"KCC", "5G", "40M", "HT", "1T", "110", "32",
+	"ACMA", "5G", "40M", "HT", "1T", "110", "32",
+	"CHILE", "5G", "40M", "HT", "1T", "110", "30",
+	"FCC", "5G", "40M", "HT", "1T", "118", "32",
+	"ETSI", "5G", "40M", "HT", "1T", "118", "32",
+	"MKK", "5G", "40M", "HT", "1T", "118", "32",
+	"IC", "5G", "40M", "HT", "1T", "118", "63",
+	"KCC", "5G", "40M", "HT", "1T", "118", "32",
+	"ACMA", "5G", "40M", "HT", "1T", "118", "32",
+	"CHILE", "5G", "40M", "HT", "1T", "118", "30",
+	"FCC", "5G", "40M", "HT", "1T", "126", "32",
+	"ETSI", "5G", "40M", "HT", "1T", "126", "32",
+	"MKK", "5G", "40M", "HT", "1T", "126", "32",
+	"IC", "5G", "40M", "HT", "1T", "126", "63",
+	"KCC", "5G", "40M", "HT", "1T", "126", "63",
+	"ACMA", "5G", "40M", "HT", "1T", "126", "32",
+	"CHILE", "5G", "40M", "HT", "1T", "126", "30",
+	"FCC", "5G", "40M", "HT", "1T", "134", "32",
+	"ETSI", "5G", "40M", "HT", "1T", "134", "32",
+	"MKK", "5G", "40M", "HT", "1T", "134", "32",
+	"IC", "5G", "40M", "HT", "1T", "134", "32",
+	"KCC", "5G", "40M", "HT", "1T", "134", "63",
+	"ACMA", "5G", "40M", "HT", "1T", "134", "32",
+	"CHILE", "5G", "40M", "HT", "1T", "134", "30",
+	"FCC", "5G", "40M", "HT", "1T", "142", "29",
+	"ETSI", "5G", "40M", "HT", "1T", "142", "63",
+	"MKK", "5G", "40M", "HT", "1T", "142", "63",
+	"IC", "5G", "40M", "HT", "1T", "142", "29",
+	"KCC", "5G", "40M", "HT", "1T", "142", "63",
+	"ACMA", "5G", "40M", "HT", "1T", "142", "63",
+	"CHILE", "5G", "40M", "HT", "1T", "142", "30",
+	"FCC", "5G", "40M", "HT", "1T", "151", "32",
+	"ETSI", "5G", "40M", "HT", "1T", "151", "63",
+	"MKK", "5G", "40M", "HT", "1T", "151", "63",
+	"IC", "5G", "40M", "HT", "1T", "151", "32",
+	"KCC", "5G", "40M", "HT", "1T", "151", "27",
+	"ACMA", "5G", "40M", "HT", "1T", "151", "32",
+	"CHILE", "5G", "40M", "HT", "1T", "151", "30",
+	"FCC", "5G", "40M", "HT", "1T", "159", "32",
+	"ETSI", "5G", "40M", "HT", "1T", "159", "63",
+	"MKK", "5G", "40M", "HT", "1T", "159", "63",
+	"IC", "5G", "40M", "HT", "1T", "159", "32",
+	"KCC", "5G", "40M", "HT", "1T", "159", "26",
+	"ACMA", "5G", "40M", "HT", "1T", "159", "32",
+	"CHILE", "5G", "40M", "HT", "1T", "159", "30",
+	"FCC", "5G", "80M", "VHT", "1T", "42", "19",
+	"ETSI", "5G", "80M", "VHT", "1T", "42", "32",
+	"MKK", "5G", "80M", "VHT", "1T", "42", "28",
+	"IC", "5G", "80M", "VHT", "1T", "42", "19",
+	"KCC", "5G", "80M", "VHT", "1T", "42", "25",
+	"ACMA", "5G", "80M", "VHT", "1T", "42", "32",
+	"CHILE", "5G", "80M", "VHT", "1T", "42", "19",
+	"FCC", "5G", "80M", "VHT", "1T", "58", "22",
+	"ETSI", "5G", "80M", "VHT", "1T", "58", "32",
+	"MKK", "5G", "80M", "VHT", "1T", "58", "28",
+	"IC", "5G", "80M", "VHT", "1T", "58", "22",
+	"KCC", "5G", "80M", "VHT", "1T", "58", "28",
+	"ACMA", "5G", "80M", "VHT", "1T", "58", "32",
+	"CHILE", "5G", "80M", "VHT", "1T", "58", "22",
+	"FCC", "5G", "80M", "VHT", "1T", "106", "18",
+	"ETSI", "5G", "80M", "VHT", "1T", "106", "32",
+	"MKK", "5G", "80M", "VHT", "1T", "106", "32",
+	"IC", "5G", "80M", "VHT", "1T", "106", "18",
+	"KCC", "5G", "80M", "VHT", "1T", "106", "30",
+	"ACMA", "5G", "80M", "VHT", "1T", "106", "32",
+	"CHILE", "5G", "80M", "VHT", "1T", "106", "30",
+	"FCC", "5G", "80M", "VHT", "1T", "122", "32",
+	"ETSI", "5G", "80M", "VHT", "1T", "122", "32",
+	"MKK", "5G", "80M", "VHT", "1T", "122", "32",
+	"IC", "5G", "80M", "VHT", "1T", "122", "63",
+	"KCC", "5G", "80M", "VHT", "1T", "122", "26",
+	"ACMA", "5G", "80M", "VHT", "1T", "122", "32",
+	"CHILE", "5G", "80M", "VHT", "1T", "122", "30",
+	"FCC", "5G", "80M", "VHT", "1T", "138", "28",
+	"ETSI", "5G", "80M", "VHT", "1T", "138", "63",
+	"MKK", "5G", "80M", "VHT", "1T", "138", "63",
+	"IC", "5G", "80M", "VHT", "1T", "138", "28",
+	"KCC", "5G", "80M", "VHT", "1T", "138", "63",
+	"ACMA", "5G", "80M", "VHT", "1T", "138", "63",
+	"CHILE", "5G", "80M", "VHT", "1T", "138", "30",
+	"FCC", "5G", "80M", "VHT", "1T", "155", "32",
+	"ETSI", "5G", "80M", "VHT", "1T", "155", "63",
+	"MKK", "5G", "80M", "VHT", "1T", "155", "63",
+	"IC", "5G", "80M", "VHT", "1T", "155", "32",
+	"KCC", "5G", "80M", "VHT", "1T", "155", "27",
+	"ACMA", "5G", "80M", "VHT", "1T", "155", "32",
+	"CHILE", "5G", "80M", "VHT", "1T", "155", "30"
+};
+
+void
+odm_read_and_config_mp_8821c_txpwr_lmt(struct dm_struct *dm)
+{
+	u32	i = 0;
+#if (DM_ODM_SUPPORT_TYPE == ODM_IOT)
+	u32	array_len = sizeof(array_mp_8821c_txpwr_lmt) / sizeof(u8);
+	u8	*array = (u8 *)array_mp_8821c_txpwr_lmt;
+#else
+	u32	array_len = sizeof(array_mp_8821c_txpwr_lmt) / sizeof(u8 *);
+	u8	**array = (u8 **)array_mp_8821c_txpwr_lmt;
+#endif
+
+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
+	void	*adapter = dm->adapter;
+	HAL_DATA_TYPE	*hal_data = GET_HAL_DATA(((PADAPTER)adapter));
+
+	PlatformZeroMemory(hal_data->BufOfLinesPwrLmt, MAX_LINES_HWCONFIG_TXT * MAX_BYTES_LINE_HWCONFIG_TXT);
+	hal_data->nLinesReadPwrLmt = array_len / 7;
+#endif
+
+	PHYDM_DBG(dm, ODM_COMP_INIT, "===> %s\n", __func__);
+
+	for (i = 0; i < array_len; i += 7) {
+#if (DM_ODM_SUPPORT_TYPE == ODM_IOT)
+		u8	regulation = array[i];
+		u8	band = array[i + 1];
+		u8	bandwidth = array[i + 2];
+		u8	rate = array[i + 3];
+		u8	rf_path = array[i + 4];
+		u8	chnl = array[i + 5];
+		u8	val = array[i + 6];
+#else
+		u8	*regulation = array[i];
+		u8	*band = array[i + 1];
+		u8	*bandwidth = array[i + 2];
+		u8	*rate = array[i + 3];
+		u8	*rf_path = array[i + 4];
+		u8	*chnl = array[i + 5];
+		u8	*val = array[i + 6];
+#endif
+
+		odm_config_bb_txpwr_lmt_8821c(dm, regulation, band, bandwidth, rate, rf_path, chnl, val);
+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
+		rsprintf((char *)hal_data->BufOfLinesPwrLmt[i / 7], 100, "\"%s\", \"%s\", \"%s\", \"%s\", \"%s\", \"%s\", \"%s\",",
+		regulation, band, bandwidth, rate, rf_path, chnl, val);
+#endif
+	}
+}
+
+/******************************************************************************
+*                           txpwr_lmt_fccsar.TXT
+******************************************************************************/
+
+const char *array_mp_8821c_txpwr_lmt_fccsar[] = {
+	"FCC", "2.4G", "20M", "CCK", "1T", "01", "30",
+	"ETSI", "2.4G", "20M", "CCK", "1T", "01", "30",
+	"MKK", "2.4G", "20M", "CCK", "1T", "01", "34",
+	"IC", "2.4G", "20M", "CCK", "1T", "01", "30",
+	"KCC", "2.4G", "20M", "CCK", "1T", "01", "34",
+	"ACMA", "2.4G", "20M", "CCK", "1T", "01", "30",
+	"CHILE", "2.4G", "20M", "CCK", "1T", "01", "30",
+	"FCC", "2.4G", "20M", "CCK", "1T", "02", "32",
+	"ETSI", "2.4G", "20M", "CCK", "1T", "02", "30",
+	"MKK", "2.4G", "20M", "CCK", "1T", "02", "34",
+	"IC", "2.4G", "20M", "CCK", "1T", "02", "32",
+	"KCC", "2.4G", "20M", "CCK", "1T", "02", "34",
+	"ACMA", "2.4G", "20M", "CCK", "1T", "02", "30",
+	"CHILE", "2.4G", "20M", "CCK", "1T", "02", "32",
+	"FCC", "2.4G", "20M", "CCK", "1T", "03", "32",
+	"ETSI", "2.4G", "20M", "CCK", "1T", "03", "30",
+	"MKK", "2.4G", "20M", "CCK", "1T", "03", "34",
+	"IC", "2.4G", "20M", "CCK", "1T", "03", "32",
+	"KCC", "2.4G", "20M", "CCK", "1T", "03", "34",
+	"ACMA", "2.4G", "20M", "CCK", "1T", "03", "30",
+	"CHILE", "2.4G", "20M", "CCK", "1T", "03", "32",
+	"FCC", "2.4G", "20M", "CCK", "1T", "04", "32",
+	"ETSI", "2.4G", "20M", "CCK", "1T", "04", "30",
+	"MKK", "2.4G", "20M", "CCK", "1T", "04", "34",
+	"IC", "2.4G", "20M", "CCK", "1T", "04", "32",
+	"KCC", "2.4G", "20M", "CCK", "1T", "04", "34",
+	"ACMA", "2.4G", "20M", "CCK", "1T", "04", "30",
+	"CHILE", "2.4G", "20M", "CCK", "1T", "04", "32",
+	"FCC", "2.4G", "20M", "CCK", "1T", "05", "32",
+	"ETSI", "2.4G", "20M", "CCK", "1T", "05", "30",
+	"MKK", "2.4G", "20M", "CCK", "1T", "05", "34",
+	"IC", "2.4G", "20M", "CCK", "1T", "05", "32",
+	"KCC", "2.4G", "20M", "CCK", "1T", "05", "34",
+	"ACMA", "2.4G", "20M", "CCK", "1T", "05", "30",
+	"CHILE", "2.4G", "20M", "CCK", "1T", "05", "32",
+	"FCC", "2.4G", "20M", "CCK", "1T", "06", "32",
+	"ETSI", "2.4G", "20M", "CCK", "1T", "06", "30",
+	"MKK", "2.4G", "20M", "CCK", "1T", "06", "34",
+	"IC", "2.4G", "20M", "CCK", "1T", "06", "32",
+	"KCC", "2.4G", "20M", "CCK", "1T", "06", "34",
+	"ACMA", "2.4G", "20M", "CCK", "1T", "06", "30",
+	"CHILE", "2.4G", "20M", "CCK", "1T", "06", "32",
+	"FCC", "2.4G", "20M", "CCK", "1T", "07", "32",
+	"ETSI", "2.4G", "20M", "CCK", "1T", "07", "30",
+	"MKK", "2.4G", "20M", "CCK", "1T", "07", "34",
+	"IC", "2.4G", "20M", "CCK", "1T", "07", "32",
+	"KCC", "2.4G", "20M", "CCK", "1T", "07", "34",
+	"ACMA", "2.4G", "20M", "CCK", "1T", "07", "30",
+	"CHILE", "2.4G", "20M", "CCK", "1T", "07", "32",
+	"FCC", "2.4G", "20M", "CCK", "1T", "08", "32",
+	"ETSI", "2.4G", "20M", "CCK", "1T", "08", "30",
+	"MKK", "2.4G", "20M", "CCK", "1T", "08", "34",
+	"IC", "2.4G", "20M", "CCK", "1T", "08", "32",
+	"KCC", "2.4G", "20M", "CCK", "1T", "08", "34",
+	"ACMA", "2.4G", "20M", "CCK", "1T", "08", "30",
+	"CHILE", "2.4G", "20M", "CCK", "1T", "08", "32",
+	"FCC", "2.4G", "20M", "CCK", "1T", "09", "32",
+	"ETSI", "2.4G", "20M", "CCK", "1T", "09", "30",
+	"MKK", "2.4G", "20M", "CCK", "1T", "09", "34",
+	"IC", "2.4G", "20M", "CCK", "1T", "09", "32",
+	"KCC", "2.4G", "20M", "CCK", "1T", "09", "34",
+	"ACMA", "2.4G", "20M", "CCK", "1T", "09", "30",
+	"CHILE", "2.4G", "20M", "CCK", "1T", "09", "32",
+	"FCC", "2.4G", "20M", "CCK", "1T", "10", "32",
+	"ETSI", "2.4G", "20M", "CCK", "1T", "10", "30",
+	"MKK", "2.4G", "20M", "CCK", "1T", "10", "34",
+	"IC", "2.4G", "20M", "CCK", "1T", "10", "32",
+	"KCC", "2.4G", "20M", "CCK", "1T", "10", "34",
+	"ACMA", "2.4G", "20M", "CCK", "1T", "10", "30",
+	"CHILE", "2.4G", "20M", "CCK", "1T", "10", "32",
+	"FCC", "2.4G", "20M", "CCK", "1T", "11", "32",
+	"ETSI", "2.4G", "20M", "CCK", "1T", "11", "30",
+	"MKK", "2.4G", "20M", "CCK", "1T", "11", "34",
+	"IC", "2.4G", "20M", "CCK", "1T", "11", "32",
+	"KCC", "2.4G", "20M", "CCK", "1T", "11", "34",
+	"ACMA", "2.4G", "20M", "CCK", "1T", "11", "30",
+	"CHILE", "2.4G", "20M", "CCK", "1T", "11", "32",
+	"FCC", "2.4G", "20M", "CCK", "1T", "12", "24",
+	"ETSI", "2.4G", "20M", "CCK", "1T", "12", "30",
+	"MKK", "2.4G", "20M", "CCK", "1T", "12", "34",
+	"IC", "2.4G", "20M", "CCK", "1T", "12", "24",
+	"KCC", "2.4G", "20M", "CCK", "1T", "12", "34",
+	"ACMA", "2.4G", "20M", "CCK", "1T", "12", "30",
+	"CHILE", "2.4G", "20M", "CCK", "1T", "12", "24",
+	"FCC", "2.4G", "20M", "CCK", "1T", "13", "16",
+	"ETSI", "2.4G", "20M", "CCK", "1T", "13", "30",
+	"MKK", "2.4G", "20M", "CCK", "1T", "13", "34",
+	"IC", "2.4G", "20M", "CCK", "1T", "13", "16",
+	"KCC", "2.4G", "20M", "CCK", "1T", "13", "34",
+	"ACMA", "2.4G", "20M", "CCK", "1T", "13", "30",
+	"CHILE", "2.4G", "20M", "CCK", "1T", "13", "16",
+	"FCC", "2.4G", "20M", "CCK", "1T", "14", "63",
+	"ETSI", "2.4G", "20M", "CCK", "1T", "14", "63",
+	"MKK", "2.4G", "20M", "CCK", "1T", "14", "34",
+	"IC", "2.4G", "20M", "CCK", "1T", "14", "63",
+	"KCC", "2.4G", "20M", "CCK", "1T", "14", "63",
+	"ACMA", "2.4G", "20M", "CCK", "1T", "14", "63",
+	"CHILE", "2.4G", "20M", "CCK", "1T", "14", "63",
+	"FCC", "2.4G", "20M", "OFDM", "1T", "01", "30",
+	"ETSI", "2.4G", "20M", "OFDM", "1T", "01", "30",
+	"MKK", "2.4G", "20M", "OFDM", "1T", "01", "34",
+	"IC", "2.4G", "20M", "OFDM", "1T", "01", "30",
+	"KCC", "2.4G", "20M", "OFDM", "1T", "01", "32",
+	"ACMA", "2.4G", "20M", "OFDM", "1T", "01", "30",
+	"CHILE", "2.4G", "20M", "OFDM", "1T", "01", "30",
+	"FCC", "2.4G", "20M", "OFDM", "1T", "02", "32",
+	"ETSI", "2.4G", "20M", "OFDM", "1T", "02", "30",
+	"MKK", "2.4G", "20M", "OFDM", "1T", "02", "34",
+	"IC", "2.4G", "20M", "OFDM", "1T", "02", "32",
+	"KCC", "2.4G", "20M", "OFDM", "1T", "02", "34",
+	"ACMA", "2.4G", "20M", "OFDM", "1T", "02", "30",
+	"CHILE", "2.4G", "20M", "OFDM", "1T", "02", "32",
+	"FCC", "2.4G", "20M", "OFDM", "1T", "03", "34",
+	"ETSI", "2.4G", "20M", "OFDM", "1T", "03", "30",
+	"MKK", "2.4G", "20M", "OFDM", "1T", "03", "34",
+	"IC", "2.4G", "20M", "OFDM", "1T", "03", "34",
+	"KCC", "2.4G", "20M", "OFDM", "1T", "03", "34",
+	"ACMA", "2.4G", "20M", "OFDM", "1T", "03", "30",
+	"CHILE", "2.4G", "20M", "OFDM", "1T", "03", "34",
+	"FCC", "2.4G", "20M", "OFDM", "1T", "04", "34",
+	"ETSI", "2.4G", "20M", "OFDM", "1T", "04", "30",
+	"MKK", "2.4G", "20M", "OFDM", "1T", "04", "34",
+	"IC", "2.4G", "20M", "OFDM", "1T", "04", "34",
+	"KCC", "2.4G", "20M", "OFDM", "1T", "04", "34",
+	"ACMA", "2.4G", "20M", "OFDM", "1T", "04", "30",
+	"CHILE", "2.4G", "20M", "OFDM", "1T", "04", "34",
+	"FCC", "2.4G", "20M", "OFDM", "1T", "05", "34",
+	"ETSI", "2.4G", "20M", "OFDM", "1T", "05", "30",
+	"MKK", "2.4G", "20M", "OFDM", "1T", "05", "34",
+	"IC", "2.4G", "20M", "OFDM", "1T", "05", "34",
+	"KCC", "2.4G", "20M", "OFDM", "1T", "05", "34",
+	"ACMA", "2.4G", "20M", "OFDM", "1T", "05", "30",
+	"CHILE", "2.4G", "20M", "OFDM", "1T", "05", "34",
+	"FCC", "2.4G", "20M", "OFDM", "1T", "06", "34",
+	"ETSI", "2.4G", "20M", "OFDM", "1T", "06", "30",
+	"MKK", "2.4G", "20M", "OFDM", "1T", "06", "34",
+	"IC", "2.4G", "20M", "OFDM", "1T", "06", "34",
+	"KCC", "2.4G", "20M", "OFDM", "1T", "06", "34",
+	"ACMA", "2.4G", "20M", "OFDM", "1T", "06", "30",
+	"CHILE", "2.4G", "20M", "OFDM", "1T", "06", "34",
+	"FCC", "2.4G", "20M", "OFDM", "1T", "07", "34",
+	"ETSI", "2.4G", "20M", "OFDM", "1T", "07", "30",
+	"MKK", "2.4G", "20M", "OFDM", "1T", "07", "34",
+	"IC", "2.4G", "20M", "OFDM", "1T", "07", "34",
+	"KCC", "2.4G", "20M", "OFDM", "1T", "07", "34",
+	"ACMA", "2.4G", "20M", "OFDM", "1T", "07", "30",
+	"CHILE", "2.4G", "20M", "OFDM", "1T", "07", "34",
+	"FCC", "2.4G", "20M", "OFDM", "1T", "08", "34",
+	"ETSI", "2.4G", "20M", "OFDM", "1T", "08", "30",
+	"MKK", "2.4G", "20M", "OFDM", "1T", "08", "34",
+	"IC", "2.4G", "20M", "OFDM", "1T", "08", "34",
+	"KCC", "2.4G", "20M", "OFDM", "1T", "08", "34",
+	"ACMA", "2.4G", "20M", "OFDM", "1T", "08", "30",
+	"CHILE", "2.4G", "20M", "OFDM", "1T", "08", "34",
+	"FCC", "2.4G", "20M", "OFDM", "1T", "09", "34",
+	"ETSI", "2.4G", "20M", "OFDM", "1T", "09", "30",
+	"MKK", "2.4G", "20M", "OFDM", "1T", "09", "34",
+	"IC", "2.4G", "20M", "OFDM", "1T", "09", "34",
+	"KCC", "2.4G", "20M", "OFDM", "1T", "09", "34",
+	"ACMA", "2.4G", "20M", "OFDM", "1T", "09", "30",
+	"CHILE", "2.4G", "20M", "OFDM", "1T", "09", "34",
+	"FCC", "2.4G", "20M", "OFDM", "1T", "10", "32",
+	"ETSI", "2.4G", "20M", "OFDM", "1T", "10", "30",
+	"MKK", "2.4G", "20M", "OFDM", "1T", "10", "34",
+	"IC", "2.4G", "20M", "OFDM", "1T", "10", "32",
+	"KCC", "2.4G", "20M", "OFDM", "1T", "10", "34",
+	"ACMA", "2.4G", "20M", "OFDM", "1T", "10", "30",
+	"CHILE", "2.4G", "20M", "OFDM", "1T", "10", "32",
+	"FCC", "2.4G", "20M", "OFDM", "1T", "11", "30",
+	"ETSI", "2.4G", "20M", "OFDM", "1T", "11", "30",
+	"MKK", "2.4G", "20M", "OFDM", "1T", "11", "34",
+	"IC", "2.4G", "20M", "OFDM", "1T", "11", "30",
+	"KCC", "2.4G", "20M", "OFDM", "1T", "11", "34",
+	"ACMA", "2.4G", "20M", "OFDM", "1T", "11", "30",
+	"CHILE", "2.4G", "20M", "OFDM", "1T", "11", "30",
+	"FCC", "2.4G", "20M", "OFDM", "1T", "12", "28",
+	"ETSI", "2.4G", "20M", "OFDM", "1T", "12", "30",
+	"MKK", "2.4G", "20M", "OFDM", "1T", "12", "34",
+	"IC", "2.4G", "20M", "OFDM", "1T", "12", "28",
+	"KCC", "2.4G", "20M", "OFDM", "1T", "12", "34",
+	"ACMA", "2.4G", "20M", "OFDM", "1T", "12", "30",
+	"CHILE", "2.4G", "20M", "OFDM", "1T", "12", "28",
+	"FCC", "2.4G", "20M", "OFDM", "1T", "13", "16",
+	"ETSI", "2.4G", "20M", "OFDM", "1T", "13", "30",
+	"MKK", "2.4G", "20M", "OFDM", "1T", "13", "34",
+	"IC", "2.4G", "20M", "OFDM", "1T", "13", "16",
+	"KCC", "2.4G", "20M", "OFDM", "1T", "13", "32",
+	"ACMA", "2.4G", "20M", "OFDM", "1T", "13", "30",
+	"CHILE", "2.4G", "20M", "OFDM", "1T", "13", "16",
+	"FCC", "2.4G", "20M", "OFDM", "1T", "14", "63",
+	"ETSI", "2.4G", "20M", "OFDM", "1T", "14", "63",
+	"MKK", "2.4G", "20M", "OFDM", "1T", "14", "63",
+	"IC", "2.4G", "20M", "OFDM", "1T", "14", "63",
+	"KCC", "2.4G", "20M", "OFDM", "1T", "14", "63",
+	"ACMA", "2.4G", "20M", "OFDM", "1T", "14", "63",
+	"CHILE", "2.4G", "20M", "OFDM", "1T", "14", "63",
+	"FCC", "2.4G", "20M", "HT", "1T", "01", "26",
+	"ETSI", "2.4G", "20M", "HT", "1T", "01", "30",
+	"MKK", "2.4G", "20M", "HT", "1T", "01", "34",
+	"IC", "2.4G", "20M", "HT", "1T", "01", "26",
+	"KCC", "2.4G", "20M", "HT", "1T", "01", "32",
+	"ACMA", "2.4G", "20M", "HT", "1T", "01", "30",
+	"CHILE", "2.4G", "20M", "HT", "1T", "01", "26",
+	"FCC", "2.4G", "20M", "HT", "1T", "02", "30",
+	"ETSI", "2.4G", "20M", "HT", "1T", "02", "30",
+	"MKK", "2.4G", "20M", "HT", "1T", "02", "34",
+	"IC", "2.4G", "20M", "HT", "1T", "02", "30",
+	"KCC", "2.4G", "20M", "HT", "1T", "02", "34",
+	"ACMA", "2.4G", "20M", "HT", "1T", "02", "30",
+	"CHILE", "2.4G", "20M", "HT", "1T", "02", "30",
+	"FCC", "2.4G", "20M", "HT", "1T", "03", "32",
+	"ETSI", "2.4G", "20M", "HT", "1T", "03", "30",
+	"MKK", "2.4G", "20M", "HT", "1T", "03", "34",
+	"IC", "2.4G", "20M", "HT", "1T", "03", "32",
+	"KCC", "2.4G", "20M", "HT", "1T", "03", "34",
+	"ACMA", "2.4G", "20M", "HT", "1T", "03", "30",
+	"CHILE", "2.4G", "20M", "HT", "1T", "03", "32",
+	"FCC", "2.4G", "20M", "HT", "1T", "04", "34",
+	"ETSI", "2.4G", "20M", "HT", "1T", "04", "30",
+	"MKK", "2.4G", "20M", "HT", "1T", "04", "34",
+	"IC", "2.4G", "20M", "HT", "1T", "04", "34",
+	"KCC", "2.4G", "20M", "HT", "1T", "04", "34",
+	"ACMA", "2.4G", "20M", "HT", "1T", "04", "30",
+	"CHILE", "2.4G", "20M", "HT", "1T", "04", "34",
+	"FCC", "2.4G", "20M", "HT", "1T", "05", "34",
+	"ETSI", "2.4G", "20M", "HT", "1T", "05", "30",
+	"MKK", "2.4G", "20M", "HT", "1T", "05", "34",
+	"IC", "2.4G", "20M", "HT", "1T", "05", "34",
+	"KCC", "2.4G", "20M", "HT", "1T", "05", "34",
+	"ACMA", "2.4G", "20M", "HT", "1T", "05", "30",
+	"CHILE", "2.4G", "20M", "HT", "1T", "05", "34",
+	"FCC", "2.4G", "20M", "HT", "1T", "06", "34",
+	"ETSI", "2.4G", "20M", "HT", "1T", "06", "30",
+	"MKK", "2.4G", "20M", "HT", "1T", "06", "34",
+	"IC", "2.4G", "20M", "HT", "1T", "06", "34",
+	"KCC", "2.4G", "20M", "HT", "1T", "06", "34",
+	"ACMA", "2.4G", "20M", "HT", "1T", "06", "30",
+	"CHILE", "2.4G", "20M", "HT", "1T", "06", "34",
+	"FCC", "2.4G", "20M", "HT", "1T", "07", "34",
+	"ETSI", "2.4G", "20M", "HT", "1T", "07", "30",
+	"MKK", "2.4G", "20M", "HT", "1T", "07", "34",
+	"IC", "2.4G", "20M", "HT", "1T", "07", "34",
+	"KCC", "2.4G", "20M", "HT", "1T", "07", "34",
+	"ACMA", "2.4G", "20M", "HT", "1T", "07", "30",
+	"CHILE", "2.4G", "20M", "HT", "1T", "07", "34",
+	"FCC", "2.4G", "20M", "HT", "1T", "08", "34",
+	"ETSI", "2.4G", "20M", "HT", "1T", "08", "30",
+	"MKK", "2.4G", "20M", "HT", "1T", "08", "34",
+	"IC", "2.4G", "20M", "HT", "1T", "08", "34",
+	"KCC", "2.4G", "20M", "HT", "1T", "08", "34",
+	"ACMA", "2.4G", "20M", "HT", "1T", "08", "30",
+	"CHILE", "2.4G", "20M", "HT", "1T", "08", "34",
+	"FCC", "2.4G", "20M", "HT", "1T", "09", "32",
+	"ETSI", "2.4G", "20M", "HT", "1T", "09", "30",
+	"MKK", "2.4G", "20M", "HT", "1T", "09", "34",
+	"IC", "2.4G", "20M", "HT", "1T", "09", "32",
+	"KCC", "2.4G", "20M", "HT", "1T", "09", "34",
+	"ACMA", "2.4G", "20M", "HT", "1T", "09", "30",
+	"CHILE", "2.4G", "20M", "HT", "1T", "09", "32",
+	"FCC", "2.4G", "20M", "HT", "1T", "10", "30",
+	"ETSI", "2.4G", "20M", "HT", "1T", "10", "30",
+	"MKK", "2.4G", "20M", "HT", "1T", "10", "34",
+	"IC", "2.4G", "20M", "HT", "1T", "10", "30",
+	"KCC", "2.4G", "20M", "HT", "1T", "10", "34",
+	"ACMA", "2.4G", "20M", "HT", "1T", "10", "30",
+	"CHILE", "2.4G", "20M", "HT", "1T", "10", "30",
+	"FCC", "2.4G", "20M", "HT", "1T", "11", "28",
+	"ETSI", "2.4G", "20M", "HT", "1T", "11", "30",
+	"MKK", "2.4G", "20M", "HT", "1T", "11", "34",
+	"IC", "2.4G", "20M", "HT", "1T", "11", "28",
+	"KCC", "2.4G", "20M", "HT", "1T", "11", "34",
+	"ACMA", "2.4G", "20M", "HT", "1T", "11", "30",
+	"CHILE", "2.4G", "20M", "HT", "1T", "11", "28",
+	"FCC", "2.4G", "20M", "HT", "1T", "12", "26",
+	"ETSI", "2.4G", "20M", "HT", "1T", "12", "30",
+	"MKK", "2.4G", "20M", "HT", "1T", "12", "34",
+	"IC", "2.4G", "20M", "HT", "1T", "12", "26",
+	"KCC", "2.4G", "20M", "HT", "1T", "12", "34",
+	"ACMA", "2.4G", "20M", "HT", "1T", "12", "30",
+	"CHILE", "2.4G", "20M", "HT", "1T", "12", "26",
+	"FCC", "2.4G", "20M", "HT", "1T", "13", "12",
+	"ETSI", "2.4G", "20M", "HT", "1T", "13", "30",
+	"MKK", "2.4G", "20M", "HT", "1T", "13", "34",
+	"IC", "2.4G", "20M", "HT", "1T", "13", "12",
+	"KCC", "2.4G", "20M", "HT", "1T", "13", "32",
+	"ACMA", "2.4G", "20M", "HT", "1T", "13", "30",
+	"CHILE", "2.4G", "20M", "HT", "1T", "13", "12",
+	"FCC", "2.4G", "20M", "HT", "1T", "14", "63",
+	"ETSI", "2.4G", "20M", "HT", "1T", "14", "63",
+	"MKK", "2.4G", "20M", "HT", "1T", "14", "63",
+	"IC", "2.4G", "20M", "HT", "1T", "14", "63",
+	"KCC", "2.4G", "20M", "HT", "1T", "14", "63",
+	"ACMA", "2.4G", "20M", "HT", "1T", "14", "63",
+	"CHILE", "2.4G", "20M", "HT", "1T", "14", "63",
+	"FCC", "2.4G", "40M", "HT", "1T", "01", "63",
+	"ETSI", "2.4G", "40M", "HT", "1T", "01", "63",
+	"MKK", "2.4G", "40M", "HT", "1T", "01", "63",
+	"IC", "2.4G", "40M", "HT", "1T", "01", "63",
+	"KCC", "2.4G", "40M", "HT", "1T", "01", "63",
+	"ACMA", "2.4G", "40M", "HT", "1T", "01", "63",
+	"CHILE", "2.4G", "40M", "HT", "1T", "01", "63",
+	"FCC", "2.4G", "40M", "HT", "1T", "02", "63",
+	"ETSI", "2.4G", "40M", "HT", "1T", "02", "63",
+	"MKK", "2.4G", "40M", "HT", "1T", "02", "63",
+	"IC", "2.4G", "40M", "HT", "1T", "02", "63",
+	"KCC", "2.4G", "40M", "HT", "1T", "02", "63",
+	"ACMA", "2.4G", "40M", "HT", "1T", "02", "63",
+	"CHILE", "2.4G", "40M", "HT", "1T", "02", "63",
+	"FCC", "2.4G", "40M", "HT", "1T", "03", "26",
+	"ETSI", "2.4G", "40M", "HT", "1T", "03", "30",
+	"MKK", "2.4G", "40M", "HT", "1T", "03", "30",
+	"IC", "2.4G", "40M", "HT", "1T", "03", "26",
+	"KCC", "2.4G", "40M", "HT", "1T", "03", "30",
+	"ACMA", "2.4G", "40M", "HT", "1T", "03", "30",
+	"CHILE", "2.4G", "40M", "HT", "1T", "03", "26",
+	"FCC", "2.4G", "40M", "HT", "1T", "04", "26",
+	"ETSI", "2.4G", "40M", "HT", "1T", "04", "30",
+	"MKK", "2.4G", "40M", "HT", "1T", "04", "30",
+	"IC", "2.4G", "40M", "HT", "1T", "04", "26",
+	"KCC", "2.4G", "40M", "HT", "1T", "04", "30",
+	"ACMA", "2.4G", "40M", "HT", "1T", "04", "30",
+	"CHILE", "2.4G", "40M", "HT", "1T", "04", "26",
+	"FCC", "2.4G", "40M", "HT", "1T", "05", "30",
+	"ETSI", "2.4G", "40M", "HT", "1T", "05", "30",
+	"MKK", "2.4G", "40M", "HT", "1T", "05", "30",
+	"IC", "2.4G", "40M", "HT", "1T", "05", "30",
+	"KCC", "2.4G", "40M", "HT", "1T", "05", "30",
+	"ACMA", "2.4G", "40M", "HT", "1T", "05", "30",
+	"CHILE", "2.4G", "40M", "HT", "1T", "05", "30",
+	"FCC", "2.4G", "40M", "HT", "1T", "06", "30",
+	"ETSI", "2.4G", "40M", "HT", "1T", "06", "30",
+	"MKK", "2.4G", "40M", "HT", "1T", "06", "30",
+	"IC", "2.4G", "40M", "HT", "1T", "06", "30",
+	"KCC", "2.4G", "40M", "HT", "1T", "06", "30",
+	"ACMA", "2.4G", "40M", "HT", "1T", "06", "30",
+	"CHILE", "2.4G", "40M", "HT", "1T", "06", "30",
+	"FCC", "2.4G", "40M", "HT", "1T", "07", "30",
+	"ETSI", "2.4G", "40M", "HT", "1T", "07", "30",
+	"MKK", "2.4G", "40M", "HT", "1T", "07", "30",
+	"IC", "2.4G", "40M", "HT", "1T", "07", "30",
+	"KCC", "2.4G", "40M", "HT", "1T", "07", "30",
+	"ACMA", "2.4G", "40M", "HT", "1T", "07", "30",
+	"CHILE", "2.4G", "40M", "HT", "1T", "07", "30",
+	"FCC", "2.4G", "40M", "HT", "1T", "08", "26",
+	"ETSI", "2.4G", "40M", "HT", "1T", "08", "30",
+	"MKK", "2.4G", "40M", "HT", "1T", "08", "30",
+	"IC", "2.4G", "40M", "HT", "1T", "08", "26",
+	"KCC", "2.4G", "40M", "HT", "1T", "08", "30",
+	"ACMA", "2.4G", "40M", "HT", "1T", "08", "30",
+	"CHILE", "2.4G", "40M", "HT", "1T", "08", "26",
+	"FCC", "2.4G", "40M", "HT", "1T", "09", "26",
+	"ETSI", "2.4G", "40M", "HT", "1T", "09", "30",
+	"MKK", "2.4G", "40M", "HT", "1T", "09", "30",
+	"IC", "2.4G", "40M", "HT", "1T", "09", "26",
+	"KCC", "2.4G", "40M", "HT", "1T", "09", "30",
+	"ACMA", "2.4G", "40M", "HT", "1T", "09", "30",
+	"CHILE", "2.4G", "40M", "HT", "1T", "09", "26",
+	"FCC", "2.4G", "40M", "HT", "1T", "10", "28",
+	"ETSI", "2.4G", "40M", "HT", "1T", "10", "30",
+	"MKK", "2.4G", "40M", "HT", "1T", "10", "30",
+	"IC", "2.4G", "40M", "HT", "1T", "10", "28",
+	"KCC", "2.4G", "40M", "HT", "1T", "10", "30",
+	"ACMA", "2.4G", "40M", "HT", "1T", "10", "30",
+	"CHILE", "2.4G", "40M", "HT", "1T", "10", "28",
+	"FCC", "2.4G", "40M", "HT", "1T", "11", "20",
+	"ETSI", "2.4G", "40M", "HT", "1T", "11", "30",
+	"MKK", "2.4G", "40M", "HT", "1T", "11", "30",
+	"IC", "2.4G", "40M", "HT", "1T", "11", "20",
+	"KCC", "2.4G", "40M", "HT", "1T", "11", "30",
+	"ACMA", "2.4G", "40M", "HT", "1T", "11", "30",
+	"CHILE", "2.4G", "40M", "HT", "1T", "11", "20",
+	"FCC", "2.4G", "40M", "HT", "1T", "12", "63",
+	"ETSI", "2.4G", "40M", "HT", "1T", "12", "63",
+	"MKK", "2.4G", "40M", "HT", "1T", "12", "63",
+	"IC", "2.4G", "40M", "HT", "1T", "12", "63",
+	"KCC", "2.4G", "40M", "HT", "1T", "12", "63",
+	"ACMA", "2.4G", "40M", "HT", "1T", "12", "63",
+	"CHILE", "2.4G", "40M", "HT", "1T", "12", "63",
+	"FCC", "2.4G", "40M", "HT", "1T", "13", "63",
+	"ETSI", "2.4G", "40M", "HT", "1T", "13", "63",
+	"MKK", "2.4G", "40M", "HT", "1T", "13", "63",
+	"IC", "2.4G", "40M", "HT", "1T", "13", "63",
+	"KCC", "2.4G", "40M", "HT", "1T", "13", "63",
+	"ACMA", "2.4G", "40M", "HT", "1T", "13", "63",
+	"CHILE", "2.4G", "40M", "HT", "1T", "13", "63",
+	"FCC", "2.4G", "40M", "HT", "1T", "14", "63",
+	"ETSI", "2.4G", "40M", "HT", "1T", "14", "63",
+	"MKK", "2.4G", "40M", "HT", "1T", "14", "63",
+	"IC", "2.4G", "40M", "HT", "1T", "14", "63",
+	"KCC", "2.4G", "40M", "HT", "1T", "14", "63",
+	"ACMA", "2.4G", "40M", "HT", "1T", "14", "63",
+	"CHILE", "2.4G", "40M", "HT", "1T", "14", "63",
+	"FCC", "5G", "20M", "OFDM", "1T", "36", "27",
+	"ETSI", "5G", "20M", "OFDM", "1T", "36", "32",
+	"MKK", "5G", "20M", "OFDM", "1T", "36", "33",
+	"IC", "5G", "20M", "OFDM", "1T", "36", "31",
+	"KCC", "5G", "20M", "OFDM", "1T", "36", "29",
+	"ACMA", "5G", "20M", "OFDM", "1T", "36", "32",
+	"CHILE", "5G", "20M", "OFDM", "1T", "36", "29",
+	"FCC", "5G", "20M", "OFDM", "1T", "40", "27",
+	"ETSI", "5G", "20M", "OFDM", "1T", "40", "32",
+	"MKK", "5G", "20M", "OFDM", "1T", "40", "33",
+	"IC", "5G", "20M", "OFDM", "1T", "40", "31",
+	"KCC", "5G", "20M", "OFDM", "1T", "40", "28",
+	"ACMA", "5G", "20M", "OFDM", "1T", "40", "32",
+	"CHILE", "5G", "20M", "OFDM", "1T", "40", "29",
+	"FCC", "5G", "20M", "OFDM", "1T", "44", "27",
+	"ETSI", "5G", "20M", "OFDM", "1T", "44", "32",
+	"MKK", "5G", "20M", "OFDM", "1T", "44", "33",
+	"IC", "5G", "20M", "OFDM", "1T", "44", "31",
+	"KCC", "5G", "20M", "OFDM", "1T", "44", "28",
+	"ACMA", "5G", "20M", "OFDM", "1T", "44", "32",
+	"CHILE", "5G", "20M", "OFDM", "1T", "44", "30",
+	"FCC", "5G", "20M", "OFDM", "1T", "48", "27",
+	"ETSI", "5G", "20M", "OFDM", "1T", "48", "32",
+	"MKK", "5G", "20M", "OFDM", "1T", "48", "33",
+	"IC", "5G", "20M", "OFDM", "1T", "48", "31",
+	"KCC", "5G", "20M", "OFDM", "1T", "48", "27",
+	"ACMA", "5G", "20M", "OFDM", "1T", "48", "32",
+	"CHILE", "5G", "20M", "OFDM", "1T", "48", "30",
+	"FCC", "5G", "20M", "OFDM", "1T", "52", "27",
+	"ETSI", "5G", "20M", "OFDM", "1T", "52", "32",
+	"MKK", "5G", "20M", "OFDM", "1T", "52", "33",
+	"IC", "5G", "20M", "OFDM", "1T", "52", "32",
+	"KCC", "5G", "20M", "OFDM", "1T", "52", "16",
+	"ACMA", "5G", "20M", "OFDM", "1T", "52", "32",
+	"CHILE", "5G", "20M", "OFDM", "1T", "52", "30",
+	"FCC", "5G", "20M", "OFDM", "1T", "56", "27",
+	"ETSI", "5G", "20M", "OFDM", "1T", "56", "32",
+	"MKK", "5G", "20M", "OFDM", "1T", "56", "33",
+	"IC", "5G", "20M", "OFDM", "1T", "56", "32",
+	"KCC", "5G", "20M", "OFDM", "1T", "56", "33",
+	"ACMA", "5G", "20M", "OFDM", "1T", "56", "32",
+	"CHILE", "5G", "20M", "OFDM", "1T", "56", "30",
+	"FCC", "5G", "20M", "OFDM", "1T", "60", "27",
+	"ETSI", "5G", "20M", "OFDM", "1T", "60", "32",
+	"MKK", "5G", "20M", "OFDM", "1T", "60", "33",
+	"IC", "5G", "20M", "OFDM", "1T", "60", "32",
+	"KCC", "5G", "20M", "OFDM", "1T", "60", "33",
+	"ACMA", "5G", "20M", "OFDM", "1T", "60", "32",
+	"CHILE", "5G", "20M", "OFDM", "1T", "60", "30",
+	"FCC", "5G", "20M", "OFDM", "1T", "64", "27",
+	"ETSI", "5G", "20M", "OFDM", "1T", "64", "32",
+	"MKK", "5G", "20M", "OFDM", "1T", "64", "33",
+	"IC", "5G", "20M", "OFDM", "1T", "64", "30",
+	"KCC", "5G", "20M", "OFDM", "1T", "64", "33",
+	"ACMA", "5G", "20M", "OFDM", "1T", "64", "32",
+	"CHILE", "5G", "20M", "OFDM", "1T", "64", "29",
+	"FCC", "5G", "20M", "OFDM", "1T", "100", "27",
+	"ETSI", "5G", "20M", "OFDM", "1T", "100", "32",
+	"MKK", "5G", "20M", "OFDM", "1T", "100", "33",
+	"IC", "5G", "20M", "OFDM", "1T", "100", "30",
+	"KCC", "5G", "20M", "OFDM", "1T", "100", "33",
+	"ACMA", "5G", "20M", "OFDM", "1T", "100", "32",
+	"CHILE", "5G", "20M", "OFDM", "1T", "100", "30",
+	"FCC", "5G", "20M", "OFDM", "1T", "104", "27",
+	"ETSI", "5G", "20M", "OFDM", "1T", "104", "32",
+	"MKK", "5G", "20M", "OFDM", "1T", "104", "33",
+	"IC", "5G", "20M", "OFDM", "1T", "104", "33",
+	"KCC", "5G", "20M", "OFDM", "1T", "104", "33",
+	"ACMA", "5G", "20M", "OFDM", "1T", "104", "32",
+	"CHILE", "5G", "20M", "OFDM", "1T", "104", "30",
+	"FCC", "5G", "20M", "OFDM", "1T", "108", "27",
+	"ETSI", "5G", "20M", "OFDM", "1T", "108", "32",
+	"MKK", "5G", "20M", "OFDM", "1T", "108", "33",
+	"IC", "5G", "20M", "OFDM", "1T", "108", "33",
+	"KCC", "5G", "20M", "OFDM", "1T", "108", "33",
+	"ACMA", "5G", "20M", "OFDM", "1T", "108", "32",
+	"CHILE", "5G", "20M", "OFDM", "1T", "108", "30",
+	"FCC", "5G", "20M", "OFDM", "1T", "112", "27",
+	"ETSI", "5G", "20M", "OFDM", "1T", "112", "32",
+	"MKK", "5G", "20M", "OFDM", "1T", "112", "33",
+	"IC", "5G", "20M", "OFDM", "1T", "112", "33",
+	"KCC", "5G", "20M", "OFDM", "1T", "112", "33",
+	"ACMA", "5G", "20M", "OFDM", "1T", "112", "32",
+	"CHILE", "5G", "20M", "OFDM", "1T", "112", "30",
+	"FCC", "5G", "20M", "OFDM", "1T", "116", "27",
+	"ETSI", "5G", "20M", "OFDM", "1T", "116", "32",
+	"MKK", "5G", "20M", "OFDM", "1T", "116", "33",
+	"IC", "5G", "20M", "OFDM", "1T", "116", "33",
+	"KCC", "5G", "20M", "OFDM", "1T", "116", "33",
+	"ACMA", "5G", "20M", "OFDM", "1T", "116", "32",
+	"CHILE", "5G", "20M", "OFDM", "1T", "116", "30",
+	"FCC", "5G", "20M", "OFDM", "1T", "120", "27",
+	"ETSI", "5G", "20M", "OFDM", "1T", "120", "32",
+	"MKK", "5G", "20M", "OFDM", "1T", "120", "33",
+	"IC", "5G", "20M", "OFDM", "1T", "120", "63",
+	"KCC", "5G", "20M", "OFDM", "1T", "120", "33",
+	"ACMA", "5G", "20M", "OFDM", "1T", "120", "32",
+	"CHILE", "5G", "20M", "OFDM", "1T", "120", "30",
+	"FCC", "5G", "20M", "OFDM", "1T", "124", "27",
+	"ETSI", "5G", "20M", "OFDM", "1T", "124", "32",
+	"MKK", "5G", "20M", "OFDM", "1T", "124", "33",
+	"IC", "5G", "20M", "OFDM", "1T", "124", "63",
+	"KCC", "5G", "20M", "OFDM", "1T", "124", "33",
+	"ACMA", "5G", "20M", "OFDM", "1T", "124", "32",
+	"CHILE", "5G", "20M", "OFDM", "1T", "124", "30",
+	"FCC", "5G", "20M", "OFDM", "1T", "128", "27",
+	"ETSI", "5G", "20M", "OFDM", "1T", "128", "32",
+	"MKK", "5G", "20M", "OFDM", "1T", "128", "33",
+	"IC", "5G", "20M", "OFDM", "1T", "128", "63",
+	"KCC", "5G", "20M", "OFDM", "1T", "128", "63",
+	"ACMA", "5G", "20M", "OFDM", "1T", "128", "32",
+	"CHILE", "5G", "20M", "OFDM", "1T", "128", "30",
+	"FCC", "5G", "20M", "OFDM", "1T", "132", "27",
+	"ETSI", "5G", "20M", "OFDM", "1T", "132", "32",
+	"MKK", "5G", "20M", "OFDM", "1T", "132", "33",
+	"IC", "5G", "20M", "OFDM", "1T", "132", "33",
+	"KCC", "5G", "20M", "OFDM", "1T", "132", "63",
+	"ACMA", "5G", "20M", "OFDM", "1T", "132", "32",
+	"CHILE", "5G", "20M", "OFDM", "1T", "132", "30",
+	"FCC", "5G", "20M", "OFDM", "1T", "136", "27",
+	"ETSI", "5G", "20M", "OFDM", "1T", "136", "32",
+	"MKK", "5G", "20M", "OFDM", "1T", "136", "33",
+	"IC", "5G", "20M", "OFDM", "1T", "136", "33",
+	"KCC", "5G", "20M", "OFDM", "1T", "136", "63",
+	"ACMA", "5G", "20M", "OFDM", "1T", "136", "32",
+	"CHILE", "5G", "20M", "OFDM", "1T", "136", "30",
+	"FCC", "5G", "20M", "OFDM", "1T", "140", "27",
+	"ETSI", "5G", "20M", "OFDM", "1T", "140", "32",
+	"MKK", "5G", "20M", "OFDM", "1T", "140", "33",
+	"IC", "5G", "20M", "OFDM", "1T", "140", "31",
+	"KCC", "5G", "20M", "OFDM", "1T", "140", "63",
+	"ACMA", "5G", "20M", "OFDM", "1T", "140", "32",
+	"CHILE", "5G", "20M", "OFDM", "1T", "140", "30",
+	"FCC", "5G", "20M", "OFDM", "1T", "144", "27",
+	"ETSI", "5G", "20M", "OFDM", "1T", "144", "63",
+	"MKK", "5G", "20M", "OFDM", "1T", "144", "63",
+	"IC", "5G", "20M", "OFDM", "1T", "144", "30",
+	"KCC", "5G", "20M", "OFDM", "1T", "144", "63",
+	"ACMA", "5G", "20M", "OFDM", "1T", "144", "63",
+	"CHILE", "5G", "20M", "OFDM", "1T", "144", "30",
+	"FCC", "5G", "20M", "OFDM", "1T", "149", "28",
+	"ETSI", "5G", "20M", "OFDM", "1T", "149", "63",
+	"MKK", "5G", "20M", "OFDM", "1T", "149", "63",
+	"IC", "5G", "20M", "OFDM", "1T", "149", "30",
+	"KCC", "5G", "20M", "OFDM", "1T", "149", "33",
+	"ACMA", "5G", "20M", "OFDM", "1T", "149", "33",
+	"CHILE", "5G", "20M", "OFDM", "1T", "149", "30",
+	"FCC", "5G", "20M", "OFDM", "1T", "153", "28",
+	"ETSI", "5G", "20M", "OFDM", "1T", "153", "63",
+	"MKK", "5G", "20M", "OFDM", "1T", "153", "63",
+	"IC", "5G", "20M", "OFDM", "1T", "153", "33",
+	"KCC", "5G", "20M", "OFDM", "1T", "153", "33",
+	"ACMA", "5G", "20M", "OFDM", "1T", "153", "33",
+	"CHILE", "5G", "20M", "OFDM", "1T", "153", "30",
+	"FCC", "5G", "20M", "OFDM", "1T", "157", "28",
+	"ETSI", "5G", "20M", "OFDM", "1T", "157", "63",
+	"MKK", "5G", "20M", "OFDM", "1T", "157", "63",
+	"IC", "5G", "20M", "OFDM", "1T", "157", "33",
+	"KCC", "5G", "20M", "OFDM", "1T", "157", "33",
+	"ACMA", "5G", "20M", "OFDM", "1T", "157", "33",
+	"CHILE", "5G", "20M", "OFDM", "1T", "157", "30",
+	"FCC", "5G", "20M", "OFDM", "1T", "161", "28",
+	"ETSI", "5G", "20M", "OFDM", "1T", "161", "63",
+	"MKK", "5G", "20M", "OFDM", "1T", "161", "63",
+	"IC", "5G", "20M", "OFDM", "1T", "161", "33",
+	"KCC", "5G", "20M", "OFDM", "1T", "161", "31",
+	"ACMA", "5G", "20M", "OFDM", "1T", "161", "33",
+	"CHILE", "5G", "20M", "OFDM", "1T", "161", "30",
+	"FCC", "5G", "20M", "OFDM", "1T", "165", "28",
+	"ETSI", "5G", "20M", "OFDM", "1T", "165", "63",
+	"MKK", "5G", "20M", "OFDM", "1T", "165", "63",
+	"IC", "5G", "20M", "OFDM", "1T", "165", "33",
+	"KCC", "5G", "20M", "OFDM", "1T", "165", "63",
+	"ACMA", "5G", "20M", "OFDM", "1T", "165", "33",
+	"CHILE", "5G", "20M", "OFDM", "1T", "165", "30",
+	"FCC", "5G", "20M", "HT", "1T", "36", "27",
+	"ETSI", "5G", "20M", "HT", "1T", "36", "32",
+	"MKK", "5G", "20M", "HT", "1T", "36", "33",
+	"IC", "5G", "20M", "HT", "1T", "36", "30",
+	"KCC", "5G", "20M", "HT", "1T", "36", "27",
+	"ACMA", "5G", "20M", "HT", "1T", "36", "32",
+	"CHILE", "5G", "20M", "HT", "1T", "36", "30",
+	"FCC", "5G", "20M", "HT", "1T", "40", "27",
+	"ETSI", "5G", "20M", "HT", "1T", "40", "32",
+	"MKK", "5G", "20M", "HT", "1T", "40", "33",
+	"IC", "5G", "20M", "HT", "1T", "40", "31",
+	"KCC", "5G", "20M", "HT", "1T", "40", "29",
+	"ACMA", "5G", "20M", "HT", "1T", "40", "32",
+	"CHILE", "5G", "20M", "HT", "1T", "40", "30",
+	"FCC", "5G", "20M", "HT", "1T", "44", "27",
+	"ETSI", "5G", "20M", "HT", "1T", "44", "32",
+	"MKK", "5G", "20M", "HT", "1T", "44", "33",
+	"IC", "5G", "20M", "HT", "1T", "44", "31",
+	"KCC", "5G", "20M", "HT", "1T", "44", "29",
+	"ACMA", "5G", "20M", "HT", "1T", "44", "32",
+	"CHILE", "5G", "20M", "HT", "1T", "44", "30",
+	"FCC", "5G", "20M", "HT", "1T", "48", "27",
+	"ETSI", "5G", "20M", "HT", "1T", "48", "32",
+	"MKK", "5G", "20M", "HT", "1T", "48", "33",
+	"IC", "5G", "20M", "HT", "1T", "48", "31",
+	"KCC", "5G", "20M", "HT", "1T", "48", "26",
+	"ACMA", "5G", "20M", "HT", "1T", "48", "32",
+	"CHILE", "5G", "20M", "HT", "1T", "48", "30",
+	"FCC", "5G", "20M", "HT", "1T", "52", "27",
+	"ETSI", "5G", "20M", "HT", "1T", "52", "32",
+	"MKK", "5G", "20M", "HT", "1T", "52", "33",
+	"IC", "5G", "20M", "HT", "1T", "52", "32",
+	"KCC", "5G", "20M", "HT", "1T", "52", "7",
+	"ACMA", "5G", "20M", "HT", "1T", "52", "32",
+	"CHILE", "5G", "20M", "HT", "1T", "52", "30",
+	"FCC", "5G", "20M", "HT", "1T", "56", "27",
+	"ETSI", "5G", "20M", "HT", "1T", "56", "32",
+	"MKK", "5G", "20M", "HT", "1T", "56", "33",
+	"IC", "5G", "20M", "HT", "1T", "56", "32",
+	"KCC", "5G", "20M", "HT", "1T", "56", "33",
+	"ACMA", "5G", "20M", "HT", "1T", "56", "32",
+	"CHILE", "5G", "20M", "HT", "1T", "56", "30",
+	"FCC", "5G", "20M", "HT", "1T", "60", "27",
+	"ETSI", "5G", "20M", "HT", "1T", "60", "32",
+	"MKK", "5G", "20M", "HT", "1T", "60", "33",
+	"IC", "5G", "20M", "HT", "1T", "60", "32",
+	"KCC", "5G", "20M", "HT", "1T", "60", "33",
+	"ACMA", "5G", "20M", "HT", "1T", "60", "32",
+	"CHILE", "5G", "20M", "HT", "1T", "60", "30",
+	"FCC", "5G", "20M", "HT", "1T", "64", "27",
+	"ETSI", "5G", "20M", "HT", "1T", "64", "32",
+	"MKK", "5G", "20M", "HT", "1T", "64", "33",
+	"IC", "5G", "20M", "HT", "1T", "64", "30",
+	"KCC", "5G", "20M", "HT", "1T", "64", "33",
+	"ACMA", "5G", "20M", "HT", "1T", "64", "32",
+	"CHILE", "5G", "20M", "HT", "1T", "64", "30",
+	"FCC", "5G", "20M", "HT", "1T", "100", "27",
+	"ETSI", "5G", "20M", "HT", "1T", "100", "32",
+	"MKK", "5G", "20M", "HT", "1T", "100", "33",
+	"IC", "5G", "20M", "HT", "1T", "100", "30",
+	"KCC", "5G", "20M", "HT", "1T", "100", "33",
+	"ACMA", "5G", "20M", "HT", "1T", "100", "32",
+	"CHILE", "5G", "20M", "HT", "1T", "100", "30",
+	"FCC", "5G", "20M", "HT", "1T", "104", "27",
+	"ETSI", "5G", "20M", "HT", "1T", "104", "32",
+	"MKK", "5G", "20M", "HT", "1T", "104", "33",
+	"IC", "5G", "20M", "HT", "1T", "104", "33",
+	"KCC", "5G", "20M", "HT", "1T", "104", "33",
+	"ACMA", "5G", "20M", "HT", "1T", "104", "32",
+	"CHILE", "5G", "20M", "HT", "1T", "104", "30",
+	"FCC", "5G", "20M", "HT", "1T", "108", "27",
+	"ETSI", "5G", "20M", "HT", "1T", "108", "32",
+	"MKK", "5G", "20M", "HT", "1T", "108", "33",
+	"IC", "5G", "20M", "HT", "1T", "108", "33",
+	"KCC", "5G", "20M", "HT", "1T", "108", "33",
+	"ACMA", "5G", "20M", "HT", "1T", "108", "32",
+	"CHILE", "5G", "20M", "HT", "1T", "108", "30",
+	"FCC", "5G", "20M", "HT", "1T", "112", "27",
+	"ETSI", "5G", "20M", "HT", "1T", "112", "32",
+	"MKK", "5G", "20M", "HT", "1T", "112", "33",
+	"IC", "5G", "20M", "HT", "1T", "112", "33",
+	"KCC", "5G", "20M", "HT", "1T", "112", "33",
+	"ACMA", "5G", "20M", "HT", "1T", "112", "32",
+	"CHILE", "5G", "20M", "HT", "1T", "112", "30",
+	"FCC", "5G", "20M", "HT", "1T", "116", "27",
+	"ETSI", "5G", "20M", "HT", "1T", "116", "32",
+	"MKK", "5G", "20M", "HT", "1T", "116", "33",
+	"IC", "5G", "20M", "HT", "1T", "116", "33",
+	"KCC", "5G", "20M", "HT", "1T", "116", "33",
+	"ACMA", "5G", "20M", "HT", "1T", "116", "32",
+	"CHILE", "5G", "20M", "HT", "1T", "116", "30",
+	"FCC", "5G", "20M", "HT", "1T", "120", "27",
+	"ETSI", "5G", "20M", "HT", "1T", "120", "32",
+	"MKK", "5G", "20M", "HT", "1T", "120", "33",
+	"IC", "5G", "20M", "HT", "1T", "120", "63",
+	"KCC", "5G", "20M", "HT", "1T", "120", "33",
+	"ACMA", "5G", "20M", "HT", "1T", "120", "32",
+	"CHILE", "5G", "20M", "HT", "1T", "120", "30",
+	"FCC", "5G", "20M", "HT", "1T", "124", "27",
+	"ETSI", "5G", "20M", "HT", "1T", "124", "32",
+	"MKK", "5G", "20M", "HT", "1T", "124", "33",
+	"IC", "5G", "20M", "HT", "1T", "124", "63",
+	"KCC", "5G", "20M", "HT", "1T", "124", "33",
+	"ACMA", "5G", "20M", "HT", "1T", "124", "32",
+	"CHILE", "5G", "20M", "HT", "1T", "124", "30",
+	"FCC", "5G", "20M", "HT", "1T", "128", "27",
+	"ETSI", "5G", "20M", "HT", "1T", "128", "32",
+	"MKK", "5G", "20M", "HT", "1T", "128", "33",
+	"IC", "5G", "20M", "HT", "1T", "128", "63",
+	"KCC", "5G", "20M", "HT", "1T", "128", "63",
+	"ACMA", "5G", "20M", "HT", "1T", "128", "32",
+	"CHILE", "5G", "20M", "HT", "1T", "128", "30",
+	"FCC", "5G", "20M", "HT", "1T", "132", "27",
+	"ETSI", "5G", "20M", "HT", "1T", "132", "32",
+	"MKK", "5G", "20M", "HT", "1T", "132", "33",
+	"IC", "5G", "20M", "HT", "1T", "132", "33",
+	"KCC", "5G", "20M", "HT", "1T", "132", "63",
+	"ACMA", "5G", "20M", "HT", "1T", "132", "32",
+	"CHILE", "5G", "20M", "HT", "1T", "132", "30",
+	"FCC", "5G", "20M", "HT", "1T", "136", "27",
+	"ETSI", "5G", "20M", "HT", "1T", "136", "32",
+	"MKK", "5G", "20M", "HT", "1T", "136", "33",
+	"IC", "5G", "20M", "HT", "1T", "136", "33",
+	"KCC", "5G", "20M", "HT", "1T", "136", "63",
+	"ACMA", "5G", "20M", "HT", "1T", "136", "32",
+	"CHILE", "5G", "20M", "HT", "1T", "136", "30",
+	"FCC", "5G", "20M", "HT", "1T", "140", "27",
+	"ETSI", "5G", "20M", "HT", "1T", "140", "32",
+	"MKK", "5G", "20M", "HT", "1T", "140", "33",
+	"IC", "5G", "20M", "HT", "1T", "140", "29",
+	"KCC", "5G", "20M", "HT", "1T", "140", "63",
+	"ACMA", "5G", "20M", "HT", "1T", "140", "32",
+	"CHILE", "5G", "20M", "HT", "1T", "140", "30",
+	"FCC", "5G", "20M", "HT", "1T", "144", "27",
+	"ETSI", "5G", "20M", "HT", "1T", "144", "63",
+	"MKK", "5G", "20M", "HT", "1T", "144", "63",
+	"IC", "5G", "20M", "HT", "1T", "144", "27",
+	"KCC", "5G", "20M", "HT", "1T", "144", "63",
+	"ACMA", "5G", "20M", "HT", "1T", "144", "63",
+	"CHILE", "5G", "20M", "HT", "1T", "144", "30",
+	"FCC", "5G", "20M", "HT", "1T", "149", "28",
+	"ETSI", "5G", "20M", "HT", "1T", "149", "63",
+	"MKK", "5G", "20M", "HT", "1T", "149", "63",
+	"IC", "5G", "20M", "HT", "1T", "149", "33",
+	"KCC", "5G", "20M", "HT", "1T", "149", "33",
+	"ACMA", "5G", "20M", "HT", "1T", "149", "33",
+	"CHILE", "5G", "20M", "HT", "1T", "149", "30",
+	"FCC", "5G", "20M", "HT", "1T", "153", "28",
+	"ETSI", "5G", "20M", "HT", "1T", "153", "63",
+	"MKK", "5G", "20M", "HT", "1T", "153", "63",
+	"IC", "5G", "20M", "HT", "1T", "153", "33",
+	"KCC", "5G", "20M", "HT", "1T", "153", "33",
+	"ACMA", "5G", "20M", "HT", "1T", "153", "33",
+	"CHILE", "5G", "20M", "HT", "1T", "153", "30",
+	"FCC", "5G", "20M", "HT", "1T", "157", "28",
+	"ETSI", "5G", "20M", "HT", "1T", "157", "63",
+	"MKK", "5G", "20M", "HT", "1T", "157", "63",
+	"IC", "5G", "20M", "HT", "1T", "157", "33",
+	"KCC", "5G", "20M", "HT", "1T", "157", "33",
+	"ACMA", "5G", "20M", "HT", "1T", "157", "33",
+	"CHILE", "5G", "20M", "HT", "1T", "157", "30",
+	"FCC", "5G", "20M", "HT", "1T", "161", "28",
+	"ETSI", "5G", "20M", "HT", "1T", "161", "63",
+	"MKK", "5G", "20M", "HT", "1T", "161", "63",
+	"IC", "5G", "20M", "HT", "1T", "161", "33",
+	"KCC", "5G", "20M", "HT", "1T", "161", "31",
+	"ACMA", "5G", "20M", "HT", "1T", "161", "33",
+	"CHILE", "5G", "20M", "HT", "1T", "161", "30",
+	"FCC", "5G", "20M", "HT", "1T", "165", "28",
+	"ETSI", "5G", "20M", "HT", "1T", "165", "63",
+	"MKK", "5G", "20M", "HT", "1T", "165", "63",
+	"IC", "5G", "20M", "HT", "1T", "165", "33",
+	"KCC", "5G", "20M", "HT", "1T", "165", "63",
+	"ACMA", "5G", "20M", "HT", "1T", "165", "33",
+	"CHILE", "5G", "20M", "HT", "1T", "165", "30",
+	"FCC", "5G", "40M", "HT", "1T", "38", "22",
+	"ETSI", "5G", "40M", "HT", "1T", "38", "32",
+	"MKK", "5G", "40M", "HT", "1T", "38", "32",
+	"IC", "5G", "40M", "HT", "1T", "38", "22",
+	"KCC", "5G", "40M", "HT", "1T", "38", "26",
+	"ACMA", "5G", "40M", "HT", "1T", "38", "32",
+	"CHILE", "5G", "40M", "HT", "1T", "38", "22",
+	"FCC", "5G", "40M", "HT", "1T", "46", "24",
+	"ETSI", "5G", "40M", "HT", "1T", "46", "32",
+	"MKK", "5G", "40M", "HT", "1T", "46", "32",
+	"IC", "5G", "40M", "HT", "1T", "46", "32",
+	"KCC", "5G", "40M", "HT", "1T", "46", "28",
+	"ACMA", "5G", "40M", "HT", "1T", "46", "32",
+	"CHILE", "5G", "40M", "HT", "1T", "46", "30",
+	"FCC", "5G", "40M", "HT", "1T", "54", "27",
+	"ETSI", "5G", "40M", "HT", "1T", "54", "32",
+	"MKK", "5G", "40M", "HT", "1T", "54", "32",
+	"IC", "5G", "40M", "HT", "1T", "54", "32",
+	"KCC", "5G", "40M", "HT", "1T", "54", "22",
+	"ACMA", "5G", "40M", "HT", "1T", "54", "32",
+	"CHILE", "5G", "40M", "HT", "1T", "54", "30",
+	"FCC", "5G", "40M", "HT", "1T", "62", "23",
+	"ETSI", "5G", "40M", "HT", "1T", "62", "32",
+	"MKK", "5G", "40M", "HT", "1T", "62", "32",
+	"IC", "5G", "40M", "HT", "1T", "62", "23",
+	"KCC", "5G", "40M", "HT", "1T", "62", "31",
+	"ACMA", "5G", "40M", "HT", "1T", "62", "32",
+	"CHILE", "5G", "40M", "HT", "1T", "62", "23",
+	"FCC", "5G", "40M", "HT", "1T", "102", "21",
+	"ETSI", "5G", "40M", "HT", "1T", "102", "32",
+	"MKK", "5G", "40M", "HT", "1T", "102", "32",
+	"IC", "5G", "40M", "HT", "1T", "102", "21",
+	"KCC", "5G", "40M", "HT", "1T", "102", "31",
+	"ACMA", "5G", "40M", "HT", "1T", "102", "32",
+	"CHILE", "5G", "40M", "HT", "1T", "102", "30",
+	"FCC", "5G", "40M", "HT", "1T", "110", "27",
+	"ETSI", "5G", "40M", "HT", "1T", "110", "32",
+	"MKK", "5G", "40M", "HT", "1T", "110", "32",
+	"IC", "5G", "40M", "HT", "1T", "110", "32",
+	"KCC", "5G", "40M", "HT", "1T", "110", "32",
+	"ACMA", "5G", "40M", "HT", "1T", "110", "32",
+	"CHILE", "5G", "40M", "HT", "1T", "110", "30",
+	"FCC", "5G", "40M", "HT", "1T", "118", "27",
+	"ETSI", "5G", "40M", "HT", "1T", "118", "32",
+	"MKK", "5G", "40M", "HT", "1T", "118", "32",
+	"IC", "5G", "40M", "HT", "1T", "118", "63",
+	"KCC", "5G", "40M", "HT", "1T", "118", "32",
+	"ACMA", "5G", "40M", "HT", "1T", "118", "32",
+	"CHILE", "5G", "40M", "HT", "1T", "118", "30",
+	"FCC", "5G", "40M", "HT", "1T", "126", "27",
+	"ETSI", "5G", "40M", "HT", "1T", "126", "32",
+	"MKK", "5G", "40M", "HT", "1T", "126", "32",
+	"IC", "5G", "40M", "HT", "1T", "126", "63",
+	"KCC", "5G", "40M", "HT", "1T", "126", "63",
+	"ACMA", "5G", "40M", "HT", "1T", "126", "32",
+	"CHILE", "5G", "40M", "HT", "1T", "126", "30",
+	"FCC", "5G", "40M", "HT", "1T", "134", "27",
+	"ETSI", "5G", "40M", "HT", "1T", "134", "32",
+	"MKK", "5G", "40M", "HT", "1T", "134", "32",
+	"IC", "5G", "40M", "HT", "1T", "134", "32",
+	"KCC", "5G", "40M", "HT", "1T", "134", "63",
+	"ACMA", "5G", "40M", "HT", "1T", "134", "32",
+	"CHILE", "5G", "40M", "HT", "1T", "134", "30",
+	"FCC", "5G", "40M", "HT", "1T", "142", "27",
+	"ETSI", "5G", "40M", "HT", "1T", "142", "63",
+	"MKK", "5G", "40M", "HT", "1T", "142", "63",
+	"IC", "5G", "40M", "HT", "1T", "142", "29",
+	"KCC", "5G", "40M", "HT", "1T", "142", "63",
+	"ACMA", "5G", "40M", "HT", "1T", "142", "63",
+	"CHILE", "5G", "40M", "HT", "1T", "142", "30",
+	"FCC", "5G", "40M", "HT", "1T", "151", "28",
+	"ETSI", "5G", "40M", "HT", "1T", "151", "63",
+	"MKK", "5G", "40M", "HT", "1T", "151", "63",
+	"IC", "5G", "40M", "HT", "1T", "151", "32",
+	"KCC", "5G", "40M", "HT", "1T", "151", "27",
+	"ACMA", "5G", "40M", "HT", "1T", "151", "32",
+	"CHILE", "5G", "40M", "HT", "1T", "151", "30",
+	"FCC", "5G", "40M", "HT", "1T", "159", "28",
+	"ETSI", "5G", "40M", "HT", "1T", "159", "63",
+	"MKK", "5G", "40M", "HT", "1T", "159", "63",
+	"IC", "5G", "40M", "HT", "1T", "159", "32",
+	"KCC", "5G", "40M", "HT", "1T", "159", "26",
+	"ACMA", "5G", "40M", "HT", "1T", "159", "32",
+	"CHILE", "5G", "40M", "HT", "1T", "159", "30",
+	"FCC", "5G", "80M", "VHT", "1T", "42", "19",
+	"ETSI", "5G", "80M", "VHT", "1T", "42", "32",
+	"MKK", "5G", "80M", "VHT", "1T", "42", "28",
+	"IC", "5G", "80M", "VHT", "1T", "42", "19",
+	"KCC", "5G", "80M", "VHT", "1T", "42", "25",
+	"ACMA", "5G", "80M", "VHT", "1T", "42", "32",
+	"CHILE", "5G", "80M", "VHT", "1T", "42", "19",
+	"FCC", "5G", "80M", "VHT", "1T", "58", "22",
+	"ETSI", "5G", "80M", "VHT", "1T", "58", "32",
+	"MKK", "5G", "80M", "VHT", "1T", "58", "28",
+	"IC", "5G", "80M", "VHT", "1T", "58", "22",
+	"KCC", "5G", "80M", "VHT", "1T", "58", "28",
+	"ACMA", "5G", "80M", "VHT", "1T", "58", "32",
+	"CHILE", "5G", "80M", "VHT", "1T", "58", "22",
+	"FCC", "5G", "80M", "VHT", "1T", "106", "18",
+	"ETSI", "5G", "80M", "VHT", "1T", "106", "32",
+	"MKK", "5G", "80M", "VHT", "1T", "106", "32",
+	"IC", "5G", "80M", "VHT", "1T", "106", "18",
+	"KCC", "5G", "80M", "VHT", "1T", "106", "30",
+	"ACMA", "5G", "80M", "VHT", "1T", "106", "32",
+	"CHILE", "5G", "80M", "VHT", "1T", "106", "30",
+	"FCC", "5G", "80M", "VHT", "1T", "122", "27",
+	"ETSI", "5G", "80M", "VHT", "1T", "122", "32",
+	"MKK", "5G", "80M", "VHT", "1T", "122", "32",
+	"IC", "5G", "80M", "VHT", "1T", "122", "63",
+	"KCC", "5G", "80M", "VHT", "1T", "122", "26",
+	"ACMA", "5G", "80M", "VHT", "1T", "122", "32",
+	"CHILE", "5G", "80M", "VHT", "1T", "122", "30",
+	"FCC", "5G", "80M", "VHT", "1T", "138", "27",
+	"ETSI", "5G", "80M", "VHT", "1T", "138", "63",
+	"MKK", "5G", "80M", "VHT", "1T", "138", "63",
+	"IC", "5G", "80M", "VHT", "1T", "138", "28",
+	"KCC", "5G", "80M", "VHT", "1T", "138", "63",
+	"ACMA", "5G", "80M", "VHT", "1T", "138", "63",
+	"CHILE", "5G", "80M", "VHT", "1T", "138", "30",
+	"FCC", "5G", "80M", "VHT", "1T", "155", "28",
+	"ETSI", "5G", "80M", "VHT", "1T", "155", "63",
+	"MKK", "5G", "80M", "VHT", "1T", "155", "63",
+	"IC", "5G", "80M", "VHT", "1T", "155", "32",
+	"KCC", "5G", "80M", "VHT", "1T", "155", "27",
+	"ACMA", "5G", "80M", "VHT", "1T", "155", "32",
+	"CHILE", "5G", "80M", "VHT", "1T", "155", "30"
+};
+
+void
+odm_read_and_config_mp_8821c_txpwr_lmt_fccsar(struct dm_struct *dm)
+{
+	u32	i = 0;
+#if (DM_ODM_SUPPORT_TYPE == ODM_IOT)
+	u32	array_len = sizeof(array_mp_8821c_txpwr_lmt_fccsar) / sizeof(u8);
+	u8	*array = (u8 *)array_mp_8821c_txpwr_lmt_fccsar;
+#else
+	u32	array_len = sizeof(array_mp_8821c_txpwr_lmt_fccsar) / sizeof(u8 *);
+	u8	**array = (u8 **)array_mp_8821c_txpwr_lmt_fccsar;
+#endif
+
+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
+	void	*adapter = dm->adapter;
+	HAL_DATA_TYPE	*hal_data = GET_HAL_DATA(((PADAPTER)adapter));
+
+	PlatformZeroMemory(hal_data->BufOfLinesPwrLmt, MAX_LINES_HWCONFIG_TXT * MAX_BYTES_LINE_HWCONFIG_TXT);
+	hal_data->nLinesReadPwrLmt = array_len / 7;
+#endif
+
+	PHYDM_DBG(dm, ODM_COMP_INIT, "===> %s\n", __func__);
+
+	for (i = 0; i < array_len; i += 7) {
+#if (DM_ODM_SUPPORT_TYPE == ODM_IOT)
+		u8	regulation = array[i];
+		u8	band = array[i + 1];
+		u8	bandwidth = array[i + 2];
+		u8	rate = array[i + 3];
+		u8	rf_path = array[i + 4];
+		u8	chnl = array[i + 5];
+		u8	val = array[i + 6];
+#else
+		u8	*regulation = array[i];
+		u8	*band = array[i + 1];
+		u8	*bandwidth = array[i + 2];
+		u8	*rate = array[i + 3];
+		u8	*rf_path = array[i + 4];
+		u8	*chnl = array[i + 5];
+		u8	*val = array[i + 6];
+#endif
+
+		odm_config_bb_txpwr_lmt_8821c(dm, regulation, band, bandwidth, rate, rf_path, chnl, val);
+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
+		rsprintf((char *)hal_data->BufOfLinesPwrLmt[i / 7], 100, "\"%s\", \"%s\", \"%s\", \"%s\", \"%s\", \"%s\", \"%s\",",
+		regulation, band, bandwidth, rate, rf_path, chnl, val);
+#endif
+	}
+}
+
+#endif /* end of HWIMG_SUPPORT*/
+
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/rtl8821c/halhwimg8821c_rf.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/rtl8821c/halhwimg8821c_rf.h
--- linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/rtl8821c/halhwimg8821c_rf.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/rtl8821c/halhwimg8821c_rf.h	2020-04-10 16:35:06.834660908 +0300
@@ -0,0 +1,90 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * The full GNU General Public License is included in this distribution in the
+ * file called LICENSE.
+ *
+ * Contact Information:
+ * wlanfae <wlanfae@realtek.com>
+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
+ * Hsinchu 300, Taiwan.
+ *
+ * Larry Finger <Larry.Finger@lwfinger.net>
+ *
+ *****************************************************************************/
+
+/*Image2HeaderVersion: R3 1.0*/
+#if (RTL8821C_SUPPORT == 1)
+#ifndef __INC_MP_RF_HW_IMG_8821C_H
+#define __INC_MP_RF_HW_IMG_8821C_H
+
+
+/******************************************************************************
+*                           radioa.TXT
+******************************************************************************/
+
+void
+odm_read_and_config_mp_8821c_radioa( /* tc: Test Chip, mp: mp Chip*/
+				    struct dm_struct *dm);
+u32 odm_get_version_mp_8821c_radioa(void);
+
+/******************************************************************************
+*                           txpowertrack.TXT
+******************************************************************************/
+
+void
+odm_read_and_config_mp_8821c_txpowertrack( /* tc: Test Chip, mp: mp Chip*/
+					  struct dm_struct *dm);
+u32	odm_get_version_mp_8821c_txpowertrack(void);
+
+/******************************************************************************
+*                           txpowertrack_type0x20.TXT
+******************************************************************************/
+
+void
+odm_read_and_config_mp_8821c_txpowertrack_type0x20(
+						   /* tc: Test Chip, mp: mp Chip*/
+						   struct dm_struct *dm);
+u32	odm_get_version_mp_8821c_txpowertrack_type0x20(void);
+
+/******************************************************************************
+*                           txpowertrack_type0x28.TXT
+******************************************************************************/
+
+void
+odm_read_and_config_mp_8821c_txpowertrack_type0x28(
+						   /* tc: Test Chip, mp: mp Chip*/
+						   struct dm_struct *dm);
+u32	odm_get_version_mp_8821c_txpowertrack_type0x28(void);
+
+/******************************************************************************
+*                           txpwr_lmt.TXT
+******************************************************************************/
+
+void
+odm_read_and_config_mp_8821c_txpwr_lmt( /* tc: Test Chip, mp: mp Chip*/
+				       struct dm_struct *dm);
+u32	odm_get_version_mp_8821c_txpwr_lmt(void);
+
+/******************************************************************************
+*                           txpwr_lmt_fccsar.TXT
+******************************************************************************/
+
+void
+odm_read_and_config_mp_8821c_txpwr_lmt_fccsar( /* tc: Test Chip, mp: mp Chip*/
+					      struct dm_struct *dm);
+u32	odm_get_version_mp_8821c_txpwr_lmt_fccsar(void);
+
+#endif
+#endif /* end of HWIMG_SUPPORT*/
+
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/rtl8821c/halhwimg8821c_testchip_bb.c linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/rtl8821c/halhwimg8821c_testchip_bb.c
--- linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/rtl8821c/halhwimg8821c_testchip_bb.c	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/rtl8821c/halhwimg8821c_testchip_bb.c	2020-04-10 16:35:06.834660908 +0300
@@ -0,0 +1,1925 @@
+/******************************************************************************
+*
+* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
+*
+* This program is free software; you can redistribute it and/or modify it
+* under the terms of version 2 of the GNU General Public License as
+* published by the Free Software Foundation.
+*
+* This program is distributed in the hope that it will be useful, but WITHOUT
+* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+* more details.
+*
+* You should have received a copy of the GNU General Public License along with
+* this program; if not, write to the Free Software Foundation, Inc.,
+* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
+*
+*
+******************************************************************************/
+
+/*Image2HeaderVersion: 2.22*/
+#include "mp_precomp.h"
+#include "../phydm_precomp.h"
+
+#if (RTL8821C_SUPPORT == 1)
+static boolean
+check_positive(
+	struct PHY_DM_STRUCT     *p_dm_odm,
+	const u32  condition1,
+	const u32  condition2,
+	const u32  condition3,
+	const u32  condition4
+)
+{
+	u8    _board_type = ((p_dm_odm->board_type & BIT(4)) >> 4) << 0 | /* _GLNA*/
+		    ((p_dm_odm->board_type & BIT(3)) >> 3) << 1 | /* _GPA*/
+		    ((p_dm_odm->board_type & BIT(7)) >> 7) << 2 | /* _ALNA*/
+		    ((p_dm_odm->board_type & BIT(6)) >> 6) << 3 | /* _APA */
+		    ((p_dm_odm->board_type & BIT(2)) >> 2) << 4;  /* _BT*/
+
+	u32	cond1   = condition1, cond2 = condition2, cond3 = condition3, cond4 = condition4;
+	u32    driver1 = p_dm_odm->cut_version       << 24 |
+			 (p_dm_odm->support_interface & 0xF0) << 16 |
+			 p_dm_odm->support_platform  << 16 |
+			 p_dm_odm->package_type      << 12 |
+			 (p_dm_odm->support_interface & 0x0F) << 8  |
+			 _board_type;
+
+	u32    driver2 = (p_dm_odm->type_glna & 0xFF) <<  0 |
+			 (p_dm_odm->type_gpa & 0xFF)  <<  8 |
+			 (p_dm_odm->type_alna & 0xFF) << 16 |
+			 (p_dm_odm->type_apa & 0xFF)  << 24;
+
+	u32    driver3 = 0;
+
+	u32    driver4 = (p_dm_odm->type_glna & 0xFF00) >>  8 |
+			 (p_dm_odm->type_gpa & 0xFF00) |
+			 (p_dm_odm->type_alna & 0xFF00) << 8 |
+			 (p_dm_odm->type_apa & 0xFF00)  << 16;
+
+	ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_TRACE,
+		("===> check_positive (cond1, cond2, cond3, cond4) = (0x%X 0x%X 0x%X 0x%X)\n", cond1, cond2, cond3, cond4));
+	ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_TRACE,
+		("===> check_positive (driver1, driver2, driver3, driver4) = (0x%X 0x%X 0x%X 0x%X)\n", driver1, driver2, driver3, driver4));
+
+	ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_TRACE,
+		("	(Platform, Interface) = (0x%X, 0x%X)\n", p_dm_odm->support_platform, p_dm_odm->support_interface));
+	ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_TRACE,
+		("	(Board, Package) = (0x%X, 0x%X)\n", p_dm_odm->board_type, p_dm_odm->package_type));
+
+
+	/*============== value Defined Check ===============*/
+	/*QFN type [15:12] and cut version [27:24] need to do value check*/
+
+	if (((cond1 & 0x0000F000) != 0) && ((cond1 & 0x0000F000) != (driver1 & 0x0000F000)))
+		return false;
+	if (((cond1 & 0x0F000000) != 0) && ((cond1 & 0x0F000000) != (driver1 & 0x0F000000)))
+		return false;
+
+	/*=============== Bit Defined Check ================*/
+	/* We don't care [31:28] */
+
+	cond1   &= 0x00FF0FFF;
+	driver1 &= 0x00FF0FFF;
+
+	if ((cond1 & driver1) == cond1) {
+		u32 bit_mask = 0;
+
+		if ((cond1 & 0x0F) == 0) /* board_type is DONTCARE*/
+			return true;
+
+		if ((cond1 & BIT(0)) != 0) /*GLNA*/
+			bit_mask |= 0x000000FF;
+		if ((cond1 & BIT(1)) != 0) /*GPA*/
+			bit_mask |= 0x0000FF00;
+		if ((cond1 & BIT(2)) != 0) /*ALNA*/
+			bit_mask |= 0x00FF0000;
+		if ((cond1 & BIT(3)) != 0) /*APA*/
+			bit_mask |= 0xFF000000;
+
+		if (((cond2 & bit_mask) == (driver2 & bit_mask)) && ((cond4 & bit_mask) == (driver4 & bit_mask)))  /* board_type of each RF path is matched*/
+			return true;
+		else
+			return false;
+	} else
+		return false;
+}
+static boolean
+check_negative(
+	struct PHY_DM_STRUCT     *p_dm_odm,
+	const u32  condition1,
+	const u32  condition2
+)
+{
+	return true;
+}
+
+/******************************************************************************
+*                           AGC_TAB.TXT
+******************************************************************************/
+
+u32 array_tc_8821c_agc_tab[] = {
+	0x81C, 0xFB000003,
+	0x81C, 0xFA020003,
+	0x81C, 0xF9040003,
+	0x81C, 0xF8060003,
+	0x81C, 0xF7080003,
+	0x81C, 0xF60A0003,
+	0x81C, 0xF50C0003,
+	0x81C, 0xF40E0003,
+	0x81C, 0xF3100003,
+	0x81C, 0xF2120003,
+	0x81C, 0xF1140003,
+	0x81C, 0xF0160003,
+	0x81C, 0xEF180003,
+	0x81C, 0xEE1A0003,
+	0x81C, 0xED1C0003,
+	0x81C, 0xEC1E0003,
+	0x81C, 0xEB200003,
+	0x81C, 0xEA220003,
+	0x81C, 0xE9240003,
+	0x81C, 0xE8260003,
+	0x81C, 0xE7280003,
+	0x81C, 0xE62A0003,
+	0x81C, 0xCA2C0003,
+	0x81C, 0xC92E0003,
+	0x81C, 0xC8300003,
+	0x81C, 0xC7320003,
+	0x81C, 0xC6340003,
+	0x81C, 0xC5360003,
+	0x81C, 0xC4380003,
+	0x81C, 0xC33A0003,
+	0x81C, 0xC23C0003,
+	0x81C, 0xC13E0003,
+	0x81C, 0x88400003,
+	0x81C, 0x87420003,
+	0x81C, 0x86440003,
+	0x81C, 0x85460003,
+	0x81C, 0x84480003,
+	0x81C, 0x834A0003,
+	0x81C, 0x674C0003,
+	0x81C, 0x664E0003,
+	0x81C, 0x65500003,
+	0x81C, 0x64520003,
+	0x81C, 0x63540003,
+	0x81C, 0x62560003,
+	0x81C, 0x61580003,
+	0x81C, 0x455A0003,
+	0x81C, 0x445C0003,
+	0x81C, 0x435E0003,
+	0x81C, 0x42600003,
+	0x81C, 0x41620003,
+	0x81C, 0x25640003,
+	0x81C, 0x24660003,
+	0x81C, 0x23680003,
+	0x81C, 0x226A0003,
+	0x81C, 0x216C0003,
+	0x81C, 0x016E0003,
+	0x81C, 0x01700003,
+	0x81C, 0x01720003,
+	0x81C, 0x01740003,
+	0x81C, 0x01760003,
+	0x81C, 0x01780003,
+	0x81C, 0x017A0003,
+	0x81C, 0x017C0003,
+	0x81C, 0x017E0003,
+	0x81C, 0xFF000103,
+	0x81C, 0xFF020103,
+	0x81C, 0xFF040103,
+	0x81C, 0xFE060103,
+	0x81C, 0xFD080103,
+	0x81C, 0xFC0A0103,
+	0x81C, 0xFB0C0103,
+	0x81C, 0xFA0E0103,
+	0x81C, 0xF9100103,
+	0x81C, 0xF8120103,
+	0x81C, 0xF7140103,
+	0x81C, 0xF6160103,
+	0x81C, 0xF5180103,
+	0x81C, 0xF41A0103,
+	0x81C, 0xF31C0103,
+	0x81C, 0xF21E0103,
+	0x81C, 0xF1200103,
+	0x81C, 0xF0220103,
+	0x81C, 0xEF240103,
+	0x81C, 0xEE260103,
+	0x81C, 0xED280103,
+	0x81C, 0xEC2A0103,
+	0x81C, 0xEB2C0103,
+	0x81C, 0xEA2E0103,
+	0x81C, 0xE9300103,
+	0x81C, 0xE8320103,
+	0x81C, 0xE7340103,
+	0x81C, 0xE6360103,
+	0x81C, 0xE5380103,
+	0x81C, 0xE43A0103,
+	0x81C, 0xC63C0103,
+	0x81C, 0xC53E0103,
+	0x81C, 0xC4400103,
+	0x81C, 0xC3420103,
+	0x81C, 0xC2440103,
+	0x81C, 0xC1460103,
+	0x81C, 0xA3480103,
+	0x81C, 0xA24A0103,
+	0x81C, 0xA14C0103,
+	0x81C, 0x834E0103,
+	0x81C, 0x82500103,
+	0x81C, 0x81520103,
+	0x81C, 0x64540103,
+	0x81C, 0x63560103,
+	0x81C, 0x62580103,
+	0x81C, 0x615A0103,
+	0x81C, 0x425C0103,
+	0x81C, 0x415E0103,
+	0x81C, 0x24600103,
+	0x81C, 0x23620103,
+	0x81C, 0x22640103,
+	0x81C, 0x21660103,
+	0x81C, 0x03680103,
+	0x81C, 0x026A0103,
+	0x81C, 0x016C0103,
+	0x81C, 0x016E0103,
+	0x81C, 0x01700103,
+	0x81C, 0x01720103,
+	0x81C, 0x01740103,
+	0x81C, 0x01760103,
+	0x81C, 0x01780103,
+	0x81C, 0x017A0103,
+	0x81C, 0x017C0103,
+	0x81C, 0x017E0103,
+	0x81C, 0xFF000203,
+	0x81C, 0xFF020203,
+	0x81C, 0xFE040203,
+	0x81C, 0xFD060203,
+	0x81C, 0xFC080203,
+	0x81C, 0xFB0A0203,
+	0x81C, 0xFA0C0203,
+	0x81C, 0xF90E0203,
+	0x81C, 0xF8100203,
+	0x81C, 0xF7120203,
+	0x81C, 0xF6140203,
+	0x81C, 0xF5160203,
+	0x81C, 0xF4180203,
+	0x81C, 0xF31A0203,
+	0x81C, 0xF21C0203,
+	0x81C, 0xF11E0203,
+	0x81C, 0xF0200203,
+	0x81C, 0xEF220203,
+	0x81C, 0xEE240203,
+	0x81C, 0xED260203,
+	0x81C, 0xEC280203,
+	0x81C, 0xEB2A0203,
+	0x81C, 0xEA2C0203,
+	0x81C, 0xE92E0203,
+	0x81C, 0xE8300203,
+	0x81C, 0xE7320203,
+	0x81C, 0xE6340203,
+	0x81C, 0xE5360203,
+	0x81C, 0xE4380203,
+	0x81C, 0xE33A0203,
+	0x81C, 0xE23C0203,
+	0x81C, 0xE13E0203,
+	0x81C, 0xC4400203,
+	0x81C, 0xC3420203,
+	0x81C, 0xC2440203,
+	0x81C, 0xC1460203,
+	0x81C, 0xA3480203,
+	0x81C, 0xA24A0203,
+	0x81C, 0xA14C0203,
+	0x81C, 0x834E0203,
+	0x81C, 0x82500203,
+	0x81C, 0x81520203,
+	0x81C, 0x64540203,
+	0x81C, 0x63560203,
+	0x81C, 0x62580203,
+	0x81C, 0x615A0203,
+	0x81C, 0x425C0203,
+	0x81C, 0x415E0203,
+	0x81C, 0x22600203,
+	0x81C, 0x21620203,
+	0x81C, 0x04640203,
+	0x81C, 0x03660203,
+	0x81C, 0x02680203,
+	0x81C, 0x016A0203,
+	0x81C, 0x016C0203,
+	0x81C, 0x016E0203,
+	0x81C, 0x01700203,
+	0x81C, 0x01720203,
+	0x81C, 0x01740203,
+	0x81C, 0x01760203,
+	0x81C, 0x01780203,
+	0x81C, 0x017A0203,
+	0x81C, 0x017C0203,
+	0x81C, 0x017E0203,
+	0x81C, 0xFF000303,
+	0x81C, 0xFF020303,
+	0x81C, 0xFE040303,
+	0x81C, 0xFD060303,
+	0x81C, 0xFC080303,
+	0x81C, 0xFB0A0303,
+	0x81C, 0xFA0C0303,
+	0x81C, 0xF90E0303,
+	0x81C, 0xF8100303,
+	0x81C, 0xF7120303,
+	0x81C, 0xF6140303,
+	0x81C, 0xF5160303,
+	0x81C, 0xF4180303,
+	0x81C, 0xF31A0303,
+	0x81C, 0xF21C0303,
+	0x81C, 0xF11E0303,
+	0x81C, 0xF0200303,
+	0x81C, 0xEF220303,
+	0x81C, 0xEE240303,
+	0x81C, 0xED260303,
+	0x81C, 0xEC280303,
+	0x81C, 0xEB2A0303,
+	0x81C, 0xEA2C0303,
+	0x81C, 0xE92E0303,
+	0x81C, 0xE8300303,
+	0x81C, 0xE7320303,
+	0x81C, 0xE6340303,
+	0x81C, 0xE5360303,
+	0x81C, 0xE4380303,
+	0x81C, 0xE33A0303,
+	0x81C, 0xE23C0303,
+	0x81C, 0xE13E0303,
+	0x81C, 0xC4400303,
+	0x81C, 0xC3420303,
+	0x81C, 0xC2440303,
+	0x81C, 0xC1460303,
+	0x81C, 0xA4480303,
+	0x81C, 0xA34A0303,
+	0x81C, 0xA24C0303,
+	0x81C, 0xA14E0303,
+	0x81C, 0x83500303,
+	0x81C, 0x82520303,
+	0x81C, 0x81540303,
+	0x81C, 0x64560303,
+	0x81C, 0x63580303,
+	0x81C, 0x625A0303,
+	0x81C, 0x615C0303,
+	0x81C, 0x425E0303,
+	0x81C, 0x41600303,
+	0x81C, 0x23620303,
+	0x81C, 0x22640303,
+	0x81C, 0x21660303,
+	0x81C, 0x03680303,
+	0x81C, 0x026A0303,
+	0x81C, 0x016C0303,
+	0x81C, 0x016E0303,
+	0x81C, 0x01700303,
+	0x81C, 0x01720303,
+	0x81C, 0x01740303,
+	0x81C, 0x01760303,
+	0x81C, 0x01780303,
+	0x81C, 0x017A0303,
+	0x81C, 0x017C0303,
+	0x81C, 0x017E0303,
+	0x81C, 0xFB000403,
+	0x81C, 0xFA020403,
+	0x81C, 0xF9040403,
+	0x81C, 0xF8060403,
+	0x81C, 0xF7080403,
+	0x81C, 0xF60A0403,
+	0x81C, 0xF50C0403,
+	0x81C, 0xF40E0403,
+	0x81C, 0xF3100403,
+	0x81C, 0xF2120403,
+	0x81C, 0xF1140403,
+	0x81C, 0xF0160403,
+	0x81C, 0xEF180403,
+	0x81C, 0xEE1A0403,
+	0x81C, 0xED1C0403,
+	0x81C, 0xB61E0403,
+	0x81C, 0xB5200403,
+	0x81C, 0xB4220403,
+	0x81C, 0xB3240403,
+	0x81C, 0xB2260403,
+	0x81C, 0xB1280403,
+	0x81C, 0xAF2A0403,
+	0x81C, 0xAE2C0403,
+	0x81C, 0xAD2E0403,
+	0x81C, 0xAC300403,
+	0x81C, 0xAB320403,
+	0x81C, 0xAA340403,
+	0x81C, 0xA9360403,
+	0x81C, 0xA8380403,
+	0x81C, 0xA73A0403,
+	0x81C, 0xA63C0403,
+	0x81C, 0xA53E0403,
+	0x81C, 0x88400403,
+	0x81C, 0x87420403,
+	0x81C, 0x86440403,
+	0x81C, 0x85460403,
+	0x81C, 0x84480403,
+	0x81C, 0x834A0403,
+	0x81C, 0x674C0403,
+	0x81C, 0x664E0403,
+	0x81C, 0x65500403,
+	0x81C, 0x64520403,
+	0x81C, 0x63540403,
+	0x81C, 0x62560403,
+	0x81C, 0x61580403,
+	0x81C, 0x455A0403,
+	0x81C, 0x445C0403,
+	0x81C, 0x435E0403,
+	0x81C, 0x42600403,
+	0x81C, 0x41620403,
+	0x81C, 0x25640403,
+	0x81C, 0x24660403,
+	0x81C, 0x23680403,
+	0x81C, 0x226A0403,
+	0x81C, 0x216C0403,
+	0x81C, 0x016E0403,
+	0x81C, 0x01700403,
+	0x81C, 0x01720403,
+	0x81C, 0x01740403,
+	0x81C, 0x01760403,
+	0x81C, 0x01780403,
+	0x81C, 0x017A0403,
+	0x81C, 0x017C0403,
+	0x81C, 0x017E0403,
+	0xC50, 0x00000022,
+	0xC50, 0x00000020,
+
+};
+
+void
+odm_read_and_config_tc_8821c_agc_tab(
+	struct PHY_DM_STRUCT  *p_dm_odm
+)
+{
+	u32     i         = 0;
+	u8     c_cond;
+	boolean is_matched = true, is_skipped = false;
+	u32     array_len    = sizeof(array_tc_8821c_agc_tab) / sizeof(u32);
+	u32    *array       = array_tc_8821c_agc_tab;
+
+	u32	v1 = 0, v2 = 0, pre_v1 = 0, pre_v2 = 0;
+
+	ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> odm_read_and_config_tc_8821c_agc_tab\n"));
+
+	while ((i + 1) < array_len) {
+		v1 = array[i];
+		v2 = array[i + 1];
+
+		if (v1 & (BIT(31) | BIT30)) {/*positive & negative condition*/
+			if (v1 & BIT(31)) {/* positive condition*/
+				c_cond  = (u8)((v1 & (BIT(29) | BIT(28))) >> 28);
+				if (c_cond == COND_ENDIF) {/*end*/
+					is_matched = true;
+					is_skipped = false;
+					ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ENDIF\n"));
+				} else if (c_cond == COND_ELSE) { /*else*/
+					is_matched = is_skipped ? false : true;
+					ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ELSE\n"));
+				} else {/*if , else if*/
+					pre_v1 = v1;
+					pre_v2 = v2;
+					ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("IF or ELSE IF\n"));
+				}
+			} else if (v1 & BIT(30)) { /*negative condition*/
+				if (is_skipped == false) {
+					if (check_positive(p_dm_odm, pre_v1, pre_v2, v1, v2)) {
+						is_matched = true;
+						is_skipped = true;
+					} else {
+						is_matched = false;
+						is_skipped = false;
+					}
+				} else
+					is_matched = false;
+			}
+		} else {
+			if (is_matched)
+				odm_config_bb_agc_8821c(p_dm_odm, v1, MASKDWORD, v2);
+		}
+		i = i + 2;
+	}
+}
+
+u32
+odm_get_version_tc_8821c_agc_tab(void)
+{
+	return 9;
+}
+
+/******************************************************************************
+*                           PHY_REG.TXT
+******************************************************************************/
+
+u32 array_tc_8821c_phy_reg[] = {
+	0x800, 0x9020D010,
+	0x804, 0x80018180,
+	0x808, 0x04028211,
+	0x80C, 0x13D10011,
+	0x810, 0x21101263,
+	0x814, 0x020C3D10,
+	0x818, 0x84A10385,
+	0x81C, 0x1E1E081F,
+	0x820, 0x0001AAAA,
+	0x824, 0x00030FE0,
+	0x828, 0x0000CCCC,
+	0x82C, 0x75CB7010,
+	0x830, 0x79A0EA2A,
+	0x834, 0x072E6986,
+	0x838, 0x87766461,
+	0x83C, 0x9194B2B6,
+	0x840, 0x171740E0,
+	0x844, 0x4D3D7CDB,
+	0x848, 0x4AD0408B,
+	0x84C, 0x6AFBF7A5,
+	0x850, 0x28A74706,
+	0x854, 0x0001520C,
+	0x858, 0x4060C000,
+	0x85C, 0x74010360,
+	0x860, 0x68A7C321,
+	0x864, 0x79F27432,
+	0x868, 0x8CA7A314,
+	0x86C, 0x778C2878,
+	0x870, 0x77777777,
+	0x874, 0x27612C2E,
+	0x878, 0xC0003152,
+	0x87C, 0x5C8FC000,
+	0x880, 0x00000000,
+	0x884, 0x00000000,
+	0x888, 0x00000000,
+	0x88C, 0x00000000,
+	0x890, 0x00000000,
+	0x894, 0x00000000,
+	0x898, 0x00000000,
+	0x89C, 0x00000000,
+	0x8A0, 0x00000013,
+	0x8A4, 0x7F7F7F7F,
+	0x8A8, 0x2202033E,
+	0x8AC, 0xF00F000A,
+	0x8B0, 0x00000600,
+	0x8B4, 0x000FC080,
+	0x8B8, 0xEC0057FF,
+	0x8BC, 0xACB520A3,
+	0x8C0, 0xFFE04020,
+	0x8C4, 0x47C00000,
+	0x8C8, 0x000251A5,
+	0x8CC, 0x08108492,
+	0x8D0, 0x0000B800,
+	0x8D4, 0x860308A0,
+	0x8D8, 0x290B5612,
+	0x8DC, 0x00000000,
+	0x8E0, 0x32D16777,
+	0x8E4, 0x49092925,
+	0x8E8, 0xFFFFC42C,
+	0x8EC, 0x99999999,
+	0x8F0, 0x00009999,
+	0x8F4, 0x00D80FA1,
+	0x8F8, 0x400000C0,
+	0x8FC, 0x00000130,
+	0x900, 0x00C00000,
+	0x904, 0x0FFF0FFF,
+	0x908, 0x00000000,
+	0x90C, 0x13000000,
+	0x910, 0x0000FC00,
+	0x914, 0xC6380000,
+	0x918, 0x1C1028C0,
+	0x91C, 0x64B11A1C,
+	0x920, 0xE0767233,
+	0x924, 0x055A2500,
+	0x928, 0x4AB0E4E4,
+	0x92C, 0xFFFEB200,
+	0x930, 0xFFFFFFFE,
+	0x934, 0x001FFFFF,
+	0x938, 0x00008480,
+	0x93C, 0xE41C0642,
+	0x940, 0x0E470430,
+	0x944, 0x00000000,
+	0x948, 0xAC000000,
+	0x94C, 0x10000083,
+	0x950, 0xF2010080,
+	0x954, 0x86510080,
+	0x958, 0x00000001,
+	0x95C, 0x04248000,
+	0x960, 0x00000000,
+	0x964, 0x00000000,
+	0x968, 0x00000000,
+	0x96C, 0x00000000,
+	0x970, 0x00001FFF,
+	0x974, 0x04000FFF,
+	0x978, 0x00000000,
+	0x97C, 0x00000000,
+	0x980, 0x00000000,
+	0x984, 0x00000000,
+	0x988, 0x00000000,
+	0x98C, 0x23440000,
+	0x990, 0x27100000,
+	0x994, 0xFFFF0100,
+	0x998, 0xFFFFFF5C,
+	0x99C, 0xFFFFFFFF,
+	0x9A0, 0x000000FF,
+	0x9A4, 0x80000088,
+	0x9A8, 0x0C2F0000,
+	0x9AC, 0x01560000,
+	0x9B0, 0x70000000,
+	0x9B4, 0x00000000,
+	0x9B8, 0x00000000,
+	0x9BC, 0x00000000,
+	0x9C0, 0x00000000,
+	0x9C4, 0x00000000,
+	0x9C8, 0x00000000,
+	0x9CC, 0x00000000,
+	0x9D0, 0x00000000,
+	0x9D4, 0x00000000,
+	0x9D8, 0x00000000,
+	0x9DC, 0x00000000,
+	0x9E0, 0x00000000,
+	0x9E4, 0x02000402,
+	0x9E8, 0x000022D4,
+	0x9EC, 0x00000000,
+	0x9F0, 0x00000000,
+	0x9F4, 0x00000000,
+	0x9F8, 0x00000000,
+	0x9FC, 0xEFFFF7FF,
+	0xA00, 0x00D047C8,
+	0xA04, 0x80FF800C,
+	0xA08, 0x9C838300,
+	0xA0C, 0x2E20200F,
+	0xA10, 0x9500BB78,
+	0xA14, 0x1114D028,
+	0xA18, 0x00881117,
+	0xA1C, 0x89140F00,
+	0xA20, 0xE82C0000,
+	0xA24, 0x64B80C1C,
+	0xA28, 0x00008810,
+	0xA2C, 0x00D20000,
+	0xA70, 0x101FBF00,
+	0xA74, 0x00000107,
+	0xA78, 0x00008900,
+	0xA7C, 0x225B0606,
+	0xA80, 0x21807532,
+	0xA84, 0x80200000,
+	0xA88, 0x048C0000,
+	0xA8C, 0x12345678,
+	0xA90, 0xABCDEF00,
+	0xA94, 0x001B1B89,
+	0xA98, 0x00000000,
+	0xA9C, 0x00060000,
+	0xAA0, 0x00000000,
+	0xAA4, 0x00040000,
+	0xAA8, 0xEACF0004,
+	0xAAC, 0x01235667,
+	0xAB0, 0x00000000,
+	0xB00, 0xE1000440,
+	0xB04, 0x00800000,
+	0xB08, 0xFF02030B,
+	0xB0C, 0x01EAA406,
+	0xB10, 0x00030690,
+	0xB14, 0x006000FA,
+	0xB18, 0x00000002,
+	0xB1C, 0x00000002,
+	0xB20, 0x4B00001F,
+	0xB24, 0x4E8E3E40,
+	0xB28, 0x03020100,
+	0xB2C, 0x07060504,
+	0xB30, 0x0B0A0908,
+	0xB34, 0x0F0E0D0C,
+	0xB38, 0x13121110,
+	0xB3C, 0x0000003A,
+	0xB40, 0x00000000,
+	0xB44, 0x80000000,
+	0xB48, 0x3F0000FA,
+	0xB4C, 0x88C80020,
+	0xB50, 0x00000000,
+	0xB54, 0x00004241,
+	0xB58, 0xE0008208,
+	0xB5C, 0x41EFFFF9,
+	0xB60, 0x00000000,
+	0xB64, 0x00200063,
+	0xB68, 0x0000003A,
+	0xB6C, 0x00000102,
+	0xB70, 0x4E6D1870,
+	0xB74, 0x03020100,
+	0xB78, 0x07060504,
+	0xB7C, 0x0B0A0908,
+	0xB80, 0x0F0E0D0C,
+	0xB84, 0x13121110,
+	0xB88, 0x00000000,
+	0xB8C, 0x00000000,
+	0xC00, 0x00000007,
+	0xC04, 0x03000020,
+	0xC08, 0x60403231,
+	0xC0C, 0x00012345,
+	0xC10, 0x00000100,
+	0xC14, 0x01000000,
+	0xC18, 0x00000000,
+	0xC1C, 0x40040053,
+	0xC20, 0x000503A3,
+	0xC24, 0x00000000,
+	0xC28, 0x00000000,
+	0xC2C, 0x00000000,
+	0xC30, 0x00000000,
+	0xC34, 0x00000000,
+	0xC38, 0x00000000,
+	0xC3C, 0x00000000,
+	0xC40, 0x00000000,
+	0xC44, 0x00000000,
+	0xC48, 0x00000000,
+	0xC4C, 0x00000000,
+	0xC50, 0x00000020,
+	0xC54, 0x00000000,
+	0xC58, 0xD8020402,
+	0xC5C, 0xDE000120,
+	0xC68, 0x00000179,
+	0xC6C, 0x0000122A,
+	0xC70, 0x00000000,
+	0xC74, 0x00000000,
+	0xC78, 0x00000000,
+	0xC7C, 0x00000000,
+	0xC80, 0x00000000,
+	0xC84, 0x00000000,
+	0xC88, 0x00000000,
+	0xC8C, 0x07000000,
+	0xC94, 0x01000100,
+	0xC98, 0x201C8000,
+	0xC9C, 0x00000000,
+	0xCA0, 0x0000A555,
+	0xCA4, 0x08040201,
+	0xCA8, 0x80402010,
+	0xCAC, 0x00000000,
+	0xCB0, 0x98543210,
+	0xCB4, 0x10000077,
+	0xCB8, 0x00000000,
+	0xCBC, 0x00000000,
+	0xCC0, 0x00000000,
+	0xCC4, 0x00000000,
+	0xCC8, 0x00000000,
+	0xCCC, 0x00000000,
+	0xCD0, 0x00000000,
+	0xCD4, 0x00000000,
+	0xCD8, 0x00000000,
+	0xCDC, 0x00000000,
+	0xCE0, 0x00000000,
+	0xCE4, 0x00000000,
+	0xCE8, 0x00000000,
+	0xCEC, 0x00000000,
+	0xE00, 0x00000007,
+	0xE04, 0x00000020,
+	0xE08, 0x60403231,
+	0xE0C, 0x00012345,
+	0xE10, 0x00000100,
+	0xE14, 0x01000000,
+	0xE18, 0x00000000,
+	0xE1C, 0x40040053,
+	0xE20, 0x00020103,
+	0xE24, 0x00000000,
+	0xE28, 0x00000000,
+	0xE2C, 0x00000000,
+	0xE30, 0x00000000,
+	0xE34, 0x00000000,
+	0xE38, 0x00000000,
+	0xE3C, 0x00000000,
+	0xE40, 0x00000000,
+	0xE44, 0x00000000,
+	0xE48, 0x00000000,
+	0xE4C, 0x00000000,
+	0xE50, 0x00000020,
+	0xE54, 0x00000000,
+	0xE58, 0xD8020402,
+	0xE5C, 0xDE000120,
+	0xE68, 0x59799979,
+	0xE6C, 0x0000122A,
+	0xE70, 0x99795979,
+	0xE74, 0x99795979,
+	0xE78, 0x99799979,
+	0xE7C, 0x99791979,
+	0xE80, 0x19791979,
+	0xE84, 0x19791979,
+	0xE88, 0x00000000,
+	0xE8C, 0x07000000,
+	0xE94, 0x01000100,
+	0xE98, 0x201C8000,
+	0xE9C, 0x00000000,
+	0xEA0, 0x0000A555,
+	0xEA4, 0x08040201,
+	0xEA8, 0x80402010,
+	0xEAC, 0x00000000,
+	0xEB0, 0x98543210,
+	0xEB4, 0x000000BA,
+	0xEB8, 0x00000000,
+	0xEBC, 0x00000000,
+	0xEC0, 0x00000000,
+	0xEC4, 0x00000000,
+	0xEC8, 0x00000000,
+	0xECC, 0x00000000,
+	0xED0, 0x00000000,
+	0xED4, 0x00000000,
+	0xED8, 0x00000000,
+	0xEDC, 0x00000000,
+	0xEE0, 0x00000000,
+	0xEE4, 0x00000000,
+	0xEE8, 0x00000000,
+	0xEEC, 0x00000000,
+	0x1900, 0x00000000,
+	0x1904, 0x00238000,
+	0x1908, 0x00000000,
+	0x190C, 0x00000000,
+	0x1910, 0x00000000,
+	0x1914, 0x00000000,
+	0x1918, 0x00000000,
+	0x191C, 0x00000000,
+	0x1920, 0x00000000,
+	0x1924, 0x00000000,
+	0x1928, 0x00000000,
+	0x192C, 0x00000000,
+	0x1930, 0x00000000,
+	0x1934, 0x00000000,
+	0x1938, 0x00000000,
+	0x193C, 0x00000000,
+	0x1940, 0x00000000,
+	0x1944, 0x00000000,
+	0x1948, 0x00000000,
+	0x194C, 0x00000000,
+	0x1950, 0x00000000,
+	0x1954, 0x00000000,
+	0x1958, 0x00000000,
+	0x195C, 0x00000000,
+	0x1960, 0x00000000,
+	0x1964, 0x00000000,
+	0x1968, 0x00000000,
+	0x196C, 0x00000000,
+	0x1970, 0x00000000,
+	0x1974, 0x00000000,
+	0x1978, 0x00000000,
+	0x197C, 0x00000000,
+	0x1980, 0x00000000,
+	0x1984, 0x03000000,
+	0x1988, 0x21401E88,
+	0x198C, 0x00004000,
+	0x1990, 0x00000000,
+	0x1994, 0x00000000,
+	0x1998, 0x00000053,
+	0x199C, 0x00000000,
+	0x19A0, 0x00000000,
+	0x19A4, 0x00000000,
+	0x19A8, 0x00000000,
+	0x19AC, 0x0E47E47F,
+	0x19B0, 0x00000000,
+	0x19B4, 0x0E47E47F,
+	0x19B8, 0x00000000,
+	0x19BC, 0x00000000,
+	0x19C0, 0x00000000,
+	0x19C4, 0x00000000,
+	0x19C8, 0x00000000,
+	0x19CC, 0x00000000,
+	0x19D0, 0x00000000,
+	0x19D4, 0x77777777,
+	0x19D8, 0x00000777,
+	0x19DC, 0x133E0F37,
+	0x19E0, 0x00000000,
+	0x19E4, 0x00000000,
+	0x19E8, 0x00000000,
+	0x19EC, 0x00000000,
+	0x19F0, 0x00000000,
+	0x19F4, 0x00000000,
+	0x19F8, 0x01A00000,
+	0x19FC, 0x00000000,
+	0x1C00, 0x00000100,
+	0x1C04, 0x01000000,
+	0x1C08, 0x00000100,
+	0x1C0C, 0x01000000,
+	0x1C10, 0x00000100,
+	0x1C14, 0x01000000,
+	0x1C18, 0x00000100,
+	0x1C1C, 0x01000000,
+	0x1C20, 0x00000100,
+	0x1C24, 0x01000000,
+	0x1C28, 0x00000100,
+	0x1C2C, 0x01000000,
+	0x1C30, 0x00000100,
+	0x1C34, 0x01000000,
+	0x1C38, 0x00000000,
+	0x1C3C, 0x00000000,
+	0x1C40, 0x000C0100,
+	0x1C44, 0x000000F3,
+	0x1C48, 0x1A8249A8,
+	0x1C4C, 0x1461C826,
+	0x1C50, 0x0001469E,
+	0x1C54, 0x58D158D1,
+	0x1C58, 0x04490088,
+	0x1C5C, 0x04004400,
+	0x1C60, 0x00000000,
+	0x1C64, 0x04004400,
+	0x1C68, 0x00000100,
+	0x1C6C, 0x01000000,
+	0x1C70, 0x00A018C6,
+	0x1C74, 0x2080E0C0,
+	0x1C78, 0x00000000,
+	0x1C7C, 0x00000010,
+	0x1C80, 0x00000100,
+	0x1C84, 0x01000000,
+	0x1C88, 0x00000100,
+	0x1C8C, 0x01000000,
+	0x1C90, 0x00000100,
+	0x1C94, 0x01000000,
+	0x1C98, 0x00000100,
+	0x1C9C, 0x01000000,
+	0x1CA0, 0x00000100,
+	0x1CA4, 0x01000000,
+	0x1CA8, 0x00000100,
+	0x1CAC, 0x01000000,
+	0x1CB0, 0x00000100,
+	0x1CB4, 0x01000000,
+	0x1CB8, 0x00000000,
+	0x1CBC, 0x00000000,
+	0x1CC0, 0x50055100,
+	0x1CC4, 0x06318000,
+	0x1CC8, 0x5B75B6EB,
+	0x1CCC, 0x01000000,
+	0x1CD0, 0x00000100,
+	0x1CD4, 0x01000014,
+	0x1CD8, 0x00000100,
+	0x1CDC, 0x01000000,
+	0x1CE0, 0x02050205,
+	0x1CE4, 0x7B780003,
+	0x1CE8, 0x00000100,
+	0x1CEC, 0x01000000,
+	0x1CF0, 0x00000100,
+	0x1CF4, 0x01000000,
+	0x1CF8, 0x01B8ADEB,
+	0x1CFC, 0x00000000,
+	0xC60, 0x700B8040,
+	0xC60, 0x700B8040,
+	0xC60, 0x70146040,
+	0xC60, 0x70246040,
+	0xC60, 0x70346040,
+	0xC60, 0x70446040,
+	0xC60, 0x705B2040,
+	0xC60, 0x70646040,
+	0xC60, 0x707B8040,
+	0xC60, 0x708B8040,
+	0xC60, 0x709B8040,
+	0xC60, 0x70AB8040,
+	0xC60, 0x70BB6040,
+	0xC60, 0x70C06040,
+	0xC60, 0x70D06040,
+	0xC60, 0x70EF6040,
+	0xC60, 0x70F06040,
+	0xE60, 0x700B8040,
+	0xE60, 0x700B8040,
+	0xE60, 0x70146040,
+	0xE60, 0x70246040,
+	0xE60, 0x70346040,
+	0xE60, 0x70446040,
+	0xE60, 0x705B2040,
+	0xE60, 0x70646040,
+	0xE60, 0x707B8040,
+	0xE60, 0x708B8040,
+	0xE60, 0x709B8040,
+	0xE60, 0x70AB8040,
+	0xE60, 0x70BB6040,
+	0xE60, 0x70C06040,
+	0xE60, 0x70D06040,
+	0xE60, 0x70EF6040,
+	0xE60, 0x70F06040,
+	0xC64, 0x00800000,
+	0xC64, 0x08800001,
+	0xC64, 0x00800002,
+	0xC64, 0x00800003,
+	0xC64, 0x00800004,
+	0xC64, 0x00800005,
+	0xC64, 0x00800006,
+	0xC64, 0x08800007,
+	0xC64, 0x00004000,
+	0xE64, 0x00800000,
+	0xE64, 0x08800001,
+	0xE64, 0x00800002,
+	0xE64, 0x00800003,
+	0xE64, 0x00800004,
+	0xE64, 0x00800005,
+	0xE64, 0x00800006,
+	0xE64, 0x08800007,
+	0xE64, 0x00004000,
+	0x1B00, 0xF8000008,
+	0x1B00, 0xF80A7008,
+	0x1B00, 0xF8015008,
+	0x1B00, 0xF8000008,
+	0x1B04, 0xE24629D2,
+	0x1B08, 0x00000080,
+	0x1B0C, 0x00000000,
+	0x1B10, 0x00010C00,
+	0x1B14, 0x00000000,
+	0x1B18, 0x00292903,
+	0x1B1C, 0xA2193C32,
+	0x1B20, 0x01840008,
+	0x1B24, 0x01860008,
+	0x1B28, 0x80060300,
+	0x1B2C, 0x00000003,
+	0x1B30, 0x20000000,
+	0x1B34, 0x00000800,
+	0x1B3C, 0x20000000,
+	0x1BC0, 0x01000000,
+	0x1BCC, 0x00000000,
+	0x1B00, 0xF800000A,
+	0x1B1C, 0xA2193C32,
+	0x1B20, 0x01840008,
+	0x1B24, 0x01860008,
+	0x1B28, 0x80060300,
+	0x1B2C, 0x00000003,
+	0x1B30, 0x20000000,
+	0x1B34, 0x00000800,
+	0x1B3C, 0x20000000,
+	0x1BC0, 0x01000000,
+	0x1BCC, 0x00000000,
+	0x1B00, 0xF8000008,
+	0x1B80, 0x00000007,
+	0x1B80, 0x090A0005,
+	0x1B80, 0x090A0007,
+	0x1B80, 0x0FFE0015,
+	0x1B80, 0x0FFE0017,
+	0x1B80, 0x00220025,
+	0x1B80, 0x00220027,
+	0x1B80, 0x00040035,
+	0x1B80, 0x00040037,
+	0x1B80, 0x05C00045,
+	0x1B80, 0x05C00047,
+	0x1B80, 0x00070055,
+	0x1B80, 0x00070057,
+	0x1B80, 0x64000065,
+	0x1B80, 0x64000067,
+	0x1B80, 0x00020075,
+	0x1B80, 0x00020077,
+	0x1B80, 0x00080085,
+	0x1B80, 0x00080087,
+	0x1B80, 0x80000095,
+	0x1B80, 0x80000097,
+	0x1B80, 0x090800A5,
+	0x1B80, 0x090800A7,
+	0x1B80, 0x0F0200B5,
+	0x1B80, 0x0F0200B7,
+	0x1B80, 0x002200C5,
+	0x1B80, 0x002200C7,
+	0x1B80, 0x000400D5,
+	0x1B80, 0x000400D7,
+	0x1B80, 0x05C000E5,
+	0x1B80, 0x05C000E7,
+	0x1B80, 0x000700F5,
+	0x1B80, 0x000700F7,
+	0x1B80, 0x64020105,
+	0x1B80, 0x64020107,
+	0x1B80, 0x00020115,
+	0x1B80, 0x00020117,
+	0x1B80, 0x00040125,
+	0x1B80, 0x00040127,
+	0x1B80, 0x4A000135,
+	0x1B80, 0x4A000137,
+	0x1B80, 0x4B040145,
+	0x1B80, 0x4B040147,
+	0x1B80, 0x85030155,
+	0x1B80, 0x85030157,
+	0x1B80, 0x40090165,
+	0x1B80, 0x40090167,
+	0x1B80, 0xE0210175,
+	0x1B80, 0xE0210177,
+	0x1B80, 0x4B050185,
+	0x1B80, 0x4B050187,
+	0x1B80, 0x86030195,
+	0x1B80, 0x86030197,
+	0x1B80, 0x400B01A5,
+	0x1B80, 0x400B01A7,
+	0x1B80, 0xE02101B5,
+	0x1B80, 0xE02101B7,
+	0x1B80, 0x4B0001C5,
+	0x1B80, 0x4B0001C7,
+	0x1B80, 0x000701D5,
+	0x1B80, 0x000701D7,
+	0x1B80, 0x4C0001E5,
+	0x1B80, 0x4C0001E7,
+	0x1B80, 0x000401F5,
+	0x1B80, 0x000401F7,
+	0x1B80, 0x30000205,
+	0x1B80, 0x30000207,
+	0x1B80, 0xFE160215,
+	0x1B80, 0xFE160217,
+	0x1B80, 0xFF160225,
+	0x1B80, 0xFF160227,
+	0x1B80, 0xE1670235,
+	0x1B80, 0xE1670237,
+	0x1B80, 0xF00A0245,
+	0x1B80, 0xF00A0247,
+	0x1B80, 0xF10A0255,
+	0x1B80, 0xF10A0257,
+	0x1B80, 0xF20A0265,
+	0x1B80, 0xF20A0267,
+	0x1B80, 0xF30A0275,
+	0x1B80, 0xF30A0277,
+	0x1B80, 0xF40A0285,
+	0x1B80, 0xF40A0287,
+	0x1B80, 0xF50A0295,
+	0x1B80, 0xF50A0297,
+	0x1B80, 0xF60A02A5,
+	0x1B80, 0xF60A02A7,
+	0x1B80, 0xF70A02B5,
+	0x1B80, 0xF70A02B7,
+	0x1B80, 0xF80A02C5,
+	0x1B80, 0xF80A02C7,
+	0x1B80, 0x000102D5,
+	0x1B80, 0x000102D7,
+	0x1B80, 0x303902E5,
+	0x1B80, 0x303902E7,
+	0x1B80, 0x305102F5,
+	0x1B80, 0x305102F7,
+	0x1B80, 0x309C0305,
+	0x1B80, 0x309C0307,
+	0x1B80, 0x30530315,
+	0x1B80, 0x30530317,
+	0x1B80, 0x305E0325,
+	0x1B80, 0x305E0327,
+	0x1B80, 0x30690335,
+	0x1B80, 0x30690337,
+	0x1B80, 0x30A00345,
+	0x1B80, 0x30A00347,
+	0x1B80, 0x30AF0355,
+	0x1B80, 0x30AF0357,
+	0x1B80, 0x30BA0365,
+	0x1B80, 0x30BA0367,
+	0x1B80, 0x30ED0375,
+	0x1B80, 0x30ED0377,
+	0x1B80, 0x30F00385,
+	0x1B80, 0x30F00387,
+	0x1B80, 0xE1060395,
+	0x1B80, 0xE1060397,
+	0x1B80, 0x4D0403A5,
+	0x1B80, 0x4D0403A7,
+	0x1B80, 0x208003B5,
+	0x1B80, 0x208003B7,
+	0x1B80, 0x000003C5,
+	0x1B80, 0x000003C7,
+	0x1B80, 0x4D0003D5,
+	0x1B80, 0x4D0003D7,
+	0x1B80, 0x550703E5,
+	0x1B80, 0x550703E7,
+	0x1B80, 0xE0FE03F5,
+	0x1B80, 0xE0FE03F7,
+	0x1B80, 0xE0FE0405,
+	0x1B80, 0xE0FE0407,
+	0x1B80, 0x4D040415,
+	0x1B80, 0x4D040417,
+	0x1B80, 0x20880425,
+	0x1B80, 0x20880427,
+	0x1B80, 0x02000435,
+	0x1B80, 0x02000437,
+	0x1B80, 0x4D000445,
+	0x1B80, 0x4D000447,
+	0x1B80, 0x550F0455,
+	0x1B80, 0x550F0457,
+	0x1B80, 0xE0FE0465,
+	0x1B80, 0xE0FE0467,
+	0x1B80, 0x4F020475,
+	0x1B80, 0x4F020477,
+	0x1B80, 0x4E000485,
+	0x1B80, 0x4E000487,
+	0x1B80, 0x53020495,
+	0x1B80, 0x53020497,
+	0x1B80, 0x520104A5,
+	0x1B80, 0x520104A7,
+	0x1B80, 0xE10204B5,
+	0x1B80, 0xE10204B7,
+	0x1B80, 0x4D0804C5,
+	0x1B80, 0x4D0804C7,
+	0x1B80, 0x571004D5,
+	0x1B80, 0x571004D7,
+	0x1B80, 0x570004E5,
+	0x1B80, 0x570004E7,
+	0x1B80, 0x4D0004F5,
+	0x1B80, 0x4D0004F7,
+	0x1B80, 0x00010505,
+	0x1B80, 0x00010507,
+	0x1B80, 0xE1060515,
+	0x1B80, 0xE1060517,
+	0x1B80, 0x00010525,
+	0x1B80, 0x00010527,
+	0x1B80, 0x30730535,
+	0x1B80, 0x30730537,
+	0x1B80, 0x00230545,
+	0x1B80, 0x00230547,
+	0x1B80, 0xE15A0555,
+	0x1B80, 0xE15A0557,
+	0x1B80, 0x00020565,
+	0x1B80, 0x00020567,
+	0x1B80, 0x54E90575,
+	0x1B80, 0x54E90577,
+	0x1B80, 0x0BA60585,
+	0x1B80, 0x0BA60587,
+	0x1B80, 0x00230595,
+	0x1B80, 0x00230597,
+	0x1B80, 0xE15A05A5,
+	0x1B80, 0xE15A05A7,
+	0x1B80, 0x000205B5,
+	0x1B80, 0x000205B7,
+	0x1B80, 0x4D3005C5,
+	0x1B80, 0x4D3005C7,
+	0x1B80, 0x308C05D5,
+	0x1B80, 0x308C05D7,
+	0x1B80, 0x306F05E5,
+	0x1B80, 0x306F05E7,
+	0x1B80, 0x002205F5,
+	0x1B80, 0x002205F7,
+	0x1B80, 0xE15A0605,
+	0x1B80, 0xE15A0607,
+	0x1B80, 0x00020615,
+	0x1B80, 0x00020617,
+	0x1B80, 0x54E80625,
+	0x1B80, 0x54E80627,
+	0x1B80, 0x0BA60635,
+	0x1B80, 0x0BA60637,
+	0x1B80, 0x00220645,
+	0x1B80, 0x00220647,
+	0x1B80, 0xE15A0655,
+	0x1B80, 0xE15A0657,
+	0x1B80, 0x00020665,
+	0x1B80, 0x00020667,
+	0x1B80, 0x4D300675,
+	0x1B80, 0x4D300677,
+	0x1B80, 0x308C0685,
+	0x1B80, 0x308C0687,
+	0x1B80, 0x63F10695,
+	0x1B80, 0x63F10697,
+	0x1B80, 0xE10606A5,
+	0x1B80, 0xE10606A7,
+	0x1B80, 0xE15A06B5,
+	0x1B80, 0xE15A06B7,
+	0x1B80, 0x63F406C5,
+	0x1B80, 0x63F406C7,
+	0x1B80, 0xE10606D5,
+	0x1B80, 0xE10606D7,
+	0x1B80, 0xE15A06E5,
+	0x1B80, 0xE15A06E7,
+	0x1B80, 0x0BA806F5,
+	0x1B80, 0x0BA806F7,
+	0x1B80, 0x63F80705,
+	0x1B80, 0x63F80707,
+	0x1B80, 0xE1060715,
+	0x1B80, 0xE1060717,
+	0x1B80, 0xE15A0725,
+	0x1B80, 0xE15A0727,
+	0x1B80, 0x0BA90735,
+	0x1B80, 0x0BA90737,
+	0x1B80, 0x63FC0745,
+	0x1B80, 0x63FC0747,
+	0x1B80, 0xE1060755,
+	0x1B80, 0xE1060757,
+	0x1B80, 0xE15A0765,
+	0x1B80, 0xE15A0767,
+	0x1B80, 0x63FF0775,
+	0x1B80, 0x63FF0777,
+	0x1B80, 0xE1060785,
+	0x1B80, 0xE1060787,
+	0x1B80, 0xE15A0795,
+	0x1B80, 0xE15A0797,
+	0x1B80, 0x630007A5,
+	0x1B80, 0x630007A7,
+	0x1B80, 0xE10607B5,
+	0x1B80, 0xE10607B7,
+	0x1B80, 0xE15A07C5,
+	0x1B80, 0xE15A07C7,
+	0x1B80, 0x630307D5,
+	0x1B80, 0x630307D7,
+	0x1B80, 0xE10607E5,
+	0x1B80, 0xE10607E7,
+	0x1B80, 0xE15A07F5,
+	0x1B80, 0xE15A07F7,
+	0x1B80, 0xF3D40805,
+	0x1B80, 0xF3D40807,
+	0x1B80, 0x63070815,
+	0x1B80, 0x63070817,
+	0x1B80, 0xE1060825,
+	0x1B80, 0xE1060827,
+	0x1B80, 0xE15A0835,
+	0x1B80, 0xE15A0837,
+	0x1B80, 0xF4DB0845,
+	0x1B80, 0xF4DB0847,
+	0x1B80, 0x630B0855,
+	0x1B80, 0x630B0857,
+	0x1B80, 0xE1060865,
+	0x1B80, 0xE1060867,
+	0x1B80, 0xE15A0875,
+	0x1B80, 0xE15A0877,
+	0x1B80, 0x630E0885,
+	0x1B80, 0x630E0887,
+	0x1B80, 0xE1060895,
+	0x1B80, 0xE1060897,
+	0x1B80, 0xE15A08A5,
+	0x1B80, 0xE15A08A7,
+	0x1B80, 0x4D3008B5,
+	0x1B80, 0x4D3008B7,
+	0x1B80, 0x550108C5,
+	0x1B80, 0x550108C7,
+	0x1B80, 0x570408D5,
+	0x1B80, 0x570408D7,
+	0x1B80, 0x570008E5,
+	0x1B80, 0x570008E7,
+	0x1B80, 0x960008F5,
+	0x1B80, 0x960008F7,
+	0x1B80, 0x57080905,
+	0x1B80, 0x57080907,
+	0x1B80, 0x57000915,
+	0x1B80, 0x57000917,
+	0x1B80, 0x95000925,
+	0x1B80, 0x95000927,
+	0x1B80, 0x4D000935,
+	0x1B80, 0x4D000937,
+	0x1B80, 0x6C070945,
+	0x1B80, 0x6C070947,
+	0x1B80, 0x7B200955,
+	0x1B80, 0x7B200957,
+	0x1B80, 0x7A000965,
+	0x1B80, 0x7A000967,
+	0x1B80, 0x79000975,
+	0x1B80, 0x79000977,
+	0x1B80, 0x7F200985,
+	0x1B80, 0x7F200987,
+	0x1B80, 0x7E000995,
+	0x1B80, 0x7E000997,
+	0x1B80, 0x7D0009A5,
+	0x1B80, 0x7D0009A7,
+	0x1B80, 0x000109B5,
+	0x1B80, 0x000109B7,
+	0x1B80, 0x628509C5,
+	0x1B80, 0x628509C7,
+	0x1B80, 0xE10609D5,
+	0x1B80, 0xE10609D7,
+	0x1B80, 0xE13409E5,
+	0x1B80, 0xE13409E7,
+	0x1B80, 0x000109F5,
+	0x1B80, 0x000109F7,
+	0x1B80, 0x5C320A05,
+	0x1B80, 0x5C320A07,
+	0x1B80, 0x63FC0A15,
+	0x1B80, 0x63FC0A17,
+	0x1B80, 0x62850A25,
+	0x1B80, 0x62850A27,
+	0x1B80, 0xE1060A35,
+	0x1B80, 0xE1060A37,
+	0x1B80, 0x30CC0A45,
+	0x1B80, 0x30CC0A47,
+	0x1B80, 0x00230A55,
+	0x1B80, 0x00230A57,
+	0x1B80, 0xE15F0A65,
+	0x1B80, 0xE15F0A67,
+	0x1B80, 0x00020A75,
+	0x1B80, 0x00020A77,
+	0x1B80, 0x54E90A85,
+	0x1B80, 0x54E90A87,
+	0x1B80, 0x0BA60A95,
+	0x1B80, 0x0BA60A97,
+	0x1B80, 0x00230AA5,
+	0x1B80, 0x00230AA7,
+	0x1B80, 0xE15F0AB5,
+	0x1B80, 0xE15F0AB7,
+	0x1B80, 0x00020AC5,
+	0x1B80, 0x00020AC7,
+	0x1B80, 0x4D100AD5,
+	0x1B80, 0x4D100AD7,
+	0x1B80, 0x308C0AE5,
+	0x1B80, 0x308C0AE7,
+	0x1B80, 0x30C40AF5,
+	0x1B80, 0x30C40AF7,
+	0x1B80, 0x00220B05,
+	0x1B80, 0x00220B07,
+	0x1B80, 0xE15F0B15,
+	0x1B80, 0xE15F0B17,
+	0x1B80, 0x00020B25,
+	0x1B80, 0x00020B27,
+	0x1B80, 0x54E80B35,
+	0x1B80, 0x54E80B37,
+	0x1B80, 0x0BA60B45,
+	0x1B80, 0x0BA60B47,
+	0x1B80, 0x00220B55,
+	0x1B80, 0x00220B57,
+	0x1B80, 0xE15F0B65,
+	0x1B80, 0xE15F0B67,
+	0x1B80, 0x00020B75,
+	0x1B80, 0x00020B77,
+	0x1B80, 0x4D100B85,
+	0x1B80, 0x4D100B87,
+	0x1B80, 0x308C0B95,
+	0x1B80, 0x308C0B97,
+	0x1B80, 0x5C320BA5,
+	0x1B80, 0x5C320BA7,
+	0x1B80, 0x63F40BB5,
+	0x1B80, 0x63F40BB7,
+	0x1B80, 0x62850BC5,
+	0x1B80, 0x62850BC7,
+	0x1B80, 0xE1060BD5,
+	0x1B80, 0xE1060BD7,
+	0x1B80, 0x67F10BE5,
+	0x1B80, 0x67F10BE7,
+	0x1B80, 0xE1340BF5,
+	0x1B80, 0xE1340BF7,
+	0x1B80, 0xE15F0C05,
+	0x1B80, 0xE15F0C07,
+	0x1B80, 0x67F40C15,
+	0x1B80, 0x67F40C17,
+	0x1B80, 0xE1340C25,
+	0x1B80, 0xE1340C27,
+	0x1B80, 0xE15F0C35,
+	0x1B80, 0xE15F0C37,
+	0x1B80, 0x5C320C45,
+	0x1B80, 0x5C320C47,
+	0x1B80, 0x63FC0C55,
+	0x1B80, 0x63FC0C57,
+	0x1B80, 0x62850C65,
+	0x1B80, 0x62850C67,
+	0x1B80, 0xE1060C75,
+	0x1B80, 0xE1060C77,
+	0x1B80, 0x0BA80C85,
+	0x1B80, 0x0BA80C87,
+	0x1B80, 0x67F80C95,
+	0x1B80, 0x67F80C97,
+	0x1B80, 0xE1340CA5,
+	0x1B80, 0xE1340CA7,
+	0x1B80, 0xE15F0CB5,
+	0x1B80, 0xE15F0CB7,
+	0x1B80, 0x0BA90CC5,
+	0x1B80, 0x0BA90CC7,
+	0x1B80, 0x67FC0CD5,
+	0x1B80, 0x67FC0CD7,
+	0x1B80, 0xE1340CE5,
+	0x1B80, 0xE1340CE7,
+	0x1B80, 0xE15F0CF5,
+	0x1B80, 0xE15F0CF7,
+	0x1B80, 0x67FF0D05,
+	0x1B80, 0x67FF0D07,
+	0x1B80, 0xE1340D15,
+	0x1B80, 0xE1340D17,
+	0x1B80, 0xE15F0D25,
+	0x1B80, 0xE15F0D27,
+	0x1B80, 0x5C320D35,
+	0x1B80, 0x5C320D37,
+	0x1B80, 0x63030D45,
+	0x1B80, 0x63030D47,
+	0x1B80, 0xE1060D55,
+	0x1B80, 0xE1060D57,
+	0x1B80, 0x67000D65,
+	0x1B80, 0x67000D67,
+	0x1B80, 0xE1340D75,
+	0x1B80, 0xE1340D77,
+	0x1B80, 0xE15F0D85,
+	0x1B80, 0xE15F0D87,
+	0x1B80, 0x67030D95,
+	0x1B80, 0x67030D97,
+	0x1B80, 0xE1340DA5,
+	0x1B80, 0xE1340DA7,
+	0x1B80, 0xE15F0DB5,
+	0x1B80, 0xE15F0DB7,
+	0x1B80, 0xF6C90DC5,
+	0x1B80, 0xF6C90DC7,
+	0x1B80, 0x67070DD5,
+	0x1B80, 0x67070DD7,
+	0x1B80, 0xE1340DE5,
+	0x1B80, 0xE1340DE7,
+	0x1B80, 0xE15F0DF5,
+	0x1B80, 0xE15F0DF7,
+	0x1B80, 0xF7D00E05,
+	0x1B80, 0xF7D00E07,
+	0x1B80, 0x5C320E15,
+	0x1B80, 0x5C320E17,
+	0x1B80, 0x630B0E25,
+	0x1B80, 0x630B0E27,
+	0x1B80, 0xE1060E35,
+	0x1B80, 0xE1060E37,
+	0x1B80, 0x670B0E45,
+	0x1B80, 0x670B0E47,
+	0x1B80, 0xE1340E55,
+	0x1B80, 0xE1340E57,
+	0x1B80, 0xE15F0E65,
+	0x1B80, 0xE15F0E67,
+	0x1B80, 0x670E0E75,
+	0x1B80, 0x670E0E77,
+	0x1B80, 0xE1340E85,
+	0x1B80, 0xE1340E87,
+	0x1B80, 0xE15F0E95,
+	0x1B80, 0xE15F0E97,
+	0x1B80, 0x4D100EA5,
+	0x1B80, 0x4D100EA7,
+	0x1B80, 0x308C0EB5,
+	0x1B80, 0x308C0EB7,
+	0x1B80, 0x00010EC5,
+	0x1B80, 0x00010EC7,
+	0x1B80, 0x62850ED5,
+	0x1B80, 0x62850ED7,
+	0x1B80, 0xE1060EE5,
+	0x1B80, 0xE1060EE7,
+	0x1B80, 0x00010EF5,
+	0x1B80, 0x00010EF7,
+	0x1B80, 0xE1340F05,
+	0x1B80, 0xE1340F07,
+	0x1B80, 0x00010F15,
+	0x1B80, 0x00010F17,
+	0x1B80, 0x7B240F25,
+	0x1B80, 0x7B240F27,
+	0x1B80, 0x7A400F35,
+	0x1B80, 0x7A400F37,
+	0x1B80, 0x79000F45,
+	0x1B80, 0x79000F47,
+	0x1B80, 0x55030F55,
+	0x1B80, 0x55030F57,
+	0x1B80, 0x30FE0F65,
+	0x1B80, 0x30FE0F67,
+	0x1B80, 0x7B1C0F75,
+	0x1B80, 0x7B1C0F77,
+	0x1B80, 0x7A400F85,
+	0x1B80, 0x7A400F87,
+	0x1B80, 0x550B0F95,
+	0x1B80, 0x550B0F97,
+	0x1B80, 0x30FE0FA5,
+	0x1B80, 0x30FE0FA7,
+	0x1B80, 0x7B200FB5,
+	0x1B80, 0x7B200FB7,
+	0x1B80, 0x7A000FC5,
+	0x1B80, 0x7A000FC7,
+	0x1B80, 0x55130FD5,
+	0x1B80, 0x55130FD7,
+	0x1B80, 0x74010FE5,
+	0x1B80, 0x74010FE7,
+	0x1B80, 0x74000FF5,
+	0x1B80, 0x74000FF7,
+	0x1B80, 0x8E001005,
+	0x1B80, 0x8E001007,
+	0x1B80, 0x00011015,
+	0x1B80, 0x00011017,
+	0x1B80, 0x57021025,
+	0x1B80, 0x57021027,
+	0x1B80, 0x57001035,
+	0x1B80, 0x57001037,
+	0x1B80, 0x97001045,
+	0x1B80, 0x97001047,
+	0x1B80, 0x00011055,
+	0x1B80, 0x00011057,
+	0x1B80, 0x4F781065,
+	0x1B80, 0x4F781067,
+	0x1B80, 0x53881075,
+	0x1B80, 0x53881077,
+	0x1B80, 0xE1141085,
+	0x1B80, 0xE1141087,
+	0x1B80, 0x54801095,
+	0x1B80, 0x54801097,
+	0x1B80, 0x540010A5,
+	0x1B80, 0x540010A7,
+	0x1B80, 0xE11410B5,
+	0x1B80, 0xE11410B7,
+	0x1B80, 0x548110C5,
+	0x1B80, 0x548110C7,
+	0x1B80, 0x540010D5,
+	0x1B80, 0x540010D7,
+	0x1B80, 0xE11410E5,
+	0x1B80, 0xE11410E7,
+	0x1B80, 0x548210F5,
+	0x1B80, 0x548210F7,
+	0x1B80, 0x54001105,
+	0x1B80, 0x54001107,
+	0x1B80, 0xE11F1115,
+	0x1B80, 0xE11F1117,
+	0x1B80, 0xBF1D1125,
+	0x1B80, 0xBF1D1127,
+	0x1B80, 0x301D1135,
+	0x1B80, 0x301D1137,
+	0x1B80, 0xE0F21145,
+	0x1B80, 0xE0F21147,
+	0x1B80, 0xE0F71155,
+	0x1B80, 0xE0F71157,
+	0x1B80, 0xE0FB1165,
+	0x1B80, 0xE0FB1167,
+	0x1B80, 0xE1021175,
+	0x1B80, 0xE1021177,
+	0x1B80, 0xE1561185,
+	0x1B80, 0xE1561187,
+	0x1B80, 0x55131195,
+	0x1B80, 0x55131197,
+	0x1B80, 0xE0FE11A5,
+	0x1B80, 0xE0FE11A7,
+	0x1B80, 0x551511B5,
+	0x1B80, 0x551511B7,
+	0x1B80, 0xE10211C5,
+	0x1B80, 0xE10211C7,
+	0x1B80, 0xE15611D5,
+	0x1B80, 0xE15611D7,
+	0x1B80, 0x000111E5,
+	0x1B80, 0x000111E7,
+	0x1B80, 0x54BF11F5,
+	0x1B80, 0x54BF11F7,
+	0x1B80, 0x54C01205,
+	0x1B80, 0x54C01207,
+	0x1B80, 0x54A31215,
+	0x1B80, 0x54A31217,
+	0x1B80, 0x54C11225,
+	0x1B80, 0x54C11227,
+	0x1B80, 0x54A41235,
+	0x1B80, 0x54A41237,
+	0x1B80, 0x4C181245,
+	0x1B80, 0x4C181247,
+	0x1B80, 0xBF071255,
+	0x1B80, 0xBF071257,
+	0x1B80, 0x54C21265,
+	0x1B80, 0x54C21267,
+	0x1B80, 0x54A41275,
+	0x1B80, 0x54A41277,
+	0x1B80, 0xBF041285,
+	0x1B80, 0xBF041287,
+	0x1B80, 0x54C11295,
+	0x1B80, 0x54C11297,
+	0x1B80, 0x54A312A5,
+	0x1B80, 0x54A312A7,
+	0x1B80, 0xBF0112B5,
+	0x1B80, 0xBF0112B7,
+	0x1B80, 0xE16412C5,
+	0x1B80, 0xE16412C7,
+	0x1B80, 0x54DF12D5,
+	0x1B80, 0x54DF12D7,
+	0x1B80, 0x000112E5,
+	0x1B80, 0x000112E7,
+	0x1B80, 0x54BF12F5,
+	0x1B80, 0x54BF12F7,
+	0x1B80, 0x54E51305,
+	0x1B80, 0x54E51307,
+	0x1B80, 0x050A1315,
+	0x1B80, 0x050A1317,
+	0x1B80, 0x54DF1325,
+	0x1B80, 0x54DF1327,
+	0x1B80, 0x00011335,
+	0x1B80, 0x00011337,
+	0x1B80, 0x7F201345,
+	0x1B80, 0x7F201347,
+	0x1B80, 0x7E001355,
+	0x1B80, 0x7E001357,
+	0x1B80, 0x7D001365,
+	0x1B80, 0x7D001367,
+	0x1B80, 0x55011375,
+	0x1B80, 0x55011377,
+	0x1B80, 0x5C311385,
+	0x1B80, 0x5C311387,
+	0x1B80, 0xE0FE1395,
+	0x1B80, 0xE0FE1397,
+	0x1B80, 0xE10213A5,
+	0x1B80, 0xE10213A7,
+	0x1B80, 0x548013B5,
+	0x1B80, 0x548013B7,
+	0x1B80, 0x540013C5,
+	0x1B80, 0x540013C7,
+	0x1B80, 0xE0FE13D5,
+	0x1B80, 0xE0FE13D7,
+	0x1B80, 0xE10213E5,
+	0x1B80, 0xE10213E7,
+	0x1B80, 0x548113F5,
+	0x1B80, 0x548113F7,
+	0x1B80, 0x54001405,
+	0x1B80, 0x54001407,
+	0x1B80, 0xE0FE1415,
+	0x1B80, 0xE0FE1417,
+	0x1B80, 0xE1021425,
+	0x1B80, 0xE1021427,
+	0x1B80, 0x54821435,
+	0x1B80, 0x54821437,
+	0x1B80, 0x54001445,
+	0x1B80, 0x54001447,
+	0x1B80, 0xE11F1455,
+	0x1B80, 0xE11F1457,
+	0x1B80, 0xBFE91465,
+	0x1B80, 0xBFE91467,
+	0x1B80, 0x301D1475,
+	0x1B80, 0x301D1477,
+	0x1B80, 0x00231485,
+	0x1B80, 0x00231487,
+	0x1B80, 0x7B201495,
+	0x1B80, 0x7B201497,
+	0x1B80, 0x7A0014A5,
+	0x1B80, 0x7A0014A7,
+	0x1B80, 0x790014B5,
+	0x1B80, 0x790014B7,
+	0x1B80, 0xE15A14C5,
+	0x1B80, 0xE15A14C7,
+	0x1B80, 0x000214D5,
+	0x1B80, 0x000214D7,
+	0x1B80, 0x000114E5,
+	0x1B80, 0x000114E7,
+	0x1B80, 0x002214F5,
+	0x1B80, 0x002214F7,
+	0x1B80, 0x7B201505,
+	0x1B80, 0x7B201507,
+	0x1B80, 0x7A001515,
+	0x1B80, 0x7A001517,
+	0x1B80, 0x79001525,
+	0x1B80, 0x79001527,
+	0x1B80, 0xE15A1535,
+	0x1B80, 0xE15A1537,
+	0x1B80, 0x00021545,
+	0x1B80, 0x00021547,
+	0x1B80, 0x00011555,
+	0x1B80, 0x00011557,
+	0x1B80, 0x549F1565,
+	0x1B80, 0x549F1567,
+	0x1B80, 0x54FF1575,
+	0x1B80, 0x54FF1577,
+	0x1B80, 0x54001585,
+	0x1B80, 0x54001587,
+	0x1B80, 0x00011595,
+	0x1B80, 0x00011597,
+	0x1B80, 0x5C3115A5,
+	0x1B80, 0x5C3115A7,
+	0x1B80, 0x071415B5,
+	0x1B80, 0x071415B7,
+	0x1B80, 0x540015C5,
+	0x1B80, 0x540015C7,
+	0x1B80, 0x5C3215D5,
+	0x1B80, 0x5C3215D7,
+	0x1B80, 0x000115E5,
+	0x1B80, 0x000115E7,
+	0x1B80, 0x5C3215F5,
+	0x1B80, 0x5C3215F7,
+	0x1B80, 0x07141605,
+	0x1B80, 0x07141607,
+	0x1B80, 0x54001615,
+	0x1B80, 0x54001617,
+	0x1B80, 0x5C311625,
+	0x1B80, 0x5C311627,
+	0x1B80, 0x00011635,
+	0x1B80, 0x00011637,
+	0x1B80, 0x4C981645,
+	0x1B80, 0x4C981647,
+	0x1B80, 0x4C181655,
+	0x1B80, 0x4C181657,
+	0x1B80, 0x00011665,
+	0x1B80, 0x00011667,
+	0x1B80, 0x5C321675,
+	0x1B80, 0x5C321677,
+	0x1B80, 0x62841685,
+	0x1B80, 0x62841687,
+	0x1B80, 0x66861695,
+	0x1B80, 0x66861697,
+	0x1B80, 0x6C0316A5,
+	0x1B80, 0x6C0316A7,
+	0x1B80, 0x7B2016B5,
+	0x1B80, 0x7B2016B7,
+	0x1B80, 0x7A0016C5,
+	0x1B80, 0x7A0016C7,
+	0x1B80, 0x790016D5,
+	0x1B80, 0x790016D7,
+	0x1B80, 0x7F2016E5,
+	0x1B80, 0x7F2016E7,
+	0x1B80, 0x7E0016F5,
+	0x1B80, 0x7E0016F7,
+	0x1B80, 0x7D001705,
+	0x1B80, 0x7D001707,
+	0x1B80, 0x09011715,
+	0x1B80, 0x09011717,
+	0x1B80, 0x0C011725,
+	0x1B80, 0x0C011727,
+	0x1B80, 0x0BA61735,
+	0x1B80, 0x0BA61737,
+	0x1B80, 0x00011745,
+	0x1B80, 0x00011747,
+	0x1B80, 0x00000006,
+	0x1B80, 0x00000002,
+
+};
+
+void
+odm_read_and_config_tc_8821c_phy_reg(
+	struct PHY_DM_STRUCT  *p_dm_odm
+)
+{
+	u32     i         = 0;
+	u8     c_cond;
+	boolean is_matched = true, is_skipped = false;
+	u32     array_len    = sizeof(array_tc_8821c_phy_reg) / sizeof(u32);
+	u32    *array       = array_tc_8821c_phy_reg;
+
+	u32	v1 = 0, v2 = 0, pre_v1 = 0, pre_v2 = 0;
+
+	ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> odm_read_and_config_tc_8821c_phy_reg\n"));
+
+	while ((i + 1) < array_len) {
+		v1 = array[i];
+		v2 = array[i + 1];
+
+		if (v1 & (BIT(31) | BIT30)) {/*positive & negative condition*/
+			if (v1 & BIT(31)) {/* positive condition*/
+				c_cond  = (u8)((v1 & (BIT(29) | BIT(28))) >> 28);
+				if (c_cond == COND_ENDIF) {/*end*/
+					is_matched = true;
+					is_skipped = false;
+					ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ENDIF\n"));
+				} else if (c_cond == COND_ELSE) { /*else*/
+					is_matched = is_skipped ? false : true;
+					ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ELSE\n"));
+				} else {/*if , else if*/
+					pre_v1 = v1;
+					pre_v2 = v2;
+					ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("IF or ELSE IF\n"));
+				}
+			} else if (v1 & BIT(30)) { /*negative condition*/
+				if (is_skipped == false) {
+					if (check_positive(p_dm_odm, pre_v1, pre_v2, v1, v2)) {
+						is_matched = true;
+						is_skipped = true;
+					} else {
+						is_matched = false;
+						is_skipped = false;
+					}
+				} else
+					is_matched = false;
+			}
+		} else {
+			if (is_matched)
+				odm_config_bb_phy_8821c(p_dm_odm, v1, MASKDWORD, v2);
+		}
+		i = i + 2;
+	}
+}
+
+u32
+odm_get_version_tc_8821c_phy_reg(void)
+{
+	return 9;
+}
+
+/******************************************************************************
+*                           PHY_REG_PG.TXT
+******************************************************************************/
+
+u32 array_tc_8821c_phy_reg_pg[] = {
+	0, 0, 0, 0x00000c20, 0xffffffff, 0x34363840,
+	0, 0, 0, 0x00000c24, 0xffffffff, 0x42424444,
+	0, 0, 0, 0x00000c28, 0xffffffff, 0x30323638,
+	0, 0, 0, 0x00000c2c, 0xffffffff, 0x40424444,
+	0, 0, 0, 0x00000c30, 0xffffffff, 0x28303236,
+	0, 0, 1, 0x00000c34, 0xffffffff, 0x38404242,
+	0, 0, 1, 0x00000c38, 0xffffffff, 0x26283034,
+	0, 0, 2, 0x00000cd8, 0xffffffff, 0x36384040,
+	0, 0, 2, 0x00000cdc, 0xffffffff, 0x24262832,
+	0, 0, 0, 0x00000c3c, 0xffffffff, 0x40424444,
+	0, 0, 0, 0x00000c40, 0xffffffff, 0x28303236,
+	0, 0, 0, 0x00000c44, 0xffffffff, 0x42422426,
+	0, 0, 1, 0x00000c48, 0xffffffff, 0x30343840,
+	0, 0, 1, 0x00000c4c, 0xffffffff, 0x22242628,
+	0, 0, 2, 0x00000ce0, 0xffffffff, 0x36384040,
+	0, 0, 2, 0x00000ce4, 0xffffffff, 0x24262832,
+	0, 0, 2, 0x00000ce8, 0x0000ffff, 0x20202022,
+	1, 0, 0, 0x00000c24, 0xffffffff, 0x42424444,
+	1, 0, 0, 0x00000c28, 0xffffffff, 0x30323640,
+	1, 0, 0, 0x00000c2c, 0xffffffff, 0x40424444,
+	1, 0, 0, 0x00000c30, 0xffffffff, 0x28303236,
+	1, 0, 1, 0x00000c34, 0xffffffff, 0x38404242,
+	1, 0, 1, 0x00000c38, 0xffffffff, 0x26283034,
+	1, 0, 2, 0x00000cd8, 0xffffffff, 0x36384040,
+	1, 0, 2, 0x00000cdc, 0xffffffff, 0x24262832,
+	1, 0, 0, 0x00000c3c, 0xffffffff, 0x40424444,
+	1, 0, 0, 0x00000c40, 0xffffffff, 0x28303236,
+	1, 0, 0, 0x00000c44, 0xffffffff, 0x42422426,
+	1, 0, 1, 0x00000c48, 0xffffffff, 0x30343840,
+	1, 0, 1, 0x00000c4c, 0xffffffff, 0x22242628,
+	1, 0, 2, 0x00000ce0, 0xffffffff, 0x36384040,
+	1, 0, 2, 0x00000ce4, 0xffffffff, 0x24262832,
+	1, 0, 2, 0x00000ce8, 0x0000ffff, 0x20202022
+};
+
+void
+odm_read_and_config_tc_8821c_phy_reg_pg(
+	struct PHY_DM_STRUCT  *p_dm_odm
+)
+{
+	u32     i         = 0;
+	u32     array_len    = sizeof(array_tc_8821c_phy_reg_pg) / sizeof(u32);
+	u32    *array       = array_tc_8821c_phy_reg_pg;
+
+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
+	struct _ADAPTER		*adapter = p_dm_odm->adapter;
+	HAL_DATA_TYPE	*p_hal_data = GET_HAL_DATA(adapter);
+
+	PlatformZeroMemory(p_hal_data->BufOfLinesPwrByRate, MAX_LINES_HWCONFIG_TXT * MAX_BYTES_LINE_HWCONFIG_TXT);
+	p_hal_data->nLinesReadPwrByRate = array_len / 6;
+#endif
+
+	ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> odm_read_and_config_tc_8821c_phy_reg_pg\n"));
+
+	p_dm_odm->phy_reg_pg_version = 1;
+	p_dm_odm->phy_reg_pg_value_type = PHY_REG_PG_EXACT_VALUE;
+
+	for (i = 0; i < array_len; i += 6) {
+		u32 v1 = array[i];
+		u32 v2 = array[i + 1];
+		u32 v3 = array[i + 2];
+		u32 v4 = array[i + 3];
+		u32 v5 = array[i + 4];
+		u32 v6 = array[i + 5];
+
+		odm_config_bb_phy_reg_pg_8821c(p_dm_odm, v1, v2, v3, v4, v5, v6);
+
+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
+		rsprintf((char *)p_hal_data->BufOfLinesPwrByRate[i / 6], 100, "%s, %s, %s, 0x%X, 0x%08X, 0x%08X,",
+			(v1 == 0 ? "2.4G" : "  5G"), (v2 == 0 ? "A" : "B"), (v3 == 0 ? "1Tx" : "2Tx"), v4, v5, v6);
+#endif
+	}
+}
+
+
+
+#endif /* end of HWIMG_SUPPORT*/
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/rtl8821c/halhwimg8821c_testchip_bb.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/rtl8821c/halhwimg8821c_testchip_bb.h
--- linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/rtl8821c/halhwimg8821c_testchip_bb.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/rtl8821c/halhwimg8821c_testchip_bb.h	2020-04-10 16:35:06.834660908 +0300
@@ -0,0 +1,58 @@
+/******************************************************************************
+*
+* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
+*
+* This program is free software; you can redistribute it and/or modify it
+* under the terms of version 2 of the GNU General Public License as
+* published by the Free Software Foundation.
+*
+* This program is distributed in the hope that it will be useful, but WITHOUT
+* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+* more details.
+*
+* You should have received a copy of the GNU General Public License along with
+* this program; if not, write to the Free Software Foundation, Inc.,
+* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
+*
+*
+******************************************************************************/
+
+/*Image2HeaderVersion: 2.22*/
+#if (RTL8821C_SUPPORT == 1)
+#ifndef __INC_TC_BB_HW_IMG_8821C_H
+#define __INC_TC_BB_HW_IMG_8821C_H
+
+
+/******************************************************************************
+*                           AGC_TAB.TXT
+******************************************************************************/
+
+void
+odm_read_and_config_tc_8821c_agc_tab(/* TC: Test Chip, MP: MP Chip*/
+	struct PHY_DM_STRUCT  *p_dm_odm
+);
+u32 odm_get_version_tc_8821c_agc_tab(void);
+
+/******************************************************************************
+*                           PHY_REG.TXT
+******************************************************************************/
+
+void
+odm_read_and_config_tc_8821c_phy_reg(/* TC: Test Chip, MP: MP Chip*/
+	struct PHY_DM_STRUCT  *p_dm_odm
+);
+u32 odm_get_version_tc_8821c_phy_reg(void);
+
+/******************************************************************************
+*                           PHY_REG_PG.TXT
+******************************************************************************/
+
+void
+odm_read_and_config_tc_8821c_phy_reg_pg(/* TC: Test Chip, MP: MP Chip*/
+	struct PHY_DM_STRUCT  *p_dm_odm
+);
+u32 odm_get_version_tc_8821c_phy_reg_pg(void);
+
+#endif
+#endif /* end of HWIMG_SUPPORT*/
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/rtl8821c/halhwimg8821c_testchip_fw.c linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/rtl8821c/halhwimg8821c_testchip_fw.c
--- linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/rtl8821c/halhwimg8821c_testchip_fw.c	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/rtl8821c/halhwimg8821c_testchip_fw.c	2020-04-10 16:35:06.834660908 +0300
@@ -0,0 +1,16138 @@
+/******************************************************************************
+*
+* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
+*
+* This program is free software; you can redistribute it and/or modify it
+* under the terms of version 2 of the GNU General Public License as
+* published by the Free Software Foundation.
+*
+* This program is distributed in the hope that it will be useful, but WITHOUT
+* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+* more details.
+*
+* You should have received a copy of the GNU General Public License along with
+* this program; if not, write to the Free Software Foundation, Inc.,
+* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
+*
+*
+******************************************************************************/
+
+/*Image2HeaderVersion: 2.16*/
+#include "mp_precomp.h"
+#include "../phydm_precomp.h"
+
+#ifdef LOAD_FW_HEADER_FROM_DRIVER
+	#include "../../rtl8821c/hal8821c_testchip_fw.h"
+#endif
+
+
+#if (RTL8821C_SUPPORT == 1)
+#if (defined(CONFIG_AP_WOWLAN) || (DM_ODM_SUPPORT_TYPE & (ODM_AP)))
+
+
+#ifndef LOAD_FW_HEADER_FROM_DRIVER
+u8 array_tc_8821c_fw_ap[] = {
+	0x21, 0x88, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x91, 0x2D, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x01, 0x19, 0x10, 0x3B, 0xE0, 0x07, 0x00, 0x00, 0x18, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x20, 0x80, 0x60, 0x19, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x88, 0xBA, 0x00, 0x00, 0x80, 0x7E, 0x00, 0x00, 0x00, 0x00, 0x10, 0x80, 0x00, 0x00, 0x03, 0x80,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x25, 0x4A, 0x03, 0x80, 0x15, 0x04, 0x03, 0x80,
+	0x03, 0x02, 0x01, 0xFE, 0x03, 0x03, 0x01, 0xFE, 0x03, 0x04, 0x01, 0xFE, 0x03, 0x05, 0x01, 0xFE,
+	0x03, 0x06, 0x01, 0xFE, 0x03, 0x07, 0x01, 0xFE, 0x75, 0x5D, 0x03, 0x80, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06, 0x09, 0x0C, 0x12, 0x18, 0x24, 0x30, 0x36,
+	0x01, 0x02, 0x05, 0x0B, 0x00, 0x00, 0x00, 0x00, 0x0A, 0x08, 0x03, 0x03, 0x00, 0x04, 0x09, 0x07,
+	0x03, 0x03, 0x00, 0x04, 0x08, 0x06, 0x03, 0x02, 0x00, 0x04, 0x08, 0x05, 0x03, 0x01, 0x00, 0x04,
+	0x0D, 0x0A, 0x07, 0x05, 0x00, 0x08, 0x0C, 0x0A, 0x07, 0x04, 0x00, 0x08, 0x0B, 0x0A, 0x06, 0x05,
+	0x00, 0x08, 0x0B, 0x0A, 0x05, 0x03, 0x00, 0x08, 0x0B, 0x0A, 0x03, 0x02, 0x00, 0x08, 0x14, 0x12,
+	0x0C, 0x04, 0x00, 0x10, 0x14, 0x12, 0x09, 0x04, 0x00, 0x10, 0x24, 0x22, 0x1C, 0x12, 0x00, 0x20,
+	0x24, 0x22, 0x18, 0x0C, 0x00, 0x20, 0x24, 0x22, 0x14, 0x06, 0x00, 0x20, 0x24, 0x22, 0x0F, 0x04,
+	0x00, 0x20, 0x24, 0x21, 0x0A, 0x04, 0x00, 0x20, 0x23, 0x21, 0x0C, 0x04, 0x00, 0x20, 0x23, 0x1F,
+	0x0A, 0x04, 0x00, 0x20, 0x22, 0x1F, 0x0F, 0x04, 0x00, 0x20, 0x21, 0x1F, 0x16, 0x0C, 0x00, 0x20,
+	0x31, 0x2F, 0x20, 0x14, 0x00, 0x30, 0x31, 0x2F, 0x18, 0x10, 0x00, 0x30, 0x31, 0x2C, 0x18, 0x0C,
+	0x00, 0x30, 0x31, 0x2A, 0x14, 0x0C, 0x00, 0x30, 0x31, 0x28, 0x14, 0x00, 0x00, 0x30, 0x31, 0x24,
+	0x14, 0x00, 0x00, 0x30, 0x31, 0x1E, 0x14, 0x00, 0x00, 0x30, 0x31, 0x18, 0x0A, 0x00, 0x00, 0x30,
+	0x01, 0x02, 0x03, 0x06, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B, 0x2C, 0xFF, 0x00, 0x01, 0x02,
+	0x02, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A, 0x02, 0x02, 0x02, 0x04, 0x02, 0x04, 0x06, 0x06,
+	0x08, 0x08, 0x09, 0x09, 0x04, 0x08, 0x08, 0x08, 0x0C, 0x10, 0x10, 0x18, 0x04, 0x08, 0x08, 0x08,
+	0x0C, 0x10, 0x10, 0x18, 0x05, 0x08, 0x08, 0x09, 0x10, 0x14, 0x1C, 0x20, 0x04, 0x06, 0x08, 0x0A,
+	0x10, 0x18, 0x18, 0x20, 0x03, 0x05, 0x08, 0x09, 0x10, 0x14, 0x1C, 0x24, 0x2A, 0x2C, 0x05, 0x07,
+	0x09, 0x0A, 0x10, 0x14, 0x1C, 0x28, 0x2C, 0x30, 0x06, 0x08, 0x0A, 0x0C, 0x12, 0x18, 0x1E, 0x30,
+	0x38, 0x42, 0x0A, 0x0C, 0x0C, 0x12, 0x16, 0x1C, 0x20, 0x24, 0x24, 0x30, 0x01, 0x01, 0x01, 0x01,
+	0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08,
+	0x02, 0x04, 0x06, 0x07, 0x08, 0x0A, 0x0B, 0x0C, 0x03, 0x05, 0x06, 0x07, 0x08, 0x0A, 0x0B, 0x0C,
+	0x05, 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x02, 0x04, 0x06, 0x07, 0x08, 0x09, 0x0B, 0x0C,
+	0x0C, 0x0C, 0x03, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0B, 0x0C, 0x0C, 0x0C, 0x05, 0x06, 0x07, 0x08,
+	0x09, 0x0A, 0x0B, 0x0C, 0x0C, 0x0C, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0C, 0x0C,
+	0x36, 0x2D, 0xFF, 0x36, 0x2E, 0xFF, 0x37, 0x2F, 0xFF, 0x41, 0x38, 0x30, 0x39, 0x42, 0x31, 0x42,
+	0x3A, 0x32, 0x43, 0x3A, 0x33, 0x43, 0x3A, 0x34, 0x3A, 0x44, 0x35, 0x44, 0x3B, 0xFF, 0x37, 0x2E,
+	0x40, 0x38, 0x30, 0x41, 0x39, 0x42, 0x31, 0x3A, 0x43, 0x32, 0x3B, 0x43, 0x35, 0x3C, 0x44, 0xFF,
+	0x3D, 0x45, 0xFF, 0x3E, 0x45, 0xFF, 0x45, 0x3F, 0xFF, 0x46, 0xFF, 0xFF, 0x37, 0x41, 0x2F, 0x39,
+	0x42, 0x31, 0x43, 0x3A, 0x33, 0x44, 0x3B, 0x35, 0x45, 0x3D, 0xFF, 0x46, 0x47, 0x3E, 0x47, 0xFF,
+	0xFF, 0x48, 0xFF, 0xFF, 0x49, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x0D, 0x14, 0xFF, 0x15,
+	0x0E, 0xFF, 0x15, 0x0F, 0xFF, 0x16, 0x10, 0xFF, 0x17, 0x1E, 0x11, 0x1E, 0x18, 0x12, 0x1F, 0x18,
+	0x13, 0x18, 0x1F, 0xFF, 0x15, 0x0E, 0xFF, 0x16, 0x1D, 0x10, 0x17, 0x1E, 0x10, 0x18, 0x1E, 0x11,
+	0x19, 0x1F, 0xFF, 0x1A, 0x20, 0xFF, 0x21, 0x1B, 0xFF, 0x21, 0xFF, 0xFF, 0x15, 0x13, 0x0F, 0x17,
+	0x1E, 0x11, 0x18, 0x1F, 0x13, 0x20, 0x19, 0xFF, 0x21, 0x1B, 0xFF, 0x22, 0xFF, 0xFF, 0x23, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0x04, 0x04, 0x04, 0x36, 0x2C, 0xFF, 0x2D, 0xFF, 0xFF, 0x2E, 0x37, 0xFF,
+	0x38, 0x41, 0x2F, 0x39, 0x42, 0x30, 0x43, 0x39, 0x31, 0x42, 0x39, 0x32, 0x43, 0x3A, 0x33, 0x43,
+	0x3A, 0x34, 0x2D, 0x2C, 0xFF, 0x36, 0x2E, 0xFF, 0x37, 0x2F, 0x40, 0x38, 0x30, 0x41, 0x42, 0x33,
+	0x39, 0x43, 0x35, 0x3A, 0x3B, 0x43, 0x34, 0x44, 0x3C, 0x3B, 0x45, 0x3D, 0x3C, 0x45, 0x3E, 0x3D,
+	0x37, 0x2E, 0xFF, 0x38, 0x2F, 0x40, 0x39, 0x31, 0x41, 0x3A, 0x42, 0xFF, 0x43, 0x3B, 0xFF, 0x44,
+	0x3C, 0xFF, 0x45, 0x3D, 0x3C, 0x46, 0x3F, 0x45, 0x47, 0x46, 0x45, 0x48, 0x47, 0x47, 0x00, 0x00,
+	0x04, 0xFF, 0xFF, 0x0C, 0xFF, 0xFF, 0x0D, 0x14, 0xFF, 0x0E, 0x15, 0xFF, 0x16, 0x0F, 0xFF, 0x17,
+	0x10, 0xFF, 0x17, 0x11, 0xFF, 0x17, 0x12, 0xFF, 0x0D, 0x0C, 0xFF, 0x14, 0x0E, 0xFF, 0x15, 0x0F,
+	0xFF, 0x16, 0x1D, 0x10, 0x17, 0x1E, 0x12, 0x18, 0x1F, 0x13, 0x19, 0x20, 0x19, 0x20, 0x1A, 0x19,
+	0x14, 0x0E, 0xFF, 0x15, 0x1C, 0xFF, 0x17, 0x1D, 0x11, 0x18, 0x1E, 0x13, 0x19, 0x1F, 0x1E, 0x20,
+	0x1A, 0x1F, 0x21, 0x1B, 0x20, 0x22, 0x21, 0x1B, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x24, 0x26, 0x2A, 0x00, 0x00, 0x00, 0x1F, 0x21, 0x25, 0x27, 0x28, 0x00, 0x00, 0x00, 0x00,
+	0x23, 0x26, 0x28, 0x30, 0x00, 0x00, 0x00, 0x00, 0x23, 0x26, 0x28, 0x2A, 0x00, 0x00, 0x00, 0x00,
+	0x23, 0x26, 0x28, 0x2A, 0x00, 0x00, 0x00, 0x00, 0x24, 0x28, 0x2A, 0x2C, 0x2E, 0x30, 0x00, 0x00,
+	0x00, 0x00, 0x26, 0x29, 0x2B, 0x2D, 0x2F, 0x31, 0x00, 0x00, 0x00, 0x00, 0x28, 0x2A, 0x2C, 0x2E,
+	0x30, 0x32, 0x00, 0x00, 0x00, 0x1F, 0x23, 0x26, 0x28, 0x2A, 0x2A, 0x2A, 0x04, 0x00, 0x04, 0x00,
+	0x08, 0x00, 0x10, 0x00, 0x18, 0x00, 0x24, 0x00, 0x30, 0x00, 0x48, 0x00, 0x60, 0x00, 0x90, 0x00,
+	0xC0, 0x00, 0xD8, 0x00, 0x50, 0x00, 0x64, 0x00, 0x78, 0x00, 0xA0, 0x00, 0xF0, 0x00, 0x40, 0x01,
+	0x90, 0x01, 0xE0, 0x01, 0xC8, 0x00, 0xF0, 0x00, 0x40, 0x01, 0x90, 0x01, 0x58, 0x02, 0x20, 0x03,
+	0xB0, 0x04, 0x40, 0x06, 0xC8, 0x00, 0x18, 0x01, 0xE0, 0x01, 0xF4, 0x01, 0x84, 0x03, 0x20, 0x03,
+	0xB0, 0x04, 0x40, 0x06, 0xC8, 0x00, 0x18, 0x01, 0xE0, 0x01, 0xD0, 0x02, 0x20, 0x03, 0xE8, 0x03,
+	0xB0, 0x04, 0x40, 0x06, 0x3C, 0x00, 0x64, 0x00, 0x78, 0x00, 0xA0, 0x00, 0xF0, 0x00, 0x40, 0x01,
+	0x90, 0x01, 0xE0, 0x01, 0x58, 0x02, 0x20, 0x03, 0x78, 0x00, 0xF0, 0x00, 0x68, 0x01, 0xA4, 0x01,
+	0xE0, 0x01, 0x1C, 0x02, 0x58, 0x02, 0x20, 0x03, 0xE8, 0x03, 0xB0, 0x04, 0xB4, 0x00, 0x2C, 0x01,
+	0xA4, 0x01, 0xE0, 0x01, 0x1C, 0x02, 0x58, 0x02, 0x20, 0x03, 0xE8, 0x03, 0xB0, 0x04, 0x78, 0x05,
+	0xC8, 0x00, 0x18, 0x01, 0xE0, 0x01, 0xD0, 0x02, 0xE8, 0x03, 0xB0, 0x04, 0x40, 0x06, 0xD0, 0x07,
+	0xD0, 0x07, 0xD0, 0x07, 0x02, 0x00, 0x02, 0x00, 0x04, 0x00, 0x08, 0x00, 0x0C, 0x00, 0x12, 0x00,
+	0x18, 0x00, 0x24, 0x00, 0x30, 0x00, 0x48, 0x00, 0x60, 0x00, 0x6C, 0x00, 0x28, 0x00, 0x32, 0x00,
+	0x3C, 0x00, 0x50, 0x00, 0x78, 0x00, 0xA0, 0x00, 0xC8, 0x00, 0xF0, 0x00, 0x64, 0x00, 0x78, 0x00,
+	0xA0, 0x00, 0xC8, 0x00, 0x2C, 0x01, 0x90, 0x01, 0x58, 0x02, 0x20, 0x03, 0x64, 0x00, 0x8C, 0x00,
+	0xF0, 0x00, 0xFA, 0x00, 0xC2, 0x01, 0x90, 0x01, 0x58, 0x02, 0x20, 0x03, 0x64, 0x00, 0x8C, 0x00,
+	0xF0, 0x00, 0x68, 0x01, 0xF4, 0x01, 0x20, 0x03, 0xE8, 0x03, 0x78, 0x05, 0x1E, 0x00, 0x32, 0x00,
+	0x3C, 0x00, 0x50, 0x00, 0x78, 0x00, 0xA0, 0x00, 0xC8, 0x00, 0xF0, 0x00, 0x2C, 0x01, 0x90, 0x01,
+	0x3C, 0x00, 0x78, 0x00, 0xB4, 0x00, 0xD2, 0x00, 0xF0, 0x00, 0x0E, 0x01, 0x2C, 0x01, 0x90, 0x01,
+	0xF4, 0x01, 0x58, 0x02, 0x5A, 0x00, 0x96, 0x00, 0xD2, 0x00, 0xF0, 0x00, 0x0E, 0x01, 0x2C, 0x01,
+	0x90, 0x01, 0xF4, 0x01, 0x58, 0x02, 0xBC, 0x02, 0x64, 0x00, 0x8C, 0x00, 0xF0, 0x00, 0x68, 0x01,
+	0xF4, 0x01, 0x58, 0x02, 0x20, 0x03, 0xE8, 0x03, 0xE8, 0x03, 0xE8, 0x03, 0x01, 0x00, 0x02, 0x00,
+	0x05, 0x00, 0x0B, 0x00, 0x06, 0x00, 0x09, 0x00, 0x0C, 0x00, 0x12, 0x00, 0x18, 0x00, 0x24, 0x00,
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+	0x7A, 0x00, 0x87, 0x00, 0x1B, 0x00, 0x36, 0x00, 0x51, 0x00, 0x6C, 0x00, 0xA2, 0x00, 0xD8, 0x00,
+	0xF3, 0x00, 0x0E, 0x01, 0x29, 0x00, 0x51, 0x00, 0x7A, 0x00, 0xA2, 0x00, 0xF3, 0x00, 0x44, 0x01,
+	0x6D, 0x01, 0x95, 0x01, 0x36, 0x00, 0x6C, 0x00, 0xA2, 0x00, 0xD8, 0x00, 0x44, 0x01, 0xB0, 0x01,
+	0xE6, 0x01, 0x1C, 0x02, 0x0E, 0x00, 0x1B, 0x00, 0x29, 0x00, 0x36, 0x00, 0x51, 0x00, 0x6C, 0x00,
+	0x7A, 0x00, 0x87, 0x00, 0xA2, 0x00, 0xB4, 0x00, 0x1B, 0x00, 0x36, 0x00, 0x51, 0x00, 0x6C, 0x00,
+	0xA2, 0x00, 0xD8, 0x00, 0xF3, 0x00, 0xFF, 0x00, 0x23, 0x01, 0x44, 0x01, 0x29, 0x00, 0x51, 0x00,
+	0x7A, 0x00, 0xA2, 0x00, 0xF3, 0x00, 0x44, 0x01, 0x64, 0x01, 0x64, 0x01, 0xB5, 0x01, 0xE6, 0x01,
+	0x36, 0x00, 0x6C, 0x00, 0xA2, 0x00, 0xD8, 0x00, 0x44, 0x01, 0xB0, 0x01, 0xE6, 0x01, 0x1C, 0x02,
+	0x88, 0x02, 0xD0, 0x02, 0x14, 0x14, 0x15, 0x15, 0x16, 0x17, 0x17, 0x18, 0x1C, 0x1C, 0x1C, 0x1C,
+	0x1D, 0x1D, 0x1E, 0x1E, 0x1C, 0x1C, 0x1D, 0x1E, 0x1F, 0x20, 0x20, 0x20, 0x36, 0x36, 0x37, 0x37,
+	0x38, 0x39, 0x39, 0x3A, 0x3A, 0x3A, 0x00, 0x00, 0x40, 0x40, 0x40, 0x40, 0x41, 0x41, 0x42, 0x42,
+	0x43, 0x43, 0x00, 0x00, 0x40, 0x40, 0x41, 0x42, 0x43, 0x44, 0x44, 0x44, 0x45, 0x46, 0x00, 0x00,
+	0x00, 0xF0, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF0, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0xF0, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF0, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00,
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+	0x18, 0x00, 0x00, 0x00, 0x00, 0x83, 0x01, 0x06, 0x80, 0x03, 0x00, 0x00, 0x00, 0x00, 0x70, 0xE0,
+	0x00, 0x05, 0x00, 0x00, 0x64, 0x01, 0x64, 0xB8, 0xFC, 0x10, 0x60, 0xB8, 0xFF, 0xFF, 0xFF, 0x00,
+	0xFF, 0xFF, 0x07, 0x00, 0xEC, 0x10, 0x60, 0xB8, 0xFA, 0xFA, 0xFA, 0xFA, 0x4C, 0x04, 0x64, 0xB8,
+	0x50, 0x04, 0x64, 0xB8, 0x84, 0x04, 0x64, 0xB8, 0x88, 0x04, 0x64, 0xB8, 0x8C, 0x04, 0x64, 0xB8,
+	0x90, 0x04, 0x64, 0xB8, 0x94, 0x04, 0x64, 0xB8, 0x98, 0x04, 0x64, 0xB8, 0x9C, 0x04, 0x64, 0xB8,
+	0xA0, 0x04, 0x64, 0xB8, 0xA4, 0x04, 0x64, 0xB8, 0xA8, 0x04, 0x64, 0xB8, 0xD0, 0x04, 0x64, 0xB8,
+	0xA5, 0x2E, 0x5A, 0xE2, 0x06, 0x00, 0x00, 0x00, 0x05, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00,
+	0x40, 0x00, 0x00, 0x00, 0x00, 0x01, 0x10, 0x00, 0x00, 0x09, 0x3D, 0x00, 0xFC, 0x10, 0x60, 0xB8,
+	0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0xFF, 0xFF, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x60, 0xB8,
+	0x00, 0x00, 0x64, 0xB8, 0x0D, 0x00, 0x78, 0xB8, 0x12, 0x00, 0x78, 0xB8, 0x11, 0x00, 0x78, 0xB8,
+	0x06, 0x00, 0x78, 0xB8, 0xA7, 0x04, 0x64, 0xB8, 0xA6, 0x04, 0x64, 0xB8, 0xA5, 0x04, 0x64, 0xB8,
+	0xA4, 0x04, 0x64, 0xB8, 0x14, 0x00, 0x78, 0xB8, 0x09, 0x00, 0x78, 0xB8, 0x31, 0x00, 0x78, 0xB8,
+	0x1D, 0x04, 0x64, 0xB8, 0x22, 0x05, 0x64, 0xB8, 0x00, 0x00, 0x64, 0xB8, 0x00, 0x00, 0x60, 0xB8,
+	0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x42, 0xE0, 0x00, 0x60, 0xB8, 0xFF, 0xFF, 0xFF, 0xFD,
+	0xE3, 0x00, 0x60, 0xB8, 0x53, 0x5B, 0x03, 0x80, 0x5B, 0x5B, 0x03, 0x80, 0x63, 0x5B, 0x03, 0x80,
+	0x6B, 0x5B, 0x03, 0x80, 0x73, 0x5B, 0x03, 0x80, 0x7B, 0x5B, 0x03, 0x80, 0xFF, 0xFF, 0x03, 0x00,
+	0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x04, 0xFF, 0xFF, 0xFF, 0xFB, 0x00, 0x00, 0x00, 0x20,
+	0xFF, 0xFF, 0xFF, 0xDF, 0x00, 0x00, 0x60, 0xB8, 0xFF, 0xFF, 0xFF, 0x1F, 0x00, 0x00, 0x64, 0xB8,
+	0x04, 0x00, 0x60, 0xB8, 0x04, 0x00, 0x64, 0xB8, 0x08, 0x00, 0x60, 0xB8, 0x08, 0x00, 0x64, 0xB8,
+	0xF8, 0x10, 0x60, 0xB8, 0xE8, 0x12, 0x64, 0xB8, 0x24, 0x00, 0x60, 0xB8, 0x80, 0x00, 0x60, 0xB8,
+	0x50, 0x14, 0x60, 0xB8, 0x50, 0x14, 0x64, 0xB8, 0xFC, 0x10, 0x60, 0xB8, 0xCC, 0x07, 0x64, 0xB8,
+	0x00, 0x0C, 0x01, 0x00, 0x00, 0x00, 0x60, 0xB8, 0x00, 0x00, 0x64, 0xB8, 0x01, 0x00, 0x66, 0xB8,
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+	0x62, 0x58, 0x2C, 0x20, 0x20, 0x5B, 0x32, 0x5D, 0x3D, 0x30, 0x78, 0x25, 0x62, 0x58, 0x2C, 0x20,
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+	0xE7, 0x19, 0x10, 0x80, 0xAD, 0x19, 0x10, 0x80, 0xB7, 0x19, 0x10, 0x80, 0xC1, 0x19, 0x10, 0x80,
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+	0xFF, 0xFF, 0x3F, 0x00, 0x1F, 0x00, 0x60, 0xB8, 0x04, 0x1C, 0x66, 0xB8, 0xFF, 0xFF, 0xFF, 0x3F,
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+	0x30, 0xF0, 0x20, 0x6A, 0xA0, 0xF6, 0x50, 0x9A, 0x49, 0xE4, 0x80, 0xA2, 0xFF, 0x6A, 0x8C, 0xEA,
+	0x00, 0xF6, 0x40, 0x32, 0x00, 0xF6, 0x43, 0x32, 0xBD, 0x67, 0x82, 0xA5, 0x01, 0x6D, 0xC5, 0x67,
+	0xC4, 0xEC, 0x86, 0x67, 0x00, 0xF6, 0x80, 0x34, 0x00, 0xF6, 0x83, 0x34, 0x8F, 0xEC, 0x00, 0xF6,
+	0x80, 0x34, 0x00, 0xF6, 0x83, 0x34, 0x8C, 0xEA, 0x00, 0xF6, 0x40, 0x34, 0x00, 0xF6, 0x83, 0x34,
+	0xFF, 0x6A, 0x8C, 0xEA, 0x40, 0xC3, 0x14, 0x11, 0x5D, 0x67, 0x60, 0xAA, 0x30, 0xF0, 0x20, 0x6A,
+	0xA0, 0xF6, 0x50, 0x9A, 0x49, 0xE3, 0x62, 0x67, 0xBD, 0x67, 0x80, 0xAD, 0x1F, 0xF7, 0x00, 0x6A,
+	0x8C, 0xEA, 0x02, 0xF0, 0x00, 0x6E, 0xCE, 0xEA, 0x06, 0x22, 0x5D, 0x67, 0x80, 0xAA, 0x1F, 0xF7,
+	0x00, 0x6A, 0x8C, 0xEA, 0x0F, 0x2A, 0xBD, 0x67, 0x80, 0xAD, 0x30, 0xF0, 0x20, 0x6A, 0xA0, 0xF6,
+	0x4C, 0x9A, 0x49, 0xE4, 0x80, 0xA2, 0xFF, 0x6A, 0x8C, 0xEA, 0x00, 0xF6, 0x40, 0x32, 0x00, 0xF6,
+	0x43, 0x32, 0x0E, 0x10, 0xDD, 0x67, 0x80, 0xAE, 0x30, 0xF0, 0x20, 0x6A, 0xA0, 0xF6, 0x50, 0x9A,
+	0x49, 0xE4, 0x80, 0xA2, 0xFF, 0x6A, 0x8C, 0xEA, 0x00, 0xF6, 0x40, 0x32, 0x00, 0xF6, 0x43, 0x32,
+	0xBD, 0x67, 0x82, 0xA5, 0x01, 0x6D, 0xC5, 0x67, 0xC4, 0xEC, 0x86, 0x67, 0x00, 0xF6, 0x80, 0x34,
+	0x00, 0xF6, 0x83, 0x34, 0x8F, 0xEC, 0x00, 0xF6, 0x80, 0x34, 0x00, 0xF6, 0x83, 0x34, 0x8C, 0xEA,
+	0x00, 0xF6, 0x40, 0x34, 0x00, 0xF6, 0x83, 0x34, 0xFF, 0x6A, 0x8C, 0xEA, 0x40, 0xC3, 0xC8, 0x10,
+	0x5D, 0x67, 0x83, 0xA2, 0xBD, 0x67, 0x63, 0xA5, 0x30, 0xF0, 0x20, 0x6A, 0x83, 0xF2, 0x10, 0x4A,
+	0x49, 0xE3, 0x82, 0xF4, 0x49, 0xA2, 0x00, 0xF6, 0x40, 0x33, 0x00, 0xF6, 0x63, 0x33, 0xDD, 0x67,
+	0x42, 0xA6, 0x01, 0x6D, 0xC5, 0x67, 0xC4, 0xEA, 0x46, 0x67, 0x00, 0xF6, 0x40, 0x32, 0x00, 0xF6,
+	0x43, 0x32, 0x4F, 0xEA, 0x00, 0xF6, 0x40, 0x32, 0x00, 0xF6, 0x43, 0x32, 0x6C, 0xEA, 0x00, 0xF6,
+	0x40, 0x33, 0x00, 0xF6, 0x63, 0x33, 0xFF, 0x6A, 0x4C, 0xEB, 0x30, 0xF0, 0x20, 0x6A, 0x83, 0xF2,
+	0x10, 0x4A, 0x49, 0xE4, 0x82, 0xF4, 0x69, 0xC2, 0x5D, 0x67, 0x60, 0xAA, 0x1F, 0xF7, 0x00, 0x6A,
+	0x6C, 0xEA, 0x02, 0xF0, 0x00, 0x6B, 0x6E, 0xEA, 0x06, 0x22, 0x9D, 0x67, 0x60, 0xAC, 0x1F, 0xF7,
+	0x00, 0x6A, 0x6C, 0xEA, 0x47, 0x2A, 0xBD, 0x67, 0x60, 0xAD, 0x30, 0xF0, 0x20, 0x6A, 0xA0, 0xF6,
+	0x4C, 0x9A, 0x49, 0xE3, 0x62, 0x67, 0xDD, 0x67, 0x80, 0xAE, 0x1F, 0xF7, 0x00, 0x6A, 0x8C, 0xEA,
+	0x02, 0xF0, 0x00, 0x6C, 0x8E, 0xEA, 0x06, 0x22, 0xBD, 0x67, 0x80, 0xAD, 0x1F, 0xF7, 0x00, 0x6A,
+	0x8C, 0xEA, 0x0F, 0x2A, 0xDD, 0x67, 0x80, 0xAE, 0x30, 0xF0, 0x20, 0x6A, 0xA0, 0xF6, 0x4C, 0x9A,
+	0x49, 0xE4, 0x80, 0xA2, 0xFF, 0x6A, 0x8C, 0xEA, 0x00, 0xF6, 0x40, 0x32, 0x00, 0xF6, 0x43, 0x32,
+	0x0E, 0x10, 0x5D, 0x67, 0x80, 0xAA, 0x30, 0xF0, 0x20, 0x6A, 0xA0, 0xF6, 0x50, 0x9A, 0x49, 0xE4,
+	0x80, 0xA2, 0xFF, 0x6A, 0x8C, 0xEA, 0x00, 0xF6, 0x40, 0x32, 0x00, 0xF6, 0x43, 0x32, 0xBD, 0x67,
+	0x82, 0xA5, 0x01, 0x6D, 0xC5, 0x67, 0xC4, 0xEC, 0x86, 0x67, 0x00, 0xF6, 0x80, 0x34, 0x00, 0xF6,
+	0x83, 0x34, 0x8D, 0xEA, 0x00, 0xF6, 0x40, 0x34, 0x00, 0xF6, 0x83, 0x34, 0xFF, 0x6A, 0x8C, 0xEA,
+	0x40, 0xC3, 0x46, 0x10, 0x5D, 0x67, 0x60, 0xAA, 0x30, 0xF0, 0x20, 0x6A, 0xA0, 0xF6, 0x50, 0x9A,
+	0x49, 0xE3, 0x62, 0x67, 0xBD, 0x67, 0x80, 0xAD, 0x1F, 0xF7, 0x00, 0x6A, 0x8C, 0xEA, 0x02, 0xF0,
+	0x00, 0x6E, 0xCE, 0xEA, 0x06, 0x22, 0x5D, 0x67, 0x80, 0xAA, 0x1F, 0xF7, 0x00, 0x6A, 0x8C, 0xEA,
+	0x0F, 0x2A, 0xBD, 0x67, 0x80, 0xAD, 0x30, 0xF0, 0x20, 0x6A, 0xA0, 0xF6, 0x4C, 0x9A, 0x49, 0xE4,
+	0x80, 0xA2, 0xFF, 0x6A, 0x8C, 0xEA, 0x00, 0xF6, 0x40, 0x32, 0x00, 0xF6, 0x43, 0x32, 0x0E, 0x10,
+	0xDD, 0x67, 0x80, 0xAE, 0x30, 0xF0, 0x20, 0x6A, 0xA0, 0xF6, 0x50, 0x9A, 0x49, 0xE4, 0x80, 0xA2,
+	0xFF, 0x6A, 0x8C, 0xEA, 0x00, 0xF6, 0x40, 0x32, 0x00, 0xF6, 0x43, 0x32, 0xBD, 0x67, 0x82, 0xA5,
+	0x01, 0x6D, 0xC5, 0x67, 0xC4, 0xEC, 0x86, 0x67, 0x00, 0xF6, 0x80, 0x34, 0x00, 0xF6, 0x83, 0x34,
+	0x8D, 0xEA, 0x00, 0xF6, 0x40, 0x34, 0x00, 0xF6, 0x83, 0x34, 0xFF, 0x6A, 0x8C, 0xEA, 0x40, 0xC3,
+	0x01, 0x63, 0x20, 0xE8, 0xFF, 0x63, 0x44, 0x67, 0x7D, 0x67, 0x48, 0xC3, 0x9D, 0x67, 0x48, 0xA4,
+	0x4E, 0x32, 0x7D, 0x67, 0x41, 0xC3, 0x9D, 0x67, 0x68, 0xA4, 0x07, 0x6A, 0x6C, 0xEA, 0x7D, 0x67,
+	0x40, 0xC3, 0x9D, 0x67, 0x61, 0xA4, 0x30, 0xF0, 0x20, 0x6A, 0x83, 0xF2, 0x10, 0x4A, 0x49, 0xE3,
+	0x82, 0xF4, 0x49, 0xA2, 0x62, 0x67, 0x9D, 0x67, 0x40, 0xA4, 0x67, 0xEA, 0x01, 0x6A, 0x4C, 0xEB,
+	0xFF, 0x6A, 0x6C, 0xEA, 0x02, 0x22, 0x01, 0x6A, 0x01, 0x10, 0x00, 0x6A, 0x01, 0x63, 0x20, 0xE8,
+	0xFF, 0x63, 0x02, 0xD4, 0x00, 0x6A, 0x7D, 0x67, 0x40, 0xC3, 0x02, 0x93, 0x30, 0xF0, 0x20, 0x6A,
+	0xA0, 0xF6, 0x54, 0x9A, 0x49, 0xE3, 0x02, 0x94, 0x30, 0xF0, 0x20, 0x6B, 0xA0, 0xF6, 0x74, 0x9B,
+	0x6D, 0xE4, 0x80, 0xA3, 0xFF, 0x6B, 0x6C, 0xEC, 0x01, 0x6B, 0x6D, 0xEC, 0xFF, 0x6B, 0x8C, 0xEB,
+	0x60, 0xC2, 0x02, 0x93, 0x30, 0xF0, 0x20, 0x6A, 0xA0, 0xF6, 0x54, 0x9A, 0x49, 0xE3, 0x62, 0x67,
+	0x02, 0x94, 0x30, 0xF0, 0x20, 0x6A, 0xA0, 0xF6, 0x54, 0x9A, 0x49, 0xE4, 0x80, 0xA2, 0xFF, 0x6A,
+	0x8C, 0xEA, 0xFB, 0x6C, 0x8C, 0xEA, 0x40, 0xC3, 0x02, 0x93, 0x30, 0xF0, 0x20, 0x6A, 0xA0, 0xF6,
+	0x58, 0x9A, 0x49, 0xE3, 0x02, 0x94, 0x30, 0xF0, 0x20, 0x6B, 0xA0, 0xF6, 0x78, 0x9B, 0x6D, 0xE4,
+	0x80, 0xA3, 0xFF, 0x6B, 0x6C, 0xEC, 0x06, 0x6B, 0x6B, 0xEB, 0x6D, 0xEC, 0xFF, 0x6B, 0x8C, 0xEB,
+	0x60, 0xC2, 0x02, 0x93, 0x30, 0xF0, 0x20, 0x6A, 0xA0, 0xF6, 0x5C, 0x9A, 0x49, 0xE3, 0x02, 0x94,
+	0x30, 0xF0, 0x20, 0x6B, 0xA0, 0xF6, 0x7C, 0x9B, 0x6D, 0xE4, 0x80, 0xA3, 0xFF, 0x6B, 0x6C, 0xEC,
+	0x1F, 0x6B, 0x6D, 0xEC, 0xFF, 0x6B, 0x8C, 0xEB, 0x60, 0xC2, 0x02, 0x93, 0x30, 0xF0, 0x20, 0x6A,
+	0xC0, 0xF6, 0x40, 0x9A, 0x49, 0xE3, 0x02, 0x94, 0x30, 0xF0, 0x20, 0x6B, 0xC0, 0xF6, 0x60, 0x9B,
+	0x6D, 0xE4, 0x80, 0xA3, 0xFF, 0x6B, 0x6C, 0xEC, 0x0E, 0x6B, 0x6D, 0xEC, 0xFF, 0x6B, 0x8C, 0xEB,
+	0x60, 0xC2, 0x30, 0xF0, 0x20, 0x6A, 0xC0, 0xF6, 0x44, 0x9A, 0x00, 0x6B, 0x60, 0xC2, 0x30, 0xF0,
+	0x20, 0x6A, 0xC0, 0xF6, 0x48, 0x9A, 0x00, 0x6B, 0x60, 0xC2, 0x30, 0xF0, 0x20, 0x6A, 0xC0, 0xF6,
+	0x4C, 0x9A, 0x01, 0x6B, 0x6B, 0xEB, 0x60, 0xC2, 0x30, 0xF0, 0x20, 0x6A, 0xC0, 0xF6, 0x50, 0x9A,
+	0x03, 0x6B, 0x6B, 0xEB, 0x60, 0xC2, 0x02, 0x93, 0x30, 0xF0, 0x20, 0x6A, 0xC0, 0xF6, 0x54, 0x9A,
+	0x49, 0xE3, 0x02, 0x94, 0x30, 0xF0, 0x20, 0x6B, 0xC0, 0xF6, 0x74, 0x9B, 0x6D, 0xE4, 0x80, 0xA3,
+	0xFF, 0x6B, 0x8C, 0xEB, 0x00, 0xF6, 0x60, 0x34, 0x00, 0xF6, 0x83, 0x34, 0x40, 0x6B, 0x6B, 0xEB,
+	0x8C, 0xEB, 0x00, 0xF6, 0x60, 0x34, 0x00, 0xF6, 0x83, 0x34, 0xBD, 0x67, 0x60, 0x85, 0x8D, 0xEB,
+	0x00, 0xF6, 0x60, 0x34, 0x00, 0xF6, 0x83, 0x34, 0xFF, 0x6B, 0x8C, 0xEB, 0x60, 0xC2, 0x01, 0x63,
+	0x20, 0xE8, 0x00, 0x65, 0xFF, 0x63, 0x64, 0x67, 0x03, 0xD5, 0x46, 0x67, 0x9D, 0x67, 0x68, 0xC4,
+	0x7D, 0x67, 0x50, 0xC3, 0x03, 0x93, 0x30, 0xF0, 0x20, 0x6A, 0xC0, 0xF6, 0x58, 0x9A, 0x49, 0xE3,
+	0x62, 0x67, 0x03, 0x94, 0x30, 0xF0, 0x20, 0x6A, 0xC0, 0xF6, 0x58, 0x9A, 0x49, 0xE4, 0x80, 0xA2,
+	0xFF, 0x6A, 0x8C, 0xEA, 0x3F, 0x6C, 0x8C, 0xEA, 0x40, 0xC3, 0x9D, 0x67, 0x48, 0xA4, 0x2A, 0x22,
+	0x03, 0x93, 0x30, 0xF0, 0x20, 0x6A, 0xC0, 0xF6, 0x5C, 0x9A, 0x49, 0xE3, 0x03, 0x94, 0x30, 0xF0,
+	0x20, 0x6B, 0xC0, 0xF6, 0x7C, 0x9B, 0x6D, 0xE4, 0x80, 0xA3, 0xFF, 0x6B, 0x6C, 0xEC, 0x10, 0x6B,
+	0x6D, 0xEC, 0xFF, 0x6B, 0x8C, 0xEB, 0x60, 0xC2, 0x03, 0x93, 0x30, 0xF0, 0x20, 0x6A, 0xC0, 0xF6,
+	0x58, 0x9A, 0x49, 0xE3, 0x03, 0x94, 0x30, 0xF0, 0x20, 0x6B, 0xC0, 0xF6, 0x78, 0x9B, 0x6D, 0xE4,
+	0x80, 0xA3, 0xFF, 0x6B, 0x6C, 0xEC, 0x80, 0x6B, 0x6B, 0xEB, 0x6D, 0xEC, 0xFF, 0x6B, 0x8C, 0xEB,
+	0x60, 0xC2, 0x27, 0x10, 0x03, 0x93, 0x30, 0xF0, 0x20, 0x6A, 0xC0, 0xF6, 0x5C, 0x9A, 0x49, 0xE3,
+	0x62, 0x67, 0x03, 0x94, 0x30, 0xF0, 0x20, 0x6A, 0xC0, 0xF6, 0x5C, 0x9A, 0x49, 0xE4, 0x80, 0xA2,
+	0xFF, 0x6A, 0x8C, 0xEA, 0xEF, 0x6C, 0x8C, 0xEA, 0x40, 0xC3, 0x03, 0x93, 0x30, 0xF0, 0x20, 0x6A,
+	0xC0, 0xF6, 0x58, 0x9A, 0x49, 0xE3, 0x03, 0x94, 0x30, 0xF0, 0x20, 0x6B, 0xC0, 0xF6, 0x78, 0x9B,
+	0x6D, 0xE4, 0x80, 0xA3, 0xFF, 0x6B, 0x6C, 0xEC, 0x40, 0x6B, 0x6D, 0xEC, 0xFF, 0x6B, 0x8C, 0xEB,
+	0x60, 0xC2, 0x03, 0x93, 0x30, 0xF0, 0x20, 0x6A, 0xC0, 0xF6, 0x54, 0x9A, 0x49, 0xE3, 0x40, 0x9A,
+	0x00, 0xD2, 0x7D, 0x67, 0x50, 0xA3, 0x80, 0xF4, 0x40, 0x32, 0x00, 0x93, 0x6D, 0xEA, 0x00, 0xD2,
+	0x03, 0x93, 0x30, 0xF0, 0x20, 0x6A, 0xC0, 0xF6, 0x54, 0x9A, 0x49, 0xE3, 0x00, 0x93, 0x60, 0xDA,
+	0x01, 0x63, 0x20, 0xE8, 0xFC, 0x63, 0x07, 0x62, 0x65, 0x67, 0x46, 0x67, 0xBD, 0x67, 0x20, 0xF0,
+	0x80, 0xC5, 0x9D, 0x67, 0x20, 0xF0, 0x64, 0xC4, 0xBD, 0x67, 0x20, 0xF0, 0x48, 0xC5, 0x30, 0xF0,
+	0x20, 0x6A, 0x83, 0xF2, 0x10, 0x4A, 0x60, 0xF0, 0x50, 0xA2, 0x61, 0x42, 0xFF, 0x6A, 0x4C, 0xEB,
+	0x30, 0xF0, 0x20, 0x6A, 0x83, 0xF2, 0x10, 0x4A, 0x60, 0xF0, 0x70, 0xC2, 0x30, 0xF0, 0x20, 0x6A,
+	0xE0, 0xF6, 0x40, 0x9A, 0x60, 0xA2, 0xFF, 0x6A, 0x6C, 0xEA, 0x52, 0x32, 0x7D, 0x67, 0x50, 0xC3,
+	0x9D, 0x67, 0x50, 0xA4, 0x37, 0x22, 0x30, 0xF0, 0x20, 0x6A, 0xE0, 0xF6, 0x44, 0x9A, 0x40, 0xA2,
+	0xBD, 0x67, 0x51, 0xC5, 0xFF, 0x6C, 0x26, 0x6D, 0x00, 0x18, 0x59, 0xE9, 0x00, 0x18, 0x31, 0xE9,
+	0x01, 0x6B, 0x6E, 0xEA, 0x20, 0x2A, 0x30, 0xF0, 0x20, 0x6A, 0x83, 0xF2, 0x10, 0x4A, 0xE0, 0xF4,
+	0x53, 0xA2, 0x62, 0x67, 0x9D, 0x67, 0x20, 0xF0, 0x44, 0xA4, 0x83, 0x67, 0x01, 0x6D, 0xC2, 0x67,
+	0x00, 0x6F, 0x00, 0x18, 0x64, 0xE9, 0x05, 0xD2, 0xBD, 0x67, 0x20, 0xF0, 0x80, 0xA5, 0x7D, 0x67,
+	0x20, 0xF0, 0x48, 0xA3, 0x05, 0x93, 0xA3, 0x67, 0xC2, 0x67, 0x00, 0x18, 0x8F, 0xD5, 0x05, 0x92,
+	0x82, 0x67, 0x00, 0x18, 0x3A, 0xD5, 0x9D, 0x67, 0x51, 0xA4, 0x82, 0x67, 0x27, 0x6D, 0x00, 0x18,
+	0x59, 0xE9, 0x20, 0x10, 0x30, 0xF0, 0x20, 0x6A, 0x83, 0xF2, 0x10, 0x4A, 0xE0, 0xF4, 0x53, 0xA2,
+	0x62, 0x67, 0xBD, 0x67, 0x20, 0xF0, 0x44, 0xA5, 0x83, 0x67, 0x01, 0x6D, 0xC2, 0x67, 0x00, 0x6F,
+	0x00, 0x18, 0x64, 0xE9, 0x05, 0xD2, 0x5D, 0x67, 0x20, 0xF0, 0x80, 0xA2, 0x7D, 0x67, 0x20, 0xF0,
+	0x48, 0xA3, 0x05, 0x93, 0xA3, 0x67, 0xC2, 0x67, 0x00, 0x18, 0x8F, 0xD5, 0x05, 0x92, 0x82, 0x67,
+	0x00, 0x18, 0x3A, 0xD5, 0x00, 0x18, 0xB2, 0xDD, 0x07, 0x97, 0x04, 0x63, 0x00, 0xEF, 0x00, 0x65,
+	0x30, 0xF0, 0x20, 0x6A, 0x83, 0xF2, 0x10, 0x4A, 0x00, 0x6B, 0x62, 0xF3, 0x7C, 0xC2, 0x30, 0xF0,
+	0x20, 0x6A, 0x83, 0xF2, 0x10, 0x4A, 0x00, 0x6B, 0x62, 0xF3, 0x7D, 0xC2, 0x30, 0xF0, 0x20, 0x6A,
+	0x83, 0xF2, 0x10, 0x4A, 0x00, 0x6B, 0x62, 0xF3, 0x7E, 0xC2, 0x30, 0xF0, 0x20, 0x6A, 0x83, 0xF2,
+	0x10, 0x4A, 0x00, 0x6B, 0x62, 0xF3, 0x7F, 0xC2, 0x20, 0xE8, 0x00, 0x65, 0xFF, 0x63, 0x02, 0xD4,
+	0x00, 0x6A, 0x00, 0xD2, 0x0E, 0x10, 0x00, 0x92, 0x02, 0x93, 0x83, 0x67, 0x86, 0xEA, 0x44, 0x67,
+	0x62, 0x67, 0x01, 0x6A, 0x4C, 0xEB, 0xFF, 0x6A, 0x6C, 0xEA, 0x08, 0x2A, 0x00, 0x92, 0x01, 0x4A,
+	0x00, 0xD2, 0x00, 0x92, 0x20, 0x5A, 0x58, 0x67, 0xEE, 0x2A, 0x01, 0x10, 0x00, 0x65, 0x00, 0x92,
+	0x01, 0x63, 0x20, 0xE8, 0xFB, 0x63, 0x09, 0x62, 0x0A, 0xD4, 0x0B, 0xD5, 0x0A, 0x93, 0x30, 0xF0,
+	0x20, 0x6A, 0xE0, 0xF6, 0x48, 0x9A, 0x49, 0xE3, 0x40, 0x9A, 0x06, 0xD2, 0x0B, 0x92, 0x82, 0x67,
+	0x00, 0x18, 0x25, 0xD6, 0x04, 0xD2, 0x06, 0x93, 0x0B, 0x92, 0x4C, 0xEB, 0x04, 0x92, 0x83, 0x67,
+	0x86, 0xEA, 0x44, 0x67, 0x05, 0xD2, 0x05, 0x92, 0x09, 0x97, 0x05, 0x63, 0x00, 0xEF, 0x00, 0x65,
+	0xFB, 0x63, 0x09, 0x62, 0x0A, 0xD4, 0x0B, 0xD5, 0x0C, 0xD6, 0x0B, 0x92, 0x01, 0x4A, 0x21, 0x22,
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+	0xFF, 0x6A, 0x6C, 0xEA, 0x74, 0x4A, 0x48, 0x33, 0xDD, 0x67, 0x40, 0xA6, 0x49, 0xE3, 0x62, 0x67,
+	0x30, 0xF0, 0x20, 0x6A, 0x42, 0xF5, 0x50, 0x9A, 0x49, 0xE3, 0x60, 0xA2, 0xFF, 0x6A, 0x4C, 0xEB,
+	0x14, 0x10, 0x30, 0xF0, 0x20, 0x6A, 0x83, 0xF2, 0x6A, 0xA2, 0xFF, 0x6A, 0x6C, 0xEA, 0x74, 0x4A,
+	0x48, 0x33, 0xDD, 0x67, 0x40, 0xA6, 0x49, 0xE3, 0x62, 0x67, 0x30, 0xF0, 0x20, 0x6A, 0x42, 0xF5,
+	0x54, 0x9A, 0x49, 0xE3, 0x60, 0xA2, 0xFF, 0x6A, 0x4C, 0xEB, 0x30, 0xF0, 0x20, 0x6A, 0xAC, 0x35,
+	0x83, 0xF2, 0x10, 0x4A, 0x49, 0xE5, 0x89, 0xE2, 0x80, 0xF3, 0x6C, 0xC2, 0x30, 0xF0, 0x20, 0x6A,
+	0x83, 0xF2, 0x10, 0x4A, 0xC0, 0xF3, 0x4D, 0xA2, 0xA2, 0x67, 0x7D, 0x67, 0x40, 0xA3, 0x84, 0x42,
+	0x30, 0xF0, 0x20, 0x6A, 0x83, 0xF2, 0x6A, 0xA2, 0xFF, 0x6A, 0x6C, 0xEA, 0x7C, 0x4A, 0x48, 0x33,
+	0xDD, 0x67, 0x40, 0xA6, 0x4D, 0xE3, 0x1F, 0xF7, 0x00, 0x6A, 0x6C, 0xEA, 0x02, 0xF0, 0x00, 0x6B,
+	0x6E, 0xEA, 0x0F, 0x22, 0x30, 0xF0, 0x20, 0x6A, 0x83, 0xF2, 0x6A, 0xA2, 0xFF, 0x6A, 0x6C, 0xEA,
+	0x7C, 0x4A, 0x48, 0x33, 0xDD, 0x67, 0x40, 0xA6, 0x4D, 0xE3, 0x1F, 0xF7, 0x00, 0x6A, 0x6C, 0xEA,
+	0x15, 0x2A, 0x30, 0xF0, 0x20, 0x6A, 0x83, 0xF2, 0x6A, 0xA2, 0xFF, 0x6A, 0x6C, 0xEA, 0x7C, 0x4A,
+	0x48, 0x33, 0xDD, 0x67, 0x40, 0xA6, 0x49, 0xE3, 0x62, 0x67, 0x30, 0xF0, 0x20, 0x6A, 0x42, 0xF5,
+	0x50, 0x9A, 0x49, 0xE3, 0x60, 0xA2, 0xFF, 0x6A, 0x4C, 0xEB, 0x14, 0x10, 0x30, 0xF0, 0x20, 0x6A,
+	0x83, 0xF2, 0x6A, 0xA2, 0xFF, 0x6A, 0x6C, 0xEA, 0x7C, 0x4A, 0x48, 0x33, 0xDD, 0x67, 0x40, 0xA6,
+	0x49, 0xE3, 0x62, 0x67, 0x30, 0xF0, 0x20, 0x6A, 0x42, 0xF5, 0x54, 0x9A, 0x49, 0xE3, 0x60, 0xA2,
+	0xFF, 0x6A, 0x4C, 0xEB, 0x30, 0xF0, 0x20, 0x6A, 0xAC, 0x35, 0x83, 0xF2, 0x10, 0x4A, 0x49, 0xE5,
+	0x89, 0xE2, 0x80, 0xF3, 0x6C, 0xC2, 0x7D, 0x67, 0x40, 0xA3, 0x01, 0x4A, 0x9D, 0x67, 0x40, 0xC4,
+	0xDD, 0x67, 0x40, 0xA6, 0x04, 0x5A, 0x58, 0x67, 0x3F, 0xF7, 0x1C, 0x2A, 0x30, 0xF0, 0x20, 0x6A,
+	0x83, 0xF2, 0x6A, 0xA2, 0xFF, 0x6A, 0x6C, 0xEA, 0x01, 0x6B, 0x83, 0x67, 0x84, 0xEA, 0x44, 0x67,
+	0x00, 0xF6, 0x40, 0x32, 0x00, 0xF6, 0x43, 0x32, 0x4F, 0xEA, 0x00, 0xF6, 0x40, 0x33, 0x00, 0xF6,
+	0x63, 0x33, 0xDD, 0x67, 0x41, 0x86, 0x6C, 0xEA, 0x00, 0xF6, 0x40, 0x32, 0x00, 0xF6, 0x43, 0x32,
+	0x7D, 0x67, 0x41, 0xC3, 0x30, 0xF0, 0x20, 0x6A, 0x42, 0xF5, 0x4C, 0x9A, 0x30, 0xF0, 0x20, 0x6B,
+	0x83, 0xF2, 0x8A, 0xA3, 0xFF, 0x6B, 0x8C, 0xEB, 0x01, 0x6C, 0x84, 0xEB, 0xFF, 0x6B, 0x8C, 0xEB,
+	0x60, 0xC2, 0x30, 0xF0, 0x20, 0x6A, 0x83, 0xF2, 0x6A, 0xA2, 0xFF, 0x6A, 0x6C, 0xEA, 0x61, 0x42,
+	0xFF, 0x6A, 0x4C, 0xEB, 0x30, 0xF0, 0x20, 0x6A, 0x83, 0xF2, 0x6A, 0xC2, 0x30, 0xF0, 0x20, 0x6A,
+	0x83, 0xF2, 0x6A, 0xA2, 0xFF, 0x6A, 0x6C, 0xEA, 0x03, 0x6B, 0x6C, 0xEA, 0x30, 0xF0, 0x20, 0x6B,
+	0x83, 0xF2, 0x4A, 0xC3, 0x30, 0xF0, 0x20, 0x6A, 0x83, 0xF2, 0x10, 0x4A, 0xC0, 0xF3, 0x4D, 0xA2,
+	0x61, 0x42, 0xFF, 0x6A, 0x4C, 0xEB, 0x30, 0xF0, 0x20, 0x6A, 0x83, 0xF2, 0x10, 0x4A, 0xC0, 0xF3,
+	0x6D, 0xC2, 0x30, 0xF0, 0x20, 0x6A, 0x83, 0xF2, 0x10, 0x4A, 0xC0, 0xF3, 0x4D, 0xA2, 0x08, 0x6C,
+	0x8E, 0xEA, 0x15, 0x2A, 0x30, 0xF0, 0x20, 0x6A, 0x83, 0xF2, 0x10, 0x4A, 0x00, 0x6B, 0xC0, 0xF3,
+	0x6D, 0xC2, 0x0D, 0x10, 0x30, 0xF0, 0x20, 0x6A, 0x02, 0xF5, 0x50, 0x9A, 0x30, 0xF0, 0x20, 0x6B,
+	0x02, 0xF5, 0x70, 0x9B, 0x80, 0x9B, 0x02, 0x6B, 0x8D, 0xEB, 0x60, 0xDA, 0x04, 0x10, 0xDD, 0x67,
+	0x41, 0xA6, 0x9F, 0xF6, 0x06, 0x2A, 0x01, 0x63, 0x20, 0xE8, 0x00, 0x65, 0xFD, 0x63, 0x05, 0x62,
+	0x30, 0xF0, 0x20, 0x6A, 0x83, 0xF2, 0x10, 0x4A, 0xC0, 0xF3, 0x6C, 0xA2, 0x30, 0xF0, 0x20, 0x6A,
+	0x83, 0xF2, 0x10, 0x4A, 0xC0, 0xF3, 0x4D, 0xA2, 0x6E, 0xEA, 0x5F, 0x22, 0x30, 0xF0, 0x20, 0x6A,
+	0x83, 0xF2, 0x10, 0x4A, 0xC0, 0xF3, 0x4C, 0xA2, 0x62, 0x67, 0x30, 0xF0, 0x20, 0x6A, 0x71, 0x4B,
+	0x6C, 0x33, 0x83, 0xF2, 0x10, 0x4A, 0x49, 0xE3, 0x44, 0xA2, 0x62, 0x67, 0x30, 0xF0, 0x20, 0x6A,
+	0x83, 0xF2, 0x10, 0x4A, 0xC0, 0xF3, 0x4C, 0xA2, 0x4C, 0x32, 0x80, 0xF3, 0x89, 0x42, 0x30, 0xF0,
+	0x20, 0x6A, 0x83, 0xF2, 0x10, 0x4A, 0x49, 0xE4, 0x04, 0x4A, 0x83, 0x67, 0xA2, 0x67, 0x00, 0x18,
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+	0xFF, 0x6A, 0x4C, 0xEB, 0x30, 0xF0, 0x20, 0x6A, 0x83, 0xF2, 0x10, 0x4A, 0xC0, 0xF3, 0x6C, 0xC2,
+	0x30, 0xF0, 0x20, 0x6A, 0x83, 0xF2, 0x10, 0x4A, 0xC0, 0xF3, 0x6C, 0xA2, 0x30, 0xF0, 0x20, 0x6A,
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+	0x83, 0xF2, 0x10, 0x4A, 0x77, 0x9A, 0x02, 0x6A, 0x4D, 0xEB, 0x30, 0xF0, 0x20, 0x6A, 0x83, 0xF2,
+	0x10, 0x4A, 0x77, 0xDA, 0x30, 0xF0, 0x20, 0x6A, 0x83, 0xF2, 0x10, 0x4A, 0xC0, 0xF3, 0x4C, 0xA2,
+	0x08, 0x6B, 0x6E, 0xEA, 0x07, 0x2A, 0x30, 0xF0, 0x20, 0x6A, 0x83, 0xF2, 0x10, 0x4A, 0x00, 0x6B,
+	0xC0, 0xF3, 0x6C, 0xC2, 0x00, 0x18, 0x0C, 0xE4, 0x01, 0x10, 0x00, 0x65, 0x05, 0x97, 0x03, 0x63,
+	0x00, 0xEF, 0x00, 0x65, 0xFB, 0x63, 0x09, 0x62, 0x19, 0x6A, 0x7D, 0x67, 0x50, 0xC3, 0x08, 0x6A,
+	0x7D, 0x67, 0x4F, 0xCB, 0x30, 0xF0, 0x20, 0x6A, 0x83, 0xF2, 0x10, 0x4A, 0xE5, 0xF2, 0x54, 0xA2,
+	0x7D, 0x67, 0x52, 0xC3, 0x30, 0xF0, 0x20, 0x6A, 0x83, 0xF2, 0x10, 0x4A, 0xE5, 0xF2, 0x55, 0xA2,
+	0x7D, 0x67, 0x53, 0xC3, 0x30, 0xF0, 0x20, 0x6A, 0x83, 0xF2, 0x10, 0x4A, 0xE5, 0xF2, 0x56, 0xA2,
+	0x00, 0xF6, 0x40, 0x33, 0x00, 0xF6, 0x63, 0x33, 0x30, 0xF0, 0x20, 0x6A, 0x83, 0xF2, 0x10, 0x4A,
+	0xE5, 0xF2, 0x58, 0xAA, 0x54, 0x32, 0x00, 0xF6, 0x40, 0x32, 0x00, 0xF6, 0x43, 0x32, 0x6D, 0xEA,
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+	0x30, 0xF0, 0x20, 0x6A, 0x83, 0xF2, 0x10, 0x4A, 0xE5, 0xF2, 0x58, 0xAA, 0x4E, 0x33, 0xFF, 0xF7,
+	0x1F, 0x6A, 0x4C, 0xEB, 0xFF, 0x6A, 0x6C, 0xEA, 0x7D, 0x67, 0x55, 0xC3, 0x30, 0xF0, 0x20, 0x6A,
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+	0x30, 0xF0, 0x20, 0x6A, 0x83, 0xF2, 0x10, 0x4A, 0xE5, 0xF2, 0x5B, 0xA2, 0x50, 0x32, 0x00, 0xF6,
+	0x40, 0x32, 0x00, 0xF6, 0x43, 0x32, 0x6D, 0xEA, 0x00, 0xF6, 0x40, 0x33, 0x00, 0xF6, 0x63, 0x33,
+	0xFF, 0x6A, 0x6C, 0xEA, 0x7D, 0x67, 0x56, 0xC3, 0x30, 0xF0, 0x20, 0x6A, 0x83, 0xF2, 0x10, 0x4A,
+	0xE5, 0xF2, 0x5C, 0xA2, 0x00, 0xF6, 0x40, 0x33, 0x00, 0xF6, 0x63, 0x33, 0x30, 0xF0, 0x20, 0x6A,
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+	0x43, 0x32, 0x6D, 0xEA, 0x00, 0xF6, 0x40, 0x33, 0x00, 0xF6, 0x63, 0x33, 0x30, 0xF0, 0x20, 0x6A,
+	0x83, 0xF2, 0x10, 0x4A, 0xE5, 0xF2, 0x5E, 0xA2, 0x48, 0x32, 0x00, 0xF6, 0x40, 0x32, 0x00, 0xF6,
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+	0x83, 0xF2, 0x10, 0x4A, 0xE5, 0xF2, 0x5F, 0xA2, 0x4C, 0x32, 0x00, 0xF6, 0x40, 0x32, 0x00, 0xF6,
+	0x43, 0x32, 0x6D, 0xEA, 0x00, 0xF6, 0x40, 0x33, 0x00, 0xF6, 0x63, 0x33, 0xFF, 0x6A, 0x6C, 0xEA,
+	0x7D, 0x67, 0x57, 0xC3, 0x30, 0xF0, 0x20, 0x6A, 0x83, 0xF2, 0x10, 0x4A, 0x05, 0xF3, 0x40, 0xA2,
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+	0x05, 0xF3, 0x41, 0xA2, 0x54, 0x32, 0x00, 0xF6, 0x40, 0x32, 0x00, 0xF6, 0x43, 0x32, 0x6D, 0xEA,
+	0x00, 0xF6, 0x40, 0x33, 0x00, 0xF6, 0x63, 0x33, 0xFF, 0x6A, 0x6C, 0xEA, 0x7D, 0x67, 0x58, 0xC3,
+	0x30, 0xF0, 0x20, 0x6A, 0x83, 0xF2, 0x10, 0x4A, 0x05, 0xF3, 0x42, 0xA2, 0x48, 0x32, 0x00, 0xF6,
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+	0x43, 0xA2, 0x58, 0x32, 0x00, 0xF6, 0x40, 0x32, 0x00, 0xF6, 0x43, 0x32, 0x6D, 0xEA, 0x00, 0xF6,
+	0x40, 0x33, 0x00, 0xF6, 0x63, 0x33, 0xFF, 0x6A, 0x6C, 0xEA, 0x7D, 0x67, 0x59, 0xC3, 0x04, 0x02,
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+	0x05, 0x97, 0x03, 0x63, 0x00, 0xEF, 0x00, 0x65, 0xFF, 0x63, 0x64, 0x67, 0x45, 0x67, 0x04, 0xD6,
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+	0x54, 0x9A, 0x4C, 0xEB, 0x9D, 0x67, 0x4C, 0xA4, 0x40, 0xF6, 0x40, 0x32, 0x4D, 0xEB, 0x30, 0xF0,
+	0x20, 0x6A, 0x62, 0xF5, 0x58, 0x9A, 0x6D, 0xEA, 0x00, 0xD2, 0x5D, 0x67, 0x64, 0xAA, 0x1F, 0xF7,
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+	0x1F, 0xF7, 0x00, 0x6A, 0x6C, 0xEA, 0x0A, 0x2A, 0x5D, 0x67, 0x64, 0xAA, 0x30, 0xF0, 0x20, 0x6A,
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+	0x30, 0xF0, 0x20, 0x6A, 0x82, 0xF5, 0x40, 0x9A, 0x49, 0xE3, 0x00, 0x93, 0x60, 0xDA, 0x01, 0x63,
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+	0x7D, 0x67, 0x4C, 0xC3, 0x9D, 0x67, 0x64, 0xAC, 0x1F, 0xF7, 0x00, 0x6A, 0x6C, 0xEA, 0x02, 0xF0,
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+	0x0A, 0x2A, 0x5D, 0x67, 0x64, 0xAA, 0x30, 0xF0, 0x20, 0x6A, 0x62, 0xF5, 0x5C, 0x9A, 0x49, 0xE3,
+	0x00, 0x6B, 0x60, 0xDA, 0x09, 0x10, 0x9D, 0x67, 0x64, 0xAC, 0x30, 0xF0, 0x20, 0x6A, 0x82, 0xF5,
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+	0x62, 0xF5, 0x54, 0x9A, 0x4C, 0xEB, 0x9D, 0x67, 0x4C, 0xA4, 0x40, 0xF6, 0x40, 0x32, 0x4D, 0xEB,
+	0x30, 0xF0, 0x20, 0x6A, 0x62, 0xF5, 0x58, 0x9A, 0x6D, 0xEA, 0x00, 0xD2, 0x5D, 0x67, 0x64, 0xAA,
+	0x1F, 0xF7, 0x00, 0x6A, 0x6C, 0xEA, 0x02, 0xF0, 0x00, 0x6B, 0x6E, 0xEA, 0x06, 0x22, 0x9D, 0x67,
+	0x64, 0xAC, 0x1F, 0xF7, 0x00, 0x6A, 0x6C, 0xEA, 0x0A, 0x2A, 0x5D, 0x67, 0x64, 0xAA, 0x30, 0xF0,
+	0x20, 0x6A, 0x62, 0xF5, 0x5C, 0x9A, 0x49, 0xE3, 0x00, 0x93, 0x60, 0xDA, 0x09, 0x10, 0x9D, 0x67,
+	0x64, 0xAC, 0x30, 0xF0, 0x20, 0x6A, 0x82, 0xF5, 0x40, 0x9A, 0x49, 0xE3, 0x00, 0x93, 0x60, 0xDA,
+	0x01, 0x63, 0x20, 0xE8, 0xFF, 0x63, 0x64, 0x67, 0x45, 0x67, 0x04, 0xD6, 0x9D, 0x67, 0x64, 0xCC,
+	0x7D, 0x67, 0x4C, 0xC3, 0x04, 0x94, 0x64, 0x67, 0x68, 0x32, 0x62, 0x67, 0x74, 0x32, 0x6B, 0xE2,
+	0x89, 0xE2, 0x40, 0x32, 0x62, 0x67, 0x30, 0xF0, 0x20, 0x6A, 0x62, 0xF5, 0x54, 0x9A, 0x4C, 0xEB,
+	0x9D, 0x67, 0x4C, 0xA4, 0x40, 0xF6, 0x40, 0x32, 0x4D, 0xEB, 0x30, 0xF0, 0x20, 0x6A, 0x62, 0xF5,
+	0x58, 0x9A, 0x6D, 0xEA, 0x00, 0xD2, 0x5D, 0x67, 0x64, 0xAA, 0x1F, 0xF7, 0x00, 0x6A, 0x6C, 0xEA,
+	0x02, 0xF0, 0x00, 0x6B, 0x6E, 0xEA, 0x06, 0x22, 0x9D, 0x67, 0x64, 0xAC, 0x1F, 0xF7, 0x00, 0x6A,
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+	0x49, 0xE3, 0x00, 0x93, 0x60, 0xDA, 0x09, 0x10, 0x9D, 0x67, 0x64, 0xAC, 0x30, 0xF0, 0x20, 0x6A,
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+	0x00, 0xD2, 0x30, 0xF0, 0x20, 0x6A, 0x83, 0xF2, 0x10, 0x4A, 0x6C, 0x9A, 0x00, 0x92, 0x4C, 0xEB,
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+	0x01, 0x6A, 0x4B, 0xEA, 0x83, 0x67, 0xA2, 0x67, 0x00, 0x18, 0x18, 0xE8, 0x62, 0x67, 0x30, 0xF0,
+	0x20, 0x6A, 0x63, 0xF2, 0x7C, 0xDA, 0x1C, 0x10, 0x06, 0x92, 0x60, 0x9A, 0x30, 0xF0, 0x20, 0x6A,
+	0xE2, 0xF3, 0x54, 0x9A, 0x6C, 0xEA, 0x12, 0x22, 0x06, 0x92, 0x41, 0x9A, 0x05, 0x5A, 0x58, 0x67,
+	0x0D, 0x2A, 0x30, 0xF0, 0x20, 0x6A, 0x62, 0x67, 0xA2, 0xF2, 0x14, 0x4B, 0x30, 0xF0, 0x20, 0x6A,
+	0xC2, 0xF2, 0x08, 0x4A, 0x83, 0x67, 0xA2, 0x67, 0x80, 0x18, 0xC9, 0x01, 0x00, 0x6A, 0x01, 0x10,
+	0x01, 0x6A, 0x05, 0x97, 0x03, 0x63, 0x00, 0xEF, 0x36, 0x23, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+
+};
+u32 array_length_tc_8821c_fw_ap = 86720;
+
+#endif
+
+void
+odm_read_firmware_tc_8821c_fw_ap(
+	struct PHY_DM_STRUCT    *p_dm_odm,
+	u8       *p_firmware,
+	u32       *p_firmware_size
+)
+{
+#if (DM_ODM_SUPPORT_TYPE & (ODM_CE))
+	*((SIZE_PTR *)p_firmware) = (SIZE_PTR)array_tc_8821c_fw_ap;
+#else
+	odm_move_memory(p_dm_odm, p_firmware, array_tc_8821c_fw_ap, array_length_tc_8821c_fw_ap);
+#endif
+	*p_firmware_size = array_length_tc_8821c_fw_ap;
+}
+
+
+#endif /* #if (defined(CONFIG_AP_WOWLAN) || (DM_ODM_SUPPORT_TYPE & (ODM_AP)) */
+
+
+#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN)) || (DM_ODM_SUPPORT_TYPE & (ODM_CE))
+
+#ifndef LOAD_FW_HEADER_FROM_DRIVER
+u8 array_tc_8821c_fw_nic[] = {
+	0x21, 0x88, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x91, 0x2D, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x01, 0x19, 0x10, 0x3B, 0xE0, 0x07, 0x00, 0x00, 0x18, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x20, 0x80, 0x78, 0x1A, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x38, 0xEE, 0x00, 0x00, 0x88, 0x7E, 0x00, 0x00, 0x00, 0x00, 0x10, 0x80, 0x00, 0x00, 0x03, 0x80,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1D, 0x4A, 0x03, 0x80, 0x15, 0x04, 0x03, 0x80,
+	0x03, 0x02, 0x01, 0xFE, 0x03, 0x03, 0x01, 0xFE, 0x03, 0x04, 0x01, 0xFE, 0x03, 0x05, 0x01, 0xFE,
+	0x03, 0x06, 0x01, 0xFE, 0x03, 0x07, 0x01, 0xFE, 0x6D, 0x7C, 0x03, 0x80, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06, 0x09, 0x0C, 0x12, 0x18, 0x24, 0x30, 0x36,
+	0x01, 0x02, 0x05, 0x0B, 0x00, 0x00, 0x00, 0x00, 0x0A, 0x08, 0x03, 0x03, 0x00, 0x04, 0x09, 0x07,
+	0x03, 0x03, 0x00, 0x04, 0x08, 0x06, 0x03, 0x02, 0x00, 0x04, 0x08, 0x05, 0x03, 0x01, 0x00, 0x04,
+	0x0D, 0x0A, 0x07, 0x05, 0x00, 0x08, 0x0C, 0x0A, 0x07, 0x04, 0x00, 0x08, 0x0B, 0x0A, 0x06, 0x05,
+	0x00, 0x08, 0x0B, 0x0A, 0x05, 0x03, 0x00, 0x08, 0x0B, 0x0A, 0x03, 0x02, 0x00, 0x08, 0x14, 0x12,
+	0x0C, 0x04, 0x00, 0x10, 0x14, 0x12, 0x09, 0x04, 0x00, 0x10, 0x24, 0x22, 0x1C, 0x12, 0x00, 0x20,
+	0x24, 0x22, 0x18, 0x0C, 0x00, 0x20, 0x24, 0x22, 0x14, 0x06, 0x00, 0x20, 0x24, 0x22, 0x0F, 0x04,
+	0x00, 0x20, 0x24, 0x21, 0x0A, 0x04, 0x00, 0x20, 0x23, 0x21, 0x0C, 0x04, 0x00, 0x20, 0x23, 0x1F,
+	0x0A, 0x04, 0x00, 0x20, 0x22, 0x1F, 0x0F, 0x04, 0x00, 0x20, 0x21, 0x1F, 0x16, 0x0C, 0x00, 0x20,
+	0x31, 0x2F, 0x20, 0x14, 0x00, 0x30, 0x31, 0x2F, 0x18, 0x10, 0x00, 0x30, 0x31, 0x2C, 0x18, 0x0C,
+	0x00, 0x30, 0x31, 0x2A, 0x14, 0x0C, 0x00, 0x30, 0x31, 0x28, 0x14, 0x00, 0x00, 0x30, 0x31, 0x24,
+	0x14, 0x00, 0x00, 0x30, 0x31, 0x1E, 0x14, 0x00, 0x00, 0x30, 0x31, 0x18, 0x0A, 0x00, 0x00, 0x30,
+	0x01, 0x02, 0x03, 0x06, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B, 0x2C, 0xFF, 0x00, 0x01, 0x02,
+	0x02, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A, 0x02, 0x02, 0x02, 0x04, 0x02, 0x04, 0x06, 0x06,
+	0x08, 0x08, 0x09, 0x09, 0x04, 0x08, 0x08, 0x08, 0x0C, 0x10, 0x10, 0x18, 0x04, 0x08, 0x08, 0x08,
+	0x0C, 0x10, 0x10, 0x18, 0x05, 0x08, 0x08, 0x09, 0x10, 0x14, 0x1C, 0x20, 0x04, 0x06, 0x08, 0x0A,
+	0x10, 0x18, 0x18, 0x20, 0x03, 0x05, 0x08, 0x09, 0x10, 0x14, 0x1C, 0x24, 0x2A, 0x2C, 0x05, 0x07,
+	0x09, 0x0A, 0x10, 0x14, 0x1C, 0x28, 0x2C, 0x30, 0x06, 0x08, 0x0A, 0x0C, 0x12, 0x18, 0x1E, 0x30,
+	0x38, 0x42, 0x0A, 0x0C, 0x0C, 0x12, 0x16, 0x1C, 0x20, 0x24, 0x24, 0x30, 0x01, 0x01, 0x01, 0x01,
+	0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08,
+	0x02, 0x04, 0x06, 0x07, 0x08, 0x0A, 0x0B, 0x0C, 0x03, 0x05, 0x06, 0x07, 0x08, 0x0A, 0x0B, 0x0C,
+	0x05, 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x02, 0x04, 0x06, 0x07, 0x08, 0x09, 0x0B, 0x0C,
+	0x0C, 0x0C, 0x03, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0B, 0x0C, 0x0C, 0x0C, 0x05, 0x06, 0x07, 0x08,
+	0x09, 0x0A, 0x0B, 0x0C, 0x0C, 0x0C, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0C, 0x0C,
+	0x36, 0x2D, 0xFF, 0x36, 0x2E, 0xFF, 0x37, 0x2F, 0xFF, 0x41, 0x38, 0x30, 0x39, 0x42, 0x31, 0x42,
+	0x3A, 0x32, 0x43, 0x3A, 0x33, 0x43, 0x3A, 0x34, 0x3A, 0x44, 0x35, 0x44, 0x3B, 0xFF, 0x37, 0x2E,
+	0x40, 0x38, 0x30, 0x41, 0x39, 0x42, 0x31, 0x3A, 0x43, 0x32, 0x3B, 0x43, 0x35, 0x3C, 0x44, 0xFF,
+	0x3D, 0x45, 0xFF, 0x3E, 0x45, 0xFF, 0x45, 0x3F, 0xFF, 0x46, 0xFF, 0xFF, 0x37, 0x41, 0x2F, 0x39,
+	0x42, 0x31, 0x43, 0x3A, 0x33, 0x44, 0x3B, 0x35, 0x45, 0x3D, 0xFF, 0x46, 0x47, 0x3E, 0x47, 0xFF,
+	0xFF, 0x48, 0xFF, 0xFF, 0x49, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x0D, 0x14, 0xFF, 0x15,
+	0x0E, 0xFF, 0x15, 0x0F, 0xFF, 0x16, 0x10, 0xFF, 0x17, 0x1E, 0x11, 0x1E, 0x18, 0x12, 0x1F, 0x18,
+	0x13, 0x18, 0x1F, 0xFF, 0x15, 0x0E, 0xFF, 0x16, 0x1D, 0x10, 0x17, 0x1E, 0x10, 0x18, 0x1E, 0x11,
+	0x19, 0x1F, 0xFF, 0x1A, 0x20, 0xFF, 0x21, 0x1B, 0xFF, 0x21, 0xFF, 0xFF, 0x15, 0x13, 0x0F, 0x17,
+	0x1E, 0x11, 0x18, 0x1F, 0x13, 0x20, 0x19, 0xFF, 0x21, 0x1B, 0xFF, 0x22, 0xFF, 0xFF, 0x23, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0x04, 0x04, 0x04, 0x36, 0x2C, 0xFF, 0x2D, 0xFF, 0xFF, 0x2E, 0x37, 0xFF,
+	0x38, 0x41, 0x2F, 0x39, 0x42, 0x30, 0x43, 0x39, 0x31, 0x42, 0x39, 0x32, 0x43, 0x3A, 0x33, 0x43,
+	0x3A, 0x34, 0x2D, 0x2C, 0xFF, 0x36, 0x2E, 0xFF, 0x37, 0x2F, 0x40, 0x38, 0x30, 0x41, 0x42, 0x33,
+	0x39, 0x43, 0x35, 0x3A, 0x3B, 0x43, 0x34, 0x44, 0x3C, 0x3B, 0x45, 0x3D, 0x3C, 0x45, 0x3E, 0x3D,
+	0x37, 0x2E, 0xFF, 0x38, 0x2F, 0x40, 0x39, 0x31, 0x41, 0x3A, 0x42, 0xFF, 0x43, 0x3B, 0xFF, 0x44,
+	0x3C, 0xFF, 0x45, 0x3D, 0x3C, 0x46, 0x3F, 0x45, 0x47, 0x46, 0x45, 0x48, 0x47, 0x47, 0x00, 0x00,
+	0x04, 0xFF, 0xFF, 0x0C, 0xFF, 0xFF, 0x0D, 0x14, 0xFF, 0x0E, 0x15, 0xFF, 0x16, 0x0F, 0xFF, 0x17,
+	0x10, 0xFF, 0x17, 0x11, 0xFF, 0x17, 0x12, 0xFF, 0x0D, 0x0C, 0xFF, 0x14, 0x0E, 0xFF, 0x15, 0x0F,
+	0xFF, 0x16, 0x1D, 0x10, 0x17, 0x1E, 0x12, 0x18, 0x1F, 0x13, 0x19, 0x20, 0x19, 0x20, 0x1A, 0x19,
+	0x14, 0x0E, 0xFF, 0x15, 0x1C, 0xFF, 0x17, 0x1D, 0x11, 0x18, 0x1E, 0x13, 0x19, 0x1F, 0x1E, 0x20,
+	0x1A, 0x1F, 0x21, 0x1B, 0x20, 0x22, 0x21, 0x1B, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x24, 0x26, 0x2A, 0x00, 0x00, 0x00, 0x1F, 0x21, 0x25, 0x27, 0x28, 0x00, 0x00, 0x00, 0x00,
+	0x23, 0x26, 0x28, 0x30, 0x00, 0x00, 0x00, 0x00, 0x23, 0x26, 0x28, 0x2A, 0x00, 0x00, 0x00, 0x00,
+	0x23, 0x26, 0x28, 0x2A, 0x00, 0x00, 0x00, 0x00, 0x24, 0x28, 0x2A, 0x2C, 0x2E, 0x30, 0x00, 0x00,
+	0x00, 0x00, 0x26, 0x29, 0x2B, 0x2D, 0x2F, 0x31, 0x00, 0x00, 0x00, 0x00, 0x28, 0x2A, 0x2C, 0x2E,
+	0x30, 0x32, 0x00, 0x00, 0x00, 0x1F, 0x23, 0x26, 0x28, 0x2A, 0x2A, 0x2A, 0x04, 0x00, 0x04, 0x00,
+	0x08, 0x00, 0x10, 0x00, 0x18, 0x00, 0x24, 0x00, 0x30, 0x00, 0x48, 0x00, 0x60, 0x00, 0x90, 0x00,
+	0xC0, 0x00, 0xD8, 0x00, 0x50, 0x00, 0x64, 0x00, 0x78, 0x00, 0xA0, 0x00, 0xF0, 0x00, 0x40, 0x01,
+	0x90, 0x01, 0xE0, 0x01, 0xC8, 0x00, 0xF0, 0x00, 0x40, 0x01, 0x90, 0x01, 0x58, 0x02, 0x20, 0x03,
+	0xB0, 0x04, 0x40, 0x06, 0xC8, 0x00, 0x18, 0x01, 0xE0, 0x01, 0xF4, 0x01, 0x84, 0x03, 0x20, 0x03,
+	0xB0, 0x04, 0x40, 0x06, 0xC8, 0x00, 0x18, 0x01, 0xE0, 0x01, 0xD0, 0x02, 0x20, 0x03, 0xE8, 0x03,
+	0xB0, 0x04, 0x40, 0x06, 0x3C, 0x00, 0x64, 0x00, 0x78, 0x00, 0xA0, 0x00, 0xF0, 0x00, 0x40, 0x01,
+	0x90, 0x01, 0xE0, 0x01, 0x58, 0x02, 0x20, 0x03, 0x78, 0x00, 0xF0, 0x00, 0x68, 0x01, 0xA4, 0x01,
+	0xE0, 0x01, 0x1C, 0x02, 0x58, 0x02, 0x20, 0x03, 0xE8, 0x03, 0xB0, 0x04, 0xB4, 0x00, 0x2C, 0x01,
+	0xA4, 0x01, 0xE0, 0x01, 0x1C, 0x02, 0x58, 0x02, 0x20, 0x03, 0xE8, 0x03, 0xB0, 0x04, 0x78, 0x05,
+	0xC8, 0x00, 0x18, 0x01, 0xE0, 0x01, 0xD0, 0x02, 0xE8, 0x03, 0xB0, 0x04, 0x40, 0x06, 0xD0, 0x07,
+	0xD0, 0x07, 0xD0, 0x07, 0x02, 0x00, 0x02, 0x00, 0x04, 0x00, 0x08, 0x00, 0x0C, 0x00, 0x12, 0x00,
+	0x18, 0x00, 0x24, 0x00, 0x30, 0x00, 0x48, 0x00, 0x60, 0x00, 0x6C, 0x00, 0x28, 0x00, 0x32, 0x00,
+	0x3C, 0x00, 0x50, 0x00, 0x78, 0x00, 0xA0, 0x00, 0xC8, 0x00, 0xF0, 0x00, 0x64, 0x00, 0x78, 0x00,
+	0xA0, 0x00, 0xC8, 0x00, 0x2C, 0x01, 0x90, 0x01, 0x58, 0x02, 0x20, 0x03, 0x64, 0x00, 0x8C, 0x00,
+	0xF0, 0x00, 0xFA, 0x00, 0xC2, 0x01, 0x90, 0x01, 0x58, 0x02, 0x20, 0x03, 0x64, 0x00, 0x8C, 0x00,
+	0xF0, 0x00, 0x68, 0x01, 0xF4, 0x01, 0x20, 0x03, 0xE8, 0x03, 0x78, 0x05, 0x1E, 0x00, 0x32, 0x00,
+	0x3C, 0x00, 0x50, 0x00, 0x78, 0x00, 0xA0, 0x00, 0xC8, 0x00, 0xF0, 0x00, 0x2C, 0x01, 0x90, 0x01,
+	0x3C, 0x00, 0x78, 0x00, 0xB4, 0x00, 0xD2, 0x00, 0xF0, 0x00, 0x0E, 0x01, 0x2C, 0x01, 0x90, 0x01,
+	0xF4, 0x01, 0x58, 0x02, 0x5A, 0x00, 0x96, 0x00, 0xD2, 0x00, 0xF0, 0x00, 0x0E, 0x01, 0x2C, 0x01,
+	0x90, 0x01, 0xF4, 0x01, 0x58, 0x02, 0xBC, 0x02, 0x64, 0x00, 0x8C, 0x00, 0xF0, 0x00, 0x68, 0x01,
+	0xF4, 0x01, 0x58, 0x02, 0x20, 0x03, 0xE8, 0x03, 0xE8, 0x03, 0xE8, 0x03, 0x01, 0x00, 0x02, 0x00,
+	0x05, 0x00, 0x0B, 0x00, 0x06, 0x00, 0x09, 0x00, 0x0C, 0x00, 0x12, 0x00, 0x18, 0x00, 0x24, 0x00,
+	0x30, 0x00, 0x36, 0x00, 0x0E, 0x00, 0x1B, 0x00, 0x29, 0x00, 0x36, 0x00, 0x51, 0x00, 0x6C, 0x00,
+	0x7A, 0x00, 0x87, 0x00, 0x1B, 0x00, 0x36, 0x00, 0x51, 0x00, 0x6C, 0x00, 0xA2, 0x00, 0xD8, 0x00,
+	0xF3, 0x00, 0x0E, 0x01, 0x29, 0x00, 0x51, 0x00, 0x7A, 0x00, 0xA2, 0x00, 0xF3, 0x00, 0x44, 0x01,
+	0x6D, 0x01, 0x95, 0x01, 0x36, 0x00, 0x6C, 0x00, 0xA2, 0x00, 0xD8, 0x00, 0x44, 0x01, 0xB0, 0x01,
+	0xE6, 0x01, 0x1C, 0x02, 0x0E, 0x00, 0x1B, 0x00, 0x29, 0x00, 0x36, 0x00, 0x51, 0x00, 0x6C, 0x00,
+	0x7A, 0x00, 0x87, 0x00, 0xA2, 0x00, 0xB4, 0x00, 0x1B, 0x00, 0x36, 0x00, 0x51, 0x00, 0x6C, 0x00,
+	0xA2, 0x00, 0xD8, 0x00, 0xF3, 0x00, 0xFF, 0x00, 0x23, 0x01, 0x44, 0x01, 0x29, 0x00, 0x51, 0x00,
+	0x7A, 0x00, 0xA2, 0x00, 0xF3, 0x00, 0x44, 0x01, 0x64, 0x01, 0x64, 0x01, 0xB5, 0x01, 0xE6, 0x01,
+	0x36, 0x00, 0x6C, 0x00, 0xA2, 0x00, 0xD8, 0x00, 0x44, 0x01, 0xB0, 0x01, 0xE6, 0x01, 0x1C, 0x02,
+	0x88, 0x02, 0xD0, 0x02, 0x14, 0x14, 0x15, 0x15, 0x16, 0x17, 0x17, 0x18, 0x1C, 0x1C, 0x1C, 0x1C,
+	0x1D, 0x1D, 0x1E, 0x1E, 0x1C, 0x1C, 0x1D, 0x1E, 0x1F, 0x20, 0x20, 0x20, 0x36, 0x36, 0x37, 0x37,
+	0x38, 0x39, 0x39, 0x3A, 0x3A, 0x3A, 0x00, 0x00, 0x40, 0x40, 0x40, 0x40, 0x41, 0x41, 0x42, 0x42,
+	0x43, 0x43, 0x00, 0x00, 0x40, 0x40, 0x41, 0x42, 0x43, 0x44, 0x44, 0x44, 0x45, 0x46, 0x00, 0x00,
+	0x00, 0xF0, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF0, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0xF0, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF0, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x30, 0xC0, 0xE0, 0x00, 0x00, 0x00, 0x00, 0x0C, 0x0E, 0x38,
+	0x18, 0x00, 0x00, 0x00, 0x00, 0x83, 0x01, 0x06, 0x80, 0x03, 0x00, 0x00, 0x00, 0x00, 0x70, 0xE0,
+	0x00, 0x05, 0x00, 0x00, 0x64, 0x01, 0x64, 0xB8, 0xFC, 0x10, 0x60, 0xB8, 0xFF, 0xFF, 0xFF, 0x00,
+	0xFF, 0xFF, 0x07, 0x00, 0xEC, 0x10, 0x60, 0xB8, 0xFA, 0xFA, 0xFA, 0xFA, 0x4C, 0x04, 0x64, 0xB8,
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+	0x49, 0xE4, 0x80, 0xA2, 0xFF, 0x6A, 0x8C, 0xEA, 0x00, 0xF6, 0x40, 0x32, 0x00, 0xF6, 0x43, 0x32,
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+	0x68, 0xC4, 0xBD, 0x67, 0x4C, 0xC5, 0xDD, 0x67, 0x48, 0xA6, 0x4E, 0x32, 0x7D, 0x67, 0x43, 0xC3,
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+	0x80, 0x34, 0x00, 0xF6, 0x83, 0x34, 0x8C, 0xEA, 0x00, 0xF6, 0x40, 0x34, 0x00, 0xF6, 0x83, 0x34,
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+	0xA0, 0xF6, 0x50, 0x9A, 0x49, 0xE3, 0x62, 0x67, 0xBD, 0x67, 0x80, 0xAD, 0x1F, 0xF7, 0x00, 0x6A,
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+	0x4C, 0x9A, 0x49, 0xE4, 0x80, 0xA2, 0xFF, 0x6A, 0x8C, 0xEA, 0x00, 0xF6, 0x40, 0x32, 0x00, 0xF6,
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+	0xBD, 0x67, 0x82, 0xA5, 0x01, 0x6D, 0xC5, 0x67, 0xC4, 0xEC, 0x86, 0x67, 0x00, 0xF6, 0x80, 0x34,
+	0x00, 0xF6, 0x83, 0x34, 0x8F, 0xEC, 0x00, 0xF6, 0x80, 0x34, 0x00, 0xF6, 0x83, 0x34, 0x8C, 0xEA,
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+	0x48, 0xA3, 0xC0, 0xF0, 0x1C, 0x2A, 0x30, 0xF0, 0x20, 0x6A, 0xA0, 0xF6, 0x54, 0x9A, 0x40, 0x9A,
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+	0x30, 0xF0, 0x20, 0x6B, 0xA3, 0xF3, 0x08, 0x4B, 0xA2, 0xF4, 0x50, 0xCB, 0xC8, 0x10, 0xBD, 0x67,
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+	0x82, 0xF4, 0x49, 0xA2, 0x00, 0xF6, 0x40, 0x33, 0x00, 0xF6, 0x63, 0x33, 0xBD, 0x67, 0x42, 0xA5,
+	0x01, 0x6D, 0xC5, 0x67, 0xC4, 0xEA, 0x46, 0x67, 0x00, 0xF6, 0x40, 0x32, 0x00, 0xF6, 0x43, 0x32,
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+	0x49, 0xE4, 0x82, 0xF4, 0x69, 0xC2, 0x5D, 0x67, 0x60, 0xAA, 0x1F, 0xF7, 0x00, 0x6A, 0x6C, 0xEA,
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+	0x6C, 0xEA, 0x47, 0x2A, 0xBD, 0x67, 0x60, 0xAD, 0x30, 0xF0, 0x20, 0x6A, 0xA0, 0xF6, 0x4C, 0x9A,
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+	0x00, 0x6C, 0x8E, 0xEA, 0x06, 0x22, 0xBD, 0x67, 0x80, 0xAD, 0x1F, 0xF7, 0x00, 0x6A, 0x8C, 0xEA,
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+	0x80, 0xA2, 0xFF, 0x6A, 0x8C, 0xEA, 0x00, 0xF6, 0x40, 0x32, 0x00, 0xF6, 0x43, 0x32, 0x0E, 0x10,
+	0x5D, 0x67, 0x80, 0xAA, 0x30, 0xF0, 0x20, 0x6A, 0xA0, 0xF6, 0x50, 0x9A, 0x49, 0xE4, 0x80, 0xA2,
+	0xFF, 0x6A, 0x8C, 0xEA, 0x00, 0xF6, 0x40, 0x32, 0x00, 0xF6, 0x43, 0x32, 0xBD, 0x67, 0x82, 0xA5,
+	0x01, 0x6D, 0xC5, 0x67, 0xC4, 0xEC, 0x86, 0x67, 0x00, 0xF6, 0x80, 0x34, 0x00, 0xF6, 0x83, 0x34,
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+	0x46, 0x10, 0x5D, 0x67, 0x60, 0xAA, 0x30, 0xF0, 0x20, 0x6A, 0xA0, 0xF6, 0x50, 0x9A, 0x49, 0xE3,
+	0x62, 0x67, 0xBD, 0x67, 0x80, 0xAD, 0x1F, 0xF7, 0x00, 0x6A, 0x8C, 0xEA, 0x02, 0xF0, 0x00, 0x6E,
+	0xCE, 0xEA, 0x06, 0x22, 0x5D, 0x67, 0x80, 0xAA, 0x1F, 0xF7, 0x00, 0x6A, 0x8C, 0xEA, 0x0F, 0x2A,
+	0xBD, 0x67, 0x80, 0xAD, 0x30, 0xF0, 0x20, 0x6A, 0xA0, 0xF6, 0x4C, 0x9A, 0x49, 0xE4, 0x80, 0xA2,
+	0xFF, 0x6A, 0x8C, 0xEA, 0x00, 0xF6, 0x40, 0x32, 0x00, 0xF6, 0x43, 0x32, 0x0E, 0x10, 0xDD, 0x67,
+	0x80, 0xAE, 0x30, 0xF0, 0x20, 0x6A, 0xA0, 0xF6, 0x50, 0x9A, 0x49, 0xE4, 0x80, 0xA2, 0xFF, 0x6A,
+	0x8C, 0xEA, 0x00, 0xF6, 0x40, 0x32, 0x00, 0xF6, 0x43, 0x32, 0xBD, 0x67, 0x82, 0xA5, 0x01, 0x6D,
+	0xC5, 0x67, 0xC4, 0xEC, 0x86, 0x67, 0x00, 0xF6, 0x80, 0x34, 0x00, 0xF6, 0x83, 0x34, 0x8D, 0xEA,
+	0x00, 0xF6, 0x40, 0x34, 0x00, 0xF6, 0x83, 0x34, 0xFF, 0x6A, 0x8C, 0xEA, 0x40, 0xC3, 0x01, 0x63,
+	0x20, 0xE8, 0x00, 0x65, 0xFF, 0x63, 0x44, 0x67, 0x7D, 0x67, 0x48, 0xC3, 0x9D, 0x67, 0x48, 0xA4,
+	0x4E, 0x32, 0x7D, 0x67, 0x41, 0xC3, 0x9D, 0x67, 0x68, 0xA4, 0x07, 0x6A, 0x6C, 0xEA, 0x7D, 0x67,
+	0x40, 0xC3, 0x9D, 0x67, 0x61, 0xA4, 0x30, 0xF0, 0x20, 0x6A, 0xA3, 0xF3, 0x08, 0x4A, 0x49, 0xE3,
+	0x82, 0xF4, 0x49, 0xA2, 0x62, 0x67, 0x9D, 0x67, 0x40, 0xA4, 0x67, 0xEA, 0x01, 0x6A, 0x4C, 0xEB,
+	0xFF, 0x6A, 0x6C, 0xEA, 0x02, 0x22, 0x01, 0x6A, 0x01, 0x10, 0x00, 0x6A, 0x01, 0x63, 0x20, 0xE8,
+	0xFD, 0x63, 0x05, 0x62, 0x30, 0xF0, 0x20, 0x6A, 0xA3, 0xF3, 0x08, 0x4A, 0xA2, 0xF4, 0x49, 0xA2,
+	0x04, 0x6B, 0x6C, 0xEA, 0x06, 0x22, 0x30, 0xF0, 0x20, 0x6A, 0xE0, 0xF6, 0x4C, 0x9A, 0x00, 0x6B,
+	0x60, 0xC2, 0x30, 0xF0, 0x20, 0x6A, 0xE0, 0xF6, 0x50, 0x9A, 0x02, 0x6B, 0x60, 0xC2, 0x30, 0xF0,
+	0x20, 0x6A, 0xE0, 0xF6, 0x54, 0x9A, 0x04, 0x6B, 0x60, 0xDA, 0x30, 0xF0, 0x20, 0x6A, 0xA3, 0xF3,
+	0x08, 0x4A, 0x02, 0xF5, 0x52, 0xA2, 0x46, 0x33, 0xFF, 0x6A, 0x6C, 0xEA, 0xFF, 0x6B, 0x59, 0x4B,
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+	0x30, 0xF0, 0x20, 0x6A, 0xA3, 0xF3, 0x08, 0x4A, 0xA2, 0xF4, 0x74, 0xC2, 0x30, 0xF0, 0x20, 0x6A,
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+	0x08, 0x4A, 0xC2, 0xF4, 0x46, 0xA2, 0x62, 0x67, 0x30, 0xF0, 0x20, 0x6A, 0xA3, 0xF3, 0x08, 0x4A,
+	0xA2, 0xF4, 0x7A, 0xCA, 0x30, 0xF0, 0x20, 0x6A, 0x00, 0xF7, 0x58, 0x9A, 0x60, 0xA2, 0xFF, 0x6A,
+	0x6C, 0xEA, 0x62, 0x67, 0x30, 0xF0, 0x20, 0x6A, 0xA3, 0xF3, 0x08, 0x4A, 0xA2, 0xF4, 0x5A, 0xAA,
+	0x6E, 0xEA, 0x0D, 0x22, 0x30, 0xF0, 0x20, 0x6A, 0x00, 0xF7, 0x58, 0x9A, 0x30, 0xF0, 0x20, 0x6B,
+	0xA3, 0xF3, 0x08, 0x4B, 0xA2, 0xF4, 0x9A, 0xAB, 0xFF, 0x6B, 0x8C, 0xEB, 0x60, 0xC2, 0x30, 0xF0,
+	0x20, 0x6A, 0xA3, 0xF3, 0x08, 0x4A, 0xA2, 0xF4, 0x8A, 0xA2, 0x41, 0x6B, 0x6B, 0xEB, 0x8C, 0xEB,
+	0xA2, 0xF4, 0x6A, 0xC2, 0x0A, 0x10, 0x30, 0xF0, 0x20, 0x6A, 0xA3, 0xF3, 0x08, 0x4A, 0xA2, 0xF4,
+	0x8A, 0xA2, 0x40, 0x6B, 0x8D, 0xEB, 0xA2, 0xF4, 0x6A, 0xC2, 0x20, 0xE8, 0x30, 0xF0, 0x20, 0x6A,
+	0xA3, 0xF3, 0x08, 0x4A, 0x04, 0x6B, 0x02, 0xF5, 0x68, 0xC2, 0x30, 0xF0, 0x20, 0x6A, 0xA3, 0xF3,
+	0x08, 0x4A, 0x03, 0x6B, 0x02, 0xF5, 0x69, 0xC2, 0x30, 0xF0, 0x20, 0x6A, 0xA3, 0xF3, 0x08, 0x4A,
+	0x64, 0x6B, 0x02, 0xF5, 0x6A, 0xCA, 0x30, 0xF0, 0x20, 0x6A, 0xA3, 0xF3, 0x08, 0x4A, 0x05, 0x6B,
+	0x02, 0xF5, 0x6C, 0xC2, 0x30, 0xF0, 0x20, 0x6A, 0xA3, 0xF3, 0x08, 0x4A, 0x05, 0x6B, 0x02, 0xF5,
+	0x6D, 0xC2, 0x20, 0xE8, 0xFC, 0x63, 0x07, 0x62, 0x00, 0x6A, 0x7D, 0x67, 0x54, 0xC3, 0x00, 0x6A,
+	0x9D, 0x67, 0x53, 0xC4, 0x00, 0x6A, 0x7D, 0x67, 0x52, 0xC3, 0x30, 0xF0, 0x20, 0x6A, 0x20, 0xF7,
+	0x54, 0x9A, 0x60, 0x9A, 0x30, 0xF0, 0x20, 0x6A, 0xA3, 0xF3, 0x08, 0x4A, 0x02, 0xF5, 0x60, 0xDA,
+	0x30, 0xF0, 0x20, 0x6A, 0xA3, 0xF3, 0x08, 0x4A, 0x02, 0xF5, 0x60, 0x9A, 0x30, 0xF0, 0x20, 0x6A,
+	0xA3, 0xF3, 0x08, 0x4A, 0x02, 0xF5, 0x44, 0x9A, 0x43, 0xEB, 0x58, 0x67, 0x80, 0xF0, 0x08, 0x2A,
+	0x30, 0xF0, 0x20, 0x6A, 0xA3, 0xF3, 0x08, 0x4A, 0xA2, 0xF4, 0x49, 0xA2, 0x01, 0x6B, 0x6C, 0xEA,
+	0x30, 0x22, 0x30, 0xF0, 0x20, 0x6A, 0xA3, 0xF3, 0x08, 0x4A, 0x02, 0xF5, 0x60, 0x9A, 0x30, 0xF0,
+	0x20, 0x6A, 0xA3, 0xF3, 0x08, 0x4A, 0x02, 0xF5, 0x44, 0x9A, 0x4B, 0xE3, 0x42, 0x33, 0x6A, 0x33,
+	0xFF, 0x6A, 0x4C, 0xEB, 0x30, 0xF0, 0x20, 0x6A, 0xA3, 0xF3, 0x08, 0x4A, 0xC2, 0xF4, 0x46, 0xA2,
+	0x4F, 0xE3, 0xFF, 0x6A, 0x4C, 0xEB, 0x30, 0xF0, 0x20, 0x6A, 0xA3, 0xF3, 0x08, 0x4A, 0xC2, 0xF4,
+	0x4B, 0xA2, 0x4D, 0xE3, 0xFF, 0x6A, 0x4C, 0xEB, 0x30, 0xF0, 0x20, 0x6A, 0xA3, 0xF3, 0x08, 0x4A,
+	0x02, 0xF5, 0x48, 0xA2, 0x4F, 0xE3, 0xFF, 0x6A, 0x6C, 0xEA, 0x0E, 0x4A, 0x7D, 0x67, 0x53, 0xC3,
+	0x26, 0x10, 0x30, 0xF0, 0x20, 0x6A, 0xA3, 0xF3, 0x08, 0x4A, 0x02, 0xF5, 0x60, 0x9A, 0x30, 0xF0,
+	0x20, 0x6A, 0xA3, 0xF3, 0x08, 0x4A, 0x02, 0xF5, 0x44, 0x9A, 0x4B, 0xE3, 0x42, 0x33, 0x6A, 0x33,
+	0xFF, 0x6A, 0x4C, 0xEB, 0x30, 0xF0, 0x20, 0x6A, 0xA3, 0xF3, 0x08, 0x4A, 0xC2, 0xF4, 0x46, 0xA2,
+	0x4F, 0xE3, 0xFF, 0x6A, 0x4C, 0xEB, 0x30, 0xF0, 0x20, 0x6A, 0xA3, 0xF3, 0x08, 0x4A, 0x02, 0xF5,
+	0x49, 0xA2, 0x4F, 0xE3, 0xFF, 0x6A, 0x6C, 0xEA, 0x0A, 0x4A, 0x9D, 0x67, 0x53, 0xC4, 0x7D, 0x67,
+	0x53, 0xA3, 0x2D, 0x5A, 0x58, 0x67, 0x24, 0x22, 0x5D, 0x67, 0x93, 0xA2, 0x5D, 0x67, 0x73, 0xA2,
+	0x30, 0xF0, 0x20, 0x6A, 0xA3, 0xF3, 0x08, 0x4A, 0x49, 0xE3, 0xC2, 0xF4, 0x4C, 0xA2, 0x61, 0x42,
+	0xFF, 0x6A, 0x4C, 0xEB, 0x30, 0xF0, 0x20, 0x6A, 0xA3, 0xF3, 0x08, 0x4A, 0x49, 0xE4, 0xC2, 0xF4,
+	0x6C, 0xC2, 0x30, 0xF0, 0x20, 0x6A, 0xA3, 0xF3, 0x08, 0x4A, 0xC2, 0xF4, 0x44, 0xA2, 0x61, 0x42,
+	0xFF, 0x6A, 0x4C, 0xEB, 0x30, 0xF0, 0x20, 0x6A, 0xA3, 0xF3, 0x08, 0x4A, 0xC2, 0xF4, 0x64, 0xC2,
+	0x30, 0xF0, 0x20, 0x6A, 0xA3, 0xF3, 0x08, 0x4A, 0xC2, 0xF4, 0x44, 0xA2, 0x62, 0x67, 0x30, 0xF0,
+	0x20, 0x6A, 0xA3, 0xF3, 0x08, 0x4A, 0x02, 0xF5, 0x4A, 0xAA, 0x43, 0xEB, 0x58, 0x67, 0x20, 0xF1,
+	0x18, 0x2A, 0x00, 0x6A, 0x7D, 0x67, 0x52, 0xC3, 0x00, 0x6A, 0x9D, 0x67, 0x54, 0xC4, 0x23, 0x10,
+	0x5D, 0x67, 0x74, 0xA2, 0x30, 0xF0, 0x20, 0x6A, 0xA3, 0xF3, 0x08, 0x4A, 0x49, 0xE3, 0xC2, 0xF4,
+	0x6C, 0xA2, 0x9D, 0x67, 0x52, 0xA4, 0x49, 0xE3, 0x7D, 0x67, 0x52, 0xC3, 0x30, 0xF0, 0x20, 0x6A,
+	0xA3, 0xF3, 0x08, 0x4A, 0x02, 0xF5, 0x4C, 0xA2, 0x9D, 0x67, 0x72, 0xA4, 0x63, 0xEA, 0x58, 0x67,
+	0x05, 0x22, 0x7D, 0x67, 0x54, 0xA3, 0x9D, 0x67, 0x51, 0xC4, 0x0A, 0x10, 0x7D, 0x67, 0x54, 0xA3,
+	0x01, 0x4A, 0x9D, 0x67, 0x54, 0xC4, 0x7D, 0x67, 0x54, 0xA3, 0x2D, 0x5A, 0x58, 0x67, 0xD8, 0x2A,
+	0x00, 0x6A, 0x7D, 0x67, 0x52, 0xC3, 0x00, 0x6A, 0x9D, 0x67, 0x54, 0xC4, 0x2B, 0x10, 0x5D, 0x67,
+	0x74, 0xA2, 0x30, 0xF0, 0x20, 0x6A, 0xA3, 0xF3, 0x08, 0x4A, 0x49, 0xE3, 0xC2, 0xF4, 0x6C, 0xA2,
+	0x9D, 0x67, 0x52, 0xA4, 0x49, 0xE3, 0x7D, 0x67, 0x52, 0xC3, 0x9D, 0x67, 0x72, 0xA4, 0x30, 0xF0,
+	0x20, 0x6A, 0xA3, 0xF3, 0x08, 0x4A, 0x02, 0xF5, 0x4A, 0xAA, 0x82, 0x67, 0x30, 0xF0, 0x20, 0x6A,
+	0xA3, 0xF3, 0x08, 0x4A, 0x02, 0xF5, 0x4C, 0xA2, 0x4B, 0xE4, 0x62, 0xEA, 0x58, 0x67, 0x05, 0x22,
+	0x7D, 0x67, 0x54, 0xA3, 0x9D, 0x67, 0x50, 0xC4, 0x0A, 0x10, 0x7D, 0x67, 0x54, 0xA3, 0x01, 0x4A,
+	0x9D, 0x67, 0x54, 0xC4, 0x7D, 0x67, 0x54, 0xA3, 0x2D, 0x5A, 0x58, 0x67, 0xD0, 0x2A, 0x30, 0xF0,
+	0x20, 0x6A, 0xA3, 0xF3, 0x08, 0x4A, 0x9D, 0x67, 0x71, 0xA4, 0xC2, 0xF4, 0x69, 0xC2, 0x30, 0xF0,
+	0x20, 0x6A, 0xA3, 0xF3, 0x08, 0x4A, 0x9D, 0x67, 0x70, 0xA4, 0xC2, 0xF4, 0x6A, 0xC2, 0x30, 0xF0,
+	0x20, 0x6A, 0xA3, 0xF3, 0x08, 0x4A, 0xC2, 0xF4, 0x49, 0xA2, 0x0A, 0x5A, 0x58, 0x67, 0x18, 0x2A,
+	0x30, 0xF0, 0x20, 0x6A, 0xA3, 0xF3, 0x08, 0x4A, 0xC2, 0xF4, 0x49, 0xA2, 0x68, 0x42, 0xFE, 0x4B,
+	0xFF, 0x6A, 0x4C, 0xEB, 0x30, 0xF0, 0x20, 0x6A, 0xA3, 0xF3, 0x08, 0x4A, 0xC2, 0xF4, 0x61, 0xC2,
+	0x30, 0xF0, 0x20, 0x6A, 0xA3, 0xF3, 0x08, 0x4A, 0x00, 0x6B, 0xC2, 0xF4, 0x60, 0xC2, 0x17, 0x10,
+	0x30, 0xF0, 0x20, 0x6A, 0xA3, 0xF3, 0x08, 0x4A, 0x00, 0x6B, 0xC2, 0xF4, 0x61, 0xC2, 0x30, 0xF0,
+	0x20, 0x6A, 0xA3, 0xF3, 0x08, 0x4A, 0xC2, 0xF4, 0x49, 0xA2, 0x0A, 0x6B, 0x4F, 0xE3, 0xFF, 0x6A,
+	0x4C, 0xEB, 0x30, 0xF0, 0x20, 0x6A, 0xA3, 0xF3, 0x08, 0x4A, 0xC2, 0xF4, 0x60, 0xC2, 0x30, 0xF0,
+	0x20, 0x6A, 0xA3, 0xF3, 0x08, 0x4A, 0xC2, 0xF4, 0x6A, 0xA2, 0x30, 0xF0, 0x20, 0x6A, 0xA3, 0xF3,
+	0x08, 0x4A, 0xC2, 0xF4, 0x49, 0xA2, 0x4F, 0xE3, 0xFF, 0x6A, 0x4C, 0xEB, 0x30, 0xF0, 0x20, 0x6A,
+	0xA3, 0xF3, 0x08, 0x4A, 0xC2, 0xF4, 0x67, 0xC2, 0x30, 0xF0, 0x20, 0x6A, 0xA3, 0xF3, 0x08, 0x4A,
+	0xA2, 0xF4, 0x49, 0xA2, 0x01, 0x6B, 0x6C, 0xEA, 0x19, 0x22, 0x30, 0xF0, 0x20, 0x6A, 0xA3, 0xF3,
+	0x08, 0x4A, 0xC2, 0xF4, 0x67, 0xA2, 0x30, 0xF0, 0x20, 0x6A, 0xA3, 0xF3, 0x08, 0x4A, 0x02, 0xF5,
+	0x48, 0xA2, 0x4D, 0xE3, 0xFF, 0x6A, 0x6C, 0xEA, 0x61, 0x42, 0xFF, 0x6A, 0x4C, 0xEB, 0x30, 0xF0,
+	0x20, 0x6A, 0xA3, 0xF3, 0x08, 0x4A, 0xC2, 0xF4, 0x67, 0xC2, 0x18, 0x10, 0x30, 0xF0, 0x20, 0x6A,
+	0xA3, 0xF3, 0x08, 0x4A, 0xC2, 0xF4, 0x67, 0xA2, 0x30, 0xF0, 0x20, 0x6A, 0xA3, 0xF3, 0x08, 0x4A,
+	0x02, 0xF5, 0x49, 0xA2, 0x4D, 0xE3, 0xFF, 0x6A, 0x6C, 0xEA, 0x61, 0x42, 0xFF, 0x6A, 0x4C, 0xEB,
+	0x30, 0xF0, 0x20, 0x6A, 0xA3, 0xF3, 0x08, 0x4A, 0xC2, 0xF4, 0x67, 0xC2, 0x30, 0xF0, 0x20, 0x6A,
+	0xA3, 0xF3, 0x08, 0x4A, 0xC2, 0xF4, 0x47, 0xA2, 0x0A, 0x5A, 0x58, 0x67, 0x07, 0x22, 0x30, 0xF0,
+	0x20, 0x6A, 0xA3, 0xF3, 0x08, 0x4A, 0x0A, 0x6B, 0xC2, 0xF4, 0x67, 0xC2, 0x30, 0xF0, 0x20, 0x6A,
+	0xA3, 0xF3, 0x08, 0x4A, 0xC2, 0xF4, 0x47, 0xA2, 0x62, 0x42, 0xFF, 0x6A, 0x4C, 0xEB, 0x30, 0xF0,
+	0x20, 0x6A, 0xA3, 0xF3, 0x08, 0x4A, 0xC2, 0xF4, 0x67, 0xC2, 0x30, 0xF0, 0x20, 0x6A, 0xA3, 0xF3,
+	0x08, 0x4A, 0xC2, 0xF4, 0x40, 0xA2, 0x82, 0x67, 0x30, 0xF0, 0x20, 0x6A, 0xA3, 0xF3, 0x08, 0x4A,
+	0xC2, 0xF4, 0x41, 0xA2, 0x62, 0x67, 0x30, 0xF0, 0x20, 0x6A, 0xA3, 0xF3, 0x08, 0x4A, 0xC2, 0xF4,
+	0x47, 0xA2, 0xA3, 0x67, 0xC2, 0x67, 0x03, 0x6F, 0x00, 0x18, 0x1C, 0xDA, 0x00, 0x6C, 0x00, 0x18,
+	0xFE, 0xDB, 0x07, 0x97, 0x04, 0x63, 0x00, 0xEF, 0xFD, 0x63, 0x05, 0x62, 0x30, 0xF0, 0x20, 0x6A,
+	0xA3, 0xF3, 0x08, 0x4A, 0xA2, 0xF4, 0x75, 0xA2, 0x30, 0xF0, 0x20, 0x6A, 0xA3, 0xF3, 0x08, 0x4A,
+	0x02, 0xF5, 0x50, 0xA2, 0x63, 0xEA, 0x58, 0x67, 0x64, 0x22, 0x30, 0xF0, 0x20, 0x6A, 0xA3, 0xF3,
+	0x08, 0x4A, 0xC2, 0xF4, 0x48, 0xA2, 0x61, 0x42, 0xFF, 0x6A, 0x4C, 0xEB, 0x30, 0xF0, 0x20, 0x6A,
+	0xA3, 0xF3, 0x08, 0x4A, 0xC2, 0xF4, 0x68, 0xC2, 0x30, 0xF0, 0x20, 0x6A, 0xA3, 0xF3, 0x08, 0x4A,
+	0xC2, 0xF4, 0x68, 0xA2, 0x30, 0xF0, 0x20, 0x6A, 0xA3, 0xF3, 0x08, 0x4A, 0x02, 0xF5, 0x4D, 0xA2,
+	0x63, 0xEA, 0x58, 0x67, 0x46, 0x2A, 0x30, 0xF0, 0x20, 0x6A, 0xA3, 0xF3, 0x08, 0x4A, 0xC2, 0xF4,
+	0x40, 0xA2, 0x61, 0x42, 0xFF, 0x6A, 0x4C, 0xEB, 0x30, 0xF0, 0x20, 0x6A, 0xA3, 0xF3, 0x08, 0x4A,
+	0xC2, 0xF4, 0x60, 0xC2, 0x30, 0xF0, 0x20, 0x6A, 0xA3, 0xF3, 0x08, 0x4A, 0xA2, 0xF4, 0x94, 0xA2,
+	0x30, 0xF0, 0x20, 0x6A, 0xA3, 0xF3, 0x08, 0x4A, 0xA2, 0xF4, 0x55, 0xA2, 0x62, 0x67, 0x43, 0x67,
+	0x44, 0x32, 0x6D, 0xE2, 0xFF, 0x6A, 0x6C, 0xEA, 0x4D, 0xE4, 0xFF, 0x6A, 0x6C, 0xEA, 0x6E, 0x42,
+	0xFF, 0x6A, 0x4C, 0xEB, 0x30, 0xF0, 0x20, 0x6A, 0xA3, 0xF3, 0x08, 0x4A, 0xC2, 0xF4, 0x67, 0xC2,
+	0x30, 0xF0, 0x20, 0x6A, 0xA3, 0xF3, 0x08, 0x4A, 0xC2, 0xF4, 0x40, 0xA2, 0x82, 0x67, 0x30, 0xF0,
+	0x20, 0x6A, 0xA3, 0xF3, 0x08, 0x4A, 0xC2, 0xF4, 0x41, 0xA2, 0x62, 0x67, 0x30, 0xF0, 0x20, 0x6A,
+	0xA3, 0xF3, 0x08, 0x4A, 0xC2, 0xF4, 0x47, 0xA2, 0xA3, 0x67, 0xC2, 0x67, 0x04, 0x6F, 0x00, 0x18,
+	0x1C, 0xDA, 0x05, 0x97, 0x03, 0x63, 0x00, 0xEF, 0xFF, 0x63, 0x44, 0x67, 0x7D, 0x67, 0x48, 0xC3,
+	0x00, 0x6A, 0x7D, 0x67, 0x40, 0xC3, 0x00, 0x6A, 0x7D, 0x67, 0x40, 0xC3, 0x0F, 0x10, 0x5D, 0x67,
+	0x60, 0xA2, 0x30, 0xF0, 0x20, 0x6A, 0xA3, 0xF3, 0x08, 0x4A, 0x49, 0xE3, 0x00, 0x6B, 0xC2, 0xF4,
+	0x6C, 0xC2, 0x7D, 0x67, 0x40, 0xA3, 0x01, 0x4A, 0x7D, 0x67, 0x40, 0xC3, 0x7D, 0x67, 0x40, 0xA3,
+	0x2D, 0x5A, 0x58, 0x67, 0xEC, 0x2A, 0x30, 0xF0, 0x20, 0x6A, 0xA3, 0xF3, 0x08, 0x4A, 0x00, 0x6B,
+	0xC2, 0xF4, 0x64, 0xC2, 0x30, 0xF0, 0x20, 0x6A, 0xA3, 0xF3, 0x08, 0x4A, 0x00, 0x6B, 0xC2, 0xF4,
+	0x68, 0xC2, 0x30, 0xF0, 0x20, 0x6A, 0xA3, 0xF3, 0x08, 0x4A, 0x00, 0x6B, 0xC2, 0xF4, 0x60, 0xC2,
+	0x7D, 0x67, 0x48, 0xA3, 0x01, 0x6B, 0x6E, 0xEA, 0x0E, 0x2A, 0x30, 0xF0, 0x20, 0x6A, 0xA3, 0xF3,
+	0x08, 0x4A, 0x2D, 0x6B, 0xC2, 0xF4, 0x69, 0xC2, 0x30, 0xF0, 0x20, 0x6A, 0xA3, 0xF3, 0x08, 0x4A,
+	0x00, 0x6B, 0xC2, 0xF4, 0x6A, 0xC2, 0x01, 0x63, 0x20, 0xE8, 0x00, 0x65, 0xFD, 0x63, 0x05, 0x62,
+	0x30, 0xF0, 0x20, 0x6A, 0xA3, 0xF3, 0x08, 0x4A, 0xA2, 0xF4, 0x44, 0xA2, 0x7F, 0x6B, 0x6C, 0xEA,
+	0x01, 0x6B, 0x6E, 0xEA, 0x1F, 0x2A, 0x30, 0xF0, 0x20, 0x6A, 0xA3, 0xF3, 0x08, 0x4A, 0xA2, 0xF4,
+	0x45, 0xA2, 0xF0, 0x6B, 0x6C, 0xEA, 0x0B, 0x22, 0x0C, 0x6C, 0x00, 0x6D, 0x00, 0x18, 0xD0, 0xD7,
+	0x00, 0x6C, 0x00, 0x6D, 0x00, 0x18, 0x2E, 0xF2, 0x00, 0x18, 0x44, 0xD5, 0x0B, 0x10, 0x30, 0xF0,
+	0x20, 0x6A, 0xA3, 0xF3, 0x08, 0x4A, 0xA2, 0xF4, 0x4C, 0xA2, 0x04, 0x2A, 0x04, 0x6C, 0x01, 0x6D,
+	0x00, 0x18, 0xD0, 0xD7, 0x05, 0x97, 0x03, 0x63, 0x00, 0xEF, 0x00, 0x65, 0xFD, 0x63, 0x05, 0x62,
+	0x30, 0xF0, 0x20, 0x6A, 0xA3, 0xF3, 0x08, 0x4A, 0xA2, 0xF4, 0x49, 0xA2, 0x40, 0x6B, 0x6C, 0xEA,
+	0x0D, 0x22, 0x30, 0xF0, 0x20, 0x6A, 0xA3, 0xF3, 0x08, 0x4A, 0xA2, 0xF4, 0x4A, 0xA2, 0x10, 0x6B,
+	0x6C, 0xEA, 0x04, 0x22, 0x02, 0x6C, 0x01, 0x6D, 0x00, 0x18, 0x8C, 0xC7, 0x30, 0xF0, 0x20, 0x6A,
+	0xA3, 0xF3, 0x08, 0x4A, 0xA2, 0xF4, 0x49, 0xA2, 0x02, 0x6B, 0x6C, 0xEA, 0x26, 0x22, 0x30, 0xF0,
+	0x20, 0x6A, 0xA3, 0xF3, 0x08, 0x4A, 0xA2, 0xF4, 0x89, 0xA2, 0x03, 0x6B, 0x6B, 0xEB, 0x8C, 0xEB,
+	0xA2, 0xF4, 0x69, 0xC2, 0x30, 0xF0, 0x20, 0x6A, 0xA3, 0xF3, 0x08, 0x4A, 0xA2, 0xF4, 0x4D, 0xA2,
+	0xFD, 0x6B, 0x6C, 0xEA, 0x30, 0xF0, 0x20, 0x6B, 0xA3, 0xF3, 0x08, 0x4B, 0xA2, 0xF4, 0x4D, 0xC3,
+	0x30, 0xF0, 0x20, 0x6A, 0xA3, 0xF3, 0x08, 0x4A, 0xA2, 0xF4, 0x4D, 0xA2, 0x62, 0x67, 0x07, 0x6A,
+	0x6C, 0xEA, 0x43, 0x2A, 0x00, 0x18, 0x8D, 0xD8, 0x40, 0x10, 0x30, 0xF0, 0x20, 0x6A, 0xA3, 0xF3,
+	0x08, 0x4A, 0xA2, 0xF4, 0x55, 0xA2, 0x61, 0x42, 0xFF, 0x6A, 0x4C, 0xEB, 0x30, 0xF0, 0x20, 0x6A,
+	0xA3, 0xF3, 0x08, 0x4A, 0xA2, 0xF4, 0x75, 0xC2, 0x30, 0xF0, 0x20, 0x6A, 0xA3, 0xF3, 0x08, 0x4A,
+	0xA2, 0xF4, 0x4D, 0xA2, 0xEF, 0x6B, 0x6C, 0xEA, 0x30, 0xF0, 0x20, 0x6B, 0xA3, 0xF3, 0x08, 0x4B,
+	0xA2, 0xF4, 0x4D, 0xC3, 0x30, 0xF0, 0x20, 0x6A, 0xA3, 0xF3, 0x08, 0x4A, 0xA2, 0xF4, 0x75, 0xA2,
+	0x30, 0xF0, 0x20, 0x6A, 0xA3, 0xF3, 0x08, 0x4A, 0x02, 0xF5, 0x50, 0xA2, 0x63, 0xEA, 0x58, 0x67,
+	0x12, 0x22, 0x00, 0x6C, 0x00, 0x18, 0x31, 0xD5, 0x01, 0x6B, 0x6E, 0xEA, 0x0E, 0x2A, 0x30, 0xF0,
+	0x20, 0x6A, 0xA3, 0xF3, 0x08, 0x4A, 0xA2, 0xF4, 0x89, 0xA2, 0x21, 0x6B, 0x6B, 0xEB, 0x8C, 0xEB,
+	0xA2, 0xF4, 0x69, 0xC2, 0x02, 0x10, 0x00, 0x18, 0x8D, 0xD8, 0x05, 0x97, 0x03, 0x63, 0x00, 0xEF,
+	0xFB, 0x63, 0x09, 0x62, 0x44, 0x67, 0x7D, 0x67, 0x20, 0xF0, 0x48, 0xC3, 0x30, 0xF0, 0x20, 0x6A,
+	0xA3, 0xF3, 0x08, 0x4A, 0xA2, 0xF4, 0x47, 0xA2, 0x04, 0x6B, 0x6C, 0xEA, 0x0F, 0x22, 0x1E, 0x6A,
+	0x7D, 0x67, 0x50, 0xC3, 0x01, 0x6A, 0x7D, 0x67, 0x4F, 0xCB, 0x7D, 0x67, 0x20, 0xF0, 0x48, 0xA3,
+	0x7D, 0x67, 0x52, 0xC3, 0x04, 0x02, 0x82, 0x67, 0x00, 0x18, 0xE0, 0xE0, 0x09, 0x97, 0x05, 0x63,
+	0x00, 0xEF, 0x00, 0x65, 0xFF, 0x63, 0x02, 0xD4, 0x00, 0x6A, 0x7D, 0x67, 0x40, 0xC3, 0x02, 0x93,
+	0x30, 0xF0, 0x20, 0x6A, 0x40, 0xF7, 0x44, 0x9A, 0x49, 0xE3, 0x02, 0x94, 0x30, 0xF0, 0x20, 0x6B,
+	0x40, 0xF7, 0x64, 0x9B, 0x6D, 0xE4, 0x80, 0xA3, 0xFF, 0x6B, 0x6C, 0xEC, 0x01, 0x6B, 0x6D, 0xEC,
+	0xFF, 0x6B, 0x8C, 0xEB, 0x60, 0xC2, 0x02, 0x93, 0x30, 0xF0, 0x20, 0x6A, 0x40, 0xF7, 0x44, 0x9A,
+	0x49, 0xE3, 0x62, 0x67, 0x02, 0x94, 0x30, 0xF0, 0x20, 0x6A, 0x40, 0xF7, 0x44, 0x9A, 0x49, 0xE4,
+	0x80, 0xA2, 0xFF, 0x6A, 0x8C, 0xEA, 0xFB, 0x6C, 0x8C, 0xEA, 0x40, 0xC3, 0x02, 0x93, 0x30, 0xF0,
+	0x20, 0x6A, 0x40, 0xF7, 0x48, 0x9A, 0x49, 0xE3, 0x02, 0x94, 0x30, 0xF0, 0x20, 0x6B, 0x40, 0xF7,
+	0x68, 0x9B, 0x6D, 0xE4, 0x80, 0xA3, 0xFF, 0x6B, 0x6C, 0xEC, 0x06, 0x6B, 0x6B, 0xEB, 0x6D, 0xEC,
+	0xFF, 0x6B, 0x8C, 0xEB, 0x60, 0xC2, 0x02, 0x93, 0x30, 0xF0, 0x20, 0x6A, 0x40, 0xF7, 0x4C, 0x9A,
+	0x49, 0xE3, 0x02, 0x94, 0x30, 0xF0, 0x20, 0x6B, 0x40, 0xF7, 0x6C, 0x9B, 0x6D, 0xE4, 0x80, 0xA3,
+	0xFF, 0x6B, 0x6C, 0xEC, 0x1F, 0x6B, 0x6D, 0xEC, 0xFF, 0x6B, 0x8C, 0xEB, 0x60, 0xC2, 0x02, 0x93,
+	0x30, 0xF0, 0x20, 0x6A, 0x40, 0xF7, 0x50, 0x9A, 0x49, 0xE3, 0x02, 0x94, 0x30, 0xF0, 0x20, 0x6B,
+	0x40, 0xF7, 0x70, 0x9B, 0x6D, 0xE4, 0x80, 0xA3, 0xFF, 0x6B, 0x6C, 0xEC, 0x0E, 0x6B, 0x6D, 0xEC,
+	0xFF, 0x6B, 0x8C, 0xEB, 0x60, 0xC2, 0x30, 0xF0, 0x20, 0x6A, 0x40, 0xF7, 0x54, 0x9A, 0x00, 0x6B,
+	0x60, 0xC2, 0x30, 0xF0, 0x20, 0x6A, 0x40, 0xF7, 0x58, 0x9A, 0x00, 0x6B, 0x60, 0xC2, 0x30, 0xF0,
+	0x20, 0x6A, 0x40, 0xF7, 0x5C, 0x9A, 0x01, 0x6B, 0x6B, 0xEB, 0x60, 0xC2, 0x30, 0xF0, 0x20, 0x6A,
+	0x60, 0xF7, 0x40, 0x9A, 0x03, 0x6B, 0x6B, 0xEB, 0x60, 0xC2, 0x02, 0x93, 0x30, 0xF0, 0x20, 0x6A,
+	0x60, 0xF7, 0x44, 0x9A, 0x49, 0xE3, 0x02, 0x94, 0x30, 0xF0, 0x20, 0x6B, 0x60, 0xF7, 0x64, 0x9B,
+	0x6D, 0xE4, 0x80, 0xA3, 0xFF, 0x6B, 0x8C, 0xEB, 0x00, 0xF6, 0x60, 0x34, 0x00, 0xF6, 0x83, 0x34,
+	0x40, 0x6B, 0x6B, 0xEB, 0x8C, 0xEB, 0x00, 0xF6, 0x60, 0x34, 0x00, 0xF6, 0x83, 0x34, 0xBD, 0x67,
+	0x60, 0x85, 0x8D, 0xEB, 0x00, 0xF6, 0x60, 0x34, 0x00, 0xF6, 0x83, 0x34, 0xFF, 0x6B, 0x8C, 0xEB,
+	0x60, 0xC2, 0x01, 0x63, 0x20, 0xE8, 0x00, 0x65, 0xFF, 0x63, 0x64, 0x67, 0x03, 0xD5, 0x46, 0x67,
+	0x9D, 0x67, 0x68, 0xC4, 0x7D, 0x67, 0x50, 0xC3, 0x03, 0x93, 0x30, 0xF0, 0x20, 0x6A, 0x60, 0xF7,
+	0x48, 0x9A, 0x49, 0xE3, 0x62, 0x67, 0x03, 0x94, 0x30, 0xF0, 0x20, 0x6A, 0x60, 0xF7, 0x48, 0x9A,
+	0x49, 0xE4, 0x80, 0xA2, 0xFF, 0x6A, 0x8C, 0xEA, 0x3F, 0x6C, 0x8C, 0xEA, 0x40, 0xC3, 0x9D, 0x67,
+	0x48, 0xA4, 0x2A, 0x22, 0x03, 0x93, 0x30, 0xF0, 0x20, 0x6A, 0x60, 0xF7, 0x4C, 0x9A, 0x49, 0xE3,
+	0x03, 0x94, 0x30, 0xF0, 0x20, 0x6B, 0x60, 0xF7, 0x6C, 0x9B, 0x6D, 0xE4, 0x80, 0xA3, 0xFF, 0x6B,
+	0x6C, 0xEC, 0x10, 0x6B, 0x6D, 0xEC, 0xFF, 0x6B, 0x8C, 0xEB, 0x60, 0xC2, 0x03, 0x93, 0x30, 0xF0,
+	0x20, 0x6A, 0x60, 0xF7, 0x48, 0x9A, 0x49, 0xE3, 0x03, 0x94, 0x30, 0xF0, 0x20, 0x6B, 0x60, 0xF7,
+	0x68, 0x9B, 0x6D, 0xE4, 0x80, 0xA3, 0xFF, 0x6B, 0x6C, 0xEC, 0x80, 0x6B, 0x6B, 0xEB, 0x6D, 0xEC,
+	0xFF, 0x6B, 0x8C, 0xEB, 0x60, 0xC2, 0x27, 0x10, 0x03, 0x93, 0x30, 0xF0, 0x20, 0x6A, 0x60, 0xF7,
+	0x4C, 0x9A, 0x49, 0xE3, 0x62, 0x67, 0x03, 0x94, 0x30, 0xF0, 0x20, 0x6A, 0x60, 0xF7, 0x4C, 0x9A,
+	0x49, 0xE4, 0x80, 0xA2, 0xFF, 0x6A, 0x8C, 0xEA, 0xEF, 0x6C, 0x8C, 0xEA, 0x40, 0xC3, 0x03, 0x93,
+	0x30, 0xF0, 0x20, 0x6A, 0x60, 0xF7, 0x48, 0x9A, 0x49, 0xE3, 0x03, 0x94, 0x30, 0xF0, 0x20, 0x6B,
+	0x60, 0xF7, 0x68, 0x9B, 0x6D, 0xE4, 0x80, 0xA3, 0xFF, 0x6B, 0x6C, 0xEC, 0x40, 0x6B, 0x6D, 0xEC,
+	0xFF, 0x6B, 0x8C, 0xEB, 0x60, 0xC2, 0x03, 0x93, 0x30, 0xF0, 0x20, 0x6A, 0x60, 0xF7, 0x44, 0x9A,
+	0x49, 0xE3, 0x40, 0x9A, 0x00, 0xD2, 0x7D, 0x67, 0x50, 0xA3, 0x80, 0xF4, 0x40, 0x32, 0x00, 0x93,
+	0x6D, 0xEA, 0x00, 0xD2, 0x03, 0x93, 0x30, 0xF0, 0x20, 0x6A, 0x60, 0xF7, 0x44, 0x9A, 0x49, 0xE3,
+	0x00, 0x93, 0x60, 0xDA, 0x01, 0x63, 0x20, 0xE8, 0xFC, 0x63, 0x07, 0x62, 0x30, 0xF0, 0x20, 0x6A,
+	0x60, 0xF7, 0x50, 0x9A, 0x60, 0xA2, 0xFF, 0x6A, 0x6C, 0xEA, 0x52, 0x32, 0x7D, 0x67, 0x51, 0xC3,
+	0x7D, 0x67, 0x51, 0xA3, 0x11, 0x2A, 0x30, 0xF0, 0x20, 0x6A, 0xA3, 0xF3, 0x08, 0x4A, 0xE0, 0xF4,
+	0x52, 0xA2, 0x82, 0x67, 0x00, 0x6D, 0x18, 0x6E, 0x00, 0x6F, 0x00, 0x18, 0x39, 0xF2, 0x05, 0xD2,
+	0x00, 0x18, 0xB0, 0xE2, 0x7D, 0x67, 0x50, 0xC3, 0x07, 0x97, 0x04, 0x63, 0x00, 0xEF, 0x00, 0x65,
+	0xFC, 0x63, 0x07, 0x62, 0x44, 0x67, 0x7D, 0x67, 0x20, 0xF0, 0x40, 0xC3, 0x30, 0xF0, 0x20, 0x6A,
+	0x60, 0xF7, 0x54, 0x9A, 0x60, 0xAA, 0xFF, 0xF7, 0x1F, 0x6A, 0x4C, 0xEB, 0xFF, 0x6A, 0x4C, 0xEB,
+	0x30, 0xF0, 0x20, 0x6A, 0x60, 0xF7, 0x58, 0x9A, 0x80, 0xAA, 0xFF, 0xF7, 0x1F, 0x6A, 0x4C, 0xEC,
+	0xFF, 0x6A, 0x8C, 0xEA, 0x4B, 0xE3, 0x9D, 0x67, 0x50, 0xC4, 0x30, 0xF0, 0x20, 0x6A, 0xA3, 0xF3,
+	0x08, 0x4A, 0xE0, 0xF4, 0x53, 0xA2, 0x9D, 0x67, 0x70, 0xA4, 0x6E, 0xEA, 0x73, 0x2A, 0x30, 0xF0,
+	0x20, 0x6A, 0xA3, 0xF3, 0x08, 0x4A, 0xA2, 0xF4, 0x4C, 0xA2, 0x0E, 0x6B, 0x6E, 0xEA, 0x26, 0x2A,
+	0x9D, 0x67, 0x20, 0xF0, 0x40, 0xA4, 0x66, 0x2A, 0x30, 0xF0, 0x20, 0x6A, 0xA3, 0xF3, 0x08, 0x4A,
+	0xA2, 0xF4, 0x8A, 0xA2, 0x03, 0x6B, 0x6B, 0xEB, 0x8C, 0xEB, 0xA2, 0xF4, 0x6A, 0xC2, 0x30, 0xF0,
+	0x20, 0x6A, 0x60, 0xF7, 0x7C, 0x9A, 0x30, 0xF0, 0x20, 0x6A, 0x60, 0xF7, 0x5C, 0x9A, 0x80, 0xA2,
+	0xFF, 0x6A, 0x8C, 0xEA, 0x7F, 0x6C, 0x8C, 0xEA, 0x40, 0xC3, 0x01, 0x6C, 0x0C, 0x6D, 0x00, 0x18,
+	0x61, 0xD5, 0x00, 0x6C, 0x00, 0x6D, 0x00, 0x18, 0x2E, 0xF2, 0x44, 0x10, 0x30, 0xF0, 0x20, 0x6A,
+	0xA3, 0xF3, 0x08, 0x4A, 0xA2, 0xF4, 0x4C, 0xA2, 0x06, 0x6B, 0x6E, 0xEA, 0x3B, 0x2A, 0x9D, 0x67,
+	0x20, 0xF0, 0x40, 0xA4, 0x37, 0x22, 0x30, 0xF0, 0x20, 0x6A, 0xA3, 0xF3, 0x08, 0x4A, 0xA2, 0xF4,
+	0x8A, 0xA2, 0x02, 0x6B, 0x6B, 0xEB, 0x8C, 0xEB, 0xA2, 0xF4, 0x6A, 0xC2, 0x30, 0xF0, 0x20, 0x6A,
+	0x60, 0xF7, 0x5C, 0x9A, 0x30, 0xF0, 0x20, 0x6B, 0x60, 0xF7, 0x7C, 0x9B, 0x80, 0xA3, 0xFF, 0x6B,
+	0x6C, 0xEC, 0x40, 0x6B, 0x6D, 0xEC, 0xFF, 0x6B, 0x8C, 0xEB, 0x60, 0xC2, 0x30, 0xF0, 0x20, 0x6A,
+	0x60, 0xF7, 0x5C, 0x9A, 0x30, 0xF0, 0x20, 0x6B, 0x60, 0xF7, 0x7C, 0x9B, 0x80, 0xA3, 0xFF, 0x6B,
+	0x6C, 0xEC, 0x80, 0x6B, 0x6B, 0xEB, 0x6D, 0xEC, 0xFF, 0x6B, 0x8C, 0xEB, 0x60, 0xC2, 0x30, 0xF0,
+	0x20, 0x6A, 0xA3, 0xF3, 0x08, 0x4A, 0x04, 0x6B, 0xA2, 0xF4, 0x6C, 0xC2, 0x00, 0x6C, 0x00, 0x6D,
+	0x00, 0x18, 0x2E, 0xF2, 0x07, 0x97, 0x04, 0x63, 0x00, 0xEF, 0x00, 0x65, 0xFC, 0x63, 0x07, 0x62,
+	0x65, 0x67, 0x46, 0x67, 0xBD, 0x67, 0x20, 0xF0, 0x80, 0xC5, 0x9D, 0x67, 0x20, 0xF0, 0x64, 0xC4,
+	0xBD, 0x67, 0x20, 0xF0, 0x48, 0xC5, 0x30, 0xF0, 0x20, 0x6A, 0xA3, 0xF3, 0x08, 0x4A, 0x60, 0xF0,
+	0x50, 0xA2, 0x61, 0x42, 0xFF, 0x6A, 0x4C, 0xEB, 0x30, 0xF0, 0x20, 0x6A, 0xA3, 0xF3, 0x08, 0x4A,
+	0x60, 0xF0, 0x70, 0xC2, 0x30, 0xF0, 0x20, 0x6A, 0x60, 0xF7, 0x50, 0x9A, 0x60, 0xA2, 0xFF, 0x6A,
+	0x6C, 0xEA, 0x52, 0x32, 0x7D, 0x67, 0x50, 0xC3, 0x9D, 0x67, 0x50, 0xA4, 0x3D, 0x22, 0x30, 0xF0,
+	0x20, 0x6A, 0x80, 0xF7, 0x40, 0x9A, 0x40, 0xA2, 0xBD, 0x67, 0x51, 0xC5, 0xFF, 0x6C, 0x26, 0x6D,
+	0x00, 0x18, 0x2E, 0xF2, 0x00, 0x18, 0x6B, 0xF1, 0x01, 0x6B, 0x6E, 0xEA, 0x20, 0x2A, 0x30, 0xF0,
+	0x20, 0x6A, 0xA3, 0xF3, 0x08, 0x4A, 0xE0, 0xF4, 0x53, 0xA2, 0x62, 0x67, 0x9D, 0x67, 0x20, 0xF0,
+	0x44, 0xA4, 0x83, 0x67, 0x01, 0x6D, 0xC2, 0x67, 0x00, 0x6F, 0x00, 0x18, 0x39, 0xF2, 0x05, 0xD2,
+	0xBD, 0x67, 0x20, 0xF0, 0x80, 0xA5, 0x7D, 0x67, 0x20, 0xF0, 0x48, 0xA3, 0x05, 0x93, 0xA3, 0x67,
+	0xC2, 0x67, 0x00, 0x18, 0xE6, 0xDC, 0x05, 0x92, 0x82, 0x67, 0x00, 0x18, 0x91, 0xDC, 0x9D, 0x67,
+	0x51, 0xA4, 0x82, 0x67, 0x27, 0x6D, 0x00, 0x18, 0x2E, 0xF2, 0xBD, 0x67, 0x20, 0xF0, 0x40, 0xA5,
+	0x82, 0x67, 0x00, 0x18, 0x3C, 0xDD, 0x26, 0x10, 0x7D, 0x67, 0x20, 0xF0, 0x40, 0xA3, 0x82, 0x67,
+	0x00, 0x18, 0x3C, 0xDD, 0x30, 0xF0, 0x20, 0x6A, 0xA3, 0xF3, 0x08, 0x4A, 0xE0, 0xF4, 0x53, 0xA2,
+	0x62, 0x67, 0x9D, 0x67, 0x20, 0xF0, 0x44, 0xA4, 0x83, 0x67, 0x01, 0x6D, 0xC2, 0x67, 0x00, 0x6F,
+	0x00, 0x18, 0x39, 0xF2, 0x05, 0xD2, 0xBD, 0x67, 0x20, 0xF0, 0x80, 0xA5, 0x7D, 0x67, 0x20, 0xF0,
+	0x48, 0xA3, 0x05, 0x93, 0xA3, 0x67, 0xC2, 0x67, 0x00, 0x18, 0xE6, 0xDC, 0x05, 0x92, 0x82, 0x67,
+	0x00, 0x18, 0x91, 0xDC, 0x00, 0x18, 0xB0, 0xE2, 0x07, 0x97, 0x04, 0x63, 0x00, 0xEF, 0x00, 0x65,
+	0x30, 0xF0, 0x20, 0x6A, 0xA3, 0xF3, 0x08, 0x4A, 0x00, 0x6B, 0x62, 0xF3, 0x7C, 0xC2, 0x30, 0xF0,
+	0x20, 0x6A, 0xA3, 0xF3, 0x08, 0x4A, 0x00, 0x6B, 0x62, 0xF3, 0x7D, 0xC2, 0x30, 0xF0, 0x20, 0x6A,
+	0xA3, 0xF3, 0x08, 0x4A, 0x00, 0x6B, 0x62, 0xF3, 0x7E, 0xC2, 0x30, 0xF0, 0x20, 0x6A, 0xA3, 0xF3,
+	0x08, 0x4A, 0x00, 0x6B, 0x62, 0xF3, 0x7F, 0xC2, 0x20, 0xE8, 0x00, 0x65, 0xFF, 0x63, 0x02, 0xD4,
+	0x00, 0x6A, 0x00, 0xD2, 0x0E, 0x10, 0x00, 0x92, 0x02, 0x93, 0x83, 0x67, 0x86, 0xEA, 0x44, 0x67,
+	0x62, 0x67, 0x01, 0x6A, 0x4C, 0xEB, 0xFF, 0x6A, 0x6C, 0xEA, 0x08, 0x2A, 0x00, 0x92, 0x01, 0x4A,
+	0x00, 0xD2, 0x00, 0x92, 0x20, 0x5A, 0x58, 0x67, 0xEE, 0x2A, 0x01, 0x10, 0x00, 0x65, 0x00, 0x92,
+	0x01, 0x63, 0x20, 0xE8, 0xFB, 0x63, 0x09, 0x62, 0x0A, 0xD4, 0x0B, 0xD5, 0x0A, 0x93, 0x30, 0xF0,
+	0x20, 0x6A, 0x80, 0xF7, 0x44, 0x9A, 0x49, 0xE3, 0x40, 0x9A, 0x06, 0xD2, 0x0B, 0x92, 0x82, 0x67,
+	0x00, 0x18, 0xE3, 0xDD, 0x04, 0xD2, 0x06, 0x93, 0x0B, 0x92, 0x4C, 0xEB, 0x04, 0x92, 0x83, 0x67,
+	0x86, 0xEA, 0x44, 0x67, 0x05, 0xD2, 0x05, 0x92, 0x09, 0x97, 0x05, 0x63, 0x00, 0xEF, 0x00, 0x65,
+	0xFB, 0x63, 0x09, 0x62, 0x0A, 0xD4, 0x0B, 0xD5, 0x0C, 0xD6, 0x0B, 0x92, 0x01, 0x4A, 0x21, 0x22,
+	0x0A, 0x93, 0x30, 0xF0, 0x20, 0x6A, 0x80, 0xF7, 0x44, 0x9A, 0x49, 0xE3, 0x40, 0x9A, 0x06, 0xD2,
+	0x0B, 0x92, 0x82, 0x67, 0x00, 0x18, 0xE3, 0xDD, 0x05, 0xD2, 0x0B, 0x92, 0x4F, 0xEB, 0x06, 0x92,
+	0x4C, 0xEB, 0x05, 0x92, 0x0C, 0x94, 0xA4, 0x67, 0xA4, 0xEA, 0x45, 0x67, 0x6D, 0xEA, 0x04, 0xD2,
+	0x0A, 0x93, 0x30, 0xF0, 0x20, 0x6A, 0x80, 0xF7, 0x44, 0x9A, 0x49, 0xE3, 0x04, 0x93, 0x60, 0xDA,
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+	0xA3, 0xF3, 0x08, 0x4A, 0x45, 0xF0, 0x41, 0xA2, 0x52, 0x35, 0xFF, 0x6A, 0xAC, 0xEA, 0xA3, 0x67,
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+	0x63, 0xA2, 0x7F, 0x6A, 0x4C, 0xEB, 0xFF, 0x6A, 0x6C, 0xEA, 0x1F, 0x22, 0x01, 0x6B, 0x6E, 0xEA,
+	0x20, 0xF2, 0x07, 0x2A, 0x00, 0x6C, 0x00, 0x18, 0xF5, 0xE3, 0x7D, 0x67, 0x55, 0xC3, 0x7D, 0x67,
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+	0x7D, 0x67, 0x48, 0xC3, 0x7D, 0x67, 0x50, 0xA3, 0x50, 0x32, 0x62, 0x67, 0x30, 0xF0, 0x20, 0x6A,
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+	0x03, 0xF1, 0x5C, 0x9A, 0x49, 0xE3, 0x40, 0xA2, 0x7D, 0x67, 0x40, 0xC3, 0x02, 0x63, 0x20, 0xE8,
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+	0x7D, 0x67, 0x48, 0xA3, 0x50, 0x32, 0x62, 0x67, 0x30, 0xF0, 0x20, 0x6A, 0x03, 0xF1, 0x54, 0x9A,
+	0x49, 0xE3, 0x60, 0xA2, 0xFF, 0x6A, 0x6C, 0xEA, 0x62, 0x67, 0x40, 0x6A, 0x6C, 0xEA, 0x5B, 0x32,
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+	0x80, 0xA3, 0xFF, 0x6B, 0x6C, 0xEC, 0x02, 0x6B, 0x6D, 0xEC, 0xFF, 0x6B, 0x8C, 0xEB, 0x60, 0xC2,
+	0x30, 0xF0, 0x20, 0x6A, 0x43, 0xF1, 0x4C, 0x9A, 0x01, 0x6B, 0x6B, 0xEB, 0x60, 0xC2, 0x30, 0xF0,
+	0x20, 0x6A, 0x43, 0xF1, 0x50, 0x9A, 0x09, 0x6B, 0x60, 0xC2, 0x30, 0xF0, 0x20, 0x6A, 0x43, 0xF1,
+	0x54, 0x9A, 0x7A, 0x6B, 0x6B, 0xEB, 0x60, 0xC2, 0xA1, 0xF0, 0x14, 0x6B, 0x01, 0x6A, 0x4B, 0xEA,
+	0x83, 0x67, 0xA2, 0x67, 0x00, 0x18, 0x76, 0xEE, 0x62, 0x67, 0x41, 0x6A, 0x4B, 0xEA, 0x6C, 0xEA,
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+	0x43, 0xF1, 0x78, 0x9B, 0x80, 0xA3, 0xFF, 0x6B, 0x6C, 0xEC, 0x01, 0x6B, 0x6D, 0xEC, 0xFF, 0x6B,
+	0x8C, 0xEB, 0x60, 0xC2, 0x81, 0xF4, 0x10, 0x6C, 0x01, 0x6B, 0x6B, 0xEB, 0x30, 0xF0, 0x20, 0x6A,
+	0x43, 0xF1, 0x5C, 0x9A, 0xA3, 0x67, 0xC2, 0x67, 0x00, 0x18, 0x8A, 0xEE, 0x81, 0xF6, 0x10, 0x6C,
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+	0x00, 0x18, 0x8A, 0xEE, 0x01, 0xF6, 0x00, 0x6B, 0x01, 0x6A, 0x4B, 0xEA, 0x83, 0x67, 0xA2, 0x67,
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+	0x00, 0x6C, 0x01, 0x6B, 0x6B, 0xEB, 0x04, 0x92, 0xA3, 0x67, 0xC2, 0x67, 0x00, 0x18, 0x8A, 0xEE,
+	0x81, 0xF4, 0x10, 0x6B, 0x01, 0x6A, 0x4B, 0xEA, 0x83, 0x67, 0xA2, 0x67, 0x00, 0x6E, 0x00, 0x18,
+	0x8A, 0xEE, 0x81, 0xF6, 0x10, 0x6B, 0x01, 0x6A, 0x4B, 0xEA, 0x83, 0x67, 0xA2, 0x67, 0x00, 0x6E,
+	0x00, 0x18, 0x8A, 0xEE, 0xA1, 0xF0, 0x14, 0x6B, 0x01, 0x6A, 0x4B, 0xEA, 0x83, 0x67, 0xA2, 0x67,
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+	0x01, 0x6B, 0x6B, 0xEB, 0x04, 0x92, 0xA3, 0x67, 0xC2, 0x67, 0x00, 0x18, 0x8A, 0xEE, 0x30, 0xF0,
+	0x20, 0x6A, 0x43, 0xF1, 0x78, 0x9A, 0x30, 0xF0, 0x20, 0x6A, 0x43, 0xF1, 0x58, 0x9A, 0x80, 0xA2,
+	0xFF, 0x6A, 0x8C, 0xEA, 0xFE, 0x6C, 0x8C, 0xEA, 0x40, 0xC3, 0x30, 0xF0, 0x20, 0x6A, 0x43, 0xF1,
+	0x4C, 0x9A, 0x3F, 0x6B, 0x60, 0xC2, 0x30, 0xF0, 0x20, 0x6A, 0x43, 0xF1, 0x68, 0x9A, 0x30, 0xF0,
+	0x20, 0x6A, 0x43, 0xF1, 0x48, 0x9A, 0x80, 0xA2, 0xFF, 0x6A, 0x8C, 0xEA, 0xFD, 0x6C, 0x8C, 0xEA,
+	0x40, 0xC3, 0x07, 0x97, 0x04, 0x63, 0x00, 0xEF, 0xFF, 0x63, 0x02, 0xD4, 0x45, 0x67, 0x7D, 0x67,
+	0x46, 0xCB, 0x00, 0x6A, 0x01, 0xD2, 0x00, 0x6A, 0x9D, 0x67, 0x41, 0xCC, 0x00, 0x6A, 0x7D, 0x67,
+	0x40, 0xCB, 0x67, 0x10, 0x9D, 0x67, 0x66, 0xAC, 0x01, 0x6A, 0x4C, 0xEB, 0xFF, 0x6A, 0x6C, 0xEA,
+	0x37, 0x22, 0x5D, 0x67, 0x60, 0xAA, 0x9D, 0x67, 0x46, 0xAC, 0xFF, 0x4A, 0x6E, 0xEA, 0x10, 0x2A,
+	0x5D, 0x67, 0x60, 0xAA, 0x02, 0x92, 0x4D, 0xE3, 0x30, 0xF0, 0x20, 0x6A, 0x63, 0xF1, 0x40, 0x9A,
+	0x49, 0xE3, 0x60, 0xA2, 0xFF, 0x6A, 0x6C, 0xEA, 0x40, 0x32, 0x7D, 0x67, 0x41, 0xCB, 0x3F, 0x10,
+	0x9D, 0x67, 0x60, 0xAC, 0x02, 0x92, 0x4D, 0xE3, 0x30, 0xF0, 0x20, 0x6A, 0x63, 0xF1, 0x40, 0x9A,
+	0x49, 0xE3, 0x60, 0xA2, 0xFF, 0x6A, 0x6C, 0xEA, 0x40, 0x33, 0xFF, 0xF7, 0x1F, 0x6A, 0x4C, 0xEB,
+	0x5D, 0x67, 0x80, 0xAA, 0x02, 0x92, 0x51, 0xE4, 0x30, 0xF0, 0x20, 0x6A, 0x63, 0xF1, 0x44, 0x9A,
+	0x49, 0xE4, 0x80, 0xA2, 0xFF, 0x6A, 0x8C, 0xEA, 0x49, 0xE3, 0x7D, 0x67, 0x41, 0xCB, 0x1F, 0x10,
+	0x9D, 0x67, 0x60, 0xAC, 0x02, 0x92, 0x4D, 0xE3, 0x30, 0xF0, 0x20, 0x6A, 0x63, 0xF1, 0x40, 0x9A,
+	0x49, 0xE3, 0x60, 0xA2, 0xFF, 0x6A, 0x6C, 0xEA, 0x40, 0x33, 0xFF, 0xF7, 0x1F, 0x6A, 0x4C, 0xEB,
+	0x5D, 0x67, 0x80, 0xAA, 0x02, 0x92, 0x51, 0xE4, 0x30, 0xF0, 0x20, 0x6A, 0x63, 0xF1, 0x44, 0x9A,
+	0x49, 0xE4, 0x80, 0xA2, 0xFF, 0x6A, 0x8C, 0xEA, 0x49, 0xE3, 0x7D, 0x67, 0x41, 0xCB, 0x9D, 0x67,
+	0x41, 0xAC, 0x01, 0x93, 0x49, 0xE3, 0x01, 0xD2, 0x7D, 0x67, 0x40, 0xAB, 0x02, 0x4A, 0x9D, 0x67,
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+	0x0C, 0x92, 0x02, 0x6B, 0x6E, 0xEA, 0x27, 0x2A, 0x9D, 0x67, 0x20, 0xF0, 0x4C, 0xA4, 0x05, 0x5A,
+	0x58, 0x67, 0x21, 0x2A, 0x0A, 0x92, 0x60, 0x9A, 0x30, 0xF0, 0x20, 0x6A, 0x82, 0xF4, 0x50, 0x9A,
+	0x6C, 0xEA, 0x17, 0x22, 0x0A, 0x92, 0x41, 0x9A, 0x05, 0x5A, 0x58, 0x67, 0x12, 0x2A, 0x7D, 0x67,
+	0x20, 0xF0, 0x4C, 0xA3, 0x30, 0xF0, 0x20, 0x6B, 0x83, 0x67, 0x02, 0xF2, 0x00, 0x4C, 0x30, 0xF0,
+	0x20, 0x6B, 0xA3, 0x67, 0x82, 0xF3, 0x08, 0x4D, 0x0C, 0x93, 0xC3, 0x67, 0xE2, 0x67, 0x80, 0x18,
+	0xCB, 0x01, 0x00, 0x6A, 0x55, 0x12, 0x30, 0xF0, 0x20, 0x6A, 0x0C, 0x93, 0x83, 0xF3, 0x78, 0xDA,
+	0x0A, 0x93, 0x30, 0xF0, 0x20, 0x6A, 0x82, 0xF4, 0x58, 0x9A, 0x83, 0x67, 0x00, 0x6D, 0x18, 0x6E,
+	0xE2, 0x67, 0x80, 0x18, 0x5C, 0x1A, 0x07, 0xD2, 0x00, 0x6A, 0x07, 0x93, 0x01, 0x4B, 0x01, 0x23,
+	0x01, 0x6A, 0x9D, 0x67, 0x78, 0x84, 0x6C, 0xEA, 0x00, 0xF6, 0x40, 0x32, 0x00, 0xF6, 0x43, 0x32,
+	0x7D, 0x67, 0x58, 0xC3, 0x0C, 0x92, 0x06, 0x5A, 0x58, 0x67, 0x80, 0xF1, 0x1D, 0x22, 0x0C, 0x92,
+	0x48, 0x33, 0x30, 0xF0, 0x20, 0x6A, 0xC2, 0xF2, 0x18, 0x4A, 0x49, 0xE3, 0x40, 0x9A, 0x00, 0xEA,
+	0xA1, 0xF0, 0x0C, 0x6A, 0x82, 0x67, 0xFF, 0x6D, 0x00, 0x6E, 0x00, 0x18, 0x8A, 0xEE, 0xA1, 0xF0,
+	0x0C, 0x6B, 0x00, 0xF3, 0x00, 0x6A, 0x83, 0x67, 0xA2, 0x67, 0x00, 0x6E, 0x00, 0x18, 0x8A, 0xEE,
+	0xA1, 0xF0, 0x0C, 0x6B, 0x30, 0xF0, 0x20, 0x6A, 0xA2, 0xF4, 0x40, 0x9A, 0x83, 0x67, 0xA2, 0x67,
+	0x01, 0x6E, 0x00, 0x18, 0x8A, 0xEE, 0xA1, 0xF0, 0x0C, 0x6B, 0x30, 0xF0, 0x20, 0x6A, 0xC2, 0xF4,
+	0x48, 0x9A, 0x83, 0x67, 0xA2, 0x67, 0x00, 0x6E, 0x00, 0x18, 0x8A, 0xEE, 0xA1, 0xF0, 0x0C, 0x6B,
+	0x30, 0xF0, 0x20, 0x6A, 0x82, 0xF4, 0x50, 0x9A, 0x83, 0x67, 0xA2, 0x67, 0x01, 0x6E, 0x00, 0x18,
+	0x8A, 0xEE, 0xC1, 0xF0, 0x04, 0x6B, 0x30, 0xF0, 0x20, 0x6A, 0xC2, 0xF4, 0x4C, 0x9A, 0x83, 0x67,
+	0xA2, 0x67, 0x01, 0x6E, 0x00, 0x18, 0x8A, 0xEE, 0x07, 0x93, 0x01, 0xF4, 0x00, 0x6A, 0x6D, 0xEA,
+	0x07, 0xD2, 0x71, 0x11, 0x5D, 0x67, 0x20, 0xF0, 0x6C, 0xA2, 0x0F, 0x6A, 0x6C, 0xEA, 0x48, 0x33,
+	0x01, 0x6A, 0x6D, 0xEA, 0xA1, 0xF0, 0x0C, 0x6B, 0x83, 0x67, 0xFF, 0x6D, 0xC2, 0x67, 0x00, 0x18,
+	0x8A, 0xEE, 0x7D, 0x67, 0x20, 0xF0, 0x4C, 0xA3, 0x01, 0x6C, 0x8E, 0xEA, 0x0B, 0x2A, 0x7D, 0x67,
+	0x20, 0xF0, 0x4C, 0xA3, 0x01, 0xF2, 0x00, 0x6B, 0x83, 0x67, 0x10, 0x6D, 0xC2, 0x67, 0x00, 0x18,
+	0x8A, 0xEE, 0x07, 0x10, 0x01, 0xF2, 0x00, 0x6A, 0x82, 0x67, 0x10, 0x6D, 0x00, 0x6E, 0x00, 0x18,
+	0x8A, 0xEE, 0xA1, 0xF0, 0x0C, 0x6B, 0x01, 0xF4, 0x00, 0x6A, 0x83, 0x67, 0xA2, 0x67, 0x00, 0x6E,
+	0x00, 0x18, 0x8A, 0xEE, 0xA1, 0xF0, 0x0C, 0x6B, 0x30, 0xF0, 0x20, 0x6A, 0xC2, 0xF4, 0x40, 0x9A,
+	0x83, 0x67, 0xA2, 0x67, 0x01, 0x6E, 0x00, 0x18, 0x8A, 0xEE, 0xA1, 0xF0, 0x0C, 0x6B, 0x30, 0xF0,
+	0x20, 0x6A, 0xC2, 0xF4, 0x50, 0x9A, 0x83, 0x67, 0xA2, 0x67, 0x00, 0x6E, 0x00, 0x18, 0x8A, 0xEE,
+	0xA1, 0xF0, 0x0C, 0x6B, 0x30, 0xF0, 0x20, 0x6A, 0xC2, 0xF4, 0x54, 0x9A, 0x83, 0x67, 0xA2, 0x67,
+	0x01, 0x6E, 0x00, 0x18, 0x8A, 0xEE, 0xC1, 0xF0, 0x04, 0x6B, 0x30, 0xF0, 0x20, 0x6A, 0xC2, 0xF4,
+	0x4C, 0x9A, 0x83, 0x67, 0xA2, 0x67, 0x01, 0x6E, 0x00, 0x18, 0x8A, 0xEE, 0x07, 0x93, 0x01, 0xF4,
+	0x01, 0x6A, 0x4B, 0xEA, 0x6C, 0xEA, 0x07, 0xD2, 0x07, 0x93, 0x01, 0xF0, 0x00, 0x6A, 0x6D, 0xEA,
+	0x07, 0xD2, 0x09, 0x11, 0x9D, 0x67, 0x20, 0xF0, 0x6C, 0xA4, 0x0F, 0x6A, 0x6C, 0xEA, 0x48, 0x33,
+	0x02, 0x6A, 0x6D, 0xEA, 0xA1, 0xF0, 0x0C, 0x6B, 0x83, 0x67, 0xFF, 0x6D, 0xC2, 0x67, 0x00, 0x18,
+	0x8A, 0xEE, 0xA1, 0xF0, 0x0C, 0x6B, 0x06, 0xF0, 0x00, 0x6A, 0x83, 0x67, 0xA2, 0x67, 0x00, 0x6E,
+	0x00, 0x18, 0x8A, 0xEE, 0xA1, 0xF0, 0x0C, 0x6B, 0x30, 0xF0, 0x20, 0x6A, 0xA2, 0xF4, 0x48, 0x9A,
+	0x83, 0x67, 0xA2, 0x67, 0x01, 0x6E, 0x00, 0x18, 0x8A, 0xEE, 0xA1, 0xF0, 0x0C, 0x6B, 0x30, 0xF0,
+	0x20, 0x6A, 0xC2, 0xF4, 0x58, 0x9A, 0x83, 0x67, 0xA2, 0x67, 0x00, 0x6E, 0x00, 0x18, 0x8A, 0xEE,
+	0xA1, 0xF0, 0x0C, 0x6B, 0x30, 0xF0, 0x20, 0x6A, 0xC2, 0xF4, 0x4C, 0x9A, 0x83, 0x67, 0xA2, 0x67,
+	0x01, 0x6E, 0x00, 0x18, 0x8A, 0xEE, 0xC1, 0xF0, 0x04, 0x6B, 0x30, 0xF0, 0x20, 0x6A, 0xC2, 0xF4,
+	0x4C, 0x9A, 0x83, 0x67, 0xA2, 0x67, 0x01, 0x6E, 0x00, 0x18, 0x8A, 0xEE, 0x07, 0x93, 0x01, 0xF4,
+	0x01, 0x6A, 0x4B, 0xEA, 0x6C, 0xEA, 0x07, 0xD2, 0x07, 0x93, 0x00, 0xF4, 0x00, 0x6A, 0x6D, 0xEA,
+	0x07, 0xD2, 0xB9, 0x10, 0xA1, 0xF0, 0x0C, 0x6A, 0x82, 0x67, 0xFF, 0x6D, 0x40, 0x6E, 0x00, 0x18,
+	0x8A, 0xEE, 0xA1, 0xF0, 0x0C, 0x6B, 0x00, 0xF3, 0x00, 0x6A, 0x83, 0x67, 0xA2, 0x67, 0x02, 0x6E,
+	0x00, 0x18, 0x8A, 0xEE, 0xA1, 0xF0, 0x0C, 0x6B, 0x30, 0xF0, 0x20, 0x6A, 0xA2, 0xF4, 0x40, 0x9A,
+	0x83, 0x67, 0xA2, 0x67, 0x00, 0x6E, 0x00, 0x18, 0x8A, 0xEE, 0xA1, 0xF0, 0x0C, 0x6B, 0x30, 0xF0,
+	0x20, 0x6A, 0xC2, 0xF4, 0x48, 0x9A, 0x83, 0x67, 0xA2, 0x67, 0x02, 0x6E, 0x00, 0x18, 0x8A, 0xEE,
+	0xA1, 0xF0, 0x0C, 0x6B, 0x30, 0xF0, 0x20, 0x6A, 0x82, 0xF4, 0x50, 0x9A, 0x83, 0x67, 0xA2, 0x67,
+	0x00, 0x6E, 0x00, 0x18, 0x8A, 0xEE, 0xC1, 0xF0, 0x04, 0x6B, 0x30, 0xF0, 0x20, 0x6A, 0xC2, 0xF4,
+	0x4C, 0x9A, 0x83, 0x67, 0xA2, 0x67, 0x00, 0x6E, 0x00, 0x18, 0x8A, 0xEE, 0xC1, 0xF0, 0x08, 0x6B,
+	0x30, 0xF0, 0x20, 0x6A, 0xC2, 0xF4, 0x5C, 0x9A, 0x83, 0x67, 0xA2, 0x67, 0x01, 0x6E, 0x00, 0x18,
+	0x8A, 0xEE, 0x07, 0x93, 0x01, 0xF4, 0x00, 0x6A, 0x6D, 0xEA, 0x07, 0xD2, 0x6C, 0x10, 0xA1, 0xF0,
+	0x0C, 0x6A, 0x82, 0x67, 0xFF, 0x6D, 0x80, 0x6E, 0x00, 0x18, 0x8A, 0xEE, 0xA1, 0xF0, 0x0C, 0x6B,
+	0x00, 0xF3, 0x00, 0x6A, 0x83, 0x67, 0xA2, 0x67, 0x03, 0x6E, 0x00, 0x18, 0x8A, 0xEE, 0xA1, 0xF0,
+	0x0C, 0x6B, 0x30, 0xF0, 0x20, 0x6A, 0xA2, 0xF4, 0x40, 0x9A, 0x83, 0x67, 0xA2, 0x67, 0x00, 0x6E,
+	0x00, 0x18, 0x8A, 0xEE, 0xA1, 0xF0, 0x0C, 0x6B, 0x30, 0xF0, 0x20, 0x6A, 0xC2, 0xF4, 0x48, 0x9A,
+	0x83, 0x67, 0xA2, 0x67, 0x03, 0x6E, 0x00, 0x18, 0x8A, 0xEE, 0xA1, 0xF0, 0x0C, 0x6B, 0x30, 0xF0,
+	0x20, 0x6A, 0x82, 0xF4, 0x50, 0x9A, 0x83, 0x67, 0xA2, 0x67, 0x00, 0x6E, 0x00, 0x18, 0x8A, 0xEE,
+	0xC1, 0xF0, 0x04, 0x6B, 0x30, 0xF0, 0x20, 0x6A, 0xC2, 0xF4, 0x4C, 0x9A, 0x83, 0x67, 0xA2, 0x67,
+	0x00, 0x6E, 0x00, 0x18, 0x8A, 0xEE, 0xC1, 0xF0, 0x08, 0x6B, 0x30, 0xF0, 0x20, 0x6A, 0xC2, 0xF4,
+	0x5C, 0x9A, 0x83, 0x67, 0xA2, 0x67, 0x01, 0x6E, 0x00, 0x18, 0x8A, 0xEE, 0x07, 0x93, 0x01, 0xF4,
+	0x00, 0x6A, 0x6D, 0xEA, 0x07, 0xD2, 0x1F, 0x10, 0x0A, 0x92, 0x60, 0x9A, 0x30, 0xF0, 0x20, 0x6A,
+	0x82, 0xF4, 0x50, 0x9A, 0x6C, 0xEA, 0x17, 0x22, 0x0A, 0x92, 0x41, 0x9A, 0x05, 0x5A, 0x58, 0x67,
+	0x12, 0x2A, 0x7D, 0x67, 0x20, 0xF0, 0x4C, 0xA3, 0x30, 0xF0, 0x20, 0x6B, 0x83, 0x67, 0x02, 0xF2,
+	0x00, 0x4C, 0x30, 0xF0, 0x20, 0x6B, 0xA3, 0x67, 0x82, 0xF3, 0x08, 0x4D, 0x0C, 0x93, 0xC3, 0x67,
+	0xE2, 0x67, 0x80, 0x18, 0xCB, 0x01, 0x0A, 0x93, 0x30, 0xF0, 0x20, 0x6A, 0x82, 0xF4, 0x58, 0x9A,
+	0x07, 0x94, 0x04, 0xD4, 0x83, 0x67, 0x00, 0x6D, 0x18, 0x6E, 0xE2, 0x67, 0x80, 0x18, 0xAE, 0x1A,
+	0x62, 0x67, 0x9D, 0x67, 0x58, 0xA4, 0x6C, 0xEA, 0x7D, 0x67, 0x58, 0xC3, 0x9D, 0x67, 0x58, 0xA4,
+	0x21, 0x2A, 0x0A, 0x92, 0x60, 0x9A, 0x30, 0xF0, 0x20, 0x6A, 0x82, 0xF4, 0x50, 0x9A, 0x6C, 0xEA,
+	0x17, 0x22, 0x0A, 0x92, 0x41, 0x9A, 0x05, 0x5A, 0x58, 0x67, 0x12, 0x2A, 0x7D, 0x67, 0x20, 0xF0,
+	0x4C, 0xA3, 0x30, 0xF0, 0x20, 0x6B, 0x83, 0x67, 0x22, 0xF2, 0x1C, 0x4C, 0x30, 0xF0, 0x20, 0x6B,
+	0xA3, 0x67, 0x82, 0xF3, 0x08, 0x4D, 0x0C, 0x93, 0xC3, 0x67, 0xE2, 0x67, 0x80, 0x18, 0xCB, 0x01,
+	0x00, 0x6A, 0x3E, 0x10, 0x0A, 0x93, 0x0C, 0x92, 0x83, 0x67, 0xA2, 0x67, 0x80, 0x18, 0xF8, 0x19,
+	0x0A, 0x93, 0x0C, 0x92, 0x83, 0x67, 0xA2, 0x67, 0x80, 0x18, 0xF5, 0x19, 0x0A, 0x92, 0x82, 0x67,
+	0x80, 0x18, 0xF4, 0x19, 0x01, 0xF0, 0x08, 0x6A, 0x82, 0x67, 0xFF, 0x6D, 0x00, 0x6E, 0x00, 0x18,
+	0x8A, 0xEE, 0x01, 0xF0, 0x08, 0x6A, 0x82, 0x67, 0xFF, 0x6D, 0x11, 0x6E, 0x00, 0x18, 0x8A, 0xEE,
+	0x0A, 0x92, 0x60, 0x9A, 0x30, 0xF0, 0x20, 0x6A, 0x82, 0xF4, 0x50, 0x9A, 0x6C, 0xEA, 0x17, 0x22,
+	0x0A, 0x92, 0x41, 0x9A, 0x05, 0x5A, 0x58, 0x67, 0x12, 0x2A, 0x7D, 0x67, 0x20, 0xF0, 0x4C, 0xA3,
+	0x30, 0xF0, 0x20, 0x6B, 0x83, 0x67, 0x82, 0xF2, 0x1C, 0x4C, 0x30, 0xF0, 0x20, 0x6B, 0xA3, 0x67,
+	0x82, 0xF3, 0x08, 0x4D, 0x0C, 0x93, 0xC3, 0x67, 0xE2, 0x67, 0x80, 0x18, 0xCB, 0x01, 0x01, 0x6A,
+	0x09, 0x97, 0x05, 0x63, 0x00, 0xEF, 0x00, 0x65, 0xFD, 0x63, 0x05, 0x62, 0x06, 0xD4, 0x65, 0x67,
+	0x46, 0x67, 0x09, 0xD7, 0x9D, 0x67, 0x7C, 0xC4, 0x7D, 0x67, 0x20, 0xF0, 0x40, 0xC3, 0x9D, 0x67,
+	0x5C, 0xA4, 0x06, 0x93, 0x83, 0x67, 0xA2, 0x67, 0x80, 0x18, 0xD5, 0x1B, 0x02, 0x2A, 0x00, 0x6A,
+	0x17, 0x10, 0x7D, 0x67, 0x5C, 0xA3, 0x06, 0x93, 0x83, 0x67, 0xA2, 0x67, 0x80, 0x18, 0x7B, 0x1C,
+	0x02, 0x2A, 0x00, 0x6A, 0x0D, 0x10, 0x9D, 0x67, 0x20, 0xF0, 0x60, 0xA4, 0x06, 0x94, 0x09, 0x92,
+	0xA3, 0x67, 0xC2, 0x67, 0x80, 0x18, 0xCF, 0x1D, 0x02, 0x2A, 0x00, 0x6A, 0x01, 0x10, 0x01, 0x6A,
+	0x05, 0x97, 0x03, 0x63, 0x00, 0xEF, 0x00, 0x65, 0xFD, 0x63, 0x05, 0x62, 0x06, 0xD4, 0x07, 0xD5,
+	0x07, 0x92, 0x27, 0x2A, 0x01, 0xF0, 0x08, 0x6B, 0x30, 0xF0, 0x20, 0x6A, 0xE2, 0xF4, 0x40, 0x9A,
+	0x83, 0x67, 0xA2, 0x67, 0x00, 0x6E, 0x00, 0x18, 0x8A, 0xEE, 0x06, 0x92, 0x60, 0x9A, 0x30, 0xF0,
+	0x20, 0x6A, 0x82, 0xF4, 0x50, 0x9A, 0x6C, 0xEA, 0x80, 0xF0, 0x00, 0x22, 0x06, 0x92, 0x41, 0x9A,
+	0x05, 0x5A, 0x58, 0x67, 0x7B, 0x2A, 0x30, 0xF0, 0x20, 0x6A, 0x62, 0x67, 0xE2, 0xF2, 0x10, 0x4B,
+	0x30, 0xF0, 0x20, 0x6A, 0x62, 0xF3, 0x04, 0x4A, 0x83, 0x67, 0xA2, 0x67, 0x80, 0x18, 0xCB, 0x01,
+	0x6D, 0x10, 0x07, 0x92, 0x01, 0x6B, 0x6E, 0xEA, 0x4D, 0x2A, 0x01, 0xF0, 0x08, 0x6B, 0x30, 0xF0,
+	0x20, 0x6A, 0xE2, 0xF4, 0x40, 0x9A, 0x83, 0x67, 0xA2, 0x67, 0x03, 0x6E, 0x00, 0x18, 0x8A, 0xEE,
+	0x06, 0x92, 0x60, 0x9A, 0x30, 0xF0, 0x20, 0x6A, 0x82, 0xF4, 0x50, 0x9A, 0x6C, 0xEA, 0x12, 0x22,
+	0x06, 0x92, 0x41, 0x9A, 0x05, 0x5A, 0x58, 0x67, 0x0D, 0x2A, 0x30, 0xF0, 0x20, 0x6A, 0x62, 0x67,
+	0x22, 0xF3, 0x00, 0x4B, 0x30, 0xF0, 0x20, 0x6A, 0x62, 0xF3, 0x04, 0x4A, 0x83, 0x67, 0xA2, 0x67,
+	0x80, 0x18, 0xCB, 0x01, 0x21, 0xF0, 0x0C, 0x6B, 0x01, 0x6A, 0x4B, 0xEA, 0x83, 0x67, 0xA2, 0x67,
+	0x00, 0x18, 0x76, 0xEE, 0x62, 0x67, 0x30, 0xF0, 0x20, 0x6A, 0x83, 0xF3, 0x6C, 0xDA, 0x21, 0xF0,
+	0x18, 0x6B, 0x01, 0x6A, 0x4B, 0xEA, 0x83, 0x67, 0xA2, 0x67, 0x00, 0x18, 0x76, 0xEE, 0x62, 0x67,
+	0x30, 0xF0, 0x20, 0x6A, 0x83, 0xF3, 0x70, 0xDA, 0x21, 0xF0, 0x10, 0x6B, 0x01, 0x6A, 0x4B, 0xEA,
+	0x83, 0x67, 0xA2, 0x67, 0x00, 0x18, 0x76, 0xEE, 0x62, 0x67, 0x30, 0xF0, 0x20, 0x6A, 0x83, 0xF3,
+	0x74, 0xDA, 0x1C, 0x10, 0x06, 0x92, 0x60, 0x9A, 0x30, 0xF0, 0x20, 0x6A, 0x82, 0xF4, 0x50, 0x9A,
+	0x6C, 0xEA, 0x12, 0x22, 0x06, 0x92, 0x41, 0x9A, 0x05, 0x5A, 0x58, 0x67, 0x0D, 0x2A, 0x30, 0xF0,
+	0x20, 0x6A, 0x62, 0x67, 0x42, 0xF3, 0x10, 0x4B, 0x30, 0xF0, 0x20, 0x6A, 0x62, 0xF3, 0x04, 0x4A,
+	0x83, 0x67, 0xA2, 0x67, 0x80, 0x18, 0xCB, 0x01, 0x00, 0x6A, 0x01, 0x10, 0x01, 0x6A, 0x05, 0x97,
+	0x03, 0x63, 0x00, 0xEF, 0x81, 0x1A, 0x00, 0x00, 0xF1, 0x92, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+
+};
+u32 array_length_tc_8821c_fw_nic = 100240;
+
+
+#endif
+
+void
+odm_read_firmware_tc_8821c_fw_nic(
+	struct PHY_DM_STRUCT    *p_dm_odm,
+	u8       *p_firmware,
+	u32       *p_firmware_size
+)
+{
+#if (DM_ODM_SUPPORT_TYPE & (ODM_CE))
+	*((SIZE_PTR *)p_firmware) = (SIZE_PTR)array_tc_8821c_fw_nic;
+#else
+	odm_move_memory(p_dm_odm, p_firmware, array_tc_8821c_fw_nic, array_length_tc_8821c_fw_nic);
+#endif
+	*p_firmware_size = array_length_tc_8821c_fw_nic;
+}
+
+#ifndef LOAD_FW_HEADER_FROM_DRIVER
+u8 array_tc_8821c_fw_wowlan[] = {
+	0x21, 0x88, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x91, 0x2D, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x01, 0x19, 0x10, 0x3B, 0xE0, 0x07, 0x00, 0x00, 0x18, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x20, 0x80, 0xA8, 0x0B, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x08, 0xF3, 0x00, 0x00, 0x30, 0x10, 0x00, 0x00, 0x00, 0x00, 0x10, 0x80, 0x00, 0x00, 0x03, 0x80,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0D, 0x4A, 0x03, 0x80, 0x15, 0x04, 0x03, 0x80,
+	0x03, 0x02, 0x01, 0xFE, 0x03, 0x03, 0x01, 0xFE, 0x03, 0x04, 0x01, 0xFE, 0x03, 0x05, 0x01, 0xFE,
+	0x03, 0x06, 0x01, 0xFE, 0x03, 0x07, 0x01, 0xFE, 0xD9, 0x8E, 0x03, 0x80, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x64, 0x01, 0x64, 0xB8, 0xFC, 0x10, 0x60, 0xB8,
+	0xFF, 0xFF, 0xFF, 0x00, 0xFF, 0xFF, 0x07, 0x00, 0xEC, 0x10, 0x60, 0xB8, 0xFA, 0xFA, 0xFA, 0xFA,
+	0x4C, 0x04, 0x64, 0xB8, 0x50, 0x04, 0x64, 0xB8, 0x84, 0x04, 0x64, 0xB8, 0x88, 0x04, 0x64, 0xB8,
+	0x8C, 0x04, 0x64, 0xB8, 0x90, 0x04, 0x64, 0xB8, 0x94, 0x04, 0x64, 0xB8, 0x98, 0x04, 0x64, 0xB8,
+	0x9C, 0x04, 0x64, 0xB8, 0xA0, 0x04, 0x64, 0xB8, 0xA4, 0x04, 0x64, 0xB8, 0xA8, 0x04, 0x64, 0xB8,
+	0xD0, 0x04, 0x64, 0xB8, 0xA5, 0x2E, 0x5A, 0xE2, 0x06, 0x00, 0x00, 0x00, 0x05, 0x00, 0x00, 0x00,
+	0x01, 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x01, 0x10, 0x00, 0x00, 0x09, 0x3D, 0x00,
+	0xFC, 0x10, 0x60, 0xB8, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0xFF, 0xFF, 0x00, 0x00, 0x01, 0x00,
+	0x00, 0x00, 0x60, 0xB8, 0x00, 0x00, 0x64, 0xB8, 0x54, 0x05, 0x64, 0xB8, 0xC1, 0x60, 0x03, 0x80,
+	0xFB, 0x61, 0x03, 0x80, 0x39, 0x61, 0x03, 0x80, 0xFB, 0x61, 0x03, 0x80, 0x51, 0x60, 0x03, 0x80,
+	0xFB, 0x61, 0x03, 0x80, 0xFB, 0x61, 0x03, 0x80, 0xFB, 0x61, 0x03, 0x80, 0xBB, 0x61, 0x03, 0x80,
+	0xFB, 0x61, 0x03, 0x80, 0xFB, 0x61, 0x03, 0x80, 0xFB, 0x61, 0x03, 0x80, 0xCF, 0x5F, 0x03, 0x80,
+	0x5B, 0x01, 0x64, 0xB8, 0x92, 0x06, 0x64, 0xB8, 0x3C, 0x01, 0x64, 0xB8, 0x53, 0x04, 0x64, 0xB8,
+	0x89, 0x00, 0x60, 0xB8, 0x8A, 0x00, 0x60, 0xB8, 0x04, 0x06, 0x64, 0xB8, 0x0A, 0x06, 0x64, 0xB8,
+	0x1A, 0x04, 0x64, 0xB8, 0x1B, 0x04, 0x64, 0xB8, 0x00, 0x00, 0x1E, 0x00, 0x58, 0x05, 0x64, 0xB8,
+	0x57, 0x01, 0x64, 0xB8, 0x87, 0x02, 0x64, 0xB8, 0x82, 0x02, 0x64, 0xB8, 0x86, 0x02, 0x64, 0xB8,
+	0x1D, 0x04, 0x64, 0xB8, 0x34, 0x01, 0x64, 0xB8, 0xA8, 0x06, 0x64, 0xB8, 0x73, 0x05, 0x64, 0xB8,
+	0xAB, 0x06, 0x64, 0xB8, 0xAA, 0x06, 0x64, 0xB8, 0x0D, 0x00, 0x78, 0xB8, 0x12, 0x00, 0x78, 0xB8,
+	0x11, 0x00, 0x78, 0xB8, 0x06, 0x00, 0x78, 0xB8, 0xA7, 0x04, 0x64, 0xB8, 0xA6, 0x04, 0x64, 0xB8,
+	0xA5, 0x04, 0x64, 0xB8, 0xA4, 0x04, 0x64, 0xB8, 0x14, 0x00, 0x78, 0xB8, 0x09, 0x00, 0x78, 0xB8,
+	0x31, 0x00, 0x78, 0xB8, 0x1D, 0x04, 0x64, 0xB8, 0x7A, 0x04, 0x64, 0xB8, 0x24, 0x04, 0x64, 0xB8,
+	0x04, 0x06, 0x64, 0xB8, 0x22, 0x05, 0x64, 0xB8, 0x4D, 0x01, 0x64, 0xB8, 0x00, 0x01, 0x64, 0xB8,
+	0x90, 0x06, 0x64, 0xB8, 0x84, 0x02, 0x64, 0xB8, 0x86, 0x02, 0x64, 0xB8, 0x00, 0x00, 0x78, 0xB8,
+	0x1C, 0x01, 0x64, 0xB8, 0xFF, 0xFF, 0x03, 0x00, 0x00, 0x00, 0x70, 0xB8, 0xC7, 0x01, 0x64, 0xB8,
+	0x84, 0x04, 0x60, 0xB8, 0x84, 0x04, 0x64, 0xB8, 0x8C, 0x04, 0x64, 0xB8, 0x24, 0x01, 0x64, 0xB8,
+	0x80, 0x34, 0x00, 0xB8, 0x18, 0x11, 0x64, 0xB8, 0x87, 0x02, 0x64, 0xB8, 0xFC, 0x10, 0x60, 0xB8,
+	0x20, 0x34, 0x00, 0xB8, 0x24, 0x04, 0x64, 0xB8, 0xE4, 0x10, 0x60, 0xB8, 0x18, 0x06, 0x60, 0xB8,
+	0x18, 0x06, 0x64, 0xB8, 0x10, 0x06, 0x60, 0xB8, 0x10, 0x06, 0x64, 0xB8, 0x09, 0x06, 0x64, 0xB8,
+	0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x64, 0xB8, 0x00, 0x00, 0x60, 0xB8, 0x00, 0x00, 0x00, 0x03,
+	0x00, 0x00, 0x00, 0x42, 0xE0, 0x00, 0x60, 0xB8, 0xFF, 0xFF, 0xFF, 0xFD, 0xE3, 0x00, 0x60, 0xB8,
+	0xB7, 0x8C, 0x03, 0x80, 0xBF, 0x8C, 0x03, 0x80, 0xC7, 0x8C, 0x03, 0x80, 0xCF, 0x8C, 0x03, 0x80,
+	0xD7, 0x8C, 0x03, 0x80, 0xDF, 0x8C, 0x03, 0x80, 0xFF, 0xFF, 0x03, 0x00, 0x00, 0x00, 0x00, 0x80,
+	0x00, 0x00, 0x00, 0x04, 0xFF, 0xFF, 0xFF, 0xFB, 0x00, 0x00, 0x00, 0x20, 0xFF, 0xFF, 0xFF, 0xDF,
+	0x00, 0x00, 0x60, 0xB8, 0xFF, 0xFF, 0xFF, 0x1F, 0x00, 0x00, 0x64, 0xB8, 0x04, 0x00, 0x60, 0xB8,
+	0x04, 0x00, 0x64, 0xB8, 0x08, 0x00, 0x60, 0xB8, 0x08, 0x00, 0x64, 0xB8, 0xF8, 0x10, 0x60, 0xB8,
+	0xE8, 0x12, 0x64, 0xB8, 0x24, 0x00, 0x60, 0xB8, 0x80, 0x00, 0x60, 0xB8, 0x50, 0x14, 0x60, 0xB8,
+	0x50, 0x14, 0x64, 0xB8, 0xFC, 0x10, 0x60, 0xB8, 0xCC, 0x07, 0x64, 0xB8, 0x00, 0x0C, 0x01, 0x00,
+	0x00, 0x00, 0x60, 0xB8, 0x00, 0x00, 0x64, 0xB8, 0x01, 0x00, 0x66, 0xB8, 0x97, 0x0B, 0x10, 0x80,
+	0x1B, 0x0C, 0x10, 0x80, 0xEB, 0x0C, 0x10, 0x80, 0xBD, 0x0E, 0x10, 0x80, 0x8B, 0x0D, 0x10, 0x80,
+	0x25, 0x0E, 0x10, 0x80, 0x00, 0x00, 0x00, 0xFF, 0xFF, 0xFF, 0x0F, 0x00, 0xFF, 0xFF, 0xFF, 0x0F,
+	0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x7F, 0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x04, 0x00,
+	0xFF, 0xFC, 0xFE, 0xFF, 0x00, 0x01, 0x01, 0x00, 0x00, 0xFF, 0xF9, 0xFF, 0x00, 0x00, 0xFE, 0x1F,
+	0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x02, 0x00, 0xFF, 0xFF, 0xF7, 0xFF, 0x00, 0x00, 0x30, 0x00,
+	0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0xC0, 0x00, 0x00, 0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x03,
+	0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x30, 0xF8, 0x10, 0x60, 0xB8, 0x96, 0x02, 0x64, 0xB8,
+	0x00, 0x00, 0x70, 0xB8, 0xFF, 0xFF, 0xF0, 0xFF, 0x00, 0x00, 0x00, 0x80, 0x0B, 0x00, 0x70, 0xB8,
+	0x02, 0x00, 0x70, 0xB8, 0x1C, 0x01, 0x64, 0xB8, 0xFF, 0xFF, 0x03, 0x00, 0x94, 0x02, 0x64, 0xB8,
+	0x97, 0x02, 0x64, 0xB8, 0x1C, 0x04, 0x64, 0xB8, 0x00, 0x00, 0x00, 0x20, 0x6B, 0xA1, 0x03, 0x80,
+	0x75, 0xA1, 0x03, 0x80, 0xF7, 0xA1, 0x03, 0x80, 0xF7, 0xA1, 0x03, 0x80, 0xF7, 0xA1, 0x03, 0x80,
+	0xF7, 0xA1, 0x03, 0x80, 0xF7, 0xA1, 0x03, 0x80, 0xF7, 0xA1, 0x03, 0x80, 0xF7, 0xA1, 0x03, 0x80,
+	0xF7, 0xA1, 0x03, 0x80, 0xF7, 0xA1, 0x03, 0x80, 0x7F, 0xA1, 0x03, 0x80, 0xF7, 0xA1, 0x03, 0x80,
+	0xF7, 0xA1, 0x03, 0x80, 0xF7, 0xA1, 0x03, 0x80, 0xF7, 0xA1, 0x03, 0x80, 0x17, 0xA2, 0x03, 0x80,
+	0x17, 0xA2, 0x03, 0x80, 0xF7, 0xA1, 0x03, 0x80, 0x17, 0xA2, 0x03, 0x80, 0x17, 0xA2, 0x03, 0x80,
+	0xF7, 0xA1, 0x03, 0x80, 0xF7, 0xA1, 0x03, 0x80, 0xF7, 0xA1, 0x03, 0x80, 0xF7, 0xA1, 0x03, 0x80,
+	0xF7, 0xA1, 0x03, 0x80, 0xF7, 0xA1, 0x03, 0x80, 0xF7, 0xA1, 0x03, 0x80, 0xF7, 0xA1, 0x03, 0x80,
+	0xF7, 0xA1, 0x03, 0x80, 0xF7, 0xA1, 0x03, 0x80, 0xF7, 0xA1, 0x03, 0x80, 0x89, 0xA1, 0x03, 0x80,
+	0x17, 0xA2, 0x03, 0x80, 0xF7, 0xA1, 0x03, 0x80, 0x17, 0xA2, 0x03, 0x80, 0xF7, 0xA1, 0x03, 0x80,
+	0x17, 0xA2, 0x03, 0x80, 0xF7, 0xA1, 0x03, 0x80, 0xF7, 0xA1, 0x03, 0x80, 0xF7, 0xA1, 0x03, 0x80,
+	0xF7, 0xA1, 0x03, 0x80, 0xF7, 0xA1, 0x03, 0x80, 0xF7, 0xA1, 0x03, 0x80, 0xF7, 0xA1, 0x03, 0x80,
+	0xF7, 0xA1, 0x03, 0x80, 0xF7, 0xA1, 0x03, 0x80, 0xF7, 0xA1, 0x03, 0x80, 0xF7, 0xA1, 0x03, 0x80,
+	0xF7, 0xA1, 0x03, 0x80, 0xF7, 0xA1, 0x03, 0x80, 0xF7, 0xA1, 0x03, 0x80, 0xF7, 0xA1, 0x03, 0x80,
+	0xF7, 0xA1, 0x03, 0x80, 0xF7, 0xA1, 0x03, 0x80, 0xF7, 0xA1, 0x03, 0x80, 0xF7, 0xA1, 0x03, 0x80,
+	0xF7, 0xA1, 0x03, 0x80, 0xF7, 0xA1, 0x03, 0x80, 0xF7, 0xA1, 0x03, 0x80, 0xF7, 0xA1, 0x03, 0x80,
+	0xF7, 0xA1, 0x03, 0x80, 0xF7, 0xA1, 0x03, 0x80, 0xF7, 0xA1, 0x03, 0x80, 0xF7, 0xA1, 0x03, 0x80,
+	0xF7, 0xA1, 0x03, 0x80, 0xF7, 0xA1, 0x03, 0x80, 0xF7, 0xA1, 0x03, 0x80, 0xF7, 0xA1, 0x03, 0x80,
+	0xF7, 0xA1, 0x03, 0x80, 0xF7, 0xA1, 0x03, 0x80, 0xF7, 0xA1, 0x03, 0x80, 0xF7, 0xA1, 0x03, 0x80,
+	0xF7, 0xA1, 0x03, 0x80, 0xF7, 0xA1, 0x03, 0x80, 0xF7, 0xA1, 0x03, 0x80, 0xF7, 0xA1, 0x03, 0x80,
+	0xF7, 0xA1, 0x03, 0x80, 0xF7, 0xA1, 0x03, 0x80, 0xF7, 0xA1, 0x03, 0x80, 0xF7, 0xA1, 0x03, 0x80,
+	0xF7, 0xA1, 0x03, 0x80, 0xF7, 0xA1, 0x03, 0x80, 0xF7, 0xA1, 0x03, 0x80, 0xF7, 0xA1, 0x03, 0x80,
+	0xF7, 0xA1, 0x03, 0x80, 0xF7, 0xA1, 0x03, 0x80, 0xF7, 0xA1, 0x03, 0x80, 0xF7, 0xA1, 0x03, 0x80,
+	0xF7, 0xA1, 0x03, 0x80, 0xF7, 0xA1, 0x03, 0x80, 0xF7, 0xA1, 0x03, 0x80, 0xF7, 0xA1, 0x03, 0x80,
+	0xF7, 0xA1, 0x03, 0x80, 0xF7, 0xA1, 0x03, 0x80, 0xF7, 0xA1, 0x03, 0x80, 0xF7, 0xA1, 0x03, 0x80,
+	0xF7, 0xA1, 0x03, 0x80, 0xF7, 0xA1, 0x03, 0x80, 0xF7, 0xA1, 0x03, 0x80, 0xF7, 0xA1, 0x03, 0x80,
+	0xF7, 0xA1, 0x03, 0x80, 0xF7, 0xA1, 0x03, 0x80, 0xF7, 0xA1, 0x03, 0x80, 0xF7, 0xA1, 0x03, 0x80,
+	0xF7, 0xA1, 0x03, 0x80, 0xF7, 0xA1, 0x03, 0x80, 0xF7, 0xA1, 0x03, 0x80, 0xF7, 0xA1, 0x03, 0x80,
+	0xF7, 0xA1, 0x03, 0x80, 0xF7, 0xA1, 0x03, 0x80, 0xF7, 0xA1, 0x03, 0x80, 0xF7, 0xA1, 0x03, 0x80,
+	0xF7, 0xA1, 0x03, 0x80, 0xF7, 0xA1, 0x03, 0x80, 0xF7, 0xA1, 0x03, 0x80, 0xF7, 0xA1, 0x03, 0x80,
+	0xF7, 0xA1, 0x03, 0x80, 0xF7, 0xA1, 0x03, 0x80, 0xF7, 0xA1, 0x03, 0x80, 0xF7, 0xA1, 0x03, 0x80,
+	0xF7, 0xA1, 0x03, 0x80, 0xF7, 0xA1, 0x03, 0x80, 0xF7, 0xA1, 0x03, 0x80, 0xF7, 0xA1, 0x03, 0x80,
+	0xF7, 0xA1, 0x03, 0x80, 0xF7, 0xA1, 0x03, 0x80, 0xF7, 0xA1, 0x03, 0x80, 0x93, 0xA1, 0x03, 0x80,
+	0x9D, 0xA1, 0x03, 0x80, 0xA7, 0xA1, 0x03, 0x80, 0xB1, 0xA1, 0x03, 0x80, 0xBB, 0xA1, 0x03, 0x80,
+	0xF7, 0xA1, 0x03, 0x80, 0xF7, 0xA1, 0x03, 0x80, 0xD9, 0xA1, 0x03, 0x80, 0xC5, 0xA1, 0x03, 0x80,
+	0xF7, 0xA1, 0x03, 0x80, 0xF7, 0xA1, 0x03, 0x80, 0xF7, 0xA1, 0x03, 0x80, 0xCF, 0xA1, 0x03, 0x80,
+	0xF7, 0xA1, 0x03, 0x80, 0xF7, 0xA1, 0x03, 0x80, 0xF7, 0xA1, 0x03, 0x80, 0xF7, 0xA1, 0x03, 0x80,
+	0xF7, 0xA1, 0x03, 0x80, 0xF7, 0xA1, 0x03, 0x80, 0xF7, 0xA1, 0x03, 0x80, 0xF7, 0xA1, 0x03, 0x80,
+	0xF7, 0xA1, 0x03, 0x80, 0xF7, 0xA1, 0x03, 0x80, 0xF7, 0xA1, 0x03, 0x80, 0xF7, 0xA1, 0x03, 0x80,
+	0xF7, 0xA1, 0x03, 0x80, 0xF7, 0xA1, 0x03, 0x80, 0xF7, 0xA1, 0x03, 0x80, 0xF7, 0xA1, 0x03, 0x80,
+	0xF7, 0xA1, 0x03, 0x80, 0xF7, 0xA1, 0x03, 0x80, 0xF7, 0xA1, 0x03, 0x80, 0xF7, 0xA1, 0x03, 0x80,
+	0xF7, 0xA1, 0x03, 0x80, 0xF7, 0xA1, 0x03, 0x80, 0xF7, 0xA1, 0x03, 0x80, 0xF7, 0xA1, 0x03, 0x80,
+	0xF7, 0xA1, 0x03, 0x80, 0xF7, 0xA1, 0x03, 0x80, 0xF7, 0xA1, 0x03, 0x80, 0xF7, 0xA1, 0x03, 0x80,
+	0xF7, 0xA1, 0x03, 0x80, 0xF7, 0xA1, 0x03, 0x80, 0xF7, 0xA1, 0x03, 0x80, 0xF7, 0xA1, 0x03, 0x80,
+	0xF7, 0xA1, 0x03, 0x80, 0xF7, 0xA1, 0x03, 0x80, 0xF7, 0xA1, 0x03, 0x80, 0xF7, 0xA1, 0x03, 0x80,
+	0xF7, 0xA1, 0x03, 0x80, 0xF7, 0xA1, 0x03, 0x80, 0xF7, 0xA1, 0x03, 0x80, 0xF7, 0xA1, 0x03, 0x80,
+	0xF7, 0xA1, 0x03, 0x80, 0xF7, 0xA1, 0x03, 0x80, 0xF7, 0xA1, 0x03, 0x80, 0xF7, 0xA1, 0x03, 0x80,
+	0xF7, 0xA1, 0x03, 0x80, 0xF7, 0xA1, 0x03, 0x80, 0xF7, 0xA1, 0x03, 0x80, 0xF7, 0xA1, 0x03, 0x80,
+	0xF7, 0xA1, 0x03, 0x80, 0xF7, 0xA1, 0x03, 0x80, 0xF7, 0xA1, 0x03, 0x80, 0xF7, 0xA1, 0x03, 0x80,
+	0xF7, 0xA1, 0x03, 0x80, 0xF7, 0xA1, 0x03, 0x80, 0xED, 0xA1, 0x03, 0x80, 0xF7, 0xA1, 0x03, 0x80,
+	0xE3, 0xA1, 0x03, 0x80, 0xD1, 0xAB, 0x03, 0x80, 0xD1, 0xAB, 0x03, 0x80, 0x73, 0xAB, 0x03, 0x80,
+	0x81, 0xAB, 0x03, 0x80, 0xD1, 0xAB, 0x03, 0x80, 0xD1, 0xAB, 0x03, 0x80, 0xD1, 0xAB, 0x03, 0x80,
+	0xD1, 0xAB, 0x03, 0x80, 0x8B, 0xAB, 0x03, 0x80, 0x99, 0xAB, 0x03, 0x80, 0xA7, 0xAB, 0x03, 0x80,
+	0xD1, 0xAB, 0x03, 0x80, 0xB5, 0xAB, 0x03, 0x80, 0xC3, 0xAB, 0x03, 0x80, 0xF9, 0xAB, 0x03, 0x80,
+	0xF9, 0xAB, 0x03, 0x80, 0xF9, 0xAB, 0x03, 0x80, 0x1F, 0x00, 0x60, 0xB8, 0x24, 0x04, 0x64, 0xB8,
+	0x30, 0x01, 0x64, 0xB8, 0xF8, 0x10, 0x60, 0xB8, 0x00, 0x00, 0x78, 0x18, 0x00, 0x00, 0x00, 0x80,
+	0x00, 0x00, 0x78, 0xB8, 0x00, 0x00, 0x02, 0x00, 0x64, 0x05, 0x64, 0xB8, 0x60, 0x05, 0x64, 0xB8,
+	0xC8, 0x01, 0x64, 0xB8, 0xC9, 0x01, 0x64, 0xB8, 0x54, 0x02, 0x64, 0xB8, 0x50, 0x02, 0x64, 0xB8,
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+	0x20, 0x6B, 0xC1, 0xF3, 0x14, 0x4B, 0x45, 0xF3, 0x58, 0xC3, 0x30, 0xF0, 0x20, 0x6A, 0xC1, 0xF3,
+	0x14, 0x4A, 0x45, 0xF3, 0x59, 0xA2, 0x19, 0x2A, 0x7D, 0x67, 0x48, 0xAB, 0x67, 0x42, 0x03, 0x4B,
+	0xFF, 0xF7, 0x1F, 0x6A, 0x6C, 0xEA, 0x62, 0x67, 0x00, 0xF0, 0x12, 0x02, 0x83, 0x67, 0xA2, 0x67,
+	0x00, 0x18, 0x17, 0xC3, 0x7D, 0x67, 0x52, 0xA3, 0x56, 0x33, 0xFF, 0x6A, 0x4C, 0xEB, 0x30, 0xF0,
+	0x20, 0x6A, 0xC1, 0xF3, 0x14, 0x4A, 0x45, 0xF3, 0x79, 0xC2, 0x30, 0xF0, 0x20, 0x6A, 0xC1, 0xF3,
+	0x14, 0x4A, 0x45, 0xF3, 0x5A, 0xA2, 0x18, 0x2A, 0x7D, 0x67, 0x48, 0xAB, 0x67, 0x42, 0x06, 0x4B,
+	0xFF, 0xF7, 0x1F, 0x6A, 0x6C, 0xEA, 0x62, 0x67, 0x00, 0xF0, 0x12, 0x02, 0x83, 0x67, 0xA2, 0x67,
+	0x00, 0x18, 0x17, 0xC3, 0x7D, 0x67, 0x52, 0xA3, 0x03, 0x6B, 0x6C, 0xEA, 0x30, 0xF0, 0x20, 0x6B,
+	0xC1, 0xF3, 0x14, 0x4B, 0x45, 0xF3, 0x5A, 0xC3, 0x30, 0xF0, 0x20, 0x6A, 0xC1, 0xF3, 0x14, 0x4A,
+	0x45, 0xF3, 0x5B, 0xA2, 0x1C, 0x2A, 0x7D, 0x67, 0x48, 0xAB, 0x67, 0x42, 0x06, 0x4B, 0xFF, 0xF7,
+	0x1F, 0x6A, 0x6C, 0xEA, 0x62, 0x67, 0x00, 0xF0, 0x12, 0x02, 0x83, 0x67, 0xA2, 0x67, 0x00, 0x18,
+	0x17, 0xC3, 0x7D, 0x67, 0x52, 0xA3, 0x62, 0x67, 0x30, 0x6A, 0x6C, 0xEA, 0x53, 0x33, 0xFF, 0x6A,
+	0x4C, 0xEB, 0x30, 0xF0, 0x20, 0x6A, 0xC1, 0xF3, 0x14, 0x4A, 0x45, 0xF3, 0x7B, 0xC2, 0x07, 0x97,
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+	0x9D, 0x67, 0x48, 0xAC, 0x64, 0x42, 0xFF, 0xF7, 0x1F, 0x6A, 0x6C, 0xEA, 0x62, 0x67, 0x00, 0xF0,
+	0x12, 0x02, 0x83, 0x67, 0xA2, 0x67, 0x00, 0x18, 0x17, 0xC3, 0x5D, 0x67, 0x72, 0xA2, 0x30, 0xF0,
+	0x20, 0x6A, 0xC1, 0xF3, 0x14, 0x4A, 0x45, 0xF3, 0x6C, 0xC2, 0x7D, 0x67, 0x48, 0xAB, 0x65, 0x42,
+	0xFF, 0xF7, 0x1F, 0x6A, 0x6C, 0xEA, 0x62, 0x67, 0x00, 0xF0, 0x12, 0x02, 0x83, 0x67, 0xA2, 0x67,
+	0x00, 0x18, 0x17, 0xC3, 0x9D, 0x67, 0x72, 0xA4, 0x30, 0xF0, 0x20, 0x6A, 0xC1, 0xF3, 0x14, 0x4A,
+	0x45, 0xF3, 0x6D, 0xC2, 0x7D, 0x67, 0x48, 0xAB, 0x66, 0x42, 0xFF, 0xF7, 0x1F, 0x6A, 0x6C, 0xEA,
+	0x62, 0x67, 0x00, 0xF0, 0x12, 0x02, 0x83, 0x67, 0xA2, 0x67, 0x00, 0x18, 0x17, 0xC3, 0x9D, 0x67,
+	0x48, 0xAC, 0x67, 0x42, 0xFF, 0xF7, 0x1F, 0x6A, 0x6C, 0xEA, 0x62, 0x67, 0x00, 0xF0, 0x13, 0x02,
+	0x83, 0x67, 0xA2, 0x67, 0x00, 0x18, 0x17, 0xC3, 0x7D, 0x67, 0x52, 0xA3, 0x1F, 0x6B, 0x6C, 0xEA,
+	0x30, 0xF0, 0x20, 0x6B, 0xC1, 0xF3, 0x14, 0x4B, 0x45, 0xF3, 0x4E, 0xC3, 0x9D, 0x67, 0x52, 0xA4,
+	0x56, 0x33, 0xFF, 0x6A, 0x6C, 0xEA, 0x62, 0x67, 0x9D, 0x67, 0x53, 0xA4, 0x4C, 0x32, 0x40, 0x32,
+	0x40, 0x32, 0x43, 0x32, 0x43, 0x32, 0x6D, 0xEA, 0x40, 0x33, 0x60, 0x33, 0x63, 0x33, 0x63, 0x33,
+	0xFF, 0xF7, 0x1F, 0x6A, 0x4C, 0xEB, 0x30, 0xF0, 0x20, 0x6A, 0xC1, 0xF3, 0x14, 0x4A, 0x45, 0xF3,
+	0x70, 0xCA, 0x7D, 0x67, 0x48, 0xAB, 0x67, 0x42, 0x01, 0x4B, 0xFF, 0xF7, 0x1F, 0x6A, 0x6C, 0xEA,
+	0x62, 0x67, 0x00, 0xF0, 0x12, 0x02, 0x83, 0x67, 0xA2, 0x67, 0x00, 0x18, 0x17, 0xC3, 0x9D, 0x67,
+	0x52, 0xA4, 0x0F, 0x6B, 0x6C, 0xEA, 0x30, 0xF0, 0x20, 0x6B, 0xC1, 0xF3, 0x14, 0x4B, 0x45, 0xF3,
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+	0xC1, 0xF3, 0x14, 0x4A, 0x45, 0xF3, 0x73, 0xC2, 0x9D, 0x67, 0x48, 0xAC, 0x67, 0x42, 0x02, 0x4B,
+	0xFF, 0xF7, 0x1F, 0x6A, 0x6C, 0xEA, 0x62, 0x67, 0x00, 0xF0, 0x12, 0x02, 0x83, 0x67, 0xA2, 0x67,
+	0x00, 0x18, 0x17, 0xC3, 0x7D, 0x67, 0x52, 0xA3, 0x01, 0x6B, 0x6C, 0xEA, 0x30, 0xF0, 0x20, 0x6B,
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+	0x6C, 0xEA, 0x47, 0x33, 0xFF, 0x6A, 0x4C, 0xEB, 0x30, 0xF0, 0x20, 0x6A, 0xC1, 0xF3, 0x14, 0x4A,
+	0x45, 0xF3, 0x75, 0xC2, 0x7D, 0x67, 0x52, 0xA3, 0x62, 0x67, 0x04, 0x6A, 0x6C, 0xEA, 0x4B, 0x33,
+	0xFF, 0x6A, 0x4C, 0xEB, 0x30, 0xF0, 0x20, 0x6A, 0xC1, 0xF3, 0x14, 0x4A, 0x45, 0xF3, 0x76, 0xC2,
+	0x9D, 0x67, 0x52, 0xA4, 0x62, 0x67, 0x08, 0x6A, 0x6C, 0xEA, 0x4F, 0x33, 0xFF, 0x6A, 0x4C, 0xEB,
+	0x30, 0xF0, 0x20, 0x6A, 0xC1, 0xF3, 0x14, 0x4A, 0x45, 0xF3, 0x77, 0xC2, 0x7D, 0x67, 0x48, 0xAB,
+	0x67, 0x42, 0x04, 0x4B, 0xFF, 0xF7, 0x1F, 0x6A, 0x6C, 0xEA, 0x62, 0x67, 0x00, 0xF0, 0x12, 0x02,
+	0x83, 0x67, 0xA2, 0x67, 0x00, 0x18, 0x17, 0xC3, 0x9D, 0x67, 0x52, 0xA4, 0x07, 0x6B, 0x6C, 0xEA,
+	0x30, 0xF0, 0x20, 0x6B, 0xC1, 0xF3, 0x14, 0x4B, 0x45, 0xF3, 0x58, 0xC3, 0x7D, 0x67, 0x52, 0xA3,
+	0x56, 0x33, 0xFF, 0x6A, 0x4C, 0xEB, 0x30, 0xF0, 0x20, 0x6A, 0xC1, 0xF3, 0x14, 0x4A, 0x45, 0xF3,
+	0x79, 0xC2, 0x9D, 0x67, 0x48, 0xAC, 0x67, 0x42, 0x06, 0x4B, 0xFF, 0xF7, 0x1F, 0x6A, 0x6C, 0xEA,
+	0x62, 0x67, 0x00, 0xF0, 0x12, 0x02, 0x83, 0x67, 0xA2, 0x67, 0x00, 0x18, 0x17, 0xC3, 0x7D, 0x67,
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+	0x20, 0x6A, 0xC1, 0xF3, 0x14, 0x4A, 0x45, 0xF3, 0x7A, 0xC2, 0x9D, 0x67, 0x52, 0xA4, 0x5A, 0x33,
+	0xFF, 0x6A, 0x4C, 0xEB, 0x30, 0xF0, 0x20, 0x6A, 0xC1, 0xF3, 0x14, 0x4A, 0x45, 0xF3, 0x7B, 0xC2,
+	0x00, 0x18, 0xD8, 0xC5, 0x00, 0x18, 0x46, 0xC5, 0x07, 0x97, 0x04, 0x63, 0x00, 0xEF, 0x00, 0x65,
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+	0x80, 0xA3, 0xFF, 0x6B, 0x6C, 0xEC, 0x20, 0x6B, 0x6D, 0xEC, 0xFF, 0x6B, 0x8C, 0xEB, 0x60, 0xC2,
+	0x30, 0xF0, 0x20, 0x6A, 0x80, 0xF7, 0x48, 0x9A, 0x30, 0xF0, 0x20, 0x6B, 0x80, 0xF7, 0x68, 0x9B,
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+	0x20, 0xE8, 0x00, 0x65, 0x30, 0xF0, 0x20, 0x6A, 0xA0, 0xF7, 0x44, 0x9A, 0x30, 0xF0, 0x20, 0x6B,
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+	0x8C, 0xEB, 0x60, 0xC2, 0x20, 0xE8, 0x00, 0x65, 0xFC, 0x63, 0x07, 0x62, 0x30, 0xF0, 0x20, 0x6A,
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+	0x1D, 0xE4, 0x00, 0x6A, 0x7D, 0x67, 0x48, 0xCB, 0x0E, 0x10, 0x5D, 0x67, 0x68, 0xAA, 0x30, 0xF0,
+	0x20, 0x6A, 0xA0, 0xF7, 0x48, 0x9A, 0x49, 0xE3, 0x04, 0x6B, 0x60, 0xC2, 0x7D, 0x67, 0x48, 0xAB,
+	0x20, 0x4A, 0x7D, 0x67, 0x48, 0xCB, 0x7D, 0x67, 0x48, 0xAB, 0x02, 0xF0, 0x00, 0x5A, 0x58, 0x67,
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+	0xFC, 0x63, 0x07, 0x62, 0x30, 0xF0, 0x20, 0x6A, 0xA0, 0xF7, 0x50, 0x9A, 0x60, 0xA2, 0xFF, 0x6A,
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+	0x30, 0xF0, 0x20, 0x6A, 0xA0, 0xF7, 0x54, 0x9A, 0x60, 0xA2, 0xFF, 0x6A, 0x4C, 0xEB, 0x80, 0x6A,
+	0x4B, 0xEA, 0x6C, 0xEA, 0x7D, 0x67, 0x50, 0xC3, 0x9D, 0x67, 0x50, 0xA4, 0x02, 0x2A, 0x01, 0x6A,
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+	0x23, 0x6B, 0xE3, 0xF3, 0x1D, 0x4B, 0x60, 0xDA, 0x32, 0x10, 0x7D, 0x67, 0x48, 0xAB, 0x82, 0xF3,
+	0x08, 0x5A, 0x58, 0x67, 0x14, 0x2A, 0x30, 0xF0, 0x20, 0x6A, 0xA0, 0xF7, 0x5C, 0x9A, 0x30, 0xF0,
+	0x20, 0x6B, 0xA0, 0xF7, 0x7C, 0x9B, 0x80, 0xA3, 0xFF, 0x6B, 0x8C, 0xEB, 0x60, 0xC2, 0x30, 0xF0,
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+	0x60, 0xA2, 0xFF, 0x6A, 0x6C, 0xEA, 0x62, 0x67, 0x08, 0x6A, 0x6C, 0xEA, 0x06, 0x2A, 0x00, 0x18,
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+	0x48, 0x33, 0x30, 0xF0, 0x20, 0x6A, 0x80, 0xF7, 0x10, 0x4A, 0x49, 0xE3, 0x40, 0x9A, 0x00, 0xEA,
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+	0x60, 0x9A, 0x01, 0x92, 0x4D, 0xEB, 0x30, 0xF0, 0x20, 0x6A, 0x88, 0x34, 0xC1, 0xF3, 0x14, 0x4A,
+	0x49, 0xE4, 0x60, 0xDA, 0x30, 0xF0, 0x20, 0x6A, 0xC0, 0xF7, 0x48, 0x9A, 0x01, 0x93, 0x60, 0xDA,
+	0x30, 0xF0, 0x20, 0x6A, 0xC0, 0xF7, 0x4C, 0x9A, 0x00, 0x94, 0x30, 0xF0, 0x20, 0x6B, 0x88, 0x34,
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+	0x6D, 0xE4, 0x60, 0x9B, 0x60, 0xDA, 0x71, 0x10, 0x00, 0x94, 0x00, 0x93, 0x30, 0xF0, 0x20, 0x6A,
+	0x68, 0x33, 0xC1, 0xF3, 0x14, 0x4A, 0x49, 0xE3, 0x60, 0x9A, 0x01, 0x92, 0x4D, 0xEB, 0x30, 0xF0,
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+	0xC0, 0xF7, 0x58, 0x9A, 0x01, 0x93, 0x60, 0xDA, 0x30, 0xF0, 0x20, 0x6A, 0xC0, 0xF7, 0x5C, 0x9A,
+	0x00, 0x94, 0x30, 0xF0, 0x20, 0x6B, 0x88, 0x34, 0xC1, 0xF3, 0x14, 0x4B, 0x6D, 0xE4, 0x60, 0x9B,
+	0x60, 0xDA, 0x4B, 0x10, 0x00, 0x94, 0x00, 0x93, 0x30, 0xF0, 0x20, 0x6A, 0x68, 0x33, 0xC1, 0xF3,
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+	0xC1, 0xF3, 0x14, 0x4A, 0x49, 0xE4, 0x60, 0xDA, 0x30, 0xF0, 0x20, 0x6A, 0xE0, 0xF7, 0x40, 0x9A,
+	0x01, 0x93, 0x60, 0xDA, 0x30, 0xF0, 0x20, 0x6A, 0xE0, 0xF7, 0x44, 0x9A, 0x00, 0x94, 0x30, 0xF0,
+	0x20, 0x6B, 0x88, 0x34, 0xC1, 0xF3, 0x14, 0x4B, 0x6D, 0xE4, 0x60, 0x9B, 0x60, 0xDA, 0x25, 0x10,
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+	0x60, 0x9A, 0x01, 0x92, 0x4D, 0xEB, 0x30, 0xF0, 0x20, 0x6A, 0x88, 0x34, 0xC1, 0xF3, 0x14, 0x4A,
+	0x49, 0xE4, 0x60, 0xDA, 0x30, 0xF0, 0x20, 0x6A, 0xE0, 0xF7, 0x48, 0x9A, 0x01, 0x93, 0x60, 0xDA,
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+	0x40, 0xC3, 0x01, 0x63, 0x20, 0xE8, 0x00, 0x65, 0xFF, 0x63, 0x64, 0x67, 0x45, 0x67, 0x9D, 0x67,
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+	0xBD, 0x67, 0x60, 0xAD, 0x30, 0xF0, 0x20, 0x6A, 0x20, 0xF1, 0x40, 0x9A, 0x49, 0xE3, 0x62, 0x67,
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+	0x06, 0x22, 0xBD, 0x67, 0x80, 0xAD, 0x1F, 0xF7, 0x00, 0x6A, 0x8C, 0xEA, 0x0F, 0x2A, 0xDD, 0x67,
+	0x80, 0xAE, 0x30, 0xF0, 0x20, 0x6A, 0x20, 0xF1, 0x40, 0x9A, 0x49, 0xE4, 0x80, 0xA2, 0xFF, 0x6A,
+	0x8C, 0xEA, 0x00, 0xF6, 0x40, 0x32, 0x00, 0xF6, 0x43, 0x32, 0x0E, 0x10, 0x5D, 0x67, 0x80, 0xAA,
+	0x30, 0xF0, 0x20, 0x6A, 0x20, 0xF1, 0x44, 0x9A, 0x49, 0xE4, 0x80, 0xA2, 0xFF, 0x6A, 0x8C, 0xEA,
+	0x00, 0xF6, 0x40, 0x32, 0x00, 0xF6, 0x43, 0x32, 0xBD, 0x67, 0x82, 0xA5, 0x01, 0x6D, 0xC5, 0x67,
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+	0x20, 0xF1, 0x44, 0x9A, 0x49, 0xE3, 0x62, 0x67, 0xBD, 0x67, 0x80, 0xAD, 0x1F, 0xF7, 0x00, 0x6A,
+	0x8C, 0xEA, 0x02, 0xF0, 0x00, 0x6E, 0xCE, 0xEA, 0x06, 0x22, 0x5D, 0x67, 0x80, 0xAA, 0x1F, 0xF7,
+	0x00, 0x6A, 0x8C, 0xEA, 0x0F, 0x2A, 0xBD, 0x67, 0x80, 0xAD, 0x30, 0xF0, 0x20, 0x6A, 0x20, 0xF1,
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+	0x43, 0x32, 0x0E, 0x10, 0xDD, 0x67, 0x80, 0xAE, 0x30, 0xF0, 0x20, 0x6A, 0x20, 0xF1, 0x44, 0x9A,
+	0x49, 0xE4, 0x80, 0xA2, 0xFF, 0x6A, 0x8C, 0xEA, 0x00, 0xF6, 0x40, 0x32, 0x00, 0xF6, 0x43, 0x32,
+	0xBD, 0x67, 0x82, 0xA5, 0x01, 0x6D, 0xC5, 0x67, 0xC4, 0xEC, 0x86, 0x67, 0x00, 0xF6, 0x80, 0x34,
+	0x00, 0xF6, 0x83, 0x34, 0x8F, 0xEC, 0x00, 0xF6, 0x80, 0x34, 0x00, 0xF6, 0x83, 0x34, 0x8C, 0xEA,
+	0x00, 0xF6, 0x40, 0x34, 0x00, 0xF6, 0x83, 0x34, 0xFF, 0x6A, 0x8C, 0xEA, 0x40, 0xC3, 0x7D, 0x67,
+	0x48, 0xA3, 0xC0, 0xF0, 0x1C, 0x2A, 0x30, 0xF0, 0x20, 0x6A, 0x20, 0xF1, 0x48, 0x9A, 0x40, 0x9A,
+	0x42, 0x33, 0x62, 0x33, 0xFF, 0xF7, 0x1F, 0x6A, 0x6C, 0xEA, 0xE1, 0xF7, 0x1F, 0x6B, 0x6C, 0xEA,
+	0x30, 0xF0, 0x20, 0x6B, 0xC1, 0xF3, 0x14, 0x4B, 0xA2, 0xF4, 0x48, 0xCB, 0xC8, 0x10, 0xBD, 0x67,
+	0x83, 0xA5, 0xDD, 0x67, 0x63, 0xA6, 0x30, 0xF0, 0x20, 0x6A, 0xC1, 0xF3, 0x14, 0x4A, 0x49, 0xE3,
+	0x82, 0xF4, 0x49, 0xA2, 0x00, 0xF6, 0x40, 0x33, 0x00, 0xF6, 0x63, 0x33, 0xBD, 0x67, 0x42, 0xA5,
+	0x01, 0x6D, 0xC5, 0x67, 0xC4, 0xEA, 0x46, 0x67, 0x00, 0xF6, 0x40, 0x32, 0x00, 0xF6, 0x43, 0x32,
+	0x4F, 0xEA, 0x00, 0xF6, 0x40, 0x32, 0x00, 0xF6, 0x43, 0x32, 0x6C, 0xEA, 0x00, 0xF6, 0x40, 0x33,
+	0x00, 0xF6, 0x63, 0x33, 0xFF, 0x6A, 0x4C, 0xEB, 0x30, 0xF0, 0x20, 0x6A, 0xC1, 0xF3, 0x14, 0x4A,
+	0x49, 0xE4, 0x82, 0xF4, 0x69, 0xC2, 0x5D, 0x67, 0x60, 0xAA, 0x1F, 0xF7, 0x00, 0x6A, 0x6C, 0xEA,
+	0x02, 0xF0, 0x00, 0x6B, 0x6E, 0xEA, 0x06, 0x22, 0x9D, 0x67, 0x60, 0xAC, 0x1F, 0xF7, 0x00, 0x6A,
+	0x6C, 0xEA, 0x47, 0x2A, 0xBD, 0x67, 0x60, 0xAD, 0x30, 0xF0, 0x20, 0x6A, 0x20, 0xF1, 0x40, 0x9A,
+	0x49, 0xE3, 0x62, 0x67, 0xDD, 0x67, 0x80, 0xAE, 0x1F, 0xF7, 0x00, 0x6A, 0x8C, 0xEA, 0x02, 0xF0,
+	0x00, 0x6C, 0x8E, 0xEA, 0x06, 0x22, 0xBD, 0x67, 0x80, 0xAD, 0x1F, 0xF7, 0x00, 0x6A, 0x8C, 0xEA,
+	0x0F, 0x2A, 0xDD, 0x67, 0x80, 0xAE, 0x30, 0xF0, 0x20, 0x6A, 0x20, 0xF1, 0x40, 0x9A, 0x49, 0xE4,
+	0x80, 0xA2, 0xFF, 0x6A, 0x8C, 0xEA, 0x00, 0xF6, 0x40, 0x32, 0x00, 0xF6, 0x43, 0x32, 0x0E, 0x10,
+	0x5D, 0x67, 0x80, 0xAA, 0x30, 0xF0, 0x20, 0x6A, 0x20, 0xF1, 0x44, 0x9A, 0x49, 0xE4, 0x80, 0xA2,
+	0xFF, 0x6A, 0x8C, 0xEA, 0x00, 0xF6, 0x40, 0x32, 0x00, 0xF6, 0x43, 0x32, 0xBD, 0x67, 0x82, 0xA5,
+	0x01, 0x6D, 0xC5, 0x67, 0xC4, 0xEC, 0x86, 0x67, 0x00, 0xF6, 0x80, 0x34, 0x00, 0xF6, 0x83, 0x34,
+	0x8D, 0xEA, 0x00, 0xF6, 0x40, 0x34, 0x00, 0xF6, 0x83, 0x34, 0xFF, 0x6A, 0x8C, 0xEA, 0x40, 0xC3,
+	0x46, 0x10, 0x5D, 0x67, 0x60, 0xAA, 0x30, 0xF0, 0x20, 0x6A, 0x20, 0xF1, 0x44, 0x9A, 0x49, 0xE3,
+	0x62, 0x67, 0xBD, 0x67, 0x80, 0xAD, 0x1F, 0xF7, 0x00, 0x6A, 0x8C, 0xEA, 0x02, 0xF0, 0x00, 0x6E,
+	0xCE, 0xEA, 0x06, 0x22, 0x5D, 0x67, 0x80, 0xAA, 0x1F, 0xF7, 0x00, 0x6A, 0x8C, 0xEA, 0x0F, 0x2A,
+	0xBD, 0x67, 0x80, 0xAD, 0x30, 0xF0, 0x20, 0x6A, 0x20, 0xF1, 0x40, 0x9A, 0x49, 0xE4, 0x80, 0xA2,
+	0xFF, 0x6A, 0x8C, 0xEA, 0x00, 0xF6, 0x40, 0x32, 0x00, 0xF6, 0x43, 0x32, 0x0E, 0x10, 0xDD, 0x67,
+	0x80, 0xAE, 0x30, 0xF0, 0x20, 0x6A, 0x20, 0xF1, 0x44, 0x9A, 0x49, 0xE4, 0x80, 0xA2, 0xFF, 0x6A,
+	0x8C, 0xEA, 0x00, 0xF6, 0x40, 0x32, 0x00, 0xF6, 0x43, 0x32, 0xBD, 0x67, 0x82, 0xA5, 0x01, 0x6D,
+	0xC5, 0x67, 0xC4, 0xEC, 0x86, 0x67, 0x00, 0xF6, 0x80, 0x34, 0x00, 0xF6, 0x83, 0x34, 0x8D, 0xEA,
+	0x00, 0xF6, 0x40, 0x34, 0x00, 0xF6, 0x83, 0x34, 0xFF, 0x6A, 0x8C, 0xEA, 0x40, 0xC3, 0x01, 0x63,
+	0x20, 0xE8, 0x00, 0x65, 0xFF, 0x63, 0x44, 0x67, 0x7D, 0x67, 0x48, 0xC3, 0x9D, 0x67, 0x48, 0xA4,
+	0x4E, 0x32, 0x7D, 0x67, 0x41, 0xC3, 0x9D, 0x67, 0x68, 0xA4, 0x07, 0x6A, 0x6C, 0xEA, 0x7D, 0x67,
+	0x40, 0xC3, 0x9D, 0x67, 0x61, 0xA4, 0x30, 0xF0, 0x20, 0x6A, 0xC1, 0xF3, 0x14, 0x4A, 0x49, 0xE3,
+	0x82, 0xF4, 0x49, 0xA2, 0x62, 0x67, 0x9D, 0x67, 0x40, 0xA4, 0x67, 0xEA, 0x01, 0x6A, 0x4C, 0xEB,
+	0xFF, 0x6A, 0x6C, 0xEA, 0x02, 0x22, 0x01, 0x6A, 0x01, 0x10, 0x00, 0x6A, 0x01, 0x63, 0x20, 0xE8,
+	0xFD, 0x63, 0x05, 0x62, 0x30, 0xF0, 0x20, 0x6A, 0xC1, 0xF3, 0x14, 0x4A, 0xA2, 0xF4, 0x41, 0xA2,
+	0x04, 0x6B, 0x6C, 0xEA, 0x06, 0x22, 0x30, 0xF0, 0x20, 0x6A, 0x60, 0xF1, 0x40, 0x9A, 0x00, 0x6B,
+	0x60, 0xC2, 0x30, 0xF0, 0x20, 0x6A, 0x60, 0xF1, 0x44, 0x9A, 0x02, 0x6B, 0x60, 0xC2, 0x30, 0xF0,
+	0x20, 0x6A, 0x60, 0xF1, 0x48, 0x9A, 0x04, 0x6B, 0x60, 0xDA, 0x30, 0xF0, 0x20, 0x6A, 0xC1, 0xF3,
+	0x14, 0x4A, 0x02, 0xF5, 0x4A, 0xA2, 0x46, 0x33, 0xFF, 0x6A, 0x6C, 0xEA, 0xFF, 0x6B, 0x59, 0x4B,
+	0x83, 0x67, 0x00, 0x6D, 0xC2, 0x67, 0x00, 0x18, 0x89, 0xF0, 0x30, 0xF0, 0x20, 0x6A, 0xC1, 0xF3,
+	0x14, 0x4A, 0xA2, 0xF4, 0x81, 0xA2, 0x04, 0x6B, 0x8D, 0xEB, 0xA2, 0xF4, 0x61, 0xC2, 0x05, 0x97,
+	0x03, 0x63, 0x00, 0xEF, 0x64, 0x67, 0x45, 0x67, 0x9D, 0x67, 0x60, 0xC4, 0x7D, 0x67, 0x44, 0xC3,
+	0x9D, 0x67, 0x40, 0xA4, 0x01, 0x6B, 0x4E, 0xEB, 0x1A, 0x23, 0x02, 0x6B, 0x4E, 0xEB, 0x20, 0x23,
+	0x27, 0x2A, 0x5D, 0x67, 0x64, 0xA2, 0x01, 0x6A, 0x4C, 0xEB, 0xFF, 0x6A, 0x83, 0x67, 0x4C, 0xEC,
+	0x30, 0xF0, 0x20, 0x6A, 0xC1, 0xF3, 0x14, 0x4A, 0x01, 0x6B, 0x8C, 0xEB, 0xA2, 0xF4, 0xA1, 0xA2,
+	0x02, 0x6C, 0x8B, 0xEC, 0xAC, 0xEC, 0x8D, 0xEB, 0xA2, 0xF4, 0x61, 0xC2, 0x11, 0x10, 0x30, 0xF0,
+	0x20, 0x6A, 0xC1, 0xF3, 0x14, 0x4A, 0x9D, 0x67, 0x64, 0xA4, 0xA2, 0xF4, 0x64, 0xC2, 0x08, 0x10,
+	0x30, 0xF0, 0x20, 0x6A, 0xC1, 0xF3, 0x14, 0x4A, 0x9D, 0x67, 0x64, 0xA4, 0xA2, 0xF4, 0x60, 0xC2,
+	0x30, 0xF0, 0x20, 0x6A, 0x60, 0xF1, 0x4C, 0x9A, 0x60, 0xA2, 0xFF, 0x6A, 0x6C, 0xEA, 0x62, 0x67,
+	0x10, 0x6A, 0x6C, 0xEA, 0x41, 0x22, 0x7D, 0x67, 0x40, 0xA3, 0x00, 0x52, 0x78, 0x67, 0x3C, 0x2B,
+	0x02, 0x52, 0x78, 0x67, 0x04, 0x2B, 0x02, 0x6B, 0x6E, 0xEA, 0x2B, 0x22, 0x35, 0x10, 0x30, 0xF0,
+	0x20, 0x6A, 0x60, 0xF1, 0x70, 0x9A, 0x30, 0xF0, 0x20, 0x6A, 0xC1, 0xF3, 0x14, 0x4A, 0xA2, 0xF4,
+	0x44, 0xA2, 0x00, 0xF6, 0x40, 0x34, 0x00, 0xF6, 0x83, 0x34, 0xFF, 0x6A, 0x8C, 0xEA, 0x7F, 0x6C,
+	0x8C, 0xEA, 0x30, 0xF0, 0x20, 0x6C, 0xC1, 0xF3, 0x14, 0x4C, 0xA2, 0xF4, 0xA1, 0xA4, 0x01, 0x6C,
+	0x8C, 0xED, 0xFF, 0x6C, 0xAC, 0xEC, 0x9C, 0x34, 0x00, 0xF6, 0x80, 0x34, 0x00, 0xF6, 0x83, 0x34,
+	0x8D, 0xEA, 0x00, 0xF6, 0x40, 0x34, 0x00, 0xF6, 0x83, 0x34, 0xFF, 0x6A, 0x8C, 0xEA, 0x40, 0xC3,
+	0x0B, 0x10, 0x30, 0xF0, 0x20, 0x6A, 0x60, 0xF1, 0x54, 0x9A, 0x30, 0xF0, 0x20, 0x6B, 0xC1, 0xF3,
+	0x14, 0x4B, 0xA2, 0xF4, 0x60, 0xA3, 0x60, 0xC2, 0x20, 0xE8, 0x00, 0x65, 0xFD, 0x63, 0x05, 0x62,
+	0x30, 0xF0, 0x20, 0x6A, 0x64, 0xF0, 0x10, 0x4A, 0x82, 0x67, 0x00, 0x6D, 0x6C, 0x6E, 0x00, 0x18,
+	0x1D, 0xE4, 0x30, 0xF0, 0x20, 0x6A, 0xC1, 0xF3, 0x14, 0x4A, 0x02, 0x6B, 0x82, 0xF4, 0x7E, 0xC2,
+	0x30, 0xF0, 0x20, 0x6A, 0xC1, 0xF3, 0x14, 0x4A, 0x01, 0x6B, 0xA2, 0xF4, 0x6A, 0xC2, 0x30, 0xF0,
+	0x20, 0x6A, 0xC1, 0xF3, 0x14, 0x4A, 0x01, 0x6B, 0xA2, 0xF4, 0x6B, 0xC2, 0x30, 0xF0, 0x20, 0x6A,
+	0xC1, 0xF3, 0x14, 0x4A, 0x0A, 0x6B, 0xA2, 0xF4, 0x6C, 0xC2, 0x30, 0xF0, 0x20, 0x6A, 0xC1, 0xF3,
+	0x14, 0x4A, 0x05, 0x6B, 0xA2, 0xF4, 0x72, 0xCA, 0x30, 0xF0, 0x20, 0x6A, 0xC1, 0xF3, 0x14, 0x4A,
+	0xC2, 0xF4, 0x43, 0xA2, 0x64, 0x42, 0xFF, 0x6A, 0x4C, 0xEB, 0x30, 0xF0, 0x20, 0x6A, 0xC1, 0xF3,
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+	0xE0, 0xF1, 0x50, 0x9A, 0x30, 0xF0, 0x20, 0x6B, 0xE0, 0xF1, 0x70, 0x9B, 0x80, 0xA3, 0xFF, 0x6B,
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+	0x50, 0xA2, 0x61, 0x42, 0xFF, 0x6A, 0x4C, 0xEB, 0x30, 0xF0, 0x20, 0x6A, 0xC1, 0xF3, 0x14, 0x4A,
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+	0x45, 0xC3, 0x04, 0x92, 0x04, 0x4A, 0x40, 0xA2, 0x9D, 0x67, 0x46, 0xC4, 0x04, 0x92, 0x05, 0x4A,
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+	0x9D, 0x67, 0x41, 0xC4, 0x7D, 0x67, 0x54, 0xA3, 0x29, 0x2A, 0x00, 0x6A, 0x9D, 0x67, 0x40, 0xC4,
+	0x20, 0x10, 0x7D, 0x67, 0x40, 0xA3, 0x9D, 0x67, 0x49, 0xE4, 0x44, 0xA2, 0xFF, 0x6B, 0x6E, 0xEA,
+	0x0C, 0x2A, 0x9D, 0x67, 0x40, 0xA4, 0x7D, 0x67, 0x49, 0xE3, 0x00, 0x6B, 0x64, 0xC2, 0x9D, 0x67,
+	0x40, 0xA4, 0x01, 0x4A, 0x7D, 0x67, 0x40, 0xC3, 0x0C, 0x10, 0x9D, 0x67, 0x40, 0xA4, 0x9D, 0x67,
+	0x4D, 0xE4, 0x64, 0xA3, 0x81, 0x43, 0xFF, 0x6B, 0x8C, 0xEB, 0x9D, 0x67, 0x49, 0xE4, 0x64, 0xC2,
+	0x05, 0x10, 0x7D, 0x67, 0x40, 0xA3, 0x06, 0x5A, 0x58, 0x67, 0xDB, 0x2A, 0x7D, 0x67, 0x58, 0xA3,
+	0x04, 0x6C, 0x8E, 0xEA, 0x0E, 0x2A, 0x5D, 0x67, 0x64, 0xA2, 0x04, 0x92, 0x60, 0xC2, 0x04, 0x92,
+	0x01, 0x4A, 0x9D, 0x67, 0x65, 0xA4, 0x60, 0xC2, 0x04, 0x92, 0x02, 0x4A, 0x00, 0x6B, 0x60, 0xC2,
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+	0x04, 0x92, 0x60, 0xC2, 0x04, 0x92, 0x61, 0x42, 0x9D, 0x67, 0x45, 0xA4, 0x5F, 0x6C, 0x8C, 0xEA,
+	0x20, 0x6C, 0x4D, 0xEC, 0xFF, 0x6A, 0x8C, 0xEA, 0x40, 0xC3, 0x04, 0x92, 0x02, 0x4A, 0x9D, 0x67,
+	0x64, 0xA4, 0x60, 0xC2, 0x04, 0x92, 0x03, 0x4A, 0x04, 0x93, 0x03, 0x4B, 0x80, 0xA3, 0x20, 0x6B,
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+	0x60, 0xC2, 0x04, 0x92, 0x05, 0x4A, 0x9D, 0x67, 0x67, 0xA4, 0x60, 0xC2, 0x04, 0x92, 0x06, 0x4A,
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+	0x02, 0x63, 0x20, 0xE8, 0xFC, 0x63, 0x07, 0x62, 0x08, 0xD4, 0x45, 0x67, 0x7D, 0x67, 0x20, 0xF0,
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+	0x40, 0x9A, 0x83, 0x67, 0xA2, 0x67, 0x01, 0x6E, 0x00, 0x18, 0x08, 0xF4, 0xA1, 0xF0, 0x0C, 0x6B,
+	0x30, 0xF0, 0x20, 0x6A, 0x40, 0xF3, 0x4C, 0x9A, 0x83, 0x67, 0xA2, 0x67, 0x00, 0x6E, 0x00, 0x18,
+	0x08, 0xF4, 0xA1, 0xF0, 0x0C, 0x6B, 0x30, 0xF0, 0x20, 0x6A, 0x20, 0xF3, 0x48, 0x9A, 0x83, 0x67,
+	0xA2, 0x67, 0x01, 0x6E, 0x00, 0x18, 0x08, 0xF4, 0xC1, 0xF0, 0x04, 0x6B, 0x30, 0xF0, 0x20, 0x6A,
+	0x40, 0xF3, 0x50, 0x9A, 0x83, 0x67, 0xA2, 0x67, 0x01, 0x6E, 0x00, 0x18, 0x08, 0xF4, 0x07, 0x93,
+	0x01, 0xF4, 0x00, 0x6A, 0x6D, 0xEA, 0x07, 0xD2, 0x51, 0x11, 0x5D, 0x67, 0x20, 0xF0, 0x6C, 0xA2,
+	0x0F, 0x6A, 0x6C, 0xEA, 0x48, 0x33, 0x01, 0x6A, 0x6D, 0xEA, 0xA1, 0xF0, 0x0C, 0x6B, 0x83, 0x67,
+	0xFF, 0x6D, 0xC2, 0x67, 0x00, 0x18, 0x08, 0xF4, 0x7D, 0x67, 0x20, 0xF0, 0x4C, 0xA3, 0x01, 0x6C,
+	0x8E, 0xEA, 0x0B, 0x2A, 0x7D, 0x67, 0x20, 0xF0, 0x4C, 0xA3, 0x01, 0xF2, 0x00, 0x6B, 0x83, 0x67,
+	0x10, 0x6D, 0xC2, 0x67, 0x00, 0x18, 0x08, 0xF4, 0x07, 0x10, 0x01, 0xF2, 0x00, 0x6A, 0x82, 0x67,
+	0x10, 0x6D, 0x00, 0x6E, 0x00, 0x18, 0x08, 0xF4, 0xA1, 0xF0, 0x0C, 0x6B, 0x01, 0xF4, 0x00, 0x6A,
+	0x83, 0x67, 0xA2, 0x67, 0x00, 0x6E, 0x00, 0x18, 0x08, 0xF4, 0xA1, 0xF0, 0x0C, 0x6B, 0x30, 0xF0,
+	0x20, 0x6A, 0x40, 0xF3, 0x44, 0x9A, 0x83, 0x67, 0xA2, 0x67, 0x01, 0x6E, 0x00, 0x18, 0x08, 0xF4,
+	0xA1, 0xF0, 0x0C, 0x6B, 0x30, 0xF0, 0x20, 0x6A, 0x40, 0xF3, 0x54, 0x9A, 0x83, 0x67, 0xA2, 0x67,
+	0x00, 0x6E, 0x00, 0x18, 0x08, 0xF4, 0xA1, 0xF0, 0x0C, 0x6B, 0x30, 0xF0, 0x20, 0x6A, 0x40, 0xF3,
+	0x58, 0x9A, 0x83, 0x67, 0xA2, 0x67, 0x01, 0x6E, 0x00, 0x18, 0x08, 0xF4, 0xC1, 0xF0, 0x04, 0x6B,
+	0x30, 0xF0, 0x20, 0x6A, 0x40, 0xF3, 0x50, 0x9A, 0x83, 0x67, 0xA2, 0x67, 0x01, 0x6E, 0x00, 0x18,
+	0x08, 0xF4, 0x07, 0x93, 0x01, 0xF4, 0x01, 0x6A, 0x4B, 0xEA, 0x6C, 0xEA, 0x07, 0xD2, 0x07, 0x93,
+	0x01, 0xF0, 0x00, 0x6A, 0x6D, 0xEA, 0x07, 0xD2, 0xE9, 0x10, 0x9D, 0x67, 0x20, 0xF0, 0x6C, 0xA4,
+	0x0F, 0x6A, 0x6C, 0xEA, 0x48, 0x33, 0x02, 0x6A, 0x6D, 0xEA, 0xA1, 0xF0, 0x0C, 0x6B, 0x83, 0x67,
+	0xFF, 0x6D, 0xC2, 0x67, 0x00, 0x18, 0x08, 0xF4, 0xA1, 0xF0, 0x0C, 0x6B, 0x06, 0xF0, 0x00, 0x6A,
+	0x83, 0x67, 0xA2, 0x67, 0x00, 0x6E, 0x00, 0x18, 0x08, 0xF4, 0xA1, 0xF0, 0x0C, 0x6B, 0x30, 0xF0,
+	0x20, 0x6A, 0x20, 0xF3, 0x4C, 0x9A, 0x83, 0x67, 0xA2, 0x67, 0x01, 0x6E, 0x00, 0x18, 0x08, 0xF4,
+	0xA1, 0xF0, 0x0C, 0x6B, 0x30, 0xF0, 0x20, 0x6A, 0x40, 0xF3, 0x5C, 0x9A, 0x83, 0x67, 0xA2, 0x67,
+	0x00, 0x6E, 0x00, 0x18, 0x08, 0xF4, 0xA1, 0xF0, 0x0C, 0x6B, 0x30, 0xF0, 0x20, 0x6A, 0x40, 0xF3,
+	0x50, 0x9A, 0x83, 0x67, 0xA2, 0x67, 0x01, 0x6E, 0x00, 0x18, 0x08, 0xF4, 0xC1, 0xF0, 0x04, 0x6B,
+	0x30, 0xF0, 0x20, 0x6A, 0x40, 0xF3, 0x50, 0x9A, 0x83, 0x67, 0xA2, 0x67, 0x01, 0x6E, 0x00, 0x18,
+	0x08, 0xF4, 0x07, 0x93, 0x01, 0xF4, 0x01, 0x6A, 0x4B, 0xEA, 0x6C, 0xEA, 0x07, 0xD2, 0x07, 0x93,
+	0x00, 0xF4, 0x00, 0x6A, 0x6D, 0xEA, 0x07, 0xD2, 0x99, 0x10, 0xA1, 0xF0, 0x0C, 0x6A, 0x82, 0x67,
+	0xFF, 0x6D, 0x40, 0x6E, 0x00, 0x18, 0x08, 0xF4, 0xA1, 0xF0, 0x0C, 0x6B, 0x00, 0xF3, 0x00, 0x6A,
+	0x83, 0x67, 0xA2, 0x67, 0x02, 0x6E, 0x00, 0x18, 0x08, 0xF4, 0xA1, 0xF0, 0x0C, 0x6B, 0x30, 0xF0,
+	0x20, 0x6A, 0x20, 0xF3, 0x40, 0x9A, 0x83, 0x67, 0xA2, 0x67, 0x00, 0x6E, 0x00, 0x18, 0x08, 0xF4,
+	0xA1, 0xF0, 0x0C, 0x6B, 0x30, 0xF0, 0x20, 0x6A, 0x40, 0xF3, 0x4C, 0x9A, 0x83, 0x67, 0xA2, 0x67,
+	0x02, 0x6E, 0x00, 0x18, 0x08, 0xF4, 0xA1, 0xF0, 0x0C, 0x6B, 0x30, 0xF0, 0x20, 0x6A, 0x20, 0xF3,
+	0x48, 0x9A, 0x83, 0x67, 0xA2, 0x67, 0x00, 0x6E, 0x00, 0x18, 0x08, 0xF4, 0xC1, 0xF0, 0x04, 0x6B,
+	0x30, 0xF0, 0x20, 0x6A, 0x40, 0xF3, 0x50, 0x9A, 0x83, 0x67, 0xA2, 0x67, 0x00, 0x6E, 0x00, 0x18,
+	0x08, 0xF4, 0xC1, 0xF0, 0x08, 0x6B, 0x30, 0xF0, 0x20, 0x6A, 0x60, 0xF3, 0x40, 0x9A, 0x83, 0x67,
+	0xA2, 0x67, 0x01, 0x6E, 0x00, 0x18, 0x08, 0xF4, 0x07, 0x93, 0x01, 0xF4, 0x00, 0x6A, 0x6D, 0xEA,
+	0x07, 0xD2, 0x4C, 0x10, 0xA1, 0xF0, 0x0C, 0x6A, 0x82, 0x67, 0xFF, 0x6D, 0x80, 0x6E, 0x00, 0x18,
+	0x08, 0xF4, 0xA1, 0xF0, 0x0C, 0x6B, 0x00, 0xF3, 0x00, 0x6A, 0x83, 0x67, 0xA2, 0x67, 0x03, 0x6E,
+	0x00, 0x18, 0x08, 0xF4, 0xA1, 0xF0, 0x0C, 0x6B, 0x30, 0xF0, 0x20, 0x6A, 0x20, 0xF3, 0x40, 0x9A,
+	0x83, 0x67, 0xA2, 0x67, 0x00, 0x6E, 0x00, 0x18, 0x08, 0xF4, 0xA1, 0xF0, 0x0C, 0x6B, 0x30, 0xF0,
+	0x20, 0x6A, 0x40, 0xF3, 0x4C, 0x9A, 0x83, 0x67, 0xA2, 0x67, 0x03, 0x6E, 0x00, 0x18, 0x08, 0xF4,
+	0xA1, 0xF0, 0x0C, 0x6B, 0x30, 0xF0, 0x20, 0x6A, 0x20, 0xF3, 0x48, 0x9A, 0x83, 0x67, 0xA2, 0x67,
+	0x00, 0x6E, 0x00, 0x18, 0x08, 0xF4, 0xC1, 0xF0, 0x04, 0x6B, 0x30, 0xF0, 0x20, 0x6A, 0x40, 0xF3,
+	0x50, 0x9A, 0x83, 0x67, 0xA2, 0x67, 0x00, 0x6E, 0x00, 0x18, 0x08, 0xF4, 0xC1, 0xF0, 0x08, 0x6B,
+	0x30, 0xF0, 0x20, 0x6A, 0x60, 0xF3, 0x40, 0x9A, 0x83, 0x67, 0xA2, 0x67, 0x01, 0x6E, 0x00, 0x18,
+	0x08, 0xF4, 0x07, 0x93, 0x01, 0xF4, 0x00, 0x6A, 0x6D, 0xEA, 0x07, 0xD2, 0x0A, 0x93, 0x30, 0xF0,
+	0x20, 0x6A, 0x00, 0xF3, 0x58, 0x9A, 0x07, 0x94, 0x04, 0xD4, 0x83, 0x67, 0x00, 0x6D, 0x18, 0x6E,
+	0xE2, 0x67, 0x80, 0x18, 0xDC, 0x00, 0x62, 0x67, 0x9D, 0x67, 0x58, 0xA4, 0x6C, 0xEA, 0x7D, 0x67,
+	0x58, 0xC3, 0x9D, 0x67, 0x58, 0xA4, 0x02, 0x2A, 0x00, 0x6A, 0x1F, 0x10, 0x0A, 0x93, 0x0C, 0x92,
+	0x83, 0x67, 0xA2, 0x67, 0x80, 0x18, 0x76, 0x00, 0x0A, 0x93, 0x0C, 0x92, 0x83, 0x67, 0xA2, 0x67,
+	0x80, 0x18, 0x73, 0x00, 0x0A, 0x92, 0x82, 0x67, 0x80, 0x18, 0x72, 0x00, 0x01, 0xF0, 0x08, 0x6A,
+	0x82, 0x67, 0xFF, 0x6D, 0x00, 0x6E, 0x00, 0x18, 0x08, 0xF4, 0x01, 0xF0, 0x08, 0x6A, 0x82, 0x67,
+	0xFF, 0x6D, 0x11, 0x6E, 0x00, 0x18, 0x08, 0xF4, 0x01, 0x6A, 0x09, 0x97, 0x05, 0x63, 0x00, 0xEF,
+	0xFD, 0x63, 0x05, 0x62, 0x06, 0xD4, 0x65, 0x67, 0x46, 0x67, 0x09, 0xD7, 0x9D, 0x67, 0x7C, 0xC4,
+	0x7D, 0x67, 0x20, 0xF0, 0x40, 0xC3, 0x9D, 0x67, 0x5C, 0xA4, 0x06, 0x93, 0x83, 0x67, 0xA2, 0x67,
+	0x80, 0x18, 0x76, 0x01, 0x02, 0x2A, 0x00, 0x6A, 0x17, 0x10, 0x7D, 0x67, 0x5C, 0xA3, 0x06, 0x93,
+	0x83, 0x67, 0xA2, 0x67, 0x80, 0x18, 0xD7, 0x01, 0x02, 0x2A, 0x00, 0x6A, 0x0D, 0x10, 0x9D, 0x67,
+	0x20, 0xF0, 0x60, 0xA4, 0x06, 0x94, 0x09, 0x92, 0xA3, 0x67, 0xC2, 0x67, 0x80, 0x18, 0xBA, 0x02,
+	0x02, 0x2A, 0x00, 0x6A, 0x01, 0x10, 0x01, 0x6A, 0x05, 0x97, 0x03, 0x63, 0x00, 0xEF, 0x00, 0x65,
+	0xFD, 0x63, 0x05, 0x62, 0x06, 0xD4, 0x07, 0xD5, 0x07, 0x92, 0x0C, 0x2A, 0x01, 0xF0, 0x08, 0x6B,
+	0x30, 0xF0, 0x20, 0x6A, 0x60, 0xF3, 0x44, 0x9A, 0x83, 0x67, 0xA2, 0x67, 0x00, 0x6E, 0x00, 0x18,
+	0x08, 0xF4, 0x39, 0x10, 0x07, 0x92, 0x01, 0x6B, 0x6E, 0xEA, 0x33, 0x2A, 0x01, 0xF0, 0x08, 0x6B,
+	0x30, 0xF0, 0x20, 0x6A, 0x60, 0xF3, 0x44, 0x9A, 0x83, 0x67, 0xA2, 0x67, 0x03, 0x6E, 0x00, 0x18,
+	0x08, 0xF4, 0x21, 0xF0, 0x0C, 0x6B, 0x01, 0x6A, 0x4B, 0xEA, 0x83, 0x67, 0xA2, 0x67, 0x00, 0x18,
+	0xF4, 0xF3, 0x62, 0x67, 0x30, 0xF0, 0x20, 0x6A, 0xA1, 0xF3, 0x78, 0xDA, 0x21, 0xF0, 0x18, 0x6B,
+	0x01, 0x6A, 0x4B, 0xEA, 0x83, 0x67, 0xA2, 0x67, 0x00, 0x18, 0xF4, 0xF3, 0x62, 0x67, 0x30, 0xF0,
+	0x20, 0x6A, 0xA1, 0xF3, 0x7C, 0xDA, 0x21, 0xF0, 0x10, 0x6B, 0x01, 0x6A, 0x4B, 0xEA, 0x83, 0x67,
+	0xA2, 0x67, 0x00, 0x18, 0xF4, 0xF3, 0x62, 0x67, 0x30, 0xF0, 0x20, 0x6A, 0xC1, 0xF3, 0x60, 0xDA,
+	0x02, 0x10, 0x00, 0x6A, 0x01, 0x10, 0x01, 0x6A, 0x05, 0x97, 0x03, 0x63, 0x00, 0xEF, 0x00, 0x65,
+	0x0D, 0x48, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+};
+u32 array_length_tc_8821c_fw_wowlan = 69432;
+
+#endif
+
+void
+odm_read_firmware_tc_8821c_fw_wowlan(
+	struct PHY_DM_STRUCT    *p_dm_odm,
+	u8       *p_firmware,
+	u32       *p_firmware_size
+)
+{
+#if (DM_ODM_SUPPORT_TYPE & (ODM_CE))
+	*((SIZE_PTR *)p_firmware) = (SIZE_PTR)array_tc_8821c_fw_wowlan;
+#else
+	odm_move_memory(p_dm_odm, p_firmware, array_tc_8821c_fw_wowlan, array_length_tc_8821c_fw_wowlan);
+#endif
+	*p_firmware_size = array_length_tc_8821c_fw_wowlan;
+}
+
+
+
+#endif /* end of (defined(CONFIG_AP_WOWLAN) || (DM_ODM_SUPPORT_TYPE & (ODM_AP)))*/
+
+#endif /* end of HWIMG_SUPPORT*/
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/rtl8821c/halhwimg8821c_testchip_fw.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/rtl8821c/halhwimg8821c_testchip_fw.h
--- linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/rtl8821c/halhwimg8821c_testchip_fw.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/rtl8821c/halhwimg8821c_testchip_fw.h	2020-04-10 16:35:06.834660908 +0300
@@ -0,0 +1,61 @@
+/******************************************************************************
+*
+* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
+*
+* This program is free software; you can redistribute it and/or modify it
+* under the terms of version 2 of the GNU General Public License as
+* published by the Free Software Foundation.
+*
+* This program is distributed in the hope that it will be useful, but WITHOUT
+* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+* more details.
+*
+* You should have received a copy of the GNU General Public License along with
+* this program; if not, write to the Free Software Foundation, Inc.,
+* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
+*
+*
+******************************************************************************/
+
+/*Image2HeaderVersion: 2.16*/
+#if (RTL8821C_SUPPORT == 1)
+#ifndef __INC_TC_FW_HW_IMG_8821C_H
+#define __INC_TC_FW_HW_IMG_8821C_H
+
+
+/******************************************************************************
+*                           FW_AP.TXT
+******************************************************************************/
+
+void
+odm_read_firmware_tc_8821c_fw_ap(
+	struct PHY_DM_STRUCT    *p_dm_odm,
+	u8       *p_firmware,
+	u32       *p_firmware_size
+);
+
+/******************************************************************************
+*                           FW_NIC.TXT
+******************************************************************************/
+
+void
+odm_read_firmware_tc_8821c_fw_nic(
+	struct PHY_DM_STRUCT    *p_dm_odm,
+	u8       *p_firmware,
+	u32       *p_firmware_size
+);
+
+/******************************************************************************
+*                           FW_WoWLAN.TXT
+******************************************************************************/
+
+void
+odm_read_firmware_tc_8821c_fw_wowlan(
+	struct PHY_DM_STRUCT    *p_dm_odm,
+	u8       *p_firmware,
+	u32       *p_firmware_size
+);
+
+#endif
+#endif /* end of HWIMG_SUPPORT*/
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/rtl8821c/halhwimg8821c_testchip_mac.c linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/rtl8821c/halhwimg8821c_testchip_mac.c
--- linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/rtl8821c/halhwimg8821c_testchip_mac.c	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/rtl8821c/halhwimg8821c_testchip_mac.c	2020-04-10 16:35:06.834660908 +0300
@@ -0,0 +1,324 @@
+/******************************************************************************
+*
+* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
+*
+* This program is free software; you can redistribute it and/or modify it
+* under the terms of version 2 of the GNU General Public License as
+* published by the Free Software Foundation.
+*
+* This program is distributed in the hope that it will be useful, but WITHOUT
+* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+* more details.
+*
+* You should have received a copy of the GNU General Public License along with
+* this program; if not, write to the Free Software Foundation, Inc.,
+* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
+*
+*
+******************************************************************************/
+
+/*Image2HeaderVersion: 2.22*/
+#include "mp_precomp.h"
+#include "../phydm_precomp.h"
+
+#if (RTL8821C_SUPPORT == 1)
+static boolean
+check_positive(
+	struct PHY_DM_STRUCT     *p_dm_odm,
+	const u32  condition1,
+	const u32  condition2,
+	const u32  condition3,
+	const u32  condition4
+)
+{
+	u8    _board_type = ((p_dm_odm->board_type & BIT(4)) >> 4) << 0 | /* _GLNA*/
+		    ((p_dm_odm->board_type & BIT(3)) >> 3) << 1 | /* _GPA*/
+		    ((p_dm_odm->board_type & BIT(7)) >> 7) << 2 | /* _ALNA*/
+		    ((p_dm_odm->board_type & BIT(6)) >> 6) << 3 | /* _APA */
+		    ((p_dm_odm->board_type & BIT(2)) >> 2) << 4;  /* _BT*/
+
+	u32	cond1   = condition1, cond2 = condition2, cond3 = condition3, cond4 = condition4;
+	u32    driver1 = p_dm_odm->cut_version       << 24 |
+			 (p_dm_odm->support_interface & 0xF0) << 16 |
+			 p_dm_odm->support_platform  << 16 |
+			 p_dm_odm->package_type      << 12 |
+			 (p_dm_odm->support_interface & 0x0F) << 8  |
+			 _board_type;
+
+	u32    driver2 = (p_dm_odm->type_glna & 0xFF) <<  0 |
+			 (p_dm_odm->type_gpa & 0xFF)  <<  8 |
+			 (p_dm_odm->type_alna & 0xFF) << 16 |
+			 (p_dm_odm->type_apa & 0xFF)  << 24;
+
+	u32    driver3 = 0;
+
+	u32    driver4 = (p_dm_odm->type_glna & 0xFF00) >>  8 |
+			 (p_dm_odm->type_gpa & 0xFF00) |
+			 (p_dm_odm->type_alna & 0xFF00) << 8 |
+			 (p_dm_odm->type_apa & 0xFF00)  << 16;
+
+	ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_TRACE,
+		("===> check_positive (cond1, cond2, cond3, cond4) = (0x%X 0x%X 0x%X 0x%X)\n", cond1, cond2, cond3, cond4));
+	ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_TRACE,
+		("===> check_positive (driver1, driver2, driver3, driver4) = (0x%X 0x%X 0x%X 0x%X)\n", driver1, driver2, driver3, driver4));
+
+	ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_TRACE,
+		("	(Platform, Interface) = (0x%X, 0x%X)\n", p_dm_odm->support_platform, p_dm_odm->support_interface));
+	ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_TRACE,
+		("	(Board, Package) = (0x%X, 0x%X)\n", p_dm_odm->board_type, p_dm_odm->package_type));
+
+
+	/*============== value Defined Check ===============*/
+	/*QFN type [15:12] and cut version [27:24] need to do value check*/
+
+	if (((cond1 & 0x0000F000) != 0) && ((cond1 & 0x0000F000) != (driver1 & 0x0000F000)))
+		return false;
+	if (((cond1 & 0x0F000000) != 0) && ((cond1 & 0x0F000000) != (driver1 & 0x0F000000)))
+		return false;
+
+	/*=============== Bit Defined Check ================*/
+	/* We don't care [31:28] */
+
+	cond1   &= 0x00FF0FFF;
+	driver1 &= 0x00FF0FFF;
+
+	if ((cond1 & driver1) == cond1) {
+		u32 bit_mask = 0;
+
+		if ((cond1 & 0x0F) == 0) /* board_type is DONTCARE*/
+			return true;
+
+		if ((cond1 & BIT(0)) != 0) /*GLNA*/
+			bit_mask |= 0x000000FF;
+		if ((cond1 & BIT(1)) != 0) /*GPA*/
+			bit_mask |= 0x0000FF00;
+		if ((cond1 & BIT(2)) != 0) /*ALNA*/
+			bit_mask |= 0x00FF0000;
+		if ((cond1 & BIT(3)) != 0) /*APA*/
+			bit_mask |= 0xFF000000;
+
+		if (((cond2 & bit_mask) == (driver2 & bit_mask)) && ((cond4 & bit_mask) == (driver4 & bit_mask)))  /* board_type of each RF path is matched*/
+			return true;
+		else
+			return false;
+	} else
+		return false;
+}
+static boolean
+check_negative(
+	struct PHY_DM_STRUCT     *p_dm_odm,
+	const u32  condition1,
+	const u32  condition2
+)
+{
+	return true;
+}
+
+/******************************************************************************
+*                           MAC_REG.TXT
+******************************************************************************/
+
+u32 array_tc_8821c_mac_reg[] = {
+	0x010, 0x00000043,
+	0x025, 0x0000001D,
+	0x026, 0x000000CE,
+	0x04F, 0x00000001,
+	0x420, 0x00000080,
+	0x421, 0x0000000F,
+	0x428, 0x0000000A,
+	0x429, 0x00000010,
+	0x430, 0x00000000,
+	0x431, 0x00000000,
+	0x432, 0x00000000,
+	0x433, 0x00000001,
+	0x434, 0x00000004,
+	0x435, 0x00000005,
+	0x436, 0x00000007,
+	0x437, 0x00000008,
+	0x43C, 0x00000004,
+	0x43D, 0x00000005,
+	0x43E, 0x00000007,
+	0x43F, 0x00000008,
+	0x440, 0x0000005D,
+	0x441, 0x00000001,
+	0x442, 0x00000000,
+	0x444, 0x00000010,
+	0x445, 0x000000F0,
+	0x446, 0x00000001,
+	0x447, 0x000000FE,
+	0x448, 0x00000000,
+	0x449, 0x00000000,
+	0x44A, 0x00000000,
+	0x44B, 0x00000040,
+	0x44C, 0x00000010,
+	0x44D, 0x000000F0,
+	0x44E, 0x0000003F,
+	0x44F, 0x00000000,
+	0x450, 0x00000000,
+	0x451, 0x00000000,
+	0x452, 0x00000000,
+	0x453, 0x00000040,
+	0x455, 0x00000070,
+	0x45E, 0x00000004,
+	0x49C, 0x00000010,
+	0x49D, 0x000000F0,
+	0x49E, 0x00000000,
+	0x49F, 0x00000006,
+	0x4A0, 0x000000E0,
+	0x4A1, 0x00000003,
+	0x4A2, 0x00000000,
+	0x4A3, 0x00000040,
+	0x4A4, 0x00000015,
+	0x4A5, 0x000000F0,
+	0x4A6, 0x00000000,
+	0x4A7, 0x00000006,
+	0x4A8, 0x000000E0,
+	0x4A9, 0x00000000,
+	0x4AA, 0x00000000,
+	0x4AB, 0x00000000,
+	0x7DA, 0x00000008,
+	0x1448, 0x00000006,
+	0x144A, 0x00000006,
+	0x144C, 0x00000006,
+	0x144E, 0x00000006,
+	0x4C8, 0x000000FF,
+	0x4C9, 0x00000008,
+	0x4CA, 0x0000002B,
+	0x4CB, 0x0000002B,
+	0x4CC, 0x000000FF,
+	0x4CD, 0x000000FF,
+	0x4CE, 0x00000001,
+	0x4CF, 0x00000008,
+	0x500, 0x00000026,
+	0x501, 0x000000A2,
+	0x502, 0x0000002F,
+	0x503, 0x00000000,
+	0x504, 0x00000028,
+	0x505, 0x000000A3,
+	0x506, 0x0000005E,
+	0x507, 0x00000000,
+	0x508, 0x0000002B,
+	0x509, 0x000000A4,
+	0x50A, 0x0000005E,
+	0x50B, 0x00000000,
+	0x50C, 0x0000004F,
+	0x50D, 0x000000A4,
+	0x50E, 0x00000000,
+	0x50F, 0x00000000,
+	0x512, 0x0000001C,
+	0x514, 0x0000000A,
+	0x516, 0x0000000A,
+	0x521, 0x0000002F,
+	0x525, 0x0000004F,
+	0x551, 0x00000010,
+	0x559, 0x00000002,
+	0x55C, 0x00000050,
+	0x55D, 0x000000FF,
+	0x577, 0x0000000B,
+	0x5BE, 0x00000064,
+	0x604, 0x00000001,
+	0x605, 0x00000030,
+	0x607, 0x00000001,
+	0x608, 0x0000000E,
+	0x609, 0x00000022,
+	0x60C, 0x00000018,
+	0x6A0, 0x000000FF,
+	0x6A1, 0x000000FF,
+	0x6A2, 0x000000FF,
+	0x6A3, 0x000000FF,
+	0x6A4, 0x000000FF,
+	0x6A5, 0x000000FF,
+	0x6DE, 0x00000084,
+	0x620, 0x000000FF,
+	0x621, 0x000000FF,
+	0x622, 0x000000FF,
+	0x623, 0x000000FF,
+	0x624, 0x000000FF,
+	0x625, 0x000000FF,
+	0x626, 0x000000FF,
+	0x627, 0x000000FF,
+	0x638, 0x00000050,
+	0x63C, 0x0000000A,
+	0x63D, 0x0000000A,
+	0x63E, 0x0000000E,
+	0x63F, 0x0000000E,
+	0x640, 0x00000040,
+	0x642, 0x00000040,
+	0x643, 0x00000000,
+	0x652, 0x000000C8,
+	0x66E, 0x00000005,
+	0x700, 0x00000021,
+	0x701, 0x00000043,
+	0x702, 0x00000065,
+	0x703, 0x00000087,
+	0x708, 0x00000021,
+	0x709, 0x00000043,
+	0x70A, 0x00000065,
+	0x70B, 0x00000087,
+	0x718, 0x00000040,
+	0x7D4, 0x00000010,
+
+};
+
+void
+odm_read_and_config_tc_8821c_mac_reg(
+	struct PHY_DM_STRUCT  *p_dm_odm
+)
+{
+	u32     i         = 0;
+	u8     c_cond;
+	boolean is_matched = true, is_skipped = false;
+	u32     array_len    = sizeof(array_tc_8821c_mac_reg) / sizeof(u32);
+	u32    *array       = array_tc_8821c_mac_reg;
+
+	u32	v1 = 0, v2 = 0, pre_v1 = 0, pre_v2 = 0;
+
+	ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> odm_read_and_config_tc_8821c_mac_reg\n"));
+
+	while ((i + 1) < array_len) {
+		v1 = array[i];
+		v2 = array[i + 1];
+
+		if (v1 & (BIT(31) | BIT30)) {/*positive & negative condition*/
+			if (v1 & BIT(31)) {/* positive condition*/
+				c_cond  = (u8)((v1 & (BIT(29) | BIT(28))) >> 28);
+				if (c_cond == COND_ENDIF) {/*end*/
+					is_matched = true;
+					is_skipped = false;
+					ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ENDIF\n"));
+				} else if (c_cond == COND_ELSE) { /*else*/
+					is_matched = is_skipped ? false : true;
+					ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ELSE\n"));
+				} else {/*if , else if*/
+					pre_v1 = v1;
+					pre_v2 = v2;
+					ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("IF or ELSE IF\n"));
+				}
+			} else if (v1 & BIT(30)) { /*negative condition*/
+				if (is_skipped == false) {
+					if (check_positive(p_dm_odm, pre_v1, pre_v2, v1, v2)) {
+						is_matched = true;
+						is_skipped = true;
+					} else {
+						is_matched = false;
+						is_skipped = false;
+					}
+				} else
+					is_matched = false;
+			}
+		} else {
+			if (is_matched)
+				odm_config_mac_8821c(p_dm_odm, v1, (u8)v2);
+		}
+		i = i + 2;
+	}
+}
+
+u32
+odm_get_version_tc_8821c_mac_reg(void)
+{
+	return 9;
+}
+
+#endif /* end of HWIMG_SUPPORT*/
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/rtl8821c/halhwimg8821c_testchip_mac.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/rtl8821c/halhwimg8821c_testchip_mac.h
--- linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/rtl8821c/halhwimg8821c_testchip_mac.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/rtl8821c/halhwimg8821c_testchip_mac.h	2020-04-10 16:35:06.834660908 +0300
@@ -0,0 +1,38 @@
+/******************************************************************************
+*
+* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
+*
+* This program is free software; you can redistribute it and/or modify it
+* under the terms of version 2 of the GNU General Public License as
+* published by the Free Software Foundation.
+*
+* This program is distributed in the hope that it will be useful, but WITHOUT
+* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+* more details.
+*
+* You should have received a copy of the GNU General Public License along with
+* this program; if not, write to the Free Software Foundation, Inc.,
+* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
+*
+*
+******************************************************************************/
+
+/*Image2HeaderVersion: 2.22*/
+#if (RTL8821C_SUPPORT == 1)
+#ifndef __INC_TC_MAC_HW_IMG_8821C_H
+#define __INC_TC_MAC_HW_IMG_8821C_H
+
+
+/******************************************************************************
+*                           MAC_REG.TXT
+******************************************************************************/
+
+void
+odm_read_and_config_tc_8821c_mac_reg(/* TC: Test Chip, MP: MP Chip*/
+	struct PHY_DM_STRUCT  *p_dm_odm
+);
+u32 odm_get_version_tc_8821c_mac_reg(void);
+
+#endif
+#endif /* end of HWIMG_SUPPORT*/
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/rtl8821c/halhwimg8821c_testchip_rf.c linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/rtl8821c/halhwimg8821c_testchip_rf.c
--- linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/rtl8821c/halhwimg8821c_testchip_rf.c	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/rtl8821c/halhwimg8821c_testchip_rf.c	2020-04-10 16:35:06.834660908 +0300
@@ -0,0 +1,2304 @@
+/******************************************************************************
+*
+* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
+*
+* This program is free software; you can redistribute it and/or modify it
+* under the terms of version 2 of the GNU General Public License as
+* published by the Free Software Foundation.
+*
+* This program is distributed in the hope that it will be useful, but WITHOUT
+* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+* more details.
+*
+* You should have received a copy of the GNU General Public License along with
+* this program; if not, write to the Free Software Foundation, Inc.,
+* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
+*
+*
+******************************************************************************/
+
+/*Image2HeaderVersion: 2.22*/
+#include "mp_precomp.h"
+#include "../phydm_precomp.h"
+
+#if (RTL8821C_SUPPORT == 1)
+static boolean
+check_positive(
+	struct PHY_DM_STRUCT     *p_dm_odm,
+	const u32  condition1,
+	const u32  condition2,
+	const u32  condition3,
+	const u32  condition4
+)
+{
+	u8    _board_type = ((p_dm_odm->board_type & BIT(4)) >> 4) << 0 | /* _GLNA*/
+		    ((p_dm_odm->board_type & BIT(3)) >> 3) << 1 | /* _GPA*/
+		    ((p_dm_odm->board_type & BIT(7)) >> 7) << 2 | /* _ALNA*/
+		    ((p_dm_odm->board_type & BIT(6)) >> 6) << 3 | /* _APA */
+		    ((p_dm_odm->board_type & BIT(2)) >> 2) << 4;  /* _BT*/
+
+	u32	cond1   = condition1, cond2 = condition2, cond3 = condition3, cond4 = condition4;
+	u32    driver1 = p_dm_odm->cut_version       << 24 |
+			 (p_dm_odm->support_interface & 0xF0) << 16 |
+			 p_dm_odm->support_platform  << 16 |
+			 p_dm_odm->package_type      << 12 |
+			 (p_dm_odm->support_interface & 0x0F) << 8  |
+			 _board_type;
+
+	u32    driver2 = (p_dm_odm->type_glna & 0xFF) <<  0 |
+			 (p_dm_odm->type_gpa & 0xFF)  <<  8 |
+			 (p_dm_odm->type_alna & 0xFF) << 16 |
+			 (p_dm_odm->type_apa & 0xFF)  << 24;
+
+	u32    driver3 = 0;
+
+	u32    driver4 = (p_dm_odm->type_glna & 0xFF00) >>  8 |
+			 (p_dm_odm->type_gpa & 0xFF00) |
+			 (p_dm_odm->type_alna & 0xFF00) << 8 |
+			 (p_dm_odm->type_apa & 0xFF00)  << 16;
+
+	ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_TRACE,
+		("===> check_positive (cond1, cond2, cond3, cond4) = (0x%X 0x%X 0x%X 0x%X)\n", cond1, cond2, cond3, cond4));
+	ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_TRACE,
+		("===> check_positive (driver1, driver2, driver3, driver4) = (0x%X 0x%X 0x%X 0x%X)\n", driver1, driver2, driver3, driver4));
+
+	ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_TRACE,
+		("	(Platform, Interface) = (0x%X, 0x%X)\n", p_dm_odm->support_platform, p_dm_odm->support_interface));
+	ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_TRACE,
+		("	(Board, Package) = (0x%X, 0x%X)\n", p_dm_odm->board_type, p_dm_odm->package_type));
+
+
+	/*============== value Defined Check ===============*/
+	/*QFN type [15:12] and cut version [27:24] need to do value check*/
+
+	if (((cond1 & 0x0000F000) != 0) && ((cond1 & 0x0000F000) != (driver1 & 0x0000F000)))
+		return false;
+	if (((cond1 & 0x0F000000) != 0) && ((cond1 & 0x0F000000) != (driver1 & 0x0F000000)))
+		return false;
+
+	/*=============== Bit Defined Check ================*/
+	/* We don't care [31:28] */
+
+	cond1   &= 0x00FF0FFF;
+	driver1 &= 0x00FF0FFF;
+
+	if ((cond1 & driver1) == cond1) {
+		u32 bit_mask = 0;
+
+		if ((cond1 & 0x0F) == 0) /* board_type is DONTCARE*/
+			return true;
+
+		if ((cond1 & BIT(0)) != 0) /*GLNA*/
+			bit_mask |= 0x000000FF;
+		if ((cond1 & BIT(1)) != 0) /*GPA*/
+			bit_mask |= 0x0000FF00;
+		if ((cond1 & BIT(2)) != 0) /*ALNA*/
+			bit_mask |= 0x00FF0000;
+		if ((cond1 & BIT(3)) != 0) /*APA*/
+			bit_mask |= 0xFF000000;
+
+		if (((cond2 & bit_mask) == (driver2 & bit_mask)) && ((cond4 & bit_mask) == (driver4 & bit_mask)))  /* board_type of each RF path is matched*/
+			return true;
+		else
+			return false;
+	} else
+		return false;
+}
+static boolean
+check_negative(
+	struct PHY_DM_STRUCT     *p_dm_odm,
+	const u32  condition1,
+	const u32  condition2
+)
+{
+	return true;
+}
+
+/******************************************************************************
+*                           RadioA.TXT
+******************************************************************************/
+
+u32 array_tc_8821c_radioa[] = {
+	0x80002000,	0x00000000,	0x40000000,	0x00000000,
+	0x000, 0x00030000,
+	0x018, 0x00010D24,
+	0xA0000000,	0x00000000,
+	0x000, 0x00030000,
+	0x018, 0x00010D24,
+	0xB0000000,	0x00000000,
+	0x80002000,	0x00000000,	0x40000000,	0x00000000,
+	0x0EF, 0x00080000,
+	0x033, 0x00000002,
+	0x03E, 0x0000003F,
+	0x03F, 0x000C0F4E,
+	0x033, 0x00000001,
+	0x03E, 0x00000034,
+	0x03F, 0x0004080E,
+	0xA0000000,	0x00000000,
+	0x0EF, 0x00080000,
+	0x033, 0x00000002,
+	0x03E, 0x0000003F,
+	0x03F, 0x000C0F4E,
+	0x033, 0x00000001,
+	0x03E, 0x00000034,
+	0x03F, 0x0004080E,
+	0xB0000000,	0x00000000,
+	0x80002000,	0x00000000,	0x40000000,	0x00000000,
+	0x0EF, 0x00080000,
+	0x033, 0x00000024,
+	0x03E, 0x0000003F,
+	0x03F, 0x000E0FDE,
+	0x0EF, 0x00000000,
+	0xA0000000,	0x00000000,
+	0x0EF, 0x00080000,
+	0x033, 0x00000024,
+	0x03E, 0x0000003F,
+	0x03F, 0x000E0FDE,
+	0x0EF, 0x00000000,
+	0xB0000000,	0x00000000,
+	0x80002000,	0x00000000,	0x40000000,	0x00000000,
+	0x0EF, 0x00080000,
+	0x033, 0x00000025,
+	0x03E, 0x00000037,
+	0x03F, 0x0007EFCE,
+	0x0EF, 0x00000000,
+	0xA0000000,	0x00000000,
+	0x0EF, 0x00080000,
+	0x033, 0x00000025,
+	0x03E, 0x00000037,
+	0x03F, 0x0007EFCE,
+	0x0EF, 0x00000000,
+	0xB0000000,	0x00000000,
+	0x80002000,	0x00000000,	0x40000000,	0x00000000,
+	0x0EF, 0x00080000,
+	0x033, 0x00000026,
+	0x03E, 0x00000037,
+	0x03F, 0x0005EFCE,
+	0x0EF, 0x00000000,
+	0xA0000000,	0x00000000,
+	0x0EF, 0x00080000,
+	0x033, 0x00000026,
+	0x03E, 0x00000037,
+	0x03F, 0x0005EFCE,
+	0x0EF, 0x00000000,
+	0xB0000000,	0x00000000,
+	0x80002000,	0x00000000,	0x40000000,	0x00000000,
+	0x0B0, 0x000FF0F8,
+	0x0B1, 0x0007DBE4,
+	0x0B2, 0x000225D1,
+	0x0B3, 0x000FC760,
+	0x0B4, 0x00099DD0,
+	0x0B5, 0x000400FC,
+	0x0B6, 0x000187F0,
+	0x0B7, 0x00030018,
+	0x0B8, 0x00080800,
+	0x0B9, 0x00000000,
+	0x0BA, 0x00008000,
+	0x0BB, 0x00000000,
+	0x0BC, 0x00040000,
+	0x0BD, 0x00000000,
+	0x0BE, 0x00000000,
+	0x0BF, 0x00000000,
+	0x0C0, 0x00000000,
+	0x0C1, 0x00000000,
+	0x0C2, 0x00000000,
+	0x0C3, 0x00000000,
+	0x0C4, 0x00002402,
+	0x0C5, 0x00000009,
+	0x0C6, 0x00040299,
+	0x0C7, 0x00055555,
+	0x0C8, 0x0000C16C,
+	0x0C9, 0x0001C140,
+	0x0CA, 0x00000000,
+	0x0CB, 0x00000000,
+	0x0CC, 0x00000000,
+	0x0CD, 0x00000000,
+	0x0CE, 0x00090C00,
+	0x0CF, 0x0006D200,
+	0x0DF, 0x00000009,
+	0xA0000000,	0x00000000,
+	0x0B0, 0x000FF0F8,
+	0x0B1, 0x0007DBE4,
+	0x0B2, 0x000225D1,
+	0x0B3, 0x000FC760,
+	0x0B4, 0x00099DD0,
+	0x0B5, 0x000400FC,
+	0x0B6, 0x000187F0,
+	0x0B7, 0x00030018,
+	0x0B8, 0x00080800,
+	0x0B9, 0x00000000,
+	0x0BA, 0x00008000,
+	0x0BB, 0x00000000,
+	0x0BC, 0x00040000,
+	0x0BD, 0x00000000,
+	0x0BE, 0x00000000,
+	0x0BF, 0x00000000,
+	0x0C0, 0x00000000,
+	0x0C1, 0x00000000,
+	0x0C2, 0x00000000,
+	0x0C3, 0x00000000,
+	0x0C4, 0x00002402,
+	0x0C5, 0x00000009,
+	0x0C6, 0x00040299,
+	0x0C7, 0x00055555,
+	0x0C8, 0x0000C16C,
+	0x0C9, 0x0001C140,
+	0x0CA, 0x00000000,
+	0x0CB, 0x00000000,
+	0x0CC, 0x00000000,
+	0x0CD, 0x00000000,
+	0x0CE, 0x00090C00,
+	0x0CF, 0x0006D200,
+	0x0DF, 0x00000009,
+	0xB0000000,	0x00000000,
+	0x80002000,	0x00000000,	0x40000000,	0x00000000,
+	0x018, 0x00010524,
+	0x089, 0x00000207,
+	0x08A, 0x000F5186,
+	0x08B, 0x00061830,
+	0x08C, 0x000112C7,
+	0x08D, 0x00060000,
+	0x08E, 0x00064540,
+	0xA0000000,	0x00000000,
+	0x018, 0x00010524,
+	0x089, 0x00000207,
+	0x08A, 0x000F5186,
+	0x08B, 0x00061830,
+	0x08C, 0x000112C7,
+	0x08D, 0x00060000,
+	0x08E, 0x00064540,
+	0xB0000000,	0x00000000,
+	0x80002000,	0x00000000,	0x40000000,	0x00000000,
+	0x0EF, 0x00020000,
+	0xA0000000,	0x00000000,
+	0x0EF, 0x00020000,
+	0xB0000000,	0x00000000,
+	0x80002000,	0x00000000,	0x40000000,	0x00000000,
+	0x033, 0x00000007,
+	0x03E, 0x0003C000,
+	0x03F, 0x000C3186,
+	0x033, 0x00000006,
+	0x03E, 0x0003C080,
+	0x03F, 0x000C3186,
+	0x033, 0x00000005,
+	0x03E, 0x0003C0C8,
+	0x03F, 0x000C3186,
+	0x033, 0x00000004,
+	0x03E, 0x0003C190,
+	0x03F, 0x000C3186,
+	0x033, 0x00000003,
+	0x03E, 0x0003C998,
+	0x03F, 0x000C3186,
+	0x033, 0x00000002,
+	0x03E, 0x0003D840,
+	0x03F, 0x000C3186,
+	0x033, 0x00000001,
+	0x03E, 0x0003D8C4,
+	0x03F, 0x000C3186,
+	0x033, 0x00000000,
+	0x03E, 0x0003D930,
+	0x03F, 0x000C3186,
+	0xA0000000,	0x00000000,
+	0x033, 0x00000007,
+	0x03E, 0x0003C000,
+	0x03F, 0x000C3186,
+	0x033, 0x00000006,
+	0x03E, 0x0003C080,
+	0x03F, 0x000C3186,
+	0x033, 0x00000005,
+	0x03E, 0x0003C0C8,
+	0x03F, 0x000C3186,
+	0x033, 0x00000004,
+	0x03E, 0x0003C190,
+	0x03F, 0x000C3186,
+	0x033, 0x00000003,
+	0x03E, 0x0003C998,
+	0x03F, 0x000C3186,
+	0x033, 0x00000002,
+	0x03E, 0x0003D840,
+	0x03F, 0x000C3186,
+	0x033, 0x00000001,
+	0x03E, 0x0003D8C4,
+	0x03F, 0x000C3186,
+	0x033, 0x00000000,
+	0x03E, 0x0003D930,
+	0x03F, 0x000C3186,
+	0xB0000000,	0x00000000,
+	0x80002000,	0x00000000,	0x40000000,	0x00000000,
+	0x033, 0x0000000F,
+	0x03E, 0x0003C000,
+	0x03F, 0x000C3186,
+	0x033, 0x0000000E,
+	0x03E, 0x0003C080,
+	0x03F, 0x000C3186,
+	0x033, 0x0000000D,
+	0x03E, 0x0003C0C8,
+	0x03F, 0x000C3186,
+	0x033, 0x0000000C,
+	0x03E, 0x0003C190,
+	0x03F, 0x000C3186,
+	0x033, 0x0000000B,
+	0x03E, 0x0003C998,
+	0x03F, 0x000C3186,
+	0x033, 0x0000000A,
+	0x03E, 0x0003D840,
+	0x03F, 0x000C3186,
+	0x033, 0x00000009,
+	0x03E, 0x0003D8C4,
+	0x03F, 0x000C3186,
+	0x033, 0x00000008,
+	0x03E, 0x0003D930,
+	0x03F, 0x000C3186,
+	0xA0000000,	0x00000000,
+	0x033, 0x0000000F,
+	0x03E, 0x0003C000,
+	0x03F, 0x000C3186,
+	0x033, 0x0000000E,
+	0x03E, 0x0003C080,
+	0x03F, 0x000C3186,
+	0x033, 0x0000000D,
+	0x03E, 0x0003C0C8,
+	0x03F, 0x000C3186,
+	0x033, 0x0000000C,
+	0x03E, 0x0003C190,
+	0x03F, 0x000C3186,
+	0x033, 0x0000000B,
+	0x03E, 0x0003C998,
+	0x03F, 0x000C3186,
+	0x033, 0x0000000A,
+	0x03E, 0x0003D840,
+	0x03F, 0x000C3186,
+	0x033, 0x00000009,
+	0x03E, 0x0003D8C4,
+	0x03F, 0x000C3186,
+	0x033, 0x00000008,
+	0x03E, 0x0003D930,
+	0x03F, 0x000C3186,
+	0xB0000000,	0x00000000,
+	0x80002000,	0x00000000,	0x40000000,	0x00000000,
+	0x033, 0x00000017,
+	0x03E, 0x0003C000,
+	0x03F, 0x000C3186,
+	0x033, 0x00000016,
+	0x03E, 0x0003C080,
+	0x03F, 0x000C3186,
+	0x033, 0x00000015,
+	0x03E, 0x0003C0C8,
+	0x03F, 0x000C3186,
+	0x033, 0x00000014,
+	0x03E, 0x0003C190,
+	0x03F, 0x000C3186,
+	0x033, 0x00000013,
+	0x03E, 0x0003C998,
+	0x03F, 0x000C3186,
+	0x033, 0x00000012,
+	0x03E, 0x0003D840,
+	0x03F, 0x000C3186,
+	0x033, 0x00000011,
+	0x03E, 0x0003D8C4,
+	0x03F, 0x000C3186,
+	0x033, 0x00000010,
+	0x03E, 0x0003D930,
+	0x03F, 0x000C3186,
+	0x0EF, 0x00000000,
+	0xA0000000,	0x00000000,
+	0x033, 0x00000017,
+	0x03E, 0x0003C000,
+	0x03F, 0x000C3186,
+	0x033, 0x00000016,
+	0x03E, 0x0003C080,
+	0x03F, 0x000C3186,
+	0x033, 0x00000015,
+	0x03E, 0x0003C0C8,
+	0x03F, 0x000C3186,
+	0x033, 0x00000014,
+	0x03E, 0x0003C190,
+	0x03F, 0x000C3186,
+	0x033, 0x00000013,
+	0x03E, 0x0003C998,
+	0x03F, 0x000C3186,
+	0x033, 0x00000012,
+	0x03E, 0x0003D840,
+	0x03F, 0x000C3186,
+	0x033, 0x00000011,
+	0x03E, 0x0003D8C4,
+	0x03F, 0x000C3186,
+	0x033, 0x00000010,
+	0x03E, 0x0003D930,
+	0x03F, 0x000C3186,
+	0x0EF, 0x00000000,
+	0xB0000000,	0x00000000,
+	0x80002000,	0x00000000,	0x40000000,	0x00000000,
+	0x0EF, 0x00004000,
+	0x033, 0x00000000,
+	0x03F, 0x00000005,
+	0x033, 0x00000001,
+	0x03F, 0x00000000,
+	0x033, 0x00000002,
+	0x03F, 0x00000000,
+	0x0EF, 0x00000000,
+	0xA0000000,	0x00000000,
+	0x0EF, 0x00004000,
+	0x033, 0x00000000,
+	0x03F, 0x00000005,
+	0x033, 0x00000001,
+	0x03F, 0x00000000,
+	0x033, 0x00000002,
+	0x03F, 0x00000000,
+	0x0EF, 0x00000000,
+	0xB0000000,	0x00000000,
+	0x80002000,	0x00000000,	0x40000000,	0x00000000,
+	0x018, 0x00000401,
+	0x084, 0x00001209,
+	0x086, 0x000001A0,
+	0x087, 0x000E8180,
+	0x088, 0x00040020,
+	0x0DF, 0x00008009,
+	0xA0000000,	0x00000000,
+	0x018, 0x00000401,
+	0x084, 0x00001209,
+	0x086, 0x000001A0,
+	0x087, 0x000E8180,
+	0x088, 0x00040020,
+	0x0DF, 0x00008009,
+	0xB0000000,	0x00000000,
+	0x80002000,	0x00000000,	0x40000000,	0x00000000,
+	0x0EF, 0x00008000,
+	0x033, 0x0000000F,
+	0x03F, 0x0000003C,
+	0x033, 0x0000000E,
+	0x03F, 0x00000038,
+	0x033, 0x0000000D,
+	0x03F, 0x00000030,
+	0x033, 0x0000000C,
+	0x03F, 0x00000028,
+	0x033, 0x0000000B,
+	0x03F, 0x00000020,
+	0x033, 0x0000000A,
+	0x03F, 0x00000018,
+	0x033, 0x00000009,
+	0x03F, 0x00000010,
+	0x033, 0x00000008,
+	0x03F, 0x00000008,
+	0x033, 0x00000007,
+	0x03F, 0x0000003C,
+	0x033, 0x00000006,
+	0x03F, 0x00000038,
+	0x033, 0x00000005,
+	0x03F, 0x00000030,
+	0x033, 0x00000004,
+	0x03F, 0x00000028,
+	0x033, 0x00000003,
+	0x03F, 0x00000020,
+	0x033, 0x00000002,
+	0x03F, 0x00000018,
+	0x033, 0x00000001,
+	0x03F, 0x00000010,
+	0x033, 0x00000000,
+	0x03F, 0x00000008,
+	0x0EF, 0x00000000,
+	0xA0000000,	0x00000000,
+	0x0EF, 0x00008000,
+	0x033, 0x0000000F,
+	0x03F, 0x0000003C,
+	0x033, 0x0000000E,
+	0x03F, 0x00000038,
+	0x033, 0x0000000D,
+	0x03F, 0x00000030,
+	0x033, 0x0000000C,
+	0x03F, 0x00000028,
+	0x033, 0x0000000B,
+	0x03F, 0x00000020,
+	0x033, 0x0000000A,
+	0x03F, 0x00000018,
+	0x033, 0x00000009,
+	0x03F, 0x00000010,
+	0x033, 0x00000008,
+	0x03F, 0x00000008,
+	0x033, 0x00000007,
+	0x03F, 0x0000003C,
+	0x033, 0x00000006,
+	0x03F, 0x00000038,
+	0x033, 0x00000005,
+	0x03F, 0x00000030,
+	0x033, 0x00000004,
+	0x03F, 0x00000028,
+	0x033, 0x00000003,
+	0x03F, 0x00000020,
+	0x033, 0x00000002,
+	0x03F, 0x00000018,
+	0x033, 0x00000001,
+	0x03F, 0x00000010,
+	0x033, 0x00000000,
+	0x03F, 0x00000008,
+	0x0EF, 0x00000000,
+	0xB0000000,	0x00000000,
+	0x80002000,	0x00000000,	0x40000000,	0x00000000,
+	0x0EE, 0x00000002,
+	0x033, 0x0000001E,
+	0x03F, 0x00000000,
+	0x033, 0x0000001C,
+	0x03F, 0x00000006,
+	0x033, 0x0000000E,
+	0x03F, 0x00000006,
+	0x033, 0x0000000C,
+	0x03F, 0x00000006,
+	0x033, 0x0000000A,
+	0x03F, 0x00000006,
+	0x033, 0x00000008,
+	0x03F, 0x00000006,
+	0x033, 0x00000036,
+	0x03F, 0x00000006,
+	0x033, 0x00000037,
+	0x03F, 0x00000006,
+	0x033, 0x00000034,
+	0x03F, 0x00000006,
+	0x033, 0x00000026,
+	0x03F, 0x00000006,
+	0x033, 0x00000027,
+	0x03F, 0x00000006,
+	0x033, 0x00000024,
+	0x03F, 0x00000006,
+	0x033, 0x00000022,
+	0x03F, 0x00000006,
+	0x033, 0x00000020,
+	0x03F, 0x00000006,
+	0x033, 0x00000006,
+	0x03F, 0x00000006,
+	0x033, 0x00000007,
+	0x03F, 0x00000006,
+	0x033, 0x00000004,
+	0x03F, 0x00000006,
+	0x033, 0x00000002,
+	0x03F, 0x00000006,
+	0x033, 0x00000000,
+	0x03F, 0x00000006,
+	0x0EE, 0x00000000,
+	0xA0000000,	0x00000000,
+	0x0EE, 0x00000002,
+	0x033, 0x0000001E,
+	0x03F, 0x00000000,
+	0x033, 0x0000001C,
+	0x03F, 0x00000006,
+	0x033, 0x0000000E,
+	0x03F, 0x00000006,
+	0x033, 0x0000000C,
+	0x03F, 0x00000006,
+	0x033, 0x0000000A,
+	0x03F, 0x00000006,
+	0x033, 0x00000008,
+	0x03F, 0x00000006,
+	0x033, 0x00000036,
+	0x03F, 0x00000006,
+	0x033, 0x00000037,
+	0x03F, 0x00000006,
+	0x033, 0x00000034,
+	0x03F, 0x00000006,
+	0x033, 0x00000026,
+	0x03F, 0x00000006,
+	0x033, 0x00000027,
+	0x03F, 0x00000006,
+	0x033, 0x00000024,
+	0x03F, 0x00000006,
+	0x033, 0x00000022,
+	0x03F, 0x00000006,
+	0x033, 0x00000020,
+	0x03F, 0x00000006,
+	0x033, 0x00000006,
+	0x03F, 0x00000006,
+	0x033, 0x00000007,
+	0x03F, 0x00000006,
+	0x033, 0x00000004,
+	0x03F, 0x00000006,
+	0x033, 0x00000002,
+	0x03F, 0x00000006,
+	0x033, 0x00000000,
+	0x03F, 0x00000006,
+	0x0EE, 0x00000000,
+	0xB0000000,	0x00000000,
+	0x80002000,	0x00000000,	0x40000000,	0x00000000,
+	0x0A0, 0x000F0005,
+	0x0A1, 0x0006C000,
+	0x0A2, 0x0000161B,
+	0x0A3, 0x000B9DBD,
+	0x0AF, 0x00070000,
+	0xA0000000,	0x00000000,
+	0x0A0, 0x000F0005,
+	0x0A1, 0x0006C000,
+	0x0A2, 0x0000161B,
+	0x0A3, 0x000B9DBD,
+	0x0AF, 0x00070000,
+	0xB0000000,	0x00000000,
+	0x80002000,	0x00000000,	0x40000000,	0x00000000,
+	0x0B8, 0x00080A00,
+	0x0B0, 0x000FF0FA,
+	0x0CA, 0x00080000,
+	0x0C9, 0x0001C141,
+	0x0B0, 0x000FF0F8,
+	0xA0000000,	0x00000000,
+	0x0B8, 0x00080A00,
+	0x0B0, 0x000FF0FA,
+	0x0CA, 0x00080000,
+	0x0C9, 0x0001C141,
+	0x0B0, 0x000FF0F8,
+	0xB0000000,	0x00000000,
+	0x80002000,	0x00000000,	0x40000000,	0x00000000,
+	0x018, 0x00018D24,
+	0xA0000000,	0x00000000,
+	0x018, 0x00018D24,
+	0xB0000000,	0x00000000,
+	0xFFE, 0x00000000,
+	0xFFE, 0x00000000,
+	0xFFE, 0x00000000,
+	0xFFE, 0x00000000,
+	0x80002000,	0x00000000,	0x40000000,	0x00000000,
+	0x018, 0x00010D24,
+	0xA0000000,	0x00000000,
+	0x018, 0x00010D24,
+	0xB0000000,	0x00000000,
+	0x80002000,	0x00000000,	0x40000000,	0x00000000,
+	0x01B, 0x00003A40,
+	0xA0000000,	0x00000000,
+	0x01B, 0x00003A40,
+	0xB0000000,	0x00000000,
+	0x80002000,	0x00000000,	0x40000000,	0x00000000,
+	0x061, 0x0004D301,
+	0x062, 0x0000D303,
+	0x063, 0x00000002,
+	0xA0000000,	0x00000000,
+	0x061, 0x0004D301,
+	0x062, 0x0000D303,
+	0x063, 0x00000002,
+	0xB0000000,	0x00000000,
+	0x80002000,	0x00000000,	0x40000000,	0x00000000,
+	0x0EF, 0x00000200,
+	0x030, 0x000004F1,
+	0x030, 0x000014F1,
+	0x030, 0x000024F1,
+	0x030, 0x000034F1,
+	0x030, 0x000044F1,
+	0x030, 0x000054F1,
+	0x030, 0x000064F1,
+	0x030, 0x000074F1,
+	0x030, 0x000084F1,
+	0x030, 0x000094F1,
+	0x030, 0x0000A4F1,
+	0x030, 0x0000B4F1,
+	0x0EF, 0x00000000,
+	0xA0000000,	0x00000000,
+	0x0EF, 0x00000200,
+	0x030, 0x00000491,
+	0x030, 0x00001491,
+	0x030, 0x00002491,
+	0x030, 0x00003491,
+	0x030, 0x00004492,
+	0x030, 0x00005492,
+	0x030, 0x00006492,
+	0x030, 0x00007492,
+	0x030, 0x00008592,
+	0x030, 0x00009592,
+	0x030, 0x0000A592,
+	0x030, 0x0000B592,
+	0x0EF, 0x00000000,
+	0xB0000000,	0x00000000,
+	0x80002000,	0x00000000,	0x40000000,	0x00000000,
+	0x0EF, 0x00000080,
+	0x030, 0x00000301,
+	0x030, 0x00001301,
+	0x030, 0x00002301,
+	0x030, 0x00003301,
+	0x030, 0x00004301,
+	0x030, 0x00005301,
+	0x030, 0x00006301,
+	0x030, 0x00007301,
+	0x030, 0x00008301,
+	0x030, 0x00009301,
+	0x030, 0x0000A301,
+	0x030, 0x0000B301,
+	0x0EF, 0x00000000,
+	0xA0000000,	0x00000000,
+	0x0EF, 0x00000080,
+	0x030, 0x00000401,
+	0x030, 0x00001401,
+	0x030, 0x00002401,
+	0x030, 0x00003401,
+	0x030, 0x00004403,
+	0x030, 0x00005403,
+	0x030, 0x00006403,
+	0x030, 0x00007403,
+	0x030, 0x00008402,
+	0x030, 0x00009402,
+	0x030, 0x0000A402,
+	0x030, 0x0000B402,
+	0x0EF, 0x00000000,
+	0xB0000000,	0x00000000,
+	0x80002000,	0x00000000,	0x40000000,	0x00000000,
+	0x0EF, 0x00000040,
+	0x030, 0x00000770,
+	0x030, 0x00001670,
+	0x030, 0x00002120,
+	0x030, 0x00004000,
+	0x030, 0x00005000,
+	0x030, 0x00006000,
+	0x0EF, 0x00000000,
+	0xA0000000,	0x00000000,
+	0x0EF, 0x00000040,
+	0x030, 0x00000773,
+	0x030, 0x00001543,
+	0x030, 0x00002330,
+	0x030, 0x00004000,
+	0x030, 0x00005000,
+	0x030, 0x00006000,
+	0x0EF, 0x00000000,
+	0xB0000000,	0x00000000,
+	0x80002000,	0x00000000,	0x40000000,	0x00000000,
+	0x0EF, 0x00000800,
+	0x0DE, 0x00020200,
+	0x05C, 0x00007FE0,
+	0xA0000000,	0x00000000,
+	0x0EF, 0x00000800,
+	0x0DE, 0x00020200,
+	0x05C, 0x00007FE0,
+	0xB0000000,	0x00000000,
+	0x80002000,	0x00000000,	0x40000000,	0x00000000,
+	0x033, 0x00000020,
+	0x03F, 0x00000E08,
+	0x033, 0x00000021,
+	0x03F, 0x00000E0B,
+	0x033, 0x00000022,
+	0x03F, 0x00000E0E,
+	0x033, 0x00000023,
+	0x03F, 0x00000E2B,
+	0x033, 0x00000024,
+	0x03F, 0x00000E2E,
+	0x033, 0x00000025,
+	0x03F, 0x00000E6B,
+	0x033, 0x00000026,
+	0x03F, 0x00000EE9,
+	0x033, 0x00000027,
+	0x03F, 0x00000EEC,
+	0x033, 0x00000028,
+	0x03F, 0x00000EEF,
+	0x033, 0x00000029,
+	0x03F, 0x00000EF2,
+	0x033, 0x0000002A,
+	0x03F, 0x00000EF5,
+	0xA0000000,	0x00000000,
+	0x033, 0x00000020,
+	0x03F, 0x00000E08,
+	0x033, 0x00000021,
+	0x03F, 0x00000E0B,
+	0x033, 0x00000022,
+	0x03F, 0x00000E0E,
+	0x033, 0x00000023,
+	0x03F, 0x00000E2B,
+	0x033, 0x00000024,
+	0x03F, 0x00000E2E,
+	0x033, 0x00000025,
+	0x03F, 0x00000E6B,
+	0x033, 0x00000026,
+	0x03F, 0x00000EE8,
+	0x033, 0x00000027,
+	0x03F, 0x00000EEB,
+	0x033, 0x00000028,
+	0x03F, 0x00000EEE,
+	0x033, 0x00000029,
+	0x03F, 0x00000EF1,
+	0x033, 0x0000002A,
+	0x03F, 0x00000EF4,
+	0xB0000000,	0x00000000,
+	0x80002000,	0x00000000,	0x40000000,	0x00000000,
+	0x033, 0x00000060,
+	0x03F, 0x00000E09,
+	0x033, 0x00000061,
+	0x03F, 0x00000E0C,
+	0x033, 0x00000062,
+	0x03F, 0x00000E0F,
+	0x033, 0x00000063,
+	0x03F, 0x00000E2C,
+	0x033, 0x00000064,
+	0x03F, 0x00000E2F,
+	0x033, 0x00000065,
+	0x03F, 0x00000E6B,
+	0x033, 0x00000066,
+	0x03F, 0x00000EE6,
+	0x033, 0x00000067,
+	0x03F, 0x00000EE9,
+	0x033, 0x00000068,
+	0x03F, 0x00000EEC,
+	0x033, 0x00000069,
+	0x03F, 0x00000EF0,
+	0x033, 0x0000006A,
+	0x03F, 0x00000EF3,
+	0xA0000000,	0x00000000,
+	0x033, 0x00000060,
+	0x03F, 0x00000E08,
+	0x033, 0x00000061,
+	0x03F, 0x00000E0B,
+	0x033, 0x00000062,
+	0x03F, 0x00000E0E,
+	0x033, 0x00000063,
+	0x03F, 0x00000E2B,
+	0x033, 0x00000064,
+	0x03F, 0x00000E2E,
+	0x033, 0x00000065,
+	0x03F, 0x00000E6B,
+	0x033, 0x00000066,
+	0x03F, 0x00000EE7,
+	0x033, 0x00000067,
+	0x03F, 0x00000EEA,
+	0x033, 0x00000068,
+	0x03F, 0x00000EED,
+	0x033, 0x00000069,
+	0x03F, 0x00000EF0,
+	0x033, 0x0000006A,
+	0x03F, 0x00000EF3,
+	0xB0000000,	0x00000000,
+	0x80002000,	0x00000000,	0x40000000,	0x00000000,
+	0x033, 0x000000A0,
+	0x03F, 0x00000E09,
+	0x033, 0x000000A1,
+	0x03F, 0x00000E0C,
+	0x033, 0x000000A2,
+	0x03F, 0x00000E0F,
+	0x033, 0x000000A3,
+	0x03F, 0x00000E2C,
+	0x033, 0x000000A4,
+	0x03F, 0x00000E2F,
+	0x033, 0x000000A5,
+	0x03F, 0x00000E6C,
+	0x033, 0x000000A6,
+	0x03F, 0x00000EE9,
+	0x033, 0x000000A7,
+	0x03F, 0x00000EEC,
+	0x033, 0x000000A8,
+	0x03F, 0x00000EEF,
+	0x033, 0x000000A9,
+	0x03F, 0x00000EF2,
+	0x033, 0x000000AA,
+	0x03F, 0x00000EF5,
+	0x0EF, 0x00000000,
+	0xA0000000,	0x00000000,
+	0x033, 0x000000A0,
+	0x03F, 0x00000E09,
+	0x033, 0x000000A1,
+	0x03F, 0x00000E0C,
+	0x033, 0x000000A2,
+	0x03F, 0x00000E0F,
+	0x033, 0x000000A3,
+	0x03F, 0x00000E2C,
+	0x033, 0x000000A4,
+	0x03F, 0x00000E2F,
+	0x033, 0x000000A5,
+	0x03F, 0x00000E6C,
+	0x033, 0x000000A6,
+	0x03F, 0x00000EE9,
+	0x033, 0x000000A7,
+	0x03F, 0x00000EEC,
+	0x033, 0x000000A8,
+	0x03F, 0x00000EEF,
+	0x033, 0x000000A9,
+	0x03F, 0x00000EF2,
+	0x033, 0x000000AA,
+	0x03F, 0x00000EF5,
+	0x0EF, 0x00000000,
+	0xB0000000,	0x00000000,
+	0x80002000,	0x00000000,	0x40000000,	0x00000000,
+	0x0EF, 0x00000400,
+	0x033, 0x00000000,
+	0x03F, 0x0000267C,
+	0x033, 0x00000001,
+	0x03F, 0x0000267C,
+	0x033, 0x00000002,
+	0x03F, 0x0000267C,
+	0x033, 0x00000003,
+	0x03F, 0x0000267C,
+	0x0EF, 0x00000000,
+	0xA0000000,	0x00000000,
+	0x0EF, 0x00000400,
+	0x033, 0x00000000,
+	0x03F, 0x0000267C,
+	0x033, 0x00000001,
+	0x03F, 0x0000267C,
+	0x033, 0x00000002,
+	0x03F, 0x0000267C,
+	0x033, 0x00000003,
+	0x03F, 0x0000267C,
+	0x0EF, 0x00000000,
+	0xB0000000,	0x00000000,
+	0x80002000,	0x00000000,	0x40000000,	0x00000000,
+	0x0EF, 0x00000100,
+	0x033, 0x00000000,
+	0x03F, 0x00000ED0,
+	0x033, 0x00000001,
+	0x03F, 0x00000ED0,
+	0x033, 0x00000002,
+	0x03F, 0x00000ED0,
+	0x033, 0x00000003,
+	0x03F, 0x00000ED0,
+	0x0EF, 0x00000000,
+	0xA0000000,	0x00000000,
+	0x0EF, 0x00000100,
+	0x033, 0x00000000,
+	0x03F, 0x00000ED0,
+	0x033, 0x00000001,
+	0x03F, 0x00000ED0,
+	0x033, 0x00000002,
+	0x03F, 0x00000ED0,
+	0x033, 0x00000003,
+	0x03F, 0x00000ED0,
+	0x0EF, 0x00000000,
+	0xB0000000,	0x00000000,
+	0x80002000,	0x00000000,	0x40000000,	0x00000000,
+	0x051, 0x00000818,
+	0x052, 0x0009E063,
+	0x053, 0x00000DA1,
+	0x054, 0x00070022,
+	0x055, 0x00082000,
+	0x056, 0x00051CCC,
+	0x057, 0x0000CE16,
+	0x058, 0x00072C10,
+	0x059, 0x000A0000,
+	0xA0000000,	0x00000000,
+	0x051, 0x00000818,
+	0x052, 0x0009E063,
+	0x053, 0x00000DA1,
+	0x054, 0x00070022,
+	0x055, 0x00082000,
+	0x056, 0x00051CCC,
+	0x057, 0x0000CE16,
+	0x058, 0x00072C10,
+	0x059, 0x000A0000,
+	0xB0000000,	0x00000000,
+	0x80002000,	0x00000000,	0x40000000,	0x00000000,
+	0x0EF, 0x00000800,
+	0x0DE, 0x00020200,
+	0x05C, 0x00007FE0,
+	0x033, 0x00000000,
+	0x03F, 0x00051427,
+	0x033, 0x00000001,
+	0x03F, 0x00051446,
+	0x033, 0x00000002,
+	0x03F, 0x00051449,
+	0x033, 0x00000003,
+	0x03F, 0x0005144C,
+	0x033, 0x00000004,
+	0x03F, 0x00051C69,
+	0x033, 0x00000005,
+	0x03F, 0x00051C6C,
+	0x033, 0x00000006,
+	0x03F, 0x00051C8D,
+	0x033, 0x00000007,
+	0x03F, 0x00051CEB,
+	0x033, 0x00000008,
+	0x03F, 0x00051CEE,
+	0x033, 0x00000009,
+	0x03F, 0x00051CF1,
+	0x033, 0x0000000A,
+	0x03F, 0x00051CF4,
+	0x0EF, 0x00000000,
+	0xA0000000,	0x00000000,
+	0x0EF, 0x00000800,
+	0x0DE, 0x00020200,
+	0x05C, 0x00007FE0,
+	0x033, 0x00000000,
+	0x03F, 0x00051427,
+	0x033, 0x00000001,
+	0x03F, 0x00051446,
+	0x033, 0x00000002,
+	0x03F, 0x00051449,
+	0x033, 0x00000003,
+	0x03F, 0x0005144C,
+	0x033, 0x00000004,
+	0x03F, 0x00051C69,
+	0x033, 0x00000005,
+	0x03F, 0x00051C6C,
+	0x033, 0x00000006,
+	0x03F, 0x00051C8D,
+	0x033, 0x00000007,
+	0x03F, 0x00051CEB,
+	0x033, 0x00000008,
+	0x03F, 0x00051CEE,
+	0x033, 0x00000009,
+	0x03F, 0x00051CF1,
+	0x033, 0x0000000A,
+	0x03F, 0x00051CF4,
+	0x0EF, 0x00000000,
+	0xB0000000,	0x00000000,
+	0x80002000,	0x00000000,	0x40000000,	0x00000000,
+	0x0EE, 0x00004000,
+	0x033, 0x00000000,
+	0x03F, 0x0000209D,
+	0x033, 0x00000001,
+	0x03F, 0x0000209D,
+	0x033, 0x00000002,
+	0x03F, 0x0000209D,
+	0x033, 0x00000003,
+	0x03F, 0x0000209D,
+	0x0EE, 0x00000000,
+	0xA0000000,	0x00000000,
+	0x0EE, 0x00004000,
+	0x033, 0x00000000,
+	0x03F, 0x0000209D,
+	0x033, 0x00000001,
+	0x03F, 0x0000209D,
+	0x033, 0x00000002,
+	0x03F, 0x0000209D,
+	0x033, 0x00000003,
+	0x03F, 0x0000209D,
+	0x0EE, 0x00000000,
+	0xB0000000,	0x00000000,
+	0x80002000,	0x00000000,	0x40000000,	0x00000000,
+	0x0EE, 0x00002000,
+	0x033, 0x00000000,
+	0x03F, 0x00000840,
+	0x033, 0x00000001,
+	0x03F, 0x00000840,
+	0x033, 0x00000002,
+	0x03F, 0x00000840,
+	0x033, 0x00000003,
+	0x03F, 0x00000840,
+	0x0EE, 0x00000000,
+	0xA0000000,	0x00000000,
+	0x0EE, 0x00002000,
+	0x033, 0x00000000,
+	0x03F, 0x00000840,
+	0x033, 0x00000001,
+	0x03F, 0x00000840,
+	0x033, 0x00000002,
+	0x03F, 0x00000840,
+	0x033, 0x00000003,
+	0x03F, 0x00000840,
+	0x0EE, 0x00000000,
+	0xB0000000,	0x00000000,
+	0x80002000,	0x00000000,	0x40000000,	0x00000000,
+	0x070, 0x00008000,
+	0x075, 0x00002645,
+	0x076, 0x0000E984,
+	0x077, 0x00004408,
+	0x078, 0x0003F000,
+	0x07D, 0x00007600,
+	0x07F, 0x00000000,
+	0x06A, 0x000FCC00,
+	0xA0000000,	0x00000000,
+	0x070, 0x00008000,
+	0x075, 0x00002645,
+	0x076, 0x0000E984,
+	0x077, 0x00004408,
+	0x078, 0x0003F000,
+	0x07D, 0x00007600,
+	0x07F, 0x00000000,
+	0x06A, 0x000FCC00,
+	0xB0000000,	0x00000000,
+	0x80002000,	0x00000000,	0x40000000,	0x00000000,
+	0x0EE, 0x00008000,
+	0x033, 0x00000000,
+	0x03F, 0x00051427,
+	0x033, 0x00000001,
+	0x03F, 0x00051446,
+	0x033, 0x00000002,
+	0x03F, 0x00051449,
+	0x033, 0x00000003,
+	0x03F, 0x0005144C,
+	0x033, 0x00000004,
+	0x03F, 0x00051C69,
+	0x033, 0x00000005,
+	0x03F, 0x00051C6C,
+	0x033, 0x00000006,
+	0x03F, 0x00051C8D,
+	0x033, 0x00000007,
+	0x03F, 0x00051CEB,
+	0x033, 0x00000008,
+	0x03F, 0x00051CEE,
+	0x033, 0x00000009,
+	0x03F, 0x00051CF1,
+	0x033, 0x0000000A,
+	0x03F, 0x00051CF4,
+	0x0EE, 0x00000000,
+	0xA0000000,	0x00000000,
+	0x0EE, 0x00008000,
+	0x033, 0x00000000,
+	0x03F, 0x00051427,
+	0x033, 0x00000001,
+	0x03F, 0x00051446,
+	0x033, 0x00000002,
+	0x03F, 0x00051449,
+	0x033, 0x00000003,
+	0x03F, 0x0005144C,
+	0x033, 0x00000004,
+	0x03F, 0x00051C69,
+	0x033, 0x00000005,
+	0x03F, 0x00051C6C,
+	0x033, 0x00000006,
+	0x03F, 0x00051C8D,
+	0x033, 0x00000007,
+	0x03F, 0x00051CEB,
+	0x033, 0x00000008,
+	0x03F, 0x00051CEE,
+	0x033, 0x00000009,
+	0x03F, 0x00051CF1,
+	0x033, 0x0000000A,
+	0x03F, 0x00051CF4,
+	0x0EE, 0x00000000,
+	0xB0000000,	0x00000000,
+	0x80002000,	0x00000000,	0x40000000,	0x00000000,
+	0x0EF, 0x00000010,
+	0x033, 0x00000000,
+	0x008, 0x0009C060,
+	0x033, 0x00000001,
+	0x008, 0x0009C060,
+	0x0EF, 0x00000000,
+	0xA0000000,	0x00000000,
+	0x0EF, 0x00000010,
+	0x033, 0x00000000,
+	0x008, 0x0009C060,
+	0x033, 0x00000001,
+	0x008, 0x0009C060,
+	0x0EF, 0x00000000,
+	0xB0000000,	0x00000000,
+	0x80002000,	0x00000000,	0x40000000,	0x00000000,
+	0x033, 0x000000A2,
+	0x0EF, 0x00080000,
+	0x03E, 0x0000593F,
+	0x03F, 0x000C0F4F,
+	0x0EF, 0x00000000,
+	0xA0000000,	0x00000000,
+	0x033, 0x000000A2,
+	0x0EF, 0x00080000,
+	0x03E, 0x0000593F,
+	0x03F, 0x000C0F4F,
+	0x0EF, 0x00000000,
+	0xB0000000,	0x00000000,
+	0x80002000,	0x00000000,	0x40000000,	0x00000000,
+	0x033, 0x000000A3,
+	0x0EF, 0x00080000,
+	0x03E, 0x00005934,
+	0x03F, 0x0005AFCF,
+	0x0EF, 0x00000000,
+	0xA0000000,	0x00000000,
+	0x033, 0x000000A3,
+	0x0EF, 0x00080000,
+	0x03E, 0x00005934,
+	0x03F, 0x0005AFCF,
+	0x0EF, 0x00000000,
+	0xB0000000,	0x00000000,
+
+};
+
+void
+odm_read_and_config_tc_8821c_radioa(
+	struct PHY_DM_STRUCT  *p_dm_odm
+)
+{
+	u32     i         = 0;
+	u8     c_cond;
+	boolean is_matched = true, is_skipped = false;
+	u32     array_len    = sizeof(array_tc_8821c_radioa) / sizeof(u32);
+	u32    *array       = array_tc_8821c_radioa;
+
+	u32	v1 = 0, v2 = 0, pre_v1 = 0, pre_v2 = 0;
+
+	ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> odm_read_and_config_tc_8821c_radioa\n"));
+
+	while ((i + 1) < array_len) {
+		v1 = array[i];
+		v2 = array[i + 1];
+
+		if (v1 & (BIT(31) | BIT30)) {/*positive & negative condition*/
+			if (v1 & BIT(31)) {/* positive condition*/
+				c_cond  = (u8)((v1 & (BIT(29) | BIT(28))) >> 28);
+				if (c_cond == COND_ENDIF) {/*end*/
+					is_matched = true;
+					is_skipped = false;
+					ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ENDIF\n"));
+				} else if (c_cond == COND_ELSE) { /*else*/
+					is_matched = is_skipped ? false : true;
+					ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ELSE\n"));
+				} else {/*if , else if*/
+					pre_v1 = v1;
+					pre_v2 = v2;
+					ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("IF or ELSE IF\n"));
+				}
+			} else if (v1 & BIT(30)) { /*negative condition*/
+				if (is_skipped == false) {
+					if (check_positive(p_dm_odm, pre_v1, pre_v2, v1, v2)) {
+						is_matched = true;
+						is_skipped = true;
+					} else {
+						is_matched = false;
+						is_skipped = false;
+					}
+				} else
+					is_matched = false;
+			}
+		} else {
+			if (is_matched)
+				odm_config_rf_radio_a_8821c(p_dm_odm, v1, v2);
+		}
+		i = i + 2;
+	}
+}
+
+u32
+odm_get_version_tc_8821c_radioa(void)
+{
+	return 9;
+}
+
+/******************************************************************************
+*                           TxPowerTrack.TXT
+******************************************************************************/
+
+u8 g_delta_swing_table_idx_tc_5ga_n_txpowertrack_8821c[][DELTA_SWINGIDX_SIZE] = {
+	{0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 11, 11, 11, 11, 12, 12, 13, 13, 14},
+	{0, 1, 1, 2, 3, 4, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 11, 12, 13, 14, 14, 15, 16, 16, 17, 18, 19, 19, 20, 21},
+	{0, 1, 1, 2, 3, 3, 4, 5, 5, 6, 6, 7, 8, 8, 9, 10, 10, 11, 12, 12, 13, 14, 14, 15, 16, 16, 17, 17, 18, 19},
+};
+u8 g_delta_swing_table_idx_tc_5ga_p_txpowertrack_8821c[][DELTA_SWINGIDX_SIZE] = {
+	{0, 1, 2, 2, 3, 4, 5, 6, 7, 7, 8, 9, 10, 11, 12, 12, 13, 14, 15, 16, 16, 17, 18, 19, 20, 21, 21, 22, 23, 24},
+	{0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 23, 24, 25, 25, 25, 25},
+	{0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 17, 18, 19, 20, 21, 22, 23, 24, 25, 25, 25, 25},
+};
+u8 g_delta_swing_table_idx_tc_2ga_n_txpowertrack_8821c[]    = {0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 4, 5, 5, 6, 6, 7, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 11, 12, 12, 13};
+u8 g_delta_swing_table_idx_tc_2ga_p_txpowertrack_8821c[]    = {0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14};
+u8 g_delta_swing_table_idx_tc_2g_cck_a_n_txpowertrack_8821c[] = {0, 0, 1, 1, 2, 2, 3, 3, 3, 4, 4, 5, 5, 5, 6, 6, 7, 7, 8, 8, 8, 9, 9, 10, 10, 11, 11, 11, 12, 12};
+u8 g_delta_swing_table_idx_tc_2g_cck_a_p_txpowertrack_8821c[] = {0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14};
+
+void
+odm_read_and_config_tc_8821c_txpowertrack(
+	struct PHY_DM_STRUCT  *p_dm_odm
+)
+{
+	struct odm_rf_calibration_structure  *p_rf_calibrate_info = &(p_dm_odm->rf_calibrate_info);
+
+	ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_TC_8821C\n"));
+
+
+	odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_2ga_p, g_delta_swing_table_idx_tc_2ga_p_txpowertrack_8821c, DELTA_SWINGIDX_SIZE);
+	odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_2ga_n, g_delta_swing_table_idx_tc_2ga_n_txpowertrack_8821c, DELTA_SWINGIDX_SIZE);
+
+	odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_2g_cck_a_p, g_delta_swing_table_idx_tc_2g_cck_a_p_txpowertrack_8821c, DELTA_SWINGIDX_SIZE);
+	odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_2g_cck_a_n, g_delta_swing_table_idx_tc_2g_cck_a_n_txpowertrack_8821c, DELTA_SWINGIDX_SIZE);
+
+	odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_5ga_p, g_delta_swing_table_idx_tc_5ga_p_txpowertrack_8821c, DELTA_SWINGIDX_SIZE * 3);
+	odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_5ga_n, g_delta_swing_table_idx_tc_5ga_n_txpowertrack_8821c, DELTA_SWINGIDX_SIZE * 3);
+}
+
+/******************************************************************************
+*                           TXPWR_LMT.TXT
+******************************************************************************/
+
+const char *array_tc_8821c_txpwr_lmt[] = {
+	"FCC", "2.4G", "20M", "CCK", "1T", "01", "36",
+	"ETSI", "2.4G", "20M", "CCK", "1T", "01", "32",
+	"MKK", "2.4G", "20M", "CCK", "1T", "01", "32",
+	"FCC", "2.4G", "20M", "CCK", "1T", "02", "36",
+	"ETSI", "2.4G", "20M", "CCK", "1T", "02", "32",
+	"MKK", "2.4G", "20M", "CCK", "1T", "02", "32",
+	"FCC", "2.4G", "20M", "CCK", "1T", "03", "36",
+	"ETSI", "2.4G", "20M", "CCK", "1T", "03", "32",
+	"MKK", "2.4G", "20M", "CCK", "1T", "03", "32",
+	"FCC", "2.4G", "20M", "CCK", "1T", "04", "36",
+	"ETSI", "2.4G", "20M", "CCK", "1T", "04", "32",
+	"MKK", "2.4G", "20M", "CCK", "1T", "04", "32",
+	"FCC", "2.4G", "20M", "CCK", "1T", "05", "36",
+	"ETSI", "2.4G", "20M", "CCK", "1T", "05", "32",
+	"MKK", "2.4G", "20M", "CCK", "1T", "05", "32",
+	"FCC", "2.4G", "20M", "CCK", "1T", "06", "36",
+	"ETSI", "2.4G", "20M", "CCK", "1T", "06", "32",
+	"MKK", "2.4G", "20M", "CCK", "1T", "06", "32",
+	"FCC", "2.4G", "20M", "CCK", "1T", "07", "36",
+	"ETSI", "2.4G", "20M", "CCK", "1T", "07", "32",
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+	"MKK", "5G", "20M", "HT", "1T", "140", "32",
+	"FCC", "5G", "20M", "HT", "1T", "149", "36",
+	"ETSI", "5G", "20M", "HT", "1T", "149", "32",
+	"MKK", "5G", "20M", "HT", "1T", "149", "63",
+	"FCC", "5G", "20M", "HT", "1T", "153", "36",
+	"ETSI", "5G", "20M", "HT", "1T", "153", "32",
+	"MKK", "5G", "20M", "HT", "1T", "153", "63",
+	"FCC", "5G", "20M", "HT", "1T", "157", "36",
+	"ETSI", "5G", "20M", "HT", "1T", "157", "32",
+	"MKK", "5G", "20M", "HT", "1T", "157", "63",
+	"FCC", "5G", "20M", "HT", "1T", "161", "36",
+	"ETSI", "5G", "20M", "HT", "1T", "161", "32",
+	"MKK", "5G", "20M", "HT", "1T", "161", "63",
+	"FCC", "5G", "20M", "HT", "1T", "165", "36",
+	"ETSI", "5G", "20M", "HT", "1T", "165", "32",
+	"MKK", "5G", "20M", "HT", "1T", "165", "63",
+	"FCC", "5G", "20M", "HT", "2T", "36", "28",
+	"ETSI", "5G", "20M", "HT", "2T", "36", "30",
+	"MKK", "5G", "20M", "HT", "2T", "36", "30",
+	"FCC", "5G", "20M", "HT", "2T", "40", "28",
+	"ETSI", "5G", "20M", "HT", "2T", "40", "30",
+	"MKK", "5G", "20M", "HT", "2T", "40", "30",
+	"FCC", "5G", "20M", "HT", "2T", "44", "28",
+	"ETSI", "5G", "20M", "HT", "2T", "44", "30",
+	"MKK", "5G", "20M", "HT", "2T", "44", "30",
+	"FCC", "5G", "20M", "HT", "2T", "48", "28",
+	"ETSI", "5G", "20M", "HT", "2T", "48", "30",
+	"MKK", "5G", "20M", "HT", "2T", "48", "30",
+	"FCC", "5G", "20M", "HT", "2T", "52", "34",
+	"ETSI", "5G", "20M", "HT", "2T", "52", "30",
+	"MKK", "5G", "20M", "HT", "2T", "52", "30",
+	"FCC", "5G", "20M", "HT", "2T", "56", "32",
+	"ETSI", "5G", "20M", "HT", "2T", "56", "30",
+	"MKK", "5G", "20M", "HT", "2T", "56", "30",
+	"FCC", "5G", "20M", "HT", "2T", "60", "30",
+	"ETSI", "5G", "20M", "HT", "2T", "60", "30",
+	"MKK", "5G", "20M", "HT", "2T", "60", "30",
+	"FCC", "5G", "20M", "HT", "2T", "64", "26",
+	"ETSI", "5G", "20M", "HT", "2T", "64", "30",
+	"MKK", "5G", "20M", "HT", "2T", "64", "30",
+	"FCC", "5G", "20M", "HT", "2T", "100", "28",
+	"ETSI", "5G", "20M", "HT", "2T", "100", "30",
+	"MKK", "5G", "20M", "HT", "2T", "100", "30",
+	"FCC", "5G", "20M", "HT", "2T", "104", "28",
+	"ETSI", "5G", "20M", "HT", "2T", "104", "30",
+	"MKK", "5G", "20M", "HT", "2T", "104", "30",
+	"FCC", "5G", "20M", "HT", "2T", "108", "30",
+	"ETSI", "5G", "20M", "HT", "2T", "108", "30",
+	"MKK", "5G", "20M", "HT", "2T", "108", "30",
+	"FCC", "5G", "20M", "HT", "2T", "112", "32",
+	"ETSI", "5G", "20M", "HT", "2T", "112", "30",
+	"MKK", "5G", "20M", "HT", "2T", "112", "30",
+	"FCC", "5G", "20M", "HT", "2T", "116", "32",
+	"ETSI", "5G", "20M", "HT", "2T", "116", "30",
+	"MKK", "5G", "20M", "HT", "2T", "116", "30",
+	"FCC", "5G", "20M", "HT", "2T", "120", "34",
+	"ETSI", "5G", "20M", "HT", "2T", "120", "30",
+	"MKK", "5G", "20M", "HT", "2T", "120", "30",
+	"FCC", "5G", "20M", "HT", "2T", "124", "32",
+	"ETSI", "5G", "20M", "HT", "2T", "124", "30",
+	"MKK", "5G", "20M", "HT", "2T", "124", "30",
+	"FCC", "5G", "20M", "HT", "2T", "128", "30",
+	"ETSI", "5G", "20M", "HT", "2T", "128", "30",
+	"MKK", "5G", "20M", "HT", "2T", "128", "30",
+	"FCC", "5G", "20M", "HT", "2T", "132", "28",
+	"ETSI", "5G", "20M", "HT", "2T", "132", "30",
+	"MKK", "5G", "20M", "HT", "2T", "132", "30",
+	"FCC", "5G", "20M", "HT", "2T", "136", "28",
+	"ETSI", "5G", "20M", "HT", "2T", "136", "30",
+	"MKK", "5G", "20M", "HT", "2T", "136", "30",
+	"FCC", "5G", "20M", "HT", "2T", "140", "26",
+	"ETSI", "5G", "20M", "HT", "2T", "140", "30",
+	"MKK", "5G", "20M", "HT", "2T", "140", "30",
+	"FCC", "5G", "20M", "HT", "2T", "149", "34",
+	"ETSI", "5G", "20M", "HT", "2T", "149", "30",
+	"MKK", "5G", "20M", "HT", "2T", "149", "63",
+	"FCC", "5G", "20M", "HT", "2T", "153", "34",
+	"ETSI", "5G", "20M", "HT", "2T", "153", "30",
+	"MKK", "5G", "20M", "HT", "2T", "153", "63",
+	"FCC", "5G", "20M", "HT", "2T", "157", "34",
+	"ETSI", "5G", "20M", "HT", "2T", "157", "30",
+	"MKK", "5G", "20M", "HT", "2T", "157", "63",
+	"FCC", "5G", "20M", "HT", "2T", "161", "34",
+	"ETSI", "5G", "20M", "HT", "2T", "161", "30",
+	"MKK", "5G", "20M", "HT", "2T", "161", "63",
+	"FCC", "5G", "20M", "HT", "2T", "165", "34",
+	"ETSI", "5G", "20M", "HT", "2T", "165", "30",
+	"MKK", "5G", "20M", "HT", "2T", "165", "63",
+	"FCC", "5G", "20M", "HT", "3T", "36", "26",
+	"ETSI", "5G", "20M", "HT", "3T", "36", "28",
+	"MKK", "5G", "20M", "HT", "3T", "36", "28",
+	"FCC", "5G", "20M", "HT", "3T", "40", "26",
+	"ETSI", "5G", "20M", "HT", "3T", "40", "28",
+	"MKK", "5G", "20M", "HT", "3T", "40", "28",
+	"FCC", "5G", "20M", "HT", "3T", "44", "26",
+	"ETSI", "5G", "20M", "HT", "3T", "44", "28",
+	"MKK", "5G", "20M", "HT", "3T", "44", "28",
+	"FCC", "5G", "20M", "HT", "3T", "48", "26",
+	"ETSI", "5G", "20M", "HT", "3T", "48", "28",
+	"MKK", "5G", "20M", "HT", "3T", "48", "28",
+	"FCC", "5G", "20M", "HT", "3T", "52", "32",
+	"ETSI", "5G", "20M", "HT", "3T", "52", "28",
+	"MKK", "5G", "20M", "HT", "3T", "52", "28",
+	"FCC", "5G", "20M", "HT", "3T", "56", "30",
+	"ETSI", "5G", "20M", "HT", "3T", "56", "28",
+	"MKK", "5G", "20M", "HT", "3T", "56", "28",
+	"FCC", "5G", "20M", "HT", "3T", "60", "28",
+	"ETSI", "5G", "20M", "HT", "3T", "60", "28",
+	"MKK", "5G", "20M", "HT", "3T", "60", "28",
+	"FCC", "5G", "20M", "HT", "3T", "64", "24",
+	"ETSI", "5G", "20M", "HT", "3T", "64", "28",
+	"MKK", "5G", "20M", "HT", "3T", "64", "28",
+	"FCC", "5G", "20M", "HT", "3T", "100", "26",
+	"ETSI", "5G", "20M", "HT", "3T", "100", "28",
+	"MKK", "5G", "20M", "HT", "3T", "100", "28",
+	"FCC", "5G", "20M", "HT", "3T", "104", "26",
+	"ETSI", "5G", "20M", "HT", "3T", "104", "28",
+	"MKK", "5G", "20M", "HT", "3T", "104", "28",
+	"FCC", "5G", "20M", "HT", "3T", "108", "28",
+	"ETSI", "5G", "20M", "HT", "3T", "108", "28",
+	"MKK", "5G", "20M", "HT", "3T", "108", "28",
+	"FCC", "5G", "20M", "HT", "3T", "112", "30",
+	"ETSI", "5G", "20M", "HT", "3T", "112", "28",
+	"MKK", "5G", "20M", "HT", "3T", "112", "28",
+	"FCC", "5G", "20M", "HT", "3T", "116", "30",
+	"ETSI", "5G", "20M", "HT", "3T", "116", "28",
+	"MKK", "5G", "20M", "HT", "3T", "116", "28",
+	"FCC", "5G", "20M", "HT", "3T", "120", "32",
+	"ETSI", "5G", "20M", "HT", "3T", "120", "28",
+	"MKK", "5G", "20M", "HT", "3T", "120", "28",
+	"FCC", "5G", "20M", "HT", "3T", "124", "30",
+	"ETSI", "5G", "20M", "HT", "3T", "124", "28",
+	"MKK", "5G", "20M", "HT", "3T", "124", "28",
+	"FCC", "5G", "20M", "HT", "3T", "128", "28",
+	"ETSI", "5G", "20M", "HT", "3T", "128", "28",
+	"MKK", "5G", "20M", "HT", "3T", "128", "28",
+	"FCC", "5G", "20M", "HT", "3T", "132", "26",
+	"ETSI", "5G", "20M", "HT", "3T", "132", "28",
+	"MKK", "5G", "20M", "HT", "3T", "132", "28",
+	"FCC", "5G", "20M", "HT", "3T", "136", "26",
+	"ETSI", "5G", "20M", "HT", "3T", "136", "28",
+	"MKK", "5G", "20M", "HT", "3T", "136", "28",
+	"FCC", "5G", "20M", "HT", "3T", "140", "24",
+	"ETSI", "5G", "20M", "HT", "3T", "140", "28",
+	"MKK", "5G", "20M", "HT", "3T", "140", "28",
+	"FCC", "5G", "20M", "HT", "3T", "149", "32",
+	"ETSI", "5G", "20M", "HT", "3T", "149", "28",
+	"MKK", "5G", "20M", "HT", "3T", "149", "63",
+	"FCC", "5G", "20M", "HT", "3T", "153", "32",
+	"ETSI", "5G", "20M", "HT", "3T", "153", "28",
+	"MKK", "5G", "20M", "HT", "3T", "153", "63",
+	"FCC", "5G", "20M", "HT", "3T", "157", "32",
+	"ETSI", "5G", "20M", "HT", "3T", "157", "28",
+	"MKK", "5G", "20M", "HT", "3T", "157", "63",
+	"FCC", "5G", "20M", "HT", "3T", "161", "32",
+	"ETSI", "5G", "20M", "HT", "3T", "161", "28",
+	"MKK", "5G", "20M", "HT", "3T", "161", "63",
+	"FCC", "5G", "20M", "HT", "3T", "165", "32",
+	"ETSI", "5G", "20M", "HT", "3T", "165", "28",
+	"MKK", "5G", "20M", "HT", "3T", "165", "63",
+	"FCC", "5G", "20M", "HT", "4T", "36", "24",
+	"ETSI", "5G", "20M", "HT", "4T", "36", "26",
+	"MKK", "5G", "20M", "HT", "4T", "36", "26",
+	"FCC", "5G", "20M", "HT", "4T", "40", "24",
+	"ETSI", "5G", "20M", "HT", "4T", "40", "26",
+	"MKK", "5G", "20M", "HT", "4T", "40", "26",
+	"FCC", "5G", "20M", "HT", "4T", "44", "24",
+	"ETSI", "5G", "20M", "HT", "4T", "44", "26",
+	"MKK", "5G", "20M", "HT", "4T", "44", "26",
+	"FCC", "5G", "20M", "HT", "4T", "48", "24",
+	"ETSI", "5G", "20M", "HT", "4T", "48", "26",
+	"MKK", "5G", "20M", "HT", "4T", "48", "26",
+	"FCC", "5G", "20M", "HT", "4T", "52", "30",
+	"ETSI", "5G", "20M", "HT", "4T", "52", "26",
+	"MKK", "5G", "20M", "HT", "4T", "52", "26",
+	"FCC", "5G", "20M", "HT", "4T", "56", "28",
+	"ETSI", "5G", "20M", "HT", "4T", "56", "26",
+	"MKK", "5G", "20M", "HT", "4T", "56", "26",
+	"FCC", "5G", "20M", "HT", "4T", "60", "26",
+	"ETSI", "5G", "20M", "HT", "4T", "60", "26",
+	"MKK", "5G", "20M", "HT", "4T", "60", "26",
+	"FCC", "5G", "20M", "HT", "4T", "64", "22",
+	"ETSI", "5G", "20M", "HT", "4T", "64", "26",
+	"MKK", "5G", "20M", "HT", "4T", "64", "26",
+	"FCC", "5G", "20M", "HT", "4T", "100", "24",
+	"ETSI", "5G", "20M", "HT", "4T", "100", "26",
+	"MKK", "5G", "20M", "HT", "4T", "100", "26",
+	"FCC", "5G", "20M", "HT", "4T", "104", "24",
+	"ETSI", "5G", "20M", "HT", "4T", "104", "26",
+	"MKK", "5G", "20M", "HT", "4T", "104", "26",
+	"FCC", "5G", "20M", "HT", "4T", "108", "26",
+	"ETSI", "5G", "20M", "HT", "4T", "108", "26",
+	"MKK", "5G", "20M", "HT", "4T", "108", "26",
+	"FCC", "5G", "20M", "HT", "4T", "112", "28",
+	"ETSI", "5G", "20M", "HT", "4T", "112", "26",
+	"MKK", "5G", "20M", "HT", "4T", "112", "26",
+	"FCC", "5G", "20M", "HT", "4T", "116", "28",
+	"ETSI", "5G", "20M", "HT", "4T", "116", "26",
+	"MKK", "5G", "20M", "HT", "4T", "116", "26",
+	"FCC", "5G", "20M", "HT", "4T", "120", "30",
+	"ETSI", "5G", "20M", "HT", "4T", "120", "26",
+	"MKK", "5G", "20M", "HT", "4T", "120", "26",
+	"FCC", "5G", "20M", "HT", "4T", "124", "28",
+	"ETSI", "5G", "20M", "HT", "4T", "124", "26",
+	"MKK", "5G", "20M", "HT", "4T", "124", "26",
+	"FCC", "5G", "20M", "HT", "4T", "128", "26",
+	"ETSI", "5G", "20M", "HT", "4T", "128", "26",
+	"MKK", "5G", "20M", "HT", "4T", "128", "26",
+	"FCC", "5G", "20M", "HT", "4T", "132", "24",
+	"ETSI", "5G", "20M", "HT", "4T", "132", "26",
+	"MKK", "5G", "20M", "HT", "4T", "132", "26",
+	"FCC", "5G", "20M", "HT", "4T", "136", "24",
+	"ETSI", "5G", "20M", "HT", "4T", "136", "26",
+	"MKK", "5G", "20M", "HT", "4T", "136", "26",
+	"FCC", "5G", "20M", "HT", "4T", "140", "22",
+	"ETSI", "5G", "20M", "HT", "4T", "140", "26",
+	"MKK", "5G", "20M", "HT", "4T", "140", "26",
+	"FCC", "5G", "20M", "HT", "4T", "149", "30",
+	"ETSI", "5G", "20M", "HT", "4T", "149", "26",
+	"MKK", "5G", "20M", "HT", "4T", "149", "63",
+	"FCC", "5G", "20M", "HT", "4T", "153", "30",
+	"ETSI", "5G", "20M", "HT", "4T", "153", "26",
+	"MKK", "5G", "20M", "HT", "4T", "153", "63",
+	"FCC", "5G", "20M", "HT", "4T", "157", "30",
+	"ETSI", "5G", "20M", "HT", "4T", "157", "26",
+	"MKK", "5G", "20M", "HT", "4T", "157", "63",
+	"FCC", "5G", "20M", "HT", "4T", "161", "30",
+	"ETSI", "5G", "20M", "HT", "4T", "161", "26",
+	"MKK", "5G", "20M", "HT", "4T", "161", "63",
+	"FCC", "5G", "20M", "HT", "4T", "165", "30",
+	"ETSI", "5G", "20M", "HT", "4T", "165", "26",
+	"MKK", "5G", "20M", "HT", "4T", "165", "63",
+	"FCC", "5G", "40M", "HT", "1T", "38", "30",
+	"ETSI", "5G", "40M", "HT", "1T", "38", "32",
+	"MKK", "5G", "40M", "HT", "1T", "38", "32",
+	"FCC", "5G", "40M", "HT", "1T", "46", "30",
+	"ETSI", "5G", "40M", "HT", "1T", "46", "32",
+	"MKK", "5G", "40M", "HT", "1T", "46", "32",
+	"FCC", "5G", "40M", "HT", "1T", "54", "32",
+	"ETSI", "5G", "40M", "HT", "1T", "54", "32",
+	"MKK", "5G", "40M", "HT", "1T", "54", "32",
+	"FCC", "5G", "40M", "HT", "1T", "62", "32",
+	"ETSI", "5G", "40M", "HT", "1T", "62", "32",
+	"MKK", "5G", "40M", "HT", "1T", "62", "32",
+	"FCC", "5G", "40M", "HT", "1T", "102", "28",
+	"ETSI", "5G", "40M", "HT", "1T", "102", "32",
+	"MKK", "5G", "40M", "HT", "1T", "102", "32",
+	"FCC", "5G", "40M", "HT", "1T", "110", "32",
+	"ETSI", "5G", "40M", "HT", "1T", "110", "32",
+	"MKK", "5G", "40M", "HT", "1T", "110", "32",
+	"FCC", "5G", "40M", "HT", "1T", "118", "36",
+	"ETSI", "5G", "40M", "HT", "1T", "118", "32",
+	"MKK", "5G", "40M", "HT", "1T", "118", "32",
+	"FCC", "5G", "40M", "HT", "1T", "126", "34",
+	"ETSI", "5G", "40M", "HT", "1T", "126", "32",
+	"MKK", "5G", "40M", "HT", "1T", "126", "32",
+	"FCC", "5G", "40M", "HT", "1T", "134", "32",
+	"ETSI", "5G", "40M", "HT", "1T", "134", "32",
+	"MKK", "5G", "40M", "HT", "1T", "134", "32",
+	"FCC", "5G", "40M", "HT", "1T", "151", "36",
+	"ETSI", "5G", "40M", "HT", "1T", "151", "32",
+	"MKK", "5G", "40M", "HT", "1T", "151", "63",
+	"FCC", "5G", "40M", "HT", "1T", "159", "36",
+	"ETSI", "5G", "40M", "HT", "1T", "159", "32",
+	"MKK", "5G", "40M", "HT", "1T", "159", "63",
+	"FCC", "5G", "40M", "HT", "2T", "38", "28",
+	"ETSI", "5G", "40M", "HT", "2T", "38", "30",
+	"MKK", "5G", "40M", "HT", "2T", "38", "30",
+	"FCC", "5G", "40M", "HT", "2T", "46", "28",
+	"ETSI", "5G", "40M", "HT", "2T", "46", "30",
+	"MKK", "5G", "40M", "HT", "2T", "46", "30",
+	"FCC", "5G", "40M", "HT", "2T", "54", "30",
+	"ETSI", "5G", "40M", "HT", "2T", "54", "30",
+	"MKK", "5G", "40M", "HT", "2T", "54", "30",
+	"FCC", "5G", "40M", "HT", "2T", "62", "30",
+	"ETSI", "5G", "40M", "HT", "2T", "62", "30",
+	"MKK", "5G", "40M", "HT", "2T", "62", "30",
+	"FCC", "5G", "40M", "HT", "2T", "102", "26",
+	"ETSI", "5G", "40M", "HT", "2T", "102", "30",
+	"MKK", "5G", "40M", "HT", "2T", "102", "30",
+	"FCC", "5G", "40M", "HT", "2T", "110", "30",
+	"ETSI", "5G", "40M", "HT", "2T", "110", "30",
+	"MKK", "5G", "40M", "HT", "2T", "110", "30",
+	"FCC", "5G", "40M", "HT", "2T", "118", "34",
+	"ETSI", "5G", "40M", "HT", "2T", "118", "30",
+	"MKK", "5G", "40M", "HT", "2T", "118", "30",
+	"FCC", "5G", "40M", "HT", "2T", "126", "32",
+	"ETSI", "5G", "40M", "HT", "2T", "126", "30",
+	"MKK", "5G", "40M", "HT", "2T", "126", "30",
+	"FCC", "5G", "40M", "HT", "2T", "134", "30",
+	"ETSI", "5G", "40M", "HT", "2T", "134", "30",
+	"MKK", "5G", "40M", "HT", "2T", "134", "30",
+	"FCC", "5G", "40M", "HT", "2T", "151", "34",
+	"ETSI", "5G", "40M", "HT", "2T", "151", "30",
+	"MKK", "5G", "40M", "HT", "2T", "151", "63",
+	"FCC", "5G", "40M", "HT", "2T", "159", "34",
+	"ETSI", "5G", "40M", "HT", "2T", "159", "30",
+	"MKK", "5G", "40M", "HT", "2T", "159", "63",
+	"FCC", "5G", "40M", "HT", "3T", "38", "26",
+	"ETSI", "5G", "40M", "HT", "3T", "38", "28",
+	"MKK", "5G", "40M", "HT", "3T", "38", "28",
+	"FCC", "5G", "40M", "HT", "3T", "46", "26",
+	"ETSI", "5G", "40M", "HT", "3T", "46", "28",
+	"MKK", "5G", "40M", "HT", "3T", "46", "28",
+	"FCC", "5G", "40M", "HT", "3T", "54", "28",
+	"ETSI", "5G", "40M", "HT", "3T", "54", "28",
+	"MKK", "5G", "40M", "HT", "3T", "54", "28",
+	"FCC", "5G", "40M", "HT", "3T", "62", "28",
+	"ETSI", "5G", "40M", "HT", "3T", "62", "28",
+	"MKK", "5G", "40M", "HT", "3T", "62", "28",
+	"FCC", "5G", "40M", "HT", "3T", "102", "24",
+	"ETSI", "5G", "40M", "HT", "3T", "102", "28",
+	"MKK", "5G", "40M", "HT", "3T", "102", "28",
+	"FCC", "5G", "40M", "HT", "3T", "110", "28",
+	"ETSI", "5G", "40M", "HT", "3T", "110", "28",
+	"MKK", "5G", "40M", "HT", "3T", "110", "28",
+	"FCC", "5G", "40M", "HT", "3T", "118", "32",
+	"ETSI", "5G", "40M", "HT", "3T", "118", "28",
+	"MKK", "5G", "40M", "HT", "3T", "118", "28",
+	"FCC", "5G", "40M", "HT", "3T", "126", "30",
+	"ETSI", "5G", "40M", "HT", "3T", "126", "28",
+	"MKK", "5G", "40M", "HT", "3T", "126", "28",
+	"FCC", "5G", "40M", "HT", "3T", "134", "28",
+	"ETSI", "5G", "40M", "HT", "3T", "134", "28",
+	"MKK", "5G", "40M", "HT", "3T", "134", "28",
+	"FCC", "5G", "40M", "HT", "3T", "151", "32",
+	"ETSI", "5G", "40M", "HT", "3T", "151", "28",
+	"MKK", "5G", "40M", "HT", "3T", "151", "63",
+	"FCC", "5G", "40M", "HT", "3T", "159", "32",
+	"ETSI", "5G", "40M", "HT", "3T", "159", "28",
+	"MKK", "5G", "40M", "HT", "3T", "159", "63",
+	"FCC", "5G", "40M", "HT", "4T", "38", "24",
+	"ETSI", "5G", "40M", "HT", "4T", "38", "26",
+	"MKK", "5G", "40M", "HT", "4T", "38", "26",
+	"FCC", "5G", "40M", "HT", "4T", "46", "24",
+	"ETSI", "5G", "40M", "HT", "4T", "46", "26",
+	"MKK", "5G", "40M", "HT", "4T", "46", "26",
+	"FCC", "5G", "40M", "HT", "4T", "54", "26",
+	"ETSI", "5G", "40M", "HT", "4T", "54", "26",
+	"MKK", "5G", "40M", "HT", "4T", "54", "26",
+	"FCC", "5G", "40M", "HT", "4T", "62", "26",
+	"ETSI", "5G", "40M", "HT", "4T", "62", "26",
+	"MKK", "5G", "40M", "HT", "4T", "62", "26",
+	"FCC", "5G", "40M", "HT", "4T", "102", "22",
+	"ETSI", "5G", "40M", "HT", "4T", "102", "26",
+	"MKK", "5G", "40M", "HT", "4T", "102", "26",
+	"FCC", "5G", "40M", "HT", "4T", "110", "26",
+	"ETSI", "5G", "40M", "HT", "4T", "110", "26",
+	"MKK", "5G", "40M", "HT", "4T", "110", "26",
+	"FCC", "5G", "40M", "HT", "4T", "118", "30",
+	"ETSI", "5G", "40M", "HT", "4T", "118", "26",
+	"MKK", "5G", "40M", "HT", "4T", "118", "26",
+	"FCC", "5G", "40M", "HT", "4T", "126", "28",
+	"ETSI", "5G", "40M", "HT", "4T", "126", "26",
+	"MKK", "5G", "40M", "HT", "4T", "126", "26",
+	"FCC", "5G", "40M", "HT", "4T", "134", "26",
+	"ETSI", "5G", "40M", "HT", "4T", "134", "26",
+	"MKK", "5G", "40M", "HT", "4T", "134", "26",
+	"FCC", "5G", "40M", "HT", "4T", "151", "30",
+	"ETSI", "5G", "40M", "HT", "4T", "151", "26",
+	"MKK", "5G", "40M", "HT", "4T", "151", "63",
+	"FCC", "5G", "40M", "HT", "4T", "159", "30",
+	"ETSI", "5G", "40M", "HT", "4T", "159", "26",
+	"MKK", "5G", "40M", "HT", "4T", "159", "63",
+	"FCC", "5G", "80M", "VHT", "1T", "42", "30",
+	"ETSI", "5G", "80M", "VHT", "1T", "42", "32",
+	"MKK", "5G", "80M", "VHT", "1T", "42", "32",
+	"FCC", "5G", "80M", "VHT", "1T", "58", "28",
+	"ETSI", "5G", "80M", "VHT", "1T", "58", "32",
+	"MKK", "5G", "80M", "VHT", "1T", "58", "32",
+	"FCC", "5G", "80M", "VHT", "1T", "106", "30",
+	"ETSI", "5G", "80M", "VHT", "1T", "106", "32",
+	"MKK", "5G", "80M", "VHT", "1T", "106", "32",
+	"FCC", "5G", "80M", "VHT", "1T", "122", "34",
+	"ETSI", "5G", "80M", "VHT", "1T", "122", "32",
+	"MKK", "5G", "80M", "VHT", "1T", "122", "32",
+	"FCC", "5G", "80M", "VHT", "1T", "155", "36",
+	"ETSI", "5G", "80M", "VHT", "1T", "155", "32",
+	"MKK", "5G", "80M", "VHT", "1T", "155", "63",
+	"FCC", "5G", "80M", "VHT", "2T", "42", "28",
+	"ETSI", "5G", "80M", "VHT", "2T", "42", "30",
+	"MKK", "5G", "80M", "VHT", "2T", "42", "30",
+	"FCC", "5G", "80M", "VHT", "2T", "58", "26",
+	"ETSI", "5G", "80M", "VHT", "2T", "58", "30",
+	"MKK", "5G", "80M", "VHT", "2T", "58", "30",
+	"FCC", "5G", "80M", "VHT", "2T", "106", "28",
+	"ETSI", "5G", "80M", "VHT", "2T", "106", "30",
+	"MKK", "5G", "80M", "VHT", "2T", "106", "30",
+	"FCC", "5G", "80M", "VHT", "2T", "122", "32",
+	"ETSI", "5G", "80M", "VHT", "2T", "122", "30",
+	"MKK", "5G", "80M", "VHT", "2T", "122", "30",
+	"FCC", "5G", "80M", "VHT", "2T", "155", "34",
+	"ETSI", "5G", "80M", "VHT", "2T", "155", "30",
+	"MKK", "5G", "80M", "VHT", "2T", "155", "63",
+	"FCC", "5G", "80M", "VHT", "3T", "42", "26",
+	"ETSI", "5G", "80M", "VHT", "3T", "42", "28",
+	"MKK", "5G", "80M", "VHT", "3T", "42", "28",
+	"FCC", "5G", "80M", "VHT", "3T", "58", "24",
+	"ETSI", "5G", "80M", "VHT", "3T", "58", "28",
+	"MKK", "5G", "80M", "VHT", "3T", "58", "28",
+	"FCC", "5G", "80M", "VHT", "3T", "106", "26",
+	"ETSI", "5G", "80M", "VHT", "3T", "106", "28",
+	"MKK", "5G", "80M", "VHT", "3T", "106", "28",
+	"FCC", "5G", "80M", "VHT", "3T", "122", "30",
+	"ETSI", "5G", "80M", "VHT", "3T", "122", "28",
+	"MKK", "5G", "80M", "VHT", "3T", "122", "28",
+	"FCC", "5G", "80M", "VHT", "3T", "155", "32",
+	"ETSI", "5G", "80M", "VHT", "3T", "155", "28",
+	"MKK", "5G", "80M", "VHT", "3T", "155", "63",
+	"FCC", "5G", "80M", "VHT", "4T", "42", "24",
+	"ETSI", "5G", "80M", "VHT", "4T", "42", "26",
+	"MKK", "5G", "80M", "VHT", "4T", "42", "26",
+	"FCC", "5G", "80M", "VHT", "4T", "58", "22",
+	"ETSI", "5G", "80M", "VHT", "4T", "58", "26",
+	"MKK", "5G", "80M", "VHT", "4T", "58", "26",
+	"FCC", "5G", "80M", "VHT", "4T", "106", "24",
+	"ETSI", "5G", "80M", "VHT", "4T", "106", "26",
+	"MKK", "5G", "80M", "VHT", "4T", "106", "26",
+	"FCC", "5G", "80M", "VHT", "4T", "122", "28",
+	"ETSI", "5G", "80M", "VHT", "4T", "122", "26",
+	"MKK", "5G", "80M", "VHT", "4T", "122", "26",
+	"FCC", "5G", "80M", "VHT", "4T", "155", "30",
+	"ETSI", "5G", "80M", "VHT", "4T", "155", "26",
+	"MKK", "5G", "80M", "VHT", "4T", "155", "63"
+};
+
+void
+odm_read_and_config_tc_8821c_txpwr_lmt(
+	struct PHY_DM_STRUCT  *p_dm_odm
+)
+{
+	u32     i           = 0;
+	u32     array_len    = sizeof(array_tc_8821c_txpwr_lmt) / sizeof(u8 *);
+	u8 **array      = (u8 **)array_tc_8821c_txpwr_lmt;
+
+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
+	struct _ADAPTER		*adapter = p_dm_odm->adapter;
+	HAL_DATA_TYPE	*p_hal_data = GET_HAL_DATA(adapter);
+
+	PlatformZeroMemory(p_hal_data->BufOfLinesPwrLmt, MAX_LINES_HWCONFIG_TXT * MAX_BYTES_LINE_HWCONFIG_TXT);
+	p_hal_data->nLinesReadPwrLmt = array_len / 7;
+#endif
+
+	ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> odm_read_and_config_tc_8821c_txpwr_lmt\n"));
+
+	for (i = 0; i < array_len; i += 7) {
+		u8 *regulation = array[i];
+		u8 *band = array[i + 1];
+		u8 *bandwidth = array[i + 2];
+		u8 *rate = array[i + 3];
+		u8 *rf_path = array[i + 4];
+		u8 *chnl = array[i + 5];
+		u8 *val = array[i + 6];
+
+		odm_config_bb_txpwr_lmt_8821c(p_dm_odm, regulation, band, bandwidth, rate, rf_path, chnl, val);
+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
+		rsprintf((char *)p_hal_data->BufOfLinesPwrLmt[i / 7], 100, "\"%s\", \"%s\", \"%s\", \"%s\", \"%s\", \"%s\", \"%s\",",
+			 regulation, band, bandwidth, rate, rf_path, chnl, val);
+#endif
+	}
+
+}
+
+#endif /* end of HWIMG_SUPPORT*/
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/rtl8821c/halhwimg8821c_testchip_rf.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/rtl8821c/halhwimg8821c_testchip_rf.h
--- linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/rtl8821c/halhwimg8821c_testchip_rf.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/rtl8821c/halhwimg8821c_testchip_rf.h	2020-04-10 16:35:06.834660908 +0300
@@ -0,0 +1,58 @@
+/******************************************************************************
+*
+* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
+*
+* This program is free software; you can redistribute it and/or modify it
+* under the terms of version 2 of the GNU General Public License as
+* published by the Free Software Foundation.
+*
+* This program is distributed in the hope that it will be useful, but WITHOUT
+* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+* more details.
+*
+* You should have received a copy of the GNU General Public License along with
+* this program; if not, write to the Free Software Foundation, Inc.,
+* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
+*
+*
+******************************************************************************/
+
+/*Image2HeaderVersion: 2.22*/
+#if (RTL8821C_SUPPORT == 1)
+#ifndef __INC_TC_RF_HW_IMG_8821C_H
+#define __INC_TC_RF_HW_IMG_8821C_H
+
+
+/******************************************************************************
+*                           RadioA.TXT
+******************************************************************************/
+
+void
+odm_read_and_config_tc_8821c_radioa(/* TC: Test Chip, MP: MP Chip*/
+	struct PHY_DM_STRUCT  *p_dm_odm
+);
+u32 odm_get_version_tc_8821c_radioa(void);
+
+/******************************************************************************
+*                           TxPowerTrack.TXT
+******************************************************************************/
+
+void
+odm_read_and_config_tc_8821c_txpowertrack(/* TC: Test Chip, MP: MP Chip*/
+	struct PHY_DM_STRUCT  *p_dm_odm
+);
+u32 odm_get_version_tc_8821c_txpowertrack(void);
+
+/******************************************************************************
+*                           TXPWR_LMT.TXT
+******************************************************************************/
+
+void
+odm_read_and_config_tc_8821c_txpwr_lmt(/* TC: Test Chip, MP: MP Chip*/
+	struct PHY_DM_STRUCT  *p_dm_odm
+);
+u32 odm_get_version_tc_8821c_txpwr_lmt(void);
+
+#endif
+#endif /* end of HWIMG_SUPPORT*/
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/rtl8821c/halphyrf_8821c.c linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/rtl8821c/halphyrf_8821c.c
--- linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/rtl8821c/halphyrf_8821c.c	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/rtl8821c/halphyrf_8821c.c	2020-04-10 16:35:06.835660954 +0300
@@ -0,0 +1,486 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
+ *
+ *
+ ******************************************************************************/
+
+#include "mp_precomp.h"
+#include "../phydm_precomp.h"
+
+#if (RTL8821C_SUPPORT == 1)
+
+boolean
+get_mix_mode_tx_agc_bbs_wing_offset_8821c(
+	void				*p_dm_void,
+	enum pwrtrack_method	method,
+	u8				rf_path,
+	u8				tx_power_index_offest_upper_bound,
+	s8				tx_power_index_offest_lower_bound
+)
+{
+	struct PHY_DM_STRUCT		*p_dm_odm	=	(struct PHY_DM_STRUCT *)p_dm_void;
+	struct odm_rf_calibration_structure	*p_rf_calibrate_info = &(p_dm_odm->rf_calibrate_info);
+
+	u8	bb_swing_upper_bound = p_rf_calibrate_info->default_ofdm_index + 10;
+	u8	bb_swing_lower_bound = 0;
+
+	s8	tx_agc_index = 0;
+	u8	tx_bb_swing_index = p_rf_calibrate_info->default_ofdm_index;
+
+	ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
+		("Path_%d pRF->absolute_ofdm_swing_idx[rf_path]=%d, tx_power_index_offest_upper_bound=%d, tx_power_index_offest_lower_bound=%d\n",
+		rf_path, p_rf_calibrate_info->absolute_ofdm_swing_idx[rf_path], tx_power_index_offest_upper_bound, tx_power_index_offest_lower_bound));
+
+	if (tx_power_index_offest_upper_bound > 0XF)
+		tx_power_index_offest_upper_bound = 0XF;
+
+	if (tx_power_index_offest_lower_bound < -15)
+		tx_power_index_offest_lower_bound = -15;
+
+
+	if (p_rf_calibrate_info->absolute_ofdm_swing_idx[rf_path] >= 0 && p_rf_calibrate_info->absolute_ofdm_swing_idx[rf_path] <= tx_power_index_offest_upper_bound) {
+		tx_agc_index = p_rf_calibrate_info->absolute_ofdm_swing_idx[rf_path];
+		tx_bb_swing_index = p_rf_calibrate_info->default_ofdm_index;
+	} else if (p_rf_calibrate_info->absolute_ofdm_swing_idx[rf_path] >= 0 && (p_rf_calibrate_info->absolute_ofdm_swing_idx[rf_path] > tx_power_index_offest_upper_bound)) {
+		tx_agc_index = tx_power_index_offest_upper_bound;
+		p_rf_calibrate_info->remnant_ofdm_swing_idx[rf_path] = p_rf_calibrate_info->absolute_ofdm_swing_idx[rf_path] - tx_power_index_offest_upper_bound;
+		tx_bb_swing_index = p_rf_calibrate_info->default_ofdm_index + p_rf_calibrate_info->remnant_ofdm_swing_idx[rf_path];
+
+		if (tx_bb_swing_index > bb_swing_upper_bound)
+			tx_bb_swing_index = bb_swing_upper_bound;
+	} else if (p_rf_calibrate_info->absolute_ofdm_swing_idx[rf_path] < 0 && (p_rf_calibrate_info->absolute_ofdm_swing_idx[rf_path] >= tx_power_index_offest_lower_bound)) {
+		tx_agc_index = p_rf_calibrate_info->absolute_ofdm_swing_idx[rf_path];
+		tx_bb_swing_index = p_rf_calibrate_info->default_ofdm_index;
+	} else if (p_rf_calibrate_info->absolute_ofdm_swing_idx[rf_path] < 0 && (p_rf_calibrate_info->absolute_ofdm_swing_idx[rf_path] < tx_power_index_offest_lower_bound)) {
+		tx_agc_index = tx_power_index_offest_lower_bound;
+		p_rf_calibrate_info->remnant_ofdm_swing_idx[rf_path] = p_rf_calibrate_info->absolute_ofdm_swing_idx[rf_path] - tx_power_index_offest_lower_bound;
+
+		if (p_rf_calibrate_info->default_ofdm_index > (p_rf_calibrate_info->remnant_ofdm_swing_idx[rf_path] * (-1)))
+			tx_bb_swing_index = p_rf_calibrate_info->default_ofdm_index + p_rf_calibrate_info->remnant_ofdm_swing_idx[rf_path];
+		else
+			tx_bb_swing_index = bb_swing_lower_bound;
+	}
+
+	p_rf_calibrate_info->absolute_ofdm_swing_idx[rf_path] = tx_agc_index;
+	p_rf_calibrate_info->bb_swing_idx_ofdm[rf_path] = tx_bb_swing_index;
+
+	ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
+		("MixMode Offset Path_%d   pRF->absolute_ofdm_swing_idx[rf_path]=%d   pRF->bb_swing_idx_ofdm[rf_path]=%d   TxPwrIdxOffestUpper=%d   TxPwrIdxOffestLower=%d\n",
+		rf_path, p_rf_calibrate_info->absolute_ofdm_swing_idx[rf_path], p_rf_calibrate_info->bb_swing_idx_ofdm[rf_path], tx_power_index_offest_upper_bound, tx_power_index_offest_lower_bound));
+
+	return true;
+}
+
+
+void
+odm_tx_pwr_track_set_pwr8821c(
+	void				*p_dm_void,
+	enum pwrtrack_method	method,
+	u8				rf_path,
+	u8				channel_mapped_index
+)
+{
+	struct PHY_DM_STRUCT	*p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
+	struct _ADAPTER	*adapter = p_dm_odm->adapter;
+	HAL_DATA_TYPE	*p_hal_data = GET_HAL_DATA(adapter);
+	struct odm_rf_calibration_structure	*p_rf_calibrate_info = &(p_dm_odm->rf_calibrate_info);
+	u8			channel  = *p_dm_odm->p_channel;
+	u8			band_width  = *p_dm_odm->p_band_width;
+	u8			tx_power_index_offest_upper_bound = 0;
+	s8			tx_power_index_offest_lower_bound = 0;
+	u8			tx_power_index = 0;
+	u8			tx_rate = 0xFF;
+
+
+	if (p_dm_odm->mp_mode == true) {
+#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
+#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
+#if (MP_DRIVER == 1)
+		PMPT_CONTEXT p_mpt_ctx = &(adapter->MptCtx);
+
+		tx_rate = MptToMgntRate(p_mpt_ctx->MptRateIndex);
+#endif
+#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
+		PMPT_CONTEXT p_mpt_ctx = &(adapter->mppriv.mpt_ctx);
+
+		tx_rate = mpt_to_mgnt_rate(p_mpt_ctx->mpt_rate_index);
+#endif
+#endif
+	} else {
+		u16	rate	 = *(p_dm_odm->p_forced_data_rate);
+
+		if (!rate) { /*auto rate*/
+#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
+			tx_rate = adapter->HalFunc.GetHwRateFromMRateHandler(p_dm_odm->tx_rate);
+#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
+			if (p_dm_odm->number_linked_client != 0)
+				tx_rate = hw_rate_to_m_rate(p_dm_odm->tx_rate);
+#endif
+		} else   /*force rate*/
+			tx_rate = (u8) rate;
+	}
+
+	ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("Call:%s tx_rate=0x%X\n", __func__, tx_rate));
+
+	ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
+		("pRF->default_ofdm_index=%d   pRF->default_cck_index=%d\n", p_rf_calibrate_info->default_ofdm_index, p_rf_calibrate_info->default_cck_index));
+
+	ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
+		("pRF->absolute_ofdm_swing_idx=%d   pRF->remnant_ofdm_swing_idx=%d   pRF->absolute_cck_swing_idx=%d   pRF->remnant_cck_swing_idx=%d   rf_path=%d\n",
+		p_rf_calibrate_info->absolute_ofdm_swing_idx[rf_path], p_rf_calibrate_info->remnant_ofdm_swing_idx[rf_path], p_rf_calibrate_info->absolute_cck_swing_idx[rf_path], p_rf_calibrate_info->remnant_cck_swing_idx, rf_path));
+
+#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
+	tx_power_index = odm_get_tx_power_index(p_dm_odm, (enum odm_rf_radio_path_e) rf_path, tx_rate, band_width, channel);
+#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
+	if (p_dm_odm->mp_mode == true)
+		tx_power_index = odm_get_tx_power_index(p_dm_odm, (enum odm_rf_radio_path_e) rf_path, tx_rate, band_width, channel);
+	else {
+		if (p_dm_odm->number_linked_client != 0)
+			tx_power_index = odm_get_tx_power_index(p_dm_odm, (enum odm_rf_radio_path_e) rf_path, tx_rate, band_width, channel);
+	}
+#endif
+
+	if (tx_power_index >= 63)
+		tx_power_index = 63;
+
+	tx_power_index_offest_upper_bound = 63 - tx_power_index;
+
+	tx_power_index_offest_lower_bound = 0 - tx_power_index;
+
+	ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
+		("tx_power_index=%d tx_power_index_offest_upper_bound=%d tx_power_index_offest_lower_bound=%d rf_path=%d\n", tx_power_index, tx_power_index_offest_upper_bound, tx_power_index_offest_lower_bound, rf_path));
+
+	if (method == BBSWING) {	/*use for mp driver clean power tracking status*/
+		switch (rf_path) {
+		case ODM_RF_PATH_A:
+			odm_set_bb_reg(p_dm_odm, 0xC94, (BIT(6) | BIT(5) | BIT(4) | BIT(3) | BIT(2) | BIT(1)), ((p_rf_calibrate_info->absolute_ofdm_swing_idx[rf_path]) & 0x3f));
+			odm_set_bb_reg(p_dm_odm, REG_A_TX_SCALE_JAGUAR, 0xFFE00000, tx_scaling_table_jaguar[p_rf_calibrate_info->bb_swing_idx_ofdm[rf_path]]);
+			break;
+
+		default:
+			break;
+		}
+
+	} else if (method == MIX_MODE) {
+		switch (rf_path) {
+		case ODM_RF_PATH_A:
+			get_mix_mode_tx_agc_bbs_wing_offset_8821c(p_dm_odm, method, rf_path, tx_power_index_offest_upper_bound, tx_power_index_offest_lower_bound);
+			odm_set_bb_reg(p_dm_odm, 0xC94, (BIT(6) | BIT(5) | BIT(4) | BIT(3) | BIT(2) | BIT(1)), ((p_rf_calibrate_info->absolute_ofdm_swing_idx[rf_path]) & 0x3f));
+			odm_set_bb_reg(p_dm_odm, REG_A_TX_SCALE_JAGUAR, 0xFFE00000, tx_scaling_table_jaguar[p_rf_calibrate_info->bb_swing_idx_ofdm[rf_path]]);
+
+			ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
+				("TXAGC(0xC94)=0x%x BBSwing(0xc1c)=0x%x BBSwingIndex=%d rf_path=%d\n",
+				odm_get_bb_reg(p_dm_odm, 0xC94, (BIT(6) | BIT(5) | BIT(4) | BIT(3) | BIT(2) | BIT(1))),
+				odm_get_bb_reg(p_dm_odm, 0xc1c, 0xFFE00000),
+				p_rf_calibrate_info->bb_swing_idx_ofdm[rf_path], rf_path));
+			break;
+
+		default:
+			break;
+		}
+	}
+
+
+}
+
+
+void
+get_delta_swing_table_8821c(
+	void		*p_dm_void,
+#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
+	u8 **temperature_up_a,
+	u8 **temperature_down_a,
+	u8 **temperature_up_b,
+	u8 **temperature_down_b,
+	u8 **temperature_up_cck_a,
+	u8 **temperature_down_cck_a,
+	u8 **temperature_up_cck_b,
+	u8 **temperature_down_cck_b
+#else
+	u8 **temperature_up_a,
+	u8 **temperature_down_a,
+	u8 **temperature_up_b,
+	u8 **temperature_down_b
+#endif
+)
+{
+	struct PHY_DM_STRUCT		*p_dm_odm		= (struct PHY_DM_STRUCT *)p_dm_void;
+	struct odm_rf_calibration_structure	*p_rf_calibrate_info	= &(p_dm_odm->rf_calibrate_info);
+
+#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
+	u8			channel			= *(p_dm_odm->p_channel);
+#else
+	struct _ADAPTER		*adapter			= p_dm_odm->adapter;
+	HAL_DATA_TYPE	*p_hal_data		= GET_HAL_DATA(adapter);
+	u8			channel			= *p_dm_odm->p_channel;
+#endif
+
+#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
+	*temperature_up_cck_a   = p_rf_calibrate_info->delta_swing_table_idx_2g_cck_a_p;
+	*temperature_down_cck_a = p_rf_calibrate_info->delta_swing_table_idx_2g_cck_a_n;
+	*temperature_up_cck_b   = p_rf_calibrate_info->delta_swing_table_idx_2g_cck_b_p;
+	*temperature_down_cck_b = p_rf_calibrate_info->delta_swing_table_idx_2g_cck_b_n;
+#endif
+
+	*temperature_up_a   = p_rf_calibrate_info->delta_swing_table_idx_2ga_p;
+	*temperature_down_a = p_rf_calibrate_info->delta_swing_table_idx_2ga_n;
+	*temperature_up_b   = p_rf_calibrate_info->delta_swing_table_idx_2gb_p;
+	*temperature_down_b = p_rf_calibrate_info->delta_swing_table_idx_2gb_n;
+
+	if (36 <= channel && channel <= 64) {
+		*temperature_up_a   = p_rf_calibrate_info->delta_swing_table_idx_5ga_p[0];
+		*temperature_down_a = p_rf_calibrate_info->delta_swing_table_idx_5ga_n[0];
+		*temperature_up_b   = p_rf_calibrate_info->delta_swing_table_idx_5gb_p[0];
+		*temperature_down_b = p_rf_calibrate_info->delta_swing_table_idx_5gb_n[0];
+	} else if (100 <= channel && channel <= 144)	{
+		*temperature_up_a   = p_rf_calibrate_info->delta_swing_table_idx_5ga_p[1];
+		*temperature_down_a = p_rf_calibrate_info->delta_swing_table_idx_5ga_n[1];
+		*temperature_up_b   = p_rf_calibrate_info->delta_swing_table_idx_5gb_p[1];
+		*temperature_down_b = p_rf_calibrate_info->delta_swing_table_idx_5gb_n[1];
+	} else if (149 <= channel && channel <= 177)	{
+		*temperature_up_a   = p_rf_calibrate_info->delta_swing_table_idx_5ga_p[2];
+		*temperature_down_a = p_rf_calibrate_info->delta_swing_table_idx_5ga_n[2];
+		*temperature_up_b   = p_rf_calibrate_info->delta_swing_table_idx_5gb_p[2];
+		*temperature_down_b = p_rf_calibrate_info->delta_swing_table_idx_5gb_n[2];
+	}
+}
+
+
+void
+_phy_aac_calibrate_8821c(
+	struct PHY_DM_STRUCT	*p_dm_odm
+	)
+{
+	u32 cnt = 0;
+
+	ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[AACK]AACK start!!!!!!!\n"));
+	odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0xb8, bRFRegOffsetMask, 0x80a00);
+	odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0xb0, bRFRegOffsetMask, 0xff0fa);
+	ODM_delay_ms(10);
+	odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0xca, bRFRegOffsetMask, 0x80000);
+	odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0xc9, bRFRegOffsetMask, 0x1c141);
+	for (cnt = 0; cnt < 100; cnt++) {
+		ODM_delay_ms(1);
+		if (odm_get_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0xca, 0x1000) != 0x1)
+			break;
+	}
+
+	odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0xb0, bRFRegOffsetMask, 0xff0f8);
+
+	ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[AACK]AACK end!!!!!!!\n"));
+}
+
+
+void
+_phy_lc_calibrate_8821c(
+	struct PHY_DM_STRUCT	*p_dm_odm
+)
+{
+	u32 lc_cal = 0, cnt = 0, tmp0xc00;
+
+	ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[LCK]LCK start!!!!!!!\n"));
+
+	/*RF to standby mode*/
+	tmp0xc00 = odm_read_4byte(p_dm_odm, 0xc00);
+	odm_write_4byte(p_dm_odm, 0xc00, 0x4);
+	odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x0, bRFRegOffsetMask, 0x10000);
+
+	_phy_aac_calibrate_8821c(p_dm_odm);
+
+	/*backup RF0x18*/
+	lc_cal = odm_get_rf_reg(p_dm_odm, ODM_RF_PATH_A, RF_CHNLBW, RFREGOFFSETMASK);
+	/*Start LCK*/
+	odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, RF_CHNLBW, RFREGOFFSETMASK, lc_cal | 0x08000);
+	ODM_delay_ms(50);
+
+	for (cnt = 0; cnt < 100; cnt++) {
+		if (odm_get_rf_reg(p_dm_odm, ODM_RF_PATH_A, RF_CHNLBW, 0x8000) != 0x1)
+			break;
+		ODM_delay_ms(10);
+	}
+
+	/*Recover channel number*/
+	odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, RF_CHNLBW, RFREGOFFSETMASK, lc_cal);
+	/**restore*/
+	odm_write_4byte(p_dm_odm, 0xc00, tmp0xc00);
+	odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x0, bRFRegOffsetMask, 0x3ffff);
+	ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[LCK]LCK end!!!!!!!\n"));
+}
+
+
+void
+phy_lc_calibrate_8821c(
+	void	*p_dm_void
+)
+{
+#if 1
+	struct PHY_DM_STRUCT	*p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
+	boolean	is_start_cont_tx = false, is_single_tone = false, is_carrier_suppression = false;
+	u64		start_time;
+	u64		progressing_time;
+
+
+#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
+	struct _ADAPTER		*p_adapter = p_dm_odm->adapter;
+
+#if (MP_DRIVER == 1)
+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
+	PMPT_CONTEXT	p_mpt_ctx = &(p_adapter->MptCtx);
+#else
+	PMPT_CONTEXT	p_mpt_ctx = &(p_adapter->mppriv.mpt_ctx);
+#endif
+
+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
+	is_start_cont_tx = p_mpt_ctx->bStartContTx;
+	is_single_tone = p_mpt_ctx->bSingleTone;
+	is_carrier_suppression = p_mpt_ctx->bCarrierSuppression;
+#else
+	is_start_cont_tx = p_mpt_ctx->is_start_cont_tx;
+	is_single_tone = p_mpt_ctx->is_single_tone;
+	is_carrier_suppression = p_mpt_ctx->is_carrier_suppression;
+#endif
+#endif
+#endif
+
+	if (is_start_cont_tx || is_single_tone || is_carrier_suppression) {
+		ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[LCK]continues TX ing !!! LCK return\n"));
+		return;
+	}
+
+	if (*(p_dm_odm->p_is_scan_in_process)) {
+		ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[LCK]scan is in process, bypass LCK\n"));
+		return;
+	}
+
+	start_time = odm_get_current_time(p_dm_odm);
+	p_dm_odm->rf_calibrate_info.is_lck_in_progress = true;
+	_phy_lc_calibrate_8821c(p_dm_odm);
+	p_dm_odm->rf_calibrate_info.is_lck_in_progress = false;
+	progressing_time = odm_get_progressing_time(p_dm_odm, start_time);
+	ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[LCK]LCK progressing_time = %lld\n", progressing_time));
+#endif
+}
+
+
+
+void configure_txpower_track_8821c(
+	struct _TXPWRTRACK_CFG	*p_config
+)
+{
+	p_config->swing_table_size_cck = TXSCALE_TABLE_SIZE;
+	p_config->swing_table_size_ofdm = TXSCALE_TABLE_SIZE;
+	p_config->threshold_iqk = IQK_THRESHOLD;
+	p_config->threshold_dpk = DPK_THRESHOLD;
+	p_config->average_thermal_num = AVG_THERMAL_NUM_8821C;
+	p_config->rf_path_count = MAX_PATH_NUM_8821C;
+	p_config->thermal_reg_addr = RF_T_METER_8821C;
+
+	p_config->odm_tx_pwr_track_set_pwr = odm_tx_pwr_track_set_pwr8821c;
+	p_config->do_iqk = do_iqk_8821c;
+	p_config->phy_lc_calibrate = phy_lc_calibrate_8821c;
+
+#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
+	p_config->get_delta_all_swing_table = get_delta_swing_table_8821c;
+#else
+	p_config->get_delta_swing_table = get_delta_swing_table_8821c;
+#endif
+}
+
+
+void phy_set_rf_path_switch_8821c(
+#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
+	struct PHY_DM_STRUCT		*p_dm_odm,
+#else
+	struct _ADAPTER	*p_adapter,
+#endif
+	boolean		is_main
+)
+{
+#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
+	HAL_DATA_TYPE	*p_hal_data = GET_HAL_DATA(p_adapter);
+#if (DM_ODM_SUPPORT_TYPE == ODM_CE)
+	struct PHY_DM_STRUCT		*p_dm_odm = &p_hal_data->odmpriv;
+#endif
+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
+	struct PHY_DM_STRUCT		*p_dm_odm = &p_hal_data->DM_OutSrc;
+#endif
+#endif
+	u8		ant_num = 0; /*0: ANT_1, 1: ANT_2*/
+
+	if (is_main)
+		ant_num = SWITCH_TO_ANT1; /*Main = ANT_1*/
+	else
+		ant_num = SWITCH_TO_ANT2; /*Aux = ANT_2*/
+
+	config_phydm_set_ant_path(p_dm_odm, p_dm_odm->current_rf_set_8821c, ant_num);
+
+}
+
+boolean
+_phy_query_rf_path_switch_8821c(
+#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
+	struct PHY_DM_STRUCT	*p_dm_odm
+#else
+	struct _ADAPTER	*p_adapter
+#endif
+)
+{
+#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
+	HAL_DATA_TYPE	*p_hal_data = GET_HAL_DATA(p_adapter);
+#if (DM_ODM_SUPPORT_TYPE == ODM_CE)
+	struct PHY_DM_STRUCT		*p_dm_odm = &p_hal_data->odmpriv;
+#endif
+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
+	struct PHY_DM_STRUCT		*p_dm_odm = &p_hal_data->DM_OutSrc;
+#endif
+#endif
+	u8		ant_num = 0; /*0: ANT_1, 1: ANT_2*/
+
+	ODM_delay_ms(300);
+
+	ant_num = query_phydm_current_ant_num_8821c(p_dm_odm);
+
+	if (ant_num == SWITCH_TO_ANT1)
+		return true; /*Main = ANT_1*/
+	else
+		return false; /*Aux = ANT_2*/
+
+}
+
+
+boolean phy_query_rf_path_switch_8821c(
+#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
+	struct PHY_DM_STRUCT		*p_dm_odm
+#else
+	struct _ADAPTER	*p_adapter
+#endif
+)
+{
+
+#if DISABLE_BB_RF
+	return true;
+#endif
+
+#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
+	return _phy_query_rf_path_switch_8821c(p_dm_odm);
+#else
+	return _phy_query_rf_path_switch_8821c(p_adapter);
+#endif
+}
+
+
+#endif	/* (RTL8821C_SUPPORT == 0)*/
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/rtl8821c/halphyrf_8821c.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/rtl8821c/halphyrf_8821c.h
--- linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/rtl8821c/halphyrf_8821c.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/rtl8821c/halphyrf_8821c.h	2020-04-10 16:35:06.835660954 +0300
@@ -0,0 +1,83 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
+ *
+ *
+ ******************************************************************************/
+
+#ifndef __HAL_PHY_RF_8821C_H__
+#define __HAL_PHY_RF_8821C_H__
+
+#define AVG_THERMAL_NUM_8821C	4
+#define RF_T_METER_8821C		0x42
+
+void configure_txpower_track_8821c(
+	struct _TXPWRTRACK_CFG	*p_config
+);
+
+void
+odm_tx_pwr_track_set_pwr8821c(
+	void				*p_dm_void,
+	enum pwrtrack_method	method,
+	u8				rf_path,
+	u8				channel_mapped_index
+);
+
+void
+get_delta_swing_table_8821c(
+	void		*p_dm_void,
+#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
+	u8 **temperature_up_a,
+	u8 **temperature_down_a,
+	u8 **temperature_up_b,
+	u8 **temperature_down_b,
+	u8 **temperature_up_cck_a,
+	u8 **temperature_down_cck_a,
+	u8 **temperature_up_cck_b,
+	u8 **temperature_down_cck_b
+#else
+	u8 **temperature_up_a,
+	u8 **temperature_down_a,
+	u8 **temperature_up_b,
+	u8 **temperature_down_b
+#endif
+);
+
+void
+phy_lc_calibrate_8821c(
+	void *p_dm_void
+);
+
+
+
+void phy_set_rf_path_switch_8821c(
+#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
+	struct PHY_DM_STRUCT		*p_dm_odm,
+#else
+	struct _ADAPTER	*p_adapter,
+#endif
+	boolean		is_main
+);
+
+boolean phy_query_rf_path_switch_8821c(
+#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
+	struct PHY_DM_STRUCT	*p_dm_odm,
+#else
+	struct _ADAPTER	*p_adapter
+#endif
+);
+
+#endif	/* #ifndef __HAL_PHY_RF_8821C_H__ */
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/rtl8821c/mp_precomp.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/rtl8821c/mp_precomp.h
--- linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/rtl8821c/mp_precomp.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/rtl8821c/mp_precomp.h	2020-04-10 16:35:06.835660954 +0300
@@ -0,0 +1,14 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2016 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/rtl8821c/phydm_hal_api8821c.c linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/rtl8821c/phydm_hal_api8821c.c
--- linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/rtl8821c/phydm_hal_api8821c.c	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/rtl8821c/phydm_hal_api8821c.c	2020-04-10 16:35:06.835660954 +0300
@@ -0,0 +1,1370 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2016 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+
+#include "mp_precomp.h"
+#include "../phydm_precomp.h"
+
+#if (RTL8821C_SUPPORT == 1)
+#if (PHYDM_FW_API_ENABLE_8821C == 1)
+/* ======================================================================== */
+/* These following functions can be used for PHY DM only*/
+
+u32 rega24_8821c;
+u32 rega28_8821c;
+u32 regaac_8821c;
+
+enum channel_width bw_8821c;
+u8 central_ch_8821c;
+
+__iram_odm_func__
+s8 phydm_cck_rssi_8821c(struct dm_struct *dm, u8 lna_idx, u8 vga_idx)
+{
+	s8 rx_pwr_all = 0;
+	s8 lna_gain = 0;
+	/*only use lna2/3/5/7*/
+	s8 lna_gain_table_0[8] = {22, 8, -6, -22, -31, -40, -46, -52};
+	/*only use lna4/8/C/F*/
+	s8 lna_gain_table_1[16] = {10, 6, 2, -2, -6, -10, -14, -17,
+				   -20, -24, -28, -31, -34, -37, -40, -44};
+
+	if (dm->cck_agc_report_type == 0)
+		lna_gain = lna_gain_table_0[lna_idx];
+	else
+		lna_gain = lna_gain_table_1[lna_idx];
+
+	rx_pwr_all = lna_gain - (2 * vga_idx);
+
+	return rx_pwr_all;
+}
+
+__iram_odm_func__
+boolean
+phydm_rfe_8821c(struct dm_struct *dm, u8 channel)
+{
+#if 0
+	/* Efuse is not wrote now */
+	/* Need to check RFE type finally */
+	/*if (dm->rfe_type == 1) {*/
+	if (channel <= 14) {
+		/* signal source */
+		odm_set_bb_reg(dm, R_0xcb0, (MASKBYTE2 | MASKLWORD), 0x704570);
+		odm_set_bb_reg(dm, R_0xeb0, (MASKBYTE2 | MASKLWORD), 0x704570);
+		odm_set_bb_reg(dm, R_0xcb4, MASKBYTE1, 0x45);
+		odm_set_bb_reg(dm, R_0xeb4, MASKBYTE1, 0x45);
+	} else if (channel > 35) {
+		odm_set_bb_reg(dm, R_0xcb0, (MASKBYTE2 | MASKLWORD), 0x174517);
+		odm_set_bb_reg(dm, R_0xeb0, (MASKBYTE2 | MASKLWORD), 0x174517);
+		odm_set_bb_reg(dm, R_0xcb4, MASKBYTE1, 0x45);
+		odm_set_bb_reg(dm, R_0xeb4, MASKBYTE1, 0x45);
+	} else
+		return false;
+
+	/* chip top mux */
+	odm_set_bb_reg(dm, R_0x64, BIT(29) | BIT(28), 0x3);
+	odm_set_bb_reg(dm, R_0x4c, BIT(26) | BIT(25), 0x0);
+	odm_set_bb_reg(dm, R_0x40, BIT(2), 0x1);
+
+	/* from s0 or s1 */
+	odm_set_bb_reg(dm, R_0x1990, (BIT(5) | BIT(4) | BIT(3) | BIT(2) | BIT(1) | BIT(0)), 0x30);
+	odm_set_bb_reg(dm, R_0x1990, (BIT(11) | BIT(10)), 0x3);
+
+	/* input or output */
+	odm_set_bb_reg(dm, R_0x974, (BIT(5) | BIT(4) | BIT(3) | BIT(2) | BIT(1) | BIT(0)), 0x3f);
+	odm_set_bb_reg(dm, R_0x974, (BIT(11) | BIT(10)), 0x3);
+
+	/* delay 400ns for PAPE */
+	odm_set_bb_reg(dm, R_0x810, MASKBYTE3 | BIT(20) | BIT(21) | BIT(22) | BIT(23), 0x211);
+
+	/* antenna switch table */
+	odm_set_bb_reg(dm, R_0xca0, MASKLWORD, 0xa555);
+	odm_set_bb_reg(dm, R_0xea0, MASKLWORD, 0xa555);
+
+	/* inverse or not */
+	odm_set_bb_reg(dm, R_0xcbc, (BIT(5) | BIT(4) | BIT(3) | BIT(2) | BIT(1) | BIT(0)), 0x0);
+	odm_set_bb_reg(dm, R_0xcbc, (BIT(11) | BIT(10)), 0x0);
+	odm_set_bb_reg(dm, R_0xebc, (BIT(5) | BIT(4) | BIT(3) | BIT(2) | BIT(1) | BIT(0)), 0x0);
+	odm_set_bb_reg(dm, R_0xebc, (BIT(11) | BIT(10)), 0x0);
+	/*}*/
+#endif
+	return true;
+}
+
+__iram_odm_func__
+void phydm_ccapar_8821c(struct dm_struct *dm)
+{
+#if 0
+	u32	cca_ifem[9][4] = {
+		/*20M*/
+		{0x75D97010, 0x75D97010, 0x75D97010, 0x75D97010}, /*Reg82C*/
+		{0x00000000, 0x00000000, 0x00000000, 0x00000000}, /*Reg830*/
+		{0x00000000, 0x00000000, 0x00000000, 0x00000000}, /*Reg838*/
+		/*40M*/
+		{0x75D97010, 0x75D97010, 0x75D97010, 0x75D97010}, /*Reg82C*/
+		{0x00000000, 0x79a0ea28, 0x00000000, 0x79a0ea28}, /*Reg830*/
+		{0x87765541, 0x87766341, 0x87765541, 0x87766341}, /*Reg838*/
+		/*80M*/
+		{0x75D97010, 0x75D97010, 0x75D97010, 0x75D97010}, /*Reg82C*/
+		{0x00000000, 0x00000000, 0x00000000, 0x00000000}, /*Reg830*/
+		{0x00000000, 0x87746641, 0x00000000, 0x87746641}
+	}; /*Reg838*/
+
+	u32	cca_efem[9][4] = {
+		/*20M*/
+		{0x75A76010, 0x75A76010, 0x75A76010, 0x75A75010}, /*Reg82C*/
+		{0x00000000, 0x00000000, 0x00000000, 0x00000000}, /*Reg830*/
+		{0x87766651, 0x87766431, 0x87766451, 0x87766431}, /*Reg838*/
+		/*40M*/
+		{0x75A75010, 0x75A75010, 0x75A75010, 0x75A75010}, /*Reg82C*/
+		{0x00000000, 0x00000000, 0x00000000, 0x00000000}, /*Reg830*/
+		{0x87766431, 0x87766431, 0x87766431, 0x87766431}, /*Reg838*/
+		/*80M*/
+		{0x75BA7010, 0x75BA7010, 0x75BA7010, 0x75BA7010}, /*Reg82C*/
+		{0x00000000, 0x00000000, 0x00000000, 0x00000000}, /*Reg830*/
+		{0x87766431, 0x87766431, 0x87766431, 0x87766431}
+	}; /*Reg838*/
+
+	u8	row, col;
+	u32	reg82c, reg830, reg838;
+
+	if (dm->cut_version != ODM_CUT_B)
+		return;
+
+	if (bw_8821c == CHANNEL_WIDTH_20)
+		row = 0;
+	else if (bw_8821c == CHANNEL_WIDTH_40)
+		row = 3;
+	else
+		row = 6;
+
+	if (central_ch_8821c <= 14) {
+		if (dm->rx_ant_status == BB_PATH_A || dm->rx_ant_status == BB_PATH_B)
+			col = 0;
+		else
+			col = 1;
+	} else {
+		if (dm->rx_ant_status == BB_PATH_A || dm->rx_ant_status == BB_PATH_B)
+			col = 2;
+		else
+			col = 3;
+	}
+
+	if (dm->rfe_type == 0) {/*iFEM*/
+		reg82c = (cca_ifem[row][col] != 0) ? cca_ifem[row][col] : reg82c_8821c;
+		reg830 = (cca_ifem[row + 1][col] != 0) ? cca_ifem[row + 1][col] : reg830_8821c;
+		reg838 = (cca_ifem[row + 2][col] != 0) ? cca_ifem[row + 2][col] : reg838_8821c;
+	} else {/*eFEM*/
+		reg82c = (cca_efem[row][col] != 0) ? cca_efem[row][col] : reg82c_8821c;
+		reg830 = (cca_efem[row + 1][col] != 0) ? cca_efem[row + 1][col] : reg830_8821c;
+		reg838 = (cca_efem[row + 2][col] != 0) ? cca_efem[row + 2][col] : reg838_8821c;
+	}
+
+	odm_set_bb_reg(dm, R_0x82c, MASKDWORD, reg82c);
+	odm_set_bb_reg(dm, R_0x830, MASKDWORD, reg830);
+	odm_set_bb_reg(dm, R_0x838, MASKDWORD, reg838);
+
+	PHYDM_DBG(dm, ODM_PHY_CONFIG,
+		  "[%s]: Update CCA parameters for Bcut (Pkt%d, Intf%d, RFE%d), row = %d, col = %d\n",
+		  __func__, dm->package_type, dm->support_interface,
+		  dm->rfe_type, row, col);
+#endif
+}
+
+__iram_odm_func__
+void phydm_ccapar_by_bw_8821c(struct dm_struct *dm,
+			      enum channel_width bandwidth)
+{
+#if 0
+	u32		reg82c;
+
+
+	if (dm->cut_version != ODM_CUT_A)
+		return;
+
+	/* A-cut */
+	reg82c = odm_get_bb_reg(dm, R_0x82c, MASKDWORD);
+
+	if (bandwidth == CHANNEL_WIDTH_20) {
+		/* 82c[15:12] = 4 */
+		/* 82c[27:24] = 6 */
+
+		reg82c &= (~(0x0f00f000));
+		reg82c |= ((0x4) << 12);
+		reg82c |= ((0x6) << 24);
+	} else if (bandwidth == CHANNEL_WIDTH_40) {
+		/* 82c[19:16] = 9 */
+		/* 82c[27:24] = 6 */
+
+		reg82c &= (~(0x0f0f0000));
+		reg82c |= ((0x9) << 16);
+		reg82c |= ((0x6) << 24);
+	} else if (bandwidth == CHANNEL_WIDTH_80) {
+		/* 82c[15:12] 7 */
+		/* 82c[19:16] b */
+		/* 82c[23:20] d */
+		/* 82c[27:24] 3 */
+
+		reg82c &= (~(0x0ffff000));
+		reg82c |= ((0xdb7) << 12);
+		reg82c |= ((0x3) << 24);
+	}
+
+	odm_set_bb_reg(dm, R_0x82c, MASKDWORD, reg82c);
+	PHYDM_DBG(dm, ODM_PHY_CONFIG, "[%s]: Update CCA parameters for Acut\n",
+		  __func__);
+#endif
+}
+
+__iram_odm_func__
+void phydm_ccapar_by_rxpath_8821c(struct dm_struct *dm)
+{
+#if 0
+	if (dm->cut_version != ODM_CUT_A)
+		return;
+
+	if (dm->rx_ant_status == BB_PATH_A || dm->rx_ant_status == BB_PATH_B) {
+		/* 838[7:4] = 8 */
+		/* 838[11:8] = 7 */
+		/* 838[15:12] = 6 */
+		/* 838[19:16] = 7 */
+		/* 838[23:20] = 7 */
+		/* 838[27:24] = 7 */
+		odm_set_bb_reg(dm, R_0x838, 0x0ffffff0, 0x777678);
+	} else {
+		/* 838[7:4] = 3 */
+		/* 838[11:8] = 3 */
+		/* 838[15:12] = 6 */
+		/* 838[19:16] = 6 */
+		/* 838[23:20] = 7 */
+		/* 838[27:24] = 7 */
+		odm_set_bb_reg(dm, R_0x838, 0x0ffffff0, 0x776633);
+	}
+	PHYDM_DBG(dm, ODM_PHY_CONFIG, "[%s]: Update CCA parameters for Acut\n",
+		  __func__);
+#endif
+}
+
+__iram_odm_func__
+void phydm_rxdfirpar_by_bw_8821c(struct dm_struct *dm,
+				 enum channel_width bandwidth)
+{
+	if (bandwidth == CHANNEL_WIDTH_40) {
+		/* RX DFIR for BW40 */
+		odm_set_bb_reg(dm, R_0x948, BIT(29) | BIT(28), 0x2);
+		odm_set_bb_reg(dm, R_0x94c, BIT(29) | BIT(28), 0x2);
+		odm_set_bb_reg(dm, R_0xc20, BIT(31), 0x0);
+		odm_set_bb_reg(dm, R_0x8f0, BIT(31), 0x0);
+	} else if (bandwidth == CHANNEL_WIDTH_80) {
+		/* RX DFIR for BW80 */
+		odm_set_bb_reg(dm, R_0x948, BIT(29) | BIT(28), 0x2);
+		odm_set_bb_reg(dm, R_0x94c, BIT(29) | BIT(28), 0x1);
+		odm_set_bb_reg(dm, R_0xc20, BIT(31), 0x0);
+		odm_set_bb_reg(dm, R_0x8f0, BIT(31), 0x1);
+	} else {
+		/* RX DFIR for BW20, BW10 and BW5*/
+		odm_set_bb_reg(dm, R_0x948, BIT(29) | BIT(28), 0x2);
+		odm_set_bb_reg(dm, R_0x94c, BIT(29) | BIT(28), 0x2);
+		odm_set_bb_reg(dm, R_0xc20, BIT(31), 0x1);
+		odm_set_bb_reg(dm, R_0x8f0, BIT(31), 0x0);
+	}
+	/* PHYDM_DBG(dm, ODM_PHY_CONFIG, "phydm_rxdfirpar_by_bw_8821c\n");*/
+}
+
+__iram_odm_func__
+boolean
+phydm_write_txagc_1byte_8821c(struct dm_struct *dm, u32 power_index,
+			      enum rf_path path, u8 hw_rate)
+{
+#if (PHYDM_FW_API_FUNC_ENABLE_8821C == 1)
+	u32 offset_txagc[2] = {0x1d00, 0x1d80};
+	u8 rate_idx = (hw_rate & 0xfc), i;
+	u8 rate_offset = (hw_rate & 0x3);
+	u32 txagc_content = 0x0;
+
+	/* For debug command only!!!! */
+
+	/* Error handling */
+	if (path > RF_PATH_A || hw_rate > 0x53) {
+		PHYDM_DBG(dm, ODM_PHY_CONFIG, "[%s]: unsupported path (%d)\n",
+			  __func__, path);
+		return false;
+	}
+
+#if 1
+	/* For HW limitation, We can't write TXAGC once a byte. */
+	for (i = 0; i < 4; i++) {
+		if (i != rate_offset)
+			txagc_content = txagc_content | (config_phydm_read_txagc_8821c(dm, path, rate_idx + i) << (i << 3));
+		else
+			txagc_content = txagc_content | ((power_index & 0x3f) << (i << 3));
+	}
+	odm_set_bb_reg(dm, (offset_txagc[path] + rate_idx), MASKDWORD, txagc_content);
+#else
+	odm_write_1byte(dm, (offset_txagc[path] + hw_rate), (power_index & 0x3f));
+#endif
+
+	PHYDM_DBG(dm, ODM_PHY_CONFIG,
+		  "[%s]: path-%d rate index 0x%x (0x%x) = 0x%x\n", __func__,
+		  path, hw_rate, (offset_txagc[path] + hw_rate), power_index);
+	return true;
+#else
+	return false;
+#endif
+}
+
+__iram_odm_func__
+void phydm_init_hw_info_by_rfe_type_8821c(struct dm_struct *dm)
+{
+#if (PHYDM_FW_API_FUNC_ENABLE_8821C == 1)
+	dm->is_init_hw_info_by_rfe = false;
+	/*
+	 * Let original variable rfe_type to be rfe_type_8821c.
+	 * Varible rfe_type as symbol is used to identify PHY parameter.
+	 */
+	dm->rfe_type = dm->rfe_type_expand >> 3;
+
+	/*2.4G default rf set with wlg or btg*/
+	if (dm->rfe_type_expand == 2 || dm->rfe_type_expand == 4 || dm->rfe_type_expand == 7) {
+		dm->default_rf_set_8821c = SWITCH_TO_BTG;
+	} else if (dm->rfe_type_expand == 0 || dm->rfe_type_expand == 1 ||
+		 dm->rfe_type_expand == 3 || dm->rfe_type_expand == 5 ||
+		 dm->rfe_type_expand == 6) {
+		dm->default_rf_set_8821c = SWITCH_TO_WLG;
+	} else if (dm->rfe_type_expand == 0x22 || dm->rfe_type_expand == 0x24 ||
+		 dm->rfe_type_expand == 0x27 || dm->rfe_type_expand == 0x2a ||
+		 dm->rfe_type_expand == 0x2c || dm->rfe_type_expand == 0x2f) {
+		dm->default_rf_set_8821c = SWITCH_TO_BTG;
+		odm_cmn_info_init(dm, ODM_CMNINFO_PACKAGE_TYPE, 1);
+	} else if (dm->rfe_type_expand == 0x20 || dm->rfe_type_expand == 0x21 ||
+		   dm->rfe_type_expand == 0x23 || dm->rfe_type_expand == 0x25 ||
+		   dm->rfe_type_expand == 0x26 || dm->rfe_type_expand == 0x28 ||
+		   dm->rfe_type_expand == 0x29 || dm->rfe_type_expand == 0x2b ||
+		   dm->rfe_type_expand == 0x2d || dm->rfe_type_expand == 0x2e) {
+		dm->default_rf_set_8821c = SWITCH_TO_WLG;
+		odm_cmn_info_init(dm, ODM_CMNINFO_PACKAGE_TYPE, 1);
+	}
+
+	if (dm->rfe_type_expand == 3 || dm->rfe_type_expand == 4 ||
+	    dm->rfe_type_expand == 0x23 || dm->rfe_type_expand == 0x24 ||
+	    dm->rfe_type_expand == 0x2b || dm->rfe_type_expand == 0x2c)
+		dm->default_ant_num_8821c = SWITCH_TO_ANT2;
+	else
+		dm->default_ant_num_8821c = SWITCH_TO_ANT1;
+
+	dm->is_init_hw_info_by_rfe = true;
+	PHYDM_DBG(dm, ODM_PHY_CONFIG, "%s: RFE type (%d), rf set (%s)\n",
+		  __FUNCTION__, dm->rfe_type_expand,
+		  dm->default_rf_set_8821c == 0 ? "BTG" : "WLG");
+#endif
+}
+
+__iram_odm_func__
+void phydm_set_gnt_state_8821c(struct dm_struct *dm, boolean gnt_wl_state,
+			       boolean gnt_bt_state)
+{
+#if (PHYDM_FW_API_FUNC_ENABLE_8821C == 1)
+	u32 gnt_val = 0;
+
+	odm_set_bb_reg(dm, R_0x70, BIT(26), 0x1);
+
+	if (gnt_wl_state)
+		gnt_val = 0x3300;
+	else
+		gnt_val = 0x1100;
+
+	if (gnt_bt_state)
+		gnt_val = gnt_val | 0xcc00;
+	else
+		gnt_val = gnt_val | 0x4400;
+
+	odm_set_bb_reg(dm, R_0x1704, MASKLWORD, gnt_val);
+	ODM_delay_us(50); /*waiting before access 0x1700 */
+	odm_set_bb_reg(dm, R_0x1700, MASKDWORD, 0xc00f0038);
+#endif
+}
+/* ======================================================================== */
+
+/* ======================================================================== */
+/* These following functions can be used by driver*/
+
+__iram_odm_func__
+u32 config_phydm_read_rf_reg_8821c(struct dm_struct *dm, enum rf_path path,
+				   u32 reg_addr, u32 bit_mask)
+{
+	u32 readback_value, direct_addr;
+	u32 offset_read_rf[2] = {0x2800, 0x2c00};
+
+	/* Error handling.*/
+	if (path > RF_PATH_A) {
+		PHYDM_DBG(dm, ODM_PHY_CONFIG, "[%s]: unsupported path (%d)\n",
+			  __func__, path);
+		return INVALID_RF_DATA;
+	}
+
+	/* Calculate offset */
+	reg_addr &= 0xff;
+	direct_addr = offset_read_rf[path] + (reg_addr << 2);
+
+	/* RF register only has 20bits */
+	bit_mask &= RFREGOFFSETMASK;
+
+	/* Read RF register directly */
+	readback_value = odm_get_bb_reg(dm, direct_addr, bit_mask);
+	PHYDM_DBG(dm, ODM_PHY_CONFIG,
+		  "[%s]: RF-%d 0x%x = 0x%x, bit mask = 0x%x\n", __func__, path,
+		  reg_addr, readback_value, bit_mask);
+	return readback_value;
+}
+
+__iram_odm_func__
+boolean
+config_phydm_write_rf_reg_8821c(struct dm_struct *dm, enum rf_path path,
+				u32 reg_addr, u32 bit_mask, u32 data)
+{
+	u32 data_and_addr = 0, data_original = 0;
+	u32 offset_write_rf[2] = {0xc90, 0xe90};
+	u8 bit_shift;
+
+	/* Error handling.*/
+	if (path > RF_PATH_A) {
+		PHYDM_DBG(dm, ODM_PHY_CONFIG, "[%s]: unsupported path (%d)\n",
+			  __func__, path);
+		return false;
+	}
+
+	/* Read RF register content first */
+	reg_addr &= 0xff;
+	bit_mask = bit_mask & RFREGOFFSETMASK;
+
+	if (bit_mask != RFREGOFFSETMASK) {
+		data_original = config_phydm_read_rf_reg_8821c(dm, path, reg_addr, RFREGOFFSETMASK);
+
+		/* Error handling. RF is disabled */
+		if (config_phydm_read_rf_check_8821c(data_original) == false) {
+			PHYDM_DBG(dm, ODM_PHY_CONFIG,
+				  "[%s]: Write fail, RF is disable\n",
+				  __func__);
+			return false;
+		}
+
+		/* check bit mask */
+		if (bit_mask != 0xfffff) {
+			for (bit_shift = 0; bit_shift <= 19; bit_shift++) {
+				if (((bit_mask >> bit_shift) & 0x1) == 1)
+					break;
+			}
+			data = ((data_original) & (~bit_mask)) | (data << bit_shift);
+		}
+	}
+
+	/* Put write addr in [27:20]  and write data in [19:00] */
+	data_and_addr = ((reg_addr << 20) | (data & 0x000fffff)) & 0x0fffffff;
+
+	/* Write operation */
+	odm_set_bb_reg(dm, offset_write_rf[path], MASKDWORD, data_and_addr);
+	PHYDM_DBG(dm, ODM_PHY_CONFIG,
+		  "[%s]: RF-%d 0x%x = 0x%x (original: 0x%x), bit mask = 0x%x\n",
+		  __func__, path, reg_addr, data, data_original, bit_mask);
+
+#if (defined(CONFIG_RUN_IN_DRV))
+	if (dm->support_interface == ODM_ITRF_PCIE)
+		ODM_delay_us(13);
+#elif (defined(CONFIG_RUN_IN_FW))
+	ODM_delay_us(13);
+#endif
+
+	return true;
+}
+
+__iram_odm_func__
+boolean
+config_phydm_write_txagc_8821c(struct dm_struct *dm, u32 power_index,
+			       enum rf_path path, u8 hw_rate)
+{
+#if (PHYDM_FW_API_FUNC_ENABLE_8821C == 1)
+	u32 offset_txagc[2] = {0x1d00, 0x1d80};
+	u8 rate_idx = (hw_rate & 0xfc);
+
+	/* Input need to be HW rate index, not driver rate index!!!! */
+
+	if (dm->is_disable_phy_api) {
+		PHYDM_DBG(dm, ODM_PHY_CONFIG,
+			  "[%s]: disable PHY API for debug!!\n", __func__);
+		return true;
+	}
+
+	/* Error handling */
+	if (path > RF_PATH_A || hw_rate > 0x53) {
+		PHYDM_DBG(dm, ODM_PHY_CONFIG, "[%s]: unsupported path (%d)\n",
+			  __func__, path);
+		return false;
+	}
+
+	/* driver need to construct a 4-byte power index */
+	odm_set_bb_reg(dm, (offset_txagc[path] + rate_idx), MASKDWORD, power_index);
+
+	PHYDM_DBG(dm, ODM_PHY_CONFIG,
+		  "[%s]: path-%d rate index 0x%x (0x%x) = 0x%x\n", __func__,
+		  path, hw_rate, (offset_txagc[path] + hw_rate), power_index);
+	return true;
+#else
+	return false;
+#endif
+}
+
+__iram_odm_func__
+u8 config_phydm_read_txagc_8821c(struct dm_struct *dm, enum rf_path path,
+				 u8 hw_rate)
+{
+#if (PHYDM_FW_API_FUNC_ENABLE_8821C == 1)
+	u8 read_back_data;
+
+	/* Input need to be HW rate index, not driver rate index!!!! */
+
+	/* Error handling */
+	if (path > RF_PATH_A || hw_rate > 0x53) {
+		PHYDM_DBG(dm, ODM_PHY_CONFIG, "[%s]: unsupported path (%d)\n",
+			  __func__, path);
+		return INVALID_TXAGC_DATA;
+	}
+
+	/* Disable TX AGC report */
+	odm_set_bb_reg(dm, R_0x1998, BIT(16), 0x0); /* need to check */
+
+	/* Set data rate index (bit0~6) and path index (bit7) */
+	odm_set_bb_reg(dm, R_0x1998, MASKBYTE0, (hw_rate | (path << 7)));
+
+	/* Enable TXAGC report */
+	odm_set_bb_reg(dm, R_0x1998, BIT(16), 0x1);
+
+	/* Read TX AGC report */
+	read_back_data = (u8)odm_get_bb_reg(dm, R_0xd30, 0x7f0000);
+
+	/* Driver have to disable TXAGC report after reading TXAGC (ref. user guide v11) */
+	odm_set_bb_reg(dm, R_0x1998, BIT(16), 0x0);
+
+	PHYDM_DBG(dm, ODM_PHY_CONFIG, "[%s]: path-%d rate index 0x%x = 0x%x\n",
+		  __func__, path, hw_rate, read_back_data);
+	return read_back_data;
+#else
+	return 0;
+#endif
+}
+
+__iram_odm_func__
+boolean
+config_phydm_switch_band_8821c(struct dm_struct *dm, u8 central_ch)
+{
+	u32 rf_reg18;
+	boolean rf_reg_status = true;
+
+	PHYDM_DBG(dm, ODM_PHY_CONFIG, "[%s]======================>\n",
+		  __func__);
+
+	if (dm->is_disable_phy_api) {
+		PHYDM_DBG(dm, ODM_PHY_CONFIG,
+			  "[%s]: disable PHY API for debug!!\n", __func__);
+		return true;
+	}
+
+	rf_reg18 = config_phydm_read_rf_reg_8821c(dm, RF_PATH_A, 0x18, RFREGOFFSETMASK);
+	rf_reg_status = rf_reg_status & config_phydm_read_rf_check_8821c(rf_reg18);
+
+	if (central_ch <= 14) {
+		/* 2.4G */
+
+		/* Enable CCK block */
+		odm_set_bb_reg(dm, R_0x808, BIT(28), 0x1);
+
+		/* Disable MAC CCK check */
+		odm_set_bb_reg(dm, R_0x454, BIT(7), 0x0);
+
+		/* Disable BB CCK check */
+		odm_set_bb_reg(dm, R_0xa80, BIT(18), 0x0);
+
+		/*CCA Mask*/
+		odm_set_bb_reg(dm, R_0x814, 0x0000FC00, 15); /*default value*/
+
+		/* RF band */
+		rf_reg18 = (rf_reg18 & (~(BIT(16) | BIT(9) | BIT(8))));
+#if (PHYDM_FW_API_FUNC_ENABLE_8821C == 1)
+		/* Switch WLG/BTG*/
+		if (dm->default_rf_set_8821c == SWITCH_TO_BTG)
+			config_phydm_switch_rf_set_8821c(dm, SWITCH_TO_BTG);
+		else if (dm->default_rf_set_8821c == SWITCH_TO_WLG)
+			config_phydm_switch_rf_set_8821c(dm, SWITCH_TO_WLG);
+#endif
+		/*RF TXA_TANK LUT mode*/
+		odm_set_rf_reg(dm, RF_PATH_A, RF_0xdf, BIT(6), 0x1);
+
+		/*RF TXA_PA_TANK*/
+		odm_set_rf_reg(dm, RF_PATH_A, RF_0x64, 0x0000f, 0xf);
+
+	} else if (central_ch > 35) {
+		/* 5G */
+
+		/* Enable BB CCK check */
+		odm_set_bb_reg(dm, R_0xa80, BIT(18), 0x1);
+
+		/* Enable CCK check */
+		odm_set_bb_reg(dm, R_0x454, BIT(7), 0x1);
+
+		/* Disable CCK block */
+		odm_set_bb_reg(dm, R_0x808, BIT(28), 0x0);
+
+		/*CCA Mask*/
+		odm_set_bb_reg(dm, R_0x814, 0x0000FC00, 15); /*default value*/
+		/*odm_set_bb_reg(dm, R_0x814, 0x0000FC00, 34); CCA mask = 13.6us*/
+
+		/* RF band */
+		rf_reg18 = (rf_reg18 & (~(BIT(16) | BIT(9) | BIT(8))));
+		rf_reg18 = (rf_reg18 | BIT(8) | BIT(16));
+#if (PHYDM_FW_API_FUNC_ENABLE_8821C == 1)
+		/* Switch WLA */
+		config_phydm_switch_rf_set_8821c(dm, SWITCH_TO_WLA);
+#endif
+		/*RF TXA_TANK LUT mode*/
+		odm_set_rf_reg(dm, RF_PATH_A, RF_0xdf, BIT(6), 0x0);
+
+	} else {
+		PHYDM_DBG(dm, ODM_PHY_CONFIG,
+			  "[%s]: Fail to switch band (ch: %d)\n", __func__,
+			  central_ch);
+		return false;
+	}
+
+	odm_set_rf_reg(dm, RF_PATH_A, RF_0x18, RFREGOFFSETMASK, rf_reg18);
+
+	if (phydm_rfe_8821c(dm, central_ch) == false)
+		return false;
+
+	if (!rf_reg_status) {
+		PHYDM_DBG(dm, ODM_PHY_CONFIG,
+			  "[%s]: Fail to switch band (ch: %d), because writing RF register is fail\n",
+			  __func__, central_ch);
+		return false;
+	}
+
+	PHYDM_DBG(dm, ODM_PHY_CONFIG, "[%s]: Success to switch band (ch: %d)\n",
+		  __func__, central_ch);
+	return true;
+}
+
+__iram_odm_func__
+boolean
+config_phydm_switch_channel_8821c(struct dm_struct *dm, u8 central_ch)
+{
+	struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
+	u32 rf_reg18, rf_reg_b8 = 0;
+	boolean rf_reg_status = true;
+
+	PHYDM_DBG(dm, ODM_PHY_CONFIG, "[%s]====================>\n", __func__);
+
+	if (dm->is_disable_phy_api) {
+		PHYDM_DBG(dm, ODM_PHY_CONFIG,
+			  "[%s]: disable PHY API for debug!!\n", __func__);
+		return true;
+	}
+
+	central_ch_8821c = central_ch;
+	rf_reg18 = config_phydm_read_rf_reg_8821c(dm, RF_PATH_A, 0x18, RFREGOFFSETMASK);
+	rf_reg_status = rf_reg_status & config_phydm_read_rf_check_8821c(rf_reg18);
+
+	if (dm->cut_version == ODM_CUT_A) {
+		rf_reg_b8 = config_phydm_read_rf_reg_8821c(dm, RF_PATH_A, 0xb8, RFREGOFFSETMASK);
+		rf_reg_status = rf_reg_status & config_phydm_read_rf_check_8821c(rf_reg_b8);
+	}
+
+	/* Switch band and channel */
+	if (central_ch <= 14) {
+		/* 2.4G */
+
+		/* 1. RF band and channel*/
+		rf_reg18 = (rf_reg18 & (~(BIT(18) | BIT(17) | MASKBYTE0)));
+		rf_reg18 = (rf_reg18 | central_ch);
+
+		/* 2. AGC table selection */
+		odm_set_bb_reg(dm, R_0xc1c, 0x00000F00, 0x0);
+		dig_t->agc_table_idx = 0x0;
+
+		/* 3. Set central frequency for clock offset tracking */
+		odm_set_bb_reg(dm, R_0x860, 0x1ffe0000, 0x96a);
+
+		/* Fix A-cut LCK fail issue @ 5285MHz~5375MHz, 0xb8[19]=0x0 */
+		if (dm->cut_version == ODM_CUT_A)
+			rf_reg_b8 = rf_reg_b8 | BIT(19);
+
+		/* CCK TX filter parameters */
+		if (central_ch == 14) {
+			odm_set_bb_reg(dm, R_0xa24, MASKDWORD, 0x0000b81c);
+			odm_set_bb_reg(dm, R_0xa28, MASKLWORD, 0x0000);
+			odm_set_bb_reg(dm, R_0xaac, MASKDWORD, 0x00003667);
+		} else {
+			odm_set_bb_reg(dm, R_0xa24, MASKDWORD, rega24_8821c);
+			odm_set_bb_reg(dm, R_0xa28, MASKLWORD, (rega28_8821c & MASKLWORD));
+			odm_set_bb_reg(dm, R_0xaac, MASKDWORD, regaac_8821c);
+		}
+
+	} else if (central_ch > 35) {
+		/* 5G */
+
+		/* 1. RF band and channel*/
+		rf_reg18 = (rf_reg18 & (~(BIT(18) | BIT(17) | MASKBYTE0)));
+		rf_reg18 = (rf_reg18 | central_ch);
+
+		if (central_ch >= 36 && central_ch <= 64) {
+			;
+		} else if ((central_ch >= 100) && (central_ch <= 140)) {
+			rf_reg18 = (rf_reg18 | BIT(17));
+		} else if (central_ch > 140) {
+			rf_reg18 = (rf_reg18 | BIT(18));
+		} else {
+			PHYDM_DBG(dm, ODM_PHY_CONFIG,
+				  "[%s]: Fail to switch channel (RF18) (ch: %d)\n",
+				  __func__, central_ch);
+			return false;
+		}
+
+		/* 2. AGC table selection */
+		if (central_ch >= 36 && central_ch <= 64) {
+			odm_set_bb_reg(dm, R_0xc1c, 0x00000F00, 0x1);
+			dig_t->agc_table_idx = 0x1;
+		} else if ((central_ch >= 100) && (central_ch <= 144)) {
+			odm_set_bb_reg(dm, R_0xc1c, 0x00000F00, 0x2);
+			dig_t->agc_table_idx = 0x2;
+		} else if (central_ch >= 149) {
+			odm_set_bb_reg(dm, R_0xc1c, 0x00000F00, 0x3);
+			dig_t->agc_table_idx = 0x3;
+		} else {
+			PHYDM_DBG(dm, ODM_PHY_CONFIG,
+				  "[%s]: Fail to switch channel (AGC) (ch: %d)\n",
+				  __func__, central_ch);
+			return false;
+		}
+
+		/* 3. Set central frequency for clock offset tracking */
+		if (central_ch >= 36 && central_ch <= 48) {
+			odm_set_bb_reg(dm, R_0x860, 0x1ffe0000, 0x494);
+		} else if ((central_ch >= 52) && (central_ch <= 64)) {
+			odm_set_bb_reg(dm, R_0x860, 0x1ffe0000, 0x453);
+		} else if ((central_ch >= 100) && (central_ch <= 116)) {
+			odm_set_bb_reg(dm, R_0x860, 0x1ffe0000, 0x452);
+		} else if ((central_ch >= 118) && (central_ch <= 177)) {
+			odm_set_bb_reg(dm, R_0x860, 0x1ffe0000, 0x412);
+		} else {
+			PHYDM_DBG(dm, ODM_PHY_CONFIG,
+				  "[%s]: Fail to switch channel (fc_area) (ch: %d)\n",
+				  __func__, central_ch);
+			return false;
+		}
+
+		/* Fix A-cut LCK fail issue @ 5285MHz~5375MHz, 0xb8[19]=0x0 */
+		if (dm->cut_version == ODM_CUT_A) {
+			if (central_ch >= 57 && central_ch <= 75)
+				rf_reg_b8 = rf_reg_b8 & (~BIT(19));
+			else
+				rf_reg_b8 = rf_reg_b8 | BIT(19);
+		}
+
+#if (PHYDM_FW_API_FUNC_ENABLE_8821C == 1)
+		/*notch 5760 spur by CSI_MASK*/
+		if (central_ch == 153)
+			phydm_csi_mask_setting(dm, FUNC_ENABLE, (u32)central_ch, 20, 5760, PHYDM_DONT_CARE);
+		else if (central_ch == 151)
+			phydm_csi_mask_setting(dm, FUNC_ENABLE, (u32)central_ch, 40, 5760, PHYDM_DONT_CARE);
+		else if (central_ch == 155)
+			phydm_csi_mask_setting(dm, FUNC_ENABLE, (u32)central_ch, 80, 5760, PHYDM_DONT_CARE);
+		else
+			phydm_csi_mask_setting(dm, FUNC_DISABLE, (u32)central_ch, 80, 5760, PHYDM_DONT_CARE);
+#endif
+
+	} else {
+		PHYDM_DBG(dm, ODM_PHY_CONFIG,
+			  "[%s]: Fail to switch band (ch: %d)\n", __func__,
+			  central_ch);
+		return false;
+	}
+
+	odm_set_rf_reg(dm, RF_PATH_A, RF_0x18, RFREGOFFSETMASK, rf_reg18);
+
+	if (dm->cut_version == ODM_CUT_A)
+		odm_set_rf_reg(dm, RF_PATH_A, RF_0xb8, RFREGOFFSETMASK, rf_reg_b8);
+
+	if (!rf_reg_status) {
+		PHYDM_DBG(dm, ODM_PHY_CONFIG,
+			  "[%s]: Fail to switch channel (ch: %d), because writing RF register is fail\n",
+			  __func__, central_ch);
+		return false;
+	}
+
+	phydm_ccapar_8821c(dm);
+	PHYDM_DBG(dm, ODM_PHY_CONFIG,
+		  "[%s]: Success to switch channel (ch: %d)\n", __func__,
+		  central_ch);
+	return true;
+}
+
+__iram_odm_func__
+boolean
+config_phydm_switch_bandwidth_8821c(struct dm_struct *dm, u8 primary_ch_idx,
+				    enum channel_width bandwidth)
+{
+	u32 rf_reg18;
+	boolean rf_reg_status = true;
+	u32 bb_reg8ac;
+
+	PHYDM_DBG(dm, ODM_PHY_CONFIG, "[%s]===================>\n", __func__);
+
+	if (dm->is_disable_phy_api) {
+		PHYDM_DBG(dm, ODM_PHY_CONFIG,
+			  "[%s]: disable PHY API for debug!!\n", __func__);
+		return true;
+	}
+
+	/* Error handling */
+	if (bandwidth >= CHANNEL_WIDTH_MAX || (bandwidth == CHANNEL_WIDTH_40 && primary_ch_idx > 2) || (bandwidth == CHANNEL_WIDTH_80 && primary_ch_idx > 4)) {
+		PHYDM_DBG(dm, ODM_PHY_CONFIG,
+			  "[%s]: Fail to switch bandwidth (bw: %d, primary ch: %d)\n",
+			  __func__, bandwidth, primary_ch_idx);
+		return false;
+	}
+	/*Make protection*/
+	if (central_ch_8821c == 165 && !(*dm->mp_mode))
+		bandwidth = CHANNEL_WIDTH_20;
+
+	bw_8821c = bandwidth;
+	rf_reg18 = config_phydm_read_rf_reg_8821c(dm, RF_PATH_A, 0x18, RFREGOFFSETMASK);
+	rf_reg_status = rf_reg_status & config_phydm_read_rf_check_8821c(rf_reg18);
+
+	/* Switch bandwidth */
+	switch (bandwidth) {
+	case CHANNEL_WIDTH_20: {
+/* Small BW([7:6]) = 0, primary channel ([5:2]) = 0, rf mode([1:0]) = 20M */
+#if 0
+		odm_set_bb_reg(dm, R_0x8ac, MASKBYTE0, CHANNEL_WIDTH_20);
+
+		/* ADC clock = 160M clock for BW20 */
+		odm_set_bb_reg(dm, R_0x8ac, (BIT(9) | BIT(8)), 0x0);
+		odm_set_bb_reg(dm, R_0x8ac, BIT(16), 0x1);
+
+		/* DAC clock = 160M clock for BW20 */
+		odm_set_bb_reg(dm, R_0x8ac, (BIT(21) | BIT(20)), 0x0);
+		odm_set_bb_reg(dm, R_0x8ac, BIT(28), 0x1);
+#endif
+		bb_reg8ac = odm_get_bb_reg(dm, R_0x8ac, MASKDWORD);
+		bb_reg8ac &= 0xffcffc00;
+		bb_reg8ac |= 0x10010000;
+		odm_set_bb_reg(dm, R_0x8ac, MASKDWORD, bb_reg8ac);
+
+		/* ADC buffer clock */
+		odm_set_bb_reg(dm, R_0x8c4, BIT(30), 0x1);
+
+		/* RF bandwidth */
+		rf_reg18 = (rf_reg18 | BIT(11) | BIT(10));
+
+		break;
+	}
+	case CHANNEL_WIDTH_40: {
+		/* Small BW([7:6]) = 0, primary channel ([5:2]) = sub-channel, rf mode([1:0]) = 40M */
+		/*odm_set_bb_reg(dm, R_0x8ac, MASKBYTE0, (((primary_ch_idx & 0xf) << 2) | CHANNEL_WIDTH_40));*/
+
+		/* CCK primary channel */
+		if (primary_ch_idx == 1)
+			odm_set_bb_reg(dm, R_0xa00, BIT(4), primary_ch_idx);
+		else
+			odm_set_bb_reg(dm, R_0xa00, BIT(4), 0);
+#if 0
+		/* ADC clock = 160M clock for BW40 */
+		odm_set_bb_reg(dm, R_0x8ac, (BIT(11) | BIT(10)), 0x0);
+		odm_set_bb_reg(dm, R_0x8ac, BIT(17), 0x1);
+
+		/* DAC clock = 160M clock for BW20 */
+		odm_set_bb_reg(dm, R_0x8ac, (BIT(23) | BIT(22)), 0x0);
+		odm_set_bb_reg(dm, R_0x8ac, BIT(29), 0x1);
+#endif
+		bb_reg8ac = odm_get_bb_reg(dm, R_0x8ac, MASKDWORD);
+		bb_reg8ac &= 0xff3ff300;
+		bb_reg8ac |= 0x20020000 | ((primary_ch_idx & 0xf) << 2) | CHANNEL_WIDTH_40;
+		odm_set_bb_reg(dm, R_0x8ac, MASKDWORD, bb_reg8ac);
+
+		/* ADC buffer clock */
+		odm_set_bb_reg(dm, R_0x8c4, BIT(30), 0x1);
+
+		/* RF bandwidth */
+		rf_reg18 = (rf_reg18 & (~(BIT(11) | BIT(10))));
+		rf_reg18 = (rf_reg18 | BIT(11));
+
+		break;
+	}
+	case CHANNEL_WIDTH_80: {
+/* Small BW([7:6]) = 0, primary channel ([5:2]) = sub-channel, rf mode([1:0]) = 80M */
+#if 0
+		odm_set_bb_reg(dm, R_0x8ac, MASKBYTE0, (((primary_ch_idx & 0xf) << 2) | CHANNEL_WIDTH_80));
+
+		/* ADC clock = 160M clock for BW80 */
+		odm_set_bb_reg(dm, R_0x8ac, (BIT(13) | BIT(12)), 0x0);
+		odm_set_bb_reg(dm, R_0x8ac, BIT(18), 0x1);
+
+		/* DAC clock = 160M clock for BW20 */
+		odm_set_bb_reg(dm, R_0x8ac, (BIT(25) | BIT(24)), 0x0);
+		odm_set_bb_reg(dm, R_0x8ac, BIT(30), 0x1);
+#endif
+		bb_reg8ac = odm_get_bb_reg(dm, R_0x8ac, MASKDWORD);
+		bb_reg8ac &= 0xfcffcf00;
+		bb_reg8ac |= 0x40040000 | ((primary_ch_idx & 0xf) << 2) | CHANNEL_WIDTH_80;
+		odm_set_bb_reg(dm, R_0x8ac, MASKDWORD, bb_reg8ac);
+
+		/* ADC buffer clock */
+		odm_set_bb_reg(dm, R_0x8c4, BIT(30), 0x1);
+
+		/* RF bandwidth */
+		rf_reg18 = (rf_reg18 & (~(BIT(11) | BIT(10))));
+		rf_reg18 = (rf_reg18 | BIT(10));
+
+		break;
+	}
+	case CHANNEL_WIDTH_5: {
+/* Small BW([7:6]) = 1, primary channel ([5:2]) = 0, rf mode([1:0]) = 20M */
+#if 0
+		odm_set_bb_reg(dm, R_0x8ac, MASKBYTE0, (BIT(6) | CHANNEL_WIDTH_20));
+
+		/* ADC clock = 40M clock */
+		odm_set_bb_reg(dm, R_0x8ac, (BIT(9) | BIT(8)), 0x2);
+		odm_set_bb_reg(dm, R_0x8ac, BIT(16), 0x0);
+
+		/* DAC clock = 160M clock for BW20 */
+		odm_set_bb_reg(dm, R_0x8ac, (BIT(21) | BIT(20)), 0x2);
+		odm_set_bb_reg(dm, R_0x8ac, BIT(28), 0x0);
+#endif
+		bb_reg8ac = odm_get_bb_reg(dm, R_0x8ac, MASKDWORD);
+		bb_reg8ac &= 0xefcefc00;
+		bb_reg8ac |= (0x2 << 20) | (0x2 << 8) | BIT(6);
+		odm_set_bb_reg(dm, R_0x8ac, MASKDWORD, bb_reg8ac);
+
+		/* ADC buffer clock */
+		odm_set_bb_reg(dm, R_0x8c4, BIT(30), 0x0);
+		odm_set_bb_reg(dm, R_0x8c8, BIT(31), 0x1);
+
+		/* RF bandwidth */
+		rf_reg18 = (rf_reg18 | BIT(11) | BIT(10));
+
+		break;
+	}
+	case CHANNEL_WIDTH_10: {
+/* Small BW([7:6]) = 1, primary channel ([5:2]) = 0, rf mode([1:0]) = 20M */
+#if 0
+		odm_set_bb_reg(dm, R_0x8ac, MASKBYTE0, (BIT(7) | CHANNEL_WIDTH_20));
+
+		/* ADC clock = 80M clock */
+		odm_set_bb_reg(dm, R_0x8ac, (BIT(9) | BIT(8)), 0x3);
+		odm_set_bb_reg(dm, R_0x8ac, BIT(16), 0x0);
+
+		/* DAC clock = 160M clock for BW20 */
+		odm_set_bb_reg(dm, R_0x8ac, (BIT(21) | BIT(20)), 0x3);
+		odm_set_bb_reg(dm, R_0x8ac, BIT(28), 0x0);
+#endif
+		bb_reg8ac = odm_get_bb_reg(dm, R_0x8ac, MASKDWORD);
+		bb_reg8ac &= 0xefcefc00;
+		bb_reg8ac |= (0x3 << 20) | (0x3 << 8) | BIT(7);
+		odm_set_bb_reg(dm, R_0x8ac, MASKDWORD, bb_reg8ac);
+
+		/* ADC buffer clock */
+		odm_set_bb_reg(dm, R_0x8c4, BIT(30), 0x0);
+		odm_set_bb_reg(dm, R_0x8c8, BIT(31), 0x1);
+
+		/* RF bandwidth */
+		rf_reg18 = (rf_reg18 | BIT(11) | BIT(10));
+
+		break;
+	}
+	default:
+		PHYDM_DBG(dm, ODM_PHY_CONFIG,
+			  "[%s]: Fail to switch bandwidth (bw: %d, primary ch: %d)\n",
+			  __func__, bandwidth, primary_ch_idx);
+	}
+
+	/* Write RF register */
+	odm_set_rf_reg(dm, RF_PATH_A, RF_0x18, RFREGOFFSETMASK, rf_reg18);
+
+	if (!rf_reg_status) {
+		PHYDM_DBG(dm, ODM_PHY_CONFIG,
+			  "[%s]: Fail to switch bandwidth (bw: %d, primary ch: %d), because writing RF register is fail\n",
+			  __func__, bandwidth, primary_ch_idx);
+		return false;
+	}
+
+	/* Modify RX DFIR parameters */
+	phydm_rxdfirpar_by_bw_8821c(dm, bandwidth);
+
+	/* Modify CCA parameters */
+	phydm_ccapar_by_bw_8821c(dm, bandwidth);
+	phydm_ccapar_8821c(dm);
+
+	/* Toggle RX path to avoid RX dead zone issue */
+	/*odm_set_bb_reg(dm, R_0x808, MASKBYTE0, 0x0);*/
+	/*odm_set_bb_reg(dm, R_0x808, MASKBYTE0, 0x11);*/
+
+	PHYDM_DBG(dm, ODM_PHY_CONFIG,
+		  "[%s]: Success to switch bandwidth (bw: %d, primary ch: %d)\n",
+		  __func__, bandwidth, primary_ch_idx);
+	return true;
+}
+
+__iram_odm_func__
+boolean
+config_phydm_switch_channel_bw_8821c(struct dm_struct *dm, u8 central_ch,
+				     u8 primary_ch_idx,
+				     enum channel_width bandwidth)
+{
+	/* Switch band */
+	if (config_phydm_switch_band_8821c(dm, central_ch) == false)
+		return false;
+
+	/* Switch channel */
+	if (config_phydm_switch_channel_8821c(dm, central_ch) == false)
+		return false;
+
+	/* Switch bandwidth */
+	if (config_phydm_switch_bandwidth_8821c(dm, primary_ch_idx, bandwidth) == false)
+		return false;
+
+	return true;
+}
+
+__iram_odm_func__
+boolean
+config_phydm_trx_mode_8821c(struct dm_struct *dm, enum bb_path tx_path,
+			    enum bb_path rx_path, boolean is_tx2_path)
+{
+	return true;
+}
+
+__iram_odm_func__
+boolean
+config_phydm_parameter_init_8821c(struct dm_struct *dm,
+				  enum odm_parameter_init type)
+{
+	if (type == ODM_PRE_SETTING) {
+		odm_set_bb_reg(dm, R_0x808, (BIT(28) | BIT(29)), 0x0);
+		PHYDM_DBG(dm, ODM_PHY_CONFIG,
+			  "[%s]: Pre setting: disable OFDM and CCK block\n",
+			  __func__);
+	} else if (type == ODM_POST_SETTING) {
+		odm_set_bb_reg(dm, R_0x808, (BIT(28) | BIT(29)), 0x3);
+		PHYDM_DBG(dm, ODM_PHY_CONFIG,
+			  "[%s]: Post setting: enable OFDM and CCK block\n",
+			  __func__);
+		rega24_8821c = odm_get_bb_reg(dm, R_0xa24, MASKDWORD);
+		rega28_8821c = odm_get_bb_reg(dm, R_0xa28, MASKDWORD);
+		regaac_8821c = odm_get_bb_reg(dm, R_0xaac, MASKDWORD);
+#if (PHYDM_FW_API_FUNC_ENABLE_8821C == 1)
+	} else if (type == ODM_INIT_FW_SETTING) {
+		u8 h2c_content[4] = {0};
+
+		h2c_content[0] = dm->rfe_type_expand;
+		h2c_content[1] = dm->rf_type;
+		h2c_content[2] = dm->cut_version;
+		h2c_content[3] = (dm->tx_ant_status << 4) | dm->rx_ant_status;
+
+		odm_fill_h2c_cmd(dm, PHYDM_H2C_FW_GENERAL_INIT, 4, h2c_content);
+#endif
+	} else {
+		PHYDM_DBG(dm, ODM_PHY_CONFIG, "[%s]: Wrong type!!\n", __func__);
+		return false;
+	}
+
+	return true;
+}
+
+__iram_odm_func__
+void config_phydm_switch_rf_set_8821c(struct dm_struct *dm, u8 rf_set)
+{
+#if (PHYDM_FW_API_FUNC_ENABLE_8821C == 1)
+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
+	void *adapter = dm->adapter;
+	PMGNT_INFO mgnt_info = &(((PADAPTER)(adapter))->MgntInfo);
+#endif
+
+	u32 bb_reg32;
+
+	odm_set_bb_reg(dm, R_0x1080, BIT(16), 0x1);
+	odm_set_bb_reg(dm, R_0x00, BIT(26), 0x1);
+	/*odm_set_mac_reg(dm, R_0x70, BIT(26), 0x1);*/
+	/*odm_set_mac_reg(dm, R_0x1704, MASKLWORD, 0x4000);*/
+	/*odm_set_mac_reg(dm, R_0x1700, (BIT(31) | BIT(30)), 0x3); */
+
+	bb_reg32 = odm_get_bb_reg(dm, R_0xcb8, MASKDWORD);
+	switch (rf_set) {
+	case SWITCH_TO_BTG:
+
+		dm->current_rf_set_8821c = SWITCH_TO_BTG;
+
+		bb_reg32 = (bb_reg32 | BIT(16));
+		bb_reg32 &= (~(BIT(18) | BIT(20) | BIT(21) | BIT(22) | BIT(23)));
+		odm_set_bb_reg(dm, R_0xa84, MASKBYTE2, 0xe);
+		odm_set_bb_reg(dm, R_0xa80, MASKLWORD, 0xfc84);
+
+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
+		if (*dm->mp_mode == true && mgnt_info->RegPHYParaFromFolder == 0) {
+#else
+		if (*dm->mp_mode == true) {
+#endif
+			odm_set_bb_reg(dm, R_0xaa8, 0x1f0000, 0x14);
+			odm_config_bb_with_header_file(dm, CONFIG_BB_AGC_TAB_DIFF);
+			/*Toggle initial gain twice for valid gain table*/
+			odm_set_bb_reg(dm, ODM_REG(IGI_A, dm), ODM_BIT(IGI, dm), 0x22);
+			odm_set_bb_reg(dm, ODM_REG(IGI_A, dm), ODM_BIT(IGI, dm), 0x20);
+		}
+		break;
+	case SWITCH_TO_WLG:
+
+		dm->current_rf_set_8821c = SWITCH_TO_WLG;
+
+		bb_reg32 = (bb_reg32 | BIT(20) | BIT(21) | BIT(22));
+		bb_reg32 &= (~(BIT(16) | BIT(18) | BIT(23)));
+		odm_set_bb_reg(dm, R_0xa84, MASKBYTE2, 0x12);
+		odm_set_bb_reg(dm, R_0xa80, MASKLWORD, 0x7532);
+
+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
+		if (*dm->mp_mode == true && mgnt_info->RegPHYParaFromFolder == 0) {
+#else
+		if (*dm->mp_mode == true) {
+#endif
+			odm_set_bb_reg(dm, R_0xaa8, 0x1f0000, 0x13);
+			odm_config_bb_with_header_file(dm, CONFIG_BB_AGC_TAB_DIFF);
+			/*Toggle initial gain twice for valid gain table*/
+			odm_set_bb_reg(dm, ODM_REG(IGI_A, dm), ODM_BIT(IGI, dm), 0x22);
+			odm_set_bb_reg(dm, ODM_REG(IGI_A, dm), ODM_BIT(IGI, dm), 0x20);
+		}
+		break;
+	case SWITCH_TO_WLA:
+
+		dm->current_rf_set_8821c = SWITCH_TO_WLA;
+
+		bb_reg32 = (bb_reg32 | BIT(20) | BIT(22) | BIT(23));
+		bb_reg32 &= (~(BIT(16) | BIT(18) | BIT(21)));
+
+		break;
+	case SWITCH_TO_BT:
+
+		dm->current_rf_set_8821c = SWITCH_TO_BT;
+
+		break;
+	default:
+		break;
+	}
+
+	odm_set_bb_reg(dm, R_0xcb8, MASKDWORD, bb_reg32);
+#endif
+}
+
+__iram_odm_func__
+void config_phydm_set_ant_path(struct dm_struct *dm, u8 rf_set, u8 ant_num)
+{
+#if (PHYDM_FW_API_FUNC_ENABLE_8821C == 1)
+	boolean switch_polarity_inverse = false;
+	u8 regval_0xcb7 = 0;
+
+	dm->current_ant_num_8821c = ant_num;
+	config_phydm_switch_rf_set_8821c(dm, rf_set);
+
+	if (rf_set == SWITCH_TO_BT)
+		phydm_set_gnt_state_8821c(dm, false, true); /* GNT_WL=0, GNT_BT=1 for BT test */
+	else
+		phydm_set_gnt_state_8821c(dm, true, false); /* GNT_WL=1, GNT_BT=0 for WL test */
+
+	/*switch does not exist*/
+	if (dm->rfe_type_expand == 0x5 || dm->rfe_type_expand == 0x6 ||
+	    dm->rfe_type_expand == 0x25 || dm->rfe_type_expand == 0x26 ||
+	    dm->rfe_type_expand == 0x2a || dm->rfe_type_expand == 0x2d ||
+	    dm->rfe_type_expand == 0x2e)
+		return;
+
+	if (dm->current_ant_num_8821c) /*Ant1 = 0, Ant2 = 1*/
+		switch_polarity_inverse = !switch_polarity_inverse;
+
+	if (rf_set == SWITCH_TO_WLG)
+		switch_polarity_inverse = !switch_polarity_inverse;
+
+	/*set antenna control by WL 0xcb4[29:28]*/
+	odm_set_bb_reg(dm, R_0x4c, BIT(24) | BIT(23), 0x2);
+
+	/*set RFE_ctrl8 and RFE_ctrl9 as antenna control pins by software*/
+	odm_set_bb_reg(dm, R_0xcb4, 0x000000ff, 0x77);
+
+	/*0xcb4[29:28] = 2b'01 for no switch_polatiry_inverse, DPDT_SEL_N =1, DPDT_SEL_P =0*/
+	regval_0xcb7 = (!switch_polarity_inverse ? 0x1 : 0x2);
+
+	odm_set_bb_reg(dm, R_0xcb4, 0x30000000, regval_0xcb7);
+#endif
+}
+
+__iram_odm_func__
+u32 query_phydm_trx_capability_8821c(struct dm_struct *dm)
+{
+#if (PHYDM_FW_API_FUNC_ENABLE_8821C == 1)
+	u32 value32 = 0x00000000;
+
+	PHYDM_DBG(dm, ODM_PHY_CONFIG, "[%s]: trx_capability = 0x%x\n", __func__,
+		  value32);
+	return value32;
+#else
+	return 0;
+#endif
+}
+
+__iram_odm_func__
+u32 query_phydm_stbc_capability_8821c(struct dm_struct *dm)
+{
+#if (PHYDM_FW_API_FUNC_ENABLE_8821C == 1)
+	u32 value32 = 0x00010001;
+
+	PHYDM_DBG(dm, ODM_PHY_CONFIG, "[%s]: stbc_capability = 0x%x\n",
+		  __func__, value32);
+	return value32;
+#else
+	return 0;
+#endif
+}
+
+__iram_odm_func__
+u32 query_phydm_ldpc_capability_8821c(struct dm_struct *dm)
+{
+#if (PHYDM_FW_API_FUNC_ENABLE_8821C == 1)
+	u32 value32 = 0x01000100;
+
+	PHYDM_DBG(dm, ODM_PHY_CONFIG, "[%s]: ldpc_capability = 0x%x\n",
+		  __func__, value32);
+	return value32;
+#else
+	return 0;
+#endif
+}
+
+__iram_odm_func__
+u32 query_phydm_txbf_parameters_8821c(struct dm_struct *dm)
+{
+#if (PHYDM_FW_API_FUNC_ENABLE_8821C == 1)
+	u32 value32 = 0x00030003;
+
+	PHYDM_DBG(dm, ODM_PHY_CONFIG, "[%s]: txbf_parameters = 0x%x\n",
+		  __func__, value32);
+	return value32;
+#else
+	return 0;
+#endif
+}
+
+__iram_odm_func__
+u32 query_phydm_txbf_capability_8821c(struct dm_struct *dm)
+{
+#if (PHYDM_FW_API_FUNC_ENABLE_8821C == 1)
+	u32 value32 = 0x01010001;
+
+	PHYDM_DBG(dm, ODM_PHY_CONFIG, "[%s]: txbf_capability = 0x%x\n",
+		  __func__, value32);
+	return value32;
+#else
+	return 0;
+#endif
+}
+
+__iram_odm_func__
+u8 query_phydm_default_rf_set_8821c(struct dm_struct *dm)
+{
+#if (PHYDM_FW_API_FUNC_ENABLE_8821C == 1)
+	return dm->default_rf_set_8821c;
+#else
+	return 0;
+#endif
+}
+
+__iram_odm_func__
+u8 query_phydm_current_rf_set_8821c(struct dm_struct *dm)
+{
+#if (PHYDM_FW_API_FUNC_ENABLE_8821C == 1)
+	return dm->current_rf_set_8821c;
+#else
+	return 0;
+#endif
+}
+
+__iram_odm_func__
+u8 query_phydm_rfetype_8821c(struct dm_struct *dm)
+{
+#if (PHYDM_FW_API_FUNC_ENABLE_8821C == 1)
+	return dm->rfe_type_expand;
+#else
+	return 0;
+#endif
+}
+
+__iram_odm_func__
+u8 query_phydm_current_ant_num_8821c(struct dm_struct *dm)
+{
+#if (PHYDM_FW_API_FUNC_ENABLE_8821C == 1)
+	u32 regval_0xcb4 = odm_get_bb_reg(dm, R_0xcb4, BIT(29) | BIT(28));
+
+	if (dm->current_rf_set_8821c == SWITCH_TO_BTG || dm->current_rf_set_8821c == SWITCH_TO_WLA || dm->current_rf_set_8821c == SWITCH_TO_BT) {
+		if (regval_0xcb4 == 1)
+			dm->current_ant_num_8821c = SWITCH_TO_ANT1;
+		else if (regval_0xcb4 == 2)
+			dm->current_ant_num_8821c = SWITCH_TO_ANT2;
+		else if (regval_0xcb4 == 1)
+			dm->current_ant_num_8821c = SWITCH_TO_ANT2;
+		else if (regval_0xcb4 == 2)
+			dm->current_ant_num_8821c = SWITCH_TO_ANT1;
+	}
+
+	return dm->current_ant_num_8821c;
+#else
+	return 0;
+#endif
+}
+
+__iram_odm_func__
+u8 query_phydm_ant_num_map_8821c(struct dm_struct *dm)
+{
+#if (PHYDM_FW_API_FUNC_ENABLE_8821C == 1)
+	u8 mapping_table = 0;
+
+	/* mapping table meaning
+	 * 1: choose ant1 or ant2
+	 * 2: only ant1
+	 * 3: only ant2
+	 * 4: cannot choose
+	 */
+
+	if (dm->rfe_type_expand == 0 || dm->rfe_type_expand == 7 || dm->rfe_type_expand == 0x20 ||
+	    dm->rfe_type_expand == 0x27 || dm->rfe_type_expand == 0x28 || dm->rfe_type_expand == 0x2f)
+		mapping_table = 1;
+	else if (dm->rfe_type_expand == 1 || dm->rfe_type_expand == 2 || dm->rfe_type_expand == 0x21 ||
+		 dm->rfe_type_expand == 0x22 || dm->rfe_type_expand == 0x29 || dm->rfe_type_expand == 0x2a)
+		mapping_table = 2;
+	else if (dm->rfe_type_expand == 3 || dm->rfe_type_expand == 4 || dm->rfe_type_expand == 0x23 ||
+		 dm->rfe_type_expand == 0x24 || dm->rfe_type_expand == 0x2b || dm->rfe_type_expand == 0x2c)
+		mapping_table = 3;
+	else if (dm->rfe_type_expand == 5 || dm->rfe_type_expand == 6 || dm->rfe_type_expand == 0x25 ||
+		 dm->rfe_type_expand == 0x26 || dm->rfe_type_expand == 0x2d || dm->rfe_type_expand == 0x2e)
+		mapping_table = 4;
+
+	return mapping_table;
+#else
+	return 0;
+#endif
+}
+
+/* ======================================================================== */
+#endif /*PHYDM_FW_API_ENABLE_8821C == 1*/
+#endif /* RTL8821C_SUPPORT == 1 */
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/rtl8821c/phydm_hal_api8821c.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/rtl8821c/phydm_hal_api8821c.h
--- linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/rtl8821c/phydm_hal_api8821c.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/rtl8821c/phydm_hal_api8821c.h	2020-04-10 16:35:06.835660954 +0300
@@ -0,0 +1,125 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2016 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#ifndef __INC_PHYDM_API_H_8821C__
+#define __INC_PHYDM_API_H_8821C__
+
+#if (RTL8821C_SUPPORT == 1)
+
+#define PHY_CONFIG_VERSION_8821C "3.1.27" /*2017.08.08     (HW user guide version: R03, SW user guide version: R01, Modification: R27)*/
+
+#define INVALID_RF_DATA 0xffffffff
+#define INVALID_TXAGC_DATA 0xff
+
+#define config_phydm_read_rf_check_8821c(data) (data != INVALID_RF_DATA)
+#define config_phydm_read_txagc_check_8821c(data) (data != INVALID_TXAGC_DATA)
+
+enum rf_set_8821c {
+	SWITCH_TO_BTG = 0x0,
+	SWITCH_TO_WLG = 0x1,
+	SWITCH_TO_WLA = 0x2,
+	SWITCH_TO_BT = 0x3
+};
+
+enum ant_num_8821c {
+	SWITCH_TO_ANT1 = 0x0,
+	SWITCH_TO_ANT2 = 0x1
+};
+
+enum ant_num_map_8821c {
+	BOTH_AVAILABLE = 0x1,
+	ONLY_ANT1 = 0x2,
+	ONLY_ANT2 = 0x3,
+	DONT_CARE = 0x4
+};
+
+s8 phydm_cck_rssi_8821c(struct dm_struct *dm, u8 lna_idx, u8 vga_idx);
+
+u32 config_phydm_read_rf_reg_8821c(struct dm_struct *dm, enum rf_path path,
+				   u32 reg_addr, u32 bit_mask);
+
+boolean
+config_phydm_write_rf_reg_8821c(struct dm_struct *dm, enum rf_path path,
+				u32 reg_addr, u32 bit_mask, u32 data);
+
+boolean
+config_phydm_write_txagc_8821c(struct dm_struct *dm, u32 power_index,
+			       enum rf_path path, u8 hw_rate);
+
+u8 config_phydm_read_txagc_8821c(struct dm_struct *dm, enum rf_path path,
+				 u8 hw_rate);
+
+boolean
+config_phydm_switch_band_8821c(struct dm_struct *dm, u8 central_ch);
+
+boolean
+config_phydm_switch_channel_8821c(struct dm_struct *dm, u8 central_ch);
+
+boolean
+config_phydm_switch_bandwidth_8821c(struct dm_struct *dm, u8 primary_ch_idx,
+				    enum channel_width bandwidth);
+
+boolean
+config_phydm_switch_channel_bw_8821c(struct dm_struct *dm, u8 central_ch,
+				     u8 primary_ch_idx,
+				     enum channel_width bandwidth);
+
+boolean
+config_phydm_trx_mode_8821c(struct dm_struct *dm, enum bb_path tx_path,
+			    enum bb_path rx_path, boolean is_tx2_path);
+
+boolean
+config_phydm_parameter_init_8821c(struct dm_struct *dm,
+				  enum odm_parameter_init type);
+
+void config_phydm_switch_rf_set_8821c(struct dm_struct *dm, u8 rf_set);
+
+void config_phydm_set_ant_path(struct dm_struct *dm, u8 rf_set, u8 ant_num);
+
+/* ======================================================================== */
+/* These following functions can be used for PHY DM only*/
+
+boolean
+phydm_write_txagc_1byte_8821c(struct dm_struct *dm, u32 power_index,
+			      enum rf_path path, u8 hw_rate);
+
+void phydm_init_hw_info_by_rfe_type_8821c(struct dm_struct *dm);
+
+void phydm_set_gnt_state_8821c(struct dm_struct *dm, boolean gnt_wl_state,
+			       boolean gnt_bt_state);
+
+/* ======================================================================== */
+
+u32 query_phydm_trx_capability_8821c(struct dm_struct *dm);
+
+u32 query_phydm_stbc_capability_8821c(struct dm_struct *dm);
+
+u32 query_phydm_ldpc_capability_8821c(struct dm_struct *dm);
+
+u32 query_phydm_txbf_parameters_8821c(struct dm_struct *dm);
+
+u32 query_phydm_txbf_capability_8821c(struct dm_struct *dm);
+
+u8 query_phydm_default_rf_set_8821c(struct dm_struct *dm);
+
+u8 query_phydm_current_rf_set_8821c(struct dm_struct *dm);
+
+u8 query_phydm_rfetype_8821c(struct dm_struct *dm);
+
+u8 query_phydm_current_ant_num_8821c(struct dm_struct *dm);
+
+u8 query_phydm_ant_num_map_8821c(struct dm_struct *dm);
+
+#endif /* RTL8821C_SUPPORT == 1 */
+#endif /*  __INC_PHYDM_API_H_8821C__ */
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/rtl8821c/phydm_iqk_8821c.c linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/rtl8821c/phydm_iqk_8821c.c
--- linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/rtl8821c/phydm_iqk_8821c.c	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/rtl8821c/phydm_iqk_8821c.c	2020-04-10 16:35:06.835660954 +0300
@@ -0,0 +1,2478 @@
+
+#include "mp_precomp.h"
+#include "../phydm_precomp.h"
+
+#if (RTL8821C_SUPPORT == 1)
+
+
+/*---------------------------Define Local Constant---------------------------*/
+
+static u32	dpk_result[DPK_BACKUP_REG_NUM_8821C] ;
+#define enable_8821c_dpk 1
+#define dpk_forcein_sram4 0
+
+/*---------------------------Define Local Constant---------------------------*/
+
+
+#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
+void do_iqk_8821c(
+	void		*p_dm_void,
+	u8		delta_thermal_index,
+	u8		thermal_value,
+	u8		threshold
+)
+{
+	struct PHY_DM_STRUCT		*p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
+
+	struct _ADAPTER		*adapter = p_dm_odm->adapter;
+	HAL_DATA_TYPE	*p_hal_data = GET_HAL_DATA(adapter);
+
+	odm_reset_iqk_result(p_dm_odm);
+	p_dm_odm->rf_calibrate_info.thermal_value_iqk = thermal_value;
+	phy_iq_calibrate_8821c(p_dm_odm, true);
+}
+#else
+/*Originally p_config->do_iqk is hooked phy_iq_calibrate_8821c, but do_iqk_8821c and phy_iq_calibrate_8821c have different arguments*/
+void do_iqk_8821c(
+	void		*p_dm_void,
+	u8	delta_thermal_index,
+	u8	thermal_value,
+	u8	threshold
+)
+{
+	struct PHY_DM_STRUCT	*p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
+	boolean		is_recovery = (boolean) delta_thermal_index;
+
+	phy_iq_calibrate_8821c(p_dm_odm, true);
+}
+#endif
+void do_dpk_8821c(
+	void		*p_dm_void,
+	u8	delta_thermal_index,
+	u8	thermal_value,
+	u8	threshold
+)
+{
+	struct PHY_DM_STRUCT	*p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
+	boolean		is_recovery = (boolean) delta_thermal_index;
+	phy_dp_calibrate_8821c(p_dm_odm, true);
+}
+
+
+
+void
+_iqk_check_coex_status(
+	struct PHY_DM_STRUCT	*p_dm_odm,
+	boolean		beforeK
+)
+{
+	u8		u1b_tmp;
+	u16		count = 0;
+	u8		h2c_parameter;
+
+	h2c_parameter = 1;
+
+	if (beforeK) {
+		u1b_tmp = odm_read_1byte(p_dm_odm, 0x49c);
+		ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]check 0x49c[0] = 0x%x before h2c 0x6d\n", u1b_tmp));
+		RT_TRACE(COMP_COEX, DBG_LOUD, ("[IQK]check 0x49c[0] = 0x%x before h2c 0x6d\n", u1b_tmp));
+
+		/*check if BT IQK */
+		u1b_tmp = odm_read_1byte(p_dm_odm, 0x49c);
+		while ((u1b_tmp & BIT(1)) && (count < 100)) {
+			ODM_delay_ms(10);
+			u1b_tmp = odm_read_1byte(p_dm_odm, 0x49c);
+			count++;
+			ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]check 0x49c[1]=0x%x, count = %d\n", u1b_tmp, count));
+			RT_TRACE(COMP_COEX, DBG_LOUD, ("[IQK]check 0x49c[1]=0x%x, count = %d\n", u1b_tmp, count));
+		}
+#if 1
+		odm_fill_h2c_cmd(p_dm_odm, ODM_H2C_WIFI_CALIBRATION, 1, &h2c_parameter);
+
+		u1b_tmp = odm_read_1byte(p_dm_odm, 0x49c);
+		ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]check 0x49c[0] = 0x%x after h2c 0x6d\n", u1b_tmp));
+		RT_TRACE(COMP_COEX, DBG_LOUD, ("[IQK]check 0x49c[0] = 0x%x after h2c 0x6d\n", u1b_tmp));
+
+		u1b_tmp = odm_read_1byte(p_dm_odm, 0x49c);
+		/*check if WL IQK available form WL FW */
+		while ((!(u1b_tmp & BIT(0))) && (count < 100)) {
+			ODM_delay_ms(10);
+			u1b_tmp = odm_read_1byte(p_dm_odm, 0x49c);
+			count++;
+			ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]check 0x49c[1]=0x%x, count = %d\n", u1b_tmp, count));
+			RT_TRACE(COMP_COEX, DBG_LOUD, ("[IQK]check 0x49c[1]=0x%x, count = %d\n", u1b_tmp, count));
+		}
+
+		if (count >= 100)
+			ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]Polling 0x49c to 1 for WiFi calibration H2C cmd FAIL! count(%d)\n", count));
+#endif
+
+	} else
+		odm_set_bb_reg(p_dm_odm, 0x49c, BIT(0), 0x0);
+}
+
+
+u32
+_iqk_indirect_read_reg(
+	struct PHY_DM_STRUCT	*p_dm_odm,
+	u16 reg_addr
+)
+{
+	u32 j = 0;
+
+	/*wait for ready bit before access 0x1700*/
+	odm_write_4byte(p_dm_odm, 0x1700, 0x800f0000 | reg_addr);
+
+	do {
+		j++;
+	} while (((odm_read_1byte(p_dm_odm, 0x1703) & BIT(5)) == 0) && (j < 30000));
+
+	return odm_read_4byte(p_dm_odm, 0x1708);  /*get read data*/
+
+}
+
+
+void
+_iqk_indirect_write_reg(
+	struct PHY_DM_STRUCT	*p_dm_odm,
+	u16 reg_addr,
+	u32 bit_mask,
+	u32 reg_value
+)
+{
+	u32 val, i = 0, j = 0, bitpos = 0;
+
+	if (bit_mask == 0x0)
+		return;
+	if (bit_mask == 0xffffffff) {
+		odm_write_4byte(p_dm_odm, 0x1704, reg_value); /*put write data*/
+
+		/*wait for ready bit before access 0x1700*/
+		do {
+			j++;
+		} while (((odm_read_1byte(p_dm_odm, 0x1703) & BIT(5)) == 0) && (j < 30000));
+
+		odm_write_4byte(p_dm_odm, 0x1700, 0xc00f0000 | reg_addr);
+	} else {
+		for (i = 0; i <= 31; i++) {
+			if (((bit_mask >> i) & 0x1) == 0x1) {
+				bitpos = i;
+				break;
+			}
+		}
+
+		/*read back register value before write*/
+		val = _iqk_indirect_read_reg(p_dm_odm, reg_addr);
+		val = (val & (~bit_mask)) | (reg_value << bitpos);
+
+		odm_write_4byte(p_dm_odm, 0x1704, val); /*put write data*/
+
+		/*wait for ready bit before access 0x1700*/
+		do {
+			j++;
+		} while (((odm_read_1byte(p_dm_odm, 0x1703) & BIT(5)) == 0) && (j < 30000));
+
+		odm_write_4byte(p_dm_odm, 0x1700, 0xc00f0000 | reg_addr);
+	}
+}
+
+
+void
+_iqk_set_gnt_wl_high(
+	struct PHY_DM_STRUCT	*p_dm_odm
+)
+{
+	u32 val = 0;
+	u8 state = 0x1, sw_control = 0x1;
+
+	/*GNT_WL = 1*/
+	val = (sw_control) ? ((state << 1) | 0x1) : 0;
+	_iqk_indirect_write_reg(p_dm_odm, 0x38, 0x3000, val); /*0x38[13:12]*/
+	_iqk_indirect_write_reg(p_dm_odm, 0x38, 0x0300, val); /*0x38[9:8]*/
+}
+
+void _iqk_set_gnt_bt_low(
+	struct PHY_DM_STRUCT	*p_dm_odm
+)
+{
+	u32 val = 0;
+	u8 state = 0x0, sw_control = 0x1;
+
+	/*GNT_BT = 0*/
+	val = (sw_control) ? ((state << 1) | 0x1) : 0;
+	_iqk_indirect_write_reg(p_dm_odm, 0x38, 0xc000, val); /*0x38[15:14]*/
+	_iqk_indirect_write_reg(p_dm_odm, 0x38, 0x0c00, val); /*0x38[11:10]*/
+}
+
+void _iqk_set_gnt_wl_gnt_bt(
+	struct PHY_DM_STRUCT	*p_dm_odm,
+	boolean beforeK
+)
+{
+	struct _IQK_INFORMATION	*p_iqk_info = &p_dm_odm->IQK_info;
+
+	if (beforeK) {
+		_iqk_set_gnt_wl_high(p_dm_odm);
+		_iqk_set_gnt_bt_low(p_dm_odm);
+	} else
+		_iqk_indirect_write_reg(p_dm_odm, 0x38, MASKDWORD, p_iqk_info->tmp_GNTWL);
+}
+
+
+void
+_iqk_fill_iqk_report_8821c(
+	void		*p_dm_void,
+	u8			channel
+)
+{
+	struct PHY_DM_STRUCT	*p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
+	struct _IQK_INFORMATION	*p_iqk_info = &p_dm_odm->IQK_info;
+	u32		tmp1 = 0x0, tmp2 = 0x0, tmp3 = 0x0;
+	u8		i;
+
+	for (i = 0; i < SS_8821C; i++) {
+		tmp1 = tmp1 + ((p_iqk_info->IQK_fail_report[channel][i][TX_IQK] & 0x1) << i);
+		tmp2 = tmp2 + ((p_iqk_info->IQK_fail_report[channel][i][RX_IQK] & 0x1) << (i + 4));
+		tmp3 = tmp3 + ((p_iqk_info->RXIQK_fail_code[channel][i] & 0x3) << (i * 2 + 8));
+	}
+	odm_write_4byte(p_dm_odm, 0x1b00, 0xf8000008);
+	odm_set_bb_reg(p_dm_odm, 0x1bf0, 0x00ffffff, tmp1 | tmp2 | tmp3);
+
+	for (i = 0; i < SS_8821C; i++)
+		odm_write_4byte(p_dm_odm, 0x1be8 + (i * 4), (p_iqk_info->RXIQK_AGC[channel][(i * 2) + 1] << 16) | p_iqk_info->RXIQK_AGC[channel][i * 2]);
+}
+
+
+void
+_iqk_iqk_fail_report_8821c(
+	struct PHY_DM_STRUCT	*p_dm_odm
+)
+{
+	u32		tmp1bf0 = 0x0;
+	u8		i;
+
+	tmp1bf0 = odm_read_4byte(p_dm_odm, 0x1bf0);
+
+	for (i = 0; i < 4; i++) {
+		if (tmp1bf0 & (0x1 << i))
+#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
+			ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK] please check S%d TXIQK\n", i));
+#else
+			panic_printk("[IQK] please check S%d TXIQK\n", i);
+#endif
+		if (tmp1bf0 & (0x1 << (i + 12)))
+#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
+			ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK] please check S%d RXIQK\n", i));
+#else
+			panic_printk("[IQK] please check S%d RXIQK\n", i);
+#endif
+
+	}
+}
+
+
+void
+_iqk_backup_mac_bb_8821c(
+	struct PHY_DM_STRUCT	*p_dm_odm,
+	u32		*MAC_backup,
+	u32		*BB_backup,
+	u32		*backup_mac_reg,
+	u32		*backup_bb_reg,
+	u8		num_backup_bb_reg
+)
+{
+	u32 i;
+
+	for (i = 0; i < MAC_REG_NUM_8821C; i++)
+		MAC_backup[i] = odm_read_4byte(p_dm_odm, backup_mac_reg[i]);
+
+	for (i = 0; i < num_backup_bb_reg; i++)
+		BB_backup[i] = odm_read_4byte(p_dm_odm, backup_bb_reg[i]);
+	/*	ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]BackupMacBB Success!!!!\n")); */
+}
+
+
+void
+_iqk_backup_rf_8821c(
+	struct PHY_DM_STRUCT	*p_dm_odm,
+	u32		RF_backup[][SS_8821C],
+	u32		*backup_rf_reg
+)
+{
+	u32 i, j;
+
+	for (i = 0; i < RF_REG_NUM_8821C; i++)
+		for (j = 0; j < SS_8821C; j++)
+			RF_backup[i][j] = odm_get_rf_reg(p_dm_odm, j, backup_rf_reg[i], RFREGOFFSETMASK);
+	/*	ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]BackupRF Success!!!!\n")); */
+
+}
+
+void
+_iqk_agc_bnd_int_8821c(
+	struct PHY_DM_STRUCT	*p_dm_odm
+)
+{
+	/*initialize RX AGC bnd, it must do after bbreset*/
+	odm_write_4byte(p_dm_odm, 0x1b00, 0xf8000008);
+	odm_write_4byte(p_dm_odm, 0x1b00, 0xf80a7008);
+	odm_write_4byte(p_dm_odm, 0x1b00, 0xf8015008);
+	odm_write_4byte(p_dm_odm, 0x1b00, 0xf8000008);
+	/*ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_TRACE, ("[IQK]init. rx agc bnd\n"));*/
+}
+
+
+void
+_iqk_bb_reset_8821c(
+	struct PHY_DM_STRUCT	*p_dm_odm
+)
+{
+	boolean		cca_ing = false;
+	u32		count = 0;
+
+	odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x0, RFREGOFFSETMASK, 0x10000);
+
+	while (1) {
+		odm_write_4byte(p_dm_odm, 0x8fc, 0x0);
+		odm_set_bb_reg(p_dm_odm, 0x198c, 0x7, 0x7);
+		cca_ing = (boolean) odm_get_bb_reg(p_dm_odm, 0xfa0, BIT(3));
+
+		if (count > 30)
+			cca_ing = false;
+
+		if (cca_ing) {
+			ODM_delay_ms(1);
+			count++;
+		} else {
+			odm_write_1byte(p_dm_odm, 0x808, 0x0);	/*RX ant off*/
+			odm_set_bb_reg(p_dm_odm, 0xa04, BIT(27) | BIT26 | BIT25 | BIT24, 0x0);		/*CCK RX path off*/
+
+			/*BBreset*/
+			odm_set_bb_reg(p_dm_odm, 0x0, BIT(16), 0x0);
+			odm_set_bb_reg(p_dm_odm, 0x0, BIT(16), 0x1);
+
+			if (odm_get_bb_reg(p_dm_odm, 0x660, BIT(16)))
+				odm_write_4byte(p_dm_odm, 0x6b4, 0x89000006);
+			ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]BBreset!!!!\n"));
+			break;
+		}
+	}
+}
+
+void
+_iqk_afe_setting_8821c(
+	struct PHY_DM_STRUCT	*p_dm_odm,
+	boolean		do_iqk
+)
+{
+	if (do_iqk) {
+		/*IQK AFE setting RX_WAIT_CCA mode */
+		odm_write_4byte(p_dm_odm, 0xc60, 0x50000000);
+		odm_write_4byte(p_dm_odm, 0xc60, 0x700F0040);
+
+
+		/*AFE setting*/
+		odm_write_4byte(p_dm_odm, 0xc58, 0xd8000402);
+		odm_write_4byte(p_dm_odm, 0xc5c, 0xd1000120);
+		odm_write_4byte(p_dm_odm, 0xc6c, 0x00000a15);
+		_iqk_bb_reset_8821c(p_dm_odm);
+		/*		ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]AFE setting for IQK mode!!!!\n")); */
+	} else {
+		/*IQK AFE setting RX_WAIT_CCA mode */
+		odm_write_4byte(p_dm_odm, 0xc60, 0x50000000);
+		odm_write_4byte(p_dm_odm, 0xc60, 0x700B8040);
+
+		/*AFE setting*/
+		odm_write_4byte(p_dm_odm, 0xc58, 0xd8020402);
+		odm_write_4byte(p_dm_odm, 0xc5c, 0xde000120);
+		odm_write_4byte(p_dm_odm, 0xc6c, 0x0000122a);
+		/*		ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]AFE setting for Normal mode!!!!\n")); */
+	}
+}
+
+void
+_iqk_restore_mac_bb_8821c(
+	struct PHY_DM_STRUCT		*p_dm_odm,
+	u32		*MAC_backup,
+	u32		*BB_backup,
+	u32		*backup_mac_reg,
+	u32		*backup_bb_reg,
+	u8		num_backup_bb_reg
+)
+{
+	u32 i;
+
+	for (i = 0; i < MAC_REG_NUM_8821C; i++)
+		odm_write_4byte(p_dm_odm, backup_mac_reg[i], MAC_backup[i]);
+	for (i = 0; i < num_backup_bb_reg; i++)
+		odm_write_4byte(p_dm_odm, backup_bb_reg[i], BB_backup[i]);
+
+	/*	ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]RestoreMacBB Success!!!!\n")); */
+}
+
+void
+_iqk_restore_rf_8821c(
+	struct PHY_DM_STRUCT			*p_dm_odm,
+	u32			*backup_rf_reg,
+	u32			RF_backup[][SS_8821C]
+)
+{
+	u32 i;
+
+	odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0xef, RFREGOFFSETMASK, 0x0);
+	odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0xee, RFREGOFFSETMASK, 0x0);
+	odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0xdf, RFREGOFFSETMASK, RF_backup[0][ODM_RF_PATH_A] & (~BIT(4)));
+	/*odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0xde, RFREGOFFSETMASK, RF_backup[1][ODM_RF_PATH_A]|BIT4);*/
+	odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0xde, RFREGOFFSETMASK, RF_backup[1][ODM_RF_PATH_A] & (~BIT(4)));
+
+	for (i = 2; i < (RF_REG_NUM_8821C-1); i++)
+		odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, backup_rf_reg[i], RFREGOFFSETMASK, RF_backup[i][ODM_RF_PATH_A]);
+
+	odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x1, RFREGOFFSETMASK, (RF_backup[5][ODM_RF_PATH_A] & (~BIT(0))));
+
+	/*ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]RestoreRF Success!!!!\n")); */
+
+}
+
+
+void
+_iqk_backup_iqk_8821c(
+	struct PHY_DM_STRUCT			*p_dm_odm,
+	u8				step
+)
+{
+	struct _IQK_INFORMATION	*p_iqk_info = &p_dm_odm->IQK_info;
+	u8		i, j, k, path, idx;
+	u32		tmp;
+	u16		iqk_apply[2] = {0xc94, 0xe94};
+
+	if (step == 0x0) {
+		p_iqk_info->iqk_channel[1] = p_iqk_info->iqk_channel[0];
+		for (i = 0; i < SS_8821C; i++) {
+			p_iqk_info->LOK_IDAC[1][i] = p_iqk_info->LOK_IDAC[0][i];
+			p_iqk_info->RXIQK_AGC[1][i] = p_iqk_info->RXIQK_AGC[0][i];
+			p_iqk_info->bypass_iqk[1][i] = p_iqk_info->bypass_iqk[0][i];
+			p_iqk_info->RXIQK_fail_code[1][i] = p_iqk_info->RXIQK_fail_code[0][i];
+			for (j = 0; j < 2; j++) {
+				p_iqk_info->IQK_fail_report[1][i][j] = p_iqk_info->IQK_fail_report[0][i][j];
+				for (k = 0; k < 8; k++) {
+					p_iqk_info->IQK_CFIR_real[1][i][j][k] = p_iqk_info->IQK_CFIR_real[0][i][j][k];
+					p_iqk_info->IQK_CFIR_imag[1][i][j][k] = p_iqk_info->IQK_CFIR_imag[0][i][j][k];
+				}
+			}
+		}
+
+		for (i = 0; i < 4; i++) {
+			p_iqk_info->RXIQK_fail_code[0][i] = 0x0;
+			p_iqk_info->RXIQK_AGC[0][i] = 0x0;
+			for (j = 0; j < 2; j++) {
+				p_iqk_info->IQK_fail_report[0][i][j] = true;
+				p_iqk_info->gs_retry_count[0][i][j] = 0x0;
+			}
+			for (j = 0; j < 3; j++)
+				p_iqk_info->retry_count[0][i][j] = 0x0;
+		}
+	} else {
+		p_iqk_info->iqk_channel[0] = p_iqk_info->rf_reg18;
+		for (path = 0; path < SS_8821C; path++) {
+			p_iqk_info->LOK_IDAC[0][path] = odm_get_rf_reg(p_dm_odm, path, 0x58, RFREGOFFSETMASK);
+			p_iqk_info->bypass_iqk[0][path] = odm_get_bb_reg(p_dm_odm, iqk_apply[path], MASKDWORD);
+
+			for (idx = 0; idx < 2; idx++) {
+				odm_set_bb_reg(p_dm_odm, 0x1b00, MASKDWORD, 0xf8000008 | path << 1);
+
+				if (idx == 0)
+					odm_set_bb_reg(p_dm_odm, 0x1b0c, BIT(13) | BIT(12), 0x3);
+				else
+					odm_set_bb_reg(p_dm_odm, 0x1b0c, BIT(13) | BIT(12), 0x1);
+
+				odm_set_bb_reg(p_dm_odm, 0x1bd4, BIT(20) | BIT(19) | BIT(18) | BIT(17) | BIT(16), 0x10);
+
+				for (i = 0; i < 8; i++) {
+					odm_set_bb_reg(p_dm_odm, 0x1bd8, MASKDWORD, 0xe0000001 + (i * 4));
+					tmp = odm_get_bb_reg(p_dm_odm, 0x1bfc, MASKDWORD);
+					p_iqk_info->IQK_CFIR_real[0][path][idx][i] = (tmp & 0x0fff0000) >> 16;
+					p_iqk_info->IQK_CFIR_imag[0][path][idx][i] = tmp & 0xfff;
+				}
+			}
+			odm_set_bb_reg(p_dm_odm, 0x1bd8, MASKDWORD, 0x0);
+			odm_set_bb_reg(p_dm_odm, 0x1b0c, BIT(13) | BIT(12), 0x0);
+		}
+	}
+}
+
+
+void
+_iqk_reload_iqk_setting_8821c(
+	struct PHY_DM_STRUCT			*p_dm_odm,
+	u8				channel,
+	u8				reload_idx  /*1: reload TX, 2: reload LO, TX, RX*/
+)
+{
+	struct _IQK_INFORMATION	*p_iqk_info = &p_dm_odm->IQK_info;
+	u8 i, path, idx;
+	u16		iqk_apply[2] = {0xc94, 0xe94};
+
+	for (path = 0; path < SS_8821C; path++) {
+#if 0
+		if (reload_idx == 2) {
+			odm_set_rf_reg(p_dm_odm, (enum odm_rf_radio_path_e)path, 0xdf, BIT(4), 0x1);
+			odm_set_rf_reg(p_dm_odm, (enum odm_rf_radio_path_e)path, 0x58, RFREGOFFSETMASK, p_iqk_info->LOK_IDAC[channel][path]);
+		}
+#endif
+		for (idx = 0; idx < reload_idx; idx++) {
+			odm_set_bb_reg(p_dm_odm, 0x1b00, MASKDWORD, 0xf8000008 | path << 1);
+			odm_set_bb_reg(p_dm_odm, 0x1b2c, MASKDWORD, 0x7);
+			odm_set_bb_reg(p_dm_odm, 0x1b38, MASKDWORD, 0x20000000);
+			odm_set_bb_reg(p_dm_odm, 0x1b3c, MASKDWORD, 0x20000000);
+			odm_set_bb_reg(p_dm_odm, 0x1bcc, MASKDWORD, 0x00000000);
+
+			if (idx == 0)
+				odm_set_bb_reg(p_dm_odm, 0x1b0c, BIT(13) | BIT(12), 0x3);
+			else
+				odm_set_bb_reg(p_dm_odm, 0x1b0c, BIT(13) | BIT(12), 0x1);
+
+			odm_set_bb_reg(p_dm_odm, 0x1bd4, BIT(20) | BIT(19) | BIT(18) | BIT(17) | BIT(16), 0x10);
+
+			for (i = 0; i < 8; i++) {
+				odm_write_4byte(p_dm_odm, 0x1bd8,	((0xc0000000 >> idx) + 0x3) + (i * 4) + (p_iqk_info->IQK_CFIR_real[channel][path][idx][i] << 9));
+				odm_write_4byte(p_dm_odm, 0x1bd8, ((0xc0000000 >> idx) + 0x1) + (i * 4) + (p_iqk_info->IQK_CFIR_imag[channel][path][idx][i] << 9));
+			}
+		}
+		odm_set_bb_reg(p_dm_odm, iqk_apply[path], MASKDWORD, p_iqk_info->bypass_iqk[channel][path]);
+
+		odm_set_bb_reg(p_dm_odm, 0x1bd8, MASKDWORD, 0x0);
+		odm_set_bb_reg(p_dm_odm, 0x1b0c, BIT(13) | BIT(12), 0x0);
+	}
+}
+
+
+boolean
+_iqk_reload_iqk_8821c(
+	struct PHY_DM_STRUCT			*p_dm_odm,
+	boolean			reset
+)
+{
+	struct _IQK_INFORMATION	*p_iqk_info = &p_dm_odm->IQK_info;
+	u8 i;
+	boolean reload = false;
+
+	if (reset) {
+		for (i = 0; i < 2; i++)
+			p_iqk_info->iqk_channel[i] = 0x0;
+	} else {
+		p_iqk_info->rf_reg18 = odm_get_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x18, RFREGOFFSETMASK);
+
+		for (i = 0; i < 2; i++) {
+			if (p_iqk_info->rf_reg18 == p_iqk_info->iqk_channel[i]) {
+				_iqk_reload_iqk_setting_8821c(p_dm_odm, i, 2);
+				_iqk_fill_iqk_report_8821c(p_dm_odm, i);
+				ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]reload IQK result before!!!!\n"));
+				reload = true;
+			}
+		}
+	}
+	return reload;
+}
+
+
+void
+_iqk_rfe_setting_8821c(
+	struct PHY_DM_STRUCT	*p_dm_odm,
+	boolean		ext_pa_on
+)
+{
+	if (ext_pa_on) {
+		/*RFE setting*/
+		odm_write_4byte(p_dm_odm, 0xcb0, 0x77777777);
+		odm_write_4byte(p_dm_odm, 0xcb4, 0x00007777);
+		odm_write_4byte(p_dm_odm, 0xcbc, 0x0000083B);
+		/*odm_write_4byte(p_dm_odm, 0x1990, 0x00000c30);*/
+		ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]external PA on!!!!\n"));
+	} else {
+		/*RFE setting*/
+		odm_write_4byte(p_dm_odm, 0xcb0, 0x77171117);
+		odm_write_4byte(p_dm_odm, 0xcb4, 0x00001177);
+		odm_write_4byte(p_dm_odm, 0xcbc, 0x00000404);
+		/*odm_write_4byte(p_dm_odm, 0x1990, 0x00000c30);*/
+		/*		ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]external PA off!!!!\n"));*/
+	}
+}
+
+void
+_iqk_rfsetting_8821c(
+	struct PHY_DM_STRUCT	*p_dm_odm
+)
+{
+	struct _IQK_INFORMATION	*p_iqk_info = &p_dm_odm->IQK_info;
+
+	u8 path;
+	u32 tmp;
+
+	odm_write_4byte(p_dm_odm, 0x1b00, 0xf8000008);
+	odm_write_4byte(p_dm_odm, 0x1bb8, 0x00000000);
+
+	for (path = 0; path < SS_8821C; path++) {
+		/*0xdf:B11 = 1,B4 = 0, B1 = 1*/
+		tmp = odm_get_rf_reg(p_dm_odm, (enum odm_rf_radio_path_e)path, 0xdf, RFREGOFFSETMASK);
+		tmp = (tmp & (~BIT(4))) | BIT(1) | BIT(11);
+		odm_set_rf_reg(p_dm_odm, (enum odm_rf_radio_path_e)path, 0xdf, RFREGOFFSETMASK, tmp);
+
+		if (p_iqk_info->is_BTG) {
+			tmp = odm_get_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0xde, RFREGOFFSETMASK);
+			tmp = (tmp & (~BIT(4))) | BIT(15);
+			/*tmp = tmp|BIT4|BIT15; //manual LOK value  for A-cut*/
+			odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0xde, RFREGOFFSETMASK, tmp);
+		}
+
+		if (!p_iqk_info->is_BTG) {
+			/*WLAN_AG*/
+			/*TX IQK	 mode init*/
+			odm_set_rf_reg(p_dm_odm, (enum odm_rf_radio_path_e)path, 0xef, RFREGOFFSETMASK, 0x80000);
+			odm_set_rf_reg(p_dm_odm, (enum odm_rf_radio_path_e)path, 0x33, RFREGOFFSETMASK, 0x00024);
+			odm_set_rf_reg(p_dm_odm, (enum odm_rf_radio_path_e)path, 0x3e, RFREGOFFSETMASK, 0x0003f);
+			odm_set_rf_reg(p_dm_odm, (enum odm_rf_radio_path_e)path, 0x3f, RFREGOFFSETMASK, 0x60fde);
+			odm_set_rf_reg(p_dm_odm, (enum odm_rf_radio_path_e)path, 0xef, RFREGOFFSETMASK, 0x00000);
+			if (*p_dm_odm->p_band_type == ODM_BAND_5G) {
+				odm_set_rf_reg(p_dm_odm, (enum odm_rf_radio_path_e)path, 0xef, BIT(19), 0x1);
+				odm_set_rf_reg(p_dm_odm, (enum odm_rf_radio_path_e)path, 0x33, RFREGOFFSETMASK, 0x00026);
+				odm_set_rf_reg(p_dm_odm, (enum odm_rf_radio_path_e)path, 0x3e, RFREGOFFSETMASK, 0x00037);
+				odm_set_rf_reg(p_dm_odm, (enum odm_rf_radio_path_e)path, 0x3f, RFREGOFFSETMASK, 0xdefce);
+				odm_set_rf_reg(p_dm_odm, (enum odm_rf_radio_path_e)path, 0xef, BIT(19), 0x0);
+			} else {
+				odm_set_rf_reg(p_dm_odm, (enum odm_rf_radio_path_e)path, 0xef, BIT(19), 0x1);
+				odm_set_rf_reg(p_dm_odm, (enum odm_rf_radio_path_e)path, 0x33, RFREGOFFSETMASK, 0x00026);
+				odm_set_rf_reg(p_dm_odm, (enum odm_rf_radio_path_e)path, 0x3e, RFREGOFFSETMASK, 0x00037);
+				odm_set_rf_reg(p_dm_odm, (enum odm_rf_radio_path_e)path, 0x3f, RFREGOFFSETMASK, 0x5efce);
+				odm_set_rf_reg(p_dm_odm, (enum odm_rf_radio_path_e)path, 0xef, BIT(19), 0x0);
+			}
+		} else {
+			/*WLAN_BTG*/
+			/*TX IQK	 mode init*/
+			odm_set_rf_reg(p_dm_odm, (enum odm_rf_radio_path_e)path, 0xee, RFREGOFFSETMASK, 0x01000);
+			odm_set_rf_reg(p_dm_odm, (enum odm_rf_radio_path_e)path, 0x33, RFREGOFFSETMASK, 0x00004);
+			odm_set_rf_reg(p_dm_odm, (enum odm_rf_radio_path_e)path, 0x3f, RFREGOFFSETMASK, 0x01ec1);
+			odm_set_rf_reg(p_dm_odm, (enum odm_rf_radio_path_e)path, 0xee, RFREGOFFSETMASK, 0x00000);
+		}
+	}
+}
+
+void
+_iqk_configure_macbb_8821c(
+	struct PHY_DM_STRUCT		*p_dm_odm
+)
+{
+	/*MACBB register setting*/
+	odm_write_1byte(p_dm_odm, 0x522, 0x7f);
+	odm_set_bb_reg(p_dm_odm, 0x1518, BIT(16), 0x1);
+	odm_set_bb_reg(p_dm_odm, 0x550, BIT(11) | BIT(3), 0x0);
+	odm_set_bb_reg(p_dm_odm, 0x90c, BIT(15), 0x1);			/*0x90c[15]=1: dac_buf reset selection*/
+	odm_set_bb_reg(p_dm_odm, 0x9a4, BIT(31), 0x0);         /*0x9a4[31]=0: Select da clock*/
+	/*0xc94[0]=1, 0xe94[0]=1: ��tx�qiqk���X��*/
+	odm_set_bb_reg(p_dm_odm, 0xc94, BIT(0), 0x1);
+	/* 3-wire off*/
+	odm_write_4byte(p_dm_odm, 0xc00, 0x00000004);
+	/*disable PMAC*/
+	odm_set_bb_reg(p_dm_odm, 0xb00, BIT(8), 0x0);
+	/*	ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]Set MACBB setting for IQK!!!!\n"));*/
+
+}
+
+
+void
+_iqk_lok_setting_8821c(
+	struct PHY_DM_STRUCT	*p_dm_odm,
+	u8 path,
+	u8          uPADindex
+)
+{
+	u32 LOK0x56_2G = 0x50ef3;
+	u32 LOK0x56_5G = 0x50ee8;
+	u32 LOK0x33 = 0;
+	u32 LOK0x78 = 0xbcbba;
+	u32 tmp = 0;
+
+	struct _IQK_INFORMATION	*p_iqk_info = &p_dm_odm->IQK_info;
+
+	LOK0x33 = uPADindex;
+/*add delay of MAC send packet*/
+	if (p_dm_odm->mp_mode)
+		odm_set_bb_reg(p_dm_odm, 0x810, BIT(7)|BIT(6)|BIT(5)|BIT(4), 0x8);
+
+	if (p_iqk_info->is_BTG) {
+		tmp = (LOK0x78 & 0x1c000) >> 14;
+		odm_write_4byte(p_dm_odm, 0x1b00, 0xf8000008 | path << 1);
+		odm_write_4byte(p_dm_odm, 0x1bcc, 0x1b);
+		odm_write_1byte(p_dm_odm, 0x1b23, 0x00);
+		odm_write_1byte(p_dm_odm, 0x1b2b, 0x80);
+		/*0x78[11:0] = IDAC value*/
+		LOK0x78 = LOK0x78 & (0xe3fff | ((u32)uPADindex << 14));
+		odm_set_rf_reg(p_dm_odm, path, 0x78, RFREGOFFSETMASK, LOK0x78);
+		odm_set_rf_reg(p_dm_odm, path, 0x5c, RFREGOFFSETMASK, 0x05320);
+		odm_set_rf_reg(p_dm_odm, path, 0x8f, RFREGOFFSETMASK, 0xac018);
+		odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0xee, BIT(4), 0x1);
+		odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x33, BIT(3), 0x0);
+		ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_TRACE, ("[IQK] In the BTG\n"));
+	} else {
+		/*tmp = (LOK0x56 & 0xe0) >> 5;*/
+		odm_write_4byte(p_dm_odm, 0x1b00, 0xf8000008 | path << 1);
+		odm_write_4byte(p_dm_odm, 0x1bcc, 0x9);
+		odm_write_1byte(p_dm_odm, 0x1b23, 0x00);
+
+		switch (*p_dm_odm->p_band_type) {
+		case ODM_BAND_2_4G:
+			odm_write_1byte(p_dm_odm, 0x1b2b, 0x00);
+			LOK0x56_2G = LOK0x56_2G & (0xfff1f | ((u32)uPADindex << 5));
+			odm_set_rf_reg(p_dm_odm, path, 0x56, RFREGOFFSETMASK, LOK0x56_2G);
+			odm_set_rf_reg(p_dm_odm, path, 0x8f, RFREGOFFSETMASK, 0xadc18);
+			odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0xef, BIT(4), 0x1);
+			odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x33, BIT(3), 0x0);
+			break;
+		case ODM_BAND_5G:
+			odm_write_1byte(p_dm_odm, 0x1b2b, 0x00);
+			LOK0x56_5G = LOK0x56_5G & (0xfff1f | ((u32)uPADindex << 5));
+			odm_set_rf_reg(p_dm_odm, path, 0x56, RFREGOFFSETMASK, LOK0x56_5G);
+			odm_set_rf_reg(p_dm_odm, path, 0x8f, RFREGOFFSETMASK, 0xadc18);
+			odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0xef, BIT(4), 0x1);
+			odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x33, BIT(3), 0x1);
+			break;
+		}
+	}
+	/*for IDAC LUT by PAD idx*/
+	odm_set_rf_reg(p_dm_odm, path, 0x33, BIT(2) | BIT(1) | BIT(0), LOK0x33);
+	ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_TRACE,
+		("[IQK] LOK0x33 = 0x%x, LOK0x56_2G = 0x%x, LOK0x56_5G = 0x%x,LOK0x78 =0x%x\n",
+		      LOK0x33, LOK0x56_2G, LOK0x56_5G, LOK0x78));
+	/*	ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]Set LOK setting!!!!\n"));*/
+}
+
+
+void
+_iqk_txk_setting_8821c(
+	struct PHY_DM_STRUCT	*p_dm_odm,
+	u8 path
+)
+{
+	struct _IQK_INFORMATION	*p_iqk_info = &p_dm_odm->IQK_info;
+
+	if (p_iqk_info->is_BTG) {
+		odm_write_4byte(p_dm_odm, 0x1b00, 0xf8000008 | path << 1);
+		odm_write_4byte(p_dm_odm, 0x1bcc, 0x1b);
+		odm_write_4byte(p_dm_odm, 0x1b20, 0x00840008);
+
+		/*0x78[11:0] = IDAC value*/
+		odm_set_rf_reg(p_dm_odm, path, 0x78, RFREGOFFSETMASK, 0xbcbba);
+		odm_set_rf_reg(p_dm_odm, path, 0x5c, RFREGOFFSETMASK, 0x04320);
+		odm_set_rf_reg(p_dm_odm, path, 0x8f, RFREGOFFSETMASK, 0xac018);
+		odm_write_1byte(p_dm_odm, 0x1b2b, 0x80);
+	} else {
+		odm_write_4byte(p_dm_odm, 0x1b00, 0xf8000008 | path << 1);
+		odm_write_4byte(p_dm_odm, 0x1bcc, 0x9);
+		odm_write_4byte(p_dm_odm, 0x1b20, 0x01440008);
+
+		switch (*p_dm_odm->p_band_type) {
+		case ODM_BAND_2_4G:
+			odm_set_rf_reg(p_dm_odm, path, 0x56, RFREGOFFSETMASK, 0x50EF3);
+			odm_set_rf_reg(p_dm_odm, path, 0x8f, RFREGOFFSETMASK, 0xadc18);
+			odm_write_1byte(p_dm_odm, 0x1b2b, 0x00);
+			break;
+		case ODM_BAND_5G:
+			odm_set_rf_reg(p_dm_odm, path, 0x56, RFREGOFFSETMASK, 0x50EF0);
+			odm_set_rf_reg(p_dm_odm, path, 0x8f, RFREGOFFSETMASK, 0xa9c18);
+			odm_write_1byte(p_dm_odm, 0x1b2b, 0x00);
+			break;
+		}
+
+	}
+	/*	ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]Set TXK setting!!!!\n"));*/
+}
+
+
+void
+_iqk_rxk1setting_8821c(
+	struct PHY_DM_STRUCT	*p_dm_odm,
+	u8 path
+)
+{
+	struct _IQK_INFORMATION	*p_iqk_info = &p_dm_odm->IQK_info;
+
+	if (p_iqk_info->is_BTG) {
+		odm_write_4byte(p_dm_odm, 0x1b00, 0xf8000008 | path << 1);
+		odm_write_1byte(p_dm_odm, 0x1b2b, 0x80);
+		odm_write_4byte(p_dm_odm, 0x1bcc, 0x09);
+		odm_write_4byte(p_dm_odm, 0x1b20, 0x01450008);
+		odm_write_4byte(p_dm_odm, 0x1b24, 0x01460c88);
+
+		/*0x78[11:0] = IDAC value*/
+		odm_set_rf_reg(p_dm_odm, path, 0x78, RFREGOFFSETMASK, 0x8cbba);
+		odm_set_rf_reg(p_dm_odm, path, 0x5c, RFREGOFFSETMASK, 0x00320);
+		odm_set_rf_reg(p_dm_odm, path, 0x8f, RFREGOFFSETMASK, 0xa8018);
+	} else {
+		odm_write_4byte(p_dm_odm, 0x1b00, 0xf8000008 | path << 1);
+		switch (*p_dm_odm->p_band_type) {
+		case ODM_BAND_2_4G:
+			odm_write_1byte(p_dm_odm, 0x1bcc, 0x12);
+			odm_write_1byte(p_dm_odm, 0x1b2b, 0x00);
+			odm_write_4byte(p_dm_odm, 0x1b20, 0x01450008);
+			odm_write_4byte(p_dm_odm, 0x1b24, 0x01461068);
+
+			odm_set_rf_reg(p_dm_odm, path, 0x56, RFREGOFFSETMASK, 0x510f3);
+			odm_set_rf_reg(p_dm_odm, path, 0x8f, RFREGOFFSETMASK, 0xa9c00);
+			break;
+		case ODM_BAND_5G:
+			odm_write_1byte(p_dm_odm, 0x1bcc, 0x9);
+			odm_write_1byte(p_dm_odm, 0x1b2b, 0x00);
+			odm_write_4byte(p_dm_odm, 0x1b20, 0x00450008);
+			odm_write_4byte(p_dm_odm, 0x1b24, 0x00461468);
+
+			odm_set_rf_reg(p_dm_odm, path, 0x56, RFREGOFFSETMASK, 0x510f3);
+			odm_set_rf_reg(p_dm_odm, path, 0x8f, RFREGOFFSETMASK, 0xa9c00);
+			break;
+		}
+	}
+	/*ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]Set RXK setting!!!!\n"));*/
+}
+
+static	u8	btg_lna[5] = {0x0, 0x4, 0x8, 0xc, 0xf};
+static	u8	wlg_lna[5] = {0x0, 0x1, 0x2, 0x3, 0x5};
+static	u8	wla_lna[5] = {0x0, 0x1, 0x3, 0x4, 0x5};
+
+void
+_iqk_rxk2setting_8821c(
+	struct PHY_DM_STRUCT	*p_dm_odm,
+	u8 path,
+	boolean is_gs
+)
+{
+	struct _IQK_INFORMATION	*p_iqk_info = &p_dm_odm->IQK_info;
+
+	if (p_iqk_info->is_BTG) {
+		if (is_gs) {
+			p_iqk_info->tmp1bcc = 0x1b;
+			p_iqk_info->lna_idx = 2;
+		}
+		odm_write_4byte(p_dm_odm, 0x1b00, 0xf8000008 | path << 1);
+		odm_write_1byte(p_dm_odm, 0x1b2b, 0x80);
+		odm_write_4byte(p_dm_odm, 0x1bcc, p_iqk_info->tmp1bcc);
+		odm_write_4byte(p_dm_odm, 0x1b20, 0x01450008);
+		odm_write_4byte(p_dm_odm, 0x1b24, (0x01460048 | (btg_lna[p_iqk_info->lna_idx] << 10)));
+		/*0x78[11:0] = IDAC value*/
+		odm_set_rf_reg(p_dm_odm, path, 0x78, RFREGOFFSETMASK, 0x8cbba);
+		odm_set_rf_reg(p_dm_odm, path, 0x5c, RFREGOFFSETMASK, 0x00320);
+		odm_set_rf_reg(p_dm_odm, path, 0x8f, RFREGOFFSETMASK, 0xa8018);
+	} else {
+		odm_write_4byte(p_dm_odm, 0x1b00, 0xf8000008 | path << 1);
+		switch (*p_dm_odm->p_band_type) {
+		case ODM_BAND_2_4G:
+			if (is_gs) {
+				p_iqk_info->tmp1bcc = 0x12;
+				p_iqk_info->lna_idx = 2;
+			}
+			odm_write_1byte(p_dm_odm, 0x1bcc, p_iqk_info->tmp1bcc);
+			odm_write_1byte(p_dm_odm, 0x1b2b, 0x00);
+			odm_write_4byte(p_dm_odm, 0x1b20, 0x01450008);
+			odm_write_4byte(p_dm_odm, 0x1b24, (0x01460048 | (wlg_lna[p_iqk_info->lna_idx] << 10)));
+			odm_set_rf_reg(p_dm_odm, path, 0x56, RFREGOFFSETMASK, 0x510f3);
+			odm_set_rf_reg(p_dm_odm, path, 0x8f, RFREGOFFSETMASK, 0xa9c00);
+			break;
+		case ODM_BAND_5G:
+			if (is_gs) {
+				p_iqk_info->tmp1bcc = 0x12;
+				p_iqk_info->lna_idx = 2;
+			}
+			odm_write_1byte(p_dm_odm, 0x1bcc, p_iqk_info->tmp1bcc);
+			odm_write_1byte(p_dm_odm, 0x1b2b, 0x00);
+			odm_write_4byte(p_dm_odm, 0x1b20, 0x00450008);
+			odm_write_4byte(p_dm_odm, 0x1b24, (0x01460048 | (wla_lna[p_iqk_info->lna_idx] << 10)));
+			odm_set_rf_reg(p_dm_odm, path, 0x56, RFREGOFFSETMASK, 0x51000);
+			odm_set_rf_reg(p_dm_odm, path, 0x8f, RFREGOFFSETMASK, 0xa9c00);
+			break;
+		}
+	}
+	/*	ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]Set RXK setting!!!!\n"));*/
+
+}
+
+boolean
+_iqk_check_cal_8821c(
+	struct PHY_DM_STRUCT			*p_dm_odm,
+	u32				IQK_CMD
+)
+{
+	boolean		notready = true, fail = true;
+	u32		delay_count = 0x0;
+
+	while (notready) {
+		if (odm_read_4byte(p_dm_odm, 0x1b00) == (IQK_CMD & 0xffffff0f)) {
+			fail = (boolean) odm_get_bb_reg(p_dm_odm, 0x1b08, BIT(26));
+			notready = false;
+		} else {
+			ODM_delay_ms(1);
+			delay_count++;
+		}
+
+		if (delay_count >= 50) {
+			fail = true;
+			ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD,
+				     ("[IQK]IQK timeout!!!\n"));
+			break;
+		}
+	}
+	ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD,
+		     ("[IQK]delay count = 0x%x!!!\n", delay_count));
+	return fail;
+}
+
+
+boolean
+_iqk_rx_iqk_gain_search_fail_8821c(
+	struct PHY_DM_STRUCT			*p_dm_odm,
+	u8		path,
+	u8		step
+)
+{
+	struct _IQK_INFORMATION	*p_iqk_info = &p_dm_odm->IQK_info;
+	boolean		fail = true;
+	u32	IQK_CMD = 0x0, rf_reg0, tmp, rxbb;
+	u8	IQMUX[4] = {0x9, 0x12, 0x1b, 0x24}, *plna;
+	u8	idx;
+	u8	lna_setting[5];
+
+	if (p_iqk_info->is_BTG)
+		plna = btg_lna;
+	else if (*p_dm_odm->p_band_type == ODM_BAND_2_4G)
+		plna = wlg_lna;
+	else
+		plna = wla_lna;
+
+
+	for (idx = 0; idx < 4; idx++)
+		if (p_iqk_info->tmp1bcc == IQMUX[idx])
+			break;
+
+	odm_write_4byte(p_dm_odm, 0x1b00, 0xf8000008 | path << 1);
+	odm_write_4byte(p_dm_odm, 0x1bcc, p_iqk_info->tmp1bcc);
+
+	if (step == RXIQK1)
+		ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]============ S%d RXIQK GainSearch ============\n", p_iqk_info->is_BTG));
+
+	if (step == RXIQK1)
+		IQK_CMD = 0xf8000208 | (1 << (path + 4));
+	else
+		IQK_CMD = 0xf8000308 | (1 << (path + 4));
+
+	ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_TRACE, ("[IQK]S%d GS%d_Trigger = 0x%x\n", path, step, IQK_CMD));
+
+	_iqk_set_gnt_wl_gnt_bt(p_dm_odm, true);
+	odm_write_4byte(p_dm_odm, 0x1b00, IQK_CMD);
+	odm_write_4byte(p_dm_odm, 0x1b00, IQK_CMD + 0x1);
+	ODM_delay_ms(GS_delay_8821C);
+	fail = _iqk_check_cal_8821c(p_dm_odm, IQK_CMD);
+	RT_TRACE(COMP_COEX, DBG_LOUD, ("[IQK]check 0x49c = %x\n", odm_read_1byte(p_dm_odm, 0x49c)));
+	_iqk_set_gnt_wl_gnt_bt(p_dm_odm, false);
+
+	if (step == RXIQK2) {
+		rf_reg0 = odm_get_rf_reg(p_dm_odm, (enum odm_rf_radio_path_e)path, 0x0, RFREGOFFSETMASK);
+		odm_write_4byte(p_dm_odm, 0x1b00, 0xf8000008 | path << 1);
+		ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_TRACE,
+			("[IQK]S%d ==> RF0x0 = 0x%x, tmp1bcc = 0x%x, idx = %d, 0x1b3c = 0x%x\n", path, rf_reg0, p_iqk_info->tmp1bcc, idx, odm_read_4byte(p_dm_odm, 0x1b3c)));
+		tmp = (rf_reg0 & 0x1fe0) >> 5;
+		rxbb = tmp & 0x1f;
+#if 1
+
+		if (rxbb == 0x1) {
+			if (idx != 3)
+				idx++;
+			else if (p_iqk_info->lna_idx != 0x0)
+				p_iqk_info->lna_idx--;
+			else
+				p_iqk_info->isbnd = true;
+			fail = true;
+		} else if (rxbb == 0xa) {
+			if (idx != 0)
+				idx--;
+			else if (p_iqk_info->lna_idx != 0x4)
+				p_iqk_info->lna_idx++;
+			else
+				p_iqk_info->isbnd = true;
+			fail = true;
+		} else
+			fail = false;
+
+		if (p_iqk_info->isbnd == true)
+			fail = false;
+#endif
+
+#if 0
+		if (rxbb == 0x1) {
+			if (p_iqk_info->lna_idx != 0x0)
+				p_iqk_info->lna_idx--;
+			else if (idx != 3)
+				idx++;
+			else
+				p_iqk_info->isbnd = true;
+			fail = true;
+		} else if (rxbb == 0xa) {
+			if (idx != 0)
+				idx--;
+			else if (p_iqk_info->lna_idx != 0x7)
+				p_iqk_info->lna_idx++;
+			else
+				p_iqk_info->isbnd = true;
+			fail = true;
+		} else
+			fail = false;
+
+		if (p_iqk_info->isbnd == true)
+			fail = false;
+#endif
+		p_iqk_info->tmp1bcc = IQMUX[idx];
+
+		if (fail) {
+			odm_write_4byte(p_dm_odm, 0x1b00, 0xf8000008 | path << 1);
+			odm_write_4byte(p_dm_odm, 0x1b24, (odm_read_4byte(p_dm_odm, 0x1b24) & 0xffffc3ff) | (*(plna + p_iqk_info->lna_idx) << 10));
+		}
+	}
+	return fail;
+}
+
+boolean
+_lok_one_shot_8821c(
+	struct PHY_DM_STRUCT	*p_dm_void,
+	u8 path,
+	u8          uPADindex
+
+)
+{
+	struct PHY_DM_STRUCT	*p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
+	struct _IQK_INFORMATION	*p_iqk_info = &p_dm_odm->IQK_info;
+	u8		delay_count = 0, i;
+	boolean		LOK_notready = false;
+	u32		LOK_temp1 = 0, LOK_temp2 = 0, LOK_temp3 = 0;
+	u32		IQK_CMD = 0x0;
+	u8		LOKreg[] = {0x58, 0x78};
+
+	ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_TRACE,
+		("[IQK]==========S%d LOK ==========\n", p_iqk_info->is_BTG));
+
+	IQK_CMD = 0xf8000008 | (1 << (4 + path));
+
+	ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_TRACE, ("[IQK]LOK_Trigger = 0x%x\n", IQK_CMD));
+
+	_iqk_set_gnt_wl_gnt_bt(p_dm_odm, true);
+	odm_write_4byte(p_dm_odm, 0x1b00, IQK_CMD);
+	odm_write_4byte(p_dm_odm, 0x1b00, IQK_CMD + 1);
+	/*LOK: CMD ID = 0	{0xf8000018, 0xf8000028}*/
+	/*LOK: CMD ID = 0	{0xf8000019, 0xf8000029}*/
+	ODM_delay_ms(LOK_delay_8821C);
+
+	delay_count = 0;
+	LOK_notready = true;
+
+	while (LOK_notready) {
+		if (odm_read_4byte(p_dm_odm, 0x1b00) == (IQK_CMD & 0xffffff0f))
+			LOK_notready = false;
+		else
+			LOK_notready = true;
+
+		if (LOK_notready) {
+			ODM_delay_ms(1);
+			delay_count++;
+		}
+
+		if (delay_count >= 50) {
+			ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD,
+				     ("[IQK]S%d LOK timeout!!!\n", path));
+			break;
+		}
+	}
+
+	_iqk_set_gnt_wl_gnt_bt(p_dm_odm, false);
+	ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_TRACE,
+		     ("[IQK]S%d ==> delay_count = 0x%x\n", path, delay_count));
+
+	if (!LOK_notready) {
+		LOK_temp2 = odm_get_rf_reg(p_dm_odm, (enum odm_rf_radio_path_e)path, 0x8, RFREGOFFSETMASK);
+		LOK_temp3 = odm_get_rf_reg(p_dm_odm, (enum odm_rf_radio_path_e)path, 0x58, RFREGOFFSETMASK);
+
+		ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_TRACE,
+			("[IQK]0x8 = 0x%x, 0x58 = 0x%x\n", LOK_temp2, LOK_temp3));
+	} else {
+		ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_TRACE,
+			     ("[IQK]==>S%d LOK Fail!!!\n", path));
+	}
+	p_iqk_info->LOK_fail[path] = LOK_notready;
+
+	/*fill IDAC LUT table*/
+	/*
+	for (i = 0; i < 8; i++) {
+		odm_set_rf_reg(p_dm_odm, path, 0x33, BIT(2)|BIT(1)|BIT(0), i);
+		odm_set_rf_reg(p_dm_odm, path, 0x8, RFREGOFFSETMASK, LOK_temp2);
+	}
+	*/
+	return LOK_notready;
+}
+
+boolean
+_iqk_one_shot_8821c(
+	void		*p_dm_void,
+	u8		path,
+	u8		idx
+)
+{
+	struct PHY_DM_STRUCT	*p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
+	struct _IQK_INFORMATION	*p_iqk_info = &p_dm_odm->IQK_info;
+	u8		delay_count = 0;
+	boolean		notready = true, fail = true, search_fail = true;
+	u32		IQK_CMD = 0x0, tmp;
+	u16		iqk_apply[2] = {0xc94, 0xe94};
+
+	if (idx == TX_IQK)
+		ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]============ S%d WBTXIQK ============\n", p_iqk_info->is_BTG));
+	else if (idx == RXIQK1)
+		ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]============ S%d WBRXIQK STEP1============\n", p_iqk_info->is_BTG));
+	else
+		ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]============ S%d WBRXIQK STEP2============\n", p_iqk_info->is_BTG));
+
+	if (idx == TXIQK) {
+		IQK_CMD = 0xf8000008 | ((*p_dm_odm->p_band_width + 4) << 8) | (1 << (path + 4));
+		ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_TRACE, ("[IQK]TXK_Trigger = 0x%x\n", IQK_CMD));
+		/*{0xf8000418, 0xf800042a} ==> 20 WBTXK (CMD = 4)*/
+		/*{0xf8000518, 0xf800052a} ==> 40 WBTXK (CMD = 5)*/
+		/*{0xf8000618, 0xf800062a} ==> 80 WBTXK (CMD = 6)*/
+	} else if (idx == RXIQK1) {
+		if (*p_dm_odm->p_band_width == 2)
+			IQK_CMD = 0xf8000808 | (1 << (path + 4));
+		else
+			IQK_CMD = 0xf8000708 | (1 << (path + 4));
+		ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_TRACE, ("[IQK]RXK1_Trigger = 0x%x\n", IQK_CMD));
+		/*{0xf8000718, 0xf800072a} ==> 20 WBTXK (CMD = 7)*/
+		/*{0xf8000718, 0xf800072a} ==> 40 WBTXK (CMD = 7)*/
+		/*{0xf8000818, 0xf800082a} ==> 80 WBTXK (CMD = 8)*/
+	} else if (idx == RXIQK2) {
+		IQK_CMD = 0xf8000008 | ((*p_dm_odm->p_band_width + 9) << 8) | (1 << (path + 4));
+		ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_TRACE, ("[IQK]RXK2_Trigger = 0x%x\n", IQK_CMD));
+		/*{0xf8000918, 0xf800092a} ==> 20 WBRXK (CMD = 9)*/
+		/*{0xf8000a18, 0xf8000a2a} ==> 40 WBRXK (CMD = 10)*/
+		/*{0xf8000b18, 0xf8000b2a} ==> 80 WBRXK (CMD = 11)*/
+	}
+
+	_iqk_set_gnt_wl_gnt_bt(p_dm_odm, true);
+
+
+	odm_write_4byte(p_dm_odm, 0x1bc8, 0x80000000);
+	odm_write_4byte(p_dm_odm, 0x8f8, 0x41400080);
+
+
+	odm_write_4byte(p_dm_odm, 0x1b00, IQK_CMD);
+	odm_write_4byte(p_dm_odm, 0x1b00, IQK_CMD + 0x1);
+	ODM_delay_ms(WBIQK_delay_8821C);
+
+
+	while (notready) {
+		if (odm_read_4byte(p_dm_odm, 0xfa0) & BIT(27))/*if (odm_read_4byte(p_dm_odm, 0x1b00) == (IQK_CMD & 0xffffff0f))*/
+			notready = false;
+		else
+			notready = true;
+
+		if (notready) {
+			ODM_delay_ms(1);
+			delay_count++;
+		} else {
+			fail = (boolean) odm_get_bb_reg(p_dm_odm, 0x1b08, BIT(26));
+			break;
+		}
+
+		if (delay_count >= 50) {
+			ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD,
+				     ("[IQK]S%d IQK timeout!!!\n", path));
+			break;
+		}
+	}
+
+	RT_TRACE(COMP_COEX, DBG_LOUD, ("[IQK]check 0x49c = %x\n", odm_read_1byte(p_dm_odm, 0x49c)));
+	_iqk_set_gnt_wl_gnt_bt(p_dm_odm, false);
+
+	if (p_dm_odm->debug_components && ODM_COMP_CALIBRATION) {
+		odm_write_4byte(p_dm_odm, 0x1b00, 0xf8000008 | path << 1);
+		ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_TRACE,
+			("[IQK]S%d ==> 0x1b00 = 0x%x, 0x1b08 = 0x%x\n", path, odm_read_4byte(p_dm_odm, 0x1b00), odm_read_4byte(p_dm_odm, 0x1b08)));
+		ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_TRACE,
+			("[IQK]S%d ==> delay_count = 0x%x\n", path, delay_count));
+		if (idx != TXIQK)
+			ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_TRACE,
+				("[IQK]S%d ==> RF0x0 = 0x%x, RF0x%x = 0x%x\n", path,
+				odm_get_rf_reg(p_dm_odm, path, 0x0, RFREGOFFSETMASK), (p_iqk_info->is_BTG) ? 0x78 : 0x56,
+				(p_iqk_info->is_BTG) ? odm_get_rf_reg(p_dm_odm, path, 0x78, RFREGOFFSETMASK) : odm_get_rf_reg(p_dm_odm, path, 0x56, RFREGOFFSETMASK)));
+	}
+
+	odm_write_4byte(p_dm_odm, 0x1b00, 0xf8000008 | path << 1);
+	if (idx == TXIQK)
+		if (fail)
+			odm_set_bb_reg(p_dm_odm, iqk_apply[path], BIT(0), 0x0);
+
+	if (idx == RXIQK2) {
+		p_iqk_info->RXIQK_AGC[0][path] =
+			(u16)(((odm_get_rf_reg(p_dm_odm, (enum odm_rf_radio_path_e)path, 0x0, RFREGOFFSETMASK) >> 5) & 0xff) |
+			      (p_iqk_info->tmp1bcc << 8));
+
+		odm_write_4byte(p_dm_odm, 0x1b38, 0x20000000);
+
+		if (!fail)
+			odm_set_bb_reg(p_dm_odm, iqk_apply[path], (BIT(11) | BIT(10)), 0x1);
+		else
+			odm_set_bb_reg(p_dm_odm, iqk_apply[path], (BIT(11) | BIT(10)), 0x0);
+	}
+
+	if (idx == TXIQK)
+		p_iqk_info->IQK_fail_report[0][path][TXIQK] = fail;
+	else
+		p_iqk_info->IQK_fail_report[0][path][RXIQK] = fail;
+
+	return fail;
+}
+
+boolean
+_iqk_rxiqkbystep_8821c(
+	void		*p_dm_void,
+	u8		path
+)
+{
+	struct PHY_DM_STRUCT	*p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
+	struct _IQK_INFORMATION	*p_iqk_info = &p_dm_odm->IQK_info;
+	boolean		KFAIL = true, gonext;
+
+#if 1
+	switch (p_iqk_info->rxiqk_step) {
+	case 1:		/*gain search_RXK1*/
+		_iqk_rxk1setting_8821c(p_dm_odm, path);
+		gonext = false;
+		while (1) {
+			KFAIL = _iqk_rx_iqk_gain_search_fail_8821c(p_dm_odm, path, RXIQK1);
+			if (KFAIL && (p_iqk_info->gs_retry_count[0][path][RXIQK1] < 2))
+				p_iqk_info->gs_retry_count[0][path][RXIQK1]++;
+			else if (KFAIL) {
+				p_iqk_info->RXIQK_fail_code[0][path] = 0;
+				p_iqk_info->rxiqk_step = 5;
+				gonext = true;
+			} else {
+				p_iqk_info->rxiqk_step++;
+				gonext = true;
+			}
+			if (gonext)
+				break;
+		}
+		break;
+	case 2:		/*gain search_RXK2*/
+		_iqk_rxk2setting_8821c(p_dm_odm, path, true);
+		p_iqk_info->isbnd = false;
+		while (1) {
+			KFAIL = _iqk_rx_iqk_gain_search_fail_8821c(p_dm_odm, path, RXIQK2);
+			if (KFAIL && (p_iqk_info->gs_retry_count[0][path][RXIQK2] < rxiqk_gs_limit))
+				p_iqk_info->gs_retry_count[0][path][RXIQK2]++;
+			else {
+				p_iqk_info->rxiqk_step++;
+				break;
+			}
+		}
+		break;
+	case 3:		/*RXK1*/
+		_iqk_rxk1setting_8821c(p_dm_odm, path);
+		gonext = false;
+		while (1) {
+			KFAIL = _iqk_one_shot_8821c(p_dm_odm, path, RXIQK1);
+			if (KFAIL && (p_iqk_info->retry_count[0][path][RXIQK1] < 2))
+				p_iqk_info->retry_count[0][path][RXIQK1]++;
+			else if (KFAIL) {
+				p_iqk_info->RXIQK_fail_code[0][path] = 1;
+				p_iqk_info->rxiqk_step = 5;
+				gonext = true;
+			} else {
+				p_iqk_info->rxiqk_step++;
+				gonext = true;
+			}
+			if (gonext)
+				break;
+		}
+		break;
+	case 4:		/*RXK2*/
+		_iqk_rxk2setting_8821c(p_dm_odm, path, false);
+		gonext = false;
+		while (1) {
+			KFAIL = _iqk_one_shot_8821c(p_dm_odm, path,	RXIQK2);
+			if (KFAIL && (p_iqk_info->retry_count[0][path][RXIQK2] < 2))
+				p_iqk_info->retry_count[0][path][RXIQK2]++;
+			else if (KFAIL) {
+				p_iqk_info->RXIQK_fail_code[0][path] = 2;
+				p_iqk_info->rxiqk_step = 5;
+				gonext = true;
+			} else {
+				p_iqk_info->rxiqk_step++;
+				gonext = true;
+			}
+			if (gonext)
+				break;
+		}
+		break;
+	}
+	return KFAIL;
+#endif
+}
+
+
+void
+_iqk_iqk_by_path_8821c(
+	void		*p_dm_void,
+	boolean		segment_iqk
+)
+{
+	struct PHY_DM_STRUCT	*p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
+	struct _IQK_INFORMATION	*p_iqk_info = &p_dm_odm->IQK_info;
+	boolean		KFAIL = true;
+	u8		i, kcount_limit;
+	u32		cnt_iqk_fail = 0;
+	/*	ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_TRACE, ("[IQK]iqk_step = 0x%x\n", p_dm_odm->rf_calibrate_info.iqk_step)); */
+
+	if (*p_dm_odm->p_band_width == 2)
+		kcount_limit = kcount_limit_80m;
+	else
+		kcount_limit = kcount_limit_others;
+
+	while (1) {
+		switch (p_dm_odm->rf_calibrate_info.iqk_step) {
+		case 1:		/*S0 LOK*/
+			for (i = 0; i < 8 ; i++) {/* the LOK Cal in the each PAD stage*/
+				_iqk_lok_setting_8821c(p_dm_odm, ODM_RF_PATH_A, i);
+				_lok_one_shot_8821c(p_dm_odm, ODM_RF_PATH_A, i);
+			}
+			p_dm_odm->rf_calibrate_info.iqk_step++;
+			break;
+		case 2:		/*S0 TXIQK*/
+			_iqk_txk_setting_8821c(p_dm_odm, ODM_RF_PATH_A);
+			KFAIL = _iqk_one_shot_8821c(p_dm_odm, ODM_RF_PATH_A, TXIQK);
+			p_iqk_info->kcount++;
+			ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_TRACE, ("[IQK]KFail = 0x%x\n", KFAIL));
+			if (KFAIL)
+				cnt_iqk_fail++;
+			if (KFAIL && (p_iqk_info->retry_count[0][ODM_RF_PATH_A][TXIQK] < 3))
+				p_iqk_info->retry_count[0][ODM_RF_PATH_A][TXIQK]++;
+			else
+				p_dm_odm->rf_calibrate_info.iqk_step++;
+			break;
+		case 3:		/*S0 RXIQK*/
+			while (1) {
+				KFAIL = _iqk_rxiqkbystep_8821c(p_dm_odm, ODM_RF_PATH_A);
+				ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_TRACE, ("[IQK]S0RXK KFail = 0x%x\n", KFAIL));
+				if (p_iqk_info->rxiqk_step == 5) {
+					p_dm_odm->rf_calibrate_info.iqk_step++;
+					p_iqk_info->rxiqk_step = 1;
+					if (KFAIL) {
+						cnt_iqk_fail++;
+						ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD,
+							("[IQK]S0RXK fail code: %d!!!\n", p_iqk_info->RXIQK_fail_code[0][ODM_RF_PATH_A]));
+					}
+					break;
+				}
+			}
+			p_iqk_info->kcount++;
+			break;
+		}
+
+
+		if (p_dm_odm->rf_calibrate_info.iqk_step == 4) {
+			ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_TRACE,
+				("[IQK]==========LOK summary ==========\n"));
+			ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD,
+				     ("[IQK]PathA_LOK_notready = %d\n",
+				      p_iqk_info->LOK_fail[ODM_RF_PATH_A]));
+			ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_TRACE,
+				("[IQK]==========IQK summary ==========\n"));
+			ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD,
+				     ("[IQK]PathA_TXIQK_fail = %d\n",
+				p_iqk_info->IQK_fail_report[0][ODM_RF_PATH_A][TXIQK]));
+			ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD,
+				     ("[IQK]PathA_RXIQK_fail = %d\n",
+				p_iqk_info->IQK_fail_report[0][ODM_RF_PATH_A][RXIQK]));
+			ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD,
+				     ("[IQK]PathA_TXIQK_retry = %d\n",
+				p_iqk_info->retry_count[0][ODM_RF_PATH_A][TXIQK]));
+			ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD,
+				("[IQK]PathA_RXK1_retry = %d, PathA_RXK2_retry = %d\n",
+				p_iqk_info->retry_count[0][ODM_RF_PATH_A][RXIQK1], p_iqk_info->retry_count[0][ODM_RF_PATH_A][RXIQK2]));
+			ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD,
+				("[IQK]PathA_GS1_retry = %d, PathA_GS2_retry = %d\n",
+				p_iqk_info->gs_retry_count[0][ODM_RF_PATH_A][RXIQK1], p_iqk_info->gs_retry_count[0][ODM_RF_PATH_A][RXIQK2]));
+
+			for (i = 0; i < SS_8821C; i++) {
+				odm_write_4byte(p_dm_odm, 0x1b00, 0xf8000008 | i << 1);
+				odm_write_4byte(p_dm_odm, 0x1b2c, 0x7);
+				odm_write_4byte(p_dm_odm, 0x1bcc, 0x0);
+				odm_write_4byte(p_dm_odm, 0x1b38, 0x20000000);
+			}
+			break;
+		}
+
+		p_dm_odm->n_iqk_cnt++;
+
+		if (cnt_iqk_fail == 0)
+			p_dm_odm->n_iqk_ok_cnt++;
+		else
+			p_dm_odm->n_iqk_fail_cnt = p_dm_odm->n_iqk_fail_cnt + cnt_iqk_fail;
+
+		ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD,
+			("All/Ok/Fail = %d %d %d\n", p_dm_odm->n_iqk_cnt, p_dm_odm->n_iqk_ok_cnt, p_dm_odm->n_iqk_fail_cnt));
+
+		if ((segment_iqk == true) && (p_iqk_info->kcount == kcount_limit))
+			break;
+
+	}
+}
+
+void
+_iqk_start_iqk_8821c(
+	struct PHY_DM_STRUCT		*p_dm_odm,
+	boolean			segment_iqk
+)
+{
+	struct _IQK_INFORMATION	*p_iqk_info = &p_dm_odm->IQK_info;
+
+	u32 tmp;
+
+	odm_write_4byte(p_dm_odm, 0x1b00, 0xf8000008);
+	odm_write_4byte(p_dm_odm, 0x1bb8, 0x00000000);
+
+	/*GNT_WL = 1*/
+	if (p_iqk_info->is_BTG) {
+		tmp = odm_get_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x1, RFREGOFFSETMASK);
+		tmp = (tmp & (~BIT(3))) | BIT(0) | BIT(2);
+		odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x1, RFREGOFFSETMASK, tmp);
+	}
+
+	_iqk_iqk_by_path_8821c(p_dm_odm, segment_iqk);
+}
+
+void
+_iq_calibrate_8821c_init(
+	void		*p_dm_void
+)
+{
+	struct PHY_DM_STRUCT	*p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
+	struct _IQK_INFORMATION	*p_iqk_info = &p_dm_odm->IQK_info;
+	u8	i, j, k, m;
+
+	if (p_iqk_info->iqk_times == 0x0) {
+		ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]=====>PHY_IQCalibrate_8821C_Init\n"));
+
+		for (i = 0; i < SS_8821C; i++) {
+			for (j = 0; j < 2; j++) {
+				p_iqk_info->LOK_fail[i] = true;
+				p_iqk_info->IQK_fail[j][i] = true;
+				p_iqk_info->iqc_matrix[j][i] = 0x20000000;
+			}
+		}
+
+		for (i = 0; i < 2; i++) {
+			p_iqk_info->iqk_channel[i] = 0x0;
+
+			for (j = 0; j < SS_8821C; j++) {
+				p_iqk_info->LOK_IDAC[i][j] = 0x0;
+				p_iqk_info->RXIQK_AGC[i][j] = 0x0;
+				p_iqk_info->bypass_iqk[i][j] = 0x0;
+
+				for (k = 0; k < 2; k++) {
+					p_iqk_info->IQK_fail_report[i][j][k] = true;
+					for (m = 0; m < 8; m++) {
+						p_iqk_info->IQK_CFIR_real[i][j][k][m] = 0x0;
+						p_iqk_info->IQK_CFIR_imag[i][j][k][m] = 0x0;
+					}
+				}
+
+				for (k = 0; k < 3; k++)
+					p_iqk_info->retry_count[i][j][k] = 0x0;
+			}
+		}
+	}
+}
+/*
+void
+_DPK_BackupReg_8821C(
+	struct PHY_DM_STRUCT*	p_dm_odm,
+	static u32*	DPK_backup,
+	u32*		backup_dpk_reg
+	)
+{
+
+	u32 i;
+
+	for (i = 0; i < DPK_BACKUP_REG_NUM_8821C; i++)
+		DPK_backup[i] = odm_read_4byte(p_dm_odm, backup_dpk_reg[i]);
+
+}
+void
+_DPK_Restore_8821C(
+	struct PHY_DM_STRUCT*		p_dm_odm,
+	static  u32*		DPK_backup,
+	u32*		backup_dpk_reg
+	)
+{
+	u32 i;
+	for (i = 0; i < DPK_BACKUP_REG_NUM_8821C; i++)
+		odm_write_4byte(p_dm_odm, backup_dpk_reg[i], DPK_backup[i]);
+}
+
+*/
+void
+_dpk_dpk_setting_8821c(
+	struct PHY_DM_STRUCT	*p_dm_odm,
+	u8 path
+)
+{
+	ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_TRACE,
+		     ("[DPK]==========Start the DPD setting Initilaize/n"));
+	/*AFE setting*/
+	odm_write_4byte(p_dm_odm, 0xc60, 0x50000000);
+	odm_write_4byte(p_dm_odm, 0xc60, 0x700F0040);
+	odm_write_4byte(p_dm_odm, 0xc5c, 0xd1000120);
+	odm_write_4byte(p_dm_odm, 0xc58, 0xd8000402);
+	odm_write_4byte(p_dm_odm, 0xc6c, 0x00000a15);
+	odm_write_4byte(p_dm_odm, 0xc00, 0x00000000);
+	/*_iqk_bb_reset_8821c(p_dm_odm);*/
+	odm_write_4byte(p_dm_odm, 0xe5c, 0xD1000120);
+	odm_write_4byte(p_dm_odm, 0xc6c, 0x00000A15);
+	odm_write_4byte(p_dm_odm, 0xe6c, 0x00000A15);
+	odm_write_4byte(p_dm_odm, 0x808, 0x2D028200);
+	odm_write_4byte(p_dm_odm, 0x810, 0x20101063);
+	odm_write_4byte(p_dm_odm, 0x90c, 0x0B00C000);
+	odm_write_4byte(p_dm_odm, 0x9a4, 0x00000080);
+	odm_write_4byte(p_dm_odm, 0xc94, 0x01000101);
+	odm_write_4byte(p_dm_odm, 0xe94, 0x01000101);
+	odm_write_4byte(p_dm_odm, 0xe5c, 0xD1000120);
+	odm_write_4byte(p_dm_odm, 0xc6c, 0x00000A15);
+	odm_write_4byte(p_dm_odm, 0xe6c, 0x00000A15);
+
+
+	odm_write_4byte(p_dm_odm, 0x808, 0x2D028200);
+	odm_write_4byte(p_dm_odm, 0x810, 0x20101063);
+	odm_write_4byte(p_dm_odm, 0x90c, 0x0B00C000);
+	odm_write_4byte(p_dm_odm, 0x9a4, 0x00000080);
+	odm_write_4byte(p_dm_odm, 0xc94, 0x01000101);
+	odm_write_4byte(p_dm_odm, 0xe94, 0x01000101);
+	odm_write_4byte(p_dm_odm, 0x1904, 0x00020000);
+	/*path A*/
+	odm_set_bb_reg(p_dm_odm, 0x1d00, MASKDWORD, 0x30303030); /* cck */
+	odm_set_bb_reg(p_dm_odm, 0x1d04, MASKDWORD, 0x30303030); /* ofdm 6M/9M/12M/18M */
+	odm_set_bb_reg(p_dm_odm, 0x1d08, MASKDWORD, 0x30303030); /* ofdm 24M/36M/48M/54M */
+	odm_set_bb_reg(p_dm_odm, 0x1d0c, MASKDWORD, 0x30303030); /* mcs0~3 */
+	odm_set_bb_reg(p_dm_odm, 0x1d10, MASKDWORD, 0x30303030); /* mcs4~7 */
+	odm_set_bb_reg(p_dm_odm, 0x1d2c, MASKDWORD, 0x30303030); /* vht_1ss_mcs0~3 */
+	odm_set_bb_reg(p_dm_odm, 0x1d30, MASKDWORD, 0x30303030); /* vht_1ss_mcs4~7 */
+	odm_set_bb_reg(p_dm_odm, 0x1d34, 0x0000FFFF, 0x3030);     /* vht_1ss_mcs8/9 */
+
+	/*RF*/
+	odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0xEF, RFREGOFFSETMASK, 0x80000);
+	odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x33, RFREGOFFSETMASK, 0x00024);
+	odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x3E, RFREGOFFSETMASK, 0x0003F);
+	odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x3F, RFREGOFFSETMASK, 0xCBFCE);
+	odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0xEF, RFREGOFFSETMASK, 0x00000);
+	/*AGC boundary selection*/
+	odm_write_4byte(p_dm_odm, 0x1bbc, 0x0001abf6);
+	odm_write_4byte(p_dm_odm, 0x1b90, 0x0001e018);
+	odm_write_4byte(p_dm_odm, 0x1bb8, 0x000fffff);
+	odm_write_4byte(p_dm_odm, 0x1bc8, 0x000c55aa);
+	/*odm_write_4byte(p_dm_odm, 0x1bcc, 0x11978200);*/
+	odm_write_4byte(p_dm_odm, 0x1bcc, 0x11978800);
+	odm_write_4byte(p_dm_odm, 0xcb0, 0x77775747);
+	odm_write_4byte(p_dm_odm, 0xcb4, 0x100000f7);
+	odm_write_4byte(p_dm_odm, 0xcbc, 0x0);
+}
+
+void
+_dpk_dynamic_bias_8821c(
+	struct PHY_DM_STRUCT	*p_dm_odm,
+	u8 path,
+	u8 dynamicbias
+)
+{
+	u32 tmp;
+	tmp = odm_get_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0xdf, RFREGOFFSETMASK);
+	tmp = tmp | BIT(8);
+	odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0xdf, RFREGOFFSETMASK, tmp);
+	if ((*p_dm_odm->p_band_type == ODM_BAND_5G) && (*p_dm_odm->p_band_width == 1))
+		odm_set_rf_reg(p_dm_odm, path, 0x61, BIT(7) | BIT(6) | BIT(5) | BIT(4), dynamicbias);
+	if ((*p_dm_odm->p_band_type == ODM_BAND_5G) && (*p_dm_odm->p_band_width == 2))
+		odm_set_rf_reg(p_dm_odm, path, 0x61, BIT(7) | BIT(6) | BIT(5) | BIT(4), dynamicbias);
+	tmp = tmp & (~BIT(8));
+	odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0xdf, RFREGOFFSETMASK, tmp);
+	ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_TRACE,
+		("[DPK]Set DynamicBias 0xdf=0x%x, 0x61=0x%x\n", odm_get_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0xdf, RFREGOFFSETMASK), odm_get_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x61, RFREGOFFSETMASK)));
+
+}
+
+
+void
+_dpk_dpk_boundary_selection_8821c(
+	struct PHY_DM_STRUCT	*p_dm_odm,
+	u8 path
+)
+{
+	u8 tmp_pad, compared_pad, reg_tmp, compared_txbb;
+	u8 tmp_txbb = 0;
+	u32 rf_backup_reg00;
+	u8 i = 0;
+	u8 j = 1;
+	u32 boundaryselect = 0;
+	struct _IQK_INFORMATION	*p_iqk_info = &p_dm_odm->IQK_info;
+
+	ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_TRACE,
+		     ("[DPK]Start the DPD boundary selection\n"));
+	rf_backup_reg00 = odm_get_rf_reg(p_dm_odm, (enum odm_rf_radio_path_e)path, 0x00, RFREGOFFSETMASK);
+	tmp_pad = 0;
+	compared_pad = 0;
+	boundaryselect = 0;
+#if dpk_forcein_sram4
+	for (i = 0x1f; i > 0x0; i--) { /*i=tx index*/
+		odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x00, RFREGOFFSETMASK, 0x20000 + i);
+
+		if (p_iqk_info->is_BTG) {
+			compared_pad = (u8)((0x1c000 & odm_get_rf_reg(p_dm_odm, (enum odm_rf_radio_path_e)path, 0x78, RFREGOFFSETMASK)) >> 14);
+			compared_txbb = (u8)((0x07C00 & odm_get_rf_reg(p_dm_odm, (enum odm_rf_radio_path_e)path, 0x5c, RFREGOFFSETMASK)) >> 10);
+		} else {
+			compared_pad = (u8)((0xe0 & odm_get_rf_reg(p_dm_odm, (enum odm_rf_radio_path_e)path, 0x56, RFREGOFFSETMASK)) >> 5);
+			compared_txbb = (u8)((0x1f & odm_get_rf_reg(p_dm_odm, (enum odm_rf_radio_path_e)path, 0x56, RFREGOFFSETMASK)));
+		}
+		if (i == 0x1f) {
+			/*boundaryselect = compared_txbb;*/
+			boundaryselect = 0x1f;
+			tmp_pad = compared_pad;
+		}
+		if (compared_pad < tmp_pad) {
+			boundaryselect = boundaryselect + (i << (j * 5));
+			tmp_pad = compared_pad ;
+			j++;
+		}
+
+		if (j >= 4)
+			break;
+	}
+
+#else
+	boundaryselect = 0x0;
+#endif
+	odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x00, RFREGOFFSETMASK, rf_backup_reg00);
+	odm_write_4byte(p_dm_odm, 0x1bbc, boundaryselect);
+
+}
+
+u8
+_dpk_get_dpk_tx_agc_8821c(
+	struct PHY_DM_STRUCT	*p_dm_odm,
+	u8 path
+)
+{
+
+	u8 tx_agc_init_value = 0x1f; /* DPK TXAGC value*/
+	u32 rf_reg00 = 0x0;
+	u8 gainloss = 0x1;
+	u8 best_tx_agc ;
+	u8 tmp;
+	u8 i = 0;
+	boolean notready = true;
+	u8 delay_count = 0x0;
+	u32 temp2;
+	/* rf_reg00 = 0x40000 + tx_agc_init_value;  set TXAGC value */
+	if (*p_dm_odm->p_band_type == ODM_BAND_5G) {
+		tx_agc_init_value = 0x1d;
+		rf_reg00 = 0x40000 + tx_agc_init_value; /* set TXAGC value*/
+		odm_write_4byte(p_dm_odm, 0x1bc8, 0x000c55aa);
+		odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x8F, RFREGOFFSETMASK, 0xA9C00);
+	} else {
+		tx_agc_init_value = 0x17;
+		rf_reg00 = 0x44000 + tx_agc_init_value; /* set TXAGC value*/
+		odm_write_4byte(p_dm_odm, 0x1bc8, 0x000c44aa);
+		odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x8F, RFREGOFFSETMASK, 0xAEC00);
+	}
+	odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x00, RFREGOFFSETMASK, rf_reg00);
+	odm_set_bb_reg(p_dm_odm, 0x1b8c, BIT(15) | BIT(14) | BIT(13), gainloss);
+	odm_set_bb_reg(p_dm_odm, 0x1bc8, BIT(31), 0x1);
+	odm_set_bb_reg(p_dm_odm, 0x8f8, BIT(25) | BIT(24) | BIT(23) | BIT(22), 0x5);
+	odm_write_4byte(p_dm_odm, 0x1b00, 0xf8000d18);
+	/*ODM_delay_ms(1);*/
+	odm_write_4byte(p_dm_odm, 0x1b00, 0xf8000d19);
+	ODM_delay_ms(2);
+
+#if 0
+	ODM_delay_ms(100);
+#else
+	while (notready) {
+		if (odm_read_4byte(p_dm_odm, 0xfa0) & BIT(27))/*if (odm_read_4byte(p_dm_odm, 0x1b00) == (IQK_CMD & 0xffffff0f))*/
+			notready = false;
+		else
+			notready = true;
+
+		if (notready) {
+			ODM_delay_ms(1);
+			delay_count++;
+		}
+
+		if (delay_count >= 50) {
+			ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD,
+				("[DPK]S%d DPK_GetDPKTXAGC_8821C timeout!!!\n", path));
+			break;
+		}
+	}
+
+	odm_write_4byte(p_dm_odm, 0x1b90, 0x0001e018);
+#endif
+
+	ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_TRACE,
+		("rf_reg00 =0x%x, 0x8F =0x%x\n",	 odm_get_rf_reg(p_dm_odm, path, 0x00, RFREGOFFSETMASK), odm_get_rf_reg(p_dm_odm, path, 0x8f, RFREGOFFSETMASK)));
+
+
+	odm_write_4byte(p_dm_odm, 0x1bd4, 0x60001);
+	tmp = (u8)odm_read_4byte(p_dm_odm, 0x1bfc);
+	best_tx_agc = tx_agc_init_value - (0xa - tmp);
+	ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_TRACE,
+		("[DPK](2), 0x1b8c =0x%x, delay_count=%d, rf_reg00 = 0x%x, 0x1b00 = 0x%x, 0x1bfc = 0x%x, 0x1bd4 = 0x%x,best_tx_agc =0x%x, tmp =0x%x, delay =%d ms\n",
+		odm_read_4byte(p_dm_odm, 0x1b8c), delay_count, rf_reg00, odm_read_4byte(p_dm_odm, 0x1b00), odm_read_4byte(p_dm_odm, 0x1bfc), odm_read_4byte(p_dm_odm, 0x1bd4), best_tx_agc, tmp, i * 2));
+	/* dbg message*/
+#if 0
+
+	ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_TRACE,
+		("[DQK] 3  0x1bcc = 0x%x, 0x1bb8 =0x%x\n", odm_read_4byte(p_dm_odm, 0x1bcc), odm_read_4byte(p_dm_odm, 0x1bb8)));
+
+	odm_write_4byte(p_dm_odm, 0x1bcc, 0x118f8800);
+	for (i = 0 ; i < 8; i++) {
+		odm_write_4byte(p_dm_odm, 0x1b90, 0x0101e018 + i);
+		odm_write_4byte(p_dm_odm, 0x1bd4, 0x00060000);
+		ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_TRACE,
+			     ("0x%x\n",
+			      odm_read_4byte(p_dm_odm, 0x1bfc)));
+		odm_write_4byte(p_dm_odm, 0x1bd4, 0x00070000);
+		ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_TRACE,
+			     ("0x%x\n",
+			      odm_read_4byte(p_dm_odm, 0x1bfc)));
+		odm_write_4byte(p_dm_odm, 0x1bd4, 0x00080000);
+		ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_TRACE,
+			     ("0x%x\n",
+			      odm_read_4byte(p_dm_odm, 0x1bfc)));
+		odm_write_4byte(p_dm_odm, 0x1bd4, 0x00090000);
+		ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_TRACE,
+			     ("0x%x\n",
+			      odm_read_4byte(p_dm_odm, 0x1bfc)));
+
+	}
+
+	odm_write_4byte(p_dm_odm, 0x1b90, 0x0001e018);
+
+#endif
+	return best_tx_agc;
+
+}
+
+boolean
+_dpk_enable_dpk_8821c(
+	struct PHY_DM_STRUCT	*p_dm_odm,
+	u8 path,
+	u8 best_tx_agc
+)
+{
+	u32 rf_reg00 = 0x0;
+	u32 tmp;
+	boolean fail = true;
+	u8 i = 0;
+	boolean notready = true;
+	u8 delay_count = 0x0;
+
+	if (*p_dm_odm->p_band_type == ODM_BAND_5G)	   {
+		rf_reg00 = 0x40000 + best_tx_agc; /* set TXAGC value*/
+	} else {
+		rf_reg00 = 0x44000 + best_tx_agc; /* set TXAGC value*/
+	}
+	odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x00, RFREGOFFSETMASK, rf_reg00);
+	ODM_delay_ms(1);
+	odm_set_bb_reg(p_dm_odm, 0x1bc8, BIT(31), 0x1);
+	odm_write_4byte(p_dm_odm, 0x8f8, 0x41400080);
+	ODM_delay_ms(1);
+	odm_write_4byte(p_dm_odm, 0x1b00, 0xf8000e18);
+	odm_write_4byte(p_dm_odm, 0x1b00, 0xf8000e19);
+#if 0
+	ODM_delay_ms(10);
+#else
+
+	ODM_delay_ms(5);
+	while (notready) {
+		if (odm_read_4byte(p_dm_odm, 0xfa0) & BIT(27))/*if (odm_read_4byte(p_dm_odm, 0x1b00) == (IQK_CMD & 0xffffff0f))*/
+			notready = false;
+		else
+			notready = true;
+
+		if (notready) {
+			ODM_delay_ms(1);
+			delay_count++;
+		}
+
+		if (delay_count >= 50) {
+			ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD,
+				("[DPK]S%d DPK_GetDPKTXAGC_8821C timeout!!!\n", path));
+			break;
+		}
+	}
+
+
+#endif
+	odm_write_4byte(p_dm_odm, 0x1b90, 0x0001e018);
+	odm_write_4byte(p_dm_odm, 0x1bd4, 0xA0001);
+	tmp = odm_read_4byte(p_dm_odm, 0x1bfc);
+
+	if ((odm_read_4byte(p_dm_odm, 0x1b08) & 0x0f000000) == 0x0)
+		fail = false;
+	else
+		fail = true;
+	ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_TRACE,
+		("[DPK] (3), delay_count= %d, 0x1b0b = 0x%x, 0x1bc8 = 0x%x, rf_reg00 = 0x%x, ,0x1bfc = 0x%x, 0x1b90=0x%x, 0x1b94=0x%x\n",
+		delay_count, odm_read_1byte(p_dm_odm, 0x1b0b), odm_read_4byte(p_dm_odm, 0x1bc8), rf_reg00, tmp, odm_read_4byte(p_dm_odm, 0x1b90), odm_read_4byte(p_dm_odm, 0x1b94)));
+	/* dbg message*/
+#if 0
+	odm_write_4byte(p_dm_odm, 0x1b00, 0xf8000008);
+	odm_write_4byte(p_dm_odm, 0x1b08, 0x00000080);
+	odm_write_4byte(p_dm_odm, 0x1bd4, 0x00040001);
+
+	ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD,
+		     ("[DPK] SRAM value!!!\n"));
+
+	for (i = 0 ; i < 64; i++) {
+		/*odm_write_4byte(p_dm_odm, 0x1b90, 0x0101e018+i);*/
+		odm_write_4byte(p_dm_odm, 0x1bdc, 0xc0000081 + i * 2);
+
+		ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_TRACE,
+			     ("0x%x\n", odm_read_4byte(p_dm_odm, 0x1bfc)));
+
+	}
+	odm_write_4byte(p_dm_odm, 0x1bd4, 0x00050001);
+	for (i = 0 ; i < 64; i++) {
+		/*odm_write_4byte(p_dm_odm, 0x1b90, 0x0101e018+i);*/
+		odm_write_4byte(p_dm_odm, 0x1bdc, 0xc0000081 + i * 2);
+
+		ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_TRACE,
+			     ("0x%x\n", odm_read_4byte(p_dm_odm, 0x1bfc)));
+
+	}
+
+	/*odm_write_4byte(p_dm_odm, 0x1b08, 0x00000080);*/
+	odm_write_4byte(p_dm_odm, 0x1bd4, 0x00000001);
+	odm_write_4byte(p_dm_odm, 0x1bdc, 0x00000000);
+#endif
+	return fail;
+
+}
+
+
+boolean
+_dpk_enable_dpd_8821c(
+	struct PHY_DM_STRUCT	*p_dm_odm,
+	u8 path,
+	u8 best_tx_agc
+)
+{
+
+	boolean fail = true;
+	u8 tmp;
+	u8 offset = 0x0;
+	u8 i = 0;
+	boolean notready = true;
+	u8 delay_count = 0x0;
+
+
+	odm_set_bb_reg(p_dm_odm, 0x1bc8, BIT(31), 0x1);
+	odm_write_4byte(p_dm_odm, 0x8f8, 0x41400080);
+	ODM_delay_ms(1);
+	odm_write_4byte(p_dm_odm, 0x1b00, 0xf8000f18);
+	odm_write_4byte(p_dm_odm, 0x1b00, 0xf8000f19);
+	ODM_delay_ms(30);
+#if 0
+	ODM_delay_ms(100);
+#else
+	while (notready) {
+		if (odm_read_4byte(p_dm_odm, 0xfa0) & BIT(27))/*if (odm_read_4byte(p_dm_odm, 0x1b00) == (IQK_CMD & 0xffffff0f))*/
+			notready = false;
+		else
+			notready = true;
+
+		if (notready) {
+			ODM_delay_ms(1);
+			delay_count++;
+		}
+
+		if (delay_count >= 50) {
+			ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD,
+				("[DPK]S%d DPK_GetDPKTXAGC_8821C timeout!!!\n", path));
+			break;
+		}
+	}
+	odm_write_4byte(p_dm_odm, 0x1b90, 0x0001e018);
+#endif
+	odm_write_4byte(p_dm_odm, 0x1b90, 0x0001e018);
+	odm_write_4byte(p_dm_odm, 0x1bd4, 0xA0001);
+	tmp = odm_read_1byte(p_dm_odm, 0x1bfc);
+
+
+	ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_TRACE,
+		("[DPK](4) init 0x1b08 =%x, 0x1bc8 = 0x%x,0x1bfc = 0x%x, ,0x1bd0 = 0x%x, offset =%x, 1bcc =%x\n",
+		odm_read_4byte(p_dm_odm, 0x1b08), odm_read_4byte(p_dm_odm, 0x1bc8), tmp, odm_read_4byte(p_dm_odm, 0x1bd0), offset, odm_read_4byte(p_dm_odm, 0x1bcc)));
+
+	/*if( (odm_read_4byte(p_dm_odm, 0x1b08) & 0x0f000000) == 0x0)*/
+	if (true) {
+		odm_write_4byte(p_dm_odm, 0x1b98, 0x48004800);
+		odm_write_4byte(p_dm_odm, 0x1bdc, 0x0);
+
+		if (best_tx_agc >= 0x19)
+			offset = best_tx_agc - 0x19;
+		else
+			offset = 0x20 - (0x19 - best_tx_agc);
+		odm_set_bb_reg(p_dm_odm, 0x1bd0, BIT(12) | BIT(11) | BIT(10) | BIT(9) | BIT(8), offset);
+
+		fail = false;
+
+		ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_TRACE,
+			("[DPK](4) OK 0x1b08 =%x, 0x1bc8 = 0x%x,0x1bfc = 0x%x, ,0x1bd0 = 0x%x, offset =%x, 1bcc =%x\n",
+			odm_read_4byte(p_dm_odm, 0x1b08), odm_read_4byte(p_dm_odm, 0x1bc8), tmp, odm_read_4byte(p_dm_odm, 0x1bd0), offset, odm_read_4byte(p_dm_odm, 0x1bcc)));
+	} else
+		fail = true;
+
+
+
+
+	return fail;
+
+}
+void
+phy_dpd_calibrate_8821c(
+	struct PHY_DM_STRUCT		*p_dm_odm,
+	boolean			reset
+)
+{
+
+	u32  backup_dpdbb[3];
+	u32	backup_dpdbb_reg[3] = {0x1b2c, 0x1b38, 0xc1b3c};
+	u8	best_tx_agc = 0x1c;
+	u32	MAC_backup[MAC_REG_NUM_8821C], RF_backup[RF_REG_NUM_8821C][1];
+	u32	backup_mac_reg[MAC_REG_NUM_8821C] = {0x520, 0x550, 0x1518};
+	u32  BB_backup[DPK_BB_REG_NUM_8821C];
+	u32	backup_bb_reg[DPK_BB_REG_NUM_8821C] = {0x808, 0x90c, 0xc00, 0xcb0, 0xcb4, 0xcbc, 0x1990, 0x9a4, 0xa04
+		, 0xc58, 0xc5c, 0xe58, 0xe5c, 0xc6c, 0xe6c, 0x810, 0x90c, 0xc94, 0xe94, 0x1904, 0xcb0, 0xcb4, 0xcbc, 0xc00
+						  };
+	u32	backup_rf_reg[RF_REG_NUM_8821C] = {0xdf,  0xde, 0x8f, 0x65, 0x0, 0x1};
+	u8  i;
+	u32	backup_dpk_reg[3] = {0x1bd0, 0x1b98, 0x1bbc};
+
+
+	struct _IQK_INFORMATION   *p_iqk_info = &p_dm_odm->IQK_info;
+	p_iqk_info->is_BTG = (boolean) odm_get_bb_reg(p_dm_odm, 0xcb8, BIT(16));
+	if (!p_dm_odm->mp_mode)
+		if (_iqk_reload_iqk_8821c(p_dm_odm, reset))
+			return;
+	/*2G is not stable*/
+	/* if (!(*p_dm_odm->p_band_type == ODM_BAND_5G)) return; */
+
+	ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_TRACE,
+		     ("[DPK]==========DPK strat!!!!!==========\n"));
+	ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD,
+		("[DPK]p_band_type = %s, band_width = %d, ExtPA2G = %d, ext_pa_5g = %d\n", (*p_dm_odm->p_band_type == ODM_BAND_5G) ? "5G" : "2G", *p_dm_odm->p_band_width, p_dm_odm->ext_pa, p_dm_odm->ext_pa_5g));
+#if 1
+	_iqk_backup_mac_bb_8821c(p_dm_odm, MAC_backup, BB_backup, backup_mac_reg, backup_bb_reg, DPK_BB_REG_NUM_8821C);
+	_iqk_afe_setting_8821c(p_dm_odm, true);
+	_iqk_backup_rf_8821c(p_dm_odm, RF_backup, backup_rf_reg);
+
+#else
+	_iqk_rfe_setting_8821c(p_dm_odm, false);
+	_iqk_agc_bnd_int_8821c(p_dm_odm);
+	_iqk_rf_setting_8821c(p_dm_odm);
+
+#endif
+
+
+	if (p_iqk_info->is_BTG) {
+	} else {
+		if (*p_dm_odm->p_band_type == ODM_BAND_2_4G)
+			odm_set_bb_reg(p_dm_odm, 0xcb8, BIT(8), 0x1);
+		else
+			odm_set_bb_reg(p_dm_odm, 0xcb8, BIT(8), 0x0);
+	}
+
+
+	/*backup 0x1b2c, 1b38,0x1b3c*/
+	{
+		backup_dpdbb[0] = odm_read_4byte(p_dm_odm, 0x1b2c);
+	}
+	{
+		backup_dpdbb[1] = odm_read_4byte(p_dm_odm, 0x1b38);
+	}
+	{
+		backup_dpdbb[2] = odm_read_4byte(p_dm_odm, 0x1b3c);
+	}
+	ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_TRACE,
+		     ("[DPK]In DPD Proces(1), Backup\n"));
+#if 1
+
+	/*PDK Init Register setting*/
+	_dpk_dpk_setting_8821c(p_dm_odm, ODM_RF_PATH_A);
+	_dpk_dpk_boundary_selection_8821c(p_dm_odm, ODM_RF_PATH_A);
+	odm_set_bb_reg(p_dm_odm, 0x1bc8, BIT(31), 0x1);
+	odm_set_bb_reg(p_dm_odm, 0x8f8, BIT(25) | BIT(24) | BIT(23) | BIT(22), 0x5);
+	/* Get the best TXAGC*/
+#endif
+
+#if 1
+	best_tx_agc = _dpk_get_dpk_tx_agc_8821c(p_dm_odm, ODM_RF_PATH_A);
+#endif
+	ODM_delay_ms(2);
+	ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_TRACE,
+		("[DPK]In DPD Process(2), Best TXAGC = 0x%x\n", best_tx_agc));
+
+#if 1
+	if (_dpk_enable_dpk_8821c(p_dm_odm, ODM_RF_PATH_A, best_tx_agc)) {
+		ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_TRACE,
+			     ("[DPK]In DPD Process(3), DPK process is Fail\n"));
+	}
+#endif
+#if 1
+	ODM_delay_ms(2);
+	if (_dpk_enable_dpd_8821c(p_dm_odm, ODM_RF_PATH_A, best_tx_agc)) {
+		ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_TRACE,
+			     ("[DPK]In DPD Process(4), DPD process is Fail\n"));
+	}
+#endif
+	/* restore IQK */
+	p_iqk_info->rf_reg18 = odm_get_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x18, RFREGOFFSETMASK);
+	ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[DPK]reload IQK result before, p_iqk_info->rf_reg18=0x%x, p_iqk_info->iqk_channel[0]=0x%x, p_iqk_info->iqk_channel[1]=0x%x!!!!\n", p_iqk_info->rf_reg18, p_iqk_info->iqk_channel[0], p_iqk_info->iqk_channel[1]));
+	_iqk_reload_iqk_setting_8821c(p_dm_odm, 0, 2);
+	_iqk_fill_iqk_report_8821c(p_dm_odm, 0);
+	/* Restore setup */
+	odm_set_bb_reg(p_dm_odm, 0x8f8, BIT(25) | BIT(24) | BIT(23) | BIT(22), 0x5);
+	odm_set_bb_reg(p_dm_odm, 0x1bd4, BIT(20) | BIT(19) | BIT(18) | BIT(17) | BIT(16), 0x0);
+	odm_set_bb_reg(p_dm_odm, 0x1b00, BIT(2) | BIT(1), 0x0);
+	odm_set_bb_reg(p_dm_odm, 0x1b08, BIT(6) | BIT(5), 0x2);
+
+	odm_write_4byte(p_dm_odm, 0x1b2c, backup_dpdbb[0]);
+	odm_write_4byte(p_dm_odm, 0x1b38, backup_dpdbb[1]);
+	odm_write_4byte(p_dm_odm, 0x1b3c, backup_dpdbb[2]);
+	/*enable DPK*/
+	odm_set_bb_reg(p_dm_odm, 0x1b2c, BIT(7) | BIT(6) | BIT(5) | BIT(4) | BIT(3) | BIT(2) | BIT(1) | BIT(0), 0x5);
+	/*enable boundary condition*/
+#if dpk_forcein_sram4 /* disable : froce in sram4*/
+	odm_set_bb_reg(p_dm_odm, 0x1bcc, BIT(27), 0x1);
+#endif
+	odm_write_4byte(p_dm_odm, 0x1bcc, 0x11868800);
+	ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_TRACE,
+		     ("[DPK]In DPD Process(5), Restore\n"));
+#if 1
+	_iqk_restore_mac_bb_8821c(p_dm_odm, MAC_backup, BB_backup, backup_mac_reg, backup_bb_reg, DPK_BB_REG_NUM_8821C);
+	_iqk_afe_setting_8821c(p_dm_odm, false);
+	_iqk_restore_rf_8821c(p_dm_odm, backup_rf_reg, RF_backup);
+#else
+	_iqk_restore_rf_8821c(p_dm_odm, backup_rf_reg, RF_backup);
+#endif
+	/* backup the DPK current result*/
+	for (i = 0; i < DPK_BACKUP_REG_NUM_8821C; i++)
+		dpk_result[i] = odm_read_4byte(p_dm_odm, backup_dpk_reg[i]);
+
+	ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_TRACE,
+		("[DPK]the DPD calibration Process Finish (6), dpk_result = 0x%x\n", dpk_result[0]));
+	return;
+}
+
+void
+_phy_iq_calibrate_8821c(
+	struct PHY_DM_STRUCT		*p_dm_odm,
+	boolean			reset
+)
+{
+
+	u32	MAC_backup[MAC_REG_NUM_8821C], BB_backup[BB_REG_NUM_8821C], RF_backup[RF_REG_NUM_8821C][1];
+	u32	backup_mac_reg[MAC_REG_NUM_8821C] = {0x520, 0x550, 0x1518};
+	u32	backup_bb_reg[BB_REG_NUM_8821C] = {0x808, 0x90c, 0xc00, 0xcb0, 0xcb4, 0xcbc, 0x1990, 0x9a4, 0xa04, 0xb00};
+	u32	backup_rf_reg[RF_REG_NUM_8821C] = {0xdf,  0xde, 0x8f, 0x65, 0x0, 0x1};
+	u8	i, j;
+	boolean segment_iqk = false, is_mp = false;
+
+	struct _IQK_INFORMATION	*p_iqk_info = &p_dm_odm->IQK_info;
+
+	if (p_dm_odm->mp_mode)
+		is_mp = true;
+	else if (p_dm_odm->is_linked)
+		segment_iqk = false;
+
+	p_iqk_info->is_BTG = (boolean)odm_get_bb_reg(p_dm_odm, 0xcb8, BIT(16));
+
+	if (!is_mp)
+		if (_iqk_reload_iqk_8821c(p_dm_odm, reset))
+			return;
+
+	ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_TRACE,
+		     ("[IQK]==========IQK strat!!!!!==========\n"));
+
+	ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD,
+		("[IQK]p_band_type = %s, band_width = %d, ExtPA2G = %d, ext_pa_5g = %d\n", (*p_dm_odm->p_band_type == ODM_BAND_5G) ? "5G" : "2G", *p_dm_odm->p_band_width, p_dm_odm->ext_pa, p_dm_odm->ext_pa_5g));
+	ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD,
+		("[IQK]Interface = %d, cut_version = %x\n", p_dm_odm->support_interface, p_dm_odm->cut_version));
+
+	p_iqk_info->tmp_GNTWL = _iqk_indirect_read_reg(p_dm_odm, 0x38);
+
+	p_iqk_info->iqk_times++;
+	p_iqk_info->kcount = 0;
+	p_dm_odm->rf_calibrate_info.iqk_total_progressing_time = 0;
+	p_dm_odm->rf_calibrate_info.iqk_step = 1;
+	p_iqk_info->rxiqk_step = 1;
+
+	_iqk_backup_iqk_8821c(p_dm_odm, 0);
+	_iqk_backup_mac_bb_8821c(p_dm_odm, MAC_backup, BB_backup, backup_mac_reg, backup_bb_reg,BB_REG_NUM_8821C);
+	_iqk_backup_rf_8821c(p_dm_odm, RF_backup, backup_rf_reg);
+#if 0
+	_iqk_configure_macbb_8821c(p_dm_odm);
+	_iqk_afe_setting_8821c(p_dm_odm, true);
+	_iqk_rfe_setting_8821c(p_dm_odm, false);
+	_iqk_agc_bnd_int_8821c(p_dm_odm);
+	_IQK_RFSetting_8821C(p_dm_odm);
+#endif
+
+	while (1) {
+		if (!is_mp)
+			p_dm_odm->rf_calibrate_info.iqk_start_time = odm_get_current_time(p_dm_odm);
+
+		_iqk_configure_macbb_8821c(p_dm_odm);
+		_iqk_afe_setting_8821c(p_dm_odm, true);
+		_iqk_rfe_setting_8821c(p_dm_odm, false);
+		_iqk_agc_bnd_int_8821c(p_dm_odm);
+		_iqk_rfsetting_8821c(p_dm_odm);
+
+		_iqk_start_iqk_8821c(p_dm_odm, segment_iqk);
+
+		_iqk_afe_setting_8821c(p_dm_odm, false);
+		_iqk_restore_mac_bb_8821c(p_dm_odm, MAC_backup, BB_backup, backup_mac_reg, backup_bb_reg,BB_REG_NUM_8821C);
+		_iqk_restore_rf_8821c(p_dm_odm, backup_rf_reg, RF_backup);
+
+		if (!is_mp) {
+			p_dm_odm->rf_calibrate_info.iqk_progressing_time = odm_get_progressing_time(p_dm_odm, p_dm_odm->rf_calibrate_info.iqk_start_time);
+			p_dm_odm->rf_calibrate_info.iqk_total_progressing_time += odm_get_progressing_time(p_dm_odm, p_dm_odm->rf_calibrate_info.iqk_start_time);
+			ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD,
+				("[IQK]IQK progressing_time = %lld ms\n", p_dm_odm->rf_calibrate_info.iqk_progressing_time));
+		}
+
+		if (p_dm_odm->rf_calibrate_info.iqk_step == 4)
+			break;
+
+		p_iqk_info->kcount = 0;
+		ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]delay 50ms!!!\n"));
+		ODM_delay_ms(50);
+	};
+
+	_iqk_backup_iqk_8821c(p_dm_odm, 1);
+#if 0
+	_iqk_afe_setting_8821c(p_dm_odm, false);
+	_iqk_restore_mac_bb_8821c(p_dm_odm, MAC_backup, BB_backup, backup_mac_reg, backup_bb_reg);
+	_iqk_restore_rf_8821c(p_dm_odm, backup_rf_reg, RF_backup);
+#endif
+	_iqk_fill_iqk_report_8821c(p_dm_odm, 0);
+
+	if (!is_mp)
+		ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]Total IQK progressing_time = %lld ms\n",
+			p_dm_odm->rf_calibrate_info.iqk_total_progressing_time));
+
+	ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_TRACE,
+		     ("[IQK]==========IQK end!!!!!==========\n"));
+
+	RT_TRACE(COMP_COEX, DBG_LOUD, ("[IQK]check 0x49c = %x\n", odm_read_1byte(p_dm_odm, 0x49c)));
+}
+
+
+void
+_phy_iq_calibrate_by_fw_8821c(
+	struct PHY_DM_STRUCT	*p_dm_odm,
+	u8		clear
+)
+{
+
+	u8			iqk_cmd[3] = { *p_dm_odm->p_channel, 0x0, 0x0};
+	u8			buf1 = 0x0;
+	u8			buf2 = 0x0;
+}
+
+
+/*IQK version:0xe, NCTL:0x7*/
+/*1. disable segment IQK*/
+void
+phy_iq_calibrate_8821c(
+	void		*p_dm_void,
+	boolean		clear
+)
+{
+	struct PHY_DM_STRUCT	*p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
+	u32		counter = 0x0;
+
+#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
+	struct _ADAPTER		*p_adapter = p_dm_odm->adapter;
+	HAL_DATA_TYPE	*p_hal_data = GET_HAL_DATA(p_adapter);
+
+#if (MP_DRIVER == 1)
+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
+		PMPT_CONTEXT	p_mpt_ctx = &(p_adapter->MptCtx);
+#else
+	PMPT_CONTEXT	p_mpt_ctx = &(p_adapter->mppriv.mpt_ctx);
+#endif
+#endif
+#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN))
+	if (odm_check_power_status(p_adapter) == false)
+		return;
+#endif
+
+#if MP_DRIVER == 1
+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
+	if (p_mpt_ctx->bSingleTone || p_mpt_ctx->bCarrierSuppression)
+	return;
+#else
+	if (p_mpt_ctx->is_single_tone || p_mpt_ctx->is_carrier_suppression)
+		return;
+#endif
+#endif
+#endif
+
+	if (!p_dm_odm->mp_mode)
+		_iqk_check_coex_status(p_dm_odm, true);
+
+	if (*(p_dm_odm->p_is_scan_in_process)) {
+		ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]scan is in process, bypass IQK\n"));
+		return;
+	}
+
+	p_dm_odm->iqk_fw_offload = 0;
+
+	/*FW IQK*/
+	if (p_dm_odm->iqk_fw_offload) {
+		if (!p_dm_odm->rf_calibrate_info.is_iqk_in_progress) {
+			odm_acquire_spin_lock(p_dm_odm, RT_IQK_SPINLOCK);
+			p_dm_odm->rf_calibrate_info.is_iqk_in_progress = true;
+			odm_release_spin_lock(p_dm_odm, RT_IQK_SPINLOCK);
+
+			p_dm_odm->rf_calibrate_info.iqk_start_time = odm_get_current_time(p_dm_odm);
+
+			odm_write_4byte(p_dm_odm, 0x1b00, 0xf8000008);
+			odm_set_bb_reg(p_dm_odm, 0x1bf0, 0xff000000, 0xff);
+			ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_TRACE,
+				("[IQK]0x1bf0 = 0x%x\n", odm_read_4byte(p_dm_odm, 0x1bf0)));
+
+			_phy_iq_calibrate_by_fw_8821c(p_dm_odm, clear);
+
+			while (1) {
+				if (((odm_read_4byte(p_dm_odm, 0x1bf0) >> 24) == 0x7f) || (counter > 300))
+					break;
+
+				counter++;
+				ODM_delay_ms(1);
+			};
+
+			ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_TRACE, ("[IQK]counter = %d\n", counter));
+
+			p_dm_odm->rf_calibrate_info.iqk_progressing_time = odm_get_progressing_time(p_dm_odm, p_dm_odm->rf_calibrate_info.iqk_start_time);
+
+			ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]IQK progressing_time = %lld ms\n", p_dm_odm->rf_calibrate_info.iqk_progressing_time));
+
+			odm_acquire_spin_lock(p_dm_odm, RT_IQK_SPINLOCK);
+			p_dm_odm->rf_calibrate_info.is_iqk_in_progress = false;
+			odm_release_spin_lock(p_dm_odm, RT_IQK_SPINLOCK);
+		}	else
+			ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("== Return the IQK CMD, because the IQK in Progress ==\n"));
+	} else {
+
+		_iq_calibrate_8821c_init(p_dm_void);
+
+		if (!p_dm_odm->rf_calibrate_info.is_iqk_in_progress) {
+			odm_acquire_spin_lock(p_dm_odm, RT_IQK_SPINLOCK);
+			p_dm_odm->rf_calibrate_info.is_iqk_in_progress = true;
+			odm_release_spin_lock(p_dm_odm, RT_IQK_SPINLOCK);
+			if (p_dm_odm->mp_mode)
+				p_dm_odm->rf_calibrate_info.iqk_start_time = odm_get_current_time(p_dm_odm);
+
+#if (DM_ODM_SUPPORT_TYPE & (ODM_CE))
+			_phy_iq_calibrate_8821c(p_dm_odm, clear);
+			/*DBG_871X("%s,%d, do IQK %u ms\n", __func__, __LINE__, rtw_get_passing_time_ms(time_iqk));*/
+#else
+			_phy_iq_calibrate_8821c(p_dm_odm, clear);
+#endif
+			if (p_dm_odm->mp_mode) {
+				p_dm_odm->rf_calibrate_info.iqk_progressing_time = odm_get_progressing_time(p_dm_odm, p_dm_odm->rf_calibrate_info.iqk_start_time);
+				ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]IQK progressing_time = %lld ms\n", p_dm_odm->rf_calibrate_info.iqk_progressing_time));
+			}
+			odm_acquire_spin_lock(p_dm_odm, RT_IQK_SPINLOCK);
+			p_dm_odm->rf_calibrate_info.is_iqk_in_progress = false;
+			odm_release_spin_lock(p_dm_odm, RT_IQK_SPINLOCK);
+		} else
+			ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]== Return the IQK CMD, because the IQK in Progress ==\n"));
+	}
+
+#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
+	_iqk_iqk_fail_report_8821c(p_dm_odm);
+#endif
+
+	if (!p_dm_odm->mp_mode)
+		_iqk_check_coex_status(p_dm_odm, false);
+	RT_TRACE(COMP_COEX, DBG_LOUD, ("[IQK]final 0x49c = %x\n", odm_read_1byte(p_dm_odm, 0x49c)));
+}
+
+void
+phy_dp_calibrate_8821c(
+	void		*p_dm_void,
+	boolean		clear
+)
+{
+	struct PHY_DM_STRUCT	*p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
+	u32		counter = 0x0;
+
+
+#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
+	struct _ADAPTER		*p_adapter = p_dm_odm->adapter;
+	HAL_DATA_TYPE	*p_hal_data = GET_HAL_DATA(p_adapter);
+
+#if (MP_DRIVER == 1)
+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
+	PMPT_CONTEXT	p_mpt_ctx = &(p_adapter->MptCtx);
+#else
+	PMPT_CONTEXT	p_mpt_ctx = &(p_adapter->mppriv.mpt_ctx);
+#endif
+#endif
+#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN))
+	if (odm_check_power_status(p_adapter) == false)
+		return;
+#endif
+
+#if MP_DRIVER == 1
+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
+	if (p_mpt_ctx->bSingleTone || p_mpt_ctx->bCarrierSuppression)
+		return;
+#else
+	if (p_mpt_ctx->is_single_tone || p_mpt_ctx->is_carrier_suppression)
+		return;
+#endif
+#endif
+
+#endif
+
+
+	ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[DPK] In PHY, p_dm_odm->dpk_en == %x\n", p_dm_odm->dpk_en));
+
+	/*if dpk is not enable*/
+	if (p_dm_odm->dpk_en == 0x0)
+		return;
+
+	/*start*/
+	if (!p_dm_odm->rf_calibrate_info.is_iqk_in_progress) {
+		odm_acquire_spin_lock(p_dm_odm, RT_IQK_SPINLOCK);
+		p_dm_odm->rf_calibrate_info.is_iqk_in_progress = true;
+		odm_release_spin_lock(p_dm_odm, RT_IQK_SPINLOCK);
+		if (p_dm_odm->mp_mode)
+			p_dm_odm->rf_calibrate_info.iqk_start_time = odm_get_current_time(p_dm_odm);
+
+		/*do DPK*/
+		phy_dpd_calibrate_8821c(p_dm_odm, clear);
+
+
+		if (p_dm_odm->mp_mode) {
+			p_dm_odm->rf_calibrate_info.iqk_progressing_time = odm_get_progressing_time(p_dm_odm, p_dm_odm->rf_calibrate_info.iqk_start_time);
+			ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[DPK]DPK progressing_time = %lld ms\n", p_dm_odm->rf_calibrate_info.iqk_progressing_time));
+		}
+		odm_acquire_spin_lock(p_dm_odm, RT_IQK_SPINLOCK);
+		p_dm_odm->rf_calibrate_info.is_iqk_in_progress = false;
+		odm_release_spin_lock(p_dm_odm, RT_IQK_SPINLOCK);
+	} else
+		ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[DPK]== Return the DPK CMD, because the DPK in Progress ==\n"));
+
+
+
+
+}
+void dpk_temperature_compensate_8821c(
+	void		*p_dm_void
+)
+{
+
+	struct PHY_DM_STRUCT		*p_dm_odm	=	(struct PHY_DM_STRUCT *) p_dm_void;
+	struct _ADAPTER		*adapter = p_dm_odm->adapter;
+	HAL_DATA_TYPE	*p_hal_data = GET_HAL_DATA(adapter);
+	static u8	dpk_tm_trigger = 0;
+	u8			thermal_value = 0, delta_dpk, p = 0, i = 0;
+	u8			thermal_value_avg_count = 0;
+	u8          thermal_value_avg_times = 2;
+	u32	        thermal_value_avg = 0;
+	u8          tmp, abs_temperature;
+
+	/*if dpk is not enable*/
+	if (p_dm_odm->dpk_en == 0x0)
+		return;
+
+
+	if (!dpk_tm_trigger) {
+		odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x42, BIT(17) | BIT(16), 0x03);
+		/*ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[DPK] (1) Trigger Thermal Meter!!\n"));*/
+		dpk_tm_trigger = 1;
+		return;
+	} else {
+
+		/* Initialize */
+		dpk_tm_trigger = 0;
+		/*ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[DPK] (2) calculate the thermal !!\n"));
+		*/
+
+		/* calculate average thermal meter */
+		thermal_value = (u8)odm_get_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x42, 0xfc00);	/*0x42: RF Reg[15:10] 88E*/
+		ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD,
+			("[DPK] (3) current Thermal Meter = %d\n", thermal_value));
+
+		p_dm_odm->rf_calibrate_info.thermal_value_dpk = thermal_value;
+		p_dm_odm->rf_calibrate_info.thermal_value_avg[p_dm_odm->rf_calibrate_info.thermal_value_avg_index] = thermal_value;
+		p_dm_odm->rf_calibrate_info.thermal_value_avg_index++;
+		if (p_dm_odm->rf_calibrate_info.thermal_value_avg_index == thermal_value_avg_times)
+			p_dm_odm->rf_calibrate_info.thermal_value_avg_index = 0;
+		for (i = 0; i < thermal_value_avg_times; i++) {
+			if (p_dm_odm->rf_calibrate_info.thermal_value_avg[i]) {
+				thermal_value_avg += p_dm_odm->rf_calibrate_info.thermal_value_avg[i];
+				thermal_value_avg_count++;
+			}
+		}
+		if (thermal_value_avg_count)  /*Calculate Average thermal_value after average enough times*/
+			thermal_value = (u8)(thermal_value_avg / thermal_value_avg_count);
+		/* compensate the DPK */
+		delta_dpk = (thermal_value > p_hal_data->eeprom_thermal_meter) ? (thermal_value - p_hal_data->eeprom_thermal_meter) : (p_hal_data->eeprom_thermal_meter - thermal_value);
+		tmp = (u8)((dpk_result[0] & 0x00001f00) >> 8);
+		ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD,
+			("[DPK] (5)delta_dpk = %d, eeprom_thermal_meter = %d, tmp=%d\n", delta_dpk, p_hal_data->eeprom_thermal_meter, tmp));
+
+
+		if (thermal_value > p_hal_data->eeprom_thermal_meter) {
+			abs_temperature = thermal_value - p_hal_data->eeprom_thermal_meter;
+			if (abs_temperature >= 20)
+				tmp = tmp + 4;
+			else if (abs_temperature >= 15)
+				tmp = tmp + 3;
+			else if (abs_temperature >= 10)
+				tmp = tmp + 2;
+			else if (abs_temperature >= 5)
+				tmp = tmp + 1;
+		} else { /*low temperature*/
+			abs_temperature = p_hal_data->eeprom_thermal_meter - thermal_value;
+			if (abs_temperature >= 20)
+				tmp = tmp - 4;
+			else if (abs_temperature >= 15)
+				tmp = tmp - 3;
+			else if (abs_temperature >= 10)
+				tmp = tmp - 2;
+			else if (abs_temperature >= 5)
+				tmp = tmp - 1;
+		}
+
+		odm_set_bb_reg(p_dm_odm, 0x1bd0, BIT(12) | BIT(11) | BIT(10) | BIT(9) | BIT(8), tmp);
+		ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD,
+			("[DPK] (6)delta_dpk = %d, eeprom_thermal_meter = %d, new tmp=%d, 0x1bd0=0x%x\n", delta_dpk, p_hal_data->eeprom_thermal_meter, tmp, odm_read_4byte(p_dm_odm, 0x1bd0)));
+
+	}
+}
+
+#endif
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/rtl8821c/phydm_iqk_8821c.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/rtl8821c/phydm_iqk_8821c.h
--- linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/rtl8821c/phydm_iqk_8821c.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/rtl8821c/phydm_iqk_8821c.h	2020-04-10 16:35:06.835660954 +0300
@@ -0,0 +1,63 @@
+#ifndef	__PHYDM_IQK_8821C_H__
+#define    __PHYDM_IQK_8821C_H__
+
+#if (RTL8821C_SUPPORT == 1)
+
+
+/*--------------------------Define Parameters-------------------------------*/
+#define		MAC_REG_NUM_8821C 3
+#define		BB_REG_NUM_8821C 10
+#define		RF_REG_NUM_8821C 6
+#define     DPK_BB_REG_NUM_8821C 24
+#define     DPK_BACKUP_REG_NUM_8821C 3
+
+
+#define	LOK_delay_8821C 2
+#define	GS_delay_8821C 2
+#define	WBIQK_delay_8821C 2
+
+#define TXIQK 0
+#define RXIQK 1
+#define	SS_8821C 1
+
+/*---------------------------End Define Parameters-------------------------------*/
+
+
+#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
+void
+do_iqk_8821c(
+	void	*p_dm_void,
+	u8		delta_thermal_index,
+	u8		thermal_value,
+	u8		threshold
+);
+#else
+void
+do_iqk_8821c(
+	void		*p_dm_void,
+	u8		delta_thermal_index,
+	u8		thermal_value,
+	u8		threshold
+);
+#endif
+
+void
+phy_iq_calibrate_8821c(
+	void		*p_dm_void,
+	boolean		clear
+);
+VOID
+phy_dp_calibrate_8821c(
+	void		*p_dm_void,
+	boolean		clear
+
+	);
+
+#else	/* (RTL8821C_SUPPORT == 0)*/
+
+#define phy_iq_calibrate_8821c(_pdm_void, clear)
+#define phy_dp_calibrate_8821c(_pDM_VOID, clear)
+
+#endif	/* RTL8821C_SUPPORT */
+
+#endif	/* #ifndef __PHYDM_IQK_8821C_H__*/
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/rtl8821c/phydm_regconfig8821c.c linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/rtl8821c/phydm_regconfig8821c.c
--- linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/rtl8821c/phydm_regconfig8821c.c	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/rtl8821c/phydm_regconfig8821c.c	2020-04-10 16:35:06.835660954 +0300
@@ -0,0 +1,248 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2016 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+
+#include "mp_precomp.h"
+#include "../phydm_precomp.h"
+
+#if (RTL8821C_SUPPORT == 1)
+
+void odm_config_rf_reg_8821c(struct dm_struct *dm, u32 addr, u32 data,
+			     enum rf_path rf_path, u32 reg_addr)
+{
+	if (dm->fw_offload_ability & PHYDM_PHY_PARAM_OFFLOAD) {
+		if (addr == 0xffe) {
+			phydm_set_reg_by_fw(dm,
+					    PHYDM_HALMAC_CMD_DELAY_MS,
+					    reg_addr,
+					    data,
+					    RFREGOFFSETMASK,
+					    rf_path,
+					    50);
+		} else if (addr == 0xfe) {
+			phydm_set_reg_by_fw(dm,
+					    PHYDM_HALMAC_CMD_DELAY_US,
+					    reg_addr,
+					    data,
+					    RFREGOFFSETMASK,
+					    rf_path,
+					    100);
+		} else {
+			phydm_set_reg_by_fw(dm,
+					    PHYDM_HALMAC_CMD_RF_W,
+					    reg_addr,
+					    data,
+					    RFREGOFFSETMASK,
+					    rf_path,
+					    0);
+			phydm_set_reg_by_fw(dm,
+					    PHYDM_HALMAC_CMD_DELAY_US,
+					    reg_addr,
+					    data,
+					    RFREGOFFSETMASK,
+					    rf_path,
+					    1);
+		}
+	} else {
+		if (addr == 0xffe) {
+#ifdef CONFIG_LONG_DELAY_ISSUE
+			ODM_sleep_ms(50);
+#else
+			ODM_delay_ms(50);
+#endif
+		} else if (addr == 0xfe) {
+#ifdef CONFIG_LONG_DELAY_ISSUE
+			ODM_sleep_us(100);
+#else
+			ODM_delay_us(100);
+#endif
+		} else {
+			odm_set_rf_reg(dm, rf_path, reg_addr, RFREGOFFSETMASK, data);
+
+			/* Add 1us delay between BB/RF register setting. */
+			ODM_delay_us(1);
+		}
+	}
+}
+
+void odm_config_rf_radio_a_8821c(struct dm_struct *dm, u32 addr, u32 data)
+{
+	u32 content = 0x1000; /* RF_Content: radioa_txt */
+	u32 maskfor_phy_set = (u32)(content & 0xE000);
+
+	odm_config_rf_reg_8821c(dm, addr, data, RF_PATH_A, addr | maskfor_phy_set);
+
+	PHYDM_DBG(dm, ODM_COMP_INIT,
+		  "===> odm_config_rf_with_header_file: [RadioA] %08X %08X\n",
+		  addr, data);
+}
+
+void odm_config_mac_8821c(struct dm_struct *dm, u32 addr, u8 data)
+{
+	if (dm->fw_offload_ability & PHYDM_PHY_PARAM_OFFLOAD)
+		phydm_set_reg_by_fw(dm,
+				    PHYDM_HALMAC_CMD_MAC_W8,
+				    addr,
+				    data,
+				    0,
+				    (enum rf_path)0,
+				    0);
+	else
+		odm_write_1byte(dm, addr, data);
+	PHYDM_DBG(dm, ODM_COMP_INIT, "===> config_mac: [MAC_REG] %08X %08X\n",
+		  addr, data);
+}
+
+void odm_update_agc_big_jump_lmt_8821c(struct dm_struct *dm, u32 addr, u32 data)
+{
+	struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
+	u8 rf_gain_idx = (u8)((data & 0xFF000000) >> 24);
+	u8 bb_gain_idx = (u8)((data & 0x00ff0000) >> 16);
+	u8 agc_table_idx = (u8)((data & 0x00000f00) >> 8);
+	static boolean is_limit;
+
+	if (addr != 0x81c)
+		return;
+
+	/*dbg_print("data = 0x%x, rf_gain_idx = 0x%x, bb_gain_idx = 0x%x, agc_table_idx = 0x%x\n", data, rf_gain_idx, bb_gain_idx, agc_table_idx);*/
+	/*dbg_print("rf_gain_idx = 0x%x, dig_t->rf_gain_idx = 0x%x\n", rf_gain_idx, dig_t->rf_gain_idx);*/
+
+	if (bb_gain_idx > 0x3c) {
+		if (rf_gain_idx == dig_t->rf_gain_idx && is_limit == false) {
+			is_limit = true;
+			dig_t->big_jump_lmt[agc_table_idx] = bb_gain_idx - 2;
+			PHYDM_DBG(dm, DBG_DIG,
+				  "===> [AGC_TAB] big_jump_lmt [%d] = 0x%x\n",
+				  agc_table_idx,
+				  dig_t->big_jump_lmt[agc_table_idx]);
+		}
+	} else {
+		is_limit = false;
+	}
+
+	dig_t->rf_gain_idx = rf_gain_idx;
+}
+
+void odm_config_bb_agc_8821c(struct dm_struct *dm, u32 addr, u32 bitmask,
+			     u32 data)
+{
+	odm_update_agc_big_jump_lmt_8821c(dm, addr, data);
+
+	if (dm->fw_offload_ability & PHYDM_PHY_PARAM_OFFLOAD)
+		phydm_set_reg_by_fw(dm,
+				    PHYDM_HALMAC_CMD_BB_W32,
+				    addr,
+				    data,
+				    bitmask,
+				    (enum rf_path)0,
+				    0);
+	else
+		odm_set_bb_reg(dm, addr, bitmask, data);
+
+	PHYDM_DBG(dm, ODM_COMP_INIT, "===> config_bb: [AGC_TAB] %08X %08X\n",
+		  addr, data);
+}
+
+void odm_config_bb_phy_reg_pg_8821c(struct dm_struct *dm, u32 band, u32 rf_path,
+				    u32 tx_num, u32 addr, u32 bitmask, u32 data)
+{
+#if (DM_ODM_SUPPORT_TYPE & ODM_CE)
+	phy_store_tx_power_by_rate(dm->adapter, band, rf_path, tx_num, addr, bitmask, data);
+#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)
+	PHY_StoreTxPowerByRate(dm->adapter, band, rf_path, tx_num, addr, bitmask, data);
+#endif
+
+	PHYDM_DBG(dm, ODM_COMP_INIT,
+		  "===> odm_config_bb_with_header_file: [PHY_REG] %08X %08X %08X\n",
+		  addr, bitmask, data);
+}
+
+void odm_config_bb_phy_8821c(struct dm_struct *dm, u32 addr, u32 bitmask,
+			     u32 data)
+{
+	if (dm->fw_offload_ability & PHYDM_PHY_PARAM_OFFLOAD) {
+		u32 delay_time = 0;
+
+		if (addr >= 0xf9 && addr <= 0xfe) {
+			if (addr == 0xfe || addr == 0xfb)
+				delay_time = 50;
+			else if (addr == 0xfd || addr == 0xfa)
+				delay_time = 5;
+			else
+				delay_time = 1;
+
+			if (addr >= 0xfc && addr <= 0xfe)
+				phydm_set_reg_by_fw(dm,
+						    PHYDM_HALMAC_CMD_DELAY_MS,
+						    addr,
+						    data,
+						    bitmask,
+						    (enum rf_path)0,
+						    delay_time);
+			else
+				phydm_set_reg_by_fw(dm,
+						    PHYDM_HALMAC_CMD_DELAY_US,
+						    addr,
+						    data,
+						    bitmask,
+						    (enum rf_path)0,
+						    delay_time);
+		} else {
+			phydm_set_reg_by_fw(dm,
+					    PHYDM_HALMAC_CMD_BB_W32,
+					    addr,
+					    data,
+					    bitmask,
+					    (enum rf_path)0,
+					    0);
+		}
+	} else {
+		if (addr == 0xfe)
+#ifdef CONFIG_LONG_DELAY_ISSUE
+			ODM_sleep_ms(50);
+#else
+			ODM_delay_ms(50);
+#endif
+		else if (addr == 0xfd)
+			ODM_delay_ms(5);
+		else if (addr == 0xfc)
+			ODM_delay_ms(1);
+		else if (addr == 0xfb)
+			ODM_delay_us(50);
+		else if (addr == 0xfa)
+			ODM_delay_us(5);
+		else if (addr == 0xf9)
+			ODM_delay_us(1);
+		else
+			odm_set_bb_reg(dm, addr, bitmask, data);
+	}
+
+	PHYDM_DBG(dm, ODM_COMP_INIT, "===> config_bb: [PHY_REG] %08X %08X\n",
+		  addr, data);
+}
+
+void odm_config_bb_txpwr_lmt_8821c(struct dm_struct *dm, u8 *regulation,
+				   u8 *band, u8 *bandwidth, u8 *rate_section,
+				   u8 *rf_path, u8 *channel, u8 *power_limit)
+{
+#if (DM_ODM_SUPPORT_TYPE & ODM_CE)
+	phy_set_tx_power_limit(dm, regulation, band,
+			       bandwidth, rate_section, rf_path, channel, power_limit);
+#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)
+	PHY_SetTxPowerLimit(dm, regulation, band,
+			    bandwidth, rate_section, rf_path, channel, power_limit);
+#endif
+}
+
+#endif
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/rtl8821c/phydm_regconfig8821c.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/rtl8821c/phydm_regconfig8821c.h
--- linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/rtl8821c/phydm_regconfig8821c.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/rtl8821c/phydm_regconfig8821c.h	2020-04-10 16:35:06.835660954 +0300
@@ -0,0 +1,50 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2016 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#ifndef __INC_ODM_REGCONFIG_H_8821C
+#define __INC_ODM_REGCONFIG_H_8821C
+
+#if (RTL8821C_SUPPORT == 1)
+
+void odm_config_rf_reg_8821c(struct dm_struct *dm, u32 addr, u32 data,
+			     enum rf_path rf_path, u32 reg_addr);
+
+void odm_config_rf_radio_a_8821c(struct dm_struct *dm, u32 addr, u32 data);
+
+void odm_config_rf_radio_b_8821c(
+	struct dm_struct *dm,
+	u32 addr,
+	u32 data);
+
+void odm_config_mac_8821c(struct dm_struct *dm, u32 addr, u8 data);
+
+void odm_update_agc_big_jump_lmt_8821c(struct dm_struct *dm, u32 addr,
+				       u32 data);
+
+void odm_config_bb_agc_8821c(struct dm_struct *dm, u32 addr, u32 bitmask,
+			     u32 data);
+
+void odm_config_bb_phy_reg_pg_8821c(struct dm_struct *dm, u32 band, u32 rf_path,
+				    u32 tx_num, u32 addr, u32 bitmask,
+				    u32 data);
+
+void odm_config_bb_phy_8821c(struct dm_struct *dm, u32 addr, u32 bitmask,
+			     u32 data);
+
+void odm_config_bb_txpwr_lmt_8821c(struct dm_struct *dm, u8 *regulation,
+				   u8 *band, u8 *bandwidth, u8 *rate_section,
+				   u8 *rf_path, u8 *channel, u8 *power_limit);
+
+#endif
+#endif /* RTL8822B_SUPPORT == 1*/
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/rtl8821c/version_rtl8821c.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/rtl8821c/version_rtl8821c.h
--- linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/rtl8821c/version_rtl8821c.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/rtl8821c/version_rtl8821c.h	2020-04-10 16:35:06.835660954 +0300
@@ -0,0 +1,33 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017  Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * The full GNU General Public License is included in this distribution in the
+ * file called LICENSE.
+ *
+ * Contact Information:
+ * wlanfae <wlanfae@realtek.com>
+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
+ * Hsinchu 300, Taiwan.
+ *
+ * Larry Finger <Larry.Finger@lwfinger.net>
+ *
+ *****************************************************************************/
+/*RTL8821C PHY Parameters*/
+/*
+ * [Caution]
+ * Since 01/Aug/2015, the commit rules will be simplified. You do not need to fill up the version.h anymore,
+ * only the maintenance supervisor fills it before formal release.
+ */
+#define	RELEASE_DATE_8821C		20180209
+#define	COMMIT_BY_8821C			"Coiln"
+#define	RELEASE_VERSION_8821C	49
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/sd4_phydm_2_kernel.mk linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/sd4_phydm_2_kernel.mk
--- linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/sd4_phydm_2_kernel.mk	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/sd4_phydm_2_kernel.mk	2020-04-10 16:35:06.835660954 +0300
@@ -0,0 +1,188 @@
+EXTRA_CFLAGS += -I$(topDIR)/hal/phydm
+
+_PHYDM_FILES := hal/phydm/phydm_debug.o	\
+								hal/phydm/phydm_interface.o\
+								hal/phydm/phydm_phystatus.o\
+								hal/phydm/phydm_hwconfig.o\
+								hal/phydm/phydm.o\
+								hal/phydm/phydm_dig.o\
+								hal/phydm/phydm_rainfo.o\
+								hal/phydm/phydm_adaptivity.o\
+								hal/phydm/phydm_cfotracking.o\
+								hal/phydm/phydm_noisemonitor.o\
+								hal/phydm/phydm_beamforming.o\
+								hal/phydm/phydm_dfs.o\
+								hal/phydm/txbf/halcomtxbf.o\
+								hal/phydm/txbf/haltxbfinterface.o\
+								hal/phydm/txbf/phydm_hal_txbf_api.o\
+								hal/phydm/phydm_ccx.o\
+								hal/phydm/phydm_cck_pd.o\
+								hal/phydm/phydm_rssi_monitor.o\
+								hal/phydm/phydm_math_lib.o\
+								hal/phydm/phydm_api.o\
+								hal/phydm/halrf/halrf.o\
+								hal/phydm/halrf/halrf_debug.o\
+								hal/phydm/halrf/halphyrf_ce.o\
+								hal/phydm/halrf/halrf_powertracking_ce.o\
+								hal/phydm/halrf/halrf_powertracking.o\
+								hal/phydm/halrf/halrf_kfree.o
+
+ifeq ($(CONFIG_RTL8188E), y)
+RTL871X = rtl8188e
+_PHYDM_FILES += hal/phydm/$(RTL871X)/halhwimg8188e_mac.o\
+								hal/phydm/$(RTL871X)/halhwimg8188e_bb.o\
+								hal/phydm/$(RTL871X)/halhwimg8188e_rf.o\
+								hal/phydm/halrf/$(RTL871X)/halrf_8188e_ce.o\
+								hal/phydm/$(RTL871X)/phydm_regconfig8188e.o\
+								hal/phydm/$(RTL871X)/hal8188erateadaptive.o\
+								hal/phydm/$(RTL871X)/phydm_rtl8188e.o
+endif
+
+ifeq ($(CONFIG_RTL8192E), y)
+RTL871X = rtl8192e
+_PHYDM_FILES += hal/phydm/$(RTL871X)/halhwimg8192e_mac.o\
+								hal/phydm/$(RTL871X)/halhwimg8192e_bb.o\
+								hal/phydm/$(RTL871X)/halhwimg8192e_rf.o\
+								hal/phydm/halrf/$(RTL871X)/halrf_8192e_ce.o\
+								hal/phydm/$(RTL871X)/phydm_regconfig8192e.o\
+								hal/phydm/$(RTL871X)/phydm_rtl8192e.o
+endif
+
+
+ifeq ($(CONFIG_RTL8812A), y)
+RTL871X = rtl8812a
+_PHYDM_FILES += hal/phydm/$(RTL871X)/halhwimg8812a_mac.o\
+								hal/phydm/$(RTL871X)/halhwimg8812a_bb.o\
+								hal/phydm/$(RTL871X)/halhwimg8812a_rf.o\
+								hal/phydm/halrf/$(RTL871X)/halrf_8812a_ce.o\
+								hal/phydm/$(RTL871X)/phydm_regconfig8812a.o\
+								hal/phydm/$(RTL871X)/phydm_rtl8812a.o\
+								hal/phydm/txbf/haltxbfjaguar.o
+endif
+
+ifeq ($(CONFIG_RTL8821A), y)
+RTL871X = rtl8821a
+_PHYDM_FILES += hal/phydm/rtl8821a/halhwimg8821a_mac.o\
+								hal/phydm/rtl8821a/halhwimg8821a_bb.o\
+								hal/phydm/rtl8821a/halhwimg8821a_rf.o\
+								hal/phydm/halrf/rtl8812a/halrf_8812a_ce.o\
+								hal/phydm/halrf/rtl8821a/halrf_8821a_ce.o\
+								hal/phydm/rtl8821a/phydm_regconfig8821a.o\
+								hal/phydm/rtl8821a/phydm_rtl8821a.o\
+								hal/phydm/halrf/rtl8821a/halrf_iqk_8821a_ce.o\
+								hal/phydm/txbf/haltxbfjaguar.o
+endif
+
+
+ifeq ($(CONFIG_RTL8723B), y)
+RTL871X = rtl8723b
+_PHYDM_FILES += hal/phydm/$(RTL871X)/halhwimg8723b_bb.o\
+								hal/phydm/$(RTL871X)/halhwimg8723b_mac.o\
+								hal/phydm/$(RTL871X)/halhwimg8723b_rf.o\
+								hal/phydm/$(RTL871X)/halhwimg8723b_mp.o\
+								hal/phydm/$(RTL871X)/phydm_regconfig8723b.o\
+								hal/phydm/halrf/$(RTL871X)/halrf_8723b_ce.o\
+								hal/phydm/$(RTL871X)/phydm_rtl8723b.o
+endif
+
+
+ifeq ($(CONFIG_RTL8814A), y)
+RTL871X = rtl8814a
+_PHYDM_FILES += hal/phydm/$(RTL871X)/halhwimg8814a_bb.o\
+								hal/phydm/$(RTL871X)/halhwimg8814a_mac.o\
+								hal/phydm/$(RTL871X)/halhwimg8814a_rf.o\
+								hal/phydm/halrf/$(RTL871X)/halrf_iqk_8814a.o\
+								hal/phydm/$(RTL871X)/phydm_regconfig8814a.o\
+								hal/phydm/halrf/$(RTL871X)/halrf_8814a_ce.o\
+								hal/phydm/$(RTL871X)/phydm_rtl8814a.o\
+								hal/phydm/txbf/haltxbf8814a.o
+endif
+
+
+ifeq ($(CONFIG_RTL8723C), y)
+RTL871X = rtl8703b
+_PHYDM_FILES += hal/phydm/$(RTL871X)/halhwimg8703b_bb.o\
+								hal/phydm/$(RTL871X)/halhwimg8703b_mac.o\
+								hal/phydm/$(RTL871X)/halhwimg8703b_rf.o\
+								hal/phydm/$(RTL871X)/phydm_regconfig8703b.o\
+								hal/phydm/$(RTL871X)/phydm_rtl8703b.o\
+								hal/phydm/halrf/$(RTL871X)/halrf_8703b.o
+endif
+
+ifeq ($(CONFIG_RTL8723D), y)
+RTL871X = rtl8723d
+_PHYDM_FILES += hal/phydm/$(RTL871X)/halhwimg8723d_bb.o\
+								hal/phydm/$(RTL871X)/halhwimg8723d_mac.o\
+								hal/phydm/$(RTL871X)/halhwimg8723d_rf.o\
+								hal/phydm/$(RTL871X)/phydm_regconfig8723d.o\
+								hal/phydm/$(RTL871X)/phydm_rtl8723d.o\
+								hal/phydm/halrf/$(RTL871X)/halrf_8723d.o
+endif
+
+
+ifeq ($(CONFIG_RTL8710B), y)
+RTL871X = rtl8710b
+_PHYDM_FILES += hal/phydm/$(RTL871X)/halhwimg8710b_bb.o\
+								hal/phydm/$(RTL871X)/halhwimg8710b_mac.o\
+								hal/phydm/$(RTL871X)/halhwimg8710b_rf.o\
+								hal/phydm/$(RTL871X)/phydm_regconfig8710b.o\
+								hal/phydm/$(RTL871X)/phydm_rtl8710b.o\
+								hal/phydm/halrf/$(RTL871X)/halrf_8710b.o
+endif
+
+
+ifeq ($(CONFIG_RTL8188F), y)
+RTL871X = rtl8188f
+_PHYDM_FILES += hal/phydm/$(RTL871X)/halhwimg8188f_bb.o\
+								hal/phydm/$(RTL871X)/halhwimg8188f_mac.o\
+								hal/phydm/$(RTL871X)/halhwimg8188f_rf.o\
+								hal/phydm/$(RTL871X)/phydm_regconfig8188f.o\
+								hal/phydm/halrf/$(RTL871X)/halrf_8188f.o \
+								hal/phydm/$(RTL871X)/phydm_rtl8188f.o
+endif
+
+ifeq ($(CONFIG_RTL8822B), y)
+RTL871X = rtl8822b
+_PHYDM_FILES +=	hal/phydm/$(RTL871X)/halhwimg8822b_bb.o \
+								hal/phydm/$(RTL871X)/halhwimg8822b_mac.o \
+								hal/phydm/$(RTL871X)/halhwimg8822b_rf.o \
+								hal/phydm/halrf/$(RTL871X)/halrf_8822b.o \
+								hal/phydm/$(RTL871X)/phydm_hal_api8822b.o \
+								hal/phydm/halrf/$(RTL871X)/halrf_iqk_8822b.o \
+								hal/phydm/halrf/$(RTL871X)/halrf_rfk_init_8822b.o \
+								hal/phydm/$(RTL871X)/phydm_regconfig8822b.o \
+								hal/phydm/$(RTL871X)/phydm_rtl8822b.o
+
+_PHYDM_FILES +=	hal/phydm/txbf/haltxbf8822b.o
+endif
+
+
+ifeq ($(CONFIG_RTL8821C), y)
+RTL871X = rtl8821c
+_PHYDM_FILES +=	hal/phydm/$(RTL871X)/halhwimg8821c_bb.o \
+								hal/phydm/$(RTL871X)/halhwimg8821c_mac.o \
+								hal/phydm/$(RTL871X)/halhwimg8821c_rf.o \
+								hal/phydm/$(RTL871X)/phydm_hal_api8821c.o \
+								hal/phydm/$(RTL871X)/phydm_regconfig8821c.o\
+								hal/phydm/halrf/$(RTL871X)/halrf_8821c.o\
+								hal/phydm/halrf/$(RTL871X)/halrf_iqk_8821c.o
+endif
+ifeq ($(CONFIG_RTL8192F), y)
+RTL871X = rtl8192f
+_PHYDM_FILES += hal/phydm/$(RTL871X)/halhwimg8192f_bb.o\
+								hal/phydm/$(RTL871X)/halhwimg8192f_mac.o\
+								hal/phydm/$(RTL871X)/halhwimg8192f_rf.o\
+								hal/phydm/$(RTL871X)/phydm_hal_api8192f.o\
+								hal/phydm/$(RTL871X)/phydm_regconfig8192f.o\
+								hal/phydm/$(RTL871X)/phydm_rtl8192f.o\
+								hal/phydm/halrf/$(RTL871X)/halrf_8192f.o
+endif
+
+ifeq ($(CONFIG_RTL8198F), y)
+RTL871X = rtl8198f
+_PHYDM_FILES += hal/phydm/$(RTL871X)/halhwimg8198f_bb.o\
+								hal/phydm/$(RTL871X)/halhwimg8198f_mac.o\
+								hal/phydm/$(RTL871X)/halhwimg8198f_rf.o\
+								hal/phydm/$(RTL871X)/phydm_hal_api8198f.o\
+								hal/phydm/$(RTL871X)/phydm_regconfig8198f.o
+endif
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/txbf/halcomtxbf.c linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/txbf/halcomtxbf.c
--- linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/txbf/halcomtxbf.c	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/txbf/halcomtxbf.c	2020-04-10 16:35:06.835660954 +0300
@@ -0,0 +1,514 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2016 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+/*@************************************************************
+ * Description:
+ *
+ * This file is for TXBF mechanism
+ *
+ ************************************************************/
+#include "mp_precomp.h"
+#include "../phydm_precomp.h"
+
+#if (BEAMFORMING_SUPPORT == 1)
+/*@Beamforming halcomtxbf API create by YuChen 2015/05*/
+
+void hal_com_txbf_beamform_init(
+	void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	boolean is_iqgen_setting_ok = false;
+
+	if (dm->support_ic_type & ODM_RTL8814A) {
+		is_iqgen_setting_ok = phydm_beamforming_set_iqgen_8814A(dm);
+		PHYDM_DBG(dm, DBG_TXBF, "[%s] is_iqgen_setting_ok = %d\n",
+			  __func__, is_iqgen_setting_ok);
+	}
+}
+
+/*Only used for MU BFer Entry when get GID management frame (self as MU STA)*/
+void hal_com_txbf_config_gtab(
+	void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+
+	if (dm->support_ic_type & ODM_RTL8822B)
+		hal_txbf_8822b_config_gtab(dm);
+}
+
+void phydm_beamform_set_sounding_enter(
+	void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
+	struct _HAL_TXBF_INFO *p_txbf_info = &dm->beamforming_info.txbf_info;
+
+	if (!odm_is_work_item_scheduled(&p_txbf_info->txbf_enter_work_item))
+		odm_schedule_work_item(&p_txbf_info->txbf_enter_work_item);
+#else
+	hal_com_txbf_enter_work_item_callback(dm);
+#endif
+}
+
+void phydm_beamform_set_sounding_leave(
+	void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
+	struct _HAL_TXBF_INFO *p_txbf_info = &dm->beamforming_info.txbf_info;
+
+	if (!odm_is_work_item_scheduled(&p_txbf_info->txbf_leave_work_item))
+		odm_schedule_work_item(&p_txbf_info->txbf_leave_work_item);
+#else
+	hal_com_txbf_leave_work_item_callback(dm);
+#endif
+}
+
+void phydm_beamform_set_sounding_rate(
+	void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
+	struct _HAL_TXBF_INFO *p_txbf_info = &dm->beamforming_info.txbf_info;
+
+	if (!odm_is_work_item_scheduled(&p_txbf_info->txbf_rate_work_item))
+		odm_schedule_work_item(&p_txbf_info->txbf_rate_work_item);
+#else
+	hal_com_txbf_rate_work_item_callback(dm);
+#endif
+}
+
+void phydm_beamform_set_sounding_status(
+	void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
+	struct _HAL_TXBF_INFO *p_txbf_info = &dm->beamforming_info.txbf_info;
+
+	if (!odm_is_work_item_scheduled(&p_txbf_info->txbf_status_work_item))
+		odm_schedule_work_item(&p_txbf_info->txbf_status_work_item);
+#else
+	hal_com_txbf_status_work_item_callback(dm);
+#endif
+}
+
+void phydm_beamform_set_sounding_fw_ndpa(
+	void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
+	struct _HAL_TXBF_INFO *p_txbf_info = &dm->beamforming_info.txbf_info;
+
+	if (*dm->is_fw_dw_rsvd_page_in_progress)
+		odm_set_timer(dm, &p_txbf_info->txbf_fw_ndpa_timer, 5);
+	else
+		odm_schedule_work_item(&p_txbf_info->txbf_fw_ndpa_work_item);
+#else
+	hal_com_txbf_fw_ndpa_work_item_callback(dm);
+#endif
+}
+
+void phydm_beamform_set_sounding_clk(
+	void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
+	struct _HAL_TXBF_INFO *p_txbf_info = &dm->beamforming_info.txbf_info;
+
+	if (!odm_is_work_item_scheduled(&p_txbf_info->txbf_clk_work_item))
+		odm_schedule_work_item(&p_txbf_info->txbf_clk_work_item);
+#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
+	phydm_run_in_thread_cmd(dm, hal_com_txbf_clk_work_item_callback, dm);
+#else
+	hal_com_txbf_clk_work_item_callback(dm);
+#endif
+}
+
+void phydm_beamform_set_reset_tx_path(
+	void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
+	struct _HAL_TXBF_INFO *p_txbf_info = &dm->beamforming_info.txbf_info;
+	struct _RT_WORK_ITEM *pwi = &p_txbf_info->txbf_reset_tx_path_work_item;
+
+	if (!odm_is_work_item_scheduled(pwi))
+		odm_schedule_work_item(pwi);
+#else
+	hal_com_txbf_reset_tx_path_work_item_callback(dm);
+#endif
+}
+
+void phydm_beamform_set_get_tx_rate(
+	void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
+	struct _HAL_TXBF_INFO *p_txbf_info = &dm->beamforming_info.txbf_info;
+	struct _RT_WORK_ITEM *pwi = &p_txbf_info->txbf_get_tx_rate_work_item;
+
+	if (!odm_is_work_item_scheduled(pwi))
+		odm_schedule_work_item(pwi);
+#else
+	hal_com_txbf_get_tx_rate_work_item_callback(dm);
+#endif
+}
+
+void hal_com_txbf_enter_work_item_callback(
+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
+	void *adapter
+#else
+	void *dm_void
+#endif
+	)
+{
+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
+	PHAL_DATA_TYPE hal_data = GET_HAL_DATA(((PADAPTER)adapter));
+	struct dm_struct *dm = &hal_data->DM_OutSrc;
+#else
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+#endif
+	struct _HAL_TXBF_INFO *p_txbf_info = &dm->beamforming_info.txbf_info;
+	u8 idx = p_txbf_info->txbf_idx;
+
+	PHYDM_DBG(dm, DBG_TXBF, "[%s] Start!\n", __func__);
+
+	if (dm->support_ic_type & (ODM_RTL8812 | ODM_RTL8821))
+		hal_txbf_jaguar_enter(dm, idx);
+	else if (dm->support_ic_type & ODM_RTL8192E)
+		hal_txbf_8192e_enter(dm, idx);
+	else if (dm->support_ic_type & ODM_RTL8814A)
+		hal_txbf_8814a_enter(dm, idx);
+	else if (dm->support_ic_type & ODM_RTL8822B)
+		hal_txbf_8822b_enter(dm, idx);
+}
+
+void hal_com_txbf_leave_work_item_callback(
+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
+	void *adapter
+#else
+	void *dm_void
+#endif
+	)
+{
+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
+	PHAL_DATA_TYPE hal_data = GET_HAL_DATA(((PADAPTER)adapter));
+	struct dm_struct *dm = &hal_data->DM_OutSrc;
+#else
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+#endif
+	struct _HAL_TXBF_INFO *p_txbf_info = &dm->beamforming_info.txbf_info;
+
+	u8 idx = p_txbf_info->txbf_idx;
+
+	PHYDM_DBG(dm, DBG_TXBF, "[%s] Start!\n", __func__);
+
+	if (dm->support_ic_type & (ODM_RTL8812 | ODM_RTL8821))
+		hal_txbf_jaguar_leave(dm, idx);
+	else if (dm->support_ic_type & ODM_RTL8192E)
+		hal_txbf_8192e_leave(dm, idx);
+	else if (dm->support_ic_type & ODM_RTL8814A)
+		hal_txbf_8814a_leave(dm, idx);
+	else if (dm->support_ic_type & ODM_RTL8822B)
+		hal_txbf_8822b_leave(dm, idx);
+}
+
+void hal_com_txbf_fw_ndpa_work_item_callback(
+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
+	void *adapter
+#else
+	void *dm_void
+#endif
+	)
+{
+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
+	PHAL_DATA_TYPE hal_data = GET_HAL_DATA(((PADAPTER)adapter));
+	struct dm_struct *dm = &hal_data->DM_OutSrc;
+#else
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+#endif
+	struct _HAL_TXBF_INFO *p_txbf_info = &dm->beamforming_info.txbf_info;
+	u8 idx = p_txbf_info->ndpa_idx;
+
+	PHYDM_DBG(dm, DBG_TXBF, "[%s] Start!\n", __func__);
+
+	if (dm->support_ic_type & (ODM_RTL8812 | ODM_RTL8821))
+		hal_txbf_jaguar_fw_txbf(dm, idx);
+	else if (dm->support_ic_type & ODM_RTL8192E)
+		hal_txbf_8192e_fw_tx_bf(dm, idx);
+	else if (dm->support_ic_type & ODM_RTL8814A)
+		hal_txbf_8814a_fw_txbf(dm, idx);
+	else if (dm->support_ic_type & ODM_RTL8822B)
+		hal_txbf_8822b_fw_txbf(dm, idx);
+}
+
+void hal_com_txbf_clk_work_item_callback(
+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
+	void *adapter
+#else
+	void *dm_void
+#endif
+	)
+{
+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
+	PHAL_DATA_TYPE hal_data = GET_HAL_DATA(((PADAPTER)adapter));
+	struct dm_struct *dm = &hal_data->DM_OutSrc;
+#else
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+#endif
+
+	PHYDM_DBG(dm, DBG_TXBF, "[%s] Start!\n", __func__);
+
+	if (dm->support_ic_type & ODM_RTL8812)
+		hal_txbf_jaguar_clk_8812a(dm);
+}
+
+void hal_com_txbf_rate_work_item_callback(
+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
+	void *adapter
+#else
+	void *dm_void
+#endif
+	)
+{
+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
+	PHAL_DATA_TYPE hal_data = GET_HAL_DATA(((PADAPTER)adapter));
+	struct dm_struct *dm = &hal_data->DM_OutSrc;
+#else
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+#endif
+	struct _HAL_TXBF_INFO *p_txbf_info = &dm->beamforming_info.txbf_info;
+	u8 BW = p_txbf_info->BW;
+	u8 rate = p_txbf_info->rate;
+
+	PHYDM_DBG(dm, DBG_TXBF, "[%s] Start!\n", __func__);
+
+	if (dm->support_ic_type & ODM_RTL8812)
+		hal_txbf_8812a_set_ndpa_rate(dm, BW, rate);
+	else if (dm->support_ic_type & ODM_RTL8192E)
+		hal_txbf_8192e_set_ndpa_rate(dm, BW, rate);
+	else if (dm->support_ic_type & ODM_RTL8814A)
+		hal_txbf_8814a_set_ndpa_rate(dm, BW, rate);
+}
+
+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
+void hal_com_txbf_fw_ndpa_timer_callback(
+	struct phydm_timer_list *timer)
+{
+	void *adapter = (void *)timer->Adapter;
+	PHAL_DATA_TYPE hal_data = GET_HAL_DATA(((PADAPTER)adapter));
+	struct dm_struct *dm = &hal_data->DM_OutSrc;
+
+	struct _HAL_TXBF_INFO *p_txbf_info = &dm->beamforming_info.txbf_info;
+
+	PHYDM_DBG(dm, DBG_TXBF, "[%s] Start!\n", __func__);
+
+	if (*dm->is_fw_dw_rsvd_page_in_progress)
+		odm_set_timer(dm, &(p_txbf_info->txbf_fw_ndpa_timer), 5);
+	else
+		odm_schedule_work_item(&(p_txbf_info->txbf_fw_ndpa_work_item));
+}
+#endif
+
+void hal_com_txbf_status_work_item_callback(
+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
+	void *adapter
+#else
+	void *dm_void
+#endif
+	)
+{
+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
+	PHAL_DATA_TYPE hal_data = GET_HAL_DATA(((PADAPTER)adapter));
+	struct dm_struct *dm = &hal_data->DM_OutSrc;
+#else
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+#endif
+	struct _HAL_TXBF_INFO *p_txbf_info = &dm->beamforming_info.txbf_info;
+
+	u8 idx = p_txbf_info->txbf_idx;
+
+	PHYDM_DBG(dm, DBG_TXBF, "[%s] Start!\n", __func__);
+
+	if (dm->support_ic_type & (ODM_RTL8812 | ODM_RTL8821))
+		hal_txbf_jaguar_status(dm, idx);
+	else if (dm->support_ic_type & ODM_RTL8192E)
+		hal_txbf_8192e_status(dm, idx);
+	else if (dm->support_ic_type & ODM_RTL8814A)
+		hal_txbf_8814a_status(dm, idx);
+	else if (dm->support_ic_type & ODM_RTL8822B)
+		hal_txbf_8822b_status(dm, idx);
+}
+
+void hal_com_txbf_reset_tx_path_work_item_callback(
+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
+	void *adapter
+#else
+	void *dm_void
+#endif
+	)
+{
+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
+	PHAL_DATA_TYPE hal_data = GET_HAL_DATA(((PADAPTER)adapter));
+	struct dm_struct *dm = &hal_data->DM_OutSrc;
+#else
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+#endif
+	struct _HAL_TXBF_INFO *p_txbf_info = &dm->beamforming_info.txbf_info;
+
+	u8 idx = p_txbf_info->txbf_idx;
+
+	if (dm->support_ic_type & ODM_RTL8814A)
+		hal_txbf_8814a_reset_tx_path(dm, idx);
+}
+
+void hal_com_txbf_get_tx_rate_work_item_callback(
+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
+	void *adapter
+#else
+	void *dm_void
+#endif
+	)
+{
+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
+	PHAL_DATA_TYPE hal_data = GET_HAL_DATA(((PADAPTER)adapter));
+	struct dm_struct *dm = &hal_data->DM_OutSrc;
+#else
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+#endif
+
+	if (dm->support_ic_type & ODM_RTL8814A)
+		hal_txbf_8814a_get_tx_rate(dm);
+}
+
+boolean
+hal_com_txbf_set(
+	void *dm_void,
+	u8 set_type,
+	void *p_in_buf)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	u8 *p_u1_tmp = (u8 *)p_in_buf;
+	struct _HAL_TXBF_INFO *p_txbf_info = &dm->beamforming_info.txbf_info;
+
+	PHYDM_DBG(dm, DBG_TXBF, "[%s] set_type = 0x%X\n", __func__, set_type);
+
+	switch (set_type) {
+	case TXBF_SET_SOUNDING_ENTER:
+		p_txbf_info->txbf_idx = *p_u1_tmp;
+		phydm_beamform_set_sounding_enter(dm);
+		break;
+
+	case TXBF_SET_SOUNDING_LEAVE:
+		p_txbf_info->txbf_idx = *p_u1_tmp;
+		phydm_beamform_set_sounding_leave(dm);
+		break;
+
+	case TXBF_SET_SOUNDING_RATE:
+		p_txbf_info->BW = p_u1_tmp[0];
+		p_txbf_info->rate = p_u1_tmp[1];
+		phydm_beamform_set_sounding_rate(dm);
+		break;
+
+	case TXBF_SET_SOUNDING_STATUS:
+		p_txbf_info->txbf_idx = *p_u1_tmp;
+		phydm_beamform_set_sounding_status(dm);
+		break;
+
+	case TXBF_SET_SOUNDING_FW_NDPA:
+		p_txbf_info->ndpa_idx = *p_u1_tmp;
+		phydm_beamform_set_sounding_fw_ndpa(dm);
+		break;
+
+	case TXBF_SET_SOUNDING_CLK:
+		phydm_beamform_set_sounding_clk(dm);
+		break;
+
+	case TXBF_SET_TX_PATH_RESET:
+		p_txbf_info->txbf_idx = *p_u1_tmp;
+		phydm_beamform_set_reset_tx_path(dm);
+		break;
+
+	case TXBF_SET_GET_TX_RATE:
+		phydm_beamform_set_get_tx_rate(dm);
+		break;
+	}
+
+	return true;
+}
+
+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
+boolean
+hal_com_txbf_get(
+	void *adapter,
+	u8 get_type,
+	void *p_out_buf)
+{
+	PHAL_DATA_TYPE hal_data = GET_HAL_DATA(((PADAPTER)adapter));
+	struct dm_struct *dm = &hal_data->DM_OutSrc;
+	boolean *p_boolean = (boolean *)p_out_buf;
+
+	PHYDM_DBG(dm, DBG_TXBF, "[%s] Start!\n", __func__);
+
+	if (get_type == TXBF_GET_EXPLICIT_BEAMFORMEE) {
+		if (IS_HARDWARE_TYPE_OLDER_THAN_8812A(adapter))
+			*p_boolean = false;
+		else if (/*@IS_HARDWARE_TYPE_8822B(adapter)	||*/
+			 IS_HARDWARE_TYPE_8821B(adapter) ||
+			 IS_HARDWARE_TYPE_8192E(adapter) ||
+			 IS_HARDWARE_TYPE_8192F(adapter) ||
+			 IS_HARDWARE_TYPE_JAGUAR(adapter) ||
+			 IS_HARDWARE_TYPE_JAGUAR_AND_JAGUAR2(adapter))
+			*p_boolean = true;
+		else
+			*p_boolean = false;
+	} else if (get_type == TXBF_GET_EXPLICIT_BEAMFORMER) {
+		if (IS_HARDWARE_TYPE_OLDER_THAN_8812A(adapter))
+			*p_boolean = false;
+		else if (/*@IS_HARDWARE_TYPE_8822B(adapter)	||*/
+			 IS_HARDWARE_TYPE_8821B(adapter) ||
+			 IS_HARDWARE_TYPE_8192E(adapter) ||
+			 IS_HARDWARE_TYPE_8192F(adapter) ||
+			 IS_HARDWARE_TYPE_JAGUAR(adapter) ||
+			 IS_HARDWARE_TYPE_JAGUAR_AND_JAGUAR2(adapter)) {
+			if (hal_data->RF_Type == RF_2T2R ||
+			    hal_data->RF_Type == RF_3T3R)
+				*p_boolean = true;
+			else
+				*p_boolean = false;
+		} else
+			*p_boolean = false;
+	} else if (get_type == TXBF_GET_MU_MIMO_STA) {
+#if ((RTL8822B_SUPPORT == 1) || (RTL8821C_SUPPORT == 1))
+		if (IS_HARDWARE_TYPE_8822B(adapter) ||
+		    IS_HARDWARE_TYPE_8821C(adapter))
+			*p_boolean = true;
+		else
+#endif
+			*p_boolean = false;
+
+	} else if (get_type == TXBF_GET_MU_MIMO_AP) {
+#if (RTL8822B_SUPPORT == 1)
+		if (IS_HARDWARE_TYPE_8822B(adapter))
+			*p_boolean = true;
+		else
+#endif
+			*p_boolean = false;
+	}
+
+	return true;
+}
+#endif
+
+#endif
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/txbf/halcomtxbf.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/txbf/halcomtxbf.h
--- linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/txbf/halcomtxbf.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/txbf/halcomtxbf.h	2020-04-10 16:35:06.835660954 +0300
@@ -0,0 +1,183 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017  Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * The full GNU General Public License is included in this distribution in the
+ * file called LICENSE.
+ *
+ * Contact Information:
+ * wlanfae <wlanfae@realtek.com>
+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
+ * Hsinchu 300, Taiwan.
+ *
+ * Larry Finger <Larry.Finger@lwfinger.net>
+ *
+ *****************************************************************************/
+#ifndef __HAL_COM_TXBF_H__
+#define __HAL_COM_TXBF_H__
+
+#if 0
+typedef	bool
+(*TXBF_GET)(
+	void*			adapter,
+	u8			get_type,
+	void*			p_out_buf
+	);
+
+typedef	bool
+(*TXBF_SET)(
+	void*			adapter,
+	u8			set_type,
+	void*			p_in_buf
+	);
+#endif
+
+enum txbf_set_type {
+	TXBF_SET_SOUNDING_ENTER,
+	TXBF_SET_SOUNDING_LEAVE,
+	TXBF_SET_SOUNDING_RATE,
+	TXBF_SET_SOUNDING_STATUS,
+	TXBF_SET_SOUNDING_FW_NDPA,
+	TXBF_SET_SOUNDING_CLK,
+	TXBF_SET_TX_PATH_RESET,
+	TXBF_SET_GET_TX_RATE
+};
+
+enum txbf_get_type {
+	TXBF_GET_EXPLICIT_BEAMFORMEE,
+	TXBF_GET_EXPLICIT_BEAMFORMER,
+	TXBF_GET_MU_MIMO_STA,
+	TXBF_GET_MU_MIMO_AP
+};
+
+/* @2 HAL TXBF related */
+struct _HAL_TXBF_INFO {
+	u8 txbf_idx;
+	u8 ndpa_idx;
+	u8 BW;
+	u8 rate;
+
+	struct phydm_timer_list txbf_fw_ndpa_timer;
+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
+	RT_WORK_ITEM txbf_enter_work_item;
+	RT_WORK_ITEM txbf_leave_work_item;
+	RT_WORK_ITEM txbf_fw_ndpa_work_item;
+	RT_WORK_ITEM txbf_clk_work_item;
+	RT_WORK_ITEM txbf_status_work_item;
+	RT_WORK_ITEM txbf_rate_work_item;
+	RT_WORK_ITEM txbf_reset_tx_path_work_item;
+	RT_WORK_ITEM txbf_get_tx_rate_work_item;
+#endif
+};
+
+#if (BEAMFORMING_SUPPORT == 1)
+
+void hal_com_txbf_beamform_init(
+	void *dm_void);
+
+void hal_com_txbf_config_gtab(
+	void *dm_void);
+
+void hal_com_txbf_enter_work_item_callback(
+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
+	void *adapter
+#else
+	void *dm_void
+#endif
+	);
+
+void hal_com_txbf_leave_work_item_callback(
+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
+	void *adapter
+#else
+	void *dm_void
+#endif
+	);
+
+void hal_com_txbf_fw_ndpa_work_item_callback(
+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
+	void *adapter
+#else
+	void *dm_void
+#endif
+	);
+
+void hal_com_txbf_clk_work_item_callback(
+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
+	void *adapter
+#else
+	void *dm_void
+#endif
+	);
+
+void hal_com_txbf_reset_tx_path_work_item_callback(
+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
+	void *adapter
+#else
+	void *dm_void
+#endif
+	);
+
+void hal_com_txbf_get_tx_rate_work_item_callback(
+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
+	void *adapter
+#else
+	void *dm_void
+#endif
+	);
+
+void hal_com_txbf_rate_work_item_callback(
+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
+	void *adapter
+#else
+	void *dm_void
+#endif
+	);
+
+void hal_com_txbf_fw_ndpa_timer_callback(
+	struct phydm_timer_list *timer);
+
+void hal_com_txbf_status_work_item_callback(
+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
+	void *adapter
+#else
+	void *dm_void
+#endif
+	);
+
+boolean
+hal_com_txbf_set(
+	void *dm_void,
+	u8 set_type,
+	void *p_in_buf);
+
+boolean
+hal_com_txbf_get(
+	void *adapter,
+	u8 get_type,
+	void *p_out_buf);
+
+#else
+#define hal_com_txbf_beamform_init(dm_void) NULL
+#define hal_com_txbf_config_gtab(dm_void) NULL
+#define hal_com_txbf_enter_work_item_callback(_adapter) NULL
+#define hal_com_txbf_leave_work_item_callback(_adapter) NULL
+#define hal_com_txbf_fw_ndpa_work_item_callback(_adapter) NULL
+#define hal_com_txbf_clk_work_item_callback(_adapter) NULL
+#define hal_com_txbf_rate_work_item_callback(_adapter) NULL
+#define hal_com_txbf_fw_ndpa_timer_callback(_adapter) NULL
+#define hal_com_txbf_status_work_item_callback(_adapter) NULL
+#define hal_com_txbf_get(_adapter, _get_type, _pout_buf)
+
+#endif
+
+#endif /*  @#ifndef __HAL_COM_TXBF_H__ */
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/txbf/haltxbf8192e.c linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/txbf/haltxbf8192e.c
--- linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/txbf/haltxbf8192e.c	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/txbf/haltxbf8192e.c	2020-04-10 16:35:06.835660954 +0300
@@ -0,0 +1,382 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2016 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+/*************************************************************
+ * Description:
+ *
+ * This file is for 8192E TXBF mechanism
+ *
+ ************************************************************/
+#include "mp_precomp.h"
+#include "../phydm_precomp.h"
+
+#if (BEAMFORMING_SUPPORT == 1)
+#if (RTL8192E_SUPPORT == 1)
+
+void hal_txbf_8192e_set_ndpa_rate(
+	void *dm_void,
+	u8 BW,
+	u8 rate)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+
+	odm_write_1byte(dm, REG_NDPA_OPT_CTRL_8192E, (rate << 2 | BW));
+}
+
+void hal_txbf_8192e_rf_mode(
+	void *dm_void,
+	struct _RT_BEAMFORMING_INFO *beam_info)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+
+	PHYDM_DBG(dm, DBG_TXBF, "[%s] Start!\n", __func__);
+
+	if (dm->rf_type == RF_1T1R)
+		return;
+
+	odm_set_rf_reg(dm, RF_PATH_A, RF_WE_LUT, 0x80000, 0x1); /*RF mode table write enable*/
+	odm_set_rf_reg(dm, RF_PATH_B, RF_WE_LUT, 0x80000, 0x1); /*RF mode table write enable*/
+
+	if (beam_info->beamformee_su_cnt > 0) {
+		/*Path_A*/
+		odm_set_rf_reg(dm, RF_PATH_A, RF_0x30, 0xfffff, 0x18000); /*Select RX mode  0x30=0x18000*/
+		odm_set_rf_reg(dm, RF_PATH_A, RF_0x31, 0xfffff, 0x0000f); /*Set Table data*/
+		odm_set_rf_reg(dm, RF_PATH_A, RF_0x32, 0xfffff, 0x77fc2); /*@Enable TXIQGEN in RX mode*/
+		/*Path_B*/
+		odm_set_rf_reg(dm, RF_PATH_B, RF_0x30, 0xfffff, 0x18000); /*Select RX mode*/
+		odm_set_rf_reg(dm, RF_PATH_B, RF_0x31, 0xfffff, 0x0000f); /*Set Table data*/
+		odm_set_rf_reg(dm, RF_PATH_B, RF_0x32, 0xfffff, 0x77fc2); /*@Enable TXIQGEN in RX mode*/
+	} else {
+		/*Path_A*/
+		odm_set_rf_reg(dm, RF_PATH_A, RF_0x30, 0xfffff, 0x18000); /*Select RX mode*/
+		odm_set_rf_reg(dm, RF_PATH_A, RF_0x31, 0xfffff, 0x0000f); /*Set Table data*/
+		odm_set_rf_reg(dm, RF_PATH_A, RF_0x32, 0xfffff, 0x77f82); /*@Disable TXIQGEN in RX mode*/
+		/*Path_B*/
+		odm_set_rf_reg(dm, RF_PATH_B, RF_0x30, 0xfffff, 0x18000); /*Select RX mode*/
+		odm_set_rf_reg(dm, RF_PATH_B, RF_0x31, 0xfffff, 0x0000f); /*Set Table data*/
+		odm_set_rf_reg(dm, RF_PATH_B, RF_0x32, 0xfffff, 0x77f82); /*@Disable TXIQGEN in RX mode*/
+	}
+
+	odm_set_rf_reg(dm, RF_PATH_A, RF_WE_LUT, 0x80000, 0x0); /*RF mode table write disable*/
+	odm_set_rf_reg(dm, RF_PATH_B, RF_WE_LUT, 0x80000, 0x0); /*RF mode table write disable*/
+
+	if (beam_info->beamformee_su_cnt > 0) {
+		odm_set_bb_reg(dm, R_0x90c, MASKDWORD, 0x83321333);
+		odm_set_bb_reg(dm, R_0xa04, MASKBYTE3, 0xc1);
+	} else
+		odm_set_bb_reg(dm, R_0x90c, MASKDWORD, 0x81121313);
+}
+
+void hal_txbf_8192e_fw_txbf_cmd(
+	void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	u8 idx, period0 = 0, period1 = 0;
+	u8 PageNum0 = 0xFF, PageNum1 = 0xFF;
+	u8 u1_tx_bf_parm[3] = {0};
+	struct _RT_BEAMFORMING_INFO *beam_info = &dm->beamforming_info;
+
+	for (idx = 0; idx < BEAMFORMEE_ENTRY_NUM; idx++) {
+		if (beam_info->beamformee_entry[idx].beamform_entry_state == BEAMFORMING_ENTRY_STATE_PROGRESSED) {
+			if (idx == 0) {
+				if (beam_info->beamformee_entry[idx].is_sound)
+					PageNum0 = 0xFE;
+				else
+					PageNum0 = 0xFF; /* stop sounding */
+				period0 = (u8)(beam_info->beamformee_entry[idx].sound_period);
+			} else if (idx == 1) {
+				if (beam_info->beamformee_entry[idx].is_sound)
+					PageNum1 = 0xFE;
+				else
+					PageNum1 = 0xFF; /* stop sounding */
+				period1 = (u8)(beam_info->beamformee_entry[idx].sound_period);
+			}
+		}
+	}
+
+	u1_tx_bf_parm[0] = PageNum0;
+	u1_tx_bf_parm[1] = PageNum1;
+	u1_tx_bf_parm[2] = (period1 << 4) | period0;
+	odm_fill_h2c_cmd(dm, PHYDM_H2C_TXBF, 3, u1_tx_bf_parm);
+
+	PHYDM_DBG(dm, DBG_TXBF,
+		  "[%s] PageNum0 = %d period0 = %d, PageNum1 = %d period1 %d\n",
+		  __func__, PageNum0, period0, PageNum1, period1);
+}
+
+void hal_txbf_8192e_download_ndpa(
+	void *dm_void,
+	u8 idx)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	u8 u1b_tmp = 0, tmp_reg422 = 0, head_page;
+	u8 bcn_valid_reg = 0, count = 0, dl_bcn_count = 0;
+	boolean is_send_beacon = false;
+	u8 tx_page_bndy = LAST_ENTRY_OF_TX_PKT_BUFFER_8812;
+	/*@default reseved 1 page for the IC type which is undefined.*/
+	struct _RT_BEAMFORMING_INFO *beam_info = &dm->beamforming_info;
+	struct _RT_BEAMFORMEE_ENTRY *p_beam_entry = beam_info->beamformee_entry + idx;
+
+	PHYDM_DBG(dm, DBG_TXBF, "[%s] Start!\n", __func__);
+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
+	*dm->is_fw_dw_rsvd_page_in_progress = true;
+#endif
+	if (idx == 0)
+		head_page = 0xFE;
+	else
+		head_page = 0xFE;
+
+	phydm_get_hal_def_var_handler_interface(dm, HAL_DEF_TX_PAGE_BOUNDARY, (u8 *)&tx_page_bndy);
+
+	/*Set REG_CR bit 8. DMA beacon by SW.*/
+	u1b_tmp = odm_read_1byte(dm, REG_CR_8192E + 1);
+	odm_write_1byte(dm, REG_CR_8192E + 1, (u1b_tmp | BIT(0)));
+
+	/*Set FWHW_TXQ_CTRL 0x422[6]=0 to tell Hw the packet is not a real beacon frame.*/
+	tmp_reg422 = odm_read_1byte(dm, REG_FWHW_TXQ_CTRL_8192E + 2);
+	odm_write_1byte(dm, REG_FWHW_TXQ_CTRL_8192E + 2, tmp_reg422 & (~BIT(6)));
+
+	if (tmp_reg422 & BIT(6)) {
+		PHYDM_DBG(dm, DBG_TXBF,
+			  "%s There is an adapter is sending beacon.\n",
+			  __func__);
+		is_send_beacon = true;
+	}
+
+	/*TDECTRL[15:8] 0x209[7:0] = 0xFE/0xFD	NDPA Head for TXDMA*/
+	odm_write_1byte(dm, REG_DWBCN0_CTRL_8192E + 1, head_page);
+
+	do {
+		/*@Clear beacon valid check bit.*/
+		bcn_valid_reg = odm_read_1byte(dm, REG_DWBCN0_CTRL_8192E + 2);
+		odm_write_1byte(dm, REG_DWBCN0_CTRL_8192E + 2, (bcn_valid_reg | BIT(0)));
+
+		/* @download NDPA rsvd page. */
+		beamforming_send_ht_ndpa_packet(dm, p_beam_entry->mac_addr, p_beam_entry->sound_bw, BEACON_QUEUE);
+
+#if (DEV_BUS_TYPE == RT_PCI_INTERFACE)
+		u1b_tmp = odm_read_1byte(dm, REG_MGQ_TXBD_NUM_8192E + 3);
+		count = 0;
+		while ((count < 20) && (u1b_tmp & BIT(4))) {
+			count++;
+			ODM_delay_us(10);
+			u1b_tmp = odm_read_1byte(dm, REG_MGQ_TXBD_NUM_8192E + 3);
+		}
+		odm_write_1byte(dm, REG_MGQ_TXBD_NUM_8192E + 3, u1b_tmp | BIT(4));
+#endif
+
+		/*@check rsvd page download OK.*/
+		bcn_valid_reg = odm_read_1byte(dm, REG_DWBCN0_CTRL_8192E + 2);
+		count = 0;
+		while (!(bcn_valid_reg & BIT(0)) && count < 20) {
+			count++;
+			ODM_delay_us(10);
+			bcn_valid_reg = odm_read_1byte(dm, REG_DWBCN0_CTRL_8192E + 2);
+		}
+		dl_bcn_count++;
+	} while (!(bcn_valid_reg & BIT(0)) && dl_bcn_count < 5);
+
+	if (!(bcn_valid_reg & BIT(0)))
+		PHYDM_DBG(dm, DBG_TXBF, "%s Download RSVD page failed!\n",
+			  __func__);
+
+	/*TDECTRL[15:8] 0x209[7:0] = 0xF9	Beacon Head for TXDMA*/
+	odm_write_1byte(dm, REG_DWBCN0_CTRL_8192E + 1, tx_page_bndy);
+
+	/*To make sure that if there exists an adapter which would like to send beacon.*/
+	/*@If exists, the origianl value of 0x422[6] will be 1, we should check this to*/
+	/*prevent from setting 0x422[6] to 0 after download reserved page, or it will cause*/
+	/*the beacon cannot be sent by HW.*/
+	/*@2010.06.23. Added by tynli.*/
+	if (is_send_beacon)
+		odm_write_1byte(dm, REG_FWHW_TXQ_CTRL_8192E + 2, tmp_reg422);
+
+	/*@Do not enable HW DMA BCN or it will cause Pcie interface hang by timing issue. 2011.11.24. by tynli.*/
+	/*@Clear CR[8] or beacon packet will not be send to TxBuf anymore.*/
+	u1b_tmp = odm_read_1byte(dm, REG_CR_8192E + 1);
+	odm_write_1byte(dm, REG_CR_8192E + 1, (u1b_tmp & (~BIT(0))));
+
+	p_beam_entry->beamform_entry_state = BEAMFORMING_ENTRY_STATE_PROGRESSED;
+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
+	*dm->is_fw_dw_rsvd_page_in_progress = false;
+#endif
+}
+
+void hal_txbf_8192e_enter(
+	void *dm_void,
+	u8 bfer_bfee_idx)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	u8 i = 0;
+	u8 bfer_idx = (bfer_bfee_idx & 0xF0) >> 4;
+	u8 bfee_idx = (bfer_bfee_idx & 0xF);
+	u32 csi_param;
+	struct _RT_BEAMFORMING_INFO *beamforming_info = &dm->beamforming_info;
+	struct _RT_BEAMFORMEE_ENTRY beamformee_entry;
+	struct _RT_BEAMFORMER_ENTRY beamformer_entry;
+	u16 sta_id = 0;
+
+	PHYDM_DBG(dm, DBG_TXBF, "[%s] Start!\n", __func__);
+
+	hal_txbf_8192e_rf_mode(dm, beamforming_info);
+
+	if (dm->rf_type == RF_2T2R)
+		odm_write_4byte(dm, 0xd80, 0x00000000); /*nc =2*/
+
+	if (beamforming_info->beamformer_su_cnt > 0 && bfer_idx < BEAMFORMER_ENTRY_NUM) {
+		beamformer_entry = beamforming_info->beamformer_entry[bfer_idx];
+
+		/*Sounding protocol control*/
+		odm_write_1byte(dm, REG_SND_PTCL_CTRL_8192E, 0xCB);
+
+		/*@MAC address/Partial AID of Beamformer*/
+		if (bfer_idx == 0) {
+			for (i = 0; i < 6; i++)
+				odm_write_1byte(dm, (REG_ASSOCIATED_BFMER0_INFO_8192E + i), beamformer_entry.mac_addr[i]);
+		} else {
+			for (i = 0; i < 6; i++)
+				odm_write_1byte(dm, (REG_ASSOCIATED_BFMER1_INFO_8192E + i), beamformer_entry.mac_addr[i]);
+		}
+
+		/*@CSI report parameters of Beamformer Default use nc = 2*/
+		csi_param = 0x03090309;
+
+		odm_write_4byte(dm, REG_CSI_RPT_PARAM_BW20_8192E, csi_param);
+		odm_write_4byte(dm, REG_CSI_RPT_PARAM_BW40_8192E, csi_param);
+		odm_write_4byte(dm, REG_CSI_RPT_PARAM_BW80_8192E, csi_param);
+
+		/*Timeout value for MAC to leave NDP_RX_standby_state (60 us, Test chip) (80 us,  MP chip)*/
+		odm_write_1byte(dm, REG_SND_PTCL_CTRL_8192E + 3, 0x50);
+	}
+
+	if (beamforming_info->beamformee_su_cnt > 0 && bfee_idx < BEAMFORMEE_ENTRY_NUM) {
+		beamformee_entry = beamforming_info->beamformee_entry[bfee_idx];
+
+		if (phydm_acting_determine(dm, phydm_acting_as_ibss))
+			sta_id = beamformee_entry.mac_id;
+		else
+			sta_id = beamformee_entry.p_aid;
+
+		PHYDM_DBG(dm, DBG_TXBF, "[%s], sta_id=0x%X\n", __func__,
+			  sta_id);
+
+		/*P_AID of Beamformee & enable NDPA transmission & enable NDPA interrupt*/
+		if (bfee_idx == 0) {
+			odm_write_2byte(dm, REG_TXBF_CTRL_8192E, sta_id);
+			odm_write_1byte(dm, REG_TXBF_CTRL_8192E + 3, odm_read_1byte(dm, REG_TXBF_CTRL_8192E + 3) | BIT(4) | BIT(6) | BIT(7));
+		} else
+			odm_write_2byte(dm, REG_TXBF_CTRL_8192E + 2, sta_id | BIT(12) | BIT(14) | BIT(15));
+
+		/*@CSI report parameters of Beamformee*/
+		if (bfee_idx == 0) {
+			/*@Get BIT24 & BIT25*/
+			u8 tmp = odm_read_1byte(dm, REG_ASSOCIATED_BFMEE_SEL_8192E + 3) & 0x3;
+
+			odm_write_1byte(dm, REG_ASSOCIATED_BFMEE_SEL_8192E + 3, tmp | 0x60);
+			odm_write_2byte(dm, REG_ASSOCIATED_BFMEE_SEL_8192E, sta_id | BIT(9));
+		} else {
+			/*Set BIT25*/
+			odm_write_2byte(dm, REG_ASSOCIATED_BFMEE_SEL_8192E + 2, sta_id | 0xE200);
+		}
+		phydm_beamforming_notify(dm);
+	}
+}
+
+void hal_txbf_8192e_leave(
+	void *dm_void,
+	u8 idx)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct _RT_BEAMFORMING_INFO *beam_info = &dm->beamforming_info;
+
+	hal_txbf_8192e_rf_mode(dm, beam_info);
+
+	/*	@Clear P_AID of Beamformee
+	*	Clear MAC addresss of Beamformer
+	*	Clear Associated Bfmee Sel
+	*/
+	if (beam_info->beamform_cap == BEAMFORMING_CAP_NONE)
+		odm_write_1byte(dm, REG_SND_PTCL_CTRL_8192E, 0xC8);
+
+	if (idx == 0) {
+		odm_write_2byte(dm, REG_TXBF_CTRL_8192E, 0);
+		odm_write_4byte(dm, REG_ASSOCIATED_BFMER0_INFO_8192E, 0);
+		odm_write_2byte(dm, REG_ASSOCIATED_BFMER0_INFO_8192E + 4, 0);
+		odm_write_2byte(dm, REG_ASSOCIATED_BFMEE_SEL_8192E, 0);
+	} else {
+		odm_write_2byte(dm, REG_TXBF_CTRL_8192E + 2, odm_read_1byte(dm, REG_TXBF_CTRL_8192E + 2) & 0xF000);
+		odm_write_4byte(dm, REG_ASSOCIATED_BFMER1_INFO_8192E, 0);
+		odm_write_2byte(dm, REG_ASSOCIATED_BFMER1_INFO_8192E + 4, 0);
+		odm_write_2byte(dm, REG_ASSOCIATED_BFMEE_SEL_8192E + 2, odm_read_2byte(dm, REG_ASSOCIATED_BFMEE_SEL_8192E + 2) & 0x60);
+	}
+
+	PHYDM_DBG(dm, DBG_TXBF, "[%s] idx %d\n", __func__, idx);
+}
+
+void hal_txbf_8192e_status(
+	void *dm_void,
+	u8 idx)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	u16 beam_ctrl_val;
+	u32 beam_ctrl_reg;
+	struct _RT_BEAMFORMING_INFO *beam_info = &dm->beamforming_info;
+	struct _RT_BEAMFORMEE_ENTRY beamform_entry = beam_info->beamformee_entry[idx];
+
+	if (phydm_acting_determine(dm, phydm_acting_as_ibss))
+		beam_ctrl_val = beamform_entry.mac_id;
+	else
+		beam_ctrl_val = beamform_entry.p_aid;
+
+	if (idx == 0)
+		beam_ctrl_reg = REG_TXBF_CTRL_8192E;
+	else {
+		beam_ctrl_reg = REG_TXBF_CTRL_8192E + 2;
+		beam_ctrl_val |= BIT(12) | BIT(14) | BIT(15);
+	}
+
+	if (beamform_entry.beamform_entry_state == BEAMFORMING_ENTRY_STATE_PROGRESSED && beam_info->apply_v_matrix == true) {
+		if (beamform_entry.sound_bw == CHANNEL_WIDTH_20)
+			beam_ctrl_val |= BIT(9);
+		else if (beamform_entry.sound_bw == CHANNEL_WIDTH_40)
+			beam_ctrl_val |= BIT(10);
+	} else
+		beam_ctrl_val &= ~(BIT(9) | BIT(10) | BIT(11));
+
+	odm_write_2byte(dm, beam_ctrl_reg, beam_ctrl_val);
+
+	PHYDM_DBG(dm, DBG_TXBF,
+		  "[%s] idx %d beam_ctrl_reg %x beam_ctrl_val %x\n", __func__,
+		  idx, beam_ctrl_reg, beam_ctrl_val);
+}
+
+void hal_txbf_8192e_fw_tx_bf(
+	void *dm_void,
+	u8 idx)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct _RT_BEAMFORMING_INFO *beam_info = &dm->beamforming_info;
+	struct _RT_BEAMFORMEE_ENTRY *p_beam_entry = beam_info->beamformee_entry + idx;
+
+	PHYDM_DBG(dm, DBG_TXBF, "[%s] Start!\n", __func__);
+
+	if (p_beam_entry->beamform_entry_state == BEAMFORMING_ENTRY_STATE_PROGRESSING)
+		hal_txbf_8192e_download_ndpa(dm, idx);
+
+	hal_txbf_8192e_fw_txbf_cmd(dm);
+}
+
+#endif /* @#if (RTL8192E_SUPPORT == 1)*/
+
+#endif
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/txbf/haltxbf8192e.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/txbf/haltxbf8192e.h
--- linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/txbf/haltxbf8192e.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/txbf/haltxbf8192e.h	2020-04-10 16:35:06.835660954 +0300
@@ -0,0 +1,71 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017  Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * The full GNU General Public License is included in this distribution in the
+ * file called LICENSE.
+ *
+ * Contact Information:
+ * wlanfae <wlanfae@realtek.com>
+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
+ * Hsinchu 300, Taiwan.
+ *
+ * Larry Finger <Larry.Finger@lwfinger.net>
+ *
+ *****************************************************************************/
+#ifndef __HAL_TXBF_8192E_H__
+#define __HAL_TXBF_8192E_H__
+
+#if (RTL8192E_SUPPORT == 1)
+#if (BEAMFORMING_SUPPORT == 1)
+
+void hal_txbf_8192e_set_ndpa_rate(
+	void *dm_void,
+	u8 BW,
+	u8 rate);
+
+void hal_txbf_8192e_enter(
+	void *dm_void,
+	u8 idx);
+
+void hal_txbf_8192e_leave(
+	void *dm_void,
+	u8 idx);
+
+void hal_txbf_8192e_status(
+	void *dm_void,
+	u8 idx);
+
+void hal_txbf_8192e_fw_tx_bf(
+	void *dm_void,
+	u8 idx);
+#else
+
+#define hal_txbf_8192e_set_ndpa_rate(dm_void, BW, rate)
+#define hal_txbf_8192e_enter(dm_void, idx)
+#define hal_txbf_8192e_leave(dm_void, idx)
+#define hal_txbf_8192e_status(dm_void, idx)
+#define hal_txbf_8192e_fw_tx_bf(dm_void, idx)
+
+#endif
+
+#else
+
+#define hal_txbf_8192e_set_ndpa_rate(dm_void, BW, rate)
+#define hal_txbf_8192e_enter(dm_void, idx)
+#define hal_txbf_8192e_leave(dm_void, idx)
+#define hal_txbf_8192e_status(dm_void, idx)
+#define hal_txbf_8192e_fw_tx_bf(dm_void, idx)
+
+#endif
+
+#endif
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/txbf/haltxbf8814a.c linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/txbf/haltxbf8814a.c
--- linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/txbf/haltxbf8814a.c	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/txbf/haltxbf8814a.c	2020-04-10 16:35:06.835660954 +0300
@@ -0,0 +1,675 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2016 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+/* ************************************************************
+ * Description:
+ *
+ * This file is for 8814A TXBF mechanism
+ *
+ * ************************************************************ */
+
+#include "mp_precomp.h"
+#include "../phydm_precomp.h"
+
+#if (BEAMFORMING_SUPPORT == 1)
+#if (RTL8814A_SUPPORT == 1)
+
+boolean
+phydm_beamforming_set_iqgen_8814A(void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	u8 i = 0;
+	u16 counter = 0;
+	u32 rf_mode[4];
+
+	for (i = RF_PATH_A; i < MAX_RF_PATH; i++)
+		odm_set_rf_reg(dm, i, RF_WE_LUT, 0x80000, 0x1); /*RF mode table write enable*/
+
+	while (1) {
+		counter++;
+		for (i = RF_PATH_A; i < MAX_RF_PATH; i++)
+			odm_set_rf_reg(dm, i, RF_RCK_OS, 0xfffff, 0x18000); /*Select Rx mode*/
+
+		ODM_delay_us(2);
+
+		for (i = RF_PATH_A; i < MAX_RF_PATH; i++)
+			rf_mode[i] = odm_get_rf_reg(dm, i, RF_RCK_OS, 0xfffff);
+
+		if (rf_mode[0] == 0x18000 && rf_mode[1] == 0x18000 && rf_mode[2] == 0x18000 && rf_mode[3] == 0x18000)
+			break;
+		else if (counter == 100) {
+			PHYDM_DBG(dm, DBG_TXBF, "iqgen setting fail:8814A\n");
+			return false;
+		}
+	}
+
+	for (i = RF_PATH_A; i < MAX_RF_PATH; i++) {
+		odm_set_rf_reg(dm, i, RF_TXPA_G1, 0xfffff, 0xBE77F); /*Set Table data*/
+		odm_set_rf_reg(dm, i, RF_TXPA_G2, 0xfffff, 0x226BF); /*@Enable TXIQGEN in Rx mode*/
+	}
+	odm_set_rf_reg(dm, RF_PATH_A, RF_TXPA_G2, 0xfffff, 0xE26BF); /*@Enable TXIQGEN in Rx mode*/
+
+	for (i = RF_PATH_A; i < MAX_RF_PATH; i++)
+		odm_set_rf_reg(dm, i, RF_WE_LUT, 0x80000, 0x0); /*RF mode table write disable*/
+
+	return true;
+}
+
+void hal_txbf_8814a_set_ndpa_rate(void *dm_void, u8 BW, u8 rate)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+
+	odm_write_1byte(dm, REG_NDPA_OPT_CTRL_8814A, BW);
+	odm_write_1byte(dm, REG_NDPA_RATE_8814A, (u8)rate);
+}
+#if 0
+#define PHYDM_MEMORY_MAP_BUF_READ 0x8000
+#define PHYDM_CTRL_INFO_PAGE 0x660
+
+void
+phydm_data_rate_8814a(
+	struct dm_struct			*dm,
+	u8				mac_id,
+	u32				*data,
+	u8				data_len
+)
+{
+	u8	i = 0;
+	u16	x_read_data_addr = 0;
+
+	odm_write_2byte(dm, REG_PKTBUF_DBG_CTRL_8814A, PHYDM_CTRL_INFO_PAGE);
+	x_read_data_addr = PHYDM_MEMORY_MAP_BUF_READ + mac_id * 32; /*@Ctrl Info: 32Bytes for each macid(n)*/
+
+	if (x_read_data_addr < PHYDM_MEMORY_MAP_BUF_READ || x_read_data_addr > 0x8FFF) {
+		PHYDM_DBG(dm, DBG_TXBF,
+			  "x_read_data_addr(0x%x) is not correct!\n",
+			  x_read_data_addr);
+		return;
+	}
+
+	/* Read data */
+	for (i = 0; i < data_len; i++)
+		*(data + i) = odm_read_2byte(dm, x_read_data_addr + i);
+}
+#endif
+
+void hal_txbf_8814a_get_tx_rate(void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct _RT_BEAMFORMING_INFO *beam_info = &dm->beamforming_info;
+	struct _RT_BEAMFORMEE_ENTRY *entry;
+	struct ra_table *ra_tab = &dm->dm_ra_table;
+	struct cmn_sta_info *sta = NULL;
+	u8 data_rate = 0xFF;
+	u8 macid = 0;
+
+	entry = &(beam_info->beamformee_entry[beam_info->beamformee_cur_idx]);
+	macid = (u8)entry->mac_id;
+
+	sta = dm->phydm_sta_info[macid];
+
+	if (is_sta_active(sta)) {
+		data_rate = (sta->ra_info.curr_tx_rate) & 0x7f; /*@Bit7 indicates SGI*/
+		beam_info->tx_bf_data_rate = data_rate;
+	}
+
+	PHYDM_DBG(dm, DBG_TXBF, "[%s] dm->tx_bf_data_rate = 0x%x\n", __func__,
+		  beam_info->tx_bf_data_rate);
+}
+
+void hal_txbf_8814a_reset_tx_path(void *dm_void, u8 idx)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+#if DEV_BUS_TYPE == RT_USB_INTERFACE
+	struct _RT_BEAMFORMING_INFO *beamforming_info = &dm->beamforming_info;
+	struct _RT_BEAMFORMEE_ENTRY beamformee_entry;
+	u8 nr_index = 0, tx_ss = 0;
+
+	if (idx < BEAMFORMEE_ENTRY_NUM)
+		beamformee_entry = beamforming_info->beamformee_entry[idx];
+	else
+		return;
+
+	if (beamforming_info->last_usb_hub != (*dm->hub_usb_mode)) {
+		nr_index = tx_bf_nr(hal_txbf_8814a_get_ntx(dm), beamformee_entry.comp_steering_num_of_bfer);
+
+		if (*dm->hub_usb_mode == 2) {
+			if (dm->rf_type == RF_4T4R)
+				tx_ss = 0xf;
+			else if (dm->rf_type == RF_3T3R)
+				tx_ss = 0xe;
+			else
+				tx_ss = 0x6;
+		} else if (*dm->hub_usb_mode == 1) /*USB 2.0 always 2Tx*/
+			tx_ss = 0x6;
+		else
+			tx_ss = 0x6;
+
+		if (tx_ss == 0xf) {
+			odm_set_bb_reg(dm, REG_BB_TX_PATH_SEL_1_8814A, MASKBYTE3 | MASKBYTE2HIGHNIBBLE, 0x93f);
+			odm_set_bb_reg(dm, REG_BB_TX_PATH_SEL_1_8814A, MASKDWORD, 0x93f93f0);
+		} else if (tx_ss == 0xe) {
+			odm_set_bb_reg(dm, REG_BB_TX_PATH_SEL_1_8814A, MASKBYTE3 | MASKBYTE2HIGHNIBBLE, 0x93e);
+			odm_set_bb_reg(dm, REG_BB_TX_PATH_SEL_2_8814A, MASKDWORD, 0x93e93e0);
+		} else if (tx_ss == 0x6) {
+			odm_set_bb_reg(dm, REG_BB_TX_PATH_SEL_1_8814A, MASKBYTE3 | MASKBYTE2HIGHNIBBLE, 0x936);
+			odm_set_bb_reg(dm, REG_BB_TX_PATH_SEL_2_8814A, MASKLWORD, 0x9360);
+		}
+
+		if (idx == 0) {
+			switch (nr_index) {
+			case 0:
+				break;
+
+			case 1: /*Nsts = 2	BC*/
+				odm_set_bb_reg(dm, REG_BB_TXBF_ANT_SET_BF0_8814A, MASKBYTE3LOWNIBBLE | MASKL3BYTES, 0x9366); /*tx2path, BC*/
+				break;
+
+			case 2: /*Nsts = 3	BCD*/
+				odm_set_bb_reg(dm, REG_BB_TXBF_ANT_SET_BF0_8814A, MASKBYTE3LOWNIBBLE | MASKL3BYTES, 0x93e93ee); /*tx3path, BCD*/
+				break;
+
+			default: /*nr>3, same as Case 3*/
+				odm_set_bb_reg(dm, REG_BB_TXBF_ANT_SET_BF0_8814A, MASKBYTE3LOWNIBBLE | MASKL3BYTES, 0x93f93ff); /*tx4path, ABCD*/
+				break;
+			}
+		} else {
+			switch (nr_index) {
+			case 0:
+				break;
+
+			case 1: /*Nsts = 2	BC*/
+				odm_set_bb_reg(dm, REG_BB_TXBF_ANT_SET_BF1_8814A, MASKBYTE3LOWNIBBLE | MASKL3BYTES, 0x9366); /*tx2path, BC*/
+				break;
+
+			case 2: /*Nsts = 3	BCD*/
+				odm_set_bb_reg(dm, REG_BB_TXBF_ANT_SET_BF1_8814A, MASKBYTE3LOWNIBBLE | MASKL3BYTES, 0x93e93ee); /*tx3path, BCD*/
+				break;
+
+			default: /*nr>3, same as Case 3*/
+				odm_set_bb_reg(dm, REG_BB_TXBF_ANT_SET_BF1_8814A, MASKBYTE3LOWNIBBLE | MASKL3BYTES, 0x93f93ff); /*tx4path, ABCD*/
+				break;
+			}
+		}
+
+		beamforming_info->last_usb_hub = *dm->hub_usb_mode;
+	} else
+		return;
+#endif
+}
+
+u8 hal_txbf_8814a_get_ntx(void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	u8 ntx = 0, tx_ss = 3;
+
+#if DEV_BUS_TYPE == RT_USB_INTERFACE
+	tx_ss = *dm->hub_usb_mode;
+#endif
+	if (tx_ss == 3 || tx_ss == 2) {
+		if (dm->rf_type == RF_4T4R)
+			ntx = 3;
+		else if (dm->rf_type == RF_3T3R)
+			ntx = 2;
+		else
+			ntx = 1;
+	} else if (tx_ss == 1) /*USB 2.0 always 2Tx*/
+		ntx = 1;
+	else
+		ntx = 1;
+
+	PHYDM_DBG(dm, DBG_TXBF, "[%s] ntx = %d\n", __func__, ntx);
+	return ntx;
+}
+
+u8 hal_txbf_8814a_get_nrx(void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	u8 nrx = 0;
+
+	if (dm->rf_type == RF_4T4R)
+		nrx = 3;
+	else if (dm->rf_type == RF_3T3R)
+		nrx = 2;
+	else if (dm->rf_type == RF_2T2R)
+		nrx = 1;
+	else if (dm->rf_type == RF_2T3R)
+		nrx = 2;
+	else if (dm->rf_type == RF_2T4R)
+		nrx = 3;
+	else if (dm->rf_type == RF_1T1R)
+		nrx = 0;
+	else if (dm->rf_type == RF_1T2R)
+		nrx = 1;
+	else
+		nrx = 0;
+
+	PHYDM_DBG(dm, DBG_TXBF, "[%s] nrx = %d\n", __func__, nrx);
+	return nrx;
+}
+
+void hal_txbf_8814a_rf_mode(void *dm_void,
+			    struct _RT_BEAMFORMING_INFO *beamforming_info,
+			    u8 idx)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	u8 nr_index = 0;
+	u8 tx_ss = 3; /*@default use 3 Tx*/
+	struct _RT_BEAMFORMEE_ENTRY beamformee_entry;
+
+	if (idx < BEAMFORMEE_ENTRY_NUM)
+		beamformee_entry = beamforming_info->beamformee_entry[idx];
+	else
+		return;
+
+	nr_index = tx_bf_nr(hal_txbf_8814a_get_ntx(dm), beamformee_entry.comp_steering_num_of_bfer);
+
+	if (dm->rf_type == RF_1T1R)
+		return;
+
+	if (beamforming_info->beamformee_su_cnt > 0) {
+#if DEV_BUS_TYPE == RT_USB_INTERFACE
+		beamforming_info->last_usb_hub = *dm->hub_usb_mode;
+		tx_ss = *dm->hub_usb_mode;
+#endif
+		if (tx_ss == 3 || tx_ss == 2) {
+			if (dm->rf_type == RF_4T4R)
+				tx_ss = 0xf;
+			else if (dm->rf_type == RF_3T3R)
+				tx_ss = 0xe;
+			else
+				tx_ss = 0x6;
+		} else if (tx_ss == 1) /*USB 2.0 always 2Tx*/
+			tx_ss = 0x6;
+		else
+			tx_ss = 0x6;
+
+		if (tx_ss == 0xf) {
+			odm_set_bb_reg(dm, REG_BB_TX_PATH_SEL_1_8814A, MASKBYTE3 | MASKBYTE2HIGHNIBBLE, 0x93f);
+			odm_set_bb_reg(dm, REG_BB_TX_PATH_SEL_1_8814A, MASKDWORD, 0x93f93f0);
+		} else if (tx_ss == 0xe) {
+			odm_set_bb_reg(dm, REG_BB_TX_PATH_SEL_1_8814A, MASKBYTE3 | MASKBYTE2HIGHNIBBLE, 0x93e);
+			odm_set_bb_reg(dm, REG_BB_TX_PATH_SEL_2_8814A, MASKDWORD, 0x93e93e0);
+		} else if (tx_ss == 0x6) {
+			odm_set_bb_reg(dm, REG_BB_TX_PATH_SEL_1_8814A, MASKBYTE3 | MASKBYTE2HIGHNIBBLE, 0x936);
+			odm_set_bb_reg(dm, REG_BB_TX_PATH_SEL_2_8814A, MASKLWORD, 0x9360);
+		}
+
+		/*@for 8814 19ac(idx 1), 19b4(idx 0), different Tx ant setting*/
+		odm_set_bb_reg(dm, REG_BB_TXBF_ANT_SET_BF1_8814A, BIT(28) | BIT29, 0x2); /*@enable BB TxBF ant mapping register*/
+		odm_set_bb_reg(dm, REG_BB_TXBF_ANT_SET_BF1_8814A, BIT30, 0x1); /*@if Nsts > Nc don't apply V matrix*/
+
+		if (idx == 0) {
+			switch (nr_index) {
+			case 0:
+				break;
+
+			case 1: /*Nsts = 2	BC*/
+				odm_set_bb_reg(dm, REG_BB_TXBF_ANT_SET_BF0_8814A, MASKBYTE3LOWNIBBLE | MASKL3BYTES, 0x9366); /*tx2path, BC*/
+				break;
+
+			case 2: /*Nsts = 3	BCD*/
+				odm_set_bb_reg(dm, REG_BB_TXBF_ANT_SET_BF0_8814A, MASKBYTE3LOWNIBBLE | MASKL3BYTES, 0x93e93ee); /*tx3path, BCD*/
+				break;
+
+			default: /*nr>3, same as Case 3*/
+				odm_set_bb_reg(dm, REG_BB_TXBF_ANT_SET_BF0_8814A, MASKBYTE3LOWNIBBLE | MASKL3BYTES, 0x93f93ff); /*tx4path, ABCD*/
+
+				break;
+			}
+		} else {
+			switch (nr_index) {
+			case 0:
+				break;
+
+			case 1: /*Nsts = 2	BC*/
+				odm_set_bb_reg(dm, REG_BB_TXBF_ANT_SET_BF1_8814A, MASKBYTE3LOWNIBBLE | MASKL3BYTES, 0x9366); /*tx2path, BC*/
+				break;
+
+			case 2: /*Nsts = 3	BCD*/
+				odm_set_bb_reg(dm, REG_BB_TXBF_ANT_SET_BF1_8814A, MASKBYTE3LOWNIBBLE | MASKL3BYTES, 0x93e93ee); /*tx3path, BCD*/
+				break;
+
+			default: /*nr>3, same as Case 3*/
+				odm_set_bb_reg(dm, REG_BB_TXBF_ANT_SET_BF1_8814A, MASKBYTE3LOWNIBBLE | MASKL3BYTES, 0x93f93ff); /*tx4path, ABCD*/
+				break;
+			}
+		}
+	}
+
+	if (beamforming_info->beamformee_su_cnt == 0 && beamforming_info->beamformer_su_cnt == 0) {
+		odm_set_bb_reg(dm, REG_BB_TX_PATH_SEL_1_8814A, MASKBYTE3 | MASKBYTE2HIGHNIBBLE, 0x932); /*set tx_path selection for 8814a BFer bug refine*/
+		odm_set_bb_reg(dm, REG_BB_TX_PATH_SEL_2_8814A, MASKDWORD, 0x93e9360);
+	}
+}
+#if 0
+void
+hal_txbf_8814a_download_ndpa(
+	void			*dm_void,
+	u8				idx
+)
+{
+	struct dm_struct	*dm = (struct dm_struct *)dm_void;
+	u8			u1b_tmp = 0, tmp_reg422 = 0;
+	u8			bcn_valid_reg = 0, count = 0, dl_bcn_count = 0;
+	u16			head_page = 0x7FE;
+	boolean			is_send_beacon = false;
+	u16			tx_page_bndy = LAST_ENTRY_OF_TX_PKT_BUFFER_8814A; /*@default reseved 1 page for the IC type which is undefined.*/
+	struct _RT_BEAMFORMING_INFO	*beam_info = &dm->beamforming_info;
+	struct _RT_BEAMFORMEE_ENTRY	*p_beam_entry = beam_info->beamformee_entry + idx;
+	void		*adapter = dm->adapter;
+
+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
+	*dm->is_fw_dw_rsvd_page_in_progress = true;
+#endif
+	PHYDM_DBG(dm, DBG_TXBF, "[%s] Start!\n", __func__);
+
+	phydm_get_hal_def_var_handler_interface(dm, HAL_DEF_TX_PAGE_BOUNDARY, (u16 *)&tx_page_bndy);
+
+	/*Set REG_CR bit 8. DMA beacon by SW.*/
+	u1b_tmp = odm_read_1byte(dm, REG_CR_8814A + 1);
+	odm_write_1byte(dm,  REG_CR_8814A + 1, (u1b_tmp | BIT(0)));
+
+
+	/*Set FWHW_TXQ_CTRL 0x422[6]=0 to tell Hw the packet is not a real beacon frame.*/
+	tmp_reg422 = odm_read_1byte(dm, REG_FWHW_TXQ_CTRL_8814A + 2);
+	odm_write_1byte(dm, REG_FWHW_TXQ_CTRL_8814A + 2,  tmp_reg422 & (~BIT(6)));
+
+	if (tmp_reg422 & BIT(6)) {
+		PHYDM_DBG(dm, DBG_TXBF,
+			  "%s: There is an adapter is sending beacon.\n",
+			  __func__);
+		is_send_beacon = true;
+	}
+
+	/*@0x204[11:0]	Beacon Head for TXDMA*/
+	odm_write_2byte(dm, REG_FIFOPAGE_CTRL_2_8814A, head_page);
+
+	do {
+		/*@Clear beacon valid check bit.*/
+		bcn_valid_reg = odm_read_1byte(dm, REG_FIFOPAGE_CTRL_2_8814A + 1);
+		odm_write_1byte(dm, REG_FIFOPAGE_CTRL_2_8814A + 1, (bcn_valid_reg | BIT(7)));
+
+		/*@download NDPA rsvd page.*/
+		if (p_beam_entry->beamform_entry_cap & BEAMFORMER_CAP_VHT_SU)
+			beamforming_send_vht_ndpa_packet(dm, p_beam_entry->mac_addr, p_beam_entry->AID, p_beam_entry->sound_bw, BEACON_QUEUE);
+		else
+			beamforming_send_ht_ndpa_packet(dm, p_beam_entry->mac_addr, p_beam_entry->sound_bw, BEACON_QUEUE);
+
+		/*@check rsvd page download OK.*/
+		bcn_valid_reg = odm_read_1byte(dm, REG_FIFOPAGE_CTRL_2_8814A + 1);
+		count = 0;
+		while (!(bcn_valid_reg & BIT(7)) && count < 20) {
+			count++;
+			ODM_delay_ms(10);
+			bcn_valid_reg = odm_read_1byte(dm, REG_FIFOPAGE_CTRL_2_8814A + 2);
+		}
+		dl_bcn_count++;
+	} while (!(bcn_valid_reg & BIT(7)) && dl_bcn_count < 5);
+
+	if (!(bcn_valid_reg & BIT(7)))
+		PHYDM_DBG(dm, DBG_TXBF, "%s Download RSVD page failed!\n",
+			  __func__);
+
+	/*@0x204[11:0]	Beacon Head for TXDMA*/
+	odm_write_2byte(dm, REG_FIFOPAGE_CTRL_2_8814A, tx_page_bndy);
+
+	/*To make sure that if there exists an adapter which would like to send beacon.*/
+	/*@If exists, the origianl value of 0x422[6] will be 1, we should check this to*/
+	/*prevent from setting 0x422[6] to 0 after download reserved page, or it will cause */
+	/*the beacon cannot be sent by HW.*/
+	/*@2010.06.23. Added by tynli.*/
+	if (is_send_beacon)
+		odm_write_1byte(dm, REG_FWHW_TXQ_CTRL_8814A + 2, tmp_reg422);
+
+	/*@Do not enable HW DMA BCN or it will cause Pcie interface hang by timing issue. 2011.11.24. by tynli.*/
+	/*@Clear CR[8] or beacon packet will not be send to TxBuf anymore.*/
+	u1b_tmp = odm_read_1byte(dm, REG_CR_8814A + 1);
+	odm_write_1byte(dm, REG_CR_8814A + 1, (u1b_tmp & (~BIT(0))));
+
+	p_beam_entry->beamform_entry_state = BEAMFORMING_ENTRY_STATE_PROGRESSED;
+
+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
+	*dm->is_fw_dw_rsvd_page_in_progress = false;
+#endif
+}
+
+void
+hal_txbf_8814a_fw_txbf_cmd(
+	void			*dm_void
+)
+{
+	struct dm_struct	*dm = (struct dm_struct *)dm_void;
+	u8	idx, period = 0;
+	u8	PageNum0 = 0xFF, PageNum1 = 0xFF;
+	u8	u1_tx_bf_parm[3] = {0};
+	struct _RT_BEAMFORMING_INFO *beam_info = &dm->beamforming_info;
+
+	for (idx = 0; idx < BEAMFORMEE_ENTRY_NUM; idx++) {
+		if (beam_info->beamformee_entry[idx].is_used && beam_info->beamformee_entry[idx].beamform_entry_state == BEAMFORMING_ENTRY_STATE_PROGRESSED) {
+			if (beam_info->beamformee_entry[idx].is_sound) {
+				PageNum0 = 0xFE;
+				PageNum1 = 0x07;
+				period = (u8)(beam_info->beamformee_entry[idx].sound_period);
+			} else if (PageNum0 == 0xFF) {
+				PageNum0 = 0xFF; /*stop sounding*/
+				PageNum1 = 0x0F;
+			}
+		}
+	}
+
+	u1_tx_bf_parm[0] = PageNum0;
+	u1_tx_bf_parm[1] = PageNum1;
+	u1_tx_bf_parm[2] = period;
+	odm_fill_h2c_cmd(dm, PHYDM_H2C_TXBF, 3, u1_tx_bf_parm);
+
+	PHYDM_DBG(dm, DBG_TXBF,
+		  "[%s] PageNum0 = %d, PageNum1 = %d period = %d\n", __func__,
+		  PageNum0, PageNum1, period);
+}
+#endif
+void hal_txbf_8814a_enter(void *dm_void, u8 bfer_bfee_idx)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	u8 i = 0;
+	u8 bfer_idx = (bfer_bfee_idx & 0xF0) >> 4;
+	u8 bfee_idx = (bfer_bfee_idx & 0xF);
+	struct _RT_BEAMFORMING_INFO *beamforming_info = &dm->beamforming_info;
+	struct _RT_BEAMFORMEE_ENTRY beamformee_entry;
+	struct _RT_BEAMFORMER_ENTRY beamformer_entry;
+	u16 sta_id = 0, csi_param = 0;
+	u8 nc_index = 0, nr_index = 0, grouping = 0, codebookinfo = 0, coefficientsize = 0;
+
+	PHYDM_DBG(dm, DBG_TXBF, "[%s] bfer_idx=%d, bfee_idx=%d\n", __func__,
+		  bfer_idx, bfee_idx);
+	odm_set_mac_reg(dm, REG_SND_PTCL_CTRL_8814A, MASKBYTE1 | MASKBYTE2, 0x0202);
+
+	if (beamforming_info->beamformer_su_cnt > 0 && bfer_idx < BEAMFORMER_ENTRY_NUM) {
+		beamformer_entry = beamforming_info->beamformer_entry[bfer_idx];
+		/*Sounding protocol control*/
+		odm_write_1byte(dm, REG_SND_PTCL_CTRL_8814A, 0xDB);
+
+		/*@MAC address/Partial AID of Beamformer*/
+		if (bfer_idx == 0) {
+			for (i = 0; i < 6; i++)
+				odm_write_1byte(dm, (REG_ASSOCIATED_BFMER0_INFO_8814A + i), beamformer_entry.mac_addr[i]);
+		} else {
+			for (i = 0; i < 6; i++)
+				odm_write_1byte(dm, (REG_ASSOCIATED_BFMER1_INFO_8814A + i), beamformer_entry.mac_addr[i]);
+		}
+
+		/*@CSI report parameters of Beamformer*/
+		nc_index = hal_txbf_8814a_get_nrx(dm); /*@for 8814A nrx = 3(4 ant), min=0(1 ant)*/
+		nr_index = beamformer_entry.num_of_sounding_dim; /*@0x718[7] = 1 use Nsts, 0x718[7] = 0 use reg setting. as Bfee, we use Nsts, so nr_index don't care*/
+
+		grouping = 0;
+
+		/*@for ac = 1, for n = 3*/
+		if (beamformer_entry.beamform_entry_cap & BEAMFORMEE_CAP_VHT_SU)
+			codebookinfo = 1;
+		else if (beamformer_entry.beamform_entry_cap & BEAMFORMEE_CAP_HT_EXPLICIT)
+			codebookinfo = 3;
+
+		coefficientsize = 3;
+
+		csi_param = (u16)((coefficientsize << 10) | (codebookinfo << 8) | (grouping << 6) | (nr_index << 3) | (nc_index));
+
+		if (bfer_idx == 0)
+			odm_write_2byte(dm, REG_CSI_RPT_PARAM_BW20_8814A, csi_param);
+		else
+			odm_write_2byte(dm, REG_CSI_RPT_PARAM_BW20_8814A + 2, csi_param);
+		/*ndp_rx_standby_timer, 8814 need > 0x56, suggest from Dvaid*/
+		odm_write_1byte(dm, REG_SND_PTCL_CTRL_8814A + 3, 0x40);
+	}
+
+	if (beamforming_info->beamformee_su_cnt > 0 && bfee_idx < BEAMFORMEE_ENTRY_NUM) {
+		beamformee_entry = beamforming_info->beamformee_entry[bfee_idx];
+
+		hal_txbf_8814a_rf_mode(dm, beamforming_info, bfee_idx);
+
+		if (phydm_acting_determine(dm, phydm_acting_as_ibss))
+			sta_id = beamformee_entry.mac_id;
+		else
+			sta_id = beamformee_entry.p_aid;
+
+		/*P_AID of Beamformee & enable NDPA transmission & enable NDPA interrupt*/
+		if (bfee_idx == 0) {
+			odm_write_2byte(dm, REG_TXBF_CTRL_8814A, sta_id);
+			odm_write_1byte(dm, REG_TXBF_CTRL_8814A + 3, odm_read_1byte(dm, REG_TXBF_CTRL_8814A + 3) | BIT(4) | BIT(6) | BIT(7));
+		} else
+			odm_write_2byte(dm, REG_TXBF_CTRL_8814A + 2, sta_id | BIT(14) | BIT(15) | BIT(12));
+
+		/*@CSI report parameters of Beamformee*/
+		if (bfee_idx == 0) {
+			/*@Get BIT24 & BIT25*/
+			u8 tmp = odm_read_1byte(dm, REG_ASSOCIATED_BFMEE_SEL_8814A + 3) & 0x3;
+
+			odm_write_1byte(dm, REG_ASSOCIATED_BFMEE_SEL_8814A + 3, tmp | 0x60);
+			odm_write_2byte(dm, REG_ASSOCIATED_BFMEE_SEL_8814A, sta_id | BIT(9));
+		} else
+			odm_write_2byte(dm, REG_ASSOCIATED_BFMEE_SEL_8814A + 2, sta_id | 0xE200); /*Set BIT25*/
+
+		phydm_beamforming_notify(dm);
+	}
+}
+
+void hal_txbf_8814a_leave(void *dm_void, u8 idx)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct _RT_BEAMFORMING_INFO *beamforming_info = &dm->beamforming_info;
+	struct _RT_BEAMFORMER_ENTRY beamformer_entry;
+	struct _RT_BEAMFORMEE_ENTRY beamformee_entry;
+
+	if (idx < BEAMFORMER_ENTRY_NUM) {
+		beamformer_entry = beamforming_info->beamformer_entry[idx];
+		beamformee_entry = beamforming_info->beamformee_entry[idx];
+	} else
+		return;
+
+	/*@Clear P_AID of Beamformee*/
+	/*@Clear MAC address of Beamformer*/
+	/*@Clear Associated Bfmee Sel*/
+
+	if (beamformer_entry.beamform_entry_cap == BEAMFORMING_CAP_NONE) {
+		odm_write_1byte(dm, REG_SND_PTCL_CTRL_8814A, 0xD8);
+		if (idx == 0) {
+			odm_write_4byte(dm, REG_ASSOCIATED_BFMER0_INFO_8814A, 0);
+			odm_write_2byte(dm, REG_ASSOCIATED_BFMER0_INFO_8814A + 4, 0);
+			odm_write_2byte(dm, REG_CSI_RPT_PARAM_BW20_8814A, 0);
+		} else {
+			odm_write_4byte(dm, REG_ASSOCIATED_BFMER1_INFO_8814A, 0);
+			odm_write_2byte(dm, REG_ASSOCIATED_BFMER1_INFO_8814A + 4, 0);
+			odm_write_2byte(dm, REG_CSI_RPT_PARAM_BW20_8814A + 2, 0);
+		}
+	}
+
+	if (beamformee_entry.beamform_entry_cap == BEAMFORMING_CAP_NONE) {
+		hal_txbf_8814a_rf_mode(dm, beamforming_info, idx);
+		if (idx == 0) {
+			odm_write_2byte(dm, REG_TXBF_CTRL_8814A, 0x0);
+			odm_write_1byte(dm, REG_TXBF_CTRL_8814A + 3, odm_read_1byte(dm, REG_TXBF_CTRL_8814A + 3) | BIT(4) | BIT(6) | BIT(7));
+			odm_write_2byte(dm, REG_ASSOCIATED_BFMEE_SEL_8814A, 0);
+		} else {
+			odm_write_2byte(dm, REG_TXBF_CTRL_8814A + 2, 0x0 | BIT(14) | BIT(15) | BIT(12));
+
+			odm_write_2byte(dm, REG_ASSOCIATED_BFMEE_SEL_8814A + 2, odm_read_2byte(dm, REG_ASSOCIATED_BFMEE_SEL_8814A + 2) & 0x60);
+		}
+	}
+}
+
+void hal_txbf_8814a_status(void *dm_void, u8 idx)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	u16 beam_ctrl_val, tmp_val;
+	u32 beam_ctrl_reg;
+	struct _RT_BEAMFORMING_INFO *beamforming_info = &dm->beamforming_info;
+	struct _RT_BEAMFORMEE_ENTRY beamform_entry;
+
+	if (idx < BEAMFORMEE_ENTRY_NUM)
+		beamform_entry = beamforming_info->beamformee_entry[idx];
+	else
+		return;
+
+	if (phydm_acting_determine(dm, phydm_acting_as_ibss))
+		beam_ctrl_val = beamform_entry.mac_id;
+	else
+		beam_ctrl_val = beamform_entry.p_aid;
+
+	PHYDM_DBG(dm, DBG_TXBF, "@%s, beamform_entry.beamform_entry_state = %d",
+		  __func__, beamform_entry.beamform_entry_state);
+
+	if (idx == 0)
+		beam_ctrl_reg = REG_TXBF_CTRL_8814A;
+	else {
+		beam_ctrl_reg = REG_TXBF_CTRL_8814A + 2;
+		beam_ctrl_val |= BIT(12) | BIT(14) | BIT(15);
+	}
+
+	if (beamform_entry.beamform_entry_state == BEAMFORMING_ENTRY_STATE_PROGRESSED && beamforming_info->apply_v_matrix == true) {
+		if (beamform_entry.sound_bw == CHANNEL_WIDTH_20)
+			beam_ctrl_val |= BIT(9);
+		else if (beamform_entry.sound_bw == CHANNEL_WIDTH_40)
+			beam_ctrl_val |= (BIT(9) | BIT(10));
+		else if (beamform_entry.sound_bw == CHANNEL_WIDTH_80)
+			beam_ctrl_val |= (BIT(9) | BIT(10) | BIT(11));
+	} else {
+		PHYDM_DBG(dm, DBG_TXBF, "@%s, Don't apply Vmatrix", __func__);
+		beam_ctrl_val &= ~(BIT(9) | BIT(10) | BIT(11));
+	}
+
+	odm_write_2byte(dm, beam_ctrl_reg, beam_ctrl_val);
+	/*@disable NDP packet use beamforming */
+	tmp_val = odm_read_2byte(dm, REG_TXBF_CTRL_8814A);
+	odm_write_2byte(dm, REG_TXBF_CTRL_8814A, tmp_val | BIT(15));
+}
+
+void hal_txbf_8814a_fw_txbf(void *dm_void, u8 idx)
+{
+#if 0
+	struct dm_struct	*dm = (struct dm_struct *)dm_void;
+	struct _RT_BEAMFORMING_INFO	*beam_info = &dm->beamforming_info;
+	struct _RT_BEAMFORMEE_ENTRY	*p_beam_entry = beam_info->beamformee_entry + idx;
+
+	PHYDM_DBG(dm, DBG_TXBF, "[%s] Start!\n", __func__);
+
+	if (p_beam_entry->beamform_entry_state == BEAMFORMING_ENTRY_STATE_PROGRESSING)
+		hal_txbf_8814a_download_ndpa(dm, idx);
+
+	hal_txbf_8814a_fw_txbf_cmd(dm);
+#endif
+}
+
+#endif /* @(RTL8814A_SUPPORT == 1)*/
+
+#endif
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/txbf/haltxbf8814a.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/txbf/haltxbf8814a.h
--- linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/txbf/haltxbf8814a.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/txbf/haltxbf8814a.h	2020-04-10 16:35:06.835660954 +0300
@@ -0,0 +1,77 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017  Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * The full GNU General Public License is included in this distribution in the
+ * file called LICENSE.
+ *
+ * Contact Information:
+ * wlanfae <wlanfae@realtek.com>
+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
+ * Hsinchu 300, Taiwan.
+ *
+ * Larry Finger <Larry.Finger@lwfinger.net>
+ *
+ *****************************************************************************/
+#ifndef __HAL_TXBF_8814A_H__
+#define __HAL_TXBF_8814A_H__
+
+#if (RTL8814A_SUPPORT == 1)
+#if (BEAMFORMING_SUPPORT == 1)
+
+boolean
+phydm_beamforming_set_iqgen_8814A(void *dm_void);
+
+void hal_txbf_8814a_set_ndpa_rate(void *dm_void, u8 BW, u8 rate);
+
+u8 hal_txbf_8814a_get_ntx(void *dm_void);
+
+void hal_txbf_8814a_enter(void *dm_void, u8 idx);
+
+void hal_txbf_8814a_leave(void *dm_void, u8 idx);
+
+void hal_txbf_8814a_status(void *dm_void, u8 idx);
+
+void hal_txbf_8814a_reset_tx_path(void *dm_void, u8 idx);
+
+void hal_txbf_8814a_get_tx_rate(void *dm_void);
+
+void hal_txbf_8814a_fw_txbf(void *dm_void, u8 idx);
+
+#else
+
+#define hal_txbf_8814a_set_ndpa_rate(dm_void, BW, rate)
+#define hal_txbf_8814a_get_ntx(dm_void) 0
+#define hal_txbf_8814a_enter(dm_void, idx)
+#define hal_txbf_8814a_leave(dm_void, idx)
+#define hal_txbf_8814a_status(dm_void, idx)
+#define hal_txbf_8814a_reset_tx_path(dm_void, idx)
+#define hal_txbf_8814a_get_tx_rate(dm_void)
+#define hal_txbf_8814a_fw_txbf(dm_void, idx)
+#define phydm_beamforming_set_iqgen_8814A(dm_void) 0
+
+#endif
+
+#else
+
+#define hal_txbf_8814a_set_ndpa_rate(dm_void, BW, rate)
+#define hal_txbf_8814a_get_ntx(dm_void) 0
+#define hal_txbf_8814a_enter(dm_void, idx)
+#define hal_txbf_8814a_leave(dm_void, idx)
+#define hal_txbf_8814a_status(dm_void, idx)
+#define hal_txbf_8814a_reset_tx_path(dm_void, idx)
+#define hal_txbf_8814a_get_tx_rate(dm_void)
+#define hal_txbf_8814a_fw_txbf(dm_void, idx)
+#define phydm_beamforming_set_iqgen_8814A(dm_void) 0
+#endif
+
+#endif
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/txbf/haltxbf8822b.c linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/txbf/haltxbf8822b.c
--- linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/txbf/haltxbf8822b.c	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/txbf/haltxbf8822b.c	2020-04-10 16:35:06.835660954 +0300
@@ -0,0 +1,1087 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2016 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+/*@============================================================*/
+/* @Description:                                              */
+/*                                                           @*/
+/* This file is for 8814A TXBF mechanism                     */
+/*                                                           @*/
+/*@============================================================*/
+
+#include "mp_precomp.h"
+#include "phydm_precomp.h"
+
+#if (RTL8822B_SUPPORT == 1)
+#if (BEAMFORMING_SUPPORT == 1)
+
+u8 hal_txbf_8822b_get_ntx(
+	void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	u8 ntx = 0;
+
+#if DEV_BUS_TYPE == RT_USB_INTERFACE
+	if (dm->support_interface == ODM_ITRF_USB) {
+		if (*dm->hub_usb_mode == 2) { /*USB3.0*/
+			if (dm->rf_type == RF_4T4R)
+				ntx = 3;
+			else if (dm->rf_type == RF_3T3R)
+				ntx = 2;
+			else
+				ntx = 1;
+		} else if (*dm->hub_usb_mode == 1) /*USB 2.0 always 2Tx*/
+			ntx = 1;
+		else
+			ntx = 1;
+	} else
+#endif
+	{
+		if (dm->rf_type == RF_4T4R)
+			ntx = 3;
+		else if (dm->rf_type == RF_3T3R)
+			ntx = 2;
+		else
+			ntx = 1;
+	}
+
+	return ntx;
+}
+
+u8 hal_txbf_8822b_get_nrx(
+	void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	u8 nrx = 0;
+
+	if (dm->rf_type == RF_4T4R)
+		nrx = 3;
+	else if (dm->rf_type == RF_3T3R)
+		nrx = 2;
+	else if (dm->rf_type == RF_2T2R)
+		nrx = 1;
+	else if (dm->rf_type == RF_2T3R)
+		nrx = 2;
+	else if (dm->rf_type == RF_2T4R)
+		nrx = 3;
+	else if (dm->rf_type == RF_1T1R)
+		nrx = 0;
+	else if (dm->rf_type == RF_1T2R)
+		nrx = 1;
+	else
+		nrx = 0;
+
+	return nrx;
+}
+
+/***************SU & MU BFee Entry********************/
+void hal_txbf_8822b_rf_mode(
+	void *dm_void,
+	struct _RT_BEAMFORMING_INFO *beamforming_info,
+	u8 idx)
+{
+#if 0
+	struct dm_struct	*dm = (struct dm_struct *)dm_void;
+	u8				i, nr_index = 0;
+	boolean				is_self_beamformer = false;
+	boolean				is_self_beamformee = false;
+	struct _RT_BEAMFORMEE_ENTRY	beamformee_entry;
+
+	if (idx < BEAMFORMEE_ENTRY_NUM)
+		beamformee_entry = beamforming_info->beamformee_entry[idx];
+	else
+		return;
+
+	if (dm->rf_type == RF_1T1R)
+		return;
+
+	for (i = RF_PATH_A; i < RF_PATH_B; i++) {
+		odm_set_rf_reg(dm, (enum rf_path)i, rf_welut_jaguar, 0x80000, 0x1);
+		/*RF mode table write enable*/
+	}
+
+	if (beamforming_info->beamformee_su_cnt > 0 || beamforming_info->beamformee_mu_cnt > 0) {
+		for (i = RF_PATH_A; i < RF_PATH_B; i++) {
+			odm_set_rf_reg(dm, (enum rf_path)i, rf_mode_table_addr, 0xfffff, 0x18000);
+			/*Select RX mode*/
+			odm_set_rf_reg(dm, (enum rf_path)i, rf_mode_table_data0, 0xfffff, 0xBE77F);
+			/*Set Table data*/
+			odm_set_rf_reg(dm, (enum rf_path)i, rf_mode_table_data1, 0xfffff, 0x226BF);
+			/*@Enable TXIQGEN in RX mode*/
+		}
+		odm_set_rf_reg(dm, RF_PATH_A, rf_mode_table_data1, 0xfffff, 0xE26BF);
+		/*@Enable TXIQGEN in RX mode*/
+	}
+
+	for (i = RF_PATH_A; i < RF_PATH_B; i++) {
+		odm_set_rf_reg(dm, (enum rf_path)i, rf_welut_jaguar, 0x80000, 0x0);
+		/*RF mode table write disable*/
+	}
+
+	if (beamforming_info->beamformee_su_cnt > 0) {
+		/*@for 8814 19ac(idx 1), 19b4(idx 0), different Tx ant setting*/
+		odm_set_bb_reg(dm, REG_BB_TXBF_ANT_SET_BF1_8822B, BIT(28) | BIT29, 0x2);			/*@enable BB TxBF ant mapping register*/
+
+		if (idx == 0) {
+			/*Nsts = 2	AB*/
+			odm_set_bb_reg(dm, REG_BB_TXBF_ANT_SET_BF0_8822B, 0xffff, 0x0433);
+			odm_set_bb_reg(dm, REG_BB_TX_PATH_SEL_1_8822B, 0xfff00000, 0x043);
+			/*odm_set_bb_reg(dm, REG_BB_TX_PATH_SEL_2, MASKLWORD, 0x430);*/
+
+		} else {/*@IDX =1*/
+			odm_set_bb_reg(dm, REG_BB_TXBF_ANT_SET_BF1_8822B, 0xffff, 0x0433);
+			odm_set_bb_reg(dm, REG_BB_TX_PATH_SEL_1_8822B, 0xfff00000, 0x043);
+			/*odm_set_bb_reg(dm, REG_BB_TX_PATH_SEL_2, MASKLWORD, 0x430;*/
+		}
+	} else {
+		odm_set_bb_reg(dm, REG_BB_TX_PATH_SEL_1_8822B, 0xfff00000, 0x1); /*@1SS by path-A*/
+		odm_set_bb_reg(dm, REG_BB_TX_PATH_SEL_2_8822B, MASKLWORD, 0x430); /*@2SS by path-A,B*/
+	}
+
+	if (beamforming_info->beamformee_mu_cnt > 0) {
+		/*@MU STAs share the common setting*/
+		odm_set_bb_reg(dm, REG_BB_TXBF_ANT_SET_BF1_8822B, BIT(31), 1);
+		odm_set_bb_reg(dm, REG_BB_TXBF_ANT_SET_BF1_8822B, 0xffff, 0x0433);
+		odm_set_bb_reg(dm, REG_BB_TX_PATH_SEL_1_8822B, 0xfff00000, 0x043);
+	}
+#endif
+}
+#if 0
+void
+hal_txbf_8822b_download_ndpa(
+	void			*adapter,
+	u8				idx
+)
+{
+	u8			u1b_tmp = 0, tmp_reg422 = 0;
+	u8			bcn_valid_reg = 0, count = 0, dl_bcn_count = 0;
+	u16			head_page = 0x7FE;
+	boolean			is_send_beacon = false;
+	HAL_DATA_TYPE	*hal_data = GET_HAL_DATA(adapter);
+	u16			tx_page_bndy = LAST_ENTRY_OF_TX_PKT_BUFFER_8814A; /*@default reseved 1 page for the IC type which is undefined.*/
+	struct _RT_BEAMFORMING_INFO	*beam_info = GET_BEAMFORM_INFO(adapter);
+	struct _RT_BEAMFORMEE_ENTRY	*p_beam_entry = beam_info->beamformee_entry + idx;
+
+	hal_data->is_fw_dw_rsvd_page_in_progress = true;
+	phydm_get_hal_def_var_handler_interface(dm, HAL_DEF_TX_PAGE_BOUNDARY, (u16 *)&tx_page_bndy);
+
+	/*Set REG_CR bit 8. DMA beacon by SW.*/
+	u1b_tmp = platform_efio_read_1byte(adapter, REG_CR_8814A + 1);
+	platform_efio_write_1byte(adapter,  REG_CR_8814A + 1, (u1b_tmp | BIT(0)));
+
+
+	/*Set FWHW_TXQ_CTRL 0x422[6]=0 to tell Hw the packet is not a real beacon frame.*/
+	tmp_reg422 = platform_efio_read_1byte(adapter, REG_FWHW_TXQ_CTRL_8814A + 2);
+	platform_efio_write_1byte(adapter, REG_FWHW_TXQ_CTRL_8814A + 2,  tmp_reg422 & (~BIT(6)));
+
+	if (tmp_reg422 & BIT(6)) {
+		RT_TRACE(COMP_INIT, DBG_LOUD, ("SetBeamformDownloadNDPA_8814A(): There is an adapter is sending beacon.\n"));
+		is_send_beacon = true;
+	}
+
+	/*@0x204[11:0]	Beacon Head for TXDMA*/
+	platform_efio_write_2byte(adapter, REG_FIFOPAGE_CTRL_2_8814A, head_page);
+
+	do {
+		/*@Clear beacon valid check bit.*/
+		bcn_valid_reg = platform_efio_read_1byte(adapter, REG_FIFOPAGE_CTRL_2_8814A + 1);
+		platform_efio_write_1byte(adapter, REG_FIFOPAGE_CTRL_2_8814A + 1, (bcn_valid_reg | BIT(7)));
+
+		/*@download NDPA rsvd page.*/
+		if (p_beam_entry->beamform_entry_cap & BEAMFORMER_CAP_VHT_SU)
+			beamforming_send_vht_ndpa_packet(dm, p_beam_entry->mac_addr, p_beam_entry->AID, p_beam_entry->sound_bw, BEACON_QUEUE);
+		else
+			beamforming_send_ht_ndpa_packet(dm, p_beam_entry->mac_addr, p_beam_entry->sound_bw, BEACON_QUEUE);
+
+		/*@check rsvd page download OK.*/
+		bcn_valid_reg = platform_efio_read_1byte(adapter, REG_FIFOPAGE_CTRL_2_8814A + 1);
+		count = 0;
+		while (!(bcn_valid_reg & BIT(7)) && count < 20) {
+			count++;
+			delay_us(10);
+			bcn_valid_reg = platform_efio_read_1byte(adapter, REG_FIFOPAGE_CTRL_2_8814A + 2);
+		}
+		dl_bcn_count++;
+	} while (!(bcn_valid_reg & BIT(7)) && dl_bcn_count < 5);
+
+	if (!(bcn_valid_reg & BIT(0)))
+		RT_DISP(FBEAM, FBEAM_ERROR, ("%s Download RSVD page failed!\n", __func__));
+
+	/*@0x204[11:0]	Beacon Head for TXDMA*/
+	platform_efio_write_2byte(adapter, REG_FIFOPAGE_CTRL_2_8814A, tx_page_bndy);
+
+	/*To make sure that if there exists an adapter which would like to send beacon.*/
+	/*@If exists, the origianl value of 0x422[6] will be 1, we should check this to*/
+	/*prevent from setting 0x422[6] to 0 after download reserved page, or it will cause */
+	/*the beacon cannot be sent by HW.*/
+	/*@2010.06.23. Added by tynli.*/
+	if (is_send_beacon)
+		platform_efio_write_1byte(adapter, REG_FWHW_TXQ_CTRL_8814A + 2, tmp_reg422);
+
+	/*@Do not enable HW DMA BCN or it will cause Pcie interface hang by timing issue. 2011.11.24. by tynli.*/
+	/*@Clear CR[8] or beacon packet will not be send to TxBuf anymore.*/
+	u1b_tmp = platform_efio_read_1byte(adapter, REG_CR_8814A + 1);
+	platform_efio_write_1byte(adapter, REG_CR_8814A + 1, (u1b_tmp & (~BIT(0))));
+
+	p_beam_entry->beamform_entry_state = BEAMFORMING_ENTRY_STATE_PROGRESSED;
+
+	hal_data->is_fw_dw_rsvd_page_in_progress = false;
+}
+
+void
+hal_txbf_8822b_fw_txbf_cmd(
+	void	*adapter
+)
+{
+	u8	idx, period = 0;
+	u8	PageNum0 = 0xFF, PageNum1 = 0xFF;
+	u8	u1_tx_bf_parm[3] = {0};
+
+	PMGNT_INFO				mgnt_info = &(adapter->MgntInfo);
+	struct _RT_BEAMFORMING_INFO	*beam_info = GET_BEAMFORM_INFO(adapter);
+
+	for (idx = 0; idx < BEAMFORMEE_ENTRY_NUM; idx++) {
+		if (beam_info->beamformee_entry[idx].is_used && beam_info->beamformee_entry[idx].beamform_entry_state == BEAMFORMING_ENTRY_STATE_PROGRESSED) {
+			if (beam_info->beamformee_entry[idx].is_sound) {
+				PageNum0 = 0xFE;
+				PageNum1 = 0x07;
+				period = (u8)(beam_info->beamformee_entry[idx].sound_period);
+			} else if (PageNum0 == 0xFF) {
+				PageNum0 = 0xFF; /*stop sounding*/
+				PageNum1 = 0x0F;
+			}
+		}
+	}
+
+	u1_tx_bf_parm[0] = PageNum0;
+	u1_tx_bf_parm[1] = PageNum1;
+	u1_tx_bf_parm[2] = period;
+	fill_h2c_cmd(adapter, PHYDM_H2C_TXBF, 3, u1_tx_bf_parm);
+
+	RT_DISP(FBEAM, FBEAM_FUN, ("@%s End, PageNum0 = 0x%x, PageNum1 = 0x%x period = %d", __func__, PageNum0, PageNum1, period));
+}
+#endif
+
+#if 0
+void
+hal_txbf_8822b_init(
+	void			*dm_void
+)
+{
+	struct dm_struct	*dm = (struct dm_struct *)dm_void;
+	u8		u1b_tmp;
+	struct _RT_BEAMFORMING_INFO		*beamforming_info = &dm->beamforming_info;
+	void				*adapter = dm->adapter;
+
+	odm_set_bb_reg(dm, R_0x14c0, BIT(16), 1); /*@Enable P1 aggr new packet according to P0 transfer time*/
+	odm_set_bb_reg(dm, R_0x14c0, BIT(15) | BIT14 | BIT13 | BIT12, 10); /*@MU Retry Limit*/
+	odm_set_bb_reg(dm, R_0x14c0, BIT(7), 0); /*@Disable Tx MU-MIMO until sounding done*/
+	odm_set_bb_reg(dm, R_0x14c0, 0x3F, 0); /* @Clear validity of MU STAs */
+	odm_write_1byte(dm, 0x167c, 0x70); /*@MU-MIMO Option as default value*/
+	odm_write_2byte(dm, 0x1680, 0); /*@MU-MIMO Control as default value*/
+
+	/* Set MU NDPA rate & BW source */
+	/* @0x42C[30] = 1 (0: from Tx desc, 1: from 0x45F) */
+	u1b_tmp = odm_read_1byte(dm, 0x42C);
+	odm_write_1byte(dm, REG_TXBF_CTRL_8822B, (u1b_tmp | BIT(6)));
+	/* @0x45F[7:0] = 0x10 (rate=OFDM_6M, BW20) */
+	odm_write_1byte(dm, REG_NDPA_OPT_CTRL_8822B, 0x10);
+
+	/*Temp Settings*/
+	odm_set_bb_reg(dm, R_0x6dc, 0x3F000000, 4); /*STA2's CSI rate is fixed at 6M*/
+	odm_set_bb_reg(dm, R_0x1c94, MASKDWORD, 0xAFFFAFFF); /*@Grouping bitmap parameters*/
+
+	/* @Init HW variable */
+	beamforming_info->reg_mu_tx_ctrl = odm_read_4byte(dm, 0x14c0);
+
+	if (dm->rf_type == RF_2T2R) { /*@2T2R*/
+		PHYDM_DBG(dm, DBG_TXBF, "%s: rf_type is 2T2R\n", __func__);
+		config_phydm_trx_mode_8822b(dm, (enum bb_path)3, (enum bb_path)3, true);/*Tx2path*/
+	}
+
+#if (OMNIPEEK_SNIFFER_ENABLED == 1)
+	/* @Config HW to receive packet on the user position from registry for sniffer mode. */
+	/* odm_set_bb_reg(dm, R_0xb00, BIT(9), 1);*/ /* For A-cut only. RegB00[9] = 1 (enable PMAC Rx) */
+	odm_set_bb_reg(dm, R_0xb54, BIT(30), 1); /* RegB54[30] = 1 (force user position) */
+	odm_set_bb_reg(dm, R_0xb54, (BIT(29) | BIT28), adapter->MgntInfo.sniff_user_position); /* RegB54[29:28] = user position (0~3) */
+	PHYDM_DBG(dm, DBG_TXBF,
+		  "Set adapter->MgntInfo.sniff_user_position=%#X\n",
+		  adapter->MgntInfo.sniff_user_position);
+#endif
+}
+#endif
+
+void hal_txbf_8822b_enter(
+	void *dm_void,
+	u8 bfer_bfee_idx)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	u8 i = 0;
+	u8 bfer_idx = (bfer_bfee_idx & 0xF0) >> 4;
+	u8 bfee_idx = (bfer_bfee_idx & 0xF);
+	u16 csi_param = 0;
+	struct _RT_BEAMFORMING_INFO *beamforming_info = &dm->beamforming_info;
+	struct _RT_BEAMFORMEE_ENTRY *p_beamformee_entry;
+	struct _RT_BEAMFORMER_ENTRY *beamformer_entry;
+	u16 value16, sta_id = 0;
+	u8 nc_index = 0, nr_index = 0, grouping = 0, codebookinfo = 0, coefficientsize = 0;
+	u32 gid_valid, user_position_l, user_position_h;
+	u32 mu_reg[6] = {0x1684, 0x1686, 0x1688, 0x168a, 0x168c, 0x168e};
+	u8 u1b_tmp;
+	u32 u4b_tmp;
+
+	RT_DISP(FBEAM, FBEAM_FUN, ("%s: bfer_bfee_idx=%d, bfer_idx=%d, bfee_idx=%d\n", __func__, bfer_bfee_idx, bfer_idx, bfee_idx));
+
+	/*************SU BFer Entry Init*************/
+	if (beamforming_info->beamformer_su_cnt > 0 && bfer_idx < BEAMFORMER_ENTRY_NUM) {
+		beamformer_entry = &beamforming_info->beamformer_entry[bfer_idx];
+		beamformer_entry->is_mu_ap = false;
+		/*Sounding protocol control*/
+		odm_write_1byte(dm, REG_SND_PTCL_CTRL_8822B, 0xDB);
+
+		for (i = 0; i < MAX_BEAMFORMER_SU; i++) {
+			if ((beamforming_info->beamformer_su_reg_maping & BIT(i)) == 0) {
+				beamforming_info->beamformer_su_reg_maping |= BIT(i);
+				beamformer_entry->su_reg_index = i;
+				break;
+			}
+		}
+
+		/*@MAC address/Partial AID of Beamformer*/
+		if (beamformer_entry->su_reg_index == 0) {
+			for (i = 0; i < 6; i++)
+				odm_write_1byte(dm, (REG_ASSOCIATED_BFMER0_INFO_8822B + i), beamformer_entry->mac_addr[i]);
+		} else {
+			for (i = 0; i < 6; i++)
+				odm_write_1byte(dm, (REG_ASSOCIATED_BFMER1_INFO_8822B + i), beamformer_entry->mac_addr[i]);
+		}
+
+		/*@CSI report parameters of Beamformer*/
+		nc_index = hal_txbf_8822b_get_nrx(dm); /*@for 8814A nrx = 3(4 ant), min=0(1 ant)*/
+		nr_index = beamformer_entry->num_of_sounding_dim; /*@0x718[7] = 1 use Nsts, 0x718[7] = 0 use reg setting. as Bfee, we use Nsts, so nr_index don't care*/
+
+		grouping = 0;
+
+		/*@for ac = 1, for n = 3*/
+		if (beamformer_entry->beamform_entry_cap & BEAMFORMEE_CAP_VHT_SU)
+			codebookinfo = 1;
+		else if (beamformer_entry->beamform_entry_cap & BEAMFORMEE_CAP_HT_EXPLICIT)
+			codebookinfo = 3;
+
+		coefficientsize = 3;
+
+		csi_param = (u16)((coefficientsize << 10) | (codebookinfo << 8) | (grouping << 6) | (nr_index << 3) | (nc_index));
+
+		if (bfer_idx == 0)
+			odm_write_2byte(dm, REG_TX_CSI_RPT_PARAM_BW20_8822B, csi_param);
+		else
+			odm_write_2byte(dm, REG_TX_CSI_RPT_PARAM_BW20_8822B + 2, csi_param);
+		/*ndp_rx_standby_timer, 8814 need > 0x56, suggest from Dvaid*/
+		odm_write_1byte(dm, REG_SND_PTCL_CTRL_8822B + 3, 0x70);
+	}
+
+	/*************SU BFee Entry Init*************/
+	if (beamforming_info->beamformee_su_cnt > 0 && bfee_idx < BEAMFORMEE_ENTRY_NUM) {
+		p_beamformee_entry = &beamforming_info->beamformee_entry[bfee_idx];
+		p_beamformee_entry->is_mu_sta = false;
+		hal_txbf_8822b_rf_mode(dm, beamforming_info, bfee_idx);
+
+		if (phydm_acting_determine(dm, phydm_acting_as_ibss))
+			sta_id = p_beamformee_entry->mac_id;
+		else
+			sta_id = p_beamformee_entry->p_aid;
+
+		for (i = 0; i < MAX_BEAMFORMEE_SU; i++) {
+			if ((beamforming_info->beamformee_su_reg_maping & BIT(i)) == 0) {
+				beamforming_info->beamformee_su_reg_maping |= BIT(i);
+				p_beamformee_entry->su_reg_index = i;
+				break;
+			}
+		}
+
+		/*P_AID of Beamformee & enable NDPA transmission & enable NDPA interrupt*/
+		if (p_beamformee_entry->su_reg_index == 0) {
+			odm_write_2byte(dm, REG_TXBF_CTRL_8822B, sta_id);
+			odm_write_1byte(dm, REG_TXBF_CTRL_8822B + 3, odm_read_1byte(dm, REG_TXBF_CTRL_8822B + 3) | BIT(4) | BIT(6) | BIT(7));
+		} else
+			odm_write_2byte(dm, REG_TXBF_CTRL_8822B + 2, sta_id | BIT(14) | BIT(15) | BIT(12));
+
+		/*@CSI report parameters of Beamformee*/
+		if (p_beamformee_entry->su_reg_index == 0) {
+			/*@Get BIT24 & BIT25*/
+			u8 tmp = odm_read_1byte(dm, REG_ASSOCIATED_BFMEE_SEL_8822B + 3) & 0x3;
+
+			odm_write_1byte(dm, REG_ASSOCIATED_BFMEE_SEL_8822B + 3, tmp | 0x60);
+			odm_write_2byte(dm, REG_ASSOCIATED_BFMEE_SEL_8822B, sta_id | BIT(9));
+		} else
+			odm_write_2byte(dm, REG_ASSOCIATED_BFMEE_SEL_8822B + 2, sta_id | 0xE200); /*Set BIT25*/
+
+		phydm_beamforming_notify(dm);
+	}
+
+	/*************MU BFer Entry Init*************/
+	if (beamforming_info->beamformer_mu_cnt > 0 && bfer_idx < BEAMFORMER_ENTRY_NUM) {
+		beamformer_entry = &beamforming_info->beamformer_entry[bfer_idx];
+		beamforming_info->mu_ap_index = bfer_idx;
+		beamformer_entry->is_mu_ap = true;
+		for (i = 0; i < 8; i++)
+			beamformer_entry->gid_valid[i] = 0;
+		for (i = 0; i < 16; i++)
+			beamformer_entry->user_position[i] = 0;
+
+		/*Sounding protocol control*/
+		odm_write_1byte(dm, REG_SND_PTCL_CTRL_8822B, 0xDB);
+
+		/* @MAC address */
+		for (i = 0; i < 6; i++)
+			odm_write_1byte(dm, (REG_ASSOCIATED_BFMER0_INFO_8822B + i), beamformer_entry->mac_addr[i]);
+
+		/* Set partial AID */
+		odm_write_2byte(dm, (REG_ASSOCIATED_BFMER0_INFO_8822B + 6), beamformer_entry->p_aid);
+
+		/* @Fill our AID to 0x1680[11:0] and [13:12] = 2b'00, BF report segment select to 3895 bytes*/
+		u1b_tmp = odm_read_1byte(dm, 0x1680);
+		u1b_tmp = (beamformer_entry->p_aid) & 0xFFF;
+		odm_write_1byte(dm, 0x1680, u1b_tmp);
+
+		/* Set 80us for leaving ndp_rx_standby_state */
+		odm_write_1byte(dm, 0x71B, 0x50);
+
+		/* Set 0x6A0[14] = 1 to accept action_no_ack */
+		u1b_tmp = odm_read_1byte(dm, REG_RXFLTMAP0_8822B + 1);
+		u1b_tmp |= 0x40;
+		odm_write_1byte(dm, REG_RXFLTMAP0_8822B + 1, u1b_tmp);
+		/* Set 0x6A2[5:4] = 1 to NDPA and BF report poll */
+		u1b_tmp = odm_read_1byte(dm, REG_RXFLTMAP1_8822B);
+		u1b_tmp |= 0x30;
+		odm_write_1byte(dm, REG_RXFLTMAP1_8822B, u1b_tmp);
+
+		/*@CSI report parameters of Beamformer*/
+		nc_index = hal_txbf_8822b_get_nrx(dm); /* @Depend on RF type */
+		nr_index = 1; /*@0x718[7] = 1 use Nsts, 0x718[7] = 0 use reg setting. as Bfee, we use Nsts, so nr_index don't care*/
+		grouping = 0; /*no grouping*/
+		codebookinfo = 1; /*@7 bit for psi, 9 bit for phi*/
+		coefficientsize = 0; /*This is nothing really matter*/
+		csi_param = (u16)((coefficientsize << 10) | (codebookinfo << 8) | (grouping << 6) | (nr_index << 3) | (nc_index));
+		odm_write_2byte(dm, 0x6F4, csi_param);
+
+		/*@for B-cut*/
+		odm_set_bb_reg(dm, R_0x6a0, BIT(20), 0);
+		odm_set_bb_reg(dm, R_0x688, BIT(20), 0);
+	}
+
+	/*************MU BFee Entry Init*************/
+	if (beamforming_info->beamformee_mu_cnt > 0 && bfee_idx < BEAMFORMEE_ENTRY_NUM) {
+		p_beamformee_entry = &beamforming_info->beamformee_entry[bfee_idx];
+		p_beamformee_entry->is_mu_sta = true;
+		for (i = 0; i < MAX_BEAMFORMEE_MU; i++) {
+			if ((beamforming_info->beamformee_mu_reg_maping & BIT(i)) == 0) {
+				beamforming_info->beamformee_mu_reg_maping |= BIT(i);
+				p_beamformee_entry->mu_reg_index = i;
+				break;
+			}
+		}
+
+		if (p_beamformee_entry->mu_reg_index == 0xFF) {
+			/* There is no valid bit in beamformee_mu_reg_maping */
+			RT_DISP(FBEAM, FBEAM_FUN, ("%s: ERROR! There is no valid bit in beamformee_mu_reg_maping!\n", __func__));
+			return;
+		}
+
+		/*User position table*/
+		switch (p_beamformee_entry->mu_reg_index) {
+		case 0:
+			gid_valid = 0x7fe;
+			user_position_l = 0x111110;
+			user_position_h = 0x0;
+			break;
+		case 1:
+			gid_valid = 0x7f806;
+			user_position_l = 0x11000004;
+			user_position_h = 0x11;
+			break;
+		case 2:
+			gid_valid = 0x1f81818;
+			user_position_l = 0x400040;
+			user_position_h = 0x11100;
+			break;
+		case 3:
+			gid_valid = 0x1e186060;
+			user_position_l = 0x4000400;
+			user_position_h = 0x1100040;
+			break;
+		case 4:
+			gid_valid = 0x66618180;
+			user_position_l = 0x40004000;
+			user_position_h = 0x10040400;
+			break;
+		case 5:
+			gid_valid = 0x79860600;
+			user_position_l = 0x40000;
+			user_position_h = 0x4404004;
+			break;
+		}
+
+		for (i = 0; i < 8; i++) {
+			if (i < 4) {
+				p_beamformee_entry->gid_valid[i] = (u8)(gid_valid & 0xFF);
+				gid_valid = (gid_valid >> 8);
+			} else
+				p_beamformee_entry->gid_valid[i] = 0;
+		}
+		for (i = 0; i < 16; i++) {
+			if (i < 4)
+				p_beamformee_entry->user_position[i] = (u8)((user_position_l >> (i * 8)) & 0xFF);
+			else if (i < 8)
+				p_beamformee_entry->user_position[i] = (u8)((user_position_h >> ((i - 4) * 8)) & 0xFF);
+			else
+				p_beamformee_entry->user_position[i] = 0;
+		}
+
+		/*Sounding protocol control*/
+		odm_write_1byte(dm, REG_SND_PTCL_CTRL_8822B, 0xDB);
+
+		/*select MU STA table*/
+		beamforming_info->reg_mu_tx_ctrl &= ~(BIT(8) | BIT(9) | BIT(10));
+		beamforming_info->reg_mu_tx_ctrl |= (p_beamformee_entry->mu_reg_index << 8) & (BIT(8) | BIT(9) | BIT(10));
+		odm_write_4byte(dm, 0x14c0, beamforming_info->reg_mu_tx_ctrl);
+
+		odm_set_bb_reg(dm, R_0x14c4, MASKDWORD, 0); /*Reset gid_valid table*/
+		odm_set_bb_reg(dm, R_0x14c8, MASKDWORD, user_position_l);
+		odm_set_bb_reg(dm, R_0x14cc, MASKDWORD, user_position_h);
+
+		/*set validity of MU STAs*/
+		beamforming_info->reg_mu_tx_ctrl &= 0xFFFFFFC0;
+		beamforming_info->reg_mu_tx_ctrl |= beamforming_info->beamformee_mu_reg_maping & 0x3F;
+		odm_write_4byte(dm, 0x14c0, beamforming_info->reg_mu_tx_ctrl);
+
+		PHYDM_DBG(dm, DBG_TXBF,
+			  "@%s, reg_mu_tx_ctrl = 0x%x, user_position_l = 0x%x, user_position_h = 0x%x\n",
+			  __func__, beamforming_info->reg_mu_tx_ctrl,
+			  user_position_l, user_position_h);
+
+		value16 = odm_read_2byte(dm, mu_reg[p_beamformee_entry->mu_reg_index]);
+		value16 &= 0xFE00; /*@Clear PAID*/
+		value16 |= BIT(9); /*@Enable MU BFee*/
+		value16 |= p_beamformee_entry->p_aid;
+		odm_write_2byte(dm, mu_reg[p_beamformee_entry->mu_reg_index], value16);
+
+		/* @0x42C[30] = 1 (0: from Tx desc, 1: from 0x45F) */
+		u1b_tmp = odm_read_1byte(dm, REG_TXBF_CTRL_8822B + 3);
+		u1b_tmp |= 0xD0; /* Set bit 28, 30, 31 to 3b'111*/
+		odm_write_1byte(dm, REG_TXBF_CTRL_8822B + 3, u1b_tmp);
+		/* Set NDPA to 6M*/
+		odm_write_1byte(dm, REG_NDPA_RATE_8822B, 0x4);
+
+		u1b_tmp = odm_read_1byte(dm, REG_NDPA_OPT_CTRL_8822B);
+		u1b_tmp &= 0xFC; /* @Clear bit 0, 1*/
+		odm_write_1byte(dm, REG_NDPA_OPT_CTRL_8822B, u1b_tmp);
+
+		u4b_tmp = odm_read_4byte(dm, REG_SND_PTCL_CTRL_8822B);
+		u4b_tmp = ((u4b_tmp & 0xFF0000FF) | 0x020200); /* Set [23:8] to 0x0202*/
+		odm_write_4byte(dm, REG_SND_PTCL_CTRL_8822B, u4b_tmp);
+
+		/* Set 0x6A0[14] = 1 to accept action_no_ack */
+		u1b_tmp = odm_read_1byte(dm, REG_RXFLTMAP0_8822B + 1);
+		u1b_tmp |= 0x40;
+		odm_write_1byte(dm, REG_RXFLTMAP0_8822B + 1, u1b_tmp);
+		/* @End of MAC registers setting */
+
+		hal_txbf_8822b_rf_mode(dm, beamforming_info, bfee_idx);
+#if (SUPPORT_MU_BF == 1)
+		/*Special for plugfest*/
+		delay_ms(50); /* wait for 4-way handshake ending*/
+		send_sw_vht_gid_mgnt_frame(dm, p_beamformee_entry->mac_addr, bfee_idx);
+#endif
+
+		phydm_beamforming_notify(dm);
+#if 1
+		{
+			u32 ctrl_info_offset, index;
+			/*Set Ctrl Info*/
+			odm_write_2byte(dm, 0x140, 0x660);
+			ctrl_info_offset = 0x8000 + 32 * p_beamformee_entry->mac_id;
+			/*Reset Ctrl Info*/
+			for (index = 0; index < 8; index++)
+				odm_write_4byte(dm, ctrl_info_offset + index * 4, 0);
+
+			odm_write_4byte(dm, ctrl_info_offset, (p_beamformee_entry->mu_reg_index + 1) << 16);
+			odm_write_1byte(dm, 0x81, 0x80); /*RPTBUF ready*/
+
+			PHYDM_DBG(dm, DBG_TXBF,
+				  "@%s, mac_id = %d, ctrl_info_offset = 0x%x, mu_reg_index = %x\n",
+				  __func__, p_beamformee_entry->mac_id,
+				  ctrl_info_offset,
+				  p_beamformee_entry->mu_reg_index);
+		}
+#endif
+	}
+}
+
+void hal_txbf_8822b_leave(
+	void *dm_void,
+	u8 idx)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct _RT_BEAMFORMING_INFO *beamforming_info = &dm->beamforming_info;
+	struct _RT_BEAMFORMER_ENTRY *beamformer_entry;
+	struct _RT_BEAMFORMEE_ENTRY *p_beamformee_entry;
+	u32 mu_reg[6] = {0x1684, 0x1686, 0x1688, 0x168a, 0x168c, 0x168e};
+
+	if (idx < BEAMFORMER_ENTRY_NUM) {
+		beamformer_entry = &beamforming_info->beamformer_entry[idx];
+		p_beamformee_entry = &beamforming_info->beamformee_entry[idx];
+	} else
+		return;
+
+	/*@Clear P_AID of Beamformee*/
+	/*@Clear MAC address of Beamformer*/
+	/*@Clear Associated Bfmee Sel*/
+
+	if (beamformer_entry->beamform_entry_cap == BEAMFORMING_CAP_NONE) {
+		odm_write_1byte(dm, REG_SND_PTCL_CTRL_8822B, 0xD8);
+		if (beamformer_entry->is_mu_ap == 0) { /*SU BFer */
+			if (beamformer_entry->su_reg_index == 0) {
+				odm_write_4byte(dm, REG_ASSOCIATED_BFMER0_INFO_8822B, 0);
+				odm_write_2byte(dm, REG_ASSOCIATED_BFMER0_INFO_8822B + 4, 0);
+				odm_write_2byte(dm, REG_TX_CSI_RPT_PARAM_BW20_8822B, 0);
+			} else {
+				odm_write_4byte(dm, REG_ASSOCIATED_BFMER1_INFO_8822B, 0);
+				odm_write_2byte(dm, REG_ASSOCIATED_BFMER1_INFO_8822B + 4, 0);
+				odm_write_2byte(dm, REG_TX_CSI_RPT_PARAM_BW20_8822B + 2, 0);
+			}
+			beamforming_info->beamformer_su_reg_maping &= ~(BIT(beamformer_entry->su_reg_index));
+			beamformer_entry->su_reg_index = 0xFF;
+		} else { /*@MU BFer */
+			/*set validity of MU STA0 and MU STA1*/
+			beamforming_info->reg_mu_tx_ctrl &= 0xFFFFFFC0;
+			odm_write_4byte(dm, 0x14c0, beamforming_info->reg_mu_tx_ctrl);
+
+			odm_memory_set(dm, beamformer_entry->gid_valid, 0, 8);
+			odm_memory_set(dm, beamformer_entry->user_position, 0, 16);
+			beamformer_entry->is_mu_ap = false;
+		}
+	}
+
+	if (p_beamformee_entry->beamform_entry_cap == BEAMFORMING_CAP_NONE) {
+		hal_txbf_8822b_rf_mode(dm, beamforming_info, idx);
+		if (p_beamformee_entry->is_mu_sta == 0) { /*SU BFee*/
+			if (p_beamformee_entry->su_reg_index == 0) {
+				odm_write_2byte(dm, REG_TXBF_CTRL_8822B, 0x0);
+				odm_write_1byte(dm, REG_TXBF_CTRL_8822B + 3, odm_read_1byte(dm, REG_TXBF_CTRL_8822B + 3) | BIT(4) | BIT(6) | BIT(7));
+				odm_write_2byte(dm, REG_ASSOCIATED_BFMEE_SEL_8822B, 0);
+			} else {
+				odm_write_2byte(dm, REG_TXBF_CTRL_8822B + 2, 0x0 | BIT(14) | BIT(15) | BIT(12));
+
+				odm_write_2byte(dm, REG_ASSOCIATED_BFMEE_SEL_8822B + 2,
+						odm_read_2byte(dm, REG_ASSOCIATED_BFMEE_SEL_8822B + 2) & 0x60);
+			}
+			beamforming_info->beamformee_su_reg_maping &= ~(BIT(p_beamformee_entry->su_reg_index));
+			p_beamformee_entry->su_reg_index = 0xFF;
+		} else { /*@MU BFee */
+			/*@Disable sending NDPA & BF-rpt-poll to this BFee*/
+			odm_write_2byte(dm, mu_reg[p_beamformee_entry->mu_reg_index], 0);
+			/*set validity of MU STA*/
+			beamforming_info->reg_mu_tx_ctrl &= ~(BIT(p_beamformee_entry->mu_reg_index));
+			odm_write_4byte(dm, 0x14c0, beamforming_info->reg_mu_tx_ctrl);
+
+			p_beamformee_entry->is_mu_sta = false;
+			beamforming_info->beamformee_mu_reg_maping &= ~(BIT(p_beamformee_entry->mu_reg_index));
+			p_beamformee_entry->mu_reg_index = 0xFF;
+		}
+	}
+}
+
+/***********SU & MU BFee Entry Only when souding done****************/
+void hal_txbf_8822b_status(
+	void *dm_void,
+	u8 beamform_idx)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	u16 beam_ctrl_val, tmp_val;
+	u32 beam_ctrl_reg;
+	struct _RT_BEAMFORMING_INFO *beamforming_info = &dm->beamforming_info;
+	struct _RT_BEAMFORMEE_ENTRY *beamform_entry;
+	boolean is_mu_sounding = beamforming_info->is_mu_sounding, is_bitmap_ready = false;
+	u16 bitmap;
+	u8 idx, gid, i;
+	u8 id1, id0;
+	u32 gid_valid[6] = {0};
+	u32 value32;
+	boolean is_sounding_success[6] = {false};
+
+	if (beamform_idx < BEAMFORMEE_ENTRY_NUM)
+		beamform_entry = &beamforming_info->beamformee_entry[beamform_idx];
+	else
+		return;
+
+	/*SU sounding done */
+	if (is_mu_sounding == false) {
+		if (phydm_acting_determine(dm, phydm_acting_as_ibss))
+			beam_ctrl_val = beamform_entry->mac_id;
+		else
+			beam_ctrl_val = beamform_entry->p_aid;
+
+		PHYDM_DBG(dm, DBG_TXBF,
+			  "@%s, beamform_entry.beamform_entry_state = %d",
+			  __func__, beamform_entry->beamform_entry_state);
+
+		if (beamform_entry->su_reg_index == 0)
+			beam_ctrl_reg = REG_TXBF_CTRL_8822B;
+		else {
+			beam_ctrl_reg = REG_TXBF_CTRL_8822B + 2;
+			beam_ctrl_val |= BIT(12) | BIT(14) | BIT(15);
+		}
+
+		if (beamform_entry->beamform_entry_state == BEAMFORMING_ENTRY_STATE_PROGRESSED) {
+			if (beamform_entry->sound_bw == CHANNEL_WIDTH_20)
+				beam_ctrl_val |= BIT(9);
+			else if (beamform_entry->sound_bw == CHANNEL_WIDTH_40)
+				beam_ctrl_val |= (BIT(9) | BIT(10));
+			else if (beamform_entry->sound_bw == CHANNEL_WIDTH_80)
+				beam_ctrl_val |= (BIT(9) | BIT(10) | BIT(11));
+		} else {
+			PHYDM_DBG(dm, DBG_TXBF, "@%s, Don't apply Vmatrix",
+				  __func__);
+			beam_ctrl_val &= ~(BIT(9) | BIT(10) | BIT(11));
+		}
+
+		odm_write_2byte(dm, beam_ctrl_reg, beam_ctrl_val);
+		/*@disable NDP packet use beamforming */
+		tmp_val = odm_read_2byte(dm, REG_TXBF_CTRL_8822B);
+		odm_write_2byte(dm, REG_TXBF_CTRL_8822B, tmp_val | BIT(15));
+	} else {
+		PHYDM_DBG(dm, DBG_TXBF, "@%s, MU Sounding Done\n", __func__);
+		/*@MU sounding done */
+		if (1) { /* @(beamform_entry->beamform_entry_state == BEAMFORMING_ENTRY_STATE_PROGRESSED) { */
+			PHYDM_DBG(dm, DBG_TXBF,
+				  "@%s, BEAMFORMING_ENTRY_STATE_PROGRESSED\n",
+				  __func__);
+
+			value32 = odm_get_bb_reg(dm, R_0x1684, MASKDWORD);
+			is_sounding_success[0] = (value32 & BIT(10)) ? 1 : 0;
+			is_sounding_success[1] = (value32 & BIT(26)) ? 1 : 0;
+			value32 = odm_get_bb_reg(dm, R_0x1688, MASKDWORD);
+			is_sounding_success[2] = (value32 & BIT(10)) ? 1 : 0;
+			is_sounding_success[3] = (value32 & BIT(26)) ? 1 : 0;
+			value32 = odm_get_bb_reg(dm, R_0x168c, MASKDWORD);
+			is_sounding_success[4] = (value32 & BIT(10)) ? 1 : 0;
+			is_sounding_success[5] = (value32 & BIT(26)) ? 1 : 0;
+
+			PHYDM_DBG(dm, DBG_TXBF,
+				  "@%s, is_sounding_success STA1:%d,  STA2:%d, STA3:%d, STA4:%d, STA5:%d, STA6:%d\n",
+				  __func__, is_sounding_success[0],
+				  is_sounding_success[1],
+				  is_sounding_success[2],
+				  is_sounding_success[3],
+				  is_sounding_success[4],
+				  is_sounding_success[5]);
+
+			value32 = odm_get_bb_reg(dm, R_0xf4c, 0xFFFF0000);
+			/* odm_set_bb_reg(dm, R_0x19e0, MASKHWORD, 0xFFFF);Let MAC ignore bitmap */
+
+			is_bitmap_ready = (boolean)((value32 & BIT(15)) >> 15);
+			bitmap = (u16)(value32 & 0x3FFF);
+
+			for (idx = 0; idx < 15; idx++) {
+				if (idx < 5) { /*@bit0~4*/
+					id0 = 0;
+					id1 = (u8)(idx + 1);
+				} else if (idx < 9) { /*@bit5~8*/
+					id0 = 1;
+					id1 = (u8)(idx - 3);
+				} else if (idx < 12) { /*@bit9~11*/
+					id0 = 2;
+					id1 = (u8)(idx - 6);
+				} else if (idx < 14) { /*@bit12~13*/
+					id0 = 3;
+					id1 = (u8)(idx - 8);
+				} else { /*@bit14*/
+					id0 = 4;
+					id1 = (u8)(idx - 9);
+				}
+				if (bitmap & BIT(idx)) {
+					/*Pair 1*/
+					gid = (idx << 1) + 1;
+					gid_valid[id0] |= (BIT(gid));
+					gid_valid[id1] |= (BIT(gid));
+					/*Pair 2*/
+					gid += 1;
+					gid_valid[id0] |= (BIT(gid));
+					gid_valid[id1] |= (BIT(gid));
+				} else {
+					/*Pair 1*/
+					gid = (idx << 1) + 1;
+					gid_valid[id0] &= ~(BIT(gid));
+					gid_valid[id1] &= ~(BIT(gid));
+					/*Pair 2*/
+					gid += 1;
+					gid_valid[id0] &= ~(BIT(gid));
+					gid_valid[id1] &= ~(BIT(gid));
+				}
+			}
+
+			for (i = 0; i < BEAMFORMEE_ENTRY_NUM; i++) {
+				beamform_entry = &beamforming_info->beamformee_entry[i];
+				if (beamform_entry->is_mu_sta && beamform_entry->mu_reg_index < 6) {
+					value32 = gid_valid[beamform_entry->mu_reg_index];
+					for (idx = 0; idx < 4; idx++) {
+						beamform_entry->gid_valid[idx] = (u8)(value32 & 0xFF);
+						value32 = (value32 >> 8);
+					}
+				}
+			}
+
+			for (idx = 0; idx < 6; idx++) {
+				beamforming_info->reg_mu_tx_ctrl &= ~(BIT(8) | BIT(9) | BIT(10));
+				beamforming_info->reg_mu_tx_ctrl |= ((idx << 8) & (BIT(8) | BIT(9) | BIT(10)));
+				odm_write_4byte(dm, 0x14c0, beamforming_info->reg_mu_tx_ctrl);
+				odm_set_mac_reg(dm, R_0x14c4, MASKDWORD, gid_valid[idx]); /*set MU STA gid valid table*/
+			}
+
+			/*@Enable TxMU PPDU*/
+			if (beamforming_info->dbg_disable_mu_tx == false)
+				beamforming_info->reg_mu_tx_ctrl |= BIT(7);
+			else
+				beamforming_info->reg_mu_tx_ctrl &= ~BIT(7);
+			odm_write_4byte(dm, 0x14c0, beamforming_info->reg_mu_tx_ctrl);
+		}
+	}
+}
+
+/*Only used for MU BFer Entry when get GID management frame (self is as MU STA)*/
+void hal_txbf_8822b_config_gtab(
+	void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct _RT_BEAMFORMING_INFO *beamforming_info = &dm->beamforming_info;
+	struct _RT_BEAMFORMER_ENTRY *beamformer_entry = NULL;
+	u32 gid_valid = 0, user_position_l = 0, user_position_h = 0, i;
+
+	if (beamforming_info->mu_ap_index < BEAMFORMER_ENTRY_NUM)
+		beamformer_entry = &beamforming_info->beamformer_entry[beamforming_info->mu_ap_index];
+	else
+		return;
+
+	PHYDM_DBG(dm, DBG_TXBF, "%s==>\n", __func__);
+
+	/*@For GID 0~31*/
+	for (i = 0; i < 4; i++)
+		gid_valid |= (beamformer_entry->gid_valid[i] << (i << 3));
+	for (i = 0; i < 8; i++) {
+		if (i < 4)
+			user_position_l |= (beamformer_entry->user_position[i] << (i << 3));
+		else
+			user_position_h |= (beamformer_entry->user_position[i] << ((i - 4) << 3));
+	}
+	/*select MU STA0 table*/
+	beamforming_info->reg_mu_tx_ctrl &= ~(BIT(8) | BIT(9) | BIT(10));
+	odm_write_4byte(dm, 0x14c0, beamforming_info->reg_mu_tx_ctrl);
+	odm_set_bb_reg(dm, R_0x14c4, MASKDWORD, gid_valid);
+	odm_set_bb_reg(dm, R_0x14c8, MASKDWORD, user_position_l);
+	odm_set_bb_reg(dm, R_0x14cc, MASKDWORD, user_position_h);
+
+	PHYDM_DBG(dm, DBG_TXBF,
+		  "%s: STA0: gid_valid = 0x%x, user_position_l = 0x%x, user_position_h = 0x%x\n",
+		  __func__, gid_valid, user_position_l, user_position_h);
+
+	gid_valid = 0;
+	user_position_l = 0;
+	user_position_h = 0;
+
+	/*@For GID 32~64*/
+	for (i = 4; i < 8; i++)
+		gid_valid |= (beamformer_entry->gid_valid[i] << ((i - 4) << 3));
+	for (i = 8; i < 16; i++) {
+		if (i < 4)
+			user_position_l |= (beamformer_entry->user_position[i] << ((i - 8) << 3));
+		else
+			user_position_h |= (beamformer_entry->user_position[i] << ((i - 12) << 3));
+	}
+	/*select MU STA1 table*/
+	beamforming_info->reg_mu_tx_ctrl &= ~(BIT(8) | BIT(9) | BIT(10));
+	beamforming_info->reg_mu_tx_ctrl |= BIT(8);
+	odm_write_4byte(dm, 0x14c0, beamforming_info->reg_mu_tx_ctrl);
+	odm_set_bb_reg(dm, R_0x14c4, MASKDWORD, gid_valid);
+	odm_set_bb_reg(dm, R_0x14c8, MASKDWORD, user_position_l);
+	odm_set_bb_reg(dm, R_0x14cc, MASKDWORD, user_position_h);
+
+	PHYDM_DBG(dm, DBG_TXBF,
+		  "%s: STA1: gid_valid = 0x%x, user_position_l = 0x%x, user_position_h = 0x%x\n",
+		  __func__, gid_valid, user_position_l, user_position_h);
+
+	/* Set validity of MU STA0 and MU STA1*/
+	beamforming_info->reg_mu_tx_ctrl &= 0xFFFFFFC0;
+	beamforming_info->reg_mu_tx_ctrl |= 0x3; /* STA0, STA1*/
+	odm_write_4byte(dm, 0x14c0, beamforming_info->reg_mu_tx_ctrl);
+}
+
+#if 0
+/*This function translate the bitmap to GTAB*/
+void
+haltxbf8822b_gtab_translation(
+	struct dm_struct			*dm
+)
+{
+	u8 idx, gid;
+	u8 id1, id0;
+	u32 gid_valid[6] = {0};
+	u32 user_position_lsb[6] = {0};
+	u32 user_position_msb[6] = {0};
+
+	for (idx = 0; idx < 15; idx++) {
+		if (idx < 5) {/*@bit0~4*/
+			id0 = 0;
+			id1 = (u8)(idx + 1);
+		} else if (idx < 9) { /*@bit5~8*/
+			id0 = 1;
+			id1 = (u8)(idx - 3);
+		} else if (idx < 12) { /*@bit9~11*/
+			id0 = 2;
+			id1 = (u8)(idx - 6);
+		} else if (idx < 14) { /*@bit12~13*/
+			id0 = 3;
+			id1 = (u8)(idx - 8);
+		} else { /*@bit14*/
+			id0 = 4;
+			id1 = (u8)(idx - 9);
+		}
+
+		/*Pair 1*/
+		gid = (idx << 1) + 1;
+		gid_valid[id0] |= (1 << gid);
+		gid_valid[id1] |= (1 << gid);
+		if (gid < 16) {
+			/*user_position_lsb[id0] |= (0 << (gid << 1));*/
+			user_position_lsb[id1] |= (1 << (gid << 1));
+		} else {
+			/*user_position_msb[id0] |= (0 << ((gid - 16) << 1));*/
+			user_position_msb[id1] |= (1 << ((gid - 16) << 1));
+		}
+
+		/*Pair 2*/
+		gid += 1;
+		gid_valid[id0] |= (1 << gid);
+		gid_valid[id1] |= (1 << gid);
+		if (gid < 16) {
+			user_position_lsb[id0] |= (1 << (gid << 1));
+			/*user_position_lsb[id1] |= (0 << (gid << 1));*/
+		} else {
+			user_position_msb[id0] |= (1 << ((gid - 16) << 1));
+			/*user_position_msb[id1] |= (0 << ((gid - 16) << 1));*/
+		}
+	}
+
+
+	for (idx = 0; idx < 6; idx++) {
+		/*@dbg_print("gid_valid[%d] = 0x%x\n", idx, gid_valid[idx]);
+		dbg_print("user_position[%d] = 0x%x   %x\n", idx, user_position_msb[idx], user_position_lsb[idx]);*/
+	}
+}
+#endif
+
+void hal_txbf_8822b_fw_txbf(
+	void *dm_void,
+	u8 idx)
+{
+#if 0
+	struct _RT_BEAMFORMING_INFO	*beam_info = GET_BEAMFORM_INFO(adapter);
+	struct _RT_BEAMFORMEE_ENTRY	*p_beam_entry = beam_info->beamformee_entry + idx;
+
+	if (p_beam_entry->beamform_entry_state == BEAMFORMING_ENTRY_STATE_PROGRESSING)
+		hal_txbf_8822b_download_ndpa(adapter, idx);
+
+	hal_txbf_8822b_fw_txbf_cmd(adapter);
+#endif
+}
+
+#endif
+
+#if (defined(CONFIG_BB_TXBF_API))
+/*this function is only used for BFer*/
+void phydm_8822btxbf_rfmode(void *dm_void, u8 su_bfee_cnt, u8 mu_bfee_cnt)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	u8 i;
+
+	if (dm->rf_type == RF_1T1R)
+		return;
+
+	if (su_bfee_cnt > 0 || mu_bfee_cnt > 0) {
+		for (i = RF_PATH_A; i <= RF_PATH_B; i++) {
+			odm_set_rf_reg(dm, (enum rf_path)i, RF_0xef, BIT(19), 0x1); /*RF mode table write enable*/
+			odm_set_rf_reg(dm, (enum rf_path)i, RF_0x33, 0xF, 3); /*Select RX mode*/
+			odm_set_rf_reg(dm, (enum rf_path)i, RF_0x3e, 0xfffff, 0x00036); /*Set Table data*/
+			odm_set_rf_reg(dm, (enum rf_path)i, RF_0x3f, 0xfffff, 0x5AFCE); /*Set Table data*/
+			odm_set_rf_reg(dm, (enum rf_path)i, RF_0xef, BIT(19), 0x0); /*RF mode table write disable*/
+		}
+	}
+
+	odm_set_bb_reg(dm, REG_BB_TXBF_ANT_SET_BF1_8822B, BIT(30), 1); /*@if Nsts > Nc, don't apply V matrix*/
+
+	if (su_bfee_cnt > 0 || mu_bfee_cnt > 0) {
+		/*@for 8814 19ac(idx 1), 19b4(idx 0), different Tx ant setting*/
+		odm_set_bb_reg(dm, REG_BB_TXBF_ANT_SET_BF1_8822B, BIT(28) | BIT29, 0x2); /*@enable BB TxBF ant mapping register*/
+		odm_set_bb_reg(dm, REG_BB_TXBF_ANT_SET_BF1_8822B, BIT(31), 1); /*@ignore user since 8822B only 2Tx*/
+
+		/*Nsts = 2	AB*/
+		odm_set_bb_reg(dm, REG_BB_TXBF_ANT_SET_BF1_8822B, 0xffff, 0x0433);
+		odm_set_bb_reg(dm, REG_BB_TX_PATH_SEL_1_8822B, 0xfff00000, 0x043);
+
+	} else {
+		odm_set_bb_reg(dm, REG_BB_TXBF_ANT_SET_BF1_8822B, BIT(28) | BIT29, 0x0); /*@enable BB TxBF ant mapping register*/
+		odm_set_bb_reg(dm, REG_BB_TXBF_ANT_SET_BF1_8822B, BIT(31), 0); /*@ignore user since 8822B only 2Tx*/
+
+		odm_set_bb_reg(dm, REG_BB_TX_PATH_SEL_1_8822B, 0xfff00000, 0x1); /*@1SS by path-A*/
+		odm_set_bb_reg(dm, REG_BB_TX_PATH_SEL_2_8822B, MASKLWORD, 0x430); /*@2SS by path-A,B*/
+	}
+}
+
+/*this function is for BFer bug workaround*/
+void phydm_8822b_sutxbfer_workaroud(void *dm_void, boolean enable_su_bfer,
+				    u8 nc, u8 nr, u8 ng, u8 CB, u8 BW,
+				    boolean is_vht)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+
+	if (enable_su_bfer) {
+		odm_set_bb_reg(dm, R_0x19f8, BIT(22) | BIT(21) | BIT(20), 0x1);
+		odm_set_bb_reg(dm, R_0x19f8, BIT(25) | BIT(24) | BIT(23), 0x0);
+		odm_set_bb_reg(dm, R_0x19f8, BIT(16), 0x1);
+
+		if (is_vht)
+			odm_set_bb_reg(dm, R_0x19f0, BIT(5) | BIT(4) | BIT(3) | BIT(2) | BIT(1) | BIT(0), 0x1f);
+		else
+			odm_set_bb_reg(dm, R_0x19f0, BIT(5) | BIT(4) | BIT(3) | BIT(2) | BIT(1) | BIT(0), 0x22);
+
+		odm_set_bb_reg(dm, R_0x19f0, BIT(7) | BIT(6), nc);
+		odm_set_bb_reg(dm, R_0x19f0, BIT(9) | BIT(8), nr);
+		odm_set_bb_reg(dm, R_0x19f0, BIT(11) | BIT(10), ng);
+		odm_set_bb_reg(dm, R_0x19f0, BIT(13) | BIT(12), CB);
+
+		odm_set_bb_reg(dm, R_0xb58, BIT(3) | BIT(2), BW);
+		odm_set_bb_reg(dm, R_0xb58, BIT(7) | BIT(6) | BIT(5) | BIT(4), 0x0);
+		odm_set_bb_reg(dm, R_0xb58, BIT(9) | BIT(8), BW);
+		odm_set_bb_reg(dm, R_0xb58, BIT(13) | BIT(12) | BIT(11) | BIT(10), 0x0);
+	} else {
+		odm_set_bb_reg(dm, R_0x19f8, BIT(16), 0x0);
+	}
+
+	PHYDM_DBG(dm, DBG_TXBF, "[%s] enable_su_bfer = %d, is_vht = %d\n",
+		  __func__, enable_su_bfer, is_vht);
+	PHYDM_DBG(dm, DBG_TXBF,
+		  "[%s] nc = %d, nr = %d, ng = %d, CB = %d, BW = %d\n",
+		  __func__, nc, nr, ng, CB, BW);
+}
+#endif
+#endif /* @(RTL8822B_SUPPORT == 1)*/
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/txbf/haltxbf8822b.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/txbf/haltxbf8822b.h
--- linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/txbf/haltxbf8822b.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/txbf/haltxbf8822b.h	2020-04-10 16:35:06.835660954 +0300
@@ -0,0 +1,78 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017  Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * The full GNU General Public License is included in this distribution in the
+ * file called LICENSE.
+ *
+ * Contact Information:
+ * wlanfae <wlanfae@realtek.com>
+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
+ * Hsinchu 300, Taiwan.
+ *
+ * Larry Finger <Larry.Finger@lwfinger.net>
+ *
+ *****************************************************************************/
+#ifndef __HAL_TXBF_8822B_H__
+#define __HAL_TXBF_8822B_H__
+
+#if (RTL8822B_SUPPORT == 1)
+#if (BEAMFORMING_SUPPORT == 1)
+
+void hal_txbf_8822b_enter(
+	void *dm_void,
+	u8 idx);
+
+void hal_txbf_8822b_leave(
+	void *dm_void,
+	u8 idx);
+
+void hal_txbf_8822b_status(
+	void *dm_void,
+	u8 beamform_idx);
+
+void hal_txbf_8822b_config_gtab(
+	void *dm_void);
+
+void hal_txbf_8822b_fw_txbf(
+	void *dm_void,
+	u8 idx);
+#else
+#define hal_txbf_8822b_enter(dm_void, idx)
+#define hal_txbf_8822b_leave(dm_void, idx)
+#define hal_txbf_8822b_status(dm_void, idx)
+#define hal_txbf_8822b_fw_txbf(dm_void, idx)
+#define hal_txbf_8822b_config_gtab(dm_void)
+
+#endif
+
+#if (defined(CONFIG_BB_TXBF_API))
+void phydm_8822btxbf_rfmode(void *dm_void, u8 su_bfee_cnt, u8 mu_bfee_cnt);
+
+void phydm_8822b_sutxbfer_workaroud(void *dm_void, boolean enable_su_bfer,
+				    u8 nc, u8 nr, u8 ng, u8 CB, u8 BW,
+				    boolean is_vht);
+
+#else
+#define phydm_8822btxbf_rfmode(dm_void, su_bfee_cnt, mu_bfee_cnt)
+#define phydm_8822b_sutxbfer_workaroud(dm_void, enable_su_bfer, nc, nr, ng, CB, BW, is_vht)
+#endif
+
+#else
+#define hal_txbf_8822b_enter(dm_void, idx)
+#define hal_txbf_8822b_leave(dm_void, idx)
+#define hal_txbf_8822b_status(dm_void, idx)
+#define hal_txbf_8822b_fw_txbf(dm_void, idx)
+#define hal_txbf_8822b_config_gtab(dm_void)
+
+#endif
+#endif
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/txbf/haltxbfinterface.c linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/txbf/haltxbfinterface.c
--- linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/txbf/haltxbfinterface.c	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/txbf/haltxbfinterface.c	2020-04-10 16:35:06.836661001 +0300
@@ -0,0 +1,1484 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2016 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+/*************************************************************
+ * Description:
+ *
+ * This file is for TXBF interface mechanism
+ *
+ ************************************************************/
+#include "mp_precomp.h"
+#include "../phydm_precomp.h"
+
+#if (BEAMFORMING_SUPPORT == 1)
+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
+void beamforming_gid_paid(
+	void *adapter,
+	PRT_TCB tcb)
+{
+	u8 RA[6] = {0};
+	u8 *p_header = GET_FRAME_OF_FIRST_FRAG(adapter, tcb);
+	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter));
+	struct dm_struct *dm = &hal_data->DM_OutSrc;
+	struct _RT_BEAMFORMING_INFO *beam_info = &(dm->beamforming_info);
+
+	if (((PADAPTER)adapter)->HardwareType < HARDWARE_TYPE_RTL8192EE)
+		return;
+	else if (IS_WIRELESS_MODE_N((PADAPTER)adapter) == false)
+		return;
+
+#if (SUPPORT_MU_BF == 1)
+	if (tcb->tx_bf_pkt_type == RT_BF_PKT_TYPE_BROADCAST_NDPA) { /* @MU NDPA */
+#else
+	if (0) {
+#endif
+		/* @Fill G_ID and P_AID */
+		tcb->G_ID = 63;
+		if (beam_info->first_mu_bfee_index < BEAMFORMEE_ENTRY_NUM) {
+			tcb->P_AID = beam_info->beamformee_entry[beam_info->first_mu_bfee_index].p_aid;
+			RT_DISP(FBEAM, FBEAM_FUN, ("[David]@%s End, G_ID=0x%X, P_AID=0x%X\n", __func__, tcb->G_ID, tcb->P_AID));
+		}
+	} else {
+		GET_80211_HDR_ADDRESS1(p_header, &RA);
+
+		/* VHT SU PPDU carrying one or more group addressed MPDUs or */
+		/* Transmitting a VHT NDP intended for multiple recipients */
+		if (MacAddr_isBcst(RA) || MacAddr_isMulticast(RA) || tcb->macId == MAC_ID_STATIC_FOR_BROADCAST_MULTICAST) {
+			tcb->G_ID = 63;
+			tcb->P_AID = 0;
+		} else if (ACTING_AS_AP(adapter)) {
+			u16 AID = (u16)(MacIdGetOwnerAssociatedClientAID(adapter, tcb->macId) & 0x1ff); /*@AID[0:8]*/
+
+			/*RT_DISP(FBEAM, FBEAM_FUN, ("@%s  tcb->mac_id=0x%X, AID=0x%X\n", __func__, tcb->mac_id, AID));*/
+			tcb->G_ID = 63;
+
+			if (AID == 0) /*@A PPDU sent by an AP to a non associated STA*/
+				tcb->P_AID = 0;
+			else { /*Sent by an AP and addressed to a STA associated with that AP*/
+				u16 BSSID = 0;
+				GET_80211_HDR_ADDRESS2(p_header, &RA);
+				BSSID = ((RA[5] & 0xf0) >> 4) ^ (RA[5] & 0xf); /*@BSSID[44:47] xor BSSID[40:43]*/
+				tcb->P_AID = (AID + BSSID * 32) & 0x1ff; /*@(dec(A) + dec(B)*32) mod 512*/
+			}
+		} else if (ACTING_AS_IBSS(((PADAPTER)adapter))) {
+			tcb->G_ID = 63;
+			/*P_AID for infrasturcture mode; MACID for ad-hoc mode. */
+			tcb->P_AID = tcb->macId;
+		} else if (MgntLinkStatusQuery(adapter)) { /*@Addressed to AP*/
+			tcb->G_ID = 0;
+			GET_80211_HDR_ADDRESS1(p_header, &RA);
+			tcb->P_AID = RA[5]; /*RA[39:47]*/
+			tcb->P_AID = (tcb->P_AID << 1) | (RA[4] >> 7);
+		} else {
+			tcb->G_ID = 63;
+			tcb->P_AID = 0;
+		}
+		/*RT_DISP(FBEAM, FBEAM_FUN, ("[David]@%s End, G_ID=0x%X, P_AID=0x%X\n", __func__, tcb->G_ID, tcb->P_AID));*/
+	}
+}
+
+enum rt_status
+beamforming_get_report_frame(
+	void *adapter,
+	PRT_RFD rfd,
+	POCTET_STRING p_pdu_os)
+{
+	HAL_DATA_TYPE *hal_data = GET_HAL_DATA((PADAPTER)adapter);
+	struct dm_struct *dm = &hal_data->DM_OutSrc;
+	struct _RT_BEAMFORMEE_ENTRY *beamform_entry = NULL;
+	u8 *p_mimo_ctrl_field, p_csi_matrix;
+	u8 idx, nc, nr, CH_W;
+	u16 csi_matrix_len = 0;
+
+	ACT_PKT_TYPE pkt_type = ACT_PKT_TYPE_UNKNOWN;
+
+	/* @Memory comparison to see if CSI report is the same with previous one */
+	beamform_entry = phydm_beamforming_get_bfee_entry_by_addr(dm, Frame_Addr2(*p_pdu_os), &idx);
+
+	if (beamform_entry == NULL) {
+		PHYDM_DBG(dm, DBG_TXBF, "%s: Cannot find entry by addr\n",
+			  __func__);
+		return RT_STATUS_FAILURE;
+	}
+
+	pkt_type = PacketGetActionFrameType(p_pdu_os);
+
+	/* @-@ Modified by David */
+	if (pkt_type == ACT_PKT_VHT_COMPRESSED_BEAMFORMING) {
+		p_mimo_ctrl_field = p_pdu_os->Octet + 26;
+		nc = ((*p_mimo_ctrl_field) & 0x7) + 1;
+		nr = (((*p_mimo_ctrl_field) & 0x38) >> 3) + 1;
+		CH_W = (((*p_mimo_ctrl_field) & 0xC0) >> 6);
+		/*p_csi_matrix = p_mimo_ctrl_field + 3 + nc;*/ /* 24+(1+1+3)+2  MAC header+(Category+ActionCode+MIMOControlField) +SNR(nc=2) */
+		csi_matrix_len = p_pdu_os->Length - 26 - 3 - nc;
+	} else if (pkt_type == ACT_PKT_HT_COMPRESSED_BEAMFORMING) {
+		p_mimo_ctrl_field = p_pdu_os->Octet + 26;
+		nc = ((*p_mimo_ctrl_field) & 0x3) + 1;
+		nr = (((*p_mimo_ctrl_field) & 0xC) >> 2) + 1;
+		CH_W = (((*p_mimo_ctrl_field) & 0x10) >> 4);
+		/*p_csi_matrix = p_mimo_ctrl_field + 6 + nr;*/ /* 24+(1+1+6)+2  MAC header+(Category+ActionCode+MIMOControlField) +SNR(nc=2) */
+		csi_matrix_len = p_pdu_os->Length - 26 - 6 - nr;
+	} else
+		return RT_STATUS_SUCCESS;
+
+	PHYDM_DBG(dm, DBG_TXBF,
+		  "[%s] idx=%d, pkt type=%d, nc=%d, nr=%d, CH_W=%d\n", __func__,
+		  idx, pkt_type, nc, nr, CH_W);
+
+	return RT_STATUS_SUCCESS;
+}
+
+void construct_ht_ndpa_packet(
+	// 2017/11 MH PHYDM compile. But why need to use windows maco?
+	// For all linux code, it should be useless?
+	//void				*adapter = dm->adapter;
+	ADAPTER * adapter,
+	//void		*adapter,
+	u8 *RA,
+	u8 *buffer,
+	u32 *p_length,
+	enum channel_width BW)
+{
+	u16 duration = 0;
+	PMGNT_INFO mgnt_info = &(((PADAPTER)adapter)->MgntInfo);
+	//PMGNT_INFO				mgnt_info = &((MGNT_INFO)(((PADAPTER)adapter)->MgntInfo));
+	OCTET_STRING p_ndpa_frame, action_content;
+	u8 action_hdr[4] = {ACT_CAT_VENDOR, 0x00, 0xe0, 0x4c};
+
+	PlatformZeroMemory(buffer, 32);
+
+	SET_80211_HDR_FRAME_CONTROL(buffer, 0);
+
+	SET_80211_HDR_ORDER(buffer, 1);
+	SET_80211_HDR_TYPE_AND_SUBTYPE(buffer, Type_Action_No_Ack);
+
+	SET_80211_HDR_ADDRESS1(buffer, RA);
+	SET_80211_HDR_ADDRESS2(buffer, ((PADAPTER)adapter)->CurrentAddress);
+	SET_80211_HDR_ADDRESS3(buffer, ((PMGNT_INFO)mgnt_info)->Bssid);
+
+	duration = 2 * a_SifsTime + 40;
+
+	if (BW == CHANNEL_WIDTH_40)
+		duration += 87;
+	else
+		duration += 180;
+
+	SET_80211_HDR_DURATION(buffer, duration);
+
+	/* @HT control field */
+	SET_HT_CTRL_CSI_STEERING(buffer + sMacHdrLng, 3);
+	SET_HT_CTRL_NDP_ANNOUNCEMENT(buffer + sMacHdrLng, 1);
+
+	FillOctetString(p_ndpa_frame, buffer, sMacHdrLng + sHTCLng);
+
+	FillOctetString(action_content, action_hdr, 4);
+	PacketAppendData(&p_ndpa_frame, action_content);
+
+	*p_length = 32;
+}
+
+boolean
+send_fw_ht_ndpa_packet(
+	void *dm_void,
+	u8 *RA,
+	enum channel_width BW)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	void *adapter = dm->adapter;
+	PRT_TCB tcb;
+	PRT_TX_LOCAL_BUFFER p_buf;
+	boolean ret = true;
+	u32 buf_len;
+	u8 *buf_addr;
+	u8 desc_len = 0, idx = 0, ndp_tx_rate;
+	void *p_def_adapter = GetDefaultAdapter(((PADAPTER)adapter));
+	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter));
+	struct _RT_BEAMFORMEE_ENTRY *beamform_entry = phydm_beamforming_get_bfee_entry_by_addr(dm, RA, &idx);
+
+	PHYDM_DBG(dm, DBG_TXBF, "[%s] Start!\n", __func__);
+
+	if (beamform_entry == NULL)
+		return false;
+
+	ndp_tx_rate = beamforming_get_htndp_tx_rate(dm, beamform_entry->comp_steering_num_of_bfer);
+	PHYDM_DBG(dm, DBG_TXBF, "[%s] ndp_tx_rate =%d\n", __func__,
+		  ndp_tx_rate);
+	PlatformAcquireSpinLock(adapter, RT_TX_SPINLOCK);
+
+	if (MgntGetFWBuffer(p_def_adapter, &tcb, &p_buf)) {
+#if (DEV_BUS_TYPE != RT_PCI_INTERFACE)
+		desc_len = ((PADAPTER)adapter)->HWDescHeadLength - hal_data->USBALLDummyLength;
+#endif
+		buf_addr = p_buf->Buffer.VirtualAddress + desc_len;
+
+		construct_ht_ndpa_packet(
+			adapter,
+			RA,
+			buf_addr,
+			&buf_len,
+			BW);
+
+		tcb->PacketLength = buf_len + desc_len;
+
+		tcb->bTxEnableSwCalcDur = true;
+
+		tcb->BWOfPacket = BW;
+
+		if (ACTING_AS_IBSS(((PADAPTER)adapter)) || ACTING_AS_AP(((PADAPTER)adapter)))
+			tcb->G_ID = 63;
+
+		tcb->P_AID = beamform_entry->p_aid;
+		tcb->DataRate = ndp_tx_rate; /*rate of NDP decide by nr*/
+
+		((PADAPTER)adapter)->HalFunc.CmdSendPacketHandler(((PADAPTER)adapter), tcb, p_buf, tcb->PacketLength, DESC_PACKET_TYPE_NORMAL, false);
+	} else
+		ret = false;
+
+	PlatformReleaseSpinLock(adapter, RT_TX_SPINLOCK);
+
+	if (ret)
+		RT_DISP_DATA(FBEAM, FBEAM_DATA, "", p_buf->Buffer.VirtualAddress, tcb->PacketLength);
+
+	return ret;
+}
+
+boolean
+send_sw_ht_ndpa_packet(
+	void *dm_void,
+	u8 *RA,
+	enum channel_width BW)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	void *adapter = dm->adapter;
+	PRT_TCB tcb;
+	PRT_TX_LOCAL_BUFFER p_buf;
+	boolean ret = true;
+	u8 idx = 0, ndp_tx_rate = 0;
+	struct _RT_BEAMFORMEE_ENTRY *beamform_entry = phydm_beamforming_get_bfee_entry_by_addr(dm, RA, &idx);
+
+	PHYDM_DBG(dm, DBG_TXBF, "[%s] Start!\n", __func__);
+
+	ndp_tx_rate = beamforming_get_htndp_tx_rate(dm, beamform_entry->comp_steering_num_of_bfer);
+	PHYDM_DBG(dm, DBG_TXBF, "[%s] ndp_tx_rate =%d\n", __func__,
+		  ndp_tx_rate);
+
+	PlatformAcquireSpinLock(adapter, RT_TX_SPINLOCK);
+
+	if (MgntGetBuffer(adapter, &tcb, &p_buf)) {
+		construct_ht_ndpa_packet(
+			adapter,
+			RA,
+			p_buf->Buffer.VirtualAddress,
+			&tcb->PacketLength,
+			BW);
+
+		tcb->bTxEnableSwCalcDur = true;
+
+		tcb->BWOfPacket = BW;
+
+		MgntSendPacket(adapter, tcb, p_buf, tcb->PacketLength, NORMAL_QUEUE, ndp_tx_rate);
+	} else
+		ret = false;
+
+	PlatformReleaseSpinLock(adapter, RT_TX_SPINLOCK);
+
+	if (ret)
+		RT_DISP_DATA(FBEAM, FBEAM_DATA, "", p_buf->Buffer.VirtualAddress, tcb->PacketLength);
+
+	return ret;
+}
+
+void construct_vht_ndpa_packet(
+	struct dm_struct *dm,
+	u8 *RA,
+	u16 AID,
+	u8 *buffer,
+	u32 *p_length,
+	enum channel_width BW)
+{
+	u16 duration = 0;
+	u8 sequence = 0;
+	u8 *p_ndpa_frame = buffer;
+	struct _RT_NDPA_STA_INFO sta_info;
+	// 2017/11 MH PHYDM compile. But why need to use windows maco?
+	// For all linux code, it should be useless?
+	//void				*adapter = dm->adapter;
+	ADAPTER * adapter = (PADAPTER)(dm->adapter);
+	u8 idx = 0;
+	struct _RT_BEAMFORMEE_ENTRY *beamform_entry = phydm_beamforming_get_bfee_entry_by_addr(dm, RA, &idx);
+	/* @Frame control. */
+	SET_80211_HDR_FRAME_CONTROL(p_ndpa_frame, 0);
+	SET_80211_HDR_TYPE_AND_SUBTYPE(p_ndpa_frame, Type_NDPA);
+
+	SET_80211_HDR_ADDRESS1(p_ndpa_frame, RA);
+	SET_80211_HDR_ADDRESS2(p_ndpa_frame, beamform_entry->my_mac_addr);
+
+	// 2017/11 MH PHYDM compile. But why need to use windows maco?
+	// For all linux code, it should be useless?
+	duration = 2 * a_SifsTime + 44;
+
+	if (BW == CHANNEL_WIDTH_80)
+		duration += 40;
+	else if (BW == CHANNEL_WIDTH_40)
+		duration += 87;
+	else
+		duration += 180;
+
+	SET_80211_HDR_DURATION(p_ndpa_frame, duration);
+
+	sequence = *(dm->sounding_seq) << 2;
+	odm_move_memory(dm, p_ndpa_frame + 16, &sequence, 1);
+
+	if (phydm_acting_determine(dm, phydm_acting_as_ibss) || phydm_acting_determine(dm, phydm_acting_as_ap) == false)
+		AID = 0;
+
+	sta_info.aid = AID;
+	sta_info.feedback_type = 0;
+	sta_info.nc_index = 0;
+
+	odm_move_memory(dm, p_ndpa_frame + 17, (u8 *)&sta_info, 2);
+
+	*p_length = 19;
+}
+
+boolean
+send_fw_vht_ndpa_packet(
+	void *dm_void,
+	u8 *RA,
+	u16 AID,
+	enum channel_width BW)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	void *adapter = dm->adapter;
+	PRT_TCB tcb;
+	PRT_TX_LOCAL_BUFFER p_buf;
+	boolean ret = true;
+	u32 buf_len;
+	u8 *buf_addr;
+	u8 desc_len = 0, idx = 0, ndp_tx_rate = 0;
+	void *p_def_adapter = GetDefaultAdapter(((PADAPTER)adapter));
+	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter));
+	struct _RT_BEAMFORMEE_ENTRY *beamform_entry = phydm_beamforming_get_bfee_entry_by_addr(dm, RA, &idx);
+
+	PHYDM_DBG(dm, DBG_TXBF, "[%s] Start!\n", __func__);
+
+	if (beamform_entry == NULL)
+		return false;
+
+	ndp_tx_rate = beamforming_get_vht_ndp_tx_rate(dm, beamform_entry->comp_steering_num_of_bfer);
+	PHYDM_DBG(dm, DBG_TXBF, "[%s] ndp_tx_rate =%d\n", __func__,
+		  ndp_tx_rate);
+
+	PlatformAcquireSpinLock(adapter, RT_TX_SPINLOCK);
+
+	if (MgntGetFWBuffer(p_def_adapter, &tcb, &p_buf)) {
+#if (DEV_BUS_TYPE != RT_PCI_INTERFACE)
+		desc_len = ((PADAPTER)adapter)->HWDescHeadLength - hal_data->USBALLDummyLength;
+#endif
+		buf_addr = p_buf->Buffer.VirtualAddress + desc_len;
+
+		construct_vht_ndpa_packet(
+			dm,
+			RA,
+			AID,
+			buf_addr,
+			&buf_len,
+			BW);
+
+		tcb->PacketLength = buf_len + desc_len;
+
+		tcb->bTxEnableSwCalcDur = true;
+
+		tcb->BWOfPacket = BW;
+
+		if (phydm_acting_determine(dm, phydm_acting_as_ibss) || phydm_acting_determine(dm, phydm_acting_as_ap))
+			tcb->G_ID = 63;
+
+		tcb->P_AID = beamform_entry->p_aid;
+		tcb->DataRate = ndp_tx_rate; /*@decide by nr*/
+
+		((PADAPTER)adapter)->HalFunc.CmdSendPacketHandler(adapter, tcb, p_buf, tcb->PacketLength, DESC_PACKET_TYPE_NORMAL, false);
+	} else
+		ret = false;
+
+	PlatformReleaseSpinLock(adapter, RT_TX_SPINLOCK);
+
+	PHYDM_DBG(dm, DBG_TXBF, "[%s] End, ret=%d\n", __func__, ret);
+
+	if (ret)
+		RT_DISP_DATA(FBEAM, FBEAM_DATA, "", p_buf->Buffer.VirtualAddress, tcb->PacketLength);
+
+	return ret;
+}
+
+boolean
+send_sw_vht_ndpa_packet(
+	void *dm_void,
+	u8 *RA,
+	u16 AID,
+	enum channel_width BW)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	void *adapter = dm->adapter;
+	PRT_TCB tcb;
+	PRT_TX_LOCAL_BUFFER p_buf;
+	boolean ret = true;
+	u8 idx = 0, ndp_tx_rate = 0;
+	struct _RT_BEAMFORMEE_ENTRY *beamform_entry = phydm_beamforming_get_bfee_entry_by_addr(dm, RA, &idx);
+
+	ndp_tx_rate = beamforming_get_vht_ndp_tx_rate(dm, beamform_entry->comp_steering_num_of_bfer);
+	PHYDM_DBG(dm, DBG_TXBF, "[%s] ndp_tx_rate =%d\n", __func__,
+		  ndp_tx_rate);
+
+	PlatformAcquireSpinLock(adapter, RT_TX_SPINLOCK);
+
+	if (MgntGetBuffer(adapter, &tcb, &p_buf)) {
+		construct_vht_ndpa_packet(
+			dm,
+			RA,
+			AID,
+			p_buf->Buffer.VirtualAddress,
+			&tcb->PacketLength,
+			BW);
+
+		tcb->bTxEnableSwCalcDur = true;
+		tcb->BWOfPacket = BW;
+
+		/*rate of NDP decide by nr*/
+		MgntSendPacket(adapter, tcb, p_buf, tcb->PacketLength, NORMAL_QUEUE, ndp_tx_rate);
+	} else
+		ret = false;
+
+	PlatformReleaseSpinLock(adapter, RT_TX_SPINLOCK);
+
+	if (ret)
+		RT_DISP_DATA(FBEAM, FBEAM_DATA, "", p_buf->Buffer.VirtualAddress, tcb->PacketLength);
+
+	return ret;
+}
+
+#ifdef SUPPORT_MU_BF
+#if (SUPPORT_MU_BF == 1)
+/*@
+ * Description: On VHT GID management frame by an MU beamformee.
+ *
+ * 2015.05.20. Created by tynli.
+ */
+enum rt_status
+beamforming_get_vht_gid_mgnt_frame(
+	void *adapter,
+	PRT_RFD rfd,
+	POCTET_STRING p_pdu_os)
+{
+	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter));
+	struct dm_struct *dm = &hal_data->DM_OutSrc;
+	enum rt_status rt_status = RT_STATUS_SUCCESS;
+	u8 *p_buffer = NULL;
+	u8 *p_raddr = NULL;
+	u8 mem_status[8] = {0}, user_pos[16] = {0};
+	u8 idx;
+	struct _RT_BEAMFORMING_INFO *beam_info = &(dm->beamforming_info);
+	struct _RT_BEAMFORMER_ENTRY *beamform_entry = &beam_info->beamformer_entry[beam_info->mu_ap_index];
+
+	PHYDM_DBG(dm, DBG_TXBF, "[%s] On VHT GID mgnt frame!\n", __func__);
+
+	/* @Check length*/
+	if (p_pdu_os->length < (FRAME_OFFSET_VHT_GID_MGNT_USER_POSITION_ARRAY + 16)) {
+		PHYDM_DBG(dm, DBG_TXBF, "%s: Invalid length (%d)\n", __func__,
+			  p_pdu_os->length);
+		return RT_STATUS_INVALID_LENGTH;
+	}
+
+	/* @Check RA*/
+	p_raddr = (u8 *)(p_pdu_os->Octet) + 4;
+	if (!eq_mac_addr(p_raddr, adapter->CurrentAddress)) {
+		PHYDM_DBG(dm, DBG_TXBF, "%s: Drop because of RA error.\n",
+			  __func__);
+		return RT_STATUS_PKT_DROP;
+	}
+
+	RT_DISP_DATA(FBEAM, FBEAM_DATA, "On VHT GID Mgnt Frame ==>:\n", p_pdu_os->Octet, p_pdu_os->length);
+
+	/*Parsing Membership status array*/
+	p_buffer = p_pdu_os->Octet + FRAME_OFFSET_VHT_GID_MGNT_MEMBERSHIP_STATUS_ARRAY;
+	for (idx = 0; idx < 8; idx++) {
+		mem_status[idx] = GET_VHT_GID_MGNT_INFO_MEMBERSHIP_STATUS(p_buffer + idx);
+		beamform_entry->gid_valid[idx] = GET_VHT_GID_MGNT_INFO_MEMBERSHIP_STATUS(p_buffer + idx);
+	}
+
+	RT_DISP_DATA(FBEAM, FBEAM_DATA, "mem_status: ", mem_status, 8);
+
+	/* Parsing User Position array*/
+	p_buffer = p_pdu_os->Octet + FRAME_OFFSET_VHT_GID_MGNT_USER_POSITION_ARRAY;
+	for (idx = 0; idx < 16; idx++) {
+		user_pos[idx] = GET_VHT_GID_MGNT_INFO_USER_POSITION(p_buffer + idx);
+		beamform_entry->user_position[idx] = GET_VHT_GID_MGNT_INFO_USER_POSITION(p_buffer + idx);
+	}
+
+	RT_DISP_DATA(FBEAM, FBEAM_DATA, "user_pos: ", user_pos, 16);
+
+	/* @Group ID detail printed*/
+	{
+		u8 i, j;
+		u8 tmp_val;
+		u16 tmp_val2;
+
+		for (i = 0; i < 8; i++) {
+			tmp_val = mem_status[i];
+			tmp_val2 = ((user_pos[i * 2 + 1] << 8) & 0xFF00) + (user_pos[i * 2] & 0xFF);
+			for (j = 0; j < 8; j++) {
+				if ((tmp_val >> j) & BIT(0)) {
+					PHYDM_DBG(dm, DBG_TXBF, "Use Group ID (%d), User Position (%d)\n",
+						  (i * 8 + j), (tmp_val2 >> 2 * j) & 0x3);
+				}
+			}
+		}
+	}
+
+	/* @Indicate GID frame to IHV service. */
+	{
+		u8 indibuffer[24] = {0};
+		u8 indioffset = 0;
+
+		PlatformMoveMemory(indibuffer + indioffset, beamform_entry->gid_valid, 8);
+		indioffset += 8;
+		PlatformMoveMemory(indibuffer + indioffset, beamform_entry->user_position, 16);
+		indioffset += 16;
+
+		PlatformIndicateCustomStatus(
+			adapter,
+			RT_CUSTOM_EVENT_VHT_RECV_GID_MGNT_FRAME,
+			RT_CUSTOM_INDI_TARGET_IHV,
+			indibuffer,
+			indioffset);
+	}
+
+	/* @Config HW GID table */
+	hal_com_txbf_config_gtab(dm);
+
+	return rt_status;
+}
+
+/*@
+ * Description: Construct VHT Group ID (GID) management frame.
+ *
+ * 2015.05.20. Created by tynli.
+ */
+void construct_vht_gid_mgnt_frame(
+	struct dm_struct *dm,
+	u8 *RA,
+	struct _RT_BEAMFORMEE_ENTRY *beamform_entry,
+	u8 *buffer,
+	u32 *p_length
+
+	)
+{
+	struct _RT_BEAMFORMING_INFO *beam_info = &(dm->beamforming_info);
+	void *adapter = beam_info->source_adapter;
+	OCTET_STRING os_ftm_frame, tmp;
+
+	FillOctetString(os_ftm_frame, buffer, 0);
+	*p_length = 0;
+
+	ConstructMaFrameHdr(
+		adapter,
+		RA,
+		ACT_CAT_VHT,
+		ACT_VHT_GROUPID_MANAGEMENT,
+		&os_ftm_frame);
+
+	/* @Membership status array*/
+	FillOctetString(tmp, beamform_entry->gid_valid, 8);
+	PacketAppendData(&os_ftm_frame, tmp);
+
+	/* User Position array*/
+	FillOctetString(tmp, beamform_entry->user_position, 16);
+	PacketAppendData(&os_ftm_frame, tmp);
+
+	*p_length = os_ftm_frame.length;
+
+	RT_DISP_DATA(FBEAM, FBEAM_DATA, "construct_vht_gid_mgnt_frame():\n", buffer, *p_length);
+}
+
+boolean
+send_sw_vht_gid_mgnt_frame(
+	void *dm_void,
+	u8 *RA,
+	u8 idx)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	PRT_TCB tcb;
+	PRT_TX_LOCAL_BUFFER p_buf;
+	boolean ret = true;
+	u8 data_rate = 0;
+	struct _RT_BEAMFORMING_INFO *beam_info = &(dm->beamforming_info);
+	struct _RT_BEAMFORMEE_ENTRY *beamform_entry = &beam_info->beamformee_entry[idx];
+	void *adapter = beam_info->source_adapter;
+
+	PHYDM_DBG(dm, DBG_TXBF, "[%s] Start!\n", __func__);
+
+	PlatformAcquireSpinLock(adapter, RT_TX_SPINLOCK);
+
+	if (MgntGetBuffer(adapter, &tcb, &p_buf)) {
+		construct_vht_gid_mgnt_frame(
+			dm,
+			RA,
+			beamform_entry,
+			p_buf->Buffer.VirtualAddress,
+			&tcb->PacketLength);
+
+		tcb->bw_of_packet = CHANNEL_WIDTH_20;
+		data_rate = MGN_6M;
+		MgntSendPacket(adapter, tcb, p_buf, tcb->PacketLength, NORMAL_QUEUE, data_rate);
+	} else
+		ret = false;
+
+	PlatformReleaseSpinLock(adapter, RT_TX_SPINLOCK);
+
+	if (ret)
+		RT_DISP_DATA(FBEAM, FBEAM_DATA, "", p_buf->Buffer.VirtualAddress, tcb->PacketLength);
+
+	return ret;
+}
+
+/*@
+ * Description: Construct VHT beamforming report poll.
+ *
+ * 2015.05.20. Created by tynli.
+ */
+void construct_vht_bf_report_poll(
+	struct dm_struct *dm,
+	u8 *RA,
+	u8 *buffer,
+	u32 *p_length)
+{
+	struct _RT_BEAMFORMING_INFO *beam_info = &(dm->beamforming_info);
+	void *adapter = beam_info->source_adapter;
+	u8 *p_bf_rpt_poll = buffer;
+
+	/* @Frame control*/
+	SET_80211_HDR_FRAME_CONTROL(p_bf_rpt_poll, 0);
+	SET_80211_HDR_TYPE_AND_SUBTYPE(p_bf_rpt_poll, Type_Beamforming_Report_Poll);
+
+	/* @duration*/
+	SET_80211_HDR_DURATION(p_bf_rpt_poll, 100);
+
+	/* RA*/
+	SET_VHT_BF_REPORT_POLL_RA(p_bf_rpt_poll, RA);
+
+	/* TA*/
+	SET_VHT_BF_REPORT_POLL_TA(p_bf_rpt_poll, adapter->CurrentAddress);
+
+	/* @Feedback Segment Retransmission Bitmap*/
+	SET_VHT_BF_REPORT_POLL_FEEDBACK_SEG_RETRAN_BITMAP(p_bf_rpt_poll, 0xFF);
+
+	*p_length = 17;
+
+	RT_DISP_DATA(FBEAM, FBEAM_DATA, "construct_vht_bf_report_poll():\n", buffer, *p_length);
+}
+
+boolean
+send_sw_vht_bf_report_poll(
+	void *dm_void,
+	u8 *RA,
+	boolean is_final_poll)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	PRT_TCB tcb;
+	PRT_TX_LOCAL_BUFFER p_buf;
+	boolean ret = true;
+	u8 idx = 0, data_rate = 0;
+	struct _RT_BEAMFORMING_INFO *beam_info = &(dm->beamforming_info);
+	struct _RT_BEAMFORMEE_ENTRY *beamform_entry = phydm_beamforming_get_bfee_entry_by_addr(dm, RA, &idx);
+	void *adapter = beam_info->source_adapter;
+
+	PHYDM_DBG(dm, DBG_TXBF, "[%s] Start!\n", __func__);
+
+	PlatformAcquireSpinLock(adapter, RT_TX_SPINLOCK);
+
+	if (MgntGetBuffer(adapter, &tcb, &p_buf)) {
+		construct_vht_bf_report_poll(
+			dm,
+			RA,
+			p_buf->Buffer.VirtualAddress,
+			&tcb->PacketLength);
+
+		tcb->bTxEnableSwCalcDur = true; /* @<tynli_note> need?*/
+		tcb->BWOfPacket = CHANNEL_WIDTH_20;
+
+		if (is_final_poll)
+			tcb->TxBFPktType = RT_BF_PKT_TYPE_FINAL_BF_REPORT_POLL;
+		else
+			tcb->TxBFPktType = RT_BF_PKT_TYPE_BF_REPORT_POLL;
+
+		data_rate = MGN_6M; /* @Legacy OFDM rate*/
+		MgntSendPacket(adapter, tcb, p_buf, tcb->PacketLength, NORMAL_QUEUE, data_rate);
+	} else
+		ret = false;
+
+	PlatformReleaseSpinLock(adapter, RT_TX_SPINLOCK);
+
+	if (ret)
+		RT_DISP_DATA(FBEAM, FBEAM_DATA, "send_sw_vht_bf_report_poll:\n",
+		p_buf->Buffer.VirtualAddress, tcb->PacketLength);
+
+	return ret;
+}
+
+/*@
+ * Description: Construct VHT MU NDPA packet.
+ *	<Note> We should combine this function with construct_vht_ndpa_packet() in the future.
+ *
+ * 2015.05.21. Created by tynli.
+ */
+void construct_vht_mu_ndpa_packet(
+	struct dm_struct *dm,
+	enum channel_width BW,
+	u8 *buffer,
+	u32 *p_length)
+{
+	struct _RT_BEAMFORMING_INFO *beam_info = &(dm->beamforming_info);
+	void *adapter = beam_info->source_adapter;
+	u16 duration = 0;
+	u8 sequence = 0;
+	u8 *p_ndpa_frame = buffer;
+	struct _RT_NDPA_STA_INFO sta_info;
+	u8 idx;
+	u8 dest_addr[6] = {0};
+	struct _RT_BEAMFORMEE_ENTRY *entry = NULL;
+
+	/* @Fill the first MU BFee entry (STA1) MAC addr to destination address then
+	     HW will change A1 to broadcast addr. 2015.05.28. Suggested by SD1 Chunchu. */
+	for (idx = 0; idx < BEAMFORMEE_ENTRY_NUM; idx++) {
+		entry = &(beam_info->beamformee_entry[idx]);
+		if (entry->is_mu_sta) {
+			cp_mac_addr(dest_addr, entry->mac_addr);
+			break;
+		}
+	}
+	if (entry == NULL)
+		return;
+
+	/* @Frame control.*/
+	SET_80211_HDR_FRAME_CONTROL(p_ndpa_frame, 0);
+	SET_80211_HDR_TYPE_AND_SUBTYPE(p_ndpa_frame, Type_NDPA);
+
+	SET_80211_HDR_ADDRESS1(p_ndpa_frame, dest_addr);
+	SET_80211_HDR_ADDRESS2(p_ndpa_frame, entry->my_mac_addr);
+
+	/*@--------------------------------------------*/
+	/* @<Note> Need to modify "duration" to MU consideration. */
+	duration = 2 * a_SifsTime + 44;
+
+	if (BW == CHANNEL_WIDTH_80)
+		duration += 40;
+	else if (BW == CHANNEL_WIDTH_40)
+		duration += 87;
+	else
+		duration += 180;
+	/*@--------------------------------------------*/
+
+	SET_80211_HDR_DURATION(p_ndpa_frame, duration);
+
+	sequence = *(dm->sounding_seq) << 2;
+	odm_move_memory(dm, p_ndpa_frame + 16, &sequence, 1);
+
+	*p_length = 17;
+
+	/* @Construct STA info. for multiple STAs*/
+	for (idx = 0; idx < BEAMFORMEE_ENTRY_NUM; idx++) {
+		entry = &(beam_info->beamformee_entry[idx]);
+		if (entry->is_mu_sta) {
+			sta_info.aid = entry->AID;
+			sta_info.feedback_type = 1; /* @1'b1: MU*/
+			sta_info.nc_index = 0;
+
+			PHYDM_DBG(dm, DBG_TXBF,
+				  "[%s] Get beamformee_entry idx(%d), AID =%d\n",
+				  __func__, idx, entry->AID);
+
+			odm_move_memory(dm, p_ndpa_frame + (*p_length), (u8 *)&sta_info, 2);
+			*p_length += 2;
+		}
+	}
+}
+
+boolean
+send_sw_vht_mu_ndpa_packet(
+	void *dm_void,
+	enum channel_width BW)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	PRT_TCB tcb;
+	PRT_TX_LOCAL_BUFFER p_buf;
+	boolean ret = true;
+	u8 ndp_tx_rate = 0;
+	struct _RT_BEAMFORMING_INFO *beam_info = &(dm->beamforming_info);
+	void *adapter = beam_info->source_adapter;
+
+	ndp_tx_rate = MGN_VHT2SS_MCS0;
+	PHYDM_DBG(dm, DBG_TXBF, "[%s] ndp_tx_rate =%d\n", __func__,
+		  ndp_tx_rate);
+
+	PlatformAcquireSpinLock(adapter, RT_TX_SPINLOCK);
+
+	if (MgntGetBuffer(adapter, &tcb, &p_buf)) {
+		construct_vht_mu_ndpa_packet(
+			dm,
+			BW,
+			p_buf->Buffer.VirtualAddress,
+			&tcb->PacketLength);
+
+		tcb->bTxEnableSwCalcDur = true;
+		tcb->BWOfPacket = BW;
+		tcb->TxBFPktType = RT_BF_PKT_TYPE_BROADCAST_NDPA;
+
+		/*rate of NDP decide by nr*/
+		MgntSendPacket(adapter, tcb, p_buf, tcb->PacketLength, NORMAL_QUEUE, ndp_tx_rate);
+	} else
+		ret = false;
+
+	PlatformReleaseSpinLock(adapter, RT_TX_SPINLOCK);
+
+	if (ret)
+		RT_DISP_DATA(FBEAM, FBEAM_DATA, "", p_buf->Buffer.VirtualAddress, tcb->PacketLength);
+
+	return ret;
+}
+
+void dbg_construct_vht_mundpa_packet(
+	struct dm_struct *dm,
+	enum channel_width BW,
+	u8 *buffer,
+	u32 *p_length)
+{
+	struct _RT_BEAMFORMING_INFO *beam_info = &(dm->beamforming_info);
+	void *adapter = beam_info->source_adapter;
+	u16 duration = 0;
+	u8 sequence = 0;
+	u8 *p_ndpa_frame = buffer;
+	struct _RT_NDPA_STA_INFO sta_info;
+	u8 idx;
+	u8 dest_addr[6] = {0};
+	struct _RT_BEAMFORMEE_ENTRY *entry = NULL;
+
+	boolean is_STA1 = false;
+
+	/* @Fill the first MU BFee entry (STA1) MAC addr to destination address then
+	     HW will change A1 to broadcast addr. 2015.05.28. Suggested by SD1 Chunchu. */
+	for (idx = 0; idx < BEAMFORMEE_ENTRY_NUM; idx++) {
+		entry = &(beam_info->beamformee_entry[idx]);
+		if (entry->is_mu_sta) {
+			if (is_STA1 == false) {
+				is_STA1 = true;
+				continue;
+			} else {
+				cp_mac_addr(dest_addr, entry->mac_addr);
+				break;
+			}
+		}
+	}
+
+	/* @Frame control.*/
+	SET_80211_HDR_FRAME_CONTROL(p_ndpa_frame, 0);
+	SET_80211_HDR_TYPE_AND_SUBTYPE(p_ndpa_frame, Type_NDPA);
+
+	SET_80211_HDR_ADDRESS1(p_ndpa_frame, dest_addr);
+	SET_80211_HDR_ADDRESS2(p_ndpa_frame, dm->CurrentAddress);
+
+	/*@--------------------------------------------*/
+	/* @<Note> Need to modify "duration" to MU consideration. */
+	duration = 2 * a_SifsTime + 44;
+
+	if (BW == CHANNEL_WIDTH_80)
+		duration += 40;
+	else if (BW == CHANNEL_WIDTH_40)
+		duration += 87;
+	else
+		duration += 180;
+	/*@--------------------------------------------*/
+
+	SET_80211_HDR_DURATION(p_ndpa_frame, duration);
+
+	sequence = *(dm->sounding_seq) << 2;
+	odm_move_memory(dm, p_ndpa_frame + 16, &sequence, 1);
+
+	*p_length = 17;
+
+	/*STA2's STA Info*/
+	sta_info.aid = entry->aid;
+	sta_info.feedback_type = 1; /* @1'b1: MU */
+	sta_info.nc_index = 0;
+
+	PHYDM_DBG(dm, DBG_TXBF, "[%s] Get beamformee_entry idx(%d), AID =%d\n",
+		  __func__, idx, entry->aid);
+
+	odm_move_memory(dm, p_ndpa_frame + (*p_length), (u8 *)&sta_info, 2);
+	*p_length += 2;
+}
+
+boolean
+dbg_send_sw_vht_mundpa_packet(
+	void *dm_void,
+	enum channel_width BW)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	PRT_TCB tcb;
+	PRT_TX_LOCAL_BUFFER p_buf;
+	boolean ret = true;
+	u8 ndp_tx_rate = 0;
+	struct _RT_BEAMFORMING_INFO *beam_info = &(dm->beamforming_info);
+	void *adapter = beam_info->source_adapter;
+
+	ndp_tx_rate = MGN_VHT2SS_MCS0;
+	PHYDM_DBG(dm, DBG_TXBF, "[%s] ndp_tx_rate =%d\n", __func__,
+		  ndp_tx_rate);
+
+	PlatformAcquireSpinLock(adapter, RT_TX_SPINLOCK);
+
+	if (MgntGetBuffer(adapter, &tcb, &p_buf)) {
+		dbg_construct_vht_mundpa_packet(
+			dm,
+			BW,
+			p_buf->Buffer.VirtualAddress,
+			&tcb->PacketLength);
+
+		tcb->bTxEnableSwCalcDur = true;
+		tcb->BWOfPacket = BW;
+		tcb->TxBFPktType = RT_BF_PKT_TYPE_UNICAST_NDPA;
+
+		/*rate of NDP decide by nr*/
+		MgntSendPacket(adapter, tcb, p_buf, tcb->PacketLength, NORMAL_QUEUE, ndp_tx_rate);
+	} else
+		ret = false;
+
+	PlatformReleaseSpinLock(adapter, RT_TX_SPINLOCK);
+
+	if (ret)
+		RT_DISP_DATA(FBEAM, FBEAM_DATA, "", p_buf->Buffer.VirtualAddress, tcb->PacketLength);
+
+	return ret;
+}
+
+#endif /*@#if (SUPPORT_MU_BF == 1)*/
+#endif /*@#ifdef SUPPORT_MU_BF*/
+
+#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
+
+u32 beamforming_get_report_frame(
+	void *dm_void,
+	union recv_frame *precv_frame)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	u32 ret = _SUCCESS;
+	struct _RT_BEAMFORMEE_ENTRY *beamform_entry = NULL;
+	u8 *pframe = precv_frame->u.hdr.rx_data;
+	u32 frame_len = precv_frame->u.hdr.len;
+	u8 *TA;
+	u8 idx, offset;
+
+	/*@Memory comparison to see if CSI report is the same with previous one*/
+	TA = get_addr2_ptr(pframe);
+	beamform_entry = phydm_beamforming_get_bfee_entry_by_addr(dm, TA, &idx);
+	if (beamform_entry->beamform_entry_cap & BEAMFORMER_CAP_VHT_SU)
+		offset = 31; /*@24+(1+1+3)+2  MAC header+(Category+ActionCode+MIMOControlField)+SNR(nc=2)*/
+	else if (beamform_entry->beamform_entry_cap & BEAMFORMER_CAP_HT_EXPLICIT)
+		offset = 34; /*@24+(1+1+6)+2  MAC header+(Category+ActionCode+MIMOControlField)+SNR(nc=2)*/
+	else
+		return ret;
+
+	return ret;
+}
+
+boolean
+send_fw_ht_ndpa_packet(
+	void *dm_void,
+	u8 *RA,
+	enum channel_width BW)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct _ADAPTER *adapter = dm->adapter;
+	struct xmit_frame *pmgntframe;
+	struct pkt_attrib *pattrib;
+	struct rtw_ieee80211_hdr *pwlanhdr;
+	struct xmit_priv *pxmitpriv = &(adapter->xmitpriv);
+	struct mlme_ext_priv *pmlmeext = &adapter->mlmeextpriv;
+	struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
+	u8 action_hdr[4] = {ACT_CAT_VENDOR, 0x00, 0xe0, 0x4c};
+	u8 *pframe;
+	u16 *fctrl;
+	u16 duration = 0;
+	u8 a_sifs_time = 0, ndp_tx_rate = 0, idx = 0;
+	struct _RT_BEAMFORMING_INFO *beam_info = &(dm->beamforming_info);
+	struct _RT_BEAMFORMEE_ENTRY *beamform_entry = phydm_beamforming_get_bfee_entry_by_addr(dm, RA, &idx);
+
+	pmgntframe = alloc_mgtxmitframe(pxmitpriv);
+
+	if (pmgntframe == NULL) {
+		PHYDM_DBG(dm, DBG_TXBF, "%s, alloc mgnt frame fail\n",
+			  __func__);
+		return false;
+	}
+
+	/* update attribute */
+	pattrib = &pmgntframe->attrib;
+	update_mgntframe_attrib(adapter, pattrib);
+
+	pattrib->qsel = QSLT_BEACON;
+	ndp_tx_rate = beamforming_get_htndp_tx_rate(dm, beamform_entry->comp_steering_num_of_bfer);
+	PHYDM_DBG(dm, DBG_TXBF, "[%s] ndp_tx_rate =%d\n", __func__,
+		  ndp_tx_rate);
+	pattrib->rate = ndp_tx_rate;
+	pattrib->bwmode = BW;
+	pattrib->order = 1;
+	pattrib->subtype = WIFI_ACTION_NOACK;
+
+	_rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET);
+
+	pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET;
+
+	pwlanhdr = (struct rtw_ieee80211_hdr *)pframe;
+
+	fctrl = &pwlanhdr->frame_ctl;
+	*(fctrl) = 0;
+
+	set_order_bit(pframe);
+	set_frame_sub_type(pframe, WIFI_ACTION_NOACK);
+
+	_rtw_memcpy(pwlanhdr->addr1, RA, ETH_ALEN);
+	_rtw_memcpy(pwlanhdr->addr2, beamform_entry->my_mac_addr, ETH_ALEN);
+	_rtw_memcpy(pwlanhdr->addr3, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN);
+
+	if (pmlmeext->cur_wireless_mode == WIRELESS_11B)
+		a_sifs_time = 10;
+	else
+		a_sifs_time = 16;
+
+	duration = 2 * a_sifs_time + 40;
+
+	if (BW == CHANNEL_WIDTH_40)
+		duration += 87;
+	else
+		duration += 180;
+
+	set_duration(pframe, duration);
+
+	/* @HT control field */
+	SET_HT_CTRL_CSI_STEERING(pframe + 24, 3);
+	SET_HT_CTRL_NDP_ANNOUNCEMENT(pframe + 24, 1);
+
+	_rtw_memcpy(pframe + 28, action_hdr, 4);
+
+	pattrib->pktlen = 32;
+
+	pattrib->last_txcmdsz = pattrib->pktlen;
+
+	dump_mgntframe(adapter, pmgntframe);
+
+	return true;
+}
+
+boolean
+send_sw_ht_ndpa_packet(
+	void *dm_void,
+	u8 *RA,
+	enum channel_width BW)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct _ADAPTER *adapter = dm->adapter;
+	struct xmit_frame *pmgntframe;
+	struct pkt_attrib *pattrib;
+	struct rtw_ieee80211_hdr *pwlanhdr;
+	struct xmit_priv *pxmitpriv = &(adapter->xmitpriv);
+	struct mlme_ext_priv *pmlmeext = &adapter->mlmeextpriv;
+	struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
+	u8 action_hdr[4] = {ACT_CAT_VENDOR, 0x00, 0xe0, 0x4c};
+	u8 *pframe;
+	u16 *fctrl;
+	u16 duration = 0;
+	u8 a_sifs_time = 0, ndp_tx_rate = 0, idx = 0;
+	struct _RT_BEAMFORMING_INFO *beam_info = &(dm->beamforming_info);
+	struct _RT_BEAMFORMEE_ENTRY *beamform_entry = phydm_beamforming_get_bfee_entry_by_addr(dm, RA, &idx);
+
+	ndp_tx_rate = beamforming_get_htndp_tx_rate(dm, beamform_entry->comp_steering_num_of_bfer);
+
+	pmgntframe = alloc_mgtxmitframe(pxmitpriv);
+
+	if (pmgntframe == NULL) {
+		PHYDM_DBG(dm, DBG_TXBF, "%s, alloc mgnt frame fail\n",
+			  __func__);
+		return false;
+	}
+
+	/*update attribute*/
+	pattrib = &pmgntframe->attrib;
+	update_mgntframe_attrib(adapter, pattrib);
+	pattrib->qsel = QSLT_MGNT;
+	pattrib->rate = ndp_tx_rate;
+	pattrib->bwmode = BW;
+	pattrib->order = 1;
+	pattrib->subtype = WIFI_ACTION_NOACK;
+
+	_rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET);
+
+	pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET;
+
+	pwlanhdr = (struct rtw_ieee80211_hdr *)pframe;
+
+	fctrl = &pwlanhdr->frame_ctl;
+	*(fctrl) = 0;
+
+	set_order_bit(pframe);
+	set_frame_sub_type(pframe, WIFI_ACTION_NOACK);
+
+	_rtw_memcpy(pwlanhdr->addr1, RA, ETH_ALEN);
+	_rtw_memcpy(pwlanhdr->addr2, beamform_entry->my_mac_addr, ETH_ALEN);
+	_rtw_memcpy(pwlanhdr->addr3, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN);
+
+	if (pmlmeext->cur_wireless_mode == WIRELESS_11B)
+		a_sifs_time = 10;
+	else
+		a_sifs_time = 16;
+
+	duration = 2 * a_sifs_time + 40;
+
+	if (BW == CHANNEL_WIDTH_40)
+		duration += 87;
+	else
+		duration += 180;
+
+	set_duration(pframe, duration);
+
+	/*@HT control field*/
+	SET_HT_CTRL_CSI_STEERING(pframe + 24, 3);
+	SET_HT_CTRL_NDP_ANNOUNCEMENT(pframe + 24, 1);
+
+	_rtw_memcpy(pframe + 28, action_hdr, 4);
+
+	pattrib->pktlen = 32;
+
+	pattrib->last_txcmdsz = pattrib->pktlen;
+
+	dump_mgntframe(adapter, pmgntframe);
+
+	return true;
+}
+
+boolean
+send_fw_vht_ndpa_packet(
+	void *dm_void,
+	u8 *RA,
+	u16 AID,
+	enum channel_width BW)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct _ADAPTER *adapter = dm->adapter;
+	struct xmit_frame *pmgntframe;
+	struct pkt_attrib *pattrib;
+	struct rtw_ieee80211_hdr *pwlanhdr;
+	struct xmit_priv *pxmitpriv = &(adapter->xmitpriv);
+	struct mlme_ext_priv *pmlmeext = &adapter->mlmeextpriv;
+	struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
+	struct mlme_priv *pmlmepriv = &(adapter->mlmepriv);
+	u8 *pframe;
+	u16 *fctrl;
+	u16 duration = 0;
+	u8 sequence = 0, a_sifs_time = 0, ndp_tx_rate = 0, idx = 0;
+	struct _RT_BEAMFORMING_INFO *beam_info = &(dm->beamforming_info);
+	struct _RT_BEAMFORMEE_ENTRY *beamform_entry = phydm_beamforming_get_bfee_entry_by_addr(dm, RA, &idx);
+	struct _RT_NDPA_STA_INFO sta_info;
+
+	pmgntframe = alloc_mgtxmitframe(pxmitpriv);
+
+	if (pmgntframe == NULL) {
+		PHYDM_DBG(dm, DBG_TXBF, "%s, alloc mgnt frame fail\n",
+			  __func__);
+		return false;
+	}
+
+	/* update attribute */
+	pattrib = &pmgntframe->attrib;
+	_rtw_memcpy(pattrib->ra, RA, ETH_ALEN);
+	update_mgntframe_attrib(adapter, pattrib);
+
+	pattrib->qsel = QSLT_BEACON;
+	ndp_tx_rate = beamforming_get_vht_ndp_tx_rate(dm, beamform_entry->comp_steering_num_of_bfer);
+	PHYDM_DBG(dm, DBG_TXBF, "[%s] ndp_tx_rate =%d\n", __func__,
+		  ndp_tx_rate);
+	pattrib->rate = ndp_tx_rate;
+	pattrib->bwmode = BW;
+	pattrib->subtype = WIFI_NDPA;
+
+	_rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET);
+
+	pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET;
+
+	pwlanhdr = (struct rtw_ieee80211_hdr *)pframe;
+
+	fctrl = &pwlanhdr->frame_ctl;
+	*(fctrl) = 0;
+
+	set_frame_sub_type(pframe, WIFI_NDPA);
+
+	_rtw_memcpy(pwlanhdr->addr1, RA, ETH_ALEN);
+	_rtw_memcpy(pwlanhdr->addr2, beamform_entry->my_mac_addr, ETH_ALEN);
+
+	if (is_supported_5g(pmlmeext->cur_wireless_mode) || is_supported_ht(pmlmeext->cur_wireless_mode))
+		a_sifs_time = 16;
+	else
+		a_sifs_time = 10;
+
+	duration = 2 * a_sifs_time + 44;
+
+	if (BW == CHANNEL_WIDTH_80)
+		duration += 40;
+	else if (BW == CHANNEL_WIDTH_40)
+		duration += 87;
+	else
+		duration += 180;
+
+	set_duration(pframe, duration);
+
+	sequence = beam_info->sounding_sequence << 2;
+	if (beam_info->sounding_sequence >= 0x3f)
+		beam_info->sounding_sequence = 0;
+	else
+		beam_info->sounding_sequence++;
+
+	_rtw_memcpy(pframe + 16, &sequence, 1);
+
+	if (((pmlmeinfo->state & 0x03) == WIFI_FW_ADHOC_STATE) || ((pmlmeinfo->state & 0x03) == WIFI_FW_AP_STATE))
+		AID = 0;
+
+	sta_info.aid = AID;
+	sta_info.feedback_type = 0;
+	sta_info.nc_index = 0;
+
+	_rtw_memcpy(pframe + 17, (u8 *)&sta_info, 2);
+
+	pattrib->pktlen = 19;
+
+	pattrib->last_txcmdsz = pattrib->pktlen;
+
+	dump_mgntframe(adapter, pmgntframe);
+
+	return true;
+}
+
+boolean
+send_sw_vht_ndpa_packet(
+	void *dm_void,
+	u8 *RA,
+	u16 AID,
+	enum channel_width BW)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct _ADAPTER *adapter = dm->adapter;
+	struct xmit_frame *pmgntframe;
+	struct pkt_attrib *pattrib;
+	struct rtw_ieee80211_hdr *pwlanhdr;
+	struct xmit_priv *pxmitpriv = &(adapter->xmitpriv);
+	struct mlme_ext_priv *pmlmeext = &adapter->mlmeextpriv;
+	struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
+	struct mlme_priv *pmlmepriv = &(adapter->mlmepriv);
+	struct _RT_NDPA_STA_INFO ndpa_sta_info;
+	u8 ndp_tx_rate = 0, sequence = 0, a_sifs_time = 0, idx = 0;
+	u8 *pframe;
+	u16 *fctrl;
+	u16 duration = 0;
+	struct _RT_BEAMFORMING_INFO *beam_info = &(dm->beamforming_info);
+	struct _RT_BEAMFORMEE_ENTRY *beamform_entry = phydm_beamforming_get_bfee_entry_by_addr(dm, RA, &idx);
+
+	ndp_tx_rate = beamforming_get_vht_ndp_tx_rate(dm, beamform_entry->comp_steering_num_of_bfer);
+	PHYDM_DBG(dm, DBG_TXBF, "[%s] ndp_tx_rate =%d\n", __func__,
+		  ndp_tx_rate);
+
+	pmgntframe = alloc_mgtxmitframe(pxmitpriv);
+
+	if (pmgntframe == NULL) {
+		PHYDM_DBG(dm, DBG_TXBF, "%s, alloc mgnt frame fail\n",
+			  __func__);
+		return false;
+	}
+
+	/*update attribute*/
+	pattrib = &pmgntframe->attrib;
+	_rtw_memcpy(pattrib->ra, RA, ETH_ALEN);
+	update_mgntframe_attrib(adapter, pattrib);
+	pattrib->qsel = QSLT_MGNT;
+	pattrib->rate = ndp_tx_rate;
+	pattrib->bwmode = BW;
+	pattrib->subtype = WIFI_NDPA;
+
+	_rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET);
+
+	pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET;
+
+	pwlanhdr = (struct rtw_ieee80211_hdr *)pframe;
+
+	fctrl = &pwlanhdr->frame_ctl;
+	*(fctrl) = 0;
+
+	set_frame_sub_type(pframe, WIFI_NDPA);
+
+	_rtw_memcpy(pwlanhdr->addr1, RA, ETH_ALEN);
+	_rtw_memcpy(pwlanhdr->addr2, beamform_entry->my_mac_addr, ETH_ALEN);
+
+	if (is_supported_5g(pmlmeext->cur_wireless_mode) || is_supported_ht(pmlmeext->cur_wireless_mode))
+		a_sifs_time = 16;
+	else
+		a_sifs_time = 10;
+
+	duration = 2 * a_sifs_time + 44;
+
+	if (BW == CHANNEL_WIDTH_80)
+		duration += 40;
+	else if (BW == CHANNEL_WIDTH_40)
+		duration += 87;
+	else
+		duration += 180;
+
+	set_duration(pframe, duration);
+
+	sequence = beam_info->sounding_sequence << 2;
+	if (beam_info->sounding_sequence >= 0x3f)
+		beam_info->sounding_sequence = 0;
+	else
+		beam_info->sounding_sequence++;
+
+	_rtw_memcpy(pframe + 16, &sequence, 1);
+	if (((pmlmeinfo->state & 0x03) == WIFI_FW_ADHOC_STATE) || ((pmlmeinfo->state & 0x03) == WIFI_FW_AP_STATE))
+		AID = 0;
+
+	ndpa_sta_info.aid = AID;
+	ndpa_sta_info.feedback_type = 0;
+	ndpa_sta_info.nc_index = 0;
+
+	_rtw_memcpy(pframe + 17, (u8 *)&ndpa_sta_info, 2);
+
+	pattrib->pktlen = 19;
+
+	pattrib->last_txcmdsz = pattrib->pktlen;
+
+	dump_mgntframe(adapter, pmgntframe);
+	PHYDM_DBG(dm, DBG_TXBF, "[%s] [%d]\n", __func__, __LINE__);
+
+	return true;
+}
+
+#endif
+
+void beamforming_get_ndpa_frame(
+	void *dm_void,
+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
+	OCTET_STRING pdu_os
+#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
+	union recv_frame *precv_frame
+#endif
+	)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	u8 *TA;
+	u8 idx, sequence;
+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
+	u8 *p_ndpa_frame = pdu_os.Octet;
+#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
+	u8 *p_ndpa_frame = precv_frame->u.hdr.rx_data;
+#endif
+	struct _RT_BEAMFORMER_ENTRY *beamformer_entry = NULL; /*@Modified By Jeffery @2014-10-29*/
+
+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
+	RT_DISP_DATA(FBEAM, FBEAM_DATA, "beamforming_get_ndpa_frame\n",
+	pdu_os.Octet, pdu_os.Length);
+	if (IsCtrlNDPA(p_ndpa_frame) == false)
+#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
+	if (get_frame_sub_type(p_ndpa_frame) != WIFI_NDPA)
+#endif
+		return;
+	else if (!(dm->support_ic_type & (ODM_RTL8812 | ODM_RTL8821))) {
+		PHYDM_DBG(dm, DBG_TXBF, "[%s] not 8812 or 8821A, return\n",
+			  __func__);
+		return;
+	}
+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
+	TA = Frame_Addr2(pdu_os);
+#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
+	TA = get_addr2_ptr(p_ndpa_frame);
+#endif
+	/*Remove signaling TA. */
+	TA[0] = TA[0] & 0xFE;
+
+	beamformer_entry = phydm_beamforming_get_bfer_entry_by_addr(dm, TA, &idx); /* @Modified By Jeffery @2014-10-29 */
+
+	/*@Break options for Clock Reset*/
+	if (beamformer_entry == NULL)
+		return;
+	else if (!(beamformer_entry->beamform_entry_cap & BEAMFORMEE_CAP_VHT_SU))
+		return;
+	/*@log_success: As long as 8812A receive NDPA and feedback CSI succeed once, clock reset is NO LONGER needed !2015-04-10, Jeffery*/
+	/*@clock_reset_times: While BFer entry always doesn't receive our CSI, clock will reset again and again.So clock_reset_times is limited to 5 times.2015-04-13, Jeffery*/
+	else if ((beamformer_entry->log_success == 1) || (beamformer_entry->clock_reset_times == 5)) {
+		PHYDM_DBG(dm, DBG_TXBF,
+			  "[%s] log_seq=%d, pre_log_seq=%d, log_retry_cnt=%d, log_success=%d, clock_reset_times=%d, clock reset is no longer needed.\n",
+			  __func__, beamformer_entry->log_seq,
+			  beamformer_entry->pre_log_seq,
+			  beamformer_entry->log_retry_cnt,
+			  beamformer_entry->log_success,
+			  beamformer_entry->clock_reset_times);
+
+		return;
+	}
+
+	sequence = (p_ndpa_frame[16]) >> 2;
+
+	PHYDM_DBG(dm, DBG_TXBF,
+		  "[%s] Start, sequence=%d, log_seq=%d, pre_log_seq=%d, log_retry_cnt=%d, clock_reset_times=%d, log_success=%d\n",
+		  __func__, sequence, beamformer_entry->log_seq,
+		  beamformer_entry->pre_log_seq,
+		  beamformer_entry->log_retry_cnt,
+		  beamformer_entry->clock_reset_times,
+		  beamformer_entry->log_success);
+
+	if (beamformer_entry->log_seq != 0 && beamformer_entry->pre_log_seq != 0) {
+		/*Success condition*/
+		if (beamformer_entry->log_seq != sequence && beamformer_entry->pre_log_seq != beamformer_entry->log_seq) {
+			/* @break option for clcok reset, 2015-03-30, Jeffery */
+			beamformer_entry->log_retry_cnt = 0;
+			/*@As long as 8812A receive NDPA and feedback CSI succeed once, clock reset is no longer needed.*/
+			/*That is, log_success is NOT needed to be reset to zero, 2015-04-13, Jeffery*/
+			beamformer_entry->log_success = 1;
+
+		} else { /*@Fail condition*/
+
+			if (beamformer_entry->log_retry_cnt == 5) {
+				beamformer_entry->clock_reset_times++;
+				beamformer_entry->log_retry_cnt = 0;
+
+				PHYDM_DBG(dm, DBG_TXBF,
+					  "[%s] Clock Reset!!! clock_reset_times=%d\n",
+					  __func__,
+					  beamformer_entry->clock_reset_times);
+				hal_com_txbf_set(dm, TXBF_SET_SOUNDING_CLK, NULL);
+
+			} else
+				beamformer_entry->log_retry_cnt++;
+		}
+	}
+
+	/*Update log_seq & pre_log_seq*/
+	beamformer_entry->pre_log_seq = beamformer_entry->log_seq;
+	beamformer_entry->log_seq = sequence;
+}
+
+#endif
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/txbf/haltxbfinterface.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/txbf/haltxbfinterface.h
--- linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/txbf/haltxbfinterface.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/txbf/haltxbfinterface.h	2020-04-10 16:35:06.836661001 +0300
@@ -0,0 +1,167 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017  Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * The full GNU General Public License is included in this distribution in the
+ * file called LICENSE.
+ *
+ * Contact Information:
+ * wlanfae <wlanfae@realtek.com>
+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
+ * Hsinchu 300, Taiwan.
+ *
+ * Larry Finger <Larry.Finger@lwfinger.net>
+ *
+ *****************************************************************************/
+#ifndef __HAL_TXBF_INTERFACE_H__
+#define __HAL_TXBF_INTERFACE_H__
+
+#if (BEAMFORMING_SUPPORT == 1)
+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
+
+#define a_SifsTime ((IS_WIRELESS_MODE_5G(adapter) || IS_WIRELESS_MODE_N_24G(adapter)) ? 16 : 10)
+
+void beamforming_gid_paid(
+	void *adapter,
+	PRT_TCB tcb);
+
+enum rt_status
+beamforming_get_report_frame(
+	void *adapter,
+	PRT_RFD rfd,
+	POCTET_STRING p_pdu_os);
+
+void beamforming_get_ndpa_frame(
+	void *dm_void,
+	OCTET_STRING pdu_os);
+
+boolean
+send_fw_ht_ndpa_packet(
+	void *dm_void,
+	u8 *RA,
+	enum channel_width BW);
+
+boolean
+send_fw_vht_ndpa_packet(
+	void *dm_void,
+	u8 *RA,
+	u16 AID,
+	enum channel_width BW);
+
+boolean
+send_sw_vht_ndpa_packet(
+	void *dm_void,
+	u8 *RA,
+	u16 AID,
+	enum channel_width BW);
+
+boolean
+send_sw_ht_ndpa_packet(
+	void *dm_void,
+	u8 *RA,
+	enum channel_width BW);
+
+#if (SUPPORT_MU_BF == 1)
+enum rt_status
+beamforming_get_vht_gid_mgnt_frame(
+	void *adapter,
+	PRT_RFD rfd,
+	POCTET_STRING p_pdu_os);
+
+boolean
+send_sw_vht_gid_mgnt_frame(
+	void *dm_void,
+	u8 *RA,
+	u8 idx);
+
+boolean
+send_sw_vht_bf_report_poll(
+	void *dm_void,
+	u8 *RA,
+	boolean is_final_poll);
+
+boolean
+send_sw_vht_mu_ndpa_packet(
+	void *dm_void,
+	enum channel_width BW);
+#else
+#define beamforming_get_vht_gid_mgnt_frame(adapter, rfd, p_pdu_os) RT_STATUS_FAILURE
+#define send_sw_vht_gid_mgnt_frame(dm_void, RA)
+#define send_sw_vht_bf_report_poll(dm_void, RA, is_final_poll)
+#define send_sw_vht_mu_ndpa_packet(dm_void, BW)
+#endif
+
+#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
+
+u32 beamforming_get_report_frame(
+	void *dm_void,
+	union recv_frame *precv_frame);
+
+boolean
+send_fw_ht_ndpa_packet(
+	void *dm_void,
+	u8 *RA,
+	enum channel_width BW);
+
+boolean
+send_sw_ht_ndpa_packet(
+	void *dm_void,
+	u8 *RA,
+	enum channel_width BW);
+
+boolean
+send_fw_vht_ndpa_packet(
+	void *dm_void,
+	u8 *RA,
+	u16 AID,
+	enum channel_width BW);
+
+boolean
+send_sw_vht_ndpa_packet(
+	void *dm_void,
+	u8 *RA,
+	u16 AID,
+	enum channel_width BW);
+#endif
+
+void beamforming_get_ndpa_frame(
+	void *dm_void,
+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
+	OCTET_STRING pdu_os
+#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
+	union recv_frame *precv_frame
+#endif
+	);
+
+boolean
+dbg_send_sw_vht_mundpa_packet(
+	void *dm_void,
+	enum channel_width BW);
+
+#else
+#define beamforming_get_ndpa_frame(dm, _pdu_os)
+#if (DM_ODM_SUPPORT_TYPE == ODM_CE)
+#define beamforming_get_report_frame(adapter, precv_frame) RT_STATUS_FAILURE
+#elif (DM_ODM_SUPPORT_TYPE == ODM_WIN)
+#define beamforming_get_report_frame(adapter, rfd, p_pdu_os) RT_STATUS_FAILURE
+#define beamforming_get_vht_gid_mgnt_frame(adapter, rfd, p_pdu_os) RT_STATUS_FAILURE
+#endif
+#define send_fw_ht_ndpa_packet(dm_void, RA, BW)
+#define send_sw_ht_ndpa_packet(dm_void, RA, BW)
+#define send_fw_vht_ndpa_packet(dm_void, RA, AID, BW)
+#define send_sw_vht_ndpa_packet(dm_void, RA, AID, BW)
+#define send_sw_vht_gid_mgnt_frame(dm_void, RA, idx)
+#define send_sw_vht_bf_report_poll(dm_void, RA, is_final_poll)
+#define send_sw_vht_mu_ndpa_packet(dm_void, BW)
+#endif
+
+#endif
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/txbf/haltxbfjaguar.c linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/txbf/haltxbfjaguar.c
--- linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/txbf/haltxbfjaguar.c	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/txbf/haltxbfjaguar.c	2020-04-10 16:35:06.836661001 +0300
@@ -0,0 +1,508 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2016 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+/*************************************************************
+ * Description:
+ *
+ * This file is for 8812/8821/8811 TXBF mechanism
+ *
+ ************************************************************/
+#include "mp_precomp.h"
+#include "../phydm_precomp.h"
+
+#if (BEAMFORMING_SUPPORT == 1)
+#if ((RTL8812A_SUPPORT == 1) || (RTL8821A_SUPPORT == 1))
+void hal_txbf_8812a_set_ndpa_rate(
+	void *dm_void,
+	u8 BW,
+	u8 rate)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+
+	odm_write_1byte(dm, REG_NDPA_OPT_CTRL_8812A, (rate << 2 | BW));
+}
+
+void hal_txbf_jaguar_rf_mode(
+	void *dm_void,
+	struct _RT_BEAMFORMING_INFO *beam_info)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+
+	if (dm->rf_type == RF_1T1R)
+		return;
+
+	PHYDM_DBG(dm, DBG_TXBF, "[%s] set TxIQGen\n", __func__);
+
+	odm_set_rf_reg(dm, RF_PATH_A, RF_0xef, 0x80000, 0x1); /*RF mode table write enable*/
+	odm_set_rf_reg(dm, RF_PATH_B, RF_0xef, 0x80000, 0x1); /*RF mode table write enable*/
+
+	if (beam_info->beamformee_su_cnt > 0) {
+		/* Paath_A */
+		odm_set_rf_reg(dm, RF_PATH_A, RF_0x30, 0x78000, 0x3); /*Select RX mode*/
+		odm_set_rf_reg(dm, RF_PATH_A, RF_0x31, 0xfffff, 0x3F7FF); /*Set Table data*/
+		odm_set_rf_reg(dm, RF_PATH_A, RF_0x32, 0xfffff, 0xE26BF); /*@Enable TXIQGEN in RX mode*/
+		/* Path_B */
+		odm_set_rf_reg(dm, RF_PATH_B, RF_0x30, 0x78000, 0x3); /*Select RX mode*/
+		odm_set_rf_reg(dm, RF_PATH_B, RF_0x31, 0xfffff, 0x3F7FF); /*Set Table data*/
+		odm_set_rf_reg(dm, RF_PATH_B, RF_0x32, 0xfffff, 0xE26BF); /*@Enable TXIQGEN in RX mode*/
+	} else {
+		/* Paath_A */
+		odm_set_rf_reg(dm, RF_PATH_A, RF_0x30, 0x78000, 0x3); /*Select RX mode*/
+		odm_set_rf_reg(dm, RF_PATH_A, RF_0x31, 0xfffff, 0x3F7FF); /*Set Table data*/
+		odm_set_rf_reg(dm, RF_PATH_A, RF_0x32, 0xfffff, 0xC26BF); /*@Disable TXIQGEN in RX mode*/
+		/* Path_B */
+		odm_set_rf_reg(dm, RF_PATH_B, RF_0x30, 0x78000, 0x3); /*Select RX mode*/
+		odm_set_rf_reg(dm, RF_PATH_B, RF_0x31, 0xfffff, 0x3F7FF); /*Set Table data*/
+		odm_set_rf_reg(dm, RF_PATH_B, RF_0x32, 0xfffff, 0xC26BF); /*@Disable TXIQGEN in RX mode*/
+	}
+
+	odm_set_rf_reg(dm, RF_PATH_A, RF_0xef, 0x80000, 0x0); /*RF mode table write disable*/
+	odm_set_rf_reg(dm, RF_PATH_B, RF_0xef, 0x80000, 0x0); /*RF mode table write disable*/
+
+	if (beam_info->beamformee_su_cnt > 0)
+		odm_set_bb_reg(dm, R_0x80c, MASKBYTE1, 0x33);
+	else
+		odm_set_bb_reg(dm, R_0x80c, MASKBYTE1, 0x11);
+}
+
+void hal_txbf_jaguar_download_ndpa(
+	void *dm_void,
+	u8 idx)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	u8 u1b_tmp = 0, tmp_reg422 = 0, head_page;
+	u8 bcn_valid_reg = 0, count = 0, dl_bcn_count = 0;
+	boolean is_send_beacon = false;
+	u8 tx_page_bndy = LAST_ENTRY_OF_TX_PKT_BUFFER_8812; /*@default reseved 1 page for the IC type which is undefined.*/
+	struct _RT_BEAMFORMING_INFO *beam_info = &dm->beamforming_info;
+	struct _RT_BEAMFORMEE_ENTRY *p_beam_entry = beam_info->beamformee_entry + idx;
+	void *adapter = dm->adapter;
+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
+	*dm->is_fw_dw_rsvd_page_in_progress = true;
+#endif
+	PHYDM_DBG(dm, DBG_TXBF, "[%s] Start!\n", __func__);
+
+	if (idx == 0)
+		head_page = 0xFE;
+	else
+		head_page = 0xFE;
+
+	phydm_get_hal_def_var_handler_interface(dm, HAL_DEF_TX_PAGE_BOUNDARY, (u8 *)&tx_page_bndy);
+
+	/*Set REG_CR bit 8. DMA beacon by SW.*/
+	u1b_tmp = odm_read_1byte(dm, REG_CR_8812A + 1);
+	odm_write_1byte(dm, REG_CR_8812A + 1, (u1b_tmp | BIT(0)));
+
+	/*Set FWHW_TXQ_CTRL 0x422[6]=0 to tell Hw the packet is not a real beacon frame.*/
+	tmp_reg422 = odm_read_1byte(dm, REG_FWHW_TXQ_CTRL_8812A + 2);
+	odm_write_1byte(dm, REG_FWHW_TXQ_CTRL_8812A + 2, tmp_reg422 & (~BIT(6)));
+
+	if (tmp_reg422 & BIT(6)) {
+		PHYDM_DBG(dm, DBG_TXBF,
+			  "SetBeamformDownloadNDPA_8812(): There is an adapter is sending beacon.\n");
+		is_send_beacon = true;
+	}
+
+	/*TDECTRL[15:8] 0x209[7:0] = 0xF6	Beacon Head for TXDMA*/
+	odm_write_1byte(dm, REG_TDECTRL_8812A + 1, head_page);
+
+	do {
+		/*@Clear beacon valid check bit.*/
+		bcn_valid_reg = odm_read_1byte(dm, REG_TDECTRL_8812A + 2);
+		odm_write_1byte(dm, REG_TDECTRL_8812A + 2, (bcn_valid_reg | BIT(0)));
+
+		/*@download NDPA rsvd page.*/
+		if (p_beam_entry->beamform_entry_cap & BEAMFORMER_CAP_VHT_SU)
+			beamforming_send_vht_ndpa_packet(dm, p_beam_entry->mac_addr, p_beam_entry->aid, p_beam_entry->sound_bw, BEACON_QUEUE);
+		else
+			beamforming_send_ht_ndpa_packet(dm, p_beam_entry->mac_addr, p_beam_entry->sound_bw, BEACON_QUEUE);
+
+		/*@check rsvd page download OK.*/
+		bcn_valid_reg = odm_read_1byte(dm, REG_TDECTRL_8812A + 2);
+		count = 0;
+		while (!(bcn_valid_reg & BIT(0)) && count < 20) {
+			count++;
+			ODM_delay_ms(10);
+			bcn_valid_reg = odm_read_1byte(dm, REG_TDECTRL_8812A + 2);
+		}
+		dl_bcn_count++;
+	} while (!(bcn_valid_reg & BIT(0)) && dl_bcn_count < 5);
+
+	if (!(bcn_valid_reg & BIT(0)))
+		PHYDM_DBG(dm, DBG_TXBF, "%s Download RSVD page failed!\n",
+			  __func__);
+
+	/*TDECTRL[15:8] 0x209[7:0] = 0xF6	Beacon Head for TXDMA*/
+	odm_write_1byte(dm, REG_TDECTRL_8812A + 1, tx_page_bndy);
+
+	/*To make sure that if there exists an adapter which would like to send beacon.*/
+	/*@If exists, the origianl value of 0x422[6] will be 1, we should check this to*/
+	/*prevent from setting 0x422[6] to 0 after download reserved page, or it will cause*/
+	/*the beacon cannot be sent by HW.*/
+	/*@2010.06.23. Added by tynli.*/
+	if (is_send_beacon)
+		odm_write_1byte(dm, REG_FWHW_TXQ_CTRL_8812A + 2, tmp_reg422);
+
+	/*@Do not enable HW DMA BCN or it will cause Pcie interface hang by timing issue. 2011.11.24. by tynli.*/
+	/*@Clear CR[8] or beacon packet will not be send to TxBuf anymore.*/
+	u1b_tmp = odm_read_1byte(dm, REG_CR_8812A + 1);
+	odm_write_1byte(dm, REG_CR_8812A + 1, (u1b_tmp & (~BIT(0))));
+
+	p_beam_entry->beamform_entry_state = BEAMFORMING_ENTRY_STATE_PROGRESSED;
+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
+	*dm->is_fw_dw_rsvd_page_in_progress = false;
+#endif
+}
+
+void hal_txbf_jaguar_fw_txbf_cmd(
+	void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	u8 idx, period0 = 0, period1 = 0;
+	u8 PageNum0 = 0xFF, PageNum1 = 0xFF;
+	u8 u1_tx_bf_parm[3] = {0};
+	struct _RT_BEAMFORMING_INFO *beam_info = &dm->beamforming_info;
+
+	for (idx = 0; idx < BEAMFORMEE_ENTRY_NUM; idx++) {
+		/*@Modified by David*/
+		if (beam_info->beamformee_entry[idx].is_used && beam_info->beamformee_entry[idx].beamform_entry_state == BEAMFORMING_ENTRY_STATE_PROGRESSED) {
+			if (idx == 0) {
+				if (beam_info->beamformee_entry[idx].is_sound)
+					PageNum0 = 0xFE;
+				else
+					PageNum0 = 0xFF; /*stop sounding*/
+				period0 = (u8)(beam_info->beamformee_entry[idx].sound_period);
+			} else if (idx == 1) {
+				if (beam_info->beamformee_entry[idx].is_sound)
+					PageNum1 = 0xFE;
+				else
+					PageNum1 = 0xFF; /*stop sounding*/
+				period1 = (u8)(beam_info->beamformee_entry[idx].sound_period);
+			}
+		}
+	}
+
+	u1_tx_bf_parm[0] = PageNum0;
+	u1_tx_bf_parm[1] = PageNum1;
+	u1_tx_bf_parm[2] = (period1 << 4) | period0;
+	odm_fill_h2c_cmd(dm, PHYDM_H2C_TXBF, 3, u1_tx_bf_parm);
+
+	PHYDM_DBG(dm, DBG_TXBF,
+		  "[%s] PageNum0 = %d period0 = %d, PageNum1 = %d period1 %d\n",
+		  __func__, PageNum0, period0, PageNum1, period1);
+}
+
+void hal_txbf_jaguar_enter(
+	void *dm_void,
+	u8 bfer_bfee_idx)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	u8 i = 0;
+	u8 bfer_idx = (bfer_bfee_idx & 0xF0) >> 4;
+	u8 bfee_idx = (bfer_bfee_idx & 0xF);
+	u32 csi_param;
+	struct _RT_BEAMFORMING_INFO *beamforming_info = &dm->beamforming_info;
+	struct _RT_BEAMFORMEE_ENTRY beamformee_entry;
+	struct _RT_BEAMFORMER_ENTRY beamformer_entry;
+	u16 sta_id = 0;
+
+	PHYDM_DBG(dm, DBG_TXBF, "[%s]Start!\n", __func__);
+
+	hal_txbf_jaguar_rf_mode(dm, beamforming_info);
+
+	if (dm->rf_type == RF_2T2R)
+		odm_set_bb_reg(dm, ODM_REG_CSI_CONTENT_VALUE, MASKDWORD, 0x00000000); /*nc =2*/
+	else
+		odm_set_bb_reg(dm, ODM_REG_CSI_CONTENT_VALUE, MASKDWORD, 0x01081008); /*nc =1*/
+
+	if (beamforming_info->beamformer_su_cnt > 0 && bfer_idx < BEAMFORMER_ENTRY_NUM) {
+		beamformer_entry = beamforming_info->beamformer_entry[bfer_idx];
+
+		/*Sounding protocol control*/
+		odm_write_1byte(dm, REG_SND_PTCL_CTRL_8812A, 0xCB);
+
+		/*@MAC address/Partial AID of Beamformer*/
+		if (bfer_idx == 0) {
+			for (i = 0; i < 6; i++)
+				odm_write_1byte(dm, (REG_BFMER0_INFO_8812A + i), beamformer_entry.mac_addr[i]);
+			/*@CSI report use legacy ofdm so don't need to fill P_AID. */
+			/*platform_efio_write_2byte(adapter, REG_BFMER0_INFO_8812A+6, beamform_entry.P_AID); */
+		} else {
+			for (i = 0; i < 6; i++)
+				odm_write_1byte(dm, (REG_BFMER1_INFO_8812A + i), beamformer_entry.mac_addr[i]);
+			/*@CSI report use legacy ofdm so don't need to fill P_AID.*/
+			/*platform_efio_write_2byte(adapter, REG_BFMER1_INFO_8812A+6, beamform_entry.P_AID);*/
+		}
+
+		/*@CSI report parameters of Beamformee*/
+		if (beamformer_entry.beamform_entry_cap & BEAMFORMEE_CAP_VHT_SU) {
+			if (dm->rf_type == RF_2T2R)
+				csi_param = 0x01090109;
+			else
+				csi_param = 0x01080108;
+		} else {
+			if (dm->rf_type == RF_2T2R)
+				csi_param = 0x03090309;
+			else
+				csi_param = 0x03080308;
+		}
+
+		odm_write_4byte(dm, REG_CSI_RPT_PARAM_BW20_8812A, csi_param);
+		odm_write_4byte(dm, REG_CSI_RPT_PARAM_BW40_8812A, csi_param);
+		odm_write_4byte(dm, REG_CSI_RPT_PARAM_BW80_8812A, csi_param);
+
+		/*Timeout value for MAC to leave NDP_RX_standby_state (60 us, Test chip) (80 us,  MP chip)*/
+		odm_write_1byte(dm, REG_SND_PTCL_CTRL_8812A + 3, 0x50);
+	}
+
+	if (beamforming_info->beamformee_su_cnt > 0 && bfee_idx < BEAMFORMEE_ENTRY_NUM) {
+		beamformee_entry = beamforming_info->beamformee_entry[bfee_idx];
+
+		if (phydm_acting_determine(dm, phydm_acting_as_ibss))
+			sta_id = beamformee_entry.mac_id;
+		else
+			sta_id = beamformee_entry.p_aid;
+
+		/*P_AID of Beamformee & enable NDPA transmission & enable NDPA interrupt*/
+		if (bfee_idx == 0) {
+			odm_write_2byte(dm, REG_TXBF_CTRL_8812A, sta_id);
+			odm_write_1byte(dm, REG_TXBF_CTRL_8812A + 3, odm_read_1byte(dm, REG_TXBF_CTRL_8812A + 3) | BIT(4) | BIT(6) | BIT(7));
+		} else
+			odm_write_2byte(dm, REG_TXBF_CTRL_8812A + 2, sta_id | BIT(12) | BIT(14) | BIT(15));
+
+		/*@CSI report parameters of Beamformee*/
+		if (bfee_idx == 0) {
+			/*@Get BIT24 & BIT25*/
+			u8 tmp = odm_read_1byte(dm, REG_BFMEE_SEL_8812A + 3) & 0x3;
+
+			odm_write_1byte(dm, REG_BFMEE_SEL_8812A + 3, tmp | 0x60);
+			odm_write_2byte(dm, REG_BFMEE_SEL_8812A, sta_id | BIT(9));
+		} else {
+			/*Set BIT25*/
+			odm_write_2byte(dm, REG_BFMEE_SEL_8812A + 2, sta_id | 0xE200);
+		}
+		phydm_beamforming_notify(dm);
+	}
+}
+
+void hal_txbf_jaguar_leave(
+	void *dm_void,
+	u8 idx)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct _RT_BEAMFORMING_INFO *beamforming_info = &dm->beamforming_info;
+	struct _RT_BEAMFORMER_ENTRY beamformer_entry;
+	struct _RT_BEAMFORMEE_ENTRY beamformee_entry;
+
+	if (idx < BEAMFORMER_ENTRY_NUM) {
+		beamformer_entry = beamforming_info->beamformer_entry[idx];
+		beamformee_entry = beamforming_info->beamformee_entry[idx];
+	} else
+		return;
+
+	PHYDM_DBG(dm, DBG_TXBF, "[%s]Start!, IDx = %d\n", __func__, idx);
+
+	/*@Clear P_AID of Beamformee*/
+	/*@Clear MAC address of Beamformer*/
+	/*@Clear Associated Bfmee Sel*/
+
+	if (beamformer_entry.beamform_entry_cap == BEAMFORMING_CAP_NONE) {
+		odm_write_1byte(dm, REG_SND_PTCL_CTRL_8812A, 0xC8);
+		if (idx == 0) {
+			odm_write_4byte(dm, REG_BFMER0_INFO_8812A, 0);
+			odm_write_2byte(dm, REG_BFMER0_INFO_8812A + 4, 0);
+			odm_write_2byte(dm, REG_CSI_RPT_PARAM_BW20_8812A, 0);
+			odm_write_2byte(dm, REG_CSI_RPT_PARAM_BW40_8812A, 0);
+			odm_write_2byte(dm, REG_CSI_RPT_PARAM_BW80_8812A, 0);
+		} else {
+			odm_write_4byte(dm, REG_BFMER1_INFO_8812A, 0);
+			odm_write_2byte(dm, REG_BFMER1_INFO_8812A + 4, 0);
+			odm_write_2byte(dm, REG_CSI_RPT_PARAM_BW20_8812A, 0);
+			odm_write_2byte(dm, REG_CSI_RPT_PARAM_BW40_8812A, 0);
+			odm_write_2byte(dm, REG_CSI_RPT_PARAM_BW80_8812A, 0);
+		}
+	}
+
+	if (beamformee_entry.beamform_entry_cap == BEAMFORMING_CAP_NONE) {
+		hal_txbf_jaguar_rf_mode(dm, beamforming_info);
+		if (idx == 0) {
+			odm_write_2byte(dm, REG_TXBF_CTRL_8812A, 0x0);
+			odm_write_2byte(dm, REG_BFMEE_SEL_8812A, 0);
+		} else {
+			odm_write_2byte(dm, REG_TXBF_CTRL_8812A + 2, odm_read_2byte(dm, REG_TXBF_CTRL_8812A + 2) & 0xF000);
+			odm_write_2byte(dm, REG_BFMEE_SEL_8812A + 2, odm_read_2byte(dm, REG_BFMEE_SEL_8812A + 2) & 0x60);
+		}
+	}
+}
+
+void hal_txbf_jaguar_status(
+	void *dm_void,
+	u8 idx)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	u16 beam_ctrl_val;
+	u32 beam_ctrl_reg;
+	struct _RT_BEAMFORMING_INFO *beam_info = &dm->beamforming_info;
+	struct _RT_BEAMFORMEE_ENTRY beamform_entry = beam_info->beamformee_entry[idx];
+
+	if (phydm_acting_determine(dm, phydm_acting_as_ibss))
+		beam_ctrl_val = beamform_entry.mac_id;
+	else
+		beam_ctrl_val = beamform_entry.p_aid;
+
+	if (idx == 0)
+		beam_ctrl_reg = REG_TXBF_CTRL_8812A;
+	else {
+		beam_ctrl_reg = REG_TXBF_CTRL_8812A + 2;
+		beam_ctrl_val |= BIT(12) | BIT(14) | BIT(15);
+	}
+
+	if (beamform_entry.beamform_entry_state == BEAMFORMING_ENTRY_STATE_PROGRESSED && beam_info->apply_v_matrix == true) {
+		if (beamform_entry.sound_bw == CHANNEL_WIDTH_20)
+			beam_ctrl_val |= BIT(9);
+		else if (beamform_entry.sound_bw == CHANNEL_WIDTH_40)
+			beam_ctrl_val |= (BIT(9) | BIT(10));
+		else if (beamform_entry.sound_bw == CHANNEL_WIDTH_80)
+			beam_ctrl_val |= (BIT(9) | BIT(10) | BIT(11));
+	} else
+		beam_ctrl_val &= ~(BIT(9) | BIT(10) | BIT(11));
+
+	PHYDM_DBG(dm, DBG_TXBF, "[%s] beam_ctrl_val = 0x%x!\n", __func__,
+		  beam_ctrl_val);
+
+	odm_write_2byte(dm, beam_ctrl_reg, beam_ctrl_val);
+}
+
+void hal_txbf_jaguar_fw_txbf(
+	void *dm_void,
+	u8 idx)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct _RT_BEAMFORMING_INFO *beam_info = &dm->beamforming_info;
+	struct _RT_BEAMFORMEE_ENTRY *p_beam_entry = beam_info->beamformee_entry + idx;
+
+	PHYDM_DBG(dm, DBG_TXBF, "[%s] Start!\n", __func__);
+
+	if (p_beam_entry->beamform_entry_state == BEAMFORMING_ENTRY_STATE_PROGRESSING)
+		hal_txbf_jaguar_download_ndpa(dm, idx);
+
+	hal_txbf_jaguar_fw_txbf_cmd(dm);
+}
+
+void hal_txbf_jaguar_patch(
+	void *dm_void,
+	u8 operation)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct _RT_BEAMFORMING_INFO *beam_info = &dm->beamforming_info;
+
+	PHYDM_DBG(dm, DBG_TXBF, "[%s] Start!\n", __func__);
+
+	if (beam_info->beamform_cap == BEAMFORMING_CAP_NONE)
+		return;
+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
+	if (operation == SCAN_OPT_BACKUP_BAND0)
+		odm_write_1byte(dm, REG_SND_PTCL_CTRL_8812A, 0xC8);
+	else if (operation == SCAN_OPT_RESTORE)
+		odm_write_1byte(dm, REG_SND_PTCL_CTRL_8812A, 0xCB);
+#endif
+}
+
+void hal_txbf_jaguar_clk_8812a(
+	void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	u16 u2btmp;
+	u8 count = 0, u1btmp;
+	void *adapter = dm->adapter;
+
+	PHYDM_DBG(dm, DBG_TXBF, "[%s] Start!\n", __func__);
+
+	if (*dm->is_scan_in_process) {
+		PHYDM_DBG(dm, DBG_TXBF, "[%s] return by Scan\n", __func__);
+		return;
+	}
+#if DEV_BUS_TYPE == RT_PCI_INTERFACE
+	/*Stop PCIe TxDMA*/
+	odm_write_1byte(dm, REG_PCIE_CTRL_REG_8812A + 1, 0xFE);
+#endif
+
+/*Stop Usb TxDMA*/
+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
+	RT_DISABLE_FUNC((PADAPTER)adapter, DF_TX_BIT);
+	PlatformReturnAllPendingTxPackets(adapter);
+#else
+	rtw_write_port_cancel(adapter);
+#endif
+
+	/*Wait TXFF empty*/
+	for (count = 0; count < 100; count++) {
+		u2btmp = odm_read_2byte(dm, REG_TXPKT_EMPTY_8812A);
+		u2btmp = u2btmp & 0xfff;
+		if (u2btmp != 0xfff) {
+			ODM_delay_ms(10);
+			continue;
+		} else
+			break;
+	}
+
+	/*TX pause*/
+	odm_write_1byte(dm, REG_TXPAUSE_8812A, 0xFF);
+
+	/*Wait TX state Machine OK*/
+	for (count = 0; count < 100; count++) {
+		if (odm_read_4byte(dm, REG_SCH_TXCMD_8812A) != 0)
+			continue;
+		else
+			break;
+	}
+
+	/*Stop RX DMA path*/
+	u1btmp = odm_read_1byte(dm, REG_RXDMA_CONTROL_8812A);
+	odm_write_1byte(dm, REG_RXDMA_CONTROL_8812A, u1btmp | BIT(2));
+
+	for (count = 0; count < 100; count++) {
+		u1btmp = odm_read_1byte(dm, REG_RXDMA_CONTROL_8812A);
+		if (u1btmp & BIT(1))
+			break;
+		else
+			ODM_delay_ms(10);
+	}
+
+	/*@Disable clock*/
+	odm_write_1byte(dm, REG_SYS_CLKR_8812A + 1, 0xf0);
+	/*@Disable 320M*/
+	odm_write_1byte(dm, REG_AFE_PLL_CTRL_8812A + 3, 0x8);
+	/*@Enable 320M*/
+	odm_write_1byte(dm, REG_AFE_PLL_CTRL_8812A + 3, 0xa);
+	/*@Enable clock*/
+	odm_write_1byte(dm, REG_SYS_CLKR_8812A + 1, 0xfc);
+
+	/*Release Tx pause*/
+	odm_write_1byte(dm, REG_TXPAUSE_8812A, 0);
+
+	/*@Enable RX DMA path*/
+	u1btmp = odm_read_1byte(dm, REG_RXDMA_CONTROL_8812A);
+	odm_write_1byte(dm, REG_RXDMA_CONTROL_8812A, u1btmp & (~BIT(2)));
+#if DEV_BUS_TYPE == RT_PCI_INTERFACE
+	/*@Enable PCIe TxDMA*/
+	odm_write_1byte(dm, REG_PCIE_CTRL_REG_8812A + 1, 0);
+#endif
+	/*Start Usb TxDMA*/
+	RT_ENABLE_FUNC((PADAPTER)adapter, DF_TX_BIT);
+}
+
+#endif
+
+#endif
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/txbf/haltxbfjaguar.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/txbf/haltxbfjaguar.h
--- linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/txbf/haltxbfjaguar.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/txbf/haltxbfjaguar.h	2020-04-10 16:35:06.836661001 +0300
@@ -0,0 +1,78 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017  Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * The full GNU General Public License is included in this distribution in the
+ * file called LICENSE.
+ *
+ * Contact Information:
+ * wlanfae <wlanfae@realtek.com>
+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
+ * Hsinchu 300, Taiwan.
+ *
+ * Larry Finger <Larry.Finger@lwfinger.net>
+ *
+ *****************************************************************************/
+#ifndef __HAL_TXBF_JAGUAR_H__
+#define __HAL_TXBF_JAGUAR_H__
+#if ((RTL8812A_SUPPORT == 1) || (RTL8821A_SUPPORT == 1))
+#if (BEAMFORMING_SUPPORT == 1)
+
+void hal_txbf_8812a_set_ndpa_rate(
+	void *dm_void,
+	u8 BW,
+	u8 rate);
+
+void hal_txbf_jaguar_enter(
+	void *dm_void,
+	u8 idx);
+
+void hal_txbf_jaguar_leave(
+	void *dm_void,
+	u8 idx);
+
+void hal_txbf_jaguar_status(
+	void *dm_void,
+	u8 idx);
+
+void hal_txbf_jaguar_fw_txbf(
+	void *dm_void,
+	u8 idx);
+
+void hal_txbf_jaguar_patch(
+	void *dm_void,
+	u8 operation);
+
+void hal_txbf_jaguar_clk_8812a(
+	void *dm_void);
+#else
+
+#define hal_txbf_8812a_set_ndpa_rate(dm_void, BW, rate)
+#define hal_txbf_jaguar_enter(dm_void, idx)
+#define hal_txbf_jaguar_leave(dm_void, idx)
+#define hal_txbf_jaguar_status(dm_void, idx)
+#define hal_txbf_jaguar_fw_txbf(dm_void, idx)
+#define hal_txbf_jaguar_patch(dm_void, operation)
+#define hal_txbf_jaguar_clk_8812a(dm_void)
+#endif
+#else
+
+#define hal_txbf_8812a_set_ndpa_rate(dm_void, BW, rate)
+#define hal_txbf_jaguar_enter(dm_void, idx)
+#define hal_txbf_jaguar_leave(dm_void, idx)
+#define hal_txbf_jaguar_status(dm_void, idx)
+#define hal_txbf_jaguar_fw_txbf(dm_void, idx)
+#define hal_txbf_jaguar_patch(dm_void, operation)
+#define hal_txbf_jaguar_clk_8812a(dm_void)
+#endif
+
+#endif /*  @#ifndef __HAL_TXBF_JAGUAR_H__ */
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/txbf/phydm_hal_txbf_api.c linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/txbf/phydm_hal_txbf_api.c
--- linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/txbf/phydm_hal_txbf_api.c	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/txbf/phydm_hal_txbf_api.c	2020-04-10 16:35:06.836661001 +0300
@@ -0,0 +1,183 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+
+#include "mp_precomp.h"
+#include "phydm_precomp.h"
+
+#if (defined(CONFIG_BB_TXBF_API))
+#if (RTL8822B_SUPPORT == 1 || RTL8192F_SUPPORT == 1 ||\
+	RTL8822C_SUPPORT == 1 || RTL8198F_SUPPORT == 1 || RTL8814B_SUPPORT == 1)
+/*@Add by YuChen for 8822B MU-MIMO API*/
+
+/*this function is only used for BFer*/
+u8 phydm_get_ndpa_rate(void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	u8 ndpa_rate = ODM_RATE6M;
+
+	if (dm->rssi_min >= 30) /*@link RSSI > 30%*/
+		ndpa_rate = ODM_RATE24M;
+	else if (dm->rssi_min <= 25)
+		ndpa_rate = ODM_RATE6M;
+
+	PHYDM_DBG(dm, DBG_TXBF, "[%s] ndpa_rate = 0x%x\n", __func__, ndpa_rate);
+
+	return ndpa_rate;
+}
+
+/*this function is only used for BFer*/
+u8 phydm_get_beamforming_sounding_info(void *dm_void, u16 *throughput,
+				       u8 total_bfee_num, u8 *tx_rate)
+{
+	u8 idx = 0;
+	u8 snddecision = 0xff;
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+
+	for (idx = 0; idx < total_bfee_num; idx++) {
+		if (dm->support_ic_type & (ODM_RTL8814A)) {
+			if ((tx_rate[idx] >= ODM_RATEVHTSS3MCS7 &&
+			     tx_rate[idx] <= ODM_RATEVHTSS3MCS9))
+				snddecision = snddecision & ~(1 << idx);
+		} else if (dm->support_ic_type & (ODM_RTL8822B | ODM_RTL8822C |
+			   ODM_RTL8812 | ODM_RTL8192F)) {
+			if ((tx_rate[idx] >= ODM_RATEVHTSS2MCS7 &&
+			     tx_rate[idx] <= ODM_RATEVHTSS2MCS9))
+				snddecision = snddecision & ~(1 << idx);
+		} else if (dm->support_ic_type & (ODM_RTL8814B)) {
+			if ((tx_rate[idx] >= ODM_RATEVHTSS4MCS7 &&
+			     tx_rate[idx] <= ODM_RATEVHTSS4MCS9))
+				snddecision = snddecision & ~(1 << idx);
+		}
+	}
+
+	for (idx = 0; idx < total_bfee_num; idx++) {
+		if (throughput[idx] <= 10)
+			snddecision = snddecision & ~(1 << idx);
+	}
+
+	PHYDM_DBG(dm, DBG_TXBF, "[%s] soundingdecision = 0x%x\n", __func__,
+		  snddecision);
+
+	return snddecision;
+}
+
+/*this function is only used for BFer*/
+u8 phydm_get_mu_bfee_snding_decision(void *dm_void, u16 throughput)
+{
+	u8 snding_score = 0;
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+
+	/*throughput unit is Mbps*/
+	if (throughput >= 500)
+		snding_score = 100;
+	else if (throughput >= 450)
+		snding_score = 90;
+	else if (throughput >= 400)
+		snding_score = 80;
+	else if (throughput >= 350)
+		snding_score = 70;
+	else if (throughput >= 300)
+		snding_score = 60;
+	else if (throughput >= 250)
+		snding_score = 50;
+	else if (throughput >= 200)
+		snding_score = 40;
+	else if (throughput >= 150)
+		snding_score = 30;
+	else if (throughput >= 100)
+		snding_score = 20;
+	else if (throughput >= 50)
+		snding_score = 10;
+	else
+		snding_score = 0;
+
+	PHYDM_DBG(dm, DBG_TXBF, "[%s] snding_score = 0x%x\n", __func__,
+		  snding_score);
+
+	return snding_score;
+}
+
+#endif
+#if (DM_ODM_SUPPORT_TYPE != ODM_AP)
+u8 beamforming_get_htndp_tx_rate(void *dm_void, u8 bfer_str_num)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	u8 nr_index = 0;
+	u8 ndp_tx_rate;
+/*@Find nr*/
+#if (RTL8814A_SUPPORT == 1)
+	if (dm->support_ic_type & ODM_RTL8814A)
+		nr_index = tx_bf_nr(hal_txbf_8814a_get_ntx(dm), bfer_str_num);
+	else
+#endif
+		nr_index = tx_bf_nr(1, bfer_str_num);
+
+	switch (nr_index) {
+	case 1:
+		ndp_tx_rate = ODM_MGN_MCS8;
+		break;
+
+	case 2:
+		ndp_tx_rate = ODM_MGN_MCS16;
+		break;
+
+	case 3:
+		ndp_tx_rate = ODM_MGN_MCS24;
+		break;
+
+	default:
+		ndp_tx_rate = ODM_MGN_MCS8;
+		break;
+	}
+
+	return ndp_tx_rate;
+}
+
+u8 beamforming_get_vht_ndp_tx_rate(void *dm_void, u8 bfer_str_num)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	u8 nr_index = 0;
+	u8 ndp_tx_rate;
+/*@Find nr*/
+#if (RTL8814A_SUPPORT == 1)
+	if (dm->support_ic_type & ODM_RTL8814A)
+		nr_index = tx_bf_nr(hal_txbf_8814a_get_ntx(dm), bfer_str_num);
+	else
+#endif
+		nr_index = tx_bf_nr(1, bfer_str_num);
+
+	switch (nr_index) {
+	case 1:
+		ndp_tx_rate = ODM_MGN_VHT2SS_MCS0;
+		break;
+
+	case 2:
+		ndp_tx_rate = ODM_MGN_VHT3SS_MCS0;
+		break;
+
+	case 3:
+		ndp_tx_rate = ODM_MGN_VHT4SS_MCS0;
+		break;
+
+	default:
+		ndp_tx_rate = ODM_MGN_VHT2SS_MCS0;
+		break;
+	}
+
+	return ndp_tx_rate;
+}
+#endif
+
+#endif
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/txbf/phydm_hal_txbf_api.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/txbf/phydm_hal_txbf_api.h
--- linux-5.6.3/3rdparty/rtl8821ce/hal/phydm/txbf/phydm_hal_txbf_api.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/phydm/txbf/phydm_hal_txbf_api.h	2020-04-10 16:35:06.836661001 +0300
@@ -0,0 +1,63 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017  Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * The full GNU General Public License is included in this distribution in the
+ * file called LICENSE.
+ *
+ * Contact Information:
+ * wlanfae <wlanfae@realtek.com>
+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
+ * Hsinchu 300, Taiwan.
+ *
+ * Larry Finger <Larry.Finger@lwfinger.net>
+ *
+ *****************************************************************************/
+#ifndef __PHYDM_HAL_TXBF_API_H__
+#define __PHYDM_HAL_TXBF_API_H__
+
+#if (defined(CONFIG_BB_TXBF_API))
+
+#if (DM_ODM_SUPPORT_TYPE != ODM_AP)
+#if defined(DM_ODM_CE_MAC80211)
+#define tx_bf_nr(a, b) ({	\
+	u8 __tx_bf_nr_a = (a);	\
+	u8 __tx_bf_nr_b = (b);	\
+	((__tx_bf_nr_a > __tx_bf_nr_b) ? (__tx_bf_nr_b) : (__tx_bf_nr_a)); })
+#else
+#define tx_bf_nr(a, b) ((a > b) ? (b) : (a))
+#endif
+
+u8 beamforming_get_htndp_tx_rate(void *dm_void, u8 bfer_str_num);
+
+u8 beamforming_get_vht_ndp_tx_rate(void *dm_void, u8 bfer_str_num);
+
+#endif
+
+#if (RTL8822B_SUPPORT == 1 || RTL8822C_SUPPORT == 1 || RTL8192F_SUPPORT == 1 ||\
+	RTL8814B_SUPPORT == 1 || RTL8198F_SUPPORT == 1)
+u8 phydm_get_beamforming_sounding_info(void *dm_void, u16 *throughput,
+				       u8 total_bfee_num, u8 *tx_rate);
+
+u8 phydm_get_ndpa_rate(void *dm_void);
+
+u8 phydm_get_mu_bfee_snding_decision(void *dm_void, u16 throughput);
+
+#else
+#define phydm_get_beamforming_sounding_info(dm, tp, bfee_num, rate) 0
+#define phydm_get_ndpa_rate(dm)
+#define phydm_get_mu_bfee_snding_decision(dm, tp)
+
+#endif
+
+#endif
+#endif
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/rtl8821c/hal8821c_fw.c linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/rtl8821c/hal8821c_fw.c
--- linux-5.6.3/3rdparty/rtl8821ce/hal/rtl8821c/hal8821c_fw.c	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/rtl8821c/hal8821c_fw.c	2020-04-10 16:35:06.842661282 +0300
@@ -0,0 +1,53340 @@
+/******************************************************************************
+*
+* Copyright(c) 2012 - 2017 Realtek Corporation.
+*
+* This program is free software; you can redistribute it and/or modify it
+* under the terms of version 2 of the GNU General Public License as
+* published by the Free Software Foundation.
+*
+* This program is distributed in the hope that it will be useful, but WITHOUT
+* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+* more details.
+*
+******************************************************************************/
+
+#ifdef CONFIG_RTL8821C
+
+#include "drv_types.h"
+
+#ifdef LOAD_FW_HEADER_FROM_DRIVER
+
+#if (defined(CONFIG_AP_WOWLAN) || (DM_ODM_SUPPORT_TYPE & (ODM_AP)))
+
+u8 array_mp_8821c_fw_ap[] = {
+0x21, 0x88, 0x00, 0x00, 0x14, 0x00, 0x01, 0x00,
+0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00,
+0x07, 0x01, 0x0E, 0x33, 0xE2, 0x07, 0x00, 0x00,
+0x18, 0x00, 0x00, 0x00, 0x0C, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x20, 0x80, 0x38, 0x7D, 0x00, 0x00,
+0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x40, 0xC3, 0x00, 0x00, 0x50, 0x7D, 0x00, 0x00,
+0x00, 0x00, 0x10, 0x80, 0x00, 0x00, 0x03, 0x80,
+0x00, 0x00, 0x04, 0x04, 0x08, 0x08, 0x08, 0x08,
+0x0C, 0x0C, 0x0C, 0x0C, 0x0C, 0x0C, 0x0C, 0x0C,
+0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10,
+0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10,
+0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14,
+0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14,
+0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14,
+0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14,
+0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18,
+0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18,
+0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18,
+0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18,
+0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18,
+0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18,
+0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18,
+0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18,
+0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C,
+0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C,
+0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C,
+0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C,
+0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C,
+0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C,
+0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C,
+0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C,
+0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C,
+0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C,
+0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C,
+0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C,
+0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C,
+0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C,
+0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C,
+0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x03, 0x00, 0x01, 0xFE, 0x03, 0x01, 0x01, 0xFE,
+0x03, 0x02, 0x01, 0xFE, 0x03, 0x03, 0x01, 0xFE,
+0x03, 0x04, 0x01, 0xFE, 0x03, 0x05, 0x01, 0xFE,
+0x03, 0x06, 0x01, 0xFE, 0x03, 0x07, 0x01, 0xFE,
+0x06, 0x00, 0x00, 0x00, 0x05, 0x00, 0x00, 0x00,
+0x01, 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00,
+0x00, 0x01, 0x10, 0x00, 0x01, 0x00, 0x03, 0x80,
+0xA1, 0x01, 0x03, 0x80, 0xA1, 0x01, 0x03, 0x80,
+0xF5, 0x5A, 0x03, 0x80, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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+0xD0, 0x67, 0x00, 0x18, 0xF8, 0xE3, 0x0E, 0x6B,
+0x6B, 0xEB, 0x4C, 0xEB, 0x00, 0x6C, 0x01, 0x6D,
+0xD0, 0x67, 0x05, 0x6F, 0x6D, 0xEF, 0x0F, 0x10,
+0x10, 0xF0, 0x24, 0x6A, 0x96, 0xF4, 0x18, 0x9A,
+0x00, 0x6C, 0x01, 0x6D, 0xD0, 0x67, 0x00, 0x18,
+0xF8, 0xE3, 0x02, 0x6F, 0xEB, 0xEF, 0x00, 0x6C,
+0x01, 0x6D, 0xD0, 0x67, 0x4C, 0xEF, 0x00, 0x18,
+0x0B, 0xE4, 0x07, 0x97, 0x06, 0x91, 0x05, 0x90,
+0x04, 0x63, 0x00, 0xEF, 0x10, 0xF0, 0x21, 0x6A,
+0x84, 0xF4, 0x08, 0x4A, 0x30, 0xF0, 0x20, 0x6B,
+0x8E, 0xF6, 0x48, 0xDB, 0x10, 0xF0, 0x21, 0x6A,
+0x24, 0xF5, 0x00, 0x4A, 0x30, 0xF0, 0x20, 0x6B,
+0x8E, 0xF6, 0x4C, 0xDB, 0x10, 0xF0, 0x21, 0x6A,
+0xC4, 0xF5, 0x14, 0x4A, 0x30, 0xF0, 0x20, 0x6B,
+0x8E, 0xF6, 0x50, 0xDB, 0x10, 0xF0, 0x21, 0x6A,
+0x24, 0xF6, 0x08, 0x4A, 0x30, 0xF0, 0x20, 0x6B,
+0x8E, 0xF6, 0x54, 0xDB, 0x10, 0xF0, 0x21, 0x6A,
+0x64, 0xF6, 0x04, 0x4A, 0x30, 0xF0, 0x20, 0x6B,
+0x8E, 0xF6, 0x58, 0xDB, 0x10, 0xF0, 0x21, 0x6A,
+0xE4, 0xF6, 0x00, 0x4A, 0x30, 0xF0, 0x20, 0x6B,
+0x8E, 0xF6, 0x5C, 0xDB, 0x10, 0xF0, 0x21, 0x6A,
+0xE4, 0xF7, 0x18, 0x4A, 0x30, 0xF0, 0x20, 0x6B,
+0xAE, 0xF6, 0x40, 0xDB, 0x10, 0xF0, 0x21, 0x6A,
+0x65, 0xF1, 0x14, 0x4A, 0x30, 0xF0, 0x20, 0x6B,
+0xAE, 0xF6, 0x44, 0xDB, 0x10, 0xF0, 0x21, 0x6A,
+0x45, 0xF2, 0x14, 0x4A, 0x30, 0xF0, 0x20, 0x6B,
+0xAE, 0xF6, 0x48, 0xDB, 0x10, 0xF0, 0x21, 0x6A,
+0x45, 0xF3, 0x08, 0x4A, 0x30, 0xF0, 0x20, 0x6B,
+0xAE, 0xF6, 0x4C, 0xDB, 0x10, 0xF0, 0x21, 0x6A,
+0xC5, 0xF5, 0x10, 0x4A, 0x30, 0xF0, 0x20, 0x6B,
+0xAE, 0xF6, 0x50, 0xDB, 0x10, 0xF0, 0x21, 0x6A,
+0xA5, 0xF7, 0x14, 0x4A, 0x30, 0xF0, 0x20, 0x6B,
+0xAE, 0xF6, 0x54, 0xDB, 0x10, 0xF0, 0x21, 0x6A,
+0xA5, 0xF7, 0x18, 0x4A, 0x30, 0xF0, 0x20, 0x6B,
+0xAE, 0xF6, 0x58, 0xDB, 0x10, 0xF0, 0x21, 0x6A,
+0x06, 0xF1, 0x18, 0x4A, 0x30, 0xF0, 0x20, 0x6B,
+0xAE, 0xF6, 0x5C, 0xDB, 0x10, 0xF0, 0x21, 0x6A,
+0xC6, 0xF1, 0x0C, 0x4A, 0x30, 0xF0, 0x20, 0x6B,
+0xCE, 0xF6, 0x40, 0xDB, 0x20, 0xE8, 0x00, 0x65,
+0x46, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+};
+
+u32 array_length_mp_8821c_fw_ap = 114208;
+
+#endif /*defined(CONFIG_AP_WOWLAN) || (DM_ODM_SUPPORT_TYPE & (ODM_AP))*/
+
+#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN)) || (DM_ODM_SUPPORT_TYPE & (ODM_CE))
+
+u8 array_mp_8821c_fw_nic[] = {
+0x21, 0x88, 0x00, 0x00, 0x14, 0x00, 0x01, 0x00,
+0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00,
+0x07, 0x01, 0x0E, 0x32, 0xE2, 0x07, 0x00, 0x00,
+0x18, 0x00, 0x00, 0x00, 0x0C, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x20, 0x80, 0xE0, 0x7C, 0x00, 0x00,
+0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00,
+0xC8, 0xFF, 0x00, 0x00, 0x90, 0x9C, 0x00, 0x00,
+0x00, 0x00, 0x10, 0x80, 0x00, 0x00, 0x03, 0x80,
+0x00, 0x00, 0x04, 0x04, 0x08, 0x08, 0x08, 0x08,
+0x0C, 0x0C, 0x0C, 0x0C, 0x0C, 0x0C, 0x0C, 0x0C,
+0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10,
+0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10,
+0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14,
+0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14,
+0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14,
+0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14,
+0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18,
+0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18,
+0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18,
+0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18,
+0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18,
+0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18,
+0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18,
+0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18,
+0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C,
+0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C,
+0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C,
+0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C,
+0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C,
+0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C,
+0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C,
+0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C,
+0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C,
+0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C,
+0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C,
+0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C,
+0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C,
+0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C,
+0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C,
+0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x03, 0x00, 0x01, 0xFE, 0x03, 0x01, 0x01, 0xFE,
+0x03, 0x02, 0x01, 0xFE, 0x03, 0x03, 0x01, 0xFE,
+0x03, 0x04, 0x01, 0xFE, 0x03, 0x05, 0x01, 0xFE,
+0x03, 0x06, 0x01, 0xFE, 0x03, 0x07, 0x01, 0xFE,
+0x06, 0x00, 0x00, 0x00, 0x05, 0x00, 0x00, 0x00,
+0x01, 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00,
+0x00, 0x01, 0x10, 0x00, 0x01, 0x00, 0x03, 0x80,
+0xA1, 0x01, 0x03, 0x80, 0xA1, 0x01, 0x03, 0x80,
+0xD1, 0x6F, 0x03, 0x80, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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+0xDE, 0xF0, 0x00, 0x9A, 0x00, 0x6C, 0x01, 0x6D,
+0xD0, 0x67, 0x00, 0x18, 0x46, 0xEA, 0x0E, 0x6B,
+0x6B, 0xEB, 0x4C, 0xEB, 0x00, 0x6C, 0x01, 0x6D,
+0xD0, 0x67, 0x05, 0x6F, 0x6D, 0xEF, 0x0F, 0x10,
+0x10, 0xF0, 0x24, 0x6A, 0xDE, 0xF0, 0x00, 0x9A,
+0x00, 0x6C, 0x01, 0x6D, 0xD0, 0x67, 0x00, 0x18,
+0x46, 0xEA, 0x02, 0x6F, 0xEB, 0xEF, 0x00, 0x6C,
+0x01, 0x6D, 0xD0, 0x67, 0x4C, 0xEF, 0x00, 0x18,
+0x59, 0xEA, 0x07, 0x97, 0x06, 0x91, 0x05, 0x90,
+0x04, 0x63, 0x00, 0xEF, 0x10, 0xF0, 0x21, 0x6A,
+0x84, 0xF4, 0x08, 0x4A, 0x30, 0xF0, 0x20, 0x6B,
+0x8E, 0xF6, 0x48, 0xDB, 0x10, 0xF0, 0x21, 0x6A,
+0x24, 0xF5, 0x00, 0x4A, 0x30, 0xF0, 0x20, 0x6B,
+0x8E, 0xF6, 0x4C, 0xDB, 0x10, 0xF0, 0x21, 0x6A,
+0xC4, 0xF5, 0x14, 0x4A, 0x30, 0xF0, 0x20, 0x6B,
+0x8E, 0xF6, 0x50, 0xDB, 0x10, 0xF0, 0x21, 0x6A,
+0x24, 0xF6, 0x08, 0x4A, 0x30, 0xF0, 0x20, 0x6B,
+0x8E, 0xF6, 0x54, 0xDB, 0x10, 0xF0, 0x21, 0x6A,
+0x64, 0xF6, 0x04, 0x4A, 0x30, 0xF0, 0x20, 0x6B,
+0x8E, 0xF6, 0x58, 0xDB, 0x10, 0xF0, 0x21, 0x6A,
+0xE4, 0xF6, 0x00, 0x4A, 0x30, 0xF0, 0x20, 0x6B,
+0x8E, 0xF6, 0x5C, 0xDB, 0x10, 0xF0, 0x21, 0x6A,
+0xE4, 0xF7, 0x18, 0x4A, 0x30, 0xF0, 0x20, 0x6B,
+0xAE, 0xF6, 0x40, 0xDB, 0x10, 0xF0, 0x21, 0x6A,
+0x65, 0xF1, 0x14, 0x4A, 0x30, 0xF0, 0x20, 0x6B,
+0xAE, 0xF6, 0x44, 0xDB, 0x10, 0xF0, 0x21, 0x6A,
+0x45, 0xF2, 0x14, 0x4A, 0x30, 0xF0, 0x20, 0x6B,
+0xAE, 0xF6, 0x48, 0xDB, 0x10, 0xF0, 0x21, 0x6A,
+0x45, 0xF3, 0x08, 0x4A, 0x30, 0xF0, 0x20, 0x6B,
+0xAE, 0xF6, 0x4C, 0xDB, 0x10, 0xF0, 0x21, 0x6A,
+0xC5, 0xF5, 0x10, 0x4A, 0x30, 0xF0, 0x20, 0x6B,
+0xAE, 0xF6, 0x50, 0xDB, 0x10, 0xF0, 0x21, 0x6A,
+0xA5, 0xF7, 0x14, 0x4A, 0x30, 0xF0, 0x20, 0x6B,
+0xAE, 0xF6, 0x54, 0xDB, 0x10, 0xF0, 0x21, 0x6A,
+0xA5, 0xF7, 0x18, 0x4A, 0x30, 0xF0, 0x20, 0x6B,
+0xAE, 0xF6, 0x58, 0xDB, 0x10, 0xF0, 0x21, 0x6A,
+0x06, 0xF1, 0x18, 0x4A, 0x30, 0xF0, 0x20, 0x6B,
+0xAE, 0xF6, 0x5C, 0xDB, 0x10, 0xF0, 0x21, 0x6A,
+0xC6, 0xF1, 0x0C, 0x4A, 0x30, 0xF0, 0x20, 0x6B,
+0xCE, 0xF6, 0x40, 0xDB, 0x20, 0xE8, 0x00, 0x65,
+0xDC, 0x12, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+};
+
+u32 array_length_mp_8821c_fw_nic = 137616;
+
+u8 array_mp_8821c_fw_spic[] = {
+0x21, 0x88, 0x00, 0x00, 0x14, 0x00, 0x01, 0x00,
+0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00,
+0x07, 0x01, 0x0E, 0x34, 0xE2, 0x07, 0x00, 0x00,
+0x18, 0x00, 0x00, 0x00, 0x0C, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x20, 0x80, 0xB8, 0x7C, 0x00, 0x00,
+0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00,
+0xA0, 0x7B, 0x00, 0x00, 0xB0, 0x1D, 0x00, 0x00,
+0x00, 0x00, 0x10, 0x80, 0x00, 0x00, 0x03, 0x80,
+0x00, 0x00, 0x04, 0x04, 0x08, 0x08, 0x08, 0x08,
+0x0C, 0x0C, 0x0C, 0x0C, 0x0C, 0x0C, 0x0C, 0x0C,
+0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10,
+0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10,
+0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14,
+0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14,
+0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14,
+0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14,
+0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18,
+0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18,
+0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18,
+0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18,
+0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18,
+0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18,
+0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18,
+0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18,
+0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C,
+0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C,
+0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C,
+0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C,
+0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C,
+0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C,
+0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C,
+0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C,
+0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C,
+0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C,
+0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C,
+0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C,
+0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C,
+0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C,
+0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C,
+0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x03, 0x00, 0x01, 0xFE, 0x03, 0x01, 0x01, 0xFE,
+0x03, 0x02, 0x01, 0xFE, 0x03, 0x03, 0x01, 0xFE,
+0x03, 0x04, 0x01, 0xFE, 0x03, 0x05, 0x01, 0xFE,
+0x03, 0x06, 0x01, 0xFE, 0x03, 0x07, 0x01, 0xFE,
+0x06, 0x00, 0x00, 0x00, 0x05, 0x00, 0x00, 0x00,
+0x01, 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00,
+0x00, 0x01, 0x10, 0x00, 0x01, 0x00, 0x03, 0x80,
+0xAD, 0x01, 0x03, 0x80, 0xAD, 0x01, 0x03, 0x80,
+0xA5, 0x37, 0x03, 0x80, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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+0x10, 0xF0, 0x23, 0x6A, 0x4F, 0xF1, 0x54, 0x9A,
+0xC8, 0x36, 0x01, 0x6D, 0x4D, 0xEE, 0x30, 0xF0,
+0x20, 0x6A, 0xCE, 0xF4, 0x70, 0x9A, 0xED, 0xEE,
+0xA1, 0xF0, 0x0C, 0x6C, 0xAB, 0xED, 0x40, 0xEB,
+0x30, 0xF0, 0x20, 0x6B, 0xCE, 0xF4, 0x50, 0x9B,
+0x10, 0xF0, 0x23, 0x6B, 0xAF, 0xF0, 0xA8, 0x9B,
+0xC1, 0xF0, 0x04, 0x6C, 0x01, 0x6E, 0x40, 0xEA,
+0x01, 0xF4, 0x01, 0x6A, 0x4B, 0xEA, 0x2C, 0xEA,
+0x00, 0xF4, 0x00, 0x6B, 0x6D, 0xEA, 0x48, 0x10,
+0x01, 0x6D, 0xA1, 0xF0, 0x0C, 0x6C, 0xAB, 0xED,
+0x00, 0x18, 0xC4, 0xD5, 0x10, 0xF0, 0x23, 0x6B,
+0x4F, 0xF1, 0x78, 0x9B, 0x30, 0xF0, 0x20, 0x68,
+0x01, 0x6D, 0x4C, 0xEB, 0x10, 0xF0, 0x23, 0x6A,
+0xCE, 0xF4, 0xF0, 0x98, 0xA1, 0xF0, 0x0C, 0x6C,
+0xAB, 0xED, 0x4F, 0xF1, 0xDC, 0x9A, 0x17, 0x10,
+0x01, 0x6D, 0xA1, 0xF0, 0x0C, 0x6C, 0xAB, 0xED,
+0x00, 0x18, 0xC4, 0xD5, 0x10, 0xF0, 0x23, 0x6B,
+0x4F, 0xF1, 0x78, 0x9B, 0x30, 0xF0, 0x20, 0x68,
+0xCE, 0xF4, 0xF0, 0x98, 0x4C, 0xEB, 0x10, 0xF0,
+0x23, 0x6A, 0x6F, 0xF1, 0xC0, 0x9A, 0x01, 0x6D,
+0xA1, 0xF0, 0x0C, 0x6C, 0xAB, 0xED, 0x6D, 0xEE,
+0x40, 0xEF, 0x10, 0xF0, 0x23, 0x6B, 0xAF, 0xF0,
+0xA8, 0x9B, 0xCE, 0xF4, 0x50, 0x98, 0xC1, 0xF0,
+0x04, 0x6C, 0x00, 0x6E, 0x40, 0xEA, 0x10, 0xF0,
+0x23, 0x6B, 0xCE, 0xF4, 0x50, 0x98, 0x6F, 0xF0,
+0xA8, 0x9B, 0xC1, 0xF0, 0x08, 0x6C, 0x01, 0x6E,
+0x40, 0xEA, 0x01, 0xF4, 0x00, 0x6A, 0x2D, 0xEA,
+0x04, 0xD2, 0x10, 0xF0, 0x23, 0x6A, 0x0A, 0x94,
+0x0F, 0xF1, 0xF8, 0x9A, 0x00, 0x6D, 0x18, 0x6E,
+0x01, 0x49, 0x80, 0x18, 0xD4, 0x04, 0x00, 0x6C,
+0x01, 0x21, 0x01, 0x6C, 0xFF, 0x6B, 0x4C, 0xEB,
+0x8C, 0xEB, 0x06, 0x23, 0x0A, 0x94, 0x0C, 0x95,
+0x80, 0x18, 0x8D, 0x04, 0x01, 0x6A, 0x01, 0x10,
+0x00, 0x6A, 0x09, 0x97, 0x08, 0x91, 0x07, 0x90,
+0x05, 0x63, 0x00, 0xEF, 0xFB, 0x63, 0x09, 0x62,
+0x08, 0xD1, 0x07, 0xD0, 0xFF, 0x68, 0x0C, 0xED,
+0x24, 0x67, 0x0D, 0xD7, 0x04, 0xD5, 0xCC, 0xE8,
+0x80, 0x18, 0xB6, 0x05, 0x0F, 0x22, 0x04, 0x95,
+0x91, 0x67, 0x80, 0x18, 0xF8, 0x04, 0x0A, 0x22,
+0x0D, 0x96, 0x91, 0x67, 0xB0, 0x67, 0x80, 0x18,
+0x0A, 0x06, 0x4B, 0xEB, 0x4D, 0xEB, 0xC0, 0xF7,
+0x62, 0x32, 0x01, 0x10, 0x00, 0x6A, 0x09, 0x97,
+0x08, 0x91, 0x07, 0x90, 0x05, 0x63, 0x00, 0xEF,
+0x30, 0xF0, 0x20, 0x6B, 0x86, 0xF0, 0x99, 0xA3,
+0x30, 0xF0, 0x20, 0x6A, 0x1F, 0x6B, 0x8C, 0xEB,
+0xAF, 0xF4, 0x18, 0x4A, 0x60, 0xF4, 0x60, 0xC2,
+0xFF, 0x6D, 0xFF, 0x4B, 0xAC, 0xEB, 0x00, 0x6C,
+0x07, 0x5B, 0x60, 0xF4, 0x83, 0xC2, 0x08, 0x60,
+0x10, 0xF0, 0x23, 0x6A, 0x68, 0x33, 0xCE, 0xF6,
+0x1C, 0x4A, 0x69, 0xE2, 0x40, 0x9A, 0x00, 0xEA,
+0x01, 0x6B, 0x60, 0xF4, 0x61, 0xC2, 0x60, 0xF4,
+0x82, 0xC2, 0x0A, 0x10, 0x30, 0xF0, 0x20, 0x6A,
+0xAF, 0xF4, 0x18, 0x4A, 0x01, 0x6B, 0x60, 0xF4,
+0x61, 0xC2, 0x60, 0xF4, 0x62, 0xC2, 0x00, 0x6C,
+0x60, 0xF4, 0x85, 0xC2, 0x38, 0x10, 0x30, 0xF0,
+0x20, 0x6A, 0xAF, 0xF4, 0x18, 0x4A, 0x01, 0x6B,
+0x60, 0xF4, 0x61, 0xC2, 0x08, 0x10, 0x30, 0xF0,
+0x20, 0x6A, 0x01, 0x6B, 0xAF, 0xF4, 0x18, 0x4A,
+0x60, 0xF4, 0x61, 0xC2, 0x00, 0x6B, 0x60, 0xF4,
+0x62, 0xC2, 0x23, 0x10, 0x30, 0xF0, 0x20, 0x6A,
+0xAF, 0xF4, 0x18, 0x4A, 0x01, 0x6C, 0x00, 0x6B,
+0x60, 0xF4, 0x81, 0xC2, 0x60, 0xF4, 0x62, 0xC2,
+0xDF, 0x17, 0x30, 0xF0, 0x20, 0x6A, 0xAF, 0xF4,
+0x18, 0x4A, 0x00, 0x6B, 0x02, 0x6C, 0x60, 0xF4,
+0x61, 0xC2, 0x60, 0xF4, 0x65, 0xC2, 0x60, 0xF4,
+0x82, 0xC2, 0x01, 0x6B, 0x0C, 0x10, 0x30, 0xF0,
+0x20, 0x6A, 0xAF, 0xF4, 0x18, 0x4A, 0x01, 0x6B,
+0x00, 0x6C, 0x60, 0xF4, 0x61, 0xC2, 0x60, 0xF4,
+0x82, 0xC2, 0x60, 0xF4, 0x65, 0xC2, 0x60, 0xF4,
+0x64, 0xC2, 0x20, 0xE8, 0xFC, 0x63, 0x07, 0x62,
+0x06, 0xD1, 0x05, 0xD0, 0x30, 0xF0, 0x20, 0x6B,
+0xFF, 0x6A, 0xAF, 0xF4, 0x18, 0x4B, 0x8C, 0xEA,
+0x60, 0xF4, 0x81, 0xA3, 0x55, 0x24, 0x60, 0xF4,
+0x63, 0xA3, 0x00, 0x69, 0x01, 0x23, 0x01, 0x69,
+0x30, 0xF0, 0x21, 0x6B, 0x10, 0xF1, 0x7C, 0xA3,
+0x02, 0x2B, 0x01, 0x6B, 0x6E, 0xE9, 0x29, 0x2A,
+0x23, 0x10, 0x10, 0xF0, 0x23, 0x6B, 0x30, 0xF0,
+0x20, 0x68, 0x6F, 0xF1, 0xA4, 0x9B, 0xCE, 0xF4,
+0x50, 0x98, 0x4C, 0x6C, 0x02, 0x6E, 0x40, 0xEA,
+0xCE, 0xF4, 0x50, 0x98, 0xA1, 0xF4, 0x14, 0x6C,
+0xFF, 0x6D, 0x66, 0x6E, 0x40, 0xEA, 0x01, 0x6A,
+0x4E, 0xE9, 0x2B, 0xEB, 0x2D, 0xEB, 0xC0, 0xF7,
+0x62, 0x33, 0x10, 0xF0, 0x23, 0x6D, 0x02, 0x6E,
+0xCE, 0xF4, 0x50, 0x98, 0xA1, 0xF4, 0x14, 0x6C,
+0xEF, 0xF0, 0xBC, 0x9D, 0x7B, 0xE6, 0x23, 0x10,
+0x30, 0xF0, 0x21, 0x6A, 0x10, 0xF1, 0x5D, 0xA2,
+0xD8, 0x22, 0x10, 0xF0, 0x23, 0x6B, 0x30, 0xF0,
+0x20, 0x68, 0x6F, 0xF1, 0xA4, 0x9B, 0xCE, 0xF4,
+0x50, 0x98, 0x4C, 0x6C, 0x02, 0x6E, 0x40, 0xEA,
+0xCE, 0xF4, 0x50, 0x98, 0xA1, 0xF4, 0x14, 0x6C,
+0xFF, 0x6D, 0x77, 0x6E, 0x40, 0xEA, 0x10, 0xF0,
+0x23, 0x6B, 0x2B, 0xE9, 0xCE, 0xF4, 0x50, 0x98,
+0xEF, 0xF0, 0xBC, 0x9B, 0xC0, 0xF7, 0x22, 0x36,
+0xA1, 0xF4, 0x14, 0x6C, 0x01, 0x4E, 0x40, 0xEA,
+0x07, 0x97, 0x06, 0x91, 0x05, 0x90, 0x04, 0x63,
+0x00, 0xEF, 0x00, 0x65, 0xFD, 0x63, 0x05, 0x62,
+0xFF, 0x6A, 0x4C, 0xEC, 0x0F, 0x5C, 0x0A, 0x60,
+0x10, 0xF0, 0x23, 0x6A, 0x6F, 0xF1, 0x68, 0x9A,
+0xFC, 0x6A, 0x80, 0xA3, 0x8C, 0xEA, 0x40, 0xC3,
+0x00, 0x6C, 0x0E, 0x10, 0x24, 0x5C, 0x00, 0x6C,
+0x0B, 0x61, 0x10, 0xF0, 0x23, 0x6B, 0x6F, 0xF1,
+0x88, 0x9B, 0x03, 0x6D, 0x60, 0xA4, 0x4C, 0xEB,
+0xAD, 0xEB, 0x4C, 0xEB, 0x60, 0xC4, 0x01, 0x6C,
+0x80, 0x18, 0xE9, 0x06, 0x05, 0x97, 0x03, 0x63,
+0x00, 0xEF, 0x00, 0x65, 0x10, 0xF0, 0x21, 0x6A,
+0x84, 0xF4, 0x08, 0x4A, 0x30, 0xF0, 0x20, 0x6B,
+0x8E, 0xF6, 0x48, 0xDB, 0x10, 0xF0, 0x21, 0x6A,
+0x24, 0xF5, 0x00, 0x4A, 0x30, 0xF0, 0x20, 0x6B,
+0x8E, 0xF6, 0x4C, 0xDB, 0x10, 0xF0, 0x21, 0x6A,
+0xC4, 0xF5, 0x14, 0x4A, 0x30, 0xF0, 0x20, 0x6B,
+0x8E, 0xF6, 0x50, 0xDB, 0x10, 0xF0, 0x21, 0x6A,
+0x24, 0xF6, 0x08, 0x4A, 0x30, 0xF0, 0x20, 0x6B,
+0x8E, 0xF6, 0x54, 0xDB, 0x10, 0xF0, 0x21, 0x6A,
+0x64, 0xF6, 0x04, 0x4A, 0x30, 0xF0, 0x20, 0x6B,
+0x8E, 0xF6, 0x58, 0xDB, 0x10, 0xF0, 0x21, 0x6A,
+0xE4, 0xF6, 0x00, 0x4A, 0x30, 0xF0, 0x20, 0x6B,
+0x8E, 0xF6, 0x5C, 0xDB, 0x10, 0xF0, 0x21, 0x6A,
+0xE4, 0xF7, 0x18, 0x4A, 0x30, 0xF0, 0x20, 0x6B,
+0xAE, 0xF6, 0x40, 0xDB, 0x10, 0xF0, 0x21, 0x6A,
+0x65, 0xF1, 0x14, 0x4A, 0x30, 0xF0, 0x20, 0x6B,
+0xAE, 0xF6, 0x44, 0xDB, 0x10, 0xF0, 0x21, 0x6A,
+0x45, 0xF2, 0x14, 0x4A, 0x30, 0xF0, 0x20, 0x6B,
+0xAE, 0xF6, 0x48, 0xDB, 0x10, 0xF0, 0x21, 0x6A,
+0x45, 0xF3, 0x08, 0x4A, 0x30, 0xF0, 0x20, 0x6B,
+0xAE, 0xF6, 0x4C, 0xDB, 0x10, 0xF0, 0x21, 0x6A,
+0xC5, 0xF5, 0x10, 0x4A, 0x30, 0xF0, 0x20, 0x6B,
+0xAE, 0xF6, 0x50, 0xDB, 0x10, 0xF0, 0x21, 0x6A,
+0xA5, 0xF7, 0x14, 0x4A, 0x30, 0xF0, 0x20, 0x6B,
+0xAE, 0xF6, 0x54, 0xDB, 0x10, 0xF0, 0x21, 0x6A,
+0xA5, 0xF7, 0x18, 0x4A, 0x30, 0xF0, 0x20, 0x6B,
+0xAE, 0xF6, 0x58, 0xDB, 0x10, 0xF0, 0x21, 0x6A,
+0x06, 0xF1, 0x18, 0x4A, 0x30, 0xF0, 0x20, 0x6B,
+0xAE, 0xF6, 0x5C, 0xDB, 0x10, 0xF0, 0x21, 0x6A,
+0xC6, 0xF1, 0x0C, 0x4A, 0x30, 0xF0, 0x20, 0x6B,
+0xCE, 0xF6, 0x40, 0xDB, 0x20, 0xE8, 0x00, 0x65,
+0xBA, 0xE1, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+};
+
+u32 array_length_mp_8821c_fw_spic = 71264;
+
+#ifdef CONFIG_WOWLAN
+
+u8 array_mp_8821c_fw_wowlan[] = {
+0x21, 0x88, 0x00, 0x00, 0x14, 0x00, 0x01, 0x00,
+0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00,
+0x07, 0x01, 0x0E, 0x33, 0xE2, 0x07, 0x00, 0x00,
+0x18, 0x00, 0x00, 0x00, 0x0C, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x20, 0x80, 0xC0, 0x7C, 0x00, 0x00,
+0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x28, 0xF6, 0x00, 0x00, 0xD0, 0x1F, 0x00, 0x00,
+0x00, 0x00, 0x10, 0x80, 0x00, 0x00, 0x03, 0x80,
+0x00, 0x00, 0x04, 0x04, 0x08, 0x08, 0x08, 0x08,
+0x0C, 0x0C, 0x0C, 0x0C, 0x0C, 0x0C, 0x0C, 0x0C,
+0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10,
+0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10,
+0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14,
+0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14,
+0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14,
+0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14,
+0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18,
+0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18,
+0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18,
+0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18,
+0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18,
+0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18,
+0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18,
+0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18,
+0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C,
+0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C,
+0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C,
+0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C,
+0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C,
+0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C,
+0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C,
+0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C,
+0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C,
+0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C,
+0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C,
+0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C,
+0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C,
+0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C,
+0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C,
+0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x03, 0x00, 0x01, 0xFE, 0x03, 0x01, 0x01, 0xFE,
+0x03, 0x02, 0x01, 0xFE, 0x03, 0x03, 0x01, 0xFE,
+0x03, 0x04, 0x01, 0xFE, 0x03, 0x05, 0x01, 0xFE,
+0x03, 0x06, 0x01, 0xFE, 0x03, 0x07, 0x01, 0xFE,
+0x06, 0x00, 0x00, 0x00, 0x05, 0x00, 0x00, 0x00,
+0x01, 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00,
+0x00, 0x01, 0x10, 0x00, 0x01, 0x00, 0x03, 0x80,
+0x9D, 0x01, 0x03, 0x80, 0x9D, 0x01, 0x03, 0x80,
+0x61, 0x96, 0x03, 0x80, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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+0x8E, 0xF6, 0x4C, 0xDB, 0x10, 0xF0, 0x21, 0x6A,
+0xC4, 0xF5, 0x14, 0x4A, 0x30, 0xF0, 0x20, 0x6B,
+0x8E, 0xF6, 0x50, 0xDB, 0x10, 0xF0, 0x21, 0x6A,
+0x24, 0xF6, 0x08, 0x4A, 0x30, 0xF0, 0x20, 0x6B,
+0x8E, 0xF6, 0x54, 0xDB, 0x10, 0xF0, 0x21, 0x6A,
+0x64, 0xF6, 0x04, 0x4A, 0x30, 0xF0, 0x20, 0x6B,
+0x8E, 0xF6, 0x58, 0xDB, 0x10, 0xF0, 0x21, 0x6A,
+0xE4, 0xF6, 0x00, 0x4A, 0x30, 0xF0, 0x20, 0x6B,
+0x8E, 0xF6, 0x5C, 0xDB, 0x10, 0xF0, 0x21, 0x6A,
+0xE4, 0xF7, 0x18, 0x4A, 0x30, 0xF0, 0x20, 0x6B,
+0xAE, 0xF6, 0x40, 0xDB, 0x10, 0xF0, 0x21, 0x6A,
+0x65, 0xF1, 0x14, 0x4A, 0x30, 0xF0, 0x20, 0x6B,
+0xAE, 0xF6, 0x44, 0xDB, 0x10, 0xF0, 0x21, 0x6A,
+0x45, 0xF2, 0x14, 0x4A, 0x30, 0xF0, 0x20, 0x6B,
+0xAE, 0xF6, 0x48, 0xDB, 0x10, 0xF0, 0x21, 0x6A,
+0x45, 0xF3, 0x08, 0x4A, 0x30, 0xF0, 0x20, 0x6B,
+0xAE, 0xF6, 0x4C, 0xDB, 0x10, 0xF0, 0x21, 0x6A,
+0xC5, 0xF5, 0x10, 0x4A, 0x30, 0xF0, 0x20, 0x6B,
+0xAE, 0xF6, 0x50, 0xDB, 0x10, 0xF0, 0x21, 0x6A,
+0xA5, 0xF7, 0x14, 0x4A, 0x30, 0xF0, 0x20, 0x6B,
+0xAE, 0xF6, 0x54, 0xDB, 0x10, 0xF0, 0x21, 0x6A,
+0xA5, 0xF7, 0x18, 0x4A, 0x30, 0xF0, 0x20, 0x6B,
+0xAE, 0xF6, 0x58, 0xDB, 0x10, 0xF0, 0x21, 0x6A,
+0x06, 0xF1, 0x18, 0x4A, 0x30, 0xF0, 0x20, 0x6B,
+0xAE, 0xF6, 0x5C, 0xDB, 0x10, 0xF0, 0x21, 0x6A,
+0xC6, 0xF1, 0x0C, 0x4A, 0x30, 0xF0, 0x20, 0x6B,
+0xCE, 0xF6, 0x40, 0xDB, 0x20, 0xE8, 0x00, 0x65,
+0xF3, 0x59, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+};
+
+u32 array_length_mp_8821c_fw_wowlan = 103184;
+
+#endif /*CONFIG_WOWLAN*/
+
+#endif
+
+#endif /* end of LOAD_FW_HEADER_FROM_DRIVER */
+
+#endif
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/rtl8821c/hal8821c_fw.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/rtl8821c/hal8821c_fw.h
--- linux-5.6.3/3rdparty/rtl8821ce/hal/rtl8821c/hal8821c_fw.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/rtl8821c/hal8821c_fw.h	2020-04-10 16:35:06.842661282 +0300
@@ -0,0 +1,42 @@
+/******************************************************************************
+*
+* Copyright(c) 2012 - 2017 Realtek Corporation.
+*
+* This program is free software; you can redistribute it and/or modify it
+* under the terms of version 2 of the GNU General Public License as
+* published by the Free Software Foundation.
+*
+* This program is distributed in the hope that it will be useful, but WITHOUT
+* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+* more details.
+*
+******************************************************************************/
+
+#ifdef CONFIG_RTL8821C
+
+#ifndef _FW_HEADER_8821C_H
+#define _FW_HEADER_8821C_H
+
+#ifdef LOAD_FW_HEADER_FROM_DRIVER
+#if (defined(CONFIG_AP_WOWLAN) || (DM_ODM_SUPPORT_TYPE & (ODM_AP)))
+extern u8 array_mp_8821c_fw_ap[114208];
+extern u32 array_length_mp_8821c_fw_ap;
+#endif
+
+#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN)) || (DM_ODM_SUPPORT_TYPE & (ODM_CE))
+extern u8 array_mp_8821c_fw_nic[137616];
+extern u32 array_length_mp_8821c_fw_nic;
+extern u8 array_mp_8821c_fw_spic[71264];
+extern u32 array_length_mp_8821c_fw_spic;
+#ifdef CONFIG_WOWLAN
+extern u8 array_mp_8821c_fw_wowlan[103184];
+extern u32 array_length_mp_8821c_fw_wowlan;
+#endif /*CONFIG_WOWLAN*/
+#endif
+#endif /* end of LOAD_FW_HEADER_FROM_DRIVER */
+
+#endif
+
+#endif
+
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/rtl8821c/pci/rtl8821ce.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/rtl8821c/pci/rtl8821ce.h
--- linux-5.6.3/3rdparty/rtl8821ce/hal/rtl8821c/pci/rtl8821ce.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/rtl8821c/pci/rtl8821ce.h	2020-04-10 16:35:06.843661328 +0300
@@ -0,0 +1,127 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2016 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#ifndef _RTL8821CE_H_
+#define _RTL8821CE_H_
+
+#include <drv_types.h>		/* PADAPTER */
+
+#define TX_BD_NUM_8821CE	128
+#define RX_BD_NUM_8821CE	128
+#define TX_BD_NUM_8821CE_BCN	2
+#define TX_BD_NUM_8821CE_CMD	128
+
+#define RTL8821CE_SEG_NUM       1 /* 0:2 seg, 1: 4 seg, 2: 8 seg */
+
+#ifndef MAX_RECVBUF_SZ
+	#ifdef PLATFORM_OS_CE
+		#define MAX_RECVBUF_SZ (8192+1024)
+	#else /* !PLATFORM_OS_CE */
+		#ifndef CONFIG_MINIMAL_MEMORY_USAGE
+			#define MAX_RECVBUF_SZ (32768)
+		#else
+			#define MAX_RECVBUF_SZ (4000)
+		#endif
+	#endif /* PLATFORM_OS_CE */
+#endif /* !MAX_RECVBUF_SZ */
+
+#define TX_BUFFER_SEG_NUM	1 /* 0:2 seg, 1: 4 seg, 2: 8 seg. */
+
+#define MAX_RECVBUF_SZ_8821C	16384	/* 16k */
+
+#ifdef CONFIG_64BIT_DMA
+#define SET_TXBUFFER_DESC_LEN_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) \
+	SET_BITS_TO_LE_4BYTE(__pTxDesc+(__Offset*16), 0, 16, __Valeu)
+#define SET_TXBUFFER_DESC_AMSDU_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) \
+	SET_BITS_TO_LE_4BYTE(__pTxDesc+(__Offset*16), 31, 1, __Valeu)
+#define SET_TXBUFFER_DESC_ADD_LOW_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) \
+	SET_BITS_TO_LE_4BYTE(__pTxDesc+(__Offset*16)+4, 0, 32, __Valeu)
+#define SET_TXBUFFER_DESC_ADD_HIGH_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) \
+	SET_BITS_TO_LE_4BYTE(__pTxDesc+(__Offset*16)+8, 0, 32, __Valeu)
+#else
+/* TX BD */
+#define SET_TXBUFFER_DESC_LEN_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) \
+	SET_BITS_TO_LE_4BYTE(__pTxDesc+(__Offset*8), 0, 16, __Valeu)
+#define SET_TXBUFFER_DESC_AMSDU_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) \
+	SET_BITS_TO_LE_4BYTE(__pTxDesc+(__Offset*8), 31, 1, __Valeu)
+#define SET_TXBUFFER_DESC_ADD_LOW_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) \
+	SET_BITS_TO_LE_4BYTE(__pTxDesc+(__Offset*8)+4, 0, 32, __Valeu)
+#define SET_TXBUFFER_DESC_ADD_HIGH_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) 0
+#endif
+
+/* RX BD */
+#define SET_RX_BD_PHYSICAL_ADDR_LOW(__pRxBd, __Value) \
+	SET_BITS_TO_LE_4BYTE(__pRxBd + 0x04, 0, 32, __Value)
+#ifdef CONFIG_64BIT_DMA
+#define SET_RX_BD_PHYSICAL_ADDR_HIGH(__pRxBd, __Value) \
+	SET_BITS_TO_LE_4BYTE(__pRxBd + 0x08, 0, 32, __Value)
+#else
+#define SET_RX_BD_PHYSICAL_ADDR_HIGH(__pRxBd, __Value) 0
+#endif
+#define SET_RX_BD_RXBUFFSIZE(__pRxBd, __Value) \
+	SET_BITS_TO_LE_4BYTE(__pRxBd + 0x00, 0, 14, __Value)
+#define SET_RX_BD_LS(__pRxBd, __Value) \
+	SET_BITS_TO_LE_4BYTE(__pRxBd + 0x00, 14, 1, __Value)
+#define SET_RX_BD_FS(__pRxBd, __Value) \
+	SET_BITS_TO_LE_4BYTE(__pRxBd + 0x00, 15, 1, __Value)
+#define SET_RX_BD_TOTALRXPKTSIZE(__pRxBd, __Value) \
+	SET_BITS_TO_LE_4BYTE(__pRxBd + 0x00, 16, 13, __Value)
+
+/* rtl8821ce_halinit.c */
+u32 rtl8821ce_hal_init(PADAPTER);
+u32 rtl8821ce_hal_deinit(PADAPTER);
+void rtl8821ce_init_default_value(PADAPTER);
+
+/* rtl8821ce_halmac.c */
+int rtl8821ce_halmac_init_adapter(PADAPTER);
+
+/* rtl8821ce_io.c */
+
+/* rtl8821ce_led.c */
+void rtl8821ce_initswleds(PADAPTER);
+void rtl8821ce_deinitswleds(PADAPTER);
+
+/* rtl8821ce_xmit.c */
+#define OFFSET_SZ 0
+
+s32 rtl8821ce_init_xmit_priv(PADAPTER);
+void rtl8821ce_free_xmit_priv(PADAPTER);
+struct xmit_buf *rtl8821ce_dequeue_xmitbuf(struct rtw_tx_ring *);
+void rtl8821ce_fill_fake_txdesc(PADAPTER, u8 *pDesc, u32 BufferLen,
+				u8 IsPsPoll, u8 IsBTQosNull, u8 bDataFrame);
+int rtl8821ce_init_txbd_ring(PADAPTER, unsigned int q_idx,
+			     unsigned int entries);
+void rtl8821ce_free_txbd_ring(PADAPTER, unsigned int prio);
+
+void rtl8821ce_tx_isr(PADAPTER, int prio);
+
+s32 rtl8821ce_mgnt_xmit(PADAPTER, struct xmit_frame *);
+s32 rtl8821ce_hal_xmit(PADAPTER, struct xmit_frame *);
+s32 rtl8821ce_hal_xmitframe_enqueue(PADAPTER, struct xmit_frame *);
+
+#ifdef CONFIG_XMIT_THREAD_MODE
+	s32 rtl8821ce_xmit_buf_handler(PADAPTER);
+#endif
+
+void rtl8821ce_xmitframe_resume(PADAPTER);
+
+/* rtl8821ce_recv.c */
+s32 rtl8821ce_init_recv_priv(PADAPTER);
+void rtl8821ce_free_recv_priv(PADAPTER);
+int rtl8821ce_init_rxbd_ring(PADAPTER);
+void rtl8821ce_free_rxbd_ring(PADAPTER);
+
+/* rtl8821cs_ops.c */
+
+#endif /* _RTL8821CE_H_ */
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/rtl8821c/pci/rtl8821ce_halinit.c linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/rtl8821c/pci/rtl8821ce_halinit.c
--- linux-5.6.3/3rdparty/rtl8821ce/hal/rtl8821c/pci/rtl8821ce_halinit.c	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/rtl8821c/pci/rtl8821ce_halinit.c	2020-04-10 16:35:06.843661328 +0300
@@ -0,0 +1,381 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2016 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+
+#define _RTL8821CE_HALINIT_C_
+#include <drv_types.h>          /* PADAPTER, basic_types.h and etc. */
+#include <hal_data.h>		/* HAL_DATA_TYPE */
+#include "../rtl8821c.h"
+#include "rtl8821ce.h"
+
+u32 InitMAC_TRXBD_8821CE(PADAPTER Adapter)
+{
+	u8 tmpU1b;
+	u16 tmpU2b;
+	u32 tmpU4b;
+	int q_idx;
+	struct recv_priv *precvpriv = &Adapter->recvpriv;
+	struct xmit_priv *pxmitpriv = &Adapter->xmitpriv;
+	HAL_DATA_TYPE	*pHalData	= GET_HAL_DATA(Adapter);
+
+	RTW_INFO("=======>InitMAC_TXBD_8821CE()\n");
+
+	/*
+	 * Set CMD TX BD (buffer descriptor) physical address(from OS API).
+	 */
+	rtw_write32(Adapter, REG_H2CQ_TXBD_DESA_8821C,
+		    (u64)pxmitpriv->tx_ring[TXCMD_QUEUE_INX].dma &
+		    DMA_BIT_MASK(32));
+	rtw_write32(Adapter, REG_H2CQ_TXBD_NUM_8821C,
+		    TX_BD_NUM_8821CE_CMD | ((RTL8821CE_SEG_NUM << 12) &
+					 0x3000));
+
+#ifdef CONFIG_64BIT_DMA
+	rtw_write32(Adapter, REG_H2CQ_TXBD_DESA_8821C + 4,
+		    ((u64)pxmitpriv->tx_ring[TXCMD_QUEUE_INX].dma) >> 32);
+#endif
+	/*
+	 * Set TX/RX BD (buffer descriptor) physical address(from OS API).
+	 */
+	rtw_write32(Adapter, REG_BCNQ_TXBD_DESA_8821C,
+		    (u64)pxmitpriv->tx_ring[BCN_QUEUE_INX].dma &
+		    DMA_BIT_MASK(32));
+	rtw_write32(Adapter, REG_MGQ_TXBD_DESA_8821C,
+		    (u64)pxmitpriv->tx_ring[MGT_QUEUE_INX].dma &
+		    DMA_BIT_MASK(32));
+	rtw_write32(Adapter, REG_VOQ_TXBD_DESA_8821C,
+		    (u64)pxmitpriv->tx_ring[VO_QUEUE_INX].dma &
+		    DMA_BIT_MASK(32));
+	rtw_write32(Adapter, REG_VIQ_TXBD_DESA_8821C,
+		    (u64)pxmitpriv->tx_ring[VI_QUEUE_INX].dma &
+		    DMA_BIT_MASK(32));
+	rtw_write32(Adapter, REG_BEQ_TXBD_DESA_8821C,
+		    (u64)pxmitpriv->tx_ring[BE_QUEUE_INX].dma &
+		    DMA_BIT_MASK(32));
+
+	/* vincent sync windows */
+	tmpU4b = rtw_read32(Adapter, REG_BEQ_TXBD_DESA_8821C);
+
+	rtw_write32(Adapter, REG_BKQ_TXBD_DESA_8821C,
+		    (u64)pxmitpriv->tx_ring[BK_QUEUE_INX].dma &
+		    DMA_BIT_MASK(32));
+	rtw_write32(Adapter, REG_HI0Q_TXBD_DESA_8821C,
+		    (u64)pxmitpriv->tx_ring[HIGH_QUEUE_INX].dma &
+		    DMA_BIT_MASK(32));
+	rtw_write32(Adapter, REG_RXQ_RXBD_DESA_8821C,
+		    (u64)precvpriv->rx_ring[RX_MPDU_QUEUE].dma &
+		    DMA_BIT_MASK(32));
+
+#ifdef CONFIG_64BIT_DMA
+	/*
+	 * 2009/10/28 MH For DMA 64 bits. We need to assign the high
+	 * 32 bit address for NIC HW to transmit data to correct path.
+	 */
+	rtw_write32(Adapter, REG_BCNQ_TXBD_DESA_8821C + 4,
+		    ((u64)pxmitpriv->tx_ring[BCN_QUEUE_INX].dma) >> 32);
+	rtw_write32(Adapter, REG_MGQ_TXBD_DESA_8821C + 4,
+		    ((u64)pxmitpriv->tx_ring[MGT_QUEUE_INX].dma) >> 32);
+	rtw_write32(Adapter, REG_VOQ_TXBD_DESA_8821C + 4,
+		    ((u64)pxmitpriv->tx_ring[VO_QUEUE_INX].dma) >> 32);
+	rtw_write32(Adapter, REG_VIQ_TXBD_DESA_8821C + 4,
+		    ((u64)pxmitpriv->tx_ring[VI_QUEUE_INX].dma) >> 32);
+	rtw_write32(Adapter, REG_BEQ_TXBD_DESA_8821C + 4,
+		    ((u64)pxmitpriv->tx_ring[BE_QUEUE_INX].dma) >> 32);
+	rtw_write32(Adapter, REG_BKQ_TXBD_DESA_8821C + 4,
+		    ((u64)pxmitpriv->tx_ring[BK_QUEUE_INX].dma) >> 32);
+	rtw_write32(Adapter, REG_HI0Q_TXBD_DESA_8821C + 4,
+		    ((u64)pxmitpriv->tx_ring[HIGH_QUEUE_INX].dma) >> 32);
+	rtw_write32(Adapter, REG_RXQ_RXBD_DESA_8821C + 4,
+		    ((u64)precvpriv->rx_ring[RX_MPDU_QUEUE].dma) >> 32);
+
+#if 0
+	/* 2009/10/28 MH If RX descriptor address is not equal to zero.
+	* We will enable DMA 64 bit functuion.
+	* Note: We never saw thd consition which the descripto address are
+	*	divided into 4G down and 4G upper separate area.
+	*/
+	if (((u64)precvpriv->rx_ring[RX_MPDU_QUEUE].dma) >> 32 != 0) {
+		RTW_INFO("Enable DMA64 bit\n");
+
+		/* Check if other descriptor address is zero and
+		* abnormally be in 4G lower area.
+		*/
+		if (((u64)pxmitpriv->tx_ring[MGT_QUEUE_INX].dma) >> 32)
+			RTW_INFO("MGNT_QUEUE HA=0\n");
+
+	} else
+		RTW_INFO("Enable DMA32 bit\n");
+#endif
+	if (adapter_to_dvobj(Adapter)->bdma64)	
+		PlatformEnableDMA64(Adapter);
+#endif
+
+	/* pci buffer descriptor mode: Reset the Read/Write point to 0 */
+	PlatformEFIOWrite4Byte(Adapter, REG_TSFTIMER_HCI_8821C, 0x3fffffff);
+
+	/* Reset the H2CQ R/W point index to 0 */
+	tmpU4b = rtw_read32(Adapter, REG_H2CQ_CSR_8821C);
+	rtw_write32(Adapter, REG_H2CQ_CSR_8821C, (tmpU4b | BIT8 | BIT16));
+
+	tmpU1b = rtw_read8(Adapter, REG_PCIE_CTRL + 3);
+	rtw_write8(Adapter, REG_PCIE_CTRL + 3, (tmpU1b | 0xF7));
+
+	/* 20100318 Joseph: Reset interrupt migration setting
+	* when initialization. Suggested by SD1
+	*/
+
+	rtw_write32(Adapter, REG_INT_MIG, 0);
+	pHalData->bInterruptMigration = _FALSE;
+
+	/* 2009.10.19. Reset H2C protection register. by tynli. */
+	rtw_write32(Adapter, REG_MCUTST_I_8821C, 0x0);
+
+#if MP_DRIVER == 1
+	if (Adapter->registrypriv.mp_mode == 1) {
+		rtw_write32(Adapter, REG_MACID, 0x87654321);
+		rtw_write32(Adapter, 0x0700, 0x87654321);
+	}
+#endif
+
+	/* pic buffer descriptor mode: */
+	/* ---- tx */
+	rtw_write16(Adapter, REG_MGQ_TXBD_NUM_8821C,
+		    TX_BD_NUM_8821CE | ((RTL8821CE_SEG_NUM << 12) & 0x3000));
+	rtw_write16(Adapter, REG_VOQ_TXBD_NUM_8821C,
+		    TX_BD_NUM_8821CE | ((RTL8821CE_SEG_NUM << 12) & 0x3000));
+	rtw_write16(Adapter, REG_VIQ_TXBD_NUM_8821C,
+		    TX_BD_NUM_8821CE | ((RTL8821CE_SEG_NUM << 12) & 0x3000));
+	rtw_write16(Adapter, REG_BEQ_TXBD_NUM_8821C,
+		    TX_BD_NUM_8821CE | ((RTL8821CE_SEG_NUM << 12) & 0x3000));
+	rtw_write16(Adapter, REG_BKQ_TXBD_NUM_8821C,
+		    TX_BD_NUM_8821CE | ((RTL8821CE_SEG_NUM << 12) & 0x3000));
+	rtw_write16(Adapter, REG_HI0Q_TXBD_NUM_8821C,
+		    TX_BD_NUM_8821CE | ((RTL8821CE_SEG_NUM << 12) & 0x3000));
+	rtw_write16(Adapter, REG_HI1Q_TXBD_NUM_8821C,
+		    TX_BD_NUM_8821CE | ((RTL8821CE_SEG_NUM << 12) & 0x3000));
+	rtw_write16(Adapter, REG_HI2Q_TXBD_NUM_8821C,
+		    TX_BD_NUM_8821CE | ((RTL8821CE_SEG_NUM << 12) & 0x3000));
+	rtw_write16(Adapter, REG_HI3Q_TXBD_NUM_8821C,
+		    TX_BD_NUM_8821CE | ((RTL8821CE_SEG_NUM << 12) & 0x3000));
+	rtw_write16(Adapter, REG_HI4Q_TXBD_NUM_8821C,
+		    TX_BD_NUM_8821CE | ((RTL8821CE_SEG_NUM << 12) & 0x3000));
+	rtw_write16(Adapter, REG_HI5Q_TXBD_NUM_8821C,
+		    TX_BD_NUM_8821CE | ((RTL8821CE_SEG_NUM << 12) & 0x3000));
+	rtw_write16(Adapter, REG_HI6Q_TXBD_NUM_8821C,
+		    TX_BD_NUM_8821CE | ((RTL8821CE_SEG_NUM << 12) & 0x3000));
+	rtw_write16(Adapter, REG_HI7Q_TXBD_NUM_8821C,
+		    TX_BD_NUM_8821CE | ((RTL8821CE_SEG_NUM << 12) & 0x3000));
+
+
+	/* rx. support 32 bits in linux */
+
+#ifdef CONFIG_64BIT_DMA
+	/* using 64bit */
+	rtw_write16(Adapter, REG_RX_RXBD_NUM_8821C,
+		    RX_BD_NUM_8821CE |((RTL8821CE_SEG_NUM<<13 ) & 0x6000) |0x8000);
+#else
+	/* using 32bit */
+	rtw_write16(Adapter, REG_RX_RXBD_NUM_8821C,
+		    RX_BD_NUM_8821CE | ((RTL8821CE_SEG_NUM << 13) & 0x6000));
+#endif
+
+	/* reset read/write point */
+	rtw_write32(Adapter, REG_TSFTIMER_HCI_8821C, 0XFFFFFFFF);
+
+#if 1 /* vincent windows */
+	/* Start debug mode */
+	{
+		u8 reg0x3f3 = 0;
+
+		reg0x3f3 = rtw_read8(Adapter, 0x3f3);
+		rtw_write8(Adapter, 0x3f3, reg0x3f3 | BIT2);
+	}
+
+	{
+	/* Need to disable BT coex to let MP tool Tx, this would be done in FW
+	*  in the future, suggest by ChunChu, 2015.05.19
+	*/
+
+		u8 tmp1Byte;
+		u16 tmp2Byte;
+		u32 tmp4Byte;
+
+		tmp2Byte = rtw_read16(Adapter, REG_SYS_FUNC_EN_8821C);
+		rtw_write16(Adapter, REG_SYS_FUNC_EN_8821C, tmp2Byte | BIT10);
+		tmp1Byte = rtw_read8(Adapter, REG_DIS_TXREQ_CLR_8821C);
+		rtw_write8(Adapter, REG_DIS_TXREQ_CLR_8821C, tmp1Byte | BIT7);
+		tmp4Byte = rtw_read32(Adapter, 0x1080);
+		rtw_write32(Adapter, 0x1080, tmp4Byte | BIT16);
+	}
+#endif
+
+	RTW_INFO("InitMAC_TXBD_8821CE() <====\n");
+
+	return _SUCCESS;
+}
+
+u32 rtl8821ce_hal_init(PADAPTER padapter)
+{
+	u8 ok = _TRUE;
+	u8 val8;
+	PHAL_DATA_TYPE hal;
+	struct registry_priv  *registry_par;
+
+	hal = GET_HAL_DATA(padapter);
+	registry_par = &padapter->registrypriv;
+
+	InitMAC_TRXBD_8821CE(padapter);
+
+	ok = rtl8821c_hal_init(padapter);
+	if (ok == _FALSE)
+		return _FAIL;
+
+#if defined(USING_RX_TAG)
+	/* have to init after halmac init */
+	val8 = rtw_read8(padapter, REG_PCIE_CTRL_8821C + 2);
+	rtw_write8(padapter, REG_PCIE_CTRL_8821C + 2, (val8 | BIT4));
+	rtw_write16(padapter, REG_PCIE_CTRL_8821C, 0x8000);
+#else
+	rtw_write16(padapter, REG_PCIE_CTRL_8821C, 0x0000);
+#endif
+
+	rtw_write8(padapter, REG_RX_DRVINFO_SZ_8821C, 0x4);
+
+	/* MAX AMPDU Number = 43, Reg0x4C8[21:16] = 0x2B */
+	rtw_write16(padapter, REG_PROT_MODE_CTRL_8821C + 2, 0x2B2B);
+
+	hal->pci_backdoor_ctrl = registry_par->pci_aspm_config;
+
+	rtw_pci_aspm_config(padapter);
+
+	return _SUCCESS;
+}
+
+void rtl8821ce_init_default_value(PADAPTER padapter)
+{
+	PHAL_DATA_TYPE pHalData;
+
+
+	pHalData = GET_HAL_DATA(padapter);
+
+	rtl8821c_init_default_value(padapter);
+
+	/* interface related variable */
+	pHalData->CurrentWirelessMode = WIRELESS_MODE_AUTO;
+	pHalData->bDefaultAntenna = 1;
+	pHalData->TransmitConfig = BIT_CFEND_FORMAT | BIT_WMAC_TCR_ERRSTEN_3;
+
+	/* Set RCR-Receive Control Register .
+	 * The value is set in InitializeAdapter8190Pci().
+	 */
+	pHalData->ReceiveConfig = (
+#ifdef CONFIG_RX_PACKET_APPEND_FCS
+				BIT_APP_FCS		|
+#endif
+				BIT_APP_MIC			|
+				BIT_APP_ICV			|
+				BIT_APP_PHYSTS		|
+				BIT_VHT_DACK		|
+				BIT_HTC_LOC_CTRL	|
+				/* BIT_AMF		| */
+				BIT_CBSSID_DATA		|
+				BIT_CBSSID_BCN		|
+				/* BIT_ACF		| */
+				/* BIT_ADF		|  PS-Poll filter */
+				BIT_AB				|
+				BIT_AB				|
+				BIT_APM				|
+				0);
+
+	/*
+	 * Set default value of Interrupt Mask Register0
+	 */
+	pHalData->IntrMaskDefault[0] = (u32)(
+				BIT(29)			| /* BIT_PSTIMEOUT */
+				BIT(27)			| /* BIT_GTINT3 */
+				BIT_TXBCN0ERR_MSK	|
+				BIT_TXBCN0OK_MSK	|
+				BIT_BCNDMAINT0_MSK	|
+				BIT_HSISR_IND_ON_INT_MSK |
+				BIT_C2HCMD_MSK		|
+	#ifdef CONFIG_LPS_LCLK
+				BIT_CPWM_MSK		|
+	#endif
+				BIT_HIGHDOK_MSK	|
+				BIT_MGTDOK_MSK		|
+				BIT_BKDOK_MSK		|
+				BIT_BEDOK_MSK		|
+				BIT_VIDOK_MSK		|
+				BIT_VODOK_MSK		|
+				BIT_RDU_MSK		|
+				BIT_RXOK_MSK		|
+				0);
+
+	/*
+	 * Set default value of Interrupt Mask Register1
+	 */
+	pHalData->IntrMaskDefault[1] = (u32)(
+				BIT(9)		| /* TXFOVW */
+				BIT_FOVW_MSK	|
+				BIT_PRETXERR_HANDLE_IMR |
+				0);
+
+	/*
+	 * Set default value of Interrupt Mask Register3
+	 */
+	pHalData->IntrMaskDefault[3] = (u32)(
+				BIT_SETH2CDOK_MASK	| /* H2C_TX_OK */
+				0);
+
+	/* 2012/03/27 hpfan Add for win8 DTM DPC ISR test */
+	pHalData->IntrMaskReg[0] = (u32)(
+				BIT_RDU_MSK	|
+				BIT(29)		| /* BIT_PSTIMEOUT */
+				0);
+
+	pHalData->IntrMaskReg[1] = (u32)(
+					   BIT_C2HCMD_MSK	|
+					   0);
+
+	pHalData->IntrMask[0] = pHalData->IntrMaskDefault[0];
+	pHalData->IntrMask[1] = pHalData->IntrMaskDefault[1];
+	pHalData->IntrMask[3] = pHalData->IntrMaskDefault[3];
+
+}
+
+static void hal_deinit_misc(PADAPTER padapter)
+{
+
+}
+
+u32 rtl8821ce_hal_deinit(PADAPTER padapter)
+{
+	struct pwrctrl_priv *pwrctl = adapter_to_pwrctl(padapter);
+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(padapter);
+	struct dvobj_priv *pobj_priv = adapter_to_dvobj(padapter);
+	u8 status = _TRUE;
+
+	RTW_INFO("==> %s\n", __func__);
+
+
+	hal_deinit_misc(padapter);
+	status = rtl8821c_hal_deinit(padapter);
+	if (status == _FALSE) {
+		RTW_INFO("%s: rtl8821c_hal_deinit fail\n", __func__);
+		return _FAIL;
+	}
+
+	RTW_INFO("%s <==\n", __func__);
+	return _SUCCESS;
+}
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/rtl8821c/pci/rtl8821ce_halmac.c linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/rtl8821c/pci/rtl8821ce_halmac.c
--- linux-5.6.3/3rdparty/rtl8821ce/hal/rtl8821c/pci/rtl8821ce_halmac.c	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/rtl8821c/pci/rtl8821ce_halmac.c	2020-04-10 16:35:06.843661328 +0300
@@ -0,0 +1,382 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2016 - 2018 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#define _RTL8821CE_HALMAC_C_
+#include <drv_types.h>		/* struct dvobj_priv and etc. */
+#include "../../hal_halmac.h"
+#include "rtl8821ce.h"
+
+static u8 pci_write_port_not_xmitframe(void *d,  u32 size, u8 *pBuf, u8 qsel)
+{
+	struct dvobj_priv *pobj = (struct dvobj_priv *)d;
+	struct pci_dev *pdev = pobj->ppcidev;
+	PADAPTER padapter = dvobj_get_primary_adapter(pobj);
+	u32 page_size = 0;
+	u8 *txbd;
+#ifdef  CONFIG_64BIT
+	u64 txbd_dma;
+#else
+	dma_addr_t txbd_dma;
+#endif
+	u8 ret = _SUCCESS;
+	dma_addr_t mapping;
+
+	u16 seg_num = 2 << TX_BUFFER_SEG_NUM;
+
+	u16 page_size_length = 0;
+#ifdef CONFIG_64BIT_DMA	
+	u16 tmp = rtw_read16(padapter, REG_RX_RXBD_NUM_8821C);
+	/* using 64bit */	
+	rtw_write16(padapter, REG_RX_RXBD_NUM_8821C, tmp | 0x8000);
+#endif
+
+	rtw_hal_get_def_var(padapter, HAL_DEF_TX_PAGE_SIZE, &page_size);
+
+	/* map TX DESC buf_addr (including TX DESC + tx data) */
+	mapping = pci_map_single(pdev, pBuf,
+			size+TX_WIFI_INFO_SIZE, PCI_DMA_TODEVICE);
+
+
+	/* Calculate page size.
+	 * Total buffer length including TX_WIFI_INFO and PacketLen
+	 */
+	page_size_length =
+		(size + TX_WIFI_INFO_SIZE) / page_size;
+
+	if (((size + TX_WIFI_INFO_SIZE) % page_size) > 0)
+		page_size_length++;
+
+	txbd = pci_alloc_consistent(pdev,
+		sizeof(struct tx_buf_desc), &txbd_dma);
+
+	if (!txbd) {
+		pci_unmap_single(pdev, mapping,
+			size + TX_WIFI_INFO_SIZE, PCI_DMA_FROMDEVICE);
+
+		return _FALSE;
+	}
+	if (qsel == HALMAC_TXDESC_QSEL_H2C_CMD) {
+		rtw_write32(padapter, REG_H2CQ_TXBD_DESA_8821C,
+			txbd_dma & DMA_BIT_MASK(32));
+	#ifdef CONFIG_64BIT_DMA	
+		rtw_write32(padapter, REG_H2CQ_TXBD_DESA_8821C + 4,
+			txbd_dma >> 32);
+	#endif
+
+		rtw_write32(padapter, REG_H2CQ_TXBD_NUM_8821C,
+			2 | ((RTL8821CE_SEG_NUM << 12) & 0x3000));
+	} else {
+		/* Set BCN BD Reg */
+		rtw_write32(padapter, REG_BCNQ_TXBD_DESA_8821C,
+			txbd_dma & DMA_BIT_MASK(32));
+	#ifdef CONFIG_64BIT_DMA	
+		rtw_write32(padapter, REG_BCNQ_TXBD_DESA_8821C + 4,
+			txbd_dma >> 32);
+	#endif
+	}
+
+	/*
+	 * Reset all tx buffer desciprtor content
+	 * -- Reset first element
+	 */
+	_rtw_memset(txbd, 0, sizeof(struct tx_buf_desc));
+
+	/*
+	 * Fill buffer length of the first buffer,
+	 * For 8821ce, it is required that TX_WIFI_INFO is put in first segment,
+	 * and the size of the first segment cannot be larger than
+	 * TX_WIFI_INFO_SIZE.
+	 */
+	SET_TX_BD_TX_BUFF_SIZE0(txbd, TX_WIFI_INFO_SIZE);
+	SET_TX_BD_PSB(txbd, page_size_length);
+	/* starting addr of TXDESC */
+	SET_TX_BD_PHYSICAL_ADDR0_LOW(txbd, mapping);
+#ifdef CONFIG_64BIT_DMA 
+	SET_TX_BD_PHYSICAL_ADDR0_HIGH(txbd, mapping>>32);
+#endif
+
+	/*
+	 * It is assumed that in linux implementation, packet is coalesced
+	 * in only one buffer. Extension mode is not supported here
+	 */
+	SET_TXBUFFER_DESC_LEN_WITH_OFFSET(txbd, 1, size);
+
+	SET_TXBUFFER_DESC_ADD_LOW_WITH_OFFSET(txbd, 1,
+				      mapping + TX_WIFI_INFO_SIZE); /* pkt */
+
+#ifdef CONFIG_64BIT_DMA 
+	SET_TXBUFFER_DESC_ADD_HIGH_WITH_OFFSET(txbd, 1,
+				      (mapping + TX_WIFI_INFO_SIZE) >> 32); /* pkt */
+#endif
+
+
+	/* Need Comment */
+	wmb();
+
+	if (qsel == HALMAC_TXDESC_QSEL_H2C_CMD)
+		rtw_write16(padapter, REG_H2CQ_TXBD_IDX, 1);
+	else {
+		/* fill_txbd_own*/
+		SET_TX_BD_OWN(txbd, 1);
+		/* kick start */
+		rtw_write8(padapter, REG_RX_RXBD_NUM + 1,
+			rtw_read8(padapter, REG_RX_RXBD_NUM + 1) | BIT(4));
+	}
+
+	udelay(100);
+
+	pci_free_consistent(pdev, sizeof(struct tx_buf_desc), txbd, txbd_dma);
+
+	pci_unmap_single(pdev, mapping,
+			size + TX_WIFI_INFO_SIZE,	 PCI_DMA_FROMDEVICE);
+
+	return ret;
+
+}
+
+static u8 pci_write_data_not_xmitframe(void *d, u8 *pBuf, u32 size, u8 qsel)
+{
+	struct dvobj_priv *pobj = (struct dvobj_priv *)d;
+	PADAPTER padapter = dvobj_get_primary_adapter(pobj);
+	struct halmac_adapter *halmac = dvobj_to_halmac((struct dvobj_priv *)d);
+	struct halmac_api *api = HALMAC_GET_API(halmac);
+	u32 desclen = 0;
+	u8 *buf = NULL;
+	u8 ret = _FALSE;
+
+	if ((size + TXDESC_OFFSET) > MAX_CMDBUF_SZ) {
+		RTW_INFO("%s: total buffer size(%d) > MAX_CMDBUF_SZ(%d)\n"
+			, __func__, size + TXDESC_OFFSET, MAX_CMDBUF_SZ);
+		return _FALSE;
+	}
+
+	rtw_halmac_get_tx_desc_size(pobj, &desclen);
+
+	buf = rtw_zmalloc(desclen + size);
+
+	if (!buf) {
+		RTW_INFO("%s: rtw_zmalloc for rsvd Fail\n", __func__);
+		return _FALSE;
+	}
+
+	_rtw_memcpy(buf + desclen, pBuf, size);
+
+	SET_TX_DESC_TXPKTSIZE_8821C(buf, size);
+
+	/* TX_DESC is not included in the data,
+	 * driver needs to fill in the TX_DESC with qsel=h2c
+	 * Offset in TX_DESC should be set to 0.
+	 */
+	if (qsel == HALMAC_TXDESC_QSEL_H2C_CMD)
+		SET_TX_DESC_OFFSET_8821C(buf, 0);
+	else
+		SET_TX_DESC_OFFSET_8821C(buf, desclen);
+
+	SET_TX_DESC_QSEL_8821C(buf, qsel);
+
+	api->halmac_fill_txdesc_checksum(halmac, buf);
+
+	ret = pci_write_port_not_xmitframe(d, size, buf, qsel);
+
+
+	if (ret == _SUCCESS)
+		ret = _TRUE;
+	else
+		ret = _FALSE;
+
+	rtw_mfree(buf, desclen + size);
+
+	return _TRUE;
+}
+
+static u8 pci_write_data_rsvd_page_xmitframe(void *d, u8 *pBuf, u32 size)
+{
+	struct dvobj_priv *pobj = (struct dvobj_priv *)d;
+	PADAPTER padapter = dvobj_get_primary_adapter(pobj);
+	struct xmit_priv        *pxmitpriv = &padapter->xmitpriv;
+	struct xmit_frame       *pcmdframe = NULL;
+	struct pkt_attrib       *pattrib = NULL;
+	u32 desclen = 0;
+	struct rtw_tx_ring *ring = &pxmitpriv->tx_ring[BCN_QUEUE_INX];
+	struct pci_dev *pdev = pobj->ppcidev;
+	struct xmit_buf       	*pxmitbuf = NULL;
+	u8 DLBcnCount = 0;
+	u32 poll = 0;
+	u8 *txbd;
+	bool bcn_valid = _FALSE;
+	u8 *txdesc = NULL;
+	dma_addr_t mapping;
+
+	if (size + TXDESC_OFFSET > MAX_CMDBUF_SZ) {
+		RTW_INFO("%s: total buffer size(%d) > MAX_CMDBUF_SZ(%d)\n"
+			, __func__, size + TXDESC_OFFSET, MAX_CMDBUF_SZ);
+		return _FALSE;
+	}
+
+	pcmdframe = rtw_alloc_cmdxmitframe(pxmitpriv);
+
+	if (pcmdframe == NULL) {
+		RTW_INFO("%s: alloc ReservedPagePacket fail!\n", __func__);
+		return _FALSE;
+	}
+
+        pxmitbuf = pcmdframe->pxmitbuf;
+	rtw_halmac_get_tx_desc_size(pobj, &desclen);
+	txdesc = pcmdframe->buf_addr;
+
+	_rtw_memcpy((txdesc + desclen), pBuf, size); /* shift desclen */
+
+	/* update attribute */
+	pattrib = &pcmdframe->attrib;
+	update_mgntframe_attrib(padapter, pattrib);
+	pattrib->qsel = QSLT_BEACON;
+	pattrib->pktlen = size;
+	pattrib->last_txcmdsz = size;
+
+	/* Clear beacon valid check bit. */
+	rtw_hal_set_hwreg(padapter, HW_VAR_BCN_VALID, NULL);
+
+	dump_mgntframe(padapter, pcmdframe);
+
+	DLBcnCount = 0;
+	poll = 0;
+	do {
+		DLBcnCount++;
+		do {
+			rtw_yield_os();
+			/* does rsvd page download OK. */
+			rtw_hal_get_hwreg(padapter,
+				HW_VAR_BCN_VALID,(u8 *)(&bcn_valid));
+			poll++;
+		} while (!bcn_valid && (poll % 10) != 0 && !RTW_CANNOT_RUN(padapter));
+	} while (!bcn_valid && DLBcnCount <= 100 && !RTW_CANNOT_RUN(padapter));
+
+	txbd = (u8 *)(&ring->buf_desc[0]);
+
+	mapping = GET_TX_BD_PHYSICAL_ADDR0_LOW(txbd);
+	#ifdef CONFIG_64BIT_DMA
+		mapping |= (dma_addr_t)GET_TX_BD_PHYSICAL_ADDR0_HIGH(txbd) << 32;
+	#endif
+
+	/*To patch*/
+
+	pci_unmap_single(pdev, mapping,	pxmitbuf->len, PCI_DMA_TODEVICE);
+
+	return _TRUE;
+}
+
+static u8 pci_write_data_h2c_normal(void *d, u8 *pBuf, u32 size)
+{
+	struct dvobj_priv *pobj = (struct dvobj_priv *)d;
+	PADAPTER padapter = dvobj_get_primary_adapter(pobj);
+	struct halmac_adapter *halmac = dvobj_to_halmac((struct dvobj_priv *)d);
+	struct xmit_priv        *pxmitpriv = &padapter->xmitpriv;
+	struct xmit_frame       *pcmdframe = NULL;
+	struct pkt_attrib       *pattrib = NULL;
+	struct halmac_api *api;
+	u32 desclen;
+	u8 *buf;
+
+	if (size + TXDESC_OFFSET > MAX_XMIT_EXTBUF_SZ) {
+		RTW_INFO("%s: total buffer size(%d) > MAX_XMIT_EXTBUF_SZ(%d)\n"
+			, __func__, size + TXDESC_OFFSET, MAX_XMIT_EXTBUF_SZ);
+		return _FALSE;
+	}
+
+	pcmdframe = alloc_mgtxmitframe(pxmitpriv);
+
+	if (pcmdframe == NULL) {
+		RTW_INFO("%s: alloc ReservedPagePacket fail!\n", __func__);
+		return _FALSE;
+	}
+
+	api = HALMAC_GET_API(halmac);
+
+	rtw_halmac_get_tx_desc_size(pobj, &desclen);
+	buf = pcmdframe->buf_addr;
+	_rtw_memcpy(buf + desclen, pBuf, size); /* shift desclen */
+
+	SET_TX_DESC_TXPKTSIZE_8821C(buf, size);
+	SET_TX_DESC_OFFSET_8821C(buf, 0);
+	SET_TX_DESC_QSEL_8821C(buf, HALMAC_TXDESC_QSEL_H2C_CMD);
+	SET_TX_DESC_TXDESC_CHECKSUM_8821C(buf, 0);
+	api->halmac_fill_txdesc_checksum(halmac, buf);
+
+	/* update attribute */
+	pattrib = &pcmdframe->attrib;
+	update_mgntframe_attrib(padapter, pattrib);
+	pattrib->qsel = QSLT_CMD;
+	pattrib->pktlen = size;
+	pattrib->last_txcmdsz = size;
+
+	/* fill tx desc in dump_mgntframe */
+	dump_mgntframe(padapter, pcmdframe);
+
+	return _TRUE;
+}
+
+static u8 pci_write_data_rsvd_page(void *d, u8 *pBuf, u32 size)
+{
+	struct dvobj_priv *pobj = (struct dvobj_priv *)d;
+	PADAPTER padapter = dvobj_get_primary_adapter(pobj);
+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(padapter);
+	u8 ret;
+
+	if (pHalData->not_xmitframe_fw_dl)
+		ret = pci_write_data_not_xmitframe(d, pBuf, size, HALMAC_TXDESC_QSEL_BEACON);
+	else
+		ret = pci_write_data_rsvd_page_xmitframe(d, pBuf, size);
+
+	if (ret == _TRUE)
+		return 1;
+	return 0;
+}
+
+static u8 pci_write_data_h2c(void *d, u8 *pBuf, u32 size)
+{
+	struct dvobj_priv *pobj = (struct dvobj_priv *)d;
+	PADAPTER padapter = dvobj_get_primary_adapter(pobj);
+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(padapter);
+	u8 ret;
+
+	if (pHalData->not_xmitframe_fw_dl)
+		ret = pci_write_data_not_xmitframe(d, pBuf, size, HALMAC_TXDESC_QSEL_H2C_CMD);
+	else
+		ret = pci_write_data_h2c_normal(d, pBuf, size);
+
+	if (ret == _TRUE)
+		return 1;
+	return 0;
+}
+
+int rtl8821ce_halmac_init_adapter(PADAPTER padapter)
+{
+	struct dvobj_priv *d;
+	struct halmac_platform_api *api;
+	int err;
+
+#ifdef CONFIG_64BIT_DMA	
+	if (adapter_to_dvobj(padapter)->bdma64)
+		PlatformEnableDMA64(padapter);
+#endif
+
+	d = adapter_to_dvobj(padapter);
+	api = &rtw_halmac_platform_api;
+	api->SEND_RSVD_PAGE = pci_write_data_rsvd_page;
+	api->SEND_H2C_PKT = pci_write_data_h2c;
+
+	err = rtw_halmac_init_adapter(d, api);
+
+	return err;
+}
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/rtl8821c/pci/rtl8821ce_io.c linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/rtl8821c/pci/rtl8821ce_io.c
--- linux-5.6.3/3rdparty/rtl8821ce/hal/rtl8821c/pci/rtl8821ce_io.c	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/rtl8821c/pci/rtl8821ce_io.c	2020-04-10 16:35:06.843661328 +0300
@@ -0,0 +1,348 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2016 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#define _RTL8821CE_IO_C_
+
+#include <drv_types.h>		/* PADAPTER and etc. */
+
+#ifdef RTK_129X_PLATFORM
+#include <soc/realtek/rtd129x_lockapi.h>
+
+#define IO_2K_MASK 0xFFFFF800
+#define IO_4K_MASK 0xFFFFF000
+#define MAX_RETRY 5
+
+static u32 pci_io_read_129x(struct dvobj_priv *pdvobjpriv, u32 addr, u8 size)
+{
+	unsigned long mask_addr = pdvobjpriv->mask_addr;
+	unsigned long tran_addr = pdvobjpriv->tran_addr;
+	u8 busnumber = pdvobjpriv->pcipriv.busnumber;
+	u32 rval = 0;
+	u32 mask;
+	u32 translate_val = 0;
+	u32 tmp_addr = addr & 0xFFF;
+	_irqL irqL;
+	u32 pci_error_status = 0;
+	int retry_cnt = 0;
+	unsigned long flags;
+
+	_enter_critical(&pdvobjpriv->io_reg_lock, &irqL);
+
+	/* PCIE1.1 0x9804FCEC, PCIE2.0 0x9803CCEC & 0x9803CC68
+	 * can't be used because of 1295 hardware issue.
+	 */
+	if ((tmp_addr == 0xCEC) || ((busnumber == 0x01) &&
+	    (tmp_addr == 0xC68))) {
+		mask = IO_2K_MASK;
+		writel(0xFFFFF800, (u8 *)mask_addr);
+		translate_val = readl((u8 *)tran_addr);
+		writel(translate_val|(addr&mask), (u8 *)tran_addr);
+	} else if (addr >= 0x1000) {
+		mask = IO_4K_MASK;
+		translate_val = readl((u8 *)tran_addr);
+		writel(translate_val|(addr&mask), (u8 *)tran_addr);
+	} else
+		mask = 0x0;
+
+pci_read_129x_retry:
+
+	/* All RBUS1 driver need to have a workaround for emmc hardware error */
+	/* Need to protect 0xXXXX_X8XX~ 0xXXXX_X9XX */
+	if ((tmp_addr > 0x7FF) && (tmp_addr < 0xA00))
+		rtk_lockapi_lock(flags, __func__);
+
+	switch (size) {
+	case 1:
+		rval = readb((u8 *)pdvobjpriv->pci_mem_start + (addr&~mask));
+		break;
+	case 2:
+		rval = readw((u8 *)pdvobjpriv->pci_mem_start + (addr&~mask));
+		break;
+	case 4:
+		rval = readl((u8 *)pdvobjpriv->pci_mem_start + (addr&~mask));
+		break;
+	default:
+		RTW_WARN("RTD129X: %s: wrong size %d\n", __func__, size);
+		break;
+	}
+
+	if ((tmp_addr > 0x7FF) && (tmp_addr < 0xA00))
+		rtk_lockapi_unlock(flags, __func__);
+
+	/* DLLP error patch*/
+	pci_error_status = readl((u8 *)(pdvobjpriv->ctrl_start + 0x7C));
+
+	if (pci_error_status & 0x1F) {
+		writel(pci_error_status, (u8 *)(pdvobjpriv->ctrl_start + 0x7C));
+		RTW_WARN("RTD129X: %s: DLLP(#%d) 0x%x reg=0x%x val=0x%x\n",
+			__func__, retry_cnt, pci_error_status, addr, rval);
+
+		if (retry_cnt < MAX_RETRY) {
+			retry_cnt++;
+			goto pci_read_129x_retry;
+		}
+	}
+
+	/* PCIE1.1 0x9804FCEC, PCIE2.0 0x9803CCEC & 0x9803CC68
+	 * can't be used because of 1295 hardware issue.
+	 */
+	if ((tmp_addr == 0xCEC) || ((busnumber == 0x01) &&
+	    (tmp_addr == 0xC68))) {
+		writel(translate_val, (u8 *)tran_addr);
+		writel(0xFFFFF000, (u8 *)mask_addr);
+	} else if (addr >= 0x1000) {
+		writel(translate_val, (u8 *)tran_addr);
+	}
+
+	_exit_critical(&pdvobjpriv->io_reg_lock, &irqL);
+
+	return rval;
+}
+
+static void pci_io_write_129x(struct dvobj_priv *pdvobjpriv,
+			      u32 addr, u8 size, u32 wval)
+{
+	unsigned long mask_addr = pdvobjpriv->mask_addr;
+	unsigned long tran_addr = pdvobjpriv->tran_addr;
+	u8 busnumber = pdvobjpriv->pcipriv.busnumber;
+	u32 mask;
+	u32 translate_val = 0;
+	u32 tmp_addr = addr & 0xFFF;
+	_irqL irqL;
+	unsigned long flags;
+
+	_enter_critical(&pdvobjpriv->io_reg_lock, &irqL);
+
+	/* PCIE1.1 0x9804FCEC, PCIE2.0 0x9803CCEC & 0x9803CC68
+	 * can't be used because of 1295 hardware issue.
+	 */
+	if ((tmp_addr == 0xCEC) || ((busnumber == 0x01) &&
+	    (tmp_addr == 0xC68))) {
+		mask = IO_2K_MASK;
+		writel(0xFFFFF800, (u8 *)mask_addr);
+		translate_val = readl((u8 *)tran_addr);
+		writel(translate_val|(addr&mask), (u8 *)tran_addr);
+	} else if (addr >= 0x1000) {
+		mask = IO_4K_MASK;
+		translate_val = readl((u8 *)tran_addr);
+		writel(translate_val|(addr&mask), (u8 *)tran_addr);
+	} else
+		mask = 0x0;
+
+	/* All RBUS1 driver need to have a workaround for emmc hardware error */
+	/* Need to protect 0xXXXX_X8XX~ 0xXXXX_X9XX */
+	if ((tmp_addr > 0x7FF) && (tmp_addr < 0xA00))
+		rtk_lockapi_lock(flags, __func__);
+
+	switch (size) {
+	case 1:
+		writeb((u8)wval,
+		       (u8 *)pdvobjpriv->pci_mem_start + (addr&~mask));
+		break;
+	case 2:
+		writew((u16)wval,
+		       (u8 *)pdvobjpriv->pci_mem_start + (addr&~mask));
+		break;
+	case 4:
+		writel((u32)wval,
+		       (u8 *)pdvobjpriv->pci_mem_start + (addr&~mask));
+		break;
+	default:
+		RTW_WARN("RTD129X: %s: wrong size %d\n", __func__, size);
+		break;
+	}
+
+	if ((tmp_addr > 0x7FF) && (tmp_addr < 0xA00))
+		rtk_lockapi_unlock(flags, __func__);
+
+	/* PCIE1.1 0x9804FCEC, PCIE2.0 0x9803CCEC & 0x9803CC68
+	 * can't be used because of 1295 hardware issue.
+	 */
+	if ((tmp_addr == 0xCEC) || ((busnumber == 0x01) &&
+	    (tmp_addr == 0xC68))) {
+		writel(translate_val, (u8 *)tran_addr);
+		writel(0xFFFFF000, (u8 *)mask_addr);
+	} else if (addr >= 0x1000) {
+		writel(translate_val, (u8 *)tran_addr);
+	}
+
+	_exit_critical(&pdvobjpriv->io_reg_lock, &irqL);
+}
+
+static u8 pci_read8_129x(struct intf_hdl *phdl, u32 addr)
+{
+	struct dvobj_priv  *pdvobjpriv = (struct dvobj_priv  *)phdl->pintf_dev;
+
+	return (u8)pci_io_read_129x(pdvobjpriv, addr, 1);
+}
+
+static u16 pci_read16_129x(struct intf_hdl *phdl, u32 addr)
+{
+	struct dvobj_priv  *pdvobjpriv = (struct dvobj_priv  *)phdl->pintf_dev;
+
+	return (u16)pci_io_read_129x(pdvobjpriv, addr, 2);
+}
+
+static u32 pci_read32_129x(struct intf_hdl *phdl, u32 addr)
+{
+	struct dvobj_priv  *pdvobjpriv = (struct dvobj_priv  *)phdl->pintf_dev;
+
+	return (u32)pci_io_read_129x(pdvobjpriv, addr, 4);
+}
+
+/*
+ * 2009.12.23. by tynli. Suggested by SD1 victorh.
+ * For ASPM hang on AMD and Nvidia.
+ * 20100212 Tynli: Do read IO operation after write for
+ * all PCI bridge suggested by SD1. Origianally this is only for INTEL.
+ */
+static int pci_write8_129x(struct intf_hdl *phdl, u32 addr, u8 val)
+{
+	struct dvobj_priv  *pdvobjpriv = (struct dvobj_priv  *)phdl->pintf_dev;
+
+	pci_io_write_129x(pdvobjpriv, addr, 1, val);
+	return 1;
+}
+
+static int pci_write16_129x(struct intf_hdl *phdl, u32 addr, u16 val)
+{
+	struct dvobj_priv  *pdvobjpriv = (struct dvobj_priv  *)phdl->pintf_dev;
+
+	pci_io_write_129x(pdvobjpriv, addr, 2, val);
+	return 2;
+}
+
+static int pci_write32_129x(struct intf_hdl *phdl, u32 addr, u32 val)
+{
+	struct dvobj_priv  *pdvobjpriv = (struct dvobj_priv  *)phdl->pintf_dev;
+
+	pci_io_write_129x(pdvobjpriv, addr, 4, val);
+	return 4;
+}
+
+#else /* original*/
+
+static u8 pci_read8(struct intf_hdl *phdl, u32 addr)
+{
+	struct dvobj_priv *pdvobjpriv = (struct dvobj_priv *)phdl->pintf_dev;
+
+	return 0xff & readb((u8 *)pdvobjpriv->pci_mem_start + addr);
+}
+
+static u16 pci_read16(struct intf_hdl *phdl, u32 addr)
+{
+	struct dvobj_priv *pdvobjpriv = (struct dvobj_priv *)phdl->pintf_dev;
+
+	return readw((u8 *)pdvobjpriv->pci_mem_start + addr);
+}
+
+static u32 pci_read32(struct intf_hdl *phdl, u32 addr)
+{
+	struct dvobj_priv *pdvobjpriv = (struct dvobj_priv *)phdl->pintf_dev;
+
+	return readl((u8 *)pdvobjpriv->pci_mem_start + addr);
+}
+
+/*
+ * 2009.12.23. by tynli. Suggested by SD1 victorh.
+ * For ASPM hang on AMD and Nvidia.
+ * 20100212 Tynli: Do read IO operation after write for
+ * all PCI bridge suggested by SD1. Origianally this is only for INTEL.
+ */
+static int pci_write8(struct intf_hdl *phdl, u32 addr, u8 val)
+{
+	struct dvobj_priv *pdvobjpriv = (struct dvobj_priv *)phdl->pintf_dev;
+
+	writeb(val, (u8 *)pdvobjpriv->pci_mem_start + addr);
+	return 1;
+}
+
+static int pci_write16(struct intf_hdl *phdl, u32 addr, u16 val)
+{
+	struct dvobj_priv *pdvobjpriv = (struct dvobj_priv *)phdl->pintf_dev;
+
+	writew(val, (u8 *)pdvobjpriv->pci_mem_start + addr);
+	return 2;
+}
+
+static int pci_write32(struct intf_hdl *phdl, u32 addr, u32 val)
+{
+	struct dvobj_priv *pdvobjpriv = (struct dvobj_priv *)phdl->pintf_dev;
+
+	writel(val, (u8 *)pdvobjpriv->pci_mem_start + addr);
+	return 4;
+}
+#endif /* RTK_129X_PLATFORM */
+
+static void pci_read_mem(struct intf_hdl *phdl, u32 addr, u32 cnt, u8 *rmem)
+{
+	RTW_INFO("%s(%d)fake function\n", __func__, __LINE__);
+}
+
+static void pci_write_mem(struct intf_hdl *phdl, u32 addr, u32 cnt, u8 *wmem)
+{
+	RTW_INFO("%s(%d)fake function\n", __func__, __LINE__);
+}
+
+static u32 pci_read_port(struct intf_hdl *phdl, u32 addr, u32 cnt, u8 *rmem)
+{
+	return 0;
+}
+
+static u32 pci_write_port(struct intf_hdl *phdl, u32 addr, u32 cnt, u8 *wmem)
+{
+	_adapter *padapter = (_adapter *)phdl->padapter;
+
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 7, 0))
+	netif_trans_update(padapter->pnetdev);
+#else
+	padapter->pnetdev->trans_start = jiffies;
+#endif
+
+	return 0;
+}
+
+void rtl8821ce_set_intf_ops(struct _io_ops *pops)
+{
+
+	_rtw_memset((u8 *)pops, 0, sizeof(struct _io_ops));
+
+#ifdef RTK_129X_PLATFORM
+	pops->_read8 = &pci_read8_129x;
+	pops->_read16 = &pci_read16_129x;
+	pops->_read32 = &pci_read32_129x;
+#else
+	pops->_read8 = &pci_read8;
+	pops->_read16 = &pci_read16;
+	pops->_read32 = &pci_read32;
+#endif /* RTK_129X_PLATFORM */
+
+	pops->_read_mem = &pci_read_mem;
+	pops->_read_port = &pci_read_port;
+
+#ifdef RTK_129X_PLATFORM
+	pops->_write8 = &pci_write8_129x;
+	pops->_write16 = &pci_write16_129x;
+	pops->_write32 = &pci_write32_129x;
+#else
+	pops->_write8 = &pci_write8;
+	pops->_write16 = &pci_write16;
+	pops->_write32 = &pci_write32;
+#endif /* RTK_129X_PLATFORM */
+
+	pops->_write_mem = &pci_write_mem;
+	pops->_write_port = &pci_write_port;
+
+
+}
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/rtl8821c/pci/rtl8821ce_led.c linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/rtl8821c/pci/rtl8821ce_led.c
--- linux-5.6.3/3rdparty/rtl8821ce/hal/rtl8821c/pci/rtl8821ce_led.c	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/rtl8821c/pci/rtl8821ce_led.c	2020-04-10 16:35:06.843661328 +0300
@@ -0,0 +1,161 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2016 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+
+#include <drv_types.h>		/* PADAPTER */
+#include <hal_data.h>		/* PHAL_DATA_TYPE */
+#include <hal_com_led.h>	/* PLED_PCIE */
+
+#ifdef CONFIG_RTW_SW_LED
+
+/*
+ *==============================================================================
+ *	Prototype of protected function.
+ *==============================================================================
+ */
+
+/*
+ *==============================================================================
+ * LED_819xUsb routines.
+ *==============================================================================
+ */
+
+/*
+ * Description:
+ *	Turn on LED according to LedPin specified.
+ */
+static void SwLedOn_8821ce(PADAPTER adapter, PLED_PCIE pLed)
+{
+#if 0
+	u16 LedReg = REG_LEDCFG0;
+	u8 LedCfg = 0;
+	struct led_priv	*ledpriv = adapter_to_led(adapter);
+
+	if (RTW_CANNOT_RUN(adapter))
+		return;
+
+	switch (pLed->LedPin) {
+	case LED_PIN_LED0:
+		if (ledpriv->LedStrategy == SW_LED_MODE10)
+			LedReg = REG_LEDCFG0;
+		else
+			LedReg = REG_LEDCFG1;
+		break;
+
+	case LED_PIN_LED1:
+		LedReg = REG_LEDCFG2;
+		break;
+
+	case LED_PIN_GPIO0:
+	default:
+		break;
+	}
+
+	LedCfg = rtw_read8(adapter, LedReg);
+	LedCfg |= BIT5; /* Set 0x4c[21] */
+
+	/* Clear 0x4c[23:22] and 0x4c[19:16] */
+	LedCfg &= ~(BIT7 | BIT6 | BIT3 | BIT2 | BIT1 | BIT0);
+
+	/* SW control led0 on. */
+	rtw_write8(adapter, LedReg, LedCfg);
+	pLed->bLedOn = _TRUE;
+#else
+	RTW_INFO("%s(%d)TODO LED\n", __func__, __LINE__);
+#endif
+}
+
+
+/*
+ * Description:
+ *	Turn off LED according to LedPin specified.
+ */
+static void SwLedOff_8821ce(PADAPTER adapter, PLED_PCIE pLed)
+{
+#if 0
+	u16 LedReg = REG_LEDCFG0;
+	PHAL_DATA_TYPE hal = GET_HAL_DATA(adapter);
+	struct led_priv	*ledpriv = adapter_to_led(adapter);
+
+	if (RTW_CANNOT_RUN(adapter))
+		return;
+
+	switch (pLed->LedPin) {
+	case LED_PIN_LED0:
+		if (ledpriv->LedStrategy == SW_LED_MODE10)
+			LedReg = REG_LEDCFG0;
+		else
+			LedReg = REG_LEDCFG1;
+		break;
+
+	case LED_PIN_LED1:
+		LedReg = REG_LEDCFG2;
+		break;
+
+	case LED_PIN_GPIO0:
+	default:
+		break;
+	}
+
+	/* Open-drain arrangement for controlling the LED */
+	if (hal->bLedOpenDrain == _TRUE) {
+		u8 LedCfg = rtw_read8(adapter, LedReg);
+
+		LedCfg &= 0xd0; /* Set to software control. */
+		rtw_write8(adapter, LedReg, (LedCfg | BIT3));
+
+		/* Open-drain arrangement */
+		LedCfg = rtw_read8(adapter, REG_MAC_PINMUX_CFG);
+		LedCfg &= 0xFE;/* Set GPIO[8] to input mode */
+		rtw_write8(adapter, REG_MAC_PINMUX_CFG, LedCfg);
+
+	} else
+		rtw_write8(adapter, LedReg, 0x28);
+
+	pLed->bLedOn = _FALSE;
+#else
+	RTW_INFO("%s(%d)TODO LED\n", __func__, __LINE__);
+#endif
+}
+
+/*
+ * Description:
+ *	Initialize all LED_871x objects.
+ */
+void rtl8821ce_InitSwLeds(PADAPTER adapter)
+{
+	struct led_priv *pledpriv = adapter_to_led(adapter);
+
+	pledpriv->LedControlHandler = LedControlPCIE;
+
+	pledpriv->SwLedOn = SwLedOn_8821ce;
+	pledpriv->SwLedOff = SwLedOff_8821ce;
+
+	InitLed(adapter, &pledpriv->SwLed0, LED_PIN_LED0);
+	InitLed(adapter, &pledpriv->SwLed1, LED_PIN_LED1);
+}
+
+
+/*
+ * Description:
+ *	DeInitialize all LED_819xUsb objects.
+ */
+void rtl8821ce_DeInitSwLeds(PADAPTER adapter)
+{
+	struct led_priv	*ledpriv = adapter_to_led(adapter);
+
+	DeInitLed(&ledpriv->SwLed0);
+	DeInitLed(&ledpriv->SwLed1);
+}
+#endif
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/rtl8821c/pci/rtl8821ce_ops.c linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/rtl8821c/pci/rtl8821ce_ops.c
--- linux-5.6.3/3rdparty/rtl8821ce/hal/rtl8821c/pci/rtl8821ce_ops.c	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/rtl8821c/pci/rtl8821ce_ops.c	2020-04-10 16:35:06.843661328 +0300
@@ -0,0 +1,834 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2016 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+
+#define _HCI_OPS_OS_C_
+
+#include <drv_types.h>		/* PADAPTER, basic_types.h and etc. */
+#include <hal_data.h>		/* HAL_DATA_TYPE, GET_HAL_DATA() and etc. */
+#include <hal_intf.h>		/* struct hal_ops */
+#include "../rtl8821c.h"
+#include "rtl8821ce.h"
+
+static void init_bd_ring_var(_adapter *padapter)
+{
+	struct recv_priv *r_priv = &padapter->recvpriv;
+	struct xmit_priv *t_priv = &padapter->xmitpriv;
+	u8 i = 0;
+
+	for (i = 0; i < HW_QUEUE_ENTRY; i++)
+		t_priv->txringcount[i] = TX_BD_NUM_8821CE;
+
+	/*
+	 * we just alloc 2 desc for beacon queue,
+	 * because we just need first desc in hw beacon.
+	 */
+	t_priv->txringcount[BCN_QUEUE_INX] = TX_BD_NUM_8821CE_BCN;
+	t_priv->txringcount[TXCMD_QUEUE_INX] = TX_BD_NUM_8821CE_CMD;
+
+	/*
+	 * BE queue need more descriptor for performance consideration
+	 * or, No more tx desc will happen, and may cause mac80211 mem leakage.
+	 */
+	r_priv->rxbuffersize = MAX_RECVBUF_SZ;
+	r_priv->rxringcount = PCI_MAX_RX_COUNT;
+}
+
+static void rtl8821ce_reset_bd(_adapter *padapter)
+{
+	_irqL	irqL;
+	struct xmit_priv *t_priv = &padapter->xmitpriv;
+	struct recv_priv *r_priv = &padapter->recvpriv;
+	struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(padapter);
+	struct xmit_buf	*pxmitbuf = NULL;
+	u8 *tx_bd, *rx_bd;
+	int i, rx_queue_idx;
+	dma_addr_t mapping;
+
+	for (rx_queue_idx = 0; rx_queue_idx < 1; rx_queue_idx++) {
+		if (r_priv->rx_ring[rx_queue_idx].buf_desc) {
+			rx_bd = NULL;
+			for (i = 0; i < r_priv->rxringcount; i++) {
+				rx_bd = (u8 *)
+					&r_priv->rx_ring[rx_queue_idx].buf_desc[i];
+			}
+			r_priv->rx_ring[rx_queue_idx].idx = 0;
+		}
+	}
+
+	_enter_critical(&pdvobjpriv->irq_th_lock, &irqL);
+	for (i = 0; i < PCI_MAX_TX_QUEUE_COUNT; i++) {
+		if (t_priv->tx_ring[i].buf_desc) {
+			struct rtw_tx_ring *ring = &t_priv->tx_ring[i];
+
+			while (ring->qlen) {
+				tx_bd = (u8 *)(&ring->buf_desc[ring->idx]);
+				SET_TX_BD_OWN(tx_bd, 0);
+
+				if (i != BCN_QUEUE_INX)
+					ring->idx =
+						(ring->idx + 1) % ring->entries;
+
+				pxmitbuf = rtl8821ce_dequeue_xmitbuf(ring);
+				if (pxmitbuf) {
+					mapping = GET_TX_BD_PHYSICAL_ADDR0_LOW(tx_bd);
+				#ifdef CONFIG_64BIT_DMA
+					mapping |= (dma_addr_t)GET_TX_BD_PHYSICAL_ADDR0_HIGH(tx_bd) << 32;
+				#endif
+					pci_unmap_single(pdvobjpriv->ppcidev,
+						mapping,
+						pxmitbuf->len, PCI_DMA_TODEVICE);
+					rtw_free_xmitbuf(t_priv, pxmitbuf);
+				} else {
+					RTW_INFO("%s(): qlen(%d) is not zero, but have xmitbuf in pending queue\n",
+						 __func__, ring->qlen);
+					break;
+				}
+			}
+			ring->idx = 0;
+		}
+	}
+	_exit_critical(&pdvobjpriv->irq_th_lock, &irqL);
+}
+
+static void intf_chip_configure(PADAPTER padapter)
+{
+	HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
+	struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(padapter);
+	struct pwrctrl_priv *pwrpriv = dvobj_to_pwrctl(pdvobjpriv);
+
+	/* close ASPM for AMD defaultly */
+	pdvobjpriv->const_amdpci_aspm = 0;
+
+	/* ASPM PS mode. */
+	/* 0 - Disable ASPM, 1 - Enable ASPM without Clock Req, */
+	/* 2 - Enable ASPM with Clock Req, 3- Alwyas Enable ASPM with Clock Req, */
+	/* 4-  Always Enable ASPM without Clock Req. */
+	/* set default to rtl8188ee:3 RTL8192E:2 */
+	pdvobjpriv->const_pci_aspm = 0;
+
+	/* Setting for PCI-E device */
+	pdvobjpriv->const_devicepci_aspm_setting = 0x03;
+
+	/* Setting for PCI-E bridge */
+	pdvobjpriv->const_hostpci_aspm_setting = 0x03;
+
+	/* In Hw/Sw Radio Off situation. */
+	/* 0 - Default, 1 - From ASPM setting without low Mac Pwr, */
+	/* 2 - From ASPM setting with low Mac Pwr, 3 - Bus D3 */
+	/* set default to RTL8192CE:0 RTL8192SE:2 */
+	pdvobjpriv->const_hwsw_rfoff_d3 = 0;
+
+	/* This setting works for those device with backdoor ASPM setting such as EPHY setting. */
+	/* 0: Not support ASPM, 1: Support ASPM, 2: According to chipset. */
+	pdvobjpriv->const_support_pciaspm = 1;
+
+	pwrpriv->reg_rfoff = 0;
+	pwrpriv->rfoff_reason = 0;
+
+	pHalData->bL1OffSupport = _FALSE;
+}
+
+/*
+ * Description:
+ *	Collect all hardware information, fill "HAL_DATA_TYPE".
+ *	Sometimes this would be used to read MAC address.
+ *	This function will do
+ *	1. Read Efuse/EEPROM to initialize
+ *	2. Read registers to initialize
+ *	3. Other vaiables initialization
+ */
+static u8 read_adapter_info(PADAPTER padapter)
+{
+	u8 ret = _FAIL;
+
+	/*
+	 * 1. Read Efuse/EEPROM to initialize
+	 */
+	if (rtl8821c_read_efuse(padapter) != _SUCCESS)
+		goto exit;
+
+	/*
+	 * 2. Read registers to initialize
+	 */
+
+	/*
+	 * 3. Other Initialization
+	 */
+
+	ret = _SUCCESS;
+
+exit:
+	return ret;
+}
+
+static BOOLEAN rtl8821ce_InterruptRecognized(PADAPTER Adapter)
+{
+	HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
+	BOOLEAN bRecognized = _FALSE;
+
+	/* 2013.11.18 Glayrainx suggests that turn off IMR and
+	 * restore after cleaning ISR.
+	 */
+	rtw_write32(Adapter, REG_HIMR0, 0);
+	rtw_write32(Adapter, REG_HIMR1, 0);
+	rtw_write32(Adapter, REG_HIMR3, 0);
+
+	pHalData->IntArray[0] = rtw_read32(Adapter, REG_HISR0);
+	pHalData->IntArray[0] &= pHalData->IntrMask[0];
+	rtw_write32(Adapter, REG_HISR0, pHalData->IntArray[0]);
+
+	/* For HISR extension. Added by tynli. 2009.10.07. */
+	pHalData->IntArray[1] = rtw_read32(Adapter, REG_HISR1);
+	pHalData->IntArray[1] &= pHalData->IntrMask[1];
+	rtw_write32(Adapter, REG_HISR1, pHalData->IntArray[1]);
+
+	/* for H2C cmd queue */
+	pHalData->IntArray[3] = rtw_read32(Adapter, REG_HISR3);
+	pHalData->IntArray[3] &= pHalData->IntrMask[3];
+	rtw_write32(Adapter, REG_HISR3, pHalData->IntArray[3]);
+
+	if (((pHalData->IntArray[0]) & pHalData->IntrMask[0]) != 0 ||
+	    ((pHalData->IntArray[1]) & pHalData->IntrMask[1]) != 0)
+		bRecognized = _TRUE;
+
+	/* restore IMR */
+	rtw_write32(Adapter, REG_HIMR0, pHalData->IntrMask[0] & 0xFFFFFFFF);
+	rtw_write32(Adapter, REG_HIMR1, pHalData->IntrMask[1] & 0xFFFFFFFF);
+	rtw_write32(Adapter, REG_HIMR3, pHalData->IntrMask[3] & 0xFFFFFFFF);
+
+	return bRecognized;
+}
+
+static VOID DisableInterrupt8821ce(PADAPTER Adapter)
+{
+	struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(Adapter);
+
+	rtw_write32(Adapter, REG_HIMR0, 0x0);
+	rtw_write32(Adapter, REG_HIMR1, 0x0);
+	rtw_write32(Adapter, REG_HIMR3, 0x0);
+	pdvobjpriv->irq_enabled = 0;
+}
+
+static VOID rtl8821ce_enable_interrupt(PADAPTER Adapter)
+{
+	HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
+	struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(Adapter);
+
+	pdvobjpriv->irq_enabled = 1;
+
+	rtw_write32(Adapter, REG_HIMR0, pHalData->IntrMask[0] & 0xFFFFFFFF);
+	rtw_write32(Adapter, REG_HIMR1, pHalData->IntrMask[1] & 0xFFFFFFFF);
+	rtw_write32(Adapter, REG_HIMR3, pHalData->IntrMask[3] & 0xFFFFFFFF);
+
+}
+
+static VOID rtl8821ce_clear_interrupt(PADAPTER Adapter)
+{
+	u32 u32b;
+	HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(Adapter);
+
+	u32b = rtw_read32(Adapter, REG_HISR0_8821C);
+	rtw_write32(Adapter, REG_HISR0_8821C, u32b);
+	pHalData->IntArray[0] = 0;
+
+	u32b = rtw_read32(Adapter, REG_HISR1_8821C);
+	rtw_write32(Adapter, REG_HISR1_8821C, u32b);
+	pHalData->IntArray[1] = 0;
+}
+
+static VOID rtl8821ce_disable_interrupt(PADAPTER Adapter)
+{
+	struct dvobj_priv	*pdvobjpriv = adapter_to_dvobj(Adapter);
+
+	rtw_write32(Adapter, REG_HIMR0, 0x0);
+	rtw_write32(Adapter, REG_HIMR1, 0x0);	/* by tynli */
+	pdvobjpriv->irq_enabled = 0;
+}
+
+VOID UpdateInterruptMask8821CE(PADAPTER Adapter, u32 AddMSR, u32 AddMSR1,
+			       u32 RemoveMSR, u32 RemoveMSR1)
+{
+	PHAL_DATA_TYPE pHalData = GET_HAL_DATA(Adapter);
+
+	DisableInterrupt8821ce(Adapter);
+
+	if (AddMSR)
+		pHalData->IntrMask[0] |= AddMSR;
+
+	if (AddMSR1)
+		pHalData->IntrMask[1] |= AddMSR1;
+
+	if (RemoveMSR)
+		pHalData->IntrMask[0] &= (~RemoveMSR);
+
+	if (RemoveMSR1)
+		pHalData->IntrMask[1] &= (~RemoveMSR1);
+
+#if 0 /* TODO */
+	if (RemoveMSR3)
+		pHalData->IntrMask[3] &= (~RemoveMSR3);
+#endif
+
+	rtl8821ce_enable_interrupt(Adapter);
+}
+
+static void rtl8821ce_bcn_handler(PADAPTER Adapter, u32 handled[])
+{
+	PHAL_DATA_TYPE pHalData = GET_HAL_DATA(Adapter);
+
+	if (pHalData->IntArray[0] & BIT_TXBCN0OK_MSK) {
+#ifdef CONFIG_BCN_ICF
+		/* do nothing */
+#else
+		/* Modify for MI temporary,
+		 * this processor cannot apply to multi-ap
+		 */
+		PADAPTER bcn_adapter = rtw_mi_get_ap_adapter(Adapter);
+
+		if (bcn_adapter->xmitpriv.beaconDMAing) {
+			bcn_adapter->xmitpriv.beaconDMAing = _FAIL;
+			rtl8821ce_tx_isr(Adapter, BCN_QUEUE_INX);
+		}
+#endif /* CONFIG_BCN_ICF */
+		handled[0] |= BIT_TXBCN0OK_MSK;
+	}
+
+	if (pHalData->IntArray[0] & BIT_TXBCN0ERR_MSK) {
+#ifdef CONFIG_BCN_ICF
+		RTW_INFO("IMR_TXBCN0ERR isr!\n");
+#else /* !CONFIG_BCN_ICF */
+		/* Modify for MI temporary,
+		 * this processor cannot apply to multi-ap
+		 */
+		PADAPTER bcn_adapter = rtw_mi_get_ap_adapter(Adapter);
+
+		if (bcn_adapter->xmitpriv.beaconDMAing) {
+			bcn_adapter->xmitpriv.beaconDMAing = _FAIL;
+			rtl8821ce_tx_isr(Adapter, BCN_QUEUE_INX);
+		}
+#endif /* CONFIG_BCN_ICF */
+		handled[0] |= BIT_TXBCN0ERR_MSK;
+	}
+
+	if (pHalData->IntArray[0] & BIT_BCNDERR0_MSK) {
+#ifdef CONFIG_BCN_ICF
+		RTW_INFO("BIT_BCNDERR0_MSK isr!\n");
+#else /* !CONFIG_BCN_ICF */
+		/* Release resource and re-transmit beacon to HW */
+		struct tasklet_struct  *bcn_tasklet;
+		/* Modify for MI temporary,
+		 * this processor cannot apply to multi-ap
+		 */
+		PADAPTER bcn_adapter = rtw_mi_get_ap_adapter(Adapter);
+
+		rtl8821ce_tx_isr(Adapter, BCN_QUEUE_INX);
+		bcn_adapter->mlmepriv.update_bcn = _TRUE;
+		bcn_tasklet = &bcn_adapter->recvpriv.irq_prepare_beacon_tasklet;
+		tasklet_hi_schedule(bcn_tasklet);
+#endif /* CONFIG_BCN_ICF */
+		handled[0] |= BIT_BCNDERR0_MSK;
+	}
+
+	if (pHalData->IntArray[0] & BIT_BCNDMAINT0_MSK) {
+		struct tasklet_struct  *bcn_tasklet;
+		/* Modify for MI temporary,
+		*   this processor cannot apply to multi-ap
+		*/
+		PADAPTER bcn_adapter = rtw_mi_get_ap_adapter(Adapter);
+
+		bcn_tasklet = &bcn_adapter->recvpriv.irq_prepare_beacon_tasklet;
+		tasklet_hi_schedule(bcn_tasklet);
+		handled[0] |= BIT_BCNDMAINT0_MSK;
+	}
+}
+
+static void rtl8821ce_rx_handler(PADAPTER Adapter, u32 handled[])
+{
+	PHAL_DATA_TYPE pHalData = GET_HAL_DATA(Adapter);
+
+	if ((pHalData->IntArray[0] & (BIT_RXOK | BIT_RDU)) ||
+	    (pHalData->IntArray[1] & (BIT_FOVW | BIT_RXERR_INT))) {
+		pHalData->IntrMask[0] &= (~(BIT_RXOK_MSK | BIT_RDU_MSK));
+		pHalData->IntrMask[1] &= (~(BIT_FOVW_MSK | BIT_RXERR_MSK));
+		rtw_write32(Adapter, REG_HIMR0, pHalData->IntrMask[0]);
+		rtw_write32(Adapter, REG_HIMR1, pHalData->IntrMask[1]);
+		tasklet_hi_schedule(&Adapter->recvpriv.recv_tasklet);
+		handled[0] |= pHalData->IntArray[0] & (BIT_RXOK | BIT_RDU);
+		handled[1] |= pHalData->IntArray[1] & (BIT_FOVW | BIT_RXERR_INT);
+	}
+}
+
+static void rtl8821ce_tx_handler(PADAPTER Adapter, u32 events[], u32 handled[])
+{
+	PHAL_DATA_TYPE pHalData = GET_HAL_DATA(Adapter);
+
+	if (events[0] & BIT_MGTDOK_MSK) {
+		rtl8821ce_tx_isr(Adapter, MGT_QUEUE_INX);
+		handled[0] |= BIT_MGTDOK_MSK;
+	}
+
+	if (events[0] & BIT_HIGHDOK_MSK) {
+		rtl8821ce_tx_isr(Adapter, HIGH_QUEUE_INX);
+		handled[0] |= BIT_HIGHDOK_MSK;
+	}
+
+	if (events[0] & BIT_BKDOK_MSK) {
+		rtl8821ce_tx_isr(Adapter, BK_QUEUE_INX);
+		handled[0] |= BIT_BKDOK_MSK;
+	}
+
+	if (events[0] & BIT_BEDOK_MSK) {
+		rtl8821ce_tx_isr(Adapter, BE_QUEUE_INX);
+		handled[0] |= BIT_BEDOK_MSK;
+	}
+
+	if (events[0] & BIT_VIDOK_MSK) {
+		rtl8821ce_tx_isr(Adapter, VI_QUEUE_INX);
+		handled[0] |= BIT_VIDOK_MSK;
+	}
+
+	if (events[0] & BIT_VODOK_MSK) {
+		rtl8821ce_tx_isr(Adapter, VO_QUEUE_INX);
+		handled[0] |= BIT_VODOK_MSK;
+	}
+}
+
+static void rtl8821ce_cmd_handler(PADAPTER Adapter, u32 handled[])
+{
+	PHAL_DATA_TYPE pHalData = GET_HAL_DATA(Adapter);
+
+	if (pHalData->IntArray[3] & BIT_SETH2CDOK_MASK) {
+		rtl8821ce_tx_isr(Adapter, TXCMD_QUEUE_INX);
+		handled[3] |= BIT_SETH2CDOK_MASK;
+	}
+}
+
+static s32 rtl8821ce_interrupt(PADAPTER Adapter)
+{
+	_irqL irqL;
+	HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
+	struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(Adapter);
+	struct xmit_priv *t_priv = &Adapter->xmitpriv;
+	int ret = _SUCCESS;
+	u32 handled[4] = {0};
+
+	_enter_critical(&pdvobjpriv->irq_th_lock, &irqL);
+
+	/* read ISR: 4/8bytes */
+	if (rtl8821ce_InterruptRecognized(Adapter) == _FALSE) {
+		ret = _FAIL;
+		goto done;
+	}
+
+	/* <1> beacon related */
+	rtl8821ce_bcn_handler(Adapter, handled);
+
+	/* <2> Rx related */
+	rtl8821ce_rx_handler(Adapter, handled);
+
+	/* <3> Tx related */
+	rtl8821ce_tx_handler(Adapter, pHalData->IntArray, handled);
+
+	if (pHalData->IntArray[1] & BIT_TXFOVW) {
+		/*if (printk_ratelimit())*/
+		RTW_WARN("[TXFOVW]\n");
+		handled[1] |= BIT_TXFOVW;
+	}
+
+	if (pHalData->IntArray[1] & BIT_PRETXERR_HANDLE_ISR) {
+		RTW_ERR("[PRE-TX HANG]\n");
+		handled[1] |= BIT_PRETXERR_HANDLE_ISR;
+	}
+
+	/* <4> Cmd related */
+	rtl8821ce_cmd_handler(Adapter, handled);
+
+#ifdef CONFIG_LPS_LCLK
+	if (pHalData->IntArray[0] & BIT_CPWM) {
+		struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(Adapter);
+
+		_set_workitem(&(pwrpriv->cpwm_event));
+		handled[0] |= BIT_CPWM;
+	}
+#endif
+
+	if ((pHalData->IntArray[0] & (~handled[0])) || (pHalData->IntArray[1] & (~handled[1])) || (pHalData->IntArray[3] & (~handled[3]))) {
+		/*if (printk_ratelimit()) */
+		{
+			RTW_WARN("Unhandled ISR = %x, %x, %x\n",
+				(pHalData->IntArray[0] & (~handled[0])),
+				(pHalData->IntArray[1] & (~handled[1])),
+				(pHalData->IntArray[3] & (~handled[3]))
+			);
+		}
+	}
+done:
+	_exit_critical(&pdvobjpriv->irq_th_lock, &irqL);
+	return ret;
+}
+
+u32 rtl8821ce_init_bd(_adapter *padapter)
+{
+	struct xmit_priv *t_priv = &padapter->xmitpriv;
+	int	i, ret = _SUCCESS;
+
+	init_bd_ring_var(padapter);
+	ret = rtl8821ce_init_rxbd_ring(padapter);
+
+	if (ret == _FAIL)
+		return ret;
+
+	/* general process for other queue */
+	for (i = 0; i < PCI_MAX_TX_QUEUE_COUNT; i++) {
+		ret = rtl8821ce_init_txbd_ring(padapter, i,
+					       t_priv->txringcount[i]);
+		if (ret == _FAIL)
+			goto err_free_rings;
+	}
+
+	return ret;
+
+err_free_rings:
+
+	rtl8821ce_free_rxbd_ring(padapter);
+
+	for (i = 0; i < PCI_MAX_TX_QUEUE_COUNT; i++)
+		if (t_priv->tx_ring[i].buf_desc)
+			rtl8821ce_free_txbd_ring(padapter, i);
+
+
+	return ret;
+}
+
+u32 rtl8821ce_free_bd(_adapter *padapter)
+{
+	struct xmit_priv	*t_priv = &padapter->xmitpriv;
+	u32 i;
+
+
+	/* free rxbd rings */
+	rtl8821ce_free_rxbd_ring(padapter);
+
+	/* free txbd rings */
+	for (i = 0; i < HW_QUEUE_ENTRY; i++)
+		rtl8821ce_free_txbd_ring(padapter, i);
+
+
+	return _SUCCESS;
+}
+
+
+static u16
+hal_mdio_read_8821ce(PADAPTER Adapter, u8 Addr)
+{
+	u2Byte ret = 0;
+	u1Byte tmpU1b = 0, count = 0;
+
+	rtw_write8(Adapter, REG_PCIE_MIX_CFG_8821C, Addr | BIT6);
+	tmpU1b = rtw_read8(Adapter, REG_PCIE_MIX_CFG_8821C) & BIT6;
+	count = 0;
+	while (tmpU1b && count < 20) {
+		rtw_udelay_os(10);
+		tmpU1b = rtw_read8(Adapter, REG_PCIE_MIX_CFG_8821C) & BIT6;
+		count++;
+	}
+	if (tmpU1b == 0)
+		ret = rtw_read16(Adapter, REG_MDIO_V1_8821C);
+
+	return ret;
+}
+
+
+static VOID
+hal_mdio_write_8821ce(PADAPTER Adapter, u8 Addr, u16 Data)
+{
+	u1Byte tmpU1b = 0, count = 0;
+
+	rtw_write16(Adapter, REG_MDIO_V1_8821C, Data);
+	rtw_write8(Adapter, REG_PCIE_MIX_CFG_8821C, Addr | BIT5);
+	tmpU1b = rtw_read8(Adapter, REG_PCIE_MIX_CFG_8821C) & BIT5;
+	count = 0;
+	while (tmpU1b && count < 20) {
+		rtw_udelay_os(10);
+		tmpU1b = rtw_read8(Adapter, REG_PCIE_MIX_CFG_8821C) & BIT5;
+		count++;
+	}
+}
+
+
+static void hal_dbi_write_8821ce(PADAPTER Adapter, u16 Addr, u8 Data)
+{
+	u1Byte tmpU1b = 0, count = 0;
+	u2Byte WriteAddr = 0, Remainder = Addr % 4;
+
+	/* Write DBI 1Byte Data */
+	WriteAddr = REG_DBI_WDATA_V1_8821C + Remainder;
+	rtw_write8(Adapter, WriteAddr, Data);
+
+	/* Write DBI 2Byte Address & Write Enable */
+	WriteAddr = (Addr & 0xfffc) | (BIT0 << (Remainder + 12));
+	rtw_write16(Adapter, REG_DBI_FLAG_V1_8821C, WriteAddr);
+
+	/* Write DBI Write Flag */
+	rtw_write8(Adapter, REG_DBI_FLAG_V1_8821C + 2, 0x1);
+
+	tmpU1b = rtw_read8(Adapter, REG_DBI_FLAG_V1_8821C + 2);
+	count = 0;
+	while (tmpU1b && count < 20) {
+		rtw_udelay_os(10);
+		tmpU1b = rtw_read8(Adapter, REG_DBI_FLAG_V1_8821C + 2);
+		count++;
+	}
+}
+
+static u8 hal_dbi_read_8821ce(PADAPTER Adapter, u16 Addr)
+{
+	u16 ReadAddr = Addr & 0xfffc;
+	u8 ret = 0, tmpU1b = 0, count = 0;
+
+	rtw_write16(Adapter, REG_DBI_FLAG_V1_8821C, ReadAddr);
+	rtw_write8(Adapter, REG_DBI_FLAG_V1_8821C + 2, 0x2);
+	tmpU1b = rtw_read8(Adapter, REG_DBI_FLAG_V1_8821C + 2);
+	count = 0;
+	while (tmpU1b && count < 20) {
+		rtw_udelay_os(10);
+		tmpU1b = rtw_read8(Adapter, REG_DBI_FLAG_V1_8821C + 2);
+		count++;
+	}
+	if (tmpU1b == 0) {
+		ReadAddr = REG_DBI_RDATA_V1_8821C + Addr % 4;
+		ret = rtw_read8(Adapter, ReadAddr);
+	}
+
+	return ret;
+}
+
+/*
+*	Description:
+*		Query setting of specified variable.
+*/
+static u8 gethaldefvar(PADAPTER	padapter, HAL_DEF_VARIABLE eVariable, PVOID pValue)
+{
+	HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
+	u8 bResult = _SUCCESS;
+
+	switch (eVariable) {
+
+	case HAL_DEF_MAX_RECVBUF_SZ:
+		*((u32 *)pValue) = MAX_RECVBUF_SZ;
+		break;
+
+	case HW_VAR_MAX_RX_AMPDU_FACTOR:
+		*(HT_CAP_AMPDU_FACTOR *)pValue = MAX_AMPDU_FACTOR_64K;
+		break;
+	default:
+		bResult = rtl8821c_gethaldefvar(padapter, eVariable, pValue);
+		break;
+	}
+
+	return bResult;
+}
+
+/*
+ * Description:
+ *	Change default setting of specified variable.
+ */
+static u8 sethaldefvar(PADAPTER adapter, HAL_DEF_VARIABLE eVariable, void *pval)
+{
+	PHAL_DATA_TYPE hal = GET_HAL_DATA(adapter);
+	u8 bResult = _SUCCESS;
+
+	switch (eVariable) {
+	default:
+		bResult = rtl8821c_sethaldefvar(adapter, eVariable, pval);
+		break;
+	}
+
+	return bResult;
+}
+
+/*
+ * If variable not handled here,
+ * some variables will be processed in rtl8821c_sethwreg()
+ */
+static u8 sethwreg(PADAPTER adapter, u8 variable, u8 *val)
+{
+	PHAL_DATA_TYPE hal;
+	u8 ret = _SUCCESS;
+	u8 val8;
+
+
+	hal = GET_HAL_DATA(adapter);
+
+	switch (variable) {
+
+	case HW_VAR_DBI:
+	{
+		u16 *pCmd;
+
+		pCmd = (u16 *)val;
+		hal_dbi_write_8821ce(adapter, pCmd[0], (u8)pCmd[1]);
+		break;
+	}
+	case HW_VAR_MDIO:
+	{
+		u16 *pCmd;
+
+		pCmd = (u16 *)val;
+		hal_mdio_write_8821ce(adapter, (u8)pCmd[0], pCmd[1]);
+		break;
+	}
+#ifdef CONFIG_LPS_LCLK
+	case HW_VAR_SET_RPWM:
+	{
+		u8 ps_state = *((u8 *)val);
+		/* rpwm value only use BIT0(clock bit) ,BIT6(Ack bit), and BIT7(Toggle bit) for 88e. */
+		/* BIT0 value - 1: 32k, 0:40MHz. */
+		/* BIT6 value - 1: report cpwm value after success set, 0:do not report. */
+		/* BIT7 value - Toggle bit change. */
+		/* modify by Thomas. 2012/4/2. */
+		ps_state = ps_state & 0xC1;
+		/* RTW_INFO("##### Change RPWM value to = %x for switch clk #####\n",ps_state); */
+		rtw_write8(adapter, REG_PCIE_HRPWM1_V1_8821C, ps_state);
+		break;
+	}
+#endif
+
+	default:
+		ret = rtl8821c_sethwreg(adapter, variable, val);
+		break;
+	}
+
+	return ret;
+}
+
+/*
+ * If variable not handled here,
+ * some variables will be processed in GetHwReg8723B()
+ */
+static void gethwreg(PADAPTER adapter, u8 variable, u8 *val)
+{
+	PHAL_DATA_TYPE hal;
+
+
+	hal = GET_HAL_DATA(adapter);
+	switch (variable) {
+	case HW_VAR_DBI:
+		*val = hal_dbi_read_8821ce(adapter, *((u16 *)(val)));
+		break;
+	case HW_VAR_MDIO:
+		*((u16 *)(val)) = hal_mdio_read_8821ce(adapter, *val);
+		break;
+	case HW_VAR_L1OFF_NIC_SUPPORT:
+		{
+		u8 l1off;
+
+		l1off = hal_dbi_read_8821ce(adapter, 0x168);
+		if (l1off & (BIT2|BIT3))
+			*val = _TRUE;
+		else
+			*val = _FALSE;
+		}
+		break;
+	case HW_VAR_L1OFF_CAPABILITY:
+		{
+		u8 l1off;
+
+		l1off = hal_dbi_read_8821ce(adapter, 0x164);
+		if (l1off & (BIT2|BIT3))
+			*val = _TRUE;
+		else
+			*val = _FALSE;
+		}
+		break;
+
+#ifdef CONFIG_LPS_LCLK
+	case HW_VAR_CPWM:
+		*val = rtw_read8(adapter, REG_PCIE_HCPWM1_V1_8821C);
+		break;
+#endif
+
+	default:
+		rtl8821c_gethwreg(adapter, variable, val);
+		break;
+	}
+}
+
+void rtl8821ce_set_hal_ops(PADAPTER padapter)
+{
+	struct hal_ops *ops;
+	int err;
+
+	err = rtl8821ce_halmac_init_adapter(padapter);
+	if (err) {
+		RTW_INFO("%s: [ERROR]HALMAC initialize FAIL!\n", __func__);
+		return;
+	}
+
+	rtl8821c_set_hal_ops(padapter);
+
+	ops = &padapter->hal_func;
+
+	ops->hal_init = rtl8821ce_hal_init;
+	ops->hal_deinit = rtl8821ce_hal_deinit;
+	ops->inirp_init = rtl8821ce_init_bd;
+	ops->inirp_deinit = rtl8821ce_free_bd;
+	ops->irp_reset = rtl8821ce_reset_bd;
+	ops->init_xmit_priv = rtl8821ce_init_xmit_priv;
+	ops->free_xmit_priv = rtl8821ce_free_xmit_priv;
+	ops->init_recv_priv = rtl8821ce_init_recv_priv;
+	ops->free_recv_priv = rtl8821ce_free_recv_priv;
+
+#ifdef CONFIG_RTW_SW_LED
+	ops->InitSwLeds = rtl8821ce_InitSwLeds;
+	ops->DeInitSwLeds = rtl8821ce_DeInitSwLeds;
+#endif
+
+	ops->init_default_value = rtl8821ce_init_default_value;
+	ops->intf_chip_configure = intf_chip_configure;
+	ops->read_adapter_info = read_adapter_info;
+
+	ops->enable_interrupt = rtl8821ce_enable_interrupt;
+	ops->disable_interrupt = rtl8821ce_disable_interrupt;
+	ops->interrupt_handler = rtl8821ce_interrupt;
+	/*
+	* ops->check_ips_status = check_ips_status;
+	*/
+	ops->clear_interrupt = rtl8821ce_clear_interrupt;
+#if defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN) ||\
+	defined(CONFIG_PCI_HCI)
+	/*
+	* ops->clear_interrupt = clear_interrupt_all;
+	*/
+#endif
+
+	ops->set_hw_reg_handler = sethwreg;
+	ops->GetHwRegHandler = gethwreg;
+	ops->get_hal_def_var_handler = gethaldefvar;
+	ops->SetHalDefVarHandler = sethaldefvar;
+
+	ops->hal_xmit = rtl8821ce_hal_xmit;
+	ops->mgnt_xmit = rtl8821ce_mgnt_xmit;
+	ops->hal_xmitframe_enqueue = rtl8821ce_hal_xmitframe_enqueue;
+#ifdef CONFIG_HOSTAPD_MLME
+	ops->hostap_mgnt_xmit_entry = rtl8821ce_hostap_mgnt_xmit_entry;
+#endif
+
+#ifdef CONFIG_XMIT_THREAD_MODE
+	/* TODO */
+	ops->xmit_thread_handler = rtl8821ce_xmit_buf_handler;
+#endif
+	ops->hal_set_l1ssbackdoor_handler = rtw_pci_aspm_config_l1off_general;
+}
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/rtl8821c/pci/rtl8821ce_recv.c linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/rtl8821c/pci/rtl8821ce_recv.c
--- linux-5.6.3/3rdparty/rtl8821ce/hal/rtl8821c/pci/rtl8821ce_recv.c	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/rtl8821c/pci/rtl8821ce_recv.c	2020-04-10 16:35:06.843661328 +0300
@@ -0,0 +1,463 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2016 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#define _RTL8821CE_RECV_C_
+
+#include <drv_types.h>		/* PADAPTER and etc. */
+#include <hal_data.h>		/* HAL_DATA_TYPE */
+#include "../../hal_halmac.h"	/* rtw_halmac_get_rx_desc_size() */
+#include "../rtl8821c.h"
+#include "rtl8821ce.h"
+
+/* Debug Buffer Descriptor Ring */
+
+/*#define BUF_DESC_DEBUG*/
+#ifdef BUF_DESC_DEBUG
+#define buf_desc_debug(...) RTW_INFO("BUF_DESC:" __VA_ARGS__)
+#else
+#define buf_desc_debug(...)  do {} while (0)
+#endif
+
+/*
+ * Wait until rx data is ready
+ *	return value: _SUCCESS if Rx packet is ready, _FAIL if not ready
+ */
+
+static u32 rtl8821ce_wait_rxrdy(_adapter *padapter,
+				u8 *rx_bd, u16 rx_q_idx)
+{
+	struct recv_priv *r_priv = &padapter->recvpriv;
+	u8 first_seg = 0, last_seg = 0;
+	u16 total_len = 0, read_cnt = 0;
+
+	static BOOLEAN start_rx = _FALSE;
+	u16 status = _SUCCESS;
+	HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
+
+	if (rx_bd == NULL)
+		return _FAIL;
+
+	total_len = (u2Byte)GET_RX_BD_TOTALRXPKTSIZE(rx_bd);
+	first_seg = (u1Byte)GET_RX_BD_FS(rx_bd);
+	last_seg = (u1Byte)GET_RX_BD_LS(rx_bd);
+
+	buf_desc_debug("RX:%s enter: rx_bd addr = %p, total_len=%d, first_seg=%d, last_seg=%d, read_cnt %d, index %d, address %p\n",
+		       __func__,
+		(u8 *)&r_priv->rx_ring[rx_q_idx].desc[r_priv->rx_ring[rx_q_idx].idx],
+		       total_len, first_seg, last_seg, read_cnt,
+		       r_priv->rx_ring[rx_q_idx].idx, rx_bd);
+
+#if defined(USING_RX_TAG)
+	/* Rx Tag not ported */
+	if (!start_rx) {
+		start_rx = _TRUE;
+		pHalData->RxTag = 1;
+	} else {
+		while (total_len != (pHalData->RxTag + 1)) {
+
+			read_cnt++;
+
+			total_len = (u2Byte)GET_RX_BD_TOTALRXPKTSIZE(rx_bd);
+			first_seg = (u1Byte)GET_RX_BD_FS(rx_bd);
+			last_seg = (u1Byte)GET_RX_BD_LS(rx_bd);
+
+			if (read_cnt > 10000) {
+				pHalData->RxTag = total_len;
+				break;
+			}
+
+			if (total_len == 0 && pHalData->RxTag == 0x1fff)
+				break;
+		}
+		pHalData->RxTag = total_len;
+	}
+#else
+	while (total_len == 0) {
+		read_cnt++;
+
+		total_len = (u2Byte) GET_RX_BD_TOTALRXPKTSIZE(rx_bd);
+		first_seg = (u1Byte) GET_RX_BD_FS(rx_bd);
+		last_seg = (u1Byte) GET_RX_BD_LS(rx_bd);
+
+		if (read_cnt > 20) {
+			status = _FAIL;
+			break;
+		}
+	}
+#endif
+
+	buf_desc_debug("RX:%s exit total_len=%d, rx_tag = %d, first_seg=%d, last_seg=%d, read_cnt %d\n",
+		       __func__, total_len, pHalData->RxTag,
+		       first_seg, last_seg, read_cnt);
+
+	return status;
+}
+
+/*
+ * Check the number of rxdec to be handled between
+ *   "index of RX queue descriptor maintained by host (write pointer)" and
+ *   "index of RX queue descriptor maintained by hardware (read pointer)"
+ */
+static u16 rtl8821ce_check_rxdesc_remain(_adapter *padapter, int rx_queue_idx)
+{
+	struct recv_priv *r_priv = &padapter->recvpriv;
+	u16 desc_idx_hw = 0, desc_idx_host = 0, num_rxdesc_to_handle = 0;
+	u32 tmp_4bytes = 0;
+	static BOOLEAN	start_rx = FALSE;
+
+
+	tmp_4bytes = rtw_read32(padapter, REG_RXQ_RXBD_IDX_8821C);
+	desc_idx_hw = (u16)((tmp_4bytes >> 16) & 0x7ff);
+	desc_idx_host = (u16)(tmp_4bytes & 0x7ff);
+
+	/*
+	 * make sure driver does not handle packet if hardware pointer
+	 * keeps in zero in initial state
+	 */
+	buf_desc_debug("RX:%s(%d) reg_value %x\n", __func__, __LINE__,
+		       tmp_4bytes);
+
+	if (desc_idx_hw > 0)
+		start_rx = TRUE;
+
+	if (!start_rx)
+		return 0;
+
+	if (desc_idx_hw < desc_idx_host)
+		/* hw idx is turn around */
+		num_rxdesc_to_handle = RX_BD_NUM_8821CE - desc_idx_host + desc_idx_hw;
+	else
+		num_rxdesc_to_handle = desc_idx_hw - desc_idx_host;
+
+	if (num_rxdesc_to_handle == 0)
+		return 0;
+
+	r_priv->rx_ring[rx_queue_idx].idx = desc_idx_host;
+
+	buf_desc_debug("RX:%s reg_val %x, hw_idx %x, host_idx %x, desc to handle = %d\n",
+		__func__, tmp_4bytes, desc_idx_hw, desc_idx_host, num_rxdesc_to_handle);
+
+	return num_rxdesc_to_handle;
+}
+
+static void rtl8821ce_rx_mpdu(_adapter *padapter)
+{
+	struct recv_priv *r_priv = &padapter->recvpriv;
+	struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(padapter);
+	_queue *pfree_recv_queue = &r_priv->free_recv_queue;
+	HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
+	union recv_frame *precvframe = NULL;
+	struct rx_pkt_attrib *pattrib = NULL;
+	int rx_q_idx = RX_MPDU_QUEUE;
+	u32 count = r_priv->rxringcount;
+	u16 remaing_rxdesc = 0;
+	u8 *rx_bd;
+	struct sk_buff *skb;
+	u32 desc_size;
+
+	rtw_halmac_get_rx_desc_size(adapter_to_dvobj(padapter), &desc_size);
+
+	/* RX NORMAL PKT */
+
+	remaing_rxdesc = rtl8821ce_check_rxdesc_remain(padapter, rx_q_idx);
+	while (remaing_rxdesc) {
+
+		/* rx descriptor */
+		rx_bd = (u8 *)&r_priv->rx_ring[rx_q_idx].buf_desc[r_priv->rx_ring[rx_q_idx].idx];
+
+		/* rx packet */
+		skb = r_priv->rx_ring[rx_q_idx].rx_buf[r_priv->rx_ring[rx_q_idx].idx];
+
+		buf_desc_debug("RX:%s(%d), rx_bd addr = %x, total_len = %d, ring idx = %d\n",
+			       __func__, __LINE__, (u32)rx_bd,
+			       GET_RX_BD_TOTALRXPKTSIZE(rx_bd),
+			       r_priv->rx_ring[rx_q_idx].idx);
+
+		buf_desc_debug("RX:%s(%d), skb(rx_buf)=%x, buf addr(virtual = %x, phisycal = %x)\n",
+			       __func__, __LINE__, (u32)skb,
+			       (u32)(skb_tail_pointer(skb)),
+			       GET_RX_BD_PHYSICAL_ADDR_LOW(rx_bd));
+
+		/* wait until packet is ready. this operation is similar to
+		 * check own bit and should be called before pci_unmap_single
+		 * which release memory mapping
+		 */
+
+		if (rtl8821ce_wait_rxrdy(padapter, rx_bd, rx_q_idx) !=
+		    _SUCCESS)
+			buf_desc_debug("RX:%s(%d) packet not ready\n",
+				       __func__, __LINE__);
+
+		{
+			precvframe = rtw_alloc_recvframe(pfree_recv_queue);
+
+			if (precvframe == NULL)
+				goto done;
+
+			_rtw_init_listhead(&precvframe->u.hdr.list);
+			precvframe->u.hdr.len = 0;
+
+			pci_unmap_single(pdvobjpriv->ppcidev,
+					 *((dma_addr_t *)skb->cb),
+					 r_priv->rxbuffersize,
+					 PCI_DMA_FROMDEVICE);
+
+			rtl8821c_query_rx_desc(precvframe, skb->data);
+			pattrib = &precvframe->u.hdr.attrib;
+
+#ifdef CONFIG_RX_PACKET_APPEND_FCS
+			{
+				struct mlme_priv *mlmepriv =
+						&padapter->mlmepriv;
+
+				if (check_fwstate(mlmepriv,
+						  WIFI_MONITOR_STATE) == _FALSE)
+					if (pattrib->pkt_rpt_type == NORMAL_RX)
+						pattrib->pkt_len -=
+							IEEE80211_FCS_LEN;
+			}
+#endif
+
+			buf_desc_debug("RX:%s(%d), pkt_len = %d, pattrib->drvinfo_sz = %d, pattrib->qos = %d, pattrib->shift_sz = %d\n",
+				       __func__, __LINE__, pattrib->pkt_len,
+				       pattrib->drvinfo_sz, pattrib->qos,
+				       pattrib->shift_sz);
+
+			if (rtw_os_alloc_recvframe(padapter, precvframe,
+				   (skb->data + desc_size +
+				    pattrib->drvinfo_sz + pattrib->shift_sz),
+						   skb) == _FAIL) {
+
+				rtw_free_recvframe(precvframe,
+						   &r_priv->free_recv_queue);
+
+				RTW_INFO("rtl8821ce_rx_mpdu:can't allocate memory for skb copy\n");
+				*((dma_addr_t *) skb->cb) =
+					pci_map_single(pdvobjpriv->ppcidev,
+						       skb_tail_pointer(skb),
+						       r_priv->rxbuffersize,
+						       PCI_DMA_FROMDEVICE);
+				goto done;
+			}
+
+			recvframe_put(precvframe, pattrib->pkt_len);
+
+			if (pattrib->pkt_rpt_type == NORMAL_RX) {
+				/* Normal rx packet */
+				pre_recv_entry(precvframe, pattrib->physt ? ((u8 *)(skb->data) + desc_size) : NULL);
+
+			} else {
+				if (pattrib->pkt_rpt_type == C2H_PACKET)
+					c2h_pre_handler_rtl8821c(padapter, skb->data, desc_size + pattrib->pkt_len);
+
+				rtw_free_recvframe(precvframe, pfree_recv_queue);
+			}
+			*((dma_addr_t *) skb->cb) =
+				pci_map_single(pdvobjpriv->ppcidev,
+					       skb_tail_pointer(skb),
+					       r_priv->rxbuffersize,
+					       PCI_DMA_FROMDEVICE);
+		}
+done:
+
+
+		SET_RX_BD_PHYSICAL_ADDR_LOW(rx_bd, *((dma_addr_t *)skb->cb));
+#ifdef CONFIG_64BIT_DMA
+		SET_RX_BD_PHYSICAL_ADDR_HIGH(rx_bd, (*((dma_addr_t *)skb->cb)>>32));
+#endif
+		SET_RX_BD_RXBUFFSIZE(rx_bd, r_priv->rxbuffersize);
+
+		r_priv->rx_ring[rx_q_idx].idx =
+			(r_priv->rx_ring[rx_q_idx].idx + 1) %
+			r_priv->rxringcount;
+
+		rtw_write16(padapter, REG_RXQ_RXBD_IDX,
+			    r_priv->rx_ring[rx_q_idx].idx);
+
+		buf_desc_debug("RX:%s(%d) reg_value %x\n", __func__, __LINE__,
+			       rtw_read32(padapter, REG_RXQ_RXBD_IDX));
+
+		remaing_rxdesc--;
+	}
+}
+
+static void rtl8821ce_recv_tasklet(void *priv)
+{
+	_irqL	irqL;
+	_adapter	*padapter = (_adapter *)priv;
+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(padapter);
+	struct dvobj_priv	*pdvobjpriv = adapter_to_dvobj(padapter);
+
+	rtl8821ce_rx_mpdu(padapter);
+	_enter_critical(&pdvobjpriv->irq_th_lock, &irqL);
+	pHalData->IntrMask[0] |= (BIT_RXOK_MSK_8821C | BIT_RDU_MSK_8821C);
+	pHalData->IntrMask[1] |= BIT_FOVW_MSK_8821C;
+	rtw_write32(padapter, REG_HIMR0_8821C, pHalData->IntrMask[0]);
+	rtw_write32(padapter, REG_HIMR1_8821C, pHalData->IntrMask[1]);
+	_exit_critical(&pdvobjpriv->irq_th_lock, &irqL);
+}
+
+static void rtl8821ce_xmit_beacon(PADAPTER Adapter)
+{
+#if defined(CONFIG_AP_MODE) && defined(CONFIG_NATIVEAP_MLME)
+	struct mlme_priv *pmlmepriv = &Adapter->mlmepriv;
+
+	if (MLME_IS_AP(Adapter) || MLME_IS_MESH(Adapter)) {
+		/* send_beacon(Adapter); */
+		if (pmlmepriv->update_bcn == _TRUE)
+			tx_beacon_hdl(Adapter, NULL);
+	}
+#endif
+}
+
+static void rtl8821ce_prepare_bcn_tasklet(void *priv)
+{
+	_adapter *padapter = (_adapter *)priv;
+
+	rtl8821ce_xmit_beacon(padapter);
+}
+
+s32 rtl8821ce_init_recv_priv(_adapter *padapter)
+{
+	struct recv_priv	*precvpriv = &padapter->recvpriv;
+	s32	ret = _SUCCESS;
+
+
+#ifdef PLATFORM_LINUX
+	tasklet_init(&precvpriv->recv_tasklet,
+		     (void(*)(unsigned long))rtl8821ce_recv_tasklet,
+		     (unsigned long)padapter);
+
+	tasklet_init(&precvpriv->irq_prepare_beacon_tasklet,
+		     (void(*)(unsigned long))rtl8821ce_prepare_bcn_tasklet,
+		     (unsigned long)padapter);
+#endif
+
+
+	return ret;
+}
+
+void rtl8821ce_free_recv_priv(_adapter *padapter)
+{
+
+}
+
+int rtl8821ce_init_rxbd_ring(_adapter *padapter)
+{
+	struct recv_priv	*r_priv = &padapter->recvpriv;
+	struct dvobj_priv	*pdvobjpriv = adapter_to_dvobj(padapter);
+	struct pci_dev	*pdev = pdvobjpriv->ppcidev;
+	struct net_device	*dev = padapter->pnetdev;
+	dma_addr_t *mapping = NULL;
+	struct sk_buff *skb = NULL;
+	u8	*rx_desc = NULL;
+	int	i, rx_queue_idx;
+
+
+	/* rx_queue_idx 0:RX_MPDU_QUEUE */
+	/* rx_queue_idx 1:RX_CMD_QUEUE */
+	for (rx_queue_idx = 0; rx_queue_idx < 1; rx_queue_idx++) {
+		r_priv->rx_ring[rx_queue_idx].buf_desc =
+			pci_alloc_consistent(pdev,
+			     sizeof(*r_priv->rx_ring[rx_queue_idx].buf_desc) *
+					     r_priv->rxringcount,
+				     &r_priv->rx_ring[rx_queue_idx].dma);
+
+		if (!r_priv->rx_ring[rx_queue_idx].buf_desc ||
+		    (unsigned long)r_priv->rx_ring[rx_queue_idx].buf_desc &
+		    0xFF) {
+			RTW_INFO("Cannot allocate RX ring\n");
+			return _FAIL;
+		}
+
+		_rtw_memset(r_priv->rx_ring[rx_queue_idx].buf_desc, 0,
+			    sizeof(*r_priv->rx_ring[rx_queue_idx].buf_desc) *
+			    r_priv->rxringcount);
+		r_priv->rx_ring[rx_queue_idx].idx = 0;
+
+		for (i = 0; i < r_priv->rxringcount; i++) {
+			skb = dev_alloc_skb(r_priv->rxbuffersize);
+			if (!skb) {
+				RTW_INFO("Cannot allocate skb for RX ring\n");
+				return _FAIL;
+			}
+
+			rx_desc =
+				(u8 *)(&r_priv->rx_ring[rx_queue_idx].buf_desc[i]);
+			r_priv->rx_ring[rx_queue_idx].rx_buf[i] = skb;
+			mapping = (dma_addr_t *)skb->cb;
+
+			/* just set skb->cb to mapping addr
+			 * for pci_unmap_single use
+			 */
+			*mapping = pci_map_single(pdev, skb_tail_pointer(skb),
+						  r_priv->rxbuffersize,
+						  PCI_DMA_FROMDEVICE);
+
+			/* Reset FS, LS, Total len */
+			SET_RX_BD_LS(rx_desc, 0);
+			SET_RX_BD_FS(rx_desc, 0);
+			SET_RX_BD_TOTALRXPKTSIZE(rx_desc, 0);
+			SET_RX_BD_RXBUFFSIZE(rx_desc, r_priv->rxbuffersize);
+			SET_RX_BD_PHYSICAL_ADDR_LOW(rx_desc, *mapping);
+#ifdef CONFIG_64BIT_DMA
+			SET_RX_BD_PHYSICAL_ADDR_HIGH(rx_desc, *mapping >> 32);
+#endif
+
+			buf_desc_debug("RX:rx buffer desc addr[%d] = %x, skb(rx_buf) = %x, buffer addr (virtual = %x, physical = %x)\n",
+				i, (u32)&r_priv->rx_ring[rx_queue_idx].buf_desc[i],
+				(u32)r_priv->rx_ring[rx_queue_idx].rx_buf[i],
+				(u32)(skb_tail_pointer(skb)), (u32)(*mapping));
+		}
+	}
+
+
+	return _SUCCESS;
+}
+
+void rtl8821ce_free_rxbd_ring(_adapter *padapter)
+{
+	struct recv_priv *r_priv = &padapter->recvpriv;
+	struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(padapter);
+	struct pci_dev *pdev = pdvobjpriv->ppcidev;
+	int i, rx_queue_idx;
+
+
+	/* rx_queue_idx 0:RX_MPDU_QUEUE */
+	/* rx_queue_idx 1:RX_CMD_QUEUE */
+	for (rx_queue_idx = 0; rx_queue_idx < 1; rx_queue_idx++) {
+		for (i = 0; i < r_priv->rxringcount; i++) {
+			struct sk_buff *skb;
+
+			skb = r_priv->rx_ring[rx_queue_idx].rx_buf[i];
+
+			if (!skb)
+				continue;
+
+			pci_unmap_single(pdev,
+					 *((dma_addr_t *) skb->cb),
+					 r_priv->rxbuffersize,
+					 PCI_DMA_FROMDEVICE);
+			kfree_skb(skb);
+		}
+
+		pci_free_consistent(pdev,
+			    sizeof(*r_priv->rx_ring[rx_queue_idx].buf_desc) *
+				    r_priv->rxringcount,
+				    r_priv->rx_ring[rx_queue_idx].buf_desc,
+				    r_priv->rx_ring[rx_queue_idx].dma);
+		r_priv->rx_ring[rx_queue_idx].buf_desc = NULL;
+	}
+
+}
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/rtl8821c/pci/rtl8821ce_xmit.c linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/rtl8821c/pci/rtl8821ce_xmit.c
--- linux-5.6.3/3rdparty/rtl8821ce/hal/rtl8821c/pci/rtl8821ce_xmit.c	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/rtl8821c/pci/rtl8821ce_xmit.c	2020-04-10 16:35:06.843661328 +0300
@@ -0,0 +1,1671 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2016 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#define _RTL8821CE_XMIT_C_
+
+#include <drv_types.h>		/* PADAPTER, rtw_xmit.h and etc. */
+#include <hal_data.h>		/* HAL_DATA_TYPE */
+#include "../halmac/halmac_api.h"
+#include "../rtl8821c.h"
+#include "rtl8821ce.h"
+
+/* Debug Buffer Descriptor Ring */
+/*#define BUF_DESC_DEBUG*/
+#ifdef BUF_DESC_DEBUG
+#define buf_desc_debug(...) RTW_INFO("BUF_DESC:" __VA_ARGS__)
+
+#else
+#define buf_desc_debug(...)  do {} while (0)
+#endif
+
+static void rtl8821ce_xmit_tasklet(void *priv)
+{
+	_irqL irqL;
+	_adapter *padapter = (_adapter *)priv;
+	HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
+	struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(padapter);
+
+	/* try to deal with the pending packets */
+	rtl8821ce_xmitframe_resume(padapter);
+
+}
+
+s32 rtl8821ce_init_xmit_priv(_adapter *padapter)
+{
+	s32 ret = _SUCCESS;
+	struct xmit_priv *pxmitpriv = &padapter->xmitpriv;
+	struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(padapter);
+
+	_rtw_spinlock_init(&pdvobjpriv->irq_th_lock);
+
+#ifdef PLATFORM_LINUX
+	tasklet_init(&pxmitpriv->xmit_tasklet,
+		     (void(*)(unsigned long))rtl8821ce_xmit_tasklet,
+		     (unsigned long)padapter);
+#endif
+	rtl8821c_init_xmit_priv(padapter);
+	return ret;
+}
+
+void rtl8821ce_free_xmit_priv(_adapter *padapter)
+{
+	struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(padapter);
+
+	_rtw_spinlock_free(&pdvobjpriv->irq_th_lock);
+}
+
+static s32 rtl8821ce_enqueue_xmitbuf(struct rtw_tx_ring	*ring,
+				     struct xmit_buf *pxmitbuf)
+{
+	_irqL irqL;
+	_queue *ppending_queue = &ring->queue;
+
+
+	if (pxmitbuf == NULL)
+		return _FAIL;
+
+	rtw_list_delete(&pxmitbuf->list);
+	rtw_list_insert_tail(&(pxmitbuf->list), get_list_head(ppending_queue));
+	ring->qlen++;
+
+
+	return _SUCCESS;
+}
+
+struct xmit_buf *rtl8821ce_dequeue_xmitbuf(struct rtw_tx_ring	*ring)
+{
+	_irqL irqL;
+	_list *plist, *phead;
+	struct xmit_buf *pxmitbuf =  NULL;
+	_queue *ppending_queue = &ring->queue;
+
+
+	if (_rtw_queue_empty(ppending_queue) == _TRUE)
+		pxmitbuf = NULL;
+	else {
+
+		phead = get_list_head(ppending_queue);
+		plist = get_next(phead);
+		pxmitbuf = LIST_CONTAINOR(plist, struct xmit_buf, list);
+		rtw_list_delete(&(pxmitbuf->list));
+		ring->qlen--;
+	}
+
+
+	return pxmitbuf;
+}
+
+static u8 *get_txbd(_adapter *padapter, u8 q_idx)
+{
+	struct xmit_priv *pxmitpriv = &padapter->xmitpriv;
+	struct rtw_tx_ring *ring;
+	u8 *ptxbd = NULL;
+	int idx = 0;
+
+	ring = &pxmitpriv->tx_ring[q_idx];
+
+	/* DO NOT use last entry. */
+	/* (len -1) to avoid wrap around overlap problem in cycler queue. */
+	if (ring->qlen == (ring->entries - 1)) {
+		RTW_INFO("No more TX desc@%d, ring->idx = %d,idx = %d\n",
+			 q_idx, ring->idx, idx);
+		return NULL;
+	}
+
+	if (q_idx == BCN_QUEUE_INX)
+		idx = 0;
+	else
+		idx = (ring->idx + ring->qlen) % ring->entries;
+
+	ptxbd = (u8 *)&ring->buf_desc[idx];
+
+	return ptxbd;
+}
+
+/*
+ * Get txbd reg addr according to q_sel
+ */
+u16 get_txbd_rw_reg(u16 q_idx)
+{
+	u16 txbd_reg_addr = REG_BEQ_TXBD_IDX;
+
+	switch (q_idx) {
+
+	case BK_QUEUE_INX:
+		txbd_reg_addr = REG_BKQ_TXBD_IDX;
+		break;
+
+	case BE_QUEUE_INX:
+		txbd_reg_addr = REG_BEQ_TXBD_IDX;
+		break;
+
+	case VI_QUEUE_INX:
+		txbd_reg_addr = REG_VIQ_TXBD_IDX;
+		break;
+
+	case VO_QUEUE_INX:
+		txbd_reg_addr = REG_VOQ_TXBD_IDX;
+		break;
+
+	case BCN_QUEUE_INX:
+		txbd_reg_addr = REG_BEQ_TXBD_IDX;	/* need check */
+		break;
+
+	case TXCMD_QUEUE_INX:
+		txbd_reg_addr = REG_H2CQ_TXBD_IDX;
+		break;
+
+	case MGT_QUEUE_INX:
+		txbd_reg_addr = REG_MGQ_TXBD_IDX;
+		break;
+
+	case HIGH_QUEUE_INX:
+		txbd_reg_addr = REG_HI0Q_TXBD_IDX;   /* need check */
+		break;
+
+	default:
+		break;
+	}
+
+	return txbd_reg_addr;
+}
+
+struct xmit_frame *__rtw_alloc_cmdxmitframe_8821ce(struct xmit_priv *pxmitpriv,
+		enum cmdbuf_type buf_type)
+{
+	_adapter *padapter;
+	u16	queue_idx = BCN_QUEUE_INX;
+	u8 *ptxdesc = NULL;
+
+	padapter = GET_PRIMARY_ADAPTER(pxmitpriv->adapter);
+
+	ptxdesc = get_txbd(padapter, BCN_QUEUE_INX);
+
+	/* set OWN bit in Beacon tx descriptor */
+#if 1 /* vincent TODO */
+	if (ptxdesc != NULL)
+		SET_TX_BD_OWN(ptxdesc, 0);
+	else
+		return NULL;
+#endif
+
+	return __rtw_alloc_cmdxmitframe(pxmitpriv, CMDBUF_BEACON);
+}
+
+/*
+ * Update Read/Write pointer
+ *	Read pointer is h/w descriptor index
+ *	Write pointer is host desciptor index:
+ *	For tx side, if own bit is set in packet index n,
+ *	host pointer (write pointer) point to index n + 1.)
+ */
+void fill_txbd_own(_adapter *padapter, u8 *txbd, u16 queue_idx,
+	struct rtw_tx_ring *ptxring)
+{
+	struct xmit_priv *pxmitpriv = &padapter->xmitpriv;
+	struct rtw_tx_ring *ring;
+	u16 host_wp = 0;
+
+	if (queue_idx == BCN_QUEUE_INX) {
+
+		SET_TX_BD_OWN(txbd, 1);
+
+		/* kick start */
+		rtw_write8(padapter, REG_RX_RXBD_NUM + 1,
+		rtw_read8(padapter, REG_RX_RXBD_NUM + 1) | BIT(4));
+
+		return;
+	}
+
+	/*
+	 * update h/w index
+	 * for tx side, if own bit is set in packet index n,
+	 * host pointer (write pointer) point to index n + 1.
+	 */
+
+	/* for current tx packet, enqueue has been ring->qlen++ before.
+	 * so, host_wp = ring->idx + ring->qlen.
+	 */
+	host_wp = (ptxring->idx + ptxring->qlen) % ptxring->entries;
+	rtw_write16(padapter, get_txbd_rw_reg(queue_idx), host_wp);
+}
+
+static u16 ffaddr2dma(u32 addr)
+{
+	u16	dma_ctrl;
+
+	switch (addr) {
+	case VO_QUEUE_INX:
+		dma_ctrl = BIT3;
+		break;
+	case VI_QUEUE_INX:
+		dma_ctrl = BIT2;
+		break;
+	case BE_QUEUE_INX:
+		dma_ctrl = BIT1;
+		break;
+	case BK_QUEUE_INX:
+		dma_ctrl = BIT0;
+		break;
+	case BCN_QUEUE_INX:
+		dma_ctrl = BIT4;
+		break;
+	case MGT_QUEUE_INX:
+		dma_ctrl = BIT6;
+		break;
+	case HIGH_QUEUE_INX:
+		dma_ctrl = BIT7;
+		break;
+	default:
+		dma_ctrl = 0;
+		break;
+	}
+
+	return dma_ctrl;
+}
+
+/*
+ * Fill tx buffer desciptor. Map each buffer address in tx buffer descriptor
+ * segment. Designed for tx buffer descriptor architecture
+ * Input *pmem: pointer to the Tx Buffer Descriptor
+ */
+static void rtl8821ce_update_txbd(struct xmit_frame *pxmitframe,
+				  u8 *txbd, s32 sz)
+{
+	_adapter *padapter = pxmitframe->padapter;
+	struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(padapter);
+	dma_addr_t mapping;
+	u32 i = 0;
+	u16 seg_num =
+		((TX_BUFFER_SEG_NUM == 0) ? 2 : ((TX_BUFFER_SEG_NUM == 1) ? 4 : 8));
+	u16 tx_page_size_reg = 1;
+	u16 page_size_length = 0;
+
+	/* map TX DESC buf_addr (including TX DESC + tx data) */
+	mapping = pci_map_single(pdvobjpriv->ppcidev, pxmitframe->buf_addr,
+				 sz + TX_WIFI_INFO_SIZE, PCI_DMA_TODEVICE);
+
+	/* Calculate page size.
+	 * Total buffer length including TX_WIFI_INFO and PacketLen
+	 */
+	if (tx_page_size_reg > 0) {
+		page_size_length = (sz + TX_WIFI_INFO_SIZE) /
+				   (tx_page_size_reg * 128);
+		if (((sz + TX_WIFI_INFO_SIZE) % (tx_page_size_reg * 128)) > 0)
+			page_size_length++;
+	}
+
+	/*
+	 * Reset all tx buffer desciprtor content
+	 * -- Reset first element
+	 */
+	SET_TX_BD_TX_BUFF_SIZE0(txbd, 0);
+	SET_TX_BD_PSB(txbd, 0);
+	SET_TX_BD_OWN(txbd, 0);
+
+	/* -- Reset second and other element */
+	for (i = 1 ; i < seg_num ; i++) {
+		SET_TXBUFFER_DESC_LEN_WITH_OFFSET(txbd, i, 0);
+		SET_TXBUFFER_DESC_AMSDU_WITH_OFFSET(txbd, i, 0);
+		SET_TXBUFFER_DESC_ADD_LOW_WITH_OFFSET(txbd, i, 0);
+	}
+
+	/*
+	 * Fill buffer length of the first buffer,
+	 * For 8821ce, it is required that TX_WIFI_INFO is put in first segment,
+	 * and the size of the first segment cannot be larger than
+	 * TX_WIFI_INFO_SIZE.
+	 */
+	SET_TX_BD_TX_BUFF_SIZE0(txbd, TX_WIFI_INFO_SIZE);
+	SET_TX_BD_PSB(txbd, page_size_length);
+	/* starting addr of TXDESC */
+	SET_TX_BD_PHYSICAL_ADDR0_LOW(txbd, mapping);
+
+#ifdef CONFIG_64BIT_DMA 
+	SET_TX_BD_PHYSICAL_ADDR0_HIGH(txbd, mapping >> 32);
+#endif
+
+	/*
+	 * It is assumed that in linux implementation, packet is coalesced
+	 * in only one buffer. Extension mode is not supported here
+	 */
+	SET_TXBUFFER_DESC_LEN_WITH_OFFSET(txbd, 1, sz);
+	/* don't using extendsion mode. */
+	SET_TXBUFFER_DESC_AMSDU_WITH_OFFSET(txbd, 1, 0);
+	SET_TXBUFFER_DESC_ADD_LOW_WITH_OFFSET(txbd, 1,
+				      mapping + TX_WIFI_INFO_SIZE); /* pkt */
+#ifdef CONFIG_64BIT_DMA 
+	SET_TXBUFFER_DESC_ADD_HIGH_WITH_OFFSET(txbd, 1,
+				      (mapping + TX_WIFI_INFO_SIZE) >> 32); /* pkt */
+#endif
+
+	/*buf_desc_debug("TX:%s, txbd = 0x%p\n", __FUNCTION__, txbd);*/
+	buf_desc_debug("%s, txbd = 0x%08x\n", __func__, txbd);
+	buf_desc_debug("TXBD:, 00h(0x%08x)\n", *((u32 *)(txbd)));
+	buf_desc_debug("TXBD:, 04h(0x%08x)\n", *((u32 *)(txbd + 4)));
+	buf_desc_debug("TXBD:, 08h(0x%08x)\n", *((u32 *)(txbd + 8)));
+	buf_desc_debug("TXBD:, 12h(0x%08x)\n", *((u32 *)(txbd + 12)));
+
+}
+
+static s32 update_txdesc(struct xmit_frame *pxmitframe, s32 sz)
+{
+	uint qsel;
+	u8 data_rate, pwr_status;
+	_adapter *padapter = pxmitframe->padapter;
+	struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
+	struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(padapter);
+	struct pkt_attrib *pattrib = &pxmitframe->attrib;
+	HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
+	struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
+	struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
+	u8 *ptxdesc;
+	sint bmcst = IS_MCAST(pattrib->ra);
+	u16 SWDefineContent = 0x0;
+	u8 DriverFixedRate = 0x0;
+	u8 hw_port = rtw_hal_get_port(padapter);
+
+	ptxdesc = pxmitframe->buf_addr;
+	_rtw_memset(ptxdesc, 0, TXDESC_SIZE);
+
+	/* offset 0 */
+	/*SET_TX_DESC_FIRST_SEG_8812(ptxdesc, 1);*/
+	SET_TX_DESC_LS_8821C(ptxdesc, 1);
+	/*SET_TX_DESC_OWN_8812(ptxdesc, 1);*/
+
+	SET_TX_DESC_TXPKTSIZE_8821C(ptxdesc, sz);
+	/* TX_DESC is not included in the data,
+	 * driver needs to fill in the TX_DESC with qsel=h2c
+	 * Offset in TX_DESC should be set to 0.
+	 */
+#ifdef CONFIG_TX_EARLY_MODE
+	SET_TX_DESC_PKT_OFFSET_8812(ptxdesc, 1);
+	if (pattrib->qsel == HALMAC_TXDESC_QSEL_H2C_CMD)
+		SET_TX_DESC_OFFSET_8821C(ptxdesc, 0);
+	else
+		SET_TX_DESC_OFFSET_8821C(ptxdesc,
+			TXDESC_SIZE + EARLY_MODE_INFO_SIZE);
+#else
+	if (pattrib->qsel == HALMAC_TXDESC_QSEL_H2C_CMD)
+		SET_TX_DESC_OFFSET_8821C(ptxdesc, 0);
+	else
+		SET_TX_DESC_OFFSET_8821C(ptxdesc, TXDESC_SIZE);
+#endif
+
+	if (bmcst)
+		SET_TX_DESC_BMC_8821C(ptxdesc, 1);
+
+	SET_TX_DESC_MACID_8821C(ptxdesc, pattrib->mac_id);
+	SET_TX_DESC_RATE_ID_8821C(ptxdesc, pattrib->raid);
+
+	SET_TX_DESC_QSEL_8821C(ptxdesc,  pattrib->qsel);
+
+	if (!pattrib->qos_en) {
+		/* Hw set sequence number */
+		SET_TX_DESC_DISQSELSEQ_8821C(ptxdesc, 1);
+		SET_TX_DESC_EN_HWSEQ_8821C(ptxdesc, 1);
+		SET_TX_DESC_HW_SSN_SEL_8821C(ptxdesc, pattrib->hw_ssn_sel);
+		SET_TX_DESC_EN_HWEXSEQ_8821C(ptxdesc, 0);
+	} else
+		SET_TX_DESC_SW_SEQ_8821C(ptxdesc, pattrib->seqnum);
+
+	if ((pxmitframe->frame_tag & 0x0f) == DATA_FRAMETAG) {
+		rtl8821c_fill_txdesc_sectype(pattrib, ptxdesc);
+		rtl8821c_fill_txdesc_vcs(padapter, pattrib, ptxdesc);
+
+#ifdef CONFIG_CONCURRENT_MODE
+		if (bmcst)
+			fill_txdesc_force_bmc_camid(pattrib, ptxdesc);
+#endif
+#ifdef CONFIG_SUPPORT_DYNAMIC_TXPWR
+		rtw_phydm_set_dyntxpwr(padapter, ptxdesc, pattrib->mac_id);
+#endif
+
+		if ((pattrib->ether_type != 0x888e) &&
+		    (pattrib->ether_type != 0x0806) &&
+		    (pattrib->ether_type != 0x88b4) &&
+		    (pattrib->dhcp_pkt != 1)
+#ifdef CONFIG_AUTO_AP_MODE
+		    && (pattrib->pctrl != _TRUE)
+#endif
+		   ) {
+			/* Non EAP & ARP & DHCP type data packet */
+
+			if (pattrib->ampdu_en == _TRUE) {
+				/* 8821c does NOT support AGG broadcast pkt */
+				if (!bmcst)
+					SET_TX_DESC_AGG_EN_8821C(ptxdesc, 1);
+
+				SET_TX_DESC_MAX_AGG_NUM_8821C(ptxdesc, 0x1f);
+				/* Set A-MPDU aggregation. */
+				SET_TX_DESC_AMPDU_DENSITY_8821C(ptxdesc,
+							pattrib->ampdu_spacing);
+			} else
+				SET_TX_DESC_BK_8821C(ptxdesc, 1);
+
+			rtl8821c_fill_txdesc_phy(padapter, pattrib, ptxdesc);
+
+			/* DATA  Rate FB LMT */
+			/* compatibility for MCC consideration,
+			 * use pmlmeext->cur_channel
+			 */
+			if (pmlmeext->cur_channel > 14)
+				/* for 5G. OFMD 6M */
+				SET_TX_DESC_DATA_RTY_LOWEST_RATE_8821C(
+					ptxdesc, 4);
+			else
+				/* for 2.4G. CCK 1M */
+				SET_TX_DESC_DATA_RTY_LOWEST_RATE_8821C(
+					ptxdesc, 0);
+
+			if (pHalData->fw_ractrl == _FALSE) {
+				SET_TX_DESC_USE_RATE_8821C(ptxdesc, 1);
+				DriverFixedRate = 0x01;
+
+				if (pHalData->INIDATA_RATE[pattrib->mac_id] &
+				    BIT(7))
+					SET_TX_DESC_DATA_SHORT_8821C(
+						ptxdesc, 1);
+
+				SET_TX_DESC_DATARATE_8821C(ptxdesc,
+					pHalData->INIDATA_RATE[pattrib->mac_id]
+							   & 0x7F);
+			}
+			if (bmcst) {
+				DriverFixedRate = 0x01;
+				fill_txdesc_bmc_tx_rate(pattrib, ptxdesc);
+			}
+
+			if (padapter->fix_rate != 0xFF) {
+				/* modify data rate by iwpriv */
+				SET_TX_DESC_USE_RATE_8821C(ptxdesc, 1);
+
+				DriverFixedRate = 0x01;
+				if (padapter->fix_rate & BIT(7))
+					SET_TX_DESC_DATA_SHORT_8821C(
+						ptxdesc, 1);
+
+				SET_TX_DESC_DATARATE_8821C(ptxdesc,
+						   (padapter->fix_rate & 0x7F));
+				if (!padapter->data_fb)
+					SET_TX_DESC_DISDATAFB_8821C(ptxdesc, 1);
+			}
+
+			if (pattrib->ldpc)
+				SET_TX_DESC_DATA_LDPC_8821C(ptxdesc, 1);
+			if (pattrib->stbc)
+				SET_TX_DESC_DATA_STBC_8821C(ptxdesc, 1);
+
+#ifdef CONFIG_WMMPS_STA
+			if (pattrib->trigger_frame)
+				SET_TX_DESC_TRI_FRAME_8821C (ptxdesc, 1);
+#endif /* CONFIG_WMMPS_STA */
+			
+		} else {
+			/*
+			 * EAP data packet and ARP packet and DHCP.
+			 * Use the 1M data rate to send the EAP/ARP packet.
+			 * This will maybe make the handshake smooth.
+			 */
+
+			SET_TX_DESC_USE_RATE_8821C(ptxdesc, 1);
+			DriverFixedRate = 0x01;
+			SET_TX_DESC_BK_8821C(ptxdesc, 1);
+
+			/* HW will ignore this setting if the transmission rate
+			 * is legacy OFDM.
+			 */
+			if (pmlmeinfo->preamble_mode == PREAMBLE_SHORT)
+				SET_TX_DESC_DATA_SHORT_8821C(ptxdesc, 1);
+
+			SET_TX_DESC_DATARATE_8821C(ptxdesc,
+					   MRateToHwRate(pmlmeext->tx_rate));
+		}
+
+#ifdef CONFIG_TDLS
+#ifdef CONFIG_XMIT_ACK
+		/* CCX-TXRPT ack for xmit mgmt frames. */
+		if (pxmitframe->ack_report) {
+			SET_TX_DESC_SPE_RPT_8821C(ptxdesc, 1);
+#ifdef DBG_CCX
+			RTW_INFO("%s set tx report\n", __func__);
+#endif
+		}
+#endif /* CONFIG_XMIT_ACK */
+#endif
+	} else if ((pxmitframe->frame_tag & 0x0f) == MGNT_FRAMETAG) {
+		SET_TX_DESC_MBSSID_8821C(ptxdesc, pattrib->mbssid & 0xF);
+		SET_TX_DESC_USE_RATE_8821C(ptxdesc, 1);
+		DriverFixedRate = 0x01;
+
+		SET_TX_DESC_DATARATE_8821C(ptxdesc, MRateToHwRate(pattrib->rate));
+
+		SET_TX_DESC_RTY_LMT_EN_8821C(ptxdesc, 1);
+		if (pattrib->retry_ctrl == _TRUE)
+			SET_TX_DESC_RTS_DATA_RTY_LMT_8821C(ptxdesc, 6);
+		else
+			SET_TX_DESC_RTS_DATA_RTY_LMT_8821C(ptxdesc, 12);
+
+		/*rtl8821c_fill_txdesc_mgnt_bf(pxmitframe, ptxdesc); Todo for 8821C*/
+
+#ifdef CONFIG_XMIT_ACK
+		/* CCX-TXRPT ack for xmit mgmt frames. */
+		if (pxmitframe->ack_report) {
+			SET_TX_DESC_SPE_RPT_8821C(ptxdesc, 1);
+#ifdef DBG_CCX
+			RTW_INFO("%s set tx report\n", __func__);
+#endif
+		}
+#endif /* CONFIG_XMIT_ACK */
+	} else if ((pxmitframe->frame_tag & 0x0f) == TXAGG_FRAMETAG)
+		RTW_INFO("pxmitframe->frame_tag == TXAGG_FRAMETAG\n");
+#ifdef CONFIG_MP_INCLUDED
+	else if (((pxmitframe->frame_tag & 0x0f) == MP_FRAMETAG) &&
+		 (padapter->registrypriv.mp_mode == 1))
+		fill_txdesc_for_mp(padapter, ptxdesc);
+#endif
+	else {
+		RTW_INFO("pxmitframe->frame_tag = %d\n",
+			 pxmitframe->frame_tag);
+
+		SET_TX_DESC_USE_RATE_8821C(ptxdesc, 1);
+		DriverFixedRate = 0x01;
+		SET_TX_DESC_DATARATE_8821C(ptxdesc,
+					   MRateToHwRate(pmlmeext->tx_rate));
+	}
+
+#ifdef CONFIG_ANTENNA_DIVERSITY
+	ODM_SetTxAntByTxInfo(&pHalData->odmpriv, ptxdesc,
+			     pxmitframe->attrib.mac_id);
+#endif
+
+	/*rtl8821c_fill_txdesc_bf(pxmitframe, ptxdesc);Todo for 8821C*/
+
+	/*SET_TX_DESC_TX_BUFFER_SIZE_8812(ptxdesc, sz);*/
+
+	if (DriverFixedRate)
+		SWDefineContent |= 0x01;
+
+	SET_TX_DESC_SW_DEFINE_8821C(ptxdesc, SWDefineContent);
+
+	SET_TX_DESC_PORT_ID_8821C(ptxdesc, hw_port);
+	SET_TX_DESC_MULTIPLE_PORT_8821C(ptxdesc, hw_port);
+
+	rtl8821c_cal_txdesc_chksum(padapter, ptxdesc);
+	rtl8821c_dbg_dump_tx_desc(padapter, pxmitframe->frame_tag, ptxdesc);
+	return 0;
+}
+
+s32 rtl8821ce_dump_xframe(_adapter *padapter, struct xmit_frame *pxmitframe)
+{
+	s32 ret = _SUCCESS;
+	s32 inner_ret = _SUCCESS;
+	_irqL irqL;
+	int t, sz, w_sz, pull = 0;
+	u32 ff_hwaddr;
+	struct xmit_buf *pxmitbuf = pxmitframe->pxmitbuf;
+	struct pkt_attrib *pattrib = &pxmitframe->attrib;
+	struct xmit_priv *pxmitpriv = &padapter->xmitpriv;
+	struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(padapter);
+	struct security_priv *psecuritypriv = &padapter->securitypriv;
+	u8 *txbd;
+	struct rtw_tx_ring *ptx_ring;
+
+
+#ifdef CONFIG_80211N_HT
+	if ((pxmitframe->frame_tag == DATA_FRAMETAG) &&
+	    (pxmitframe->attrib.ether_type != 0x0806) &&
+	    (pxmitframe->attrib.ether_type != 0x888e) &&
+	    (pxmitframe->attrib.dhcp_pkt != 1))
+		rtw_issue_addbareq_cmd(padapter, pxmitframe);
+#endif /* CONFIG_80211N_HT */
+	for (t = 0; t < pattrib->nr_frags; t++) {
+
+		if (inner_ret != _SUCCESS && ret == _SUCCESS)
+			ret = _FAIL;
+
+		if (t != (pattrib->nr_frags - 1)) {
+
+			sz = pxmitpriv->frag_len - 4;
+
+			if (!psecuritypriv->sw_encrypt)
+				sz -= pattrib->icv_len;
+		} else {
+			/* no frag */
+			sz = pattrib->last_txcmdsz;
+		}
+
+		ff_hwaddr = rtw_get_ff_hwaddr(pxmitframe);
+
+		_enter_critical(&pdvobjpriv->irq_th_lock, &irqL);
+		txbd = get_txbd(GET_PRIMARY_ADAPTER(padapter), ff_hwaddr);
+
+		ptx_ring = &(GET_PRIMARY_ADAPTER(padapter)->xmitpriv.tx_ring[ff_hwaddr]);
+
+#ifndef CONFIG_BCN_ICF
+		if (ff_hwaddr == BCN_QUEUE_INX)
+			padapter->xmitpriv.beaconDMAing = _TRUE;
+#endif
+
+		if (txbd == NULL) {
+			_exit_critical(&pdvobjpriv->irq_th_lock, &irqL);
+			rtw_sctx_done_err(&pxmitbuf->sctx,
+					  RTW_SCTX_DONE_TX_DESC_NA);
+			rtw_free_xmitbuf(pxmitpriv, pxmitbuf);
+			RTW_INFO("##### Tx desc unavailable !#####\n");
+			break;
+		}
+
+		if (pattrib->qsel != HALMAC_TXDESC_QSEL_H2C_CMD)
+			update_txdesc(pxmitframe, sz);
+
+		/* rtl8821ce_update_txbd() must be called after update_txdesc()
+		 * It rely on rtl8821ce_update_txbd() to map it into non cache memory
+		 */
+
+		rtl8821ce_update_txbd(pxmitframe, txbd, sz);
+
+		if (pxmitbuf->buf_tag != XMITBUF_CMD)
+			rtl8821ce_enqueue_xmitbuf(ptx_ring, pxmitbuf);
+
+		pxmitbuf->len = sz + TX_WIFI_INFO_SIZE;
+		w_sz = sz;
+
+		/* Please comment here */
+		wmb();
+		fill_txbd_own(padapter, txbd, ff_hwaddr, ptx_ring);
+
+#ifdef DBG_TXBD_DESC_DUMP
+		if (pxmitpriv->dump_txbd_desc)
+			rtw_tx_desc_backup(padapter, pxmitframe, TX_WIFI_INFO_SIZE, ff_hwaddr);
+#endif
+		_exit_critical(&pdvobjpriv->irq_th_lock, &irqL);
+
+		inner_ret = rtw_write_port(padapter, ff_hwaddr, w_sz,
+					   (unsigned char *)pxmitbuf);
+
+		rtw_count_tx_stats(padapter, pxmitframe, sz);
+	}
+
+	rtw_free_xmitframe(pxmitpriv, pxmitframe);
+
+	if (ret != _SUCCESS)
+		rtw_sctx_done_err(&pxmitbuf->sctx, RTW_SCTX_DONE_UNKNOWN);
+
+	return ret;
+}
+
+/*
+ * Packet should not be dequeued if there is no available descriptor
+ * return: _SUCCESS if there is available descriptor
+ */
+static u8 check_tx_desc_resource(_adapter *padapter, int prio)
+{
+	struct xmit_priv	*pxmitpriv = &padapter->xmitpriv;
+	struct rtw_tx_ring	*ring;
+
+	ring = &pxmitpriv->tx_ring[prio];
+
+	/*
+	 * for now we reserve two free descriptor as a safety boundary
+	 * between the tail and the head
+	 */
+
+	if ((ring->entries - ring->qlen) >= 2)
+		return _TRUE;
+	else
+		return _FALSE;
+}
+
+static u8 check_nic_enough_desc_all(_adapter *padapter)
+{
+	u8 status = (check_tx_desc_resource(padapter, VI_QUEUE_INX) &&
+		     check_tx_desc_resource(padapter, VO_QUEUE_INX) &&
+		     check_tx_desc_resource(padapter, BE_QUEUE_INX) &&
+		     check_tx_desc_resource(padapter, BK_QUEUE_INX) &&
+		     check_tx_desc_resource(padapter, MGT_QUEUE_INX) &&
+		     check_tx_desc_resource(padapter, TXCMD_QUEUE_INX) &&
+		     check_tx_desc_resource(padapter, HIGH_QUEUE_INX));
+	return status;
+}
+
+static u8 check_nic_enough_desc(_adapter *padapter, struct pkt_attrib *pattrib)
+{
+	u32 prio;
+	struct xmit_priv	*pxmitpriv = &padapter->xmitpriv;
+	struct rtw_tx_ring	*ring;
+
+	switch (pattrib->qsel) {
+	case 0:
+	case 3:
+		prio = BE_QUEUE_INX;
+		break;
+	case 1:
+	case 2:
+		prio = BK_QUEUE_INX;
+		break;
+	case 4:
+	case 5:
+		prio = VI_QUEUE_INX;
+		break;
+	case 6:
+	case 7:
+		prio = VO_QUEUE_INX;
+		break;
+	default:
+		prio = BE_QUEUE_INX;
+		break;
+	}
+
+	ring = &pxmitpriv->tx_ring[prio];
+
+	/*
+	 * for now we reserve two free descriptor as a safety boundary
+	 * between the tail and the head
+	 */
+	if ((ring->entries - ring->qlen) >= 2)
+		return _TRUE;
+	else
+		return _FALSE;
+}
+
+#ifdef CONFIG_XMIT_THREAD_MODE
+/*
+ * Description
+ *	Transmit xmitbuf to hardware tx fifo
+ *
+ * Return
+ *	_SUCCESS	ok
+ *	_FAIL		something error
+ */
+s32 rtl8821ce_xmit_buf_handler(_adapter *padapter)
+{
+	PHAL_DATA_TYPE phal;
+	struct xmit_priv *pxmitpriv;
+	struct xmit_buf *pxmitbuf;
+	struct xmit_frame *pxmitframe;
+	s32 ret;
+
+	phal = GET_HAL_DATA(padapter);
+	pxmitpriv = &padapter->xmitpriv;
+
+	ret = _rtw_down_sema(&pxmitpriv->xmit_sema);
+
+	if (ret == _FAIL) {
+		RTW_ERR("%s: down XmitBufSema fail!\n", __FUNCTION__);
+		return _FAIL;
+	}
+
+	if (RTW_CANNOT_RUN(padapter)) {
+		RTW_INFO("%s: bDriverStopped(%s) bSurpriseRemoved(%s)!\n"
+			, __func__
+			, rtw_is_drv_stopped(padapter)?"True":"False"
+			, rtw_is_surprise_removed(padapter)?"True":"False");
+		return _FAIL;
+	}
+
+	if (check_pending_xmitbuf(pxmitpriv) == _FALSE)
+		return _SUCCESS;
+
+#ifdef CONFIG_LPS_LCLK
+	ret = rtw_register_tx_alive(padapter);
+	if (ret != _SUCCESS) {
+		RTW_INFO("%s: wait to leave LPS_LCLK\n", __FUNCTION__);
+		return _SUCCESS;
+	}
+#endif
+
+	do {
+		pxmitbuf = select_and_dequeue_pending_xmitbuf(padapter);
+
+		if (pxmitbuf == NULL)
+			break;
+		pxmitframe = (struct xmit_frame *)pxmitbuf->priv_data;
+
+		if (check_nic_enough_desc(padapter, &pxmitframe->attrib) == _FALSE) {
+			enqueue_pending_xmitbuf_to_head(pxmitpriv, pxmitbuf);
+			break;
+		}
+		rtl8821ce_dump_xframe(padapter, pxmitframe);
+	} while (1);
+
+
+	return _SUCCESS;
+}
+#endif
+
+static s32 xmitframe_direct(_adapter *padapter, struct xmit_frame *pxmitframe)
+{
+#ifdef CONFIG_XMIT_THREAD_MODE
+	struct xmit_priv *pxmitpriv = &padapter->xmitpriv;
+#endif
+	s32 res = _SUCCESS;
+
+	res = rtw_xmitframe_coalesce(padapter, pxmitframe->pkt, pxmitframe);
+	if (res == _SUCCESS) {
+	#ifdef CONFIG_XMIT_THREAD_MODE
+		enqueue_pending_xmitbuf(pxmitpriv, pxmitframe->pxmitbuf);
+	#else
+		rtl8821ce_dump_xframe(padapter, pxmitframe);
+	#endif
+	}
+	return res;
+}
+
+#ifdef CONFIG_TX_AMSDU
+static s32 xmitframe_amsdu_direct(_adapter *padapter, struct xmit_frame *pxmitframe)
+{
+	struct xmit_buf *pxmitbuf = pxmitframe->pxmitbuf;
+	struct xmit_priv *pxmitpriv = &padapter->xmitpriv;
+	s32 res = _SUCCESS;
+
+	res = rtw_xmitframe_coalesce_amsdu(padapter, pxmitframe, NULL);
+
+	if (res == _SUCCESS) {
+	#ifdef CONFIG_XMIT_THREAD_MODE
+		enqueue_pending_xmitbuf(pxmitpriv, pxmitframe->pxmitbuf);
+	#else
+		res = rtl8821ce_dump_xframe(padapter, pxmitframe);
+	#endif
+	} else {
+		rtw_free_xmitbuf(pxmitpriv, pxmitbuf);
+		rtw_free_xmitframe(pxmitpriv, pxmitframe);
+	}
+
+	return res;
+}
+#endif
+
+void rtl8821ce_xmitframe_resume(_adapter *padapter)
+{
+	struct xmit_priv *pxmitpriv = &padapter->xmitpriv;
+	struct xmit_frame *pxmitframe = NULL;
+	struct xmit_buf	*pxmitbuf = NULL;
+	int res = _SUCCESS, xcnt = 0;
+
+#ifdef CONFIG_TX_AMSDU
+	struct mlme_priv *pmlmepriv =  &padapter->mlmepriv;
+	struct dvobj_priv	*pdvobjpriv = adapter_to_dvobj(padapter);
+
+	int tx_amsdu = padapter->tx_amsdu;
+	int tx_amsdu_rate = padapter->tx_amsdu_rate;
+	int current_tx_rate = pdvobjpriv->traffic_stat.cur_tx_tp;
+
+	struct pkt_attrib *pattrib = NULL;
+
+	struct xmit_frame *pxmitframe_next = NULL;
+	struct xmit_buf *pxmitbuf_next = NULL;
+	struct pkt_attrib *pattrib_next = NULL;
+	int num_frame = 0;
+
+	u8 amsdu_timeout = 0;
+#endif
+
+	while (1) {
+		if (RTW_CANNOT_RUN(padapter)) {
+			RTW_INFO("%s => bDriverStopped or bSurpriseRemoved\n",
+				 __func__);
+			break;
+		}
+
+	#ifndef CONFIG_XMIT_THREAD_MODE
+		if (!check_nic_enough_desc_all(padapter))
+			break;
+	#endif
+
+		pxmitbuf = rtw_alloc_xmitbuf(pxmitpriv);
+		if (!pxmitbuf)
+			break;
+
+#ifdef CONFIG_TX_AMSDU
+		if (tx_amsdu == 0)
+			goto dump_pkt;
+
+		if (!check_fwstate(pmlmepriv, WIFI_STATION_STATE))
+			goto dump_pkt;
+
+		pxmitframe = rtw_get_xframe(pxmitpriv, &num_frame);
+
+		if (num_frame == 0 || pxmitframe == NULL || !check_amsdu(pxmitframe))
+			goto dump_pkt;
+
+		pattrib = &pxmitframe->attrib;
+
+		if (tx_amsdu == 1) {
+			pxmitframe =  rtw_dequeue_xframe(pxmitpriv, pxmitpriv->hwxmits,
+						pxmitpriv->hwxmit_entry);
+			if (pxmitframe) {
+				pxmitframe->pxmitbuf = pxmitbuf;
+				pxmitframe->buf_addr = pxmitbuf->pbuf;
+				pxmitbuf->priv_data = pxmitframe;
+				xmitframe_amsdu_direct(padapter, pxmitframe);
+				pxmitpriv->amsdu_debug_coalesce_one++;
+				continue;
+			} else {
+				rtw_free_xmitbuf(pxmitpriv, pxmitbuf);
+				break;
+			}
+		} else if (tx_amsdu == 2 && ((tx_amsdu_rate == 0) || (current_tx_rate > tx_amsdu_rate))) {
+
+			if (num_frame == 1) {
+				amsdu_timeout = rtw_amsdu_get_timer_status(padapter, pattrib->priority);
+
+				if (amsdu_timeout == RTW_AMSDU_TIMER_UNSET) {
+					rtw_free_xmitbuf(pxmitpriv, pxmitbuf);
+					rtw_amsdu_set_timer_status(padapter,
+						pattrib->priority, RTW_AMSDU_TIMER_SETTING);
+					rtw_amsdu_set_timer(padapter, pattrib->priority);
+					pxmitpriv->amsdu_debug_set_timer++;
+					break;
+				} else if (amsdu_timeout == RTW_AMSDU_TIMER_SETTING) {
+					rtw_free_xmitbuf(pxmitpriv, pxmitbuf);
+					break;
+				} else if (amsdu_timeout == RTW_AMSDU_TIMER_TIMEOUT) {
+					rtw_amsdu_set_timer_status(padapter,
+						pattrib->priority, RTW_AMSDU_TIMER_UNSET);
+					pxmitpriv->amsdu_debug_timeout++;
+					pxmitframe = rtw_dequeue_xframe(pxmitpriv,
+						pxmitpriv->hwxmits, pxmitpriv->hwxmit_entry);
+					if (pxmitframe) {
+						pxmitframe->pxmitbuf = pxmitbuf;
+						pxmitframe->buf_addr = pxmitbuf->pbuf;
+						pxmitbuf->priv_data = pxmitframe;
+						xmitframe_amsdu_direct(padapter, pxmitframe);
+					} else {
+						rtw_free_xmitbuf(pxmitpriv, pxmitbuf);
+					}
+					break;
+				}
+			} else/* num_frame > 1*/{
+				pxmitframe = rtw_dequeue_xframe(pxmitpriv,
+					pxmitpriv->hwxmits, pxmitpriv->hwxmit_entry);
+
+				if (!pxmitframe) {
+					rtw_free_xmitbuf(pxmitpriv, pxmitbuf);
+					break;
+				}
+
+				pxmitframe->pxmitbuf = pxmitbuf;
+				pxmitframe->buf_addr = pxmitbuf->pbuf;
+				pxmitbuf->priv_data = pxmitframe;
+
+				pxmitframe_next = rtw_get_xframe(pxmitpriv, &num_frame);
+
+				if (num_frame == 0) {
+					xmitframe_amsdu_direct(padapter, pxmitframe);
+					pxmitpriv->amsdu_debug_coalesce_one++;
+					break;
+				}
+
+				if (!check_amsdu(pxmitframe_next)) {
+					xmitframe_amsdu_direct(padapter, pxmitframe);
+					pxmitpriv->amsdu_debug_coalesce_one++;
+					continue;
+				} else {
+					pxmitbuf_next = rtw_alloc_xmitbuf(pxmitpriv);
+					if (!pxmitbuf_next) {
+						xmitframe_amsdu_direct(padapter, pxmitframe);
+						pxmitpriv->amsdu_debug_coalesce_one++;
+						continue;
+					}
+
+					pxmitframe_next = rtw_dequeue_xframe(pxmitpriv,
+						pxmitpriv->hwxmits, pxmitpriv->hwxmit_entry);
+					if (!pxmitframe_next) {
+						rtw_free_xmitbuf(pxmitpriv, pxmitbuf_next);
+						xmitframe_amsdu_direct(padapter, pxmitframe);
+						pxmitpriv->amsdu_debug_coalesce_one++;
+						continue;
+					}
+
+					pxmitframe_next->pxmitbuf = pxmitbuf_next;
+					pxmitframe_next->buf_addr = pxmitbuf_next->pbuf;
+					pxmitbuf_next->priv_data = pxmitframe_next;
+
+					rtw_xmitframe_coalesce_amsdu(padapter,
+						pxmitframe_next, pxmitframe);
+					rtw_free_xmitframe(pxmitpriv, pxmitframe);
+					rtw_free_xmitbuf(pxmitpriv, pxmitbuf);
+
+#ifdef CONFIG_XMIT_THREAD_MODE
+					enqueue_pending_xmitbuf(pxmitpriv, pxmitframe_next->pxmitbuf);
+#else
+					rtl8821ce_dump_xframe(padapter, pxmitframe_next);
+#endif
+					pxmitpriv->amsdu_debug_coalesce_two++;
+
+					continue;
+				}
+
+			}
+
+		}
+dump_pkt:
+#endif /* CONFIG_TX_AMSDU */
+
+		pxmitframe =  rtw_dequeue_xframe(pxmitpriv, pxmitpriv->hwxmits,
+						 pxmitpriv->hwxmit_entry);
+
+		if (pxmitframe) {
+			pxmitframe->pxmitbuf = pxmitbuf;
+			pxmitframe->buf_addr = pxmitbuf->pbuf;
+			pxmitbuf->priv_data = pxmitframe;
+
+			if ((pxmitframe->frame_tag & 0x0f) == DATA_FRAMETAG) {
+				if (pxmitframe->attrib.priority <= 15) {
+					/* TID0~15 */
+					res = rtw_xmitframe_coalesce(padapter,
+						pxmitframe->pkt, pxmitframe);
+				}
+
+				/* always return ndis_packet after
+				 * rtw_xmitframe_coalesce
+				*/
+				rtw_os_xmit_complete(padapter, pxmitframe);
+			}
+
+
+			if (res == _SUCCESS) {
+			#ifdef CONFIG_XMIT_THREAD_MODE
+				enqueue_pending_xmitbuf(pxmitpriv, pxmitframe->pxmitbuf);
+			#else
+				rtl8821ce_dump_xframe(padapter, pxmitframe);
+			#endif
+			} else {
+				rtw_free_xmitbuf(pxmitpriv, pxmitbuf);
+				rtw_free_xmitframe(pxmitpriv, pxmitframe);
+			}
+
+			xcnt++;
+		} else {
+			rtw_free_xmitbuf(pxmitpriv, pxmitbuf);
+			break;
+		}
+	}
+}
+
+/*
+ * Return
+ *	_TRUE	dump packet directly
+ *	_FALSE	enqueue packet
+ */
+static s32 pre_xmitframe(_adapter *padapter, struct xmit_frame *pxmitframe)
+{
+	_irqL irqL;
+	s32 res;
+	struct xmit_buf *pxmitbuf = NULL;
+	struct xmit_priv *pxmitpriv = &padapter->xmitpriv;
+	struct pkt_attrib *pattrib = &pxmitframe->attrib;
+	struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
+
+#ifdef CONFIG_TX_AMSDU
+	int tx_amsdu = padapter->tx_amsdu;
+	u8 amsdu_timeout = 0;
+#endif
+	_enter_critical_bh(&pxmitpriv->lock, &irqL);
+
+	if (rtw_txframes_sta_ac_pending(padapter, pattrib) > 0)
+		goto enqueue;
+
+#ifndef CONFIG_XMIT_THREAD_MODE
+	if (check_nic_enough_desc(padapter, pattrib) == _FALSE)
+		goto enqueue;
+
+	if (rtw_xmit_ac_blocked(padapter) == _TRUE)
+		goto enqueue;
+#endif
+
+	if (DEV_STA_LG_NUM(padapter->dvobj))
+		goto enqueue;
+
+#ifdef CONFIG_TX_AMSDU
+	if (check_fwstate(pmlmepriv, WIFI_STATION_STATE) &&
+		check_amsdu_tx_support(padapter)) {
+
+		if (IS_AMSDU_AMPDU_VALID(pattrib))
+			goto enqueue;
+	}
+#endif
+
+	pxmitbuf = rtw_alloc_xmitbuf(pxmitpriv);
+	if (pxmitbuf == NULL)
+		goto enqueue;
+
+	_exit_critical_bh(&pxmitpriv->lock, &irqL);
+
+	pxmitframe->pxmitbuf = pxmitbuf;
+	pxmitframe->buf_addr = pxmitbuf->pbuf;
+	pxmitbuf->priv_data = pxmitframe;
+
+	if (xmitframe_direct(padapter, pxmitframe) != _SUCCESS) {
+		rtw_free_xmitbuf(pxmitpriv, pxmitbuf);
+		rtw_free_xmitframe(pxmitpriv, pxmitframe);
+	}
+
+	return _TRUE;
+
+enqueue:
+	res = rtw_xmitframe_enqueue(padapter, pxmitframe);
+
+#ifdef CONFIG_TX_AMSDU
+	if (res == _SUCCESS && tx_amsdu == 2) {
+		amsdu_timeout = rtw_amsdu_get_timer_status(padapter, pattrib->priority);
+		if (amsdu_timeout == RTW_AMSDU_TIMER_SETTING) {
+			rtw_amsdu_cancel_timer(padapter, pattrib->priority);
+			rtw_amsdu_set_timer_status(padapter, pattrib->priority,
+				RTW_AMSDU_TIMER_UNSET);
+		}
+	}
+#endif
+	_exit_critical_bh(&pxmitpriv->lock, &irqL);
+
+	if (res != _SUCCESS) {
+		rtw_free_xmitframe(pxmitpriv, pxmitframe);
+
+		pxmitpriv->tx_drop++;
+		return _TRUE;
+	}
+
+#ifdef CONFIG_TX_AMSDU
+	tasklet_hi_schedule(&pxmitpriv->xmit_tasklet);
+#endif
+	return _FALSE;
+}
+
+s32 rtl8821ce_mgnt_xmit(_adapter *padapter, struct xmit_frame *pmgntframe)
+{
+
+#ifdef CONFIG_XMIT_THREAD_MODE
+	struct xmit_priv *pxmitpriv = &padapter->xmitpriv;
+	struct pkt_attrib	*pattrib = &pmgntframe->attrib;
+	s32 ret = _SUCCESS;
+
+	/* For FW download rsvd page and H2C pkt */
+	if ((pattrib->qsel == QSLT_CMD) || (pattrib->qsel == QSLT_BEACON))
+		ret = rtl8821ce_dump_xframe(padapter, pmgntframe);
+	else
+		enqueue_pending_xmitbuf(pxmitpriv, pmgntframe->pxmitbuf);
+	return ret;
+
+#else
+	return rtl8821ce_dump_xframe(padapter, pmgntframe);
+#endif
+}
+
+/*
+ * Return
+ *	_TRUE	dump packet directly ok
+ *	_FALSE	temporary can't transmit packets to hardware
+ */
+s32 rtl8821ce_hal_xmit(_adapter *padapter, struct xmit_frame *pxmitframe)
+{
+	return pre_xmitframe(padapter, pxmitframe);
+}
+
+s32 rtl8821ce_hal_xmitframe_enqueue(_adapter *padapter,
+				    struct xmit_frame *pxmitframe)
+{
+	struct xmit_priv *pxmitpriv = &padapter->xmitpriv;
+	s32 err;
+
+	err = rtw_xmitframe_enqueue(padapter, pxmitframe);
+	if (err != _SUCCESS) {
+		rtw_free_xmitframe(pxmitpriv, pxmitframe);
+		pxmitpriv->tx_drop++;
+	} else {
+#ifdef PLATFORM_LINUX
+		if (check_nic_enough_desc(padapter,
+					  &pxmitframe->attrib) == _TRUE)
+			tasklet_hi_schedule(&pxmitpriv->xmit_tasklet);
+#endif
+	}
+
+	return err;
+}
+
+int rtl8821ce_init_txbd_ring(_adapter *padapter, unsigned int q_idx,
+			     unsigned int entries)
+{
+	struct xmit_priv *t_priv = &padapter->xmitpriv;
+	struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(padapter);
+	struct pci_dev *pdev = pdvobjpriv->ppcidev;
+	struct tx_buf_desc *txbd;
+	u8 *tx_desc;
+	dma_addr_t dma;
+	int i;
+
+
+	RTW_INFO("%s entries num:%d\n", __func__, entries);
+
+	txbd = pci_alloc_consistent(pdev, sizeof(*txbd) * entries, &dma);
+
+	if (!txbd || (unsigned long)txbd & 0xFF) {
+		RTW_INFO("Cannot allocate TXBD (q_idx = %d)\n", q_idx);
+		return _FAIL;
+	}
+
+	_rtw_memset(txbd, 0, sizeof(*txbd) * entries);
+	t_priv->tx_ring[q_idx].buf_desc = txbd;
+	t_priv->tx_ring[q_idx].dma = dma;
+	t_priv->tx_ring[q_idx].idx = 0;
+	t_priv->tx_ring[q_idx].entries = entries;
+	_rtw_init_queue(&t_priv->tx_ring[q_idx].queue);
+	t_priv->tx_ring[q_idx].qlen = 0;
+
+	RTW_INFO("%s queue:%d, ring_addr:%p\n", __func__, q_idx, txbd);
+
+
+	return _SUCCESS;
+}
+
+void rtl8821ce_free_txbd_ring(_adapter *padapter, unsigned int prio)
+{
+	struct xmit_priv *t_priv = &padapter->xmitpriv;
+	struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(padapter);
+	struct pci_dev *pdev = pdvobjpriv->ppcidev;
+	struct rtw_tx_ring *ring = &t_priv->tx_ring[prio];
+	u8 *txbd;
+	struct xmit_buf	*pxmitbuf;
+	dma_addr_t mapping;
+
+
+	while (ring->qlen) {
+		txbd = (u8 *)(&ring->buf_desc[ring->idx]);
+		SET_TX_BD_OWN(txbd, 0);
+
+		if (prio != BCN_QUEUE_INX)
+			ring->idx = (ring->idx + 1) % ring->entries;
+
+		pxmitbuf = rtl8821ce_dequeue_xmitbuf(ring);
+
+		if (pxmitbuf) {
+			mapping = GET_TX_BD_PHYSICAL_ADDR0_LOW(txbd);
+		#ifdef CONFIG_64BIT_DMA
+			mapping |= (dma_addr_t)GET_TX_BD_PHYSICAL_ADDR0_HIGH(txbd) << 32;
+		#endif
+			pci_unmap_single(pdev,
+				mapping,
+				pxmitbuf->len, PCI_DMA_TODEVICE);
+
+			rtw_free_xmitbuf(t_priv, pxmitbuf);
+
+		} else {
+			RTW_INFO("%s qlen=%d!=0,but have xmitbuf in pendingQ\n",
+				 __func__, ring->qlen);
+			break;
+		}
+	}
+
+	pci_free_consistent(pdev, sizeof(*ring->buf_desc) * ring->entries,
+			    ring->buf_desc, ring->dma);
+	ring->buf_desc = NULL;
+
+}
+
+/*
+ * Draw a line to show queue status. For debug
+ * i: queue index / W:HW index / h:host index / .: enpty entry / *:ready to DMA
+ * Example:  R- 3- 4- 8 ..iW***h..... (i=3,W=4,h=8,
+ * *** means 3 tx_desc is reaady to dma)
+ */
+#ifdef BUF_DESC_DEBUG
+static void _draw_queue(PADAPTER Adapter, int prio)
+{
+	int i;
+	u8 line[TX_BD_NUM_8821CE + 1];
+	u16 hw, host;
+	u32	index, tmp_4bytes = 0;
+
+	struct xmit_priv	*t_priv = &Adapter->xmitpriv;
+	struct rtw_tx_ring	*ring = &t_priv->tx_ring[prio];
+
+	tmp_4bytes = rtw_read32(Adapter, get_txbd_rw_reg(prio));
+	hw   = (u16)((tmp_4bytes >> 16) & 0x7ff);
+	host = (u16)(tmp_4bytes & 0x7ff);
+
+	index = ring->idx;
+	_rtw_memset(line, '.', TX_BD_NUM_8821CE);
+
+	/* ready to return to driver */
+	if (index <= hw) {
+		for (i = index; i < hw; i++)
+			line[i] = ':';
+	} else { /* wrap */
+		for (i = index; i < TX_BD_NUM_8821CE; i++)
+			line[i] = ':';
+		for (i = 0; i < hw; i++)
+			line[i] = ':';
+	}
+
+	/* ready to dma */
+	if (hw <= host) {
+		for (i = hw; i < host; i++)
+			line[i] = '*';
+	} else { /* wrap */
+		for (i = hw; i < TX_BD_NUM_8821CE; i++)
+			line[i] = '*';
+		for (i = 0; i < host; i++)
+			line[i] = '*';
+	}
+
+	line[index] = 'i'; /* software queue index */
+	line[host] = 'h';  /* host index */
+	line[hw] = 'W';	   /* hardware index */
+	line[TX_BD_NUM_8821CE] = 0x0;
+
+	/* Q2:10-20-30: */
+	buf_desc_debug("Q%d:%02d-%02d-%02d %s\n", prio, index, hw, host, line);
+}
+#endif
+
+/*
+ * Read pointer is h/w descriptor index
+ * Write pointer is host desciptor index: For tx side, if own bit is set in
+ * packet index n, host pointer (write pointer) point to index n + 1.
+ */
+static u32 rtl8821ce_check_txdesc_closed(PADAPTER Adapter, u32 queue_idx,
+		struct rtw_tx_ring *ring)
+{
+	/*
+	 * hw_rp_cache is used to reduce REG access.
+	 */
+	u32	tmp32;
+
+	/* bcn queue should not enter this function */
+	if (queue_idx == BCN_QUEUE_INX)
+		return _TRUE;
+
+	/* qlen == 0 --> don't need to process */
+	if (ring->qlen == 0)
+		return _FALSE;
+
+	/* sw_rp == hw_rp_cache --> sync hw_rp */
+	if (ring->idx == ring->hw_rp_cache) {
+
+		tmp32 = rtw_read32(Adapter, get_txbd_rw_reg(queue_idx));
+
+		ring->hw_rp_cache = (tmp32 >> 16) & 0x0FFF;
+	}
+
+	/* check if need to handle TXOK */
+	if (ring->idx == ring->hw_rp_cache)
+		return _FALSE;
+
+	return _TRUE;
+}
+
+#ifdef CONFIG_BCN_ICF
+void rtl8821ce_tx_isr(PADAPTER Adapter, int prio)
+{
+	struct xmit_priv *t_priv = &Adapter->xmitpriv;
+	struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(Adapter);
+	struct rtw_tx_ring *ring = &t_priv->tx_ring[prio];
+	struct xmit_buf	*pxmitbuf;
+	u8 *tx_desc;
+	u16 tmp_4bytes;
+	u16 desc_idx_hw = 0, desc_idx_host = 0;
+	dma_addr_t mapping;
+
+#ifdef CONFIG_LPS_LCLK
+	int index;
+	s32 enter32k = _SUCCESS;
+	struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(Adapter);
+#endif
+
+	while (ring->qlen) {
+		tx_desc = (u8 *)&ring->buf_desc[ring->idx];
+
+		/*  beacon use cmd buf Never run into here */
+		if (!rtl8821ce_check_txdesc_closed(Adapter, prio, ring))
+			return;
+
+		buf_desc_debug("TX: %s, q_idx = %d, tx_bd = %04x, close [%04x] r_idx [%04x]\n",
+			       __func__, prio, (u32)tx_desc, ring->idx,
+			       (ring->idx + 1) % ring->entries);
+
+		ring->idx = (ring->idx + 1) % ring->entries;
+		pxmitbuf = rtl8821ce_dequeue_xmitbuf(ring);
+
+		if (pxmitbuf) {
+			mapping = GET_TX_BD_PHYSICAL_ADDR0_LOW(tx_desc);
+		#ifdef CONFIG_64BIT_DMA
+			mapping |= (dma_addr_t)GET_TX_BD_PHYSICAL_ADDR0_HIGH(tx_desc) << 32;
+		#endif
+			pci_unmap_single(pdvobjpriv->ppcidev,
+				mapping,
+				pxmitbuf->len, PCI_DMA_TODEVICE);
+			rtw_sctx_done(&pxmitbuf->sctx);
+			rtw_free_xmitbuf(&(pxmitbuf->padapter->xmitpriv),
+					 pxmitbuf);
+		} else {
+			RTW_INFO("%s qlen=%d!=0,but have xmitbuf in pendingQ\n",
+				 __func__, ring->qlen);
+		}
+	}
+
+#ifdef CONFIG_LPS_LCLK
+	for (index = 0; index < HW_QUEUE_ENTRY; index++) {
+		if (index != BCN_QUEUE_INX) {
+			if (_rtw_queue_empty(&(Adapter->xmitpriv.tx_ring[index].queue)) == _FALSE) {
+				enter32k = _FAIL;
+				break;
+			}
+		}
+	}
+	if (enter32k)
+		_set_workitem(&(pwrpriv->dma_event));
+#endif
+
+	if (check_tx_desc_resource(Adapter, prio)
+	    && rtw_xmit_ac_blocked(Adapter) != _TRUE)
+		rtw_mi_xmit_tasklet_schedule(Adapter);
+}
+
+#else /* !CONFIG_BCN_ICF */
+void rtl8821ce_tx_isr(PADAPTER Adapter, int prio)
+{
+	struct xmit_priv *t_priv = &Adapter->xmitpriv;
+	struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(Adapter);
+	struct rtw_tx_ring *ring = &t_priv->tx_ring[prio];
+	struct xmit_buf	*pxmitbuf;
+	u8 *tx_desc;
+	u16 tmp_4bytes;
+	u16 desc_idx_hw = 0, desc_idx_host = 0;
+
+#ifdef CONFIG_LPS_LCLK
+	int index;
+	s32 enter32k = _SUCCESS;
+	struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(Adapter);
+#endif
+
+	while (ring->qlen) {
+		tx_desc = (u8 *)&ring->buf_desc[ring->idx];
+
+		/*
+		 * beacon packet will only use the first descriptor defautly,
+		 * check register to see whether h/w has consumed buffer
+		 * descriptor
+		 */
+		if (prio != BCN_QUEUE_INX) {
+			if (!rtl8821ce_check_txdesc_closed(Adapter,
+							   prio, ring->idx))
+				return;
+
+			buf_desc_debug("TX: %s, queue_idx = %d, tx_desc = %04x, close desc [%04x] and update ring->idx to [%04x]\n",
+				       __func__, prio, (u32)tx_desc, ring->idx,
+				       (ring->idx + 1) % ring->entries);
+			ring->idx = (ring->idx + 1) % ring->entries;
+		}
+		#if 0 /* 8821c change 00[31] to DISQSELSEQ */
+		else if (prio == BCN_QUEUE_INX)
+			SET_TX_DESC_OWN_92E(tx_desc, 0);
+		#endif
+
+		pxmitbuf = rtl8821ce_dequeue_xmitbuf(ring);
+		if (pxmitbuf) {
+			dma_addr_t mapping;
+			mapping = GET_TX_BD_PHYSICAL_ADDR0_LOW(tx_desc);
+		#ifdef CONFIG_64BIT_DMA
+			mapping |= (dma_addr_t)GET_TX_BD_PHYSICAL_ADDR0_HIGH(tx_desc) << 32;
+		#endif
+			pci_unmap_single(pdvobjpriv->ppcidev,
+				 	mapping,
+					 pxmitbuf->len, PCI_DMA_TODEVICE);
+			rtw_sctx_done(&pxmitbuf->sctx);
+			rtw_free_xmitbuf(&(pxmitbuf->padapter->xmitpriv),
+					 pxmitbuf);
+		} else {
+			RTW_INFO("%s qlen=%d!=0,but have xmitbuf in pendingQ\n",
+				 __func__, ring->qlen);
+		}
+	}
+
+#ifdef CONFIG_LPS_LCLK
+	for (index = 0; index < HW_QUEUE_ENTRY; index++) {
+		if (index != BCN_QUEUE_INX) {
+			if (_rtw_queue_empty(&(Adapter->xmitpriv.tx_ring[index].queue)) == _FALSE) {
+				enter32k = _FAIL;
+				break;
+			}
+		}
+	}
+	if (enter32k)
+		_set_workitem(&(pwrpriv->dma_event));
+#endif
+
+	if ((prio != BCN_QUEUE_INX) && check_tx_desc_resource(Adapter, prio)
+	    && rtw_xmit_ac_blocked(Adapter) != _TRUE)
+		rtw_mi_xmit_tasklet_schedule(Adapter);
+}
+#endif /* CONFIG_BCN_ICF */
+
+#ifdef CONFIG_HOSTAPD_MLME
+static void rtl8812ae_hostap_mgnt_xmit_cb(struct urb *urb)
+{
+#ifdef PLATFORM_LINUX
+	struct sk_buff *skb = (struct sk_buff *)urb->context;
+
+	dev_kfree_skb_any(skb);
+#endif
+}
+
+s32 rtl8821ce_hostap_mgnt_xmit_entry(_adapter *padapter, _pkt *pkt)
+{
+#ifdef PLATFORM_LINUX
+	u16 fc;
+	int rc, len, pipe;
+	unsigned int bmcst, tid, qsel;
+	struct sk_buff *skb, *pxmit_skb;
+	struct urb *urb;
+	unsigned char *pxmitbuf;
+	struct tx_desc *ptxdesc;
+	struct rtw_ieee80211_hdr *tx_hdr;
+	struct hostapd_priv *phostapdpriv = padapter->phostapdpriv;
+	struct net_device *pnetdev = padapter->pnetdev;
+	HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
+	struct dvobj_priv *pdvobj = adapter_to_dvobj(padapter);
+
+
+	skb = pkt;
+	len = skb->len;
+	tx_hdr = (struct rtw_ieee80211_hdr *)(skb->data);
+	fc = le16_to_cpu(tx_hdr->frame_ctl);
+	bmcst = IS_MCAST(tx_hdr->addr1);
+
+	if ((fc & RTW_IEEE80211_FCTL_FTYPE) != RTW_IEEE80211_FTYPE_MGMT)
+		goto _exit;
+
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 18))
+	/* http://www.mail-archive.com/netdev@vger.kernel.org/msg17214.html */
+	pxmit_skb = dev_alloc_skb(len + TXDESC_SIZE);
+#else
+	pxmit_skb = netdev_alloc_skb(pnetdev, len + TXDESC_SIZE);
+#endif
+
+	if (!pxmit_skb)
+		goto _exit;
+
+	pxmitbuf = pxmit_skb->data;
+
+	urb = usb_alloc_urb(0, GFP_ATOMIC);
+	if (!urb)
+		goto _exit;
+
+	/* ----- fill tx desc ----- */
+	ptxdesc = (struct tx_desc *)pxmitbuf;
+	_rtw_memset(ptxdesc, 0, sizeof(*ptxdesc));
+
+	/* offset 0 */
+	ptxdesc->txdw0 |= cpu_to_le32(len & 0x0000ffff);
+	/* default = 32 bytes for TX Desc */
+	ptxdesc->txdw0 |= cpu_to_le32(((TXDESC_SIZE + OFFSET_SZ) << OFFSET_SHT) &
+				      0x00ff0000);
+	ptxdesc->txdw0 |= cpu_to_le32(OWN | FSG | LSG);
+
+	if (bmcst)
+		ptxdesc->txdw0 |= cpu_to_le32(BIT(24));
+
+	/* offset 4 */
+	ptxdesc->txdw1 |= cpu_to_le32(0x00);/* MAC_ID */
+
+	ptxdesc->txdw1 |= cpu_to_le32((0x12 << QSEL_SHT) & 0x00001f00);
+
+	ptxdesc->txdw1 |= cpu_to_le32((0x06 << 16) & 0x000f0000);/* b mode */
+
+	/* offset 8 */
+
+	/* offset 12 */
+	ptxdesc->txdw3 |= cpu_to_le32((le16_to_cpu(tx_hdr->seq_ctl) << 16) &
+				      0xffff0000);
+
+	/* offset 16 */
+	ptxdesc->txdw4 |= cpu_to_le32(BIT(8));/* driver uses rate */
+
+	/* offset 20 */
+
+	rtl8188e_cal_txdesc_chksum(ptxdesc);
+	/* ----- end of fill tx desc ----- */
+
+	skb_put(pxmit_skb, len + TXDESC_SIZE);
+	pxmitbuf = pxmitbuf + TXDESC_SIZE;
+	_rtw_memcpy(pxmitbuf, skb->data, len);
+
+	/* ----- prepare urb for submit ----- */
+
+	/* translate DMA FIFO addr to pipehandle */
+	/*pipe = ffaddr2pipehdl(pdvobj, MGT_QUEUE_INX);*/
+	pipe = usb_sndbulkpipe(pdvobj->pusbdev,
+			       pHalData->Queue2EPNum[(u8)MGT_QUEUE_INX] & 0x0f);
+
+	usb_fill_bulk_urb(urb, pdvobj->pusbdev, pipe, pxmit_skb->data,
+		  pxmit_skb->len, rtl8188ee_hostap_mgnt_xmit_cb, pxmit_skb);
+
+	urb->transfer_flags |= URB_ZERO_PACKET;
+	usb_anchor_urb(urb, &phostapdpriv->anchored);
+	rc = usb_submit_urb(urb, GFP_ATOMIC);
+	if (rc < 0) {
+		usb_unanchor_urb(urb);
+		kfree_skb(skb);
+	}
+	usb_free_urb(urb);
+
+
+_exit:
+
+	dev_kfree_skb_any(skb);
+#endif
+	return 0;
+
+}
+#endif
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/rtl8821c/rtl8821c_cmd.c linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/rtl8821c/rtl8821c_cmd.c
--- linux-5.6.3/3rdparty/rtl8821ce/hal/rtl8821c/rtl8821c_cmd.c	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/rtl8821c/rtl8821c_cmd.c	2020-04-10 16:35:06.843661328 +0300
@@ -0,0 +1,460 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2016 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#define _RTL8821C_CMD_C_
+
+#include <hal_data.h>		/* HAL_DATA_TYPE */
+#include "../hal_halmac.h"	/* HRTW_HALMAC_H2C_MAX_SIZE, CMD_ID_RSVD_PAGE and etc. */
+#include "rtl8821c.h"
+
+/*
+ * Below functions are for C2H
+ */
+/*****************************************
+ * H2C Msg format :
+ *| 31 - 8		|7-5	| 4 - 0	|
+ *| h2c_msg		|Class	|CMD_ID	|
+ *| 31-0				|
+ *| Ext msg				|
+ *
+ ******************************************/
+s32 rtl8821c_fillh2ccmd(PADAPTER adapter, u8 id, u32 buf_len, u8 *pbuf)
+{
+	u8 h2c[RTW_HALMAC_H2C_MAX_SIZE] = {0};
+#ifdef DBG_H2C_CONTENT
+	u8 msg[(RTW_HALMAC_H2C_MAX_SIZE - 1) * 5 + 1] = {0};
+	u8 *msg_p;
+	u32 msg_size, i, n;
+#endif /* CONFIG_RTW_DEBUG */
+	int err;
+	s32 ret = _FAIL;
+
+
+	if (!pbuf)
+		goto exit;
+
+	if (buf_len > (RTW_HALMAC_H2C_MAX_SIZE - 1))
+		goto exit;
+
+	if (rtw_is_surprise_removed(adapter))
+		goto exit;
+
+#ifdef DBG_H2C_CONTENT
+	msg_p = msg;
+	msg_size = (RTW_HALMAC_H2C_MAX_SIZE - 1) * 5 + 1;
+	for (i = 0; i < buf_len; i++) {
+		n = rtw_sprintf(msg_p, msg_size, " 0x%02x", pbuf[i]);
+		msg_p += n;
+		msg_size -= n;
+		if (msg_size == 0)
+			break;
+	}
+	RTW_INFO(FUNC_ADPT_FMT ": id=0x%02x buf=%s\n",
+		 FUNC_ADPT_ARG(adapter), id, msg);
+#endif /* CONFIG_RTW_DEBUG */
+
+	h2c[0] = id;
+	_rtw_memcpy(h2c + 1, pbuf, buf_len);
+
+	err = rtw_halmac_send_h2c(adapter_to_dvobj(adapter), h2c);
+	if (!err)
+		ret = _SUCCESS;
+
+exit:
+
+	return ret;
+}
+
+static u8 get_ra_vht_en(u32 wirelessMode, u32 bitmap)
+{
+	u8 ret = 0;
+
+	if (wirelessMode == WIRELESS_11_24AC) {
+		if (bitmap & 0xfff00000) /* 2SS */
+			ret = 3;
+		else 					/* 1SS */
+			ret = 2;
+	} else if (wirelessMode == WIRELESS_11_5AC)
+		ret = 1;
+
+	return ret;
+}
+
+#define SET_PWR_MODE_SET_BCN_RECEIVING_TIME(h2c_pkt, value)                    \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 24, 5, value)
+#define SET_PWR_MODE_SET_ADOPT_BCN_RECEIVING_TIME(h2c_pkt, value)              \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 31, 1, value)
+
+void rtl8821c_set_FwPwrMode_cmd(PADAPTER adapter, u8 psmode)
+{
+	u8 mode = 0, smart_ps = 0;
+	struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(adapter);
+#ifdef CONFIG_BCN_RECV_TIME
+	u8 bcn_recv_time;
+	struct mlme_ext_priv *pmlmeext = &adapter->mlmeextpriv;
+#endif
+#ifdef CONFIG_WMMPS_STA
+	struct mlme_priv	*pmlmepriv = &(adapter->mlmepriv);
+	struct qos_priv	*pqospriv = &pmlmepriv->qospriv;
+#endif /* CONFIG_WMMPS_STA */	
+	u8 h2c[RTW_HALMAC_H2C_MAX_SIZE] = {0};
+	u8 PowerState = 0, awake_intvl = 1, rlbm = 0;
+	u8 allQueueUAPSD = 0;
+	char *fw_psmode_str = "";
+#ifdef CONFIG_P2P
+	struct wifidirect_info *wdinfo = &adapter->wdinfo;
+#endif /* CONFIG_P2P */
+	u8 hw_port = rtw_hal_get_port(adapter);
+
+	if (pwrpriv->dtim > 0)
+		RTW_INFO(FUNC_ADPT_FMT ": dtim=%d, HW port id=%d\n", FUNC_ADPT_ARG(adapter),
+			pwrpriv->dtim, psmode == PS_MODE_ACTIVE ? pwrpriv->current_lps_hw_port_id : hw_port);
+	else
+		RTW_INFO(FUNC_ADPT_FMT ": HW port id=%d\n", FUNC_ADPT_ARG(adapter),
+			psmode == PS_MODE_ACTIVE ? pwrpriv->current_lps_hw_port_id : hw_port);
+
+	smart_ps = pwrpriv->smart_ps;
+	switch (psmode) {
+		case PS_MODE_MIN:
+		case PS_MODE_MAX:
+			{
+#ifdef CONFIG_WMMPS_STA	
+				if (rtw_is_wmmps_mode(adapter)) {
+					mode = 2;
+
+					smart_ps = pwrpriv->wmm_smart_ps;
+
+					/* (WMMPS) allQueueUAPSD: 0: PSPoll, 1: QosNullData (if wmm_smart_ps=1) or do nothing (if wmm_smart_ps=2) */
+					if ((pqospriv->uapsd_tid & BIT_MASK_TID_TC) == ALL_TID_TC_SUPPORTED_UAPSD)
+						allQueueUAPSD = 1;
+				} else
+#endif /* CONFIG_WMMPS_STA */
+				{
+					mode = 1;
+#ifdef CONFIG_WMMPS_STA	
+					/* For WMMPS test case, the station must retain sleep mode to capture buffered data on LPS mechanism */ 
+					if ((pqospriv->uapsd_tid & BIT_MASK_TID_TC)  != 0)
+						smart_ps = 0;
+					else
+#endif /* CONFIG_WMMPS_STA */
+					{
+						smart_ps = pwrpriv->smart_ps;
+					}
+				}
+
+				if (psmode == PS_MODE_MIN)
+					rlbm = 0;
+				else
+					rlbm = 1;
+			}
+			break;
+		case PS_MODE_DTIM:
+			{
+				mode = 1;
+				rlbm = 2;
+
+				/* For WOWLAN LPS, DTIM = (awake_intvl - 1) */
+				if (pwrpriv->dtim > 0 && pwrpriv->dtim < 16) /* DTIM = (awake_intvl - 1) */
+					awake_intvl = pwrpriv->dtim + 1;
+				else /* DTIM = 3 */
+					awake_intvl = 4;
+			}
+			break;
+		case PS_MODE_ACTIVE:
+		default:
+			mode = 0;
+			break;
+	}
+
+#ifdef CONFIG_P2P
+	if (!rtw_p2p_chk_state(wdinfo, P2P_STATE_NONE)) {
+		awake_intvl = 2;
+		rlbm = 1;
+	}
+#endif /* CONFIG_P2P */
+
+	if (adapter->registrypriv.wifi_spec == 1) {
+		awake_intvl = 2;
+		rlbm = 1;
+	}
+
+	if (psmode > 0) {
+#ifdef CONFIG_BT_COEXIST
+		if (rtw_btcoex_IsBtControlLps(adapter) == _TRUE)
+			PowerState = rtw_btcoex_RpwmVal(adapter);
+		else
+#endif /* CONFIG_BT_COEXIST */
+			PowerState = 0x00; /* AllON(0x0C), RFON(0x04), RFOFF(0x00) */
+	} else
+		PowerState = 0x0C; /* AllON(0x0C), RFON(0x04), RFOFF(0x00) */
+
+	if (mode == 0)
+		fw_psmode_str = "ACTIVE";
+	else if (mode == 1)
+		fw_psmode_str = "LPS";
+	else if (mode == 2)
+		fw_psmode_str = "WMMPS";
+	else
+		fw_psmode_str = "UNSPECIFIED";
+
+	RTW_INFO(FUNC_ADPT_FMT": fw ps mode = %s, drv ps mode = %d, rlbm = %d , smart_ps = %d, allQueueUAPSD = %d\n", 
+				FUNC_ADPT_ARG(adapter), fw_psmode_str, psmode, rlbm, smart_ps, allQueueUAPSD);
+
+	SET_PWR_MODE_SET_CMD_ID(h2c, CMD_ID_SET_PWR_MODE);
+	SET_PWR_MODE_SET_CLASS(h2c, CLASS_SET_PWR_MODE);
+	SET_PWR_MODE_SET_MODE(h2c, mode);
+	SET_PWR_MODE_SET_SMART_PS(h2c, smart_ps);
+	SET_PWR_MODE_SET_RLBM(h2c, rlbm);
+	SET_PWR_MODE_SET_AWAKE_INTERVAL(h2c, awake_intvl);
+	SET_PWR_MODE_SET_B_ALL_QUEUE_UAPSD(h2c, allQueueUAPSD);
+	SET_PWR_MODE_SET_PWR_STATE(h2c, PowerState);
+	if (psmode == PS_MODE_ACTIVE) {
+		/* Leave LPS, set the same HW port ID */
+		SET_PWR_MODE_SET_PORT_ID(h2c, pwrpriv->current_lps_hw_port_id);
+	} else {
+		/* Enter LPS, record HW port ID */
+		SET_PWR_MODE_SET_PORT_ID(h2c, hw_port);
+		pwrpriv->current_lps_hw_port_id = hw_port;
+	}
+
+#ifdef CONFIG_BCN_RECV_TIME
+	if (pmlmeext->bcn_rx_time) {
+		bcn_recv_time = pmlmeext->bcn_rx_time / 128;
+		if (pmlmeext->bcn_rx_time % 128)
+			bcn_recv_time += 1;
+
+		if (bcn_recv_time >= 31)
+			bcn_recv_time = 31;
+		SET_PWR_MODE_SET_ADOPT_BCN_RECEIVING_TIME(h2c, 1);
+		SET_PWR_MODE_SET_BCN_RECEIVING_TIME(h2c, bcn_recv_time);
+	}
+#endif
+
+	RTW_INFO("%s=> psmode:%02x, smart_ps:%02x, PowerState:%02x\n", __func__, psmode, smart_ps, PowerState);
+
+#ifdef CONFIG_BT_COEXIST
+	rtw_btcoex_RecordPwrMode(adapter, h2c + 1, RTW_HALMAC_H2C_MAX_SIZE - 1);
+#endif /* CONFIG_BT_COEXIST */
+
+	RTW_DBG_DUMP("H2C-PwrMode Parm:", h2c, RTW_HALMAC_H2C_MAX_SIZE);
+	rtw_halmac_send_h2c(adapter_to_dvobj(adapter), h2c);
+}
+
+void rtl8821c_set_FwPwrModeInIPS_cmd(PADAPTER adapter, u8 cmd_param)
+{
+	u8 h2c[RTW_HALMAC_H2C_MAX_SIZE] = {0};
+
+	INACTIVE_PS_SET_CMD_ID(h2c, CMD_ID_INACTIVE_PS);
+	INACTIVE_PS_SET_CLASS(h2c, CLASS_INACTIVE_PS);
+
+	if (cmd_param & BIT0)
+		INACTIVE_PS_SET_ENABLE(h2c, 1);
+	if (cmd_param & BIT1)
+		INACTIVE_PS_SET_IGNORE_PS_CONDITION(h2c, 1);
+
+	RTW_DBG_DUMP("FW_IPS Parm:", h2c, RTW_HALMAC_H2C_MAX_SIZE);
+	rtw_halmac_send_h2c(adapter_to_dvobj(adapter), h2c);
+}
+
+#ifdef CONFIG_BT_COEXIST
+void rtl8821c_download_BTCoex_AP_mode_rsvd_page(PADAPTER adapter)
+{
+	rtl8821c_dl_rsvd_page(adapter, RT_MEDIA_CONNECT);
+}
+#endif /* CONFIG_BT_COEXIST */
+
+/*
+* Below functions are for C2H
+*/
+static void c2h_ccx_rpt(PADAPTER adapter, u8 *pdata)
+{
+#ifdef CONFIG_XMIT_ACK
+		u8 tx_state;
+
+		tx_state = CCX_RPT_GET_TX_STATE(pdata);
+
+		/* 0 means success, 1 means retry drop */
+		if (tx_state == 0)
+			rtw_ack_tx_done(&adapter->xmitpriv, RTW_SCTX_DONE_SUCCESS);
+		else
+			rtw_ack_tx_done(&adapter->xmitpriv, RTW_SCTX_DONE_CCX_PKT_FAIL);
+#endif /* CONFIG_XMIT_ACK */
+}
+#ifdef CONFIG_FW_HANDLE_TXBCN
+#define C2H_SUB_CMD_ID_FW_TBTT_RPT  0X23
+#define TBTT_RPT_GET_SN(c2h_pkt)	LE_BITS_TO_4BYTE(c2h_pkt + 0X01, 0, 8)
+#define TBTT_RPT_GET_PORT_ID(c2h_pkt)	LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 0, 8)
+
+#define TBTT_ROOT	0x00
+#define TBTT_VAP1	0x10
+#define TBTT_VAP2	0x20
+#define TBTT_VAP3	0x30
+
+static void c2h_tbtt_rpt(PADAPTER adapter, u8 *pdata)
+{
+	u8 ap_id, c2h_sn;
+
+	ap_id = TBTT_RPT_GET_PORT_ID(pdata);
+	c2h_sn = TBTT_RPT_GET_SN(pdata);
+#ifdef DBG_FW_TBTT_RPT
+	if (ap_id == TBTT_ROOT)
+		RTW_INFO("== TBTT ROOT SN:%d==\n", c2h_sn);
+	else if (ap_id == TBTT_VAP1)
+		RTW_INFO("== TBTT_VAP1 SN:%d==\n", c2h_sn);
+	else if (ap_id == TBTT_VAP2)
+		RTW_INFO("== TBTT_VAP2 SN:%d==\n", c2h_sn);
+	else if (ap_id == TBTT_VAP3)
+		RTW_INFO("== TBTT_VAP3 SN:%d==\n", c2h_sn);
+	else
+		RTW_ERR("TBTT RPT INFO ERROR\n");
+#endif
+}
+#endif
+
+/**
+* pbuf = RXDESC + c2h packet
+* length = RXDESC_SIZE + c2h packet size
+* c2h format => ID(1B) | SN(1B) | Payload
+* C2H - 0xFF format
+*	u8 CMD_ID
+*	u8 CMD_SEQ
+*	u8 SUB_CMD_ID
+*	u8 CMD_LEN
+*	u8 *pContent
+*/
+void c2h_handler_rtl8821c(PADAPTER adapter, u8 *pbuf, u16 length)
+{
+	u8 c2h_id, c2h_sn;
+	int c2h_len;
+	u8 *pc2h_hdr;
+	u8 *pc2h_data;
+	u8 c2h_sub_cmd_id = 0;
+	u32 desc_size = 0;
+#ifdef CONFIG_WOWLAN
+	struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(adapter);
+#endif /* CONFIG_WOWLAN*/
+
+	rtw_halmac_get_rx_desc_size(adapter_to_dvobj(adapter), &desc_size);
+
+#ifdef CONFIG_WOWLAN
+	if (pwrpriv->wowlan_mode == _TRUE) {
+		RTW_INFO("%s: return because wowolan_mode==TRUE! CMDID=%d\n",
+			 __FUNCTION__, C2H_GET_CMD_ID(pbuf + desc_size));
+		return;
+	}
+#endif /* CONFIG_WOWLAN*/
+	if (pbuf == NULL)
+		return;
+
+	if (length < desc_size) {
+		RTW_INFO("%s: [ERROR] c2h length(%d) is smaller than RXDESC_SIZE(%d)!!\n",
+			 __func__, length, desc_size);
+		return;
+	}
+
+	pc2h_hdr = pbuf + desc_size;
+	pc2h_data = pbuf + desc_size + 2; /* cmd ID not 0xFF original C2H have 2 bytes C2H header */
+	c2h_id = C2H_GET_CMD_ID(pc2h_hdr);
+	c2h_sn = C2H_GET_SEQ(pc2h_hdr);
+	c2h_len = length - desc_size - 2;
+
+	if ((c2h_len < 0) || (c2h_len > C2H_DBG_CONTENT_MAX_LENGTH)) {
+		RTW_ERR("%s: [ERROR] C2H_ID(%02x) C2H_SN(%d) warn c2h_len :%d (length:%d)\n", __func__, c2h_id, c2h_sn, c2h_len, length);
+		rtw_warn_on(1);
+	}
+#ifdef DBG_C2H_CONTENT
+	RTW_INFO("%s "ADPT_FMT" C2H, ID=%d seq=%d len=%d\n", __func__, ADPT_ARG(adapter), c2h_id, c2h_sn, length);
+#endif
+	switch (c2h_id) {
+	case CMD_ID_C2H_SND_TXBF:
+		/*C2HTxBeamformingHandler_8821C(adapter, pc2h_data, c2h_len);*/
+		break;
+
+	/* FW offload C2H is 0xFF cmd according to halmac function - halmac_parse_c2h_packet */
+	case 0xFF:
+		/* Get C2H sub cmd ID */
+		c2h_sub_cmd_id = (u8)C2H_HDR_GET_C2H_SUB_CMD_ID(pc2h_hdr);
+		if (c2h_sub_cmd_id == C2H_SUB_CMD_ID_CCX_RPT)
+			c2h_ccx_rpt(adapter, pbuf + desc_size);
+		#ifdef CONFIG_FW_HANDLE_TXBCN
+		else if (c2h_sub_cmd_id == C2H_SUB_CMD_ID_FW_TBTT_RPT)
+			c2h_tbtt_rpt(adapter, pbuf + desc_size);
+		#endif
+		else
+		/* indicate  rx desc + c2h pkt to halmac */
+			if (rtw_halmac_c2h_handle(adapter_to_dvobj(adapter), pbuf, length) == -1)
+				RTW_ERR("%s "ADPT_FMT" C2H, ID=%d, SubID=%d seq=%d len=%d ,HALMAC not to handle\n",
+					__func__, ADPT_ARG(adapter), c2h_id, c2h_sub_cmd_id, c2h_sn, length);
+		break;
+	/* others for c2h common code */
+	default:
+		/* shift 2 byte to remove cmd id & seq */
+		c2h_handler(adapter, c2h_id, c2h_sn, c2h_len, pc2h_data);
+		break;
+	}
+}
+
+
+static inline u8 is_c2h_id_handle_directly(u8 c2h_id, u8 c2h_sub_cmd_id)
+{
+	switch (c2h_id) {
+	case CMD_ID_C2H_CCX_RPT:
+	case C2H_IQK_FINISH:
+	case C2H_EXTEND:
+
+	#if defined(CONFIG_TDLS) && defined(CONFIG_TDLS_CH_SW)
+	case C2H_BCN_EARLY_RPT:
+	case C2H_FW_CHNL_SWITCH_COMPLETE:
+	#endif
+
+	#ifdef CONFIG_BT_COEXIST
+	case C2H_BT_MP_INFO:
+	#endif
+
+	#ifdef CONFIG_MCC_MODE
+	case C2H_MCC:
+	#endif
+		return _TRUE;
+	default:
+		return _FALSE;
+	}
+
+}
+
+/*
+* pbuf = RXDESC + c2h packet
+* length = RXDESC_SIZE + c2h packet size
+*/
+void c2h_pre_handler_rtl8821c(_adapter *adapter, u8 *pbuf, s32 length)
+{
+	u8 c2h_id;
+	u8 c2h_sub_cmd_id = 0;
+	u32 desc_size = 0;
+
+	if ((length <= 0) || (!pbuf))
+		return;
+
+	rtw_halmac_get_rx_desc_size(adapter_to_dvobj(adapter), &desc_size);
+
+	c2h_id = C2H_GET_CMD_ID(pbuf + desc_size);
+
+	/* Get C2H sub cmd ID */
+	if (c2h_id == 0xFF)
+		c2h_sub_cmd_id = (u8)C2H_HDR_GET_C2H_SUB_CMD_ID(pbuf + desc_size);
+
+	if (is_c2h_id_handle_directly(c2h_id, c2h_sub_cmd_id))
+		c2h_handler_rtl8821c(adapter, pbuf, length);
+	else
+		rtw_c2h_packet_wk_cmd(adapter, pbuf, length);
+}
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/rtl8821c/rtl8821c_dm.c linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/rtl8821c/rtl8821c_dm.c
--- linux-5.6.3/3rdparty/rtl8821ce/hal/rtl8821c/rtl8821c_dm.c	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/rtl8821c/rtl8821c_dm.c	2020-04-10 16:35:06.843661328 +0300
@@ -0,0 +1,264 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2016 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+/* ************************************************************
+ * Description:
+ *
+ * This file is for 8821C dynamic mechanism
+ *
+ *
+ * ************************************************************ */
+#define _RTL8812C_DM_C_
+
+/* ************************************************************
+ * include files
+ * ************************************************************
+ */
+
+#include <drv_types.h>
+#include <rtl8821c_hal.h>
+
+/* ************************************************************
+ * Global var
+ * ************************************************************ */
+static void dm_CheckProtection(PADAPTER adapter)
+{
+}
+	
+	
+#ifdef CONFIG_SUPPORT_HW_WPS_PBC
+static void dm_CheckPbcGPIO(PADAPTER adapter)
+{
+	u8 tmp1byte;
+	u8 bPbcPressed = _FALSE;
+
+	if (!adapter->registrypriv.hw_wps_pbc)
+		return;
+	
+#ifdef CONFIG_USB_HCI
+	tmp1byte = rtw_read8(adapter, GPIO_IO_SEL);
+	tmp1byte |= (HAL_8192C_HW_GPIO_WPS_BIT);
+	rtw_write8(adapter, GPIO_IO_SEL, tmp1byte); /* enable GPIO[2] as output mode */
+
+	tmp1byte &= ~(HAL_8192C_HW_GPIO_WPS_BIT);
+	rtw_write8(adapter, GPIO_IN, tmp1byte); /* reset the floating voltage level */
+
+	tmp1byte = rtw_read8(adapter, GPIO_IO_SEL);
+	tmp1byte &= ~(HAL_8192C_HW_GPIO_WPS_BIT);
+	rtw_write8(adapter, GPIO_IO_SEL, tmp1byte); /* enable GPIO[2] as input mode */
+
+	tmp1byte = rtw_read8(adapter, GPIO_IN);
+	if (tmp1byte == 0xff)
+		return;
+	
+	if (tmp1byte & HAL_8192C_HW_GPIO_WPS_BIT)
+		bPbcPressed = _TRUE;
+#else
+	tmp1byte = rtw_read8(adapter, GPIO_IN);
+	
+	if ((tmp1byte == 0xff) || adapter->init_adpt_in_progress)
+		return;
+	
+	if ((tmp1byte & HAL_8192C_HW_GPIO_WPS_BIT) == 0)
+		bPbcPressed = _TRUE;
+#endif
+	
+	if (_TRUE == bPbcPressed) {
+	/*
+	 * Here we only set bPbcPressed to true
+	 * After trigger PBC, the variable will be set to false
+	 */
+		RTW_INFO("CheckPbcGPIO - PBC is pressed\n");
+			rtw_request_wps_pbc_event(adapter);
+	}
+}
+#endif /* CONFIG_SUPPORT_HW_WPS_PBC */
+	
+	
+#ifdef CONFIG_PCI_HCI
+/*
+ * Description:
+ *	Perform interrupt migration dynamically to reduce CPU utilization.
+ *
+ * Assumption:
+ *	1. Do not enable migration under WIFI test.
+ */
+void dm_InterruptMigration(PADAPTER adapter)
+{
+	PHAL_DATA_TYPE hal = GET_HAL_DATA(adapter);
+	struct mlme_priv *pmlmepriv = &adapter->mlmepriv;
+	BOOLEAN bCurrentIntMt, bCurrentACIntDisable;
+	BOOLEAN IntMtToSet = _FALSE;
+	BOOLEAN ACIntToSet = _FALSE;
+
+
+	/* Retrieve current interrupt migration and Tx four ACs IMR settings first. */
+	bCurrentIntMt = hal->bInterruptMigration;
+	bCurrentACIntDisable = hal->bDisableTxInt;
+
+	/*
+	 * <Roger_Notes> Currently we use busy traffic for reference instead of RxIntOK counts to prevent non-linear Rx statistics
+	 * when interrupt migration is set before. 2010.03.05.
+	 */
+	if (!adapter->registrypriv.wifi_spec
+		&& (check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE)
+		&& pmlmepriv->LinkDetectInfo.bHigherBusyTraffic) {
+		IntMtToSet = _TRUE;
+
+		/* To check whether we should disable Tx interrupt or not. */
+		if (pmlmepriv->LinkDetectInfo.bHigherBusyRxTraffic)
+			ACIntToSet = _TRUE;
+	}
+
+	/* Update current settings. */
+	if (bCurrentIntMt != IntMtToSet) {
+		RTW_INFO("%s: Update interrrupt migration(%d)\n", __FUNCTION__, IntMtToSet);
+		if (IntMtToSet) {
+			/*
+			 * <Roger_Notes> Set interrrupt migration timer and corresponging Tx/Rx counter.
+			 * timer 25ns*0xfa0=100us for 0xf packets.
+			 * 2010.03.05.
+			 */
+			rtw_write32(adapter, REG_INT_MIG, 0xff000fa0); /* 0x306:Rx, 0x307:Tx */
+			hal->bInterruptMigration = IntMtToSet;
+		} else {
+			/* Reset all interrupt migration settings. */
+			rtw_write32(adapter, REG_INT_MIG, 0);
+			hal->bInterruptMigration = IntMtToSet;
+		}
+	}
+}
+#endif /* CONFIG_PCI_HCI */
+	
+/*
+ * ============================================================
+ * functions
+ * ============================================================
+ */
+static void init_phydm_cominfo(PADAPTER adapter)
+{
+	PHAL_DATA_TYPE hal = GET_HAL_DATA(adapter);
+	struct dm_struct *pDM_Odm = &hal->odmpriv;
+	u8 cut_ver = ODM_CUT_A, fab_ver = ODM_TSMC;
+
+	Init_ODM_ComInfo(adapter);
+
+	odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_PACKAGE_TYPE, hal->PackageType);
+
+	if (IS_CHIP_VENDOR_TSMC(hal->version_id))
+		fab_ver = ODM_TSMC;
+	else if (IS_CHIP_VENDOR_UMC(hal->version_id))
+		fab_ver = ODM_UMC;
+	else if (IS_CHIP_VENDOR_SMIC(hal->version_id))
+		fab_ver = ODM_UMC + 1;
+	else
+		RTW_INFO("%s: unknown fab_ver=%d !!\n",
+			 __FUNCTION__, GET_CVID_MANUFACTUER(hal->version_id));
+
+	if (IS_A_CUT(hal->version_id))
+		cut_ver = ODM_CUT_A;
+	else if (IS_B_CUT(hal->version_id))
+		cut_ver = ODM_CUT_B;
+	else if (IS_C_CUT(hal->version_id))
+		cut_ver = ODM_CUT_C;
+	else if (IS_D_CUT(hal->version_id))
+		cut_ver = ODM_CUT_D;
+	else if (IS_E_CUT(hal->version_id))
+		cut_ver = ODM_CUT_E;
+	else if (IS_F_CUT(hal->version_id))
+		cut_ver = ODM_CUT_F;
+	else if (IS_I_CUT(hal->version_id))
+		cut_ver = ODM_CUT_I;
+	else if (IS_J_CUT(hal->version_id))
+		cut_ver = ODM_CUT_J;
+	else if (IS_K_CUT(hal->version_id))
+		cut_ver = ODM_CUT_K;
+	else
+		RTW_INFO("%s: unknown cut_ver=%d !!\n",
+			 __FUNCTION__, GET_CVID_CUT_VERSION(hal->version_id));
+
+	RTW_INFO("%s: fab_ver=%d cut_ver=%d\n", __FUNCTION__, fab_ver, cut_ver);
+	odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_FAB_VER, fab_ver);
+	odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_CUT_VER, cut_ver);
+
+}
+	
+void rtl8821c_phy_init_dm_priv(PADAPTER adapter)
+{
+	struct dm_struct *phydm = adapter_to_phydm(adapter);
+
+	init_phydm_cominfo(adapter);
+	odm_init_all_timers(phydm);
+}
+	
+void rtl8821c_phy_deinit_dm_priv(PADAPTER adapter)
+{
+	struct dm_struct *phydm = adapter_to_phydm(adapter);
+
+	odm_cancel_all_timers(phydm);
+}
+
+void rtl8821c_phy_init_haldm(PADAPTER adapter)
+{
+	rtw_phydm_init(adapter);
+}
+
+void rtl8821c_phy_haldm_watchdog(PADAPTER Adapter)
+{
+	BOOLEAN bFwCurrentInPSMode = _FALSE;
+	u8 bFwPSAwake = _TRUE;
+
+	if (!rtw_is_hw_init_completed(Adapter))
+		goto skip_dm;
+
+#ifdef CONFIG_LPS
+	bFwCurrentInPSMode = adapter_to_pwrctl(Adapter)->bFwCurrentInPSMode;
+	rtw_hal_get_hwreg(Adapter, HW_VAR_FWLPS_RF_ON, &bFwPSAwake);
+#endif
+
+#ifdef CONFIG_P2P_PS
+	/* Fw is under p2p powersaving mode, driver should stop dynamic mechanism.
+	 modifed by thomas. 2011.06.11.*/
+	if (Adapter->wdinfo.p2p_ps_mode)
+		bFwPSAwake = _FALSE;
+#endif /*CONFIG_P2P_PS*/
+
+	if ((rtw_is_hw_init_completed(Adapter))
+		&& ((!bFwCurrentInPSMode) && bFwPSAwake)) {
+
+		/* Dynamically switch RTS/CTS protection.*/
+		/*dm_CheckProtection(Adapter);*/
+	}
+
+#ifdef CONFIG_DISABLE_ODM
+	goto skip_dm;
+#endif
+	rtw_phydm_watchdog(Adapter);
+
+skip_dm:
+
+#ifdef CONFIG_BEAMFORMING
+#ifdef RTW_BEAMFORMING_VERSION_2
+	if (check_fwstate(&Adapter->mlmepriv, WIFI_STATION_STATE) &&
+			check_fwstate(&Adapter->mlmepriv, _FW_LINKED))
+		rtw_hal_beamforming_config_csirate(Adapter);
+#endif
+#endif
+#ifdef CONFIG_SUPPORT_HW_WPS_PBC
+	/* Check GPIO to determine current Pbc status.*/
+	dm_CheckPbcGPIO(Adapter);
+#endif
+	return;
+}
+
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/rtl8821c/rtl8821c.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/rtl8821c/rtl8821c.h
--- linux-5.6.3/3rdparty/rtl8821ce/hal/rtl8821c/rtl8821c.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/rtl8821c/rtl8821c.h	2020-04-10 16:35:06.843661328 +0300
@@ -0,0 +1,116 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2016 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#ifndef _RTL8821C_H_
+#define _RTL8821C_H_
+
+#include <drv_types.h>		/* PADAPTER */
+#include <rtw_rf.h>		/* CHANNEL_WIDTH */
+#include <rtw_xmit.h>		/* struct pkt_attrib, struct xmit_frame */
+#include <rtw_recv.h>		/* struct recv_frame */
+#include <hal_intf.h>		/* HAL_DEF_VARIABLE */
+#include <rtl8821c_dm.h>
+
+#define DRIVER_EARLY_INT_TIME_8821C	0x05
+#define BCN_DMA_ATIME_INT_TIME_8821C	0x02
+
+/* rtl8821c_halinit.c */
+u32 rtl8821c_power_on(PADAPTER);
+void rtl8821c_power_off(PADAPTER);
+u8 rtl8821c_mac_init(PADAPTER);
+u8 rtl8821c_mac_verify(PADAPTER);
+void rtl8821c_hal_init_channel_setting(PADAPTER adapter);
+void rtl8821c_hal_init_misc(PADAPTER padapter);
+u32 rtl8821c_hal_init(PADAPTER);
+u32 rtl8821c_hal_deinit(PADAPTER);
+void rtl8821c_init_default_value(PADAPTER);
+u8 rtl8821c_phy_init(PADAPTER adapter);
+u8 rtl8821c_init_phy_parameter_mac(PADAPTER adapter);
+
+/* rtl8821c_mac.c */
+#ifdef CONFIG_XMIT_ACK
+u8 rtl8821c_set_mgnt_xmit_ack(_adapter *adapter);
+#endif
+u8 rtl8821c_rx_ba_ssn_appended(PADAPTER);
+u8 rtl8821c_rx_fcs_append_switch(PADAPTER, u8 enable);
+u8 rtl8821c_rx_fcs_appended(PADAPTER);
+u8 rtl8821c_rx_tsf_addr_filter_config(_adapter *adapter, u8 config);
+s32 rtl8821c_fw_dl(PADAPTER, u8 wowlan);
+s32 rtl8821c_fw_mem_dl(PADAPTER adapter, enum fw_mem mem);
+
+#define BIT_PRETXERR_HANDLE_IMR	BIT(31)
+#define BIT_PRETXERR_HANDLE_ISR	BIT(31)
+
+#ifdef CONFIG_AMPDU_PRETX_CD
+#define BIT_PRETXERR			BIT(7)
+
+void rtl8821c_pretx_cd_config(_adapter *adapter);
+#endif
+/* rtl8821c_ops.c */
+u8 rtl8821c_read_efuse(PADAPTER);
+void rtl8821c_run_thread(PADAPTER);
+void rtl8821c_cancel_thread(PADAPTER);
+u8 rtl8821c_sethwreg(PADAPTER, u8 variable, u8 *pval);
+void rtl8821c_gethwreg(PADAPTER, u8 variable, u8 *pval);
+u8 rtl8821c_sethaldefvar(PADAPTER, HAL_DEF_VARIABLE, void *pval);
+u8 rtl8821c_gethaldefvar(PADAPTER, HAL_DEF_VARIABLE, void *pval);
+void rtl8821c_set_hal_ops(PADAPTER);
+
+/* tx */
+void rtl8821c_init_xmit_priv(_adapter *adapter);
+void rtl8821c_fill_txdesc_sectype(struct pkt_attrib *, u8 *ptxdesc);
+void rtl8821c_fill_txdesc_vcs(PADAPTER, struct pkt_attrib *, u8 *ptxdesc);
+void rtl8821c_fill_txdesc_phy(PADAPTER, struct pkt_attrib *, u8 *ptxdesc);
+u8 rtl8821c_bw_mapping(PADAPTER, struct pkt_attrib *);
+u8 rtl8821c_sc_mapping(PADAPTER, struct pkt_attrib *);
+void rtl8821c_cal_txdesc_chksum(PADAPTER, u8 *ptxdesc);
+void rtl8821c_update_txdesc(struct xmit_frame *, u8 *pbuf);
+void rtl8821c_dbg_dump_tx_desc(PADAPTER, int frame_tag, u8 *ptxdesc);
+#if defined(CONFIG_CONCURRENT_MODE)
+void fill_txdesc_force_bmc_camid(struct pkt_attrib *pattrib, u8 *ptxdesc);
+#endif
+void fill_txdesc_bmc_tx_rate(struct pkt_attrib *pattrib, u8 *ptxdesc);
+
+/* rx */
+void rtl8821c_rxdesc2attribute(struct rx_pkt_attrib *a, u8 *desc);
+void rtl8821c_query_rx_desc(union recv_frame *, u8 *pdesc);
+
+/* rtl8821c_cmd.c */
+s32 rtl8821c_fillh2ccmd(PADAPTER, u8 id, u32 buf_len, u8 *pbuf);
+void rtl8821c_set_FwPwrMode_cmd(PADAPTER, u8 psmode);
+void rtl8821c_set_FwPwrModeInIPS_cmd(PADAPTER adapter, u8 cmd_param);
+void c2h_handler_rtl8821c(_adapter *adapter, u8 *pbuf, u16 length);
+void c2h_pre_handler_rtl8821c(_adapter *adapter, u8 *pbuf, s32 length);
+#ifdef CONFIG_BT_COEXIST
+void rtl8821c_download_BTCoex_AP_mode_rsvd_page(PADAPTER);
+#endif /* CONFIG_BT_COEXIST */
+
+/* rtl8821c_phy.c */
+u32 rtl8821c_read_bb_reg(PADAPTER, u32 addr, u32 mask);
+void rtl8821c_write_bb_reg(PADAPTER, u32 addr, u32 mask, u32 val);
+u32 rtl8821c_read_rf_reg(PADAPTER adapter, enum rf_path path, u32 addr, u32 mask);
+void rtl8821c_write_rf_reg(PADAPTER adapter, enum rf_path path, u32 addr, u32 mask, u32 val);
+void rtl8821c_set_channel_bw(PADAPTER adapter, u8 center_ch, enum channel_width, u8 offset40, u8 offset80);
+void rtl8821c_set_tx_power_level(PADAPTER, u8 channel);
+void rtl8821c_get_tx_power_level(PADAPTER, s32 *power);
+void rtl8821c_set_tx_power_index(PADAPTER adapter, u32 powerindex, enum rf_path rfpath, u8 rate);
+u8 rtl8821c_get_tx_power_index(PADAPTER adapter, enum rf_path rfpath, u8 rate, u8 bandwidth, u8 channel, struct txpwr_idx_comp *tic);
+void rtl8821c_notch_filter_switch(PADAPTER, bool enable);
+#ifdef CONFIG_BEAMFORMING
+void rtl8821c_phy_bf_init(PADAPTER);
+void rtl8821c_phy_bf_enter(PADAPTER, struct sta_info*);
+void rtl8821c_phy_bf_leave(PADAPTER, u8 *addr);
+void rtl8821c_phy_bf_set_gid_table(PADAPTER, struct beamformer_entry*);
+#endif /* CONFIG_BEAMFORMING */
+#endif /* _RTL8821C_H_ */
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/rtl8821c/rtl8821c_halinit.c linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/rtl8821c/rtl8821c_halinit.c
--- linux-5.6.3/3rdparty/rtl8821ce/hal/rtl8821c/rtl8821c_halinit.c	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/rtl8821c/rtl8821c_halinit.c	2020-04-10 16:35:06.843661328 +0300
@@ -0,0 +1,354 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2016 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#define _RTL8821C_HALINIT_C_
+
+#include <drv_types.h>		/* PADAPTER, basic_types.h and etc. */
+#include <hal_data.h>		/* GET_HAL_SPEC(), HAL_DATA_TYPE */
+#include "../hal_halmac.h"	/* HALMAC API */
+#include "rtl8821c.h"
+
+void init_hal_spec_rtl8821c(PADAPTER adapter)
+{
+	struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter);
+
+	rtw_halmac_fill_hal_spec(adapter_to_dvobj(adapter), hal_spec);
+
+	hal_spec->ic_name = "rtl8821c";
+	hal_spec->macid_num = 128;
+	/* hal_spec->sec_cam_ent_num follow halmac setting */
+	hal_spec->sec_cap = SEC_CAP_CHK_BMC;
+
+	hal_spec->rfpath_num_2g = 2;
+	hal_spec->rfpath_num_5g = 1;
+	hal_spec->txgi_max = 63;
+	hal_spec->txgi_pdbm = 2;
+	hal_spec->max_tx_cnt = 1;
+	hal_spec->tx_nss_num = 1;
+	hal_spec->rx_nss_num = 1;
+	hal_spec->band_cap = BAND_CAP_2G | BAND_CAP_5G;
+	hal_spec->bw_cap = BW_CAP_20M | BW_CAP_40M | BW_CAP_80M;
+	hal_spec->port_num = 5;
+	hal_spec->hci_type = 0;
+	hal_spec->proto_cap = PROTO_CAP_11B | PROTO_CAP_11G | PROTO_CAP_11N | PROTO_CAP_11AC;
+
+	hal_spec->wl_func = 0
+			    | WL_FUNC_P2P
+			    | WL_FUNC_MIRACAST
+			    | WL_FUNC_TDLS
+			    ;
+
+	hal_spec->rx_tsf_filter = 1;
+
+	hal_spec->pg_txpwr_saddr = 0x10;
+	hal_spec->pg_txgi_diff_factor = 1;
+
+	rtw_macid_ctl_init_sleep_reg(adapter_to_macidctl(adapter)
+		, REG_MACID_SLEEP_8821C
+		, REG_MACID_SLEEP1_8821C
+		, REG_MACID_SLEEP2_8821C
+		, REG_MACID_SLEEP3_8821C);
+}
+
+u32 rtl8821c_power_on(PADAPTER adapter)
+{
+	struct dvobj_priv *d;
+	PHAL_DATA_TYPE hal;
+	u8 bMacPwrCtrlOn;
+	int err = 0;
+	u8 ret = _SUCCESS;
+
+
+	d = adapter_to_dvobj(adapter);
+
+	bMacPwrCtrlOn = _FALSE;
+	rtw_hal_get_hwreg(adapter, HW_VAR_APFM_ON_MAC, &bMacPwrCtrlOn);
+	if (bMacPwrCtrlOn == _TRUE)
+		goto out;
+
+	err = rtw_halmac_poweron(d);
+
+	#ifdef CONFIG_POWER_STATE_UNEXPECTED_HDL
+	if ((-2) == err) {
+		RTW_ERR("%s:Power ON Fail, Try to power on again !!\n", __FUNCTION__);
+		rtw_halmac_poweroff(d);
+		rtw_msleep_os(2);
+		err = rtw_halmac_poweron(d);
+	}
+	#endif
+
+	if (err) {
+		RTW_ERR("%s: Power ON Fail!!\n", __FUNCTION__);
+		rtw_warn_on(1);
+		ret = _FAIL;
+		goto out;
+	}
+
+	bMacPwrCtrlOn = _TRUE;
+	rtw_hal_set_hwreg(adapter, HW_VAR_APFM_ON_MAC, &bMacPwrCtrlOn);
+
+out:
+	return ret;
+}
+
+void rtl8821c_power_off(PADAPTER adapter)
+{
+	struct dvobj_priv *d;
+	u8 bMacPwrCtrlOn;
+	int err = 0;
+
+
+	d = adapter_to_dvobj(adapter);
+
+	bMacPwrCtrlOn = _FALSE;
+	rtw_hal_get_hwreg(adapter, HW_VAR_APFM_ON_MAC, &bMacPwrCtrlOn);
+	if (bMacPwrCtrlOn == _FALSE)
+		goto out;
+
+	err = rtw_halmac_poweroff(d);
+	if (err) {
+		RTW_ERR("%s: Power OFF Fail!!\n", __FUNCTION__);
+		rtw_warn_on(1);
+		goto out;
+	}
+
+	bMacPwrCtrlOn = _FALSE;
+	rtw_hal_set_hwreg(adapter, HW_VAR_APFM_ON_MAC, &bMacPwrCtrlOn);
+
+	GET_HAL_DATA(adapter)->bFWReady = _FALSE;
+
+out:
+	return;
+}
+
+u8 rtl8821c_hal_init_main(PADAPTER adapter)
+{
+	struct dvobj_priv *d = adapter_to_dvobj(adapter);
+	PHAL_DATA_TYPE hal = GET_HAL_DATA(adapter);
+	int err;
+	s32 ret;
+
+	hal->bFWReady = _FALSE;
+	hal->fw_ractrl = _FALSE;
+
+#ifdef CONFIG_NO_FW
+	err = rtw_halmac_init_hal(d);
+#else
+	#ifdef CONFIG_FILE_FWIMG
+	rtw_get_phy_file_path(adapter, MAC_FILE_FW_NIC);
+	err = rtw_halmac_init_hal_fw_file(d, rtw_phy_para_file_path);
+	#else
+	err = rtw_halmac_init_hal_fw(d, array_mp_8821c_fw_nic, array_length_mp_8821c_fw_nic);
+	#endif
+
+	if (!err) {
+		hal->bFWReady = _TRUE;
+		hal->fw_ractrl = _TRUE;
+	}
+	RTW_INFO("FW Version:%d SubVersion:%d\n", hal->firmware_version, hal->firmware_sub_version);
+#endif
+	if (err) {
+		RTW_INFO("%s: fail\n", __FUNCTION__);
+		return _FALSE;
+	}
+
+	RTW_INFO("%s: successful\n", __FUNCTION__);
+
+	return _TRUE;
+}
+
+u8 rtl8821c_mac_verify(PADAPTER adapter)
+{
+	struct dvobj_priv *d;
+	int err;
+
+
+	d = adapter_to_dvobj(adapter);
+
+	err = rtw_halmac_self_verify(d);
+	if (err) {
+		RTW_INFO("%s fail\n", __FUNCTION__);
+		return _FALSE;
+	}
+
+	RTW_INFO("%s successful\n", __FUNCTION__);
+	return _TRUE;
+}
+
+void rtl8821c_hal_init_channel_setting(PADAPTER adapter)
+{
+	PHAL_DATA_TYPE hal_data = GET_HAL_DATA(adapter);
+
+	/* initial channel setting */
+	hal_data->current_channel = 0;
+	hal_data->current_channel_bw = CHANNEL_WIDTH_MAX;
+	hal_data->current_band_type = BAND_MAX;
+}
+
+void rtl8821c_hal_init_misc(PADAPTER adapter)
+{
+	PHAL_DATA_TYPE hal_data = GET_HAL_DATA(adapter);
+	u8 drv_info_sz = 0;
+	u32	rcr_bits;
+	/*
+	 * Sync driver status and hardware setting
+	 */
+
+	/* initial security setting */
+	invalidate_cam_all(adapter);
+
+	/* enable to rx ps-poll ,disable Control frame filter*/
+	rtw_write16(adapter, REG_RXFLTMAP1_8821C, 0x0400);
+	/* Accept all data frames */
+	rtw_write16(adapter, REG_RXFLTMAP2_8821C, 0xFFFF);
+
+	/* Accept all management frames */
+	rtw_write16(adapter, REG_RXFLTMAP0_8821C, 0xFFFF);
+
+	/*RCR setting - Sync driver status with hardware setting */
+	rtw_hal_get_hwreg(adapter, HW_VAR_RCR, (u8 *)&rcr_bits);
+
+	rcr_bits &= ~(BIT_AICV_8821C | BIT_ACRC32_8821C | BIT_APP_FCS_8821C | BIT_APWRMGT_8821C);
+
+	rtw_halmac_get_rx_drv_info_sz(adapter_to_dvobj(adapter), &drv_info_sz);
+	if (drv_info_sz)
+		rcr_bits |= BIT_APP_PHYSTS_8821C;
+
+#ifdef CONFIG_RX_PACKET_APPEND_FCS
+	rcr_bits |= BIT_APP_FCS_8821C;
+#endif
+
+#ifdef CONFIG_RX_PACKET_APPEND_ICV_ERROR
+	rcr_bits |= BIT_AICV_8821C;
+#endif
+
+	rtw_hal_set_hwreg(adapter, HW_VAR_RCR, (u8 *)&rcr_bits);
+
+#ifdef CONFIG_XMIT_ACK
+	rtl8821c_set_mgnt_xmit_ack(adapter);
+#endif /*CONFIG_XMIT_ACK*/
+
+	/*Disable BAR, suggested by Scott */
+	rtw_write32(adapter, REG_BAR_MODE_CTRL_8821C, 0x0201ffff);
+	/*Disable secondary CCA 20M,40M?*/
+	rtw_write8(adapter, REG_MISC_CTRL_8821C, 0x03);
+
+	/*Enable MAC security engine*/
+	rtw_write16(adapter, REG_CR, (rtw_read16(adapter, REG_CR) | BIT_MAC_SEC_EN));
+
+	rtl8821c_rx_tsf_addr_filter_config(adapter, BIT_CHK_TSF_EN_8821C | BIT_CHK_TSF_CBSSID_8821C);
+
+	/*for 1212 module - 5G RX issue*/
+	if (hal_data->rfe_type == 2)
+		rtw_write8(adapter, REG_PAD_CTRL1 + 3, 0x36);
+#ifdef CONFIG_AMPDU_PRETX_CD
+	rtl8821c_pretx_cd_config(adapter);
+#endif
+}
+
+u32 rtl8821c_hal_init(PADAPTER adapter)
+{
+	PHAL_DATA_TYPE hal;
+
+	hal = GET_HAL_DATA(adapter);
+
+	if (_FALSE == rtl8821c_hal_init_main(adapter))
+		return _FAIL;
+
+	rtl8821c_hal_init_misc(adapter);
+
+	rtl8821c_phy_init_haldm(adapter);
+#ifdef CONFIG_BEAMFORMING
+	rtl8821c_phy_bf_init(adapter);
+#endif
+
+#ifdef CONFIG_FW_MULTI_PORT_SUPPORT
+	/*HW / FW init*/
+	rtw_hal_set_default_port_id_cmd(adapter, 0);
+#endif
+
+#ifdef CONFIG_BT_COEXIST
+	/* Init BT hw config. */
+	if (_TRUE == hal->EEPROMBluetoothCoexist) {
+		rtw_btcoex_HAL_Initialize(adapter, _FALSE);
+		#ifdef CONFIG_FW_MULTI_PORT_SUPPORT
+		rtw_hal_set_wifi_btc_port_id_cmd(adapter);
+		#endif
+	} else
+#endif /* CONFIG_BT_COEXIST */
+		rtw_btcoex_wifionly_hw_config(adapter);
+
+	rtl8821c_hal_init_channel_setting(adapter);
+
+	return _SUCCESS;
+}
+
+u32 rtl8821c_hal_deinit(PADAPTER adapter)
+{
+	struct dvobj_priv *d;
+	PHAL_DATA_TYPE hal;
+	int err;
+
+
+	d = adapter_to_dvobj(adapter);
+	hal = GET_HAL_DATA(adapter);
+
+	hal->bFWReady = _FALSE;
+	hal->fw_ractrl = _FALSE;
+
+	err = rtw_halmac_deinit_hal(d);
+	if (err)
+		return _FAIL;
+
+	return _SUCCESS;
+}
+
+void rtl8821c_init_default_value(PADAPTER adapter)
+{
+	PHAL_DATA_TYPE hal;
+	u8 i;
+
+
+	hal = GET_HAL_DATA(adapter);
+
+
+	/* init default value */
+	hal->fw_ractrl = _FALSE;
+
+	if (!adapter_to_pwrctl(adapter)->bkeepfwalive)
+		hal->LastHMEBoxNum = 0;
+
+	/* init phydm default value */
+	hal->bIQKInitialized = _FALSE;
+
+	/* init Efuse variables */
+	hal->EfuseUsedBytes = 0;
+	hal->EfuseUsedPercentage = 0;
+#ifdef HAL_EFUSE_MEMORY
+	hal->EfuseHal.fakeEfuseBank = 0;
+	hal->EfuseHal.fakeEfuseUsedBytes = 0;
+	_rtw_memset(hal->EfuseHal.fakeEfuseContent, 0xFF, EFUSE_MAX_HW_SIZE);
+	_rtw_memset(hal->EfuseHal.fakeEfuseInitMap, 0xFF, EFUSE_MAX_MAP_LEN);
+	_rtw_memset(hal->EfuseHal.fakeEfuseModifiedMap, 0xFF, EFUSE_MAX_MAP_LEN);
+	hal->EfuseHal.BTEfuseUsedBytes = 0;
+	hal->EfuseHal.BTEfuseUsedPercentage = 0;
+	_rtw_memset(hal->EfuseHal.BTEfuseContent, 0xFF, EFUSE_MAX_BT_BANK * EFUSE_MAX_HW_SIZE);
+	_rtw_memset(hal->EfuseHal.BTEfuseInitMap, 0xFF, EFUSE_BT_MAX_MAP_LEN);
+	_rtw_memset(hal->EfuseHal.BTEfuseModifiedMap, 0xFF, EFUSE_BT_MAX_MAP_LEN);
+	hal->EfuseHal.fakeBTEfuseUsedBytes = 0;
+	_rtw_memset(hal->EfuseHal.fakeBTEfuseContent, 0xFF, EFUSE_MAX_BT_BANK * EFUSE_MAX_HW_SIZE);
+	_rtw_memset(hal->EfuseHal.fakeBTEfuseInitMap, 0xFF, EFUSE_BT_MAX_MAP_LEN);
+	_rtw_memset(hal->EfuseHal.fakeBTEfuseModifiedMap, 0xFF, EFUSE_BT_MAX_MAP_LEN);
+#endif
+}
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/rtl8821c/rtl8821c_mac.c linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/rtl8821c/rtl8821c_mac.c
--- linux-5.6.3/3rdparty/rtl8821ce/hal/rtl8821c/rtl8821c_mac.c	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/rtl8821c/rtl8821c_mac.c	2020-04-10 16:35:06.843661328 +0300
@@ -0,0 +1,182 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2016 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#define _RTL8821C_MAC_C_
+
+#include <drv_types.h>		/* PADAPTER, basic_types.h and etc. */
+#include <hal_data.h>		/* HAL_DATA_TYPE */
+#include "../hal_halmac.h"	/* Register Definition and etc. */
+
+#ifdef CONFIG_XMIT_ACK
+inline u8 rtl8821c_set_mgnt_xmit_ack(_adapter *adapter)
+{
+	int err;
+
+	/*ack for xmit mgmt frames.*/
+	err = rtw_write32(adapter, REG_FWHW_TXQ_CTRL_8821C, rtw_read32(adapter, REG_FWHW_TXQ_CTRL_8821C) | BIT(12));
+	if (err == _FAIL)
+		return _FAIL;
+
+	return _SUCCESS;
+}
+#endif
+
+inline u8 rtl8821c_rx_ba_ssn_appended(PADAPTER p)
+{
+	return rtw_hal_rcr_check(p, BIT_APP_BASSN_8821C);
+}
+
+inline u8 rtl8821c_rx_fcs_append_switch(PADAPTER p, u8 enable)
+{
+	u32 rcr_bit;
+	u8 ret = _TRUE;
+
+	rcr_bit = BIT_APP_FCS_8821C;
+	if (_TRUE == enable)
+		ret = rtw_hal_rcr_add(p, rcr_bit);
+	else
+		ret = rtw_hal_rcr_clear(p, rcr_bit);
+
+	return ret;
+}
+
+inline u8 rtl8821c_rx_fcs_appended(PADAPTER p)
+{
+	return rtw_hal_rcr_check(p, BIT_APP_FCS_8821C);
+}
+
+u8 rtl8821c_rx_tsf_addr_filter_config(_adapter *adapter, u8 config)
+{
+	u8 v8;
+	int err;
+
+	v8 = GET_HAL_DATA(adapter)->rx_tsf_addr_filter_config;
+
+	if (v8 != config) {
+
+		err = rtw_write8(adapter, REG_NAN_RX_TSF_FILTER_8821C, config);
+		if (_FAIL == err)
+			return _FALSE;
+	}
+
+	GET_HAL_DATA(adapter)->rx_tsf_addr_filter_config = config;
+	return _TRUE;
+}
+
+/*
+ * Return:
+ *	_SUCCESS	Download Firmware OK.
+ *	_FAIL		Download Firmware FAIL!
+ */
+s32 rtl8821c_fw_dl(PADAPTER adapter, u8 wowlan)
+{
+	struct dvobj_priv *d = adapter_to_dvobj(adapter);
+	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
+	int err;
+	u8 fw_bin = _TRUE;
+
+#ifdef CONFIG_FILE_FWIMG
+	fw_bin = _TRUE;
+	if (_TRUE == wowlan) {
+		rtw_get_phy_file_path(adapter, MAC_FILE_FW_WW_IMG);
+		err = rtw_halmac_dlfw_from_file(d, rtw_phy_para_file_path);
+	} else {
+		rtw_get_phy_file_path(adapter, MAC_FILE_FW_NIC);
+		err = rtw_halmac_dlfw_from_file(d, rtw_phy_para_file_path);
+	}
+#else
+	fw_bin = _FALSE;
+	#ifdef CONFIG_WOWLAN
+	if (_TRUE == wowlan)
+		err = rtw_halmac_dlfw(d, array_mp_8821c_fw_wowlan, array_length_mp_8821c_fw_wowlan);
+	else
+	#endif
+		err = rtw_halmac_dlfw(d, array_mp_8821c_fw_nic, array_length_mp_8821c_fw_nic);
+#endif
+
+	if (!err) {
+		hal_data->bFWReady = _TRUE;
+		hal_data->fw_ractrl = _TRUE;
+		RTW_INFO("%s Download Firmware from %s success\n", __func__, (fw_bin) ? "file" : "array");
+		RTW_INFO("%s FW Version:%d SubVersion:%d\n", (wowlan) ? "WOW" : "NIC", hal_data->firmware_version, hal_data->firmware_sub_version);
+
+		return _SUCCESS;
+	} else {
+		RTW_ERR("%s Download Firmware from %s failed\n", __func__, (fw_bin) ? "file" : "array");
+		return _FAIL;
+	}
+}
+/*
+ * Return:
+ *	_SUCCESS	Download Firmware MEM OK.
+ *	_FAIL		Download Firmware MEM FAIL!
+ */
+s32 rtl8821c_fw_mem_dl(PADAPTER adapter, enum fw_mem mem)
+{
+	struct dvobj_priv *d = adapter_to_dvobj(adapter);
+	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
+	int err = 0;
+	u8 fw_bin = _TRUE;
+
+#ifdef CONFIG_FILE_FWIMG
+	fw_bin = _TRUE;
+	rtw_get_phy_file_path(adapter, MAC_FILE_FW_NIC);
+	err = rtw_halmac_dlfw_mem_from_file(d, rtw_phy_para_file_path, mem);
+#else
+	fw_bin = _FALSE;
+	err = rtw_halmac_dlfw_mem(d, array_mp_8821c_fw_nic, array_length_mp_8821c_fw_nic, mem);
+#endif
+
+	if (err) {
+		RTW_ERR("%s Download Firmware MEM from %s failed\n", __func__, (fw_bin) ? "file" : "array");
+		return _FAIL;
+	}
+
+	RTW_INFO("%s Download Firmware MEM from %s success\n", __func__, (fw_bin) ? "file" : "array");
+	return _SUCCESS;
+
+}
+#ifdef CONFIG_AMPDU_PRETX_CD
+#include "rtl8821c.h"
+#define AMPDU_NUMBER				0x3F3F /*MAX AMPDU Number = 63*/
+#define REG_PRECNT_CTRL_8821C		0x04E5
+#define BIT_EN_PRECNT_8821C			BIT(11)
+#define PRECNT_TH					0x1E4 /*6.05us*/
+
+/* pre-tx count-down mechanism */
+void rtl8821c_pretx_cd_config(_adapter *adapter)
+{
+	u8 burst_mode;
+	u16 pre_cnt = PRECNT_TH | BIT_EN_PRECNT_8821C;
+
+	/*Enable AMPDU PRE-TX, Reg0x4BC[6] = 1*/
+	burst_mode = rtw_read8(adapter, REG_SW_AMPDU_BURST_MODE_CTRL_8821C);
+	if (!(burst_mode & BIT_PRE_TX_CMD_8821C)) {
+		burst_mode |= BIT_PRE_TX_CMD_8821C;
+		rtw_write8(adapter, REG_SW_AMPDU_BURST_MODE_CTRL_8821C, burst_mode);
+	}
+
+	/*MAX AMPDU Number = 63, Reg0x4C8[21:16] = 0x3F*/
+	rtw_write16(adapter, REG_PROT_MODE_CTRL_8821C + 2, AMPDU_NUMBER);
+
+	/*Reg0x4E5[11] = 1, Reg0x4E5[10:0] = 0x1E4 */
+	rtw_write8(adapter, REG_PRECNT_CTRL_8821C, (u8)(pre_cnt & 0xFF));
+	rtw_write8(adapter, (REG_PRECNT_CTRL_8821C + 1), (u8)(pre_cnt >> 8));
+
+	#if (defined(DBG_PRE_TX_HANG) && (defined(CONFIG_USB_HCI) || defined(CONFIG_SDIO_HCI)))
+	rtw_write32(adapter, REG_HIMR1_8821C ,
+		(rtw_read32(adapter, REG_HIMR1_8821C) | BIT_PRETXERR_HANDLE_IMR));
+	#endif
+}
+#endif /*CONFIG_AMPDU_PRETX_CD*/
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/rtl8821c/rtl8821c_ops.c linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/rtl8821c/rtl8821c_ops.c
--- linux-5.6.3/3rdparty/rtl8821ce/hal/rtl8821c/rtl8821c_ops.c	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/rtl8821c/rtl8821c_ops.c	2020-04-10 16:35:06.844661375 +0300
@@ -0,0 +1,3678 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2016 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#define _RTL8821C_OPS_C_
+
+#include <drv_types.h>		/* basic_types.h, rtw_io.h and etc. */
+#include <rtw_xmit.h>		/* struct xmit_priv */
+#ifdef DBG_CONFIG_ERROR_DETECT
+	#include <rtw_sreset.h>
+#endif /* DBG_CONFIG_ERROR_DETECT */
+#include <hal_data.h>		/* PHAL_DATA_TYPE, GET_HAL_DATA() */
+#include <hal_com.h>		/* rtw_hal_config_rftype(), dump_chip_info() and etc. */
+#include "../hal_halmac.h"	/* GET_RX_DESC_XXX_8821C() */
+#include "rtl8821c.h"
+#ifdef CONFIG_PCI_HCI
+	#include "rtl8821ce_hal.h"
+#endif
+#include "rtl8821c_dm.h"
+#ifdef CONFIG_SDIO_HCI
+#include "sdio/rtl8821cs.h"
+#endif
+
+static void read_chip_version(PADAPTER adapter)
+{
+	PHAL_DATA_TYPE hal;
+	u32 value32;
+
+
+	hal = GET_HAL_DATA(adapter);
+
+	value32 = rtw_read32(adapter, REG_SYS_CFG1_8821C);
+	hal->version_id.ICType = CHIP_8821C;
+	hal->version_id.ChipType = ((value32 & BIT_RTL_ID_8821C) ? TEST_CHIP : NORMAL_CHIP);
+	hal->version_id.CUTVersion = BIT_GET_CHIP_VER_8821C(value32);
+	hal->version_id.VendorType = BIT_GET_VENDOR_ID_8821C(value32);
+	hal->version_id.VendorType >>= 2;
+	switch (hal->version_id.VendorType) {
+	case 0:
+		hal->version_id.VendorType = CHIP_VENDOR_TSMC;
+		break;
+	case 1:
+		hal->version_id.VendorType = CHIP_VENDOR_SMIC;
+		break;
+	case 2:
+		hal->version_id.VendorType = CHIP_VENDOR_UMC;
+		break;
+	}
+	hal->version_id.RFType = ((value32 & BIT_RF_TYPE_ID_8821C) ? RF_TYPE_2T2R : RF_TYPE_1T1R);
+	hal->RegulatorMode = ((value32 & BIT_SPSLDO_SEL_8821C) ? RT_LDO_REGULATOR : RT_SWITCHING_REGULATOR);
+
+	value32 = rtw_read32(adapter, REG_SYS_STATUS1_8821C);
+	hal->version_id.ROMVer = BIT_GET_RF_RL_ID_8821C(value32);
+
+	/* For multi-function consideration. */
+	hal->MultiFunc = RT_MULTI_FUNC_NONE;
+	value32 = rtw_read32(adapter, REG_WL_BT_PWR_CTRL_8821C);
+	hal->MultiFunc |= ((value32 & BIT_WL_FUNC_EN_8821C) ? RT_MULTI_FUNC_WIFI : 0);
+	hal->MultiFunc |= ((value32 & BIT_BT_FUNC_EN_8821C) ? RT_MULTI_FUNC_BT : 0);
+	hal->PolarityCtl = ((value32 & BIT_WL_HWPDN_SL_8821C) ? RT_POLARITY_HIGH_ACT : RT_POLARITY_LOW_ACT);
+
+	rtw_hal_config_rftype(adapter);
+
+	dump_chip_info(hal->version_id);
+}
+
+/*
+ * Return:
+ *	_TRUE	valid ID
+ *	_FALSE	invalid ID
+ */
+static u8 Hal_EfuseParseIDCode(PADAPTER adapter, u8 *map)
+{
+	u16 EEPROMId;
+
+
+	/* Check 0x8129 again for making sure autoload status!! */
+	EEPROMId = le16_to_cpu(*(u16 *)map);
+	RTW_INFO("EEPROM ID = 0x%04x\n", EEPROMId);
+	if (EEPROMId == RTL_EEPROM_ID)
+		return _TRUE;
+
+	RTW_INFO("<WARN> EEPROM ID is invalid!!\n");
+	return _FALSE;
+}
+
+static void Hal_EfuseParseEEPROMVer(PADAPTER adapter, u8 *map, u8 mapvalid)
+{
+	PHAL_DATA_TYPE hal = GET_HAL_DATA(adapter);
+
+
+	if (_TRUE == mapvalid)
+		hal->EEPROMVersion = map[EEPROM_VERSION_8821C];
+	else
+		hal->EEPROMVersion = 1;
+
+	RTW_INFO("EEPROM Version = %d\n", hal->EEPROMVersion);
+}
+
+static void Hal_EfuseParseTxPowerInfo(PADAPTER adapter, u8 *map, u8 mapvalid)
+{
+	PHAL_DATA_TYPE hal = GET_HAL_DATA(adapter);
+	TxPowerInfo24G tbl2G4;
+	TxPowerInfo5G tbl5g;
+
+	hal_load_txpwr_info(adapter, &tbl2G4, &tbl5g, map);
+
+	if ((_TRUE == mapvalid) && (map[EEPROM_RF_BOARD_OPTION_8821C] != 0xFF))
+		hal->EEPROMRegulatory = map[EEPROM_RF_BOARD_OPTION_8821C] & 0x7; /* bit0~2 */
+	else
+		hal->EEPROMRegulatory = EEPROM_DEFAULT_BOARD_OPTION & 0x7; /* bit0~2 */
+	RTW_INFO("EEPROM Regulatory=0x%02x\n", hal->EEPROMRegulatory);
+}
+
+static void Hal_EfuseParseBoardType(PADAPTER adapter, u8 *map, u8 mapvalid)
+{
+	PHAL_DATA_TYPE hal = GET_HAL_DATA(adapter);
+
+
+	if ((_TRUE == mapvalid) && (map[EEPROM_RF_BOARD_OPTION_8821C] != 0xFF))
+		hal->InterfaceSel = (map[EEPROM_RF_BOARD_OPTION_8821C] & 0xE0) >> 5;
+	else
+		hal->InterfaceSel = (EEPROM_DEFAULT_BOARD_OPTION & 0xE0) >> 5;
+
+	RTW_INFO("EEPROM Board Type=0x%02x\n", hal->InterfaceSel);
+}
+
+static void Hal_EfuseParseBTCoexistInfo(PADAPTER adapter, u8 *map, u8 mapvalid)
+{
+	PHAL_DATA_TYPE hal = GET_HAL_DATA(adapter);
+	u8 setting;
+	u32 tmpu4;
+	u32 tmp_u32;
+
+	if ((mapvalid == _TRUE) && (map[EEPROM_RF_BOARD_OPTION_8821C] != 0xFF)) {
+
+		tmp_u32 = rtw_read32(adapter, REG_WL_BT_PWR_CTRL_8821C);
+		/* 0xc1[7:5] = 0x01 */
+		if ((((map[EEPROM_RF_BOARD_OPTION_8821C] & 0xe0) >> 5) == 0x01) && (tmp_u32 & BIT_BT_FUNC_EN_8821C))
+			hal->EEPROMBluetoothCoexist = _TRUE;
+		else
+			hal->EEPROMBluetoothCoexist = _FALSE;
+	} else
+		hal->EEPROMBluetoothCoexist = _FALSE;
+
+	hal->EEPROMBluetoothType = BT_RTL8821C;
+
+	setting = map[EEPROM_RF_BT_SETTING_8821C];
+	if ((_TRUE == mapvalid) && (setting != 0xFF)) {
+		/*Bit[0]: Total antenna number
+			0: 2-Antenna / 1: 1-Antenna	*/
+		hal->EEPROMBluetoothAntNum = setting & BIT(0);
+		/*
+		 * Bit[6]: One-Ant structure use Ant2(aux.) path or Ant1(main) path
+		 *	0: Ant2(aux.)
+		 *	1: Ant1(main), default
+		 */
+		hal->ant_path = (setting & BIT(6)) ? RF_PATH_B : RF_PATH_A;
+	} else {
+		hal->EEPROMBluetoothAntNum = Ant_x1;
+		hal->ant_path = RF_PATH_A;
+	}
+
+exit:
+	RTW_INFO("EEPROM %s BT-coex, ant_num=%d\n",
+		 hal->EEPROMBluetoothCoexist == _TRUE ? "Enable" : "Disable",
+		 hal->EEPROMBluetoothAntNum == Ant_x2 ? 2 : 1);
+}
+
+static void Hal_EfuseParseChnlPlan(PADAPTER adapter, u8 *map, u8 autoloadfail)
+{
+	hal_com_config_channel_plan(
+		adapter,
+		map ? &map[EEPROM_COUNTRY_CODE_8821C] : NULL,
+		map ? map[EEPROM_CHANNEL_PLAN_8821C] : 0xFF,
+		adapter->registrypriv.alpha2,
+		adapter->registrypriv.channel_plan,
+		RTW_CHPLAN_REALTEK_DEFINE,
+		autoloadfail
+	);
+}
+
+static void Hal_EfuseParseXtal(PADAPTER adapter, u8 *map, u8 mapvalid)
+{
+	PHAL_DATA_TYPE hal = GET_HAL_DATA(adapter);
+
+
+	if ((_TRUE == mapvalid) && map[EEPROM_XTAL_8821C] != 0xFF)
+		hal->crystal_cap = map[EEPROM_XTAL_8821C];
+	else
+		hal->crystal_cap = EEPROM_Default_CrystalCap;
+
+	RTW_INFO("EEPROM crystal_cap=0x%02x\n", hal->crystal_cap);
+}
+
+static void Hal_EfuseParseThermalMeter(PADAPTER adapter, u8 *map, u8 mapvalid)
+{
+	PHAL_DATA_TYPE hal = GET_HAL_DATA(adapter);
+
+
+	/* ThermalMeter from EEPROM */
+	if ((_TRUE == mapvalid) && (map[EEPROM_THERMAL_METER_8821C] != 0xFF))
+		hal->eeprom_thermal_meter = map[EEPROM_THERMAL_METER_8821C];
+	else {
+		hal->eeprom_thermal_meter = EEPROM_Default_ThermalMeter;
+		hal->odmpriv.rf_calibrate_info.is_apk_thermal_meter_ignore = _TRUE;
+	}
+
+	RTW_INFO("EEPROM ThermalMeter=0x%02x\n", hal->eeprom_thermal_meter);
+}
+
+static void Hal_EfuseParseAntennaDiversity(PADAPTER adapter, u8 *map, u8 mapvalid)
+{
+#ifdef CONFIG_ANTENNA_DIVERSITY
+	PHAL_DATA_TYPE hal = GET_HAL_DATA(adapter);
+	struct registry_priv *registry_par = &adapter->registrypriv;
+
+
+	if (hal->EEPROMBluetoothAntNum == Ant_x1)
+		hal->AntDivCfg = 0;
+	else {
+		if (registry_par->antdiv_cfg == 2)/* 0:OFF , 1:ON, 2:By EFUSE */
+			hal->AntDivCfg = (map[EEPROM_RF_BOARD_OPTION_8821C] & BIT3) ? _TRUE : _FALSE;
+		else
+			hal->AntDivCfg = registry_par->antdiv_cfg;
+	}
+	/*hal->TRxAntDivType = S0S1_TRX_HW_ANTDIV;*/
+	hal->with_extenal_ant_switch = ((map[EEPROM_RF_BT_SETTING_8821C] & BIT7) >> 7);
+
+	RTW_INFO("%s:EEPROM AntDivCfg=%d, AntDivType=%d, extenal_ant_switch:%d\n",
+		 __func__, hal->AntDivCfg, hal->TRxAntDivType, hal->with_extenal_ant_switch);
+#endif /* CONFIG_ANTENNA_DIVERSITY */
+}
+
+static void Hal_EfuseTxBBSwing(PADAPTER adapter, u8 *map, u8 mapvalid)
+{
+	PHAL_DATA_TYPE hal_data = GET_HAL_DATA(adapter);
+
+	if (_TRUE == mapvalid) {
+		hal_data->tx_bbswing_24G = map[EEPROM_TX_BBSWING_2G_8821C];
+		if (0xFF == hal_data->tx_bbswing_24G)
+			hal_data->tx_bbswing_24G = 0;
+		hal_data->tx_bbswing_5G = map[EEPROM_TX_BBSWING_5G_8821C];
+		if (0xFF == hal_data->tx_bbswing_5G)
+			hal_data->tx_bbswing_5G = 0;
+	} else {
+		hal_data->tx_bbswing_24G = 0;
+		hal_data->tx_bbswing_5G = 0;
+	}
+	RTW_INFO("EEPROM tx_bbswing_24G =0x%02x\n", hal_data->tx_bbswing_24G);
+	RTW_INFO("EEPROM tx_bbswing_5G =0x%02x\n", hal_data->tx_bbswing_5G);
+}
+
+static void Hal_EfuseParseCustomerID(PADAPTER adapter, u8 *map, u8 mapvalid)
+{
+	PHAL_DATA_TYPE hal = GET_HAL_DATA(adapter);
+
+
+	if (_TRUE == mapvalid)
+		hal->EEPROMCustomerID = map[EEPROM_CUSTOMER_ID_8821C];
+	else
+		hal->EEPROMCustomerID = 0;
+	RTW_INFO("EEPROM Customer ID=0x%02x\n", hal->EEPROMCustomerID);
+}
+
+static void Hal_DetectWoWMode(PADAPTER adapter)
+{
+#if defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN)
+	adapter_to_pwrctl(adapter)->bSupportRemoteWakeup = _TRUE;
+#else /* !(CONFIG_WOWLAN || CONFIG_AP_WOWLAN) */
+	adapter_to_pwrctl(adapter)->bSupportRemoteWakeup = _FALSE;
+#endif /* !(CONFIG_WOWLAN || CONFIG_AP_WOWLAN) */
+
+	RTW_INFO("EEPROM SupportRemoteWakeup=%d\n", adapter_to_pwrctl(adapter)->bSupportRemoteWakeup);
+}
+
+static void hal_ReadPAType(PADAPTER adapter, u8 *map, u8 mapvalid)
+{
+	PHAL_DATA_TYPE hal_data = GET_HAL_DATA(adapter);
+
+	if (mapvalid) {
+		/* AUTO - Get INFO from eFuse*/
+		if (GetRegAmplifierType2G(adapter) == 0) {
+			switch (hal_data->rfe_type) {
+			default:
+					hal_data->PAType_2G = 0;
+					hal_data->LNAType_2G = 0;
+					hal_data->ExternalPA_2G = 0;
+					hal_data->ExternalLNA_2G = 0;
+				break;
+			}
+		} else {
+			hal_data->ExternalPA_2G  = (GetRegAmplifierType2G(adapter) & ODM_BOARD_EXT_PA)  ? 1 : 0;
+			hal_data->ExternalLNA_2G = (GetRegAmplifierType2G(adapter) & ODM_BOARD_EXT_LNA) ? 1 : 0;
+		}
+
+		/* AUTO */
+		if (GetRegAmplifierType5G(adapter) == 0) {
+			switch (hal_data->rfe_type) {
+			default:
+				hal_data->PAType_5G = 0;
+				hal_data->LNAType_5G = 0;
+				hal_data->external_pa_5g = 0;
+				hal_data->external_lna_5g = 0;
+				break;
+			}
+		} else {
+			hal_data->external_pa_5g  = (GetRegAmplifierType5G(adapter) & ODM_BOARD_EXT_PA_5G)  ? 1 : 0;
+			hal_data->external_lna_5g = (GetRegAmplifierType5G(adapter) & ODM_BOARD_EXT_LNA_5G) ? 1 : 0;
+		}
+	} else {
+		/*Get INFO from registry*/
+		hal_data->ExternalPA_2G  = EEPROM_Default_PAType;
+		hal_data->external_pa_5g  = 0xFF;
+		hal_data->ExternalLNA_2G = EEPROM_Default_LNAType;
+		hal_data->external_lna_5g = 0xFF;
+
+		if (GetRegAmplifierType2G(adapter) == 0) {
+			hal_data->ExternalPA_2G  = 0;
+			hal_data->ExternalLNA_2G = 0;
+		} else {
+			hal_data->ExternalPA_2G  = (GetRegAmplifierType2G(adapter) & ODM_BOARD_EXT_PA)  ? 1 : 0;
+			hal_data->ExternalLNA_2G = (GetRegAmplifierType2G(adapter) & ODM_BOARD_EXT_LNA) ? 1 : 0;
+		}
+
+		if (GetRegAmplifierType5G(adapter) == 0) {
+			hal_data->external_pa_5g  = 0;
+			hal_data->external_lna_5g = 0;
+		} else {
+			hal_data->external_pa_5g  = (GetRegAmplifierType5G(adapter) & ODM_BOARD_EXT_PA_5G)  ? 1 : 0;
+			hal_data->external_lna_5g = (GetRegAmplifierType5G(adapter) & ODM_BOARD_EXT_LNA_5G) ? 1 : 0;
+		}
+	}
+
+	RTW_INFO("EEPROM PAType_2G is 0x%x, ExternalPA_2G = %d\n", hal_data->PAType_2G, hal_data->ExternalPA_2G);
+	RTW_INFO("EEPROM PAType_5G is 0x%x, external_pa_5g = %d\n", hal_data->PAType_5G, hal_data->external_pa_5g);
+	RTW_INFO("EEPROM LNAType_2G is 0x%x, ExternalLNA_2G = %d\n", hal_data->LNAType_2G, hal_data->ExternalLNA_2G);
+	RTW_INFO("EEPROM LNAType_5G is 0x%x, external_lna_5g = %d\n", hal_data->LNAType_5G, hal_data->external_lna_5g);
+}
+
+static void Hal_ReadAmplifierType(PADAPTER adapter, u8 *map, u8 mapvalid)
+{
+	PHAL_DATA_TYPE hal_data = GET_HAL_DATA(adapter);
+
+	if (hal_data->rfe_type < 8) { /*According to RF-EFUSE DOC : R15]*/
+		RTW_INFO("WIFI Module is iPA/iLNA\n");
+		return;
+	}
+
+	hal_ReadPAType(adapter, map, mapvalid);
+
+	/* [2.4G] extPA */
+	hal_data->TypeGPA  = hal_data->PAType_2G;
+
+	/* [5G] extPA */
+	hal_data->TypeAPA  = hal_data->PAType_5G;
+
+	/* [2.4G] extLNA */
+	hal_data->TypeGLNA = hal_data->LNAType_2G;
+
+	/* [5G] extLNA */
+	hal_data->TypeALNA = hal_data->LNAType_5G;
+
+	RTW_INFO("EEPROM TypeGPA = 0x%X\n", hal_data->TypeGPA);
+	RTW_INFO("EEPROM TypeAPA = 0x%X\n", hal_data->TypeAPA);
+	RTW_INFO("EEPROM TypeGLNA = 0x%X\n", hal_data->TypeGLNA);
+	RTW_INFO("EEPROM TypeALNA = 0x%X\n", hal_data->TypeALNA);
+}
+
+static u8 Hal_ReadRFEType(PADAPTER adapter, u8 *map, u8 mapvalid)
+{
+	/* [20160-06-22 -R15]
+		Type 0 - (2-Ant, DPDT), (2G_WLG, iPA, iLNA, iSW), (5G, iPA, iLNA, iSW)
+		Type 1 - (1-Ant, SPDT@Ant1), (2G_WLG, iPA, iLNA, iSW), (5G, iPA, iLNA, iSW)
+		Type 2 -(1-Ant, SPDT@Ant1) , (2G_BTG, iPA, iLNA, iSW), (5G, iPA, iLNA, iSW)
+		Type 3 - (1-Ant, DPDT@Ant2), (2G_WLG, iPA, iLNA, iSW), (5G, iPA, iLNA, iSW)
+		Type 4 - (1-Ant, DPDT@Ant2), (2G_BTG, iPA, iLNA, iSW), (5G, iPA, iLNA, iSW)
+		Type 5 - (2-Ant), (2G_WLG, iPA, iLNA, iSW), (5G, iPA, iLNA, iSW)
+		Type 6 - (2-Ant), (2G_WLG, iPA, iLNA, iSW), (5G, iPA, iLNA, iSW)
+		Type 7 - (1-Ant), (2G_BTG, iPA, iLNA, iSW), (5G, iPA, iLNA, iSW)
+	*/
+
+	PHAL_DATA_TYPE hal = GET_HAL_DATA(adapter);
+
+	/* check registry valye */
+	if (GetRegRFEType(adapter) != CONFIG_RTW_RFE_TYPE) {
+		hal->rfe_type = GetRegRFEType(adapter);
+		goto exit;
+	}
+
+	if (mapvalid) {
+		/* check efuse map */
+		hal->rfe_type = map[EEPROM_RFE_OPTION_8821C];
+		if (0xFF != hal->rfe_type)
+			goto exit;
+	}
+
+	/* error handle */
+	hal->rfe_type = 0;
+	RTW_ERR("\n\nEmpty EFUSE with unknown REF type!!\n\n");
+	RTW_ERR("please program efuse or specify correct RFE type.\n");
+	RTW_ERR("cmd: insmod rtl8821cx.ko rtw_RFE_type=<rfe_type>\n\n");
+	return _FAIL;
+
+exit:
+	RTW_INFO("EEPROM rfe_type=0x%x\n", hal->rfe_type);
+	return _SUCCESS;
+}
+
+
+static void Hal_EfuseParsePackageType(PADAPTER adapter, u8 *map, u8 mapvalid)
+{
+}
+
+#ifdef CONFIG_USB_HCI
+static void Hal_ReadUsbModeSwitch(PADAPTER adapter, u8 *map, u8 mapvalid)
+{
+	PHAL_DATA_TYPE hal = GET_HAL_DATA(adapter);
+
+	if (_TRUE == mapvalid)
+		/* check efuse 0x06 bit7 */
+		hal->EEPROMUsbSwitch = (map[EEPROM_USB_MODE_8821CU] & BIT7) >> 7;
+	else
+		hal->EEPROMUsbSwitch = _FALSE;
+
+	RTW_INFO("EEPROM USB Switch=%d\n", hal->EEPROMUsbSwitch);
+}
+
+static void hal_read_usb_pid_vid(PADAPTER adapter, u8 *map, u8 mapvalid)
+{
+	PHAL_DATA_TYPE hal = GET_HAL_DATA(adapter);
+
+	if (mapvalid == _TRUE) {
+		/* VID, PID */
+		hal->EEPROMVID = ReadLE2Byte(&map[EEPROM_VID_8821CU]);
+		hal->EEPROMPID = ReadLE2Byte(&map[EEPROM_PID_8821CU]);
+	} else {
+		hal->EEPROMVID = EEPROM_Default_VID;
+		hal->EEPROMPID = EEPROM_Default_PID;
+	}
+
+	RTW_INFO("EEPROM VID = 0x%04X, PID = 0x%04X\n", hal->EEPROMVID, hal->EEPROMPID);
+}
+
+#endif /* CONFIG_USB_HCI */
+
+/*
+ * Description:
+ *	Collect all information from efuse or files.
+ *	This function will do
+ *	1. Read registers to check hardware efuse available or not
+ *	2. Read Efuse/EEPROM
+ *	3. Read file if necessary
+ *	4. Parsing Efuse data
+ */
+u8 rtl8821c_read_efuse(PADAPTER adapter)
+{
+	PHAL_DATA_TYPE hal;
+	u8 val8;
+	u8 *efuse_map = NULL;
+	u8 valid;
+	u8 ret = _FAIL;
+
+	hal = GET_HAL_DATA(adapter);
+	efuse_map = hal->efuse_eeprom_data;
+
+	/* 1. Read registers to check hardware eFuse available or not */
+	val8 = rtw_read8(adapter, REG_SYS_EEPROM_CTRL_8821C);
+	hal->bautoload_fail_flag = (val8 & BIT_AUTOLOAD_SUS_8821C) ? _FALSE : _TRUE;
+	/*
+	* In 8821C, bautoload_fail_flag is used to present eFuse map is valid
+	* or not, no matter the map comes from hardware or files.
+	*/
+
+	/* 2. Read eFuse */
+	EFUSE_ShadowMapUpdate(adapter, EFUSE_WIFI, 0);
+
+	/* 3. Read Efuse file if necessary */
+#ifdef CONFIG_EFUSE_CONFIG_FILE
+	if (check_phy_efuse_tx_power_info_valid(adapter) == _FALSE)
+		if (Hal_readPGDataFromConfigFile(adapter) != _SUCCESS)
+			RTW_INFO("%s: <WARN> invalid phy efuse and read from file fail, will use driver default!!\n", __FUNCTION__);
+#endif /* CONFIG_EFUSE_CONFIG_FILE */
+
+	/* 4. Parse Efuse data */
+	valid = Hal_EfuseParseIDCode(adapter, efuse_map);
+	if (_TRUE == valid)
+		hal->bautoload_fail_flag = _FALSE;
+	else
+		hal->bautoload_fail_flag = _TRUE;
+
+	Hal_EfuseParseEEPROMVer(adapter, efuse_map, valid);
+	hal_config_macaddr(adapter, hal->bautoload_fail_flag);
+	Hal_EfuseParseTxPowerInfo(adapter, efuse_map, valid);
+	Hal_EfuseParseBoardType(adapter, efuse_map, valid);
+	Hal_EfuseParseBTCoexistInfo(adapter, efuse_map, valid);
+	Hal_EfuseParseChnlPlan(adapter, efuse_map, hal->bautoload_fail_flag);
+	Hal_EfuseParseXtal(adapter, efuse_map, valid);
+	Hal_EfuseParseThermalMeter(adapter, efuse_map, valid);
+	Hal_EfuseParseAntennaDiversity(adapter, efuse_map, valid);
+	Hal_EfuseParseCustomerID(adapter, efuse_map, valid);
+	Hal_DetectWoWMode(adapter);
+	if (Hal_ReadRFEType(adapter, efuse_map, valid) != _SUCCESS)
+		goto exit;
+	Hal_ReadAmplifierType(adapter, efuse_map, valid);
+	Hal_EfuseTxBBSwing(adapter, efuse_map, valid);
+
+	/* Data out of Efuse Map */
+	Hal_EfuseParsePackageType(adapter, efuse_map, valid);
+
+#ifdef CONFIG_USB_HCI
+	Hal_ReadUsbModeSwitch(adapter, efuse_map, valid);
+	hal_read_usb_pid_vid(adapter, efuse_map, valid);
+#endif /* CONFIG_USB_HCI */
+
+	/* set coex. ant info once efuse parsing is done */
+	rtw_btcoex_set_ant_info(adapter);
+
+#ifdef CONFIG_RTW_MAC_HIDDEN_RPT
+	if (hal_read_mac_hidden_rpt(adapter) != _SUCCESS)
+		goto exit;
+	{
+		struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter);
+
+		if (hal_spec->hci_type <= 3 && hal_spec->hci_type >= 1) {
+			hal->EEPROMBluetoothCoexist = _FALSE;
+			RTW_INFO("EEPROM Disable BT-coex by hal_spec\n");
+			rtw_btcoex_wifionly_AntInfoSetting(adapter);
+		}
+	}
+#endif
+	rtw_phydm_read_efuse(adapter);
+
+	ret = _SUCCESS;
+
+exit:
+	return ret;
+}
+
+void rtl8821c_run_thread(PADAPTER adapter)
+{
+}
+
+void rtl8821c_cancel_thread(PADAPTER adapter)
+{
+}
+
+/*
+ * Description:
+ *	Using 0x100 to check the power status of FW.
+ */
+static u8 check_ips_status(PADAPTER adapter)
+{
+	u8 val8;
+
+
+	RTW_INFO(FUNC_ADPT_FMT ": Read 0x100=0x%02x 0x86=0x%02x\n",
+		 FUNC_ADPT_ARG(adapter),
+		 rtw_read8(adapter, 0x100), rtw_read8(adapter, 0x86));
+
+	val8 = rtw_read8(adapter, 0x100);
+	if (val8 == 0xEA)
+		return _TRUE;
+
+	return _FALSE;
+}
+
+#ifdef DBG_CONFIG_ERROR_DETECT
+static void xmit_status_check(PADAPTER p)
+{
+	PHAL_DATA_TYPE hal = GET_HAL_DATA(p);
+	struct sreset_priv *psrtpriv = &hal->srestpriv;
+	struct xmit_priv *pxmitpriv = &p->xmitpriv;
+	systime current_time = 0;
+	unsigned int diff_time = 0;
+	u32 txdma_status = 0;
+
+	txdma_status = rtw_read32(p, REG_TXDMA_STATUS_8821C);
+	if (txdma_status != 0x00) {
+		RTW_INFO("%s REG_TXDMA_STATUS:0x%08x\n", __FUNCTION__, txdma_status);
+		psrtpriv->tx_dma_status_cnt++;
+		psrtpriv->self_dect_case = 4;
+		rtw_hal_sreset_reset(p);
+	}
+	#ifdef DBG_PRE_TX_HANG
+	#if defined(CONFIG_USB_HCI) || defined(CONFIG_SDIO_HCI)
+	{
+		u8 hisr = rtw_read8(p, REG_HISR1_8821C + 3);
+		if (hisr & BIT_PRETXERR) {
+			RTW_ERR("PRE_TX_HANG\n");
+			rtw_write8(p, REG_HISR1_8821C + 3, BIT_PRETXERR);
+		}
+	}
+	#endif
+	#endif/*DBG_PRE_TX_HANG*/
+
+#ifdef CONFIG_USB_HCI
+	current_time = rtw_get_current_time();
+
+	if (0 == pxmitpriv->free_xmitbuf_cnt || 0 == pxmitpriv->free_xmit_extbuf_cnt) {
+		diff_time = rtw_get_passing_time_ms(psrtpriv->last_tx_time);
+
+		if (diff_time > 2000) {
+			if (psrtpriv->last_tx_complete_time == 0)
+				psrtpriv->last_tx_complete_time = current_time;
+			else {
+				diff_time = rtw_get_passing_time_ms(psrtpriv->last_tx_complete_time);
+				if (diff_time > 4000) {
+					u32 ability = 0;
+
+					ability = rtw_phydm_ability_get(p);
+
+					RTW_INFO("%s tx hang %s\n", __FUNCTION__,
+						(ability & ODM_BB_ADAPTIVITY) ? "ODM_BB_ADAPTIVITY" : "");
+
+					if (!(ability & ODM_BB_ADAPTIVITY)) {
+						psrtpriv->self_dect_tx_cnt++;
+						psrtpriv->self_dect_case = 1;
+						rtw_hal_sreset_reset(p);
+					}
+				}
+			}
+		}
+	}
+
+#endif /* CONFIG_USB_HCI */
+
+	if (psrtpriv->dbg_trigger_point == SRESET_TGP_XMIT_STATUS) {
+		psrtpriv->dbg_trigger_point = SRESET_TGP_NULL;
+		rtw_hal_sreset_reset(p);
+		return;
+	}
+}
+
+static void check_rx_count(PADAPTER p)
+{
+	PHAL_DATA_TYPE hal = GET_HAL_DATA(p);
+	struct sreset_priv *psrtpriv = &hal->srestpriv;
+	u16 cur_mac_rxff_ptr;
+
+	cur_mac_rxff_ptr = rtw_read16(p, REG_RXFF_PTR_V1_8821C);
+
+#if 0
+	RTW_INFO("%s,psrtpriv->last_mac_rxff_ptr = %d , cur_mac_rxff_ptr = %d\n", __func__, psrtpriv->last_mac_rxff_ptr, cur_mac_rxff_ptr);
+#endif
+
+	if (psrtpriv->last_mac_rxff_ptr == cur_mac_rxff_ptr) {
+		psrtpriv->rx_cnt++;
+#if 0
+		RTW_INFO("%s,MAC case rx_cnt=%d\n", __func__, psrtpriv->rx_cnt);
+#endif
+		goto exit;
+	}
+
+	psrtpriv->rx_cnt = 0;
+
+exit:
+
+	psrtpriv->last_mac_rxff_ptr = cur_mac_rxff_ptr;
+
+	if (psrtpriv->rx_cnt > 3) {
+		psrtpriv->self_dect_case = 2;
+		psrtpriv->self_dect_rx_cnt++;
+		rtw_hal_sreset_reset(p);
+	}
+}
+
+static void linked_status_check(PADAPTER p)
+{
+	PHAL_DATA_TYPE hal = GET_HAL_DATA(p);
+	struct sreset_priv *psrtpriv = &hal->srestpriv;
+	struct	pwrctrl_priv *pwrpriv = adapter_to_pwrctl(p);
+	u32 rx_dma_status = 0;
+
+	rx_dma_status = rtw_read32(p, REG_RXDMA_STATUS_8821C);
+	if (rx_dma_status != 0x00) {
+		RTW_INFO("%s REG_RXDMA_STATUS:0x%08x\n", __FUNCTION__, rx_dma_status);
+		psrtpriv->rx_dma_status_cnt++;
+		psrtpriv->self_dect_case = 5;
+#ifdef CONFIG_USB_HCI
+		rtw_hal_sreset_reset(p);
+#endif /* CONFIG_USB_HCI */
+	}
+
+	if (psrtpriv->self_dect_fw) {
+		psrtpriv->self_dect_case = 3;
+#ifdef CONFIG_USB_HCI
+		rtw_hal_sreset_reset(p);
+#endif /* CONFIG_USB_HCI */
+	}
+
+#ifdef CONFIG_USB_HCI
+	check_rx_count(p);
+#endif /* CONFIG_USB_HCI */
+
+	if (psrtpriv->dbg_trigger_point == SRESET_TGP_LINK_STATUS) {
+		psrtpriv->dbg_trigger_point = SRESET_TGP_NULL;
+		rtw_hal_sreset_reset(p);
+		return;
+	}
+}
+#endif /* DBG_CONFIG_ERROR_DETECT */
+
+static const struct hw_port_reg port_cfg[] = {
+	/*port 0*/
+	{
+	.net_type = (REG_CR_8821C + 2),
+	.net_type_shift = 0,
+	.macaddr = REG_MACID,
+	.bssid = REG_BSSID,
+	.bcn_ctl = REG_BCN_CTRL,
+	.tsf_rst = REG_DUAL_TSF_RST,
+	.tsf_rst_bit = BIT_TSFTR_RST,
+	.bcn_space = REG_MBSSID_BCN_SPACE,
+	.bcn_space_shift = 0,
+	.bcn_space_mask = 0xffff,
+	.ps_aid = REG_BCN_PSR_RPT_8821C,
+	.ta = REG_TRANSMIT_ADDRSS_0_8821C,
+	},
+	/*port 1*/
+	{
+	.net_type = (REG_CR_8821C + 2),
+	.net_type_shift = 2,
+	.macaddr = REG_MACID1,
+	.bssid = REG_BSSID1,
+	.bcn_ctl = REG_BCN_CTRL_CLINT0,
+	.tsf_rst = REG_DUAL_TSF_RST,
+	.tsf_rst_bit = BIT_TSFTR_CLI0_RST,
+	.bcn_space = REG_MBSSID_BCN_SPACE,
+	.bcn_space_shift = 16,
+	.bcn_space_mask = 0xfff,
+	.ps_aid = REG_BCN_PSR_RPT1_8821C,
+	.ta = REG_TRANSMIT_ADDRSS_1_8821C,
+	},
+	/*port 2*/
+	{
+	.net_type =  REG_CR_EXT_8821C,
+	.net_type_shift = 0,
+	.macaddr = REG_MACID2,
+	.bssid = REG_BSSID2,
+	.bcn_ctl = REG_BCN_CTRL_CLINT1,
+	.tsf_rst = REG_DUAL_TSF_RST,
+	.tsf_rst_bit = BIT_TSFTR_CLI1_RST,
+	.bcn_space = REG_MBSSID_BCN_SPACE2,
+	.bcn_space_shift = 0,
+	.bcn_space_mask = 0xfff,
+	.ps_aid = REG_BCN_PSR_RPT2_8821C,
+	.ta = REG_TRANSMIT_ADDRSS_2_8821C,
+	},
+	/*port 3*/
+	{
+	.net_type =  REG_CR_EXT_8821C,
+	.net_type_shift = 2,
+	.macaddr = REG_MACID3,
+	.bssid = REG_BSSID3,
+	.bcn_ctl = REG_BCN_CTRL_CLINT2,
+	.tsf_rst = REG_DUAL_TSF_RST,
+	.tsf_rst_bit = BIT_TSFTR_CLI2_RST,
+	.bcn_space = REG_MBSSID_BCN_SPACE2,
+	.bcn_space_shift = 16,
+	.bcn_space_mask = 0xfff,
+	.ps_aid = REG_BCN_PSR_RPT3_8821C,
+	.ta = REG_TRANSMIT_ADDRSS_3_8821C,
+	},
+	/*port 4*/
+	{
+	.net_type =  REG_CR_EXT_8821C,
+	.net_type_shift = 4,
+	.macaddr = REG_MACID4,
+	.bssid = REG_BSSID4,
+	.bcn_ctl = REG_BCN_CTRL_CLINT3,
+	.tsf_rst = REG_DUAL_TSF_RST,
+	.tsf_rst_bit = BIT_TSFTR_CLI3_RST,
+	.bcn_space = REG_MBSSID_BCN_SPACE3,
+	.bcn_space_shift = 0,
+	.bcn_space_mask = 0xfff,
+	.ps_aid = REG_BCN_PSR_RPT4_8821C,
+	.ta = REG_TRANSMIT_ADDRSS_4_8821C,
+	},
+};
+
+static u32 hw_bcn_ctrl_addr(_adapter *adapter, u8 hw_port)
+{
+	struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter);
+	u32 addr = 0;
+
+	if (hw_port >= hal_spec->port_num) {
+		RTW_ERR(FUNC_ADPT_FMT" HW Port(%d) invalid\n", FUNC_ADPT_ARG(adapter), hw_port);
+		rtw_warn_on(1);
+		goto exit;
+	}
+
+	addr = port_cfg[hw_port].bcn_ctl;
+
+exit:
+	return addr;
+}
+
+static void hw_bcn_ctrl_set(_adapter *adapter, u8 hw_port, u8 bcn_ctl_val)
+{
+	u32 bcn_ctl_addr = 0;
+
+	if (hw_port >= MAX_HW_PORT) {
+		RTW_ERR(FUNC_ADPT_FMT" HW Port(%d) invalid\n", FUNC_ADPT_ARG(adapter), hw_port);
+		rtw_warn_on(1);
+		return;
+	}
+
+	bcn_ctl_addr = port_cfg[hw_port].bcn_ctl;
+	rtw_write8(adapter, bcn_ctl_addr, bcn_ctl_val);
+}
+
+static void hw_bcn_ctrl_add(_adapter *adapter, u8 hw_port, u8 bcn_ctl_val)
+{
+	u32 bcn_ctl_addr = 0;
+	u8 val8 = 0;
+
+	if (hw_port >= MAX_HW_PORT) {
+		RTW_ERR(FUNC_ADPT_FMT" HW Port(%d) invalid\n", FUNC_ADPT_ARG(adapter), hw_port);
+		rtw_warn_on(1);
+		return;
+	}
+
+	bcn_ctl_addr = port_cfg[hw_port].bcn_ctl;
+	val8 = rtw_read8(adapter, bcn_ctl_addr) | bcn_ctl_val;
+	rtw_write8(adapter, bcn_ctl_addr, val8);
+}
+
+static void hw_bcn_ctrl_clr(_adapter *adapter, u8 hw_port, u8 bcn_ctl_val)
+{
+	u32 bcn_ctl_addr = 0;
+	u8 val8 = 0;
+
+	if (hw_port >= MAX_HW_PORT) {
+		RTW_ERR(FUNC_ADPT_FMT" HW Port(%d) invalid\n", FUNC_ADPT_ARG(adapter), hw_port);
+		rtw_warn_on(1);
+		return;
+	}
+
+	bcn_ctl_addr = port_cfg[hw_port].bcn_ctl;
+	val8 = rtw_read8(adapter, bcn_ctl_addr);
+	val8 &= ~bcn_ctl_val;
+	rtw_write8(adapter, bcn_ctl_addr, val8);
+}
+
+
+static void hw_bcn_func(_adapter *adapter, u8 enable)
+{
+	if (enable)
+		hw_bcn_ctrl_add(adapter, get_hw_port(adapter), BIT_EN_BCN_FUNCTION);
+	else
+		hw_bcn_ctrl_clr(adapter, get_hw_port(adapter), BIT_EN_BCN_FUNCTION);
+}
+
+void hw_port0_tsf_sync(_adapter *adapter)
+{
+	rtw_write8(adapter, REG_SCHEDULER_RST, rtw_read8(adapter, REG_SCHEDULER_RST) | BIT_SYNC_CLI_ONCE_BY_TBTT_8821C);
+}
+
+void hw_tsf_reset(_adapter *adapter)
+{
+	u8 hw_port = rtw_hal_get_port(adapter);
+	u32 tsf_rst_addr = 0;
+	u8 tsf_rst_bit = 0;
+
+	if (hw_port >= MAX_HW_PORT) {
+		RTW_ERR(FUNC_ADPT_FMT" HW Port(%d) invalid\n", FUNC_ADPT_ARG(adapter), hw_port);
+		rtw_warn_on(1);
+		return;
+	}
+
+	tsf_rst_addr = port_cfg[hw_port].tsf_rst;
+	tsf_rst_bit = port_cfg[hw_port].tsf_rst_bit;
+	rtw_write8(adapter, tsf_rst_addr, tsf_rst_bit);
+}
+
+static void hw_var_set_monitor(PADAPTER Adapter, u8 *val)
+{
+	u32	rcr_bits;
+	u8 mode;
+	HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
+	struct mlme_priv *pmlmepriv = &(Adapter->mlmepriv);
+
+	mode = *((u8 *)val);
+
+	if (mode != _HW_STATE_MONITOR_) {
+		RTW_ERR(FUNC_ADPT_FMT" mode(0x%02x) invalid\n", FUNC_ADPT_ARG(Adapter), mode);
+		return;
+	}
+
+	/* Receive all type */
+	rcr_bits = BIT_AAP_8821C | BIT_APM_8821C  | BIT_AM_8821C
+		   | BIT_AB_8821C  | BIT_APWRMGT_8821C
+		   | BIT_APP_PHYSTS_8821C;
+
+	#ifdef CONFIG_RX_PACKET_APPEND_FCS
+	/* Append FCS */
+	rcr_bits |= BIT_APP_FCS_8821C;
+	#endif
+
+	#ifdef CONFIG_RX_PACKET_APPEND_CRC
+	/*CRC and ICV packet will drop in rx func*/
+	rcr_bits |= (BIT_ACRC32_8821C | BIT_AICV_8821C);
+	#endif
+
+	rtw_hal_get_hwreg(Adapter, HW_VAR_RCR, (u8 *)&pHalData->rcr_backup);
+	rtw_hal_set_hwreg(Adapter, HW_VAR_RCR, (u8 *)&rcr_bits);
+
+	/* Receive all data frames */
+	rtw_write16(Adapter, REG_RXFLTMAP2_8821C, 0xFFFF);
+
+	#if 0
+	/* tx pause */
+	rtw_write8(padapter, REG_TXPAUSE, 0xFF);
+	#endif
+}
+
+void hw_set_ta(_adapter *adapter, u8 hw_port, u8 *val)
+{
+	u8 idx = 0;
+	u32 reg = port_cfg[hw_port].ta;
+
+	for (idx = 0 ; idx < ETH_ALEN; idx++)
+		rtw_write8(adapter, (reg + idx), val[idx]);
+
+	RTW_INFO("%s("ADPT_FMT") hw port -%d TA: "MAC_FMT"\n",
+		__func__, ADPT_ARG(adapter), hw_port, MAC_ARG(val));
+}
+void hw_set_aid(_adapter *adapter, u8 hw_port, u8 aid)
+{
+	rtw_write16(adapter, port_cfg[hw_port].ps_aid, (0xF800 | aid));
+	RTW_INFO("%s("ADPT_FMT") hw port -%d AID: %d\n",
+			__func__, ADPT_ARG(adapter), hw_port, aid);
+}
+#ifdef CONFIG_CLIENT_PORT_CFG
+void rtw_hw_client_port_cfg(_adapter *adapter)
+{
+	struct mlme_ext_priv	*pmlmeext = &adapter->mlmeextpriv;
+	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
+	u8 clt_port = get_clt_port(adapter);
+
+	if (clt_port == CLT_PORT_INVALID)
+		return;
+	RTW_INFO("%s ("ADPT_FMT")\n", __func__, ADPT_ARG(adapter));
+
+	/*Network type*/
+	rtw_halmac_set_network_type(adapter_to_dvobj(adapter), clt_port, _HW_STATE_STATION_);
+	/*A1*/
+	rtw_halmac_set_mac_address(adapter_to_dvobj(adapter), clt_port, adapter_mac_addr(adapter));
+	/*A2*/
+	hw_set_ta(adapter, clt_port, pmlmeinfo->network.MacAddress);
+	/*A3*/
+	rtw_halmac_set_bssid(adapter_to_dvobj(adapter), clt_port, pmlmeinfo->network.MacAddress);
+	/*Beacon space*/
+	rtw_halmac_set_bcn_interval(adapter_to_dvobj(adapter), clt_port, pmlmeinfo->bcn_interval);
+	/*AID*/
+	hw_set_aid(adapter, clt_port, pmlmeinfo->aid);
+	/*Beacon control*/
+	hw_bcn_ctrl_set(adapter, clt_port, (BIT_P0_EN_RXBCN_RPT | BIT_EN_BCN_FUNCTION));
+
+	RTW_INFO("%s ("ADPT_FMT") clt_port:%d\n", __func__, ADPT_ARG(adapter), clt_port);
+}
+
+/*#define DBG_TSF_MONITOR*/
+void rtw_hw_client_port_clr(_adapter *adapter)
+{
+	u8 null_addr[ETH_ALEN] = {0};
+	u8 clt_port = get_clt_port(adapter);
+
+	if (clt_port == CLT_PORT_INVALID)
+		return;
+	RTW_INFO("%s ("ADPT_FMT") ==> \n", __func__, ADPT_ARG(adapter));
+	#ifdef DBG_TSF_MONITOR
+	/*Beacon control*/
+	hw_bcn_ctrl_clr(adapter, clt_port, BIT_EN_BCN_FUNCTION);
+	hw_tsf_reset(adapter);
+	#endif
+	/*Network type*/
+	rtw_halmac_set_network_type(adapter_to_dvobj(adapter), clt_port, _HW_STATE_NOLINK_);
+	/*A1*/
+	rtw_halmac_set_mac_address(adapter_to_dvobj(adapter), clt_port, null_addr);
+	/*A2*/
+	hw_set_ta(adapter, clt_port, null_addr);
+	/*A3*/
+	rtw_halmac_set_bssid(adapter_to_dvobj(adapter), clt_port, null_addr);
+ 	#ifdef DBG_TSF_MONITOR
+	if (0)
+	#endif
+	/*Beacon control*/
+	hw_bcn_ctrl_set(adapter, clt_port, (BIT_DIS_TSF_UDT | BIT_EN_BCN_FUNCTION));
+	/*AID*/
+	hw_set_aid(adapter, clt_port, 0);
+	RTW_INFO("%s("ADPT_FMT") clt_port:%d\n", __func__, ADPT_ARG(adapter), clt_port);
+}
+#endif
+
+static void hw_var_set_opmode(PADAPTER Adapter, u8 *val)
+{
+	u8	mode = *((u8 *)val);
+	static u8 isMonitor = _FALSE;
+	HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
+
+	if (isMonitor == _TRUE) {
+		/* reset RCR from backup */
+		rtw_hal_set_hwreg(Adapter, HW_VAR_RCR, (u8 *)&pHalData->rcr_backup);
+		rtw_hal_rcr_set_chk_bssid(Adapter, MLME_ACTION_NONE);
+		isMonitor = _FALSE;
+	}
+
+	if (mode == _HW_STATE_MONITOR_) {
+		isMonitor = _TRUE;
+		/* set net_type */
+		Set_MSR(Adapter, _HW_STATE_NOLINK_);
+
+		hw_var_set_monitor(Adapter, val);
+		return;
+	}
+
+	rtw_hal_set_hwreg(Adapter, HW_VAR_MAC_ADDR, adapter_mac_addr(Adapter)); /* set mac addr to mac register */
+	RTW_INFO(ADPT_FMT ": hw_port(%d) set mode=%d\n", ADPT_ARG(Adapter), get_hw_port(Adapter), mode);
+
+#ifdef CONFIG_MI_WITH_MBSSID_CAM /*For Port0 - MBSS CAM*/
+	if (Adapter->hw_port != HW_PORT0) {
+		RTW_ERR(ADPT_FMT ": Configure MBSSID cam on HW_PORT%d\n", ADPT_ARG(Adapter), Adapter->hw_port);
+		rtw_warn_on(1);
+	} else
+		hw_var_set_opmode_mbid(Adapter, mode);
+#else
+
+	rtw_iface_disable_tsf_update(Adapter);
+
+	/* set net_type */
+	Set_MSR(Adapter, mode);
+
+	if ((mode == _HW_STATE_STATION_) || (mode == _HW_STATE_NOLINK_)) {
+		#ifdef CONFIG_INTERRUPT_BASED_TXBCN
+		if (!rtw_mi_get_ap_num(Adapter) && !rtw_mi_get_mesh_num(Adapter)) {
+			/*CONFIG_INTERRUPT_BASED_TXBCN*/
+			#ifdef CONFIG_INTERRUPT_BASED_TXBCN_EARLY_INT
+			rtw_write8(Adapter, REG_DRVERLYINT, 0x05);/* restore early int time to 5ms */
+			#if defined(CONFIG_SDIO_HCI)
+			rtl8821cs_update_interrupt_mask(Adapter, 0, SDIO_HIMR_BCNERLY_INT_MSK);
+			#endif
+			#endif/* CONFIG_INTERRUPT_BASED_TXBCN_EARLY_INT */
+
+			#ifdef CONFIG_INTERRUPT_BASED_TXBCN_BCN_OK_ERR
+			#if defined(CONFIG_SDIO_HCI)
+			rtl8821cs_update_interrupt_mask(Adapter, 0, (SDIO_HIMR_TXBCNOK_MSK | SDIO_HIMR_TXBCNERR_MSK));
+			#endif
+			#endif /* CONFIG_INTERRUPT_BASED_TXBCN_BCN_OK_ERR */
+		}
+		#endif /* CONFIG_INTERRUPT_BASED_TXBCN */
+
+		if (!rtw_mi_get_ap_num(Adapter) && !rtw_mi_get_mesh_num(Adapter))
+			StopTxBeacon(Adapter);
+		hw_bcn_ctrl_set(Adapter, get_hw_port(Adapter), BIT_EN_BCN_FUNCTION_8821C | BIT_DIS_TSF_UDT_8821C);
+
+	} else if (mode == _HW_STATE_ADHOC_) {
+		ResumeTxBeacon(Adapter);
+		hw_bcn_ctrl_set(Adapter, get_hw_port(Adapter), BIT_EN_BCN_FUNCTION_8821C | BIT_DIS_TSF_UDT_8821C);
+
+	} else if (mode == _HW_STATE_AP_) {
+
+		if (Adapter->hw_port == HW_PORT0) {
+			#ifdef CONFIG_INTERRUPT_BASED_TXBCN
+			#ifdef CONFIG_INTERRUPT_BASED_TXBCN_EARLY_INT
+			#if defined(CONFIG_SDIO_HCI)
+			rtl8821cs_update_interrupt_mask(Adapter, SDIO_HIMR_BCNERLY_INT_MSK, 0);
+			#endif
+			#endif/* CONFIG_INTERRUPT_BASED_TXBCN_EARLY_INT */
+
+			#ifdef CONFIG_INTERRUPT_BASED_TXBCN_BCN_OK_ERR
+			#if defined(CONFIG_SDIO_HCI)
+			rtl8821cs_update_interrupt_mask(Adapter, (SDIO_HIMR_TXBCNOK_MSK | SDIO_HIMR_TXBCNERR_MSK), 0);
+			#endif
+			#endif/* CONFIG_INTERRUPT_BASED_TXBCN_BCN_OK_ERR */
+			#endif /* CONFIG_INTERRUPT_BASED_TXBCN */
+
+			/* enable to rx data frame */
+			rtw_write16(Adapter, REG_RXFLTMAP2_8821C, 0xFFFF);
+
+			/* Beacon Control related register for first time */
+			rtw_write8(Adapter, REG_BCNDMATIM_8821C, 0x02); /* 2ms	*/
+
+			rtw_write8(Adapter, REG_ATIMWND_8821C, 0x0c); /* ATIM:12ms */
+
+			/*rtw_write16(Adapter, REG_TSFTR_SYN_OFFSET_8821C, 0x7fff);*//* +32767 (~32ms) */
+			hw_tsf_reset(Adapter);
+			/* don't enable update TSF0 for if1 (due to TSF update when beacon/probe rsp are received) */
+		#if defined(CONFIG_INTERRUPT_BASED_TXBCN_BCN_OK_ERR)
+			hw_bcn_ctrl_set(Adapter, get_hw_port(Adapter), BIT_EN_BCN_FUNCTION_8821C | BIT_DIS_TSF_UDT_8821C | BIT_P0_EN_TXBCN_RPT_8821C);
+		#else
+			hw_bcn_ctrl_set(Adapter, get_hw_port(Adapter), BIT_EN_BCN_FUNCTION_8821C | BIT_DIS_TSF_UDT_8821C);
+		#endif
+		} else {
+			RTW_ERR(ADPT_FMT ": set AP mode on HW_PORT%d\n", ADPT_ARG(Adapter), Adapter->hw_port);
+			rtw_warn_on(1);
+		}
+	}
+#endif
+}
+
+#ifdef CONFIG_AP_PORT_SWAP
+void rtw_hal_port_reconfig(_adapter *adapter, u8 port)
+{
+	struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter);
+	u32 bssid_offset = 0;
+	u8 bssid[6] = {0};
+	u8 vnet_type = 0;
+	u8 vbcn_ctrl = 0;
+	u8 i;
+
+	if (port > (hal_spec->port_num - 1)) {
+		RTW_INFO("[WARN] "ADPT_FMT"- hw_port : %d,will switch to invalid port-%d\n",
+			 ADPT_ARG(adapter), adapter->hw_port, port);
+		rtw_warn_on(1);
+	}
+
+	RTW_PRINT(ADPT_FMT" - hw_port : %d,will switch to port-%d\n",
+		  ADPT_ARG(adapter), adapter->hw_port, port);
+
+	/*backup*/
+	vnet_type = (rtw_read8(adapter, port_cfg[adapter->hw_port].net_type) >> port_cfg[adapter->hw_port].net_type_shift) & 0x03;
+	vbcn_ctrl = rtw_read8(adapter, port_cfg[adapter->hw_port].bcn_ctl);
+	if (is_client_associated_to_ap(adapter)) {
+		RTW_INFO("port0-iface is STA mode and linked\n");
+		bssid_offset = port_cfg[adapter->hw_port].bssid;
+		for (i = 0; i < 6; i++)
+			bssid[i] = rtw_read8(adapter, bssid_offset + i);
+	}
+	/*reconfigure*/
+	adapter->hw_port = port;
+	rtw_hal_set_hwreg(adapter, HW_VAR_MAC_ADDR, adapter_mac_addr(adapter));
+	Set_MSR(adapter, vnet_type);
+
+	if (is_client_associated_to_ap(adapter)) {
+		rtw_hal_set_hwreg(adapter, HW_VAR_BSSID, bssid);
+		hw_tsf_reset(adapter);
+		#ifdef CONFIG_FW_MULTI_PORT_SUPPORT
+		rtw_set_default_port_id(adapter);
+		#endif
+	}
+#if defined(CONFIG_BT_COEXIST) && defined(CONFIG_FW_MULTI_PORT_SUPPORT)
+	if (GET_HAL_DATA(adapter)->EEPROMBluetoothCoexist == _TRUE)
+		rtw_hal_set_wifi_btc_port_id_cmd(adapter);
+#endif
+
+	rtw_write8(adapter, port_cfg[adapter->hw_port].bcn_ctl, vbcn_ctrl);
+}
+static void rtl8821c_ap_port_switch(_adapter *adapter, u8 mode)
+{
+	u8 hw_port = get_hw_port(adapter);
+	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
+	u8 ap_nums = 0;
+	_adapter *if_port0 = NULL;
+	int i;
+
+	RTW_INFO(ADPT_FMT ": hw_port(%d) will set mode to %d\n", ADPT_ARG(adapter), hw_port, mode);
+#if 0
+	#ifdef CONFIG_P2P
+	if (!rtw_p2p_chk_state(&adapter->wdinfo, P2P_STATE_NONE)) {
+		RTW_INFO("%s, role=%d, p2p_state=%d, pre_p2p_state=%d\n", __func__,
+			rtw_p2p_role(&adapter->wdinfo), rtw_p2p_state(&adapter->wdinfo), rtw_p2p_pre_state(&adapter->wdinfo));
+	}
+	#endif
+#endif
+
+	if (mode != _HW_STATE_AP_)
+		return;
+
+	if ((mode == _HW_STATE_AP_) && (hw_port == HW_PORT0))
+		return;
+
+	/*check and prepare switch port to port0 for AP mode's BCN function*/
+	ap_nums = rtw_mi_get_ap_num(adapter);
+	if (ap_nums > 0) {
+		RTW_ERR("SortAP mode numbers:%d, must move setting to MBSSID CAM, not support yet\n", ap_nums);
+		rtw_warn_on(1);
+		return;
+	}
+
+	/*Get iface of port-0*/
+	for (i = 0; i < dvobj->iface_nums; i++) {
+		if (get_hw_port(dvobj->padapters[i]) == HW_PORT0) {
+			if_port0 = dvobj->padapters[i];
+			break;
+		}
+	}
+
+	if (if_port0 == NULL) {
+		RTW_ERR("%s if_port0 == NULL\n", __func__);
+		rtw_warn_on(1);
+		return;
+	}
+	rtw_hal_port_reconfig(if_port0, hw_port);
+
+	adapter->hw_port = HW_PORT0;
+	RTW_INFO(ADPT_FMT ": Cfg SoftAP mode to hw_port(%d) done\n", ADPT_ARG(adapter), adapter->hw_port);
+
+}
+#endif
+
+static void hw_var_set_basic_rate(PADAPTER adapter, u8 *ratetbl)
+{
+#define RATE_1M		BIT(0)
+#define RATE_2M		BIT(1)
+#define RATE_5_5M	BIT(2)
+#define RATE_11M	BIT(3)
+#define RATE_6M		BIT(4)
+#define RATE_9M		BIT(5)
+#define RATE_12M	BIT(6)
+#define RATE_18M	BIT(7)
+#define RATE_24M	BIT(8)
+#define RATE_36M	BIT(9)
+#define RATE_48M	BIT(10)
+#define RATE_54M	BIT(11)
+#define RATE_MCS0	BIT(12)
+#define RATE_MCS1	BIT(13)
+#define RATE_MCS2	BIT(14)
+#define RATE_MCS3	BIT(15)
+#define RATE_MCS4	BIT(16)
+#define RATE_MCS5	BIT(17)
+#define RATE_MCS6	BIT(18)
+#define RATE_MCS7	BIT(19)
+
+#define RATES_CCK	(RATE_11M | RATE_5_5M | RATE_2M | RATE_1M)
+#define RATES_OFDM	(RATE_54M | RATE_48M | RATE_36M | RATE_24M | RATE_18M | RATE_12M | RATE_9M | RATE_6M)
+
+	struct mlme_ext_info *mlmext_info = &adapter->mlmeextpriv.mlmext_info;
+	PHAL_DATA_TYPE hal = GET_HAL_DATA(adapter);
+	u16 input_b = 0, masked = 0, ioted = 0, BrateCfg = 0;
+	u16 rrsr_2g_force_mask = RATES_CCK;
+	u16 rrsr_2g_allow_mask = RATE_24M | RATE_12M | RATE_6M | RATES_CCK;
+	u16 rrsr_5g_force_mask = RATE_6M;
+	u16 rrsr_5g_allow_mask = RATES_OFDM;
+	u32 val32;
+
+	HalSetBrateCfg(adapter, ratetbl, &BrateCfg);
+	input_b = BrateCfg;
+
+	/* apply force and allow mask */
+	if (hal->current_band_type == BAND_ON_2_4G) {
+		BrateCfg |= rrsr_2g_force_mask;
+		BrateCfg &= rrsr_2g_allow_mask;
+	} else {
+		BrateCfg |= rrsr_5g_force_mask;
+		BrateCfg &= rrsr_5g_allow_mask;
+	}
+
+	masked = BrateCfg;
+
+	/* IOT consideration */
+	if (mlmext_info->assoc_AP_vendor == HT_IOT_PEER_CISCO) {
+		/* if peer is cisco and didn't use ofdm rate, we enable 6M ack */
+		if ((BrateCfg & (RATE_24M | RATE_12M | RATE_6M)) == 0)
+			BrateCfg |= RATE_6M;
+	}
+
+	ioted = BrateCfg;
+
+	hal->BasicRateSet = BrateCfg;
+
+	RTW_INFO("[HW_VAR_BASIC_RATE] %#x->%#x->%#x\n", input_b, masked, ioted);
+
+	/* Set RRSR rate table. */
+	val32 = rtw_read32(adapter, REG_RRSR_8821C);
+	val32 &= ~(BIT_MASK_RRSC_BITMAP << BIT_SHIFT_RRSC_BITMAP);
+	val32 |= BIT_RRSC_BITMAP(BrateCfg);
+	val32 = rtw_write32(adapter, REG_RRSR_8821C, val32);
+}
+
+static void hw_var_hw_port_cfg(_adapter *adapter, u8 enable)
+{
+	if (enable)
+		hw_bcn_ctrl_add(adapter, get_hw_port(adapter), (BIT_P0_EN_RXBCN_RPT | BIT_DIS_TSF_UDT | BIT_EN_BCN_FUNCTION));
+	else
+		hw_bcn_ctrl_clr(adapter, get_hw_port(adapter), BIT_EN_BCN_FUNCTION);
+}
+static void hw_var_set_bcn_func(PADAPTER adapter, u8 enable)
+{
+	u8 val8;
+
+	if (enable) {
+		/* enable TX BCN report
+		 *  Reg REG_FWHW_TXQ_CTRL_8821C[2] = 1
+		 *  Reg REG_BCN_CTRL_8821C[3][5] = 1
+		 */
+		val8 = rtw_read8(adapter, REG_FWHW_TXQ_CTRL_8821C);
+		val8 |= BIT_EN_BCN_TRXRPT_V1_8821C;
+		rtw_write8(adapter, REG_FWHW_TXQ_CTRL_8821C, val8);
+
+		if (adapter->hw_port == HW_PORT0)
+			hw_bcn_ctrl_add(adapter, get_hw_port(adapter), BIT_EN_BCN_FUNCTION_8821C | BIT_P0_EN_TXBCN_RPT_8821C);
+		else
+			hw_bcn_ctrl_add(adapter, get_hw_port(adapter), BIT_EN_BCN_FUNCTION_8821C);
+	} else {
+		if (adapter->hw_port == HW_PORT0) {
+			val8 = BIT_EN_BCN_FUNCTION_8821C | BIT_P0_EN_TXBCN_RPT_8821C;
+
+			#ifdef CONFIG_BT_COEXIST
+			/* Always enable port0 beacon function for PSTDMA */
+			if (GET_HAL_DATA(adapter)->EEPROMBluetoothCoexist)
+				val8 = BIT_P0_EN_TXBCN_RPT_8821C;
+			#endif
+			hw_bcn_ctrl_clr(adapter, get_hw_port(adapter), val8);
+		} else
+			hw_bcn_ctrl_clr(adapter, get_hw_port(adapter), BIT_EN_BCN_FUNCTION_8821C);
+	}
+}
+
+static void hw_var_set_mlme_disconnect(PADAPTER adapter)
+{
+	u8 val8;
+
+#ifdef DBG_IFACE_STATUS
+	DBG_IFACE_STATUS_DUMP(adapter);
+#endif
+
+#ifdef CONFIG_CONCURRENT_MODE
+	if (rtw_mi_check_status(adapter, MI_LINKED) == _FALSE)
+#endif
+		/* reject all data frames under not link state */
+		rtw_write16(adapter, REG_RXFLTMAP2_8821C, 0);
+
+	/* reset TSF*/
+	hw_tsf_reset(adapter);
+
+	/* disable update TSF*/
+	rtw_iface_disable_tsf_update(adapter);
+
+	#ifdef CONFIG_CLIENT_PORT_CFG
+	if (MLME_IS_STA(adapter))
+		rtw_hw_client_port_clr(adapter);
+	#endif
+}
+
+static void hw_var_set_mlme_sitesurvey(PADAPTER adapter, u8 enable)
+{
+	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
+	u16 value_rxfltmap2;
+	u8 val8;
+	PHAL_DATA_TYPE hal;
+	struct mlme_priv *pmlmepriv;
+	int i;
+	_adapter *iface;
+
+
+#ifdef DBG_IFACE_STATUS
+	DBG_IFACE_STATUS_DUMP(adapter);
+#endif
+
+	hal = GET_HAL_DATA(adapter);
+	pmlmepriv = &adapter->mlmepriv;
+
+#ifdef CONFIG_FIND_BEST_CHANNEL
+	/* Receive all data frames */
+	value_rxfltmap2 = 0xFFFF;
+#else
+	/* not to receive data frame */
+	value_rxfltmap2 = 0;
+#endif
+
+	if (enable) {
+		/*
+		 * 1. configure REG_RXFLTMAP2
+		 * 2. disable TSF update &  buddy TSF update to avoid updating wrong TSF due to clear RCR_CBSSID_BCN
+		 * 3. config RCR to receive different BSSID BCN or probe rsp
+		 */
+
+		rtw_write16(adapter, REG_RXFLTMAP2_8821C, value_rxfltmap2);
+
+		rtw_hal_rcr_set_chk_bssid(adapter, MLME_SCAN_ENTER);
+
+		/* Save orignal RRSR setting. */
+		hal->RegRRSR = rtw_read16(adapter, REG_RRSR_8821C);
+
+		if (rtw_mi_get_ap_num(adapter) || rtw_mi_get_mesh_num(adapter))
+			StopTxBeacon(adapter);
+	} else {
+		/* sitesurvey done
+		 * 1. enable rx data frame
+		 * 2. config RCR not to receive different BSSID BCN or probe rsp
+		 * 3. can enable TSF update &  buddy TSF right now due to HW support(IC before 8821C not support ex:8812A/8814A/8192E...)
+		 */
+		if (rtw_mi_check_fwstate(adapter, _FW_LINKED | WIFI_AP_STATE | WIFI_MESH_STATE))/* enable to rx data frame */
+			rtw_write16(adapter, REG_RXFLTMAP2_8821C, 0xFFFF);
+
+		rtw_hal_rcr_set_chk_bssid(adapter, MLME_SCAN_DONE);
+
+		/* Restore orignal RRSR setting. */
+		rtw_write16(adapter, REG_RRSR_8821C, hal->RegRRSR);
+
+		if (rtw_mi_get_ap_num(adapter) || rtw_mi_get_mesh_num(adapter)) {
+			ResumeTxBeacon(adapter);
+			rtw_mi_tx_beacon_hdl(adapter);
+		}
+	}
+}
+static void hw_var_set_mlme_join(PADAPTER adapter, u8 type)
+{
+	u8 val8;
+	u16 val16;
+	u32 val32;
+	u8 RetryLimit;
+	PHAL_DATA_TYPE hal;
+	struct mlme_priv *pmlmepriv;
+
+	RetryLimit = RL_VAL_STA;
+	hal = GET_HAL_DATA(adapter);
+	pmlmepriv = &adapter->mlmepriv;
+
+
+#ifdef CONFIG_CONCURRENT_MODE
+	if (type == 0) {
+		/* prepare to join */
+		if (rtw_mi_get_ap_num(adapter) || rtw_mi_get_mesh_num(adapter))
+			StopTxBeacon(adapter);
+
+		/* enable to rx data frame.Accept all data frame */
+		rtw_write16(adapter, REG_RXFLTMAP2_8821C, 0xFFFF);
+
+		hw_bcn_func(adapter, _TRUE);
+		if (check_fwstate(pmlmepriv, WIFI_STATION_STATE) == _TRUE)
+			RetryLimit = (hal->CustomerID == RT_CID_CCX) ? RL_VAL_AP : RL_VAL_STA;
+		else /* Ad-hoc Mode */
+			RetryLimit = RL_VAL_AP;
+		#ifdef CONFIG_CLIENT_PORT_CFG
+		rtw_hw_client_port_cfg(adapter);
+		#endif
+
+		rtw_iface_enable_tsf_update(adapter);
+
+	} else if (type == 1) {
+		/* joinbss_event call back when join res < 0 */
+		if (rtw_mi_check_status(adapter, MI_LINKED) == _FALSE)
+			rtw_write16(adapter, REG_RXFLTMAP2_8821C, 0x00);
+
+		rtw_iface_disable_tsf_update(adapter);
+
+		if (rtw_mi_get_ap_num(adapter) || rtw_mi_get_mesh_num(adapter)) {
+			ResumeTxBeacon(adapter);
+
+			/* reset TSF 1/2 after resume_tx_beacon */
+			val8 = BIT_TSFTR_RST_8821C | BIT_TSFTR_CLI0_RST_8821C;
+			rtw_write8(adapter, REG_DUAL_TSF_RST_8821C, val8);
+		}
+		#ifdef CONFIG_CLIENT_PORT_CFG
+		if (MLME_IS_STA(adapter))
+			rtw_hw_client_port_clr(adapter);
+		#endif
+	} else if (type == 2) {
+		/* sta add event callback */
+		if (check_fwstate(pmlmepriv, WIFI_ADHOC_STATE | WIFI_ADHOC_MASTER_STATE)) {
+			rtw_write8(adapter, 0x542, 0x02);
+			RetryLimit = RL_VAL_AP;
+		}
+
+		if (rtw_mi_get_ap_num(adapter) || rtw_mi_get_mesh_num(adapter)) {
+			ResumeTxBeacon(adapter);
+
+			/* reset TSF 1/2 after resume_tx_beacon */
+			rtw_write8(adapter, REG_DUAL_TSF_RST_8821C, BIT_TSFTR_RST_8821C | BIT_TSFTR_CLI0_RST_8821C);
+		}
+	}
+
+	val16 = BIT_LRL_8821C(RetryLimit) | BIT_SRL_8821C(RetryLimit);
+	rtw_write16(adapter, REG_RETRY_LIMIT_8821C, val16);
+#else /* !CONFIG_CONCURRENT_MODE */
+	if (type == 0) {
+		/* prepare to join */
+
+		/* enable to rx data frame.Accept all data frame */
+		rtw_write16(adapter, REG_RXFLTMAP2_8821C, 0xFFFF);
+
+		if (check_fwstate(pmlmepriv, WIFI_STATION_STATE) == _TRUE)
+			RetryLimit = (hal->CustomerID == RT_CID_CCX) ? RL_VAL_AP : RL_VAL_STA;
+		else /* Ad-hoc Mode */
+			RetryLimit = RL_VAL_AP;
+		hw_bcn_func(adapter, _TRUE);
+
+		rtw_iface_enable_tsf_update(adapter);
+
+	} else if (type == 1) {
+		/* joinbss_event call back when join res < 0 */
+		rtw_write16(adapter, REG_RXFLTMAP2_8821C, 0x00);
+
+		rtw_iface_disable_tsf_update(adapter);
+
+	} else if (type == 2) {
+		/* sta add event callback */
+		if (check_fwstate(pmlmepriv, WIFI_ADHOC_STATE | WIFI_ADHOC_MASTER_STATE))
+			RetryLimit = RL_VAL_AP;
+	}
+
+	val16 = BIT_LRL_8821C(RetryLimit) | BIT_SRL_8821C(RetryLimit);
+	rtw_write16(adapter, REG_RETRY_LIMIT_8821C, val16);
+#endif /* !CONFIG_CONCURRENT_MODE */
+}
+
+static void hw_var_set_acm_ctrl(PADAPTER adapter, u8 ctrl)
+{
+	u8 hwctrl = 0;
+
+	if (ctrl) {
+		hwctrl |= BIT_ACMHWEN_8821C;
+
+		if (ctrl & BIT(1)) /* BE */
+			hwctrl |= BIT_BEQ_ACM_EN_8821C;
+		else
+			hwctrl &= (~BIT_BEQ_ACM_EN_8821C);
+
+		if (ctrl & BIT(2)) /* VI */
+			hwctrl |= BIT_VIQ_ACM_EN_8821C;
+		else
+			hwctrl &= (~BIT_VIQ_ACM_EN_8821C);
+
+		if (ctrl & BIT(3)) /* VO */
+			hwctrl |= BIT_VOQ_ACM_EN_8821C;
+		else
+			hwctrl &= (~BIT_VOQ_ACM_EN_8821C);
+	}
+
+	RTW_INFO("[HW_VAR_ACM_CTRL] Write 0x%02X\n", hwctrl);
+	rtw_write8(adapter, REG_ACMHWCTRL_8821C, hwctrl);
+}
+
+static void hw_var_set_sec_cfg(PADAPTER adapter, u8 cfg)
+{
+	u16 reg_scr_ori;
+	u16 reg_scr;
+
+	reg_scr = reg_scr_ori = rtw_read16(adapter, REG_SECCFG_8821C);
+	reg_scr |= (BIT_CHK_KEYID_8821C | BIT_RXDEC_8821C | BIT_TXENC_8821C);
+
+	if (_rtw_camctl_chk_cap(adapter, SEC_CAP_CHK_BMC))
+		reg_scr |= BIT_CHK_BMC_8821C;
+
+	if (_rtw_camctl_chk_flags(adapter, SEC_STATUS_STA_PK_GK_CONFLICT_DIS_BMC_SEARCH))
+		reg_scr |= BIT_NOSKMC_8821C;
+
+	if (reg_scr != reg_scr_ori)
+		rtw_write16(adapter, REG_SECCFG_8821C, reg_scr);
+
+	RTW_INFO("%s: [HW_VAR_SEC_CFG] 0x%x=0x%x\n", __FUNCTION__,
+		 REG_SECCFG_8821C, rtw_read32(adapter, REG_SECCFG_8821C));
+}
+
+static void hw_var_set_sec_dk_cfg(PADAPTER adapter, u8 enable)
+{
+	struct security_priv *sec = &adapter->securitypriv;
+	u8 reg_scr = rtw_read8(adapter, REG_SECCFG_8821C);
+
+	if (enable) {
+		/* Enable default key related setting */
+		reg_scr |= BIT_TXBCUSEDK_8821C;
+		if (sec->dot11AuthAlgrthm != dot11AuthAlgrthm_8021X)
+			reg_scr |= BIT_RXUHUSEDK_8821C | BIT_TXUHUSEDK_8821C;
+	} else {
+		/* Disable default key related setting */
+		reg_scr &= ~(BIT_RXBCUSEDK_8821C | BIT_TXBCUSEDK_8821C | BIT_RXUHUSEDK_8821C | BIT_TXUHUSEDK_8821C);
+	}
+
+	rtw_write8(adapter, REG_SECCFG_8821C, reg_scr);
+
+	RTW_INFO("%s: [HW_VAR_SEC_DK_CFG] 0x%x=0x%08x\n", __FUNCTION__,
+		 REG_SECCFG_8821C, rtw_read32(adapter, REG_SECCFG_8821C));
+}
+
+static void hw_var_set_bcn_valid(PADAPTER adapter)
+{
+	u8 val8 = 0;
+
+	/* only port 0 can TX BCN */
+	val8 = rtw_read8(adapter, REG_FIFOPAGE_CTRL_2_8821C + 1);
+	val8 = val8 | BIT(7);
+	rtw_write8(adapter, REG_FIFOPAGE_CTRL_2_8821C + 1, val8);
+}
+
+static void hw_var_set_cam_empty_entry(PADAPTER adapter, u8 ucIndex)
+{
+	u8 i;
+	u32 ulCommand = 0;
+	u32 ulContent = 0;
+	u32 ulEncAlgo = CAM_AES;
+
+	for (i = 0; i < CAM_CONTENT_COUNT; i++) {
+		/* filled id in CAM config 2 byte */
+		if (i == 0)
+			ulContent |= (ucIndex & 0x03) | ((u16)(ulEncAlgo) << 2);
+		else
+			ulContent = 0;
+
+		/* polling bit, and No Write enable, and address */
+		ulCommand = CAM_CONTENT_COUNT * ucIndex + i;
+		ulCommand |= BIT_SECCAM_POLLING_8821C | BIT_SECCAM_WE_8821C;
+		/* write content 0 is equall to mark invalid */
+		rtw_write32(adapter, REG_CAMWRITE_8821C, ulContent);
+		rtw_write32(adapter, REG_CAMCMD_8821C, ulCommand);
+	}
+}
+
+static void hw_var_set_ack_preamble(PADAPTER adapter, u8 bShortPreamble)
+{
+	u8 val8 = 0;
+
+
+	val8 = rtw_read8(adapter, REG_WMAC_TRXPTCL_CTL_8821C + 2);
+	val8 |= BIT(4) | BIT(5);
+
+	if (bShortPreamble)
+		val8 |= BIT1;
+	else
+		val8 &= (~BIT1);
+
+	rtw_write8(adapter, REG_WMAC_TRXPTCL_CTL_8821C + 2, val8);
+}
+
+void rtl8821c_dl_rsvd_page(PADAPTER adapter, u8 mstatus)
+{
+	PHAL_DATA_TYPE hal = GET_HAL_DATA(adapter);
+	struct mlme_ext_priv *pmlmeext = &adapter->mlmeextpriv;
+	struct mlme_ext_info *pmlmeinfo = &pmlmeext->mlmext_info;
+	struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(adapter);
+	BOOLEAN bcn_valid = _FALSE;
+	u8 DLBcnCount = 0;
+	u32 poll = 0;
+	u8 val8, org_bcn, org_cr;
+	u8 hw_port = rtw_hal_get_port(adapter);
+
+	RTW_INFO(FUNC_ADPT_FMT ":+ hw_port=%d mstatus(%x)\n",
+		 FUNC_ADPT_ARG(adapter), hw_port, mstatus);
+
+	if (mstatus == RT_MEDIA_CONNECT) {
+#if 0
+		BOOLEAN bRecover = _FALSE;
+#endif
+		u8 v8;
+
+		/* We should set AID, correct TSF, HW seq enable before set JoinBssReport to Fw in 8821C -bit 10:0 */
+		rtw_write16(adapter, port_cfg[hw_port].ps_aid, (0xF800 | pmlmeinfo->aid));
+
+		/* Enable SW TX beacon - Set REG_CR bit 8. DMA beacon by SW */
+		v8 = rtw_read8(adapter, REG_CR_8821C + 1);
+		org_cr = v8;
+		v8 |= (BIT_ENSWBCN_8821C >> 8);
+		rtw_write8(adapter, REG_CR_8821C + 1, v8);
+
+		/*
+		 * Disable Hw protection for a time which revserd for Hw sending beacon.
+		 * Fix download reserved page packet fail that access collision with the protection time.
+		 */
+		val8 = rtw_read8(adapter, REG_BCN_CTRL_8821C);
+		org_bcn = val8;
+		val8 &= ~BIT_EN_BCN_FUNCTION_8821C;
+		val8 |= BIT_DIS_TSF_UDT_8821C;
+		rtw_write8(adapter, REG_BCN_CTRL_8821C, val8);
+
+#if 0
+		/* Set FWHW_TXQ_CTRL 0x422[6]=0 to tell Hw the packet is not a real beacon frame. */
+		RegFwHwTxQCtrl = rtw_read8(adapter, REG_FWHW_TXQ_CTRL_8821C + 2);
+
+		if (RegFwHwTxQCtrl & BIT(6))
+			bRecover = _TRUE;
+
+		/* To tell Hw the packet is not a real beacon frame. */
+		RegFwHwTxQCtrl &= ~BIT(6);
+		rtw_write8(adapter, REG_FWHW_TXQ_CTRL_8821C + 2, RegFwHwTxQCtrl);
+#endif
+
+		/* Clear beacon valid check bit. */
+		rtw_hal_set_hwreg(adapter, HW_VAR_BCN_VALID, NULL);
+
+		DLBcnCount = 0;
+		poll = 0;
+		do {
+			/* download rsvd page. */
+			rtw_hal_set_fw_rsvd_page(adapter, _FALSE);
+			DLBcnCount++;
+			do {
+				rtw_yield_os();
+
+				/* check rsvd page download OK. */
+				rtw_hal_get_hwreg(adapter, HW_VAR_BCN_VALID, (u8 *)(&bcn_valid));
+				poll++;
+			} while (!bcn_valid && (poll % 10) != 0 && !RTW_CANNOT_RUN(adapter));
+
+		} while (!bcn_valid && DLBcnCount <= 100 && !RTW_CANNOT_RUN(adapter));
+
+		if (RTW_CANNOT_RUN(adapter))
+			;
+		else if (!bcn_valid)
+			RTW_ERR(FUNC_ADPT_FMT ": DL RSVD page failed! DLBcnCount:%u, poll:%u\n",
+				 FUNC_ADPT_ARG(adapter), DLBcnCount, poll);
+		else {
+			struct pwrctrl_priv *pwrctl = adapter_to_pwrctl(adapter);
+
+			pwrctl->fw_psmode_iface_id = adapter->iface_id;
+			rtw_hal_set_fw_rsvd_page(adapter, _TRUE);
+			RTW_INFO(ADPT_FMT ": DL RSVD page success! DLBcnCount:%u, poll:%u\n",
+				 ADPT_ARG(adapter), DLBcnCount, poll);
+		}
+
+		rtw_write8(adapter, REG_CR_8821C + 1, org_cr);
+		rtw_write8(adapter, REG_BCN_CTRL_8821C, org_bcn);
+#if 0
+		/*
+		 * To make sure that if there exists an adapter which would like to send beacon.
+		 * If exists, the origianl value of 0x422[6] will be 1, we should check this to
+		 * prevent from setting 0x422[6] to 0 after download reserved page, or it will cause
+		 * the beacon cannot be sent by HW.
+		 */
+		if (bRecover) {
+			RegFwHwTxQCtrl |= BIT(6);
+			rtw_write8(adapter, REG_FWHW_TXQ_CTRL_8821C + 2, RegFwHwTxQCtrl);
+		}
+#endif
+#ifndef CONFIG_PCI_HCI
+		/* Clear CR[8] or beacon packet will not be send to TxBuf anymore. */
+		v8 = rtw_read8(adapter, REG_CR_8821C + 1);
+		v8 &= ~BIT(0); /* ~ENSWBCN */
+		rtw_write8(adapter, REG_CR_8821C + 1, v8);
+#endif /* !CONFIG_PCI_HCI */
+	}
+
+}
+
+static void rtl8821c_set_h2c_fw_joinbssrpt(PADAPTER adapter, u8 mstatus)
+{
+	if (mstatus == RT_MEDIA_CONNECT)
+		rtl8821c_dl_rsvd_page(adapter, RT_MEDIA_CONNECT);
+}
+
+/*
+ * Parameters:
+ *	adapter
+ *	enable		_TRUE: enable; _FALSE: disable
+ */
+static u8 rx_agg_switch(PADAPTER adapter, u8 enable)
+{
+	/* if (rtl8821c_config_rx_agg(adapter, enable)) */
+	return _SUCCESS;
+
+	return _FAIL;
+}
+
+u8 rtl8821c_sethwreg(PADAPTER adapter, u8 variable, u8 *val)
+{
+	PHAL_DATA_TYPE hal = GET_HAL_DATA(adapter);
+	u8 ret = _SUCCESS;
+	u8 val8;
+	u16 val16;
+	u32 val32;
+
+
+	switch (variable) {
+	case HW_VAR_SET_OPMODE:
+		hw_var_set_opmode(adapter, val);
+		break;
+	/*
+		case HW_VAR_INIT_RTS_RATE:
+			break;
+	*/
+	case HW_VAR_BASIC_RATE:
+		hw_var_set_basic_rate(adapter, val);
+		break;
+
+	case HW_VAR_TXPAUSE:
+		rtw_write8(adapter, REG_TXPAUSE_8821C, *val);
+		break;
+
+	case HW_VAR_BCN_FUNC:
+		hw_var_set_bcn_func(adapter, *val);
+		break;
+
+	case HW_VAR_PORT_CFG:
+		hw_var_hw_port_cfg(adapter, *val);
+		break;
+
+	case HW_VAR_MLME_DISCONNECT:
+		hw_var_set_mlme_disconnect(adapter);
+		break;
+
+	case HW_VAR_MLME_SITESURVEY:
+		hw_var_set_mlme_sitesurvey(adapter, *val);
+#ifdef CONFIG_BT_COEXIST
+		if (hal->EEPROMBluetoothCoexist)
+			rtw_btcoex_ScanNotify(adapter, *val ? _TRUE : _FALSE);
+		else
+#endif /* CONFIG_BT_COEXIST */
+		rtw_btcoex_wifionly_scan_notify(adapter);
+		break;
+
+	case HW_VAR_MLME_JOIN:
+		hw_var_set_mlme_join(adapter, *val);
+#ifdef CONFIG_BT_COEXIST
+		if (hal->EEPROMBluetoothCoexist)
+			rtw_btcoex_ConnectNotify(adapter, *val ? _FALSE : _TRUE);
+		else
+#endif /* CONFIG_BT_COEXIST */
+		rtw_btcoex_wifionly_connect_notify(adapter);
+		break;
+
+	case HW_VAR_SLOT_TIME:
+		rtw_write8(adapter, REG_SLOT_8821C, *val);
+		break;
+
+	case HW_VAR_RESP_SIFS:
+		/* RESP_SIFS for CCK */
+		rtw_write8(adapter, REG_RESP_SIFS_CCK_8821C, val[0]);
+		rtw_write8(adapter, REG_RESP_SIFS_CCK_8821C + 1, val[1]);
+		/* RESP_SIFS for OFDM */
+		rtw_write8(adapter, REG_RESP_SIFS_OFDM_8821C, val[2]);
+		rtw_write8(adapter, REG_RESP_SIFS_OFDM_8821C + 1, val[3]);
+		break;
+
+	case HW_VAR_ACK_PREAMBLE:
+		hw_var_set_ack_preamble(adapter, *val);
+		break;
+
+	case HW_VAR_SEC_CFG:
+		hw_var_set_sec_cfg(adapter, *val);
+		break;
+
+	case HW_VAR_SEC_DK_CFG:
+		if (val)
+			hw_var_set_sec_dk_cfg(adapter, _TRUE);
+		else
+			hw_var_set_sec_dk_cfg(adapter, _FALSE);
+		break;
+
+	case HW_VAR_BCN_VALID:
+		hw_var_set_bcn_valid(adapter);
+		break;
+	/*
+		case HW_VAR_RF_TYPE:
+			break;
+	*/
+	case HW_VAR_CAM_EMPTY_ENTRY:
+		hw_var_set_cam_empty_entry(adapter, *val);
+		break;
+
+	case HW_VAR_CAM_INVALID_ALL:
+		val32 = BIT_SECCAM_POLLING_8821C | BIT_SECCAM_CLR_8821C;
+		rtw_write32(adapter, REG_CAMCMD_8821C, val32);
+		break;
+
+	case HW_VAR_AC_PARAM_VO:
+		rtw_write32(adapter, REG_EDCA_VO_PARAM_8821C, *(u32 *)val);
+		break;
+
+	case HW_VAR_AC_PARAM_VI:
+		rtw_write32(adapter, REG_EDCA_VI_PARAM_8821C, *(u32 *)val);
+		break;
+
+	case HW_VAR_AC_PARAM_BE:
+		hal->ac_param_be = *(u32 *)val;
+		rtw_write32(adapter, REG_EDCA_BE_PARAM_8821C, *(u32 *)val);
+		break;
+
+	case HW_VAR_AC_PARAM_BK:
+		rtw_write32(adapter, REG_EDCA_BK_PARAM_8821C, *(u32 *)val);
+		break;
+
+	case HW_VAR_ACM_CTRL:
+		hw_var_set_acm_ctrl(adapter, *val);
+		break;
+	/*
+		case HW_VAR_AMPDU_MIN_SPACE:
+			break;
+	*/
+#ifdef CONFIG_80211N_HT
+	case HW_VAR_AMPDU_FACTOR: {
+		u32 AMPDULen = *val; /* enum AGGRE_SIZE */
+
+		AMPDULen = (0x2000 << AMPDULen) - 1;
+		rtw_write32(adapter, REG_AMPDU_MAX_LENGTH_8821C, AMPDULen);
+	}
+	break;
+#endif /* CONFIG_80211N_HT */
+	case HW_VAR_RXDMA_AGG_PG_TH:
+		/*
+		 * TH=1 => invalidate RX DMA aggregation
+		 * TH=0 => validate RX DMA aggregation, use init value.
+		 */
+		if (*val == 0)
+			/* enable RXDMA aggregation */
+			rx_agg_switch(adapter, _TRUE);
+		else
+			/* disable RXDMA aggregation */
+			rx_agg_switch(adapter, _FALSE);
+		break;
+
+	case HW_VAR_H2C_FW_PWRMODE:
+		rtl8821c_set_FwPwrMode_cmd(adapter, *val);
+		break;
+	/*
+		case HW_VAR_H2C_PS_TUNE_PARAM:
+			break;
+	*/
+	case HW_VAR_H2C_FW_JOINBSSRPT:
+		rtl8821c_set_h2c_fw_joinbssrpt(adapter, *val);
+		break;
+	case HW_VAR_DL_RSVD_PAGE:
+		#ifdef CONFIG_BT_COEXIST
+		if (check_fwstate(&adapter->mlmepriv, WIFI_AP_STATE) == _TRUE)
+			rtl8821c_download_BTCoex_AP_mode_rsvd_page(adapter);
+		#endif
+		break;		/*
+			case HW_VAR_FWLPS_RF_ON:
+				break;
+		*/
+#ifdef CONFIG_P2P
+	case HW_VAR_H2C_FW_P2P_PS_OFFLOAD:
+		#ifdef CONFIG_FW_MULTI_PORT_SUPPORT
+		if (*val == P2P_PS_ENABLE)
+			rtw_set_default_port_id(adapter);
+		#endif
+		rtw_set_p2p_ps_offload_cmd(adapter, *val);
+		break;
+#endif
+
+		/*
+			case HW_VAR_TRIGGER_GPIO_0:
+			case HW_VAR_BT_SET_COEXIST:
+			case HW_VAR_BT_ISSUE_DELBA:
+				break;
+		*/
+
+	/*
+		case HW_VAR_SWITCH_EPHY_WoWLAN:
+		case HW_VAR_EFUSE_USAGE:
+		case HW_VAR_EFUSE_BYTES:
+		case HW_VAR_EFUSE_BT_USAGE:
+		case HW_VAR_EFUSE_BT_BYTES:
+			break;
+	*/
+	case HW_VAR_FIFO_CLEARN_UP: {
+		struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(adapter);
+		u8 trycnt = 100;
+		u32 reg_hw_ssn;
+
+		/* pause tx */
+		rtw_write8(adapter, REG_TXPAUSE_8821C, 0xff);
+
+		/* keep hw sn */
+		if (adapter->xmitpriv.hw_ssn_seq_no == 1)
+			reg_hw_ssn = REG_HW_SEQ1_8821C;
+		else if (adapter->xmitpriv.hw_ssn_seq_no == 2)
+			reg_hw_ssn = REG_HW_SEQ2_8821C;
+		else if (adapter->xmitpriv.hw_ssn_seq_no == 3)
+			reg_hw_ssn = REG_HW_SEQ3_8821C;
+		else
+			reg_hw_ssn = REG_HW_SEQ0_8821C;
+
+		adapter->xmitpriv.nqos_ssn = rtw_read16(adapter, reg_hw_ssn);
+
+		if (pwrpriv->bkeepfwalive != _TRUE) {
+			/* RX DMA stop */
+			val32 = rtw_read32(adapter, REG_RXPKT_NUM_8821C);
+			val32 |= BIT_RW_RELEASE_EN;
+			rtw_write32(adapter, REG_RXPKT_NUM_8821C, val32);
+			do {
+				val32 = rtw_read32(adapter, REG_RXPKT_NUM_8821C);
+				val32 &= BIT_RXDMA_IDLE_8821C;
+				if (val32)
+					break;
+
+				RTW_INFO("[HW_VAR_FIFO_CLEARN_UP] val=%x times:%d\n", val32, trycnt);
+			} while (--trycnt);
+			if (trycnt == 0)
+				RTW_INFO("[HW_VAR_FIFO_CLEARN_UP] Stop RX DMA failed!\n");
+#if 0
+			/* RQPN Load 0 */
+			rtw_write16(adapter, REG_RQPN_NPQ, 0);
+			rtw_write32(adapter, REG_RQPN, 0x80000000);
+			rtw_mdelay_os(2);
+#endif
+		}
+	}
+	break;
+
+	case HW_VAR_RESTORE_HW_SEQ: {
+		/* restore Sequence No. */
+		u32 reg_hw_ssn;
+
+		if (adapter->xmitpriv.hw_ssn_seq_no == 1)
+			reg_hw_ssn = REG_HW_SEQ1_8821C;
+		else if (adapter->xmitpriv.hw_ssn_seq_no == 2)
+			reg_hw_ssn = REG_HW_SEQ2_8821C;
+		else if (adapter->xmitpriv.hw_ssn_seq_no == 3)
+			reg_hw_ssn = REG_HW_SEQ3_8821C;
+		else
+			reg_hw_ssn = REG_HW_SEQ0_8821C;
+
+		rtw_write8(adapter, reg_hw_ssn, adapter->xmitpriv.nqos_ssn);
+	}
+	break;
+
+	case HW_VAR_CHECK_TXBUF: {
+		u16 rtylmtorg;
+		u8 RetryLimit = 0x01;
+		systime start;
+		u32 passtime;
+		u32 timelmt = 2000;	/* ms */
+		u32 waittime = 10;	/* ms */
+		u32 high, low, normal, extra, publc;
+		u16 rsvd, available;
+		u8 empty;
+
+
+		rtylmtorg = rtw_read16(adapter, REG_RETRY_LIMIT_8821C);
+
+		val16 = BIT_LRL_8821C(RetryLimit) | BIT_SRL_8821C(RetryLimit);
+		rtw_write16(adapter, REG_RETRY_LIMIT_8821C, val16);
+
+		/* Check TX FIFO empty or not */
+		empty = _FALSE;
+		high = 0;
+		low = 0;
+		normal = 0;
+		extra = 0;
+		publc = 0;
+		start = rtw_get_current_time();
+		while ((rtw_get_passing_time_ms(start) < timelmt)
+		       && !RTW_CANNOT_RUN(adapter)) {
+			high = rtw_read32(adapter, REG_FIFOPAGE_INFO_1_8821C);
+			low = rtw_read32(adapter, REG_FIFOPAGE_INFO_2_8821C);
+			normal = rtw_read32(adapter, REG_FIFOPAGE_INFO_3_8821C);
+			extra = rtw_read32(adapter, REG_FIFOPAGE_INFO_4_8821C);
+			publc = rtw_read32(adapter, REG_FIFOPAGE_INFO_5_8821C);
+
+			rsvd = BIT_GET_HPQ_V1_8821C(high);
+			available = BIT_GET_HPQ_AVAL_PG_V1_8821C(high);
+			if (rsvd != available) {
+				rtw_msleep_os(waittime);
+				continue;
+			}
+
+			rsvd = BIT_GET_LPQ_V1_8821C(low);
+			available = BIT_GET_LPQ_AVAL_PG_V1_8821C(low);
+			if (rsvd != available) {
+				rtw_msleep_os(waittime);
+				continue;
+			}
+
+			rsvd = BIT_GET_NPQ_V1_8821C(normal);
+			available = BIT_GET_NPQ_AVAL_PG_V1_8821C(normal);
+			if (rsvd != available) {
+				rtw_msleep_os(waittime);
+				continue;
+			}
+
+			rsvd = BIT_GET_EXQ_V1_8821C(extra);
+			available = BIT_GET_EXQ_AVAL_PG_V1_8821C(extra);
+			if (rsvd != available) {
+				rtw_msleep_os(waittime);
+				continue;
+			}
+
+			rsvd = BIT_GET_PUBQ_V1_8821C(publc);
+			available = BIT_GET_PUBQ_AVAL_PG_V1_8821C(publc);
+			if (rsvd != available) {
+				rtw_msleep_os(waittime);
+				continue;
+			}
+
+			empty = _TRUE;
+			break;
+		}
+
+		passtime = rtw_get_passing_time_ms(start);
+		if (_TRUE == empty)
+			RTW_INFO("[HW_VAR_CHECK_TXBUF] Empty in %d ms\n", passtime);
+		else if (RTW_CANNOT_RUN(adapter))
+			RTW_INFO("[HW_VAR_CHECK_TXBUF] bDriverStopped or bSurpriseRemoved\n");
+		else {
+			RTW_INFO("[HW_VAR_CHECK_TXBUF] NOT empty in %d ms\n", passtime);
+			RTW_INFO("[HW_VAR_CHECK_TXBUF] 0x230=0x%08x 0x234=0x%08x 0x238=0x%08x 0x23c=0x%08x 0x240=0x%08x\n",
+				 high, low, normal, extra, publc);
+
+		}
+
+		rtw_write16(adapter, REG_RETRY_LIMIT_8821C, rtylmtorg);
+	}
+	break;
+	/*
+		case HW_VAR_PCIE_STOP_TX_DMA:
+			break;
+	*/
+
+	/*
+		case HW_VAR_SYS_CLKR:
+			break;
+	*/
+#ifdef CONFIG_GPIO_WAKEUP
+	case HW_SET_GPIO_WL_CTRL: {
+		u8 enable = *val;
+		u8 value = 0;
+		u8 addr = REG_PAD_CTRL1_8821C + 3;
+
+		if (WAKEUP_GPIO_IDX == 6) {
+			value = rtw_read8(adapter, addr);
+
+			if (enable == _TRUE && (value & BIT(1)))
+				/* set 0x64[25] = 0 to control GPIO 6 */
+				rtw_write8(adapter, addr, value & (~BIT(1)));
+			else if (enable == _FALSE)
+				rtw_write8(adapter, addr, value | BIT(1));
+
+			RTW_INFO("[HW_SET_GPIO_WL_CTRL] 0x%02X=0x%02X\n",
+				 addr, rtw_read8(adapter, addr));
+		}
+	}
+	break;
+#endif
+	case HW_VAR_NAV_UPPER: {
+#define HAL_NAV_UPPER_UNIT	128	/* micro-second */
+		u32 usNavUpper = *(u32 *)val;
+
+		if (usNavUpper > HAL_NAV_UPPER_UNIT * 0xFF) {
+			RTW_INFO(FUNC_ADPT_FMT ": [HW_VAR_NAV_UPPER] value(0x%08X us) is larger than (%d * 0xFF)!!!\n",
+				FUNC_ADPT_ARG(adapter), usNavUpper, HAL_NAV_UPPER_UNIT);
+			break;
+		}
+
+		usNavUpper = (usNavUpper + HAL_NAV_UPPER_UNIT - 1) / HAL_NAV_UPPER_UNIT;
+		rtw_write8(adapter, REG_NAV_CTRL_8821C + 2, (u8)usNavUpper);
+	}
+	break;
+
+	/*
+		case HW_VAR_RPT_TIMER_SETTING:
+		case HW_VAR_TX_RPT_MAX_MACID:
+		case HW_VAR_CHK_HI_QUEUE_EMPTY:
+			break;
+	*/
+
+	/*
+		case HW_VAR_AMPDU_MAX_TIME:
+		case HW_VAR_WIRELESS_MODE:
+		case HW_VAR_USB_MODE:
+		break;
+	*/
+#ifdef CONFIG_AP_PORT_SWAP
+	case HW_VAR_PORT_SWITCH:
+		{
+			u8 mode = *((u8 *)val);
+
+			rtl8821c_ap_port_switch(adapter, mode);
+		}
+		break;
+#endif
+
+	/*
+		case HW_VAR_SOUNDING_RATE:
+		case HW_VAR_SOUNDING_STATUS:
+		case HW_VAR_SOUNDING_FW_NDPA:
+		case HW_VAR_SOUNDING_CLK:
+			break;
+	*/
+#ifdef CONFIG_BEAMFORMING	
+	case HW_VAR_SOUNDING_ENTER:
+		rtl8821c_phy_bf_enter(adapter, (struct sta_info*)val);
+		break;	
+
+	case HW_VAR_SOUNDING_LEAVE:
+		rtl8821c_phy_bf_leave(adapter, val);
+		break;
+
+	case HW_VAR_SOUNDING_SET_GID_TABLE:	
+		rtl8821c_phy_bf_set_gid_table(adapter, (struct beamformer_entry*)val);
+		break;
+#endif
+	default:
+		ret = SetHwReg(adapter, variable, val);
+		break;
+	}
+
+	return ret;
+}
+
+struct qinfo {
+	u32 head:11;
+	u32 tail:11;
+	u32 empty:1;
+	u32 ac:2;
+	u32 macid:7;
+};
+
+struct bcn_qinfo {
+	u16 head:12;
+	u16 rsvd:4;
+};
+
+static void dump_qinfo(void *sel, struct qinfo *info, u32 pkt_num, const char *tag)
+{
+	RTW_PRINT_SEL(sel, "%shead:0x%02x, tail:0x%02x, pkt_num:%u, macid:%u, ac:%u\n",
+		tag ? tag : "", info->head, info->tail, pkt_num, info->macid, info->ac);
+}
+
+static void dump_bcn_qinfo(void *sel, struct bcn_qinfo *info, u32 pkt_num, const char *tag)
+{
+	RTW_PRINT_SEL(sel, "%shead:0x%02x, pkt_num:%u\n",
+		      tag ? tag : "", info->head, pkt_num);
+}
+
+static void dump_mac_qinfo(void *sel, _adapter *adapter)
+{
+	u32 q0_info;
+	u32 q1_info;
+	u32 q2_info;
+	u32 q3_info;
+	u32 q4_info;
+	u32 q5_info;
+	u32 q6_info;
+	u32 q7_info;
+	u32 mg_q_info;
+	u32 hi_q_info;
+	u16 bcn_q_info;
+	u32 q0_q1_info;
+	u32 q2_q3_info;
+	u32 q4_q5_info;
+	u32 q6_q7_info;
+	u32 mg_hi_q_info;
+	u32 cmd_bcn_q_info;
+
+
+	q0_info = rtw_read32(adapter, REG_Q0_INFO_8821C);
+	q1_info = rtw_read32(adapter, REG_Q1_INFO_8821C);
+	q2_info = rtw_read32(adapter, REG_Q2_INFO_8821C);
+	q3_info = rtw_read32(adapter, REG_Q3_INFO_8821C);
+	q4_info = rtw_read32(adapter, REG_Q4_INFO_8821C);
+	q5_info = rtw_read32(adapter, REG_Q5_INFO_8821C);
+	q6_info = rtw_read32(adapter, REG_Q6_INFO_8821C);
+	q7_info = rtw_read32(adapter, REG_Q7_INFO_8821C);
+	mg_q_info = rtw_read32(adapter, REG_MGQ_INFO_8821C);
+	hi_q_info = rtw_read32(adapter, REG_HIQ_INFO_8821C);
+	bcn_q_info = rtw_read16(adapter, REG_BCNQ_INFO_8821C);
+
+	q0_q1_info = rtw_read32(adapter, REG_Q0_Q1_INFO_8821C);
+	q2_q3_info = rtw_read32(adapter, REG_Q2_Q3_INFO_8821C);
+	q4_q5_info = rtw_read32(adapter, REG_Q4_Q5_INFO_8821C);
+	q6_q7_info = rtw_read32(adapter, REG_Q6_Q7_INFO_8821C);
+	mg_hi_q_info = rtw_read32(adapter, REG_MGQ_HIQ_INFO_8821C);
+	cmd_bcn_q_info = rtw_read32(adapter, REG_CMDQ_BCNQ_INFO_8821C);
+
+	dump_qinfo(sel, (struct qinfo *)&q0_info, q0_q1_info&0xFFF, "Q0 ");
+	dump_qinfo(sel, (struct qinfo *)&q1_info, (q0_q1_info>>15)&0xFFF, "Q1 ");
+	dump_qinfo(sel, (struct qinfo *)&q2_info, q2_q3_info&0xFFF, "Q2 ");
+	dump_qinfo(sel, (struct qinfo *)&q3_info, (q2_q3_info>>15)&0xFFF, "Q3 ");
+	dump_qinfo(sel, (struct qinfo *)&q4_info, q4_q5_info&0xFFF, "Q4 ");
+	dump_qinfo(sel, (struct qinfo *)&q5_info, (q4_q5_info>>15)&0xFFF, "Q5 ");
+	dump_qinfo(sel, (struct qinfo *)&q6_info, q6_q7_info&0xFFF, "Q6 ");
+	dump_qinfo(sel, (struct qinfo *)&q7_info, (q6_q7_info>>15)&0xFFF, "Q7 ");
+	dump_qinfo(sel, (struct qinfo *)&mg_q_info, mg_hi_q_info&0xFFF, "MG ");
+	dump_qinfo(sel, (struct qinfo *)&hi_q_info, (mg_hi_q_info>>15)&0xFFF, "HI ");
+	dump_bcn_qinfo(sel, (struct bcn_qinfo *)&bcn_q_info, cmd_bcn_q_info&0xFFF, "BCN ");
+
+}
+
+static void dump_mac_txfifo(void *sel, _adapter *adapter)
+{
+	u32 hpq, lpq, npq, epq, pubq;
+
+	hpq = rtw_read32(adapter, REG_FIFOPAGE_INFO_1_8821C);
+	lpq = rtw_read32(adapter, REG_FIFOPAGE_INFO_2_8821C);
+	npq = rtw_read32(adapter, REG_FIFOPAGE_INFO_3_8821C);
+	epq = rtw_read32(adapter, REG_FIFOPAGE_INFO_4_8821C);
+	pubq = rtw_read32(adapter, REG_FIFOPAGE_INFO_5_8821C);
+
+	hpq = (hpq & 0xFFF0000)>>16;
+	lpq = (lpq & 0xFFF0000)>>16;
+	npq = (npq & 0xFFF0000)>>16;
+	epq = (epq & 0xFFF0000)>>16;
+	pubq = (pubq & 0xFFF0000)>>16;
+
+	RTW_PRINT_SEL(sel, "Tx: available page num: ");
+	if ((hpq == 0xAEA) && (hpq == lpq) && (hpq == pubq))
+		RTW_PRINT_SEL(sel, "N/A (reg val = 0xea)\n");
+	else
+		RTW_PRINT_SEL(sel, "HPQ: %d, LPQ: %d, NPQ: %d, EPQ: %d, PUBQ: %d\n"
+			, hpq, lpq, npq, epq, pubq);
+}
+
+static u8 hw_var_get_bcn_valid(PADAPTER adapter)
+{
+	u8 val8 = 0;
+	u8 ret = _FALSE;
+
+	/* only port 0 can TX BCN */
+	val8 = rtw_read8(adapter, REG_FIFOPAGE_CTRL_2_8821C + 1);
+	ret = (BIT(7) & val8) ? _TRUE : _FALSE;
+
+	return ret;
+}
+
+void rtl8821c_read_wmmedca_reg(PADAPTER adapter, u16 *vo_params, u16 *vi_params, u16 *be_params, u16 *bk_params)
+{
+	u8 vo_reg_params[4];
+	u8 vi_reg_params[4];
+	u8 be_reg_params[4];
+	u8 bk_reg_params[4];
+
+	rtl8821c_gethwreg(adapter, HW_VAR_AC_PARAM_VO, vo_reg_params);
+	rtl8821c_gethwreg(adapter, HW_VAR_AC_PARAM_VI, vi_reg_params);
+	rtl8821c_gethwreg(adapter, HW_VAR_AC_PARAM_BE, be_reg_params);
+	rtl8821c_gethwreg(adapter, HW_VAR_AC_PARAM_BK, bk_reg_params);
+
+	vo_params[0] = vo_reg_params[0];
+	vo_params[1] = vo_reg_params[1] & 0x0F;
+	vo_params[2] = (vo_reg_params[1] & 0xF0) >> 4;
+	vo_params[3] = ((vo_reg_params[3] << 8) | (vo_reg_params[2])) * 32;
+
+	vi_params[0] = vi_reg_params[0];
+	vi_params[1] = vi_reg_params[1] & 0x0F;
+	vi_params[2] = (vi_reg_params[1] & 0xF0) >> 4;
+	vi_params[3] = ((vi_reg_params[3] << 8) | (vi_reg_params[2])) * 32;
+
+	be_params[0] = be_reg_params[0];
+	be_params[1] = be_reg_params[1] & 0x0F;
+	be_params[2] = (be_reg_params[1] & 0xF0) >> 4;
+	be_params[3] = ((be_reg_params[3] << 8) | (be_reg_params[2])) * 32;
+
+	bk_params[0] = bk_reg_params[0];
+	bk_params[1] = bk_reg_params[1] & 0x0F;
+	bk_params[2] = (bk_reg_params[1] & 0xF0) >> 4;
+	bk_params[3] = ((bk_reg_params[3] << 8) | (bk_reg_params[2])) * 32;
+
+	vo_params[1] = (1 << vo_params[1]) - 1;
+	vo_params[2] = (1 << vo_params[2]) - 1;
+	vi_params[1] = (1 << vi_params[1]) - 1;
+	vi_params[2] = (1 << vi_params[2]) - 1;
+	be_params[1] = (1 << be_params[1]) - 1;
+	be_params[2] = (1 << be_params[2]) - 1;
+	bk_params[1] = (1 << bk_params[1]) - 1;
+	bk_params[2] = (1 << bk_params[2]) - 1;
+}
+
+void rtl8821c_gethwreg(PADAPTER adapter, u8 variable, u8 *val)
+{
+	PHAL_DATA_TYPE hal;
+	u8 val8;
+	u16 val16;
+	u32 val32;
+
+
+	hal = GET_HAL_DATA(adapter);
+
+	switch (variable) {
+	/*
+		case HW_VAR_INIT_RTS_RATE:
+		case HW_VAR_BASIC_RATE:
+			break;
+	*/
+	case HW_VAR_TXPAUSE:
+		*val = rtw_read8(adapter, REG_TXPAUSE_8821C);
+		break;
+	/*
+		case HW_VAR_BCN_FUNC:
+		case HW_VAR_MLME_DISCONNECT:
+		case HW_VAR_MLME_SITESURVEY:
+		case HW_VAR_MLME_JOIN:
+		case HW_VAR_BEACON_INTERVAL:
+		case HW_VAR_SLOT_TIME:
+		case HW_VAR_RESP_SIFS:
+		case HW_VAR_ACK_PREAMBLE:
+		case HW_VAR_SEC_CFG:
+		case HW_VAR_SEC_DK_CFG:
+			break;
+	*/
+	case HW_VAR_BCN_VALID:
+		*val = hw_var_get_bcn_valid(adapter);
+		break;
+	/*
+		case HW_VAR_RF_TYPE:
+		case HW_VAR_CAM_EMPTY_ENTRY:
+		case HW_VAR_CAM_INVALID_ALL:
+	*/
+	case HW_VAR_AC_PARAM_VO:
+		val32 = rtw_read32(adapter, REG_EDCA_VO_PARAM);
+		val[0] = val32 & 0xFF;
+		val[1] = (val32 >> 8) & 0xFF;
+		val[2] = (val32 >> 16) & 0xFF;
+		val[3] = (val32 >> 24) & 0x07;
+		break;
+
+	case HW_VAR_AC_PARAM_VI:
+		val32 = rtw_read32(adapter, REG_EDCA_VI_PARAM);
+		val[0] = val32 & 0xFF;
+		val[1] = (val32 >> 8) & 0xFF;
+		val[2] = (val32 >> 16) & 0xFF;
+		val[3] = (val32 >> 24) & 0x07;
+		break;
+
+	case HW_VAR_AC_PARAM_BE:
+		val32 = rtw_read32(adapter, REG_EDCA_BE_PARAM);
+		val[0] = val32 & 0xFF;
+		val[1] = (val32 >> 8) & 0xFF;
+		val[2] = (val32 >> 16) & 0xFF;
+		val[3] = (val32 >> 24) & 0x07;
+		break;
+
+	case HW_VAR_AC_PARAM_BK:
+		val32 = rtw_read32(adapter, REG_EDCA_BK_PARAM);
+		val[0] = val32 & 0xFF;
+		val[1] = (val32 >> 8) & 0xFF;
+		val[2] = (val32 >> 16) & 0xFF;
+		val[3] = (val32 >> 24) & 0x07;
+		break;
+	/*
+		case HW_VAR_ACM_CTRL:
+		case HW_VAR_AMPDU_MIN_SPACE:
+		case HW_VAR_AMPDU_FACTOR:
+		case HW_VAR_RXDMA_AGG_PG_TH:
+		case HW_VAR_H2C_FW_PWRMODE:
+		case HW_VAR_H2C_PS_TUNE_PARAM:
+		case HW_VAR_H2C_FW_JOINBSSRPT:
+			break;
+	*/
+		/*
+			case HW_VAR_H2C_FW_P2P_PS_OFFLOAD:
+			case HW_VAR_TRIGGER_GPIO_0:
+			case HW_VAR_BT_SET_COEXIST:
+			case HW_VAR_BT_ISSUE_DELBA:
+				break;
+		*/
+
+	/*
+		case HW_VAR_ANTENNA_DIVERSITY_SELECT:
+		case HW_VAR_SWITCH_EPHY_WoWLAN:
+		case HW_VAR_EFUSE_USAGE:
+		case HW_VAR_EFUSE_BYTES:
+		case HW_VAR_EFUSE_BT_USAGE:
+		case HW_VAR_EFUSE_BT_BYTES:
+		case HW_VAR_FIFO_CLEARN_UP:
+		case HW_VAR_RESTORE_HW_SEQ:
+		case HW_VAR_CHECK_TXBUF:
+		case HW_VAR_PCIE_STOP_TX_DMA:
+			break;
+	*/
+
+
+
+#if defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN)
+	case HW_VAR_SYS_CLKR:
+		*val = rtw_read8(adapter, REG_SYS_CLK_CTRL_8821C);
+		break;
+#endif
+	/*
+		case HW_VAR_NAV_UPPER:
+		case HW_VAR_RPT_TIMER_SETTING:
+		case HW_VAR_TX_RPT_MAX_MACID:
+			break;
+	*/
+	case HW_VAR_CHK_HI_QUEUE_EMPTY:
+		val16 = rtw_read16(adapter, REG_TXPKT_EMPTY_8821C);
+		*val = (val16 & BIT_HQQ_EMPTY_8821C) ? _TRUE : _FALSE;
+		break;
+	case HW_VAR_CHK_MGQ_CPU_EMPTY:
+		val16 = rtw_read16(adapter, REG_TXPKT_EMPTY_8821C);
+		*val = (val16 & BIT_MGQ_CPU_EMPTY_8821C) ? _TRUE : _FALSE;
+		break;
+	/*
+		case HW_VAR_AMPDU_MAX_TIME:
+		case HW_VAR_WIRELESS_MODE:
+		case HW_VAR_USB_MODE:
+		case HW_VAR_DO_IQK:
+		case HW_VAR_SOUNDING_ENTER:
+		case HW_VAR_SOUNDING_LEAVE:
+		case HW_VAR_SOUNDING_RATE:
+		case HW_VAR_SOUNDING_STATUS:
+		case HW_VAR_SOUNDING_FW_NDPA:
+		case HW_VAR_SOUNDING_CLK:
+			break;
+	*/
+	case HW_VAR_FW_PS_STATE:
+		/* driver read REG_SYS_CFG5 - BIT_LPS_STATUS REG_1070[3] to get hw ps state */
+		*((u16 *)val) = rtw_read8(adapter, REG_SYS_CFG5);
+		break;
+
+	case HW_VAR_DUMP_MAC_QUEUE_INFO:
+		dump_mac_qinfo(val, adapter);
+		break;
+
+	case HW_VAR_DUMP_MAC_TXFIFO:
+		dump_mac_txfifo(val, adapter);
+		break;
+	/*
+		case HW_VAR_ASIX_IOT:
+		case HW_VAR_H2C_BT_MP_OPER:
+			break;
+	*/
+
+	case HW_VAR_BCN_CTRL_ADDR:
+		*((u32 *)val) = hw_bcn_ctrl_addr(adapter, adapter->hw_port);
+		break;
+
+	default:
+		GetHwReg(adapter, variable, val);
+		break;
+	}
+}
+
+/*
+ * Description:
+ *	Change default setting of specified variable.
+ */
+u8 rtl8821c_sethaldefvar(PADAPTER adapter, HAL_DEF_VARIABLE variable, void *pval)
+{
+	PHAL_DATA_TYPE hal;
+	u8 bResult, val8;
+
+
+	hal = GET_HAL_DATA(adapter);
+	bResult = _SUCCESS;
+
+	switch (variable) {
+	/*
+		case HAL_DEF_UNDERCORATEDSMOOTHEDPWDB:
+		case HAL_DEF_IS_SUPPORT_ANT_DIV:
+		case HAL_DEF_DRVINFO_SZ:
+		case HAL_DEF_MAX_RECVBUF_SZ:
+		case HAL_DEF_RX_PACKET_OFFSET:
+		case HAL_DEF_RX_DMA_SZ_WOW:
+		case HAL_DEF_RX_DMA_SZ:
+		case HAL_DEF_RX_PAGE_SIZE:
+		case HAL_DEF_DBG_DUMP_RXPKT:
+		case HAL_DEF_RA_DECISION_RATE:
+		case HAL_DEF_RA_SGI:
+		case HAL_DEF_PT_PWR_STATUS:
+		case HW_VAR_MAX_RX_AMPDU_FACTOR:
+		case HAL_DEF_DBG_DUMP_TXPKT:
+		case HAL_DEF_TX_PAGE_BOUNDARY:
+		case HAL_DEF_TX_PAGE_BOUNDARY_WOWLAN:
+		case HAL_DEF_ANT_DETECT:
+		case HAL_DEF_PCI_SUUPORT_L1_BACKDOOR:
+		case HAL_DEF_PCI_AMD_L1_SUPPORT:
+		case HAL_DEF_PCI_ASPM_OSC:
+		case HAL_DEF_EFUSE_USAGE:
+		case HAL_DEF_EFUSE_BYTES:
+		case HW_VAR_BEST_AMPDU_DENSITY:
+			break;
+	*/
+	case HW_VAR_FREECNT:
+
+		val8 = *((u8*)pval);
+
+		if (val8 == 0) {
+			/* disable free run counter set 0x577[3]=0 */
+			rtw_write8(adapter, REG_MISC_CTRL,
+				rtw_read8(adapter, REG_MISC_CTRL)&(~BIT_EN_FREECNT));
+
+			/* reset FREE_RUN_COUNTER set 0x553[5]=1 */
+			val8 = rtw_read8(adapter, REG_DUAL_TSF_RST);
+			val8 |=  BIT_FREECNT_RST;
+			rtw_write8(adapter, REG_DUAL_TSF_RST, val8);
+
+		} else if (val8 == 1){
+
+			/* enable free run counter */
+
+			/* disable first set 0x577[3]=0 */
+			rtw_write8(adapter, REG_MISC_CTRL,
+				rtw_read8(adapter, REG_MISC_CTRL)&(~BIT_EN_FREECNT));
+
+			/* reset FREE_RUN_COUNTER set 0x553[5]=1 */
+			val8 = rtw_read8(adapter, REG_DUAL_TSF_RST);
+			val8 |=  BIT_FREECNT_RST;
+			rtw_write8(adapter, REG_DUAL_TSF_RST, val8);
+
+			/* enable free run counter 0x577[3]=1 */
+			rtw_write8(adapter, REG_MISC_CTRL,
+				rtw_read8(adapter, REG_MISC_CTRL)|BIT_EN_FREECNT);
+		}
+		break;
+
+	default:
+		bResult = SetHalDefVar(adapter, variable, pval);
+		break;
+	}
+
+	return bResult;
+}
+
+void rtl8821c_ra_info_dump(_adapter *padapter, void *sel)
+{
+	u8 mac_id;
+	struct sta_info *psta;
+	u32 rate_mask1, rate_mask2;
+	struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
+	struct macid_ctl_t *macid_ctl = dvobj_to_macidctl(dvobj);
+
+	for (mac_id = 0; mac_id < macid_ctl->num; mac_id++) {
+		if (rtw_macid_is_used(macid_ctl, mac_id) && !rtw_macid_is_bmc(macid_ctl, mac_id)) {
+			psta = macid_ctl->sta[mac_id];
+			if (!psta)
+				continue;
+
+			dump_sta_info(sel, psta);
+			rate_mask1 = macid_ctl->rate_bmp0[mac_id];
+			rate_mask2 = macid_ctl->rate_bmp1[mac_id];
+			_RTW_PRINT_SEL(sel, "rate_mask2:0x%08x, rate_mask1:0x%08x\n", rate_mask2, rate_mask1);
+		}
+	}
+}
+
+/*
+ * Description:
+ *	Query setting of specified variable.
+ */
+u8 rtl8821c_gethaldefvar(PADAPTER adapter, HAL_DEF_VARIABLE variable, void *pval)
+{
+	PHAL_DATA_TYPE hal;
+	u8 bResult;
+	u8 val8 = 0;
+	u32 val32 = 0;
+
+
+	hal = GET_HAL_DATA(adapter);
+	bResult = _SUCCESS;
+
+	switch (variable) {
+	/*
+		case HAL_DEF_UNDERCORATEDSMOOTHEDPWDB:
+			break;
+	*/
+	case HAL_DEF_IS_SUPPORT_ANT_DIV:
+#ifdef CONFIG_ANTENNA_DIVERSITY
+		*(u8 *)pval = _TRUE;
+#else
+		*(u8 *)pval = _FALSE;
+#endif
+		break;
+	case HAL_DEF_MAX_RECVBUF_SZ:
+		*((u32 *)pval) = MAX_RECVBUF_SZ;
+		break;
+	case HAL_DEF_RX_PACKET_OFFSET:
+		rtw_halmac_get_rx_desc_size(adapter_to_dvobj(adapter), &val32);
+		rtw_halmac_get_rx_drv_info_sz(adapter_to_dvobj(adapter), &val8);
+		*((u32 *)pval) = val32 + val8;
+		break;
+	/*
+	case HAL_DEF_DRVINFO_SZ:
+		rtw_halmac_get_rx_drv_info_sz(adapter_to_dvobj(adapter), &val8);
+		*((u32 *)pval) = val8;
+		break;
+		case HAL_DEF_RX_DMA_SZ_WOW:
+		case HAL_DEF_RX_DMA_SZ:
+		case HAL_DEF_RX_PAGE_SIZE:
+		case HAL_DEF_DBG_DUMP_RXPKT:
+		case HAL_DEF_RA_DECISION_RATE:
+		case HAL_DEF_RA_SGI:
+			break;
+	*/
+	/* only for 8188E */
+	case HAL_DEF_PT_PWR_STATUS:
+		break;
+
+	case HAL_DEF_TX_LDPC:
+		*(u8 *)pval = ((hal->phy_spec.ldpc_cap >> 8) & 0xFF) ? _TRUE : _FALSE;
+		break;
+
+	case HAL_DEF_RX_LDPC:
+		*(u8 *)pval = (hal->phy_spec.ldpc_cap & 0xFF) ? _TRUE : _FALSE;
+		break;
+
+	case HAL_DEF_TX_STBC:
+		*(u8 *)pval = ((hal->phy_spec.stbc_cap >> 8) & 0xFF) ? _TRUE : _FALSE;
+		break;
+
+	/* support 1RX for STBC */
+	case HAL_DEF_RX_STBC:
+		*(u8 *)pval = hal->phy_spec.stbc_cap & 0xFF;
+		break;
+
+	/* support Explicit TxBF for HT/VHT */
+	case HAL_DEF_EXPLICIT_BEAMFORMER:
+#ifdef CONFIG_BEAMFORMING
+		*(u8 *)pval = ((hal->phy_spec.txbf_cap >> 20)& 0xF) ? _TRUE : _FALSE;
+#else
+		*(u8 *)pval = _FALSE;
+#endif
+		break;
+
+	case HAL_DEF_EXPLICIT_BEAMFORMEE:
+#ifdef CONFIG_BEAMFORMING
+		*(u8 *)pval = ((hal->phy_spec.txbf_cap >> 16) & 0xF) ? _TRUE : _FALSE;
+#else
+		*(u8 *)pval = _FALSE;
+#endif
+		break;
+
+	
+	case HAL_DEF_VHT_MU_BEAMFORMER:
+#ifdef CONFIG_BEAMFORMING
+		*(u8 *)pval = ((hal->phy_spec.txbf_cap >> 28)& 0xF) ? _TRUE : _FALSE;
+#else
+		*(u8 *)pval = _FALSE;
+#endif
+		break;
+            
+	case HAL_DEF_VHT_MU_BEAMFORMEE:
+#ifdef CONFIG_BEAMFORMING
+		*(u8 *)pval = ((hal->phy_spec.txbf_cap >> 24)& 0xF) ? _TRUE : _FALSE;
+#else
+		*(u8 *)pval = _FALSE;
+#endif
+		break;
+
+	case HAL_DEF_BEAMFORMER_CAP:
+		*(u8 *)pval = (hal->phy_spec.txbf_param >> 24)& 0xFF ;
+		break;
+
+	case HAL_DEF_BEAMFORMEE_CAP:
+		*(u8 *)pval = (hal->phy_spec.txbf_param >> 16) & 0xFF ;
+		break;
+
+	case HW_DEF_RA_INFO_DUMP:
+		rtl8821c_ra_info_dump(adapter, pval);
+		break;
+	/*
+		case HAL_DEF_DBG_DUMP_TXPKT:
+		case HAL_DEF_TX_PAGE_SIZE:
+			break;
+	*/
+	case HAL_DEF_TX_PAGE_BOUNDARY:
+		rtw_halmac_get_rsvd_drv_pg_bndy(adapter_to_dvobj(adapter), (u16 *)pval);
+		break;
+	/*	case HAL_DEF_TX_PAGE_BOUNDARY_WOWLAN:
+		case HAL_DEF_ANT_DETECT:
+		case HAL_DEF_PCI_SUUPORT_L1_BACKDOOR:
+		case HAL_DEF_PCI_AMD_L1_SUPPORT:
+		case HAL_DEF_PCI_ASPM_OSC:
+		case HAL_DEF_EFUSE_USAGE:
+		case HAL_DEF_EFUSE_BYTES:
+			break;
+	*/
+	case HW_VAR_BEST_AMPDU_DENSITY:
+		*((u32 *)pval) = AMPDU_DENSITY_VALUE_4;
+		break;
+
+	default:
+		bResult = GetHalDefVar(adapter, variable, pval);
+		break;
+	}
+
+	return bResult;
+}
+
+/* xmit section */
+void rtl8821c_init_xmit_priv(_adapter *adapter)
+{
+	struct xmit_priv *pxmitpriv = &adapter->xmitpriv;
+
+	pxmitpriv->hw_ssn_seq_no = rtw_get_hwseq_no(adapter);
+	pxmitpriv->nqos_ssn = 0;
+}
+
+
+#if defined(CONFIG_CONCURRENT_MODE)
+void fill_txdesc_force_bmc_camid(struct pkt_attrib *pattrib, u8 *ptxdesc)
+{
+	if ((pattrib->encrypt > 0) && (!pattrib->bswenc)
+	    && (pattrib->bmc_camid != INVALID_SEC_MAC_CAM_ID)) {
+
+		SET_TX_DESC_EN_DESC_ID_8821C(ptxdesc, 1);
+		SET_TX_DESC_MACID_8821C(ptxdesc, pattrib->bmc_camid);
+	}
+}
+#endif
+
+void fill_txdesc_bmc_tx_rate(struct pkt_attrib *pattrib, u8 *ptxdesc)
+{
+	SET_TX_DESC_USE_RATE_8821C(ptxdesc, 1);
+	SET_TX_DESC_DATARATE_8821C(ptxdesc, MRateToHwRate(pattrib->rate));
+	SET_TX_DESC_DISDATAFB_8821C(ptxdesc, 1);
+}
+
+void rtl8821c_fill_txdesc_sectype(struct pkt_attrib *pattrib, u8 *ptxdesc)
+{
+	if ((pattrib->encrypt > 0) && !pattrib->bswenc) {
+		/* SEC_TYPE : 0:NO_ENC,1:WEP40/TKIP,2:WAPI,3:AES */
+		switch (pattrib->encrypt) {
+		case _WEP40_:
+		case _WEP104_:
+		case _TKIP_:
+		case _TKIP_WTMIC_:
+			SET_TX_DESC_SEC_TYPE_8821C(ptxdesc, 0x1);
+			break;
+#ifdef CONFIG_WAPI_SUPPORT
+		case _SMS4_:
+			SET_TX_DESC_SEC_TYPE_8821C(ptxdesc, 0x2);
+			break;
+#endif
+		case _AES_:
+			SET_TX_DESC_SEC_TYPE_8821C(ptxdesc, 0x3);
+			break;
+		case _NO_PRIVACY_:
+		default:
+			SET_TX_DESC_SEC_TYPE_8821C(ptxdesc, 0x0);
+			break;
+		}
+	}
+}
+
+void rtl8821c_fill_txdesc_vcs(PADAPTER adapter, struct pkt_attrib *pattrib, u8 *ptxdesc)
+{
+	struct mlme_ext_priv *pmlmeext = &adapter->mlmeextpriv;
+	struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
+
+
+	if (pattrib->vcs_mode) {
+		switch (pattrib->vcs_mode) {
+		case RTS_CTS:
+			SET_TX_DESC_RTSEN_8821C(ptxdesc, 1);
+			break;
+		case CTS_TO_SELF:
+			SET_TX_DESC_CTS2SELF_8821C(ptxdesc, 1);
+			break;
+		case NONE_VCS:
+		default:
+			break;
+		}
+
+		if (pmlmeinfo->preamble_mode == PREAMBLE_SHORT)
+			SET_TX_DESC_RTS_SHORT_8821C(ptxdesc, 1);
+
+		SET_TX_DESC_RTSRATE_8821C(ptxdesc, 0x8);/* RTS Rate=24M */
+		SET_TX_DESC_RTS_RTY_LOWEST_RATE_8821C(ptxdesc, 0xf);
+	}
+}
+
+u8 rtl8821c_bw_mapping(PADAPTER adapter, struct pkt_attrib *pattrib)
+{
+	u8 BWSettingOfDesc = 0;
+	PHAL_DATA_TYPE hal = GET_HAL_DATA(adapter);
+
+
+	if (hal->current_channel_bw == CHANNEL_WIDTH_80) {
+		if (pattrib->bwmode == CHANNEL_WIDTH_80)
+			BWSettingOfDesc = 2;
+		else if (pattrib->bwmode == CHANNEL_WIDTH_40)
+			BWSettingOfDesc = 1;
+		else
+			BWSettingOfDesc = 0;
+	} else if (hal->current_channel_bw == CHANNEL_WIDTH_40) {
+		if ((pattrib->bwmode == CHANNEL_WIDTH_40) || (pattrib->bwmode == CHANNEL_WIDTH_80))
+			BWSettingOfDesc = 1;
+		else
+			BWSettingOfDesc = 0;
+	} else
+		BWSettingOfDesc = 0;
+
+	return BWSettingOfDesc;
+}
+
+u8 rtl8821c_sc_mapping(PADAPTER adapter, struct pkt_attrib *pattrib)
+{
+	u8 SCSettingOfDesc = 0;
+	PHAL_DATA_TYPE hal = GET_HAL_DATA(adapter);
+
+
+	if (hal->current_channel_bw == CHANNEL_WIDTH_80) {
+		if (pattrib->bwmode == CHANNEL_WIDTH_80)
+			SCSettingOfDesc = VHT_DATA_SC_DONOT_CARE;
+		else if (pattrib->bwmode == CHANNEL_WIDTH_40) {
+			if (hal->nCur80MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_LOWER)
+				SCSettingOfDesc = VHT_DATA_SC_40_LOWER_OF_80MHZ;
+			else if (hal->nCur80MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_UPPER)
+				SCSettingOfDesc = VHT_DATA_SC_40_UPPER_OF_80MHZ;
+			else
+				RTW_INFO("SCMapping: DONOT CARE Mode Setting\n");
+		} else {
+			if ((hal->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_LOWER) && (hal->nCur80MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_LOWER))
+				SCSettingOfDesc = VHT_DATA_SC_20_LOWEST_OF_80MHZ;
+			else if ((hal->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_UPPER) && (hal->nCur80MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_LOWER))
+				SCSettingOfDesc = VHT_DATA_SC_20_LOWER_OF_80MHZ;
+			else if ((hal->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_LOWER) && (hal->nCur80MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_UPPER))
+				SCSettingOfDesc = VHT_DATA_SC_20_UPPER_OF_80MHZ;
+			else if ((hal->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_UPPER) && (hal->nCur80MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_UPPER))
+				SCSettingOfDesc = VHT_DATA_SC_20_UPPERST_OF_80MHZ;
+			else
+				RTW_INFO("SCMapping: DONOT CARE Mode Setting\n");
+		}
+	} else if (hal->current_channel_bw == CHANNEL_WIDTH_40) {
+		if (pattrib->bwmode == CHANNEL_WIDTH_40)
+			SCSettingOfDesc = VHT_DATA_SC_DONOT_CARE;
+		else if (pattrib->bwmode == CHANNEL_WIDTH_20) {
+			if (hal->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_UPPER)
+				SCSettingOfDesc = VHT_DATA_SC_20_UPPER_OF_80MHZ;
+			else if (hal->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_LOWER)
+				SCSettingOfDesc = VHT_DATA_SC_20_LOWER_OF_80MHZ;
+			else
+				SCSettingOfDesc = VHT_DATA_SC_DONOT_CARE;
+		}
+	} else
+		SCSettingOfDesc = VHT_DATA_SC_DONOT_CARE;
+
+	return SCSettingOfDesc;
+}
+
+void rtl8821c_fill_txdesc_phy(PADAPTER adapter, struct pkt_attrib *pattrib, u8 *ptxdesc)
+{
+	if (pattrib->ht_en) {
+		/* Set Bandwidth and sub-channel settings. */
+		SET_TX_DESC_DATA_BW_8821C(ptxdesc, rtl8821c_bw_mapping(adapter, pattrib));
+		SET_TX_DESC_DATA_SC_8821C(ptxdesc, rtl8821c_sc_mapping(adapter, pattrib));
+	}
+}
+
+void rtl8821c_cal_txdesc_chksum(PADAPTER adapter, u8 *ptxdesc)
+{
+	struct halmac_adapter *halmac;
+	struct halmac_api *api;
+
+
+	halmac = adapter_to_halmac(adapter);
+	api = HALMAC_GET_API(halmac);
+
+	api->halmac_fill_txdesc_checksum(halmac, ptxdesc);
+}
+
+
+#ifdef CONFIG_MP_INCLUDED
+void rtl8821c_prepare_mp_txdesc(PADAPTER adapter, struct mp_priv *pmp_priv)
+{
+	u32 desc_size = 0;
+	u8 *desc;
+	struct pkt_attrib *attrib;
+	u32 pkt_size;
+	s32 bmcast;
+	u8 data_rate, pwr_status, offset;
+
+	rtw_halmac_get_tx_desc_size(adapter_to_dvobj(adapter), &desc_size);
+
+	desc = pmp_priv->tx.desc;
+	attrib = &pmp_priv->tx.attrib;
+	pkt_size = attrib->last_txcmdsz;
+	bmcast = IS_MCAST(attrib->ra);
+
+	SET_TX_DESC_LS_8821C(desc, 1);
+	SET_TX_DESC_TXPKTSIZE_8821C(desc, pkt_size);
+
+	offset = desc_size;
+	SET_TX_DESC_OFFSET_8821C(desc, offset);
+
+#if defined(CONFIG_PCI_HCI) || defined(CONFIG_SDIO_HCI)
+	SET_TX_DESC_PKT_OFFSET_8821C(desc, 0); /* Don't need to set PACKET Offset bit,it's no use 512bytes of length */
+#else
+	SET_TX_DESC_PKT_OFFSET_8821C(desc, 1);
+#endif
+
+	if (bmcast)
+		SET_TX_DESC_BMC_8821C(desc, 1);
+
+	SET_TX_DESC_MACID_8821C(desc, attrib->mac_id);
+	SET_TX_DESC_RATE_ID_8821C(desc, attrib->raid);
+	SET_TX_DESC_QSEL_8821C(desc, attrib->qsel);
+
+	if (pmp_priv->preamble)
+		SET_TX_DESC_DATA_SHORT_8821C(desc, 1);
+
+	if (!attrib->qos_en)
+		SET_TX_DESC_EN_HWSEQ_8821C(desc, 1);
+	else
+		SET_TX_DESC_SW_SEQ_8821C(desc, attrib->seqnum);
+
+	if (pmp_priv->bandwidth <= CHANNEL_WIDTH_160)
+		SET_TX_DESC_DATA_BW_8821C(desc, pmp_priv->bandwidth);
+	else {
+		RTW_INFO("%s: <ERROR> unknown bandwidth %d, use 20M\n",
+			 __FUNCTION__, pmp_priv->bandwidth);
+		SET_TX_DESC_DATA_BW_8821C(desc, CHANNEL_WIDTH_20);
+	}
+
+	SET_TX_DESC_DISDATAFB_8821C(desc, 1);
+	SET_TX_DESC_USE_RATE_8821C(desc, 1);
+	SET_TX_DESC_DATARATE_8821C(desc, pmp_priv->rateidx);
+}
+#endif /* CONFIG_MP_INCLUDED */
+
+#define OFFSET_SZ	0
+static void fill_default_txdesc(struct xmit_frame *pxmitframe, u8 *pbuf)
+{
+	PADAPTER adapter = pxmitframe->padapter;
+	HAL_DATA_TYPE *phal_data = GET_HAL_DATA(adapter);
+	struct mlme_ext_priv *pmlmeext = &adapter->mlmeextpriv;
+	struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
+	struct pkt_attrib *pattrib = &pxmitframe->attrib;
+	s32 bmcst = IS_MCAST(pattrib->ra);
+	u32 desc_size = 0;
+	u8 offset, pkt_offset = 0;
+#define RA_SW_DEFINE_CONT	0x01
+	u8	drv_fixed_reate = _FALSE;
+	u8 hw_port = rtw_hal_get_port(adapter);
+
+#if 0
+#ifndef CONFIG_USE_USB_BUFFER_ALLOC_TX
+	if (adapter->registrypriv.mp_mode == 0) {
+		if ((PACKET_OFFSET_SZ != 0) && (!bagg_pkt) &&
+		    (rtw_usb_bulk_size_boundary(adapter, TXDESC_SIZE + pattrib->last_txcmdsz) == _FALSE)) {
+			ptxdesc = (pmem + PACKET_OFFSET_SZ);
+			/* RTW_INFO("==> non-agg-pkt,shift pointer...\n"); */
+			pull = 1;
+		}
+	}
+#endif	/* CONFIG_USE_USB_BUFFER_ALLOC_TX*/
+#endif
+	rtw_halmac_get_tx_desc_size(adapter_to_dvobj(adapter), &desc_size);
+
+	_rtw_memset(pbuf, 0, desc_size);
+
+	/*SET_TX_DESC_LS_8821C(pbuf, 1);*/ /*for USB only*/
+
+	SET_TX_DESC_TXPKTSIZE_8821C(pbuf, pattrib->last_txcmdsz);
+
+	offset = desc_size + OFFSET_SZ;
+
+#ifdef CONFIG_TX_EARLY_MODE
+	if (pxmitframe->frame_tag == DATA_FRAMETAG)
+		if (bagg_pkt)
+			offset += EARLY_MODE_INFO_SIZE ;/*0x28	*/
+	pkt_offset = pxmitframe->pkt_offset = 0x01;
+#endif
+	SET_TX_DESC_OFFSET_8821C(pbuf, offset);
+
+	if (bmcst)
+		SET_TX_DESC_BMC_8821C(pbuf, 1);
+
+#if 0
+#ifndef CONFIG_USE_USB_BUFFER_ALLOC_TX
+	if (adapter->registrypriv.mp_mode == 0) {
+		if ((PACKET_OFFSET_SZ != 0) && (!bagg_pkt)) {
+			if ((pull) && (pxmitframe->pkt_offset > 0)) {
+				pxmitframe->pkt_offset = pxmitframe->pkt_offset - 1;
+				pkt_offset = pxmitframe->pkt_offset;
+			}
+		}
+	}
+	/*RTW_INFO("%s, pkt_offset=0x%02x\n", __func__, pxmitframe->pkt_offset);*/
+#endif
+#endif
+
+	/* pkt_offset, unit:8 bytes padding*/
+	if (pkt_offset > 0)
+		SET_TX_DESC_PKT_OFFSET_8821C(pbuf, pkt_offset);
+
+
+	SET_TX_DESC_MACID_8821C(pbuf, pattrib->mac_id);
+	SET_TX_DESC_RATE_ID_8821C(pbuf, pattrib->raid);
+	SET_TX_DESC_QSEL_8821C(pbuf, pattrib->qsel);
+
+	/* 2009.11.05. tynli_test. Suggested by SD4 Filen for FW LPS.
+	* (1) The sequence number of each non-Qos frame / broadcast / multicast /
+	* mgnt frame should be controled by Hw because Fw will also send null data
+	* which we cannot control when Fw LPS enable.
+	* --> default enable non-Qos data sequense number. 2010.06.23. by tynli.
+	* (2) Enable HW SEQ control for beacon packet, because we use Hw beacon.
+	* (3) Use HW Qos SEQ to control the seq num of Ext port non-Qos packets.
+	*/
+
+	/* HW sequence, to fix to use 0 queue. todo: 4AC packets to use auto queue select */
+	if (!pattrib->qos_en) {
+		SET_TX_DESC_DISQSELSEQ_8821C(pbuf, 1);
+		SET_TX_DESC_EN_HWSEQ_8821C(pbuf, 1);
+		SET_TX_DESC_HW_SSN_SEL_8821C(pbuf, pattrib->hw_ssn_sel);
+		SET_TX_DESC_EN_HWEXSEQ_8821C(pbuf, 0);
+	} else
+		SET_TX_DESC_SW_SEQ_8821C(pbuf, pattrib->seqnum);
+
+	if (pxmitframe->frame_tag == DATA_FRAMETAG) {
+
+		rtl8821c_fill_txdesc_sectype(pattrib, pbuf);
+
+#if defined(CONFIG_CONCURRENT_MODE)
+		if (bmcst)
+			fill_txdesc_force_bmc_camid(pattrib, pbuf);
+#endif
+
+#if defined(CONFIG_USB_TX_AGGREGATION) || defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
+		if (pxmitframe->agg_num > 1) {
+			/*RTW_INFO("%s agg_num:%d\n",__func__,pxmitframe->agg_num );*/
+			SET_TX_DESC_DMA_TXAGG_NUM_8821C(pbuf, pxmitframe->agg_num);
+		}
+#endif /*CONFIG_USB_TX_AGGREGATION*/
+
+		rtl8821c_fill_txdesc_vcs(adapter, pattrib, pbuf);
+
+#ifdef CONFIG_SUPPORT_DYNAMIC_TXPWR
+		rtw_phydm_set_dyntxpwr(adapter, pbuf, pattrib->mac_id);
+#endif
+		if ((pattrib->ether_type != 0x888e) &&
+		    (pattrib->ether_type != 0x0806) &&
+		    (pattrib->ether_type != 0x88B4) &&
+		    (pattrib->dhcp_pkt != 1)
+#ifdef CONFIG_AUTO_AP_MODE
+		    && (pattrib->pctrl != _TRUE)
+#endif
+		   ) {
+			/* Non EAP & ARP & DHCP type data packet */
+
+			if (pattrib->ampdu_en == _TRUE) {
+				SET_TX_DESC_AGG_EN_8821C(pbuf, 1);
+				SET_TX_DESC_MAX_AGG_NUM_8821C(pbuf, 0x1F);
+				SET_TX_DESC_AMPDU_DENSITY_8821C(pbuf, pattrib->ampdu_spacing);
+			} else
+				SET_TX_DESC_BK_8821C(pbuf, 1);
+
+			if (adapter->fix_bw != 0xFF)
+				pattrib->bwmode =  adapter->fix_bw;
+
+			rtl8821c_fill_txdesc_phy(adapter, pattrib, pbuf);
+
+			if (phal_data->current_band_type == BAND_ON_5G)/*Data Rate Fallback Limit rate*/
+				SET_TX_DESC_DATA_RTY_LOWEST_RATE_8821C(pbuf, 4);
+			else
+				SET_TX_DESC_DATA_RTY_LOWEST_RATE_8821C(pbuf, 0);
+
+			if (bmcst) {
+				drv_fixed_reate = _TRUE;
+				fill_txdesc_bmc_tx_rate(pattrib, pbuf);
+			}
+
+			/* modify data rate by iwpriv*/
+			if (adapter->fix_rate != 0xFF) {
+				drv_fixed_reate = _TRUE;
+				SET_TX_DESC_USE_RATE_8821C(pbuf, 1);
+
+				if (adapter->fix_rate & BIT(7))
+					SET_TX_DESC_DATA_SHORT_8821C(pbuf, 1);
+				SET_TX_DESC_DATARATE_8821C(pbuf, adapter->fix_rate & 0x7F);
+				if (!adapter->data_fb)
+					SET_TX_DESC_DISDATAFB_8821C(pbuf, 1);
+			}
+
+			if (pattrib->ldpc)
+				SET_TX_DESC_DATA_LDPC_8821C(pbuf, 1);
+			if (pattrib->stbc)
+				SET_TX_DESC_DATA_STBC_8821C(pbuf, 1);
+
+#ifdef CONFIG_CMCC_TEST
+			SET_TX_DESC_DATA_SHORT_8821C(pbuf, 1); /* use cck short premble */
+#endif
+
+#ifdef CONFIG_WMMPS_STA
+			if (pattrib->trigger_frame)
+				SET_TX_DESC_TRI_FRAME_8821C (pbuf, 1);
+#endif /* CONFIG_WMMPS_STA */
+		} else {
+
+			/*
+			 * EAP data packet and ARP packet.
+			 * Use the 1M data rate to send the EAP/ARP packet.
+			 * This will maybe make the handshake smooth.
+			 */
+			SET_TX_DESC_BK_8821C(pbuf, 1);
+			drv_fixed_reate = _TRUE;
+			SET_TX_DESC_USE_RATE_8821C(pbuf, 1);
+
+			/* HW will ignore this setting if the transmission rate is legacy OFDM.*/
+			if (pmlmeinfo->preamble_mode == PREAMBLE_SHORT)
+				SET_TX_DESC_DATA_SHORT_8821C(pbuf, 1);
+
+			SET_TX_DESC_DATARATE_8821C(pbuf, MRateToHwRate(pmlmeext->tx_rate));
+
+			RTW_INFO(FUNC_ADPT_FMT ": SP Packet(0x%04X) rate=0x%x\n",
+				FUNC_ADPT_ARG(adapter), pattrib->ether_type, MRateToHwRate(pmlmeext->tx_rate));
+		}
+#ifdef CONFIG_TDLS
+#ifdef CONFIG_XMIT_ACK
+		/* CCX-TXRPT ack for xmit mgmt frames. */
+		if (pxmitframe->ack_report) {
+#ifdef DBG_CCX
+			RTW_INFO("%s set spe_rpt\n", __func__);
+#endif
+			SET_TX_DESC_SPE_RPT_8821C(pbuf, 1);
+		}
+#endif /* CONFIG_XMIT_ACK */
+#endif
+
+	} else if (pxmitframe->frame_tag == MGNT_FRAMETAG) {
+		SET_TX_DESC_MBSSID_8821C(pbuf, pattrib->mbssid & 0xF);
+		SET_TX_DESC_USE_RATE_8821C(pbuf, 1);
+		drv_fixed_reate = _TRUE;
+
+		SET_TX_DESC_DATARATE_8821C(pbuf, MRateToHwRate(pattrib->rate));
+
+		/* VHT NDPA or HT NDPA Packet for Beamformer.*/
+#ifdef CONFIG_BEAMFORMING
+		if ((pattrib->subtype == WIFI_NDPA) ||
+		    ((pattrib->subtype == WIFI_ACTION_NOACK) && (pattrib->order == 1))) {
+			SET_TX_DESC_NAVUSEHDR_8821C(pbuf, 1);
+
+			SET_TX_DESC_DATA_BW_8821C(pbuf, rtl8821c_bw_mapping(adapter, pattrib));
+			/*SET_TX_DESC_DATA_SC_8821C(pbuf, rtl8821c_sc_mapping(adapter, pattrib));*/
+			SET_TX_DESC_SIGNALING_TA_PKT_SC_8821C(pbuf, rtl8821c_sc_mapping(adapter,pattrib));
+
+			SET_TX_DESC_RTY_LMT_EN_8821C(pbuf, 1);
+			SET_TX_DESC_RTS_DATA_RTY_LMT_8821C(pbuf, 5);
+			SET_TX_DESC_DISDATAFB_8821C(pbuf, 1);
+
+			/*if(pattrib->rts_cca)
+				SET_TX_DESC_NDPA_8821C(ptxdesc, 2);
+			else*/
+			SET_TX_DESC_NDPA_8821C(pbuf, 1);
+		} else
+#endif
+		{
+			SET_TX_DESC_RTY_LMT_EN_8821C(pbuf, 1);
+			if (pattrib->retry_ctrl == _TRUE)
+				SET_TX_DESC_RTS_DATA_RTY_LMT_8821C(pbuf, 6);
+			else
+				SET_TX_DESC_RTS_DATA_RTY_LMT_8821C(pbuf, 12);
+		}
+
+#ifdef CONFIG_XMIT_ACK
+		/* CCX-TXRPT ack for xmit mgmt frames. */
+		if (pxmitframe->ack_report) {
+#ifdef DBG_CCX
+			RTW_INFO("%s set spe_rpt\n", __func__);
+#endif
+			SET_TX_DESC_SPE_RPT_8821C(pbuf, 1);
+		}
+#endif /* CONFIG_XMIT_ACK */
+	} else if (pxmitframe->frame_tag == TXAGG_FRAMETAG)
+		RTW_INFO("%s: TXAGG_FRAMETAG\n", __func__);
+#ifdef CONFIG_MP_INCLUDED
+	else if (pxmitframe->frame_tag == MP_FRAMETAG) {
+		RTW_INFO("%s: MP_FRAMETAG\n", __func__);
+		fill_txdesc_for_mp(adapter, pbuf);
+	}
+#endif
+	else {
+		RTW_INFO("%s: frame_tag=0x%x\n", __func__, pxmitframe->frame_tag);
+
+		SET_TX_DESC_USE_RATE_8821C(pbuf, 1);
+		drv_fixed_reate = _TRUE;
+		SET_TX_DESC_DATARATE_8821C(pbuf, MRateToHwRate(pmlmeext->tx_rate));
+	}
+
+	if (drv_fixed_reate == _TRUE)
+		SET_TX_DESC_SW_DEFINE_8821C(pbuf, RA_SW_DEFINE_CONT);
+
+	if (adapter->power_offset != 0)
+		SET_TX_DESC_TXPWR_OFSET_8821C(pbuf, adapter->power_offset);
+
+#ifdef CONFIG_ANTENNA_DIVERSITY
+	if (!bmcst && pattrib->psta)
+		odm_set_tx_ant_by_tx_info(adapter_to_phydm(adapter), pbuf, pattrib->psta->cmn.mac_id);
+#endif
+
+#ifdef CONFIG_BEAMFORMING
+	SET_TX_DESC_G_ID_8821C(pbuf, pattrib->txbf_g_id);
+	SET_TX_DESC_P_AID_8821C(pbuf, pattrib->txbf_p_aid);
+#endif
+
+	SET_TX_DESC_PORT_ID_8821C(pbuf, hw_port);
+	SET_TX_DESC_MULTIPLE_PORT_8821C(pbuf, hw_port);
+}
+
+void rtl8821c_dbg_dump_tx_desc(PADAPTER adapter, int frame_tag, u8 *ptxdesc)
+{
+	u8 bDumpTxPkt;
+	u8 bDumpTxDesc = _FALSE;
+
+
+	rtw_hal_get_def_var(adapter, HAL_DEF_DBG_DUMP_TXPKT, &bDumpTxPkt);
+
+	/* 1 for data frame, 2 for mgnt frame */
+	if (bDumpTxPkt == 1) {
+		RTW_INFO("dump tx_desc for data frame\n");
+		if ((frame_tag & 0x0f) == DATA_FRAMETAG)
+			bDumpTxDesc = _TRUE;
+	} else if (bDumpTxPkt == 2) {
+		RTW_INFO("dump tx_desc for mgnt frame\n");
+		if ((frame_tag & 0x0f) == MGNT_FRAMETAG)
+			bDumpTxDesc = _TRUE;
+	}
+
+	/* 8821C TX SIZE = 48(HALMAC_TX_DESC_SIZE_8821C) */
+	if (_TRUE == bDumpTxDesc) {
+		RTW_INFO("=====================================\n");
+		RTW_INFO("Offset00(0x%08x)\n", *((u32 *)(ptxdesc)));
+		RTW_INFO("Offset04(0x%08x)\n", *((u32 *)(ptxdesc + 4)));
+		RTW_INFO("Offset08(0x%08x)\n", *((u32 *)(ptxdesc + 8)));
+		RTW_INFO("Offset12(0x%08x)\n", *((u32 *)(ptxdesc + 12)));
+		RTW_INFO("Offset16(0x%08x)\n", *((u32 *)(ptxdesc + 16)));
+		RTW_INFO("Offset20(0x%08x)\n", *((u32 *)(ptxdesc + 20)));
+		RTW_INFO("Offset24(0x%08x)\n", *((u32 *)(ptxdesc + 24)));
+		RTW_INFO("Offset28(0x%08x)\n", *((u32 *)(ptxdesc + 28)));
+		RTW_INFO("Offset32(0x%08x)\n", *((u32 *)(ptxdesc + 32)));
+		RTW_INFO("Offset36(0x%08x)\n", *((u32 *)(ptxdesc + 36)));
+		RTW_INFO("Offset40(0x%08x)\n", *((u32 *)(ptxdesc + 40)));
+		RTW_INFO("Offset44(0x%08x)\n", *((u32 *)(ptxdesc + 44)));
+		RTW_INFO("=====================================\n");
+	}
+}
+
+/*
+ * Description:
+ *
+ * Parameters:
+ *	pxmitframe	xmitframe
+ *	pbuf		where to fill tx desc
+ */
+void rtl8821c_update_txdesc(struct xmit_frame *pxmitframe, u8 *pbuf)
+{
+	fill_default_txdesc(pxmitframe, pbuf);
+	rtl8821c_cal_txdesc_chksum(pxmitframe->padapter, pbuf);
+	rtl8821c_dbg_dump_tx_desc(pxmitframe->padapter, pxmitframe->frame_tag, pbuf);
+}
+
+/*
+ * Description:
+ *	In normal chip, we should send some packet to HW which will be used by FW
+ *	in FW LPS mode.
+ *	The function is to fill the Tx descriptor of this packets,
+ *	then FW can tell HW to send these packet directly.
+ */
+static void fill_fake_txdesc(PADAPTER adapter, u8 *pDesc, u32 BufferLen,
+			     u8 IsPsPoll, u8 IsBTQosNull, u8 bDataFrame)
+{
+	struct mlme_ext_priv	*pmlmeext = &adapter->mlmeextpriv;
+	struct xmit_priv		*pxmitpriv = &adapter->xmitpriv;
+	u32 desc_size = 0;
+	u8 hw_port = rtw_hal_get_port(adapter);
+
+	rtw_halmac_get_tx_desc_size(adapter_to_dvobj(adapter), &desc_size);
+
+	/* Clear all status */
+	_rtw_memset(pDesc, 0, desc_size);
+
+	SET_TX_DESC_LS_8821C(pDesc, 1);
+
+	SET_TX_DESC_OFFSET_8821C(pDesc, desc_size);
+
+	SET_TX_DESC_TXPKTSIZE_8821C(pDesc, BufferLen);
+	SET_TX_DESC_QSEL_8821C(pDesc, QSLT_MGNT); /* Fixed queue of Mgnt queue */
+
+	if (pmlmeext->cur_wireless_mode & WIRELESS_11B)
+		SET_TX_DESC_RATE_ID_8821C(pDesc, RATEID_IDX_B);
+	else
+		SET_TX_DESC_RATE_ID_8821C(pDesc, RATEID_IDX_G);
+
+	/* Set NAVUSEHDR to prevent Ps-poll AId filed to be changed to error vlaue by HW */
+	if (_TRUE == IsPsPoll)
+		SET_TX_DESC_NAVUSEHDR_8821C(pDesc, 1);
+	else {
+		SET_TX_DESC_DISQSELSEQ_8821C(pDesc, 1);
+		SET_TX_DESC_EN_HWSEQ_8821C(pDesc, 1);
+		SET_TX_DESC_HW_SSN_SEL_8821C(pDesc, pxmitpriv->hw_ssn_seq_no);/*pattrib->hw_ssn_sel*/
+		SET_TX_DESC_EN_HWEXSEQ_8821C(pDesc, 0);
+	}
+
+	if (_TRUE == IsBTQosNull)
+		SET_TX_DESC_BT_NULL_8821C(pDesc, 1);
+
+	SET_TX_DESC_USE_RATE_8821C(pDesc, 1);
+	SET_TX_DESC_DATARATE_8821C(pDesc, MRateToHwRate(pmlmeext->tx_rate));
+
+#ifdef CONFIG_MCC_MODE
+	/* config Null data retry number */
+	if (IsPsPoll == _FALSE && IsBTQosNull == _FALSE && bDataFrame == _FALSE) {
+		if (rtw_hal_check_mcc_status(adapter, MCC_STATUS_PROCESS_MCC_START_SETTING)) {
+			u8 rty_num = adapter->mcc_adapterpriv.null_rty_num;
+			if (rty_num != 0) {
+				SET_TX_DESC_RTY_LMT_EN_8821C(pDesc, 1);
+				SET_TX_DESC_RTS_DATA_RTY_LMT_8821C(pDesc, rty_num);
+			}
+		}
+	}
+#endif
+
+	/*
+	 * Encrypt the data frame if under security mode excepct null data.
+	 */
+	if (_TRUE == bDataFrame) {
+		u32 EncAlg;
+
+		EncAlg = adapter->securitypriv.dot11PrivacyAlgrthm;
+		switch (EncAlg) {
+		case _NO_PRIVACY_:
+			SET_TX_DESC_SEC_TYPE_8821C(pDesc, 0x0);
+			break;
+		case _WEP40_:
+		case _WEP104_:
+		case _TKIP_:
+			SET_TX_DESC_SEC_TYPE_8821C(pDesc, 0x1);
+			break;
+		case _SMS4_:
+			SET_TX_DESC_SEC_TYPE_8821C(pDesc, 0x2);
+			break;
+		case _AES_:
+			SET_TX_DESC_SEC_TYPE_8821C(pDesc, 0x3);
+			break;
+		default:
+			SET_TX_DESC_SEC_TYPE_8821C(pDesc, 0x0);
+			break;
+		}
+	}
+	SET_TX_DESC_PORT_ID_8821C(pDesc, hw_port);
+	SET_TX_DESC_MULTIPLE_PORT_8821C(pDesc, hw_port);
+
+#if defined(CONFIG_USB_HCI) || defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
+	/*
+	 * USB interface drop packet if the checksum of descriptor isn't correct.
+	 * Using this checksum can let hardware recovery from packet bulk out error (e.g. Cancel URC, Bulk out error.).
+	 */
+	rtl8821c_cal_txdesc_chksum(adapter, pDesc);
+#endif
+}
+
+void rtl8821c_rxdesc2attribute(struct rx_pkt_attrib *pattrib, u8 *desc)
+{
+	/* initial value */
+	_rtw_memset(pattrib, 0, sizeof(struct rx_pkt_attrib));
+
+	pattrib->pkt_len = (u16)GET_RX_DESC_PKT_LEN_8821C(desc);
+	pattrib->pkt_rpt_type = (GET_RX_DESC_C2H_8821C(desc)) ? C2H_PACKET : NORMAL_RX;
+
+	if (pattrib->pkt_rpt_type == NORMAL_RX) {
+		/* Get from RX DESC */
+		pattrib->crc_err = (u8)GET_RX_DESC_CRC32_8821C(desc);
+		pattrib->icv_err = (u8)GET_RX_DESC_ICV_ERR_8821C(desc);
+
+		pattrib->drvinfo_sz = (u8)GET_RX_DESC_DRV_INFO_SIZE_8821C(desc) << 3;
+		pattrib->encrypt = (u8)GET_RX_DESC_SECURITY_8821C(desc);
+		pattrib->qos = (u8)GET_RX_DESC_QOS_8821C(desc);
+		pattrib->shift_sz = (u8)GET_RX_DESC_SHIFT_8821C(desc);
+		pattrib->physt = (u8)GET_RX_DESC_PHYST_8821C(desc);
+		pattrib->bdecrypted = (u8)GET_RX_DESC_SWDEC_8821C(desc) ? 0 : 1;
+
+		pattrib->priority = (u8)GET_RX_DESC_TID_8821C(desc);
+		pattrib->amsdu = (u8)GET_RX_DESC_AMSDU_8821C(desc);
+		pattrib->mdata = (u8)GET_RX_DESC_MD_8821C(desc);
+		pattrib->mfrag = (u8)GET_RX_DESC_MF_8821C(desc);
+
+		pattrib->seq_num = (u16)GET_RX_DESC_SEQ_8821C(desc);
+		pattrib->frag_num = (u8)GET_RX_DESC_FRAG_8821C(desc);
+		pattrib->ppdu_cnt = (u8)GET_RX_DESC_PPDU_CNT_8821C(desc);
+		pattrib->free_cnt = (u32)GET_RX_DESC_TSFL_8821C(desc);
+
+		pattrib->bw = CHANNEL_WIDTH_MAX;
+		pattrib->data_rate = (u8)GET_RX_DESC_RX_RATE_8821C(desc);
+	}
+}
+
+void rtl8821c_query_rx_desc(union recv_frame *precvframe, u8 *pdesc)
+{
+	rtl8821c_rxdesc2attribute(&precvframe->u.hdr.attrib, pdesc);
+}
+
+static void InitBeaconParameters(PADAPTER adapter)
+{
+	PHAL_DATA_TYPE hal = GET_HAL_DATA(adapter);
+
+	/* TBTT setup time */
+	rtw_write8(adapter, REG_TBTT_PROHIBIT_8821C, TBTT_PROHIBIT_SETUP_TIME);
+
+	/* TBTT hold time: 0x540[19:8] */
+	rtw_write8(adapter, REG_TBTT_PROHIBIT_8821C + 1, TBTT_PROHIBIT_HOLD_TIME_STOP_BCN & 0xFF);
+	rtw_write8(adapter, REG_TBTT_PROHIBIT_8821C + 2,
+		(rtw_read8(adapter, REG_TBTT_PROHIBIT_8821C + 2) & 0xF0) | (TBTT_PROHIBIT_HOLD_TIME_STOP_BCN >> 8));
+
+	rtw_write8(adapter, REG_DRVERLYINT_8821C, DRIVER_EARLY_INT_TIME_8821C); /* 5ms */
+	rtw_write8(adapter, REG_BCNDMATIM_8821C, BCN_DMA_ATIME_INT_TIME_8821C); /* 2ms */
+
+	/*
+	 * Suggested by designer timchen. Change beacon AIFS to the largest number
+	 * beacause test chip does not contension before sending beacon.
+	 */
+	rtw_write16(adapter, REG_BCNTCFG_8821C, 0x4413);
+}
+
+static void beacon_function_enable(PADAPTER adapter, u8 Enable, u8 Linked)
+{
+	hw_bcn_ctrl_add(adapter, get_hw_port(adapter), BIT_DIS_TSF_UDT_8821C | BIT_EN_BCN_FUNCTION_8821C);
+}
+
+static void set_beacon_related_registers(PADAPTER adapter)
+{
+	struct mlme_ext_priv *pmlmeext = &adapter->mlmeextpriv;
+	struct mlme_ext_info *pmlmeinfo = &pmlmeext->mlmext_info;
+
+	/* reset TSF, enable update TSF, correcting TSF On Beacon */
+#if 0
+	/* * REG_MBSSID_BCN_SPACE */
+	/* * REG_BCNDMATIM */
+	/* * REG_ATIMWND */
+	/* * REG_TBTT_PROHIBIT */
+	/* * REG_DRVERLYINT */
+	/* * REG_BCN_MAX_ERR */
+	/* * REG_BCNTCFG  (0x510) */
+	/* * REG_DUAL_TSF_RST */
+	/* * REG_BCN_CTRL  (0x550) */
+#endif
+
+	/* ATIM window */
+	rtw_write16(adapter, REG_ATIMWND_8821C, 2);
+
+	/* Beacon interval (in unit of TU). */
+	rtw_hal_set_hwreg(adapter, HW_VAR_BEACON_INTERVAL, (u8 *)&pmlmeinfo->bcn_interval);
+
+	InitBeaconParameters(adapter);
+
+	rtw_write8(adapter, REG_SLOT_8821C, 0x09);
+
+	/* Reset TSF Timer to zero */
+	hw_tsf_reset(adapter);
+
+	rtw_write8(adapter, REG_RXTSF_OFFSET_CCK_8821C, 0x50);
+	rtw_write8(adapter, REG_RXTSF_OFFSET_OFDM_8821C, 0x50);
+
+	beacon_function_enable(adapter, _TRUE, _TRUE);
+
+	ResumeTxBeacon(adapter);
+}
+
+void rtl8821c_set_hal_ops(PADAPTER adapter)
+{
+	struct hal_ops *ops_func = &adapter->hal_func;
+
+	/*** initialize section ***/
+	ops_func->read_chip_version = read_chip_version;
+	/*
+		ops->init_default_value = NULL;
+	*/
+	ops_func->read_adapter_info = rtl8821c_read_efuse;
+	ops_func->hal_power_on = rtl8821c_power_on;
+	ops_func->hal_power_off = rtl8821c_power_off;
+
+	ops_func->dm_init = rtl8821c_phy_init_dm_priv;
+	ops_func->dm_deinit = rtl8821c_phy_deinit_dm_priv;
+
+	/*** xmit section ***/
+	/*
+		ops->init_xmit_priv = NULL;
+		ops->free_xmit_priv = NULL;
+		ops->hal_xmit = NULL;
+		ops->mgnt_xmit = NULL;
+		ops->hal_xmitframe_enqueue = NULL;
+	#ifdef CONFIG_XMIT_THREAD_MODE
+		ops->xmit_thread_handler = NULL;
+	#endif
+	*/
+	/*
+		ops_func->run_thread = rtl8821c_run_thread;
+		ops_func->cancel_thread = rtl8821c_cancel_thread;
+	*/
+	/*** recv section ***/
+	/*
+		ops->init_recv_priv = NULL;
+		ops->free_recv_priv = NULL;
+	#if defined(CONFIG_USB_HCI) || defined(CONFIG_PCI_HCI)
+		ops->inirp_init = NULL;
+		ops->inirp_deinit = NULL;
+	#endif
+	*/
+	/*** interrupt hdl section ***/
+	/*
+		ops->enable_interrupt = NULL;
+		ops->disable_interrupt = NULL;
+	*/
+	ops_func->check_ips_status = check_ips_status;
+	/*
+	#if defined(CONFIG_PCI_HCI)
+		ops->interrupt_handler = NULL;
+	#endif
+	#if defined(CONFIG_USB_HCI) && defined(CONFIG_SUPPORT_USB_INT)
+		ops->interrupt_handler = NULL;
+	#endif
+	#if defined(CONFIG_PCI_HCI)
+		ops->irp_reset = NULL;
+	#endif
+	*/
+
+	/*** DM section ***/
+	ops_func->set_chnl_bw_handler = rtl8821c_set_channel_bw;
+
+	ops_func->set_tx_power_level_handler = rtl8821c_set_tx_power_level;
+	ops_func->get_tx_power_level_handler = rtl8821c_get_tx_power_level;
+
+	ops_func->set_tx_power_index_handler = rtl8821c_set_tx_power_index;
+	ops_func->get_tx_power_index_handler = rtl8821c_get_tx_power_index;
+
+	ops_func->hal_dm_watchdog = rtl8821c_phy_haldm_watchdog;
+
+	ops_func->GetHalODMVarHandler = GetHalODMVar;
+	ops_func->SetHalODMVarHandler = SetHalODMVar;
+
+	ops_func->SetBeaconRelatedRegistersHandler = set_beacon_related_registers;
+
+#ifdef CONFIG_ANTENNA_DIVERSITY
+	/*
+		ops->AntDivBeforeLinkHandler = NULL;
+		ops->AntDivCompareHandler = NULL;
+	*/
+#endif
+	/*
+		ops->interface_ps_func = NULL;
+	*/
+
+	ops_func->read_bbreg = rtl8821c_read_bb_reg;
+	ops_func->write_bbreg = rtl8821c_write_bb_reg;
+	ops_func->read_rfreg = rtl8821c_read_rf_reg;
+	ops_func->write_rfreg = rtl8821c_write_rf_reg;
+	ops_func->read_wmmedca_reg = rtl8821c_read_wmmedca_reg;
+
+#ifdef CONFIG_HOSTAPD_MLME
+	/*
+		ops->hostap_mgnt_xmit_entry = NULL;
+	*/
+#endif
+	/*
+		ops->EfusePowerSwitch = NULL;
+		ops->BTEfusePowerSwitch = NULL;
+		ops->ReadEFuse = NULL;
+		ops->EFUSEGetEfuseDefinition = NULL;
+		ops->EfuseGetCurrentSize = NULL;
+		ops->Efuse_PgPacketRead = NULL;
+		ops->Efuse_PgPacketWrite = NULL;
+		ops->Efuse_WordEnableDataWrite = NULL;
+		ops->Efuse_PgPacketWrite_BT = NULL;
+	*/
+#ifdef DBG_CONFIG_ERROR_DETECT
+	ops_func->sreset_init_value = sreset_init_value;
+	ops_func->sreset_reset_value = sreset_reset_value;
+	ops_func->silentreset = sreset_reset;
+	ops_func->sreset_xmit_status_check = xmit_status_check;
+	ops_func->sreset_linked_status_check  = linked_status_check;
+	ops_func->sreset_get_wifi_status  = sreset_get_wifi_status;
+	ops_func->sreset_inprogress = sreset_inprogress;
+#endif /* DBG_CONFIG_ERROR_DETECT */
+
+#ifdef CONFIG_IOL
+	/*
+		ops->IOL_exec_cmds_sync = NULL;
+	*/
+#endif
+
+	ops_func->hal_notch_filter = rtl8821c_notch_filter_switch;
+	ops_func->hal_mac_c2h_handler = c2h_handler_rtl8821c;
+	ops_func->fill_h2c_cmd = rtl8821c_fillh2ccmd;
+	ops_func->fill_fake_txdesc = fill_fake_txdesc;
+	ops_func->fw_dl = rtl8821c_fw_dl;
+
+#ifdef CONFIG_LPS_PG
+	ops_func->fw_mem_dl = rtl8821c_fw_mem_dl;
+#endif
+#if defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN)
+	/*
+		ops->clear_interrupt = NULL;
+	*/
+#endif
+	/*
+		ops_func->hal_get_tx_buff_rsvd_page_num = NULL;
+	*/
+#ifdef CONFIG_GPIO_API
+	/*
+		ops->update_hisr_hsisr_ind = NULL;
+	*/
+#endif
+
+	/* HALMAC related functions */
+	ops_func->init_mac_register = rtl8821c_init_phy_parameter_mac;
+	ops_func->init_phy = rtl8821c_phy_init;
+
+}
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/hal/rtl8821c/rtl8821c_phy.c linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/rtl8821c/rtl8821c_phy.c
--- linux-5.6.3/3rdparty/rtl8821ce/hal/rtl8821c/rtl8821c_phy.c	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/hal/rtl8821c/rtl8821c_phy.c	2020-04-10 16:35:06.844661375 +0300
@@ -0,0 +1,1457 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2016 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#define _RTL8821C_PHY_C_
+
+#include <hal_data.h>		/* HAL_DATA_TYPE */
+#include "../hal_halmac.h"	/* REG_CCK_CHECK_8821C */
+#include "rtl8821c.h"
+
+
+/*
+ * Description:
+ *	Initialize Register definition offset for Radio Path A/B/C/D
+ *	The initialization value is constant and it should never be changes
+ */
+static void bb_rf_register_definition(PADAPTER adapter)
+{
+	PHAL_DATA_TYPE hal = GET_HAL_DATA(adapter);
+
+
+	/* RF Interface Sowrtware Control */
+	hal->PHYRegDef[RF_PATH_A].rfintfs = rFPGA0_XAB_RFInterfaceSW;
+	hal->PHYRegDef[RF_PATH_B].rfintfs = rFPGA0_XAB_RFInterfaceSW;
+
+	/* RF Interface Output (and Enable) */
+	hal->PHYRegDef[RF_PATH_A].rfintfo = rFPGA0_XA_RFInterfaceOE;
+	hal->PHYRegDef[RF_PATH_B].rfintfo = rFPGA0_XB_RFInterfaceOE;
+
+	/* RF Interface (Output and) Enable */
+	hal->PHYRegDef[RF_PATH_A].rfintfe = rFPGA0_XA_RFInterfaceOE;
+	hal->PHYRegDef[RF_PATH_B].rfintfe = rFPGA0_XB_RFInterfaceOE;
+
+	hal->PHYRegDef[RF_PATH_A].rf3wireOffset = rA_LSSIWrite_Jaguar;
+	hal->PHYRegDef[RF_PATH_B].rf3wireOffset = rB_LSSIWrite_Jaguar;
+
+	hal->PHYRegDef[RF_PATH_A].rfHSSIPara2 = rHSSIRead_Jaguar;
+	hal->PHYRegDef[RF_PATH_B].rfHSSIPara2 = rHSSIRead_Jaguar;
+
+	/* Tranceiver Readback LSSI/HSPI mode */
+	hal->PHYRegDef[RF_PATH_A].rfLSSIReadBack = rA_SIRead_Jaguar;
+	hal->PHYRegDef[RF_PATH_B].rfLSSIReadBack = rB_SIRead_Jaguar;
+	hal->PHYRegDef[RF_PATH_A].rfLSSIReadBackPi = rA_PIRead_Jaguar;
+	hal->PHYRegDef[RF_PATH_B].rfLSSIReadBackPi = rB_PIRead_Jaguar;
+}
+
+static void init_bb_rf(PADAPTER adapter)
+{
+	u8 val8;
+	u16 val16;
+
+
+	/* Enable BB and RF */
+	val8 = rtw_read8(adapter, REG_SYS_FUNC_EN_8821C);
+	if (IS_HARDWARE_TYPE_8821CU(adapter))
+		val8 |= BIT_FEN_USBA_8821C;
+	else if (IS_HARDWARE_TYPE_8821CE(adapter))
+		val8 |= BIT_FEN_PCIEA_8821C;
+	rtw_write8(adapter, REG_SYS_FUNC_EN_8821C, val8);
+
+	/*
+	 * 8821C MP Chip => Reset BB/RF ??
+	 * Need to set BBRSTB and GLB_RSTB = 1->0->1 to generate a postive edge and negtive edge for BB
+	 */
+	val8 |= BIT_FEN_BB_GLB_RSTN_8821C | BIT_FEN_BBRSTB_8821C;
+	rtw_write8(adapter, REG_SYS_FUNC_EN_8821C, val8);
+	val8 &= ~(BIT_FEN_BB_GLB_RSTN_8821C | BIT_FEN_BBRSTB_8821C);
+	rtw_write8(adapter, REG_SYS_FUNC_EN_8821C, val8);
+	val8 |= BIT_FEN_BB_GLB_RSTN_8821C | BIT_FEN_BBRSTB_8821C;
+	rtw_write8(adapter, REG_SYS_FUNC_EN_8821C, val8);
+
+	val8 = BIT_RF_EN_8821C | BIT_RF_RSTB_8821C | BIT_RF_SDMRSTB_8821C;
+	/* 0x1F[7:0] = 0x07 PathA RF Power On */
+	rtw_write8(adapter, REG_RF_CTRL_8821C, val8);
+	rtw_usleep_os(10);
+
+	/*0xEC [31:24],BIT_WLRF1_CTRL,	For WLRF1 control*/
+	/* 0xEF[7:0] = 0x07 for RFE Type=2,BTG RF Power On*/
+	rtw_write8(adapter, REG_WLRF1_8821C + 3, val8);
+	rtw_usleep_os(10);
+
+}
+
+u8 rtl8821c_init_phy_parameter_mac(PADAPTER adapter)
+{
+	u8 ret = _FAIL;
+	PHAL_DATA_TYPE hal;
+
+	hal = GET_HAL_DATA(adapter);
+
+#ifdef CONFIG_LOAD_PHY_PARA_FROM_FILE
+	ret = phy_ConfigMACWithParaFile(adapter, PHY_FILE_MAC_REG);
+	if (ret == _FAIL)
+#endif /* CONFIG_LOAD_PHY_PARA_FROM_FILE */
+	{
+		odm_config_mac_with_header_file(&hal->odmpriv);
+		ret = _SUCCESS;
+	}
+
+	return ret;
+}
+
+static u8 _init_phy_parameter_bb(PADAPTER Adapter)
+{
+	PHAL_DATA_TYPE hal = GET_HAL_DATA(Adapter);
+	u8 ret = _TRUE;
+	int res;
+	enum hal_status status;
+
+
+	/*
+	 * 1. Read PHY_REG.TXT BB INIT!!
+	 */
+#ifdef CONFIG_LOAD_PHY_PARA_FROM_FILE
+	res = phy_ConfigBBWithParaFile(Adapter, PHY_FILE_PHY_REG, CONFIG_BB_PHY_REG);
+	if (res == _FAIL)
+#endif
+	{
+		ret = _FALSE;
+		status = odm_config_bb_with_header_file(&hal->odmpriv, CONFIG_BB_PHY_REG);
+		if (HAL_STATUS_SUCCESS == status)
+			ret = _TRUE;
+	}
+
+	if (ret != _TRUE) {
+		RTW_INFO("%s: Write BB Reg Fail!!", __FUNCTION__);
+		goto exit;
+	}
+
+#ifdef CONFIG_MP_INCLUDED
+	if (Adapter->registrypriv.mp_mode == 1) {
+		/*
+		 * 1.1 Read PHY_REG_MP.TXT BB INIT!!
+		 */
+#ifdef CONFIG_LOAD_PHY_PARA_FROM_FILE
+		res = phy_ConfigBBWithMpParaFile(Adapter, PHY_FILE_PHY_REG_MP);
+		if (res == _FAIL)
+#endif
+		{
+			ret = _FALSE;
+			status = odm_config_bb_with_header_file(&hal->odmpriv, CONFIG_BB_PHY_REG_MP);
+			if (HAL_STATUS_SUCCESS == status)
+				ret = _TRUE;
+		}
+
+		if (ret != _TRUE) {
+			RTW_INFO("%s : Write BB Reg MP Fail!!", __FUNCTION__);
+			goto exit;
+		}
+	}
+#endif /* CONFIG_MP_INCLUDED */
+
+	/*
+	 * 2. Read BB AGC table Initialization
+	 */
+#ifdef CONFIG_LOAD_PHY_PARA_FROM_FILE
+	res = phy_ConfigBBWithParaFile(Adapter, PHY_FILE_AGC_TAB, CONFIG_BB_AGC_TAB);
+	if (res == _FAIL)
+#endif
+	{
+		ret = _FALSE;
+		status = odm_config_bb_with_header_file(&hal->odmpriv, CONFIG_BB_AGC_TAB);
+		if (HAL_STATUS_SUCCESS == status)
+			ret = _TRUE;
+	}
+
+	if (ret != _TRUE) {
+		RTW_INFO("%s: AGC Table Fail\n", __FUNCTION__);
+		goto exit;
+	}
+
+exit:
+	return ret;
+}
+
+static u8 init_bb_reg(PADAPTER adapter)
+{
+	u8 ret = _TRUE;
+	PHAL_DATA_TYPE hal = GET_HAL_DATA(adapter);
+
+
+	/*
+	 * Config BB and AGC
+	 */
+	ret = _init_phy_parameter_bb(adapter);
+
+	hal_set_crystal_cap(adapter, hal->crystal_cap);
+
+	phy_set_bb_reg(adapter, rCCK0_FalseAlarmReport, BIT18 | BIT22, 0);
+	return ret;
+}
+
+static u8 _init_phy_parameter_rf(PADAPTER adapter)
+{
+	u32 val32 = 0;
+	enum rf_path eRFPath;
+	PBB_REGISTER_DEFINITION_T pPhyReg;
+	PHAL_DATA_TYPE hal = GET_HAL_DATA(adapter);
+	enum hal_status status;
+	int res;
+	u8 ret = _TRUE;
+
+
+	/*
+	 * Initialize RF
+	 */
+	for (eRFPath = RF_PATH_A; eRFPath < hal->NumTotalRFPath; eRFPath++) {
+		pPhyReg = &hal->PHYRegDef[eRFPath];
+
+		/* Initialize RF from configuration file */
+		switch (eRFPath) {
+		case RF_PATH_A:
+#ifdef CONFIG_LOAD_PHY_PARA_FROM_FILE
+			res = PHY_ConfigRFWithParaFile(adapter, PHY_FILE_RADIO_A, eRFPath);
+			if (res == _FAIL)
+#endif
+			{
+				ret = _FALSE;
+				status = odm_config_rf_with_header_file(&hal->odmpriv, CONFIG_RF_RADIO, eRFPath);
+				if (HAL_STATUS_SUCCESS == status)
+					ret = _TRUE;
+			}
+			break;
+		case RF_PATH_B:
+#ifdef CONFIG_LOAD_PHY_PARA_FROM_FILE
+			res = PHY_ConfigRFWithParaFile(adapter, PHY_FILE_RADIO_B, eRFPath);
+			if (res == _FAIL)
+#endif
+			{
+				ret = _FALSE;
+				status = odm_config_rf_with_header_file(&hal->odmpriv, CONFIG_RF_RADIO, eRFPath);
+				if (HAL_STATUS_SUCCESS == status)
+					ret = _TRUE;
+			}
+			break;
+		default:
+			RTW_INFO("Unknown RF path!! %d\r\n", eRFPath);
+			break;
+		}
+
+		if (ret != _TRUE)
+			goto exit;
+	}
+
+	/*
+	 * Configuration of Tx Power Tracking
+	 */
+#ifdef CONFIG_LOAD_PHY_PARA_FROM_FILE
+	res = PHY_ConfigRFWithTxPwrTrackParaFile(adapter, PHY_FILE_TXPWR_TRACK);
+	if (res == _FAIL)
+#endif
+	{
+		ret = _FALSE;
+		status = odm_config_rf_with_tx_pwr_track_header_file(&hal->odmpriv);
+		if (HAL_STATUS_SUCCESS == status)
+			ret = _TRUE;
+	}
+	if (ret != _TRUE)
+		goto exit;
+
+exit:
+	return ret;
+}
+
+static u8 init_rf_reg(PADAPTER adapter)
+{
+	u8 ret = _TRUE;
+
+
+	ret = _init_phy_parameter_rf(adapter);
+
+	return ret;
+}
+u8 rtl8821c_phy_init(PADAPTER adapter)
+{
+	PHAL_DATA_TYPE hal = GET_HAL_DATA(adapter);
+	struct dm_struct *phydm = &hal->odmpriv;
+
+	bb_rf_register_definition(adapter);
+
+	init_bb_rf(adapter);
+
+	if (_FALSE == config_phydm_parameter_init_8821c(phydm, ODM_PRE_SETTING))
+		return _FALSE;
+
+	if (_FALSE == init_bb_reg(adapter))
+		return _FALSE;
+
+	if (_FALSE == init_rf_reg(adapter))
+		return _FALSE;
+
+#if 0
+	if (_FALSE = config_phydm_trx_mode_8821c(phydm, ODM_RF_A, ODM_RF_A, FALSE))
+		return _FALSE;
+#endif
+
+	if (_FALSE ==  config_phydm_parameter_init_8821c(phydm, ODM_POST_SETTING))
+		return _FALSE;
+
+	hal->phy_spec.trx_cap = query_phydm_trx_capability(phydm);
+	hal->phy_spec.stbc_cap = query_phydm_stbc_capability(phydm);
+	hal->phy_spec.ldpc_cap = query_phydm_ldpc_capability(phydm);
+	hal->phy_spec.txbf_param = query_phydm_txbf_parameters(phydm);
+	hal->phy_spec.txbf_cap = query_phydm_txbf_capability(phydm);
+	/*rtw_dump_phy_cap(RTW_DBGDUMP, adapter);*/
+	return _TRUE;
+}
+
+static u32 phy_calculatebitshift(u32 mask)
+{
+	u32 i;
+
+
+	for (i = 0; i <= 31; i++)
+		if (mask & BIT(i))
+			break;
+
+	return i;
+}
+
+u32 rtl8821c_read_bb_reg(PADAPTER adapter, u32 addr, u32 mask)
+{
+	u32 val = 0, val_org, shift;
+
+
+#if (DISABLE_BB_RF == 1)
+	return 0;
+#endif
+
+	val_org = rtw_read32(adapter, addr);
+	shift = phy_calculatebitshift(mask);
+	val = (val_org & mask) >> shift;
+
+	return val;
+}
+
+void rtl8821c_write_bb_reg(PADAPTER adapter, u32 addr, u32 mask, u32 val)
+{
+	u32 val_org, shift;
+
+
+#if (DISABLE_BB_RF == 1)
+	return;
+#endif
+
+	if (mask != 0xFFFFFFFF) {
+		/* not "double word" write */
+		val_org = rtw_read32(adapter, addr);
+		shift = phy_calculatebitshift(mask);
+		val = ((val_org & (~mask)) | ((val << shift) & mask));
+	}
+
+	rtw_write32(adapter, addr, val);
+}
+
+u32 rtl8821c_read_rf_reg(PADAPTER adapter, enum rf_path path, u32 addr, u32 mask)
+{
+	struct dm_struct *phydm = adapter_to_phydm(adapter);
+	u32 val = 0;
+
+	val = config_phydm_read_rf_reg_8821c(phydm, path, addr, mask);
+	if (!config_phydm_read_rf_check_8821c(val))
+		RTW_INFO(FUNC_ADPT_FMT ": read RF reg path=%d addr=0x%x mask=0x%x FAIL!\n",
+			 FUNC_ADPT_ARG(adapter), path, addr, mask);
+	return val;
+}
+
+void rtl8821c_write_rf_reg(PADAPTER adapter, enum rf_path path, u32 addr, u32 mask, u32 val)
+{
+	struct dm_struct *phydm = adapter_to_phydm(adapter);
+	u8 ret;
+
+	ret = config_phydm_write_rf_reg_8821c(phydm, path, addr, mask, val);
+	if (_FALSE == ret)
+		RTW_INFO(FUNC_ADPT_FMT ": write RF reg path=%d addr=0x%x mask=0x%x val=0x%x FAIL!\n",
+			 FUNC_ADPT_ARG(adapter), path, addr, mask, val);
+
+}
+
+void rtl8821c_set_tx_power_level(PADAPTER adapter, u8 channel)
+{
+	u8 path = RF_PATH_A;
+	struct dm_struct *phydm = adapter_to_phydm(adapter);
+	PHAL_DATA_TYPE hal = GET_HAL_DATA(adapter);
+	u8 under_survey_ch = phy_check_under_survey_ch(adapter);
+	u8 under_24g = (hal->current_band_type == BAND_ON_2_4G);
+
+	/*((hal->RFEType == 2) || (hal->RFEType == 4) || (hal->RFEType == 7))*/
+	if ((channel <= 14) && (SWITCH_TO_BTG == query_phydm_default_rf_set_8821c(phydm)))
+		path = RF_PATH_B;
+
+	/*if (adapter->registrypriv.mp_mode == 1)*/
+	if (under_24g)
+		phy_set_tx_power_index_by_rate_section(adapter, path, channel, CCK);
+
+	phy_set_tx_power_index_by_rate_section(adapter, path, channel, OFDM);
+	if (!under_survey_ch) {
+		phy_set_tx_power_index_by_rate_section(adapter, path, channel, HT_MCS0_MCS7);
+		phy_set_tx_power_index_by_rate_section(adapter, path, channel, VHT_1SSMCS0_1SSMCS9);
+	}
+}
+
+void rtl8821c_get_tx_power_level(PADAPTER adapter, s32 *power)
+{
+}
+
+/*
+ * Parameters:
+ *	padatper
+ *	powerindex	power index for rate
+ *	rfpath		Antenna(RF) path, type "enum rf_path"
+ *	rate		data rate, type "enum MGN_RATE"
+ */
+ /*#define DBG_SET_TX_POWER_IDX*/
+void rtl8821c_set_tx_power_index(PADAPTER adapter, u32 powerindex, enum rf_path rfpath, u8 rate)
+{
+	struct dm_struct *phydm = adapter_to_phydm(adapter);
+	u8 shift = 0;
+	u8 hw_rate_idx;
+	static u32 index = 0;
+
+	/*hw_rate_idx = PHY_GetRateIndexOfTxPowerByRate(rate);*/
+	hw_rate_idx = MRateToHwRate(rate);
+
+	if (hw_rate_idx > DESC_RATEVHTSS1MCS9) {
+		RTW_ERR(FUNC_ADPT_FMT"warn rate(%s)\n", FUNC_ADPT_ARG(adapter), HDATA_RATE(hw_rate_idx));
+		rtw_warn_on(1);
+	}
+
+	if (rfpath > RF_PATH_A) {
+		#ifdef DBG_SET_TX_POWER_IDX
+		RTW_INFO(FUNC_ADPT_FMT" rfpath(%d) power index to RF_PATH_A\n", FUNC_ADPT_ARG(adapter), rfpath);
+		#endif
+		rfpath =  RF_PATH_A;
+	}
+	/*
+	* For 8821C, phydm api use 4 bytes txagc value
+	* driver must combine every four 1 byte to one 4 byte and send to phydm api
+	*/
+	shift = hw_rate_idx % 4;
+	index |= ((powerindex & 0xff) << (shift * 8));
+
+	if (shift == 3) {
+		hw_rate_idx = hw_rate_idx - 3;
+
+		if (!config_phydm_write_txagc_8821c(phydm, index, rfpath, hw_rate_idx)) {
+			RTW_ERR(FUNC_ADPT_FMT" (power index:0x%02x, rfpath:%d, rate:0x%02x, disable api:%d) wite TX-AGC failed\n",
+				FUNC_ADPT_ARG(adapter), index, rfpath, hw_rate_idx, phydm->is_disable_phy_api);
+
+			rtw_warn_on(1);
+		}
+		#ifdef DBG_SET_TX_POWER_IDX
+		RTW_INFO(FUNC_ADPT_FMT"Rate:%s ,tx_power_idx: 0x%08x\n", FUNC_ADPT_ARG(adapter), HDATA_RATE(hw_rate_idx), index);
+		#endif
+		index = 0;
+	}
+	if (MGN_VHT1SS_MCS9 == rate) {
+		if (!config_phydm_write_txagc_8821c(phydm, index, rfpath, MRateToHwRate(MGN_VHT1SS_MCS8))) {
+			RTW_ERR(FUNC_ADPT_FMT" (power index:0x%02x, rfpath:%d, rate:0x%02x, disable api:%d) wite TX-AGC failed\n",
+				FUNC_ADPT_ARG(adapter), index, rfpath, hw_rate_idx, phydm->is_disable_phy_api);
+
+			rtw_warn_on(1);
+		}
+		#ifdef DBG_SET_TX_POWER_IDX
+		RTW_INFO(FUNC_ADPT_FMT"-Rate:%s ,tx_power_idx: 0x%08x\n", FUNC_ADPT_ARG(adapter), HDATA_RATE(MRateToHwRate(MGN_VHT1SS_MCS8)), index);
+		#endif
+		index = 0;
+	}
+
+}
+
+/*
+ * Parameters:
+ *	padatper
+ *	rfpath		Antenna(RF) path, type "enum rf_path"
+ *	rate		data rate, type "enum MGN_RATE"
+ *	bandwidth	Bandwidth, type "enum _CHANNEL_WIDTH"
+ *	channel		Channel number
+ *
+ * Rteurn:
+ *	tx_power	power index for rate
+ */
+u8 rtl8821c_get_tx_power_index(PADAPTER adapter, enum rf_path rfpath, u8 rate, u8 bandwidth, u8 channel, struct txpwr_idx_comp *tic)
+{
+	PHAL_DATA_TYPE hal = GET_HAL_DATA(adapter);
+	struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter);
+	s16 power_idx;
+	u8 base_idx = 0;
+	s8 by_rate_diff = 0, limit = 0, tpt_offset = 0, extra_bias = 0;
+	u8 bIn24G = _FALSE;
+
+	base_idx = PHY_GetTxPowerIndexBase(adapter, rfpath, rate, RF_1TX, bandwidth, channel, &bIn24G);
+
+	by_rate_diff = PHY_GetTxPowerByRate(adapter, (u8)(!bIn24G), rfpath, rate);
+	limit = PHY_GetTxPowerLimit(adapter, NULL, (BAND_TYPE)(!bIn24G),
+		    hal->current_channel_bw, rfpath, rate, RF_1TX, hal->current_channel);
+
+	/* tpt_offset += PHY_GetTxPowerTrackingOffset(adapter, rfpath, rate); */
+
+	if (tic) {
+		tic->ntx_idx = RF_1TX;
+		tic->base = base_idx;
+		tic->by_rate = by_rate_diff;
+		tic->limit = limit;
+		tic->tpt = tpt_offset;
+		tic->ebias = extra_bias;
+	}
+
+	by_rate_diff = by_rate_diff > limit ? limit : by_rate_diff;
+	power_idx = base_idx + by_rate_diff + tpt_offset + extra_bias;
+
+#if 0
+#if CCX_SUPPORT
+	CCX_CellPowerLimit(adapter, channel, rate, (pu1Byte)&power_idx);
+#endif
+#endif
+
+	if (power_idx < 0)
+		power_idx = 0;
+	else if (power_idx > hal_spec->txgi_max)
+		power_idx = hal_spec->txgi_max;
+
+	return power_idx;
+}
+
+/*
+ * Description:
+ *	Check need to switch band or not
+ * Parameters:
+ *	channelToSW	channel wiii be switch to
+ * Return:
+ *	_TRUE		need to switch band
+ *	_FALSE		not need to switch band
+ */
+static u8 need_switch_band(PADAPTER adapter, u8 channelToSW)
+{
+	u8 u1tmp = 0;
+	u8 ret_value = _TRUE;
+	u8 Band = BAND_ON_5G, BandToSW = BAND_ON_5G;
+	PHAL_DATA_TYPE hal = GET_HAL_DATA(adapter);
+
+	Band = hal->current_band_type;
+
+	/* Use current swich channel to judge Band Type and switch Band if need */
+	if (channelToSW > 14)
+		BandToSW = BAND_ON_5G;
+	else
+		BandToSW = BAND_ON_2_4G;
+
+	if (BandToSW != Band) {
+		/* record current band type for other hal use */
+		hal->current_band_type = (BAND_TYPE)BandToSW;
+		ret_value = _TRUE;
+	} else
+		ret_value = _FALSE;
+
+	return ret_value;
+}
+
+static u8 get_pri_ch_id(PADAPTER adapter)
+{
+	u8 pri_ch_idx = 0;
+	PHAL_DATA_TYPE hal = GET_HAL_DATA(adapter);
+
+	if (hal->current_channel_bw == CHANNEL_WIDTH_80) {
+		/* primary channel is at lower subband of 80MHz & 40MHz */
+		if ((hal->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_LOWER) && (hal->nCur80MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_LOWER))
+			pri_ch_idx = VHT_DATA_SC_20_LOWEST_OF_80MHZ;
+		/* primary channel is at lower subband of 80MHz & upper subband of 40MHz */
+		else if ((hal->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_UPPER) && (hal->nCur80MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_LOWER))
+			pri_ch_idx = VHT_DATA_SC_20_LOWER_OF_80MHZ;
+		/* primary channel is at upper subband of 80MHz & lower subband of 40MHz */
+		else if ((hal->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_LOWER) && (hal->nCur80MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_UPPER))
+			pri_ch_idx = VHT_DATA_SC_20_UPPER_OF_80MHZ;
+		/* primary channel is at upper subband of 80MHz & upper subband of 40MHz */
+		else if ((hal->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_UPPER) && (hal->nCur80MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_UPPER))
+			pri_ch_idx = VHT_DATA_SC_20_UPPERST_OF_80MHZ;
+		else {
+			if (hal->nCur80MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_LOWER)
+				pri_ch_idx = VHT_DATA_SC_40_LOWER_OF_80MHZ;
+			else if (hal->nCur80MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_UPPER)
+				pri_ch_idx = VHT_DATA_SC_40_UPPER_OF_80MHZ;
+			else
+				RTW_INFO("SCMapping: DONOT CARE Mode Setting\n");
+		}
+	} else if (hal->current_channel_bw == CHANNEL_WIDTH_40) {
+		/* primary channel is at upper subband of 40MHz */
+		if (hal->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_UPPER)
+			pri_ch_idx = VHT_DATA_SC_20_UPPER_OF_80MHZ;
+		/* primary channel is at lower subband of 40MHz */
+		else if (hal->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_LOWER)
+			pri_ch_idx = VHT_DATA_SC_20_LOWER_OF_80MHZ;
+		else
+			RTW_INFO("SCMapping: DONOT CARE Mode Setting\n");
+	}
+
+	return  pri_ch_idx;
+}
+
+static void mac_switch_bandwidth(PADAPTER adapter, u8 pri_ch_idx)
+{
+	u8 channel = 0, bw = 0;
+	PHAL_DATA_TYPE hal = GET_HAL_DATA(adapter);
+	int err;
+
+	channel = hal->current_channel;
+	bw = hal->current_channel_bw;
+	err = rtw_halmac_set_bandwidth(adapter_to_dvobj(adapter), channel, pri_ch_idx, bw);
+	if (err) {
+		RTW_INFO(FUNC_ADPT_FMT ": (channel=%d, pri_ch_idx=%d, bw=%d) fail\n",
+			 FUNC_ADPT_ARG(adapter), channel, pri_ch_idx, bw);
+	}
+}
+u32 phy_get_tx_bbswing_8812c(_adapter *adapter, BAND_TYPE band, u8 rf_path)
+{
+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(adapter);
+	struct dm_struct		*pDM_Odm = &pHalData->odmpriv;
+	struct dm_rf_calibration_struct	*pRFCalibrateInfo = &(pDM_Odm->rf_calibrate_info);
+	s8	bbSwing_2G = -1 * GetRegTxBBSwing_2G(adapter);
+	s8	bbSwing_5G = -1 * GetRegTxBBSwing_5G(adapter);
+	u32	out = 0x200;
+	const s8	AUTO = -1;
+
+	if (pHalData->bautoload_fail_flag) {
+		if (band == BAND_ON_2_4G) {
+			pRFCalibrateInfo->bb_swing_diff_2g = bbSwing_2G;
+			if (bbSwing_2G == 0)
+				out = 0x200; /* 0 dB */
+			else if (bbSwing_2G == -3)
+				out = 0x16A; /* -3 dB */
+			else if (bbSwing_2G == -6)
+				out = 0x101; /* -6 dB */
+			else if (bbSwing_2G == -9)
+				out = 0x0B6; /* -9 dB */
+			else {
+				if (pHalData->ExternalPA_2G) {
+					pRFCalibrateInfo->bb_swing_diff_2g = -3;
+					out = 0x16A;
+				} else  {
+					pRFCalibrateInfo->bb_swing_diff_2g = 0;
+					out = 0x200;
+				}
+			}
+		} else if (band == BAND_ON_5G) {
+			pRFCalibrateInfo->bb_swing_diff_5g = bbSwing_5G;
+			if (bbSwing_5G == 0)
+				out = 0x200; /* 0 dB */
+			else if (bbSwing_5G == -3)
+				out = 0x16A; /* -3 dB */
+			else if (bbSwing_5G == -6)
+				out = 0x101; /* -6 dB */
+			else if (bbSwing_5G == -9)
+				out = 0x0B6; /* -9 dB */
+			else {
+				if (pHalData->external_pa_5g) {
+					pRFCalibrateInfo->bb_swing_diff_5g = -3;
+					out = 0x16A;
+				} else {
+					pRFCalibrateInfo->bb_swing_diff_5g = 0;
+					out = 0x200;
+				}
+			}
+		} else {
+			pRFCalibrateInfo->bb_swing_diff_2g = -3;
+			pRFCalibrateInfo->bb_swing_diff_5g = -3;
+			out = 0x16A; /* -3 dB */
+		}
+	} else {
+		u32 swing = 0, onePathSwing = 0;
+
+		if (band == BAND_ON_2_4G) {
+			if (GetRegTxBBSwing_2G(adapter) == AUTO)
+				swing = pHalData->tx_bbswing_24G;
+			else if (bbSwing_2G ==  0)
+				swing = 0x00; /* 0 dB */
+			else if (bbSwing_2G == -3)
+				swing = 0x55; /* -3 dB */
+			else if (bbSwing_2G == -6)
+				swing = 0xAA; /* -6 dB */
+			else if (bbSwing_2G == -9)
+				swing = 0xFF; /* -9 dB */
+			else
+				swing = 0x00;
+		} else {
+			if (GetRegTxBBSwing_5G(adapter) == AUTO)
+				swing = pHalData->tx_bbswing_5G;
+			else if (bbSwing_5G ==  0)
+				swing = 0x00; /* 0 dB */
+			else if (bbSwing_5G == -3)
+				swing = 0x55; /* -3 dB */
+			else if (bbSwing_5G == -6)
+				swing = 0xAA; /* -6 dB */
+			else if (bbSwing_5G == -9)
+				swing = 0xFF; /* -9 dB */
+			else
+				swing = 0x00;
+		}
+
+		if (rf_path == RF_PATH_A)
+			onePathSwing = (swing & 0x3) >> 0; /* 0xC6/C7[1:0] */
+
+		if (onePathSwing == 0x0) {
+			if (band == BAND_ON_2_4G)
+				pRFCalibrateInfo->bb_swing_diff_2g = 0;
+			else
+				pRFCalibrateInfo->bb_swing_diff_5g = 0;
+			out = 0x200; /* 0 dB */
+		} else if (onePathSwing == 0x1) {
+			if (band == BAND_ON_2_4G)
+				pRFCalibrateInfo->bb_swing_diff_2g = -3;
+			else
+				pRFCalibrateInfo->bb_swing_diff_5g = -3;
+			out = 0x16A; /* -3 dB */
+		} else if (onePathSwing == 0x2) {
+			if (band == BAND_ON_2_4G)
+				pRFCalibrateInfo->bb_swing_diff_2g = -6;
+			else
+				pRFCalibrateInfo->bb_swing_diff_5g = -6;
+			out = 0x101; /* -6 dB */
+		} else if (onePathSwing == 0x3) {
+			if (band == BAND_ON_2_4G)
+				pRFCalibrateInfo->bb_swing_diff_2g = -9;
+			else
+				pRFCalibrateInfo->bb_swing_diff_5g = -9;
+			out = 0x0B6; /* -9 dB */
+		}
+	}
+
+	/* RTW_INFO("<=== PHY_GetTxBBSwing_8812C, out = 0x%X\n", out); */
+
+	return out;
+}
+
+void phy_set_bb_swing_by_band_8812c(_adapter *adapter, u8 band, u8 previous_band)
+{
+	s8 BBDiffBetweenBand = 0;
+	struct dm_struct *pDM_Odm = adapter_to_phydm(adapter);
+	struct dm_rf_calibration_struct *pRFCalibrateInfo = &(pDM_Odm->rf_calibrate_info);
+
+	phy_set_bb_reg(adapter, rA_TxScale_Jaguar, 0xFFE00000,
+			phy_get_tx_bbswing_8812c(adapter, (BAND_TYPE)band, RF_PATH_A)); /* 0xC1C[31:21] */
+
+	/* When TxPowerTrack is ON, we should take care of the change of BB swing. */
+	/* That is, reset all info to trigger Tx power tracking. */
+	{
+
+		if (band != previous_band) {
+			BBDiffBetweenBand = (pRFCalibrateInfo->bb_swing_diff_2g - pRFCalibrateInfo->bb_swing_diff_5g);
+			BBDiffBetweenBand = (band == BAND_ON_2_4G) ? BBDiffBetweenBand : (-1 * BBDiffBetweenBand);
+			pRFCalibrateInfo->default_ofdm_index += BBDiffBetweenBand * 2;
+		}
+
+		odm_clear_txpowertracking_state(pDM_Odm);
+	}
+
+}
+
+void phy_switch_wireless_band_8821c(_adapter *adapter)
+{
+	u8 ret = 0;
+	PHAL_DATA_TYPE hal_data = GET_HAL_DATA(adapter);
+	struct dm_struct *pDM_Odm = &hal_data->odmpriv;
+	u8 current_band = hal_data->current_band_type;
+
+	if (need_switch_band(adapter, hal_data->current_channel) == _TRUE) {
+#ifdef CONFIG_BT_COEXIST
+		if (hal_data->EEPROMBluetoothCoexist) {
+			struct mlme_ext_priv *mlmeext;
+
+			/* switch band under site survey or not, must notify to BT COEX */
+			mlmeext = &adapter->mlmeextpriv;
+			if (mlmeext_scan_state(mlmeext) != SCAN_DISABLE)
+				rtw_btcoex_switchband_notify(_TRUE, hal_data->current_band_type);
+			else
+				rtw_btcoex_switchband_notify(_FALSE, hal_data->current_band_type);
+		} else
+			rtw_btcoex_wifionly_switchband_notify(adapter);
+#else /* !CONFIG_BT_COEXIST */
+		rtw_btcoex_wifionly_switchband_notify(adapter);
+#endif /* CONFIG_BT_COEXIST */
+
+		/* hal->current_channel is center channel of pmlmeext->cur_channel(primary channel) */
+		ret = config_phydm_switch_band_8821c(pDM_Odm, hal_data->current_channel);
+
+		if (!ret) {
+			RTW_ERR("%s: config_phydm_switch_band_8821c fail\n", __func__);
+			rtw_warn_on(1);
+			return;
+		}
+		phy_set_bb_swing_by_band_8812c(adapter, hal_data->current_band_type, current_band);
+	}
+}
+
+/*
+ * Description:
+ *	Set channel & bandwidth & offset
+ */
+void rtl8821c_switch_chnl_and_set_bw(PADAPTER adapter)
+{
+	PHAL_DATA_TYPE hal = GET_HAL_DATA(adapter);
+	struct dm_struct *pDM_Odm = &hal->odmpriv;
+	u8 center_ch = 0, ret = 0;
+
+	if (adapter->bNotifyChannelChange) {
+		RTW_INFO("[%s] bSwChnl=%d, ch=%d, bSetChnlBW=%d, bw=%d\n",
+			 __FUNCTION__,
+			 hal->bSwChnl,
+			 hal->current_channel,
+			 hal->bSetChnlBW,
+			 hal->current_channel_bw);
+	}
+
+	if (RTW_CANNOT_RUN(adapter)) {
+		hal->bSwChnlAndSetBWInProgress = _FALSE;
+		return;
+	}
+
+	/* set channel & Bandwidth register */
+	/* 1. set switch band register if need to switch band */
+	phy_switch_wireless_band_8821c(adapter);
+
+	/* 2. set channel register */
+	if (hal->bSwChnl) {
+		ret = config_phydm_switch_channel_8821c(pDM_Odm, hal->current_channel);
+		hal->bSwChnl = _FALSE;
+
+		if (!ret) {
+			RTW_INFO("%s: config_phydm_switch_channel_8821c fail\n", __FUNCTION__);
+			rtw_warn_on(1);
+			return;
+		}
+	}
+	phydm_config_kfree(pDM_Odm, hal->current_channel);
+
+	/* 3. set Bandwidth register */
+	if (hal->bSetChnlBW) {
+		/* get primary channel index */
+		u8 pri_ch_idx = get_pri_ch_id(adapter);
+
+		/* 3.1 set MAC register */
+		mac_switch_bandwidth(adapter, pri_ch_idx);
+
+		/* 3.2 set BB/RF registet */
+		ret = config_phydm_switch_bandwidth_8821c(pDM_Odm, pri_ch_idx, hal->current_channel_bw);
+		hal->bSetChnlBW = _FALSE;
+
+		if (!ret) {
+			RTW_INFO("%s: config_phydm_switch_bandwidth_8821c fail\n", __FUNCTION__);
+			rtw_warn_on(1);
+			return;
+		}
+	}
+
+	/* TX Power Setting */
+	/* odm_clear_txpowertracking_state(pDM_Odm); */
+	rtw_hal_set_tx_power_level(adapter, hal->current_channel);
+
+	/* IQK */
+	if ((hal->bNeedIQK == _TRUE)
+	    || (adapter->registrypriv.mp_mode == 1))  {
+		#ifdef CONFIG_IQK_MONITOR
+		systime iqk_start_time = rtw_get_current_time();
+		#endif
+
+		/*phy_iq_calibrate_8821c(pDM_Odm, _FALSE);*/
+		rtw_phydm_iqk_trigger(adapter);
+
+		#ifdef CONFIG_IQK_MONITOR
+		RTW_INFO(ADPT_FMT" switch CH(%d) DO IQK : %d ms\n", 
+			ADPT_ARG(adapter), hal->current_channel, rtw_get_passing_time_ms(iqk_start_time));
+		#endif
+		hal->bNeedIQK = _FALSE;
+	}
+}
+
+/*
+ * Description:
+ *	Store channel setting to hal date
+ * Parameters:
+ *	bSwitchChannel		swith channel or not
+ *	bSetBandWidth		set band or not
+ *	ChannelNum		center channel
+ *	ChnlWidth		bandwidth
+ *	ChnlOffsetOf40MHz	channel offset for 40MHz Bandwidth
+ *	ChnlOffsetOf80MHz	channel offset for 80MHz Bandwidth
+ *	CenterFrequencyIndex1	center channel index
+ */
+
+void rtl8821c_handle_sw_chnl_and_set_bw(
+	PADAPTER Adapter, u8 bSwitchChannel, u8 bSetBandWidth,
+	u8 ChannelNum, enum channel_width ChnlWidth, u8 ChnlOffsetOf40MHz,
+	u8 ChnlOffsetOf80MHz, u8 CenterFrequencyIndex1)
+{
+	PHAL_DATA_TYPE hal = GET_HAL_DATA(Adapter);
+	u8 tmpChannel = hal->current_channel;
+	enum channel_width tmpBW = hal->current_channel_bw;
+	u8 tmpnCur40MhzPrimeSC = hal->nCur40MhzPrimeSC;
+	u8 tmpnCur80MhzPrimeSC = hal->nCur80MhzPrimeSC;
+	u8 tmpCenterFrequencyIndex1 = hal->CurrentCenterFrequencyIndex1;
+	struct mlme_ext_priv *pmlmeext = &Adapter->mlmeextpriv;
+
+
+	/* check swchnl or setbw */
+	if (!bSwitchChannel && !bSetBandWidth) {
+		RTW_INFO("%s: not switch channel and not set bandwidth\n", __FUNCTION__);
+		return;
+	}
+
+	/* skip switch channel operation for current channel & ChannelNum(will be switch) are the same */
+	if (bSwitchChannel) {
+		if (hal->current_channel != ChannelNum) {
+			if (HAL_IsLegalChannel(Adapter, ChannelNum))
+				hal->bSwChnl = _TRUE;
+			else
+				return;
+		}
+	}
+
+	/* check set BandWidth */
+	if (bSetBandWidth) {
+		/* initial channel bw setting */
+		if (hal->bChnlBWInitialized == _FALSE) {
+			hal->bChnlBWInitialized = _TRUE;
+			hal->bSetChnlBW = _TRUE;
+		} else if ((hal->current_channel_bw != ChnlWidth) || /* check whether need set band or not */
+			   (hal->nCur40MhzPrimeSC != ChnlOffsetOf40MHz) ||
+			   (hal->nCur80MhzPrimeSC != ChnlOffsetOf80MHz) ||
+			(hal->CurrentCenterFrequencyIndex1 != CenterFrequencyIndex1))
+			hal->bSetChnlBW = _TRUE;
+	}
+
+	/* return if not need set bandwidth nor channel after check*/
+	if (!hal->bSetChnlBW && !hal->bSwChnl && hal->bNeedIQK != _TRUE)
+		return;
+
+	/* set channel number to hal data */
+	if (hal->bSwChnl) {
+		hal->current_channel = ChannelNum;
+		hal->CurrentCenterFrequencyIndex1 = ChannelNum;
+	}
+
+	/* set bandwidth info to hal data */
+	if (hal->bSetChnlBW) {
+		hal->current_channel_bw = ChnlWidth;
+		hal->nCur40MhzPrimeSC = ChnlOffsetOf40MHz;
+		hal->nCur80MhzPrimeSC = ChnlOffsetOf80MHz;
+		hal->CurrentCenterFrequencyIndex1 = CenterFrequencyIndex1;
+	}
+
+	/* switch channel & bandwidth */
+	if (!RTW_CANNOT_RUN(Adapter))
+		rtl8821c_switch_chnl_and_set_bw(Adapter);
+	else {
+		if (hal->bSwChnl) {
+			hal->current_channel = tmpChannel;
+			hal->CurrentCenterFrequencyIndex1 = tmpChannel;
+		}
+
+		if (hal->bSetChnlBW) {
+			hal->current_channel_bw = tmpBW;
+			hal->nCur40MhzPrimeSC = tmpnCur40MhzPrimeSC;
+			hal->nCur80MhzPrimeSC = tmpnCur80MhzPrimeSC;
+			hal->CurrentCenterFrequencyIndex1 = tmpCenterFrequencyIndex1;
+		}
+	}
+}
+
+/*
+ * Description:
+ *	Change channel, bandwidth & offset
+ * Parameters:
+ *	center_ch	center channel
+ *	bw		bandwidth
+ *	offset40	channel offset for 40MHz Bandwidth
+ *	offset80	channel offset for 80MHz Bandwidth
+ */
+void rtl8821c_set_channel_bw(PADAPTER adapter, u8 center_ch, enum channel_width bw, u8 offset40, u8 offset80)
+{
+	rtl8821c_handle_sw_chnl_and_set_bw(adapter, _TRUE, _TRUE, center_ch, bw, offset40, offset80, center_ch);
+}
+
+void rtl8821c_notch_filter_switch(PADAPTER adapter, bool enable)
+{
+	if (enable)
+		RTW_INFO("%s: Enable notch filter\n", __FUNCTION__);
+	else
+		RTW_INFO("%s: Disable notch filter\n", __FUNCTION__);
+}
+#ifdef CONFIG_BEAMFORMING
+#ifdef RTW_BEAMFORMING_VERSION_2
+/* REG_TXBF_CTRL		(Offset 0x42C) */
+#define BITS_R_TXBF1_AID_8821C			(BIT_MASK_R_TXBF1_AID_8821C << BIT_SHIFT_R_TXBF1_AID_8821C)
+#define BIT_CLEAR_R_TXBF1_AID_8821C(x)		((x) & (~BITS_R_TXBF1_AID_8821C))
+#define BIT_SET_R_TXBF1_AID_8821C(x, v)		(BIT_CLEAR_R_TXBF1_AID_8821C(x) | BIT_R_TXBF1_AID_8821C(v))
+
+#define BITS_R_TXBF0_AID_8821C			(BIT_MASK_R_TXBF0_AID_8821C << BIT_SHIFT_R_TXBF0_AID_8821C)
+#define BIT_CLEAR_R_TXBF0_AID_8821C(x)		((x) & (~BITS_R_TXBF0_AID_8821C))
+#define BIT_SET_R_TXBF0_AID_8821C(x, v)		(BIT_CLEAR_R_TXBF0_AID_8821C(x) | BIT_R_TXBF0_AID_8821C(v))
+
+/* REG_NDPA_OPT_CTRL		(Offset 0x45F) */
+#define BITS_R_NDPA_BW_8821C			(BIT_MASK_R_NDPA_BW_8821C << BIT_SHIFT_R_NDPA_BW_8821C)
+#define BIT_CLEAR_R_NDPA_BW_8821C(x)		((x) & (~BITS_R_NDPA_BW_8821C))
+#define BIT_SET_R_NDPA_BW_8821C(x, v)		(BIT_CLEAR_R_NDPA_BW_8821C(x) | BIT_R_NDPA_BW_8821C(v))
+
+/* REG_ASSOCIATED_BFMEE_SEL	(Offset 0x714) */
+#define BITS_AID1_8821C				(BIT_MASK_AID1_8821C << BIT_SHIFT_AID1_8821C)
+#define BIT_CLEAR_AID1_8821C(x)			((x) & (~BITS_AID1_8821C))
+#define BIT_SET_AID1_8821C(x, v)		(BIT_CLEAR_AID1_8821C(x) | BIT_AID1_8821C(v))
+
+#define BITS_AID0_8821C				(BIT_MASK_AID0_8821C << BIT_SHIFT_AID0_8821C)
+#define BIT_CLEAR_AID0_8821C(x)			((x) & (~BITS_AID0_8821C))
+#define BIT_SET_AID0_8821C(x, v)		(BIT_CLEAR_AID0_8821C(x) | BIT_AID0_8821C(v))
+
+/* REG_MU_TX_CTL		(Offset 0x14C0) */
+#define BIT_R_MU_P1_WAIT_STATE_EN_8821C		BIT(16)
+
+#define BIT_SHIFT_R_MU_RL_8821C			12
+#define BITS_R_MU_RL_8821C			(BIT_MASK_R_MU_RL_8821C << BIT_SHIFT_R_MU_RL_8821C)
+#define BIT_R_MU_RL_8821C(x)			(((x) & BIT_MASK_R_MU_RL_8821C) << BIT_SHIFT_R_MU_RL_8821C)
+#define BIT_CLEAR_R_MU_RL_8821C(x)		((x) & (~BITS_R_MU_RL_8821C))
+#define BIT_SET_R_MU_RL_8821C(x, v)		(BIT_CLEAR_R_MU_RL_8821C(x) | BIT_R_MU_RL_8821C(v))
+
+#define BIT_SHIFT_R_MU_TAB_SEL_8821C		8
+#define BIT_MASK_R_MU_TAB_SEL_8821C		0x7
+#define BITS_R_MU_TAB_SEL_8821C			(BIT_MASK_R_MU_TAB_SEL_8821C << BIT_SHIFT_R_MU_TAB_SEL_8821C)
+#define BIT_R_MU_TAB_SEL_8821C(x)		(((x) & BIT_MASK_R_MU_TAB_SEL_8821C) << BIT_SHIFT_R_MU_TAB_SEL_8821C)
+#define BIT_CLEAR_R_MU_TAB_SEL_8821C(x)		((x) & (~BITS_R_MU_TAB_SEL_8821C))
+#define BIT_SET_R_MU_TAB_SEL_8821C(x, v)	(BIT_CLEAR_R_MU_TAB_SEL_8821C(x) | BIT_R_MU_TAB_SEL_8821C(v))
+
+#define BIT_R_EN_MU_MIMO_8821C			BIT(7)
+
+#define BITS_R_MU_TABLE_VALID_8821C		(BIT_MASK_R_MU_TABLE_VALID_8821C << BIT_SHIFT_R_MU_TABLE_VALID_8821C)
+#define BIT_CLEAR_R_MU_TABLE_VALID_8821C(x)	((x) & (~BITS_R_MU_TABLE_VALID_8821C))
+#define BIT_SET_R_MU_TABLE_VALID_8821C(x, v)	(BIT_CLEAR_R_MU_TABLE_VALID_8821C(x) | BIT_R_MU_TABLE_VALID_8821C(v))
+
+/* REG_WMAC_MU_BF_CTL		(Offset 0x1680) */
+#define BITS_WMAC_MU_BFRPTSEG_SEL_8821C			(BIT_MASK_WMAC_MU_BFRPTSEG_SEL_8821C << BIT_SHIFT_WMAC_MU_BFRPTSEG_SEL_8821C)
+#define BIT_CLEAR_WMAC_MU_BFRPTSEG_SEL_8821C(x)		((x) & (~BITS_WMAC_MU_BFRPTSEG_SEL_8821C))
+#define BIT_SET_WMAC_MU_BFRPTSEG_SEL_8821C(x, v)	(BIT_CLEAR_WMAC_MU_BFRPTSEG_SEL_8821C(x) | BIT_WMAC_MU_BFRPTSEG_SEL_8821C(v))
+
+#define BITS_WMAC_MU_BF_MYAID_8821C		(BIT_MASK_WMAC_MU_BF_MYAID_8821C << BIT_SHIFT_WMAC_MU_BF_MYAID_8821C)
+#define BIT_CLEAR_WMAC_MU_BF_MYAID_8821C(x)	((x) & (~BITS_WMAC_MU_BF_MYAID_8821C))
+#define BIT_SET_WMAC_MU_BF_MYAID_8821C(x, v)	(BIT_CLEAR_WMAC_MU_BF_MYAID_8821C(x) | BIT_WMAC_MU_BF_MYAID_8821C(v))
+
+/* REG_WMAC_ASSOCIATED_MU_BFMEE7	(Offset 0x168E) */
+#define BIT_STATUS_BFEE7_8821C			BIT(10)
+
+
+static u8 _bf_get_nrx(PADAPTER adapter)
+{
+	u8 rf;
+	u8 nrx = 0;
+
+
+	rtw_hal_get_hwreg(adapter, HW_VAR_RF_TYPE, &rf);
+	switch (rf) {
+	case RF_1T1R:
+		nrx = 0;
+		break;
+	default:
+	case RF_1T2R:
+	case RF_2T2R:
+		nrx = 1;
+		break;
+	}
+
+	return nrx;
+}
+
+
+static void _config_beamformer_su(PADAPTER adapter, struct beamformer_entry *bfer)
+{
+	/* Beamforming */
+	u8 nc_index = 0, nr_index = 0;
+	u8 grouping = 0, codebookinfo = 0, coefficientsize = 0;
+	u32 addr_bfer_info, addr_csi_rpt;
+	u32 csi_param;
+	/* Misc */
+	u8 i;
+
+
+	RTW_INFO("%s: Config SU BFer entry HW setting\n", __FUNCTION__);
+
+	if (bfer->su_reg_index == 0) {
+		addr_bfer_info = REG_ASSOCIATED_BFMER0_INFO_8821C;
+		addr_csi_rpt = REG_TX_CSI_RPT_PARAM_BW20_8821C;
+	} else {
+		addr_bfer_info = REG_ASSOCIATED_BFMER1_INFO_8821C;
+		addr_csi_rpt = REG_TX_CSI_RPT_PARAM_BW20_8821C + 2;
+	}
+
+	/* Sounding protocol control */
+	rtw_write8(adapter, REG_SND_PTCL_CTRL_8821C, 0xDB);
+
+	/* MAC address/Partial AID of Beamformer */
+	for (i = 0; i < ETH_ALEN; i++)
+		rtw_write8(adapter, addr_bfer_info+i, bfer->mac_addr[i]);
+
+	/* CSI report parameters of Beamformer */
+	nc_index = _bf_get_nrx(adapter);
+	/*
+	 * 0x718[7] = 1 use Nsts
+	 * 0x718[7] = 0 use reg setting
+	 * As Bfee, we use Nsts, so nr_index don't care
+	 */
+	nr_index = bfer->NumofSoundingDim;
+	grouping = 0;
+	/* for ac = 1, for n = 3 */
+	if (TEST_FLAG(bfer->cap, BEAMFORMER_CAP_VHT_SU))
+		codebookinfo = 1;
+	else if (TEST_FLAG(bfer->cap, BEAMFORMER_CAP_HT_EXPLICIT))
+		codebookinfo = 3;
+	coefficientsize = 3;
+	csi_param = (u16)((coefficientsize<<10)|(codebookinfo<<8)|(grouping<<6)|(nr_index<<3)|(nc_index));
+	rtw_write16(adapter, addr_csi_rpt, csi_param);
+	RTW_INFO("%s: nc=%d nr=%d group=%d codebookinfo=%d coefficientsize=%d\n",
+		 __FUNCTION__, nc_index, nr_index, grouping, codebookinfo, coefficientsize);
+	RTW_INFO("%s: csi=0x%04x\n", __FUNCTION__, csi_param);
+
+	/* ndp_rx_standby_timer */
+	rtw_write8(adapter, REG_SND_PTCL_CTRL_8821C+3, 0x70);
+}
+
+static void _config_beamformer_mu(PADAPTER adapter, struct beamformer_entry *bfer)
+{
+	/* General */
+	PHAL_DATA_TYPE hal;
+	/* Beamforming */
+	struct beamforming_info *bf_info;
+	u8 nc_index = 0, nr_index = 0;
+	u8 grouping = 0, codebookinfo = 0, coefficientsize = 0;
+	u32 csi_param;
+	/* Misc */
+	u8 i, val8;
+	u16 val16;
+
+	RTW_INFO("%s: Config MU BFer entry HW setting\n", __FUNCTION__);
+
+	hal = GET_HAL_DATA(adapter);
+	bf_info = GET_BEAMFORM_INFO(adapter);
+
+	/* Reset GID table */
+	for (i = 0; i < 8; i++)
+		bfer->gid_valid[i] = 0;
+	for (i = 0; i < 16; i++)
+		bfer->user_position[i] = 0;
+
+	/* CSI report parameters of Beamformer */
+	nc_index = _bf_get_nrx(adapter);
+	nr_index = 1; /* 0x718[7] = 1 use Nsts, 0x718[7] = 0 use reg setting. as Bfee, we use Nsts, so Nr_index don't care */
+	grouping = 0; /* no grouping */
+	codebookinfo = 1; /* 7 bit for psi, 9 bit for phi */
+	coefficientsize = 0; /* This is nothing really matter */
+	csi_param = (u16)((coefficientsize<<10)|(codebookinfo<<8)|
+			(grouping<<6)|(nr_index<<3)|(nc_index));
+
+	RTW_INFO("%s: nc=%d nr=%d group=%d codebookinfo=%d coefficientsize=%d\n",
+		__func__, nc_index, nr_index, grouping, codebookinfo,
+		coefficientsize);
+	RTW_INFO("%s: csi=0x%04x\n", __func__, csi_param);
+
+	rtw_halmac_bf_add_mu_bfer(adapter_to_dvobj(adapter), bfer->p_aid,
+			csi_param, bfer->aid & 0xfff, HAL_CSI_SEG_4K,
+			bfer->mac_addr);
+
+	bf_info->cur_csi_rpt_rate = HALMAC_OFDM6;
+	rtw_halmac_bf_cfg_sounding(adapter_to_dvobj(adapter), HAL_BFEE,
+			bf_info->cur_csi_rpt_rate);
+
+	/* Set 0x6A0[14] = 1 to accept action_no_ack */
+	val8 = rtw_read8(adapter, REG_RXFLTMAP0_8821C+1);
+	val8 |= (BIT_MGTFLT14EN_8821C >> 8);
+	rtw_write8(adapter, REG_RXFLTMAP0_8821C+1, val8);
+
+	/* Set 0x6A2[5:4] = 1 to NDPA and BF report poll */
+	val8 = rtw_read8(adapter, REG_RXFLTMAP1_8821C);
+	val8 |= BIT_CTRLFLT4EN_8821C | BIT_CTRLFLT5EN_8821C;
+	rtw_write8(adapter, REG_RXFLTMAP1_8821C, val8);
+
+	/* for B-Cut */
+	if (IS_B_CUT(hal->version_id)) {
+		phy_set_bb_reg(adapter, REG_RXFLTMAP0_8821C, BIT(20), 0);
+		phy_set_bb_reg(adapter, REG_RXFLTMAP3_8821C, BIT(20), 0);
+	}
+}
+
+
+
+static void _reset_beamformer_su(PADAPTER adapter, struct beamformer_entry *bfer)
+{
+	/* Beamforming */
+	struct beamforming_info *info;
+	u8 idx;
+
+
+	info = GET_BEAMFORM_INFO(adapter);
+	/* SU BFer */
+	idx = bfer->su_reg_index;
+
+	if (idx == 0) {
+		rtw_write32(adapter, REG_ASSOCIATED_BFMER0_INFO_8821C, 0);
+		rtw_write16(adapter, REG_ASSOCIATED_BFMER0_INFO_8821C+4, 0);
+		rtw_write16(adapter, REG_TX_CSI_RPT_PARAM_BW20_8821C, 0);
+	} else {
+		rtw_write32(adapter, REG_ASSOCIATED_BFMER1_INFO_8821C, 0);
+		rtw_write16(adapter, REG_ASSOCIATED_BFMER1_INFO_8821C+4, 0);
+		rtw_write16(adapter, REG_TX_CSI_RPT_PARAM_BW20_8821C+2, 0);
+	}
+
+	info->beamformer_su_reg_maping &= ~BIT(idx);
+	bfer->su_reg_index = 0xFF;
+
+	RTW_INFO("%s: Clear SU BFer entry(%d) HW setting\n", __FUNCTION__, idx);
+}
+
+static void _reset_beamformer_mu(PADAPTER adapter, struct beamformer_entry *bfer)
+{
+	struct beamforming_info *bf_info;
+
+	bf_info = GET_BEAMFORM_INFO(adapter);
+
+	rtw_halmac_bf_del_mu_bfer(adapter_to_dvobj(adapter));
+
+	if (bf_info->beamformer_su_cnt == 0 &&
+			bf_info->beamformer_mu_cnt == 0)
+		rtw_halmac_bf_del_sounding(adapter_to_dvobj(adapter), HAL_BFEE);
+
+	RTW_INFO("%s: Clear MU BFer entry HW setting\n", __FUNCTION__);
+}
+
+void rtl8821c_phy_bf_init(PADAPTER adapter)
+{
+	u8 v8;
+	u32 v32;
+
+	v32 = rtw_read32(adapter, REG_MU_TX_CTL_8821C);
+	/* Enable P1 aggr new packet according to P0 transfer time */
+	v32 |= BIT_R_MU_P1_WAIT_STATE_EN_8821C;
+	/* MU Retry Limit */
+	v32 = BIT_SET_R_MU_RL_8821C(v32, 0xA);
+	/* Disable Tx MU-MIMO until sounding done */
+	v32 &= ~BIT_R_EN_MU_MIMO_8821C;
+	/* Clear validity of MU STAs */
+	v32 = BIT_SET_R_MU_TABLE_VALID_8821C(v32, 0);
+	rtw_write32(adapter, REG_MU_TX_CTL_8821C, v32);
+
+	/* MU-MIMO Option as default value */
+	v8 = BIT_WMAC_TXMU_ACKPOLICY_8821C(3);
+	v8 |= BIT_WMAC_TXMU_ACKPOLICY_EN_8821C;
+	rtw_write8(adapter, REG_MU_BF_OPTION_8821C, v8);
+	/* MU-MIMO Control as default value */
+	rtw_write16(adapter, REG_WMAC_MU_BF_CTL_8821C, 0);
+
+	/* Set MU NDPA rate & BW source */
+	/* 0x42C[30] = 1 (0: from Tx desc, 1: from 0x45F) */
+	v8 = rtw_read8(adapter, REG_TXBF_CTRL_8821C+3);
+	v8 |= (BIT_USE_NDPA_PARAMETER_8821C >> 24);
+	rtw_write8(adapter, REG_TXBF_CTRL_8821C+3, v8);
+	/* 0x45F[7:0] = 0x10 (Rate=OFDM_6M, BW20) */
+	rtw_write8(adapter, REG_NDPA_OPT_CTRL_8821C, 0x10);
+
+	/* Temp Settings */
+	/* STA2's CSI rate is fixed at 6M */
+	v8 = rtw_read8(adapter, 0x6DF);
+	v8 = (v8 & 0xC0) | 0x4;
+	rtw_write8(adapter, 0x6DF, v8);
+	/* Grouping bitmap parameters */
+	rtw_write32(adapter, 0x1C94, 0xAFFFAFFF);
+}
+
+void rtl8821c_phy_bf_enter(PADAPTER adapter, struct sta_info *sta)
+{
+	struct beamforming_info *info;
+	struct beamformer_entry *bfer;
+
+
+
+	RTW_INFO("+%s: " MAC_FMT "\n", __FUNCTION__, MAC_ARG(sta->cmn.mac_addr));
+
+	info = GET_BEAMFORM_INFO(adapter);
+	bfer = rtw_bf_bfer_get_entry_by_addr(adapter, sta->cmn.mac_addr);
+
+
+	info->bSetBFHwConfigInProgess = _TRUE;
+
+	if (bfer) {
+		bfer->state = BEAMFORM_ENTRY_HW_STATE_ADDING;
+
+		if (TEST_FLAG(bfer->cap, BEAMFORMER_CAP_VHT_MU))
+			_config_beamformer_mu(adapter, bfer);
+		else if (TEST_FLAG(bfer->cap, BEAMFORMER_CAP_VHT_SU|BEAMFORMER_CAP_HT_EXPLICIT))
+			_config_beamformer_su(adapter, bfer);
+
+		bfer->state = BEAMFORM_ENTRY_HW_STATE_ADDED;
+	}
+
+	info->bSetBFHwConfigInProgess = _FALSE;
+
+	RTW_INFO("-%s\n", __FUNCTION__);
+}
+
+void rtl8821c_phy_bf_leave(PADAPTER adapter, u8 *addr)
+{
+	struct beamforming_info *info;
+	struct beamformer_entry *bfer;
+
+
+
+	RTW_INFO("+%s: " MAC_FMT "\n", __FUNCTION__, MAC_ARG(addr));
+
+	info = GET_BEAMFORM_INFO(adapter);
+
+	bfer = rtw_bf_bfer_get_entry_by_addr(adapter, addr);
+
+
+	/* Clear P_AID of Beamformee */
+	/* Clear MAC address of Beamformer */
+	/* Clear Associated Bfmee Sel */
+	if (bfer) {
+		bfer->state = BEAMFORM_ENTRY_HW_STATE_DELETING;
+
+		rtw_write8(adapter, REG_SND_PTCL_CTRL_8821C, 0xD8);
+
+		if (TEST_FLAG(bfer->cap, BEAMFORMER_CAP_VHT_MU))
+			_reset_beamformer_mu(adapter, bfer);
+		else if (TEST_FLAG(bfer->cap, BEAMFORMER_CAP_VHT_SU|BEAMFORMER_CAP_HT_EXPLICIT))
+			_reset_beamformer_su(adapter, bfer);
+
+		bfer->state = BEAMFORM_ENTRY_HW_STATE_NONE;
+		bfer->cap = BEAMFORMING_CAP_NONE;
+		bfer->used = _FALSE;
+	}
+
+
+	RTW_INFO("-%s\n", __FUNCTION__);
+}
+
+void rtl8821c_phy_bf_set_gid_table(PADAPTER adapter,
+		struct beamformer_entry	*bfer_info)
+{
+	struct beamformer_entry *bfer;
+	struct beamforming_info *info;
+	u32 gid_valid[2] = {0};
+	u32 user_position[4] = {0};
+	int i;
+
+	/* update bfer info */
+	bfer = rtw_bf_bfer_get_entry_by_addr(adapter, bfer_info->mac_addr);
+	if (!bfer) {
+		RTW_INFO("%s: Cannot find BFer entry!!\n", __func__);
+		return;
+	}
+	_rtw_memcpy(bfer->gid_valid, bfer_info->gid_valid, 8);
+	_rtw_memcpy(bfer->user_position, bfer_info->user_position, 16);
+
+	info = GET_BEAMFORM_INFO(adapter);
+	info->bSetBFHwConfigInProgess = _TRUE;
+
+	/* For GID 0~31 */
+	for (i = 0; i < 4; i++)
+		gid_valid[0] |= (bfer->gid_valid[i] << (i << 3));
+
+	for (i = 0; i < 8; i++) {
+		if (i < 4)
+			user_position[0] |= (bfer->user_position[i] << (i << 3));
+		else
+			user_position[1] |= (bfer->user_position[i] << ((i - 4) << 3));
+	}
+
+	RTW_INFO("%s: STA0: gid_valid=0x%x, user_position_l=0x%x, user_position_h=0x%x\n",
+		__func__, gid_valid[0], user_position[0], user_position[1]);
+
+	/* For GID 32~64 */
+	for (i = 4; i < 8; i++)
+		gid_valid[1] |= (bfer->gid_valid[i] << ((i - 4) << 3));
+
+	for (i = 8; i < 16; i++) {
+		if (i < 12)
+			user_position[2] |= (bfer->user_position[i] << ((i - 8) << 3));
+		else
+			user_position[3] |= (bfer->user_position[i] << ((i - 12) << 3));
+	}
+
+	RTW_INFO("%s: STA1: gid_valid=0x%x, user_position_l=0x%x, user_position_h=0x%x\n",
+		__func__, gid_valid[1], user_position[2], user_position[3]);
+
+	rtw_halmac_bf_cfg_mu_bfee(adapter_to_dvobj(adapter), gid_valid, user_position);
+
+	info->bSetBFHwConfigInProgess = _FALSE;
+}
+#endif /* RTW_BEAMFORMING_VERSION_2 */
+#endif /* CONFIG_BEAMFORMING */
+#ifdef CONFIG_MP_INCLUDED
+/*
+ * Description:
+ *	Config RF path
+ *
+ * Parameters:
+ *	adapter	pointer of struct _ADAPTER
+ */
+void rtl8821c_mp_config_rfpath(PADAPTER adapter)
+{
+	PHAL_DATA_TYPE hal;
+	PMPT_CONTEXT mpt;
+	ANTENNA_PATH anttx, antrx;
+	enum rf_path rxant;
+
+
+	hal = GET_HAL_DATA(adapter);
+	mpt = &adapter->mppriv.mpt_ctx;
+	anttx = hal->antenna_tx_path;
+	antrx = hal->AntennaRxPath;
+	RTW_INFO("+Config RF Path, tx=0x%x rx=0x%x\n", anttx, antrx);
+
+#if 0 /* phydm not ready */
+	switch (anttx) {
+	case ANTENNA_A:
+		mpt->mpt_rf_path = ODM_RF_A;
+		break;
+	case ANTENNA_B:
+		mpt->mpt_rf_path = ODM_RF_B;
+		break;
+	case ANTENNA_AB:
+	default:
+		mpt->mpt_rf_path = ODM_RF_A | ODM_RF_B;
+		break;
+	}
+
+	switch (antrx) {
+	case ANTENNA_A:
+		rxant = ODM_RF_A;
+		break;
+	case ANTENNA_B:
+		rxant = ODM_RF_B;
+		break;
+	case ANTENNA_AB:
+	default:
+		rxant = ODM_RF_A | ODM_RF_B;
+		break;
+	}
+
+	config_phydm_trx_mode_8821c(GET_PDM_ODM(adapter), mpt->mpt_rf_path, rxant, FALSE);
+#endif
+	RTW_INFO("-Config RF Path Finish\n");
+}
+
+#endif /* CONFIG_MP_INCLUDED */
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/halmac.mk linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/halmac.mk
--- linux-5.6.3/3rdparty/rtl8821ce/halmac.mk	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/halmac.mk	2020-04-10 16:35:06.844661375 +0300
@@ -0,0 +1,68 @@
+# All needed files would be added to _HAL_INTFS_FILES, and it would include
+# hal/hal_halmac.c and all related files in directory hal/halmac/.
+# Before include this makefile, be sure interface (CONFIG_*_HCI) and IC
+# (CONFIG_RTL*) setting are all ready!
+
+# Base directory
+path_hm := $(topDIR)/hal/halmac
+# Level 1 directory
+path_hm_d1 := $(path_hm)/halmac_88xx
+
+ifeq ($(CONFIG_PCI_HCI), y)
+pci := y
+endif
+ifeq ($(CONFIG_SDIO_HCI), y)
+sdio := y
+endif
+ifeq ($(CONFIG_USB_HCI), y)
+usb := y
+endif
+
+ifeq ($(CONFIG_RTL8822B), y)
+ic := 8822b
+endif
+
+ifeq ($(CONFIG_RTL8822C), y)
+ic := 8822c
+endif
+
+ifeq ($(CONFIG_RTL8821C), y)
+ic := 8821c
+endif
+
+ifeq ($(CONFIG_RTL8814B), y)
+v1 := "_v1"
+ic := 8814b
+endif
+
+halmac-y +=		$(path_hm)/halmac_api.o
+
+# Modify level 1 directory if needed
+path_hm_d1 := $(path_hm_d1)$(v1)
+halmac-y +=		$(path_hm_d1)/halmac_bb_rf_88xx$(v1).o \
+			$(path_hm_d1)/halmac_cfg_wmac_88xx$(v1).o \
+			$(path_hm_d1)/halmac_common_88xx$(v1).o \
+			$(path_hm_d1)/halmac_efuse_88xx$(v1).o \
+			$(path_hm_d1)/halmac_flash_88xx$(v1).o \
+			$(path_hm_d1)/halmac_fw_88xx$(v1).o \
+			$(path_hm_d1)/halmac_gpio_88xx$(v1).o \
+			$(path_hm_d1)/halmac_init_88xx$(v1).o \
+			$(path_hm_d1)/halmac_mimo_88xx$(v1).o
+halmac-$(pci) += 	$(path_hm_d1)/halmac_pcie_88xx$(v1).o
+halmac-$(sdio) +=	$(path_hm_d1)/halmac_sdio_88xx$(v1).o
+halmac-$(usb) += 	$(path_hm_d1)/halmac_usb_88xx$(v1).o
+
+# Level 2 directory
+path_hm_d2 := $(path_hm_d1)/halmac_$(ic)
+halmac-y +=		$(path_hm_d2)/halmac_cfg_wmac_$(ic).o \
+			$(path_hm_d2)/halmac_common_$(ic).o \
+			$(path_hm_d2)/halmac_gpio_$(ic).o \
+			$(path_hm_d2)/halmac_init_$(ic).o \
+			$(path_hm_d2)/halmac_phy_$(ic).o \
+			$(path_hm_d2)/halmac_pwr_seq_$(ic).o
+halmac-$(pci) += 	$(path_hm_d2)/halmac_pcie_$(ic).o
+halmac-$(sdio) +=	$(path_hm_d2)/halmac_sdio_$(ic).o
+halmac-$(usb) += 	$(path_hm_d2)/halmac_usb_$(ic).o
+
+_HAL_INTFS_FILES +=	hal/hal_halmac.o
+_HAL_INTFS_FILES +=	$(halmac-y)
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/include/autoconf.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/autoconf.h
--- linux-5.6.3/3rdparty/rtl8821ce/include/autoconf.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/autoconf.h	2020-04-10 16:35:06.845661421 +0300
@@ -0,0 +1,305 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2015 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+/***** temporarily flag *******/
+#define CONFIG_SINGLE_IMG
+/* #define CONFIG_DISABLE_ODM */
+
+/***** temporarily flag *******/
+/*
+ * Public  General Config
+ */
+#define AUTOCONF_INCLUDED
+#define DRV_NAME "rtl8821ce"
+
+#define CONFIG_PCI_HCI
+#define PLATFORM_LINUX
+
+/*
+ * Wi-Fi Functions Config
+ */
+
+#define CONFIG_RECV_REORDERING_CTRL
+
+#define CONFIG_80211N_HT
+#define CONFIG_80211AC_VHT
+#ifdef CONFIG_80211AC_VHT
+	#ifndef CONFIG_80211N_HT
+		#define CONFIG_80211N_HT
+	#endif
+#endif
+
+#define CONFIG_IEEE80211_BAND_5GHZ
+
+/*#define CONFIG_IOCTL_CFG80211*/
+#ifdef CONFIG_IOCTL_CFG80211
+	/*#define RTW_USE_CFG80211_STA_EVENT*/ /* Indecate new sta asoc through cfg80211_new_sta */
+	#define CONFIG_CFG80211_FORCE_COMPATIBLE_2_6_37_UNDER
+	/*#define CONFIG_DEBUG_CFG80211*/
+	/*#define CONFIG_DRV_ISSUE_PROV_REQ*/ /* IOT FOR S2 */
+	#define CONFIG_SET_SCAN_DENY_TIMER
+#endif
+
+/*
+ * Internal  General Config
+ */
+/*#define CONFIG_PWRCTRL*/
+/*#define CONFIG_H2CLBK*/
+#define CONFIG_TRX_BD_ARCH	/* PCI only */
+#define USING_RX_TAG
+/*#define CONFIG_64BIT_DMA*/	/* Enable PCI 64bit DMA */
+
+#define CONFIG_EMBEDDED_FWIMG
+
+#ifdef CONFIG_EMBEDDED_FWIMG
+	#define	LOAD_FW_HEADER_FROM_DRIVER
+#endif
+/*#define CONFIG_FILE_FWIMG*/
+
+#define CONFIG_XMIT_ACK
+#ifdef CONFIG_XMIT_ACK
+	#define CONFIG_ACTIVE_KEEP_ALIVE_CHECK
+#endif
+
+/*#define CONFIG_DISABLE_MCS13TO15	1*/	/* Disable MSC13-15 rates for more stable TX throughput with some 5G APs */
+
+#define BUF_DESC_ARCH		/* if defined, hardware follows Rx buffer descriptor architecture */
+
+#ifdef CONFIG_POWER_SAVING
+	#define CONFIG_IPS
+	#ifdef CONFIG_IPS
+		/*#define CONFIG_IPS_LEVEL_2*/	 /* enable this to set default IPS mode to IPS_LEVEL_2 */
+	#endif
+	/*#define SUPPORT_HW_RFOFF_DETECTED*/
+
+	#define CONFIG_LPS
+	#if defined(CONFIG_LPS)
+		/*#define CONFIG_LPS_LCLK*/	 /* 32K */
+	#endif
+
+	#ifdef CONFIG_LPS_LCLK
+		#define CONFIG_XMIT_THREAD_MODE
+		#define LPS_RPWM_WAIT_MS 300
+	#endif
+
+	#ifdef CONFIG_LPS
+		#define CONFIG_WMMPS_STA 1
+	#endif /* CONFIG_LPS */
+#endif
+
+/*#define CONFIG_PCI_ASPM*/
+
+/*#define SUPPORT_HW_RFOFF_DETECTED*/
+#define CONFIG_HIGH_CHAN_SUPER_CALIBRATION
+
+/*#define CONFIG_ANTENNA_DIVERSITY*/
+
+#define CONFIG_AP_MODE
+#ifdef CONFIG_AP_MODE
+	/*#define CONFIG_INTERRUPT_BASED_TXBCN*/ /* Tx Beacon when driver BCN_OK ,BCN_ERR interrupt occurs */
+	#if defined(CONFIG_CONCURRENT_MODE) && defined(CONFIG_INTERRUPT_BASED_TXBCN)
+		#undef CONFIG_INTERRUPT_BASED_TXBCN
+	#endif
+	#ifdef CONFIG_INTERRUPT_BASED_TXBCN
+		/*#define CONFIG_INTERRUPT_BASED_TXBCN_EARLY_INT*/
+		#define CONFIG_INTERRUPT_BASED_TXBCN_BCN_OK_ERR
+	#endif
+
+	#define CONFIG_NATIVEAP_MLME
+	#ifndef CONFIG_NATIVEAP_MLME
+		#define CONFIG_HOSTAPD_MLME
+	#endif
+	#define CONFIG_FIND_BEST_CHANNEL
+	/*#define CONFIG_AUTO_AP_MODE*/
+#endif
+
+#define CONFIG_P2P
+#ifdef CONFIG_P2P
+	/* The CONFIG_WFD is for supporting the Wi-Fi display */
+	#define CONFIG_WFD
+
+	#define CONFIG_P2P_REMOVE_GROUP_INFO
+
+	/*#define CONFIG_DBG_P2P*/
+
+	#define CONFIG_P2P_PS
+	/*#define CONFIG_P2P_IPS*/
+	#define CONFIG_P2P_OP_CHK_SOCIAL_CH
+	#define CONFIG_CFG80211_ONECHANNEL_UNDER_CONCURRENT  /* replace CONFIG_P2P_CHK_INVITE_CH_LIST flag */
+	/*#define CONFIG_P2P_INVITE_IOT*/
+#endif
+
+/* Added by Kurt 20110511 */
+#ifdef CONFIG_TDLS
+	#define CONFIG_TDLS_DRIVER_SETUP
+#if 0
+	#ifndef CONFIG_WFD
+		#define CONFIG_WFD
+	#endif
+	#define CONFIG_TDLS_AUTOSETUP
+#endif
+	#define CONFIG_TDLS_AUTOCHECKALIVE
+	#define CONFIG_TDLS_CH_SW		/* Enable "CONFIG_TDLS_CH_SW" by default, however limit it to only work in wifi logo test mode but not in normal mode currently */
+#endif
+
+#define CONFIG_SKB_COPY	/* for amsdu */
+
+/*#define CONFIG_RTW_LED*/
+#ifdef CONFIG_RTW_LED
+	/*#define CONFIG_RTW_SW_LED*/
+	#ifdef CONFIG_RTW_SW_LED
+		/*#define CONFIG_RTW_LED_HANDLED_BY_CMD_THREAD*/
+	#endif
+#endif /* CONFIG_RTW_LED */
+
+#define CONFIG_GLOBAL_UI_PID
+
+/*#define CONFIG_RTW_80211K*/
+
+#define CONFIG_LAYER2_ROAMING
+#define CONFIG_LAYER2_ROAMING_RESUME
+/*#define CONFIG_ADAPTOR_INFO_CACHING_FILE*/ /* now just applied on 8192cu only, should make it general...*/
+/*#define CONFIG_RESUME_IN_WORKQUEUE*/
+/*#define CONFIG_SET_SCAN_DENY_TIMER*/
+#define CONFIG_LONG_DELAY_ISSUE
+#define CONFIG_NEW_SIGNAL_STAT_PROCESS
+/*#define CONFIG_SIGNAL_DISPLAY_DBM*/ /* display RX signal with dbm */
+#ifdef CONFIG_SIGNAL_DISPLAY_DBM
+/*#define CONFIG_BACKGROUND_NOISE_MONITOR*/
+#endif
+
+#define RTW_NOTCH_FILTER 0 /* 0:Disable, 1:Enable, */
+
+#define CONFIG_TX_MCAST2UNI		/* Support IP multicast->unicast*/
+/*#define CONFIG_CHECK_AC_LIFETIME 1*/	/* Check packet lifetime of 4 ACs. */
+
+/*#define CONFIG_BEAMFORMING*/
+
+/*
+ * Software feature Related Config
+ */
+#define RTW_HALMAC		/* Use HALMAC architecture, necessary for 8822B */
+
+/* #define CONFIG_TX_AMSDU */
+
+/*
+ * Interface  Related Config
+ */
+
+/*
+ * HAL  Related Config
+ */
+
+#define RTL8192E_RX_PACKET_INCLUDE_CRC	0
+#define CONFIG_RX_PACKET_APPEND_FCS
+#define SUPPORTED_BLOCK_IO
+#define RTL8188E_FW_DOWNLOAD_ENABLE
+
+/*#define CONFIG_ONLY_ONE_OUT_EP_TO_LOW	0*/
+
+#define CONFIG_OUT_EP_WIFI_MODE	0
+
+#define ENABLE_USB_DROP_INCORRECT_OUT
+
+
+#define DISABLE_BB_RF	0
+#ifdef CONFIG_WOWLAN
+	#define CONFIG_GTK_OL
+	/* #define CONFIG_ARP_KEEP_ALIVE */
+#endif /* CONFIG_WOWLAN */
+
+#ifdef CONFIG_GPIO_WAKEUP
+	#ifndef WAKEUP_GPIO_IDX
+		#define WAKEUP_GPIO_IDX 10
+	#endif
+#endif
+
+/*#define RTL8191C_FPGA_NETWORKTYPE_ADHOC 0*/
+
+#ifdef CONFIG_MP_INCLUDED
+	#define MP_DRIVER 1
+	#define CONFIG_MP_IWPRIV_SUPPORT	1
+#else
+	#define MP_DRIVER 0
+#endif
+
+/* Use cmd frame to issue beacon. Use a fixed buffer for beacon. */
+#define CONFIG_BCN_ICF
+
+/*
+ * Platform  Related Config
+ */
+
+
+#ifdef CONFIG_BT_COEXIST
+	/* for ODM and outsrc BT-Coex */
+	#ifndef CONFIG_LPS
+		#define CONFIG_LPS	/* download reserved page to FW */
+	#endif
+#endif /* !CONFIG_BT_COEXIST */
+
+
+#ifdef CONFIG_USB_TX_AGGREGATION
+/*#define CONFIG_TX_EARLY_MODE*/
+#endif
+
+#ifdef CONFIG_TX_EARLY_MODE
+#define	RTL8192E_EARLY_MODE_PKT_NUM_10	0
+#endif
+
+/*
+ * Debug Related Config
+ */
+#define DBG	1
+
+#define CONFIG_PROC_DEBUG
+
+#define DBG_CONFIG_ERROR_DETECT
+/*
+#define DBG_CONFIG_ERROR_DETECT_INT
+#define DBG_CONFIG_ERROR_RESET
+
+#define DBG_IO
+#define DBG_DELAY_OS
+#define DBG_MEM_ALLOC
+#define DBG_IOCTL
+
+#define DBG_TX
+#define DBG_XMIT_BUF
+#define DBG_XMIT_BUF_EXT
+#define DBG_TX_DROP_FRAME
+
+#define DBG_RX_DROP_FRAME
+#define DBG_RX_SEQ
+#define DBG_RX_SIGNAL_DISPLAY_PROCESSING
+#define DBG_RX_SIGNAL_DISPLAY_SSID_MONITORED "jeff-ap"
+*/
+#define DBG_RX_SIGNAL_DISPLAY_RAW_DATA
+#if 0
+#define DBG_NOISE_MONITOR
+
+#define DBG_SHOW_MCUFWDL_BEFORE_51_ENABLE
+#define DBG_ROAMING_TEST
+
+#define DBG_HAL_INIT_PROFILING
+
+#define DBG_MEMORY_LEAK	1
+
+/* TX use 1 urb */
+#define CONFIG_SINGLE_XMIT_BUF
+/* RX use 1 urb */
+#define CONFIG_SINGLE_RECV_BUF
+#endif
+
+#define	DBG_TXBD_DESC_DUMP
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/include/basic_types.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/basic_types.h
--- linux-5.6.3/3rdparty/rtl8821ce/include/basic_types.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/basic_types.h	2020-04-10 16:35:06.845661421 +0300
@@ -0,0 +1,414 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#ifndef __BASIC_TYPES_H__
+#define __BASIC_TYPES_H__
+
+
+#define SUCCESS	0
+#define FAIL	(-1)
+
+#ifndef TRUE
+	#define _TRUE	1
+#else
+	#define _TRUE	TRUE
+#endif
+
+#ifndef FALSE
+	#define _FALSE	0
+#else
+	#define _FALSE	FALSE
+#endif
+
+#ifdef PLATFORM_WINDOWS
+
+	typedef signed char s8;
+	typedef unsigned char u8;
+
+	typedef signed short s16;
+	typedef unsigned short u16;
+
+	typedef signed long s32;
+	typedef unsigned long u32;
+
+	typedef unsigned int	uint;
+	typedef	signed int		sint;
+
+
+	typedef signed long long s64;
+	typedef unsigned long long u64;
+
+	#ifdef NDIS50_MINIPORT
+
+		#define NDIS_MAJOR_VERSION       5
+		#define NDIS_MINOR_VERSION       0
+
+	#endif
+
+	#ifdef NDIS51_MINIPORT
+
+		#define NDIS_MAJOR_VERSION       5
+		#define NDIS_MINOR_VERSION       1
+
+	#endif
+
+	typedef NDIS_PROC proc_t;
+
+	typedef LONG atomic_t;
+
+#endif
+
+
+#ifdef PLATFORM_LINUX
+	#include <linux/version.h>
+	#include <linux/types.h>
+	#include <linux/module.h>
+	#include <linux/kernel.h>
+	#include <linux/init.h>
+	#include <linux/utsname.h>
+	#define IN
+	#define OUT
+	#define VOID void
+	#define NDIS_OID uint
+	#define NDIS_STATUS uint
+
+	typedef	signed int sint;
+
+	#ifndef	PVOID
+		typedef void *PVOID;
+		/* #define PVOID	(void *) */
+	#endif
+
+	#define UCHAR u8
+	#define USHORT u16
+	#define UINT u32
+	#define ULONG u32
+
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 19))
+typedef _Bool bool;
+
+enum {
+	false	= 0,
+	true	= 1
+};
+#endif
+
+	typedef void (*proc_t)(void *);
+
+	typedef	__kernel_size_t	SIZE_T;
+	typedef	__kernel_ssize_t	SSIZE_T;
+	#define FIELD_OFFSET(s, field)	((SSIZE_T)&((s *)(0))->field)
+
+#define u1Byte		u8
+#define pu1Byte		u8*
+
+#define u2Byte		u16
+#define pu2Byte		u16*
+
+#define u4Byte		u32
+#define pu4Byte		u32*
+
+#define u8Byte		u64
+#define pu8Byte		u64*
+
+#define s1Byte		s8
+#define ps1Byte		s8*
+
+#define s2Byte		s16
+#define ps2Byte		s16*
+
+#define s4Byte		s32
+#define ps4Byte		s32*
+
+#define s8Byte		s64
+#define ps8Byte		s64*
+
+#define UCHAR u8
+#define USHORT u16
+#define UINT u32
+#define ULONG u32
+#define PULONG u32*
+
+#endif
+
+
+#ifdef PLATFORM_FREEBSD
+
+	typedef signed char s8;
+	typedef unsigned char u8;
+
+	typedef signed short s16;
+	typedef unsigned short u16;
+
+	typedef signed int s32;
+	typedef unsigned int u32;
+
+	typedef unsigned int	uint;
+	typedef	signed int		sint;
+	typedef long atomic_t;
+
+	typedef signed long long s64;
+	typedef unsigned long long u64;
+	#define IN
+	#define OUT
+	#define VOID void
+	#define NDIS_OID uint
+	#define NDIS_STATUS uint
+
+	#ifndef	PVOID
+		typedef void *PVOID;
+		/* #define PVOID	(void *) */
+	#endif
+	typedef u32 dma_addr_t;
+	#define UCHAR u8
+	#define USHORT u16
+	#define UINT u32
+	#define ULONG u32
+
+	typedef void (*proc_t)(void *);
+
+	typedef unsigned int __kernel_size_t;
+	typedef int __kernel_ssize_t;
+
+	typedef	__kernel_size_t	SIZE_T;
+	typedef	__kernel_ssize_t	SSIZE_T;
+	#define FIELD_OFFSET(s, field)	((SSIZE_T)&((s *)(0))->field)
+
+#endif
+
+#define MEM_ALIGNMENT_OFFSET	(sizeof (SIZE_T))
+#define MEM_ALIGNMENT_PADDING	(sizeof(SIZE_T) - 1)
+
+#define SIZE_PTR SIZE_T
+#define SSIZE_PTR SSIZE_T
+
+/*
+* Continuous bits starting from least significant bit
+* Example:
+* BIT_LEN_MASK_32(0) => 0x00000000
+* BIT_LEN_MASK_32(1) => 0x00000001
+* BIT_LEN_MASK_32(2) => 0x00000003
+* BIT_LEN_MASK_32(32) => 0xFFFFFFFF
+*/
+#define BIT_LEN_MASK_32(__BitLen) ((u32)(0xFFFFFFFF >> (32 - (__BitLen))))
+#define BIT_LEN_MASK_16(__BitLen) ((u16)(0xFFFF >> (16 - (__BitLen))))
+#define BIT_LEN_MASK_8(__BitLen) ((u8)(0xFF >> (8 - (__BitLen))))
+
+/*
+* Continuous bits starting from least significant bit
+* Example:
+* BIT_OFFSET_LEN_MASK_32(0, 2) => 0x00000003
+* BIT_OFFSET_LEN_MASK_32(16, 2) => 0x00030000
+*/
+#define BIT_OFFSET_LEN_MASK_32(__BitOffset, __BitLen) ((u32)(BIT_LEN_MASK_32(__BitLen) << (__BitOffset)))
+#define BIT_OFFSET_LEN_MASK_16(__BitOffset, __BitLen) ((u16)(BIT_LEN_MASK_16(__BitLen) << (__BitOffset)))
+#define BIT_OFFSET_LEN_MASK_8(__BitOffset, __BitLen) ((u8)(BIT_LEN_MASK_8(__BitLen) << (__BitOffset)))
+
+/*
+* Convert LE data to host byte order
+*/
+#define EF1Byte (u8)
+#define EF2Byte le16_to_cpu
+#define EF4Byte le32_to_cpu
+
+/*
+* Read LE data from memory to host byte order
+*/
+#define ReadLE4Byte(_ptr)	le32_to_cpu(*((u32 *)(_ptr)))
+#define ReadLE2Byte(_ptr)	le16_to_cpu(*((u16 *)(_ptr)))
+#define ReadLE1Byte(_ptr)	(*((u8 *)(_ptr)))
+
+/*
+* Read BE data from memory to host byte order
+*/
+#define ReadBEE4Byte(_ptr)	be32_to_cpu(*((u32 *)(_ptr)))
+#define ReadBE2Byte(_ptr)	be16_to_cpu(*((u16 *)(_ptr)))
+#define ReadBE1Byte(_ptr)	(*((u8 *)(_ptr)))
+
+/*
+* Write host byte order data to memory in LE order
+*/
+#define WriteLE4Byte(_ptr, _val)	((*((u32 *)(_ptr))) = cpu_to_le32(_val))
+#define WriteLE2Byte(_ptr, _val)	((*((u16 *)(_ptr))) = cpu_to_le16(_val))
+#define WriteLE1Byte(_ptr, _val)	((*((u8 *)(_ptr))) = ((u8)(_val)))
+
+/*
+* Write host byte order data to memory in BE order
+*/
+#define WriteBE4Byte(_ptr, _val)	((*((u32 *)(_ptr))) = cpu_to_be32(_val))
+#define WriteBE2Byte(_ptr, _val)	((*((u16 *)(_ptr))) = cpu_to_be16(_val))
+#define WriteBE1Byte(_ptr, _val)	((*((u8 *)(_ptr))) = ((u8)(_val)))
+
+/*
+* Return 4-byte value in host byte ordering from 4-byte pointer in litten-endian system.
+*/
+#define LE_P4BYTE_TO_HOST_4BYTE(__pStart) (le32_to_cpu(*((u32 *)(__pStart))))
+#define LE_P2BYTE_TO_HOST_2BYTE(__pStart) (le16_to_cpu(*((u16 *)(__pStart))))
+#define LE_P1BYTE_TO_HOST_1BYTE(__pStart) ((*((u8 *)(__pStart))))
+
+/*
+* Return 4-byte value in host byte ordering from 4-byte pointer in big-endian system.
+*/
+#define BE_P4BYTE_TO_HOST_4BYTE(__pStart) (be32_to_cpu(*((u32 *)(__pStart))))
+#define BE_P2BYTE_TO_HOST_2BYTE(__pStart) (be16_to_cpu(*((u16 *)(__pStart))))
+#define BE_P1BYTE_TO_HOST_1BYTE(__pStart) ((*((u8 *)(__pStart))))
+
+/*
+* Translate subfield (continuous bits in little-endian) of 4-byte value in LE byte to
+* 4-byte value in host byte ordering.
+*/
+#define LE_BITS_TO_4BYTE(__pStart, __BitOffset, __BitLen) \
+	((LE_P4BYTE_TO_HOST_4BYTE(__pStart) >> (__BitOffset)) & BIT_LEN_MASK_32(__BitLen))
+
+#define LE_BITS_TO_2BYTE(__pStart, __BitOffset, __BitLen) \
+	((LE_P2BYTE_TO_HOST_2BYTE(__pStart) >> (__BitOffset)) & BIT_LEN_MASK_16(__BitLen))
+
+#define LE_BITS_TO_1BYTE(__pStart, __BitOffset, __BitLen) \
+	((LE_P1BYTE_TO_HOST_1BYTE(__pStart) >> (__BitOffset)) & BIT_LEN_MASK_8(__BitLen))
+
+/*
+* Translate subfield (continuous bits in big-endian) of 4-byte value in BE byte to
+* 4-byte value in host byte ordering.
+*/
+#define BE_BITS_TO_4BYTE(__pStart, __BitOffset, __BitLen) \
+	((BE_P4BYTE_TO_HOST_4BYTE(__pStart) >> (__BitOffset)) & BIT_LEN_MASK_32(__BitLen))
+
+#define BE_BITS_TO_2BYTE(__pStart, __BitOffset, __BitLen) \
+	((BE_P2BYTE_TO_HOST_2BYTE(__pStart) >> (__BitOffset)) & BIT_LEN_MASK_16(__BitLen))
+
+#define BE_BITS_TO_1BYTE(__pStart, __BitOffset, __BitLen) \
+	((BE_P1BYTE_TO_HOST_1BYTE(__pStart) >> (__BitOffset)) & BIT_LEN_MASK_8(__BitLen))
+
+/*
+* Mask subfield (continuous bits in little-endian) of 4-byte value in LE byte oredering
+* and return the result in 4-byte value in host byte ordering.
+*/
+#define LE_BITS_CLEARED_TO_4BYTE(__pStart, __BitOffset, __BitLen) \
+	(LE_P4BYTE_TO_HOST_4BYTE(__pStart) & (~BIT_OFFSET_LEN_MASK_32(__BitOffset, __BitLen)))
+
+#define LE_BITS_CLEARED_TO_2BYTE(__pStart, __BitOffset, __BitLen) \
+	(LE_P2BYTE_TO_HOST_2BYTE(__pStart) & (~BIT_OFFSET_LEN_MASK_16(__BitOffset, __BitLen)))
+
+#define LE_BITS_CLEARED_TO_1BYTE(__pStart, __BitOffset, __BitLen) \
+	(LE_P1BYTE_TO_HOST_1BYTE(__pStart) & ((u8)(~BIT_OFFSET_LEN_MASK_8(__BitOffset, __BitLen))))
+
+/*
+* Mask subfield (continuous bits in big-endian) of 4-byte value in BE byte oredering
+* and return the result in 4-byte value in host byte ordering.
+*/
+#define BE_BITS_CLEARED_TO_4BYTE(__pStart, __BitOffset, __BitLen) \
+	(BE_P4BYTE_TO_HOST_4BYTE(__pStart) & (~BIT_OFFSET_LEN_MASK_32(__BitOffset, __BitLen)))
+
+#define BE_BITS_CLEARED_TO_2BYTE(__pStart, __BitOffset, __BitLen) \
+	(BE_P2BYTE_TO_HOST_2BYTE(__pStart) & (~BIT_OFFSET_LEN_MASK_16(__BitOffset, __BitLen)))
+
+#define BE_BITS_CLEARED_TO_1BYTE(__pStart, __BitOffset, __BitLen) \
+	(BE_P1BYTE_TO_HOST_1BYTE(__pStart) & (~BIT_OFFSET_LEN_MASK_8(__BitOffset, __BitLen)))
+
+/*
+* Set subfield of little-endian 4-byte value to specified value.
+*/
+#define SET_BITS_TO_LE_4BYTE(__pStart, __BitOffset, __BitLen, __Value) \
+	do { \
+		if (__BitOffset == 0 && __BitLen == 32) \
+			WriteLE4Byte(__pStart, __Value); \
+		else { \
+			WriteLE4Byte(__pStart, \
+				LE_BITS_CLEARED_TO_4BYTE(__pStart, __BitOffset, __BitLen) \
+				| \
+				((((u32)__Value) & BIT_LEN_MASK_32(__BitLen)) << (__BitOffset)) \
+			); \
+		} \
+	} while (0)
+
+#define SET_BITS_TO_LE_2BYTE(__pStart, __BitOffset, __BitLen, __Value) \
+	do { \
+		if (__BitOffset == 0 && __BitLen == 16) \
+			WriteLE2Byte(__pStart, __Value); \
+		else { \
+			WriteLE2Byte(__pStart, \
+				LE_BITS_CLEARED_TO_2BYTE(__pStart, __BitOffset, __BitLen) \
+				| \
+				((((u16)__Value) & BIT_LEN_MASK_16(__BitLen)) << (__BitOffset)) \
+			); \
+		} \
+	} while (0)
+
+#define SET_BITS_TO_LE_1BYTE(__pStart, __BitOffset, __BitLen, __Value) \
+	do { \
+		if (__BitOffset == 0 && __BitLen == 8) \
+			WriteLE1Byte(__pStart, __Value); \
+		else { \
+			WriteLE1Byte(__pStart, \
+				LE_BITS_CLEARED_TO_1BYTE(__pStart, __BitOffset, __BitLen) \
+				| \
+				((((u8)__Value) & BIT_LEN_MASK_8(__BitLen)) << (__BitOffset)) \
+			); \
+		} \
+	} while (0)
+
+/*
+* Set subfield of big-endian 4-byte value to specified value.
+*/
+#define SET_BITS_TO_BE_4BYTE(__pStart, __BitOffset, __BitLen, __Value) \
+	do { \
+		if (__BitOffset == 0 && __BitLen == 32) \
+			WriteBE4Byte(__pStart, __Value); \
+		else { \
+			WriteBE4Byte(__pStart, \
+				BE_BITS_CLEARED_TO_4BYTE(__pStart, __BitOffset, __BitLen) \
+				| \
+				((((u32)__Value) & BIT_LEN_MASK_32(__BitLen)) << (__BitOffset)) \
+			); \
+		} \
+	} while (0)
+
+#define SET_BITS_TO_BE_2BYTE(__pStart, __BitOffset, __BitLen, __Value) \
+	do { \
+		if (__BitOffset == 0 && __BitLen == 16) \
+			WriteBE2Byte(__pStart, __Value); \
+		else { \
+			WriteBE2Byte(__pStart, \
+				BE_BITS_CLEARED_TO_2BYTE(__pStart, __BitOffset, __BitLen) \
+				| \
+				((((u16)__Value) & BIT_LEN_MASK_16(__BitLen)) << (__BitOffset)) \
+			); \
+		} \
+	} while (0)
+
+#define SET_BITS_TO_BE_1BYTE(__pStart, __BitOffset, __BitLen, __Value) \
+	do { \
+		if (__BitOffset == 0 && __BitLen == 8) \
+			WriteBE1Byte(__pStart, __Value); \
+		else { \
+			WriteBE1Byte(__pStart, \
+				BE_BITS_CLEARED_TO_1BYTE(__pStart, __BitOffset, __BitLen) \
+				| \
+				((((u8)__Value) & BIT_LEN_MASK_8(__BitLen)) << (__BitOffset)) \
+			); \
+		} \
+	} while (0)
+
+/* Get the N-bytes aligment offset from the current length */
+#define N_BYTE_ALIGMENT(__Value, __Aligment) ((__Aligment == 1) ? (__Value) : (((__Value + __Aligment - 1) / __Aligment) * __Aligment))
+
+typedef unsigned char	BOOLEAN, *PBOOLEAN, boolean;
+
+#define TEST_FLAG(__Flag, __testFlag)		(((__Flag) & (__testFlag)) != 0)
+#define SET_FLAG(__Flag, __setFlag)			((__Flag) |= __setFlag)
+#define CLEAR_FLAG(__Flag, __clearFlag)		((__Flag) &= ~(__clearFlag))
+#define CLEAR_FLAGS(__Flag)					((__Flag) = 0)
+#define TEST_FLAGS(__Flag, __testFlags)		(((__Flag) & (__testFlags)) == (__testFlags))
+
+#endif /* __BASIC_TYPES_H__ */
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/include/byteorder/big_endian.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/byteorder/big_endian.h
--- linux-5.6.3/3rdparty/rtl8821ce/include/byteorder/big_endian.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/byteorder/big_endian.h	2020-04-10 16:35:06.845661421 +0300
@@ -0,0 +1,82 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#ifndef _LINUX_BYTEORDER_BIG_ENDIAN_H
+#define _LINUX_BYTEORDER_BIG_ENDIAN_H
+
+#ifndef __BIG_ENDIAN
+	#define __BIG_ENDIAN 4321
+#endif
+#ifndef __BIG_ENDIAN_BITFIELD
+	#define __BIG_ENDIAN_BITFIELD
+#endif
+
+#include <byteorder/swab.h>
+
+#define __constant_htonl(x) ((__u32)(x))
+#define __constant_ntohl(x) ((__u32)(x))
+#define __constant_htons(x) ((__u16)(x))
+#define __constant_ntohs(x) ((__u16)(x))
+#define __constant_cpu_to_le64(x) ___constant_swab64((x))
+#define __constant_le64_to_cpu(x) ___constant_swab64((x))
+#define __constant_cpu_to_le32(x) ___constant_swab32((x))
+#define __constant_le32_to_cpu(x) ___constant_swab32((x))
+#define __constant_cpu_to_le16(x) ___constant_swab16((x))
+#define __constant_le16_to_cpu(x) ___constant_swab16((x))
+#define __constant_cpu_to_be64(x) ((__u64)(x))
+#define __constant_be64_to_cpu(x) ((__u64)(x))
+#define __constant_cpu_to_be32(x) ((__u32)(x))
+#define __constant_be32_to_cpu(x) ((__u32)(x))
+#define __constant_cpu_to_be16(x) ((__u16)(x))
+#define __constant_be16_to_cpu(x) ((__u16)(x))
+#define __cpu_to_le64(x) __swab64((x))
+#define __le64_to_cpu(x) __swab64((x))
+#define __cpu_to_le32(x) __swab32((x))
+#define __le32_to_cpu(x) __swab32((x))
+#define __cpu_to_le16(x) __swab16((x))
+#define __le16_to_cpu(x) __swab16((x))
+#define __cpu_to_be64(x) ((__u64)(x))
+#define __be64_to_cpu(x) ((__u64)(x))
+#define __cpu_to_be32(x) ((__u32)(x))
+#define __be32_to_cpu(x) ((__u32)(x))
+#define __cpu_to_be16(x) ((__u16)(x))
+#define __be16_to_cpu(x) ((__u16)(x))
+#define __cpu_to_le64p(x) __swab64p((x))
+#define __le64_to_cpup(x) __swab64p((x))
+#define __cpu_to_le32p(x) __swab32p((x))
+#define __le32_to_cpup(x) __swab32p((x))
+#define __cpu_to_le16p(x) __swab16p((x))
+#define __le16_to_cpup(x) __swab16p((x))
+#define __cpu_to_be64p(x) (*(__u64 *)(x))
+#define __be64_to_cpup(x) (*(__u64 *)(x))
+#define __cpu_to_be32p(x) (*(__u32 *)(x))
+#define __be32_to_cpup(x) (*(__u32 *)(x))
+#define __cpu_to_be16p(x) (*(__u16 *)(x))
+#define __be16_to_cpup(x) (*(__u16 *)(x))
+#define __cpu_to_le64s(x) __swab64s((x))
+#define __le64_to_cpus(x) __swab64s((x))
+#define __cpu_to_le32s(x) __swab32s((x))
+#define __le32_to_cpus(x) __swab32s((x))
+#define __cpu_to_le16s(x) __swab16s((x))
+#define __le16_to_cpus(x) __swab16s((x))
+#define __cpu_to_be64s(x) do {} while (0)
+#define __be64_to_cpus(x) do {} while (0)
+#define __cpu_to_be32s(x) do {} while (0)
+#define __be32_to_cpus(x) do {} while (0)
+#define __cpu_to_be16s(x) do {} while (0)
+#define __be16_to_cpus(x) do {} while (0)
+
+#include <byteorder/generic.h>
+
+#endif /* _LINUX_BYTEORDER_BIG_ENDIAN_H */
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/include/byteorder/generic.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/byteorder/generic.h
--- linux-5.6.3/3rdparty/rtl8821ce/include/byteorder/generic.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/byteorder/generic.h	2020-04-10 16:35:06.845661421 +0300
@@ -0,0 +1,207 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#ifndef _LINUX_BYTEORDER_GENERIC_H
+#define _LINUX_BYTEORDER_GENERIC_H
+
+/*
+ * linux/byteorder_generic.h
+ * Generic Byte-reordering support
+ *
+ * Francois-Rene Rideau <fare@tunes.org> 19970707
+ *    gathered all the good ideas from all asm-foo/byteorder.h into one file,
+ *    cleaned them up.
+ *    I hope it is compliant with non-GCC compilers.
+ *    I decided to put __BYTEORDER_HAS_U64__ in byteorder.h,
+ *    because I wasn't sure it would be ok to put it in types.h
+ *    Upgraded it to 2.1.43
+ * Francois-Rene Rideau <fare@tunes.org> 19971012
+ *    Upgraded it to 2.1.57
+ *    to please Linus T., replaced huge #ifdef's between little/big endian
+ *    by nestedly #include'd files.
+ * Francois-Rene Rideau <fare@tunes.org> 19971205
+ *    Made it to 2.1.71; now a facelift:
+ *    Put files under include/linux/byteorder/
+ *    Split swab from generic support.
+ *
+ * TODO:
+ *   = Regular kernel maintainers could also replace all these manual
+ *    byteswap macros that remain, disseminated among drivers,
+ *    after some grep or the sources...
+ *   = Linus might want to rename all these macros and files to fit his taste,
+ *    to fit his personal naming scheme.
+ *   = it seems that a few drivers would also appreciate
+ *    nybble swapping support...
+ *   = every architecture could add their byteswap macro in asm/byteorder.h
+ *    see how some architectures already do (i386, alpha, ppc, etc)
+ *   = cpu_to_beXX and beXX_to_cpu might some day need to be well
+ *    distinguished throughout the kernel. This is not the case currently,
+ *    since little endian, big endian, and pdp endian machines needn't it.
+ *    But this might be the case for, say, a port of Linux to 20/21 bit
+ *    architectures (and F21 Linux addict around?).
+ */
+
+/*
+ * The following macros are to be defined by <asm/byteorder.h>:
+ *
+ * Conversion of long and short int between network and host format
+ *	ntohl(__u32 x)
+ *	ntohs(__u16 x)
+ *	htonl(__u32 x)
+ *	htons(__u16 x)
+ * It seems that some programs (which? where? or perhaps a standard? POSIX?)
+ * might like the above to be functions, not macros (why?).
+ * if that's true, then detect them, and take measures.
+ * Anyway, the measure is: define only ___ntohl as a macro instead,
+ * and in a separate file, have
+ * unsigned long inline ntohl(x){return ___ntohl(x);}
+ *
+ * The same for constant arguments
+ *	__constant_ntohl(__u32 x)
+ *	__constant_ntohs(__u16 x)
+ *	__constant_htonl(__u32 x)
+ *	__constant_htons(__u16 x)
+ *
+ * Conversion of XX-bit integers (16- 32- or 64-)
+ * between native CPU format and little/big endian format
+ * 64-bit stuff only defined for proper architectures
+ *	cpu_to_[bl]eXX(__uXX x)
+ *	[bl]eXX_to_cpu(__uXX x)
+ *
+ * The same, but takes a pointer to the value to convert
+ *	cpu_to_[bl]eXXp(__uXX x)
+ *	[bl]eXX_to_cpup(__uXX x)
+ *
+ * The same, but change in situ
+ *	cpu_to_[bl]eXXs(__uXX x)
+ *	[bl]eXX_to_cpus(__uXX x)
+ *
+ * See asm-foo/byteorder.h for examples of how to provide
+ * architecture-optimized versions
+ *
+ */
+
+
+#if defined(PLATFORM_LINUX) || defined(PLATFORM_WINDOWS) || defined(PLATFORM_MPIXEL) || defined(PLATFORM_FREEBSD)
+	/*
+	* inside the kernel, we can use nicknames;
+	* outside of it, we must avoid POSIX namespace pollution...
+	*/
+	#define cpu_to_le64 __cpu_to_le64
+	#define le64_to_cpu __le64_to_cpu
+	#define cpu_to_le32 __cpu_to_le32
+	#define le32_to_cpu __le32_to_cpu
+	#define cpu_to_le16 __cpu_to_le16
+	#define le16_to_cpu __le16_to_cpu
+	#define cpu_to_be64 __cpu_to_be64
+	#define be64_to_cpu __be64_to_cpu
+	#define cpu_to_be32 __cpu_to_be32
+	#define be32_to_cpu __be32_to_cpu
+	#define cpu_to_be16 __cpu_to_be16
+	#define be16_to_cpu __be16_to_cpu
+	#define cpu_to_le64p __cpu_to_le64p
+	#define le64_to_cpup __le64_to_cpup
+	#define cpu_to_le32p __cpu_to_le32p
+	#define le32_to_cpup __le32_to_cpup
+	#define cpu_to_le16p __cpu_to_le16p
+	#define le16_to_cpup __le16_to_cpup
+	#define cpu_to_be64p __cpu_to_be64p
+	#define be64_to_cpup __be64_to_cpup
+	#define cpu_to_be32p __cpu_to_be32p
+	#define be32_to_cpup __be32_to_cpup
+	#define cpu_to_be16p __cpu_to_be16p
+	#define be16_to_cpup __be16_to_cpup
+	#define cpu_to_le64s __cpu_to_le64s
+	#define le64_to_cpus __le64_to_cpus
+	#define cpu_to_le32s __cpu_to_le32s
+	#define le32_to_cpus __le32_to_cpus
+	#define cpu_to_le16s __cpu_to_le16s
+	#define le16_to_cpus __le16_to_cpus
+	#define cpu_to_be64s __cpu_to_be64s
+	#define be64_to_cpus __be64_to_cpus
+	#define cpu_to_be32s __cpu_to_be32s
+	#define be32_to_cpus __be32_to_cpus
+	#define cpu_to_be16s __cpu_to_be16s
+	#define be16_to_cpus __be16_to_cpus
+#endif
+
+
+/*
+ * Handle ntohl and suches. These have various compatibility
+ * issues - like we want to give the prototype even though we
+ * also have a macro for them in case some strange program
+ * wants to take the address of the thing or something..
+ *
+ * Note that these used to return a "long" in libc5, even though
+ * long is often 64-bit these days.. Thus the casts.
+ *
+ * They have to be macros in order to do the constant folding
+ * correctly - if the argument passed into a inline function
+ * it is no longer constant according to gcc..
+ */
+
+#undef ntohl
+#undef ntohs
+#undef htonl
+#undef htons
+
+/*
+ * Do the prototypes. Somebody might want to take the
+ * address or some such sick thing..
+ */
+#if defined(PLATFORM_LINUX) || (defined(__GLIBC__) && __GLIBC__ >= 2)
+	extern __u32			ntohl(__u32);
+	extern __u32			htonl(__u32);
+#else /* defined(PLATFORM_LINUX) || (defined (__GLIBC__) && __GLIBC__ >= 2) */
+	#ifndef PLATFORM_FREEBSD
+		extern unsigned long int	ntohl(unsigned long int);
+		extern unsigned long int	htonl(unsigned long int);
+	#endif
+#endif
+#ifndef PLATFORM_FREEBSD
+	extern unsigned short int	ntohs(unsigned short int);
+	extern unsigned short int	htons(unsigned short int);
+#endif
+
+#if defined(__GNUC__) && (__GNUC__ >= 2) && defined(__OPTIMIZE__) || defined(PLATFORM_MPIXEL)
+
+	#define ___htonl(x) __cpu_to_be32(x)
+	#define ___htons(x) __cpu_to_be16(x)
+	#define ___ntohl(x) __be32_to_cpu(x)
+	#define ___ntohs(x) __be16_to_cpu(x)
+
+	#if defined(PLATFORM_LINUX) || (defined(__GLIBC__) && __GLIBC__ >= 2)
+		#define htonl(x) ___htonl(x)
+		#define ntohl(x) ___ntohl(x)
+	#else
+		#define htonl(x) ((unsigned long)___htonl(x))
+		#define ntohl(x) ((unsigned long)___ntohl(x))
+	#endif
+	#define htons(x) ___htons(x)
+	#define ntohs(x) ___ntohs(x)
+
+#endif /* OPTIMIZE */
+
+
+#if defined(PLATFORM_WINDOWS)
+
+	#define htonl(x) __cpu_to_be32(x)
+	#define ntohl(x) __be32_to_cpu(x)
+	#define htons(x) __cpu_to_be16(x)
+	#define ntohs(x) __be16_to_cpu(x)
+
+
+#endif
+
+#endif /* _LINUX_BYTEORDER_GENERIC_H */
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/include/byteorder/little_endian.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/byteorder/little_endian.h
--- linux-5.6.3/3rdparty/rtl8821ce/include/byteorder/little_endian.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/byteorder/little_endian.h	2020-04-10 16:35:06.845661421 +0300
@@ -0,0 +1,84 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#ifndef _LINUX_BYTEORDER_LITTLE_ENDIAN_H
+#define _LINUX_BYTEORDER_LITTLE_ENDIAN_H
+
+#ifndef __LITTLE_ENDIAN
+	#define __LITTLE_ENDIAN 1234
+#endif
+#ifndef __LITTLE_ENDIAN_BITFIELD
+	#define __LITTLE_ENDIAN_BITFIELD
+#endif
+
+#include <byteorder/swab.h>
+
+#ifndef __constant_htonl
+	#define __constant_htonl(x) ___constant_swab32((x))
+	#define __constant_ntohl(x) ___constant_swab32((x))
+	#define __constant_htons(x) ___constant_swab16((x))
+	#define __constant_ntohs(x) ___constant_swab16((x))
+	#define __constant_cpu_to_le64(x) ((__u64)(x))
+	#define __constant_le64_to_cpu(x) ((__u64)(x))
+	#define __constant_cpu_to_le32(x) ((__u32)(x))
+	#define __constant_le32_to_cpu(x) ((__u32)(x))
+	#define __constant_cpu_to_le16(x) ((__u16)(x))
+	#define __constant_le16_to_cpu(x) ((__u16)(x))
+	#define __constant_cpu_to_be64(x) ___constant_swab64((x))
+	#define __constant_be64_to_cpu(x) ___constant_swab64((x))
+	#define __constant_cpu_to_be32(x) ___constant_swab32((x))
+	#define __constant_be32_to_cpu(x) ___constant_swab32((x))
+	#define __constant_cpu_to_be16(x) ___constant_swab16((x))
+	#define __constant_be16_to_cpu(x) ___constant_swab16((x))
+	#define __cpu_to_le64(x) ((__u64)(x))
+	#define __le64_to_cpu(x) ((__u64)(x))
+	#define __cpu_to_le32(x) ((__u32)(x))
+	#define __le32_to_cpu(x) ((__u32)(x))
+	#define __cpu_to_le16(x) ((__u16)(x))
+	#define __le16_to_cpu(x) ((__u16)(x))
+	#define __cpu_to_be64(x) __swab64((x))
+	#define __be64_to_cpu(x) __swab64((x))
+	#define __cpu_to_be32(x) __swab32((x))
+	#define __be32_to_cpu(x) __swab32((x))
+	#define __cpu_to_be16(x) __swab16((x))
+	#define __be16_to_cpu(x) __swab16((x))
+	#define __cpu_to_le64p(x) (*(__u64 *)(x))
+	#define __le64_to_cpup(x) (*(__u64 *)(x))
+	#define __cpu_to_le32p(x) (*(__u32 *)(x))
+	#define __le32_to_cpup(x) (*(__u32 *)(x))
+	#define __cpu_to_le16p(x) (*(__u16 *)(x))
+	#define __le16_to_cpup(x) (*(__u16 *)(x))
+	#define __cpu_to_be64p(x) __swab64p((x))
+	#define __be64_to_cpup(x) __swab64p((x))
+	#define __cpu_to_be32p(x) __swab32p((x))
+	#define __be32_to_cpup(x) __swab32p((x))
+	#define __cpu_to_be16p(x) __swab16p((x))
+	#define __be16_to_cpup(x) __swab16p((x))
+	#define __cpu_to_le64s(x) do {} while (0)
+	#define __le64_to_cpus(x) do {} while (0)
+	#define __cpu_to_le32s(x) do {} while (0)
+	#define __le32_to_cpus(x) do {} while (0)
+	#define __cpu_to_le16s(x) do {} while (0)
+	#define __le16_to_cpus(x) do {} while (0)
+	#define __cpu_to_be64s(x) __swab64s((x))
+	#define __be64_to_cpus(x) __swab64s((x))
+	#define __cpu_to_be32s(x) __swab32s((x))
+	#define __be32_to_cpus(x) __swab32s((x))
+	#define __cpu_to_be16s(x) __swab16s((x))
+	#define __be16_to_cpus(x) __swab16s((x))
+#endif /* __constant_htonl */
+
+#include <byteorder/generic.h>
+
+#endif /* _LINUX_BYTEORDER_LITTLE_ENDIAN_H */
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/include/byteorder/swabb.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/byteorder/swabb.h
--- linux-5.6.3/3rdparty/rtl8821ce/include/byteorder/swabb.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/byteorder/swabb.h	2020-04-10 16:35:06.845661421 +0300
@@ -0,0 +1,151 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#ifndef _LINUX_BYTEORDER_SWABB_H
+#define _LINUX_BYTEORDER_SWABB_H
+
+/*
+ * linux/byteorder/swabb.h
+ * SWAp Bytes Bizarrely
+ *	swaHHXX[ps]?(foo)
+ *
+ * Support for obNUXIous pdp-endian and other bizarre architectures.
+ * Will Linux ever run on such ancient beasts? if not, this file
+ * will be but a programming pearl. Still, it's a reminder that we
+ * shouldn't be making too many assumptions when trying to be portable.
+ *
+ */
+
+/*
+ * Meaning of the names I chose (vaxlinux people feel free to correct them):
+ * swahw32	swap 16-bit half-words in a 32-bit word
+ * swahb32	swap 8-bit halves of each 16-bit half-word in a 32-bit word
+ *
+ * No 64-bit support yet. I don't know NUXI conventions for long longs.
+ * I guarantee it will be a mess when it's there, though :->
+ * It will be even worse if there are conflicting 64-bit conventions.
+ * Hopefully, no one ever used 64-bit objects on NUXI machines.
+ *
+ */
+
+#define ___swahw32(x) \
+	({ \
+		__u32 __x = (x); \
+		((__u32)(\
+			 (((__u32)(__x) & (__u32)0x0000ffffUL) << 16) | \
+			 (((__u32)(__x) & (__u32)0xffff0000UL) >> 16))); \
+	})
+#define ___swahb32(x) \
+	({ \
+		__u32 __x = (x); \
+		((__u32)(\
+			 (((__u32)(__x) & (__u32)0x00ff00ffUL) << 8) | \
+			 (((__u32)(__x) & (__u32)0xff00ff00UL) >> 8))); \
+	})
+
+#define ___constant_swahw32(x) \
+	((__u32)(\
+		 (((__u32)(x) & (__u32)0x0000ffffUL) << 16) | \
+		 (((__u32)(x) & (__u32)0xffff0000UL) >> 16)))
+#define ___constant_swahb32(x) \
+	((__u32)(\
+		 (((__u32)(x) & (__u32)0x00ff00ffUL) << 8) | \
+		 (((__u32)(x) & (__u32)0xff00ff00UL) >> 8)))
+
+/*
+ * provide defaults when no architecture-specific optimization is detected
+ */
+#ifndef __arch__swahw32
+	#define __arch__swahw32(x) ___swahw32(x)
+#endif
+#ifndef __arch__swahb32
+	#define __arch__swahb32(x) ___swahb32(x)
+#endif
+
+#ifndef __arch__swahw32p
+	#define __arch__swahw32p(x) __swahw32(*(x))
+#endif
+#ifndef __arch__swahb32p
+	#define __arch__swahb32p(x) __swahb32(*(x))
+#endif
+
+#ifndef __arch__swahw32s
+	#define __arch__swahw32s(x) do { *(x) = __swahw32p((x)); } while (0)
+#endif
+#ifndef __arch__swahb32s
+	#define __arch__swahb32s(x) do { *(x) = __swahb32p((x)); } while (0)
+#endif
+
+
+/*
+ * Allow constant folding
+ */
+#if defined(__GNUC__) && (__GNUC__ >= 2) && defined(__OPTIMIZE__)
+#  define __swahw32(x) \
+	(__builtin_constant_p((__u32)(x)) ? \
+	 ___swahw32((x)) : \
+	 __fswahw32((x)))
+#  define __swahb32(x) \
+	(__builtin_constant_p((__u32)(x)) ? \
+	 ___swahb32((x)) : \
+	 __fswahb32((x)))
+#else
+#  define __swahw32(x) __fswahw32(x)
+#  define __swahb32(x) __fswahb32(x)
+#endif /* OPTIMIZE */
+
+
+__inline static__ __const__ __u32 __fswahw32(__u32 x)
+{
+	return __arch__swahw32(x);
+}
+__inline static__ __u32 __swahw32p(__u32 *x)
+{
+	return __arch__swahw32p(x);
+}
+__inline static__ void __swahw32s(__u32 *addr)
+{
+	__arch__swahw32s(addr);
+}
+
+
+__inline static__ __const__ __u32 __fswahb32(__u32 x)
+{
+	return __arch__swahb32(x);
+}
+__inline static__ __u32 __swahb32p(__u32 *x)
+{
+	return __arch__swahb32p(x);
+}
+__inline static__ void __swahb32s(__u32 *addr)
+{
+	__arch__swahb32s(addr);
+}
+
+#ifdef __BYTEORDER_HAS_U64__
+	/*
+	* Not supported yet
+	*/
+#endif /* __BYTEORDER_HAS_U64__ */
+
+#if defined(PLATFORM_LINUX)
+	#define swahw32 __swahw32
+	#define swahb32 __swahb32
+	#define swahw32p __swahw32p
+	#define swahb32p __swahb32p
+	#define swahw32s __swahw32s
+	#define swahb32s __swahb32s
+#endif
+
+#endif /* _LINUX_BYTEORDER_SWABB_H */
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/include/byteorder/swab.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/byteorder/swab.h
--- linux-5.6.3/3rdparty/rtl8821ce/include/byteorder/swab.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/byteorder/swab.h	2020-04-10 16:35:06.845661421 +0300
@@ -0,0 +1,136 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#ifndef _LINUX_BYTEORDER_SWAB_H
+#define _LINUX_BYTEORDER_SWAB_H
+
+#if !defined(CONFIG_PLATFORM_MSTAR)
+#ifndef __u16
+	typedef unsigned short __u16;
+#endif
+
+#ifndef __u32
+	typedef unsigned int	__u32;
+#endif
+
+#ifndef __u8
+	typedef unsigned char __u8;
+#endif
+
+#ifndef __u64
+	typedef unsigned long long	__u64;
+#endif
+
+
+__inline static __u16  ___swab16(__u16 x)
+{
+	__u16 __x = x;
+	return
+		 (__u16)(
+			 (((__u16)(__x)&(__u16)0x00ffU) << 8) |
+			 (((__u16)(__x)&(__u16)0xff00U) >> 8));
+
+}
+
+__inline static __u32  ___swab32(__u32 x)
+{
+	__u32 __x = (x);
+	return  (__u32)(
+			(((__u32)(__x)&(__u32)0x000000ffUL) << 24) |
+			(((__u32)(__x)&(__u32)0x0000ff00UL) <<  8) |
+			(((__u32)(__x)&(__u32)0x00ff0000UL) >>  8) |
+			(((__u32)(__x)&(__u32)0xff000000UL) >> 24));
+}
+
+__inline static __u64  ___swab64(__u64 x)
+{
+	__u64 __x = (x);
+
+	return
+		 (__u64)(\
+		 (__u64)(((__u64)(__x)&(__u64)0x00000000000000ffULL) << 56) | \
+		 (__u64)(((__u64)(__x)&(__u64)0x000000000000ff00ULL) << 40) | \
+		 (__u64)(((__u64)(__x)&(__u64)0x0000000000ff0000ULL) << 24) | \
+		 (__u64)(((__u64)(__x)&(__u64)0x00000000ff000000ULL) <<  8) | \
+		 (__u64)(((__u64)(__x)&(__u64)0x000000ff00000000ULL) >>  8) | \
+		 (__u64)(((__u64)(__x)&(__u64)0x0000ff0000000000ULL) >> 24) | \
+		 (__u64)(((__u64)(__x)&(__u64)0x00ff000000000000ULL) >> 40) | \
+		 (__u64)(((__u64)(__x)&(__u64)0xff00000000000000ULL) >> 56));
+	\
+}
+#endif /* CONFIG_PLATFORM_MSTAR */
+
+#ifndef __arch__swab16
+__inline static __u16 __arch__swab16(__u16 x)
+{
+	return ___swab16(x);
+}
+
+#endif
+
+#ifndef __arch__swab32
+__inline static __u32 __arch__swab32(__u32 x)
+{
+	__u32 __tmp = (x) ;
+	return ___swab32(__tmp);
+}
+#endif
+
+#ifndef __arch__swab64
+
+__inline static __u64 __arch__swab64(__u64 x)
+{
+	__u64 __tmp = (x) ;
+	return ___swab64(__tmp);
+}
+
+
+#endif
+
+#ifndef __swab16
+	#define __swab16(x) __fswab16(x)
+	#define __swab32(x) __fswab32(x)
+	#define __swab64(x) __fswab64(x)
+#endif /* __swab16 */
+
+#ifdef PLATFORM_FREEBSD
+	__inline static __u16 __fswab16(__u16 x)
+#else
+	__inline static const __u16 __fswab16(__u16 x)
+#endif /* PLATFORM_FREEBSD */
+{
+	return __arch__swab16(x);
+}
+#ifdef PLATFORM_FREEBSD
+	__inline static __u32 __fswab32(__u32 x)
+#else
+	__inline static const __u32 __fswab32(__u32 x)
+#endif /* PLATFORM_FREEBSD */
+{
+	return __arch__swab32(x);
+}
+
+#if defined(PLATFORM_LINUX) || defined(PLATFORM_WINDOWS)
+	#define swab16 __swab16
+	#define swab32 __swab32
+	#define swab64 __swab64
+	#define swab16p __swab16p
+	#define swab32p __swab32p
+	#define swab64p __swab64p
+	#define swab16s __swab16s
+	#define swab32s __swab32s
+	#define swab64s __swab64s
+#endif
+
+#endif /* _LINUX_BYTEORDER_SWAB_H */
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/include/circ_buf.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/circ_buf.h
--- linux-5.6.3/3rdparty/rtl8821ce/include/circ_buf.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/circ_buf.h	2020-04-10 16:35:06.845661421 +0300
@@ -0,0 +1,23 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#ifndef __CIRC_BUF_H_
+#define __CIRC_BUF_H_ 1
+
+#define CIRC_CNT(head,tail,size) (((head) - (tail)) & ((size)-1))
+
+#define CIRC_SPACE(head,tail,size) CIRC_CNT((tail),((head)+1),(size))
+
+#endif //_CIRC_BUF_H_
+
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/include/cmd_osdep.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/cmd_osdep.h
--- linux-5.6.3/3rdparty/rtl8821ce/include/cmd_osdep.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/cmd_osdep.h	2020-04-10 16:35:06.845661421 +0300
@@ -0,0 +1,26 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#ifndef __CMD_OSDEP_H_
+#define __CMD_OSDEP_H_
+
+
+extern sint _rtw_init_cmd_priv(struct	cmd_priv *pcmdpriv);
+extern sint _rtw_init_evt_priv(struct evt_priv *pevtpriv);
+extern void _rtw_free_evt_priv(struct	evt_priv *pevtpriv);
+extern void _rtw_free_cmd_priv(struct	cmd_priv *pcmdpriv);
+extern sint _rtw_enqueue_cmd(_queue *queue, struct cmd_obj *obj, bool to_head);
+extern struct cmd_obj *_rtw_dequeue_cmd(_queue *queue);
+
+#endif
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/include/cmn_info/rtw_sta_info.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/cmn_info/rtw_sta_info.h
--- linux-5.6.3/3rdparty/rtl8821ce/include/cmn_info/rtw_sta_info.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/cmn_info/rtw_sta_info.h	2020-04-10 16:35:06.845661421 +0300
@@ -0,0 +1,250 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
+ *
+ *
+ ******************************************************************************/
+
+ /*This header file is for all driver teams to use the same station info.
+If you want to change this file please make sure notify all driver teams maintainers.*/
+
+/*Created by YuChen 20170301*/
+
+#ifndef __INC_RTW_STA_INFO_H
+#define __INC_RTW_STA_INFO_H
+
+/*--------------------Define ---------------------------------------*/
+
+#define STA_DM_CTRL_ACTIVE			BIT(0)
+#define STA_DM_CTRL_CFO_TRACKING	BIT(1)
+
+#ifdef CONFIG_BEAMFORMING
+#define	BEAMFORMING_HT_BEAMFORMER_ENABLE	BIT(0)	/*Declare sta support beamformer*/
+#define	BEAMFORMING_HT_BEAMFORMEE_ENABLE	BIT(1)	/*Declare sta support beamformee*/
+#define	BEAMFORMING_HT_BEAMFORMER_TEST		BIT(2)	/*Transmiting Beamforming no matter the target supports it or not*/
+#define	BEAMFORMING_HT_BEAMFORMER_STEER_NUM		(BIT(4)|BIT(5))		/*Sta Bfer's capability*/
+#define	BEAMFORMING_HT_BEAMFORMEE_CHNL_EST_CAP	(BIT(6)|BIT(7))		/*Sta BFee's capability*/
+
+#define	BEAMFORMING_VHT_BEAMFORMER_ENABLE	BIT(0)	/*Declare sta support beamformer*/
+#define	BEAMFORMING_VHT_BEAMFORMEE_ENABLE	BIT(1)	/*Declare sta support beamformee*/
+#define	BEAMFORMING_VHT_MU_MIMO_AP_ENABLE	BIT(2)	/*Declare sta support MU beamformer*/
+#define	BEAMFORMING_VHT_MU_MIMO_STA_ENABLE	BIT(3)	/*Declare sta support MU beamformer*/
+#define	BEAMFORMING_VHT_BEAMFORMER_TEST		BIT(4)	/*Transmiting Beamforming no matter the target supports it or not*/
+#define	BEAMFORMING_VHT_BEAMFORMER_STS_CAP		(BIT(8)|BIT(9)|BIT(10))		/*Sta BFee's capability*/
+#define	BEAMFORMING_VHT_BEAMFORMEE_SOUND_DIM	(BIT(12)|BIT(13)|BIT(14))	/*Sta Bfer's capability*/
+#endif
+
+#define HT_STBC_EN	BIT(0)
+#define VHT_STBC_EN	BIT(1)
+
+#define HT_LDPC_EN	BIT(0)
+#define VHT_LDPC_EN	BIT(1)
+
+#define	SM_PS_STATIC	0
+#define	SM_PS_DYNAMIC	1
+#define	SM_PS_INVALID	2
+#define	SM_PS_DISABLE	3
+
+
+/*cmn_sta_info.ra_sta_info.txrx_state*/
+#define	TX_STATE				0
+#define	RX_STATE				1
+#define	BI_DIRECTION_STATE	2
+
+/*--------------------Define Enum-----------------------------------*/
+enum channel_width {
+	CHANNEL_WIDTH_20		= 0,
+	CHANNEL_WIDTH_40		= 1,
+	CHANNEL_WIDTH_80		= 2,
+	CHANNEL_WIDTH_160		= 3,
+	CHANNEL_WIDTH_80_80	= 4,
+	CHANNEL_WIDTH_5		= 5,
+	CHANNEL_WIDTH_10	= 6,
+	CHANNEL_WIDTH_MAX	= 7,
+};
+
+enum rf_type {
+	RF_1T1R			= 0,
+	RF_1T2R			= 1,
+	RF_2T2R			= 2,
+	RF_2T3R			= 3,
+	RF_2T4R			= 4,
+	RF_3T3R			= 5,
+	RF_3T4R			= 6,
+	RF_4T4R			= 7,
+	RF_TYPE_MAX,
+};
+
+enum bb_path {
+	BB_PATH_A = 0x00000001,
+	BB_PATH_B = 0x00000002,
+	BB_PATH_C = 0x00000004,
+	BB_PATH_D = 0x00000008,
+
+	BB_PATH_AB = (BB_PATH_A | BB_PATH_B),
+	BB_PATH_AC = (BB_PATH_A | BB_PATH_C),
+	BB_PATH_AD = (BB_PATH_A | BB_PATH_D),
+	BB_PATH_BC = (BB_PATH_B | BB_PATH_C),
+	BB_PATH_BD = (BB_PATH_B | BB_PATH_D),
+	BB_PATH_CD = (BB_PATH_C | BB_PATH_D),
+
+	BB_PATH_ABC = (BB_PATH_A | BB_PATH_B | BB_PATH_C),
+	BB_PATH_ABD = (BB_PATH_A | BB_PATH_B | BB_PATH_D),
+	BB_PATH_ACD = (BB_PATH_A | BB_PATH_C | BB_PATH_D),
+	BB_PATH_BCD = (BB_PATH_B | BB_PATH_C | BB_PATH_D),
+
+	BB_PATH_ABCD = (BB_PATH_A | BB_PATH_B | BB_PATH_C | BB_PATH_D),
+};
+
+enum rf_path {
+	RF_PATH_A = 0,
+	RF_PATH_B = 1,
+	RF_PATH_C = 2,
+	RF_PATH_D = 3,
+	RF_PATH_AB,
+	RF_PATH_AC,
+	RF_PATH_AD,
+	RF_PATH_BC,
+	RF_PATH_BD,
+	RF_PATH_CD,
+	RF_PATH_ABC,
+	RF_PATH_ACD,
+	RF_PATH_BCD,
+	RF_PATH_ABCD,
+};
+
+enum wireless_set {
+	WIRELESS_CCK	= 0x00000001,
+	WIRELESS_OFDM	= 0x00000002,
+	WIRELESS_HT	= 0x00000004,
+	WIRELESS_VHT	= 0x00000008,
+};
+
+/*--------------------Define MACRO---------------------------------*/
+
+/*--------------------Define Struct-----------------------------------*/
+
+#ifdef CONFIG_BEAMFORMING
+struct bf_cmn_info {
+	u8	ht_beamform_cap;		/*Sta capablity*/
+	u16	vht_beamform_cap;		/*Sta capablity*/
+	u16	p_aid;
+	u8	g_id;
+};
+#endif
+struct rssi_info {
+	s8		rssi;
+	s8		rssi_cck;
+	s8		rssi_ofdm;
+	u8		packet_map;
+	u8		ofdm_pkt_cnt;
+	u8		cck_pkt_cnt;
+	u16		cck_sum_power;
+	u8		is_send_rssi;
+	u8		valid_bit;
+	s16		rssi_acc;	/*accumulate RSSI for per packet MA sum*/
+};
+
+struct ra_sta_info {
+	u8	rate_id;			/*[PHYDM] ratr_idx*/
+	u8	rssi_level;			/*[PHYDM]*/
+	u8	is_first_connect:1;		/*[PHYDM] CE: ra_rpt_linked, AP: H2C_rssi_rpt*/
+	u8	is_support_sgi:1;		/*[driver]*/
+	u8	is_vht_enable:2;		/*[driver]*/
+	u8	disable_ra:1;			/*[driver]*/
+	u8	disable_pt:1;			/*[driver] remove is_disable_power_training*/
+	u8	txrx_state:2;			/*[PHYDM] 0: Tx, 1:Rx, 2:bi-direction*/
+	u8	is_noisy:1;			/*[PHYDM]*/
+	u8	curr_tx_rate;			/*[PHYDM] FW->Driver*/
+	enum channel_width	ra_bw_mode;	/*[Driver] max bandwidth, for RA only*/
+	enum channel_width	curr_tx_bw;	/*[PHYDM] FW->Driver*/
+	u8	curr_retry_ratio;		/*[PHYDM] FW->Driver*/
+	u64	ramask;
+};
+
+struct dtp_info {
+	u8	dyn_tx_power;	/*Dynamic Tx power offset*/
+	u8	last_tx_power;
+	u8	sta_tx_high_power_lvl:4;
+	u8	sta_last_dtp_lvl:4;
+};
+
+struct cmn_sta_info {
+	u16	dm_ctrl;			/*[Driver]*/			
+	enum channel_width	bw_mode;	/*[Driver] max support BW*/
+	u8	mac_id;				/*[Driver]*/
+	u8	mac_addr[6];			/*[Driver]*/
+	u16	aid;				/*[Driver]*/
+	enum rf_type mimo_type;			/*[Driver] sta XTXR*/
+	struct rssi_info	rssi_stat;	/*[PHYDM]*/
+	struct ra_sta_info	ra_info;	/*[Driver&PHYDM]*/
+	u16	tx_moving_average_tp;		/*[Driver] tx average MBps*/
+	u16	rx_moving_average_tp;		/*[Driver] rx average MBps*/
+	u8	stbc_en:2;			/*[Driver] really transmitt STBC*/
+	u8	ldpc_en:2;			/*[Driver] really transmitt LDPC*/
+	enum wireless_set	support_wireless_set;/*[Driver]*/
+#ifdef CONFIG_BEAMFORMING
+	struct bf_cmn_info	bf_info;	/*[Driver]*/
+#endif
+	u8	sm_ps:2;			/*[Driver]*/
+	struct dtp_info dtp_stat;		/*[PHYDM] Dynamic Tx power offset*/
+	/*u8		pw2cca_over_TH_cnt;*/
+	/*u8		total_pw2cca_cnt;*/
+};
+
+struct phydm_phyinfo_struct {
+	u8		rx_pwdb_all;
+	u8		signal_quality;				/* OFDM: signal_quality=rx_mimo_signal_quality[0], CCK: signal qualityin 0-100 index. */
+	u8		rx_mimo_signal_strength[4];	/* RSSI in 0~100 index */
+	s8		rx_mimo_signal_quality[4];		/* OFDM: per-path's EVM translate to 0~100% , no used for CCK*/
+	u8		rx_mimo_evm_dbm[4];			/* per-path's original EVM (dbm) */
+	s16		cfo_short[4];					/* per-path's cfo_short */
+	s16		cfo_tail[4];					/* per-path's cfo_tail */
+	s8		rx_power;					/* in dBm Translate from PWdB */
+	s8		recv_signal_power;			/* Real power in dBm for this packet, no beautification and aggregation. Keep this raw info to be used for the other procedures. */
+	u8		bt_rx_rssi_percentage;
+	u8		signal_strength;				/* in 0-100 index. */
+	s8		rx_pwr[4];					/* per-path's pwdb */
+	s8		rx_snr[4];					/* per-path's SNR	*/
+/*ODM_PHY_STATUS_NEW_TYPE_SUPPORT*/
+	u8		rx_count:2;					/* RX path counter---*/
+	u8		band_width:2;
+	u8		rxsc:4;						/* sub-channel---*/
+	u8		channel;						/* channel number---*/
+	u8		is_mu_packet:1;				/* is MU packet or not---boolean*/
+	u8		is_beamformed:1;				/* BF packet---boolean*/
+	u8		cnt_pw2cca;
+	u8		cnt_cca2agc_rdy;
+/*ODM_PHY_STATUS_NEW_TYPE_SUPPORT*/
+};
+
+struct phydm_perpkt_info_struct {
+	u8		data_rate;
+	u8		station_id;
+	u8		is_cck_rate: 1;
+	u8		rate_ss:3;			/*spatial stream of data rate*/
+	u8		is_packet_match_bssid:1;	/*boolean*/
+	u8		is_packet_to_self:1;		/*boolean*/
+	u8		is_packet_beacon:1;		/*boolean*/
+	u8		is_to_self:1;				/*boolean*/
+	u8		ppdu_cnt;
+};
+
+/*--------------------Export global variable----------------------------*/
+
+/*--------------------Function declaration-----------------------------*/
+
+#endif
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/include/custom_gpio.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/custom_gpio.h
--- linux-5.6.3/3rdparty/rtl8821ce/include/custom_gpio.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/custom_gpio.h	2020-04-10 16:35:06.845661421 +0300
@@ -0,0 +1,46 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2016 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#ifndef __CUSTOM_GPIO_H__
+#define __CUSTOM_GPIO_H___
+
+#include <drv_conf.h>
+#include <osdep_service.h>
+
+#ifdef PLATFORM_OS_XP
+	#include <drv_types_xp.h>
+#endif
+
+#ifdef PLATFORM_OS_CE
+	#include <drv_types_ce.h>
+#endif
+
+#ifdef PLATFORM_LINUX
+	#include <drv_types_linux.h>
+#endif
+
+typedef enum cust_gpio_modes {
+	WLAN_PWDN_ON,
+	WLAN_PWDN_OFF,
+	WLAN_POWER_ON,
+	WLAN_POWER_OFF,
+	WLAN_BT_PWDN_ON,
+	WLAN_BT_PWDN_OFF
+} cust_gpio_modes_t;
+
+extern int rtw_wifi_gpio_init(void);
+extern int rtw_wifi_gpio_deinit(void);
+extern void rtw_wifi_gpio_wlan_ctrl(int onoff);
+
+#endif
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/include/drv_conf.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/drv_conf.h
--- linux-5.6.3/3rdparty/rtl8821ce/include/drv_conf.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/drv_conf.h	2020-04-10 16:35:06.845661421 +0300
@@ -0,0 +1,478 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#ifndef __DRV_CONF_H__
+#define __DRV_CONF_H__
+#include "autoconf.h"
+#include "hal_ic_cfg.h"
+
+#if defined(PLATFORM_LINUX) && defined (PLATFORM_WINDOWS)
+
+	#error "Shall be Linux or Windows, but not both!\n"
+
+#endif
+#define CONFIG_RSSI_PRIORITY
+#ifdef CONFIG_RTW_REPEATER_SON
+	#ifndef CONFIG_AP
+		#define CONFIG_AP
+	#endif
+	#ifndef CONFIG_CONCURRENT_MODE
+		#define CONFIG_CONCURRENT_MODE
+	#endif
+	#ifndef CONFIG_BR_EXT
+		#define CONFIG_BR_EXT
+	#endif
+	#ifndef CONFIG_RTW_REPEATER_SON_ID
+		#define CONFIG_RTW_REPEATER_SON_ID			0x02040608
+	#endif
+	//#define CONFIG_RTW_REPEATER_SON_ROOT
+	#ifndef CONFIG_RTW_REPEATER_SON_ROOT
+		#define CONFIG_LAYER2_ROAMING_ACTIVE
+	#endif
+	#undef CONFIG_POWER_SAVING
+#endif
+
+#if defined(CONFIG_MCC_MODE) && (!defined(CONFIG_CONCURRENT_MODE))
+
+	#error "Enable CONCURRENT_MODE before enable MCC MODE\n"
+
+#endif
+
+#if defined(CONFIG_MCC_MODE) && defined(CONFIG_BT_COEXIST)
+
+	#error "Disable BT COEXIST before enable MCC MODE\n"
+
+#endif
+
+#if defined(CONFIG_MCC_MODE) && defined(CONFIG_TDLS)
+
+	#error "Disable TDLS before enable MCC MODE\n"
+
+#endif
+
+#if defined(CONFIG_RTW_80211R) && !defined(CONFIG_LAYER2_ROAMING)
+
+	#error "Enable CONFIG_LAYER2_ROAMING before enable CONFIG_RTW_80211R\n"
+
+#endif
+
+/* Older Android kernel doesn't has CONFIG_ANDROID defined,
+ * add this to force CONFIG_ANDROID defined */
+#ifdef CONFIG_PLATFORM_ANDROID
+	#ifndef CONFIG_ANDROID
+		#define CONFIG_ANDROID
+	#endif
+#endif
+
+#ifdef CONFIG_ANDROID
+	/* Some Android build will restart the UI while non-printable ascii is passed
+	* between java and c/c++ layer (JNI). We force CONFIG_VALIDATE_SSID
+	* for Android here. If you are sure there is no risk on your system about this,
+	* mask this macro define to support non-printable ascii ssid.
+	* #define CONFIG_VALIDATE_SSID */
+
+	/* Android expect dbm as the rx signal strength unit */
+	#define CONFIG_SIGNAL_DISPLAY_DBM
+#endif
+
+/*
+#if defined(CONFIG_HAS_EARLYSUSPEND) && defined(CONFIG_RESUME_IN_WORKQUEUE)
+	#warning "You have CONFIG_HAS_EARLYSUSPEND enabled in your system, we disable CONFIG_RESUME_IN_WORKQUEUE automatically"
+	#undef CONFIG_RESUME_IN_WORKQUEUE
+#endif
+
+#if defined(CONFIG_ANDROID_POWER) && defined(CONFIG_RESUME_IN_WORKQUEUE)
+	#warning "You have CONFIG_ANDROID_POWER enabled in your system, we disable CONFIG_RESUME_IN_WORKQUEUE automatically"
+	#undef CONFIG_RESUME_IN_WORKQUEUE
+#endif
+*/
+
+#ifdef CONFIG_RESUME_IN_WORKQUEUE /* this can be removed, because there is no case for this... */
+	#if !defined(CONFIG_WAKELOCK) && !defined(CONFIG_ANDROID_POWER)
+		#error "enable CONFIG_RESUME_IN_WORKQUEUE without CONFIG_WAKELOCK or CONFIG_ANDROID_POWER will suffer from the danger of wifi's unfunctionality..."
+		#error "If you still want to enable CONFIG_RESUME_IN_WORKQUEUE in this case, mask this preprossor checking and GOOD LUCK..."
+	#endif
+#endif
+
+/* About USB VENDOR REQ */
+#if defined(CONFIG_USB_VENDOR_REQ_BUFFER_PREALLOC) && !defined(CONFIG_USB_VENDOR_REQ_MUTEX)
+	#warning "define CONFIG_USB_VENDOR_REQ_MUTEX for CONFIG_USB_VENDOR_REQ_BUFFER_PREALLOC automatically"
+	#define CONFIG_USB_VENDOR_REQ_MUTEX
+#endif
+#if defined(CONFIG_VENDOR_REQ_RETRY) &&  !defined(CONFIG_USB_VENDOR_REQ_MUTEX)
+	#warning "define CONFIG_USB_VENDOR_REQ_MUTEX for CONFIG_VENDOR_REQ_RETRY automatically"
+	#define CONFIG_USB_VENDOR_REQ_MUTEX
+#endif
+
+#if defined(CONFIG_DFS_SLAVE_WITH_RADAR_DETECT) && !defined(CONFIG_DFS_MASTER)
+	#define CONFIG_DFS_MASTER
+#endif
+
+#if !defined(CONFIG_AP_MODE) && defined(CONFIG_DFS_MASTER)
+	#error "enable CONFIG_DFS_MASTER without CONFIG_AP_MODE"
+#endif
+
+#ifdef CONFIG_RTW_MESH
+	#ifndef CONFIG_RTW_MESH_ACNODE_PREVENT
+	#define CONFIG_RTW_MESH_ACNODE_PREVENT 1
+	#endif
+
+	#ifndef CONFIG_RTW_MESH_OFFCH_CAND
+	#define CONFIG_RTW_MESH_OFFCH_CAND 1
+	#endif
+
+	#ifndef CONFIG_RTW_MESH_PEER_BLACKLIST
+	#define CONFIG_RTW_MESH_PEER_BLACKLIST 1
+	#endif
+
+	#ifndef CONFIG_RTW_MESH_CTO_MGATE_BLACKLIST
+	#define CONFIG_RTW_MESH_CTO_MGATE_BLACKLIST 1
+	#endif
+	#ifndef CONFIG_RTW_MESH_CTO_MGATE_CARRIER
+	#define CONFIG_RTW_MESH_CTO_MGATE_CARRIER CONFIG_RTW_MESH_CTO_MGATE_BLACKLIST
+	#endif
+
+	#ifndef CONFIG_RTW_MPM_TX_IES_SYNC_BSS
+	#define CONFIG_RTW_MPM_TX_IES_SYNC_BSS 1
+	#endif
+	#if CONFIG_RTW_MPM_TX_IES_SYNC_BSS
+		#ifndef CONFIG_RTW_MESH_AEK
+		#define CONFIG_RTW_MESH_AEK
+		#endif
+	#endif
+
+	#ifndef CONFIG_RTW_MESH_DATA_BMC_TO_UC
+	#define CONFIG_RTW_MESH_DATA_BMC_TO_UC 1
+	#endif
+#endif
+
+#if !defined(CONFIG_SCAN_BACKOP) && defined(CONFIG_AP_MODE)
+#define CONFIG_SCAN_BACKOP
+#endif
+
+#define RTW_SCAN_SPARSE_MIRACAST 1
+#define RTW_SCAN_SPARSE_BG 0
+#define RTW_SCAN_SPARSE_ROAMING_ACTIVE 1
+
+#ifndef CONFIG_RTW_HIQ_FILTER
+	#define CONFIG_RTW_HIQ_FILTER 1
+#endif
+
+#ifndef CONFIG_RTW_ADAPTIVITY_EN
+	#define CONFIG_RTW_ADAPTIVITY_EN 0
+#endif
+
+#ifndef CONFIG_RTW_ADAPTIVITY_MODE
+	#define CONFIG_RTW_ADAPTIVITY_MODE 0
+#endif
+
+#ifndef CONFIG_RTW_ADAPTIVITY_TH_L2H_INI
+	#define CONFIG_RTW_ADAPTIVITY_TH_L2H_INI 0
+#endif
+
+#ifndef CONFIG_RTW_ADAPTIVITY_TH_EDCCA_HL_DIFF
+	#define CONFIG_RTW_ADAPTIVITY_TH_EDCCA_HL_DIFF 0
+#endif
+
+#ifndef CONFIG_RTW_EXCL_CHS
+	#define CONFIG_RTW_EXCL_CHS {0}
+#endif
+
+#ifndef CONFIG_RTW_DFS_REGION_DOMAIN
+	#define CONFIG_RTW_DFS_REGION_DOMAIN 0
+#endif
+
+#ifndef CONFIG_TXPWR_BY_RATE_EN
+#define CONFIG_TXPWR_BY_RATE_EN 2 /* by efuse */
+#endif
+#ifndef CONFIG_TXPWR_LIMIT_EN
+#define CONFIG_TXPWR_LIMIT_EN 2 /* by efuse */
+#endif
+
+#ifndef CONFIG_RTW_CHPLAN
+#define CONFIG_RTW_CHPLAN 0xFF /* RTW_CHPLAN_UNSPECIFIED */
+#endif
+
+/* compatible with old fashion configuration */
+#if defined(CONFIG_CALIBRATE_TX_POWER_BY_REGULATORY)
+	#undef CONFIG_TXPWR_BY_RATE_EN
+	#undef CONFIG_TXPWR_LIMIT_EN
+	#define CONFIG_TXPWR_BY_RATE_EN 1
+	#define CONFIG_TXPWR_LIMIT_EN 1
+#elif defined(CONFIG_CALIBRATE_TX_POWER_TO_MAX)
+	#undef CONFIG_TXPWR_BY_RATE_EN
+	#undef CONFIG_TXPWR_LIMIT_EN
+	#define CONFIG_TXPWR_BY_RATE_EN 1
+	#define CONFIG_TXPWR_LIMIT_EN 0
+#endif
+
+#ifndef RTW_DEF_MODULE_REGULATORY_CERT
+	#define RTW_DEF_MODULE_REGULATORY_CERT 0
+#endif
+
+#if RTW_DEF_MODULE_REGULATORY_CERT
+	/* force enable TX power by rate and TX power limit */
+	#undef CONFIG_TXPWR_BY_RATE_EN
+	#undef CONFIG_TXPWR_LIMIT_EN
+	#define CONFIG_TXPWR_BY_RATE_EN 1
+	#define CONFIG_TXPWR_LIMIT_EN 1
+#endif
+
+#if !defined(CONFIG_TXPWR_LIMIT) && CONFIG_TXPWR_LIMIT_EN
+	#define CONFIG_TXPWR_LIMIT
+#endif
+
+#ifdef CONFIG_RTW_IPCAM_APPLICATION
+	#undef CONFIG_TXPWR_BY_RATE_EN
+	#define CONFIG_TXPWR_BY_RATE_EN 1
+	#define CONFIG_RTW_CUSTOMIZE_BEEDCA		0x0000431C
+	#define CONFIG_RTW_CUSTOMIZE_BWMODE		0x00
+	#define CONFIG_RTW_CUSTOMIZE_RLSTA		0x7
+#if defined(CONFIG_RTL8192E) || defined(CONFIG_RTL8192F) || defined(CONFIG_RTL8822B)
+	#define CONFIG_RTW_TX_2PATH_EN		/*	mutually incompatible with STBC_TX & Beamformer	*/
+#endif
+#endif
+/*#define CONFIG_EXTEND_LOWRATE_TXOP			*/
+
+#ifndef CONFIG_RTW_RX_AMPDU_SZ_LIMIT_1SS
+	#define CONFIG_RTW_RX_AMPDU_SZ_LIMIT_1SS {0xFF, 0xFF, 0xFF, 0xFF}
+#endif
+#ifndef CONFIG_RTW_RX_AMPDU_SZ_LIMIT_2SS
+	#define CONFIG_RTW_RX_AMPDU_SZ_LIMIT_2SS {0xFF, 0xFF, 0xFF, 0xFF}
+#endif
+#ifndef CONFIG_RTW_RX_AMPDU_SZ_LIMIT_3SS
+	#define CONFIG_RTW_RX_AMPDU_SZ_LIMIT_3SS {0xFF, 0xFF, 0xFF, 0xFF}
+#endif
+#ifndef CONFIG_RTW_RX_AMPDU_SZ_LIMIT_4SS
+	#define CONFIG_RTW_RX_AMPDU_SZ_LIMIT_4SS {0xFF, 0xFF, 0xFF, 0xFF}
+#endif
+
+#ifndef CONFIG_RTW_TARGET_TX_PWR_2G_A
+	#define CONFIG_RTW_TARGET_TX_PWR_2G_A {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}
+#endif
+
+#ifndef CONFIG_RTW_TARGET_TX_PWR_2G_B
+	#define CONFIG_RTW_TARGET_TX_PWR_2G_B {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}
+#endif
+
+#ifndef CONFIG_RTW_TARGET_TX_PWR_2G_C
+	#define CONFIG_RTW_TARGET_TX_PWR_2G_C {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}
+#endif
+
+#ifndef CONFIG_RTW_TARGET_TX_PWR_2G_D
+	#define CONFIG_RTW_TARGET_TX_PWR_2G_D {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}
+#endif
+
+#ifndef CONFIG_RTW_TARGET_TX_PWR_5G_A
+	#define CONFIG_RTW_TARGET_TX_PWR_5G_A {-1, -1, -1, -1, -1, -1, -1, -1, -1}
+#endif
+
+#ifndef CONFIG_RTW_TARGET_TX_PWR_5G_B
+	#define CONFIG_RTW_TARGET_TX_PWR_5G_B {-1, -1, -1, -1, -1, -1, -1, -1, -1}
+#endif
+
+#ifndef CONFIG_RTW_TARGET_TX_PWR_5G_C
+	#define CONFIG_RTW_TARGET_TX_PWR_5G_C {-1, -1, -1, -1, -1, -1, -1, -1, -1}
+#endif
+
+#ifndef CONFIG_RTW_TARGET_TX_PWR_5G_D
+	#define CONFIG_RTW_TARGET_TX_PWR_5G_D {-1, -1, -1, -1, -1, -1, -1, -1, -1}
+#endif
+
+#ifndef CONFIG_RTW_AMPLIFIER_TYPE_2G
+	#define CONFIG_RTW_AMPLIFIER_TYPE_2G 0
+#endif
+
+#ifndef CONFIG_RTW_AMPLIFIER_TYPE_5G
+	#define CONFIG_RTW_AMPLIFIER_TYPE_5G 0
+#endif
+
+#ifndef CONFIG_RTW_RFE_TYPE
+	#define CONFIG_RTW_RFE_TYPE 64
+#endif
+
+#ifndef CONFIG_RTW_GLNA_TYPE
+	#define CONFIG_RTW_GLNA_TYPE 0
+#endif
+
+#ifndef CONFIG_RTW_PLL_REF_CLK_SEL
+	#define CONFIG_RTW_PLL_REF_CLK_SEL 0x0F
+#endif
+
+#ifndef CONFIG_IFACE_NUMBER
+	#ifdef CONFIG_CONCURRENT_MODE
+		#define CONFIG_IFACE_NUMBER	2
+	#else
+		#define CONFIG_IFACE_NUMBER	1
+	#endif
+#endif
+
+#ifndef CONFIG_CONCURRENT_MODE
+	#if (CONFIG_IFACE_NUMBER > 1)
+		#error "CONFIG_IFACE_NUMBER over 1,but CONFIG_CONCURRENT_MODE not defined"
+	#endif
+#endif
+
+#if (CONFIG_IFACE_NUMBER == 0)
+	#error "CONFIG_IFACE_NUMBER cound not be 0 !!"
+#endif
+
+#if defined(CONFIG_RTL8188E) || defined(CONFIG_RTL8192E) || defined(CONFIG_RTL8188F) || \
+defined(CONFIG_RTL8188GTV) || defined(CONFIG_RTL8192F) || \
+defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A) || defined(CONFIG_RTL8710B) || \
+defined(CONFIG_RTL8723B) || defined(CONFIG_RTL8703B) || defined(CONFIG_RTL8723D)
+#define CONFIG_HWMPCAP_GEN1
+#elif defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C) || defined(CONFIG_RTL8822C) /*|| defined(CONFIG_RTL8814A)*/
+#define CONFIG_HWMPCAP_GEN2
+#elif defined(CONFIG_RTL8814B) /*Address CAM - 128*/
+#define CONFIG_HWMPCAP_GEN3
+#endif
+
+#if defined(CONFIG_HWMPCAP_GEN1) && (CONFIG_IFACE_NUMBER > 2) 
+	#ifdef CONFIG_POWER_SAVING
+	/*#warning "Disable PS when CONFIG_IFACE_NUMBER > 2"*/
+	#undef CONFIG_POWER_SAVING
+	#endif
+
+	#ifdef CONFIG_WOWLAN
+	#error "This IC can't support MI and WoWLan at the same time"
+	#endif
+#endif
+
+#if (CONFIG_IFACE_NUMBER > 4)
+	#error "Not support over 4 interfaces yet !!"
+#endif
+
+#if (CONFIG_IFACE_NUMBER > 8)	/*IFACE_ID_MAX*/
+	#error "HW count not support over 8 interfaces !!"
+#endif
+
+#if (CONFIG_IFACE_NUMBER > 2)
+	#define CONFIG_MI_WITH_MBSSID_CAM
+
+	#ifdef CONFIG_MI_WITH_MBSSID_CAM
+		#define CONFIG_MBSSID_CAM
+		#if defined(CONFIG_RUNTIME_PORT_SWITCH)
+			#undef CONFIG_RUNTIME_PORT_SWITCH
+		#endif
+	#endif
+
+	#ifdef CONFIG_AP_MODE
+		#define CONFIG_SUPPORT_MULTI_BCN
+
+		#define CONFIG_SWTIMER_BASED_TXBCN
+
+		#ifdef CONFIG_HWMPCAP_GEN2 /*CONFIG_RTL8822B/CONFIG_RTL8821C/CONFIG_RTL8822C*/
+		#define CONFIG_FW_HANDLE_TXBCN
+
+		#ifdef CONFIG_FW_HANDLE_TXBCN
+			#ifdef CONFIG_SWTIMER_BASED_TXBCN
+				#undef CONFIG_SWTIMER_BASED_TXBCN
+			#endif
+
+			#define CONFIG_LIMITED_AP_NUM	4
+		#endif
+	#endif /*CONFIG_HWMPCAP_GEN2*/
+	#endif /*CONFIG_AP_MODE*/
+
+	#ifdef CONFIG_HWMPCAP_GEN2 /*CONFIG_RTL8822B/CONFIG_RTL8821C/CONFIG_RTL8822C*/
+	#define CONFIG_CLIENT_PORT_CFG
+	#define CONFIG_NEW_NETDEV_HDL
+	#endif/*CONFIG_HWMPCAP_GEN2*/
+#endif/*(CONFIG_IFACE_NUMBER > 2)*/
+
+#define MACID_NUM_SW_LIMIT 32
+#define SEC_CAM_ENT_NUM_SW_LIMIT 32
+
+#if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A) || defined(CONFIG_RTL8814A)
+	#define CONFIG_IEEE80211_BAND_5GHZ
+#endif
+
+#if defined(CONFIG_WOWLAN) && (defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C) || defined(CONFIG_RTL8814A))
+	#define CONFIG_WOW_PATTERN_HW_CAM
+#endif
+
+#ifndef CONFIG_TSF_UPDATE_PAUSE_FACTOR
+#define CONFIG_TSF_UPDATE_PAUSE_FACTOR 200
+#endif
+
+#ifndef CONFIG_TSF_UPDATE_RESTORE_FACTOR
+#define CONFIG_TSF_UPDATE_RESTORE_FACTOR 5
+#endif
+
+/*
+	Mark CONFIG_DEAUTH_BEFORE_CONNECT by Arvin 2015/07/20
+	If the failure of Wi-Fi connection is due to some irregular disconnection behavior (like unplug dongle,
+	power down etc.) in last time, we can unmark this flag to avoid some unpredictable response from AP.
+*/
+/*#define CONFIG_DEAUTH_BEFORE_CONNECT */
+
+/*#define CONFIG_WEXT_DONT_JOIN_BYSSID	*/
+/* #include <rtl871x_byteorder.h> */
+
+
+/*#define CONFIG_DOSCAN_IN_BUSYTRAFFIC	*/
+/*#define CONFIG_PHDYM_FW_FIXRATE		*/	/*	Another way to fix tx rate	*/
+
+/*Don't release SDIO irq in suspend/resume procedure*/
+#define CONFIG_RTW_SDIO_KEEP_IRQ	0
+
+/*
+ * Add by Lucas@2016/02/15
+ * For RX Aggregation
+ */
+#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_USB_RX_AGGREGATION)
+	#define RTW_RX_AGGREGATION
+#endif /* CONFIG_SDIO_HCI || CONFIG_USB_RX_AGGREGATION */
+
+#ifdef CONFIG_RTW_HOSTAPD_ACS
+	#if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A) || defined(CONFIG_RTL8814A)
+		#ifndef CONFIG_FIND_BEST_CHANNEL
+			#define CONFIG_FIND_BEST_CHANNEL
+		#endif
+	#else
+		#ifdef CONFIG_FIND_BEST_CHANNEL
+			#undef CONFIG_FIND_BEST_CHANNEL
+		#endif
+		#ifndef CONFIG_RTW_ACS
+			#define CONFIG_RTW_ACS
+		#endif
+		#ifndef CONFIG_BACKGROUND_NOISE_MONITOR
+			#define CONFIG_BACKGROUND_NOISE_MONITOR
+		#endif
+	#endif
+#endif
+
+#ifdef CONFIG_RTW_80211K
+	#ifndef CONFIG_RTW_ACS
+		#define CONFIG_RTW_ACS
+	#endif
+#endif /*CONFIG_RTW_80211K*/
+
+#ifdef DBG_CONFIG_ERROR_RESET
+#ifndef CONFIG_IPS
+#define CONFIG_IPS
+#endif
+#endif
+
+#ifdef RTW_REDUCE_SCAN_SWITCH_CH_TIME
+#ifndef CONFIG_RTL8822B
+	#error "Only 8822B support RTW_REDUCE_SCAN_SWITCH_CH_TIME"
+#endif
+	#ifndef RTW_CHANNEL_SWITCH_OFFLOAD
+		#define RTW_CHANNEL_SWITCH_OFFLOAD
+	#endif
+#endif
+
+#endif /* __DRV_CONF_H__ */
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/include/drv_types_ce.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/drv_types_ce.h
--- linux-5.6.3/3rdparty/rtl8821ce/include/drv_types_ce.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/drv_types_ce.h	2020-04-10 16:35:06.846661469 +0300
@@ -0,0 +1,86 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#ifndef __DRV_TYPES_CE_H__
+#define __DRV_TYPES_CE_H__
+
+#include <drv_conf.h>
+#include <osdep_service.h>
+
+#include <Sdcardddk.h>
+
+#define MAX_ACTIVE_REG_PATH 256
+
+#define MAX_MCAST_LIST_NUM					32
+
+
+
+/* for ioctl */
+#define MAKE_DRIVER_VERSION(_MainVer, _MinorVer)	((((u32)(_MainVer))<<16)+_MinorVer)
+
+#define NIC_HEADER_SIZE				14			/* !< can be moved to typedef.h */
+#define NIC_MAX_PACKET_SIZE			1514		/* !< can be moved to typedef.h */
+#define NIC_MAX_SEND_PACKETS			10		/* max number of send packets the MiniportSendPackets function can accept, can be moved to typedef.h */
+#define NIC_VENDOR_DRIVER_VERSION       MAKE_DRIVER_VERSION(0, 001)	/* !< can be moved to typedef.h */
+#define NIC_MAX_PACKET_SIZE			1514		/* !< can be moved to typedef.h */
+
+typedef struct _MP_REG_ENTRY {
+
+	NDIS_STRING		RegName;	/* variable name text */
+	BOOLEAN			bRequired;	/* 1->required, 0->optional */
+
+	u8			Type;		/* NdisParameterInteger/NdisParameterHexInteger/NdisParameterStringle/NdisParameterMultiString */
+	uint			FieldOffset;	/* offset to MP_ADAPTER field */
+	uint			FieldSize;	/* size (in bytes) of the field */
+
+#ifdef UNDER_AMD64
+	u64			Default;
+#else
+	u32			Default;		/* default value to use */
+#endif
+
+	u32			Min;			/* minimum value allowed */
+	u32			Max;		/* maximum value allowed */
+} MP_REG_ENTRY, *PMP_REG_ENTRY;
+
+#ifdef CONFIG_USB_HCI
+typedef struct _USB_EXTENSION {
+	LPCUSB_FUNCS    _lpUsbFuncs;
+	USB_HANDLE	    _hDevice;
+	PVOID		    pAdapter;
+
+#if 0
+	USB_ENDPOINT_DESCRIPTOR		_endpACLIn;
+	USB_ENDPOINT_DESCRIPTOR		_endpACLOutHigh;
+	USB_ENDPOINT_DESCRIPTOR		_endpACLOutNormal;
+
+	USB_PIPE        pPipeIn;
+	USB_PIPE        pPipeOutNormal;
+	USB_PIPE        pPipeOutHigh;
+#endif
+
+} USB_EXTENSION, *PUSB_EXTENSION;
+#endif
+
+
+typedef struct _OCTET_STRING {
+	u8      *Octet;
+	u16      Length;
+} OCTET_STRING, *POCTET_STRING;
+
+
+
+
+
+#endif
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/include/drv_types_gspi.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/drv_types_gspi.h
--- linux-5.6.3/3rdparty/rtl8821ce/include/drv_types_gspi.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/drv_types_gspi.h	2020-04-10 16:35:06.846661469 +0300
@@ -0,0 +1,49 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#ifndef __DRV_TYPES_GSPI_H__
+#define __DRV_TYPES_GSPI_H__
+
+/* SPI Header Files */
+#ifdef PLATFORM_LINUX
+	#include <linux/platform_device.h>
+	#include <linux/spi/spi.h>
+	#include <linux/gpio.h>
+	/* #include <mach/ldo.h> */
+	#include <asm/mach-types.h>
+	#include <asm/gpio.h>
+	#include <asm/io.h>
+	#include <mach/board.h>
+	#include <mach/hardware.h>
+	#include <mach/irqs.h>
+	#include <custom_gpio.h>
+#endif
+
+
+typedef struct gspi_data {
+	u8  func_number;
+
+	u8  tx_block_mode;
+	u8  rx_block_mode;
+	u32 block_transfer_len;
+
+#ifdef PLATFORM_LINUX
+	struct spi_device *func;
+
+	struct workqueue_struct *priv_wq;
+	struct delayed_work irq_work;
+#endif
+} GSPI_DATA, *PGSPI_DATA;
+
+#endif /*  #ifndef __DRV_TYPES_GSPI_H__ */
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/include/drv_types.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/drv_types.h
--- linux-5.6.3/3rdparty/rtl8821ce/include/drv_types.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/drv_types.h	2020-04-10 16:35:06.846661469 +0300
@@ -0,0 +1,1820 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+/*-------------------------------------------------------------------------------
+
+	For type defines and data structure defines
+
+--------------------------------------------------------------------------------*/
+
+
+#ifndef __DRV_TYPES_H__
+#define __DRV_TYPES_H__
+
+#include <drv_conf.h>
+#include <basic_types.h>
+#include <osdep_service.h>
+#include <rtw_byteorder.h>
+#include <wlan_bssdef.h>
+#include <wifi.h>
+#include <ieee80211.h>
+#ifdef CONFIG_ARP_KEEP_ALIVE
+	#include <net/neighbour.h>
+	#include <net/arp.h>
+#endif
+
+#ifdef PLATFORM_OS_XP
+	#include <drv_types_xp.h>
+#endif
+
+#ifdef PLATFORM_OS_CE
+	#include <drv_types_ce.h>
+#endif
+
+#ifdef PLATFORM_LINUX
+	#include <drv_types_linux.h>
+#endif
+
+enum _NIC_VERSION {
+
+	RTL8711_NIC,
+	RTL8712_NIC,
+	RTL8713_NIC,
+	RTL8716_NIC
+
+};
+
+typedef struct _ADAPTER _adapter, ADAPTER, *PADAPTER;
+
+#include <rtw_debug.h>
+#include <cmn_info/rtw_sta_info.h>
+#include <rtw_rf.h>
+#include "../core/rtw_chplan.h"
+
+#ifdef CONFIG_80211N_HT
+	#include <rtw_ht.h>
+#endif
+
+#ifdef CONFIG_80211AC_VHT
+	#include <rtw_vht.h>
+#endif
+
+#ifdef CONFIG_INTEL_WIDI
+	#include <rtw_intel_widi.h>
+#endif
+
+#include <rtw_cmd.h>
+#include <cmd_osdep.h>
+#include <rtw_security.h>
+#include <rtw_xmit.h>
+#include <xmit_osdep.h>
+#include <rtw_recv.h>
+#include <rtw_rm.h>
+
+#ifdef CONFIG_BEAMFORMING
+	#include <rtw_beamforming.h>
+#endif
+
+#include <recv_osdep.h>
+#include <rtw_efuse.h>
+#include <rtw_sreset.h>
+#include <hal_intf.h>
+#include <hal_com.h>
+#include<hal_com_h2c.h>
+#include <hal_com_led.h>
+#include "../hal/hal_dm.h"
+#include <rtw_qos.h>
+#include <rtw_pwrctrl.h>
+#include <rtw_mlme.h>
+#include <mlme_osdep.h>
+#include <rtw_io.h>
+#include <rtw_ioctl.h>
+#include <rtw_ioctl_set.h>
+#include <rtw_ioctl_query.h>
+#include <rtw_ioctl_rtl.h>
+#include <osdep_intf.h>
+#include <rtw_eeprom.h>
+#include <sta_info.h>
+#include <rtw_event.h>
+#include <rtw_mlme_ext.h>
+#include <rtw_mi.h>
+#include <rtw_ap.h>
+#ifdef CONFIG_RTW_MESH
+#include "../core/mesh/rtw_mesh.h"
+#endif
+#include <rtw_efuse.h>
+#include <rtw_version.h>
+#include <rtw_odm.h>
+
+#ifdef CONFIG_PREALLOC_RX_SKB_BUFFER
+	#include <rtw_mem.h>
+#endif
+
+#include <rtw_p2p.h>
+
+#ifdef CONFIG_TDLS
+	#include <rtw_tdls.h>
+#endif /* CONFIG_TDLS */
+
+#ifdef CONFIG_WAPI_SUPPORT
+	#include <rtw_wapi.h>
+#endif /* CONFIG_WAPI_SUPPORT */
+
+#ifdef CONFIG_MP_INCLUDED
+	#include <rtw_mp.h>
+#endif /* CONFIG_MP_INCLUDED */
+
+#ifdef CONFIG_BR_EXT
+	#include <rtw_br_ext.h>
+#endif /* CONFIG_BR_EXT */
+
+#ifdef CONFIG_IOL
+	#include <rtw_iol.h>
+#endif /* CONFIG_IOL */
+
+#include <ip.h>
+#include <if_ether.h>
+#include <ethernet.h>
+#include <circ_buf.h>
+
+#include <rtw_android.h>
+
+#include <rtw_btcoex_wifionly.h>
+#include <rtw_btcoex.h>
+
+#ifdef CONFIG_MCC_MODE
+	#include <rtw_mcc.h>
+#endif /*CONFIG_MCC_MODE */
+
+#ifdef CONFIG_RTW_REPEATER_SON
+	#include <rtw_rson.h>
+#endif /*CONFIG_RTW_REPEATER_SON */
+
+#define SPEC_DEV_ID_NONE BIT(0)
+#define SPEC_DEV_ID_DISABLE_HT BIT(1)
+#define SPEC_DEV_ID_ENABLE_PS BIT(2)
+#define SPEC_DEV_ID_RF_CONFIG_1T1R BIT(3)
+#define SPEC_DEV_ID_RF_CONFIG_2T2R BIT(4)
+#define SPEC_DEV_ID_ASSIGN_IFNAME BIT(5)
+
+struct specific_device_id {
+
+	u32		flags;
+
+	u16		idVendor;
+	u16		idProduct;
+
+};
+
+struct registry_priv {
+	u8	chip_version;
+	u8	rfintfs;
+	u8	lbkmode;
+	u8	hci;
+	NDIS_802_11_SSID	ssid;
+	u8	network_mode;	/* infra, ad-hoc, auto */
+	u8	channel;/* ad-hoc support requirement */
+	u8	wireless_mode;/* A, B, G, auto */
+	u8	scan_mode;/* active, passive */
+	u8	radio_enable;
+	u8	preamble;/* long, short, auto */
+	u8	vrtl_carrier_sense;/* Enable, Disable, Auto */
+	u8	vcs_type;/* RTS/CTS, CTS-to-self */
+	u16	rts_thresh;
+	u16  frag_thresh;
+	u8	adhoc_tx_pwr;
+	u8	soft_ap;
+	u8	power_mgnt;
+	u8	ips_mode;
+	u8	lps_level;
+	u8	lps_chk_by_tp;
+	u8	smart_ps;
+#ifdef CONFIG_WMMPS_STA
+	u8	wmm_smart_ps;
+#endif /* CONFIG_WMMPS_STA */
+	u8   usb_rxagg_mode;
+	u8	dynamic_agg_enable;
+	u8	long_retry_lmt;
+	u8	short_retry_lmt;
+	u16	busy_thresh;
+	u16	max_bss_cnt;
+	u8	ack_policy;
+	u8	mp_mode;
+#if defined(CONFIG_MP_INCLUDED) && defined(CONFIG_RTW_CUSTOMER_STR)
+	u8 mp_customer_str;
+#endif
+	u8  mp_dm;
+	u8	software_encrypt;
+	u8	software_decrypt;
+#ifdef CONFIG_TX_EARLY_MODE
+	u8   early_mode;
+#endif
+	u8	acm_method;
+	/* WMM */
+	u8	wmm_enable;
+#ifdef CONFIG_WMMPS_STA
+	/* uapsd (unscheduled automatic power-save delivery) = a kind of wmmps */
+	u8	uapsd_max_sp_len;
+	/* BIT0: AC_VO UAPSD, BIT1: AC_VI UAPSD, BIT2: AC_BK UAPSD, BIT3: AC_BE UAPSD */
+	u8	uapsd_ac_enable;
+#endif /* CONFIG_WMMPS_STA */
+
+	WLAN_BSSID_EX    dev_network;
+
+	u8 tx_bw_mode;
+#ifdef CONFIG_AP_MODE
+	u8 bmc_tx_rate;
+#endif
+#ifdef CONFIG_80211N_HT
+	u8	ht_enable;
+	/* 0: 20 MHz, 1: 40 MHz, 2: 80 MHz, 3: 160MHz */
+	/* 2.4G use bit 0 ~ 3, 5G use bit 4 ~ 7 */
+	/* 0x21 means enable 2.4G 40MHz & 5G 80MHz */
+	u8	bw_mode;
+	u8	ampdu_enable;/* for tx */
+	u8	rx_stbc;
+	u8	rx_ampdu_amsdu;/* Rx A-MPDU Supports A-MSDU is permitted */
+	u8	tx_ampdu_amsdu;/* Tx A-MPDU Supports A-MSDU is permitted */
+	u8 rx_ampdu_sz_limit_by_nss_bw[4][4]; /* 1~4SS, BW20~BW160 */
+	/* Short GI support Bit Map */
+	/* BIT0 - 20MHz, 1: support, 0: non-support */
+	/* BIT1 - 40MHz, 1: support, 0: non-support */
+	/* BIT2 - 80MHz, 1: support, 0: non-support */
+	/* BIT3 - 160MHz, 1: support, 0: non-support */
+	u8	short_gi;
+	/* BIT0: Enable VHT LDPC Rx, BIT1: Enable VHT LDPC Tx, BIT4: Enable HT LDPC Rx, BIT5: Enable HT LDPC Tx */
+	u8	ldpc_cap;
+	/* BIT0: Enable VHT STBC Rx, BIT1: Enable VHT STBC Tx, BIT4: Enable HT STBC Rx, BIT5: Enable HT STBC Tx */
+	u8	stbc_cap;
+	/*
+	 * BIT0: Enable VHT SU Beamformer
+	 * BIT1: Enable VHT SU Beamformee
+	 * BIT2: Enable VHT MU Beamformer, depend on VHT SU Beamformer
+	 * BIT3: Enable VHT MU Beamformee, depend on VHT SU Beamformee
+	 * BIT4: Enable HT Beamformer
+	 * BIT5: Enable HT Beamformee
+	 */
+	u8	beamform_cap;
+	u8	beamformer_rf_num;
+	u8	beamformee_rf_num;
+#endif /* CONFIG_80211N_HT */
+
+#ifdef CONFIG_80211AC_VHT
+	u8	vht_enable; /* 0:disable, 1:enable, 2:auto */
+	u8	ampdu_factor;
+	u8 vht_rx_mcs_map[2];
+#endif /* CONFIG_80211AC_VHT */
+
+	u8	lowrate_two_xmit;
+
+	u8	rf_config ;
+	u8	low_power ;
+
+	u8	wifi_spec;/* !turbo_mode */
+	u8	special_rf_path; /* 0: 2T2R ,1: only turn on path A 1T1R */
+	char alpha2[2];
+	u8	channel_plan;
+	u8	excl_chs[MAX_CHANNEL_NUM];
+	u8	full_ch_in_p2p_handshake; /* 0: reply only softap channel, 1: reply full channel list*/
+
+#ifdef CONFIG_BT_COEXIST
+	u8	btcoex;
+	u8	bt_iso;
+	u8	bt_sco;
+	u8	bt_ampdu;
+	u8	ant_num;
+	u8	single_ant_path;
+#endif
+	BOOLEAN	bAcceptAddbaReq;
+
+	u8	antdiv_cfg;
+	u8	antdiv_type;
+	u8	drv_ant_band_switch;
+
+	u8	switch_usb_mode;
+
+	u8	usbss_enable;/* 0:disable,1:enable */
+	u8	hwpdn_mode;/* 0:disable,1:enable,2:decide by EFUSE config */
+	u8	hwpwrp_detect;/* 0:disable,1:enable */
+
+	u8	hw_wps_pbc;/* 0:disable,1:enable */
+
+#ifdef CONFIG_ADAPTOR_INFO_CACHING_FILE
+	char	adaptor_info_caching_file_path[PATH_LENGTH_MAX];
+#endif
+
+#ifdef CONFIG_LAYER2_ROAMING
+	u8	max_roaming_times; /* the max number driver will try to roaming */
+#endif
+
+#ifdef CONFIG_IOL
+	u8 fw_iol; /* enable iol without other concern */
+#endif
+
+#ifdef CONFIG_80211D
+	u8 enable80211d;
+#endif
+
+	u8 ifname[16];
+	u8 if2name[16];
+
+	u8 notch_filter;
+
+	/* for pll reference clock selction */
+	u8 pll_ref_clk_sel;
+
+	/* define for tx power adjust */
+#ifdef CONFIG_TXPWR_LIMIT
+	u8	RegEnableTxPowerLimit;
+#endif
+	u8	RegEnableTxPowerByRate;
+
+	u8 target_tx_pwr_valid;
+	s8 target_tx_pwr_2g[RF_PATH_MAX][RATE_SECTION_NUM];
+#ifdef CONFIG_IEEE80211_BAND_5GHZ
+	s8 target_tx_pwr_5g[RF_PATH_MAX][RATE_SECTION_NUM - 1];
+#endif
+
+	u8 tsf_update_pause_factor;
+	u8 tsf_update_restore_factor;
+
+	s8	TxBBSwing_2G;
+	s8	TxBBSwing_5G;
+	u8	AmplifierType_2G;
+	u8	AmplifierType_5G;
+	u8	bEn_RFE;
+	u8	RFE_Type;
+	u8	PowerTracking_Type;
+	u8	GLNA_Type;
+	u8  check_fw_ps;
+	u8	RegPwrTrimEnable;
+
+#ifdef CONFIG_LOAD_PHY_PARA_FROM_FILE
+	u8	load_phy_file;
+	u8	RegDecryptCustomFile;
+#endif
+#ifdef CONFIG_CONCURRENT_MODE
+	u8 virtual_iface_num;
+#endif
+	u8 qos_opt_enable;
+
+	u8 hiq_filter;
+	u8 adaptivity_en;
+	u8 adaptivity_mode;
+	s8 adaptivity_th_l2h_ini;
+	s8 adaptivity_th_edcca_hl_diff;
+
+	u8 boffefusemask;
+	BOOLEAN bFileMaskEfuse;
+#ifdef CONFIG_RTW_ACS
+	u8 acs_auto_scan;
+	u8 acs_mode;
+#endif
+
+#ifdef CONFIG_BACKGROUND_NOISE_MONITOR
+	u8 nm_mode;
+#endif
+	u32	reg_rxgain_offset_2g;
+	u32	reg_rxgain_offset_5gl;
+	u32	reg_rxgain_offset_5gm;
+	u32	reg_rxgain_offset_5gh;
+
+#ifdef CONFIG_DFS_MASTER
+	u8 dfs_region_domain;
+#endif
+
+#ifdef CONFIG_MCC_MODE
+	u8 en_mcc;
+	u32 rtw_mcc_single_tx_cri;
+	u32 rtw_mcc_ap_bw20_target_tx_tp;
+	u32 rtw_mcc_ap_bw40_target_tx_tp;
+	u32 rtw_mcc_ap_bw80_target_tx_tp;
+	u32 rtw_mcc_sta_bw20_target_tx_tp;
+	u32 rtw_mcc_sta_bw40_target_tx_tp;
+	u32 rtw_mcc_sta_bw80_target_tx_tp;
+	s8 rtw_mcc_policy_table_idx;
+	u8 rtw_mcc_duration;
+	u8 rtw_mcc_enable_runtime_duration;
+#endif /* CONFIG_MCC_MODE */
+
+#ifdef CONFIG_RTW_NAPI
+	u8 en_napi;
+#ifdef CONFIG_RTW_NAPI_DYNAMIC
+	u32 napi_threshold;	/* unit: Mbps */
+#endif /* CONFIG_RTW_NAPI_DYNAMIC */
+#ifdef CONFIG_RTW_GRO
+	u8 en_gro;
+#endif /* CONFIG_RTW_GRO */
+#endif /* CONFIG_RTW_NAPI */
+
+#ifdef CONFIG_WOWLAN
+	u8 wakeup_event;
+#endif
+
+#ifdef CONFIG_SUPPORT_TRX_SHARED
+	u8 trx_share_mode;
+#endif
+	u8 check_hw_status;
+
+	u32 pci_aspm_config;
+
+	u8 iqk_fw_offload;
+	u8 ch_switch_offload;
+
+#ifdef CONFIG_TDLS
+	u8 en_tdls;
+#endif
+
+#ifdef CONFIG_ADVANCE_OTA
+	u8	adv_ota;
+#endif
+
+#ifdef CONFIG_FW_OFFLOAD_PARAM_INIT
+	u8 fw_param_init;
+#endif
+#ifdef CONFIG_DYNAMIC_SOML
+	u8 dyn_soml_en;
+	u8 dyn_soml_train_num;
+	u8 dyn_soml_interval;
+	u8 dyn_soml_period;
+	u8 dyn_soml_delay;
+#endif
+#ifdef CONFIG_FW_HANDLE_TXBCN
+	u8 fw_tbtt_rpt;
+#endif
+
+#ifdef DBG_LA_MODE
+	u8 la_mode_en;
+#endif
+};
+
+/* For registry parameters */
+#define RGTRY_OFT(field) ((ULONG)FIELD_OFFSET(struct registry_priv, field))
+#define RGTRY_SZ(field)   sizeof(((struct registry_priv *) 0)->field)
+
+#define GetRegAmplifierType2G(_Adapter)	(_Adapter->registrypriv.AmplifierType_2G)
+#define GetRegAmplifierType5G(_Adapter)	(_Adapter->registrypriv.AmplifierType_5G)
+
+#define GetRegTxBBSwing_2G(_Adapter)	(_Adapter->registrypriv.TxBBSwing_2G)
+#define GetRegTxBBSwing_5G(_Adapter)	(_Adapter->registrypriv.TxBBSwing_5G)
+
+#define GetRegbENRFEType(_Adapter)	(_Adapter->registrypriv.bEn_RFE)
+#define GetRegRFEType(_Adapter)	(_Adapter->registrypriv.RFE_Type)
+#define GetRegGLNAType(_Adapter)	(_Adapter->registrypriv.GLNA_Type)
+#define GetRegPowerTrackingType(_Adapter)	(_Adapter->registrypriv.PowerTracking_Type)
+
+#define BSSID_OFT(field) ((ULONG)FIELD_OFFSET(WLAN_BSSID_EX, field))
+#define BSSID_SZ(field)   sizeof(((PWLAN_BSSID_EX) 0)->field)
+
+#define BW_MODE_2G(bw_mode) ((bw_mode) & 0x0F)
+#define BW_MODE_5G(bw_mode) ((bw_mode) >> 4)
+#ifdef CONFIG_80211N_HT
+#define REGSTY_BW_2G(regsty) BW_MODE_2G((regsty)->bw_mode)
+#define REGSTY_BW_5G(regsty) BW_MODE_5G((regsty)->bw_mode)
+#else
+#define REGSTY_BW_2G(regsty) CHANNEL_WIDTH_20
+#define REGSTY_BW_5G(regsty) CHANNEL_WIDTH_20
+#endif
+#define REGSTY_IS_BW_2G_SUPPORT(regsty, bw) (REGSTY_BW_2G((regsty)) >= (bw))
+#define REGSTY_IS_BW_5G_SUPPORT(regsty, bw) (REGSTY_BW_5G((regsty)) >= (bw))
+
+#define REGSTY_IS_11AC_ENABLE(regsty) ((regsty)->vht_enable != 0)
+#define REGSTY_IS_11AC_AUTO(regsty) ((regsty)->vht_enable == 2)
+
+typedef struct rtw_if_operations {
+	int __must_check (*read)(struct dvobj_priv *d, unsigned int addr, void *buf,
+				size_t len, bool fixed);
+	int __must_check (*write)(struct dvobj_priv *d, unsigned int addr, void *buf,
+				 size_t len, bool fixed);
+} RTW_IF_OPS, *PRTW_IF_OPS;
+
+#ifdef CONFIG_SDIO_HCI
+	#include <drv_types_sdio.h>
+	#define INTF_DATA	SDIO_DATA
+	#define INTF_OPS	PRTW_IF_OPS
+#elif defined(CONFIG_GSPI_HCI)
+	#include <drv_types_gspi.h>
+	#define INTF_DATA GSPI_DATA
+#elif defined(CONFIG_PCI_HCI)
+	#include <drv_types_pci.h>
+#endif
+
+#ifdef CONFIG_CONCURRENT_MODE
+	#define is_primary_adapter(adapter) (adapter->adapter_type == PRIMARY_ADAPTER)
+	#define is_vir_adapter(adapter) (adapter->adapter_type == VIRTUAL_ADAPTER)
+	#define get_hw_port(adapter) (adapter->hw_port)
+#else
+	#define is_primary_adapter(adapter) (1)
+	#define is_vir_adapter(adapter) (0)
+	#define get_hw_port(adapter) (HW_PORT0)
+#endif
+#define GET_PRIMARY_ADAPTER(padapter) (((_adapter *)padapter)->dvobj->padapters[IFACE_ID0])
+#define GET_IFACE_NUMS(padapter) (((_adapter *)padapter)->dvobj->iface_nums)
+#define GET_ADAPTER(padapter, iface_id) (((_adapter *)padapter)->dvobj->padapters[iface_id])
+
+#define GetDefaultAdapter(padapter)	padapter
+
+enum _IFACE_ID {
+	IFACE_ID0, /*PRIMARY_ADAPTER*/
+	IFACE_ID1,
+	IFACE_ID2,
+	IFACE_ID3,
+	IFACE_ID4,
+	IFACE_ID5,
+	IFACE_ID6,
+	IFACE_ID7,
+	IFACE_ID_MAX,
+};
+
+#define VIF_START_ID	1
+
+#ifdef CONFIG_DBG_COUNTER
+
+struct rx_logs {
+	u32 intf_rx;
+	u32 intf_rx_err_recvframe;
+	u32 intf_rx_err_skb;
+	u32 intf_rx_report;
+	u32 core_rx;
+	u32 core_rx_pre;
+	u32 core_rx_pre_ver_err;
+	u32 core_rx_pre_mgmt;
+	u32 core_rx_pre_mgmt_err_80211w;
+	u32 core_rx_pre_mgmt_err;
+	u32 core_rx_pre_ctrl;
+	u32 core_rx_pre_ctrl_err;
+	u32 core_rx_pre_data;
+	u32 core_rx_pre_data_wapi_seq_err;
+	u32 core_rx_pre_data_wapi_key_err;
+	u32 core_rx_pre_data_handled;
+	u32 core_rx_pre_data_err;
+	u32 core_rx_pre_data_unknown;
+	u32 core_rx_pre_unknown;
+	u32 core_rx_enqueue;
+	u32 core_rx_dequeue;
+	u32 core_rx_post;
+	u32 core_rx_post_decrypt;
+	u32 core_rx_post_decrypt_wep;
+	u32 core_rx_post_decrypt_tkip;
+	u32 core_rx_post_decrypt_aes;
+	u32 core_rx_post_decrypt_wapi;
+	u32 core_rx_post_decrypt_hw;
+	u32 core_rx_post_decrypt_unknown;
+	u32 core_rx_post_decrypt_err;
+	u32 core_rx_post_defrag_err;
+	u32 core_rx_post_portctrl_err;
+	u32 core_rx_post_indicate;
+	u32 core_rx_post_indicate_in_oder;
+	u32 core_rx_post_indicate_reoder;
+	u32 core_rx_post_indicate_err;
+	u32 os_indicate;
+	u32 os_indicate_ap_mcast;
+	u32 os_indicate_ap_forward;
+	u32 os_indicate_ap_self;
+	u32 os_indicate_err;
+	u32 os_netif_ok;
+	u32 os_netif_err;
+};
+
+struct tx_logs {
+	u32 os_tx;
+	u32 os_tx_err_up;
+	u32 os_tx_err_xmit;
+	u32 os_tx_m2u;
+	u32 os_tx_m2u_ignore_fw_linked;
+	u32 os_tx_m2u_ignore_self;
+	u32 os_tx_m2u_entry;
+	u32 os_tx_m2u_entry_err_xmit;
+	u32 os_tx_m2u_entry_err_skb;
+	u32 os_tx_m2u_stop;
+	u32 core_tx;
+	u32 core_tx_err_pxmitframe;
+	u32 core_tx_err_brtx;
+	u32 core_tx_upd_attrib;
+	u32 core_tx_upd_attrib_adhoc;
+	u32 core_tx_upd_attrib_sta;
+	u32 core_tx_upd_attrib_ap;
+	u32 core_tx_upd_attrib_unknown;
+	u32 core_tx_upd_attrib_dhcp;
+	u32 core_tx_upd_attrib_icmp;
+	u32 core_tx_upd_attrib_active;
+	u32 core_tx_upd_attrib_err_ucast_sta;
+	u32 core_tx_upd_attrib_err_ucast_ap_link;
+	u32 core_tx_upd_attrib_err_sta;
+	u32 core_tx_upd_attrib_err_link;
+	u32 core_tx_upd_attrib_err_sec;
+	u32 core_tx_ap_enqueue_warn_fwstate;
+	u32 core_tx_ap_enqueue_warn_sta;
+	u32 core_tx_ap_enqueue_warn_nosta;
+	u32 core_tx_ap_enqueue_warn_link;
+	u32 core_tx_ap_enqueue_warn_trigger;
+	u32 core_tx_ap_enqueue_mcast;
+	u32 core_tx_ap_enqueue_ucast;
+	u32 core_tx_ap_enqueue;
+	u32 intf_tx;
+	u32 intf_tx_pending_ac;
+	u32 intf_tx_pending_fw_under_survey;
+	u32 intf_tx_pending_fw_under_linking;
+	u32 intf_tx_pending_xmitbuf;
+	u32 intf_tx_enqueue;
+	u32 core_tx_enqueue;
+	u32 core_tx_enqueue_class;
+	u32 core_tx_enqueue_class_err_sta;
+	u32 core_tx_enqueue_class_err_nosta;
+	u32 core_tx_enqueue_class_err_fwlink;
+	u32 intf_tx_direct;
+	u32 intf_tx_direct_err_coalesce;
+	u32 intf_tx_dequeue;
+	u32 intf_tx_dequeue_err_coalesce;
+	u32 intf_tx_dump_xframe;
+	u32 intf_tx_dump_xframe_err_txdesc;
+	u32 intf_tx_dump_xframe_err_port;
+};
+
+struct int_logs {
+	u32 all;
+	u32 err;
+	u32 tbdok;
+	u32 tbder;
+	u32 bcnderr;
+	u32 bcndma;
+	u32 bcndma_e;
+	u32 rx;
+	u32 rx_rdu;
+	u32 rx_fovw;
+	u32 txfovw;
+	u32 mgntok;
+	u32 highdok;
+	u32 bkdok;
+	u32 bedok;
+	u32 vidok;
+	u32 vodok;
+};
+
+#endif /* CONFIG_DBG_COUNTER */
+
+struct debug_priv {
+	u32 dbg_sdio_free_irq_error_cnt;
+	u32 dbg_sdio_alloc_irq_error_cnt;
+	u32 dbg_sdio_free_irq_cnt;
+	u32 dbg_sdio_alloc_irq_cnt;
+	u32 dbg_sdio_deinit_error_cnt;
+	u32 dbg_sdio_init_error_cnt;
+	u32 dbg_suspend_error_cnt;
+	u32 dbg_suspend_cnt;
+	u32 dbg_resume_cnt;
+	u32 dbg_resume_error_cnt;
+	u32 dbg_deinit_fail_cnt;
+	u32 dbg_carddisable_cnt;
+	u32 dbg_carddisable_error_cnt;
+	u32 dbg_ps_insuspend_cnt;
+	u32	dbg_dev_unload_inIPS_cnt;
+	u32 dbg_wow_leave_ps_fail_cnt;
+	u32 dbg_scan_pwr_state_cnt;
+	u32 dbg_downloadfw_pwr_state_cnt;
+	u32 dbg_fw_read_ps_state_fail_cnt;
+	u32 dbg_leave_ips_fail_cnt;
+	u32 dbg_leave_lps_fail_cnt;
+	u32 dbg_h2c_leave32k_fail_cnt;
+	u32 dbg_diswow_dload_fw_fail_cnt;
+	u32 dbg_enwow_dload_fw_fail_cnt;
+	u32 dbg_ips_drvopen_fail_cnt;
+	u32 dbg_poll_fail_cnt;
+	u32 dbg_rpwm_toogle_cnt;
+	u32 dbg_rpwm_timeout_fail_cnt;
+	u32 dbg_sreset_cnt;
+	u32 dbg_fw_mem_dl_error_cnt;
+	u64 dbg_rx_fifo_last_overflow;
+	u64 dbg_rx_fifo_curr_overflow;
+	u64 dbg_rx_fifo_diff_overflow;
+};
+
+struct rtw_traffic_statistics {
+	/* tx statistics */
+	u64	tx_bytes;
+	u64	tx_pkts;
+	u64	tx_drop;
+	u64	cur_tx_bytes;
+	u64	last_tx_bytes;
+	u32	cur_tx_tp; /* Tx throughput in Mbps. */
+
+	/* rx statistics */
+	u64	rx_bytes;
+	u64	rx_pkts;
+	u64	rx_drop;
+	u64	cur_rx_bytes;
+	u64	last_rx_bytes;
+	u32	cur_rx_tp; /* Rx throughput in Mbps. */
+};
+
+#define SEC_CAP_CHK_BMC	BIT0
+
+#define SEC_STATUS_STA_PK_GK_CONFLICT_DIS_BMC_SEARCH	BIT0
+
+struct sec_cam_bmp {
+	u32 m0;
+#if (SEC_CAM_ENT_NUM_SW_LIMIT > 32)
+	u32 m1;
+#endif
+#if (SEC_CAM_ENT_NUM_SW_LIMIT > 64)
+	u32 m2;
+#endif
+#if (SEC_CAM_ENT_NUM_SW_LIMIT > 96)
+	u32 m3;
+#endif
+};
+
+struct cam_ctl_t {
+	_lock lock;
+
+	u8 sec_cap;
+	u32 flags;
+
+	u8 num;
+	struct sec_cam_bmp used;
+
+	_mutex sec_cam_access_mutex;
+};
+
+struct sec_cam_ent {
+	u16 ctrl;
+	u8 mac[ETH_ALEN];
+	u8 key[16];
+};
+
+#define KEY_FMT "%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x"
+#define KEY_ARG(x) ((u8 *)(x))[0], ((u8 *)(x))[1], ((u8 *)(x))[2], ((u8 *)(x))[3], ((u8 *)(x))[4], ((u8 *)(x))[5], \
+	((u8 *)(x))[6], ((u8 *)(x))[7], ((u8 *)(x))[8], ((u8 *)(x))[9], ((u8 *)(x))[10], ((u8 *)(x))[11], \
+	((u8 *)(x))[12], ((u8 *)(x))[13], ((u8 *)(x))[14], ((u8 *)(x))[15]
+
+#define RTW_DEFAULT_MGMT_MACID 1
+
+struct macid_bmp {
+	u32 m0;
+#if (MACID_NUM_SW_LIMIT > 32)
+	u32 m1;
+#endif
+#if (MACID_NUM_SW_LIMIT > 64)
+	u32 m2;
+#endif
+#if (MACID_NUM_SW_LIMIT > 96)
+	u32 m3;
+#endif
+};
+
+#ifdef CONFIG_CLIENT_PORT_CFG
+struct clt_port_t{
+	_lock lock;
+	u8 bmp;
+	s8 num;
+};
+#define get_clt_num(adapter) (adapter_to_dvobj(adapter)->clt_port.num)
+#endif
+
+struct macid_ctl_t {
+	_lock lock;
+	u8 num;
+	struct macid_bmp used;
+	struct macid_bmp bmc;
+	struct macid_bmp if_g[CONFIG_IFACE_NUMBER];
+	struct macid_bmp ch_g[2]; /* 2 ch concurrency */
+
+	u8 iface_bmc[CONFIG_IFACE_NUMBER]; /* bmc TX macid for each iface*/
+
+	u8 h2c_msr[MACID_NUM_SW_LIMIT];
+	u8 bw[MACID_NUM_SW_LIMIT];
+	u8 vht_en[MACID_NUM_SW_LIMIT];
+	u32 rate_bmp0[MACID_NUM_SW_LIMIT];
+	u32 rate_bmp1[MACID_NUM_SW_LIMIT];
+
+	struct sta_info *sta[MACID_NUM_SW_LIMIT]; /* corresponding stainfo when macid is not shared */
+
+	/* macid sleep registers */
+	u16 reg_sleep_m0;
+#if (MACID_NUM_SW_LIMIT > 32)
+	u16 reg_sleep_m1;
+#endif
+#if (MACID_NUM_SW_LIMIT > 64)
+	u16 reg_sleep_m2;
+#endif
+#if (MACID_NUM_SW_LIMIT > 96)
+	u16 reg_sleep_m3;
+#endif
+};
+
+/* used for rf_ctl_t.rate_bmp_cck_ofdm */
+#define RATE_BMP_CCK		0x000F
+#define RATE_BMP_OFDM		0xFFF0
+#define RATE_BMP_HAS_CCK(_bmp_cck_ofdm)		(_bmp_cck_ofdm & RATE_BMP_CCK)
+#define RATE_BMP_HAS_OFDM(_bmp_cck_ofdm)	(_bmp_cck_ofdm & RATE_BMP_OFDM)
+#define RATE_BMP_GET_CCK(_bmp_cck_ofdm)		(_bmp_cck_ofdm & RATE_BMP_CCK)
+#define RATE_BMP_GET_OFDM(_bmp_cck_ofdm)	((_bmp_cck_ofdm & RATE_BMP_OFDM) >> 4)
+
+/* used for rf_ctl_t.rate_bmp_ht_by_bw */
+#define RATE_BMP_HT_1SS		0x000000FF
+#define RATE_BMP_HT_2SS		0x0000FF00
+#define RATE_BMP_HT_3SS		0x00FF0000
+#define RATE_BMP_HT_4SS		0xFF000000
+#define RATE_BMP_HAS_HT_1SS(_bmp_ht)		(_bmp_ht & RATE_BMP_HT_1SS)
+#define RATE_BMP_HAS_HT_2SS(_bmp_ht)		(_bmp_ht & RATE_BMP_HT_2SS)
+#define RATE_BMP_HAS_HT_3SS(_bmp_ht)		(_bmp_ht & RATE_BMP_HT_3SS)
+#define RATE_BMP_HAS_HT_4SS(_bmp_ht)		(_bmp_ht & RATE_BMP_HT_4SS)
+#define RATE_BMP_GET_HT_1SS(_bmp_ht)		(_bmp_ht & RATE_BMP_HT_1SS)
+#define RATE_BMP_GET_HT_2SS(_bmp_ht)		((_bmp_ht & RATE_BMP_HT_2SS) >> 8)
+#define RATE_BMP_GET_HT_3SS(_bmp_ht)		((_bmp_ht & RATE_BMP_HT_3SS) >> 16)
+#define RATE_BMP_GET_HT_4SS(_bmp_ht)		((_bmp_ht & RATE_BMP_HT_4SS) >> 24)
+
+/* used for rf_ctl_t.rate_bmp_vht_by_bw */
+#define RATE_BMP_VHT_1SS	0x000003FF
+#define RATE_BMP_VHT_2SS	0x000FFC00
+#define RATE_BMP_VHT_3SS	0x3FF00000
+#define RATE_BMP_HAS_VHT_1SS(_bmp_vht)		(_bmp_vht & RATE_BMP_VHT_1SS)
+#define RATE_BMP_HAS_VHT_2SS(_bmp_vht)		(_bmp_vht & RATE_BMP_VHT_2SS)
+#define RATE_BMP_HAS_VHT_3SS(_bmp_vht)		(_bmp_vht & RATE_BMP_VHT_3SS)
+#define RATE_BMP_GET_VHT_1SS(_bmp_vht)		(_bmp_vht & RATE_BMP_VHT_1SS)
+#define RATE_BMP_GET_VHT_2SS(_bmp_vht)		((_bmp_vht & RATE_BMP_VHT_2SS) >> 10)
+#define RATE_BMP_GET_VHT_3SS(_bmp_vht)		((_bmp_vht & RATE_BMP_VHT_3SS) >> 20)
+
+#define TXPWR_LMT_REF_VHT_FROM_HT	BIT0
+#define TXPWR_LMT_REF_HT_FROM_VHT	BIT1
+
+#define TXPWR_LMT_HAS_CCK_1T	BIT0
+#define TXPWR_LMT_HAS_CCK_2T	BIT1
+#define TXPWR_LMT_HAS_CCK_3T	BIT2
+#define TXPWR_LMT_HAS_CCK_4T	BIT3
+#define TXPWR_LMT_HAS_OFDM_1T	BIT4
+#define TXPWR_LMT_HAS_OFDM_2T	BIT5
+#define TXPWR_LMT_HAS_OFDM_3T	BIT6
+#define TXPWR_LMT_HAS_OFDM_4T	BIT7
+
+#define OFFCHS_NONE			0
+#define OFFCHS_LEAVING_OP	1
+#define OFFCHS_LEAVE_OP		2
+#define OFFCHS_BACKING_OP	3
+
+struct rf_ctl_t {
+	const struct country_chplan *country_ent;
+	u8 ChannelPlan;
+	u8 max_chan_nums;
+	RT_CHANNEL_INFO channel_set[MAX_CHANNEL_NUM];
+	struct p2p_channels channel_list;
+
+	_mutex offch_mutex;
+	u8 offch_state;
+
+	/* used for debug or by tx power limit */
+	u16 rate_bmp_cck_ofdm;		/* 20MHz */
+	u32 rate_bmp_ht_by_bw[2];	/* 20MHz, 40MHz. 4SS supported */
+	u32 rate_bmp_vht_by_bw[4];	/* 20MHz, 40MHz, 80MHz, 160MHz. up to 3SS supported */
+
+	/* used by tx power limit */
+	u8 highest_ht_rate_bw_bmp;
+	u8 highest_vht_rate_bw_bmp;
+
+#ifdef CONFIG_TXPWR_LIMIT
+	_mutex txpwr_lmt_mutex;
+	_list reg_exc_list;
+	u8 regd_exc_num;
+	_list txpwr_lmt_list;
+	u8 txpwr_regd_num;
+	const char *regd_name;
+
+	u8 txpwr_lmt_2g_cck_ofdm_state;
+	#ifdef CONFIG_IEEE80211_BAND_5GHZ
+	u8 txpwr_lmt_5g_cck_ofdm_state;
+	u8 txpwr_lmt_5g_20_40_ref;
+	#endif
+#endif
+
+	u8 ch_sel_same_band_prefer;
+
+#ifdef CONFIG_DFS
+	u8 csa_ch;
+
+#ifdef CONFIG_DFS_MASTER
+	_timer radar_detect_timer;
+	bool radar_detect_by_others;
+	u8 radar_detect_enabled;
+	bool radar_detected;
+
+	u8 radar_detect_ch;
+	u8 radar_detect_bw;
+	u8 radar_detect_offset;
+
+	systime cac_start_time;
+	systime cac_end_time;
+	u8 cac_force_stop;
+
+#ifdef CONFIG_DFS_SLAVE_WITH_RADAR_DETECT
+	u8 dfs_slave_with_rd;
+#endif
+	u8 dfs_ch_sel_d_flags;
+
+	u8 dbg_dfs_fake_radar_detect_cnt;
+	u8 dbg_dfs_radar_detect_trigger_non;
+	u8 dbg_dfs_choose_dfs_ch_first;
+#endif /* CONFIG_DFS_MASTER */
+#endif /* CONFIG_DFS */
+};
+
+#define RTW_CAC_STOPPED 0
+#ifdef CONFIG_DFS_MASTER
+#define IS_CAC_STOPPED(rfctl) ((rfctl)->cac_end_time == RTW_CAC_STOPPED)
+#define IS_CH_WAITING(rfctl) (!IS_CAC_STOPPED(rfctl) && rtw_time_after((rfctl)->cac_end_time, rtw_get_current_time()))
+#define IS_UNDER_CAC(rfctl) (IS_CH_WAITING(rfctl) && rtw_time_after(rtw_get_current_time(), (rfctl)->cac_start_time))
+#define IS_RADAR_DETECTED(rfctl) ((rfctl)->radar_detected)
+#else
+#define IS_CAC_STOPPED(rfctl) 1
+#define IS_CH_WAITING(rfctl) 0
+#define IS_UNDER_CAC(rfctl) 0
+#define IS_RADAR_DETECTED(rfctl) 0
+#endif /* CONFIG_DFS_MASTER */
+
+#ifdef CONFIG_DFS_SLAVE_WITH_RADAR_DETECT
+#define IS_DFS_SLAVE_WITH_RD(rfctl) ((rfctl)->dfs_slave_with_rd)
+#else
+#define IS_DFS_SLAVE_WITH_RD(rfctl) 0
+#endif
+
+#ifdef CONFIG_MBSSID_CAM
+#define TOTAL_MBID_CAM_NUM	8
+#define INVALID_CAM_ID			0xFF
+struct mbid_cam_ctl_t {
+	_lock lock;
+	u8 bitmap;
+	ATOMIC_T mbid_entry_num;
+};
+struct mbid_cam_cache {
+	u8 iface_id;
+	/*u8 role;*/ /*WIFI_STATION_STATE or WIFI_AP_STATE*/
+	u8 mac_addr[ETH_ALEN];
+};
+#endif /*CONFIG_MBSSID_CAM*/
+
+#ifdef RTW_HALMAC
+struct halmac_indicator {
+	struct submit_ctx *sctx;
+	u8 *buffer;
+	u32 buf_size;
+	u32 ret_size;
+	u32 status;
+};
+
+struct halmacpriv {
+	/* flags */
+
+	/* For asynchronous functions */
+	struct halmac_indicator *indicator;
+
+	/* Hardware parameters */
+#ifdef CONFIG_SDIO_HCI
+	/* Store hardware tx queue page number setting */
+	u16 txpage[HW_QUEUE_ENTRY];
+#endif /* CONFIG_SDIO_HCI */
+};
+#endif /* RTW_HALMAC */
+
+#ifdef CONFIG_FW_MULTI_PORT_SUPPORT
+/*info for H2C-0x2C*/
+struct dft_info {
+	u8 port_id;
+	u8 mac_id;
+};
+#endif
+
+#ifdef CONFIG_HW_P0_TSF_SYNC
+struct tsf_info {
+	u8 sync_port;/*port_x's tsf sync to port_0*/
+	u8 offset; /*tsf timer offset*/
+};
+#endif
+
+struct dvobj_priv {
+	/*-------- below is common data --------*/
+	u8	chip_type;
+	u8	HardwareType;
+	u8	interface_type;/*USB,SDIO,SPI,PCI*/
+
+	ATOMIC_T	bSurpriseRemoved;
+	ATOMIC_T	bDriverStopped;
+
+	s32	processing_dev_remove;
+
+	struct debug_priv drv_dbg;
+
+	_mutex hw_init_mutex;
+	_mutex h2c_fwcmd_mutex;
+
+#ifdef CONFIG_RTW_CUSTOMER_STR
+	_mutex customer_str_mutex;
+	struct submit_ctx *customer_str_sctx;
+	u8 customer_str[RTW_CUSTOMER_STR_LEN];
+#endif
+
+	_mutex setch_mutex;
+	_mutex setbw_mutex;
+	_mutex rf_read_reg_mutex;
+#ifdef CONFIG_SDIO_INDIRECT_ACCESS
+	_mutex sd_indirect_access_mutex;
+#endif
+
+#ifdef CONFIG_SYSON_INDIRECT_ACCESS
+	_mutex syson_indirect_access_mutex;	/* System On Reg R/W */
+#endif
+
+	unsigned char	oper_channel; /* saved channel info when call set_channel_bw */
+	unsigned char	oper_bwmode;
+	unsigned char	oper_ch_offset;/* PRIME_CHNL_OFFSET */
+	systime on_oper_ch_time;
+
+	_adapter *padapters[CONFIG_IFACE_NUMBER];/*IFACE_ID_MAX*/
+	u8 iface_nums; /* total number of ifaces used runtime */
+	struct mi_state iface_state;
+
+#ifdef CONFIG_AP_MODE
+	#ifdef CONFIG_SUPPORT_MULTI_BCN
+	u8		nr_ap_if; /* total interface number of ap /go /mesh / nan mode. */
+	u16		inter_bcn_space; /* unit:ms */
+	_queue	ap_if_q;
+	u8		vap_map;
+	u8		fw_bcn_offload;
+	u8		vap_tbtt_rpt_map;
+	#endif /*CONFIG_SUPPORT_MULTI_BCN*/
+	#ifdef CONFIG_RTW_REPEATER_SON
+	struct rtw_rson_struct  rson_data;
+	#endif
+#endif
+#ifdef CONFIG_CLIENT_PORT_CFG
+	struct clt_port_t clt_port;
+#endif
+
+#ifdef CONFIG_HW_P0_TSF_SYNC
+	struct tsf_info p0_tsf;
+#endif
+	systime periodic_tsf_update_etime;
+	_timer periodic_tsf_update_end_timer;
+
+	struct macid_ctl_t macid_ctl;
+
+	struct cam_ctl_t cam_ctl;
+	struct sec_cam_ent cam_cache[SEC_CAM_ENT_NUM_SW_LIMIT];
+
+#ifdef CONFIG_MBSSID_CAM
+	struct mbid_cam_ctl_t mbid_cam_ctl;
+	struct mbid_cam_cache mbid_cam_cache[TOTAL_MBID_CAM_NUM];
+#endif
+
+	struct rf_ctl_t rf_ctl;
+
+	/* For 92D, DMDP have 2 interface. */
+	u8	InterfaceNumber;
+	u8	NumInterfaces;
+
+	/* In /Out Pipe information */
+	int	RtInPipe[2];
+	int	RtOutPipe[4];
+	u8	Queue2Pipe[HW_QUEUE_ENTRY];/* for out pipe mapping */
+
+	u8	irq_alloc;
+	ATOMIC_T continual_io_error;
+
+	ATOMIC_T disable_func;
+
+	u8 xmit_block;
+	_lock xmit_block_lock;
+
+	struct pwrctrl_priv pwrctl_priv;
+
+	struct rtw_traffic_statistics	traffic_stat;
+
+#ifdef PLATFORM_LINUX
+	_thread_hdl_ rtnl_lock_holder;
+
+	#if defined(CONFIG_IOCTL_CFG80211) && defined(RTW_SINGLE_WIPHY)
+	struct wiphy *wiphy;
+	#endif
+#endif /* PLATFORM_LINUX */
+
+#ifdef CONFIG_SWTIMER_BASED_TXBCN
+	_timer txbcn_timer;
+#endif
+	_timer dynamic_chk_timer; /* dynamic/periodic check timer */
+	
+#ifdef CONFIG_RTW_NAPI_DYNAMIC
+	u8 en_napi_dynamic;
+#endif /* CONFIG_RTW_NAPI_DYNAMIC */
+
+#ifdef RTW_HALMAC
+	void *halmac;
+	struct halmacpriv hmpriv;
+#endif /* RTW_HALMAC */
+
+#ifdef CONFIG_FW_MULTI_PORT_SUPPORT
+	/*info for H2C-0x2C*/
+	struct dft_info dft;
+#endif
+
+#ifdef CONFIG_RTW_WIFI_HAL
+	u32 nodfs;
+#endif
+
+	/*-------- below is for SDIO INTERFACE --------*/
+
+#ifdef INTF_DATA
+	INTF_DATA intf_data;
+#endif
+#ifdef INTF_OPS
+	INTF_OPS intf_ops;
+#endif
+
+	/*-------- below is for USB INTERFACE --------*/
+
+#ifdef CONFIG_USB_HCI
+
+	u8	usb_speed; /* 1.1, 2.0 or 3.0 */
+	u8	nr_endpoint;
+	u8	RtNumInPipes;
+	u8	RtNumOutPipes;
+	int	ep_num[6]; /* endpoint number */
+
+	int	RegUsbSS;
+
+	_sema	usb_suspend_sema;
+
+#ifdef CONFIG_USB_VENDOR_REQ_MUTEX
+	_mutex  usb_vendor_req_mutex;
+#endif
+
+#ifdef CONFIG_USB_VENDOR_REQ_BUFFER_PREALLOC
+	u8 *usb_alloc_vendor_req_buf;
+	u8 *usb_vendor_req_buf;
+#endif
+
+#ifdef PLATFORM_WINDOWS
+	/* related device objects */
+	PDEVICE_OBJECT	pphysdevobj;/* pPhysDevObj; */
+	PDEVICE_OBJECT	pfuncdevobj;/* pFuncDevObj; */
+	PDEVICE_OBJECT	pnextdevobj;/* pNextDevObj; */
+
+	u8	nextdevstacksz;/* unsigned char NextDeviceStackSize;	 */ /* = (CHAR)CEdevice->pUsbDevObj->StackSize + 1; */
+
+	/* urb for control diescriptor request */
+
+#ifdef PLATFORM_OS_XP
+	struct _URB_CONTROL_DESCRIPTOR_REQUEST descriptor_urb;
+	PUSB_CONFIGURATION_DESCRIPTOR	pconfig_descriptor;/* UsbConfigurationDescriptor; */
+#endif
+
+#ifdef PLATFORM_OS_CE
+	WCHAR			active_path[MAX_ACTIVE_REG_PATH];	/* adapter regpath */
+	USB_EXTENSION	usb_extension;
+
+	_nic_hdl		pipehdls_r8192c[0x10];
+#endif
+
+	u32	config_descriptor_len;/* ULONG UsbConfigurationDescriptorLength; */
+#endif/* PLATFORM_WINDOWS */
+
+#ifdef PLATFORM_LINUX
+	struct usb_interface *pusbintf;
+	struct usb_device *pusbdev;
+#endif/* PLATFORM_LINUX */
+
+#ifdef PLATFORM_FREEBSD
+	struct usb_interface *pusbintf;
+	struct usb_device *pusbdev;
+#endif/* PLATFORM_FREEBSD */
+
+#endif/* CONFIG_USB_HCI */
+
+	/*-------- below is for PCIE INTERFACE --------*/
+
+#ifdef CONFIG_PCI_HCI
+
+#ifdef PLATFORM_LINUX
+	struct pci_dev *ppcidev;
+
+	/* PCI MEM map */
+	unsigned long	pci_mem_end;	/* shared mem end	*/
+	unsigned long	pci_mem_start;	/* shared mem start	*/
+
+	/* PCI IO map */
+	unsigned long	pci_base_addr;	/* device I/O address	*/
+
+#ifdef RTK_129X_PLATFORM
+	unsigned long	ctrl_start;
+	/* PCI MASK addr */
+	unsigned long	mask_addr;
+
+	/* PCI TRANSLATE addr */
+	unsigned long	tran_addr;
+
+	_lock   io_reg_lock;
+#endif
+
+	/* PciBridge */
+	struct pci_priv	pcipriv;
+
+	unsigned int irq; /* get from pci_dev.irq, store to net_device.irq */
+	u16	irqline;
+	u8	irq_enabled;
+	RT_ISR_CONTENT	isr_content;
+	_lock	irq_th_lock;
+
+	/* ASPM */
+	u8	const_pci_aspm;
+	u8	const_amdpci_aspm;
+	u8	const_hwsw_rfoff_d3;
+	u8	const_support_pciaspm;
+	/* pci-e bridge */
+	u8	const_hostpci_aspm_setting;
+	/* pci-e device */
+	u8	const_devicepci_aspm_setting;
+	u8	b_support_aspm; /* If it supports ASPM, Offset[560h] = 0x40, otherwise Offset[560h] = 0x00. */
+	u8	b_support_backdoor;
+	u8	bdma64;
+#endif/* PLATFORM_LINUX */
+
+#endif/* CONFIG_PCI_HCI */
+
+#ifdef CONFIG_MCC_MODE
+	struct mcc_obj_priv mcc_objpriv;
+#endif /*CONFIG_MCC_MODE */
+};
+
+#define DEV_STA_NUM(_dvobj)			MSTATE_STA_NUM(&((_dvobj)->iface_state))
+#define DEV_STA_LD_NUM(_dvobj)		MSTATE_STA_LD_NUM(&((_dvobj)->iface_state))
+#define DEV_STA_LG_NUM(_dvobj)		MSTATE_STA_LG_NUM(&((_dvobj)->iface_state))
+#define DEV_TDLS_LD_NUM(_dvobj)		MSTATE_TDLS_LD_NUM(&((_dvobj)->iface_state))
+#define DEV_AP_NUM(_dvobj)			MSTATE_AP_NUM(&((_dvobj)->iface_state))
+#define DEV_AP_STARTING_NUM(_dvobj)	MSTATE_AP_STARTING_NUM(&((_dvobj)->iface_state))
+#define DEV_AP_LD_NUM(_dvobj)		MSTATE_AP_LD_NUM(&((_dvobj)->iface_state))
+#define DEV_ADHOC_NUM(_dvobj)		MSTATE_ADHOC_NUM(&((_dvobj)->iface_state))
+#define DEV_ADHOC_LD_NUM(_dvobj)	MSTATE_ADHOC_LD_NUM(&((_dvobj)->iface_state))
+#define DEV_MESH_NUM(_dvobj)		MSTATE_MESH_NUM(&((_dvobj)->iface_state))
+#define DEV_MESH_LD_NUM(_dvobj)		MSTATE_MESH_LD_NUM(&((_dvobj)->iface_state))
+#define DEV_P2P_DV_NUM(_dvobj)		MSTATE_P2P_DV_NUM(&((_dvobj)->iface_state))
+#define DEV_P2P_GC_NUM(_dvobj)		MSTATE_P2P_GC_NUM(&((_dvobj)->iface_state))
+#define DEV_P2P_GO_NUM(_dvobj)		MSTATE_P2P_GO_NUM(&((_dvobj)->iface_state))
+#define DEV_SCAN_NUM(_dvobj)		MSTATE_SCAN_NUM(&((_dvobj)->iface_state))
+#define DEV_WPS_NUM(_dvobj)			MSTATE_WPS_NUM(&((_dvobj)->iface_state))
+#define DEV_ROCH_NUM(_dvobj)		MSTATE_ROCH_NUM(&((_dvobj)->iface_state))
+#define DEV_MGMT_TX_NUM(_dvobj)		MSTATE_MGMT_TX_NUM(&((_dvobj)->iface_state))
+#define DEV_U_CH(_dvobj)			MSTATE_U_CH(&((_dvobj)->iface_state))
+#define DEV_U_BW(_dvobj)			MSTATE_U_BW(&((_dvobj)->iface_state))
+#define DEV_U_OFFSET(_dvobj)		MSTATE_U_OFFSET(&((_dvobj)->iface_state))
+
+#define dvobj_to_pwrctl(dvobj) (&(dvobj->pwrctl_priv))
+#define pwrctl_to_dvobj(pwrctl) container_of(pwrctl, struct dvobj_priv, pwrctl_priv)
+#define dvobj_to_macidctl(dvobj) (&(dvobj->macid_ctl))
+#define dvobj_to_sec_camctl(dvobj) (&(dvobj->cam_ctl))
+#define dvobj_to_regsty(dvobj) (&(dvobj->padapters[IFACE_ID0]->registrypriv))
+#if defined(CONFIG_IOCTL_CFG80211) && defined(RTW_SINGLE_WIPHY)
+#define dvobj_to_wiphy(dvobj) ((dvobj)->wiphy)
+#endif
+#define dvobj_to_rfctl(dvobj) (&(dvobj->rf_ctl))
+#define rfctl_to_dvobj(rfctl) container_of((rfctl), struct dvobj_priv, rf_ctl)
+
+static inline void dev_set_surprise_removed(struct dvobj_priv *dvobj)
+{
+	ATOMIC_SET(&dvobj->bSurpriseRemoved, _TRUE);
+}
+static inline void dev_clr_surprise_removed(struct dvobj_priv *dvobj)
+{
+	ATOMIC_SET(&dvobj->bSurpriseRemoved, _FALSE);
+}
+static inline void dev_set_drv_stopped(struct dvobj_priv *dvobj)
+{
+	ATOMIC_SET(&dvobj->bDriverStopped, _TRUE);
+}
+static inline void dev_clr_drv_stopped(struct dvobj_priv *dvobj)
+{
+	ATOMIC_SET(&dvobj->bDriverStopped, _FALSE);
+}
+#define dev_is_surprise_removed(dvobj)	(ATOMIC_READ(&dvobj->bSurpriseRemoved) == _TRUE)
+#define dev_is_drv_stopped(dvobj)		(ATOMIC_READ(&dvobj->bDriverStopped) == _TRUE)
+
+#ifdef PLATFORM_LINUX
+static inline struct device *dvobj_to_dev(struct dvobj_priv *dvobj)
+{
+	/* todo: get interface type from dvobj and the return the dev accordingly */
+#ifdef RTW_DVOBJ_CHIP_HW_TYPE
+#endif
+
+#ifdef CONFIG_USB_HCI
+	return &dvobj->pusbintf->dev;
+#endif
+#ifdef CONFIG_SDIO_HCI
+	return &dvobj->intf_data.func->dev;
+#endif
+#ifdef CONFIG_GSPI_HCI
+	return &dvobj->intf_data.func->dev;
+#endif
+#ifdef CONFIG_PCI_HCI
+	return &dvobj->ppcidev->dev;
+#endif
+}
+#endif
+
+_adapter *dvobj_get_port0_adapter(struct dvobj_priv *dvobj);
+_adapter *dvobj_get_unregisterd_adapter(struct dvobj_priv *dvobj);
+_adapter *dvobj_get_adapter_by_addr(struct dvobj_priv *dvobj, u8 *addr);
+#define dvobj_get_primary_adapter(dvobj)	((dvobj)->padapters[IFACE_ID0])
+
+enum _hw_port {
+	HW_PORT0,
+	HW_PORT1,
+	HW_PORT2,
+	HW_PORT3,
+	HW_PORT4,
+	MAX_HW_PORT,
+};
+
+#ifdef CONFIG_CLIENT_PORT_CFG
+enum _client_port {
+	CLT_PORT0 = HW_PORT1,
+	CLT_PORT1 = HW_PORT2,
+	CLT_PORT2 = HW_PORT3,
+	CLT_PORT3 = HW_PORT4,
+	CLT_PORT_INVALID = HW_PORT0,
+};
+
+#define MAX_CLIENT_PORT_NUM	4
+#define get_clt_port(adapter) (adapter->client_port)
+#endif
+
+enum _ADAPTER_TYPE {
+	PRIMARY_ADAPTER,
+	VIRTUAL_ADAPTER,
+	MAX_ADAPTER = 0xFF,
+};
+
+typedef enum _DRIVER_STATE {
+	DRIVER_NORMAL = 0,
+	DRIVER_DISAPPEAR = 1,
+	DRIVER_REPLACE_DONGLE = 2,
+} DRIVER_STATE;
+
+#ifdef CONFIG_RTW_NAPI
+enum _NAPI_STATE {
+	NAPI_DISABLE = 0,
+	NAPI_ENABLE = 1,
+};
+#endif
+
+#ifdef CONFIG_INTEL_PROXIM
+struct proxim {
+	bool proxim_support;
+	bool proxim_on;
+
+	void *proximity_priv;
+	int (*proxim_rx)(_adapter *padapter,
+			 union recv_frame *precv_frame);
+	u8(*proxim_get_var)(_adapter *padapter, u8 type);
+};
+#endif /* CONFIG_INTEL_PROXIM */
+
+#ifdef CONFIG_MAC_LOOPBACK_DRIVER
+typedef struct loopbackdata {
+	_sema	sema;
+	_thread_hdl_ lbkthread;
+	u8 bstop;
+	u32 cnt;
+	u16 size;
+	u16 txsize;
+	u8 txbuf[0x8000];
+	u16 rxsize;
+	u8 rxbuf[0x8000];
+	u8 msg[100];
+
+} LOOPBACKDATA, *PLOOPBACKDATA;
+#endif
+
+#define ADAPTER_TX_BW_2G(adapter) BW_MODE_2G((adapter)->driver_tx_bw_mode)
+#define ADAPTER_TX_BW_5G(adapter) BW_MODE_5G((adapter)->driver_tx_bw_mode)
+
+struct _ADAPTER {
+	int	DriverState;/* for disable driver using module, use dongle to replace module. */
+	int	pid[3];/* process id from UI, 0:wps, 1:hostapd, 2:dhcpcd */
+	int	bDongle;/* build-in module or external dongle */
+
+	#if defined(CONFIG_AP_MODE) && defined(CONFIG_SUPPORT_MULTI_BCN)
+	_list	list;
+	u8 vap_id;
+	#endif
+	struct dvobj_priv *dvobj;
+	struct	mlme_priv mlmepriv;
+	struct	mlme_ext_priv mlmeextpriv;
+	struct	cmd_priv	cmdpriv;
+	struct	evt_priv	evtpriv;
+
+#ifdef CONFIG_RTW_80211K
+	struct	rm_priv		rmpriv;
+#endif
+	/* struct	io_queue	*pio_queue; */
+	struct	io_priv	iopriv;
+	struct	xmit_priv	xmitpriv;
+	struct	recv_priv	recvpriv;
+	struct	sta_priv	stapriv;
+	struct	security_priv	securitypriv;
+	_lock   security_key_mutex; /* add for CONFIG_IEEE80211W, none 11w also can use */
+	struct	registry_priv	registrypriv;
+
+#ifdef CONFIG_RTW_NAPI
+	struct	napi_struct napi;
+	u8	napi_state;
+#endif
+
+#ifdef CONFIG_MP_INCLUDED
+	struct	mp_priv	mppriv;
+#endif
+
+#ifdef CONFIG_AP_MODE
+	struct	hostapd_priv	*phostapdpriv;
+#endif
+
+#ifdef CONFIG_IOCTL_CFG80211
+#ifdef CONFIG_P2P
+	struct cfg80211_wifidirect_info	cfg80211_wdinfo;
+#endif /* CONFIG_P2P */
+#endif /* CONFIG_IOCTL_CFG80211 */
+	u32	setband;
+	ATOMIC_T bandskip;
+
+#ifdef CONFIG_P2P
+	struct wifidirect_info	wdinfo;
+#endif /* CONFIG_P2P */
+
+#ifdef CONFIG_TDLS
+	struct tdls_info	tdlsinfo;
+#endif /* CONFIG_TDLS */
+
+#ifdef CONFIG_WAPI_SUPPORT
+	u8	WapiSupport;
+	RT_WAPI_T	wapiInfo;
+#endif
+
+#ifdef CONFIG_RTW_REPEATER_SON
+	u8	rtw_rson_scanstage;
+#endif
+
+#ifdef CONFIG_WFD
+	struct wifi_display_info wfd_info;
+#endif /* CONFIG_WFD */
+
+#ifdef CONFIG_BT_COEXIST_SOCKET_TRX
+	struct bt_coex_info coex_info;
+#endif /* CONFIG_BT_COEXIST_SOCKET_TRX */
+
+	ERROR_CODE		LastError; /* <20130613, Kordan> Only the functions associated with MP records the error code by now. */
+
+	PVOID			HalData;
+	u32 hal_data_sz;
+	struct hal_ops	hal_func;
+
+	u32	IsrContent;
+	u32	ImrContent;
+
+	u8	EepromAddressSize;
+	u8	bDriverIsGoingToUnload;
+	u8	init_adpt_in_progress;
+	u8	bHaltInProgress;
+#ifdef CONFIG_GPIO_API
+	u8	pre_gpio_pin;
+	struct gpio_int_priv {
+		u8 interrupt_mode;
+		u8 interrupt_enable_mask;
+		void (*callback[8])(u8 level);
+	} gpiointpriv;
+#endif
+	_thread_hdl_ cmdThread;
+#ifdef CONFIG_EVENT_THREAD_MODE
+	_thread_hdl_ evtThread;
+#endif
+#ifdef CONFIG_XMIT_THREAD_MODE
+	_thread_hdl_ xmitThread;
+#endif
+#ifdef CONFIG_RECV_THREAD_MODE
+	_thread_hdl_ recvThread;
+#endif
+	u8 registered;
+#ifndef PLATFORM_LINUX
+	NDIS_STATUS(*dvobj_init)(struct dvobj_priv *dvobj);
+	void (*dvobj_deinit)(struct dvobj_priv *dvobj);
+#endif
+
+	void (*intf_start)(_adapter *adapter);
+	void (*intf_stop)(_adapter *adapter);
+
+#ifdef PLATFORM_WINDOWS
+	_nic_hdl		hndis_adapter;/* hNdisAdapter(NDISMiniportAdapterHandle); */
+	_nic_hdl		hndis_config;/* hNdisConfiguration; */
+	NDIS_STRING fw_img;
+
+	u32	NdisPacketFilter;
+	u8	MCList[MAX_MCAST_LIST_NUM][6];
+	u32	MCAddrCount;
+#endif /* end of PLATFORM_WINDOWS */
+
+
+#ifdef PLATFORM_LINUX
+	_nic_hdl pnetdev;
+	char old_ifname[IFNAMSIZ];
+
+	/* used by rtw_rereg_nd_name related function */
+	struct rereg_nd_name_data {
+		_nic_hdl old_pnetdev;
+		char old_ifname[IFNAMSIZ];
+		u8 old_ips_mode;
+		u8 old_bRegUseLed;
+	} rereg_nd_name_priv;
+
+	u8 ndev_unregistering;
+	int bup;
+	struct net_device_stats stats;
+	struct iw_statistics iwstats;
+	struct proc_dir_entry *dir_dev;/* for proc directory */
+	struct proc_dir_entry *dir_odm;
+
+#ifdef CONFIG_MCC_MODE
+	struct proc_dir_entry *dir_mcc;
+#endif /* CONFIG_MCC_MODE */
+
+#ifdef CONFIG_IOCTL_CFG80211
+	struct wireless_dev *rtw_wdev;
+	struct rtw_wdev_priv wdev_data;
+
+#if !defined(RTW_SINGLE_WIPHY)
+	struct wiphy *wiphy;
+#endif
+
+#endif /* CONFIG_IOCTL_CFG80211 */
+
+#endif /* PLATFORM_LINUX */
+
+#ifdef PLATFORM_FREEBSD
+	_nic_hdl pifp;
+	int bup;
+	_lock glock;
+#endif /* PLATFORM_FREEBSD */
+	u8 mac_addr[ETH_ALEN];
+	int net_closed;
+
+	u8 netif_up;
+
+	u8 bLinkInfoDump;
+	/*	Added by Albert 2012/10/26 */
+	/*	The driver will show up the desired channel number when this flag is 1. */
+	u8 bNotifyChannelChange;
+	u8 bsta_tp_dump;
+#ifdef CONFIG_P2P
+	/*	Added by Albert 2012/12/06 */
+	/*	The driver will show the current P2P status when the upper application reads it. */
+	u8 bShowGetP2PState;
+#endif
+#ifdef CONFIG_AUTOSUSPEND
+	u8	bDisableAutosuspend;
+#endif
+
+	u8 isprimary; /* is primary adapter or not */
+	/* notes:
+	**	if isprimary is true, the adapter_type value is 0, iface_id is IFACE_ID0 for PRIMARY_ADAPTER
+	**	if isprimary is false, the adapter_type value is 1, iface_id is IFACE_ID1 for VIRTUAL_ADAPTER
+	**	refer to iface_id if iface_nums>2 and isprimary is false and the adapter_type value is 0xff.*/
+	u8 adapter_type;/*be used in  Multi-interface to recognize whether is PRIMARY_ADAPTER  or not(PRIMARY_ADAPTER/VIRTUAL_ADAPTER) .*/
+	u8 hw_port; /*interface port type, it depends on HW port */
+
+	#ifdef CONFIG_CLIENT_PORT_CFG
+	u8 client_id;
+	u8 client_port;
+	#endif
+	/*struct tsf_info tsf;*//*reserve define for 8814B*/
+
+	/*extend to support multi interface*/
+	u8 iface_id;
+
+#ifdef CONFIG_BR_EXT
+	_lock					br_ext_lock;
+	/* unsigned int			macclone_completed; */
+	struct nat25_network_db_entry	*nethash[NAT25_HASH_SIZE];
+	int				pppoe_connection_in_progress;
+	unsigned char			pppoe_addr[MACADDRLEN];
+	unsigned char			scdb_mac[MACADDRLEN];
+	unsigned char			scdb_ip[4];
+	struct nat25_network_db_entry	*scdb_entry;
+	unsigned char			br_mac[MACADDRLEN];
+	unsigned char			br_ip[4];
+
+	struct br_ext_info		ethBrExtInfo;
+#endif /* CONFIG_BR_EXT */
+
+#ifdef CONFIG_INTEL_PROXIM
+	/* intel Proximity, should be alloc mem
+	 * in intel Proximity module and can only
+	 * be used in intel Proximity mode */
+	struct proxim proximity;
+#endif /* CONFIG_INTEL_PROXIM */
+
+#ifdef CONFIG_MAC_LOOPBACK_DRIVER
+	PLOOPBACKDATA ploopback;
+#endif
+#ifdef CONFIG_AP_MODE
+	u8 bmc_tx_rate;
+#endif
+
+	/* for debug purpose */
+	u8 fix_rate;
+	u8 fix_bw;
+	u8 data_fb; /* data rate fallback, valid only when fix_rate is not 0xff */
+	u8 power_offset;
+	u8 driver_tx_bw_mode;
+	u8 rsvd_page_offset;
+	u8 rsvd_page_num;
+#ifdef CONFIG_SUPPORT_FIFO_DUMP
+	u8 fifo_sel;
+	u32 fifo_addr;
+	u32 fifo_size;
+#endif
+
+	u8 driver_vcs_en; /* Enable=1, Disable=0 driver control vrtl_carrier_sense for tx */
+	u8 driver_vcs_type;/* force 0:disable VCS, 1:RTS-CTS, 2:CTS-to-self when vcs_en=1. */
+	u8 driver_ampdu_spacing;/* driver control AMPDU Density for peer sta's rx */
+	u8 driver_rx_ampdu_factor;/* 0xff: disable drv ctrl, 0:8k, 1:16k, 2:32k, 3:64k; */
+	u8 driver_rx_ampdu_spacing;  /* driver control Rx AMPDU Density */
+	u8 fix_rx_ampdu_accept;
+	u8 fix_rx_ampdu_size; /* 0~127, TODO:consider each sta and each TID */
+#ifdef CONFIG_TX_AMSDU
+	u8 tx_amsdu;
+	u16 tx_amsdu_rate;
+#endif
+	u8 driver_tx_max_agg_num; /*fix tx desc max agg num , 0xff: disable drv ctrl*/
+#ifdef DBG_RX_COUNTER_DUMP
+	u8 dump_rx_cnt_mode;/*BIT0:drv,BIT1:mac,BIT2:phy*/
+	u32 drv_rx_cnt_ok;
+	u32 drv_rx_cnt_crcerror;
+	u32 drv_rx_cnt_drop;
+#endif
+
+#ifdef CONFIG_DBG_COUNTER
+	struct rx_logs rx_logs;
+	struct tx_logs tx_logs;
+	struct int_logs int_logs;
+#endif
+
+#ifdef CONFIG_MCC_MODE
+	struct mcc_adapter_priv mcc_adapterpriv;
+#endif /* CONFIG_MCC_MODE */
+
+#ifdef CONFIG_RTW_MESH
+	struct rtw_mesh_cfg mesh_cfg;
+	struct rtw_mesh_info mesh_info;
+	_timer mesh_path_timer;
+	_timer mesh_path_root_timer;
+	_timer mesh_atlm_param_req_timer; /* airtime link metrics param request timer */
+	_workitem mesh_work;
+	unsigned long wrkq_flags;
+#endif /* CONFIG_RTW_MESH */
+};
+
+#define adapter_to_dvobj(adapter) ((adapter)->dvobj)
+#define adapter_to_regsty(adapter) dvobj_to_regsty(adapter_to_dvobj((adapter)))
+#define adapter_to_pwrctl(adapter) dvobj_to_pwrctl(adapter_to_dvobj((adapter)))
+#define adapter_wdev_data(adapter) (&((adapter)->wdev_data))
+#if defined(RTW_SINGLE_WIPHY)
+#define adapter_to_wiphy(adapter) dvobj_to_wiphy(adapter_to_dvobj(adapter))
+#else
+#define adapter_to_wiphy(adapter) ((adapter)->wiphy)
+#endif
+
+#define adapter_to_rfctl(adapter) dvobj_to_rfctl(adapter_to_dvobj((adapter)))
+#define adapter_to_macidctl(adapter) dvobj_to_macidctl(adapter_to_dvobj((adapter)))
+
+#define adapter_mac_addr(adapter) (adapter->mac_addr)
+#ifdef CONFIG_RTW_CFGVENDOR_RANDOM_MAC_OUI
+#define adapter_pno_mac_addr(adapter) \
+	((adapter_wdev_data(adapter))->pno_mac_addr)
+#endif
+
+#define adapter_to_chset(adapter) (adapter_to_rfctl((adapter))->channel_set)
+
+#define mlme_to_adapter(mlme) container_of((mlme), struct _ADAPTER, mlmepriv)
+#define tdls_info_to_adapter(tdls) container_of((tdls), struct _ADAPTER, tdlsinfo)
+
+#define rtw_get_chip_type(adapter) (((PADAPTER)adapter)->dvobj->chip_type)
+#define rtw_get_hw_type(adapter) (((PADAPTER)adapter)->dvobj->HardwareType)
+#define rtw_get_intf_type(adapter) (((PADAPTER)adapter)->dvobj->interface_type)
+
+#define rtw_get_mi_nums(adapter) (((PADAPTER)adapter)->dvobj->iface_nums)
+
+static inline void rtw_set_surprise_removed(_adapter *padapter)
+{
+	dev_set_surprise_removed(adapter_to_dvobj(padapter));
+}
+static inline void rtw_clr_surprise_removed(_adapter *padapter)
+{
+	dev_clr_surprise_removed(adapter_to_dvobj(padapter));
+}
+static inline void rtw_set_drv_stopped(_adapter *padapter)
+{
+	dev_set_drv_stopped(adapter_to_dvobj(padapter));
+}
+static inline void rtw_clr_drv_stopped(_adapter *padapter)
+{
+	dev_clr_drv_stopped(adapter_to_dvobj(padapter));
+}
+#define rtw_is_surprise_removed(padapter)	(dev_is_surprise_removed(adapter_to_dvobj(padapter)))
+#define rtw_is_drv_stopped(padapter)		(dev_is_drv_stopped(adapter_to_dvobj(padapter)))
+
+/*
+ * Function disabled.
+ *   */
+#define DF_TX_BIT		BIT0			/*write_port_cancel*/
+#define DF_RX_BIT		BIT1			/*read_port_cancel*/
+#define DF_IO_BIT		BIT2
+
+/* #define RTW_DISABLE_FUNC(padapter, func) (ATOMIC_ADD(&adapter_to_dvobj(padapter)->disable_func, (func))) */
+/* #define RTW_ENABLE_FUNC(padapter, func) (ATOMIC_SUB(&adapter_to_dvobj(padapter)->disable_func, (func))) */
+__inline static void RTW_DISABLE_FUNC(_adapter *padapter, int func_bit)
+{
+	int	df = ATOMIC_READ(&adapter_to_dvobj(padapter)->disable_func);
+	df |= func_bit;
+	ATOMIC_SET(&adapter_to_dvobj(padapter)->disable_func, df);
+}
+
+__inline static void RTW_ENABLE_FUNC(_adapter *padapter, int func_bit)
+{
+	int	df = ATOMIC_READ(&adapter_to_dvobj(padapter)->disable_func);
+	df &= ~(func_bit);
+	ATOMIC_SET(&adapter_to_dvobj(padapter)->disable_func, df);
+}
+
+#define RTW_CANNOT_RUN(padapter) \
+	(rtw_is_surprise_removed(padapter) || \
+	 rtw_is_drv_stopped(padapter))
+
+#define RTW_IS_FUNC_DISABLED(padapter, func_bit) (ATOMIC_READ(&adapter_to_dvobj(padapter)->disable_func) & (func_bit))
+
+#define RTW_CANNOT_IO(padapter) \
+	(rtw_is_surprise_removed(padapter) || \
+	 RTW_IS_FUNC_DISABLED((padapter), DF_IO_BIT))
+
+#define RTW_CANNOT_RX(padapter) \
+	(RTW_CANNOT_RUN(padapter) || \
+	 RTW_IS_FUNC_DISABLED((padapter), DF_RX_BIT))
+
+#define RTW_CANNOT_TX(padapter) \
+	(RTW_CANNOT_RUN(padapter) || \
+	 RTW_IS_FUNC_DISABLED((padapter), DF_TX_BIT))
+
+#ifdef CONFIG_PNO_SUPPORT
+int rtw_parse_ssid_list_tlv(char **list_str, pno_ssid_t *ssid, int max, int *bytes_left);
+int rtw_dev_pno_set(struct net_device *net, pno_ssid_t *ssid, int num,
+		    int pno_time, int pno_repeat, int pno_freq_expo_max);
+#ifdef CONFIG_PNO_SET_DEBUG
+	void rtw_dev_pno_debug(struct net_device *net);
+#endif /* CONFIG_PNO_SET_DEBUG */
+#endif /* CONFIG_PNO_SUPPORT */
+
+int rtw_suspend_free_assoc_resource(_adapter *padapter);
+#ifdef CONFIG_WOWLAN
+	int rtw_suspend_wow(_adapter *padapter);
+	int rtw_resume_process_wow(_adapter *padapter);
+#endif
+
+/* HCI Related header file */
+#ifdef CONFIG_USB_HCI
+	#include <usb_osintf.h>
+	#include <usb_ops.h>
+	#include <usb_hal.h>
+#endif
+
+#ifdef CONFIG_SDIO_HCI
+	#include <sdio_osintf.h>
+	#include <sdio_ops.h>
+	#include <sdio_hal.h>
+#endif
+
+#ifdef CONFIG_GSPI_HCI
+	#include <gspi_osintf.h>
+	#include <gspi_ops.h>
+	#include <gspi_hal.h>
+#endif
+
+#ifdef CONFIG_PCI_HCI
+	#include <pci_osintf.h>
+	#include <pci_ops.h>
+	#include <pci_hal.h>
+#endif
+
+#endif /* __DRV_TYPES_H__ */
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/include/drv_types_linux.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/drv_types_linux.h
--- linux-5.6.3/3rdparty/rtl8821ce/include/drv_types_linux.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/drv_types_linux.h	2020-04-10 16:35:06.846661469 +0300
@@ -0,0 +1,19 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#ifndef __DRV_TYPES_LINUX_H__
+#define __DRV_TYPES_LINUX_H__
+
+
+#endif
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/include/drv_types_pci.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/drv_types_pci.h
--- linux-5.6.3/3rdparty/rtl8821ce/include/drv_types_pci.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/drv_types_pci.h	2020-04-10 16:35:06.846661469 +0300
@@ -0,0 +1,266 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#ifndef __DRV_TYPES_PCI_H__
+#define __DRV_TYPES_PCI_H__
+
+
+#ifdef PLATFORM_LINUX
+	#include <linux/pci.h>
+#endif
+
+
+#define	INTEL_VENDOR_ID				0x8086
+#define	SIS_VENDOR_ID					0x1039
+#define	ATI_VENDOR_ID					0x1002
+#define	ATI_DEVICE_ID					0x7914
+#define	AMD_VENDOR_ID					0x1022
+
+#define	PCI_MAX_BRIDGE_NUMBER			255
+#define	PCI_MAX_DEVICES				32
+#define	PCI_MAX_FUNCTION				8
+
+#define	PCI_CONF_ADDRESS   				0x0CF8   /* PCI Configuration Space Address */
+#define	PCI_CONF_DATA					0x0CFC   /* PCI Configuration Space Data */
+
+#define	PCI_CLASS_BRIDGE_DEV			0x06
+#define	PCI_SUBCLASS_BR_PCI_TO_PCI	0x04
+
+#define	PCI_CAPABILITY_ID_PCI_EXPRESS	0x10
+
+#define	U1DONTCARE					0xFF
+#define	U2DONTCARE					0xFFFF
+#define	U4DONTCARE					0xFFFFFFFF
+
+#define PCI_VENDER_ID_REALTEK		0x10ec
+
+#define HAL_HW_PCI_8180_DEVICE_ID	0x8180
+#define HAL_HW_PCI_8185_DEVICE_ID           	0x8185	/* 8185 or 8185b */
+#define HAL_HW_PCI_8188_DEVICE_ID           	0x8188	/* 8185b		 */
+#define HAL_HW_PCI_8198_DEVICE_ID           	0x8198	/* 8185b		 */
+#define HAL_HW_PCI_8190_DEVICE_ID           	0x8190	/* 8190 */
+#define HAL_HW_PCI_8723E_DEVICE_ID		0x8723	/* 8723E */
+#define HAL_HW_PCI_8192_DEVICE_ID           	0x8192	/* 8192 PCI-E */
+#define HAL_HW_PCI_8192SE_DEVICE_ID		0x8192	/* 8192 SE */
+#define HAL_HW_PCI_8174_DEVICE_ID           	0x8174	/* 8192 SE */
+#define HAL_HW_PCI_8173_DEVICE_ID           	0x8173	/* 8191 SE Crab */
+#define HAL_HW_PCI_8172_DEVICE_ID           	0x8172	/* 8191 SE RE */
+#define HAL_HW_PCI_8171_DEVICE_ID           	0x8171	/* 8191 SE Unicron */
+#define HAL_HW_PCI_0045_DEVICE_ID			0x0045	/* 8190 PCI for Ceraga */
+#define HAL_HW_PCI_0046_DEVICE_ID			0x0046	/* 8190 Cardbus for Ceraga */
+#define HAL_HW_PCI_0044_DEVICE_ID			0x0044	/* 8192e PCIE for Ceraga */
+#define HAL_HW_PCI_0047_DEVICE_ID			0x0047	/* 8192e Express Card for Ceraga */
+#define HAL_HW_PCI_700F_DEVICE_ID			0x700F
+#define HAL_HW_PCI_701F_DEVICE_ID			0x701F
+#define HAL_HW_PCI_DLINK_DEVICE_ID		0x3304
+#define HAL_HW_PCI_8188EE_DEVICE_ID		0x8179
+
+#define HAL_MEMORY_MAPPED_IO_RANGE_8190PCI 		0x1000     /* 8190 support 16 pages of IO registers */
+#define HAL_HW_PCI_REVISION_ID_8190PCI			0x00
+#define HAL_MEMORY_MAPPED_IO_RANGE_8192PCIE	0x4000	/* 8192 support 16 pages of IO registers */
+#define HAL_HW_PCI_REVISION_ID_8192PCIE			0x01
+#define HAL_MEMORY_MAPPED_IO_RANGE_8192SE		0x4000	/* 8192 support 16 pages of IO registers */
+#define HAL_HW_PCI_REVISION_ID_8192SE			0x10
+#define HAL_HW_PCI_REVISION_ID_8192CE			0x1
+#define HAL_MEMORY_MAPPED_IO_RANGE_8192CE		0x4000	/* 8192 support 16 pages of IO registers */
+#define HAL_HW_PCI_REVISION_ID_8192DE			0x0
+#define HAL_MEMORY_MAPPED_IO_RANGE_8192DE		0x4000	/* 8192 support 16 pages of IO registers */
+
+enum pci_bridge_vendor {
+	PCI_BRIDGE_VENDOR_INTEL = 0x0,/* 0b'0000,0001 */
+	PCI_BRIDGE_VENDOR_ATI, /* = 0x02, */ /* 0b'0000,0010 */
+	PCI_BRIDGE_VENDOR_AMD, /* = 0x04, */ /* 0b'0000,0100 */
+	PCI_BRIDGE_VENDOR_SIS ,/* = 0x08, */ /* 0b'0000,1000 */
+	PCI_BRIDGE_VENDOR_UNKNOWN, /* = 0x40, */ /* 0b'0100,0000 */
+	PCI_BRIDGE_VENDOR_MAX ,/* = 0x80 */
+} ;
+
+/* copy this data structor defination from MSDN SDK */
+typedef struct _PCI_COMMON_CONFIG {
+	u16	VendorID;
+	u16	DeviceID;
+	u16	Command;
+	u16	Status;
+	u8	RevisionID;
+	u8	ProgIf;
+	u8	SubClass;
+	u8	BaseClass;
+	u8	CacheLineSize;
+	u8	LatencyTimer;
+	u8	HeaderType;
+	u8	BIST;
+
+	union {
+		struct _PCI_HEADER_TYPE_0 {
+			u32	BaseAddresses[6];
+			u32	CIS;
+			u16	SubVendorID;
+			u16	SubSystemID;
+			u32	ROMBaseAddress;
+			u8	CapabilitiesPtr;
+			u8	Reserved1[3];
+			u32	Reserved2;
+
+			u8	InterruptLine;
+			u8	InterruptPin;
+			u8	MinimumGrant;
+			u8	MaximumLatency;
+		} type0;
+#if 0
+		struct _PCI_HEADER_TYPE_1 {
+			ULONG BaseAddresses[PCI_TYPE1_ADDRESSES];
+			UCHAR PrimaryBusNumber;
+			UCHAR SecondaryBusNumber;
+			UCHAR SubordinateBusNumber;
+			UCHAR SecondaryLatencyTimer;
+			UCHAR IOBase;
+			UCHAR IOLimit;
+			USHORT SecondaryStatus;
+			USHORT MemoryBase;
+			USHORT MemoryLimit;
+			USHORT PrefetchableMemoryBase;
+			USHORT PrefetchableMemoryLimit;
+			ULONG PrefetchableMemoryBaseUpper32;
+			ULONG PrefetchableMemoryLimitUpper32;
+			USHORT IOBaseUpper;
+			USHORT IOLimitUpper;
+			ULONG Reserved2;
+			ULONG ExpansionROMBase;
+			UCHAR InterruptLine;
+			UCHAR InterruptPin;
+			USHORT BridgeControl;
+		} type1;
+
+		struct _PCI_HEADER_TYPE_2 {
+			ULONG BaseAddress;
+			UCHAR CapabilitiesPtr;
+			UCHAR Reserved2;
+			USHORT SecondaryStatus;
+			UCHAR PrimaryBusNumber;
+			UCHAR CardbusBusNumber;
+			UCHAR SubordinateBusNumber;
+			UCHAR CardbusLatencyTimer;
+			ULONG MemoryBase0;
+			ULONG MemoryLimit0;
+			ULONG MemoryBase1;
+			ULONG MemoryLimit1;
+			USHORT IOBase0_LO;
+			USHORT IOBase0_HI;
+			USHORT IOLimit0_LO;
+			USHORT IOLimit0_HI;
+			USHORT IOBase1_LO;
+			USHORT IOBase1_HI;
+			USHORT IOLimit1_LO;
+			USHORT IOLimit1_HI;
+			UCHAR InterruptLine;
+			UCHAR InterruptPin;
+			USHORT BridgeControl;
+			USHORT SubVendorID;
+			USHORT SubSystemID;
+			ULONG LegacyBaseAddress;
+			UCHAR Reserved3[56];
+			ULONG SystemControl;
+			UCHAR MultiMediaControl;
+			UCHAR GeneralStatus;
+			UCHAR Reserved4[2];
+			UCHAR GPIO0Control;
+			UCHAR GPIO1Control;
+			UCHAR GPIO2Control;
+			UCHAR GPIO3Control;
+			ULONG IRQMuxRouting;
+			UCHAR RetryStatus;
+			UCHAR CardControl;
+			UCHAR DeviceControl;
+			UCHAR Diagnostic;
+		} type2;
+#endif
+	} u;
+
+	u8	DeviceSpecific[108];
+} PCI_COMMON_CONFIG , *PPCI_COMMON_CONFIG;
+
+typedef struct _RT_PCI_CAPABILITIES_HEADER {
+	u8   CapabilityID;
+	u8   Next;
+} RT_PCI_CAPABILITIES_HEADER, *PRT_PCI_CAPABILITIES_HEADER;
+
+struct pci_priv {
+	BOOLEAN		pci_clk_req;
+
+	u8	pciehdr_offset;
+	/* PCIeCap is only differece between B-cut and C-cut. */
+	/* Configuration Space offset 72[7:4] */
+	/* 0: A/B cut */
+	/* 1: C cut and later. */
+	u8	pcie_cap;
+	u8	linkctrl_reg;
+
+	u8	busnumber;
+	u8	devnumber;
+	u8	funcnumber;
+
+	u8	pcibridge_busnum;
+	u8	pcibridge_devnum;
+	u8	pcibridge_funcnum;
+	u8	pcibridge_vendor;
+	u16	pcibridge_vendorid;
+	u16	pcibridge_deviceid;
+	u8	pcibridge_pciehdr_offset;
+	u8	pcibridge_linkctrlreg;
+
+	u8	amd_l1_patch;
+};
+
+typedef struct _RT_ISR_CONTENT {
+	union {
+		u32			IntArray[2];
+		u32			IntReg4Byte;
+		u16			IntReg2Byte;
+	};
+} RT_ISR_CONTENT, *PRT_ISR_CONTENT;
+
+/* #define RegAddr(addr)           (addr + 0xB2000000UL) */
+/* some platform macros will def here */
+static inline void NdisRawWritePortUlong(u32 port,  u32 val)
+{
+	outl(val, port);
+	/* writel(val, (u8 *)RegAddr(port));	 */
+}
+
+static inline void NdisRawWritePortUchar(u32 port,  u8 val)
+{
+	outb(val, port);
+	/* writeb(val, (u8 *)RegAddr(port)); */
+}
+
+static inline void NdisRawReadPortUchar(u32 port, u8 *pval)
+{
+	*pval = inb(port);
+	/* *pval = readb((u8 *)RegAddr(port)); */
+}
+
+static inline void NdisRawReadPortUshort(u32 port, u16 *pval)
+{
+	*pval = inw(port);
+	/* *pval = readw((u8 *)RegAddr(port)); */
+}
+
+static inline void NdisRawReadPortUlong(u32 port, u32 *pval)
+{
+	*pval = inl(port);
+	/* *pval = readl((u8 *)RegAddr(port)); */
+}
+
+
+#endif
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/include/drv_types_sdio.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/drv_types_sdio.h
--- linux-5.6.3/3rdparty/rtl8821ce/include/drv_types_sdio.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/drv_types_sdio.h	2020-04-10 16:35:06.846661469 +0300
@@ -0,0 +1,90 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#ifndef __DRV_TYPES_SDIO_H__
+#define __DRV_TYPES_SDIO_H__
+
+/* SDIO Header Files */
+#ifdef PLATFORM_LINUX
+	#include <linux/mmc/sdio_func.h>
+	#include <linux/mmc/sdio_ids.h>
+	#include <linux/mmc/host.h>
+	#include <linux/mmc/card.h>
+
+	#ifdef CONFIG_PLATFORM_SPRD
+		#include <linux/gpio.h>
+		#include <custom_gpio.h>
+	#endif /* CONFIG_PLATFORM_SPRD */
+#endif
+
+#ifdef PLATFORM_OS_XP
+	#include <wdm.h>
+	#include <ntddsd.h>
+#endif
+
+#ifdef PLATFORM_OS_CE
+	#include <sdcardddk.h>
+#endif
+
+#define RTW_SDIO_CLK_33M	33000000
+#define RTW_SDIO_CLK_40M	40000000
+#define RTW_SDIO_CLK_80M	80000000
+#define RTW_SDIO_CLK_160M	160000000
+
+typedef struct sdio_data {
+	u8  func_number;
+
+	u8  tx_block_mode;
+	u8  rx_block_mode;
+	u32 block_transfer_len;
+
+#ifdef PLATFORM_LINUX
+	struct sdio_func	*func;
+	_thread_hdl_ sys_sdio_irq_thd;
+	unsigned int clock;
+	unsigned int timing;
+	u8	sd3_bus_mode;
+#endif
+
+#ifdef PLATFORM_OS_XP
+	PDEVICE_OBJECT				pphysdevobj;
+	PDEVICE_OBJECT				pfuncdevobj;
+	PDEVICE_OBJECT				pnextdevobj;
+	SDBUS_INTERFACE_STANDARD	sdbusinft;
+	u8							nextdevstacksz;
+#endif
+
+#ifdef PLATFORM_OS_CE
+	SD_DEVICE_HANDLE			hDevice;
+	SD_CARD_RCA					sd_rca;
+	SD_CARD_INTERFACE			card_intf;
+	BOOLEAN						enableIsarWithStatus;
+	WCHAR						active_path[MAX_ACTIVE_REG_PATH];
+	SD_HOST_BLOCK_CAPABILITY	sd_host_blk_cap;
+#endif
+} SDIO_DATA, *PSDIO_DATA;
+
+#define dvobj_to_sdio_func(d)	((d)->intf_data.func)
+
+#define RTW_SDIO_ADDR_CMD52_BIT		(1<<17)
+#define RTW_SDIO_ADDR_CMD52_GEN(a)	(a | RTW_SDIO_ADDR_CMD52_BIT)
+#define RTW_SDIO_ADDR_CMD52_CLR(a)	(a&~RTW_SDIO_ADDR_CMD52_BIT)
+#define RTW_SDIO_ADDR_CMD52_CHK(a)	(a&RTW_SDIO_ADDR_CMD52_BIT ? 1 : 0)
+
+#define RTW_SDIO_ADDR_F0_BIT		(1<<18)
+#define RTW_SDIO_ADDR_F0_GEN(a)		(a | RTW_SDIO_ADDR_F0_BIT)
+#define RTW_SDIO_ADDR_F0_CLR(a)		(a&~RTW_SDIO_ADDR_F0_BIT)
+#define RTW_SDIO_ADDR_F0_CHK(a)		(a&RTW_SDIO_ADDR_F0_BIT ? 1 : 0)
+
+#endif
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/include/drv_types_xp.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/drv_types_xp.h
--- linux-5.6.3/3rdparty/rtl8821ce/include/drv_types_xp.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/drv_types_xp.h	2020-04-10 16:35:06.846661469 +0300
@@ -0,0 +1,88 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#ifndef __DRV_TYPES_XP_H__
+#define __DRV_TYPES_XP_H__
+
+#include <drv_conf.h>
+#include <osdep_service.h>
+
+
+
+#define MAX_MCAST_LIST_NUM					32
+
+
+
+/* for ioctl */
+#define MAKE_DRIVER_VERSION(_MainVer, _MinorVer)	((((u32)(_MainVer))<<16)+_MinorVer)
+
+#define NIC_HEADER_SIZE				14			/* !< can be moved to typedef.h */
+#define NIC_MAX_PACKET_SIZE			1514		/* !< can be moved to typedef.h */
+#define NIC_MAX_SEND_PACKETS			10		/* max number of send packets the MiniportSendPackets function can accept, can be moved to typedef.h */
+#define NIC_VENDOR_DRIVER_VERSION       MAKE_DRIVER_VERSION(0, 001)	/* !< can be moved to typedef.h */
+#define NIC_MAX_PACKET_SIZE			1514		/* !< can be moved to typedef.h */
+
+
+#undef ON_VISTA
+/* added by Jackson */
+#ifndef ON_VISTA
+	/*
+	* Bus driver versions
+	*   */
+
+	#define SDBUS_DRIVER_VERSION_1          0x100
+	#define SDBUS_DRIVER_VERSION_2          0x200
+
+	#define    SDP_FUNCTION_TYPE	4
+	#define    SDP_BUS_DRIVER_VERSION 5
+	#define    SDP_BUS_WIDTH 6
+	#define    SDP_BUS_CLOCK 7
+	#define    SDP_BUS_INTERFACE_CONTROL 8
+	#define    SDP_HOST_BLOCK_LENGTH 9
+	#define    SDP_FUNCTION_BLOCK_LENGTH 10
+	#define    SDP_FN0_BLOCK_LENGTH 11
+	#define    SDP_FUNCTION_INT_ENABLE 12
+#endif
+
+
+typedef struct _MP_REG_ENTRY {
+
+	NDIS_STRING		RegName;	/* variable name text */
+	BOOLEAN			bRequired;	/* 1->required, 0->optional */
+
+	u8			Type;		/* NdisParameterInteger/NdisParameterHexInteger/NdisParameterStringle/NdisParameterMultiString */
+	uint			FieldOffset;	/* offset to MP_ADAPTER field */
+	uint			FieldSize;	/* size (in bytes) of the field */
+
+#ifdef UNDER_AMD64
+	u64			Default;
+#else
+	u32			Default;		/* default value to use */
+#endif
+
+	u32			Min;			/* minimum value allowed */
+	u32			Max;		/* maximum value allowed */
+} MP_REG_ENTRY, *PMP_REG_ENTRY;
+
+
+typedef struct _OCTET_STRING {
+	u8      *Octet;
+	u16      Length;
+} OCTET_STRING, *POCTET_STRING;
+
+
+
+
+
+#endif
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/include/ethernet.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/ethernet.h
--- linux-5.6.3/3rdparty/rtl8821ce/include/ethernet.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/ethernet.h	2020-04-10 16:35:06.846661469 +0300
@@ -0,0 +1,36 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+/*! \file */
+#ifndef __INC_ETHERNET_H
+#define __INC_ETHERNET_H
+
+#define ETHERNET_ADDRESS_LENGTH				6		/* !< Ethernet Address Length */
+#define ETHERNET_HEADER_SIZE				14		/* !< Ethernet Header Length */
+#define LLC_HEADER_SIZE						6		/* !< LLC Header Length */
+#define TYPE_LENGTH_FIELD_SIZE				2		/* !< Type/Length Size */
+#define MINIMUM_ETHERNET_PACKET_SIZE		60		/* !< Minimum Ethernet Packet Size */
+#define MAXIMUM_ETHERNET_PACKET_SIZE		1514	/* !< Maximum Ethernet Packet Size */
+
+#define RT_ETH_IS_MULTICAST(_pAddr)	((((UCHAR *)(_pAddr))[0]&0x01) != 0)		/* !< Is Multicast Address? */
+#define RT_ETH_IS_BROADCAST(_pAddr)	(\
+		((UCHAR *)(_pAddr))[0] == 0xff	&&		\
+		((UCHAR *)(_pAddr))[1] == 0xff	&&		\
+		((UCHAR *)(_pAddr))[2] == 0xff	&&		\
+		((UCHAR *)(_pAddr))[3] == 0xff	&&		\
+		((UCHAR *)(_pAddr))[4] == 0xff	&&		\
+		((UCHAR *)(_pAddr))[5] == 0xff)	/* !< Is Broadcast Address? */
+
+
+#endif /*  #ifndef __INC_ETHERNET_H */
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/include/gspi_hal.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/gspi_hal.h
--- linux-5.6.3/3rdparty/rtl8821ce/include/gspi_hal.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/gspi_hal.h	2020-04-10 16:35:06.846661469 +0300
@@ -0,0 +1,30 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#ifndef __GSPI_HAL_H__
+#define __GSPI_HAL_H__
+
+
+void spi_int_dpc(PADAPTER padapter, u32 sdio_hisr);
+u8 rtw_set_hal_ops(_adapter *padapter);
+
+#ifdef CONFIG_RTL8188E
+	void rtl8188es_set_hal_ops(PADAPTER padapter);
+#endif
+
+#ifdef CONFIG_RTL8723B
+	void rtl8723bs_set_hal_ops(PADAPTER padapter);
+#endif
+
+#endif /* __GSPI_HAL_H__ */
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/include/gspi_ops.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/gspi_ops.h
--- linux-5.6.3/3rdparty/rtl8821ce/include/gspi_ops.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/gspi_ops.h	2020-04-10 16:35:06.846661469 +0300
@@ -0,0 +1,180 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#ifndef __GSPI_OPS_H__
+#define __GSPI_OPS_H__
+
+/* follwing defination is based on
+ * GSPI spec of RTL8723, we temp
+ * suppose that it will be the same
+ * for diff chips of GSPI, if not
+ * we should move it to HAL folder */
+#define SPI_LOCAL_DOMAIN				0x0
+#define WLAN_IOREG_DOMAIN			0x8
+#define FW_FIFO_DOMAIN				0x4
+#define TX_HIQ_DOMAIN					0xc
+#define TX_MIQ_DOMAIN					0xd
+#define TX_LOQ_DOMAIN					0xe
+#define RX_RXFIFO_DOMAIN				0x1f
+
+/* IO Bus domain address mapping */
+#define DEFUALT_OFFSET					0x0
+#define SPI_LOCAL_OFFSET				0x10250000
+#define WLAN_IOREG_OFFSET			0x10260000
+#define FW_FIFO_OFFSET				0x10270000
+#define TX_HIQ_OFFSET					0x10310000
+#define TX_MIQ_OFFSET					0x1032000
+#define TX_LOQ_OFFSET					0x10330000
+#define RX_RXOFF_OFFSET				0x10340000
+
+/* SPI Local registers */
+#define SPI_REG_TX_CTRL					0x0000 /* SPI Tx Control */
+#define SPI_REG_STATUS_RECOVERY		0x0004
+#define SPI_REG_INT_TIMEOUT			0x0006
+#define SPI_REG_HIMR					0x0014 /* SPI Host Interrupt Mask */
+#define SPI_REG_HISR					0x0018 /* SPI Host Interrupt Service Routine */
+#define SPI_REG_RX0_REQ_LEN			0x001C /* RXDMA Request Length */
+#define SPI_REG_FREE_TXPG				0x0020 /* Free Tx Buffer Page */
+#define SPI_REG_HCPWM1					0x0024 /* HCI Current Power Mode 1 */
+#define SPI_REG_HCPWM2					0x0026 /* HCI Current Power Mode 2 */
+#define SPI_REG_HTSFR_INFO				0x0030 /* HTSF Informaion */
+#define SPI_REG_HRPWM1					0x0080 /* HCI Request Power Mode 1 */
+#define SPI_REG_HRPWM2					0x0082 /* HCI Request Power Mode 2 */
+#define SPI_REG_HPS_CLKR				0x0084 /* HCI Power Save Clock */
+#define SPI_REG_HSUS_CTRL				0x0086 /* SPI HCI Suspend Control */
+#define SPI_REG_HIMR_ON				0x0090 /* SPI Host Extension Interrupt Mask Always */
+#define SPI_REG_HISR_ON				0x0091 /* SPI Host Extension Interrupt Status Always */
+#define SPI_REG_CFG						0x00F0 /* SPI Configuration Register */
+
+#define SPI_TX_CTRL				(SPI_REG_TX_CTRL | SPI_LOCAL_OFFSET)
+#define SPI_STATUS_RECOVERY			(SPI_REG_STATUS_RECOVERY | SPI_LOCAL_OFFSET)
+#define SPI_INT_TIMEOUT					(SPI_REG_INT_TIMEOUT | SPI_LOCAL_OFFSET)
+#define SPI_HIMR				(SPI_REG_HIMR | SPI_LOCAL_OFFSET)
+#define SPI_HISR				(SPI_REG_HISR | SPI_LOCAL_OFFSET)
+#define SPI_RX0_REQ_LEN_1_BYTE		(SPI_REG_RX0_REQ_LEN | SPI_LOCAL_OFFSET)
+#define SPI_FREE_TXPG			(SPI_REG_FREE_TXPG | SPI_LOCAL_OFFSET)
+
+#define	SPI_HIMR_DISABLED				0
+
+/* SPI HIMR MASK diff with SDIO */
+#define SPI_HISR_RX_REQUEST			BIT(0)
+#define SPI_HISR_AVAL					BIT(1)
+#define SPI_HISR_TXERR					BIT(2)
+#define SPI_HISR_RXERR					BIT(3)
+#define SPI_HISR_TXFOVW				BIT(4)
+#define SPI_HISR_RXFOVW				BIT(5)
+#define SPI_HISR_TXBCNOK				BIT(6)
+#define SPI_HISR_TXBCNERR				BIT(7)
+#define SPI_HISR_BCNERLY_INT			BIT(16)
+#define SPI_HISR_ATIMEND				BIT(17)
+#define SPI_HISR_ATIMEND_E				BIT(18)
+#define SPI_HISR_CTWEND				BIT(19)
+#define SPI_HISR_C2HCMD				BIT(20)
+#define SPI_HISR_CPWM1					BIT(21)
+#define SPI_HISR_CPWM2					BIT(22)
+#define SPI_HISR_HSISR_IND				BIT(23)
+#define SPI_HISR_GTINT3_IND				BIT(24)
+#define SPI_HISR_GTINT4_IND				BIT(25)
+#define SPI_HISR_PSTIMEOUT				BIT(26)
+#define SPI_HISR_OCPINT					BIT(27)
+#define SPI_HISR_TSF_BIT32_TOGGLE		BIT(29)
+
+#define MASK_SPI_HISR_CLEAR		(SPI_HISR_TXERR |\
+		SPI_HISR_RXERR |\
+		SPI_HISR_TXFOVW |\
+		SPI_HISR_RXFOVW |\
+		SPI_HISR_TXBCNOK |\
+		SPI_HISR_TXBCNERR |\
+		SPI_HISR_C2HCMD |\
+		SPI_HISR_CPWM1 |\
+		SPI_HISR_CPWM2 |\
+		SPI_HISR_HSISR_IND |\
+		SPI_HISR_GTINT3_IND |\
+		SPI_HISR_GTINT4_IND |\
+		SPI_HISR_PSTIMEOUT |\
+		SPI_HISR_OCPINT)
+
+#define REG_LEN_FORMAT(pcmd, x) 			SET_BITS_TO_LE_4BYTE(pcmd, 0, 8, x)/* (x<<(unsigned int)24) */
+#define REG_ADDR_FORMAT(pcmd, x) 			SET_BITS_TO_LE_4BYTE(pcmd, 8, 16, x)/* (x<<(unsigned int)16) */
+#define REG_DOMAIN_ID_FORMAT(pcmd, x) 		SET_BITS_TO_LE_4BYTE(pcmd, 24, 5, x)/* (x<<(unsigned int)0) */
+#define REG_FUN_FORMAT(pcmd, x) 			SET_BITS_TO_LE_4BYTE(pcmd, 29, 2, x)/* (x<<(unsigned int)5) */
+#define REG_RW_FORMAT(pcmd, x) 				SET_BITS_TO_LE_4BYTE(pcmd, 31, 1, x)/* (x<<(unsigned int)7) */
+
+#define FIFO_LEN_FORMAT(pcmd, x) 			SET_BITS_TO_LE_4BYTE(pcmd, 0, 16, x)/* (x<<(unsigned int)24)
+ * #define FIFO_ADDR_FORMAT(pcmd,x) 			SET_BITS_TO_LE_4BYTE(pcmd, 8, 16, x) */ /* (x<<(unsigned int)16) */
+#define FIFO_DOMAIN_ID_FORMAT(pcmd, x) 	SET_BITS_TO_LE_4BYTE(pcmd, 24, 5, x)/* (x<<(unsigned int)0) */
+#define FIFO_FUN_FORMAT(pcmd, x) 			SET_BITS_TO_LE_4BYTE(pcmd, 29, 2, x)/* (x<<(unsigned int)5) */
+#define FIFO_RW_FORMAT(pcmd, x) 			SET_BITS_TO_LE_4BYTE(pcmd, 31, 1, x)/* (x<<(unsigned int)7) */
+
+
+/* get status dword0 */
+#define GET_STATUS_PUB_PAGE_NUM(status)		LE_BITS_TO_4BYTE(status, 24, 8)
+#define GET_STATUS_HI_PAGE_NUM(status)		LE_BITS_TO_4BYTE(status, 18, 6)
+#define GET_STATUS_MID_PAGE_NUM(status)		LE_BITS_TO_4BYTE(status, 12, 6)
+#define GET_STATUS_LOW_PAGE_NUM(status)		LE_BITS_TO_4BYTE(status, 6, 6)
+#define GET_STATUS_HISR_HI6BIT(status)			LE_BITS_TO_4BYTE(status, 0, 6)
+
+/* get status dword1 */
+#define GET_STATUS_HISR_MID8BIT(status)		LE_BITS_TO_4BYTE(status + 4, 24, 8)
+#define GET_STATUS_HISR_LOW8BIT(status)		LE_BITS_TO_4BYTE(status + 4, 16, 8)
+#define GET_STATUS_ERROR(status)				LE_BITS_TO_4BYTE(status + 4, 17, 1)
+#define GET_STATUS_INT(status)				LE_BITS_TO_4BYTE(status + 4, 16, 1)
+#define GET_STATUS_RX_LENGTH(status)			LE_BITS_TO_4BYTE(status + 4, 0, 16)
+
+
+#define RXDESC_SIZE	24
+
+
+struct spi_more_data {
+	unsigned long more_data;
+	unsigned long len;
+};
+
+#ifdef CONFIG_RTL8188E
+	void rtl8188es_set_hal_ops(PADAPTER padapter);
+	#define set_hal_ops rtl8188es_set_hal_ops
+#endif
+extern void spi_set_chip_endian(PADAPTER padapter);
+extern unsigned int spi_write8_endian(ADAPTER *Adapter, unsigned int addr, unsigned int buf, u32 big);
+extern void spi_set_intf_ops(_adapter *padapter, struct _io_ops *pops);
+extern void spi_set_chip_endian(PADAPTER padapter);
+extern void InitInterrupt8723ASdio(PADAPTER padapter);
+extern void InitSysInterrupt8723ASdio(PADAPTER padapter);
+extern void EnableInterrupt8723ASdio(PADAPTER padapter);
+extern void DisableInterrupt8723ASdio(PADAPTER padapter);
+extern void spi_int_hdl(PADAPTER padapter);
+extern u8 HalQueryTxBufferStatus8723ASdio(PADAPTER padapter);
+#ifdef CONFIG_RTL8723B
+	extern void InitInterrupt8723BSdio(PADAPTER padapter);
+	extern void InitSysInterrupt8723BSdio(PADAPTER padapter);
+	extern void EnableInterrupt8723BSdio(PADAPTER padapter);
+	extern void DisableInterrupt8723BSdio(PADAPTER padapter);
+	extern u8 HalQueryTxBufferStatus8723BSdio(PADAPTER padapter);
+#endif
+
+#ifdef CONFIG_RTL8188E
+	extern void InitInterrupt8188EGspi(PADAPTER padapter);
+	extern void EnableInterrupt8188EGspi(PADAPTER padapter);
+	extern void DisableInterrupt8188EGspi(PADAPTER padapter);
+	extern void UpdateInterruptMask8188EGspi(PADAPTER padapter, u32 AddMSR, u32 RemoveMSR);
+	extern u8 HalQueryTxBufferStatus8189EGspi(PADAPTER padapter);
+	extern u8 HalQueryTxOQTBufferStatus8189EGspi(PADAPTER padapter);
+	extern void ClearInterrupt8188EGspi(PADAPTER padapter);
+	extern u8 CheckIPSStatus(PADAPTER padapter);
+#endif /* CONFIG_RTL8188E */
+#if defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN)
+	extern u8 RecvOnePkt(PADAPTER padapter);
+#endif /* CONFIG_WOWLAN */
+
+#endif /* __GSPI_OPS_H__ */
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/include/gspi_ops_linux.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/gspi_ops_linux.h
--- linux-5.6.3/3rdparty/rtl8821ce/include/gspi_ops_linux.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/gspi_ops_linux.h	2020-04-10 16:35:06.846661469 +0300
@@ -0,0 +1,18 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#ifndef __SDIO_OPS_LINUX_H__
+#define __SDIO_OPS_LINUX_H__
+
+#endif
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/include/gspi_osintf.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/gspi_osintf.h
--- linux-5.6.3/3rdparty/rtl8821ce/include/gspi_osintf.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/gspi_osintf.h	2020-04-10 16:35:06.846661469 +0300
@@ -0,0 +1,25 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#ifndef __SDIO_OSINTF_H__
+#define __SDIO_OSINTF_H__
+
+
+#ifdef PLATFORM_OS_CE
+	extern NDIS_STATUS ce_sd_get_dev_hdl(PADAPTER padapter);
+	SD_API_STATUS ce_sd_int_callback(SD_DEVICE_HANDLE hDevice, PADAPTER padapter);
+	extern void sd_setup_irs(PADAPTER padapter);
+#endif
+
+#endif
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/include/h2clbk.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/h2clbk.h
--- linux-5.6.3/3rdparty/rtl8821ce/include/h2clbk.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/h2clbk.h	2020-04-10 16:35:06.846661469 +0300
@@ -0,0 +1,26 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+
+
+#define _H2CLBK_H_
+
+
+void _lbk_cmd(PADAPTER Adapter);
+
+void _lbk_rsp(PADAPTER Adapter);
+
+void _lbk_evt(IN PADAPTER Adapter);
+
+void h2c_event_callback(unsigned char *dev, unsigned char *pbuf);
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/include/Hal8188EPhyCfg.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/Hal8188EPhyCfg.h
--- linux-5.6.3/3rdparty/rtl8821ce/include/Hal8188EPhyCfg.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/Hal8188EPhyCfg.h	2020-04-10 16:35:06.844661375 +0300
@@ -0,0 +1,260 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#ifndef __INC_HAL8188EPHYCFG_H__
+#define __INC_HAL8188EPHYCFG_H__
+
+
+/*--------------------------Define Parameters-------------------------------*/
+#define LOOP_LIMIT				5
+#define MAX_STALL_TIME			50		/* us */
+#define AntennaDiversityValue		0x80	/* (Adapter->bSoftwareAntennaDiversity ? 0x00 : 0x80) */
+#define MAX_TXPWR_IDX_NMODE_92S	63
+#define Reset_Cnt_Limit			3
+
+#ifdef CONFIG_PCI_HCI
+	#define MAX_AGGR_NUM	0x0B
+#else
+	#define MAX_AGGR_NUM	0x07
+#endif /* CONFIG_PCI_HCI */
+
+
+/*--------------------------Define Parameters-------------------------------*/
+
+
+/*------------------------------Define structure----------------------------*/
+
+#define	MAX_TX_COUNT_8188E			1
+
+/* BB/RF related */
+
+
+/*------------------------------Define structure----------------------------*/
+
+
+/*------------------------Export global variable----------------------------*/
+/*------------------------Export global variable----------------------------*/
+
+
+/*------------------------Export Marco Definition---------------------------*/
+/*------------------------Export Marco Definition---------------------------*/
+
+
+/*--------------------------Exported Function prototype---------------------*/
+/*
+ * BB and RF register read/write
+ *   */
+u32	PHY_QueryBBReg8188E(IN	PADAPTER	Adapter,
+			    IN	u32		RegAddr,
+			    IN	u32		BitMask);
+void	PHY_SetBBReg8188E(IN	PADAPTER	Adapter,
+			  IN	u32		RegAddr,
+			  IN	u32		BitMask,
+			  IN	u32		Data);
+u32	PHY_QueryRFReg8188E(IN	PADAPTER	Adapter,
+			    IN	enum rf_path		eRFPath,
+			    IN	u32				RegAddr,
+			    IN	u32				BitMask);
+void	PHY_SetRFReg8188E(IN	PADAPTER		Adapter,
+			  IN	enum rf_path		eRFPath,
+			  IN	u32				RegAddr,
+			  IN	u32				BitMask,
+			  IN	u32				Data);
+
+/*
+ * Initialization related function
+ */
+/* MAC/BB/RF HAL config */
+int	PHY_MACConfig8188E(IN	PADAPTER	Adapter);
+int	PHY_BBConfig8188E(IN	PADAPTER	Adapter);
+int	PHY_RFConfig8188E(IN	PADAPTER	Adapter);
+
+/* RF config */
+int	rtl8188e_PHY_ConfigRFWithParaFile(IN PADAPTER Adapter, IN u8 *pFileName, enum rf_path eRFPath);
+
+/*
+ * RF Power setting
+ */
+/* extern	BOOLEAN	PHY_SetRFPowerState(IN	PADAPTER			Adapter,
+ *									IN	RT_RF_POWER_STATE	eRFPowerState); */
+
+/*
+ * BB TX Power R/W
+ *   */
+void	PHY_GetTxPowerLevel8188E(IN	PADAPTER		Adapter,
+				 OUT s32		*powerlevel);
+void	PHY_SetTxPowerLevel8188E(IN	PADAPTER		Adapter,
+				 IN	u8			channel);
+BOOLEAN	PHY_UpdateTxPowerDbm8188E(IN	PADAPTER	Adapter,
+				  IN	int		powerInDbm);
+
+VOID
+PHY_SetTxPowerIndex_8188E(
+	IN	PADAPTER			Adapter,
+	IN	u32					PowerIndex,
+	IN	enum rf_path			RFPath,
+	IN	u8					Rate
+);
+
+u8
+PHY_GetTxPowerIndex_8188E(
+	IN	PADAPTER		pAdapter,
+	IN	enum rf_path		RFPath,
+	IN	u8				Rate,
+	IN	u8				BandWidth,
+	IN	u8				Channel,
+	struct txpwr_idx_comp *tic
+);
+
+/*
+ * Switch bandwidth for 8192S
+ */
+/* extern	void	PHY_SetBWModeCallback8192C(	IN	PRT_TIMER		pTimer	); */
+void	PHY_SetBWMode8188E(IN	PADAPTER			pAdapter,
+			   IN	enum channel_width	ChnlWidth,
+			   IN	unsigned char	Offset);
+
+/*
+ * Set FW CMD IO for 8192S.
+ */
+/* extern	BOOLEAN HalSetIO8192C(	IN	PADAPTER			Adapter,
+ *									IN	IO_TYPE				IOType); */
+
+/*
+ * Set A2 entry to fw for 8192S
+ *   */
+extern	void FillA2Entry8192C(IN	PADAPTER			Adapter,
+			      IN	u8				index,
+			      IN	u8				*val);
+
+
+/*
+ * channel switch related funciton
+ */
+/* extern	void	PHY_SwChnlCallback8192C(	IN	PRT_TIMER		pTimer	); */
+void	PHY_SwChnl8188E(IN	PADAPTER		pAdapter,
+			IN	u8			channel);
+
+VOID
+PHY_SetSwChnlBWMode8188E(
+	IN	PADAPTER			Adapter,
+	IN	u8					channel,
+	IN	enum channel_width	Bandwidth,
+	IN	u8					Offset40,
+	IN	u8					Offset80
+);
+
+VOID
+PHY_SetRFEReg_8188E(
+	IN PADAPTER		Adapter
+);
+/*
+ * BB/MAC/RF other monitor API
+ *   */
+VOID phy_set_rf_path_switch_8188e(IN	struct dm_struct	*phydm, IN	bool		bMain);
+
+extern	VOID
+PHY_SwitchEphyParameter(
+	IN	PADAPTER			Adapter
+);
+
+extern	VOID
+PHY_EnableHostClkReq(
+	IN	PADAPTER			Adapter
+);
+
+BOOLEAN
+SetAntennaConfig92C(
+	IN	PADAPTER	Adapter,
+	IN	u8		DefaultAnt
+);
+
+/*--------------------------Exported Function prototype---------------------*/
+
+/*
+ * Initialization related function
+ *
+ * MAC/BB/RF HAL config */
+/* extern s32 PHY_MACConfig8723(PADAPTER padapter);
+ * s32 PHY_BBConfig8723(PADAPTER padapter);
+ * s32 PHY_RFConfig8723(PADAPTER padapter); */
+
+
+
+/* ******************************************************************
+ * Note: If SIC_ENABLE under PCIE, because of the slow operation
+ *	you should
+ * 	2) "#define RTL8723_FPGA_VERIFICATION	1"				in Precomp.h.WlanE.Windows
+ * 	3) "#define RTL8190_Download_Firmware_From_Header	0"	in Precomp.h.WlanE.Windows if needed.
+ *   */
+#if (RTL8188E_SUPPORT == 1) && (RTL8188E_FPGA_TRUE_PHY_VERIFICATION == 1)
+	#define	SIC_ENABLE				1
+	#define	SIC_HW_SUPPORT		1
+#else
+	#define	SIC_ENABLE				0
+	#define	SIC_HW_SUPPORT		0
+#endif
+/* ****************************************************************** */
+
+
+#define	SIC_MAX_POLL_CNT		5
+
+#if (SIC_HW_SUPPORT == 1)
+	#define	SIC_CMD_READY			0
+	#define	SIC_CMD_PREWRITE		0x1
+	#if (RTL8188E_SUPPORT == 1)
+		#define	SIC_CMD_WRITE			0x40
+		#define	SIC_CMD_PREREAD		0x2
+		#define	SIC_CMD_READ			0x80
+		#define	SIC_CMD_INIT			0xf0
+		#define	SIC_INIT_VAL			0xff
+
+		#define	SIC_INIT_REG			0x1b7
+		#define	SIC_CMD_REG			0x1EB		/* 1byte */
+		#define	SIC_ADDR_REG			0x1E8		/* 1b4~1b5, 2 bytes */
+		#define	SIC_DATA_REG			0x1EC		/* 1b0~1b3 */
+	#else
+		#define	SIC_CMD_WRITE			0x11
+		#define	SIC_CMD_PREREAD		0x2
+		#define	SIC_CMD_READ			0x12
+		#define	SIC_CMD_INIT			0x1f
+		#define	SIC_INIT_VAL			0xff
+
+		#define	SIC_INIT_REG			0x1b7
+		#define	SIC_CMD_REG			0x1b6		/* 1byte */
+		#define	SIC_ADDR_REG			0x1b4		/* 1b4~1b5, 2 bytes */
+		#define	SIC_DATA_REG			0x1b0		/* 1b0~1b3 */
+	#endif
+#else
+	#define	SIC_CMD_READY			0
+	#define	SIC_CMD_WRITE			1
+	#define	SIC_CMD_READ			2
+
+	#if (RTL8188E_SUPPORT == 1)
+		#define	SIC_CMD_REG			0x1EB		/* 1byte */
+		#define	SIC_ADDR_REG			0x1E8		/* 1b9~1ba, 2 bytes */
+		#define	SIC_DATA_REG			0x1EC		/* 1bc~1bf */
+	#else
+		#define	SIC_CMD_REG			0x1b8		/* 1byte */
+		#define	SIC_ADDR_REG			0x1b9		/* 1b9~1ba, 2 bytes */
+		#define	SIC_DATA_REG			0x1bc		/* 1bc~1bf */
+	#endif
+#endif
+
+#if (SIC_ENABLE == 1)
+	VOID SIC_Init(IN PADAPTER Adapter);
+#endif
+
+
+#endif /* __INC_HAL8192CPHYCFG_H */
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/include/Hal8188EPhyReg.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/Hal8188EPhyReg.h
--- linux-5.6.3/3rdparty/rtl8821ce/include/Hal8188EPhyReg.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/Hal8188EPhyReg.h	2020-04-10 16:35:06.844661375 +0300
@@ -0,0 +1,1100 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#ifndef __INC_HAL8188EPHYREG_H__
+#define __INC_HAL8188EPHYREG_H__
+/*--------------------------Define Parameters-------------------------------*/
+/*
+ * BB-PHY register PMAC 0x100 PHY 0x800 - 0xEFF
+ * 1. PMAC duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF
+ * 2. 0x800/0x900/0xA00/0xC00/0xD00/0xE00
+ * 3. RF register 0x00-2E
+ * 4. Bit Mask for BB/RF register
+ * 5. Other defintion for BB/RF R/W
+ *   */
+
+
+/*
+ * 1. PMAC duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF
+ * 1. Page1(0x100)
+ *   */
+#define		rPMAC_Reset					0x100
+#define		rPMAC_TxStart				0x104
+#define		rPMAC_TxLegacySIG			0x108
+#define		rPMAC_TxHTSIG1				0x10c
+#define		rPMAC_TxHTSIG2				0x110
+#define		rPMAC_PHYDebug				0x114
+#define		rPMAC_TxPacketNum			0x118
+#define		rPMAC_TxIdle					0x11c
+#define		rPMAC_TxMACHeader0			0x120
+#define		rPMAC_TxMACHeader1			0x124
+#define		rPMAC_TxMACHeader2			0x128
+#define		rPMAC_TxMACHeader3			0x12c
+#define		rPMAC_TxMACHeader4			0x130
+#define		rPMAC_TxMACHeader5			0x134
+#define		rPMAC_TxDataType				0x138
+#define		rPMAC_TxRandomSeed			0x13c
+#define		rPMAC_CCKPLCPPreamble		0x140
+#define		rPMAC_CCKPLCPHeader			0x144
+#define		rPMAC_CCKCRC16				0x148
+#define		rPMAC_OFDMRxCRC32OK		0x170
+#define		rPMAC_OFDMRxCRC32Er		0x174
+#define		rPMAC_OFDMRxParityEr			0x178
+#define		rPMAC_OFDMRxCRC8Er			0x17c
+#define		rPMAC_CCKCRxRC16Er			0x180
+#define		rPMAC_CCKCRxRC32Er			0x184
+#define		rPMAC_CCKCRxRC32OK			0x188
+#define		rPMAC_TxStatus				0x18c
+
+/*
+ * 2. Page2(0x200)
+ *
+ * The following two definition are only used for USB interface. */
+#define		RF_BB_CMD_ADDR				0x02c0	/* RF/BB read/write command address. */
+#define		RF_BB_CMD_DATA				0x02c4	/* RF/BB read/write command data. */
+
+/*
+ * 3. Page8(0x800)
+ *   */
+#define		rFPGA0_RFMOD				0x800	/* RF mode & CCK TxSC */ /* RF BW Setting?? */
+
+#define		rFPGA0_TxInfo					0x804	/* Status report?? */
+#define		rFPGA0_PSDFunction			0x808
+
+#define		rFPGA0_TxGainStage			0x80c	/* Set TX PWR init gain? */
+
+#define		rFPGA0_RFTiming1				0x810	/* Useless now */
+#define		rFPGA0_RFTiming2				0x814
+
+#define		rFPGA0_XA_HSSIParameter1		0x820	/* RF 3 wire register */
+#define		rFPGA0_XA_HSSIParameter2		0x824
+#define		rFPGA0_XB_HSSIParameter1		0x828
+#define		rFPGA0_XB_HSSIParameter2		0x82c
+
+#define		rFPGA0_XA_LSSIParameter		0x840
+#define		rFPGA0_XB_LSSIParameter		0x844
+
+#define		rFPGA0_RFWakeUpParameter	0x850	/* Useless now */
+#define		rFPGA0_RFSleepUpParameter		0x854
+
+#define		rFPGA0_XAB_SwitchControl		0x858	/* RF Channel switch */
+#define		rFPGA0_XCD_SwitchControl		0x85c
+
+#define		rFPGA0_XA_RFInterfaceOE		0x860	/* RF Channel switch */
+#define		rFPGA0_XB_RFInterfaceOE		0x864
+#define		rFPGA0_XAB_RFInterfaceSW		0x870	/* RF Interface Software Control */
+#define		rFPGA0_XCD_RFInterfaceSW		0x874
+
+#define		rFPGA0_XAB_RFParameter		0x878	/* RF Parameter */
+#define		rFPGA0_XCD_RFParameter		0x87c
+
+#define		rFPGA0_AnalogParameter1		0x880	/* Crystal cap setting RF-R/W protection for parameter4?? */
+#define		rFPGA0_AnalogParameter2		0x884
+#define		rFPGA0_AnalogParameter3		0x888
+#define		rFPGA0_AdDaClockEn			0x888	/* enable ad/da clock1 for dual-phy */
+#define		rFPGA0_AnalogParameter4		0x88c
+
+#define		rFPGA0_XA_LSSIReadBack		0x8a0	/* Tranceiver LSSI Readback */
+#define		rFPGA0_XB_LSSIReadBack		0x8a4
+#define		rFPGA0_XC_LSSIReadBack		0x8a8
+#define		rFPGA0_XD_LSSIReadBack		0x8ac
+
+#define		rFPGA0_PSDReport				0x8b4	/* Useless now */
+#define		TransceiverA_HSPI_Readback		0x8b8	/* Transceiver A HSPI Readback */
+#define		TransceiverB_HSPI_Readback		0x8bc	/* Transceiver B HSPI Readback */
+#define		rFPGA0_XAB_RFInterfaceRB		0x8e0	/* Useless now */ /* RF Interface Readback Value */
+#define		rFPGA0_XCD_RFInterfaceRB		0x8e4	/* Useless now */
+
+/*
+ * 4. Page9(0x900)
+ *   */
+#define		rFPGA1_RFMOD				0x900	/* RF mode & OFDM TxSC */ /* RF BW Setting?? */
+
+#define		rFPGA1_TxBlock				0x904	/* Useless now */
+#define		rFPGA1_DebugSelect			0x908	/* Useless now */
+#define		rFPGA1_TxInfo					0x90c	/* Useless now */ /* Status report?? */
+
+/*
+ * 5. PageA(0xA00)
+ *
+ * Set Control channel to upper or lower. These settings are required only for 40MHz */
+#define		rCCK0_System					0xa00
+
+#define		rCCK0_AFESetting				0xa04	/* Disable init gain now */ /* Select RX path by RSSI */
+#define		rCCK0_CCA					0xa08	/* Disable init gain now */ /* Init gain */
+
+#define		rCCK0_RxAGC1				0xa0c	/* AGC default value, saturation level  */ /* Antenna Diversity, RX AGC, LNA Threshold, RX LNA Threshold useless now. Not the same as 90 series */
+#define		rCCK0_RxAGC2				0xa10	/* AGC & DAGC */
+
+#define		rCCK0_RxHP					0xa14
+
+#define		rCCK0_DSPParameter1			0xa18	/* Timing recovery & Channel estimation threshold */
+#define		rCCK0_DSPParameter2			0xa1c	/* SQ threshold */
+
+#define		rCCK0_TxFilter1				0xa20
+#define		rCCK0_TxFilter2				0xa24
+#define		rCCK0_DebugPort				0xa28	/* debug port and Tx filter3 */
+#define		rCCK0_FalseAlarmReport		0xa2c	/* 0xa2d	useless now 0xa30-a4f channel report */
+#define		rCCK0_TRSSIReport			0xa50
+#define		rCCK0_RxReport            			0xa54  /* 0xa57 */
+#define		rCCK0_FACounterLower      		0xa5c  /* 0xa5b */
+#define		rCCK0_FACounterUpper      		0xa58  /* 0xa5c */
+
+/*
+ * PageB(0xB00)
+ *   */
+#define		rPdp_AntA					0xb00
+#define		rPdp_AntA_4				0xb04
+#define		rConfig_Pmpd_AntA			0xb28
+#define		rConfig_ram64x16				0xb2c
+#define		rConfig_AntA					0xb68
+#define		rConfig_AntB					0xb6c
+#define		rPdp_AntB					0xb70
+#define		rPdp_AntB_4					0xb74
+#define		rConfig_Pmpd_AntB			0xb98
+#define		rAPK							0xbd8
+
+
+
+/*
+ * 6. PageC(0xC00)
+ *   */
+#define		rOFDM0_LSTF					0xc00
+
+#define		rOFDM0_TRxPathEnable			0xc04
+#define		rOFDM0_TRMuxPar				0xc08
+#define		rOFDM0_TRSWIsolation			0xc0c
+
+#define		rOFDM0_XARxAFE				0xc10  /* RxIQ DC offset, Rx digital filter, DC notch filter */
+#define		rOFDM0_XARxIQImbalance    		0xc14  /* RxIQ imblance matrix */
+#define		rOFDM0_XBRxAFE			0xc18
+#define		rOFDM0_XBRxIQImbalance		0xc1c
+#define		rOFDM0_XCRxAFE			0xc20
+#define		rOFDM0_XCRxIQImbalance		0xc24
+#define		rOFDM0_XDRxAFE			0xc28
+#define		rOFDM0_XDRxIQImbalance		0xc2c
+
+#define		rOFDM0_RxDetector1			0xc30  /* PD, BW & SBD	 */ /* DM tune init gain */
+#define		rOFDM0_RxDetector2			0xc34  /* SBD & Fame Sync. */
+#define		rOFDM0_RxDetector3			0xc38  /* Frame Sync. */
+#define		rOFDM0_RxDetector4			0xc3c  /* PD, SBD, Frame Sync & Short-GI */
+
+#define		rOFDM0_RxDSP				0xc40  /* Rx Sync Path */
+#define		rOFDM0_CFOandDAGC			0xc44  /* CFO & DAGC */
+#define		rOFDM0_CCADropThreshold		0xc48 /* CCA Drop threshold */
+#define		rOFDM0_ECCAThreshold			0xc4c /* energy CCA */
+
+#define		rOFDM0_XAAGCCore1			0xc50	/* DIG */
+#define		rOFDM0_XAAGCCore2			0xc54
+#define		rOFDM0_XBAGCCore1			0xc58
+#define		rOFDM0_XBAGCCore2			0xc5c
+#define		rOFDM0_XCAGCCore1			0xc60
+#define		rOFDM0_XCAGCCore2			0xc64
+#define		rOFDM0_XDAGCCore1			0xc68
+#define		rOFDM0_XDAGCCore2			0xc6c
+
+#define		rOFDM0_AGCParameter1		0xc70
+#define		rOFDM0_AGCParameter2		0xc74
+#define		rOFDM0_AGCRSSITable			0xc78
+#define		rOFDM0_HTSTFAGC				0xc7c
+
+#define		rOFDM0_XATxIQImbalance		0xc80	/* TX PWR TRACK and DIG */
+#define		rOFDM0_XATxAFE				0xc84
+#define		rOFDM0_XBTxIQImbalance		0xc88
+#define		rOFDM0_XBTxAFE				0xc8c
+#define		rOFDM0_XCTxIQImbalance		0xc90
+#define		rOFDM0_XCTxAFE			0xc94
+#define		rOFDM0_XDTxIQImbalance		0xc98
+#define		rOFDM0_XDTxAFE				0xc9c
+
+#define		rOFDM0_RxIQExtAnta			0xca0
+#define		rOFDM0_TxCoeff1				0xca4
+#define		rOFDM0_TxCoeff2				0xca8
+#define		rOFDM0_TxCoeff3				0xcac
+#define		rOFDM0_TxCoeff4				0xcb0
+#define		rOFDM0_TxCoeff5				0xcb4
+#define		rOFDM0_TxCoeff6				0xcb8
+#define		rOFDM0_RxHPParameter		0xce0
+#define		rOFDM0_TxPseudoNoiseWgt		0xce4
+#define		rOFDM0_FrameSync			0xcf0
+#define		rOFDM0_DFSReport			0xcf4
+
+
+/*
+ * 7. PageD(0xD00)
+ *   */
+#define		rOFDM1_LSTF					0xd00
+#define		rOFDM1_TRxPathEnable			0xd04
+
+#define		rOFDM1_CFO					0xd08	/* No setting now */
+#define		rOFDM1_CSI1					0xd10
+#define		rOFDM1_SBD					0xd14
+#define		rOFDM1_CSI2					0xd18
+#define		rOFDM1_CFOTracking			0xd2c
+#define		rOFDM1_TRxMesaure1			0xd34
+#define		rOFDM1_IntfDet				0xd3c
+#define		rOFDM1_csi_fix_mask1				0xd40
+#define		rOFDM1_csi_fix_mask2				0xd44
+#define		rOFDM1_PseudoNoiseStateAB	0xd50
+#define		rOFDM1_PseudoNoiseStateCD	0xd54
+#define		rOFDM1_RxPseudoNoiseWgt		0xd58
+
+#define		rOFDM_PHYCounter1			0xda0  /* cca, parity fail */
+#define		rOFDM_PHYCounter2			0xda4  /* rate illegal, crc8 fail */
+#define		rOFDM_PHYCounter3			0xda8  /* MCS not support */
+
+#define		rOFDM_ShortCFOAB			0xdac	/* No setting now */
+#define		rOFDM_ShortCFOCD			0xdb0
+#define		rOFDM_LongCFOAB				0xdb4
+#define		rOFDM_LongCFOCD				0xdb8
+#define		rOFDM_TailCFOAB				0xdbc
+#define		rOFDM_TailCFOCD				0xdc0
+#define		rOFDM_PWMeasure1		0xdc4
+#define		rOFDM_PWMeasure2		0xdc8
+#define		rOFDM_BWReport				0xdcc
+#define		rOFDM_AGCReport				0xdd0
+#define		rOFDM_RxSNR				0xdd4
+#define		rOFDM_RxEVMCSI				0xdd8
+#define		rOFDM_SIGReport				0xddc
+
+
+/*
+ * 8. PageE(0xE00)
+ *   */
+#define		rTxAGC_A_Rate18_06			0xe00
+#define		rTxAGC_A_Rate54_24			0xe04
+#define		rTxAGC_A_CCK1_Mcs32			0xe08
+#define		rTxAGC_A_Mcs03_Mcs00		0xe10
+#define		rTxAGC_A_Mcs07_Mcs04		0xe14
+#define		rTxAGC_A_Mcs11_Mcs08		0xe18
+#define		rTxAGC_A_Mcs15_Mcs12		0xe1c
+
+#define		rTxAGC_B_Rate18_06			0x830
+#define		rTxAGC_B_Rate54_24			0x834
+#define		rTxAGC_B_CCK1_55_Mcs32		0x838
+#define		rTxAGC_B_Mcs03_Mcs00		0x83c
+#define		rTxAGC_B_Mcs07_Mcs04		0x848
+#define		rTxAGC_B_Mcs11_Mcs08		0x84c
+#define		rTxAGC_B_Mcs15_Mcs12		0x868
+#define		rTxAGC_B_CCK11_A_CCK2_11		0x86c
+
+#define		rFPGA0_IQK					0xe28
+#define		rTx_IQK_Tone_A				0xe30
+#define		rRx_IQK_Tone_A				0xe34
+#define		rTx_IQK_PI_A					0xe38
+#define		rRx_IQK_PI_A					0xe3c
+
+#define		rTx_IQK						0xe40
+#define		rRx_IQK						0xe44
+#define		rIQK_AGC_Pts					0xe48
+#define		rIQK_AGC_Rsp					0xe4c
+#define		rTx_IQK_Tone_B				0xe50
+#define		rRx_IQK_Tone_B				0xe54
+#define		rTx_IQK_PI_B					0xe58
+#define		rRx_IQK_PI_B					0xe5c
+#define		rIQK_AGC_Cont				0xe60
+
+#define		rBlue_Tooth					0xe6c
+#define		rRx_Wait_CCA					0xe70
+#define		rTx_CCK_RFON					0xe74
+#define		rTx_CCK_BBON				0xe78
+#define		rTx_OFDM_RFON				0xe7c
+#define		rTx_OFDM_BBON				0xe80
+#define		rTx_To_Rx					0xe84
+#define		rTx_To_Tx					0xe88
+#define		rRx_CCK						0xe8c
+
+#define		rTx_Power_Before_IQK_A		0xe94
+#define		rTx_Power_After_IQK_A			0xe9c
+
+#define		rRx_Power_Before_IQK_A		0xea0
+#define		rRx_Power_Before_IQK_A_2		0xea4
+#define		rRx_Power_After_IQK_A			0xea8
+#define		rRx_Power_After_IQK_A_2		0xeac
+
+#define		rTx_Power_Before_IQK_B		0xeb4
+#define		rTx_Power_After_IQK_B			0xebc
+
+#define		rRx_Power_Before_IQK_B		0xec0
+#define		rRx_Power_Before_IQK_B_2		0xec4
+#define		rRx_Power_After_IQK_B			0xec8
+#define		rRx_Power_After_IQK_B_2		0xecc
+
+#define		rRx_OFDM					0xed0
+#define		rRx_Wait_RIFS				0xed4
+#define		rRx_TO_Rx					0xed8
+#define		rStandby						0xedc
+#define		rSleep						0xee0
+#define		rPMPD_ANAEN				0xeec
+
+/*
+ * 7. RF Register 0x00-0x2E (RF 8256)
+ * RF-0222D 0x00-3F
+ *
+ * Zebra1 */
+#define		rZebra1_HSSIEnable				0x0	/* Useless now */
+#define		rZebra1_TRxEnable1			0x1
+#define		rZebra1_TRxEnable2			0x2
+#define		rZebra1_AGC					0x4
+#define		rZebra1_ChargePump			0x5
+#define		rZebra1_Channel				0x7	/* RF channel switch */
+
+/* #endif */
+#define		rZebra1_TxGain				0x8	/* Useless now */
+#define		rZebra1_TxLPF					0x9
+#define		rZebra1_RxLPF					0xb
+#define		rZebra1_RxHPFCorner			0xc
+
+/* Zebra4 */
+#define		rGlobalCtrl					0	/* Useless now */
+#define		rRTL8256_TxLPF				19
+#define		rRTL8256_RxLPF				11
+
+/* RTL8258 */
+#define		rRTL8258_TxLPF				0x11	/* Useless now */
+#define		rRTL8258_RxLPF				0x13
+#define		rRTL8258_RSSILPF				0xa
+
+/*
+ * RL6052 Register definition
+ *   */
+#define		RF_AC						0x00	/*  */
+
+#define		RF_IQADJ_G1					0x01	/*  */
+#define		RF_IQADJ_G2					0x02	/*  */
+
+#define		RF_POW_TRSW				0x05	/*  */
+
+#define		RF_GAIN_RX					0x06	/*  */
+#define		RF_GAIN_TX					0x07	/*  */
+
+#define		RF_TXM_IDAC					0x08	/*  */
+#define		RF_IPA_G						0x09	/*  */
+#define		RF_TXBIAS_G					0x0A
+#define		RF_TXPA_AG					0x0B
+#define		RF_IPA_A						0x0C	/*  */
+#define		RF_TXBIAS_A					0x0D
+#define		RF_BS_PA_APSET_G9_G11		0x0E
+#define		RF_BS_IQGEN					0x0F	/*  */
+
+#define		RF_MODE1					0x10	/*  */
+#define		RF_MODE2					0x11	/*  */
+
+#define		RF_RX_AGC_HP				0x12	/*  */
+#define		RF_TX_AGC					0x13	/*  */
+#define		RF_BIAS						0x14	/*  */
+#define		RF_IPA						0x15	/*  */
+#define		RF_TXBIAS					0x16
+#define		RF_POW_ABILITY				0x17	/*  */
+#define		RF_CHNLBW					0x18	/* RF channel and BW switch */
+#define		RF_TOP						0x19	/*  */
+
+#define		RF_RX_G1					0x1A	/*  */
+#define		RF_RX_G2					0x1B	/*  */
+
+#define		RF_RX_BB2					0x1C	/*  */
+#define		RF_RX_BB1					0x1D	/*  */
+
+#define		RF_RCK1						0x1E	/*  */
+#define		RF_RCK2						0x1F	/*  */
+
+#define		RF_TX_G1						0x20	/*  */
+#define		RF_TX_G2						0x21	/*  */
+#define		RF_TX_G3						0x22	/*  */
+
+#define		RF_TX_BB1					0x23	/*  */
+
+#define		RF_T_METER_88E					0x42	/*  */
+#define		RF_T_METER					0x24	/*  */
+
+#define		RF_SYN_G1					0x25	/* RF TX Power control */
+#define		RF_SYN_G2					0x26	/* RF TX Power control */
+#define		RF_SYN_G3					0x27	/* RF TX Power control */
+#define		RF_SYN_G4					0x28	/* RF TX Power control */
+#define		RF_SYN_G5					0x29	/* RF TX Power control */
+#define		RF_SYN_G6					0x2A	/* RF TX Power control */
+#define		RF_SYN_G7					0x2B	/* RF TX Power control */
+#define		RF_SYN_G8					0x2C	/* RF TX Power control */
+
+#define		RF_RCK_OS					0x30	/* RF TX PA control */
+#define		RF_TXPA_G1					0x31	/* RF TX PA control */
+#define		RF_TXPA_G2					0x32	/* RF TX PA control */
+#define		RF_TXPA_G3					0x33	/* RF TX PA control */
+#define		RF_TX_BIAS_A					0x35
+#define		RF_TX_BIAS_D					0x36
+#define		RF_LOBF_9					0x38
+#define		RF_RXRF_A3					0x3C	/*	 */
+#define		RF_TRSW						0x3F
+
+#define		RF_TXRF_A2					0x41
+#define		RF_TXPA_G4					0x46
+#define		RF_TXPA_A4					0x4B
+#define	RF_0x52					0x52
+#define		RF_WE_LUT					0xEF
+
+
+/*
+ * Bit Mask
+ *
+ * 1. Page1(0x100) */
+#define		bBBResetB					0x100	/* Useless now? */
+#define		bGlobalResetB					0x200
+#define		bOFDMTxStart					0x4
+#define		bCCKTxStart					0x8
+#define		bCRC32Debug					0x100
+#define		bPMACLoopback				0x10
+#define		bTxLSIG						0xffffff
+#define		bOFDMTxRate					0xf
+#define		bOFDMTxReserved				0x10
+#define		bOFDMTxLength				0x1ffe0
+#define		bOFDMTxParity				0x20000
+#define		bTxHTSIG1					0xffffff
+#define		bTxHTMCSRate				0x7f
+#define		bTxHTBW						0x80
+#define		bTxHTLength					0xffff00
+#define		bTxHTSIG2					0xffffff
+#define		bTxHTSmoothing				0x1
+#define		bTxHTSounding				0x2
+#define		bTxHTReserved				0x4
+#define		bTxHTAggreation				0x8
+#define		bTxHTSTBC					0x30
+#define		bTxHTAdvanceCoding			0x40
+#define		bTxHTShortGI					0x80
+#define		bTxHTNumberHT_LTF			0x300
+#define		bTxHTCRC8					0x3fc00
+#define		bCounterReset				0x10000
+#define		bNumOfOFDMTx				0xffff
+#define		bNumOfCCKTx					0xffff0000
+#define		bTxIdleInterval				0xffff
+#define		bOFDMService					0xffff0000
+#define		bTxMACHeader				0xffffffff
+#define		bTxDataInit					0xff
+#define		bTxHTMode					0x100
+#define		bTxDataType					0x30000
+#define		bTxRandomSeed				0xffffffff
+#define		bCCKTxPreamble				0x1
+#define		bCCKTxSFD					0xffff0000
+#define		bCCKTxSIG					0xff
+#define		bCCKTxService					0xff00
+#define		bCCKLengthExt					0x8000
+#define		bCCKTxLength					0xffff0000
+#define		bCCKTxCRC16					0xffff
+#define		bCCKTxStatus					0x1
+#define		bOFDMTxStatus				0x2
+
+#define		IS_BB_REG_OFFSET_92S(_Offset)		((_Offset >= 0x800) && (_Offset <= 0xfff))
+
+/* 2. Page8(0x800) */
+#define		bRFMOD						0x1	/* Reg 0x800 rFPGA0_RFMOD */
+#define		bJapanMode					0x2
+#define		bCCKTxSC						0x30
+#define		bCCKEn						0x1000000
+#define		bOFDMEn					0x2000000
+
+#define		bOFDMRxADCPhase           		0x10000	/* Useless now */
+#define		bOFDMTxDACPhase		0x40000
+#define		bXATxAGC				0x3f
+
+#define		bAntennaSelect			0x0300
+
+#define		bXBTxAGC                  				0xf00	/* Reg 80c rFPGA0_TxGainStage */
+#define		bXCTxAGC				0xf000
+#define		bXDTxAGC				0xf0000
+
+#define		bPAStart                  				0xf0000000	/* Useless now */
+#define		bTRStart				0x00f00000
+#define		bRFStart				0x0000f000
+#define		bBBStart				0x000000f0
+#define		bBBCCKStart			0x0000000f
+#define		bPAEnd                    				0xf          /* Reg0x814 */
+#define		bTREnd				0x0f000000
+#define		bRFEnd				0x000f0000
+#define		bCCAMask                  				0x000000f0   /* T2R */
+#define		bR2RCCAMask			0x00000f00
+#define		bHSSI_R2TDelay			0xf8000000
+#define		bHSSI_T2RDelay			0xf80000
+#define		bContTxHSSI               			0x400     /* chane gain at continue Tx */
+#define		bIGFromCCK			0x200
+#define		bAGCAddress			0x3f
+#define		bRxHPTx				0x7000
+#define		bRxHPT2R				0x38000
+#define		bRxHPCCKIni			0xc0000
+#define		bAGCTxCode			0xc00000
+#define		bAGCRxCode			0x300000
+
+#define		b3WireDataLength          			0x800	/* Reg 0x820~84f rFPGA0_XA_HSSIParameter1 */
+#define		b3WireAddressLength		0x400
+
+#define		b3WireRFPowerDown         		0x1	/* Useless now
+ * #define bHWSISelect		0x8 */
+#define		b5GPAPEPolarity			0x40000000
+#define		b2GPAPEPolarity			0x80000000
+#define		bRFSW_TxDefaultAnt		0x3
+#define		bRFSW_TxOptionAnt		0x30
+#define		bRFSW_RxDefaultAnt		0x300
+#define		bRFSW_RxOptionAnt		0x3000
+#define		bRFSI_3WireData			0x1
+#define		bRFSI_3WireClock			0x2
+#define		bRFSI_3WireLoad			0x4
+#define		bRFSI_3WireRW			0x8
+#define		bRFSI_3Wire			0xf
+
+#define		bRFSI_RFENV               		0x10	/* Reg 0x870 rFPGA0_XAB_RFInterfaceSW */
+
+#define		bRFSI_TRSW                		0x20	/* Useless now */
+#define		bRFSI_TRSWB		0x40
+#define		bRFSI_ANTSW		0x100
+#define		bRFSI_ANTSWB		0x200
+#define		bRFSI_PAPE			0x400
+#define		bRFSI_PAPE5G		0x800
+#define		bBandSelect			0x1
+#define		bHTSIG2_GI			0x80
+#define		bHTSIG2_Smoothing		0x01
+#define		bHTSIG2_Sounding		0x02
+#define		bHTSIG2_Aggreaton		0x08
+#define		bHTSIG2_STBC		0x30
+#define		bHTSIG2_AdvCoding		0x40
+#define		bHTSIG2_NumOfHTLTF	0x300
+#define		bHTSIG2_CRC8		0x3fc
+#define		bHTSIG1_MCS		0x7f
+#define		bHTSIG1_BandWidth		0x80
+#define		bHTSIG1_HTLength		0xffff
+#define		bLSIG_Rate			0xf
+#define		bLSIG_Reserved		0x10
+#define		bLSIG_Length		0x1fffe
+#define		bLSIG_Parity			0x20
+#define		bCCKRxPhase		0x4
+
+#define		bLSSIReadAddress          		0x7f800000   /* T65 RF */
+
+#define		bLSSIReadEdge             		0x80000000   /* LSSI "Read" edge signal */
+
+#define		bLSSIReadBackData         		0xfffff		/* T65 RF */
+
+#define		bLSSIReadOKFlag           		0x1000	/* Useless now */
+#define		bCCKSampleRate            		0x8       /* 0: 44MHz, 1:88MHz      		 */
+#define		bRegulator0Standby		0x1
+#define		bRegulatorPLLStandby	0x2
+#define		bRegulator1Standby		0x4
+#define		bPLLPowerUp		0x8
+#define		bDPLLPowerUp		0x10
+#define		bDA10PowerUp		0x20
+#define		bAD7PowerUp		0x200
+#define		bDA6PowerUp		0x2000
+#define		bXtalPowerUp		0x4000
+#define		b40MDClkPowerUP	0x8000
+#define		bDA6DebugMode		0x20000
+#define		bDA6Swing			0x380000
+
+#define		bADClkPhase               		0x4000000	/* Reg 0x880 rFPGA0_AnalogParameter1 20/40 CCK support switch 40/80 BB MHZ */
+
+#define		b80MClkDelay              		0x18000000	/* Useless */
+#define		bAFEWatchDogEnable	0x20000000
+
+#define		bXtalCap01                			0xc0000000	/* Reg 0x884 rFPGA0_AnalogParameter2 Crystal cap */
+#define		bXtalCap23			0x3
+#define		bXtalCap92x				0x0f000000
+#define		bXtalCap			0x0f000000
+
+#define		bIntDifClkEnable          		0x400	/* Useless */
+#define		bExtSigClkEnable		0x800
+#define		bBandgapMbiasPowerUp	0x10000
+#define		bAD11SHGain		0xc0000
+#define		bAD11InputRange		0x700000
+#define		bAD11OPCurrent		0x3800000
+#define		bIPathLoopback		0x4000000
+#define		bQPathLoopback		0x8000000
+#define		bAFELoopback		0x10000000
+#define		bDA10Swing		0x7e0
+#define		bDA10Reverse		0x800
+#define		bDAClkSource		0x1000
+#define		bAD7InputRange		0x6000
+#define		bAD7Gain			0x38000
+#define		bAD7OutputCMMode	0x40000
+#define		bAD7InputCMMode	0x380000
+#define		bAD7Current		0xc00000
+#define		bRegulatorAdjust		0x7000000
+#define		bAD11PowerUpAtTx	0x1
+#define		bDA10PSAtTx		0x10
+#define		bAD11PowerUpAtRx	0x100
+#define		bDA10PSAtRx		0x1000
+#define		bCCKRxAGCFormat		0x200
+#define		bPSDFFTSamplepPoint	0xc000
+#define		bPSDAverageNum		0x3000
+#define		bIQPathControl		0xc00
+#define		bPSDFreq			0x3ff
+#define		bPSDAntennaPath		0x30
+#define		bPSDIQSwitch		0x40
+#define		bPSDRxTrigger		0x400000
+#define		bPSDTxTrigger		0x80000000
+#define		bPSDSineToneScale		0x7f000000
+#define		bPSDReport		0xffff
+
+/* 3. Page9(0x900) */
+#define		bOFDMTxSC                 		0x30000000	/* Useless */
+#define		bCCKTxOn			0x1
+#define		bOFDMTxOn		0x2
+#define		bDebugPage                		0xfff  /* reset debug page and also HWord, LWord */
+#define		bDebugItem                		0xff   /* reset debug page and LWord */
+#define		bAntL				0x10
+#define		bAntNonHT			0x100
+#define		bAntHT1			0x1000
+#define		bAntHT2			0x10000
+#define		bAntHT1S1			0x100000
+#define		bAntNonHTS1		0x1000000
+
+/* 4. PageA(0xA00) */
+#define		bCCKBBMode                		0x3	/* Useless */
+#define		bCCKTxPowerSaving		0x80
+#define		bCCKRxPowerSaving		0x40
+
+#define		bCCKSideBand              		0x10	/* Reg 0xa00 rCCK0_System 20/40 switch */
+
+#define		bCCKScramble              		0x8	/* Useless */
+#define		bCCKAntDiversity			0x8000
+#define		bCCKCarrierRecovery		0x4000
+#define		bCCKTxRate			0x3000
+#define		bCCKDCCancel		0x0800
+#define		bCCKISICancel		0x0400
+#define		bCCKMatchFilter		0x0200
+#define		bCCKEqualizer		0x0100
+#define		bCCKPreambleDetect		0x800000
+#define		bCCKFastFalseCCA		0x400000
+#define		bCCKChEstStart		0x300000
+#define		bCCKCCACount		0x080000
+#define		bCCKcs_lim			0x070000
+#define		bCCKBistMode		0x80000000
+#define		bCCKCCAMask		0x40000000
+#define		bCCKTxDACPhase		0x4
+#define		bCCKRxADCPhase         	   	0x20000000   /* r_rx_clk */
+#define		bCCKr_cp_mode0		0x0100
+#define		bCCKTxDCOffset		0xf0
+#define		bCCKRxDCOffset		0xf
+#define		bCCKCCAMode		0xc000
+#define		bCCKFalseCS_lim		0x3f00
+#define		bCCKCS_ratio		0xc00000
+#define		bCCKCorgBit_sel		0x300000
+#define		bCCKPD_lim		0x0f0000
+#define		bCCKNewCCA		0x80000000
+#define		bCCKRxHPofIG		0x8000
+#define		bCCKRxIG			0x7f00
+#define		bCCKLNAPolarity		0x800000
+#define		bCCKRx1stGain		0x7f0000
+#define		bCCKRFExtend              		0x20000000 /* CCK Rx Iinital gain polarity */
+#define		bCCKRxAGCSatLevel		0x1f000000
+#define		bCCKRxAGCSatCount		0xe0
+#define		bCCKRxRFSettle            		0x1f       /* AGCsamp_dly */
+#define		bCCKFixedRxAGC		0x8000
+/* #define bCCKRxAGCFormat		0x4000 */   /* remove to HSSI register 0x824 */
+#define		bCCKAntennaPolarity		0x2000
+#define		bCCKTxFilterType		0x0c00
+#define		bCCKRxAGCReportType		0x0300
+#define		bCCKRxDAGCEn		0x80000000
+#define		bCCKRxDAGCPeriod		0x20000000
+#define		bCCKRxDAGCSatLevel		0x1f000000
+#define		bCCKTimingRecovery		0x800000
+#define		bCCKTxC0			0x3f0000
+#define		bCCKTxC1			0x3f000000
+#define		bCCKTxC2			0x3f
+#define		bCCKTxC3			0x3f00
+#define		bCCKTxC4			0x3f0000
+#define		bCCKTxC5			0x3f000000
+#define		bCCKTxC6			0x3f
+#define		bCCKTxC7			0x3f00
+#define		bCCKDebugPort		0xff0000
+#define		bCCKDACDebug		0x0f000000
+#define		bCCKFalseAlarmEnable	0x8000
+#define		bCCKFalseAlarmRead	0x4000
+#define		bCCKTRSSI			0x7f
+#define		bCCKRxAGCReport		0xfe
+#define		bCCKRxReport_AntSel	0x80000000
+#define		bCCKRxReport_MFOff	0x40000000
+#define		bCCKRxRxReport_SQLoss	0x20000000
+#define		bCCKRxReport_Pktloss	0x10000000
+#define		bCCKRxReport_Lockedbit	0x08000000
+#define		bCCKRxReport_RateError	0x04000000
+#define		bCCKRxReport_RxRate	0x03000000
+#define		bCCKRxFACounterLower	0xff
+#define		bCCKRxFACounterUpper	0xff000000
+#define		bCCKRxHPAGCStart		0xe000
+#define		bCCKRxHPAGCFinal		0x1c00
+#define		bCCKRxFalseAlarmEnable	0x8000
+#define		bCCKFACounterFreeze	0x4000
+#define		bCCKTxPathSel		0x10000000
+#define		bCCKDefaultRxPath		0xc000000
+#define		bCCKOptionRxPath		0x3000000
+
+/* 5. PageC(0xC00) */
+#define		bNumOfSTF                			0x3	/* Useless */
+#define		bShift_L			0xc0
+#define		bGI_TH			0xc
+#define		bRxPathA			0x1
+#define		bRxPathB			0x2
+#define		bRxPathC			0x4
+#define		bRxPathD			0x8
+#define		bTxPathA			0x1
+#define		bTxPathB			0x2
+#define		bTxPathC			0x4
+#define		bTxPathD			0x8
+#define		bTRSSIFreq			0x200
+#define		bADCBackoff			0x3000
+#define		bDFIRBackoff			0xc000
+#define		bTRSSILatchPhase		0x10000
+#define		bRxIDCOffset			0xff
+#define		bRxQDCOffset		0xff00
+#define		bRxDFIRMode		0x1800000
+#define		bRxDCNFType		0xe000000
+#define		bRXIQImb_A		0x3ff
+#define		bRXIQImb_B			0xfc00
+#define		bRXIQImb_C			0x3f0000
+#define		bRXIQImb_D		0xffc00000
+#define		bDC_dc_Notch		0x60000
+#define		bRxNBINotch		0x1f000000
+#define		bPD_TH			0xf
+#define		bPD_TH_Opt2		0xc000
+#define		bPWED_TH			0x700
+#define		bIfMF_Win_L		0x800
+#define		bPD_Option			0x1000
+#define		bMF_Win_L			0xe000
+#define		bBW_Search_L		0x30000
+#define		bwin_enh_L			0xc0000
+#define		bBW_TH			0x700000
+#define		bED_TH2			0x3800000
+#define		bBW_option			0x4000000
+#define		bRatio_TH			0x18000000
+#define		bWindow_L			0xe0000000
+#define		bSBD_Option		0x1
+#define		bFrame_TH			0x1c
+#define		bFS_Option			0x60
+#define		bDC_Slope_check		0x80
+#define		bFGuard_Counter_DC_L	0xe00
+#define		bFrame_Weight_Short	0x7000
+#define		bSub_Tune			0xe00000
+#define		bFrame_DC_Length		0xe000000
+#define		bSBD_start_offset		0x30000000
+#define		bFrame_TH_2		0x7
+#define		bFrame_GI2_TH		0x38
+#define		bGI2_Sync_en		0x40
+#define		bSarch_Short_Early		0x300
+#define		bSarch_Short_Late		0xc00
+#define		bSarch_GI2_Late		0x70000
+#define		bCFOAntSum		0x1
+#define		bCFOAcc			0x2
+#define		bCFOStartOffset		0xc
+#define		bCFOLookBack		0x70
+#define		bCFOSumWeight		0x80
+#define		bDAGCEnable		0x10000
+#define		bTXIQImb_A			0x3ff
+#define		bTXIQImb_B			0xfc00
+#define		bTXIQImb_C			0x3f0000
+#define		bTXIQImb_D			0xffc00000
+#define		bTxIDCOffset			0xff
+#define		bTxQDCOffset		0xff00
+#define		bTxDFIRMode		0x10000
+#define		bTxPesudoNoiseOn		0x4000000
+#define		bTxPesudoNoise_A		0xff
+#define		bTxPesudoNoise_B		0xff00
+#define		bTxPesudoNoise_C		0xff0000
+#define		bTxPesudoNoise_D		0xff000000
+#define		bCCADropOption		0x20000
+#define		bCCADropThres		0xfff00000
+#define		bEDCCA_H			0xf
+#define		bEDCCA_L			0xf0
+#define		bLambda_ED		0x300
+#define		bRxInitialGain			0x7f
+#define		bRxAntDivEn		0x80
+#define		bRxAGCAddressForLNA	0x7f00
+#define		bRxHighPowerFlow		0x8000
+#define		bRxAGCFreezeThres		0xc0000
+#define		bRxFreezeStep_AGC1	0x300000
+#define		bRxFreezeStep_AGC2	0xc00000
+#define		bRxFreezeStep_AGC3	0x3000000
+#define		bRxFreezeStep_AGC0	0xc000000
+#define		bRxRssi_Cmp_En		0x10000000
+#define		bRxQuickAGCEn		0x20000000
+#define		bRxAGCFreezeThresMode	0x40000000
+#define		bRxOverFlowCheckType	0x80000000
+#define		bRxAGCShift			0x7f
+#define		bTRSW_Tri_Only		0x80
+#define		bPowerThres		0x300
+#define		bRxAGCEn			0x1
+#define		bRxAGCTogetherEn		0x2
+#define		bRxAGCMin		0x4
+#define		bRxHP_Ini			0x7
+#define		bRxHP_TRLNA		0x70
+#define		bRxHP_RSSI			0x700
+#define		bRxHP_BBP1		0x7000
+#define		bRxHP_BBP2		0x70000
+#define		bRxHP_BBP3		0x700000
+#define		bRSSI_H                  			0x7f0000     /* the threshold for high power */
+#define		bRSSI_Gen                			0x7f000000   /* the threshold for ant diversity */
+#define		bRxSettle_TRSW		0x7
+#define		bRxSettle_LNA		0x38
+#define		bRxSettle_RSSI		0x1c0
+#define		bRxSettle_BBP		0xe00
+#define		bRxSettle_RxHP		0x7000
+#define		bRxSettle_AntSW_RSSI	0x38000
+#define		bRxSettle_AntSW		0xc0000
+#define		bRxProcessTime_DAGC	0x300000
+#define		bRxSettle_HSSI		0x400000
+#define		bRxProcessTime_BBPPW	0x800000
+#define		bRxAntennaPowerShift	0x3000000
+#define		bRSSITableSelect		0xc000000
+#define		bRxHP_Final			0x7000000
+#define		bRxHTSettle_BBP		0x7
+#define		bRxHTSettle_HSSI		0x8
+#define		bRxHTSettle_RxHP		0x70
+#define		bRxHTSettle_BBPPW		0x80
+#define		bRxHTSettle_Idle		0x300
+#define		bRxHTSettle_Reserved	0x1c00
+#define		bRxHTRxHPEn		0x8000
+#define		bRxHTAGCFreezeThres	0x30000
+#define		bRxHTAGCTogetherEn	0x40000
+#define		bRxHTAGCMin		0x80000
+#define		bRxHTAGCEn		0x100000
+#define		bRxHTDAGCEn		0x200000
+#define		bRxHTRxHP_BBP		0x1c00000
+#define		bRxHTRxHP_Final		0xe0000000
+#define		bRxPWRatioTH		0x3
+#define		bRxPWRatioEn		0x4
+#define		bRxMFHold			0x3800
+#define		bRxPD_Delay_TH1		0x38
+#define		bRxPD_Delay_TH2		0x1c0
+#define		bRxPD_DC_COUNT_MAX	0x600
+/* #define bRxMF_Hold               0x3800 */
+#define		bRxPD_Delay_TH		0x8000
+#define		bRxProcess_Delay		0xf0000
+#define		bRxSearchrange_GI2_Early	0x700000
+#define		bRxFrame_Guard_Counter_L	0x3800000
+#define		bRxSGI_Guard_L		0xc000000
+#define		bRxSGI_Search_L		0x30000000
+#define		bRxSGI_TH			0xc0000000
+#define		bDFSCnt0			0xff
+#define		bDFSCnt1			0xff00
+#define		bDFSFlag			0xf0000
+#define		bMFWeightSum		0x300000
+#define		bMinIdxTH			0x7f000000
+#define		bDAFormat			0x40000
+#define		bTxChEmuEnable		0x01000000
+#define		bTRSWIsolation_A		0x7f
+#define		bTRSWIsolation_B		0x7f00
+#define		bTRSWIsolation_C		0x7f0000
+#define		bTRSWIsolation_D		0x7f000000
+#define		bExtLNAGain		0x7c00
+
+/* 6. PageE(0xE00) */
+#define		bSTBCEn                  			0x4	/* Useless */
+#define		bAntennaMapping		0x10
+#define		bNss			0x20
+#define		bCFOAntSumD		0x200
+#define		bPHYCounterReset		0x8000000
+#define		bCFOReportGet		0x4000000
+#define		bOFDMContinueTx		0x10000000
+#define		bOFDMSingleCarrier		0x20000000
+#define		bOFDMSingleTone		0x40000000
+/* #define bRxPath1                 0x01 */
+/* #define bRxPath2                 0x02 */
+/* #define bRxPath3                 0x04 */
+/* #define bRxPath4                 0x08 */
+/* #define bTxPath1                 0x10 */
+/* #define bTxPath2                 0x20 */
+#define		bHTDetect			0x100
+#define		bCFOEn			0x10000
+#define		bCFOValue			0xfff00000
+#define		bSigTone_Re			0x3f
+#define		bSigTone_Im			0x7f00
+#define		bCounter_CCA		0xffff
+#define		bCounter_ParityFail		0xffff0000
+#define		bCounter_RateIllegal		0xffff
+#define		bCounter_CRC8Fail		0xffff0000
+#define		bCounter_MCSNoSupport	0xffff
+#define		bCounter_FastSync		0xffff
+#define		bShortCFO			0xfff
+#define		bShortCFOTLength         		12   /* total */
+#define		bShortCFOFLength         		11   /* fraction */
+#define		bLongCFO			0x7ff
+#define		bLongCFOTLength		11
+#define		bLongCFOFLength		11
+#define		bTailCFO			0x1fff
+#define		bTailCFOTLength		13
+#define		bTailCFOFLength		12
+#define		bmax_en_pwdB		0xffff
+#define		bCC_power_dB		0xffff0000
+#define		bnoise_pwdB		0xffff
+#define		bPowerMeasTLength	10
+#define		bPowerMeasFLength	3
+#define		bRx_HT_BW		0x1
+#define		bRxSC			0x6
+#define		bRx_HT			0x8
+#define		bNB_intf_det_on		0x1
+#define		bIntf_win_len_cfg		0x30
+#define		bNB_Intf_TH_cfg		0x1c0
+#define		bRFGain			0x3f
+#define		bTableSel			0x40
+#define		bTRSW			0x80
+#define		bRxSNR_A			0xff
+#define		bRxSNR_B			0xff00
+#define		bRxSNR_C			0xff0000
+#define		bRxSNR_D			0xff000000
+#define		bSNREVMTLength		8
+#define		bSNREVMFLength		1
+#define		bCSI1st			0xff
+#define		bCSI2nd			0xff00
+#define		bRxEVM1st			0xff0000
+#define		bRxEVM2nd		0xff000000
+#define		bSIGEVM			0xff
+#define		bPWDB			0xff00
+#define		bSGIEN			0x10000
+
+#define		bSFactorQAM1             		0xf	/* Useless */
+#define		bSFactorQAM2		0xf0
+#define		bSFactorQAM3		0xf00
+#define		bSFactorQAM4		0xf000
+#define		bSFactorQAM5		0xf0000
+#define		bSFactorQAM6		0xf0000
+#define		bSFactorQAM7		0xf00000
+#define		bSFactorQAM8		0xf000000
+#define		bSFactorQAM9		0xf0000000
+#define		bCSIScheme			0x100000
+
+#define		bNoiseLvlTopSet          		0x3	/* Useless */
+#define		bChSmooth			0x4
+#define		bChSmoothCfg1		0x38
+#define		bChSmoothCfg2		0x1c0
+#define		bChSmoothCfg3		0xe00
+#define		bChSmoothCfg4		0x7000
+#define		bMRCMode		0x800000
+#define		bTHEVMCfg			0x7000000
+
+#define		bLoopFitType             			0x1	/* Useless */
+#define		bUpdCFO			0x40
+#define		bUpdCFOOffData		0x80
+#define		bAdvUpdCFO		0x100
+#define		bAdvTimeCtrl		0x800
+#define		bUpdClko			0x1000
+#define		bFC				0x6000
+#define		bTrackingMode		0x8000
+#define		bPhCmpEnable		0x10000
+#define		bUpdClkoLTF			0x20000
+#define		bComChCFO		0x40000
+#define		bCSIEstiMode		0x80000
+#define		bAdvUpdEqz		0x100000
+#define		bUChCfg			0x7000000
+#define		bUpdEqz			0x8000000
+
+/* Rx Pseduo noise */
+#define		bRxPesudoNoiseOn         		0x20000000	/* Useless */
+#define		bRxPesudoNoise_A		0xff
+#define		bRxPesudoNoise_B		0xff00
+#define		bRxPesudoNoise_C		0xff0000
+#define		bRxPesudoNoise_D		0xff000000
+#define		bPesudoNoiseState_A	0xffff
+#define		bPesudoNoiseState_B	0xffff0000
+#define		bPesudoNoiseState_C		0xffff
+#define		bPesudoNoiseState_D	0xffff0000
+
+/* 7. RF Register
+ * Zebra1 */
+#define		bZebra1_HSSIEnable        		0x8		/* Useless */
+#define		bZebra1_TRxControl		0xc00
+#define		bZebra1_TRxGainSetting	0x07f
+#define		bZebra1_RxCorner		0xc00
+#define		bZebra1_TxChargePump	0x38
+#define		bZebra1_RxChargePump	0x7
+#define		bZebra1_ChannelNum	0xf80
+#define		bZebra1_TxLPFBW		0x400
+#define		bZebra1_RxLPFBW		0x600
+
+/* Zebra4 */
+#define		bRTL8256RegModeCtrl1      	0x100	/* Useless */
+#define		bRTL8256RegModeCtrl0	0x40
+#define		bRTL8256_TxLPFBW	0x18
+#define		bRTL8256_RxLPFBW	0x600
+
+/* RTL8258 */
+#define		bRTL8258_TxLPFBW          	0xc	/* Useless */
+#define		bRTL8258_RxLPFBW	0xc00
+#define		bRTL8258_RSSILPFBW	0xc0
+
+
+/*
+ * Other Definition
+ *   */
+
+/* byte endable for sb_write */
+#define		bByte0                    			0x1	/* Useless */
+#define		bByte1			0x2
+#define		bByte2			0x4
+#define		bByte3			0x8
+#define		bWord0			0x3
+#define		bWord1			0xc
+#define		bDWord			0xf
+
+/* for PutRegsetting & GetRegSetting BitMask */
+#define		bMaskByte0                		0xff	/* Reg 0xc50 rOFDM0_XAAGCCore~0xC6f */
+#define		bMaskByte1		0xff00
+#define		bMaskByte2		0xff0000
+#define		bMaskByte3		0xff000000
+#define		bMaskHWord		0xffff0000
+#define		bMaskLWord		0x0000ffff
+#define		bMaskDWord		0xffffffff
+#define		bMaskH3Bytes				0xffffff00
+#define		bMask12Bits				0xfff
+#define		bMaskH4Bits				0xf0000000
+#define		bMaskOFDM_D			0xffc00000
+#define		bMaskCCK				0x3f3f3f3f
+
+
+
+#define		bEnable                   0x1	/* Useless */
+#define		bDisable                  0x0
+
+#define		LeftAntenna               			0x0	/* Useless */
+#define		RightAntenna		0x1
+
+#define		tCheckTxStatus            		500   /* 500ms */ /* Useless */
+#define		tUpdateRxCounter          		100   /* 100ms */
+
+#define		rateCCK     				0	/* Useless */
+#define		rateOFDM				1
+#define		rateHT					2
+
+/* define Register-End */
+#define		bPMAC_End                 		0x1ff	/* Useless */
+#define		bFPGAPHY0_End		0x8ff
+#define		bFPGAPHY1_End		0x9ff
+#define		bCCKPHY0_End		0xaff
+#define		bOFDMPHY0_End		0xcff
+#define		bOFDMPHY1_End		0xdff
+
+/* define max debug item in each debug page
+ * #define bMaxItem_FPGA_PHY0        0x9
+ * #define bMaxItem_FPGA_PHY1        0x3
+ * #define bMaxItem_PHY_11B          0x16
+ * #define bMaxItem_OFDM_PHY0        0x29
+ * #define bMaxItem_OFDM_PHY1        0x0 */
+
+#define		bPMACControl              		0x0		/* Useless */
+#define		bWMACControl		0x1
+#define		bWNICControl		0x2
+
+#define		PathA                     			0x0	/* Useless */
+#define		PathB			0x1
+#define		PathC			0x2
+#define		PathD			0x3
+
+/*--------------------------Define Parameters-------------------------------*/
+
+
+#endif
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/include/Hal8188EPwrSeq.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/Hal8188EPwrSeq.h
--- linux-5.6.3/3rdparty/rtl8821ce/include/Hal8188EPwrSeq.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/Hal8188EPwrSeq.h	2020-04-10 16:35:06.844661375 +0300
@@ -0,0 +1,170 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+
+
+#ifndef __HAL8188EPWRSEQ_H__
+#define __HAL8188EPWRSEQ_H__
+
+#include "HalPwrSeqCmd.h"
+
+/*
+	Check document WM-20110607-Paul-RTL8188E_Power_Architecture-R02.vsd
+	There are 6 HW Power States:
+	0: POFF--Power Off
+	1: PDN--Power Down
+	2: CARDEMU--Card Emulation
+	3: ACT--Active Mode
+	4: LPS--Low Power State
+	5: SUS--Suspend
+
+	The transision from different states are defined below
+	TRANS_CARDEMU_TO_ACT
+	TRANS_ACT_TO_CARDEMU
+	TRANS_CARDEMU_TO_SUS
+	TRANS_SUS_TO_CARDEMU
+	TRANS_CARDEMU_TO_PDN
+	TRANS_ACT_TO_LPS
+	TRANS_LPS_TO_ACT
+
+	TRANS_END
+
+    PWR SEQ Version: rtl8188E_PwrSeq_V09.h
+*/
+#define	RTL8188E_TRANS_CARDEMU_TO_ACT_STEPS	10
+#define	RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS	10
+#define	RTL8188E_TRANS_CARDEMU_TO_SUS_STEPS	10
+#define	RTL8188E_TRANS_SUS_TO_CARDEMU_STEPS	10
+#define	RTL8188E_TRANS_CARDEMU_TO_PDN_STEPS	10
+#define	RTL8188E_TRANS_PDN_TO_CARDEMU_STEPS	10
+#define	RTL8188E_TRANS_ACT_TO_LPS_STEPS	15
+#define	RTL8188E_TRANS_LPS_TO_ACT_STEPS	15
+#define	RTL8188E_TRANS_END_STEPS	1
+
+
+#define RTL8188E_TRANS_CARDEMU_TO_ACT														\
+	/* format */																\
+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
+	{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT1, BIT1},/* wait till 0x04[17] = 1    power ready*/	\
+	{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0 | BIT1, 0}, /* 0x02[1:0] = 0	reset BB*/			\
+	{0x0026, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, BIT7}, /*0x24[23] = 2b'01 schmit trigger */	\
+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, 0}, /* 0x04[15] = 0 disable HWPDN (control by DRV)*/\
+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4 | BIT3, 0}, /*0x04[12:11] = 2b'00 disable WL suspend*/	\
+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0}, /*0x04[8] = 1 polling until return 0*/	\
+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT0, 0}, /*wait till 0x04[8] = 0*/	\
+	{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0}, /*LDO normal mode*/	\
+
+#define RTL8188E_TRANS_ACT_TO_CARDEMU													\
+	/* format */																\
+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
+	{0x001F, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0},/*0x1F[7:0] = 0 turn off RF*/	\
+	{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, BIT4}, /*LDO Sleep mode*/	\
+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1}, /*0x04[9] = 1 turn off MAC by HW state machine*/	\
+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT1, 0}, /*wait till 0x04[9] = 0 polling until return 0 to disable*/	\
+
+#define RTL8188E_TRANS_CARDEMU_TO_SUS													\
+	/* format */																\
+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT4, BIT3}, /*0x04[12:11] = 2b'01enable WL suspend*/	\
+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT4, BIT3 | BIT4}, /*0x04[12:11] = 2b'11enable WL suspend for PCIe*/	\
+	{0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, BIT7}, /*  0x04[31:30] = 2b'10 enable enable bandgap mbias in suspend */	\
+	{0x0041, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0}, /*Clear SIC_EN register 0x40[12] = 1'b0 */	\
+	{0xfe10, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, BIT4}, /*Set USB suspend enable local register  0xfe10[4]=1 */	\
+	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT0, BIT0}, /*Set SDIO suspend local register*/	\
+	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, 0}, /*wait power state to suspend*/
+
+#define RTL8188E_TRANS_SUS_TO_CARDEMU													\
+	/* format */																\
+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
+	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT0, 0}, /*Set SDIO suspend local register*/	\
+	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, BIT1}, /*wait power state to suspend*/\
+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT4, 0}, /*0x04[12:11] = 2b'01enable WL suspend*/
+
+#define RTL8188E_TRANS_CARDEMU_TO_CARDDIS													\
+	/* format */																\
+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
+	{0x0026, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, BIT7}, /*0x24[23] = 2b'01 schmit trigger */	\
+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT4, BIT3}, /*0x04[12:11] = 2b'01 enable WL suspend*/	\
+	{0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0}, /*  0x04[31:30] = 2b'10 enable enable bandgap mbias in suspend */	\
+	{0x0041, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0}, /*Clear SIC_EN register 0x40[12] = 1'b0 */	\
+	{0xfe10, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, BIT4}, /*Set USB suspend enable local register  0xfe10[4]=1 */	\
+	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT0, BIT0}, /*Set SDIO suspend local register*/	\
+	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, 0}, /*wait power state to suspend*/
+
+#define RTL8188E_TRANS_CARDDIS_TO_CARDEMU													\
+	/* format */																\
+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
+	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT0, 0}, /*Set SDIO suspend local register*/	\
+	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, BIT1}, /*wait power state to suspend*/\
+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT4, 0}, /*0x04[12:11] = 2b'01enable WL suspend*/
+
+#define RTL8188E_TRANS_CARDEMU_TO_PDN												\
+	/* format */																\
+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
+	{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0},/* 0x04[16] = 0*/\
+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, BIT7},/* 0x04[15] = 1*/
+
+#define RTL8188E_TRANS_PDN_TO_CARDEMU												\
+	/* format */																\
+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, 0},/* 0x04[15] = 0*/
+
+	/* This is used by driver for LPSRadioOff Procedure, not for FW LPS Step */
+#define RTL8188E_TRANS_ACT_TO_LPS														\
+	/* format */																\
+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
+	{0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x7F},/*Tx Pause*/	\
+	{0x05F8, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/	\
+	{0x05F9, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/	\
+	{0x05FA, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/	\
+	{0x05FB, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/	\
+	{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0},/*CCK and OFDM are disabled, and clock are gated*/	\
+	{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_US},/*Delay 1us*/	\
+	{0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x3F},/*Reset MAC TRX*/	\
+	{0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0},/*check if removed later*/	\
+	{0x0553, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT5, BIT5},/*Respond TxOK to scheduler*/	\
+
+
+#define RTL8188E_TRANS_LPS_TO_ACT															\
+	/* format */																\
+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
+	{0x0080, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, 0xFF, 0x84}, /*SDIO RPWM*/\
+	{0xFE58, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x84}, /*USB RPWM*/\
+	{0x0361, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x84}, /*PCIe RPWM*/\
+	{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_MS}, /*Delay*/\
+	{0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0}, /*.	0x08[4] = 0		 switch TSF to 40M*/\
+	{0x0109, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT7, 0}, /*Polling 0x109[7]=0  TSF in 40M*/\
+	{0x0029, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT6 | BIT7, 0}, /*.	0x29[7:6] = 2b'00	 enable BB clock*/\
+	{0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1}, /*.	0x101[1] = 1*/\
+	{0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF}, /*.	0x100[7:0] = 0xFF	 enable WMAC TRX*/\
+	{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1 | BIT0, BIT1 | BIT0}, /*.	0x02[1:0] = 2b'11	 enable BB macro*/\
+	{0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0}, /*.	0x522 = 0*/
+
+#define RTL8188E_TRANS_END															\
+	/* format */																\
+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
+	{0xFFFF, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, 0, PWR_CMD_END, 0, 0},
+
+
+	extern WLAN_PWR_CFG rtl8188E_power_on_flow[RTL8188E_TRANS_CARDEMU_TO_ACT_STEPS + RTL8188E_TRANS_END_STEPS];
+	extern WLAN_PWR_CFG rtl8188E_radio_off_flow[RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS + RTL8188E_TRANS_END_STEPS];
+	extern WLAN_PWR_CFG rtl8188E_card_disable_flow[RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS + RTL8188E_TRANS_CARDEMU_TO_PDN_STEPS + RTL8188E_TRANS_END_STEPS];
+	extern WLAN_PWR_CFG rtl8188E_card_enable_flow[RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS + RTL8188E_TRANS_CARDEMU_TO_PDN_STEPS + RTL8188E_TRANS_END_STEPS];
+	extern WLAN_PWR_CFG rtl8188E_suspend_flow[RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS + RTL8188E_TRANS_CARDEMU_TO_SUS_STEPS + RTL8188E_TRANS_END_STEPS];
+	extern WLAN_PWR_CFG rtl8188E_resume_flow[RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS + RTL8188E_TRANS_CARDEMU_TO_SUS_STEPS + RTL8188E_TRANS_END_STEPS];
+	extern WLAN_PWR_CFG rtl8188E_hwpdn_flow[RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS + RTL8188E_TRANS_CARDEMU_TO_PDN_STEPS + RTL8188E_TRANS_END_STEPS];
+	extern WLAN_PWR_CFG rtl8188E_enter_lps_flow[RTL8188E_TRANS_ACT_TO_LPS_STEPS + RTL8188E_TRANS_END_STEPS];
+	extern WLAN_PWR_CFG rtl8188E_leave_lps_flow[RTL8188E_TRANS_LPS_TO_ACT_STEPS + RTL8188E_TRANS_END_STEPS];
+
+#endif /* __HAL8188EPWRSEQ_H__ */
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/include/Hal8188FPhyCfg.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/Hal8188FPhyCfg.h
--- linux-5.6.3/3rdparty/rtl8821ce/include/Hal8188FPhyCfg.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/Hal8188FPhyCfg.h	2020-04-10 16:35:06.844661375 +0300
@@ -0,0 +1,134 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#ifndef __INC_HAL8188FPHYCFG_H__
+#define __INC_HAL8188FPHYCFG_H__
+
+/*--------------------------Define Parameters-------------------------------*/
+#define LOOP_LIMIT				5
+#define MAX_STALL_TIME			50		/* us */
+#define AntennaDiversityValue	0x80	/* (Adapter->bSoftwareAntennaDiversity ? 0x00 : 0x80) */
+#define MAX_TXPWR_IDX_NMODE_92S	63
+#define Reset_Cnt_Limit			3
+
+#ifdef CONFIG_PCI_HCI
+	#define MAX_AGGR_NUM	0x0B
+#else
+	#define MAX_AGGR_NUM	0x07
+#endif /* CONFIG_PCI_HCI */
+
+
+/*--------------------------Define Parameters End-------------------------------*/
+
+
+/*------------------------------Define structure----------------------------*/
+
+/*------------------------------Define structure End----------------------------*/
+
+/*--------------------------Exported Function prototype---------------------*/
+u32
+PHY_QueryBBReg_8188F(
+	IN	PADAPTER	Adapter,
+	IN	u32		RegAddr,
+	IN	u32		BitMask
+);
+
+VOID
+PHY_SetBBReg_8188F(
+	IN	PADAPTER	Adapter,
+	IN	u32		RegAddr,
+	IN	u32		BitMask,
+	IN	u32		Data
+);
+
+u32
+PHY_QueryRFReg_8188F(
+	IN	PADAPTER			Adapter,
+	IN	enum rf_path			eRFPath,
+	IN	u32				RegAddr,
+	IN	u32				BitMask
+);
+
+VOID
+PHY_SetRFReg_8188F(
+	IN	PADAPTER			Adapter,
+	IN	enum rf_path			eRFPath,
+	IN	u32				RegAddr,
+	IN	u32				BitMask,
+	IN	u32				Data
+);
+
+/* MAC/BB/RF HAL config */
+int PHY_BBConfig8188F(PADAPTER	Adapter);
+
+int PHY_RFConfig8188F(PADAPTER	Adapter);
+
+s32 PHY_MACConfig8188F(PADAPTER padapter);
+
+int
+PHY_ConfigRFWithParaFile_8188F(
+	IN	PADAPTER			Adapter,
+	IN	u8					*pFileName,
+	enum rf_path				eRFPath
+);
+
+VOID
+PHY_SetTxPowerIndex_8188F(
+	IN	PADAPTER			Adapter,
+	IN	u32					PowerIndex,
+	IN	enum rf_path			RFPath,
+	IN	u8					Rate
+);
+
+u8
+PHY_GetTxPowerIndex_8188F(
+	IN	PADAPTER			pAdapter,
+	IN	enum rf_path			RFPath,
+	IN	u8					Rate,
+	IN	u8		BandWidth,
+	IN	u8					Channel,
+	struct txpwr_idx_comp *tic
+);
+
+VOID
+PHY_GetTxPowerLevel8188F(
+	IN	PADAPTER		Adapter,
+	OUT s32				*powerlevel
+);
+
+VOID
+PHY_SetTxPowerLevel8188F(
+	IN	PADAPTER		Adapter,
+	IN	u8			channel
+);
+
+VOID
+PHY_SetSwChnlBWMode8188F(
+	IN	PADAPTER			Adapter,
+	IN	u8					channel,
+	IN	enum channel_width	Bandwidth,
+	IN	u8					Offset40,
+	IN	u8					Offset80
+);
+
+VOID phy_set_rf_path_switch_8188f(
+	IN	struct		dm_struct *phydm,
+	IN	bool		bMain
+);
+
+void BBTurnOnBlock_8188F(_adapter *adapter);
+
+/*--------------------------Exported Function prototype End---------------------*/
+
+#endif
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/include/Hal8188FPhyReg.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/Hal8188FPhyReg.h
--- linux-5.6.3/3rdparty/rtl8821ce/include/Hal8188FPhyReg.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/Hal8188FPhyReg.h	2020-04-10 16:35:06.844661375 +0300
@@ -0,0 +1,1165 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#ifndef __INC_HAL8188FPHYREG_H__
+#define __INC_HAL8188FPHYREG_H__
+
+/*--------------------------Define Parameters-------------------------------*/
+
+/* ************************************************************
+ * Regsiter offset definition
+ * ************************************************************ */
+
+/*
+ * BB-PHY register PMAC 0x100 PHY 0x800 - 0xEFF
+ * 1. PMAC duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF
+ * 2. 0x800/0x900/0xA00/0xC00/0xD00/0xE00
+ * 3. RF register 0x00-2E
+ * 4. Bit Mask for BB/RF register
+ * 5. Other defintion for BB/RF R/W
+ *   */
+
+
+/*
+ * 1. PMAC duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF
+ * 1. Page1(0x100)
+ *   */
+#define		rPMAC_Reset					0x100
+#define		rPMAC_TxStart					0x104
+#define		rPMAC_TxLegacySIG				0x108
+#define		rPMAC_TxHTSIG1				0x10c
+#define		rPMAC_TxHTSIG2				0x110
+#define		rPMAC_PHYDebug				0x114
+#define		rPMAC_TxPacketNum				0x118
+#define		rPMAC_TxIdle					0x11c
+#define		rPMAC_TxMACHeader0			0x120
+#define		rPMAC_TxMACHeader1			0x124
+#define		rPMAC_TxMACHeader2			0x128
+#define		rPMAC_TxMACHeader3			0x12c
+#define		rPMAC_TxMACHeader4			0x130
+#define		rPMAC_TxMACHeader5			0x134
+#define		rPMAC_TxDataType				0x138
+#define		rPMAC_TxRandomSeed			0x13c
+#define		rPMAC_CCKPLCPPreamble			0x140
+#define		rPMAC_CCKPLCPHeader			0x144
+#define		rPMAC_CCKCRC16				0x148
+#define		rPMAC_OFDMRxCRC32OK			0x170
+#define		rPMAC_OFDMRxCRC32Er			0x174
+#define		rPMAC_OFDMRxParityEr			0x178
+#define		rPMAC_OFDMRxCRC8Er			0x17c
+#define		rPMAC_CCKCRxRC16Er			0x180
+#define		rPMAC_CCKCRxRC32Er			0x184
+#define		rPMAC_CCKCRxRC32OK			0x188
+#define		rPMAC_TxStatus					0x18c
+
+/*
+ * 2. Page2(0x200)
+ *
+ * The following two definition are only used for USB interface. */
+#define		RF_BB_CMD_ADDR				0x02c0	/* RF/BB read/write command address. */
+#define		RF_BB_CMD_DATA				0x02c4	/* RF/BB read/write command data. */
+
+/*
+ * 3. Page8(0x800)
+ *   */
+#define		rFPGA0_RFMOD				0x800	/* RF mode & CCK TxSC */ /* RF BW Setting?? */
+
+#define		rFPGA0_TxInfo				0x804	/* Status report?? */
+#define		rFPGA0_PSDFunction			0x808
+
+#define		rFPGA0_TxGainStage			0x80c	/* Set TX PWR init gain? */
+
+#define		rFPGA0_RFTiming1			0x810	/* Useless now */
+#define		rFPGA0_RFTiming2			0x814
+
+#define		rFPGA0_XA_HSSIParameter1		0x820	/* RF 3 wire register */
+#define		rFPGA0_XA_HSSIParameter2		0x824
+#define		rFPGA0_XB_HSSIParameter1		0x828
+#define		rFPGA0_XB_HSSIParameter2		0x82c
+#define		rTxAGC_B_Rate18_06				0x830
+#define		rTxAGC_B_Rate54_24				0x834
+#define		rTxAGC_B_CCK1_55_Mcs32		0x838
+#define		rTxAGC_B_Mcs03_Mcs00			0x83c
+
+#define		rTxAGC_B_Mcs07_Mcs04			0x848
+#define		rTxAGC_B_Mcs11_Mcs08			0x84c
+
+#define		rFPGA0_XA_LSSIParameter		0x840
+#define		rFPGA0_XB_LSSIParameter		0x844
+
+#define		rFPGA0_RFWakeUpParameter		0x850	/* Useless now */
+#define		rFPGA0_RFSleepUpParameter		0x854
+
+#define		rFPGA0_XAB_SwitchControl		0x858	/* RF Channel switch */
+#define		rFPGA0_XCD_SwitchControl		0x85c
+
+#define		rFPGA0_XA_RFInterfaceOE		0x860	/* RF Channel switch */
+#define		rFPGA0_XB_RFInterfaceOE		0x864
+
+#define		rTxAGC_B_Mcs15_Mcs12			0x868
+#define		rTxAGC_B_CCK11_A_CCK2_11		0x86c
+
+#define		rFPGA0_XAB_RFInterfaceSW		0x870	/* RF Interface Software Control */
+#define		rFPGA0_XCD_RFInterfaceSW		0x874
+
+#define		rFPGA0_XAB_RFParameter		0x878	/* RF Parameter */
+#define		rFPGA0_XCD_RFParameter		0x87c
+
+#define		rFPGA0_AnalogParameter1		0x880	/* Crystal cap setting RF-R/W protection for parameter4?? */
+#define		rFPGA0_AnalogParameter2		0x884
+#define		rFPGA0_AnalogParameter3		0x888	/* Useless now */
+#define		rFPGA0_AnalogParameter4		0x88c
+
+#define		rFPGA0_XA_LSSIReadBack		0x8a0	/* Tranceiver LSSI Readback */
+#define		rFPGA0_XB_LSSIReadBack		0x8a4
+#define		rFPGA0_XC_LSSIReadBack		0x8a8
+#define		rFPGA0_XD_LSSIReadBack		0x8ac
+
+#define		rFPGA0_PSDReport				0x8b4	/* Useless now */
+#define		TransceiverA_HSPI_Readback	0x8b8	/* Transceiver A HSPI Readback */
+#define		TransceiverB_HSPI_Readback	0x8bc	/* Transceiver B HSPI Readback */
+#define		rFPGA0_XAB_RFInterfaceRB		0x8e0	/* Useless now */ /* RF Interface Readback Value */
+#define		rFPGA0_XCD_RFInterfaceRB		0x8e4	/* Useless now */
+
+/*
+ * 4. Page9(0x900)
+ *   */
+#define		rFPGA1_RFMOD				0x900	/* RF mode & OFDM TxSC */ /* RF BW Setting?? */
+
+#define		rFPGA1_TxBlock				0x904	/* Useless now */
+#define		rFPGA1_DebugSelect			0x908	/* Useless now */
+#define		rFPGA1_TxInfo				0x90c	/* Useless now */ /* Status report?? */
+#define	rS0S1_PathSwitch			0x948
+
+/*
+ * 5. PageA(0xA00)
+ *
+ * Set Control channel to upper or lower. These settings are required only for 40MHz */
+#define		rCCK0_System				0xa00
+
+#define		rCCK0_AFESetting			0xa04	/* Disable init gain now */ /* Select RX path by RSSI */
+#define		rCCK0_CCA					0xa08	/* Disable init gain now */ /* Init gain */
+
+#define		rCCK0_RxAGC1				0xa0c	/* AGC default value, saturation level  */ /* Antenna Diversity, RX AGC, LNA Threshold, RX LNA Threshold useless now. Not the same as 90 series */
+#define		rCCK0_RxAGC2				0xa10	/* AGC & DAGC */
+
+#define		rCCK0_RxHP					0xa14
+
+#define		rCCK0_DSPParameter1		0xa18	/* Timing recovery & Channel estimation threshold */
+#define		rCCK0_DSPParameter2		0xa1c	/* SQ threshold */
+
+#define		rCCK0_TxFilter1				0xa20
+#define		rCCK0_TxFilter2				0xa24
+#define		rCCK0_DebugPort			0xa28	/* debug port and Tx filter3 */
+#define		rCCK0_FalseAlarmReport		0xa2c	/* 0xa2d	useless now 0xa30-a4f channel report */
+#define		rCCK0_TRSSIReport		0xa50
+#define		rCCK0_RxReport            		0xa54  /* 0xa57 */
+#define		rCCK0_FACounterLower      	0xa5c  /* 0xa5b */
+#define		rCCK0_FACounterUpper      	0xa58  /* 0xa5c
+ *
+ * PageB(0xB00)
+ *   */
+#define		rPdp_AntA				0xb00
+#define		rPdp_AntA_4				0xb04
+#define		rConfig_Pmpd_AntA			0xb28
+#define		rConfig_AntA				0xb68
+#define		rConfig_AntB				0xb6c
+#define		rPdp_AntB					0xb70
+#define		rPdp_AntB_4				0xb74
+#define		rConfig_Pmpd_AntB			0xb98
+#define		rAPK						0xbd8
+
+/*
+ * 6. PageC(0xC00)
+ *   */
+#define		rOFDM0_LSTF				0xc00
+
+#define		rOFDM0_TRxPathEnable		0xc04
+#define		rOFDM0_TRMuxPar			0xc08
+#define		rOFDM0_TRSWIsolation		0xc0c
+
+#define		rOFDM0_XARxAFE			0xc10  /* RxIQ DC offset, Rx digital filter, DC notch filter */
+#define		rOFDM0_XARxIQImbalance    	0xc14  /* RxIQ imblance matrix */
+#define		rOFDM0_XBRxAFE		0xc18
+#define		rOFDM0_XBRxIQImbalance	0xc1c
+#define		rOFDM0_XCRxAFE		0xc20
+#define		rOFDM0_XCRxIQImbalance	0xc24
+#define		rOFDM0_XDRxAFE		0xc28
+#define		rOFDM0_XDRxIQImbalance	0xc2c
+
+#define		rOFDM0_RxDetector1			0xc30  /* PD, BW & SBD	 */ /* DM tune init gain */
+#define		rOFDM0_RxDetector2			0xc34  /* SBD & Fame Sync. */
+#define		rOFDM0_RxDetector3			0xc38  /* Frame Sync. */
+#define		rOFDM0_RxDetector4			0xc3c  /* PD, SBD, Frame Sync & Short-GI */
+
+#define		rOFDM0_RxDSP				0xc40  /* Rx Sync Path */
+#define		rOFDM0_CFOandDAGC		0xc44  /* CFO & DAGC */
+#define		rOFDM0_CCADropThreshold	0xc48 /* CCA Drop threshold */
+#define		rOFDM0_ECCAThreshold		0xc4c /* energy CCA */
+
+#define		rOFDM0_XAAGCCore1			0xc50	/* DIG */
+#define		rOFDM0_XAAGCCore2			0xc54
+#define		rOFDM0_XBAGCCore1			0xc58
+#define		rOFDM0_XBAGCCore2			0xc5c
+#define		rOFDM0_XCAGCCore1			0xc60
+#define		rOFDM0_XCAGCCore2			0xc64
+#define		rOFDM0_XDAGCCore1			0xc68
+#define		rOFDM0_XDAGCCore2			0xc6c
+
+#define		rOFDM0_AGCParameter1			0xc70
+#define		rOFDM0_AGCParameter2			0xc74
+#define		rOFDM0_AGCRSSITable			0xc78
+#define		rOFDM0_HTSTFAGC				0xc7c
+
+#define		rOFDM0_XATxIQImbalance		0xc80	/* TX PWR TRACK and DIG */
+#define		rOFDM0_XATxAFE				0xc84
+#define		rOFDM0_XBTxIQImbalance		0xc88
+#define		rOFDM0_XBTxAFE				0xc8c
+#define		rOFDM0_XCTxIQImbalance		0xc90
+#define		rOFDM0_XCTxAFE			0xc94
+#define		rOFDM0_XDTxIQImbalance		0xc98
+#define		rOFDM0_XDTxAFE				0xc9c
+
+#define		rOFDM0_RxIQExtAnta			0xca0
+#define		rOFDM0_TxCoeff1				0xca4
+#define		rOFDM0_TxCoeff2				0xca8
+#define		rOFDM0_TxCoeff3				0xcac
+#define		rOFDM0_TxCoeff4				0xcb0
+#define		rOFDM0_TxCoeff5				0xcb4
+#define		rOFDM0_TxCoeff6				0xcb8
+#define		rOFDM0_RxHPParameter			0xce0
+#define		rOFDM0_TxPseudoNoiseWgt		0xce4
+#define		rOFDM0_FrameSync				0xcf0
+#define		rOFDM0_DFSReport				0xcf4
+
+/*
+ * 7. PageD(0xD00)
+ *   */
+#define		rOFDM1_LSTF					0xd00
+#define		rOFDM1_TRxPathEnable			0xd04
+
+#define		rOFDM1_CFO						0xd08	/* No setting now */
+#define		rOFDM1_CSI1					0xd10
+#define		rOFDM1_SBD						0xd14
+#define		rOFDM1_CSI2					0xd18
+#define		rOFDM1_CFOTracking			0xd2c
+#define		rOFDM1_TRxMesaure1			0xd34
+#define		rOFDM1_IntfDet					0xd3c
+#define		rOFDM1_PseudoNoiseStateAB		0xd50
+#define		rOFDM1_PseudoNoiseStateCD		0xd54
+#define		rOFDM1_RxPseudoNoiseWgt		0xd58
+
+#define		rOFDM_PHYCounter1				0xda0  /* cca, parity fail */
+#define		rOFDM_PHYCounter2				0xda4  /* rate illegal, crc8 fail */
+#define		rOFDM_PHYCounter3				0xda8  /* MCS not support */
+
+#define		rOFDM_ShortCFOAB				0xdac	/* No setting now */
+#define		rOFDM_ShortCFOCD				0xdb0
+#define		rOFDM_LongCFOAB				0xdb4
+#define		rOFDM_LongCFOCD				0xdb8
+#define		rOFDM_TailCFOAB				0xdbc
+#define		rOFDM_TailCFOCD				0xdc0
+#define		rOFDM_PWMeasure1		0xdc4
+#define		rOFDM_PWMeasure2		0xdc8
+#define		rOFDM_BWReport				0xdcc
+#define		rOFDM_AGCReport				0xdd0
+#define		rOFDM_RxSNR					0xdd4
+#define		rOFDM_RxEVMCSI				0xdd8
+#define		rOFDM_SIGReport				0xddc
+
+
+/*
+ * 8. PageE(0xE00)
+ *   */
+#define		rTxAGC_A_Rate18_06			0xe00
+#define		rTxAGC_A_Rate54_24			0xe04
+#define		rTxAGC_A_CCK1_Mcs32			0xe08
+#define		rTxAGC_A_Mcs03_Mcs00			0xe10
+#define		rTxAGC_A_Mcs07_Mcs04			0xe14
+#define		rTxAGC_A_Mcs11_Mcs08			0xe18
+#define		rTxAGC_A_Mcs15_Mcs12			0xe1c
+
+#define		rFPGA0_IQK					0xe28
+#define		rTx_IQK_Tone_A				0xe30
+#define		rRx_IQK_Tone_A				0xe34
+#define		rTx_IQK_PI_A					0xe38
+#define		rRx_IQK_PI_A					0xe3c
+
+#define		rTx_IQK						0xe40
+#define		rRx_IQK						0xe44
+#define		rIQK_AGC_Pts					0xe48
+#define		rIQK_AGC_Rsp					0xe4c
+#define		rTx_IQK_Tone_B				0xe50
+#define		rRx_IQK_Tone_B				0xe54
+#define		rTx_IQK_PI_B					0xe58
+#define		rRx_IQK_PI_B					0xe5c
+#define		rIQK_AGC_Cont				0xe60
+
+#define		rBlue_Tooth					0xe6c
+#define		rRx_Wait_CCA					0xe70
+#define		rTx_CCK_RFON					0xe74
+#define		rTx_CCK_BBON				0xe78
+#define		rTx_OFDM_RFON				0xe7c
+#define		rTx_OFDM_BBON				0xe80
+#define		rTx_To_Rx					0xe84
+#define		rTx_To_Tx					0xe88
+#define		rRx_CCK						0xe8c
+
+#define		rTx_Power_Before_IQK_A		0xe94
+#define		rTx_Power_After_IQK_A			0xe9c
+
+#define		rRx_Power_Before_IQK_A		0xea0
+#define		rRx_Power_Before_IQK_A_2		0xea4
+#define		rRx_Power_After_IQK_A			0xea8
+#define		rRx_Power_After_IQK_A_2		0xeac
+
+#define		rTx_Power_Before_IQK_B		0xeb4
+#define		rTx_Power_After_IQK_B			0xebc
+
+#define		rRx_Power_Before_IQK_B		0xec0
+#define		rRx_Power_Before_IQK_B_2		0xec4
+#define		rRx_Power_After_IQK_B			0xec8
+#define		rRx_Power_After_IQK_B_2		0xecc
+
+#define		rRx_OFDM					0xed0
+#define		rRx_Wait_RIFS				0xed4
+#define		rRx_TO_Rx					0xed8
+#define		rStandby						0xedc
+#define		rSleep						0xee0
+#define		rPMPD_ANAEN				0xeec
+
+/*
+ * 7. RF Register 0x00-0x2E (RF 8256)
+ * RF-0222D 0x00-3F
+ *
+ * Zebra1 */
+#define		rZebra1_HSSIEnable				0x0	/* Useless now */
+#define		rZebra1_TRxEnable1				0x1
+#define		rZebra1_TRxEnable2				0x2
+#define		rZebra1_AGC					0x4
+#define		rZebra1_ChargePump			0x5
+#define		rZebra1_Channel				0x7	/* RF channel switch */
+
+/* #endif */
+#define		rZebra1_TxGain					0x8	/* Useless now */
+#define		rZebra1_TxLPF					0x9
+#define		rZebra1_RxLPF					0xb
+#define		rZebra1_RxHPFCorner			0xc
+
+/* Zebra4 */
+#define		rGlobalCtrl						0	/* Useless now */
+#define		rRTL8256_TxLPF					19
+#define		rRTL8256_RxLPF					11
+
+/* RTL8258 */
+#define		rRTL8258_TxLPF					0x11	/* Useless now */
+#define		rRTL8258_RxLPF					0x13
+#define		rRTL8258_RSSILPF				0xa
+
+/*
+ * RL6052 Register definition
+ *   */
+#define		RF_AC						0x00	/*  */
+
+#define		RF_IQADJ_G1				0x01	/*  */
+#define		RF_IQADJ_G2				0x02	/*  */
+#define		RF_BS_PA_APSET_G1_G4		0x03
+#define		RF_BS_PA_APSET_G5_G8		0x04
+#define		RF_POW_TRSW				0x05	/*  */
+
+#define		RF_GAIN_RX					0x06	/*  */
+#define		RF_GAIN_TX					0x07	/*  */
+
+#define		RF_TXM_IDAC				0x08	/*  */
+#define		RF_IPA_G					0x09	/*  */
+#define		RF_TXBIAS_G				0x0A
+#define		RF_TXPA_AG					0x0B
+#define		RF_IPA_A					0x0C	/*  */
+#define		RF_TXBIAS_A				0x0D
+#define		RF_BS_PA_APSET_G9_G11	0x0E
+#define		RF_BS_IQGEN				0x0F	/*  */
+
+#define		RF_MODE1					0x10	/*  */
+#define		RF_MODE2					0x11	/*  */
+
+#define		RF_RX_AGC_HP				0x12	/*  */
+#define		RF_TX_AGC					0x13	/*  */
+#define		RF_BIAS						0x14	/*  */
+#define		RF_IPA						0x15	/*  */
+#define		RF_TXBIAS					0x16
+#define		RF_POW_ABILITY			0x17	/*  */
+#define		RF_MODE_AG				0x18	/*  */
+#define		rRfChannel					0x18	/* RF channel and BW switch */
+#define		RF_CHNLBW					0x18	/* RF channel and BW switch */
+#define		RF_TOP						0x19	/*  */
+
+#define		RF_RX_G1					0x1A	/*  */
+#define		RF_RX_G2					0x1B	/*  */
+
+#define		RF_RX_BB2					0x1C	/*  */
+#define		RF_RX_BB1					0x1D	/*  */
+
+#define		RF_RCK1					0x1E	/*  */
+#define		RF_RCK2					0x1F	/*  */
+
+#define		RF_TX_G1					0x20	/*  */
+#define		RF_TX_G2					0x21	/*  */
+#define		RF_TX_G3					0x22	/*  */
+
+#define		RF_TX_BB1					0x23	/*  */
+
+#define		RF_T_METER					0x24	/*  */
+
+#define		RF_SYN_G1					0x25	/* RF TX Power control */
+#define		RF_SYN_G2					0x26	/* RF TX Power control */
+#define		RF_SYN_G3					0x27	/* RF TX Power control */
+#define		RF_SYN_G4					0x28	/* RF TX Power control */
+#define		RF_SYN_G5					0x29	/* RF TX Power control */
+#define		RF_SYN_G6					0x2A	/* RF TX Power control */
+#define		RF_SYN_G7					0x2B	/* RF TX Power control */
+#define		RF_SYN_G8					0x2C	/* RF TX Power control */
+
+#define		RF_RCK_OS					0x30	/* RF TX PA control */
+
+#define		RF_TXPA_G1					0x31	/* RF TX PA control */
+#define		RF_TXPA_G2					0x32	/* RF TX PA control */
+#define		RF_TXPA_G3					0x33	/* RF TX PA control */
+#define	RF_TX_BIAS_A				0x35
+#define	RF_TX_BIAS_D				0x36
+#define	RF_LOBF_9					0x38
+#define 	RF_RXRF_A3					0x3C	/*	 */
+#define	RF_TRSW					0x3F
+
+#define	RF_TXRF_A2					0x41
+#define	RF_TXPA_G4					0x46
+#define	RF_TXPA_A4					0x4B
+#define	RF_0x52					0x52
+#define		RF_RXG_MIX_SWBW				0x87
+#define		RF_DBG_LP_RX2				0xDF
+#define	RF_WE_LUT					0xEF
+#define	RF_S0S1					0xB0
+
+#define RF_TX_GAIN_OFFSET_8188F(_val) (abs((_val)) | (((_val) > 0) ? BIT5 : 0))
+
+/*
+ * Bit Mask
+ *
+ * 1. Page1(0x100) */
+#define		bBBResetB						0x100	/* Useless now? */
+#define		bGlobalResetB					0x200
+#define		bOFDMTxStart					0x4
+#define		bCCKTxStart						0x8
+#define		bCRC32Debug					0x100
+#define		bPMACLoopback					0x10
+#define		bTxLSIG							0xffffff
+#define		bOFDMTxRate					0xf
+#define		bOFDMTxReserved				0x10
+#define		bOFDMTxLength					0x1ffe0
+#define		bOFDMTxParity					0x20000
+#define		bTxHTSIG1						0xffffff
+#define		bTxHTMCSRate					0x7f
+#define		bTxHTBW						0x80
+#define		bTxHTLength					0xffff00
+#define		bTxHTSIG2						0xffffff
+#define		bTxHTSmoothing					0x1
+#define		bTxHTSounding					0x2
+#define		bTxHTReserved					0x4
+#define		bTxHTAggreation				0x8
+#define		bTxHTSTBC						0x30
+#define		bTxHTAdvanceCoding			0x40
+#define		bTxHTShortGI					0x80
+#define		bTxHTNumberHT_LTF			0x300
+#define		bTxHTCRC8						0x3fc00
+#define		bCounterReset					0x10000
+#define		bNumOfOFDMTx					0xffff
+#define		bNumOfCCKTx					0xffff0000
+#define		bTxIdleInterval					0xffff
+#define		bOFDMService					0xffff0000
+#define		bTxMACHeader					0xffffffff
+#define		bTxDataInit						0xff
+#define		bTxHTMode						0x100
+#define		bTxDataType					0x30000
+#define		bTxRandomSeed					0xffffffff
+#define		bCCKTxPreamble					0x1
+#define		bCCKTxSFD						0xffff0000
+#define		bCCKTxSIG						0xff
+#define		bCCKTxService					0xff00
+#define		bCCKLengthExt					0x8000
+#define		bCCKTxLength					0xffff0000
+#define		bCCKTxCRC16					0xffff
+#define		bCCKTxStatus					0x1
+#define		bOFDMTxStatus					0x2
+
+#define		IS_BB_REG_OFFSET_92S(_Offset)		((_Offset >= 0x800) && (_Offset <= 0xfff))
+
+/* 2. Page8(0x800) */
+#define		bRFMOD							0x1	/* Reg 0x800 rFPGA0_RFMOD */
+#define		bJapanMode						0x2
+#define		bCCKTxSC						0x30
+#define		bCCKEn							0x1000000
+#define		bOFDMEn						0x2000000
+
+#define		bOFDMRxADCPhase           		0x10000	/* Useless now */
+#define		bOFDMTxDACPhase		0x40000
+#define		bXATxAGC			0x3f
+
+#define		bAntennaSelect		0x0300
+
+#define		bXBTxAGC                  			0xf00	/* Reg 80c rFPGA0_TxGainStage */
+#define		bXCTxAGC			0xf000
+#define		bXDTxAGC			0xf0000
+
+#define		bPAStart                  			0xf0000000	/* Useless now */
+#define		bTRStart			0x00f00000
+#define		bRFStart			0x0000f000
+#define		bBBStart			0x000000f0
+#define		bBBCCKStart		0x0000000f
+#define		bPAEnd                    			0xf          /* Reg0x814 */
+#define		bTREnd			0x0f000000
+#define		bRFEnd			0x000f0000
+#define		bCCAMask                  			0x000000f0   /* T2R */
+#define		bR2RCCAMask		0x00000f00
+#define		bHSSI_R2TDelay		0xf8000000
+#define		bHSSI_T2RDelay		0xf80000
+#define		bContTxHSSI               		0x400     /* chane gain at continue Tx */
+#define		bIGFromCCK		0x200
+#define		bAGCAddress		0x3f
+#define		bRxHPTx			0x7000
+#define		bRxHPT2R			0x38000
+#define		bRxHPCCKIni		0xc0000
+#define		bAGCTxCode		0xc00000
+#define		bAGCRxCode		0x300000
+
+#define		b3WireDataLength          		0x800	/* Reg 0x820~84f rFPGA0_XA_HSSIParameter1 */
+#define		b3WireAddressLength		0x400
+
+#define		b3WireRFPowerDown         		0x1	/* Useless now
+ * #define bHWSISelect		0x8 */
+#define		b5GPAPEPolarity		0x40000000
+#define		b2GPAPEPolarity		0x80000000
+#define		bRFSW_TxDefaultAnt		0x3
+#define		bRFSW_TxOptionAnt		0x30
+#define		bRFSW_RxDefaultAnt		0x300
+#define		bRFSW_RxOptionAnt		0x3000
+#define		bRFSI_3WireData		0x1
+#define		bRFSI_3WireClock		0x2
+#define		bRFSI_3WireLoad		0x4
+#define		bRFSI_3WireRW		0x8
+#define		bRFSI_3Wire			0xf
+
+#define		bRFSI_RFENV               		0x10	/* Reg 0x870 rFPGA0_XAB_RFInterfaceSW */
+
+#define		bRFSI_TRSW                		0x20	/* Useless now */
+#define		bRFSI_TRSWB		0x40
+#define		bRFSI_ANTSW		0x100
+#define		bRFSI_ANTSWB		0x200
+#define		bRFSI_PAPE			0x400
+#define		bRFSI_PAPE5G		0x800
+#define		bBandSelect			0x1
+#define		bHTSIG2_GI			0x80
+#define		bHTSIG2_Smoothing		0x01
+#define		bHTSIG2_Sounding		0x02
+#define		bHTSIG2_Aggreaton		0x08
+#define		bHTSIG2_STBC		0x30
+#define		bHTSIG2_AdvCoding		0x40
+#define		bHTSIG2_NumOfHTLTF	0x300
+#define		bHTSIG2_CRC8		0x3fc
+#define		bHTSIG1_MCS		0x7f
+#define		bHTSIG1_BandWidth		0x80
+#define		bHTSIG1_HTLength		0xffff
+#define		bLSIG_Rate			0xf
+#define		bLSIG_Reserved		0x10
+#define		bLSIG_Length		0x1fffe
+#define		bLSIG_Parity			0x20
+#define		bCCKRxPhase		0x4
+
+#define		bLSSIReadAddress          		0x7f800000   /* T65 RF */
+
+#define		bLSSIReadEdge             		0x80000000   /* LSSI "Read" edge signal */
+
+#define		bLSSIReadBackData         		0xfffff		/* T65 RF */
+
+#define		bLSSIReadOKFlag           		0x1000	/* Useless now */
+#define		bCCKSampleRate            		0x8       /* 0: 44MHz, 1:88MHz      		 */
+#define		bRegulator0Standby		0x1
+#define		bRegulatorPLLStandby		0x2
+#define		bRegulator1Standby		0x4
+#define		bPLLPowerUp		0x8
+#define		bDPLLPowerUp		0x10
+#define		bDA10PowerUp		0x20
+#define		bAD7PowerUp		0x200
+#define		bDA6PowerUp		0x2000
+#define		bXtalPowerUp		0x4000
+#define		b40MDClkPowerUP		0x8000
+#define		bDA6DebugMode		0x20000
+#define		bDA6Swing			0x380000
+
+#define		bADClkPhase               		0x4000000	/* Reg 0x880 rFPGA0_AnalogParameter1 20/40 CCK support switch 40/80 BB MHZ */
+
+#define		b80MClkDelay              		0x18000000	/* Useless */
+#define		bAFEWatchDogEnable		0x20000000
+
+#define		bXtalCap01                			0xc0000000	/* Reg 0x884 rFPGA0_AnalogParameter2 Crystal cap */
+#define		bXtalCap23			0x3
+#define		bXtalCap92x					0x0f000000
+#define		bXtalCap			0x0f000000
+
+#define		bIntDifClkEnable          		0x400	/* Useless */
+#define		bExtSigClkEnable		0x800
+#define		bBandgapMbiasPowerUp	0x10000
+#define		bAD11SHGain		0xc0000
+#define		bAD11InputRange		0x700000
+#define		bAD11OPCurrent		0x3800000
+#define		bIPathLoopback		0x4000000
+#define		bQPathLoopback		0x8000000
+#define		bAFELoopback		0x10000000
+#define		bDA10Swing		0x7e0
+#define		bDA10Reverse		0x800
+#define		bDAClkSource		0x1000
+#define		bAD7InputRange		0x6000
+#define		bAD7Gain			0x38000
+#define		bAD7OutputCMMode		0x40000
+#define		bAD7InputCMMode		0x380000
+#define		bAD7Current			0xc00000
+#define		bRegulatorAdjust		0x7000000
+#define		bAD11PowerUpAtTx		0x1
+#define		bDA10PSAtTx		0x10
+#define		bAD11PowerUpAtRx		0x100
+#define		bDA10PSAtRx		0x1000
+#define		bCCKRxAGCFormat		0x200
+#define		bPSDFFTSamplepPoint		0xc000
+#define		bPSDAverageNum		0x3000
+#define		bIQPathControl		0xc00
+#define		bPSDFreq			0x3ff
+#define		bPSDAntennaPath		0x30
+#define		bPSDIQSwitch		0x40
+#define		bPSDRxTrigger		0x400000
+#define		bPSDTxTrigger		0x80000000
+#define		bPSDSineToneScale		0x7f000000
+#define		bPSDReport			0xffff
+
+/* 3. Page9(0x900) */
+#define		bOFDMTxSC                 		0x30000000	/* Useless */
+#define		bCCKTxOn			0x1
+#define		bOFDMTxOn		0x2
+#define		bDebugPage                		0xfff  /* reset debug page and also HWord, LWord */
+#define		bDebugItem                		0xff   /* reset debug page and LWord */
+#define		bAntL			0x10
+#define		bAntNonHT				0x100
+#define		bAntHT1			0x1000
+#define		bAntHT2			0x10000
+#define		bAntHT1S1			0x100000
+#define		bAntNonHTS1		0x1000000
+
+/* 4. PageA(0xA00) */
+#define		bCCKBBMode				0x3	/* Useless */
+#define		bCCKTxPowerSaving		0x80
+#define		bCCKRxPowerSaving		0x40
+
+#define		bCCKSideBand			0x10	/* Reg 0xa00 rCCK0_System 20/40 switch */
+
+#define		bCCKScramble			0x8	/* Useless */
+#define		bCCKAntDiversity		0x8000
+#define		bCCKCarrierRecovery		0x4000
+#define		bCCKTxRate				0x3000
+#define		bCCKDCCancel			0x0800
+#define		bCCKISICancel			0x0400
+#define		bCCKMatchFilter			0x0200
+#define		bCCKEqualizer			0x0100
+#define		bCCKPreambleDetect		0x800000
+#define		bCCKFastFalseCCA		0x400000
+#define		bCCKChEstStart			0x300000
+#define		bCCKCCACount			0x080000
+#define		bCCKcs_lim				0x070000
+#define		bCCKBistMode			0x80000000
+#define		bCCKCCAMask			0x40000000
+#define		bCCKTxDACPhase		0x4
+#define		bCCKRxADCPhase		0x20000000   /* r_rx_clk */
+#define		bCCKr_cp_mode0		0x0100
+#define		bCCKTxDCOffset			0xf0
+#define		bCCKRxDCOffset			0xf
+#define		bCCKCCAMode			0xc000
+#define		bCCKFalseCS_lim			0x3f00
+#define		bCCKCS_ratio			0xc00000
+#define		bCCKCorgBit_sel			0x300000
+#define		bCCKPD_lim				0x0f0000
+#define		bCCKNewCCA			0x80000000
+#define		bCCKRxHPofIG			0x8000
+#define		bCCKRxIG				0x7f00
+#define		bCCKLNAPolarity			0x800000
+#define		bCCKRx1stGain			0x7f0000
+#define		bCCKRFExtend			0x20000000 /* CCK Rx Iinital gain polarity */
+#define		bCCKRxAGCSatLevel		0x1f000000
+#define		bCCKRxAGCSatCount		0xe0
+#define		bCCKRxRFSettle			0x1f       /* AGCsamp_dly */
+#define		bCCKFixedRxAGC			0x8000
+/* #define bCCKRxAGCFormat		0x4000 */   /* remove to HSSI register 0x824 */
+#define		bCCKAntennaPolarity		0x2000
+#define		bCCKTxFilterType		0x0c00
+#define		bCCKRxAGCReportType	0x0300
+#define		bCCKRxDAGCEn			0x80000000
+#define		bCCKRxDAGCPeriod		0x20000000
+#define		bCCKRxDAGCSatLevel		0x1f000000
+#define		bCCKTimingRecovery		0x800000
+#define		bCCKTxC0				0x3f0000
+#define		bCCKTxC1				0x3f000000
+#define		bCCKTxC2				0x3f
+#define		bCCKTxC3				0x3f00
+#define		bCCKTxC4				0x3f0000
+#define		bCCKTxC5				0x3f000000
+#define		bCCKTxC6				0x3f
+#define		bCCKTxC7				0x3f00
+#define		bCCKDebugPort			0xff0000
+#define		bCCKDACDebug			0x0f000000
+#define		bCCKFalseAlarmEnable	0x8000
+#define		bCCKFalseAlarmRead		0x4000
+#define		bCCKTRSSI				0x7f
+#define		bCCKRxAGCReport		0xfe
+#define		bCCKRxReport_AntSel	0x80000000
+#define		bCCKRxReport_MFOff		0x40000000
+#define		bCCKRxRxReport_SQLoss	0x20000000
+#define		bCCKRxReport_Pktloss	0x10000000
+#define		bCCKRxReport_Lockedbit	0x08000000
+#define		bCCKRxReport_RateError	0x04000000
+#define		bCCKRxReport_RxRate	0x03000000
+#define		bCCKRxFACounterLower	0xff
+#define		bCCKRxFACounterUpper	0xff000000
+#define		bCCKRxHPAGCStart		0xe000
+#define		bCCKRxHPAGCFinal		0x1c00
+#define		bCCKRxFalseAlarmEnable	0x8000
+#define		bCCKFACounterFreeze	0x4000
+#define		bCCKTxPathSel			0x10000000
+#define		bCCKDefaultRxPath		0xc000000
+#define		bCCKOptionRxPath		0x3000000
+
+/* 5. PageC(0xC00) */
+#define		bNumOfSTF				0x3	/* Useless */
+#define		bShift_L					0xc0
+#define		bGI_TH					0xc
+#define		bRxPathA				0x1
+#define		bRxPathB				0x2
+#define		bRxPathC				0x4
+#define		bRxPathD				0x8
+#define		bTxPathA				0x1
+#define		bTxPathB				0x2
+#define		bTxPathC				0x4
+#define		bTxPathD				0x8
+#define		bTRSSIFreq				0x200
+#define		bADCBackoff				0x3000
+#define		bDFIRBackoff			0xc000
+#define		bTRSSILatchPhase		0x10000
+#define		bRxIDCOffset			0xff
+#define		bRxQDCOffset			0xff00
+#define		bRxDFIRMode			0x1800000
+#define		bRxDCNFType			0xe000000
+#define		bRXIQImb_A				0x3ff
+#define		bRXIQImb_B				0xfc00
+#define		bRXIQImb_C				0x3f0000
+#define		bRXIQImb_D				0xffc00000
+#define		bDC_dc_Notch			0x60000
+#define		bRxNBINotch			0x1f000000
+#define		bPD_TH					0xf
+#define		bPD_TH_Opt2			0xc000
+#define		bPWED_TH				0x700
+#define		bIfMF_Win_L			0x800
+#define		bPD_Option				0x1000
+#define		bMF_Win_L				0xe000
+#define		bBW_Search_L			0x30000
+#define		bwin_enh_L				0xc0000
+#define		bBW_TH					0x700000
+#define		bED_TH2				0x3800000
+#define		bBW_option				0x4000000
+#define		bRatio_TH				0x18000000
+#define		bWindow_L				0xe0000000
+#define		bSBD_Option				0x1
+#define		bFrame_TH				0x1c
+#define		bFS_Option				0x60
+#define		bDC_Slope_check		0x80
+#define		bFGuard_Counter_DC_L	0xe00
+#define		bFrame_Weight_Short	0x7000
+#define		bSub_Tune				0xe00000
+#define		bFrame_DC_Length		0xe000000
+#define		bSBD_start_offset		0x30000000
+#define		bFrame_TH_2			0x7
+#define		bFrame_GI2_TH			0x38
+#define		bGI2_Sync_en			0x40
+#define		bSarch_Short_Early		0x300
+#define		bSarch_Short_Late		0xc00
+#define		bSarch_GI2_Late		0x70000
+#define		bCFOAntSum				0x1
+#define		bCFOAcc				0x2
+#define		bCFOStartOffset			0xc
+#define		bCFOLookBack			0x70
+#define		bCFOSumWeight			0x80
+#define		bDAGCEnable			0x10000
+#define		bTXIQImb_A				0x3ff
+#define		bTXIQImb_B				0xfc00
+#define		bTXIQImb_C				0x3f0000
+#define		bTXIQImb_D				0xffc00000
+#define		bTxIDCOffset			0xff
+#define		bTxQDCOffset			0xff00
+#define		bTxDFIRMode			0x10000
+#define		bTxPesudoNoiseOn		0x4000000
+#define		bTxPesudoNoise_A		0xff
+#define		bTxPesudoNoise_B		0xff00
+#define		bTxPesudoNoise_C		0xff0000
+#define		bTxPesudoNoise_D		0xff000000
+#define		bCCADropOption			0x20000
+#define		bCCADropThres			0xfff00000
+#define		bEDCCA_H				0xf
+#define		bEDCCA_L				0xf0
+#define		bLambda_ED			0x300
+#define		bRxInitialGain			0x7f
+#define		bRxAntDivEn				0x80
+#define		bRxAGCAddressForLNA	0x7f00
+#define		bRxHighPowerFlow		0x8000
+#define		bRxAGCFreezeThres		0xc0000
+#define		bRxFreezeStep_AGC1	0x300000
+#define		bRxFreezeStep_AGC2	0xc00000
+#define		bRxFreezeStep_AGC3	0x3000000
+#define		bRxFreezeStep_AGC0	0xc000000
+#define		bRxRssi_Cmp_En			0x10000000
+#define		bRxQuickAGCEn			0x20000000
+#define		bRxAGCFreezeThresMode	0x40000000
+#define		bRxOverFlowCheckType	0x80000000
+#define		bRxAGCShift				0x7f
+#define		bTRSW_Tri_Only			0x80
+#define		bPowerThres			0x300
+#define		bRxAGCEn				0x1
+#define		bRxAGCTogetherEn		0x2
+#define		bRxAGCMin				0x4
+#define		bRxHP_Ini				0x7
+#define		bRxHP_TRLNA			0x70
+#define		bRxHP_RSSI				0x700
+#define		bRxHP_BBP1				0x7000
+#define		bRxHP_BBP2				0x70000
+#define		bRxHP_BBP3				0x700000
+#define		bRSSI_H					0x7f0000     /* the threshold for high power */
+#define		bRSSI_Gen				0x7f000000   /* the threshold for ant diversity */
+#define		bRxSettle_TRSW			0x7
+#define		bRxSettle_LNA			0x38
+#define		bRxSettle_RSSI			0x1c0
+#define		bRxSettle_BBP			0xe00
+#define		bRxSettle_RxHP			0x7000
+#define		bRxSettle_AntSW_RSSI	0x38000
+#define		bRxSettle_AntSW		0xc0000
+#define		bRxProcessTime_DAGC	0x300000
+#define		bRxSettle_HSSI			0x400000
+#define		bRxProcessTime_BBPPW	0x800000
+#define		bRxAntennaPowerShift	0x3000000
+#define		bRSSITableSelect		0xc000000
+#define		bRxHP_Final				0x7000000
+#define		bRxHTSettle_BBP			0x7
+#define		bRxHTSettle_HSSI		0x8
+#define		bRxHTSettle_RxHP		0x70
+#define		bRxHTSettle_BBPPW		0x80
+#define		bRxHTSettle_Idle		0x300
+#define		bRxHTSettle_Reserved	0x1c00
+#define		bRxHTRxHPEn			0x8000
+#define		bRxHTAGCFreezeThres	0x30000
+#define		bRxHTAGCTogetherEn	0x40000
+#define		bRxHTAGCMin			0x80000
+#define		bRxHTAGCEn				0x100000
+#define		bRxHTDAGCEn			0x200000
+#define		bRxHTRxHP_BBP			0x1c00000
+#define		bRxHTRxHP_Final		0xe0000000
+#define		bRxPWRatioTH			0x3
+#define		bRxPWRatioEn			0x4
+#define		bRxMFHold				0x3800
+#define		bRxPD_Delay_TH1		0x38
+#define		bRxPD_Delay_TH2		0x1c0
+#define		bRxPD_DC_COUNT_MAX	0x600
+/* #define bRxMF_Hold               0x3800 */
+#define		bRxPD_Delay_TH			0x8000
+#define		bRxProcess_Delay		0xf0000
+#define		bRxSearchrange_GI2_Early	0x700000
+#define		bRxFrame_Guard_Counter_L	0x3800000
+#define		bRxSGI_Guard_L			0xc000000
+#define		bRxSGI_Search_L		0x30000000
+#define		bRxSGI_TH				0xc0000000
+#define		bDFSCnt0				0xff
+#define		bDFSCnt1				0xff00
+#define		bDFSFlag				0xf0000
+#define		bMFWeightSum			0x300000
+#define		bMinIdxTH				0x7f000000
+#define		bDAFormat				0x40000
+#define		bTxChEmuEnable		0x01000000
+#define		bTRSWIsolation_A		0x7f
+#define		bTRSWIsolation_B		0x7f00
+#define		bTRSWIsolation_C		0x7f0000
+#define		bTRSWIsolation_D		0x7f000000
+#define		bExtLNAGain				0x7c00
+
+/* 6. PageE(0xE00) */
+#define		bSTBCEn				0x4	/* Useless */
+#define		bAntennaMapping		0x10
+#define		bNss					0x20
+#define		bCFOAntSumD			0x200
+#define		bPHYCounterReset		0x8000000
+#define		bCFOReportGet			0x4000000
+#define		bOFDMContinueTx		0x10000000
+#define		bOFDMSingleCarrier		0x20000000
+#define		bOFDMSingleTone		0x40000000
+/* #define bRxPath1                 0x01 */
+/* #define bRxPath2                 0x02 */
+/* #define bRxPath3                 0x04 */
+/* #define bRxPath4                 0x08 */
+/* #define bTxPath1                 0x10 */
+/* #define bTxPath2                 0x20 */
+#define		bHTDetect			0x100
+#define		bCFOEn				0x10000
+#define		bCFOValue			0xfff00000
+#define		bSigTone_Re		0x3f
+#define		bSigTone_Im		0x7f00
+#define		bCounter_CCA		0xffff
+#define		bCounter_ParityFail	0xffff0000
+#define		bCounter_RateIllegal		0xffff
+#define		bCounter_CRC8Fail	0xffff0000
+#define		bCounter_MCSNoSupport	0xffff
+#define		bCounter_FastSync	0xffff
+#define		bShortCFO			0xfff
+#define		bShortCFOTLength	12   /* total */
+#define		bShortCFOFLength	11   /* fraction */
+#define		bLongCFO			0x7ff
+#define		bLongCFOTLength	11
+#define		bLongCFOFLength	11
+#define		bTailCFO			0x1fff
+#define		bTailCFOTLength		13
+#define		bTailCFOFLength		12
+#define		bmax_en_pwdB		0xffff
+#define		bCC_power_dB		0xffff0000
+#define		bnoise_pwdB		0xffff
+#define		bPowerMeasTLength	10
+#define		bPowerMeasFLength	3
+#define		bRx_HT_BW			0x1
+#define		bRxSC				0x6
+#define		bRx_HT				0x8
+#define		bNB_intf_det_on		0x1
+#define		bIntf_win_len_cfg	0x30
+#define		bNB_Intf_TH_cfg		0x1c0
+#define		bRFGain				0x3f
+#define		bTableSel			0x40
+#define		bTRSW				0x80
+#define		bRxSNR_A			0xff
+#define		bRxSNR_B			0xff00
+#define		bRxSNR_C			0xff0000
+#define		bRxSNR_D			0xff000000
+#define		bSNREVMTLength		8
+#define		bSNREVMFLength		1
+#define		bCSI1st				0xff
+#define		bCSI2nd				0xff00
+#define		bRxEVM1st			0xff0000
+#define		bRxEVM2nd			0xff000000
+#define		bSIGEVM			0xff
+#define		bPWDB				0xff00
+#define		bSGIEN				0x10000
+
+#define		bSFactorQAM1		0xf	/* Useless */
+#define		bSFactorQAM2		0xf0
+#define		bSFactorQAM3		0xf00
+#define		bSFactorQAM4		0xf000
+#define		bSFactorQAM5		0xf0000
+#define		bSFactorQAM6		0xf0000
+#define		bSFactorQAM7		0xf00000
+#define		bSFactorQAM8		0xf000000
+#define		bSFactorQAM9		0xf0000000
+#define		bCSIScheme			0x100000
+
+#define		bNoiseLvlTopSet		0x3	/* Useless */
+#define		bChSmooth			0x4
+#define		bChSmoothCfg1		0x38
+#define		bChSmoothCfg2		0x1c0
+#define		bChSmoothCfg3		0xe00
+#define		bChSmoothCfg4		0x7000
+#define		bMRCMode			0x800000
+#define		bTHEVMCfg			0x7000000
+
+#define		bLoopFitType		0x1	/* Useless */
+#define		bUpdCFO			0x40
+#define		bUpdCFOOffData		0x80
+#define		bAdvUpdCFO			0x100
+#define		bAdvTimeCtrl		0x800
+#define		bUpdClko			0x1000
+#define		bFC					0x6000
+#define		bTrackingMode		0x8000
+#define		bPhCmpEnable		0x10000
+#define		bUpdClkoLTF		0x20000
+#define		bComChCFO			0x40000
+#define		bCSIEstiMode		0x80000
+#define		bAdvUpdEqz			0x100000
+#define		bUChCfg				0x7000000
+#define		bUpdEqz			0x8000000
+
+/* Rx Pseduo noise */
+#define		bRxPesudoNoiseOn		0x20000000	/* Useless */
+#define		bRxPesudoNoise_A		0xff
+#define		bRxPesudoNoise_B		0xff00
+#define		bRxPesudoNoise_C		0xff0000
+#define		bRxPesudoNoise_D		0xff000000
+#define		bPesudoNoiseState_A	0xffff
+#define		bPesudoNoiseState_B	0xffff0000
+#define		bPesudoNoiseState_C	0xffff
+#define		bPesudoNoiseState_D	0xffff0000
+
+/* 7. RF Register
+ * Zebra1 */
+#define		bZebra1_HSSIEnable		0x8		/* Useless */
+#define		bZebra1_TRxControl		0xc00
+#define		bZebra1_TRxGainSetting	0x07f
+#define		bZebra1_RxCorner		0xc00
+#define		bZebra1_TxChargePump	0x38
+#define		bZebra1_RxChargePump	0x7
+#define		bZebra1_ChannelNum	0xf80
+#define		bZebra1_TxLPFBW		0x400
+#define		bZebra1_RxLPFBW		0x600
+
+/* Zebra4 */
+#define		bRTL8256RegModeCtrl1	0x100	/* Useless */
+#define		bRTL8256RegModeCtrl0	0x40
+#define		bRTL8256_TxLPFBW		0x18
+#define		bRTL8256_RxLPFBW		0x600
+
+/* RTL8258 */
+#define		bRTL8258_TxLPFBW		0xc	/* Useless */
+#define		bRTL8258_RxLPFBW		0xc00
+#define		bRTL8258_RSSILPFBW	0xc0
+
+
+/*
+ * Other Definition
+ *   */
+
+/* byte endable for sb_write */
+#define		bByte0				0x1	/* Useless */
+#define		bByte1				0x2
+#define		bByte2				0x4
+#define		bByte3				0x8
+#define		bWord0				0x3
+#define		bWord1				0xc
+#define		bDWord				0xf
+
+/* for PutRegsetting & GetRegSetting BitMask */
+#define		bMaskByte0			0xff	/* Reg 0xc50 rOFDM0_XAAGCCore~0xC6f */
+#define		bMaskByte1			0xff00
+#define		bMaskByte2			0xff0000
+#define		bMaskByte3			0xff000000
+#define		bMaskHWord		0xffff0000
+#define		bMaskLWord			0x0000ffff
+#define		bMaskDWord		0xffffffff
+#define		bMaskH3Bytes		0xffffff00
+#define		bMask12Bits			0xfff
+#define		bMaskH4Bits			0xf0000000
+#define		bMaskOFDM_D		0xffc00000
+#define		bMaskCCK			0x3f3f3f3f
+
+
+#define		bEnable			0x1	/* Useless */
+#define		bDisable		0x0
+
+#define		LeftAntenna		0x0	/* Useless */
+#define		RightAntenna	0x1
+
+#define		tCheckTxStatus		500   /* 500ms */ /* Useless */
+#define		tUpdateRxCounter	100   /* 100ms */
+
+#define		rateCCK		0	/* Useless */
+#define		rateOFDM	1
+#define		rateHT		2
+
+/* define Register-End */
+#define		bPMAC_End			0x1ff	/* Useless */
+#define		bFPGAPHY0_End		0x8ff
+#define		bFPGAPHY1_End		0x9ff
+#define		bCCKPHY0_End		0xaff
+#define		bOFDMPHY0_End		0xcff
+#define		bOFDMPHY1_End		0xdff
+
+/* define max debug item in each debug page
+ * #define bMaxItem_FPGA_PHY0        0x9
+ * #define bMaxItem_FPGA_PHY1        0x3
+ * #define bMaxItem_PHY_11B          0x16
+ * #define bMaxItem_OFDM_PHY0        0x29
+ * #define bMaxItem_OFDM_PHY1        0x0 */
+
+#define		bPMACControl		0x0		/* Useless */
+#define		bWMACControl		0x1
+#define		bWNICControl		0x2
+
+#define		PathA			0x0	/* Useless */
+#define		PathB			0x1
+#define		PathC			0x2
+#define		PathD			0x3
+
+/*--------------------------Define Parameters-------------------------------*/
+
+
+/* BB Register Definition
+ *
+ * 4. Page9(0x900)
+ *   */
+#define rDPDT_control				0x92c
+#define rfe_ctrl_anta_src				0x930
+#define rS0S1_PathSwitch			0x948
+#define	BBrx_DFIR						0x954
+#define AGC_table_select				0xb2c
+
+/*
+ * PageB(0xB00)
+ *   */
+#define rPdp_AntA						0xb00
+#define rPdp_AntA_4						0xb04
+#define rPdp_AntA_8						0xb08
+#define rPdp_AntA_C						0xb0c
+#define rPdp_AntA_10					0xb10
+#define rPdp_AntA_14					0xb14
+#define rPdp_AntA_18					0xb18
+#define rPdp_AntA_1C					0xb1c
+#define rPdp_AntA_20					0xb20
+#define rPdp_AntA_24					0xb24
+
+#define rConfig_Pmpd_AntA				0xb28
+#define rConfig_ram64x16				0xb2c
+
+#define rBndA							0xb30
+#define rHssiPar						0xb34
+
+#define rConfig_AntA					0xb68
+#define rConfig_AntB					0xb6c
+
+#define rPdp_AntB						0xb70
+#define rPdp_AntB_4						0xb74
+#define rPdp_AntB_8						0xb78
+#define rPdp_AntB_C						0xb7c
+#define rPdp_AntB_10					0xb80
+#define rPdp_AntB_14					0xb84
+#define rPdp_AntB_18					0xb88
+#define rPdp_AntB_1C					0xb8c
+#define rPdp_AntB_20					0xb90
+#define rPdp_AntB_24					0xb94
+
+#define rConfig_Pmpd_AntB				0xb98
+
+#define rBndB							0xba0
+
+#define rAPK							0xbd8
+#define rPm_Rx0_AntA					0xbdc
+#define rPm_Rx1_AntA					0xbe0
+#define rPm_Rx2_AntA					0xbe4
+#define rPm_Rx3_AntA					0xbe8
+#define rPm_Rx0_AntB					0xbec
+#define rPm_Rx1_AntB					0xbf0
+#define rPm_Rx2_AntB					0xbf4
+#define rPm_Rx3_AntB					0xbf8
+
+#endif
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/include/Hal8188FPwrSeq.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/Hal8188FPwrSeq.h
--- linux-5.6.3/3rdparty/rtl8821ce/include/Hal8188FPwrSeq.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/Hal8188FPwrSeq.h	2020-04-10 16:35:06.844661375 +0300
@@ -0,0 +1,212 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2016 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#ifndef REALTEK_POWER_SEQUENCE_8188F
+#define REALTEK_POWER_SEQUENCE_8188F
+
+#include "HalPwrSeqCmd.h"
+
+/*
+	Check document WM-20130815-JackieLau-RTL8188F_Power_Architecture v08.vsd
+	There are 6 HW Power States:
+	0: POFF--Power Off
+	1: PDN--Power Down
+	2: CARDEMU--Card Emulation
+	3: ACT--Active Mode
+	4: LPS--Low Power State
+	5: SUS--Suspend
+
+	The transision from different states are defined below
+	TRANS_CARDEMU_TO_ACT
+	TRANS_ACT_TO_CARDEMU
+	TRANS_CARDEMU_TO_SUS
+	TRANS_SUS_TO_CARDEMU
+	TRANS_CARDEMU_TO_PDN
+	TRANS_ACT_TO_LPS
+	TRANS_LPS_TO_ACT
+
+	TRANS_END
+*/
+#define	RTL8188F_TRANS_CARDEMU_TO_ACT_STEPS	13
+#define	RTL8188F_TRANS_ACT_TO_CARDEMU_STEPS	15
+#define	RTL8188F_TRANS_CARDEMU_TO_SUS_STEPS	14
+#define	RTL8188F_TRANS_SUS_TO_CARDEMU_STEPS	15
+#define	RTL8188F_TRANS_CARDEMU_TO_PDN_STEPS	15
+#define	RTL8188F_TRANS_PDN_TO_CARDEMU_STEPS	15
+#define	RTL8188F_TRANS_ACT_TO_LPS_STEPS		11
+#define	RTL8188F_TRANS_LPS_TO_ACT_STEPS		13
+#define	RTL8188F_TRANS_ACT_TO_SWLPS_STEPS		21
+#define	RTL8188F_TRANS_SWLPS_TO_ACT_STEPS		14
+#define	RTL8188F_TRANS_END_STEPS		1
+
+
+#define RTL8188F_TRANS_CARDEMU_TO_ACT														\
+	/* format */																\
+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, 0},/* disable SW LPS 0x04[10]=0*/	\
+	{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT1, BIT1},/* wait till 0x04[17] = 1    power ready*/	\
+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, 0},/* disable HWPDN 0x04[15]=0*/	\
+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, (BIT3), 0},/*  0x4[11]=1'b0 disable WL suspend*/	\
+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0},/* 0x4[8]=1 polling until return 0*/	\
+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT0, 0},/**/	 \
+	{0x0027, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xff, 0x35}, /*0x27<=35 to reduce RF noise*/
+
+#define RTL8188F_TRANS_ACT_TO_CARDEMU													\
+	/* format */																\
+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
+	{0x001F, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0},/*0x1F[7:0] = 0 turn off RF*/	\
+	{0x004E, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, 0},/*0x4C[23] = 0x4E[7] = 0, switch DPDT_SEL_P output from register 0x65[2] */\
+	{0x0027, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xff, 0x34}, /*0x27 <= 34, xtal_qsel = 0 to xtal bring up*/\
+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1}, /*0x04[9] = 1 turn off MAC by HW state machine*/	\
+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT1, 0}, /*wait till 0x04[9] = 0 polling until return 0 to disable*/	\
+
+#define RTL8188F_TRANS_CARDEMU_TO_SUS													\
+	/* format */																\
+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
+	{0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x00}, /*0x07 = 0x00 , SOP option to disable BG/MB*/	\
+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT4, BIT3}, /*0x04[12:11] = 2b'01 enable WL suspend*/	\
+	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT0, BIT0}, /*Set SDIO suspend local register*/	\
+	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, 0}, /*wait power state to suspend*/ \
+	{0x00C4, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, BIT4},/* 0xC4[4] <= 1, turn off USB APHY LDO under suspend mode*/
+
+#define RTL8188F_TRANS_SUS_TO_CARDEMU													\
+	/* format */																\
+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
+	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT0, 0}, /*Set SDIO suspend local register*/	\
+	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, BIT1}, /*wait power state to suspend*/\
+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT4, 0}, /*0x04[12:11] = 2b'01enable WL suspend*/	\
+	{0x00C4, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0},/* 0xC4[4] <= 1, turn off USB APHY LDO under suspend mode*/
+
+#define RTL8188F_TRANS_CARDEMU_TO_CARDDIS													\
+	/* format */																\
+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
+	{0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x00}, /*0x07 = 0x00 , SOP option to disable BG/MB*/	\
+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT4, BIT3}, /*0x04[12:11] = 2b'01 enable WL suspend*/	\
+	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT0, BIT0}, /*Set SDIO suspend local register*/	\
+	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, 0}, /*wait power state to suspend*/ \
+	{0x00C4, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, BIT4},/* 0xC4[4] <= 1, turn off USB APHY LDO under suspend mode*/
+
+#define RTL8188F_TRANS_CARDDIS_TO_CARDEMU													\
+	/* format */																\
+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
+	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT0, 0}, /*Set SDIO suspend local register*/	\
+	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, BIT1}, /*wait power state to suspend*/\
+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT4, 0}, /*0x04[12:11] = 2b'01enable WL suspend*/	\
+	{0x00C4, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0},/* 0xC4[4] <= 1, turn off USB APHY LDO under suspend mode*/
+
+
+#define RTL8188F_TRANS_CARDEMU_TO_PDN												\
+	/* format */																\
+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
+	{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0},/* 0x04[16] = 0*/\
+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, BIT7},/* 0x04[15] = 1*/
+
+#define RTL8188F_TRANS_PDN_TO_CARDEMU												\
+	/* format */																\
+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, 0},/* 0x04[15] = 0*/
+
+#define RTL8188F_TRANS_ACT_TO_LPS														\
+	/* format */																\
+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
+	{0x0139, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0},/*set RPWM IMR*/	\
+	{0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF},/*Tx Pause*/	\
+	{0x05F8, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/	\
+	{0x05F9, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/	\
+	{0x05FA, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/	\
+	{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0},/*CCK and OFDM are disabled, and clock are gated*/	\
+	{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_US},/*Delay 1us*/	\
+	{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0},/*Whole BB is reset*/	\
+	{0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x3F},/*Reset MAC TRX*/	\
+	{0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0},/*check if removed later*/	\
+	{0x0553, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT5, BIT5},/*Respond TxOK to scheduler*/
+
+
+#define RTL8188F_TRANS_LPS_TO_ACT															\
+	/* format */																\
+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
+	{0x0080, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, 0xFF, 0x84},  /*SDIO RPWM*/\
+	{0xFE58, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x84}, /*USB RPWM*/\
+	{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_MS}, /*Delay*/\
+	{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_MS}, /*Delay*/\
+	{0x0027, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xff, 0x35},/*xtal_qsel = 1 for low noise*/	\
+	{0x0109, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT7, 0}, /*Polling 0x109[7]=0  TSF in 40M*/\
+	{0x002B, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x1c, 0x1c},   /*.	0x2b[4:2] = 3b'111	to enable BB, AFE clock*/\
+	{0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1}, /*.	0x101[1] = 1*/\
+	{0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF}, /*.	0x100[7:0] = 0xFF	 enable WMAC TRX*/\
+	{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1 | BIT0, BIT1 | BIT0},  /*.	0x02[1:0] = 2b'11	 enable BB macro*/\
+	{0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0}, /*.	0x522 = 0*/
+
+
+#define RTL8188F_TRANS_ACT_TO_SWLPS														\
+	/* format */																\
+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
+	{0x0139, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0},/*set RPWM IMR*/	\
+	{0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF},/*Tx Pause*/	\
+	{0x05F8, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/	\
+	{0x05F9, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/	\
+	{0x05FA, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/	\
+	{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0},/*CCK and OFDM are disabled, and clock are gated*/	\
+	{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_US},/*Delay 1us*/	\
+	{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0},/*Whole BB is reset*/	\
+	{0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x3F},/*Reset MAC TRX*/	\
+	{0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0},/*check if removed later*/	\
+	{0x0553, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT5, BIT5},/*Respond TxOK to scheduler*/	\
+	{0x002b, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x1C, 0x00},/*0x2b[4:2]<=0 to gated BB, AFE clock*/	\
+	{0x0027, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xff, 0x34},/*xtal_qsel = 0 for bring up*/	\
+	{0x0093, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xff, 0x00},/* sdio LPS option*/	\
+	{0x0093, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xff, 0x83},/* usb LPS option, open bandgap, xtal*/	\
+	{0x00C4, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT5, 0}, /* 0xC4[5]<=0, digital LDO no standby mode*/	\
+	{0x00C4, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, BIT7}, /* 0xC4[7]<=1, on domain voltage adjust*/	\
+	{0x00a7, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xff, 0xe0}, /* low power LPS enable for sdio*/	\
+	{0x00a7, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xff, 0xe4}, /* low power LPS enable for usb*/	\
+	{0x0090, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0}, /* enable WL_LPS_EN*/
+
+
+#define RTL8188F_TRANS_SWLPS_TO_ACT															\
+	/* format */																\
+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
+	{0x0109, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, 0},/*polling TSF stable*/\
+	{0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1}, /*.	0x101[1] = 1, enable security engine*/\
+	{0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF}, /*.	0x100[7:0] = 0xFF	 enable WMAC TRX*/\
+	{0x06B7, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x09}, /*.	reset MAC rx state machine*/\
+	{0x06B4, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x86}, /*.	reset MAC rx state machine*/\
+	{0x0080, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1},/* set CPU RAM code ready*/	\
+	{0x001D, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0},/*Reset CPU IO Wrapper*/	\
+	{0x0003, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, 0},/* Enable CPU*/	\
+	{0x001D, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0},/*enable CPU IO Wrapper*/	\
+	{0x0003, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, BIT2},/* Enable CPU*/	\
+	{0x0080, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT7, BIT7},/*polling FW init ready */	\
+	{0x0080, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT6, BIT6},/*polling FW init ready */	\
+	{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0}, /*.	0x02[1:0] = 2b'11	 enable BB macro*/\
+	{0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0}, /*.	0x522 = 0*/
+
+#define RTL8188F_TRANS_END															\
+	/* format */																\
+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
+	{0xFFFF, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, 0, PWR_CMD_END, 0, 0},
+
+
+	extern WLAN_PWR_CFG rtl8188F_power_on_flow[RTL8188F_TRANS_CARDEMU_TO_ACT_STEPS + RTL8188F_TRANS_END_STEPS];
+	extern WLAN_PWR_CFG rtl8188F_radio_off_flow[RTL8188F_TRANS_ACT_TO_CARDEMU_STEPS + RTL8188F_TRANS_END_STEPS];
+	extern WLAN_PWR_CFG rtl8188F_card_disable_flow[RTL8188F_TRANS_ACT_TO_CARDEMU_STEPS + RTL8188F_TRANS_CARDEMU_TO_PDN_STEPS + RTL8188F_TRANS_END_STEPS];
+	extern WLAN_PWR_CFG rtl8188F_card_enable_flow[RTL8188F_TRANS_ACT_TO_CARDEMU_STEPS + RTL8188F_TRANS_CARDEMU_TO_PDN_STEPS + RTL8188F_TRANS_END_STEPS];
+	extern WLAN_PWR_CFG rtl8188F_suspend_flow[RTL8188F_TRANS_ACT_TO_CARDEMU_STEPS + RTL8188F_TRANS_CARDEMU_TO_SUS_STEPS + RTL8188F_TRANS_END_STEPS];
+	extern WLAN_PWR_CFG rtl8188F_resume_flow[RTL8188F_TRANS_ACT_TO_CARDEMU_STEPS + RTL8188F_TRANS_CARDEMU_TO_SUS_STEPS + RTL8188F_TRANS_END_STEPS];
+	extern WLAN_PWR_CFG rtl8188F_hwpdn_flow[RTL8188F_TRANS_ACT_TO_CARDEMU_STEPS + RTL8188F_TRANS_CARDEMU_TO_PDN_STEPS + RTL8188F_TRANS_END_STEPS];
+	extern WLAN_PWR_CFG rtl8188F_enter_lps_flow[RTL8188F_TRANS_ACT_TO_LPS_STEPS + RTL8188F_TRANS_END_STEPS];
+	extern WLAN_PWR_CFG rtl8188F_leave_lps_flow[RTL8188F_TRANS_LPS_TO_ACT_STEPS + RTL8188F_TRANS_END_STEPS];
+	extern WLAN_PWR_CFG rtl8188F_enter_swlps_flow[RTL8188F_TRANS_ACT_TO_SWLPS_STEPS + RTL8188F_TRANS_END_STEPS];
+	extern WLAN_PWR_CFG rtl8188F_leave_swlps_flow[RTL8188F_TRANS_SWLPS_TO_ACT_STEPS + RTL8188F_TRANS_END_STEPS];
+#endif
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/include/Hal8192EPhyCfg.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/Hal8192EPhyCfg.h
--- linux-5.6.3/3rdparty/rtl8821ce/include/Hal8192EPhyCfg.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/Hal8192EPhyCfg.h	2020-04-10 16:35:06.844661375 +0300
@@ -0,0 +1,148 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2012 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#ifndef __INC_HAL8192EPHYCFG_H__
+#define __INC_HAL8192EPHYCFG_H__
+
+
+/*--------------------------Define Parameters-------------------------------*/
+#define LOOP_LIMIT				5
+#define MAX_STALL_TIME			50		/* us */
+#define AntennaDiversityValue	0x80	/* (Adapter->bSoftwareAntennaDiversity ? 0x00 : 0x80) */
+#define MAX_TXPWR_IDX_NMODE_92S	63
+#define Reset_Cnt_Limit			3
+
+#ifdef CONFIG_PCI_HCI
+	#define MAX_AGGR_NUM	0x0B
+#else
+	#define MAX_AGGR_NUM	0x07
+#endif /* CONFIG_PCI_HCI */
+
+
+/*--------------------------Define Parameters-------------------------------*/
+
+/*------------------------------Define structure----------------------------*/
+
+/* BB/RF related */
+
+/*------------------------------Define structure----------------------------*/
+
+
+/*------------------------Export global variable----------------------------*/
+/*------------------------Export global variable----------------------------*/
+
+
+/*------------------------Export Marco Definition---------------------------*/
+/*------------------------Export Marco Definition---------------------------*/
+
+
+/*--------------------------Exported Function prototype---------------------*/
+/*
+ * BB and RF register read/write
+ *   */
+u32	PHY_QueryBBReg8192E(IN	PADAPTER	Adapter,
+			    IN	u32			RegAddr,
+			    IN	u32			BitMask);
+void	PHY_SetBBReg8192E(IN	PADAPTER		Adapter,
+			  IN	u32			RegAddr,
+			  IN	u32			BitMask,
+			  IN	u32			Data);
+u32	PHY_QueryRFReg8192E(IN	PADAPTER	Adapter,
+			    IN	enum rf_path	eRFPath,
+			    IN	u32			RegAddr,
+			    IN	u32			BitMask);
+void	PHY_SetRFReg8192E(IN	PADAPTER		Adapter,
+			  IN	enum rf_path	eRFPath,
+			  IN	u32			RegAddr,
+			  IN	u32			BitMask,
+			  IN	u32			Data);
+
+/*
+ * Initialization related function
+ *
+ * MAC/BB/RF HAL config */
+int	PHY_MACConfig8192E(IN PADAPTER	Adapter);
+int	PHY_BBConfig8192E(IN PADAPTER	Adapter);
+int	PHY_RFConfig8192E(IN PADAPTER	Adapter);
+
+/* RF config */
+
+
+/*
+ * BB TX Power R/W
+ *   */
+void	PHY_GetTxPowerLevel8192E(IN PADAPTER	Adapter, OUT s32	*powerlevel);
+void	PHY_SetTxPowerLevel8192E(IN PADAPTER	Adapter, IN u8	channel);
+BOOLEAN	PHY_UpdateTxPowerDbm8192E(IN PADAPTER	Adapter, IN int	powerInDbm);
+
+VOID
+PHY_SetTxPowerIndex_8192E(
+	IN	PADAPTER			Adapter,
+	IN	u32					PowerIndex,
+	IN	enum rf_path			RFPath,
+	IN	u8					Rate
+);
+
+u8
+PHY_GetTxPowerIndex_8192E(
+	IN	PADAPTER			pAdapter,
+	IN	enum rf_path			RFPath,
+	IN	u8					Rate,
+	IN	u8					BandWidth,
+	IN	u8					Channel,
+	struct txpwr_idx_comp *tic
+);
+
+/*
+ * channel switch related funciton
+ *   */
+VOID
+PHY_SetSwChnlBWMode8192E(
+	IN	PADAPTER			Adapter,
+	IN	u8					channel,
+	IN	enum channel_width	Bandwidth,
+	IN	u8					Offset40,
+	IN	u8					Offset80
+);
+
+VOID
+PHY_SetRFEReg_8192E(
+	IN PADAPTER		Adapter
+);
+
+void
+phy_SpurCalibration_8192E(
+	IN	PADAPTER			Adapter,
+	IN	enum spur_cal_method	method
+);
+void PHY_SpurCalibration_8192E(IN PADAPTER Adapter);
+
+#ifdef CONFIG_SPUR_CAL_NBI
+void
+phy_SpurCalibration_8192E_NBI(
+	IN	PADAPTER			Adapter
+);
+#endif
+/*
+ * BB/MAC/RF other monitor API
+ *   */
+
+VOID
+phy_set_rf_path_switch_8192e(
+	IN	struct dm_struct		*phydm,
+	IN	bool		bMain
+);
+
+/*--------------------------Exported Function prototype---------------------*/
+#endif /* __INC_HAL8192CPHYCFG_H */
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/include/Hal8192EPhyReg.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/Hal8192EPhyReg.h
--- linux-5.6.3/3rdparty/rtl8821ce/include/Hal8192EPhyReg.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/Hal8192EPhyReg.h	2020-04-10 16:35:06.844661375 +0300
@@ -0,0 +1,1146 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2012 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+/*****************************************************************************
+ *	Copyright(c) 2008,  RealTEK Technology Inc. All Right Reserved.
+ *
+ * Module:	__INC_HAL8192SPHYREG_H
+ *
+ *
+ * Note:	1. Define PMAC/BB register map
+ *			2. Define RF register map
+ *			3. PMAC/BB register bit mask.
+ *			4. RF reg bit mask.
+ *			5. Other BB/RF relative definition.
+ *
+ *
+ * Export:	Constants, macro, functions(API), global variables(None).
+ *
+ * Abbrev:
+ *
+ * History:
+ *		Data		Who		Remark
+ *      08/07/2007  MHC	1. Porting from 9x series PHYCFG.h.
+ *							2. Reorganize code architecture.
+ *	09/25/2008	MH		1. Add RL6052 register definition
+ *
+ *****************************************************************************/
+#ifndef __INC_HAL8192EPHYREG_H
+#define __INC_HAL8192EPHYREG_H
+
+
+/*--------------------------Define Parameters-------------------------------*/
+
+/* ************************************************************
+ * 8192S Regsiter offset definition
+ * ************************************************************ */
+
+/*
+ * BB-PHY register PMAC 0x100 PHY 0x800 - 0xEFF
+ * 1. PMAC duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF
+ * 2. 0x800/0x900/0xA00/0xC00/0xD00/0xE00
+ * 3. RF register 0x00-2E
+ * 4. Bit Mask for BB/RF register
+ * 5. Other defintion for BB/RF R/W
+ *   */
+
+
+/*
+ * 1. PMAC duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF
+ * 1. Page1(0x100)
+ *   */
+#define		rPMAC_Reset					0x100
+#define		rPMAC_TxStart				0x104
+#define		rPMAC_TxLegacySIG			0x108
+#define		rPMAC_TxHTSIG1				0x10c
+#define		rPMAC_TxHTSIG2				0x110
+#define		rPMAC_PHYDebug				0x114
+#define		rPMAC_TxPacketNum			0x118
+#define		rPMAC_TxIdle					0x11c
+#define		rPMAC_TxMACHeader0			0x120
+#define		rPMAC_TxMACHeader1			0x124
+#define		rPMAC_TxMACHeader2			0x128
+#define		rPMAC_TxMACHeader3			0x12c
+#define		rPMAC_TxMACHeader4			0x130
+#define		rPMAC_TxMACHeader5			0x134
+#define		rPMAC_TxDataType				0x138
+#define		rPMAC_TxRandomSeed			0x13c
+#define		rPMAC_CCKPLCPPreamble		0x140
+#define		rPMAC_CCKPLCPHeader			0x144
+#define		rPMAC_CCKCRC16				0x148
+#define		rPMAC_OFDMRxCRC32OK		0x170
+#define		rPMAC_OFDMRxCRC32Er		0x174
+#define		rPMAC_OFDMRxParityEr			0x178
+#define		rPMAC_OFDMRxCRC8Er			0x17c
+#define		rPMAC_CCKCRxRC16Er			0x180
+#define		rPMAC_CCKCRxRC32Er			0x184
+#define		rPMAC_CCKCRxRC32OK			0x188
+#define		rPMAC_TxStatus				0x18c
+
+
+/*
+ * 3. Page8(0x800)
+ *   */
+#define		rFPGA0_RFMOD				0x800	/* RF mode & CCK TxSC */ /* RF BW Setting?? */
+
+#define		rFPGA0_TxInfo					0x804	/* Status report?? */
+#define		rFPGA0_PSDFunction			0x808
+
+#define		rFPGA0_TxGainStage			0x80c	/* Set TX PWR init gain? */
+
+#define		rFPGA0_RFTiming1				0x810	/* Useless now */
+#define		rFPGA0_RFTiming2				0x814
+
+#define		rFPGA0_XA_HSSIParameter1		0x820	/* RF 3 wire register */
+#define		rFPGA0_XA_HSSIParameter2		0x824
+#define		rFPGA0_XB_HSSIParameter1		0x828
+#define		rFPGA0_XB_HSSIParameter2		0x82c
+
+#define		rFPGA0_XA_LSSIParameter		0x840
+#define		rFPGA0_XB_LSSIParameter		0x844
+
+#define		rFPGA0_RFWakeUpParameter	0x850	/* Useless now */
+#define		rFPGA0_RFSleepUpParameter		0x854
+
+#define		rFPGA0_XAB_SwitchControl		0x858	/* RF Channel switch */
+#define		rFPGA0_XCD_SwitchControl		0x85c
+
+#define		rFPGA0_XA_RFInterfaceOE		0x860	/* RF Channel switch */
+#define		rFPGA0_XB_RFInterfaceOE		0x864
+
+#define		rFPGA0_XAB_RFInterfaceSW		0x870	/* RF Interface Software Control */
+#define		rFPGA0_XCD_RFInterfaceSW		0x874
+
+#define		rFPGA0_XAB_RFParameter		0x878	/* RF Parameter */
+#define		rFPGA0_XCD_RFParameter		0x87c
+
+#define		rFPGA0_AnalogParameter1		0x880	/* Crystal cap setting RF-R/W protection for parameter4?? */
+#define		rFPGA0_AnalogParameter2		0x884
+#define		rFPGA0_AnalogParameter3		0x888
+#define		rFPGA0_AdDaClockEn			0x888	/* enable ad/da clock1 for dual-phy */
+#define		rFPGA0_AnalogParameter4		0x88c
+
+#define		rFPGA0_XA_LSSIReadBack		0x8a0	/* Tranceiver LSSI Readback */
+#define		rFPGA0_XB_LSSIReadBack		0x8a4
+#define		rFPGA0_XC_LSSIReadBack		0x8a8
+#define		rFPGA0_XD_LSSIReadBack		0x8ac
+
+#define		rFPGA0_PSDReport				0x8b4	/* Useless now */
+#define		TransceiverA_HSPI_Readback		0x8b8	/* Transceiver A HSPI Readback */
+#define		TransceiverB_HSPI_Readback		0x8bc	/* Transceiver B HSPI Readback */
+#define		rFPGA0_XAB_RFInterfaceRB		0x8e0	/* Useless now */ /* RF Interface Readback Value */
+#define		rFPGA0_XCD_RFInterfaceRB		0x8e4	/* Useless now */
+
+/*
+ * 4. Page9(0x900)
+ *   */
+#define		rFPGA1_RFMOD				0x900	/* RF mode & OFDM TxSC */ /* RF BW Setting?? */
+
+#define		rFPGA1_TxBlock				0x904	/* Useless now */
+#define		rFPGA1_DebugSelect			0x908	/* Useless now */
+#define		rFPGA1_TxInfo					0x90c	/* Useless now */ /* Status report?? */
+
+/*
+ * 5. PageA(0xA00)
+ *
+ * Set Control channel to upper or lower. These settings are required only for 40MHz */
+#define		rCCK0_System					0xa00
+
+#define		rCCK0_AFESetting				0xa04	/* Disable init gain now */ /* Select RX path by RSSI */
+#define		rCCK0_CCA					0xa08	/* Disable init gain now */ /* Init gain */
+
+#define		rCCK0_RxAGC1				0xa0c	/* AGC default value, saturation level  */ /* Antenna Diversity, RX AGC, LNA Threshold, RX LNA Threshold useless now. Not the same as 90 series */
+#define		rCCK0_RxAGC2				0xa10	/* AGC & DAGC */
+
+#define		rCCK0_RxHP					0xa14
+
+#define		rCCK0_DSPParameter1			0xa18	/* Timing recovery & Channel estimation threshold */
+#define		rCCK0_DSPParameter2			0xa1c	/* SQ threshold */
+
+#define		rCCK0_TxFilter1				0xa20
+#define		rCCK0_TxFilter2				0xa24
+#define		rCCK0_DebugPort				0xa28	/* debug port and Tx filter3 */
+#define		rCCK0_FalseAlarmReport		0xa2c	/* 0xa2d	useless now 0xa30-a4f channel report */
+#define		rCCK0_TRSSIReport			0xa50
+#define		rCCK0_RxReport            			0xa54  /* 0xa57 */
+#define		rCCK0_FACounterLower      		0xa5c  /* 0xa5b */
+#define		rCCK0_FACounterUpper      		0xa58  /* 0xa5c */
+
+/*
+ * PageB(0xB00)
+ *   */
+#define		rPdp_AntA					0xb00
+#define		rPdp_AntA_4				0xb04
+#define		rConfig_Pmpd_AntA			0xb28
+#define		rConfig_ram64x16				0xb2c
+
+#define		rConfig_AntA					0xb68
+#define		rConfig_AntB					0xb6c
+#define		rPdp_AntB					0xb70
+#define		rPdp_AntB_4					0xb74
+#define		rConfig_Pmpd_AntB			0xb98
+#define		rAPK							0xbd8
+
+
+
+/*
+ * 6. PageC(0xC00)
+ *   */
+#define		rOFDM0_LSTF					0xc00
+
+#define		rOFDM0_TRxPathEnable			0xc04
+#define		rOFDM0_TRMuxPar				0xc08
+#define		rOFDM0_TRSWIsolation			0xc0c
+
+#define		rOFDM0_XARxAFE				0xc10  /* RxIQ DC offset, Rx digital filter, DC notch filter */
+#define		rOFDM0_XARxIQImbalance    		0xc14  /* RxIQ imblance matrix */
+#define		rOFDM0_XBRxAFE			0xc18
+#define		rOFDM0_XBRxIQImbalance		0xc1c
+#define		rOFDM0_XCRxAFE			0xc20
+#define		rOFDM0_XCRxIQImbalance		0xc24
+#define		rOFDM0_XDRxAFE			0xc28
+#define		rOFDM0_XDRxIQImbalance		0xc2c
+
+#define		rOFDM0_RxDetector1			0xc30  /* PD, BW & SBD	 */ /* DM tune init gain */
+#define		rOFDM0_RxDetector2			0xc34  /* SBD & Fame Sync. */
+#define		rOFDM0_RxDetector3			0xc38  /* Frame Sync. */
+#define		rOFDM0_RxDetector4			0xc3c  /* PD, SBD, Frame Sync & Short-GI */
+
+#define		rOFDM0_RxDSP				0xc40  /* Rx Sync Path */
+#define		rOFDM0_CFOandDAGC			0xc44  /* CFO & DAGC */
+#define		rOFDM0_CCADropThreshold		0xc48 /* CCA Drop threshold */
+#define		rOFDM0_ECCAThreshold			0xc4c /* energy CCA */
+
+#define		rOFDM0_XAAGCCore1			0xc50	/* DIG */
+#define		rOFDM0_XAAGCCore2			0xc54
+#define		rOFDM0_XBAGCCore1			0xc58
+#define		rOFDM0_XBAGCCore2			0xc5c
+#define		rOFDM0_XCAGCCore1			0xc60
+#define		rOFDM0_XCAGCCore2			0xc64
+#define		rOFDM0_XDAGCCore1			0xc68
+#define		rOFDM0_XDAGCCore2			0xc6c
+
+#define		rOFDM0_AGCParameter1		0xc70
+#define		rOFDM0_AGCParameter2		0xc74
+#define		rOFDM0_AGCRSSITable			0xc78
+#define		rOFDM0_HTSTFAGC				0xc7c
+
+#define		rOFDM0_XATxIQImbalance		0xc80	/* TX PWR TRACK and DIG */
+#define		rOFDM0_XATxAFE				0xc84
+#define		rOFDM0_XBTxIQImbalance		0xc88
+#define		rOFDM0_XBTxAFE				0xc8c
+#define		rOFDM0_XCTxIQImbalance		0xc90
+#define		rOFDM0_XCTxAFE			0xc94
+#define		rOFDM0_XDTxIQImbalance		0xc98
+#define		rOFDM0_XDTxAFE				0xc9c
+
+#define		rOFDM0_RxIQExtAnta			0xca0
+#define		rOFDM0_TxCoeff1				0xca4
+#define		rOFDM0_TxCoeff2				0xca8
+#define		rOFDM0_TxCoeff3				0xcac
+#define		rOFDM0_TxCoeff4				0xcb0
+#define		rOFDM0_TxCoeff5				0xcb4
+#define		rOFDM0_RxHPParameter		0xce0
+#define		rOFDM0_TxPseudoNoiseWgt		0xce4
+#define		rOFDM0_FrameSync			0xcf0
+#define		rOFDM0_DFSReport			0xcf4
+
+
+/*
+ * 7. PageD(0xD00)
+ *   */
+#define		rOFDM1_LSTF					0xd00
+#define		rOFDM1_TRxPathEnable			0xd04
+
+#define		rOFDM1_CFO					0xd08	/* No setting now */
+#define		rOFDM1_CSI1					0xd10
+#define		rOFDM1_SBD					0xd14
+#define		rOFDM1_CSI2					0xd18
+#define		rOFDM1_CFOTracking			0xd2c
+#define		rOFDM1_TRxMesaure1			0xd34
+#define		rOFDM1_IntfDet				0xd3c
+#define		rOFDM1_PseudoNoiseStateAB	0xd50
+#define		rOFDM1_PseudoNoiseStateCD	0xd54
+#define		rOFDM1_RxPseudoNoiseWgt		0xd58
+
+#define		rOFDM_PHYCounter1			0xda0  /* cca, parity fail */
+#define		rOFDM_PHYCounter2			0xda4  /* rate illegal, crc8 fail */
+#define		rOFDM_PHYCounter3			0xda8  /* MCS not support */
+
+#define		rOFDM_ShortCFOAB			0xdac	/* No setting now */
+#define		rOFDM_ShortCFOCD			0xdb0
+#define		rOFDM_LongCFOAB				0xdb4
+#define		rOFDM_LongCFOCD				0xdb8
+#define		rOFDM_TailCFOAB				0xdbc
+#define		rOFDM_TailCFOCD				0xdc0
+#define		rOFDM_PWMeasure1		0xdc4
+#define		rOFDM_PWMeasure2		0xdc8
+#define		rOFDM_BWReport				0xdcc
+#define		rOFDM_AGCReport				0xdd0
+#define		rOFDM_RxSNR				0xdd4
+#define		rOFDM_RxEVMCSI				0xdd8
+#define		rOFDM_SIGReport				0xddc
+
+
+/*
+ * 8. PageE(0xE00)
+ *   */
+#define		rTxAGC_A_Rate18_06			0xe00
+#define		rTxAGC_A_Rate54_24			0xe04
+#define		rTxAGC_A_CCK1_Mcs32			0xe08
+#define		rTxAGC_A_Mcs03_Mcs00		0xe10
+#define		rTxAGC_A_Mcs07_Mcs04		0xe14
+#define		rTxAGC_A_Mcs11_Mcs08		0xe18
+#define		rTxAGC_A_Mcs15_Mcs12		0xe1c
+
+#define		rTxAGC_B_Rate18_06			0x830
+#define		rTxAGC_B_Rate54_24			0x834
+#define		rTxAGC_B_CCK1_55_Mcs32		0x838
+#define		rTxAGC_B_Mcs03_Mcs00		0x83c
+#define		rTxAGC_B_Mcs07_Mcs04		0x848
+#define		rTxAGC_B_Mcs11_Mcs08		0x84c
+#define		rTxAGC_B_Mcs15_Mcs12		0x868
+#define		rTxAGC_B_CCK11_A_CCK2_11		0x86c
+
+#define		rFPGA0_IQK					0xe28
+#define		rTx_IQK_Tone_A				0xe30
+#define		rRx_IQK_Tone_A				0xe34
+#define		rTx_IQK_PI_A					0xe38
+#define		rRx_IQK_PI_A					0xe3c
+
+#define		rTx_IQK						0xe40
+#define		rRx_IQK						0xe44
+#define		rIQK_AGC_Pts					0xe48
+#define		rIQK_AGC_Rsp					0xe4c
+#define		rTx_IQK_Tone_B				0xe50
+#define		rRx_IQK_Tone_B				0xe54
+#define		rTx_IQK_PI_B					0xe58
+#define		rRx_IQK_PI_B					0xe5c
+#define		rIQK_AGC_Cont				0xe60
+
+#define		rBlue_Tooth					0xe6c
+#define		rRx_Wait_CCA					0xe70
+#define		rTx_CCK_RFON					0xe74
+#define		rTx_CCK_BBON				0xe78
+#define		rTx_OFDM_RFON				0xe7c
+#define		rTx_OFDM_BBON				0xe80
+#define		rTx_To_Rx					0xe84
+#define		rTx_To_Tx					0xe88
+#define		rRx_CCK						0xe8c
+
+#define		rTx_Power_Before_IQK_A		0xe94
+#define		rTx_Power_After_IQK_A			0xe9c
+
+#define		rRx_Power_Before_IQK_A		0xea0
+#define		rRx_Power_Before_IQK_A_2		0xea4
+#define		rRx_Power_After_IQK_A			0xea8
+#define		rRx_Power_After_IQK_A_2		0xeac
+
+#define		rTx_Power_Before_IQK_B		0xeb4
+#define		rTx_Power_After_IQK_B			0xebc
+
+#define		rRx_Power_Before_IQK_B		0xec0
+#define		rRx_Power_Before_IQK_B_2		0xec4
+#define		rRx_Power_After_IQK_B			0xec8
+#define		rRx_Power_After_IQK_B_2		0xecc
+
+#define		rRx_OFDM					0xed0
+#define		rRx_Wait_RIFS				0xed4
+#define		rRx_TO_Rx					0xed8
+#define		rStandby						0xedc
+#define		rSleep						0xee0
+#define		rPMPD_ANAEN				0xeec
+
+/*
+ * 7. RF Register 0x00-0x2E (RF 8256)
+ * RF-0222D 0x00-3F
+ *
+ * Zebra1 */
+#define		rZebra1_HSSIEnable				0x0	/* Useless now */
+#define		rZebra1_TRxEnable1			0x1
+#define		rZebra1_TRxEnable2			0x2
+#define		rZebra1_AGC					0x4
+#define		rZebra1_ChargePump			0x5
+#define		rZebra1_Channel				0x7	/* RF channel switch */
+
+/* #endif */
+#define		rZebra1_TxGain				0x8	/* Useless now */
+#define		rZebra1_TxLPF					0x9
+#define		rZebra1_RxLPF					0xb
+#define		rZebra1_RxHPFCorner			0xc
+
+/* Zebra4 */
+#define		rGlobalCtrl					0	/* Useless now */
+#define		rRTL8256_TxLPF				19
+#define		rRTL8256_RxLPF				11
+
+/* RTL8258 */
+#define		rRTL8258_TxLPF				0x11	/* Useless now */
+#define		rRTL8258_RxLPF				0x13
+#define		rRTL8258_RSSILPF				0xa
+
+/*
+ * RL6052 Register definition
+ *   */
+#define		RF_AC						0x00	/*  */
+
+#define		RF_IQADJ_G1					0x01	/*  */
+#define		RF_IQADJ_G2					0x02	/*  */
+
+#define		RF_POW_TRSW				0x05	/*  */
+
+#define		RF_GAIN_RX					0x06	/*  */
+#define		RF_GAIN_TX					0x07	/*  */
+
+#define		RF_TXM_IDAC					0x08	/*  */
+#define		RF_IPA_G						0x09	/*  */
+#define		RF_TXBIAS_G					0x0A
+#define		RF_TXPA_AG					0x0B
+#define		RF_IPA_A						0x0C	/*  */
+#define		RF_TXBIAS_A					0x0D
+#define		RF_BS_PA_APSET_G9_G11		0x0E
+#define		RF_BS_IQGEN					0x0F	/*  */
+
+#define		RF_MODE1					0x10	/*  */
+#define		RF_MODE2					0x11	/*  */
+
+#define		RF_RX_AGC_HP				0x12	/*  */
+#define		RF_TX_AGC					0x13	/*  */
+#define		RF_BIAS						0x14	/*  */
+#define		RF_IPA						0x15	/*  */
+#define		RF_TXBIAS					0x16
+#define		RF_POW_ABILITY				0x17	/*  */
+#define		RF_CHNLBW					0x18	/* RF channel and BW switch */
+#define		RF_TOP						0x19	/*  */
+
+#define		RF_RX_G1					0x1A	/*  */
+#define		RF_RX_G2					0x1B	/*  */
+
+#define		RF_RX_BB2					0x1C	/*  */
+#define		RF_RX_BB1					0x1D	/*  */
+
+#define		RF_RCK1						0x1E	/*  */
+#define		RF_RCK2						0x1F	/*  */
+
+#define		RF_TX_G1						0x20	/*  */
+#define		RF_TX_G2						0x21	/*  */
+#define		RF_TX_G3						0x22	/*  */
+
+#define		RF_TX_BB1					0x23	/*  */
+
+#define		RF_T_METER_8192E			0x42	/*  */
+#define		RF_T_METER_88E				0x42
+#define		RF_T_METER					0x24	/*  */
+
+/* #endif */
+
+#define		RF_SYN_G1					0x25	/* RF TX Power control */
+#define		RF_SYN_G2					0x26	/* RF TX Power control */
+#define		RF_SYN_G3					0x27	/* RF TX Power control */
+#define		RF_SYN_G4					0x28	/* RF TX Power control */
+#define		RF_SYN_G5					0x29	/* RF TX Power control */
+#define		RF_SYN_G6					0x2A	/* RF TX Power control */
+#define		RF_SYN_G7					0x2B	/* RF TX Power control */
+#define		RF_SYN_G8					0x2C	/* RF TX Power control */
+
+#define		RF_RCK_OS					0x30	/* RF TX PA control */
+#define		RF_TXPA_G1					0x31	/* RF TX PA control */
+#define		RF_TXPA_G2					0x32	/* RF TX PA control */
+#define		RF_TXPA_G3					0x33	/* RF TX PA control */
+#define		RF_TX_BIAS_A					0x35
+#define		RF_TX_BIAS_D					0x36
+#define		RF_LOBF_9					0x38
+#define		RF_RXRF_A3					0x3C	/*	 */
+#define		RF_TRSW						0x3F
+
+#define		RF_TXRF_A2					0x41
+#define		RF_TXPA_G4					0x46
+#define		RF_TXPA_A4					0x4B
+#define		RF_0x52						0x52
+#define		RF_LDO						0xB1
+#define		RF_WE_LUT					0xEF
+
+
+/*
+ * Bit Mask
+ *
+ * 1. Page1(0x100) */
+#define		bBBResetB					0x100	/* Useless now? */
+#define		bGlobalResetB					0x200
+#define		bOFDMTxStart					0x4
+#define		bCCKTxStart					0x8
+#define		bCRC32Debug					0x100
+#define		bPMACLoopback				0x10
+#define		bTxLSIG						0xffffff
+#define		bOFDMTxRate					0xf
+#define		bOFDMTxReserved				0x10
+#define		bOFDMTxLength				0x1ffe0
+#define		bOFDMTxParity				0x20000
+#define		bTxHTSIG1					0xffffff
+#define		bTxHTMCSRate				0x7f
+#define		bTxHTBW						0x80
+#define		bTxHTLength					0xffff00
+#define		bTxHTSIG2					0xffffff
+#define		bTxHTSmoothing				0x1
+#define		bTxHTSounding				0x2
+#define		bTxHTReserved				0x4
+#define		bTxHTAggreation				0x8
+#define		bTxHTSTBC					0x30
+#define		bTxHTAdvanceCoding			0x40
+#define		bTxHTShortGI					0x80
+#define		bTxHTNumberHT_LTF			0x300
+#define		bTxHTCRC8					0x3fc00
+#define		bCounterReset				0x10000
+#define		bNumOfOFDMTx				0xffff
+#define		bNumOfCCKTx					0xffff0000
+#define		bTxIdleInterval				0xffff
+#define		bOFDMService					0xffff0000
+#define		bTxMACHeader				0xffffffff
+#define		bTxDataInit					0xff
+#define		bTxHTMode					0x100
+#define		bTxDataType					0x30000
+#define		bTxRandomSeed				0xffffffff
+#define		bCCKTxPreamble				0x1
+#define		bCCKTxSFD					0xffff0000
+#define		bCCKTxSIG					0xff
+#define		bCCKTxService					0xff00
+#define		bCCKLengthExt					0x8000
+#define		bCCKTxLength					0xffff0000
+#define		bCCKTxCRC16					0xffff
+#define		bCCKTxStatus					0x1
+#define		bOFDMTxStatus				0x2
+
+#define		IS_BB_REG_OFFSET_92S(_Offset)		((_Offset >= 0x800) && (_Offset <= 0xfff))
+#define		RF_TX_GAIN_OFFSET_8192E(_val)		((abs((_val)) << 1) | (((_val) > 0) ? BIT0 : 0))
+
+
+/* 2. Page8(0x800) */
+#define		bRFMOD						0x1	/* Reg 0x800 rFPGA0_RFMOD */
+#define		bJapanMode					0x2
+#define		bCCKTxSC						0x30
+#define		bCCKEn						0x1000000
+#define		bOFDMEn					0x2000000
+
+#define		bOFDMRxADCPhase           		0x10000	/* Useless now */
+#define		bOFDMTxDACPhase		0x40000
+#define		bXATxAGC				0x3f
+
+#define		bAntennaSelect			0x0300
+
+#define		bXBTxAGC                  				0xf00	/* Reg 80c rFPGA0_TxGainStage */
+#define		bXCTxAGC				0xf000
+#define		bXDTxAGC				0xf0000
+
+#define		bPAStart                  				0xf0000000	/* Useless now */
+#define		bTRStart				0x00f00000
+#define		bRFStart				0x0000f000
+#define		bBBStart				0x000000f0
+#define		bBBCCKStart			0x0000000f
+#define		bPAEnd                    				0xf          /* Reg0x814 */
+#define		bTREnd				0x0f000000
+#define		bRFEnd				0x000f0000
+#define		bCCAMask                  				0x000000f0   /* T2R */
+#define		bR2RCCAMask			0x00000f00
+#define		bHSSI_R2TDelay			0xf8000000
+#define		bHSSI_T2RDelay			0xf80000
+#define		bContTxHSSI               			0x400     /* chane gain at continue Tx */
+#define		bIGFromCCK			0x200
+#define		bAGCAddress			0x3f
+#define		bRxHPTx				0x7000
+#define		bRxHPT2R				0x38000
+#define		bRxHPCCKIni			0xc0000
+#define		bAGCTxCode			0xc00000
+#define		bAGCRxCode			0x300000
+
+#define		b3WireDataLength          			0x800	/* Reg 0x820~84f rFPGA0_XA_HSSIParameter1 */
+#define		b3WireAddressLength		0x400
+
+#define		b3WireRFPowerDown         		0x1	/* Useless now
+ * #define bHWSISelect		0x8 */
+#define		b5GPAPEPolarity			0x40000000
+#define		b2GPAPEPolarity			0x80000000
+#define		bRFSW_TxDefaultAnt		0x3
+#define		bRFSW_TxOptionAnt		0x30
+#define		bRFSW_RxDefaultAnt		0x300
+#define		bRFSW_RxOptionAnt		0x3000
+#define		bRFSI_3WireData			0x1
+#define		bRFSI_3WireClock			0x2
+#define		bRFSI_3WireLoad			0x4
+#define		bRFSI_3WireRW			0x8
+#define		bRFSI_3Wire			0xf
+
+#define		bRFSI_RFENV               		0x10	/* Reg 0x870 rFPGA0_XAB_RFInterfaceSW */
+
+#define		bRFSI_TRSW                		0x20	/* Useless now */
+#define		bRFSI_TRSWB		0x40
+#define		bRFSI_ANTSW		0x100
+#define		bRFSI_ANTSWB		0x200
+#define		bRFSI_PAPE			0x400
+#define		bRFSI_PAPE5G		0x800
+#define		bBandSelect			0x1
+#define		bHTSIG2_GI			0x80
+#define		bHTSIG2_Smoothing		0x01
+#define		bHTSIG2_Sounding		0x02
+#define		bHTSIG2_Aggreaton		0x08
+#define		bHTSIG2_STBC		0x30
+#define		bHTSIG2_AdvCoding		0x40
+#define		bHTSIG2_NumOfHTLTF	0x300
+#define		bHTSIG2_CRC8		0x3fc
+#define		bHTSIG1_MCS		0x7f
+#define		bHTSIG1_BandWidth		0x80
+#define		bHTSIG1_HTLength		0xffff
+#define		bLSIG_Rate			0xf
+#define		bLSIG_Reserved		0x10
+#define		bLSIG_Length		0x1fffe
+#define		bLSIG_Parity			0x20
+#define		bCCKRxPhase		0x4
+
+#define		bLSSIReadAddress          		0x7f800000   /* T65 RF */
+
+#define		bLSSIReadEdge             		0x80000000   /* LSSI "Read" edge signal */
+
+#define		bLSSIReadBackData         		0xfffff		/* T65 RF */
+
+#define		bLSSIReadOKFlag           		0x1000	/* Useless now */
+#define		bCCKSampleRate            		0x8       /* 0: 44MHz, 1:88MHz      		 */
+#define		bRegulator0Standby		0x1
+#define		bRegulatorPLLStandby	0x2
+#define		bRegulator1Standby		0x4
+#define		bPLLPowerUp		0x8
+#define		bDPLLPowerUp		0x10
+#define		bDA10PowerUp		0x20
+#define		bAD7PowerUp		0x200
+#define		bDA6PowerUp		0x2000
+#define		bXtalPowerUp		0x4000
+#define		b40MDClkPowerUP	0x8000
+#define		bDA6DebugMode		0x20000
+#define		bDA6Swing			0x380000
+
+#define		bADClkPhase               		0x4000000	/* Reg 0x880 rFPGA0_AnalogParameter1 20/40 CCK support switch 40/80 BB MHZ */
+
+#define		b80MClkDelay              		0x18000000	/* Useless */
+#define		bAFEWatchDogEnable	0x20000000
+
+#define		bXtalCap01                			0xc0000000	/* Reg 0x884 rFPGA0_AnalogParameter2 Crystal cap */
+#define		bXtalCap23			0x3
+#define		bXtalCap92x				0x0f000000
+#define		bXtalCap			0x0f000000
+
+#define		bIntDifClkEnable          		0x400	/* Useless */
+#define		bExtSigClkEnable		0x800
+#define		bBandgapMbiasPowerUp	0x10000
+#define		bAD11SHGain		0xc0000
+#define		bAD11InputRange		0x700000
+#define		bAD11OPCurrent		0x3800000
+#define		bIPathLoopback		0x4000000
+#define		bQPathLoopback		0x8000000
+#define		bAFELoopback		0x10000000
+#define		bDA10Swing		0x7e0
+#define		bDA10Reverse		0x800
+#define		bDAClkSource		0x1000
+#define		bAD7InputRange		0x6000
+#define		bAD7Gain			0x38000
+#define		bAD7OutputCMMode	0x40000
+#define		bAD7InputCMMode	0x380000
+#define		bAD7Current		0xc00000
+#define		bRegulatorAdjust		0x7000000
+#define		bAD11PowerUpAtTx	0x1
+#define		bDA10PSAtTx		0x10
+#define		bAD11PowerUpAtRx	0x100
+#define		bDA10PSAtRx		0x1000
+#define		bCCKRxAGCFormat		0x200
+#define		bPSDFFTSamplepPoint	0xc000
+#define		bPSDAverageNum		0x3000
+#define		bIQPathControl		0xc00
+#define		bPSDFreq			0x3ff
+#define		bPSDAntennaPath		0x30
+#define		bPSDIQSwitch		0x40
+#define		bPSDRxTrigger		0x400000
+#define		bPSDTxTrigger		0x80000000
+#define		bPSDSineToneScale		0x7f000000
+#define		bPSDReport		0xffff
+
+/* 3. Page9(0x900) */
+#define		bOFDMTxSC                 		0x30000000	/* Useless */
+#define		bCCKTxOn			0x1
+#define		bOFDMTxOn		0x2
+#define		bDebugPage                		0xfff  /* reset debug page and also HWord, LWord */
+#define		bDebugItem                		0xff   /* reset debug page and LWord */
+#define		bAntL				0x10
+#define		bAntNonHT			0x100
+#define		bAntHT1			0x1000
+#define		bAntHT2			0x10000
+#define		bAntHT1S1			0x100000
+#define		bAntNonHTS1		0x1000000
+
+/* 4. PageA(0xA00) */
+#define		bCCKBBMode                		0x3	/* Useless */
+#define		bCCKTxPowerSaving		0x80
+#define		bCCKRxPowerSaving		0x40
+
+#define		bCCKSideBand              		0x10	/* Reg 0xa00 rCCK0_System 20/40 switch */
+
+#define		bCCKScramble              		0x8	/* Useless */
+#define		bCCKAntDiversity			0x8000
+#define		bCCKCarrierRecovery		0x4000
+#define		bCCKTxRate			0x3000
+#define		bCCKDCCancel		0x0800
+#define		bCCKISICancel		0x0400
+#define		bCCKMatchFilter		0x0200
+#define		bCCKEqualizer		0x0100
+#define		bCCKPreambleDetect		0x800000
+#define		bCCKFastFalseCCA		0x400000
+#define		bCCKChEstStart		0x300000
+#define		bCCKCCACount		0x080000
+#define		bCCKcs_lim			0x070000
+#define		bCCKBistMode		0x80000000
+#define		bCCKCCAMask		0x40000000
+#define		bCCKTxDACPhase		0x4
+#define		bCCKRxADCPhase         	   	0x20000000   /* r_rx_clk */
+#define		bCCKr_cp_mode0		0x0100
+#define		bCCKTxDCOffset		0xf0
+#define		bCCKRxDCOffset		0xf
+#define		bCCKCCAMode		0xc000
+#define		bCCKFalseCS_lim		0x3f00
+#define		bCCKCS_ratio		0xc00000
+#define		bCCKCorgBit_sel		0x300000
+#define		bCCKPD_lim		0x0f0000
+#define		bCCKNewCCA		0x80000000
+#define		bCCKRxHPofIG		0x8000
+#define		bCCKRxIG			0x7f00
+#define		bCCKLNAPolarity		0x800000
+#define		bCCKRx1stGain		0x7f0000
+#define		bCCKRFExtend              		0x20000000 /* CCK Rx Iinital gain polarity */
+#define		bCCKRxAGCSatLevel		0x1f000000
+#define		bCCKRxAGCSatCount		0xe0
+#define		bCCKRxRFSettle            		0x1f       /* AGCsamp_dly */
+#define		bCCKFixedRxAGC		0x8000
+/* #define bCCKRxAGCFormat		0x4000 */   /* remove to HSSI register 0x824 */
+#define		bCCKAntennaPolarity		0x2000
+#define		bCCKTxFilterType		0x0c00
+#define		bCCKRxAGCReportType		0x0300
+#define		bCCKRxDAGCEn		0x80000000
+#define		bCCKRxDAGCPeriod		0x20000000
+#define		bCCKRxDAGCSatLevel		0x1f000000
+#define		bCCKTimingRecovery		0x800000
+#define		bCCKTxC0			0x3f0000
+#define		bCCKTxC1			0x3f000000
+#define		bCCKTxC2			0x3f
+#define		bCCKTxC3			0x3f00
+#define		bCCKTxC4			0x3f0000
+#define		bCCKTxC5			0x3f000000
+#define		bCCKTxC6			0x3f
+#define		bCCKTxC7			0x3f00
+#define		bCCKDebugPort		0xff0000
+#define		bCCKDACDebug		0x0f000000
+#define		bCCKFalseAlarmEnable	0x8000
+#define		bCCKFalseAlarmRead	0x4000
+#define		bCCKTRSSI			0x7f
+#define		bCCKRxAGCReport		0xfe
+#define		bCCKRxReport_AntSel	0x80000000
+#define		bCCKRxReport_MFOff	0x40000000
+#define		bCCKRxRxReport_SQLoss	0x20000000
+#define		bCCKRxReport_Pktloss	0x10000000
+#define		bCCKRxReport_Lockedbit	0x08000000
+#define		bCCKRxReport_RateError	0x04000000
+#define		bCCKRxReport_RxRate	0x03000000
+#define		bCCKRxFACounterLower	0xff
+#define		bCCKRxFACounterUpper	0xff000000
+#define		bCCKRxHPAGCStart		0xe000
+#define		bCCKRxHPAGCFinal		0x1c00
+#define		bCCKRxFalseAlarmEnable	0x8000
+#define		bCCKFACounterFreeze	0x4000
+#define		bCCKTxPathSel		0x10000000
+#define		bCCKDefaultRxPath		0xc000000
+#define		bCCKOptionRxPath		0x3000000
+
+/* 5. PageC(0xC00) */
+#define		bNumOfSTF                			0x3	/* Useless */
+#define		bShift_L			0xc0
+#define		bGI_TH			0xc
+#define		bRxPathA			0x1
+#define		bRxPathB			0x2
+#define		bRxPathC			0x4
+#define		bRxPathD			0x8
+#define		bTxPathA			0x1
+#define		bTxPathB			0x2
+#define		bTxPathC			0x4
+#define		bTxPathD			0x8
+#define		bTRSSIFreq			0x200
+#define		bADCBackoff			0x3000
+#define		bDFIRBackoff			0xc000
+#define		bTRSSILatchPhase		0x10000
+#define		bRxIDCOffset			0xff
+#define		bRxQDCOffset		0xff00
+#define		bRxDFIRMode		0x1800000
+#define		bRxDCNFType		0xe000000
+#define		bRXIQImb_A		0x3ff
+#define		bRXIQImb_B			0xfc00
+#define		bRXIQImb_C			0x3f0000
+#define		bRXIQImb_D		0xffc00000
+#define		bDC_dc_Notch		0x60000
+#define		bRxNBINotch		0x1f000000
+#define		bPD_TH			0xf
+#define		bPD_TH_Opt2		0xc000
+#define		bPWED_TH			0x700
+#define		bIfMF_Win_L		0x800
+#define		bPD_Option			0x1000
+#define		bMF_Win_L			0xe000
+#define		bBW_Search_L		0x30000
+#define		bwin_enh_L			0xc0000
+#define		bBW_TH			0x700000
+#define		bED_TH2			0x3800000
+#define		bBW_option			0x4000000
+#define		bRatio_TH			0x18000000
+#define		bWindow_L			0xe0000000
+#define		bSBD_Option		0x1
+#define		bFrame_TH			0x1c
+#define		bFS_Option			0x60
+#define		bDC_Slope_check		0x80
+#define		bFGuard_Counter_DC_L	0xe00
+#define		bFrame_Weight_Short	0x7000
+#define		bSub_Tune			0xe00000
+#define		bFrame_DC_Length		0xe000000
+#define		bSBD_start_offset		0x30000000
+#define		bFrame_TH_2		0x7
+#define		bFrame_GI2_TH		0x38
+#define		bGI2_Sync_en		0x40
+#define		bSarch_Short_Early		0x300
+#define		bSarch_Short_Late		0xc00
+#define		bSarch_GI2_Late		0x70000
+#define		bCFOAntSum		0x1
+#define		bCFOAcc			0x2
+#define		bCFOStartOffset		0xc
+#define		bCFOLookBack		0x70
+#define		bCFOSumWeight		0x80
+#define		bDAGCEnable		0x10000
+#define		bTXIQImb_A			0x3ff
+#define		bTXIQImb_B			0xfc00
+#define		bTXIQImb_C			0x3f0000
+#define		bTXIQImb_D			0xffc00000
+#define		bTxIDCOffset			0xff
+#define		bTxQDCOffset		0xff00
+#define		bTxDFIRMode		0x10000
+#define		bTxPesudoNoiseOn		0x4000000
+#define		bTxPesudoNoise_A		0xff
+#define		bTxPesudoNoise_B		0xff00
+#define		bTxPesudoNoise_C		0xff0000
+#define		bTxPesudoNoise_D		0xff000000
+#define		bCCADropOption		0x20000
+#define		bCCADropThres		0xfff00000
+#define		bEDCCA_H			0xf
+#define		bEDCCA_L			0xf0
+#define		bLambda_ED		0x300
+#define		bRxInitialGain			0x7f
+#define		bRxAntDivEn		0x80
+#define		bRxAGCAddressForLNA	0x7f00
+#define		bRxHighPowerFlow		0x8000
+#define		bRxAGCFreezeThres		0xc0000
+#define		bRxFreezeStep_AGC1	0x300000
+#define		bRxFreezeStep_AGC2	0xc00000
+#define		bRxFreezeStep_AGC3	0x3000000
+#define		bRxFreezeStep_AGC0	0xc000000
+#define		bRxRssi_Cmp_En		0x10000000
+#define		bRxQuickAGCEn		0x20000000
+#define		bRxAGCFreezeThresMode	0x40000000
+#define		bRxOverFlowCheckType	0x80000000
+#define		bRxAGCShift			0x7f
+#define		bTRSW_Tri_Only		0x80
+#define		bPowerThres		0x300
+#define		bRxAGCEn			0x1
+#define		bRxAGCTogetherEn		0x2
+#define		bRxAGCMin		0x4
+#define		bRxHP_Ini			0x7
+#define		bRxHP_TRLNA		0x70
+#define		bRxHP_RSSI			0x700
+#define		bRxHP_BBP1		0x7000
+#define		bRxHP_BBP2		0x70000
+#define		bRxHP_BBP3		0x700000
+#define		bRSSI_H                  			0x7f0000     /* the threshold for high power */
+#define		bRSSI_Gen                			0x7f000000   /* the threshold for ant diversity */
+#define		bRxSettle_TRSW		0x7
+#define		bRxSettle_LNA		0x38
+#define		bRxSettle_RSSI		0x1c0
+#define		bRxSettle_BBP		0xe00
+#define		bRxSettle_RxHP		0x7000
+#define		bRxSettle_AntSW_RSSI	0x38000
+#define		bRxSettle_AntSW		0xc0000
+#define		bRxProcessTime_DAGC	0x300000
+#define		bRxSettle_HSSI		0x400000
+#define		bRxProcessTime_BBPPW	0x800000
+#define		bRxAntennaPowerShift	0x3000000
+#define		bRSSITableSelect		0xc000000
+#define		bRxHP_Final			0x7000000
+#define		bRxHTSettle_BBP		0x7
+#define		bRxHTSettle_HSSI		0x8
+#define		bRxHTSettle_RxHP		0x70
+#define		bRxHTSettle_BBPPW		0x80
+#define		bRxHTSettle_Idle		0x300
+#define		bRxHTSettle_Reserved	0x1c00
+#define		bRxHTRxHPEn		0x8000
+#define		bRxHTAGCFreezeThres	0x30000
+#define		bRxHTAGCTogetherEn	0x40000
+#define		bRxHTAGCMin		0x80000
+#define		bRxHTAGCEn		0x100000
+#define		bRxHTDAGCEn		0x200000
+#define		bRxHTRxHP_BBP		0x1c00000
+#define		bRxHTRxHP_Final		0xe0000000
+#define		bRxPWRatioTH		0x3
+#define		bRxPWRatioEn		0x4
+#define		bRxMFHold			0x3800
+#define		bRxPD_Delay_TH1		0x38
+#define		bRxPD_Delay_TH2		0x1c0
+#define		bRxPD_DC_COUNT_MAX	0x600
+/* #define bRxMF_Hold               0x3800 */
+#define		bRxPD_Delay_TH		0x8000
+#define		bRxProcess_Delay		0xf0000
+#define		bRxSearchrange_GI2_Early	0x700000
+#define		bRxFrame_Guard_Counter_L	0x3800000
+#define		bRxSGI_Guard_L		0xc000000
+#define		bRxSGI_Search_L		0x30000000
+#define		bRxSGI_TH			0xc0000000
+#define		bDFSCnt0			0xff
+#define		bDFSCnt1			0xff00
+#define		bDFSFlag			0xf0000
+#define		bMFWeightSum		0x300000
+#define		bMinIdxTH			0x7f000000
+#define		bDAFormat			0x40000
+#define		bTxChEmuEnable		0x01000000
+#define		bTRSWIsolation_A		0x7f
+#define		bTRSWIsolation_B		0x7f00
+#define		bTRSWIsolation_C		0x7f0000
+#define		bTRSWIsolation_D		0x7f000000
+#define		bExtLNAGain		0x7c00
+
+/* 6. PageE(0xE00) */
+#define		bSTBCEn                  			0x4	/* Useless */
+#define		bAntennaMapping		0x10
+#define		bNss			0x20
+#define		bCFOAntSumD		0x200
+#define		bPHYCounterReset		0x8000000
+#define		bCFOReportGet		0x4000000
+#define		bOFDMContinueTx		0x10000000
+#define		bOFDMSingleCarrier		0x20000000
+#define		bOFDMSingleTone		0x40000000
+/* #define bRxPath1                 0x01 */
+/* #define bRxPath2                 0x02 */
+/* #define bRxPath3                 0x04 */
+/* #define bRxPath4                 0x08 */
+/* #define bTxPath1                 0x10 */
+/* #define bTxPath2                 0x20 */
+#define		bHTDetect			0x100
+#define		bCFOEn			0x10000
+#define		bCFOValue			0xfff00000
+#define		bSigTone_Re			0x3f
+#define		bSigTone_Im			0x7f00
+#define		bCounter_CCA		0xffff
+#define		bCounter_ParityFail		0xffff0000
+#define		bCounter_RateIllegal		0xffff
+#define		bCounter_CRC8Fail		0xffff0000
+#define		bCounter_MCSNoSupport	0xffff
+#define		bCounter_FastSync		0xffff
+#define		bShortCFO			0xfff
+#define		bShortCFOTLength         		12   /* total */
+#define		bShortCFOFLength         		11   /* fraction */
+#define		bLongCFO			0x7ff
+#define		bLongCFOTLength		11
+#define		bLongCFOFLength		11
+#define		bTailCFO			0x1fff
+#define		bTailCFOTLength		13
+#define		bTailCFOFLength		12
+#define		bmax_en_pwdB		0xffff
+#define		bCC_power_dB		0xffff0000
+#define		bnoise_pwdB		0xffff
+#define		bPowerMeasTLength	10
+#define		bPowerMeasFLength	3
+#define		bRx_HT_BW		0x1
+#define		bRxSC			0x6
+#define		bRx_HT			0x8
+#define		bNB_intf_det_on		0x1
+#define		bIntf_win_len_cfg		0x30
+#define		bNB_Intf_TH_cfg		0x1c0
+#define		bRFGain			0x3f
+#define		bTableSel			0x40
+#define		bTRSW			0x80
+#define		bRxSNR_A			0xff
+#define		bRxSNR_B			0xff00
+#define		bRxSNR_C			0xff0000
+#define		bRxSNR_D			0xff000000
+#define		bSNREVMTLength		8
+#define		bSNREVMFLength		1
+#define		bCSI1st			0xff
+#define		bCSI2nd			0xff00
+#define		bRxEVM1st			0xff0000
+#define		bRxEVM2nd		0xff000000
+#define		bSIGEVM			0xff
+#define		bPWDB			0xff00
+#define		bSGIEN			0x10000
+
+#define		bSFactorQAM1             		0xf	/* Useless */
+#define		bSFactorQAM2		0xf0
+#define		bSFactorQAM3		0xf00
+#define		bSFactorQAM4		0xf000
+#define		bSFactorQAM5		0xf0000
+#define		bSFactorQAM6		0xf0000
+#define		bSFactorQAM7		0xf00000
+#define		bSFactorQAM8		0xf000000
+#define		bSFactorQAM9		0xf0000000
+#define		bCSIScheme			0x100000
+
+#define		bNoiseLvlTopSet          		0x3	/* Useless */
+#define		bChSmooth			0x4
+#define		bChSmoothCfg1		0x38
+#define		bChSmoothCfg2		0x1c0
+#define		bChSmoothCfg3		0xe00
+#define		bChSmoothCfg4		0x7000
+#define		bMRCMode		0x800000
+#define		bTHEVMCfg			0x7000000
+
+#define		bLoopFitType             			0x1	/* Useless */
+#define		bUpdCFO			0x40
+#define		bUpdCFOOffData		0x80
+#define		bAdvUpdCFO		0x100
+#define		bAdvTimeCtrl		0x800
+#define		bUpdClko			0x1000
+#define		bFC				0x6000
+#define		bTrackingMode		0x8000
+#define		bPhCmpEnable		0x10000
+#define		bUpdClkoLTF			0x20000
+#define		bComChCFO		0x40000
+#define		bCSIEstiMode		0x80000
+#define		bAdvUpdEqz		0x100000
+#define		bUChCfg			0x7000000
+#define		bUpdEqz			0x8000000
+
+/* Rx Pseduo noise */
+#define		bRxPesudoNoiseOn         		0x20000000	/* Useless */
+#define		bRxPesudoNoise_A		0xff
+#define		bRxPesudoNoise_B		0xff00
+#define		bRxPesudoNoise_C		0xff0000
+#define		bRxPesudoNoise_D		0xff000000
+#define		bPesudoNoiseState_A	0xffff
+#define		bPesudoNoiseState_B	0xffff0000
+#define		bPesudoNoiseState_C		0xffff
+#define		bPesudoNoiseState_D	0xffff0000
+
+/* 7. RF Register
+ * Zebra1 */
+#define		bZebra1_HSSIEnable        		0x8		/* Useless */
+#define		bZebra1_TRxControl		0xc00
+#define		bZebra1_TRxGainSetting	0x07f
+#define		bZebra1_RxCorner		0xc00
+#define		bZebra1_TxChargePump	0x38
+#define		bZebra1_RxChargePump	0x7
+#define		bZebra1_ChannelNum	0xf80
+#define		bZebra1_TxLPFBW		0x400
+#define		bZebra1_RxLPFBW		0x600
+
+/* Zebra4 */
+#define		bRTL8256RegModeCtrl1      	0x100	/* Useless */
+#define		bRTL8256RegModeCtrl0	0x40
+#define		bRTL8256_TxLPFBW	0x18
+#define		bRTL8256_RxLPFBW	0x600
+
+/* RTL8258 */
+#define		bRTL8258_TxLPFBW          	0xc	/* Useless */
+#define		bRTL8258_RxLPFBW	0xc00
+#define		bRTL8258_RSSILPFBW	0xc0
+
+
+/*
+ * Other Definition
+ *   */
+
+/* byte endable for sb_write */
+#define		bByte0                    			0x1	/* Useless */
+#define		bByte1			0x2
+#define		bByte2			0x4
+#define		bByte3			0x8
+#define		bWord0			0x3
+#define		bWord1			0xc
+#define		bDWord			0xf
+
+/* for PutRegsetting & GetRegSetting BitMask */
+#define		bMaskByte0                		0xff	/* Reg 0xc50 rOFDM0_XAAGCCore~0xC6f */
+#define		bMaskByte1		0xff00
+#define		bMaskByte2		0xff0000
+#define		bMaskByte3		0xff000000
+#define		bMaskHWord		0xffff0000
+#define		bMaskLWord		0x0000ffff
+#define		bMaskDWord		0xffffffff
+#define		bMaskH3Bytes				0xffffff00
+#define		bMask12Bits				0xfff
+#define		bMaskH4Bits				0xf0000000
+#define		bMaskOFDM_D			0xffc00000
+#define		bMaskCCK				0x3f3f3f3f
+
+/* for PutRFRegsetting & GetRFRegSetting BitMask
+ * #define		bMask12Bits               0xfffff */	/* RF Reg mask bits
+ * #define		bMask20Bits               0xfffff */	/* RF Reg mask bits T65 RF */
+#define		bRFRegOffsetMask			0xfffff
+
+#define		bEnable                   0x1	/* Useless */
+#define		bDisable                  0x0
+
+#define		LeftAntenna               			0x0	/* Useless */
+#define		RightAntenna		0x1
+
+#define		tCheckTxStatus            		500   /* 500ms */ /* Useless */
+#define		tUpdateRxCounter          		100   /* 100ms */
+
+#define		rateCCK     				0	/* Useless */
+#define		rateOFDM				1
+#define		rateHT					2
+
+/* define Register-End */
+#define		bPMAC_End                 		0x1ff	/* Useless */
+#define		bFPGAPHY0_End		0x8ff
+#define		bFPGAPHY1_End		0x9ff
+#define		bCCKPHY0_End		0xaff
+#define		bOFDMPHY0_End		0xcff
+#define		bOFDMPHY1_End		0xdff
+
+/* define max debug item in each debug page
+ * #define bMaxItem_FPGA_PHY0        0x9
+ * #define bMaxItem_FPGA_PHY1        0x3
+ * #define bMaxItem_PHY_11B          0x16
+ * #define bMaxItem_OFDM_PHY0        0x29
+ * #define bMaxItem_OFDM_PHY1        0x0 */
+
+#define		bPMACControl              		0x0		/* Useless */
+#define		bWMACControl		0x1
+#define		bWNICControl		0x2
+
+#define		PathA                     			0x0	/* Useless */
+#define		PathB			0x1
+#define		PathC			0x2
+#define		PathD			0x3
+
+
+/* RSSI Dump Message */
+#define		rA_RSSIDump_92E			0xcb0
+#define		rB_RSSIDump_92E			0xcb1
+#define		rS1_RXevmDump_92E			0xcb2
+#define		rS2_RXevmDump_92E			0xcb3
+#define		rA_RXsnrDump_92E			0xcb4
+#define		rB_RXsnrDump_92E			0xcb5
+#define		rA_CfoShortDump_92E		0xcb6
+#define		rB_CfoShortDump_92E		0xcb8
+#define	rA_CfoLongDump_92E			0xcba
+#define		rB_CfoLongDump_92E			0xcbc
+
+/*--------------------------Define Parameters-------------------------------*/
+
+
+#endif /* __INC_HAL8188EPHYREG_H */
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/include/Hal8192EPwrSeq.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/Hal8192EPwrSeq.h
--- linux-5.6.3/3rdparty/rtl8821ce/include/Hal8192EPwrSeq.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/Hal8192EPwrSeq.h	2020-04-10 16:35:06.844661375 +0300
@@ -0,0 +1,169 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2012 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#ifndef REALTEK_POWER_SEQUENCE_8192E
+#define REALTEK_POWER_SEQUENCE_8192E
+
+#include "HalPwrSeqCmd.h"
+/*
+	Check document WM-20110607-Paul-RTL8192E_Power_Architecture-R02.vsd
+	There are 6 HW Power States:
+	0: POFF--Power Off
+	1: PDN--Power Down
+	2: CARDEMU--Card Emulation
+	3: ACT--Active Mode
+	4: LPS--Low Power State
+	5: SUS--Suspend
+
+	The transision from different states are defined below
+	TRANS_CARDEMU_TO_ACT
+	TRANS_ACT_TO_CARDEMU
+	TRANS_CARDEMU_TO_SUS
+	TRANS_SUS_TO_CARDEMU
+	TRANS_CARDEMU_TO_PDN
+	TRANS_ACT_TO_LPS
+	TRANS_LPS_TO_ACT
+
+	TRANS_END
+*/
+#define	RTL8192E_TRANS_CARDEMU_TO_ACT_STEPS	18
+#define	RTL8192E_TRANS_ACT_TO_CARDEMU_STEPS	18
+#define	RTL8192E_TRANS_CARDEMU_TO_SUS_STEPS	18
+#define	RTL8192E_TRANS_SUS_TO_CARDEMU_STEPS	18
+#define	RTL8192E_TRANS_CARDEMU_TO_PDN_STEPS	18
+#define	RTL8192E_TRANS_PDN_TO_CARDEMU_STEPS	18
+#define	RTL8192E_TRANS_ACT_TO_LPS_STEPS	23
+#define	RTL8192E_TRANS_LPS_TO_ACT_STEPS	23
+#define	RTL8192E_TRANS_END_STEPS	1
+
+
+#define RTL8192E_TRANS_CARDEMU_TO_ACT														\
+	/* format */																\
+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, 0},/* disable HWPDN 0x04[15]=0*/	\
+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, 0},/* disable SW LPS 0x04[10]=0*/	\
+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, (BIT4 | BIT3), 0},/* disable WL suspend*/	\
+	{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT1, BIT1},/* wait till 0x04[17] = 1    power ready*/	\
+	{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0},/* release WLON reset  0x04[16]=1*/	\
+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0},/* polling until return 0*/	\
+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT0, 0},/**/	\
+
+
+#define RTL8192E_TRANS_ACT_TO_CARDEMU													\
+	/* format */																\
+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
+	{0x001F, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0},/*0x1F[7:0] = 0 turn off RF*/	\
+	{0x004E, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, 0},/*0x4C[23] = 0x4E[7] = 0, switch DPDT_SEL_P output from register 0x65[2] */\
+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1}, /*0x04[9] = 1 turn off MAC by HW state machine*/	\
+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT1, 0}, /*wait till 0x04[9] = 0 polling until return 0 to disable*/	\
+
+
+#define RTL8192E_TRANS_CARDEMU_TO_SUS													\
+	/* format */																\
+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4 | BIT3, (BIT4 | BIT3)}, /*0x04[12:11] = 2b'11 enable WL suspend for PCIe*/	\
+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT4, BIT3}, /*0x04[12:11] = 2b'01 enable WL suspend*/	\
+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT4, BIT3 | BIT4}, /*0x04[12:11] = 2b'11 enable WL suspend for PCIe*/	\
+	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT0, BIT0}, /*Set SDIO suspend local register*/	\
+	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, 0}, /*wait power state to suspend*/
+
+#define RTL8192E_TRANS_SUS_TO_CARDEMU													\
+	/* format */																\
+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
+	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT0, 0}, /*Set SDIO suspend local register*/	\
+	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, BIT1}, /*wait power state to suspend*/\
+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT4, 0}, /*0x04[12:11] = 2b'01enable WL suspend*/
+
+#define RTL8192E_TRANS_CARDEMU_TO_CARDDIS													\
+	/* format */																\
+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
+	{0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x20}, /*0x07 = 0x20 , SOP option to disable BG/MB*/	\
+	{0x00CC, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, BIT2}, /*Unlock small LDO Register*/	\
+	{0x0011, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0}, /*Disable small LDO*/	\
+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT4, BIT3}, /*0x04[12:11] = 2b'01 enable WL suspend*/	\
+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, BIT2}, /*0x04[10] = 1, enable SW LPS*/	\
+	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT0, BIT0}, /*Set SDIO suspend local register*/	\
+	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, 0}, /*wait power state to suspend*/
+
+#define RTL8192E_TRANS_CARDDIS_TO_CARDEMU													\
+	/* format */																\
+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
+	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT0, 0}, /*Set SDIO suspend local register*/	\
+	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, BIT1}, /*wait power state to suspend*/\
+	{0x0011, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0}, /*Enable small LDO*/	\
+	{0x00CC, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, 0}, /*Lock small LDO Register*/	\
+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT4, 0}, /*0x04[12:11] = 2b'01enable WL suspend*/\
+
+
+#define RTL8192E_TRANS_CARDEMU_TO_PDN												\
+	/* format */																\
+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
+	{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0},/* 0x04[16] = 0*/\
+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, BIT7},/* 0x04[15] = 1*/
+
+#define RTL8192E_TRANS_PDN_TO_CARDEMU												\
+	/* format */																\
+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, 0},/* 0x04[15] = 0*/
+
+#define RTL8192E_TRANS_ACT_TO_LPS														\
+	/* format */																\
+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
+	{0x0301, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF},/*PCIe DMA stop*/	\
+	{0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF},/*Tx Pause*/	\
+	{0x05F8, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/	\
+	{0x05F9, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/	\
+	{0x05FA, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/	\
+	{0x05FB, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/	\
+	{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0},/*CCK and OFDM are disabled, and clock are gated*/	\
+	{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_US},/*Delay 1us*/	\
+	{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0},/*Whole BB is reset*/	\
+	{0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x03},/*Reset MAC TRX*/	\
+	{0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0},/*check if removed later*/	\
+	{0x0093, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x00},/*When driver enter Sus/ Disable, enable LOP for BT*/	\
+	{0x0553, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT5, BIT5},/*Respond TxOK to scheduler*/	\
+
+
+#define RTL8192E_TRANS_LPS_TO_ACT															\
+	/* format */																\
+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
+	{0x0080, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, 0xFF, 0x84}, /*SDIO RPWM, For Repeatly In and out, Taggle bit should be changed*/\
+	{0xFE58, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x84}, /*USB RPWM*/\
+	{0x0361, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x84}, /*PCIe RPWM*/\
+	{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_MS}, /*Delay*/\
+	{0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0}, /*.	0x08[4] = 0		 switch TSF to 40M*/\
+	{0x0109, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT7, 0}, /*Polling 0x109[7]=0  TSF in 40M*/\
+	{0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1}, /*.	0x101[1] = 1*/\
+	{0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF}, /*.	0x100[7:0] = 0xFF	 enable WMAC TRX*/\
+	{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1 | BIT0, BIT1 | BIT0}, /*.	0x02[1:0] = 2b'11	 enable BB macro*/\
+	{0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0}, /*.	0x522 = 0*/\
+	{0x013D, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF}, /*Clear ISR*/
+
+#define RTL8192E_TRANS_END															\
+	/* format */																\
+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
+	{0xFFFF, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, 0, PWR_CMD_END, 0, 0},
+
+
+	extern WLAN_PWR_CFG rtl8192E_power_on_flow[RTL8192E_TRANS_CARDEMU_TO_ACT_STEPS + RTL8192E_TRANS_END_STEPS];
+	extern WLAN_PWR_CFG rtl8192E_radio_off_flow[RTL8192E_TRANS_ACT_TO_CARDEMU_STEPS + RTL8192E_TRANS_END_STEPS];
+	extern WLAN_PWR_CFG rtl8192E_card_disable_flow[RTL8192E_TRANS_ACT_TO_CARDEMU_STEPS + RTL8192E_TRANS_CARDEMU_TO_PDN_STEPS + RTL8192E_TRANS_END_STEPS];
+	extern WLAN_PWR_CFG rtl8192E_card_enable_flow[RTL8192E_TRANS_ACT_TO_CARDEMU_STEPS + RTL8192E_TRANS_CARDEMU_TO_PDN_STEPS + RTL8192E_TRANS_END_STEPS];
+	extern WLAN_PWR_CFG rtl8192E_suspend_flow[RTL8192E_TRANS_ACT_TO_CARDEMU_STEPS + RTL8192E_TRANS_CARDEMU_TO_SUS_STEPS + RTL8192E_TRANS_END_STEPS];
+	extern WLAN_PWR_CFG rtl8192E_resume_flow[RTL8192E_TRANS_ACT_TO_CARDEMU_STEPS + RTL8192E_TRANS_CARDEMU_TO_SUS_STEPS + RTL8192E_TRANS_END_STEPS];
+	extern WLAN_PWR_CFG rtl8192E_hwpdn_flow[RTL8192E_TRANS_ACT_TO_CARDEMU_STEPS + RTL8192E_TRANS_CARDEMU_TO_PDN_STEPS + RTL8192E_TRANS_END_STEPS];
+	extern WLAN_PWR_CFG rtl8192E_enter_lps_flow[RTL8192E_TRANS_ACT_TO_LPS_STEPS + RTL8192E_TRANS_END_STEPS];
+	extern WLAN_PWR_CFG rtl8192E_leave_lps_flow[RTL8192E_TRANS_LPS_TO_ACT_STEPS + RTL8192E_TRANS_END_STEPS];
+
+#endif
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/include/Hal8192FPhyCfg.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/Hal8192FPhyCfg.h
--- linux-5.6.3/3rdparty/rtl8821ce/include/Hal8192FPhyCfg.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/Hal8192FPhyCfg.h	2020-04-10 16:35:06.844661375 +0300
@@ -0,0 +1,131 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#ifndef __INC_HAL8192FPHYCFG_H__
+#define __INC_HAL8192FPHYCFG_H__
+
+/*--------------------------Define Parameters-------------------------------*/
+#define LOOP_LIMIT				5
+#define MAX_STALL_TIME			50		/* us */
+#define AntennaDiversityValue	0x80	/* (Adapter->bSoftwareAntennaDiversity ? 0x00 : 0x80) */
+#define MAX_TXPWR_IDX_NMODE_92S	63
+#define Reset_Cnt_Limit			3
+
+#ifdef CONFIG_PCI_HCI
+	#define MAX_AGGR_NUM	0x0B
+#else
+	#define MAX_AGGR_NUM	0x07
+#endif /* CONFIG_PCI_HCI */
+
+
+/*--------------------------Define Parameters End-------------------------------*/
+
+
+/*------------------------------Define structure----------------------------*/
+
+/*------------------------------Define structure End----------------------------*/
+
+/*--------------------------Exported Function prototype---------------------*/
+u32
+PHY_QueryBBReg_8192F(
+	IN	PADAPTER	Adapter,
+	IN	u32		RegAddr,
+	IN	u32		BitMask
+);
+
+VOID
+PHY_SetBBReg_8192F(
+	IN	PADAPTER	Adapter,
+	IN	u32		RegAddr,
+	IN	u32		BitMask,
+	IN	u32		Data
+);
+
+u32
+PHY_QueryRFReg_8192F(
+	IN	PADAPTER		Adapter,
+	IN	enum rf_path		eRFPath,
+	IN	u32				RegAddr,
+	IN	u32				BitMask
+);
+
+VOID
+PHY_SetRFReg_8192F(
+	IN	PADAPTER		Adapter,
+	IN	enum rf_path		eRFPath,
+	IN	u32				RegAddr,
+	IN	u32				BitMask,
+	IN	u32				Data
+);
+
+/* MAC/BB/RF HAL config */
+int PHY_BBConfig8192F(PADAPTER	Adapter	);
+
+int PHY_RFConfig8192F(PADAPTER	Adapter);
+
+s32 PHY_MACConfig8192F(PADAPTER padapter);
+
+int
+PHY_ConfigRFWithParaFile_8192F(
+	IN	PADAPTER			Adapter,
+	IN	u8				*pFileName,
+	enum rf_path				eRFPath
+);
+
+VOID
+PHY_SetTxPowerIndex_8192F(
+	IN	PADAPTER			Adapter,
+	IN	u32					PowerIndex,
+	IN	enum rf_path			RFPath,
+	IN	u8					Rate
+);
+
+u8
+PHY_GetTxPowerIndex_8192F(
+	IN	PADAPTER			pAdapter,
+	IN	enum rf_path			RFPath,
+	IN	u8					Rate,
+	IN	u8					BandWidth,
+	IN	u8					Channel,
+	struct txpwr_idx_comp *tic
+);
+
+VOID
+PHY_GetTxPowerLevel8192F(			
+	IN	PADAPTER		Adapter,
+	OUT s32				*powerlevel
+);
+
+VOID
+PHY_SetTxPowerLevel8192F(
+	IN	PADAPTER		Adapter,
+	IN	u8			channel
+);
+
+VOID
+PHY_SetSwChnlBWMode8192F(
+	IN	PADAPTER			Adapter,
+	IN	u8					channel,
+	IN	enum channel_width	Bandwidth,
+	IN	u8					Offset40,
+	IN	u8					Offset80
+);
+
+VOID phy_set_rf_path_switch_8192f(
+	IN	PADAPTER	pAdapter,
+	IN	bool		bMain
+);
+/*--------------------------Exported Function prototype End---------------------*/
+
+#endif
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/include/Hal8192FPhyReg.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/Hal8192FPhyReg.h
--- linux-5.6.3/3rdparty/rtl8821ce/include/Hal8192FPhyReg.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/Hal8192FPhyReg.h	2020-04-10 16:35:06.844661375 +0300
@@ -0,0 +1,1134 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#ifndef __INC_HAL8192FPHYREG_H__
+#define __INC_HAL8192FPHYREG_H__
+
+#define		rSYM_WLBT_PAPE_SEL		0x64
+/*
+ * BB-PHY register PMAC 0x100 PHY 0x800 - 0xEFF
+ * 1. PMAC duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF
+ * 2. 0x800/0x900/0xA00/0xC00/0xD00/0xE00
+ * 3. RF register 0x00-2E
+ * 4. Bit Mask for BB/RF register
+ * 5. Other definition for BB/RF R/W
+ *   */
+
+
+/*
+ * 1. PMAC duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF
+ * 1. Page1(0x100)
+ *   */
+#define		rPMAC_Reset					0x100
+#define		rPMAC_TxStart					0x104
+#define		rPMAC_TxLegacySIG				0x108
+#define		rPMAC_TxHTSIG1				0x10c
+#define		rPMAC_TxHTSIG2				0x110
+#define		rPMAC_PHYDebug				0x114
+#define		rPMAC_TxPacketNum				0x118
+#define		rPMAC_TxIdle					0x11c
+#define		rPMAC_TxMACHeader0			0x120
+#define		rPMAC_TxMACHeader1			0x124
+#define		rPMAC_TxMACHeader2			0x128
+#define		rPMAC_TxMACHeader3			0x12c
+#define		rPMAC_TxMACHeader4			0x130
+#define		rPMAC_TxMACHeader5			0x134
+#define		rPMAC_TxDataType				0x138
+#define		rPMAC_TxRandomSeed			0x13c
+#define		rPMAC_CCKPLCPPreamble			0x140
+#define		rPMAC_CCKPLCPHeader			0x144
+#define		rPMAC_CCKCRC16				0x148
+#define		rPMAC_OFDMRxCRC32OK			0x170
+#define		rPMAC_OFDMRxCRC32Er			0x174
+#define		rPMAC_OFDMRxParityEr			0x178
+#define		rPMAC_OFDMRxCRC8Er			0x17c
+#define		rPMAC_CCKCRxRC16Er			0x180
+#define		rPMAC_CCKCRxRC32Er			0x184
+#define		rPMAC_CCKCRxRC32OK			0x188
+#define		rPMAC_TxStatus					0x18c
+
+/*
+ * 2. Page2(0x200)
+ *
+ * The following two definition are only used for USB interface. */
+#define		RF_BB_CMD_ADDR				0x02c0	/* RF/BB read/write command address. */
+#define		RF_BB_CMD_DATA				0x02c4	/* RF/BB read/write command data. */
+
+/*
+ * 3. Page8(0x800)
+ *   */
+#define		rFPGA0_RFMOD				0x800	/* RF mode & CCK TxSC // RF BW Setting?? */
+
+#define		rFPGA0_TxInfo				0x804	/* Status report?? */
+#define		rFPGA0_PSDFunction			0x808
+
+#define		rFPGA0_TxGainStage			0x80c	/* Set TX PWR init gain? */
+
+#define		rFPGA0_RFTiming1			0x810	/* Useless now */
+#define		rFPGA0_RFTiming2			0x814
+
+#define		rFPGA0_XA_HSSIParameter1		0x820	/* RF 3 wire register */
+#define		rFPGA0_XA_HSSIParameter2		0x824
+#define		rFPGA0_XB_HSSIParameter1		0x828
+#define		rFPGA0_XB_HSSIParameter2		0x82c
+#define		rTxAGC_B_Rate18_06				0x830
+#define		rTxAGC_B_Rate54_24				0x834
+#define		rTxAGC_B_CCK1_55_Mcs32		0x838
+#define		rTxAGC_B_Mcs03_Mcs00			0x83c
+
+#define		rTxAGC_B_Mcs07_Mcs04			0x848
+#define		rTxAGC_B_Mcs11_Mcs08			0x84c
+
+#define		rFPGA0_XA_LSSIParameter		0x840
+#define		rFPGA0_XB_LSSIParameter		0x844
+
+#define		rFPGA0_RFWakeUpParameter		0x850	/* Useless now */
+#define		rFPGA0_RFSleepUpParameter		0x854
+
+#define		rFPGA0_XAB_SwitchControl		0x858	/* RF Channel switch */
+#define		rFPGA0_XCD_SwitchControl		0x85c
+
+#define		rFPGA0_XA_RFInterfaceOE		0x860	/* RF Channel switch */
+#define		rFPGA0_XB_RFInterfaceOE		0x864
+
+#define		rTxAGC_B_Mcs15_Mcs12			0x868
+#define		rTxAGC_B_CCK11_A_CCK2_11		0x86c
+
+#define		rFPGA0_XAB_RFInterfaceSW		0x870	/* RF Interface Software Control */
+#define		rFPGA0_XCD_RFInterfaceSW		0x874
+
+#define		rFPGA0_XAB_RFParameter		0x878	/* RF Parameter */
+#define		rFPGA0_XCD_RFParameter		0x87c
+
+#define		rFPGA0_AnalogParameter1		0x880	/* Crystal cap setting RF-R/W protection for parameter4?? */
+#define		rFPGA0_AnalogParameter2		0x884
+#define		rFPGA0_AnalogParameter3		0x888	/* Useless now */
+#define		rFPGA0_AnalogParameter4		0x88c
+
+#define		rFPGA0_XA_LSSIReadBack		0x8a0	/* Tranceiver LSSI Readback */
+#define		rFPGA0_XB_LSSIReadBack		0x8a4
+#define		rFPGA0_XC_LSSIReadBack		0x8a8
+#define		rFPGA0_XD_LSSIReadBack		0x8ac
+
+#define		rFPGA0_PSDReport				0x8b4	/* Useless now */
+#define		TransceiverA_HSPI_Readback	0x8b8	/* Transceiver A HSPI Readback */
+#define		TransceiverB_HSPI_Readback	0x8bc	/* Transceiver B HSPI Readback */
+#define		rFPGA0_XAB_RFInterfaceRB		0x8e0	/* Useless now // RF Interface Readback Value */
+#define		rFPGA0_XCD_RFInterfaceRB		0x8e4	/* Useless now */
+
+/*
+ * 4. Page9(0x900)
+ *   */
+#define	rFPGA1_RFMOD				0x900	/* RF mode & OFDM TxSC // RF BW Setting?? */
+#define	rFPGA1_TxBlock				0x904	/* Useless now */
+#define	rFPGA1_DebugSelect			0x908	/* Useless now */
+#define	rFPGA1_TxInfo				0x90c	/* Useless now // Status report?? */
+#define	rDPDT_control				0x92c
+#define	rfe_ctrl_anta_src				0x930
+#define	rS0S1_PathSwitch			0x948
+#define	rBBrx_DFIR					0x954
+
+/*
+ * 5. PageA(0xA00)
+ *
+ * Set Control channel to upper or lower. These settings are required only for 40MHz */
+#define		rCCK0_System				0xa00
+
+#define		rCCK0_AFESetting			0xa04	/* Disable init gain now // Select RX path by RSSI */
+#define		rCCK0_CCA					0xa08	/* Disable init gain now // Init gain */
+
+#define		rCCK0_RxAGC1				0xa0c	/* AGC default value, saturation level // Antenna Diversity, RX AGC, LNA Threshold, RX LNA Threshold useless now. Not the same as 90 series */
+#define		rCCK0_RxAGC2				0xa10	/* AGC & DAGC */
+
+#define		rCCK0_RxHP					0xa14
+
+#define		rCCK0_DSPParameter1		0xa18	/* Timing recovery & Channel estimation threshold */
+#define		rCCK0_DSPParameter2		0xa1c	/* SQ threshold */
+
+#define		rCCK0_TxFilter1				0xa20
+#define		rCCK0_TxFilter2				0xa24
+#define		rCCK0_DebugPort			0xa28	/* debug port and Tx filter3 */
+#define		rCCK0_FalseAlarmReport		0xa2c	/* 0xa2d	useless now 0xa30-a4f channel report */
+#define		rCCK0_TRSSIReport		0xa50
+#define		rCCK0_RxReport			0xa54  /* 0xa57 */
+#define		rCCK0_FACounterLower		0xa5c  /* 0xa5b */
+#define		rCCK0_FACounterUpper		0xa58  /* 0xa5c */
+
+/*
+ * PageB(0xB00)
+ *   */
+#define rPdp_AntA						0xb00
+#define rPdp_AntA_4						0xb04
+#define rPdp_AntA_8						0xb08
+#define rPdp_AntA_C						0xb0c
+#define rPdp_AntA_10					0xb10
+#define rPdp_AntA_14					0xb14
+#define rPdp_AntA_18					0xb18
+#define rPdp_AntA_1C					0xb1c
+#define rPdp_AntA_20					0xb20
+#define rPdp_AntA_24					0xb24
+
+#define rConfig_Pmpd_AntA				0xb28
+#define rConfig_ram64x16				0xb2c
+
+#define rBndA							0xb30
+#define rHssiPar						0xb34
+
+#define rConfig_AntA					0xb68
+#define rConfig_AntB					0xb6c
+
+#define rPdp_AntB						0xb70
+#define rPdp_AntB_4						0xb74
+#define rPdp_AntB_8						0xb78
+#define rPdp_AntB_C						0xb7c
+#define rPdp_AntB_10					0xb80
+#define rPdp_AntB_14					0xb84
+#define rPdp_AntB_18					0xb88
+#define rPdp_AntB_1C					0xb8c
+#define rPdp_AntB_20					0xb90
+#define rPdp_AntB_24					0xb94
+
+#define rConfig_Pmpd_AntB				0xb98
+
+#define rBndB							0xba0
+
+#define rAPK							0xbd8
+#define rPm_Rx0_AntA					0xbdc
+#define rPm_Rx1_AntA					0xbe0
+#define rPm_Rx2_AntA					0xbe4
+#define rPm_Rx3_AntA					0xbe8
+#define rPm_Rx0_AntB					0xbec
+#define rPm_Rx1_AntB					0xbf0
+#define rPm_Rx2_AntB					0xbf4
+#define rPm_Rx3_AntB					0xbf8
+/*
+ * 6. PageC(0xC00)
+ *   */
+#define		rOFDM0_LSTF				0xc00
+
+#define		rOFDM0_TRxPathEnable		0xc04
+#define		rOFDM0_TRMuxPar			0xc08
+#define		rOFDM0_TRSWIsolation		0xc0c
+
+#define		rOFDM0_XARxAFE			0xc10  /* RxIQ DC offset, Rx digital filter, DC notch filter */
+#define		rOFDM0_XARxIQImbalance		0xc14  /* RxIQ imbalance matrix */
+#define		rOFDM0_XBRxAFE		0xc18
+#define		rOFDM0_XBRxIQImbalance	0xc1c
+#define		rOFDM0_XCRxAFE		0xc20
+#define		rOFDM0_XCRxIQImbalance	0xc24
+#define		rOFDM0_XDRxAFE		0xc28
+#define		rOFDM0_XDRxIQImbalance	0xc2c
+
+#define		rOFDM0_RxDetector1			0xc30  /* PD, BW & SBD	// DM tune init gain */
+#define		rOFDM0_RxDetector2			0xc34  /* SBD & Fame Sync. */
+#define		rOFDM0_RxDetector3			0xc38  /* Frame Sync. */
+#define		rOFDM0_RxDetector4			0xc3c  /* PD, SBD, Frame Sync & Short-GI */
+
+#define		rOFDM0_RxDSP				0xc40  /* Rx Sync Path */
+#define		rOFDM0_CFOandDAGC		0xc44  /* CFO & DAGC */
+#define		rOFDM0_CCADropThreshold	0xc48 /* CCA Drop threshold */
+#define		rOFDM0_ECCAThreshold		0xc4c /* energy CCA */
+
+#define		rOFDM0_XAAGCCore1			0xc50	/* DIG */
+#define		rOFDM0_XAAGCCore2			0xc54
+#define		rOFDM0_XBAGCCore1			0xc58
+#define		rOFDM0_XBAGCCore2			0xc5c
+#define		rOFDM0_XCAGCCore1			0xc60
+#define		rOFDM0_XCAGCCore2			0xc64
+#define		rOFDM0_XDAGCCore1			0xc68
+#define		rOFDM0_XDAGCCore2			0xc6c
+
+#define		rOFDM0_AGCParameter1			0xc70
+#define		rOFDM0_AGCParameter2			0xc74
+#define		rOFDM0_AGCRSSITable			0xc78
+#define		rOFDM0_HTSTFAGC				0xc7c
+
+#define		rOFDM0_XATxIQImbalance		0xc80	/* TX PWR TRACK and DIG */
+#define		rOFDM0_XATxAFE				0xc84
+#define		rOFDM0_XBTxIQImbalance		0xc88
+#define		rOFDM0_XBTxAFE				0xc8c
+#define		rOFDM0_XCTxIQImbalance		0xc90
+#define		rOFDM0_XCTxAFE			0xc94
+#define		rOFDM0_XDTxIQImbalance		0xc98
+#define		rOFDM0_XDTxAFE				0xc9c
+
+#define		rOFDM0_RxIQExtAnta			0xca0
+#define		rOFDM0_TxCoeff1				0xca4
+#define		rOFDM0_TxCoeff2				0xca8
+#define		rOFDM0_TxCoeff3				0xcac
+#define		rOFDM0_TxCoeff4				0xcb0
+#define		rOFDM0_TxCoeff5				0xcb4
+#define		rOFDM0_TxCoeff6				0xcb8
+#define		rOFDM0_RxHPParameter			0xce0
+#define		rOFDM0_TxPseudoNoiseWgt		0xce4
+#define		rOFDM0_FrameSync				0xcf0
+#define		rOFDM0_DFSReport				0xcf4
+
+/*
+ * 7. PageD(0xD00)
+ *   */
+#define		rOFDM1_LSTF					0xd00
+#define		rOFDM1_TRxPathEnable			0xd04
+
+#define		rOFDM1_CFO						0xd08	/* No setting now */
+#define		rOFDM1_CSI1					0xd10
+#define		rOFDM1_SBD						0xd14
+#define		rOFDM1_CSI2					0xd18
+#define		rOFDM1_CFOTracking			0xd2c
+#define		rOFDM1_TRxMesaure1			0xd34
+#define		rOFDM1_IntfDet					0xd3c
+#define		rOFDM1_PseudoNoiseStateAB		0xd50
+#define		rOFDM1_PseudoNoiseStateCD		0xd54
+#define		rOFDM1_RxPseudoNoiseWgt		0xd58
+
+#define		rOFDM_PHYCounter1				0xda0  /* cca, parity fail */
+#define		rOFDM_PHYCounter2				0xda4  /* rate illegal, crc8 fail */
+#define		rOFDM_PHYCounter3				0xda8  /* MCS not support */
+
+#define		rOFDM_ShortCFOAB				0xdac	/* No setting now */
+#define		rOFDM_ShortCFOCD				0xdb0
+#define		rOFDM_LongCFOAB				0xdb4
+#define		rOFDM_LongCFOCD				0xdb8
+#define		rOFDM_TailCFOAB				0xdbc
+#define		rOFDM_TailCFOCD				0xdc0
+#define		rOFDM_PWMeasure1		0xdc4
+#define		rOFDM_PWMeasure2		0xdc8
+#define		rOFDM_BWReport				0xdcc
+#define		rOFDM_AGCReport				0xdd0
+#define		rOFDM_RxSNR					0xdd4
+#define		rOFDM_RxEVMCSI				0xdd8
+#define		rOFDM_SIGReport				0xddc
+
+
+/*
+ * 8. PageE(0xE00)
+ *   */
+#define		rTxAGC_A_Rate18_06			0xe00
+#define		rTxAGC_A_Rate54_24			0xe04
+#define		rTxAGC_A_CCK1_Mcs32			0xe08
+#define		rTxAGC_A_Mcs03_Mcs00			0xe10
+#define		rTxAGC_A_Mcs07_Mcs04			0xe14
+#define		rTxAGC_A_Mcs11_Mcs08			0xe18
+#define		rTxAGC_A_Mcs15_Mcs12			0xe1c
+
+#define		rFPGA0_IQK					0xe28
+#define		rTx_IQK_Tone_A				0xe30
+#define		rRx_IQK_Tone_A				0xe34
+#define		rTx_IQK_PI_A					0xe38
+#define		rRx_IQK_PI_A					0xe3c
+
+#define		rTx_IQK						0xe40
+#define		rRx_IQK						0xe44
+#define		rIQK_AGC_Pts					0xe48
+#define		rIQK_AGC_Rsp					0xe4c
+#define		rTx_IQK_Tone_B				0xe50
+#define		rRx_IQK_Tone_B				0xe54
+#define		rTx_IQK_PI_B					0xe58
+#define		rRx_IQK_PI_B					0xe5c
+#define		rIQK_AGC_Cont				0xe60
+
+#define		rBlue_Tooth					0xe6c
+#define		rRx_Wait_CCA					0xe70
+#define		rTx_CCK_RFON					0xe74
+#define		rTx_CCK_BBON				0xe78
+#define		rTx_OFDM_RFON				0xe7c
+#define		rTx_OFDM_BBON				0xe80
+#define		rTx_To_Rx					0xe84
+#define		rTx_To_Tx					0xe88
+#define		rRx_CCK						0xe8c
+
+#define		rTx_Power_Before_IQK_A		0xe94
+#define		rTx_Power_After_IQK_A			0xe9c
+
+#define		rRx_Power_Before_IQK_A		0xea0
+#define		rRx_Power_Before_IQK_A_2		0xea4
+#define		rRx_Power_After_IQK_A			0xea8
+#define		rRx_Power_After_IQK_A_2		0xeac
+
+#define		rTx_Power_Before_IQK_B		0xeb4
+#define		rTx_Power_After_IQK_B			0xebc
+
+#define		rRx_Power_Before_IQK_B		0xec0
+#define		rRx_Power_Before_IQK_B_2		0xec4
+#define		rRx_Power_After_IQK_B			0xec8
+#define		rRx_Power_After_IQK_B_2		0xecc
+
+#define		rRx_OFDM					0xed0
+#define		rRx_Wait_RIFS				0xed4
+#define		rRx_TO_Rx					0xed8
+#define		rStandby						0xedc
+#define		rSleep						0xee0
+#define		rPMPD_ANAEN				0xeec
+
+/*
+ * 7. RF Register 0x00-0x2E (RF 8256)
+ * RF-0222D 0x00-3F
+ *
+ * Zebra1 */
+#define		rZebra1_HSSIEnable				0x0	/* Useless now */
+#define		rZebra1_TRxEnable1				0x1
+#define		rZebra1_TRxEnable2				0x2
+#define		rZebra1_AGC					0x4
+#define		rZebra1_ChargePump			0x5
+#define		rZebra1_Channel				0x7	/* RF channel switch */
+
+/* #endif */
+#define		rZebra1_TxGain					0x8	/* Useless now */
+#define		rZebra1_TxLPF					0x9
+#define		rZebra1_RxLPF					0xb
+#define		rZebra1_RxHPFCorner			0xc
+
+/* Zebra4 */
+#define		rGlobalCtrl						0	/* Useless now */
+#define		rRTL8256_TxLPF					19
+#define		rRTL8256_RxLPF					11
+
+/* RTL8258 */
+#define		rRTL8258_TxLPF					0x11	/* Useless now */
+#define		rRTL8258_RxLPF					0x13
+#define		rRTL8258_RSSILPF				0xa
+
+/*
+ * RL6052 Register definition
+ *   */
+#define		RF_AC						0x00	/* */
+
+#define		RF_IQADJ_G1				0x01	/* */
+#define		RF_IQADJ_G2				0x02	/* */
+#define		RF_BS_PA_APSET_G1_G4		0x03
+#define		RF_BS_PA_APSET_G5_G8		0x04
+#define		RF_POW_TRSW				0x05	/* */
+
+#define		RF_GAIN_RX					0x06	/* */
+#define		RF_GAIN_TX					0x07	/* */
+
+#define		RF_TXM_IDAC				0x08	/* */
+#define		RF_IPA_G					0x09	/* */
+#define		RF_TXBIAS_G				0x0A
+#define		RF_TXPA_AG					0x0B
+#define		RF_IPA_A					0x0C	/* */
+#define		RF_TXBIAS_A				0x0D
+#define		RF_BS_PA_APSET_G9_G11	0x0E
+#define		RF_BS_IQGEN				0x0F	/* */
+
+#define		RF_MODE1					0x10	/* */
+#define		RF_MODE2					0x11	/* */
+
+#define		RF_RX_AGC_HP				0x12	/* */
+#define		RF_TX_AGC					0x13	/* */
+#define		RF_BIAS						0x14	/* */
+#define		RF_IPA						0x15	/* */
+#define		RF_TXBIAS					0x16
+#define		RF_POW_ABILITY			0x17	/* */
+#define		RF_MODE_AG				0x18	/* */
+#define		rRfChannel					0x18	/* RF channel and BW switch */
+#define		RF_CHNLBW					0x18	/* RF channel and BW switch */
+#define		RF_TOP						0x19	/* */
+
+#define		RF_RX_G1					0x1A	/* */
+#define		RF_RX_G2					0x1B	/* */
+
+#define		RF_RX_BB2					0x1C	/* */
+#define		RF_RX_BB1					0x1D	/* */
+
+#define		RF_RCK1					0x1E	/* */
+#define		RF_RCK2					0x1F	/* */
+
+#define		RF_TX_G1					0x20	/* */
+#define		RF_TX_G2					0x21	/* */
+#define		RF_TX_G3					0x22	/* */
+
+#define		RF_TX_BB1					0x23	/* */
+
+#define		RF_T_METER					0x24	/* */
+
+#define		RF_SYN_G1					0x25	/* RF TX Power control */
+#define		RF_SYN_G2					0x26	/* RF TX Power control */
+#define		RF_SYN_G3					0x27	/* RF TX Power control */
+#define		RF_SYN_G4					0x28	/* RF TX Power control */
+#define		RF_SYN_G5					0x29	/* RF TX Power control */
+#define		RF_SYN_G6					0x2A	/* RF TX Power control */
+#define		RF_SYN_G7					0x2B	/* RF TX Power control */
+#define		RF_SYN_G8					0x2C	/* RF TX Power control */
+
+#define		RF_RCK_OS					0x30	/* RF TX PA control */
+
+#define		RF_TXPA_G1					0x31	/* RF TX PA control */
+#define		RF_TXPA_G2					0x32	/* RF TX PA control */
+#define		RF_TXPA_G3					0x33	/* RF TX PA control */
+#define	RF_TX_BIAS_A				0x35
+#define	RF_TX_BIAS_D				0x36
+#define	RF_LOBF_9					0x38
+#define	RF_RXRF_A3					0x3C	/*	 */
+#define	RF_TRSW					0x3F
+
+#define	RF_TXRF_A2					0x41
+#define	RF_T_METER_88E				0x42
+#define	RF_TXPA_G4					0x46
+#define	RF_TXPA_A4					0x4B
+#define	RF_0x52					0x52
+#define	RF_WE_LUT					0xEF
+#define	RF_S0S1					0xB0
+
+/*
+ * Bit Mask
+ *
+ * 1. Page1(0x100) */
+#define		bBBResetB						0x100	/* Useless now? */
+#define		bGlobalResetB					0x200
+#define		bOFDMTxStart					0x4
+#define		bCCKTxStart						0x8
+#define		bCRC32Debug					0x100
+#define		bPMACLoopback					0x10
+#define		bTxLSIG							0xffffff
+#define		bOFDMTxRate					0xf
+#define		bOFDMTxReserved				0x10
+#define		bOFDMTxLength					0x1ffe0
+#define		bOFDMTxParity					0x20000
+#define		bTxHTSIG1						0xffffff
+#define		bTxHTMCSRate					0x7f
+#define		bTxHTBW						0x80
+#define		bTxHTLength					0xffff00
+#define		bTxHTSIG2						0xffffff
+#define		bTxHTSmoothing					0x1
+#define		bTxHTSounding					0x2
+#define		bTxHTReserved					0x4
+#define		bTxHTAggreation				0x8
+#define		bTxHTSTBC						0x30
+#define		bTxHTAdvanceCoding			0x40
+#define		bTxHTShortGI					0x80
+#define		bTxHTNumberHT_LTF			0x300
+#define		bTxHTCRC8						0x3fc00
+#define		bCounterReset					0x10000
+#define		bNumOfOFDMTx					0xffff
+#define		bNumOfCCKTx					0xffff0000
+#define		bTxIdleInterval					0xffff
+#define		bOFDMService					0xffff0000
+#define		bTxMACHeader					0xffffffff
+#define		bTxDataInit						0xff
+#define		bTxHTMode						0x100
+#define		bTxDataType					0x30000
+#define		bTxRandomSeed					0xffffffff
+#define		bCCKTxPreamble					0x1
+#define		bCCKTxSFD						0xffff0000
+#define		bCCKTxSIG						0xff
+#define		bCCKTxService					0xff00
+#define		bCCKLengthExt					0x8000
+#define		bCCKTxLength					0xffff0000
+#define		bCCKTxCRC16					0xffff
+#define		bCCKTxStatus					0x1
+#define		bOFDMTxStatus					0x2
+
+#define		IS_BB_REG_OFFSET_92S(_Offset)		((_Offset >= 0x800) && (_Offset <= 0xfff))
+#define		RF_TX_GAIN_OFFSET_8192F(_val) (abs((_val)) | (((_val) > 0) ? BIT(4) : 0))
+
+/* 2. Page8(0x800) */
+#define		bRFMOD							0x1	/* Reg 0x800 rFPGA0_RFMOD */
+#define		bJapanMode						0x2
+#define		bCCKTxSC						0x30
+#define		bCCKEn							0x1000000
+#define		bOFDMEn						0x2000000
+
+#define		bOFDMRxADCPhase           0x10000	/* Useless now */
+#define		bOFDMTxDACPhase		0x40000
+#define		bXATxAGC			0x3f
+
+#define		bAntennaSelect		0x0300
+
+#define		bXBTxAGC                 0xf00	/* Reg 80c rFPGA0_TxGainStage */
+#define		bXCTxAGC			0xf000
+#define		bXDTxAGC			0xf0000
+
+#define		bPAStart                 0xf0000000	/* Useless now */
+#define		bTRStart			0x00f00000
+#define		bRFStart			0x0000f000
+#define		bBBStart			0x000000f0
+#define		bBBCCKStart		0x0000000f
+#define		bPAEnd                    0xf          /* Reg0x814 */
+#define		bTREnd			0x0f000000
+#define		bRFEnd			0x000f0000
+#define		bCCAMask                  0x000000f0   /* T2R */
+#define		bR2RCCAMask		0x00000f00
+#define		bHSSI_R2TDelay		0xf8000000
+#define		bHSSI_T2RDelay		0xf80000
+#define		bContTxHSSI              0x400     /* chane gain at continue Tx */
+#define		bIGFromCCK		0x200
+#define		bAGCAddress		0x3f
+#define		bRxHPTx			0x7000
+#define		bRxHPT2R			0x38000
+#define		bRxHPCCKIni		0xc0000
+#define		bAGCTxCode		0xc00000
+#define		bAGCRxCode		0x300000
+
+#define		b3WireDataLength         0x800	/* Reg 0x820~84f rFPGA0_XA_HSSIParameter1 */
+#define		b3WireAddressLength		0x400
+
+#define		b3WireRFPowerDown         0x1	/* Useless now
+ * #define bHWSISelect		0x8 */
+#define		b5GPAPEPolarity		0x40000000
+#define		b2GPAPEPolarity		0x80000000
+#define		bRFSW_TxDefaultAnt		0x3
+#define		bRFSW_TxOptionAnt		0x30
+#define		bRFSW_RxDefaultAnt		0x300
+#define		bRFSW_RxOptionAnt		0x3000
+#define		bRFSI_3WireData		0x1
+#define		bRFSI_3WireClock		0x2
+#define		bRFSI_3WireLoad		0x4
+#define		bRFSI_3WireRW		0x8
+#define		bRFSI_3Wire			0xf
+
+#define		bRFSI_RFENV              0x10	/* Reg 0x870 rFPGA0_XAB_RFInterfaceSW */
+
+#define		bRFSI_TRSW               0x20	/* Useless now */
+#define		bRFSI_TRSWB		0x40
+#define		bRFSI_ANTSW		0x100
+#define		bRFSI_ANTSWB		0x200
+#define		bRFSI_PAPE			0x400
+#define		bRFSI_PAPE5G		0x800
+#define		bBandSelect			0x1
+#define		bHTSIG2_GI			0x80
+#define		bHTSIG2_Smoothing		0x01
+#define		bHTSIG2_Sounding		0x02
+#define		bHTSIG2_Aggreaton		0x08
+#define		bHTSIG2_STBC		0x30
+#define		bHTSIG2_AdvCoding		0x40
+#define		bHTSIG2_NumOfHTLTF	0x300
+#define		bHTSIG2_CRC8		0x3fc
+#define		bHTSIG1_MCS		0x7f
+#define		bHTSIG1_BandWidth		0x80
+#define		bHTSIG1_HTLength		0xffff
+#define		bLSIG_Rate			0xf
+#define		bLSIG_Reserved		0x10
+#define		bLSIG_Length		0x1fffe
+#define		bLSIG_Parity			0x20
+#define		bCCKRxPhase		0x4
+
+#define		bLSSIReadAddress          0x7f800000   /* T65 RF */
+
+#define		bLSSIReadEdge             0x80000000   /* LSSI "Read" edge signal */
+
+#define		bLSSIReadBackData         0xfffff		/* T65 RF */
+
+#define		bLSSIReadOKFlag           0x1000	/* Useless now */
+#define		bCCKSampleRate            0x8       /* 0: 44MHz, 1:88MHz     */
+#define		bRegulator0Standby		0x1
+#define		bRegulatorPLLStandby		0x2
+#define		bRegulator1Standby		0x4
+#define		bPLLPowerUp		0x8
+#define		bDPLLPowerUp		0x10
+#define		bDA10PowerUp		0x20
+#define		bAD7PowerUp		0x200
+#define		bDA6PowerUp		0x2000
+#define		bXtalPowerUp		0x4000
+#define		b40MDClkPowerUP		0x8000
+#define		bDA6DebugMode		0x20000
+#define		bDA6Swing			0x380000
+
+#define		bADClkPhase               0x4000000	/* Reg 0x880 rFPGA0_AnalogParameter1 20/40 CCK support switch 40/80 BB MHZ */
+
+#define		b80MClkDelay              0x18000000	/* Useless */
+#define		bAFEWatchDogEnable		0x20000000
+
+#define		bXtalCap01                0xc0000000	/* Reg 0x884 rFPGA0_AnalogParameter2 Crystal cap */
+#define		bXtalCap23			0x3
+#define		bXtalCap92x					0x0f000000
+#define		bXtalCap			0x0f000000
+
+#define		bIntDifClkEnable          0x400	/* Useless */
+#define		bExtSigClkEnable		0x800
+#define		bBandgapMbiasPowerUp	0x10000
+#define		bAD11SHGain		0xc0000
+#define		bAD11InputRange		0x700000
+#define		bAD11OPCurrent		0x3800000
+#define		bIPathLoopback		0x4000000
+#define		bQPathLoopback		0x8000000
+#define		bAFELoopback		0x10000000
+#define		bDA10Swing		0x7e0
+#define		bDA10Reverse		0x800
+#define		bDAClkSource		0x1000
+#define		bAD7InputRange		0x6000
+#define		bAD7Gain			0x38000
+#define		bAD7OutputCMMode		0x40000
+#define		bAD7InputCMMode		0x380000
+#define		bAD7Current			0xc00000
+#define		bRegulatorAdjust		0x7000000
+#define		bAD11PowerUpAtTx		0x1
+#define		bDA10PSAtTx		0x10
+#define		bAD11PowerUpAtRx		0x100
+#define		bDA10PSAtRx		0x1000
+#define		bCCKRxAGCFormat		0x200
+#define		bPSDFFTSamplepPoint		0xc000
+#define		bPSDAverageNum		0x3000
+#define		bIQPathControl		0xc00
+#define		bPSDFreq			0x3ff
+#define		bPSDAntennaPath		0x30
+#define		bPSDIQSwitch		0x40
+#define		bPSDRxTrigger		0x400000
+#define		bPSDTxTrigger		0x80000000
+#define		bPSDSineToneScale		0x7f000000
+#define		bPSDReport			0xffff
+
+/* 3. Page9(0x900) */
+#define		bOFDMTxSC                 0x30000000	/* Useless */
+#define		bCCKTxOn			0x1
+#define		bOFDMTxOn		0x2
+#define		bDebugPage                0xfff  /* reset debug page and also HWord, LWord */
+#define		bDebugItem                0xff   /* reset debug page and LWord */
+#define		bAntL			0x10
+#define		bAntNonHT				0x100
+#define		bAntHT1			0x1000
+#define		bAntHT2			0x10000
+#define		bAntHT1S1			0x100000
+#define		bAntNonHTS1		0x1000000
+
+/* 4. PageA(0xA00) */
+#define		bCCKBBMode				0x3	/* Useless */
+#define		bCCKTxPowerSaving		0x80
+#define		bCCKRxPowerSaving		0x40
+
+#define		bCCKSideBand			0x10	/* Reg 0xa00 rCCK0_System 20/40 switch */
+
+#define		bCCKScramble			0x8	/* Useless */
+#define		bCCKAntDiversity		0x8000
+#define		bCCKCarrierRecovery		0x4000
+#define		bCCKTxRate				0x3000
+#define		bCCKDCCancel			0x0800
+#define		bCCKISICancel			0x0400
+#define		bCCKMatchFilter			0x0200
+#define		bCCKEqualizer			0x0100
+#define		bCCKPreambleDetect		0x800000
+#define		bCCKFastFalseCCA		0x400000
+#define		bCCKChEstStart			0x300000
+#define		bCCKCCACount			0x080000
+#define		bCCKcs_lim				0x070000
+#define		bCCKBistMode			0x80000000
+#define		bCCKCCAMask			0x40000000
+#define		bCCKTxDACPhase		0x4
+#define		bCCKRxADCPhase		0x20000000   /* r_rx_clk */
+#define		bCCKr_cp_mode0		0x0100
+#define		bCCKTxDCOffset			0xf0
+#define		bCCKRxDCOffset			0xf
+#define		bCCKCCAMode			0xc000
+#define		bCCKFalseCS_lim			0x3f00
+#define		bCCKCS_ratio			0xc00000
+#define		bCCKCorgBit_sel			0x300000
+#define		bCCKPD_lim				0x0f0000
+#define		bCCKNewCCA			0x80000000
+#define		bCCKRxHPofIG			0x8000
+#define		bCCKRxIG				0x7f00
+#define		bCCKLNAPolarity			0x800000
+#define		bCCKRx1stGain			0x7f0000
+#define		bCCKRFExtend			0x20000000 /* CCK Rx Iinital gain polarity */
+#define		bCCKRxAGCSatLevel		0x1f000000
+#define		bCCKRxAGCSatCount		0xe0
+#define		bCCKRxRFSettle			0x1f       /* AGCsamp_dly */
+#define		bCCKFixedRxAGC			0x8000
+/* #define bCCKRxAGCFormat		0x4000 */   /* remove to HSSI register 0x824 */
+#define		bCCKAntennaPolarity		0x2000
+#define		bCCKTxFilterType		0x0c00
+#define		bCCKRxAGCReportType	0x0300
+#define		bCCKRxDAGCEn			0x80000000
+#define		bCCKRxDAGCPeriod		0x20000000
+#define		bCCKRxDAGCSatLevel		0x1f000000
+#define		bCCKTimingRecovery		0x800000
+#define		bCCKTxC0				0x3f0000
+#define		bCCKTxC1				0x3f000000
+#define		bCCKTxC2				0x3f
+#define		bCCKTxC3				0x3f00
+#define		bCCKTxC4				0x3f0000
+#define		bCCKTxC5				0x3f000000
+#define		bCCKTxC6				0x3f
+#define		bCCKTxC7				0x3f00
+#define		bCCKDebugPort			0xff0000
+#define		bCCKDACDebug			0x0f000000
+#define		bCCKFalseAlarmEnable	0x8000
+#define		bCCKFalseAlarmRead		0x4000
+#define		bCCKTRSSI				0x7f
+#define		bCCKRxAGCReport		0xfe
+#define		bCCKRxReport_AntSel	0x80000000
+#define		bCCKRxReport_MFOff		0x40000000
+#define		bCCKRxRxReport_SQLoss	0x20000000
+#define		bCCKRxReport_Pktloss	0x10000000
+#define		bCCKRxReport_Lockedbit	0x08000000
+#define		bCCKRxReport_RateError	0x04000000
+#define		bCCKRxReport_RxRate	0x03000000
+#define		bCCKRxFACounterLower	0xff
+#define		bCCKRxFACounterUpper	0xff000000
+#define		bCCKRxHPAGCStart		0xe000
+#define		bCCKRxHPAGCFinal		0x1c00
+#define		bCCKRxFalseAlarmEnable	0x8000
+#define		bCCKFACounterFreeze	0x4000
+#define		bCCKTxPathSel			0x10000000
+#define		bCCKDefaultRxPath		0xc000000
+#define		bCCKOptionRxPath		0x3000000
+
+/* 5. PageC(0xC00) */
+#define		bNumOfSTF				0x3	/* Useless */
+#define		bShift_L					0xc0
+#define		bGI_TH					0xc
+#define		bRxPathA				0x1
+#define		bRxPathB				0x2
+#define		bRxPathC				0x4
+#define		bRxPathD				0x8
+#define		bTxPathA				0x1
+#define		bTxPathB				0x2
+#define		bTxPathC				0x4
+#define		bTxPathD				0x8
+#define		bTRSSIFreq				0x200
+#define		bADCBackoff				0x3000
+#define		bDFIRBackoff			0xc000
+#define		bTRSSILatchPhase		0x10000
+#define		bRxIDCOffset			0xff
+#define		bRxQDCOffset			0xff00
+#define		bRxDFIRMode			0x1800000
+#define		bRxDCNFType			0xe000000
+#define		bRXIQImb_A				0x3ff
+#define		bRXIQImb_B				0xfc00
+#define		bRXIQImb_C				0x3f0000
+#define		bRXIQImb_D				0xffc00000
+#define		bDC_dc_Notch			0x60000
+#define		bRxNBINotch			0x1f000000
+#define		bPD_TH					0xf
+#define		bPD_TH_Opt2			0xc000
+#define		bPWED_TH				0x700
+#define		bIfMF_Win_L			0x800
+#define		bPD_Option				0x1000
+#define		bMF_Win_L				0xe000
+#define		bBW_Search_L			0x30000
+#define		bwin_enh_L				0xc0000
+#define		bBW_TH					0x700000
+#define		bED_TH2				0x3800000
+#define		bBW_option				0x4000000
+#define		bRatio_TH				0x18000000
+#define		bWindow_L				0xe0000000
+#define		bSBD_Option				0x1
+#define		bFrame_TH				0x1c
+#define		bFS_Option				0x60
+#define		bDC_Slope_check		0x80
+#define		bFGuard_Counter_DC_L	0xe00
+#define		bFrame_Weight_Short	0x7000
+#define		bSub_Tune				0xe00000
+#define		bFrame_DC_Length		0xe000000
+#define		bSBD_start_offset		0x30000000
+#define		bFrame_TH_2			0x7
+#define		bFrame_GI2_TH			0x38
+#define		bGI2_Sync_en			0x40
+#define		bSarch_Short_Early		0x300
+#define		bSarch_Short_Late		0xc00
+#define		bSarch_GI2_Late		0x70000
+#define		bCFOAntSum				0x1
+#define		bCFOAcc				0x2
+#define		bCFOStartOffset			0xc
+#define		bCFOLookBack			0x70
+#define		bCFOSumWeight			0x80
+#define		bDAGCEnable			0x10000
+#define		bTXIQImb_A				0x3ff
+#define		bTXIQImb_B				0xfc00
+#define		bTXIQImb_C				0x3f0000
+#define		bTXIQImb_D				0xffc00000
+#define		bTxIDCOffset			0xff
+#define		bTxQDCOffset			0xff00
+#define		bTxDFIRMode			0x10000
+#define		bTxPesudoNoiseOn		0x4000000
+#define		bTxPesudoNoise_A		0xff
+#define		bTxPesudoNoise_B		0xff00
+#define		bTxPesudoNoise_C		0xff0000
+#define		bTxPesudoNoise_D		0xff000000
+#define		bCCADropOption			0x20000
+#define		bCCADropThres			0xfff00000
+#define		bEDCCA_H				0xf
+#define		bEDCCA_L				0xf0
+#define		bLambda_ED			0x300
+#define		bRxInitialGain			0x7f
+#define		bRxAntDivEn				0x80
+#define		bRxAGCAddressForLNA	0x7f00
+#define		bRxHighPowerFlow		0x8000
+#define		bRxAGCFreezeThres		0xc0000
+#define		bRxFreezeStep_AGC1	0x300000
+#define		bRxFreezeStep_AGC2	0xc00000
+#define		bRxFreezeStep_AGC3	0x3000000
+#define		bRxFreezeStep_AGC0	0xc000000
+#define		bRxRssi_Cmp_En			0x10000000
+#define		bRxQuickAGCEn			0x20000000
+#define		bRxAGCFreezeThresMode	0x40000000
+#define		bRxOverFlowCheckType	0x80000000
+#define		bRxAGCShift				0x7f
+#define		bTRSW_Tri_Only			0x80
+#define		bPowerThres			0x300
+#define		bRxAGCEn				0x1
+#define		bRxAGCTogetherEn		0x2
+#define		bRxAGCMin				0x4
+#define		bRxHP_Ini				0x7
+#define		bRxHP_TRLNA			0x70
+#define		bRxHP_RSSI				0x700
+#define		bRxHP_BBP1				0x7000
+#define		bRxHP_BBP2				0x70000
+#define		bRxHP_BBP3				0x700000
+#define		bRSSI_H					0x7f0000     /* the threshold for high power */
+#define		bRSSI_Gen				0x7f000000   /* the threshold for ant diversity */
+#define		bRxSettle_TRSW			0x7
+#define		bRxSettle_LNA			0x38
+#define		bRxSettle_RSSI			0x1c0
+#define		bRxSettle_BBP			0xe00
+#define		bRxSettle_RxHP			0x7000
+#define		bRxSettle_AntSW_RSSI	0x38000
+#define		bRxSettle_AntSW		0xc0000
+#define		bRxProcessTime_DAGC	0x300000
+#define		bRxSettle_HSSI			0x400000
+#define		bRxProcessTime_BBPPW	0x800000
+#define		bRxAntennaPowerShift	0x3000000
+#define		bRSSITableSelect		0xc000000
+#define		bRxHP_Final				0x7000000
+#define		bRxHTSettle_BBP			0x7
+#define		bRxHTSettle_HSSI		0x8
+#define		bRxHTSettle_RxHP		0x70
+#define		bRxHTSettle_BBPPW		0x80
+#define		bRxHTSettle_Idle		0x300
+#define		bRxHTSettle_Reserved	0x1c00
+#define		bRxHTRxHPEn			0x8000
+#define		bRxHTAGCFreezeThres	0x30000
+#define		bRxHTAGCTogetherEn	0x40000
+#define		bRxHTAGCMin			0x80000
+#define		bRxHTAGCEn				0x100000
+#define		bRxHTDAGCEn			0x200000
+#define		bRxHTRxHP_BBP			0x1c00000
+#define		bRxHTRxHP_Final		0xe0000000
+#define		bRxPWRatioTH			0x3
+#define		bRxPWRatioEn			0x4
+#define		bRxMFHold				0x3800
+#define		bRxPD_Delay_TH1		0x38
+#define		bRxPD_Delay_TH2		0x1c0
+#define		bRxPD_DC_COUNT_MAX	0x600
+/* #define bRxMF_Hold               0x3800 */
+#define		bRxPD_Delay_TH			0x8000
+#define		bRxProcess_Delay		0xf0000
+#define		bRxSearchrange_GI2_Early	0x700000
+#define		bRxFrame_Guard_Counter_L	0x3800000
+#define		bRxSGI_Guard_L			0xc000000
+#define		bRxSGI_Search_L		0x30000000
+#define		bRxSGI_TH				0xc0000000
+#define		bDFSCnt0				0xff
+#define		bDFSCnt1				0xff00
+#define		bDFSFlag				0xf0000
+#define		bMFWeightSum			0x300000
+#define		bMinIdxTH				0x7f000000
+#define		bDAFormat				0x40000
+#define		bTxChEmuEnable		0x01000000
+#define		bTRSWIsolation_A		0x7f
+#define		bTRSWIsolation_B		0x7f00
+#define		bTRSWIsolation_C		0x7f0000
+#define		bTRSWIsolation_D		0x7f000000
+#define		bExtLNAGain				0x7c00
+
+/* 6. PageE(0xE00) */
+#define		bSTBCEn				0x4	/* Useless */
+#define		bAntennaMapping		0x10
+#define		bNss					0x20
+#define		bCFOAntSumD			0x200
+#define		bPHYCounterReset		0x8000000
+#define		bCFOReportGet			0x4000000
+#define		bOFDMContinueTx		0x10000000
+#define		bOFDMSingleCarrier		0x20000000
+#define		bOFDMSingleTone		0x40000000
+/* #define bRxPath1                 0x01 */
+/* #define bRxPath2                 0x02 */
+/* #define bRxPath3                 0x04 */
+/* #define bRxPath4                 0x08 */
+/* #define bTxPath1                 0x10 */
+/* #define bTxPath2                 0x20 */
+#define		bHTDetect			0x100
+#define		bCFOEn				0x10000
+#define		bCFOValue			0xfff00000
+#define		bSigTone_Re		0x3f
+#define		bSigTone_Im		0x7f00
+#define		bCounter_CCA		0xffff
+#define		bCounter_ParityFail	0xffff0000
+#define		bCounter_RateIllegal		0xffff
+#define		bCounter_CRC8Fail	0xffff0000
+#define		bCounter_MCSNoSupport	0xffff
+#define		bCounter_FastSync	0xffff
+#define		bShortCFO			0xfff
+#define		bShortCFOTLength	12   /* total */
+#define		bShortCFOFLength	11   /* fraction */
+#define		bLongCFO			0x7ff
+#define		bLongCFOTLength	11
+#define		bLongCFOFLength	11
+#define		bTailCFO			0x1fff
+#define		bTailCFOTLength		13
+#define		bTailCFOFLength		12
+#define		bmax_en_pwdB		0xffff
+#define		bCC_power_dB		0xffff0000
+#define		bnoise_pwdB		0xffff
+#define		bPowerMeasTLength	10
+#define		bPowerMeasFLength	3
+#define		bRx_HT_BW			0x1
+#define		bRxSC				0x6
+#define		bRx_HT				0x8
+#define		bNB_intf_det_on		0x1
+#define		bIntf_win_len_cfg	0x30
+#define		bNB_Intf_TH_cfg		0x1c0
+#define		bRFGain				0x3f
+#define		bTableSel			0x40
+#define		bTRSW				0x80
+#define		bRxSNR_A			0xff
+#define		bRxSNR_B			0xff00
+#define		bRxSNR_C			0xff0000
+#define		bRxSNR_D			0xff000000
+#define		bSNREVMTLength		8
+#define		bSNREVMFLength		1
+#define		bCSI1st				0xff
+#define		bCSI2nd				0xff00
+#define		bRxEVM1st			0xff0000
+#define		bRxEVM2nd			0xff000000
+#define		bSIGEVM			0xff
+#define		bPWDB				0xff00
+#define		bSGIEN				0x10000
+
+#define		bSFactorQAM1		0xf	/* Useless */
+#define		bSFactorQAM2		0xf0
+#define		bSFactorQAM3		0xf00
+#define		bSFactorQAM4		0xf000
+#define		bSFactorQAM5		0xf0000
+#define		bSFactorQAM6		0xf0000
+#define		bSFactorQAM7		0xf00000
+#define		bSFactorQAM8		0xf000000
+#define		bSFactorQAM9		0xf0000000
+#define		bCSIScheme			0x100000
+
+#define		bNoiseLvlTopSet		0x3	/* Useless */
+#define		bChSmooth			0x4
+#define		bChSmoothCfg1		0x38
+#define		bChSmoothCfg2		0x1c0
+#define		bChSmoothCfg3		0xe00
+#define		bChSmoothCfg4		0x7000
+#define		bMRCMode			0x800000
+#define		bTHEVMCfg			0x7000000
+
+#define		bLoopFitType		0x1	/* Useless */
+#define		bUpdCFO			0x40
+#define		bUpdCFOOffData		0x80
+#define		bAdvUpdCFO			0x100
+#define		bAdvTimeCtrl		0x800
+#define		bUpdClko			0x1000
+#define		bFC					0x6000
+#define		bTrackingMode		0x8000
+#define		bPhCmpEnable		0x10000
+#define		bUpdClkoLTF		0x20000
+#define		bComChCFO			0x40000
+#define		bCSIEstiMode		0x80000
+#define		bAdvUpdEqz			0x100000
+#define		bUChCfg				0x7000000
+#define		bUpdEqz			0x8000000
+
+/* Rx Pseduo noise */
+#define		bRxPesudoNoiseOn		0x20000000	/* Useless */
+#define		bRxPesudoNoise_A		0xff
+#define		bRxPesudoNoise_B		0xff00
+#define		bRxPesudoNoise_C		0xff0000
+#define		bRxPesudoNoise_D		0xff000000
+#define		bPesudoNoiseState_A	0xffff
+#define		bPesudoNoiseState_B	0xffff0000
+#define		bPesudoNoiseState_C	0xffff
+#define		bPesudoNoiseState_D	0xffff0000
+
+/* 7. RF Register
+ * Zebra1 */
+#define		bZebra1_HSSIEnable		0x8		/* Useless */
+#define		bZebra1_TRxControl		0xc00
+#define		bZebra1_TRxGainSetting	0x07f
+#define		bZebra1_RxCorner		0xc00
+#define		bZebra1_TxChargePump	0x38
+#define		bZebra1_RxChargePump	0x7
+#define		bZebra1_ChannelNum	0xf80
+#define		bZebra1_TxLPFBW		0x400
+#define		bZebra1_RxLPFBW		0x600
+
+/* Zebra4 */
+#define		bRTL8256RegModeCtrl1	0x100	/* Useless */
+#define		bRTL8256RegModeCtrl0	0x40
+#define		bRTL8256_TxLPFBW		0x18
+#define		bRTL8256_RxLPFBW		0x600
+
+/* RTL8258 */
+#define		bRTL8258_TxLPFBW		0xc	/* Useless */
+#define		bRTL8258_RxLPFBW		0xc00
+#define		bRTL8258_RSSILPFBW	0xc0
+
+
+/*
+ * Other Definition
+ *   */
+
+/* byte endable for sb_write */
+#define		bByte0				0x1	/* Useless */
+#define		bByte1				0x2
+#define		bByte2				0x4
+#define		bByte3				0x8
+#define		bWord0				0x3
+#define		bWord1				0xc
+#define		bDWord				0xf
+
+/* for PutRegsetting & GetRegSetting BitMask */
+#define		bMaskByte0			0xff	/* Reg 0xc50 rOFDM0_XAAGCCore~0xC6f */
+#define		bMaskByte1			0xff00
+#define		bMaskByte2			0xff0000
+#define		bMaskByte3			0xff000000
+#define		bMaskHWord		0xffff0000
+#define		bMaskLWord			0x0000ffff
+#define		bMaskDWord		0xffffffff
+#define		bMaskH3Bytes		0xffffff00
+#define		bMask12Bits			0xfff
+#define		bMaskH4Bits			0xf0000000
+#define		bMaskOFDM_D		0xffc00000
+#define		bMaskCCK			0x3f3f3f3f
+
+
+#define		bEnable			0x1	/* Useless */
+#define		bDisable		0x0
+
+#define		LeftAntenna		0x0	/* Useless */
+#define		RightAntenna	0x1
+
+#define		tCheckTxStatus		500   /* 500ms // Useless */
+#define		tUpdateRxCounter	100   /* 100ms */
+
+#define		rateCCK		0	/* Useless */
+#define		rateOFDM	1
+#define		rateHT		2
+
+/* define Register-End */
+#define		bPMAC_End			0x1ff	/* Useless */
+#define		bFPGAPHY0_End		0x8ff
+#define		bFPGAPHY1_End		0x9ff
+#define		bCCKPHY0_End		0xaff
+#define		bOFDMPHY0_End		0xcff
+#define		bOFDMPHY1_End		0xdff
+
+/* define max debug item in each debug page
+ * #define bMaxItem_FPGA_PHY0        0x9
+ * #define bMaxItem_FPGA_PHY1        0x3
+ * #define bMaxItem_PHY_11B          0x16
+ * #define bMaxItem_OFDM_PHY0        0x29
+ * #define bMaxItem_OFDM_PHY1        0x0 */
+
+#define		bPMACControl		0x0		/* Useless */
+#define		bWMACControl		0x1
+#define		bWNICControl		0x2
+
+#define		PathA			0x0	/* Useless */
+#define		PathB			0x1
+#define		PathC			0x2
+#define		PathD			0x3
+
+#endif
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/include/Hal8192FPwrSeq.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/Hal8192FPwrSeq.h
--- linux-5.6.3/3rdparty/rtl8821ce/include/Hal8192FPwrSeq.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/Hal8192FPwrSeq.h	2020-04-10 16:35:06.844661375 +0300
@@ -0,0 +1,221 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2016 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#ifndef REALTEK_POWER_SEQUENCE_8192F
+#define REALTEK_POWER_SEQUENCE_8192F
+#define POWER_SEQUENCE_8192F_VER 02
+/* #include "PwrSeqCmd.h" */
+#include "HalPwrSeqCmd.h"
+
+/*
+	Check document WM-20110607-Paul-RTL8192e_Power_Architecture-R02.vsd
+	There are 6 HW Power States:
+	0: POFF--Power Off
+	1: PDN--Power Down
+	2: CARDEMU--Card Emulation
+	3: ACT--Active Mode
+	4: LPS--Low Power State
+	5: SUS--Suspend
+
+	The transition from different states are defined below
+	TRANS_CARDEMU_TO_ACT
+	TRANS_ACT_TO_CARDEMU
+	TRANS_CARDEMU_TO_SUS
+	TRANS_SUS_TO_CARDEMU
+	TRANS_CARDEMU_TO_PDN
+	TRANS_ACT_TO_LPS
+	TRANS_LPS_TO_ACT
+
+	TRANS_END
+*/
+#define	RTL8192F_TRANS_CARDEMU_TO_ACT_STEPS	38
+#define	RTL8192F_TRANS_ACT_TO_CARDEMU_STEPS	9
+#define	RTL8192F_TRANS_CARDEMU_TO_SUS_STEPS	7
+#define	RTL8192F_TRANS_SUS_TO_CARDEMU_STEPS	5
+#define	RTL8192F_TRANS_CARDEMU_TO_CARDDIS_STEPS	8
+#define	RTL8192F_TRANS_CARDDIS_TO_CARDEMU_STEPS	8
+#define	RTL8192F_TRANS_CARDEMU_TO_PDN_STEPS	4
+#define	RTL8192F_TRANS_PDN_TO_CARDEMU_STEPS	1
+#define	RTL8192F_TRANS_ACT_TO_LPS_STEPS		13
+#define	RTL8192F_TRANS_LPS_TO_ACT_STEPS		11	
+#define	RTL8192F_TRANS_END_STEPS	1
+
+
+#define RTL8192F_TRANS_CARDEMU_TO_ACT 														\
+	/* format */																\
+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
+	{0x0020, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, BIT0}, /*0x20[0] = 1b'1 enable LDOA12 MACRO block for all interface*/	\
+	{0x0067, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, 0}, /*0x67[0] = 0 to disable BT_GPS_SEL pins*/	\
+	{0x0001, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_DELAY, 1, PWRSEQ_DELAY_MS},/*Delay 1ms*/   \
+	{0x0000, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT5, 0}, /*0x00[5] = 1b'0 release analog Ips to digital ,1:isolation*/	\
+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, (BIT4|BIT3|BIT2), 0},/* disable SW LPS 0x04[10]=0 and WLSUS_EN 0x04[11]=0*/ \
+	{0x0075, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0 , BIT0},/* Disable USB suspend */	\
+	{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, BIT1, BIT1},/* wait till 0x04[17] = 1    power ready*/	\
+	{0x0075, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0 , 0},/* Enable USB suspend */	\
+	{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, BIT0},/* release WLON reset  0x04[16]=1*/ \
+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, (BIT1|BIT0), 0}, \
+	{0x0012, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT2, BIT2},/* SWR OCP enable 0x10[18]=1*/ \
+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT7, 0},/* disable HWPDN 0x04[15]=0*/	\
+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, (BIT4|BIT3), 0},/* disable WL suspend*/ \
+	{0x007f, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT7, BIT7},/* 0x7c[31]=1,LDO has max output capability*/ \
+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, BIT0},/* polling until return 0*/ \
+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, BIT0, 0},/**/ \
+	{0x0010, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT6, BIT6},/* Enable WL control XTAL setting*/ \
+	{0x0049, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, BIT1},/*Enable falling edge triggering interrupt*/\
+	{0x0063, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, 0},/*Enable GPIO9 data mode*/\
+	{0x0062, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, 0},/*Enable GPIO9 input mode*/\
+	{0x0058, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, BIT0},/*Enable HSISR GPIO[C:0] interrupt*/\
+	{0x0068, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3, 0},/*RF HW ON/OFF Enable*/\
+	{0x001C, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT7, BIT7},/*Register Lock Disable*/\
+	{0x0069, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT6, BIT6},/*For GPIO9 internal pull high setting*/\
+	{0x001f, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x00},/*reset RF path S1*/\
+	{0x007B, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x00},/*reset RF path S0*/\
+	{0x001f, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x07},/*enable RF path S1*/\
+	{0x007B, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x07},/*enalbe RF path S0*/\
+	{0x0097, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT5, BIT5},/*AFE_Ctrl*/\
+	{0x00DC, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0xCC},/*AFE_Ctrl*/\
+	{0x0024, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0x18, 0x00},/*AFE_Ctrl 0x24[4:3]=00 for xtal gmn*/\
+	{0x1050, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0xFF},/*GPIO_A[7:0] Pull down software register*/\
+	{0x1051, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0xFF},/*GPIO_A[15:8] Pull down software register*/\
+	{0x1052, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0xFF},/*GPIO_A[23:16] Pull down software register*/\
+	{0x1053, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0xFF},/*GPIO_A[31:24] Pull down software register*/\
+	{0x105B, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0xFF},/*GPIO_B[7:0] Pull down software register*/\
+	{0x001C, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT7, 0},/*Register Lock Enable*/\
+	{0x0077, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, (BIT7|BIT6), 0x3},/*set HCI Power sequence state delay time:0*/
+
+	
+#define RTL8192F_TRANS_ACT_TO_CARDEMU													\
+	/* format */																\
+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
+	/*{0x001F, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0}, */ /*0x1F[7:0] = 0 turn off RF*/	\
+	{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, 0}, /*0x2[0]=0 Reset BB,RF enter Power Down mode*/ \
+	{0x0049, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, 0},/*Enable rising edge triggering interrupt*/ \
+	{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, BIT0},/* release WLON reset  0x04[16]=1*/ \
+	{0x0012, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, 0}, /*0x10[18] = 0 to disable ocp*/	\
+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, BIT1}, /*0x04[9] = 1 turn off MAC by HW state machine*/	\
+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, BIT1, 0}, /*wait till 0x04[9] = 0 polling until return 0 to disable*/ \
+	{0x0010, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT6, 0},/* Enable BT control XTAL setting*/\
+	{0x0000, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT5, BIT5}, /*0x00[5] = 1b'1 analog Ips to digital ,1:isolation*/   \
+	{0x0020, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, 0}, /*0x20[0] = 1b'0 disable LDOA12 MACRO block*/\
+
+
+#define RTL8192F_TRANS_CARDEMU_TO_SUS													\
+	/* format */																\
+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4|BIT3, (BIT4|BIT3)}, /*0x04[12:11] = 2b'11 enable WL suspend for PCIe*/ \
+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3|BIT4, BIT3}, /*0x04[12:11] = 2b'01 enable WL suspend*/	\
+	{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, BIT4}, /*0x23[4] = 1b'1 12H LDO enter sleep mode*/	\
+	{0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x20}, /*0x07[7:0] = 0x20 USB|SDIO SOP option to disable BG/MB/ACK/SWR*/   \
+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3|BIT4, BIT3|BIT4}, /*0x04[12:11] = 2b'11 enable WL suspend for PCIe*/	\
+	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_WRITE, BIT0, BIT0}, /*Set SDIO suspend local register*/	\
+	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_POLLING, BIT1, 0}, /*wait power state to suspend*/
+
+#define RTL8192F_TRANS_SUS_TO_CARDEMU													\
+	/* format */																\
+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3 | BIT7, 0}, /*clear suspend enable and power down enable*/ \
+	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_WRITE, BIT0, 0}, /*Set SDIO suspend local register*/ \
+	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_POLLING, BIT1, BIT1}, /*wait power state to suspend*/\
+	{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, 0}, /*0x23[4] = 1b'0 12H LDO enter normal mode*/   \
+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3|BIT4, 0}, /*0x04[12:11] = 2b'01enable WL suspend*/
+	
+
+#define RTL8192F_TRANS_CARDEMU_TO_CARDDIS													\
+	/* format */																\
+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/	\
+	{0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x20}, /*0x07=0x20 , SOP option to disable BG/MB*/	\
+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3|BIT4, BIT3}, /*0x04[12:11] = 2b'01 enable WL suspend*/	\
+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT2, BIT2}, /*0x04[10] = 1, enable SW LPS*/	\
+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3|BIT4, BIT3|BIT4}, /*0x04[12:11] = 2b'11 enable WL suspend*/	\
+	{0x004A, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, 1}, /*0x48[16] = 1 to enable GPIO9 as EXT WAKEUP*/   \
+	{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, BIT4}, /*0x23[4] = 1b'1 12H LDO enter sleep mode*/	\
+	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_WRITE, BIT0, BIT0}, /*Set SDIO suspend local register*/	\
+	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_POLLING, BIT1, 0}, /*wait power state to suspend*/
+
+#define RTL8192F_TRANS_CARDDIS_TO_CARDEMU													\
+	/* format */																\
+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3 | BIT7, 0}, /*clear suspend enable and power down enable*/ \
+	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_WRITE, BIT0, 0}, /*Set SDIO suspend local register*/ \
+	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_POLLING, BIT1, BIT1}, /*wait power state to suspend*/\
+	{0x004A, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, 0}, /*0x48[16] = 0 to disable GPIO9 as EXT WAKEUP*/	\
+	{0x0012, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, BIT2}, /*0x10[18] = 1 to enable ocp*/	\
+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3|BIT4, 0}, /*0x04[12:11] = 2b'01enable WL suspend*/\
+	{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, 0}, /*0x23[4] = 1b'0 12H LDO enter normal mode*/   \
+	{0x0301, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0},/*PCIe DMA start*/
+
+
+#define RTL8192F_TRANS_CARDEMU_TO_PDN												\
+	/* format */																\
+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
+	{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, BIT4}, /*0x23[4] = 1b'1 12H LDO enter sleep mode*/	\
+	{0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK|PWR_INTF_USB_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x20}, /*0x07[7:0] = 0x20 SOP option to disable BG/MB/ACK/SWR*/   \
+	{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, 0},/* 0x04[16] = 0*/\
+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT7, BIT7},/* 0x04[15] = 1*/
+
+#define RTL8192F_TRANS_PDN_TO_CARDEMU												\
+	/* format */																\
+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT7, 0},/* 0x04[15] = 0*/
+
+#define RTL8192F_TRANS_ACT_TO_LPS														\
+	/* format */																\
+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
+	{0x0301, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0xFF},/*PCIe DMA stop*/	\
+	{0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0xFF},/*Tx Pause*/	\
+	{0x05F8, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/	\
+	{0x05F9, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/	\
+	{0x05FA, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/	\
+	{0x05FB, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/	\
+	{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, 0},/*CCK and OFDM are disabled,and clock are gated*/	\
+	{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_DELAY, 0, PWRSEQ_DELAY_US},/*Delay 1us*/	\
+	{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, 0},/*Whole BB is reset*/	\
+	{0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x03},/*Reset MAC TRX*/	\
+	{0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, 0},/*check if removed later*/ \
+	{0x0093, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x00},/*When driver enter Sus/ Disable, enable LOP for BT*/	\
+	{0x0553, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT5, BIT5},/*Respond TxOK to scheduler*/	\
+
+
+#define RTL8192F_TRANS_LPS_TO_ACT															\
+	/* format */																\
+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
+	{0x0080, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_WRITE, 0xFF, 0x84}, /*SDIO RPWM*/\
+	{0xFE58, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x84}, /*USB RPWM*/\
+	{0x0361, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x84}, /*PCIe RPWM*/\
+	{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_DELAY, 0, PWRSEQ_DELAY_MS}, /*Delay*/\
+	{0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, 0}, /*.	0x08[4] = 0 	 switch TSF to 40M*/\
+	{0x0109, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, BIT7, 0}, /*Polling 0x109[7]=0  TSF in 40M*/\
+	{0x0029, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT6|BIT7, 0}, /*.	0x29[7:6] = 2b'00	 enable BB clock*/\
+	{0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, BIT1}, /*.	0x101[1] = 1*/\
+	{0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0xFF}, /*.	0x100[7:0] = 0xFF	 enable WMAC TRX*/\
+	{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1|BIT0, BIT1|BIT0}, /*.	0x02[1:0] = 2b'11	 enable BB macro*/\
+	{0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0}, /*.	0x522 = 0*/
+ 
+#define RTL8192F_TRANS_END															\
+	/* format */																\
+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
+	{0xFFFF, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,0,PWR_CMD_END, 0, 0}, //
+
+
+extern WLAN_PWR_CFG rtl8192F_power_on_flow[RTL8192F_TRANS_CARDEMU_TO_ACT_STEPS+RTL8192F_TRANS_END_STEPS];
+extern WLAN_PWR_CFG rtl8192F_radio_off_flow[RTL8192F_TRANS_ACT_TO_CARDEMU_STEPS+RTL8192F_TRANS_END_STEPS];
+extern WLAN_PWR_CFG rtl8192F_card_disable_flow[RTL8192F_TRANS_ACT_TO_CARDEMU_STEPS+RTL8192F_TRANS_CARDEMU_TO_CARDDIS_STEPS+RTL8192F_TRANS_END_STEPS];
+extern WLAN_PWR_CFG rtl8192F_card_enable_flow[RTL8192F_TRANS_CARDDIS_TO_CARDEMU_STEPS+RTL8192F_TRANS_CARDEMU_TO_ACT_STEPS+RTL8192F_TRANS_END_STEPS];
+extern WLAN_PWR_CFG rtl8192F_suspend_flow[RTL8192F_TRANS_ACT_TO_CARDEMU_STEPS+RTL8192F_TRANS_CARDEMU_TO_SUS_STEPS+RTL8192F_TRANS_END_STEPS];
+extern WLAN_PWR_CFG rtl8192F_resume_flow[RTL8192F_TRANS_SUS_TO_CARDEMU_STEPS+RTL8192F_TRANS_CARDEMU_TO_ACT_STEPS+RTL8192F_TRANS_END_STEPS];
+extern WLAN_PWR_CFG rtl8192F_hwpdn_flow[RTL8192F_TRANS_ACT_TO_CARDEMU_STEPS+RTL8192F_TRANS_CARDEMU_TO_PDN_STEPS+RTL8192F_TRANS_END_STEPS];
+extern WLAN_PWR_CFG rtl8192F_enter_lps_flow[RTL8192F_TRANS_ACT_TO_LPS_STEPS+RTL8192F_TRANS_END_STEPS];
+extern WLAN_PWR_CFG rtl8192F_leave_lps_flow[RTL8192F_TRANS_LPS_TO_ACT_STEPS+RTL8192F_TRANS_END_STEPS];
+
+#endif
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/include/Hal8703BPhyCfg.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/Hal8703BPhyCfg.h
--- linux-5.6.3/3rdparty/rtl8821ce/include/Hal8703BPhyCfg.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/Hal8703BPhyCfg.h	2020-04-10 16:35:06.844661375 +0300
@@ -0,0 +1,132 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#ifndef __INC_HAL8703BPHYCFG_H__
+#define __INC_HAL8703BPHYCFG_H__
+
+/*--------------------------Define Parameters-------------------------------*/
+#define LOOP_LIMIT				5
+#define MAX_STALL_TIME			50		/* us */
+#define AntennaDiversityValue	0x80	/* (Adapter->bSoftwareAntennaDiversity ? 0x00 : 0x80) */
+#define MAX_TXPWR_IDX_NMODE_92S	63
+#define Reset_Cnt_Limit			3
+
+#ifdef CONFIG_PCI_HCI
+	#define MAX_AGGR_NUM	0x0B
+#else
+	#define MAX_AGGR_NUM	0x07
+#endif /* CONFIG_PCI_HCI */
+
+
+/*--------------------------Define Parameters End-------------------------------*/
+
+
+/*------------------------------Define structure----------------------------*/
+
+/*------------------------------Define structure End----------------------------*/
+
+/*--------------------------Exported Function prototype---------------------*/
+u32
+PHY_QueryBBReg_8703B(
+	IN	PADAPTER	Adapter,
+	IN	u32		RegAddr,
+	IN	u32		BitMask
+);
+
+VOID
+PHY_SetBBReg_8703B(
+	IN	PADAPTER	Adapter,
+	IN	u32		RegAddr,
+	IN	u32		BitMask,
+	IN	u32		Data
+);
+
+u32
+PHY_QueryRFReg_8703B(
+	IN	PADAPTER		Adapter,
+	IN	enum rf_path		eRFPath,
+	IN	u32				RegAddr,
+	IN	u32				BitMask
+);
+
+VOID
+PHY_SetRFReg_8703B(
+	IN	PADAPTER		Adapter,
+	IN	enum rf_path		eRFPath,
+	IN	u32				RegAddr,
+	IN	u32				BitMask,
+	IN	u32				Data
+);
+
+/* MAC/BB/RF HAL config */
+int PHY_BBConfig8703B(PADAPTER	Adapter);
+
+int PHY_RFConfig8703B(PADAPTER	Adapter);
+
+s32 PHY_MACConfig8703B(PADAPTER padapter);
+
+int
+PHY_ConfigRFWithParaFile_8703B(
+	IN	PADAPTER			Adapter,
+	IN	u8					*pFileName,
+	enum rf_path				eRFPath
+);
+
+VOID
+PHY_SetTxPowerIndex_8703B(
+	IN	PADAPTER			Adapter,
+	IN	u32					PowerIndex,
+	IN	enum rf_path			RFPath,
+	IN	u8					Rate
+);
+
+u8
+PHY_GetTxPowerIndex_8703B(
+	IN	PADAPTER			pAdapter,
+	IN	enum rf_path			RFPath,
+	IN	u8					Rate,
+	IN	u8					BandWidth,
+	IN	u8					Channel,
+	struct txpwr_idx_comp *tic
+);
+
+VOID
+PHY_GetTxPowerLevel8703B(
+	IN	PADAPTER		Adapter,
+	OUT s32				*powerlevel
+);
+
+VOID
+PHY_SetTxPowerLevel8703B(
+	IN	PADAPTER		Adapter,
+	IN	u8			channel
+);
+
+VOID
+PHY_SetSwChnlBWMode8703B(
+	IN	PADAPTER			Adapter,
+	IN	u8					channel,
+	IN	enum channel_width	Bandwidth,
+	IN	u8					Offset40,
+	IN	u8					Offset80
+);
+
+VOID phy_set_rf_path_switch_8703b(
+	IN	struct dm_struct		*phydm,
+	IN	bool		bMain
+);
+
+/*--------------------------Exported Function prototype End---------------------*/
+
+#endif
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/include/Hal8703BPhyReg.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/Hal8703BPhyReg.h
--- linux-5.6.3/3rdparty/rtl8821ce/include/Hal8703BPhyReg.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/Hal8703BPhyReg.h	2020-04-10 16:35:06.844661375 +0300
@@ -0,0 +1,1133 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#ifndef __INC_HAL8703BPHYREG_H__
+#define __INC_HAL8703BPHYREG_H__
+
+#define		rSYM_WLBT_PAPE_SEL		0x64
+/*
+ * BB-PHY register PMAC 0x100 PHY 0x800 - 0xEFF
+ * 1. PMAC duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF
+ * 2. 0x800/0x900/0xA00/0xC00/0xD00/0xE00
+ * 3. RF register 0x00-2E
+ * 4. Bit Mask for BB/RF register
+ * 5. Other defintion for BB/RF R/W
+ *   */
+
+
+/*
+ * 1. PMAC duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF
+ * 1. Page1(0x100)
+ *   */
+#define		rPMAC_Reset					0x100
+#define		rPMAC_TxStart					0x104
+#define		rPMAC_TxLegacySIG				0x108
+#define		rPMAC_TxHTSIG1				0x10c
+#define		rPMAC_TxHTSIG2				0x110
+#define		rPMAC_PHYDebug				0x114
+#define		rPMAC_TxPacketNum				0x118
+#define		rPMAC_TxIdle					0x11c
+#define		rPMAC_TxMACHeader0			0x120
+#define		rPMAC_TxMACHeader1			0x124
+#define		rPMAC_TxMACHeader2			0x128
+#define		rPMAC_TxMACHeader3			0x12c
+#define		rPMAC_TxMACHeader4			0x130
+#define		rPMAC_TxMACHeader5			0x134
+#define		rPMAC_TxDataType				0x138
+#define		rPMAC_TxRandomSeed			0x13c
+#define		rPMAC_CCKPLCPPreamble			0x140
+#define		rPMAC_CCKPLCPHeader			0x144
+#define		rPMAC_CCKCRC16				0x148
+#define		rPMAC_OFDMRxCRC32OK			0x170
+#define		rPMAC_OFDMRxCRC32Er			0x174
+#define		rPMAC_OFDMRxParityEr			0x178
+#define		rPMAC_OFDMRxCRC8Er			0x17c
+#define		rPMAC_CCKCRxRC16Er			0x180
+#define		rPMAC_CCKCRxRC32Er			0x184
+#define		rPMAC_CCKCRxRC32OK			0x188
+#define		rPMAC_TxStatus					0x18c
+
+/*
+ * 2. Page2(0x200)
+ *
+ * The following two definition are only used for USB interface. */
+#define		RF_BB_CMD_ADDR				0x02c0	/* RF/BB read/write command address. */
+#define		RF_BB_CMD_DATA				0x02c4	/* RF/BB read/write command data. */
+
+/*
+ * 3. Page8(0x800)
+ *   */
+#define		rFPGA0_RFMOD				0x800	/* RF mode & CCK TxSC */ /* RF BW Setting?? */
+
+#define		rFPGA0_TxInfo				0x804	/* Status report?? */
+#define		rFPGA0_PSDFunction			0x808
+
+#define		rFPGA0_TxGainStage			0x80c	/* Set TX PWR init gain? */
+
+#define		rFPGA0_RFTiming1			0x810	/* Useless now */
+#define		rFPGA0_RFTiming2			0x814
+
+#define		rFPGA0_XA_HSSIParameter1		0x820	/* RF 3 wire register */
+#define		rFPGA0_XA_HSSIParameter2		0x824
+#define		rFPGA0_XB_HSSIParameter1		0x828
+#define		rFPGA0_XB_HSSIParameter2		0x82c
+#define		rTxAGC_B_Rate18_06				0x830
+#define		rTxAGC_B_Rate54_24				0x834
+#define		rTxAGC_B_CCK1_55_Mcs32		0x838
+#define		rTxAGC_B_Mcs03_Mcs00			0x83c
+
+#define		rTxAGC_B_Mcs07_Mcs04			0x848
+#define		rTxAGC_B_Mcs11_Mcs08			0x84c
+
+#define		rFPGA0_XA_LSSIParameter		0x840
+#define		rFPGA0_XB_LSSIParameter		0x844
+
+#define		rFPGA0_RFWakeUpParameter		0x850	/* Useless now */
+#define		rFPGA0_RFSleepUpParameter		0x854
+
+#define		rFPGA0_XAB_SwitchControl		0x858	/* RF Channel switch */
+#define		rFPGA0_XCD_SwitchControl		0x85c
+
+#define		rFPGA0_XA_RFInterfaceOE		0x860	/* RF Channel switch */
+#define		rFPGA0_XB_RFInterfaceOE		0x864
+
+#define		rTxAGC_B_Mcs15_Mcs12			0x868
+#define		rTxAGC_B_CCK11_A_CCK2_11		0x86c
+
+#define		rFPGA0_XAB_RFInterfaceSW		0x870	/* RF Interface Software Control */
+#define		rFPGA0_XCD_RFInterfaceSW		0x874
+
+#define		rFPGA0_XAB_RFParameter		0x878	/* RF Parameter */
+#define		rFPGA0_XCD_RFParameter		0x87c
+
+#define		rFPGA0_AnalogParameter1		0x880	/* Crystal cap setting RF-R/W protection for parameter4?? */
+#define		rFPGA0_AnalogParameter2		0x884
+#define		rFPGA0_AnalogParameter3		0x888	/* Useless now */
+#define		rFPGA0_AnalogParameter4		0x88c
+
+#define		rFPGA0_XA_LSSIReadBack		0x8a0	/* Tranceiver LSSI Readback */
+#define		rFPGA0_XB_LSSIReadBack		0x8a4
+#define		rFPGA0_XC_LSSIReadBack		0x8a8
+#define		rFPGA0_XD_LSSIReadBack		0x8ac
+
+#define		rFPGA0_PSDReport				0x8b4	/* Useless now */
+#define		TransceiverA_HSPI_Readback	0x8b8	/* Transceiver A HSPI Readback */
+#define		TransceiverB_HSPI_Readback	0x8bc	/* Transceiver B HSPI Readback */
+#define		rFPGA0_XAB_RFInterfaceRB		0x8e0	/* Useless now */ /* RF Interface Readback Value */
+#define		rFPGA0_XCD_RFInterfaceRB		0x8e4	/* Useless now */
+
+/*
+ * 4. Page9(0x900)
+ *   */
+#define	rFPGA1_RFMOD				0x900	/* RF mode & OFDM TxSC */ /* RF BW Setting?? */
+#define	rFPGA1_TxBlock				0x904	/* Useless now */
+#define	rFPGA1_DebugSelect			0x908	/* Useless now */
+#define	rFPGA1_TxInfo				0x90c	/* Useless now */ /* Status report?? */
+#define	rDPDT_control				0x92c
+#define	rfe_ctrl_anta_src				0x930
+#define	rS0S1_PathSwitch			0x948
+#define	rBBrx_DFIR					0x954
+
+/*
+ * 5. PageA(0xA00)
+ *
+ * Set Control channel to upper or lower. These settings are required only for 40MHz */
+#define		rCCK0_System				0xa00
+
+#define		rCCK0_AFESetting			0xa04	/* Disable init gain now */ /* Select RX path by RSSI */
+#define		rCCK0_CCA					0xa08	/* Disable init gain now */ /* Init gain */
+
+#define		rCCK0_RxAGC1				0xa0c	/* AGC default value, saturation level  */ /* Antenna Diversity, RX AGC, LNA Threshold, RX LNA Threshold useless now. Not the same as 90 series */
+#define		rCCK0_RxAGC2				0xa10	/* AGC & DAGC */
+
+#define		rCCK0_RxHP					0xa14
+
+#define		rCCK0_DSPParameter1		0xa18	/* Timing recovery & Channel estimation threshold */
+#define		rCCK0_DSPParameter2		0xa1c	/* SQ threshold */
+
+#define		rCCK0_TxFilter1				0xa20
+#define		rCCK0_TxFilter2				0xa24
+#define		rCCK0_DebugPort			0xa28	/* debug port and Tx filter3 */
+#define		rCCK0_FalseAlarmReport		0xa2c	/* 0xa2d	useless now 0xa30-a4f channel report */
+#define		rCCK0_TRSSIReport		0xa50
+#define		rCCK0_RxReport            		0xa54  /* 0xa57 */
+#define		rCCK0_FACounterLower      	0xa5c  /* 0xa5b */
+#define		rCCK0_FACounterUpper      	0xa58  /* 0xa5c */
+
+/*
+ * PageB(0xB00)
+ *   */
+#define rPdp_AntA						0xb00
+#define rPdp_AntA_4						0xb04
+#define rPdp_AntA_8						0xb08
+#define rPdp_AntA_C						0xb0c
+#define rPdp_AntA_10					0xb10
+#define rPdp_AntA_14					0xb14
+#define rPdp_AntA_18					0xb18
+#define rPdp_AntA_1C					0xb1c
+#define rPdp_AntA_20					0xb20
+#define rPdp_AntA_24					0xb24
+
+#define rConfig_Pmpd_AntA				0xb28
+#define rConfig_ram64x16				0xb2c
+
+#define rBndA							0xb30
+#define rHssiPar						0xb34
+
+#define rConfig_AntA					0xb68
+#define rConfig_AntB					0xb6c
+
+#define rPdp_AntB						0xb70
+#define rPdp_AntB_4						0xb74
+#define rPdp_AntB_8						0xb78
+#define rPdp_AntB_C						0xb7c
+#define rPdp_AntB_10					0xb80
+#define rPdp_AntB_14					0xb84
+#define rPdp_AntB_18					0xb88
+#define rPdp_AntB_1C					0xb8c
+#define rPdp_AntB_20					0xb90
+#define rPdp_AntB_24					0xb94
+
+#define rConfig_Pmpd_AntB				0xb98
+
+#define rBndB							0xba0
+
+#define rAPK							0xbd8
+#define rPm_Rx0_AntA					0xbdc
+#define rPm_Rx1_AntA					0xbe0
+#define rPm_Rx2_AntA					0xbe4
+#define rPm_Rx3_AntA					0xbe8
+#define rPm_Rx0_AntB					0xbec
+#define rPm_Rx1_AntB					0xbf0
+#define rPm_Rx2_AntB					0xbf4
+#define rPm_Rx3_AntB					0xbf8
+/*
+ * 6. PageC(0xC00)
+ *   */
+#define		rOFDM0_LSTF				0xc00
+
+#define		rOFDM0_TRxPathEnable		0xc04
+#define		rOFDM0_TRMuxPar			0xc08
+#define		rOFDM0_TRSWIsolation		0xc0c
+
+#define		rOFDM0_XARxAFE			0xc10  /* RxIQ DC offset, Rx digital filter, DC notch filter */
+#define		rOFDM0_XARxIQImbalance    	0xc14  /* RxIQ imblance matrix */
+#define		rOFDM0_XBRxAFE		0xc18
+#define		rOFDM0_XBRxIQImbalance	0xc1c
+#define		rOFDM0_XCRxAFE		0xc20
+#define		rOFDM0_XCRxIQImbalance	0xc24
+#define		rOFDM0_XDRxAFE		0xc28
+#define		rOFDM0_XDRxIQImbalance	0xc2c
+
+#define		rOFDM0_RxDetector1			0xc30  /* PD, BW & SBD	 */ /* DM tune init gain */
+#define		rOFDM0_RxDetector2			0xc34  /* SBD & Fame Sync. */
+#define		rOFDM0_RxDetector3			0xc38  /* Frame Sync. */
+#define		rOFDM0_RxDetector4			0xc3c  /* PD, SBD, Frame Sync & Short-GI */
+
+#define		rOFDM0_RxDSP				0xc40  /* Rx Sync Path */
+#define		rOFDM0_CFOandDAGC		0xc44  /* CFO & DAGC */
+#define		rOFDM0_CCADropThreshold	0xc48 /* CCA Drop threshold */
+#define		rOFDM0_ECCAThreshold		0xc4c /* energy CCA */
+
+#define		rOFDM0_XAAGCCore1			0xc50	/* DIG */
+#define		rOFDM0_XAAGCCore2			0xc54
+#define		rOFDM0_XBAGCCore1			0xc58
+#define		rOFDM0_XBAGCCore2			0xc5c
+#define		rOFDM0_XCAGCCore1			0xc60
+#define		rOFDM0_XCAGCCore2			0xc64
+#define		rOFDM0_XDAGCCore1			0xc68
+#define		rOFDM0_XDAGCCore2			0xc6c
+
+#define		rOFDM0_AGCParameter1			0xc70
+#define		rOFDM0_AGCParameter2			0xc74
+#define		rOFDM0_AGCRSSITable			0xc78
+#define		rOFDM0_HTSTFAGC				0xc7c
+
+#define		rOFDM0_XATxIQImbalance		0xc80	/* TX PWR TRACK and DIG */
+#define		rOFDM0_XATxAFE				0xc84
+#define		rOFDM0_XBTxIQImbalance		0xc88
+#define		rOFDM0_XBTxAFE				0xc8c
+#define		rOFDM0_XCTxIQImbalance		0xc90
+#define		rOFDM0_XCTxAFE			0xc94
+#define		rOFDM0_XDTxIQImbalance		0xc98
+#define		rOFDM0_XDTxAFE				0xc9c
+
+#define		rOFDM0_RxIQExtAnta			0xca0
+#define		rOFDM0_TxCoeff1				0xca4
+#define		rOFDM0_TxCoeff2				0xca8
+#define		rOFDM0_TxCoeff3				0xcac
+#define		rOFDM0_TxCoeff4				0xcb0
+#define		rOFDM0_TxCoeff5				0xcb4
+#define		rOFDM0_TxCoeff6				0xcb8
+#define		rOFDM0_RxHPParameter			0xce0
+#define		rOFDM0_TxPseudoNoiseWgt		0xce4
+#define		rOFDM0_FrameSync				0xcf0
+#define		rOFDM0_DFSReport				0xcf4
+
+/*
+ * 7. PageD(0xD00)
+ *   */
+#define		rOFDM1_LSTF					0xd00
+#define		rOFDM1_TRxPathEnable			0xd04
+
+#define		rOFDM1_CFO						0xd08	/* No setting now */
+#define		rOFDM1_CSI1					0xd10
+#define		rOFDM1_SBD						0xd14
+#define		rOFDM1_CSI2					0xd18
+#define		rOFDM1_CFOTracking			0xd2c
+#define		rOFDM1_TRxMesaure1			0xd34
+#define		rOFDM1_IntfDet					0xd3c
+#define		rOFDM1_PseudoNoiseStateAB		0xd50
+#define		rOFDM1_PseudoNoiseStateCD		0xd54
+#define		rOFDM1_RxPseudoNoiseWgt		0xd58
+
+#define		rOFDM_PHYCounter1				0xda0  /* cca, parity fail */
+#define		rOFDM_PHYCounter2				0xda4  /* rate illegal, crc8 fail */
+#define		rOFDM_PHYCounter3				0xda8  /* MCS not support */
+
+#define		rOFDM_ShortCFOAB				0xdac	/* No setting now */
+#define		rOFDM_ShortCFOCD				0xdb0
+#define		rOFDM_LongCFOAB				0xdb4
+#define		rOFDM_LongCFOCD				0xdb8
+#define		rOFDM_TailCFOAB				0xdbc
+#define		rOFDM_TailCFOCD				0xdc0
+#define		rOFDM_PWMeasure1		0xdc4
+#define		rOFDM_PWMeasure2		0xdc8
+#define		rOFDM_BWReport				0xdcc
+#define		rOFDM_AGCReport				0xdd0
+#define		rOFDM_RxSNR					0xdd4
+#define		rOFDM_RxEVMCSI				0xdd8
+#define		rOFDM_SIGReport				0xddc
+
+
+/*
+ * 8. PageE(0xE00)
+ *   */
+#define		rTxAGC_A_Rate18_06			0xe00
+#define		rTxAGC_A_Rate54_24			0xe04
+#define		rTxAGC_A_CCK1_Mcs32			0xe08
+#define		rTxAGC_A_Mcs03_Mcs00			0xe10
+#define		rTxAGC_A_Mcs07_Mcs04			0xe14
+#define		rTxAGC_A_Mcs11_Mcs08			0xe18
+#define		rTxAGC_A_Mcs15_Mcs12			0xe1c
+
+#define		rFPGA0_IQK					0xe28
+#define		rTx_IQK_Tone_A				0xe30
+#define		rRx_IQK_Tone_A				0xe34
+#define		rTx_IQK_PI_A					0xe38
+#define		rRx_IQK_PI_A					0xe3c
+
+#define		rTx_IQK						0xe40
+#define		rRx_IQK						0xe44
+#define		rIQK_AGC_Pts					0xe48
+#define		rIQK_AGC_Rsp					0xe4c
+#define		rTx_IQK_Tone_B				0xe50
+#define		rRx_IQK_Tone_B				0xe54
+#define		rTx_IQK_PI_B					0xe58
+#define		rRx_IQK_PI_B					0xe5c
+#define		rIQK_AGC_Cont				0xe60
+
+#define		rBlue_Tooth					0xe6c
+#define		rRx_Wait_CCA					0xe70
+#define		rTx_CCK_RFON					0xe74
+#define		rTx_CCK_BBON				0xe78
+#define		rTx_OFDM_RFON				0xe7c
+#define		rTx_OFDM_BBON				0xe80
+#define		rTx_To_Rx					0xe84
+#define		rTx_To_Tx					0xe88
+#define		rRx_CCK						0xe8c
+
+#define		rTx_Power_Before_IQK_A		0xe94
+#define		rTx_Power_After_IQK_A			0xe9c
+
+#define		rRx_Power_Before_IQK_A		0xea0
+#define		rRx_Power_Before_IQK_A_2		0xea4
+#define		rRx_Power_After_IQK_A			0xea8
+#define		rRx_Power_After_IQK_A_2		0xeac
+
+#define		rTx_Power_Before_IQK_B		0xeb4
+#define		rTx_Power_After_IQK_B			0xebc
+
+#define		rRx_Power_Before_IQK_B		0xec0
+#define		rRx_Power_Before_IQK_B_2		0xec4
+#define		rRx_Power_After_IQK_B			0xec8
+#define		rRx_Power_After_IQK_B_2		0xecc
+
+#define		rRx_OFDM					0xed0
+#define		rRx_Wait_RIFS				0xed4
+#define		rRx_TO_Rx					0xed8
+#define		rStandby						0xedc
+#define		rSleep						0xee0
+#define		rPMPD_ANAEN				0xeec
+
+/*
+ * 7. RF Register 0x00-0x2E (RF 8256)
+ * RF-0222D 0x00-3F
+ *
+ * Zebra1 */
+#define		rZebra1_HSSIEnable				0x0	/* Useless now */
+#define		rZebra1_TRxEnable1				0x1
+#define		rZebra1_TRxEnable2				0x2
+#define		rZebra1_AGC					0x4
+#define		rZebra1_ChargePump			0x5
+#define		rZebra1_Channel				0x7	/* RF channel switch */
+
+/* #endif */
+#define		rZebra1_TxGain					0x8	/* Useless now */
+#define		rZebra1_TxLPF					0x9
+#define		rZebra1_RxLPF					0xb
+#define		rZebra1_RxHPFCorner			0xc
+
+/* Zebra4 */
+#define		rGlobalCtrl						0	/* Useless now */
+#define		rRTL8256_TxLPF					19
+#define		rRTL8256_RxLPF					11
+
+/* RTL8258 */
+#define		rRTL8258_TxLPF					0x11	/* Useless now */
+#define		rRTL8258_RxLPF					0x13
+#define		rRTL8258_RSSILPF				0xa
+
+/*
+ * RL6052 Register definition
+ *   */
+#define		RF_AC						0x00	/*  */
+
+#define		RF_IQADJ_G1				0x01	/*  */
+#define		RF_IQADJ_G2				0x02	/*  */
+#define		RF_BS_PA_APSET_G1_G4		0x03
+#define		RF_BS_PA_APSET_G5_G8		0x04
+#define		RF_POW_TRSW				0x05	/*  */
+
+#define		RF_GAIN_RX					0x06	/*  */
+#define		RF_GAIN_TX					0x07	/*  */
+
+#define		RF_TXM_IDAC				0x08	/*  */
+#define		RF_IPA_G					0x09	/*  */
+#define		RF_TXBIAS_G				0x0A
+#define		RF_TXPA_AG					0x0B
+#define		RF_IPA_A					0x0C	/*  */
+#define		RF_TXBIAS_A				0x0D
+#define		RF_BS_PA_APSET_G9_G11	0x0E
+#define		RF_BS_IQGEN				0x0F	/*  */
+
+#define		RF_MODE1					0x10	/*  */
+#define		RF_MODE2					0x11	/*  */
+
+#define		RF_RX_AGC_HP				0x12	/*  */
+#define		RF_TX_AGC					0x13	/*  */
+#define		RF_BIAS						0x14	/*  */
+#define		RF_IPA						0x15	/*  */
+#define		RF_TXBIAS					0x16
+#define		RF_POW_ABILITY			0x17	/*  */
+#define		RF_MODE_AG				0x18	/*  */
+#define		rRfChannel					0x18	/* RF channel and BW switch */
+#define		RF_CHNLBW					0x18	/* RF channel and BW switch */
+#define		RF_TOP						0x19	/*  */
+
+#define		RF_RX_G1					0x1A	/*  */
+#define		RF_RX_G2					0x1B	/*  */
+
+#define		RF_RX_BB2					0x1C	/*  */
+#define		RF_RX_BB1					0x1D	/*  */
+
+#define		RF_RCK1					0x1E	/*  */
+#define		RF_RCK2					0x1F	/*  */
+
+#define		RF_TX_G1					0x20	/*  */
+#define		RF_TX_G2					0x21	/*  */
+#define		RF_TX_G3					0x22	/*  */
+
+#define		RF_TX_BB1					0x23	/*  */
+
+#define		RF_T_METER					0x24	/*  */
+
+#define		RF_SYN_G1					0x25	/* RF TX Power control */
+#define		RF_SYN_G2					0x26	/* RF TX Power control */
+#define		RF_SYN_G3					0x27	/* RF TX Power control */
+#define		RF_SYN_G4					0x28	/* RF TX Power control */
+#define		RF_SYN_G5					0x29	/* RF TX Power control */
+#define		RF_SYN_G6					0x2A	/* RF TX Power control */
+#define		RF_SYN_G7					0x2B	/* RF TX Power control */
+#define		RF_SYN_G8					0x2C	/* RF TX Power control */
+
+#define		RF_RCK_OS					0x30	/* RF TX PA control */
+
+#define		RF_TXPA_G1					0x31	/* RF TX PA control */
+#define		RF_TXPA_G2					0x32	/* RF TX PA control */
+#define		RF_TXPA_G3					0x33	/* RF TX PA control */
+#define	RF_TX_BIAS_A				0x35
+#define	RF_TX_BIAS_D				0x36
+#define	RF_LOBF_9					0x38
+#define 	RF_RXRF_A3					0x3C	/*	 */
+#define	RF_TRSW					0x3F
+
+#define	RF_TXRF_A2					0x41
+#define	RF_TXPA_G4					0x46
+#define	RF_TXPA_A4					0x4B
+#define	RF_0x52					0x52
+#define	RF_WE_LUT					0xEF
+#define	RF_S0S1					0xB0
+
+/*
+ * Bit Mask
+ *
+ * 1. Page1(0x100) */
+#define		bBBResetB						0x100	/* Useless now? */
+#define		bGlobalResetB					0x200
+#define		bOFDMTxStart					0x4
+#define		bCCKTxStart						0x8
+#define		bCRC32Debug					0x100
+#define		bPMACLoopback					0x10
+#define		bTxLSIG							0xffffff
+#define		bOFDMTxRate					0xf
+#define		bOFDMTxReserved				0x10
+#define		bOFDMTxLength					0x1ffe0
+#define		bOFDMTxParity					0x20000
+#define		bTxHTSIG1						0xffffff
+#define		bTxHTMCSRate					0x7f
+#define		bTxHTBW						0x80
+#define		bTxHTLength					0xffff00
+#define		bTxHTSIG2						0xffffff
+#define		bTxHTSmoothing					0x1
+#define		bTxHTSounding					0x2
+#define		bTxHTReserved					0x4
+#define		bTxHTAggreation				0x8
+#define		bTxHTSTBC						0x30
+#define		bTxHTAdvanceCoding			0x40
+#define		bTxHTShortGI					0x80
+#define		bTxHTNumberHT_LTF			0x300
+#define		bTxHTCRC8						0x3fc00
+#define		bCounterReset					0x10000
+#define		bNumOfOFDMTx					0xffff
+#define		bNumOfCCKTx					0xffff0000
+#define		bTxIdleInterval					0xffff
+#define		bOFDMService					0xffff0000
+#define		bTxMACHeader					0xffffffff
+#define		bTxDataInit						0xff
+#define		bTxHTMode						0x100
+#define		bTxDataType					0x30000
+#define		bTxRandomSeed					0xffffffff
+#define		bCCKTxPreamble					0x1
+#define		bCCKTxSFD						0xffff0000
+#define		bCCKTxSIG						0xff
+#define		bCCKTxService					0xff00
+#define		bCCKLengthExt					0x8000
+#define		bCCKTxLength					0xffff0000
+#define		bCCKTxCRC16					0xffff
+#define		bCCKTxStatus					0x1
+#define		bOFDMTxStatus					0x2
+
+#define		IS_BB_REG_OFFSET_92S(_Offset)		((_Offset >= 0x800) && (_Offset <= 0xfff))
+#define	RF_TX_GAIN_OFFSET_8703B(_val) (abs((_val)) | (((_val) > 0) ? BIT5 : 0))
+
+/* 2. Page8(0x800) */
+#define		bRFMOD							0x1	/* Reg 0x800 rFPGA0_RFMOD */
+#define		bJapanMode						0x2
+#define		bCCKTxSC						0x30
+#define		bCCKEn							0x1000000
+#define		bOFDMEn						0x2000000
+
+#define		bOFDMRxADCPhase           		0x10000	/* Useless now */
+#define		bOFDMTxDACPhase		0x40000
+#define		bXATxAGC			0x3f
+
+#define		bAntennaSelect		0x0300
+
+#define		bXBTxAGC                  			0xf00	/* Reg 80c rFPGA0_TxGainStage */
+#define		bXCTxAGC			0xf000
+#define		bXDTxAGC			0xf0000
+
+#define		bPAStart                  			0xf0000000	/* Useless now */
+#define		bTRStart			0x00f00000
+#define		bRFStart			0x0000f000
+#define		bBBStart			0x000000f0
+#define		bBBCCKStart		0x0000000f
+#define		bPAEnd                    			0xf          /* Reg0x814 */
+#define		bTREnd			0x0f000000
+#define		bRFEnd			0x000f0000
+#define		bCCAMask                  			0x000000f0   /* T2R */
+#define		bR2RCCAMask		0x00000f00
+#define		bHSSI_R2TDelay		0xf8000000
+#define		bHSSI_T2RDelay		0xf80000
+#define		bContTxHSSI               		0x400     /* chane gain at continue Tx */
+#define		bIGFromCCK		0x200
+#define		bAGCAddress		0x3f
+#define		bRxHPTx			0x7000
+#define		bRxHPT2R			0x38000
+#define		bRxHPCCKIni		0xc0000
+#define		bAGCTxCode		0xc00000
+#define		bAGCRxCode		0x300000
+
+#define		b3WireDataLength          		0x800	/* Reg 0x820~84f rFPGA0_XA_HSSIParameter1 */
+#define		b3WireAddressLength		0x400
+
+#define		b3WireRFPowerDown         		0x1	/* Useless now
+ * #define bHWSISelect		0x8 */
+#define		b5GPAPEPolarity		0x40000000
+#define		b2GPAPEPolarity		0x80000000
+#define		bRFSW_TxDefaultAnt		0x3
+#define		bRFSW_TxOptionAnt		0x30
+#define		bRFSW_RxDefaultAnt		0x300
+#define		bRFSW_RxOptionAnt		0x3000
+#define		bRFSI_3WireData		0x1
+#define		bRFSI_3WireClock		0x2
+#define		bRFSI_3WireLoad		0x4
+#define		bRFSI_3WireRW		0x8
+#define		bRFSI_3Wire			0xf
+
+#define		bRFSI_RFENV               		0x10	/* Reg 0x870 rFPGA0_XAB_RFInterfaceSW */
+
+#define		bRFSI_TRSW                		0x20	/* Useless now */
+#define		bRFSI_TRSWB		0x40
+#define		bRFSI_ANTSW		0x100
+#define		bRFSI_ANTSWB		0x200
+#define		bRFSI_PAPE			0x400
+#define		bRFSI_PAPE5G		0x800
+#define		bBandSelect			0x1
+#define		bHTSIG2_GI			0x80
+#define		bHTSIG2_Smoothing		0x01
+#define		bHTSIG2_Sounding		0x02
+#define		bHTSIG2_Aggreaton		0x08
+#define		bHTSIG2_STBC		0x30
+#define		bHTSIG2_AdvCoding		0x40
+#define		bHTSIG2_NumOfHTLTF	0x300
+#define		bHTSIG2_CRC8		0x3fc
+#define		bHTSIG1_MCS		0x7f
+#define		bHTSIG1_BandWidth		0x80
+#define		bHTSIG1_HTLength		0xffff
+#define		bLSIG_Rate			0xf
+#define		bLSIG_Reserved		0x10
+#define		bLSIG_Length		0x1fffe
+#define		bLSIG_Parity			0x20
+#define		bCCKRxPhase		0x4
+
+#define		bLSSIReadAddress          		0x7f800000   /* T65 RF */
+
+#define		bLSSIReadEdge             		0x80000000   /* LSSI "Read" edge signal */
+
+#define		bLSSIReadBackData         		0xfffff		/* T65 RF */
+
+#define		bLSSIReadOKFlag           		0x1000	/* Useless now */
+#define		bCCKSampleRate            		0x8       /* 0: 44MHz, 1:88MHz      		 */
+#define		bRegulator0Standby		0x1
+#define		bRegulatorPLLStandby		0x2
+#define		bRegulator1Standby		0x4
+#define		bPLLPowerUp		0x8
+#define		bDPLLPowerUp		0x10
+#define		bDA10PowerUp		0x20
+#define		bAD7PowerUp		0x200
+#define		bDA6PowerUp		0x2000
+#define		bXtalPowerUp		0x4000
+#define		b40MDClkPowerUP		0x8000
+#define		bDA6DebugMode		0x20000
+#define		bDA6Swing			0x380000
+
+#define		bADClkPhase               		0x4000000	/* Reg 0x880 rFPGA0_AnalogParameter1 20/40 CCK support switch 40/80 BB MHZ */
+
+#define		b80MClkDelay              		0x18000000	/* Useless */
+#define		bAFEWatchDogEnable		0x20000000
+
+#define		bXtalCap01                			0xc0000000	/* Reg 0x884 rFPGA0_AnalogParameter2 Crystal cap */
+#define		bXtalCap23			0x3
+#define		bXtalCap92x					0x0f000000
+#define		bXtalCap			0x0f000000
+
+#define		bIntDifClkEnable          		0x400	/* Useless */
+#define		bExtSigClkEnable		0x800
+#define		bBandgapMbiasPowerUp	0x10000
+#define		bAD11SHGain		0xc0000
+#define		bAD11InputRange		0x700000
+#define		bAD11OPCurrent		0x3800000
+#define		bIPathLoopback		0x4000000
+#define		bQPathLoopback		0x8000000
+#define		bAFELoopback		0x10000000
+#define		bDA10Swing		0x7e0
+#define		bDA10Reverse		0x800
+#define		bDAClkSource		0x1000
+#define		bAD7InputRange		0x6000
+#define		bAD7Gain			0x38000
+#define		bAD7OutputCMMode		0x40000
+#define		bAD7InputCMMode		0x380000
+#define		bAD7Current			0xc00000
+#define		bRegulatorAdjust		0x7000000
+#define		bAD11PowerUpAtTx		0x1
+#define		bDA10PSAtTx		0x10
+#define		bAD11PowerUpAtRx		0x100
+#define		bDA10PSAtRx		0x1000
+#define		bCCKRxAGCFormat		0x200
+#define		bPSDFFTSamplepPoint		0xc000
+#define		bPSDAverageNum		0x3000
+#define		bIQPathControl		0xc00
+#define		bPSDFreq			0x3ff
+#define		bPSDAntennaPath		0x30
+#define		bPSDIQSwitch		0x40
+#define		bPSDRxTrigger		0x400000
+#define		bPSDTxTrigger		0x80000000
+#define		bPSDSineToneScale		0x7f000000
+#define		bPSDReport			0xffff
+
+/* 3. Page9(0x900) */
+#define		bOFDMTxSC                 		0x30000000	/* Useless */
+#define		bCCKTxOn			0x1
+#define		bOFDMTxOn		0x2
+#define		bDebugPage                		0xfff  /* reset debug page and also HWord, LWord */
+#define		bDebugItem                		0xff   /* reset debug page and LWord */
+#define		bAntL			0x10
+#define		bAntNonHT				0x100
+#define		bAntHT1			0x1000
+#define		bAntHT2			0x10000
+#define		bAntHT1S1			0x100000
+#define		bAntNonHTS1		0x1000000
+
+/* 4. PageA(0xA00) */
+#define		bCCKBBMode				0x3	/* Useless */
+#define		bCCKTxPowerSaving		0x80
+#define		bCCKRxPowerSaving		0x40
+
+#define		bCCKSideBand			0x10	/* Reg 0xa00 rCCK0_System 20/40 switch */
+
+#define		bCCKScramble			0x8	/* Useless */
+#define		bCCKAntDiversity		0x8000
+#define		bCCKCarrierRecovery		0x4000
+#define		bCCKTxRate				0x3000
+#define		bCCKDCCancel			0x0800
+#define		bCCKISICancel			0x0400
+#define		bCCKMatchFilter			0x0200
+#define		bCCKEqualizer			0x0100
+#define		bCCKPreambleDetect		0x800000
+#define		bCCKFastFalseCCA		0x400000
+#define		bCCKChEstStart			0x300000
+#define		bCCKCCACount			0x080000
+#define		bCCKcs_lim				0x070000
+#define		bCCKBistMode			0x80000000
+#define		bCCKCCAMask			0x40000000
+#define		bCCKTxDACPhase		0x4
+#define		bCCKRxADCPhase		0x20000000   /* r_rx_clk */
+#define		bCCKr_cp_mode0		0x0100
+#define		bCCKTxDCOffset			0xf0
+#define		bCCKRxDCOffset			0xf
+#define		bCCKCCAMode			0xc000
+#define		bCCKFalseCS_lim			0x3f00
+#define		bCCKCS_ratio			0xc00000
+#define		bCCKCorgBit_sel			0x300000
+#define		bCCKPD_lim				0x0f0000
+#define		bCCKNewCCA			0x80000000
+#define		bCCKRxHPofIG			0x8000
+#define		bCCKRxIG				0x7f00
+#define		bCCKLNAPolarity			0x800000
+#define		bCCKRx1stGain			0x7f0000
+#define		bCCKRFExtend			0x20000000 /* CCK Rx Iinital gain polarity */
+#define		bCCKRxAGCSatLevel		0x1f000000
+#define		bCCKRxAGCSatCount		0xe0
+#define		bCCKRxRFSettle			0x1f       /* AGCsamp_dly */
+#define		bCCKFixedRxAGC			0x8000
+/* #define bCCKRxAGCFormat		0x4000 */   /* remove to HSSI register 0x824 */
+#define		bCCKAntennaPolarity		0x2000
+#define		bCCKTxFilterType		0x0c00
+#define		bCCKRxAGCReportType	0x0300
+#define		bCCKRxDAGCEn			0x80000000
+#define		bCCKRxDAGCPeriod		0x20000000
+#define		bCCKRxDAGCSatLevel		0x1f000000
+#define		bCCKTimingRecovery		0x800000
+#define		bCCKTxC0				0x3f0000
+#define		bCCKTxC1				0x3f000000
+#define		bCCKTxC2				0x3f
+#define		bCCKTxC3				0x3f00
+#define		bCCKTxC4				0x3f0000
+#define		bCCKTxC5				0x3f000000
+#define		bCCKTxC6				0x3f
+#define		bCCKTxC7				0x3f00
+#define		bCCKDebugPort			0xff0000
+#define		bCCKDACDebug			0x0f000000
+#define		bCCKFalseAlarmEnable	0x8000
+#define		bCCKFalseAlarmRead		0x4000
+#define		bCCKTRSSI				0x7f
+#define		bCCKRxAGCReport		0xfe
+#define		bCCKRxReport_AntSel	0x80000000
+#define		bCCKRxReport_MFOff		0x40000000
+#define		bCCKRxRxReport_SQLoss	0x20000000
+#define		bCCKRxReport_Pktloss	0x10000000
+#define		bCCKRxReport_Lockedbit	0x08000000
+#define		bCCKRxReport_RateError	0x04000000
+#define		bCCKRxReport_RxRate	0x03000000
+#define		bCCKRxFACounterLower	0xff
+#define		bCCKRxFACounterUpper	0xff000000
+#define		bCCKRxHPAGCStart		0xe000
+#define		bCCKRxHPAGCFinal		0x1c00
+#define		bCCKRxFalseAlarmEnable	0x8000
+#define		bCCKFACounterFreeze	0x4000
+#define		bCCKTxPathSel			0x10000000
+#define		bCCKDefaultRxPath		0xc000000
+#define		bCCKOptionRxPath		0x3000000
+
+/* 5. PageC(0xC00) */
+#define		bNumOfSTF				0x3	/* Useless */
+#define		bShift_L					0xc0
+#define		bGI_TH					0xc
+#define		bRxPathA				0x1
+#define		bRxPathB				0x2
+#define		bRxPathC				0x4
+#define		bRxPathD				0x8
+#define		bTxPathA				0x1
+#define		bTxPathB				0x2
+#define		bTxPathC				0x4
+#define		bTxPathD				0x8
+#define		bTRSSIFreq				0x200
+#define		bADCBackoff				0x3000
+#define		bDFIRBackoff			0xc000
+#define		bTRSSILatchPhase		0x10000
+#define		bRxIDCOffset			0xff
+#define		bRxQDCOffset			0xff00
+#define		bRxDFIRMode			0x1800000
+#define		bRxDCNFType			0xe000000
+#define		bRXIQImb_A				0x3ff
+#define		bRXIQImb_B				0xfc00
+#define		bRXIQImb_C				0x3f0000
+#define		bRXIQImb_D				0xffc00000
+#define		bDC_dc_Notch			0x60000
+#define		bRxNBINotch			0x1f000000
+#define		bPD_TH					0xf
+#define		bPD_TH_Opt2			0xc000
+#define		bPWED_TH				0x700
+#define		bIfMF_Win_L			0x800
+#define		bPD_Option				0x1000
+#define		bMF_Win_L				0xe000
+#define		bBW_Search_L			0x30000
+#define		bwin_enh_L				0xc0000
+#define		bBW_TH					0x700000
+#define		bED_TH2				0x3800000
+#define		bBW_option				0x4000000
+#define		bRatio_TH				0x18000000
+#define		bWindow_L				0xe0000000
+#define		bSBD_Option				0x1
+#define		bFrame_TH				0x1c
+#define		bFS_Option				0x60
+#define		bDC_Slope_check		0x80
+#define		bFGuard_Counter_DC_L	0xe00
+#define		bFrame_Weight_Short	0x7000
+#define		bSub_Tune				0xe00000
+#define		bFrame_DC_Length		0xe000000
+#define		bSBD_start_offset		0x30000000
+#define		bFrame_TH_2			0x7
+#define		bFrame_GI2_TH			0x38
+#define		bGI2_Sync_en			0x40
+#define		bSarch_Short_Early		0x300
+#define		bSarch_Short_Late		0xc00
+#define		bSarch_GI2_Late		0x70000
+#define		bCFOAntSum				0x1
+#define		bCFOAcc				0x2
+#define		bCFOStartOffset			0xc
+#define		bCFOLookBack			0x70
+#define		bCFOSumWeight			0x80
+#define		bDAGCEnable			0x10000
+#define		bTXIQImb_A				0x3ff
+#define		bTXIQImb_B				0xfc00
+#define		bTXIQImb_C				0x3f0000
+#define		bTXIQImb_D				0xffc00000
+#define		bTxIDCOffset			0xff
+#define		bTxQDCOffset			0xff00
+#define		bTxDFIRMode			0x10000
+#define		bTxPesudoNoiseOn		0x4000000
+#define		bTxPesudoNoise_A		0xff
+#define		bTxPesudoNoise_B		0xff00
+#define		bTxPesudoNoise_C		0xff0000
+#define		bTxPesudoNoise_D		0xff000000
+#define		bCCADropOption			0x20000
+#define		bCCADropThres			0xfff00000
+#define		bEDCCA_H				0xf
+#define		bEDCCA_L				0xf0
+#define		bLambda_ED			0x300
+#define		bRxInitialGain			0x7f
+#define		bRxAntDivEn				0x80
+#define		bRxAGCAddressForLNA	0x7f00
+#define		bRxHighPowerFlow		0x8000
+#define		bRxAGCFreezeThres		0xc0000
+#define		bRxFreezeStep_AGC1	0x300000
+#define		bRxFreezeStep_AGC2	0xc00000
+#define		bRxFreezeStep_AGC3	0x3000000
+#define		bRxFreezeStep_AGC0	0xc000000
+#define		bRxRssi_Cmp_En			0x10000000
+#define		bRxQuickAGCEn			0x20000000
+#define		bRxAGCFreezeThresMode	0x40000000
+#define		bRxOverFlowCheckType	0x80000000
+#define		bRxAGCShift				0x7f
+#define		bTRSW_Tri_Only			0x80
+#define		bPowerThres			0x300
+#define		bRxAGCEn				0x1
+#define		bRxAGCTogetherEn		0x2
+#define		bRxAGCMin				0x4
+#define		bRxHP_Ini				0x7
+#define		bRxHP_TRLNA			0x70
+#define		bRxHP_RSSI				0x700
+#define		bRxHP_BBP1				0x7000
+#define		bRxHP_BBP2				0x70000
+#define		bRxHP_BBP3				0x700000
+#define		bRSSI_H					0x7f0000     /* the threshold for high power */
+#define		bRSSI_Gen				0x7f000000   /* the threshold for ant diversity */
+#define		bRxSettle_TRSW			0x7
+#define		bRxSettle_LNA			0x38
+#define		bRxSettle_RSSI			0x1c0
+#define		bRxSettle_BBP			0xe00
+#define		bRxSettle_RxHP			0x7000
+#define		bRxSettle_AntSW_RSSI	0x38000
+#define		bRxSettle_AntSW		0xc0000
+#define		bRxProcessTime_DAGC	0x300000
+#define		bRxSettle_HSSI			0x400000
+#define		bRxProcessTime_BBPPW	0x800000
+#define		bRxAntennaPowerShift	0x3000000
+#define		bRSSITableSelect		0xc000000
+#define		bRxHP_Final				0x7000000
+#define		bRxHTSettle_BBP			0x7
+#define		bRxHTSettle_HSSI		0x8
+#define		bRxHTSettle_RxHP		0x70
+#define		bRxHTSettle_BBPPW		0x80
+#define		bRxHTSettle_Idle		0x300
+#define		bRxHTSettle_Reserved	0x1c00
+#define		bRxHTRxHPEn			0x8000
+#define		bRxHTAGCFreezeThres	0x30000
+#define		bRxHTAGCTogetherEn	0x40000
+#define		bRxHTAGCMin			0x80000
+#define		bRxHTAGCEn				0x100000
+#define		bRxHTDAGCEn			0x200000
+#define		bRxHTRxHP_BBP			0x1c00000
+#define		bRxHTRxHP_Final		0xe0000000
+#define		bRxPWRatioTH			0x3
+#define		bRxPWRatioEn			0x4
+#define		bRxMFHold				0x3800
+#define		bRxPD_Delay_TH1		0x38
+#define		bRxPD_Delay_TH2		0x1c0
+#define		bRxPD_DC_COUNT_MAX	0x600
+/* #define bRxMF_Hold               0x3800 */
+#define		bRxPD_Delay_TH			0x8000
+#define		bRxProcess_Delay		0xf0000
+#define		bRxSearchrange_GI2_Early	0x700000
+#define		bRxFrame_Guard_Counter_L	0x3800000
+#define		bRxSGI_Guard_L			0xc000000
+#define		bRxSGI_Search_L		0x30000000
+#define		bRxSGI_TH				0xc0000000
+#define		bDFSCnt0				0xff
+#define		bDFSCnt1				0xff00
+#define		bDFSFlag				0xf0000
+#define		bMFWeightSum			0x300000
+#define		bMinIdxTH				0x7f000000
+#define		bDAFormat				0x40000
+#define		bTxChEmuEnable		0x01000000
+#define		bTRSWIsolation_A		0x7f
+#define		bTRSWIsolation_B		0x7f00
+#define		bTRSWIsolation_C		0x7f0000
+#define		bTRSWIsolation_D		0x7f000000
+#define		bExtLNAGain				0x7c00
+
+/* 6. PageE(0xE00) */
+#define		bSTBCEn				0x4	/* Useless */
+#define		bAntennaMapping		0x10
+#define		bNss					0x20
+#define		bCFOAntSumD			0x200
+#define		bPHYCounterReset		0x8000000
+#define		bCFOReportGet			0x4000000
+#define		bOFDMContinueTx		0x10000000
+#define		bOFDMSingleCarrier		0x20000000
+#define		bOFDMSingleTone		0x40000000
+/* #define bRxPath1                 0x01 */
+/* #define bRxPath2                 0x02 */
+/* #define bRxPath3                 0x04 */
+/* #define bRxPath4                 0x08 */
+/* #define bTxPath1                 0x10 */
+/* #define bTxPath2                 0x20 */
+#define		bHTDetect			0x100
+#define		bCFOEn				0x10000
+#define		bCFOValue			0xfff00000
+#define		bSigTone_Re		0x3f
+#define		bSigTone_Im		0x7f00
+#define		bCounter_CCA		0xffff
+#define		bCounter_ParityFail	0xffff0000
+#define		bCounter_RateIllegal		0xffff
+#define		bCounter_CRC8Fail	0xffff0000
+#define		bCounter_MCSNoSupport	0xffff
+#define		bCounter_FastSync	0xffff
+#define		bShortCFO			0xfff
+#define		bShortCFOTLength	12   /* total */
+#define		bShortCFOFLength	11   /* fraction */
+#define		bLongCFO			0x7ff
+#define		bLongCFOTLength	11
+#define		bLongCFOFLength	11
+#define		bTailCFO			0x1fff
+#define		bTailCFOTLength		13
+#define		bTailCFOFLength		12
+#define		bmax_en_pwdB		0xffff
+#define		bCC_power_dB		0xffff0000
+#define		bnoise_pwdB		0xffff
+#define		bPowerMeasTLength	10
+#define		bPowerMeasFLength	3
+#define		bRx_HT_BW			0x1
+#define		bRxSC				0x6
+#define		bRx_HT				0x8
+#define		bNB_intf_det_on		0x1
+#define		bIntf_win_len_cfg	0x30
+#define		bNB_Intf_TH_cfg		0x1c0
+#define		bRFGain				0x3f
+#define		bTableSel			0x40
+#define		bTRSW				0x80
+#define		bRxSNR_A			0xff
+#define		bRxSNR_B			0xff00
+#define		bRxSNR_C			0xff0000
+#define		bRxSNR_D			0xff000000
+#define		bSNREVMTLength		8
+#define		bSNREVMFLength		1
+#define		bCSI1st				0xff
+#define		bCSI2nd				0xff00
+#define		bRxEVM1st			0xff0000
+#define		bRxEVM2nd			0xff000000
+#define		bSIGEVM			0xff
+#define		bPWDB				0xff00
+#define		bSGIEN				0x10000
+
+#define		bSFactorQAM1		0xf	/* Useless */
+#define		bSFactorQAM2		0xf0
+#define		bSFactorQAM3		0xf00
+#define		bSFactorQAM4		0xf000
+#define		bSFactorQAM5		0xf0000
+#define		bSFactorQAM6		0xf0000
+#define		bSFactorQAM7		0xf00000
+#define		bSFactorQAM8		0xf000000
+#define		bSFactorQAM9		0xf0000000
+#define		bCSIScheme			0x100000
+
+#define		bNoiseLvlTopSet		0x3	/* Useless */
+#define		bChSmooth			0x4
+#define		bChSmoothCfg1		0x38
+#define		bChSmoothCfg2		0x1c0
+#define		bChSmoothCfg3		0xe00
+#define		bChSmoothCfg4		0x7000
+#define		bMRCMode			0x800000
+#define		bTHEVMCfg			0x7000000
+
+#define		bLoopFitType		0x1	/* Useless */
+#define		bUpdCFO			0x40
+#define		bUpdCFOOffData		0x80
+#define		bAdvUpdCFO			0x100
+#define		bAdvTimeCtrl		0x800
+#define		bUpdClko			0x1000
+#define		bFC					0x6000
+#define		bTrackingMode		0x8000
+#define		bPhCmpEnable		0x10000
+#define		bUpdClkoLTF		0x20000
+#define		bComChCFO			0x40000
+#define		bCSIEstiMode		0x80000
+#define		bAdvUpdEqz			0x100000
+#define		bUChCfg				0x7000000
+#define		bUpdEqz			0x8000000
+
+/* Rx Pseduo noise */
+#define		bRxPesudoNoiseOn		0x20000000	/* Useless */
+#define		bRxPesudoNoise_A		0xff
+#define		bRxPesudoNoise_B		0xff00
+#define		bRxPesudoNoise_C		0xff0000
+#define		bRxPesudoNoise_D		0xff000000
+#define		bPesudoNoiseState_A	0xffff
+#define		bPesudoNoiseState_B	0xffff0000
+#define		bPesudoNoiseState_C	0xffff
+#define		bPesudoNoiseState_D	0xffff0000
+
+/* 7. RF Register
+ * Zebra1 */
+#define		bZebra1_HSSIEnable		0x8		/* Useless */
+#define		bZebra1_TRxControl		0xc00
+#define		bZebra1_TRxGainSetting	0x07f
+#define		bZebra1_RxCorner		0xc00
+#define		bZebra1_TxChargePump	0x38
+#define		bZebra1_RxChargePump	0x7
+#define		bZebra1_ChannelNum	0xf80
+#define		bZebra1_TxLPFBW		0x400
+#define		bZebra1_RxLPFBW		0x600
+
+/* Zebra4 */
+#define		bRTL8256RegModeCtrl1	0x100	/* Useless */
+#define		bRTL8256RegModeCtrl0	0x40
+#define		bRTL8256_TxLPFBW		0x18
+#define		bRTL8256_RxLPFBW		0x600
+
+/* RTL8258 */
+#define		bRTL8258_TxLPFBW		0xc	/* Useless */
+#define		bRTL8258_RxLPFBW		0xc00
+#define		bRTL8258_RSSILPFBW	0xc0
+
+
+/*
+ * Other Definition
+ *   */
+
+/* byte endable for sb_write */
+#define		bByte0				0x1	/* Useless */
+#define		bByte1				0x2
+#define		bByte2				0x4
+#define		bByte3				0x8
+#define		bWord0				0x3
+#define		bWord1				0xc
+#define		bDWord				0xf
+
+/* for PutRegsetting & GetRegSetting BitMask */
+#define		bMaskByte0			0xff	/* Reg 0xc50 rOFDM0_XAAGCCore~0xC6f */
+#define		bMaskByte1			0xff00
+#define		bMaskByte2			0xff0000
+#define		bMaskByte3			0xff000000
+#define		bMaskHWord		0xffff0000
+#define		bMaskLWord			0x0000ffff
+#define		bMaskDWord		0xffffffff
+#define		bMaskH3Bytes		0xffffff00
+#define		bMask12Bits			0xfff
+#define		bMaskH4Bits			0xf0000000
+#define		bMaskOFDM_D		0xffc00000
+#define		bMaskCCK			0x3f3f3f3f
+
+
+#define		bEnable			0x1	/* Useless */
+#define		bDisable		0x0
+
+#define		LeftAntenna		0x0	/* Useless */
+#define		RightAntenna	0x1
+
+#define		tCheckTxStatus		500   /* 500ms */ /* Useless */
+#define		tUpdateRxCounter	100   /* 100ms */
+
+#define		rateCCK		0	/* Useless */
+#define		rateOFDM	1
+#define		rateHT		2
+
+/* define Register-End */
+#define		bPMAC_End			0x1ff	/* Useless */
+#define		bFPGAPHY0_End		0x8ff
+#define		bFPGAPHY1_End		0x9ff
+#define		bCCKPHY0_End		0xaff
+#define		bOFDMPHY0_End		0xcff
+#define		bOFDMPHY1_End		0xdff
+
+/* define max debug item in each debug page
+ * #define bMaxItem_FPGA_PHY0        0x9
+ * #define bMaxItem_FPGA_PHY1        0x3
+ * #define bMaxItem_PHY_11B          0x16
+ * #define bMaxItem_OFDM_PHY0        0x29
+ * #define bMaxItem_OFDM_PHY1        0x0 */
+
+#define		bPMACControl		0x0		/* Useless */
+#define		bWMACControl		0x1
+#define		bWNICControl		0x2
+
+#define		PathA			0x0	/* Useless */
+#define		PathB			0x1
+#define		PathC			0x2
+#define		PathD			0x3
+
+#endif
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/include/Hal8703BPwrSeq.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/Hal8703BPwrSeq.h
--- linux-5.6.3/3rdparty/rtl8821ce/include/Hal8703BPwrSeq.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/Hal8703BPwrSeq.h	2020-04-10 16:35:06.844661375 +0300
@@ -0,0 +1,198 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2016 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#ifndef REALTEK_POWER_SEQUENCE_8703B
+#define REALTEK_POWER_SEQUENCE_8703B
+
+#include "HalPwrSeqCmd.h"
+
+/*
+	Check document WM-20140402-JackieLau-RTL8703B_Power_Architecture v09.vsd
+	There are 6 HW Power States:
+	0: POFF--Power Off
+	1: PDN--Power Down
+	2: CARDEMU--Card Emulation
+	3: ACT--Active Mode
+	4: LPS--Low Power State
+	5: SUS--Suspend
+
+	The transision from different states are defined below
+	TRANS_CARDEMU_TO_ACT
+	TRANS_ACT_TO_CARDEMU
+	TRANS_CARDEMU_TO_SUS
+	TRANS_SUS_TO_CARDEMU
+	TRANS_CARDEMU_TO_PDN
+	TRANS_ACT_TO_LPS
+	TRANS_LPS_TO_ACT
+
+	TRANS_END
+*/
+#define	RTL8703B_TRANS_CARDEMU_TO_ACT_STEPS	23
+#define	RTL8703B_TRANS_ACT_TO_CARDEMU_STEPS	15
+#define	RTL8703B_TRANS_CARDEMU_TO_SUS_STEPS	15
+#define	RTL8703B_TRANS_SUS_TO_CARDEMU_STEPS	15
+#define	RTL8703B_TRANS_CARDEMU_TO_PDN_STEPS	15
+#define	RTL8703B_TRANS_PDN_TO_CARDEMU_STEPS	15
+#define	RTL8703B_TRANS_ACT_TO_LPS_STEPS		15
+#define	RTL8703B_TRANS_LPS_TO_ACT_STEPS		15
+#define	RTL8703B_TRANS_END_STEPS		1
+
+
+#define RTL8703B_TRANS_CARDEMU_TO_ACT														\
+	/* format */																\
+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
+	{0x0020, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0}, /*0x20[0] = 1b'1 enable LDOA12 MACRO block for all interface*/   \
+	{0x0067, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0}, /*0x67[0] = 0 to disable BT_GPS_SEL pins*/	\
+	{0x0001, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_DELAY, 1, PWRSEQ_DELAY_MS},/*Delay 1ms*/   \
+	{0x0000, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT5, 0}, /*0x00[5] = 1b'0 release analog Ips to digital ,1:isolation*/   \
+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, (BIT4 | BIT3 | BIT2), 0},/* disable SW LPS 0x04[10]=0 and WLSUS_EN 0x04[11]=0*/	\
+	{0x0075, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0 , BIT0},/* Disable USB suspend */	\
+	{0x0004, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 , BIT3},/* enabled usb resume */	\
+	{0x0004, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 , 0},/* disable usb resume */	\
+	{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT1, BIT1},/* wait till 0x04[17] = 1    power ready*/	\
+	{0x0075, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0 , 0},/* Enable USB suspend */	\
+	{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0},/* release WLON reset  0x04[16]=1*/	\
+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, 0},/* disable HWPDN 0x04[15]=0*/	\
+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, (BIT4 | BIT3), 0},/* disable WL suspend*/	\
+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0},/* polling until return 0*/	\
+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT0, 0},/**/	\
+	{0x0010, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT6, BIT6},/* Enable WL control XTAL setting*/	\
+	{0x0049, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1},/*Enable falling edge triggering interrupt*/\
+	{0x0063, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1},/*Enable GPIO9 interrupt mode*/\
+	{0x0062, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0},/*Enable GPIO9 input mode*/\
+	{0x0058, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0},/*Enable HSISR GPIO[C:0] interrupt*/\
+	{0x005A, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1},/*Enable HSISR GPIO9 interrupt*/\
+	{0x0068, PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3, BIT3},/*For GPIO9 internal pull high setting by test chip*/\
+	{0x0069, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT6, BIT6},/*For GPIO9 internal pull high setting*/\
+
+
+#define RTL8703B_TRANS_ACT_TO_CARDEMU													\
+	/* format */																\
+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
+	{0x001F, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0},/*0x1F[7:0] = 0 turn off RF*/	\
+	{0x0049, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0},/*Enable rising edge triggering interrupt*/ \
+	{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0},/* release WLON reset  0x04[16]=1*/	\
+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1}, /*0x04[9] = 1 turn off MAC by HW state machine*/	\
+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT1, 0}, /*wait till 0x04[9] = 0 polling until return 0 to disable*/	\
+	{0x0010, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT6, 0},/* Enable BT control XTAL setting*/\
+	{0x0000, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT5, BIT5}, /*0x00[5] = 1b'1 analog Ips to digital ,1:isolation*/   \
+	{0x0020, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0}, /*0x20[0] = 1b'0 disable LDOA12 MACRO block*/\
+
+
+#define RTL8703B_TRANS_CARDEMU_TO_SUS													\
+	/* format */																\
+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4 | BIT3, (BIT4 | BIT3)}, /*0x04[12:11] = 2b'11 enable WL suspend for PCIe*/	\
+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT4, BIT3}, /*0x04[12:11] = 2b'01 enable WL suspend*/	\
+	{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, BIT4}, /*0x23[4] = 1b'1 12H LDO enter sleep mode*/   \
+	{0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x20}, /*0x07[7:0] = 0x20 SDIO SOP option to disable BG/MB/ACK/SWR*/   \
+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT4, BIT3 | BIT4}, /*0x04[12:11] = 2b'11 enable WL suspend for PCIe*/	\
+	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT0, BIT0}, /*Set SDIO suspend local register*/	\
+	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, 0}, /*wait power state to suspend*/
+
+#define RTL8703B_TRANS_SUS_TO_CARDEMU													\
+	/* format */																\
+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT7, 0}, /*clear suspend enable and power down enable*/	\
+	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT0, 0}, /*Set SDIO suspend local register*/	\
+	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, BIT1}, /*wait power state to suspend*/\
+	{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0}, /*0x23[4] = 1b'0 12H LDO enter normal mode*/   \
+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT4, 0}, /*0x04[12:11] = 2b'01enable WL suspend*/
+
+#define RTL8703B_TRANS_CARDEMU_TO_CARDDIS													\
+	/* format */																\
+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
+	{0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x20}, /*0x07 = 0x20 , SOP option to disable BG/MB*/	\
+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT4, BIT3}, /*0x04[12:11] = 2b'01 enable WL suspend*/	\
+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, BIT2}, /*0x04[10] = 1, enable SW LPS*/	\
+	{0x004A, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 1}, /*0x48[16] = 1 to enable GPIO9 as EXT WAKEUP*/   \
+	{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, BIT4}, /*0x23[4] = 1b'1 12H LDO enter sleep mode*/   \
+	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT0, BIT0}, /*Set SDIO suspend local register*/	\
+	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, 0}, /*wait power state to suspend*/
+
+#define RTL8703B_TRANS_CARDDIS_TO_CARDEMU													\
+	/* format */																\
+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT7, 0}, /*clear suspend enable and power down enable*/	\
+	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT0, 0}, /*Set SDIO suspend local register*/	\
+	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, BIT1}, /*wait power state to suspend*/\
+	{0x004A, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0}, /*0x48[16] = 0 to disable GPIO9 as EXT WAKEUP*/   \
+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT4, 0}, /*0x04[12:11] = 2b'01enable WL suspend*/\
+	{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0}, /*0x23[4] = 1b'0 12H LDO enter normal mode*/   \
+	{0x0301, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0},/*PCIe DMA start*/
+
+
+#define RTL8703B_TRANS_CARDEMU_TO_PDN												\
+	/* format */																\
+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
+	{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, BIT4}, /*0x23[4] = 1b'1 12H LDO enter sleep mode*/   \
+	{0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK | PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x20}, /*0x07[7:0] = 0x20 SOP option to disable BG/MB/ACK/SWR*/   \
+	{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0},/* 0x04[16] = 0*/\
+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, BIT7},/* 0x04[15] = 1*/
+
+#define RTL8703B_TRANS_PDN_TO_CARDEMU												\
+	/* format */																\
+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, 0},/* 0x04[15] = 0*/
+
+#define RTL8703B_TRANS_ACT_TO_LPS														\
+	/* format */																\
+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
+	{0x0301, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF},/*PCIe DMA stop*/	\
+	{0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF},/*Tx Pause*/	\
+	{0x05F8, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/	\
+	{0x05F9, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/	\
+	{0x05FA, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/	\
+	{0x05FB, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/	\
+	{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0},/*CCK and OFDM are disabled, and clock are gated*/	\
+	{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_US},/*Delay 1us*/	\
+	{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0},/*Whole BB is reset*/	\
+	{0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x03},/*Reset MAC TRX*/	\
+	{0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0},/*check if removed later*/	\
+	{0x0093, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x00},/*When driver enter Sus/ Disable, enable LOP for BT*/	\
+	{0x0553, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT5, BIT5},/*Respond TxOK to scheduler*/	\
+
+
+#define RTL8703B_TRANS_LPS_TO_ACT															\
+	/* format */																\
+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
+	{0x0080, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, 0xFF, 0x84}, /*SDIO RPWM*/\
+	{0xFE58, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x84}, /*USB RPWM*/\
+	{0x0361, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x84}, /*PCIe RPWM*/\
+	{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_MS}, /*Delay*/\
+	{0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0}, /*.	0x08[4] = 0		 switch TSF to 40M*/\
+	{0x0109, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT7, 0}, /*Polling 0x109[7]=0  TSF in 40M*/\
+	{0x0029, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT6 | BIT7, 0}, /*.	0x29[7:6] = 2b'00	 enable BB clock*/\
+	{0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1}, /*.	0x101[1] = 1*/\
+	{0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF}, /*.	0x100[7:0] = 0xFF	 enable WMAC TRX*/\
+	{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1 | BIT0, BIT1 | BIT0}, /*.	0x02[1:0] = 2b'11	 enable BB macro*/\
+	{0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0}, /*.	0x522 = 0*/
+
+#define RTL8703B_TRANS_END															\
+	/* format */																\
+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
+	{0xFFFF, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, 0, PWR_CMD_END, 0, 0},
+
+
+	extern WLAN_PWR_CFG rtl8703B_power_on_flow[RTL8703B_TRANS_CARDEMU_TO_ACT_STEPS + RTL8703B_TRANS_END_STEPS];
+	extern WLAN_PWR_CFG rtl8703B_radio_off_flow[RTL8703B_TRANS_ACT_TO_CARDEMU_STEPS + RTL8703B_TRANS_END_STEPS];
+	extern WLAN_PWR_CFG rtl8703B_card_disable_flow[RTL8703B_TRANS_ACT_TO_CARDEMU_STEPS + RTL8703B_TRANS_CARDEMU_TO_PDN_STEPS + RTL8703B_TRANS_END_STEPS];
+	extern WLAN_PWR_CFG rtl8703B_card_enable_flow[RTL8703B_TRANS_ACT_TO_CARDEMU_STEPS + RTL8703B_TRANS_CARDEMU_TO_PDN_STEPS + RTL8703B_TRANS_END_STEPS];
+	extern WLAN_PWR_CFG rtl8703B_suspend_flow[RTL8703B_TRANS_ACT_TO_CARDEMU_STEPS + RTL8703B_TRANS_CARDEMU_TO_SUS_STEPS + RTL8703B_TRANS_END_STEPS];
+	extern WLAN_PWR_CFG rtl8703B_resume_flow[RTL8703B_TRANS_ACT_TO_CARDEMU_STEPS + RTL8703B_TRANS_CARDEMU_TO_SUS_STEPS + RTL8703B_TRANS_END_STEPS];
+	extern WLAN_PWR_CFG rtl8703B_hwpdn_flow[RTL8703B_TRANS_ACT_TO_CARDEMU_STEPS + RTL8703B_TRANS_CARDEMU_TO_PDN_STEPS + RTL8703B_TRANS_END_STEPS];
+	extern WLAN_PWR_CFG rtl8703B_enter_lps_flow[RTL8703B_TRANS_ACT_TO_LPS_STEPS + RTL8703B_TRANS_END_STEPS];
+	extern WLAN_PWR_CFG rtl8703B_leave_lps_flow[RTL8703B_TRANS_LPS_TO_ACT_STEPS + RTL8703B_TRANS_END_STEPS];
+
+#endif
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/include/Hal8710BPhyCfg.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/Hal8710BPhyCfg.h
--- linux-5.6.3/3rdparty/rtl8821ce/include/Hal8710BPhyCfg.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/Hal8710BPhyCfg.h	2020-04-10 16:35:06.844661375 +0300
@@ -0,0 +1,127 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#ifndef __INC_HAL8710BPHYCFG_H__
+#define __INC_HAL8710BPHYCFG_H__
+
+/*--------------------------Define Parameters-------------------------------*/
+#define LOOP_LIMIT				5
+#define MAX_STALL_TIME			50		/* us */
+#define AntennaDiversityValue	0x80	/* (Adapter->bSoftwareAntennaDiversity ? 0x00 : 0x80) */
+#define MAX_TXPWR_IDX_NMODE_92S	63
+#define Reset_Cnt_Limit			3
+
+#ifdef CONFIG_PCI_HCI
+	#define MAX_AGGR_NUM	0x0B
+#else
+	#define MAX_AGGR_NUM	0x07
+#endif /* CONFIG_PCI_HCI */
+
+
+/*--------------------------Define Parameters End-------------------------------*/
+
+
+/*------------------------------Define structure----------------------------*/
+
+/*------------------------------Define structure End----------------------------*/
+
+/*--------------------------Exported Function prototype---------------------*/
+u32
+PHY_QueryBBReg_8710B(
+	IN	PADAPTER	Adapter,
+	IN	u32		RegAddr,
+	IN	u32		BitMask
+);
+
+VOID
+PHY_SetBBReg_8710B(
+	IN	PADAPTER	Adapter,
+	IN	u32		RegAddr,
+	IN	u32		BitMask,
+	IN	u32		Data
+);
+
+u32
+PHY_QueryRFReg_8710B(
+	IN	PADAPTER		Adapter,
+	IN	enum rf_path		eRFPath,
+	IN	u32				RegAddr,
+	IN	u32				BitMask
+);
+
+VOID
+PHY_SetRFReg_8710B(
+	IN	PADAPTER		Adapter,
+	IN	enum rf_path		eRFPath,
+	IN	u32				RegAddr,
+	IN	u32				BitMask,
+	IN	u32				Data
+);
+
+/* MAC/BB/RF HAL config */
+int PHY_BBConfig8710B(PADAPTER	Adapter);
+
+int PHY_RFConfig8710B(PADAPTER	Adapter);
+
+s32 PHY_MACConfig8710B(PADAPTER padapter);
+
+int
+PHY_ConfigRFWithParaFile_8710B(
+	IN	PADAPTER			Adapter,
+	IN	u8				*pFileName,
+	enum rf_path				eRFPath
+);
+
+VOID
+PHY_SetTxPowerIndex_8710B(
+	IN	PADAPTER			Adapter,
+	IN	u32					PowerIndex,
+	IN	enum rf_path			RFPath,
+	IN	u8					Rate
+);
+
+u8
+PHY_GetTxPowerIndex_8710B(
+	IN	PADAPTER			pAdapter,
+	IN	enum rf_path			RFPath,
+	IN	u8					Rate,
+	IN	u8					BandWidth,
+	IN	u8					Channel,
+	struct txpwr_idx_comp *tic
+);
+
+VOID
+PHY_GetTxPowerLevel8710B(
+	IN	PADAPTER		Adapter,
+	OUT s32				*powerlevel
+);
+
+VOID
+PHY_SetTxPowerLevel8710B(
+	IN	PADAPTER		Adapter,
+	IN	u8			channel
+);
+
+VOID
+PHY_SetSwChnlBWMode8710B(
+	IN	PADAPTER			Adapter,
+	IN	u8					channel,
+	IN	enum channel_width	Bandwidth,
+	IN	u8					Offset40,
+	IN	u8					Offset80
+);
+
+/*--------------------------Exported Function prototype End---------------------*/
+
+#endif
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/include/Hal8710BPhyReg.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/Hal8710BPhyReg.h
--- linux-5.6.3/3rdparty/rtl8821ce/include/Hal8710BPhyReg.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/Hal8710BPhyReg.h	2020-04-10 16:35:06.845661421 +0300
@@ -0,0 +1,1134 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#ifndef __INC_HAL8710BPHYREG_H__
+#define __INC_HAL8710BPHYREG_H__
+
+#define		rSYM_WLBT_PAPE_SEL		0x64
+/*
+ * BB-PHY register PMAC 0x100 PHY 0x800 - 0xEFF
+ * 1. PMAC duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF
+ * 2. 0x800/0x900/0xA00/0xC00/0xD00/0xE00
+ * 3. RF register 0x00-2E
+ * 4. Bit Mask for BB/RF register
+ * 5. Other definition for BB/RF R/W
+ *   */
+
+
+/*
+ * 1. PMAC duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF
+ * 1. Page1(0x100)
+ *   */
+#define		rPMAC_Reset					0x100
+#define		rPMAC_TxStart					0x104
+#define		rPMAC_TxLegacySIG				0x108
+#define		rPMAC_TxHTSIG1				0x10c
+#define		rPMAC_TxHTSIG2				0x110
+#define		rPMAC_PHYDebug				0x114
+#define		rPMAC_TxPacketNum				0x118
+#define		rPMAC_TxIdle					0x11c
+#define		rPMAC_TxMACHeader0			0x120
+#define		rPMAC_TxMACHeader1			0x124
+#define		rPMAC_TxMACHeader2			0x128
+#define		rPMAC_TxMACHeader3			0x12c
+#define		rPMAC_TxMACHeader4			0x130
+#define		rPMAC_TxMACHeader5			0x134
+#define		rPMAC_TxDataType				0x138
+#define		rPMAC_TxRandomSeed			0x13c
+#define		rPMAC_CCKPLCPPreamble			0x140
+#define		rPMAC_CCKPLCPHeader			0x144
+#define		rPMAC_CCKCRC16				0x148
+#define		rPMAC_OFDMRxCRC32OK			0x170
+#define		rPMAC_OFDMRxCRC32Er			0x174
+#define		rPMAC_OFDMRxParityEr			0x178
+#define		rPMAC_OFDMRxCRC8Er			0x17c
+#define		rPMAC_CCKCRxRC16Er			0x180
+#define		rPMAC_CCKCRxRC32Er			0x184
+#define		rPMAC_CCKCRxRC32OK			0x188
+#define		rPMAC_TxStatus					0x18c
+
+/*
+ * 2. Page2(0x200)
+ *
+ * The following two definition are only used for USB interface. */
+#define		RF_BB_CMD_ADDR				0x02c0	/* RF/BB read/write command address. */
+#define		RF_BB_CMD_DATA				0x02c4	/* RF/BB read/write command data. */
+
+/*
+ * 3. Page8(0x800)
+ *   */
+#define		rFPGA0_RFMOD				0x800	/* RF mode & CCK TxSC // RF BW Setting?? */
+
+#define		rFPGA0_TxInfo				0x804	/* Status report?? */
+#define		rFPGA0_PSDFunction			0x808
+
+#define		rFPGA0_TxGainStage			0x80c	/* Set TX PWR init gain? */
+
+#define		rFPGA0_RFTiming1			0x810	/* Useless now */
+#define		rFPGA0_RFTiming2			0x814
+
+#define		rFPGA0_XA_HSSIParameter1		0x820	/* RF 3 wire register */
+#define		rFPGA0_XA_HSSIParameter2		0x824
+#define		rFPGA0_XB_HSSIParameter1		0x828
+#define		rFPGA0_XB_HSSIParameter2		0x82c
+#define		rTxAGC_B_Rate18_06				0x830
+#define		rTxAGC_B_Rate54_24				0x834
+#define		rTxAGC_B_CCK1_55_Mcs32		0x838
+#define		rTxAGC_B_Mcs03_Mcs00			0x83c
+
+#define		rTxAGC_B_Mcs07_Mcs04			0x848
+#define		rTxAGC_B_Mcs11_Mcs08			0x84c
+
+#define		rFPGA0_XA_LSSIParameter		0x840
+#define		rFPGA0_XB_LSSIParameter		0x844
+
+#define		rFPGA0_RFWakeUpParameter		0x850	/* Useless now */
+#define		rFPGA0_RFSleepUpParameter		0x854
+
+#define		rFPGA0_XAB_SwitchControl		0x858	/* RF Channel switch */
+#define		rFPGA0_XCD_SwitchControl		0x85c
+
+#define		rFPGA0_XA_RFInterfaceOE		0x860	/* RF Channel switch */
+#define		rFPGA0_XB_RFInterfaceOE		0x864
+
+#define		rTxAGC_B_Mcs15_Mcs12			0x868
+#define		rTxAGC_B_CCK11_A_CCK2_11		0x86c
+
+#define		rFPGA0_XAB_RFInterfaceSW		0x870	/* RF Interface Software Control */
+#define		rFPGA0_XCD_RFInterfaceSW		0x874
+
+#define		rFPGA0_XAB_RFParameter		0x878	/* RF Parameter */
+#define		rFPGA0_XCD_RFParameter		0x87c
+
+#define		rFPGA0_AnalogParameter1		0x880	/* Crystal cap setting RF-R/W protection for parameter4?? */
+#define		rFPGA0_AnalogParameter2		0x884
+#define		rFPGA0_AnalogParameter3		0x888	/* Useless now */
+#define		rFPGA0_AnalogParameter4		0x88c
+
+#define		rFPGA0_XA_LSSIReadBack		0x8a0	/* Tranceiver LSSI Readback */
+#define		rFPGA0_XB_LSSIReadBack		0x8a4
+#define		rFPGA0_XC_LSSIReadBack		0x8a8
+#define		rFPGA0_XD_LSSIReadBack		0x8ac
+
+#define		rFPGA0_PSDReport				0x8b4	/* Useless now */
+#define		TransceiverA_HSPI_Readback	0x8b8	/* Transceiver A HSPI Readback */
+#define		TransceiverB_HSPI_Readback	0x8bc	/* Transceiver B HSPI Readback */
+#define		rFPGA0_XAB_RFInterfaceRB		0x8e0	/* Useless now // RF Interface Readback Value */
+#define		rFPGA0_XCD_RFInterfaceRB		0x8e4	/* Useless now */
+
+/*
+ * 4. Page9(0x900)
+ *   */
+#define	rFPGA1_RFMOD				0x900	/* RF mode & OFDM TxSC // RF BW Setting?? */
+#define	rFPGA1_TxBlock				0x904	/* Useless now */
+#define	rFPGA1_DebugSelect			0x908	/* Useless now */
+#define	rFPGA1_TxInfo				0x90c	/* Useless now // Status report?? */
+#define	rDPDT_control				0x92c
+#define	rfe_ctrl_anta_src				0x930
+#define	rS0S1_PathSwitch			0x948
+#define	rBBrx_DFIR					0x954
+
+/*
+ * 5. PageA(0xA00)
+ *
+ * Set Control channel to upper or lower. These settings are required only for 40MHz */
+#define		rCCK0_System				0xa00
+
+#define		rCCK0_AFESetting			0xa04	/* Disable init gain now // Select RX path by RSSI */
+#define		rCCK0_CCA					0xa08	/* Disable init gain now // Init gain */
+
+#define		rCCK0_RxAGC1				0xa0c	/* AGC default value, saturation level // Antenna Diversity, RX AGC, LNA Threshold, RX LNA Threshold useless now. Not the same as 90 series */
+#define		rCCK0_RxAGC2				0xa10	/* AGC & DAGC */
+
+#define		rCCK0_RxHP					0xa14
+
+#define		rCCK0_DSPParameter1		0xa18	/* Timing recovery & Channel estimation threshold */
+#define		rCCK0_DSPParameter2		0xa1c	/* SQ threshold */
+
+#define		rCCK0_TxFilter1				0xa20
+#define		rCCK0_TxFilter2				0xa24
+#define		rCCK0_DebugPort			0xa28	/* debug port and Tx filter3 */
+#define		rCCK0_FalseAlarmReport		0xa2c	/* 0xa2d	useless now 0xa30-a4f channel report */
+#define		rCCK0_TRSSIReport		0xa50
+#define		rCCK0_RxReport			0xa54  /* 0xa57 */
+#define		rCCK0_FACounterLower		0xa5c  /* 0xa5b */
+#define		rCCK0_FACounterUpper		0xa58  /* 0xa5c */
+
+/*
+ * PageB(0xB00)
+ *   */
+#define rPdp_AntA						0xb00
+#define rPdp_AntA_4						0xb04
+#define rPdp_AntA_8						0xb08
+#define rPdp_AntA_C						0xb0c
+#define rPdp_AntA_10					0xb10
+#define rPdp_AntA_14					0xb14
+#define rPdp_AntA_18					0xb18
+#define rPdp_AntA_1C					0xb1c
+#define rPdp_AntA_20					0xb20
+#define rPdp_AntA_24					0xb24
+
+#define rConfig_Pmpd_AntA				0xb28
+#define rConfig_ram64x16				0xb2c
+
+#define rBndA							0xb30
+#define rHssiPar						0xb34
+
+#define rConfig_AntA					0xb68
+#define rConfig_AntB					0xb6c
+
+#define rPdp_AntB						0xb70
+#define rPdp_AntB_4						0xb74
+#define rPdp_AntB_8						0xb78
+#define rPdp_AntB_C						0xb7c
+#define rPdp_AntB_10					0xb80
+#define rPdp_AntB_14					0xb84
+#define rPdp_AntB_18					0xb88
+#define rPdp_AntB_1C					0xb8c
+#define rPdp_AntB_20					0xb90
+#define rPdp_AntB_24					0xb94
+
+#define rConfig_Pmpd_AntB				0xb98
+
+#define rBndB							0xba0
+
+#define rAPK							0xbd8
+#define rPm_Rx0_AntA					0xbdc
+#define rPm_Rx1_AntA					0xbe0
+#define rPm_Rx2_AntA					0xbe4
+#define rPm_Rx3_AntA					0xbe8
+#define rPm_Rx0_AntB					0xbec
+#define rPm_Rx1_AntB					0xbf0
+#define rPm_Rx2_AntB					0xbf4
+#define rPm_Rx3_AntB					0xbf8
+/*
+ * 6. PageC(0xC00)
+ *   */
+#define		rOFDM0_LSTF				0xc00
+
+#define		rOFDM0_TRxPathEnable		0xc04
+#define		rOFDM0_TRMuxPar			0xc08
+#define		rOFDM0_TRSWIsolation		0xc0c
+
+#define		rOFDM0_XARxAFE			0xc10  /* RxIQ DC offset, Rx digital filter, DC notch filter */
+#define		rOFDM0_XARxIQImbalance		0xc14  /* RxIQ imbalance matrix */
+#define		rOFDM0_XBRxAFE		0xc18
+#define		rOFDM0_XBRxIQImbalance	0xc1c
+#define		rOFDM0_XCRxAFE		0xc20
+#define		rOFDM0_XCRxIQImbalance	0xc24
+#define		rOFDM0_XDRxAFE		0xc28
+#define		rOFDM0_XDRxIQImbalance	0xc2c
+
+#define		rOFDM0_RxDetector1			0xc30  /* PD, BW & SBD	// DM tune init gain */
+#define		rOFDM0_RxDetector2			0xc34  /* SBD & Fame Sync. */
+#define		rOFDM0_RxDetector3			0xc38  /* Frame Sync. */
+#define		rOFDM0_RxDetector4			0xc3c  /* PD, SBD, Frame Sync & Short-GI */
+
+#define		rOFDM0_RxDSP				0xc40  /* Rx Sync Path */
+#define		rOFDM0_CFOandDAGC		0xc44  /* CFO & DAGC */
+#define		rOFDM0_CCADropThreshold	0xc48 /* CCA Drop threshold */
+#define		rOFDM0_ECCAThreshold		0xc4c /* energy CCA */
+
+#define		rOFDM0_XAAGCCore1			0xc50	/* DIG */
+#define		rOFDM0_XAAGCCore2			0xc54
+#define		rOFDM0_XBAGCCore1			0xc58
+#define		rOFDM0_XBAGCCore2			0xc5c
+#define		rOFDM0_XCAGCCore1			0xc60
+#define		rOFDM0_XCAGCCore2			0xc64
+#define		rOFDM0_XDAGCCore1			0xc68
+#define		rOFDM0_XDAGCCore2			0xc6c
+
+#define		rOFDM0_AGCParameter1			0xc70
+#define		rOFDM0_AGCParameter2			0xc74
+#define		rOFDM0_AGCRSSITable			0xc78
+#define		rOFDM0_HTSTFAGC				0xc7c
+
+#define		rOFDM0_XATxIQImbalance		0xc80	/* TX PWR TRACK and DIG */
+#define		rOFDM0_XATxAFE				0xc84
+#define		rOFDM0_XBTxIQImbalance		0xc88
+#define		rOFDM0_XBTxAFE				0xc8c
+#define		rOFDM0_XCTxIQImbalance		0xc90
+#define		rOFDM0_XCTxAFE			0xc94
+#define		rOFDM0_XDTxIQImbalance		0xc98
+#define		rOFDM0_XDTxAFE				0xc9c
+
+#define		rOFDM0_RxIQExtAnta			0xca0
+#define		rOFDM0_TxCoeff1				0xca4
+#define		rOFDM0_TxCoeff2				0xca8
+#define		rOFDM0_TxCoeff3				0xcac
+#define		rOFDM0_TxCoeff4				0xcb0
+#define		rOFDM0_TxCoeff5				0xcb4
+#define		rOFDM0_TxCoeff6				0xcb8
+#define		rOFDM0_RxHPParameter			0xce0
+#define		rOFDM0_TxPseudoNoiseWgt		0xce4
+#define		rOFDM0_FrameSync				0xcf0
+#define		rOFDM0_DFSReport				0xcf4
+
+/*
+ * 7. PageD(0xD00)
+ *   */
+#define		rOFDM1_LSTF					0xd00
+#define		rOFDM1_TRxPathEnable			0xd04
+
+#define		rOFDM1_CFO						0xd08	/* No setting now */
+#define		rOFDM1_CSI1					0xd10
+#define		rOFDM1_SBD						0xd14
+#define		rOFDM1_CSI2					0xd18
+#define		rOFDM1_CFOTracking			0xd2c
+#define		rOFDM1_TRxMesaure1			0xd34
+#define		rOFDM1_IntfDet					0xd3c
+#define		rOFDM1_PseudoNoiseStateAB		0xd50
+#define		rOFDM1_PseudoNoiseStateCD		0xd54
+#define		rOFDM1_RxPseudoNoiseWgt		0xd58
+
+#define		rOFDM_PHYCounter1				0xda0  /* cca, parity fail */
+#define		rOFDM_PHYCounter2				0xda4  /* rate illegal, crc8 fail */
+#define		rOFDM_PHYCounter3				0xda8  /* MCS not support */
+
+#define		rOFDM_ShortCFOAB				0xdac	/* No setting now */
+#define		rOFDM_ShortCFOCD				0xdb0
+#define		rOFDM_LongCFOAB				0xdb4
+#define		rOFDM_LongCFOCD				0xdb8
+#define		rOFDM_TailCFOAB				0xdbc
+#define		rOFDM_TailCFOCD				0xdc0
+#define		rOFDM_PWMeasure1		0xdc4
+#define		rOFDM_PWMeasure2		0xdc8
+#define		rOFDM_BWReport				0xdcc
+#define		rOFDM_AGCReport				0xdd0
+#define		rOFDM_RxSNR					0xdd4
+#define		rOFDM_RxEVMCSI				0xdd8
+#define		rOFDM_SIGReport				0xddc
+
+
+/*
+ * 8. PageE(0xE00)
+ *   */
+#define		rTxAGC_A_Rate18_06			0xe00
+#define		rTxAGC_A_Rate54_24			0xe04
+#define		rTxAGC_A_CCK1_Mcs32			0xe08
+#define		rTxAGC_A_Mcs03_Mcs00			0xe10
+#define		rTxAGC_A_Mcs07_Mcs04			0xe14
+#define		rTxAGC_A_Mcs11_Mcs08			0xe18
+#define		rTxAGC_A_Mcs15_Mcs12			0xe1c
+
+#define		rFPGA0_IQK					0xe28
+#define		rTx_IQK_Tone_A				0xe30
+#define		rRx_IQK_Tone_A				0xe34
+#define		rTx_IQK_PI_A					0xe38
+#define		rRx_IQK_PI_A					0xe3c
+
+#define		rTx_IQK						0xe40
+#define		rRx_IQK						0xe44
+#define		rIQK_AGC_Pts					0xe48
+#define		rIQK_AGC_Rsp					0xe4c
+#define		rTx_IQK_Tone_B				0xe50
+#define		rRx_IQK_Tone_B				0xe54
+#define		rTx_IQK_PI_B					0xe58
+#define		rRx_IQK_PI_B					0xe5c
+#define		rIQK_AGC_Cont				0xe60
+
+#define		rBlue_Tooth					0xe6c
+#define		rRx_Wait_CCA					0xe70
+#define		rTx_CCK_RFON					0xe74
+#define		rTx_CCK_BBON				0xe78
+#define		rTx_OFDM_RFON				0xe7c
+#define		rTx_OFDM_BBON				0xe80
+#define		rTx_To_Rx					0xe84
+#define		rTx_To_Tx					0xe88
+#define		rRx_CCK						0xe8c
+
+#define		rTx_Power_Before_IQK_A		0xe94
+#define		rTx_Power_After_IQK_A			0xe9c
+
+#define		rRx_Power_Before_IQK_A		0xea0
+#define		rRx_Power_Before_IQK_A_2		0xea4
+#define		rRx_Power_After_IQK_A			0xea8
+#define		rRx_Power_After_IQK_A_2		0xeac
+
+#define		rTx_Power_Before_IQK_B		0xeb4
+#define		rTx_Power_After_IQK_B			0xebc
+
+#define		rRx_Power_Before_IQK_B		0xec0
+#define		rRx_Power_Before_IQK_B_2		0xec4
+#define		rRx_Power_After_IQK_B			0xec8
+#define		rRx_Power_After_IQK_B_2		0xecc
+
+#define		rRx_OFDM					0xed0
+#define		rRx_Wait_RIFS				0xed4
+#define		rRx_TO_Rx					0xed8
+#define		rStandby						0xedc
+#define		rSleep						0xee0
+#define		rPMPD_ANAEN				0xeec
+
+/*
+ * 7. RF Register 0x00-0x2E (RF 8256)
+ * RF-0222D 0x00-3F
+ *
+ * Zebra1 */
+#define		rZebra1_HSSIEnable				0x0	/* Useless now */
+#define		rZebra1_TRxEnable1				0x1
+#define		rZebra1_TRxEnable2				0x2
+#define		rZebra1_AGC					0x4
+#define		rZebra1_ChargePump			0x5
+#define		rZebra1_Channel				0x7	/* RF channel switch */
+
+/* #endif */
+#define		rZebra1_TxGain					0x8	/* Useless now */
+#define		rZebra1_TxLPF					0x9
+#define		rZebra1_RxLPF					0xb
+#define		rZebra1_RxHPFCorner			0xc
+
+/* Zebra4 */
+#define		rGlobalCtrl						0	/* Useless now */
+#define		rRTL8256_TxLPF					19
+#define		rRTL8256_RxLPF					11
+
+/* RTL8258 */
+#define		rRTL8258_TxLPF					0x11	/* Useless now */
+#define		rRTL8258_RxLPF					0x13
+#define		rRTL8258_RSSILPF				0xa
+
+/*
+ * RL6052 Register definition
+ *   */
+#define		RF_AC						0x00	/* */
+
+#define		RF_IQADJ_G1				0x01	/* */
+#define		RF_IQADJ_G2				0x02	/* */
+#define		RF_BS_PA_APSET_G1_G4		0x03
+#define		RF_BS_PA_APSET_G5_G8		0x04
+#define		RF_POW_TRSW				0x05	/* */
+
+#define		RF_GAIN_RX					0x06	/* */
+#define		RF_GAIN_TX					0x07	/* */
+
+#define		RF_TXM_IDAC				0x08	/* */
+#define		RF_IPA_G					0x09	/* */
+#define		RF_TXBIAS_G				0x0A
+#define		RF_TXPA_AG					0x0B
+#define		RF_IPA_A					0x0C	/* */
+#define		RF_TXBIAS_A				0x0D
+#define		RF_BS_PA_APSET_G9_G11	0x0E
+#define		RF_BS_IQGEN				0x0F	/* */
+
+#define		RF_MODE1					0x10	/* */
+#define		RF_MODE2					0x11	/* */
+
+#define		RF_RX_AGC_HP				0x12	/* */
+#define		RF_TX_AGC					0x13	/* */
+#define		RF_BIAS						0x14	/* */
+#define		RF_IPA						0x15	/* */
+#define		RF_TXBIAS					0x16
+#define		RF_POW_ABILITY			0x17	/* */
+#define		RF_MODE_AG				0x18	/* */
+#define		rRfChannel					0x18	/* RF channel and BW switch */
+#define		RF_CHNLBW					0x18	/* RF channel and BW switch */
+#define		RF_TOP						0x19	/* */
+
+#define		RF_RX_G1					0x1A	/* */
+#define		RF_RX_G2					0x1B	/* */
+
+#define		RF_RX_BB2					0x1C	/* */
+#define		RF_RX_BB1					0x1D	/* */
+
+#define		RF_RCK1					0x1E	/* */
+#define		RF_RCK2					0x1F	/* */
+
+#define		RF_TX_G1					0x20	/* */
+#define		RF_TX_G2					0x21	/* */
+#define		RF_TX_G3					0x22	/* */
+
+#define		RF_TX_BB1					0x23	/* */
+
+#define		RF_T_METER					0x24	/* */
+
+#define		RF_SYN_G1					0x25	/* RF TX Power control */
+#define		RF_SYN_G2					0x26	/* RF TX Power control */
+#define		RF_SYN_G3					0x27	/* RF TX Power control */
+#define		RF_SYN_G4					0x28	/* RF TX Power control */
+#define		RF_SYN_G5					0x29	/* RF TX Power control */
+#define		RF_SYN_G6					0x2A	/* RF TX Power control */
+#define		RF_SYN_G7					0x2B	/* RF TX Power control */
+#define		RF_SYN_G8					0x2C	/* RF TX Power control */
+
+#define		RF_RCK_OS					0x30	/* RF TX PA control */
+
+#define		RF_TXPA_G1					0x31	/* RF TX PA control */
+#define		RF_TXPA_G2					0x32	/* RF TX PA control */
+#define		RF_TXPA_G3					0x33	/* RF TX PA control */
+#define	RF_TX_BIAS_A				0x35
+#define	RF_TX_BIAS_D				0x36
+#define	RF_LOBF_9					0x38
+#define	RF_RXRF_A3					0x3C	/*	 */
+#define	RF_TRSW					0x3F
+
+#define	RF_TXRF_A2					0x41
+#define	RF_T_METER_88E				0x42
+#define	RF_TXPA_G4					0x46
+#define	RF_TXPA_A4					0x4B
+#define	RF_0x52					0x52
+#define	RF_WE_LUT					0xEF
+#define	RF_S0S1					0xB0
+
+/*
+ * Bit Mask
+ *
+ * 1. Page1(0x100) */
+#define		bBBResetB						0x100	/* Useless now? */
+#define		bGlobalResetB					0x200
+#define		bOFDMTxStart					0x4
+#define		bCCKTxStart						0x8
+#define		bCRC32Debug					0x100
+#define		bPMACLoopback					0x10
+#define		bTxLSIG							0xffffff
+#define		bOFDMTxRate					0xf
+#define		bOFDMTxReserved				0x10
+#define		bOFDMTxLength					0x1ffe0
+#define		bOFDMTxParity					0x20000
+#define		bTxHTSIG1						0xffffff
+#define		bTxHTMCSRate					0x7f
+#define		bTxHTBW						0x80
+#define		bTxHTLength					0xffff00
+#define		bTxHTSIG2						0xffffff
+#define		bTxHTSmoothing					0x1
+#define		bTxHTSounding					0x2
+#define		bTxHTReserved					0x4
+#define		bTxHTAggreation				0x8
+#define		bTxHTSTBC						0x30
+#define		bTxHTAdvanceCoding			0x40
+#define		bTxHTShortGI					0x80
+#define		bTxHTNumberHT_LTF			0x300
+#define		bTxHTCRC8						0x3fc00
+#define		bCounterReset					0x10000
+#define		bNumOfOFDMTx					0xffff
+#define		bNumOfCCKTx					0xffff0000
+#define		bTxIdleInterval					0xffff
+#define		bOFDMService					0xffff0000
+#define		bTxMACHeader					0xffffffff
+#define		bTxDataInit						0xff
+#define		bTxHTMode						0x100
+#define		bTxDataType					0x30000
+#define		bTxRandomSeed					0xffffffff
+#define		bCCKTxPreamble					0x1
+#define		bCCKTxSFD						0xffff0000
+#define		bCCKTxSIG						0xff
+#define		bCCKTxService					0xff00
+#define		bCCKLengthExt					0x8000
+#define		bCCKTxLength					0xffff0000
+#define		bCCKTxCRC16					0xffff
+#define		bCCKTxStatus					0x1
+#define		bOFDMTxStatus					0x2
+
+#define		IS_BB_REG_OFFSET_92S(_Offset)		((_Offset >= 0x800) && (_Offset <= 0xfff))
+#define		RF_TX_GAIN_OFFSET_8710B(_val) (abs((_val)) | (((_val) > 0) ? BIT(4) : 0))
+
+/* 2. Page8(0x800) */
+#define		bRFMOD							0x1	/* Reg 0x800 rFPGA0_RFMOD */
+#define		bJapanMode						0x2
+#define		bCCKTxSC						0x30
+#define		bCCKEn							0x1000000
+#define		bOFDMEn						0x2000000
+
+#define		bOFDMRxADCPhase           0x10000	/* Useless now */
+#define		bOFDMTxDACPhase		0x40000
+#define		bXATxAGC			0x3f
+
+#define		bAntennaSelect		0x0300
+
+#define		bXBTxAGC                 0xf00	/* Reg 80c rFPGA0_TxGainStage */
+#define		bXCTxAGC			0xf000
+#define		bXDTxAGC			0xf0000
+
+#define		bPAStart                 0xf0000000	/* Useless now */
+#define		bTRStart			0x00f00000
+#define		bRFStart			0x0000f000
+#define		bBBStart			0x000000f0
+#define		bBBCCKStart		0x0000000f
+#define		bPAEnd                    0xf          /* Reg0x814 */
+#define		bTREnd			0x0f000000
+#define		bRFEnd			0x000f0000
+#define		bCCAMask                  0x000000f0   /* T2R */
+#define		bR2RCCAMask		0x00000f00
+#define		bHSSI_R2TDelay		0xf8000000
+#define		bHSSI_T2RDelay		0xf80000
+#define		bContTxHSSI              0x400     /* chane gain at continue Tx */
+#define		bIGFromCCK		0x200
+#define		bAGCAddress		0x3f
+#define		bRxHPTx			0x7000
+#define		bRxHPT2R			0x38000
+#define		bRxHPCCKIni		0xc0000
+#define		bAGCTxCode		0xc00000
+#define		bAGCRxCode		0x300000
+
+#define		b3WireDataLength         0x800	/* Reg 0x820~84f rFPGA0_XA_HSSIParameter1 */
+#define		b3WireAddressLength		0x400
+
+#define		b3WireRFPowerDown         0x1	/* Useless now
+ * #define bHWSISelect		0x8 */
+#define		b5GPAPEPolarity		0x40000000
+#define		b2GPAPEPolarity		0x80000000
+#define		bRFSW_TxDefaultAnt		0x3
+#define		bRFSW_TxOptionAnt		0x30
+#define		bRFSW_RxDefaultAnt		0x300
+#define		bRFSW_RxOptionAnt		0x3000
+#define		bRFSI_3WireData		0x1
+#define		bRFSI_3WireClock		0x2
+#define		bRFSI_3WireLoad		0x4
+#define		bRFSI_3WireRW		0x8
+#define		bRFSI_3Wire			0xf
+
+#define		bRFSI_RFENV              0x10	/* Reg 0x870 rFPGA0_XAB_RFInterfaceSW */
+
+#define		bRFSI_TRSW               0x20	/* Useless now */
+#define		bRFSI_TRSWB		0x40
+#define		bRFSI_ANTSW		0x100
+#define		bRFSI_ANTSWB		0x200
+#define		bRFSI_PAPE			0x400
+#define		bRFSI_PAPE5G		0x800
+#define		bBandSelect			0x1
+#define		bHTSIG2_GI			0x80
+#define		bHTSIG2_Smoothing		0x01
+#define		bHTSIG2_Sounding		0x02
+#define		bHTSIG2_Aggreaton		0x08
+#define		bHTSIG2_STBC		0x30
+#define		bHTSIG2_AdvCoding		0x40
+#define		bHTSIG2_NumOfHTLTF	0x300
+#define		bHTSIG2_CRC8		0x3fc
+#define		bHTSIG1_MCS		0x7f
+#define		bHTSIG1_BandWidth		0x80
+#define		bHTSIG1_HTLength		0xffff
+#define		bLSIG_Rate			0xf
+#define		bLSIG_Reserved		0x10
+#define		bLSIG_Length		0x1fffe
+#define		bLSIG_Parity			0x20
+#define		bCCKRxPhase		0x4
+
+#define		bLSSIReadAddress          0x7f800000   /* T65 RF */
+
+#define		bLSSIReadEdge             0x80000000   /* LSSI "Read" edge signal */
+
+#define		bLSSIReadBackData         0xfffff		/* T65 RF */
+
+#define		bLSSIReadOKFlag           0x1000	/* Useless now */
+#define		bCCKSampleRate            0x8       /* 0: 44MHz, 1:88MHz     */
+#define		bRegulator0Standby		0x1
+#define		bRegulatorPLLStandby		0x2
+#define		bRegulator1Standby		0x4
+#define		bPLLPowerUp		0x8
+#define		bDPLLPowerUp		0x10
+#define		bDA10PowerUp		0x20
+#define		bAD7PowerUp		0x200
+#define		bDA6PowerUp		0x2000
+#define		bXtalPowerUp		0x4000
+#define		b40MDClkPowerUP		0x8000
+#define		bDA6DebugMode		0x20000
+#define		bDA6Swing			0x380000
+
+#define		bADClkPhase               0x4000000	/* Reg 0x880 rFPGA0_AnalogParameter1 20/40 CCK support switch 40/80 BB MHZ */
+
+#define		b80MClkDelay              0x18000000	/* Useless */
+#define		bAFEWatchDogEnable		0x20000000
+
+#define		bXtalCap01                0xc0000000	/* Reg 0x884 rFPGA0_AnalogParameter2 Crystal cap */
+#define		bXtalCap23			0x3
+#define		bXtalCap92x					0x0f000000
+#define		bXtalCap			0x0f000000
+
+#define		bIntDifClkEnable          0x400	/* Useless */
+#define		bExtSigClkEnable		0x800
+#define		bBandgapMbiasPowerUp	0x10000
+#define		bAD11SHGain		0xc0000
+#define		bAD11InputRange		0x700000
+#define		bAD11OPCurrent		0x3800000
+#define		bIPathLoopback		0x4000000
+#define		bQPathLoopback		0x8000000
+#define		bAFELoopback		0x10000000
+#define		bDA10Swing		0x7e0
+#define		bDA10Reverse		0x800
+#define		bDAClkSource		0x1000
+#define		bAD7InputRange		0x6000
+#define		bAD7Gain			0x38000
+#define		bAD7OutputCMMode		0x40000
+#define		bAD7InputCMMode		0x380000
+#define		bAD7Current			0xc00000
+#define		bRegulatorAdjust		0x7000000
+#define		bAD11PowerUpAtTx		0x1
+#define		bDA10PSAtTx		0x10
+#define		bAD11PowerUpAtRx		0x100
+#define		bDA10PSAtRx		0x1000
+#define		bCCKRxAGCFormat		0x200
+#define		bPSDFFTSamplepPoint		0xc000
+#define		bPSDAverageNum		0x3000
+#define		bIQPathControl		0xc00
+#define		bPSDFreq			0x3ff
+#define		bPSDAntennaPath		0x30
+#define		bPSDIQSwitch		0x40
+#define		bPSDRxTrigger		0x400000
+#define		bPSDTxTrigger		0x80000000
+#define		bPSDSineToneScale		0x7f000000
+#define		bPSDReport			0xffff
+
+/* 3. Page9(0x900) */
+#define		bOFDMTxSC                 0x30000000	/* Useless */
+#define		bCCKTxOn			0x1
+#define		bOFDMTxOn		0x2
+#define		bDebugPage                0xfff  /* reset debug page and also HWord, LWord */
+#define		bDebugItem                0xff   /* reset debug page and LWord */
+#define		bAntL			0x10
+#define		bAntNonHT				0x100
+#define		bAntHT1			0x1000
+#define		bAntHT2			0x10000
+#define		bAntHT1S1			0x100000
+#define		bAntNonHTS1		0x1000000
+
+/* 4. PageA(0xA00) */
+#define		bCCKBBMode				0x3	/* Useless */
+#define		bCCKTxPowerSaving		0x80
+#define		bCCKRxPowerSaving		0x40
+
+#define		bCCKSideBand			0x10	/* Reg 0xa00 rCCK0_System 20/40 switch */
+
+#define		bCCKScramble			0x8	/* Useless */
+#define		bCCKAntDiversity		0x8000
+#define		bCCKCarrierRecovery		0x4000
+#define		bCCKTxRate				0x3000
+#define		bCCKDCCancel			0x0800
+#define		bCCKISICancel			0x0400
+#define		bCCKMatchFilter			0x0200
+#define		bCCKEqualizer			0x0100
+#define		bCCKPreambleDetect		0x800000
+#define		bCCKFastFalseCCA		0x400000
+#define		bCCKChEstStart			0x300000
+#define		bCCKCCACount			0x080000
+#define		bCCKcs_lim				0x070000
+#define		bCCKBistMode			0x80000000
+#define		bCCKCCAMask			0x40000000
+#define		bCCKTxDACPhase		0x4
+#define		bCCKRxADCPhase		0x20000000   /* r_rx_clk */
+#define		bCCKr_cp_mode0		0x0100
+#define		bCCKTxDCOffset			0xf0
+#define		bCCKRxDCOffset			0xf
+#define		bCCKCCAMode			0xc000
+#define		bCCKFalseCS_lim			0x3f00
+#define		bCCKCS_ratio			0xc00000
+#define		bCCKCorgBit_sel			0x300000
+#define		bCCKPD_lim				0x0f0000
+#define		bCCKNewCCA			0x80000000
+#define		bCCKRxHPofIG			0x8000
+#define		bCCKRxIG				0x7f00
+#define		bCCKLNAPolarity			0x800000
+#define		bCCKRx1stGain			0x7f0000
+#define		bCCKRFExtend			0x20000000 /* CCK Rx Iinital gain polarity */
+#define		bCCKRxAGCSatLevel		0x1f000000
+#define		bCCKRxAGCSatCount		0xe0
+#define		bCCKRxRFSettle			0x1f       /* AGCsamp_dly */
+#define		bCCKFixedRxAGC			0x8000
+/* #define bCCKRxAGCFormat		0x4000 */   /* remove to HSSI register 0x824 */
+#define		bCCKAntennaPolarity		0x2000
+#define		bCCKTxFilterType		0x0c00
+#define		bCCKRxAGCReportType	0x0300
+#define		bCCKRxDAGCEn			0x80000000
+#define		bCCKRxDAGCPeriod		0x20000000
+#define		bCCKRxDAGCSatLevel		0x1f000000
+#define		bCCKTimingRecovery		0x800000
+#define		bCCKTxC0				0x3f0000
+#define		bCCKTxC1				0x3f000000
+#define		bCCKTxC2				0x3f
+#define		bCCKTxC3				0x3f00
+#define		bCCKTxC4				0x3f0000
+#define		bCCKTxC5				0x3f000000
+#define		bCCKTxC6				0x3f
+#define		bCCKTxC7				0x3f00
+#define		bCCKDebugPort			0xff0000
+#define		bCCKDACDebug			0x0f000000
+#define		bCCKFalseAlarmEnable	0x8000
+#define		bCCKFalseAlarmRead		0x4000
+#define		bCCKTRSSI				0x7f
+#define		bCCKRxAGCReport		0xfe
+#define		bCCKRxReport_AntSel	0x80000000
+#define		bCCKRxReport_MFOff		0x40000000
+#define		bCCKRxRxReport_SQLoss	0x20000000
+#define		bCCKRxReport_Pktloss	0x10000000
+#define		bCCKRxReport_Lockedbit	0x08000000
+#define		bCCKRxReport_RateError	0x04000000
+#define		bCCKRxReport_RxRate	0x03000000
+#define		bCCKRxFACounterLower	0xff
+#define		bCCKRxFACounterUpper	0xff000000
+#define		bCCKRxHPAGCStart		0xe000
+#define		bCCKRxHPAGCFinal		0x1c00
+#define		bCCKRxFalseAlarmEnable	0x8000
+#define		bCCKFACounterFreeze	0x4000
+#define		bCCKTxPathSel			0x10000000
+#define		bCCKDefaultRxPath		0xc000000
+#define		bCCKOptionRxPath		0x3000000
+
+/* 5. PageC(0xC00) */
+#define		bNumOfSTF				0x3	/* Useless */
+#define		bShift_L					0xc0
+#define		bGI_TH					0xc
+#define		bRxPathA				0x1
+#define		bRxPathB				0x2
+#define		bRxPathC				0x4
+#define		bRxPathD				0x8
+#define		bTxPathA				0x1
+#define		bTxPathB				0x2
+#define		bTxPathC				0x4
+#define		bTxPathD				0x8
+#define		bTRSSIFreq				0x200
+#define		bADCBackoff				0x3000
+#define		bDFIRBackoff			0xc000
+#define		bTRSSILatchPhase		0x10000
+#define		bRxIDCOffset			0xff
+#define		bRxQDCOffset			0xff00
+#define		bRxDFIRMode			0x1800000
+#define		bRxDCNFType			0xe000000
+#define		bRXIQImb_A				0x3ff
+#define		bRXIQImb_B				0xfc00
+#define		bRXIQImb_C				0x3f0000
+#define		bRXIQImb_D				0xffc00000
+#define		bDC_dc_Notch			0x60000
+#define		bRxNBINotch			0x1f000000
+#define		bPD_TH					0xf
+#define		bPD_TH_Opt2			0xc000
+#define		bPWED_TH				0x700
+#define		bIfMF_Win_L			0x800
+#define		bPD_Option				0x1000
+#define		bMF_Win_L				0xe000
+#define		bBW_Search_L			0x30000
+#define		bwin_enh_L				0xc0000
+#define		bBW_TH					0x700000
+#define		bED_TH2				0x3800000
+#define		bBW_option				0x4000000
+#define		bRatio_TH				0x18000000
+#define		bWindow_L				0xe0000000
+#define		bSBD_Option				0x1
+#define		bFrame_TH				0x1c
+#define		bFS_Option				0x60
+#define		bDC_Slope_check		0x80
+#define		bFGuard_Counter_DC_L	0xe00
+#define		bFrame_Weight_Short	0x7000
+#define		bSub_Tune				0xe00000
+#define		bFrame_DC_Length		0xe000000
+#define		bSBD_start_offset		0x30000000
+#define		bFrame_TH_2			0x7
+#define		bFrame_GI2_TH			0x38
+#define		bGI2_Sync_en			0x40
+#define		bSarch_Short_Early		0x300
+#define		bSarch_Short_Late		0xc00
+#define		bSarch_GI2_Late		0x70000
+#define		bCFOAntSum				0x1
+#define		bCFOAcc				0x2
+#define		bCFOStartOffset			0xc
+#define		bCFOLookBack			0x70
+#define		bCFOSumWeight			0x80
+#define		bDAGCEnable			0x10000
+#define		bTXIQImb_A				0x3ff
+#define		bTXIQImb_B				0xfc00
+#define		bTXIQImb_C				0x3f0000
+#define		bTXIQImb_D				0xffc00000
+#define		bTxIDCOffset			0xff
+#define		bTxQDCOffset			0xff00
+#define		bTxDFIRMode			0x10000
+#define		bTxPesudoNoiseOn		0x4000000
+#define		bTxPesudoNoise_A		0xff
+#define		bTxPesudoNoise_B		0xff00
+#define		bTxPesudoNoise_C		0xff0000
+#define		bTxPesudoNoise_D		0xff000000
+#define		bCCADropOption			0x20000
+#define		bCCADropThres			0xfff00000
+#define		bEDCCA_H				0xf
+#define		bEDCCA_L				0xf0
+#define		bLambda_ED			0x300
+#define		bRxInitialGain			0x7f
+#define		bRxAntDivEn				0x80
+#define		bRxAGCAddressForLNA	0x7f00
+#define		bRxHighPowerFlow		0x8000
+#define		bRxAGCFreezeThres		0xc0000
+#define		bRxFreezeStep_AGC1	0x300000
+#define		bRxFreezeStep_AGC2	0xc00000
+#define		bRxFreezeStep_AGC3	0x3000000
+#define		bRxFreezeStep_AGC0	0xc000000
+#define		bRxRssi_Cmp_En			0x10000000
+#define		bRxQuickAGCEn			0x20000000
+#define		bRxAGCFreezeThresMode	0x40000000
+#define		bRxOverFlowCheckType	0x80000000
+#define		bRxAGCShift				0x7f
+#define		bTRSW_Tri_Only			0x80
+#define		bPowerThres			0x300
+#define		bRxAGCEn				0x1
+#define		bRxAGCTogetherEn		0x2
+#define		bRxAGCMin				0x4
+#define		bRxHP_Ini				0x7
+#define		bRxHP_TRLNA			0x70
+#define		bRxHP_RSSI				0x700
+#define		bRxHP_BBP1				0x7000
+#define		bRxHP_BBP2				0x70000
+#define		bRxHP_BBP3				0x700000
+#define		bRSSI_H					0x7f0000     /* the threshold for high power */
+#define		bRSSI_Gen				0x7f000000   /* the threshold for ant diversity */
+#define		bRxSettle_TRSW			0x7
+#define		bRxSettle_LNA			0x38
+#define		bRxSettle_RSSI			0x1c0
+#define		bRxSettle_BBP			0xe00
+#define		bRxSettle_RxHP			0x7000
+#define		bRxSettle_AntSW_RSSI	0x38000
+#define		bRxSettle_AntSW		0xc0000
+#define		bRxProcessTime_DAGC	0x300000
+#define		bRxSettle_HSSI			0x400000
+#define		bRxProcessTime_BBPPW	0x800000
+#define		bRxAntennaPowerShift	0x3000000
+#define		bRSSITableSelect		0xc000000
+#define		bRxHP_Final				0x7000000
+#define		bRxHTSettle_BBP			0x7
+#define		bRxHTSettle_HSSI		0x8
+#define		bRxHTSettle_RxHP		0x70
+#define		bRxHTSettle_BBPPW		0x80
+#define		bRxHTSettle_Idle		0x300
+#define		bRxHTSettle_Reserved	0x1c00
+#define		bRxHTRxHPEn			0x8000
+#define		bRxHTAGCFreezeThres	0x30000
+#define		bRxHTAGCTogetherEn	0x40000
+#define		bRxHTAGCMin			0x80000
+#define		bRxHTAGCEn				0x100000
+#define		bRxHTDAGCEn			0x200000
+#define		bRxHTRxHP_BBP			0x1c00000
+#define		bRxHTRxHP_Final		0xe0000000
+#define		bRxPWRatioTH			0x3
+#define		bRxPWRatioEn			0x4
+#define		bRxMFHold				0x3800
+#define		bRxPD_Delay_TH1		0x38
+#define		bRxPD_Delay_TH2		0x1c0
+#define		bRxPD_DC_COUNT_MAX	0x600
+/* #define bRxMF_Hold               0x3800 */
+#define		bRxPD_Delay_TH			0x8000
+#define		bRxProcess_Delay		0xf0000
+#define		bRxSearchrange_GI2_Early	0x700000
+#define		bRxFrame_Guard_Counter_L	0x3800000
+#define		bRxSGI_Guard_L			0xc000000
+#define		bRxSGI_Search_L		0x30000000
+#define		bRxSGI_TH				0xc0000000
+#define		bDFSCnt0				0xff
+#define		bDFSCnt1				0xff00
+#define		bDFSFlag				0xf0000
+#define		bMFWeightSum			0x300000
+#define		bMinIdxTH				0x7f000000
+#define		bDAFormat				0x40000
+#define		bTxChEmuEnable		0x01000000
+#define		bTRSWIsolation_A		0x7f
+#define		bTRSWIsolation_B		0x7f00
+#define		bTRSWIsolation_C		0x7f0000
+#define		bTRSWIsolation_D		0x7f000000
+#define		bExtLNAGain				0x7c00
+
+/* 6. PageE(0xE00) */
+#define		bSTBCEn				0x4	/* Useless */
+#define		bAntennaMapping		0x10
+#define		bNss					0x20
+#define		bCFOAntSumD			0x200
+#define		bPHYCounterReset		0x8000000
+#define		bCFOReportGet			0x4000000
+#define		bOFDMContinueTx		0x10000000
+#define		bOFDMSingleCarrier		0x20000000
+#define		bOFDMSingleTone		0x40000000
+/* #define bRxPath1                 0x01 */
+/* #define bRxPath2                 0x02 */
+/* #define bRxPath3                 0x04 */
+/* #define bRxPath4                 0x08 */
+/* #define bTxPath1                 0x10 */
+/* #define bTxPath2                 0x20 */
+#define		bHTDetect			0x100
+#define		bCFOEn				0x10000
+#define		bCFOValue			0xfff00000
+#define		bSigTone_Re		0x3f
+#define		bSigTone_Im		0x7f00
+#define		bCounter_CCA		0xffff
+#define		bCounter_ParityFail	0xffff0000
+#define		bCounter_RateIllegal		0xffff
+#define		bCounter_CRC8Fail	0xffff0000
+#define		bCounter_MCSNoSupport	0xffff
+#define		bCounter_FastSync	0xffff
+#define		bShortCFO			0xfff
+#define		bShortCFOTLength	12   /* total */
+#define		bShortCFOFLength	11   /* fraction */
+#define		bLongCFO			0x7ff
+#define		bLongCFOTLength	11
+#define		bLongCFOFLength	11
+#define		bTailCFO			0x1fff
+#define		bTailCFOTLength		13
+#define		bTailCFOFLength		12
+#define		bmax_en_pwdB		0xffff
+#define		bCC_power_dB		0xffff0000
+#define		bnoise_pwdB		0xffff
+#define		bPowerMeasTLength	10
+#define		bPowerMeasFLength	3
+#define		bRx_HT_BW			0x1
+#define		bRxSC				0x6
+#define		bRx_HT				0x8
+#define		bNB_intf_det_on		0x1
+#define		bIntf_win_len_cfg	0x30
+#define		bNB_Intf_TH_cfg		0x1c0
+#define		bRFGain				0x3f
+#define		bTableSel			0x40
+#define		bTRSW				0x80
+#define		bRxSNR_A			0xff
+#define		bRxSNR_B			0xff00
+#define		bRxSNR_C			0xff0000
+#define		bRxSNR_D			0xff000000
+#define		bSNREVMTLength		8
+#define		bSNREVMFLength		1
+#define		bCSI1st				0xff
+#define		bCSI2nd				0xff00
+#define		bRxEVM1st			0xff0000
+#define		bRxEVM2nd			0xff000000
+#define		bSIGEVM			0xff
+#define		bPWDB				0xff00
+#define		bSGIEN				0x10000
+
+#define		bSFactorQAM1		0xf	/* Useless */
+#define		bSFactorQAM2		0xf0
+#define		bSFactorQAM3		0xf00
+#define		bSFactorQAM4		0xf000
+#define		bSFactorQAM5		0xf0000
+#define		bSFactorQAM6		0xf0000
+#define		bSFactorQAM7		0xf00000
+#define		bSFactorQAM8		0xf000000
+#define		bSFactorQAM9		0xf0000000
+#define		bCSIScheme			0x100000
+
+#define		bNoiseLvlTopSet		0x3	/* Useless */
+#define		bChSmooth			0x4
+#define		bChSmoothCfg1		0x38
+#define		bChSmoothCfg2		0x1c0
+#define		bChSmoothCfg3		0xe00
+#define		bChSmoothCfg4		0x7000
+#define		bMRCMode			0x800000
+#define		bTHEVMCfg			0x7000000
+
+#define		bLoopFitType		0x1	/* Useless */
+#define		bUpdCFO			0x40
+#define		bUpdCFOOffData		0x80
+#define		bAdvUpdCFO			0x100
+#define		bAdvTimeCtrl		0x800
+#define		bUpdClko			0x1000
+#define		bFC					0x6000
+#define		bTrackingMode		0x8000
+#define		bPhCmpEnable		0x10000
+#define		bUpdClkoLTF		0x20000
+#define		bComChCFO			0x40000
+#define		bCSIEstiMode		0x80000
+#define		bAdvUpdEqz			0x100000
+#define		bUChCfg				0x7000000
+#define		bUpdEqz			0x8000000
+
+/* Rx Pseduo noise */
+#define		bRxPesudoNoiseOn		0x20000000	/* Useless */
+#define		bRxPesudoNoise_A		0xff
+#define		bRxPesudoNoise_B		0xff00
+#define		bRxPesudoNoise_C		0xff0000
+#define		bRxPesudoNoise_D		0xff000000
+#define		bPesudoNoiseState_A	0xffff
+#define		bPesudoNoiseState_B	0xffff0000
+#define		bPesudoNoiseState_C	0xffff
+#define		bPesudoNoiseState_D	0xffff0000
+
+/* 7. RF Register
+ * Zebra1 */
+#define		bZebra1_HSSIEnable		0x8		/* Useless */
+#define		bZebra1_TRxControl		0xc00
+#define		bZebra1_TRxGainSetting	0x07f
+#define		bZebra1_RxCorner		0xc00
+#define		bZebra1_TxChargePump	0x38
+#define		bZebra1_RxChargePump	0x7
+#define		bZebra1_ChannelNum	0xf80
+#define		bZebra1_TxLPFBW		0x400
+#define		bZebra1_RxLPFBW		0x600
+
+/* Zebra4 */
+#define		bRTL8256RegModeCtrl1	0x100	/* Useless */
+#define		bRTL8256RegModeCtrl0	0x40
+#define		bRTL8256_TxLPFBW		0x18
+#define		bRTL8256_RxLPFBW		0x600
+
+/* RTL8258 */
+#define		bRTL8258_TxLPFBW		0xc	/* Useless */
+#define		bRTL8258_RxLPFBW		0xc00
+#define		bRTL8258_RSSILPFBW	0xc0
+
+
+/*
+ * Other Definition
+ *   */
+
+/* byte endable for sb_write */
+#define		bByte0				0x1	/* Useless */
+#define		bByte1				0x2
+#define		bByte2				0x4
+#define		bByte3				0x8
+#define		bWord0				0x3
+#define		bWord1				0xc
+#define		bDWord				0xf
+
+/* for PutRegsetting & GetRegSetting BitMask */
+#define		bMaskByte0			0xff	/* Reg 0xc50 rOFDM0_XAAGCCore~0xC6f */
+#define		bMaskByte1			0xff00
+#define		bMaskByte2			0xff0000
+#define		bMaskByte3			0xff000000
+#define		bMaskHWord		0xffff0000
+#define		bMaskLWord			0x0000ffff
+#define		bMaskDWord		0xffffffff
+#define		bMaskH3Bytes		0xffffff00
+#define		bMask12Bits			0xfff
+#define		bMaskH4Bits			0xf0000000
+#define		bMaskOFDM_D		0xffc00000
+#define		bMaskCCK			0x3f3f3f3f
+
+
+#define		bEnable			0x1	/* Useless */
+#define		bDisable		0x0
+
+#define		LeftAntenna		0x0	/* Useless */
+#define		RightAntenna	0x1
+
+#define		tCheckTxStatus		500   /* 500ms // Useless */
+#define		tUpdateRxCounter	100   /* 100ms */
+
+#define		rateCCK		0	/* Useless */
+#define		rateOFDM	1
+#define		rateHT		2
+
+/* define Register-End */
+#define		bPMAC_End			0x1ff	/* Useless */
+#define		bFPGAPHY0_End		0x8ff
+#define		bFPGAPHY1_End		0x9ff
+#define		bCCKPHY0_End		0xaff
+#define		bOFDMPHY0_End		0xcff
+#define		bOFDMPHY1_End		0xdff
+
+/* define max debug item in each debug page
+ * #define bMaxItem_FPGA_PHY0        0x9
+ * #define bMaxItem_FPGA_PHY1        0x3
+ * #define bMaxItem_PHY_11B          0x16
+ * #define bMaxItem_OFDM_PHY0        0x29
+ * #define bMaxItem_OFDM_PHY1        0x0 */
+
+#define		bPMACControl		0x0		/* Useless */
+#define		bWMACControl		0x1
+#define		bWNICControl		0x2
+
+#define		PathA			0x0	/* Useless */
+#define		PathB			0x1
+#define		PathC			0x2
+#define		PathD			0x3
+
+#endif
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/include/Hal8710BPwrSeq.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/Hal8710BPwrSeq.h
--- linux-5.6.3/3rdparty/rtl8821ce/include/Hal8710BPwrSeq.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/Hal8710BPwrSeq.h	2020-04-10 16:35:06.845661421 +0300
@@ -0,0 +1,167 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2016 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#ifndef REALTEK_POWER_SEQUENCE_8710B
+#define REALTEK_POWER_SEQUENCE_8710B
+
+/* #include "PwrSeqCmd.h" */
+#include "HalPwrSeqCmd.h"
+
+/*
+	Check document WM-20110607-Paul-RTL8192e_Power_Architecture-R02.vsd
+	There are 6 HW Power States:
+	0: POFF--Power Off
+	1: PDN--Power Down
+	2: CARDEMU--Card Emulation
+	3: ACT--Active Mode
+	4: LPS--Low Power State
+	5: SUS--Suspend
+
+	The transition from different states are defined below
+	TRANS_CARDEMU_TO_ACT
+	TRANS_ACT_TO_CARDEMU
+	TRANS_CARDEMU_TO_SUS
+	TRANS_SUS_TO_CARDEMU
+	TRANS_CARDEMU_TO_PDN
+	TRANS_ACT_TO_LPS
+	TRANS_LPS_TO_ACT
+
+	TRANS_END
+*/
+#define RTL8710B_TRANS_CARDEMU_TO_ACT_STEPS 5
+#define RTL8710B_TRANS_ACT_TO_CARDEMU_STEPS 4
+#define RTL8710B_TRANS_CARDEMU_TO_SUS_STEPS 7
+#define RTL8710B_TRANS_SUS_TO_CARDEMU_STEPS 15
+#define RTL8710B_TRANS_CARDEMU_TO_PDN_STEPS 15
+#define RTL8710B_TRANS_PDN_TO_CARDEMU_STEPS 15
+#define RTL8710B_TRANS_ACT_TO_LPS_STEPS 	15
+#define RTL8710B_TRANS_LPS_TO_ACT_STEPS 	15	
+#define RTL8710B_TRANS_ACT_TO_SWLPS_STEPS		22
+#define RTL8710B_TRANS_SWLPS_TO_ACT_STEPS		15
+#define RTL8710B_TRANS_END_STEPS		1
+
+
+#define RTL8710B_TRANS_CARDEMU_TO_ACT 														\
+	/* format */																\
+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
+	{0x005D, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, 0},/*AFE power mode selection:1:  LDO mode ,0:  Power-cut mode*/\
+	{0x0004, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, 1},\
+	{0x0056, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x0E},\
+	{0x0020, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, 1},\
+	{0x0020, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, BIT0, 0},/**/ 
+
+	
+#define RTL8710B_TRANS_ACT_TO_CARDEMU													\
+	/* format */																\
+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
+	/*{0x001F, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0}, */ /*0x1F[7:0] = 0 turn off RF*/	\
+	{0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, (BIT0|BIT1|BIT2), 0},/*0x04[24:26] = 0 turn off RF*/	\
+	{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, (BIT0|BIT1), 0},/*0x04[16:17] = 0 BB reset*/	\
+	{0x0020, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, BIT1}, /*0x20[1] = 1 turn off MAC by HW state machine*/	\
+	{0x0020, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, BIT1, 0}, /*wait till 0x20[1] = 0 polling until return 0 to disable*/ \
+
+
+#define RTL8710B_TRANS_CARDEMU_TO_SUS													\
+	/* format */																\
+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4|BIT3, (BIT4|BIT3)}, /*0x04[12:11] = 2b'11 enable WL suspend for PCIe*/ \
+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3|BIT4, BIT3}, /*0x04[12:11] = 2b'01 enable WL suspend*/	\
+	{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, BIT4}, /*0x23[4] = 1b'1 12H LDO enter sleep mode*/	\
+	{0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x20}, /*0x07[7:0] = 0x20 SDIO SOP option to disable BG/MB/ACK/SWR*/   \
+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3|BIT4, BIT3|BIT4}, /*0x04[12:11] = 2b'11 enable WL suspend for PCIe*/	\
+	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_WRITE, BIT0, BIT0}, /*Set SDIO suspend local register*/	\
+	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_POLLING, BIT1, 0}, /*wait power state to suspend*/
+
+#define RTL8710B_TRANS_SUS_TO_CARDEMU													\
+	/* format */																\
+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3 | BIT7, 0}, /*clear suspend enable and power down enable*/ \
+	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_WRITE, BIT0, 0}, /*Set SDIO suspend local register*/ \
+	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_POLLING, BIT1, BIT1}, /*wait power state to suspend*/\
+	{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, 0}, /*0x23[4] = 1b'0 12H LDO enter normal mode*/   \
+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3|BIT4, 0}, /*0x04[12:11] = 2b'01enable WL suspend*/
+	
+
+#define RTL8710B_TRANS_CARDEMU_TO_CARDDIS													\
+	/* format */																\
+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/	\
+
+#define RTL8710B_TRANS_CARDDIS_TO_CARDEMU													\
+	/* format */																\
+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
+
+
+#define RTL8710B_TRANS_CARDEMU_TO_PDN												\
+	/* format */																\
+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
+	{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, BIT4}, /*0x23[4] = 1b'1 12H LDO enter sleep mode*/	\
+	{0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK|PWR_INTF_USB_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x20}, /*0x07[7:0] = 0x20 SOP option to disable BG/MB/ACK/SWR*/   \
+	{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, 0},/* 0x04[16] = 0*/\
+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT7, BIT7},/* 0x04[15] = 1*/
+
+#define RTL8710B_TRANS_PDN_TO_CARDEMU												\
+	/* format */																\
+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT7, 0},/* 0x04[15] = 0*/
+
+#define RTL8710B_TRANS_ACT_TO_LPS														\
+	/* format */																\
+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
+	{0x0301, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0xFF},/*PCIe DMA stop*/	\
+	{0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0xFF},/*Tx Pause*/	\
+	{0x05F8, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/	\
+	{0x05F9, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/	\
+	{0x05FA, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/	\
+	{0x05FB, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/	\
+	{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, 0},/*CCK and OFDM are disabled,and clock are gated*/	\
+	{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_DELAY, 0, PWRSEQ_DELAY_US},/*Delay 1us*/	\
+	{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, 0},/*Whole BB is reset*/	\
+	{0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x03},/*Reset MAC TRX*/	\
+	{0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, 0},/*check if removed later*/ \
+	{0x0093, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x00},/*When driver enter Sus/ Disable, enable LOP for BT*/	\
+	{0x0553, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT5, BIT5},/*Respond TxOK to scheduler*/	
+
+
+#define RTL8710B_TRANS_LPS_TO_ACT															\
+	/* format */																\
+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
+	{0x0080, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_WRITE, 0xFF, 0x84}, /*SDIO RPWM*/\
+	{0xFE58, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x84}, /*USB RPWM*/\
+	{0x0361, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x84}, /*PCIe RPWM*/\
+	{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_DELAY, 0, PWRSEQ_DELAY_MS}, /*Delay*/\
+	{0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, 0}, /*.	0x08[4] = 0 	 switch TSF to 40M*/\
+	{0x0109, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, BIT7, 0}, /*Polling 0x109[7]=0  TSF in 40M*/\
+	{0x0029, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT6|BIT7, 0}, /*.	0x29[7:6] = 2b'00	 enable BB clock*/\
+	{0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, BIT1}, /*.	0x101[1] = 1*/\
+	{0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0xFF}, /*.	0x100[7:0] = 0xFF	 enable WMAC TRX*/\
+	{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1|BIT0, BIT1|BIT0}, /*.	0x02[1:0] = 2b'11	 enable BB macro*/\
+	{0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0}, /*.	0x522 = 0*/
+ 
+#define RTL8710B_TRANS_END															\
+	/* format */																\
+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
+	{0xFFFF, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,0,PWR_CMD_END, 0, 0}, //
+
+
+extern WLAN_PWR_CFG rtl8710B_power_on_flow[RTL8710B_TRANS_CARDEMU_TO_ACT_STEPS+RTL8710B_TRANS_END_STEPS];
+extern WLAN_PWR_CFG rtl8710B_radio_off_flow[RTL8710B_TRANS_ACT_TO_CARDEMU_STEPS+RTL8710B_TRANS_END_STEPS];
+extern WLAN_PWR_CFG rtl8710B_card_disable_flow[RTL8710B_TRANS_ACT_TO_CARDEMU_STEPS+RTL8710B_TRANS_CARDEMU_TO_PDN_STEPS+RTL8710B_TRANS_END_STEPS];
+extern WLAN_PWR_CFG rtl8710B_card_enable_flow[RTL8710B_TRANS_ACT_TO_CARDEMU_STEPS+RTL8710B_TRANS_CARDEMU_TO_PDN_STEPS+RTL8710B_TRANS_END_STEPS];
+extern WLAN_PWR_CFG rtl8710B_suspend_flow[RTL8710B_TRANS_ACT_TO_CARDEMU_STEPS+RTL8710B_TRANS_CARDEMU_TO_SUS_STEPS+RTL8710B_TRANS_END_STEPS];
+extern WLAN_PWR_CFG rtl8710B_resume_flow[RTL8710B_TRANS_SUS_TO_CARDEMU_STEPS+RTL8710B_TRANS_CARDEMU_TO_ACT_STEPS+RTL8710B_TRANS_END_STEPS];
+extern WLAN_PWR_CFG rtl8710B_hwpdn_flow[RTL8710B_TRANS_ACT_TO_CARDEMU_STEPS+RTL8710B_TRANS_CARDEMU_TO_PDN_STEPS+RTL8710B_TRANS_END_STEPS];
+extern WLAN_PWR_CFG rtl8710B_enter_lps_flow[RTL8710B_TRANS_ACT_TO_LPS_STEPS+RTL8710B_TRANS_END_STEPS];
+extern WLAN_PWR_CFG rtl8710B_leave_lps_flow[RTL8710B_TRANS_LPS_TO_ACT_STEPS+RTL8710B_TRANS_END_STEPS];
+
+#endif
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/include/Hal8723BPhyCfg.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/Hal8723BPhyCfg.h
--- linux-5.6.3/3rdparty/rtl8821ce/include/Hal8723BPhyCfg.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/Hal8723BPhyCfg.h	2020-04-10 16:35:06.845661421 +0300
@@ -0,0 +1,132 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#ifndef __INC_HAL8723BPHYCFG_H__
+#define __INC_HAL8723BPHYCFG_H__
+
+/*--------------------------Define Parameters-------------------------------*/
+#define LOOP_LIMIT				5
+#define MAX_STALL_TIME			50		/* us */
+#define AntennaDiversityValue	0x80	/* (Adapter->bSoftwareAntennaDiversity ? 0x00 : 0x80) */
+#define MAX_TXPWR_IDX_NMODE_92S	63
+#define Reset_Cnt_Limit			3
+
+#ifdef CONFIG_PCI_HCI
+	#define MAX_AGGR_NUM	0x0B
+#else
+	#define MAX_AGGR_NUM	0x07
+#endif /* CONFIG_PCI_HCI */
+
+
+/*--------------------------Define Parameters End-------------------------------*/
+
+
+/*------------------------------Define structure----------------------------*/
+
+/*------------------------------Define structure End----------------------------*/
+
+/*--------------------------Exported Function prototype---------------------*/
+u32
+PHY_QueryBBReg_8723B(
+	IN	PADAPTER	Adapter,
+	IN	u32		RegAddr,
+	IN	u32		BitMask
+);
+
+VOID
+PHY_SetBBReg_8723B(
+	IN	PADAPTER	Adapter,
+	IN	u32		RegAddr,
+	IN	u32		BitMask,
+	IN	u32		Data
+);
+
+u32
+PHY_QueryRFReg_8723B(
+	IN	PADAPTER			Adapter,
+	IN	enum rf_path			eRFPath,
+	IN	u32				RegAddr,
+	IN	u32				BitMask
+);
+
+VOID
+PHY_SetRFReg_8723B(
+	IN	PADAPTER			Adapter,
+	IN	enum rf_path			eRFPath,
+	IN	u32				RegAddr,
+	IN	u32				BitMask,
+	IN	u32				Data
+);
+
+/* MAC/BB/RF HAL config */
+int PHY_BBConfig8723B(PADAPTER	Adapter);
+
+int PHY_RFConfig8723B(PADAPTER	Adapter);
+
+s32 PHY_MACConfig8723B(PADAPTER padapter);
+
+int
+PHY_ConfigRFWithParaFile_8723B(
+	IN	PADAPTER			Adapter,
+	IN	u8					*pFileName,
+	enum rf_path				eRFPath
+);
+
+VOID
+PHY_SetTxPowerIndex_8723B(
+	IN	PADAPTER			Adapter,
+	IN	u32					PowerIndex,
+	IN	enum rf_path			RFPath,
+	IN	u8					Rate
+);
+
+u8
+PHY_GetTxPowerIndex_8723B(
+	IN	PADAPTER			pAdapter,
+	IN	enum rf_path			RFPath,
+	IN	u8					Rate,
+	IN	u8					BandWidth,
+	IN	u8					Channel,
+	struct txpwr_idx_comp *tic
+);
+
+VOID
+PHY_GetTxPowerLevel8723B(
+	IN	PADAPTER		Adapter,
+	OUT s32				*powerlevel
+);
+
+VOID
+PHY_SetTxPowerLevel8723B(
+	IN	PADAPTER		Adapter,
+	IN	u8			channel
+);
+
+VOID
+PHY_SetSwChnlBWMode8723B(
+	IN	PADAPTER			Adapter,
+	IN	u8					channel,
+	IN	enum channel_width	Bandwidth,
+	IN	u8					Offset40,
+	IN	u8					Offset80
+);
+
+VOID phy_set_rf_path_switch_8723b(
+	IN	struct dm_struct		*phydm,
+	IN	bool		bMain
+);
+
+/*--------------------------Exported Function prototype End---------------------*/
+
+#endif
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/include/Hal8723BPhyReg.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/Hal8723BPhyReg.h
--- linux-5.6.3/3rdparty/rtl8821ce/include/Hal8723BPhyReg.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/Hal8723BPhyReg.h	2020-04-10 16:35:06.845661421 +0300
@@ -0,0 +1,1131 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#ifndef __INC_HAL8723BPHYREG_H__
+#define __INC_HAL8723BPHYREG_H__
+
+#define		rSYM_WLBT_PAPE_SEL		0x64
+/*
+ * BB-PHY register PMAC 0x100 PHY 0x800 - 0xEFF
+ * 1. PMAC duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF
+ * 2. 0x800/0x900/0xA00/0xC00/0xD00/0xE00
+ * 3. RF register 0x00-2E
+ * 4. Bit Mask for BB/RF register
+ * 5. Other defintion for BB/RF R/W
+ *   */
+
+
+/*
+ * 1. PMAC duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF
+ * 1. Page1(0x100)
+ *   */
+#define		rPMAC_Reset					0x100
+#define		rPMAC_TxStart					0x104
+#define		rPMAC_TxLegacySIG				0x108
+#define		rPMAC_TxHTSIG1				0x10c
+#define		rPMAC_TxHTSIG2				0x110
+#define		rPMAC_PHYDebug				0x114
+#define		rPMAC_TxPacketNum				0x118
+#define		rPMAC_TxIdle					0x11c
+#define		rPMAC_TxMACHeader0			0x120
+#define		rPMAC_TxMACHeader1			0x124
+#define		rPMAC_TxMACHeader2			0x128
+#define		rPMAC_TxMACHeader3			0x12c
+#define		rPMAC_TxMACHeader4			0x130
+#define		rPMAC_TxMACHeader5			0x134
+#define		rPMAC_TxDataType				0x138
+#define		rPMAC_TxRandomSeed			0x13c
+#define		rPMAC_CCKPLCPPreamble			0x140
+#define		rPMAC_CCKPLCPHeader			0x144
+#define		rPMAC_CCKCRC16				0x148
+#define		rPMAC_OFDMRxCRC32OK			0x170
+#define		rPMAC_OFDMRxCRC32Er			0x174
+#define		rPMAC_OFDMRxParityEr			0x178
+#define		rPMAC_OFDMRxCRC8Er			0x17c
+#define		rPMAC_CCKCRxRC16Er			0x180
+#define		rPMAC_CCKCRxRC32Er			0x184
+#define		rPMAC_CCKCRxRC32OK			0x188
+#define		rPMAC_TxStatus					0x18c
+
+/*
+ * 2. Page2(0x200)
+ *
+ * The following two definition are only used for USB interface. */
+#define		RF_BB_CMD_ADDR				0x02c0	/* RF/BB read/write command address. */
+#define		RF_BB_CMD_DATA				0x02c4	/* RF/BB read/write command data. */
+
+/*
+ * 3. Page8(0x800)
+ *   */
+#define		rFPGA0_RFMOD				0x800	/* RF mode & CCK TxSC */ /* RF BW Setting?? */
+
+#define		rFPGA0_TxInfo				0x804	/* Status report?? */
+#define		rFPGA0_PSDFunction			0x808
+
+#define		rFPGA0_TxGainStage			0x80c	/* Set TX PWR init gain? */
+
+#define		rFPGA0_RFTiming1			0x810	/* Useless now */
+#define		rFPGA0_RFTiming2			0x814
+
+#define		rFPGA0_XA_HSSIParameter1		0x820	/* RF 3 wire register */
+#define		rFPGA0_XA_HSSIParameter2		0x824
+#define		rFPGA0_XB_HSSIParameter1		0x828
+#define		rFPGA0_XB_HSSIParameter2		0x82c
+#define		rTxAGC_B_Rate18_06				0x830
+#define		rTxAGC_B_Rate54_24				0x834
+#define		rTxAGC_B_CCK1_55_Mcs32		0x838
+#define		rTxAGC_B_Mcs03_Mcs00			0x83c
+
+#define		rTxAGC_B_Mcs07_Mcs04			0x848
+#define		rTxAGC_B_Mcs11_Mcs08			0x84c
+
+#define		rFPGA0_XA_LSSIParameter		0x840
+#define		rFPGA0_XB_LSSIParameter		0x844
+
+#define		rFPGA0_RFWakeUpParameter		0x850	/* Useless now */
+#define		rFPGA0_RFSleepUpParameter		0x854
+
+#define		rFPGA0_XAB_SwitchControl		0x858	/* RF Channel switch */
+#define		rFPGA0_XCD_SwitchControl		0x85c
+
+#define		rFPGA0_XA_RFInterfaceOE		0x860	/* RF Channel switch */
+#define		rFPGA0_XB_RFInterfaceOE		0x864
+
+#define		rTxAGC_B_Mcs15_Mcs12			0x868
+#define		rTxAGC_B_CCK11_A_CCK2_11		0x86c
+
+#define		rFPGA0_XAB_RFInterfaceSW		0x870	/* RF Interface Software Control */
+#define		rFPGA0_XCD_RFInterfaceSW		0x874
+
+#define		rFPGA0_XAB_RFParameter		0x878	/* RF Parameter */
+#define		rFPGA0_XCD_RFParameter		0x87c
+
+#define		rFPGA0_AnalogParameter1		0x880	/* Crystal cap setting RF-R/W protection for parameter4?? */
+#define		rFPGA0_AnalogParameter2		0x884
+#define		rFPGA0_AnalogParameter3		0x888	/* Useless now */
+#define		rFPGA0_AnalogParameter4		0x88c
+
+#define		rFPGA0_XA_LSSIReadBack		0x8a0	/* Tranceiver LSSI Readback */
+#define		rFPGA0_XB_LSSIReadBack		0x8a4
+#define		rFPGA0_XC_LSSIReadBack		0x8a8
+#define		rFPGA0_XD_LSSIReadBack		0x8ac
+
+#define		rFPGA0_PSDReport				0x8b4	/* Useless now */
+#define		TransceiverA_HSPI_Readback	0x8b8	/* Transceiver A HSPI Readback */
+#define		TransceiverB_HSPI_Readback	0x8bc	/* Transceiver B HSPI Readback */
+#define		rFPGA0_XAB_RFInterfaceRB		0x8e0	/* Useless now */ /* RF Interface Readback Value */
+#define		rFPGA0_XCD_RFInterfaceRB		0x8e4	/* Useless now */
+
+/*
+ * 4. Page9(0x900)
+ *   */
+#define	rFPGA1_RFMOD				0x900	/* RF mode & OFDM TxSC */ /* RF BW Setting?? */
+#define	rFPGA1_TxBlock				0x904	/* Useless now */
+#define	rFPGA1_DebugSelect			0x908	/* Useless now */
+#define	rFPGA1_TxInfo				0x90c	/* Useless now */ /* Status report?? */
+#define	rDPDT_control				0x92c
+#define	rfe_ctrl_anta_src				0x930
+#define	rS0S1_PathSwitch			0x948
+
+/*
+ * 5. PageA(0xA00)
+ *
+ * Set Control channel to upper or lower. These settings are required only for 40MHz */
+#define		rCCK0_System				0xa00
+
+#define		rCCK0_AFESetting			0xa04	/* Disable init gain now */ /* Select RX path by RSSI */
+#define		rCCK0_CCA					0xa08	/* Disable init gain now */ /* Init gain */
+
+#define		rCCK0_RxAGC1				0xa0c	/* AGC default value, saturation level  */ /* Antenna Diversity, RX AGC, LNA Threshold, RX LNA Threshold useless now. Not the same as 90 series */
+#define		rCCK0_RxAGC2				0xa10	/* AGC & DAGC */
+
+#define		rCCK0_RxHP					0xa14
+
+#define		rCCK0_DSPParameter1		0xa18	/* Timing recovery & Channel estimation threshold */
+#define		rCCK0_DSPParameter2		0xa1c	/* SQ threshold */
+
+#define		rCCK0_TxFilter1				0xa20
+#define		rCCK0_TxFilter2				0xa24
+#define		rCCK0_DebugPort			0xa28	/* debug port and Tx filter3 */
+#define		rCCK0_FalseAlarmReport		0xa2c	/* 0xa2d	useless now 0xa30-a4f channel report */
+#define		rCCK0_TRSSIReport		0xa50
+#define		rCCK0_RxReport            		0xa54  /* 0xa57 */
+#define		rCCK0_FACounterLower      	0xa5c  /* 0xa5b */
+#define		rCCK0_FACounterUpper      	0xa58  /* 0xa5c */
+
+/*
+ * PageB(0xB00)
+ *   */
+#define rPdp_AntA						0xb00
+#define rPdp_AntA_4						0xb04
+#define rPdp_AntA_8						0xb08
+#define rPdp_AntA_C						0xb0c
+#define rPdp_AntA_10					0xb10
+#define rPdp_AntA_14					0xb14
+#define rPdp_AntA_18					0xb18
+#define rPdp_AntA_1C					0xb1c
+#define rPdp_AntA_20					0xb20
+#define rPdp_AntA_24					0xb24
+
+#define rConfig_Pmpd_AntA				0xb28
+#define rConfig_ram64x16				0xb2c
+
+#define rBndA							0xb30
+#define rHssiPar						0xb34
+
+#define rConfig_AntA					0xb68
+#define rConfig_AntB					0xb6c
+
+#define rPdp_AntB						0xb70
+#define rPdp_AntB_4						0xb74
+#define rPdp_AntB_8						0xb78
+#define rPdp_AntB_C						0xb7c
+#define rPdp_AntB_10					0xb80
+#define rPdp_AntB_14					0xb84
+#define rPdp_AntB_18					0xb88
+#define rPdp_AntB_1C					0xb8c
+#define rPdp_AntB_20					0xb90
+#define rPdp_AntB_24					0xb94
+
+#define rConfig_Pmpd_AntB				0xb98
+
+#define rBndB							0xba0
+
+#define rAPK							0xbd8
+#define rPm_Rx0_AntA					0xbdc
+#define rPm_Rx1_AntA					0xbe0
+#define rPm_Rx2_AntA					0xbe4
+#define rPm_Rx3_AntA					0xbe8
+#define rPm_Rx0_AntB					0xbec
+#define rPm_Rx1_AntB					0xbf0
+#define rPm_Rx2_AntB					0xbf4
+#define rPm_Rx3_AntB					0xbf8
+/*
+ * 6. PageC(0xC00)
+ *   */
+#define		rOFDM0_LSTF				0xc00
+
+#define		rOFDM0_TRxPathEnable		0xc04
+#define		rOFDM0_TRMuxPar			0xc08
+#define		rOFDM0_TRSWIsolation		0xc0c
+
+#define		rOFDM0_XARxAFE			0xc10  /* RxIQ DC offset, Rx digital filter, DC notch filter */
+#define		rOFDM0_XARxIQImbalance    	0xc14  /* RxIQ imblance matrix */
+#define		rOFDM0_XBRxAFE		0xc18
+#define		rOFDM0_XBRxIQImbalance	0xc1c
+#define		rOFDM0_XCRxAFE		0xc20
+#define		rOFDM0_XCRxIQImbalance	0xc24
+#define		rOFDM0_XDRxAFE		0xc28
+#define		rOFDM0_XDRxIQImbalance	0xc2c
+
+#define		rOFDM0_RxDetector1			0xc30  /* PD, BW & SBD	 */ /* DM tune init gain */
+#define		rOFDM0_RxDetector2			0xc34  /* SBD & Fame Sync. */
+#define		rOFDM0_RxDetector3			0xc38  /* Frame Sync. */
+#define		rOFDM0_RxDetector4			0xc3c  /* PD, SBD, Frame Sync & Short-GI */
+
+#define		rOFDM0_RxDSP				0xc40  /* Rx Sync Path */
+#define		rOFDM0_CFOandDAGC		0xc44  /* CFO & DAGC */
+#define		rOFDM0_CCADropThreshold	0xc48 /* CCA Drop threshold */
+#define		rOFDM0_ECCAThreshold		0xc4c /* energy CCA */
+
+#define		rOFDM0_XAAGCCore1			0xc50	/* DIG */
+#define		rOFDM0_XAAGCCore2			0xc54
+#define		rOFDM0_XBAGCCore1			0xc58
+#define		rOFDM0_XBAGCCore2			0xc5c
+#define		rOFDM0_XCAGCCore1			0xc60
+#define		rOFDM0_XCAGCCore2			0xc64
+#define		rOFDM0_XDAGCCore1			0xc68
+#define		rOFDM0_XDAGCCore2			0xc6c
+
+#define		rOFDM0_AGCParameter1			0xc70
+#define		rOFDM0_AGCParameter2			0xc74
+#define		rOFDM0_AGCRSSITable			0xc78
+#define		rOFDM0_HTSTFAGC				0xc7c
+
+#define		rOFDM0_XATxIQImbalance		0xc80	/* TX PWR TRACK and DIG */
+#define		rOFDM0_XATxAFE				0xc84
+#define		rOFDM0_XBTxIQImbalance		0xc88
+#define		rOFDM0_XBTxAFE				0xc8c
+#define		rOFDM0_XCTxIQImbalance		0xc90
+#define		rOFDM0_XCTxAFE			0xc94
+#define		rOFDM0_XDTxIQImbalance		0xc98
+#define		rOFDM0_XDTxAFE				0xc9c
+
+#define		rOFDM0_RxIQExtAnta			0xca0
+#define		rOFDM0_TxCoeff1				0xca4
+#define		rOFDM0_TxCoeff2				0xca8
+#define		rOFDM0_TxCoeff3				0xcac
+#define		rOFDM0_TxCoeff4				0xcb0
+#define		rOFDM0_TxCoeff5				0xcb4
+#define		rOFDM0_TxCoeff6				0xcb8
+#define		rOFDM0_RxHPParameter			0xce0
+#define		rOFDM0_TxPseudoNoiseWgt		0xce4
+#define		rOFDM0_FrameSync				0xcf0
+#define		rOFDM0_DFSReport				0xcf4
+
+/*
+ * 7. PageD(0xD00)
+ *   */
+#define		rOFDM1_LSTF					0xd00
+#define		rOFDM1_TRxPathEnable			0xd04
+
+#define		rOFDM1_CFO						0xd08	/* No setting now */
+#define		rOFDM1_CSI1					0xd10
+#define		rOFDM1_SBD						0xd14
+#define		rOFDM1_CSI2					0xd18
+#define		rOFDM1_CFOTracking			0xd2c
+#define		rOFDM1_TRxMesaure1			0xd34
+#define		rOFDM1_IntfDet					0xd3c
+#define		rOFDM1_PseudoNoiseStateAB		0xd50
+#define		rOFDM1_PseudoNoiseStateCD		0xd54
+#define		rOFDM1_RxPseudoNoiseWgt		0xd58
+
+#define		rOFDM_PHYCounter1				0xda0  /* cca, parity fail */
+#define		rOFDM_PHYCounter2				0xda4  /* rate illegal, crc8 fail */
+#define		rOFDM_PHYCounter3				0xda8  /* MCS not support */
+
+#define		rOFDM_ShortCFOAB				0xdac	/* No setting now */
+#define		rOFDM_ShortCFOCD				0xdb0
+#define		rOFDM_LongCFOAB				0xdb4
+#define		rOFDM_LongCFOCD				0xdb8
+#define		rOFDM_TailCFOAB				0xdbc
+#define		rOFDM_TailCFOCD				0xdc0
+#define		rOFDM_PWMeasure1		0xdc4
+#define		rOFDM_PWMeasure2		0xdc8
+#define		rOFDM_BWReport				0xdcc
+#define		rOFDM_AGCReport				0xdd0
+#define		rOFDM_RxSNR					0xdd4
+#define		rOFDM_RxEVMCSI				0xdd8
+#define		rOFDM_SIGReport				0xddc
+
+
+/*
+ * 8. PageE(0xE00)
+ *   */
+#define		rTxAGC_A_Rate18_06			0xe00
+#define		rTxAGC_A_Rate54_24			0xe04
+#define		rTxAGC_A_CCK1_Mcs32			0xe08
+#define		rTxAGC_A_Mcs03_Mcs00			0xe10
+#define		rTxAGC_A_Mcs07_Mcs04			0xe14
+#define		rTxAGC_A_Mcs11_Mcs08			0xe18
+#define		rTxAGC_A_Mcs15_Mcs12			0xe1c
+
+#define		rFPGA0_IQK					0xe28
+#define		rTx_IQK_Tone_A				0xe30
+#define		rRx_IQK_Tone_A				0xe34
+#define		rTx_IQK_PI_A					0xe38
+#define		rRx_IQK_PI_A					0xe3c
+
+#define		rTx_IQK						0xe40
+#define		rRx_IQK						0xe44
+#define		rIQK_AGC_Pts					0xe48
+#define		rIQK_AGC_Rsp					0xe4c
+#define		rTx_IQK_Tone_B				0xe50
+#define		rRx_IQK_Tone_B				0xe54
+#define		rTx_IQK_PI_B					0xe58
+#define		rRx_IQK_PI_B					0xe5c
+#define		rIQK_AGC_Cont				0xe60
+
+#define		rBlue_Tooth					0xe6c
+#define		rRx_Wait_CCA					0xe70
+#define		rTx_CCK_RFON					0xe74
+#define		rTx_CCK_BBON				0xe78
+#define		rTx_OFDM_RFON				0xe7c
+#define		rTx_OFDM_BBON				0xe80
+#define		rTx_To_Rx					0xe84
+#define		rTx_To_Tx					0xe88
+#define		rRx_CCK						0xe8c
+
+#define		rTx_Power_Before_IQK_A		0xe94
+#define		rTx_Power_After_IQK_A			0xe9c
+
+#define		rRx_Power_Before_IQK_A		0xea0
+#define		rRx_Power_Before_IQK_A_2		0xea4
+#define		rRx_Power_After_IQK_A			0xea8
+#define		rRx_Power_After_IQK_A_2		0xeac
+
+#define		rTx_Power_Before_IQK_B		0xeb4
+#define		rTx_Power_After_IQK_B			0xebc
+
+#define		rRx_Power_Before_IQK_B		0xec0
+#define		rRx_Power_Before_IQK_B_2		0xec4
+#define		rRx_Power_After_IQK_B			0xec8
+#define		rRx_Power_After_IQK_B_2		0xecc
+
+#define		rRx_OFDM					0xed0
+#define		rRx_Wait_RIFS				0xed4
+#define		rRx_TO_Rx					0xed8
+#define		rStandby						0xedc
+#define		rSleep						0xee0
+#define		rPMPD_ANAEN				0xeec
+
+/*
+ * 7. RF Register 0x00-0x2E (RF 8256)
+ * RF-0222D 0x00-3F
+ *
+ * Zebra1 */
+#define		rZebra1_HSSIEnable				0x0	/* Useless now */
+#define		rZebra1_TRxEnable1				0x1
+#define		rZebra1_TRxEnable2				0x2
+#define		rZebra1_AGC					0x4
+#define		rZebra1_ChargePump			0x5
+#define		rZebra1_Channel				0x7	/* RF channel switch */
+
+/* #endif */
+#define		rZebra1_TxGain					0x8	/* Useless now */
+#define		rZebra1_TxLPF					0x9
+#define		rZebra1_RxLPF					0xb
+#define		rZebra1_RxHPFCorner			0xc
+
+/* Zebra4 */
+#define		rGlobalCtrl						0	/* Useless now */
+#define		rRTL8256_TxLPF					19
+#define		rRTL8256_RxLPF					11
+
+/* RTL8258 */
+#define		rRTL8258_TxLPF					0x11	/* Useless now */
+#define		rRTL8258_RxLPF					0x13
+#define		rRTL8258_RSSILPF				0xa
+
+/*
+ * RL6052 Register definition
+ *   */
+#define		RF_AC						0x00	/*  */
+
+#define		RF_IQADJ_G1				0x01	/*  */
+#define		RF_IQADJ_G2				0x02	/*  */
+#define		RF_BS_PA_APSET_G1_G4		0x03
+#define		RF_BS_PA_APSET_G5_G8		0x04
+#define		RF_POW_TRSW				0x05	/*  */
+
+#define		RF_GAIN_RX					0x06	/*  */
+#define		RF_GAIN_TX					0x07	/*  */
+
+#define		RF_TXM_IDAC				0x08	/*  */
+#define		RF_IPA_G					0x09	/*  */
+#define		RF_TXBIAS_G				0x0A
+#define		RF_TXPA_AG					0x0B
+#define		RF_IPA_A					0x0C	/*  */
+#define		RF_TXBIAS_A				0x0D
+#define		RF_BS_PA_APSET_G9_G11	0x0E
+#define		RF_BS_IQGEN				0x0F	/*  */
+
+#define		RF_MODE1					0x10	/*  */
+#define		RF_MODE2					0x11	/*  */
+
+#define		RF_RX_AGC_HP				0x12	/*  */
+#define		RF_TX_AGC					0x13	/*  */
+#define		RF_BIAS						0x14	/*  */
+#define		RF_IPA						0x15	/*  */
+#define		RF_TXBIAS					0x16
+#define		RF_POW_ABILITY			0x17	/*  */
+#define		RF_MODE_AG				0x18	/*  */
+#define		rRfChannel					0x18	/* RF channel and BW switch */
+#define		RF_CHNLBW					0x18	/* RF channel and BW switch */
+#define		RF_TOP						0x19	/*  */
+
+#define		RF_RX_G1					0x1A	/*  */
+#define		RF_RX_G2					0x1B	/*  */
+
+#define		RF_RX_BB2					0x1C	/*  */
+#define		RF_RX_BB1					0x1D	/*  */
+
+#define		RF_RCK1					0x1E	/*  */
+#define		RF_RCK2					0x1F	/*  */
+
+#define		RF_TX_G1					0x20	/*  */
+#define		RF_TX_G2					0x21	/*  */
+#define		RF_TX_G3					0x22	/*  */
+
+#define		RF_TX_BB1					0x23	/*  */
+
+#define		RF_T_METER					0x24	/*  */
+
+#define		RF_SYN_G1					0x25	/* RF TX Power control */
+#define		RF_SYN_G2					0x26	/* RF TX Power control */
+#define		RF_SYN_G3					0x27	/* RF TX Power control */
+#define		RF_SYN_G4					0x28	/* RF TX Power control */
+#define		RF_SYN_G5					0x29	/* RF TX Power control */
+#define		RF_SYN_G6					0x2A	/* RF TX Power control */
+#define		RF_SYN_G7					0x2B	/* RF TX Power control */
+#define		RF_SYN_G8					0x2C	/* RF TX Power control */
+
+#define		RF_RCK_OS					0x30	/* RF TX PA control */
+
+#define		RF_TXPA_G1					0x31	/* RF TX PA control */
+#define		RF_TXPA_G2					0x32	/* RF TX PA control */
+#define		RF_TXPA_G3					0x33	/* RF TX PA control */
+#define	RF_TX_BIAS_A				0x35
+#define	RF_TX_BIAS_D				0x36
+#define	RF_LOBF_9					0x38
+#define 	RF_RXRF_A3					0x3C	/*	 */
+#define	RF_TRSW					0x3F
+
+#define	RF_TXRF_A2					0x41
+#define	RF_TXPA_G4					0x46
+#define	RF_TXPA_A4					0x4B
+#define	RF_0x52					0x52
+#define	RF_WE_LUT					0xEF
+#define	RF_S0S1					0xB0
+
+/*
+ * Bit Mask
+ *
+ * 1. Page1(0x100) */
+#define		bBBResetB						0x100	/* Useless now? */
+#define		bGlobalResetB					0x200
+#define		bOFDMTxStart					0x4
+#define		bCCKTxStart						0x8
+#define		bCRC32Debug					0x100
+#define		bPMACLoopback					0x10
+#define		bTxLSIG							0xffffff
+#define		bOFDMTxRate					0xf
+#define		bOFDMTxReserved				0x10
+#define		bOFDMTxLength					0x1ffe0
+#define		bOFDMTxParity					0x20000
+#define		bTxHTSIG1						0xffffff
+#define		bTxHTMCSRate					0x7f
+#define		bTxHTBW						0x80
+#define		bTxHTLength					0xffff00
+#define		bTxHTSIG2						0xffffff
+#define		bTxHTSmoothing					0x1
+#define		bTxHTSounding					0x2
+#define		bTxHTReserved					0x4
+#define		bTxHTAggreation				0x8
+#define		bTxHTSTBC						0x30
+#define		bTxHTAdvanceCoding			0x40
+#define		bTxHTShortGI					0x80
+#define		bTxHTNumberHT_LTF			0x300
+#define		bTxHTCRC8						0x3fc00
+#define		bCounterReset					0x10000
+#define		bNumOfOFDMTx					0xffff
+#define		bNumOfCCKTx					0xffff0000
+#define		bTxIdleInterval					0xffff
+#define		bOFDMService					0xffff0000
+#define		bTxMACHeader					0xffffffff
+#define		bTxDataInit						0xff
+#define		bTxHTMode						0x100
+#define		bTxDataType					0x30000
+#define		bTxRandomSeed					0xffffffff
+#define		bCCKTxPreamble					0x1
+#define		bCCKTxSFD						0xffff0000
+#define		bCCKTxSIG						0xff
+#define		bCCKTxService					0xff00
+#define		bCCKLengthExt					0x8000
+#define		bCCKTxLength					0xffff0000
+#define		bCCKTxCRC16					0xffff
+#define		bCCKTxStatus					0x1
+#define		bOFDMTxStatus					0x2
+
+#define		IS_BB_REG_OFFSET_92S(_Offset)		((_Offset >= 0x800) && (_Offset <= 0xfff))
+
+/* 2. Page8(0x800) */
+#define		bRFMOD							0x1	/* Reg 0x800 rFPGA0_RFMOD */
+#define		bJapanMode						0x2
+#define		bCCKTxSC						0x30
+#define		bCCKEn							0x1000000
+#define		bOFDMEn						0x2000000
+
+#define		bOFDMRxADCPhase           		0x10000	/* Useless now */
+#define		bOFDMTxDACPhase		0x40000
+#define		bXATxAGC			0x3f
+
+#define		bAntennaSelect		0x0300
+
+#define		bXBTxAGC                  			0xf00	/* Reg 80c rFPGA0_TxGainStage */
+#define		bXCTxAGC			0xf000
+#define		bXDTxAGC			0xf0000
+
+#define		bPAStart                  			0xf0000000	/* Useless now */
+#define		bTRStart			0x00f00000
+#define		bRFStart			0x0000f000
+#define		bBBStart			0x000000f0
+#define		bBBCCKStart		0x0000000f
+#define		bPAEnd                    			0xf          /* Reg0x814 */
+#define		bTREnd			0x0f000000
+#define		bRFEnd			0x000f0000
+#define		bCCAMask                  			0x000000f0   /* T2R */
+#define		bR2RCCAMask		0x00000f00
+#define		bHSSI_R2TDelay		0xf8000000
+#define		bHSSI_T2RDelay		0xf80000
+#define		bContTxHSSI               		0x400     /* chane gain at continue Tx */
+#define		bIGFromCCK		0x200
+#define		bAGCAddress		0x3f
+#define		bRxHPTx			0x7000
+#define		bRxHPT2R			0x38000
+#define		bRxHPCCKIni		0xc0000
+#define		bAGCTxCode		0xc00000
+#define		bAGCRxCode		0x300000
+
+#define		b3WireDataLength          		0x800	/* Reg 0x820~84f rFPGA0_XA_HSSIParameter1 */
+#define		b3WireAddressLength		0x400
+
+#define		b3WireRFPowerDown         		0x1	/* Useless now
+ * #define bHWSISelect		0x8 */
+#define		b5GPAPEPolarity		0x40000000
+#define		b2GPAPEPolarity		0x80000000
+#define		bRFSW_TxDefaultAnt		0x3
+#define		bRFSW_TxOptionAnt		0x30
+#define		bRFSW_RxDefaultAnt		0x300
+#define		bRFSW_RxOptionAnt		0x3000
+#define		bRFSI_3WireData		0x1
+#define		bRFSI_3WireClock		0x2
+#define		bRFSI_3WireLoad		0x4
+#define		bRFSI_3WireRW		0x8
+#define		bRFSI_3Wire			0xf
+
+#define		bRFSI_RFENV               		0x10	/* Reg 0x870 rFPGA0_XAB_RFInterfaceSW */
+
+#define		bRFSI_TRSW                		0x20	/* Useless now */
+#define		bRFSI_TRSWB		0x40
+#define		bRFSI_ANTSW		0x100
+#define		bRFSI_ANTSWB		0x200
+#define		bRFSI_PAPE			0x400
+#define		bRFSI_PAPE5G		0x800
+#define		bBandSelect			0x1
+#define		bHTSIG2_GI			0x80
+#define		bHTSIG2_Smoothing		0x01
+#define		bHTSIG2_Sounding		0x02
+#define		bHTSIG2_Aggreaton		0x08
+#define		bHTSIG2_STBC		0x30
+#define		bHTSIG2_AdvCoding		0x40
+#define		bHTSIG2_NumOfHTLTF	0x300
+#define		bHTSIG2_CRC8		0x3fc
+#define		bHTSIG1_MCS		0x7f
+#define		bHTSIG1_BandWidth		0x80
+#define		bHTSIG1_HTLength		0xffff
+#define		bLSIG_Rate			0xf
+#define		bLSIG_Reserved		0x10
+#define		bLSIG_Length		0x1fffe
+#define		bLSIG_Parity			0x20
+#define		bCCKRxPhase		0x4
+
+#define		bLSSIReadAddress          		0x7f800000   /* T65 RF */
+
+#define		bLSSIReadEdge             		0x80000000   /* LSSI "Read" edge signal */
+
+#define		bLSSIReadBackData         		0xfffff		/* T65 RF */
+
+#define		bLSSIReadOKFlag           		0x1000	/* Useless now */
+#define		bCCKSampleRate            		0x8       /* 0: 44MHz, 1:88MHz      		 */
+#define		bRegulator0Standby		0x1
+#define		bRegulatorPLLStandby		0x2
+#define		bRegulator1Standby		0x4
+#define		bPLLPowerUp		0x8
+#define		bDPLLPowerUp		0x10
+#define		bDA10PowerUp		0x20
+#define		bAD7PowerUp		0x200
+#define		bDA6PowerUp		0x2000
+#define		bXtalPowerUp		0x4000
+#define		b40MDClkPowerUP		0x8000
+#define		bDA6DebugMode		0x20000
+#define		bDA6Swing			0x380000
+
+#define		bADClkPhase               		0x4000000	/* Reg 0x880 rFPGA0_AnalogParameter1 20/40 CCK support switch 40/80 BB MHZ */
+
+#define		b80MClkDelay              		0x18000000	/* Useless */
+#define		bAFEWatchDogEnable		0x20000000
+
+#define		bXtalCap01                			0xc0000000	/* Reg 0x884 rFPGA0_AnalogParameter2 Crystal cap */
+#define		bXtalCap23			0x3
+#define		bXtalCap92x					0x0f000000
+#define		bXtalCap			0x0f000000
+
+#define		bIntDifClkEnable          		0x400	/* Useless */
+#define		bExtSigClkEnable		0x800
+#define		bBandgapMbiasPowerUp	0x10000
+#define		bAD11SHGain		0xc0000
+#define		bAD11InputRange		0x700000
+#define		bAD11OPCurrent		0x3800000
+#define		bIPathLoopback		0x4000000
+#define		bQPathLoopback		0x8000000
+#define		bAFELoopback		0x10000000
+#define		bDA10Swing		0x7e0
+#define		bDA10Reverse		0x800
+#define		bDAClkSource		0x1000
+#define		bAD7InputRange		0x6000
+#define		bAD7Gain			0x38000
+#define		bAD7OutputCMMode		0x40000
+#define		bAD7InputCMMode		0x380000
+#define		bAD7Current			0xc00000
+#define		bRegulatorAdjust		0x7000000
+#define		bAD11PowerUpAtTx		0x1
+#define		bDA10PSAtTx		0x10
+#define		bAD11PowerUpAtRx		0x100
+#define		bDA10PSAtRx		0x1000
+#define		bCCKRxAGCFormat		0x200
+#define		bPSDFFTSamplepPoint		0xc000
+#define		bPSDAverageNum		0x3000
+#define		bIQPathControl		0xc00
+#define		bPSDFreq			0x3ff
+#define		bPSDAntennaPath		0x30
+#define		bPSDIQSwitch		0x40
+#define		bPSDRxTrigger		0x400000
+#define		bPSDTxTrigger		0x80000000
+#define		bPSDSineToneScale		0x7f000000
+#define		bPSDReport			0xffff
+
+/* 3. Page9(0x900) */
+#define		bOFDMTxSC                 		0x30000000	/* Useless */
+#define		bCCKTxOn			0x1
+#define		bOFDMTxOn		0x2
+#define		bDebugPage                		0xfff  /* reset debug page and also HWord, LWord */
+#define		bDebugItem                		0xff   /* reset debug page and LWord */
+#define		bAntL			0x10
+#define		bAntNonHT				0x100
+#define		bAntHT1			0x1000
+#define		bAntHT2			0x10000
+#define		bAntHT1S1			0x100000
+#define		bAntNonHTS1		0x1000000
+
+/* 4. PageA(0xA00) */
+#define		bCCKBBMode				0x3	/* Useless */
+#define		bCCKTxPowerSaving		0x80
+#define		bCCKRxPowerSaving		0x40
+
+#define		bCCKSideBand			0x10	/* Reg 0xa00 rCCK0_System 20/40 switch */
+
+#define		bCCKScramble			0x8	/* Useless */
+#define		bCCKAntDiversity		0x8000
+#define		bCCKCarrierRecovery		0x4000
+#define		bCCKTxRate				0x3000
+#define		bCCKDCCancel			0x0800
+#define		bCCKISICancel			0x0400
+#define		bCCKMatchFilter			0x0200
+#define		bCCKEqualizer			0x0100
+#define		bCCKPreambleDetect		0x800000
+#define		bCCKFastFalseCCA		0x400000
+#define		bCCKChEstStart			0x300000
+#define		bCCKCCACount			0x080000
+#define		bCCKcs_lim				0x070000
+#define		bCCKBistMode			0x80000000
+#define		bCCKCCAMask			0x40000000
+#define		bCCKTxDACPhase		0x4
+#define		bCCKRxADCPhase		0x20000000   /* r_rx_clk */
+#define		bCCKr_cp_mode0		0x0100
+#define		bCCKTxDCOffset			0xf0
+#define		bCCKRxDCOffset			0xf
+#define		bCCKCCAMode			0xc000
+#define		bCCKFalseCS_lim			0x3f00
+#define		bCCKCS_ratio			0xc00000
+#define		bCCKCorgBit_sel			0x300000
+#define		bCCKPD_lim				0x0f0000
+#define		bCCKNewCCA			0x80000000
+#define		bCCKRxHPofIG			0x8000
+#define		bCCKRxIG				0x7f00
+#define		bCCKLNAPolarity			0x800000
+#define		bCCKRx1stGain			0x7f0000
+#define		bCCKRFExtend			0x20000000 /* CCK Rx Iinital gain polarity */
+#define		bCCKRxAGCSatLevel		0x1f000000
+#define		bCCKRxAGCSatCount		0xe0
+#define		bCCKRxRFSettle			0x1f       /* AGCsamp_dly */
+#define		bCCKFixedRxAGC			0x8000
+/* #define bCCKRxAGCFormat		0x4000 */   /* remove to HSSI register 0x824 */
+#define		bCCKAntennaPolarity		0x2000
+#define		bCCKTxFilterType		0x0c00
+#define		bCCKRxAGCReportType	0x0300
+#define		bCCKRxDAGCEn			0x80000000
+#define		bCCKRxDAGCPeriod		0x20000000
+#define		bCCKRxDAGCSatLevel		0x1f000000
+#define		bCCKTimingRecovery		0x800000
+#define		bCCKTxC0				0x3f0000
+#define		bCCKTxC1				0x3f000000
+#define		bCCKTxC2				0x3f
+#define		bCCKTxC3				0x3f00
+#define		bCCKTxC4				0x3f0000
+#define		bCCKTxC5				0x3f000000
+#define		bCCKTxC6				0x3f
+#define		bCCKTxC7				0x3f00
+#define		bCCKDebugPort			0xff0000
+#define		bCCKDACDebug			0x0f000000
+#define		bCCKFalseAlarmEnable	0x8000
+#define		bCCKFalseAlarmRead		0x4000
+#define		bCCKTRSSI				0x7f
+#define		bCCKRxAGCReport		0xfe
+#define		bCCKRxReport_AntSel	0x80000000
+#define		bCCKRxReport_MFOff		0x40000000
+#define		bCCKRxRxReport_SQLoss	0x20000000
+#define		bCCKRxReport_Pktloss	0x10000000
+#define		bCCKRxReport_Lockedbit	0x08000000
+#define		bCCKRxReport_RateError	0x04000000
+#define		bCCKRxReport_RxRate	0x03000000
+#define		bCCKRxFACounterLower	0xff
+#define		bCCKRxFACounterUpper	0xff000000
+#define		bCCKRxHPAGCStart		0xe000
+#define		bCCKRxHPAGCFinal		0x1c00
+#define		bCCKRxFalseAlarmEnable	0x8000
+#define		bCCKFACounterFreeze	0x4000
+#define		bCCKTxPathSel			0x10000000
+#define		bCCKDefaultRxPath		0xc000000
+#define		bCCKOptionRxPath		0x3000000
+
+/* 5. PageC(0xC00) */
+#define		bNumOfSTF				0x3	/* Useless */
+#define		bShift_L					0xc0
+#define		bGI_TH					0xc
+#define		bRxPathA				0x1
+#define		bRxPathB				0x2
+#define		bRxPathC				0x4
+#define		bRxPathD				0x8
+#define		bTxPathA				0x1
+#define		bTxPathB				0x2
+#define		bTxPathC				0x4
+#define		bTxPathD				0x8
+#define		bTRSSIFreq				0x200
+#define		bADCBackoff				0x3000
+#define		bDFIRBackoff			0xc000
+#define		bTRSSILatchPhase		0x10000
+#define		bRxIDCOffset			0xff
+#define		bRxQDCOffset			0xff00
+#define		bRxDFIRMode			0x1800000
+#define		bRxDCNFType			0xe000000
+#define		bRXIQImb_A				0x3ff
+#define		bRXIQImb_B				0xfc00
+#define		bRXIQImb_C				0x3f0000
+#define		bRXIQImb_D				0xffc00000
+#define		bDC_dc_Notch			0x60000
+#define		bRxNBINotch			0x1f000000
+#define		bPD_TH					0xf
+#define		bPD_TH_Opt2			0xc000
+#define		bPWED_TH				0x700
+#define		bIfMF_Win_L			0x800
+#define		bPD_Option				0x1000
+#define		bMF_Win_L				0xe000
+#define		bBW_Search_L			0x30000
+#define		bwin_enh_L				0xc0000
+#define		bBW_TH					0x700000
+#define		bED_TH2				0x3800000
+#define		bBW_option				0x4000000
+#define		bRatio_TH				0x18000000
+#define		bWindow_L				0xe0000000
+#define		bSBD_Option				0x1
+#define		bFrame_TH				0x1c
+#define		bFS_Option				0x60
+#define		bDC_Slope_check		0x80
+#define		bFGuard_Counter_DC_L	0xe00
+#define		bFrame_Weight_Short	0x7000
+#define		bSub_Tune				0xe00000
+#define		bFrame_DC_Length		0xe000000
+#define		bSBD_start_offset		0x30000000
+#define		bFrame_TH_2			0x7
+#define		bFrame_GI2_TH			0x38
+#define		bGI2_Sync_en			0x40
+#define		bSarch_Short_Early		0x300
+#define		bSarch_Short_Late		0xc00
+#define		bSarch_GI2_Late		0x70000
+#define		bCFOAntSum				0x1
+#define		bCFOAcc				0x2
+#define		bCFOStartOffset			0xc
+#define		bCFOLookBack			0x70
+#define		bCFOSumWeight			0x80
+#define		bDAGCEnable			0x10000
+#define		bTXIQImb_A				0x3ff
+#define		bTXIQImb_B				0xfc00
+#define		bTXIQImb_C				0x3f0000
+#define		bTXIQImb_D				0xffc00000
+#define		bTxIDCOffset			0xff
+#define		bTxQDCOffset			0xff00
+#define		bTxDFIRMode			0x10000
+#define		bTxPesudoNoiseOn		0x4000000
+#define		bTxPesudoNoise_A		0xff
+#define		bTxPesudoNoise_B		0xff00
+#define		bTxPesudoNoise_C		0xff0000
+#define		bTxPesudoNoise_D		0xff000000
+#define		bCCADropOption			0x20000
+#define		bCCADropThres			0xfff00000
+#define		bEDCCA_H				0xf
+#define		bEDCCA_L				0xf0
+#define		bLambda_ED			0x300
+#define		bRxInitialGain			0x7f
+#define		bRxAntDivEn				0x80
+#define		bRxAGCAddressForLNA	0x7f00
+#define		bRxHighPowerFlow		0x8000
+#define		bRxAGCFreezeThres		0xc0000
+#define		bRxFreezeStep_AGC1	0x300000
+#define		bRxFreezeStep_AGC2	0xc00000
+#define		bRxFreezeStep_AGC3	0x3000000
+#define		bRxFreezeStep_AGC0	0xc000000
+#define		bRxRssi_Cmp_En			0x10000000
+#define		bRxQuickAGCEn			0x20000000
+#define		bRxAGCFreezeThresMode	0x40000000
+#define		bRxOverFlowCheckType	0x80000000
+#define		bRxAGCShift				0x7f
+#define		bTRSW_Tri_Only			0x80
+#define		bPowerThres			0x300
+#define		bRxAGCEn				0x1
+#define		bRxAGCTogetherEn		0x2
+#define		bRxAGCMin				0x4
+#define		bRxHP_Ini				0x7
+#define		bRxHP_TRLNA			0x70
+#define		bRxHP_RSSI				0x700
+#define		bRxHP_BBP1				0x7000
+#define		bRxHP_BBP2				0x70000
+#define		bRxHP_BBP3				0x700000
+#define		bRSSI_H					0x7f0000     /* the threshold for high power */
+#define		bRSSI_Gen				0x7f000000   /* the threshold for ant diversity */
+#define		bRxSettle_TRSW			0x7
+#define		bRxSettle_LNA			0x38
+#define		bRxSettle_RSSI			0x1c0
+#define		bRxSettle_BBP			0xe00
+#define		bRxSettle_RxHP			0x7000
+#define		bRxSettle_AntSW_RSSI	0x38000
+#define		bRxSettle_AntSW		0xc0000
+#define		bRxProcessTime_DAGC	0x300000
+#define		bRxSettle_HSSI			0x400000
+#define		bRxProcessTime_BBPPW	0x800000
+#define		bRxAntennaPowerShift	0x3000000
+#define		bRSSITableSelect		0xc000000
+#define		bRxHP_Final				0x7000000
+#define		bRxHTSettle_BBP			0x7
+#define		bRxHTSettle_HSSI		0x8
+#define		bRxHTSettle_RxHP		0x70
+#define		bRxHTSettle_BBPPW		0x80
+#define		bRxHTSettle_Idle		0x300
+#define		bRxHTSettle_Reserved	0x1c00
+#define		bRxHTRxHPEn			0x8000
+#define		bRxHTAGCFreezeThres	0x30000
+#define		bRxHTAGCTogetherEn	0x40000
+#define		bRxHTAGCMin			0x80000
+#define		bRxHTAGCEn				0x100000
+#define		bRxHTDAGCEn			0x200000
+#define		bRxHTRxHP_BBP			0x1c00000
+#define		bRxHTRxHP_Final		0xe0000000
+#define		bRxPWRatioTH			0x3
+#define		bRxPWRatioEn			0x4
+#define		bRxMFHold				0x3800
+#define		bRxPD_Delay_TH1		0x38
+#define		bRxPD_Delay_TH2		0x1c0
+#define		bRxPD_DC_COUNT_MAX	0x600
+/* #define bRxMF_Hold               0x3800 */
+#define		bRxPD_Delay_TH			0x8000
+#define		bRxProcess_Delay		0xf0000
+#define		bRxSearchrange_GI2_Early	0x700000
+#define		bRxFrame_Guard_Counter_L	0x3800000
+#define		bRxSGI_Guard_L			0xc000000
+#define		bRxSGI_Search_L		0x30000000
+#define		bRxSGI_TH				0xc0000000
+#define		bDFSCnt0				0xff
+#define		bDFSCnt1				0xff00
+#define		bDFSFlag				0xf0000
+#define		bMFWeightSum			0x300000
+#define		bMinIdxTH				0x7f000000
+#define		bDAFormat				0x40000
+#define		bTxChEmuEnable		0x01000000
+#define		bTRSWIsolation_A		0x7f
+#define		bTRSWIsolation_B		0x7f00
+#define		bTRSWIsolation_C		0x7f0000
+#define		bTRSWIsolation_D		0x7f000000
+#define		bExtLNAGain				0x7c00
+
+/* 6. PageE(0xE00) */
+#define		bSTBCEn				0x4	/* Useless */
+#define		bAntennaMapping		0x10
+#define		bNss					0x20
+#define		bCFOAntSumD			0x200
+#define		bPHYCounterReset		0x8000000
+#define		bCFOReportGet			0x4000000
+#define		bOFDMContinueTx		0x10000000
+#define		bOFDMSingleCarrier		0x20000000
+#define		bOFDMSingleTone		0x40000000
+/* #define bRxPath1                 0x01 */
+/* #define bRxPath2                 0x02 */
+/* #define bRxPath3                 0x04 */
+/* #define bRxPath4                 0x08 */
+/* #define bTxPath1                 0x10 */
+/* #define bTxPath2                 0x20 */
+#define		bHTDetect			0x100
+#define		bCFOEn				0x10000
+#define		bCFOValue			0xfff00000
+#define		bSigTone_Re		0x3f
+#define		bSigTone_Im		0x7f00
+#define		bCounter_CCA		0xffff
+#define		bCounter_ParityFail	0xffff0000
+#define		bCounter_RateIllegal		0xffff
+#define		bCounter_CRC8Fail	0xffff0000
+#define		bCounter_MCSNoSupport	0xffff
+#define		bCounter_FastSync	0xffff
+#define		bShortCFO			0xfff
+#define		bShortCFOTLength	12   /* total */
+#define		bShortCFOFLength	11   /* fraction */
+#define		bLongCFO			0x7ff
+#define		bLongCFOTLength	11
+#define		bLongCFOFLength	11
+#define		bTailCFO			0x1fff
+#define		bTailCFOTLength		13
+#define		bTailCFOFLength		12
+#define		bmax_en_pwdB		0xffff
+#define		bCC_power_dB		0xffff0000
+#define		bnoise_pwdB		0xffff
+#define		bPowerMeasTLength	10
+#define		bPowerMeasFLength	3
+#define		bRx_HT_BW			0x1
+#define		bRxSC				0x6
+#define		bRx_HT				0x8
+#define		bNB_intf_det_on		0x1
+#define		bIntf_win_len_cfg	0x30
+#define		bNB_Intf_TH_cfg		0x1c0
+#define		bRFGain				0x3f
+#define		bTableSel			0x40
+#define		bTRSW				0x80
+#define		bRxSNR_A			0xff
+#define		bRxSNR_B			0xff00
+#define		bRxSNR_C			0xff0000
+#define		bRxSNR_D			0xff000000
+#define		bSNREVMTLength		8
+#define		bSNREVMFLength		1
+#define		bCSI1st				0xff
+#define		bCSI2nd				0xff00
+#define		bRxEVM1st			0xff0000
+#define		bRxEVM2nd			0xff000000
+#define		bSIGEVM			0xff
+#define		bPWDB				0xff00
+#define		bSGIEN				0x10000
+
+#define		bSFactorQAM1		0xf	/* Useless */
+#define		bSFactorQAM2		0xf0
+#define		bSFactorQAM3		0xf00
+#define		bSFactorQAM4		0xf000
+#define		bSFactorQAM5		0xf0000
+#define		bSFactorQAM6		0xf0000
+#define		bSFactorQAM7		0xf00000
+#define		bSFactorQAM8		0xf000000
+#define		bSFactorQAM9		0xf0000000
+#define		bCSIScheme			0x100000
+
+#define		bNoiseLvlTopSet		0x3	/* Useless */
+#define		bChSmooth			0x4
+#define		bChSmoothCfg1		0x38
+#define		bChSmoothCfg2		0x1c0
+#define		bChSmoothCfg3		0xe00
+#define		bChSmoothCfg4		0x7000
+#define		bMRCMode			0x800000
+#define		bTHEVMCfg			0x7000000
+
+#define		bLoopFitType		0x1	/* Useless */
+#define		bUpdCFO			0x40
+#define		bUpdCFOOffData		0x80
+#define		bAdvUpdCFO			0x100
+#define		bAdvTimeCtrl		0x800
+#define		bUpdClko			0x1000
+#define		bFC					0x6000
+#define		bTrackingMode		0x8000
+#define		bPhCmpEnable		0x10000
+#define		bUpdClkoLTF		0x20000
+#define		bComChCFO			0x40000
+#define		bCSIEstiMode		0x80000
+#define		bAdvUpdEqz			0x100000
+#define		bUChCfg				0x7000000
+#define		bUpdEqz			0x8000000
+
+/* Rx Pseduo noise */
+#define		bRxPesudoNoiseOn		0x20000000	/* Useless */
+#define		bRxPesudoNoise_A		0xff
+#define		bRxPesudoNoise_B		0xff00
+#define		bRxPesudoNoise_C		0xff0000
+#define		bRxPesudoNoise_D		0xff000000
+#define		bPesudoNoiseState_A	0xffff
+#define		bPesudoNoiseState_B	0xffff0000
+#define		bPesudoNoiseState_C	0xffff
+#define		bPesudoNoiseState_D	0xffff0000
+
+/* 7. RF Register
+ * Zebra1 */
+#define		bZebra1_HSSIEnable		0x8		/* Useless */
+#define		bZebra1_TRxControl		0xc00
+#define		bZebra1_TRxGainSetting	0x07f
+#define		bZebra1_RxCorner		0xc00
+#define		bZebra1_TxChargePump	0x38
+#define		bZebra1_RxChargePump	0x7
+#define		bZebra1_ChannelNum	0xf80
+#define		bZebra1_TxLPFBW		0x400
+#define		bZebra1_RxLPFBW		0x600
+
+/* Zebra4 */
+#define		bRTL8256RegModeCtrl1	0x100	/* Useless */
+#define		bRTL8256RegModeCtrl0	0x40
+#define		bRTL8256_TxLPFBW		0x18
+#define		bRTL8256_RxLPFBW		0x600
+
+/* RTL8258 */
+#define		bRTL8258_TxLPFBW		0xc	/* Useless */
+#define		bRTL8258_RxLPFBW		0xc00
+#define		bRTL8258_RSSILPFBW	0xc0
+
+
+/*
+ * Other Definition
+ *   */
+
+/* byte endable for sb_write */
+#define		bByte0				0x1	/* Useless */
+#define		bByte1				0x2
+#define		bByte2				0x4
+#define		bByte3				0x8
+#define		bWord0				0x3
+#define		bWord1				0xc
+#define		bDWord				0xf
+
+/* for PutRegsetting & GetRegSetting BitMask */
+#define		bMaskByte0			0xff	/* Reg 0xc50 rOFDM0_XAAGCCore~0xC6f */
+#define		bMaskByte1			0xff00
+#define		bMaskByte2			0xff0000
+#define		bMaskByte3			0xff000000
+#define		bMaskHWord		0xffff0000
+#define		bMaskLWord			0x0000ffff
+#define		bMaskDWord		0xffffffff
+#define		bMaskH3Bytes		0xffffff00
+#define		bMask12Bits			0xfff
+#define		bMaskH4Bits			0xf0000000
+#define		bMaskOFDM_D		0xffc00000
+#define		bMaskCCK			0x3f3f3f3f
+
+
+#define		bEnable			0x1	/* Useless */
+#define		bDisable		0x0
+
+#define		LeftAntenna		0x0	/* Useless */
+#define		RightAntenna	0x1
+
+#define		tCheckTxStatus		500   /* 500ms */ /* Useless */
+#define		tUpdateRxCounter	100   /* 100ms */
+
+#define		rateCCK		0	/* Useless */
+#define		rateOFDM	1
+#define		rateHT		2
+
+/* define Register-End */
+#define		bPMAC_End			0x1ff	/* Useless */
+#define		bFPGAPHY0_End		0x8ff
+#define		bFPGAPHY1_End		0x9ff
+#define		bCCKPHY0_End		0xaff
+#define		bOFDMPHY0_End		0xcff
+#define		bOFDMPHY1_End		0xdff
+
+/* define max debug item in each debug page
+ * #define bMaxItem_FPGA_PHY0        0x9
+ * #define bMaxItem_FPGA_PHY1        0x3
+ * #define bMaxItem_PHY_11B          0x16
+ * #define bMaxItem_OFDM_PHY0        0x29
+ * #define bMaxItem_OFDM_PHY1        0x0 */
+
+#define		bPMACControl		0x0		/* Useless */
+#define		bWMACControl		0x1
+#define		bWNICControl		0x2
+
+#define		PathA			0x0	/* Useless */
+#define		PathB			0x1
+#define		PathC			0x2
+#define		PathD			0x3
+
+#endif
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/include/Hal8723BPwrSeq.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/Hal8723BPwrSeq.h
--- linux-5.6.3/3rdparty/rtl8821ce/include/Hal8723BPwrSeq.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/Hal8723BPwrSeq.h	2020-04-10 16:35:06.845661421 +0300
@@ -0,0 +1,246 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2016 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#ifndef REALTEK_POWER_SEQUENCE_8723B
+#define REALTEK_POWER_SEQUENCE_8723B
+
+#include "HalPwrSeqCmd.h"
+
+/*
+	Check document WM-20130815-JackieLau-RTL8723B_Power_Architecture v08.vsd
+	There are 6 HW Power States:
+	0: POFF--Power Off
+	1: PDN--Power Down
+	2: CARDEMU--Card Emulation
+	3: ACT--Active Mode
+	4: LPS--Low Power State
+	5: SUS--Suspend
+
+	The transision from different states are defined below
+	TRANS_CARDEMU_TO_ACT
+	TRANS_ACT_TO_CARDEMU
+	TRANS_CARDEMU_TO_SUS
+	TRANS_SUS_TO_CARDEMU
+	TRANS_CARDEMU_TO_PDN
+	TRANS_ACT_TO_LPS
+	TRANS_LPS_TO_ACT
+
+	TRANS_END
+*/
+#define	RTL8723B_TRANS_CARDEMU_TO_ACT_STEPS	26
+#define	RTL8723B_TRANS_ACT_TO_CARDEMU_STEPS	15
+#define	RTL8723B_TRANS_CARDEMU_TO_SUS_STEPS	15
+#define	RTL8723B_TRANS_SUS_TO_CARDEMU_STEPS	15
+#define	RTL8723B_TRANS_CARDEMU_TO_PDN_STEPS	15
+#define	RTL8723B_TRANS_PDN_TO_CARDEMU_STEPS	15
+#define	RTL8723B_TRANS_ACT_TO_LPS_STEPS		15
+#define	RTL8723B_TRANS_LPS_TO_ACT_STEPS		15
+#define	RTL8723B_TRANS_ACT_TO_SWLPS_STEPS		22
+#define	RTL8723B_TRANS_SWLPS_TO_ACT_STEPS		15
+#define	RTL8723B_TRANS_END_STEPS		1
+
+
+#define RTL8723B_TRANS_CARDEMU_TO_ACT														\
+	/* format */																\
+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
+	{0x0020, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0}, /*0x20[0] = 1b'1 enable LDOA12 MACRO block for all interface*/   \
+	{0x0067, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0}, /*0x67[0] = 0 to disable BT_GPS_SEL pins*/	\
+	{0x0001, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_DELAY, 1, PWRSEQ_DELAY_MS},/*Delay 1ms*/   \
+	{0x0000, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT5, 0}, /*0x00[5] = 1b'0 release analog Ips to digital ,1:isolation*/   \
+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, (BIT4 | BIT3 | BIT2), 0},/* disable SW LPS 0x04[10]=0 and WLSUS_EN 0x04[11]=0*/	\
+	{0x0075, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0 , BIT0},/* Disable USB suspend */	\
+	{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT1, BIT1},/* wait till 0x04[17] = 1    power ready*/	\
+	{0x0075, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0 , 0},/* Enable USB suspend */	\
+	{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0},/* release WLON reset  0x04[16]=1*/	\
+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, 0},/* disable HWPDN 0x04[15]=0*/	\
+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, (BIT4 | BIT3), 0},/* disable WL suspend*/	\
+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0},/* polling until return 0*/	\
+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT0, 0},/**/	\
+	{0x0010, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT6, BIT6},/* Enable WL control XTAL setting*/	\
+	{0x0049, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1},/*Enable falling edge triggering interrupt*/\
+	{0x0063, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1},/*Enable GPIO9 interrupt mode*/\
+	{0x0062, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0},/*Enable GPIO9 input mode*/\
+	{0x0058, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0},/*Enable HSISR GPIO[C:0] interrupt*/\
+	{0x005A, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1},/*Enable HSISR GPIO9 interrupt*/\
+	{0x0068, PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3, BIT3},/*For GPIO9 internal pull high setting by test chip*/\
+	{0x0069, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT6, BIT6},/*For GPIO9 internal pull high setting*/\
+
+
+#define RTL8723B_TRANS_ACT_TO_CARDEMU													\
+	/* format */																\
+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
+	{0x001F, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0},/*0x1F[7:0] = 0 turn off RF*/	\
+	{0x0049, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0},/*Enable rising edge triggering interrupt*/ \
+	{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0},/* release WLON reset  0x04[16]=1*/	\
+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1}, /*0x04[9] = 1 turn off MAC by HW state machine*/	\
+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT1, 0}, /*wait till 0x04[9] = 0 polling until return 0 to disable*/	\
+	{0x0010, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT6, 0},/* Enable BT control XTAL setting*/\
+	{0x0000, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT5, BIT5}, /*0x00[5] = 1b'1 analog Ips to digital ,1:isolation*/   \
+	{0x0020, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0}, /*0x20[0] = 1b'0 disable LDOA12 MACRO block*/\
+
+
+#define RTL8723B_TRANS_CARDEMU_TO_SUS													\
+	/* format */																\
+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4 | BIT3, (BIT4 | BIT3)}, /*0x04[12:11] = 2b'11 enable WL suspend for PCIe*/	\
+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT4, BIT3}, /*0x04[12:11] = 2b'01 enable WL suspend*/	\
+	{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, BIT4}, /*0x23[4] = 1b'1 12H LDO enter sleep mode*/   \
+	{0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x20}, /*0x07[7:0] = 0x20 SDIO SOP option to disable BG/MB/ACK/SWR*/   \
+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT4, BIT3 | BIT4}, /*0x04[12:11] = 2b'11 enable WL suspend for PCIe*/	\
+	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT0, BIT0}, /*Set SDIO suspend local register*/	\
+	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, 0}, /*wait power state to suspend*/
+
+#define RTL8723B_TRANS_SUS_TO_CARDEMU													\
+	/* format */																\
+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT7, 0}, /*clear suspend enable and power down enable*/	\
+	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT0, 0}, /*Set SDIO suspend local register*/	\
+	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, BIT1}, /*wait power state to suspend*/\
+	{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0}, /*0x23[4] = 1b'0 12H LDO enter normal mode*/   \
+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT4, 0}, /*0x04[12:11] = 2b'01enable WL suspend*/
+
+#define RTL8723B_TRANS_CARDEMU_TO_CARDDIS													\
+	/* format */																\
+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
+	{0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x20}, /*0x07 = 0x20 , SOP option to disable BG/MB*/	\
+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT4, BIT3}, /*0x04[12:11] = 2b'01 enable WL suspend*/	\
+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, BIT2}, /*0x04[10] = 1, enable SW LPS*/	\
+	{0x004A, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 1}, /*0x48[16] = 1 to enable GPIO9 as EXT WAKEUP*/   \
+	{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, BIT4}, /*0x23[4] = 1b'1 12H LDO enter sleep mode*/   \
+	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT0, BIT0}, /*Set SDIO suspend local register*/	\
+	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, 0}, /*wait power state to suspend*/
+
+#define RTL8723B_TRANS_CARDDIS_TO_CARDEMU													\
+	/* format */																\
+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT7, 0}, /*clear suspend enable and power down enable*/	\
+	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT0, 0}, /*Set SDIO suspend local register*/	\
+	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, BIT1}, /*wait power state to suspend*/\
+	{0x004A, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0}, /*0x48[16] = 0 to disable GPIO9 as EXT WAKEUP*/   \
+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT4, 0}, /*0x04[12:11] = 2b'01enable WL suspend*/\
+	{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0}, /*0x23[4] = 1b'0 12H LDO enter normal mode*/   \
+	{0x0301, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0},/*PCIe DMA start*/
+
+
+#define RTL8723B_TRANS_CARDEMU_TO_PDN												\
+	/* format */																\
+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
+	{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, BIT4}, /*0x23[4] = 1b'1 12H LDO enter sleep mode*/   \
+	{0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK | PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x20}, /*0x07[7:0] = 0x20 SOP option to disable BG/MB/ACK/SWR*/   \
+	{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0},/* 0x04[16] = 0*/\
+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, BIT7},/* 0x04[15] = 1*/
+
+#define RTL8723B_TRANS_PDN_TO_CARDEMU												\
+	/* format */																\
+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, 0},/* 0x04[15] = 0*/
+
+#define RTL8723B_TRANS_ACT_TO_LPS														\
+	/* format */																\
+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
+	{0x0301, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF},/*PCIe DMA stop*/	\
+	{0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF},/*Tx Pause*/	\
+	{0x05F8, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/	\
+	{0x05F9, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/	\
+	{0x05FA, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/	\
+	{0x05FB, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/	\
+	{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0},/*CCK and OFDM are disabled, and clock are gated*/	\
+	{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_US},/*Delay 1us*/	\
+	{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0},/*Whole BB is reset*/	\
+	{0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x03},/*Reset MAC TRX*/	\
+	{0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0},/*check if removed later*/	\
+	{0x0093, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x00},/*When driver enter Sus/ Disable, enable LOP for BT*/	\
+	{0x0553, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT5, BIT5},/*Respond TxOK to scheduler*/	\
+
+
+#define RTL8723B_TRANS_LPS_TO_ACT															\
+	/* format */																\
+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
+	{0x0080, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, 0xFF, 0x84}, /*SDIO RPWM*/\
+	{0xFE58, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x84}, /*USB RPWM*/\
+	{0x0361, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x84}, /*PCIe RPWM*/\
+	{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_MS}, /*Delay*/\
+	{0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0}, /*.	0x08[4] = 0		 switch TSF to 40M*/\
+	{0x0109, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT7, 0}, /*Polling 0x109[7]=0  TSF in 40M*/\
+	{0x0029, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT6 | BIT7, 0}, /*.	0x29[7:6] = 2b'00	 enable BB clock*/\
+	{0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1}, /*.	0x101[1] = 1*/\
+	{0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF}, /*.	0x100[7:0] = 0xFF	 enable WMAC TRX*/\
+	{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1 | BIT0, BIT1 | BIT0}, /*.	0x02[1:0] = 2b'11	 enable BB macro*/\
+	{0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0}, /*.	0x522 = 0*/
+
+
+#define RTL8723B_TRANS_ACT_TO_SWLPS														\
+	/* format */																\
+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
+	{0x0194, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0},/*enable 32 K source*/	\
+	{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0},/*CCK and OFDM are disabled, and clock are gated*/	\
+	{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 1},/*CCK and OFDM are enable*/	\
+	{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0},/*CCK and OFDM are disabled, and clock are gated*/	\
+	{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 1},/*CCK and OFDM are enable*/	\
+	{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0},/*CCK and OFDM are disabled, and clock are gated*/	\
+	{0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x3F},/*Reset MAC TRX*/	\
+	{0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0},/*disable security engine*/	\
+	{0x0093, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x40},/*When driver enter Sus/ Disable, enable LOP for BT*/	\
+	{0x0553, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT5, BIT5},/*reset dual TSF*/	\
+	{0x0003, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, 0},/*Reset CPU*/	\
+	{0x0080, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0},/*Reset MCUFWDL register*/	\
+	{0x001D, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0},/*Reset CPU IO Wrapper*/	\
+	{0x001D, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 1},/*Reset CPU IO Wrapper*/	\
+	{0x0287, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*polling RXFF packet number = 0 */	\
+	{0x0286, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT1, BIT1},/*polling RXDMA idle */	\
+	{0x013D, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0},/*Clear FW RPWM interrupt */\
+	{0x0139, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0},/*Set FW RPWM interrupt source*/\
+	{0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, BIT4},/*switch TSF to 32K*/\
+	{0x0109, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, BIT7},/*polling TSF stable*/\
+	{0x0090, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0},/*Set FW LPS*/	\
+	{0x0090, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT0, 0},/*polling FW LPS ready */
+
+
+#define RTL8723B_TRANS_SWLPS_TO_ACT															\
+	/* format */																\
+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
+	{0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0},/*switch TSF to 32K*/\
+	{0x0109, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, 0},/*polling TSF stable*/\
+	{0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1}, /*.	0x101[1] = 1, enable security engine*/\
+	{0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF}, /*.	0x100[7:0] = 0xFF	 enable WMAC TRX*/\
+	{0x06B7, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x09}, /*.	reset MAC rx state machine*/\
+	{0x06B4, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x86}, /*.	reset MAC rx state machine*/\
+	{0x0080, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1},/* set CPU RAM code ready*/	\
+	{0x001D, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0},/*Reset CPU IO Wrapper*/	\
+	{0x0003, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, 0},/* Enable CPU*/	\
+	{0x001D, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0},/*enable CPU IO Wrapper*/	\
+	{0x0003, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, BIT2},/* Enable CPU*/	\
+	{0x0080, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT7, BIT7},/*polling FW init ready */	\
+	{0x0080, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT6, BIT6},/*polling FW init ready */	\
+	{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0}, /*.	0x02[1:0] = 2b'11	 enable BB macro*/\
+	{0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0}, /*.	0x522 = 0*/
+
+#define RTL8723B_TRANS_END															\
+	/* format */																\
+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
+	{0xFFFF, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, 0, PWR_CMD_END, 0, 0},
+
+
+	extern WLAN_PWR_CFG rtl8723B_power_on_flow[RTL8723B_TRANS_CARDEMU_TO_ACT_STEPS + RTL8723B_TRANS_END_STEPS];
+	extern WLAN_PWR_CFG rtl8723B_radio_off_flow[RTL8723B_TRANS_ACT_TO_CARDEMU_STEPS + RTL8723B_TRANS_END_STEPS];
+	extern WLAN_PWR_CFG rtl8723B_card_disable_flow[RTL8723B_TRANS_ACT_TO_CARDEMU_STEPS + RTL8723B_TRANS_CARDEMU_TO_PDN_STEPS + RTL8723B_TRANS_END_STEPS];
+	extern WLAN_PWR_CFG rtl8723B_card_enable_flow[RTL8723B_TRANS_ACT_TO_CARDEMU_STEPS + RTL8723B_TRANS_CARDEMU_TO_PDN_STEPS + RTL8723B_TRANS_END_STEPS];
+	extern WLAN_PWR_CFG rtl8723B_suspend_flow[RTL8723B_TRANS_ACT_TO_CARDEMU_STEPS + RTL8723B_TRANS_CARDEMU_TO_SUS_STEPS + RTL8723B_TRANS_END_STEPS];
+	extern WLAN_PWR_CFG rtl8723B_resume_flow[RTL8723B_TRANS_ACT_TO_CARDEMU_STEPS + RTL8723B_TRANS_CARDEMU_TO_SUS_STEPS + RTL8723B_TRANS_END_STEPS];
+	extern WLAN_PWR_CFG rtl8723B_hwpdn_flow[RTL8723B_TRANS_ACT_TO_CARDEMU_STEPS + RTL8723B_TRANS_CARDEMU_TO_PDN_STEPS + RTL8723B_TRANS_END_STEPS];
+	extern WLAN_PWR_CFG rtl8723B_enter_lps_flow[RTL8723B_TRANS_ACT_TO_LPS_STEPS + RTL8723B_TRANS_END_STEPS];
+	extern WLAN_PWR_CFG rtl8723B_leave_lps_flow[RTL8723B_TRANS_LPS_TO_ACT_STEPS + RTL8723B_TRANS_END_STEPS];
+	extern WLAN_PWR_CFG rtl8723B_enter_swlps_flow[RTL8723B_TRANS_ACT_TO_SWLPS_STEPS + RTL8723B_TRANS_END_STEPS];
+	extern WLAN_PWR_CFG rtl8723B_leave_swlps_flow[RTL8723B_TRANS_SWLPS_TO_ACT_STEPS + RTL8723B_TRANS_END_STEPS];
+#endif
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/include/Hal8723DPhyCfg.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/Hal8723DPhyCfg.h
--- linux-5.6.3/3rdparty/rtl8821ce/include/Hal8723DPhyCfg.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/Hal8723DPhyCfg.h	2020-04-10 16:35:06.845661421 +0300
@@ -0,0 +1,131 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#ifndef __INC_HAL8723DPHYCFG_H__
+#define __INC_HAL8723DPHYCFG_H__
+
+/*--------------------------Define Parameters-------------------------------*/
+#define LOOP_LIMIT				5
+#define MAX_STALL_TIME			50		/* us */
+#define AntennaDiversityValue	0x80	/* (Adapter->bSoftwareAntennaDiversity ? 0x00 : 0x80) */
+#define MAX_TXPWR_IDX_NMODE_92S	63
+#define Reset_Cnt_Limit			3
+
+#ifdef CONFIG_PCI_HCI
+	#define MAX_AGGR_NUM	0x0B
+#else
+	#define MAX_AGGR_NUM	0x07
+#endif /* CONFIG_PCI_HCI */
+
+
+/*--------------------------Define Parameters End-------------------------------*/
+
+
+/*------------------------------Define structure----------------------------*/
+
+/*------------------------------Define structure End----------------------------*/
+
+/*--------------------------Exported Function prototype---------------------*/
+u32
+PHY_QueryBBReg_8723D(
+	IN	PADAPTER	Adapter,
+	IN	u32		RegAddr,
+	IN	u32		BitMask
+);
+
+VOID
+PHY_SetBBReg_8723D(
+	IN	PADAPTER	Adapter,
+	IN	u32		RegAddr,
+	IN	u32		BitMask,
+	IN	u32		Data
+);
+
+u32
+PHY_QueryRFReg_8723D(
+	IN	PADAPTER		Adapter,
+	IN	enum rf_path		eRFPath,
+	IN	u32				RegAddr,
+	IN	u32				BitMask
+);
+
+VOID
+PHY_SetRFReg_8723D(
+	IN	PADAPTER		Adapter,
+	IN	enum rf_path		eRFPath,
+	IN	u32				RegAddr,
+	IN	u32				BitMask,
+	IN	u32				Data
+);
+
+/* MAC/BB/RF HAL config */
+int PHY_BBConfig8723D(PADAPTER	Adapter);
+
+int PHY_RFConfig8723D(PADAPTER	Adapter);
+
+s32 PHY_MACConfig8723D(PADAPTER padapter);
+
+int
+PHY_ConfigRFWithParaFile_8723D(
+	IN	PADAPTER			Adapter,
+	IN	u8				*pFileName,
+	enum rf_path				eRFPath
+);
+
+VOID
+PHY_SetTxPowerIndex_8723D(
+	IN	PADAPTER			Adapter,
+	IN	u32					PowerIndex,
+	IN	enum rf_path			RFPath,
+	IN	u8					Rate
+);
+
+u8
+PHY_GetTxPowerIndex_8723D(
+	IN	PADAPTER			pAdapter,
+	IN	enum rf_path			RFPath,
+	IN	u8					Rate,
+	IN	u8					BandWidth,
+	IN	u8					Channel,
+	struct txpwr_idx_comp *tic
+);
+
+VOID
+PHY_GetTxPowerLevel8723D(
+	IN	PADAPTER		Adapter,
+	OUT s32				*powerlevel
+);
+
+VOID
+PHY_SetTxPowerLevel8723D(
+	IN	PADAPTER		Adapter,
+	IN	u8			channel
+);
+
+VOID
+PHY_SetSwChnlBWMode8723D(
+	IN	PADAPTER			Adapter,
+	IN	u8					channel,
+	IN	enum channel_width	Bandwidth,
+	IN	u8					Offset40,
+	IN	u8					Offset80
+);
+
+VOID phy_set_rf_path_switch_8723d(
+	IN	struct dm_struct		*phydm,
+	IN	bool		bMain
+);
+/*--------------------------Exported Function prototype End---------------------*/
+
+#endif
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/include/Hal8723DPhyReg.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/Hal8723DPhyReg.h
--- linux-5.6.3/3rdparty/rtl8821ce/include/Hal8723DPhyReg.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/Hal8723DPhyReg.h	2020-04-10 16:35:06.845661421 +0300
@@ -0,0 +1,1134 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#ifndef __INC_HAL8723DPHYREG_H__
+#define __INC_HAL8723DPHYREG_H__
+
+#define		rSYM_WLBT_PAPE_SEL		0x64
+/*
+ * BB-PHY register PMAC 0x100 PHY 0x800 - 0xEFF
+ * 1. PMAC duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF
+ * 2. 0x800/0x900/0xA00/0xC00/0xD00/0xE00
+ * 3. RF register 0x00-2E
+ * 4. Bit Mask for BB/RF register
+ * 5. Other definition for BB/RF R/W
+ *   */
+
+
+/*
+ * 1. PMAC duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF
+ * 1. Page1(0x100)
+ *   */
+#define		rPMAC_Reset					0x100
+#define		rPMAC_TxStart					0x104
+#define		rPMAC_TxLegacySIG				0x108
+#define		rPMAC_TxHTSIG1				0x10c
+#define		rPMAC_TxHTSIG2				0x110
+#define		rPMAC_PHYDebug				0x114
+#define		rPMAC_TxPacketNum				0x118
+#define		rPMAC_TxIdle					0x11c
+#define		rPMAC_TxMACHeader0			0x120
+#define		rPMAC_TxMACHeader1			0x124
+#define		rPMAC_TxMACHeader2			0x128
+#define		rPMAC_TxMACHeader3			0x12c
+#define		rPMAC_TxMACHeader4			0x130
+#define		rPMAC_TxMACHeader5			0x134
+#define		rPMAC_TxDataType				0x138
+#define		rPMAC_TxRandomSeed			0x13c
+#define		rPMAC_CCKPLCPPreamble			0x140
+#define		rPMAC_CCKPLCPHeader			0x144
+#define		rPMAC_CCKCRC16				0x148
+#define		rPMAC_OFDMRxCRC32OK			0x170
+#define		rPMAC_OFDMRxCRC32Er			0x174
+#define		rPMAC_OFDMRxParityEr			0x178
+#define		rPMAC_OFDMRxCRC8Er			0x17c
+#define		rPMAC_CCKCRxRC16Er			0x180
+#define		rPMAC_CCKCRxRC32Er			0x184
+#define		rPMAC_CCKCRxRC32OK			0x188
+#define		rPMAC_TxStatus					0x18c
+
+/*
+ * 2. Page2(0x200)
+ *
+ * The following two definition are only used for USB interface. */
+#define		RF_BB_CMD_ADDR				0x02c0	/* RF/BB read/write command address. */
+#define		RF_BB_CMD_DATA				0x02c4	/* RF/BB read/write command data. */
+
+/*
+ * 3. Page8(0x800)
+ *   */
+#define		rFPGA0_RFMOD				0x800	/* RF mode & CCK TxSC // RF BW Setting?? */
+
+#define		rFPGA0_TxInfo				0x804	/* Status report?? */
+#define		rFPGA0_PSDFunction			0x808
+
+#define		rFPGA0_TxGainStage			0x80c	/* Set TX PWR init gain? */
+
+#define		rFPGA0_RFTiming1			0x810	/* Useless now */
+#define		rFPGA0_RFTiming2			0x814
+
+#define		rFPGA0_XA_HSSIParameter1		0x820	/* RF 3 wire register */
+#define		rFPGA0_XA_HSSIParameter2		0x824
+#define		rFPGA0_XB_HSSIParameter1		0x828
+#define		rFPGA0_XB_HSSIParameter2		0x82c
+#define		rTxAGC_B_Rate18_06				0x830
+#define		rTxAGC_B_Rate54_24				0x834
+#define		rTxAGC_B_CCK1_55_Mcs32		0x838
+#define		rTxAGC_B_Mcs03_Mcs00			0x83c
+
+#define		rTxAGC_B_Mcs07_Mcs04			0x848
+#define		rTxAGC_B_Mcs11_Mcs08			0x84c
+
+#define		rFPGA0_XA_LSSIParameter		0x840
+#define		rFPGA0_XB_LSSIParameter		0x844
+
+#define		rFPGA0_RFWakeUpParameter		0x850	/* Useless now */
+#define		rFPGA0_RFSleepUpParameter		0x854
+
+#define		rFPGA0_XAB_SwitchControl		0x858	/* RF Channel switch */
+#define		rFPGA0_XCD_SwitchControl		0x85c
+
+#define		rFPGA0_XA_RFInterfaceOE		0x860	/* RF Channel switch */
+#define		rFPGA0_XB_RFInterfaceOE		0x864
+
+#define		rTxAGC_B_Mcs15_Mcs12			0x868
+#define		rTxAGC_B_CCK11_A_CCK2_11		0x86c
+
+#define		rFPGA0_XAB_RFInterfaceSW		0x870	/* RF Interface Software Control */
+#define		rFPGA0_XCD_RFInterfaceSW		0x874
+
+#define		rFPGA0_XAB_RFParameter		0x878	/* RF Parameter */
+#define		rFPGA0_XCD_RFParameter		0x87c
+
+#define		rFPGA0_AnalogParameter1		0x880	/* Crystal cap setting RF-R/W protection for parameter4?? */
+#define		rFPGA0_AnalogParameter2		0x884
+#define		rFPGA0_AnalogParameter3		0x888	/* Useless now */
+#define		rFPGA0_AnalogParameter4		0x88c
+
+#define		rFPGA0_XA_LSSIReadBack		0x8a0	/* Tranceiver LSSI Readback */
+#define		rFPGA0_XB_LSSIReadBack		0x8a4
+#define		rFPGA0_XC_LSSIReadBack		0x8a8
+#define		rFPGA0_XD_LSSIReadBack		0x8ac
+
+#define		rFPGA0_PSDReport				0x8b4	/* Useless now */
+#define		TransceiverA_HSPI_Readback	0x8b8	/* Transceiver A HSPI Readback */
+#define		TransceiverB_HSPI_Readback	0x8bc	/* Transceiver B HSPI Readback */
+#define		rFPGA0_XAB_RFInterfaceRB		0x8e0	/* Useless now // RF Interface Readback Value */
+#define		rFPGA0_XCD_RFInterfaceRB		0x8e4	/* Useless now */
+
+/*
+ * 4. Page9(0x900)
+ *   */
+#define	rFPGA1_RFMOD				0x900	/* RF mode & OFDM TxSC // RF BW Setting?? */
+#define	rFPGA1_TxBlock				0x904	/* Useless now */
+#define	rFPGA1_DebugSelect			0x908	/* Useless now */
+#define	rFPGA1_TxInfo				0x90c	/* Useless now // Status report?? */
+#define	rDPDT_control				0x92c
+#define	rfe_ctrl_anta_src				0x930
+#define	rS0S1_PathSwitch			0x948
+#define	rBBrx_DFIR					0x954
+
+/*
+ * 5. PageA(0xA00)
+ *
+ * Set Control channel to upper or lower. These settings are required only for 40MHz */
+#define		rCCK0_System				0xa00
+
+#define		rCCK0_AFESetting			0xa04	/* Disable init gain now // Select RX path by RSSI */
+#define		rCCK0_CCA					0xa08	/* Disable init gain now // Init gain */
+
+#define		rCCK0_RxAGC1				0xa0c	/* AGC default value, saturation level // Antenna Diversity, RX AGC, LNA Threshold, RX LNA Threshold useless now. Not the same as 90 series */
+#define		rCCK0_RxAGC2				0xa10	/* AGC & DAGC */
+
+#define		rCCK0_RxHP					0xa14
+
+#define		rCCK0_DSPParameter1		0xa18	/* Timing recovery & Channel estimation threshold */
+#define		rCCK0_DSPParameter2		0xa1c	/* SQ threshold */
+
+#define		rCCK0_TxFilter1				0xa20
+#define		rCCK0_TxFilter2				0xa24
+#define		rCCK0_DebugPort			0xa28	/* debug port and Tx filter3 */
+#define		rCCK0_FalseAlarmReport		0xa2c	/* 0xa2d	useless now 0xa30-a4f channel report */
+#define		rCCK0_TRSSIReport		0xa50
+#define		rCCK0_RxReport			0xa54  /* 0xa57 */
+#define		rCCK0_FACounterLower		0xa5c  /* 0xa5b */
+#define		rCCK0_FACounterUpper		0xa58  /* 0xa5c */
+
+/*
+ * PageB(0xB00)
+ *   */
+#define rPdp_AntA						0xb00
+#define rPdp_AntA_4						0xb04
+#define rPdp_AntA_8						0xb08
+#define rPdp_AntA_C						0xb0c
+#define rPdp_AntA_10					0xb10
+#define rPdp_AntA_14					0xb14
+#define rPdp_AntA_18					0xb18
+#define rPdp_AntA_1C					0xb1c
+#define rPdp_AntA_20					0xb20
+#define rPdp_AntA_24					0xb24
+
+#define rConfig_Pmpd_AntA				0xb28
+#define rConfig_ram64x16				0xb2c
+
+#define rBndA							0xb30
+#define rHssiPar						0xb34
+
+#define rConfig_AntA					0xb68
+#define rConfig_AntB					0xb6c
+
+#define rPdp_AntB						0xb70
+#define rPdp_AntB_4						0xb74
+#define rPdp_AntB_8						0xb78
+#define rPdp_AntB_C						0xb7c
+#define rPdp_AntB_10					0xb80
+#define rPdp_AntB_14					0xb84
+#define rPdp_AntB_18					0xb88
+#define rPdp_AntB_1C					0xb8c
+#define rPdp_AntB_20					0xb90
+#define rPdp_AntB_24					0xb94
+
+#define rConfig_Pmpd_AntB				0xb98
+
+#define rBndB							0xba0
+
+#define rAPK							0xbd8
+#define rPm_Rx0_AntA					0xbdc
+#define rPm_Rx1_AntA					0xbe0
+#define rPm_Rx2_AntA					0xbe4
+#define rPm_Rx3_AntA					0xbe8
+#define rPm_Rx0_AntB					0xbec
+#define rPm_Rx1_AntB					0xbf0
+#define rPm_Rx2_AntB					0xbf4
+#define rPm_Rx3_AntB					0xbf8
+/*
+ * 6. PageC(0xC00)
+ *   */
+#define		rOFDM0_LSTF				0xc00
+
+#define		rOFDM0_TRxPathEnable		0xc04
+#define		rOFDM0_TRMuxPar			0xc08
+#define		rOFDM0_TRSWIsolation		0xc0c
+
+#define		rOFDM0_XARxAFE			0xc10  /* RxIQ DC offset, Rx digital filter, DC notch filter */
+#define		rOFDM0_XARxIQImbalance		0xc14  /* RxIQ imbalance matrix */
+#define		rOFDM0_XBRxAFE		0xc18
+#define		rOFDM0_XBRxIQImbalance	0xc1c
+#define		rOFDM0_XCRxAFE		0xc20
+#define		rOFDM0_XCRxIQImbalance	0xc24
+#define		rOFDM0_XDRxAFE		0xc28
+#define		rOFDM0_XDRxIQImbalance	0xc2c
+
+#define		rOFDM0_RxDetector1			0xc30  /* PD, BW & SBD	// DM tune init gain */
+#define		rOFDM0_RxDetector2			0xc34  /* SBD & Fame Sync. */
+#define		rOFDM0_RxDetector3			0xc38  /* Frame Sync. */
+#define		rOFDM0_RxDetector4			0xc3c  /* PD, SBD, Frame Sync & Short-GI */
+
+#define		rOFDM0_RxDSP				0xc40  /* Rx Sync Path */
+#define		rOFDM0_CFOandDAGC		0xc44  /* CFO & DAGC */
+#define		rOFDM0_CCADropThreshold	0xc48 /* CCA Drop threshold */
+#define		rOFDM0_ECCAThreshold		0xc4c /* energy CCA */
+
+#define		rOFDM0_XAAGCCore1			0xc50	/* DIG */
+#define		rOFDM0_XAAGCCore2			0xc54
+#define		rOFDM0_XBAGCCore1			0xc58
+#define		rOFDM0_XBAGCCore2			0xc5c
+#define		rOFDM0_XCAGCCore1			0xc60
+#define		rOFDM0_XCAGCCore2			0xc64
+#define		rOFDM0_XDAGCCore1			0xc68
+#define		rOFDM0_XDAGCCore2			0xc6c
+
+#define		rOFDM0_AGCParameter1			0xc70
+#define		rOFDM0_AGCParameter2			0xc74
+#define		rOFDM0_AGCRSSITable			0xc78
+#define		rOFDM0_HTSTFAGC				0xc7c
+
+#define		rOFDM0_XATxIQImbalance		0xc80	/* TX PWR TRACK and DIG */
+#define		rOFDM0_XATxAFE				0xc84
+#define		rOFDM0_XBTxIQImbalance		0xc88
+#define		rOFDM0_XBTxAFE				0xc8c
+#define		rOFDM0_XCTxIQImbalance		0xc90
+#define		rOFDM0_XCTxAFE			0xc94
+#define		rOFDM0_XDTxIQImbalance		0xc98
+#define		rOFDM0_XDTxAFE				0xc9c
+
+#define		rOFDM0_RxIQExtAnta			0xca0
+#define		rOFDM0_TxCoeff1				0xca4
+#define		rOFDM0_TxCoeff2				0xca8
+#define		rOFDM0_TxCoeff3				0xcac
+#define		rOFDM0_TxCoeff4				0xcb0
+#define		rOFDM0_TxCoeff5				0xcb4
+#define		rOFDM0_TxCoeff6				0xcb8
+#define		rOFDM0_RxHPParameter			0xce0
+#define		rOFDM0_TxPseudoNoiseWgt		0xce4
+#define		rOFDM0_FrameSync				0xcf0
+#define		rOFDM0_DFSReport				0xcf4
+
+/*
+ * 7. PageD(0xD00)
+ *   */
+#define		rOFDM1_LSTF					0xd00
+#define		rOFDM1_TRxPathEnable			0xd04
+
+#define		rOFDM1_CFO						0xd08	/* No setting now */
+#define		rOFDM1_CSI1					0xd10
+#define		rOFDM1_SBD						0xd14
+#define		rOFDM1_CSI2					0xd18
+#define		rOFDM1_CFOTracking			0xd2c
+#define		rOFDM1_TRxMesaure1			0xd34
+#define		rOFDM1_IntfDet					0xd3c
+#define		rOFDM1_PseudoNoiseStateAB		0xd50
+#define		rOFDM1_PseudoNoiseStateCD		0xd54
+#define		rOFDM1_RxPseudoNoiseWgt		0xd58
+
+#define		rOFDM_PHYCounter1				0xda0  /* cca, parity fail */
+#define		rOFDM_PHYCounter2				0xda4  /* rate illegal, crc8 fail */
+#define		rOFDM_PHYCounter3				0xda8  /* MCS not support */
+
+#define		rOFDM_ShortCFOAB				0xdac	/* No setting now */
+#define		rOFDM_ShortCFOCD				0xdb0
+#define		rOFDM_LongCFOAB				0xdb4
+#define		rOFDM_LongCFOCD				0xdb8
+#define		rOFDM_TailCFOAB				0xdbc
+#define		rOFDM_TailCFOCD				0xdc0
+#define		rOFDM_PWMeasure1		0xdc4
+#define		rOFDM_PWMeasure2		0xdc8
+#define		rOFDM_BWReport				0xdcc
+#define		rOFDM_AGCReport				0xdd0
+#define		rOFDM_RxSNR					0xdd4
+#define		rOFDM_RxEVMCSI				0xdd8
+#define		rOFDM_SIGReport				0xddc
+
+
+/*
+ * 8. PageE(0xE00)
+ *   */
+#define		rTxAGC_A_Rate18_06			0xe00
+#define		rTxAGC_A_Rate54_24			0xe04
+#define		rTxAGC_A_CCK1_Mcs32			0xe08
+#define		rTxAGC_A_Mcs03_Mcs00			0xe10
+#define		rTxAGC_A_Mcs07_Mcs04			0xe14
+#define		rTxAGC_A_Mcs11_Mcs08			0xe18
+#define		rTxAGC_A_Mcs15_Mcs12			0xe1c
+
+#define		rFPGA0_IQK					0xe28
+#define		rTx_IQK_Tone_A				0xe30
+#define		rRx_IQK_Tone_A				0xe34
+#define		rTx_IQK_PI_A					0xe38
+#define		rRx_IQK_PI_A					0xe3c
+
+#define		rTx_IQK						0xe40
+#define		rRx_IQK						0xe44
+#define		rIQK_AGC_Pts					0xe48
+#define		rIQK_AGC_Rsp					0xe4c
+#define		rTx_IQK_Tone_B				0xe50
+#define		rRx_IQK_Tone_B				0xe54
+#define		rTx_IQK_PI_B					0xe58
+#define		rRx_IQK_PI_B					0xe5c
+#define		rIQK_AGC_Cont				0xe60
+
+#define		rBlue_Tooth					0xe6c
+#define		rRx_Wait_CCA					0xe70
+#define		rTx_CCK_RFON					0xe74
+#define		rTx_CCK_BBON				0xe78
+#define		rTx_OFDM_RFON				0xe7c
+#define		rTx_OFDM_BBON				0xe80
+#define		rTx_To_Rx					0xe84
+#define		rTx_To_Tx					0xe88
+#define		rRx_CCK						0xe8c
+
+#define		rTx_Power_Before_IQK_A		0xe94
+#define		rTx_Power_After_IQK_A			0xe9c
+
+#define		rRx_Power_Before_IQK_A		0xea0
+#define		rRx_Power_Before_IQK_A_2		0xea4
+#define		rRx_Power_After_IQK_A			0xea8
+#define		rRx_Power_After_IQK_A_2		0xeac
+
+#define		rTx_Power_Before_IQK_B		0xeb4
+#define		rTx_Power_After_IQK_B			0xebc
+
+#define		rRx_Power_Before_IQK_B		0xec0
+#define		rRx_Power_Before_IQK_B_2		0xec4
+#define		rRx_Power_After_IQK_B			0xec8
+#define		rRx_Power_After_IQK_B_2		0xecc
+
+#define		rRx_OFDM					0xed0
+#define		rRx_Wait_RIFS				0xed4
+#define		rRx_TO_Rx					0xed8
+#define		rStandby						0xedc
+#define		rSleep						0xee0
+#define		rPMPD_ANAEN				0xeec
+
+/*
+ * 7. RF Register 0x00-0x2E (RF 8256)
+ * RF-0222D 0x00-3F
+ *
+ * Zebra1 */
+#define		rZebra1_HSSIEnable				0x0	/* Useless now */
+#define		rZebra1_TRxEnable1				0x1
+#define		rZebra1_TRxEnable2				0x2
+#define		rZebra1_AGC					0x4
+#define		rZebra1_ChargePump			0x5
+#define		rZebra1_Channel				0x7	/* RF channel switch */
+
+/* #endif */
+#define		rZebra1_TxGain					0x8	/* Useless now */
+#define		rZebra1_TxLPF					0x9
+#define		rZebra1_RxLPF					0xb
+#define		rZebra1_RxHPFCorner			0xc
+
+/* Zebra4 */
+#define		rGlobalCtrl						0	/* Useless now */
+#define		rRTL8256_TxLPF					19
+#define		rRTL8256_RxLPF					11
+
+/* RTL8258 */
+#define		rRTL8258_TxLPF					0x11	/* Useless now */
+#define		rRTL8258_RxLPF					0x13
+#define		rRTL8258_RSSILPF				0xa
+
+/*
+ * RL6052 Register definition
+ *   */
+#define		RF_AC						0x00	/* */
+
+#define		RF_IQADJ_G1				0x01	/* */
+#define		RF_IQADJ_G2				0x02	/* */
+#define		RF_BS_PA_APSET_G1_G4		0x03
+#define		RF_BS_PA_APSET_G5_G8		0x04
+#define		RF_POW_TRSW				0x05	/* */
+
+#define		RF_GAIN_RX					0x06	/* */
+#define		RF_GAIN_TX					0x07	/* */
+
+#define		RF_TXM_IDAC				0x08	/* */
+#define		RF_IPA_G					0x09	/* */
+#define		RF_TXBIAS_G				0x0A
+#define		RF_TXPA_AG					0x0B
+#define		RF_IPA_A					0x0C	/* */
+#define		RF_TXBIAS_A				0x0D
+#define		RF_BS_PA_APSET_G9_G11	0x0E
+#define		RF_BS_IQGEN				0x0F	/* */
+
+#define		RF_MODE1					0x10	/* */
+#define		RF_MODE2					0x11	/* */
+
+#define		RF_RX_AGC_HP				0x12	/* */
+#define		RF_TX_AGC					0x13	/* */
+#define		RF_BIAS						0x14	/* */
+#define		RF_IPA						0x15	/* */
+#define		RF_TXBIAS					0x16
+#define		RF_POW_ABILITY			0x17	/* */
+#define		RF_MODE_AG				0x18	/* */
+#define		rRfChannel					0x18	/* RF channel and BW switch */
+#define		RF_CHNLBW					0x18	/* RF channel and BW switch */
+#define		RF_TOP						0x19	/* */
+
+#define		RF_RX_G1					0x1A	/* */
+#define		RF_RX_G2					0x1B	/* */
+
+#define		RF_RX_BB2					0x1C	/* */
+#define		RF_RX_BB1					0x1D	/* */
+
+#define		RF_RCK1					0x1E	/* */
+#define		RF_RCK2					0x1F	/* */
+
+#define		RF_TX_G1					0x20	/* */
+#define		RF_TX_G2					0x21	/* */
+#define		RF_TX_G3					0x22	/* */
+
+#define		RF_TX_BB1					0x23	/* */
+
+#define		RF_T_METER					0x24	/* */
+
+#define		RF_SYN_G1					0x25	/* RF TX Power control */
+#define		RF_SYN_G2					0x26	/* RF TX Power control */
+#define		RF_SYN_G3					0x27	/* RF TX Power control */
+#define		RF_SYN_G4					0x28	/* RF TX Power control */
+#define		RF_SYN_G5					0x29	/* RF TX Power control */
+#define		RF_SYN_G6					0x2A	/* RF TX Power control */
+#define		RF_SYN_G7					0x2B	/* RF TX Power control */
+#define		RF_SYN_G8					0x2C	/* RF TX Power control */
+
+#define		RF_RCK_OS					0x30	/* RF TX PA control */
+
+#define		RF_TXPA_G1					0x31	/* RF TX PA control */
+#define		RF_TXPA_G2					0x32	/* RF TX PA control */
+#define		RF_TXPA_G3					0x33	/* RF TX PA control */
+#define	RF_TX_BIAS_A				0x35
+#define	RF_TX_BIAS_D				0x36
+#define	RF_LOBF_9					0x38
+#define	RF_RXRF_A3					0x3C	/*	 */
+#define	RF_TRSW					0x3F
+
+#define	RF_TXRF_A2					0x41
+#define	RF_T_METER_88E				0x42
+#define	RF_TXPA_G4					0x46
+#define	RF_TXPA_A4					0x4B
+#define	RF_0x52					0x52
+#define	RF_WE_LUT					0xEF
+#define	RF_S0S1					0xB0
+
+/*
+ * Bit Mask
+ *
+ * 1. Page1(0x100) */
+#define		bBBResetB						0x100	/* Useless now? */
+#define		bGlobalResetB					0x200
+#define		bOFDMTxStart					0x4
+#define		bCCKTxStart						0x8
+#define		bCRC32Debug					0x100
+#define		bPMACLoopback					0x10
+#define		bTxLSIG							0xffffff
+#define		bOFDMTxRate					0xf
+#define		bOFDMTxReserved				0x10
+#define		bOFDMTxLength					0x1ffe0
+#define		bOFDMTxParity					0x20000
+#define		bTxHTSIG1						0xffffff
+#define		bTxHTMCSRate					0x7f
+#define		bTxHTBW						0x80
+#define		bTxHTLength					0xffff00
+#define		bTxHTSIG2						0xffffff
+#define		bTxHTSmoothing					0x1
+#define		bTxHTSounding					0x2
+#define		bTxHTReserved					0x4
+#define		bTxHTAggreation				0x8
+#define		bTxHTSTBC						0x30
+#define		bTxHTAdvanceCoding			0x40
+#define		bTxHTShortGI					0x80
+#define		bTxHTNumberHT_LTF			0x300
+#define		bTxHTCRC8						0x3fc00
+#define		bCounterReset					0x10000
+#define		bNumOfOFDMTx					0xffff
+#define		bNumOfCCKTx					0xffff0000
+#define		bTxIdleInterval					0xffff
+#define		bOFDMService					0xffff0000
+#define		bTxMACHeader					0xffffffff
+#define		bTxDataInit						0xff
+#define		bTxHTMode						0x100
+#define		bTxDataType					0x30000
+#define		bTxRandomSeed					0xffffffff
+#define		bCCKTxPreamble					0x1
+#define		bCCKTxSFD						0xffff0000
+#define		bCCKTxSIG						0xff
+#define		bCCKTxService					0xff00
+#define		bCCKLengthExt					0x8000
+#define		bCCKTxLength					0xffff0000
+#define		bCCKTxCRC16					0xffff
+#define		bCCKTxStatus					0x1
+#define		bOFDMTxStatus					0x2
+
+#define		IS_BB_REG_OFFSET_92S(_Offset)		((_Offset >= 0x800) && (_Offset <= 0xfff))
+#define		RF_TX_GAIN_OFFSET_8723D(_val) (abs((_val)) | (((_val) > 0) ? BIT(4) : 0))
+
+/* 2. Page8(0x800) */
+#define		bRFMOD							0x1	/* Reg 0x800 rFPGA0_RFMOD */
+#define		bJapanMode						0x2
+#define		bCCKTxSC						0x30
+#define		bCCKEn							0x1000000
+#define		bOFDMEn						0x2000000
+
+#define		bOFDMRxADCPhase           0x10000	/* Useless now */
+#define		bOFDMTxDACPhase		0x40000
+#define		bXATxAGC			0x3f
+
+#define		bAntennaSelect		0x0300
+
+#define		bXBTxAGC                 0xf00	/* Reg 80c rFPGA0_TxGainStage */
+#define		bXCTxAGC			0xf000
+#define		bXDTxAGC			0xf0000
+
+#define		bPAStart                 0xf0000000	/* Useless now */
+#define		bTRStart			0x00f00000
+#define		bRFStart			0x0000f000
+#define		bBBStart			0x000000f0
+#define		bBBCCKStart		0x0000000f
+#define		bPAEnd                    0xf          /* Reg0x814 */
+#define		bTREnd			0x0f000000
+#define		bRFEnd			0x000f0000
+#define		bCCAMask                  0x000000f0   /* T2R */
+#define		bR2RCCAMask		0x00000f00
+#define		bHSSI_R2TDelay		0xf8000000
+#define		bHSSI_T2RDelay		0xf80000
+#define		bContTxHSSI              0x400     /* chane gain at continue Tx */
+#define		bIGFromCCK		0x200
+#define		bAGCAddress		0x3f
+#define		bRxHPTx			0x7000
+#define		bRxHPT2R			0x38000
+#define		bRxHPCCKIni		0xc0000
+#define		bAGCTxCode		0xc00000
+#define		bAGCRxCode		0x300000
+
+#define		b3WireDataLength         0x800	/* Reg 0x820~84f rFPGA0_XA_HSSIParameter1 */
+#define		b3WireAddressLength		0x400
+
+#define		b3WireRFPowerDown         0x1	/* Useless now
+ * #define bHWSISelect		0x8 */
+#define		b5GPAPEPolarity		0x40000000
+#define		b2GPAPEPolarity		0x80000000
+#define		bRFSW_TxDefaultAnt		0x3
+#define		bRFSW_TxOptionAnt		0x30
+#define		bRFSW_RxDefaultAnt		0x300
+#define		bRFSW_RxOptionAnt		0x3000
+#define		bRFSI_3WireData		0x1
+#define		bRFSI_3WireClock		0x2
+#define		bRFSI_3WireLoad		0x4
+#define		bRFSI_3WireRW		0x8
+#define		bRFSI_3Wire			0xf
+
+#define		bRFSI_RFENV              0x10	/* Reg 0x870 rFPGA0_XAB_RFInterfaceSW */
+
+#define		bRFSI_TRSW               0x20	/* Useless now */
+#define		bRFSI_TRSWB		0x40
+#define		bRFSI_ANTSW		0x100
+#define		bRFSI_ANTSWB		0x200
+#define		bRFSI_PAPE			0x400
+#define		bRFSI_PAPE5G		0x800
+#define		bBandSelect			0x1
+#define		bHTSIG2_GI			0x80
+#define		bHTSIG2_Smoothing		0x01
+#define		bHTSIG2_Sounding		0x02
+#define		bHTSIG2_Aggreaton		0x08
+#define		bHTSIG2_STBC		0x30
+#define		bHTSIG2_AdvCoding		0x40
+#define		bHTSIG2_NumOfHTLTF	0x300
+#define		bHTSIG2_CRC8		0x3fc
+#define		bHTSIG1_MCS		0x7f
+#define		bHTSIG1_BandWidth		0x80
+#define		bHTSIG1_HTLength		0xffff
+#define		bLSIG_Rate			0xf
+#define		bLSIG_Reserved		0x10
+#define		bLSIG_Length		0x1fffe
+#define		bLSIG_Parity			0x20
+#define		bCCKRxPhase		0x4
+
+#define		bLSSIReadAddress          0x7f800000   /* T65 RF */
+
+#define		bLSSIReadEdge             0x80000000   /* LSSI "Read" edge signal */
+
+#define		bLSSIReadBackData         0xfffff		/* T65 RF */
+
+#define		bLSSIReadOKFlag           0x1000	/* Useless now */
+#define		bCCKSampleRate            0x8       /* 0: 44MHz, 1:88MHz     */
+#define		bRegulator0Standby		0x1
+#define		bRegulatorPLLStandby		0x2
+#define		bRegulator1Standby		0x4
+#define		bPLLPowerUp		0x8
+#define		bDPLLPowerUp		0x10
+#define		bDA10PowerUp		0x20
+#define		bAD7PowerUp		0x200
+#define		bDA6PowerUp		0x2000
+#define		bXtalPowerUp		0x4000
+#define		b40MDClkPowerUP		0x8000
+#define		bDA6DebugMode		0x20000
+#define		bDA6Swing			0x380000
+
+#define		bADClkPhase               0x4000000	/* Reg 0x880 rFPGA0_AnalogParameter1 20/40 CCK support switch 40/80 BB MHZ */
+
+#define		b80MClkDelay              0x18000000	/* Useless */
+#define		bAFEWatchDogEnable		0x20000000
+
+#define		bXtalCap01                0xc0000000	/* Reg 0x884 rFPGA0_AnalogParameter2 Crystal cap */
+#define		bXtalCap23			0x3
+#define		bXtalCap92x					0x0f000000
+#define		bXtalCap			0x0f000000
+
+#define		bIntDifClkEnable          0x400	/* Useless */
+#define		bExtSigClkEnable		0x800
+#define		bBandgapMbiasPowerUp	0x10000
+#define		bAD11SHGain		0xc0000
+#define		bAD11InputRange		0x700000
+#define		bAD11OPCurrent		0x3800000
+#define		bIPathLoopback		0x4000000
+#define		bQPathLoopback		0x8000000
+#define		bAFELoopback		0x10000000
+#define		bDA10Swing		0x7e0
+#define		bDA10Reverse		0x800
+#define		bDAClkSource		0x1000
+#define		bAD7InputRange		0x6000
+#define		bAD7Gain			0x38000
+#define		bAD7OutputCMMode		0x40000
+#define		bAD7InputCMMode		0x380000
+#define		bAD7Current			0xc00000
+#define		bRegulatorAdjust		0x7000000
+#define		bAD11PowerUpAtTx		0x1
+#define		bDA10PSAtTx		0x10
+#define		bAD11PowerUpAtRx		0x100
+#define		bDA10PSAtRx		0x1000
+#define		bCCKRxAGCFormat		0x200
+#define		bPSDFFTSamplepPoint		0xc000
+#define		bPSDAverageNum		0x3000
+#define		bIQPathControl		0xc00
+#define		bPSDFreq			0x3ff
+#define		bPSDAntennaPath		0x30
+#define		bPSDIQSwitch		0x40
+#define		bPSDRxTrigger		0x400000
+#define		bPSDTxTrigger		0x80000000
+#define		bPSDSineToneScale		0x7f000000
+#define		bPSDReport			0xffff
+
+/* 3. Page9(0x900) */
+#define		bOFDMTxSC                 0x30000000	/* Useless */
+#define		bCCKTxOn			0x1
+#define		bOFDMTxOn		0x2
+#define		bDebugPage                0xfff  /* reset debug page and also HWord, LWord */
+#define		bDebugItem                0xff   /* reset debug page and LWord */
+#define		bAntL			0x10
+#define		bAntNonHT				0x100
+#define		bAntHT1			0x1000
+#define		bAntHT2			0x10000
+#define		bAntHT1S1			0x100000
+#define		bAntNonHTS1		0x1000000
+
+/* 4. PageA(0xA00) */
+#define		bCCKBBMode				0x3	/* Useless */
+#define		bCCKTxPowerSaving		0x80
+#define		bCCKRxPowerSaving		0x40
+
+#define		bCCKSideBand			0x10	/* Reg 0xa00 rCCK0_System 20/40 switch */
+
+#define		bCCKScramble			0x8	/* Useless */
+#define		bCCKAntDiversity		0x8000
+#define		bCCKCarrierRecovery		0x4000
+#define		bCCKTxRate				0x3000
+#define		bCCKDCCancel			0x0800
+#define		bCCKISICancel			0x0400
+#define		bCCKMatchFilter			0x0200
+#define		bCCKEqualizer			0x0100
+#define		bCCKPreambleDetect		0x800000
+#define		bCCKFastFalseCCA		0x400000
+#define		bCCKChEstStart			0x300000
+#define		bCCKCCACount			0x080000
+#define		bCCKcs_lim				0x070000
+#define		bCCKBistMode			0x80000000
+#define		bCCKCCAMask			0x40000000
+#define		bCCKTxDACPhase		0x4
+#define		bCCKRxADCPhase		0x20000000   /* r_rx_clk */
+#define		bCCKr_cp_mode0		0x0100
+#define		bCCKTxDCOffset			0xf0
+#define		bCCKRxDCOffset			0xf
+#define		bCCKCCAMode			0xc000
+#define		bCCKFalseCS_lim			0x3f00
+#define		bCCKCS_ratio			0xc00000
+#define		bCCKCorgBit_sel			0x300000
+#define		bCCKPD_lim				0x0f0000
+#define		bCCKNewCCA			0x80000000
+#define		bCCKRxHPofIG			0x8000
+#define		bCCKRxIG				0x7f00
+#define		bCCKLNAPolarity			0x800000
+#define		bCCKRx1stGain			0x7f0000
+#define		bCCKRFExtend			0x20000000 /* CCK Rx Iinital gain polarity */
+#define		bCCKRxAGCSatLevel		0x1f000000
+#define		bCCKRxAGCSatCount		0xe0
+#define		bCCKRxRFSettle			0x1f       /* AGCsamp_dly */
+#define		bCCKFixedRxAGC			0x8000
+/* #define bCCKRxAGCFormat		0x4000 */   /* remove to HSSI register 0x824 */
+#define		bCCKAntennaPolarity		0x2000
+#define		bCCKTxFilterType		0x0c00
+#define		bCCKRxAGCReportType	0x0300
+#define		bCCKRxDAGCEn			0x80000000
+#define		bCCKRxDAGCPeriod		0x20000000
+#define		bCCKRxDAGCSatLevel		0x1f000000
+#define		bCCKTimingRecovery		0x800000
+#define		bCCKTxC0				0x3f0000
+#define		bCCKTxC1				0x3f000000
+#define		bCCKTxC2				0x3f
+#define		bCCKTxC3				0x3f00
+#define		bCCKTxC4				0x3f0000
+#define		bCCKTxC5				0x3f000000
+#define		bCCKTxC6				0x3f
+#define		bCCKTxC7				0x3f00
+#define		bCCKDebugPort			0xff0000
+#define		bCCKDACDebug			0x0f000000
+#define		bCCKFalseAlarmEnable	0x8000
+#define		bCCKFalseAlarmRead		0x4000
+#define		bCCKTRSSI				0x7f
+#define		bCCKRxAGCReport		0xfe
+#define		bCCKRxReport_AntSel	0x80000000
+#define		bCCKRxReport_MFOff		0x40000000
+#define		bCCKRxRxReport_SQLoss	0x20000000
+#define		bCCKRxReport_Pktloss	0x10000000
+#define		bCCKRxReport_Lockedbit	0x08000000
+#define		bCCKRxReport_RateError	0x04000000
+#define		bCCKRxReport_RxRate	0x03000000
+#define		bCCKRxFACounterLower	0xff
+#define		bCCKRxFACounterUpper	0xff000000
+#define		bCCKRxHPAGCStart		0xe000
+#define		bCCKRxHPAGCFinal		0x1c00
+#define		bCCKRxFalseAlarmEnable	0x8000
+#define		bCCKFACounterFreeze	0x4000
+#define		bCCKTxPathSel			0x10000000
+#define		bCCKDefaultRxPath		0xc000000
+#define		bCCKOptionRxPath		0x3000000
+
+/* 5. PageC(0xC00) */
+#define		bNumOfSTF				0x3	/* Useless */
+#define		bShift_L					0xc0
+#define		bGI_TH					0xc
+#define		bRxPathA				0x1
+#define		bRxPathB				0x2
+#define		bRxPathC				0x4
+#define		bRxPathD				0x8
+#define		bTxPathA				0x1
+#define		bTxPathB				0x2
+#define		bTxPathC				0x4
+#define		bTxPathD				0x8
+#define		bTRSSIFreq				0x200
+#define		bADCBackoff				0x3000
+#define		bDFIRBackoff			0xc000
+#define		bTRSSILatchPhase		0x10000
+#define		bRxIDCOffset			0xff
+#define		bRxQDCOffset			0xff00
+#define		bRxDFIRMode			0x1800000
+#define		bRxDCNFType			0xe000000
+#define		bRXIQImb_A				0x3ff
+#define		bRXIQImb_B				0xfc00
+#define		bRXIQImb_C				0x3f0000
+#define		bRXIQImb_D				0xffc00000
+#define		bDC_dc_Notch			0x60000
+#define		bRxNBINotch			0x1f000000
+#define		bPD_TH					0xf
+#define		bPD_TH_Opt2			0xc000
+#define		bPWED_TH				0x700
+#define		bIfMF_Win_L			0x800
+#define		bPD_Option				0x1000
+#define		bMF_Win_L				0xe000
+#define		bBW_Search_L			0x30000
+#define		bwin_enh_L				0xc0000
+#define		bBW_TH					0x700000
+#define		bED_TH2				0x3800000
+#define		bBW_option				0x4000000
+#define		bRatio_TH				0x18000000
+#define		bWindow_L				0xe0000000
+#define		bSBD_Option				0x1
+#define		bFrame_TH				0x1c
+#define		bFS_Option				0x60
+#define		bDC_Slope_check		0x80
+#define		bFGuard_Counter_DC_L	0xe00
+#define		bFrame_Weight_Short	0x7000
+#define		bSub_Tune				0xe00000
+#define		bFrame_DC_Length		0xe000000
+#define		bSBD_start_offset		0x30000000
+#define		bFrame_TH_2			0x7
+#define		bFrame_GI2_TH			0x38
+#define		bGI2_Sync_en			0x40
+#define		bSarch_Short_Early		0x300
+#define		bSarch_Short_Late		0xc00
+#define		bSarch_GI2_Late		0x70000
+#define		bCFOAntSum				0x1
+#define		bCFOAcc				0x2
+#define		bCFOStartOffset			0xc
+#define		bCFOLookBack			0x70
+#define		bCFOSumWeight			0x80
+#define		bDAGCEnable			0x10000
+#define		bTXIQImb_A				0x3ff
+#define		bTXIQImb_B				0xfc00
+#define		bTXIQImb_C				0x3f0000
+#define		bTXIQImb_D				0xffc00000
+#define		bTxIDCOffset			0xff
+#define		bTxQDCOffset			0xff00
+#define		bTxDFIRMode			0x10000
+#define		bTxPesudoNoiseOn		0x4000000
+#define		bTxPesudoNoise_A		0xff
+#define		bTxPesudoNoise_B		0xff00
+#define		bTxPesudoNoise_C		0xff0000
+#define		bTxPesudoNoise_D		0xff000000
+#define		bCCADropOption			0x20000
+#define		bCCADropThres			0xfff00000
+#define		bEDCCA_H				0xf
+#define		bEDCCA_L				0xf0
+#define		bLambda_ED			0x300
+#define		bRxInitialGain			0x7f
+#define		bRxAntDivEn				0x80
+#define		bRxAGCAddressForLNA	0x7f00
+#define		bRxHighPowerFlow		0x8000
+#define		bRxAGCFreezeThres		0xc0000
+#define		bRxFreezeStep_AGC1	0x300000
+#define		bRxFreezeStep_AGC2	0xc00000
+#define		bRxFreezeStep_AGC3	0x3000000
+#define		bRxFreezeStep_AGC0	0xc000000
+#define		bRxRssi_Cmp_En			0x10000000
+#define		bRxQuickAGCEn			0x20000000
+#define		bRxAGCFreezeThresMode	0x40000000
+#define		bRxOverFlowCheckType	0x80000000
+#define		bRxAGCShift				0x7f
+#define		bTRSW_Tri_Only			0x80
+#define		bPowerThres			0x300
+#define		bRxAGCEn				0x1
+#define		bRxAGCTogetherEn		0x2
+#define		bRxAGCMin				0x4
+#define		bRxHP_Ini				0x7
+#define		bRxHP_TRLNA			0x70
+#define		bRxHP_RSSI				0x700
+#define		bRxHP_BBP1				0x7000
+#define		bRxHP_BBP2				0x70000
+#define		bRxHP_BBP3				0x700000
+#define		bRSSI_H					0x7f0000     /* the threshold for high power */
+#define		bRSSI_Gen				0x7f000000   /* the threshold for ant diversity */
+#define		bRxSettle_TRSW			0x7
+#define		bRxSettle_LNA			0x38
+#define		bRxSettle_RSSI			0x1c0
+#define		bRxSettle_BBP			0xe00
+#define		bRxSettle_RxHP			0x7000
+#define		bRxSettle_AntSW_RSSI	0x38000
+#define		bRxSettle_AntSW		0xc0000
+#define		bRxProcessTime_DAGC	0x300000
+#define		bRxSettle_HSSI			0x400000
+#define		bRxProcessTime_BBPPW	0x800000
+#define		bRxAntennaPowerShift	0x3000000
+#define		bRSSITableSelect		0xc000000
+#define		bRxHP_Final				0x7000000
+#define		bRxHTSettle_BBP			0x7
+#define		bRxHTSettle_HSSI		0x8
+#define		bRxHTSettle_RxHP		0x70
+#define		bRxHTSettle_BBPPW		0x80
+#define		bRxHTSettle_Idle		0x300
+#define		bRxHTSettle_Reserved	0x1c00
+#define		bRxHTRxHPEn			0x8000
+#define		bRxHTAGCFreezeThres	0x30000
+#define		bRxHTAGCTogetherEn	0x40000
+#define		bRxHTAGCMin			0x80000
+#define		bRxHTAGCEn				0x100000
+#define		bRxHTDAGCEn			0x200000
+#define		bRxHTRxHP_BBP			0x1c00000
+#define		bRxHTRxHP_Final		0xe0000000
+#define		bRxPWRatioTH			0x3
+#define		bRxPWRatioEn			0x4
+#define		bRxMFHold				0x3800
+#define		bRxPD_Delay_TH1		0x38
+#define		bRxPD_Delay_TH2		0x1c0
+#define		bRxPD_DC_COUNT_MAX	0x600
+/* #define bRxMF_Hold               0x3800 */
+#define		bRxPD_Delay_TH			0x8000
+#define		bRxProcess_Delay		0xf0000
+#define		bRxSearchrange_GI2_Early	0x700000
+#define		bRxFrame_Guard_Counter_L	0x3800000
+#define		bRxSGI_Guard_L			0xc000000
+#define		bRxSGI_Search_L		0x30000000
+#define		bRxSGI_TH				0xc0000000
+#define		bDFSCnt0				0xff
+#define		bDFSCnt1				0xff00
+#define		bDFSFlag				0xf0000
+#define		bMFWeightSum			0x300000
+#define		bMinIdxTH				0x7f000000
+#define		bDAFormat				0x40000
+#define		bTxChEmuEnable		0x01000000
+#define		bTRSWIsolation_A		0x7f
+#define		bTRSWIsolation_B		0x7f00
+#define		bTRSWIsolation_C		0x7f0000
+#define		bTRSWIsolation_D		0x7f000000
+#define		bExtLNAGain				0x7c00
+
+/* 6. PageE(0xE00) */
+#define		bSTBCEn				0x4	/* Useless */
+#define		bAntennaMapping		0x10
+#define		bNss					0x20
+#define		bCFOAntSumD			0x200
+#define		bPHYCounterReset		0x8000000
+#define		bCFOReportGet			0x4000000
+#define		bOFDMContinueTx		0x10000000
+#define		bOFDMSingleCarrier		0x20000000
+#define		bOFDMSingleTone		0x40000000
+/* #define bRxPath1                 0x01 */
+/* #define bRxPath2                 0x02 */
+/* #define bRxPath3                 0x04 */
+/* #define bRxPath4                 0x08 */
+/* #define bTxPath1                 0x10 */
+/* #define bTxPath2                 0x20 */
+#define		bHTDetect			0x100
+#define		bCFOEn				0x10000
+#define		bCFOValue			0xfff00000
+#define		bSigTone_Re		0x3f
+#define		bSigTone_Im		0x7f00
+#define		bCounter_CCA		0xffff
+#define		bCounter_ParityFail	0xffff0000
+#define		bCounter_RateIllegal		0xffff
+#define		bCounter_CRC8Fail	0xffff0000
+#define		bCounter_MCSNoSupport	0xffff
+#define		bCounter_FastSync	0xffff
+#define		bShortCFO			0xfff
+#define		bShortCFOTLength	12   /* total */
+#define		bShortCFOFLength	11   /* fraction */
+#define		bLongCFO			0x7ff
+#define		bLongCFOTLength	11
+#define		bLongCFOFLength	11
+#define		bTailCFO			0x1fff
+#define		bTailCFOTLength		13
+#define		bTailCFOFLength		12
+#define		bmax_en_pwdB		0xffff
+#define		bCC_power_dB		0xffff0000
+#define		bnoise_pwdB		0xffff
+#define		bPowerMeasTLength	10
+#define		bPowerMeasFLength	3
+#define		bRx_HT_BW			0x1
+#define		bRxSC				0x6
+#define		bRx_HT				0x8
+#define		bNB_intf_det_on		0x1
+#define		bIntf_win_len_cfg	0x30
+#define		bNB_Intf_TH_cfg		0x1c0
+#define		bRFGain				0x3f
+#define		bTableSel			0x40
+#define		bTRSW				0x80
+#define		bRxSNR_A			0xff
+#define		bRxSNR_B			0xff00
+#define		bRxSNR_C			0xff0000
+#define		bRxSNR_D			0xff000000
+#define		bSNREVMTLength		8
+#define		bSNREVMFLength		1
+#define		bCSI1st				0xff
+#define		bCSI2nd				0xff00
+#define		bRxEVM1st			0xff0000
+#define		bRxEVM2nd			0xff000000
+#define		bSIGEVM			0xff
+#define		bPWDB				0xff00
+#define		bSGIEN				0x10000
+
+#define		bSFactorQAM1		0xf	/* Useless */
+#define		bSFactorQAM2		0xf0
+#define		bSFactorQAM3		0xf00
+#define		bSFactorQAM4		0xf000
+#define		bSFactorQAM5		0xf0000
+#define		bSFactorQAM6		0xf0000
+#define		bSFactorQAM7		0xf00000
+#define		bSFactorQAM8		0xf000000
+#define		bSFactorQAM9		0xf0000000
+#define		bCSIScheme			0x100000
+
+#define		bNoiseLvlTopSet		0x3	/* Useless */
+#define		bChSmooth			0x4
+#define		bChSmoothCfg1		0x38
+#define		bChSmoothCfg2		0x1c0
+#define		bChSmoothCfg3		0xe00
+#define		bChSmoothCfg4		0x7000
+#define		bMRCMode			0x800000
+#define		bTHEVMCfg			0x7000000
+
+#define		bLoopFitType		0x1	/* Useless */
+#define		bUpdCFO			0x40
+#define		bUpdCFOOffData		0x80
+#define		bAdvUpdCFO			0x100
+#define		bAdvTimeCtrl		0x800
+#define		bUpdClko			0x1000
+#define		bFC					0x6000
+#define		bTrackingMode		0x8000
+#define		bPhCmpEnable		0x10000
+#define		bUpdClkoLTF		0x20000
+#define		bComChCFO			0x40000
+#define		bCSIEstiMode		0x80000
+#define		bAdvUpdEqz			0x100000
+#define		bUChCfg				0x7000000
+#define		bUpdEqz			0x8000000
+
+/* Rx Pseduo noise */
+#define		bRxPesudoNoiseOn		0x20000000	/* Useless */
+#define		bRxPesudoNoise_A		0xff
+#define		bRxPesudoNoise_B		0xff00
+#define		bRxPesudoNoise_C		0xff0000
+#define		bRxPesudoNoise_D		0xff000000
+#define		bPesudoNoiseState_A	0xffff
+#define		bPesudoNoiseState_B	0xffff0000
+#define		bPesudoNoiseState_C	0xffff
+#define		bPesudoNoiseState_D	0xffff0000
+
+/* 7. RF Register
+ * Zebra1 */
+#define		bZebra1_HSSIEnable		0x8		/* Useless */
+#define		bZebra1_TRxControl		0xc00
+#define		bZebra1_TRxGainSetting	0x07f
+#define		bZebra1_RxCorner		0xc00
+#define		bZebra1_TxChargePump	0x38
+#define		bZebra1_RxChargePump	0x7
+#define		bZebra1_ChannelNum	0xf80
+#define		bZebra1_TxLPFBW		0x400
+#define		bZebra1_RxLPFBW		0x600
+
+/* Zebra4 */
+#define		bRTL8256RegModeCtrl1	0x100	/* Useless */
+#define		bRTL8256RegModeCtrl0	0x40
+#define		bRTL8256_TxLPFBW		0x18
+#define		bRTL8256_RxLPFBW		0x600
+
+/* RTL8258 */
+#define		bRTL8258_TxLPFBW		0xc	/* Useless */
+#define		bRTL8258_RxLPFBW		0xc00
+#define		bRTL8258_RSSILPFBW	0xc0
+
+
+/*
+ * Other Definition
+ *   */
+
+/* byte endable for sb_write */
+#define		bByte0				0x1	/* Useless */
+#define		bByte1				0x2
+#define		bByte2				0x4
+#define		bByte3				0x8
+#define		bWord0				0x3
+#define		bWord1				0xc
+#define		bDWord				0xf
+
+/* for PutRegsetting & GetRegSetting BitMask */
+#define		bMaskByte0			0xff	/* Reg 0xc50 rOFDM0_XAAGCCore~0xC6f */
+#define		bMaskByte1			0xff00
+#define		bMaskByte2			0xff0000
+#define		bMaskByte3			0xff000000
+#define		bMaskHWord		0xffff0000
+#define		bMaskLWord			0x0000ffff
+#define		bMaskDWord		0xffffffff
+#define		bMaskH3Bytes		0xffffff00
+#define		bMask12Bits			0xfff
+#define		bMaskH4Bits			0xf0000000
+#define		bMaskOFDM_D		0xffc00000
+#define		bMaskCCK			0x3f3f3f3f
+
+
+#define		bEnable			0x1	/* Useless */
+#define		bDisable		0x0
+
+#define		LeftAntenna		0x0	/* Useless */
+#define		RightAntenna	0x1
+
+#define		tCheckTxStatus		500   /* 500ms // Useless */
+#define		tUpdateRxCounter	100   /* 100ms */
+
+#define		rateCCK		0	/* Useless */
+#define		rateOFDM	1
+#define		rateHT		2
+
+/* define Register-End */
+#define		bPMAC_End			0x1ff	/* Useless */
+#define		bFPGAPHY0_End		0x8ff
+#define		bFPGAPHY1_End		0x9ff
+#define		bCCKPHY0_End		0xaff
+#define		bOFDMPHY0_End		0xcff
+#define		bOFDMPHY1_End		0xdff
+
+/* define max debug item in each debug page
+ * #define bMaxItem_FPGA_PHY0        0x9
+ * #define bMaxItem_FPGA_PHY1        0x3
+ * #define bMaxItem_PHY_11B          0x16
+ * #define bMaxItem_OFDM_PHY0        0x29
+ * #define bMaxItem_OFDM_PHY1        0x0 */
+
+#define		bPMACControl		0x0		/* Useless */
+#define		bWMACControl		0x1
+#define		bWNICControl		0x2
+
+#define		PathA			0x0	/* Useless */
+#define		PathB			0x1
+#define		PathC			0x2
+#define		PathD			0x3
+
+#endif
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/include/Hal8723DPwrSeq.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/Hal8723DPwrSeq.h
--- linux-5.6.3/3rdparty/rtl8821ce/include/Hal8723DPwrSeq.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/Hal8723DPwrSeq.h	2020-04-10 16:35:06.845661421 +0300
@@ -0,0 +1,206 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2016 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#ifndef REALTEK_POWER_SEQUENCE_8723D
+#define REALTEK_POWER_SEQUENCE_8723D
+
+/* #include "PwrSeqCmd.h" */
+#include "HalPwrSeqCmd.h"
+
+/*
+	Check document WM-20110607-Paul-RTL8192e_Power_Architecture-R02.vsd
+	There are 6 HW Power States:
+	0: POFF--Power Off
+	1: PDN--Power Down
+	2: CARDEMU--Card Emulation
+	3: ACT--Active Mode
+	4: LPS--Low Power State
+	5: SUS--Suspend
+
+	The transition from different states are defined below
+	TRANS_CARDEMU_TO_ACT
+	TRANS_ACT_TO_CARDEMU
+	TRANS_CARDEMU_TO_SUS
+	TRANS_SUS_TO_CARDEMU
+	TRANS_CARDEMU_TO_PDN
+	TRANS_ACT_TO_LPS
+	TRANS_LPS_TO_ACT
+
+	TRANS_END
+*/
+#define	RTL8723D_TRANS_CARDEMU_TO_ACT_STEPS	27
+#define	RTL8723D_TRANS_ACT_TO_CARDEMU_STEPS	8
+#define	RTL8723D_TRANS_CARDEMU_TO_SUS_STEPS	7
+#define	RTL8723D_TRANS_SUS_TO_CARDEMU_STEPS	5
+#define	RTL8723D_TRANS_CARDEMU_TO_CARDDIS_STEPS	8
+#define	RTL8723D_TRANS_CARDDIS_TO_CARDEMU_STEPS	7
+#define	RTL8723D_TRANS_CARDEMU_TO_PDN_STEPS	4
+#define	RTL8723D_TRANS_PDN_TO_CARDEMU_STEPS	1
+#define	RTL8723D_TRANS_ACT_TO_LPS_STEPS		13
+#define	RTL8723D_TRANS_LPS_TO_ACT_STEPS		11
+#define	RTL8723D_TRANS_END_STEPS	1
+
+
+#define RTL8723D_TRANS_CARDEMU_TO_ACT														\
+	/* format */																\
+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, / comments here*/								\
+	{0x0020, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), BIT(0)}, /*0x20[0] = 1b'1 enable LDOA12 MACRO block for all interface*/	\
+	{0x0001, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_DELAY, 1, PWRSEQ_DELAY_MS},/*Delay 1ms*/   \
+	{0x0000, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(5), 0}, /*0x00[5] = 1b'0 release analog Ips to digital ,1:isolation*/	\
+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, (BIT(4) | BIT(3) | BIT2), 0},/* disable SW LPS 0x04[10]=0 and WLSUS_EN 0x04[11]=0*/ \
+	{0x0075, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0) , BIT(0)},/* Disable USB suspend */	\
+	{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT(1), BIT(1)},/* wait till 0x04[17] = 1    power ready*/	\
+	{0x0075, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0) , 0},/* Enable USB suspend */	\
+	{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), BIT(0)},/* release WLON reset  0x04[16]=1*/ \
+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, (BIT(1) | BIT(0)), 0}, \
+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(7), 0},/* disable HWPDN 0x04[15]=0*/	\
+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, (BIT(4) | BIT(3)), 0},/* disable WL suspend*/ \
+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), BIT(0)},/* polling until return 0*/ \
+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT(0), 0},/**/ \
+	{0x0010, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(6), BIT(6)},/* Enable WL control XTAL setting*/ \
+	{0x0049, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1), BIT(1)},/*Enable falling edge triggering interrupt*/\
+	{0x0063, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1), BIT(1)},/*Enable GPIO9 interrupt mode*/\
+	{0x0062, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1), 0},/*Enable GPIO9 input mode*/\
+	{0x0058, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), BIT(0)},/*Enable HSISR GPIO[C:0] interrupt*/\
+	{0x005A, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1), BIT(1)},/*Enable HSISR GPIO9 interrupt*/\
+	{0x0068, PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3), BIT(3)},/*For GPIO9 internal pull high setting by test chip*/\
+	{0x0069, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(6), BIT(6)},/*For GPIO9 internal pull high setting*/\
+	{0x001f, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x00},/*reset RF path S1*/\
+	{0x0077, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x00},/*reset RF path S0*/\
+	{0x001f, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x07},/*enable RF path S1*/\
+	{0x0077, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x07},/*enalbe RF path S0*/\
+
+
+#define RTL8723D_TRANS_ACT_TO_CARDEMU													\
+	/* format */																\
+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, / comments here*/								\
+	/*{0x001F, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0}, */ /*0x1F[7:0] = 0 turn off RF*/	\
+	{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), 0}, /*0x2[0]=0 Reset BB, RF enter Power Down mode*/ \
+	{0x0049, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1), 0},/*Enable rising edge triggering interrupt*/ \
+	{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), BIT(0)},/* release WLON reset  0x04[16]=1*/ \
+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1), BIT(1)}, /*0x04[9] = 1 turn off MAC by HW state machine*/	\
+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT(1), 0}, /*wait till 0x04[9] = 0 polling until return 0 to disable*/ \
+	{0x0010, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(6), 0},/* Enable BT control XTAL setting*/\
+	{0x0000, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(5), BIT(5)}, /*0x00[5] = 1b'1 analog Ips to digital ,1:isolation*/   \
+	{0x0020, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), 0}, /*0x20[0] = 1b'0 disable LDOA12 MACRO block*/\
+
+
+#define RTL8723D_TRANS_CARDEMU_TO_SUS													\
+	/* format */																\
+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, / comments here*/								\
+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4) | BIT(3), (BIT4 | BIT3)}, /*0x04[12:11] = 2b'11 enable WL suspend for PCIe*/ \
+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3) | BIT(4), BIT3}, /*0x04[12:11] = 2b'01 enable WL suspend*/	\
+	{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), BIT(4)}, /*0x23[4] = 1b'1 12H LDO enter sleep mode*/	\
+	{0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x20}, /*0x07[7:0] = 0x20 SDIO SOP option to disable BG/MB/ACK/SWR*/   \
+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3) | BIT(4), BIT3 | BIT4}, /*0x04[12:11] = 2b'11 enable WL suspend for PCIe*/	\
+	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT(0), BIT(0)}, /*Set SDIO suspend local register*/	\
+	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT(1), 0}, /*wait power state to suspend*/
+
+#define RTL8723D_TRANS_SUS_TO_CARDEMU													\
+	/* format */																\
+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, / comments here*/								\
+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3) | BIT(7), 0}, /*clear suspend enable and power down enable*/ \
+	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT(0), 0}, /*Set SDIO suspend local register*/ \
+	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT(1), BIT(1)}, /*wait power state to suspend*/\
+	{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), 0}, /*0x23[4] = 1b'0 12H LDO enter normal mode*/   \
+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3) | BIT(4), 0}, /*0x04[12:11] = 2b'01enable WL suspend*/
+
+
+#define RTL8723D_TRANS_CARDEMU_TO_CARDDIS													\
+	/* format */																\
+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, / comments here*/	\
+	{0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x20}, /*0x07 = 0x20 , SOP option to disable BG/MB*/	\
+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3) | BIT(4), BIT3}, /*0x04[12:11] = 2b'01 enable WL suspend*/	\
+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(2), BIT(2)}, /*0x04[10] = 1, enable SW LPS*/	\
+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3) | BIT(4), BIT3 | BIT4}, /*0x04[12:11] = 2b'11 enable WL suspend*/	\
+	{0x004A, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), 1}, /*0x48[16] = 1 to enable GPIO9 as EXT WAKEUP*/   \
+	{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), BIT(4)}, /*0x23[4] = 1b'1 12H LDO enter sleep mode*/	\
+	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT(0), BIT(0)}, /*Set SDIO suspend local register*/	\
+	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT(1), 0}, /*wait power state to suspend*/
+
+#define RTL8723D_TRANS_CARDDIS_TO_CARDEMU													\
+	/* format */																\
+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, / comments here*/								\
+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3) | BIT(7), 0}, /*clear suspend enable and power down enable*/ \
+	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT(0), 0}, /*Set SDIO suspend local register*/ \
+	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT(1), BIT(1)}, /*wait power state to suspend*/\
+	{0x004A, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), 0}, /*0x48[16] = 0 to disable GPIO9 as EXT WAKEUP*/	\
+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3) | BIT(4), 0}, /*0x04[12:11] = 2b'01enable WL suspend*/\
+	{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), 0}, /*0x23[4] = 1b'0 12H LDO enter normal mode*/   \
+	{0x0301, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0},/*PCIe DMA start*/
+
+
+#define RTL8723D_TRANS_CARDEMU_TO_PDN												\
+	/* format */																\
+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, / comments here*/								\
+	{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), BIT(4)}, /*0x23[4] = 1b'1 12H LDO enter sleep mode*/	\
+	{0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK | PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x20}, /*0x07[7:0] = 0x20 SOP option to disable BG/MB/ACK/SWR*/   \
+	{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), 0},/* 0x04[16] = 0*/\
+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(7), BIT(7)},/* 0x04[15] = 1*/
+
+#define RTL8723D_TRANS_PDN_TO_CARDEMU												\
+	/* format */																\
+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, / comments here*/								\
+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(7), 0},/* 0x04[15] = 0*/
+
+#define RTL8723D_TRANS_ACT_TO_LPS														\
+	/* format */																\
+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, / comments here*/								\
+	{0x0301, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF},/*PCIe DMA stop*/	\
+	{0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF},/*Tx Pause*/	\
+	{0x05F8, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/	\
+	{0x05F9, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/	\
+	{0x05FA, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/	\
+	{0x05FB, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/	\
+	{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), 0},/*CCK and OFDM are disabled, and clock are gated*/	\
+	{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_US},/*Delay 1us*/	\
+	{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1), 0},/*Whole BB is reset*/	\
+	{0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x03},/*Reset MAC TRX*/	\
+	{0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1), 0},/*check if removed later*/ \
+	{0x0093, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x00},/*When driver enter Sus/ Disable, enable LOP for BT*/	\
+	{0x0553, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(5), BIT(5)},/*Respond TxOK to scheduler*/	\
+
+
+#define RTL8723D_TRANS_LPS_TO_ACT															\
+	/* format */																\
+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, / comments here*/								\
+	{0x0080, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, 0xFF, 0x84}, /*SDIO RPWM*/\
+	{0xFE58, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x84}, /*USB RPWM*/\
+	{0x0361, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x84}, /*PCIe RPWM*/\
+	{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_MS}, /*Delay*/\
+	{0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), 0}, /*.	0x08[4] = 0  switch TSF to 40M*/\
+	{0x0109, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT(7), 0}, /*Polling 0x109[7]=0  TSF in 40M*/\
+	{0x0029, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(6) | BIT(7), 0}, /*.	0x29[7:6] = 2b'00	 enable BB clock*/\
+	{0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1), BIT(1)}, /*.	0x101[1] = 1*/\
+	{0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF}, /*.	0x100[7:0] = 0xFF	 enable WMAC TRX*/\
+	{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1) | BIT(0), BIT1 | BIT0}, /*.	0x02[1:0] = 2b'11	 enable BB macro*/\
+	{0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0}, /*.	0x522 = 0*/
+
+#define RTL8723D_TRANS_END															\
+	/* format */																\
+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, / comments here*/								\
+	{0xFFFF, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, 0, PWR_CMD_END, 0, 0},
+
+
+	extern WLAN_PWR_CFG rtl8723D_power_on_flow[RTL8723D_TRANS_CARDEMU_TO_ACT_STEPS + RTL8723D_TRANS_END_STEPS];
+	extern WLAN_PWR_CFG rtl8723D_radio_off_flow[RTL8723D_TRANS_ACT_TO_CARDEMU_STEPS + RTL8723D_TRANS_END_STEPS];
+	extern WLAN_PWR_CFG rtl8723D_card_disable_flow[RTL8723D_TRANS_ACT_TO_CARDEMU_STEPS + RTL8723D_TRANS_CARDEMU_TO_CARDDIS_STEPS + RTL8723D_TRANS_END_STEPS];
+	extern WLAN_PWR_CFG rtl8723D_card_enable_flow[RTL8723D_TRANS_CARDDIS_TO_CARDEMU_STEPS + RTL8723D_TRANS_CARDEMU_TO_ACT_STEPS + RTL8723D_TRANS_END_STEPS];
+	extern WLAN_PWR_CFG rtl8723D_suspend_flow[RTL8723D_TRANS_ACT_TO_CARDEMU_STEPS + RTL8723D_TRANS_CARDEMU_TO_SUS_STEPS + RTL8723D_TRANS_END_STEPS];
+	extern WLAN_PWR_CFG rtl8723D_resume_flow[RTL8723D_TRANS_SUS_TO_CARDEMU_STEPS + RTL8723D_TRANS_CARDEMU_TO_ACT_STEPS + RTL8723D_TRANS_END_STEPS];
+	extern WLAN_PWR_CFG rtl8723D_hwpdn_flow[RTL8723D_TRANS_ACT_TO_CARDEMU_STEPS + RTL8723D_TRANS_CARDEMU_TO_PDN_STEPS + RTL8723D_TRANS_END_STEPS];
+	extern WLAN_PWR_CFG rtl8723D_enter_lps_flow[RTL8723D_TRANS_ACT_TO_LPS_STEPS + RTL8723D_TRANS_END_STEPS];
+	extern WLAN_PWR_CFG rtl8723D_leave_lps_flow[RTL8723D_TRANS_LPS_TO_ACT_STEPS + RTL8723D_TRANS_END_STEPS];
+
+#endif
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/include/Hal8723PwrSeq.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/Hal8723PwrSeq.h
--- linux-5.6.3/3rdparty/rtl8821ce/include/Hal8723PwrSeq.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/Hal8723PwrSeq.h	2020-04-10 16:35:06.845661421 +0300
@@ -0,0 +1,183 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2016 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#ifndef __HAL8723PWRSEQ_H__
+#define __HAL8723PWRSEQ_H__
+/*
+	Check document WM-20110607-Paul-RTL8723A_Power_Architecture-R02.vsd
+	There are 6 HW Power States:
+	0: POFF--Power Off
+	1: PDN--Power Down
+	2: CARDEMU--Card Emulation
+	3: ACT--Active Mode
+	4: LPS--Low Power State
+	5: SUS--Suspend
+
+	The transision from different states are defined below
+	TRANS_CARDEMU_TO_ACT
+	TRANS_ACT_TO_CARDEMU
+	TRANS_CARDEMU_TO_SUS
+	TRANS_SUS_TO_CARDEMU
+	TRANS_CARDEMU_TO_PDN
+	TRANS_ACT_TO_LPS
+	TRANS_LPS_TO_ACT
+
+	TRANS_END
+*/
+#include "HalPwrSeqCmd.h"
+
+#define	RTL8723A_TRANS_CARDEMU_TO_ACT_STEPS	15
+#define	RTL8723A_TRANS_ACT_TO_CARDEMU_STEPS	15
+#define	RTL8723A_TRANS_CARDEMU_TO_SUS_STEPS	15
+#define	RTL8723A_TRANS_SUS_TO_CARDEMU_STEPS	15
+#define	RTL8723A_TRANS_CARDEMU_TO_PDN_STEPS	15
+#define	RTL8723A_TRANS_PDN_TO_CARDEMU_STEPS	15
+#define	RTL8723A_TRANS_ACT_TO_LPS_STEPS	15
+#define	RTL8723A_TRANS_LPS_TO_ACT_STEPS	15
+#define	RTL8723A_TRANS_END_STEPS	1
+
+
+#define RTL8723A_TRANS_CARDEMU_TO_ACT														\
+	/* format */																\
+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
+	{0x0020, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0}, /*0x20[0] = 1b'1 enable LDOA12 MACRO block for all interface*/   \
+	{0x0067, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0}, /*0x67[0] = 0 to disable BT_GPS_SEL pins*/	\
+	{0x0001, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_DELAY, 1, PWRSEQ_DELAY_MS},/*Delay 1ms*/   \
+	{0x0000, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT5, 0}, /*0x00[5] = 1b'0 release analog Ips to digital ,1:isolation*/   \
+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, 0},/* disable SW LPS 0x04[10]=0*/	\
+	{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT1, BIT1},/* wait till 0x04[17] = 1    power ready*/	\
+	{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0},/* release WLON reset  0x04[16]=1*/	\
+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, 0},/* disable HWPDN 0x04[15]=0*/	\
+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, (BIT4 | BIT3), 0},/* disable WL suspend*/	\
+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0},/* polling until return 0*/	\
+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT0, 0},/**/	\
+	{0x004E, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, 1},/*0x4C[23] = 0x4E[7] = 1, switch DPDT_SEL_P output from WL BB */\
+
+#define RTL8723A_TRANS_ACT_TO_CARDEMU													\
+	/* format */																\
+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
+	{0x001F, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0},/*0x1F[7:0] = 0 turn off RF*/	\
+	{0x004E, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, 0},/*0x4C[23] = 0x4E[7] = 0, switch DPDT_SEL_P output from register 0x65[2] */\
+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1}, /*0x04[9] = 1 turn off MAC by HW state machine*/	\
+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT1, 0}, /*wait till 0x04[9] = 0 polling until return 0 to disable*/	\
+	{0x0000, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT5, BIT5}, /*0x00[5] = 1b'1 analog Ips to digital ,1:isolation*/   \
+	{0x0020, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0}, /*0x20[0] = 1b'0 disable LDOA12 MACRO block*/   \
+
+
+#define RTL8723A_TRANS_CARDEMU_TO_SUS													\
+	/* format */																\
+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4 | BIT3, (BIT4 | BIT3)}, /*0x04[12:11] = 2b'11 enable WL suspend for PCIe*/	\
+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT4, BIT3}, /*0x04[12:11] = 2b'01 enable WL suspend*/	\
+	{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, BIT4}, /*0x23[4] = 1b'1 12H LDO enter sleep mode*/   \
+	{0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x20}, /*0x07[7:0] = 0x20 SDIO SOP option to disable BG/MB/ACK/SWR*/   \
+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT4, BIT3 | BIT4}, /*0x04[12:11] = 2b'11 enable WL suspend for PCIe*/	\
+	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT0, BIT0}, /*Set SDIO suspend local register*/	\
+	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, 0}, /*wait power state to suspend*/
+
+#define RTL8723A_TRANS_SUS_TO_CARDEMU													\
+	/* format */																\
+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT7, 0}, /*clear suspend enable and power down enable*/	\
+	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT0, 0}, /*Set SDIO suspend local register*/	\
+	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, BIT1}, /*wait power state to suspend*/\
+	{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0}, /*0x23[4] = 1b'0 12H LDO enter normal mode*/   \
+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT4, 0}, /*0x04[12:11] = 2b'01enable WL suspend*/
+
+#define RTL8723A_TRANS_CARDEMU_TO_CARDDIS													\
+	/* format */																\
+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
+	{0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x20}, /*0x07 = 0x20 , SOP option to disable BG/MB*/	\
+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT4, BIT3}, /*0x04[12:11] = 2b'01 enable WL suspend*/	\
+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, BIT2}, /*0x04[10] = 1, enable SW LPS*/	\
+	{0x004A, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 1}, /*0x48[16] = 1 to enable GPIO9 as EXT WAKEUP*/   \
+	{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, BIT4}, /*0x23[4] = 1b'1 12H LDO enter sleep mode*/   \
+	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT0, BIT0}, /*Set SDIO suspend local register*/	\
+	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, 0}, /*wait power state to suspend*/
+
+#define RTL8723A_TRANS_CARDDIS_TO_CARDEMU													\
+	/* format */																\
+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT7, 0}, /*clear suspend enable and power down enable*/	\
+	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT0, 0}, /*Set SDIO suspend local register*/	\
+	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, BIT1}, /*wait power state to suspend*/\
+	{0x004A, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0}, /*0x48[16] = 0 to disable GPIO9 as EXT WAKEUP*/   \
+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT4, 0}, /*0x04[12:11] = 2b'01enable WL suspend*/\
+	{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0}, /*0x23[4] = 1b'0 12H LDO enter normal mode*/   \
+	{0x0301, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0},/*PCIe DMA start*/
+
+
+#define RTL8723A_TRANS_CARDEMU_TO_PDN												\
+	/* format */																\
+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
+	{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, BIT4}, /*0x23[4] = 1b'1 12H LDO enter sleep mode*/   \
+	{0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK | PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x20}, /*0x07[7:0] = 0x20 SOP option to disable BG/MB/ACK/SWR*/   \
+	{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0},/* 0x04[16] = 0*/\
+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, BIT7},/* 0x04[15] = 1*/
+
+#define RTL8723A_TRANS_PDN_TO_CARDEMU												\
+	/* format */																\
+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, 0},/* 0x04[15] = 0*/
+
+#define RTL8723A_TRANS_ACT_TO_LPS														\
+	/* format */																\
+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
+	{0x0301, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF},/*PCIe DMA stop*/	\
+	{0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF},/*Tx Pause*/	\
+	{0x05F8, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/	\
+	{0x05F9, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/	\
+	{0x05FA, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/	\
+	{0x05FB, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/	\
+	{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0},/*CCK and OFDM are disabled, and clock are gated*/	\
+	{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_US},/*Delay 1us*/	\
+	{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0},/*Whole BB is reset*/	\
+	{0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x03},/*Reset MAC TRX*/	\
+	{0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0},/*check if removed later*/	\
+	{0x0093, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x00},/*When driver enter Sus/ Disable, enable LOP for BT*/	\
+	{0x0553, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT5, BIT5},/*Respond TxOK to scheduler*/	\
+
+
+#define RTL8723A_TRANS_LPS_TO_ACT															\
+	/* format */																\
+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
+	{0x0080, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, 0xFF, 0x84}, /*SDIO RPWM*/\
+	{0xFE58, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x84}, /*USB RPWM*/\
+	{0x0361, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x84}, /*PCIe RPWM*/\
+	{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_MS}, /*Delay*/\
+	{0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0}, /*.	0x08[4] = 0		 switch TSF to 40M*/\
+	{0x0109, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT7, 0}, /*Polling 0x109[7]=0  TSF in 40M*/\
+	{0x0029, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT6 | BIT7, 0}, /*.	0x29[7:6] = 2b'00	 enable BB clock*/\
+	{0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1}, /*.	0x101[1] = 1*/\
+	{0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF}, /*.	0x100[7:0] = 0xFF	 enable WMAC TRX*/\
+	{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1 | BIT0, BIT1 | BIT0}, /*.	0x02[1:0] = 2b'11	 enable BB macro*/\
+	{0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0}, /*.	0x522 = 0*/
+
+#define RTL8723A_TRANS_END															\
+	/* format */																\
+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
+	{0xFFFF, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, 0, PWR_CMD_END, 0, 0},
+
+
+	extern WLAN_PWR_CFG rtl8723A_power_on_flow[RTL8723A_TRANS_CARDEMU_TO_ACT_STEPS + RTL8723A_TRANS_END_STEPS];
+	extern WLAN_PWR_CFG rtl8723A_radio_off_flow[RTL8723A_TRANS_ACT_TO_CARDEMU_STEPS + RTL8723A_TRANS_END_STEPS];
+	extern WLAN_PWR_CFG rtl8723A_card_disable_flow[RTL8723A_TRANS_ACT_TO_CARDEMU_STEPS + RTL8723A_TRANS_CARDEMU_TO_PDN_STEPS + RTL8723A_TRANS_END_STEPS];
+	extern WLAN_PWR_CFG rtl8723A_card_enable_flow[RTL8723A_TRANS_ACT_TO_CARDEMU_STEPS + RTL8723A_TRANS_CARDEMU_TO_PDN_STEPS + RTL8723A_TRANS_END_STEPS];
+	extern WLAN_PWR_CFG rtl8723A_suspend_flow[RTL8723A_TRANS_ACT_TO_CARDEMU_STEPS + RTL8723A_TRANS_CARDEMU_TO_SUS_STEPS + RTL8723A_TRANS_END_STEPS];
+	extern WLAN_PWR_CFG rtl8723A_resume_flow[RTL8723A_TRANS_ACT_TO_CARDEMU_STEPS + RTL8723A_TRANS_CARDEMU_TO_SUS_STEPS + RTL8723A_TRANS_END_STEPS];
+	extern WLAN_PWR_CFG rtl8723A_hwpdn_flow[RTL8723A_TRANS_ACT_TO_CARDEMU_STEPS + RTL8723A_TRANS_CARDEMU_TO_PDN_STEPS + RTL8723A_TRANS_END_STEPS];
+	extern WLAN_PWR_CFG rtl8723A_enter_lps_flow[RTL8723A_TRANS_ACT_TO_LPS_STEPS + RTL8723A_TRANS_END_STEPS];
+	extern WLAN_PWR_CFG rtl8723A_leave_lps_flow[RTL8723A_TRANS_LPS_TO_ACT_STEPS + RTL8723A_TRANS_END_STEPS];
+
+#endif
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/include/Hal8812PhyCfg.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/Hal8812PhyCfg.h
--- linux-5.6.3/3rdparty/rtl8821ce/include/Hal8812PhyCfg.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/Hal8812PhyCfg.h	2020-04-10 16:35:06.845661421 +0300
@@ -0,0 +1,143 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#ifndef __INC_HAL8812PHYCFG_H__
+#define __INC_HAL8812PHYCFG_H__
+
+
+/*--------------------------Define Parameters-------------------------------*/
+#define LOOP_LIMIT				5
+#define MAX_STALL_TIME			50		/* us */
+#define AntennaDiversityValue	0x80	/* (Adapter->bSoftwareAntennaDiversity ? 0x00 : 0x80) */
+#define MAX_TXPWR_IDX_NMODE_92S	63
+#define Reset_Cnt_Limit			3
+
+
+#ifdef CONFIG_PCI_HCI
+	#define MAX_AGGR_NUM	0x0B
+#else
+	#define MAX_AGGR_NUM	0x07
+#endif /* CONFIG_PCI_HCI */
+
+
+/*--------------------------Define Parameters-------------------------------*/
+
+/*------------------------------Define structure----------------------------*/
+
+
+/* BB/RF related */
+
+/*------------------------------Define structure----------------------------*/
+
+
+/*------------------------Export global variable----------------------------*/
+/*------------------------Export global variable----------------------------*/
+
+
+/*------------------------Export Marco Definition---------------------------*/
+/*------------------------Export Marco Definition---------------------------*/
+
+
+/*--------------------------Exported Function prototype---------------------*/
+/*
+ * BB and RF register read/write
+ *   */
+u32	PHY_QueryBBReg8812(IN	PADAPTER	Adapter,
+			   IN	u32			RegAddr,
+			   IN	u32			BitMask);
+void	PHY_SetBBReg8812(IN	PADAPTER		Adapter,
+			 IN	u32			RegAddr,
+			 IN	u32			BitMask,
+			 IN	u32			Data);
+u32	PHY_QueryRFReg8812(IN	PADAPTER	Adapter,
+			   IN	enum rf_path	eRFPath,
+			   IN	u32			RegAddr,
+			   IN	u32			BitMask);
+void	PHY_SetRFReg8812(IN	PADAPTER		Adapter,
+			 IN	enum rf_path	eRFPath,
+			 IN	u32			RegAddr,
+			 IN	u32			BitMask,
+			 IN	u32			Data);
+
+/*
+ * Initialization related function
+ *
+ * MAC/BB/RF HAL config */
+int	PHY_MACConfig8812(IN PADAPTER	Adapter);
+int	PHY_BBConfig8812(IN PADAPTER	Adapter);
+void	PHY_BB8812_Config_1T(IN PADAPTER	Adapter);
+int	PHY_RFConfig8812(IN PADAPTER	Adapter);
+
+/* RF config */
+
+s32
+PHY_SwitchWirelessBand8812(
+	IN PADAPTER		Adapter,
+	IN u8			Band
+);
+
+/*
+ * BB TX Power R/W
+ *   */
+void	PHY_GetTxPowerLevel8812(IN PADAPTER	Adapter, OUT s32	*powerlevel);
+void	PHY_SetTxPowerLevel8812(IN PADAPTER	Adapter, IN u8	Channel);
+
+BOOLEAN	PHY_UpdateTxPowerDbm8812(IN PADAPTER	Adapter, IN int	powerInDbm);
+u8 PHY_GetTxPowerIndex_8812A(
+	IN	PADAPTER			pAdapter,
+	IN	enum rf_path			RFPath,
+	IN	u8					Rate,
+	IN	u8					BandWidth,
+	IN	u8					Channel,
+	struct txpwr_idx_comp *tic
+);
+
+u32 phy_get_tx_bb_swing_8812a(
+	IN	PADAPTER	Adapter,
+	IN	BAND_TYPE	Band,
+	IN	enum rf_path	RFPath
+);
+
+VOID
+PHY_SetTxPowerIndex_8812A(
+	IN	PADAPTER		Adapter,
+	IN	u32				PowerIndex,
+	IN	enum rf_path		RFPath,
+	IN	u8				Rate
+);
+
+/*
+ * channel switch related funciton
+ *   */
+VOID
+PHY_SetSwChnlBWMode8812(
+	IN	PADAPTER			Adapter,
+	IN	u8					channel,
+	IN	enum channel_width	Bandwidth,
+	IN	u8					Offset40,
+	IN	u8					Offset80
+);
+
+/*
+ * BB/MAC/RF other monitor API
+ *   */
+
+VOID
+phy_set_rf_path_switch_8812a(
+	IN	struct dm_struct		*phydm,
+	IN	bool		bMain
+);
+
+/*--------------------------Exported Function prototype---------------------*/
+#endif /* __INC_HAL8192CPHYCFG_H */
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/include/Hal8812PhyReg.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/Hal8812PhyReg.h
--- linux-5.6.3/3rdparty/rtl8821ce/include/Hal8812PhyReg.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/Hal8812PhyReg.h	2020-04-10 16:35:06.845661421 +0300
@@ -0,0 +1,735 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#ifndef __INC_HAL8812PHYREG_H__
+#define __INC_HAL8812PHYREG_H__
+/*--------------------------Define Parameters-------------------------------*/
+/*
+ * BB-PHY register PMAC 0x100 PHY 0x800 - 0xEFF
+ * 1. PMAC duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF
+ * 2. 0x800/0x900/0xA00/0xC00/0xD00/0xE00
+ * 3. RF register 0x00-2E
+ * 4. Bit Mask for BB/RF register
+ * 5. Other defintion for BB/RF R/W
+ *   */
+
+
+/* BB Register Definition */
+
+#define rCCAonSec_Jaguar		0x838
+#define rPwed_TH_Jaguar			0x830
+
+/* BW and sideband setting */
+#define rBWIndication_Jaguar		0x834
+#define rL1PeakTH_Jaguar			0x848
+#define rFPGA0_XA_LSSIReadBack	0x8a0	/*Tranceiver LSSI Readback*/
+#define rRFMOD_Jaguar			0x8ac	/* RF mode */
+#define rADC_Buf_Clk_Jaguar		0x8c4
+#define rRFECTRL_Jaguar			0x900
+#define bRFMOD_Jaguar			0xc3
+#define rCCK_System_Jaguar		0xa00   /* for cck sideband */
+#define bCCK_System_Jaguar		0x10
+
+/* Block & Path enable */
+#define rOFDMCCKEN_Jaguar 		0x808 /* OFDM/CCK block enable */
+#define bOFDMEN_Jaguar			0x20000000
+#define bCCKEN_Jaguar			0x10000000
+#define rRxPath_Jaguar			0x808	/* Rx antenna */
+#define bRxPath_Jaguar			0xff
+#define rTxPath_Jaguar			0x80c	/* Tx antenna */
+#define bTxPath_Jaguar			0x0fffffff
+#define rCCK_RX_Jaguar			0xa04	/* for cck rx path selection */
+#define bCCK_RX_Jaguar			0x0c000000
+#define rVhtlen_Use_Lsig_Jaguar	0x8c3	/* Use LSIG for VHT length */
+
+/* RF read/write-related */
+#define rHSSIRead_Jaguar			0x8b0  /* RF read addr */
+#define bHSSIRead_addr_Jaguar		0xff
+#define bHSSIRead_trigger_Jaguar	0x100
+#define rA_PIRead_Jaguar			0xd04 /* RF readback with PI */
+#define rB_PIRead_Jaguar			0xd44 /* RF readback with PI */
+#define rA_SIRead_Jaguar			0xd08 /* RF readback with SI */
+#define rB_SIRead_Jaguar			0xd48 /* RF readback with SI */
+#define rRead_data_Jaguar			0xfffff
+#define rA_LSSIWrite_Jaguar			0xc90 /* RF write addr */
+#define rB_LSSIWrite_Jaguar			0xe90 /* RF write addr */
+#define bLSSIWrite_data_Jaguar		0x000fffff
+#define bLSSIWrite_addr_Jaguar		0x0ff00000
+
+
+
+/* YN: mask the following register definition temporarily */
+#define rFPGA0_XA_RFInterfaceOE			0x860	/* RF Channel switch */
+#define rFPGA0_XB_RFInterfaceOE			0x864
+
+#define rFPGA0_XAB_RFInterfaceSW		0x870	/* RF Interface Software Control */
+#define rFPGA0_XCD_RFInterfaceSW		0x874
+
+/* #define rFPGA0_XAB_RFParameter		0x878 */	/* RF Parameter
+ * #define rFPGA0_XCD_RFParameter		0x87c */
+
+/* #define rFPGA0_AnalogParameter1		0x880 */	/* Crystal cap setting RF-R/W protection for parameter4??
+ * #define rFPGA0_AnalogParameter2		0x884
+ * #define rFPGA0_AnalogParameter3		0x888
+ * #define rFPGA0_AdDaClockEn			0x888 */	/* enable ad/da clock1 for dual-phy
+ * #define rFPGA0_AnalogParameter4		0x88c */
+
+
+/* CCK TX scaling */
+#define rCCK_TxFilter1_Jaguar		0xa20
+#define bCCK_TxFilter1_C0_Jaguar	0x00ff0000
+#define bCCK_TxFilter1_C1_Jaguar		0xff000000
+#define rCCK_TxFilter2_Jaguar		0xa24
+#define bCCK_TxFilter2_C2_Jaguar		0x000000ff
+#define bCCK_TxFilter2_C3_Jaguar		0x0000ff00
+#define bCCK_TxFilter2_C4_Jaguar		0x00ff0000
+#define bCCK_TxFilter2_C5_Jaguar		0xff000000
+#define rCCK_TxFilter3_Jaguar		0xa28
+#define bCCK_TxFilter3_C6_Jaguar		0x000000ff
+#define bCCK_TxFilter3_C7_Jaguar		0x0000ff00
+
+
+/* YN: mask the following register definition temporarily
+ * #define rPdp_AntA					0xb00
+ * #define rPdp_AntA_4				0xb04
+ * #define rConfig_Pmpd_AntA			0xb28
+ * #define rConfig_AntA					0xb68
+ * #define rConfig_AntB					0xb6c
+ * #define rPdp_AntB					0xb70
+ * #define rPdp_AntB_4					0xb74
+ * #define rConfig_Pmpd_AntB			0xb98
+ * #define rAPK							0xbd8 */
+
+/* RXIQC */
+#define rA_RxIQC_AB_Jaguar    	0xc10  /* RxIQ imblance matrix coeff. A & B */
+#define rA_RxIQC_CD_Jaguar    	0xc14  /* RxIQ imblance matrix coeff. C & D */
+#define rA_TxScale_Jaguar 		0xc1c  /* Pah_A TX scaling factor */
+#define rB_TxScale_Jaguar 		0xe1c  /* Path_B TX scaling factor */
+#define rB_RxIQC_AB_Jaguar    	0xe10  /* RxIQ imblance matrix coeff. A & B */
+#define rB_RxIQC_CD_Jaguar    	0xe14  /* RxIQ imblance matrix coeff. C & D */
+#define b_RxIQC_AC_Jaguar		0x02ff  /* bit mask for IQC matrix element A & C */
+#define b_RxIQC_BD_Jaguar		0x02ff0000 /* bit mask for IQC matrix element A & C */
+
+
+/* DIG-related */
+#define rA_IGI_Jaguar				0xc50	/* Initial Gain for path-A */
+#define rB_IGI_Jaguar				0xe50	/* Initial Gain for path-B */
+#define rOFDM_FalseAlarm1_Jaguar	0xf48  /* counter for break */
+#define rOFDM_FalseAlarm2_Jaguar	0xf4c  /* counter for spoofing */
+#define rCCK_FalseAlarm_Jaguar        	0xa5c /* counter for cck false alarm */
+#define b_FalseAlarm_Jaguar			0xffff
+#define rCCK_CCA_Jaguar				0xa08	/* cca threshold */
+#define bCCK_CCA_Jaguar				0x00ff0000
+
+/* Tx Power Ttraining-related */
+#define rA_TxPwrTraing_Jaguar		0xc54
+#define rB_TxPwrTraing_Jaguar		0xe54
+
+/* Report-related */
+#define rOFDM_ShortCFOAB_Jaguar	0xf60
+#define rOFDM_LongCFOAB_Jaguar		0xf64
+#define rOFDM_EndCFOAB_Jaguar		0xf70
+#define rOFDM_AGCReport_Jaguar		0xf84
+#define rOFDM_RxSNR_Jaguar			0xf88
+#define rOFDM_RxEVMCSI_Jaguar		0xf8c
+#define rOFDM_SIGReport_Jaguar		0xf90
+
+/* Misc functions */
+#define rEDCCA_Jaguar				0x8a4 /* EDCCA */
+#define bEDCCA_Jaguar				0xffff
+#define rAGC_table_Jaguar			0x82c   /* AGC tabel select */
+#define bAGC_table_Jaguar			0x3
+#define b_sel5g_Jaguar    				0x1000 /* sel5g */
+#define b_LNA_sw_Jaguar				0x8000 /* HW/WS control for LNA */
+#define rFc_area_Jaguar				0x860   /* fc_area */
+#define bFc_area_Jaguar				0x1ffe000
+#define rSingleTone_ContTx_Jaguar	0x914
+
+/* RFE */
+#define rA_RFE_Pinmux_Jaguar	0xcb0  /* Path_A RFE cotrol pinmux */
+#define rB_RFE_Pinmux_Jaguar	0xeb0 /* Path_B RFE control pinmux */
+#define rA_RFE_Inv_Jaguar		0xcb4  /* Path_A RFE cotrol   */
+#define rB_RFE_Inv_Jaguar		0xeb4 /* Path_B RFE control */
+#define rA_RFE_Jaguar			0xcb8  /* Path_A RFE cotrol   */
+#define rB_RFE_Jaguar			0xeb8 /* Path_B RFE control */
+#define	rA_RFE_Inverse_Jaguar	0xCBC	/* Path_A RFE control inverse */
+#define	rB_RFE_Inverse_Jaguar	0xEBC	/* Path_B RFE control inverse */
+#define r_ANTSEL_SW_Jaguar		0x900 /* ANTSEL SW Control */
+#define bMask_RFEInv_Jaguar		0x3ff00000
+#define bMask_AntselPathFollow_Jaguar 0x00030000
+
+/* TX AGC */
+#define rTxAGC_A_CCK11_CCK1_JAguar				0xc20
+#define rTxAGC_A_Ofdm18_Ofdm6_JAguar				0xc24
+#define rTxAGC_A_Ofdm54_Ofdm24_JAguar			0xc28
+#define rTxAGC_A_MCS3_MCS0_JAguar					0xc2c
+#define rTxAGC_A_MCS7_MCS4_JAguar					0xc30
+#define rTxAGC_A_MCS11_MCS8_JAguar				0xc34
+#define rTxAGC_A_MCS15_MCS12_JAguar				0xc38
+#define rTxAGC_A_Nss1Index3_Nss1Index0_JAguar	0xc3c
+#define rTxAGC_A_Nss1Index7_Nss1Index4_JAguar	0xc40
+#define rTxAGC_A_Nss2Index1_Nss1Index8_JAguar	0xc44
+#define rTxAGC_A_Nss2Index5_Nss2Index2_JAguar	0xc48
+#define rTxAGC_A_Nss2Index9_Nss2Index6_JAguar	0xc4c
+#define rTxAGC_B_CCK11_CCK1_JAguar				0xe20
+#define rTxAGC_B_Ofdm18_Ofdm6_JAguar				0xe24
+#define rTxAGC_B_Ofdm54_Ofdm24_JAguar			0xe28
+#define rTxAGC_B_MCS3_MCS0_JAguar					0xe2c
+#define rTxAGC_B_MCS7_MCS4_JAguar					0xe30
+#define rTxAGC_B_MCS11_MCS8_JAguar				0xe34
+#define rTxAGC_B_MCS15_MCS12_JAguar				0xe38
+#define rTxAGC_B_Nss1Index3_Nss1Index0_JAguar		0xe3c
+#define rTxAGC_B_Nss1Index7_Nss1Index4_JAguar		0xe40
+#define rTxAGC_B_Nss2Index1_Nss1Index8_JAguar		0xe44
+#define rTxAGC_B_Nss2Index5_Nss2Index2_JAguar		0xe48
+#define rTxAGC_B_Nss2Index9_Nss2Index6_JAguar		0xe4c
+#define bTxAGC_byte0_Jaguar							0xff
+#define bTxAGC_byte1_Jaguar							0xff00
+#define bTxAGC_byte2_Jaguar							0xff0000
+#define bTxAGC_byte3_Jaguar							0xff000000
+
+/* IQK YN: temporaily mask this part
+ * #define rFPGA0_IQK					0xe28
+ * #define rTx_IQK_Tone_A				0xe30
+ * #define rRx_IQK_Tone_A				0xe34
+ * #define rTx_IQK_PI_A					0xe38
+ * #define rRx_IQK_PI_A					0xe3c */
+
+/* #define rTx_IQK						0xe40 */
+/* #define rRx_IQK						0xe44 */
+/* #define rIQK_AGC_Pts					0xe48 */
+/* #define rIQK_AGC_Rsp					0xe4c */
+/* #define rTx_IQK_Tone_B				0xe50 */
+/* #define rRx_IQK_Tone_B				0xe54 */
+/* #define rTx_IQK_PI_B					0xe58 */
+/* #define rRx_IQK_PI_B					0xe5c */
+/* #define rIQK_AGC_Cont				0xe60 */
+
+
+/* AFE-related */
+#define rA_AFEPwr1_Jaguar					0xc60 /* dynamic AFE power control */
+#define rA_AFEPwr2_Jaguar					0xc64 /* dynamic AFE power control */
+#define rA_Rx_WaitCCA_Tx_CCKRFON_Jaguar	0xc68
+#define rA_Tx_CCKBBON_OFDMRFON_Jaguar	0xc6c
+#define rA_Tx_OFDMBBON_Tx2Rx_Jaguar		0xc70
+#define rA_Tx2Tx_RXCCK_Jaguar				0xc74
+#define rA_Rx_OFDM_WaitRIFS_Jaguar			0xc78
+#define rA_Rx2Rx_BT_Jaguar					0xc7c
+#define rA_sleep_nav_Jaguar					0xc80
+#define rA_pmpd_Jaguar						0xc84
+#define rB_AFEPwr1_Jaguar					0xe60 /* dynamic AFE power control */
+#define rB_AFEPwr2_Jaguar					0xe64 /* dynamic AFE power control */
+#define rB_Rx_WaitCCA_Tx_CCKRFON_Jaguar	0xe68
+#define rB_Tx_CCKBBON_OFDMRFON_Jaguar	0xe6c
+#define rB_Tx_OFDMBBON_Tx2Rx_Jaguar		0xe70
+#define rB_Tx2Tx_RXCCK_Jaguar				0xe74
+#define rB_Rx_OFDM_WaitRIFS_Jaguar			0xe78
+#define rB_Rx2Rx_BT_Jaguar					0xe7c
+#define rB_sleep_nav_Jaguar					0xe80
+#define rB_pmpd_Jaguar						0xe84
+
+
+/* YN: mask these registers temporaily
+ * #define rTx_Power_Before_IQK_A		0xe94
+ * #define rTx_Power_After_IQK_A			0xe9c */
+
+/* #define rRx_Power_Before_IQK_A		0xea0 */
+/* #define rRx_Power_Before_IQK_A_2		0xea4 */
+/* #define rRx_Power_After_IQK_A			0xea8 */
+/* #define rRx_Power_After_IQK_A_2		0xeac */
+
+/* #define rTx_Power_Before_IQK_B		0xeb4 */
+/* #define rTx_Power_After_IQK_B			0xebc */
+
+/* #define rRx_Power_Before_IQK_B		0xec0 */
+/* #define rRx_Power_Before_IQK_B_2		0xec4 */
+/* #define rRx_Power_After_IQK_B			0xec8 */
+/* #define rRx_Power_After_IQK_B_2		0xecc */
+
+
+/* RSSI Dump */
+#define rA_RSSIDump_Jaguar			0xBF0
+#define rB_RSSIDump_Jaguar			0xBF1
+#define rS1_RXevmDump_Jaguar		0xBF4
+#define rS2_RXevmDump_Jaguar		0xBF5
+#define rA_RXsnrDump_Jaguar		0xBF6
+#define rB_RXsnrDump_Jaguar		0xBF7
+#define rA_CfoShortDump_Jaguar		0xBF8
+#define rB_CfoShortDump_Jaguar		0xBFA
+#define rA_CfoLongDump_Jaguar		0xBEC
+#define rB_CfoLongDump_Jaguar		0xBEE
+
+
+/* RF Register
+ *   */
+#define RF_AC_Jaguar				0x00	/*  */
+#define RF_RF_Top_Jaguar			0x07	/*  */
+#define RF_TXLOK_Jaguar				0x08	/*  */
+#define RF_TXAPK_Jaguar				0x0B
+#define RF_CHNLBW_Jaguar 			0x18	/* RF channel and BW switch */
+#define RF_RCK1_Jaguar				0x1c	/*  */
+#define RF_RCK2_Jaguar				0x1d
+#define RF_RCK3_Jaguar			0x1e
+#define RF_ModeTableAddr			0x30
+#define RF_ModeTableData0			0x31
+#define RF_ModeTableData1			0x32
+#define RF_TxLCTank_Jaguar	0x54
+#define RF_APK_Jaguar				0x63
+#define RF_LCK						0xB4
+#define RF_WeLut_Jaguar				0xEF
+
+#define bRF_CHNLBW_MOD_AG_Jaguar	0x70300
+#define bRF_CHNLBW_BW				0xc00
+
+
+/*
+ * RL6052 Register definition
+ *   */
+#define RF_AC						0x00	/*  */
+#define RF_IPA_A					0x0C	/*  */
+#define RF_TXBIAS_A					0x0D
+#define RF_BS_PA_APSET_G9_G11		0x0E
+#define RF_MODE1					0x10	/*  */
+#define RF_MODE2					0x11	/*  */
+#define RF_CHNLBW					0x18	/* RF channel and BW switch */
+#define RF_RCK_OS					0x30	/* RF TX PA control */
+#define RF_TXPA_G1					0x31	/* RF TX PA control */
+#define RF_TXPA_G2					0x32	/* RF TX PA control */
+#define RF_TXPA_G3					0x33	/* RF TX PA control */
+#define RF_0x52						0x52
+#define RF_WE_LUT					0xEF
+
+#define RF_TX_GAIN_OFFSET_8812A(_val) ((abs((_val)) << 1) | (((_val) > 0) ? BIT0 : 0))
+#define RF_TX_GAIN_OFFSET_8821A(_val) ((abs((_val)) << 1) | (((_val) > 0) ? BIT0 : 0))
+
+/*
+ * Bit Mask
+ *
+ * 1. Page1(0x100) */
+#define bBBResetB					0x100	/* Useless now? */
+#define bGlobalResetB				0x200
+#define bOFDMTxStart				0x4
+#define bCCKTxStart					0x8
+#define bCRC32Debug					0x100
+#define bPMACLoopback				0x10
+#define bTxLSIG						0xffffff
+#define bOFDMTxRate					0xf
+#define bOFDMTxReserved			0x10
+#define bOFDMTxLength				0x1ffe0
+#define bOFDMTxParity				0x20000
+#define bTxHTSIG1					0xffffff
+#define bTxHTMCSRate				0x7f
+#define bTxHTBW						0x80
+#define bTxHTLength					0xffff00
+#define bTxHTSIG2					0xffffff
+#define bTxHTSmoothing				0x1
+#define bTxHTSounding				0x2
+#define bTxHTReserved				0x4
+#define bTxHTAggreation				0x8
+#define bTxHTSTBC					0x30
+#define bTxHTAdvanceCoding			0x40
+#define bTxHTShortGI					0x80
+#define bTxHTNumberHT_LTF			0x300
+#define bTxHTCRC8					0x3fc00
+#define bCounterReset				0x10000
+#define bNumOfOFDMTx				0xffff
+#define bNumOfCCKTx					0xffff0000
+#define bTxIdleInterval				0xffff
+#define bOFDMService				0xffff0000
+#define bTxMACHeader				0xffffffff
+#define bTxDataInit					0xff
+#define bTxHTMode					0x100
+#define bTxDataType					0x30000
+#define bTxRandomSeed				0xffffffff
+#define bCCKTxPreamble				0x1
+#define bCCKTxSFD					0xffff0000
+#define bCCKTxSIG					0xff
+#define bCCKTxService				0xff00
+#define bCCKLengthExt				0x8000
+#define bCCKTxLength				0xffff0000
+#define bCCKTxCRC16					0xffff
+#define bCCKTxStatus					0x1
+#define bOFDMTxStatus				0x2
+
+
+/*
+ * 1. PMAC duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF
+ * 1. Page1(0x100)
+ *   */
+#define rPMAC_Reset					0x100
+#define rPMAC_TxStart				0x104
+#define rPMAC_TxLegacySIG			0x108
+#define rPMAC_TxHTSIG1				0x10c
+#define rPMAC_TxHTSIG2				0x110
+#define rPMAC_PHYDebug				0x114
+#define rPMAC_TxPacketNum			0x118
+#define rPMAC_TxIdle					0x11c
+#define rPMAC_TxMACHeader0			0x120
+#define rPMAC_TxMACHeader1			0x124
+#define rPMAC_TxMACHeader2			0x128
+#define rPMAC_TxMACHeader3			0x12c
+#define rPMAC_TxMACHeader4			0x130
+#define rPMAC_TxMACHeader5			0x134
+#define rPMAC_TxDataType			0x138
+#define rPMAC_TxRandomSeed		0x13c
+#define rPMAC_CCKPLCPPreamble		0x140
+#define rPMAC_CCKPLCPHeader		0x144
+#define rPMAC_CCKCRC16				0x148
+#define rPMAC_OFDMRxCRC32OK		0x170
+#define rPMAC_OFDMRxCRC32Er		0x174
+#define rPMAC_OFDMRxParityEr		0x178
+#define rPMAC_OFDMRxCRC8Er			0x17c
+#define rPMAC_CCKCRxRC16Er			0x180
+#define rPMAC_CCKCRxRC32Er			0x184
+#define rPMAC_CCKCRxRC32OK			0x188
+#define rPMAC_TxStatus				0x18c
+
+/*
+ * 3. Page8(0x800)
+ *   */
+#define rFPGA0_RFMOD				0x800	/* RF mode & CCK TxSC */ /* RF BW Setting?? */
+
+#define rFPGA0_TxInfo				0x804	/* Status report?? */
+#define rFPGA0_PSDFunction			0x808
+#define rFPGA0_TxGainStage			0x80c	/* Set TX PWR init gain? */
+
+#define rFPGA0_XA_HSSIParameter1	0x820	/* RF 3 wire register */
+#define rFPGA0_XA_HSSIParameter2	0x824
+#define rFPGA0_XB_HSSIParameter1	0x828
+#define rFPGA0_XB_HSSIParameter2	0x82c
+
+#define rFPGA0_XAB_SwitchControl	0x858	/* RF Channel switch */
+#define rFPGA0_XCD_SwitchControl	0x85c
+
+#define rFPGA0_XAB_RFParameter		0x878	/* RF Parameter */
+#define rFPGA0_XCD_RFParameter		0x87c
+
+#define rFPGA0_AnalogParameter1	0x880	/* Crystal cap setting RF-R/W protection for parameter4?? */
+#define rFPGA0_AnalogParameter2	0x884
+#define rFPGA0_AnalogParameter3	0x888
+#define rFPGA0_AdDaClockEn			0x888	/* enable ad/da clock1 for dual-phy */
+#define rFPGA0_AnalogParameter4	0x88c
+#define rFPGA0_XB_LSSIReadBack		0x8a4
+#define rFPGA0_XCD_RFPara	0x8b4
+
+/*
+ * 4. Page9(0x900)
+ *   */
+#define rFPGA1_RFMOD				0x900	/* RF mode & OFDM TxSC */ /* RF BW Setting?? */
+
+#define rFPGA1_TxBlock				0x904	/* Useless now */
+#define rFPGA1_DebugSelect			0x908	/* Useless now */
+#define rFPGA1_TxInfo				0x90c	/* Useless now */ /* Status report?? */
+
+/*
+ * PageA(0xA00)
+ *   */
+#define rCCK0_System				0xa00
+#define rCCK0_AFESetting				0xa04	/* Disable init gain now */ /* Select RX path by RSSI */
+#define	rCCK0_DSPParameter2			0xa1c	/* SQ threshold */
+#define rCCK0_TxFilter1				0xa20
+#define rCCK0_TxFilter2				0xa24
+#define rCCK0_DebugPort				0xa28	/* debug port and Tx filter3 */
+#define	rCCK0_FalseAlarmReport			0xa2c	/* 0xa2d	useless now 0xa30-a4f channel report */
+
+/*
+ * PageB(0xB00)
+ *   */
+#define rPdp_AntA				0xb00
+#define rPdp_AntA_4				0xb04
+#define rConfig_Pmpd_AntA			0xb28
+#define rConfig_AntA					0xb68
+#define rConfig_AntB					0xb6c
+#define rPdp_AntB					0xb70
+#define rPdp_AntB_4					0xb74
+#define rConfig_Pmpd_AntB			0xb98
+#define rAPK							0xbd8
+
+/*
+ * 6. PageC(0xC00)
+ *   */
+#define rOFDM0_LSTF					0xc00
+
+#define rOFDM0_TRxPathEnable		0xc04
+#define rOFDM0_TRMuxPar			0xc08
+#define rOFDM0_TRSWIsolation		0xc0c
+
+#define rOFDM0_XARxAFE				0xc10  /* RxIQ DC offset, Rx digital filter, DC notch filter */
+#define rOFDM0_XARxIQImbalance    	0xc14  /* RxIQ imblance matrix */
+#define rOFDM0_XBRxAFE		0xc18
+#define rOFDM0_XBRxIQImbalance	0xc1c
+#define rOFDM0_XCRxAFE		0xc20
+#define rOFDM0_XCRxIQImbalance	0xc24
+#define rOFDM0_XDRxAFE		0xc28
+#define rOFDM0_XDRxIQImbalance	0xc2c
+
+#define rOFDM0_RxDetector1			0xc30  /* PD, BW & SBD	 */ /* DM tune init gain */
+#define rOFDM0_RxDetector2			0xc34  /* SBD & Fame Sync. */
+#define rOFDM0_RxDetector3			0xc38  /* Frame Sync. */
+#define rOFDM0_RxDetector4			0xc3c  /* PD, SBD, Frame Sync & Short-GI */
+
+#define rOFDM0_RxDSP				0xc40  /* Rx Sync Path */
+#define rOFDM0_CFOandDAGC			0xc44  /* CFO & DAGC */
+#define rOFDM0_CCADropThreshold	0xc48 /* CCA Drop threshold */
+#define rOFDM0_ECCAThreshold		0xc4c /* energy CCA */
+
+#define rOFDM0_XAAGCCore1			0xc50	/* DIG */
+#define rOFDM0_XAAGCCore2			0xc54
+#define rOFDM0_XBAGCCore1			0xc58
+#define rOFDM0_XBAGCCore2			0xc5c
+#define rOFDM0_XCAGCCore1			0xc60
+#define rOFDM0_XCAGCCore2			0xc64
+#define rOFDM0_XDAGCCore1			0xc68
+#define rOFDM0_XDAGCCore2			0xc6c
+
+#define rOFDM0_AGCParameter1		0xc70
+#define rOFDM0_AGCParameter2		0xc74
+#define rOFDM0_AGCRSSITable		0xc78
+#define rOFDM0_HTSTFAGC			0xc7c
+
+#define rOFDM0_XATxIQImbalance		0xc80	/* TX PWR TRACK and DIG */
+#define rOFDM0_XATxAFE				0xc84
+#define rOFDM0_XBTxIQImbalance		0xc88
+#define rOFDM0_XBTxAFE				0xc8c
+#define rOFDM0_XCTxIQImbalance		0xc90
+#define rOFDM0_XCTxAFE		0xc94
+#define rOFDM0_XDTxIQImbalance		0xc98
+#define rOFDM0_XDTxAFE				0xc9c
+
+#define rOFDM0_RxIQExtAnta			0xca0
+#define rOFDM0_TxCoeff1				0xca4
+#define rOFDM0_TxCoeff2				0xca8
+#define rOFDM0_TxCoeff3				0xcac
+#define rOFDM0_TxCoeff4				0xcb0
+#define rOFDM0_TxCoeff5				0xcb4
+#define rOFDM0_TxCoeff6				0xcb8
+#define rOFDM0_RxHPParameter		0xce0
+#define rOFDM0_TxPseudoNoiseWgt	0xce4
+#define rOFDM0_FrameSync			0xcf0
+#define rOFDM0_DFSReport			0xcf4
+
+/*
+ * 7. PageD(0xD00)
+ *   */
+#define rOFDM1_LSTF					0xd00
+#define rOFDM1_TRxPathEnable		0xd04
+
+/*
+ * 8. PageE(0xE00)
+ *   */
+#define rTxAGC_A_Rate18_06			0xe00
+#define rTxAGC_A_Rate54_24			0xe04
+#define rTxAGC_A_CCK1_Mcs32		0xe08
+#define rTxAGC_A_Mcs03_Mcs00		0xe10
+#define rTxAGC_A_Mcs07_Mcs04		0xe14
+#define rTxAGC_A_Mcs11_Mcs08		0xe18
+#define rTxAGC_A_Mcs15_Mcs12		0xe1c
+
+#define rTxAGC_B_Rate18_06			0x830
+#define rTxAGC_B_Rate54_24			0x834
+#define rTxAGC_B_CCK1_55_Mcs32	0x838
+#define rTxAGC_B_Mcs03_Mcs00		0x83c
+#define rTxAGC_B_Mcs07_Mcs04		0x848
+#define rTxAGC_B_Mcs11_Mcs08		0x84c
+#define rTxAGC_B_Mcs15_Mcs12		0x868
+#define rTxAGC_B_CCK11_A_CCK2_11	0x86c
+
+#define rFPGA0_IQK					0xe28
+#define rTx_IQK_Tone_A				0xe30
+#define rRx_IQK_Tone_A				0xe34
+#define rTx_IQK_PI_A				0xe38
+#define rRx_IQK_PI_A				0xe3c
+
+#define rTx_IQK						0xe40
+#define rRx_IQK						0xe44
+#define rIQK_AGC_Pts					0xe48
+#define rIQK_AGC_Rsp				0xe4c
+#define rTx_IQK_Tone_B				0xe50
+#define rRx_IQK_Tone_B				0xe54
+#define rTx_IQK_PI_B					0xe58
+#define rRx_IQK_PI_B					0xe5c
+#define rIQK_AGC_Cont				0xe60
+
+#define rBlue_Tooth					0xe6c
+#define rRx_Wait_CCA				0xe70
+#define rTx_CCK_RFON				0xe74
+#define rTx_CCK_BBON				0xe78
+#define rTx_OFDM_RFON				0xe7c
+#define rTx_OFDM_BBON				0xe80
+#define rTx_To_Rx					0xe84
+#define rTx_To_Tx					0xe88
+#define rRx_CCK						0xe8c
+
+#define rTx_Power_Before_IQK_A		0xe94
+#define rTx_Power_After_IQK_A		0xe9c
+
+#define rRx_Power_Before_IQK_A		0xea0
+#define rRx_Power_Before_IQK_A_2	0xea4
+#define rRx_Power_After_IQK_A		0xea8
+#define rRx_Power_After_IQK_A_2		0xeac
+
+#define rTx_Power_Before_IQK_B		0xeb4
+#define rTx_Power_After_IQK_B		0xebc
+
+#define rRx_Power_Before_IQK_B		0xec0
+#define rRx_Power_Before_IQK_B_2	0xec4
+#define rRx_Power_After_IQK_B		0xec8
+#define rRx_Power_After_IQK_B_2		0xecc
+
+#define rRx_OFDM					0xed0
+#define rRx_Wait_RIFS				0xed4
+#define rRx_TO_Rx					0xed8
+#define rStandby						0xedc
+#define rSleep						0xee0
+#define rPMPD_ANAEN				0xeec
+
+
+/* 2. Page8(0x800) */
+#define bRFMOD						0x1	/* Reg 0x800 rFPGA0_RFMOD */
+#define bJapanMode					0x2
+#define bCCKTxSC					0x30
+#define bCCKEn						0x1000000
+#define bOFDMEn						0x2000000
+#define bXBTxAGC                  			0xf00	/* Reg 80c rFPGA0_TxGainStage */
+#define bXCTxAGC			0xf000
+#define bXDTxAGC			0xf0000
+
+/* 4. PageA(0xA00) */
+#define bCCKBBMode                			0x3	/* Useless */
+#define bCCKTxPowerSaving		0x80
+#define bCCKRxPowerSaving		0x40
+
+#define bCCKSideBand              		0x10	/* Reg 0xa00 rCCK0_System 20/40 switch */
+
+#define bCCKScramble              		0x8	/* Useless */
+#define bCCKAntDiversity			0x8000
+#define bCCKCarrierRecovery		0x4000
+#define bCCKTxRate			0x3000
+#define bCCKDCCancel			0x0800
+#define bCCKISICancel			0x0400
+#define bCCKMatchFilter		0x0200
+#define bCCKEqualizer			0x0100
+#define bCCKPreambleDetect		0x800000
+#define bCCKFastFalseCCA		0x400000
+#define bCCKChEstStart		0x300000
+#define bCCKCCACount		0x080000
+#define bCCKcs_lim			0x070000
+#define bCCKBistMode			0x80000000
+#define bCCKCCAMask			0x40000000
+#define bCCKTxDACPhase		0x4
+#define bCCKRxADCPhase         	   	0x20000000   /* r_rx_clk */
+#define bCCKr_cp_mode0		0x0100
+#define bCCKTxDCOffset		0xf0
+#define bCCKRxDCOffset		0xf
+#define bCCKCCAMode			0xc000
+#define bCCKFalseCS_lim		0x3f00
+#define bCCKCS_ratio			0xc00000
+#define bCCKCorgBit_sel		0x300000
+#define bCCKPD_lim			0x0f0000
+#define bCCKNewCCA		0x80000000
+#define bCCKRxHPofIG		0x8000
+#define bCCKRxIG			0x7f00
+#define bCCKLNAPolarity		0x800000
+#define bCCKRx1stGain		0x7f0000
+#define bCCKRFExtend              		0x20000000 /* CCK Rx Iinital gain polarity */
+#define bCCKRxAGCSatLevel		0x1f000000
+#define bCCKRxAGCSatCount		0xe0
+#define bCCKRxRFSettle            		0x1f       /* AGCsamp_dly */
+#define bCCKFixedRxAGC		0x8000
+/* #define bCCKRxAGCFormat		0x4000 */   /* remove to HSSI register 0x824 */
+#define bCCKAntennaPolarity		0x2000
+#define bCCKTxFilterType		0x0c00
+#define bCCKRxAGCReportType		0x0300
+#define bCCKRxDAGCEn		0x80000000
+#define bCCKRxDAGCPeriod		0x20000000
+#define bCCKRxDAGCSatLevel		0x1f000000
+#define bCCKTimingRecovery		0x800000
+#define bCCKTxC0			0x3f0000
+#define bCCKTxC1			0x3f000000
+#define bCCKTxC2			0x3f
+#define bCCKTxC3			0x3f00
+#define bCCKTxC4			0x3f0000
+#define bCCKTxC5			0x3f000000
+#define bCCKTxC6			0x3f
+#define bCCKTxC7			0x3f00
+#define bCCKDebugPort		0xff0000
+#define bCCKDACDebug		0x0f000000
+#define bCCKFalseAlarmEnable		0x8000
+#define bCCKFalseAlarmRead		0x4000
+#define bCCKTRSSI			0x7f
+#define bCCKRxAGCReport		0xfe
+#define bCCKRxReport_AntSel		0x80000000
+#define bCCKRxReport_MFOff		0x40000000
+#define bCCKRxRxReport_SQLoss	0x20000000
+#define bCCKRxReport_Pktloss		0x10000000
+#define bCCKRxReport_Lockedbit	0x08000000
+#define bCCKRxReport_RateError	0x04000000
+#define bCCKRxReport_RxRate		0x03000000
+#define bCCKRxFACounterLower	0xff
+#define bCCKRxFACounterUpper	0xff000000
+#define bCCKRxHPAGCStart		0xe000
+#define bCCKRxHPAGCFinal		0x1c00
+#define bCCKRxFalseAlarmEnable	0x8000
+#define bCCKFACounterFreeze		0x4000
+#define bCCKTxPathSel		0x10000000
+#define bCCKDefaultRxPath		0xc000000
+#define bCCKOptionRxPath		0x3000000
+
+/* 6. PageE(0xE00) */
+#define bSTBCEn                  			0x4	/* Useless */
+#define bAntennaMapping		0x10
+#define bNss				0x20
+#define bCFOAntSumD		0x200
+#define bPHYCounterReset		0x8000000
+#define bCFOReportGet			0x4000000
+#define bOFDMContinueTx		0x10000000
+#define bOFDMSingleCarrier		0x20000000
+#define bOFDMSingleTone		0x40000000
+
+
+/*
+ * Other Definition
+ *   */
+
+#define bEnable                   0x1	/* Useless */
+#define bDisable                  0x0
+
+/* byte endable for srwrite */
+#define bByte0                    		0x1	/* Useless */
+#define bByte1		0x2
+#define bByte2		0x4
+#define bByte3		0x8
+#define bWord0		0x3
+#define bWord1		0xc
+#define bDWord		0xf
+
+/* for PutRegsetting & GetRegSetting BitMask */
+#define bMaskByte0                		0xff	/* Reg 0xc50 rOFDM0_XAAGCCore~0xC6f */
+#define bMaskByte1		0xff00
+#define bMaskByte2		0xff0000
+#define bMaskByte3		0xff000000
+#define bMaskHWord	0xffff0000
+#define bMaskLWord		0x0000ffff
+#define bMaskDWord	0xffffffff
+#define bMaskH3Bytes				0xffffff00
+#define bMask12Bits				0xfff
+#define bMaskH4Bits				0xf0000000
+#define bMaskOFDM_D			0xffc00000
+#define bMaskCCK				0x3f3f3f3f
+
+
+/*--------------------------Define Parameters-------------------------------*/
+
+
+#endif
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/include/Hal8812PwrSeq.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/Hal8812PwrSeq.h
--- linux-5.6.3/3rdparty/rtl8821ce/include/Hal8812PwrSeq.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/Hal8812PwrSeq.h	2020-04-10 16:35:06.845661421 +0300
@@ -0,0 +1,208 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+
+
+#ifndef __HAL8812PWRSEQ_H__
+#define __HAL8812PWRSEQ_H__
+
+#include "HalPwrSeqCmd.h"
+
+/*
+	Check document WB-110628-DZ-RTL8195 (Jaguar) Power Architecture-R04.pdf
+	There are 6 HW Power States:
+	0: POFF--Power Off
+	1: PDN--Power Down
+	2: CARDEMU--Card Emulation
+	3: ACT--Active Mode
+	4: LPS--Low Power State
+	5: SUS--Suspend
+
+	The transision from different states are defined below
+	TRANS_CARDEMU_TO_ACT
+	TRANS_ACT_TO_CARDEMU
+	TRANS_CARDEMU_TO_SUS
+	TRANS_SUS_TO_CARDEMU
+	TRANS_CARDEMU_TO_PDN
+	TRANS_ACT_TO_LPS
+	TRANS_LPS_TO_ACT
+
+	TRANS_END
+*/
+#define	RTL8812_TRANS_CARDEMU_TO_ACT_STEPS	15
+#define	RTL8812_TRANS_ACT_TO_CARDEMU_STEPS	15
+#define	RTL8812_TRANS_CARDEMU_TO_SUS_STEPS	15
+#define	RTL8812_TRANS_SUS_TO_CARDEMU_STEPS	15
+#define	RTL8812_TRANS_CARDEMU_TO_PDN_STEPS	15
+#define	RTL8812_TRANS_PDN_TO_CARDEMU_STEPS	15
+#define	RTL8812_TRANS_ACT_TO_LPS_STEPS	15
+#define	RTL8812_TRANS_LPS_TO_ACT_STEPS	15
+#define	RTL8812_TRANS_END_STEPS	1
+
+
+#define RTL8812_TRANS_CARDEMU_TO_ACT														\
+	/* format */																\
+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, 0},/* disable SW LPS 0x04[10]=0*/	\
+	{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT1, BIT1},/* wait till 0x04[17] = 1    power ready*/	\
+	/*{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, 0}, disable HWPDN 0x04[15]=0*/ \
+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3, 0},/* disable WL suspend*/	\
+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0},/* polling until return 0*/	\
+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT0, 0},/**/   \
+	{0x0024, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, 0}, /* 0x24[1] Choose the type of buffer after xosc: nand*/   \
+	{0x0028, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3, 0}, /* 0x28[33] Choose the type of buffer after xosc: nand*/
+
+#define RTL8812_TRANS_ACT_TO_CARDEMU													\
+	/* format */																\
+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
+	{0x0c00, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x04}, /* 0xc00[7:0] = 4	turn off 3-wire */	\
+	{0x0e00, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x04}, /* 0xe00[7:0] = 4	turn off 3-wire */	\
+	{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0}, /* 0x2[0] = 0	 RESET BB, CLOSE RF */	\
+	{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_US},/*Delay 1us*/	\
+	{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0},  /* Whole BB is reset*/			\
+	/*{0x001F, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0},//0x1F[7:0] = 0 turn off RF*/	\
+	/*{0x004E, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, 0},//0x4C[23] = 0x4E[7] = 0, switch DPDT_SEL_P output from register 0x65[2] */	\
+	{0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x2A}, /* 0x07[7:0] = 0x28 sps pwm mode 0x2a for BT coex*/	\
+	{0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x02, 0},/*0x8[1] = 0 ANA clk = 500k */	\
+	/*{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0 | BIT1, 0}, //  0x02[1:0] = 0	reset BB */	\
+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1}, /*0x04[9] = 1 turn off MAC by HW state machine*/	\
+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT1, 0}, /*wait till 0x04[9] = 0 polling until return 0 to disable*/
+
+#define RTL8812_TRANS_CARDEMU_TO_SUS													\
+	/* format */								\
+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
+	{0x0042, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xF0, 0xcc},\
+	{0x0042, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xF0, 0xEC},\
+	{0x0043, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x07},/* gpio11 input mode, gpio10~8 output mode */	\
+	{0x0045, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x00},/* gpio 0~7 output same value as input ?? */	\
+	{0x0046, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xff},/* gpio0~7 output mode */	\
+	{0x0047, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0},/* 0x47[7:0] = 00 gpio mode */	\
+	{0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0},/* suspend option all off */	\
+	{0x0014, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x80, BIT7},/*0x14[7] = 1 turn on ZCD */	\
+	{0x0015, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x01, BIT0},/* 0x15[0] =1 trun on ZCD */	\
+	{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x10, BIT4},/*0x23[4] = 1 hpon LDO sleep mode */	\
+	{0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x02, 0},/*0x8[1] = 0 ANA clk = 500k */	\
+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3, BIT3}, /*0x04[11] = 2b'11 enable WL suspend for PCIe*/
+
+#define RTL8812_TRANS_SUS_TO_CARDEMU													\
+	/* format */								\
+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3, 0}, /*0x04[11] = 2b'01enable WL suspend*/   \
+	{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x10, 0},/*0x23[4] = 0 hpon LDO sleep mode leave */	\
+	{0x0015, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x01, 0},/* 0x15[0] =0 trun off ZCD */	\
+	{0x0014, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x80, 0},/*0x14[7] = 0 turn off ZCD */	\
+	{0x0046, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x00},/* gpio0~7 input mode */	\
+	{0x0043, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x00},/* gpio11 input mode, gpio10~8 input mode */
+
+#define RTL8812_TRANS_CARDEMU_TO_CARDDIS													\
+	/* format */																\
+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
+	/**{0x0194, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0}, //0x194[0]=0 , disable 32K clock*/	\
+	/**{0x0093, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x94}, //0x93 = 0x94 , 90[30] =0 enable 500k ANA clock .switch clock from 12M to 500K , 90 [26] =0 disable EEprom loader clock*/	\
+	{0x0003, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, 0}, /*0x03[2] = 0, reset 8051*/	\
+	{0x0080, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x05}, /*0x80 = 05h if reload fw, fill the default value of host_CPU handshake field*/	\
+	{0x0042, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xF0, 0xcc},\
+	{0x0042, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xF0, 0xEC},\
+	{0x0043, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x07},/* gpio11 input mode, gpio10~8 output mode */	\
+	{0x0045, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x00},/* gpio 0~7 output same value as input ?? */	\
+	{0x0046, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xff},/* gpio0~7 output mode */	\
+	{0x0047, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0},/* 0x47[7:0] = 00 gpio mode */	\
+	{0x0014, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x80, BIT7},/*0x14[7] = 1 turn on ZCD */	\
+	{0x0015, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x01, BIT0},/* 0x15[0] =1 trun on ZCD */	\
+	{0x0012, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x01, 0},/*0x12[0] = 0 force PFM mode */	\
+	{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x10, BIT4},/*0x23[4] = 1 hpon LDO sleep mode */	\
+	{0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x02, 0},/*0x8[1] = 0 ANA clk = 500k */	\
+	{0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x20}, /*0x07 = 0x20 , SOP option to disable BG/MB*/	\
+	{0x001f, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0}, /*0x01f[1]=0 , disable RFC_0  control  REG_RF_CTRL_8812 */	\
+	{0x0076, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0}, /*0x076[1]=0 , disable RFC_1  control REG_OPT_CTRL_8812 +2 */	\
+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3, BIT3}, /*0x04[11] = 2b'01 enable WL suspend*/
+
+#define RTL8812_TRANS_CARDDIS_TO_CARDEMU													\
+	/* format */																\
+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/                       \
+	{0x0012, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0},/*0x12[0] = 1 force PWM mode */	\
+	{0x0014, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x80, 0},/*0x14[7] = 0 turn off ZCD */	\
+	{0x0015, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x01, 0},/* 0x15[0] =0 trun off ZCD */	\
+	{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x10, 0},/*0x23[4] = 0 hpon LDO leave sleep mode */	\
+	{0x0046, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x00},/* gpio0~7 input mode */	\
+	{0x0043, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x00},/* gpio11 input mode, gpio10~8 input mode */ \
+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, 0}, /*0x04[10] = 0, enable SW LPS PCIE only*/	\
+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3, 0}, /*0x04[11] = 2b'01enable WL suspend*/	\
+	{0x0003, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, BIT2}, /*0x03[2] = 1, enable 8051*/	\
+	{0x0301, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0},/*PCIe DMA start*/  \
+	{0x0024, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, BIT1}, /* 0x24[1] Choose the type of buffer after xosc: schmitt trigger*/ \
+	{0x0028, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3, BIT3}, /* 0x28[33] Choose the type of buffer after xosc: schmitt trigger*/
+
+
+#define RTL8812_TRANS_CARDEMU_TO_PDN												\
+	/* format */																\
+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/	\
+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, BIT7},/* 0x04[15] = 1*/
+
+#define RTL8812_TRANS_PDN_TO_CARDEMU												\
+	/* format */																\
+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/	\
+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, 0},/* 0x04[15] = 0*/
+
+#define RTL8812_TRANS_ACT_TO_LPS														\
+	/* format */																\
+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
+	{0x0301, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF},/*PCIe DMA stop*/	\
+	{0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x7F},/*Tx Pause*/		\
+	{0x05F8, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/	\
+	{0x05F9, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/	\
+	{0x05FA, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/	\
+	{0x05FB, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/	\
+	{0x0c00, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x04}, /* 0xc00[7:0] = 4	turn off 3-wire */	\
+	{0x0e00, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x04}, /* 0xe00[7:0] = 4	turn off 3-wire */	\
+	{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0},/*CCK and OFDM are disabled, and clock are gated, and RF closed*/	\
+	{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_US},/*Delay 1us*/	\
+	{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0},  /* Whole BB is reset*/			\
+	{0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x03},/*Reset MAC TRX*/			\
+	{0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0},/*check if removed later*/		\
+	{0x0553, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT5, BIT5},/*Respond TxOK to scheduler*/
+
+
+#define RTL8812_TRANS_LPS_TO_ACT															\
+	/* format */																\
+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/	\
+	{0x0080, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, 0xFF, 0x84}, /*SDIO RPWM*/	\
+	{0xFE58, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x84}, /*USB RPWM*/	\
+	{0x0361, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x84}, /*PCIe RPWM*/	\
+	{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_MS}, /*Delay*/	\
+	{0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0}, /*.	0x08[4] = 0		 switch TSF to 40M*/	\
+	{0x0109, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT7, 0}, /*Polling 0x109[7]=0  TSF in 40M*/			\
+	{0x0029, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT6 | BIT7, 0}, /*.	0x29[7:6] = 2b'00	 enable BB clock*/	\
+	{0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1}, /*.	0x101[1] = 1*/					\
+	{0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF}, /*.	0x100[7:0] = 0xFF	 enable WMAC TRX*/	\
+	{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1 | BIT0, BIT1 | BIT0}, /*.	0x02[1:0] = 2b'11	 enable BB macro*/	\
+	{0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0}, /*.	0x522 = 0*/
+
+#define RTL8812_TRANS_END																\
+	/* format */																\
+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/		\
+	{0xFFFF, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, 0, PWR_CMD_END, 0, 0},
+
+
+extern WLAN_PWR_CFG rtl8812_power_on_flow[RTL8812_TRANS_CARDEMU_TO_ACT_STEPS + RTL8812_TRANS_END_STEPS];
+extern WLAN_PWR_CFG rtl8812_radio_off_flow[RTL8812_TRANS_ACT_TO_CARDEMU_STEPS + RTL8812_TRANS_END_STEPS];
+extern WLAN_PWR_CFG rtl8812_card_disable_flow[RTL8812_TRANS_ACT_TO_CARDEMU_STEPS + RTL8812_TRANS_CARDEMU_TO_PDN_STEPS + RTL8812_TRANS_END_STEPS];
+extern WLAN_PWR_CFG rtl8812_card_enable_flow[RTL8812_TRANS_ACT_TO_CARDEMU_STEPS + RTL8812_TRANS_CARDEMU_TO_PDN_STEPS + RTL8812_TRANS_END_STEPS];
+extern WLAN_PWR_CFG rtl8812_suspend_flow[RTL8812_TRANS_ACT_TO_CARDEMU_STEPS + RTL8812_TRANS_CARDEMU_TO_SUS_STEPS + RTL8812_TRANS_END_STEPS];
+extern WLAN_PWR_CFG rtl8812_resume_flow[RTL8812_TRANS_ACT_TO_CARDEMU_STEPS + RTL8812_TRANS_CARDEMU_TO_SUS_STEPS + RTL8812_TRANS_END_STEPS];
+extern WLAN_PWR_CFG rtl8812_hwpdn_flow[RTL8812_TRANS_ACT_TO_CARDEMU_STEPS + RTL8812_TRANS_CARDEMU_TO_PDN_STEPS + RTL8812_TRANS_END_STEPS];
+extern WLAN_PWR_CFG rtl8812_enter_lps_flow[RTL8812_TRANS_ACT_TO_LPS_STEPS + RTL8812_TRANS_END_STEPS];
+extern WLAN_PWR_CFG rtl8812_leave_lps_flow[RTL8812_TRANS_LPS_TO_ACT_STEPS + RTL8812_TRANS_END_STEPS];
+
+#endif /* __HAL8812PWRSEQ_H__ */
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/include/Hal8814PhyCfg.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/Hal8814PhyCfg.h
--- linux-5.6.3/3rdparty/rtl8821ce/include/Hal8814PhyCfg.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/Hal8814PhyCfg.h	2020-04-10 16:35:06.845661421 +0300
@@ -0,0 +1,264 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#ifndef __INC_HAL8814PHYCFG_H__
+#define __INC_HAL8814PHYCFG_H__
+
+
+/*--------------------------Define Parameters-------------------------------*/
+#define LOOP_LIMIT				5
+#define MAX_STALL_TIME			50		/* us */
+#define AntennaDiversityValue	0x80	/* (Adapter->bSoftwareAntennaDiversity ? 0x00 : 0x80) */
+#define MAX_TXPWR_IDX_NMODE_92S	63
+#define Reset_Cnt_Limit			3
+
+
+#ifdef CONFIG_PCI_HCI
+	#define MAX_AGGR_NUM	0x0B
+#else
+	#define MAX_AGGR_NUM	0x07
+#endif /* CONFIG_PCI_HCI */
+
+
+/*--------------------------Define Parameters-------------------------------*/
+
+/*------------------------------Define structure----------------------------*/
+
+
+/* BB/RF related */
+
+#define	SIC_ENABLE				0
+
+/*------------------------------Define structure----------------------------*/
+
+
+/*------------------------Export global variable----------------------------*/
+/*------------------------Export global variable----------------------------*/
+
+
+/*------------------------Export Marco Definition---------------------------*/
+/*------------------------Export Marco Definition---------------------------*/
+
+
+/*--------------------------Exported Function prototype---------------------*/
+/* 1. BB register R/W API */
+
+extern	u32
+PHY_QueryBBReg8814A(IN	PADAPTER	Adapter,
+		    IN	u32		RegAddr,
+		    IN	u32		BitMask);
+
+
+VOID
+PHY_SetBBReg8814A(IN	PADAPTER	Adapter,
+		  IN	u32		RegAddr,
+		  IN	u32		BitMask,
+		  IN	u32		Data);
+
+
+extern	u32
+PHY_QueryRFReg8814A(IN	PADAPTER			Adapter,
+		    IN	enum rf_path	eRFPath,
+		    IN	u32			RegAddr,
+		    IN	u32			BitMask);
+
+
+void
+PHY_SetRFReg8814A(IN	PADAPTER			Adapter,
+		  IN	enum rf_path		eRFPath,
+		  IN	u32				RegAddr,
+		  IN	u32				BitMask,
+		  IN	u32				Data);
+
+/* 1 3. Initial BB/RF config by reading MAC/BB/RF txt. */
+s32
+phy_BB8814A_Config_ParaFile(
+	IN	PADAPTER	Adapter
+);
+
+VOID
+PHY_ConfigBB_8814A(
+	IN	PADAPTER	Adapter
+);
+
+
+VOID
+phy_ADC_CLK_8814A(
+	IN	PADAPTER	Adapter
+);
+
+s32
+PHY_RFConfig8814A(
+	IN	PADAPTER	Adapter
+);
+
+/*
+ * RF Power setting
+ *
+ * BOOLEAN	PHY_SetRFPowerState8814A(PADAPTER Adapter, rt_rf_power_state	eRFPowerState); */
+
+/* 1 5. Tx  Power setting API */
+
+VOID
+PHY_GetTxPowerLevel8814(
+	IN	PADAPTER		Adapter,
+	OUT ps4Byte			powerlevel
+);
+
+VOID
+PHY_SetTxPowerLevel8814(
+	IN	PADAPTER		Adapter,
+	IN	u8			Channel
+);
+
+u8
+phy_get_tx_power_index_8814a(
+	IN	PADAPTER		Adapter,
+	IN	enum rf_path		RFPath,
+	IN	u8				Rate,
+	IN	enum channel_width BandWidth,
+	IN	u8				Channel
+);
+
+u8
+PHY_GetTxPowerIndex8814A(
+	IN	PADAPTER		Adapter,
+	IN	enum rf_path		RFPath,
+	IN	u8				Rate,
+	IN	u8				BandWidth,
+	IN	u8				Channel,
+	struct txpwr_idx_comp *tic
+);
+
+VOID
+PHY_SetTxPowerIndex_8814A(
+	IN	PADAPTER		Adapter,
+	IN	u32				PowerIndex,
+	IN	enum rf_path		RFPath,
+	IN	u8				Rate
+);
+
+
+BOOLEAN
+PHY_UpdateTxPowerDbm8814A(
+	IN	PADAPTER	Adapter,
+	IN	s4Byte		powerInDbm
+);
+
+
+u32
+PHY_GetTxBBSwing_8814A(
+	IN	PADAPTER	Adapter,
+	IN	BAND_TYPE	Band,
+	IN	enum rf_path	RFPath
+);
+
+
+
+/* 1 6. Channel setting API */
+#if 0
+VOID
+PHY_SwChnlTimerCallback8814A(
+	IN	struct timer_list		*p_timer
+);
+#endif
+VOID
+PHY_SwChnlWorkItemCallback8814A(
+	IN PVOID            pContext
+);
+
+
+VOID
+HAL_HandleSwChnl8814A(
+	IN	PADAPTER	pAdapter,
+	IN	u8		channel
+);
+
+VOID
+PHY_SwChnlSynchronously8814A(IN	PADAPTER		pAdapter,
+			     IN	u8			channel);
+
+VOID
+PHY_SwChnlAndSetBWModeCallback8814A(IN PVOID            pContext);
+
+
+VOID
+PHY_HandleSwChnlAndSetBW8814A(
+	IN	PADAPTER			Adapter,
+	IN	BOOLEAN				bSwitchChannel,
+	IN	BOOLEAN				bSetBandWidth,
+	IN	u8					ChannelNum,
+	IN	enum channel_width	ChnlWidth,
+	IN	u8					ChnlOffsetOf40MHz,
+	IN	u8					ChnlOffsetOf80MHz,
+	IN	u8					CenterFrequencyIndex1
+);
+
+
+BOOLEAN
+PHY_QueryRFPathSwitch_8814A(IN	PADAPTER	pAdapter);
+
+
+
+#if (USE_WORKITEM)
+VOID
+RtCheckForHangWorkItemCallback8814A(
+	IN PVOID   pContext
+);
+#endif
+
+BOOLEAN
+SetAntennaConfig8814A(
+	IN	PADAPTER	Adapter,
+	IN	u8		DefaultAnt
+);
+
+VOID
+PHY_SetRFEReg8814A(
+	IN PADAPTER		Adapter,
+	IN BOOLEAN		bInit,
+	IN u8		Band
+);
+
+
+s32
+PHY_SwitchWirelessBand8814A(
+	IN PADAPTER		 Adapter,
+	IN u8		Band
+);
+
+VOID
+PHY_SetIO_8814A(
+	PADAPTER		pAdapter
+);
+
+VOID
+PHY_SetSwChnlBWMode8814(
+	IN	PADAPTER			Adapter,
+	IN	u8					channel,
+	IN	enum channel_width	Bandwidth,
+	IN	u8					Offset40,
+	IN	u8					Offset80
+);
+
+s32 PHY_MACConfig8814(PADAPTER Adapter);
+int PHY_BBConfig8814(PADAPTER	Adapter);
+VOID PHY_Set_SecCCATH_by_RXANT_8814A(PADAPTER	pAdapter, u4Byte ulAntennaRx);
+
+
+
+/*--------------------------Exported Function prototype---------------------*/
+
+/*--------------------------Exported Function prototype---------------------*/
+#endif /* __INC_HAL8192CPHYCFG_H */
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/include/Hal8814PhyReg.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/Hal8814PhyReg.h
--- linux-5.6.3/3rdparty/rtl8821ce/include/Hal8814PhyReg.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/Hal8814PhyReg.h	2020-04-10 16:35:06.845661421 +0300
@@ -0,0 +1,863 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#ifndef __INC_HAL8814PHYREG_H__
+#define __INC_HAL8814PHYREG_H__
+/*--------------------------Define Parameters-------------------------------*/
+/*
+ * BB-PHY register PMAC 0x100 PHY 0x800 - 0xEFF
+ * 1. PMAC duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF
+ * 2. 0x800/0x900/0xA00/0xC00/0xD00/0xE00
+ * 3. RF register 0x00-2E
+ * 4. Bit Mask for BB/RF register
+ * 5. Other defintion for BB/RF R/W
+ *   */
+
+
+/* BB Register Definition */
+
+#define rCCAonSec_Jaguar		0x838
+#define rPwed_TH_Jaguar			0x830
+#define rL1_Weight_Jaguar		0x840
+#define	r_L1_SBD_start_time		0x844
+
+/* BW and sideband setting */
+#define rBWIndication_Jaguar		0x834
+#define rL1PeakTH_Jaguar		0x848
+#define rRFMOD_Jaguar			0x8ac	/* RF mode */
+#define rADC_Buf_Clk_Jaguar		0x8c4
+#define	rADC_Buf_40_Clk_Jaguar2		0x8c8
+#define rRFECTRL_Jaguar			0x900
+#define bRFMOD_Jaguar			0xc3
+#define rCCK_System_Jaguar		0xa00   /* for cck sideband */
+#define bCCK_System_Jaguar		0x10
+
+/* Block & Path enable */
+#define rOFDMCCKEN_Jaguar 		0x808 /* OFDM/CCK block enable */
+#define bOFDMEN_Jaguar			0x20000000
+#define bCCKEN_Jaguar			0x10000000
+#define rRxPath_Jaguar			0x808	/* Rx antenna */
+#define bRxPath_Jaguar			0xff
+#define rTxPath_Jaguar			0x80c	/* Tx antenna */
+#define bTxPath_Jaguar			0x0fffffff
+#define rCCK_RX_Jaguar			0xa04	/* for cck rx path selection */
+#define bCCK_RX_Jaguar			0x0c000000
+#define rVhtlen_Use_Lsig_Jaguar	0x8c3	/* Use LSIG for VHT length */
+
+#define	rRxPath_Jaguar2				0xa04	/* Rx antenna */
+#define	rTxAnt_1Nsts_Jaguar2		0x93c	/* Tx antenna for 1Nsts */
+#define	rTxAnt_23Nsts_Jaguar2		0x940	/* Tx antenna for 2Nsts and 3Nsts */
+
+
+/* RF read/write-related */
+#define rHSSIRead_Jaguar			0x8b0  /* RF read addr */
+#define bHSSIRead_addr_Jaguar		0xff
+#define bHSSIRead_trigger_Jaguar	0x100
+#define rA_PIRead_Jaguar			0xd04 /* RF readback with PI */
+#define rB_PIRead_Jaguar			0xd44 /* RF readback with PI */
+#define rA_SIRead_Jaguar			0xd08 /* RF readback with SI */
+#define rB_SIRead_Jaguar			0xd48 /* RF readback with SI */
+#define rRead_data_Jaguar			0xfffff
+#define rA_LSSIWrite_Jaguar			0xc90 /* RF write addr */
+#define rB_LSSIWrite_Jaguar			0xe90 /* RF write addr */
+#define bLSSIWrite_data_Jaguar		0x000fffff
+#define bLSSIWrite_addr_Jaguar		0x0ff00000
+
+#define	rC_PIRead_Jaguar2			0xd84 /* RF readback with PI */
+#define	rD_PIRead_Jaguar2			0xdC4 /* RF readback with PI */
+#define	rC_SIRead_Jaguar2			0xd88 /* RF readback with SI */
+#define	rD_SIRead_Jaguar2			0xdC8 /* RF readback with SI */
+#define	rC_LSSIWrite_Jaguar2		0x1890 /* RF write addr */
+#define	rD_LSSIWrite_Jaguar2		0x1A90 /* RF write addr */
+
+
+/* YN: mask the following register definition temporarily */
+#define rFPGA0_XA_RFInterfaceOE			0x860	/* RF Channel switch */
+#define rFPGA0_XB_RFInterfaceOE			0x864
+
+#define rFPGA0_XAB_RFInterfaceSW		0x870	/* RF Interface Software Control */
+#define rFPGA0_XCD_RFInterfaceSW		0x874
+
+/* #define rFPGA0_XAB_RFParameter		0x878 */	/* RF Parameter
+ * #define rFPGA0_XCD_RFParameter		0x87c */
+
+/* #define rFPGA0_AnalogParameter1		0x880 */	/* Crystal cap setting RF-R/W protection for parameter4??
+ * #define rFPGA0_AnalogParameter2		0x884
+ * #define rFPGA0_AnalogParameter3		0x888
+ * #define rFPGA0_AdDaClockEn			0x888 */	/* enable ad/da clock1 for dual-phy
+ * #define rFPGA0_AnalogParameter4		0x88c */
+
+
+/* CCK TX scaling */
+#define rCCK_TxFilter1_Jaguar		0xa20
+#define bCCK_TxFilter1_C0_Jaguar	0x00ff0000
+#define bCCK_TxFilter1_C1_Jaguar		0xff000000
+#define rCCK_TxFilter2_Jaguar		0xa24
+#define bCCK_TxFilter2_C2_Jaguar		0x000000ff
+#define bCCK_TxFilter2_C3_Jaguar		0x0000ff00
+#define bCCK_TxFilter2_C4_Jaguar		0x00ff0000
+#define bCCK_TxFilter2_C5_Jaguar		0xff000000
+#define rCCK_TxFilter3_Jaguar		0xa28
+#define bCCK_TxFilter3_C6_Jaguar		0x000000ff
+#define bCCK_TxFilter3_C7_Jaguar		0x0000ff00
+/* NBI & CSI Mask setting */
+#define	rCSI_Mask_Setting1_Jaguar	0x874
+#define	rCSI_Fix_Mask0_Jaguar		0x880
+#define	rCSI_Fix_Mask1_Jaguar		0x884
+#define	rCSI_Fix_Mask2_Jaguar		0x888
+#define	rCSI_Fix_Mask3_Jaguar		0x88c
+#define	rCSI_Fix_Mask4_Jaguar		0x890
+#define	rCSI_Fix_Mask5_Jaguar		0x894
+#define	rCSI_Fix_Mask6_Jaguar		0x898
+#define	rCSI_Fix_Mask7_Jaguar		0x89c
+#define	rNBI_Setting_Jaguar			0x87c
+
+
+/* YN: mask the following register definition temporarily
+ * #define rPdp_AntA					0xb00
+ * #define rPdp_AntA_4				0xb04
+ * #define rConfig_Pmpd_AntA			0xb28
+ * #define rConfig_AntA					0xb68
+ * #define rConfig_AntB					0xb6c
+ * #define rPdp_AntB					0xb70
+ * #define rPdp_AntB_4					0xb74
+ * #define rConfig_Pmpd_AntB			0xb98
+ * #define rAPK							0xbd8 */
+
+/* RXIQC */
+#define rA_RxIQC_AB_Jaguar    	0xc10  /* RxIQ imblance matrix coeff. A & B */
+#define rA_RxIQC_CD_Jaguar    	0xc14  /* RxIQ imblance matrix coeff. C & D */
+#define rA_TxScale_Jaguar 		0xc1c  /* Pah_A TX scaling factor */
+#define rB_TxScale_Jaguar 		0xe1c  /* Path_B TX scaling factor */
+#define rB_RxIQC_AB_Jaguar    	0xe10  /* RxIQ imblance matrix coeff. A & B */
+#define rB_RxIQC_CD_Jaguar    	0xe14  /* RxIQ imblance matrix coeff. C & D */
+#define b_RxIQC_AC_Jaguar		0x02ff  /* bit mask for IQC matrix element A & C */
+#define b_RxIQC_BD_Jaguar		0x02ff0000 /* bit mask for IQC matrix element A & C */
+
+#define	rC_TxScale_Jaguar2 		0x181c  /* Pah_C TX scaling factor */
+#define	rD_TxScale_Jaguar2 		0x1A1c  /* Path_D TX scaling factor */
+#define	rRF_TxGainOffset		0x55
+
+/* DIG-related */
+#define rA_IGI_Jaguar				0xc50	/* Initial Gain for path-A */
+#define rB_IGI_Jaguar				0xe50	/* Initial Gain for path-B */
+#define	rC_IGI_Jaguar2				0x1850	/* Initial Gain for path-C */
+#define	rD_IGI_Jaguar2				0x1A50	/* Initial Gain for path-D */
+
+#define rOFDM_FalseAlarm1_Jaguar	0xf48  /* counter for break */
+#define rOFDM_FalseAlarm2_Jaguar	0xf4c  /* counter for spoofing */
+#define rCCK_FalseAlarm_Jaguar        	0xa5c /* counter for cck false alarm */
+#define b_FalseAlarm_Jaguar			0xffff
+#define rCCK_CCA_Jaguar				0xa08	/* cca threshold */
+#define bCCK_CCA_Jaguar				0x00ff0000
+
+/* Tx Power Ttraining-related */
+#define rA_TxPwrTraing_Jaguar		0xc54
+#define rB_TxPwrTraing_Jaguar		0xe54
+
+/* Report-related */
+#define rOFDM_ShortCFOAB_Jaguar	0xf60
+#define rOFDM_LongCFOAB_Jaguar		0xf64
+#define rOFDM_EndCFOAB_Jaguar		0xf70
+#define rOFDM_AGCReport_Jaguar		0xf84
+#define rOFDM_RxSNR_Jaguar			0xf88
+#define rOFDM_RxEVMCSI_Jaguar		0xf8c
+#define rOFDM_SIGReport_Jaguar		0xf90
+
+/* Misc functions */
+#define rEDCCA_Jaguar				0x8a4 /* EDCCA */
+#define bEDCCA_Jaguar				0xffff
+#define rAGC_table_Jaguar			0x82c   /* AGC tabel select */
+#define bAGC_table_Jaguar			0x3
+#define b_sel5g_Jaguar    				0x1000 /* sel5g */
+#define b_LNA_sw_Jaguar				0x8000 /* HW/WS control for LNA */
+#define rFc_area_Jaguar				0x860   /* fc_area */
+#define bFc_area_Jaguar				0x1ffe000
+#define rSingleTone_ContTx_Jaguar	0x914
+
+#define	rAGC_table_Jaguar2			0x958	/* AGC tabel select */
+#define	rDMA_trigger_Jaguar2		0x95C	/* ADC sample mode */
+
+
+/* RFE */
+#define rA_RFE_Pinmux_Jaguar	0xcb0  /* Path_A RFE cotrol pinmux */
+#define rB_RFE_Pinmux_Jaguar	0xeb0 /* Path_B RFE control pinmux */
+#define rA_RFE_Inv_Jaguar		0xcb4  /* Path_A RFE cotrol   */
+#define rB_RFE_Inv_Jaguar		0xeb4 /* Path_B RFE control */
+#define rA_RFE_Jaguar			0xcb8  /* Path_A RFE cotrol   */
+#define rB_RFE_Jaguar			0xeb8 /* Path_B RFE control */
+#define	rA_RFE_Inverse_Jaguar	0xCBC	/* Path_A RFE control inverse */
+#define	rB_RFE_Inverse_Jaguar	0xEBC	/* Path_B RFE control inverse */
+#define r_ANTSEL_SW_Jaguar		0x900 /* ANTSEL SW Control */
+#define bMask_RFEInv_Jaguar		0x3ff00000
+#define bMask_AntselPathFollow_Jaguar 0x00030000
+
+#define	rC_RFE_Pinmux_Jaguar	0x18B4	/* Path_C RFE cotrol pinmux */
+#define	rD_RFE_Pinmux_Jaguar	0x1AB4	/* Path_D RFE cotrol pinmux */
+#define	rA_RFE_Sel_Jaguar2		0x1990
+
+
+
+/* TX AGC */
+#define rTxAGC_A_CCK11_CCK1_JAguar				0xc20
+#define rTxAGC_A_Ofdm18_Ofdm6_JAguar				0xc24
+#define rTxAGC_A_Ofdm54_Ofdm24_JAguar			0xc28
+#define rTxAGC_A_MCS3_MCS0_JAguar					0xc2c
+#define rTxAGC_A_MCS7_MCS4_JAguar					0xc30
+#define rTxAGC_A_MCS11_MCS8_JAguar				0xc34
+#define rTxAGC_A_MCS15_MCS12_JAguar				0xc38
+#define rTxAGC_A_Nss1Index3_Nss1Index0_JAguar	0xc3c
+#define rTxAGC_A_Nss1Index7_Nss1Index4_JAguar	0xc40
+#define rTxAGC_A_Nss2Index1_Nss1Index8_JAguar	0xc44
+#define rTxAGC_A_Nss2Index5_Nss2Index2_JAguar	0xc48
+#define rTxAGC_A_Nss2Index9_Nss2Index6_JAguar	0xc4c
+#define rTxAGC_B_CCK11_CCK1_JAguar				0xe20
+#define rTxAGC_B_Ofdm18_Ofdm6_JAguar				0xe24
+#define rTxAGC_B_Ofdm54_Ofdm24_JAguar			0xe28
+#define rTxAGC_B_MCS3_MCS0_JAguar					0xe2c
+#define rTxAGC_B_MCS7_MCS4_JAguar					0xe30
+#define rTxAGC_B_MCS11_MCS8_JAguar				0xe34
+#define rTxAGC_B_MCS15_MCS12_JAguar				0xe38
+#define rTxAGC_B_Nss1Index3_Nss1Index0_JAguar		0xe3c
+#define rTxAGC_B_Nss1Index7_Nss1Index4_JAguar		0xe40
+#define rTxAGC_B_Nss2Index1_Nss1Index8_JAguar		0xe44
+#define rTxAGC_B_Nss2Index5_Nss2Index2_JAguar		0xe48
+#define rTxAGC_B_Nss2Index9_Nss2Index6_JAguar		0xe4c
+#define bTxAGC_byte0_Jaguar							0xff
+#define bTxAGC_byte1_Jaguar							0xff00
+#define bTxAGC_byte2_Jaguar							0xff0000
+#define bTxAGC_byte3_Jaguar							0xff000000
+
+
+/* TX AGC */
+#define		rTxAGC_A_CCK11_CCK1_Jaguar2	0xc20
+#define		rTxAGC_A_Ofdm18_Ofdm6_Jaguar2	0xc24
+#define		rTxAGC_A_Ofdm54_Ofdm24_Jaguar2	0xc28
+#define		rTxAGC_A_MCS3_MCS0_Jaguar2	0xc2c
+#define		rTxAGC_A_MCS7_MCS4_Jaguar2	0xc30
+#define		rTxAGC_A_MCS11_MCS8_Jaguar2	0xc34
+#define		rTxAGC_A_MCS15_MCS12_Jaguar2	0xc38
+#define		rTxAGC_A_MCS19_MCS16_Jaguar2	0xcd8
+#define		rTxAGC_A_MCS23_MCS20_Jaguar2	0xcdc
+#define		rTxAGC_A_Nss1Index3_Nss1Index0_Jaguar2	0xc3c
+#define		rTxAGC_A_Nss1Index7_Nss1Index4_Jaguar2	0xc40
+#define		rTxAGC_A_Nss2Index1_Nss1Index8_Jaguar2	0xc44
+#define		rTxAGC_A_Nss2Index5_Nss2Index2_Jaguar2	0xc48
+#define		rTxAGC_A_Nss2Index9_Nss2Index6_Jaguar2	0xc4c
+#define		rTxAGC_A_Nss3Index3_Nss3Index0_Jaguar2	0xce0
+#define		rTxAGC_A_Nss3Index7_Nss3Index4_Jaguar2	0xce4
+#define		rTxAGC_A_Nss3Index9_Nss3Index8_Jaguar2	0xce8
+#define		rTxAGC_B_CCK11_CCK1_Jaguar2	0xe20
+#define		rTxAGC_B_Ofdm18_Ofdm6_Jaguar2	0xe24
+#define		rTxAGC_B_Ofdm54_Ofdm24_Jaguar2	0xe28
+#define		rTxAGC_B_MCS3_MCS0_Jaguar2	0xe2c
+#define		rTxAGC_B_MCS7_MCS4_Jaguar2	0xe30
+#define		rTxAGC_B_MCS11_MCS8_Jaguar2	0xe34
+#define		rTxAGC_B_MCS15_MCS12_Jaguar2	0xe38
+#define		rTxAGC_B_MCS19_MCS16_Jaguar2	0xed8
+#define		rTxAGC_B_MCS23_MCS20_Jaguar2	0xedc
+#define		rTxAGC_B_Nss1Index3_Nss1Index0_Jaguar2	0xe3c
+#define		rTxAGC_B_Nss1Index7_Nss1Index4_Jaguar2	0xe40
+#define		rTxAGC_B_Nss2Index1_Nss1Index8_Jaguar2	0xe44
+#define		rTxAGC_B_Nss2Index5_Nss2Index2_Jaguar2	0xe48
+#define		rTxAGC_B_Nss2Index9_Nss2Index6_Jaguar2	0xe4c
+#define		rTxAGC_B_Nss3Index3_Nss3Index0_Jaguar2	0xee0
+#define		rTxAGC_B_Nss3Index7_Nss3Index4_Jaguar2	0xee4
+#define		rTxAGC_B_Nss3Index9_Nss3Index8_Jaguar2	0xee8
+#define		rTxAGC_C_CCK11_CCK1_Jaguar2	0x1820
+#define		rTxAGC_C_Ofdm18_Ofdm6_Jaguar2	0x1824
+#define		rTxAGC_C_Ofdm54_Ofdm24_Jaguar2	0x1828
+#define		rTxAGC_C_MCS3_MCS0_Jaguar2	0x182c
+#define		rTxAGC_C_MCS7_MCS4_Jaguar2	0x1830
+#define		rTxAGC_C_MCS11_MCS8_Jaguar2	0x1834
+#define		rTxAGC_C_MCS15_MCS12_Jaguar2	0x1838
+#define		rTxAGC_C_MCS19_MCS16_Jaguar2	0x18d8
+#define		rTxAGC_C_MCS23_MCS20_Jaguar2	0x18dc
+#define		rTxAGC_C_Nss1Index3_Nss1Index0_Jaguar2	0x183c
+#define		rTxAGC_C_Nss1Index7_Nss1Index4_Jaguar2	0x1840
+#define		rTxAGC_C_Nss2Index1_Nss1Index8_Jaguar2	0x1844
+#define		rTxAGC_C_Nss2Index5_Nss2Index2_Jaguar2	0x1848
+#define		rTxAGC_C_Nss2Index9_Nss2Index6_Jaguar2	0x184c
+#define		rTxAGC_C_Nss3Index3_Nss3Index0_Jaguar2	0x18e0
+#define		rTxAGC_C_Nss3Index7_Nss3Index4_Jaguar2	0x18e4
+#define		rTxAGC_C_Nss3Index9_Nss3Index8_Jaguar2	0x18e8
+#define		rTxAGC_D_CCK11_CCK1_Jaguar2	0x1a20
+#define		rTxAGC_D_Ofdm18_Ofdm6_Jaguar2	0x1a24
+#define		rTxAGC_D_Ofdm54_Ofdm24_Jaguar2	0x1a28
+#define		rTxAGC_D_MCS3_MCS0_Jaguar2	0x1a2c
+#define		rTxAGC_D_MCS7_MCS4_Jaguar2	0x1a30
+#define		rTxAGC_D_MCS11_MCS8_Jaguar2	0x1a34
+#define		rTxAGC_D_MCS15_MCS12_Jaguar2	0x1a38
+#define		rTxAGC_D_MCS19_MCS16_Jaguar2	0x1ad8
+#define		rTxAGC_D_MCS23_MCS20_Jaguar2	0x1adc
+#define		rTxAGC_D_Nss1Index3_Nss1Index0_Jaguar2	0x1a3c
+#define		rTxAGC_D_Nss1Index7_Nss1Index4_Jaguar2	0x1a40
+#define		rTxAGC_D_Nss2Index1_Nss1Index8_Jaguar2	0x1a44
+#define		rTxAGC_D_Nss2Index5_Nss2Index2_Jaguar2	0x1a48
+#define		rTxAGC_D_Nss2Index9_Nss2Index6_Jaguar2	0x1a4c
+#define		rTxAGC_D_Nss3Index3_Nss3Index0_Jaguar2	0x1ae0
+#define		rTxAGC_D_Nss3Index7_Nss3Index4_Jaguar2	0x1ae4
+#define		rTxAGC_D_Nss3Index9_Nss3Index8_Jaguar2	0x1ae8
+/* IQK YN: temporaily mask this part
+ * #define rFPGA0_IQK					0xe28
+ * #define rTx_IQK_Tone_A				0xe30
+ * #define rRx_IQK_Tone_A				0xe34
+ * #define rTx_IQK_PI_A					0xe38
+ * #define rRx_IQK_PI_A					0xe3c */
+
+/* #define rTx_IQK						0xe40 */
+/* #define rRx_IQK						0xe44 */
+/* #define rIQK_AGC_Pts					0xe48 */
+/* #define rIQK_AGC_Rsp					0xe4c */
+/* #define rTx_IQK_Tone_B				0xe50 */
+/* #define rRx_IQK_Tone_B				0xe54 */
+/* #define rTx_IQK_PI_B					0xe58 */
+/* #define rRx_IQK_PI_B					0xe5c */
+/* #define rIQK_AGC_Cont				0xe60 */
+
+
+/* AFE-related */
+#define rA_AFEPwr1_Jaguar					0xc60 /* dynamic AFE power control */
+#define rA_AFEPwr2_Jaguar					0xc64 /* dynamic AFE power control */
+#define rA_Rx_WaitCCA_Tx_CCKRFON_Jaguar	0xc68
+#define rA_Tx_CCKBBON_OFDMRFON_Jaguar	0xc6c
+#define rA_Tx_OFDMBBON_Tx2Rx_Jaguar		0xc70
+#define rA_Tx2Tx_RXCCK_Jaguar				0xc74
+#define rA_Rx_OFDM_WaitRIFS_Jaguar			0xc78
+#define rA_Rx2Rx_BT_Jaguar					0xc7c
+#define rA_sleep_nav_Jaguar					0xc80
+#define rA_pmpd_Jaguar						0xc84
+#define rB_AFEPwr1_Jaguar					0xe60 /* dynamic AFE power control */
+#define rB_AFEPwr2_Jaguar					0xe64 /* dynamic AFE power control */
+#define rB_Rx_WaitCCA_Tx_CCKRFON_Jaguar	0xe68
+#define rB_Tx_CCKBBON_OFDMRFON_Jaguar	0xe6c
+#define rB_Tx_OFDMBBON_Tx2Rx_Jaguar		0xe70
+#define rB_Tx2Tx_RXCCK_Jaguar				0xe74
+#define rB_Rx_OFDM_WaitRIFS_Jaguar			0xe78
+#define rB_Rx2Rx_BT_Jaguar					0xe7c
+#define rB_sleep_nav_Jaguar					0xe80
+#define rB_pmpd_Jaguar						0xe84
+
+
+/* YN: mask these registers temporaily
+ * #define rTx_Power_Before_IQK_A		0xe94
+ * #define rTx_Power_After_IQK_A			0xe9c */
+
+/* #define rRx_Power_Before_IQK_A		0xea0 */
+/* #define rRx_Power_Before_IQK_A_2		0xea4 */
+/* #define rRx_Power_After_IQK_A			0xea8 */
+/* #define rRx_Power_After_IQK_A_2		0xeac */
+
+/* #define rTx_Power_Before_IQK_B		0xeb4 */
+/* #define rTx_Power_After_IQK_B			0xebc */
+
+/* #define rRx_Power_Before_IQK_B		0xec0 */
+/* #define rRx_Power_Before_IQK_B_2		0xec4 */
+/* #define rRx_Power_After_IQK_B			0xec8 */
+/* #define rRx_Power_After_IQK_B_2		0xecc */
+
+
+/* RSSI Dump */
+#define rA_RSSIDump_Jaguar			0xBF0
+#define rB_RSSIDump_Jaguar			0xBF1
+#define rS1_RXevmDump_Jaguar		0xBF4
+#define rS2_RXevmDump_Jaguar		0xBF5
+#define rA_RXsnrDump_Jaguar		0xBF6
+#define rB_RXsnrDump_Jaguar		0xBF7
+#define rA_CfoShortDump_Jaguar		0xBF8
+#define rB_CfoShortDump_Jaguar		0xBFA
+#define rA_CfoLongDump_Jaguar		0xBEC
+#define rB_CfoLongDump_Jaguar		0xBEE
+
+
+/* RF Register
+ *   */
+#define RF_AC_Jaguar				0x00	/*  */
+#define RF_RF_Top_Jaguar			0x07	/*  */
+#define RF_TXLOK_Jaguar				0x08	/*  */
+#define RF_TXAPK_Jaguar				0x0B
+#define RF_CHNLBW_Jaguar 			0x18	/* RF channel and BW switch */
+#define RF_RCK1_Jaguar				0x1c	/*  */
+#define RF_RCK2_Jaguar				0x1d
+#define RF_RCK3_Jaguar			0x1e
+#define RF_ModeTableAddr			0x30
+#define RF_ModeTableData0			0x31
+#define RF_ModeTableData1			0x32
+#define RF_TxLCTank_Jaguar	0x54
+#define RF_APK_Jaguar				0x63
+#define RF_LCK						0xB4
+#define RF_WeLut_Jaguar				0xEF
+
+#define bRF_CHNLBW_MOD_AG_Jaguar	0x70300
+#define bRF_CHNLBW_BW				0xc00
+
+
+/*
+ * RL6052 Register definition
+ *   */
+#define RF_AC						0x00	/*  */
+#define RF_IPA_A					0x0C	/*  */
+#define RF_TXBIAS_A					0x0D
+#define RF_BS_PA_APSET_G9_G11		0x0E
+#define RF_MODE1					0x10	/*  */
+#define RF_MODE2					0x11	/*  */
+#define RF_CHNLBW					0x18	/* RF channel and BW switch */
+#define RF_RCK_OS					0x30	/* RF TX PA control */
+#define RF_TXPA_G1					0x31	/* RF TX PA control */
+#define RF_TXPA_G2					0x32	/* RF TX PA control */
+#define RF_TXPA_G3					0x33	/* RF TX PA control */
+#define RF_0x52						0x52
+#define RF_WE_LUT					0xEF
+
+/*
+ * Bit Mask
+ *
+ * 1. Page1(0x100) */
+#define bBBResetB					0x100	/* Useless now? */
+#define bGlobalResetB				0x200
+#define bOFDMTxStart				0x4
+#define bCCKTxStart					0x8
+#define bCRC32Debug					0x100
+#define bPMACLoopback				0x10
+#define bTxLSIG						0xffffff
+#define bOFDMTxRate					0xf
+#define bOFDMTxReserved			0x10
+#define bOFDMTxLength				0x1ffe0
+#define bOFDMTxParity				0x20000
+#define bTxHTSIG1					0xffffff
+#define bTxHTMCSRate				0x7f
+#define bTxHTBW						0x80
+#define bTxHTLength					0xffff00
+#define bTxHTSIG2					0xffffff
+#define bTxHTSmoothing				0x1
+#define bTxHTSounding				0x2
+#define bTxHTReserved				0x4
+#define bTxHTAggreation				0x8
+#define bTxHTSTBC					0x30
+#define bTxHTAdvanceCoding			0x40
+#define bTxHTShortGI					0x80
+#define bTxHTNumberHT_LTF			0x300
+#define bTxHTCRC8					0x3fc00
+#define bCounterReset				0x10000
+#define bNumOfOFDMTx				0xffff
+#define bNumOfCCKTx					0xffff0000
+#define bTxIdleInterval				0xffff
+#define bOFDMService				0xffff0000
+#define bTxMACHeader				0xffffffff
+#define bTxDataInit					0xff
+#define bTxHTMode					0x100
+#define bTxDataType					0x30000
+#define bTxRandomSeed				0xffffffff
+#define bCCKTxPreamble				0x1
+#define bCCKTxSFD					0xffff0000
+#define bCCKTxSIG					0xff
+#define bCCKTxService				0xff00
+#define bCCKLengthExt				0x8000
+#define bCCKTxLength				0xffff0000
+#define bCCKTxCRC16					0xffff
+#define bCCKTxStatus					0x1
+#define bOFDMTxStatus				0x2
+
+
+/*
+ * 1. PMAC duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF
+ * 1. Page1(0x100)
+ *   */
+#define rPMAC_Reset					0x100
+#define rPMAC_TxStart				0x104
+#define rPMAC_TxLegacySIG			0x108
+#define rPMAC_TxHTSIG1				0x10c
+#define rPMAC_TxHTSIG2				0x110
+#define rPMAC_PHYDebug				0x114
+#define rPMAC_TxPacketNum			0x118
+#define rPMAC_TxIdle					0x11c
+#define rPMAC_TxMACHeader0			0x120
+#define rPMAC_TxMACHeader1			0x124
+#define rPMAC_TxMACHeader2			0x128
+#define rPMAC_TxMACHeader3			0x12c
+#define rPMAC_TxMACHeader4			0x130
+#define rPMAC_TxMACHeader5			0x134
+#define rPMAC_TxDataType			0x138
+#define rPMAC_TxRandomSeed		0x13c
+#define rPMAC_CCKPLCPPreamble		0x140
+#define rPMAC_CCKPLCPHeader		0x144
+#define rPMAC_CCKCRC16				0x148
+#define rPMAC_OFDMRxCRC32OK		0x170
+#define rPMAC_OFDMRxCRC32Er		0x174
+#define rPMAC_OFDMRxParityEr		0x178
+#define rPMAC_OFDMRxCRC8Er			0x17c
+#define rPMAC_CCKCRxRC16Er			0x180
+#define rPMAC_CCKCRxRC32Er			0x184
+#define rPMAC_CCKCRxRC32OK			0x188
+#define rPMAC_TxStatus				0x18c
+
+/*
+ * 3. Page8(0x800)
+ *   */
+#define rFPGA0_RFMOD				0x800	/* RF mode & CCK TxSC */ /* RF BW Setting?? */
+
+#define rFPGA0_TxInfo				0x804	/* Status report?? */
+#define rFPGA0_PSDFunction			0x808
+#define rFPGA0_TxGainStage			0x80c	/* Set TX PWR init gain? */
+
+#define rFPGA0_XA_HSSIParameter1	0x820	/* RF 3 wire register */
+#define rFPGA0_XA_HSSIParameter2	0x824
+#define rFPGA0_XB_HSSIParameter1	0x828
+#define rFPGA0_XB_HSSIParameter2	0x82c
+
+#define	rFPGA0_XA_LSSIParameter		0x840
+#define	rFPGA0_XB_LSSIParameter		0x844
+
+#define rFPGA0_XAB_SwitchControl	0x858	/* RF Channel switch */
+#define rFPGA0_XCD_SwitchControl	0x85c
+
+#define rFPGA0_XAB_RFParameter		0x878	/* RF Parameter */
+#define rFPGA0_XCD_RFParameter		0x87c
+
+#define rFPGA0_AnalogParameter1	0x880	/* Crystal cap setting RF-R/W protection for parameter4?? */
+#define rFPGA0_AnalogParameter2	0x884
+#define rFPGA0_AnalogParameter3	0x888
+#define rFPGA0_AdDaClockEn			0x888	/* enable ad/da clock1 for dual-phy */
+#define rFPGA0_AnalogParameter4	0x88c
+
+#define	rFPGA0_XA_LSSIReadBack		0x8a0	/* Tranceiver LSSI Readback */
+#define	rFPGA0_XB_LSSIReadBack		0x8a4
+#define	rFPGA0_XC_LSSIReadBack		0x8a8
+#define	rFPGA0_XD_LSSIReadBack		0x8ac
+
+#define rFPGA0_XCD_RFPara	0x8b4
+#define	rFPGA0_PSDReport				0x8b4	/* Useless now */
+#define	TransceiverA_HSPI_Readback		0x8b8	/* Transceiver A HSPI Readback */
+#define	TransceiverB_HSPI_Readback		0x8bc	/* Transceiver B HSPI Readback */
+#define	rFPGA0_XAB_RFInterfaceRB		0x8e0	/* Useless now */ /* RF Interface Readback Value */
+#define	rFPGA0_XCD_RFInterfaceRB		0x8e4	/* Useless now */
+
+/*
+ * 4. Page9(0x900)
+ *   */
+#define rFPGA1_RFMOD				0x900	/* RF mode & OFDM TxSC */ /* RF BW Setting?? */
+#define	REG_BB_TX_PATH_SEL_1_8814A		0x93c
+#define	REG_BB_TX_PATH_SEL_2_8814A		0x940
+#define rFPGA1_TxBlock				0x904	/* Useless now */
+#define rFPGA1_DebugSelect			0x908	/* Useless now */
+#define rFPGA1_TxInfo				0x90c	/* Useless now */ /* Status report?? */
+/*Page 19 for TxBF*/
+#define	REG_BB_TXBF_ANT_SET_BF1_8814A	0x19ac
+#define	REG_BB_TXBF_ANT_SET_BF0_8814A	0x19b4
+/*
+ * PageA(0xA00)
+ *   */
+#define rCCK0_System				0xa00
+#define rCCK0_AFESetting				0xa04	/* Disable init gain now */ /* Select RX path by RSSI */
+#define	rCCK0_DSPParameter2			0xa1c	/* SQ threshold */
+#define rCCK0_TxFilter1				0xa20
+#define rCCK0_TxFilter2				0xa24
+#define rCCK0_DebugPort				0xa28	/* debug port and Tx filter3 */
+#define	rCCK0_FalseAlarmReport			0xa2c	/* 0xa2d	useless now 0xa30-a4f channel report */
+
+/*
+ * PageB(0xB00)
+ *   */
+#define rPdp_AntA				0xb00
+#define rPdp_AntA_4				0xb04
+#define rConfig_Pmpd_AntA			0xb28
+#define rConfig_AntA					0xb68
+#define rConfig_AntB					0xb6c
+#define rPdp_AntB					0xb70
+#define rPdp_AntB_4					0xb74
+#define rConfig_Pmpd_AntB			0xb98
+#define rAPK							0xbd8
+
+/*
+ * 6. PageC(0xC00)
+ *   */
+#define rOFDM0_LSTF					0xc00
+
+#define rOFDM0_TRxPathEnable		0xc04
+#define rOFDM0_TRMuxPar			0xc08
+#define rOFDM0_TRSWIsolation		0xc0c
+
+#define rOFDM0_XARxAFE				0xc10  /* RxIQ DC offset, Rx digital filter, DC notch filter */
+#define rOFDM0_XARxIQImbalance    	0xc14  /* RxIQ imblance matrix */
+#define rOFDM0_XBRxAFE		0xc18
+#define rOFDM0_XBRxIQImbalance	0xc1c
+#define rOFDM0_XCRxAFE		0xc20
+#define rOFDM0_XCRxIQImbalance	0xc24
+#define rOFDM0_XDRxAFE		0xc28
+#define rOFDM0_XDRxIQImbalance	0xc2c
+
+#define rOFDM0_RxDetector1			0xc30  /* PD, BW & SBD	 */ /* DM tune init gain */
+#define rOFDM0_RxDetector2			0xc34  /* SBD & Fame Sync. */
+#define rOFDM0_RxDetector3			0xc38  /* Frame Sync. */
+#define rOFDM0_RxDetector4			0xc3c  /* PD, SBD, Frame Sync & Short-GI */
+
+#define rOFDM0_RxDSP				0xc40  /* Rx Sync Path */
+#define rOFDM0_CFOandDAGC			0xc44  /* CFO & DAGC */
+#define rOFDM0_CCADropThreshold	0xc48 /* CCA Drop threshold */
+#define rOFDM0_ECCAThreshold		0xc4c /* energy CCA */
+
+#define rOFDM0_XAAGCCore1			0xc50	/* DIG */
+#define rOFDM0_XAAGCCore2			0xc54
+#define rOFDM0_XBAGCCore1			0xc58
+#define rOFDM0_XBAGCCore2			0xc5c
+#define rOFDM0_XCAGCCore1			0xc60
+#define rOFDM0_XCAGCCore2			0xc64
+#define rOFDM0_XDAGCCore1			0xc68
+#define rOFDM0_XDAGCCore2			0xc6c
+
+#define rOFDM0_AGCParameter1		0xc70
+#define rOFDM0_AGCParameter2		0xc74
+#define rOFDM0_AGCRSSITable		0xc78
+#define rOFDM0_HTSTFAGC			0xc7c
+
+#define rOFDM0_XATxIQImbalance		0xc80	/* TX PWR TRACK and DIG */
+#define rOFDM0_XATxAFE				0xc84
+#define rOFDM0_XBTxIQImbalance		0xc88
+#define rOFDM0_XBTxAFE				0xc8c
+#define rOFDM0_XCTxIQImbalance		0xc90
+#define rOFDM0_XCTxAFE		0xc94
+#define rOFDM0_XDTxIQImbalance		0xc98
+#define rOFDM0_XDTxAFE				0xc9c
+
+#define rOFDM0_RxIQExtAnta			0xca0
+#define rOFDM0_TxCoeff1				0xca4
+#define rOFDM0_TxCoeff2				0xca8
+#define rOFDM0_TxCoeff3				0xcac
+#define rOFDM0_TxCoeff4				0xcb0
+#define rOFDM0_TxCoeff5				0xcb4
+#define rOFDM0_TxCoeff6				0xcb8
+#define rOFDM0_RxHPParameter		0xce0
+#define rOFDM0_TxPseudoNoiseWgt	0xce4
+#define rOFDM0_FrameSync			0xcf0
+#define rOFDM0_DFSReport			0xcf4
+
+/*
+ * 7. PageD(0xD00)
+ *   */
+#define rOFDM1_LSTF					0xd00
+#define rOFDM1_TRxPathEnable		0xd04
+
+/*
+ * 8. PageE(0xE00)
+ *   */
+#define rTxAGC_A_Rate18_06			0xe00
+#define rTxAGC_A_Rate54_24			0xe04
+#define rTxAGC_A_CCK1_Mcs32		0xe08
+#define rTxAGC_A_Mcs03_Mcs00		0xe10
+#define rTxAGC_A_Mcs07_Mcs04		0xe14
+#define rTxAGC_A_Mcs11_Mcs08		0xe18
+#define rTxAGC_A_Mcs15_Mcs12		0xe1c
+
+#define rTxAGC_B_Rate18_06			0x830
+#define rTxAGC_B_Rate54_24			0x834
+#define rTxAGC_B_CCK1_55_Mcs32	0x838
+#define rTxAGC_B_Mcs03_Mcs00		0x83c
+#define rTxAGC_B_Mcs07_Mcs04		0x848
+#define rTxAGC_B_Mcs11_Mcs08		0x84c
+#define rTxAGC_B_Mcs15_Mcs12		0x868
+#define rTxAGC_B_CCK11_A_CCK2_11	0x86c
+
+#define rFPGA0_IQK					0xe28
+#define rTx_IQK_Tone_A				0xe30
+#define rRx_IQK_Tone_A				0xe34
+#define rTx_IQK_PI_A				0xe38
+#define rRx_IQK_PI_A				0xe3c
+
+#define rTx_IQK						0xe40
+#define rRx_IQK						0xe44
+#define rIQK_AGC_Pts					0xe48
+#define rIQK_AGC_Rsp				0xe4c
+#define rTx_IQK_Tone_B				0xe50
+#define rRx_IQK_Tone_B				0xe54
+#define rTx_IQK_PI_B					0xe58
+#define rRx_IQK_PI_B					0xe5c
+#define rIQK_AGC_Cont				0xe60
+
+#define rBlue_Tooth					0xe6c
+#define rRx_Wait_CCA				0xe70
+#define rTx_CCK_RFON				0xe74
+#define rTx_CCK_BBON				0xe78
+#define rTx_OFDM_RFON				0xe7c
+#define rTx_OFDM_BBON				0xe80
+#define rTx_To_Rx					0xe84
+#define rTx_To_Tx					0xe88
+#define rRx_CCK						0xe8c
+
+#define rTx_Power_Before_IQK_A		0xe94
+#define rTx_Power_After_IQK_A		0xe9c
+
+#define rRx_Power_Before_IQK_A		0xea0
+#define rRx_Power_Before_IQK_A_2	0xea4
+#define rRx_Power_After_IQK_A		0xea8
+#define rRx_Power_After_IQK_A_2		0xeac
+
+#define rTx_Power_Before_IQK_B		0xeb4
+#define rTx_Power_After_IQK_B		0xebc
+
+#define rRx_Power_Before_IQK_B		0xec0
+#define rRx_Power_Before_IQK_B_2	0xec4
+#define rRx_Power_After_IQK_B		0xec8
+#define rRx_Power_After_IQK_B_2		0xecc
+
+#define rRx_OFDM					0xed0
+#define rRx_Wait_RIFS				0xed4
+#define rRx_TO_Rx					0xed8
+#define rStandby						0xedc
+#define rSleep						0xee0
+#define rPMPD_ANAEN				0xeec
+
+
+/* 2. Page8(0x800) */
+#define bRFMOD						0x1	/* Reg 0x800 rFPGA0_RFMOD */
+#define bJapanMode					0x2
+#define bCCKTxSC					0x30
+#define bCCKEn						0x1000000
+#define bOFDMEn						0x2000000
+#define bXBTxAGC                  			0xf00	/* Reg 80c rFPGA0_TxGainStage */
+#define bXCTxAGC			0xf000
+#define bXDTxAGC			0xf0000
+
+/* 4. PageA(0xA00) */
+#define bCCKBBMode                			0x3	/* Useless */
+#define bCCKTxPowerSaving		0x80
+#define bCCKRxPowerSaving		0x40
+
+#define bCCKSideBand              		0x10	/* Reg 0xa00 rCCK0_System 20/40 switch */
+
+#define bCCKScramble              		0x8	/* Useless */
+#define bCCKAntDiversity			0x8000
+#define bCCKCarrierRecovery		0x4000
+#define bCCKTxRate			0x3000
+#define bCCKDCCancel			0x0800
+#define bCCKISICancel			0x0400
+#define bCCKMatchFilter		0x0200
+#define bCCKEqualizer			0x0100
+#define bCCKPreambleDetect		0x800000
+#define bCCKFastFalseCCA		0x400000
+#define bCCKChEstStart		0x300000
+#define bCCKCCACount		0x080000
+#define bCCKcs_lim			0x070000
+#define bCCKBistMode			0x80000000
+#define bCCKCCAMask			0x40000000
+#define bCCKTxDACPhase		0x4
+#define bCCKRxADCPhase         	   	0x20000000   /* r_rx_clk */
+#define bCCKr_cp_mode0		0x0100
+#define bCCKTxDCOffset		0xf0
+#define bCCKRxDCOffset		0xf
+#define bCCKCCAMode			0xc000
+#define bCCKFalseCS_lim		0x3f00
+#define bCCKCS_ratio			0xc00000
+#define bCCKCorgBit_sel		0x300000
+#define bCCKPD_lim			0x0f0000
+#define bCCKNewCCA		0x80000000
+#define bCCKRxHPofIG		0x8000
+#define bCCKRxIG			0x7f00
+#define bCCKLNAPolarity		0x800000
+#define bCCKRx1stGain		0x7f0000
+#define bCCKRFExtend              		0x20000000 /* CCK Rx Iinital gain polarity */
+#define bCCKRxAGCSatLevel		0x1f000000
+#define bCCKRxAGCSatCount		0xe0
+#define bCCKRxRFSettle            		0x1f       /* AGCsamp_dly */
+#define bCCKFixedRxAGC		0x8000
+/* #define bCCKRxAGCFormat		0x4000 */   /* remove to HSSI register 0x824 */
+#define bCCKAntennaPolarity		0x2000
+#define bCCKTxFilterType		0x0c00
+#define bCCKRxAGCReportType		0x0300
+#define bCCKRxDAGCEn		0x80000000
+#define bCCKRxDAGCPeriod		0x20000000
+#define bCCKRxDAGCSatLevel		0x1f000000
+#define bCCKTimingRecovery		0x800000
+#define bCCKTxC0			0x3f0000
+#define bCCKTxC1			0x3f000000
+#define bCCKTxC2			0x3f
+#define bCCKTxC3			0x3f00
+#define bCCKTxC4			0x3f0000
+#define bCCKTxC5			0x3f000000
+#define bCCKTxC6			0x3f
+#define bCCKTxC7			0x3f00
+#define bCCKDebugPort		0xff0000
+#define bCCKDACDebug		0x0f000000
+#define bCCKFalseAlarmEnable		0x8000
+#define bCCKFalseAlarmRead		0x4000
+#define bCCKTRSSI			0x7f
+#define bCCKRxAGCReport		0xfe
+#define bCCKRxReport_AntSel		0x80000000
+#define bCCKRxReport_MFOff		0x40000000
+#define bCCKRxRxReport_SQLoss	0x20000000
+#define bCCKRxReport_Pktloss		0x10000000
+#define bCCKRxReport_Lockedbit	0x08000000
+#define bCCKRxReport_RateError	0x04000000
+#define bCCKRxReport_RxRate		0x03000000
+#define bCCKRxFACounterLower	0xff
+#define bCCKRxFACounterUpper	0xff000000
+#define bCCKRxHPAGCStart		0xe000
+#define bCCKRxHPAGCFinal		0x1c00
+#define bCCKRxFalseAlarmEnable	0x8000
+#define bCCKFACounterFreeze		0x4000
+#define bCCKTxPathSel		0x10000000
+#define bCCKDefaultRxPath		0xc000000
+#define bCCKOptionRxPath		0x3000000
+
+#define		RF_T_METER_88E				0x42
+
+/* 6. PageE(0xE00) */
+#define bSTBCEn                  			0x4	/* Useless */
+#define bAntennaMapping		0x10
+#define bNss				0x20
+#define bCFOAntSumD		0x200
+#define bPHYCounterReset		0x8000000
+#define bCFOReportGet			0x4000000
+#define bOFDMContinueTx		0x10000000
+#define bOFDMSingleCarrier		0x20000000
+#define bOFDMSingleTone		0x40000000
+
+
+/*
+ * Other Definition
+ *   */
+
+#define bEnable                   0x1	/* Useless */
+#define bDisable                  0x0
+
+/* byte endable for srwrite */
+#define bByte0                    		0x1	/* Useless */
+#define bByte1		0x2
+#define bByte2		0x4
+#define bByte3		0x8
+#define bWord0		0x3
+#define bWord1		0xc
+#define bDWord		0xf
+
+/* for PutRegsetting & GetRegSetting BitMask */
+#define bMaskByte0                		0xff	/* Reg 0xc50 rOFDM0_XAAGCCore~0xC6f */
+#define bMaskByte1		0xff00
+#define bMaskByte2		0xff0000
+#define bMaskByte3		0xff000000
+#define bMaskHWord	0xffff0000
+#define bMaskLWord		0x0000ffff
+#define bMaskDWord	0xffffffff
+#define bMaskH3Bytes				0xffffff00
+#define bMask12Bits				0xfff
+#define bMaskH4Bits				0xf0000000
+#define bMaskOFDM_D			0xffc00000
+#define bMaskCCK				0x3f3f3f3f
+#define bMask7bits				0x7f
+#define bMaskByte2HighNibble			0x00f00000
+#define bMaskByte3LowNibble				0x0f000000
+#define bMaskL3Bytes			0x00ffffff
+
+/*--------------------------Define Parameters-------------------------------*/
+
+
+#endif
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/include/Hal8814PwrSeq.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/Hal8814PwrSeq.h
--- linux-5.6.3/3rdparty/rtl8821ce/include/Hal8814PwrSeq.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/Hal8814PwrSeq.h	2020-04-10 16:35:06.845661421 +0300
@@ -0,0 +1,231 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+
+
+#ifndef __HAL8814PWRSEQ_H__
+#define __HAL8814PWRSEQ_H__
+
+#include "HalPwrSeqCmd.h"
+
+/*
+	Check document WB-110628-DZ-RTL8195 (Jaguar) Power Architecture-R04.pdf
+	There are 6 HW Power States:
+	0: POFF--Power Off
+	1: PDN--Power Down
+	2: CARDEMU--Card Emulation
+	3: ACT--Active Mode
+	4: LPS--Low Power State
+	5: SUS--Suspend
+
+	The transision from different states are defined below
+	TRANS_CARDEMU_TO_ACT
+	TRANS_ACT_TO_CARDEMU
+	TRANS_CARDEMU_TO_SUS
+	TRANS_SUS_TO_CARDEMU
+	TRANS_CARDEMU_TO_PDN
+	TRANS_ACT_TO_LPS
+	TRANS_LPS_TO_ACT
+
+	TRANS_END
+*/
+#define	RTL8814A_TRANS_CARDEMU_TO_ACT_STEPS	16
+#define	RTL8814A_TRANS_ACT_TO_CARDEMU_STEPS	20
+#define	RTL8814A_TRANS_CARDEMU_TO_SUS_STEPS	17
+#define	RTL8814A_TRANS_SUS_TO_CARDEMU_STEPS	15
+#define	RTL8814A_TRANS_CARDEMU_TO_PDN_STEPS	17
+#define	RTL8814A_TRANS_PDN_TO_CARDEMU_STEPS	16
+#define	RTL8814A_TRANS_ACT_TO_LPS_STEPS	20
+#define	RTL8814A_TRANS_LPS_TO_ACT_STEPS	15
+#define	RTL8814A_TRANS_END_STEPS	1
+
+
+#define RTL8814A_TRANS_CARDEMU_TO_ACT														\
+	/* format */																\
+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, 0},/* disable SW LPS 0x04[10]=0*/	\
+	{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT1, BIT1},/* wait till 0x04[17] = 1    power ready*/	\
+	{0x002B, PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0}, /* ??0x28[24]=1, enable pll phase select*/ \
+	{0x0015, PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, (BIT3 | BIT2 | BIT1), (BIT3 | BIT2 | BIT1)},/* 0x14[11:9]=3'b111, OCP current threshold = 1.5A */ \
+	{0x002D, PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x0E, 0x08},/* 0x2C[11:9]=3'b100, select lpf R3 */ \
+	{0x002D, PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x70, 0x50},/* 0x2C[14:12]=3'b101, select lpf Rs*/ \
+	{0x007B, PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT6, BIT6},/* 0x78[30]=1'b1, SDM order select*/ \
+	/*{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, 0}, */ /* disable HWPDN 0x04[15]=0*/ \
+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3, 0},/* disable WL suspend*/	\
+	{0x00F0, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, 0},/* */	\
+	{0x0081, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x30, 0x20},/* */	\
+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0},/* polling until return 0*/	\
+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT0, 0},/**/
+
+#define RTL8814A_TRANS_ACT_TO_CARDEMU													\
+	/* format */																\
+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
+	{0x0c00, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x04}, /* 0xc00[7:0] = 4	turn off 3-wire */	\
+	{0x0e00, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x04}, /* 0xe00[7:0] = 4	turn off 3-wire */	\
+	{0x0002, PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0},  /* 0x2[0] = 0	 RESET BB, CLOSE RF */	\
+	{0x0002, PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_US}, /*Delay 1us*/	\
+	{0x0002, PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0},  /* Whole BB is reset*/			\
+	{0x1002, ~PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0},  /* 0x2[0] = 0	 RESET BB, CLOSE RF */	\
+	{0x0002, ~PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_US}, /*Delay 1us*/	\
+	{0x1002, ~PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0},  /* Whole BB is reset*/			\
+	{0x001F, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0},  /*0x1F[7:0] = 0 turn off RF*/	\
+	/*{0x004E, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, 0},*/  /*0x4C[23] = 0x4E[7] = 0, switch DPDT_SEL_P output from register 0x65[2] */	\
+	{0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x28},   /* 0x07[7:0] = 0x28 sps pwm mode 0x2a for BT coex*/	\
+	{0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x02, 0},   /*0x8[1] = 0 ANA clk = 500k */	\
+	/*{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0 | BIT1, 0},*/   /*  0x02[1:0] = 0	reset BB */	\
+	{0x0066, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, 0},   /*0x66[7]=0, disable ckreq for gpio7 output SUS */	\
+	{0x0041, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0},   /*0x41[4]=0, disable sic for gpio7 output SUS */	\
+	{0x0042, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0},   /*0x42[1]=0, disable ckout for gpio7 output SUS */	\
+	{0x004e, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT5, BIT5},   /*0x4E[5]=1, disable LED2 for gpio7 output SUS */	\
+	{0x0041, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0},   /*0x41[0]=0, disable uart for gpio7 output SUS */	\
+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1}, /*0x04[9] = 1 turn off MAC by HW state machine*/	\
+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT1, 0}, /*wait till 0x04[9] = 0 polling until return 0 to disable*/
+
+#define RTL8814A_TRANS_CARDEMU_TO_SUS													\
+	/* format */								\
+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
+	{0x0061, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x0F, 0x0c},\
+	{0x0061, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x0F, 0x0E},\
+	{0x0062, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x0F, 0x07},/* gpio11 input mode, gpio10~8 output mode */	\
+	{0x0045, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x00},/* gpio 0~7 output same value as input ?? */	\
+	{0x0046, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xff},/* gpio0~7 output mode */	\
+	{0x0047, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0},/* 0x47[7:0] = 00 gpio mode */	\
+	{0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0},/* suspend option all off */	\
+	{0x0015, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT5, BIT5},/*0x14[13] = 1 turn on ZCD */	\
+	{0x0015, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT6, BIT6},/* 0x14[14] =1 trun on ZCD */	\
+	{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, BIT4},/*0x23[4] = 1 hpon LDO sleep mode */	\
+	{0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0},/*0x8[1] = 0 ANA clk = 500k */	\
+	{0x0091, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xA0, 0xA0}, /* 0x91[7]=1 0x91[5]=1 , disable sps, ldo sleep mode */	\
+	{0x0070, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3, BIT3}, /* 0x70[3]=1 enable mainbias polling */	\
+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3, BIT3}, /*0x04[11] = 1 enable WL suspend */
+
+#define RTL8814A_TRANS_SUS_TO_CARDEMU													\
+	/* format */								\
+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3, 0}, /*0x04[11] = 0 enable WL suspend*/   \
+	{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x10, 0},/*0x23[4] = 0 hpon LDO sleep mode leave */	\
+	{0x0015, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT6, 0},/* 0x14[14] =0 trun off ZCD */	\
+	{0x0015, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT5, 0},/*0x14[13] = 0 turn off ZCD */	\
+	{0x0046, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x00},/* gpio0~7 input mode */	\
+	{0x0062, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x00},/* gpio11 input mode, gpio10~8 input mode */
+
+#define RTL8814A_TRANS_CARDEMU_TO_CARDDIS													\
+	/* format */																\
+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
+	/**{0x0194, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0}, //0x194[0]=0 , disable 32K clock*/	\
+	/**{0x0093, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x94}, //0x93 = 0x94 , 90[30] =0 enable 500k ANA clock .switch clock from 12M to 500K , 90 [26] =0 disable EEprom loader clock*/	\
+	{0x0003, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, 0}, /*0x03[2] = 0, reset 3081*/	\
+	{0x0080, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x01}, /*0x80 = 05h if reload fw, fill the default value of host_CPU handshake field*/	\
+	{0x0081, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x30}, /*0x80 = 05h if reload fw, fill the default value of host_CPU handshake field*/	\
+	/*{0x0042, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xF0, 0xcc},*/   \
+	/*{0x0042, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xF0, 0xEC},*/   \
+	/*{0x0043, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x07},*/  /* gpio11 input mode, gpio10~8 output mode */	\
+	{0x0045, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x00},/* gpio 0~7 output same value as input ?? */	\
+	{0x0046, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xff},/* gpio0~7 output mode */	\
+	{0x0047, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0},/* 0x47[7:0] = 00 gpio mode */	\
+	{0x0015, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT6, BIT6},/* 0x15[6] =1 trun on ZCD output */	\
+	{0x0015, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT5, BIT5},/*0x15[5] = 1 turn on ZCD */	\
+	{0x0012, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT6, 0},/*0x12[6] = 0 force PFM mode */	\
+	{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, BIT4},/*0x23[4] = 1 hpon LDO sleep mode */	\
+	{0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0},/*0x8[1] = 0 ANA clk = 500k */	\
+	{0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x20}, /*0x07 = 0x20 , SOP option to disable BG/MB*/	\
+	{0x001f, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0}, /* 0x01f[1]=0 , disable RFC_0  control  REG_RF_CTRL_8814A */	\
+	{0x0020, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0}, /* 0x020[1]=0 , disable RFC_1  control  REG_RF_CTRL_8814A */	\
+	{0x0021, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0}, /* 0x021[1]=0 , disable RFC_2  control  REG_RF_CTRL_8814A */	\
+	{0x0076, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0}, /* 0x076[1]=0 , disable RFC_3  control REG_OPT_CTRL_8814A +2 */	\
+	{0x0091, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xA0, 0xA0}, /* 0x91[7]=1 0x91[5]=1 , disable sps, ldo sleep mode */	\
+	{0x0070, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3, BIT3}, /* 0x70[3]=1 enable mainbias polling */	\
+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3, BIT3}, /*0x04[11] = 1 enable WL suspend*/
+
+#define RTL8814A_TRANS_CARDDIS_TO_CARDEMU													\
+	/* format */																\
+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/                       \
+	{0x0012, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT6, BIT6},/*0x12[6] = 1 force PWM mode */	\
+	{0x0015, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT5, 0},/*0x15[5] = 0 turn off ZCD */	\
+	{0x0015, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT6, 0},/* 0x15[6] =0 trun off ZCD output */	\
+	{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0},/*0x23[4] = 0 hpon LDO leave sleep mode */	\
+	{0x0046, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x00},/* gpio0~7 input mode */	\
+	{0x0062, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x00}, /* gpio11 input mode, gpio10~8 input mode */ \
+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, 0}, /*0x04[10] = 0, enable SW LPS PCIE only*/	\
+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3, 0}, /*0x04[11] = 0, enable WL suspend*/	\
+	/*{0x0003, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, BIT2},*/ /*0x03[2] = 1, enable 3081*/	\
+	{0x0301, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0},/*PCIe DMA start*/		\
+	{0x0071, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, 0},/*0x70[10] = 0, CPHY_MBIAS_EN disable*/
+
+
+#define RTL8814A_TRANS_CARDEMU_TO_PDN												\
+	/* format */																\
+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/	\
+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, BIT7},/* 0x04[15] = 1*/
+
+#define RTL8814A_TRANS_PDN_TO_CARDEMU												\
+	/* format */																\
+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/	\
+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, 0},/* 0x04[15] = 0*/
+
+#define RTL8814A_TRANS_ACT_TO_LPS														\
+	/* format */																\
+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
+	{0x0301, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF},/*PCIe DMA stop*/	\
+	{0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x7F},/*Tx Pause*/		\
+	{0x05F8, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/	\
+	{0x05F9, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/	\
+	{0x05FA, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/	\
+	{0x05FB, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/	\
+	{0x0c00, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x04}, /* 0xc00[7:0] = 4	turn off 3-wire */	\
+	{0x0e00, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x04}, /* 0xe00[7:0] = 4	turn off 3-wire */	\
+	{0x0002, PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0},/*CCK and OFDM are disabled, and clock are gated, and RF closed*/	\
+	{0x0002, PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_US},/*Delay 1us*/	\
+	{0x0002, PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0},  /* Whole BB is reset*/			\
+	{0x1002, ~PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0},/*CCK and OFDM are disabled, and clock are gated, and RF closed*/	\
+	{0x0002, ~PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_US},/*Delay 1us*/	\
+	{0x1002, ~PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0},  /* Whole BB is reset*/			\
+	{0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x03},/*Reset MAC TRX*/			\
+	{0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0},/*check if removed later*/		\
+	{0x05F1, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0},/*Respond TxOK to scheduler*/
+
+
+#define RTL8814A_TRANS_LPS_TO_ACT															\
+	/* format */																\
+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/	\
+	{0x0080, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, 0xFF, 0x84}, /*SDIO RPWM*/	\
+	{0xFE58, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x84}, /*USB RPWM*/	\
+	{0x0361, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x84}, /*PCIe RPWM*/	\
+	{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_MS}, /* Delay*/	\
+	{0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0}, /*.	0x08[4] = 0		 switch TSF to 40M*/	\
+	{0x0109, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT7, 0}, /* Polling 0x109[7]=0  TSF in 40M*/			\
+	/*{0x0029, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT6 | BIT7, 0}, */ /*.	??0x29[7:6] = 2b'00	 enable BB clock*/	\
+	{0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1}, /*.	0x101[1] = 1*/					\
+	{0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF}, /*.	0x100[7:0] = 0xFF	 enable WMAC TRX*/	\
+	{0x0002, PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1 | BIT0, BIT1 | BIT0}, /*.	0x02[1:0] = 2b'11	 enable BB macro*/	\
+	{0x1002, ~PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1 | BIT0, BIT1 | BIT0}, /*.	0x1002[1:0] = 2b'11	 enable BB macro*/	\
+	{0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0}, /*.	0x522 = 0*/
+
+#define RTL8814A_TRANS_END																\
+	/* format */																\
+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/		\
+	{0xFFFF, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, 0, PWR_CMD_END, 0, 0},
+
+
+extern WLAN_PWR_CFG rtl8814A_power_on_flow[RTL8814A_TRANS_CARDEMU_TO_ACT_STEPS + RTL8814A_TRANS_END_STEPS];
+extern WLAN_PWR_CFG rtl8814A_radio_off_flow[RTL8814A_TRANS_ACT_TO_CARDEMU_STEPS + RTL8814A_TRANS_END_STEPS];
+extern WLAN_PWR_CFG rtl8814A_card_disable_flow[RTL8814A_TRANS_ACT_TO_CARDEMU_STEPS + RTL8814A_TRANS_CARDEMU_TO_PDN_STEPS + RTL8814A_TRANS_END_STEPS];
+extern WLAN_PWR_CFG rtl8814A_card_enable_flow[RTL8814A_TRANS_ACT_TO_CARDEMU_STEPS + RTL8814A_TRANS_CARDEMU_TO_PDN_STEPS + RTL8814A_TRANS_END_STEPS];
+extern WLAN_PWR_CFG rtl8814A_suspend_flow[RTL8814A_TRANS_ACT_TO_CARDEMU_STEPS + RTL8814A_TRANS_CARDEMU_TO_SUS_STEPS + RTL8814A_TRANS_END_STEPS];
+extern WLAN_PWR_CFG rtl8814A_resume_flow[RTL8814A_TRANS_ACT_TO_CARDEMU_STEPS + RTL8814A_TRANS_CARDEMU_TO_SUS_STEPS + RTL8814A_TRANS_END_STEPS];
+extern WLAN_PWR_CFG rtl8814A_hwpdn_flow[RTL8814A_TRANS_ACT_TO_CARDEMU_STEPS + RTL8814A_TRANS_CARDEMU_TO_PDN_STEPS + RTL8814A_TRANS_END_STEPS];
+extern WLAN_PWR_CFG rtl8814A_enter_lps_flow[RTL8814A_TRANS_ACT_TO_LPS_STEPS + RTL8814A_TRANS_END_STEPS];
+extern WLAN_PWR_CFG rtl8814A_leave_lps_flow[RTL8814A_TRANS_LPS_TO_ACT_STEPS + RTL8814A_TRANS_END_STEPS];
+
+#endif /* __HAL8814PWRSEQ_H__ */
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/include/Hal8821APwrSeq.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/Hal8821APwrSeq.h
--- linux-5.6.3/3rdparty/rtl8821ce/include/Hal8821APwrSeq.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/Hal8821APwrSeq.h	2020-04-10 16:35:06.845661421 +0300
@@ -0,0 +1,200 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2016 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#ifndef REALTEK_POWER_SEQUENCE_8821
+#define REALTEK_POWER_SEQUENCE_8821
+
+#include "HalPwrSeqCmd.h"
+
+/*
+	Check document WM-20130516-JackieLau-RTL8821A_Power_Architecture-R10.vsd
+	There are 6 HW Power States:
+	0: POFF--Power Off
+	1: PDN--Power Down
+	2: CARDEMU--Card Emulation
+	3: ACT--Active Mode
+	4: LPS--Low Power State
+	5: SUS--Suspend
+
+	The transision from different states are defined below
+	TRANS_CARDEMU_TO_ACT
+	TRANS_ACT_TO_CARDEMU
+	TRANS_CARDEMU_TO_SUS
+	TRANS_SUS_TO_CARDEMU
+	TRANS_CARDEMU_TO_PDN
+	TRANS_ACT_TO_LPS
+	TRANS_LPS_TO_ACT
+
+	TRANS_END
+*/
+#define	RTL8821A_TRANS_CARDEMU_TO_ACT_STEPS	25
+#define	RTL8821A_TRANS_ACT_TO_CARDEMU_STEPS	15
+#define	RTL8821A_TRANS_CARDEMU_TO_SUS_STEPS	15
+#define	RTL8821A_TRANS_SUS_TO_CARDEMU_STEPS	15
+#define RTL8821A_TRANS_CARDDIS_TO_CARDEMU_STEPS	15
+#define	RTL8821A_TRANS_CARDEMU_TO_PDN_STEPS	15
+#define	RTL8821A_TRANS_PDN_TO_CARDEMU_STEPS	15
+#define	RTL8821A_TRANS_ACT_TO_LPS_STEPS	15
+#define	RTL8821A_TRANS_LPS_TO_ACT_STEPS	15
+#define	RTL8821A_TRANS_END_STEPS	1
+
+
+#define RTL8821A_TRANS_CARDEMU_TO_ACT														\
+	/* format */																\
+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
+	{0x0020, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0}, /*0x20[0] = 1b'1 enable LDOA12 MACRO block for all interface*/   \
+	{0x0067, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0}, /*0x67[0] = 0 to disable BT_GPS_SEL pins*/	\
+	{0x0001, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_DELAY, 1, PWRSEQ_DELAY_MS},/*Delay 1ms*/   \
+	{0x0000, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT5, 0}, /*0x00[5] = 1b'0 release analog Ips to digital ,1:isolation*/   \
+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, (BIT4 | BIT3 | BIT2), 0},/* disable SW LPS 0x04[10]=0 and WLSUS_EN 0x04[12:11]=0*/	\
+	{0x0075, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0 , BIT0},/* Disable USB suspend */	\
+	{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT1, BIT1},/* wait till 0x04[17] = 1    power ready*/	\
+	{0x0075, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0 , 0},/* Enable USB suspend */	\
+	{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0},/* release WLON reset  0x04[16]=1*/	\
+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, 0},/* disable HWPDN 0x04[15]=0*/	\
+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, (BIT4 | BIT3), 0},/* disable WL suspend*/	\
+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0},/* polling until return 0*/	\
+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT0, 0},/**/	\
+	{0x004F, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0},/*0x4C[24] = 0x4F[0] = 1, switch DPDT_SEL_P output from WL BB */\
+	{0x0067, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, (BIT5 | BIT4), (BIT5 | BIT4)},/*0x66[13] = 0x67[5] = 1, switch for PAPE_G/PAPE_A from WL BB ; 0x66[12] = 0x67[4] = 1, switch LNAON from WL BB */\
+	{0x0025, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT6, 0},/*anapar_mac<118> , 0x25[6]=0 by wlan single function*/\
+	{0x0049, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1},/*Enable falling edge triggering interrupt*/\
+	{0x0063, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1},/*Enable GPIO9 interrupt mode*/\
+	{0x0062, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0},/*Enable GPIO9 input mode*/\
+	{0x0058, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0},/*Enable HSISR GPIO[C:0] interrupt*/\
+	{0x005A, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1},/*Enable HSISR GPIO9 interrupt*/\
+	{0x007A, PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x3A},/*0x7A = 0x3A start BT*/\
+	{0x002E, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF , 0x82 },/* 0x2C[23:12]=0x820 ; XTAL trim */ \
+	{0x0010, PWR_CUT_A_MSK , PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT6 , BIT6 },/* 0x10[6]=1 ; MP�s�W���0x2C�������v�A����0x10[6]�]��1�~����WLAN���� */ \
+
+
+#define RTL8821A_TRANS_ACT_TO_CARDEMU													\
+	/* format */																\
+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
+	{0x001F, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0},/*0x1F[7:0] = 0 turn off RF*/	\
+	{0x004F, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0},/*0x4C[24] = 0x4F[0] = 0, switch DPDT_SEL_P output from register 0x65[2] */\
+	{0x0049, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0},/*Enable rising edge triggering interrupt*/ \
+	{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0},/* release WLON reset  0x04[16]=1*/	\
+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1}, /*0x04[9] = 1 turn off MAC by HW state machine*/	\
+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT1, 0}, /*wait till 0x04[9] = 0 polling until return 0 to disable*/	\
+	{0x0000, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT5, BIT5}, /*0x00[5] = 1b'1 analog Ips to digital ,1:isolation*/   \
+	{0x0020, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0}, /*0x20[0] = 1b'0 disable LDOA12 MACRO block*/   \
+
+
+#define RTL8821A_TRANS_CARDEMU_TO_SUS													\
+	/* format */																\
+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4 | BIT3, (BIT4 | BIT3)}, /*0x04[12:11] = 2b'11 enable WL suspend for PCIe*/	\
+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT4, BIT3}, /*0x04[12:11] = 2b'01 enable WL suspend*/	\
+	{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, BIT4}, /*0x23[4] = 1b'1 12H LDO enter sleep mode*/   \
+	{0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x20}, /*0x07[7:0] = 0x20 SDIO SOP option to disable BG/MB/ACK/SWR*/   \
+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT4, BIT3 | BIT4}, /*0x04[12:11] = 2b'11 enable WL suspend for PCIe*/	\
+	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT0, BIT0}, /*Set SDIO suspend local register*/	\
+	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, 0}, /*wait power state to suspend*/
+
+#define RTL8821A_TRANS_SUS_TO_CARDEMU													\
+	/* format */																\
+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT7, 0}, /*clear suspend enable and power down enable*/	\
+	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT0, 0}, /*Set SDIO suspend local register*/	\
+	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, BIT1}, /*wait power state to suspend*/\
+	{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0}, /*0x23[4] = 1b'0 12H LDO enter normal mode*/   \
+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT4, 0}, /*0x04[12:11] = 2b'01enable WL suspend*/
+
+#define RTL8821A_TRANS_CARDEMU_TO_CARDDIS													\
+	/* format */																\
+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
+	{0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x20}, /*0x07 = 0x20 , SOP option to disable BG/MB*/	\
+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT4, BIT3}, /*0x04[12:11] = 2b'01 enable WL suspend*/	\
+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, BIT2}, /*0x04[10] = 1, enable SW LPS*/	\
+	{0x004A, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 1}, /*0x48[16] = 1 to enable GPIO9 as EXT WAKEUP*/   \
+	{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, BIT4}, /*0x23[4] = 1b'1 12H LDO enter sleep mode*/   \
+	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT0, BIT0}, /*Set SDIO suspend local register*/	\
+	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, 0}, /*wait power state to suspend*/
+
+#define RTL8821A_TRANS_CARDDIS_TO_CARDEMU													\
+	/* format */																\
+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT7, 0}, /*clear suspend enable and power down enable*/	\
+	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT0, 0}, /*Set SDIO suspend local register*/	\
+	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, BIT1}, /*wait power state to suspend*/\
+	{0x004A, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0}, /*0x48[16] = 0 to disable GPIO9 as EXT WAKEUP*/   \
+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT4, 0}, /*0x04[12:11] = 2b'01enable WL suspend*/\
+	{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0}, /*0x23[4] = 1b'0 12H LDO enter normal mode*/   \
+	{0x0301, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0},/*PCIe DMA start*/
+
+
+#define RTL8821A_TRANS_CARDEMU_TO_PDN												\
+	/* format */																\
+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
+	{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, BIT4}, /*0x23[4] = 1b'1 12H LDO enter sleep mode*/   \
+	{0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK | PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x20}, /*0x07[7:0] = 0x20 SOP option to disable BG/MB/ACK/SWR*/   \
+	{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0},/* 0x04[16] = 0*/\
+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, BIT7},/* 0x04[15] = 1*/
+
+#define RTL8821A_TRANS_PDN_TO_CARDEMU												\
+	/* format */																\
+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, 0},/* 0x04[15] = 0*/
+
+#define RTL8821A_TRANS_ACT_TO_LPS														\
+	/* format */																\
+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
+	{0x0301, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF},/*PCIe DMA stop*/	\
+	{0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF},/*Tx Pause*/	\
+	{0x05F8, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/	\
+	{0x05F9, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/	\
+	{0x05FA, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/	\
+	{0x05FB, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/	\
+	{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0},/*CCK and OFDM are disabled, and clock are gated*/	\
+	{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_US},/*Delay 1us*/	\
+	{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0},/*Whole BB is reset*/	\
+	{0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x03},/*Reset MAC TRX*/	\
+	{0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0},/*check if removed later*/	\
+	{0x0093, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x00},/*When driver enter Sus/ Disable, enable LOP for BT*/	\
+	{0x0553, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT5, BIT5},/*Respond TxOK to scheduler*/	\
+
+
+#define RTL8821A_TRANS_LPS_TO_ACT															\
+	/* format */																\
+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
+	{0x0080, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, 0xFF, 0x84}, /*SDIO RPWM*/\
+	{0xFE58, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x84}, /*USB RPWM*/\
+	{0x0361, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x84}, /*PCIe RPWM*/\
+	{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_MS}, /*Delay*/\
+	{0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0}, /*.	0x08[4] = 0		 switch TSF to 40M*/\
+	{0x0109, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT7, 0}, /*Polling 0x109[7]=0  TSF in 40M*/\
+	{0x0029, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT6 | BIT7, 0}, /*.	0x29[7:6] = 2b'00	 enable BB clock*/\
+	{0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1}, /*.	0x101[1] = 1*/\
+	{0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF}, /*.	0x100[7:0] = 0xFF	 enable WMAC TRX*/\
+	{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1 | BIT0, BIT1 | BIT0}, /*.	0x02[1:0] = 2b'11	 enable BB macro*/\
+	{0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0}, /*.	0x522 = 0*/
+
+#define RTL8821A_TRANS_END															\
+	/* format */																\
+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
+	{0xFFFF, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, 0, PWR_CMD_END, 0, 0},
+
+
+	extern WLAN_PWR_CFG rtl8821A_power_on_flow[RTL8821A_TRANS_CARDEMU_TO_ACT_STEPS + RTL8821A_TRANS_END_STEPS];
+	extern WLAN_PWR_CFG rtl8821A_radio_off_flow[RTL8821A_TRANS_ACT_TO_CARDEMU_STEPS + RTL8821A_TRANS_END_STEPS];
+	extern WLAN_PWR_CFG rtl8821A_card_disable_flow[RTL8821A_TRANS_ACT_TO_CARDEMU_STEPS + RTL8821A_TRANS_CARDEMU_TO_PDN_STEPS + RTL8821A_TRANS_END_STEPS];
+	extern WLAN_PWR_CFG rtl8821A_card_enable_flow[RTL8821A_TRANS_CARDDIS_TO_CARDEMU_STEPS + RTL8821A_TRANS_CARDEMU_TO_ACT_STEPS + RTL8821A_TRANS_END_STEPS];
+	extern WLAN_PWR_CFG rtl8821A_suspend_flow[RTL8821A_TRANS_ACT_TO_CARDEMU_STEPS + RTL8821A_TRANS_CARDEMU_TO_SUS_STEPS + RTL8821A_TRANS_END_STEPS];
+	extern WLAN_PWR_CFG rtl8821A_resume_flow[RTL8821A_TRANS_ACT_TO_CARDEMU_STEPS + RTL8821A_TRANS_CARDEMU_TO_SUS_STEPS + RTL8821A_TRANS_END_STEPS];
+	extern WLAN_PWR_CFG rtl8821A_hwpdn_flow[RTL8821A_TRANS_ACT_TO_CARDEMU_STEPS + RTL8821A_TRANS_CARDEMU_TO_PDN_STEPS + RTL8821A_TRANS_END_STEPS];
+	extern WLAN_PWR_CFG rtl8821A_enter_lps_flow[RTL8821A_TRANS_ACT_TO_LPS_STEPS + RTL8821A_TRANS_END_STEPS];
+	extern WLAN_PWR_CFG rtl8821A_leave_lps_flow[RTL8821A_TRANS_LPS_TO_ACT_STEPS + RTL8821A_TRANS_END_STEPS];
+
+#endif
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/include/hal_btcoex.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/hal_btcoex.h
--- linux-5.6.3/3rdparty/rtl8821ce/include/hal_btcoex.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/hal_btcoex.h	2020-04-10 16:35:06.846661469 +0300
@@ -0,0 +1,97 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2013 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#ifndef __HAL_BTCOEX_H__
+#define __HAL_BTCOEX_H__
+
+#include <drv_types.h>
+
+/* Some variables can't get from outsrc BT-Coex,
+ * so we need to save here */
+typedef struct _BT_COEXIST {
+	u8 bBtExist;
+	u8 btTotalAntNum;
+	u8 btChipType;
+	u8 bInitlized;
+	u8 btAntisolation;
+} BT_COEXIST, *PBT_COEXIST;
+
+void DBG_BT_INFO(u8 *dbgmsg);
+
+void hal_btcoex_SetBTCoexist(PADAPTER padapter, u8 bBtExist);
+u8 hal_btcoex_IsBtExist(PADAPTER padapter);
+u8 hal_btcoex_IsBtDisabled(PADAPTER);
+void hal_btcoex_SetChipType(PADAPTER padapter, u8 chipType);
+void hal_btcoex_SetPgAntNum(PADAPTER padapter, u8 antNum);
+
+u8 hal_btcoex_Initialize(PADAPTER padapter);
+void hal_btcoex_PowerOnSetting(PADAPTER padapter);
+void hal_btcoex_AntInfoSetting(PADAPTER padapter);
+void hal_btcoex_PowerOffSetting(PADAPTER padapter);
+void hal_btcoex_PreLoadFirmware(PADAPTER padapter);
+void hal_btcoex_InitHwConfig(PADAPTER padapter, u8 bWifiOnly);
+
+void hal_btcoex_IpsNotify(PADAPTER padapter, u8 type);
+void hal_btcoex_LpsNotify(PADAPTER padapter, u8 type);
+void hal_btcoex_ScanNotify(PADAPTER padapter, u8 type);
+void hal_btcoex_ConnectNotify(PADAPTER padapter, u8 action);
+void hal_btcoex_MediaStatusNotify(PADAPTER padapter, u8 mediaStatus);
+void hal_btcoex_SpecialPacketNotify(PADAPTER padapter, u8 pktType);
+void hal_btcoex_IQKNotify(PADAPTER padapter, u8 state);
+void hal_btcoex_BtInfoNotify(PADAPTER padapter, u8 length, u8 *tmpBuf);
+void hal_btcoex_BtMpRptNotify(PADAPTER padapter, u8 length, u8 *tmpBuf);
+void hal_btcoex_SuspendNotify(PADAPTER padapter, u8 state);
+void hal_btcoex_HaltNotify(PADAPTER padapter, u8 do_halt);
+void hal_btcoex_SwitchBtTRxMask(PADAPTER padapter);
+
+void hal_btcoex_Hanlder(PADAPTER padapter);
+
+s32 hal_btcoex_IsBTCoexRejectAMPDU(PADAPTER padapter);
+s32 hal_btcoex_IsBTCoexCtrlAMPDUSize(PADAPTER padapter);
+u32 hal_btcoex_GetAMPDUSize(PADAPTER padapter);
+void hal_btcoex_SetManualControl(PADAPTER padapter, u8 bmanual);
+u8 hal_btcoex_1Ant(PADAPTER padapter);
+u8 hal_btcoex_IsBtControlLps(PADAPTER);
+u8 hal_btcoex_IsLpsOn(PADAPTER);
+u8 hal_btcoex_RpwmVal(PADAPTER);
+u8 hal_btcoex_LpsVal(PADAPTER);
+u32 hal_btcoex_GetRaMask(PADAPTER);
+void hal_btcoex_RecordPwrMode(PADAPTER padapter, u8 *pCmdBuf, u8 cmdLen);
+void hal_btcoex_DisplayBtCoexInfo(PADAPTER, u8 *pbuf, u32 bufsize);
+void hal_btcoex_SetDBG(PADAPTER, u32 *pDbgModule);
+u32 hal_btcoex_GetDBG(PADAPTER, u8 *pStrBuf, u32 bufSize);
+u8 hal_btcoex_IncreaseScanDeviceNum(PADAPTER);
+u8 hal_btcoex_IsBtLinkExist(PADAPTER);
+void hal_btcoex_SetBtPatchVersion(PADAPTER, u16 btHciVer, u16 btPatchVer);
+void hal_btcoex_SetHciVersion(PADAPTER, u16 hciVersion);
+void hal_btcoex_SendScanNotify(PADAPTER, u8 type);
+void hal_btcoex_StackUpdateProfileInfo(void);
+void hal_btcoex_pta_off_on_notify(PADAPTER padapter, u8 bBTON);
+void hal_btcoex_SetAntIsolationType(PADAPTER padapter, u8 anttype);
+#ifdef CONFIG_LOAD_PHY_PARA_FROM_FILE
+	int hal_btcoex_AntIsolationConfig_ParaFile(IN PADAPTER	Adapter, IN char *pFileName);
+	int hal_btcoex_ParseAntIsolationConfigFile(PADAPTER Adapter, char	*buffer);
+#endif /* CONFIG_LOAD_PHY_PARA_FROM_FILE */
+u16 hal_btcoex_btreg_read(PADAPTER padapter, u8 type, u16 addr, u32 *data);
+u16 hal_btcoex_btreg_write(PADAPTER padapter, u8 type, u16 addr, u16 val);
+void hal_btcoex_set_rfe_type(u8 type);
+void hal_btcoex_switchband_notify(u8 under_scan, u8 band_type);
+void hal_btcoex_WlFwDbgInfoNotify(PADAPTER padapter, u8* tmpBuf, u8 length);
+void hal_btcoex_rx_rate_change_notify(PADAPTER padapter, u8 is_data_frame, u8 rate_id);
+
+#ifdef CONFIG_RF4CE_COEXIST
+void hal_btcoex_set_rf4ce_link_state(u8 state);
+u8 hal_btcoex_get_rf4ce_link_state(void);
+#endif
+#endif /* !__HAL_BTCOEX_H__ */
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/include/hal_btcoex_wifionly.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/hal_btcoex_wifionly.h
--- linux-5.6.3/3rdparty/rtl8821ce/include/hal_btcoex_wifionly.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/hal_btcoex_wifionly.h	2020-04-10 16:35:06.846661469 +0300
@@ -0,0 +1,81 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2016 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#ifndef __HALBTC_WIFIONLY_H__
+#define __HALBTC_WIFIONLY_H__
+
+#include <drv_types.h>
+#include <hal_data.h>
+
+/* Define the ICs that support wifi only cfg in coex. codes */
+#if defined(CONFIG_RTL8723B) || defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C)
+#define CONFIG_BTCOEX_SUPPORT_WIFI_ONLY_CFG 1
+#else
+#define CONFIG_BTCOEX_SUPPORT_WIFI_ONLY_CFG 0
+#endif
+
+#if (CONFIG_BTCOEX_SUPPORT_WIFI_ONLY_CFG == 1)
+
+typedef enum _WIFIONLY_CHIP_INTERFACE {
+	WIFIONLY_INTF_UNKNOWN	= 0,
+	WIFIONLY_INTF_PCI		= 1,
+	WIFIONLY_INTF_USB		= 2,
+	WIFIONLY_INTF_SDIO		= 3,
+	WIFIONLY_INTF_MAX
+} WIFIONLY_CHIP_INTERFACE, *PWIFIONLY_CHIP_INTERFACE;
+
+typedef enum _WIFIONLY_CUSTOMER_ID {
+	CUSTOMER_NORMAL			= 0,
+	CUSTOMER_HP_1			= 1
+} WIFIONLY_CUSTOMER_ID, *PWIFIONLY_CUSTOMER_ID;
+
+struct wifi_only_haldata {
+	u16		customer_id;
+	u8		efuse_pg_antnum;
+	u8		efuse_pg_antpath;
+	u8		rfe_type;
+	u8		ant_div_cfg;
+};
+
+struct wifi_only_cfg {
+	PVOID						Adapter;
+	struct	wifi_only_haldata		haldata_info;
+	WIFIONLY_CHIP_INTERFACE	chip_interface;
+};
+
+void halwifionly_write1byte(PVOID pwifionlyContext, u32 RegAddr, u8 Data);
+void halwifionly_write2byte(PVOID pwifionlyContext, u32 RegAddr, u16 Data);
+void halwifionly_write4byte(PVOID pwifionlyContext, u32 RegAddr, u32 Data);
+u8 halwifionly_read1byte(PVOID pwifionlyContext, u32 RegAddr);
+u16 halwifionly_read2byte(PVOID pwifionlyContext, u32 RegAddr);
+u32 halwifionly_read4byte(PVOID pwifionlyContext, u32 RegAddr);
+void halwifionly_bitmaskwrite1byte(PVOID pwifionlyContext, u32 regAddr, u8 bitMask, u8 data);
+void halwifionly_phy_set_rf_reg(PVOID pwifionlyContext, enum rf_path eRFPath, u32 RegAddr, u32 BitMask, u32 Data);
+void halwifionly_phy_set_bb_reg(PVOID pwifionlyContext, u32 RegAddr, u32 BitMask, u32 Data);
+void hal_btcoex_wifionly_switchband_notify(PADAPTER padapter);
+void hal_btcoex_wifionly_scan_notify(PADAPTER padapter);
+void hal_btcoex_wifionly_connect_notify(PADAPTER padapter);
+void hal_btcoex_wifionly_hw_config(PADAPTER padapter);
+void hal_btcoex_wifionly_initlizevariables(PADAPTER padapter);
+void hal_btcoex_wifionly_AntInfoSetting(PADAPTER padapter);
+#else
+#define hal_btcoex_wifionly_switchband_notify(padapter)
+#define hal_btcoex_wifionly_scan_notify(padapter)
+#define hal_btcoex_wifionly_connect_notify(padapter)
+#define hal_btcoex_wifionly_hw_config(padapter)
+#define hal_btcoex_wifionly_initlizevariables(padapter)
+#define hal_btcoex_wifionly_AntInfoSetting(padapter)
+#endif
+
+#endif
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/include/hal_com.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/hal_com.h
--- linux-5.6.3/3rdparty/rtl8821ce/include/hal_com.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/hal_com.h	2020-04-10 16:35:06.846661469 +0300
@@ -0,0 +1,704 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#ifndef __HAL_COMMON_H__
+#define __HAL_COMMON_H__
+
+#include "HalVerDef.h"
+#include "hal_pg.h"
+#include "hal_phy.h"
+#include "hal_phy_reg.h"
+#include "hal_com_reg.h"
+#include "hal_com_phycfg.h"
+#include "../hal/hal_com_c2h.h"
+
+/*------------------------------ Tx Desc definition Macro ------------------------*/
+/* #pragma mark -- Tx Desc related definition. -- */
+/* ----------------------------------------------------------------------------
+ * -----------------------------------------------------------
+ *	Rate
+ * -----------------------------------------------------------
+ * CCK Rates, TxHT = 0 */
+#define DESC_RATE1M					0x00
+#define DESC_RATE2M					0x01
+#define DESC_RATE5_5M				0x02
+#define DESC_RATE11M				0x03
+
+/* OFDM Rates, TxHT = 0 */
+#define DESC_RATE6M					0x04
+#define DESC_RATE9M					0x05
+#define DESC_RATE12M				0x06
+#define DESC_RATE18M				0x07
+#define DESC_RATE24M				0x08
+#define DESC_RATE36M				0x09
+#define DESC_RATE48M				0x0a
+#define DESC_RATE54M				0x0b
+
+/* MCS Rates, TxHT = 1 */
+#define DESC_RATEMCS0				0x0c
+#define DESC_RATEMCS1				0x0d
+#define DESC_RATEMCS2				0x0e
+#define DESC_RATEMCS3				0x0f
+#define DESC_RATEMCS4				0x10
+#define DESC_RATEMCS5				0x11
+#define DESC_RATEMCS6				0x12
+#define DESC_RATEMCS7				0x13
+#define DESC_RATEMCS8				0x14
+#define DESC_RATEMCS9				0x15
+#define DESC_RATEMCS10				0x16
+#define DESC_RATEMCS11				0x17
+#define DESC_RATEMCS12				0x18
+#define DESC_RATEMCS13				0x19
+#define DESC_RATEMCS14				0x1a
+#define DESC_RATEMCS15				0x1b
+#define DESC_RATEMCS16				0x1C
+#define DESC_RATEMCS17				0x1D
+#define DESC_RATEMCS18				0x1E
+#define DESC_RATEMCS19				0x1F
+#define DESC_RATEMCS20				0x20
+#define DESC_RATEMCS21				0x21
+#define DESC_RATEMCS22				0x22
+#define DESC_RATEMCS23				0x23
+#define DESC_RATEMCS24				0x24
+#define DESC_RATEMCS25				0x25
+#define DESC_RATEMCS26				0x26
+#define DESC_RATEMCS27				0x27
+#define DESC_RATEMCS28				0x28
+#define DESC_RATEMCS29				0x29
+#define DESC_RATEMCS30				0x2A
+#define DESC_RATEMCS31				0x2B
+#define DESC_RATEVHTSS1MCS0		0x2C
+#define DESC_RATEVHTSS1MCS1		0x2D
+#define DESC_RATEVHTSS1MCS2		0x2E
+#define DESC_RATEVHTSS1MCS3		0x2F
+#define DESC_RATEVHTSS1MCS4		0x30
+#define DESC_RATEVHTSS1MCS5		0x31
+#define DESC_RATEVHTSS1MCS6		0x32
+#define DESC_RATEVHTSS1MCS7		0x33
+#define DESC_RATEVHTSS1MCS8		0x34
+#define DESC_RATEVHTSS1MCS9		0x35
+#define DESC_RATEVHTSS2MCS0		0x36
+#define DESC_RATEVHTSS2MCS1		0x37
+#define DESC_RATEVHTSS2MCS2		0x38
+#define DESC_RATEVHTSS2MCS3		0x39
+#define DESC_RATEVHTSS2MCS4		0x3A
+#define DESC_RATEVHTSS2MCS5		0x3B
+#define DESC_RATEVHTSS2MCS6		0x3C
+#define DESC_RATEVHTSS2MCS7		0x3D
+#define DESC_RATEVHTSS2MCS8		0x3E
+#define DESC_RATEVHTSS2MCS9		0x3F
+#define DESC_RATEVHTSS3MCS0		0x40
+#define DESC_RATEVHTSS3MCS1		0x41
+#define DESC_RATEVHTSS3MCS2		0x42
+#define DESC_RATEVHTSS3MCS3		0x43
+#define DESC_RATEVHTSS3MCS4		0x44
+#define DESC_RATEVHTSS3MCS5		0x45
+#define DESC_RATEVHTSS3MCS6		0x46
+#define DESC_RATEVHTSS3MCS7		0x47
+#define DESC_RATEVHTSS3MCS8		0x48
+#define DESC_RATEVHTSS3MCS9		0x49
+#define DESC_RATEVHTSS4MCS0		0x4A
+#define DESC_RATEVHTSS4MCS1		0x4B
+#define DESC_RATEVHTSS4MCS2		0x4C
+#define DESC_RATEVHTSS4MCS3		0x4D
+#define DESC_RATEVHTSS4MCS4		0x4E
+#define DESC_RATEVHTSS4MCS5		0x4F
+#define DESC_RATEVHTSS4MCS6		0x50
+#define DESC_RATEVHTSS4MCS7		0x51
+#define DESC_RATEVHTSS4MCS8		0x52
+#define DESC_RATEVHTSS4MCS9		0x53
+
+#define HDATA_RATE(rate)\
+	(rate == DESC_RATE1M) ? "CCK_1M" :\
+	(rate == DESC_RATE2M) ? "CCK_2M" :\
+	(rate == DESC_RATE5_5M) ? "CCK5_5M" :\
+	(rate == DESC_RATE11M) ? "CCK_11M" :\
+	(rate == DESC_RATE6M) ? "OFDM_6M" :\
+	(rate == DESC_RATE9M) ? "OFDM_9M" :\
+	(rate == DESC_RATE12M) ? "OFDM_12M" :\
+	(rate == DESC_RATE18M) ? "OFDM_18M" :\
+	(rate == DESC_RATE24M) ? "OFDM_24M" :\
+	(rate == DESC_RATE36M) ? "OFDM_36M" :\
+	(rate == DESC_RATE48M) ? "OFDM_48M" :\
+	(rate == DESC_RATE54M) ? "OFDM_54M" :\
+	(rate == DESC_RATEMCS0) ? "MCS0" :\
+	(rate == DESC_RATEMCS1) ? "MCS1" :\
+	(rate == DESC_RATEMCS2) ? "MCS2" :\
+	(rate == DESC_RATEMCS3) ? "MCS3" :\
+	(rate == DESC_RATEMCS4) ? "MCS4" :\
+	(rate == DESC_RATEMCS5) ? "MCS5" :\
+	(rate == DESC_RATEMCS6) ? "MCS6" :\
+	(rate == DESC_RATEMCS7) ? "MCS7" :\
+	(rate == DESC_RATEMCS8) ? "MCS8" :\
+	(rate == DESC_RATEMCS9) ? "MCS9" :\
+	(rate == DESC_RATEMCS10) ? "MCS10" :\
+	(rate == DESC_RATEMCS11) ? "MCS11" :\
+	(rate == DESC_RATEMCS12) ? "MCS12" :\
+	(rate == DESC_RATEMCS13) ? "MCS13" :\
+	(rate == DESC_RATEMCS14) ? "MCS14" :\
+	(rate == DESC_RATEMCS15) ? "MCS15" :\
+	(rate == DESC_RATEMCS16) ? "MCS16" :\
+	(rate == DESC_RATEMCS17) ? "MCS17" :\
+	(rate == DESC_RATEMCS18) ? "MCS18" :\
+	(rate == DESC_RATEMCS19) ? "MCS19" :\
+	(rate == DESC_RATEMCS20) ? "MCS20" :\
+	(rate == DESC_RATEMCS21) ? "MCS21" :\
+	(rate == DESC_RATEMCS22) ? "MCS22" :\
+	(rate == DESC_RATEMCS23) ? "MCS23" :\
+	(rate == DESC_RATEVHTSS1MCS0) ? "VHTSS1MCS0" :\
+	(rate == DESC_RATEVHTSS1MCS1) ? "VHTSS1MCS1" :\
+	(rate == DESC_RATEVHTSS1MCS2) ? "VHTSS1MCS2" :\
+	(rate == DESC_RATEVHTSS1MCS3) ? "VHTSS1MCS3" :\
+	(rate == DESC_RATEVHTSS1MCS4) ? "VHTSS1MCS4" :\
+	(rate == DESC_RATEVHTSS1MCS5) ? "VHTSS1MCS5" :\
+	(rate == DESC_RATEVHTSS1MCS6) ? "VHTSS1MCS6" :\
+	(rate == DESC_RATEVHTSS1MCS7) ? "VHTSS1MCS7" :\
+	(rate == DESC_RATEVHTSS1MCS8) ? "VHTSS1MCS8" :\
+	(rate == DESC_RATEVHTSS1MCS9) ? "VHTSS1MCS9" :\
+	(rate == DESC_RATEVHTSS2MCS0) ? "VHTSS2MCS0" :\
+	(rate == DESC_RATEVHTSS2MCS1) ? "VHTSS2MCS1" :\
+	(rate == DESC_RATEVHTSS2MCS2) ? "VHTSS2MCS2" :\
+	(rate == DESC_RATEVHTSS2MCS3) ? "VHTSS2MCS3" :\
+	(rate == DESC_RATEVHTSS2MCS4) ? "VHTSS2MCS4" :\
+	(rate == DESC_RATEVHTSS2MCS5) ? "VHTSS2MCS5" :\
+	(rate == DESC_RATEVHTSS2MCS6) ? "VHTSS2MCS6" :\
+	(rate == DESC_RATEVHTSS2MCS7) ? "VHTSS2MCS7" :\
+	(rate == DESC_RATEVHTSS2MCS8) ? "VHTSS2MCS8" :\
+	(rate == DESC_RATEVHTSS2MCS9) ? "VHTSS2MCS9" :\
+	(rate == DESC_RATEVHTSS3MCS0) ? "VHTSS3MCS0" :\
+	(rate == DESC_RATEVHTSS3MCS1) ? "VHTSS3MCS1" :\
+	(rate == DESC_RATEVHTSS3MCS2) ? "VHTSS3MCS2" :\
+	(rate == DESC_RATEVHTSS3MCS3) ? "VHTSS3MCS3" :\
+	(rate == DESC_RATEVHTSS3MCS4) ? "VHTSS3MCS4" :\
+	(rate == DESC_RATEVHTSS3MCS5) ? "VHTSS3MCS5" :\
+	(rate == DESC_RATEVHTSS3MCS6) ? "VHTSS3MCS6" :\
+	(rate == DESC_RATEVHTSS3MCS7) ? "VHTSS3MCS7" :\
+	(rate == DESC_RATEVHTSS3MCS8) ? "VHTSS3MCS8" :\
+	(rate == DESC_RATEVHTSS3MCS9) ? "VHTSS3MCS9" : "UNKNOWN"
+
+enum {
+	UP_LINK,
+	DOWN_LINK,
+};
+typedef enum _RT_MEDIA_STATUS {
+	RT_MEDIA_DISCONNECT = 0,
+	RT_MEDIA_CONNECT       = 1
+} RT_MEDIA_STATUS;
+
+#define MAX_DLFW_PAGE_SIZE			4096	/* @ page : 4k bytes */
+typedef enum _FIRMWARE_SOURCE {
+	FW_SOURCE_IMG_FILE = 0,
+	FW_SOURCE_HEADER_FILE = 1,		/* from header file */
+} FIRMWARE_SOURCE, *PFIRMWARE_SOURCE;
+
+typedef enum _CH_SW_USE_CASE {
+	CH_SW_USE_CASE_TDLS		= 0,
+	CH_SW_USE_CASE_MCC		= 1
+} CH_SW_USE_CASE;
+
+typedef enum _WAKEUP_REASON{
+	RX_PAIRWISEKEY					= 0x01,
+	RX_GTK							= 0x02,
+	RX_FOURWAY_HANDSHAKE			= 0x03,
+	RX_DISASSOC						= 0x04,
+	RX_DEAUTH						= 0x08,
+	RX_ARP_REQUEST					= 0x09,
+	FW_DECISION_DISCONNECT			= 0x10,
+	RX_MAGIC_PKT					= 0x21,
+	RX_UNICAST_PKT					= 0x22,
+	RX_PATTERN_PKT					= 0x23,
+	RTD3_SSID_MATCH					= 0x24,
+	RX_REALWOW_V2_WAKEUP_PKT		= 0x30,
+	RX_REALWOW_V2_ACK_LOST			= 0x31,
+	ENABLE_FAIL_DMA_IDLE			= 0x40,
+	ENABLE_FAIL_DMA_PAUSE			= 0x41,
+	RTIME_FAIL_DMA_IDLE				= 0x42,
+	RTIME_FAIL_DMA_PAUSE			= 0x43,
+	RX_PNO							= 0x55,
+	AP_OFFLOAD_WAKEUP				= 0x66,
+	CLK_32K_UNLOCK					= 0xFD,
+	CLK_32K_LOCK					= 0xFE
+}WAKEUP_REASON;
+
+/*
+ * Queue Select Value in TxDesc
+ *   */
+#define QSLT_BK							0x2/* 0x01 */
+#define QSLT_BE							0x0
+#define QSLT_VI							0x5/* 0x4 */
+#define QSLT_VO							0x7/* 0x6 */
+#define QSLT_BEACON						0x10
+#define QSLT_HIGH						0x11
+#define QSLT_MGNT						0x12
+#define QSLT_CMD						0x13
+
+/* BK, BE, VI, VO, HCCA, MANAGEMENT, COMMAND, HIGH, BEACON.
+ * #define MAX_TX_QUEUE		9 */
+
+#define TX_SELE_HQ			BIT(0)		/* High Queue */
+#define TX_SELE_LQ			BIT(1)		/* Low Queue */
+#define TX_SELE_NQ			BIT(2)		/* Normal Queue */
+#define TX_SELE_EQ			BIT(3)		/* Extern Queue */
+
+#define PageNum_128(_Len)		(u32)(((_Len)>>7) + ((_Len) & 0x7F ? 1 : 0))
+#define PageNum_256(_Len)		(u32)(((_Len)>>8) + ((_Len) & 0xFF ? 1 : 0))
+#define PageNum_512(_Len)		(u32)(((_Len)>>9) + ((_Len) & 0x1FF ? 1 : 0))
+#define PageNum(_Len, _Size)		(u32)(((_Len)/(_Size)) + ((_Len)&((_Size) - 1) ? 1 : 0))
+
+struct dbg_rx_counter {
+	u32	rx_pkt_ok;
+	u32	rx_pkt_crc_error;
+	u32	rx_pkt_drop;
+	u32	rx_ofdm_fa;
+	u32	rx_cck_fa;
+	u32	rx_ht_fa;
+};
+
+u8 rtw_hal_get_port(_adapter *adapter);
+
+#ifdef CONFIG_MBSSID_CAM
+	#define DBG_MBID_CAM_DUMP
+
+	void rtw_mbid_cam_init(struct dvobj_priv *dvobj);
+	void rtw_mbid_cam_deinit(struct dvobj_priv *dvobj);
+	void rtw_mbid_cam_reset(_adapter *adapter);
+	u8 rtw_get_max_mbid_cam_id(_adapter *adapter);
+	u8 rtw_get_mbid_cam_entry_num(_adapter *adapter);
+	int rtw_mbid_cam_cache_dump(void *sel, const char *fun_name , _adapter *adapter);
+	int rtw_mbid_cam_dump(void *sel, const char *fun_name, _adapter *adapter);
+	void rtw_mi_set_mbid_cam(_adapter *adapter);
+	u8 rtw_mbid_camid_alloc(_adapter *adapter, u8 *mac_addr);
+	void rtw_ap_set_mbid_num(_adapter *adapter, u8 ap_num);
+	void rtw_mbid_cam_enable(_adapter *adapter);
+#endif
+
+#ifdef CONFIG_MI_WITH_MBSSID_CAM
+	void rtw_hal_set_macaddr_mbid(_adapter *adapter, u8 *mac_addr);
+	void rtw_hal_change_macaddr_mbid(_adapter *adapter, u8 *mac_addr);
+	#ifdef CONFIG_SWTIMER_BASED_TXBCN
+	u16 rtw_hal_bcn_interval_adjust(_adapter *adapter, u16 bcn_interval);
+	#endif
+	void hw_var_set_opmode_mbid(_adapter *Adapter, u8 mode);
+#endif
+
+void rtw_dump_mac_rx_counters(_adapter *padapter, struct dbg_rx_counter *rx_counter);
+void rtw_dump_phy_rx_counters(_adapter *padapter, struct dbg_rx_counter *rx_counter);
+void rtw_reset_mac_rx_counters(_adapter *padapter);
+void rtw_reset_phy_rx_counters(_adapter *padapter);
+void rtw_reset_phy_trx_ok_counters(_adapter *padapter);
+
+#ifdef DBG_RX_COUNTER_DUMP
+	#define DUMP_DRV_RX_COUNTER	BIT0
+	#define DUMP_MAC_RX_COUNTER	BIT1
+	#define DUMP_PHY_RX_COUNTER	BIT2
+	#define DUMP_DRV_TRX_COUNTER_DATA	BIT3
+
+	void rtw_dump_phy_rxcnts_preprocess(_adapter *padapter, u8 rx_cnt_mode);
+	void rtw_dump_rx_counters(_adapter *padapter);
+#endif
+
+void dump_chip_info(HAL_VERSION	ChipVersion);
+void rtw_hal_config_rftype(PADAPTER  padapter);
+
+#define BAND_CAP_2G			BIT0
+#define BAND_CAP_5G			BIT1
+#define BAND_CAP_BIT_NUM	2
+
+#define BW_CAP_5M		BIT0
+#define BW_CAP_10M		BIT1
+#define BW_CAP_20M		BIT2
+#define BW_CAP_40M		BIT3
+#define BW_CAP_80M		BIT4
+#define BW_CAP_160M		BIT5
+#define BW_CAP_80_80M	BIT6
+#define BW_CAP_BIT_NUM	7
+
+#define PROTO_CAP_11B		BIT0
+#define PROTO_CAP_11G		BIT1
+#define PROTO_CAP_11N		BIT2
+#define PROTO_CAP_11AC		BIT3
+#define PROTO_CAP_BIT_NUM	4
+
+#define WL_FUNC_P2P			BIT0
+#define WL_FUNC_MIRACAST	BIT1
+#define WL_FUNC_TDLS		BIT2
+#define WL_FUNC_FTM			BIT3
+#define WL_FUNC_BIT_NUM		4
+
+#define TBTT_PROHIBIT_SETUP_TIME 0x04 /* 128us, unit is 32us */
+#define TBTT_PROHIBIT_HOLD_TIME 0x80 /* 4ms, unit is 32us*/
+#define TBTT_PROHIBIT_HOLD_TIME_STOP_BCN 0x64 /* 3.2ms unit is 32us*/
+
+int hal_spec_init(_adapter *adapter);
+void dump_hal_spec(void *sel, _adapter *adapter);
+
+bool hal_chk_band_cap(_adapter *adapter, u8 cap);
+bool hal_chk_bw_cap(_adapter *adapter, u8 cap);
+bool hal_chk_proto_cap(_adapter *adapter, u8 cap);
+bool hal_is_band_support(_adapter *adapter, u8 band);
+bool hal_is_bw_support(_adapter *adapter, u8 bw);
+bool hal_is_wireless_mode_support(_adapter *adapter, u8 mode);
+u8 hal_largest_bw(_adapter *adapter, u8 in_bw);
+
+bool hal_chk_wl_func(_adapter *adapter, u8 func);
+
+void hal_com_config_channel_plan(
+	IN	PADAPTER padapter,
+	IN	char *hw_alpha2,
+	IN	u8 hw_chplan,
+	IN	char *sw_alpha2,
+	IN	u8 sw_chplan,
+	IN	u8 def_chplan,
+	IN	BOOLEAN AutoLoadFail
+);
+
+int hal_config_macaddr(_adapter *adapter, bool autoload_fail);
+#ifdef RTW_HALMAC
+void rtw_hal_hw_port_enable(_adapter *adapter);
+void rtw_hal_hw_port_disable(_adapter *adapter);
+#endif
+
+BOOLEAN
+HAL_IsLegalChannel(
+	IN	PADAPTER	Adapter,
+	IN	u32			Channel
+);
+
+u8	MRateToHwRate(u8 rate);
+
+u8	hw_rate_to_m_rate(u8 rate);
+
+void	HalSetBrateCfg(
+	IN PADAPTER		Adapter,
+	IN u8			*mBratesOS,
+	OUT u16			*pBrateCfg);
+
+BOOLEAN
+Hal_MappingOutPipe(
+	IN	PADAPTER	pAdapter,
+	IN	u8		NumOutPipe
+);
+
+void rtw_dump_fw_info(void *sel, _adapter *adapter);
+void rtw_restore_hw_port_cfg(_adapter *adapter);
+void rtw_mi_set_mac_addr(_adapter *adapter);/*set mac addr when hal_init for all iface*/
+void rtw_hal_dump_macaddr(void *sel, _adapter *adapter);
+
+void rtw_init_hal_com_default_value(PADAPTER Adapter);
+
+#ifdef CONFIG_FW_C2H_REG
+void c2h_evt_clear(_adapter *adapter);
+s32 c2h_evt_read_88xx(_adapter *adapter, u8 *buf);
+#endif
+
+#ifdef CONFIG_FW_C2H_PKT
+void rtw_hal_c2h_pkt_pre_hdl(_adapter *adapter, u8 *buf, u16 len);
+void rtw_hal_c2h_pkt_hdl(_adapter *adapter, u8 *buf, u16 len);
+#endif
+
+u8 rtw_get_mgntframe_raid(_adapter *adapter, unsigned char network_type);
+
+void rtw_hal_update_sta_wset(_adapter *adapter, struct sta_info *psta);
+s8 rtw_get_sta_rx_nss(_adapter *adapter, struct sta_info *psta);
+s8 rtw_get_sta_tx_nss(_adapter *adapter, struct sta_info *psta);
+void rtw_hal_update_sta_ra_info(PADAPTER padapter, struct sta_info *psta);
+
+/* access HW only */
+u32 rtw_sec_read_cam(_adapter *adapter, u8 addr);
+void rtw_sec_write_cam(_adapter *adapter, u8 addr, u32 wdata);
+void rtw_sec_read_cam_ent(_adapter *adapter, u8 id, u8 *ctrl, u8 *mac, u8 *key);
+void rtw_sec_write_cam_ent(_adapter *adapter, u8 id, u16 ctrl, u8 *mac, u8 *key);
+void rtw_sec_clr_cam_ent(_adapter *adapter, u8 id);
+bool rtw_sec_read_cam_is_gk(_adapter *adapter, u8 id);
+
+u8 rtw_hal_rcr_check(_adapter *adapter, u32 check_bit);
+
+u8 rtw_hal_rcr_add(_adapter *adapter, u32 add);
+u8 rtw_hal_rcr_clear(_adapter *adapter, u32 clear);
+void rtw_hal_rcr_set_chk_bssid(_adapter *adapter, u8 self_action);
+
+void rtw_iface_enable_tsf_update(_adapter *adapter);
+void rtw_iface_disable_tsf_update(_adapter *adapter);
+void rtw_hal_periodic_tsf_update_chk(_adapter *adapter);
+void rtw_hal_periodic_tsf_update_end_timer_hdl(void *ctx);
+
+void hw_var_port_switch(_adapter *adapter);
+
+u8 SetHwReg(PADAPTER padapter, u8 variable, u8 *val);
+void GetHwReg(PADAPTER padapter, u8 variable, u8 *val);
+void rtw_hal_check_rxfifo_full(_adapter *adapter);
+void rtw_hal_reqtxrpt(_adapter *padapter, u8 macid);
+
+u8 SetHalDefVar(_adapter *adapter, HAL_DEF_VARIABLE variable, void *value);
+u8 GetHalDefVar(_adapter *adapter, HAL_DEF_VARIABLE variable, void *value);
+
+BOOLEAN
+eqNByte(
+	u8	*str1,
+	u8	*str2,
+	u32	num
+);
+
+u32
+MapCharToHexDigit(
+	IN	char	chTmp
+);
+
+BOOLEAN
+GetHexValueFromString(
+	IN		char			*szStr,
+	IN OUT	u32			*pu4bVal,
+	IN OUT	u32			*pu4bMove
+);
+
+BOOLEAN
+GetFractionValueFromString(
+	IN		char		*szStr,
+	IN OUT	u8			*pInteger,
+	IN OUT	u8			*pFraction,
+	IN OUT	u32		*pu4bMove
+);
+
+BOOLEAN
+IsCommentString(
+	IN		char		*szStr
+);
+
+BOOLEAN
+ParseQualifiedString(
+	IN	char *In,
+	IN OUT  u32 *Start,
+	OUT	char *Out,
+	IN	char  LeftQualifier,
+	IN	char  RightQualifier
+);
+
+BOOLEAN
+GetU1ByteIntegerFromStringInDecimal(
+	IN		char *Str,
+	IN OUT	u8 *pInt
+);
+
+BOOLEAN
+isAllSpaceOrTab(
+	u8	*data,
+	u8	size
+);
+
+void linked_info_dump(_adapter *padapter, u8 benable);
+#ifdef DBG_RX_SIGNAL_DISPLAY_RAW_DATA
+	void rtw_get_raw_rssi_info(void *sel, _adapter *padapter);
+	void rtw_dump_raw_rssi_info(_adapter *padapter, void *sel);
+#endif
+
+#ifdef DBG_RX_DFRAME_RAW_DATA
+	void rtw_dump_rx_dframe_info(_adapter *padapter, void *sel);
+#endif
+void rtw_store_phy_info(_adapter *padapter, union recv_frame *prframe);
+#define		HWSET_MAX_SIZE			1024
+
+#ifdef CONFIG_EFUSE_CONFIG_FILE
+u32 Hal_readPGDataFromConfigFile(PADAPTER padapter);
+u32 Hal_ReadMACAddrFromFile(PADAPTER padapter, u8 *mac_addr);
+#endif /* CONFIG_EFUSE_CONFIG_FILE */
+
+int hal_efuse_macaddr_offset(_adapter *adapter);
+int Hal_GetPhyEfuseMACAddr(PADAPTER padapter, u8 *mac_addr);
+void rtw_dump_cur_efuse(PADAPTER padapter);
+
+#ifdef CONFIG_RF_POWER_TRIM
+	void rtw_bb_rf_gain_offset(_adapter *padapter);
+#endif /*CONFIG_RF_POWER_TRIM*/
+
+void dm_DynamicUsbTxAgg(_adapter *padapter, u8 from_timer);
+u8 rtw_hal_busagg_qsel_check(_adapter *padapter, u8 pre_qsel, u8 next_qsel);
+
+u8 rtw_get_current_tx_rate(_adapter *padapter, struct sta_info *psta);
+u8 rtw_get_current_tx_sgi(_adapter *padapter, struct sta_info *psta);
+
+void rtw_hal_set_fw_rsvd_page(_adapter *adapter, bool finished);
+u8 rtw_hal_get_rsvd_page_num(struct _ADAPTER *adapter);
+
+#ifdef CONFIG_TSF_RESET_OFFLOAD
+int rtw_hal_reset_tsf(_adapter *adapter, u8 reset_port);
+#endif
+u64 rtw_hal_get_tsftr_by_port(_adapter *adapter, u8 port);
+
+#ifdef CONFIG_TDLS
+	#ifdef CONFIG_TDLS_CH_SW
+		s32 rtw_hal_ch_sw_oper_offload(_adapter *padapter, u8 channel, u8 channel_offset, u16 bwmode);
+	#endif
+#endif
+#if defined(CONFIG_BT_COEXIST) && defined(CONFIG_FW_MULTI_PORT_SUPPORT)
+s32 rtw_hal_set_wifi_btc_port_id_cmd(_adapter *adapter);
+#endif
+
+#ifdef CONFIG_GPIO_API
+	u8 rtw_hal_get_gpio(_adapter *adapter, u8 gpio_num);
+	int rtw_hal_set_gpio_output_value(_adapter *adapter, u8 gpio_num, bool isHigh);
+	int rtw_hal_config_gpio(_adapter *adapter, u8 gpio_num, bool isOutput);
+	int rtw_hal_register_gpio_interrupt(_adapter *adapter, int gpio_num, void(*callback)(u8 level));
+	int rtw_hal_disable_gpio_interrupt(_adapter *adapter, int gpio_num);
+#endif
+
+s8 rtw_hal_ch_sw_iqk_info_search(_adapter *padapter, u8 central_chnl, u8 bw_mode);
+void rtw_hal_ch_sw_iqk_info_backup(_adapter *adapter);
+void rtw_hal_ch_sw_iqk_info_restore(_adapter *padapter, u8 ch_sw_use_case);
+
+#ifdef CONFIG_GPIO_WAKEUP
+	void rtw_hal_switch_gpio_wl_ctrl(_adapter *padapter, u8 index, u8 enable);
+	void rtw_hal_set_output_gpio(_adapter *padapter, u8 index, u8 outputval);
+	void rtw_hal_set_input_gpio(_adapter *padapter, u8 index);
+#endif
+
+#ifdef CONFIG_LOAD_PHY_PARA_FROM_FILE
+	extern char *rtw_phy_file_path;
+	extern char rtw_phy_para_file_path[PATH_LENGTH_MAX];
+	#define GetLineFromBuffer(buffer)   strsep(&buffer, "\r\n")
+#endif
+
+void update_IOT_info(_adapter *padapter);
+
+void hal_set_crystal_cap(_adapter *adapter, u8 crystal_cap);
+
+void ResumeTxBeacon(_adapter *padapter);
+void StopTxBeacon(_adapter *padapter);
+
+#ifdef CONFIG_ANTENNA_DIVERSITY
+	u8	rtw_hal_antdiv_before_linked(_adapter *padapter);
+	void	rtw_hal_antdiv_rssi_compared(_adapter *padapter, WLAN_BSSID_EX *dst, WLAN_BSSID_EX *src);
+#endif
+
+#ifdef DBG_SEC_CAM_MOVE
+	void rtw_hal_move_sta_gk_to_dk(_adapter *adapter);
+	void rtw_hal_read_sta_dk_key(_adapter *adapter, u8 key_id);
+#endif
+
+#ifdef CONFIG_LPS_PG
+#define LPSPG_RSVD_PAGE_SET_MACID(_rsvd_pag, _value)		SET_BITS_TO_LE_4BYTE(_rsvd_pag+0x00, 0, 8, _value)/*used macid*/
+#define LPSPG_RSVD_PAGE_SET_MBSSCAMID(_rsvd_pag, _value)	SET_BITS_TO_LE_4BYTE(_rsvd_pag+0x00, 8, 8, _value)/*used BSSID CAM entry*/
+#define LPSPG_RSVD_PAGE_SET_PMC_NUM(_rsvd_pag, _value)		SET_BITS_TO_LE_4BYTE(_rsvd_pag+0x00, 16, 8, _value)/*Max used Pattern Match CAM entry*/
+#define LPSPG_RSVD_PAGE_SET_MU_RAID_GID(_rsvd_pag, _value)	SET_BITS_TO_LE_4BYTE(_rsvd_pag+0x00, 24, 8, _value)/*Max MU rate table Group ID*/
+#define LPSPG_RSVD_PAGE_SET_SEC_CAM_NUM(_rsvd_pag, _value)	SET_BITS_TO_LE_4BYTE(_rsvd_pag+0x04, 0, 8, _value)/*used Security CAM entry number*/
+#define LPSPG_RSVD_PAGE_SET_DRV_RSVDPAGE_NUM(_rsvd_pag, _value)	SET_BITS_TO_LE_4BYTE(_rsvd_pag+0x04, 8, 8, _value)/*Txbuf used page number for fw offload*/
+#define LPSPG_RSVD_PAGE_SET_SEC_CAM_ID1(_rsvd_pag, _value)	SET_BITS_TO_LE_4BYTE(_rsvd_pag+0x08, 0, 8, _value)/*used Security CAM entry -1*/
+#define LPSPG_RSVD_PAGE_SET_SEC_CAM_ID2(_rsvd_pag, _value)	SET_BITS_TO_LE_4BYTE(_rsvd_pag+0x08, 8, 8, _value)/*used Security CAM entry -2*/
+#define LPSPG_RSVD_PAGE_SET_SEC_CAM_ID3(_rsvd_pag, _value)	SET_BITS_TO_LE_4BYTE(_rsvd_pag+0x08, 16, 8, _value)/*used Security CAM entry -3*/
+#define LPSPG_RSVD_PAGE_SET_SEC_CAM_ID4(_rsvd_pag, _value)	SET_BITS_TO_LE_4BYTE(_rsvd_pag+0x08, 24, 8, _value)/*used Security CAM entry -4*/
+#define LPSPG_RSVD_PAGE_SET_SEC_CAM_ID5(_rsvd_pag, _value)	SET_BITS_TO_LE_4BYTE(_rsvd_pag+0x0C, 0, 8, _value)/*used Security CAM entry -5*/
+#define LPSPG_RSVD_PAGE_SET_SEC_CAM_ID6(_rsvd_pag, _value)	SET_BITS_TO_LE_4BYTE(_rsvd_pag+0x0C, 8, 8, _value)/*used Security CAM entry -6*/
+#define LPSPG_RSVD_PAGE_SET_SEC_CAM_ID7(_rsvd_pag, _value)	SET_BITS_TO_LE_4BYTE(_rsvd_pag+0x0C, 16, 8, _value)/*used Security CAM entry -7*/
+#define LPSPG_RSVD_PAGE_SET_SEC_CAM_ID8(_rsvd_pag, _value)	SET_BITS_TO_LE_4BYTE(_rsvd_pag+0x0C, 24, 8, _value)/*used Security CAM entry -8*/
+enum lps_pg_hdl_id {
+	LPS_PG_INFO_CFG = 0,
+	LPS_PG_REDLEMEM,
+	LPS_PG_PHYDM_DIS,
+	LPS_PG_PHYDM_EN,
+};
+
+	u8 rtw_hal_set_lps_pg_info(_adapter *adapter);
+#endif
+
+int rtw_hal_get_rsvd_page(_adapter *adapter, u32 page_offset, u32 page_num, u8 *buffer, u32 buffer_size);
+void rtw_hal_construct_beacon(_adapter *padapter, u8 *pframe, u32 *pLength);
+void rtw_hal_construct_NullFunctionData(PADAPTER, u8 *pframe, u32 *pLength,
+				u8 bQoS, u8 AC, u8 bEosp, u8 bForcePowerSave);
+
+#ifdef CONFIG_WOWLAN
+struct rtl_wow_pattern {
+	u16	crc;
+	u8	type;
+	u32	mask[4];
+};
+void rtw_wow_pattern_cam_dump(_adapter *adapter);
+
+#ifdef CONFIG_WOW_PATTERN_HW_CAM
+void rtw_wow_pattern_read_cam_ent(_adapter *adapter, u8 id, struct  rtl_wow_pattern *context);
+void rtw_dump_wow_pattern(void *sel, struct rtl_wow_pattern *pwow_pattern, u8 idx);
+#endif
+
+struct rtw_ndp_info {
+	u8 enable:1;
+	u8 check_remote_ip:1; /* Need to Check Sender IP or not */
+	u8 rsvd:6;
+	u8 num_of_target_ip; /* Number of Check IP which NA query IP */
+	u8 target_link_addr[6]; /* DUT's MAC address */
+	u8 remote_ipv6_addr[16]; /* Just respond IP */
+	u8 target_ipv6_addr[16]; /* target IP */
+};
+#define REMOTE_INFO_CTRL_SET_VALD_EN(target, _value) \
+	SET_BITS_TO_LE_4BYTE(target + 0, 0, 8, _value)
+#define REMOTE_INFO_CTRL_SET_PTK_EN(target, _value) \
+	SET_BITS_TO_LE_4BYTE(target + 1, 0, 1, _value)
+#define REMOTE_INFO_CTRL_SET_GTK_EN(target, _value) \
+	SET_BITS_TO_LE_4BYTE(target + 1, 1, 1, _value)
+#define REMOTE_INFO_CTRL_SET_GTK_IDX(target, _value) \
+	SET_BITS_TO_LE_4BYTE(target + 2, 0, 8, _value)
+#endif /*CONFIG_WOWLAN*/
+
+void rtw_dump_phy_cap(void *sel, _adapter *adapter);
+void rtw_dump_rsvd_page(void *sel, _adapter *adapter, u8 page_offset, u8 page_num);
+#ifdef CONFIG_SUPPORT_FIFO_DUMP
+void rtw_dump_fifo(void *sel, _adapter *adapter, u8 fifo_sel, u32 fifo_addr, u32 fifo_size);
+#endif
+
+#ifdef CONFIG_FW_MULTI_PORT_SUPPORT
+s32 rtw_hal_set_default_port_id_cmd(_adapter *adapter, u8 mac_id);
+s32 rtw_set_default_port_id(_adapter *adapter);
+s32 rtw_set_ps_rsvd_page(_adapter *adapter);
+
+#define get_dft_portid(adapter) (adapter_to_dvobj(adapter)->dft.port_id)
+#define get_dft_macid(adapter) (adapter_to_dvobj(adapter)->dft.mac_id)
+
+/*void rtw_search_default_port(_adapter *adapter);*/
+#endif
+
+#ifdef CONFIG_P2P_PS
+#ifdef RTW_HALMAC
+void rtw_set_p2p_ps_offload_cmd(_adapter *adapter, u8 p2p_ps_state);
+#endif
+#endif
+
+#ifdef RTW_CHANNEL_SWITCH_OFFLOAD
+void rtw_hal_switch_chnl_and_set_bw_offload(_adapter *adapter, u8 central_ch, u8 pri_ch_idx, u8 bw);
+#endif
+
+s16 translate_dbm_to_percentage(s16 signal);
+
+#ifdef CONFIG_SUPPORT_MULTI_BCN
+void rtw_ap_multi_bcn_cfg(_adapter *adapter);
+#endif
+
+#ifdef CONFIG_SWTIMER_BASED_TXBCN
+#ifdef CONFIG_BCN_RECOVERY
+u8 rtw_ap_bcn_recovery(_adapter *padapter);
+#endif
+#ifdef CONFIG_BCN_XMIT_PROTECT
+u8 rtw_ap_bcn_queue_empty_check(_adapter *padapter, u32 txbcn_timer_ms);
+#endif
+#endif /*CONFIG_SWTIMER_BASED_TXBCN*/
+
+#ifdef CONFIG_FW_HANDLE_TXBCN
+void rtw_ap_mbid_bcn_en(_adapter *adapter, u8 mbcn_id);
+void rtw_ap_mbid_bcn_dis(_adapter *adapter, u8 mbcn_id);
+#endif
+
+void rtw_hal_get_rf_path(struct dvobj_priv *d, enum rf_type *type,
+			 enum bb_path *tx, enum bb_path *rx);
+#ifdef CONFIG_BEAMFORMING
+#ifdef RTW_BEAMFORMING_VERSION_2
+void rtw_hal_beamforming_config_csirate(PADAPTER adapter);
+#endif
+#endif
+#endif /* __HAL_COMMON_H__ */
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/include/hal_com_h2c.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/hal_com_h2c.h
--- linux-5.6.3/3rdparty/rtl8821ce/include/hal_com_h2c.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/hal_com_h2c.h	2020-04-10 16:35:06.846661469 +0300
@@ -0,0 +1,605 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#ifndef __COMMON_H2C_H__
+#define __COMMON_H2C_H__
+
+/* ---------------------------------------------------------------------------------------------------------
+ * ----------------------------------    H2C CMD DEFINITION    ------------------------------------------------
+ * ---------------------------------------------------------------------------------------------------------
+ * 88e, 8723b, 8812, 8821, 92e use the same FW code base */
+enum h2c_cmd {
+	/* Common Class: 000 */
+	H2C_RSVD_PAGE = 0x00,
+	H2C_MEDIA_STATUS_RPT = 0x01,
+	H2C_SCAN_ENABLE = 0x02,
+	H2C_KEEP_ALIVE = 0x03,
+	H2C_DISCON_DECISION = 0x04,
+	H2C_PSD_OFFLOAD = 0x05,
+	H2C_CUSTOMER_STR_REQ = 0x06,
+	H2C_AP_OFFLOAD = 0x08,
+	H2C_BCN_RSVDPAGE = 0x09,
+	H2C_PROBERSP_RSVDPAGE = 0x0A,
+	H2C_FCS_RSVDPAGE = 0x10,
+	H2C_FCS_INFO = 0x11,
+	H2C_AP_WOW_GPIO_CTRL = 0x13,
+#ifdef CONFIG_MCC_MODE
+	H2C_MCC_RQT_TSF = 0x15,
+	H2C_MCC_MACID_BITMAP = 0x16,
+	H2C_MCC_LOCATION = 0x10,
+	H2C_MCC_CTRL_V2 = 0x17,
+	H2C_MCC_CTRL = 0x18,
+	H2C_MCC_TIME_SETTING = 0x19,
+	H2C_MCC_IQK_PARAM = 0x1A,
+#endif /* CONFIG_MCC_MODE */
+	H2C_CHNL_SWITCH_OPER_OFFLOAD = 0x1C,
+	H2C_SINGLE_CHANNELSWITCH_V2 = 0x1D,
+
+	/* PoweSave Class: 001 */
+	H2C_SET_PWR_MODE = 0x20,
+	H2C_PS_TUNING_PARA = 0x21,
+	H2C_PS_TUNING_PARA2 = 0x22,
+	H2C_P2P_LPS_PARAM = 0x23,
+	H2C_P2P_PS_OFFLOAD = 0x24,
+	H2C_PS_SCAN_ENABLE = 0x25,
+	H2C_SAP_PS_ = 0x26,
+	H2C_INACTIVE_PS_ = 0x27, /* Inactive_PS */
+	H2C_FWLPS_IN_IPS_ = 0x28,
+#ifdef CONFIG_LPS_POFF
+	H2C_LPS_POFF_CTRL = 0x29,
+	H2C_LPS_POFF_PARAM = 0x2A,
+#endif
+#ifdef CONFIG_LPS_PG
+	H2C_LPS_PG_INFO = 0x2B,
+#endif
+
+#ifdef CONFIG_FW_MULTI_PORT_SUPPORT
+	H2C_DEFAULT_PORT_ID = 0x2C,
+#endif
+	/* Dynamic Mechanism Class: 010 */
+	H2C_MACID_CFG = 0x40,
+	H2C_TXBF = 0x41,
+	H2C_RSSI_SETTING = 0x42,
+	H2C_AP_REQ_TXRPT = 0x43,
+	H2C_INIT_RATE_COLLECT = 0x44,
+	H2C_IQ_CALIBRATION	= 0x45,
+
+	H2C_RA_MASK_3SS = 0x46,/* for 8814A */
+	H2C_RA_PARA_ADJUST = 0x47,/* CONFIG_RA_DBG_CMD */
+	H2C_DYNAMIC_TX_PATH = 0x48,/* for 8814A */
+
+	H2C_FW_TRACE_EN = 0x49,
+#ifdef RTW_PER_CMD_SUPPORT_FW
+	H2C_REQ_PER_RPT = 0x4e,
+#endif
+	/* BT Class: 011 */
+	H2C_B_TYPE_TDMA = 0x60,
+	H2C_BT_INFO = 0x61,
+	H2C_FORCE_BT_TXPWR = 0x62,
+	H2C_BT_IGNORE_WLANACT = 0x63,
+	H2C_DAC_SWING_VALUE = 0x64,
+	H2C_ANT_SEL_RSV = 0x65,
+	H2C_WL_OPMODE = 0x66,
+	H2C_BT_MP_OPER = 0x67,
+	H2C_BT_CONTROL = 0x68,
+	H2C_BT_WIFI_CTRL = 0x69,
+	H2C_BT_FW_PATCH = 0x6A,
+#if defined(CONFIG_BT_COEXIST) && defined(CONFIG_FW_MULTI_PORT_SUPPORT)
+	H2C_BTC_WL_PORT_ID = 0x71,
+#endif
+	/* WOWLAN Class: 100 */
+	H2C_WOWLAN = 0x80,
+	H2C_REMOTE_WAKE_CTRL = 0x81,
+	H2C_AOAC_GLOBAL_INFO = 0x82,
+	H2C_AOAC_RSVD_PAGE = 0x83,
+	H2C_AOAC_RSVD_PAGE2 = 0x84,
+	H2C_D0_SCAN_OFFLOAD_CTRL = 0x85,
+	H2C_D0_SCAN_OFFLOAD_INFO = 0x86,
+	H2C_CHNL_SWITCH_OFFLOAD = 0x87,
+	H2C_AOAC_RSVDPAGE3 = 0x88,
+	H2C_P2P_OFFLOAD_RSVD_PAGE = 0x8A,
+	H2C_P2P_OFFLOAD = 0x8B,
+#ifdef CONFIG_FW_HANDLE_TXBCN
+	H2C_FW_BCN_OFFLOAD = 0xBA,
+#endif
+	H2C_RESET_TSF = 0xC0,
+#ifdef CONFIG_FW_CORRECT_BCN
+	H2C_BCNHWSEQ = 0xC5,
+#endif
+	H2C_CUSTOMER_STR_W1 = 0xC6,
+	H2C_CUSTOMER_STR_W2 = 0xC7,
+	H2C_CUSTOMER_STR_W3 = 0xC8,
+#ifdef DBG_FW_DEBUG_MSG_PKT
+	H2C_FW_DBG_MSG_PKT = 0xE1,
+#endif /*DBG_FW_DEBUG_MSG_PKT*/
+	H2C_MAXID,
+};
+
+#define H2C_INACTIVE_PS_LEN		3
+#define H2C_RSVDPAGE_LOC_LEN		5
+#ifdef CONFIG_FW_MULTI_PORT_SUPPORT
+#define H2C_DEFAULT_PORT_ID_LEN		2
+#define H2C_MEDIA_STATUS_RPT_LEN		4
+#else
+#define H2C_MEDIA_STATUS_RPT_LEN		3
+#endif
+#define H2C_KEEP_ALIVE_CTRL_LEN	2
+#define H2C_DISCON_DECISION_LEN		3
+#define H2C_AP_OFFLOAD_LEN		3
+#define H2C_AP_WOW_GPIO_CTRL_LEN	4
+#define H2C_AP_PS_LEN			2
+#define H2C_PWRMODE_LEN			7
+#define H2C_PSTUNEPARAM_LEN			4
+#define H2C_MACID_CFG_LEN		7
+#define H2C_BTMP_OPER_LEN			5
+#define H2C_WOWLAN_LEN			7
+#define H2C_REMOTE_WAKE_CTRL_LEN	3
+#define H2C_AOAC_GLOBAL_INFO_LEN	2
+#define H2C_AOAC_RSVDPAGE_LOC_LEN	7
+#define H2C_SCAN_OFFLOAD_CTRL_LEN	4
+#define H2C_BT_FW_PATCH_LEN			6
+#define H2C_RSSI_SETTING_LEN		4
+#define H2C_AP_REQ_TXRPT_LEN		3
+#define H2C_FORCE_BT_TXPWR_LEN		3
+#define H2C_BCN_RSVDPAGE_LEN		5
+#define H2C_PROBERSP_RSVDPAGE_LEN	5
+#define H2C_P2PRSVDPAGE_LOC_LEN	5
+#define H2C_P2P_OFFLOAD_LEN	3
+#ifdef CONFIG_MCC_MODE
+	#define H2C_MCC_CTRL_LEN			7
+#ifdef CONFIG_MCC_MODE_V2
+	#define H2C_MCC_LOCATION_LEN		7
+#else
+	#define H2C_MCC_LOCATION_LEN		3
+#endif
+	#define H2C_MCC_MACID_BITMAP_LEN	6
+	#define H2C_MCC_RQT_TSF_LEN		1
+	#define H2C_MCC_TIME_SETTING_LEN		6
+	#define H2C_MCC_IQK_PARAM_LEN		7
+#endif /* CONFIG_MCC_MODE */
+#ifdef CONFIG_LPS_PG
+	#define H2C_LPS_PG_INFO_LEN		2
+	#define H2C_LPSPG_LEN			16
+#endif
+#ifdef CONFIG_LPS_POFF
+	#define H2C_LPS_POFF_CTRL_LEN		1
+	#define H2C_LPS_POFF_PARAM_LEN		5
+#endif
+
+#if defined(CONFIG_BT_COEXIST) && defined(CONFIG_FW_MULTI_PORT_SUPPORT)
+#define H2C_BTC_WL_PORT_ID_LEN	1
+#endif
+
+#ifdef DBG_FW_DEBUG_MSG_PKT
+	#define H2C_FW_DBG_MSG_PKT_LEN	2
+#endif /*DBG_FW_DEBUG_MSG_PKT*/
+
+#define H2C_SINGLE_CHANNELSWITCH_V2_LEN 2
+
+#define eq_mac_addr(a, b)						(((a)[0] == (b)[0] && (a)[1] == (b)[1] && (a)[2] == (b)[2] && (a)[3] == (b)[3] && (a)[4] == (b)[4] && (a)[5] == (b)[5]) ? 1 : 0)
+#define cp_mac_addr(des, src)					((des)[0] = (src)[0], (des)[1] = (src)[1], (des)[2] = (src)[2], (des)[3] = (src)[3], (des)[4] = (src)[4], (des)[5] = (src)[5])
+#define cpIpAddr(des, src)					((des)[0] = (src)[0], (des)[1] = (src)[1], (des)[2] = (src)[2], (des)[3] = (src)[3])
+
+
+#if defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN)
+#define FW_WOWLAN_FUN_EN				BIT(0)
+#define FW_WOWLAN_PATTERN_MATCH			BIT(1)
+#define FW_WOWLAN_MAGIC_PKT				BIT(2)
+#define FW_WOWLAN_UNICAST				BIT(3)
+#define FW_WOWLAN_ALL_PKT_DROP			BIT(4)
+#define FW_WOWLAN_GPIO_ACTIVE			BIT(5)
+#define FW_WOWLAN_REKEY_WAKEUP			BIT(6)
+#define FW_WOWLAN_DEAUTH_WAKEUP			BIT(7)
+
+#define FW_WOWLAN_GPIO_WAKEUP_EN		BIT(0)
+#define FW_FW_PARSE_MAGIC_PKT			BIT(1)
+
+#define FW_REMOTE_WAKE_CTRL_EN			BIT(0)
+#define FW_REALWOWLAN_EN				BIT(5)
+
+#define FW_WOWLAN_KEEP_ALIVE_EN			BIT(0)
+#define FW_ADOPT_USER					BIT(1)
+#define FW_WOWLAN_KEEP_ALIVE_PKT_TYPE	BIT(2)
+
+#define FW_REMOTE_WAKE_CTRL_EN			BIT(0)
+#define FW_ARP_EN						BIT(1)
+#define FW_REALWOWLAN_EN				BIT(5)
+#define FW_WOW_FW_UNICAST_EN			BIT(7)
+
+#endif /* CONFIG_WOWLAN */
+
+/* _RSVDPAGE_LOC_CMD_0x00 */
+#define SET_H2CCMD_RSVDPAGE_LOC_PROBE_RSP(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
+#define SET_H2CCMD_RSVDPAGE_LOC_PSPOLL(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 8, __Value)
+#define SET_H2CCMD_RSVDPAGE_LOC_NULL_DATA(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value)
+#define SET_H2CCMD_RSVDPAGE_LOC_QOS_NULL_DATA(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 8, __Value)
+#define SET_H2CCMD_RSVDPAGE_LOC_BT_QOS_NULL_DATA(__pH2CCmd, __Value)SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 0, 8, __Value)
+
+/* _MEDIA_STATUS_RPT_PARM_CMD_0x01 */
+#define SET_H2CCMD_MSRRPT_PARM_OPMODE(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE(((u8 *)(__pH2CCmd)), 0, 1, (__Value))
+#define SET_H2CCMD_MSRRPT_PARM_MACID_IND(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(((u8 *)(__pH2CCmd)), 1, 1, (__Value))
+#define SET_H2CCMD_MSRRPT_PARM_MIRACAST(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE(((u8 *)(__pH2CCmd)), 2, 1, (__Value))
+#define SET_H2CCMD_MSRRPT_PARM_MIRACAST_SINK(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE(((u8 *)(__pH2CCmd)), 3, 1, (__Value))
+#define SET_H2CCMD_MSRRPT_PARM_ROLE(__pH2CCmd, __Value)				SET_BITS_TO_LE_1BYTE(((u8 *)(__pH2CCmd)), 4, 4, (__Value))
+#define SET_H2CCMD_MSRRPT_PARM_MACID(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE(((u8 *)(__pH2CCmd)) + 1, 0, 8, (__Value))
+#define SET_H2CCMD_MSRRPT_PARM_MACID_END(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(((u8 *)(__pH2CCmd)) + 2, 0, 8, (__Value))
+#define SET_H2CCMD_MSRRPT_PARM_PORT_NUM(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE(((u8 *)(__pH2CCmd)) + 3, 0, 3, (__Value))
+
+#define GET_H2CCMD_MSRRPT_PARM_OPMODE(__pH2CCmd)		LE_BITS_TO_1BYTE(((u8 *)(__pH2CCmd)), 0, 1)
+#define GET_H2CCMD_MSRRPT_PARM_MIRACAST(__pH2CCmd)		LE_BITS_TO_1BYTE(((u8 *)(__pH2CCmd)), 2, 1)
+#define GET_H2CCMD_MSRRPT_PARM_MIRACAST_SINK(__pH2CCmd)	LE_BITS_TO_1BYTE(((u8 *)(__pH2CCmd)), 3, 1)
+#define GET_H2CCMD_MSRRPT_PARM_ROLE(__pH2CCmd)			LE_BITS_TO_1BYTE(((u8 *)(__pH2CCmd)), 4, 4)
+
+#define H2C_MSR_ROLE_RSVD	0
+#define H2C_MSR_ROLE_STA	1
+#define H2C_MSR_ROLE_AP		2
+#define H2C_MSR_ROLE_GC		3
+#define H2C_MSR_ROLE_GO		4
+#define H2C_MSR_ROLE_TDLS	5
+#define H2C_MSR_ROLE_ADHOC	6
+#define H2C_MSR_ROLE_MESH	7
+#define H2C_MSR_ROLE_MAX	8
+
+extern const char *const _h2c_msr_role_str[];
+#define h2c_msr_role_str(role) (((role) >= H2C_MSR_ROLE_MAX) ? _h2c_msr_role_str[H2C_MSR_ROLE_MAX] : _h2c_msr_role_str[(role)])
+
+#define H2C_MSR_FMT "%s %s%s"
+#define H2C_MSR_ARG(h2c_msr) \
+	GET_H2CCMD_MSRRPT_PARM_OPMODE((h2c_msr)) ? " C" : "", \
+	h2c_msr_role_str(GET_H2CCMD_MSRRPT_PARM_ROLE((h2c_msr))), \
+	GET_H2CCMD_MSRRPT_PARM_MIRACAST((h2c_msr)) ? (GET_H2CCMD_MSRRPT_PARM_MIRACAST_SINK((h2c_msr)) ? " MSINK" : " MSRC") : ""
+
+s32 rtw_hal_set_FwMediaStatusRpt_cmd(_adapter *adapter, bool opmode, bool miracast, bool miracast_sink, u8 role, u8 macid, bool macid_ind, u8 macid_end);
+s32 rtw_hal_set_FwMediaStatusRpt_single_cmd(_adapter *adapter, bool opmode, bool miracast, bool miracast_sink, u8 role, u8 macid);
+s32 rtw_hal_set_FwMediaStatusRpt_range_cmd(_adapter *adapter, bool opmode, bool miracast, bool miracast_sink, u8 role, u8 macid, u8 macid_end);
+
+/* _KEEP_ALIVE_CMD_0x03 */
+#define SET_H2CCMD_KEEPALIVE_PARM_ENABLE(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 1, __Value)
+#define SET_H2CCMD_KEEPALIVE_PARM_ADOPT(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd, 1, 1, __Value)
+#define SET_H2CCMD_KEEPALIVE_PARM_PKT_TYPE(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd, 2, 1, __Value)
+#define SET_H2CCMD_KEEPALIVE_PARM_PORT_NUM(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd, 3, 3, __Value)
+#define SET_H2CCMD_KEEPALIVE_PARM_CHECK_PERIOD(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 0, 8, __Value)
+
+/* _DISCONNECT_DECISION_CMD_0x04 */
+#define SET_H2CCMD_DISCONDECISION_PARM_ENABLE(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 1, __Value)
+#define SET_H2CCMD_DISCONDECISION_PARM_ADOPT(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd, 1, 1, __Value)
+#define SET_H2CCMD_DISCONDECISION_PORT_NUM(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE(__pH2CCmd, 4, 3, __Value)
+#define SET_H2CCMD_DISCONDECISION_PARM_CHECK_PERIOD(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 0, 8, __Value)
+#define SET_H2CCMD_DISCONDECISION_PARM_TRY_PKT_NUM(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 0, 8, __Value)
+
+#ifdef CONFIG_RTW_CUSTOMER_STR
+#define RTW_CUSTOMER_STR_LEN 16
+#define RTW_CUSTOMER_STR_FMT "%02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x"
+#define RTW_CUSTOMER_STR_ARG(x) ((u8 *)(x))[0], ((u8 *)(x))[1], ((u8 *)(x))[2], ((u8 *)(x))[3], ((u8 *)(x))[4], ((u8 *)(x))[5], \
+	((u8 *)(x))[6], ((u8 *)(x))[7], ((u8 *)(x))[8], ((u8 *)(x))[9], ((u8 *)(x))[10], ((u8 *)(x))[11], \
+	((u8 *)(x))[12], ((u8 *)(x))[13], ((u8 *)(x))[14], ((u8 *)(x))[15]
+
+/* H2C_CUSTOMER_STR_REQ  0x06 */
+#define H2C_CUSTOMER_STR_REQ_LEN 1
+#define SET_H2CCMD_CUSTOMER_STR_REQ_EN(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE(((u8 *)(__pH2CCmd)), 0, 1, (__Value))
+s32 rtw_hal_h2c_customer_str_req(_adapter *adapter);
+s32 rtw_hal_customer_str_read(_adapter *adapter, u8 *cs);
+
+/* H2C_CUSTOMER_STR_W1 0xC6 */
+#define H2C_CUSTOMER_STR_W1_LEN 7
+#define SET_H2CCMD_CUSTOMER_STR_W1_EN(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE(((u8 *)(__pH2CCmd)), 0, 1, (__Value))
+#define H2CCMD_CUSTOMER_STR_W1_BYTE0(__pH2CCmd)				(((u8 *)(__pH2CCmd)) + 1)
+
+/* H2C_CUSTOMER_STR_W2 0xC7 */
+#define H2C_CUSTOMER_STR_W2_LEN 7
+#define SET_H2CCMD_CUSTOMER_STR_W2_EN(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE(((u8 *)(__pH2CCmd)), 0, 1, (__Value))
+#define H2CCMD_CUSTOMER_STR_W2_BYTE6(__pH2CCmd)				(((u8 *)(__pH2CCmd)) + 1)
+
+/* H2C_CUSTOMER_STR_W3 0xC8 */
+#define H2C_CUSTOMER_STR_W3_LEN 5
+#define SET_H2CCMD_CUSTOMER_STR_W3_EN(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE(((u8 *)(__pH2CCmd)), 0, 1, (__Value))
+#define H2CCMD_CUSTOMER_STR_W3_BYTE12(__pH2CCmd)			(((u8 *)(__pH2CCmd)) + 1)
+s32 rtw_hal_h2c_customer_str_write(_adapter *adapter, const u8 *cs);
+s32 rtw_hal_customer_str_write(_adapter *adapter, const u8 *cs);
+#endif /* CONFIG_RTW_CUSTOMER_STR */
+
+/* _AP_Offload 0x08 */
+#define SET_H2CCMD_AP_WOWLAN_EN(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
+/* _BCN_RsvdPage	0x09 */
+#define SET_H2CCMD_AP_WOWLAN_RSVDPAGE_LOC_BCN(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
+/* _Probersp_RsvdPage 0x0a */
+#define SET_H2CCMD_AP_WOWLAN_RSVDPAGE_LOC_ProbeRsp(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
+/* _Probersp_RsvdPage 0x13 */
+#define SET_H2CCMD_AP_WOW_GPIO_CTRL_INDEX(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 4, __Value)
+#define SET_H2CCMD_AP_WOW_GPIO_CTRL_C2H_EN(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd, 4, 1, __Value)
+#define SET_H2CCMD_AP_WOW_GPIO_CTRL_PLUS(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd, 5, 1, __Value)
+#define SET_H2CCMD_AP_WOW_GPIO_CTRL_HIGH_ACTIVE(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE(__pH2CCmd, 6, 1, __Value)
+#define SET_H2CCMD_AP_WOW_GPIO_CTRL_EN(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd, 7, 1, __Value)
+#define SET_H2CCMD_AP_WOW_GPIO_CTRL_DURATION(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 8, __Value)
+#define SET_H2CCMD_AP_WOW_GPIO_CTRL_C2H_DURATION(__pH2CCmd, __Value)SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value)
+/* _AP_PS 0x26 */
+#define SET_H2CCMD_AP_WOW_PS_EN(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 1, __Value)
+#define SET_H2CCMD_AP_WOW_PS_32K_EN(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd, 1, 1, __Value)
+#define SET_H2CCMD_AP_WOW_PS_RF(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE(__pH2CCmd, 2, 1, __Value)
+#define SET_H2CCMD_AP_WOW_PS_DURATION(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 8, __Value)
+
+#ifdef CONFIG_LPS_POFF
+/*PARTIAL OFF Control 0x29*/
+#define SET_H2CCMD_LPS_POFF_CTRL_EN(__pH2CCmd, __Value) \
+	SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 1, __Value)
+/*PARTIAL OFF PARAM   0x2A*/
+#define SET_H2CCMD_LPS_POFF_PARAM_RDVLD(__pH2CCmd, __Value) \
+	SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 1, __Value)
+#define SET_H2CCMD_LPS_POFF_PARAM_WRVLD(__pH2CCmd, __Value) \
+	SET_BITS_TO_LE_1BYTE(__pH2CCmd, 1, 1, __Value)
+#define SET_H2CCMD_LPS_POFF_PARAM_STARTADDL(__pH2CCmd, __Value) \
+	SET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 0, 8, __Value)
+#define SET_H2CCMD_LPS_POFF_PARAM_STARTADDH(__pH2CCmd, __Value) \
+	SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 0, 8, __Value)
+#define SET_H2CCMD_LPS_POFF_PARAM_ENDADDL(__pH2CCmd, __Value) \
+	SET_BITS_TO_LE_1BYTE(__pH2CCmd+3, 0, 8, __Value)
+#define SET_H2CCMD_LPS_POFF_PARAM_ENDADDH(__pH2CCmd, __Value) \
+	SET_BITS_TO_LE_1BYTE(__pH2CCmd+4, 0, 8, __Value)
+#endif
+
+#ifdef CONFIG_FW_MULTI_PORT_SUPPORT
+/* DEFAULT PORT ID 0x2C*/
+#define SET_H2CCMD_DFTPID_PORT_ID(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE(((u8 *)(__pH2CCmd)), 0, 8, (__Value))
+#define SET_H2CCMD_DFTPID_MAC_ID(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE(((u8 *)(__pH2CCmd)) + 1, 0, 8, (__Value))
+#endif
+
+#ifdef CONFIG_MCC_MODE
+/* MCC LOC CMD 0x10 */
+#define SET_H2CCMD_MCC_RSVDPAGE_LOC(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
+#define SET_H2CCMD_MCC_PWRIDX_OFFLOAD_EN(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE((__pH2CCmd) + 3, 0, 1, __Value)
+#define SET_H2CCMD_MCC_PWRIDX_OFFLOAD_RFNUM(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE((__pH2CCmd) + 3, 4, 4, __Value)
+#define SET_H2CCMD_MCC_PWRIDX_RSVDPAGE_LOC(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE((__pH2CCmd) + 4, 0, 8, __Value)
+
+/* MCC RQT TSF 0x15 */
+#define SET_H2CCMD_MCC_RQT_TSFX(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 4, __Value)
+#define SET_H2CCMD_MCC_RQT_TSFY(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE(__pH2CCmd, 4, 4, __Value)
+
+/* MCC MAC ID CMD 0x16 */
+#define SET_H2CCMD_MCC_MACID_BITMAP_L(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
+#define SET_H2CCMD_MCC_MACID_BITMAP_H(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 8, __Value)
+
+/* NEW MCC CTRL CMD 0x17 */
+#define SET_H2CCMD_MCC_CTRL_V2_ORDER(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 4, __Value)
+#define SET_H2CCMD_MCC_CTRL_V2_TOTALNUM(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE(__pH2CCmd, 4, 4, __Value)
+#define SET_H2CCMD_MCC_CTRL_V2_CENTRAL_CH(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 8, __Value)
+#define SET_H2CCMD_MCC_CTRL_V2_PRIMARY_CH(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 4, __Value)
+#define SET_H2CCMD_MCC_CTRL_V2_BW(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 4, 4, __Value)
+#define SET_H2CCMD_MCC_CTRL_V2_DURATION(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 8, __Value)
+#define SET_H2CCMD_MCC_CTRL_V2_ROLE(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 0, 3, __Value)			
+#define SET_H2CCMD_MCC_CTRL_V2_INCURCH(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 3, 1, __Value)
+#define SET_H2CCMD_MCC_CTRL_V2_DIS_SW_RETRY(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 4, 1, __Value)
+#define SET_H2CCMD_MCC_CTRL_V2_DISTXNULL(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 5, 1, __Value)
+#define SET_H2CCMD_MCC_CTRL_V2_C2HRPT(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 6, 2, __Value)
+#define SET_H2CCMD_MCC_CTRL_V2_TSFX(__pH2CCmd, __Value)				SET_BITS_TO_LE_1BYTE((__pH2CCmd)+5, 0, 4, __Value)
+#define SET_H2CCMD_MCC_CTRL_V2_NULL_EARLY(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE((__pH2CCmd)+5, 4, 4, __Value)
+#define SET_H2CCMD_MCC_CTRL_V2_UPDATE_PARM(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE((__pH2CCmd)+6, 7, 1, __Value)
+
+
+/* MCC CTRL CMD 0x18 */
+#define SET_H2CCMD_MCC_CTRL_ORDER(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 4, __Value)
+#define SET_H2CCMD_MCC_CTRL_TOTALNUM(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE(__pH2CCmd, 4, 4, __Value)
+#define SET_H2CCMD_MCC_CTRL_CHIDX(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 8, __Value)
+#define SET_H2CCMD_MCC_CTRL_BW(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 2, __Value)
+#define SET_H2CCMD_MCC_CTRL_BW40SC(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 2, 3, __Value)
+#define SET_H2CCMD_MCC_CTRL_BW80SC(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 5, 3, __Value)
+#define SET_H2CCMD_MCC_CTRL_DURATION(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 8, __Value)
+#define SET_H2CCMD_MCC_CTRL_ROLE(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 0, 3, __Value)
+#define SET_H2CCMD_MCC_CTRL_INCURCH(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 3, 1, __Value)
+#define SET_H2CCMD_MCC_CTRL_RSVD0(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 4, 4, __Value)
+#define SET_H2CCMD_MCC_CTRL_RSVD1(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE((__pH2CCmd)+5, 0, 8, __Value)
+#define SET_H2CCMD_MCC_CTRL_RFETYPE(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE((__pH2CCmd)+6, 0, 4, __Value)
+#define SET_H2CCMD_MCC_CTRL_DISTXNULL(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE((__pH2CCmd)+6, 4, 1, __Value)
+#define SET_H2CCMD_MCC_CTRL_C2HRPT(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE((__pH2CCmd)+6, 5, 2, __Value)
+#define SET_H2CCMD_MCC_CTRL_CHSCAN(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE((__pH2CCmd)+6, 7, 1, __Value)
+
+/* MCC Time CMD 0x19 */
+#define SET_H2CCMD_MCC_TIME_SETTING_FW_EN(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 1, __Value)
+#define SET_H2CCMD_MCC_TIME_SETTING_TSF_SYNC_OFFSET(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE(__pH2CCmd, 1, 7, __Value)
+#define SET_H2CCMD_MCC_TIME_SETTING_START_TIME(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 8, __Value)
+#define SET_H2CCMD_MCC_TIME_SETTING_INTERVAL(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value)
+#define SET_H2CCMD_MCC_TIME_SETTING_EARLY_SWITCH_RPT(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 8, __Value)
+#define  SET_H2CCMD_MCC_TIME_SETTING_ORDER_BASE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 0, 4, __Value)
+#define  SET_H2CCMD_MCC_TIME_SETTING_ORDER_SYNC(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 4, 4, __Value)
+#define  SET_H2CCMD_MCC_TIME_SETTING_UPDATE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+5, 0, 1, __Value)
+#define  SET_H2CCMD_MCC_TIME_SETTING_ORDER0_DURATION(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+5, 1, 7, __Value)
+
+/* MCC IQK CMD 0x1A */
+#define SET_H2CCMD_MCC_IQK_READY(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 1, __Value)
+#define SET_H2CCMD_MCC_IQK_ORDER(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE(__pH2CCmd, 1, 4, __Value)
+#define SET_H2CCMD_MCC_IQK_PATH(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE(__pH2CCmd, 5, 2, __Value)
+#define SET_H2CCMD_MCC_IQK_RX_L(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 8, __Value)
+#define SET_H2CCMD_MCC_IQK_RX_M1(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 2, __Value)
+#define SET_H2CCMD_MCC_IQK_RX_M2(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 2, 6, __Value)
+#define SET_H2CCMD_MCC_IQK_RX_H(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 4, __Value)
+#define SET_H2CCMD_MCC_IQK_TX_L(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 0, 8, __Value)
+#define SET_H2CCMD_MCC_IQK_TX_M1(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE((__pH2CCmd)+5, 0, 3, __Value)
+#define SET_H2CCMD_MCC_IQK_TX_M2(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE((__pH2CCmd)+5, 3, 5, __Value)
+#define SET_H2CCMD_MCC_IQK_TX_H(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE((__pH2CCmd)+6, 0, 6, __Value)
+#endif /* CONFIG_MCC_MODE */
+
+/* CHNL SWITCH OPER OFFLOAD 0x1C */
+#define SET_H2CCMD_CH_SW_OPER_OFFLOAD_CH_NUM(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
+#define SET_H2CCMD_CH_SW_OPER_OFFLOAD_BW_MODE(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE((__pH2CCmd) + 1, 0, 2, __Value)
+#define SET_H2CCMD_CH_SW_OPER_OFFLOAD_BW_40M_SC(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE((__pH2CCmd) + 1, 2, 3, __Value)
+#define SET_H2CCMD_CH_SW_OPER_OFFLOAD_BW_80M_SC(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE((__pH2CCmd) + 1, 5, 3, __Value)
+#define SET_H2CCMD_CH_SW_OPER_OFFLOAD_RFE_TYPE(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE((__pH2CCmd) + 2, 0, 4, __Value)
+
+/* H2C_SINGLE_CHANNELSWITCH_V2 = 0x1D */
+#define SET_H2CCMD_SINGLE_CH_SWITCH_V2_CENTRAL_CH_NUM(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
+#define SET_H2CCMD_SINGLE_CH_SWITCH_V2_PRIMARY_CH_IDX(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE((__pH2CCmd) + 1, 0, 4, __Value)
+#define SET_H2CCMD_SINGLE_CH_SWITCH_V2_BW(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE((__pH2CCmd) + 1, 4, 4, __Value)
+
+
+#if defined(CONFIG_BT_COEXIST) && defined(CONFIG_FW_MULTI_PORT_SUPPORT)
+#define SET_H2CCMD_BTC_WL_PORT_ID(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 4, __Value)
+#endif
+
+/* _WoWLAN PARAM_CMD_0x80 */
+#define SET_H2CCMD_WOWLAN_FUNC_ENABLE(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 1, __Value)
+#define SET_H2CCMD_WOWLAN_PATTERN_MATCH_ENABLE(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE(__pH2CCmd, 1, 1, __Value)
+#define SET_H2CCMD_WOWLAN_MAGIC_PKT_ENABLE(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd, 2, 1, __Value)
+#define SET_H2CCMD_WOWLAN_UNICAST_PKT_ENABLE(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE(__pH2CCmd, 3, 1, __Value)
+#define SET_H2CCMD_WOWLAN_ALL_PKT_DROP(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE(__pH2CCmd, 4, 1, __Value)
+#define SET_H2CCMD_WOWLAN_GPIO_ACTIVE(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE(__pH2CCmd, 5, 1, __Value)
+#define SET_H2CCMD_WOWLAN_REKEY_WAKE_UP(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE(__pH2CCmd, 6, 1, __Value)
+#define SET_H2CCMD_WOWLAN_DISCONNECT_WAKE_UP(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE(__pH2CCmd, 7, 1, __Value)
+#define SET_H2CCMD_WOWLAN_GPIONUM(__pH2CCmd, __Value)				SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 7, __Value)
+#define SET_H2CCMD_WOWLAN_DATAPIN_WAKE_UP(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 7, 1, __Value)
+#define SET_H2CCMD_WOWLAN_GPIO_DURATION(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value)
+#define SET_H2CCMD_WOWLAN_GPIO_PULSE_EN(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 1, __Value)
+#define SET_H2CCMD_WOWLAN_GPIO_PULSE_COUNT(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 1, 7, __Value)
+#define SET_H2CCMD_WOWLAN_DISABLE_UPHY(__pH2CCmd, __Value)				SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 0, 1, __Value)
+#define SET_H2CCMD_WOWLAN_HST2DEV_EN(__pH2CCmd, __Value)				SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 1, 1, __Value)
+#define SET_H2CCMD_WOWLAN_GPIO_DURATION_MS(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 2, 1, __Value)
+#define SET_H2CCMD_WOWLAN_CHANGE_UNIT(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 2, 1, __Value)
+#define SET_H2CCMD_WOWLAN_UNIT_FOR_UPHY_DISABLE(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 3, 1, __Value)
+#define SET_H2CCMD_WOWLAN_TAKE_PDN_UPHY_DIS_EN(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 4, 1, __Value)
+#define SET_H2CCMD_WOWLAN_GPIO_INPUT_EN(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 5, 1, __Value)
+#define SET_H2CCMD_WOWLAN_DEV2HST_EN(__pH2CCmd, __Value) 	SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 7, 1, __Value)
+#define SET_H2CCMD_WOWLAN_TIME_FOR_UPHY_DISABLE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+5, 0, 8, __Value)
+#define SET_H2CCMD_WOWLAN_RISE_HST2DEV(__pH2CCmd, __Value) 	SET_BITS_TO_LE_1BYTE((__pH2CCmd)+6, 2, 1, __Value)
+
+/* _REMOTE_WAKEUP_CMD_0x81 */
+#define SET_H2CCMD_REMOTE_WAKECTRL_ENABLE(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 1, __Value)
+#define SET_H2CCMD_REMOTE_WAKE_CTRL_ARP_OFFLOAD_EN(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE(__pH2CCmd, 1, 1, __Value)
+#define SET_H2CCMD_REMOTE_WAKE_CTRL_NDP_OFFLOAD_EN(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE(__pH2CCmd, 2, 1, __Value)
+#define SET_H2CCMD_REMOTE_WAKE_CTRL_GTK_OFFLOAD_EN(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE(__pH2CCmd, 3, 1, __Value)
+#define SET_H2CCMD_REMOTE_WAKE_CTRL_NLO_OFFLOAD_EN(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE(__pH2CCmd, 4, 1, __Value)
+#define SET_H2CCMD_REMOTE_WAKE_CTRL_FW_UNICAST_EN(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE(__pH2CCmd, 7, 1, __Value)
+#define SET_H2CCMD_REMOTE_WAKE_CTRL_P2P_OFFLAD_EN(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 1, __Value)
+#define SET_H2CCMD_REMOTE_WAKE_CTRL_NBNS_FILTER_EN(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 2, 1, __Value)
+#define SET_H2CCMD_REMOTE_WAKE_CTRL_TKIP_OFFLOAD_EN(__pH2CCmd, __Value) \
+	SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 3, 1, __Value)
+
+#define SET_H2CCMD_REMOTE_WAKE_CTRL_ARP_ACTION(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 1, __Value)
+#define SET_H2CCMD_REMOTE_WAKE_CTRL_FW_PARSING_UNTIL_WAKEUP(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 4, 1, __Value)
+
+/* AOAC_GLOBAL_INFO_0x82 */
+#define SET_H2CCMD_AOAC_GLOBAL_INFO_PAIRWISE_ENC_ALG(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
+#define SET_H2CCMD_AOAC_GLOBAL_INFO_GROUP_ENC_ALG(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 8, __Value)
+
+/* AOAC_RSVDPAGE_LOC_0x83 */
+#define SET_H2CCMD_AOAC_RSVDPAGE_LOC_REMOTE_WAKE_CTRL_INFO(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE((__pH2CCmd), 0, 8, __Value)
+#define SET_H2CCMD_AOAC_RSVDPAGE_LOC_ARP_RSP(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 8, __Value)
+#define SET_H2CCMD_AOAC_RSVDPAGE_LOC_NEIGHBOR_ADV(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value)
+#define SET_H2CCMD_AOAC_RSVDPAGE_LOC_GTK_RSP(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 8, __Value)
+#define SET_H2CCMD_AOAC_RSVDPAGE_LOC_GTK_INFO(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 0, 8, __Value)
+#ifdef CONFIG_GTK_OL
+#define SET_H2CCMD_AOAC_RSVDPAGE_LOC_GTK_EXT_MEM(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE((__pH2CCmd)+5, 0, 8, __Value)
+#endif /* CONFIG_GTK_OL */
+#define SET_H2CCMD_AOAC_RSVDPAGE_LOC_NDP_INFO(__pH2CCmd, __Value) \
+	SET_BITS_TO_LE_1BYTE((__pH2CCmd)+6, 0, 8, __Value)
+
+/* AOAC_RSVDPAGE_2_0x84 */
+
+/* AOAC_RSVDPAGE_3_0x88 */
+#ifdef CONFIG_PNO_SUPPORT
+#define SET_H2CCMD_AOAC_RSVDPAGE_LOC_NLO_INFO(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE((__pH2CCmd), 0, 8, __Value)
+#endif
+#define SET_H2CCMD_AOAC_RSVDPAGE_LOC_AOAC_REPORT(__pH2CCmd, __Value) \
+	SET_BITS_TO_LE_1BYTE((__pH2CCmd) + 1, 0, 8, __Value)
+
+#ifdef CONFIG_PNO_SUPPORT
+/* D0_Scan_Offload_Info_0x86 */
+#define SET_H2CCMD_AOAC_NLO_FUN_EN(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE((__pH2CCmd), 3, 1, __Value)
+#define SET_H2CCMD_AOAC_NLO_IPS_EN(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE((__pH2CCmd), 4, 1, __Value)
+#define SET_H2CCMD_AOAC_RSVDPAGE_LOC_PROBE_PACKET(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 8, __Value)
+#define SET_H2CCMD_AOAC_RSVDPAGE_LOC_SCAN_INFO(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value)
+#define SET_H2CCMD_AOAC_RSVDPAGE_LOC_SSID_INFO(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 8, __Value)
+#endif /* CONFIG_PNO_SUPPORT */
+
+#ifdef CONFIG_P2P_WOWLAN
+/* P2P_RsvdPage_0x8a */
+#define SET_H2CCMD_RSVDPAGE_LOC_P2P_BCN(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
+#define SET_H2CCMD_RSVDPAGE_LOC_P2P_PROBE_RSP(__pH2CCmd, __Value)				SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 8, __Value)
+#define SET_H2CCMD_RSVDPAGE_LOC_P2P_NEGO_RSP(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value)
+#define SET_H2CCMD_RSVDPAGE_LOC_P2P_INVITE_RSP(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 8, __Value)
+#define SET_H2CCMD_RSVDPAGE_LOC_P2P_PD_RSP(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 0, 8, __Value)
+#endif /* CONFIG_P2P_WOWLAN */
+
+#ifdef CONFIG_LPS_PG
+#define SET_H2CCMD_LPSPG_SEC_CAM_EN(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 1, __Value)/*SecurityCAM_En*/
+#define SET_H2CCMD_LPSPG_MBID_CAM_EN(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE(__pH2CCmd, 1, 1, __Value)/*BSSIDCAM_En*/
+#define SET_H2CCMD_LPSPG_PMC_CAM_EN(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE(__pH2CCmd, 2, 1, __Value)/*PatternMatchCAM_En*/
+#define SET_H2CCMD_LPSPG_MACID_SEARCH_EN(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE(__pH2CCmd, 3, 1, __Value)/*MACIDSearch_En*/
+#define SET_H2CCMD_LPSPG_TXSC_EN(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE(__pH2CCmd, 4, 1, __Value)/*TXSC_En*/
+#define SET_H2CCMD_LPSPG_MU_RATE_TB_EN(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE(__pH2CCmd, 5, 1, __Value)/*MURateTable_En*/
+#define SET_H2CCMD_LPSPG_LOC(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 0, 8, __Value)/*Loc_LPS_PG*/
+#endif
+
+#ifdef DBG_FW_DEBUG_MSG_PKT
+#define SET_H2CCMD_FW_DBG_MSG_PKT_EN(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 1, __Value)/*sniffer_dbg_en*/
+#define SET_H2CCMD_RSVDPAGE_LOC_FW_DBG_MSG_PKT(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 8, __Value) /*loc_debug_packet*/
+#endif /*DBG_FW_DEBUG_MSG_PKT*/
+
+/* ---------------------------------------------------------------------------------------------------------
+ * -------------------------------------------    Structure    --------------------------------------------------
+ * --------------------------------------------------------------------------------------------------------- */
+typedef struct _RSVDPAGE_LOC {
+	u8 LocProbeRsp;
+	u8 LocPsPoll;
+	u8 LocNullData;
+	u8 LocQosNull;
+	u8 LocBTQosNull;
+#ifdef CONFIG_WOWLAN
+	u8 LocRemoteCtrlInfo;
+	u8 LocArpRsp;
+	u8 LocNbrAdv;
+	u8 LocGTKRsp;
+	u8 LocGTKInfo;
+	u8 LocProbeReq;
+	u8 LocNetList;
+#ifdef CONFIG_GTK_OL
+	u8 LocGTKEXTMEM;
+#endif /* CONFIG_GTK_OL */
+	u8 LocNDPInfo;
+	u8 LocAOACReport;
+#ifdef CONFIG_PNO_SUPPORT
+	u8 LocPNOInfo;
+	u8 LocScanInfo;
+	u8 LocSSIDInfo;
+	u8 LocProbePacket;
+#endif /* CONFIG_PNO_SUPPORT */
+#endif /* CONFIG_WOWLAN	 */
+	u8 LocApOffloadBCN;
+#ifdef CONFIG_P2P_WOWLAN
+	u8 LocP2PBeacon;
+	u8 LocP2PProbeRsp;
+	u8 LocNegoRsp;
+	u8 LocInviteRsp;
+	u8 LocPDRsp;
+#endif /* CONFIG_P2P_WOWLAN */
+#ifdef DBG_FW_DEBUG_MSG_PKT
+	u8 loc_fw_dbg_msg_pkt;
+#endif /*DBG_FW_DEBUG_MSG_PKT*/
+} RSVDPAGE_LOC, *PRSVDPAGE_LOC;
+
+#endif
+void dump_TX_FIFO(PADAPTER padapter, u8 page_num, u16 page_size);
+u8 rtw_hal_set_fw_media_status_cmd(_adapter *adapter, u8 mstatus, u8 macid);
+#if defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN)
+	/* WOW command function */
+	void rtw_hal_set_fw_wow_related_cmd(_adapter *padapter, u8 enable);
+	#ifdef CONFIG_P2P_WOWLAN
+		/* H2C 0x8A */
+		u8 rtw_hal_set_FwP2PRsvdPage_cmd(_adapter *adapter, PRSVDPAGE_LOC rsvdpageloc);
+		/* H2C 0x8B */
+		u8 rtw_hal_set_p2p_wowlan_offload_cmd(_adapter *adapter);
+	#endif /* CONFIG_P2P_WOWLAN */
+#endif
+
+#ifdef RTW_PER_CMD_SUPPORT_FW
+u8 rtw_hal_set_req_per_rpt_cmd(_adapter *adapter, u8 group_macid,
+			       u8 rpt_type, u32 macid_bitmap);
+#endif
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/include/hal_com_led.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/hal_com_led.h
--- linux-5.6.3/3rdparty/rtl8821ce/include/hal_com_led.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/hal_com_led.h	2020-04-10 16:35:06.846661469 +0300
@@ -0,0 +1,437 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#ifndef __HAL_COMMON_LED_H_
+#define __HAL_COMMON_LED_H_
+
+#define NO_LED 0
+#define HW_LED 1
+
+#ifdef CONFIG_RTW_LED
+#define MSECS(t)        (HZ * ((t) / 1000) + (HZ * ((t) % 1000)) / 1000)
+
+/* ********************************************************************************
+ *	LED Behavior Constant.
+ * ********************************************************************************
+ * Default LED behavior.
+ *   */
+#define LED_BLINK_NORMAL_INTERVAL	100
+#define LED_BLINK_SLOWLY_INTERVAL	200
+#define LED_BLINK_LONG_INTERVAL	400
+#define LED_INITIAL_INTERVAL		1800
+
+/* LED Customerization */
+
+/* NETTRONIX */
+#define LED_BLINK_NORMAL_INTERVAL_NETTRONIX	100
+#define LED_BLINK_SLOWLY_INTERVAL_NETTRONIX	2000
+
+/* PORNET */
+#define LED_BLINK_SLOWLY_INTERVAL_PORNET	1000
+#define LED_BLINK_NORMAL_INTERVAL_PORNET	100
+#define LED_BLINK_FAST_INTERVAL_BITLAND		30
+
+/* AzWave. */
+#define LED_CM2_BLINK_ON_INTERVAL		250
+#define LED_CM2_BLINK_OFF_INTERVAL		4750
+#define LED_CM8_BLINK_OFF_INTERVAL		3750	/* for QMI */
+
+/* RunTop */
+#define LED_RunTop_BLINK_INTERVAL		300
+
+/* ALPHA */
+#define LED_BLINK_NO_LINK_INTERVAL_ALPHA	1000
+#define LED_BLINK_NO_LINK_INTERVAL_ALPHA_500MS 500 /* add by ylb 20121012 for customer led for alpha */
+#define LED_BLINK_LINK_INTERVAL_ALPHA		500	/* 500 */
+#define LED_BLINK_SCAN_INTERVAL_ALPHA		180	/* 150 */
+#define LED_BLINK_FASTER_INTERVAL_ALPHA		50
+#define LED_BLINK_WPS_SUCESS_INTERVAL_ALPHA	5000
+
+/* 111122 by hpfan: Customized for Xavi */
+#define LED_CM11_BLINK_INTERVAL			300
+#define LED_CM11_LINK_ON_INTERVEL		3000
+
+/* Netgear */
+#define LED_BLINK_LINK_INTERVAL_NETGEAR		500
+#define LED_BLINK_LINK_SLOWLY_INTERVAL_NETGEAR		1000
+
+#define LED_WPS_BLINK_OFF_INTERVAL_NETGEAR		100
+#define LED_WPS_BLINK_ON_INTERVAL_NETGEAR		500
+
+/* Belkin AC950 */
+#define LED_BLINK_LINK_INTERVAL_ON_BELKIN		200
+#define LED_BLINK_LINK_INTERVAL_OFF_BELKIN		100
+#define LED_BLINK_ERROR_INTERVAL_BELKIN		100
+
+/* by chiyokolin for Azurewave */
+#define LED_CM12_BLINK_INTERVAL_5Mbps		160
+#define LED_CM12_BLINK_INTERVAL_10Mbps		80
+#define LED_CM12_BLINK_INTERVAL_20Mbps		50
+#define LED_CM12_BLINK_INTERVAL_40Mbps		40
+#define LED_CM12_BLINK_INTERVAL_80Mbps		30
+#define LED_CM12_BLINK_INTERVAL_MAXMbps		25
+
+/* Dlink */
+#define	LED_BLINK_NO_LINK_INTERVAL		1000
+#define	LED_BLINK_LINK_IDEL_INTERVAL		100
+
+#define	LED_BLINK_SCAN_ON_INTERVAL		30
+#define	LED_BLINK_SCAN_OFF_INTERVAL		300
+
+#define LED_WPS_BLINK_ON_INTERVAL_DLINK		30
+#define LED_WPS_BLINK_OFF_INTERVAL_DLINK			300
+#define LED_WPS_BLINK_LINKED_ON_INTERVAL_DLINK			5000
+
+/* ********************************************************************************
+ * LED object.
+ * ******************************************************************************** */
+
+typedef enum _LED_CTL_MODE {
+	LED_CTL_POWER_ON = 1,
+	LED_CTL_LINK = 2,
+	LED_CTL_NO_LINK = 3,
+	LED_CTL_TX = 4, /* unspecific data TX, including single & group addressed */
+	LED_CTL_RX = 5, /* unspecific data RX, including single & group addressed */
+	LED_CTL_UC_TX = 6, /* single addressed data TX */
+	LED_CTL_UC_RX = 7, /* single addressed data RX */
+	LED_CTL_BMC_TX = 8, /* group addressed data TX */
+	LED_CTL_BMC_RX = 9, /* group addressed data RX */
+	LED_CTL_SITE_SURVEY = 10,
+	LED_CTL_POWER_OFF = 11,
+	LED_CTL_START_TO_LINK = 12,
+	LED_CTL_START_WPS = 13,
+	LED_CTL_STOP_WPS = 14,
+	LED_CTL_START_WPS_BOTTON = 15, /* added for runtop */
+	LED_CTL_STOP_WPS_FAIL = 16, /* added for ALPHA	 */
+	LED_CTL_STOP_WPS_FAIL_OVERLAP = 17, /* added for BELKIN */
+	LED_CTL_CONNECTION_NO_TRANSFER = 18,
+} LED_CTL_MODE;
+
+typedef	enum _LED_STATE {
+	LED_UNKNOWN = 0,
+	RTW_LED_ON = 1,
+	RTW_LED_OFF = 2,
+	LED_BLINK_NORMAL = 3,
+	LED_BLINK_SLOWLY = 4,
+	LED_BLINK_POWER_ON = 5,
+	LED_BLINK_SCAN = 6,	/* LED is blinking during scanning period, the # of times to blink is depend on time for scanning. */
+	LED_BLINK_NO_LINK = 7, /* LED is blinking during no link state. */
+	LED_BLINK_StartToBlink = 8, /* Customzied for Sercomm Printer Server case */
+	LED_BLINK_TXRX = 9,
+	LED_BLINK_WPS = 10,	/* LED is blinkg during WPS communication */
+	LED_BLINK_WPS_STOP = 11,	/* for ALPHA */
+	LED_BLINK_WPS_STOP_OVERLAP = 12,	/* for BELKIN */
+	LED_BLINK_RUNTOP = 13,	/* Customized for RunTop */
+	LED_BLINK_CAMEO = 14,
+	LED_BLINK_XAVI = 15,
+	LED_BLINK_ALWAYS_ON = 16,
+	LED_BLINK_LINK_IN_PROCESS = 17,  /* Customized for Belkin AC950 */
+	LED_BLINK_AUTH_ERROR = 18,  /* Customized for Belkin AC950 */
+	LED_BLINK_Azurewave_5Mbps = 19,
+	LED_BLINK_Azurewave_10Mbps = 20,
+	LED_BLINK_Azurewave_20Mbps = 21,
+	LED_BLINK_Azurewave_40Mbps = 22,
+	LED_BLINK_Azurewave_80Mbps = 23,
+	LED_BLINK_Azurewave_MAXMbps = 24,
+	LED_BLINK_LINK_IDEL = 25,
+	LED_BLINK_WPS_LINKED = 26,
+} LED_STATE;
+
+typedef enum _LED_PIN {
+	LED_PIN_GPIO0,
+	LED_PIN_LED0,
+	LED_PIN_LED1,
+	LED_PIN_LED2
+} LED_PIN;
+
+
+/* ********************************************************************************
+ * PCIE LED Definition.
+ * ******************************************************************************** */
+#ifdef CONFIG_PCI_HCI
+typedef	enum _LED_STRATEGY_PCIE {
+	/* start from 2 */
+	SW_LED_MODE_UC_TRX_ONLY = 2,
+	SW_LED_MODE0, /* SW control 1 LED via GPIO0. It is default option. */
+	SW_LED_MODE1, /* SW control for PCI Express */
+	SW_LED_MODE2, /* SW control for Cameo. */
+	SW_LED_MODE3, /* SW contorl for RunTop. */
+	SW_LED_MODE4, /* SW control for Netcore */
+	SW_LED_MODE5, /* added by vivi, for led new mode, DLINK */
+	SW_LED_MODE6, /* added by vivi, for led new mode, PRONET */
+	SW_LED_MODE7, /* added by chiyokolin, for Lenovo, PCI Express Minicard Spec Rev.1.2 spec */
+	SW_LED_MODE8, /* added by chiyokolin, for QMI */
+	SW_LED_MODE9, /* added by chiyokolin, for BITLAND-LENOVO, PCI Express Minicard Spec Rev.1.1	 */
+	SW_LED_MODE10, /* added by chiyokolin, for Edimax-ASUS */
+	SW_LED_MODE11,	/* added by hpfan, for Xavi */
+	SW_LED_MODE12,	/* added by chiyokolin, for Azurewave */
+} LED_STRATEGY_PCIE, *PLED_STRATEGY_PCIE;
+
+typedef struct _LED_PCIE {
+	PADAPTER		padapter;
+
+	LED_PIN			LedPin;	/* Identify how to implement this SW led. */
+
+	LED_STATE		CurrLedState; /* Current LED state. */
+	BOOLEAN			bLedOn; /* TRUE if LED is ON, FALSE if LED is OFF. */
+
+	BOOLEAN			bLedBlinkInProgress; /* TRUE if it is blinking, FALSE o.w.. */
+	BOOLEAN			bLedWPSBlinkInProgress; /* TRUE if it is blinking, FALSE o.w.. */
+
+	BOOLEAN			bLedSlowBlinkInProgress;/* added by vivi, for led new mode */
+	u32				BlinkTimes; /* Number of times to toggle led state for blinking. */
+	LED_STATE		BlinkingLedState; /* Next state for blinking, either LED_ON or LED_OFF are. */
+
+	_timer			BlinkTimer; /* Timer object for led blinking. */
+} LED_PCIE, *PLED_PCIE;
+
+typedef struct _LED_PCIE	LED_DATA, *PLED_DATA;
+typedef enum _LED_STRATEGY_PCIE	LED_STRATEGY, *PLED_STRATEGY;
+
+VOID
+LedControlPCIE(
+	IN	PADAPTER		Adapter,
+	IN	LED_CTL_MODE		LedAction
+);
+
+VOID
+gen_RefreshLedState(
+	IN	PADAPTER		Adapter);
+
+/* ********************************************************************************
+ * USB  LED Definition.
+ * ******************************************************************************** */
+#elif defined(CONFIG_USB_HCI)
+
+#define IS_LED_WPS_BLINKING(_LED_USB)	(((PLED_USB)_LED_USB)->CurrLedState == LED_BLINK_WPS \
+		|| ((PLED_USB)_LED_USB)->CurrLedState == LED_BLINK_WPS_STOP \
+		|| ((PLED_USB)_LED_USB)->bLedWPSBlinkInProgress)
+
+#define IS_LED_BLINKING(_LED_USB)	(((PLED_USB)_LED_USB)->bLedWPSBlinkInProgress \
+		|| ((PLED_USB)_LED_USB)->bLedScanBlinkInProgress)
+
+
+typedef	enum _LED_STRATEGY_USB {
+	/* start from 2 */
+	SW_LED_MODE_UC_TRX_ONLY = 2,
+	SW_LED_MODE0, /* SW control 1 LED via GPIO0. It is default option. */
+	SW_LED_MODE1, /* 2 LEDs, through LED0 and LED1. For ALPHA. */
+	SW_LED_MODE2, /* SW control 1 LED via GPIO0, customized for AzWave 8187 minicard. */
+	SW_LED_MODE3, /* SW control 1 LED via GPIO0, customized for Sercomm Printer Server case. */
+	SW_LED_MODE4, /* for Edimax / Belkin */
+	SW_LED_MODE5, /* for Sercomm / Belkin	 */
+	SW_LED_MODE6,	/* for 88CU minicard, porting from ce SW_LED_MODE7 */
+	SW_LED_MODE7,	/* for Netgear special requirement */
+	SW_LED_MODE8, /* for LC */
+	SW_LED_MODE9, /* for Belkin AC950 */
+	SW_LED_MODE10, /* for Netgear A6200V2 */
+	SW_LED_MODE11, /* for Edimax / ASUS */
+	SW_LED_MODE12, /* for WNC/NEC */
+	SW_LED_MODE13, /* for Netgear A6100, 8811Au */
+	SW_LED_MODE14, /* for Buffalo, DNI, 8811Au */
+	SW_LED_MODE15, /* for DLINK,  8811Au/8812AU	 */
+} LED_STRATEGY_USB, *PLED_STRATEGY_USB;
+
+
+typedef struct _LED_USB {
+	PADAPTER			padapter;
+
+	LED_PIN				LedPin;	/* Identify how to implement this SW led. */
+
+	LED_STATE			CurrLedState; /* Current LED state. */
+	BOOLEAN				bLedOn; /* TRUE if LED is ON, FALSE if LED is OFF. */
+
+	BOOLEAN				bSWLedCtrl;
+
+	BOOLEAN				bLedBlinkInProgress; /* TRUE if it is blinking, FALSE o.w.. */
+	/* ALPHA, added by chiyoko, 20090106 */
+	BOOLEAN				bLedNoLinkBlinkInProgress;
+	BOOLEAN				bLedLinkBlinkInProgress;
+	BOOLEAN				bLedStartToLinkBlinkInProgress;
+	BOOLEAN				bLedScanBlinkInProgress;
+	BOOLEAN				bLedWPSBlinkInProgress;
+
+	u32					BlinkTimes; /* Number of times to toggle led state for blinking. */
+	u8					BlinkCounter; /* Added for turn off overlap led after blinking a while, by page, 20120821 */
+	LED_STATE			BlinkingLedState; /* Next state for blinking, either LED_ON or LED_OFF are. */
+
+	_timer				BlinkTimer; /* Timer object for led blinking. */
+
+	_workitem			BlinkWorkItem; /* Workitem used by BlinkTimer to manipulate H/W to blink LED.' */
+} LED_USB, *PLED_USB;
+
+typedef struct _LED_USB	LED_DATA, *PLED_DATA;
+typedef enum _LED_STRATEGY_USB	LED_STRATEGY, *PLED_STRATEGY;
+#ifdef CONFIG_RTW_SW_LED
+VOID
+LedControlUSB(
+	IN	PADAPTER		Adapter,
+	IN	LED_CTL_MODE		LedAction
+);
+#endif
+
+
+/* ********************************************************************************
+ * SDIO LED Definition.
+ * ******************************************************************************** */
+#elif defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
+
+#define IS_LED_WPS_BLINKING(_LED_SDIO)	(((PLED_SDIO)_LED_SDIO)->CurrLedState == LED_BLINK_WPS \
+		|| ((PLED_SDIO)_LED_SDIO)->CurrLedState == LED_BLINK_WPS_STOP \
+		|| ((PLED_SDIO)_LED_SDIO)->bLedWPSBlinkInProgress)
+
+#define IS_LED_BLINKING(_LED_SDIO)	(((PLED_SDIO)_LED_SDIO)->bLedWPSBlinkInProgress \
+		|| ((PLED_SDIO)_LED_SDIO)->bLedScanBlinkInProgress)
+
+
+typedef	enum _LED_STRATEGY_SDIO {
+	/* start from 2 */
+	SW_LED_MODE_UC_TRX_ONLY = 2,
+	SW_LED_MODE0, /* SW control 1 LED via GPIO0. It is default option. */
+	SW_LED_MODE1, /* 2 LEDs, through LED0 and LED1. For ALPHA. */
+	SW_LED_MODE2, /* SW control 1 LED via GPIO0, customized for AzWave 8187 minicard. */
+	SW_LED_MODE3, /* SW control 1 LED via GPIO0, customized for Sercomm Printer Server case. */
+	SW_LED_MODE4, /* for Edimax / Belkin */
+	SW_LED_MODE5, /* for Sercomm / Belkin	 */
+	SW_LED_MODE6,	/* for 88CU minicard, porting from ce SW_LED_MODE7 */
+} LED_STRATEGY_SDIO, *PLED_STRATEGY_SDIO;
+
+typedef struct _LED_SDIO {
+	PADAPTER			padapter;
+
+	LED_PIN				LedPin;	/* Identify how to implement this SW led. */
+
+	LED_STATE			CurrLedState; /* Current LED state. */
+	BOOLEAN				bLedOn; /* TRUE if LED is ON, FALSE if LED is OFF. */
+
+	BOOLEAN				bSWLedCtrl;
+
+	BOOLEAN				bLedBlinkInProgress; /* TRUE if it is blinking, FALSE o.w.. */
+	/* ALPHA, added by chiyoko, 20090106 */
+	BOOLEAN				bLedNoLinkBlinkInProgress;
+	BOOLEAN				bLedLinkBlinkInProgress;
+	BOOLEAN				bLedStartToLinkBlinkInProgress;
+	BOOLEAN				bLedScanBlinkInProgress;
+	BOOLEAN				bLedWPSBlinkInProgress;
+
+	u32					BlinkTimes; /* Number of times to toggle led state for blinking. */
+	LED_STATE			BlinkingLedState; /* Next state for blinking, either LED_ON or LED_OFF are. */
+
+	_timer				BlinkTimer; /* Timer object for led blinking. */
+
+	_workitem			BlinkWorkItem; /* Workitem used by BlinkTimer to manipulate H/W to blink LED. */
+} LED_SDIO, *PLED_SDIO;
+
+typedef struct _LED_SDIO	LED_DATA, *PLED_DATA;
+typedef enum _LED_STRATEGY_SDIO	LED_STRATEGY, *PLED_STRATEGY;
+
+VOID
+LedControlSDIO(
+	IN	PADAPTER		Adapter,
+	IN	LED_CTL_MODE		LedAction
+);
+
+#endif
+
+struct led_priv {
+	LED_STRATEGY		LedStrategy;
+#ifdef CONFIG_RTW_SW_LED
+	LED_DATA			SwLed0;
+	LED_DATA			SwLed1;
+	LED_DATA			SwLed2;
+	u8					bRegUseLed;
+	u8 iface_en_mask;
+	u32 ctl_en_mask[CONFIG_IFACE_NUMBER];
+	void (*LedControlHandler)(_adapter *padapter, LED_CTL_MODE LedAction);
+	void (*SwLedOn)(_adapter *padapter, PLED_DATA pLed);
+	void (*SwLedOff)(_adapter *padapter, PLED_DATA pLed);
+#endif
+};
+
+#define SwLedOn(adapter, pLed) \
+	do { \
+		if (adapter_to_led(adapter)->SwLedOn) \
+			adapter_to_led(adapter)->SwLedOn((adapter), (pLed)); \
+	} while (0)
+
+#define SwLedOff(adapter, pLed) \
+	do { \
+		if (adapter_to_led(adapter)->SwLedOff) \
+			adapter_to_led(adapter)->SwLedOff((adapter), (pLed)); \
+	} while (0)
+
+void BlinkTimerCallback(void *data);
+void BlinkWorkItemCallback(_workitem *work);
+
+void ResetLedStatus(PLED_DATA pLed);
+
+void
+InitLed(
+	_adapter			*padapter,
+	PLED_DATA		pLed,
+	LED_PIN			LedPin
+);
+
+void
+DeInitLed(
+	PLED_DATA		pLed
+);
+
+/* hal... */
+extern void BlinkHandler(PLED_DATA	pLed);
+void dump_led_config(void *sel, _adapter *adapter);
+void rtw_led_set_strategy(_adapter *adapter, u8 strategy);
+#endif /* CONFIG_RTW_LED */
+
+#if defined(CONFIG_RTW_LED)
+#define rtw_led_get_strategy(adapter) (adapter_to_led(adapter)->LedStrategy)
+#else
+#define rtw_led_get_strategy(adapter) NO_LED
+#endif
+
+#define IS_NO_LED_STRATEGY(s) ((s) == NO_LED)
+#define IS_HW_LED_STRATEGY(s) ((s) == HW_LED)
+#define IS_SW_LED_STRATEGY(s) ((s) != NO_LED && (s) != HW_LED)
+
+#if defined(CONFIG_RTW_LED) && defined(CONFIG_RTW_SW_LED)
+
+#ifndef CONFIG_RTW_SW_LED_TRX_DA_CLASSIFY
+#define CONFIG_RTW_SW_LED_TRX_DA_CLASSIFY 0
+#endif
+
+#if CONFIG_RTW_SW_LED_TRX_DA_CLASSIFY
+void rtw_sw_led_blink_uc_trx_only(LED_DATA *led);
+void rtw_sw_led_ctl_mode_uc_trx_only(_adapter *adapter, LED_CTL_MODE ctl);
+#endif
+void rtw_led_control(_adapter *adapter, LED_CTL_MODE ctl);
+void rtw_led_tx_control(_adapter *adapter, const u8 *da);
+void rtw_led_rx_control(_adapter *adapter, const u8 *da);
+void rtw_led_set_iface_en(_adapter *adapter, u8 en);
+void rtw_led_set_iface_en_mask(_adapter *adapter, u8 mask);
+void rtw_led_set_ctl_en_mask(_adapter *adapter, u32 ctl_mask);
+void rtw_led_set_ctl_en_mask_primary(_adapter *adapter);
+void rtw_led_set_ctl_en_mask_virtual(_adapter *adapter);
+#else
+#define rtw_led_control(adapter, ctl) do {} while (0)
+#define rtw_led_tx_control(adapter, da) do {} while (0)
+#define rtw_led_rx_control(adapter, da) do {} while (0)
+#define rtw_led_set_iface_en(adapter, en) do {} while (0)
+#define rtw_led_set_iface_en_mask(adapter, mask) do {} while (0)
+#define rtw_led_set_ctl_en_mask(adapter, ctl_mask) do {} while (0)
+#define rtw_led_set_ctl_en_mask_primary(adapter) do {} while (0)
+#define rtw_led_set_ctl_en_mask_virtual(adapter) do {} while (0)
+#endif /* defined(CONFIG_RTW_LED) && defined(CONFIG_RTW_SW_LED) */
+
+#endif /*__HAL_COMMON_LED_H_*/
+
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/include/hal_com_phycfg.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/hal_com_phycfg.h
--- linux-5.6.3/3rdparty/rtl8821ce/include/hal_com_phycfg.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/hal_com_phycfg.h	2020-04-10 16:35:06.846661469 +0300
@@ -0,0 +1,299 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#ifndef __HAL_COM_PHYCFG_H__
+#define __HAL_COM_PHYCFG_H__
+
+#define		PathA                     			0x0	/* Useless */
+#define		PathB			0x1
+#define		PathC			0x2
+#define		PathD			0x3
+
+typedef enum _RF_TX_NUM {
+	RF_1TX = 0,
+	RF_2TX,
+	RF_3TX,
+	RF_4TX,
+	RF_MAX_TX_NUM,
+	RF_TX_NUM_NONIMPLEMENT,
+} RF_TX_NUM;
+
+/*------------------------------Define structure----------------------------*/
+typedef struct _BB_REGISTER_DEFINITION {
+	u32 rfintfs;			/* set software control: */
+	/*		0x870~0x877[8 bytes] */
+
+	u32 rfintfo; 			/* output data: */
+	/*		0x860~0x86f [16 bytes] */
+
+	u32 rfintfe; 			/* output enable: */
+	/*		0x860~0x86f [16 bytes] */
+
+	u32 rf3wireOffset;	/* LSSI data: */
+	/*		0x840~0x84f [16 bytes] */
+
+	u32 rfHSSIPara2;	/* wire parameter control2 :  */
+	/*		0x824~0x827,0x82c~0x82f, 0x834~0x837, 0x83c~0x83f [16 bytes] */
+
+	u32 rfLSSIReadBack;	/* LSSI RF readback data SI mode */
+	/*		0x8a0~0x8af [16 bytes] */
+
+	u32 rfLSSIReadBackPi;	/* LSSI RF readback data PI mode 0x8b8-8bc for Path A and B */
+
+} BB_REGISTER_DEFINITION_T, *PBB_REGISTER_DEFINITION_T;
+
+
+/* ---------------------------------------------------------------------- */
+u8
+PHY_GetTxPowerByRateBase(
+	IN	PADAPTER		Adapter,
+	IN	u8				Band,
+	IN	u8				RfPath,
+	IN	RATE_SECTION	RateSection
+);
+
+VOID
+PHY_GetRateValuesOfTxPowerByRate(
+	IN	PADAPTER pAdapter,
+	IN	u32 RegAddr,
+	IN	u32 BitMask,
+	IN	u32 Value,
+	OUT	u8 *Rate,
+	OUT	s8 *PwrByRateVal,
+	OUT	u8 *RateNum
+);
+
+u8
+PHY_GetRateIndexOfTxPowerByRate(
+	IN	u8	Rate
+);
+
+VOID
+phy_set_tx_power_index_by_rate_section(
+	IN	PADAPTER		pAdapter,
+	IN	enum rf_path		RFPath,
+	IN	u8				Channel,
+	IN	u8				RateSection
+);
+
+s8
+_PHY_GetTxPowerByRate(
+	IN	PADAPTER	pAdapter,
+	IN	u8			Band,
+	IN	enum rf_path	RFPath,
+	IN	u8			RateIndex
+);
+
+s8
+PHY_GetTxPowerByRate(
+	IN	PADAPTER	pAdapter,
+	IN	u8			Band,
+	IN	enum rf_path	RFPath,
+	IN	u8			RateIndex
+);
+
+VOID
+PHY_SetTxPowerByRate(
+	IN	PADAPTER	pAdapter,
+	IN	u8			Band,
+	IN	enum rf_path	RFPath,
+	IN	u8			Rate,
+	IN	s8			Value
+);
+
+VOID
+phy_set_tx_power_level_by_path(
+	IN	PADAPTER	Adapter,
+	IN	u8			channel,
+	IN	u8			path
+);
+
+VOID
+PHY_SetTxPowerIndexByRateArray(
+	IN	PADAPTER		pAdapter,
+	IN	enum rf_path		RFPath,
+	IN	enum channel_width BandWidth,
+	IN	u8				Channel,
+	IN	u8				*Rates,
+	IN	u8				RateArraySize
+);
+
+VOID
+PHY_InitTxPowerByRate(
+	IN	PADAPTER	pAdapter
+);
+
+VOID
+phy_store_tx_power_by_rate(
+	IN	PADAPTER	pAdapter,
+	IN	u32			Band,
+	IN	u32			RfPath,
+	IN	u32			TxNum,
+	IN	u32			RegAddr,
+	IN	u32			BitMask,
+	IN	u32			Data
+);
+
+VOID
+PHY_TxPowerByRateConfiguration(
+	IN  PADAPTER			pAdapter
+);
+
+u8
+PHY_GetTxPowerIndexBase(
+	IN	PADAPTER		pAdapter,
+	IN	enum rf_path		RFPath,
+	IN	u8				Rate,
+	u8 ntx_idx,
+	IN	enum channel_width	BandWidth,
+	IN	u8				Channel,
+	OUT PBOOLEAN		bIn24G
+);
+
+#ifdef CONFIG_TXPWR_LIMIT
+s8 phy_get_txpwr_lmt_abs(_adapter *adapter
+	, const char *regd_name
+	, BAND_TYPE band, enum channel_width bw
+	, u8 tlrs, u8 ntx_idx, u8 cch, u8 lock
+);
+
+s8 phy_get_txpwr_lmt(_adapter *adapter
+	, const char *regd_name
+	, BAND_TYPE band, enum channel_width bw
+	, u8 rfpath, u8 rs, u8 ntx_idx, u8 cch, u8 lock
+);
+
+s8 PHY_GetTxPowerLimit(_adapter *adapter
+	, const char *regd_name
+	, BAND_TYPE band, enum channel_width bw
+	, u8 rfpath, u8 rate, u8 ntx_idx, u8 cch
+);
+#else
+#define phy_get_txpwr_lmt_abs(adapter, regd_name, band, bw, tlrs, ntx_idx, cch, lock) (GET_HAL_SPEC(adapter)->txgi_max)
+#define phy_get_txpwr_lmt(adapter, regd_name, band, bw, rfpath, rs, ntx_idx, cch, lock) (GET_HAL_SPEC(adapter)->txgi_max)
+#define PHY_GetTxPowerLimit(adapter, regd_name, band, bw, rfpath, rate, ntx_idx, cch) (GET_HAL_SPEC(adapter)->txgi_max)
+#endif /* CONFIG_TXPWR_LIMIT */
+
+s8
+PHY_GetTxPowerTrackingOffset(
+	PADAPTER	pAdapter,
+	enum rf_path	RFPath,
+	u8			Rate
+);
+
+struct txpwr_idx_comp {
+	u8 ntx_idx;
+	u8 base;
+	s8 by_rate;
+	s8 limit;
+	s8 tpt;
+	s8 ebias;
+};
+
+u8
+phy_get_tx_power_index(
+	IN	PADAPTER			pAdapter,
+	IN	enum rf_path			RFPath,
+	IN	u8					Rate,
+	IN	enum channel_width	BandWidth,
+	IN	u8					Channel
+);
+
+VOID
+PHY_SetTxPowerIndex(
+	IN	PADAPTER		pAdapter,
+	IN	u32				PowerIndex,
+	IN	enum rf_path		RFPath,
+	IN	u8				Rate
+);
+
+void dump_tx_power_idx_title(void *sel, _adapter *adapter);
+void dump_tx_power_idx_by_path_rs(void *sel, _adapter *adapter, u8 rfpath, u8 rs);
+void dump_tx_power_idx(void *sel, _adapter *adapter);
+
+bool phy_is_tx_power_limit_needed(_adapter *adapter);
+bool phy_is_tx_power_by_rate_needed(_adapter *adapter);
+int phy_load_tx_power_by_rate(_adapter *adapter, u8 chk_file);
+#ifdef CONFIG_TXPWR_LIMIT
+int phy_load_tx_power_limit(_adapter *adapter, u8 chk_file);
+#endif
+void phy_load_tx_power_ext_info(_adapter *adapter, u8 chk_file);
+void phy_reload_tx_power_ext_info(_adapter *adapter);
+void phy_reload_default_tx_power_ext_info(_adapter *adapter);
+
+const struct map_t *hal_pg_txpwr_def_info(_adapter *adapter);
+
+#ifdef CONFIG_EFUSE_CONFIG_FILE
+int check_phy_efuse_tx_power_info_valid(_adapter *adapter);
+#endif
+
+void dump_hal_txpwr_info_2g(void *sel, _adapter *adapter, u8 rfpath_num, u8 max_tx_cnt);
+void dump_hal_txpwr_info_5g(void *sel, _adapter *adapter, u8 rfpath_num, u8 max_tx_cnt);
+
+void hal_load_txpwr_info(
+	_adapter *adapter,
+	TxPowerInfo24G *pwr_info_2g,
+	TxPowerInfo5G *pwr_info_5g,
+	u8 *pg_data
+);
+
+void dump_tx_power_ext_info(void *sel, _adapter *adapter);
+void dump_target_tx_power(void *sel, _adapter *adapter);
+void dump_tx_power_by_rate(void *sel, _adapter *adapter);
+
+int rtw_get_phy_file_path(_adapter *adapter, const char *file_name);
+
+#ifdef CONFIG_LOAD_PHY_PARA_FROM_FILE
+#define MAC_FILE_FW_NIC			"FW_NIC.bin"
+#define MAC_FILE_FW_WW_IMG		"FW_WoWLAN.bin"
+#define PHY_FILE_MAC_REG		"MAC_REG.txt"
+
+#define PHY_FILE_AGC_TAB		"AGC_TAB.txt"
+#define PHY_FILE_PHY_REG		"PHY_REG.txt"
+#define PHY_FILE_PHY_REG_MP		"PHY_REG_MP.txt"
+#define PHY_FILE_PHY_REG_PG		"PHY_REG_PG.txt"
+
+#define PHY_FILE_RADIO_A		"RadioA.txt"
+#define PHY_FILE_RADIO_B		"RadioB.txt"
+#define PHY_FILE_RADIO_C		"RadioC.txt"
+#define PHY_FILE_RADIO_D		"RadioD.txt"
+#define PHY_FILE_TXPWR_TRACK	"TxPowerTrack.txt"
+#define PHY_FILE_TXPWR_LMT		"TXPWR_LMT.txt"
+
+#define PHY_FILE_WIFI_ANT_ISOLATION	"wifi_ant_isolation.txt"
+
+#define MAX_PARA_FILE_BUF_LEN	25600
+
+#define LOAD_MAC_PARA_FILE				BIT0
+#define LOAD_BB_PARA_FILE					BIT1
+#define LOAD_BB_PG_PARA_FILE				BIT2
+#define LOAD_BB_MP_PARA_FILE				BIT3
+#define LOAD_RF_PARA_FILE					BIT4
+#define LOAD_RF_TXPWR_TRACK_PARA_FILE	BIT5
+#define LOAD_RF_TXPWR_LMT_PARA_FILE		BIT6
+
+int phy_ConfigMACWithParaFile(IN PADAPTER	Adapter, IN char	*pFileName);
+int phy_ConfigBBWithParaFile(IN PADAPTER	Adapter, IN char	*pFileName, IN u32	ConfigType);
+int phy_ConfigBBWithPgParaFile(IN PADAPTER	Adapter, IN const char *pFileName);
+int phy_ConfigBBWithMpParaFile(IN PADAPTER	Adapter, IN char	*pFileName);
+int PHY_ConfigRFWithParaFile(IN	PADAPTER	Adapter, IN char	*pFileName, IN enum rf_path	eRFPath);
+int PHY_ConfigRFWithTxPwrTrackParaFile(IN PADAPTER	Adapter, IN char	*pFileName);
+#ifdef CONFIG_TXPWR_LIMIT
+int PHY_ConfigRFWithPowerLimitTableParaFile(IN PADAPTER	Adapter, IN const char *pFileName);
+#endif
+void phy_free_filebuf_mask(_adapter *padapter, u8 mask);
+void phy_free_filebuf(_adapter *padapter);
+#endif /* CONFIG_LOAD_PHY_PARA_FROM_FILE */
+u8 phy_check_under_survey_ch(_adapter *adapter);
+#endif /* __HAL_COMMON_H__ */
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/include/hal_com_reg.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/hal_com_reg.h
--- linux-5.6.3/3rdparty/rtl8821ce/include/hal_com_reg.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/hal_com_reg.h	2020-04-10 16:35:06.847661515 +0300
@@ -0,0 +1,1873 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#ifndef __HAL_COMMON_REG_H__
+#define __HAL_COMMON_REG_H__
+
+
+#define MAC_ADDR_LEN				6
+
+#define HAL_NAV_UPPER_UNIT		128		/* micro-second */
+
+/* 8188E PKT_BUFF_ACCESS_CTRL value */
+#define TXPKT_BUF_SELECT				0x69
+#define RXPKT_BUF_SELECT				0xA5
+#define DISABLE_TRXPKT_BUF_ACCESS		0x0
+
+#ifndef RTW_HALMAC
+/* ************************************************************
+*
+* ************************************************************ */
+
+/* -----------------------------------------------------
+*
+*	0x0000h ~ 0x00FFh	System Configuration
+*
+* ----------------------------------------------------- */
+#define REG_SYS_ISO_CTRL				0x0000
+#define REG_SYS_FUNC_EN				0x0002
+#define REG_APS_FSMCO					0x0004
+#define REG_SYS_CLKR					0x0008
+#define REG_SYS_CLK_CTRL				REG_SYS_CLKR
+#define REG_9346CR						0x000A
+#define REG_SYS_EEPROM_CTRL			0x000A
+#define REG_EE_VPD						0x000C
+#define REG_AFE_MISC					0x0010
+#define REG_SPS0_CTRL					0x0011
+#define REG_SPS0_CTRL_6					0x0016
+#define REG_POWER_OFF_IN_PROCESS		0x0017
+#define REG_SPS_OCP_CFG				0x0018
+#define REG_RSV_CTRL					0x001C
+#define REG_RF_CTRL						0x001F
+#define REG_LDOA15_CTRL				0x0020
+#define REG_LDOV12D_CTRL				0x0021
+#define REG_LDOHCI12_CTRL				0x0022
+#define REG_LPLDO_CTRL					0x0023
+#define REG_AFE_XTAL_CTRL				0x0024
+#define REG_AFE_LDO_CTRL				0x0027 /* 1.5v for 8188EE test chip, 1.4v for MP chip */
+#define REG_AFE_PLL_CTRL				0x0028
+#define REG_MAC_PHY_CTRL				0x002c /* for 92d, DMDP, SMSP, DMSP contrl */
+#define REG_APE_PLL_CTRL_EXT			0x002c
+#define REG_EFUSE_CTRL					0x0030
+#define REG_EFUSE_TEST					0x0034
+#define REG_PWR_DATA					0x0038
+#define REG_CAL_TIMER					0x003C
+#define REG_ACLK_MON					0x003E
+#define REG_GPIO_MUXCFG				0x0040
+#define REG_GPIO_IO_SEL					0x0042
+#define REG_MAC_PINMUX_CFG			0x0043
+#define REG_GPIO_PIN_CTRL				0x0044
+#define REG_GPIO_INTM					0x0048
+#define REG_LEDCFG0						0x004C
+#define REG_LEDCFG1						0x004D
+#define REG_LEDCFG2						0x004E
+#define REG_LEDCFG3						0x004F
+#define REG_FSIMR						0x0050
+#define REG_FSISR						0x0054
+#define REG_HSIMR						0x0058
+#define REG_HSISR						0x005c
+#define REG_GPIO_PIN_CTRL_2			0x0060 /* RTL8723 WIFI/BT/GPS Multi-Function GPIO Pin Control. */
+#define REG_GPIO_IO_SEL_2				0x0062 /* RTL8723 WIFI/BT/GPS Multi-Function GPIO Select. */
+#define REG_PAD_CTRL_1				0x0064
+#define REG_MULTI_FUNC_CTRL			0x0068 /* RTL8723 WIFI/BT/GPS Multi-Function control source. */
+#define REG_GSSR						0x006c
+#define REG_AFE_XTAL_CTRL_EXT			0x0078 /* RTL8188E */
+#define REG_XCK_OUT_CTRL				0x007c /* RTL8188E */
+#define REG_MCUFWDL					0x0080
+#define REG_WOL_EVENT					0x0081 /* RTL8188E */
+#define REG_MCUTSTCFG					0x0084
+#define REG_FDHM0						0x0088
+#define REG_HOST_SUSP_CNT				0x00BC	/* RTL8192C Host suspend counter on FPGA platform */
+#define REG_SYSTEM_ON_CTRL			0x00CC	/* For 8723AE Reset after S3 */
+#define REG_EFUSE_ACCESS				0x00CF	/* Efuse access protection for RTL8723 */
+#define REG_BIST_SCAN					0x00D0
+#define REG_BIST_RPT					0x00D4
+#define REG_BIST_ROM_RPT				0x00D8
+#define REG_USB_SIE_INTF				0x00E0
+#define REG_PCIE_MIO_INTF				0x00E4
+#define REG_PCIE_MIO_INTD				0x00E8
+#define REG_HPON_FSM					0x00EC
+#define REG_SYS_CFG						0x00F0
+#define REG_GPIO_OUTSTS				0x00F4	/* For RTL8723 only. */
+#define REG_TYPE_ID						0x00FC
+
+/*
+* 2010/12/29 MH Add for 92D
+*   */
+#define REG_MAC_PHY_CTRL_NORMAL		0x00f8
+
+
+/* -----------------------------------------------------
+*
+*	0x0100h ~ 0x01FFh	MACTOP General Configuration
+*
+* ----------------------------------------------------- */
+#define REG_CR							0x0100
+#define REG_PBP							0x0104
+#define REG_PKT_BUFF_ACCESS_CTRL		0x0106
+#define REG_TRXDMA_CTRL				0x010C
+#define REG_TRXFF_BNDY					0x0114
+#define REG_TRXFF_STATUS				0x0118
+#define REG_RXFF_PTR					0x011C
+#define REG_HIMR						0x0120
+#define REG_FE1IMR						0x0120
+#define REG_HISR							0x0124
+#define REG_HIMRE						0x0128
+#define REG_HISRE						0x012C
+#define REG_CPWM						0x012F
+#define REG_FWIMR						0x0130
+#define REG_FWISR						0x0134
+#define REG_FTIMR						0x0138
+#define REG_FTISR						0x013C /* RTL8192C */
+#define REG_PKTBUF_DBG_CTRL			0x0140
+#define REG_RXPKTBUF_CTRL				(REG_PKTBUF_DBG_CTRL+2)
+#define REG_PKTBUF_DBG_DATA_L			0x0144
+#define REG_PKTBUF_DBG_DATA_H		0x0148
+
+#define REG_TC0_CTRL					0x0150
+#define REG_TC1_CTRL					0x0154
+#define REG_TC2_CTRL					0x0158
+#define REG_TC3_CTRL					0x015C
+#define REG_TC4_CTRL					0x0160
+#define REG_TCUNIT_BASE				0x0164
+#define REG_MBIST_START				0x0174
+#define REG_MBIST_DONE					0x0178
+#define REG_MBIST_FAIL					0x017C
+#define REG_32K_CTRL					0x0194 /* RTL8188E */
+#define REG_C2HEVT_MSG_NORMAL		0x01A0
+#define REG_C2HEVT_CLEAR				0x01AF
+#define REG_MCUTST_1					0x01c0
+#define REG_MCUTST_WOWLAN			0x01C7	/* Defined after 8188E series. */
+#define REG_FMETHR						0x01C8
+#define REG_HMETFR						0x01CC
+#define REG_HMEBOX_0					0x01D0
+#define REG_HMEBOX_1					0x01D4
+#define REG_HMEBOX_2					0x01D8
+#define REG_HMEBOX_3					0x01DC
+#define REG_LLT_INIT					0x01E0
+#define REG_HMEBOX_EXT_0				0x01F0
+#define REG_HMEBOX_EXT_1				0x01F4
+#define REG_HMEBOX_EXT_2				0x01F8
+#define REG_HMEBOX_EXT_3				0x01FC
+
+
+/* -----------------------------------------------------
+*
+*	0x0200h ~ 0x027Fh	TXDMA Configuration
+*
+* ----------------------------------------------------- */
+#define REG_RQPN						0x0200
+#define REG_FIFOPAGE					0x0204
+#define REG_TDECTRL						0x0208
+#define REG_TXDMA_OFFSET_CHK			0x020C
+#define REG_TXDMA_STATUS				0x0210
+#define REG_RQPN_NPQ					0x0214
+#define REG_AUTO_LLT					0x0224
+
+
+/* -----------------------------------------------------
+*
+*	0x0280h ~ 0x02FFh	RXDMA Configuration
+*
+* ----------------------------------------------------- */
+#define REG_RXDMA_AGG_PG_TH			0x0280
+#define REG_RXPKT_NUM					0x0284
+#define REG_RXDMA_STATUS				0x0288
+
+/* -----------------------------------------------------
+*
+*	0x0300h ~ 0x03FFh	PCIe
+*
+* ----------------------------------------------------- */
+#ifndef CONFIG_TRX_BD_ARCH	/* prevent CONFIG_TRX_BD_ARCH to use old registers */
+
+#define REG_PCIE_CTRL_REG				0x0300
+#define REG_INT_MIG					0x0304	/* Interrupt Migration */
+#define REG_BCNQ_DESA					0x0308	/* TX Beacon Descriptor Address */
+#define REG_HQ_DESA					0x0310	/* TX High Queue Descriptor Address */
+#define REG_MGQ_DESA					0x0318	/* TX Manage Queue Descriptor Address */
+#define REG_VOQ_DESA					0x0320	/* TX VO Queue Descriptor Address */
+#define REG_VIQ_DESA					0x0328	/* TX VI Queue Descriptor Address */
+#define REG_BEQ_DESA					0x0330	/* TX BE Queue Descriptor Address */
+#define REG_BKQ_DESA					0x0338	/* TX BK Queue Descriptor Address */
+#define REG_RX_DESA					0x0340	/* RX Queue Descriptor Address */
+/* sherry added for DBI Read/Write  20091126 */
+#define REG_DBI_WDATA					0x0348	/*  Backdoor REG for Access Configuration */
+#define REG_DBI_RDATA					0x034C	/* Backdoor REG for Access Configuration */
+#define REG_DBI_CTRL					0x0350	/* Backdoor REG for Access Configuration */
+#define REG_DBI_FLAG					0x0352	/* Backdoor REG for Access Configuration */
+#define REG_MDIO					0x0354	/* MDIO for Access PCIE PHY */
+#define REG_DBG_SEL					0x0360	/* Debug Selection Register */
+#define REG_WATCH_DOG					0x0368
+#define REG_RX_RXBD_NUM					0x0382
+
+/* RTL8723 series ------------------------------- */
+#define REG_PCIE_HISR_EN				0x0394	/* PCIE Local Interrupt Enable Register */
+#define REG_PCIE_HISR					0x03A0
+#define REG_PCIE_HISRE					0x03A4
+#define REG_PCIE_HIMR					0x03A8
+#define REG_PCIE_HIMRE					0x03AC
+
+#endif /* !CONFIG_TRX_BD_ARCH */
+
+#define REG_USB_HIMR					0xFE38
+#define REG_USB_HIMRE					0xFE3C
+#define REG_USB_HISR					0xFE78
+#define REG_USB_HISRE					0xFE7C
+
+
+/* -----------------------------------------------------
+*
+*	0x0400h ~ 0x047Fh	Protocol Configuration
+*
+* ----------------------------------------------------- */
+
+/* 92C, 92D */
+#define REG_VOQ_INFO	0x0400
+#define REG_VIQ_INFO	0x0404
+#define REG_BEQ_INFO	0x0408
+#define REG_BKQ_INFO	0x040C
+
+/* 88E, 8723A, 8812A, 8821A, 92E, 8723B */
+#define REG_Q0_INFO	0x400
+#define REG_Q1_INFO	0x404
+#define REG_Q2_INFO	0x408
+#define REG_Q3_INFO	0x40C
+
+#define REG_MGQ_INFO	0x0410
+#define REG_HGQ_INFO	0x0414
+#define REG_BCNQ_INFO	0x0418
+#define REG_TXPKT_EMPTY				0x041A
+#define REG_CPU_MGQ_INFORMATION		0x041C
+#define REG_FWHW_TXQ_CTRL				0x0420
+#define REG_HWSEQ_CTRL					0x0423
+#define REG_BCNQ_BDNY					0x0424
+#define REG_MGQ_BDNY					0x0425
+#define REG_LIFETIME_CTRL				0x0426
+#define REG_MULTI_BCNQ_OFFSET			0x0427
+#define REG_SPEC_SIFS					0x0428
+#define REG_RETRY_LIMIT					0x042A
+#define REG_DARFRC						0x0430
+#define REG_RARFRC						0x0438
+#define REG_RRSR						0x0440
+#define REG_ARFR0						0x0444
+#define REG_ARFR1						0x0448
+#define REG_ARFR2						0x044C
+#define REG_ARFR3						0x0450
+#define REG_CCK_CHECK					0x0454
+#define REG_BCNQ1_BDNY					0x0457
+
+#define REG_AGGLEN_LMT					0x0458
+#define REG_AMPDU_MIN_SPACE			0x045C
+#define REG_WMAC_LBK_BF_HD			0x045D
+#define REG_FAST_EDCA_CTRL				0x0460
+#define REG_RD_RESP_PKT_TH				0x0463
+
+/* 8723A, 8812A, 8821A, 92E, 8723B */
+#define REG_Q4_INFO	0x468
+#define REG_Q5_INFO	0x46C
+#define REG_Q6_INFO	0x470
+#define REG_Q7_INFO	0x474
+
+#define REG_INIRTS_RATE_SEL				0x0480
+#define REG_INIDATA_RATE_SEL			0x0484
+
+/* 8723B, 92E, 8812A, 8821A*/
+#define REG_MACID_SLEEP_3				0x0484
+#define REG_MACID_SLEEP_1				0x0488
+
+#define REG_POWER_STAGE1				0x04B4
+#define REG_POWER_STAGE2				0x04B8
+#define REG_PKT_VO_VI_LIFE_TIME		0x04C0
+#define REG_PKT_BE_BK_LIFE_TIME		0x04C2
+#define REG_STBC_SETTING				0x04C4
+#define REG_QUEUE_CTRL					0x04C6
+#define REG_SINGLE_AMPDU_CTRL			0x04c7
+#define REG_PROT_MODE_CTRL			0x04C8
+#define REG_MAX_AGGR_NUM				0x04CA
+#define REG_RTS_MAX_AGGR_NUM			0x04CB
+#define REG_BAR_MODE_CTRL				0x04CC
+#define REG_RA_TRY_RATE_AGG_LMT		0x04CF
+
+/* 8723A */
+#define REG_MACID_DROP	0x04D0
+
+/* 88E */
+#define REG_EARLY_MODE_CONTROL	0x04D0
+
+/* 8723B, 92E, 8812A, 8821A */
+#define REG_MACID_SLEEP_2	0x04D0
+
+/* 8723A, 8723B, 92E, 8812A, 8821A */
+#define REG_MACID_SLEEP	0x04D4
+
+#define REG_NQOS_SEQ					0x04DC
+#define REG_HW_SEQ0						0x04D8
+#define REG_HW_SEQ1						0x04DA
+#define REG_HW_SEQ2						0x04DC
+#define REG_HW_SEQ3						0x04DE
+
+#define REG_QOS_SEQ					0x04DE
+#define REG_NEED_CPU_HANDLE			0x04E0
+#define REG_PKT_LOSE_RPT				0x04E1
+#define REG_PTCL_ERR_STATUS			0x04E2
+#define REG_TX_RPT_CTRL					0x04EC
+#define REG_TX_RPT_TIME					0x04F0	/* 2 byte */
+#define REG_DUMMY						0x04FC
+
+/* -----------------------------------------------------
+*
+*	0x0500h ~ 0x05FFh	EDCA Configuration
+*
+* ----------------------------------------------------- */
+#define REG_EDCA_VO_PARAM				0x0500
+#define REG_EDCA_VI_PARAM				0x0504
+#define REG_EDCA_BE_PARAM				0x0508
+#define REG_EDCA_BK_PARAM				0x050C
+#define REG_BCNTCFG						0x0510
+#define REG_PIFS							0x0512
+#define REG_RDG_PIFS					0x0513
+#define REG_SIFS_CTX					0x0514
+#define REG_SIFS_TRX					0x0516
+#define REG_TSFTR_SYN_OFFSET			0x0518
+#define REG_AGGR_BREAK_TIME			0x051A
+#define REG_SLOT						0x051B
+#define REG_TX_PTCL_CTRL				0x0520
+#define REG_TXPAUSE						0x0522
+#define REG_DIS_TXREQ_CLR				0x0523
+#define REG_RD_CTRL						0x0524
+/*
+* Format for offset 540h-542h:
+*	[3:0]:   TBTT prohibit setup in unit of 32us. The time for HW getting beacon content before TBTT.
+*	[7:4]:   Reserved.
+*	[19:8]:  TBTT prohibit hold in unit of 32us. The time for HW holding to send the beacon packet.
+*	[23:20]: Reserved
+* Description:
+*	              |
+*      |<--Setup--|--Hold------------>|
+*   --------------|----------------------
+*                 |
+*                TBTT
+* Note: We cannot update beacon content to HW or send any AC packets during the time between Setup and Hold.
+* Described by Designer Tim and Bruce, 2011-01-14.
+*   */
+#define REG_TBTT_PROHIBIT				0x0540
+#define REG_RD_NAV_NXT					0x0544
+#define REG_NAV_PROT_LEN				0x0546
+#define REG_BCN_CTRL					0x0550
+#define REG_BCN_CTRL_1					0x0551
+#define REG_MBID_NUM					0x0552
+#define REG_DUAL_TSF_RST				0x0553
+#define REG_MBSSID_BCN_SPACE			0x0554
+#define REG_DRVERLYINT					0x0558
+#define REG_BCNDMATIM					0x0559
+#define REG_ATIMWND					0x055A
+#define REG_USTIME_TSF					0x055C
+#define REG_BCN_MAX_ERR				0x055D
+#define REG_RXTSF_OFFSET_CCK			0x055E
+#define REG_RXTSF_OFFSET_OFDM			0x055F
+#define REG_TSFTR						0x0560
+#define REG_TSFTR1						0x0568	/* HW Port 1 TSF Register */
+#define REG_ATIMWND_1					0x0570
+#define REG_P2P_CTWIN					0x0572 /* 1 Byte long (in unit of TU) */
+#define REG_PSTIMER						0x0580
+#define REG_TIMER0						0x0584
+#define REG_TIMER1						0x0588
+#define REG_HIQ_NO_LMT_EN				0x05A7
+#define REG_ACMHWCTRL					0x05C0
+#define REG_NOA_DESC_SEL				0x05CF
+#define REG_NOA_DESC_DURATION		0x05E0
+#define REG_NOA_DESC_INTERVAL			0x05E4
+#define REG_NOA_DESC_START			0x05E8
+#define REG_NOA_DESC_COUNT			0x05EC
+
+#define REG_DMC							0x05F0	/* Dual MAC Co-Existence Register */
+#define REG_SCH_TX_CMD					0x05F8
+
+#define REG_FW_RESET_TSF_CNT_1		0x05FC
+#define REG_FW_RESET_TSF_CNT_0		0x05FD
+#define REG_FW_BCN_DIS_CNT			0x05FE
+
+/* -----------------------------------------------------
+*
+*	0x0600h ~ 0x07FFh	WMAC Configuration
+*
+* ----------------------------------------------------- */
+#define REG_APSD_CTRL					0x0600
+#define REG_BWOPMODE					0x0603
+#define REG_TCR							0x0604
+#define REG_RCR							0x0608
+#define REG_RX_PKT_LIMIT				0x060C
+#define REG_RX_DLK_TIME				0x060D
+#define REG_RX_DRVINFO_SZ				0x060F
+
+#define REG_MACID						0x0610
+#define REG_BSSID						0x0618
+#define REG_MAR							0x0620
+#define REG_MBIDCAMCFG_1				0x0628
+#define REG_MBIDCAMCFG_2				0x062C
+
+#define REG_PNO_STATUS					0x0631
+#define REG_USTIME_EDCA				0x0638
+#define REG_MAC_SPEC_SIFS				0x063A
+/* 20100719 Joseph: Hardware register definition change. (HW datasheet v54) */
+#define REG_RESP_SIFS_CCK				0x063C	/* [15:8]SIFS_R2T_OFDM, [7:0]SIFS_R2T_CCK */
+#define REG_RESP_SIFS_OFDM                    0x063E	/* [15:8]SIFS_T2T_OFDM, [7:0]SIFS_T2T_CCK */
+
+#define REG_ACKTO						0x0640
+#define REG_CTS2TO						0x0641
+#define REG_EIFS							0x0642
+
+/*REG_TCR*/
+#define BIT_PWRBIT_OW_EN BIT(7)
+
+/* RXERR_RPT */
+#define RXERR_TYPE_OFDM_PPDU			0
+#define RXERR_TYPE_OFDM_FALSE_ALARM	1
+#define RXERR_TYPE_OFDM_MPDU_OK		2
+#define RXERR_TYPE_OFDM_MPDU_FAIL	3
+#define RXERR_TYPE_CCK_PPDU			4
+#define RXERR_TYPE_CCK_FALSE_ALARM	5
+#define RXERR_TYPE_CCK_MPDU_OK		6
+#define RXERR_TYPE_CCK_MPDU_FAIL		7
+#define RXERR_TYPE_HT_PPDU				8
+#define RXERR_TYPE_HT_FALSE_ALARM	9
+#define RXERR_TYPE_HT_MPDU_TOTAL		10
+#define RXERR_TYPE_HT_MPDU_OK			11
+#define RXERR_TYPE_HT_MPDU_FAIL		12
+#define RXERR_TYPE_RX_FULL_DROP		15
+
+#define RXERR_COUNTER_MASK			0xFFFFF
+#define RXERR_RPT_RST					BIT(27)
+#define _RXERR_RPT_SEL(type)			((type) << 28)
+
+/*
+* Note:
+*	The NAV upper value is very important to WiFi 11n 5.2.3 NAV test. The default value is
+*	always too small, but the WiFi TestPlan test by 25,000 microseconds of NAV through sending
+*	CTS in the air. We must update this value greater than 25,000 microseconds to pass the item.
+*	The offset of NAV_UPPER in 8192C Spec is incorrect, and the offset should be 0x0652. Commented
+*	by SD1 Scott.
+* By Bruce, 2011-07-18.
+*   */
+#define REG_NAV_UPPER					0x0652	/* unit of 128 */
+
+/* WMA, BA, CCX */
+#define REG_NAV_CTRL					0x0650
+#define REG_BACAMCMD					0x0654
+#define REG_BACAMCONTENT				0x0658
+#define REG_LBDLY						0x0660
+#define REG_FWDLY						0x0661
+#define REG_RXERR_RPT					0x0664
+#define REG_WMAC_TRXPTCL_CTL			0x0668
+
+/* Security */
+#define REG_CAMCMD						0x0670
+#define REG_CAMWRITE					0x0674
+#define REG_CAMREAD					0x0678
+#define REG_CAMDBG						0x067C
+#define REG_SECCFG						0x0680
+
+/* Power */
+#define REG_WOW_CTRL					0x0690
+#define REG_PS_RX_INFO					0x0692
+#define REG_WMMPS_UAPSD_TID			0x0693
+#define REG_WKFMCAM_CMD				0x0698
+#define REG_WKFMCAM_NUM				REG_WKFMCAM_CMD
+#define REG_WKFMCAM_RWD				0x069C
+#define REG_RXFLTMAP0					0x06A0
+#define REG_RXFLTMAP1					0x06A2
+#define REG_RXFLTMAP2					0x06A4
+#define REG_BCN_PSR_RPT				0x06A8
+#define REG_BT_COEX_TABLE				0x06C0
+
+#define BIT_WKFCAM_WE					BIT(16)
+#define BIT_WKFCAM_POLLING_V1				BIT(31)
+#define BIT_WKFCAM_CLR_V1				BIT(30)
+#define BIT_SHIFT_WKFCAM_ADDR_V2			8
+#define BIT_MASK_WKFCAM_ADDR_V2			0xff
+#define BIT_WKFCAM_ADDR_V2(x)				(((x) & BIT_MASK_WKFCAM_ADDR_V2) << BIT_SHIFT_WKFCAM_ADDR_V2)
+
+/* Hardware Port 1 */
+#define REG_MACID1						0x0700
+#define REG_BSSID1						0x0708
+
+/* Enable/Disable Port 0 and Port 1 for Specific ICs (ex. 8192F)*/
+#define REG_WLAN_ACT_MASK_CTRL_1		0x076C
+
+/* Hardware Port 2 */
+#define REG_MACID2						0x1620
+#define REG_BSSID2						0x1628
+/* Hardware Port 3*/
+#define REG_MACID3						0x1630
+#define REG_BSSID3						0x1638
+/* Hardware Port 4 */
+#define REG_MACID4						0x1640
+#define REG_BSSID4						0x1648
+
+
+#define REG_CR_EXT						0x1100
+
+/* -----------------------------------------------------
+*
+*	0xFE00h ~ 0xFE55h	USB Configuration
+*
+* ----------------------------------------------------- */
+#define REG_USB_INFO					0xFE17
+#define REG_USB_SPECIAL_OPTION		0xFE55
+#define REG_USB_DMA_AGG_TO			0xFE5B
+#define REG_USB_AGG_TO					0xFE5C
+#define REG_USB_AGG_TH					0xFE5D
+
+#define REG_USB_HRPWM					0xFE58
+#define REG_USB_HCPWM					0xFE57
+
+/* for 92DU high_Queue low_Queue Normal_Queue select */
+#define REG_USB_High_NORMAL_Queue_Select_MAC0	0xFE44
+/* #define REG_USB_LOW_Queue_Select_MAC0		0xFE45 */
+#define REG_USB_High_NORMAL_Queue_Select_MAC1	0xFE47
+/* #define REG_USB_LOW_Queue_Select_MAC1		0xFE48 */
+
+/* For test chip */
+#define REG_TEST_USB_TXQS				0xFE48
+#define REG_TEST_SIE_VID				0xFE60		/* 0xFE60~0xFE61 */
+#define REG_TEST_SIE_PID				0xFE62		/* 0xFE62~0xFE63 */
+#define REG_TEST_SIE_OPTIONAL			0xFE64
+#define REG_TEST_SIE_CHIRP_K			0xFE65
+#define REG_TEST_SIE_PHY				0xFE66		/* 0xFE66~0xFE6B */
+#define REG_TEST_SIE_MAC_ADDR			0xFE70		/* 0xFE70~0xFE75 */
+#define REG_TEST_SIE_STRING			0xFE80		/* 0xFE80~0xFEB9 */
+
+
+/* For normal chip */
+#define REG_NORMAL_SIE_VID				0xFE60		/* 0xFE60~0xFE61 */
+#define REG_NORMAL_SIE_PID				0xFE62		/* 0xFE62~0xFE63 */
+#define REG_NORMAL_SIE_OPTIONAL		0xFE64
+#define REG_NORMAL_SIE_EP				0xFE65		/* 0xFE65~0xFE67 */
+#define REG_NORMAL_SIE_PHY			0xFE68		/* 0xFE68~0xFE6B */
+#define REG_NORMAL_SIE_OPTIONAL2		0xFE6C
+#define REG_NORMAL_SIE_GPS_EP			0xFE6D		/* 0xFE6D, for RTL8723 only. */
+#define REG_NORMAL_SIE_MAC_ADDR		0xFE70		/* 0xFE70~0xFE75 */
+#define REG_NORMAL_SIE_STRING			0xFE80		/* 0xFE80~0xFEDF */
+
+
+/* -----------------------------------------------------
+*
+*	Redifine 8192C register definition for compatibility
+*
+* ----------------------------------------------------- */
+
+/* TODO: use these definition when using REG_xxx naming rule.
+* NOTE: DO NOT Remove these definition. Use later. */
+
+#define EFUSE_CTRL				REG_EFUSE_CTRL		/* E-Fuse Control. */
+#define EFUSE_TEST				REG_EFUSE_TEST		/* E-Fuse Test. */
+#define MSR						(REG_CR + 2)		/* Media Status register */
+/* #define ISR						REG_HISR */
+#define MSR1						REG_CR_EXT
+
+#define TSFR						REG_TSFTR			/* Timing Sync Function Timer Register. */
+#define TSFR1					REG_TSFTR1			/* HW Port 1 TSF Register */
+
+#define PBP						REG_PBP
+
+/* Redifine MACID register, to compatible prior ICs. */
+#define IDR0						REG_MACID			/* MAC ID Register, Offset 0x0050-0x0053 */
+#define IDR4						(REG_MACID + 4)		/* MAC ID Register, Offset 0x0054-0x0055 */
+
+
+/*
+* 9. Security Control Registers	(Offset: )
+*   */
+#define RWCAM					REG_CAMCMD		/* IN 8190 Data Sheet is called CAMcmd */
+#define WCAMI					REG_CAMWRITE	/* Software write CAM input content */
+#define RCAMO					REG_CAMREAD		/* Software read/write CAM config */
+#define CAMDBG					REG_CAMDBG
+#define SECR						REG_SECCFG		/* Security Configuration Register */
+
+/* Unused register */
+#define UnusedRegister			0x1BF
+#define DCAM					UnusedRegister
+#define PSR						UnusedRegister
+#define BBAddr					UnusedRegister
+#define PhyDataR					UnusedRegister
+
+/* Min Spacing related settings. */
+#define MAX_MSS_DENSITY_2T			0x13
+#define MAX_MSS_DENSITY_1T			0x0A
+
+/* ----------------------------------------------------------------------------
+* 8192C Cmd9346CR bits					(Offset 0xA, 16bit)
+* ---------------------------------------------------------------------------- */
+#define CmdEEPROM_En				BIT(5)	 /* EEPROM enable when set 1 */
+#define CmdEERPOMSEL				BIT(4)	/* System EEPROM select, 0: boot from E-FUSE, 1: The EEPROM used is 9346 */
+#define Cmd9346CR_9356SEL			BIT(4)
+
+/* ----------------------------------------------------------------------------
+* 8192C GPIO MUX Configuration Register (offset 0x40, 4 byte)
+* ---------------------------------------------------------------------------- */
+#define GPIOSEL_GPIO				0
+#define GPIOSEL_ENBT				BIT(5)
+
+/* ----------------------------------------------------------------------------
+* 8192C GPIO PIN Control Register (offset 0x44, 4 byte)
+* ---------------------------------------------------------------------------- */
+#define GPIO_IN					REG_GPIO_PIN_CTRL		/* GPIO pins input value */
+#define GPIO_OUT				(REG_GPIO_PIN_CTRL+1)	/* GPIO pins output value */
+#define GPIO_IO_SEL				(REG_GPIO_PIN_CTRL+2)	/* GPIO pins output enable when a bit is set to "1"; otherwise, input is configured. */
+#define GPIO_MOD				(REG_GPIO_PIN_CTRL+3)
+
+/* ----------------------------------------------------------------------------
+* 8811A GPIO PIN Control Register (offset 0x60, 4 byte)
+* ---------------------------------------------------------------------------- */
+#define GPIO_IN_8811A			REG_GPIO_PIN_CTRL_2		/* GPIO pins input value */
+#define GPIO_OUT_8811A			(REG_GPIO_PIN_CTRL_2+1)	/* GPIO pins output value */
+#define GPIO_IO_SEL_8811A		(REG_GPIO_PIN_CTRL_2+2)	/* GPIO pins output enable when a bit is set to "1"; otherwise, input is configured. */
+#define GPIO_MOD_8811A			(REG_GPIO_PIN_CTRL_2+3)
+
+/* ----------------------------------------------------------------------------
+* 8723/8188E Host System Interrupt Mask Register (offset 0x58, 32 byte)
+* ---------------------------------------------------------------------------- */
+#define HSIMR_GPIO12_0_INT_EN			BIT(0)
+#define HSIMR_SPS_OCP_INT_EN			BIT(5)
+#define HSIMR_RON_INT_EN				BIT(6)
+#define HSIMR_PDN_INT_EN				BIT(7)
+#define HSIMR_GPIO9_INT_EN				BIT(25)
+
+/* ----------------------------------------------------------------------------
+* 8723/8188E Host System Interrupt Status Register (offset 0x5C, 32 byte)
+* ---------------------------------------------------------------------------- */
+#define HSISR_GPIO12_0_INT				BIT(0)
+#define HSISR_SPS_OCP_INT				BIT(5)
+#define HSISR_RON_INT					BIT(6)
+#define HSISR_PDNINT					BIT(7)
+#define HSISR_GPIO9_INT					BIT(25)
+
+/* ----------------------------------------------------------------------------
+* 8192C (MSR) Media Status Register	(Offset 0x4C, 8 bits)
+* ---------------------------------------------------------------------------- */
+/*
+Network Type
+00: No link
+01: Link in ad hoc network
+10: Link in infrastructure network
+11: AP mode
+Default: 00b.
+*/
+#define MSR_NOLINK				0x00
+#define MSR_ADHOC				0x01
+#define MSR_INFRA				0x02
+#define MSR_AP					0x03
+
+/* ----------------------------------------------------------------------------
+* USB INTR CONTENT
+* ---------------------------------------------------------------------------- */
+#define USB_C2H_CMDID_OFFSET					0
+#define USB_C2H_SEQ_OFFSET					1
+#define USB_C2H_EVENT_OFFSET					2
+#define USB_INTR_CPWM_OFFSET					16
+#define USB_INTR_CONTENT_C2H_OFFSET			0
+#define USB_INTR_CONTENT_CPWM1_OFFSET		16
+#define USB_INTR_CONTENT_CPWM2_OFFSET		20
+#define USB_INTR_CONTENT_HISR_OFFSET			48
+#define USB_INTR_CONTENT_HISRE_OFFSET		52
+#define USB_INTR_CONTENT_LENGTH				56
+
+/* ----------------------------------------------------------------------------
+* Response Rate Set Register	(offset 0x440, 24bits)
+* ---------------------------------------------------------------------------- */
+#define RRSR_1M					BIT(0)
+#define RRSR_2M					BIT(1)
+#define RRSR_5_5M				BIT(2)
+#define RRSR_11M				BIT(3)
+#define RRSR_6M					BIT(4)
+#define RRSR_9M					BIT(5)
+#define RRSR_12M				BIT(6)
+#define RRSR_18M				BIT(7)
+#define RRSR_24M				BIT(8)
+#define RRSR_36M				BIT(9)
+#define RRSR_48M				BIT(10)
+#define RRSR_54M				BIT(11)
+#define RRSR_MCS0				BIT(12)
+#define RRSR_MCS1				BIT(13)
+#define RRSR_MCS2				BIT(14)
+#define RRSR_MCS3				BIT(15)
+#define RRSR_MCS4				BIT(16)
+#define RRSR_MCS5				BIT(17)
+#define RRSR_MCS6				BIT(18)
+#define RRSR_MCS7				BIT(19)
+
+#define RRSR_CCK_RATES (RRSR_11M | RRSR_5_5M | RRSR_2M | RRSR_1M)
+#define RRSR_OFDM_RATES (RRSR_54M | RRSR_48M | RRSR_36M | RRSR_24M | RRSR_18M | RRSR_12M | RRSR_9M | RRSR_6M)
+
+/* WOL bit information */
+#define HAL92C_WOL_PTK_UPDATE_EVENT		BIT(0)
+#define HAL92C_WOL_GTK_UPDATE_EVENT		BIT(1)
+#define HAL92C_WOL_DISASSOC_EVENT		BIT(2)
+#define HAL92C_WOL_DEAUTH_EVENT			BIT(3)
+#define HAL92C_WOL_FW_DISCONNECT_EVENT	BIT(4)
+
+
+/*----------------------------------------------------------------------------
+**      REG_CCK_CHECK						(offset 0x454)
+------------------------------------------------------------------------------*/
+#define BIT_BCN_PORT_SEL		BIT(5)
+#define BIT_EN_BCN_PKT_REL		BIT(6)
+
+#endif /* RTW_HALMAC */
+
+/* ----------------------------------------------------------------------------
+ * Rate Definition
+ * ---------------------------------------------------------------------------- */
+/* CCK */
+#define	RATR_1M					0x00000001
+#define	RATR_2M					0x00000002
+#define	RATR_55M					0x00000004
+#define	RATR_11M					0x00000008
+/* OFDM		 */
+#define	RATR_6M					0x00000010
+#define	RATR_9M					0x00000020
+#define	RATR_12M					0x00000040
+#define	RATR_18M					0x00000080
+#define	RATR_24M					0x00000100
+#define	RATR_36M					0x00000200
+#define	RATR_48M					0x00000400
+#define	RATR_54M					0x00000800
+/* MCS 1 Spatial Stream	 */
+#define	RATR_MCS0					0x00001000
+#define	RATR_MCS1					0x00002000
+#define	RATR_MCS2					0x00004000
+#define	RATR_MCS3					0x00008000
+#define	RATR_MCS4					0x00010000
+#define	RATR_MCS5					0x00020000
+#define	RATR_MCS6					0x00040000
+#define	RATR_MCS7					0x00080000
+/* MCS 2 Spatial Stream */
+#define	RATR_MCS8					0x00100000
+#define	RATR_MCS9					0x00200000
+#define	RATR_MCS10					0x00400000
+#define	RATR_MCS11					0x00800000
+#define	RATR_MCS12					0x01000000
+#define	RATR_MCS13					0x02000000
+#define	RATR_MCS14					0x04000000
+#define	RATR_MCS15					0x08000000
+
+/* CCK */
+#define RATE_1M					BIT(0)
+#define RATE_2M					BIT(1)
+#define RATE_5_5M				BIT(2)
+#define RATE_11M				BIT(3)
+/* OFDM */
+#define RATE_6M					BIT(4)
+#define RATE_9M					BIT(5)
+#define RATE_12M				BIT(6)
+#define RATE_18M				BIT(7)
+#define RATE_24M				BIT(8)
+#define RATE_36M				BIT(9)
+#define RATE_48M				BIT(10)
+#define RATE_54M				BIT(11)
+/* MCS 1 Spatial Stream */
+#define RATE_MCS0				BIT(12)
+#define RATE_MCS1				BIT(13)
+#define RATE_MCS2				BIT(14)
+#define RATE_MCS3				BIT(15)
+#define RATE_MCS4				BIT(16)
+#define RATE_MCS5				BIT(17)
+#define RATE_MCS6				BIT(18)
+#define RATE_MCS7				BIT(19)
+/* MCS 2 Spatial Stream */
+#define RATE_MCS8				BIT(20)
+#define RATE_MCS9				BIT(21)
+#define RATE_MCS10				BIT(22)
+#define RATE_MCS11				BIT(23)
+#define RATE_MCS12				BIT(24)
+#define RATE_MCS13				BIT(25)
+#define RATE_MCS14				BIT(26)
+#define RATE_MCS15				BIT(27)
+
+
+/* ALL CCK Rate */
+#define	RATE_ALL_CCK				(RATR_1M | RATR_2M | RATR_55M | RATR_11M)
+#define	RATE_ALL_OFDM_AG			(RATR_6M | RATR_9M | RATR_12M | RATR_18M | RATR_24M|\
+	RATR_36M | RATR_48M | RATR_54M)
+#define	RATE_ALL_OFDM_1SS			(RATR_MCS0 | RATR_MCS1 | RATR_MCS2 | RATR_MCS3 |\
+	RATR_MCS4 | RATR_MCS5 | RATR_MCS6 | RATR_MCS7)
+#define	RATE_ALL_OFDM_2SS			(RATR_MCS8 | RATR_MCS9 | RATR_MCS10 | RATR_MCS11|\
+	RATR_MCS12 | RATR_MCS13 | RATR_MCS14 | RATR_MCS15)
+
+#define RATE_BITMAP_ALL			0xFFFFF
+
+/* Only use CCK 1M rate for ACK */
+#define RATE_RRSR_CCK_ONLY_1M		0xFFFF1
+#define RATE_RRSR_WITHOUT_CCK		0xFFFF0
+
+/* ----------------------------------------------------------------------------
+ * BW_OPMODE bits				(Offset 0x603, 8bit)
+ * ---------------------------------------------------------------------------- */
+#define BW_OPMODE_20MHZ			BIT(2)
+#define BW_OPMODE_5G				BIT(1)
+
+/* ----------------------------------------------------------------------------
+ * CAM Config Setting (offset 0x680, 1 byte)
+ * ----------------------------------------------------------------------------			 */
+#define CAM_VALID				BIT(15)
+#define CAM_NOTVALID			0x0000
+#define CAM_USEDK				BIT(5)
+
+#define CAM_CONTENT_COUNT	8
+
+#define CAM_NONE				0x0
+#define CAM_WEP40				0x01
+#define CAM_TKIP				0x02
+#define CAM_AES					0x04
+#define CAM_WEP104				0x05
+#define CAM_SMS4				0x6
+
+#define TOTAL_CAM_ENTRY		32
+#define HALF_CAM_ENTRY			16
+
+#define CAM_CONFIG_USEDK		_TRUE
+#define CAM_CONFIG_NO_USEDK	_FALSE
+
+#define CAM_WRITE				BIT(16)
+#define CAM_READ				0x00000000
+#define CAM_POLLINIG			BIT(31)
+
+/*
+ * 10. Power Save Control Registers
+ *   */
+#define WOW_PMEN				BIT(0) /* Power management Enable. */
+#define WOW_WOMEN				BIT(1) /* WoW function on or off. */
+#define WOW_MAGIC				BIT(2) /* Magic packet */
+#define WOW_UWF				BIT(3) /* Unicast Wakeup frame. */
+
+/*
+ * 12. Host Interrupt Status Registers
+ *
+ * ----------------------------------------------------------------------------
+ * 8190 IMR/ISR bits
+ * ---------------------------------------------------------------------------- */
+#define IMR8190_DISABLED		0x0
+#define IMR_DISABLED			0x0
+/* IMR DW0 Bit 0-31 */
+#define IMR_BCNDMAINT6			BIT(31)		/* Beacon DMA Interrupt 6 */
+#define IMR_BCNDMAINT5			BIT(30)		/* Beacon DMA Interrupt 5 */
+#define IMR_BCNDMAINT4			BIT(29)		/* Beacon DMA Interrupt 4 */
+#define IMR_BCNDMAINT3			BIT(28)		/* Beacon DMA Interrupt 3 */
+#define IMR_BCNDMAINT2			BIT(27)		/* Beacon DMA Interrupt 2 */
+#define IMR_BCNDMAINT1			BIT(26)		/* Beacon DMA Interrupt 1 */
+#define IMR_BCNDOK8				BIT(25)		/* Beacon Queue DMA OK Interrupt 8 */
+#define IMR_BCNDOK7				BIT(24)		/* Beacon Queue DMA OK Interrupt 7 */
+#define IMR_BCNDOK6				BIT(23)		/* Beacon Queue DMA OK Interrupt 6 */
+#define IMR_BCNDOK5				BIT(22)		/* Beacon Queue DMA OK Interrupt 5 */
+#define IMR_BCNDOK4				BIT(21)		/* Beacon Queue DMA OK Interrupt 4 */
+#define IMR_BCNDOK3				BIT(20)		/* Beacon Queue DMA OK Interrupt 3 */
+#define IMR_BCNDOK2				BIT(19)		/* Beacon Queue DMA OK Interrupt 2 */
+#define IMR_BCNDOK1				BIT(18)		/* Beacon Queue DMA OK Interrupt 1 */
+#define IMR_TIMEOUT2			BIT(17)		/* Timeout interrupt 2 */
+#define IMR_TIMEOUT1			BIT(16)		/* Timeout interrupt 1 */
+#define IMR_TXFOVW				BIT(15)		/* Transmit FIFO Overflow */
+#define IMR_PSTIMEOUT			BIT(14)		/* Power save time out interrupt */
+#define IMR_BcnInt				BIT(13)		/* Beacon DMA Interrupt 0 */
+#define IMR_RXFOVW				BIT(12)		/* Receive FIFO Overflow */
+#define IMR_RDU					BIT(11)		/* Receive Descriptor Unavailable */
+#define IMR_ATIMEND				BIT(10)		/* For 92C, ATIM Window End Interrupt. For 8723 and later ICs, it also means P2P CTWin End interrupt. */
+#define IMR_BDOK				BIT(9)		/* Beacon Queue DMA OK Interrupt */
+#define IMR_HIGHDOK				BIT(8)		/* High Queue DMA OK Interrupt */
+#define IMR_TBDOK				BIT(7)		/* Transmit Beacon OK interrupt */
+#define IMR_MGNTDOK			BIT(6)		/* Management Queue DMA OK Interrupt */
+#define IMR_TBDER				BIT(5)		/* For 92C, Transmit Beacon Error Interrupt */
+#define IMR_BKDOK				BIT(4)		/* AC_BK DMA OK Interrupt */
+#define IMR_BEDOK				BIT(3)		/* AC_BE DMA OK Interrupt */
+#define IMR_VIDOK				BIT(2)		/* AC_VI DMA OK Interrupt */
+#define IMR_VODOK				BIT(1)		/* AC_VO DMA Interrupt */
+#define IMR_ROK					BIT(0)		/* Receive DMA OK Interrupt */
+
+/* 13. Host Interrupt Status Extension Register	 (Offset: 0x012C-012Eh) */
+#define IMR_TSF_BIT32_TOGGLE	BIT(15)
+#define IMR_BcnInt_E				BIT(12)
+#define IMR_TXERR				BIT(11)
+#define IMR_RXERR				BIT(10)
+#define IMR_C2HCMD				BIT(9)
+#define IMR_CPWM				BIT(8)
+/* RSVD [2-7] */
+#define IMR_OCPINT				BIT(1)
+#define IMR_WLANOFF			BIT(0)
+
+/* ----------------------------------------------------------------------------
+ * 8723E series PCIE Host IMR/ISR bit
+ * ---------------------------------------------------------------------------- */
+/* IMR DW0 Bit 0-31 */
+#define PHIMR_TIMEOUT2				BIT(31)
+#define PHIMR_TIMEOUT1				BIT(30)
+#define PHIMR_PSTIMEOUT			BIT(29)
+#define PHIMR_GTINT4				BIT(28)
+#define PHIMR_GTINT3				BIT(27)
+#define PHIMR_TXBCNERR				BIT(26)
+#define PHIMR_TXBCNOK				BIT(25)
+#define PHIMR_TSF_BIT32_TOGGLE	BIT(24)
+#define PHIMR_BCNDMAINT3			BIT(23)
+#define PHIMR_BCNDMAINT2			BIT(22)
+#define PHIMR_BCNDMAINT1			BIT(21)
+#define PHIMR_BCNDMAINT0			BIT(20)
+#define PHIMR_BCNDOK3				BIT(19)
+#define PHIMR_BCNDOK2				BIT(18)
+#define PHIMR_BCNDOK1				BIT(17)
+#define PHIMR_BCNDOK0				BIT(16)
+#define PHIMR_HSISR_IND_ON			BIT(15)
+#define PHIMR_BCNDMAINT_E			BIT(14)
+#define PHIMR_ATIMEND_E			BIT(13)
+#define PHIMR_ATIM_CTW_END		BIT(12)
+#define PHIMR_HISRE_IND			BIT(11)	/* RO. HISRE Indicator (HISRE & HIMRE is true, this bit is set to 1) */
+#define PHIMR_C2HCMD				BIT(10)
+#define PHIMR_CPWM2				BIT(9)
+#define PHIMR_CPWM					BIT(8)
+#define PHIMR_HIGHDOK				BIT(7)		/* High Queue DMA OK Interrupt */
+#define PHIMR_MGNTDOK				BIT(6)		/* Management Queue DMA OK Interrupt */
+#define PHIMR_BKDOK					BIT(5)		/* AC_BK DMA OK Interrupt */
+#define PHIMR_BEDOK					BIT(4)		/* AC_BE DMA OK Interrupt */
+#define PHIMR_VIDOK					BIT(3)		/* AC_VI DMA OK Interrupt */
+#define PHIMR_VODOK				BIT(2)		/* AC_VO DMA Interrupt */
+#define PHIMR_RDU					BIT(1)		/* Receive Descriptor Unavailable */
+#define PHIMR_ROK					BIT(0)		/* Receive DMA OK Interrupt */
+
+/* PCIE Host Interrupt Status Extension bit */
+#define PHIMR_BCNDMAINT7			BIT(23)
+#define PHIMR_BCNDMAINT6			BIT(22)
+#define PHIMR_BCNDMAINT5			BIT(21)
+#define PHIMR_BCNDMAINT4			BIT(20)
+#define PHIMR_BCNDOK7				BIT(19)
+#define PHIMR_BCNDOK6				BIT(18)
+#define PHIMR_BCNDOK5				BIT(17)
+#define PHIMR_BCNDOK4				BIT(16)
+/* bit12 15: RSVD */
+#define PHIMR_TXERR					BIT(11)
+#define PHIMR_RXERR					BIT(10)
+#define PHIMR_TXFOVW				BIT(9)
+#define PHIMR_RXFOVW				BIT(8)
+/* bit2-7: RSVD */
+#define PHIMR_OCPINT				BIT(1)
+/* bit0: RSVD */
+
+#define UHIMR_TIMEOUT2				BIT(31)
+#define UHIMR_TIMEOUT1				BIT(30)
+#define UHIMR_PSTIMEOUT			BIT(29)
+#define UHIMR_GTINT4				BIT(28)
+#define UHIMR_GTINT3				BIT(27)
+#define UHIMR_TXBCNERR				BIT(26)
+#define UHIMR_TXBCNOK				BIT(25)
+#define UHIMR_TSF_BIT32_TOGGLE	BIT(24)
+#define UHIMR_BCNDMAINT3			BIT(23)
+#define UHIMR_BCNDMAINT2			BIT(22)
+#define UHIMR_BCNDMAINT1			BIT(21)
+#define UHIMR_BCNDMAINT0			BIT(20)
+#define UHIMR_BCNDOK3				BIT(19)
+#define UHIMR_BCNDOK2				BIT(18)
+#define UHIMR_BCNDOK1				BIT(17)
+#define UHIMR_BCNDOK0				BIT(16)
+#define UHIMR_HSISR_IND			BIT(15)
+#define UHIMR_BCNDMAINT_E			BIT(14)
+/* RSVD	BIT(13) */
+#define UHIMR_CTW_END				BIT(12)
+/* RSVD	BIT(11) */
+#define UHIMR_C2HCMD				BIT(10)
+#define UHIMR_CPWM2				BIT(9)
+#define UHIMR_CPWM					BIT(8)
+#define UHIMR_HIGHDOK				BIT(7)		/* High Queue DMA OK Interrupt */
+#define UHIMR_MGNTDOK				BIT(6)		/* Management Queue DMA OK Interrupt */
+#define UHIMR_BKDOK				BIT(5)		/* AC_BK DMA OK Interrupt */
+#define UHIMR_BEDOK				BIT(4)		/* AC_BE DMA OK Interrupt */
+#define UHIMR_VIDOK					BIT(3)		/* AC_VI DMA OK Interrupt */
+#define UHIMR_VODOK				BIT(2)		/* AC_VO DMA Interrupt */
+#define UHIMR_RDU					BIT(1)		/* Receive Descriptor Unavailable */
+#define UHIMR_ROK					BIT(0)		/* Receive DMA OK Interrupt */
+
+/* USB Host Interrupt Status Extension bit */
+#define UHIMR_BCNDMAINT7			BIT(23)
+#define UHIMR_BCNDMAINT6			BIT(22)
+#define UHIMR_BCNDMAINT5			BIT(21)
+#define UHIMR_BCNDMAINT4			BIT(20)
+#define UHIMR_BCNDOK7				BIT(19)
+#define UHIMR_BCNDOK6				BIT(18)
+#define UHIMR_BCNDOK5				BIT(17)
+#define UHIMR_BCNDOK4				BIT(16)
+/* bit14-15: RSVD */
+#define UHIMR_ATIMEND_E			BIT(13)
+#define UHIMR_ATIMEND				BIT(12)
+#define UHIMR_TXERR					BIT(11)
+#define UHIMR_RXERR					BIT(10)
+#define UHIMR_TXFOVW				BIT(9)
+#define UHIMR_RXFOVW				BIT(8)
+/* bit2-7: RSVD */
+#define UHIMR_OCPINT				BIT(1)
+/* bit0: RSVD */
+
+
+#define HAL_NIC_UNPLUG_ISR			0xFFFFFFFF	/* The value when the NIC is unplugged for PCI. */
+#define HAL_NIC_UNPLUG_PCI_ISR		0xEAEAEAEA	/* The value when the NIC is unplugged for PCI in PCI interrupt (page 3). */
+
+/* ----------------------------------------------------------------------------
+ * 8188 IMR/ISR bits
+ * ---------------------------------------------------------------------------- */
+#define IMR_DISABLED_88E			0x0
+/* IMR DW0(0x0060-0063) Bit 0-31 */
+#define IMR_TXCCK_88E				BIT(30)		/* TXRPT interrupt when CCX bit of the packet is set	 */
+#define IMR_PSTIMEOUT_88E			BIT(29)		/* Power Save Time Out Interrupt */
+#define IMR_GTINT4_88E				BIT(28)		/* When GTIMER4 expires, this bit is set to 1	 */
+#define IMR_GTINT3_88E				BIT(27)		/* When GTIMER3 expires, this bit is set to 1	 */
+#define IMR_TBDER_88E				BIT(26)		/* Transmit Beacon0 Error			 */
+#define IMR_TBDOK_88E				BIT(25)		/* Transmit Beacon0 OK			 */
+#define IMR_TSF_BIT32_TOGGLE_88E	BIT(24)		/* TSF Timer BIT32 toggle indication interrupt			 */
+#define IMR_BCNDMAINT0_88E		BIT(20)		/* Beacon DMA Interrupt 0			 */
+#define IMR_BCNDERR0_88E			BIT(16)		/* Beacon Queue DMA Error 0 */
+#define IMR_HSISR_IND_ON_INT_88E	BIT(15)		/* HSISR Indicator (HSIMR & HSISR is true, this bit is set to 1)			 */
+#define IMR_BCNDMAINT_E_88E		BIT(14)		/* Beacon DMA Interrupt Extension for Win7			 */
+#define IMR_ATIMEND_88E			BIT(12)		/* CTWidnow End or ATIM Window End */
+#define IMR_HISR1_IND_INT_88E		BIT(11)		/* HISR1 Indicator (HISR1 & HIMR1 is true, this bit is set to 1) */
+#define IMR_C2HCMD_88E				BIT(10)		/* CPU to Host Command INT Status, Write 1 clear	 */
+#define IMR_CPWM2_88E				BIT(9)			/* CPU power Mode exchange INT Status, Write 1 clear	 */
+#define IMR_CPWM_88E				BIT(8)			/* CPU power Mode exchange INT Status, Write 1 clear	 */
+#define IMR_HIGHDOK_88E			BIT(7)			/* High Queue DMA OK	 */
+#define IMR_MGNTDOK_88E			BIT(6)			/* Management Queue DMA OK	 */
+#define IMR_BKDOK_88E				BIT(5)			/* AC_BK DMA OK		 */
+#define IMR_BEDOK_88E				BIT(4)			/* AC_BE DMA OK	 */
+#define IMR_VIDOK_88E				BIT(3)			/* AC_VI DMA OK		 */
+#define IMR_VODOK_88E				BIT(2)			/* AC_VO DMA OK	 */
+#define IMR_RDU_88E					BIT(1)			/* Rx Descriptor Unavailable	 */
+#define IMR_ROK_88E					BIT(0)			/* Receive DMA OK */
+
+/* IMR DW1(0x00B4-00B7) Bit 0-31 */
+#define IMR_BCNDMAINT7_88E		BIT(27)		/* Beacon DMA Interrupt 7 */
+#define IMR_BCNDMAINT6_88E		BIT(26)		/* Beacon DMA Interrupt 6 */
+#define IMR_BCNDMAINT5_88E		BIT(25)		/* Beacon DMA Interrupt 5 */
+#define IMR_BCNDMAINT4_88E		BIT(24)		/* Beacon DMA Interrupt 4 */
+#define IMR_BCNDMAINT3_88E		BIT(23)		/* Beacon DMA Interrupt 3 */
+#define IMR_BCNDMAINT2_88E		BIT(22)		/* Beacon DMA Interrupt 2 */
+#define IMR_BCNDMAINT1_88E		BIT(21)		/* Beacon DMA Interrupt 1 */
+#define IMR_BCNDOK7_88E			BIT(20)		/* Beacon Queue DMA OK Interrupt 7 */
+#define IMR_BCNDOK6_88E			BIT(19)		/* Beacon Queue DMA OK Interrupt 6 */
+#define IMR_BCNDOK5_88E			BIT(18)		/* Beacon Queue DMA OK Interrupt 5 */
+#define IMR_BCNDOK4_88E			BIT(17)		/* Beacon Queue DMA OK Interrupt 4 */
+#define IMR_BCNDOK3_88E			BIT(16)		/* Beacon Queue DMA OK Interrupt 3 */
+#define IMR_BCNDOK2_88E			BIT(15)		/* Beacon Queue DMA OK Interrupt 2 */
+#define IMR_BCNDOK1_88E			BIT(14)		/* Beacon Queue DMA OK Interrupt 1 */
+#define IMR_ATIMEND_E_88E			BIT(13)		/* ATIM Window End Extension for Win7 */
+#define IMR_TXERR_88E				BIT(11)		/* Tx Error Flag Interrupt Status, write 1 clear. */
+#define IMR_RXERR_88E				BIT(10)		/* Rx Error Flag INT Status, Write 1 clear */
+#define IMR_TXFOVW_88E				BIT(9)			/* Transmit FIFO Overflow */
+#define IMR_RXFOVW_88E				BIT(8)			/* Receive FIFO Overflow */
+
+/*===================================================================
+=====================================================================
+Here the register defines are for 92C. When the define is as same with 92C,
+we will use the 92C's define for the consistency
+So the following defines for 92C is not entire!!!!!!
+=====================================================================
+=====================================================================*/
+/*
+Based on Datasheet V33---090401
+Register Summary
+Current IOREG MAP
+0x0000h ~ 0x00FFh   System Configuration (256 Bytes)
+0x0100h ~ 0x01FFh   MACTOP General Configuration (256 Bytes)
+0x0200h ~ 0x027Fh   TXDMA Configuration (128 Bytes)
+0x0280h ~ 0x02FFh   RXDMA Configuration (128 Bytes)
+0x0300h ~ 0x03FFh   PCIE EMAC Reserved Region (256 Bytes)
+0x0400h ~ 0x04FFh   Protocol Configuration (256 Bytes)
+0x0500h ~ 0x05FFh   EDCA Configuration (256 Bytes)
+0x0600h ~ 0x07FFh   WMAC Configuration (512 Bytes)
+0x2000h ~ 0x3FFFh   8051 FW Download Region (8196 Bytes)
+*/
+/* ---------------------------------------------------------------------------- */
+/*		 8192C (TXPAUSE) transmission pause 	(Offset 0x522, 8 bits) */
+/* ---------------------------------------------------------------------------- */
+/* Note:
+*	The the bits of stoping AC(VO/VI/BE/BK) queue in datasheet RTL8192S/RTL8192C are wrong,
+*	the correct arragement is VO - Bit0, VI - Bit1, BE - Bit2, and BK - Bit3.
+*	8723 and 88E may be not correct either in the eralier version. Confirmed with DD Tim.
+* By Bruce, 2011-09-22. */
+#define StopBecon		BIT(6)
+#define StopHigh			BIT(5)
+#define StopMgt			BIT(4)
+#define StopBK			BIT(3)
+#define StopBE			BIT(2)
+#define StopVI			BIT(1)
+#define StopVO			BIT(0)
+
+/* ----------------------------------------------------------------------------
+ * 8192C (RCR) Receive Configuration Register	(Offset 0x608, 32 bits)
+ * ---------------------------------------------------------------------------- */
+#define RCR_APPFCS				BIT(31)	/* WMAC append FCS after pauload */
+#define RCR_APP_MIC				BIT(30)	/* MACRX will retain the MIC at the bottom of the packet. */
+#define RCR_APP_ICV				BIT(29)	/* MACRX will retain the ICV at the bottom of the packet. */
+#define RCR_APP_PHYST_RXFF		BIT(28)	/* PHY Status is appended before RX packet in RXFF */
+#define RCR_APP_BA_SSN			BIT(27)	/* SSN of previous TXBA is appended as after original RXDESC as the 4-th DW of RXDESC. */
+#define RCR_VHT_DACK			BIT(26)	/* This bit to control response type for vht single mpdu data packet. 1. ACK as response 0. BA as response */
+#define RCR_TCPOFLD_EN			BIT(25)	/* Enable TCP checksum offload */
+#define RCR_ENMBID				BIT(24)	/* Enable Multiple BssId. Only response ACK to the packets whose DID(A1) matching to the addresses in the MBSSID CAM Entries. */
+#define RCR_LSIGEN				BIT(23)	/* Enable LSIG TXOP Protection function. Search KEYCAM for each rx packet to check if LSIGEN bit is set. */
+#define RCR_MFBEN				BIT(22)	/* Enable immediate MCS Feedback function. When Rx packet with MRQ = 1'b1, then search KEYCAM to find sender's MCS Feedback function and send response. */
+#define RCR_DISCHKPPDLLEN		BIT(21)	/* Do not check PPDU while the PPDU length is smaller than 14 byte. */
+#define RCR_PKTCTL_DLEN			BIT(20)	/* While rx path dead lock occurs, reset rx path */
+#define RCR_DISGCLK				BIT(19)	/* Disable macrx clock gating control (no used) */
+#define RCR_TIM_PARSER_EN		BIT(18)	/* RX Beacon TIM Parser. */
+#define RCR_BC_MD_EN			BIT(17)	/* Broadcast data packet more data bit check interrupt enable.*/
+#define RCR_UC_MD_EN			BIT(16)	/* Unicast data packet more data bit check interrupt enable. */
+#define RCR_RXSK_PERPKT			BIT(15)	/* Executing key search per MPDU */
+#define RCR_HTC_LOC_CTRL		BIT(14)	/* MFC<--HTC = 1 MFC-->HTC = 0 */
+#define RCR_AMF					BIT(13)	/* Accept management type frame */
+#define RCR_ACF					BIT(12)	/* Accept control type frame. Control frames BA, BAR, and PS-Poll (when in AP mode) are not controlled by this bit. They are controlled by ADF. */
+#define RCR_ADF					BIT(11)	/* Accept data type frame. This bit also regulates BA, BAR, and PS-Poll (AP mode only). */
+#define RCR_DISDECMYPKT			BIT(10)	/* This bit determines whether hw need to do decryption.1: If A1 match, do decryption.0: Do decryption. */
+#define RCR_AICV					BIT(9)		/* Accept ICV error packet */
+#define RCR_ACRC32				BIT(8)		/* Accept CRC32 error packet */
+#define RCR_CBSSID_BCN			BIT(7)		/* Accept BSSID match packet (Rx beacon, probe rsp) */
+#define RCR_CBSSID_DATA		BIT(6)		/* Accept BSSID match packet (Data) */
+#define RCR_APWRMGT			BIT(5)		/* Accept power management packet */
+#define RCR_ADD3				BIT(4)		/* Accept address 3 match packet */
+#define RCR_AB					BIT(3)		/* Accept broadcast packet */
+#define RCR_AM					BIT(2)		/* Accept multicast packet */
+#define RCR_APM					BIT(1)		/* Accept physical match packet */
+#define RCR_AAP					BIT(0)		/* Accept all unicast packet */
+
+
+/* -----------------------------------------------------
+ *
+ *	0x0000h ~ 0x00FFh	System Configuration
+ *
+ * ----------------------------------------------------- */
+
+/* 2 SYS_ISO_CTRL */
+#define ISO_MD2PP				BIT(0)
+#define ISO_UA2USB				BIT(1)
+#define ISO_UD2CORE				BIT(2)
+#define ISO_PA2PCIE				BIT(3)
+#define ISO_PD2CORE				BIT(4)
+#define ISO_IP2MAC				BIT(5)
+#define ISO_DIOP					BIT(6)
+#define ISO_DIOE					BIT(7)
+#define ISO_EB2CORE				BIT(8)
+#define ISO_DIOR					BIT(9)
+#define PWC_EV12V				BIT(15)
+
+
+/* 2 SYS_FUNC_EN */
+#define FEN_BBRSTB				BIT(0)
+#define FEN_BB_GLB_RSTn		BIT(1)
+#define FEN_USBA				BIT(2)
+#define FEN_UPLL				BIT(3)
+#define FEN_USBD				BIT(4)
+#define FEN_DIO_PCIE			BIT(5)
+#define FEN_PCIEA				BIT(6)
+#define FEN_PPLL					BIT(7)
+#define FEN_PCIED				BIT(8)
+#define FEN_DIOE				BIT(9)
+#define FEN_CPUEN				BIT(10)
+#define FEN_DCORE				BIT(11)
+#define FEN_ELDR				BIT(12)
+#define FEN_EN_25_1				BIT(13)
+#define FEN_HWPDN				BIT(14)
+#define FEN_MREGEN				BIT(15)
+
+/* 2 APS_FSMCO */
+#define PFM_LDALL				BIT(0)
+#define PFM_ALDN				BIT(1)
+#define PFM_LDKP				BIT(2)
+#define PFM_WOWL				BIT(3)
+#define EnPDN					BIT(4)
+#define PDN_PL					BIT(5)
+#define APFM_ONMAC				BIT(8)
+#define APFM_OFF				BIT(9)
+#define APFM_RSM				BIT(10)
+#define AFSM_HSUS				BIT(11)
+#define AFSM_PCIE				BIT(12)
+#define APDM_MAC				BIT(13)
+#define APDM_HOST				BIT(14)
+#define APDM_HPDN				BIT(15)
+#define RDY_MACON				BIT(16)
+#define SUS_HOST				BIT(17)
+#define ROP_ALD					BIT(20)
+#define ROP_PWR					BIT(21)
+#define ROP_SPS					BIT(22)
+#define SOP_MRST				BIT(25)
+#define SOP_FUSE				BIT(26)
+#define SOP_ABG					BIT(27)
+#define SOP_AMB					BIT(28)
+#define SOP_RCK					BIT(29)
+#define SOP_A8M					BIT(30)
+#define XOP_BTCK				BIT(31)
+
+/* 2 SYS_CLKR */
+#define ANAD16V_EN				BIT(0)
+#define ANA8M					BIT(1)
+#define MACSLP					BIT(4)
+#define LOADER_CLK_EN			BIT(5)
+
+
+/* 2 9346CR /REG_SYS_EEPROM_CTRL */
+#define BOOT_FROM_EEPROM		BIT(4)
+#define EEPROMSEL				BIT(4)
+#define EEPROM_EN				BIT(5)
+
+
+/* 2 RF_CTRL */
+#define RF_EN					BIT(0)
+#define RF_RSTB					BIT(1)
+#define RF_SDMRSTB				BIT(2)
+
+
+/* 2 LDOV12D_CTRL */
+#define LDV12_EN				BIT(0)
+#define LDV12_SDBY				BIT(1)
+#define LPLDO_HSM				BIT(2)
+#define LPLDO_LSM_DIS			BIT(3)
+#define _LDV12_VADJ(x)			(((x) & 0xF) << 4)
+
+
+
+/* 2 EFUSE_TEST (For RTL8723 partially) */
+#define EF_TRPT					BIT(7)
+#define EF_CELL_SEL				(BIT(8) | BIT(9)) /* 00: Wifi Efuse, 01: BT Efuse0, 10: BT Efuse1, 11: BT Efuse2 */
+#define LDOE25_EN				BIT(31)
+#define EFUSE_SEL(x)				(((x) & 0x3) << 8)
+#define EFUSE_SEL_MASK			0x300
+#define EFUSE_WIFI_SEL_0		0x0
+#define EFUSE_BT_SEL_0			0x1
+#define EFUSE_BT_SEL_1			0x2
+#define EFUSE_BT_SEL_2			0x3
+
+
+/* 2 8051FWDL
+ * 2 MCUFWDL */
+#define MCUFWDL_EN				BIT(0)
+#define MCUFWDL_RDY			BIT(1)
+#define FWDL_ChkSum_rpt		BIT(2)
+#define MACINI_RDY				BIT(3)
+#define BBINI_RDY				BIT(4)
+#define RFINI_RDY				BIT(5)
+#define WINTINI_RDY				BIT(6)
+#define RAM_DL_SEL				BIT(7)
+#define CPU_DL_READY			BIT(15) /* add flag  by gw for fw download ready 20130826 */
+#define ROM_DLEN				BIT(19)
+#define CPRST					BIT(23)
+
+
+/* 2 REG_SYS_CFG */
+#define XCLK_VLD				BIT(0)
+#define ACLK_VLD				BIT(1)
+#define UCLK_VLD				BIT(2)
+#define PCLK_VLD				BIT(3)
+#define PCIRSTB					BIT(4)
+#define V15_VLD					BIT(5)
+#define SW_OFFLOAD_EN			BIT(7)
+#define SIC_IDLE					BIT(8)
+#define BD_MAC2					BIT(9)
+#define BD_MAC1					BIT(10)
+#define IC_MACPHY_MODE		BIT(11)
+#define CHIP_VER				(BIT(12) | BIT(13) | BIT(14) | BIT(15))
+#define BT_FUNC					BIT(16)
+#define VENDOR_ID				BIT(19)
+#define EXT_VENDOR_ID			(BIT(18) | BIT(19)) /* Currently only for RTL8723B */
+#define PAD_HWPD_IDN			BIT(22)
+#define TRP_VAUX_EN				BIT(23)	/* RTL ID */
+#define TRP_BT_EN				BIT(24)
+#define BD_PKG_SEL				BIT(25)
+#define BD_HCI_SEL				BIT(26)
+#define TYPE_ID					BIT(27)
+#define RF_TYPE_ID				BIT(27)
+
+#define RTL_ID					BIT(23) /* TestChip ID, 1:Test(RLE); 0:MP(RL) */
+#define SPS_SEL					BIT(24) /* 1:LDO regulator mode; 0:Switching regulator mode */
+
+
+#define CHIP_VER_RTL_MASK		0xF000	/* Bit 12 ~ 15 */
+#define CHIP_VER_RTL_SHIFT		12
+#define EXT_VENDOR_ID_SHIFT	18
+
+/* 2 REG_GPIO_OUTSTS (For RTL8723 only) */
+#define EFS_HCI_SEL				(BIT(0) | BIT(1))
+#define PAD_HCI_SEL				(BIT(2) | BIT(3))
+#define HCI_SEL					(BIT(4) | BIT(5))
+#define PKG_SEL_HCI				BIT(6)
+#define FEN_GPS					BIT(7)
+#define FEN_BT					BIT(8)
+#define FEN_WL					BIT(9)
+#define FEN_PCI					BIT(10)
+#define FEN_USB					BIT(11)
+#define BTRF_HWPDN_N			BIT(12)
+#define WLRF_HWPDN_N			BIT(13)
+#define PDN_BT_N				BIT(14)
+#define PDN_GPS_N				BIT(15)
+#define BT_CTL_HWPDN			BIT(16)
+#define GPS_CTL_HWPDN			BIT(17)
+#define PPHY_SUSB				BIT(20)
+#define UPHY_SUSB				BIT(21)
+#define PCI_SUSEN				BIT(22)
+#define USB_SUSEN				BIT(23)
+#define RF_RL_ID					(BIT(31) | BIT(30) | BIT(29) | BIT(28))
+
+
+/* -----------------------------------------------------
+ *
+ *	0x0100h ~ 0x01FFh	MACTOP General Configuration
+ *
+ * ----------------------------------------------------- */
+
+/* 2 Function Enable Registers
+ * 2 CR */
+#define HCI_TXDMA_EN			BIT(0)
+#define HCI_RXDMA_EN			BIT(1)
+#define TXDMA_EN				BIT(2)
+#define RXDMA_EN				BIT(3)
+#define PROTOCOL_EN				BIT(4)
+#define SCHEDULE_EN				BIT(5)
+#define MACTXEN					BIT(6)
+#define MACRXEN					BIT(7)
+#define ENSWBCN					BIT(8)
+#define ENSEC					BIT(9)
+#define CALTMR_EN				BIT(10)	/* 32k CAL TMR enable */
+
+/* Network type */
+#define _NETTYPE(x)				(((x) & 0x3) << 16)
+#define MASK_NETTYPE			0x30000
+#define NT_NO_LINK				0x0
+#define NT_LINK_AD_HOC			0x1
+#define NT_LINK_AP				0x2
+#define NT_AS_AP				0x3
+
+/* 2 PBP - Page Size Register */
+#define GET_RX_PAGE_SIZE(value)			((value) & 0xF)
+#define GET_TX_PAGE_SIZE(value)			(((value) & 0xF0) >> 4)
+#define _PSRX_MASK				0xF
+#define _PSTX_MASK				0xF0
+#define _PSRX(x)				(x)
+#define _PSTX(x)				((x) << 4)
+
+#define PBP_64					0x0
+#define PBP_128					0x1
+#define PBP_256					0x2
+#define PBP_512					0x3
+#define PBP_1024				0x4
+
+
+/* 2 TX/RXDMA */
+#define RXDMA_ARBBW_EN		BIT(0)
+#define RXSHFT_EN				BIT(1)
+#define RXDMA_AGG_EN			BIT(2)
+#define QS_VO_QUEUE			BIT(8)
+#define QS_VI_QUEUE				BIT(9)
+#define QS_BE_QUEUE			BIT(10)
+#define QS_BK_QUEUE			BIT(11)
+#define QS_MANAGER_QUEUE		BIT(12)
+#define QS_HIGH_QUEUE			BIT(13)
+
+#define HQSEL_VOQ				BIT(0)
+#define HQSEL_VIQ				BIT(1)
+#define HQSEL_BEQ				BIT(2)
+#define HQSEL_BKQ				BIT(3)
+#define HQSEL_MGTQ				BIT(4)
+#define HQSEL_HIQ				BIT(5)
+
+/* For normal driver, 0x10C */
+#define _TXDMA_CMQ_MAP(x)			(((x) & 0x3) << 16)
+#define _TXDMA_HIQ_MAP(x)			(((x) & 0x3) << 14)
+#define _TXDMA_MGQ_MAP(x)			(((x) & 0x3) << 12)
+#define _TXDMA_BKQ_MAP(x)			(((x) & 0x3) << 10)
+#define _TXDMA_BEQ_MAP(x)			(((x) & 0x3) << 8)
+#define _TXDMA_VIQ_MAP(x)			(((x) & 0x3) << 6)
+#define _TXDMA_VOQ_MAP(x)			(((x) & 0x3) << 4)
+
+#define QUEUE_EXTRA				0
+#define QUEUE_LOW				1
+#define QUEUE_NORMAL			2
+#define QUEUE_HIGH				3
+#define QUEUE_EXTRA_1			4
+#define QUEUE_EXTRA_2			5
+
+/* 2 TRXFF_BNDY */
+
+
+/* 2 LLT_INIT */
+#define _LLT_NO_ACTIVE				0x0
+#define _LLT_WRITE_ACCESS			0x1
+#define _LLT_READ_ACCESS			0x2
+
+#define _LLT_INIT_DATA(x)			((x) & 0xFF)
+#define _LLT_INIT_ADDR(x)			(((x) & 0xFF) << 8)
+#define _LLT_OP(x)					(((x) & 0x3) << 30)
+#define _LLT_OP_VALUE(x)			(((x) >> 30) & 0x3)
+
+
+/* -----------------------------------------------------
+ *
+ *	0x0200h ~ 0x027Fh	TXDMA Configuration
+ *
+ * ----------------------------------------------------- */
+/* 2 RQPN */
+#define _HPQ(x)					((x) & 0xFF)
+#define _LPQ(x)					(((x) & 0xFF) << 8)
+#define _PUBQ(x)					(((x) & 0xFF) << 16)
+#define _NPQ(x)					((x) & 0xFF)			/* NOTE: in RQPN_NPQ register */
+#define _EPQ(x)					(((x) & 0xFF) << 16)	/* NOTE: in RQPN_EPQ register */
+
+
+#define HPQ_PUBLIC_DIS			BIT(24)
+#define LPQ_PUBLIC_DIS			BIT(25)
+#define LD_RQPN					BIT(31)
+
+
+/* 2 TDECTL */
+#define BLK_DESC_NUM_SHIFT			4
+#define BLK_DESC_NUM_MASK			0xF
+
+
+/* 2 TXDMA_OFFSET_CHK */
+#define DROP_DATA_EN				BIT(9)
+
+/* 2 AUTO_LLT */
+#define BIT_SHIFT_TXPKTNUM 24
+#define BIT_MASK_TXPKTNUM 0xff
+#define BIT_TXPKTNUM(x) (((x) & BIT_MASK_TXPKTNUM) << BIT_SHIFT_TXPKTNUM)
+
+#define BIT_TDE_DBG_SEL BIT(23)
+#define BIT_AUTO_INIT_LLT BIT(16)
+
+#define BIT_SHIFT_Tx_OQT_free_space 8
+#define BIT_MASK_Tx_OQT_free_space 0xff
+#define BIT_Tx_OQT_free_space(x) (((x) & BIT_MASK_Tx_OQT_free_space) << BIT_SHIFT_Tx_OQT_free_space)
+
+
+/* -----------------------------------------------------
+ *
+ *	0x0120h ~ 0x0123h	RX DMA Configuration
+ *
+ * ----------------------------------------------------- */
+#define BIT_FS_RXDONE_INT_EN				BIT(16)
+
+
+/* REG_RXPKT_NUM				(Offset 0x0284) */
+#define BIT_RW_RELEASE_EN				BIT(18)
+
+/* -----------------------------------------------------
+ *
+ *	0x0280h ~ 0x028Bh	RX DMA Configuration
+ *
+ * ----------------------------------------------------- */
+
+/* 2 REG_RXDMA_CONTROL, 0x0286h
+ * Write only. When this bit is set, RXDMA will decrease RX PKT counter by one. Before
+ * this bit is polled, FW shall update RXFF_RD_PTR first. This register is write pulse and auto clear.
+ * #define RXPKT_RELEASE_POLL			BIT(0)
+ * Read only. When RXMA finishes on-going DMA operation, RXMDA will report idle state in
+ * this bit. FW can start releasing packets after RXDMA entering idle mode.
+ * #define RXDMA_IDLE					BIT(1)
+ * When this bit is set, RXDMA will enter this mode after on-going RXDMA packet to host
+ * completed, and stop DMA packet to host. RXDMA will then report Default: 0;
+ * #define RW_RELEASE_EN				BIT(2) */
+
+/* 2 REG_RXPKT_NUM, 0x0284 */
+#define	RXPKT_RELEASE_POLL	BIT(16)
+#define	RXDMA_IDLE				BIT(17)
+#define	RW_RELEASE_EN			BIT(18)
+
+/* -----------------------------------------------------
+ *
+ *	0x0400h ~ 0x047Fh	Protocol Configuration
+ *
+ * ----------------------------------------------------- */
+/* 2 FWHW_TXQ_CTRL */
+#define EN_AMPDU_RTY_NEW			BIT(7)
+
+
+/* 2 SPEC SIFS */
+#define _SPEC_SIFS_CCK(x)			((x) & 0xFF)
+#define _SPEC_SIFS_OFDM(x)			(((x) & 0xFF) << 8)
+
+/* 2 RL */
+#define BIT_SHIFT_SRL 8
+#define BIT_MASK_SRL 0x3f
+#define BIT_SRL(x) (((x) & BIT_MASK_SRL) << BIT_SHIFT_SRL)
+
+#define BIT_SHIFT_LRL 0
+#define BIT_MASK_LRL 0x3f
+#define BIT_LRL(x) (((x) & BIT_MASK_LRL) << BIT_SHIFT_LRL)
+
+#define	RL_VAL_AP					7
+#ifdef CONFIG_RTW_CUSTOMIZE_RLSTA
+#define	RL_VAL_STA					CONFIG_RTW_CUSTOMIZE_RLSTA
+#else
+#define	RL_VAL_STA					0x30
+#endif
+/* -----------------------------------------------------
+ *
+ *	0x0500h ~ 0x05FFh	EDCA Configuration
+ *
+ * ----------------------------------------------------- */
+
+/* 2 EDCA setting */
+#define AC_PARAM_TXOP_LIMIT_OFFSET		16
+#define AC_PARAM_ECW_MAX_OFFSET			12
+#define AC_PARAM_ECW_MIN_OFFSET			8
+#define AC_PARAM_AIFS_OFFSET				0
+
+/* 2 BCN_CTRL */
+#define EN_TXBCN_RPT			BIT(2)
+#define EN_BCN_FUNCTION		BIT(3)
+#define STOP_BCNQ				BIT(6)
+#define DIS_RX_BSSID_FIT		BIT(6)
+
+#define DIS_ATIM					BIT(0)
+#define DIS_BCNQ_SUB			BIT(1)
+#define DIS_TSF_UDT				BIT(4)
+
+/* 2 ACMHWCTRL */
+#define AcmHw_HwEn				BIT(0)
+#define AcmHw_VoqEn			BIT(1)
+#define AcmHw_ViqEn				BIT(2)
+#define AcmHw_BeqEn			BIT(3)
+#define AcmHw_VoqStatus		BIT(5)
+#define AcmHw_ViqStatus			BIT(6)
+#define AcmHw_BeqStatus		BIT(7)
+
+/* 2 */ /* REG_DUAL_TSF_RST (0x553) */
+#define DUAL_TSF_RST_P2P		BIT(4)
+
+/* 2 */ /* REG_NOA_DESC_SEL (0x5CF) */
+#define NOA_DESC_SEL_0			0
+#define NOA_DESC_SEL_1			BIT(4)
+
+/* -----------------------------------------------------
+ *
+ *	0x0600h ~ 0x07FFh	WMAC Configuration
+ *
+ * ----------------------------------------------------- */
+
+/* 2 APSD_CTRL */
+#define APSDOFF					BIT(6)
+
+/* 2 TCR */
+#define TSFRST					BIT(0)
+#define DIS_GCLK					BIT(1)
+#define PAD_SEL					BIT(2)
+#define PWR_ST					BIT(6)
+#define PWRBIT_OW_EN			BIT(7)
+#define ACRC						BIT(8)
+#define CFENDFORM				BIT(9)
+#define ICV						BIT(10)
+
+
+/* 2 RCR */
+#define AAP						BIT(0)
+#define APM						BIT(1)
+#define AM						BIT(2)
+#define AB						BIT(3)
+#define ADD3						BIT(4)
+#define APWRMGT				BIT(5)
+#define CBSSID					BIT(6)
+#define CBSSID_DATA				BIT(6)
+#define CBSSID_BCN				BIT(7)
+#define ACRC32					BIT(8)
+#define AICV						BIT(9)
+#define ADF						BIT(11)
+#define ACF						BIT(12)
+#define AMF						BIT(13)
+#define HTC_LOC_CTRL			BIT(14)
+#define UC_DATA_EN				BIT(16)
+#define BM_DATA_EN				BIT(17)
+#define MFBEN					BIT(22)
+#define LSIGEN					BIT(23)
+#define EnMBID					BIT(24)
+#define FORCEACK				BIT(26)
+#define APP_BASSN				BIT(27)
+#define APP_PHYSTS				BIT(28)
+#define APP_ICV					BIT(29)
+#define APP_MIC					BIT(30)
+#define APP_FCS					BIT(31)
+
+
+/* 2 SECCFG */
+#define SCR_TxUseDK				BIT(0)			/* Force Tx Use Default Key */
+#define SCR_RxUseDK				BIT(1)			/* Force Rx Use Default Key */
+#define SCR_TxEncEnable			BIT(2)			/* Enable Tx Encryption */
+#define SCR_RxDecEnable			BIT(3)			/* Enable Rx Decryption */
+#define SCR_SKByA2				BIT(4)			/* Search kEY BY A2 */
+#define SCR_NoSKMC				BIT(5)			/* No Key Search Multicast */
+#define SCR_TXBCUSEDK			BIT(6)			/* Force Tx Broadcast packets Use Default Key */
+#define SCR_RXBCUSEDK			BIT(7)			/* Force Rx Broadcast packets Use Default Key */
+#define SCR_CHK_KEYID			BIT(8)
+#define SCR_CHK_BMC				BIT(9)			/* add option to support a2+keyid+bcm */
+
+/*REG_MBIDCAMCFG           (Offset 0x0628/0x62C)*/
+#define BIT_MBIDCAM_POLL		BIT(31)
+#define BIT_MBIDCAM_WT_EN		BIT(30)
+
+#define MBIDCAM_ADDR_MASK		0x1F
+#define MBIDCAM_ADDR_SHIFT		24
+
+#define BIT_MBIDCAM_VALID		BIT(23)
+#define BIT_LSIC_TXOP_EN		BIT(17)
+#define BIT_CTS_EN				BIT(16)
+
+/*REG_RXFLTMAP1 (Offset 0x6A2)*/
+#define BIT_CTRLFLT10EN	BIT(10) /*PS-POLL*/
+
+/*REG_WLAN_ACT_MASK_CTRL_1	(Offset 0x76C)*/
+#define EN_PORT_0_FUNCTION		BIT(12)
+#define EN_PORT_1_FUNCTION		BIT(13)
+
+/* -----------------------------------------------------
+ *
+ *	SDIO Bus Specification
+ *
+ * ----------------------------------------------------- */
+
+/* I/O bus domain address mapping */
+#define SDIO_LOCAL_BASE		0x10250000
+#define WLAN_IOREG_BASE		0x10260000
+#define FIRMWARE_FIFO_BASE	0x10270000
+#define TX_HIQ_BASE				0x10310000
+#define TX_MIQ_BASE				0x10320000
+#define TX_LOQ_BASE				0x10330000
+#define TX_EPQ_BASE				0x10350000
+#define RX_RX0FF_BASE			0x10340000
+
+/* SDIO host local register space mapping. */
+#define SDIO_LOCAL_MSK				0x0FFF
+#define WLAN_IOREG_MSK		0x7FFF
+#define WLAN_FIFO_MSK			      	0x1FFF	/* Aggregation Length[12:0] */
+#define WLAN_RX0FF_MSK				0x0003
+
+#define SDIO_WITHOUT_REF_DEVICE_ID	0	/* Without reference to the SDIO Device ID */
+#define SDIO_LOCAL_DEVICE_ID           		0	/* 0b[16], 000b[15:13] */
+#define WLAN_TX_HIQ_DEVICE_ID			4	/* 0b[16], 100b[15:13] */
+#define WLAN_TX_MIQ_DEVICE_ID 		5	/* 0b[16], 101b[15:13] */
+#define WLAN_TX_LOQ_DEVICE_ID 		6	/* 0b[16], 110b[15:13] */
+#define WLAN_TX_EXQ_DEVICE_ID		3	/* 0b[16], 011b[15:13] */
+#define WLAN_RX0FF_DEVICE_ID 			7	/* 0b[16], 111b[15:13] */
+#define WLAN_IOREG_DEVICE_ID 			8	/* 1b[16] */
+
+/* SDIO Tx Free Page Index */
+#define HI_QUEUE_IDX			0
+#define MID_QUEUE_IDX			1
+#define LOW_QUEUE_IDX				2
+#define PUBLIC_QUEUE_IDX			3
+
+#define SDIO_MAX_TX_QUEUE			3		/* HIQ, MIQ and LOQ */
+#define SDIO_MAX_RX_QUEUE			1
+
+#define SDIO_REG_TX_CTRL			0x0000 /* SDIO Tx Control */
+#define SDIO_REG_TIMEOUT			0x0002/*SDIO status timeout*/
+#define SDIO_REG_HIMR				0x0014 /* SDIO Host Interrupt Mask */
+#define SDIO_REG_HISR				0x0018 /* SDIO Host Interrupt Service Routine */
+#define SDIO_REG_HCPWM			0x0019 /* HCI Current Power Mode */
+#define SDIO_REG_RX0_REQ_LEN		0x001C /* RXDMA Request Length */
+#define SDIO_REG_OQT_FREE_PG		0x001E /* OQT Free Page */
+#define SDIO_REG_FREE_TXPG			0x0020 /* Free Tx Buffer Page */
+#define SDIO_REG_HCPWM1			0x0024 /* HCI Current Power Mode 1 */
+#define SDIO_REG_HCPWM2			0x0026 /* HCI Current Power Mode 2 */
+#define SDIO_REG_FREE_TXPG_SEQ	0x0028 /* Free Tx Page Sequence */
+#define SDIO_REG_HTSFR_INFO		0x0030 /* HTSF Informaion */
+#define SDIO_REG_HRPWM1			0x0080 /* HCI Request Power Mode 1 */
+#define SDIO_REG_HRPWM2			0x0082 /* HCI Request Power Mode 2 */
+#define SDIO_REG_HPS_CLKR			0x0084 /* HCI Power Save Clock */
+#define SDIO_REG_HSUS_CTRL			0x0086 /* SDIO HCI Suspend Control */
+#define SDIO_REG_HIMR_ON			0x0090 /* SDIO Host Extension Interrupt Mask Always */
+#define SDIO_REG_HISR_ON			0x0091 /* SDIO Host Extension Interrupt Status Always */
+
+#define SDIO_HIMR_DISABLED			0
+
+/* RTL8723/RTL8188E SDIO Host Interrupt Mask Register */
+#define SDIO_HIMR_RX_REQUEST_MSK		BIT(0)
+#define SDIO_HIMR_AVAL_MSK			BIT(1)
+#define SDIO_HIMR_TXERR_MSK			BIT(2)
+#define SDIO_HIMR_RXERR_MSK			BIT(3)
+#define SDIO_HIMR_TXFOVW_MSK			BIT(4)
+#define SDIO_HIMR_RXFOVW_MSK			BIT(5)
+#define SDIO_HIMR_TXBCNOK_MSK			BIT(6)
+#define SDIO_HIMR_TXBCNERR_MSK		BIT(7)
+#define SDIO_HIMR_BCNERLY_INT_MSK		BIT(16)
+#define SDIO_HIMR_C2HCMD_MSK			BIT(17)
+#define SDIO_HIMR_CPWM1_MSK			BIT(18)
+#define SDIO_HIMR_CPWM2_MSK			BIT(19)
+#define SDIO_HIMR_HSISR_IND_MSK		BIT(20)
+#define SDIO_HIMR_GTINT3_IND_MSK		BIT(21)
+#define SDIO_HIMR_GTINT4_IND_MSK		BIT(22)
+#define SDIO_HIMR_PSTIMEOUT_MSK		BIT(23)
+#define SDIO_HIMR_OCPINT_MSK			BIT(24)
+#define SDIO_HIMR_ATIMEND_MSK			BIT(25)
+#define SDIO_HIMR_ATIMEND_E_MSK		BIT(26)
+#define SDIO_HIMR_CTWEND_MSK			BIT(27)
+
+/* RTL8188E SDIO Specific */
+#define SDIO_HIMR_MCU_ERR_MSK			BIT(28)
+#define SDIO_HIMR_TSF_BIT32_TOGGLE_MSK		BIT(29)
+
+/* SDIO Host Interrupt Service Routine */
+#define SDIO_HISR_RX_REQUEST			BIT(0)
+#define SDIO_HISR_AVAL					BIT(1)
+#define SDIO_HISR_TXERR					BIT(2)
+#define SDIO_HISR_RXERR					BIT(3)
+#define SDIO_HISR_TXFOVW				BIT(4)
+#define SDIO_HISR_RXFOVW				BIT(5)
+#define SDIO_HISR_TXBCNOK				BIT(6)
+#define SDIO_HISR_TXBCNERR				BIT(7)
+#define SDIO_HISR_BCNERLY_INT			BIT(16)
+#define SDIO_HISR_C2HCMD				BIT(17)
+#define SDIO_HISR_CPWM1				BIT(18)
+#define SDIO_HISR_CPWM2				BIT(19)
+#define SDIO_HISR_HSISR_IND			BIT(20)
+#define SDIO_HISR_GTINT3_IND			BIT(21)
+#define SDIO_HISR_GTINT4_IND			BIT(22)
+#define SDIO_HISR_PSTIMEOUT			BIT(23)
+#define SDIO_HISR_OCPINT				BIT(24)
+#define SDIO_HISR_ATIMEND				BIT(25)
+#define SDIO_HISR_ATIMEND_E			BIT(26)
+#define SDIO_HISR_CTWEND				BIT(27)
+
+/* RTL8188E SDIO Specific */
+#define SDIO_HISR_MCU_ERR				BIT(28)
+#define SDIO_HISR_TSF_BIT32_TOGGLE	BIT(29)
+
+#define MASK_SDIO_HISR_CLEAR		(SDIO_HISR_TXERR |\
+		SDIO_HISR_RXERR |\
+		SDIO_HISR_TXFOVW |\
+		SDIO_HISR_RXFOVW |\
+		SDIO_HISR_TXBCNOK |\
+		SDIO_HISR_TXBCNERR |\
+		SDIO_HISR_C2HCMD |\
+		SDIO_HISR_CPWM1 |\
+		SDIO_HISR_CPWM2 |\
+		SDIO_HISR_HSISR_IND |\
+		SDIO_HISR_GTINT3_IND |\
+		SDIO_HISR_GTINT4_IND |\
+		SDIO_HISR_PSTIMEOUT |\
+		SDIO_HISR_OCPINT)
+
+/* SDIO HCI Suspend Control Register */
+#define HCI_RESUME_PWR_RDY			BIT(1)
+#define HCI_SUS_CTRL					BIT(0)
+
+/* SDIO Tx FIFO related */
+#define SDIO_TX_FREE_PG_QUEUE			4	/* The number of Tx FIFO free page */
+#define SDIO_TX_FIFO_PAGE_SZ			128
+
+/* indirect access */
+#ifdef CONFIG_SDIO_INDIRECT_ACCESS
+#define SDIO_REG_INDIRECT_REG_CFG		0x40
+#define SDIO_REG_INDIRECT_REG_DATA	0x44
+#define SET_INDIRECT_REG_ADDR(_cmd, _addr)	SET_BITS_TO_LE_2BYTE(((u8 *)(_cmd)) + 0, 0, 16, (_addr))
+#define SET_INDIRECT_REG_SIZE_1BYTE(_cmd)		SET_BITS_TO_LE_1BYTE(((u8 *)(_cmd)) + 2, 0, 2, 0)
+#define SET_INDIRECT_REG_SIZE_2BYTE(_cmd)		SET_BITS_TO_LE_1BYTE(((u8 *)(_cmd)) + 2, 0, 2, 1)
+#define SET_INDIRECT_REG_SIZE_4BYTE(_cmd)		SET_BITS_TO_LE_1BYTE(((u8 *)(_cmd)) + 2, 0, 2, 2)
+#define SET_INDIRECT_REG_WRITE(_cmd)			SET_BITS_TO_LE_1BYTE(((u8 *)(_cmd)) + 2, 2, 1, 1)
+#define SET_INDIRECT_REG_READ(_cmd)			SET_BITS_TO_LE_1BYTE(((u8 *)(_cmd)) + 2, 3, 1, 1)
+#define GET_INDIRECT_REG_RDY(_cmd)			LE_BITS_TO_1BYTE(((u8 *)(_cmd)) + 2, 4, 1)
+#endif/*CONFIG_SDIO_INDIRECT_ACCESS*/
+
+#ifdef CONFIG_SDIO_HCI
+	#define MAX_TX_AGG_PACKET_NUMBER	0x8
+#else
+	#define MAX_TX_AGG_PACKET_NUMBER	0xFF
+	#define MAX_TX_AGG_PACKET_NUMBER_8812	64
+#endif
+
+/* -----------------------------------------------------
+ *
+ *	0xFE00h ~ 0xFE55h	USB Configuration
+ *
+ * ----------------------------------------------------- */
+
+/* 2 USB Information (0xFE17) */
+#define USB_IS_HIGH_SPEED			0
+#define USB_IS_FULL_SPEED			1
+#define USB_SPEED_MASK				BIT(5)
+
+#define USB_NORMAL_SIE_EP_MASK	0xF
+#define USB_NORMAL_SIE_EP_SHIFT	4
+
+/* 2 Special Option */
+#define USB_AGG_EN				BIT(3)
+
+/* 0; Use interrupt endpoint to upload interrupt pkt
+ * 1; Use bulk endpoint to upload interrupt pkt, */
+#define INT_BULK_SEL			BIT(4)
+
+/* 2REG_C2HEVT_CLEAR */
+#define C2H_EVT_HOST_CLOSE		0x00	/* Set by driver and notify FW that the driver has read the C2H command message */
+#define C2H_EVT_FW_CLOSE		0xFF	/* Set by FW indicating that FW had set the C2H command message and it's not yet read by driver. */
+
+
+/* 2REG_MULTI_FUNC_CTRL(For RTL8723 Only) */
+#define WL_HWPDN_EN			BIT(0)	/* Enable GPIO[9] as WiFi HW PDn source */
+#define WL_HWPDN_SL			BIT(1)	/* WiFi HW PDn polarity control */
+#define WL_FUNC_EN				BIT(2)	/* WiFi function enable */
+#define WL_HWROF_EN			BIT(3)	/* Enable GPIO[9] as WiFi RF HW PDn source */
+#define BT_HWPDN_EN			BIT(16)	/* Enable GPIO[11] as BT HW PDn source */
+#define BT_HWPDN_SL			BIT(17)	/* BT HW PDn polarity control */
+#define BT_FUNC_EN				BIT(18)	/* BT function enable */
+#define BT_HWROF_EN			BIT(19)	/* Enable GPIO[11] as BT/GPS RF HW PDn source */
+#define GPS_HWPDN_EN			BIT(20)	/* Enable GPIO[10] as GPS HW PDn source */
+#define GPS_HWPDN_SL			BIT(21)	/* GPS HW PDn polarity control */
+#define GPS_FUNC_EN			BIT(22)	/* GPS function enable */
+
+/* 3 REG_LIFECTRL_CTRL */
+#define HAL92C_EN_PKT_LIFE_TIME_BK		BIT(3)
+#define HAL92C_EN_PKT_LIFE_TIME_BE		BIT(2)
+#define HAL92C_EN_PKT_LIFE_TIME_VI		BIT(1)
+#define HAL92C_EN_PKT_LIFE_TIME_VO		BIT(0)
+
+#define HAL92C_MSDU_LIFE_TIME_UNIT		128	/* in us, said by Tim. */
+
+/* 2 8192D PartNo. */
+#define PARTNO_92D_NIC							(BIT7 | BIT6)
+#define PARTNO_92D_NIC_REMARK				(BIT5 | BIT4)
+#define PARTNO_SINGLE_BAND_VS				BIT(3)
+#define PARTNO_SINGLE_BAND_VS_REMARK		BIT(1)
+#define PARTNO_CONCURRENT_BAND_VC			(BIT3 | BIT2)
+#define PARTNO_CONCURRENT_BAND_VC_REMARK	(BIT1 | BIT0)
+
+/* ********************************************************
+ * General definitions
+ * ******************************************************** */
+
+#ifdef CONFIG_USB_HCI
+	#define LAST_ENTRY_OF_TX_PKT_BUFFER_8188E(__Adapter)	(175)
+#else
+	#define LAST_ENTRY_OF_TX_PKT_BUFFER_8188E(__Adapter)	(IS_VENDOR_8188E_I_CUT_SERIES(__Adapter) ? 255 : 175)
+#endif
+#define LAST_ENTRY_OF_TX_PKT_BUFFER_8812			255
+#define LAST_ENTRY_OF_TX_PKT_BUFFER_8723B		255
+#define LAST_ENTRY_OF_TX_PKT_BUFFER_8192C		255
+#define LAST_ENTRY_OF_TX_PKT_BUFFER_8703B		255
+#define LAST_ENTRY_OF_TX_PKT_BUFFER_DUAL_MAC	127
+#define LAST_ENTRY_OF_TX_PKT_BUFFER_8188F		255
+#define LAST_ENTRY_OF_TX_PKT_BUFFER_8188GTV		255
+#define LAST_ENTRY_OF_TX_PKT_BUFFER_8723D		255
+#define LAST_ENTRY_OF_TX_PKT_BUFFER_8710B		255
+#define LAST_ENTRY_OF_TX_PKT_BUFFER_8192F		255
+#define POLLING_LLT_THRESHOLD				20
+#if defined(CONFIG_RTL8723B) && defined(CONFIG_PCI_HCI)
+	#define POLLING_READY_TIMEOUT_COUNT		6000
+#else
+	#define POLLING_READY_TIMEOUT_COUNT		1000
+#endif
+
+
+/* GPIO BIT */
+#define	HAL_8812A_HW_GPIO_WPS_BIT	BIT(2)
+#define	HAL_8192C_HW_GPIO_WPS_BIT	BIT(2)
+#define	HAL_8192EU_HW_GPIO_WPS_BIT	BIT(7)
+#define	HAL_8188E_HW_GPIO_WPS_BIT	BIT(7)
+
+#endif /* __HAL_COMMON_H__ */
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/include/hal_data.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/hal_data.h
--- linux-5.6.3/3rdparty/rtl8821ce/include/hal_data.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/hal_data.h	2020-04-10 16:35:06.847661515 +0300
@@ -0,0 +1,1061 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#ifndef __HAL_DATA_H__
+#define __HAL_DATA_H__
+
+#if 1/* def  CONFIG_SINGLE_IMG */
+
+#include "../hal/phydm/phydm_precomp.h"
+#ifdef CONFIG_BT_COEXIST
+	#include <hal_btcoex.h>
+#endif
+	#include <hal_btcoex_wifionly.h>
+
+#ifdef CONFIG_SDIO_HCI
+	#include <hal_sdio.h>
+#endif
+#ifdef CONFIG_GSPI_HCI
+	#include <hal_gspi.h>
+#endif
+
+#if defined(CONFIG_RTW_ACS) || defined(CONFIG_BACKGROUND_NOISE_MONITOR)
+#include "../hal/hal_dm_acs.h"
+#endif
+
+/*
+ * <Roger_Notes> For RTL8723 WiFi/BT/GPS multi-function configuration. 2010.10.06.
+ *   */
+typedef enum _RT_MULTI_FUNC {
+	RT_MULTI_FUNC_NONE	= 0x00,
+	RT_MULTI_FUNC_WIFI	= 0x01,
+	RT_MULTI_FUNC_BT		= 0x02,
+	RT_MULTI_FUNC_GPS	= 0x04,
+} RT_MULTI_FUNC, *PRT_MULTI_FUNC;
+/*
+ * <Roger_Notes> For RTL8723 WiFi PDn/GPIO polarity control configuration. 2010.10.08.
+ *   */
+typedef enum _RT_POLARITY_CTL {
+	RT_POLARITY_LOW_ACT	= 0,
+	RT_POLARITY_HIGH_ACT	= 1,
+} RT_POLARITY_CTL, *PRT_POLARITY_CTL;
+
+/* For RTL8723 regulator mode. by tynli. 2011.01.14. */
+typedef enum _RT_REGULATOR_MODE {
+	RT_SWITCHING_REGULATOR	= 0,
+	RT_LDO_REGULATOR			= 1,
+} RT_REGULATOR_MODE, *PRT_REGULATOR_MODE;
+
+/*
+ * Interface type.
+ *   */
+typedef	enum _INTERFACE_SELECT_PCIE {
+	INTF_SEL0_SOLO_MINICARD			= 0,		/* WiFi solo-mCard */
+	INTF_SEL1_BT_COMBO_MINICARD		= 1,		/* WiFi+BT combo-mCard */
+	INTF_SEL2_PCIe						= 2,		/* PCIe Card */
+} INTERFACE_SELECT_PCIE, *PINTERFACE_SELECT_PCIE;
+
+
+typedef	enum _INTERFACE_SELECT_USB {
+	INTF_SEL0_USB 				= 0,		/* USB */
+	INTF_SEL1_USB_High_Power  	= 1,		/* USB with high power PA */
+	INTF_SEL2_MINICARD		  	= 2,		/* Minicard */
+	INTF_SEL3_USB_Solo 		= 3,		/* USB solo-Slim module */
+	INTF_SEL4_USB_Combo		= 4,		/* USB Combo-Slim module */
+	INTF_SEL5_USB_Combo_MF	= 5,		/* USB WiFi+BT Multi-Function Combo, i.e., Proprietary layout(AS-VAU) which is the same as SDIO card */
+} INTERFACE_SELECT_USB, *PINTERFACE_SELECT_USB;
+
+typedef enum _RT_AMPDU_BRUST_MODE {
+	RT_AMPDU_BRUST_NONE		= 0,
+	RT_AMPDU_BRUST_92D		= 1,
+	RT_AMPDU_BRUST_88E		= 2,
+	RT_AMPDU_BRUST_8812_4	= 3,
+	RT_AMPDU_BRUST_8812_8	= 4,
+	RT_AMPDU_BRUST_8812_12	= 5,
+	RT_AMPDU_BRUST_8812_15	= 6,
+	RT_AMPDU_BRUST_8723B		= 7,
+} RT_AMPDU_BRUST, *PRT_AMPDU_BRUST_MODE;
+
+/* Tx Power Limit Table Size */
+#define MAX_REGULATION_NUM						4
+#define MAX_RF_PATH_NUM_IN_POWER_LIMIT_TABLE	4
+#define MAX_2_4G_BANDWIDTH_NUM					2
+#define MAX_RATE_SECTION_NUM						10
+#define MAX_5G_BANDWIDTH_NUM						4
+
+#define MAX_BASE_NUM_IN_PHY_REG_PG_2_4G			10 /* CCK:1, OFDM:1, HT:4, VHT:4 */
+#define MAX_BASE_NUM_IN_PHY_REG_PG_5G			9 /* OFDM:1, HT:4, VHT:4 */
+
+#ifdef RTW_RX_AGGREGATION
+typedef enum _RX_AGG_MODE {
+	RX_AGG_DISABLE,
+	RX_AGG_DMA,
+	RX_AGG_USB,
+	RX_AGG_MIX
+} RX_AGG_MODE;
+
+/* #define MAX_RX_DMA_BUFFER_SIZE	10240 */		/* 10K for 8192C RX DMA buffer */
+
+#endif /* RTW_RX_AGGREGATION */
+
+/* E-Fuse */
+#ifdef CONFIG_RTL8188E
+	#define EFUSE_MAP_SIZE	512
+#endif
+#if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A) || defined(CONFIG_RTL8814A)
+	#define EFUSE_MAP_SIZE	512
+#endif
+#ifdef CONFIG_RTL8192E
+	#define EFUSE_MAP_SIZE	512
+#endif
+#ifdef CONFIG_RTL8723B
+	#define EFUSE_MAP_SIZE	512
+#endif
+#ifdef CONFIG_RTL8814A
+	#define EFUSE_MAP_SIZE	512
+#endif
+#ifdef CONFIG_RTL8703B
+	#define EFUSE_MAP_SIZE	512
+#endif
+#ifdef CONFIG_RTL8723D
+	#define EFUSE_MAP_SIZE	512
+#endif
+#ifdef CONFIG_RTL8188F
+	#define EFUSE_MAP_SIZE	512
+#endif
+#ifdef CONFIG_RTL8188GTV
+	#define EFUSE_MAP_SIZE	512
+#endif
+#ifdef CONFIG_RTL8710B
+	#define EFUSE_MAP_SIZE	512
+#endif
+#ifdef CONFIG_RTL8192F
+	#define EFUSE_MAP_SIZE	512
+#endif
+
+#if defined(CONFIG_RTL8814A) || defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C)
+	#define EFUSE_MAX_SIZE	1024
+#elif defined(CONFIG_RTL8188E) || defined(CONFIG_RTL8188F) || defined(CONFIG_RTL8188GTV) || defined(CONFIG_RTL8703B) || defined(CONFIG_RTL8710B)
+	#define EFUSE_MAX_SIZE	256
+#else
+	#define EFUSE_MAX_SIZE	512
+#endif
+/* end of E-Fuse */
+
+#define Mac_OFDM_OK			0x00000000
+#define Mac_OFDM_Fail		0x10000000
+#define Mac_OFDM_FasleAlarm	0x20000000
+#define Mac_CCK_OK			0x30000000
+#define Mac_CCK_Fail		0x40000000
+#define Mac_CCK_FasleAlarm	0x50000000
+#define Mac_HT_OK			0x60000000
+#define Mac_HT_Fail			0x70000000
+#define Mac_HT_FasleAlarm	0x90000000
+#define Mac_DropPacket		0xA0000000
+
+#ifdef CONFIG_RF_POWER_TRIM
+#if defined(CONFIG_RTL8723B)
+	#define REG_RF_BB_GAIN_OFFSET	0x7f
+	#define RF_GAIN_OFFSET_MASK		0xfffff
+#elif defined(CONFIG_RTL8188E)
+	#define REG_RF_BB_GAIN_OFFSET	0x55
+	#define RF_GAIN_OFFSET_MASK		0xfffff
+#else
+	#define REG_RF_BB_GAIN_OFFSET	0x55
+	#define RF_GAIN_OFFSET_MASK		0xfffff
+#endif /* CONFIG_RTL8723B */
+#endif /*CONFIG_RF_POWER_TRIM*/
+
+/* For store initial value of BB register */
+typedef struct _BB_INIT_REGISTER {
+	u16	offset;
+	u32	value;
+
+} BB_INIT_REGISTER, *PBB_INIT_REGISTER;
+
+#define PAGE_SIZE_128	128
+#define PAGE_SIZE_256	256
+#define PAGE_SIZE_512	512
+
+#define HCI_SUS_ENTER		0
+#define HCI_SUS_LEAVING		1
+#define HCI_SUS_LEAVE		2
+#define HCI_SUS_ENTERING	3
+#define HCI_SUS_ERR			4
+
+#define EFUSE_FILE_UNUSED 0
+#define EFUSE_FILE_FAILED 1
+#define EFUSE_FILE_LOADED 2
+
+#define MACADDR_FILE_UNUSED 0
+#define MACADDR_FILE_FAILED 1
+#define MACADDR_FILE_LOADED 2
+
+#define MAX_IQK_INFO_BACKUP_CHNL_NUM	5
+#define MAX_IQK_INFO_BACKUP_REG_NUM		10
+
+struct kfree_data_t {
+	u8 flag;
+	s8 bb_gain[BB_GAIN_NUM][RF_PATH_MAX];
+
+#ifdef CONFIG_IEEE80211_BAND_5GHZ
+	s8 pa_bias_5g[RF_PATH_MAX];
+	s8 pad_bias_5g[RF_PATH_MAX];
+#endif
+	s8 thermal;
+};
+
+bool kfree_data_is_bb_gain_empty(struct kfree_data_t *data);
+
+struct hal_spec_t {
+	char *ic_name;
+	u8 macid_num;
+
+	u8 sec_cam_ent_num;
+	u8 sec_cap;
+
+	u8 rfpath_num_2g:4;	/* used for tx power index path */
+	u8 rfpath_num_5g:4;	/* used for tx power index path */
+	u8 txgi_max; /* maximum tx power gain index */
+	u8 txgi_pdbm; /* tx power gain index per dBm */
+
+	u8 max_tx_cnt;
+	u8 tx_nss_num:4;
+	u8 rx_nss_num:4;
+	u8 band_cap;	/* value of BAND_CAP_XXX */
+	u8 bw_cap;		/* value of BW_CAP_XXX */
+	u8 port_num;
+	u8 proto_cap;	/* value of PROTO_CAP_XXX */
+	u8 wl_func;		/* value of WL_FUNC_XXX */
+
+	u8 rx_tsf_filter:1;
+
+	u8 pg_txpwr_saddr; /* starting address of PG tx power info */
+	u8 pg_txgi_diff_factor; /* PG tx power gain index diff to tx power gain index */
+
+	u8 hci_type;	/* value of HCI Type */
+};
+
+#define HAL_SPEC_CHK_RF_PATH_2G(_spec, _path) ((_spec)->rfpath_num_2g > (_path))
+#define HAL_SPEC_CHK_RF_PATH_5G(_spec, _path) ((_spec)->rfpath_num_5g > (_path))
+#define HAL_SPEC_CHK_RF_PATH(_spec, _band, _path) ( \
+	_band == BAND_ON_2_4G ? HAL_SPEC_CHK_RF_PATH_2G(_spec, _path) : \
+	_band == BAND_ON_5G ? HAL_SPEC_CHK_RF_PATH_5G(_spec, _path) : 0)
+
+#define HAL_SPEC_CHK_TX_CNT(_spec, _cnt_idx) ((_spec)->max_tx_cnt > (_cnt_idx))
+
+#ifdef CONFIG_PHY_CAPABILITY_QUERY
+struct phy_spec_t {
+	u32 trx_cap;
+	u32 stbc_cap;
+	u32 ldpc_cap;
+	u32 txbf_param;
+	u32 txbf_cap;
+};
+#endif
+struct hal_iqk_reg_backup {
+	u8 central_chnl;
+	u8 bw_mode;
+	u32 reg_backup[MAX_RF_PATH][MAX_IQK_INFO_BACKUP_REG_NUM];
+};
+
+
+typedef struct hal_p2p_ps_para {
+	/*DW0*/
+	u8  offload_en:1;
+	u8  role:1;
+	u8  ctwindow_en:1;
+	u8  noa_en:1;
+	u8  noa_sel:1;
+	u8  all_sta_sleep:1;
+	u8  discovery:1;
+	u8  rsvd2:1;
+	u8  p2p_port_id;
+	u8  p2p_group;
+	u8  p2p_macid;
+
+	/*DW1*/
+	u8 ctwindow_length;
+	u8 rsvd3;
+	u8 rsvd4;
+	u8 rsvd5;
+
+	/*DW2*/
+	u32 noa_duration_para;
+
+	/*DW3*/
+	u32 noa_interval_para;
+
+	/*DW4*/
+	u32 noa_start_time_para;
+
+	/*DW5*/
+	u32 noa_count_para;
+} HAL_P2P_PS_PARA, *PHAL_P2P_PS_PARA;
+
+#define TXPWR_LMT_RS_CCK	0
+#define TXPWR_LMT_RS_OFDM	1
+#define TXPWR_LMT_RS_HT		2
+#define TXPWR_LMT_RS_VHT	3
+#define TXPWR_LMT_RS_NUM	4
+
+#define TXPWR_LMT_RS_NUM_2G	4 /* CCK, OFDM, HT, VHT */
+#define TXPWR_LMT_RS_NUM_5G	3 /* OFDM, HT, VHT */
+
+#ifdef CONFIG_TXPWR_LIMIT
+extern const char *const _txpwr_lmt_rs_str[];
+#define txpwr_lmt_rs_str(rs) (((rs) >= TXPWR_LMT_RS_NUM) ? _txpwr_lmt_rs_str[TXPWR_LMT_RS_NUM] : _txpwr_lmt_rs_str[(rs)])
+
+struct txpwr_lmt_ent {
+	_list list;
+
+	s8 lmt_2g[MAX_2_4G_BANDWIDTH_NUM]
+		[TXPWR_LMT_RS_NUM_2G]
+		[CENTER_CH_2G_NUM]
+		[MAX_TX_COUNT];
+
+#ifdef CONFIG_IEEE80211_BAND_5GHZ
+	s8 lmt_5g[MAX_5G_BANDWIDTH_NUM]
+		[TXPWR_LMT_RS_NUM_5G]
+		[CENTER_CH_5G_ALL_NUM]
+		[MAX_TX_COUNT];
+#endif
+
+	char regd_name[0];
+};
+#endif /* CONFIG_TXPWR_LIMIT */
+
+typedef struct hal_com_data {
+	HAL_VERSION			version_id;
+	RT_MULTI_FUNC		MultiFunc; /* For multi-function consideration. */
+	RT_POLARITY_CTL		PolarityCtl; /* For Wifi PDn Polarity control. */
+	RT_REGULATOR_MODE	RegulatorMode; /* switching regulator or LDO */
+	u8	hw_init_completed;
+	/****** FW related ******/
+	u32 firmware_size;
+	u16 firmware_version;
+	u16	FirmwareVersionRev;
+	u16 firmware_sub_version;
+	u16	FirmwareSignature;
+	u8	RegFWOffload;
+	u8	bFWReady;
+	u8	bBTFWReady;
+	u8	fw_ractrl;
+	u8	LastHMEBoxNum;	/* H2C - for host message to fw */
+
+	/****** current WIFI_PHY values ******/
+	WIRELESS_MODE	CurrentWirelessMode;
+	enum channel_width current_channel_bw;
+	BAND_TYPE		current_band_type;	/* 0:2.4G, 1:5G */
+	BAND_TYPE		BandSet;
+	u8				current_channel;
+	u8				cch_20;
+	u8				cch_40;
+	u8				cch_80;
+	u8				CurrentCenterFrequencyIndex1;
+	u8				nCur40MhzPrimeSC;	/* Control channel sub-carrier */
+	u8				nCur80MhzPrimeSC;   /* used for primary 40MHz of 80MHz mode */
+	BOOLEAN		bSwChnlAndSetBWInProgress;
+	u8				bDisableSWChannelPlan; /* flag of disable software change channel plan	 */
+	u16				BasicRateSet;
+	u32				ReceiveConfig;
+	u32				rcr_backup; /* used for switching back from monitor mode */
+	u8				rx_tsf_addr_filter_config; /* for 8822B/8821C USE */
+	BOOLEAN			bSwChnl;
+	BOOLEAN			bSetChnlBW;
+	BOOLEAN			bSWToBW40M;
+	BOOLEAN			bSWToBW80M;
+	BOOLEAN			bChnlBWInitialized;
+	u32				BackUp_BB_REG_4_2nd_CCA[3];
+
+#ifdef CONFIG_RTW_ACS
+	struct auto_chan_sel acs;
+#endif
+#ifdef CONFIG_BCN_RECOVERY
+	u8 issue_bcn_fail;
+#endif /*CONFIG_BCN_RECOVERY*/
+
+	/****** rf_ctrl *****/
+	u8	rf_chip;
+	u8	rf_type;	/*enum rf_type*/
+	u8	PackageType;
+	u8	NumTotalRFPath;
+	u8	antenna_test;
+
+	/****** Debug ******/
+	u16	ForcedDataRate;	/* Force Data Rate. 0: Auto, 0x02: 1M ~ 0x6C: 54M. */
+	u8	bDumpRxPkt;
+	u8	bDumpTxPkt;
+	u8	dis_turboedca;
+
+
+	/****** EEPROM setting.******/
+	u8	bautoload_fail_flag;
+	u8	efuse_file_status;
+	u8	macaddr_file_status;
+	u8	EepromOrEfuse;
+	u8	efuse_eeprom_data[EEPROM_MAX_SIZE]; /*92C:256bytes, 88E:512bytes, we use union set (512bytes)*/
+	u8	InterfaceSel; /* board type kept in eFuse */
+	u16	CustomerID;
+
+	u16	EEPROMVID;
+	u16	EEPROMSVID;
+#ifdef CONFIG_USB_HCI
+	u8	EEPROMUsbSwitch;
+	u16	EEPROMPID;
+	u16	EEPROMSDID;
+#endif
+#ifdef CONFIG_PCI_HCI
+	u16	EEPROMDID;
+	u16	EEPROMSMID;
+#endif
+
+	u8	EEPROMCustomerID;
+	u8	EEPROMSubCustomerID;
+	u8	EEPROMVersion;
+	u8	EEPROMRegulatory;
+	u8	eeprom_thermal_meter;
+	u8	EEPROMBluetoothCoexist;
+	u8	EEPROMBluetoothType;
+	u8	EEPROMBluetoothAntNum;
+	u8	EEPROMBluetoothAntIsolation;
+	u8	EEPROMBluetoothRadioShared;
+	u8	EEPROMMACAddr[ETH_ALEN];
+	u8	tx_bbswing_24G;
+	u8	tx_bbswing_5G;
+	u8	efuse0x3d7;	/* efuse[0x3D7] */
+	u8	efuse0x3d8;	/* efuse[0x3D8] */
+
+#ifdef CONFIG_RF_POWER_TRIM
+	u8	EEPROMRFGainOffset;
+	u8	EEPROMRFGainVal;
+	struct kfree_data_t kfree_data;
+#endif /*CONFIG_RF_POWER_TRIM*/
+
+#if defined(CONFIG_RTL8723B) || defined(CONFIG_RTL8703B) || \
+	defined(CONFIG_RTL8723D) || \
+	defined(CONFIG_RTL8192F)
+
+	u8	adjuseVoltageVal;
+	u8	need_restore;
+#endif
+	u8	EfuseUsedPercentage;
+	u16	EfuseUsedBytes;
+	/*u8		EfuseMap[2][HWSET_MAX_SIZE_JAGUAR];*/
+	EFUSE_HAL	EfuseHal;
+
+	/*---------------------------------------------------------------------------------*/
+	/* 2.4G TX power info for target TX power*/
+	u8	Index24G_CCK_Base[MAX_RF_PATH][CENTER_CH_2G_NUM];
+	u8	Index24G_BW40_Base[MAX_RF_PATH][CENTER_CH_2G_NUM];
+	s8	CCK_24G_Diff[MAX_RF_PATH][MAX_TX_COUNT];
+	s8	OFDM_24G_Diff[MAX_RF_PATH][MAX_TX_COUNT];
+	s8	BW20_24G_Diff[MAX_RF_PATH][MAX_TX_COUNT];
+	s8	BW40_24G_Diff[MAX_RF_PATH][MAX_TX_COUNT];
+
+	/* 5G TX power info for target TX power*/
+#ifdef CONFIG_IEEE80211_BAND_5GHZ
+	u8	Index5G_BW40_Base[MAX_RF_PATH][CENTER_CH_5G_ALL_NUM];
+	u8	Index5G_BW80_Base[MAX_RF_PATH][CENTER_CH_5G_80M_NUM];
+	s8	OFDM_5G_Diff[MAX_RF_PATH][MAX_TX_COUNT];
+	s8	BW20_5G_Diff[MAX_RF_PATH][MAX_TX_COUNT];
+	s8	BW40_5G_Diff[MAX_RF_PATH][MAX_TX_COUNT];
+	s8	BW80_5G_Diff[MAX_RF_PATH][MAX_TX_COUNT];
+#endif
+
+	u8 txpwr_by_rate_undefined_band_path[TX_PWR_BY_RATE_NUM_BAND]
+		[TX_PWR_BY_RATE_NUM_RF];
+
+	s8	TxPwrByRateOffset[TX_PWR_BY_RATE_NUM_BAND]
+		[TX_PWR_BY_RATE_NUM_RF]
+		[TX_PWR_BY_RATE_NUM_RATE];
+
+	/* Store the original power by rate value of the base rate for each rate section and rf path */
+	u8	TxPwrByRateBase2_4G[TX_PWR_BY_RATE_NUM_RF]
+		[MAX_BASE_NUM_IN_PHY_REG_PG_2_4G];
+	u8	TxPwrByRateBase5G[TX_PWR_BY_RATE_NUM_RF]
+		[MAX_BASE_NUM_IN_PHY_REG_PG_5G];
+
+	u8	txpwr_by_rate_loaded:1;
+	u8	txpwr_by_rate_from_file:1;
+	u8	txpwr_limit_loaded:1;
+	u8	txpwr_limit_from_file:1;
+	u8	rf_power_tracking_type;
+
+	/* Read/write are allow for following hardware information variables	 */
+	u8	crystal_cap;
+
+	u8	PAType_2G;
+	u8	PAType_5G;
+	u8	LNAType_2G;
+	u8	LNAType_5G;
+	u8	ExternalPA_2G;
+	u8	ExternalLNA_2G;
+	u8	external_pa_5g;
+	u8	external_lna_5g;
+	u16	TypeGLNA;
+	u16	TypeGPA;
+	u16	TypeALNA;
+	u16	TypeAPA;
+	u16	rfe_type;
+
+	u8	bLedOpenDrain; /* Support Open-drain arrangement for controlling the LED. Added by Roger, 2009.10.16. */
+	u32	ac_param_be; /* Original parameter for BE, use for EDCA turbo.	*/
+	u8	is_turbo_edca;
+	u8	prv_traffic_idx;
+	BB_REGISTER_DEFINITION_T	PHYRegDef[MAX_RF_PATH];	/* Radio A/B/C/D */
+
+	u32	RfRegChnlVal[MAX_RF_PATH];
+
+	/* RDG enable */
+	BOOLEAN	 bRDGEnable;
+
+	u16 RegRRSR;
+	/****** antenna diversity ******/
+	u8	AntDivCfg;
+	u8	with_extenal_ant_switch;
+	u8	b_fix_tx_ant;
+	u8	AntDetection;
+	u8	TRxAntDivType;
+	u8	ant_path; /* for 8723B s0/s1 selection	 */
+	u32	antenna_tx_path;					/* Antenna path Tx */
+	u32	AntennaRxPath;					/* Antenna path Rx */
+	u8 sw_antdiv_bl_state;
+
+	/******** PHY DM & DM Section **********/
+	_lock		IQKSpinLock;
+	u8			INIDATA_RATE[MACID_NUM_SW_LIMIT];
+
+	struct dm_struct	 odmpriv;
+	u64			bk_rf_ability;
+	u8			bIQKInitialized;
+	u8			bNeedIQK;
+	u8			neediqk_24g;
+	u8			IQK_MP_Switch;
+	u8			bScanInProcess;
+	/******** PHY DM & DM Section **********/
+
+
+
+	/* 2010/08/09 MH Add CU power down mode. */
+	BOOLEAN		pwrdown;
+
+	/* Add for dual MAC  0--Mac0 1--Mac1 */
+	u32	interfaceIndex;
+
+#ifdef CONFIG_P2P
+	u8	p2p_ps_offload;
+#endif
+	/* Auto FSM to Turn On, include clock, isolation, power control for MAC only */
+	u8	bMacPwrCtrlOn;
+	u8 hci_sus_state;
+
+	u8	RegIQKFWOffload;
+	struct submit_ctx	iqk_sctx;
+	u8 ch_switch_offload;
+	struct submit_ctx chsw_sctx;
+
+	RT_AMPDU_BRUST		AMPDUBurstMode; /* 92C maybe not use, but for compile successfully */
+
+	u8	OutEpQueueSel;
+	u8	OutEpNumber;
+
+#ifdef RTW_RX_AGGREGATION
+	RX_AGG_MODE rxagg_mode;
+
+	/* For RX Aggregation DMA Mode */
+	u8 rxagg_dma_size;
+	u8 rxagg_dma_timeout;
+#endif /* RTW_RX_AGGREGATION */
+
+#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
+	/*  */
+	/* For SDIO Interface HAL related */
+	/*  */
+
+	/*  */
+	/* SDIO ISR Related */
+	/*
+	*	u32			IntrMask[1];
+	*	u32			IntrMaskToSet[1];
+	*	LOG_INTERRUPT		InterruptLog; */
+	u32			sdio_himr;
+	u32			sdio_hisr;
+#ifndef RTW_HALMAC
+	/*  */
+	/* SDIO Tx FIFO related. */
+	/*  */
+	/* HIQ, MID, LOW, PUB free pages; padapter->xmitpriv.free_txpg */
+#ifdef CONFIG_RTL8192F
+	u16			SdioTxFIFOFreePage[SDIO_TX_FREE_PG_QUEUE];
+#else
+	u8			SdioTxFIFOFreePage[SDIO_TX_FREE_PG_QUEUE];
+#endif/*CONFIG_RTL8192F*/
+	_lock		SdioTxFIFOFreePageLock;
+	u8			SdioTxOQTMaxFreeSpace;
+	u8			SdioTxOQTFreeSpace;
+#else /* RTW_HALMAC */
+	u16			SdioTxOQTFreeSpace;
+#endif /* RTW_HALMAC */
+
+	/*  */
+	/* SDIO Rx FIFO related. */
+	/*  */
+	u8			SdioRxFIFOCnt;
+	u16			SdioRxFIFOSize;
+
+#ifndef RTW_HALMAC
+	u32			sdio_tx_max_len[SDIO_MAX_TX_QUEUE];/* H, N, L, used for sdio tx aggregation max length per queue */
+#else
+#ifdef CONFIG_RTL8821C
+	u16			tx_high_page;
+	u16			tx_low_page;
+	u16			tx_normal_page;
+	u16			tx_extra_page;
+	u16			tx_pub_page;
+	u8			max_oqt_size;
+	#ifdef XMIT_BUF_SIZE
+	u32			max_xmit_size_vovi;
+	u32			max_xmit_size_bebk;
+	#endif /*XMIT_BUF_SIZE*/
+	u16			max_xmit_page;
+	u16			max_xmit_page_vo;
+	u16			max_xmit_page_vi;
+	u16			max_xmit_page_be;
+	u16			max_xmit_page_bk;
+
+#endif /*#ifdef CONFIG_RTL8821C*/
+#endif /* !RTW_HALMAC */
+#endif /* CONFIG_SDIO_HCI */
+
+#ifdef CONFIG_USB_HCI
+
+	/* 2010/12/10 MH Add for USB aggreation mode dynamic shceme. */
+	BOOLEAN		UsbRxHighSpeedMode;
+	BOOLEAN		UsbTxVeryHighSpeedMode;
+	u32			UsbBulkOutSize;
+	BOOLEAN		bSupportUSB3;
+	u8			usb_intf_start;
+
+	/* Interrupt relatd register information. */
+	u32			IntArray[3];/* HISR0,HISR1,HSISR */
+	u32			IntrMask[3];
+#ifdef CONFIG_USB_TX_AGGREGATION
+	u8			UsbTxAggMode;
+	u8			UsbTxAggDescNum;
+#endif /* CONFIG_USB_TX_AGGREGATION */
+
+#ifdef CONFIG_USB_RX_AGGREGATION
+	u16			HwRxPageSize;				/* Hardware setting */
+
+	/* For RX Aggregation USB Mode */
+	u8			rxagg_usb_size;
+	u8			rxagg_usb_timeout;
+#endif/* CONFIG_USB_RX_AGGREGATION */
+#endif /* CONFIG_USB_HCI */
+
+
+#ifdef CONFIG_PCI_HCI
+	/*  */
+	/* EEPROM setting. */
+	/*  */
+	u32			TransmitConfig;
+	u32			IntrMaskToSet[2];
+	u32			IntArray[4];
+	u32			IntrMask[4];
+	u32			SysIntArray[1];
+	u32			SysIntrMask[1];
+	u32			IntrMaskReg[2];
+	u32			IntrMaskDefault[4];
+
+	BOOLEAN		bL1OffSupport;
+	BOOLEAN	bSupportBackDoor;
+	u32			pci_backdoor_ctrl;
+
+	u8			bDefaultAntenna;
+
+	u8			bInterruptMigration;
+	u8			bDisableTxInt;
+
+	u16			RxTag;
+#ifdef CONFIG_PCI_DYNAMIC_ASPM
+	BOOLEAN		bAspmL1LastIdle;
+#endif
+#endif /* CONFIG_PCI_HCI */
+
+
+#ifdef DBG_CONFIG_ERROR_DETECT
+	struct sreset_priv srestpriv;
+#endif /* #ifdef DBG_CONFIG_ERROR_DETECT */
+
+#ifdef CONFIG_BT_COEXIST
+	/* For bluetooth co-existance */
+	BT_COEXIST		bt_coexist;
+#endif /* CONFIG_BT_COEXIST */
+
+#if defined(CONFIG_RTL8723B) || defined(CONFIG_RTL8703B) \
+	|| defined(CONFIG_RTL8188F) || defined(CONFIG_RTL8188GTV) || defined(CONFIG_RTL8723D)|| defined(CONFIG_RTL8192F)
+#ifndef CONFIG_PCI_HCI	/* mutual exclusive with PCI -- so they're SDIO and GSPI */
+	/* Interrupt relatd register information. */
+	u32			SysIntrStatus;
+	u32			SysIntrMask;
+#endif
+#endif /*endif CONFIG_RTL8723B	*/
+
+#ifdef CONFIG_LOAD_PHY_PARA_FROM_FILE
+	char	para_file_buf[MAX_PARA_FILE_BUF_LEN];
+	char *mac_reg;
+	u32	mac_reg_len;
+	char *bb_phy_reg;
+	u32	bb_phy_reg_len;
+	char *bb_agc_tab;
+	u32	bb_agc_tab_len;
+	char *bb_phy_reg_pg;
+	u32	bb_phy_reg_pg_len;
+	char *bb_phy_reg_mp;
+	u32	bb_phy_reg_mp_len;
+	char *rf_radio_a;
+	u32	rf_radio_a_len;
+	char *rf_radio_b;
+	u32	rf_radio_b_len;
+	char *rf_tx_pwr_track;
+	u32	rf_tx_pwr_track_len;
+	char *rf_tx_pwr_lmt;
+	u32	rf_tx_pwr_lmt_len;
+#endif
+
+#ifdef CONFIG_BACKGROUND_NOISE_MONITOR
+	struct noise_monitor nm;
+#endif
+
+	struct hal_spec_t hal_spec;
+#ifdef CONFIG_PHY_CAPABILITY_QUERY
+	struct phy_spec_t phy_spec;
+#endif
+	u8	RfKFreeEnable;
+	u8	RfKFree_ch_group;
+	BOOLEAN				bCCKinCH14;
+	BB_INIT_REGISTER	RegForRecover[5];
+
+#if defined(CONFIG_PCI_HCI) && defined(RTL8814AE_SW_BCN)
+	BOOLEAN bCorrectBCN;
+#endif
+	u32 RxGainOffset[4]; /*{2G, 5G_Low, 5G_Middle, G_High}*/
+	u8 BackUp_IG_REG_4_Chnl_Section[4]; /*{A,B,C,D}*/
+
+	struct hal_iqk_reg_backup iqk_reg_backup[MAX_IQK_INFO_BACKUP_CHNL_NUM];
+
+#ifdef RTW_HALMAC
+	u8 drv_rsvd_page_number;
+#endif
+
+#ifdef CONFIG_BEAMFORMING
+	u8 backup_snd_ptcl_ctrl;
+#ifdef RTW_BEAMFORMING_VERSION_2
+	struct beamforming_info beamforming_info;
+#endif /* RTW_BEAMFORMING_VERSION_2 */
+#endif /* CONFIG_BEAMFORMING */
+
+	u8 not_xmitframe_fw_dl; /*not use xmitframe to download fw*/
+	u8 phydm_op_mode;
+
+	u8 in_cta_test;
+
+#ifdef CONFIG_RTW_LED
+	struct led_priv led;
+#endif
+} HAL_DATA_COMMON, *PHAL_DATA_COMMON;
+
+typedef struct hal_com_data HAL_DATA_TYPE, *PHAL_DATA_TYPE;
+#define GET_HAL_DATA(__pAdapter)			((HAL_DATA_TYPE *)(((struct _ADAPTER*)__pAdapter)->HalData))
+#define GET_HAL_SPEC(__pAdapter)			(&(GET_HAL_DATA((__pAdapter))->hal_spec))
+#define adapter_to_led(adapter) (&(GET_HAL_DATA(adapter)->led))
+
+#define GET_HAL_RFPATH_NUM(__pAdapter)		(((HAL_DATA_TYPE *)((__pAdapter)->HalData))->NumTotalRFPath)
+#define RT_GetInterfaceSelection(_Adapter)		(GET_HAL_DATA(_Adapter)->InterfaceSel)
+#define GET_RF_TYPE(__pAdapter)				(GET_HAL_DATA(__pAdapter)->rf_type)
+#define GET_KFREE_DATA(_adapter) (&(GET_HAL_DATA((_adapter))->kfree_data))
+
+#define	SUPPORT_HW_RADIO_DETECT(Adapter)	(RT_GetInterfaceSelection(Adapter) == INTF_SEL2_MINICARD || \
+		RT_GetInterfaceSelection(Adapter) == INTF_SEL3_USB_Solo || \
+		RT_GetInterfaceSelection(Adapter) == INTF_SEL4_USB_Combo)
+
+#define get_hal_mac_addr(adapter)				(GET_HAL_DATA(adapter)->EEPROMMACAddr)
+#define is_boot_from_eeprom(adapter)			(GET_HAL_DATA(adapter)->EepromOrEfuse)
+#define rtw_get_hw_init_completed(adapter)		(GET_HAL_DATA(adapter)->hw_init_completed)
+#define rtw_set_hw_init_completed(adapter, cmp)	(GET_HAL_DATA(adapter)->hw_init_completed = cmp)
+#define rtw_is_hw_init_completed(adapter)		(GET_HAL_DATA(adapter)->hw_init_completed == _TRUE)
+#endif
+
+#ifdef RTW_HALMAC
+int rtw_halmac_deinit_adapter(struct dvobj_priv *);
+#endif /* RTW_HALMAC */
+
+/* alias for phydm coding style */
+#define REG_OFDM_0_XA_TX_IQ_IMBALANCE	rOFDM0_XATxIQImbalance
+#define REG_OFDM_0_ECCA_THRESHOLD		rOFDM0_ECCAThreshold
+#define REG_FPGA0_XB_LSSI_READ_BACK		rFPGA0_XB_LSSIReadBack
+#define REG_FPGA0_TX_GAIN_STAGE			rFPGA0_TxGainStage
+#define REG_OFDM_0_XA_AGC_CORE1			rOFDM0_XAAGCCore1
+#define REG_OFDM_0_XB_AGC_CORE1			rOFDM0_XBAGCCore1
+#define REG_A_TX_SCALE_JAGUAR			rA_TxScale_Jaguar
+#define REG_B_TX_SCALE_JAGUAR			rB_TxScale_Jaguar
+
+#define REG_FPGA0_XAB_RF_INTERFACE_SW	rFPGA0_XAB_RFInterfaceSW
+#define REG_FPGA0_XAB_RF_PARAMETER	rFPGA0_XAB_RFParameter
+#define REG_FPGA0_XA_HSSI_PARAMETER1	rFPGA0_XA_HSSIParameter1
+#define REG_FPGA0_XA_LSSI_PARAMETER	rFPGA0_XA_LSSIParameter
+#define REG_FPGA0_XA_RF_INTERFACE_OE	rFPGA0_XA_RFInterfaceOE
+#define REG_FPGA0_XB_HSSI_PARAMETER1	rFPGA0_XB_HSSIParameter1
+#define REG_FPGA0_XB_LSSI_PARAMETER	rFPGA0_XB_LSSIParameter
+#define REG_FPGA0_XB_LSSI_READ_BACK	rFPGA0_XB_LSSIReadBack
+#define REG_FPGA0_XB_RF_INTERFACE_OE	rFPGA0_XB_RFInterfaceOE
+#define REG_FPGA0_XCD_RF_INTERFACE_SW	rFPGA0_XCD_RFInterfaceSW
+#define REG_FPGA0_XCD_SWITCH_CONTROL	rFPGA0_XCD_SwitchControl
+#define REG_FPGA1_TX_BLOCK	rFPGA1_TxBlock
+#define REG_FPGA1_TX_INFO	rFPGA1_TxInfo
+#define REG_IQK_AGC_CONT	rIQK_AGC_Cont
+#define REG_IQK_AGC_PTS	rIQK_AGC_Pts
+#define REG_IQK_AGC_RSP	rIQK_AGC_Rsp
+#define REG_OFDM_0_AGC_RSSI_TABLE	rOFDM0_AGCRSSITable
+#define REG_OFDM_0_ECCA_THRESHOLD	rOFDM0_ECCAThreshold
+#define REG_OFDM_0_RX_IQ_EXT_ANTA	rOFDM0_RxIQExtAnta
+#define REG_OFDM_0_TR_MUX_PAR	rOFDM0_TRMuxPar
+#define REG_OFDM_0_TRX_PATH_ENABLE	rOFDM0_TRxPathEnable
+#define REG_OFDM_0_XA_AGC_CORE1	rOFDM0_XAAGCCore1
+#define REG_OFDM_0_XA_RX_IQ_IMBALANCE	rOFDM0_XARxIQImbalance
+#define REG_OFDM_0_XA_TX_IQ_IMBALANCE	rOFDM0_XATxIQImbalance
+#define REG_OFDM_0_XB_AGC_CORE1	rOFDM0_XBAGCCore1
+#define REG_OFDM_0_XB_RX_IQ_IMBALANCE	rOFDM0_XBRxIQImbalance
+#define REG_OFDM_0_XB_TX_IQ_IMBALANCE	rOFDM0_XBTxIQImbalance
+#define REG_OFDM_0_XC_TX_AFE	rOFDM0_XCTxAFE
+#define REG_OFDM_0_XD_TX_AFE	rOFDM0_XDTxAFE
+
+/*#define REG_A_CFO_LONG_DUMP_92E	rA_CfoLongDump_92E*/
+#define REG_A_CFO_LONG_DUMP_JAGUAR	rA_CfoLongDump_Jaguar
+/*#define REG_A_CFO_SHORT_DUMP_92E	rA_CfoShortDump_92E*/
+#define REG_A_CFO_SHORT_DUMP_JAGUAR	rA_CfoShortDump_Jaguar
+#define REG_A_RFE_PINMUX_JAGUAR	rA_RFE_Pinmux_Jaguar
+/*#define REG_A_RSSI_DUMP_92E	rA_RSSIDump_92E*/
+#define REG_A_RSSI_DUMP_JAGUAR	rA_RSSIDump_Jaguar
+/*#define REG_A_RX_SNR_DUMP_92E	rA_RXsnrDump_92E*/
+#define REG_A_RX_SNR_DUMP_JAGUAR	rA_RXsnrDump_Jaguar
+/*#define REG_A_TX_AGC	rA_TXAGC*/
+#define REG_A_TX_SCALE_JAGUAR	rA_TxScale_Jaguar
+#define REG_BW_INDICATION_JAGUAR	rBWIndication_Jaguar
+/*#define REG_B_BBSWING	rB_BBSWING*/
+/*#define REG_B_CFO_LONG_DUMP_92E	rB_CfoLongDump_92E*/
+#define REG_B_CFO_LONG_DUMP_JAGUAR	rB_CfoLongDump_Jaguar
+/*#define REG_B_CFO_SHORT_DUMP_92E	rB_CfoShortDump_92E*/
+#define REG_B_CFO_SHORT_DUMP_JAGUAR	rB_CfoShortDump_Jaguar
+/*#define REG_B_RSSI_DUMP_92E	rB_RSSIDump_92E*/
+#define REG_B_RSSI_DUMP_JAGUAR	rB_RSSIDump_Jaguar
+/*#define REG_B_RX_SNR_DUMP_92E	rB_RXsnrDump_92E*/
+#define REG_B_RX_SNR_DUMP_JAGUAR	rB_RXsnrDump_Jaguar
+/*#define REG_B_TX_AGC	rB_TXAGC*/
+#define REG_B_TX_SCALE_JAGUAR	rB_TxScale_Jaguar
+#define REG_BLUE_TOOTH	rBlue_Tooth
+#define REG_CCK_0_AFE_SETTING	rCCK0_AFESetting
+/*#define REG_C_BBSWING	rC_BBSWING*/
+/*#define REG_C_TX_AGC	rC_TXAGC*/
+#define REG_C_TX_SCALE_JAGUAR2	rC_TxScale_Jaguar2
+#define REG_CONFIG_ANT_A	rConfig_AntA
+#define REG_CONFIG_ANT_B	rConfig_AntB
+#define REG_CONFIG_PMPD_ANT_A	rConfig_Pmpd_AntA
+#define REG_CONFIG_PMPD_ANT_B	rConfig_Pmpd_AntB
+#define REG_DPDT_CONTROL	rDPDT_control
+/*#define REG_D_BBSWING	rD_BBSWING*/
+/*#define REG_D_TX_AGC	rD_TXAGC*/
+#define REG_D_TX_SCALE_JAGUAR2	rD_TxScale_Jaguar2
+#define REG_FPGA0_ANALOG_PARAMETER4	rFPGA0_AnalogParameter4
+#define REG_FPGA0_IQK	rFPGA0_IQK
+#define REG_FPGA0_PSD_FUNCTION	rFPGA0_PSDFunction
+#define REG_FPGA0_PSD_REPORT	rFPGA0_PSDReport
+#define REG_FPGA0_RFMOD	rFPGA0_RFMOD
+#define REG_FPGA0_TX_GAIN_STAGE	rFPGA0_TxGainStage
+#define REG_FPGA0_XAB_RF_INTERFACE_SW	rFPGA0_XAB_RFInterfaceSW
+#define REG_FPGA0_XAB_RF_PARAMETER	rFPGA0_XAB_RFParameter
+#define REG_FPGA0_XA_HSSI_PARAMETER1	rFPGA0_XA_HSSIParameter1
+#define REG_FPGA0_XA_LSSI_PARAMETER	rFPGA0_XA_LSSIParameter
+#define REG_FPGA0_XA_RF_INTERFACE_OE	rFPGA0_XA_RFInterfaceOE
+#define REG_FPGA0_XB_HSSI_PARAMETER1	rFPGA0_XB_HSSIParameter1
+#define REG_FPGA0_XB_LSSI_PARAMETER	rFPGA0_XB_LSSIParameter
+#define REG_FPGA0_XB_LSSI_READ_BACK	rFPGA0_XB_LSSIReadBack
+#define REG_FPGA0_XB_RF_INTERFACE_OE	rFPGA0_XB_RFInterfaceOE
+#define REG_FPGA0_XCD_RF_INTERFACE_SW	rFPGA0_XCD_RFInterfaceSW
+#define REG_FPGA0_XCD_SWITCH_CONTROL	rFPGA0_XCD_SwitchControl
+#define REG_FPGA1_TX_BLOCK	rFPGA1_TxBlock
+#define REG_FPGA1_TX_INFO	rFPGA1_TxInfo
+#define REG_IQK_AGC_CONT	rIQK_AGC_Cont
+#define REG_IQK_AGC_PTS	rIQK_AGC_Pts
+#define REG_IQK_AGC_RSP	rIQK_AGC_Rsp
+#define REG_OFDM_0_AGC_RSSI_TABLE	rOFDM0_AGCRSSITable
+#define REG_OFDM_0_ECCA_THRESHOLD	rOFDM0_ECCAThreshold
+#define REG_OFDM_0_RX_IQ_EXT_ANTA	rOFDM0_RxIQExtAnta
+#define REG_OFDM_0_TR_MUX_PAR	rOFDM0_TRMuxPar
+#define REG_OFDM_0_TRX_PATH_ENABLE	rOFDM0_TRxPathEnable
+#define REG_OFDM_0_XA_AGC_CORE1	rOFDM0_XAAGCCore1
+#define REG_OFDM_0_XA_RX_IQ_IMBALANCE	rOFDM0_XARxIQImbalance
+#define REG_OFDM_0_XA_TX_IQ_IMBALANCE	rOFDM0_XATxIQImbalance
+#define REG_OFDM_0_XB_AGC_CORE1	rOFDM0_XBAGCCore1
+#define REG_OFDM_0_XB_RX_IQ_IMBALANCE	rOFDM0_XBRxIQImbalance
+#define REG_OFDM_0_XB_TX_IQ_IMBALANCE	rOFDM0_XBTxIQImbalance
+#define REG_OFDM_0_XC_TX_AFE	rOFDM0_XCTxAFE
+#define REG_OFDM_0_XD_TX_AFE	rOFDM0_XDTxAFE
+#define REG_PMPD_ANAEN	rPMPD_ANAEN
+#define REG_PDP_ANT_A	rPdp_AntA
+#define REG_PDP_ANT_A_4	rPdp_AntA_4
+#define REG_PDP_ANT_B	rPdp_AntB
+#define REG_PDP_ANT_B_4	rPdp_AntB_4
+#define REG_PWED_TH_JAGUAR	rPwed_TH_Jaguar
+#define REG_RX_CCK	rRx_CCK
+#define REG_RX_IQK	rRx_IQK
+#define REG_RX_IQK_PI_A	rRx_IQK_PI_A
+#define REG_RX_IQK_PI_B	rRx_IQK_PI_B
+#define REG_RX_IQK_TONE_A	rRx_IQK_Tone_A
+#define REG_RX_IQK_TONE_B	rRx_IQK_Tone_B
+#define REG_RX_OFDM	rRx_OFDM
+#define REG_RX_POWER_AFTER_IQK_A_2	rRx_Power_After_IQK_A_2
+#define REG_RX_POWER_AFTER_IQK_B_2	rRx_Power_After_IQK_B_2
+#define REG_RX_POWER_BEFORE_IQK_A_2	rRx_Power_Before_IQK_A_2
+#define REG_RX_POWER_BEFORE_IQK_B_2	rRx_Power_Before_IQK_B_2
+#define REG_RX_TO_RX	rRx_TO_Rx
+#define REG_RX_WAIT_CCA	rRx_Wait_CCA
+#define REG_RX_WAIT_RIFS	rRx_Wait_RIFS
+#define REG_S0_S1_PATH_SWITCH	rS0S1_PathSwitch
+/*#define REG_S1_RXEVM_DUMP_92E	rS1_RXevmDump_92E*/
+#define REG_S1_RXEVM_DUMP_JAGUAR	rS1_RXevmDump_Jaguar
+/*#define REG_S2_RXEVM_DUMP_92E	rS2_RXevmDump_92E*/
+#define REG_S2_RXEVM_DUMP_JAGUAR	rS2_RXevmDump_Jaguar
+#define REG_SYM_WLBT_PAPE_SEL	rSYM_WLBT_PAPE_SEL
+#define REG_SINGLE_TONE_CONT_TX_JAGUAR	rSingleTone_ContTx_Jaguar
+#define REG_SLEEP	rSleep
+#define REG_STANDBY	rStandby
+#define REG_TX_AGC_A_CCK_11_CCK_1_JAGUAR	rTxAGC_A_CCK11_CCK1_JAguar
+#define REG_TX_AGC_A_CCK_1_MCS32	rTxAGC_A_CCK1_Mcs32
+#define REG_TX_AGC_A_MCS11_MCS8_JAGUAR	rTxAGC_A_MCS11_MCS8_JAguar
+#define REG_TX_AGC_A_MCS15_MCS12_JAGUAR	rTxAGC_A_MCS15_MCS12_JAguar
+#define REG_TX_AGC_A_MCS19_MCS16_JAGUAR	rTxAGC_A_MCS19_MCS16_JAguar
+#define REG_TX_AGC_A_MCS23_MCS20_JAGUAR	rTxAGC_A_MCS23_MCS20_JAguar
+#define REG_TX_AGC_A_MCS3_MCS0_JAGUAR	rTxAGC_A_MCS3_MCS0_JAguar
+#define REG_TX_AGC_A_MCS7_MCS4_JAGUAR	rTxAGC_A_MCS7_MCS4_JAguar
+#define REG_TX_AGC_A_MCS03_MCS00	rTxAGC_A_Mcs03_Mcs00
+#define REG_TX_AGC_A_MCS07_MCS04	rTxAGC_A_Mcs07_Mcs04
+#define REG_TX_AGC_A_MCS11_MCS08	rTxAGC_A_Mcs11_Mcs08
+#define REG_TX_AGC_A_MCS15_MCS12	rTxAGC_A_Mcs15_Mcs12
+#define REG_TX_AGC_A_NSS1_INDEX3_NSS1_INDEX0_JAGUAR	rTxAGC_A_Nss1Index3_Nss1Index0_JAguar
+#define REG_TX_AGC_A_NSS1_INDEX7_NSS1_INDEX4_JAGUAR	rTxAGC_A_Nss1Index7_Nss1Index4_JAguar
+#define REG_TX_AGC_A_NSS2_INDEX1_NSS1_INDEX8_JAGUAR	rTxAGC_A_Nss2Index1_Nss1Index8_JAguar
+#define REG_TX_AGC_A_NSS2_INDEX5_NSS2_INDEX2_JAGUAR	rTxAGC_A_Nss2Index5_Nss2Index2_JAguar
+#define REG_TX_AGC_A_NSS2_INDEX9_NSS2_INDEX6_JAGUAR	rTxAGC_A_Nss2Index9_Nss2Index6_JAguar
+#define REG_TX_AGC_A_NSS3_INDEX3_NSS3_INDEX0_JAGUAR	rTxAGC_A_Nss3Index3_Nss3Index0_JAguar
+#define REG_TX_AGC_A_NSS3_INDEX7_NSS3_INDEX4_JAGUAR	rTxAGC_A_Nss3Index7_Nss3Index4_JAguar
+#define REG_TX_AGC_A_NSS3_INDEX9_NSS3_INDEX8_JAGUAR	rTxAGC_A_Nss3Index9_Nss3Index8_JAguar
+#define REG_TX_AGC_A_OFDM18_OFDM6_JAGUAR	rTxAGC_A_Ofdm18_Ofdm6_JAguar
+#define REG_TX_AGC_A_OFDM54_OFDM24_JAGUAR	rTxAGC_A_Ofdm54_Ofdm24_JAguar
+#define REG_TX_AGC_A_RATE18_06	rTxAGC_A_Rate18_06
+#define REG_TX_AGC_A_RATE54_24	rTxAGC_A_Rate54_24
+#define REG_TX_AGC_B_CCK_11_A_CCK_2_11	rTxAGC_B_CCK11_A_CCK2_11
+#define REG_TX_AGC_B_CCK_11_CCK_1_JAGUAR	rTxAGC_B_CCK11_CCK1_JAguar
+#define REG_TX_AGC_B_CCK_1_55_MCS32	rTxAGC_B_CCK1_55_Mcs32
+#define REG_TX_AGC_B_MCS11_MCS8_JAGUAR	rTxAGC_B_MCS11_MCS8_JAguar
+#define REG_TX_AGC_B_MCS15_MCS12_JAGUAR	rTxAGC_B_MCS15_MCS12_JAguar
+#define REG_TX_AGC_B_MCS19_MCS16_JAGUAR	rTxAGC_B_MCS19_MCS16_JAguar
+#define REG_TX_AGC_B_MCS23_MCS20_JAGUAR	rTxAGC_B_MCS23_MCS20_JAguar
+#define REG_TX_AGC_B_MCS3_MCS0_JAGUAR	rTxAGC_B_MCS3_MCS0_JAguar
+#define REG_TX_AGC_B_MCS7_MCS4_JAGUAR	rTxAGC_B_MCS7_MCS4_JAguar
+#define REG_TX_AGC_B_MCS03_MCS00	rTxAGC_B_Mcs03_Mcs00
+#define REG_TX_AGC_B_MCS07_MCS04	rTxAGC_B_Mcs07_Mcs04
+#define REG_TX_AGC_B_MCS11_MCS08	rTxAGC_B_Mcs11_Mcs08
+#define REG_TX_AGC_B_MCS15_MCS12	rTxAGC_B_Mcs15_Mcs12
+#define REG_TX_AGC_B_NSS1_INDEX3_NSS1_INDEX0_JAGUAR	rTxAGC_B_Nss1Index3_Nss1Index0_JAguar
+#define REG_TX_AGC_B_NSS1_INDEX7_NSS1_INDEX4_JAGUAR	rTxAGC_B_Nss1Index7_Nss1Index4_JAguar
+#define REG_TX_AGC_B_NSS2_INDEX1_NSS1_INDEX8_JAGUAR	rTxAGC_B_Nss2Index1_Nss1Index8_JAguar
+#define REG_TX_AGC_B_NSS2_INDEX5_NSS2_INDEX2_JAGUAR	rTxAGC_B_Nss2Index5_Nss2Index2_JAguar
+#define REG_TX_AGC_B_NSS2_INDEX9_NSS2_INDEX6_JAGUAR	rTxAGC_B_Nss2Index9_Nss2Index6_JAguar
+#define REG_TX_AGC_B_NSS3_INDEX3_NSS3_INDEX0_JAGUAR	rTxAGC_B_Nss3Index3_Nss3Index0_JAguar
+#define REG_TX_AGC_B_NSS3_INDEX7_NSS3_INDEX4_JAGUAR	rTxAGC_B_Nss3Index7_Nss3Index4_JAguar
+#define REG_TX_AGC_B_NSS3_INDEX9_NSS3_INDEX8_JAGUAR	rTxAGC_B_Nss3Index9_Nss3Index8_JAguar
+#define REG_TX_AGC_B_OFDM18_OFDM6_JAGUAR	rTxAGC_B_Ofdm18_Ofdm6_JAguar
+#define REG_TX_AGC_B_OFDM54_OFDM24_JAGUAR	rTxAGC_B_Ofdm54_Ofdm24_JAguar
+#define REG_TX_AGC_B_RATE18_06	rTxAGC_B_Rate18_06
+#define REG_TX_AGC_B_RATE54_24	rTxAGC_B_Rate54_24
+#define REG_TX_AGC_C_CCK_11_CCK_1_JAGUAR	rTxAGC_C_CCK11_CCK1_JAguar
+#define REG_TX_AGC_C_MCS11_MCS8_JAGUAR	rTxAGC_C_MCS11_MCS8_JAguar
+#define REG_TX_AGC_C_MCS15_MCS12_JAGUAR	rTxAGC_C_MCS15_MCS12_JAguar
+#define REG_TX_AGC_C_MCS19_MCS16_JAGUAR	rTxAGC_C_MCS19_MCS16_JAguar
+#define REG_TX_AGC_C_MCS23_MCS20_JAGUAR	rTxAGC_C_MCS23_MCS20_JAguar
+#define REG_TX_AGC_C_MCS3_MCS0_JAGUAR	rTxAGC_C_MCS3_MCS0_JAguar
+#define REG_TX_AGC_C_MCS7_MCS4_JAGUAR	rTxAGC_C_MCS7_MCS4_JAguar
+#define REG_TX_AGC_C_NSS1_INDEX3_NSS1_INDEX0_JAGUAR	rTxAGC_C_Nss1Index3_Nss1Index0_JAguar
+#define REG_TX_AGC_C_NSS1_INDEX7_NSS1_INDEX4_JAGUAR	rTxAGC_C_Nss1Index7_Nss1Index4_JAguar
+#define REG_TX_AGC_C_NSS2_INDEX1_NSS1_INDEX8_JAGUAR	rTxAGC_C_Nss2Index1_Nss1Index8_JAguar
+#define REG_TX_AGC_C_NSS2_INDEX5_NSS2_INDEX2_JAGUAR	rTxAGC_C_Nss2Index5_Nss2Index2_JAguar
+#define REG_TX_AGC_C_NSS2_INDEX9_NSS2_INDEX6_JAGUAR	rTxAGC_C_Nss2Index9_Nss2Index6_JAguar
+#define REG_TX_AGC_C_NSS3_INDEX3_NSS3_INDEX0_JAGUAR	rTxAGC_C_Nss3Index3_Nss3Index0_JAguar
+#define REG_TX_AGC_C_NSS3_INDEX7_NSS3_INDEX4_JAGUAR	rTxAGC_C_Nss3Index7_Nss3Index4_JAguar
+#define REG_TX_AGC_C_NSS3_INDEX9_NSS3_INDEX8_JAGUAR	rTxAGC_C_Nss3Index9_Nss3Index8_JAguar
+#define REG_TX_AGC_C_OFDM18_OFDM6_JAGUAR	rTxAGC_C_Ofdm18_Ofdm6_JAguar
+#define REG_TX_AGC_C_OFDM54_OFDM24_JAGUAR	rTxAGC_C_Ofdm54_Ofdm24_JAguar
+#define REG_TX_AGC_D_CCK_11_CCK_1_JAGUAR	rTxAGC_D_CCK11_CCK1_JAguar
+#define REG_TX_AGC_D_MCS11_MCS8_JAGUAR	rTxAGC_D_MCS11_MCS8_JAguar
+#define REG_TX_AGC_D_MCS15_MCS12_JAGUAR	rTxAGC_D_MCS15_MCS12_JAguar
+#define REG_TX_AGC_D_MCS19_MCS16_JAGUAR	rTxAGC_D_MCS19_MCS16_JAguar
+#define REG_TX_AGC_D_MCS23_MCS20_JAGUAR	rTxAGC_D_MCS23_MCS20_JAguar
+#define REG_TX_AGC_D_MCS3_MCS0_JAGUAR	rTxAGC_D_MCS3_MCS0_JAguar
+#define REG_TX_AGC_D_MCS7_MCS4_JAGUAR	rTxAGC_D_MCS7_MCS4_JAguar
+#define REG_TX_AGC_D_NSS1_INDEX3_NSS1_INDEX0_JAGUAR	rTxAGC_D_Nss1Index3_Nss1Index0_JAguar
+#define REG_TX_AGC_D_NSS1_INDEX7_NSS1_INDEX4_JAGUAR	rTxAGC_D_Nss1Index7_Nss1Index4_JAguar
+#define REG_TX_AGC_D_NSS2_INDEX1_NSS1_INDEX8_JAGUAR	rTxAGC_D_Nss2Index1_Nss1Index8_JAguar
+#define REG_TX_AGC_D_NSS2_INDEX5_NSS2_INDEX2_JAGUAR	rTxAGC_D_Nss2Index5_Nss2Index2_JAguar
+#define REG_TX_AGC_D_NSS2_INDEX9_NSS2_INDEX6_JAGUAR	rTxAGC_D_Nss2Index9_Nss2Index6_JAguar
+#define REG_TX_AGC_D_NSS3_INDEX3_NSS3_INDEX0_JAGUAR	rTxAGC_D_Nss3Index3_Nss3Index0_JAguar
+#define REG_TX_AGC_D_NSS3_INDEX7_NSS3_INDEX4_JAGUAR	rTxAGC_D_Nss3Index7_Nss3Index4_JAguar
+#define REG_TX_AGC_D_NSS3_INDEX9_NSS3_INDEX8_JAGUAR	rTxAGC_D_Nss3Index9_Nss3Index8_JAguar
+#define REG_TX_AGC_D_OFDM18_OFDM6_JAGUAR	rTxAGC_D_Ofdm18_Ofdm6_JAguar
+#define REG_TX_AGC_D_OFDM54_OFDM24_JAGUAR	rTxAGC_D_Ofdm54_Ofdm24_JAguar
+#define REG_TX_PATH_JAGUAR	rTxPath_Jaguar
+#define REG_TX_CCK_BBON	rTx_CCK_BBON
+#define REG_TX_CCK_RFON	rTx_CCK_RFON
+#define REG_TX_IQK	rTx_IQK
+#define REG_TX_IQK_PI_A	rTx_IQK_PI_A
+#define REG_TX_IQK_PI_B	rTx_IQK_PI_B
+#define REG_TX_IQK_TONE_A	rTx_IQK_Tone_A
+#define REG_TX_IQK_TONE_B	rTx_IQK_Tone_B
+#define REG_TX_OFDM_BBON	rTx_OFDM_BBON
+#define REG_TX_OFDM_RFON	rTx_OFDM_RFON
+#define REG_TX_POWER_AFTER_IQK_A	rTx_Power_After_IQK_A
+#define REG_TX_POWER_AFTER_IQK_B	rTx_Power_After_IQK_B
+#define REG_TX_POWER_BEFORE_IQK_A	rTx_Power_Before_IQK_A
+#define REG_TX_POWER_BEFORE_IQK_B	rTx_Power_Before_IQK_B
+#define REG_TX_TO_RX	rTx_To_Rx
+#define REG_TX_TO_TX	rTx_To_Tx
+#define REG_APK	rAPK
+#define REG_ANTSEL_SW_JAGUAR	r_ANTSEL_SW_Jaguar
+
+
+
+#define rf_welut_jaguar	RF_WeLut_Jaguar
+#define rf_mode_table_addr	RF_ModeTableAddr
+#define rf_mode_table_data0	RF_ModeTableData0
+#define rf_mode_table_data1	RF_ModeTableData1
+
+
+
+
+
+
+#define RX_SMOOTH_FACTOR	Rx_Smooth_Factor
+
+#endif /* __HAL_DATA_H__ */
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/include/hal_gspi.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/hal_gspi.h
--- linux-5.6.3/3rdparty/rtl8821ce/include/hal_gspi.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/hal_gspi.h	2020-04-10 16:35:06.847661515 +0300
@@ -0,0 +1,26 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#ifndef __HAL_GSPI_H_
+#define __HAL_GSPI_H_
+
+#define ffaddr2deviceId(pdvobj, addr)	(pdvobj->Queue2Pipe[addr])
+
+u8 rtw_hal_gspi_max_txoqt_free_space(_adapter *padapter);
+u8 rtw_hal_gspi_query_tx_freepage(_adapter *padapter, u8 PageIdx, u8 RequiredPageNum);
+void rtw_hal_gspi_update_tx_freepage(_adapter *padapter, u8 PageIdx, u8 RequiredPageNum);
+void rtw_hal_set_gspi_tx_max_length(PADAPTER padapter, u8 numHQ, u8 numNQ, u8 numLQ, u8 numPubQ);
+u32 rtw_hal_get_gspi_tx_max_length(PADAPTER padapter, u8 queue_idx);
+
+#endif
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/include/hal_ic_cfg.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/hal_ic_cfg.h
--- linux-5.6.3/3rdparty/rtl8821ce/include/hal_ic_cfg.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/hal_ic_cfg.h	2020-04-10 16:35:06.847661515 +0300
@@ -0,0 +1,282 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#ifndef __HAL_IC_CFG_H__
+#define __HAL_IC_CFG_H__
+
+#define RTL8188E_SUPPORT				0
+#define RTL8812A_SUPPORT				0
+#define RTL8821A_SUPPORT				0
+#define RTL8723B_SUPPORT				0
+#define RTL8723D_SUPPORT				0
+#define RTL8192E_SUPPORT				0
+#define RTL8192F_SUPPORT				0
+#define RTL8814A_SUPPORT				0
+#define RTL8195A_SUPPORT				0
+#define RTL8197F_SUPPORT				0
+#define RTL8703B_SUPPORT				0
+#define RTL8188F_SUPPORT				0
+#define RTL8822B_SUPPORT				0
+#define RTL8821B_SUPPORT				0
+#define RTL8821C_SUPPORT				0
+#define RTL8710B_SUPPORT				0
+#define RTL8814B_SUPPORT				0
+#define RTL8824B_SUPPORT				0
+#define RTL8198F_SUPPORT				0
+#define RTL8195B_SUPPORT				0
+#define RTL8822C_SUPPORT				0
+/*#if (RTL8188E_SUPPORT==1)*/
+#define RATE_ADAPTIVE_SUPPORT			0
+#define POWER_TRAINING_ACTIVE			0
+
+#ifdef CONFIG_MULTIDRV
+#endif
+
+#ifdef CONFIG_RTL8188E
+	#undef RTL8188E_SUPPORT
+	#undef RATE_ADAPTIVE_SUPPORT
+	#undef POWER_TRAINING_ACTIVE
+
+	#define RTL8188E_SUPPORT				1
+	#define RATE_ADAPTIVE_SUPPORT			1
+	#define POWER_TRAINING_ACTIVE			1
+#endif
+
+#ifdef CONFIG_RTL8812A
+	#undef RTL8812A_SUPPORT
+	#define RTL8812A_SUPPORT				1
+	#ifndef CONFIG_FW_C2H_PKT
+		#define CONFIG_FW_C2H_PKT
+	#endif
+#endif
+
+#ifdef CONFIG_RTL8821A
+	#undef RTL8821A_SUPPORT
+	#define RTL8821A_SUPPORT				1
+	#ifndef CONFIG_FW_C2H_PKT
+		#define CONFIG_FW_C2H_PKT
+	#endif
+#endif
+
+#ifdef CONFIG_RTL8192E
+	#undef RTL8192E_SUPPORT
+	#define RTL8192E_SUPPORT				1
+	#ifndef CONFIG_FW_C2H_PKT
+		#define CONFIG_FW_C2H_PKT
+	#endif
+#endif
+
+#ifdef CONFIG_RTL8192F
+	#undef RTL8192F_SUPPORT
+	#define RTL8192F_SUPPORT				1
+	#ifndef CONFIG_FW_C2H_PKT
+		#define CONFIG_FW_C2H_PKT
+	#endif
+	#ifndef CONFIG_RTW_MAC_HIDDEN_RPT
+		#define CONFIG_RTW_MAC_HIDDEN_RPT
+	#endif
+	/*#define CONFIG_AMPDU_PRETX_CD*/
+	/*#define DBG_LA_MODE*/
+#endif
+
+#ifdef CONFIG_RTL8723B
+	#undef RTL8723B_SUPPORT
+	#define RTL8723B_SUPPORT				1
+	#ifndef CONFIG_FW_C2H_PKT
+		#define CONFIG_FW_C2H_PKT
+	#endif
+#endif
+
+#ifdef CONFIG_RTL8723D
+	#undef RTL8723D_SUPPORT
+	#define RTL8723D_SUPPORT				1
+	#ifndef CONFIG_FW_C2H_PKT
+		#define CONFIG_FW_C2H_PKT
+	#endif
+	#ifndef CONFIG_RTW_MAC_HIDDEN_RPT
+		#define CONFIG_RTW_MAC_HIDDEN_RPT
+	#endif
+	#ifndef CONFIG_RTW_CUSTOMER_STR
+		#define CONFIG_RTW_CUSTOMER_STR
+	#endif
+#endif
+
+#ifdef CONFIG_RTL8814A
+	#undef RTL8814A_SUPPORT
+	#define RTL8814A_SUPPORT				1
+	#ifndef CONFIG_FW_C2H_PKT
+		#define CONFIG_FW_C2H_PKT
+	#endif
+	#define CONFIG_FW_CORRECT_BCN
+#endif
+
+#ifdef CONFIG_RTL8703B
+	#undef RTL8703B_SUPPORT
+	#define RTL8703B_SUPPORT				1
+	#ifndef CONFIG_FW_C2H_PKT
+		#define CONFIG_FW_C2H_PKT
+	#endif
+	#ifndef CONFIG_RTW_MAC_HIDDEN_RPT
+		#define CONFIG_RTW_MAC_HIDDEN_RPT
+	#endif
+#endif
+
+#ifdef CONFIG_RTL8188F
+	#undef RTL8188F_SUPPORT
+	#define RTL8188F_SUPPORT				1
+	#ifndef CONFIG_FW_C2H_PKT
+		#define CONFIG_FW_C2H_PKT
+	#endif
+	#ifndef CONFIG_RTW_MAC_HIDDEN_RPT
+		#define CONFIG_RTW_MAC_HIDDEN_RPT
+	#endif
+	#ifndef CONFIG_RTW_CUSTOMER_STR
+		#define CONFIG_RTW_CUSTOMER_STR
+	#endif
+#endif
+
+#ifdef CONFIG_RTL8188GTV
+	#undef RTL8188F_SUPPORT
+	#define RTL8188F_SUPPORT				1
+	#ifndef CONFIG_FW_C2H_PKT
+		#define CONFIG_FW_C2H_PKT
+	#endif
+	#ifndef CONFIG_RTW_MAC_HIDDEN_RPT
+		#define CONFIG_RTW_MAC_HIDDEN_RPT
+	#endif
+	#ifndef CONFIG_RTW_CUSTOMER_STR
+		#define CONFIG_RTW_CUSTOMER_STR
+	#endif
+#endif
+
+#ifdef CONFIG_RTL8822B
+	#undef RTL8822B_SUPPORT
+	#define RTL8822B_SUPPORT				1
+	#ifndef CONFIG_FW_C2H_PKT
+		#define CONFIG_FW_C2H_PKT
+	#endif /* CONFIG_FW_C2H_PKT */
+	#define RTW_TX_PA_BIAS	/* Adjust TX PA Bias from eFuse */
+	#define CONFIG_DFS	/* Enable 5G band 2&3 channel */
+
+	#ifdef CONFIG_WOWLAN
+		#define CONFIG_GTK_OL
+		/*#define CONFIG_ARP_KEEP_ALIVE*/
+
+		#ifdef CONFIG_GPIO_WAKEUP
+			#ifndef WAKEUP_GPIO_IDX
+				#define WAKEUP_GPIO_IDX	6	/* WIFI Chip Side */
+			#endif /* !WAKEUP_GPIO_IDX */
+		#endif /* CONFIG_GPIO_WAKEUP */
+	#endif /* CONFIG_WOWLAN */
+
+	#ifdef CONFIG_CONCURRENT_MODE
+		#define CONFIG_AP_PORT_SWAP
+		#define CONFIG_FW_MULTI_PORT_SUPPORT
+	#endif /* CONFIG_CONCURRENT_MODE */
+
+	/*
+	 * Beamforming related definition
+	 */
+	/* Beamforming mechanism is on driver not phydm, always disable it */
+	#define BEAMFORMING_SUPPORT				0
+	/* Only support new beamforming mechanism */
+	#ifdef CONFIG_BEAMFORMING
+		#define RTW_BEAMFORMING_VERSION_2
+	#endif /* CONFIG_BEAMFORMING */
+
+	#ifndef CONFIG_RTW_MAC_HIDDEN_RPT
+		#define CONFIG_RTW_MAC_HIDDEN_RPT
+	#endif /* CONFIG_RTW_MAC_HIDDEN_RPT */
+
+	#ifndef DBG_RX_DFRAME_RAW_DATA
+		#define DBG_RX_DFRAME_RAW_DATA
+	#endif /* DBG_RX_DFRAME_RAW_DATA */
+
+	#ifndef RTW_IQK_FW_OFFLOAD
+		#define RTW_IQK_FW_OFFLOAD
+	#endif /* RTW_IQK_FW_OFFLOAD */
+	#define CONFIG_ADVANCE_OTA
+
+	#ifdef CONFIG_MCC_MODE
+		#define CONFIG_MCC_MODE_V2
+	#endif /* CONFIG_MCC_MODE */
+
+	#if defined(CONFIG_TDLS) && defined(CONFIG_TDLS_CH_SW)
+		#define CONFIG_TDLS_CH_SW_V2
+	#endif
+
+	#ifndef RTW_CHANNEL_SWITCH_OFFLOAD
+		#ifdef CONFIG_TDLS_CH_SW_V2
+			#define RTW_CHANNEL_SWITCH_OFFLOAD
+		#endif
+	#endif /* RTW_CHANNEL_SWITCH_OFFLOAD */
+
+	#if defined(CONFIG_RTW_MESH) && !defined(RTW_PER_CMD_SUPPORT_FW)
+		/* Supported since fw v22.1 */
+		#define RTW_PER_CMD_SUPPORT_FW
+	#endif /* RTW_PER_CMD_SUPPORT_FW */
+	#define CONFIG_SUPPORT_FIFO_DUMP
+	#define CONFIG_HW_P0_TSF_SYNC
+	#define CONFIG_BCN_RECV_TIME
+#endif /* CONFIG_RTL8822B */
+
+#ifdef CONFIG_RTL8821C
+	#undef RTL8821C_SUPPORT
+	#define RTL8821C_SUPPORT				1
+	#define CONFIG_DFS	/* Enable 5G band 2&3 channel */
+	#ifndef CONFIG_FW_C2H_PKT
+		#define CONFIG_FW_C2H_PKT
+	#endif
+	#ifdef CONFIG_NO_FW
+		#ifdef CONFIG_RTW_MAC_HIDDEN_RPT
+			#undef CONFIG_RTW_MAC_HIDDEN_RPT
+		#endif
+	#else
+		#ifndef CONFIG_RTW_MAC_HIDDEN_RPT
+			#define CONFIG_RTW_MAC_HIDDEN_RPT
+		#endif
+	#endif
+	#define LOAD_FW_HEADER_FROM_DRIVER
+	#define CONFIG_PHY_CAPABILITY_QUERY
+	#ifdef CONFIG_CONCURRENT_MODE
+	#define CONFIG_AP_PORT_SWAP
+	#define CONFIG_FW_MULTI_PORT_SUPPORT
+	#endif
+	#define CONFIG_SUPPORT_FIFO_DUMP
+	#ifndef RTW_IQK_FW_OFFLOAD
+		#define RTW_IQK_FW_OFFLOAD
+	#endif /* RTW_IQK_FW_OFFLOAD */
+	/*#define CONFIG_AMPDU_PRETX_CD*/
+	/*#define DBG_PRE_TX_HANG*/
+
+	/* Beamforming related definition */
+	/* Beamforming mechanism is on driver not phydm, always disable it */
+	#define BEAMFORMING_SUPPORT				0
+	/* Only support new beamforming mechanism */
+	#ifdef CONFIG_BEAMFORMING
+		#define RTW_BEAMFORMING_VERSION_2
+	#endif /* CONFIG_BEAMFORMING */
+	#define CONFIG_HW_P0_TSF_SYNC
+	#define CONFIG_BCN_RECV_TIME
+#endif /*CONFIG_RTL8821C*/
+
+#ifdef CONFIG_RTL8710B
+	#undef RTL8710B_SUPPORT
+	#define RTL8710B_SUPPORT				1
+	#ifndef CONFIG_FW_C2H_PKT
+		#define CONFIG_FW_C2H_PKT
+	#endif
+#endif
+
+#endif /*__HAL_IC_CFG_H__*/
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/include/hal_intf.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/hal_intf.h
--- linux-5.6.3/3rdparty/rtl8821ce/include/hal_intf.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/hal_intf.h	2020-04-10 16:35:06.847661515 +0300
@@ -0,0 +1,838 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#ifndef __HAL_INTF_H__
+#define __HAL_INTF_H__
+
+
+enum RTL871X_HCI_TYPE {
+	RTW_PCIE	= BIT0,
+	RTW_USB	= BIT1,
+	RTW_SDIO	= BIT2,
+	RTW_GSPI	= BIT3,
+};
+
+enum _CHIP_TYPE {
+
+	NULL_CHIP_TYPE,
+	RTL8188E,
+	RTL8192E,
+	RTL8812,
+	RTL8821, /* RTL8811 */
+	RTL8723B,
+	RTL8814A,
+	RTL8703B,
+	RTL8188F,
+	RTL8188GTV,
+	RTL8822B,
+	RTL8723D,
+	RTL8821C,
+	RTL8710B,
+	RTL8192F,
+	MAX_CHIP_TYPE
+};
+
+#ifdef RTW_HALMAC
+enum fw_mem {
+	FW_EMEM,
+	FW_IMEM,
+	FW_DMEM,
+};
+#endif
+
+extern const u32 _chip_type_to_odm_ic_type[];
+#define chip_type_to_odm_ic_type(chip_type) (((chip_type) >= MAX_CHIP_TYPE) ? _chip_type_to_odm_ic_type[MAX_CHIP_TYPE] : _chip_type_to_odm_ic_type[(chip_type)])
+
+typedef enum _HAL_HW_TIMER_TYPE {
+	HAL_TIMER_NONE = 0,
+	HAL_TIMER_TXBF = 1,
+	HAL_TIMER_EARLYMODE = 2,
+} HAL_HW_TIMER_TYPE, *PHAL_HW_TIMER_TYPE;
+
+
+typedef enum _HW_VARIABLES {
+	HW_VAR_MEDIA_STATUS,
+	HW_VAR_SET_OPMODE,
+	HW_VAR_MAC_ADDR,
+	HW_VAR_BSSID,
+	HW_VAR_INIT_RTS_RATE,
+	HW_VAR_BASIC_RATE,
+	HW_VAR_TXPAUSE,
+	HW_VAR_BCN_FUNC,
+	HW_VAR_BCN_CTRL_ADDR,
+	HW_VAR_CORRECT_TSF,
+	HW_VAR_RCR,
+	HW_VAR_MLME_DISCONNECT,
+	HW_VAR_MLME_SITESURVEY,
+	HW_VAR_MLME_JOIN,
+	HW_VAR_ON_RCR_AM,
+	HW_VAR_OFF_RCR_AM,
+	HW_VAR_BEACON_INTERVAL,
+	HW_VAR_SLOT_TIME,
+	HW_VAR_RESP_SIFS,
+	HW_VAR_ACK_PREAMBLE,
+	HW_VAR_SEC_CFG,
+	HW_VAR_SEC_DK_CFG,
+	HW_VAR_BCN_VALID,
+	HW_VAR_RF_TYPE,
+	HW_VAR_FREECNT,
+
+	/* PHYDM odm->SupportAbility */
+	HW_VAR_CAM_EMPTY_ENTRY,
+	HW_VAR_CAM_INVALID_ALL,
+	HW_VAR_AC_PARAM_VO,
+	HW_VAR_AC_PARAM_VI,
+	HW_VAR_AC_PARAM_BE,
+	HW_VAR_AC_PARAM_BK,
+	HW_VAR_ACM_CTRL,
+#ifdef CONFIG_WMMPS_STA
+	HW_VAR_UAPSD_TID,
+#endif /* CONFIG_WMMPS_STA */
+	HW_VAR_AMPDU_MIN_SPACE,
+#ifdef CONFIG_80211N_HT
+	HW_VAR_AMPDU_FACTOR,
+#endif /* CONFIG_80211N_HT */
+	HW_VAR_RXDMA_AGG_PG_TH,
+	HW_VAR_SET_RPWM,
+	HW_VAR_CPWM,
+	HW_VAR_H2C_FW_PWRMODE,
+	HW_VAR_H2C_PS_TUNE_PARAM,
+	HW_VAR_H2C_FW_JOINBSSRPT,
+	HW_VAR_FWLPS_RF_ON,
+	HW_VAR_H2C_FW_P2P_PS_OFFLOAD,
+#ifdef CONFIG_LPS_POFF
+	HW_VAR_LPS_POFF_INIT,
+	HW_VAR_LPS_POFF_DEINIT,
+	HW_VAR_LPS_POFF_SET_MODE,
+	HW_VAR_LPS_POFF_WOW_EN,
+#endif
+#ifdef CONFIG_LPS_PG
+	HW_VAR_LPS_PG_HANDLE,
+#endif
+	HW_VAR_TRIGGER_GPIO_0,
+	HW_VAR_BT_SET_COEXIST,
+	HW_VAR_BT_ISSUE_DELBA,
+	HW_VAR_SWITCH_EPHY_WoWLAN,
+	HW_VAR_EFUSE_USAGE,
+	HW_VAR_EFUSE_BYTES,
+	HW_VAR_EFUSE_BT_USAGE,
+	HW_VAR_EFUSE_BT_BYTES,
+	HW_VAR_FIFO_CLEARN_UP,
+	HW_VAR_RESTORE_HW_SEQ,
+	HW_VAR_CHECK_TXBUF,
+	HW_VAR_PCIE_STOP_TX_DMA,
+	HW_VAR_APFM_ON_MAC, /* Auto FSM to Turn On, include clock, isolation, power control for MAC only */
+	HW_VAR_HCI_SUS_STATE,
+	/* The valid upper nav range for the HW updating, if the true value is larger than the upper range, the HW won't update it. */
+	/* Unit in microsecond. 0 means disable this function. */
+#if defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN)
+	HW_VAR_WOWLAN,
+	HW_VAR_WAKEUP_REASON,
+#endif
+	HW_VAR_RPWM_TOG,
+#ifdef CONFIG_GPIO_WAKEUP
+	HW_SET_GPIO_WL_CTRL,
+#endif
+	HW_VAR_SYS_CLKR,
+	HW_VAR_NAV_UPPER,
+	HW_VAR_RPT_TIMER_SETTING,
+	HW_VAR_TX_RPT_MAX_MACID,
+	HW_VAR_CHK_HI_QUEUE_EMPTY,
+	HW_VAR_CHK_MGQ_CPU_EMPTY,
+	HW_VAR_DL_BCN_SEL,
+	HW_VAR_AMPDU_MAX_TIME,
+	HW_VAR_WIRELESS_MODE,
+	HW_VAR_USB_MODE,
+	HW_VAR_PORT_SWITCH,
+	HW_VAR_PORT_CFG,
+	HW_VAR_DO_IQK,
+	HW_VAR_DM_IN_LPS_LCLK,/*flag CONFIG_LPS_LCLK_WD_TIMER*/
+	HW_VAR_SET_REQ_FW_PS,
+	HW_VAR_FW_PS_STATE,
+	HW_VAR_SOUNDING_ENTER,
+	HW_VAR_SOUNDING_LEAVE,
+	HW_VAR_SOUNDING_RATE,
+	HW_VAR_SOUNDING_STATUS,
+	HW_VAR_SOUNDING_FW_NDPA,
+	HW_VAR_SOUNDING_CLK,
+	HW_VAR_SOUNDING_SET_GID_TABLE,
+	HW_VAR_SOUNDING_CSI_REPORT,
+	/*Add by YuChen for TXBF HW timer*/
+	HW_VAR_HW_REG_TIMER_INIT,
+	HW_VAR_HW_REG_TIMER_RESTART,
+	HW_VAR_HW_REG_TIMER_START,
+	HW_VAR_HW_REG_TIMER_STOP,
+	/*Add by YuChen for TXBF HW timer*/
+	HW_VAR_DL_RSVD_PAGE,
+	HW_VAR_MACID_LINK,
+	HW_VAR_MACID_NOLINK,
+	HW_VAR_DUMP_MAC_QUEUE_INFO,
+	HW_VAR_ASIX_IOT,
+#ifdef CONFIG_MBSSID_CAM
+	HW_VAR_MBSSID_CAM_WRITE,
+	HW_VAR_MBSSID_CAM_CLEAR,
+	HW_VAR_RCR_MBSSID_EN,
+#endif
+	HW_VAR_EN_HW_UPDATE_TSF,
+	HW_VAR_CH_SW_NEED_TO_TAKE_CARE_IQK_INFO,
+	HW_VAR_CH_SW_IQK_INFO_BACKUP,
+	HW_VAR_CH_SW_IQK_INFO_RESTORE,
+
+	HW_VAR_DBI,
+	HW_VAR_MDIO,
+	HW_VAR_L1OFF_CAPABILITY,
+	HW_VAR_L1OFF_NIC_SUPPORT,
+#ifdef CONFIG_TDLS
+#ifdef CONFIG_TDLS_CH_SW
+	HW_VAR_TDLS_BCN_EARLY_C2H_RPT,
+#endif
+#endif
+	HW_VAR_DUMP_MAC_TXFIFO,
+	HW_VAR_PWR_CMD,
+#ifdef CONFIG_FW_HANDLE_TXBCN
+	HW_VAR_BCN_HEAD_SEL,
+#endif
+	HW_VAR_SET_SOML_PARAM,
+	HW_VAR_ENABLE_RX_BAR,
+	HW_VAR_TSF_AUTO_SYNC,
+	HW_VAR_LPS_STATE_CHK,
+} HW_VARIABLES;
+
+typedef enum _HAL_DEF_VARIABLE {
+	HAL_DEF_UNDERCORATEDSMOOTHEDPWDB,
+	HAL_DEF_IS_SUPPORT_ANT_DIV,
+	HAL_DEF_DRVINFO_SZ,
+	HAL_DEF_MAX_RECVBUF_SZ,
+	HAL_DEF_RX_PACKET_OFFSET,
+	HAL_DEF_RX_DMA_SZ_WOW,
+	HAL_DEF_RX_DMA_SZ,
+	HAL_DEF_RX_PAGE_SIZE,
+	HAL_DEF_DBG_DUMP_RXPKT,/* for dbg */
+	HAL_DEF_RA_DECISION_RATE,
+	HAL_DEF_RA_SGI,
+	HAL_DEF_PT_PWR_STATUS,
+	HAL_DEF_TX_LDPC,				/* LDPC support */
+	HAL_DEF_RX_LDPC,				/* LDPC support */
+	HAL_DEF_TX_STBC,				/* TX STBC support */
+	HAL_DEF_RX_STBC,				/* RX STBC support */
+	HAL_DEF_EXPLICIT_BEAMFORMER,/* Explicit  Compressed Steering Capable */
+	HAL_DEF_EXPLICIT_BEAMFORMEE,/* Explicit Compressed Beamforming Feedback Capable */
+	HAL_DEF_VHT_MU_BEAMFORMER,	/* VHT MU Beamformer support */
+	HAL_DEF_VHT_MU_BEAMFORMEE,	/* VHT MU Beamformee support */
+	HAL_DEF_BEAMFORMER_CAP,
+	HAL_DEF_BEAMFORMEE_CAP,
+	HW_VAR_MAX_RX_AMPDU_FACTOR,
+	HW_DEF_RA_INFO_DUMP,
+	HAL_DEF_DBG_DUMP_TXPKT,
+
+	HAL_DEF_TX_PAGE_SIZE,
+	HAL_DEF_TX_PAGE_BOUNDARY,
+	HAL_DEF_TX_PAGE_BOUNDARY_WOWLAN,
+	HAL_DEF_ANT_DETECT,/* to do for 8723a */
+	HAL_DEF_PCI_SUUPORT_L1_BACKDOOR, /* Determine if the L1 Backdoor setting is turned on. */
+	HAL_DEF_PCI_AMD_L1_SUPPORT,
+	HAL_DEF_PCI_ASPM_OSC, /* Support for ASPM OSC, added by Roger, 2013.03.27. */
+	HAL_DEF_EFUSE_USAGE,	/* Get current EFUSE utilization. 2008.12.19. Added by Roger. */
+	HAL_DEF_EFUSE_BYTES,
+	HW_VAR_BEST_AMPDU_DENSITY,
+} HAL_DEF_VARIABLE;
+
+typedef enum _HAL_ODM_VARIABLE {
+	HAL_ODM_STA_INFO,
+	HAL_ODM_P2P_STATE,
+	HAL_ODM_WIFI_DISPLAY_STATE,
+	HAL_ODM_REGULATION,
+	HAL_ODM_INITIAL_GAIN,
+	HAL_ODM_RX_INFO_DUMP,
+	HAL_ODM_RX_Dframe_INFO,
+#ifdef CONFIG_ANTENNA_DIVERSITY
+	HAL_ODM_ANTDIV_SELECT
+#endif
+} HAL_ODM_VARIABLE;
+
+typedef enum _HAL_INTF_PS_FUNC {
+	HAL_USB_SELECT_SUSPEND,
+	HAL_MAX_ID,
+} HAL_INTF_PS_FUNC;
+
+typedef s32(*c2h_id_filter)(_adapter *adapter, u8 id, u8 seq, u8 plen, u8 *payload);
+
+struct txpwr_idx_comp;
+
+struct hal_ops {
+	/*** initialize section ***/
+	void	(*read_chip_version)(_adapter *padapter);
+	void	(*init_default_value)(_adapter *padapter);
+	void	(*intf_chip_configure)(_adapter *padapter);
+	u8	(*read_adapter_info)(_adapter *padapter);
+	u32(*hal_power_on)(_adapter *padapter);
+	void	(*hal_power_off)(_adapter *padapter);
+	u32(*hal_init)(_adapter *padapter);
+	u32(*hal_deinit)(_adapter *padapter);
+	void	(*dm_init)(_adapter *padapter);
+	void	(*dm_deinit)(_adapter *padapter);
+
+	/*** xmit section ***/
+	s32(*init_xmit_priv)(_adapter *padapter);
+	void	(*free_xmit_priv)(_adapter *padapter);
+	s32(*hal_xmit)(_adapter *padapter, struct xmit_frame *pxmitframe);
+	/*
+	 * mgnt_xmit should be implemented to run in interrupt context
+	 */
+	s32(*mgnt_xmit)(_adapter *padapter, struct xmit_frame *pmgntframe);
+	s32(*hal_xmitframe_enqueue)(_adapter *padapter, struct xmit_frame *pxmitframe);
+#ifdef CONFIG_XMIT_THREAD_MODE
+	s32(*xmit_thread_handler)(_adapter *padapter);
+#endif
+	void	(*run_thread)(_adapter *padapter);
+	void	(*cancel_thread)(_adapter *padapter);
+
+	/*** recv section ***/
+	s32(*init_recv_priv)(_adapter *padapter);
+	void	(*free_recv_priv)(_adapter *padapter);
+#ifdef CONFIG_RECV_THREAD_MODE
+	s32 (*recv_hdl)(_adapter *adapter);
+#endif
+#if defined(CONFIG_USB_HCI) || defined(CONFIG_PCI_HCI)
+	u32(*inirp_init)(_adapter *padapter);
+	u32(*inirp_deinit)(_adapter *padapter);
+#endif
+	/*** interrupt hdl section ***/
+	void	(*enable_interrupt)(_adapter *padapter);
+	void	(*disable_interrupt)(_adapter *padapter);
+	u8(*check_ips_status)(_adapter *padapter);
+#if defined(CONFIG_PCI_HCI)
+	s32(*interrupt_handler)(_adapter *padapter);
+#endif
+
+#if defined(CONFIG_USB_HCI) && defined(CONFIG_SUPPORT_USB_INT)
+	void	(*interrupt_handler)(_adapter *padapter, u16 pkt_len, u8 *pbuf);
+#endif
+
+#if defined(CONFIG_PCI_HCI)
+	void	(*irp_reset)(_adapter *padapter);
+#endif
+
+	/*** DM section ***/
+#ifdef CONFIG_RTW_SW_LED
+	void	(*InitSwLeds)(_adapter *padapter);
+	void	(*DeInitSwLeds)(_adapter *padapter);
+#endif
+	void	(*set_chnl_bw_handler)(_adapter *padapter, u8 channel, enum channel_width Bandwidth, u8 Offset40, u8 Offset80);
+
+	void	(*set_tx_power_level_handler)(_adapter *padapter, u8 channel);
+	void	(*get_tx_power_level_handler)(_adapter *padapter, s32 *powerlevel);
+
+	void (*set_tx_power_index_handler)(_adapter *padapter, u32 powerindex, enum rf_path rfpath, u8 rate);
+	u8 (*get_tx_power_index_handler)(_adapter *padapter, enum rf_path rfpath, u8 rate, u8 bandwidth, u8 channel, struct txpwr_idx_comp *tic);
+
+	void	(*hal_dm_watchdog)(_adapter *padapter);
+
+	u8	(*set_hw_reg_handler)(_adapter *padapter, u8	variable, u8 *val);
+
+	void	(*GetHwRegHandler)(_adapter *padapter, u8	variable, u8 *val);
+
+
+
+	u8 (*get_hal_def_var_handler)(_adapter *padapter, HAL_DEF_VARIABLE eVariable, PVOID pValue);
+
+	u8(*SetHalDefVarHandler)(_adapter *padapter, HAL_DEF_VARIABLE eVariable, PVOID pValue);
+
+	void	(*GetHalODMVarHandler)(_adapter *padapter, HAL_ODM_VARIABLE eVariable, PVOID pValue1, PVOID pValue2);
+	void	(*SetHalODMVarHandler)(_adapter *padapter, HAL_ODM_VARIABLE eVariable, PVOID pValue1, BOOLEAN bSet);
+
+	void	(*SetBeaconRelatedRegistersHandler)(_adapter *padapter);
+
+	u8(*interface_ps_func)(_adapter *padapter, HAL_INTF_PS_FUNC efunc_id, u8 *val);
+
+	u32(*read_bbreg)(_adapter *padapter, u32 RegAddr, u32 BitMask);
+	void	(*write_bbreg)(_adapter *padapter, u32 RegAddr, u32 BitMask, u32 Data);
+	u32 (*read_rfreg)(_adapter *padapter, enum rf_path eRFPath, u32 RegAddr, u32 BitMask);
+	void	(*write_rfreg)(_adapter *padapter, enum rf_path eRFPath, u32 RegAddr, u32 BitMask, u32 Data);
+#ifdef CONFIG_SYSON_INDIRECT_ACCESS
+	u32 (*read_syson_reg)(_adapter *padapter, u32 RegAddr, u32 BitMask);
+	void (*write_syson_reg)(_adapter *padapter, u32 RegAddr, u32 BitMask, u32 Data);
+#endif
+	void (*read_wmmedca_reg)(_adapter *padapter, u16 *vo_params, u16 *vi_params, u16 *be_params, u16 *bk_params);
+	
+#ifdef CONFIG_HOSTAPD_MLME
+	s32(*hostap_mgnt_xmit_entry)(_adapter *padapter, _pkt *pkt);
+#endif
+
+	void (*EfusePowerSwitch)(_adapter *padapter, u8 bWrite, u8 PwrState);
+	void (*BTEfusePowerSwitch)(_adapter *padapter, u8 bWrite, u8 PwrState);
+	void (*ReadEFuse)(_adapter *padapter, u8 efuseType, u16 _offset, u16 _size_byte, u8 *pbuf, BOOLEAN bPseudoTest);
+	void (*EFUSEGetEfuseDefinition)(_adapter *padapter, u8 efuseType, u8 type, void *pOut, BOOLEAN bPseudoTest);
+	u16(*EfuseGetCurrentSize)(_adapter *padapter, u8 efuseType, BOOLEAN bPseudoTest);
+	int	(*Efuse_PgPacketRead)(_adapter *padapter, u8 offset, u8 *data, BOOLEAN bPseudoTest);
+	int	(*Efuse_PgPacketWrite)(_adapter *padapter, u8 offset, u8 word_en, u8 *data, BOOLEAN bPseudoTest);
+	u8(*Efuse_WordEnableDataWrite)(_adapter *padapter, u16 efuse_addr, u8 word_en, u8 *data, BOOLEAN bPseudoTest);
+	BOOLEAN(*Efuse_PgPacketWrite_BT)(_adapter *padapter, u8 offset, u8 word_en, u8 *data, BOOLEAN bPseudoTest);
+#if defined(CONFIG_RTL8710B)
+	BOOLEAN(*efuse_indirect_read4)(_adapter *padapter, u16 regaddr, u8 *value);
+#endif
+
+#ifdef DBG_CONFIG_ERROR_DETECT
+	void (*sreset_init_value)(_adapter *padapter);
+	void (*sreset_reset_value)(_adapter *padapter);
+	void (*silentreset)(_adapter *padapter);
+	void (*sreset_xmit_status_check)(_adapter *padapter);
+	void (*sreset_linked_status_check)(_adapter *padapter);
+	u8(*sreset_get_wifi_status)(_adapter *padapter);
+	bool (*sreset_inprogress)(_adapter *padapter);
+#endif
+
+#ifdef CONFIG_IOL
+	int (*IOL_exec_cmds_sync)(_adapter *padapter, struct xmit_frame *xmit_frame, u32 max_wating_ms, u32 bndy_cnt);
+#endif
+
+	void (*hal_notch_filter)(_adapter *adapter, bool enable);
+#ifdef RTW_HALMAC
+	void (*hal_mac_c2h_handler)(_adapter *adapter, u8 *pbuf, u16 length);
+#else
+	s32(*c2h_handler)(_adapter *adapter, u8 id, u8 seq, u8 plen, u8 *payload);
+#endif
+	void (*reqtxrpt)(_adapter *padapter, u8 macid);
+	s32(*fill_h2c_cmd)(PADAPTER, u8 ElementID, u32 CmdLen, u8 *pCmdBuffer);
+	void (*fill_fake_txdesc)(PADAPTER, u8 *pDesc, u32 BufferLen,
+				 u8 IsPsPoll, u8 IsBTQosNull, u8 bDataFrame);
+	s32(*fw_dl)(_adapter *adapter, u8 wowlan);
+#ifdef RTW_HALMAC
+	s32 (*fw_mem_dl)(_adapter *adapter, enum fw_mem mem);
+#endif
+
+#if defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN) || defined(CONFIG_PCI_HCI)
+	void (*clear_interrupt)(_adapter *padapter);
+#endif
+	u8(*hal_get_tx_buff_rsvd_page_num)(_adapter *adapter, bool wowlan);
+#ifdef CONFIG_GPIO_API
+	void (*update_hisr_hsisr_ind)(PADAPTER padapter, u32 flag);
+	int (*hal_gpio_func_check)(_adapter *padapter, u8 gpio_num);
+	void (*hal_gpio_multi_func_reset)(_adapter *padapter, u8 gpio_num);
+#endif
+#ifdef CONFIG_FW_CORRECT_BCN
+	void (*fw_correct_bcn)(PADAPTER padapter);
+#endif
+
+#ifdef RTW_HALMAC
+	u8(*init_mac_register)(PADAPTER);
+	u8(*init_phy)(PADAPTER);
+#endif /* RTW_HALMAC */
+
+#ifdef CONFIG_PCI_HCI
+	void (*hal_set_l1ssbackdoor_handler)(_adapter *padapter, u8 enable);
+#endif
+
+#ifdef CONFIG_RFKILL_POLL
+	bool (*hal_radio_onoff_check)(_adapter *adapter, u8 *valid);
+#endif
+
+};
+
+typedef	enum _RT_EEPROM_TYPE {
+	EEPROM_93C46,
+	EEPROM_93C56,
+	EEPROM_BOOT_EFUSE,
+} RT_EEPROM_TYPE, *PRT_EEPROM_TYPE;
+
+
+
+#define RF_CHANGE_BY_INIT	0
+#define RF_CHANGE_BY_IPS	BIT28
+#define RF_CHANGE_BY_PS	BIT29
+#define RF_CHANGE_BY_HW	BIT30
+#define RF_CHANGE_BY_SW	BIT31
+
+typedef enum _HARDWARE_TYPE {
+	HARDWARE_TYPE_RTL8188EE,
+	HARDWARE_TYPE_RTL8188EU,
+	HARDWARE_TYPE_RTL8188ES,
+	/*	NEW_GENERATION_IC */
+	HARDWARE_TYPE_RTL8192EE,
+	HARDWARE_TYPE_RTL8192EU,
+	HARDWARE_TYPE_RTL8192ES,
+	HARDWARE_TYPE_RTL8812E,
+	HARDWARE_TYPE_RTL8812AU,
+	HARDWARE_TYPE_RTL8811AU,
+	HARDWARE_TYPE_RTL8821E,
+	HARDWARE_TYPE_RTL8821U,
+	HARDWARE_TYPE_RTL8821S,
+	HARDWARE_TYPE_RTL8723BE,
+	HARDWARE_TYPE_RTL8723BU,
+	HARDWARE_TYPE_RTL8723BS,
+	HARDWARE_TYPE_RTL8814AE,
+	HARDWARE_TYPE_RTL8814AU,
+	HARDWARE_TYPE_RTL8814AS,
+	HARDWARE_TYPE_RTL8821BE,
+	HARDWARE_TYPE_RTL8821BU,
+	HARDWARE_TYPE_RTL8821BS,
+	HARDWARE_TYPE_RTL8822BE,
+	HARDWARE_TYPE_RTL8822BU,
+	HARDWARE_TYPE_RTL8822BS,
+	HARDWARE_TYPE_RTL8703BE,
+	HARDWARE_TYPE_RTL8703BU,
+	HARDWARE_TYPE_RTL8703BS,
+	HARDWARE_TYPE_RTL8188FE,
+	HARDWARE_TYPE_RTL8188FU,
+	HARDWARE_TYPE_RTL8188FS,
+	HARDWARE_TYPE_RTL8188GTVU,
+	HARDWARE_TYPE_RTL8188GTVS,
+	HARDWARE_TYPE_RTL8723DE,
+	HARDWARE_TYPE_RTL8723DU,
+	HARDWARE_TYPE_RTL8723DS,
+	HARDWARE_TYPE_RTL8821CE,
+	HARDWARE_TYPE_RTL8821CU,
+	HARDWARE_TYPE_RTL8821CS,
+	HARDWARE_TYPE_RTL8710BU,
+	HARDWARE_TYPE_RTL8192FS,
+	HARDWARE_TYPE_RTL8192FU,
+	HARDWARE_TYPE_RTL8192FE,
+	HARDWARE_TYPE_MAX,
+} HARDWARE_TYPE;
+
+#define IS_NEW_GENERATION_IC(_Adapter)	(rtw_get_hw_type(_Adapter) >= HARDWARE_TYPE_RTL8192EE)
+/*
+ * RTL8188E Series
+ *   */
+#define IS_HARDWARE_TYPE_8188EE(_Adapter)	(rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8188EE)
+#define IS_HARDWARE_TYPE_8188EU(_Adapter)	(rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8188EU)
+#define IS_HARDWARE_TYPE_8188ES(_Adapter)	(rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8188ES)
+#define	IS_HARDWARE_TYPE_8188E(_Adapter)	\
+	(IS_HARDWARE_TYPE_8188EE(_Adapter) || IS_HARDWARE_TYPE_8188EU(_Adapter) || IS_HARDWARE_TYPE_8188ES(_Adapter))
+
+/* RTL8812 Series */
+#define IS_HARDWARE_TYPE_8812E(_Adapter)		(rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8812E)
+#define IS_HARDWARE_TYPE_8812AU(_Adapter)	(rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8812AU)
+#define IS_HARDWARE_TYPE_8812(_Adapter)			\
+	(IS_HARDWARE_TYPE_8812E(_Adapter) || IS_HARDWARE_TYPE_8812AU(_Adapter))
+
+/* RTL8821 Series */
+#define IS_HARDWARE_TYPE_8821E(_Adapter)		(rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8821E)
+#define IS_HARDWARE_TYPE_8811AU(_Adapter)		(rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8811AU)
+#define IS_HARDWARE_TYPE_8821U(_Adapter)		(rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8821U || \
+		rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8811AU)
+#define IS_HARDWARE_TYPE_8821S(_Adapter)		(rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8821S)
+#define IS_HARDWARE_TYPE_8821(_Adapter)			\
+	(IS_HARDWARE_TYPE_8821E(_Adapter) || IS_HARDWARE_TYPE_8821U(_Adapter) || IS_HARDWARE_TYPE_8821S(_Adapter))
+
+#define IS_HARDWARE_TYPE_JAGUAR(_Adapter)		\
+	(IS_HARDWARE_TYPE_8812(_Adapter) || IS_HARDWARE_TYPE_8821(_Adapter))
+
+/* RTL8192E Series */
+#define IS_HARDWARE_TYPE_8192EE(_Adapter)		(rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8192EE)
+#define IS_HARDWARE_TYPE_8192EU(_Adapter)		(rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8192EU)
+#define IS_HARDWARE_TYPE_8192ES(_Adapter)		(rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8192ES)
+
+#define IS_HARDWARE_TYPE_8192E(_Adapter)		\
+	(IS_HARDWARE_TYPE_8192EE(_Adapter) || IS_HARDWARE_TYPE_8192EU(_Adapter) || IS_HARDWARE_TYPE_8192ES(_Adapter))
+
+#define IS_HARDWARE_TYPE_8723BE(_Adapter)		(rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8723BE)
+#define IS_HARDWARE_TYPE_8723BU(_Adapter)		(rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8723BU)
+#define IS_HARDWARE_TYPE_8723BS(_Adapter)		(rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8723BS)
+
+#define IS_HARDWARE_TYPE_8723B(_Adapter) \
+	(IS_HARDWARE_TYPE_8723BE(_Adapter) || IS_HARDWARE_TYPE_8723BU(_Adapter) || IS_HARDWARE_TYPE_8723BS(_Adapter))
+
+/* RTL8814A Series */
+#define IS_HARDWARE_TYPE_8814AE(_Adapter)		(rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8814AE)
+#define IS_HARDWARE_TYPE_8814AU(_Adapter)		(rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8814AU)
+#define IS_HARDWARE_TYPE_8814AS(_Adapter)		(rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8814AS)
+
+#define IS_HARDWARE_TYPE_8814A(_Adapter)		\
+	(IS_HARDWARE_TYPE_8814AE(_Adapter) || IS_HARDWARE_TYPE_8814AU(_Adapter) || IS_HARDWARE_TYPE_8814AS(_Adapter))
+
+/* RTL8703B Series */
+#define IS_HARDWARE_TYPE_8703BE(_Adapter)		(rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8703BE)
+#define IS_HARDWARE_TYPE_8703BS(_Adapter)		(rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8703BS)
+#define IS_HARDWARE_TYPE_8703BU(_Adapter)		(rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8703BU)
+#define	IS_HARDWARE_TYPE_8703B(_Adapter)			\
+	(IS_HARDWARE_TYPE_8703BE(_Adapter) || IS_HARDWARE_TYPE_8703BU(_Adapter) || IS_HARDWARE_TYPE_8703BS(_Adapter))
+
+/* RTL8723D Series */
+#define IS_HARDWARE_TYPE_8723DE(_Adapter)\
+	(rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8723DE)
+#define IS_HARDWARE_TYPE_8723DS(_Adapter)\
+	(rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8723DS)
+#define IS_HARDWARE_TYPE_8723DU(_Adapter)\
+	(rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8723DU)
+#define	IS_HARDWARE_TYPE_8723D(_Adapter)\
+	(IS_HARDWARE_TYPE_8723DE(_Adapter) || \
+	 IS_HARDWARE_TYPE_8723DU(_Adapter) || \
+	 IS_HARDWARE_TYPE_8723DS(_Adapter))
+
+/* RTL8192F Series */
+#define IS_HARDWARE_TYPE_8192FS(_Adapter)\
+	(rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8192FS)
+#define IS_HARDWARE_TYPE_8192FU(_Adapter)\
+	(rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8192FU)	
+#define IS_HARDWARE_TYPE_8192FE(_Adapter)\
+	(rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8192FE)	
+#define	IS_HARDWARE_TYPE_8192F(_Adapter)\
+	(IS_HARDWARE_TYPE_8192FS(_Adapter) ||\
+	 IS_HARDWARE_TYPE_8192FU(_Adapter) ||\
+	 IS_HARDWARE_TYPE_8192FE(_Adapter))
+
+/* RTL8188F Series */
+#define IS_HARDWARE_TYPE_8188FE(_Adapter)		(rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8188FE)
+#define IS_HARDWARE_TYPE_8188FS(_Adapter)		(rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8188FS)
+#define IS_HARDWARE_TYPE_8188FU(_Adapter)		(rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8188FU)
+#define	IS_HARDWARE_TYPE_8188F(_Adapter)			\
+	(IS_HARDWARE_TYPE_8188FE(_Adapter) || IS_HARDWARE_TYPE_8188FU(_Adapter) || IS_HARDWARE_TYPE_8188FS(_Adapter))
+
+#define IS_HARDWARE_TYPE_8188GTVU(_Adapter)		(rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8188GTVU)
+#define IS_HARDWARE_TYPE_8188GTVS(_Adapter)		(rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8188GTVS)
+#define	IS_HARDWARE_TYPE_8188GTV(_Adapter)			\
+	(IS_HARDWARE_TYPE_8188GTVU(_Adapter) || IS_HARDWARE_TYPE_8188GTVS(_Adapter))
+
+/* RTL8710B Series */
+#define IS_HARDWARE_TYPE_8710BU(_Adapter) (rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8710BU)
+#define IS_HARDWARE_TYPE_8710B(_Adapter) (IS_HARDWARE_TYPE_8710BU(_Adapter))
+
+#define IS_HARDWARE_TYPE_8821BE(_Adapter)		(rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8821BE)
+#define IS_HARDWARE_TYPE_8821BU(_Adapter)		(rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8821BU)
+#define IS_HARDWARE_TYPE_8821BS(_Adapter)		(rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8821BS)
+
+#define IS_HARDWARE_TYPE_8821B(_Adapter)		\
+	(IS_HARDWARE_TYPE_8821BE(_Adapter) || IS_HARDWARE_TYPE_8821BU(_Adapter) || IS_HARDWARE_TYPE_8821BS(_Adapter))
+
+#define IS_HARDWARE_TYPE_8822BE(_Adapter)		(rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8822BE)
+#define IS_HARDWARE_TYPE_8822BU(_Adapter)		(rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8822BU)
+#define IS_HARDWARE_TYPE_8822BS(_Adapter)		(rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8822BS)
+#define IS_HARDWARE_TYPE_8822B(_Adapter)		\
+	(IS_HARDWARE_TYPE_8822BE(_Adapter) || IS_HARDWARE_TYPE_8822BU(_Adapter) || IS_HARDWARE_TYPE_8822BS(_Adapter))
+
+#define IS_HARDWARE_TYPE_8821CE(_Adapter)		(rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8821CE)
+#define IS_HARDWARE_TYPE_8821CU(_Adapter)		(rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8821CU)
+#define IS_HARDWARE_TYPE_8821CS(_Adapter)		(rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8821CS)
+#define IS_HARDWARE_TYPE_8821C(_Adapter)		\
+	(IS_HARDWARE_TYPE_8821CE(_Adapter) || IS_HARDWARE_TYPE_8821CU(_Adapter) || IS_HARDWARE_TYPE_8821CS(_Adapter))
+
+#define IS_HARDWARE_TYPE_JAGUAR2(_Adapter)		\
+	(IS_HARDWARE_TYPE_8814A(_Adapter) || IS_HARDWARE_TYPE_8821B(_Adapter) || IS_HARDWARE_TYPE_8822B(_Adapter) || IS_HARDWARE_TYPE_8821C(_Adapter))
+
+#define IS_HARDWARE_TYPE_JAGUAR_AND_JAGUAR2(_Adapter)		\
+	(IS_HARDWARE_TYPE_JAGUAR(_Adapter) || IS_HARDWARE_TYPE_JAGUAR2(_Adapter))
+
+
+
+typedef enum _wowlan_subcode {
+	WOWLAN_ENABLE			= 0,
+	WOWLAN_DISABLE			= 1,
+	WOWLAN_AP_ENABLE		= 2,
+	WOWLAN_AP_DISABLE		= 3,
+	WOWLAN_PATTERN_CLEAN		= 4
+} wowlan_subcode;
+
+struct wowlan_ioctl_param {
+	unsigned int subcode;
+	unsigned int subcode_value;
+	unsigned int wakeup_reason;
+};
+
+u8 rtw_hal_data_init(_adapter *padapter);
+void rtw_hal_data_deinit(_adapter *padapter);
+
+void rtw_hal_def_value_init(_adapter *padapter);
+
+void	rtw_hal_free_data(_adapter *padapter);
+
+void rtw_hal_dm_init(_adapter *padapter);
+void rtw_hal_dm_deinit(_adapter *padapter);
+#ifdef CONFIG_RTW_SW_LED
+void rtw_hal_sw_led_init(_adapter *padapter);
+void rtw_hal_sw_led_deinit(_adapter *padapter);
+#endif
+u32 rtw_hal_power_on(_adapter *padapter);
+void rtw_hal_power_off(_adapter *padapter);
+
+uint rtw_hal_init(_adapter *padapter);
+#ifdef CONFIG_NEW_NETDEV_HDL
+uint rtw_hal_iface_init(_adapter *adapter);
+#endif
+uint rtw_hal_deinit(_adapter *padapter);
+void rtw_hal_stop(_adapter *padapter);
+u8 rtw_hal_set_hwreg(PADAPTER padapter, u8 variable, u8 *val);
+void rtw_hal_get_hwreg(PADAPTER padapter, u8 variable, u8 *val);
+
+void rtw_hal_chip_configure(_adapter *padapter);
+u8 rtw_hal_read_chip_info(_adapter *padapter);
+void rtw_hal_read_chip_version(_adapter *padapter);
+
+u8 rtw_hal_set_def_var(_adapter *padapter, HAL_DEF_VARIABLE eVariable, PVOID pValue);
+u8 rtw_hal_get_def_var(_adapter *padapter, HAL_DEF_VARIABLE eVariable, PVOID pValue);
+
+void rtw_hal_set_odm_var(_adapter *padapter, HAL_ODM_VARIABLE eVariable, PVOID pValue1, BOOLEAN bSet);
+void	rtw_hal_get_odm_var(_adapter *padapter, HAL_ODM_VARIABLE eVariable, PVOID pValue1, PVOID pValue2);
+
+void rtw_hal_enable_interrupt(_adapter *padapter);
+void rtw_hal_disable_interrupt(_adapter *padapter);
+
+u8 rtw_hal_check_ips_status(_adapter *padapter);
+
+#if defined(CONFIG_USB_HCI) || defined(CONFIG_PCI_HCI)
+	u32	rtw_hal_inirp_init(_adapter *padapter);
+	u32	rtw_hal_inirp_deinit(_adapter *padapter);
+#endif
+
+#if defined(CONFIG_PCI_HCI)
+	void	rtw_hal_irp_reset(_adapter *padapter);
+void	rtw_hal_pci_dbi_write(_adapter *padapter, u16 addr, u8 data);
+u8	rtw_hal_pci_dbi_read(_adapter *padapter, u16 addr);
+void	rtw_hal_pci_mdio_write(_adapter *padapter, u8 addr, u16 data);
+u16	rtw_hal_pci_mdio_read(_adapter *padapter, u8 addr);
+u8	rtw_hal_pci_l1off_nic_support(_adapter *padapter);
+u8	rtw_hal_pci_l1off_capability(_adapter *padapter);
+#endif
+
+u8	rtw_hal_intf_ps_func(_adapter *padapter, HAL_INTF_PS_FUNC efunc_id, u8 *val);
+
+s32	rtw_hal_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe);
+s32	rtw_hal_xmit(_adapter *padapter, struct xmit_frame *pxmitframe);
+s32	rtw_hal_mgnt_xmit(_adapter *padapter, struct xmit_frame *pmgntframe);
+
+s32	rtw_hal_init_xmit_priv(_adapter *padapter);
+void	rtw_hal_free_xmit_priv(_adapter *padapter);
+
+s32	rtw_hal_init_recv_priv(_adapter *padapter);
+void	rtw_hal_free_recv_priv(_adapter *padapter);
+
+void rtw_hal_update_ra_mask(struct sta_info *psta);
+
+void	rtw_hal_start_thread(_adapter *padapter);
+void	rtw_hal_stop_thread(_adapter *padapter);
+
+void rtw_hal_bcn_related_reg_setting(_adapter *padapter);
+
+u32	rtw_hal_read_bbreg(_adapter *padapter, u32 RegAddr, u32 BitMask);
+void	rtw_hal_write_bbreg(_adapter *padapter, u32 RegAddr, u32 BitMask, u32 Data);
+u32	rtw_hal_read_rfreg(_adapter *padapter, enum rf_path eRFPath, u32 RegAddr, u32 BitMask);
+void	rtw_hal_write_rfreg(_adapter *padapter, enum rf_path eRFPath, u32 RegAddr, u32 BitMask, u32 Data);
+
+
+#define phy_query_bb_reg(Adapter, RegAddr, BitMask) rtw_hal_read_bbreg((Adapter), (RegAddr), (BitMask))
+#define phy_set_bb_reg(Adapter, RegAddr, BitMask, Data) rtw_hal_write_bbreg((Adapter), (RegAddr), (BitMask), (Data))
+#define phy_query_rf_reg(Adapter, eRFPath, RegAddr, BitMask) rtw_hal_read_rfreg((Adapter), (eRFPath), (RegAddr), (BitMask))
+#define phy_set_rf_reg(Adapter, eRFPath, RegAddr, BitMask, Data) rtw_hal_write_rfreg((Adapter), (eRFPath), (RegAddr), (BitMask), (Data))
+
+#ifdef CONFIG_SYSON_INDIRECT_ACCESS
+u32 rtw_hal_read_syson_reg(PADAPTER padapter, u32 RegAddr, u32 BitMask);
+void rtw_hal_write_syson_reg(_adapter *padapter, u32 RegAddr, u32 BitMask, u32 Data);
+#define hal_query_syson_reg(Adapter, RegAddr, BitMask) rtw_hal_read_syson_reg((Adapter), (RegAddr), (BitMask))
+#define hal_set_syson_reg(Adapter, RegAddr, BitMask, Data) rtw_hal_write_syson_reg((Adapter), (RegAddr), (BitMask), (Data))
+#endif
+
+#define phy_set_mac_reg	phy_set_bb_reg
+#define phy_query_mac_reg phy_query_bb_reg
+
+#if defined(CONFIG_PCI_HCI)
+	s32	rtw_hal_interrupt_handler(_adapter *padapter);
+#endif
+#if  defined(CONFIG_USB_HCI) && defined(CONFIG_SUPPORT_USB_INT)
+	void	rtw_hal_interrupt_handler(_adapter *padapter, u16 pkt_len, u8 *pbuf);
+#endif
+
+void	rtw_hal_set_chnl_bw(_adapter *padapter, u8 channel, enum channel_width Bandwidth, u8 Offset40, u8 Offset80);
+void	rtw_hal_dm_watchdog(_adapter *padapter);
+void	rtw_hal_dm_watchdog_in_lps(_adapter *padapter);
+
+void	rtw_hal_set_tx_power_level(_adapter *padapter, u8 channel);
+void	rtw_hal_get_tx_power_level(_adapter *padapter, s32 *powerlevel);
+
+#ifdef CONFIG_HOSTAPD_MLME
+	s32	rtw_hal_hostap_mgnt_xmit_entry(_adapter *padapter, _pkt *pkt);
+#endif
+
+#ifdef DBG_CONFIG_ERROR_DETECT
+void rtw_hal_sreset_init(_adapter *padapter);
+void rtw_hal_sreset_reset(_adapter *padapter);
+void rtw_hal_sreset_reset_value(_adapter *padapter);
+void rtw_hal_sreset_xmit_status_check(_adapter *padapter);
+void rtw_hal_sreset_linked_status_check(_adapter *padapter);
+u8   rtw_hal_sreset_get_wifi_status(_adapter *padapter);
+bool rtw_hal_sreset_inprogress(_adapter *padapter);
+#endif
+
+#ifdef CONFIG_IOL
+int rtw_hal_iol_cmd(ADAPTER *adapter, struct xmit_frame *xmit_frame, u32 max_wating_ms, u32 bndy_cnt);
+#endif
+
+#ifdef CONFIG_XMIT_THREAD_MODE
+s32 rtw_hal_xmit_thread_handler(_adapter *padapter);
+#endif
+
+#ifdef CONFIG_RECV_THREAD_MODE
+s32 rtw_hal_recv_hdl(_adapter *adapter);
+#endif
+
+void rtw_hal_notch_filter(_adapter *adapter, bool enable);
+
+#ifdef CONFIG_FW_C2H_REG
+bool rtw_hal_c2h_reg_hdr_parse(_adapter *adapter, u8 *buf, u8 *id, u8 *seq, u8 *plen, u8 **payload);
+bool rtw_hal_c2h_valid(_adapter *adapter, u8 *buf);
+s32 rtw_hal_c2h_evt_read(_adapter *adapter, u8 *buf);
+#endif
+
+#ifdef CONFIG_FW_C2H_PKT
+bool rtw_hal_c2h_pkt_hdr_parse(_adapter *adapter, u8 *buf, u16 len, u8 *id, u8 *seq, u8 *plen, u8 **payload);
+#endif
+
+s32 c2h_handler(_adapter *adapter, u8 id, u8 seq, u8 plen, u8 *payload);
+#ifndef RTW_HALMAC
+s32 rtw_hal_c2h_handler(_adapter *adapter, u8 id, u8 seq, u8 plen, u8 *payload);
+s32 rtw_hal_c2h_id_handle_directly(_adapter *adapter, u8 id, u8 seq, u8 plen, u8 *payload);
+#endif
+
+s32 rtw_hal_is_disable_sw_channel_plan(PADAPTER padapter);
+
+s32 rtw_hal_macid_sleep(_adapter *adapter, u8 macid);
+s32 rtw_hal_macid_wakeup(_adapter *adapter, u8 macid);
+s32 rtw_hal_macid_sleep_all_used(_adapter *adapter);
+s32 rtw_hal_macid_wakeup_all_used(_adapter *adapter);
+
+s32 rtw_hal_fill_h2c_cmd(PADAPTER padapter, u8 ElementID, u32 CmdLen, u8 *pCmdBuffer);
+void rtw_hal_fill_fake_txdesc(_adapter *padapter, u8 *pDesc, u32 BufferLen,
+			      u8 IsPsPoll, u8 IsBTQosNull, u8 bDataFrame);
+u8 rtw_hal_get_txbuff_rsvd_page_num(_adapter *adapter, bool wowlan);
+
+#ifdef CONFIG_GPIO_API
+void rtw_hal_update_hisr_hsisr_ind(_adapter *padapter, u32 flag);
+int rtw_hal_gpio_func_check(_adapter *padapter, u8 gpio_num);
+void rtw_hal_gpio_multi_func_reset(_adapter *padapter, u8 gpio_num);
+#endif
+#ifdef CONFIG_FW_CORRECT_BCN
+void rtw_hal_fw_correct_bcn(_adapter *padapter);
+#endif
+s32 rtw_hal_fw_dl(_adapter *padapter, u8 wowlan);
+
+#if defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN)
+	void rtw_hal_clear_interrupt(_adapter *padapter);
+#endif
+
+void rtw_hal_set_tx_power_index(PADAPTER adapter, u32 powerindex, enum rf_path rfpath, u8 rate);
+u8 rtw_hal_get_tx_power_index(PADAPTER adapter, enum rf_path
+	rfpath, u8 rate, u8 bandwidth, u8 channel, struct txpwr_idx_comp *tic);
+
+u8 rtw_hal_ops_check(_adapter *padapter);
+
+#ifdef RTW_HALMAC
+	u8 rtw_hal_init_mac_register(PADAPTER);
+	u8 rtw_hal_init_phy(PADAPTER);
+s32 rtw_hal_fw_mem_dl(_adapter *padapter, enum fw_mem mem);
+#endif /* RTW_HALMAC */
+
+#ifdef CONFIG_RFKILL_POLL
+bool rtw_hal_rfkill_poll(_adapter *adapter, u8 *valid);
+#endif
+
+#endif /* __HAL_INTF_H__ */
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/include/hal_pg.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/hal_pg.h
--- linux-5.6.3/3rdparty/rtl8821ce/include/hal_pg.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/hal_pg.h	2020-04-10 16:35:06.847661515 +0300
@@ -0,0 +1,880 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+
+#ifndef __HAL_PG_H__
+#define __HAL_PG_H__
+
+#define PPG_BB_GAIN_2G_TX_OFFSET_MASK	0x0F
+#define PPG_BB_GAIN_2G_TXB_OFFSET_MASK	0xF0
+
+#define PPG_BB_GAIN_5G_TX_OFFSET_MASK	0x1F
+#define PPG_THERMAL_OFFSET_MASK			0x1F
+#define KFREE_BB_GAIN_2G_TX_OFFSET(_ppg_v) (((_ppg_v) == PPG_BB_GAIN_2G_TX_OFFSET_MASK) ? 0 : (((_ppg_v) & 0x01) ? ((_ppg_v) >> 1) : (-((_ppg_v) >> 1))))
+#define KFREE_BB_GAIN_2G_TXB_OFFSET(_ppg_v) (((_ppg_v) == PPG_BB_GAIN_2G_TXB_OFFSET_MASK) ? 0 : (((_ppg_v) & 0x10) ? ((_ppg_v) >> 5) : (-((_ppg_v) >> 5))))
+#define KFREE_BB_GAIN_5G_TX_OFFSET(_ppg_v) (((_ppg_v) == PPG_BB_GAIN_5G_TX_OFFSET_MASK) ? 0 : (((_ppg_v) & 0x01) ? ((_ppg_v) >> 1) : (-((_ppg_v) >> 1))))
+#define KFREE_THERMAL_OFFSET(_ppg_v) (((_ppg_v) == PPG_THERMAL_OFFSET_MASK) ? 0 : (((_ppg_v) & 0x01) ? ((_ppg_v) >> 1) : (-((_ppg_v) >> 1))))
+
+/* ****************************************************
+ *			EEPROM/Efuse PG Offset for 88EE/88EU/88ES
+ * **************************************************** */
+#define EEPROM_ChannelPlan_88E					0xB8
+#define EEPROM_XTAL_88E						0xB9
+#define EEPROM_THERMAL_METER_88E				0xBA
+#define EEPROM_IQK_LCK_88E						0xBB
+
+#define EEPROM_RF_BOARD_OPTION_88E			0xC1
+#define EEPROM_RF_FEATURE_OPTION_88E			0xC2
+#define EEPROM_RF_BT_SETTING_88E				0xC3
+#define EEPROM_VERSION_88E						0xC4
+#define EEPROM_CustomID_88E					0xC5
+#define EEPROM_RF_ANTENNA_OPT_88E			0xC9
+#define EEPROM_COUNTRY_CODE_88E				0xCB
+
+/* RTL88EE */
+#define EEPROM_MAC_ADDR_88EE					0xD0
+#define EEPROM_VID_88EE						0xD6
+#define EEPROM_DID_88EE						0xD8
+#define EEPROM_SVID_88EE						0xDA
+#define EEPROM_SMID_88EE						0xDC
+
+/* RTL88EU */
+#define EEPROM_MAC_ADDR_88EU					0xD7
+#define EEPROM_VID_88EU						0xD0
+#define EEPROM_PID_88EU						0xD2
+#define EEPROM_USB_OPTIONAL_FUNCTION0		0xD4 /* 8188EU, 8192EU, 8812AU is the same */
+#define EEPROM_USB_OPTIONAL_FUNCTION0_8811AU 0x104
+
+/* RTL88ES */
+#define EEPROM_MAC_ADDR_88ES					0x11A
+/* ****************************************************
+ *			EEPROM/Efuse PG Offset for 8192EE/8192EU/8192ES
+ * **************************************************** */
+#define GET_PG_KFREE_ON_8192E(_pg_m)			LE_BITS_TO_1BYTE(((u8 *)(_pg_m)) + 0xC1, 4, 1)
+#define GET_PG_KFREE_THERMAL_K_ON_8192E(_pg_m)	LE_BITS_TO_1BYTE(((u8 *)(_pg_m)) + 0xC8, 5, 1)
+
+#define PPG_BB_GAIN_2G_TXA_OFFSET_8192E	0x1F6
+#define PPG_THERMAL_OFFSET_8192E		0x1F5
+
+#define	EEPROM_ChannelPlan_8192E				0xB8
+#define	EEPROM_XTAL_8192E						0xB9
+#define	EEPROM_THERMAL_METER_8192E			0xBA
+#define	EEPROM_IQK_LCK_8192E					0xBB
+#define	EEPROM_2G_5G_PA_TYPE_8192E			0xBC
+#define	EEPROM_2G_LNA_TYPE_GAIN_SEL_8192E	0xBD
+#define	EEPROM_5G_LNA_TYPE_GAIN_SEL_8192E	0xBF
+
+#define	EEPROM_RF_BOARD_OPTION_8192E		0xC1
+#define	EEPROM_RF_FEATURE_OPTION_8192E		0xC2
+#define	EEPROM_RF_BT_SETTING_8192E			0xC3
+#define	EEPROM_VERSION_8192E					0xC4
+#define	EEPROM_CustomID_8192E				0xC5
+#define	EEPROM_TX_BBSWING_2G_8192E			0xC6
+#define	EEPROM_TX_BBSWING_5G_8192E			0xC7
+#define	EEPROM_TX_PWR_CALIBRATE_RATE_8192E	0xC8
+#define	EEPROM_RF_ANTENNA_OPT_8192E			0xC9
+#define	EEPROM_RFE_OPTION_8192E				0xCA
+#define	EEPROM_RFE_OPTION_8188E				0xCA
+#define EEPROM_COUNTRY_CODE_8192E			0xCB
+
+/* RTL8192EE */
+#define	EEPROM_MAC_ADDR_8192EE				0xD0
+#define	EEPROM_VID_8192EE						0xD6
+#define	EEPROM_DID_8192EE						0xD8
+#define	EEPROM_SVID_8192EE					0xDA
+#define	EEPROM_SMID_8192EE					0xDC
+
+/* RTL8192EU */
+#define	EEPROM_MAC_ADDR_8192EU				0xD7
+#define	EEPROM_VID_8192EU						0xD0
+#define	EEPROM_PID_8192EU						0xD2
+#define	EEPROM_PA_TYPE_8192EU		0xBC
+#define	EEPROM_LNA_TYPE_2G_8192EU	0xBD
+#define	EEPROM_LNA_TYPE_5G_8192EU	0xBF
+
+/* RTL8192ES */
+#define	EEPROM_MAC_ADDR_8192ES				0x11A
+/* ****************************************************
+ *			EEPROM/Efuse PG Offset for 8812AE/8812AU/8812AS
+ * *****************************************************/
+#define EEPROM_USB_MODE_8812					0x08
+
+#define EEPROM_ChannelPlan_8812				0xB8
+#define EEPROM_XTAL_8812						0xB9
+#define EEPROM_THERMAL_METER_8812			0xBA
+#define EEPROM_IQK_LCK_8812					0xBB
+#define EEPROM_2G_5G_PA_TYPE_8812			0xBC
+#define EEPROM_2G_LNA_TYPE_GAIN_SEL_8812	0xBD
+#define EEPROM_5G_LNA_TYPE_GAIN_SEL_8812	0xBF
+
+#define EEPROM_RF_BOARD_OPTION_8812			0xC1
+#define EEPROM_RF_FEATURE_OPTION_8812		0xC2
+#define EEPROM_RF_BT_SETTING_8812				0xC3
+#define EEPROM_VERSION_8812					0xC4
+#define EEPROM_CustomID_8812					0xC5
+#define EEPROM_TX_BBSWING_2G_8812			0xC6
+#define EEPROM_TX_BBSWING_5G_8812			0xC7
+#define EEPROM_TX_PWR_CALIBRATE_RATE_8812	0xC8
+#define EEPROM_RF_ANTENNA_OPT_8812			0xC9
+#define EEPROM_RFE_OPTION_8812				0xCA
+#define EEPROM_COUNTRY_CODE_8812			0xCB
+
+/* RTL8812AE */
+#define EEPROM_MAC_ADDR_8812AE				0xD0
+#define EEPROM_VID_8812AE						0xD6
+#define EEPROM_DID_8812AE						0xD8
+#define EEPROM_SVID_8812AE						0xDA
+#define EEPROM_SMID_8812AE					0xDC
+
+/* RTL8812AU */
+#define EEPROM_MAC_ADDR_8812AU				0xD7
+#define EEPROM_VID_8812AU						0xD0
+#define EEPROM_PID_8812AU						0xD2
+#define EEPROM_PA_TYPE_8812AU					0xBC
+#define EEPROM_LNA_TYPE_2G_8812AU			0xBD
+#define EEPROM_LNA_TYPE_5G_8812AU			0xBF
+
+/* RTL8814AU */
+#define	EEPROM_MAC_ADDR_8814AU				0xD8
+#define	EEPROM_VID_8814AU						0xD0
+#define	EEPROM_PID_8814AU						0xD2
+#define	EEPROM_PA_TYPE_8814AU				0xBC
+#define	EEPROM_LNA_TYPE_2G_8814AU			0xBD
+#define	EEPROM_LNA_TYPE_5G_8814AU			0xBF
+
+/* RTL8814AE */
+#define EEPROM_MAC_ADDR_8814AE				0xD0
+#define EEPROM_VID_8814AE						0xD6
+#define EEPROM_DID_8814AE						0xD8
+#define EEPROM_SVID_8814AE						0xDA
+#define EEPROM_SMID_8814AE					0xDC
+
+/* ****************************************************
+ *			EEPROM/Efuse PG Offset for 8814AU
+ * **************************************************** */
+#define GET_PG_KFREE_ON_8814A(_pg_m)			LE_BITS_TO_1BYTE(((u8 *)(_pg_m)) + 0xC8, 4, 1)
+#define GET_PG_KFREE_THERMAL_K_ON_8814A(_pg_m)	LE_BITS_TO_1BYTE(((u8 *)(_pg_m)) + 0xC8, 5, 1)
+#define GET_PG_TX_POWER_TRACKING_MODE_8814A(_pg_m)	LE_BITS_TO_1BYTE(((u8 *)(_pg_m)) + 0xC8, 6, 2)
+
+#define KFREE_GAIN_DATA_LENGTH_8814A	22
+
+#define PPG_BB_GAIN_2G_TXBA_OFFSET_8814A	0x3EE
+
+#define PPG_THERMAL_OFFSET_8814A		0x3EF
+
+#define EEPROM_USB_MODE_8814A				0x0E
+#define EEPROM_ChannelPlan_8814				0xB8
+#define EEPROM_XTAL_8814					0xB9
+#define EEPROM_THERMAL_METER_8814			0xBA
+#define	EEPROM_IQK_LCK_8814					0xBB
+
+
+#define EEPROM_PA_TYPE_8814					0xBC
+#define EEPROM_LNA_TYPE_AB_2G_8814			0xBD
+#define	EEPROM_LNA_TYPE_CD_2G_8814			0xBE
+#define EEPROM_LNA_TYPE_AB_5G_8814			0xBF
+#define EEPROM_LNA_TYPE_CD_5G_8814			0xC0
+#define	EEPROM_RF_BOARD_OPTION_8814			0xC1
+#define	EEPROM_RF_BT_SETTING_8814			0xC3
+#define	EEPROM_VERSION_8814					0xC4
+#define	EEPROM_CustomID_8814				0xC5
+#define	EEPROM_TX_BBSWING_2G_8814			0xC6
+#define	EEPROM_TX_BBSWING_5G_8814			0xC7
+#define EEPROM_TRX_ANTENNA_OPTION_8814		0xC9
+#define	EEPROM_RFE_OPTION_8814				0xCA
+#define EEPROM_COUNTRY_CODE_8814			0xCB
+
+/*Extra Info for 8814A Initial Gain Fine Tune  suggested by Willis, JIRA: MP123*/
+#define	EEPROM_IG_OFFSET_4_AB_2G_8814A				0x120
+#define	EEPROM_IG_OFFSET_4_CD_2G_8814A				0x121
+#define	EEPROM_IG_OFFSET_4_AB_5GL_8814A				0x122
+#define	EEPROM_IG_OFFSET_4_CD_5GL_8814A				0x123
+#define	EEPROM_IG_OFFSET_4_AB_5GM_8814A				0x124
+#define	EEPROM_IG_OFFSET_4_CD_5GM_8814A				0x125
+#define	EEPROM_IG_OFFSET_4_AB_5GH_8814A				0x126
+#define	EEPROM_IG_OFFSET_4_CD_5GH_8814A				0x127
+
+/* ****************************************************
+ *			EEPROM/Efuse PG Offset for 8821AE/8821AU/8821AS
+ * **************************************************** */
+
+#define GET_PG_KFREE_ON_8821A(_pg_m)			LE_BITS_TO_1BYTE(((u8 *)(_pg_m)) + 0xC8, 4, 1)
+#define GET_PG_KFREE_THERMAL_K_ON_8821A(_pg_m)	LE_BITS_TO_1BYTE(((u8 *)(_pg_m)) + 0xC8, 5, 1)
+
+#define PPG_BB_GAIN_2G_TXA_OFFSET_8821A		0x1F6
+#define PPG_THERMAL_OFFSET_8821A			0x1F5
+#define PPG_BB_GAIN_5GLB1_TXA_OFFSET_8821A	0x1F4
+#define PPG_BB_GAIN_5GLB2_TXA_OFFSET_8821A	0x1F3
+#define PPG_BB_GAIN_5GMB1_TXA_OFFSET_8821A	0x1F2
+#define PPG_BB_GAIN_5GMB2_TXA_OFFSET_8821A	0x1F1
+#define PPG_BB_GAIN_5GHB_TXA_OFFSET_8821A	0x1F0
+
+#define EEPROM_ChannelPlan_8821				0xB8
+#define EEPROM_XTAL_8821						0xB9
+#define EEPROM_THERMAL_METER_8821			0xBA
+#define EEPROM_IQK_LCK_8821					0xBB
+
+
+#define EEPROM_RF_BOARD_OPTION_8821			0xC1
+#define EEPROM_RF_FEATURE_OPTION_8821		0xC2
+#define EEPROM_RF_BT_SETTING_8821				0xC3
+#define EEPROM_VERSION_8821					0xC4
+#define EEPROM_CustomID_8821					0xC5
+#define EEPROM_RF_ANTENNA_OPT_8821			0xC9
+
+/* RTL8821AE */
+#define EEPROM_MAC_ADDR_8821AE				0xD0
+#define EEPROM_VID_8821AE						0xD6
+#define EEPROM_DID_8821AE						0xD8
+#define EEPROM_SVID_8821AE						0xDA
+#define EEPROM_SMID_8821AE					0xDC
+
+/* RTL8821AU */
+#define EEPROM_PA_TYPE_8821AU					0xBC
+#define EEPROM_LNA_TYPE_8821AU				0xBF
+
+/* RTL8821AS */
+#define EEPROM_MAC_ADDR_8821AS				0x11A
+
+/* RTL8821AU */
+#define EEPROM_MAC_ADDR_8821AU				0x107
+#define EEPROM_VID_8821AU						0x100
+#define EEPROM_PID_8821AU						0x102
+
+
+/* ****************************************************
+ *			EEPROM/Efuse PG Offset for 8192 SE/SU
+ * **************************************************** */
+#define EEPROM_VID_92SE						0x0A
+#define EEPROM_DID_92SE						0x0C
+#define EEPROM_SVID_92SE						0x0E
+#define EEPROM_SMID_92SE						0x10
+
+#define EEPROM_MAC_ADDR_92S					0x12
+
+#define EEPROM_TSSI_A_92SE						0x74
+#define EEPROM_TSSI_B_92SE						0x75
+
+#define EEPROM_Version_92SE					0x7C
+
+
+#define EEPROM_VID_92SU						0x08
+#define EEPROM_PID_92SU						0x0A
+
+#define EEPROM_Version_92SU					0x50
+#define EEPROM_TSSI_A_92SU						0x6b
+#define EEPROM_TSSI_B_92SU						0x6c
+
+/* ====================================================
+	EEPROM/Efuse PG Offset for 8188FE/8188FU/8188FS
+   ====================================================
+ */
+
+#define GET_PG_KFREE_ON_8188F(_pg_m)			LE_BITS_TO_1BYTE(((u8 *)(_pg_m)) + 0xC1, 4, 1)
+#define GET_PG_KFREE_THERMAL_K_ON_8188F(_pg_m)	LE_BITS_TO_1BYTE(((u8 *)(_pg_m)) + 0xC8, 5, 1)
+
+#define PPG_BB_GAIN_2G_TXA_OFFSET_8188F	0xEE
+#define PPG_THERMAL_OFFSET_8188F		0xEF
+
+#define	EEPROM_ChannelPlan_8188F			0xB8
+#define	EEPROM_XTAL_8188F					0xB9
+#define	EEPROM_THERMAL_METER_8188F			0xBA
+#define	EEPROM_IQK_LCK_8188F				0xBB
+#define	EEPROM_2G_5G_PA_TYPE_8188F			0xBC
+#define	EEPROM_2G_LNA_TYPE_GAIN_SEL_8188F	0xBD
+#define	EEPROM_5G_LNA_TYPE_GAIN_SEL_8188F	0xBF
+
+#define	EEPROM_RF_BOARD_OPTION_8188F		0xC1
+#define	EEPROM_FEATURE_OPTION_8188F			0xC2
+#define	EEPROM_RF_BT_SETTING_8188F			0xC3
+#define	EEPROM_VERSION_8188F				0xC4
+#define	EEPROM_CustomID_8188F				0xC5
+#define	EEPROM_TX_BBSWING_2G_8188F			0xC6
+#define	EEPROM_TX_PWR_CALIBRATE_RATE_8188F	0xC8
+#define	EEPROM_RF_ANTENNA_OPT_8188F			0xC9
+#define	EEPROM_RFE_OPTION_8188F				0xCA
+#define EEPROM_COUNTRY_CODE_8188F			0xCB
+#define EEPROM_CUSTOMER_ID_8188F			0x7F
+#define EEPROM_SUBCUSTOMER_ID_8188F			0x59
+
+/* RTL8188FU */
+#define EEPROM_MAC_ADDR_8188FU				0xD7
+#define EEPROM_VID_8188FU					0xD0
+#define EEPROM_PID_8188FU					0xD2
+#define EEPROM_PA_TYPE_8188FU				0xBC
+#define EEPROM_LNA_TYPE_2G_8188FU			0xBD
+#define EEPROM_USB_OPTIONAL_FUNCTION0_8188FU 0xD4
+
+/* RTL8188FS */
+#define	EEPROM_MAC_ADDR_8188FS				0x11A
+#define EEPROM_Voltage_ADDR_8188F			0x8
+
+/* ====================================================
+	EEPROM/Efuse PG Offset for 8188GTV/8188GTVS
+   ====================================================
+ */
+
+#define GET_PG_KFREE_ON_8188GTV(_pg_m)				LE_BITS_TO_1BYTE(((u8 *)(_pg_m)) + 0xC1, 4, 1)
+#define GET_PG_KFREE_THERMAL_K_ON_8188GTV(_pg_m)	LE_BITS_TO_1BYTE(((u8 *)(_pg_m)) + 0xC8, 5, 1)
+
+#define PPG_BB_GAIN_2G_TXA_OFFSET_8188GTV	0xEE
+#define PPG_THERMAL_OFFSET_8188GTV			0xEF
+
+#define	EEPROM_ChannelPlan_8188GTV				0xB8
+#define	EEPROM_XTAL_8188GTV						0xB9
+#define	EEPROM_THERMAL_METER_8188GTV			0xBA
+#define	EEPROM_IQK_LCK_8188GTV					0xBB
+#define	EEPROM_2G_5G_PA_TYPE_8188GTV			0xBC
+#define	EEPROM_2G_LNA_TYPE_GAIN_SEL_8188GTV		0xBD
+#define	EEPROM_5G_LNA_TYPE_GAIN_SEL_8188GTV		0xBF
+
+#define	EEPROM_RF_BOARD_OPTION_8188GTV			0xC1
+#define	EEPROM_FEATURE_OPTION_8188GTV			0xC2
+#define	EEPROM_RF_BT_SETTING_8188GTV			0xC3
+#define	EEPROM_VERSION_8188GTV					0xC4
+#define	EEPROM_CustomID_8188GTV					0xC5
+#define	EEPROM_TX_BBSWING_2G_8188GTV			0xC6
+#define	EEPROM_TX_PWR_CALIBRATE_RATE_8188GTV	0xC8
+#define	EEPROM_RF_ANTENNA_OPT_8188GTV			0xC9
+#define	EEPROM_RFE_OPTION_8188GTV				0xCA
+#define EEPROM_COUNTRY_CODE_8188GTV				0xCB
+#define EEPROM_CUSTOMER_ID_8188GTV				0x7F
+#define EEPROM_SUBCUSTOMER_ID_8188GTV			0x59
+
+/* RTL8188GTVU */
+#define EEPROM_MAC_ADDR_8188GTVU				0xD7
+#define EEPROM_VID_8188GTVU						0xD0
+#define EEPROM_PID_8188GTVU						0xD2
+#define EEPROM_PA_TYPE_8188GTVU					0xBC
+#define EEPROM_LNA_TYPE_2G_8188GTVU				0xBD
+#define EEPROM_USB_OPTIONAL_FUNCTION0_8188GTVU	0xD4
+
+/* RTL8188GTVS */
+#define	EEPROM_MAC_ADDR_8188GTVS				0x11A
+#define EEPROM_Voltage_ADDR_8188GTV				0x8
+
+/* ****************************************************
+ *			EEPROM/Efuse PG Offset for 8723BE/8723BU/8723BS
+ * *****************************************************/
+#define	EEPROM_ChannelPlan_8723B				0xB8
+#define	EEPROM_XTAL_8723B						0xB9
+#define	EEPROM_THERMAL_METER_8723B			0xBA
+#define	EEPROM_IQK_LCK_8723B					0xBB
+#define	EEPROM_2G_5G_PA_TYPE_8723B			0xBC
+#define	EEPROM_2G_LNA_TYPE_GAIN_SEL_8723B	0xBD
+#define	EEPROM_5G_LNA_TYPE_GAIN_SEL_8723B	0xBF
+
+#define	EEPROM_RF_BOARD_OPTION_8723B		0xC1
+#define	EEPROM_FEATURE_OPTION_8723B			0xC2
+#define	EEPROM_RF_BT_SETTING_8723B			0xC3
+#define	EEPROM_VERSION_8723B					0xC4
+#define	EEPROM_CustomID_8723B				0xC5
+#define	EEPROM_TX_BBSWING_2G_8723B			0xC6
+#define	EEPROM_TX_PWR_CALIBRATE_RATE_8723B	0xC8
+#define	EEPROM_RF_ANTENNA_OPT_8723B		0xC9
+#define	EEPROM_RFE_OPTION_8723B				0xCA
+#define EEPROM_COUNTRY_CODE_8723B			0xCB
+
+/* RTL8723BE */
+#define EEPROM_MAC_ADDR_8723BE				0xD0
+#define EEPROM_VID_8723BE						0xD6
+#define EEPROM_DID_8723BE						0xD8
+#define EEPROM_SVID_8723BE						0xDA
+#define EEPROM_SMID_8723BE						0xDC
+
+/* RTL8723BU */
+#define EEPROM_MAC_ADDR_8723BU				0x107
+#define EEPROM_VID_8723BU						0x100
+#define EEPROM_PID_8723BU						0x102
+#define EEPROM_PA_TYPE_8723BU					0xBC
+#define EEPROM_LNA_TYPE_2G_8723BU				0xBD
+
+
+/* RTL8723BS */
+#define	EEPROM_MAC_ADDR_8723BS				0x11A
+#define EEPROM_Voltage_ADDR_8723B			0x8
+
+/* ****************************************************
+ *			EEPROM/Efuse PG Offset for 8703B
+ * **************************************************** */
+#define GET_PG_KFREE_ON_8703B(_pg_m)			LE_BITS_TO_1BYTE(((u8 *)(_pg_m)) + 0xC1, 4, 1)
+#define GET_PG_KFREE_THERMAL_K_ON_8703B(_pg_m)	LE_BITS_TO_1BYTE(((u8 *)(_pg_m)) + 0xC8, 5, 1)
+
+#define PPG_BB_GAIN_2G_TXA_OFFSET_8703B	0xEE
+#define PPG_THERMAL_OFFSET_8703B		0xEF
+
+#define	EEPROM_ChannelPlan_8703B				0xB8
+#define	EEPROM_XTAL_8703B					0xB9
+#define	EEPROM_THERMAL_METER_8703B			0xBA
+#define	EEPROM_IQK_LCK_8703B					0xBB
+#define	EEPROM_2G_5G_PA_TYPE_8703B			0xBC
+#define	EEPROM_2G_LNA_TYPE_GAIN_SEL_8703B	0xBD
+#define	EEPROM_5G_LNA_TYPE_GAIN_SEL_8703B	0xBF
+
+#define	EEPROM_RF_BOARD_OPTION_8703B		0xC1
+#define	EEPROM_FEATURE_OPTION_8703B			0xC2
+#define	EEPROM_RF_BT_SETTING_8703B			0xC3
+#define	EEPROM_VERSION_8703B					0xC4
+#define	EEPROM_CustomID_8703B					0xC5
+#define	EEPROM_TX_BBSWING_2G_8703B			0xC6
+#define	EEPROM_TX_PWR_CALIBRATE_RATE_8703B	0xC8
+#define	EEPROM_RF_ANTENNA_OPT_8703B		0xC9
+#define	EEPROM_RFE_OPTION_8703B				0xCA
+#define EEPROM_COUNTRY_CODE_8703B			0xCB
+
+/* RTL8703BU */
+#define EEPROM_MAC_ADDR_8703BU                          0x107
+#define EEPROM_VID_8703BU                               0x100
+#define EEPROM_PID_8703BU                               0x102
+#define EEPROM_USB_OPTIONAL_FUNCTION0_8703BU            0x104
+#define EEPROM_PA_TYPE_8703BU                           0xBC
+#define EEPROM_LNA_TYPE_2G_8703BU                       0xBD
+
+/* RTL8703BS */
+#define	EEPROM_MAC_ADDR_8703BS				0x11A
+#define	EEPROM_Voltage_ADDR_8703B			0x8
+
+/*
+ * ====================================================
+ *	EEPROM/Efuse PG Offset for 8822B
+ * ====================================================
+ */
+#define	EEPROM_ChannelPlan_8822B		0xB8
+#define	EEPROM_XTAL_8822B			0xB9
+#define	EEPROM_THERMAL_METER_8822B		0xBA
+#define	EEPROM_IQK_LCK_8822B			0xBB
+#define	EEPROM_2G_5G_PA_TYPE_8822B		0xBC
+/* PATH A & PATH B */
+#define	EEPROM_2G_LNA_TYPE_GAIN_SEL_AB_8822B	0xBD
+/* PATH C & PATH D */
+#define	EEPROM_2G_LNA_TYPE_GAIN_SEL_CD_8822B	0xBE
+/* PATH A & PATH B */
+#define	EEPROM_5G_LNA_TYPE_GAIN_SEL_AB_8822B	0xBF
+/* PATH C & PATH D */
+#define	EEPROM_5G_LNA_TYPE_GAIN_SEL_CD_8822B	0xC0
+
+#define	EEPROM_RF_BOARD_OPTION_8822B		0xC1
+#define	EEPROM_FEATURE_OPTION_8822B		0xC2
+#define	EEPROM_RF_BT_SETTING_8822B		0xC3
+#define	EEPROM_VERSION_8822B			0xC4
+#define	EEPROM_CustomID_8822B			0xC5
+#define	EEPROM_TX_BBSWING_2G_8822B		0xC6
+#define	EEPROM_TX_PWR_CALIBRATE_RATE_8822B	0xC8
+#define	EEPROM_RF_ANTENNA_OPT_8822B		0xC9
+#define	EEPROM_RFE_OPTION_8822B			0xCA
+#define EEPROM_COUNTRY_CODE_8822B		0xCB
+
+/* RTL8822BU */
+#define EEPROM_MAC_ADDR_8822BU			0x107
+#define EEPROM_VID_8822BU			0x100
+#define EEPROM_PID_8822BU			0x102
+#define EEPROM_USB_OPTIONAL_FUNCTION0_8822BU	0x104
+#define EEPROM_USB_MODE_8822BU			0x06
+
+/* RTL8822BS */
+#define	EEPROM_MAC_ADDR_8822BS			0x11A
+
+/* RTL8822BE */
+#define	EEPROM_MAC_ADDR_8822BE			0xD0
+/*
+ * ====================================================
+ *	EEPROM/Efuse PG Offset for 8821C
+ * ====================================================
+ */
+#define	EEPROM_CHANNEL_PLAN_8821C		0xB8
+#define	EEPROM_XTAL_8821C			0xB9
+#define	EEPROM_THERMAL_METER_8821C		0xBA
+#define	EEPROM_IQK_LCK_8821C			0xBB
+#define	EEPROM_2G_5G_PA_TYPE_8821C		0xBC
+/* PATH A & PATH B */
+#define	EEPROM_2G_LNA_TYPE_GAIN_SEL_AB_8821C	0xBD
+/* PATH C & PATH D */
+#define	EEPROM_2G_LNA_TYPE_GAIN_SEL_CD_8821C	0xBE
+/* PATH A & PATH B */
+#define	EEPROM_5G_LNA_TYPE_GAIN_SEL_AB_8821C	0xBF
+/* PATH C & PATH D */
+#define	EEPROM_5G_LNA_TYPE_GAIN_SEL_CD_8821C	0xC0
+
+#define	EEPROM_RF_BOARD_OPTION_8821C		0xC1
+#define	EEPROM_FEATURE_OPTION_8821C		0xC2
+#define	EEPROM_RF_BT_SETTING_8821C		0xC3
+#define	EEPROM_VERSION_8821C			0xC4
+#define	EEPROM_CUSTOMER_ID_8821C			0xC5
+#define	EEPROM_TX_BBSWING_2G_8821C		0xC6
+#define	EEPROM_TX_BBSWING_5G_8821C		0xC7
+#define	EEPROM_TX_PWR_CALIBRATE_RATE_8821C	0xC8
+#define	EEPROM_RF_ANTENNA_OPT_8821C		0xC9
+#define	EEPROM_RFE_OPTION_8821C			0xCA
+#define EEPROM_COUNTRY_CODE_8821C		0xCB
+
+/* RTL8821CU */
+#define EEPROM_MAC_ADDR_8821CU			0x107
+#define EEPROM_VID_8821CU					0x100
+#define EEPROM_PID_8821CU					0x102
+#define EEPROM_USB_OPTIONAL_FUNCTION0_8821CU	0x104
+#define EEPROM_USB_MODE_8821CU			0x06
+
+/* RTL8821CS */
+#define	EEPROM_MAC_ADDR_8821CS			0x11A
+
+/* RTL8821CE */
+#define	EEPROM_MAC_ADDR_8821CE			0xD0
+/* ****************************************************
+ *	EEPROM/Efuse PG Offset for 8723D
+ * **************************************************** */
+#define GET_PG_KFREE_ON_8723D(_pg_m)	\
+	LE_BITS_TO_1BYTE(((u8 *)(_pg_m)) + 0xC1, 4, 1)
+#define GET_PG_KFREE_THERMAL_K_ON_8723D(_pg_m)	\
+	LE_BITS_TO_1BYTE(((u8 *)(_pg_m)) + 0xC8, 5, 1)
+
+#define PPG_8723D_S1	0
+#define PPG_8723D_S0	1
+
+#define PPG_BB_GAIN_2G_TXA_OFFSET_8723D		0xEE
+#define PPG_BB_GAIN_2G_TX_OFFSET_8723D		0x1EE
+#define PPG_THERMAL_OFFSET_8723D		0xEF
+
+#define	EEPROM_ChannelPlan_8723D		0xB8
+#define	EEPROM_XTAL_8723D			0xB9
+#define	EEPROM_THERMAL_METER_8723D		0xBA
+#define	EEPROM_IQK_LCK_8723D			0xBB
+#define	EEPROM_2G_5G_PA_TYPE_8723D		0xBC
+#define	EEPROM_2G_LNA_TYPE_GAIN_SEL_8723D	0xBD
+#define	EEPROM_5G_LNA_TYPE_GAIN_SEL_8723D	0xBF
+
+#define	EEPROM_RF_BOARD_OPTION_8723D		0xC1
+#define	EEPROM_FEATURE_OPTION_8723D		0xC2
+#define	EEPROM_RF_BT_SETTING_8723D		0xC3
+#define	EEPROM_VERSION_8723D			0xC4
+#define	EEPROM_CustomID_8723D			0xC5
+#define	EEPROM_TX_BBSWING_2G_8723D		0xC6
+#define	EEPROM_TX_PWR_CALIBRATE_RATE_8723D	0xC8
+#define	EEPROM_RF_ANTENNA_OPT_8723D		0xC9
+#define	EEPROM_RFE_OPTION_8723D			0xCA
+#define EEPROM_COUNTRY_CODE_8723D		0xCB
+
+/* RTL8723DE */
+#define EEPROM_MAC_ADDR_8723DE              0xD0
+#define EEPROM_VID_8723DE                   0xD6
+#define EEPROM_DID_8723DE                   0xD8
+#define EEPROM_SVID_8723DE                  0xDA
+#define EEPROM_SMID_8723DE                  0xDC
+
+/* RTL8723DU */
+#define EEPROM_MAC_ADDR_8723DU                  0x107
+#define EEPROM_VID_8723DU                       0x100
+#define EEPROM_PID_8723DU                       0x102
+#define EEPROM_USB_OPTIONAL_FUNCTION0_8723DU    0x104
+
+/* RTL8723BS */
+#define	EEPROM_MAC_ADDR_8723DS			0x11A
+#define	EEPROM_Voltage_ADDR_8723D		0x8
+
+/* ****************************************************
+ *	EEPROM/Efuse PG Offset for 8192F
+ * **************************************************** */
+#define	EEPROM_ChannelPlan_8192F			0xB8
+#define	EEPROM_XTAL_8192F					0xB9
+#define	EEPROM_THERMAL_METER_8192F			0xBA
+#define	EEPROM_IQK_LCK_8192F				0xBB
+#define	EEPROM_2G_5G_PA_TYPE_8192F			0xBC
+#define	EEPROM_2G_LNA_TYPE_GAIN_SEL_8192F	0xBD
+#define	EEPROM_5G_LNA_TYPE_GAIN_SEL_8192F	0xBF
+
+#define	EEPROM_RF_BOARD_OPTION_8192F		0xC1
+#define	EEPROM_FEATURE_OPTION_8192F			0xC2
+#define	EEPROM_RF_BT_SETTING_8192F			0xC3
+#define	EEPROM_VERSION_8192F				0xC4
+#define	EEPROM_CustomID_8192F				0xC5
+#define	EEPROM_TX_BBSWING_2G_8192F			0xC6
+#define	EEPROM_TX_BBSWING_5G_8192F			0xC7
+#define	EEPROM_TX_PWR_CALIBRATE_RATE_8192F	0xC8
+#define	EEPROM_RF_ANTENNA_OPT_8192F			0xC9
+#define	EEPROM_RFE_OPTION_8192F				0xCA
+#define EEPROM_COUNTRY_CODE_8192F			0xCB
+/*RTL8192FS*/
+#define	EEPROM_MAC_ADDR_8192FS				0x11A
+#define EEPROM_Voltage_ADDR_8192F			0x8
+/* RTL8192FU */
+#define EEPROM_MAC_ADDR_8192FU					0x107
+#define EEPROM_VID_8192FU							0x100
+#define EEPROM_PID_8192FU							0x102
+#define EEPROM_USB_OPTIONAL_FUNCTION0_8192FU	0x104
+/* RTL8192FE */
+#define EEPROM_MAC_ADDR_8192FE					0xD0
+#define EEPROM_VID_8192FE							0xD6
+#define EEPROM_DID_8192FE							0xD8
+#define EEPROM_SVID_8192FE							0xDA
+#define EEPROM_SMID_8192FE						0xDC
+
+/* ****************************************************
+ *	EEPROM/Efuse PG Offset for 8710B
+ * **************************************************** */
+#define RTL_EEPROM_ID_8710B 					0x8195
+#define EEPROM_Default_ThermalMeter_8710B		0x1A
+
+#define	EEPROM_CHANNEL_PLAN_8710B			0xC8
+#define	EEPROM_XTAL_8710B					0xC9
+#define	EEPROM_THERMAL_METER_8710B			0xCA
+#define	EEPROM_IQK_LCK_8710B					0xCB
+#define	EEPROM_2G_5G_PA_TYPE_8710B			0xCC
+#define	EEPROM_2G_LNA_TYPE_GAIN_SEL_8710B	0xCD
+#define	EEPROM_5G_LNA_TYPE_GAIN_SEL_8710B	0xCF
+#define 	EEPROM_TX_KFREE_8710B				0xEE    //Physical  Efuse Address
+#define 	EEPROM_THERMAL_8710B				0xEF    //Physical  Efuse Address
+#define 	EEPROM_PACKAGE_TYPE_8710B			0xF8    //Physical  Efuse Address
+
+#define EEPROM_RF_BOARD_OPTION_8710B		0x131
+#define EEPROM_RF_FEATURE_OPTION_8710B		0x132
+#define EEPROM_RF_BT_SETTING_8710B			0x133
+#define EEPROM_VERSION_8710B					0x134
+#define EEPROM_CUSTOM_ID_8710B				0x135
+#define EEPROM_TX_BBSWING_2G_8710B			0x136
+#define EEPROM_TX_BBSWING_5G_8710B			0x137
+#define EEPROM_TX_PWR_CALIBRATE_RATE_8710B	0x138
+#define EEPROM_RF_ANTENNA_OPT_8710B			0x139
+#define EEPROM_RFE_OPTION_8710B				0x13A
+#define EEPROM_COUNTRY_CODE_8710B			0x13B
+#define EEPROM_COUNTRY_CODE_2_8710B			0x13C
+
+#define EEPROM_MAC_ADDR_8710B 				0x11A
+#define EEPROM_VID_8710BU						0x1C0
+#define EEPROM_PID_8710BU						0x1C2
+
+/* ****************************************************
+ *			EEPROM/Efuse Value Type
+ * **************************************************** */
+#define EETYPE_TX_PWR							0x0
+#define EETYPE_MAX_RFE_8192F					0x31
+/* ****************************************************
+ *			EEPROM/Efuse Default Value
+ * **************************************************** */
+#define EEPROM_CID_DEFAULT					0x0
+#define EEPROM_CID_DEFAULT_EXT				0xFF /* Reserved for Realtek */
+#define EEPROM_CID_TOSHIBA						0x4
+#define EEPROM_CID_CCX							0x10
+#define EEPROM_CID_QMI							0x0D
+#define EEPROM_CID_WHQL						0xFE
+
+#define EEPROM_CHANNEL_PLAN_FCC				0x0
+#define EEPROM_CHANNEL_PLAN_IC				0x1
+#define EEPROM_CHANNEL_PLAN_ETSI				0x2
+#define EEPROM_CHANNEL_PLAN_SPAIN			0x3
+#define EEPROM_CHANNEL_PLAN_FRANCE			0x4
+#define EEPROM_CHANNEL_PLAN_MKK				0x5
+#define EEPROM_CHANNEL_PLAN_MKK1				0x6
+#define EEPROM_CHANNEL_PLAN_ISRAEL			0x7
+#define EEPROM_CHANNEL_PLAN_TELEC			0x8
+#define EEPROM_CHANNEL_PLAN_GLOBAL_DOMAIN	0x9
+#define EEPROM_CHANNEL_PLAN_WORLD_WIDE_13	0xA
+#define EEPROM_CHANNEL_PLAN_NCC_TAIWAN		0xB
+#define EEPROM_CHANNEL_PLAN_CHIAN			0XC
+#define EEPROM_CHANNEL_PLAN_SINGAPORE_INDIA_MEXICO  0XD
+#define EEPROM_CHANNEL_PLAN_KOREA			0xE
+#define EEPROM_CHANNEL_PLAN_TURKEY	0xF
+#define EEPROM_CHANNEL_PLAN_JAPAN	0x10
+#define EEPROM_CHANNEL_PLAN_FCC_NO_DFS		0x11
+#define EEPROM_CHANNEL_PLAN_JAPAN_NO_DFS	0x12
+#define EEPROM_CHANNEL_PLAN_WORLD_WIDE_5G	0x13
+#define EEPROM_CHANNEL_PLAN_TAIWAN_NO_DFS	0x14
+
+#define EEPROM_USB_OPTIONAL1					0xE
+#define EEPROM_CHANNEL_PLAN_BY_HW_MASK		0x80
+
+#define RTL_EEPROM_ID							0x8129
+#define EEPROM_Default_TSSI						0x0
+#define EEPROM_Default_BoardType				0x02
+#define EEPROM_Default_ThermalMeter			0x12
+#define EEPROM_Default_ThermalMeter_92SU		0x7
+#define EEPROM_Default_ThermalMeter_88E		0x18
+#define EEPROM_Default_ThermalMeter_8812		0x18
+#define	EEPROM_Default_ThermalMeter_8192E			0x1A
+#define	EEPROM_Default_ThermalMeter_8723B		0x18
+#define	EEPROM_Default_ThermalMeter_8703B		0x18
+#define	EEPROM_Default_ThermalMeter_8723D		0x18
+#define	EEPROM_Default_ThermalMeter_8188F		0x18
+#define	EEPROM_Default_ThermalMeter_8188GTV		0x18
+#define EEPROM_Default_ThermalMeter_8814A		0x18
+#define	EEPROM_Default_ThermalMeter_8192F		0x1A
+
+#define EEPROM_Default_CrystalCap				0x0
+#define EEPROM_Default_CrystalCap_8723A		0x20
+#define EEPROM_Default_CrystalCap_88E			0x20
+#define EEPROM_Default_CrystalCap_8812			0x20
+#define EEPROM_Default_CrystalCap_8814			0x20
+#define EEPROM_Default_CrystalCap_8192E			0x20
+#define EEPROM_Default_CrystalCap_8723B			0x20
+#define EEPROM_Default_CrystalCap_8703B			0x20
+#define EEPROM_Default_CrystalCap_8723D			0x20
+#define EEPROM_Default_CrystalCap_8188F			0x20
+#define EEPROM_Default_CrystalCap_8188GTV		0x20
+#define EEPROM_Default_CrystalCap_8192F			0x20
+#define EEPROM_Default_CrystalFreq				0x0
+#define EEPROM_Default_TxPowerLevel_92C		0x22
+#define EEPROM_Default_TxPowerLevel_2G			0x2C
+#define EEPROM_Default_TxPowerLevel_5G			0x22
+#define EEPROM_Default_TxPowerLevel			0x22
+#define EEPROM_Default_HT40_2SDiff				0x0
+#define EEPROM_Default_HT20_Diff				2
+#define EEPROM_Default_LegacyHTTxPowerDiff		0x3
+#define EEPROM_Default_LegacyHTTxPowerDiff_92C	0x3
+#define EEPROM_Default_LegacyHTTxPowerDiff_92D	0x4
+#define EEPROM_Default_HT40_PwrMaxOffset		0
+#define EEPROM_Default_HT20_PwrMaxOffset		0
+
+#define EEPROM_Default_PID						0x1234
+#define EEPROM_Default_VID						0x5678
+#define EEPROM_Default_CustomerID				0xAB
+#define EEPROM_Default_CustomerID_8188E		0x00
+#define EEPROM_Default_SubCustomerID			0xCD
+#define EEPROM_Default_Version					0
+
+#define EEPROM_Default_externalPA_C9		0x00
+#define EEPROM_Default_externalPA_CC		0xFF
+#define EEPROM_Default_internalPA_SP3T_C9	0xAA
+#define EEPROM_Default_internalPA_SP3T_CC	0xAF
+#define EEPROM_Default_internalPA_SPDT_C9	0xAA
+#ifdef CONFIG_PCI_HCI
+	#define EEPROM_Default_internalPA_SPDT_CC	0xA0
+#else
+	#define EEPROM_Default_internalPA_SPDT_CC	0xFA
+#endif
+#define EEPROM_Default_PAType						0
+#define EEPROM_Default_LNAType						0
+
+/* New EFUSE default value */
+#define EEPROM_DEFAULT_CHANNEL_PLAN		0x7F
+#define EEPROM_DEFAULT_BOARD_OPTION		0x00
+#define EEPROM_DEFAULT_RFE_OPTION_8192E 0xFF
+#define EEPROM_DEFAULT_RFE_OPTION_8188E 0xFF
+#define EEPROM_DEFAULT_RFE_OPTION		0x04
+#define EEPROM_DEFAULT_FEATURE_OPTION	0x00
+#define EEPROM_DEFAULT_BT_OPTION			0x10
+
+
+#define EEPROM_DEFAULT_TX_CALIBRATE_RATE	0x00
+
+/* PCIe related */
+#define	EEPROM_PCIE_DEV_CAP_01				0xE0 /* Express device capability in PCIe configuration space, i.e., map to offset 0x74 */
+#define	EEPROM_PCIE_DEV_CAP_02				0xE1 /* Express device capability in PCIe configuration space, i.e., map to offset 0x75 */
+
+
+/*
+ * For VHT series TX power by rate table.
+ * VHT TX power by rate off setArray =
+ * Band:-2G&5G = 0 / 1
+ * RF: at most 4*4 = ABCD=0/1/2/3
+ * CCK=0 OFDM=1/2 HT-MCS 0-15=3/4/56 VHT=7/8/9/10/11
+ *   */
+#define TX_PWR_BY_RATE_NUM_BAND			2
+#define TX_PWR_BY_RATE_NUM_RF			4
+#define TX_PWR_BY_RATE_NUM_RATE			84
+
+#define TXPWR_LMT_MAX_RF				4
+
+/* ----------------------------------------------------------------------------
+ * EEPROM/EFUSE data structure definition.
+ * ---------------------------------------------------------------------------- */
+
+/* For 88E new structure */
+
+/*
+2.4G:
+{
+{1,2},
+{3,4,5},
+{6,7,8},
+{9,10,11},
+{12,13},
+{14}
+}
+
+5G:
+{
+{36,38,40},
+{44,46,48},
+{52,54,56},
+{60,62,64},
+{100,102,104},
+{108,110,112},
+{116,118,120},
+{124,126,128},
+{132,134,136},
+{140,142,144},
+{149,151,153},
+{157,159,161},
+{173,175,177},
+}
+*/
+#define	MAX_RF_PATH				4
+#define RF_PATH_MAX				MAX_RF_PATH
+#define	MAX_CHNL_GROUP_24G		6
+#define	MAX_CHNL_GROUP_5G		14
+
+/* It must always set to 4, otherwise read efuse table sequence will be wrong. */
+#define	MAX_TX_COUNT				4
+
+typedef struct _TxPowerInfo24G {
+	u8 IndexCCK_Base[MAX_RF_PATH][MAX_CHNL_GROUP_24G];
+	u8 IndexBW40_Base[MAX_RF_PATH][MAX_CHNL_GROUP_24G];
+	/* If only one tx, only BW20 and OFDM are used. */
+	s8 CCK_Diff[MAX_RF_PATH][MAX_TX_COUNT];
+	s8 OFDM_Diff[MAX_RF_PATH][MAX_TX_COUNT];
+	s8 BW20_Diff[MAX_RF_PATH][MAX_TX_COUNT];
+	s8 BW40_Diff[MAX_RF_PATH][MAX_TX_COUNT];
+} TxPowerInfo24G, *PTxPowerInfo24G;
+
+typedef struct _TxPowerInfo5G {
+	u8 IndexBW40_Base[MAX_RF_PATH][MAX_CHNL_GROUP_5G];
+	/* If only one tx, only BW20, OFDM, BW80 and BW160 are used. */
+	s8 OFDM_Diff[MAX_RF_PATH][MAX_TX_COUNT];
+	s8 BW20_Diff[MAX_RF_PATH][MAX_TX_COUNT];
+	s8 BW40_Diff[MAX_RF_PATH][MAX_TX_COUNT];
+	s8 BW80_Diff[MAX_RF_PATH][MAX_TX_COUNT];
+	s8 BW160_Diff[MAX_RF_PATH][MAX_TX_COUNT];
+} TxPowerInfo5G, *PTxPowerInfo5G;
+
+
+typedef	enum _BT_Ant_NUM {
+	Ant_x2	= 0,
+	Ant_x1	= 1
+} BT_Ant_NUM, *PBT_Ant_NUM;
+
+typedef	enum _BT_CoType {
+	BT_2WIRE		= 0,
+	BT_ISSC_3WIRE	= 1,
+	BT_ACCEL		= 2,
+	BT_CSR_BC4		= 3,
+	BT_CSR_BC8		= 4,
+	BT_RTL8756		= 5,
+	BT_RTL8723A		= 6,
+	BT_RTL8821		= 7,
+	BT_RTL8723B		= 8,
+	BT_RTL8192E		= 9,
+	BT_RTL8814A		= 10,
+	BT_RTL8812A		= 11,
+	BT_RTL8703B		= 12,
+	BT_RTL8822B		= 13,
+	BT_RTL8723D		= 14,
+	BT_RTL8821C		= 15,
+	BT_RTL8192F		= 16,
+} BT_CoType, *PBT_CoType;
+
+typedef	enum _BT_RadioShared {
+	BT_Radio_Shared	= 0,
+	BT_Radio_Individual	= 1,
+} BT_RadioShared, *PBT_RadioShared;
+
+
+#endif
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/include/hal_phy.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/hal_phy.h
--- linux-5.6.3/3rdparty/rtl8821ce/include/hal_phy.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/hal_phy.h	2020-04-10 16:35:06.847661515 +0300
@@ -0,0 +1,234 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#ifndef __HAL_PHY_H__
+#define __HAL_PHY_H__
+
+
+#if DISABLE_BB_RF
+	#define	HAL_FW_ENABLE				0
+	#define	HAL_MAC_ENABLE			0
+	#define	HAL_BB_ENABLE				0
+	#define	HAL_RF_ENABLE				0
+#else /* FPGA_PHY and ASIC */
+	#define	HAL_FW_ENABLE				1
+	#define	HAL_MAC_ENABLE			1
+	#define	HAL_BB_ENABLE				1
+	#define	HAL_RF_ENABLE				1
+#endif
+
+#define	RF6052_MAX_TX_PWR			0x3F
+#define	RF6052_MAX_REG_88E			0xFF
+#define	RF6052_MAX_REG_92C			0x7F
+
+#define	RF6052_MAX_REG	\
+	((RF6052_MAX_REG_88E > RF6052_MAX_REG_92C) ? RF6052_MAX_REG_88E : RF6052_MAX_REG_92C)
+
+#define GET_RF6052_REAL_MAX_REG(_Adapter)	\
+	(IS_HARDWARE_TYPE_8188E(_Adapter) ? RF6052_MAX_REG_88E : RF6052_MAX_REG_92C)
+
+#define	RF6052_MAX_PATH				2
+
+/*
+ * Antenna detection method, i.e., using single tone detection or RSSI reported from each antenna detected.
+ * Added by Roger, 2013.05.22.
+ *   */
+#define ANT_DETECT_BY_SINGLE_TONE	BIT0
+#define ANT_DETECT_BY_RSSI				BIT1
+#define IS_ANT_DETECT_SUPPORT_SINGLE_TONE(__Adapter)		((GET_HAL_DATA(__Adapter)->AntDetection) & ANT_DETECT_BY_SINGLE_TONE)
+#define IS_ANT_DETECT_SUPPORT_RSSI(__Adapter)		((GET_HAL_DATA(__Adapter)->AntDetection) & ANT_DETECT_BY_RSSI)
+
+
+/*--------------------------Define Parameters-------------------------------*/
+typedef	enum _RF_CHIP {
+	RF_CHIP_MIN = 0,	/* 0 */
+	RF_8225 = 1,			/* 1 11b/g RF for verification only */
+	RF_8256 = 2,			/* 2 11b/g/n */
+	RF_8258 = 3,			/* 3 11a/b/g/n RF */
+	RF_6052 = 4,			/* 4 11b/g/n RF */
+	RF_PSEUDO_11N = 5,	/* 5, It is a temporality RF. */
+	RF_CHIP_MAX
+} RF_CHIP_E, *PRF_CHIP_E;
+
+typedef enum _ANTENNA_PATH {
+	ANTENNA_NONE	= 0,
+	ANTENNA_D		= 1,
+	ANTENNA_C		= 2,
+	ANTENNA_CD	= 3,
+	ANTENNA_B		= 4,
+	ANTENNA_BD	= 5,
+	ANTENNA_BC	= 6,
+	ANTENNA_BCD	= 7,
+	ANTENNA_A		= 8,
+	ANTENNA_AD	= 9,
+	ANTENNA_AC	= 10,
+	ANTENNA_ACD	= 11,
+	ANTENNA_AB	= 12,
+	ANTENNA_ABD	= 13,
+	ANTENNA_ABC	= 14,
+	ANTENNA_ABCD	= 15
+} ANTENNA_PATH;
+
+typedef enum _RF_CONTENT {
+	radioa_txt = 0x1000,
+	radiob_txt = 0x1001,
+	radioc_txt = 0x1002,
+	radiod_txt = 0x1003
+} RF_CONTENT;
+
+typedef enum _BaseBand_Config_Type {
+	BaseBand_Config_PHY_REG = 0,			/* Radio Path A */
+	BaseBand_Config_AGC_TAB = 1,			/* Radio Path B */
+	BaseBand_Config_AGC_TAB_2G = 2,
+	BaseBand_Config_AGC_TAB_5G = 3,
+	BaseBand_Config_PHY_REG_PG
+} BaseBand_Config_Type, *PBaseBand_Config_Type;
+
+typedef enum _HW_BLOCK {
+	HW_BLOCK_MAC = 0,
+	HW_BLOCK_PHY0 = 1,
+	HW_BLOCK_PHY1 = 2,
+	HW_BLOCK_RF = 3,
+	HW_BLOCK_MAXIMUM = 4, /* Never use this */
+} HW_BLOCK_E, *PHW_BLOCK_E;
+
+typedef enum _WIRELESS_MODE {
+	WIRELESS_MODE_UNKNOWN = 0x00,
+	WIRELESS_MODE_A = 0x01,
+	WIRELESS_MODE_B = 0x02,
+	WIRELESS_MODE_G = 0x04,
+	WIRELESS_MODE_AUTO = 0x08,
+	WIRELESS_MODE_N_24G = 0x10,
+	WIRELESS_MODE_N_5G = 0x20,
+	WIRELESS_MODE_AC_5G = 0x40,
+	WIRELESS_MODE_AC_24G  = 0x80,
+	WIRELESS_MODE_AC_ONLY  = 0x100,
+} WIRELESS_MODE;
+
+typedef enum _SwChnlCmdID {
+	CmdID_End,
+	CmdID_SetTxPowerLevel,
+	CmdID_BBRegWrite10,
+	CmdID_WritePortUlong,
+	CmdID_WritePortUshort,
+	CmdID_WritePortUchar,
+	CmdID_RF_WriteReg,
+} SwChnlCmdID;
+
+typedef struct _SwChnlCmd {
+	SwChnlCmdID	CmdID;
+	u32				Para1;
+	u32				Para2;
+	u32				msDelay;
+} SwChnlCmd;
+
+typedef struct _R_ANTENNA_SELECT_OFDM {
+	u32			r_tx_antenna:4;
+	u32			r_ant_l:4;
+	u32			r_ant_non_ht:4;
+	u32			r_ant_ht1:4;
+	u32			r_ant_ht2:4;
+	u32			r_ant_ht_s1:4;
+	u32			r_ant_non_ht_s1:4;
+	u32			OFDM_TXSC:2;
+	u32			Reserved:2;
+} R_ANTENNA_SELECT_OFDM;
+
+typedef struct _R_ANTENNA_SELECT_CCK {
+	u8			r_cckrx_enable_2:2;
+	u8			r_cckrx_enable:2;
+	u8			r_ccktx_enable:4;
+} R_ANTENNA_SELECT_CCK;
+
+
+/*--------------------------Exported Function prototype---------------------*/
+u32
+PHY_CalculateBitShift(
+	u32 BitMask
+);
+
+#ifdef CONFIG_RF_SHADOW_RW
+typedef struct RF_Shadow_Compare_Map {
+	/* Shadow register value */
+	u32		Value;
+	/* Compare or not flag */
+	u8		Compare;
+	/* Record If it had ever modified unpredicted */
+	u8		ErrorOrNot;
+	/* Recorver Flag */
+	u8		Recorver;
+	/*  */
+	u8		Driver_Write;
+} RF_SHADOW_T;
+
+u32
+PHY_RFShadowRead(
+	IN	PADAPTER		Adapter,
+	IN	enum rf_path		eRFPath,
+	IN	u32				Offset);
+
+VOID
+PHY_RFShadowWrite(
+	IN	PADAPTER		Adapter,
+	IN	enum rf_path		eRFPath,
+	IN	u32				Offset,
+	IN	u32				Data);
+
+BOOLEAN
+PHY_RFShadowCompare(
+	IN	PADAPTER		Adapter,
+	IN	enum rf_path		eRFPath,
+	IN	u32				Offset);
+
+VOID
+PHY_RFShadowRecorver(
+	IN	PADAPTER		Adapter,
+	IN	enum rf_path		eRFPath,
+	IN	u32				Offset);
+
+VOID
+PHY_RFShadowCompareAll(
+	IN	PADAPTER		Adapter);
+
+VOID
+PHY_RFShadowRecorverAll(
+	IN	PADAPTER		Adapter);
+
+VOID
+PHY_RFShadowCompareFlagSet(
+	IN	PADAPTER		Adapter,
+	IN	enum rf_path		eRFPath,
+	IN	u32				Offset,
+	IN	u8				Type);
+
+VOID
+PHY_RFShadowRecorverFlagSet(
+	IN	PADAPTER		Adapter,
+	IN	enum rf_path		eRFPath,
+	IN	u32				Offset,
+	IN	u8				Type);
+
+VOID
+PHY_RFShadowCompareFlagSetAll(
+	IN	PADAPTER		Adapter);
+
+VOID
+PHY_RFShadowRecorverFlagSetAll(
+	IN	PADAPTER		Adapter);
+
+VOID
+PHY_RFShadowRefresh(
+	IN	PADAPTER		Adapter);
+#endif /*#CONFIG_RF_SHADOW_RW*/
+#endif /* __HAL_COMMON_H__ */
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/include/hal_phy_reg.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/hal_phy_reg.h
--- linux-5.6.3/3rdparty/rtl8821ce/include/hal_phy_reg.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/hal_phy_reg.h	2020-04-10 16:35:06.847661515 +0300
@@ -0,0 +1,25 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#ifndef __HAL_PHY_REG_H__
+#define __HAL_PHY_REG_H__
+
+/* for PutRFRegsetting & GetRFRegSetting BitMask
+ * #if (RTL92SE_FPGA_VERIFY == 1)
+ * #define		bRFRegOffsetMask	0xfff
+ * #else */
+#define		bRFRegOffsetMask	0xfffff
+/* #endif */
+
+#endif /* __HAL_PHY_REG_H__ */
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/include/HalPwrSeqCmd.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/HalPwrSeqCmd.h
--- linux-5.6.3/3rdparty/rtl8821ce/include/HalPwrSeqCmd.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/HalPwrSeqCmd.h	2020-04-10 16:35:06.845661421 +0300
@@ -0,0 +1,130 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#ifndef __HALPWRSEQCMD_H__
+#define __HALPWRSEQCMD_H__
+
+#include <drv_types.h>
+
+/*---------------------------------------------*/
+/* 3 The value of cmd: 4 bits
+ *---------------------------------------------*/
+#define PWR_CMD_READ			0x00
+/* offset: the read register offset
+ * msk: the mask of the read value
+ * value: N/A, left by 0
+ * note: dirver shall implement this function by read & msk */
+
+#define PWR_CMD_WRITE			0x01
+/* offset: the read register offset
+ * msk: the mask of the write bits
+ * value: write value
+ * note: driver shall implement this cmd by read & msk after write */
+
+#define PWR_CMD_POLLING			0x02
+/* offset: the read register offset
+ * msk: the mask of the polled value
+ * value: the value to be polled, masked by the msd field.
+ * note: driver shall implement this cmd by
+ * do {
+ * if( (Read(offset) & msk) == (value & msk) )
+ * break;
+ * } while(not timeout); */
+
+#define PWR_CMD_DELAY			0x03
+/* offset: the value to delay
+ * msk: N/A
+ * value: the unit of delay, 0: us, 1: ms */
+
+#define PWR_CMD_END				0x04
+/* offset: N/A
+ * msk: N/A
+ * value: N/A */
+
+/*---------------------------------------------*/
+/* 3 The value of base: 4 bits
+ *---------------------------------------------
+    * define the base address of each block */
+#define PWR_BASEADDR_MAC		0x00
+#define PWR_BASEADDR_USB		0x01
+#define PWR_BASEADDR_PCIE		0x02
+#define PWR_BASEADDR_SDIO		0x03
+
+/*---------------------------------------------*/
+/* 3 The value of interface_msk: 4 bits
+ *---------------------------------------------*/
+#define	PWR_INTF_SDIO_MSK		BIT(0)
+#define	PWR_INTF_USB_MSK		BIT(1)
+#define	PWR_INTF_PCI_MSK		BIT(2)
+#define	PWR_INTF_ALL_MSK		(BIT(0) | BIT(1) | BIT(2) | BIT(3))
+
+/*---------------------------------------------*/
+/* 3 The value of fab_msk: 4 bits
+ *---------------------------------------------*/
+#define	PWR_FAB_TSMC_MSK		BIT(0)
+#define	PWR_FAB_UMC_MSK			BIT(1)
+#define	PWR_FAB_ALL_MSK			(BIT(0) | BIT(1) | BIT(2) | BIT(3))
+
+/*---------------------------------------------*/
+/* 3 The value of cut_msk: 8 bits
+ *---------------------------------------------*/
+#define	PWR_CUT_TESTCHIP_MSK	BIT(0)
+#define	PWR_CUT_A_MSK			BIT(1)
+#define	PWR_CUT_B_MSK			BIT(2)
+#define	PWR_CUT_C_MSK			BIT(3)
+#define	PWR_CUT_D_MSK			BIT(4)
+#define	PWR_CUT_E_MSK			BIT(5)
+#define	PWR_CUT_F_MSK			BIT(6)
+#define	PWR_CUT_G_MSK			BIT(7)
+#define	PWR_CUT_ALL_MSK			0xFF
+
+
+typedef enum _PWRSEQ_CMD_DELAY_UNIT_ {
+	PWRSEQ_DELAY_US,
+	PWRSEQ_DELAY_MS,
+} PWRSEQ_DELAY_UNIT;
+
+typedef struct _WL_PWR_CFG_ {
+	u16 offset;
+	u8 cut_msk;
+	u8 fab_msk:4;
+	u8 interface_msk:4;
+	u8 base:4;
+	u8 cmd:4;
+	u8 msk;
+	u8 value;
+} WLAN_PWR_CFG, *PWLAN_PWR_CFG;
+
+
+#define GET_PWR_CFG_OFFSET(__PWR_CMD)		((__PWR_CMD).offset)
+#define GET_PWR_CFG_CUT_MASK(__PWR_CMD)		((__PWR_CMD).cut_msk)
+#define GET_PWR_CFG_FAB_MASK(__PWR_CMD)		((__PWR_CMD).fab_msk)
+#define GET_PWR_CFG_INTF_MASK(__PWR_CMD)	((__PWR_CMD).interface_msk)
+#define GET_PWR_CFG_BASE(__PWR_CMD)			((__PWR_CMD).base)
+#define GET_PWR_CFG_CMD(__PWR_CMD)			((__PWR_CMD).cmd)
+#define GET_PWR_CFG_MASK(__PWR_CMD)			((__PWR_CMD).msk)
+#define GET_PWR_CFG_VALUE(__PWR_CMD)		((__PWR_CMD).value)
+
+
+/* ********************************************************************************
+ *	Prototype of protected function.
+ * ******************************************************************************** */
+u8 HalPwrSeqCmdParsing(
+	PADAPTER		padapter,
+	u8				CutVersion,
+	u8				FabVersion,
+	u8				InterfaceType,
+	WLAN_PWR_CFG	PwrCfgCmd[]);
+
+#endif
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/include/hal_sdio.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/hal_sdio.h
--- linux-5.6.3/3rdparty/rtl8821ce/include/hal_sdio.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/hal_sdio.h	2020-04-10 16:35:06.847661515 +0300
@@ -0,0 +1,56 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#ifndef __HAL_SDIO_H_
+#define __HAL_SDIO_H_
+
+#define ffaddr2deviceId(pdvobj, addr)	(pdvobj->Queue2Pipe[addr])
+
+u8 rtw_hal_sdio_max_txoqt_free_space(_adapter *padapter);
+u8 rtw_hal_sdio_query_tx_freepage(_adapter *padapter, u8 PageIdx, u8 RequiredPageNum);
+void rtw_hal_sdio_update_tx_freepage(_adapter *padapter, u8 PageIdx, u8 RequiredPageNum);
+void rtw_hal_set_sdio_tx_max_length(PADAPTER padapter, u8 numHQ, u8 numNQ, u8 numLQ, u8 numPubQ, u8 div_num);
+u32 rtw_hal_get_sdio_tx_max_length(PADAPTER padapter, u8 queue_idx);
+bool sdio_power_on_check(PADAPTER padapter);
+
+#ifdef CONFIG_FW_C2H_REG
+void sd_c2h_hisr_hdl(_adapter *adapter);
+#endif
+
+#if defined(CONFIG_RTL8188F) || defined (CONFIG_RTL8188GTV) || defined (CONFIG_RTL8192F)
+#define SDIO_LOCAL_CMD_ADDR(addr) ((SDIO_LOCAL_DEVICE_ID << 13) | ((addr) & SDIO_LOCAL_MSK))
+#endif
+
+#ifdef CONFIG_SDIO_CHK_HCI_RESUME
+bool sdio_chk_hci_resume(struct intf_hdl *pintfhdl);
+void sdio_chk_hci_suspend(struct intf_hdl *pintfhdl);
+#else
+#define sdio_chk_hci_resume(pintfhdl) _FALSE
+#define sdio_chk_hci_suspend(pintfhdl) do {} while (0)
+#endif /* CONFIG_SDIO_CHK_HCI_RESUME */
+
+#ifdef CONFIG_SDIO_INDIRECT_ACCESS
+/* program indirect access register in sdio local to read/write page0 registers */
+s32 sdio_iread(PADAPTER padapter, u32 addr, u8 size, u8 *v);
+s32 sdio_iwrite(PADAPTER padapter, u32 addr, u8 size, u8 *v);
+u8 sdio_iread8(struct intf_hdl *pintfhdl, u32 addr);
+u16 sdio_iread16(struct intf_hdl *pintfhdl, u32 addr);
+u32 sdio_iread32(struct intf_hdl *pintfhdl, u32 addr);
+s32 sdio_iwrite8(struct intf_hdl *pintfhdl, u32 addr, u8 val);
+s32 sdio_iwrite16(struct intf_hdl *pintfhdl, u32 addr, u16 val);
+s32 sdio_iwrite32(struct intf_hdl *pintfhdl, u32 addr, u32 val);
+#endif /* CONFIG_SDIO_INDIRECT_ACCESS */
+u32 cmd53_4byte_alignment(struct intf_hdl *pintfhdl, u32 addr);
+
+#endif /* __HAL_SDIO_H_ */
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/include/HalVerDef.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/HalVerDef.h
--- linux-5.6.3/3rdparty/rtl8821ce/include/HalVerDef.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/HalVerDef.h	2020-04-10 16:35:06.845661421 +0300
@@ -0,0 +1,201 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#ifndef __HAL_VERSION_DEF_H__
+#define __HAL_VERSION_DEF_H__
+
+#define TRUE	_TRUE
+#define FALSE	_FALSE
+
+/* HAL_IC_TYPE_E */
+typedef enum tag_HAL_IC_Type_Definition {
+	CHIP_8192S	=	0,
+	CHIP_8188C	=	1,
+	CHIP_8192C	=	2,
+	CHIP_8192D	=	3,
+	CHIP_8723A	=	4,
+	CHIP_8188E	=	5,
+	CHIP_8812	=	6,
+	CHIP_8821	=	7,
+	CHIP_8723B	=	8,
+	CHIP_8192E	=	9,
+	CHIP_8814A	=	10,
+	CHIP_8703B	=	11,
+	CHIP_8188F	=	12,
+	CHIP_8822B	=	13,
+	CHIP_8723D	=	14,
+	CHIP_8821C	=	15,
+	CHIP_8710B	=	16,
+	CHIP_8192F	=	17,
+	CHIP_8188GTV =	18,
+} HAL_IC_TYPE_E;
+
+/* HAL_CHIP_TYPE_E */
+typedef enum tag_HAL_CHIP_Type_Definition {
+	TEST_CHIP		=	0,
+	NORMAL_CHIP	=	1,
+	FPGA			=	2,
+} HAL_CHIP_TYPE_E;
+
+/* HAL_CUT_VERSION_E */
+typedef enum tag_HAL_Cut_Version_Definition {
+	A_CUT_VERSION		=	0,
+	B_CUT_VERSION		=	1,
+	C_CUT_VERSION		=	2,
+	D_CUT_VERSION		=	3,
+	E_CUT_VERSION		=	4,
+	F_CUT_VERSION		=	5,
+	G_CUT_VERSION		=	6,
+	H_CUT_VERSION		=	7,
+	I_CUT_VERSION		=	8,
+	J_CUT_VERSION		=	9,
+	K_CUT_VERSION		=	10,
+} HAL_CUT_VERSION_E;
+
+/* HAL_Manufacturer */
+typedef enum tag_HAL_Manufacturer_Version_Definition {
+	CHIP_VENDOR_TSMC	=	0,
+	CHIP_VENDOR_UMC	=	1,
+	CHIP_VENDOR_SMIC	=	2,
+} HAL_VENDOR_E;
+
+typedef enum tag_HAL_RF_Type_Definition {
+	RF_TYPE_1T1R	=	0,
+	RF_TYPE_1T2R	=	1,
+	RF_TYPE_2T2R	=	2,
+	RF_TYPE_2T3R	=	3,
+	RF_TYPE_2T4R	=	4,
+	RF_TYPE_3T3R	=	5,
+	RF_TYPE_3T4R	=	6,
+	RF_TYPE_4T4R	=	7,
+} HAL_RF_TYPE_E;
+
+typedef	struct tag_HAL_VERSION {
+	HAL_IC_TYPE_E		ICType;
+	HAL_CHIP_TYPE_E		ChipType;
+	HAL_CUT_VERSION_E	CUTVersion;
+	HAL_VENDOR_E		VendorType;
+	HAL_RF_TYPE_E		RFType;
+	u8					ROMVer;
+} HAL_VERSION, *PHAL_VERSION;
+
+/* VERSION_8192C			VersionID;
+ * HAL_VERSION			VersionID; */
+
+/* Get element */
+#define GET_CVID_IC_TYPE(version)			((HAL_IC_TYPE_E)(((HAL_VERSION)version).ICType))
+#define GET_CVID_CHIP_TYPE(version)			((HAL_CHIP_TYPE_E)(((HAL_VERSION)version).ChipType))
+#define GET_CVID_RF_TYPE(version)			((HAL_RF_TYPE_E)(((HAL_VERSION)version).RFType))
+#define GET_CVID_MANUFACTUER(version)		((HAL_VENDOR_E)(((HAL_VERSION)version).VendorType))
+#define GET_CVID_CUT_VERSION(version)		((HAL_CUT_VERSION_E)(((HAL_VERSION)version).CUTVersion))
+#define GET_CVID_ROM_VERSION(version)		((((HAL_VERSION)version).ROMVer) & ROM_VERSION_MASK)
+
+/* ----------------------------------------------------------------------------
+ * Common Macro. --
+ * ----------------------------------------------------------------------------
+ * HAL_VERSION VersionID */
+
+/* HAL_IC_TYPE_E */
+#if 0
+	#define IS_81XXC(version)				(((GET_CVID_IC_TYPE(version) == CHIP_8192C) || (GET_CVID_IC_TYPE(version) == CHIP_8188C)) ? TRUE : FALSE)
+	#define IS_8723_SERIES(version)			((GET_CVID_IC_TYPE(version) == CHIP_8723A) ? TRUE : FALSE)
+	#define IS_92D(version)					((GET_CVID_IC_TYPE(version) == CHIP_8192D) ? TRUE : FALSE)
+#endif
+
+#define IS_8188E(version)					((GET_CVID_IC_TYPE(version) == CHIP_8188E) ? TRUE : FALSE)
+#define IS_8188F(version)					((GET_CVID_IC_TYPE(version) == CHIP_8188F) ? TRUE : FALSE)
+#define IS_8188GTV(version)					((GET_CVID_IC_TYPE(version) == CHIP_8188GTV) ? TRUE : FALSE)
+#define IS_8192E(version)					((GET_CVID_IC_TYPE(version) == CHIP_8192E) ? TRUE : FALSE)
+#define IS_8812_SERIES(version)			((GET_CVID_IC_TYPE(version) == CHIP_8812) ? TRUE : FALSE)
+#define IS_8821_SERIES(version)			((GET_CVID_IC_TYPE(version) == CHIP_8821) ? TRUE : FALSE)
+#define IS_8814A_SERIES(version)			((GET_CVID_IC_TYPE(version) == CHIP_8814A) ? TRUE : FALSE)
+#define IS_8723B_SERIES(version)			((GET_CVID_IC_TYPE(version) == CHIP_8723B) ? TRUE : FALSE)
+#define IS_8703B_SERIES(version)			((GET_CVID_IC_TYPE(version) == CHIP_8703B) ? TRUE : FALSE)
+#define IS_8822B_SERIES(version)			((GET_CVID_IC_TYPE(version) == CHIP_8822B) ? TRUE : FALSE)
+#define IS_8821C_SERIES(version)			((GET_CVID_IC_TYPE(version) == CHIP_8821C) ? TRUE : FALSE)
+#define IS_8723D_SERIES(version)			((GET_CVID_IC_TYPE(version) == CHIP_8723D) ? TRUE : FALSE)
+#define IS_8710B_SERIES(version)			((GET_CVID_IC_TYPE(version) == CHIP_8710B) ? TRUE : FALSE)
+
+#define IS_8192F_SERIES(version)\
+	((GET_CVID_IC_TYPE(version) == CHIP_8192F) ? TRUE : FALSE)
+/* HAL_CHIP_TYPE_E */
+#define IS_TEST_CHIP(version)			((GET_CVID_CHIP_TYPE(version) == TEST_CHIP) ? TRUE : FALSE)
+#define IS_NORMAL_CHIP(version)			((GET_CVID_CHIP_TYPE(version) == NORMAL_CHIP) ? TRUE : FALSE)
+
+/* HAL_CUT_VERSION_E */
+#define IS_A_CUT(version)				((GET_CVID_CUT_VERSION(version) == A_CUT_VERSION) ? TRUE : FALSE)
+#define IS_B_CUT(version)				((GET_CVID_CUT_VERSION(version) == B_CUT_VERSION) ? TRUE : FALSE)
+#define IS_C_CUT(version)				((GET_CVID_CUT_VERSION(version) == C_CUT_VERSION) ? TRUE : FALSE)
+#define IS_D_CUT(version)				((GET_CVID_CUT_VERSION(version) == D_CUT_VERSION) ? TRUE : FALSE)
+#define IS_E_CUT(version)				((GET_CVID_CUT_VERSION(version) == E_CUT_VERSION) ? TRUE : FALSE)
+#define IS_F_CUT(version)				((GET_CVID_CUT_VERSION(version) == F_CUT_VERSION) ? TRUE : FALSE)
+#define IS_I_CUT(version)				((GET_CVID_CUT_VERSION(version) == I_CUT_VERSION) ? TRUE : FALSE)
+#define IS_J_CUT(version)				((GET_CVID_CUT_VERSION(version) == J_CUT_VERSION) ? TRUE : FALSE)
+#define IS_K_CUT(version)				((GET_CVID_CUT_VERSION(version) == K_CUT_VERSION) ? TRUE : FALSE)
+
+/* HAL_VENDOR_E */
+#define IS_CHIP_VENDOR_TSMC(version)	((GET_CVID_MANUFACTUER(version) == CHIP_VENDOR_TSMC) ? TRUE : FALSE)
+#define IS_CHIP_VENDOR_UMC(version)	((GET_CVID_MANUFACTUER(version) == CHIP_VENDOR_UMC) ? TRUE : FALSE)
+#define IS_CHIP_VENDOR_SMIC(version)	((GET_CVID_MANUFACTUER(version) == CHIP_VENDOR_SMIC) ? TRUE : FALSE)
+
+/* HAL_RF_TYPE_E */
+#define IS_1T1R(version)					((GET_CVID_RF_TYPE(version) == RF_TYPE_1T1R) ? TRUE : FALSE)
+#define IS_1T2R(version)					((GET_CVID_RF_TYPE(version) == RF_TYPE_1T2R) ? TRUE : FALSE)
+#define IS_2T2R(version)					((GET_CVID_RF_TYPE(version) == RF_TYPE_2T2R) ? TRUE : FALSE)
+#define IS_3T3R(version)					((GET_CVID_RF_TYPE(version) == RF_TYPE_3T3R) ? TRUE : FALSE)
+#define IS_3T4R(version)					((GET_CVID_RF_TYPE(version) == RF_TYPE_3T4R) ? TRUE : FALSE)
+#define IS_4T4R(version)					((GET_CVID_RF_TYPE(version) == RF_TYPE_4T4R) ? TRUE : FALSE)
+
+
+
+/* ----------------------------------------------------------------------------
+ * Chip version Macro. --
+ * ---------------------------------------------------------------------------- */
+#if 0
+	#define IS_81XXC_TEST_CHIP(version)		((IS_81XXC(version) && (!IS_NORMAL_CHIP(version))) ? TRUE : FALSE)
+
+	#define IS_92C_SERIAL(version)					((IS_81XXC(version) && IS_2T2R(version)) ? TRUE : FALSE)
+	#define IS_81xxC_VENDOR_UMC_A_CUT(version)	(IS_81XXC(version) ? (IS_CHIP_VENDOR_UMC(version) ? (IS_A_CUT(version) ? TRUE : FALSE) : FALSE) : FALSE)
+	#define IS_81xxC_VENDOR_UMC_B_CUT(version)	(IS_81XXC(version) ? (IS_CHIP_VENDOR_UMC(version) ? (IS_B_CUT(version) ? TRUE : FALSE) : FALSE) : FALSE)
+	#define IS_81xxC_VENDOR_UMC_C_CUT(version)	(IS_81XXC(version) ? (IS_CHIP_VENDOR_UMC(version) ? (IS_C_CUT(version) ? TRUE : FALSE) : FALSE) : FALSE)
+
+	#define IS_NORMAL_CHIP92D(version)		((IS_92D(version)) ? ((GET_CVID_CHIP_TYPE(version) == NORMAL_CHIP) ? TRUE : FALSE) : FALSE)
+
+	#define IS_92D_SINGLEPHY(version)		((IS_92D(version)) ? (IS_2T2R(version) ? TRUE : FALSE) : FALSE)
+	#define IS_92D_C_CUT(version)			((IS_92D(version)) ? (IS_C_CUT(version) ? TRUE : FALSE) : FALSE)
+	#define IS_92D_D_CUT(version)			((IS_92D(version)) ? (IS_D_CUT(version) ? TRUE : FALSE) : FALSE)
+	#define IS_92D_E_CUT(version)			((IS_92D(version)) ? (IS_E_CUT(version) ? TRUE : FALSE) : FALSE)
+
+	#define IS_8723A_A_CUT(version)				((IS_8723_SERIES(version)) ? (IS_A_CUT(version) ? TRUE : FALSE) : FALSE)
+	#define IS_8723A_B_CUT(version)				((IS_8723_SERIES(version)) ? (IS_B_CUT(version) ? TRUE : FALSE) : FALSE)
+#endif
+#define IS_VENDOR_8188E_I_CUT_SERIES(_Adapter)		((IS_8188E(GET_HAL_DATA(_Adapter)->version_id)) ? ((GET_CVID_CUT_VERSION(GET_HAL_DATA(_Adapter)->version_id) >= I_CUT_VERSION) ? TRUE : FALSE) : FALSE)
+#define IS_VENDOR_8812A_TEST_CHIP(_Adapter)		((IS_8812_SERIES(GET_HAL_DATA(_Adapter)->version_id)) ? ((IS_NORMAL_CHIP(GET_HAL_DATA(_Adapter)->version_id)) ? FALSE : TRUE) : FALSE)
+#define IS_VENDOR_8812A_MP_CHIP(_Adapter)		((IS_8812_SERIES(GET_HAL_DATA(_Adapter)->version_id)) ? ((IS_NORMAL_CHIP(GET_HAL_DATA(_Adapter)->version_id)) ? TRUE : FALSE) : FALSE)
+#define IS_VENDOR_8812A_C_CUT(_Adapter)			((IS_8812_SERIES(GET_HAL_DATA(_Adapter)->version_id)) ? ((GET_CVID_CUT_VERSION(GET_HAL_DATA(_Adapter)->version_id) == C_CUT_VERSION) ? TRUE : FALSE) : FALSE)
+
+#define IS_VENDOR_8821A_TEST_CHIP(_Adapter)	((IS_8821_SERIES(GET_HAL_DATA(_Adapter)->version_id)) ? ((IS_NORMAL_CHIP(GET_HAL_DATA(_Adapter)->version_id)) ? FALSE : TRUE) : FALSE)
+#define IS_VENDOR_8821A_MP_CHIP(_Adapter)		((IS_8821_SERIES(GET_HAL_DATA(_Adapter)->version_id)) ? ((IS_NORMAL_CHIP(GET_HAL_DATA(_Adapter)->version_id)) ? TRUE : FALSE) : FALSE)
+
+#define IS_VENDOR_8192E_B_CUT(_Adapter)		((GET_CVID_CUT_VERSION(GET_HAL_DATA(_Adapter)->version_id) == B_CUT_VERSION) ? TRUE : FALSE)
+
+#define IS_VENDOR_8723B_TEST_CHIP(_Adapter)	((IS_8723B_SERIES(GET_HAL_DATA(_Adapter)->version_id)) ? ((IS_NORMAL_CHIP(GET_HAL_DATA(_Adapter)->version_id)) ? FALSE : TRUE) : FALSE)
+#define IS_VENDOR_8723B_MP_CHIP(_Adapter)		((IS_8723B_SERIES(GET_HAL_DATA(_Adapter)->version_id)) ? ((IS_NORMAL_CHIP(GET_HAL_DATA(_Adapter)->version_id)) ? TRUE : FALSE) : FALSE)
+
+#define IS_VENDOR_8703B_TEST_CHIP(_Adapter)	((IS_8703B_SERIES(GET_HAL_DATA(_Adapter)->version_id)) ? ((IS_NORMAL_CHIP(GET_HAL_DATA(_Adapter)->version_id)) ? FALSE : TRUE) : FALSE)
+#define IS_VENDOR_8703B_MP_CHIP(_Adapter)		((IS_8703B_SERIES(GET_HAL_DATA(_Adapter)->version_id)) ? ((IS_NORMAL_CHIP(GET_HAL_DATA(_Adapter)->version_id)) ? TRUE : FALSE) : FALSE)
+#define IS_VENDOR_8814A_TEST_CHIP(_Adapter)	((IS_8814A_SERIES(GET_HAL_DATA(_Adapter)->version_id)) ? ((IS_NORMAL_CHIP(GET_HAL_DATA(_Adapter)->version_id)) ? FALSE : TRUE) : FALSE)
+#define IS_VENDOR_8814A_MP_CHIP(_Adapter)		((IS_8814A_SERIES(GET_HAL_DATA(_Adapter)->version_id)) ? ((IS_NORMAL_CHIP(GET_HAL_DATA(_Adapter)->version_id)) ? TRUE : FALSE) : FALSE)
+
+#endif
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/include/ieee80211_ext.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/ieee80211_ext.h
--- linux-5.6.3/3rdparty/rtl8821ce/include/ieee80211_ext.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/ieee80211_ext.h	2020-04-10 16:35:06.847661515 +0300
@@ -0,0 +1,471 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#ifndef __IEEE80211_EXT_H
+#define __IEEE80211_EXT_H
+
+#include <drv_conf.h>
+#include <osdep_service.h>
+#include <drv_types.h>
+
+#define WMM_OUI_TYPE 2
+#define WMM_OUI_SUBTYPE_INFORMATION_ELEMENT 0
+#define WMM_OUI_SUBTYPE_PARAMETER_ELEMENT 1
+#define WMM_OUI_SUBTYPE_TSPEC_ELEMENT 2
+#define WMM_VERSION 1
+
+#define WPA_PROTO_WPA BIT(0)
+#define WPA_PROTO_RSN BIT(1)
+
+#define WPA_KEY_MGMT_IEEE8021X BIT(0)
+#define WPA_KEY_MGMT_PSK BIT(1)
+#define WPA_KEY_MGMT_NONE BIT(2)
+#define WPA_KEY_MGMT_IEEE8021X_NO_WPA BIT(3)
+#define WPA_KEY_MGMT_WPA_NONE BIT(4)
+
+
+#define WPA_CAPABILITY_PREAUTH BIT(0)
+#define WPA_CAPABILITY_MGMT_FRAME_PROTECTION BIT(6)
+#define WPA_CAPABILITY_PEERKEY_ENABLED BIT(9)
+
+
+#define PMKID_LEN 16
+
+
+#ifdef PLATFORM_LINUX
+struct wpa_ie_hdr {
+	u8 elem_id;
+	u8 len;
+	u8 oui[4]; /* 24-bit OUI followed by 8-bit OUI type */
+	u8 version[2]; /* little endian */
+} __attribute__((packed));
+
+struct rsn_ie_hdr {
+	u8 elem_id; /* WLAN_EID_RSN */
+	u8 len;
+	u8 version[2]; /* little endian */
+} __attribute__((packed));
+
+struct wme_ac_parameter {
+#if defined(CONFIG_LITTLE_ENDIAN)
+	/* byte 1 */
+	u8	aifsn:4,
+	     acm:1,
+	     aci:2,
+	     reserved:1;
+
+	/* byte 2 */
+	u8	eCWmin:4,
+	     eCWmax:4;
+#elif defined(CONFIG_BIG_ENDIAN)
+	/* byte 1 */
+	u8	reserved:1,
+	     aci:2,
+	     acm:1,
+	     aifsn:4;
+
+	/* byte 2 */
+	u8	eCWmax:4,
+	     eCWmin:4;
+#else
+#error	"Please fix <endian.h>"
+#endif
+
+	/* bytes 3 & 4 */
+	u16 txopLimit;
+} __attribute__((packed));
+
+struct wme_parameter_element {
+	/* required fields for WME version 1 */
+	u8 oui[3];
+	u8 oui_type;
+	u8 oui_subtype;
+	u8 version;
+	u8 acInfo;
+	u8 reserved;
+	struct wme_ac_parameter ac[4];
+
+} __attribute__((packed));
+
+#endif
+
+#ifdef PLATFORM_WINDOWS
+
+#pragma pack(1)
+
+struct wpa_ie_hdr {
+	u8 elem_id;
+	u8 len;
+	u8 oui[4]; /* 24-bit OUI followed by 8-bit OUI type */
+	u8 version[2]; /* little endian */
+};
+
+struct rsn_ie_hdr {
+	u8 elem_id; /* WLAN_EID_RSN */
+	u8 len;
+	u8 version[2]; /* little endian */
+};
+
+#pragma pack()
+
+#endif
+
+#define WPA_PUT_LE16(a, val)			\
+	do {					\
+		(a)[1] = ((u16) (val)) >> 8;	\
+		(a)[0] = ((u16) (val)) & 0xff;	\
+	} while (0)
+
+#define WPA_PUT_BE32(a, val)					\
+	do {							\
+		(a)[0] = (u8) ((((u32) (val)) >> 24) & 0xff);	\
+		(a)[1] = (u8) ((((u32) (val)) >> 16) & 0xff);	\
+		(a)[2] = (u8) ((((u32) (val)) >> 8) & 0xff);	\
+		(a)[3] = (u8) (((u32) (val)) & 0xff);		\
+	} while (0)
+
+#define WPA_PUT_LE32(a, val)					\
+	do {							\
+		(a)[3] = (u8) ((((u32) (val)) >> 24) & 0xff);	\
+		(a)[2] = (u8) ((((u32) (val)) >> 16) & 0xff);	\
+		(a)[1] = (u8) ((((u32) (val)) >> 8) & 0xff);	\
+		(a)[0] = (u8) (((u32) (val)) & 0xff);		\
+	} while (0)
+
+#define RSN_SELECTOR_PUT(a, val) WPA_PUT_BE32((u8 *) (a), (val))
+/* #define RSN_SELECTOR_PUT(a, val) WPA_PUT_LE32((u8 *) (a), (val)) */
+
+
+
+/* Action category code */
+enum ieee80211_category {
+	WLAN_CATEGORY_SPECTRUM_MGMT = 0,
+	WLAN_CATEGORY_QOS = 1,
+	WLAN_CATEGORY_DLS = 2,
+	WLAN_CATEGORY_BACK = 3,
+	WLAN_CATEGORY_HT = 7,
+	WLAN_CATEGORY_WMM = 17,
+};
+
+/* SPECTRUM_MGMT action code */
+enum ieee80211_spectrum_mgmt_actioncode {
+	WLAN_ACTION_SPCT_MSR_REQ = 0,
+	WLAN_ACTION_SPCT_MSR_RPRT = 1,
+	WLAN_ACTION_SPCT_TPC_REQ = 2,
+	WLAN_ACTION_SPCT_TPC_RPRT = 3,
+	WLAN_ACTION_SPCT_CHL_SWITCH = 4,
+	WLAN_ACTION_SPCT_EXT_CHL_SWITCH = 5,
+};
+
+/* BACK action code */
+enum ieee80211_back_actioncode {
+	WLAN_ACTION_ADDBA_REQ = 0,
+	WLAN_ACTION_ADDBA_RESP = 1,
+	WLAN_ACTION_DELBA = 2,
+};
+
+/* HT features action code */
+enum ieee80211_ht_actioncode {
+	WLAN_ACTION_NOTIFY_CH_WIDTH = 0,
+	WLAN_ACTION_SM_PS = 1,
+	WLAN_ACTION_PSPM = 2,
+	WLAN_ACTION_PCO_PHASE = 3,
+	WLAN_ACTION_MIMO_CSI_MX = 4,
+	WLAN_ACTION_MIMO_NONCP_BF = 5,
+	WLAN_ACTION_MIMP_CP_BF = 6,
+	WLAN_ACTION_ASEL_INDICATES_FB = 7,
+	WLAN_ACTION_HI_INFO_EXCHG = 8,
+};
+
+/* BACK (block-ack) parties */
+enum ieee80211_back_parties {
+	WLAN_BACK_RECIPIENT = 0,
+	WLAN_BACK_INITIATOR = 1,
+	WLAN_BACK_TIMER = 2,
+};
+
+#ifdef PLATFORM_LINUX
+
+struct ieee80211_mgmt {
+	u16 frame_control;
+	u16 duration;
+	u8 da[6];
+	u8 sa[6];
+	u8 bssid[6];
+	u16 seq_ctrl;
+	union {
+		struct {
+			u16 auth_alg;
+			u16 auth_transaction;
+			u16 status_code;
+			/* possibly followed by Challenge text */
+			u8 variable[0];
+		}  __attribute__((packed)) auth;
+		struct {
+			u16 reason_code;
+		}  __attribute__((packed)) deauth;
+		struct {
+			u16 capab_info;
+			u16 listen_interval;
+			/* followed by SSID and Supported rates */
+			u8 variable[0];
+		}  __attribute__((packed)) assoc_req;
+		struct {
+			u16 capab_info;
+			u16 status_code;
+			u16 aid;
+			/* followed by Supported rates */
+			u8 variable[0];
+		}  __attribute__((packed)) assoc_resp, reassoc_resp;
+		struct {
+			u16 capab_info;
+			u16 listen_interval;
+			u8 current_ap[6];
+			/* followed by SSID and Supported rates */
+			u8 variable[0];
+		}  __attribute__((packed)) reassoc_req;
+		struct {
+			u16 reason_code;
+		}  __attribute__((packed)) disassoc;
+		struct {
+			__le64 timestamp;
+			u16 beacon_int;
+			u16 capab_info;
+			/* followed by some of SSID, Supported rates,
+			 * FH Params, DS Params, CF Params, IBSS Params, TIM */
+			u8 variable[0];
+		}  __attribute__((packed)) beacon;
+		struct {
+			/* only variable items: SSID, Supported rates */
+			u8 variable[0];
+		}  __attribute__((packed)) probe_req;
+		struct {
+			__le64 timestamp;
+			u16 beacon_int;
+			u16 capab_info;
+			/* followed by some of SSID, Supported rates,
+			 * FH Params, DS Params, CF Params, IBSS Params */
+			u8 variable[0];
+		}  __attribute__((packed)) probe_resp;
+		struct {
+			u8 category;
+			union {
+				struct {
+					u8 action_code;
+					u8 dialog_token;
+					u8 status_code;
+					u8 variable[0];
+				}  __attribute__((packed)) wme_action;
+#if 0
+				struct {
+					u8 action_code;
+					u8 element_id;
+					u8 length;
+					struct ieee80211_channel_sw_ie sw_elem;
+				}  __attribute__((packed)) chan_switch;
+				struct {
+					u8 action_code;
+					u8 dialog_token;
+					u8 element_id;
+					u8 length;
+					struct ieee80211_msrment_ie msr_elem;
+				}  __attribute__((packed)) measurement;
+#endif
+				struct {
+					u8 action_code;
+					u8 dialog_token;
+					u16 capab;
+					u16 timeout;
+					u16 start_seq_num;
+				}  __attribute__((packed)) addba_req;
+				struct {
+					u8 action_code;
+					u8 dialog_token;
+					u16 status;
+					u16 capab;
+					u16 timeout;
+				}  __attribute__((packed)) addba_resp;
+				struct {
+					u8 action_code;
+					u16 params;
+					u16 reason_code;
+				}  __attribute__((packed)) delba;
+				struct {
+					u8 action_code;
+					/* capab_info for open and confirm,
+					 * reason for close
+					 */
+					u16 aux;
+					/* Followed in plink_confirm by status
+					 * code, AID and supported rates,
+					 * and directly by supported rates in
+					 * plink_open and plink_close
+					 */
+					u8 variable[0];
+				}  __attribute__((packed)) plink_action;
+				struct {
+					u8 action_code;
+					u8 variable[0];
+				}  __attribute__((packed)) mesh_action;
+			} __attribute__((packed)) u;
+		}  __attribute__((packed)) action;
+	} __attribute__((packed)) u;
+} __attribute__((packed));
+
+#endif
+
+
+#ifdef PLATFORM_WINDOWS
+
+#pragma pack(1)
+
+struct ieee80211_mgmt {
+	u16 frame_control;
+	u16 duration;
+	u8 da[6];
+	u8 sa[6];
+	u8 bssid[6];
+	u16 seq_ctrl;
+	union {
+		struct {
+			u16 auth_alg;
+			u16 auth_transaction;
+			u16 status_code;
+			/* possibly followed by Challenge text */
+			u8 variable[0];
+		}  auth;
+		struct {
+			u16 reason_code;
+		}  deauth;
+		struct {
+			u16 capab_info;
+			u16 listen_interval;
+			/* followed by SSID and Supported rates */
+			u8 variable[0];
+		}  assoc_req;
+		struct {
+			u16 capab_info;
+			u16 status_code;
+			u16 aid;
+			/* followed by Supported rates */
+			u8 variable[0];
+		}  assoc_resp, reassoc_resp;
+		struct {
+			u16 capab_info;
+			u16 listen_interval;
+			u8 current_ap[6];
+			/* followed by SSID and Supported rates */
+			u8 variable[0];
+		}  reassoc_req;
+		struct {
+			u16 reason_code;
+		}  disassoc;
+#if 0
+		struct {
+			__le64 timestamp;
+			u16 beacon_int;
+			u16 capab_info;
+			/* followed by some of SSID, Supported rates,
+			 * FH Params, DS Params, CF Params, IBSS Params, TIM */
+			u8 variable[0];
+		}  beacon;
+		struct {
+			/* only variable items: SSID, Supported rates */
+			u8 variable[0];
+		}  probe_req;
+
+		struct {
+			__le64 timestamp;
+			u16 beacon_int;
+			u16 capab_info;
+			/* followed by some of SSID, Supported rates,
+			 * FH Params, DS Params, CF Params, IBSS Params */
+			u8 variable[0];
+		}  probe_resp;
+#endif
+		struct {
+			u8 category;
+			union {
+				struct {
+					u8 action_code;
+					u8 dialog_token;
+					u8 status_code;
+					u8 variable[0];
+				}  wme_action;
+				#if 0
+				struct{
+					u8 action_code;
+					u8 element_id;
+					u8 length;
+					struct ieee80211_channel_sw_ie sw_elem;
+				}  chan_switch;
+				struct{
+					u8 action_code;
+					u8 dialog_token;
+					u8 element_id;
+					u8 length;
+					struct ieee80211_msrment_ie msr_elem;
+				}  measurement;
+				#endif
+				struct {
+					u8 action_code;
+					u8 dialog_token;
+					u16 capab;
+					u16 timeout;
+					u16 start_seq_num;
+				}  addba_req;
+				struct {
+					u8 action_code;
+					u8 dialog_token;
+					u16 status;
+					u16 capab;
+					u16 timeout;
+				}  addba_resp;
+				struct {
+					u8 action_code;
+					u16 params;
+					u16 reason_code;
+				}  delba;
+				struct {
+					u8 action_code;
+					/* capab_info for open and confirm,
+					 * reason for close
+					 */
+					u16 aux;
+					/* Followed in plink_confirm by status
+					 * code, AID and supported rates,
+					 * and directly by supported rates in
+					 * plink_open and plink_close
+					 */
+					u8 variable[0];
+				}  plink_action;
+				struct {
+					u8 action_code;
+					u8 variable[0];
+				}  mesh_action;
+			} u;
+		}  action;
+	} u;
+} ;
+
+#pragma pack()
+
+#endif
+
+/* mgmt header + 1 byte category code */
+#define IEEE80211_MIN_ACTION_SIZE FIELD_OFFSET(struct ieee80211_mgmt, u.action.u)
+
+
+
+#endif
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/include/ieee80211.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/ieee80211.h
--- linux-5.6.3/3rdparty/rtl8821ce/include/ieee80211.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/ieee80211.h	2020-04-10 16:35:06.847661515 +0300
@@ -0,0 +1,2172 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#ifndef __IEEE80211_H
+#define __IEEE80211_H
+
+
+#ifndef CONFIG_RTL8711FW
+
+	#if defined PLATFORM_OS_XP
+		#include <ntstrsafe.h>
+	#endif
+#else
+
+#endif
+
+#define MGMT_QUEUE_NUM 5
+
+#define ETH_ALEN	6
+#define ETH_TYPE_LEN		2
+#define PAYLOAD_TYPE_LEN	1
+
+#define NET80211_TU_TO_US	1024		/* unit:us */
+#define DEFAULT_BCN_INTERVAL 100 /* 100 ms */
+
+#ifdef CONFIG_AP_MODE
+
+#define RTL_IOCTL_HOSTAPD (SIOCIWFIRSTPRIV + 28)
+
+/* RTL871X_IOCTL_HOSTAPD ioctl() cmd: */
+enum {
+	RTL871X_HOSTAPD_FLUSH = 1,
+	RTL871X_HOSTAPD_ADD_STA = 2,
+	RTL871X_HOSTAPD_REMOVE_STA = 3,
+	RTL871X_HOSTAPD_GET_INFO_STA = 4,
+	/* REMOVED: PRISM2_HOSTAPD_RESET_TXEXC_STA = 5, */
+	RTL871X_HOSTAPD_GET_WPAIE_STA = 5,
+	RTL871X_SET_ENCRYPTION = 6,
+	RTL871X_GET_ENCRYPTION = 7,
+	RTL871X_HOSTAPD_SET_FLAGS_STA = 8,
+	RTL871X_HOSTAPD_GET_RID = 9,
+	RTL871X_HOSTAPD_SET_RID = 10,
+	RTL871X_HOSTAPD_SET_ASSOC_AP_ADDR = 11,
+	RTL871X_HOSTAPD_SET_GENERIC_ELEMENT = 12,
+	RTL871X_HOSTAPD_MLME = 13,
+	RTL871X_HOSTAPD_SCAN_REQ = 14,
+	RTL871X_HOSTAPD_STA_CLEAR_STATS = 15,
+	RTL871X_HOSTAPD_SET_BEACON = 16,
+	RTL871X_HOSTAPD_SET_WPS_BEACON = 17,
+	RTL871X_HOSTAPD_SET_WPS_PROBE_RESP = 18,
+	RTL871X_HOSTAPD_SET_WPS_ASSOC_RESP = 19,
+	RTL871X_HOSTAPD_SET_HIDDEN_SSID = 20,
+	RTL871X_HOSTAPD_SET_MACADDR_ACL = 21,
+	RTL871X_HOSTAPD_ACL_ADD_STA = 22,
+	RTL871X_HOSTAPD_ACL_REMOVE_STA = 23,
+};
+
+/* STA flags */
+#define WLAN_STA_AUTH BIT(0)
+#define WLAN_STA_ASSOC BIT(1)
+#define WLAN_STA_PS BIT(2)
+#define WLAN_STA_TIM BIT(3)
+#define WLAN_STA_PERM BIT(4)
+#define WLAN_STA_AUTHORIZED BIT(5)
+#define WLAN_STA_PENDING_POLL BIT(6) /* pending activity poll not ACKed */
+#define WLAN_STA_SHORT_PREAMBLE BIT(7)
+#define WLAN_STA_PREAUTH BIT(8)
+#define WLAN_STA_WME BIT(9)
+#define WLAN_STA_MFP BIT(10)
+#define WLAN_STA_HT BIT(11)
+#define WLAN_STA_WPS BIT(12)
+#define WLAN_STA_MAYBE_WPS BIT(13)
+#define WLAN_STA_VHT BIT(14)
+#define WLAN_STA_NONERP BIT(31)
+
+#endif
+
+#define IEEE_CMD_SET_WPA_PARAM			1
+#define IEEE_CMD_SET_WPA_IE				2
+#define IEEE_CMD_SET_ENCRYPTION			3
+#define IEEE_CMD_MLME						4
+
+#define IEEE_PARAM_WPA_ENABLED				1
+#define IEEE_PARAM_TKIP_COUNTERMEASURES		2
+#define IEEE_PARAM_DROP_UNENCRYPTED			3
+#define IEEE_PARAM_PRIVACY_INVOKED			4
+#define IEEE_PARAM_AUTH_ALGS					5
+#define IEEE_PARAM_IEEE_802_1X				6
+#define IEEE_PARAM_WPAX_SELECT				7
+
+#define AUTH_ALG_OPEN_SYSTEM			0x1
+#define AUTH_ALG_SHARED_KEY			0x2
+#define AUTH_ALG_LEAP				0x00000004
+
+#define IEEE_MLME_STA_DEAUTH				1
+#define IEEE_MLME_STA_DISASSOC			2
+
+#define IEEE_CRYPT_ERR_UNKNOWN_ALG			2
+#define IEEE_CRYPT_ERR_UNKNOWN_ADDR			3
+#define IEEE_CRYPT_ERR_CRYPT_INIT_FAILED		4
+#define IEEE_CRYPT_ERR_KEY_SET_FAILED			5
+#define IEEE_CRYPT_ERR_TX_KEY_SET_FAILED		6
+#define IEEE_CRYPT_ERR_CARD_CONF_FAILED		7
+
+
+#define	IEEE_CRYPT_ALG_NAME_LEN			16
+
+#define WPA_CIPHER_NONE	BIT(0)
+#define WPA_CIPHER_WEP40	BIT(1)
+#define WPA_CIPHER_WEP104 BIT(2)
+#define WPA_CIPHER_TKIP	BIT(3)
+#define WPA_CIPHER_CCMP	BIT(4)
+
+
+
+#define WPA_SELECTOR_LEN 4
+extern u8 RTW_WPA_OUI_TYPE[] ;
+extern u16 RTW_WPA_VERSION ;
+extern u8 WPA_AUTH_KEY_MGMT_NONE[];
+extern u8 WPA_AUTH_KEY_MGMT_UNSPEC_802_1X[];
+extern u8 WPA_AUTH_KEY_MGMT_PSK_OVER_802_1X[];
+extern u8 WPA_CIPHER_SUITE_NONE[];
+extern u8 WPA_CIPHER_SUITE_WEP40[];
+extern u8 WPA_CIPHER_SUITE_TKIP[];
+extern u8 WPA_CIPHER_SUITE_WRAP[];
+extern u8 WPA_CIPHER_SUITE_CCMP[];
+extern u8 WPA_CIPHER_SUITE_WEP104[];
+
+
+#define RSN_HEADER_LEN 4
+#define RSN_SELECTOR_LEN 4
+
+extern u16 RSN_VERSION_BSD;
+extern u8 RSN_AUTH_KEY_MGMT_UNSPEC_802_1X[];
+extern u8 RSN_AUTH_KEY_MGMT_PSK_OVER_802_1X[];
+extern u8 RSN_CIPHER_SUITE_NONE[];
+extern u8 RSN_CIPHER_SUITE_WEP40[];
+extern u8 RSN_CIPHER_SUITE_TKIP[];
+extern u8 RSN_CIPHER_SUITE_WRAP[];
+extern u8 RSN_CIPHER_SUITE_CCMP[];
+extern u8 RSN_CIPHER_SUITE_WEP104[];
+
+/* IEEE 802.11i */
+#define PMKID_LEN 16
+#define PMK_LEN 32
+#define PMK_LEN_SUITE_B_192 48
+#define PMK_LEN_MAX 48
+#define WPA_REPLAY_COUNTER_LEN 8
+#define WPA_NONCE_LEN 32
+#define WPA_KEY_RSC_LEN 8
+#define WPA_GMK_LEN 32
+#define WPA_GTK_MAX_LEN 32
+
+/* IEEE 802.11, 8.5.2 EAPOL-Key frames */
+#define WPA_KEY_INFO_TYPE_MASK ((u16) (BIT(0) | BIT(1) | BIT(2)))
+#define WPA_KEY_INFO_TYPE_AKM_DEFINED 0
+#define WPA_KEY_INFO_TYPE_HMAC_MD5_RC4 BIT(0)
+#define WPA_KEY_INFO_TYPE_HMAC_SHA1_AES BIT(1)
+#define WPA_KEY_INFO_TYPE_AES_128_CMAC 3
+#define WPA_KEY_INFO_KEY_TYPE BIT(3) /* 1 = Pairwise, 0 = Group key */
+/* bit4..5 is used in WPA, but is reserved in IEEE 802.11i/RSN */
+#define WPA_KEY_INFO_KEY_INDEX_MASK (BIT(4) | BIT(5))
+#define WPA_KEY_INFO_KEY_INDEX_SHIFT 4
+#define WPA_KEY_INFO_INSTALL BIT(6) /* pairwise */
+#define WPA_KEY_INFO_TXRX BIT(6) /* group */
+#define WPA_KEY_INFO_ACK BIT(7)
+#define WPA_KEY_INFO_MIC BIT(8)
+#define WPA_KEY_INFO_SECURE BIT(9)
+#define WPA_KEY_INFO_ERROR BIT(10)
+#define WPA_KEY_INFO_REQUEST BIT(11)
+#define WPA_KEY_INFO_ENCR_KEY_DATA BIT(12) /* IEEE 802.11i/RSN only */
+#define WPA_KEY_INFO_SMK_MESSAGE BIT(13)
+
+struct ieee802_1x_hdr {
+	u8 version;
+	u8 type;
+	u16 length;
+	/* followed by length octets of data */
+};
+
+struct wpa_eapol_key {
+	u8 type;
+	/* Note: key_info, key_length, and key_data_length are unaligned */
+	u8 key_info[2]; /* big endian */
+	u8 key_length[2]; /* big endian */
+	u8 replay_counter[WPA_REPLAY_COUNTER_LEN];
+	u8 key_nonce[WPA_NONCE_LEN];
+	u8 key_iv[16];
+	u8 key_rsc[WPA_KEY_RSC_LEN];
+	u8 key_id[8]; /* Reserved in IEEE 802.11i/RSN */
+	u8 key_mic[16];
+	u8 key_data_length[2]; /* big endian */
+	/* followed by key_data_length bytes of key_data */
+};
+
+typedef enum _RATEID_IDX_ {
+	RATEID_IDX_BGN_40M_2SS = 0,
+	RATEID_IDX_BGN_40M_1SS = 1,
+	RATEID_IDX_BGN_20M_2SS_BN = 2,
+	RATEID_IDX_BGN_20M_1SS_BN = 3,
+	RATEID_IDX_GN_N2SS = 4,
+	RATEID_IDX_GN_N1SS = 5,
+	RATEID_IDX_BG = 6,
+	RATEID_IDX_G = 7,
+	RATEID_IDX_B = 8,
+	RATEID_IDX_VHT_2SS = 9,
+	RATEID_IDX_VHT_1SS = 10,
+	RATEID_IDX_MIX1 = 11,
+	RATEID_IDX_MIX2 = 12,
+	RATEID_IDX_VHT_3SS = 13,
+	RATEID_IDX_BGN_3SS = 14,
+} RATEID_IDX, *PRATEID_IDX;
+
+typedef enum _RATR_TABLE_MODE {
+	RATR_INX_WIRELESS_NGB = 0,	/* BGN 40 Mhz 2SS 1SS */
+	RATR_INX_WIRELESS_NG = 1,		/* GN or N */
+	RATR_INX_WIRELESS_NB = 2,		/* BGN 20 Mhz 2SS 1SS  or BN */
+	RATR_INX_WIRELESS_N = 3,
+	RATR_INX_WIRELESS_GB = 4,
+	RATR_INX_WIRELESS_G = 5,
+	RATR_INX_WIRELESS_B = 6,
+	RATR_INX_WIRELESS_MC = 7,
+	RATR_INX_WIRELESS_AC_N = 8,
+} RATR_TABLE_MODE, *PRATR_TABLE_MODE;
+
+
+enum NETWORK_TYPE {
+	WIRELESS_INVALID = 0,
+	/* Sub-Element */
+	WIRELESS_11B = BIT(0), /* tx: cck only , rx: cck only, hw: cck */
+	WIRELESS_11G = BIT(1), /* tx: ofdm only, rx: ofdm & cck, hw: cck & ofdm */
+	WIRELESS_11A = BIT(2), /* tx: ofdm only, rx: ofdm only, hw: ofdm only */
+	WIRELESS_11_24N = BIT(3), /* tx: MCS only, rx: MCS & cck, hw: MCS & cck */
+	WIRELESS_11_5N = BIT(4), /* tx: MCS only, rx: MCS & ofdm, hw: ofdm only */
+	WIRELESS_AUTO = BIT(5),
+	WIRELESS_11AC = BIT(6),
+
+	/* Combination */
+	/* Type for current wireless mode */
+	WIRELESS_11BG = (WIRELESS_11B | WIRELESS_11G), /* tx: cck & ofdm, rx: cck & ofdm & MCS, hw: cck & ofdm */
+	WIRELESS_11G_24N = (WIRELESS_11G | WIRELESS_11_24N), /* tx: ofdm & MCS, rx: ofdm & cck & MCS, hw: cck & ofdm */
+	WIRELESS_11A_5N = (WIRELESS_11A | WIRELESS_11_5N), /* tx: ofdm & MCS, rx: ofdm & MCS, hw: ofdm only */
+	WIRELESS_11B_24N = (WIRELESS_11B | WIRELESS_11_24N), /* tx: ofdm & cck & MCS, rx: ofdm & cck & MCS, hw: ofdm & cck */
+	WIRELESS_11BG_24N = (WIRELESS_11B | WIRELESS_11G | WIRELESS_11_24N), /* tx: ofdm & cck & MCS, rx: ofdm & cck & MCS, hw: ofdm & cck */
+	WIRELESS_11_24AC = (WIRELESS_11B | WIRELESS_11G | WIRELESS_11AC),
+	WIRELESS_11_5AC = (WIRELESS_11A | WIRELESS_11AC),
+
+
+	/* Type for registry default wireless mode */
+	WIRELESS_11AGN = (WIRELESS_11A | WIRELESS_11G | WIRELESS_11_24N | WIRELESS_11_5N), /* tx: ofdm & MCS, rx: ofdm & MCS, hw: ofdm only */
+	WIRELESS_11ABGN = (WIRELESS_11A | WIRELESS_11B | WIRELESS_11G | WIRELESS_11_24N | WIRELESS_11_5N),
+	WIRELESS_MODE_24G = (WIRELESS_11B | WIRELESS_11G | WIRELESS_11_24N),
+	WIRELESS_MODE_5G = (WIRELESS_11A | WIRELESS_11_5N | WIRELESS_11AC),
+	WIRELESS_MODE_MAX = (WIRELESS_11A | WIRELESS_11B | WIRELESS_11G | WIRELESS_11_24N | WIRELESS_11_5N | WIRELESS_11AC),
+};
+
+#define SUPPORTED_24G_NETTYPE_MSK WIRELESS_MODE_24G
+#define SUPPORTED_5G_NETTYPE_MSK WIRELESS_MODE_5G
+
+#define IsLegacyOnly(NetType)  ((NetType) == ((NetType) & (WIRELESS_11BG | WIRELESS_11A)))
+
+#define IsSupported24G(NetType) ((NetType) & SUPPORTED_24G_NETTYPE_MSK ? _TRUE : _FALSE)
+#define is_supported_5g(NetType) ((NetType) & SUPPORTED_5G_NETTYPE_MSK ? _TRUE : _FALSE)
+
+#define IsEnableHWCCK(NetType) IsSupported24G(NetType)
+#define IsEnableHWOFDM(NetType) ((NetType) & (WIRELESS_11G | WIRELESS_11_24N | SUPPORTED_5G_NETTYPE_MSK) ? _TRUE : _FALSE)
+
+#define IsSupportedRxCCK(NetType) IsEnableHWCCK(NetType)
+#define IsSupportedRxOFDM(NetType) IsEnableHWOFDM(NetType)
+#define IsSupportedRxHT(NetType) IsEnableHWOFDM(NetType)
+
+#define IsSupportedTxCCK(NetType) ((NetType) & (WIRELESS_11B) ? _TRUE : _FALSE)
+#define IsSupportedTxOFDM(NetType) ((NetType) & (WIRELESS_11G | WIRELESS_11A) ? _TRUE : _FALSE)
+#define is_supported_ht(NetType) ((NetType) & (WIRELESS_11_24N | WIRELESS_11_5N) ? _TRUE : _FALSE)
+
+#define is_supported_vht(NetType) ((NetType) & (WIRELESS_11AC) ? _TRUE : _FALSE)
+
+
+
+
+
+typedef struct ieee_param {
+	u32 cmd;
+	u8 sta_addr[ETH_ALEN];
+	union {
+		struct {
+			u8 name;
+			u32 value;
+		} wpa_param;
+		struct {
+			u32 len;
+			u8 reserved[32];
+			u8 data[0];
+		} wpa_ie;
+		struct {
+			int command;
+			int reason_code;
+		} mlme;
+		struct {
+			u8 alg[IEEE_CRYPT_ALG_NAME_LEN];
+			u8 set_tx;
+			u32 err;
+			u8 idx;
+			u8 seq[8]; /* sequence counter (set: RX, get: TX) */
+			u16 key_len;
+			u8 key[0];
+		} crypt;
+#ifdef CONFIG_AP_MODE
+		struct {
+			u16 aid;
+			u16 capability;
+			int flags;
+			u8 tx_supp_rates[16];
+			struct rtw_ieee80211_ht_cap ht_cap;
+		} add_sta;
+		struct {
+			u8	reserved[2];/* for set max_num_sta */
+			u8	buf[0];
+		} bcn_ie;
+#endif
+
+	} u;
+} ieee_param;
+
+#ifdef CONFIG_AP_MODE
+typedef struct ieee_param_ex {
+	u32 cmd;
+	u8 sta_addr[ETH_ALEN];
+	u8 data[0];
+} ieee_param_ex;
+
+struct sta_data {
+	u16 aid;
+	u16 capability;
+	int flags;
+	u32 sta_set;
+	u8 tx_supp_rates[16];
+	u32 tx_supp_rates_len;
+	struct rtw_ieee80211_ht_cap ht_cap;
+	u64	rx_pkts;
+	u64	rx_bytes;
+	u64	rx_drops;
+	u64	tx_pkts;
+	u64	tx_bytes;
+	u64	tx_drops;
+};
+#endif
+
+
+#if WIRELESS_EXT < 17
+	#define IW_QUAL_QUAL_INVALID   0x10
+	#define IW_QUAL_LEVEL_INVALID  0x20
+	#define IW_QUAL_NOISE_INVALID  0x40
+	#define IW_QUAL_QUAL_UPDATED   0x1
+	#define IW_QUAL_LEVEL_UPDATED  0x2
+	#define IW_QUAL_NOISE_UPDATED  0x4
+#endif
+
+#define IEEE80211_DATA_LEN		2304
+/* Maximum size for the MA-UNITDATA primitive, 802.11 standard section
+   6.2.1.1.2.
+
+   The figure in section 7.1.2 suggests a body size of up to 2312
+   bytes is allowed, which is a bit confusing, I suspect this
+   represents the 2304 bytes of real data, plus a possible 8 bytes of
+   WEP IV and ICV. (this interpretation suggested by Ramiro Barreiro) */
+
+
+#define IEEE80211_HLEN			30
+#define IEEE80211_FRAME_LEN		(IEEE80211_DATA_LEN + IEEE80211_HLEN)
+
+
+/* this is stolen from ipw2200 driver */
+#define IEEE_IBSS_MAC_HASH_SIZE 31
+
+struct ieee_ibss_seq {
+	u8 mac[ETH_ALEN];
+	u16 seq_num;
+	u16 frag_num;
+	unsigned long packet_time;
+	_list	list;
+};
+
+#if defined(PLATFORM_LINUX) || defined(CONFIG_RTL8711FW) || defined(PLATFORM_FREEBSD)
+
+struct rtw_ieee80211_hdr {
+	u16 frame_ctl;
+	u16 duration_id;
+	u8 addr1[ETH_ALEN];
+	u8 addr2[ETH_ALEN];
+	u8 addr3[ETH_ALEN];
+	u16 seq_ctl;
+	u8 addr4[ETH_ALEN];
+} __attribute__((packed));
+
+struct rtw_ieee80211_hdr_3addr {
+	u16 frame_ctl;
+	u16 duration_id;
+	u8 addr1[ETH_ALEN];
+	u8 addr2[ETH_ALEN];
+	u8 addr3[ETH_ALEN];
+	u16 seq_ctl;
+} __attribute__((packed));
+
+
+struct rtw_ieee80211_hdr_qos {
+	u16 frame_ctl;
+	u16 duration_id;
+	u8 addr1[ETH_ALEN];
+	u8 addr2[ETH_ALEN];
+	u8 addr3[ETH_ALEN];
+	u16 seq_ctl;
+	u8 addr4[ETH_ALEN];
+	u16	qc;
+}  __attribute__((packed));
+
+struct rtw_ieee80211_hdr_3addr_qos {
+	u16 frame_ctl;
+	u16 duration_id;
+	u8 addr1[ETH_ALEN];
+	u8 addr2[ETH_ALEN];
+	u8 addr3[ETH_ALEN];
+	u16 seq_ctl;
+	u16     qc;
+}  __attribute__((packed));
+
+struct eapol {
+	u8 snap[6];
+	u16 ethertype;
+	u8 version;
+	u8 type;
+	u16 length;
+} __attribute__((packed));
+
+struct rtw_ieee80211s_hdr {
+	u8 flags;
+	u8 ttl;
+	u32 seqnum;
+	u8 eaddr1[ETH_ALEN];
+	u8 eaddr2[ETH_ALEN];
+} __attribute__((packed));
+
+/**
+ * struct rtw_ieee80211_rann_ie
+ *
+ * This structure refers to "Root Announcement information element"
+ */
+ struct rtw_ieee80211_rann_ie {
+	u8 rann_flags;
+	u8 rann_hopcount;
+	u8 rann_ttl;
+	u8 rann_addr[ETH_ALEN];
+	u32 rann_seq;
+	u32 rann_interval;
+	u32 rann_metric;
+} __attribute__((packed));
+#endif
+
+
+
+#ifdef PLATFORM_WINDOWS
+
+#pragma pack(1)
+struct rtw_ieee80211_hdr {
+	u16 frame_ctl;
+	u16 duration_id;
+	u8 addr1[ETH_ALEN];
+	u8 addr2[ETH_ALEN];
+	u8 addr3[ETH_ALEN];
+	u16 seq_ctl;
+	u8 addr4[ETH_ALEN];
+};
+
+struct rtw_ieee80211_hdr_3addr {
+	u16 frame_ctl;
+	u16 duration_id;
+	u8 addr1[ETH_ALEN];
+	u8 addr2[ETH_ALEN];
+	u8 addr3[ETH_ALEN];
+	u16 seq_ctl;
+};
+
+
+struct rtw_ieee80211_hdr_qos {
+	struct rtw_ieee80211_hdr wlan_hdr;
+	u16	qc;
+};
+
+struct rtw_ieee80211_hdr_3addr_qos {
+	struct  rtw_ieee80211_hdr_3addr wlan_hdr;
+	u16     qc;
+};
+
+struct eapol {
+	u8 snap[6];
+	u16 ethertype;
+	u8 version;
+	u8 type;
+	u16 length;
+};
+#pragma pack()
+
+#endif
+
+
+
+enum eap_type {
+	EAP_PACKET = 0,
+	EAPOL_START,
+	EAPOL_LOGOFF,
+	EAPOL_KEY,
+	EAPOL_ENCAP_ASF_ALERT
+};
+
+#define IEEE80211_3ADDR_LEN 24
+#define IEEE80211_4ADDR_LEN 30
+#define IEEE80211_FCS_LEN    4
+
+#define MIN_FRAG_THRESHOLD     256U
+#define	MAX_FRAG_THRESHOLD     2346U
+
+/* Frame control field constants */
+#define RTW_IEEE80211_FCTL_VERS		0x0003
+#define RTW_IEEE80211_FCTL_FTYPE		0x000c
+#define RTW_IEEE80211_FCTL_STYPE		0x00f0
+#define RTW_IEEE80211_FCTL_TODS		0x0100
+#define RTW_IEEE80211_FCTL_FROMDS	0x0200
+#define RTW_IEEE80211_FCTL_MOREFRAGS	0x0400
+#define RTW_IEEE80211_FCTL_RETRY		0x0800
+#define RTW_IEEE80211_FCTL_PM		0x1000
+#define RTW_IEEE80211_FCTL_MOREDATA	0x2000
+#define RTW_IEEE80211_FCTL_PROTECTED	0x4000
+#define RTW_IEEE80211_FCTL_ORDER		0x8000
+#define RTW_IEEE80211_FCTL_CTL_EXT	0x0f00
+
+#define RTW_IEEE80211_FTYPE_MGMT		0x0000
+#define RTW_IEEE80211_FTYPE_CTL		0x0004
+#define RTW_IEEE80211_FTYPE_DATA		0x0008
+#define RTW_IEEE80211_FTYPE_EXT		0x000c
+
+/* management */
+#define RTW_IEEE80211_STYPE_ASSOC_REQ	0x0000
+#define RTW_IEEE80211_STYPE_ASSOC_RESP	0x0010
+#define RTW_IEEE80211_STYPE_REASSOC_REQ	0x0020
+#define RTW_IEEE80211_STYPE_REASSOC_RESP	0x0030
+#define RTW_IEEE80211_STYPE_PROBE_REQ	0x0040
+#define RTW_IEEE80211_STYPE_PROBE_RESP	0x0050
+#define RTW_IEEE80211_STYPE_BEACON		0x0080
+#define RTW_IEEE80211_STYPE_ATIM		0x0090
+#define RTW_IEEE80211_STYPE_DISASSOC	0x00A0
+#define RTW_IEEE80211_STYPE_AUTH		0x00B0
+#define RTW_IEEE80211_STYPE_DEAUTH		0x00C0
+#define RTW_IEEE80211_STYPE_ACTION		0x00D0
+
+/* control */
+#define RTW_IEEE80211_STYPE_CTL_EXT		0x0060
+#define RTW_IEEE80211_STYPE_BACK_REQ		0x0080
+#define RTW_IEEE80211_STYPE_BACK		0x0090
+#define RTW_IEEE80211_STYPE_PSPOLL		0x00A0
+#define RTW_IEEE80211_STYPE_RTS		0x00B0
+#define RTW_IEEE80211_STYPE_CTS		0x00C0
+#define RTW_IEEE80211_STYPE_ACK		0x00D0
+#define RTW_IEEE80211_STYPE_CFEND		0x00E0
+#define RTW_IEEE80211_STYPE_CFENDACK		0x00F0
+
+/* data */
+#define RTW_IEEE80211_STYPE_DATA		0x0000
+#define RTW_IEEE80211_STYPE_DATA_CFACK	0x0010
+#define RTW_IEEE80211_STYPE_DATA_CFPOLL	0x0020
+#define RTW_IEEE80211_STYPE_DATA_CFACKPOLL	0x0030
+#define RTW_IEEE80211_STYPE_NULLFUNC	0x0040
+#define RTW_IEEE80211_STYPE_CFACK		0x0050
+#define RTW_IEEE80211_STYPE_CFPOLL		0x0060
+#define RTW_IEEE80211_STYPE_CFACKPOLL	0x0070
+#define RTW_IEEE80211_STYPE_QOS_DATA		0x0080
+#define RTW_IEEE80211_STYPE_QOS_DATA_CFACK		0x0090
+#define RTW_IEEE80211_STYPE_QOS_DATA_CFPOLL		0x00A0
+#define RTW_IEEE80211_STYPE_QOS_DATA_CFACKPOLL	0x00B0
+#define RTW_IEEE80211_STYPE_QOS_NULLFUNC	0x00C0
+#define RTW_IEEE80211_STYPE_QOS_CFACK		0x00D0
+#define RTW_IEEE80211_STYPE_QOS_CFPOLL		0x00E0
+#define RTW_IEEE80211_STYPE_QOS_CFACKPOLL	0x00F0
+
+/* sequence control field */
+#define RTW_IEEE80211_SCTL_FRAG	0x000F
+#define RTW_IEEE80211_SCTL_SEQ	0xFFF0
+
+
+#define RTW_ERP_INFO_NON_ERP_PRESENT BIT(0)
+#define RTW_ERP_INFO_USE_PROTECTION BIT(1)
+#define RTW_ERP_INFO_BARKER_PREAMBLE_MODE BIT(2)
+
+/* QoS,QOS */
+#define NORMAL_ACK			0
+#define NO_ACK				1
+#define NON_EXPLICIT_ACK	2
+#define BLOCK_ACK			3
+
+#ifndef ETH_P_PAE
+	#define ETH_P_PAE 0x888E /* Port Access Entity (IEEE 802.1X) */
+#endif /* ETH_P_PAE */
+
+#define ETH_P_PREAUTH 0x88C7 /* IEEE 802.11i pre-authentication */
+
+#define ETH_P_ECONET	0x0018
+
+#ifndef ETH_P_80211_RAW
+	#define ETH_P_80211_RAW (ETH_P_ECONET + 1)
+#endif
+
+/* IEEE 802.11 defines */
+
+#define P80211_OUI_LEN 3
+
+#if defined(PLATFORM_LINUX) || defined(CONFIG_RTL8711FW) || defined(PLATFORM_FREEBSD)
+
+struct ieee80211_snap_hdr {
+
+	u8    dsap;   /* always 0xAA */
+	u8    ssap;   /* always 0xAA */
+	u8    ctrl;   /* always 0x03 */
+	u8    oui[P80211_OUI_LEN];    /* organizational universal id */
+
+} __attribute__((packed));
+
+#endif
+
+#ifdef PLATFORM_WINDOWS
+
+#pragma pack(1)
+struct ieee80211_snap_hdr {
+
+	u8    dsap;   /* always 0xAA */
+	u8    ssap;   /* always 0xAA */
+	u8    ctrl;   /* always 0x03 */
+	u8    oui[P80211_OUI_LEN];    /* organizational universal id */
+
+};
+#pragma pack()
+
+#endif
+
+
+#define SNAP_SIZE sizeof(struct ieee80211_snap_hdr)
+
+#define WLAN_FC_GET_TYPE(fc) ((fc) & RTW_IEEE80211_FCTL_FTYPE)
+#define WLAN_FC_GET_STYPE(fc) ((fc) & RTW_IEEE80211_FCTL_STYPE)
+
+#define WLAN_QC_GET_TID(qc) ((qc) & 0x0f)
+
+#define WLAN_GET_SEQ_FRAG(seq) ((seq) & RTW_IEEE80211_SCTL_FRAG)
+#define WLAN_GET_SEQ_SEQ(seq)  ((seq) & RTW_IEEE80211_SCTL_SEQ)
+
+/* Authentication algorithms */
+#define WLAN_AUTH_OPEN 0
+#define WLAN_AUTH_SHARED_KEY 1
+
+#define WLAN_AUTH_CHALLENGE_LEN 128
+
+#define WLAN_CAPABILITY_BSS (1<<0)
+#define WLAN_CAPABILITY_IBSS (1<<1)
+#define WLAN_CAPABILITY_CF_POLLABLE (1<<2)
+#define WLAN_CAPABILITY_CF_POLL_REQUEST (1<<3)
+#define WLAN_CAPABILITY_PRIVACY (1<<4)
+#define WLAN_CAPABILITY_SHORT_PREAMBLE (1<<5)
+#define WLAN_CAPABILITY_PBCC (1<<6)
+#define WLAN_CAPABILITY_CHANNEL_AGILITY (1<<7)
+#define WLAN_CAPABILITY_SHORT_SLOT (1<<10)
+
+/* Status codes */
+#define WLAN_STATUS_SUCCESS 0
+#define WLAN_STATUS_UNSPECIFIED_FAILURE 1
+#define WLAN_STATUS_CAPS_UNSUPPORTED 10
+#define WLAN_STATUS_REASSOC_NO_ASSOC 11
+#define WLAN_STATUS_ASSOC_DENIED_UNSPEC 12
+#define WLAN_STATUS_NOT_SUPPORTED_AUTH_ALG 13
+#define WLAN_STATUS_UNKNOWN_AUTH_TRANSACTION 14
+#define WLAN_STATUS_CHALLENGE_FAIL 15
+#define WLAN_STATUS_AUTH_TIMEOUT 16
+#define WLAN_STATUS_AP_UNABLE_TO_HANDLE_NEW_STA 17
+#define WLAN_STATUS_ASSOC_DENIED_RATES 18
+/* 802.11b */
+#define WLAN_STATUS_ASSOC_DENIED_NOSHORT 19
+#define WLAN_STATUS_ASSOC_DENIED_NOPBCC 20
+#define WLAN_STATUS_ASSOC_DENIED_NOAGILITY 21
+
+/* Reason codes */
+#define WLAN_REASON_UNSPECIFIED 1
+#define WLAN_REASON_PREV_AUTH_NOT_VALID 2
+#define WLAN_REASON_DEAUTH_LEAVING 3
+#define WLAN_REASON_DISASSOC_DUE_TO_INACTIVITY 4
+#define WLAN_REASON_DISASSOC_AP_BUSY 5
+#define WLAN_REASON_CLASS2_FRAME_FROM_NONAUTH_STA 6
+#define WLAN_REASON_CLASS3_FRAME_FROM_NONASSOC_STA 7
+#define WLAN_REASON_DISASSOC_STA_HAS_LEFT 8
+#define WLAN_REASON_STA_REQ_ASSOC_WITHOUT_AUTH 9
+#define WLAN_REASON_MESH_PEER_CANCELED 52
+#define WLAN_REASON_MESH_MAX_PEERS 53
+#define WLAN_REASON_MESH_CONFIG 54
+#define WLAN_REASON_MESH_CLOSE 55
+#define WLAN_REASON_MESH_MAX_RETRIES 56 
+#define WLAN_REASON_MESH_CONFIRM_TIMEOUT 57
+#define WLAN_REASON_MESH_INVALID_GTK 58
+#define WLAN_REASON_MESH_INCONSISTENT_PARAM 59
+#define WLAN_REASON_MESH_INVALID_SECURITY 60
+#define WLAN_REASON_MESH_PATH_NOPROXY 61
+#define WLAN_REASON_MESH_PATH_NOFORWARD 62
+#define WLAN_REASON_MESH_PATH_DEST_UNREACHABLE 63
+#define WLAN_REASON_MAC_EXISTS_IN_MBSS 64
+#define WLAN_REASON_MESH_CHAN_REGULATORY 65
+#define WLAN_REASON_MESH_CHAN 66
+#define WLAN_REASON_SA_QUERY_TIMEOUT 65532
+#define WLAN_REASON_ACTIVE_ROAM 65533
+#define WLAN_REASON_JOIN_WRONG_CHANNEL       65534
+#define WLAN_REASON_EXPIRATION_CHK 65535
+
+#define WLAN_REASON_IS_PRIVATE(reason) ( \
+	reason == WLAN_REASON_EXPIRATION_CHK \
+	|| reason == WLAN_REASON_JOIN_WRONG_CHANNEL \
+	|| reason == WLAN_REASON_ACTIVE_ROAM \
+	|| reason == WLAN_REASON_SA_QUERY_TIMEOUT \
+	)
+
+/* Information Element IDs */
+#define WLAN_EID_SSID 0
+#define WLAN_EID_SUPP_RATES 1
+#define WLAN_EID_FH_PARAMS 2
+#define WLAN_EID_DS_PARAMS 3
+#define WLAN_EID_CF_PARAMS 4
+#define WLAN_EID_TIM 5
+#define WLAN_EID_IBSS_PARAMS 6
+#define WLAN_EID_CHALLENGE 16
+/* EIDs defined by IEEE 802.11h - START */
+#define WLAN_EID_PWR_CONSTRAINT 32
+#define WLAN_EID_PWR_CAPABILITY 33
+#define WLAN_EID_TPC_REQUEST 34
+#define WLAN_EID_TPC_REPORT 35
+#define WLAN_EID_SUPPORTED_CHANNELS 36
+#define WLAN_EID_CHANNEL_SWITCH 37
+#define WLAN_EID_MEASURE_REQUEST 38
+#define WLAN_EID_MEASURE_REPORT 39
+#define WLAN_EID_QUITE 40
+#define WLAN_EID_IBSS_DFS 41
+/* EIDs defined by IEEE 802.11h - END */
+#define WLAN_EID_ERP_INFO 42
+#define WLAN_EID_HT_CAP 45
+#define WLAN_EID_RSN 48
+#define WLAN_EID_EXT_SUPP_RATES 50
+#define WLAN_EID_MOBILITY_DOMAIN 54
+#define WLAN_EID_FAST_BSS_TRANSITION 55
+#define WLAN_EID_TIMEOUT_INTERVAL 56
+#define WLAN_EID_RIC_DATA 57
+#define WLAN_EID_HT_OPERATION 61
+#define WLAN_EID_SECONDARY_CHANNEL_OFFSET 62
+#define WLAN_EID_20_40_BSS_COEXISTENCE 72
+#define WLAN_EID_20_40_BSS_INTOLERANT 73
+#define WLAN_EID_OVERLAPPING_BSS_SCAN_PARAMS 74
+#define WLAN_EID_MMIE 76
+#define WLAN_EID_MESH_CONFIG 113
+#define WLAN_EID_MESH_ID 114
+#define WLAN_EID_MPM 117
+#define	WLAN_EID_RANN 126
+#define	WLAN_EID_PREQ 130
+#define	WLAN_EID_PREP 131
+#define	WLAN_EID_PERR 132
+#define WLAN_EID_AMPE 139
+#define WLAN_EID_MIC 140
+#define WLAN_EID_VENDOR_SPECIFIC 221
+#define WLAN_EID_GENERIC (WLAN_EID_VENDOR_SPECIFIC)
+#define WLAN_EID_VHT_CAPABILITY 191
+#define WLAN_EID_VHT_OPERATION 192
+#define WLAN_EID_VHT_OP_MODE_NOTIFY 199
+
+#define IEEE80211_MGMT_HDR_LEN 24
+#define IEEE80211_DATA_HDR3_LEN 24
+#define IEEE80211_DATA_HDR4_LEN 30
+
+
+#define IEEE80211_STATMASK_SIGNAL (1<<0)
+#define IEEE80211_STATMASK_RSSI (1<<1)
+#define IEEE80211_STATMASK_NOISE (1<<2)
+#define IEEE80211_STATMASK_RATE (1<<3)
+#define IEEE80211_STATMASK_WEMASK 0x7
+
+
+#define IEEE80211_CCK_MODULATION    (1<<0)
+#define IEEE80211_OFDM_MODULATION   (1<<1)
+
+#define IEEE80211_24GHZ_BAND     (1<<0)
+#define IEEE80211_52GHZ_BAND     (1<<1)
+
+#define IEEE80211_CCK_RATE_LEN		4
+#define IEEE80211_NUM_OFDM_RATESLEN	8
+
+
+#define IEEE80211_CCK_RATE_1MB		        0x02
+#define IEEE80211_CCK_RATE_2MB		        0x04
+#define IEEE80211_CCK_RATE_5MB		        0x0B
+#define IEEE80211_CCK_RATE_11MB		        0x16
+#define IEEE80211_OFDM_RATE_LEN		8
+#define IEEE80211_OFDM_RATE_6MB		        0x0C
+#define IEEE80211_OFDM_RATE_9MB		        0x12
+#define IEEE80211_OFDM_RATE_12MB		0x18
+#define IEEE80211_OFDM_RATE_18MB		0x24
+#define IEEE80211_OFDM_RATE_24MB		0x30
+#define IEEE80211_OFDM_RATE_36MB		0x48
+#define IEEE80211_OFDM_RATE_48MB		0x60
+#define IEEE80211_OFDM_RATE_54MB		0x6C
+#define IEEE80211_PBCC_RATE_22MB		0x2c
+#define IEEE80211_PBCC_RATE_33MB		0x42
+
+#define IEEE80211_BASIC_RATE_MASK		0x80
+
+#define IEEE80211_CCK_RATE_1MB_MASK		(1<<0)
+#define IEEE80211_CCK_RATE_2MB_MASK		(1<<1)
+#define IEEE80211_CCK_RATE_5MB_MASK		(1<<2)
+#define IEEE80211_CCK_RATE_11MB_MASK		(1<<3)
+#define IEEE80211_OFDM_RATE_6MB_MASK		(1<<4)
+#define IEEE80211_OFDM_RATE_9MB_MASK		(1<<5)
+#define IEEE80211_OFDM_RATE_12MB_MASK		(1<<6)
+#define IEEE80211_OFDM_RATE_18MB_MASK		(1<<7)
+#define IEEE80211_OFDM_RATE_24MB_MASK		(1<<8)
+#define IEEE80211_OFDM_RATE_36MB_MASK		(1<<9)
+#define IEEE80211_OFDM_RATE_48MB_MASK		(1<<10)
+#define IEEE80211_OFDM_RATE_54MB_MASK		(1<<11)
+
+#define IEEE80211_CCK_RATES_MASK	        0x0000000F
+#define IEEE80211_CCK_BASIC_RATES_MASK	(IEEE80211_CCK_RATE_1MB_MASK | \
+		IEEE80211_CCK_RATE_2MB_MASK)
+#define IEEE80211_CCK_DEFAULT_RATES_MASK	(IEEE80211_CCK_BASIC_RATES_MASK | \
+		IEEE80211_CCK_RATE_5MB_MASK | \
+		IEEE80211_CCK_RATE_11MB_MASK)
+
+#define IEEE80211_OFDM_RATES_MASK		0x00000FF0
+#define IEEE80211_OFDM_BASIC_RATES_MASK	(IEEE80211_OFDM_RATE_6MB_MASK | \
+		IEEE80211_OFDM_RATE_12MB_MASK | \
+		IEEE80211_OFDM_RATE_24MB_MASK)
+#define IEEE80211_OFDM_DEFAULT_RATES_MASK	(IEEE80211_OFDM_BASIC_RATES_MASK | \
+		IEEE80211_OFDM_RATE_9MB_MASK  | \
+		IEEE80211_OFDM_RATE_18MB_MASK | \
+		IEEE80211_OFDM_RATE_36MB_MASK | \
+		IEEE80211_OFDM_RATE_48MB_MASK | \
+		IEEE80211_OFDM_RATE_54MB_MASK)
+#define IEEE80211_DEFAULT_RATES_MASK (IEEE80211_OFDM_DEFAULT_RATES_MASK | \
+				      IEEE80211_CCK_DEFAULT_RATES_MASK)
+
+#define IEEE80211_NUM_OFDM_RATES	    8
+#define IEEE80211_NUM_CCK_RATES	            4
+#define IEEE80211_OFDM_SHIFT_MASK_A         4
+
+
+enum MGN_RATE {
+	MGN_1M		= 0x02,
+	MGN_2M		= 0x04,
+	MGN_5_5M	= 0x0B,
+	MGN_6M		= 0x0C,
+	MGN_9M		= 0x12,
+	MGN_11M	= 0x16,
+	MGN_12M	= 0x18,
+	MGN_18M	= 0x24,
+	MGN_24M	= 0x30,
+	MGN_36M	= 0x48,
+	MGN_48M	= 0x60,
+	MGN_54M	= 0x6C,
+	MGN_MCS32	= 0x7F,
+	MGN_MCS0,
+	MGN_MCS1,
+	MGN_MCS2,
+	MGN_MCS3,
+	MGN_MCS4,
+	MGN_MCS5,
+	MGN_MCS6,
+	MGN_MCS7,
+	MGN_MCS8,
+	MGN_MCS9,
+	MGN_MCS10,
+	MGN_MCS11,
+	MGN_MCS12,
+	MGN_MCS13,
+	MGN_MCS14,
+	MGN_MCS15,
+	MGN_MCS16,
+	MGN_MCS17,
+	MGN_MCS18,
+	MGN_MCS19,
+	MGN_MCS20,
+	MGN_MCS21,
+	MGN_MCS22,
+	MGN_MCS23,
+	MGN_MCS24,
+	MGN_MCS25,
+	MGN_MCS26,
+	MGN_MCS27,
+	MGN_MCS28,
+	MGN_MCS29,
+	MGN_MCS30,
+	MGN_MCS31,
+	MGN_VHT1SS_MCS0,
+	MGN_VHT1SS_MCS1,
+	MGN_VHT1SS_MCS2,
+	MGN_VHT1SS_MCS3,
+	MGN_VHT1SS_MCS4,
+	MGN_VHT1SS_MCS5,
+	MGN_VHT1SS_MCS6,
+	MGN_VHT1SS_MCS7,
+	MGN_VHT1SS_MCS8,
+	MGN_VHT1SS_MCS9,
+	MGN_VHT2SS_MCS0,
+	MGN_VHT2SS_MCS1,
+	MGN_VHT2SS_MCS2,
+	MGN_VHT2SS_MCS3,
+	MGN_VHT2SS_MCS4,
+	MGN_VHT2SS_MCS5,
+	MGN_VHT2SS_MCS6,
+	MGN_VHT2SS_MCS7,
+	MGN_VHT2SS_MCS8,
+	MGN_VHT2SS_MCS9,
+	MGN_VHT3SS_MCS0,
+	MGN_VHT3SS_MCS1,
+	MGN_VHT3SS_MCS2,
+	MGN_VHT3SS_MCS3,
+	MGN_VHT3SS_MCS4,
+	MGN_VHT3SS_MCS5,
+	MGN_VHT3SS_MCS6,
+	MGN_VHT3SS_MCS7,
+	MGN_VHT3SS_MCS8,
+	MGN_VHT3SS_MCS9,
+	MGN_VHT4SS_MCS0,
+	MGN_VHT4SS_MCS1,
+	MGN_VHT4SS_MCS2,
+	MGN_VHT4SS_MCS3,
+	MGN_VHT4SS_MCS4,
+	MGN_VHT4SS_MCS5,
+	MGN_VHT4SS_MCS6,
+	MGN_VHT4SS_MCS7,
+	MGN_VHT4SS_MCS8,
+	MGN_VHT4SS_MCS9,
+	MGN_UNKNOWN
+};
+
+#define IS_HT_RATE(_rate)	((_rate) >= MGN_MCS0 && (_rate) <= MGN_MCS31)
+#define IS_VHT_RATE(_rate)	((_rate) >= MGN_VHT1SS_MCS0 && (_rate) <= MGN_VHT4SS_MCS9)
+#define IS_CCK_RATE(_rate)	((_rate) == MGN_1M || (_rate) == MGN_2M || (_rate) == MGN_5_5M || (_rate) == MGN_11M)
+#define IS_OFDM_RATE(_rate)	((_rate) >= MGN_6M && (_rate) <= MGN_54M  && (_rate) != MGN_11M)
+
+#define IS_HT1SS_RATE(_rate) ((_rate) >= MGN_MCS0 && (_rate) <= MGN_MCS7)
+#define IS_HT2SS_RATE(_rate) ((_rate) >= MGN_MCS8 && (_rate) <= MGN_MCS15)
+#define IS_HT3SS_RATE(_rate) ((_rate) >= MGN_MCS16 && (_rate) <= MGN_MCS23)
+#define IS_HT4SS_RATE(_rate) ((_rate) >= MGN_MCS24 && (_rate) <= MGN_MCS31)
+
+#define IS_VHT1SS_RATE(_rate) ((_rate) >= MGN_VHT1SS_MCS0 && (_rate) <= MGN_VHT1SS_MCS9)
+#define IS_VHT2SS_RATE(_rate) ((_rate) >= MGN_VHT2SS_MCS0 && (_rate) <= MGN_VHT2SS_MCS9)
+#define IS_VHT3SS_RATE(_rate) ((_rate) >= MGN_VHT3SS_MCS0 && (_rate) <= MGN_VHT3SS_MCS9)
+#define IS_VHT4SS_RATE(_rate) ((_rate) >= MGN_VHT4SS_MCS0 && (_rate) <= MGN_VHT4SS_MCS9)
+
+#define IS_1T_RATE(_rate)	(IS_CCK_RATE((_rate)) || IS_OFDM_RATE((_rate)) || IS_HT1SS_RATE((_rate)) || IS_VHT1SS_RATE((_rate)))
+#define IS_2T_RATE(_rate)	(IS_HT2SS_RATE((_rate)) || IS_VHT2SS_RATE((_rate)))
+#define IS_3T_RATE(_rate)	(IS_HT3SS_RATE((_rate)) || IS_VHT3SS_RATE((_rate)))
+#define IS_4T_RATE(_rate)	(IS_HT4SS_RATE((_rate)) || IS_VHT4SS_RATE((_rate)))
+
+#define MGN_RATE_STR(_rate) \
+	(_rate == MGN_1M) ? "CCK_1M" : \
+	(_rate == MGN_2M) ? "CCK_2M" : \
+	(_rate == MGN_5_5M) ? "CCK_5.5M" : \
+	(_rate == MGN_11M) ? "CCK_11M" : \
+	(_rate == MGN_6M) ? "OFDM_6M" : \
+	(_rate == MGN_9M) ? "OFDM_9M" : \
+	(_rate == MGN_12M) ? "OFDM_12M" : \
+	(_rate == MGN_18M) ? "OFDM_18M" : \
+	(_rate == MGN_24M) ? "OFDM_24M" : \
+	(_rate == MGN_36M) ? "OFDM_36M" : \
+	(_rate == MGN_48M) ? "OFDM_48M" : \
+	(_rate == MGN_54M) ? "OFDM_54M" : \
+	(_rate == MGN_MCS32) ? "MCS32" : \
+	(_rate == MGN_MCS0) ? "MCS0" : \
+	(_rate == MGN_MCS1) ? "MCS1" : \
+	(_rate == MGN_MCS2) ? "MCS2" : \
+	(_rate == MGN_MCS3) ? "MCS3" : \
+	(_rate == MGN_MCS4) ? "MCS4" : \
+	(_rate == MGN_MCS5) ? "MCS5" : \
+	(_rate == MGN_MCS6) ? "MCS6" : \
+	(_rate == MGN_MCS7) ? "MCS7" : \
+	(_rate == MGN_MCS8) ? "MCS8" : \
+	(_rate == MGN_MCS9) ? "MCS9" : \
+	(_rate == MGN_MCS10) ? "MCS10" : \
+	(_rate == MGN_MCS11) ? "MCS11" : \
+	(_rate == MGN_MCS12) ? "MCS12" : \
+	(_rate == MGN_MCS13) ? "MCS13" : \
+	(_rate == MGN_MCS14) ? "MCS14" : \
+	(_rate == MGN_MCS15) ? "MCS15" : \
+	(_rate == MGN_MCS16) ? "MCS16" : \
+	(_rate == MGN_MCS17) ? "MCS17" : \
+	(_rate == MGN_MCS18) ? "MCS18" : \
+	(_rate == MGN_MCS19) ? "MCS19" : \
+	(_rate == MGN_MCS20) ? "MCS20" : \
+	(_rate == MGN_MCS21) ? "MCS21" : \
+	(_rate == MGN_MCS22) ? "MCS22" : \
+	(_rate == MGN_MCS23) ? "MCS23" : \
+	(_rate == MGN_MCS24) ? "MCS24" : \
+	(_rate == MGN_MCS25) ? "MCS25" : \
+	(_rate == MGN_MCS26) ? "MCS26" : \
+	(_rate == MGN_MCS27) ? "MCS27" : \
+	(_rate == MGN_MCS28) ? "MCS28" : \
+	(_rate == MGN_MCS29) ? "MCS29" : \
+	(_rate == MGN_MCS30) ? "MCS30" : \
+	(_rate == MGN_MCS31) ? "MCS31" : \
+	(_rate == MGN_VHT1SS_MCS0) ? "VHT1SMCS0" : \
+	(_rate == MGN_VHT1SS_MCS1) ? "VHT1SMCS1" : \
+	(_rate == MGN_VHT1SS_MCS2) ? "VHT1SMCS2" : \
+	(_rate == MGN_VHT1SS_MCS3) ? "VHT1SMCS3" : \
+	(_rate == MGN_VHT1SS_MCS4) ? "VHT1SMCS4" : \
+	(_rate == MGN_VHT1SS_MCS5) ? "VHT1SMCS5" : \
+	(_rate == MGN_VHT1SS_MCS6) ? "VHT1SMCS6" : \
+	(_rate == MGN_VHT1SS_MCS7) ? "VHT1SMCS7" : \
+	(_rate == MGN_VHT1SS_MCS8) ? "VHT1SMCS8" : \
+	(_rate == MGN_VHT1SS_MCS9) ? "VHT1SMCS9" : \
+	(_rate == MGN_VHT2SS_MCS0) ? "VHT2SMCS0" : \
+	(_rate == MGN_VHT2SS_MCS1) ? "VHT2SMCS1" : \
+	(_rate == MGN_VHT2SS_MCS2) ? "VHT2SMCS2" : \
+	(_rate == MGN_VHT2SS_MCS3) ? "VHT2SMCS3" : \
+	(_rate == MGN_VHT2SS_MCS4) ? "VHT2SMCS4" : \
+	(_rate == MGN_VHT2SS_MCS5) ? "VHT2SMCS5" : \
+	(_rate == MGN_VHT2SS_MCS6) ? "VHT2SMCS6" : \
+	(_rate == MGN_VHT2SS_MCS7) ? "VHT2SMCS7" : \
+	(_rate == MGN_VHT2SS_MCS8) ? "VHT2SMCS8" : \
+	(_rate == MGN_VHT2SS_MCS9) ? "VHT2SMCS9" : \
+	(_rate == MGN_VHT3SS_MCS0) ? "VHT3SMCS0" : \
+	(_rate == MGN_VHT3SS_MCS1) ? "VHT3SMCS1" : \
+	(_rate == MGN_VHT3SS_MCS2) ? "VHT3SMCS2" : \
+	(_rate == MGN_VHT3SS_MCS3) ? "VHT3SMCS3" : \
+	(_rate == MGN_VHT3SS_MCS4) ? "VHT3SMCS4" : \
+	(_rate == MGN_VHT3SS_MCS5) ? "VHT3SMCS5" : \
+	(_rate == MGN_VHT3SS_MCS6) ? "VHT3SMCS6" : \
+	(_rate == MGN_VHT3SS_MCS7) ? "VHT3SMCS7" : \
+	(_rate == MGN_VHT3SS_MCS8) ? "VHT3SMCS8" : \
+	(_rate == MGN_VHT3SS_MCS9) ? "VHT3SMCS9" : \
+	(_rate == MGN_VHT4SS_MCS0) ? "VHT4SMCS0" : \
+	(_rate == MGN_VHT4SS_MCS1) ? "VHT4SMCS1" : \
+	(_rate == MGN_VHT4SS_MCS2) ? "VHT4SMCS2" : \
+	(_rate == MGN_VHT4SS_MCS3) ? "VHT4SMCS3" : \
+	(_rate == MGN_VHT4SS_MCS4) ? "VHT4SMCS4" : \
+	(_rate == MGN_VHT4SS_MCS5) ? "VHT4SMCS5" : \
+	(_rate == MGN_VHT4SS_MCS6) ? "VHT4SMCS6" : \
+	(_rate == MGN_VHT4SS_MCS7) ? "VHT4SMCS7" : \
+	(_rate == MGN_VHT4SS_MCS8) ? "VHT4SMCS8" : \
+	(_rate == MGN_VHT4SS_MCS9) ? "VHT4SMCS9" : "UNKNOWN"
+
+typedef enum _RATE_SECTION {
+	CCK = 0,
+	OFDM = 1,
+	HT_MCS0_MCS7 = 2,
+	HT_MCS8_MCS15 = 3,
+	HT_MCS16_MCS23 = 4,
+	HT_MCS24_MCS31 = 5,
+	HT_1SS = HT_MCS0_MCS7,
+	HT_2SS = HT_MCS8_MCS15,
+	HT_3SS = HT_MCS16_MCS23,
+	HT_4SS = HT_MCS24_MCS31,
+	VHT_1SSMCS0_1SSMCS9 = 6,
+	VHT_2SSMCS0_2SSMCS9 = 7,
+	VHT_3SSMCS0_3SSMCS9 = 8,
+	VHT_4SSMCS0_4SSMCS9 = 9,
+	VHT_1SS = VHT_1SSMCS0_1SSMCS9,
+	VHT_2SS = VHT_2SSMCS0_2SSMCS9,
+	VHT_3SS = VHT_3SSMCS0_3SSMCS9,
+	VHT_4SS = VHT_4SSMCS0_4SSMCS9,
+	RATE_SECTION_NUM,
+} RATE_SECTION;
+
+const char *rate_section_str(u8 section);
+
+#define IS_CCK_RATE_SECTION(section) ((section) == CCK)
+#define IS_OFDM_RATE_SECTION(section) ((section) == OFDM)
+#define IS_HT_RATE_SECTION(section) ((section) >= HT_1SS && (section) <= HT_4SS)
+#define IS_VHT_RATE_SECTION(section) ((section) >= VHT_1SS && (section) <= VHT_4SS)
+
+#define IS_1T_RATE_SECTION(section) ((section) == CCK || (section) == OFDM || (section) == HT_1SS || (section) == VHT_1SS)
+#define IS_2T_RATE_SECTION(section) ((section) == HT_2SS || (section) == VHT_2SS)
+#define IS_3T_RATE_SECTION(section) ((section) == HT_3SS || (section) == VHT_3SS)
+#define IS_4T_RATE_SECTION(section) ((section) == HT_4SS || (section) == VHT_4SS)
+
+extern u8 mgn_rates_cck[];
+extern u8 mgn_rates_ofdm[];
+extern u8 mgn_rates_mcs0_7[];
+extern u8 mgn_rates_mcs8_15[];
+extern u8 mgn_rates_mcs16_23[];
+extern u8 mgn_rates_mcs24_31[];
+extern u8 mgn_rates_vht1ss[];
+extern u8 mgn_rates_vht2ss[];
+extern u8 mgn_rates_vht3ss[];
+extern u8 mgn_rates_vht4ss[];
+
+struct rate_section_ent {
+	u8 tx_num; /* value of RF_TX_NUM */
+	u8 rate_num;
+	u8 *rates;
+};
+
+extern struct rate_section_ent rates_by_sections[];
+
+#define rate_section_to_tx_num(section) (rates_by_sections[(section)].tx_num)
+#define rate_section_rate_num(section) (rates_by_sections[(section)].rate_num)
+
+/* NOTE: This data is for statistical purposes; not all hardware provides this
+ *       information for frames received.  Not setting these will not cause
+ *       any adverse affects. */
+struct ieee80211_rx_stats {
+	/* u32 mac_time[2]; */
+	s8 rssi;
+	u8 signal;
+	u8 noise;
+	u8 received_channel;
+	u16 rate; /* in 100 kbps */
+	/* u8 control; */
+	u8 mask;
+	u8 freq;
+	u16 len;
+};
+
+/* IEEE 802.11 requires that STA supports concurrent reception of at least
+ * three fragmented frames. This define can be increased to support more
+ * concurrent frames, but it should be noted that each entry can consume about
+ * 2 kB of RAM and increasing cache size will slow down frame reassembly. */
+#define IEEE80211_FRAG_CACHE_LEN 4
+
+struct ieee80211_frag_entry {
+	u32 first_frag_time;
+	uint seq;
+	uint last_frag;
+	uint qos;   /* jackson */
+	uint tid;	/* jackson */
+	struct sk_buff *skb;
+	u8 src_addr[ETH_ALEN];
+	u8 dst_addr[ETH_ALEN];
+};
+
+#ifndef PLATFORM_FREEBSD /* Baron BSD has already defined */
+struct ieee80211_stats {
+	uint tx_unicast_frames;
+	uint tx_multicast_frames;
+	uint tx_fragments;
+	uint tx_unicast_octets;
+	uint tx_multicast_octets;
+	uint tx_deferred_transmissions;
+	uint tx_single_retry_frames;
+	uint tx_multiple_retry_frames;
+	uint tx_retry_limit_exceeded;
+	uint tx_discards;
+	uint rx_unicast_frames;
+	uint rx_multicast_frames;
+	uint rx_fragments;
+	uint rx_unicast_octets;
+	uint rx_multicast_octets;
+	uint rx_fcs_errors;
+	uint rx_discards_no_buffer;
+	uint tx_discards_wrong_sa;
+	uint rx_discards_undecryptable;
+	uint rx_message_in_msg_fragments;
+	uint rx_message_in_bad_msg_fragments;
+};
+#endif /* PLATFORM_FREEBSD */
+struct ieee80211_softmac_stats {
+	uint rx_ass_ok;
+	uint rx_ass_err;
+	uint rx_probe_rq;
+	uint tx_probe_rs;
+	uint tx_beacons;
+	uint rx_auth_rq;
+	uint rx_auth_rs_ok;
+	uint rx_auth_rs_err;
+	uint tx_auth_rq;
+	uint no_auth_rs;
+	uint no_ass_rs;
+	uint tx_ass_rq;
+	uint rx_ass_rq;
+	uint tx_probe_rq;
+	uint reassoc;
+	uint swtxstop;
+	uint swtxawake;
+};
+
+#define SEC_KEY_1         (1<<0)
+#define SEC_KEY_2         (1<<1)
+#define SEC_KEY_3         (1<<2)
+#define SEC_KEY_4         (1<<3)
+#define SEC_ACTIVE_KEY    (1<<4)
+#define SEC_AUTH_MODE     (1<<5)
+#define SEC_UNICAST_GROUP (1<<6)
+#define SEC_LEVEL         (1<<7)
+#define SEC_ENABLED       (1<<8)
+
+#define SEC_LEVEL_0      0 /* None */
+#define SEC_LEVEL_1      1 /* WEP 40 and 104 bit */
+#define SEC_LEVEL_2      2 /* Level 1 + TKIP */
+#define SEC_LEVEL_2_CKIP 3 /* Level 1 + CKIP */
+#define SEC_LEVEL_3      4 /* Level 2 + CCMP */
+
+#define WEP_KEYS 4
+#define WEP_KEY_LEN 13
+#define BIP_MAX_KEYID 5
+#define BIP_AAD_SIZE  20
+
+#if defined(PLATFORM_LINUX) || defined(CONFIG_RTL8711FW)
+
+struct ieee80211_security {
+	u16 active_key:2,
+	    enabled:1,
+	    auth_mode:2,
+	    auth_algo:4,
+	    unicast_uses_group:1;
+	u8 key_sizes[WEP_KEYS];
+	u8 keys[WEP_KEYS][WEP_KEY_LEN];
+	u8 level;
+	u16 flags;
+} __attribute__((packed));
+
+#endif
+
+#ifdef PLATFORM_WINDOWS
+
+#pragma pack(1)
+struct ieee80211_security {
+	u16 active_key:2,
+	    enabled:1,
+	    auth_mode:2,
+	    auth_algo:4,
+	    unicast_uses_group:1;
+	u8 key_sizes[WEP_KEYS];
+	u8 keys[WEP_KEYS][WEP_KEY_LEN];
+	u8 level;
+	u16 flags;
+} ;
+#pragma pack()
+
+#endif
+
+/*
+
+ 802.11 data frame from AP
+
+      ,-------------------------------------------------------------------.
+Bytes |  2   |  2   |    6    |    6    |    6    |  2   | 0..2312 |   4  |
+      |------|------|---------|---------|---------|------|---------|------|
+Desc. | ctrl | dura |  DA/RA  |   TA    |    SA   | Sequ |  frame  |  fcs |
+      |      | tion | (BSSID) |         |         | ence |  data   |      |
+      `-------------------------------------------------------------------'
+
+Total: 28-2340 bytes
+
+*/
+
+struct ieee80211_header_data {
+	u16 frame_ctl;
+	u16 duration_id;
+	u8 addr1[6];
+	u8 addr2[6];
+	u8 addr3[6];
+	u16 seq_ctrl;
+};
+
+#define BEACON_PROBE_SSID_ID_POSITION 12
+
+/* Management Frame Information Element Types */
+#define MFIE_TYPE_SSID       0
+#define MFIE_TYPE_RATES      1
+#define MFIE_TYPE_FH_SET     2
+#define MFIE_TYPE_DS_SET     3
+#define MFIE_TYPE_CF_SET     4
+#define MFIE_TYPE_TIM        5
+#define MFIE_TYPE_IBSS_SET   6
+#define MFIE_TYPE_CHALLENGE  16
+#define MFIE_TYPE_ERP        42
+#define MFIE_TYPE_RSN	     48
+#define MFIE_TYPE_RATES_EX   50
+#define MFIE_TYPE_GENERIC    221
+
+#if defined(PLATFORM_LINUX) || defined(CONFIG_RTL8711FW)
+
+struct ieee80211_info_element_hdr {
+	u8 id;
+	u8 len;
+} __attribute__((packed));
+
+struct ieee80211_info_element {
+	u8 id;
+	u8 len;
+	u8 data[0];
+} __attribute__((packed));
+#endif
+
+#ifdef PLATFORM_WINDOWS
+
+#pragma pack(1)
+struct ieee80211_info_element_hdr {
+	u8 id;
+	u8 len;
+} ;
+
+struct ieee80211_info_element {
+	u8 id;
+	u8 len;
+	u8 data[0];
+} ;
+#pragma pack()
+
+#endif
+
+
+/*
+ * These are the data types that can make up management packets
+ *
+	u16 auth_algorithm;
+	u16 auth_sequence;
+	u16 beacon_interval;
+	u16 capability;
+	u8 current_ap[ETH_ALEN];
+	u16 listen_interval;
+	struct {
+		u16 association_id:14, reserved:2;
+	} __attribute__ ((packed));
+	u32 time_stamp[2];
+	u16 reason;
+	u16 status;
+*/
+
+#define IEEE80211_DEFAULT_TX_ESSID "Penguin"
+#define IEEE80211_DEFAULT_BASIC_RATE 10
+
+
+#if defined(PLATFORM_LINUX) || defined(CONFIG_RTL8711FW)
+
+
+struct ieee80211_authentication {
+	struct ieee80211_header_data header;
+	u16 algorithm;
+	u16 transaction;
+	u16 status;
+	/* struct ieee80211_info_element_hdr info_element; */
+} __attribute__((packed));
+
+
+struct ieee80211_probe_response {
+	struct ieee80211_header_data header;
+	u32 time_stamp[2];
+	u16 beacon_interval;
+	u16 capability;
+	struct ieee80211_info_element info_element;
+} __attribute__((packed));
+
+struct ieee80211_probe_request {
+	struct ieee80211_header_data header;
+	/*struct ieee80211_info_element info_element;*/
+} __attribute__((packed));
+
+struct ieee80211_assoc_request_frame {
+	struct rtw_ieee80211_hdr_3addr header;
+	u16 capability;
+	u16 listen_interval;
+	/* u8 current_ap[ETH_ALEN]; */
+	struct ieee80211_info_element_hdr info_element;
+} __attribute__((packed));
+
+struct ieee80211_assoc_response_frame {
+	struct rtw_ieee80211_hdr_3addr header;
+	u16 capability;
+	u16 status;
+	u16 aid;
+	/*	struct ieee80211_info_element info_element;  supported rates  */
+} __attribute__((packed));
+#endif
+
+
+
+#ifdef PLATFORM_WINDOWS
+
+#pragma pack(1)
+
+struct ieee80211_authentication {
+	struct ieee80211_header_data header;
+	u16 algorithm;
+	u16 transaction;
+	u16 status;
+	/* struct ieee80211_info_element_hdr info_element; */
+} ;
+
+
+struct ieee80211_probe_response {
+	struct ieee80211_header_data header;
+	u32 time_stamp[2];
+	u16 beacon_interval;
+	u16 capability;
+	struct ieee80211_info_element info_element;
+} ;
+
+struct ieee80211_probe_request {
+	struct ieee80211_header_data header;
+	/*struct ieee80211_info_element info_element;*/
+} ;
+
+struct ieee80211_assoc_request_frame {
+	struct rtw_ieee80211_hdr_3addr header;
+	u16 capability;
+	u16 listen_interval;
+	/* u8 current_ap[ETH_ALEN]; */
+	struct ieee80211_info_element_hdr info_element;
+} ;
+
+struct ieee80211_assoc_response_frame {
+	struct rtw_ieee80211_hdr_3addr header;
+	u16 capability;
+	u16 status;
+	u16 aid;
+	/*	struct ieee80211_info_element info_element;  supported rates  */
+};
+
+#pragma pack()
+
+#endif
+
+
+
+
+struct ieee80211_txb {
+	u8 nr_frags;
+	u8 encrypted;
+	u16 reserved;
+	u16 frag_size;
+	u16 payload_size;
+	struct sk_buff *fragments[0];
+};
+
+
+/* SWEEP TABLE ENTRIES NUMBER*/
+#define MAX_SWEEP_TAB_ENTRIES		  42
+#define MAX_SWEEP_TAB_ENTRIES_PER_PACKET  7
+/* MAX_RATES_LENGTH needs to be 12.  The spec says 8, and many APs
+ * only use 8, and then use extended rates for the remaining supported
+ * rates.  Other APs, however, stick all of their supported rates on the
+ * main rates information element... */
+#define MAX_RATES_LENGTH                  ((u8)12)
+#define MAX_RATES_EX_LENGTH               ((u8)16)
+#define MAX_NETWORK_COUNT                  128
+#define IEEE80211_SOFTMAC_SCAN_TIME	  400
+/* (HZ / 2) */
+#define IEEE80211_SOFTMAC_ASSOC_RETRY_TIME (HZ * 2)
+
+#define CRC_LENGTH                 4U
+
+#define MAX_WPA_IE_LEN (256)
+#define MAX_WPS_IE_LEN (512)
+#define MAX_P2P_IE_LEN (256)
+#define MAX_WFD_IE_LEN (128)
+
+#define NETWORK_EMPTY_ESSID (1<<0)
+#define NETWORK_HAS_OFDM    (1<<1)
+#define NETWORK_HAS_CCK     (1<<2)
+
+#define IEEE80211_DTIM_MBCAST 4
+#define IEEE80211_DTIM_UCAST 2
+#define IEEE80211_DTIM_VALID 1
+#define IEEE80211_DTIM_INVALID 0
+
+#define IEEE80211_PS_DISABLED 0
+#define IEEE80211_PS_UNICAST IEEE80211_DTIM_UCAST
+#define IEEE80211_PS_MBCAST IEEE80211_DTIM_MBCAST
+#define IW_ESSID_MAX_SIZE 32
+#if 0
+struct ieee80211_network {
+	/* These entries are used to identify a unique network */
+	u8 bssid[ETH_ALEN];
+	u8 channel;
+	/* Ensure null-terminated for any debug msgs */
+	u8 ssid[IW_ESSID_MAX_SIZE + 1];
+	u8 ssid_len;
+	u8	rssi;	/* relative signal strength */
+	u8	sq;		/* signal quality */
+
+	/* These are network statistics */
+	/* struct ieee80211_rx_stats stats; */
+	u16 capability;
+	u16	aid;
+	u8 rates[MAX_RATES_LENGTH];
+	u8 rates_len;
+	u8 rates_ex[MAX_RATES_EX_LENGTH];
+	u8 rates_ex_len;
+
+	u8 edca_parmsets[18];
+
+	u8 mode;
+	u8 flags;
+	u8 time_stamp[8];
+	u16 beacon_interval;
+	u16 listen_interval;
+	u16 atim_window;
+	u8 wpa_ie[MAX_WPA_IE_LEN];
+	size_t wpa_ie_len;
+	u8 rsn_ie[MAX_WPA_IE_LEN];
+	size_t rsn_ie_len;
+	u8 country[6];
+	u8 dtim_period;
+	u8 dtim_data;
+	u8 power_constraint;
+	u8 qosinfo;
+	u8 qbssload[5];
+	u8 network_type;
+	int join_res;
+	unsigned long	last_scanned;
+};
+#endif
+/*
+join_res:
+-1: authentication fail
+-2: association fail
+> 0: TID
+*/
+
+#ifndef PLATFORM_FREEBSD /* Baron BSD has already defined */
+
+enum ieee80211_state {
+
+	/* the card is not linked at all */
+	IEEE80211_NOLINK = 0,
+
+	/* IEEE80211_ASSOCIATING* are for BSS client mode
+	 * the driver shall not perform RX filtering unless
+	 * the state is LINKED.
+	 * The driver shall just check for the state LINKED and
+	 * defaults to NOLINK for ALL the other states (including
+	 * LINKED_SCANNING)
+	 */
+
+	/* the association procedure will start (wq scheduling)*/
+	IEEE80211_ASSOCIATING,
+	IEEE80211_ASSOCIATING_RETRY,
+
+	/* the association procedure is sending AUTH request*/
+	IEEE80211_ASSOCIATING_AUTHENTICATING,
+
+	/* the association procedure has successfully authentcated
+	 * and is sending association request
+	 */
+	IEEE80211_ASSOCIATING_AUTHENTICATED,
+
+	/* the link is ok. the card associated to a BSS or linked
+	 * to a ibss cell or acting as an AP and creating the bss
+	 */
+	IEEE80211_LINKED,
+
+	/* same as LINKED, but the driver shall apply RX filter
+	 * rules as we are in NO_LINK mode. As the card is still
+	 * logically linked, but it is doing a syncro site survey
+	 * then it will be back to LINKED state.
+	 */
+	IEEE80211_LINKED_SCANNING,
+
+};
+#endif /* PLATFORM_FREEBSD */
+
+#define DEFAULT_MAX_SCAN_AGE (15 * HZ)
+#define DEFAULT_FTS 2346
+#define MAC_FMT "%02x:%02x:%02x:%02x:%02x:%02x"
+#define MAC_ARG(x) ((u8 *)(x))[0], ((u8 *)(x))[1], ((u8 *)(x))[2], ((u8 *)(x))[3], ((u8 *)(x))[4], ((u8 *)(x))[5]
+#define MAC_SFMT "%02hhx:%02hhx:%02hhx:%02hhx:%02hhx:%02hhx"
+#define MAC_SARG(x) ((u8*)(x)),((u8*)(x)) + 1,((u8*)(x)) + 2,((u8*)(x)) + 3,((u8*)(x)) + 4,((u8*)(x)) + 5
+#define IP_FMT "%d.%d.%d.%d"
+#define IP_ARG(x) ((u8 *)(x))[0], ((u8 *)(x))[1], ((u8 *)(x))[2], ((u8 *)(x))[3]
+#define PORT_FMT "%u"
+#define PORT_ARG(x) ntohs(*((u16 *)(x)))
+
+#ifdef PLATFORM_FREEBSD /* Baron change func to macro */
+#define is_multicast_mac_addr(Addr) ((((Addr[0]) & 0x01) == 0x01) && ((Addr[0]) != 0xff))
+#define is_broadcast_mac_addr(Addr) ((((Addr[0]) & 0xff) == 0xff) && (((Addr[1]) & 0xff) == 0xff) && \
+	(((Addr[2]) & 0xff) == 0xff) && (((Addr[3]) & 0xff) == 0xff) && (((Addr[4]) & 0xff) == 0xff) && \
+				     (((Addr[5]) & 0xff) == 0xff))
+#else
+extern __inline int is_multicast_mac_addr(const u8 *addr)
+{
+	return (addr[0] != 0xff) && (0x01 & addr[0]);
+}
+
+extern __inline int is_broadcast_mac_addr(const u8 *addr)
+{
+	return ((addr[0] == 0xff) && (addr[1] == 0xff) && (addr[2] == 0xff) &&   \
+		(addr[3] == 0xff) && (addr[4] == 0xff) && (addr[5] == 0xff));
+}
+
+extern __inline int is_zero_mac_addr(const u8 *addr)
+{
+	return ((addr[0] == 0x00) && (addr[1] == 0x00) && (addr[2] == 0x00) &&   \
+		(addr[3] == 0x00) && (addr[4] == 0x00) && (addr[5] == 0x00));
+}
+#endif /* PLATFORM_FREEBSD */
+
+#define CFG_IEEE80211_RESERVE_FCS (1<<0)
+#define CFG_IEEE80211_COMPUTE_FCS (1<<1)
+
+typedef struct tx_pending_t {
+	int frag;
+	struct ieee80211_txb *txb;
+} tx_pending_t;
+
+
+
+#define TID_NUM	16
+
+#define IEEE_A            (1<<0)
+#define IEEE_B            (1<<1)
+#define IEEE_G            (1<<2)
+#define IEEE_MODE_MASK    (IEEE_A | IEEE_B | IEEE_G)
+
+/* Baron move to ieee80211.c */
+int ieee80211_is_empty_essid(const char *essid, int essid_len);
+int ieee80211_get_hdrlen(u16 fc);
+
+#if 0
+	/* Action frame categories (IEEE 802.11-2007, 7.3.1.11, Table 7-24) */
+	#define WLAN_ACTION_SPECTRUM_MGMT 0
+	#define WLAN_ACTION_QOS 1
+	#define WLAN_ACTION_DLS 2
+	#define WLAN_ACTION_BLOCK_ACK 3
+	#define WLAN_ACTION_RADIO_MEASUREMENT 5
+	#define WLAN_ACTION_FT 6
+	#define WLAN_ACTION_SA_QUERY 8
+	#define WLAN_ACTION_WMM 17
+#endif
+
+
+/* Action category code */
+enum rtw_ieee80211_category {
+	RTW_WLAN_CATEGORY_SPECTRUM_MGMT = 0,
+	RTW_WLAN_CATEGORY_QOS = 1,
+	RTW_WLAN_CATEGORY_DLS = 2,
+	RTW_WLAN_CATEGORY_BACK = 3,
+	RTW_WLAN_CATEGORY_PUBLIC = 4, /* IEEE 802.11 public action frames */
+	RTW_WLAN_CATEGORY_RADIO_MEAS = 5,
+	RTW_WLAN_CATEGORY_FT = 6,
+	RTW_WLAN_CATEGORY_HT = 7,
+	RTW_WLAN_CATEGORY_SA_QUERY = 8,
+	RTW_WLAN_CATEGORY_WNM = 10,
+	RTW_WLAN_CATEGORY_UNPROTECTED_WNM = 11, /* add for CONFIG_IEEE80211W, none 11w also can use */
+	RTW_WLAN_CATEGORY_TDLS = 12,
+	RTW_WLAN_CATEGORY_MESH = 13,
+	RTW_WLAN_CATEGORY_MULTIHOP = 14,
+	RTW_WLAN_CATEGORY_SELF_PROTECTED = 15,
+	RTW_WLAN_CATEGORY_WMM = 17,
+	RTW_WLAN_CATEGORY_VHT = 21,
+	RTW_WLAN_CATEGORY_P2P = 0x7f,/* P2P action frames */
+};
+
+#define CATEGORY_IS_GROUP_PRIVACY(cat) \
+	(cat == RTW_WLAN_CATEGORY_MESH || cat == RTW_WLAN_CATEGORY_MULTIHOP)
+
+#define CATEGORY_IS_NON_ROBUST(cat) \
+	(cat == RTW_WLAN_CATEGORY_PUBLIC \
+	|| cat == RTW_WLAN_CATEGORY_HT \
+	|| cat == RTW_WLAN_CATEGORY_UNPROTECTED_WNM \
+	|| cat == RTW_WLAN_CATEGORY_SELF_PROTECTED \
+	|| cat == RTW_WLAN_CATEGORY_VHT \
+	|| cat == RTW_WLAN_CATEGORY_P2P)
+
+#define CATEGORY_IS_ROBUST(cat) !CATEGORY_IS_NON_ROBUST(cat)
+
+/* SPECTRUM_MGMT action code */
+enum rtw_ieee80211_spectrum_mgmt_actioncode {
+	RTW_WLAN_ACTION_SPCT_MSR_REQ = 0,
+	RTW_WLAN_ACTION_SPCT_MSR_RPRT = 1,
+	RTW_WLAN_ACTION_SPCT_TPC_REQ = 2,
+	RTW_WLAN_ACTION_SPCT_TPC_RPRT = 3,
+	RTW_WLAN_ACTION_SPCT_CHL_SWITCH = 4,
+	RTW_WLAN_ACTION_SPCT_EXT_CHL_SWITCH = 5,
+};
+
+/* SELF_PROTECTED action code */
+enum rtw_ieee80211_self_protected_actioncode {
+	RTW_ACT_SELF_PROTECTED_RSVD = 0,
+	RTW_ACT_SELF_PROTECTED_MESH_OPEN = 1,
+	RTW_ACT_SELF_PROTECTED_MESH_CONF = 2,
+	RTW_ACT_SELF_PROTECTED_MESH_CLOSE = 3,
+	RTW_ACT_SELF_PROTECTED_MESH_GK_INFORM = 4,
+	RTW_ACT_SELF_PROTECTED_MESH_GK_ACK = 5,
+	RTW_ACT_SELF_PROTECTED_NUM,
+};
+
+/* MESH action code */
+enum rtw_ieee80211_mesh_actioncode {
+	RTW_ACT_MESH_LINK_METRIC_REPORT,
+	RTW_ACT_MESH_HWMP_PATH_SELECTION,
+	RTW_ACT_MESH_GATE_ANNOUNCEMENT,
+	RTW_ACT_MESH_CONGESTION_CONTROL_NOTIFICATION,
+	RTW_ACT_MESH_MCCA_SETUP_REQUEST,
+	RTW_ACT_MESH_MCCA_SETUP_REPLY,
+	RTW_ACT_MESH_MCCA_ADVERTISEMENT_REQUEST,
+	RTW_ACT_MESH_MCCA_ADVERTISEMENT,
+	RTW_ACT_MESH_MCCA_TEARDOWN,
+	RTW_ACT_MESH_TBTT_ADJUSTMENT_REQUEST,
+	RTW_ACT_MESH_TBTT_ADJUSTMENT_RESPONSE,
+};
+
+enum _PUBLIC_ACTION {
+	ACT_PUBLIC_BSSCOEXIST = 0, /* 20/40 BSS Coexistence */
+	ACT_PUBLIC_DSE_ENABLE = 1,
+	ACT_PUBLIC_DSE_DEENABLE = 2,
+	ACT_PUBLIC_DSE_REG_LOCATION = 3,
+	ACT_PUBLIC_EXT_CHL_SWITCH = 4,
+	ACT_PUBLIC_DSE_MSR_REQ = 5,
+	ACT_PUBLIC_DSE_MSR_RPRT = 6,
+	ACT_PUBLIC_MP = 7, /* Measurement Pilot */
+	ACT_PUBLIC_DSE_PWR_CONSTRAINT = 8,
+	ACT_PUBLIC_VENDOR = 9, /* for WIFI_DIRECT */
+	ACT_PUBLIC_GAS_INITIAL_REQ = 10,
+	ACT_PUBLIC_GAS_INITIAL_RSP = 11,
+	ACT_PUBLIC_GAS_COMEBACK_REQ = 12,
+	ACT_PUBLIC_GAS_COMEBACK_RSP = 13,
+	ACT_PUBLIC_TDLS_DISCOVERY_RSP = 14,
+	ACT_PUBLIC_LOCATION_TRACK = 15,
+	ACT_PUBLIC_MAX
+};
+
+#ifdef CONFIG_TDLS
+enum TDLS_ACTION_FIELD {
+	TDLS_SETUP_REQUEST = 0,
+	TDLS_SETUP_RESPONSE = 1,
+	TDLS_SETUP_CONFIRM = 2,
+	TDLS_TEARDOWN = 3,
+	TDLS_PEER_TRAFFIC_INDICATION = 4,
+	TDLS_CHANNEL_SWITCH_REQUEST = 5,
+	TDLS_CHANNEL_SWITCH_RESPONSE = 6,
+	TDLS_PEER_PSM_REQUEST = 7,
+	TDLS_PEER_PSM_RESPONSE = 8,
+	TDLS_PEER_TRAFFIC_RESPONSE = 9,
+	TDLS_DISCOVERY_REQUEST = 10,
+	TDLS_DISCOVERY_RESPONSE = 14,	/* it's used in public action frame */
+};
+
+#define	TUNNELED_PROBE_REQ	15
+#define	TUNNELED_PROBE_RSP	16
+#endif /* CONFIG_TDLS */
+
+/* BACK action code */
+enum rtw_ieee80211_back_actioncode {
+	RTW_WLAN_ACTION_ADDBA_REQ = 0,
+	RTW_WLAN_ACTION_ADDBA_RESP = 1,
+	RTW_WLAN_ACTION_DELBA = 2,
+};
+
+/* HT features action code */
+enum rtw_ieee80211_ht_actioncode {
+	RTW_WLAN_ACTION_HT_NOTI_CHNL_WIDTH = 0,
+	RTW_WLAN_ACTION_HT_SM_PS = 1,
+	RTW_WLAN_ACTION_HT_PSMP = 2,
+	RTW_WLAN_ACTION_HT_SET_PCO_PHASE = 3,
+	RTW_WLAN_ACTION_HT_CSI = 4,
+	RTW_WLAN_ACTION_HT_NON_COMPRESS_BEAMFORMING = 5,
+	RTW_WLAN_ACTION_HT_COMPRESS_BEAMFORMING = 6,
+	RTW_WLAN_ACTION_HT_ASEL_FEEDBACK = 7,
+};
+
+/* BACK (block-ack) parties */
+enum rtw_ieee80211_back_parties {
+	RTW_WLAN_BACK_RECIPIENT = 0,
+	RTW_WLAN_BACK_INITIATOR = 1,
+	RTW_WLAN_BACK_TIMER = 2,
+};
+
+/*20/40 BSS Coexistence element */
+#define RTW_WLAN_20_40_BSS_COEX_INFO_REQ            BIT(0)
+#define RTW_WLAN_20_40_BSS_COEX_40MHZ_INTOL         BIT(1)
+#define RTW_WLAN_20_40_BSS_COEX_20MHZ_WIDTH_REQ     BIT(2)
+#define RTW_WLAN_20_40_BSS_COEX_OBSS_EXEMPT_REQ     BIT(3)
+#define RTW_WLAN_20_40_BSS_COEX_OBSS_EXEMPT_GRNT    BIT(4)
+
+/* VHT features action code */
+enum rtw_ieee80211_vht_actioncode {
+	RTW_WLAN_ACTION_VHT_COMPRESSED_BEAMFORMING = 0,
+	RTW_WLAN_ACTION_VHT_GROUPID_MANAGEMENT = 1,
+	RTW_WLAN_ACTION_VHT_OPMODE_NOTIFICATION = 2,
+};
+
+/*IEEE 802.11r action code*/
+#ifdef CONFIG_RTW_80211R
+enum rtw_ieee80211_ft_actioncode {
+	RTW_WLAN_ACTION_FT_RESV,
+	RTW_WLAN_ACTION_FT_REQ,
+	RTW_WLAN_ACTION_FT_RSP,
+	RTW_WLAN_ACTION_FT_CONF,
+	RTW_WLAN_ACTION_FT_ACK,
+	RTW_WLAN_ACTION_FT_MAX,
+};
+#endif
+
+#ifdef CONFIG_RTW_WNM
+enum rtw_ieee80211_wnm_actioncode {
+	RTW_WLAN_ACTION_WNM_BTM_QUERY = 6,
+	RTW_WLAN_ACTION_WNM_BTM_REQ = 7,
+	RTW_WLAN_ACTION_WNM_BTM_RSP = 8,
+};
+#endif
+
+#define OUI_MICROSOFT 0x0050f2 /* Microsoft (also used in Wi-Fi specs)
+				* 00:50:F2 */
+#ifndef PLATFORM_FREEBSD /* Baron BSD has defined */
+	#define WME_OUI_TYPE 2
+#endif /* PLATFORM_FREEBSD */
+#define WME_OUI_SUBTYPE_INFORMATION_ELEMENT 0
+#define WME_OUI_SUBTYPE_PARAMETER_ELEMENT 1
+#define WME_OUI_SUBTYPE_TSPEC_ELEMENT 2
+#define WME_VERSION 1
+
+#define WME_ACTION_CODE_SETUP_REQUEST 0
+#define WME_ACTION_CODE_SETUP_RESPONSE 1
+#define WME_ACTION_CODE_TEARDOWN 2
+
+#define WME_SETUP_RESPONSE_STATUS_ADMISSION_ACCEPTED 0
+#define WME_SETUP_RESPONSE_STATUS_INVALID_PARAMETERS 1
+#define WME_SETUP_RESPONSE_STATUS_REFUSED 3
+
+#define WME_TSPEC_DIRECTION_UPLINK 0
+#define WME_TSPEC_DIRECTION_DOWNLINK 1
+#define WME_TSPEC_DIRECTION_BI_DIRECTIONAL 3
+
+
+#define OUI_BROADCOM 0x00904c /* Broadcom (Epigram) */
+
+#define VENDOR_HT_CAPAB_OUI_TYPE 0x33 /* 00-90-4c:0x33 */
+
+enum rtw_ieee80211_rann_flags {
+	RTW_RANN_FLAG_IS_GATE = 1 << 0,
+};
+
+/**
+ * enum rtw_ieee80211_preq_flags - mesh PREQ element flags
+ *
+ * @RTW_IEEE80211_PREQ_IS_GATE_FLAG: Gate Announcement subfield
+ * @RTW_IEEE80211_PREQ_PROACTIVE_PREP_FLAG: proactive PREP subfield
+ */
+enum rtw_ieee80211_preq_flags {
+	RTW_IEEE80211_PREQ_IS_GATE_FLAG = 1 << 0,
+	RTW_IEEE80211_PREQ_PROACTIVE_PREP_FLAG	= 1 << 2,
+};
+
+/**
+ * enum rtw_ieee80211_preq_target_flags - mesh PREQ element per target flags
+ *
+ * @RTW_IEEE80211_PREQ_TO_FLAG: target only subfield
+ * @RTW_IEEE80211_PREQ_USN_FLAG: unknown target HWMP sequence number subfield
+ */
+enum rtw_ieee80211_preq_target_flags {
+	RTW_IEEE80211_PREQ_TO_FLAG	= 1<<0,
+	RTW_IEEE80211_PREQ_USN_FLAG	= 1<<2,
+};
+
+/**
+ * enum rtw_ieee80211_root_mode_identifier - root mesh STA mode identifier
+ *
+ * These attribute are used by dot11MeshHWMPRootMode to set root mesh STA mode
+ *
+ * @RTW_IEEE80211_ROOTMODE_NO_ROOT: the mesh STA is not a root mesh STA (default)
+ * @RTW_IEEE80211_ROOTMODE_ROOT: the mesh STA is a root mesh STA if greater than
+ *	this value
+ * @RTW_IEEE80211_PROACTIVE_PREQ_NO_PREP: the mesh STA is a root mesh STA supports
+ *	the proactive PREQ with proactive PREP subfield set to 0
+ * @RTW_IEEE80211_PROACTIVE_PREQ_WITH_PREP: the mesh STA is a root mesh STA
+ *	supports the proactive PREQ with proactive PREP subfield set to 1
+ * @RTW_IEEE80211_PROACTIVE_RANN: the mesh STA is a root mesh STA supports
+ *	the proactive RANN
+ */
+enum rtw_ieee80211_root_mode_identifier {
+	RTW_IEEE80211_ROOTMODE_NO_ROOT = 0,
+	RTW_IEEE80211_ROOTMODE_ROOT = 1,
+	RTW_IEEE80211_PROACTIVE_PREQ_NO_PREP = 2,
+	RTW_IEEE80211_PROACTIVE_PREQ_WITH_PREP = 3,
+	RTW_IEEE80211_PROACTIVE_RANN = 4,
+};
+
+/**
+ * enum rtw_ieee80211_channel_flags - channel flags
+ *
+ * Channel flags set by the regulatory control code.
+ *
+ * @RTW_IEEE80211_CHAN_DISABLED: This channel is disabled.
+ * @RTW_IEEE80211_CHAN_PASSIVE_SCAN: Only passive scanning is permitted
+ *      on this channel.
+ * @RTW_IEEE80211_CHAN_NO_IBSS: IBSS is not allowed on this channel.
+ * @RTW_IEEE80211_CHAN_RADAR: Radar detection is required on this channel.
+ * @RTW_IEEE80211_CHAN_NO_HT40PLUS: extension channel above this channel
+ *      is not permitted.
+ * @RTW_IEEE80211_CHAN_NO_HT40MINUS: extension channel below this channel
+ *      is not permitted.
+ */
+enum rtw_ieee80211_channel_flags {
+	RTW_IEEE80211_CHAN_DISABLED         = 1 << 0,
+	RTW_IEEE80211_CHAN_PASSIVE_SCAN     = 1 << 1,
+	RTW_IEEE80211_CHAN_NO_IBSS          = 1 << 2,
+	RTW_IEEE80211_CHAN_RADAR            = 1 << 3,
+	RTW_IEEE80211_CHAN_NO_HT40PLUS      = 1 << 4,
+	RTW_IEEE80211_CHAN_NO_HT40MINUS     = 1 << 5,
+};
+
+#define RTW_IEEE80211_CHAN_NO_HT40 \
+	(RTW_IEEE80211_CHAN_NO_HT40PLUS | RTW_IEEE80211_CHAN_NO_HT40MINUS)
+
+/* Represent channel details, subset of ieee80211_channel */
+struct rtw_ieee80211_channel {
+	/* enum ieee80211_band band; */
+	/* u16 center_freq; */
+	u16 hw_value;
+	u32 flags;
+	/* int max_antenna_gain; */
+	/* int max_power; */
+	/* int max_reg_power; */
+	/* bool beacon_found; */
+	/* u32 orig_flags; */
+	/* int orig_mag; */
+	/* int orig_mpwr; */
+};
+
+#define CHAN_FMT \
+	/*"band:%d, "*/ \
+	/*"center_freq:%u, "*/ \
+	"hw_value:%u, " \
+	"flags:0x%08x" \
+	/*"max_antenna_gain:%d\n"*/ \
+	/*"max_power:%d\n"*/ \
+	/*"max_reg_power:%d\n"*/ \
+	/*"beacon_found:%u\n"*/ \
+	/*"orig_flags:0x%08x\n"*/ \
+	/*"orig_mag:%d\n"*/ \
+	/*"orig_mpwr:%d\n"*/
+
+#define CHAN_ARG(channel) \
+	/*(channel)->band*/ \
+	/*, (channel)->center_freq*/ \
+	(channel)->hw_value \
+	, (channel)->flags \
+	/*, (channel)->max_antenna_gain*/ \
+	/*, (channel)->max_power*/ \
+	/*, (channel)->max_reg_power*/ \
+	/*, (channel)->beacon_found*/ \
+	/*, (channel)->orig_flags*/ \
+	/*, (channel)->orig_mag*/ \
+	/*, (channel)->orig_mpwr*/ \
+
+/* Parsed Information Elements */
+struct rtw_ieee802_11_elems {
+	u8 *ssid;
+	u8 ssid_len;
+	u8 *supp_rates;
+	u8 supp_rates_len;
+	u8 *fh_params;
+	u8 fh_params_len;
+	u8 *ds_params;
+	u8 ds_params_len;
+	u8 *cf_params;
+	u8 cf_params_len;
+	u8 *tim;
+	u8 tim_len;
+	u8 *ibss_params;
+	u8 ibss_params_len;
+	u8 *challenge;
+	u8 challenge_len;
+	u8 *erp_info;
+	u8 erp_info_len;
+	u8 *ext_supp_rates;
+	u8 ext_supp_rates_len;
+	u8 *wpa_ie;
+	u8 wpa_ie_len;
+	u8 *rsn_ie;
+	u8 rsn_ie_len;
+	u8 *wme;
+	u8 wme_len;
+	u8 *wme_tspec;
+	u8 wme_tspec_len;
+	u8 *wps_ie;
+	u8 wps_ie_len;
+	u8 *power_cap;
+	u8 power_cap_len;
+	u8 *supp_channels;
+	u8 supp_channels_len;
+	u8 *mdie;
+	u8 mdie_len;
+	u8 *ftie;
+	u8 ftie_len;
+	u8 *timeout_int;
+	u8 timeout_int_len;
+	u8 *ht_capabilities;
+	u8 ht_capabilities_len;
+	u8 *ht_operation;
+	u8 ht_operation_len;
+	u8 *vendor_ht_cap;
+	u8 vendor_ht_cap_len;
+	u8 *vht_capabilities;
+	u8 vht_capabilities_len;
+	u8 *vht_operation;
+	u8 vht_operation_len;
+	u8 *vht_op_mode_notify;
+	u8 vht_op_mode_notify_len;
+	u8 *rm_en_cap;
+	u8 rm_en_cap_len;
+#ifdef CONFIG_RTW_MESH
+	u8 *preq;
+	u8 preq_len;
+	u8 *prep;
+	u8 prep_len;
+	u8 *perr;
+	u8 perr_len;
+	u8 *rann;
+	u8 rann_len;
+#endif
+};
+
+typedef enum { ParseOK = 0, ParseUnknown = 1, ParseFailed = -1 } ParseRes;
+
+ParseRes rtw_ieee802_11_parse_elems(u8 *start, uint len,
+				struct rtw_ieee802_11_elems *elems,
+				int show_errors);
+
+u8 *rtw_set_fixed_ie(unsigned char *pbuf, unsigned int len, unsigned char *source, unsigned int *frlen);
+u8 *rtw_set_ie(u8 *pbuf, sint index, uint len, const u8 *source, uint *frlen);
+
+enum secondary_ch_offset {
+	SCN = 0, /* no secondary channel */
+	SCA = 1, /* secondary channel above */
+	SCB = 3,  /* secondary channel below */
+};
+u8 secondary_ch_offset_to_hal_ch_offset(u8 ch_offset);
+u8 hal_ch_offset_to_secondary_ch_offset(u8 ch_offset);
+u8 *rtw_set_ie_ch_switch(u8 *buf, u32 *buf_len, u8 ch_switch_mode, u8 new_ch, u8 ch_switch_cnt);
+u8 *rtw_set_ie_secondary_ch_offset(u8 *buf, u32 *buf_len, u8 secondary_ch_offset);
+u8 *rtw_set_ie_mesh_ch_switch_parm(u8 *buf, u32 *buf_len, u8 ttl, u8 flags, u16 reason, u16 precedence);
+
+u8 *rtw_get_ie(const u8 *pbuf, sint index, sint *len, sint limit);
+int rtw_remove_ie_g_rate(u8 *ie, uint *ie_len, uint offset, u8 eid);
+u8 *rtw_get_ie_ex(const u8 *in_ie, uint in_len, u8 eid, const u8 *oui, u8 oui_len, u8 *ie, uint *ielen);
+int rtw_ies_remove_ie(u8 *ies, uint *ies_len, uint offset, u8 eid, u8 *oui, u8 oui_len);
+
+void rtw_set_supported_rate(u8 *SupportedRates, uint mode) ;
+
+#define GET_RSN_CAP_MFP_OPTION(cap)	LE_BITS_TO_2BYTE(((u8 *)(cap)), 6, 2)
+
+#define MFP_NO			0
+#define MFP_INVALID		1
+#define MFP_OPTIONAL	2
+#define MFP_REQUIRED	3
+
+struct rsne_info {
+	u8 *gcs;
+	u16 pcs_cnt;
+	u8 *pcs_list;
+	u16 akm_cnt;
+	u8 *akm_list;
+	u8 *cap;
+	u16 pmkid_cnt;
+	u8 *pmkid_list;
+	u8 *gmcs;
+
+	u8 err;
+};
+int rtw_rsne_info_parse(const u8 *ie, uint ie_len, struct rsne_info *info);
+
+unsigned char *rtw_get_wpa_ie(unsigned char *pie, int *wpa_ie_len, int limit);
+unsigned char *rtw_get_wpa2_ie(unsigned char *pie, int *rsn_ie_len, int limit);
+int rtw_get_wpa_cipher_suite(u8 *s);
+int rtw_get_wpa2_cipher_suite(u8 *s);
+int rtw_get_wapi_ie(u8 *in_ie, uint in_len, u8 *wapi_ie, u16 *wapi_len);
+int rtw_parse_wpa_ie(u8 *wpa_ie, int wpa_ie_len, int *group_cipher, int *pairwise_cipher, int *is_8021x);
+int rtw_parse_wpa2_ie(u8 *wpa_ie, int wpa_ie_len, int *group_cipher, int *pairwise_cipher, int *is_8021x, u8 *mfp_opt);
+
+int rtw_get_sec_ie(u8 *in_ie, uint in_len, u8 *rsn_ie, u16 *rsn_len, u8 *wpa_ie, u16 *wpa_len);
+
+u8 rtw_is_wps_ie(u8 *ie_ptr, uint *wps_ielen);
+u8 *rtw_get_wps_ie_from_scan_queue(u8 *in_ie, uint in_len, u8 *wps_ie, uint *wps_ielen, enum bss_type frame_type);
+u8 *rtw_get_wps_ie(const u8 *in_ie, uint in_len, u8 *wps_ie, uint *wps_ielen);
+u8 *rtw_get_wps_attr(u8 *wps_ie, uint wps_ielen, u16 target_attr_id , u8 *buf_attr, u32 *len_attr);
+u8 *rtw_get_wps_attr_content(u8 *wps_ie, uint wps_ielen, u16 target_attr_id , u8 *buf_content, uint *len_content);
+
+/**
+ * for_each_ie - iterate over continuous IEs
+ * @ie:
+ * @buf:
+ * @buf_len:
+ */
+#define for_each_ie(ie, buf, buf_len) \
+	for (ie = (void *)buf; (((u8 *)ie) - ((u8 *)buf) + 1) < buf_len; ie = (void *)(((u8 *)ie) + *(((u8 *)ie)+1) + 2))
+
+void dump_ies(void *sel, const u8 *buf, u32 buf_len);
+
+#ifdef CONFIG_80211N_HT
+#define HT_SC_OFFSET_MAX 4
+extern const char *const _ht_sc_offset_str[];
+#define ht_sc_offset_str(sc) (((sc) >= HT_SC_OFFSET_MAX) ? _ht_sc_offset_str[2] : _ht_sc_offset_str[(sc)])
+
+void dump_ht_cap_ie_content(void *sel, const u8 *buf, u32 buf_len);
+#endif
+
+void dump_wps_ie(void *sel, const u8 *ie, u32 ie_len);
+
+void rtw_ies_get_chbw(u8 *ies, int ies_len, u8 *ch, u8 *bw, u8 *offset, u8 ht, u8 vht);
+
+void rtw_bss_get_chbw(WLAN_BSSID_EX *bss, u8 *ch, u8 *bw, u8 *offset, u8 ht, u8 vht);
+
+bool rtw_is_chbw_grouped(u8 ch_a, u8 bw_a, u8 offset_a
+	, u8 ch_b, u8 bw_b, u8 offset_b);
+void rtw_sync_chbw(u8 *req_ch, u8 *req_bw, u8 *req_offset
+	, u8 *g_ch, u8 *g_bw, u8 *g_offset);
+
+u32 rtw_get_p2p_merged_ies_len(u8 *in_ie, u32 in_len);
+int rtw_p2p_merge_ies(u8 *in_ie, u32 in_len, u8 *merge_ie);
+void dump_p2p_ie(void *sel, const u8 *ie, u32 ie_len);
+u8 *rtw_get_p2p_ie(const u8 *in_ie, int in_len, u8 *p2p_ie, uint *p2p_ielen);
+u8 *rtw_get_p2p_attr(u8 *p2p_ie, uint p2p_ielen, u8 target_attr_id, u8 *buf_attr, u32 *len_attr);
+u8 *rtw_get_p2p_attr_content(u8 *p2p_ie, uint p2p_ielen, u8 target_attr_id, u8 *buf_content, uint *len_content);
+u32 rtw_set_p2p_attr_content(u8 *pbuf, u8 attr_id, u16 attr_len, u8 *pdata_attr);
+uint rtw_del_p2p_ie(u8 *ies, uint ies_len_ori, const char *msg);
+uint rtw_del_p2p_attr(u8 *ie, uint ielen_ori, u8 attr_id);
+u8 *rtw_bss_ex_get_p2p_ie(WLAN_BSSID_EX *bss_ex, u8 *p2p_ie, uint *p2p_ielen);
+void rtw_bss_ex_del_p2p_ie(WLAN_BSSID_EX *bss_ex);
+void rtw_bss_ex_del_p2p_attr(WLAN_BSSID_EX *bss_ex, u8 attr_id);
+
+void dump_wfd_ie(void *sel, const u8 *ie, u32 ie_len);
+u8 *rtw_get_wfd_ie(const u8 *in_ie, int in_len, u8 *wfd_ie, uint *wfd_ielen);
+u8 *rtw_get_wfd_attr(u8 *wfd_ie, uint wfd_ielen, u8 target_attr_id, u8 *buf_attr, u32 *len_attr);
+u8 *rtw_get_wfd_attr_content(u8 *wfd_ie, uint wfd_ielen, u8 target_attr_id, u8 *buf_content, uint *len_content);
+uint rtw_del_wfd_ie(u8 *ies, uint ies_len_ori, const char *msg);
+uint rtw_del_wfd_attr(u8 *ie, uint ielen_ori, u8 attr_id);
+u8 *rtw_bss_ex_get_wfd_ie(WLAN_BSSID_EX *bss_ex, u8 *wfd_ie, uint *wfd_ielen);
+void rtw_bss_ex_del_wfd_ie(WLAN_BSSID_EX *bss_ex);
+void rtw_bss_ex_del_wfd_attr(WLAN_BSSID_EX *bss_ex, u8 attr_id);
+
+uint	rtw_get_rateset_len(u8	*rateset);
+
+struct registry_priv;
+int rtw_generate_ie(struct registry_priv *pregistrypriv);
+
+int rtw_get_bit_value_from_ieee_value(u8 val);
+
+uint	rtw_is_cckrates_included(u8 *rate);
+
+uint	rtw_is_cckratesonly_included(u8 *rate);
+uint rtw_get_cckrate_size(u8 *rate,u32 rate_length);
+int rtw_check_network_type(unsigned char *rate, int ratelen, int channel);
+
+void rtw_get_bcn_info(struct wlan_network *pnetwork);
+
+u8 rtw_check_invalid_mac_address(u8 *mac_addr, u8 check_local_bit);
+void rtw_macaddr_cfg(u8 *out, const u8 *hw_mac_addr);
+
+u16 rtw_mcs_rate(u8 rf_type, u8 bw_40MHz, u8 short_GI, unsigned char *MCS_rate);
+u8	rtw_ht_mcsset_to_nss(u8 *supp_mcs_set);
+u32	rtw_ht_mcs_set_to_bitmap(u8 *mcs_set, u8 nss);
+
+int rtw_action_frame_parse(const u8 *frame, u32 frame_len, u8 *category, u8 *action);
+const char *action_public_str(u8 action);
+
+u8 key_2char2num(u8 hch, u8 lch);
+u8 str_2char2num(u8 hch, u8 lch);
+void macstr2num(u8 *dst, u8 *src);
+u8 convert_ip_addr(u8 hch, u8 mch, u8 lch);
+int wifirate2_ratetbl_inx(unsigned char rate);
+
+
+#endif /* IEEE80211_H */
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/include/if_ether.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/if_ether.h
--- linux-5.6.3/3rdparty/rtl8821ce/include/if_ether.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/if_ether.h	2020-04-10 16:35:06.847661515 +0300
@@ -0,0 +1,106 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+
+#ifndef _LINUX_IF_ETHER_H
+#define _LINUX_IF_ETHER_H
+
+/*
+ *	IEEE 802.3 Ethernet magic constants.  The frame sizes omit the preamble
+ *	and FCS/CRC (frame check sequence).
+ */
+
+#define ETH_ALEN	6		/* Octets in one ethernet addr	 */
+#define ETH_HLEN	14		/* Total octets in header.	 */
+#define ETH_ZLEN	60		/* Min. octets in frame sans FCS */
+#define ETH_DATA_LEN	1500		/* Max. octets in payload	 */
+#define ETH_FRAME_LEN	1514		/* Max. octets in frame sans FCS */
+
+/*
+ *	These are the defined Ethernet Protocol ID's.
+ */
+
+#define ETH_P_LOOP	0x0060		/* Ethernet Loopback packet	*/
+#define ETH_P_PUP	0x0200		/* Xerox PUP packet		*/
+#define ETH_P_PUPAT	0x0201		/* Xerox PUP Addr Trans packet	*/
+#define ETH_P_IP	0x0800		/* Internet Protocol packet	*/
+#define ETH_P_X25	0x0805		/* CCITT X.25			*/
+#define ETH_P_ARP	0x0806		/* Address Resolution packet	*/
+#define	ETH_P_BPQ	0x08FF		/* G8BPQ AX.25 Ethernet Packet	[ NOT AN OFFICIALLY REGISTERED ID ] */
+#define ETH_P_IEEEPUP	0x0a00		/* Xerox IEEE802.3 PUP packet */
+#define ETH_P_IEEEPUPAT	0x0a01		/* Xerox IEEE802.3 PUP Addr Trans packet */
+#define ETH_P_DEC       0x6000          /* DEC Assigned proto          */
+#define ETH_P_DNA_DL    0x6001          /* DEC DNA Dump/Load           */
+#define ETH_P_DNA_RC    0x6002          /* DEC DNA Remote Console      */
+#define ETH_P_DNA_RT    0x6003          /* DEC DNA Routing             */
+#define ETH_P_LAT       0x6004          /* DEC LAT                     */
+#define ETH_P_DIAG      0x6005          /* DEC Diagnostics             */
+#define ETH_P_CUST      0x6006          /* DEC Customer use            */
+#define ETH_P_SCA       0x6007          /* DEC Systems Comms Arch      */
+#define ETH_P_RARP      0x8035		/* Reverse Addr Res packet	*/
+#define ETH_P_ATALK	0x809B		/* Appletalk DDP		*/
+#define ETH_P_AARP	0x80F3		/* Appletalk AARP		*/
+#define ETH_P_8021Q	0x8100          /* 802.1Q VLAN Extended Header */
+#define ETH_P_IPX	0x8137		/* IPX over DIX			*/
+#define ETH_P_IPV6	0x86DD		/* IPv6 over bluebook		*/
+#define ETH_P_PPP_DISC	0x8863		/* PPPoE discovery messages    */
+#define ETH_P_PPP_SES	0x8864		/* PPPoE session messages	*/
+#define ETH_P_ATMMPOA	0x884c		/* MultiProtocol Over ATM	*/
+#define ETH_P_ATMFATE	0x8884		/* Frame-based ATM Transport
+					 * over Ethernet
+					 */
+
+/*
+ *	Non DIX types. Won't clash for 1500 types.
+ */
+
+#define ETH_P_802_3	0x0001		/* Dummy type for 802.3 frames */
+#define ETH_P_AX25	0x0002		/* Dummy protocol id for AX.25 */
+#define ETH_P_ALL	0x0003		/* Every packet (be careful!!!) */
+#define ETH_P_802_2	0x0004		/* 802.2 frames 		*/
+#define ETH_P_SNAP	0x0005		/* Internal only		*/
+#define ETH_P_DDCMP     0x0006          /* DEC DDCMP: Internal only    */
+#define ETH_P_WAN_PPP   0x0007          /* Dummy type for WAN PPP frames*/
+#define ETH_P_PPP_MP    0x0008          /* Dummy type for PPP MP frames */
+#define ETH_P_LOCALTALK 0x0009		/* Localtalk pseudo type 	*/
+#define ETH_P_PPPTALK	0x0010		/* Dummy type for Atalk over PPP*/
+#define ETH_P_TR_802_2	0x0011		/* 802.2 frames 		*/
+#define ETH_P_MOBITEX	0x0015		/* Mobitex (kaz@cafe.net)	*/
+#define ETH_P_CONTROL	0x0016		/* Card specific control frames */
+#define ETH_P_IRDA	0x0017		/* Linux-IrDA			*/
+#define ETH_P_ECONET	0x0018		/* Acorn Econet			*/
+
+/*
+ *	This is an Ethernet frame header.
+ */
+
+struct ethhdr {
+	unsigned char	h_dest[ETH_ALEN];	/* destination eth addr	*/
+	unsigned char	h_source[ETH_ALEN];	/* source ether addr	*/
+	unsigned short	h_proto;		/* packet type ID field	*/
+};
+
+struct _vlan {
+	unsigned short       h_vlan_TCI;                /* Encapsulates priority and VLAN ID */
+	unsigned short       h_vlan_encapsulated_proto;
+};
+
+
+
+#define get_vlan_id(pvlan) ((ntohs((unsigned short)pvlan->h_vlan_TCI)) & 0xfff)
+#define get_vlan_priority(pvlan) ((ntohs((unsigned short)pvlan->h_vlan_TCI))>>13)
+#define get_vlan_encap_proto(pvlan) (ntohs((unsigned short)pvlan->h_vlan_encapsulated_proto))
+
+
+#endif	/* _LINUX_IF_ETHER_H */
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/include/ip.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/ip.h
--- linux-5.6.3/3rdparty/rtl8821ce/include/ip.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/ip.h	2020-04-10 16:35:06.847661515 +0300
@@ -0,0 +1,135 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#ifndef _LINUX_IP_H
+#define _LINUX_IP_H
+
+/* SOL_IP socket options */
+
+#define IPTOS_TOS_MASK		0x1E
+#define IPTOS_TOS(tos)		((tos)&IPTOS_TOS_MASK)
+#define	IPTOS_LOWDELAY		0x10
+#define	IPTOS_THROUGHPUT	0x08
+#define	IPTOS_RELIABILITY	0x04
+#define	IPTOS_MINCOST		0x02
+
+#define IPTOS_PREC_MASK		0xE0
+#define IPTOS_PREC(tos)		((tos)&IPTOS_PREC_MASK)
+#define IPTOS_PREC_NETCONTROL           0xe0
+#define IPTOS_PREC_INTERNETCONTROL      0xc0
+#define IPTOS_PREC_CRITIC_ECP           0xa0
+#define IPTOS_PREC_FLASHOVERRIDE        0x80
+#define IPTOS_PREC_FLASH                0x60
+#define IPTOS_PREC_IMMEDIATE            0x40
+#define IPTOS_PREC_PRIORITY             0x20
+#define IPTOS_PREC_ROUTINE              0x00
+
+
+/* IP options */
+#define IPOPT_COPY		0x80
+#define IPOPT_CLASS_MASK	0x60
+#define IPOPT_NUMBER_MASK	0x1f
+
+#define	IPOPT_COPIED(o)		((o)&IPOPT_COPY)
+#define	IPOPT_CLASS(o)		((o)&IPOPT_CLASS_MASK)
+#define	IPOPT_NUMBER(o)		((o)&IPOPT_NUMBER_MASK)
+
+#define	IPOPT_CONTROL		0x00
+#define	IPOPT_RESERVED1		0x20
+#define	IPOPT_MEASUREMENT	0x40
+#define	IPOPT_RESERVED2		0x60
+
+#define IPOPT_END	(0 | IPOPT_CONTROL)
+#define IPOPT_NOOP	(1 | IPOPT_CONTROL)
+#define IPOPT_SEC	(2 | IPOPT_CONTROL | IPOPT_COPY)
+#define IPOPT_LSRR	(3 | IPOPT_CONTROL | IPOPT_COPY)
+#define IPOPT_TIMESTAMP	(4 | IPOPT_MEASUREMENT)
+#define IPOPT_RR	(7 | IPOPT_CONTROL)
+#define IPOPT_SID	(8 | IPOPT_CONTROL | IPOPT_COPY)
+#define IPOPT_SSRR	(9 | IPOPT_CONTROL | IPOPT_COPY)
+#define IPOPT_RA	(20 | IPOPT_CONTROL | IPOPT_COPY)
+
+#define IPVERSION	4
+#define MAXTTL		255
+#define IPDEFTTL	64
+
+/* struct timestamp, struct route and MAX_ROUTES are removed.
+
+   REASONS: it is clear that nobody used them because:
+   - MAX_ROUTES value was wrong.
+   - "struct route" was wrong.
+   - "struct timestamp" had fatally misaligned bitfields and was completely unusable.
+ */
+
+#define IPOPT_OPTVAL 0
+#define IPOPT_OLEN   1
+#define IPOPT_OFFSET 2
+#define IPOPT_MINOFF 4
+#define MAX_IPOPTLEN 40
+#define IPOPT_NOP IPOPT_NOOP
+#define IPOPT_EOL IPOPT_END
+#define IPOPT_TS  IPOPT_TIMESTAMP
+
+#define	IPOPT_TS_TSONLY		0		/* timestamps only */
+#define	IPOPT_TS_TSANDADDR	1		/* timestamps and addresses */
+#define	IPOPT_TS_PRESPEC	3		/* specified modules only */
+
+#ifdef PLATFORM_LINUX
+
+struct ip_options {
+	__u32		faddr;				/* Saved first hop address */
+	unsigned char	optlen;
+	unsigned char srr;
+	unsigned char rr;
+	unsigned char ts;
+	unsigned char is_setbyuser:1,			/* Set by setsockopt?			*/
+		 is_data:1,			/* Options in __data, rather than skb	*/
+		 is_strictroute:1,		/* Strict source route			*/
+		 srr_is_hit:1,			/* Packet destination addr was our one	*/
+		 is_changed:1,			/* IP checksum more not valid		*/
+		 rr_needaddr:1,			/* Need to record addr of outgoing dev	*/
+		 ts_needtime:1,			/* Need to record timestamp		*/
+		 ts_needaddr:1;			/* Need to record addr of outgoing dev */
+	unsigned char router_alert;
+	unsigned char __pad1;
+	unsigned char __pad2;
+	unsigned char __data[0];
+};
+
+#define optlength(opt) (sizeof(struct ip_options) + opt->optlen)
+#endif
+
+struct iphdr {
+#if defined(__LITTLE_ENDIAN_BITFIELD)
+	__u8	ihl:4,
+		version:4;
+#elif defined (__BIG_ENDIAN_BITFIELD)
+	__u8	version:4,
+		ihl:4;
+#else
+#error	"Please fix <asm/byteorder.h>"
+#endif
+	__u8	tos;
+	__u16	tot_len;
+	__u16	id;
+	__u16	frag_off;
+	__u8	ttl;
+	__u8	protocol;
+	__u16	check;
+	__u32	saddr;
+	__u32	daddr;
+	/*The options start here. */
+};
+
+#endif	/* _LINUX_IP_H */
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/include/linux/wireless.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/linux/wireless.h
--- linux-5.6.3/3rdparty/rtl8821ce/include/linux/wireless.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/linux/wireless.h	2020-04-10 16:35:06.847661515 +0300
@@ -0,0 +1,87 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+
+#ifndef _LINUX_WIRELESS_H
+#define _LINUX_WIRELESS_H
+
+/***************************** INCLUDES *****************************/
+
+#if 0
+	#include <linux/types.h>		/* for __u* and __s* typedefs */
+	#include <linux/socket.h>		/* for "struct sockaddr" et al	*/
+	#include <linux/if.h>			/* for IFNAMSIZ and co... */
+#else
+	#define __user
+	/* typedef uint16_t	__u16; */
+	#include <sys/socket.h>			/* for "struct sockaddr" et al	*/
+	#include <net/if.h>			/* for IFNAMSIZ and co... */
+#endif
+
+/****************************** TYPES ******************************/
+#ifdef CONFIG_COMPAT
+struct compat_iw_point {
+	compat_caddr_t pointer;
+	__u16 length;
+	__u16 flags;
+};
+#endif
+/* --------------------------- SUBTYPES --------------------------- */
+/*
+ *	For all data larger than 16 octets, we need to use a
+ *	pointer to memory allocated in user space.
+ */
+struct	iw_point {
+	void __user	*pointer;	/* Pointer to the data  (in user space) */
+	__u16		length;		/* number of fields or size in bytes */
+	__u16		flags;		/* Optional params */
+};
+
+
+/* ------------------------ IOCTL REQUEST ------------------------ */
+/*
+ * This structure defines the payload of an ioctl, and is used
+ * below.
+ *
+ * Note that this structure should fit on the memory footprint
+ * of iwreq (which is the same as ifreq), which mean a max size of
+ * 16 octets = 128 bits. Warning, pointers might be 64 bits wide...
+ * You should check this when increasing the structures defined
+ * above in this file...
+ */
+union	iwreq_data {
+	/* Config - generic */
+	char		name[IFNAMSIZ];
+	/* Name : used to verify the presence of  wireless extensions.
+	 * Name of the protocol/provider... */
+
+	struct iw_point	data;		/* Other large parameters */
+};
+
+/*
+ * The structure to exchange data for ioctl.
+ * This structure is the same as 'struct ifreq', but (re)defined for
+ * convenience...
+ * Do I need to remind you about structure size (32 octets) ?
+ */
+struct	iwreq {
+	union {
+		char	ifrn_name[IFNAMSIZ];	/* if name, e.g. "eth0" */
+	} ifr_ifrn;
+
+	/* Data part (defined just above) */
+	union	iwreq_data	u;
+};
+
+#endif	/* _LINUX_WIRELESS_H */
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/include/mlme_osdep.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/mlme_osdep.h
--- linux-5.6.3/3rdparty/rtl8821ce/include/mlme_osdep.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/mlme_osdep.h	2020-04-10 16:35:06.847661515 +0300
@@ -0,0 +1,25 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#ifndef	__MLME_OSDEP_H_
+#define __MLME_OSDEP_H_
+
+extern void rtw_os_indicate_disconnect(_adapter *adapter, u16 reason, u8 locally_generated);
+extern void rtw_os_indicate_connect(_adapter *adapter);
+void rtw_os_indicate_scan_done(_adapter *padapter, bool aborted);
+extern void rtw_report_sec_ie(_adapter *adapter, u8 authmode, u8 *sec_ie);
+
+void rtw_reset_securitypriv(_adapter *adapter);
+
+#endif /* _MLME_OSDEP_H_ */
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/include/mp_custom_oid.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/mp_custom_oid.h
--- linux-5.6.3/3rdparty/rtl8821ce/include/mp_custom_oid.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/mp_custom_oid.h	2020-04-10 16:35:06.847661515 +0300
@@ -0,0 +1,348 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#ifndef	__CUSTOM_OID_H
+#define __CUSTOM_OID_H
+
+/* by Owen
+ * 0xFF818000 - 0xFF81802F		RTL8180 Mass Production Kit
+ * 0xFF818500 - 0xFF81850F		RTL8185 Setup Utility
+ * 0xFF818580 - 0xFF81858F		RTL8185 Phy Status Utility */
+
+/*  */
+
+/* by Owen for Production Kit
+ * For Production Kit with Agilent Equipments
+ * in order to make our custom oids hopefully somewhat unique
+ * we will use 0xFF (indicating implementation specific OID)
+ * 81(first byte of non zero Realtek unique identifier)
+ * 80 (second byte of non zero Realtek unique identifier)
+ * XX (the custom OID number - providing 255 possible custom oids) */
+
+#define OID_RT_PRO_RESET_DUT				0xFF818000
+#define OID_RT_PRO_SET_DATA_RATE			0xFF818001
+#define OID_RT_PRO_START_TEST				0xFF818002
+#define OID_RT_PRO_STOP_TEST			0xFF818003
+#define OID_RT_PRO_SET_PREAMBLE				0xFF818004
+#define OID_RT_PRO_SET_SCRAMBLER			0xFF818005
+#define OID_RT_PRO_SET_FILTER_BB			0xFF818006
+#define OID_RT_PRO_SET_MANUAL_DIVERSITY_BB		0xFF818007
+#define OID_RT_PRO_SET_CHANNEL_DIRECT_CALL		0xFF818008
+#define OID_RT_PRO_SET_SLEEP_MODE_DIRECT_CALL		0xFF818009
+#define OID_RT_PRO_SET_WAKE_MODE_DIRECT_CALL		0xFF81800A
+
+#define OID_RT_PRO_SET_TX_ANTENNA_BB			0xFF81800D
+#define OID_RT_PRO_SET_ANTENNA_BB			0xFF81800E
+#define OID_RT_PRO_SET_CR_SCRAMBLER			0xFF81800F
+#define OID_RT_PRO_SET_CR_NEW_FILTER			0xFF818010
+#define OID_RT_PRO_SET_TX_POWER_CONTROL			0xFF818011
+#define OID_RT_PRO_SET_CR_TX_CONFIG			0xFF818012
+#define OID_RT_PRO_GET_TX_POWER_CONTROL			0xFF818013
+#define OID_RT_PRO_GET_CR_SIGNAL_QUALITY		0xFF818014
+#define OID_RT_PRO_SET_CR_SETPOINT			0xFF818015
+#define OID_RT_PRO_SET_INTEGRATOR			0xFF818016
+#define OID_RT_PRO_SET_SIGNAL_QUALITY			0xFF818017
+#define OID_RT_PRO_GET_INTEGRATOR			0xFF818018
+#define OID_RT_PRO_GET_SIGNAL_QUALITY			0xFF818019
+#define OID_RT_PRO_QUERY_EEPROM_TYPE			0xFF81801A
+#define OID_RT_PRO_WRITE_MAC_ADDRESS			0xFF81801B
+#define OID_RT_PRO_READ_MAC_ADDRESS			0xFF81801C
+#define OID_RT_PRO_WRITE_CIS_DATA			0xFF81801D
+#define OID_RT_PRO_READ_CIS_DATA			0xFF81801E
+#define OID_RT_PRO_WRITE_POWER_CONTROL			0xFF81801F
+#define OID_RT_PRO_READ_POWER_CONTROL			0xFF818020
+#define OID_RT_PRO_WRITE_EEPROM				0xFF818021
+#define OID_RT_PRO_READ_EEPROM				0xFF818022
+#define OID_RT_PRO_RESET_TX_PACKET_SENT			0xFF818023
+#define OID_RT_PRO_QUERY_TX_PACKET_SENT			0xFF818024
+#define OID_RT_PRO_RESET_RX_PACKET_RECEIVED		0xFF818025
+#define OID_RT_PRO_QUERY_RX_PACKET_RECEIVED		0xFF818026
+#define OID_RT_PRO_QUERY_RX_PACKET_CRC32_ERROR		0xFF818027
+#define OID_RT_PRO_QUERY_CURRENT_ADDRESS		0xFF818028
+#define OID_RT_PRO_QUERY_PERMANENT_ADDRESS		0xFF818029
+#define OID_RT_PRO_SET_PHILIPS_RF_PARAMETERS		0xFF81802A
+#define OID_RT_PRO_RECEIVE_PACKET			0xFF81802C
+/* added by Owen on 04/08/03 for Cameo's request */
+#define OID_RT_PRO_WRITE_EEPROM_BYTE			0xFF81802D
+#define OID_RT_PRO_READ_EEPROM_BYTE			0xFF81802E
+#define OID_RT_PRO_SET_MODULATION			0xFF81802F
+/*  */
+
+/* Sean		 */
+#define OID_RT_DRIVER_OPTION				0xFF818080
+#define OID_RT_RF_OFF					0xFF818081
+#define OID_RT_AUTH_STATUS				0xFF818082
+
+/* ************************************************************************ */
+#define OID_RT_PRO_SET_CONTINUOUS_TX			0xFF81800B
+#define OID_RT_PRO_SET_SINGLE_CARRIER_TX		0xFF81800C
+#define OID_RT_PRO_SET_CARRIER_SUPPRESSION_TX		0xFF81802B
+#define OID_RT_PRO_SET_SINGLE_TONE_TX			0xFF818043
+/* ************************************************************************ */
+
+
+/* by Owen for RTL8185 Phy Status Report Utility */
+#define OID_RT_UTILITY_FALSE_ALARM_COUNTERS				0xFF818580
+#define OID_RT_UTILITY_SELECT_DEBUG_MODE				0xFF818581
+#define OID_RT_UTILITY_SELECT_SUBCARRIER_NUMBER				0xFF818582
+#define OID_RT_UTILITY_GET_RSSI_STATUS					0xFF818583
+#define OID_RT_UTILITY_GET_FRAME_DETECTION_STATUS			0xFF818584
+#define OID_RT_UTILITY_GET_AGC_AND_FREQUENCY_OFFSET_ESTIMATION_STATUS	0xFF818585
+#define OID_RT_UTILITY_GET_CHANNEL_ESTIMATION_STATUS			0xFF818586
+/*  */
+
+/* by Owen on 03/09/19-03/09/22 for RTL8185 */
+#define OID_RT_WIRELESS_MODE				0xFF818500
+#define OID_RT_SUPPORTED_RATES				0xFF818501
+#define OID_RT_DESIRED_RATES				0xFF818502
+#define OID_RT_WIRELESS_MODE_STARTING_ADHOC		0xFF818503
+/*  */
+
+#define OID_RT_GET_CONNECT_STATE	0xFF030001
+#define OID_RT_RESCAN		0xFF030002
+#define OID_RT_SET_KEY_LENGTH				0xFF030003
+#define OID_RT_SET_DEFAULT_KEY_ID			0xFF030004
+
+#define OID_RT_SET_CHANNEL				0xFF010182
+#define OID_RT_SET_SNIFFER_MODE	0xFF010183
+#define OID_RT_GET_SIGNAL_QUALITY	0xFF010184
+#define OID_RT_GET_SMALL_PACKET_CRC			0xFF010185
+#define OID_RT_GET_MIDDLE_PACKET_CRC			0xFF010186
+#define OID_RT_GET_LARGE_PACKET_CRC			0xFF010187
+#define OID_RT_GET_TX_RETRY				0xFF010188
+#define OID_RT_GET_RX_RETRY				0xFF010189
+#define OID_RT_PRO_SET_FW_DIG_STATE			0xFF01018A/* S */
+#define OID_RT_PRO_SET_FW_RA_STATE			0xFF01018B/* S */
+
+#define OID_RT_GET_RX_TOTAL_PACKET			0xFF010190
+#define OID_RT_GET_TX_BEACON_OK				0xFF010191
+#define OID_RT_GET_TX_BEACON_ERR			0xFF010192
+#define OID_RT_GET_RX_ICV_ERR				0xFF010193
+#define OID_RT_SET_ENCRYPTION_ALGORITHM			0xFF010194
+#define OID_RT_SET_NO_AUTO_RESCAN			0xFF010195
+#define OID_RT_GET_PREAMBLE_MODE			0xFF010196
+#define OID_RT_GET_DRIVER_UP_DELTA_TIME			0xFF010197
+#define OID_RT_GET_AP_IP				0xFF010198
+#define OID_RT_GET_CHANNELPLAN				0xFF010199
+#define OID_RT_SET_PREAMBLE_MODE			0xFF01019A
+#define OID_RT_SET_BCN_INTVL				0xFF01019B
+#define OID_RT_GET_RF_VENDER				0xFF01019C
+#define OID_RT_DEDICATE_PROBE				0xFF01019D
+#define OID_RT_PRO_RX_FILTER_PATTERN			0xFF01019E
+
+#define OID_RT_GET_DCST_CURRENT_THRESHOLD		0xFF01019F
+
+#define OID_RT_GET_CCA_ERR				0xFF0101A0
+#define OID_RT_GET_CCA_UPGRADE_THRESHOLD		0xFF0101A1
+#define OID_RT_GET_CCA_FALLBACK_THRESHOLD		0xFF0101A2
+
+#define OID_RT_GET_CCA_UPGRADE_EVALUATE_TIMES		0xFF0101A3
+#define OID_RT_GET_CCA_FALLBACK_EVALUATE_TIMES		0xFF0101A4
+
+/* by Owen on 03/31/03 for Cameo's request */
+#define OID_RT_SET_RATE_ADAPTIVE			0xFF0101A5
+/*  */
+#define OID_RT_GET_DCST_EVALUATE_PERIOD			0xFF0101A5
+#define OID_RT_GET_DCST_TIME_UNIT_INDEX			0xFF0101A6
+#define OID_RT_GET_TOTAL_TX_BYTES			0xFF0101A7
+#define OID_RT_GET_TOTAL_RX_BYTES			0xFF0101A8
+#define OID_RT_CURRENT_TX_POWER_LEVEL			0xFF0101A9
+#define OID_RT_GET_ENC_KEY_MISMATCH_COUNT		0xFF0101AA
+#define OID_RT_GET_ENC_KEY_MATCH_COUNT			0xFF0101AB
+#define OID_RT_GET_CHANNEL				0xFF0101AC
+
+#define OID_RT_SET_CHANNELPLAN				0xFF0101AD
+#define OID_RT_GET_HARDWARE_RADIO_OFF			0xFF0101AE
+#define OID_RT_CHANNELPLAN_BY_COUNTRY			0xFF0101AF
+#define OID_RT_SCAN_AVAILABLE_BSSID			0xFF0101B0
+#define OID_RT_GET_HARDWARE_VERSION			0xFF0101B1
+#define OID_RT_GET_IS_ROAMING				0xFF0101B2
+#define OID_RT_GET_IS_PRIVACY				0xFF0101B3
+#define OID_RT_GET_KEY_MISMATCH				0xFF0101B4
+#define OID_RT_SET_RSSI_ROAM_TRAFFIC_TH			0xFF0101B5
+#define OID_RT_SET_RSSI_ROAM_SIGNAL_TH			0xFF0101B6
+#define OID_RT_RESET_LOG				0xFF0101B7
+#define OID_RT_GET_LOG					0xFF0101B8
+#define OID_RT_SET_INDICATE_HIDDEN_AP			0xFF0101B9
+#define OID_RT_GET_HEADER_FAIL				0xFF0101BA
+#define OID_RT_SUPPORTED_WIRELESS_MODE			0xFF0101BB
+#define OID_RT_GET_CHANNEL_LIST				0xFF0101BC
+#define OID_RT_GET_SCAN_IN_PROGRESS			0xFF0101BD
+#define OID_RT_GET_TX_INFO				0xFF0101BE
+#define OID_RT_RF_READ_WRITE_OFFSET			0xFF0101BF
+#define OID_RT_RF_READ_WRITE				0xFF0101C0
+
+/* For Netgear request. 2005.01.13, by rcnjko. */
+#define OID_RT_FORCED_DATA_RATE				0xFF0101C1
+#define OID_RT_WIRELESS_MODE_FOR_SCAN_LIST		0xFF0101C2
+/* For Netgear request. 2005.02.17, by rcnjko. */
+#define OID_RT_GET_BSS_WIRELESS_MODE			0xFF0101C3
+/* For AZ project. 2005.06.27, by rcnjko. */
+#define OID_RT_SCAN_WITH_MAGIC_PACKET			0xFF0101C4
+
+/* Vincent 8185MP */
+#define OID_RT_PRO_RX_FILTER				0xFF0111C0
+
+/* Andy TEST
+ * #define OID_RT_PRO_WRITE_REGISTRY			0xFF0111C1
+ * #define OID_RT_PRO_READ_REGISTRY			0xFF0111C2 */
+#define OID_CE_USB_WRITE_REGISTRY			0xFF0111C1
+#define OID_CE_USB_READ_REGISTRY			0xFF0111C2
+
+
+#define OID_RT_PRO_SET_INITIAL_GAIN			0xFF0111C3
+#define OID_RT_PRO_SET_BB_RF_STANDBY_MODE		0xFF0111C4
+#define OID_RT_PRO_SET_BB_RF_SHUTDOWN_MODE		0xFF0111C5
+#define OID_RT_PRO_SET_TX_CHARGE_PUMP			0xFF0111C6
+#define OID_RT_PRO_SET_RX_CHARGE_PUMP			0xFF0111C7
+#define OID_RT_PRO_RF_WRITE_REGISTRY			0xFF0111C8
+#define OID_RT_PRO_RF_READ_REGISTRY			0xFF0111C9
+#define OID_RT_PRO_QUERY_RF_TYPE			0xFF0111CA
+
+/* AP OID */
+#define OID_RT_AP_GET_ASSOCIATED_STATION_LIST		0xFF010300
+#define OID_RT_AP_GET_CURRENT_TIME_STAMP		0xFF010301
+#define OID_RT_AP_SWITCH_INTO_AP_MODE			0xFF010302
+#define OID_RT_AP_SET_DTIM_PERIOD			0xFF010303
+#define OID_RT_AP_SUPPORTED				0xFF010304	/* Determine if driver supports AP mode. 2004.08.27, by rcnjko. */
+#define OID_RT_AP_SET_PASSPHRASE			0xFF010305	/* Set WPA-PSK passphrase into authenticator. 2005.07.08, byrcnjko. */
+
+/* 8187MP. 2004.09.06, by rcnjko. */
+#define OID_RT_PRO8187_WI_POLL				0xFF818780
+#define OID_RT_PRO_WRITE_BB_REG				0xFF818781
+#define OID_RT_PRO_READ_BB_REG				0xFF818782
+#define OID_RT_PRO_WRITE_RF_REG				0xFF818783
+#define OID_RT_PRO_READ_RF_REG				0xFF818784
+
+/* Meeting House. added by Annie, 2005-07-20. */
+#define OID_RT_MH_VENDER_ID				0xFFEDC100
+
+/* 8711 MP OID added 20051230. */
+#define OID_RT_PRO8711_JOIN_BSS				0xFF871100/* S */
+
+#define OID_RT_PRO_READ_REGISTER			0xFF871101 /* Q */
+#define OID_RT_PRO_WRITE_REGISTER			0xFF871102 /* S */
+
+#define OID_RT_PRO_BURST_READ_REGISTER			0xFF871103 /* Q		 */
+#define OID_RT_PRO_BURST_WRITE_REGISTER 		0xFF871104 /* S */
+
+#define OID_RT_PRO_WRITE_TXCMD				0xFF871105 /* S */
+
+#define OID_RT_PRO_READ16_EEPROM			0xFF871106 /* Q */
+#define OID_RT_PRO_WRITE16_EEPROM			0xFF871107 /* S */
+
+#define OID_RT_PRO_H2C_SET_COMMAND			0xFF871108 /* S */
+#define OID_RT_PRO_H2C_QUERY_RESULT			0xFF871109 /* Q */
+
+#define OID_RT_PRO8711_WI_POLL				0xFF87110A /* Q */
+#define OID_RT_PRO8711_PKT_LOSS				0xFF87110B /* Q */
+#define OID_RT_RD_ATTRIB_MEM				0xFF87110C/* Q */
+#define OID_RT_WR_ATTRIB_MEM				0xFF87110D/* S */
+
+
+/* Method 2 for H2C/C2H */
+#define OID_RT_PRO_H2C_CMD_MODE				0xFF871110 /* S */
+#define OID_RT_PRO_H2C_CMD_RSP_MODE			0xFF871111 /* Q */
+#define OID_RT_PRO_H2C_CMD_EVENT_MODE			0xFF871112 /* S */
+#define OID_RT_PRO_WAIT_C2H_EVENT			0xFF871113 /* Q */
+#define OID_RT_PRO_RW_ACCESS_PROTOCOL_TEST		0xFF871114/* Q */
+
+#define OID_RT_PRO_SCSI_ACCESS_TEST			0xFF871115 /* Q, S */
+
+#define OID_RT_PRO_SCSI_TCPIPOFFLOAD_OUT		0xFF871116 /* S */
+#define OID_RT_PRO_SCSI_TCPIPOFFLOAD_IN			0xFF871117 /* Q, S */
+#define OID_RT_RRO_RX_PKT_VIA_IOCTRL			0xFF871118 /* Q */
+#define OID_RT_RRO_RX_PKTARRAY_VIA_IOCTRL		0xFF871119 /* Q */
+
+#define OID_RT_RPO_SET_PWRMGT_TEST			0xFF87111A /* S */
+#define OID_RT_PRO_QRY_PWRMGT_TEST			0XFF87111B /* Q */
+#define OID_RT_RPO_ASYNC_RWIO_TEST			0xFF87111C /* S */
+#define OID_RT_RPO_ASYNC_RWIO_POLL			0xFF87111D /* Q */
+#define OID_RT_PRO_SET_RF_INTFS				0xFF87111E /* S */
+#define OID_RT_POLL_RX_STATUS				0xFF87111F /* Q */
+
+#define OID_RT_PRO_CFG_DEBUG_MESSAGE			0xFF871120 /* Q, S */
+#define OID_RT_PRO_SET_DATA_RATE_EX			0xFF871121/* S */
+#define OID_RT_PRO_SET_BASIC_RATE			0xFF871122/* S */
+#define OID_RT_PRO_READ_TSSI				0xFF871123/* S */
+#define OID_RT_PRO_SET_POWER_TRACKING			0xFF871124/* S */
+
+
+#define OID_RT_PRO_QRY_PWRSTATE				0xFF871150 /* Q */
+#define OID_RT_PRO_SET_PWRSTATE				0xFF871151 /* S */
+
+/* Method 2 , using workitem */
+#define OID_RT_SET_READ_REG				0xFF871181 /* S */
+#define OID_RT_SET_WRITE_REG				0xFF871182 /* S */
+#define OID_RT_SET_BURST_READ_REG			0xFF871183 /* S */
+#define OID_RT_SET_BURST_WRITE_REG			0xFF871184 /* S */
+#define OID_RT_SET_WRITE_TXCMD				0xFF871185 /* S */
+#define OID_RT_SET_READ16_EEPROM			0xFF871186 /* S */
+#define OID_RT_SET_WRITE16_EEPROM			0xFF871187 /* S */
+#define OID_RT_QRY_POLL_WKITEM				0xFF871188 /* Q */
+
+/* For SDIO INTERFACE only */
+#define OID_RT_PRO_SYNCPAGERW_SRAM			0xFF8711A0 /* Q, S */
+#define OID_RT_PRO_871X_DRV_EXT			0xFF8711A1
+
+/* For USB INTERFACE only */
+#define OID_RT_PRO_USB_VENDOR_REQ			0xFF8711B0 /* Q, S */
+#define OID_RT_PRO_SCSI_AUTO_TEST			0xFF8711B1 /* S */
+#define OID_RT_PRO_USB_MAC_AC_FIFO_WRITE		0xFF8711B2 /* S */
+#define OID_RT_PRO_USB_MAC_RX_FIFO_READ			0xFF8711B3 /* Q */
+#define OID_RT_PRO_USB_MAC_RX_FIFO_POLLING		0xFF8711B4 /* Q */
+
+#define OID_RT_PRO_H2C_SET_RATE_TABLE			0xFF8711FB /* S */
+#define OID_RT_PRO_H2C_GET_RATE_TABLE			0xFF8711FC /* S */
+#define OID_RT_PRO_H2C_C2H_LBK_TEST			0xFF8711FE
+
+#define OID_RT_PRO_ENCRYPTION_CTRL			0xFF871200 /* Q, S */
+#define OID_RT_PRO_ADD_STA_INFO				0xFF871201 /* S */
+#define OID_RT_PRO_DELE_STA_INFO    			0xFF871202 /* S */
+#define OID_RT_PRO_QUERY_DR_VARIABLE   			0xFF871203 /* Q */
+
+#define OID_RT_PRO_RX_PACKET_TYPE			0xFF871204 /* Q, S */
+
+#define OID_RT_PRO_READ_EFUSE				0xFF871205 /* Q */
+#define OID_RT_PRO_WRITE_EFUSE				0xFF871206 /* S */
+#define OID_RT_PRO_RW_EFUSE_PGPKT			0xFF871207 /* Q, S */
+#define OID_RT_GET_EFUSE_CURRENT_SIZE			0xFF871208 /* Q */
+
+#define OID_RT_SET_BANDWIDTH				0xFF871209 /* S */
+#define OID_RT_SET_CRYSTAL_CAP				0xFF87120A /* S */
+
+#define OID_RT_SET_RX_PACKET_TYPE    			0xFF87120B /* S */
+
+#define OID_RT_GET_EFUSE_MAX_SIZE			0xFF87120C /* Q */
+
+#define OID_RT_PRO_SET_TX_AGC_OFFSET			0xFF87120D /* S */
+
+#define OID_RT_PRO_SET_PKT_TEST_MODE			0xFF87120E /* S */
+
+#define OID_RT_PRO_FOR_EVM_TEST_SETTING			0xFF87120F /* S */
+
+#define OID_RT_PRO_GET_THERMAL_METER			0xFF871210 /* Q */
+
+#define OID_RT_RESET_PHY_RX_PACKET_COUNT		0xFF871211 /* S */
+#define OID_RT_GET_PHY_RX_PACKET_RECEIVED		0xFF871212 /* Q */
+#define OID_RT_GET_PHY_RX_PACKET_CRC32_ERROR		0xFF871213 /* Q */
+
+#define OID_RT_SET_POWER_DOWN				0xFF871214 /* S */
+
+#define OID_RT_GET_POWER_MODE				0xFF871215 /* Q */
+
+#define OID_RT_PRO_EFUSE				0xFF871216 /* Q, S */
+#define OID_RT_PRO_EFUSE_MAP				0xFF871217 /* Q, S */
+
+#endif /* #ifndef	__CUSTOM_OID_H */
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/include/nic_spec.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/nic_spec.h
--- linux-5.6.3/3rdparty/rtl8821ce/include/nic_spec.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/nic_spec.h	2020-04-10 16:35:06.847661515 +0300
@@ -0,0 +1,41 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+
+
+#ifndef __NIC_SPEC_H__
+#define __NIC_SPEC_H__
+
+#include <drv_conf.h>
+
+#define RTL8711_MCTRL_		(0x20000)
+#define RTL8711_UART_		(0x30000)
+#define RTL8711_TIMER_		(0x40000)
+#define RTL8711_FINT_		(0x50000)
+#define RTL8711_HINT_		(0x50000)
+#define RTL8711_GPIO_		(0x60000)
+#define RTL8711_WLANCTRL_	(0x200000)
+#define RTL8711_WLANFF_		(0xe00000)
+#define RTL8711_HCICTRL_	(0x600000)
+#define RTL8711_SYSCFG_		(0x620000)
+#define RTL8711_SYSCTRL_	(0x620000)
+#define RTL8711_MCCTRL_		(0x020000)
+
+
+#include <rtl8711_regdef.h>
+
+#include <rtl8711_bitdef.h>
+
+
+#endif /* __RTL8711_SPEC_H__ */
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/include/osdep_intf.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/osdep_intf.h
--- linux-5.6.3/3rdparty/rtl8821ce/include/osdep_intf.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/osdep_intf.h	2020-04-10 16:35:06.848661561 +0300
@@ -0,0 +1,167 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+
+#ifndef __OSDEP_INTF_H_
+#define __OSDEP_INTF_H_
+
+
+struct intf_priv {
+
+	u8 *intf_dev;
+	u32	max_iosz;	/* USB2.0: 128, USB1.1: 64, SDIO:64 */
+	u32	max_xmitsz; /* USB2.0: unlimited, SDIO:512 */
+	u32	max_recvsz; /* USB2.0: unlimited, SDIO:512 */
+
+	volatile u8 *io_rwmem;
+	volatile u8 *allocated_io_rwmem;
+	u32	io_wsz; /* unit: 4bytes */
+	u32	io_rsz;/* unit: 4bytes */
+	u8 intf_status;
+
+	void (*_bus_io)(u8 *priv);
+
+	/*
+	Under Sync. IRP (SDIO/USB)
+	A protection mechanism is necessary for the io_rwmem(read/write protocol)
+
+	Under Async. IRP (SDIO/USB)
+	The protection mechanism is through the pending queue.
+	*/
+
+	_mutex ioctl_mutex;
+
+
+#ifdef PLATFORM_LINUX
+#ifdef CONFIG_USB_HCI
+	/* when in USB, IO is through interrupt in/out endpoints */
+	struct usb_device	*udev;
+	PURB	piorw_urb;
+	u8 io_irp_cnt;
+	u8 bio_irp_pending;
+	_sema io_retevt;
+	_timer	io_timer;
+	u8 bio_irp_timeout;
+	u8 bio_timer_cancel;
+#endif
+#endif
+
+#ifdef PLATFORM_OS_XP
+#ifdef CONFIG_SDIO_HCI
+	/* below is for io_rwmem... */
+	PMDL pmdl;
+	PSDBUS_REQUEST_PACKET  sdrp;
+	PSDBUS_REQUEST_PACKET  recv_sdrp;
+	PSDBUS_REQUEST_PACKET  xmit_sdrp;
+
+	PIRP		piorw_irp;
+
+#endif
+#ifdef CONFIG_USB_HCI
+	PURB	piorw_urb;
+	PIRP		piorw_irp;
+	u8 io_irp_cnt;
+	u8 bio_irp_pending;
+	_sema io_retevt;
+#endif
+#endif
+
+};
+
+
+#ifdef CONFIG_R871X_TEST
+	int rtw_start_pseudo_adhoc(_adapter *padapter);
+	int rtw_stop_pseudo_adhoc(_adapter *padapter);
+#endif
+
+struct dvobj_priv *devobj_init(void);
+void devobj_deinit(struct dvobj_priv *pdvobj);
+
+u8 rtw_init_drv_sw(_adapter *padapter);
+u8 rtw_free_drv_sw(_adapter *padapter);
+u8 rtw_reset_drv_sw(_adapter *padapter);
+void rtw_dev_unload(PADAPTER padapter);
+
+u32 rtw_start_drv_threads(_adapter *padapter);
+void rtw_stop_drv_threads(_adapter *padapter);
+#if defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN)
+void rtw_cancel_dynamic_chk_timer(_adapter *padapter);
+#endif
+void rtw_cancel_all_timer(_adapter *padapter);
+
+uint loadparam(_adapter *adapter);
+
+#ifdef PLATFORM_LINUX
+int rtw_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
+
+int rtw_init_netdev_name(struct net_device *pnetdev, const char *ifname);
+struct net_device *rtw_init_netdev(_adapter *padapter);
+
+void rtw_os_ndev_free(_adapter *adapter);
+int rtw_os_ndev_init(_adapter *adapter, const char *name);
+void rtw_os_ndev_deinit(_adapter *adapter);
+void rtw_os_ndev_unregister(_adapter *adapter);
+void rtw_os_ndevs_unregister(struct dvobj_priv *dvobj);
+int rtw_os_ndevs_init(struct dvobj_priv *dvobj);
+void rtw_os_ndevs_deinit(struct dvobj_priv *dvobj);
+
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 35))
+u16 rtw_recv_select_queue(struct sk_buff *skb);
+#endif /* LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 35) */
+
+int rtw_ndev_notifier_register(void);
+void rtw_ndev_notifier_unregister(void);
+void rtw_inetaddr_notifier_register(void);
+void rtw_inetaddr_notifier_unregister(void);
+
+#include "../os_dep/linux/rtw_proc.h"
+
+#ifdef CONFIG_IOCTL_CFG80211
+	#include "../os_dep/linux/ioctl_cfg80211.h"
+#endif /* CONFIG_IOCTL_CFG80211 */
+
+u8 rtw_rtnl_lock_needed(struct dvobj_priv *dvobj);
+void rtw_set_rtnl_lock_holder(struct dvobj_priv *dvobj, _thread_hdl_ thd_hdl);
+
+#endif /* PLATFORM_LINUX */
+
+
+#ifdef PLATFORM_FREEBSD
+extern int rtw_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data);
+#endif
+
+void rtw_ips_dev_unload(_adapter *padapter);
+
+#ifdef CONFIG_IPS
+int rtw_ips_pwr_up(_adapter *padapter);
+void rtw_ips_pwr_down(_adapter *padapter);
+#endif
+
+#ifdef CONFIG_CONCURRENT_MODE
+struct _io_ops;
+struct dvobj_priv;
+_adapter *rtw_drv_add_vir_if(_adapter *primary_padapter, void (*set_intf_ops)(_adapter *primary_padapter, struct _io_ops *pops));
+void rtw_drv_stop_vir_ifaces(struct dvobj_priv *dvobj);
+void rtw_drv_free_vir_ifaces(struct dvobj_priv *dvobj);
+#endif
+
+void rtw_ndev_destructor(_nic_hdl ndev);
+#ifdef CONFIG_ARP_KEEP_ALIVE
+int rtw_gw_addr_query(_adapter *padapter);
+#endif
+
+int rtw_suspend_common(_adapter *padapter);
+int rtw_resume_common(_adapter *padapter);
+
+#endif /* _OSDEP_INTF_H_ */
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/include/osdep_service_bsd.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/osdep_service_bsd.h
--- linux-5.6.3/3rdparty/rtl8821ce/include/osdep_service_bsd.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/osdep_service_bsd.h	2020-04-10 16:35:06.848661561 +0300
@@ -0,0 +1,756 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#ifndef __OSDEP_BSD_SERVICE_H_
+#define __OSDEP_BSD_SERVICE_H_
+
+
+#include <sys/cdefs.h>
+#include <sys/types.h>
+#include <sys/systm.h>
+#include <sys/param.h>
+#include <sys/sockio.h>
+#include <sys/sysctl.h>
+#include <sys/lock.h>
+#include <sys/mutex.h>
+#include <sys/mbuf.h>
+#include <sys/kernel.h>
+#include <sys/socket.h>
+#include <sys/systm.h>
+#include <sys/malloc.h>
+#include <sys/module.h>
+#include <sys/bus.h>
+#include <sys/endian.h>
+#include <sys/kdb.h>
+#include <sys/kthread.h>
+#include <sys/malloc.h>
+#include <sys/time.h>
+#include <machine/atomic.h>
+#include <machine/bus.h>
+#include <machine/resource.h>
+#include <sys/rman.h>
+
+#include <net/bpf.h>
+#include <net/if.h>
+#include <net/if_arp.h>
+#include <net/ethernet.h>
+#include <net/if_dl.h>
+#include <net/if_media.h>
+#include <net/if_types.h>
+#include <net/route.h>
+
+
+#include <netinet/in.h>
+#include <netinet/in_systm.h>
+#include <netinet/in_var.h>
+#include <netinet/if_ether.h>
+#include <if_ether.h>
+
+#include <net80211/ieee80211_var.h>
+#include <net80211/ieee80211_regdomain.h>
+#include <net80211/ieee80211_radiotap.h>
+#include <net80211/ieee80211_ratectl.h>
+
+#include <dev/usb/usb.h>
+#include <dev/usb/usbdi.h>
+#include "usbdevs.h"
+
+#define	USB_DEBUG_VAR rum_debug
+#include <dev/usb/usb_debug.h>
+
+#if 1 //Baron porting from linux, it's all temp solution, needs to check again
+#include <sys/sema.h>
+#include <sys/pcpu.h> /* XXX for PCPU_GET */
+//	typedef struct 	semaphore _sema;
+	typedef struct 	sema _sema;
+//	typedef	spinlock_t	_lock;
+	typedef	struct mtx	_lock;
+	typedef struct mtx 		_mutex;
+	typedef struct rtw_timer_list _timer;
+	struct list_head {
+	struct list_head *next, *prev;
+	};
+	struct	__queue	{
+		struct	list_head	queue;	
+		_lock	lock;
+	};
+
+	typedef	struct mbuf _pkt;
+	typedef struct mbuf	_buffer;
+	
+	typedef struct	__queue	_queue;
+	typedef struct	list_head	_list;
+	typedef	int	_OS_STATUS;
+	//typedef u32	_irqL;
+	typedef unsigned long _irqL;
+	typedef	struct	ifnet * _nic_hdl;
+	
+	typedef pid_t		_thread_hdl_;
+//	typedef struct thread		_thread_hdl_;
+	typedef void		thread_return;
+	typedef void*	thread_context;
+
+	typedef void timer_hdl_return;
+	typedef void* timer_hdl_context;
+	typedef struct work_struct _workitem;
+
+#define   KERNEL_VERSION(a,b,c) (((a) << 16) + ((b) << 8) + (c))
+/* emulate a modern version */
+#define LINUX_VERSION_CODE KERNEL_VERSION(2, 6, 35)
+
+#define WIRELESS_EXT -1
+#define HZ hz
+#define spin_lock_irqsave mtx_lock_irqsave
+#define spin_lock_bh mtx_lock_irqsave
+#define mtx_lock_irqsave(lock, x) mtx_lock(lock)//{local_irq_save((x)); mtx_lock_spin((lock));}
+//#define IFT_RTW	0xf9 //ifnet allocate type for RTW
+#define free_netdev if_free
+#define LIST_CONTAINOR(ptr, type, member) \
+        ((type *)((char *)(ptr)-(SIZE_T)(&((type *)0)->member)))
+#define container_of(p,t,n) (t*)((p)-&(((t*)0)->n))
+/* 
+ * Linux timers are emulated using FreeBSD callout functions
+ * (and taskqueue functionality).
+ *
+ * Currently no timer stats functionality.
+ *
+ * See (linux_compat) processes.c
+ *
+ */
+struct rtw_timer_list {
+	struct callout callout;
+	void (*function)(void *);
+	void *arg;
+};
+
+struct workqueue_struct;
+struct work_struct;
+typedef void (*work_func_t)(struct work_struct *work);
+/* Values for the state of an item of work (work_struct) */
+typedef enum work_state {
+        WORK_STATE_UNSET = 0,
+        WORK_STATE_CALLOUT_PENDING = 1,
+        WORK_STATE_TASK_PENDING = 2,
+        WORK_STATE_WORK_CANCELLED = 3        
+} work_state_t;
+
+struct work_struct {
+        struct task task; /* FreeBSD task */
+        work_state_t state; /* the pending or otherwise state of work. */
+        work_func_t func;       
+};
+#define spin_unlock_irqrestore mtx_unlock_irqrestore
+#define spin_unlock_bh mtx_unlock_irqrestore
+#define mtx_unlock_irqrestore(lock,x)    mtx_unlock(lock);
+extern void	_rtw_spinlock_init(_lock *plock);
+
+//modify private structure to match freebsd
+#define BITS_PER_LONG 32
+union ktime {
+	s64	tv64;
+#if BITS_PER_LONG != 64 && !defined(CONFIG_KTIME_SCALAR)
+	struct {
+#ifdef __BIG_ENDIAN
+	s32	sec, nsec;
+#else
+	s32	nsec, sec;
+#endif
+	} tv;
+#endif
+};
+#define kmemcheck_bitfield_begin(name)
+#define kmemcheck_bitfield_end(name)
+#define CHECKSUM_NONE 0
+typedef unsigned char *sk_buff_data_t;
+typedef union ktime ktime_t;		/* Kill this */
+
+void rtw_mtx_lock(_lock *plock);
+	
+void rtw_mtx_unlock(_lock *plock);
+
+/** 
+ *	struct sk_buff - socket buffer
+ *	@next: Next buffer in list
+ *	@prev: Previous buffer in list
+ *	@sk: Socket we are owned by
+ *	@tstamp: Time we arrived
+ *	@dev: Device we arrived on/are leaving by
+ *	@transport_header: Transport layer header
+ *	@network_header: Network layer header
+ *	@mac_header: Link layer header
+ *	@_skb_refdst: destination entry (with norefcount bit)
+ *	@sp: the security path, used for xfrm
+ *	@cb: Control buffer. Free for use by every layer. Put private vars here
+ *	@len: Length of actual data
+ *	@data_len: Data length
+ *	@mac_len: Length of link layer header
+ *	@hdr_len: writable header length of cloned skb
+ *	@csum: Checksum (must include start/offset pair)
+ *	@csum_start: Offset from skb->head where checksumming should start
+ *	@csum_offset: Offset from csum_start where checksum should be stored
+ *	@local_df: allow local fragmentation
+ *	@cloned: Head may be cloned (check refcnt to be sure)
+ *	@nohdr: Payload reference only, must not modify header
+ *	@pkt_type: Packet class
+ *	@fclone: skbuff clone status
+ *	@ip_summed: Driver fed us an IP checksum
+ *	@priority: Packet queueing priority
+ *	@users: User count - see {datagram,tcp}.c
+ *	@protocol: Packet protocol from driver
+ *	@truesize: Buffer size 
+ *	@head: Head of buffer
+ *	@data: Data head pointer
+ *	@tail: Tail pointer
+ *	@end: End pointer
+ *	@destructor: Destruct function
+ *	@mark: Generic packet mark
+ *	@nfct: Associated connection, if any
+ *	@ipvs_property: skbuff is owned by ipvs
+ *	@peeked: this packet has been seen already, so stats have been
+ *		done for it, don't do them again
+ *	@nf_trace: netfilter packet trace flag
+ *	@nfctinfo: Relationship of this skb to the connection
+ *	@nfct_reasm: netfilter conntrack re-assembly pointer
+ *	@nf_bridge: Saved data about a bridged frame - see br_netfilter.c
+ *	@skb_iif: ifindex of device we arrived on
+ *	@rxhash: the packet hash computed on receive
+ *	@queue_mapping: Queue mapping for multiqueue devices
+ *	@tc_index: Traffic control index
+ *	@tc_verd: traffic control verdict
+ *	@ndisc_nodetype: router type (from link layer)
+ *	@dma_cookie: a cookie to one of several possible DMA operations
+ *		done by skb DMA functions
+ *	@secmark: security marking
+ *	@vlan_tci: vlan tag control information
+ */
+
+struct sk_buff {
+	/* These two members must be first. */
+	struct sk_buff		*next;
+	struct sk_buff		*prev;
+
+	ktime_t			tstamp;
+
+	struct sock		*sk;
+	//struct net_device	*dev;
+	struct ifnet *dev;
+
+	/*
+	 * This is the control buffer. It is free to use for every
+	 * layer. Please put your private variables there. If you
+	 * want to keep them across layers you have to do a skb_clone()
+	 * first. This is owned by whoever has the skb queued ATM.
+	 */
+	char			cb[48] __aligned(8);
+
+	unsigned long		_skb_refdst;
+#ifdef CONFIG_XFRM
+	struct	sec_path	*sp;
+#endif
+	unsigned int		len,
+				data_len;
+	u16			mac_len,
+				hdr_len;
+	union {
+		u32		csum;
+		struct {
+			u16	csum_start;
+			u16	csum_offset;
+		}smbol2;
+	}smbol1;
+	u32			priority;
+	kmemcheck_bitfield_begin(flags1);
+	u8			local_df:1,
+				cloned:1,
+				ip_summed:2,
+				nohdr:1,
+				nfctinfo:3;
+	u8			pkt_type:3,
+				fclone:2,
+				ipvs_property:1,
+				peeked:1,
+				nf_trace:1;
+	kmemcheck_bitfield_end(flags1);
+	u16			protocol;
+
+	void			(*destructor)(struct sk_buff *skb);
+#if defined(CONFIG_NF_CONNTRACK) || defined(CONFIG_NF_CONNTRACK_MODULE)
+	struct nf_conntrack	*nfct;
+	struct sk_buff		*nfct_reasm;
+#endif
+#ifdef CONFIG_BRIDGE_NETFILTER
+	struct nf_bridge_info	*nf_bridge;
+#endif
+
+	int			skb_iif;
+#ifdef CONFIG_NET_SCHED
+	u16			tc_index;	/* traffic control index */
+#ifdef CONFIG_NET_CLS_ACT
+	u16			tc_verd;	/* traffic control verdict */
+#endif
+#endif
+
+	u32			rxhash;
+
+	kmemcheck_bitfield_begin(flags2);
+	u16			queue_mapping:16;
+#ifdef CONFIG_IPV6_NDISC_NODETYPE
+	u8			ndisc_nodetype:2,
+				deliver_no_wcard:1;
+#else
+	u8			deliver_no_wcard:1;
+#endif
+	kmemcheck_bitfield_end(flags2);
+
+	/* 0/14 bit hole */
+
+#ifdef CONFIG_NET_DMA
+	dma_cookie_t		dma_cookie;
+#endif
+#ifdef CONFIG_NETWORK_SECMARK
+	u32			secmark;
+#endif
+	union {
+		u32		mark;
+		u32		dropcount;
+	}symbol3;
+
+	u16			vlan_tci;
+
+	sk_buff_data_t		transport_header;
+	sk_buff_data_t		network_header;
+	sk_buff_data_t		mac_header;
+	/* These elements must be at the end, see alloc_skb() for details.  */
+	sk_buff_data_t		tail;
+	sk_buff_data_t		end;
+	unsigned char		*head,
+				*data;
+	unsigned int		truesize;
+	atomic_t		users;
+};
+struct sk_buff_head {
+	/* These two members must be first. */
+	struct sk_buff	*next;
+	struct sk_buff	*prev;
+
+	u32		qlen;
+	_lock	lock;
+};
+#define skb_tail_pointer(skb)	skb->tail
+static inline unsigned char *skb_put(struct sk_buff *skb, unsigned int len)
+{
+	unsigned char *tmp = skb_tail_pointer(skb);
+	//SKB_LINEAR_ASSERT(skb);
+	skb->tail += len;
+	skb->len  += len;
+	return tmp;
+}
+
+static inline unsigned char *__skb_pull(struct sk_buff *skb, unsigned int len)
+{
+	skb->len -= len;
+	if(skb->len < skb->data_len)
+		printf("%s(),%d,error!\n",__FUNCTION__,__LINE__);
+	return skb->data += len;
+}
+static inline unsigned char *skb_pull(struct sk_buff *skb, unsigned int len)
+{
+	#ifdef PLATFORM_FREEBSD
+	return __skb_pull(skb, len);
+	#else
+	return unlikely(len > skb->len) ? NULL : __skb_pull(skb, len);
+	#endif //PLATFORM_FREEBSD
+}
+static inline u32 skb_queue_len(const struct sk_buff_head *list_)
+{
+	return list_->qlen;
+}
+static inline void __skb_insert(struct sk_buff *newsk,
+				struct sk_buff *prev, struct sk_buff *next,
+				struct sk_buff_head *list)
+{
+	newsk->next = next;
+	newsk->prev = prev;
+	next->prev  = prev->next = newsk;
+	list->qlen++;
+}
+static inline void __skb_queue_before(struct sk_buff_head *list,
+				      struct sk_buff *next,
+				      struct sk_buff *newsk)
+{
+	__skb_insert(newsk, next->prev, next, list);
+}
+static inline void skb_queue_tail(struct sk_buff_head *list,
+				   struct sk_buff *newsk)
+{
+	mtx_lock(&list->lock);
+	__skb_queue_before(list, (struct sk_buff *)list, newsk);
+	mtx_unlock(&list->lock);
+}
+static inline struct sk_buff *skb_peek(struct sk_buff_head *list_)
+{
+	struct sk_buff *list = ((struct sk_buff *)list_)->next;
+	if (list == (struct sk_buff *)list_)
+		list = NULL;
+	return list;
+}
+static inline void __skb_unlink(struct sk_buff *skb, struct sk_buff_head *list)
+{
+	struct sk_buff *next, *prev;
+
+	list->qlen--;
+	next	   = skb->next;
+	prev	   = skb->prev;
+	skb->next  = skb->prev = NULL;
+	next->prev = prev;
+	prev->next = next;
+}
+
+static inline struct sk_buff *skb_dequeue(struct sk_buff_head *list)
+{
+	mtx_lock(&list->lock);
+
+	struct sk_buff *skb = skb_peek(list);
+	if (skb)
+		__skb_unlink(skb, list);
+
+	mtx_unlock(&list->lock);
+
+	return skb;
+}
+static inline void skb_reserve(struct sk_buff *skb, int len)
+{
+	skb->data += len;
+	skb->tail += len;
+}
+static inline void __skb_queue_head_init(struct sk_buff_head *list)
+{
+	list->prev = list->next = (struct sk_buff *)list;
+	list->qlen = 0;
+}
+/*
+ * This function creates a split out lock class for each invocation;
+ * this is needed for now since a whole lot of users of the skb-queue
+ * infrastructure in drivers have different locking usage (in hardirq)
+ * than the networking core (in softirq only). In the long run either the
+ * network layer or drivers should need annotation to consolidate the
+ * main types of usage into 3 classes.
+ */
+static inline void skb_queue_head_init(struct sk_buff_head *list)
+{
+	_rtw_spinlock_init(&list->lock);
+	__skb_queue_head_init(list);
+}
+unsigned long copy_from_user(void *to, const void *from, unsigned long n);
+unsigned long copy_to_user(void *to, const void *from, unsigned long n);
+struct sk_buff * dev_alloc_skb(unsigned int size);
+struct sk_buff *skb_clone(const struct sk_buff *skb);
+void dev_kfree_skb_any(struct sk_buff *skb);
+#endif //Baron porting from linux, it's all temp solution, needs to check again
+
+
+#if 1 // kenny add Linux compatibility code for Linux USB driver
+#include <dev/usb/usb_compat_linux.h>
+
+#define __init		// __attribute ((constructor))
+#define __exit		// __attribute ((destructor))
+
+/*
+ * Definitions for module_init and module_exit macros.
+ *
+ * These macros will use the SYSINIT framework to call a specified
+ * function (with no arguments) on module loading or unloading.
+ * 
+ */
+
+void module_init_exit_wrapper(void *arg);
+
+#define module_init(initfn)                             \
+        SYSINIT(mod_init_ ## initfn,                    \
+                SI_SUB_KLD, SI_ORDER_FIRST,             \
+                module_init_exit_wrapper, initfn)
+
+#define module_exit(exitfn)                             \
+        SYSUNINIT(mod_exit_ ## exitfn,                  \
+                  SI_SUB_KLD, SI_ORDER_ANY,             \
+                  module_init_exit_wrapper, exitfn)
+
+/*
+ * The usb_register and usb_deregister functions are used to register
+ * usb drivers with the usb subsystem. 
+ */
+int usb_register(struct usb_driver *driver);
+int usb_deregister(struct usb_driver *driver);
+
+/*
+ * usb_get_dev and usb_put_dev - increment/decrement the reference count 
+ * of the usb device structure.
+ *
+ * Original body of usb_get_dev:
+ *
+ *       if (dev)
+ *               get_device(&dev->dev);
+ *       return dev;
+ *
+ * Reference counts are not currently used in this compatibility
+ * layer. So these functions will do nothing.
+ */
+static inline struct usb_device *
+usb_get_dev(struct usb_device *dev)
+{
+        return dev;
+}
+
+static inline void 
+usb_put_dev(struct usb_device *dev)
+{
+        return;
+}
+
+
+// rtw_usb_compat_linux
+int rtw_usb_submit_urb(struct urb *urb, uint16_t mem_flags);
+int rtw_usb_unlink_urb(struct urb *urb);
+int rtw_usb_clear_halt(struct usb_device *dev, struct usb_host_endpoint *uhe);
+int rtw_usb_control_msg(struct usb_device *dev, struct usb_host_endpoint *uhe,
+    uint8_t request, uint8_t requesttype,
+    uint16_t value, uint16_t index, void *data,
+    uint16_t size, usb_timeout_t timeout);
+int rtw_usb_set_interface(struct usb_device *dev, uint8_t iface_no, uint8_t alt_index);
+int rtw_usb_setup_endpoint(struct usb_device *dev,
+    struct usb_host_endpoint *uhe, usb_size_t bufsize);
+struct urb *rtw_usb_alloc_urb(uint16_t iso_packets, uint16_t mem_flags);
+struct usb_host_endpoint *rtw_usb_find_host_endpoint(struct usb_device *dev, uint8_t type, uint8_t ep);
+struct usb_host_interface *rtw_usb_altnum_to_altsetting(const struct usb_interface *intf, uint8_t alt_index);
+struct usb_interface *rtw_usb_ifnum_to_if(struct usb_device *dev, uint8_t iface_no);
+void *rtw_usbd_get_intfdata(struct usb_interface *intf);
+void rtw_usb_linux_register(void *arg);
+void rtw_usb_linux_deregister(void *arg);
+void rtw_usb_linux_free_device(struct usb_device *dev);
+void rtw_usb_free_urb(struct urb *urb);
+void rtw_usb_init_urb(struct urb *urb);
+void rtw_usb_kill_urb(struct urb *urb);
+void rtw_usb_set_intfdata(struct usb_interface *intf, void *data);
+void rtw_usb_fill_bulk_urb(struct urb *urb, struct usb_device *udev,
+    struct usb_host_endpoint *uhe, void *buf,
+    int length, usb_complete_t callback, void *arg);
+int rtw_usb_bulk_msg(struct usb_device *udev, struct usb_host_endpoint *uhe,
+    void *data, int len, uint16_t *pactlen, usb_timeout_t timeout);
+void *usb_get_intfdata(struct usb_interface *intf);
+int usb_linux_init_endpoints(struct usb_device *udev);
+
+
+
+typedef struct urb *  PURB;
+
+typedef unsigned gfp_t;
+#define __GFP_WAIT      ((gfp_t)0x10u)  /* Can wait and reschedule? */
+#define __GFP_HIGH      ((gfp_t)0x20u)  /* Should access emergency pools? */
+#define __GFP_IO        ((gfp_t)0x40u)  /* Can start physical IO? */
+#define __GFP_FS        ((gfp_t)0x80u)  /* Can call down to low-level FS? */
+#define __GFP_COLD      ((gfp_t)0x100u) /* Cache-cold page required */
+#define __GFP_NOWARN    ((gfp_t)0x200u) /* Suppress page allocation failure warning */
+#define __GFP_REPEAT    ((gfp_t)0x400u) /* Retry the allocation.  Might fail */
+#define __GFP_NOFAIL    ((gfp_t)0x800u) /* Retry for ever.  Cannot fail */
+#define __GFP_NORETRY   ((gfp_t)0x1000u)/* Do not retry.  Might fail */
+#define __GFP_NO_GROW   ((gfp_t)0x2000u)/* Slab internal usage */
+#define __GFP_COMP      ((gfp_t)0x4000u)/* Add compound page metadata */
+#define __GFP_ZERO      ((gfp_t)0x8000u)/* Return zeroed page on success */
+#define __GFP_NOMEMALLOC ((gfp_t)0x10000u) /* Don't use emergency reserves */
+#define __GFP_HARDWALL   ((gfp_t)0x20000u) /* Enforce hardwall cpuset memory allocs */
+
+/* This equals 0, but use constants in case they ever change */
+#define GFP_NOWAIT      (GFP_ATOMIC & ~__GFP_HIGH)
+/* GFP_ATOMIC means both !wait (__GFP_WAIT not set) and use emergency pool */
+#define GFP_ATOMIC      (__GFP_HIGH)
+#define GFP_NOIO        (__GFP_WAIT)
+#define GFP_NOFS        (__GFP_WAIT | __GFP_IO)
+#define GFP_KERNEL      (__GFP_WAIT | __GFP_IO | __GFP_FS)
+#define GFP_USER        (__GFP_WAIT | __GFP_IO | __GFP_FS | __GFP_HARDWALL)
+#define GFP_HIGHUSER    (__GFP_WAIT | __GFP_IO | __GFP_FS | __GFP_HARDWALL | \
+                         __GFP_HIGHMEM)
+
+
+#endif // kenny add Linux compatibility code for Linux USB
+
+__inline static _list *get_next(_list	*list)
+{
+	return list->next;
+}	
+
+__inline static _list	*get_list_head(_queue	*queue)
+{
+	return (&(queue->queue));
+}
+
+	
+#define LIST_CONTAINOR(ptr, type, member) \
+        ((type *)((char *)(ptr)-(SIZE_T)(&((type *)0)->member)))	
+
+        
+__inline static void _enter_critical(_lock *plock, _irqL *pirqL)
+{
+	spin_lock_irqsave(plock, *pirqL);
+}
+
+__inline static void _exit_critical(_lock *plock, _irqL *pirqL)
+{
+	spin_unlock_irqrestore(plock, *pirqL);
+}
+
+__inline static void _enter_critical_ex(_lock *plock, _irqL *pirqL)
+{
+	spin_lock_irqsave(plock, *pirqL);
+}
+
+__inline static void _exit_critical_ex(_lock *plock, _irqL *pirqL)
+{
+	spin_unlock_irqrestore(plock, *pirqL);
+}
+
+__inline static void _enter_critical_bh(_lock *plock, _irqL *pirqL)
+{
+	spin_lock_bh(plock, *pirqL);
+}
+
+__inline static void _exit_critical_bh(_lock *plock, _irqL *pirqL)
+{
+	spin_unlock_bh(plock, *pirqL);
+}
+
+__inline static void _enter_critical_mutex(_mutex *pmutex, _irqL *pirqL)
+{
+
+		mtx_lock(pmutex);
+
+}
+
+
+__inline static void _exit_critical_mutex(_mutex *pmutex, _irqL *pirqL)
+{
+
+		mtx_unlock(pmutex);
+
+}
+static inline void __list_del(struct list_head * prev, struct list_head * next)
+{
+	next->prev = prev;
+	prev->next = next;
+}
+static inline void INIT_LIST_HEAD(struct list_head *list)
+{
+	list->next = list;
+	list->prev = list;
+}
+__inline static void rtw_list_delete(_list *plist)
+{
+	__list_del(plist->prev, plist->next);
+	INIT_LIST_HEAD(plist);
+}
+
+static inline void timer_hdl(void *ctx)
+{
+	_timer *timer = (_timer *)ctx;
+
+	rtw_mtx_lock(NULL);
+	if (callout_pending(&timer->callout)) {
+		/* callout was reset */
+		rtw_mtx_unlock(NULL);
+		return;
+	}
+
+	if (!callout_active(&timer->callout)) {
+		/* callout was stopped */
+		rtw_mtx_unlock(NULL);
+		return;
+	}
+
+	callout_deactivate(&timer->callout);
+
+	timer->function(timer->arg);
+
+	rtw_mtx_unlock(NULL);
+}
+
+static inline void _init_timer(_timer *ptimer, _nic_hdl padapter, void *pfunc, void *cntx)
+{
+	ptimer->function = pfunc;
+	ptimer->arg = cntx;
+	callout_init(&ptimer->callout, CALLOUT_MPSAFE);
+}
+
+__inline static void _set_timer(_timer *ptimer,u32 delay_time)
+{	
+	if (ptimer->function && ptimer->arg) {
+		rtw_mtx_lock(NULL);
+		callout_reset(&ptimer->callout, delay_time, timer_hdl, ptimer);
+		rtw_mtx_unlock(NULL);
+	}
+}
+
+__inline static void _cancel_timer(_timer *ptimer,u8 *bcancelled)
+{
+	rtw_mtx_lock(NULL);
+	callout_drain(&ptimer->callout);
+	rtw_mtx_unlock(NULL);
+	*bcancelled = 1; /* assume an pending timer to be canceled */
+}
+
+__inline static void _init_workitem(_workitem *pwork, void *pfunc, PVOID cntx)
+{
+	printf("%s Not implement yet! \n",__FUNCTION__);
+}
+
+__inline static void _set_workitem(_workitem *pwork)
+{
+	printf("%s Not implement yet! \n",__FUNCTION__);
+//	schedule_work(pwork);
+}
+
+//
+// Global Mutex: can only be used at PASSIVE level.
+//
+
+#define ACQUIRE_GLOBAL_MUTEX(_MutexCounter)                              \
+{                                                               \
+}
+
+#define RELEASE_GLOBAL_MUTEX(_MutexCounter)                              \
+{                                                               \
+}
+
+#define ATOMIC_INIT(i)  { (i) }
+
+static __inline void thread_enter(char *name);
+
+//Atomic integer operations
+typedef uint32_t ATOMIC_T ;
+
+#define rtw_netdev_priv(netdev) (((struct ifnet *)netdev)->if_softc)
+
+#define rtw_free_netdev(netdev) if_free((netdev))
+
+#define NDEV_FMT "%s"
+#define NDEV_ARG(ndev) ""
+#define ADPT_FMT "%s"
+#define ADPT_ARG(adapter) ""
+#define FUNC_NDEV_FMT "%s"
+#define FUNC_NDEV_ARG(ndev) __func__
+#define FUNC_ADPT_FMT "%s"
+#define FUNC_ADPT_ARG(adapter) __func__
+
+#define STRUCT_PACKED
+
+#endif
+
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/include/osdep_service_ce.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/osdep_service_ce.h
--- linux-5.6.3/3rdparty/rtl8821ce/include/osdep_service_ce.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/osdep_service_ce.h	2020-04-10 16:35:06.848661561 +0300
@@ -0,0 +1,200 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+
+#ifndef __OSDEP_CE_SERVICE_H_
+#define __OSDEP_CE_SERVICE_H_
+
+
+#include <ndis.h>
+#include <ntddndis.h>
+
+#ifdef CONFIG_SDIO_HCI
+#include "SDCardDDK.h"
+#endif
+
+#ifdef CONFIG_USB_HCI
+#include <usbdi.h>
+#endif
+
+typedef HANDLE 	_sema;
+typedef	LIST_ENTRY	_list;
+typedef NDIS_STATUS _OS_STATUS;
+
+typedef NDIS_SPIN_LOCK	_lock;
+
+typedef HANDLE 		_rwlock; //Mutex
+
+typedef u32	_irqL;
+
+typedef NDIS_HANDLE  _nic_hdl;
+
+struct rtw_timer_list {
+	NDIS_MINIPORT_TIMER ndis_timer;
+	void (*function)(void *);
+	void *arg;
+};
+
+struct	__queue	{
+	LIST_ENTRY	queue;
+	_lock	lock;
+};
+
+typedef	NDIS_PACKET	_pkt;
+typedef NDIS_BUFFER	_buffer;
+typedef struct	__queue	_queue;
+
+typedef HANDLE 	_thread_hdl_;
+typedef DWORD thread_return;
+typedef void*	thread_context;
+typedef NDIS_WORK_ITEM _workitem;
+
+
+
+#define SEMA_UPBND	(0x7FFFFFFF)   //8192
+
+__inline static _list *get_prev(_list	*list)
+{
+	return list->Blink;
+}
+	
+__inline static _list *get_next(_list	*list)
+{
+	return list->Flink;
+}
+
+__inline static _list	*get_list_head(_queue	*queue)
+{
+	return (&(queue->queue));
+}
+
+#define LIST_CONTAINOR(ptr, type, member) CONTAINING_RECORD(ptr, type, member)
+
+__inline static void _enter_critical(_lock *plock, _irqL *pirqL)
+{
+	NdisAcquireSpinLock(plock);
+}
+
+__inline static void _exit_critical(_lock *plock, _irqL *pirqL)
+{
+	NdisReleaseSpinLock(plock);
+}
+
+__inline static _enter_critical_ex(_lock *plock, _irqL *pirqL)
+{
+	NdisDprAcquireSpinLock(plock);	
+}
+
+__inline static _exit_critical_ex(_lock *plock, _irqL *pirqL)
+{
+	NdisDprReleaseSpinLock(plock);	
+}
+
+
+__inline static void _enter_hwio_critical(_rwlock *prwlock, _irqL *pirqL)
+{
+	WaitForSingleObject(*prwlock, INFINITE );
+
+}
+
+__inline static void _exit_hwio_critical(_rwlock *prwlock, _irqL *pirqL)
+{
+	ReleaseMutex(*prwlock);
+}
+
+__inline static void rtw_list_delete(_list *plist)
+{
+	RemoveEntryList(plist);
+	InitializeListHead(plist);
+}
+
+static inline void timer_hdl(
+	IN PVOID SystemSpecific1,
+	IN PVOID FunctionContext,
+	IN PVOID SystemSpecific2,
+	IN PVOID SystemSpecific3)
+{
+	_timer *timer = (_timer *)FunctionContext;
+
+	timer->function(timer->arg);
+}
+
+static inline void _init_timer(_timer *ptimer, _nic_hdl nic_hdl, void *pfunc, void *cntx)
+{
+	ptimer->function = pfunc;
+	ptimer->arg = cntx;
+	NdisMInitializeTimer(&ptimer->ndis_timer, nic_hdl, timer_hdl, ptimer);
+}
+
+static inline void _set_timer(_timer *ptimer, u32 delay_time)
+{
+	NdisMSetTimer(ptimer, delay_time);
+}
+
+static inline void _cancel_timer(_timer *ptimer, u8 *bcancelled)
+{
+	NdisMCancelTimer(ptimer, bcancelled);
+}
+
+__inline static void _init_workitem(_workitem *pwork, void *pfunc, PVOID cntx)
+{
+
+	NdisInitializeWorkItem(pwork, pfunc, cntx);
+}
+
+__inline static void _set_workitem(_workitem *pwork)
+{
+	NdisScheduleWorkItem(pwork);
+}
+
+#define ATOMIC_INIT(i)  { (i) }
+
+//
+// Global Mutex: can only be used at PASSIVE level.
+//
+
+#define ACQUIRE_GLOBAL_MUTEX(_MutexCounter)                              \
+{                                                               \
+    while (NdisInterlockedIncrement((PULONG)&(_MutexCounter)) != 1)\
+    {                                                           \
+        NdisInterlockedDecrement((PULONG)&(_MutexCounter));        \
+        NdisMSleep(10000);                          \
+    }                                                           \
+}
+
+#define RELEASE_GLOBAL_MUTEX(_MutexCounter)                              \
+{                                                               \
+    NdisInterlockedDecrement((PULONG)&(_MutexCounter));              \
+}
+
+// limitation of path length
+#define PATH_LENGTH_MAX MAX_PATH
+
+//Atomic integer operations
+#define ATOMIC_T LONG
+
+#define NDEV_FMT "%s"
+#define NDEV_ARG(ndev) ""
+#define ADPT_FMT "%s"
+#define ADPT_ARG(adapter) ""
+#define FUNC_NDEV_FMT "%s"
+#define FUNC_NDEV_ARG(ndev) __func__
+#define FUNC_ADPT_FMT "%s"
+#define FUNC_ADPT_ARG(adapter) __func__
+
+#define STRUCT_PACKED
+
+
+#endif
+
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/include/osdep_service.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/osdep_service.h
--- linux-5.6.3/3rdparty/rtl8821ce/include/osdep_service.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/osdep_service.h	2020-04-10 16:35:06.848661561 +0300
@@ -0,0 +1,794 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#ifndef __OSDEP_SERVICE_H_
+#define __OSDEP_SERVICE_H_
+
+
+#define _FAIL					0
+#define _SUCCESS				1
+#define RTW_RX_HANDLED			2
+#define RTW_RFRAME_UNAVAIL		3
+#define RTW_RFRAME_PKT_UNAVAIL	4
+#define RTW_RBUF_UNAVAIL		5
+#define RTW_RBUF_PKT_UNAVAIL	6
+#define RTW_SDIO_READ_PORT_FAIL	7
+#define RTW_ALREADY				8
+#define RTW_RA_RESOLVING		9
+#define RTW_BMC_NO_NEED			10
+
+/* #define RTW_STATUS_TIMEDOUT -110 */
+
+#undef _TRUE
+#define _TRUE		1
+
+#undef _FALSE
+#define _FALSE		0
+
+
+#ifdef PLATFORM_FREEBSD
+	#include <osdep_service_bsd.h>
+#endif
+
+#ifdef PLATFORM_LINUX
+	#include <linux/version.h>
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 11, 0))
+	#include <linux/sched/signal.h>
+	#include <linux/sched/types.h>
+#endif
+	#include <osdep_service_linux.h>
+#endif
+
+#ifdef PLATFORM_OS_XP
+	#include <osdep_service_xp.h>
+#endif
+
+#ifdef PLATFORM_OS_CE
+	#include <osdep_service_ce.h>
+#endif
+
+/* #include <rtw_byteorder.h> */
+
+#ifndef BIT
+	#define BIT(x)	(1 << (x))
+#endif
+
+#define BIT0	0x00000001
+#define BIT1	0x00000002
+#define BIT2	0x00000004
+#define BIT3	0x00000008
+#define BIT4	0x00000010
+#define BIT5	0x00000020
+#define BIT6	0x00000040
+#define BIT7	0x00000080
+#define BIT8	0x00000100
+#define BIT9	0x00000200
+#define BIT10	0x00000400
+#define BIT11	0x00000800
+#define BIT12	0x00001000
+#define BIT13	0x00002000
+#define BIT14	0x00004000
+#define BIT15	0x00008000
+#define BIT16	0x00010000
+#define BIT17	0x00020000
+#define BIT18	0x00040000
+#define BIT19	0x00080000
+#define BIT20	0x00100000
+#define BIT21	0x00200000
+#define BIT22	0x00400000
+#define BIT23	0x00800000
+#define BIT24	0x01000000
+#define BIT25	0x02000000
+#define BIT26	0x04000000
+#define BIT27	0x08000000
+#define BIT28	0x10000000
+#define BIT29	0x20000000
+#define BIT30	0x40000000
+#define BIT31	0x80000000
+#define BIT32	0x0100000000
+#define BIT33	0x0200000000
+#define BIT34	0x0400000000
+#define BIT35	0x0800000000
+#define BIT36	0x1000000000
+
+extern int RTW_STATUS_CODE(int error_code);
+
+#ifndef RTK_DMP_PLATFORM
+	#define CONFIG_USE_VMALLOC
+#endif
+
+/* flags used for rtw_mstat_update() */
+enum mstat_f {
+	/* type: 0x00ff */
+	MSTAT_TYPE_VIR = 0x00,
+	MSTAT_TYPE_PHY = 0x01,
+	MSTAT_TYPE_SKB = 0x02,
+	MSTAT_TYPE_USB = 0x03,
+	MSTAT_TYPE_MAX = 0x04,
+
+	/* func: 0xff00 */
+	MSTAT_FUNC_UNSPECIFIED = 0x00 << 8,
+	MSTAT_FUNC_IO = 0x01 << 8,
+	MSTAT_FUNC_TX_IO = 0x02 << 8,
+	MSTAT_FUNC_RX_IO = 0x03 << 8,
+	MSTAT_FUNC_TX = 0x04 << 8,
+	MSTAT_FUNC_RX = 0x05 << 8,
+	MSTAT_FUNC_CFG_VENDOR = 0x06 << 8,
+	MSTAT_FUNC_MAX = 0x07 << 8,
+};
+
+#define mstat_tf_idx(flags) ((flags) & 0xff)
+#define mstat_ff_idx(flags) (((flags) & 0xff00) >> 8)
+
+typedef enum mstat_status {
+	MSTAT_ALLOC_SUCCESS = 0,
+	MSTAT_ALLOC_FAIL,
+	MSTAT_FREE
+} MSTAT_STATUS;
+
+#ifdef DBG_MEM_ALLOC
+void rtw_mstat_update(const enum mstat_f flags, const MSTAT_STATUS status, u32 sz);
+void rtw_mstat_dump(void *sel);
+bool match_mstat_sniff_rules(const enum mstat_f flags, const size_t size);
+void *dbg_rtw_vmalloc(u32 sz, const enum mstat_f flags, const char *func, const int line);
+void *dbg_rtw_zvmalloc(u32 sz, const enum mstat_f flags, const char *func, const int line);
+void dbg_rtw_vmfree(void *pbuf, const enum mstat_f flags, u32 sz, const char *func, const int line);
+void *dbg_rtw_malloc(u32 sz, const enum mstat_f flags, const char *func, const int line);
+void *dbg_rtw_zmalloc(u32 sz, const enum mstat_f flags, const char *func, const int line);
+void dbg_rtw_mfree(void *pbuf, const enum mstat_f flags, u32 sz, const char *func, const int line);
+
+struct sk_buff *dbg_rtw_skb_alloc(unsigned int size, const enum mstat_f flags, const char *func, const int line);
+void dbg_rtw_skb_free(struct sk_buff *skb, const enum mstat_f flags, const char *func, const int line);
+struct sk_buff *dbg_rtw_skb_copy(const struct sk_buff *skb, const enum mstat_f flags, const char *func, const int line);
+struct sk_buff *dbg_rtw_skb_clone(struct sk_buff *skb, const enum mstat_f flags, const char *func, const int line);
+int dbg_rtw_netif_rx(_nic_hdl ndev, struct sk_buff *skb, const enum mstat_f flags, const char *func, int line);
+#ifdef CONFIG_RTW_NAPI
+int dbg_rtw_netif_receive_skb(_nic_hdl ndev, struct sk_buff *skb, const enum mstat_f flags, const char *func, int line);
+#ifdef CONFIG_RTW_GRO
+gro_result_t dbg_rtw_napi_gro_receive(struct napi_struct *napi, struct sk_buff *skb, const enum mstat_f flags, const char *func, int line);
+#endif
+#endif /* CONFIG_RTW_NAPI */
+void dbg_rtw_skb_queue_purge(struct sk_buff_head *list, enum mstat_f flags, const char *func, int line);
+#ifdef CONFIG_USB_HCI
+void *dbg_rtw_usb_buffer_alloc(struct usb_device *dev, size_t size, dma_addr_t *dma, const enum mstat_f flags, const char *func, const int line);
+void dbg_rtw_usb_buffer_free(struct usb_device *dev, size_t size, void *addr, dma_addr_t dma, const enum mstat_f flags, const char *func, const int line);
+#endif /* CONFIG_USB_HCI */
+
+#ifdef CONFIG_USE_VMALLOC
+#define rtw_vmalloc(sz)			dbg_rtw_vmalloc((sz), MSTAT_TYPE_VIR, __FUNCTION__, __LINE__)
+#define rtw_zvmalloc(sz)			dbg_rtw_zvmalloc((sz), MSTAT_TYPE_VIR, __FUNCTION__, __LINE__)
+#define rtw_vmfree(pbuf, sz)		dbg_rtw_vmfree((pbuf), (sz), MSTAT_TYPE_VIR, __FUNCTION__, __LINE__)
+#define rtw_vmalloc_f(sz, mstat_f)			dbg_rtw_vmalloc((sz), ((mstat_f) & 0xff00) | MSTAT_TYPE_VIR, __FUNCTION__, __LINE__)
+#define rtw_zvmalloc_f(sz, mstat_f)		dbg_rtw_zvmalloc((sz), ((mstat_f) & 0xff00) | MSTAT_TYPE_VIR, __FUNCTION__, __LINE__)
+#define rtw_vmfree_f(pbuf, sz, mstat_f)	dbg_rtw_vmfree((pbuf), (sz), ((mstat_f) & 0xff00) | MSTAT_TYPE_VIR, __FUNCTION__, __LINE__)
+#else /* CONFIG_USE_VMALLOC */
+#define rtw_vmalloc(sz)			dbg_rtw_malloc((sz), MSTAT_TYPE_PHY, __FUNCTION__, __LINE__)
+#define rtw_zvmalloc(sz)			dbg_rtw_zmalloc((sz), MSTAT_TYPE_PHY, __FUNCTION__, __LINE__)
+#define rtw_vmfree(pbuf, sz)		dbg_rtw_mfree((pbuf), (sz), MSTAT_TYPE_PHY, __FUNCTION__, __LINE__)
+#define rtw_vmalloc_f(sz, mstat_f)			dbg_rtw_malloc((sz), ((mstat_f) & 0xff00) | MSTAT_TYPE_PHY, __FUNCTION__, __LINE__)
+#define rtw_zvmalloc_f(sz, mstat_f)		dbg_rtw_zmalloc((sz), ((mstat_f) & 0xff00) | MSTAT_TYPE_PHY, __FUNCTION__, __LINE__)
+#define rtw_vmfree_f(pbuf, sz, mstat_f)	dbg_rtw_mfree((pbuf), (sz), ((mstat_f) & 0xff00) | MSTAT_TYPE_PHY, __FUNCTION__, __LINE__)
+#endif /* CONFIG_USE_VMALLOC */
+#define rtw_malloc(sz)			dbg_rtw_malloc((sz), MSTAT_TYPE_PHY, __FUNCTION__, __LINE__)
+#define rtw_zmalloc(sz)			dbg_rtw_zmalloc((sz), MSTAT_TYPE_PHY, __FUNCTION__, __LINE__)
+#define rtw_mfree(pbuf, sz)		dbg_rtw_mfree((pbuf), (sz), MSTAT_TYPE_PHY, __FUNCTION__, __LINE__)
+#define rtw_malloc_f(sz, mstat_f)			dbg_rtw_malloc((sz), ((mstat_f) & 0xff00) | MSTAT_TYPE_PHY, __FUNCTION__, __LINE__)
+#define rtw_zmalloc_f(sz, mstat_f)			dbg_rtw_zmalloc((sz), ((mstat_f) & 0xff00) | MSTAT_TYPE_PHY, __FUNCTION__, __LINE__)
+#define rtw_mfree_f(pbuf, sz, mstat_f)		dbg_rtw_mfree((pbuf), (sz), ((mstat_f) & 0xff00) | MSTAT_TYPE_PHY, __FUNCTION__, __LINE__)
+
+#define rtw_skb_alloc(size)	dbg_rtw_skb_alloc((size), MSTAT_TYPE_SKB, __FUNCTION__, __LINE__)
+#define rtw_skb_free(skb)	dbg_rtw_skb_free((skb), MSTAT_TYPE_SKB, __FUNCTION__, __LINE__)
+#define rtw_skb_alloc_f(size, mstat_f)	dbg_rtw_skb_alloc((size), ((mstat_f) & 0xff00) | MSTAT_TYPE_SKB, __FUNCTION__, __LINE__)
+#define rtw_skb_free_f(skb, mstat_f)	dbg_rtw_skb_free((skb), ((mstat_f) & 0xff00) | MSTAT_TYPE_SKB, __FUNCTION__, __LINE__)
+#define rtw_skb_copy(skb)	dbg_rtw_skb_copy((skb), MSTAT_TYPE_SKB, __FUNCTION__, __LINE__)
+#define rtw_skb_clone(skb)	dbg_rtw_skb_clone((skb), MSTAT_TYPE_SKB, __FUNCTION__, __LINE__)
+#define rtw_skb_copy_f(skb, mstat_f)	dbg_rtw_skb_copy((skb), ((mstat_f) & 0xff00) | MSTAT_TYPE_SKB, __FUNCTION__, __LINE__)
+#define rtw_skb_clone_f(skb, mstat_f)	dbg_rtw_skb_clone((skb), ((mstat_f) & 0xff00) | MSTAT_TYPE_SKB, __FUNCTION__, __LINE__)
+#define rtw_netif_rx(ndev, skb)	dbg_rtw_netif_rx(ndev, skb, MSTAT_TYPE_SKB, __FUNCTION__, __LINE__)
+#ifdef CONFIG_RTW_NAPI
+#define rtw_netif_receive_skb(ndev, skb) dbg_rtw_netif_receive_skb(ndev, skb, MSTAT_TYPE_SKB, __FUNCTION__, __LINE__)
+#ifdef CONFIG_RTW_GRO
+#define rtw_napi_gro_receive(napi, skb) dbg_rtw_napi_gro_receive(napi, skb, MSTAT_TYPE_SKB, __FUNCTION__, __LINE__)
+#endif
+#endif /* CONFIG_RTW_NAPI */
+#define rtw_skb_queue_purge(sk_buff_head) dbg_rtw_skb_queue_purge(sk_buff_head, MSTAT_TYPE_SKB, __FUNCTION__, __LINE__)
+#ifdef CONFIG_USB_HCI
+#define rtw_usb_buffer_alloc(dev, size, dma)		dbg_rtw_usb_buffer_alloc((dev), (size), (dma), MSTAT_TYPE_USB, __FUNCTION__, __LINE__)
+#define rtw_usb_buffer_free(dev, size, addr, dma)	dbg_rtw_usb_buffer_free((dev), (size), (addr), (dma), MSTAT_TYPE_USB, __FUNCTION__, __LINE__)
+#define rtw_usb_buffer_alloc_f(dev, size, dma, mstat_f)			dbg_rtw_usb_buffer_alloc((dev), (size), (dma), ((mstat_f) & 0xff00) | MSTAT_TYPE_USB, __FUNCTION__, __LINE__)
+#define rtw_usb_buffer_free_f(dev, size, addr, dma, mstat_f)	dbg_rtw_usb_buffer_free((dev), (size), (addr), (dma), ((mstat_f) & 0xff00) | MSTAT_TYPE_USB, __FUNCTION__, __LINE__)
+#endif /* CONFIG_USB_HCI */
+
+#else /* DBG_MEM_ALLOC */
+#define rtw_mstat_update(flag, status, sz) do {} while (0)
+#define rtw_mstat_dump(sel) do {} while (0)
+#define match_mstat_sniff_rules(flags, size) _FALSE
+void *_rtw_vmalloc(u32 sz);
+void *_rtw_zvmalloc(u32 sz);
+void _rtw_vmfree(void *pbuf, u32 sz);
+void *_rtw_zmalloc(u32 sz);
+void *_rtw_malloc(u32 sz);
+void _rtw_mfree(void *pbuf, u32 sz);
+
+struct sk_buff *_rtw_skb_alloc(u32 sz);
+void _rtw_skb_free(struct sk_buff *skb);
+struct sk_buff *_rtw_skb_copy(const struct sk_buff *skb);
+struct sk_buff *_rtw_skb_clone(struct sk_buff *skb);
+int _rtw_netif_rx(_nic_hdl ndev, struct sk_buff *skb);
+#ifdef CONFIG_RTW_NAPI
+int _rtw_netif_receive_skb(_nic_hdl ndev, struct sk_buff *skb);
+#ifdef CONFIG_RTW_GRO
+gro_result_t _rtw_napi_gro_receive(struct napi_struct *napi, struct sk_buff *skb);
+#endif
+#endif /* CONFIG_RTW_NAPI */
+void _rtw_skb_queue_purge(struct sk_buff_head *list);
+
+#ifdef CONFIG_USB_HCI
+void *_rtw_usb_buffer_alloc(struct usb_device *dev, size_t size, dma_addr_t *dma);
+void _rtw_usb_buffer_free(struct usb_device *dev, size_t size, void *addr, dma_addr_t dma);
+#endif /* CONFIG_USB_HCI */
+
+#ifdef CONFIG_USE_VMALLOC
+#define rtw_vmalloc(sz)			_rtw_vmalloc((sz))
+#define rtw_zvmalloc(sz)			_rtw_zvmalloc((sz))
+#define rtw_vmfree(pbuf, sz)		_rtw_vmfree((pbuf), (sz))
+#define rtw_vmalloc_f(sz, mstat_f)			_rtw_vmalloc((sz))
+#define rtw_zvmalloc_f(sz, mstat_f)		_rtw_zvmalloc((sz))
+#define rtw_vmfree_f(pbuf, sz, mstat_f)	_rtw_vmfree((pbuf), (sz))
+#else /* CONFIG_USE_VMALLOC */
+#define rtw_vmalloc(sz)			_rtw_malloc((sz))
+#define rtw_zvmalloc(sz)			_rtw_zmalloc((sz))
+#define rtw_vmfree(pbuf, sz)		_rtw_mfree((pbuf), (sz))
+#define rtw_vmalloc_f(sz, mstat_f)			_rtw_malloc((sz))
+#define rtw_zvmalloc_f(sz, mstat_f)		_rtw_zmalloc((sz))
+#define rtw_vmfree_f(pbuf, sz, mstat_f)	_rtw_mfree((pbuf), (sz))
+#endif /* CONFIG_USE_VMALLOC */
+#define rtw_malloc(sz)			_rtw_malloc((sz))
+#define rtw_zmalloc(sz)			_rtw_zmalloc((sz))
+#define rtw_mfree(pbuf, sz)		_rtw_mfree((pbuf), (sz))
+#define rtw_malloc_f(sz, mstat_f)			_rtw_malloc((sz))
+#define rtw_zmalloc_f(sz, mstat_f)			_rtw_zmalloc((sz))
+#define rtw_mfree_f(pbuf, sz, mstat_f)		_rtw_mfree((pbuf), (sz))
+
+#define rtw_skb_alloc(size) _rtw_skb_alloc((size))
+#define rtw_skb_free(skb) _rtw_skb_free((skb))
+#define rtw_skb_alloc_f(size, mstat_f)	_rtw_skb_alloc((size))
+#define rtw_skb_free_f(skb, mstat_f)	_rtw_skb_free((skb))
+#define rtw_skb_copy(skb)	_rtw_skb_copy((skb))
+#define rtw_skb_clone(skb)	_rtw_skb_clone((skb))
+#define rtw_skb_copy_f(skb, mstat_f)	_rtw_skb_copy((skb))
+#define rtw_skb_clone_f(skb, mstat_f)	_rtw_skb_clone((skb))
+#define rtw_netif_rx(ndev, skb) _rtw_netif_rx(ndev, skb)
+#ifdef CONFIG_RTW_NAPI
+#define rtw_netif_receive_skb(ndev, skb) _rtw_netif_receive_skb(ndev, skb)
+#ifdef CONFIG_RTW_GRO
+#define rtw_napi_gro_receive(napi, skb) _rtw_napi_gro_receive(napi, skb)
+#endif
+#endif /* CONFIG_RTW_NAPI */
+#define rtw_skb_queue_purge(sk_buff_head) _rtw_skb_queue_purge(sk_buff_head)
+#ifdef CONFIG_USB_HCI
+#define rtw_usb_buffer_alloc(dev, size, dma) _rtw_usb_buffer_alloc((dev), (size), (dma))
+#define rtw_usb_buffer_free(dev, size, addr, dma) _rtw_usb_buffer_free((dev), (size), (addr), (dma))
+#define rtw_usb_buffer_alloc_f(dev, size, dma, mstat_f) _rtw_usb_buffer_alloc((dev), (size), (dma))
+#define rtw_usb_buffer_free_f(dev, size, addr, dma, mstat_f) _rtw_usb_buffer_free((dev), (size), (addr), (dma))
+#endif /* CONFIG_USB_HCI */
+#endif /* DBG_MEM_ALLOC */
+
+extern void	*rtw_malloc2d(int h, int w, size_t size);
+extern void	rtw_mfree2d(void *pbuf, int h, int w, int size);
+
+void rtw_os_pkt_free(_pkt *pkt);
+_pkt *rtw_os_pkt_copy(_pkt *pkt);
+void *rtw_os_pkt_data(_pkt *pkt);
+u32 rtw_os_pkt_len(_pkt *pkt);
+
+extern void	_rtw_memcpy(void *dec, const void *sour, u32 sz);
+extern void _rtw_memmove(void *dst, const void *src, u32 sz);
+extern int	_rtw_memcmp(const void *dst, const void *src, u32 sz);
+extern void	_rtw_memset(void *pbuf, int c, u32 sz);
+
+extern void	_rtw_init_listhead(_list *list);
+extern u32	rtw_is_list_empty(_list *phead);
+extern void	rtw_list_insert_head(_list *plist, _list *phead);
+extern void	rtw_list_insert_tail(_list *plist, _list *phead);
+void rtw_list_splice(_list *list, _list *head);
+void rtw_list_splice_init(_list *list, _list *head);
+void rtw_list_splice_tail(_list *list, _list *head);
+
+#ifndef PLATFORM_FREEBSD
+extern void	rtw_list_delete(_list *plist);
+#endif /* PLATFORM_FREEBSD */
+
+void rtw_hlist_head_init(rtw_hlist_head *h);
+void rtw_hlist_add_head(rtw_hlist_node *n, rtw_hlist_head *h);
+void rtw_hlist_del(rtw_hlist_node *n);
+void rtw_hlist_add_head_rcu(rtw_hlist_node *n, rtw_hlist_head *h);
+void rtw_hlist_del_rcu(rtw_hlist_node *n);
+
+extern void	_rtw_init_sema(_sema *sema, int init_val);
+extern void	_rtw_free_sema(_sema	*sema);
+extern void	_rtw_up_sema(_sema	*sema);
+extern u32	_rtw_down_sema(_sema *sema);
+extern void	_rtw_mutex_init(_mutex *pmutex);
+extern void	_rtw_mutex_free(_mutex *pmutex);
+#ifndef PLATFORM_FREEBSD
+extern void	_rtw_spinlock_init(_lock *plock);
+#endif /* PLATFORM_FREEBSD */
+extern void	_rtw_spinlock_free(_lock *plock);
+extern void	_rtw_spinlock(_lock	*plock);
+extern void	_rtw_spinunlock(_lock	*plock);
+extern void	_rtw_spinlock_ex(_lock	*plock);
+extern void	_rtw_spinunlock_ex(_lock	*plock);
+
+extern void	_rtw_init_queue(_queue *pqueue);
+extern void _rtw_deinit_queue(_queue *pqueue);
+extern u32	_rtw_queue_empty(_queue	*pqueue);
+extern u32	rtw_end_of_queue_search(_list *queue, _list *pelement);
+
+extern systime _rtw_get_current_time(void);
+extern u32	_rtw_systime_to_ms(systime stime);
+extern systime _rtw_ms_to_systime(u32 ms);
+extern systime _rtw_us_to_systime(u32 us);
+extern s32	_rtw_get_passing_time_ms(systime start);
+extern s32 _rtw_get_remaining_time_ms(systime end);
+extern s32	_rtw_get_time_interval_ms(systime start, systime end);
+extern bool _rtw_time_after(systime a, systime b);
+
+#ifdef DBG_SYSTIME
+#define rtw_get_current_time() ({systime __stime = _rtw_get_current_time(); __stime;})
+#define rtw_systime_to_ms(stime) ({u32 __ms = _rtw_systime_to_ms(stime); typecheck(systime, stime); __ms;})
+#define rtw_ms_to_systime(ms) ({systime __stime = _rtw_ms_to_systime(ms); __stime;})
+#define rtw_us_to_systime(us) ({systime __stime = _rtw_us_to_systime(us); __stime;})
+#define rtw_get_passing_time_ms(start) ({u32 __ms = _rtw_get_passing_time_ms(start); typecheck(systime, start); __ms;})
+#define rtw_get_remaining_time_ms(end) ({u32 __ms = _rtw_get_remaining_time_ms(end); typecheck(systime, end); __ms;})
+#define rtw_get_time_interval_ms(start, end) ({u32 __ms = _rtw_get_time_interval_ms(start, end); typecheck(systime, start); typecheck(systime, end); __ms;})
+#define rtw_time_after(a,b) ({bool __r = _rtw_time_after(a,b); typecheck(systime, a); typecheck(systime, b); __r;})
+#define rtw_time_before(a,b) ({bool __r = _rtw_time_after(b, a); typecheck(systime, a); typecheck(systime, b); __r;})
+#else
+#define rtw_get_current_time() _rtw_get_current_time()
+#define rtw_systime_to_ms(stime) _rtw_systime_to_ms(stime)
+#define rtw_ms_to_systime(ms) _rtw_ms_to_systime(ms)
+#define rtw_us_to_systime(us) _rtw_us_to_systime(us)
+#define rtw_get_passing_time_ms(start) _rtw_get_passing_time_ms(start)
+#define rtw_get_remaining_time_ms(end) _rtw_get_remaining_time_ms(end)
+#define rtw_get_time_interval_ms(start, end) _rtw_get_time_interval_ms(start, end)
+#define rtw_time_after(a,b) _rtw_time_after(a,b)
+#define rtw_time_before(a,b) _rtw_time_after(b,a)
+#endif
+
+extern void	rtw_sleep_schedulable(int ms);
+
+extern void	rtw_msleep_os(int ms);
+extern void	rtw_usleep_os(int us);
+
+extern u32	rtw_atoi(u8 *s);
+
+#ifdef DBG_DELAY_OS
+#define rtw_mdelay_os(ms) _rtw_mdelay_os((ms), __FUNCTION__, __LINE__)
+#define rtw_udelay_os(ms) _rtw_udelay_os((ms), __FUNCTION__, __LINE__)
+extern void _rtw_mdelay_os(int ms, const char *func, const int line);
+extern void _rtw_udelay_os(int us, const char *func, const int line);
+#else
+extern void	rtw_mdelay_os(int ms);
+extern void	rtw_udelay_os(int us);
+#endif
+
+extern void rtw_yield_os(void);
+
+
+extern void rtw_init_timer(_timer *ptimer, void *padapter, void *pfunc, void *ctx);
+
+
+__inline static unsigned char _cancel_timer_ex(_timer *ptimer)
+{
+	u8 bcancelled;
+
+	_cancel_timer(ptimer, &bcancelled);
+
+	return bcancelled;
+}
+
+static __inline void thread_enter(char *name)
+{
+#ifdef PLATFORM_LINUX
+	allow_signal(SIGTERM);
+#endif
+#ifdef PLATFORM_FREEBSD
+	printf("%s", "RTKTHREAD_enter");
+#endif
+}
+void thread_exit(_completion *comp);
+void _rtw_init_completion(_completion *comp);
+void _rtw_wait_for_comp_timeout(_completion *comp);
+void _rtw_wait_for_comp(_completion *comp);
+
+static inline bool rtw_thread_stop(_thread_hdl_ th)
+{
+#ifdef PLATFORM_LINUX
+	return kthread_stop(th);
+#endif
+}
+static inline void rtw_thread_wait_stop(void)
+{
+#ifdef PLATFORM_LINUX
+	#if 0
+	while (!kthread_should_stop())
+		rtw_msleep_os(10);
+	#else
+	set_current_state(TASK_INTERRUPTIBLE);
+	while (!kthread_should_stop()) {
+		schedule();
+		set_current_state(TASK_INTERRUPTIBLE);
+	}
+	__set_current_state(TASK_RUNNING);
+	#endif
+#endif
+}
+
+__inline static void flush_signals_thread(void)
+{
+#ifdef PLATFORM_LINUX
+	if (signal_pending(current))
+		flush_signals(current);
+#endif
+}
+
+__inline static _OS_STATUS res_to_status(sint res)
+{
+
+#if defined(PLATFORM_LINUX) || defined (PLATFORM_MPIXEL) || defined (PLATFORM_FREEBSD)
+	return res;
+#endif
+
+#ifdef PLATFORM_WINDOWS
+
+	if (res == _SUCCESS)
+		return NDIS_STATUS_SUCCESS;
+	else
+		return NDIS_STATUS_FAILURE;
+
+#endif
+
+}
+
+__inline static void rtw_dump_stack(void)
+{
+#ifdef PLATFORM_LINUX
+	dump_stack();
+#endif
+}
+
+#ifdef PLATFORM_LINUX
+#define rtw_warn_on(condition) WARN_ON(condition)
+#else
+#define rtw_warn_on(condition) do {} while (0)
+#endif
+
+__inline static int rtw_bug_check(void *parg1, void *parg2, void *parg3, void *parg4)
+{
+	int ret = _TRUE;
+
+#ifdef PLATFORM_WINDOWS
+	if (((uint)parg1) <= 0x7fffffff ||
+	    ((uint)parg2) <= 0x7fffffff ||
+	    ((uint)parg3) <= 0x7fffffff ||
+	    ((uint)parg4) <= 0x7fffffff) {
+		ret = _FALSE;
+		KeBugCheckEx(0x87110000, (ULONG_PTR)parg1, (ULONG_PTR)parg2, (ULONG_PTR)parg3, (ULONG_PTR)parg4);
+	}
+#endif
+
+	return ret;
+
+}
+#ifdef PLATFORM_LINUX
+#define RTW_DIV_ROUND_UP(n, d)	DIV_ROUND_UP(n, d)
+#else /* !PLATFORM_LINUX */
+#define RTW_DIV_ROUND_UP(n, d)	(((n) + (d - 1)) / d)
+#endif /* !PLATFORM_LINUX */
+
+#define _RND(sz, r) ((((sz)+((r)-1))/(r))*(r))
+#define RND4(x)	(((x >> 2) + (((x & 3) == 0) ? 0 : 1)) << 2)
+
+__inline static u32 _RND4(u32 sz)
+{
+
+	u32	val;
+
+	val = ((sz >> 2) + ((sz & 3) ? 1 : 0)) << 2;
+
+	return val;
+
+}
+
+__inline static u32 _RND8(u32 sz)
+{
+
+	u32	val;
+
+	val = ((sz >> 3) + ((sz & 7) ? 1 : 0)) << 3;
+
+	return val;
+
+}
+
+__inline static u32 _RND128(u32 sz)
+{
+
+	u32	val;
+
+	val = ((sz >> 7) + ((sz & 127) ? 1 : 0)) << 7;
+
+	return val;
+
+}
+
+__inline static u32 _RND256(u32 sz)
+{
+
+	u32	val;
+
+	val = ((sz >> 8) + ((sz & 255) ? 1 : 0)) << 8;
+
+	return val;
+
+}
+
+__inline static u32 _RND512(u32 sz)
+{
+
+	u32	val;
+
+	val = ((sz >> 9) + ((sz & 511) ? 1 : 0)) << 9;
+
+	return val;
+
+}
+
+__inline static u32 bitshift(u32 bitmask)
+{
+	u32 i;
+
+	for (i = 0; i <= 31; i++)
+		if (((bitmask >> i) &  0x1) == 1)
+			break;
+
+	return i;
+}
+
+static inline int largest_bit(u32 bitmask)
+{
+	int i;
+
+	for (i = 31; i >= 0; i--)
+		if (bitmask & BIT(i))
+			break;
+
+	return i;
+}
+
+#define rtw_abs(a) (a < 0 ? -a : a)
+#define rtw_min(a, b) ((a > b) ? b : a)
+#define rtw_is_range_a_in_b(hi_a, lo_a, hi_b, lo_b) (((hi_a) <= (hi_b)) && ((lo_a) >= (lo_b)))
+#define rtw_is_range_overlap(hi_a, lo_a, hi_b, lo_b) (((hi_a) > (lo_b)) && ((lo_a) < (hi_b)))
+
+#ifndef MAC_FMT
+#define MAC_FMT "%02x:%02x:%02x:%02x:%02x:%02x"
+#endif
+#ifndef MAC_ARG
+#define MAC_ARG(x) ((u8 *)(x))[0], ((u8 *)(x))[1], ((u8 *)(x))[2], ((u8 *)(x))[3], ((u8 *)(x))[4], ((u8 *)(x))[5]
+#endif
+
+bool rtw_macaddr_is_larger(const u8 *a, const u8 *b);
+
+extern void rtw_suspend_lock_init(void);
+extern void rtw_suspend_lock_uninit(void);
+extern void rtw_lock_suspend(void);
+extern void rtw_unlock_suspend(void);
+extern void rtw_lock_suspend_timeout(u32 timeout_ms);
+extern void rtw_lock_traffic_suspend_timeout(u32 timeout_ms);
+extern void rtw_resume_lock_suspend(void);
+extern void rtw_resume_unlock_suspend(void);
+#ifdef CONFIG_AP_WOWLAN
+extern void rtw_softap_lock_suspend(void);
+extern void rtw_softap_unlock_suspend(void);
+#endif
+
+extern void rtw_set_bit(int nr, unsigned long *addr);
+extern void rtw_clear_bit(int nr, unsigned long *addr);
+extern int rtw_test_and_clear_bit(int nr, unsigned long *addr);
+
+extern void ATOMIC_SET(ATOMIC_T *v, int i);
+extern int ATOMIC_READ(ATOMIC_T *v);
+extern void ATOMIC_ADD(ATOMIC_T *v, int i);
+extern void ATOMIC_SUB(ATOMIC_T *v, int i);
+extern void ATOMIC_INC(ATOMIC_T *v);
+extern void ATOMIC_DEC(ATOMIC_T *v);
+extern int ATOMIC_ADD_RETURN(ATOMIC_T *v, int i);
+extern int ATOMIC_SUB_RETURN(ATOMIC_T *v, int i);
+extern int ATOMIC_INC_RETURN(ATOMIC_T *v);
+extern int ATOMIC_DEC_RETURN(ATOMIC_T *v);
+extern bool ATOMIC_INC_UNLESS(ATOMIC_T *v, int u);
+
+/* File operation APIs, just for linux now */
+extern int rtw_is_file_readable(const char *path);
+extern int rtw_is_file_readable_with_size(const char *path, u32 *sz);
+extern int rtw_retrieve_from_file(const char *path, u8 *buf, u32 sz);
+extern int rtw_store_to_file(const char *path, u8 *buf, u32 sz);
+
+
+#ifndef PLATFORM_FREEBSD
+extern void rtw_free_netdev(struct net_device *netdev);
+#endif /* PLATFORM_FREEBSD */
+
+
+extern u64 rtw_modular64(u64 x, u64 y);
+extern u64 rtw_division64(u64 x, u64 y);
+extern u32 rtw_random32(void);
+
+/* Macros for handling unaligned memory accesses */
+
+#define RTW_GET_BE16(a) ((u16) (((a)[0] << 8) | (a)[1]))
+#define RTW_PUT_BE16(a, val)			\
+	do {					\
+		(a)[0] = ((u16) (val)) >> 8;	\
+		(a)[1] = ((u16) (val)) & 0xff;	\
+	} while (0)
+
+#define RTW_GET_LE16(a) ((u16) (((a)[1] << 8) | (a)[0]))
+#define RTW_PUT_LE16(a, val)			\
+	do {					\
+		(a)[1] = ((u16) (val)) >> 8;	\
+		(a)[0] = ((u16) (val)) & 0xff;	\
+	} while (0)
+
+#define RTW_GET_BE24(a) ((((u32) (a)[0]) << 16) | (((u32) (a)[1]) << 8) | \
+			 ((u32) (a)[2]))
+#define RTW_PUT_BE24(a, val)					\
+	do {							\
+		(a)[0] = (u8) ((((u32) (val)) >> 16) & 0xff);	\
+		(a)[1] = (u8) ((((u32) (val)) >> 8) & 0xff);	\
+		(a)[2] = (u8) (((u32) (val)) & 0xff);		\
+	} while (0)
+
+#define RTW_GET_BE32(a) ((((u32) (a)[0]) << 24) | (((u32) (a)[1]) << 16) | \
+			 (((u32) (a)[2]) << 8) | ((u32) (a)[3]))
+#define RTW_PUT_BE32(a, val)					\
+	do {							\
+		(a)[0] = (u8) ((((u32) (val)) >> 24) & 0xff);	\
+		(a)[1] = (u8) ((((u32) (val)) >> 16) & 0xff);	\
+		(a)[2] = (u8) ((((u32) (val)) >> 8) & 0xff);	\
+		(a)[3] = (u8) (((u32) (val)) & 0xff);		\
+	} while (0)
+
+#define RTW_GET_LE32(a) ((((u32) (a)[3]) << 24) | (((u32) (a)[2]) << 16) | \
+			 (((u32) (a)[1]) << 8) | ((u32) (a)[0]))
+#define RTW_PUT_LE32(a, val)					\
+	do {							\
+		(a)[3] = (u8) ((((u32) (val)) >> 24) & 0xff);	\
+		(a)[2] = (u8) ((((u32) (val)) >> 16) & 0xff);	\
+		(a)[1] = (u8) ((((u32) (val)) >> 8) & 0xff);	\
+		(a)[0] = (u8) (((u32) (val)) & 0xff);		\
+	} while (0)
+
+#define RTW_GET_BE64(a) ((((u64) (a)[0]) << 56) | (((u64) (a)[1]) << 48) | \
+			 (((u64) (a)[2]) << 40) | (((u64) (a)[3]) << 32) | \
+			 (((u64) (a)[4]) << 24) | (((u64) (a)[5]) << 16) | \
+			 (((u64) (a)[6]) << 8) | ((u64) (a)[7]))
+#define RTW_PUT_BE64(a, val)				\
+	do {						\
+		(a)[0] = (u8) (((u64) (val)) >> 56);	\
+		(a)[1] = (u8) (((u64) (val)) >> 48);	\
+		(a)[2] = (u8) (((u64) (val)) >> 40);	\
+		(a)[3] = (u8) (((u64) (val)) >> 32);	\
+		(a)[4] = (u8) (((u64) (val)) >> 24);	\
+		(a)[5] = (u8) (((u64) (val)) >> 16);	\
+		(a)[6] = (u8) (((u64) (val)) >> 8);	\
+		(a)[7] = (u8) (((u64) (val)) & 0xff);	\
+	} while (0)
+
+#define RTW_GET_LE64(a) ((((u64) (a)[7]) << 56) | (((u64) (a)[6]) << 48) | \
+			 (((u64) (a)[5]) << 40) | (((u64) (a)[4]) << 32) | \
+			 (((u64) (a)[3]) << 24) | (((u64) (a)[2]) << 16) | \
+			 (((u64) (a)[1]) << 8) | ((u64) (a)[0]))
+#define RTW_PUT_LE64(a, val)					\
+	do {							\
+		(a)[7] = (u8) ((((u64) (val)) >> 56) & 0xff);	\
+		(a)[6] = (u8) ((((u64) (val)) >> 48) & 0xff);	\
+		(a)[5] = (u8) ((((u64) (val)) >> 40) & 0xff);	\
+		(a)[4] = (u8) ((((u64) (val)) >> 32) & 0xff);	\
+		(a)[3] = (u8) ((((u64) (val)) >> 24) & 0xff);	\
+		(a)[2] = (u8) ((((u64) (val)) >> 16) & 0xff);	\
+		(a)[1] = (u8) ((((u64) (val)) >> 8) & 0xff);	\
+		(a)[0] = (u8) (((u64) (val)) & 0xff);		\
+	} while (0)
+
+void rtw_buf_free(u8 **buf, u32 *buf_len);
+void rtw_buf_update(u8 **buf, u32 *buf_len, u8 *src, u32 src_len);
+
+struct rtw_cbuf {
+	u32 write;
+	u32 read;
+	u32 size;
+	void *bufs[0];
+};
+
+bool rtw_cbuf_full(struct rtw_cbuf *cbuf);
+bool rtw_cbuf_empty(struct rtw_cbuf *cbuf);
+bool rtw_cbuf_push(struct rtw_cbuf *cbuf, void *buf);
+void *rtw_cbuf_pop(struct rtw_cbuf *cbuf);
+struct rtw_cbuf *rtw_cbuf_alloc(u32 size);
+void rtw_cbuf_free(struct rtw_cbuf *cbuf);
+
+struct map_seg_t {
+	u16 sa;
+	u16 len;
+	u8 *c;
+};
+
+struct map_t {
+	u16 len;
+	u16 seg_num;
+	u8 init_value;
+	struct map_seg_t *segs;
+};
+
+#define MAPSEG_ARRAY_ENT(_sa, _len, _c, arg...) \
+	{ .sa = _sa, .len = _len, .c = (u8[_len]){ _c, ##arg}, }
+
+#define MAPSEG_PTR_ENT(_sa, _len, _p) \
+	{ .sa = _sa, .len = _len, .c = _p, }
+
+#define MAP_ENT(_len, _seg_num, _init_v, _seg, arg...) \
+	{ .len = _len, .seg_num = _seg_num, .init_value = _init_v, .segs = (struct map_seg_t[_seg_num]){ _seg, ##arg}, }
+
+int map_readN(const struct map_t *map, u16 offset, u16 len, u8 *buf);
+u8 map_read8(const struct map_t *map, u16 offset);
+
+struct blacklist_ent {
+	_list list;
+	u8 addr[ETH_ALEN];
+	systime exp_time;
+};
+
+int rtw_blacklist_add(_queue *blist, const u8 *addr, u32 timeout_ms);
+int rtw_blacklist_del(_queue *blist, const u8 *addr);
+int rtw_blacklist_search(_queue *blist, const u8 *addr);
+void rtw_blacklist_flush(_queue *blist);
+void dump_blacklist(void *sel, _queue *blist, const char *title);
+
+/* String handler */
+
+BOOLEAN is_null(char c);
+BOOLEAN is_all_null(char *c, int len);
+BOOLEAN is_eol(char c);
+BOOLEAN is_space(char c);
+BOOLEAN IsHexDigit(char chTmp);
+BOOLEAN is_alpha(char chTmp);
+char alpha_to_upper(char c);
+
+int hex2num_i(char c);
+int hex2byte_i(const char *hex);
+int hexstr2bin(const char *hex, u8 *buf, size_t len);
+
+/*
+ * Write formatted output to sized buffer
+ */
+#ifdef PLATFORM_LINUX
+#define rtw_sprintf(buf, size, format, arg...)	snprintf(buf, size, format, ##arg)
+#else /* !PLATFORM_LINUX */
+#error "NOT DEFINE \"rtw_sprintf\"!!"
+#endif /* !PLATFORM_LINUX */
+
+#endif
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/include/osdep_service_linux.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/osdep_service_linux.h
--- linux-5.6.3/3rdparty/rtl8821ce/include/osdep_service_linux.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/osdep_service_linux.h	2020-04-10 16:35:06.848661561 +0300
@@ -0,0 +1,539 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#ifndef __OSDEP_LINUX_SERVICE_H_
+#define __OSDEP_LINUX_SERVICE_H_
+
+#include <linux/version.h>
+#include <linux/spinlock.h>
+#include <linux/compiler.h>
+#include <linux/kernel.h>
+#include <linux/errno.h>
+#include <linux/init.h>
+#include <linux/slab.h>
+#include <linux/module.h>
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 5))
+	#include <linux/kref.h>
+#endif
+/* #include <linux/smp_lock.h> */
+#include <linux/netdevice.h>
+#include <linux/inetdevice.h>
+#include <linux/skbuff.h>
+#include <linux/circ_buf.h>
+#include <asm/uaccess.h>
+#include <asm/byteorder.h>
+#include <asm/atomic.h>
+#include <asm/io.h>
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 26))
+	#include <asm/semaphore.h>
+#else
+	#include <linux/semaphore.h>
+#endif
+#include <linux/sem.h>
+#include <linux/sched.h>
+#include <linux/etherdevice.h>
+#include <linux/wireless.h>
+#include <net/iw_handler.h>
+#include <net/addrconf.h>
+#include <linux/if_arp.h>
+#include <linux/rtnetlink.h>
+#include <linux/delay.h>
+#include <linux/interrupt.h>	/* for struct tasklet_struct */
+#include <linux/ip.h>
+#include <linux/kthread.h>
+#include <linux/list.h>
+#include <linux/vmalloc.h>
+
+#if (LINUX_VERSION_CODE <= KERNEL_VERSION(2, 5, 41))
+	#include <linux/tqueue.h>
+#endif
+
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 7, 0))
+	#include <uapi/linux/limits.h>
+#else
+	#include <linux/limits.h>
+#endif
+
+#ifdef RTK_DMP_PLATFORM
+	#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 12))
+		#include <linux/pageremap.h>
+	#endif
+	#include <asm/io.h>
+#endif
+
+#ifdef CONFIG_NET_RADIO
+	#define CONFIG_WIRELESS_EXT
+#endif
+
+/* Monitor mode */
+#include <net/ieee80211_radiotap.h>
+
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 24))
+	#include <linux/ieee80211.h>
+#endif
+
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 25) && \
+	 LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 29))
+	#define CONFIG_IEEE80211_HT_ADDT_INFO
+#endif
+
+#ifdef CONFIG_IOCTL_CFG80211
+	/*	#include <linux/ieee80211.h> */
+	#include <net/cfg80211.h>
+#endif /* CONFIG_IOCTL_CFG80211 */
+
+
+#ifdef CONFIG_HAS_EARLYSUSPEND
+	#include <linux/earlysuspend.h>
+#endif /* CONFIG_HAS_EARLYSUSPEND */
+
+#ifdef CONFIG_EFUSE_CONFIG_FILE
+	#include <linux/fs.h>
+#endif
+
+#ifdef CONFIG_USB_HCI
+	#include <linux/usb.h>
+	#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 21))
+		#include <linux/usb_ch9.h>
+	#else
+		#include <linux/usb/ch9.h>
+	#endif
+#endif
+
+#ifdef CONFIG_BT_COEXIST_SOCKET_TRX
+	#include <net/sock.h>
+	#include <net/tcp.h>
+	#include <linux/udp.h>
+	#include <linux/in.h>
+	#include <linux/netlink.h>
+#endif /* CONFIG_BT_COEXIST_SOCKET_TRX */
+
+#ifdef CONFIG_USB_HCI
+	typedef struct urb   *PURB;
+	#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 22))
+		#ifdef CONFIG_USB_SUSPEND
+			#define CONFIG_AUTOSUSPEND	1
+		#endif
+	#endif
+#endif
+
+#if defined(CONFIG_RTW_GRO) && (!defined(CONFIG_RTW_NAPI))
+
+	#error "Enable NAPI before enable GRO\n"
+
+#endif
+
+
+#if (KERNEL_VERSION(2, 6, 29) > LINUX_VERSION_CODE && defined(CONFIG_RTW_NAPI))
+
+	#undef CONFIG_RTW_NAPI
+	/*#warning "Linux Kernel version too old to support NAPI (should newer than 2.6.29)\n"*/
+
+#endif
+
+#if (KERNEL_VERSION(2, 6, 33) > LINUX_VERSION_CODE && defined(CONFIG_RTW_GRO))
+
+	#undef CONFIG_RTW_GRO
+	/*#warning "Linux Kernel version too old to support GRO(should newer than 2.6.33)\n"*/
+
+#endif
+
+typedef struct	semaphore _sema;
+typedef	spinlock_t	_lock;
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37))
+	typedef struct mutex		_mutex;
+#else
+	typedef struct semaphore	_mutex;
+#endif
+struct rtw_timer_list {
+	struct timer_list timer;
+	void (*function)(void *);
+	void *arg;
+};
+
+typedef struct rtw_timer_list _timer;
+typedef struct completion _completion;
+
+struct	__queue	{
+	struct	list_head	queue;
+	_lock	lock;
+};
+
+typedef	struct sk_buff	_pkt;
+typedef unsigned char	_buffer;
+
+typedef struct	__queue	_queue;
+typedef struct	list_head	_list;
+
+/* hlist */
+typedef struct	hlist_head	rtw_hlist_head;
+typedef struct	hlist_node	rtw_hlist_node;
+
+/* RCU */
+typedef struct rcu_head rtw_rcu_head;
+#define rtw_rcu_dereference(p) rcu_dereference((p))
+#define rtw_rcu_dereference_protected(p, c) rcu_dereference_protected(p, c)
+#define rtw_rcu_assign_pointer(p, v) rcu_assign_pointer((p), (v))
+#define rtw_rcu_read_lock() rcu_read_lock()
+#define rtw_rcu_read_unlock() rcu_read_unlock()
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 34))
+#define rtw_rcu_access_pointer(p) rcu_access_pointer(p)
+#endif
+
+/* rhashtable */
+#include "../os_dep/linux/rtw_rhashtable.h"
+
+typedef	int	_OS_STATUS;
+/* typedef u32	_irqL; */
+typedef unsigned long _irqL;
+typedef	struct	net_device *_nic_hdl;
+
+typedef void		*_thread_hdl_;
+typedef int		thread_return;
+typedef void	*thread_context;
+
+typedef void timer_hdl_return;
+typedef void *timer_hdl_context;
+
+#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 5, 41))
+	typedef struct work_struct _workitem;
+#else
+	typedef struct tq_struct _workitem;
+#endif
+
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 24))
+	#define DMA_BIT_MASK(n) (((n) == 64) ? ~0ULL : ((1ULL<<(n))-1))
+#endif
+
+typedef unsigned long systime;
+
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 22))
+/* Porting from linux kernel, for compatible with old kernel. */
+static inline unsigned char *skb_tail_pointer(const struct sk_buff *skb)
+{
+	return skb->tail;
+}
+
+static inline void skb_reset_tail_pointer(struct sk_buff *skb)
+{
+	skb->tail = skb->data;
+}
+
+static inline void skb_set_tail_pointer(struct sk_buff *skb, const int offset)
+{
+	skb->tail = skb->data + offset;
+}
+
+static inline unsigned char *skb_end_pointer(const struct sk_buff *skb)
+{
+	return skb->end;
+}
+#endif
+
+__inline static void rtw_list_delete(_list *plist)
+{
+	list_del_init(plist);
+}
+
+__inline static _list *get_next(_list	*list)
+{
+	return list->next;
+}
+
+#define LIST_CONTAINOR(ptr, type, member) \
+	((type *)((char *)(ptr)-(SIZE_T)(&((type *)0)->member)))
+
+#define rtw_list_first_entry(ptr, type, member) list_first_entry(ptr, type, member)
+
+#define rtw_hlist_for_each_entry(pos, head, member) hlist_for_each_entry(pos, head, member)
+#define rtw_hlist_for_each_safe(pos, n, head) hlist_for_each_safe(pos, n, head)
+#define rtw_hlist_entry(ptr, type, member) hlist_entry(ptr, type, member)
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 9, 0))
+#define rtw_hlist_for_each_entry_safe(pos, np, n, head, member) hlist_for_each_entry_safe(pos, n, head, member)
+#define rtw_hlist_for_each_entry_rcu(pos, node, head, member) hlist_for_each_entry_rcu(pos, head, member)
+#else
+#define rtw_hlist_for_each_entry_safe(pos, np, n, head, member) hlist_for_each_entry_safe(pos, np, n, head, member)
+#define rtw_hlist_for_each_entry_rcu(pos, node, head, member) hlist_for_each_entry_rcu(pos, node, head, member)
+#endif
+
+__inline static void _enter_critical(_lock *plock, _irqL *pirqL)
+{
+	spin_lock_irqsave(plock, *pirqL);
+}
+
+__inline static void _exit_critical(_lock *plock, _irqL *pirqL)
+{
+	spin_unlock_irqrestore(plock, *pirqL);
+}
+
+__inline static void _enter_critical_ex(_lock *plock, _irqL *pirqL)
+{
+	spin_lock_irqsave(plock, *pirqL);
+}
+
+__inline static void _exit_critical_ex(_lock *plock, _irqL *pirqL)
+{
+	spin_unlock_irqrestore(plock, *pirqL);
+}
+
+__inline static void _enter_critical_bh(_lock *plock, _irqL *pirqL)
+{
+	spin_lock_bh(plock);
+}
+
+__inline static void _exit_critical_bh(_lock *plock, _irqL *pirqL)
+{
+	spin_unlock_bh(plock);
+}
+
+__inline static void enter_critical_bh(_lock *plock)
+{
+	spin_lock_bh(plock);
+}
+
+__inline static void exit_critical_bh(_lock *plock)
+{
+	spin_unlock_bh(plock);
+}
+
+__inline static int _enter_critical_mutex(_mutex *pmutex, _irqL *pirqL)
+{
+	int ret = 0;
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37))
+	/* mutex_lock(pmutex); */
+	ret = mutex_lock_interruptible(pmutex);
+#else
+	ret = down_interruptible(pmutex);
+#endif
+	return ret;
+}
+
+
+__inline static int _enter_critical_mutex_lock(_mutex *pmutex, _irqL *pirqL)
+{
+	int ret = 0;
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37))
+	mutex_lock(pmutex);
+#else
+	down(pmutex);
+#endif
+	return ret;
+}
+
+__inline static void _exit_critical_mutex(_mutex *pmutex, _irqL *pirqL)
+{
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37))
+	mutex_unlock(pmutex);
+#else
+	up(pmutex);
+#endif
+}
+
+__inline static _list	*get_list_head(_queue	*queue)
+{
+	return &(queue->queue);
+}
+
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 14, 0))
+static inline void timer_hdl(struct timer_list *in_timer)
+#else
+static inline void timer_hdl(unsigned long cntx)
+#endif
+{
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 14, 0))
+	_timer *ptimer = from_timer(ptimer, in_timer, timer);
+#else
+	_timer *ptimer = (_timer *)cntx;
+#endif
+	ptimer->function(ptimer->arg);
+}
+
+__inline static void _init_timer(_timer *ptimer, _nic_hdl nic_hdl, void *pfunc, void *cntx)
+{
+	ptimer->function = pfunc;
+	ptimer->arg = cntx;
+
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 14, 0))
+	timer_setup(&ptimer->timer, timer_hdl, 0);
+#else
+	/* setup_timer(ptimer, pfunc,(u32)cntx);	 */
+	ptimer->timer.function = timer_hdl;
+	ptimer->timer.data = (unsigned long)ptimer;
+	init_timer(&ptimer->timer);
+#endif
+}
+
+__inline static void _set_timer(_timer *ptimer, u32 delay_time)
+{
+	mod_timer(&ptimer->timer , (jiffies + (delay_time * HZ / 1000)));
+}
+
+__inline static void _cancel_timer(_timer *ptimer, u8 *bcancelled)
+{
+	*bcancelled = del_timer_sync(&ptimer->timer) == 1 ? 1 : 0;
+}
+
+static inline void _init_workitem(_workitem *pwork, void *pfunc, void *cntx)
+{
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 20))
+	INIT_WORK(pwork, pfunc);
+#elif (LINUX_VERSION_CODE > KERNEL_VERSION(2, 5, 41))
+	INIT_WORK(pwork, pfunc, pwork);
+#else
+	INIT_TQUEUE(pwork, pfunc, pwork);
+#endif
+}
+
+__inline static void _set_workitem(_workitem *pwork)
+{
+#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 5, 41))
+	schedule_work(pwork);
+#else
+	schedule_task(pwork);
+#endif
+}
+
+__inline static void _cancel_workitem_sync(_workitem *pwork)
+{
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 22))
+	cancel_work_sync(pwork);
+#elif (LINUX_VERSION_CODE > KERNEL_VERSION(2, 5, 41))
+	flush_scheduled_work();
+#else
+	flush_scheduled_tasks();
+#endif
+}
+/*
+ * Global Mutex: can only be used at PASSIVE level.
+ *   */
+
+#define ACQUIRE_GLOBAL_MUTEX(_MutexCounter)                              \
+	{                                                               \
+		while (atomic_inc_return((atomic_t *)&(_MutexCounter)) != 1) { \
+			atomic_dec((atomic_t *)&(_MutexCounter));        \
+			msleep(10);                          \
+		}                                                           \
+	}
+
+#define RELEASE_GLOBAL_MUTEX(_MutexCounter)                              \
+	{                                                               \
+		atomic_dec((atomic_t *)&(_MutexCounter));        \
+	}
+
+static inline int rtw_netif_queue_stopped(struct net_device *pnetdev)
+{
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 35))
+	return (netif_tx_queue_stopped(netdev_get_tx_queue(pnetdev, 0)) &&
+		netif_tx_queue_stopped(netdev_get_tx_queue(pnetdev, 1)) &&
+		netif_tx_queue_stopped(netdev_get_tx_queue(pnetdev, 2)) &&
+		netif_tx_queue_stopped(netdev_get_tx_queue(pnetdev, 3)));
+#else
+	return netif_queue_stopped(pnetdev);
+#endif
+}
+
+static inline void rtw_netif_wake_queue(struct net_device *pnetdev)
+{
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 35))
+	netif_tx_wake_all_queues(pnetdev);
+#else
+	netif_wake_queue(pnetdev);
+#endif
+}
+
+static inline void rtw_netif_start_queue(struct net_device *pnetdev)
+{
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 35))
+	netif_tx_start_all_queues(pnetdev);
+#else
+	netif_start_queue(pnetdev);
+#endif
+}
+
+static inline void rtw_netif_stop_queue(struct net_device *pnetdev)
+{
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 35))
+	netif_tx_stop_all_queues(pnetdev);
+#else
+	netif_stop_queue(pnetdev);
+#endif
+}
+static inline void rtw_netif_device_attach(struct net_device *pnetdev)
+{
+	netif_device_attach(pnetdev);
+}
+static inline void rtw_netif_device_detach(struct net_device *pnetdev)
+{
+	netif_device_detach(pnetdev);
+}
+static inline void rtw_netif_carrier_on(struct net_device *pnetdev)
+{
+	netif_carrier_on(pnetdev);
+}
+static inline void rtw_netif_carrier_off(struct net_device *pnetdev)
+{
+	netif_carrier_off(pnetdev);
+}
+
+static inline int rtw_merge_string(char *dst, int dst_len, const char *src1, const char *src2)
+{
+	int	len = 0;
+	len += snprintf(dst + len, dst_len - len, "%s", src1);
+	len += snprintf(dst + len, dst_len - len, "%s", src2);
+
+	return len;
+}
+
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 27))
+	#define rtw_signal_process(pid, sig) kill_pid(find_vpid((pid)), (sig), 1)
+#else /* (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 27)) */
+	#define rtw_signal_process(pid, sig) kill_proc((pid), (sig), 1)
+#endif /* (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 27)) */
+
+
+/* Suspend lock prevent system from going suspend */
+#ifdef CONFIG_WAKELOCK
+	#include <linux/wakelock.h>
+#elif defined(CONFIG_ANDROID_POWER)
+	#include <linux/android_power.h>
+#endif
+
+/* limitation of path length */
+#define PATH_LENGTH_MAX PATH_MAX
+
+/* Atomic integer operations */
+#define ATOMIC_T atomic_t
+
+#define rtw_netdev_priv(netdev) (((struct rtw_netdev_priv_indicator *)netdev_priv(netdev))->priv)
+
+#define NDEV_FMT "%s"
+#define NDEV_ARG(ndev) ndev->name
+#define ADPT_FMT "%s"
+#define ADPT_ARG(adapter) (adapter->pnetdev ? adapter->pnetdev->name : NULL)
+#define FUNC_NDEV_FMT "%s(%s)"
+#define FUNC_NDEV_ARG(ndev) __func__, ndev->name
+#define FUNC_ADPT_FMT "%s(%s)"
+#define FUNC_ADPT_ARG(adapter) __func__, (adapter->pnetdev ? adapter->pnetdev->name : NULL)
+
+struct rtw_netdev_priv_indicator {
+	void *priv;
+	u32 sizeof_priv;
+};
+struct net_device *rtw_alloc_etherdev_with_old_priv(int sizeof_priv, void *old_priv);
+extern struct net_device *rtw_alloc_etherdev(int sizeof_priv);
+
+#define STRUCT_PACKED __attribute__ ((packed))
+
+
+#endif
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/include/osdep_service_xp.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/osdep_service_xp.h
--- linux-5.6.3/3rdparty/rtl8821ce/include/osdep_service_xp.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/osdep_service_xp.h	2020-04-10 16:35:06.848661561 +0300
@@ -0,0 +1,210 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#ifndef __OSDEP_LINUX_SERVICE_H_
+#define __OSDEP_LINUX_SERVICE_H_
+
+	#include <ndis.h>
+	#include <ntddk.h>
+	#include <ntddndis.h>
+	#include <ntdef.h>
+
+#ifdef CONFIG_USB_HCI
+	#include <usb.h>
+	#include <usbioctl.h>
+	#include <usbdlib.h>
+#endif
+
+	typedef KSEMAPHORE 	_sema;
+	typedef	LIST_ENTRY	_list;
+	typedef NDIS_STATUS _OS_STATUS;
+	
+
+	typedef NDIS_SPIN_LOCK	_lock;
+
+	typedef KMUTEX 			_mutex;
+
+	typedef KIRQL	_irqL;
+
+	// USB_PIPE for WINCE , but handle can be use just integer under windows
+	typedef NDIS_HANDLE  _nic_hdl;
+
+	struct rtw_timer_list {
+		NDIS_MINIPORT_TIMER ndis_timer;
+		void (*function)(void *);
+		void *arg;
+	};
+
+	struct	__queue	{
+		LIST_ENTRY	queue;	
+		_lock	lock;
+	};
+
+	typedef	NDIS_PACKET	_pkt;
+	typedef NDIS_BUFFER	_buffer;
+	typedef struct	__queue	_queue;
+	
+	typedef PKTHREAD _thread_hdl_;
+	typedef void	thread_return;
+	typedef void* thread_context;
+
+	typedef NDIS_WORK_ITEM _workitem;
+
+
+	#define HZ			10000000
+	#define SEMA_UPBND	(0x7FFFFFFF)   //8192
+	
+__inline static _list *get_next(_list	*list)
+{
+	return list->Flink;
+}	
+
+__inline static _list	*get_list_head(_queue	*queue)
+{
+	return (&(queue->queue));
+}
+	
+
+#define LIST_CONTAINOR(ptr, type, member) CONTAINING_RECORD(ptr, type, member)
+     
+
+__inline static _enter_critical(_lock *plock, _irqL *pirqL)
+{
+	NdisAcquireSpinLock(plock);	
+}
+
+__inline static _exit_critical(_lock *plock, _irqL *pirqL)
+{
+	NdisReleaseSpinLock(plock);	
+}
+
+
+__inline static _enter_critical_ex(_lock *plock, _irqL *pirqL)
+{
+	NdisDprAcquireSpinLock(plock);	
+}
+
+__inline static _exit_critical_ex(_lock *plock, _irqL *pirqL)
+{
+	NdisDprReleaseSpinLock(plock);	
+}
+
+__inline static void _enter_critical_bh(_lock *plock, _irqL *pirqL)
+{
+	NdisDprAcquireSpinLock(plock);
+}
+
+__inline static void _exit_critical_bh(_lock *plock, _irqL *pirqL)
+{
+	NdisDprReleaseSpinLock(plock);
+}
+
+__inline static _enter_critical_mutex(_mutex *pmutex, _irqL *pirqL)
+{
+	KeWaitForSingleObject(pmutex, Executive, KernelMode, FALSE, NULL);
+}
+
+
+__inline static _exit_critical_mutex(_mutex *pmutex, _irqL *pirqL)
+{
+	KeReleaseMutex(pmutex, FALSE);
+}
+
+
+__inline static void rtw_list_delete(_list *plist)
+{
+	RemoveEntryList(plist);
+	InitializeListHead(plist);	
+}
+
+static inline void timer_hdl(
+	IN PVOID SystemSpecific1,
+	IN PVOID FunctionContext,
+	IN PVOID SystemSpecific2,
+	IN PVOID SystemSpecific3)
+{
+	_timer *timer = (_timer *)FunctionContext;
+
+	timer->function(timer->arg);
+}
+
+static inline void _init_timer(_timer *ptimer, _nic_hdl nic_hdl, void *pfunc, void *cntx)
+{
+	ptimer->function = pfunc;
+	ptimer->arg = cntx;
+	NdisMInitializeTimer(&ptimer->ndis_timer, nic_hdl, timer_hdl, ptimer);
+}
+
+static inline void _set_timer(_timer *ptimer, u32 delay_time)
+{
+	NdisMSetTimer(ptimer, delay_time);
+}
+
+static inline void _cancel_timer(_timer *ptimer, u8 *bcancelled)
+{
+	NdisMCancelTimer(ptimer, bcancelled);
+}
+
+__inline static void _init_workitem(_workitem *pwork, void *pfunc, PVOID cntx)
+{
+
+	NdisInitializeWorkItem(pwork, pfunc, cntx);
+}
+
+__inline static void _set_workitem(_workitem *pwork)
+{
+	NdisScheduleWorkItem(pwork);
+}
+
+
+#define ATOMIC_INIT(i)  { (i) }
+
+//
+// Global Mutex: can only be used at PASSIVE level.
+//
+
+#define ACQUIRE_GLOBAL_MUTEX(_MutexCounter)                              \
+{                                                               \
+    while (NdisInterlockedIncrement((PULONG)&(_MutexCounter)) != 1)\
+    {                                                           \
+        NdisInterlockedDecrement((PULONG)&(_MutexCounter));        \
+        NdisMSleep(10000);                          \
+    }                                                           \
+}
+
+#define RELEASE_GLOBAL_MUTEX(_MutexCounter)                              \
+{                                                               \
+    NdisInterlockedDecrement((PULONG)&(_MutexCounter));              \
+}
+
+// limitation of path length
+#define PATH_LENGTH_MAX MAX_PATH
+
+//Atomic integer operations
+#define ATOMIC_T LONG
+
+
+#define NDEV_FMT "%s"
+#define NDEV_ARG(ndev) ""
+#define ADPT_FMT "%s"
+#define ADPT_ARG(adapter) ""
+#define FUNC_NDEV_FMT "%s"
+#define FUNC_NDEV_ARG(ndev) __func__
+#define FUNC_ADPT_FMT "%s"
+#define FUNC_ADPT_ARG(adapter) __func__
+
+#define STRUCT_PACKED
+
+#endif
+
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/include/pci_hal.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/pci_hal.h
--- linux-5.6.3/3rdparty/rtl8821ce/include/pci_hal.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/pci_hal.h	2020-04-10 16:35:06.848661561 +0300
@@ -0,0 +1,52 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#ifndef __PCI_HAL_H__
+#define __PCI_HAL_H__
+
+#ifdef CONFIG_RTL8188E
+	void rtl8188ee_set_hal_ops(_adapter *padapter);
+#endif
+
+#if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A)
+	void rtl8812ae_set_hal_ops(_adapter *padapter);
+#endif
+
+#if defined(CONFIG_RTL8192E)
+	void rtl8192ee_set_hal_ops(_adapter *padapter);
+#endif
+
+#if defined(CONFIG_RTL8192F)
+	void rtl8192fe_set_hal_ops(_adapter *padapter);
+#endif
+
+#ifdef CONFIG_RTL8723B
+	void rtl8723be_set_hal_ops(_adapter *padapter);
+#endif
+
+#ifdef CONFIG_RTL8723D
+	void rtl8723de_set_hal_ops(_adapter *padapter);
+#endif
+
+#ifdef CONFIG_RTL8814A
+	void rtl8814ae_set_hal_ops(_adapter *padapter);
+#endif
+
+#ifdef CONFIG_RTL8822B
+	void rtl8822be_set_hal_ops(PADAPTER padapter);
+#endif
+
+u8 rtw_set_hal_ops(_adapter *padapter);
+
+#endif /* __PCIE_HAL_H__ */
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/include/pci_ops.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/pci_ops.h
--- linux-5.6.3/3rdparty/rtl8821ce/include/pci_ops.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/pci_ops.h	2020-04-10 16:35:06.848661561 +0300
@@ -0,0 +1,102 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#ifndef __PCI_OPS_H_
+#define __PCI_OPS_H_
+
+
+#ifdef CONFIG_RTL8188E
+	u32	rtl8188ee_init_desc_ring(_adapter *padapter);
+	u32	rtl8188ee_free_desc_ring(_adapter *padapter);
+	void	rtl8188ee_reset_desc_ring(_adapter *padapter);
+	int	rtl8188ee_interrupt(PADAPTER Adapter);
+	void	rtl8188ee_xmit_tasklet(void *priv);
+	void	rtl8188ee_recv_tasklet(void *priv);
+	void	rtl8188ee_prepare_bcn_tasklet(void *priv);
+	void	rtl8188ee_set_intf_ops(struct _io_ops	*pops);
+#endif
+
+#if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A)
+	u32	rtl8812ae_init_desc_ring(_adapter *padapter);
+	u32	rtl8812ae_free_desc_ring(_adapter *padapter);
+	void	rtl8812ae_reset_desc_ring(_adapter *padapter);
+	int	rtl8812ae_interrupt(PADAPTER Adapter);
+	void	rtl8812ae_xmit_tasklet(void *priv);
+	void	rtl8812ae_recv_tasklet(void *priv);
+	void	rtl8812ae_prepare_bcn_tasklet(void *priv);
+	void	rtl8812ae_set_intf_ops(struct _io_ops	*pops);
+#endif
+
+#ifdef CONFIG_RTL8192E
+	u32	rtl8192ee_init_desc_ring(_adapter *padapter);
+	u32	rtl8192ee_free_desc_ring(_adapter *padapter);
+	void	rtl8192ee_reset_desc_ring(_adapter *padapter);
+	void	rtl8192ee_recv_tasklet(void *priv);
+	void	rtl8192ee_prepare_bcn_tasklet(void *priv);
+	int	rtl8192ee_interrupt(PADAPTER Adapter);
+	void	rtl8192ee_set_intf_ops(struct _io_ops	*pops);
+#endif
+
+#ifdef CONFIG_RTL8192F
+	u32	rtl8192fe_init_desc_ring(_adapter *padapter);
+	u32	rtl8192fe_free_desc_ring(_adapter *padapter);
+	void	rtl8192fe_reset_desc_ring(_adapter *padapter);
+	int	rtl8192fe_interrupt(PADAPTER Adapter);
+	void	rtl8192fe_recv_tasklet(void *priv);
+	void	rtl8192fe_prepare_bcn_tasklet(void *priv);
+	void	rtl8192fe_set_intf_ops(struct _io_ops	*pops);
+	u8 check_tx_desc_resource(_adapter *padapter, int prio);
+#endif
+
+#ifdef CONFIG_RTL8723B
+	u32	rtl8723be_init_desc_ring(_adapter *padapter);
+	u32	rtl8723be_free_desc_ring(_adapter *padapter);
+	void	rtl8723be_reset_desc_ring(_adapter *padapter);
+	int	rtl8723be_interrupt(PADAPTER Adapter);
+	void	rtl8723be_recv_tasklet(void *priv);
+	void	rtl8723be_prepare_bcn_tasklet(void *priv);
+	void	rtl8723be_set_intf_ops(struct _io_ops	*pops);
+#endif
+
+#ifdef CONFIG_RTL8723D
+	u32	rtl8723de_init_desc_ring(_adapter *padapter);
+	u32	rtl8723de_free_desc_ring(_adapter *padapter);
+	void	rtl8723de_reset_desc_ring(_adapter *padapter);
+	int	rtl8723de_interrupt(PADAPTER Adapter);
+	void	rtl8723de_recv_tasklet(void *priv);
+	void	rtl8723de_prepare_bcn_tasklet(void *priv);
+	void	rtl8723de_set_intf_ops(struct _io_ops	*pops);
+	u8 check_tx_desc_resource(_adapter *padapter, int prio);
+#endif
+
+#ifdef CONFIG_RTL8814A
+	u32	rtl8814ae_init_desc_ring(_adapter *padapter);
+	u32	rtl8814ae_free_desc_ring(_adapter *padapter);
+	void	rtl8814ae_reset_desc_ring(_adapter *padapter);
+	int	rtl8814ae_interrupt(PADAPTER Adapter);
+	void	rtl8814ae_xmit_tasklet(void *priv);
+	void	rtl8814ae_recv_tasklet(void *priv);
+	void	rtl8814ae_prepare_bcn_tasklet(void *priv);
+	void	rtl8814ae_set_intf_ops(struct _io_ops	*pops);
+#endif
+
+#ifdef CONFIG_RTL8822B
+	void rtl8822be_set_intf_ops(struct _io_ops *pops);
+#endif
+
+#ifdef CONFIG_RTL8821C
+	void rtl8821ce_set_intf_ops(struct _io_ops *pops);
+#endif
+
+#endif
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/include/pci_osintf.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/pci_osintf.h
--- linux-5.6.3/3rdparty/rtl8821ce/include/pci_osintf.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/pci_osintf.h	2020-04-10 16:35:06.848661561 +0300
@@ -0,0 +1,50 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#ifndef __PCI_OSINTF_H
+#define __PCI_OSINTF_H
+
+#ifdef RTK_129X_PLATFORM
+#define PCIE_SLOT1_MEM_START	0x9804F000
+#define PCIE_SLOT1_MEM_LEN	0x1000
+#define PCIE_SLOT1_CTRL_START	0x9804EC00
+
+#define PCIE_SLOT2_MEM_START	0x9803C000
+#define PCIE_SLOT2_MEM_LEN	0x1000
+#define PCIE_SLOT2_CTRL_START	0x9803BC00
+
+#define PCIE_MASK_OFFSET	0x100 /* mask offset from CTRL_START */
+#define PCIE_TRANSLATE_OFFSET	0x104 /* translate offset from CTRL_START */
+#endif
+
+#define PCI_BC_CLK_REQ		BIT0
+#define PCI_BC_ASPM_L0s		BIT1
+#define PCI_BC_ASPM_L1		BIT2
+#define PCI_BC_ASPM_L1Off	BIT3
+//#define PCI_BC_ASPM_LTR	BIT4
+//#define PCI_BC_ASPM_OBFF	BIT5
+
+void	rtw_pci_disable_aspm(_adapter *padapter);
+void	rtw_pci_enable_aspm(_adapter *padapter);
+void	PlatformClearPciPMEStatus(PADAPTER Adapter);
+void	rtw_pci_aspm_config(_adapter *padapter);
+void	rtw_pci_aspm_config_l1off_general(_adapter *padapter, u8 eanble);
+#ifdef CONFIG_PCI_DYNAMIC_ASPM
+void	rtw_pci_aspm_config_dynamic_l1_ilde_time(_adapter *padapter);
+#endif
+#ifdef CONFIG_64BIT_DMA
+	u8	PlatformEnableDMA64(PADAPTER Adapter);
+#endif
+
+#endif
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/include/recv_osdep.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/recv_osdep.h
--- linux-5.6.3/3rdparty/rtl8821ce/include/recv_osdep.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/recv_osdep.h	2020-04-10 16:35:06.848661561 +0300
@@ -0,0 +1,67 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#ifndef __RECV_OSDEP_H_
+#define __RECV_OSDEP_H_
+
+
+extern sint _rtw_init_recv_priv(struct recv_priv *precvpriv, _adapter *padapter);
+extern void _rtw_free_recv_priv(struct recv_priv *precvpriv);
+
+
+extern s32  rtw_recv_entry(union recv_frame *precv_frame);
+void rtw_rframe_set_os_pkt(union recv_frame *rframe);
+extern int rtw_recv_indicatepkt(_adapter *adapter, union recv_frame *precv_frame);
+extern void rtw_recv_returnpacket(IN _nic_hdl cnxt, IN _pkt *preturnedpkt);
+
+extern int rtw_recv_monitor(_adapter *padapter, union recv_frame *precv_frame);
+
+#ifdef CONFIG_HOSTAPD_MLME
+extern void rtw_hostapd_mlme_rx(_adapter *padapter, union recv_frame *precv_frame);
+#endif
+
+struct sta_info;
+extern void rtw_handle_tkip_mic_err(_adapter *padapter, struct sta_info *sta, u8 bgroup);
+
+
+int rtw_os_recv_resource_init(struct recv_priv *precvpriv, _adapter *padapter);
+int rtw_os_recv_resource_alloc(_adapter *padapter, union recv_frame *precvframe);
+void rtw_os_recv_resource_free(struct recv_priv *precvpriv);
+
+
+int rtw_os_alloc_recvframe(_adapter *padapter, union recv_frame *precvframe, u8 *pdata, _pkt *pskb);
+int rtw_os_recvframe_duplicate_skb(_adapter *padapter, union recv_frame *pcloneframe, _pkt *pskb);
+void rtw_os_free_recvframe(union recv_frame *precvframe);
+
+
+int rtw_os_recvbuf_resource_alloc(_adapter *padapter, struct recv_buf *precvbuf);
+int rtw_os_recvbuf_resource_free(_adapter *padapter, struct recv_buf *precvbuf);
+
+_pkt *rtw_os_alloc_msdu_pkt(union recv_frame *prframe, const u8 *da, const u8 *sa, u8 *msdu ,u16 msdu_len);
+void rtw_os_recv_indicate_pkt(_adapter *padapter, _pkt *pkt, union recv_frame *rframe);
+
+void rtw_os_read_port(_adapter *padapter, struct recv_buf *precvbuf);
+
+#ifdef PLATFORM_LINUX
+#ifdef CONFIG_RTW_NAPI
+#include <linux/netdevice.h>	/* struct napi_struct */
+
+int rtw_recv_napi_poll(struct napi_struct *, int budget);
+#ifdef CONFIG_RTW_NAPI_DYNAMIC
+void dynamic_napi_th_chk (_adapter *adapter);
+#endif /* CONFIG_RTW_NAPI_DYNAMIC */
+#endif /* CONFIG_RTW_NAPI */
+#endif /* PLATFORM_LINUX */
+
+#endif /*  */
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/include/rtl8188e_cmd.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/rtl8188e_cmd.h
--- linux-5.6.3/3rdparty/rtl8821ce/include/rtl8188e_cmd.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/rtl8188e_cmd.h	2020-04-10 16:35:06.848661561 +0300
@@ -0,0 +1,165 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#ifndef __RTL8188E_CMD_H__
+#define __RTL8188E_CMD_H__
+
+#if 0
+enum cmd_msg_element_id {
+	NONE_CMDMSG_EID,
+	AP_OFFLOAD_EID = 0,
+	SET_PWRMODE_EID = 1,
+	JOINBSS_RPT_EID = 2,
+	RSVD_PAGE_EID = 3,
+	RSSI_4_EID = 4,
+	RSSI_SETTING_EID = 5,
+	MACID_CONFIG_EID = 6,
+	MACID_PS_MODE_EID = 7,
+	P2P_PS_OFFLOAD_EID = 8,
+	SELECTIVE_SUSPEND_ROF_CMD = 9,
+	P2P_PS_CTW_CMD_EID = 32,
+	MAX_CMDMSG_EID
+};
+#else
+typedef enum _RTL8188E_H2C_CMD_ID {
+	/* Class Common */
+	H2C_COM_RSVD_PAGE			= 0x00,
+	H2C_COM_MEDIA_STATUS_RPT	= 0x01,
+	H2C_COM_SCAN					= 0x02,
+	H2C_COM_KEEP_ALIVE			= 0x03,
+	H2C_COM_DISCNT_DECISION		= 0x04,
+#ifndef CONFIG_WOWLAN
+	H2C_COM_WWLAN				= 0x05,
+#endif
+	H2C_COM_INIT_OFFLOAD			= 0x06,
+	H2C_COM_REMOTE_WAKE_CTL	= 0x07,
+	H2C_COM_AP_OFFLOAD			= 0x08,
+	H2C_COM_BCN_RSVD_PAGE		= 0x09,
+	H2C_COM_PROB_RSP_RSVD_PAGE	= 0x0A,
+
+	/* Class PS */
+	H2C_PS_PWR_MODE				= 0x20,
+	H2C_PS_TUNE_PARA				= 0x21,
+	H2C_PS_TUNE_PARA_2			= 0x22,
+	H2C_PS_LPS_PARA				= 0x23,
+	H2C_PS_P2P_OFFLOAD			= 0x24,
+
+	/* Class DM */
+	H2C_DM_MACID_CFG				= 0x40,
+	H2C_DM_TXBF					= 0x41,
+	H2C_RSSI_REPORT				= 0x42,
+	/* Class BT */
+	H2C_BT_COEX_MASK				= 0x60,
+	H2C_BT_COEX_GPIO_MODE		= 0x61,
+	H2C_BT_DAC_SWING_VAL			= 0x62,
+	H2C_BT_PSD_RST				= 0x63,
+
+	/* Class Remote WakeUp */
+#ifdef CONFIG_WOWLAN
+	H2C_COM_WWLAN				= 0x80,
+	H2C_COM_REMOTE_WAKE_CTRL	= 0x81,
+	H2C_COM_AOAC_GLOBAL_INFO	= 0x82,
+	H2C_COM_AOAC_RSVD_PAGE		= 0x83,
+#endif
+
+	/* Class */
+	/* H2C_RESET_TSF				=0xc0, */
+} RTL8188E_H2C_CMD_ID;
+
+#endif
+
+
+struct cmd_msg_parm {
+	u8 eid; /* element id */
+	u8 sz; /* sz */
+	u8 buf[6];
+};
+
+enum {
+	PWRS
+};
+
+typedef struct _SETPWRMODE_PARM {
+	u8 Mode;/* 0:Active,1:LPS,2:WMMPS */
+	/* u8 RLBM:4; */ /* 0:Min,1:Max,2: User define */
+	u8 SmartPS_RLBM;/* LPS=0:PS_Poll,1:PS_Poll,2:NullData,WMM=0:PS_Poll,1:NullData */
+	u8 AwakeInterval;	/* unit: beacon interval */
+	u8 bAllQueueUAPSD;
+	u8 PwrState;/* AllON(0x0c),RFON(0x04),RFOFF(0x00) */
+} SETPWRMODE_PARM, *PSETPWRMODE_PARM;
+
+struct H2C_SS_RFOFF_PARAM {
+	u8 ROFOn; /* 1: on, 0:off */
+	u16 gpio_period; /* unit: 1024 us */
+} __attribute__((packed));
+
+
+typedef struct JOINBSSRPT_PARM_88E {
+	u8 OpMode;	/* RT_MEDIA_STATUS */
+#ifdef CONFIG_WOWLAN
+	u8 MacID;       /* MACID */
+#endif /* CONFIG_WOWLAN */
+} JOINBSSRPT_PARM_88E, *PJOINBSSRPT_PARM_88E;
+
+#if 0
+/* move to hal_com_h2c.h */
+typedef struct _RSVDPAGE_LOC_88E {
+	u8 LocProbeRsp;
+	u8 LocPsPoll;
+	u8 LocNullData;
+	u8 LocQosNull;
+	u8 LocBTQosNull;
+#ifdef CONFIG_WOWLAN
+	u8 LocRemoteCtrlInfo;
+	u8 LocArpRsp;
+	u8 LocNbrAdv;
+	u8 LocGTKRsp;
+	u8 LocGTKInfo;
+	u8 LocProbeReq;
+	u8 LocNetList;
+#endif /* CONFIG_WOWLAN	 */
+} RSVDPAGE_LOC_88E, *PRSVDPAGE_LOC_88E;
+#endif
+
+/* host message to firmware cmd */
+void rtl8188e_set_FwPwrMode_cmd(PADAPTER padapter, u8 Mode);
+void rtl8188e_set_FwJoinBssReport_cmd(PADAPTER padapter, u8 mstatus);
+s32 FillH2CCmd_88E(PADAPTER padapter, u8 ElementID, u32 CmdLen, u8 *pCmdBuffer);
+/* u8 rtl8192c_set_FwSelectSuspend_cmd(PADAPTER padapter, u8 bfwpoll, u16 period); */
+u8 GetTxBufferRsvdPageNum8188E(_adapter *padapter, bool wowlan);
+
+
+#ifdef CONFIG_P2P
+	void rtl8188e_set_p2p_ps_offload_cmd(PADAPTER padapter, u8 p2p_ps_state);
+#endif /* CONFIG_P2P */
+
+/* #define H2C_8188E_RSVDPAGE_LOC_LEN      5 */
+/* #define H2C_8188E_AOAC_RSVDPAGE_LOC_LEN 7 */
+
+/* ---------------------------------------------------------------------------------------------------------
+ * ----------------------------------    H2C CMD CONTENT    --------------------------------------------------
+ * ---------------------------------------------------------------------------------------------------------
+ *   */
+#if 0
+	/* move to hal_com_h2c.h
+	* _RSVDPAGE_LOC_CMD_0x00 */
+	#define SET_8188E_H2CCMD_RSVDPAGE_LOC_PROBE_RSP(__pH2CCmd, __Value)     SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
+	#define SET_8188E_H2CCMD_RSVDPAGE_LOC_PSPOLL(__pH2CCmd, __Value)            SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 8, __Value)
+	#define SET_8188E_H2CCMD_RSVDPAGE_LOC_NULL_DATA(__pH2CCmd, __Value)     SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value)
+	#define SET_8188E_H2CCMD_RSVDPAGE_LOC_QOS_NULL_DATA(__pH2CCmd, __Value)     SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 8, __Value)
+	/*  AOAC_RSVDPAGE_LOC_0x83 */
+	#define SET_8188E_H2CCMD_AOAC_RSVDPAGE_LOC_REMOTE_WAKE_CTRL_INFO(__pH2CCmd, __Value)        SET_BITS_TO_LE_1BYTE((__pH2CCmd), 0, 8, __Value)
+	#define SET_8188E_H2CCMD_AOAC_RSVDPAGE_LOC_ARP_RSP(__pH2CCmd, __Value)                  SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 8, __Value)
+#endif
+#endif/* __RTL8188E_CMD_H__ */
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/include/rtl8188e_dm.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/rtl8188e_dm.h
--- linux-5.6.3/3rdparty/rtl8821ce/include/rtl8188e_dm.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/rtl8188e_dm.h	2020-04-10 16:35:06.848661561 +0300
@@ -0,0 +1,27 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#ifndef __RTL8188E_DM_H__
+#define __RTL8188E_DM_H__
+
+void rtl8188e_init_dm_priv(IN PADAPTER Adapter);
+void rtl8188e_deinit_dm_priv(IN PADAPTER Adapter);
+void rtl8188e_InitHalDm(IN PADAPTER Adapter);
+void rtl8188e_HalDmWatchDog(IN PADAPTER Adapter);
+
+/* VOID rtl8192c_dm_CheckTXPowerTracking(IN PADAPTER Adapter); */
+
+/* void rtl8192c_dm_RF_Saving(IN PADAPTER pAdapter, IN u8 bForceInNormal); */
+
+#endif
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/include/rtl8188e_hal.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/rtl8188e_hal.h
--- linux-5.6.3/3rdparty/rtl8821ce/include/rtl8188e_hal.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/rtl8188e_hal.h	2020-04-10 16:35:06.848661561 +0300
@@ -0,0 +1,316 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#ifndef __RTL8188E_HAL_H__
+#define __RTL8188E_HAL_H__
+
+/* #include "hal_com.h" */
+#include "hal_data.h"
+
+/* include HAL Related header after HAL Related compiling flags */
+#include "rtl8188e_spec.h"
+#include "Hal8188EPhyReg.h"
+#include "Hal8188EPhyCfg.h"
+#include "rtl8188e_rf.h"
+#include "rtl8188e_dm.h"
+#include "rtl8188e_recv.h"
+#include "rtl8188e_xmit.h"
+#include "rtl8188e_cmd.h"
+#include "rtl8188e_led.h"
+#include "Hal8188EPwrSeq.h"
+#ifdef DBG_CONFIG_ERROR_DETECT
+	#include "rtl8188e_sreset.h"
+#endif
+
+/* --------------------------------------------------------------------- */
+/*		RTL8188E Power Configuration CMDs for USB/SDIO/PCIE interfaces */
+/* --------------------------------------------------------------------- */
+#define Rtl8188E_NIC_PWR_ON_FLOW				rtl8188E_power_on_flow
+#define Rtl8188E_NIC_RF_OFF_FLOW				rtl8188E_radio_off_flow
+#define Rtl8188E_NIC_DISABLE_FLOW				rtl8188E_card_disable_flow
+#define Rtl8188E_NIC_ENABLE_FLOW				rtl8188E_card_enable_flow
+#define Rtl8188E_NIC_SUSPEND_FLOW				rtl8188E_suspend_flow
+#define Rtl8188E_NIC_RESUME_FLOW				rtl8188E_resume_flow
+#define Rtl8188E_NIC_PDN_FLOW					rtl8188E_hwpdn_flow
+#define Rtl8188E_NIC_LPS_ENTER_FLOW			rtl8188E_enter_lps_flow
+#define Rtl8188E_NIC_LPS_LEAVE_FLOW			rtl8188E_leave_lps_flow
+
+
+#if 1 /* download firmware related data structure */
+#define MAX_FW_8188E_SIZE			0x8000 /* 32768, 32k / 16384, 16k */
+
+#define FW_8188E_SIZE				0x4000 /* 16384, 16k */
+#define FW_8188E_SIZE_2			0x8000 /* 32768, 32k */
+
+#define FW_8188E_START_ADDRESS	0x1000
+#define FW_8188E_END_ADDRESS		0x1FFF /* 0x5FFF */
+
+
+#define IS_FW_HEADER_EXIST_88E(_pFwHdr)	((le16_to_cpu(_pFwHdr->Signature) & 0xFFF0) == 0x88E0)
+
+typedef struct _RT_FIRMWARE_8188E {
+	FIRMWARE_SOURCE	eFWSource;
+#ifdef CONFIG_EMBEDDED_FWIMG
+	u8			*szFwBuffer;
+#else
+	u8			szFwBuffer[MAX_FW_8188E_SIZE];
+#endif
+	u32			ulFwLength;
+} RT_FIRMWARE_8188E, *PRT_FIRMWARE_8188E;
+
+/*
+ * This structure must be cared byte-ordering
+ *   */
+
+typedef struct _RT_8188E_FIRMWARE_HDR {
+	/* 8-byte alinment required */
+
+	/* --- LONG WORD 0 ---- */
+	u16		Signature;	/* 92C0: test chip; 92C, 88C0: test chip; 88C1: MP A-cut; 92C1: MP A-cut */
+	u8		Category;	/* AP/NIC and USB/PCI */
+	u8		Function;	/* Reserved for different FW function indcation, for further use when driver needs to download different FW in different conditions */
+	u16		Version;		/* FW Version */
+	u8		Subversion;	/* FW Subversion, default 0x00 */
+	u16		Rsvd1;
+
+
+	/* --- LONG WORD 1 ---- */
+	u8		Month;	/* Release time Month field */
+	u8		Date;	/* Release time Date field */
+	u8		Hour;	/* Release time Hour field */
+	u8		Minute;	/* Release time Minute field */
+	u16		RamCodeSize;	/* The size of RAM code */
+	u8		Foundry;
+	u8		Rsvd2;
+
+	/* --- LONG WORD 2 ---- */
+	u32		SvnIdx;	/* The SVN entry index */
+	u32		Rsvd3;
+
+	/* --- LONG WORD 3 ---- */
+	u32		Rsvd4;
+	u32		Rsvd5;
+} RT_8188E_FIRMWARE_HDR, *PRT_8188E_FIRMWARE_HDR;
+#endif /* download firmware related data structure */
+
+
+#define DRIVER_EARLY_INT_TIME_8188E			0x05
+#define BCN_DMA_ATIME_INT_TIME_8188E		0x02
+
+
+/* #define MAX_RX_DMA_BUFFER_SIZE_88E	      0x2400 */ /* 9k for 88E nornal chip , */ /* MaxRxBuff=10k-max(TxReportSize(64*8), WOLPattern(16*24)) */
+#ifdef CONFIG_USB_HCI
+	#define RX_DMA_SIZE_88E(__Adapter) 0x2800
+#else
+	#define RX_DMA_SIZE_88E(__Adapter) ((!IS_VENDOR_8188E_I_CUT_SERIES(__Adapter))?0x2800:0x4000)
+#endif
+
+#ifdef CONFIG_WOWLAN
+	#define RESV_FMWF	(WKFMCAM_SIZE * MAX_WKFM_CAM_NUM) /* 16 entries, for each is 24 bytes*/
+#else
+	#define RESV_FMWF	0
+#endif
+
+#define RX_DMA_RESERVD_FW_FEATURE	0x200 /* for tx report (64*8) */
+
+#define MAX_RX_DMA_BUFFER_SIZE_88E(__Adapter) (RX_DMA_SIZE_88E(__Adapter)-RX_DMA_RESERVD_FW_FEATURE)
+
+#define MAX_TX_REPORT_BUFFER_SIZE			0x0400 /* 1k */
+
+#define PAGE_SIZE_TX_88E PAGE_SIZE_128
+/* Note: We will divide number of page equally for each queue other than public queue!
+ * 22k = 22528 bytes = 176 pages (@page =  128 bytes)
+ * BCN rsvd_page_num = MAX_BEACON_LEN / PAGE_SIZE_TX_88E
+ * 1 ps-poll / 1 null-data /1 prob_rsp /1 QOS null-data = 4 pages */
+
+#define BCNQ_PAGE_NUM_88E		(MAX_BEACON_LEN / PAGE_SIZE_TX_88E + 4) /*0x09*/
+
+/* For WoWLan , more reserved page */
+#ifdef CONFIG_WOWLAN
+	/* 1 ArpRsp + 2 NbrAdv + 2 NDPInfo + 1 RCI + 1 AOAC = 7 pages */
+	#define WOWLAN_PAGE_NUM_88E	0x07
+#else
+	#define WOWLAN_PAGE_NUM_88E	0x00
+#endif
+
+/* Note:
+Tx FIFO Size : previous CUT:22K /I_CUT after:32KB
+Tx page Size : 128B
+Total page numbers : 176(0xB0) / 256(0x100)
+*/
+#ifdef CONFIG_USB_HCI
+	#define TOTAL_PAGE_NUMBER_88E(_Adapter) (0xB0 - 1)
+#else
+	#define TOTAL_PAGE_NUMBER_88E(_Adapter)	((IS_VENDOR_8188E_I_CUT_SERIES(_Adapter)?0x100:0xB0) - 1)/* must reserved 1 page for dma issue */
+#endif
+#define TX_TOTAL_PAGE_NUMBER_88E(_Adapter)	(TOTAL_PAGE_NUMBER_88E(_Adapter) - BCNQ_PAGE_NUM_88E - WOWLAN_PAGE_NUM_88E)
+#define TX_PAGE_BOUNDARY_88E(_Adapter)		(TX_TOTAL_PAGE_NUMBER_88E(_Adapter) + 1) /* beacon header start address */
+
+#define WMM_NORMAL_TX_TOTAL_PAGE_NUMBER_88E(_Adapter)	TX_TOTAL_PAGE_NUMBER_88E(_Adapter)
+#define WMM_NORMAL_TX_PAGE_BOUNDARY_88E(_Adapter)		(WMM_NORMAL_TX_TOTAL_PAGE_NUMBER_88E(_Adapter) + 1)
+
+/* For Normal Chip Setting
+ * (HPQ + LPQ + NPQ + PUBQ) shall be TX_TOTAL_PAGE_NUMBER_8723B */
+#define NORMAL_PAGE_NUM_HPQ_88E		0x0
+#define NORMAL_PAGE_NUM_LPQ_88E		0x09
+#define NORMAL_PAGE_NUM_NPQ_88E		0x0
+
+/* Note: For Normal Chip Setting, modify later */
+#define WMM_NORMAL_PAGE_NUM_HPQ_88E		0x29
+#define WMM_NORMAL_PAGE_NUM_LPQ_88E		0x1C
+#define WMM_NORMAL_PAGE_NUM_NPQ_88E		0x1C
+
+
+/* -------------------------------------------------------------------------
+ *	Chip specific
+ * ------------------------------------------------------------------------- */
+#define CHIP_BONDING_IDENTIFIER(_value)	(((_value)>>22) & 0x3)
+#define CHIP_BONDING_92C_1T2R	0x1
+#define CHIP_BONDING_88C_USB_MCARD	0x2
+#define CHIP_BONDING_88C_USB_HP	0x1
+
+/* -------------------------------------------------------------------------
+ *	Channel Plan
+ * ------------------------------------------------------------------------- */
+
+
+#define EFUSE_REAL_CONTENT_LEN		512
+#define EFUSE_MAP_LEN				128
+#define EFUSE_MAX_SECTION			16
+#define EFUSE_IC_ID_OFFSET			506	/* For some inferiority IC purpose. added by Roger, 2009.09.02. */
+#define AVAILABLE_EFUSE_ADDR(addr)	(addr < EFUSE_REAL_CONTENT_LEN)
+/*
+ * <Roger_Notes>
+ * To prevent out of boundary programming case,
+ * leave 1byte and program full section
+ * 9bytes + 1byt + 5bytes and pre 1byte.
+ * For worst case:
+ * | 1byte|----8bytes----|1byte|--5bytes--|
+ * |         |            Reserved(14bytes)	      |
+ *   */
+#define EFUSE_OOB_PROTECT_BYTES 		15	/* PG data exclude header, dummy 6 bytes frome CP test and reserved 1byte. */
+
+#define		EFUSE_REAL_CONTENT_LEN_88E	256
+#define		EFUSE_MAP_LEN_88E		512
+#define		EFUSE_MAX_SECTION_88E		64
+#define		EFUSE_MAX_WORD_UNIT_88E		4
+#define		EFUSE_IC_ID_OFFSET_88E			506	/* For some inferiority IC purpose. added by Roger, 2009.09.02. */
+#define		AVAILABLE_EFUSE_ADDR_88E(addr)	(addr < EFUSE_REAL_CONTENT_LEN_88E)
+/* <Roger_Notes> To prevent out of boundary programming case, leave 1byte and program full section
+ * 9bytes + 1byt + 5bytes and pre 1byte.
+ * For worst case:
+ * | 2byte|----8bytes----|1byte|--7bytes--|  */ /* 92D */
+#define 		EFUSE_OOB_PROTECT_BYTES_88E	18	/* PG data exclude header, dummy 7 bytes frome CP test and reserved 1byte. */
+#define		EFUSE_PROTECT_BYTES_BANK_88E	16
+
+
+/* ********************************************************
+ *			EFUSE for BT definition
+ * ******************************************************** */
+#define EFUSE_BT_REAL_CONTENT_LEN		1536	/* 512*3 */
+#define EFUSE_BT_MAP_LEN				1024	/* 1k bytes */
+#define EFUSE_BT_MAX_SECTION			128		/* 1024/8 */
+
+#define EFUSE_PROTECT_BYTES_BANK		16
+
+#define INCLUDE_MULTI_FUNC_BT(_Adapter)	(GET_HAL_DATA(_Adapter)->MultiFunc & RT_MULTI_FUNC_BT)
+#define INCLUDE_MULTI_FUNC_GPS(_Adapter)	(GET_HAL_DATA(_Adapter)->MultiFunc & RT_MULTI_FUNC_GPS)
+
+/* #define IS_MULTI_FUNC_CHIP(_Adapter)	(((((PHAL_DATA_TYPE)(_Adapter->HalData))->MultiFunc) & (RT_MULTI_FUNC_BT|RT_MULTI_FUNC_GPS)) ? _TRUE : _FALSE) */
+
+/* #define RT_IS_FUNC_DISABLED(__pAdapter, __FuncBits) ( (__pAdapter)->DisabledFunctions & (__FuncBits) ) */
+
+#ifdef CONFIG_PCI_HCI
+	/* according to the define in the rtw_xmit.h, rtw_recv.h */
+	#define TX_DESC_NUM_8188EE  TXDESC_NUM   /* 128 */
+	#ifdef CONFIG_CONCURRENT_MODE
+		/*#define BE_QUEUE_TX_DESC_NUM_8188EE  (TXDESC_NUM<<1)*/		/* 256 */
+		#define BE_QUEUE_TX_DESC_NUM_8188EE  ((TXDESC_NUM<<1)+(TXDESC_NUM>>1))    /* 320 */
+		/*#define BE_QUEUE_TX_DESC_NUM_8188EE  ((TXDESC_NUM<<1)+TXDESC_NUM)*/    /* 384 */
+	#else
+		#define BE_QUEUE_TX_DESC_NUM_8188EE  TXDESC_NUM /* 128 */
+		/*#define BE_QUEUE_TX_DESC_NUM_8188EE  (TXDESC_NUM+(TXDESC_NUM>>1)) */ /* 192 */
+	#endif
+
+	void InterruptRecognized8188EE(PADAPTER Adapter, PRT_ISR_CONTENT pIsrContent);
+	void UpdateInterruptMask8188EE(PADAPTER Adapter, u32 AddMSR, u32 AddMSR1, u32 RemoveMSR, u32 RemoveMSR1);
+#endif /* CONFIG_PCI_HCI */
+
+/* rtl8188e_hal_init.c */
+
+s32 rtl8188e_FirmwareDownload(PADAPTER padapter, BOOLEAN  bUsedWoWLANFw);
+void _8051Reset88E(PADAPTER padapter);
+void rtl8188e_InitializeFirmwareVars(PADAPTER padapter);
+
+
+s32 InitLLTTable(PADAPTER padapter, u8 txpktbuf_bndy);
+
+/* EFuse */
+u8 GetEEPROMSize8188E(PADAPTER padapter);
+void Hal_InitPGData88E(PADAPTER padapter);
+void Hal_EfuseParseIDCode88E(PADAPTER padapter, u8 *hwinfo);
+void Hal_ReadTxPowerInfo88E(PADAPTER padapter, u8 *hwinfo, BOOLEAN	AutoLoadFail);
+
+void Hal_EfuseParseEEPROMVer88E(PADAPTER padapter, u8 *hwinfo, BOOLEAN AutoLoadFail);
+void rtl8188e_EfuseParseChnlPlan(PADAPTER padapter, u8 *hwinfo, BOOLEAN AutoLoadFail);
+void Hal_EfuseParseCustomerID88E(PADAPTER padapter, u8 *hwinfo, BOOLEAN AutoLoadFail);
+void Hal_ReadAntennaDiversity88E(PADAPTER pAdapter, u8 *PROMContent, BOOLEAN AutoLoadFail);
+void Hal_ReadThermalMeter_88E(PADAPTER	Adapter, u8 *PROMContent, BOOLEAN	AutoloadFail);
+void Hal_EfuseParseXtal_8188E(PADAPTER pAdapter, u8 *hwinfo, BOOLEAN AutoLoadFail);
+void Hal_EfuseParseBoardType88E(PADAPTER pAdapter, u8 *hwinfo, BOOLEAN AutoLoadFail);
+void Hal_ReadPowerSavingMode88E(PADAPTER pAdapter, u8 *hwinfo, BOOLEAN AutoLoadFail);
+void Hal_ReadPAType_8188E(PADAPTER Adapter, u8 *PROMContent, BOOLEAN AutoloadFail);
+void Hal_ReadAmplifierType_8188E(PADAPTER Adapter, u8 *PROMContent, BOOLEAN AutoloadFail);
+void Hal_ReadRFEType_8188E(PADAPTER Adapter, u8 *PROMContent, BOOLEAN AutoloadFail);
+
+BOOLEAN HalDetectPwrDownMode88E(PADAPTER Adapter);
+
+#if defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN)
+	void Hal_DetectWoWMode(PADAPTER pAdapter);
+#endif /* CONFIG_WOWLAN */
+
+
+#ifdef CONFIG_RF_POWER_TRIM
+	void Hal_ReadRFGainOffset(PADAPTER pAdapter, u8 *hwinfo, BOOLEAN AutoLoadFail);
+#endif /*CONFIG_RF_POWER_TRIM*/
+
+
+void InitBeaconParameters_8188e(_adapter *adapter);
+void SetBeaconRelatedRegisters8188E(PADAPTER padapter);
+
+void rtl8188e_set_hal_ops(struct hal_ops *pHalFunc);
+void init_hal_spec_8188e(_adapter *adapter);
+
+void rtl8188e_start_thread(_adapter *padapter);
+void rtl8188e_stop_thread(_adapter *padapter);
+
+void rtw_IOL_cmd_tx_pkt_buf_dump(ADAPTER *Adapter, int data_len);
+#ifdef CONFIG_IOL_EFUSE_PATCH
+	s32 rtl8188e_iol_efuse_patch(PADAPTER padapter);
+#endif/* CONFIG_IOL_EFUSE_PATCH */
+void _InitTransferPageSize(PADAPTER padapter);
+
+u8 SetHwReg8188E(PADAPTER padapter, u8 variable, u8 *val);
+void GetHwReg8188E(PADAPTER padapter, u8 variable, u8 *val);
+
+u8
+GetHalDefVar8188E(
+	IN	PADAPTER				Adapter,
+	IN	HAL_DEF_VARIABLE		eVariable,
+	IN	PVOID					pValue
+);
+#ifdef CONFIG_GPIO_API
+int rtl8188e_GpioFuncCheck(PADAPTER adapter, u8 gpio_num);
+#endif
+#endif /* __RTL8188E_HAL_H__ */
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/include/rtl8188e_led.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/rtl8188e_led.h
--- linux-5.6.3/3rdparty/rtl8821ce/include/rtl8188e_led.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/rtl8188e_led.h	2020-04-10 16:35:06.848661561 +0300
@@ -0,0 +1,37 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#ifndef __RTL8188E_LED_H__
+#define __RTL8188E_LED_H__
+
+#ifdef CONFIG_RTW_SW_LED
+
+/* ********************************************************************************
+ * Interface to manipulate LED objects.
+ * ******************************************************************************** */
+#ifdef CONFIG_USB_HCI
+	void rtl8188eu_InitSwLeds(PADAPTER padapter);
+	void rtl8188eu_DeInitSwLeds(PADAPTER padapter);
+#endif
+#ifdef CONFIG_PCI_HCI
+	void rtl8188ee_InitSwLeds(PADAPTER padapter);
+	void rtl8188ee_DeInitSwLeds(PADAPTER padapter);
+#endif
+#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
+	void rtl8188es_InitSwLeds(PADAPTER padapter);
+	void rtl8188es_DeInitSwLeds(PADAPTER padapter);
+#endif
+
+#endif
+#endif /*CONFIG_RTW_SW_LED*/
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/include/rtl8188e_recv.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/rtl8188e_recv.h
--- linux-5.6.3/3rdparty/rtl8821ce/include/rtl8188e_recv.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/rtl8188e_recv.h	2020-04-10 16:35:06.848661561 +0300
@@ -0,0 +1,161 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#ifndef __RTL8188E_RECV_H__
+#define __RTL8188E_RECV_H__
+
+#define RECV_BLK_SZ 512
+#define RECV_BLK_CNT 16
+#define RECV_BLK_TH RECV_BLK_CNT
+
+#if defined(CONFIG_USB_HCI)
+
+	#ifndef MAX_RECVBUF_SZ
+		#ifdef PLATFORM_OS_CE
+			#define MAX_RECVBUF_SZ (8192+1024) /* 8K+1k */
+		#else
+			#ifndef CONFIG_MINIMAL_MEMORY_USAGE
+				/* #define MAX_RECVBUF_SZ (32768) */ /* 32k */
+				/* #define MAX_RECVBUF_SZ (16384) */ /* 16K */
+				/* #define MAX_RECVBUF_SZ (10240) */ /* 10K */
+				#define MAX_RECVBUF_SZ (15360) /* 15k < 16k */
+				/* #define MAX_RECVBUF_SZ (8192+1024) */ /* 8K+1k */
+			#else
+				#define MAX_RECVBUF_SZ (4000) /* about 4K */
+			#endif
+		#endif
+	#endif /* !MAX_RECVBUF_SZ */
+
+#elif defined(CONFIG_PCI_HCI)
+	/* #ifndef CONFIG_MINIMAL_MEMORY_USAGE */
+	/*	#define MAX_RECVBUF_SZ (9100) */
+	/* #else */
+	#define MAX_RECVBUF_SZ (4000) /* about 4K
+	* #endif */
+
+
+#elif defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
+
+	#define MAX_RECVBUF_SZ (10240)
+
+#endif
+
+/* Rx smooth factor */
+#define	Rx_Smooth_Factor (20)
+
+#define TX_RPT1_PKT_LEN 8
+
+typedef struct rxreport_8188e {
+	/* Offset 0 */
+	u32 pktlen:14;
+	u32 crc32:1;
+	u32 icverr:1;
+	u32 drvinfosize:4;
+	u32 security:3;
+	u32 qos:1;
+	u32 shift:2;
+	u32 physt:1;
+	u32 swdec:1;
+	u32 ls:1;
+	u32 fs:1;
+	u32 eor:1;
+	u32 own:1;
+
+	/* Offset 4 */
+	u32 macid:5;
+	u32 tid:4;
+	u32 hwrsvd:4;
+	u32 amsdu:1;
+	u32 paggr:1;
+	u32 faggr:1;
+	u32 a1fit:4;
+	u32 a2fit:4;
+	u32 pam:1;
+	u32 pwr:1;
+	u32 md:1;
+	u32 mf:1;
+	u32 type:2;
+	u32 mc:1;
+	u32 bc:1;
+
+	/* Offset 8 */
+	u32 seq:12;
+	u32 frag:4;
+	u32 nextpktlen:14;
+	u32 nextind:1;
+	u32 rsvd0831:1;
+
+	/* Offset 12 */
+	u32 rxmcs:6;
+	u32 rxht:1;
+	u32 gf:1;
+	u32 splcp:1;
+	u32 bw:1;
+	u32 htc:1;
+	u32 eosp:1;
+	u32 bssidfit:2;
+	u32 rpt_sel:2;
+	u32 rsvd1216:13;
+	u32 pattern_match:1;
+	u32 unicastwake:1;
+	u32 magicwake:1;
+
+	/* Offset 16 */
+	/*
+	u32 pattern0match:1;
+	u32 pattern1match:1;
+	u32 pattern2match:1;
+	u32 pattern3match:1;
+	u32 pattern4match:1;
+	u32 pattern5match:1;
+	u32 pattern6match:1;
+	u32 pattern7match:1;
+	u32 pattern8match:1;
+	u32 pattern9match:1;
+	u32 patternamatch:1;
+	u32 patternbmatch:1;
+	u32 patterncmatch:1;
+	u32 rsvd1613:19;
+	*/
+	u32 rsvd16;
+
+	/* Offset 20 */
+	u32 tsfl;
+
+	/* Offset 24 */
+	u32 bassn:12;
+	u32 bavld:1;
+	u32 rsvd2413:19;
+} RXREPORT, *PRXREPORT;
+
+
+#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
+	s32 rtl8188es_init_recv_priv(PADAPTER padapter);
+	void rtl8188es_free_recv_priv(PADAPTER padapter);
+#endif
+
+#ifdef CONFIG_USB_HCI
+	void rtl8188eu_init_recvbuf(_adapter *padapter, struct recv_buf *precvbuf);
+	s32 rtl8188eu_init_recv_priv(PADAPTER padapter);
+	void rtl8188eu_free_recv_priv(PADAPTER padapter);
+#endif
+
+#ifdef CONFIG_PCI_HCI
+	s32 rtl8188ee_init_recv_priv(PADAPTER padapter);
+	void rtl8188ee_free_recv_priv(PADAPTER padapter);
+#endif
+
+void rtl8188e_query_rx_desc_status(union recv_frame *precvframe, struct recv_stat *prxstat);
+
+#endif /* __RTL8188E_RECV_H__ */
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/include/rtl8188e_rf.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/rtl8188e_rf.h
--- linux-5.6.3/3rdparty/rtl8821ce/include/rtl8188e_rf.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/rtl8188e_rf.h	2020-04-10 16:35:06.848661561 +0300
@@ -0,0 +1,27 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#ifndef __RTL8188E_RF_H__
+#define __RTL8188E_RF_H__
+
+
+
+int	PHY_RF6052_Config8188E(IN	PADAPTER		Adapter);
+void		rtl8188e_RF_ChangeTxPath(IN	PADAPTER	Adapter,
+		IN	u16		DataRate);
+void		rtl8188e_PHY_RF6052SetBandwidth(
+	IN	PADAPTER				Adapter,
+	IN	enum channel_width		Bandwidth);
+
+#endif/* __RTL8188E_RF_H__ */
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/include/rtl8188e_spec.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/rtl8188e_spec.h
--- linux-5.6.3/3rdparty/rtl8821ce/include/rtl8188e_spec.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/rtl8188e_spec.h	2020-04-10 16:35:06.848661561 +0300
@@ -0,0 +1,159 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#ifndef __RTL8188E_SPEC_H__
+#define __RTL8188E_SPEC_H__
+
+
+/* ************************************************************
+ * 8188E Regsiter offset definition
+ * ************************************************************ */
+
+
+/* ************************************************************
+ *
+ * ************************************************************ */
+
+/* -----------------------------------------------------
+ *
+ *	0x0000h ~ 0x00FFh	System Configuration
+ *
+ * ----------------------------------------------------- */
+#define REG_BB_PAD_CTRL				0x0064
+#define REG_HMEBOX_E0					0x0088
+#define REG_HMEBOX_E1					0x008A
+#define REG_HMEBOX_E2					0x008C
+#define REG_HMEBOX_E3					0x008E
+#define REG_HMEBOX_EXT_0				0x01F0
+#define REG_HMEBOX_EXT_1				0x01F4
+#define REG_HMEBOX_EXT_2				0x01F8
+#define REG_HMEBOX_EXT_3				0x01FC
+#define REG_HIMR_88E					0x00B0 /* RTL8188E */
+#define REG_HISR_88E					0x00B4 /* RTL8188E */
+#define REG_HIMRE_88E					0x00B8 /* RTL8188E */
+#define REG_HISRE_88E					0x00BC /* RTL8188E */
+
+#define	REG_DBI_WDATA_8188E				0x0348	/* DBI Write data */
+#define	REG_DBI_RDATA_8188E				0x034C	/* DBI Read data */
+#define	REG_DBI_ADDR_8188E				0x0350	/* DBI Address */
+#define	REG_DBI_FLAG_8188E				0x0352	/* DBI Read/Write Flag */
+#define	REG_MDIO_WDATA_8188E				0x0354	/* MDIO for Write PCIE PHY */
+#define	REG_MDIO_RDATA_8188E				0x0356	/* MDIO for Reads PCIE PHY */
+#define	REG_MDIO_CTL_8188E				0x0358	/* MDIO for Control */
+
+#define REG_MACID_NO_LINK_0			0x0484
+#define REG_MACID_NO_LINK_1			0x0488
+#define REG_MACID_PAUSE_0			0x048c
+#define REG_MACID_PAUSE_1			0x0490
+
+/* -----------------------------------------------------
+ *
+ *	0x0100h ~ 0x01FFh	MACTOP General Configuration
+ *
+ * ----------------------------------------------------- */
+#define REG_PKTBUF_DBG_ADDR			(REG_PKTBUF_DBG_CTRL)
+#define REG_RXPKTBUF_DBG				(REG_PKTBUF_DBG_CTRL+2)
+#define REG_TXPKTBUF_DBG				(REG_PKTBUF_DBG_CTRL+3)
+#define REG_WOWLAN_WAKE_REASON		REG_MCUTST_WOWLAN
+
+/* -----------------------------------------------------
+ *
+ *	0x0200h ~ 0x027Fh	TXDMA Configuration
+ *
+ * ----------------------------------------------------- */
+
+/* -----------------------------------------------------
+ *
+ *	0x0280h ~ 0x02FFh	RXDMA Configuration
+ *
+ * ----------------------------------------------------- */
+
+/* -----------------------------------------------------
+ *
+ *	0x0300h ~ 0x03FFh	PCIe
+ *
+ * ----------------------------------------------------- */
+#define REG_PCIE_HRPWM_8188E		0x0361	/* PCIe RPWM */
+#define REG_PCIE_HCPWM_8188E		0x0363	/* PCIe CPWM */
+
+/* -----------------------------------------------------
+ *
+ *	0x0400h ~ 0x047Fh	Protocol Configuration
+ *
+ * ----------------------------------------------------- */
+#ifdef CONFIG_WOWLAN
+	#define REG_TXPKTBUF_IV_LOW             0x01a4
+	#define REG_TXPKTBUF_IV_HIGH            0x01a8
+#endif
+
+/* -----------------------------------------------------
+ *
+ *	0x0500h ~ 0x05FFh	EDCA Configuration
+ *
+ * ----------------------------------------------------- */
+
+/* -----------------------------------------------------
+ *
+ *	0x0600h ~ 0x07FFh	WMAC Configuration
+ *
+ * ----------------------------------------------------- */
+#ifdef CONFIG_RF_POWER_TRIM
+	#define EEPROM_RF_GAIN_OFFSET			0xC1
+	#define EEPROM_RF_GAIN_VAL				0xF6
+	#define EEPROM_THERMAL_OFFSET			0xF5
+#endif /*CONFIG_RF_POWER_TRIM*/
+/* ----------------------------------------------------------------------------
+ * 88E Driver Initialization Offload REG_FDHM0(Offset 0x88, 8 bits)
+ * ----------------------------------------------------------------------------
+ * IOL config for REG_FDHM0(Reg0x88) */
+#define CMD_INIT_LLT					BIT0
+#define CMD_READ_EFUSE_MAP		BIT1
+#define CMD_EFUSE_PATCH			BIT2
+#define CMD_IOCONFIG				BIT3
+#define CMD_INIT_LLT_ERR			BIT4
+#define CMD_READ_EFUSE_MAP_ERR	BIT5
+#define CMD_EFUSE_PATCH_ERR		BIT6
+#define CMD_IOCONFIG_ERR			BIT7
+
+/* -----------------------------------------------------
+ *
+ *	Redifine register definition for compatibility
+ *
+ * ----------------------------------------------------- */
+
+/* TODO: use these definition when using REG_xxx naming rule.
+ * NOTE: DO NOT Remove these definition. Use later. */
+#define ISR_88E				REG_HISR_88E
+
+#ifdef CONFIG_PCI_HCI
+	/* #define IMR_RX_MASK		(IMR_ROK_88E|IMR_RDU_88E|IMR_RXFOVW_88E) */
+	#define IMR_TX_MASK			(IMR_VODOK_88E | IMR_VIDOK_88E | IMR_BEDOK_88E | IMR_BKDOK_88E | IMR_MGNTDOK_88E | IMR_HIGHDOK_88E | IMR_BCNDERR0_88E)
+
+	#ifdef CONFIG_CONCURRENT_MODE
+		#define RT_BCN_INT_MASKS	(IMR_BCNDMAINT0_88E | IMR_TBDOK_88E | IMR_TBDER_88E | IMR_BCNDMAINT_E_88E)
+	#else
+		#define RT_BCN_INT_MASKS	(IMR_BCNDMAINT0_88E | IMR_TBDOK_88E | IMR_TBDER_88E)
+	#endif
+
+	#define RT_AC_INT_MASKS	(IMR_VIDOK_88E | IMR_VODOK_88E | IMR_BEDOK_88E | IMR_BKDOK_88E)
+#endif
+
+/* ----------------------------------------------------------------------------
+ * 8192C EEPROM/EFUSE share register definition.
+ * ---------------------------------------------------------------------------- */
+
+#define EFUSE_ACCESS_ON			0x69	/* For RTL8723 only. */
+#define EFUSE_ACCESS_OFF			0x00	/* For RTL8723 only. */
+
+#endif /* __RTL8188E_SPEC_H__ */
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/include/rtl8188e_sreset.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/rtl8188e_sreset.h
--- linux-5.6.3/3rdparty/rtl8821ce/include/rtl8188e_sreset.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/rtl8188e_sreset.h	2020-04-10 16:35:06.848661561 +0300
@@ -0,0 +1,24 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#ifndef _RTL8188E_SRESET_H_
+#define _RTL8188E_SRESET_H_
+
+#include <rtw_sreset.h>
+
+#ifdef DBG_CONFIG_ERROR_DETECT
+	extern void rtl8188e_sreset_xmit_status_check(_adapter *padapter);
+	extern void rtl8188e_sreset_linked_status_check(_adapter *padapter);
+#endif
+#endif
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/include/rtl8188e_xmit.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/rtl8188e_xmit.h
--- linux-5.6.3/3rdparty/rtl8821ce/include/rtl8188e_xmit.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/rtl8188e_xmit.h	2020-04-10 16:35:06.848661561 +0300
@@ -0,0 +1,295 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#ifndef __RTL8188E_XMIT_H__
+#define __RTL8188E_XMIT_H__
+
+
+
+
+/* For 88e early mode */
+#define SET_EARLYMODE_PKTNUM(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr, 0, 3, __Value)
+#define SET_EARLYMODE_LEN0(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr, 4, 12, __Value)
+#define SET_EARLYMODE_LEN1(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr, 16, 12, __Value)
+#define SET_EARLYMODE_LEN2_1(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr, 28, 4, __Value)
+#define SET_EARLYMODE_LEN2_2(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr+4, 0, 8, __Value)
+#define SET_EARLYMODE_LEN3(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr+4, 8, 12, __Value)
+#define SET_EARLYMODE_LEN4(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr+4, 20, 12, __Value)
+
+/*
+ * defined for TX DESC Operation
+ *   */
+
+#define MAX_TID (15)
+
+/* OFFSET 0 */
+#define OFFSET_SZ	0
+#define OFFSET_SHT	16
+#define BMC		BIT(24)
+#define LSG		BIT(26)
+#define FSG		BIT(27)
+#define OWN		BIT(31)
+
+
+/* OFFSET 4 */
+#define PKT_OFFSET_SZ		0
+#define QSEL_SHT			8
+#define RATE_ID_SHT			16
+#define NAVUSEHDR			BIT(20)
+#define SEC_TYPE_SHT		22
+#define PKT_OFFSET_SHT		26
+
+/* OFFSET 8 */
+#define AGG_EN				BIT(12)
+#define AGG_BK					BIT(16)
+#define AMPDU_DENSITY_SHT	20
+#define ANTSEL_A			BIT(24)
+#define ANTSEL_B			BIT(25)
+#define TX_ANT_CCK_SHT		26
+#define TX_ANTL_SHT			28
+#define TX_ANT_HT_SHT		30
+
+/* OFFSET 12 */
+#define SEQ_SHT				16
+#define EN_HWSEQ			BIT(31)
+
+/* OFFSET 16 */
+#define	QOS                          BIT(6)
+#define	HW_SSN				BIT(7)
+#define	USERATE			BIT(8)
+#define	DISDATAFB			BIT(10)
+#define   CTS_2_SELF			BIT(11)
+#define	RTS_EN				BIT(12)
+#define	HW_RTS_EN			BIT(13)
+#define	DATA_SHORT			BIT(24)
+#define	PWR_STATUS_SHT	15
+#define	DATA_SC_SHT		20
+#define	DATA_BW			BIT(25)
+
+/* OFFSET 20 */
+#define	RTY_LMT_EN			BIT(17)
+
+
+/* OFFSET 20 */
+#define SGI					BIT(6)
+#define USB_TXAGG_NUM_SHT	24
+
+typedef struct txdesc_88e {
+	/* Offset 0 */
+	u32 pktlen:16;
+	u32 offset:8;
+	u32 bmc:1;
+	u32 htc:1;
+	u32 ls:1;
+	u32 fs:1;
+	u32 linip:1;
+	u32 noacm:1;
+	u32 gf:1;
+	u32 own:1;
+
+	/* Offset 4 */
+	u32 macid:6;
+	u32 rsvd0406:2;
+	u32 qsel:5;
+	u32 rd_nav_ext:1;
+	u32 lsig_txop_en:1;
+	u32 pifs:1;
+	u32 rate_id:4;
+	u32 navusehdr:1;
+	u32 en_desc_id:1;
+	u32 sectype:2;
+	u32 rsvd0424:2;
+	u32 pkt_offset:5;	/* unit: 8 bytes */
+	u32 rsvd0431:1;
+
+	/* Offset 8 */
+	u32 rts_rc:6;
+	u32 data_rc:6;
+	u32 agg_en:1;
+	u32 rd_en:1;
+	u32 bar_rty_th:2;
+	u32 bk:1;
+	u32 morefrag:1;
+	u32 raw:1;
+	u32 ccx:1;
+	u32 ampdu_density:3;
+	u32 bt_null:1;
+	u32 ant_sel_a:1;
+	u32 ant_sel_b:1;
+	u32 tx_ant_cck:2;
+	u32 tx_antl:2;
+	u32 tx_ant_ht:2;
+
+	/* Offset 12 */
+	u32 nextheadpage:8;
+	u32 tailpage:8;
+	u32 seq:12;
+	u32 cpu_handle:1;
+	u32 tag1:1;
+	u32 trigger_int:1;
+	u32 hwseq_en:1;
+
+	/* Offset 16 */
+	u32 rtsrate:5;
+	u32 ap_dcfe:1;
+	u32 hwseq_sel:2;
+	u32 userate:1;
+	u32 disrtsfb:1;
+	u32 disdatafb:1;
+	u32 cts2self:1;
+	u32 rtsen:1;
+	u32 hw_rts_en:1;
+	u32 port_id:1;
+	u32 pwr_status:3;
+	u32 wait_dcts:1;
+	u32 cts2ap_en:1;
+	u32 data_sc:2;
+	u32 data_stbc:2;
+	u32 data_short:1;
+	u32 data_bw:1;
+	u32 rts_short:1;
+	u32 rts_bw:1;
+	u32 rts_sc:2;
+	u32 vcs_stbc:2;
+
+	/* Offset 20 */
+	u32 datarate:6;
+	u32 sgi:1;
+	u32 try_rate:1;
+	u32 data_ratefb_lmt:5;
+	u32 rts_ratefb_lmt:4;
+	u32 rty_lmt_en:1;
+	u32 data_rt_lmt:6;
+	u32 usb_txagg_num:8;
+
+	/* Offset 24 */
+	u32 txagg_a:5;
+	u32 txagg_b:5;
+	u32 use_max_len:1;
+	u32 max_agg_num:5;
+	u32 mcsg1_max_len:4;
+	u32 mcsg2_max_len:4;
+	u32 mcsg3_max_len:4;
+	u32 mcs7_sgi_max_len:4;
+
+	/* Offset 28 */
+	u32 checksum:16;	/* TxBuffSize(PCIe)/CheckSum(USB) */
+	u32 sw0:8; /* offset 30 */
+	u32 sw1:4;
+	u32 mcs15_sgi_max_len:4;
+} TXDESC_8188E, *PTXDESC_8188E;
+
+#define txdesc_set_ccx_sw_88e(txdesc, value) \
+	do { \
+		((struct txdesc_88e *)(txdesc))->sw1 = (((value)>>8) & 0x0f); \
+		((struct txdesc_88e *)(txdesc))->sw0 = ((value) & 0xff); \
+	} while (0)
+
+struct txrpt_ccx_88e {
+	/* offset 0 */
+	u8 tag1:1;
+	u8 pkt_num:3;
+	u8 txdma_underflow:1;
+	u8 int_bt:1;
+	u8 int_tri:1;
+	u8 int_ccx:1;
+
+	/* offset 1 */
+	u8 mac_id:6;
+	u8 pkt_ok:1;
+	u8 bmc:1;
+
+	/* offset 2 */
+	u8 retry_cnt:6;
+	u8 lifetime_over:1;
+	u8 retry_over:1;
+
+	/* offset 3 */
+	u8 ccx_qtime0;
+	u8 ccx_qtime1;
+
+	/* offset 5 */
+	u8 final_data_rate;
+
+	/* offset 6 */
+	u8 sw1:4;
+	u8 qsel:4;
+
+	/* offset 7 */
+	u8 sw0;
+};
+
+#define txrpt_ccx_sw_88e(txrpt_ccx) ((txrpt_ccx)->sw0 + ((txrpt_ccx)->sw1<<8))
+#define txrpt_ccx_qtime_88e(txrpt_ccx) ((txrpt_ccx)->ccx_qtime0+((txrpt_ccx)->ccx_qtime1<<8))
+
+#define SET_TX_DESC_SEC_TYPE_8188E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 22, 2, __Value)
+
+void rtl8188e_fill_fake_txdesc(PADAPTER	padapter, u8 *pDesc, u32 BufferLen,
+			       u8 IsPsPoll, u8	IsBTQosNull, u8 bDataFrame);
+void rtl8188e_cal_txdesc_chksum(struct tx_desc	*ptxdesc);
+#if defined(CONFIG_CONCURRENT_MODE)
+	void fill_txdesc_force_bmc_camid(struct pkt_attrib *pattrib, struct tx_desc *ptxdesc);
+#endif
+
+#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
+	s32 rtl8188es_init_xmit_priv(PADAPTER padapter);
+	void rtl8188es_free_xmit_priv(PADAPTER padapter);
+	s32 rtl8188es_hal_xmit(PADAPTER padapter, struct xmit_frame *pxmitframe);
+	s32 rtl8188es_mgnt_xmit(PADAPTER padapter, struct xmit_frame *pmgntframe);
+	s32	rtl8188es_hal_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe);
+	thread_return rtl8188es_xmit_thread(thread_context context);
+	s32 rtl8188es_xmit_buf_handler(PADAPTER padapter);
+
+	#ifdef CONFIG_SDIO_TX_TASKLET
+		void rtl8188es_xmit_tasklet(void *priv);
+	#endif
+#endif
+
+#ifdef CONFIG_USB_HCI
+	s32 rtl8188eu_init_xmit_priv(PADAPTER padapter);
+	void rtl8188eu_free_xmit_priv(PADAPTER padapter);
+	s32 rtl8188eu_hal_xmit(PADAPTER padapter, struct xmit_frame *pxmitframe);
+	s32 rtl8188eu_mgnt_xmit(PADAPTER padapter, struct xmit_frame *pmgntframe);
+	s32	rtl8188eu_hal_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe);
+	s32 rtl8188eu_xmit_buf_handler(PADAPTER padapter);
+	void rtl8188eu_xmit_tasklet(void *priv);
+	s32 rtl8188eu_xmitframe_complete(_adapter *padapter, struct xmit_priv *pxmitpriv, struct xmit_buf *pxmitbuf);
+#endif
+
+#ifdef CONFIG_PCI_HCI
+	s32 rtl8188ee_init_xmit_priv(PADAPTER padapter);
+	void rtl8188ee_free_xmit_priv(PADAPTER padapter);
+	void	rtl8188ee_xmitframe_resume(_adapter *padapter);
+	s32 rtl8188ee_hal_xmit(PADAPTER padapter, struct xmit_frame *pxmitframe);
+	s32 rtl8188ee_mgnt_xmit(PADAPTER padapter, struct xmit_frame *pmgntframe);
+	s32	rtl8188ee_hal_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe);
+	void rtl8188ee_xmit_tasklet(void *priv);
+#endif
+
+
+
+#ifdef CONFIG_TX_EARLY_MODE
+	void UpdateEarlyModeInfo8188E(struct xmit_priv *pxmitpriv, struct xmit_buf *pxmitbuf);
+#endif
+
+#ifdef CONFIG_XMIT_ACK
+	void dump_txrpt_ccx_88e(void *buf);
+	void handle_txrpt_ccx_88e(_adapter *adapter, u8 *buf);
+#else
+	#define dump_txrpt_ccx_88e(buf) do {} while (0)
+	#define handle_txrpt_ccx_88e(adapter, buf) do {} while (0)
+#endif /* CONFIG_XMIT_ACK */
+
+void _dbg_dump_tx_info(_adapter	*padapter, int frame_tag, struct tx_desc *ptxdesc);
+#endif /* __RTL8188E_XMIT_H__ */
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/include/rtl8188f_cmd.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/rtl8188f_cmd.h
--- linux-5.6.3/3rdparty/rtl8821ce/include/rtl8188f_cmd.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/rtl8188f_cmd.h	2020-04-10 16:35:06.848661561 +0300
@@ -0,0 +1,206 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#ifndef __RTL8188F_CMD_H__
+#define __RTL8188F_CMD_H__
+
+/* ---------------------------------------------------------------------------------------------------------
+ * ----------------------------------    H2C CMD DEFINITION    ------------------------------------------------
+ * --------------------------------------------------------------------------------------------------------- */
+
+enum h2c_cmd_8188F {
+	/* Common Class: 000 */
+	H2C_8188F_RSVD_PAGE = 0x00,
+	H2C_8188F_MEDIA_STATUS_RPT = 0x01,
+	H2C_8188F_SCAN_ENABLE = 0x02,
+	H2C_8188F_KEEP_ALIVE = 0x03,
+	H2C_8188F_DISCON_DECISION = 0x04,
+	H2C_8188F_PSD_OFFLOAD = 0x05,
+	H2C_8188F_AP_OFFLOAD = 0x08,
+	H2C_8188F_BCN_RSVDPAGE = 0x09,
+	H2C_8188F_PROBERSP_RSVDPAGE = 0x0A,
+	H2C_8188F_FCS_RSVDPAGE = 0x10,
+	H2C_8188F_FCS_INFO = 0x11,
+	H2C_8188F_AP_WOW_GPIO_CTRL = 0x13,
+
+	/* PoweSave Class: 001 */
+	H2C_8188F_SET_PWR_MODE = 0x20,
+	H2C_8188F_PS_TUNING_PARA = 0x21,
+	H2C_8188F_PS_TUNING_PARA2 = 0x22,
+	H2C_8188F_P2P_LPS_PARAM = 0x23,
+	H2C_8188F_P2P_PS_OFFLOAD = 0x24,
+	H2C_8188F_PS_SCAN_ENABLE = 0x25,
+	H2C_8188F_SAP_PS_ = 0x26,
+	H2C_8188F_INACTIVE_PS_ = 0x27, /* Inactive_PS */
+	H2C_8188F_FWLPS_IN_IPS_ = 0x28,
+
+	/* Dynamic Mechanism Class: 010 */
+	H2C_8188F_MACID_CFG = 0x40,
+	H2C_8188F_TXBF = 0x41,
+	H2C_8188F_RSSI_SETTING = 0x42,
+	H2C_8188F_AP_REQ_TXRPT = 0x43,
+	H2C_8188F_INIT_RATE_COLLECT = 0x44,
+	H2C_8188F_RA_PARA_ADJUST = 0x46,
+
+	/* BT Class: 011 */
+	H2C_8188F_B_TYPE_TDMA = 0x60,
+	H2C_8188F_BT_INFO = 0x61,
+	H2C_8188F_FORCE_BT_TXPWR = 0x62,
+	H2C_8188F_BT_IGNORE_WLANACT = 0x63,
+	H2C_8188F_DAC_SWING_VALUE = 0x64,
+	H2C_8188F_ANT_SEL_RSV = 0x65,
+	H2C_8188F_WL_OPMODE = 0x66,
+	H2C_8188F_BT_MP_OPER = 0x67,
+	H2C_8188F_BT_CONTROL = 0x68,
+	H2C_8188F_BT_WIFI_CTRL = 0x69,
+	H2C_8188F_BT_FW_PATCH = 0x6A,
+	H2C_8188F_BT_WLAN_CALIBRATION = 0x6D,
+
+	/* WOWLAN Class: 100 */
+	H2C_8188F_WOWLAN = 0x80,
+	H2C_8188F_REMOTE_WAKE_CTRL = 0x81,
+	H2C_8188F_AOAC_GLOBAL_INFO = 0x82,
+	H2C_8188F_AOAC_RSVD_PAGE = 0x83,
+	H2C_8188F_AOAC_RSVD_PAGE2 = 0x84,
+	H2C_8188F_D0_SCAN_OFFLOAD_CTRL = 0x85,
+	H2C_8188F_D0_SCAN_OFFLOAD_INFO = 0x86,
+	H2C_8188F_CHNL_SWITCH_OFFLOAD = 0x87,
+	H2C_8188F_P2P_OFFLOAD_RSVD_PAGE = 0x8A,
+	H2C_8188F_P2P_OFFLOAD = 0x8B,
+
+	H2C_8188F_RESET_TSF = 0xC0,
+	H2C_8188F_MAXID,
+};
+
+/* ---------------------------------------------------------------------------------------------------------
+ * ----------------------------------    H2C CMD CONTENT    --------------------------------------------------
+ * ---------------------------------------------------------------------------------------------------------
+ * _RSVDPAGE_LOC_CMD_0x00 */
+#define SET_8188F_H2CCMD_RSVDPAGE_LOC_PROBE_RSP(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
+#define SET_8188F_H2CCMD_RSVDPAGE_LOC_PSPOLL(__pH2CCmd, __Value)				SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 8, __Value)
+#define SET_8188F_H2CCMD_RSVDPAGE_LOC_NULL_DATA(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value)
+#define SET_8188F_H2CCMD_RSVDPAGE_LOC_QOS_NULL_DATA(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 8, __Value)
+#define SET_8188F_H2CCMD_RSVDPAGE_LOC_BT_QOS_NULL_DATA(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 0, 8, __Value)
+
+/* _KEEP_ALIVE_CMD_0x03 */
+#define SET_8188F_H2CCMD_KEEPALIVE_PARM_ENABLE(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 1, __Value)
+#define SET_8188F_H2CCMD_KEEPALIVE_PARM_ADOPT(__pH2CCmd, __Value)				SET_BITS_TO_LE_1BYTE(__pH2CCmd, 1, 1, __Value)
+#define SET_8188F_H2CCMD_KEEPALIVE_PARM_PKT_TYPE(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE(__pH2CCmd, 2, 1, __Value)
+#define SET_8188F_H2CCMD_KEEPALIVE_PARM_CHECK_PERIOD(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 0, 8, __Value)
+
+/* _DISCONNECT_DECISION_CMD_0x04 */
+#define SET_8188F_H2CCMD_DISCONDECISION_PARM_ENABLE(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 1, __Value)
+#define SET_8188F_H2CCMD_DISCONDECISION_PARM_ADOPT(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE(__pH2CCmd, 1, 1, __Value)
+#define SET_8188F_H2CCMD_DISCONDECISION_PARM_CHECK_PERIOD(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 0, 8, __Value)
+#define SET_8188F_H2CCMD_DISCONDECISION_PARM_TRY_PKT_NUM(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 0, 8, __Value)
+
+/* _PWR_MOD_CMD_0x20 */
+#define SET_8188F_H2CCMD_PWRMODE_PARM_MODE(__pH2CCmd, __Value)				SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
+#define SET_8188F_H2CCMD_PWRMODE_PARM_RLBM(__pH2CCmd, __Value)				SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 4, __Value)
+#define SET_8188F_H2CCMD_PWRMODE_PARM_SMART_PS(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 4, 4, __Value)
+#define SET_8188F_H2CCMD_PWRMODE_PARM_BCN_PASS_TIME(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value)
+#define SET_8188F_H2CCMD_PWRMODE_PARM_ALL_QUEUE_UAPSD(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 8, __Value)
+#define SET_8188F_H2CCMD_PWRMODE_PARM_BCN_EARLY_C2H_RPT(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 2, 1, __Value)
+#define SET_8188F_H2CCMD_PWRMODE_PARM_PWR_STATE(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 0, 8, __Value)
+
+#define GET_8188F_H2CCMD_PWRMODE_PARM_MODE(__pH2CCmd)					LE_BITS_TO_1BYTE(__pH2CCmd, 0, 8)
+
+/* _PS_TUNE_PARAM_CMD_0x21 */
+#define SET_8188F_H2CCMD_PSTUNE_PARM_BCN_TO_LIMIT(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
+#define SET_8188F_H2CCMD_PSTUNE_PARM_DTIM_TIMEOUT(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 0, 8, __Value)
+#define SET_8188F_H2CCMD_PSTUNE_PARM_ADOPT(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 0, 1, __Value)
+#define SET_8188F_H2CCMD_PSTUNE_PARM_PS_TIMEOUT(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 1, 7, __Value)
+#define SET_8188F_H2CCMD_PSTUNE_PARM_DTIM_PERIOD(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE(__pH2CCmd+3, 0, 8, __Value)
+
+/* _MACID_CFG_CMD_0x40 */
+#define SET_8188F_H2CCMD_MACID_CFG_MACID(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
+#define SET_8188F_H2CCMD_MACID_CFG_RAID(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 0, 5, __Value)
+#define SET_8188F_H2CCMD_MACID_CFG_SGI_EN(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 7, 1, __Value)
+#define SET_8188F_H2CCMD_MACID_CFG_BW(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 0, 2, __Value)
+#define SET_8188F_H2CCMD_MACID_CFG_NO_UPDATE(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 3, 1, __Value)
+#define SET_8188F_H2CCMD_MACID_CFG_VHT_EN(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 4, 2, __Value)
+#define SET_8188F_H2CCMD_MACID_CFG_DISPT(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 6, 1, __Value)
+#define SET_8188F_H2CCMD_MACID_CFG_DISRA(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 7, 1, __Value)
+#define SET_8188F_H2CCMD_MACID_CFG_RATE_MASK0(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd+3, 0, 8, __Value)
+#define SET_8188F_H2CCMD_MACID_CFG_RATE_MASK1(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd+4, 0, 8, __Value)
+#define SET_8188F_H2CCMD_MACID_CFG_RATE_MASK2(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd+5, 0, 8, __Value)
+#define SET_8188F_H2CCMD_MACID_CFG_RATE_MASK3(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd+6, 0, 8, __Value)
+
+/* _RSSI_SETTING_CMD_0x42 */
+#define SET_8188F_H2CCMD_RSSI_SETTING_MACID(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
+#define SET_8188F_H2CCMD_RSSI_SETTING_RSSI(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 0, 7, __Value)
+#define SET_8188F_H2CCMD_RSSI_SETTING_ULDL_STATE(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd+3, 0, 8, __Value)
+
+/* _AP_REQ_TXRPT_CMD_0x43 */
+#define SET_8188F_H2CCMD_APREQRPT_PARM_MACID1(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
+#define SET_8188F_H2CCMD_APREQRPT_PARM_MACID2(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 0, 8, __Value)
+
+/* _FORCE_BT_TXPWR_CMD_0x62 */
+#define SET_8188F_H2CCMD_BT_PWR_IDX(__pH2CCmd, __Value)							SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
+
+/* _FORCE_BT_MP_OPER_CMD_0x67 */
+#define SET_8188F_H2CCMD_BT_MPOPER_VER(__pH2CCmd, __Value)							SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 4, __Value)
+#define SET_8188F_H2CCMD_BT_MPOPER_REQNUM(__pH2CCmd, __Value)							SET_BITS_TO_LE_1BYTE(__pH2CCmd, 4, 4, __Value)
+#define SET_8188F_H2CCMD_BT_MPOPER_IDX(__pH2CCmd, __Value)							SET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 0, 8, __Value)
+#define SET_8188F_H2CCMD_BT_MPOPER_PARAM1(__pH2CCmd, __Value)							SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 0, 8, __Value)
+#define SET_8188F_H2CCMD_BT_MPOPER_PARAM2(__pH2CCmd, __Value)							SET_BITS_TO_LE_1BYTE(__pH2CCmd+3, 0, 8, __Value)
+#define SET_8188F_H2CCMD_BT_MPOPER_PARAM3(__pH2CCmd, __Value)							SET_BITS_TO_LE_1BYTE(__pH2CCmd+4, 0, 8, __Value)
+
+/* _BT_FW_PATCH_0x6A */
+#define SET_8188F_H2CCMD_BT_FW_PATCH_SIZE(__pH2CCmd, __Value)					SET_BITS_TO_LE_2BYTE((pu1Byte)(__pH2CCmd), 0, 16, __Value)
+#define SET_8188F_H2CCMD_BT_FW_PATCH_ADDR0(__pH2CCmd, __Value)					SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value)
+#define SET_8188F_H2CCMD_BT_FW_PATCH_ADDR1(__pH2CCmd, __Value)					SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 8, __Value)
+#define SET_8188F_H2CCMD_BT_FW_PATCH_ADDR2(__pH2CCmd, __Value)					SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 0, 8, __Value)
+#define SET_8188F_H2CCMD_BT_FW_PATCH_ADDR3(__pH2CCmd, __Value)					SET_BITS_TO_LE_1BYTE((__pH2CCmd)+5, 0, 8, __Value)
+
+
+/* ---------------------------------------------------------------------------------------------------------
+ * -------------------------------------------    Structure    --------------------------------------------------
+ * --------------------------------------------------------------------------------------------------------- */
+
+
+/* ---------------------------------------------------------------------------------------------------------
+ * ----------------------------------    Function Statement     --------------------------------------------------
+ * --------------------------------------------------------------------------------------------------------- */
+
+/* host message to firmware cmd */
+void rtl8188f_set_FwPwrMode_cmd(PADAPTER padapter, u8 Mode);
+void rtl8188f_set_FwJoinBssRpt_cmd(PADAPTER padapter, u8 mstatus);
+void rtl8188f_fw_try_ap_cmd(PADAPTER padapter, u32 need_ack);
+/* s32 rtl8188f_set_lowpwr_lps_cmd(PADAPTER padapter, u8 enable); */
+void rtl8188f_set_FwPsTuneParam_cmd(PADAPTER padapter);
+void rtl8188f_set_FwBtMpOper_cmd(PADAPTER padapter, u8 idx, u8 ver, u8 reqnum, u8 *param);
+void rtl8188f_download_rsvd_page(PADAPTER padapter, u8 mstatus);
+#ifdef CONFIG_BT_COEXIST
+	void rtl8188f_download_BTCoex_AP_mode_rsvd_page(PADAPTER padapter);
+#endif /* CONFIG_BT_COEXIST */
+#ifdef CONFIG_P2P
+void rtl8188f_set_p2p_ps_offload_cmd(PADAPTER padapter, u8 p2p_ps_state);
+#endif /* CONFIG_P2P */
+
+#ifdef CONFIG_TDLS
+#ifdef CONFIG_TDLS_CH_SW
+void rtl8188f_set_BcnEarly_C2H_Rpt_cmd(PADAPTER padapter, u8 enable);
+#endif
+#endif
+
+#ifdef CONFIG_P2P_WOWLAN
+void rtl8188f_set_p2p_wowlan_offload_cmd(PADAPTER padapter);
+#endif
+
+void rtl8188f_set_FwPwrModeInIPS_cmd(PADAPTER padapter, u8 cmd_param);
+
+s32 FillH2CCmd8188F(PADAPTER padapter, u8 ElementID, u32 CmdLen, u8 *pCmdBuffer);
+u8 GetTxBufferRsvdPageNum8188F(_adapter *padapter, bool wowlan);
+#endif
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/include/rtl8188f_dm.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/rtl8188f_dm.h
--- linux-5.6.3/3rdparty/rtl8821ce/include/rtl8188f_dm.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/rtl8188f_dm.h	2020-04-10 16:35:06.848661561 +0300
@@ -0,0 +1,39 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#ifndef __RTL8188F_DM_H__
+#define __RTL8188F_DM_H__
+/* ************************************************************
+ * Description:
+ *
+ * This file is for 8188F dynamic mechanism only
+ *
+ *
+ * ************************************************************ */
+
+/* ************************************************************
+ * structure and define
+ * ************************************************************ */
+
+/* ************************************************************
+ * function prototype
+ * ************************************************************ */
+
+void rtl8188f_init_dm_priv(PADAPTER padapter);
+void rtl8188f_deinit_dm_priv(PADAPTER padapter);
+
+void rtl8188f_InitHalDm(PADAPTER padapter);
+void rtl8188f_HalDmWatchDog(PADAPTER padapter);
+
+#endif
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/include/rtl8188f_hal.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/rtl8188f_hal.h
--- linux-5.6.3/3rdparty/rtl8821ce/include/rtl8188f_hal.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/rtl8188f_hal.h	2020-04-10 16:35:06.848661561 +0300
@@ -0,0 +1,260 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#ifndef __RTL8188F_HAL_H__
+#define __RTL8188F_HAL_H__
+
+#include "hal_data.h"
+
+#include "rtl8188f_spec.h"
+#include "rtl8188f_rf.h"
+#include "rtl8188f_dm.h"
+#include "rtl8188f_recv.h"
+#include "rtl8188f_xmit.h"
+#include "rtl8188f_cmd.h"
+#include "rtl8188f_led.h"
+#include "Hal8188FPwrSeq.h"
+#include "Hal8188FPhyReg.h"
+#include "Hal8188FPhyCfg.h"
+#ifdef DBG_CONFIG_ERROR_DETECT
+#include "rtl8188f_sreset.h"
+#endif
+
+#define FW_8188F_SIZE			0x8000
+#define FW_8188F_START_ADDRESS	0x1000
+#define FW_8188F_END_ADDRESS		0x1FFF /* 0x5FFF */
+
+#define IS_FW_HEADER_EXIST_8188F(_pFwHdr)	((le16_to_cpu(_pFwHdr->Signature) & 0xFFF0) == 0x88F0)
+
+typedef struct _RT_FIRMWARE {
+	FIRMWARE_SOURCE	eFWSource;
+#ifdef CONFIG_EMBEDDED_FWIMG
+	u8			*szFwBuffer;
+#else
+	u8			szFwBuffer[FW_8188F_SIZE];
+#endif
+	u32			ulFwLength;
+} RT_FIRMWARE_8188F, *PRT_FIRMWARE_8188F;
+
+/*
+ * This structure must be cared byte-ordering
+ *
+ * Added by tynli. 2009.12.04. */
+typedef struct _RT_8188F_FIRMWARE_HDR {
+	/* 8-byte alinment required */
+
+	/* --- LONG WORD 0 ---- */
+	u16		Signature;	/* 92C0: test chip; 92C, 88C0: test chip; 88C1: MP A-cut; 92C1: MP A-cut */
+	u8		Category;	/* AP/NIC and USB/PCI */
+	u8		Function;	/* Reserved for different FW function indcation, for further use when driver needs to download different FW in different conditions */
+	u16		Version;		/* FW Version */
+	u16		Subversion;	/* FW Subversion, default 0x00 */
+
+	/* --- LONG WORD 1 ---- */
+	u8		Month;	/* Release time Month field */
+	u8		Date;	/* Release time Date field */
+	u8		Hour;	/* Release time Hour field */
+	u8		Minute;	/* Release time Minute field */
+	u16		RamCodeSize;	/* The size of RAM code */
+	u16		Rsvd2;
+
+	/* --- LONG WORD 2 ---- */
+	u32		SvnIdx;	/* The SVN entry index */
+	u32		Rsvd3;
+
+	/* --- LONG WORD 3 ---- */
+	u32		Rsvd4;
+	u32		Rsvd5;
+} RT_8188F_FIRMWARE_HDR, *PRT_8188F_FIRMWARE_HDR;
+
+#define DRIVER_EARLY_INT_TIME_8188F		0x05
+#define BCN_DMA_ATIME_INT_TIME_8188F		0x02
+
+/* for 8188F
+ * TX 32K, RX 16K, Page size 128B for TX, 8B for RX */
+#define PAGE_SIZE_TX_8188F			128
+#define PAGE_SIZE_RX_8188F			8
+
+#define RX_DMA_SIZE_8188F			0x4000	/* 16K */
+#ifdef CONFIG_FW_C2H_DEBUG
+	#define RX_DMA_RESERVED_SIZE_8188F	0x100	/* 256B, reserved for c2h debug message */
+#else
+	#define RX_DMA_RESERVED_SIZE_8188F	0x80	/* 128B, reserved for tx report */
+#endif
+
+#ifdef CONFIG_WOWLAN
+	#define RESV_FMWF	(WKFMCAM_SIZE * MAX_WKFM_CAM_NUM) /* 16 entries, for each is 24 bytes*/
+#else
+	#define RESV_FMWF	0
+#endif
+
+#define RX_DMA_BOUNDARY_8188F		(RX_DMA_SIZE_8188F - RX_DMA_RESERVED_SIZE_8188F - 1)
+
+/* Note: We will divide number of page equally for each queue other than public queue! */
+
+/* For General Reserved Page Number(Beacon Queue is reserved page)
+ * BCN rsvd_page_num = MAX_BEACON_LEN / PAGE_SIZE_TX_8188F,
+ * PS-Poll:1, Null Data:1,Qos Null Data:1,BT Qos Null Data:1, CTS-2-SELF / LTE QoS Null */
+
+#define BCNQ_PAGE_NUM_8188F		(MAX_BEACON_LEN / PAGE_SIZE_TX_8188F + 6) /*0x08*/
+
+/* For WoWLan , more reserved page
+ * ARP Rsp:1, RWC:1, GTK Info:1,GTK RSP:2,GTK EXT MEM:2, AOAC rpt:1 ,PNO: 6
+ * NS offload:2 NDP info: 1
+ */
+#ifdef CONFIG_WOWLAN
+	#define WOWLAN_PAGE_NUM_8188F	0x0b
+#else
+	#define WOWLAN_PAGE_NUM_8188F	0x00
+#endif
+
+#ifdef CONFIG_PNO_SUPPORT
+#undef WOWLAN_PAGE_NUM_8188F
+#define WOWLAN_PAGE_NUM_8188F	0x15
+#endif
+
+#ifdef CONFIG_AP_WOWLAN
+#define AP_WOWLAN_PAGE_NUM_8188F	0x02
+#endif
+
+#define TX_TOTAL_PAGE_NUMBER_8188F	(0xFF - BCNQ_PAGE_NUM_8188F - WOWLAN_PAGE_NUM_8188F)
+#define TX_PAGE_BOUNDARY_8188F		(TX_TOTAL_PAGE_NUMBER_8188F + 1)
+
+#define WMM_NORMAL_TX_TOTAL_PAGE_NUMBER_8188F	TX_TOTAL_PAGE_NUMBER_8188F
+#define WMM_NORMAL_TX_PAGE_BOUNDARY_8188F		(WMM_NORMAL_TX_TOTAL_PAGE_NUMBER_8188F + 1)
+
+/* For Normal Chip Setting
+ * (HPQ + LPQ + NPQ + PUBQ) shall be TX_TOTAL_PAGE_NUMBER_8188F */
+#define NORMAL_PAGE_NUM_HPQ_8188F		0x0C
+#define NORMAL_PAGE_NUM_LPQ_8188F		0x02
+#define NORMAL_PAGE_NUM_NPQ_8188F		0x02
+
+/* Note: For Normal Chip Setting, modify later */
+#define WMM_NORMAL_PAGE_NUM_HPQ_8188F		0x30
+#define WMM_NORMAL_PAGE_NUM_LPQ_8188F		0x20
+#define WMM_NORMAL_PAGE_NUM_NPQ_8188F		0x20
+
+
+#include "HalVerDef.h"
+#include "hal_com.h"
+
+#define EFUSE_OOB_PROTECT_BYTES (34 + 1)
+
+#define HAL_EFUSE_MEMORY
+
+#define HWSET_MAX_SIZE_8188F			512
+#define EFUSE_REAL_CONTENT_LEN_8188F	256
+#define EFUSE_MAP_LEN_8188F				512
+#define EFUSE_MAX_SECTION_8188F			(EFUSE_MAP_LEN_8188F / 8)
+
+#define EFUSE_IC_ID_OFFSET			506	/* For some inferiority IC purpose. added by Roger, 2009.09.02. */
+#define AVAILABLE_EFUSE_ADDR(addr)	(addr < EFUSE_REAL_CONTENT_LEN_8188F)
+
+#define EFUSE_ACCESS_ON			0x69	/* For RTL8188 only. */
+#define EFUSE_ACCESS_OFF			0x00	/* For RTL8188 only. */
+
+/* ********************************************************
+ *			EFUSE for BT definition
+ * ******************************************************** */
+#define EFUSE_BT_REAL_BANK_CONTENT_LEN	512
+#define EFUSE_BT_REAL_CONTENT_LEN		1536	/* 512*3 */
+#define EFUSE_BT_MAP_LEN				1024	/* 1k bytes */
+#define EFUSE_BT_MAX_SECTION			128		/* 1024/8 */
+
+#define EFUSE_PROTECT_BYTES_BANK		16
+
+#define INCLUDE_MULTI_FUNC_BT(_Adapter)		(GET_HAL_DATA(_Adapter)->MultiFunc & RT_MULTI_FUNC_BT)
+#define INCLUDE_MULTI_FUNC_GPS(_Adapter)	(GET_HAL_DATA(_Adapter)->MultiFunc & RT_MULTI_FUNC_GPS)
+
+/* rtl8188a_hal_init.c */
+s32 rtl8188f_FirmwareDownload(PADAPTER padapter, BOOLEAN  bUsedWoWLANFw);
+void rtl8188f_FirmwareSelfReset(PADAPTER padapter);
+void rtl8188f_InitializeFirmwareVars(PADAPTER padapter);
+
+void rtl8188f_InitAntenna_Selection(PADAPTER padapter);
+void rtl8188f_DeinitAntenna_Selection(PADAPTER padapter);
+void rtl8188f_CheckAntenna_Selection(PADAPTER padapter);
+void rtl8188f_init_default_value(PADAPTER padapter);
+
+s32 rtl8188f_InitLLTTable(PADAPTER padapter);
+
+s32 CardDisableHWSM(PADAPTER padapter, u8 resetMCU);
+s32 CardDisableWithoutHWSM(PADAPTER padapter);
+
+/* EFuse */
+u8 GetEEPROMSize8188F(PADAPTER padapter);
+void Hal_InitPGData(PADAPTER padapter, u8 *PROMContent);
+void Hal_EfuseParseIDCode(PADAPTER padapter, u8 *hwinfo);
+void Hal_EfuseParseTxPowerInfo_8188F(PADAPTER padapter, u8 *PROMContent, BOOLEAN AutoLoadFail);
+/* void Hal_EfuseParseBTCoexistInfo_8188F(PADAPTER padapter, u8 *hwinfo, BOOLEAN AutoLoadFail); */
+void Hal_EfuseParseEEPROMVer_8188F(PADAPTER padapter, u8 *hwinfo, BOOLEAN AutoLoadFail);
+void Hal_EfuseParseChnlPlan_8188F(PADAPTER padapter, u8 *hwinfo, BOOLEAN AutoLoadFail);
+void Hal_EfuseParseCustomerID_8188F(PADAPTER padapter, u8 *hwinfo, BOOLEAN AutoLoadFail);
+void Hal_EfuseParsePowerSavingMode_8188F(PADAPTER pAdapter, u8 *hwinfo, BOOLEAN AutoLoadFail);
+void Hal_EfuseParseAntennaDiversity_8188F(PADAPTER padapter, u8 *hwinfo, BOOLEAN AutoLoadFail);
+void Hal_EfuseParseXtal_8188F(PADAPTER pAdapter, u8 *hwinfo, u8 AutoLoadFail);
+void Hal_EfuseParseThermalMeter_8188F(PADAPTER padapter, u8 *hwinfo, u8 AutoLoadFail);
+void Hal_EfuseParseKFreeData_8188F(PADAPTER pAdapter, u8 *hwinfo, BOOLEAN AutoLoadFail);
+
+#if 0 /* Do not need for rtl8188f */
+VOID Hal_EfuseParseVoltage_8188F(PADAPTER pAdapter, u8 *hwinfo, BOOLEAN	AutoLoadFail);
+#endif
+
+void rtl8188f_set_pll_ref_clk_sel(_adapter *adapter, u8 sel);
+
+void rtl8188f_set_hal_ops(struct hal_ops *pHalFunc);
+void init_hal_spec_8188f(_adapter *adapter);
+u8 SetHwReg8188F(PADAPTER padapter, u8 variable, u8 *val);
+void GetHwReg8188F(PADAPTER padapter, u8 variable, u8 *val);
+u8 SetHalDefVar8188F(PADAPTER padapter, HAL_DEF_VARIABLE variable, void *pval);
+u8 GetHalDefVar8188F(PADAPTER padapter, HAL_DEF_VARIABLE variable, void *pval);
+
+/* register */
+void rtl8188f_InitBeaconParameters(PADAPTER padapter);
+void rtl8188f_InitBeaconMaxError(PADAPTER padapter, u8 InfraMode);
+void	_InitBurstPktLen_8188FS(PADAPTER Adapter);
+void _8051Reset8188(PADAPTER padapter);
+#ifdef CONFIG_WOWLAN
+void Hal_DetectWoWMode(PADAPTER pAdapter);
+#endif /* CONFIG_WOWLAN */
+
+void rtl8188f_start_thread(_adapter *padapter);
+void rtl8188f_stop_thread(_adapter *padapter);
+
+#if defined(CONFIG_CHECK_BT_HANG) && defined(CONFIG_BT_COEXIST)
+	void rtl8188fs_init_checkbthang_workqueue(_adapter *adapter);
+	void rtl8188fs_free_checkbthang_workqueue(_adapter *adapter);
+	void rtl8188fs_cancle_checkbthang_workqueue(_adapter *adapter);
+	void rtl8188fs_hal_check_bt_hang(_adapter *adapter);
+#endif
+
+#ifdef CONFIG_GPIO_WAKEUP
+void HalSetOutPutGPIO(PADAPTER padapter, u8 index, u8 OutPutValue);
+#endif
+
+#ifdef CONFIG_MP_INCLUDED
+int FirmwareDownloadBT(IN PADAPTER Adapter, PRT_MP_FIRMWARE pFirmware);
+#endif
+
+void CCX_FwC2HTxRpt_8188f(PADAPTER padapter, u8 *pdata, u8 len);
+
+u8 MRateToHwRate8188F(u8  rate);
+u8 HwRateToMRate8188F(u8	 rate);
+
+#ifdef CONFIG_PCI_HCI
+BOOLEAN	InterruptRecognized8188FE(PADAPTER Adapter);
+VOID	UpdateInterruptMask8188FE(PADAPTER Adapter, u32 AddMSR, u32 AddMSR1, u32 RemoveMSR, u32 RemoveMSR1);
+#endif
+
+#endif
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/include/rtl8188f_led.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/rtl8188f_led.h
--- linux-5.6.3/3rdparty/rtl8821ce/include/rtl8188f_led.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/rtl8188f_led.h	2020-04-10 16:35:06.848661561 +0300
@@ -0,0 +1,45 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#ifndef __RTL8188F_LED_H__
+#define __RTL8188F_LED_H__
+#ifdef CONFIG_RTW_SW_LED
+
+#include <drv_conf.h>
+#include <osdep_service.h>
+#include <drv_types.h>
+
+
+/* ********************************************************************************
+ * Interface to manipulate LED objects.
+ * ******************************************************************************** */
+#ifdef CONFIG_USB_HCI
+void rtl8188fu_InitSwLeds(PADAPTER padapter);
+void rtl8188fu_DeInitSwLeds(PADAPTER padapter);
+#endif
+#ifdef CONFIG_SDIO_HCI
+void rtl8188fs_InitSwLeds(PADAPTER padapter);
+void rtl8188fs_DeInitSwLeds(PADAPTER padapter);
+#endif
+#ifdef CONFIG_GSPI_HCI
+void rtl8188fs_InitSwLeds(PADAPTER padapter);
+void rtl8188fs_DeInitSwLeds(PADAPTER padapter);
+#endif
+#ifdef CONFIG_PCI_HCI
+void rtl8188fe_InitSwLeds(PADAPTER padapter);
+void rtl8188fe_DeInitSwLeds(PADAPTER padapter);
+#endif
+
+#endif
+#endif/*CONFIG_RTW_SW_LED*/
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/include/rtl8188f_recv.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/rtl8188f_recv.h
--- linux-5.6.3/3rdparty/rtl8821ce/include/rtl8188f_recv.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/rtl8188f_recv.h	2020-04-10 16:35:06.848661561 +0300
@@ -0,0 +1,68 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#ifndef __RTL8188F_RECV_H__
+#define __RTL8188F_RECV_H__
+
+#if defined(CONFIG_USB_HCI)
+	#ifndef MAX_RECVBUF_SZ
+		#ifdef PLATFORM_OS_CE
+			#define MAX_RECVBUF_SZ (8192+1024) /* 8K+1k */
+		#else
+			#ifdef CONFIG_MINIMAL_MEMORY_USAGE
+				#define MAX_RECVBUF_SZ (4000) /* about 4K */
+			#else
+				#ifdef CONFIG_PLATFORM_MSTAR
+					#define MAX_RECVBUF_SZ (8192) /* 8K */
+				#elif defined(CONFIG_PLATFORM_HISILICON)
+					#define MAX_RECVBUF_SZ (16384) /* 16k */
+				#else
+					#define MAX_RECVBUF_SZ (32768) /* 32k */
+				#endif
+				/* #define MAX_RECVBUF_SZ (20480) */ /* 20K */
+				/* #define MAX_RECVBUF_SZ (10240)  */ /* 10K */
+				/* #define MAX_RECVBUF_SZ (16384) */ /* 16k - 92E RX BUF :16K */
+				/* #define MAX_RECVBUF_SZ (8192+1024) */ /* 8K+1k		 */
+			#endif
+		#endif
+	#endif /* !MAX_RECVBUF_SZ */
+#elif defined(CONFIG_PCI_HCI)
+	#define MAX_RECVBUF_SZ (4000) /* about 4K */
+#elif defined(CONFIG_SDIO_HCI)
+	#define MAX_RECVBUF_SZ (RX_DMA_BOUNDARY_8188F + 1)
+#endif /* CONFIG_SDIO_HCI */
+
+/* Rx smooth factor */
+#define	Rx_Smooth_Factor (20)
+
+#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
+s32 rtl8188fs_init_recv_priv(PADAPTER padapter);
+void rtl8188fs_free_recv_priv(PADAPTER padapter);
+s32 rtl8188fs_recv_hdl(_adapter *padapter);
+#endif
+
+#ifdef CONFIG_USB_HCI
+int rtl8188fu_init_recv_priv(_adapter *padapter);
+void rtl8188fu_free_recv_priv(_adapter *padapter);
+void rtl8188fu_init_recvbuf(_adapter *padapter, struct recv_buf *precvbuf);
+#endif
+
+#ifdef CONFIG_PCI_HCI
+s32 rtl8188fe_init_recv_priv(PADAPTER padapter);
+void rtl8188fe_free_recv_priv(PADAPTER padapter);
+#endif
+
+void rtl8188f_query_rx_desc_status(union recv_frame *precvframe, u8 *pdesc);
+
+#endif /* __RTL8188F_RECV_H__ */
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/include/rtl8188f_rf.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/rtl8188f_rf.h
--- linux-5.6.3/3rdparty/rtl8821ce/include/rtl8188f_rf.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/rtl8188f_rf.h	2020-04-10 16:35:06.848661561 +0300
@@ -0,0 +1,25 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#ifndef __RTL8188F_RF_H__
+#define __RTL8188F_RF_H__
+
+int	PHY_RF6052_Config8188F(IN	PADAPTER		Adapter);
+
+VOID
+PHY_RF6052SetBandwidth8188F(
+	IN	PADAPTER				Adapter,
+	IN	enum channel_width		Bandwidth);
+
+#endif
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/include/rtl8188f_spec.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/rtl8188f_spec.h
--- linux-5.6.3/3rdparty/rtl8821ce/include/rtl8188f_spec.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/rtl8188f_spec.h	2020-04-10 16:35:06.848661561 +0300
@@ -0,0 +1,275 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#ifndef __RTL8188F_SPEC_H__
+#define __RTL8188F_SPEC_H__
+
+#include <drv_conf.h>
+
+
+#define HAL_NAV_UPPER_UNIT_8188F		128		/* micro-second */
+
+/* -----------------------------------------------------
+ *
+ *	0x0000h ~ 0x00FFh	System Configuration
+ *
+ * ----------------------------------------------------- */
+#define REG_RSV_CTRL_8188F				0x001C	/* 3 Byte */
+#define REG_BT_WIFI_ANTENNA_SWITCH_8188F	0x0038
+#define REG_HSISR_8188F					0x005c
+#define REG_PAD_CTRL1_8188F		0x0064
+#define REG_AFE_CTRL_4_8188F		0x0078
+#define REG_HMEBOX_DBG_0_8188F	0x0088
+#define REG_HMEBOX_DBG_1_8188F	0x008A
+#define REG_HMEBOX_DBG_2_8188F	0x008C
+#define REG_HMEBOX_DBG_3_8188F	0x008E
+#define REG_HIMR0_8188F					0x00B0
+#define REG_HISR0_8188F					0x00B4
+#define REG_HIMR1_8188F					0x00B8
+#define REG_HISR1_8188F					0x00BC
+#define REG_PMC_DBG_CTRL2_8188F			0x00CC
+
+/* -----------------------------------------------------
+ *
+ *	0x0100h ~ 0x01FFh	MACTOP General Configuration
+ *
+ * ----------------------------------------------------- */
+#define REG_C2HEVT_CMD_ID_8188F	0x01A0
+#define REG_C2HEVT_CMD_LEN_8188F	0x01AE
+#define REG_WOWLAN_WAKE_REASON 0x01C7
+#define REG_WOWLAN_GTK_DBG1	0x630
+#define REG_WOWLAN_GTK_DBG2	0x634
+
+#define REG_HMEBOX_EXT0_8188F			0x01F0
+#define REG_HMEBOX_EXT1_8188F			0x01F4
+#define REG_HMEBOX_EXT2_8188F			0x01F8
+#define REG_HMEBOX_EXT3_8188F			0x01FC
+
+/* -----------------------------------------------------
+ *
+ *	0x0200h ~ 0x027Fh	TXDMA Configuration
+ *
+ * ----------------------------------------------------- */
+
+/* -----------------------------------------------------
+ *
+ *	0x0280h ~ 0x02FFh	RXDMA Configuration
+ *
+ * ----------------------------------------------------- */
+#define REG_RXDMA_CONTROL_8188F		0x0286 /* Control the RX DMA. */
+#define REG_RXDMA_MODE_CTRL_8188F		0x0290
+
+/* -----------------------------------------------------
+ *
+ *	0x0300h ~ 0x03FFh	PCIe
+ *
+ * ----------------------------------------------------- */
+#define	REG_PCIE_CTRL_REG_8188F		0x0300
+#define	REG_INT_MIG_8188F				0x0304	/* Interrupt Migration */
+#define	REG_BCNQ_DESA_8188F			0x0308	/* TX Beacon Descriptor Address */
+#define	REG_HQ_DESA_8188F				0x0310	/* TX High Queue Descriptor Address */
+#define	REG_MGQ_DESA_8188F			0x0318	/* TX Manage Queue Descriptor Address */
+#define	REG_VOQ_DESA_8188F			0x0320	/* TX VO Queue Descriptor Address */
+#define	REG_VIQ_DESA_8188F				0x0328	/* TX VI Queue Descriptor Address */
+#define	REG_BEQ_DESA_8188F			0x0330	/* TX BE Queue Descriptor Address */
+#define	REG_BKQ_DESA_8188F			0x0338	/* TX BK Queue Descriptor Address */
+#define	REG_RX_DESA_8188F				0x0340	/* RX Queue	Descriptor Address */
+#define	REG_DBI_WDATA_8188F			0x0348	/* DBI Write Data */
+#define	REG_DBI_RDATA_8188F			0x034C	/* DBI Read Data */
+#define	REG_DBI_ADDR_8188F				0x0350	/* DBI Address */
+#define	REG_DBI_FLAG_8188F				0x0352	/* DBI Read/Write Flag */
+#define	REG_MDIO_WDATA_8188F		0x0354	/* MDIO for Write PCIE PHY */
+#define	REG_MDIO_RDATA_8188F			0x0356	/* MDIO for Reads PCIE PHY */
+#define	REG_MDIO_CTL_8188F			0x0358	/* MDIO for Control */
+#define	REG_DBG_SEL_8188F				0x0360	/* Debug Selection Register */
+#define	REG_PCIE_HRPWM_8188F			0x0361	/* PCIe RPWM */
+#define	REG_PCIE_HCPWM_8188F			0x0363	/* PCIe CPWM */
+#define	REG_PCIE_MULTIFET_CTRL_8188F	0x036A	/* PCIE Multi-Fethc Control */
+
+/* -----------------------------------------------------
+ *
+ *	0x0400h ~ 0x047Fh	Protocol Configuration
+ *
+ * ----------------------------------------------------- */
+#define REG_TXPKTBUF_BCNQ_BDNY_8188F	0x0424
+#define REG_TXPKTBUF_MGQ_BDNY_8188F	0x0425
+#define REG_TXPKTBUF_WMAC_LBK_BF_HD_8188F	0x045D
+#ifdef CONFIG_WOWLAN
+#define REG_TXPKTBUF_IV_LOW             0x0484
+#define REG_TXPKTBUF_IV_HIGH            0x0488
+#endif
+#define REG_AMPDU_BURST_MODE_8188F	0x04BC
+
+/* -----------------------------------------------------
+ *
+ *	0x0500h ~ 0x05FFh	EDCA Configuration
+ *
+ * ----------------------------------------------------- */
+#define REG_SECONDARY_CCA_CTRL_8188F	0x0577
+
+/* -----------------------------------------------------
+ *
+ *	0x0600h ~ 0x07FFh	WMAC Configuration
+ *
+ * ----------------------------------------------------- */
+
+
+/* ************************************************************
+ * SDIO Bus Specification
+ * ************************************************************ */
+
+/* -----------------------------------------------------
+ * SDIO CMD Address Mapping
+ * ----------------------------------------------------- */
+
+/* -----------------------------------------------------
+ * I/O bus domain (Host)
+ * ----------------------------------------------------- */
+
+/* -----------------------------------------------------
+ * SDIO register
+ * ----------------------------------------------------- */
+#define SDIO_REG_HIQ_FREEPG_8188F		0x0020
+#define SDIO_REG_MID_FREEPG_8188F		0x0022
+#define SDIO_REG_LOW_FREEPG_8188F		0x0024
+#define SDIO_REG_PUB_FREEPG_8188F		0x0026
+#define SDIO_REG_EXQ_FREEPG_8188F		0x0028
+#define SDIO_REG_AC_OQT_FREEPG_8188F	0x002A
+#define SDIO_REG_NOAC_OQT_FREEPG_8188F	0x002B
+
+#define SDIO_REG_HCPWM1_8188F			0x0038
+
+/* ****************************************************************************
+ *	8188 Regsiter Bit and Content definition
+ * **************************************************************************** */
+
+/* 2 HSISR
+ * interrupt mask which needs to clear */
+#define MASK_HSISR_CLEAR		(HSISR_GPIO12_0_INT |\
+		HSISR_SPS_OCP_INT |\
+		HSISR_RON_INT |\
+		HSISR_PDNINT |\
+		HSISR_GPIO9_INT)
+
+/* -----------------------------------------------------
+ *
+ *	0x0100h ~ 0x01FFh	MACTOP General Configuration
+ *
+ * ----------------------------------------------------- */
+
+
+/* -----------------------------------------------------
+ *
+ *	0x0200h ~ 0x027Fh	TXDMA Configuration
+ *
+ * ----------------------------------------------------- */
+
+/* -----------------------------------------------------
+ *
+ *	0x0280h ~ 0x02FFh	RXDMA Configuration
+ *
+ * ----------------------------------------------------- */
+#define BIT_USB_RXDMA_AGG_EN	BIT(31)
+#define RXDMA_AGG_MODE_EN		BIT(1)
+
+#ifdef CONFIG_WOWLAN
+#define RXPKT_RELEASE_POLL		BIT(16)
+#define RXDMA_IDLE				BIT(17)
+#define RW_RELEASE_EN			BIT(18)
+#endif
+
+/* -----------------------------------------------------
+ *
+ *	0x0400h ~ 0x047Fh	Protocol Configuration
+ *
+ * ----------------------------------------------------- */
+
+/* ----------------------------------------------------------------------------
+ * 8188F REG_CCK_CHECK						(offset 0x454)
+ * ---------------------------------------------------------------------------- */
+#define BIT_BCN_PORT_SEL		BIT(5)
+
+/* -----------------------------------------------------
+ *
+ *	0x0500h ~ 0x05FFh	EDCA Configuration
+ *
+ * ----------------------------------------------------- */
+
+/* -----------------------------------------------------
+ *
+ *	0x0600h ~ 0x07FFh	WMAC Configuration
+ *
+ * ----------------------------------------------------- */
+
+/* ----------------------------------------------------------------------------
+ * 8195 IMR/ISR bits						(offset 0xB0,  8bits)
+ * ---------------------------------------------------------------------------- */
+#define	IMR_DISABLED_8188F					0
+/* IMR DW0(0x00B0-00B3) Bit 0-31 */
+#define	IMR_TIMER2_8188F					BIT(31)		/* Timeout interrupt 2 */
+#define	IMR_TIMER1_8188F					BIT(30)		/* Timeout interrupt 1	 */
+#define	IMR_PSTIMEOUT_8188F				BIT(29)		/* Power Save Time Out Interrupt */
+#define	IMR_GTINT4_8188F					BIT(28)		/* When GTIMER4 expires, this bit is set to 1	 */
+#define	IMR_GTINT3_8188F					BIT(27)		/* When GTIMER3 expires, this bit is set to 1	 */
+#define	IMR_TXBCN0ERR_8188F				BIT(26)		/* Transmit Beacon0 Error			 */
+#define	IMR_TXBCN0OK_8188F				BIT(25)		/* Transmit Beacon0 OK			 */
+#define	IMR_TSF_BIT32_TOGGLE_8188F		BIT(24)		/* TSF Timer BIT(32) toggle indication interrupt			 */
+#define	IMR_BCNDMAINT0_8188F				BIT(20)		/* Beacon DMA Interrupt 0			 */
+#define	IMR_BCNDERR0_8188F				BIT(16)		/* Beacon Queue DMA OK0			 */
+#define	IMR_HSISR_IND_ON_INT_8188F		BIT(15)		/* HSISR Indicator (HSIMR & HSISR is true, this bit is set to 1) */
+#define	IMR_BCNDMAINT_E_8188F			BIT(14)		/* Beacon DMA Interrupt Extension for Win7			 */
+#define	IMR_ATIMEND_8188F				BIT(12)		/* CTWidnow End or ATIM Window End */
+#define	IMR_C2HCMD_8188F					BIT(10)		/* CPU to Host Command INT Status, Write 1 clear	 */
+#define	IMR_CPWM2_8188F					BIT(9)			/* CPU power Mode exchange INT Status, Write 1 clear	 */
+#define	IMR_CPWM_8188F					BIT(8)			/* CPU power Mode exchange INT Status, Write 1 clear	 */
+#define	IMR_HIGHDOK_8188F				BIT(7)			/* High Queue DMA OK	 */
+#define	IMR_MGNTDOK_8188F				BIT(6)			/* Management Queue DMA OK	 */
+#define	IMR_BKDOK_8188F					BIT(5)			/* AC_BK DMA OK		 */
+#define	IMR_BEDOK_8188F					BIT(4)			/* AC_BE DMA OK	 */
+#define	IMR_VIDOK_8188F					BIT(3)			/* AC_VI DMA OK		 */
+#define	IMR_VODOK_8188F					BIT(2)			/* AC_VO DMA OK	 */
+#define	IMR_RDU_8188F					BIT(1)			/* Rx Descriptor Unavailable	 */
+#define	IMR_ROK_8188F					BIT(0)			/* Receive DMA OK */
+
+/* IMR DW1(0x00B4-00B7) Bit 0-31 */
+#define	IMR_BCNDMAINT7_8188F				BIT(27)		/* Beacon DMA Interrupt 7 */
+#define	IMR_BCNDMAINT6_8188F				BIT(26)		/* Beacon DMA Interrupt 6 */
+#define	IMR_BCNDMAINT5_8188F				BIT(25)		/* Beacon DMA Interrupt 5 */
+#define	IMR_BCNDMAINT4_8188F				BIT(24)		/* Beacon DMA Interrupt 4 */
+#define	IMR_BCNDMAINT3_8188F				BIT(23)		/* Beacon DMA Interrupt 3 */
+#define	IMR_BCNDMAINT2_8188F				BIT(22)		/* Beacon DMA Interrupt 2 */
+#define	IMR_BCNDMAINT1_8188F				BIT(21)		/* Beacon DMA Interrupt 1 */
+#define	IMR_BCNDOK7_8188F					BIT(20)		/* Beacon Queue DMA OK Interrupt 7 */
+#define	IMR_BCNDOK6_8188F					BIT(19)		/* Beacon Queue DMA OK Interrupt 6 */
+#define	IMR_BCNDOK5_8188F					BIT(18)		/* Beacon Queue DMA OK Interrupt 5 */
+#define	IMR_BCNDOK4_8188F					BIT(17)		/* Beacon Queue DMA OK Interrupt 4 */
+#define	IMR_BCNDOK3_8188F					BIT(16)		/* Beacon Queue DMA OK Interrupt 3 */
+#define	IMR_BCNDOK2_8188F					BIT(15)		/* Beacon Queue DMA OK Interrupt 2 */
+#define	IMR_BCNDOK1_8188F					BIT(14)		/* Beacon Queue DMA OK Interrupt 1 */
+#define	IMR_ATIMEND_E_8188F				BIT(13)		/* ATIM Window End Extension for Win7 */
+#define	IMR_TXERR_8188F					BIT(11)		/* Tx Error Flag Interrupt Status, write 1 clear. */
+#define	IMR_RXERR_8188F					BIT(10)		/* Rx Error Flag INT Status, Write 1 clear */
+#define	IMR_TXFOVW_8188F					BIT(9)			/* Transmit FIFO Overflow */
+#define	IMR_RXFOVW_8188F					BIT(8)			/* Receive FIFO Overflow */
+
+#ifdef CONFIG_PCI_HCI
+/* #define IMR_RX_MASK		(IMR_ROK_8188F|IMR_RDU_8188F|IMR_RXFOVW_8188F) */
+#define IMR_TX_MASK			(IMR_VODOK_8188F | IMR_VIDOK_8188F | IMR_BEDOK_8188F | IMR_BKDOK_8188F | IMR_MGNTDOK_8188F | IMR_HIGHDOK_8188F)
+
+#define RT_BCN_INT_MASKS	(IMR_BCNDMAINT0_8188F | IMR_TXBCN0OK_8188F | IMR_TXBCN0ERR_8188F | IMR_BCNDERR0_8188F)
+
+#define RT_AC_INT_MASKS	(IMR_VIDOK_8188F | IMR_VODOK_8188F | IMR_BEDOK_8188F | IMR_BKDOK_8188F)
+#endif
+
+#endif /* __RTL8188F_SPEC_H__ */
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/include/rtl8188f_sreset.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/rtl8188f_sreset.h
--- linux-5.6.3/3rdparty/rtl8821ce/include/rtl8188f_sreset.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/rtl8188f_sreset.h	2020-04-10 16:35:06.848661561 +0300
@@ -0,0 +1,24 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#ifndef _RTL8188F_SRESET_H_
+#define _RTL8188F_SRESET_H_
+
+#include <rtw_sreset.h>
+
+#ifdef DBG_CONFIG_ERROR_DETECT
+extern void rtl8188f_sreset_xmit_status_check(_adapter *padapter);
+extern void rtl8188f_sreset_linked_status_check(_adapter *padapter);
+#endif
+#endif
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/include/rtl8188f_xmit.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/rtl8188f_xmit.h
--- linux-5.6.3/3rdparty/rtl8821ce/include/rtl8188f_xmit.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/rtl8188f_xmit.h	2020-04-10 16:35:06.848661561 +0300
@@ -0,0 +1,336 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#ifndef __RTL8188F_XMIT_H__
+#define __RTL8188F_XMIT_H__
+
+
+#define MAX_TID (15)
+
+
+#ifndef __INC_HAL8188FDESC_H
+#define __INC_HAL8188FDESC_H
+
+#define RX_STATUS_DESC_SIZE_8188F		24
+#define RX_DRV_INFO_SIZE_UNIT_8188F 8
+
+
+/* DWORD 0 */
+#define SET_RX_STATUS_DESC_PKT_LEN_8188F(__pRxStatusDesc, __Value)		SET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 0, 14, __Value)
+#define SET_RX_STATUS_DESC_EOR_8188F(__pRxStatusDesc, __Value)		SET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 30, 1, __Value)
+#define SET_RX_STATUS_DESC_OWN_8188F(__pRxStatusDesc, __Value)		SET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 31, 1, __Value)
+
+#define GET_RX_STATUS_DESC_PKT_LEN_8188F(__pRxStatusDesc)			LE_BITS_TO_4BYTE(__pRxStatusDesc, 0, 14)
+#define GET_RX_STATUS_DESC_CRC32_8188F(__pRxStatusDesc)		LE_BITS_TO_4BYTE(__pRxStatusDesc, 14, 1)
+#define GET_RX_STATUS_DESC_ICV_8188F(__pRxStatusDesc)				LE_BITS_TO_4BYTE(__pRxStatusDesc, 15, 1)
+#define GET_RX_STATUS_DESC_DRVINFO_SIZE_8188F(__pRxStatusDesc)		LE_BITS_TO_4BYTE(__pRxStatusDesc, 16, 4)
+#define GET_RX_STATUS_DESC_SECURITY_8188F(__pRxStatusDesc)			LE_BITS_TO_4BYTE(__pRxStatusDesc, 20, 3)
+#define GET_RX_STATUS_DESC_QOS_8188F(__pRxStatusDesc)				LE_BITS_TO_4BYTE(__pRxStatusDesc, 23, 1)
+#define GET_RX_STATUS_DESC_SHIFT_8188F(__pRxStatusDesc)		LE_BITS_TO_4BYTE(__pRxStatusDesc, 24, 2)
+#define GET_RX_STATUS_DESC_PHY_STATUS_8188F(__pRxStatusDesc)			LE_BITS_TO_4BYTE(__pRxStatusDesc, 26, 1)
+#define GET_RX_STATUS_DESC_SWDEC_8188F(__pRxStatusDesc)		LE_BITS_TO_4BYTE(__pRxStatusDesc, 27, 1)
+#define GET_RX_STATUS_DESC_LAST_SEG_8188F(__pRxStatusDesc)			LE_BITS_TO_4BYTE(__pRxStatusDesc, 28, 1)
+#define GET_RX_STATUS_DESC_FIRST_SEG_8188F(__pRxStatusDesc)		LE_BITS_TO_4BYTE(__pRxStatusDesc, 29, 1)
+#define GET_RX_STATUS_DESC_EOR_8188F(__pRxStatusDesc)				LE_BITS_TO_4BYTE(__pRxStatusDesc, 30, 1)
+#define GET_RX_STATUS_DESC_OWN_8188F(__pRxStatusDesc)				LE_BITS_TO_4BYTE(__pRxStatusDesc, 31, 1)
+
+/* DWORD 1 */
+#define GET_RX_STATUS_DESC_MACID_8188F(__pRxDesc)					LE_BITS_TO_4BYTE(__pRxDesc+4, 0, 7)
+#define GET_RX_STATUS_DESC_TID_8188F(__pRxDesc)					LE_BITS_TO_4BYTE(__pRxDesc+4, 8, 4)
+#define GET_RX_STATUS_DESC_AMSDU_8188F(__pRxDesc)					LE_BITS_TO_4BYTE(__pRxDesc+4, 13, 1)
+#define GET_RX_STATUS_DESC_RXID_MATCH_8188F(__pRxDesc)		LE_BITS_TO_4BYTE(__pRxDesc+4, 14, 1)
+#define GET_RX_STATUS_DESC_PAGGR_8188F(__pRxDesc)				LE_BITS_TO_4BYTE(__pRxDesc+4, 15, 1)
+#define GET_RX_STATUS_DESC_A1_FIT_8188F(__pRxDesc)				LE_BITS_TO_4BYTE(__pRxDesc+4, 16, 4)
+#define GET_RX_STATUS_DESC_CHKERR_8188F(__pRxDesc)				LE_BITS_TO_4BYTE(__pRxDesc+4, 20, 1)
+#define GET_RX_STATUS_DESC_IPVER_8188F(__pRxDesc)			LE_BITS_TO_4BYTE(__pRxDesc+4, 21, 1)
+#define GET_RX_STATUS_DESC_IS_TCPUDP__8188F(__pRxDesc)		LE_BITS_TO_4BYTE(__pRxDesc+4, 22, 1)
+#define GET_RX_STATUS_DESC_CHK_VLD_8188F(__pRxDesc)	LE_BITS_TO_4BYTE(__pRxDesc+4, 23, 1)
+#define GET_RX_STATUS_DESC_PAM_8188F(__pRxDesc)			LE_BITS_TO_4BYTE(__pRxDesc+4, 24, 1)
+#define GET_RX_STATUS_DESC_PWR_8188F(__pRxDesc)			LE_BITS_TO_4BYTE(__pRxDesc+4, 25, 1)
+#define GET_RX_STATUS_DESC_MORE_DATA_8188F(__pRxDesc)			LE_BITS_TO_4BYTE(__pRxDesc+4, 26, 1)
+#define GET_RX_STATUS_DESC_MORE_FRAG_8188F(__pRxDesc)			LE_BITS_TO_4BYTE(__pRxDesc+4, 27, 1)
+#define GET_RX_STATUS_DESC_TYPE_8188F(__pRxDesc)			LE_BITS_TO_4BYTE(__pRxDesc+4, 28, 2)
+#define GET_RX_STATUS_DESC_MC_8188F(__pRxDesc)				LE_BITS_TO_4BYTE(__pRxDesc+4, 30, 1)
+#define GET_RX_STATUS_DESC_BC_8188F(__pRxDesc)				LE_BITS_TO_4BYTE(__pRxDesc+4, 31, 1)
+
+/* DWORD 2 */
+#define GET_RX_STATUS_DESC_SEQ_8188F(__pRxStatusDesc)					LE_BITS_TO_4BYTE(__pRxStatusDesc+8, 0, 12)
+#define GET_RX_STATUS_DESC_FRAG_8188F(__pRxStatusDesc)				LE_BITS_TO_4BYTE(__pRxStatusDesc+8, 12, 4)
+#define GET_RX_STATUS_DESC_RX_IS_QOS_8188F(__pRxStatusDesc)		LE_BITS_TO_4BYTE(__pRxStatusDesc+8, 16, 1)
+#define GET_RX_STATUS_DESC_WLANHD_IV_LEN_8188F(__pRxStatusDesc)	LE_BITS_TO_4BYTE(__pRxStatusDesc+8, 18, 6)
+#define GET_RX_STATUS_DESC_RPT_SEL_8188F(__pRxStatusDesc)			LE_BITS_TO_4BYTE(__pRxStatusDesc+8, 28, 1)
+
+/* DWORD 3 */
+#define GET_RX_STATUS_DESC_RX_RATE_8188F(__pRxStatusDesc)				LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 0, 7)
+#define GET_RX_STATUS_DESC_HTC_8188F(__pRxStatusDesc)					LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 10, 1)
+#define GET_RX_STATUS_DESC_EOSP_8188F(__pRxStatusDesc)					LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 11, 1)
+#define GET_RX_STATUS_DESC_BSSID_FIT_8188F(__pRxStatusDesc)		LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 12, 2)
+#ifdef CONFIG_USB_RX_AGGREGATION
+#define GET_RX_STATUS_DESC_USB_AGG_PKTNUM_8188F(__pRxStatusDesc)	LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 16, 8)
+#endif
+#define GET_RX_STATUS_DESC_PATTERN_MATCH_8188F(__pRxDesc)			LE_BITS_TO_4BYTE(__pRxDesc+12, 29, 1)
+#define GET_RX_STATUS_DESC_UNICAST_MATCH_8188F(__pRxDesc)			LE_BITS_TO_4BYTE(__pRxDesc+12, 30, 1)
+#define GET_RX_STATUS_DESC_MAGIC_MATCH_8188F(__pRxDesc)		LE_BITS_TO_4BYTE(__pRxDesc+12, 31, 1)
+
+/* DWORD 6 */
+#define GET_RX_STATUS_DESC_SPLCP_8188F(__pRxDesc)			LE_BITS_TO_4BYTE(__pRxDesc+16, 0, 1)
+#define GET_RX_STATUS_DESC_LDPC_8188F(__pRxDesc)			LE_BITS_TO_4BYTE(__pRxDesc+16, 1, 1)
+#define GET_RX_STATUS_DESC_STBC_8188F(__pRxDesc)			LE_BITS_TO_4BYTE(__pRxDesc+16, 2, 1)
+#define GET_RX_STATUS_DESC_BW_8188F(__pRxDesc)			LE_BITS_TO_4BYTE(__pRxDesc+16, 4, 2)
+
+/* DWORD 5 */
+#define GET_RX_STATUS_DESC_TSFL_8188F(__pRxStatusDesc)				LE_BITS_TO_4BYTE(__pRxStatusDesc+20, 0, 32)
+
+#define GET_RX_STATUS_DESC_BUFF_ADDR_8188F(__pRxDesc)		LE_BITS_TO_4BYTE(__pRxDesc+24, 0, 32)
+#define GET_RX_STATUS_DESC_BUFF_ADDR64_8188F(__pRxDesc)		LE_BITS_TO_4BYTE(__pRxDesc+28, 0, 32)
+
+#define SET_RX_STATUS_DESC_BUFF_ADDR_8188F(__pRxDesc, __Value)	SET_BITS_TO_LE_4BYTE(__pRxDesc+24, 0, 32, __Value)
+
+
+/* Dword 0 */
+#define GET_TX_DESC_OWN_8188F(__pTxDesc)				LE_BITS_TO_4BYTE(__pTxDesc, 31, 1)
+
+#define SET_TX_DESC_PKT_SIZE_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 0, 16, __Value)
+#define SET_TX_DESC_OFFSET_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 16, 8, __Value)
+#define SET_TX_DESC_BMC_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 24, 1, __Value)
+#define SET_TX_DESC_HTC_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 25, 1, __Value)
+#define SET_TX_DESC_LAST_SEG_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 26, 1, __Value)
+#define SET_TX_DESC_FIRST_SEG_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 27, 1, __Value)
+#define SET_TX_DESC_LINIP_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 28, 1, __Value)
+#define SET_TX_DESC_NO_ACM_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 29, 1, __Value)
+#define SET_TX_DESC_GF_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 30, 1, __Value)
+#define SET_TX_DESC_OWN_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 31, 1, __Value)
+
+/* Dword 1 */
+#define SET_TX_DESC_MACID_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 0, 7, __Value)
+#define SET_TX_DESC_QUEUE_SEL_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 8, 5, __Value)
+#define SET_TX_DESC_RDG_NAV_EXT_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 13, 1, __Value)
+#define SET_TX_DESC_LSIG_TXOP_EN_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 14, 1, __Value)
+#define SET_TX_DESC_PIFS_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 15, 1, __Value)
+#define SET_TX_DESC_RATE_ID_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 16, 5, __Value)
+#define SET_TX_DESC_EN_DESC_ID_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 21, 1, __Value)
+#define SET_TX_DESC_SEC_TYPE_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 22, 2, __Value)
+#define SET_TX_DESC_PKT_OFFSET_8188F(__pTxDesc, __Value)		SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 24, 5, __Value)
+
+
+/* Dword 2 */
+#define SET_TX_DESC_PAID_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 0,  9, __Value)
+#define SET_TX_DESC_CCA_RTS_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 10, 2, __Value)
+#define SET_TX_DESC_AGG_ENABLE_8188F(__pTxDesc, __Value)		SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 12, 1, __Value)
+#define SET_TX_DESC_RDG_ENABLE_8188F(__pTxDesc, __Value)		SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 13, 1, __Value)
+#define SET_TX_DESC_AGG_BREAK_8188F(__pTxDesc, __Value)				SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 16, 1, __Value)
+#define SET_TX_DESC_MORE_FRAG_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 17, 1, __Value)
+#define SET_TX_DESC_RAW_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 18, 1, __Value)
+#define SET_TX_DESC_SPE_RPT_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 19, 1, __Value)
+#define SET_TX_DESC_AMPDU_DENSITY_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 20, 3, __Value)
+#define SET_TX_DESC_BT_INT_8188F(__pTxDesc, __Value)			SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 23, 1, __Value)
+#define SET_TX_DESC_GID_8188F(__pTxDesc, __Value)			SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 24, 6, __Value)
+
+
+/* Dword 3 */
+#define SET_TX_DESC_WHEADER_LEN_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 0, 4, __Value)
+#define SET_TX_DESC_CHK_EN_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 4, 1, __Value)
+#define SET_TX_DESC_EARLY_MODE_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 5, 1, __Value)
+#define SET_TX_DESC_HWSEQ_SEL_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 6, 2, __Value)
+#define SET_TX_DESC_USE_RATE_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 8, 1, __Value)
+#define SET_TX_DESC_DISABLE_RTS_FB_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 9, 1, __Value)
+#define SET_TX_DESC_DISABLE_FB_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 10, 1, __Value)
+#define SET_TX_DESC_CTS2SELF_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 11, 1, __Value)
+#define SET_TX_DESC_RTS_ENABLE_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 12, 1, __Value)
+#define SET_TX_DESC_HW_RTS_ENABLE_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 13, 1, __Value)
+#define SET_TX_DESC_NAV_USE_HDR_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 15, 1, __Value)
+#define SET_TX_DESC_USE_MAX_LEN_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 16, 1, __Value)
+#define SET_TX_DESC_MAX_AGG_NUM_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 17, 5, __Value)
+#define SET_TX_DESC_NDPA_8188F(__pTxDesc, __Value)		SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 22, 2, __Value)
+#define SET_TX_DESC_AMPDU_MAX_TIME_8188F(__pTxDesc, __Value)		SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 24, 8, __Value)
+
+/* Dword 4 */
+#define SET_TX_DESC_TX_RATE_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 0, 7, __Value)
+#define SET_TX_DESC_DATA_RATE_FB_LIMIT_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 8, 5, __Value)
+#define SET_TX_DESC_RTS_RATE_FB_LIMIT_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 13, 4, __Value)
+#define SET_TX_DESC_RETRY_LIMIT_ENABLE_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 17, 1, __Value)
+#define SET_TX_DESC_DATA_RETRY_LIMIT_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 18, 6, __Value)
+#define SET_TX_DESC_RTS_RATE_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 24, 5, __Value)
+
+
+/* Dword 5 */
+#define SET_TX_DESC_DATA_SC_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 0, 4, __Value)
+#define SET_TX_DESC_DATA_SHORT_8188F(__pTxDesc, __Value)	SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 4, 1, __Value)
+#define SET_TX_DESC_DATA_BW_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 5, 2, __Value)
+#define SET_TX_DESC_DATA_LDPC_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 7, 1, __Value)
+#define SET_TX_DESC_DATA_STBC_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 8, 2, __Value)
+#define SET_TX_DESC_CTROL_STBC_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 10, 2, __Value)
+#define SET_TX_DESC_RTS_SHORT_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 12, 1, __Value)
+#define SET_TX_DESC_RTS_SC_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 13, 4, __Value)
+
+
+/* Dword 6 */
+#define SET_TX_DESC_SW_DEFINE_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 0, 12, __Value)
+#define SET_TX_DESC_MBSSID_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 12, 4, __Value)
+#define SET_TX_DESC_ANTSEL_A_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 16, 3, __Value)
+#define SET_TX_DESC_ANTSEL_B_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 19, 3, __Value)
+#define SET_TX_DESC_ANTSEL_C_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 22, 3, __Value)
+#define SET_TX_DESC_ANTSEL_D_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 25, 3, __Value)
+
+/* Dword 7 */
+#ifdef CONFIG_PCI_HCI
+#define SET_TX_DESC_TX_BUFFER_SIZE_8188F(__pTxDesc, __Value)		SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 0, 16, __Value)
+#endif
+
+#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_USB_HCI)
+#define SET_TX_DESC_TX_DESC_CHECKSUM_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 0, 16, __Value)
+#endif
+#define SET_TX_DESC_USB_TXAGG_NUM_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 24, 8, __Value)
+#ifdef CONFIG_SDIO_HCI
+#define SET_TX_DESC_SDIO_TXSEQ_8188F(__pTxDesc, __Value)			SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 16, 8, __Value)
+#endif
+
+/* Dword 8 */
+#define SET_TX_DESC_HWSEQ_EN_8188F(__pTxDesc, __Value)			SET_BITS_TO_LE_4BYTE(__pTxDesc+32, 15, 1, __Value)
+
+/* Dword 9 */
+#define SET_TX_DESC_SEQ_8188F(__pTxDesc, __Value)					SET_BITS_TO_LE_4BYTE(__pTxDesc+36, 12, 12, __Value)
+
+/* Dword 10 */
+#define SET_TX_DESC_TX_BUFFER_ADDRESS_8188F(__pTxDesc, __Value)	SET_BITS_TO_LE_4BYTE(__pTxDesc+40, 0, 32, __Value)
+#define GET_TX_DESC_TX_BUFFER_ADDRESS_8188F(__pTxDesc)	LE_BITS_TO_4BYTE(__pTxDesc+40, 0, 32)
+
+/* Dword 11 */
+#define SET_TX_DESC_NEXT_DESC_ADDRESS_8188F(__pTxDesc, __Value)	SET_BITS_TO_LE_4BYTE(__pTxDesc+48, 0, 32, __Value)
+
+
+#define SET_EARLYMODE_PKTNUM_8188F(__pAddr, __Value)					SET_BITS_TO_LE_4BYTE(__pAddr, 0, 4, __Value)
+#define SET_EARLYMODE_LEN0_8188F(__pAddr, __Value)					SET_BITS_TO_LE_4BYTE(__pAddr, 4, 15, __Value)
+#define SET_EARLYMODE_LEN1_1_8188F(__pAddr, __Value)					SET_BITS_TO_LE_4BYTE(__pAddr, 19, 13, __Value)
+#define SET_EARLYMODE_LEN1_2_8188F(__pAddr, __Value)					SET_BITS_TO_LE_4BYTE(__pAddr+4, 0, 2, __Value)
+#define SET_EARLYMODE_LEN2_8188F(__pAddr, __Value)					SET_BITS_TO_LE_4BYTE(__pAddr+4, 2, 15,	__Value)
+#define SET_EARLYMODE_LEN3_8188F(__pAddr, __Value)					SET_BITS_TO_LE_4BYTE(__pAddr+4, 17, 15, __Value)
+
+#endif
+/* -----------------------------------------------------------
+ *
+ *	Rate
+ *
+ * -----------------------------------------------------------
+ * CCK Rates, TxHT = 0 */
+#define DESC8188F_RATE1M				0x00
+#define DESC8188F_RATE2M				0x01
+#define DESC8188F_RATE5_5M				0x02
+#define DESC8188F_RATE11M				0x03
+
+/* OFDM Rates, TxHT = 0 */
+#define DESC8188F_RATE6M				0x04
+#define DESC8188F_RATE9M				0x05
+#define DESC8188F_RATE12M				0x06
+#define DESC8188F_RATE18M				0x07
+#define DESC8188F_RATE24M				0x08
+#define DESC8188F_RATE36M				0x09
+#define DESC8188F_RATE48M				0x0a
+#define DESC8188F_RATE54M				0x0b
+
+/* MCS Rates, TxHT = 1 */
+#define DESC8188F_RATEMCS0				0x0c
+#define DESC8188F_RATEMCS1				0x0d
+#define DESC8188F_RATEMCS2				0x0e
+#define DESC8188F_RATEMCS3				0x0f
+#define DESC8188F_RATEMCS4				0x10
+#define DESC8188F_RATEMCS5				0x11
+#define DESC8188F_RATEMCS6				0x12
+#define DESC8188F_RATEMCS7				0x13
+#define DESC8188F_RATEMCS8				0x14
+#define DESC8188F_RATEMCS9				0x15
+#define DESC8188F_RATEMCS10		0x16
+#define DESC8188F_RATEMCS11		0x17
+#define DESC8188F_RATEMCS12		0x18
+#define DESC8188F_RATEMCS13		0x19
+#define DESC8188F_RATEMCS14		0x1a
+#define DESC8188F_RATEMCS15		0x1b
+#define DESC8188F_RATEVHTSS1MCS0		0x2c
+#define DESC8188F_RATEVHTSS1MCS1		0x2d
+#define DESC8188F_RATEVHTSS1MCS2		0x2e
+#define DESC8188F_RATEVHTSS1MCS3		0x2f
+#define DESC8188F_RATEVHTSS1MCS4		0x30
+#define DESC8188F_RATEVHTSS1MCS5		0x31
+#define DESC8188F_RATEVHTSS1MCS6		0x32
+#define DESC8188F_RATEVHTSS1MCS7		0x33
+#define DESC8188F_RATEVHTSS1MCS8		0x34
+#define DESC8188F_RATEVHTSS1MCS9		0x35
+#define DESC8188F_RATEVHTSS2MCS0		0x36
+#define DESC8188F_RATEVHTSS2MCS1		0x37
+#define DESC8188F_RATEVHTSS2MCS2		0x38
+#define DESC8188F_RATEVHTSS2MCS3		0x39
+#define DESC8188F_RATEVHTSS2MCS4		0x3a
+#define DESC8188F_RATEVHTSS2MCS5		0x3b
+#define DESC8188F_RATEVHTSS2MCS6		0x3c
+#define DESC8188F_RATEVHTSS2MCS7		0x3d
+#define DESC8188F_RATEVHTSS2MCS8		0x3e
+#define DESC8188F_RATEVHTSS2MCS9		0x3f
+
+
+#define	RX_HAL_IS_CCK_RATE_8188F(pDesc)\
+	(GET_RX_STATUS_DESC_RX_RATE_8188F(pDesc) == DESC8188F_RATE1M || \
+	 GET_RX_STATUS_DESC_RX_RATE_8188F(pDesc) == DESC8188F_RATE2M || \
+	 GET_RX_STATUS_DESC_RX_RATE_8188F(pDesc) == DESC8188F_RATE5_5M || \
+	 GET_RX_STATUS_DESC_RX_RATE_8188F(pDesc) == DESC8188F_RATE11M)
+
+
+void rtl8188f_update_txdesc(struct xmit_frame *pxmitframe, u8 *pmem);
+void rtl8188f_fill_fake_txdesc(PADAPTER padapter, u8 *pDesc, u32 BufferLen, u8 IsPsPoll, u8 IsBTQosNull, u8 bDataFrame);
+#if defined(CONFIG_CONCURRENT_MODE)
+void fill_txdesc_force_bmc_camid(struct pkt_attrib *pattrib, u8 *ptxdesc);
+#endif
+
+#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
+s32 rtl8188fs_init_xmit_priv(PADAPTER padapter);
+void rtl8188fs_free_xmit_priv(PADAPTER padapter);
+s32 rtl8188fs_hal_xmit(PADAPTER padapter, struct xmit_frame *pxmitframe);
+s32 rtl8188fs_mgnt_xmit(PADAPTER padapter, struct xmit_frame *pmgntframe);
+s32	rtl8188fs_hal_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe);
+s32 rtl8188fs_xmit_buf_handler(PADAPTER padapter);
+thread_return rtl8188fs_xmit_thread(thread_context context);
+#define hal_xmit_handler rtl8188fs_xmit_buf_handler
+#endif
+
+#ifdef CONFIG_USB_HCI
+#ifdef CONFIG_XMIT_THREAD_MODE
+s32 rtl8188fu_xmit_buf_handler(PADAPTER padapter);
+#define hal_xmit_handler rtl8188fu_xmit_buf_handler
+#endif
+
+s32 rtl8188fu_init_xmit_priv(PADAPTER padapter);
+void rtl8188fu_free_xmit_priv(PADAPTER padapter);
+s32 rtl8188fu_hal_xmit(PADAPTER padapter, struct xmit_frame *pxmitframe);
+s32 rtl8188fu_mgnt_xmit(PADAPTER padapter, struct xmit_frame *pmgntframe);
+s32	 rtl8188fu_hal_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe);
+/* s32 rtl8812au_xmit_buf_handler(PADAPTER padapter); */
+void rtl8188fu_xmit_tasklet(void *priv);
+s32 rtl8188fu_xmitframe_complete(_adapter *padapter, struct xmit_priv *pxmitpriv, struct xmit_buf *pxmitbuf);
+void _dbg_dump_tx_info(_adapter	*padapter, int frame_tag, struct tx_desc *ptxdesc);
+#endif
+
+#ifdef CONFIG_PCI_HCI
+s32 rtl8188fe_init_xmit_priv(PADAPTER padapter);
+void rtl8188fe_free_xmit_priv(PADAPTER padapter);
+struct xmit_buf *rtl8188fe_dequeue_xmitbuf(struct rtw_tx_ring *ring);
+void	rtl8188fe_xmitframe_resume(_adapter *padapter);
+s32 rtl8188fe_hal_xmit(PADAPTER padapter, struct xmit_frame *pxmitframe);
+s32 rtl8188fe_mgnt_xmit(PADAPTER padapter, struct xmit_frame *pmgntframe);
+s32	rtl8188fe_hal_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe);
+void rtl8188fe_xmit_tasklet(void *priv);
+#endif
+
+u8	BWMapping_8188F(PADAPTER Adapter, struct pkt_attrib *pattrib);
+u8	SCMapping_8188F(PADAPTER Adapter, struct pkt_attrib	*pattrib);
+
+#endif
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/include/rtl8192e_cmd.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/rtl8192e_cmd.h
--- linux-5.6.3/3rdparty/rtl8821ce/include/rtl8192e_cmd.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/rtl8192e_cmd.h	2020-04-10 16:35:06.848661561 +0300
@@ -0,0 +1,147 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2012 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#ifndef __RTL8192E_CMD_H__
+#define __RTL8192E_CMD_H__
+
+typedef enum _RTL8192E_H2C_CMD {
+	H2C_8192E_RSVDPAGE	= 0x00,
+	H2C_8192E_MSRRPT	= 0x01,
+	H2C_8192E_SCAN		= 0x02,
+	H2C_8192E_KEEP_ALIVE_CTRL = 0x03,
+	H2C_8192E_DISCONNECT_DECISION = 0x04,
+	H2C_8192E_INIT_OFFLOAD = 0x06,
+	H2C_8192E_AP_OFFLOAD = 0x08,
+	H2C_8192E_BCN_RSVDPAGE = 0x09,
+	H2C_8192E_PROBERSP_RSVDPAGE = 0x0a,
+
+	H2C_8192E_AP_WOW_GPIO_CTRL = 0x13,
+
+	H2C_8192E_SETPWRMODE = 0x20,
+	H2C_8192E_PS_TUNING_PARA = 0x21,
+	H2C_8192E_PS_TUNING_PARA2 = 0x22,
+	H2C_8192E_PS_LPS_PARA = 0x23,
+	H2C_8192E_P2P_PS_OFFLOAD = 0x24,
+	H2C_8192E_SAP_PS = 0x26,
+	H2C_8192E_RA_MASK = 0x40,
+	H2C_8192E_RSSI_REPORT = 0x42,
+	H2C_8192E_RA_PARA_ADJUST = 0x46,
+
+	H2C_8192E_WO_WLAN = 0x80,
+	H2C_8192E_REMOTE_WAKE_CTRL = 0x81,
+	H2C_8192E_AOAC_GLOBAL_INFO = 0x82,
+	H2C_8192E_AOAC_RSVDPAGE = 0x83,
+
+	/* Not defined in new 88E H2C CMD Format */
+	H2C_8192E_SELECTIVE_SUSPEND_ROF_CMD,
+	H2C_8192E_P2P_PS_MODE,
+	H2C_8192E_PSD_RESULT,
+	MAX_8192E_H2CCMD
+} RTL8192E_H2C_CMD;
+
+struct cmd_msg_parm {
+	u8 eid; /* element id */
+	u8 sz; /* sz */
+	u8 buf[6];
+};
+
+enum {
+	PWRS
+};
+
+typedef struct _SETPWRMODE_PARM {
+	u8 Mode;/* 0:Active,1:LPS,2:WMMPS */
+	/* u8 RLBM:4; */ /* 0:Min,1:Max,2: User define */
+	u8 SmartPS_RLBM;/* LPS=0:PS_Poll,1:PS_Poll,2:NullData,WMM=0:PS_Poll,1:NullData */
+	u8 AwakeInterval;	/* unit: beacon interval */
+	u8 bAllQueueUAPSD;
+	u8 PwrState;/* AllON(0x0c),RFON(0x04),RFOFF(0x00) */
+} SETPWRMODE_PARM, *PSETPWRMODE_PARM;
+
+struct H2C_SS_RFOFF_PARAM {
+	u8 ROFOn; /* 1: on, 0:off */
+	u16 gpio_period; /* unit: 1024 us */
+} __attribute__((packed));
+
+
+typedef struct JOINBSSRPT_PARM_92E {
+	u8 OpMode;	/* RT_MEDIA_STATUS */
+#ifdef CONFIG_WOWLAN
+	u8 MacID;       /* MACID */
+#endif /* CONFIG_WOWLAN */
+} JOINBSSRPT_PARM_92E, *PJOINBSSRPT_PARM_92E;
+
+/* move to hal_com_h2c.h
+typedef struct _RSVDPAGE_LOC_92E {
+	u8 LocProbeRsp;
+	u8 LocPsPoll;
+	u8 LocNullData;
+	u8 LocQosNull;
+	u8 LocBTQosNull;
+} RSVDPAGE_LOC_92E, *PRSVDPAGE_LOC_92E;
+*/
+
+
+/* _SETPWRMODE_PARM */
+#define SET_8192E_H2CCMD_PWRMODE_PARM_MODE(__pH2CCmd, __Value)				SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
+#define SET_8192E_H2CCMD_PWRMODE_PARM_RLBM(__pH2CCmd, __Value)				SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 4, __Value)
+#define SET_8192E_H2CCMD_PWRMODE_PARM_SMART_PS(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 4, 4, __Value)
+#define SET_8192E_H2CCMD_PWRMODE_PARM_BCN_PASS_TIME(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value)
+#define SET_8192E_H2CCMD_PWRMODE_PARM_ALL_QUEUE_UAPSD(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 8, __Value)
+#define SET_8192E_H2CCMD_PWRMODE_PARM_BCN_EARLY_C2H_RPT(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 2, 1, __Value)
+#define SET_8192E_H2CCMD_PWRMODE_PARM_PWR_STATE(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 0, 8, __Value)
+#define GET_8192E_H2CCMD_PWRMODE_PARM_MODE(__pH2CCmd)						LE_BITS_TO_1BYTE(__pH2CCmd, 0, 8)
+
+/* _P2P_PS_OFFLOAD */
+#define SET_8192E_H2CCMD_P2P_PS_OFFLOAD_ENABLE(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 1, __Value)
+#define SET_8192E_H2CCMD_P2P_PS_OFFLOAD_ROLE(__pH2CCmd, __Value)				SET_BITS_TO_LE_1BYTE(__pH2CCmd, 1, 1, __Value)
+#define SET_8192E_H2CCMD_P2P_PS_OFFLOAD_CTWINDOW_EN(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd, 2, 1, __Value)
+#define SET_8192E_H2CCMD_P2P_PS_OFFLOAD_NOA0_EN(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE(__pH2CCmd, 3, 1, __Value)
+#define SET_8192E_H2CCMD_P2P_PS_OFFLOAD_NOA1_EN(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE(__pH2CCmd, 4, 1, __Value)
+#define SET_8192E_H2CCMD_P2P_PS_OFFLOAD_ALLSTASLEEP(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd, 5, 1, __Value)
+
+
+/* host message to firmware cmd */
+void rtl8192e_set_FwPwrMode_cmd(PADAPTER padapter, u8 Mode);
+void rtl8192e_set_FwJoinBssReport_cmd(PADAPTER padapter, u8 mstatus);
+s32 FillH2CCmd_8192E(PADAPTER padapter, u8 ElementID, u32 CmdLen, u8 *pCmdBuffer);
+u8 GetTxBufferRsvdPageNum8192E(_adapter *padapter, bool wowlan);
+/* u8 rtl8192c_set_FwSelectSuspend_cmd(PADAPTER padapter, u8 bfwpoll, u16 period); */
+s32 c2h_handler_8192e(_adapter *adapter, u8 id, u8 seq, u8 plen, u8 *payload);
+#ifdef CONFIG_BT_COEXIST
+	void rtl8192e_download_BTCoex_AP_mode_rsvd_page(PADAPTER padapter);
+#endif /* CONFIG_BT_COEXIST */
+#ifdef CONFIG_P2P_PS
+	void rtl8192e_set_p2p_ps_offload_cmd(PADAPTER padapter, u8 p2p_ps_state);
+#endif /* CONFIG_P2P */
+
+#ifdef CONFIG_TDLS
+	#ifdef CONFIG_TDLS_CH_SW
+		void rtl8192e_set_BcnEarly_C2H_Rpt_cmd(PADAPTER padapter, u8 enable);
+	#endif
+#endif
+
+/* / TX Feedback Content */
+#define	USEC_UNIT_FOR_8192E_C2H_TX_RPT_QUEUE_TIME			256
+
+#define	GET_8192E_C2H_TX_RPT_QUEUE_SELECT(_Header)			LE_BITS_TO_1BYTE((_Header + 0), 0, 5)
+#define	GET_8192E_C2H_TX_RPT_PKT_BROCAST(_Header)			LE_BITS_TO_1BYTE((_Header + 0), 5, 1)
+#define	GET_8192E_C2H_TX_RPT_LIFE_TIME_OVER(_Header)			LE_BITS_TO_1BYTE((_Header + 0), 6, 1)
+#define	GET_8192E_C2H_TX_RPT_RETRY_OVER(_Header)				LE_BITS_TO_1BYTE((_Header + 0), 7, 1)
+#define	GET_8192E_C2H_TX_RPT_MAC_ID(_Header)					LE_BITS_TO_1BYTE((_Header + 1), 0, 8)
+#define	GET_8192E_C2H_TX_RPT_DATA_RETRY_CNT(_Header)		LE_BITS_TO_1BYTE((_Header + 2), 0, 6)
+#define	GET_8192E_C2H_TX_RPT_QUEUE_TIME(_Header)				LE_BITS_TO_2BYTE((_Header + 3), 0, 16)	/* In unit of 256 microseconds. */
+#define	GET_8192E_C2H_TX_RPT_FINAL_DATA_RATE(_Header)		LE_BITS_TO_1BYTE((_Header + 5), 0, 8)
+
+#endif /* __RTL8192E_CMD_H__ */
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/include/rtl8192e_dm.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/rtl8192e_dm.h
--- linux-5.6.3/3rdparty/rtl8821ce/include/rtl8192e_dm.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/rtl8192e_dm.h	2020-04-10 16:35:06.848661561 +0300
@@ -0,0 +1,28 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2012 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#ifndef __RTL8192E_DM_H__
+#define __RTL8192E_DM_H__
+
+
+void rtl8192e_init_dm_priv(IN PADAPTER Adapter);
+void rtl8192e_deinit_dm_priv(IN PADAPTER Adapter);
+void rtl8192e_InitHalDm(IN PADAPTER Adapter);
+void rtl8192e_HalDmWatchDog(IN PADAPTER Adapter);
+
+/* VOID rtl8192c_dm_CheckTXPowerTracking(IN PADAPTER Adapter); */
+
+/* void rtl8192c_dm_RF_Saving(IN PADAPTER pAdapter, IN u8 bForceInNormal); */
+
+#endif
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/include/rtl8192e_hal.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/rtl8192e_hal.h
--- linux-5.6.3/3rdparty/rtl8821ce/include/rtl8192e_hal.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/rtl8192e_hal.h	2020-04-10 16:35:06.848661561 +0300
@@ -0,0 +1,330 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2012 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#ifndef __RTL8192E_HAL_H__
+#define __RTL8192E_HAL_H__
+
+/* #include "hal_com.h" */
+
+#include "hal_data.h"
+
+/* include HAL Related header after HAL Related compiling flags */
+#include "rtl8192e_spec.h"
+#include "rtl8192e_rf.h"
+#include "rtl8192e_dm.h"
+#include "rtl8192e_recv.h"
+#include "rtl8192e_xmit.h"
+#include "rtl8192e_cmd.h"
+#include "rtl8192e_led.h"
+#include "Hal8192EPwrSeq.h"
+#include "Hal8192EPhyReg.h"
+#include "Hal8192EPhyCfg.h"
+
+
+#ifdef DBG_CONFIG_ERROR_DETECT
+	#include "rtl8192e_sreset.h"
+#endif
+
+/* ---------------------------------------------------------------------
+ *		RTL8192E Power Configuration CMDs for PCIe interface
+ * --------------------------------------------------------------------- */
+#define Rtl8192E_NIC_PWR_ON_FLOW				rtl8192E_power_on_flow
+#define Rtl8192E_NIC_RF_OFF_FLOW				rtl8192E_radio_off_flow
+#define Rtl8192E_NIC_DISABLE_FLOW				rtl8192E_card_disable_flow
+#define Rtl8192E_NIC_ENABLE_FLOW				rtl8192E_card_enable_flow
+#define Rtl8192E_NIC_SUSPEND_FLOW				rtl8192E_suspend_flow
+#define Rtl8192E_NIC_RESUME_FLOW				rtl8192E_resume_flow
+#define Rtl8192E_NIC_PDN_FLOW					rtl8192E_hwpdn_flow
+#define Rtl8192E_NIC_LPS_ENTER_FLOW			rtl8192E_enter_lps_flow
+#define Rtl8192E_NIC_LPS_LEAVE_FLOW			rtl8192E_leave_lps_flow
+
+
+#if 1 /* download firmware related data structure */
+#define FW_SIZE_8192E			0x8000 /* Compatible with RTL8192e Maximal RAM code size 32k */
+#define FW_START_ADDRESS		0x1000
+#define FW_END_ADDRESS			0x5FFF
+
+
+#define IS_FW_HEADER_EXIST_8192E(_pFwHdr)	((GET_FIRMWARE_HDR_SIGNATURE_8192E(_pFwHdr) & 0xFFF0) == 0x92E0)
+
+
+
+typedef struct _RT_FIRMWARE_8192E {
+	FIRMWARE_SOURCE	eFWSource;
+#ifdef CONFIG_EMBEDDED_FWIMG
+	u8			*szFwBuffer;
+#else
+	u8			szFwBuffer[FW_SIZE_8192E];
+#endif
+	u32			ulFwLength;
+} RT_FIRMWARE_8192E, *PRT_FIRMWARE_8192E;
+
+/*
+ * This structure must be cared byte-ordering
+ *
+ * Added by tynli. 2009.12.04. */
+
+/* *****************************************************
+ *					Firmware Header(8-byte alinment required)
+ * *****************************************************
+ * --- LONG WORD 0 ---- */
+#define GET_FIRMWARE_HDR_SIGNATURE_8192E(__FwHdr)		LE_BITS_TO_4BYTE(__FwHdr, 0, 16) /* 92C0: test chip; 92C, 88C0: test chip; 88C1: MP A-cut; 92C1: MP A-cut */
+#define GET_FIRMWARE_HDR_CATEGORY_8192E(__FwHdr)		LE_BITS_TO_4BYTE(__FwHdr, 16, 8) /* AP/NIC and USB/PCI */
+#define GET_FIRMWARE_HDR_FUNCTION_8192E(__FwHdr)		LE_BITS_TO_4BYTE(__FwHdr, 24, 8) /* Reserved for different FW function indcation, for further use when driver needs to download different FW in different conditions */
+#define GET_FIRMWARE_HDR_VERSION_8192E(__FwHdr)			LE_BITS_TO_4BYTE(__FwHdr+4, 0, 16)/* FW Version */
+#define GET_FIRMWARE_HDR_SUB_VER_8192E(__FwHdr)			LE_BITS_TO_4BYTE(__FwHdr+4, 16, 8) /* FW Subversion, default 0x00 */
+#define GET_FIRMWARE_HDR_RSVD1_8192E(__FwHdr)			LE_BITS_TO_4BYTE(__FwHdr+4, 24, 8)
+
+/* --- LONG WORD 1 ---- */
+#define GET_FIRMWARE_HDR_MONTH_8192E(__FwHdr)			LE_BITS_TO_4BYTE(__FwHdr+8, 0, 8) /* Release time Month field */
+#define GET_FIRMWARE_HDR_DATE_8192E(__FwHdr)			LE_BITS_TO_4BYTE(__FwHdr+8, 8, 8) /* Release time Date field */
+#define GET_FIRMWARE_HDR_HOUR_8192E(__FwHdr)			LE_BITS_TO_4BYTE(__FwHdr+8, 16, 8)/* Release time Hour field */
+#define GET_FIRMWARE_HDR_MINUTE_8192E(__FwHdr)			LE_BITS_TO_4BYTE(__FwHdr+8, 24, 8)/* Release time Minute field */
+#define GET_FIRMWARE_HDR_ROMCODE_SIZE_8192E(__FwHdr)	LE_BITS_TO_4BYTE(__FwHdr+12, 0, 16)/* The size of RAM code */
+#define GET_FIRMWARE_HDR_RSVD2_8192E(__FwHdr)			LE_BITS_TO_4BYTE(__FwHdr+12, 16, 16)
+
+/* --- LONG WORD 2 ---- */
+#define GET_FIRMWARE_HDR_SVN_IDX_8192E(__FwHdr)			LE_BITS_TO_4BYTE(__FwHdr+16, 0, 32)/* The SVN entry index */
+#define GET_FIRMWARE_HDR_RSVD3_8192E(__FwHdr)			LE_BITS_TO_4BYTE(__FwHdr+20, 0, 32)
+
+/* --- LONG WORD 3 ---- */
+#define GET_FIRMWARE_HDR_RSVD4_8192E(__FwHdr)			LE_BITS_TO_4BYTE(__FwHdr+24, 0, 32)
+#define GET_FIRMWARE_HDR_RSVD5_8192E(__FwHdr)			LE_BITS_TO_4BYTE(__FwHdr+28, 0, 32)
+
+#endif /* download firmware related data structure */
+
+#define DRIVER_EARLY_INT_TIME_8192E		0x05
+#define BCN_DMA_ATIME_INT_TIME_8192E		0x02
+#define RX_DMA_SIZE_8192E					0x4000	/* 16K*/
+
+#ifdef CONFIG_WOWLAN
+	#define RESV_FMWF	(WKFMCAM_SIZE * MAX_WKFM_CAM_NUM) /* 16 entries, for each is 24 bytes*/
+#else
+	#define RESV_FMWF	0
+#endif
+
+#ifdef CONFIG_FW_C2H_DEBUG
+	#define RX_DMA_RESERVED_SIZE_8192E	0x100	/* 256B, reserved for c2h debug message*/
+#else
+	#define RX_DMA_RESERVED_SIZE_8192E	0x40	/* 64B, reserved for c2h event(16bytes) or ccx(8 Bytes)*/
+#endif
+#define MAX_RX_DMA_BUFFER_SIZE_8192E		(RX_DMA_SIZE_8192E-RX_DMA_RESERVED_SIZE_8192E)	/*RX 16K*/
+
+
+#define PAGE_SIZE_TX_92E	PAGE_SIZE_256
+
+/* For General Reserved Page Number(Beacon Queue is reserved page)
+ * if (CONFIG_2BCN_EN) Beacon:4, PS-Poll:1, Null Data:1,Prob Rsp:1,Qos Null Data:1
+ * Beacon: MAX_BEACON_LEN / PAGE_SIZE_TX_92E
+ * PS-Poll:1, Null Data:1,Prob Rsp:1,Qos Null Data:1,CTS-2-SELF / LTE QoS Null*/
+
+#define RSVD_PAGE_NUM_8192E		(MAX_BEACON_LEN / PAGE_SIZE_TX_92E + 6) /*0x08*/
+/* For WoWLan , more reserved page
+ * ARP Rsp:1, RWC:1, GTK Info:1,GTK RSP:2,GTK EXT MEM:2, AOAC rpt: 1,PNO: 6
+ * NS offload: 2 NDP info: 1
+ */
+#ifdef CONFIG_WOWLAN
+	#define WOWLAN_PAGE_NUM_8192E	0x0b
+#else
+	#define WOWLAN_PAGE_NUM_8192E	0x00
+#endif
+
+#ifdef CONFIG_PNO_SUPPORT
+	#undef WOWLAN_PAGE_NUM_8192E
+	#define WOWLAN_PAGE_NUM_8192E	0x0d
+#endif
+
+/* Note:
+Tx FIFO Size : 64KB
+Tx page Size : 256B
+Total page numbers : 256(0x100)
+*/
+
+#define	TOTAL_RSVD_PAGE_NUMBER_8192E	(RSVD_PAGE_NUM_8192E + WOWLAN_PAGE_NUM_8192E)
+
+#define	TOTAL_PAGE_NUMBER_8192E	(0x100)
+#define	TX_TOTAL_PAGE_NUMBER_8192E	(TOTAL_PAGE_NUMBER_8192E - TOTAL_RSVD_PAGE_NUMBER_8192E)
+
+#define	TX_PAGE_BOUNDARY_8192E	(TX_TOTAL_PAGE_NUMBER_8192E) /* beacon header start address */
+
+
+#define RSVD_PKT_LEN_92E	(TOTAL_RSVD_PAGE_NUMBER_8192E * PAGE_SIZE_TX_92E)
+
+#define TX_PAGE_LOAD_FW_BOUNDARY_8192E		0x47 /* 0xA5 */
+#define TX_PAGE_BOUNDARY_WOWLAN_8192E		0xE0
+
+/* For Normal Chip Setting
+ * (HPQ + LPQ + NPQ + PUBQ) shall be TX_TOTAL_PAGE_NUMBER_92C */
+
+#define NORMAL_PAGE_NUM_HPQ_8192E			0x10
+#define NORMAL_PAGE_NUM_LPQ_8192E			0x10
+#define NORMAL_PAGE_NUM_NPQ_8192E			0x10
+#define NORMAL_PAGE_NUM_EPQ_8192E			0x00
+
+
+/* Note: For WMM Normal Chip Setting ,modify later */
+#define WMM_NORMAL_PAGE_NUM_HPQ_8192E		NORMAL_PAGE_NUM_HPQ_8192E
+#define WMM_NORMAL_PAGE_NUM_LPQ_8192E		NORMAL_PAGE_NUM_LPQ_8192E
+#define WMM_NORMAL_PAGE_NUM_NPQ_8192E		NORMAL_PAGE_NUM_NPQ_8192E
+
+
+/* -------------------------------------------------------------------------
+ *	Chip specific
+ * ------------------------------------------------------------------------- */
+
+/* pic buffer descriptor */
+#define RTL8192EE_SEG_NUM			TX_BUFFER_SEG_NUM
+#define TX_DESC_NUM_92E			128
+#define RX_DESC_NUM_92E			128
+
+/* -------------------------------------------------------------------------
+ *	Channel Plan
+ * ------------------------------------------------------------------------- */
+
+#define		HWSET_MAX_SIZE_8192E			512
+
+#define		EFUSE_REAL_CONTENT_LEN_8192E	512
+
+#define		EFUSE_MAP_LEN_8192E			512
+#define		EFUSE_MAX_SECTION_8192E		64
+#define		EFUSE_MAX_WORD_UNIT_8192E		4
+#define		EFUSE_IC_ID_OFFSET_8192E		506	/* For some inferiority IC purpose. added by Roger, 2009.09.02. */
+#define		AVAILABLE_EFUSE_ADDR_8192E(addr)	(addr < EFUSE_REAL_CONTENT_LEN_8192E)
+/*
+ * <Roger_Notes> To prevent out of boundary programming case, leave 1byte and program full section
+ * 9bytes + 1byt + 5bytes and pre 1byte.
+ * For worst case:
+ * | 1byte|----8bytes----|1byte|--5bytes--|
+ * |         |            Reserved(14bytes)	      |
+ *   */
+#define		EFUSE_OOB_PROTECT_BYTES_8192E 		15	/* PG data exclude header, dummy 6 bytes frome CP test and reserved 1byte. */
+
+
+
+/* ********************************************************
+ *			EFUSE for BT definition
+ * ******************************************************** */
+#define		EFUSE_BT_REAL_BANK_CONTENT_LEN_8192E	512
+#define		EFUSE_BT_REAL_CONTENT_LEN_8192E			1024	/* 512*2 */
+#define		EFUSE_BT_MAP_LEN_8192E					1024	/* 1k bytes */
+#define		EFUSE_BT_MAX_SECTION_8192E				128		/* 1024/8 */
+
+#define		EFUSE_PROTECT_BYTES_BANK_8192E			16
+#define		EFUSE_MAX_BANK_8192E					3
+/* *********************************************************** */
+
+#define INCLUDE_MULTI_FUNC_BT(_Adapter)	(GET_HAL_DATA(_Adapter)->MultiFunc & RT_MULTI_FUNC_BT)
+#define INCLUDE_MULTI_FUNC_GPS(_Adapter)	(GET_HAL_DATA(_Adapter)->MultiFunc & RT_MULTI_FUNC_GPS)
+
+/* #define IS_MULTI_FUNC_CHIP(_Adapter)	(((((PHAL_DATA_TYPE)(_Adapter->HalData))->MultiFunc) & (RT_MULTI_FUNC_BT|RT_MULTI_FUNC_GPS)) ? _TRUE : _FALSE) */
+
+/* #define RT_IS_FUNC_DISABLED(__pAdapter, __FuncBits) ( (__pAdapter)->DisabledFunctions & (__FuncBits) ) */
+
+/* rtl8812_hal_init.c */
+void	_8051Reset8192E(PADAPTER padapter);
+s32	FirmwareDownload8192E(PADAPTER Adapter, BOOLEAN bUsedWoWLANFw);
+void	InitializeFirmwareVars8192E(PADAPTER padapter);
+
+s32	InitLLTTable8192E(PADAPTER padapter, u8 txpktbuf_bndy);
+
+/* EFuse */
+u8	GetEEPROMSize8192E(PADAPTER padapter);
+void	hal_InitPGData_8192E(PADAPTER padapter, u8 *PROMContent);
+void	Hal_EfuseParseIDCode8192E(PADAPTER padapter, u8 *hwinfo);
+void	Hal_ReadPROMVersion8192E(PADAPTER padapter, u8 *hwinfo, BOOLEAN AutoLoadFail);
+void	Hal_ReadPowerSavingMode8192E(PADAPTER padapter, u8	*hwinfo, BOOLEAN	AutoLoadFail);
+void	Hal_ReadTxPowerInfo8192E(PADAPTER padapter, u8 *hwinfo, BOOLEAN	AutoLoadFail);
+void	Hal_ReadBoardType8192E(PADAPTER pAdapter, u8 *hwinfo, BOOLEAN AutoLoadFail);
+void	Hal_ReadThermalMeter_8192E(PADAPTER	Adapter, u8 *PROMContent, BOOLEAN	AutoloadFail);
+void	Hal_ReadChannelPlan8192E(PADAPTER padapter, u8 *hwinfo, BOOLEAN AutoLoadFail);
+void	Hal_EfuseParseXtal_8192E(PADAPTER pAdapter, u8 *hwinfo, BOOLEAN AutoLoadFail);
+void	Hal_ReadAntennaDiversity8192E(PADAPTER pAdapter, u8 *PROMContent, BOOLEAN AutoLoadFail);
+void	Hal_ReadPAType_8192E(PADAPTER Adapter, u8 *PROMContent, BOOLEAN AutoloadFail);
+void	Hal_ReadAmplifierType_8192E(PADAPTER Adapter, u8 *PROMContent, BOOLEAN AutoloadFail);
+void	Hal_ReadRFEType_8192E(PADAPTER Adapter, u8 *PROMContent, BOOLEAN AutoloadFail);
+void	Hal_EfuseParseBTCoexistInfo8192E(PADAPTER Adapter, u8 *hwinfo, BOOLEAN AutoLoadFail);
+void	Hal_EfuseParseKFreeData_8192E(PADAPTER pAdapter, u8 *hwinfo, BOOLEAN AutoLoadFail);
+
+u8 Hal_CrystalAFEAdjust(_adapter *Adapter);
+
+BOOLEAN HalDetectPwrDownMode8192E(PADAPTER Adapter);
+
+#if defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN)
+	void Hal_DetectWoWMode(PADAPTER pAdapter);
+#endif /* CONFIG_WOWLAN */
+
+/***********************************************************/
+/* RTL8192E-MAC Setting */
+VOID _InitQueueReservedPage_8192E(IN  PADAPTER Adapter);
+VOID _InitQueuePriority_8192E(IN	PADAPTER Adapter);
+VOID _InitTxBufferBoundary_8192E(IN PADAPTER Adapter, IN u8 txpktbuf_bndy);
+VOID _InitPageBoundary_8192E(IN PADAPTER Adapter);
+/* VOID _InitTransferPageSize_8192E(IN PADAPTER Adapter); */
+VOID _InitDriverInfoSize_8192E(IN PADAPTER Adapter, IN u8 drvInfoSize);
+VOID _InitRDGSetting_8192E(PADAPTER Adapter);
+void _InitID_8192E(IN  PADAPTER Adapter);
+VOID _InitNetworkType_8192E(IN  PADAPTER Adapter);
+VOID _InitWMACSetting_8192E(IN PADAPTER Adapter);
+VOID _InitAdaptiveCtrl_8192E(IN  PADAPTER Adapter);
+VOID _InitEDCA_8192E(IN  PADAPTER Adapter);
+VOID _InitRetryFunction_8192E(IN  PADAPTER Adapter);
+VOID _BBTurnOnBlock_8192E(IN	PADAPTER Adapter);
+VOID _InitBeaconParameters_8192E(IN  PADAPTER Adapter);
+VOID _InitBeaconMaxError_8192E(
+	IN  PADAPTER	Adapter,
+	IN	BOOLEAN		InfraMode
+);
+void SetBeaconRelatedRegisters8192E(PADAPTER padapter);
+VOID hal_ReadRFType_8192E(PADAPTER	Adapter);
+/* RTL8192E-MAC Setting
+ ***********************************************************/
+
+u8 SetHwReg8192E(PADAPTER Adapter, u8 variable, u8 *val);
+void GetHwReg8192E(PADAPTER Adapter, u8 variable, u8 *val);
+u8
+SetHalDefVar8192E(
+	IN	PADAPTER				Adapter,
+	IN	HAL_DEF_VARIABLE		eVariable,
+	IN	PVOID					pValue
+);
+u8
+GetHalDefVar8192E(
+	IN	PADAPTER				Adapter,
+	IN	HAL_DEF_VARIABLE		eVariable,
+	IN	PVOID					pValue
+);
+
+void rtl8192e_set_hal_ops(struct hal_ops *pHalFunc);
+void init_hal_spec_8192e(_adapter *adapter);
+void rtl8192e_init_default_value(_adapter *padapter);
+
+void rtl8192e_start_thread(_adapter *padapter);
+void rtl8192e_stop_thread(_adapter *padapter);
+
+#ifdef CONFIG_PCI_HCI
+	BOOLEAN	InterruptRecognized8192EE(PADAPTER Adapter);
+	u16	get_txbd_rw_reg(u16 ff_hwaddr);
+#endif
+
+#ifdef CONFIG_SDIO_HCI
+	#ifdef CONFIG_SDIO_TX_ENABLE_AVAL_INT
+		void _init_available_page_threshold(PADAPTER padapter, u8 numHQ, u8 numNQ, u8 numLQ, u8 numPubQ);
+	#endif
+#endif
+
+#ifdef CONFIG_BT_COEXIST
+	void rtl8192e_combo_card_WifiOnlyHwInit(PADAPTER Adapter);
+#endif
+
+#endif /* __RTL8192E_HAL_H__ */
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/include/rtl8192e_led.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/rtl8192e_led.h
--- linux-5.6.3/3rdparty/rtl8821ce/include/rtl8192e_led.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/rtl8192e_led.h	2020-04-10 16:35:06.848661561 +0300
@@ -0,0 +1,36 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2012 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#ifndef __RTL8192E_LED_H__
+#define __RTL8192E_LED_H__
+
+#ifdef CONFIG_RTW_SW_LED
+/* ********************************************************************************
+ * Interface to manipulate LED objects.
+ * ******************************************************************************** */
+#ifdef CONFIG_USB_HCI
+	void rtl8192eu_InitSwLeds(PADAPTER padapter);
+	void rtl8192eu_DeInitSwLeds(PADAPTER padapter);
+#endif
+#ifdef CONFIG_PCI_HCI
+	void rtl8192ee_InitSwLeds(PADAPTER padapter);
+	void rtl8192ee_DeInitSwLeds(PADAPTER padapter);
+#endif
+#ifdef CONFIG_SDIO_HCI
+	void rtl8192es_InitSwLeds(PADAPTER padapter);
+	void rtl8192es_DeInitSwLeds(PADAPTER padapter);
+#endif
+
+#endif
+#endif/*CONFIG_RTW_SW_LED*/
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/include/rtl8192e_recv.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/rtl8192e_recv.h
--- linux-5.6.3/3rdparty/rtl8821ce/include/rtl8192e_recv.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/rtl8192e_recv.h	2020-04-10 16:35:06.848661561 +0300
@@ -0,0 +1,179 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2012 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#ifndef __RTL8192E_RECV_H__
+#define __RTL8192E_RECV_H__
+
+#if defined(CONFIG_USB_HCI)
+
+	#ifndef MAX_RECVBUF_SZ
+		#ifdef PLATFORM_OS_CE
+			#define MAX_RECVBUF_SZ (8192+1024) /* 8K+1k */
+		#else
+			#ifdef CONFIG_MINIMAL_MEMORY_USAGE
+				#define MAX_RECVBUF_SZ (4000) /* about 4K */
+			#else
+				#ifdef CONFIG_PREALLOC_RX_SKB_BUFFER
+					#define MAX_RECVBUF_SZ (rtw_rtkm_get_buff_size()) /*depend rtkm*/
+				#elif defined(CONFIG_PLATFORM_HISILICON)
+					#define MAX_RECVBUF_SZ (16384) /* 16k */
+				#else
+					#define MAX_RECVBUF_SZ (32768) /* 32k */
+				#endif
+				/* #define MAX_RECVBUF_SZ (20480) */ /* 20K */
+				/* #define MAX_RECVBUF_SZ (10240)  */ /* 10K */
+				/* #define MAX_RECVBUF_SZ (16384) */ /* 16k - 92E RX BUF :16K */
+				/* #define MAX_RECVBUF_SZ (8192+1024) */ /* 8K+1k		 */
+				#ifdef CONFIG_PLATFORM_NOVATEK_NT72668
+					#undef MAX_RECVBUF_SZ
+					#define MAX_RECVBUF_SZ (15360) /* 15k < 16k */
+				#endif /* CONFIG_PLATFORM_NOVATEK_NT72668 */
+			#endif
+		#endif
+	#endif /* !MAX_RECVBUF_SZ */
+
+#elif defined(CONFIG_PCI_HCI)
+	/* #ifndef CONFIG_MINIMAL_MEMORY_USAGE */
+	/*	#define MAX_RECVBUF_SZ (9100) */
+	/* #else */
+	#define MAX_RECVBUF_SZ (4000) /* about 4K
+	* #endif */
+
+
+#elif defined(CONFIG_SDIO_HCI)
+
+	#define MAX_RECVBUF_SZ (16384)
+
+#endif
+
+
+/* Rx smooth factor */
+#define Rx_Smooth_Factor (20)
+
+/* *************
+ * [1] Rx Buffer Descriptor (for PCIE) buffer descriptor architecture
+ * DWORD 0 */
+#define SET_RX_BUFFER_DESC_DATA_LENGTH_92E(__pRxStatusDesc, __Value)		SET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 0, 14, __Value)
+#define SET_RX_BUFFER_DESC_LS_92E(__pRxStatusDesc, __Value)	SET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 15, 1, __Value)
+#define SET_RX_BUFFER_DESC_FS_92E(__pRxStatusDesc, __Value)		SET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 16, 1, __Value)
+#define SET_RX_BUFFER_DESC_TOTAL_LENGTH_92E(__pRxStatusDesc, __Value)		SET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 16, 15, __Value)
+
+#define GET_RX_BUFFER_DESC_OWN_92E(__pRxStatusDesc)		LE_BITS_TO_4BYTE(__pRxStatusDesc, 31, 1)
+#define GET_RX_BUFFER_DESC_LS_92E(__pRxStatusDesc)		LE_BITS_TO_4BYTE(__pRxStatusDesc, 15, 1)
+#define GET_RX_BUFFER_DESC_FS_92E(__pRxStatusDesc)		LE_BITS_TO_4BYTE(__pRxStatusDesc, 16, 1)
+#define GET_RX_BUFFER_DESC_TOTAL_LENGTH_92E(__pRxStatusDesc)		LE_BITS_TO_4BYTE(__pRxStatusDesc, 16, 15)
+
+
+/* DWORD 1 */
+#define SET_RX_BUFFER_PHYSICAL_LOW_92E(__pRxStatusDesc, __Value)		SET_BITS_TO_LE_4BYTE(__pRxStatusDesc+4, 0, 32, __Value)
+#define GET_RX_BUFFER_PHYSICAL_LOW_92E(__pRxStatusDesc)		LE_BITS_TO_4BYTE(__pRxStatusDesc+4, 0, 32)
+
+/* DWORD 2 */
+#define SET_RX_BUFFER_PHYSICAL_HIGH_92E(__pRxStatusDesc, __Value)		SET_BITS_TO_LE_4BYTE(__pRxStatusDesc+8, 0, 32, __Value)
+
+/* *************
+ * [2] Rx Descriptor
+ * DWORD 0 */
+#define GET_RX_STATUS_DESC_PKT_LEN_92E(__pRxStatusDesc)			LE_BITS_TO_4BYTE(__pRxStatusDesc, 0, 14)
+#define GET_RX_STATUS_DESC_CRC32_92E(__pRxStatusDesc)			LE_BITS_TO_4BYTE(__pRxStatusDesc, 14, 1)
+#define GET_RX_STATUS_DESC_ICVERR_92E(__pRxStatusDesc)			LE_BITS_TO_4BYTE(__pRxStatusDesc, 15, 1)
+#define GET_RX_STATUS_DESC_DRVINFO_SIZE_92E(__pRxStatusDesc)		LE_BITS_TO_4BYTE(__pRxStatusDesc, 16, 4)
+#define GET_RX_STATUS_DESC_SECURITY_92E(__pRxStatusDesc)			LE_BITS_TO_4BYTE(__pRxStatusDesc, 20, 3)
+#define GET_RX_STATUS_DESC_QOS_92E(__pRxStatusDesc)				LE_BITS_TO_4BYTE(__pRxStatusDesc, 23, 1)
+#define GET_RX_STATUS_DESC_SHIFT_92E(__pRxStatusDesc)				LE_BITS_TO_4BYTE(__pRxStatusDesc, 24, 2)
+#define GET_RX_STATUS_DESC_PHY_STATUS_92E(__pRxStatusDesc)		LE_BITS_TO_4BYTE(__pRxStatusDesc, 26, 1)
+#define GET_RX_STATUS_DESC_SWDEC_92E(__pRxStatusDesc)			LE_BITS_TO_4BYTE(__pRxStatusDesc, 27, 1)
+#define GET_RX_STATUS_DESC_EOR_92E(__pRxStatusDesc)				LE_BITS_TO_4BYTE(__pRxStatusDesc, 30, 1)
+#define GET_RX_STATUS_DESC_OWN_92E(__pRxStatusDesc)				LE_BITS_TO_4BYTE(__pRxStatusDesc, 31, 1)
+
+
+#define SET_RX_STATUS_DESC_PKT_LEN_92E(__pRxStatusDesc, __Value)		SET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 0, 14, __Value)
+#define SET_RX_STATUS_DESC_EOR_92E(__pRxStatusDesc, __Value)		SET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 30, 1, __Value)
+#define SET_RX_STATUS_DESC_OWN_92E(__pRxStatusDesc, __Value)		SET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 31, 1, __Value)
+
+/* DWORD 1 */
+#define GET_RX_STATUS_DESC_MACID_92E(__pRxDesc)					LE_BITS_TO_4BYTE(__pRxDesc+4, 0, 7)
+#define GET_RX_STATUS_DESC_TID_92E(__pRxDesc)					LE_BITS_TO_4BYTE(__pRxDesc+4, 8, 4)
+#define GET_RX_STATUS_DESC_MACID_VLD_92E(__pRxDesc)				LE_BITS_TO_4BYTE(__pRxDesc+4, 12, 1)
+#define GET_RX_STATUS_DESC_AMSDU_92E(__pRxDesc)					LE_BITS_TO_4BYTE(__pRxDesc+4, 13, 1)
+#define GET_RX_STATUS_DESC_RXID_MATCH_92E(__pRxDesc)			LE_BITS_TO_4BYTE(__pRxDesc+4, 14, 1)
+#define GET_RX_STATUS_DESC_PAGGR_92E(__pRxStatusDesc)			LE_BITS_TO_4BYTE(__pRxStatusDesc+4, 15, 1)
+#define GET_RX_STATUS_DESC_A1_FITS_92E(__pRxStatusDesc)			LE_BITS_TO_4BYTE(__pRxStatusDesc+4, 16, 4)
+#define GET_RX_STATUS_DESC_TCPOFFLOAD_CHKERR_92E(__pRxStatusDesc)			LE_BITS_TO_4BYTE(__pRxStatusDesc+4, 20, 1)
+#define GET_RX_STATUS_DESC_TCPOFFLOAD_IPVER_92E(__pRxStatusDesc)			LE_BITS_TO_4BYTE(__pRxStatusDesc+4, 21, 1)
+#define GET_RX_STATUS_DESC_TCPOFFLOAD_IS_TCPUDP_92E(__pRxStatusDesc)		LE_BITS_TO_4BYTE(__pRxStatusDesc+4, 22, 1)
+#define GET_RX_STATUS_DESC_TCPOFFLOAD_CHK_VLD_92E(__pRxStatusDesc)		LE_BITS_TO_4BYTE(__pRxStatusDesc+4, 23, 1)
+#define GET_RX_STATUS_DESC_PAM_92E(__pRxStatusDesc)				LE_BITS_TO_4BYTE(__pRxStatusDesc+4, 24, 1)
+#define GET_RX_STATUS_DESC_PWR_92E(__pRxStatusDesc)				LE_BITS_TO_4BYTE(__pRxStatusDesc+4, 25, 1)
+#define GET_RX_STATUS_DESC_MORE_DATA_92E(__pRxStatusDesc)			LE_BITS_TO_4BYTE(__pRxStatusDesc+4, 26, 1)
+#define GET_RX_STATUS_DESC_MORE_FRAG_92E(__pRxStatusDesc)			LE_BITS_TO_4BYTE(__pRxStatusDesc+4, 27, 1)
+#define GET_RX_STATUS_DESC_TYPE_92E(__pRxStatusDesc)			LE_BITS_TO_4BYTE(__pRxStatusDesc+4, 28, 2)
+#define GET_RX_STATUS_DESC_MC_92E(__pRxStatusDesc)				LE_BITS_TO_4BYTE(__pRxStatusDesc+4, 30, 1)
+#define GET_RX_STATUS_DESC_BC_92E(__pRxStatusDesc)				LE_BITS_TO_4BYTE(__pRxStatusDesc+4, 31, 1)
+
+/* DWORD 2 */
+#define GET_RX_STATUS_DESC_SEQ_92E(__pRxStatusDesc)					LE_BITS_TO_4BYTE(__pRxStatusDesc+8, 0, 12)
+#define GET_RX_STATUS_DESC_FRAG_92E(__pRxStatusDesc)				LE_BITS_TO_4BYTE(__pRxStatusDesc+8, 12, 4)
+#define GET_RX_STATUS_DESC_RX_IS_QOS_92E(__pRxStatusDesc)			LE_BITS_TO_4BYTE(__pRxStatusDesc+8, 16, 1)
+
+#define GET_RX_STATUS_DESC_WLANHD_IV_LEN_92E(__pRxStatusDesc)			LE_BITS_TO_4BYTE(__pRxStatusDesc+8, 18, 6)
+#define GET_RX_STATUS_DESC_HWRSVD_92E(__pRxStatusDesc)			LE_BITS_TO_4BYTE(__pRxStatusDesc+8, 24, 4)
+#define GET_RX_STATUS_DESC_FCS_OK_92E(__pRxStatusDesc)			LE_BITS_TO_4BYTE(__pRxStatusDesc+8, 31, 1)
+#define GET_RX_STATUS_DESC_RPT_SEL_92E(__pRxStatusDesc)			LE_BITS_TO_4BYTE(__pRxStatusDesc+8, 28, 1)
+
+/* DWORD 3 */
+#define GET_RX_STATUS_DESC_RX_RATE_92E(__pRxStatusDesc)				LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 0, 7)
+#define GET_RX_STATUS_DESC_HTC_92E(__pRxStatusDesc)					LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 10, 1)
+#define GET_RX_STATUS_DESC_EOSP_92E(__pRxStatusDesc)					LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 11, 1)
+#define GET_RX_STATUS_DESC_BSSID_FIT_92E(__pRxStatusDesc)			LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 12, 2)
+#define GET_RX_STATUS_DESC_DMA_AGG_NUM_92E(__pRxStatusDesc)			LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 16, 8)
+
+#define GET_RX_STATUS_DESC_PATTERN_MATCH_92E(__pRxDesc)			LE_BITS_TO_4BYTE(__pRxDesc+12, 29, 1)
+#define GET_RX_STATUS_DESC_UNICAST_92E(__pRxDesc)			LE_BITS_TO_4BYTE(__pRxDesc+12, 30, 1)
+#define GET_RX_STATUS_DESC_MAGIC_WAKE_92E(__pRxDesc)			LE_BITS_TO_4BYTE(__pRxDesc+12, 31, 1)
+
+/* DWORD 6 */
+#define GET_RX_STATUS_DESC_SPLCP_92E(__pRxDesc)			LE_BITS_TO_4BYTE(__pRxDesc+16, 0, 1)
+#define GET_RX_STATUS_DESC_LDPC_92E(__pRxDesc)			LE_BITS_TO_4BYTE(__pRxDesc+16, 1, 1)
+#define GET_RX_STATUS_DESC_STBC_92E(__pRxDesc)			LE_BITS_TO_4BYTE(__pRxDesc+16, 2, 1)
+#define GET_RX_STATUS_DESC_BW_92E(__pRxDesc)			LE_BITS_TO_4BYTE(__pRxDesc+16, 4, 2)
+
+
+/* DWORD 5 */
+#define GET_RX_STATUS_DESC_TSFL_92E(__pRxStatusDesc)				LE_BITS_TO_4BYTE(__pRxStatusDesc+20, 0, 32)
+
+#define GET_RX_STATUS_DESC_BUFF_ADDR_92E(__pRxDesc)		LE_BITS_TO_4BYTE(__pRxDesc+24, 0, 32)
+#define GET_RX_STATUS_DESC_BUFF_ADDR64_92E(__pRxDesc)		LE_BITS_TO_4BYTE(__pRxDesc+28, 0, 32)
+
+
+#ifdef CONFIG_SDIO_HCI
+	s32 rtl8192es_init_recv_priv(PADAPTER padapter);
+	void rtl8192es_free_recv_priv(PADAPTER padapter);
+	s32 rtl8192es_recv_hdl(_adapter *padapter);
+#endif
+
+#ifdef CONFIG_USB_HCI
+	void rtl8192eu_init_recvbuf(_adapter *padapter, struct recv_buf *precvbuf);
+	s32 rtl8192eu_init_recv_priv(PADAPTER padapter);
+	void rtl8192eu_free_recv_priv(PADAPTER padapter);
+#endif
+
+#ifdef CONFIG_PCI_HCI
+	s32 rtl8192ee_init_recv_priv(PADAPTER padapter);
+	void rtl8192ee_free_recv_priv(PADAPTER padapter);
+#endif
+
+void rtl8192e_query_rx_desc_status(union recv_frame *precvframe, u8 *pdesc);
+
+#endif /* __RTL8192E_RECV_H__ */
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/include/rtl8192e_rf.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/rtl8192e_rf.h
--- linux-5.6.3/3rdparty/rtl8821ce/include/rtl8192e_rf.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/rtl8192e_rf.h	2020-04-10 16:35:06.848661561 +0300
@@ -0,0 +1,28 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2012 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#ifndef __RTL8192E_RF_H__
+#define __RTL8192E_RF_H__
+
+VOID
+PHY_RF6052SetBandwidth8192E(
+	IN	PADAPTER				Adapter,
+	IN	enum channel_width		Bandwidth);
+
+
+int
+PHY_RF6052_Config_8192E(
+	IN	PADAPTER	Adapter);
+
+#endif/* __RTL8192E_RF_H__ */
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/include/rtl8192e_spec.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/rtl8192e_spec.h
--- linux-5.6.3/3rdparty/rtl8821ce/include/rtl8192e_spec.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/rtl8192e_spec.h	2020-04-10 16:35:06.848661561 +0300
@@ -0,0 +1,313 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2012 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#ifndef __RTL8192E_SPEC_H__
+#define __RTL8192E_SPEC_H__
+
+#include <drv_conf.h>
+
+#define HAL_NAV_UPPER_UNIT_8192E		128		/* micro-second */
+
+/* ************************************************************
+ * 8192E Regsiter offset definition
+ * ************************************************************ */
+
+/* ************************************************************
+ *
+ * ************************************************************ */
+
+/* -----------------------------------------------------
+ *
+ *	0x0000h ~ 0x00FFh	System Configuration
+ *
+ * ----------------------------------------------------- */
+#define REG_SYS_SWR_CTRL1_8192E		0x0010	/* 1 Byte        */
+#define REG_SYS_SWR_CTRL2_8192E		0x0014	/* 1 Byte      */
+#define REG_AFE_CTRL1_8192E			0x0024
+#define REG_AFE_CTRL2_8192E			0x0028
+#define REG_AFE_CTRL3_8192E			0x002c
+
+#define REG_PAD_CTRL1_8192E			0x0064
+#define REG_SDIO_CTRL_8192E			0x0070
+#define REG_OPT_CTRL_8192E				0x0074
+#define REG_RF_B_CTRL_8192E			0x0076
+#define REG_AFE_CTRL4_8192E			0x0078
+#define REG_LDO_SWR_CTRL				0x007C
+#define REG_FW_DRV_MSG_8192E			0x0088
+#define REG_HMEBOX_E2_E3_8192E		0x008C
+#define REG_HIMR0_8192E				0x00B0
+#define REG_HISR0_8192E					0x00B4
+#define REG_HIMR1_8192E					0x00B8
+#define REG_HISR1_8192E					0x00BC
+
+#define REG_SYS_CFG1_8192E				0x00F0
+#define REG_SYS_CFG2_8192E				0x00FC
+/* -----------------------------------------------------
+ *
+ *	0x0100h ~ 0x01FFh	MACTOP General Configuration
+ *
+ * ----------------------------------------------------- */
+#define REG_PKTBUF_DBG_ADDR			(REG_PKTBUF_DBG_CTRL)
+#define REG_RXPKTBUF_DBG				(REG_PKTBUF_DBG_CTRL+2)
+#define REG_TXPKTBUF_DBG				(REG_PKTBUF_DBG_CTRL+3)
+#define REG_WOWLAN_WAKE_REASON		REG_MCUTST_WOWLAN
+
+#define REG_RSVD3_8192E					0x0168
+#define REG_C2HEVT_CMD_SEQ_88XX		0x01A1
+#define REG_C2hEVT_CMD_CONTENT_88XX	0x01A2
+#define REG_C2HEVT_CMD_LEN_88XX		0x01AE
+
+#define REG_HMEBOX_EXT0_8192E			0x01F0
+#define REG_HMEBOX_EXT1_8192E			0x01F4
+#define REG_HMEBOX_EXT2_8192E			0x01F8
+#define REG_HMEBOX_EXT3_8192E			0x01FC
+
+/* -----------------------------------------------------
+ *
+ *	0x0200h ~ 0x027Fh	TXDMA Configuration
+ *
+ * ----------------------------------------------------- */
+#define REG_DWBCN0_CTRL             0x0208
+#define REG_DWBCN1_CTRL             0x0228
+
+/* -----------------------------------------------------
+ *
+ *	0x0280h ~ 0x02FFh	RXDMA Configuration
+ *
+ * ----------------------------------------------------- */
+#define REG_RXDMA_8192E					0x0290
+#define REG_EARLY_MODE_CONTROL_8192E		0x02BC
+
+#define REG_RSVD5_8192E					0x02F0
+#define REG_RSVD6_8192E					0x02F4
+#define REG_RSVD7_8192E					0x02F8
+#define REG_RSVD8_8192E					0x02FC
+
+/* -----------------------------------------------------
+ *
+ *	0x0300h ~ 0x03FFh	PCIe
+ *
+ * ----------------------------------------------------- */
+#define	REG_PCIE_CTRL_REG_8192E			0x0300
+#define	REG_INT_MIG_8192E					0x0304	/* Interrupt Migration */
+#define	REG_BCNQ_TXBD_DESA_8192E		0x0308	/* TX Beacon Descriptor Address */
+#define	REG_MGQ_TXBD_DESA_8192E			0x0310	/* TX Manage Queue Descriptor Address */
+#define	REG_VOQ_TXBD_DESA_8192E			0x0318	/* TX VO Queue Descriptor Address */
+#define	REG_VIQ_TXBD_DESA_8192E			0x0320	/* TX VI Queue Descriptor Address */
+#define	REG_BEQ_TXBD_DESA_8192E			0x0328	/* TX BE Queue Descriptor Address */
+#define	REG_BKQ_TXBD_DESA_8192E			0x0330	/* TX BK Queue Descriptor Address */
+#define	REG_RXQ_RXBD_DESA_8192E			0x0338	/* RX Queue	Descriptor Address */
+#define	REG_HI0Q_TXBD_DESA_8192E			0x0340
+#define	REG_HI1Q_TXBD_DESA_8192E			0x0348
+#define	REG_HI2Q_TXBD_DESA_8192E			0x0350
+#define	REG_HI3Q_TXBD_DESA_8192E			0x0358
+#define	REG_HI4Q_TXBD_DESA_8192E			0x0360
+#define	REG_HI5Q_TXBD_DESA_8192E			0x0368
+#define	REG_HI6Q_TXBD_DESA_8192E			0x0370
+#define	REG_HI7Q_TXBD_DESA_8192E			0x0378
+#define	REG_MGQ_TXBD_NUM_8192E			0x0380
+#define	REG_RX_RXBD_NUM_8192E			0x0382
+#define	REG_VOQ_TXBD_NUM_8192E			0x0384
+#define	REG_VIQ_TXBD_NUM_8192E			0x0386
+#define	REG_BEQ_TXBD_NUM_8192E			0x0388
+#define	REG_BKQ_TXBD_NUM_8192E			0x038A
+#define	REG_HI0Q_TXBD_NUM_8192E			0x038C
+#define	REG_HI1Q_TXBD_NUM_8192E			0x038E
+#define	REG_HI2Q_TXBD_NUM_8192E			0x0390
+#define	REG_HI3Q_TXBD_NUM_8192E			0x0392
+#define	REG_HI4Q_TXBD_NUM_8192E			0x0394
+#define	REG_HI5Q_TXBD_NUM_8192E			0x0396
+#define	REG_HI6Q_TXBD_NUM_8192E			0x0398
+#define	REG_HI7Q_TXBD_NUM_8192E			0x039A
+#define	REG_TSFTIMER_HCI_8192E			0x039C
+
+/* Read Write Point */
+#define	REG_VOQ_TXBD_IDX_8192E			0x03A0
+#define	REG_VIQ_TXBD_IDX_8192E			0x03A4
+#define	REG_BEQ_TXBD_IDX_8192E			0x03A8
+#define	REG_BKQ_TXBD_IDX_8192E			0x03AC
+#define	REG_MGQ_TXBD_IDX_8192E			0x03B0
+#define	REG_RXQ_TXBD_IDX_8192E			0x03B4
+#define	REG_HI0Q_TXBD_IDX_8192E			0x03B8
+#define	REG_HI1Q_TXBD_IDX_8192E			0x03BC
+#define	REG_HI2Q_TXBD_IDX_8192E			0x03C0
+#define	REG_HI3Q_TXBD_IDX_8192E			0x03C4
+#define	REG_HI4Q_TXBD_IDX_8192E			0x03C8
+#define	REG_HI5Q_TXBD_IDX_8192E			0x03CC
+#define	REG_HI6Q_TXBD_IDX_8192E			0x03D0
+#define	REG_HI7Q_TXBD_IDX_8192E			0x03D4
+
+#define	REG_PCIE_HCPWM_8192EE			0x03D8 /* ?????? */
+#define	REG_PCIE_HRPWM_8192EE			0x03DC	/* PCIe RPWM */ /* ?????? */
+#define	REG_DBI_WDATA_V1_8192E			0x03E8
+#define	REG_DBI_RDATA_V1_8192E			0x03EC
+#define	REG_DBI_FLAG_V1_8192E				0x03F0
+#define	REG_MDIO_V1_8192E					0x3F4
+#define	REG_PCIE_MIX_CFG_8192E				0x3F8
+
+/* -----------------------------------------------------
+ *
+ *	0x0400h ~ 0x047Fh	Protocol Configuration
+ *
+ * ----------------------------------------------------- */
+#define REG_TXBF_CTRL_8192E				0x042C
+#define REG_ARFR0_8192E					0x0444
+#define REG_ARFR1_8192E					0x044C
+#define REG_CCK_CHECK_8192E				0x0454
+#define REG_AMPDU_MAX_TIME_8192E			0x0456
+#define REG_BCNQ1_BDNY_8192E				0x0457
+
+#define REG_AMPDU_MAX_LENGTH_8192E	0x0458
+#define REG_WMAC_LBK_BUF_HD_8192E			0x045D
+#define REG_NDPA_OPT_CTRL_8192E		0x045F
+#define REG_DATA_SC_8192E				0x0483
+#ifdef CONFIG_WOWLAN
+	#define REG_TXPKTBUF_IV_LOW             0x0484
+	#define REG_TXPKTBUF_IV_HIGH            0x0488
+#endif
+#define REG_ARFR2_8192E					0x048C
+#define REG_ARFR3_8192E					0x0494
+#define REG_TXRPT_START_OFFSET			0x04AC
+#define REG_AMPDU_BURST_MODE_8192E	0x04BC
+#define REG_HT_SINGLE_AMPDU_8192E		0x04C7
+#define REG_MACID_PKT_DROP0_8192E		0x04D0
+
+/* -----------------------------------------------------
+ *
+ *	0x0500h ~ 0x05FFh	EDCA Configuration
+ *
+ * ----------------------------------------------------- */
+#define REG_CTWND_8192E					0x0572
+#define REG_SECONDARY_CCA_CTRL_8192E	0x0577
+#define REG_SCH_TXCMD_8192E			0x05F8
+
+/* -----------------------------------------------------
+ *
+ *	0x0600h ~ 0x07FFh	WMAC Configuration
+ *
+ * ----------------------------------------------------- */
+#define REG_MAC_CR_8192E				0x0600
+
+#define REG_MAC_TX_SM_STATE_8192E		0x06B4
+
+/* Power */
+#define REG_BFMER0_INFO_8192E			0x06E4
+#define REG_BFMER1_INFO_8192E			0x06EC
+#define REG_CSI_RPT_PARAM_BW20_8192E	0x06F4
+#define REG_CSI_RPT_PARAM_BW40_8192E	0x06F8
+#define REG_CSI_RPT_PARAM_BW80_8192E	0x06FC
+
+/* Hardware Port 2 */
+#define REG_BFMEE_SEL_8192E				0x0714
+#define REG_SND_PTCL_CTRL_8192E		0x0718
+
+
+/* -----------------------------------------------------
+ *
+ *	Redifine register definition for compatibility
+ *
+ * ----------------------------------------------------- */
+
+/* TODO: use these definition when using REG_xxx naming rule.
+ * NOTE: DO NOT Remove these definition. Use later. */
+#define	ISR_8192E							REG_HISR0_8192E
+
+/* ----------------------------------------------------------------------------
+ * 8192E IMR/ISR bits						(offset 0xB0,  8bits)
+ * ---------------------------------------------------------------------------- */
+#define	IMR_DISABLED_8192E					0
+/* IMR DW0(0x00B0-00B3) Bit 0-31 */
+#define	IMR_TIMER2_8192E					BIT(31)		/* Timeout interrupt 2 */
+#define	IMR_TIMER1_8192E					BIT(30)		/* Timeout interrupt 1	 */
+#define	IMR_PSTIMEOUT_8192E				BIT(29)		/* Power Save Time Out Interrupt */
+#define	IMR_GTINT4_8192E					BIT(28)		/* When GTIMER4 expires, this bit is set to 1	 */
+#define	IMR_GTINT3_8192E					BIT(27)		/* When GTIMER3 expires, this bit is set to 1	 */
+#define	IMR_TXBCN0ERR_8192E				BIT(26)		/* Transmit Beacon0 Error			 */
+#define	IMR_TXBCN0OK_8192E					BIT(25)		/* Transmit Beacon0 OK			 */
+#define	IMR_TSF_BIT32_TOGGLE_8192E		BIT(24)		/* TSF Timer BIT(32) toggle indication interrupt			 */
+#define	IMR_BCNDMAINT0_8192E				BIT(20)		/* Beacon DMA Interrupt 0			 */
+#define	IMR_BCNDERR0_8192E					BIT(16)		/* Beacon Queue DMA OK0			 */
+#define	IMR_HSISR_IND_ON_INT_8192E		BIT(15)		/* HSISR Indicator (HSIMR & HSISR is true, this bit is set to 1) */
+#define	IMR_BCNDMAINT_E_8192E				BIT(14)		/* Beacon DMA Interrupt Extension for Win7			 */
+#define	IMR_ATIMEND_8192E					BIT(12)		/* CTWidnow End or ATIM Window End */
+#define	IMR_C2HCMD_8192E					BIT(10)		/* CPU to Host Command INT Status, Write 1 clear	 */
+#define	IMR_CPWM2_8192E					BIT(9)			/* CPU power Mode exchange INT Status, Write 1 clear	 */
+#define	IMR_CPWM_8192E						BIT(8)			/* CPU power Mode exchange INT Status, Write 1 clear	 */
+#define	IMR_HIGHDOK_8192E					BIT(7)			/* High Queue DMA OK	 */
+#define	IMR_MGNTDOK_8192E					BIT(6)			/* Management Queue DMA OK	 */
+#define	IMR_BKDOK_8192E					BIT(5)			/* AC_BK DMA OK		 */
+#define	IMR_BEDOK_8192E					BIT(4)			/* AC_BE DMA OK	 */
+#define	IMR_VIDOK_8192E					BIT(3)			/* AC_VI DMA OK		 */
+#define	IMR_VODOK_8192E					BIT(2)			/* AC_VO DMA OK	 */
+#define	IMR_RDU_8192E						BIT(1)			/* Rx Descriptor Unavailable	 */
+#define	IMR_ROK_8192E						BIT(0)			/* Receive DMA OK */
+
+/* IMR DW1(0x00B4-00B7) Bit 0-31 */
+#define	IMR_BCNDMAINT7_8192E				BIT(27)		/* Beacon DMA Interrupt 7 */
+#define	IMR_BCNDMAINT6_8192E				BIT(26)		/* Beacon DMA Interrupt 6 */
+#define	IMR_BCNDMAINT5_8192E				BIT(25)		/* Beacon DMA Interrupt 5 */
+#define	IMR_BCNDMAINT4_8192E				BIT(24)		/* Beacon DMA Interrupt 4 */
+#define	IMR_BCNDMAINT3_8192E				BIT(23)		/* Beacon DMA Interrupt 3 */
+#define	IMR_BCNDMAINT2_8192E				BIT(22)		/* Beacon DMA Interrupt 2 */
+#define	IMR_BCNDMAINT1_8192E				BIT(21)		/* Beacon DMA Interrupt 1 */
+#define	IMR_BCNDOK7_8192E					BIT(20)		/* Beacon Queue DMA OK Interrupt 7 */
+#define	IMR_BCNDOK6_8192E					BIT(19)		/* Beacon Queue DMA OK Interrupt 6 */
+#define	IMR_BCNDOK5_8192E					BIT(18)		/* Beacon Queue DMA OK Interrupt 5 */
+#define	IMR_BCNDOK4_8192E					BIT(17)		/* Beacon Queue DMA OK Interrupt 4 */
+#define	IMR_BCNDOK3_8192E					BIT(16)		/* Beacon Queue DMA OK Interrupt 3 */
+#define	IMR_BCNDOK2_8192E					BIT(15)		/* Beacon Queue DMA OK Interrupt 2 */
+#define	IMR_BCNDOK1_8192E					BIT(14)		/* Beacon Queue DMA OK Interrupt 1 */
+#define	IMR_ATIMEND_E_8192E				BIT(13)		/* ATIM Window End Extension for Win7 */
+#define	IMR_TXERR_8192E					BIT(11)		/* Tx Error Flag Interrupt Status, write 1 clear. */
+#define	IMR_RXERR_8192E					BIT(10)		/* Rx Error Flag INT Status, Write 1 clear */
+#define	IMR_TXFOVW_8192E					BIT(9)			/* Transmit FIFO Overflow */
+#define	IMR_RXFOVW_8192E					BIT(8)			/* Receive FIFO Overflow */
+
+/* ----------------------------------------------------------------------------
+ * 8192E Auto LLT bits						(offset 0x224,  8bits)
+ * ----------------------------------------------------------------------------
+ * 224 REG_AUTO_LLT
+ * move to hal_com_reg.h */
+
+/* ----------------------------------------------------------------------------
+ * 8192E Auto LLT bits						(offset 0x290,  32bits)
+ * ---------------------------------------------------------------------------- */
+#define BIT_DMA_MODE			BIT(1)
+#define BIT_USB_RXDMA_AGG_EN	BIT(31)
+
+/* ----------------------------------------------------------------------------
+ * 8192E REG_SYS_CFG1						(offset 0xF0,  32bits)
+ * ---------------------------------------------------------------------------- */
+#define BIT_SPSLDO_SEL			BIT(24)
+
+
+/* ----------------------------------------------------------------------------
+ * 8192E REG_CCK_CHECK						(offset 0x454,  8bits)
+ * ---------------------------------------------------------------------------- */
+#define BIT_BCN_PORT_SEL		BIT(5)
+
+/* ****************************************************************************
+ * Regsiter Bit and Content definition
+ * **************************************************************************** */
+
+/* 2 ACMHWCTRL 0x05C0 */
+#define	AcmHw_HwEn_8192E				BIT(0)
+#define	AcmHw_VoqEn_8192E				BIT(1)
+#define	AcmHw_ViqEn_8192E				BIT(2)
+#define	AcmHw_BeqEn_8192E				BIT(3)
+#define	AcmHw_VoqStatus_8192E			BIT(5)
+#define	AcmHw_ViqStatus_8192E			BIT(6)
+#define	AcmHw_BeqStatus_8192E			BIT(7)
+
+#endif /* __RTL8192E_SPEC_H__ */
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/include/rtl8192e_sreset.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/rtl8192e_sreset.h
--- linux-5.6.3/3rdparty/rtl8821ce/include/rtl8192e_sreset.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/rtl8192e_sreset.h	2020-04-10 16:35:06.848661561 +0300
@@ -0,0 +1,24 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2012 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#ifndef _RTL88812A_SRESET_H_
+#define _RTL8812A_SRESET_H_
+
+#include <rtw_sreset.h>
+
+#ifdef DBG_CONFIG_ERROR_DETECT
+	extern void rtl8192e_sreset_xmit_status_check(_adapter *padapter);
+	extern void rtl8192e_sreset_linked_status_check(_adapter *padapter);
+#endif
+#endif
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/include/rtl8192e_xmit.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/rtl8192e_xmit.h
--- linux-5.6.3/3rdparty/rtl8821ce/include/rtl8192e_xmit.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/rtl8192e_xmit.h	2020-04-10 16:35:06.849661608 +0300
@@ -0,0 +1,450 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2012 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#ifndef __RTL8192E_XMIT_H__
+#define __RTL8192E_XMIT_H__
+
+typedef struct txdescriptor_8192e {
+	/* Offset 0 */
+	u32 pktlen:16;
+	u32 offset:8;
+	u32 bmc:1;
+	u32 htc:1;
+	u32 ls:1;
+	u32 fs:1;
+	u32 linip:1;
+	u32 noacm:1;
+	u32 gf:1;
+	u32 own:1;
+
+	/* Offset 4 */
+	u32 macid:6;
+	u32 rsvd0406:2;
+	u32 qsel:5;
+	u32 rd_nav_ext:1;
+	u32 lsig_txop_en:1;
+	u32 pifs:1;
+	u32 rate_id:4;
+	u32 navusehdr:1;
+	u32 en_desc_id:1;
+	u32 sectype:2;
+	u32 rsvd0424:2;
+	u32 pkt_offset:5;	/* unit: 8 bytes */
+	u32 rsvd0431:1;
+
+	/* Offset 8 */
+	u32 rts_rc:6;
+	u32 data_rc:6;
+	u32 agg_en:1;
+	u32 rd_en:1;
+	u32 bar_rty_th:2;
+	u32 bk:1;
+	u32 morefrag:1;
+	u32 raw:1;
+	u32 ccx:1;
+	u32 ampdu_density:3;
+	u32 bt_null:1;
+	u32 ant_sel_a:1;
+	u32 ant_sel_b:1;
+	u32 tx_ant_cck:2;
+	u32 tx_antl:2;
+	u32 tx_ant_ht:2;
+
+	/* Offset 12 */
+	u32 nextheadpage:8;
+	u32 tailpage:8;
+	u32 seq:12;
+	u32 cpu_handle:1;
+	u32 tag1:1;
+	u32 trigger_int:1;
+	u32 hwseq_en:1;
+
+	/* Offset 16 */
+	u32 rtsrate:5;
+	u32 ap_dcfe:1;
+	u32 hwseq_sel:2;
+	u32 userate:1;
+	u32 disrtsfb:1;
+	u32 disdatafb:1;
+	u32 cts2self:1;
+	u32 rtsen:1;
+	u32 hw_rts_en:1;
+	u32 port_id:1;
+	u32 pwr_status:3;
+	u32 wait_dcts:1;
+	u32 cts2ap_en:1;
+	u32 data_sc:2;
+	u32 data_stbc:2;
+	u32 data_short:1;
+	u32 data_bw:1;
+	u32 rts_short:1;
+	u32 rts_bw:1;
+	u32 rts_sc:2;
+	u32 vcs_stbc:2;
+
+	/* Offset 20 */
+	u32 datarate:6;
+	u32 sgi:1;
+	u32 try_rate:1;
+	u32 data_ratefb_lmt:5;
+	u32 rts_ratefb_lmt:4;
+	u32 rty_lmt_en:1;
+	u32 data_rt_lmt:6;
+	u32 usb_txagg_num:8;
+
+	/* Offset 24 */
+	u32 txagg_a:5;
+	u32 txagg_b:5;
+	u32 use_max_len:1;
+	u32 max_agg_num:5;
+	u32 mcsg1_max_len:4;
+	u32 mcsg2_max_len:4;
+	u32 mcsg3_max_len:4;
+	u32 mcs7_sgi_max_len:4;
+
+	/* Offset 28 */
+	u32 checksum:16;	/* TxBuffSize(PCIe)/CheckSum(USB) */
+	u32 mcsg4_max_len:4;
+	u32 mcsg5_max_len:4;
+	u32 mcsg6_max_len:4;
+	u32 mcs15_sgi_max_len:4;
+} TXDESC_8192E, *PTXDESC_8192E;
+
+
+
+/* For 88e early mode */
+#define SET_EARLYMODE_PKTNUM(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr, 0, 3, __Value)
+#define SET_EARLYMODE_LEN0(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr, 4, 12, __Value)
+#define SET_EARLYMODE_LEN1(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr, 16, 12, __Value)
+#define SET_EARLYMODE_LEN2_1(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr, 28, 4, __Value)
+#define SET_EARLYMODE_LEN2_2(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr+4, 0, 8, __Value)
+#define SET_EARLYMODE_LEN3(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr+4, 8, 12, __Value)
+#define SET_EARLYMODE_LEN4(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr+4, 20, 12, __Value)
+
+/*
+ * defined for TX DESC Operation
+ *   */
+
+#define MAX_TID (15)
+
+/* OFFSET 0 */
+#define OFFSET_SZ	0
+#define OFFSET_SHT	16
+#define BMC		BIT(24)
+#define LSG		BIT(26)
+#define FSG		BIT(27)
+#define OWN		BIT(31)
+
+
+/* OFFSET 4 */
+#define PKT_OFFSET_SZ		0
+#define QSEL_SHT			8
+#define RATE_ID_SHT			16
+#define NAVUSEHDR			BIT(20)
+#define SEC_TYPE_SHT		22
+#define PKT_OFFSET_SHT		26
+
+/* OFFSET 8 */
+#define AGG_EN				BIT(12)
+#define AGG_BK					BIT(16)
+#define AMPDU_DENSITY_SHT	20
+#define ANTSEL_A			BIT(24)
+#define ANTSEL_B			BIT(25)
+#define TX_ANT_CCK_SHT		26
+#define TX_ANTL_SHT			28
+#define TX_ANT_HT_SHT		30
+
+/* OFFSET 12 */
+#define SEQ_SHT				16
+#define EN_HWSEQ			BIT(31)
+
+/* OFFSET 16 */
+#define	QOS                          BIT(6)
+#define	HW_SSN				BIT(7)
+#define	USERATE			BIT(8)
+#define	DISDATAFB			BIT(10)
+#define   CTS_2_SELF			BIT(11)
+#define	RTS_EN				BIT(12)
+#define	HW_RTS_EN			BIT(13)
+#define	DATA_SHORT			BIT(24)
+#define	PWR_STATUS_SHT	15
+#define	DATA_SC_SHT		20
+#define	DATA_BW			BIT(25)
+
+/* OFFSET 20 */
+#define	RTY_LMT_EN			BIT(17)
+
+
+/* OFFSET 20 */
+#define SGI					BIT(6)
+#define USB_TXAGG_NUM_SHT	24
+
+
+/* *****Tx Desc Buffer content */
+
+/* config element for each tx buffer
+ *
+#define SET_TXBUFFER_DESC_LEN_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc+(__Offset*16), 0, 16, __Valeu)
+#define SET_TXBUFFER_DESC_AMSDU_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc+(__Offset*16), 31, 1, __Valeu)
+#define SET_TXBUFFER_DESC_ADD_LOW_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc+(__Offset*16)+4, 0, 32, __Valeu)
+#define SET_TXBUFFER_DESC_ADD_HIGT_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc+(__Offset*16)+8, 0, 32, __Valeu)
+*/
+#define SET_TXBUFFER_DESC_LEN_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc+(__Offset*8), 0, 16, __Valeu)
+#define SET_TXBUFFER_DESC_AMSDU_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc+(__Offset*8), 31, 1, __Valeu)
+#define SET_TXBUFFER_DESC_ADD_LOW_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc+(__Offset*8)+4, 0, 32, __Valeu)
+#define SET_TXBUFFER_DESC_ADD_HIGT_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc+(__Offset*16)+8, 0, 32, __Valeu)
+
+
+/* Dword 0 */
+#define SET_TX_BUFF_DESC_LEN_0_92E(__pTxDesc, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc, 0, 14, __Valeu)
+#define SET_TX_BUFF_DESC_PSB_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 16, 15, __Value)
+#define SET_TX_BUFF_DESC_OWN_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 31, 1, __Value)
+/* Dword 1 */
+#define SET_TX_BUFF_DESC_ADDR_LOW_0_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 0, 32, __Value)
+#define GET_TX_DESC_TX_BUFFER_ADDRESS_92E(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc+4, 0, 32)
+
+
+/* Dword 2 */
+#define SET_TX_BUFF_DESC_ADDR_HIGH_0_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 0, 32, __Value)
+/* Dword 3, RESERVED */
+
+
+/* *****Tx Desc content
+ * Dword 0 */
+#define SET_TX_DESC_PKT_SIZE_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 0, 16, __Value)
+#define SET_TX_DESC_OFFSET_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 16, 8, __Value)
+#define SET_TX_DESC_BMC_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 24, 1, __Value)
+#define SET_TX_DESC_HTC_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 25, 1, __Value)
+#define SET_TX_DESC_LAST_SEG_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 26, 1, __Value)
+#define SET_TX_DESC_FIRST_SEG_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 27, 1, __Value)
+#define SET_TX_DESC_LINIP_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 28, 1, __Value)
+#define SET_TX_DESC_NO_ACM_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 29, 1, __Value)
+#define SET_TX_DESC_GF_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 30, 1, __Value)
+#define SET_TX_DESC_OWN_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 31, 1, __Value)
+#define GET_TX_DESC_OWN_92E(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc, 31, 1)
+
+/* Dword 1 */
+#define SET_TX_DESC_MACID_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 0, 7, __Value)
+#define SET_TX_DESC_QUEUE_SEL_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 8, 5, __Value)
+#define SET_TX_DESC_RDG_NAV_EXT_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 13, 1, __Value)
+#define SET_TX_DESC_LSIG_TXOP_EN_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 14, 1, __Value)
+#define SET_TX_DESC_PIFS_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 15, 1, __Value)
+#define SET_TX_DESC_RATE_ID_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 16, 5, __Value)
+#define SET_TX_DESC_EN_DESC_ID_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 21, 1, __Value)
+#define SET_TX_DESC_SEC_TYPE_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 22, 2, __Value)
+#define SET_TX_DESC_PKT_OFFSET_92E(__pTxDesc, __Value)		SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 24, 5, __Value)
+#define SET_TX_DESC_MORE_DATA_92E(__pTxDesc, __Value)		SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 29, 1, __Value)
+#define SET_TX_DESC_TXOP_PS_CAP_92E(__pTxDesc, __Value)		SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 30, 1, __Value)
+#define SET_TX_DESC_TXOP_PS_MODE_92E(__pTxDesc, __Value)		SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 31, 1, __Value)
+
+
+/* Dword 2 */
+#define SET_TX_DESC_PAID_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 0,  9, __Value)
+#define SET_TX_DESC_CCA_RTS_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 10, 2, __Value)
+#define SET_TX_DESC_AGG_ENABLE_92E(__pTxDesc, __Value)		SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 12, 1, __Value)
+#define SET_TX_DESC_RDG_ENABLE_92E(__pTxDesc, __Value)		SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 13, 1, __Value)
+#define SET_TX_DESC_NULL_0_92E(__pTxDesc, __Value)		SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 14, 1, __Value)
+#define SET_TX_DESC_NULL_1_92E(__pTxDesc, __Value)		SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 15, 1, __Value)
+#define SET_TX_DESC_BK_92E(__pTxDesc, __Value)				SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 16, 1, __Value)
+#define SET_TX_DESC_MORE_FRAG_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 17, 1, __Value)
+#define SET_TX_DESC_RAW_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 18, 1, __Value)
+#define GET_TX_DESC_MORE_FRAG_92E(__pTxDesc)				LE_BITS_TO_4BYTE(__pTxDesc+8, 17, 1)
+#define SET_TX_DESC_SPE_RPT_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 19, 1, __Value)
+#define SET_TX_DESC_AMPDU_DENSITY_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 20, 3, __Value)
+#define SET_TX_DESC_BT_NULL_92E(__pTxDesc, __Value)			SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 23, 1, __Value)
+#define SET_TX_DESC_GID_92E(__pTxDesc, __Value)			SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 24, 6, __Value)
+
+
+/* Dword 3 */
+#define SET_TX_DESC_WHEADER_LEN_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 0, 4, __Value)
+#define SET_TX_DESC_CHK_EN_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 4, 1, __Value)
+#define SET_TX_DESC_EARLY_RATE_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 5, 1, __Value)
+#define SET_TX_DESC_HWSEQ_SEL_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 6, 2, __Value)
+#define SET_TX_DESC_USE_RATE_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 8, 1, __Value)
+#define SET_TX_DESC_DISABLE_RTS_FB_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 9, 1, __Value)
+#define SET_TX_DESC_DISABLE_FB_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 10, 1, __Value)
+#define SET_TX_DESC_CTS2SELF_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 11, 1, __Value)
+#define SET_TX_DESC_RTS_ENABLE_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 12, 1, __Value)
+#define SET_TX_DESC_HW_RTS_ENABLE_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 13, 1, __Value)
+#define SET_TX_DESC_HW_PORT_ID_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 14, 1, __Value)
+#define SET_TX_DESC_NAV_USE_HDR_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 15, 1, __Value)
+#define SET_TX_DESC_USE_MAX_LEN_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 16, 1, __Value)
+#define SET_TX_DESC_MAX_AGG_NUM_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 17, 5, __Value)
+#define SET_TX_DESC_NDPA_92E(__pTxDesc, __Value)		SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 22, 2, __Value)
+#define SET_TX_DESC_AMPDU_MAX_TIME_92E(__pTxDesc, __Value)		SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 24, 8, __Value)
+
+/* Dword 4 */
+#define SET_TX_DESC_TX_RATE_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 0, 7, __Value)
+#define SET_TX_DESC_TRY_RATE_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 7, 1, __Value)
+#define SET_TX_DESC_DATA_RATE_FB_LIMIT_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 8, 5, __Value)
+#define SET_TX_DESC_RTS_RATE_FB_LIMIT_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 13, 4, __Value)
+#define SET_TX_DESC_RETRY_LIMIT_ENABLE_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 17, 1, __Value)
+#define SET_TX_DESC_DATA_RETRY_LIMIT_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 18, 6, __Value)
+#define SET_TX_DESC_RTS_RATE_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 24, 5, __Value)
+#define SET_TX_DESC_PCTS_ENABLE_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 29, 1, __Value)
+#define SET_TX_DESC_PCTS_MASK_IDX_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 30, 2, __Value)
+
+
+/* Dword 5 */
+#define SET_TX_DESC_DATA_SC_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 0, 4, __Value)
+#define SET_TX_DESC_DATA_SHORT_92E(__pTxDesc, __Value)	SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 4, 1, __Value)
+#define SET_TX_DESC_DATA_BW_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 5, 2, __Value)
+#define SET_TX_DESC_DATA_LDPC_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 7, 1, __Value)
+#define SET_TX_DESC_DATA_STBC_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 8, 2, __Value)
+#define SET_TX_DESC_VCS_STBC_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 10, 2, __Value)
+#define SET_TX_DESC_RTS_SHORT_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 12, 1, __Value)
+#define SET_TX_DESC_RTS_SC_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 13, 4, __Value)
+#define SET_TX_DESC_TX_ANT_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 24, 4, __Value)
+#define SET_TX_DESC_TX_POWER_0_PSET_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 28, 3, __Value)
+
+/* Dword 6 */
+#define SET_TX_DESC_SW_DEFINE_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 0, 12, __Value)
+#define SET_TX_DESC_MBSSID_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 12, 4, __Value)
+#define SET_TX_DESC_ANTSEL_A_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 16, 3, __Value)
+#define SET_TX_DESC_ANTSEL_B_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 19, 3, __Value)
+#define SET_TX_DESC_ANTSEL_C_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 22, 3, __Value)
+#define SET_TX_DESC_ANTSEL_D_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 25, 3, __Value)
+
+/* Dword 7 */
+#ifdef CONFIG_PCI_HCI
+	#define SET_TX_DESC_TX_BUFFER_SIZE_92E(__pTxDesc, __Value)		SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 0, 16, __Value)
+#endif
+
+#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_USB_HCI)
+	#define SET_TX_DESC_TX_DESC_CHECKSUM_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 0, 16, __Value)
+#endif
+#define SET_TX_DESC_USB_TXAGG_NUM_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 24, 8, __Value)
+
+
+/* #define SET_TX_DESC_HWSEQ_EN_92E(__pTxDesc, __Value)			SET_BITS_TO_LE_4BYTE(__pTxDesc+32, 15, 1, __Value) */
+/* Dword 8 */
+
+#define SET_TX_DESC_RTS_RC_92E(__pTxDesc, __Value)			SET_BITS_TO_LE_4BYTE(__pTxDesc+32, 0, 6, __Value)
+#define SET_TX_DESC_BAR_RTY_TH_92E(__pTxDesc, __Value)			SET_BITS_TO_LE_4BYTE(__pTxDesc+32, 6, 2, __Value)
+#define SET_TX_DESC_DATA_RC_92E(__pTxDesc, __Value)			SET_BITS_TO_LE_4BYTE(__pTxDesc+32, 8, 6, __Value)
+#define SET_TX_DESC_EN_HWSEQ_92E(__pTxDesc, __Value)			SET_BITS_TO_LE_4BYTE(__pTxDesc+32, 15, 1, __Value)
+#define SET_TX_DESC_NEXT_HEAD_PAGE_92E(__pTxDesc, __Value)(__pTxDesc, __Value)	SET_BITS_TO_LE_4BYTE(__pTxDesc+32, 16, 8, __Value)
+#define SET_TX_DESC_TAIL_PAGE_92E(__pTxDesc, __Value)(__pTxDesc, __Value)	SET_BITS_TO_LE_4BYTE(__pTxDesc+32, 24, 8, __Value)
+
+/* Dword 9 */
+#define SET_TX_DESC_PADDING_LENGTH_92E(__pTxDesc, __Value)					SET_BITS_TO_LE_4BYTE(__pTxDesc+36, 0, 11, __Value)
+#define SET_TX_DESC_TXBF_PATH_92E(__pTxDesc, __Value)					SET_BITS_TO_LE_4BYTE(__pTxDesc+36, 11, 1, __Value)
+#define SET_TX_DESC_SEQ_92E(__pTxDesc, __Value)					SET_BITS_TO_LE_4BYTE(__pTxDesc+36, 12, 12, __Value)
+#define SET_TX_DESC_FINAL_DATA_RATE_92E(__pTxDesc, __Value)					SET_BITS_TO_LE_4BYTE(__pTxDesc+36, 24, 8, __Value)
+
+
+#define SET_EARLYMODE_PKTNUM_92E(__pAddr, __Value)					SET_BITS_TO_LE_4BYTE(__pAddr, 0, 4, __Value)
+#define SET_EARLYMODE_LEN0_92E(__pAddr, __Value)					SET_BITS_TO_LE_4BYTE(__pAddr, 4, 15, __Value)
+#define SET_EARLYMODE_LEN1_1_92E(__pAddr, __Value)					SET_BITS_TO_LE_4BYTE(__pAddr, 19, 13, __Value)
+#define SET_EARLYMODE_LEN1_2_92E(__pAddr, __Value)					SET_BITS_TO_LE_4BYTE(__pAddr+4, 0, 2, __Value)
+#define SET_EARLYMODE_LEN2_92E(__pAddr, __Value)					SET_BITS_TO_LE_4BYTE(__pAddr+4, 2, 15,  __Value)
+#define SET_EARLYMODE_LEN3_92E(__pAddr, __Value)					SET_BITS_TO_LE_4BYTE(__pAddr+4, 17, 15, __Value)
+
+void rtl8192e_cal_txdesc_chksum(u8 *ptxdesc);
+
+#ifdef CONFIG_USB_HCI
+	s32 rtl8192eu_init_xmit_priv(PADAPTER padapter);
+	void rtl8192eu_free_xmit_priv(PADAPTER padapter);
+	s32 rtl8192eu_hal_xmit(PADAPTER padapter, struct xmit_frame *pxmitframe);
+	s32 rtl8192eu_mgnt_xmit(PADAPTER padapter, struct xmit_frame *pmgntframe);
+	s32	rtl8192eu_hal_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe);
+	s32 rtl8192eu_xmit_buf_handler(PADAPTER padapter);
+	#define hal_xmit_handler rtl8192eu_xmit_buf_handler
+	void rtl8192eu_xmit_tasklet(void *priv);
+	s32 rtl8192eu_xmitframe_complete(_adapter *padapter, struct xmit_priv *pxmitpriv, struct xmit_buf *pxmitbuf);
+#endif
+
+#ifdef CONFIG_PCI_HCI
+	s32 rtl8192ee_init_xmit_priv(PADAPTER padapter);
+	void rtl8192ee_free_xmit_priv(PADAPTER padapter);
+	struct xmit_buf *rtl8192ee_dequeue_xmitbuf(struct rtw_tx_ring *ring);
+	s32	rtl8192ee_hal_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe);
+	void	rtl8192ee_xmitframe_resume(_adapter *padapter);
+	s32 rtl8192ee_hal_xmit(PADAPTER padapter, struct xmit_frame *pxmitframe);
+	s32 rtl8192ee_mgnt_xmit(PADAPTER padapter, struct xmit_frame *pmgntframe);
+	void rtl8192ee_xmit_tasklet(void *priv);
+#endif
+
+#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
+	s32 rtl8192es_init_xmit_priv(PADAPTER padapter);
+	void rtl8192es_free_xmit_priv(PADAPTER padapter);
+
+	s32 rtl8192es_hal_xmit(PADAPTER padapter, struct xmit_frame *pxmitframe);
+	s32 rtl8192es_mgnt_xmit(PADAPTER padapter, struct xmit_frame *pmgntframe);
+	s32	rtl8192es_hal_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe);
+	thread_return rtl8192es_xmit_thread(thread_context context);
+	s32 rtl8192es_xmit_buf_handler(PADAPTER padapter);
+
+	#ifdef CONFIG_SDIO_TX_TASKLET
+		void rtl8192es_xmit_tasklet(void *priv);
+	#endif
+#endif
+
+struct txrpt_ccx_92e {
+	/* offset 0 */
+	u8 tag1:1;
+	u8 pkt_num:3;
+	u8 txdma_underflow:1;
+	u8 int_bt:1;
+	u8 int_tri:1;
+	u8 int_ccx:1;
+
+	/* offset 1 */
+	u8 mac_id:6;
+	u8 pkt_ok:1;
+	u8 bmc:1;
+
+	/* offset 2 */
+	u8 retry_cnt:6;
+	u8 lifetime_over:1;
+	u8 retry_over:1;
+
+	/* offset 3 */
+	u8 ccx_qtime0;
+	u8 ccx_qtime1;
+
+	/* offset 5 */
+	u8 final_data_rate;
+
+	/* offset 6 */
+	u8 sw1:4;
+	u8 qsel:4;
+
+	/* offset 7 */
+	u8 sw0;
+};
+
+#ifdef CONFIG_TX_EARLY_MODE
+	void UpdateEarlyModeInfo8192E(struct xmit_priv *pxmitpriv, struct xmit_buf *pxmitbuf);
+#endif
+s32	rtl8192e_init_xmit_priv(_adapter *padapter);
+void _dbg_dump_tx_info(_adapter	*padapter, int frame_tag, u8 *ptxdesc);
+
+void rtl8192e_fill_fake_txdesc(PADAPTER	padapter, u8 *pDesc, u32 BufferLen,
+			       u8 IsPsPoll, u8	IsBTQosNull, u8 bDataFrame);
+void rtl8192e_cal_txdesc_chksum(u8 *ptxdesc);
+
+u8	BWMapping_92E(PADAPTER Adapter, struct pkt_attrib *pattrib);
+u8	SCMapping_92E(PADAPTER Adapter, struct pkt_attrib	*pattrib);
+void fill_txdesc_phy(PADAPTER padapter, struct pkt_attrib *pattrib, u8 *ptxdesc);
+void fill_txdesc_vcs(struct pkt_attrib *pattrib, u8 *ptxdesc);
+#if defined(CONFIG_CONCURRENT_MODE)
+	void fill_txdesc_force_bmc_camid(struct pkt_attrib *pattrib, u8 *ptxdesc);
+#endif
+void fill_txdesc_bmc_tx_rate(struct pkt_attrib *pattrib, u8 *ptxdesc);
+
+void fill_txdesc_sectype(struct pkt_attrib *pattrib, u8 *ptxdesc);
+void rtl8192e_fixed_rate(_adapter *padapter, u8 *ptxdesc);
+
+#endif /* __RTL8192E_XMIT_H__ */
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/include/rtl8192f_cmd.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/rtl8192f_cmd.h
--- linux-5.6.3/3rdparty/rtl8821ce/include/rtl8192f_cmd.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/rtl8192f_cmd.h	2020-04-10 16:35:06.849661608 +0300
@@ -0,0 +1,194 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#ifndef __RTL8192F_CMD_H__
+#define __RTL8192F_CMD_H__
+
+/* ---------------------------------------------------------------------------------------------------------
+ * ----------------------------------    H2C CMD DEFINITION    ------------------------------------------------
+ * --------------------------------------------------------------------------------------------------------- */
+
+enum h2c_cmd_8192F {
+	/* Common Class: 000 */
+	H2C_8192F_RSVD_PAGE = 0x00,
+	H2C_8192F_MEDIA_STATUS_RPT = 0x01,
+	H2C_8192F_SCAN_ENABLE = 0x02,
+	H2C_8192F_KEEP_ALIVE = 0x03,
+	H2C_8192F_DISCON_DECISION = 0x04,	
+	H2C_8192F_PSD_OFFLOAD = 0x05,	
+	H2C_8192F_AP_OFFLOAD = 0x08,	
+	H2C_8192F_BCN_RSVDPAGE = 0x09,	
+	H2C_8192F_PROBERSP_RSVDPAGE = 0x0A,	
+	H2C_8192F_FCS_RSVDPAGE = 0x10,	
+	H2C_8192F_FCS_INFO = 0x11,	
+	H2C_8192F_AP_WOW_GPIO_CTRL = 0x13,
+
+	/* PoweSave Class: 001 */
+	H2C_8192F_SET_PWR_MODE = 0x20,
+	H2C_8192F_PS_TUNING_PARA = 0x21,
+	H2C_8192F_PS_TUNING_PARA2 = 0x22,
+	H2C_8192F_P2P_LPS_PARAM = 0x23,	
+	H2C_8192F_P2P_PS_OFFLOAD = 0x24,	
+	H2C_8192F_PS_SCAN_ENABLE = 0x25,	
+	H2C_8192F_SAP_PS_ = 0x26,
+	H2C_8192F_INACTIVE_PS_ = 0x27,/* Inactive_PS */
+	H2C_8192F_FWLPS_IN_IPS_ = 0x28,
+
+	/* Dynamic Mechanism Class: 010 */
+	H2C_8192F_MACID_CFG = 0x40,	
+	H2C_8192F_TXBF = 0x41,	
+	H2C_8192F_RSSI_SETTING = 0x42,	
+	H2C_8192F_AP_REQ_TXRPT = 0x43,	
+	H2C_8192F_INIT_RATE_COLLECT = 0x44,	
+	H2C_8192F_RA_PARA_ADJUST = 0x46,
+
+	/* BT Class: 011 */
+	H2C_8192F_B_TYPE_TDMA = 0x60,
+	H2C_8192F_BT_INFO = 0x61,
+	H2C_8192F_FORCE_BT_TXPWR = 0x62,
+	H2C_8192F_BT_IGNORE_WLANACT = 0x63,
+	H2C_8192F_DAC_SWING_VALUE = 0x64,
+	H2C_8192F_ANT_SEL_RSV = 0x65,
+	H2C_8192F_WL_OPMODE = 0x66,
+	H2C_8192F_BT_MP_OPER = 0x67,
+	H2C_8192F_BT_CONTROL = 0x68,
+	H2C_8192F_BT_WIFI_CTRL = 0x69,
+	H2C_8192F_BT_FW_PATCH = 0x6A,
+	H2C_8192F_BT_WLAN_CALIBRATION = 0x6D,
+
+	/* WOWLAN Class: 100 */
+	H2C_8192F_WOWLAN = 0x80,
+	H2C_8192F_REMOTE_WAKE_CTRL = 0x81,
+	H2C_8192F_AOAC_GLOBAL_INFO = 0x82,	
+	H2C_8192F_AOAC_RSVD_PAGE = 0x83,	
+	H2C_8192F_AOAC_RSVD_PAGE2 = 0x84,
+	H2C_8192F_D0_SCAN_OFFLOAD_CTRL = 0x85,
+	H2C_8192F_D0_SCAN_OFFLOAD_INFO = 0x86,
+	H2C_8192F_CHNL_SWITCH_OFFLOAD = 0x87,
+	H2C_8192F_P2P_OFFLOAD_RSVD_PAGE = 0x8A,	
+	H2C_8192F_P2P_OFFLOAD = 0x8B,
+
+	H2C_8192F_RESET_TSF = 0xC0,
+	H2C_8192F_MAXID,
+};
+
+/* ---------------------------------------------------------------------------------------------------------
+ * ----------------------------------    H2C CMD CONTENT    --------------------------------------------------
+ * ---------------------------------------------------------------------------------------------------------
+ * _RSVDPAGE_LOC_CMD_0x00 */
+#define SET_8192F_H2CCMD_RSVDPAGE_LOC_PROBE_RSP(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
+#define SET_8192F_H2CCMD_RSVDPAGE_LOC_PSPOLL(__pH2CCmd, __Value)				SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 8, __Value)
+#define SET_8192F_H2CCMD_RSVDPAGE_LOC_NULL_DATA(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value)
+#define SET_8192F_H2CCMD_RSVDPAGE_LOC_QOS_NULL_DATA(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 8, __Value)
+#define SET_8192F_H2CCMD_RSVDPAGE_LOC_BT_QOS_NULL_DATA(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 0, 8, __Value)
+
+/*_MEDIA_STATUS_RPT_PARM_CMD_0x01*/
+#define SET_8192F_H2CCMD_MSRRPT_PARM_OPMODE(__pH2CCmd, __Value)				SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 1, __Value)
+#define SET_8192F_H2CCMD_MSRRPT_PARM_MACID_IND(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE(__pH2CCmd, 1, 1, __Value)
+#define SET_8192F_H2CCMD_MSRRPT_PARM_MACID(__pH2CCmd, __Value)				SET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 0, 8, __Value)
+#define SET_8192F_H2CCMD_MSRRPT_PARM_MACID_END(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 0, 8, __Value)
+/* _PWR_MOD_CMD_0x20 */
+#define SET_8192F_H2CCMD_PWRMODE_PARM_MODE(__pH2CCmd, __Value)				SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
+#define SET_8192F_H2CCMD_PWRMODE_PARM_RLBM(__pH2CCmd, __Value)				SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 4, __Value)
+#define SET_8192F_H2CCMD_PWRMODE_PARM_SMART_PS(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 4, 4, __Value)
+#define SET_8192F_H2CCMD_PWRMODE_PARM_BCN_PASS_TIME(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value)
+#define SET_8192F_H2CCMD_PWRMODE_PARM_ALL_QUEUE_UAPSD(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 8, __Value)
+#define SET_8192F_H2CCMD_PWRMODE_PARM_BCN_EARLY_C2H_RPT(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 2, 1, __Value)
+#define SET_8192F_H2CCMD_PWRMODE_PARM_PWR_STATE(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 0, 8, __Value)
+
+#define GET_8192F_H2CCMD_PWRMODE_PARM_MODE(__pH2CCmd)					LE_BITS_TO_1BYTE(__pH2CCmd, 0, 8)
+
+/* _PS_TUNE_PARAM_CMD_0x21 */
+#define SET_8192F_H2CCMD_PSTUNE_PARM_BCN_TO_LIMIT(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
+#define SET_8192F_H2CCMD_PSTUNE_PARM_DTIM_TIMEOUT(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 0, 8, __Value)
+#define SET_8192F_H2CCMD_PSTUNE_PARM_ADOPT(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 0, 1, __Value)
+#define SET_8192F_H2CCMD_PSTUNE_PARM_PS_TIMEOUT(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 1, 7, __Value)
+#define SET_8192F_H2CCMD_PSTUNE_PARM_DTIM_PERIOD(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE(__pH2CCmd+3, 0, 8, __Value)
+
+/* _MACID_CFG_CMD_0x40 */
+#define SET_8192F_H2CCMD_MACID_CFG_MACID(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
+#define SET_8192F_H2CCMD_MACID_CFG_RAID(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 0, 5, __Value)
+#define SET_8192F_H2CCMD_MACID_CFG_SGI_EN(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 7, 1, __Value)
+#define SET_8192F_H2CCMD_MACID_CFG_BW(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 0, 2, __Value)
+#define SET_8192F_H2CCMD_MACID_CFG_NO_UPDATE(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 3, 1, __Value)
+#define SET_8192F_H2CCMD_MACID_CFG_VHT_EN(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 4, 2, __Value)
+#define SET_8192F_H2CCMD_MACID_CFG_DISPT(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 6, 1, __Value)
+#define SET_8192F_H2CCMD_MACID_CFG_DISRA(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 7, 1, __Value)
+#define SET_8192F_H2CCMD_MACID_CFG_RATE_MASK0(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd+3, 0, 8, __Value)
+#define SET_8192F_H2CCMD_MACID_CFG_RATE_MASK1(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd+4, 0, 8, __Value)
+#define SET_8192F_H2CCMD_MACID_CFG_RATE_MASK2(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd+5, 0, 8, __Value)
+#define SET_8192F_H2CCMD_MACID_CFG_RATE_MASK3(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd+6, 0, 8, __Value)
+
+/* _RSSI_SETTING_CMD_0x42 */
+#define SET_8192F_H2CCMD_RSSI_SETTING_MACID(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
+#define SET_8192F_H2CCMD_RSSI_SETTING_RSSI(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 0, 7, __Value)
+#define SET_8192F_H2CCMD_RSSI_SETTING_ULDL_STATE(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd+3, 0, 8, __Value)
+
+/* _AP_REQ_TXRPT_CMD_0x43 */
+#define SET_8192F_H2CCMD_APREQRPT_PARM_MACID1(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
+#define SET_8192F_H2CCMD_APREQRPT_PARM_MACID2(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 0, 8, __Value)
+
+/* _FORCE_BT_TXPWR_CMD_0x62 */
+#define SET_8192F_H2CCMD_BT_PWR_IDX(__pH2CCmd, __Value)							SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
+
+/* _FORCE_BT_MP_OPER_CMD_0x67 */
+#define SET_8192F_H2CCMD_BT_MPOPER_VER(__pH2CCmd, __Value)							SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 4, __Value)
+#define SET_8192F_H2CCMD_BT_MPOPER_REQNUM(__pH2CCmd, __Value)							SET_BITS_TO_LE_1BYTE(__pH2CCmd, 4, 4, __Value)
+#define SET_8192F_H2CCMD_BT_MPOPER_IDX(__pH2CCmd, __Value)							SET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 0, 8, __Value)
+#define SET_8192F_H2CCMD_BT_MPOPER_PARAM1(__pH2CCmd, __Value)							SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 0, 8, __Value)
+#define SET_8192F_H2CCMD_BT_MPOPER_PARAM2(__pH2CCmd, __Value)							SET_BITS_TO_LE_1BYTE(__pH2CCmd+3, 0, 8, __Value)
+#define SET_8192F_H2CCMD_BT_MPOPER_PARAM3(__pH2CCmd, __Value)							SET_BITS_TO_LE_1BYTE(__pH2CCmd+4, 0, 8, __Value)
+
+/* _BT_FW_PATCH_0x6A */
+#define SET_8192F_H2CCMD_BT_FW_PATCH_SIZE(__pH2CCmd, __Value)					SET_BITS_TO_LE_2BYTE((pu1Byte)(__pH2CCmd), 0, 16, __Value)
+#define SET_8192F_H2CCMD_BT_FW_PATCH_ADDR0(__pH2CCmd, __Value)					SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value)
+#define SET_8192F_H2CCMD_BT_FW_PATCH_ADDR1(__pH2CCmd, __Value)					SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 8, __Value)
+#define SET_8192F_H2CCMD_BT_FW_PATCH_ADDR2(__pH2CCmd, __Value)					SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 0, 8, __Value)
+#define SET_8192F_H2CCMD_BT_FW_PATCH_ADDR3(__pH2CCmd, __Value)					SET_BITS_TO_LE_1BYTE((__pH2CCmd)+5, 0, 8, __Value)
+
+/* ---------------------------------------------------------------------------------------------------------
+ * -------------------------------------------    Structure    --------------------------------------------------
+ * --------------------------------------------------------------------------------------------------------- */
+
+
+/* ---------------------------------------------------------------------------------------------------------
+ * ----------------------------------    Function Statement     --------------------------------------------------
+ * --------------------------------------------------------------------------------------------------------- */
+
+/* host message to firmware cmd */
+void rtl8192f_set_FwPwrMode_cmd(PADAPTER padapter, u8 Mode);
+void rtl8192f_set_FwJoinBssRpt_cmd(PADAPTER padapter, u8 mstatus);
+/* s32 rtl8192f__set_lowpwr_lps_cmd(PADAPTER padapter, u8 enable); */
+void rtl8192f_set_FwPsTuneParam_cmd(PADAPTER padapter);
+void rtl8192f_download_rsvd_page(PADAPTER padapter, u8 mstatus);
+#ifdef CONFIG_BT_COEXIST
+	void rtl8192f__download_BTCoex_AP_mode_rsvd_page(PADAPTER padapter);
+#endif /* CONFIG_BT_COEXIST */
+#ifdef CONFIG_P2P
+	void rtl8192f_set_p2p_ps_offload_cmd(PADAPTER padapter, u8 p2p_ps_state);
+#endif /* CONFIG_P2P */
+
+#ifdef CONFIG_TDLS
+#ifdef CONFIG_TDLS_CH_SW
+void rtl8192f_set_BcnEarly_C2H_Rpt_cmd(PADAPTER padapter, u8 enable);
+#endif
+#endif
+
+#ifdef CONFIG_P2P_WOWLAN
+	void rtl8192f_set_p2p_wowlan_offload_cmd(PADAPTER padapter);
+#endif
+
+s32 FillH2CCmd8192F(PADAPTER padapter, u8 ElementID, u32 CmdLen, u8 *pCmdBuffer);
+u8 GetTxBufferRsvdPageNum8192F(_adapter *padapter, bool wowlan);
+#endif
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/include/rtl8192f_dm.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/rtl8192f_dm.h
--- linux-5.6.3/3rdparty/rtl8821ce/include/rtl8192f_dm.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/rtl8192f_dm.h	2020-04-10 16:35:06.849661608 +0300
@@ -0,0 +1,28 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2012 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#ifndef __RTL8192F_DM_H__
+#define __RTL8192F_DM_H__
+
+
+void rtl8192f_init_dm_priv(IN PADAPTER Adapter);
+void rtl8192f_deinit_dm_priv(IN PADAPTER Adapter);
+void rtl8192f_InitHalDm(IN PADAPTER Adapter);
+void rtl8192f_HalDmWatchDog(IN PADAPTER Adapter);
+
+/* VOID rtl8192c_dm_CheckTXPowerTracking(IN PADAPTER Adapter); */
+
+/* void rtl8192c_dm_RF_Saving(IN PADAPTER pAdapter, IN u8 bForceInNormal); */
+
+#endif
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/include/rtl8192f_hal.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/rtl8192f_hal.h
--- linux-5.6.3/3rdparty/rtl8821ce/include/rtl8192f_hal.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/rtl8192f_hal.h	2020-04-10 16:35:06.849661608 +0300
@@ -0,0 +1,315 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#ifndef __RTL8192F_HAL_H__
+#define __RTL8192F_HAL_H__
+
+#include "hal_data.h"
+
+#include "rtl8192f_spec.h"
+#include "rtl8192f_rf.h"
+#include "rtl8192f_dm.h"
+#include "rtl8192f_recv.h"
+#include "rtl8192f_xmit.h"
+#include "rtl8192f_cmd.h"
+#include "rtl8192f_led.h"
+#include "Hal8192FPwrSeq.h"
+#include "Hal8192FPhyReg.h"
+#include "Hal8192FPhyCfg.h"
+#ifdef DBG_CONFIG_ERROR_DETECT
+#include "rtl8192f_sreset.h"
+#endif
+#ifdef CONFIG_LPS_POFF
+	#include "rtl8192f_lps_poff.h"
+#endif
+
+#define FW_8192F_SIZE		0x8000
+#define FW_8192F_START_ADDRESS	0x4000
+#define FW_8192F_END_ADDRESS	0x5000 /* brian_zhang@realsil.com.cn */
+
+#define IS_FW_HEADER_EXIST_8192F(_pFwHdr)\
+	((le16_to_cpu(_pFwHdr->Signature) & 0xFFF0) == 0x92F0)
+
+typedef struct _RT_FIRMWARE {
+	FIRMWARE_SOURCE	eFWSource;
+#ifdef CONFIG_EMBEDDED_FWIMG
+	u8			*szFwBuffer;
+#else
+	u8			szFwBuffer[FW_8192F_SIZE];
+#endif
+	u32			ulFwLength;
+} RT_FIRMWARE_8192F, *PRT_FIRMWARE_8192F;
+
+/*
+ * This structure must be cared byte-ordering
+ *
+ * Added by tynli. 2009.12.04. */
+typedef struct _RT_8192F_FIRMWARE_HDR {
+	/* 8-byte alinment required */
+
+	/* --- LONG WORD 0 ---- */
+	u16		Signature;	/* 92C0: test chip; 92C, 88C0: test chip; 88C1: MP A-cut; 92C1: MP A-cut */
+	u8		Category;	/* AP/NIC and USB/PCI */
+	u8		Function;	/* Reserved for different FW function indcation, for further use when driver needs to download different FW in different conditions */
+	u16		Version;		/* FW Version */
+	u16		Subversion;	/* FW Subversion, default 0x00 */
+
+	/* --- LONG WORD 1 ---- */
+	u8		Month;	/* Release time Month field */
+	u8		Date;	/* Release time Date field */
+	u8		Hour;	/* Release time Hour field */
+	u8		Minute;	/* Release time Minute field */
+	u16		RamCodeSize;	/* The size of RAM code */
+	u16		Rsvd2;
+
+	/* --- LONG WORD 2 ---- */
+	u32		SvnIdx;	/* The SVN entry index */
+	u32		Rsvd3;
+
+	/* --- LONG WORD 3 ---- */
+	u32		Rsvd4;
+	u32		Rsvd5;
+} RT_8192F_FIRMWARE_HDR, *PRT_8192F_FIRMWARE_HDR;
+#define DRIVER_EARLY_INT_TIME_8192F		0x05
+#define BCN_DMA_ATIME_INT_TIME_8192F		0x02
+/* for 8192F
+ * TX 64K, RX 16K, Page size 256B for TX*/
+#define PAGE_SIZE_TX_8192F			256
+#define PAGE_SIZE_RX_8192F			8
+#define TX_DMA_SIZE_8192F			0x10000/* 64K(TX) */
+#define RX_DMA_SIZE_8192F			0x4000/* 16K(RX) */
+#ifdef CONFIG_WOWLAN
+	#define RESV_FMWF	(WKFMCAM_SIZE * MAX_WKFM_CAM_NUM) /* 16 entries, for each is 24 bytes*/
+#else
+	#define RESV_FMWF	0
+#endif
+
+#ifdef CONFIG_FW_C2H_DEBUG
+	#define RX_DMA_RESERVED_SIZE_8192F	0x100	/* 256B, reserved for c2h debug message */
+#else
+	#define RX_DMA_RESERVED_SIZE_8192F	0xc0	/* 192B, reserved for tx report 24*8=192*/
+#endif
+#define RX_DMA_BOUNDARY_8192F\
+	(RX_DMA_SIZE_8192F - RX_DMA_RESERVED_SIZE_8192F - 1)
+
+
+/* Note: We will divide number of page equally for each queue other than public queue! */
+
+/* For General Reserved Page Number(Beacon Queue is reserved page)
+ * Beacon:MAX_BEACON_LEN/PAGE_SIZE_TX_8192F
+ * PS-Poll:1, Null Data:1,Qos Null Data:1,BT Qos Null Data:1,CTS-2-SELF,LTE QoS Null*/
+#define BCNQ_PAGE_NUM_8192F		(MAX_BEACON_LEN/PAGE_SIZE_TX_8192F + 6) /*0x08*/
+
+
+/* For WoWLan , more reserved page
+ * ARP Rsp:1, RWC:1, GTK Info:1,GTK RSP:2,GTK EXT MEM:2, AOAC rpt 1, PNO: 6
+ * NS offload: 2 NDP info: 1
+ */
+#ifdef CONFIG_WOWLAN
+	#define WOWLAN_PAGE_NUM_8192F	0x07
+#else
+	#define WOWLAN_PAGE_NUM_8192F	0x00
+#endif
+
+#ifdef CONFIG_PNO_SUPPORT
+	#undef WOWLAN_PAGE_NUM_8192F
+	#define WOWLAN_PAGE_NUM_8192F	0x15
+#endif
+
+#ifdef CONFIG_AP_WOWLAN
+	#define AP_WOWLAN_PAGE_NUM_8192F	0x02
+#endif
+
+#ifdef DBG_LA_MODE
+	#define LA_MODE_PAGE_NUM 0xE0
+#endif
+
+#define MAX_RX_DMA_BUFFER_SIZE_8192F	(RX_DMA_SIZE_8192F - RX_DMA_RESERVED_SIZE_8192F)
+
+#ifdef DBG_LA_MODE
+	#define TX_TOTAL_PAGE_NUMBER_8192F	(0xFF - LA_MODE_PAGE_NUM)
+#else
+	#define TX_TOTAL_PAGE_NUMBER_8192F	(0xFF - BCNQ_PAGE_NUM_8192F - WOWLAN_PAGE_NUM_8192F)
+#endif
+
+#define TX_PAGE_BOUNDARY_8192F		(TX_TOTAL_PAGE_NUMBER_8192F + 1)
+
+#define WMM_NORMAL_TX_TOTAL_PAGE_NUMBER_8192F \
+	TX_TOTAL_PAGE_NUMBER_8192F
+#define WMM_NORMAL_TX_PAGE_BOUNDARY_8192F \
+	(WMM_NORMAL_TX_TOTAL_PAGE_NUMBER_8192F + 1)
+
+/* For Normal Chip Setting
+ * (HPQ + LPQ + NPQ + PUBQ) shall be TX_TOTAL_PAGE_NUMBER_8192F */
+#define NORMAL_PAGE_NUM_HPQ_8192F		0x8
+#define NORMAL_PAGE_NUM_LPQ_8192F		0x8
+#define NORMAL_PAGE_NUM_NPQ_8192F		0x8
+#define NORMAL_PAGE_NUM_EPQ_8192F		0x00
+
+/* Note: For Normal Chip Setting, modify later */
+#define WMM_NORMAL_PAGE_NUM_HPQ_8192F		0x30
+#define WMM_NORMAL_PAGE_NUM_LPQ_8192F		0x20
+#define WMM_NORMAL_PAGE_NUM_NPQ_8192F		0x20
+#define WMM_NORMAL_PAGE_NUM_EPQ_8192F		0x00
+
+
+#include "HalVerDef.h"
+#include "hal_com.h"
+
+#define EFUSE_OOB_PROTECT_BYTES 56 /*0x1C8~0x1FF*/
+
+#define HAL_EFUSE_MEMORY
+#define HWSET_MAX_SIZE_8192F                512
+#define EFUSE_REAL_CONTENT_LEN_8192F        512
+#define EFUSE_MAP_LEN_8192F                 512
+#define EFUSE_MAX_SECTION_8192F            64
+
+/* For some inferiority IC purpose. added by Roger, 2009.09.02.*/
+#define EFUSE_IC_ID_OFFSET			506
+#define AVAILABLE_EFUSE_ADDR(addr)	(addr < EFUSE_REAL_CONTENT_LEN_8192F)
+
+#define EFUSE_ACCESS_ON		0x69
+#define EFUSE_ACCESS_OFF	0x00
+
+/* ********************************************************
+ *			EFUSE for BT definition
+ * ******************************************************** */
+#define BANK_NUM			1
+#define EFUSE_BT_REAL_BANK_CONTENT_LEN	512
+#define EFUSE_BT_REAL_CONTENT_LEN	1536/*512 * 3 */
+/*	(EFUSE_BT_REAL_BANK_CONTENT_LEN * BANK_NUM)*/
+#define EFUSE_BT_MAP_LEN		1024	/* 1k bytes */
+#define EFUSE_BT_MAX_SECTION		128 /* 1024/8 */
+#define EFUSE_PROTECT_BYTES_BANK	16
+
+typedef enum tag_Package_Definition {
+	PACKAGE_DEFAULT,
+	PACKAGE_QFN32,
+	PACKAGE_QFN40,
+	PACKAGE_QFN46
+} PACKAGE_TYPE_E;
+
+#define INCLUDE_MULTI_FUNC_BT(_Adapter) \
+	(GET_HAL_DATA(_Adapter)->MultiFunc & RT_MULTI_FUNC_BT)
+#define INCLUDE_MULTI_FUNC_GPS(_Adapter) \
+	(GET_HAL_DATA(_Adapter)->MultiFunc & RT_MULTI_FUNC_GPS)
+
+#ifdef CONFIG_FILE_FWIMG
+	extern char *rtw_fw_file_path;
+	extern char *rtw_fw_wow_file_path;
+	#ifdef CONFIG_MP_INCLUDED
+		extern char *rtw_fw_mp_bt_file_path;
+	#endif /* CONFIG_MP_INCLUDED */
+#endif /* CONFIG_FILE_FWIMG */
+
+/* rtl8192f_hal_init.c */
+s32 rtl8192f_FirmwareDownload(PADAPTER padapter, BOOLEAN  bUsedWoWLANFw);
+void rtl8192f_FirmwareSelfReset(PADAPTER padapter);
+void rtl8192f_InitializeFirmwareVars(PADAPTER padapter);
+
+void rtl8192f_InitAntenna_Selection(PADAPTER padapter);
+void rtl8192f_DeinitAntenna_Selection(PADAPTER padapter);
+void rtl8192f_CheckAntenna_Selection(PADAPTER padapter);
+void rtl8192f_init_default_value(PADAPTER padapter);
+
+s32 rtl8192f_InitLLTTable(PADAPTER padapter);
+
+s32 CardDisableHWSM(PADAPTER padapter, u8 resetMCU);
+s32 CardDisableWithoutHWSM(PADAPTER padapter);
+
+/* EFuse */
+u8 GetEEPROMSize8192F(PADAPTER padapter);
+void Hal_InitPGData(PADAPTER padapter, u8 *PROMContent);
+void Hal_EfuseParseIDCode(PADAPTER padapter, u8 *hwinfo);
+void Hal_EfuseParseTxPowerInfo_8192F(PADAPTER padapter,
+					u8 *PROMContent, BOOLEAN AutoLoadFail);
+/*
+void Hal_EfuseParseBTCoexistInfo_8192F(PADAPTER padapter,
+				       u8 *hwinfo, BOOLEAN AutoLoadFail);
+*/
+void Hal_EfuseParseEEPROMVer_8192F(PADAPTER padapter,
+				   u8 *hwinfo, BOOLEAN AutoLoadFail);
+void Hal_EfuseParseChnlPlan_8192F(PADAPTER padapter,
+				  u8 *hwinfo, BOOLEAN AutoLoadFail);
+void Hal_EfuseParseCustomerID_8192F(PADAPTER padapter,
+				    u8 *hwinfo, BOOLEAN AutoLoadFail);
+void Hal_EfuseParseAntennaDiversity_8192F(PADAPTER padapter,
+		u8 *hwinfo, BOOLEAN AutoLoadFail);
+void Hal_EfuseParseXtal_8192F(PADAPTER pAdapter,
+			      u8 *hwinfo, u8 AutoLoadFail);
+void Hal_EfuseParseThermalMeter_8192F(PADAPTER padapter,
+				      u8 *hwinfo, u8 AutoLoadFail);
+VOID Hal_EfuseParseVoltage_8192F(PADAPTER pAdapter,
+				 u8 *hwinfo, BOOLEAN	AutoLoadFail);
+VOID Hal_EfuseParseBoardType_8192F(PADAPTER Adapter,
+				   u8	*PROMContent, BOOLEAN AutoloadFail);
+u8	Hal_ReadRFEType_8192F(PADAPTER Adapter, u8 *PROMContent, BOOLEAN AutoloadFail);
+void rtl8192f_set_hal_ops(struct hal_ops *pHalFunc);
+void init_hal_spec_8192f(_adapter *adapter);
+u8 SetHwReg8192F(PADAPTER padapter, u8 variable, u8 *val);
+void GetHwReg8192F(PADAPTER padapter, u8 variable, u8 *val);
+u8 SetHalDefVar8192F(PADAPTER padapter, HAL_DEF_VARIABLE variable, void *pval);
+u8 GetHalDefVar8192F(PADAPTER padapter, HAL_DEF_VARIABLE variable, void *pval);
+
+/* register */
+void rtl8192f_InitBeaconParameters(PADAPTER padapter);
+void rtl8192f_InitBeaconMaxError(PADAPTER padapter, u8 InfraMode);
+
+void _InitMacAPLLSetting_8192F(PADAPTER Adapter);
+void _8051Reset8192F(PADAPTER padapter);
+#ifdef CONFIG_WOWLAN
+	void Hal_DetectWoWMode(PADAPTER pAdapter);
+#endif /* CONFIG_WOWLAN */
+
+void rtl8192f_start_thread(_adapter *padapter);
+void rtl8192f_stop_thread(_adapter *padapter);
+
+#if defined(CONFIG_CHECK_BT_HANG) && defined(CONFIG_BT_COEXIST)
+	void rtl8192fs_init_checkbthang_workqueue(_adapter *adapter);
+	void rtl8192fs_free_checkbthang_workqueue(_adapter *adapter);
+	void rtl8192fs_cancle_checkbthang_workqueue(_adapter *adapter);
+	void rtl8192fs_hal_check_bt_hang(_adapter *adapter);
+#endif
+
+#ifdef CONFIG_GPIO_WAKEUP
+	void HalSetOutPutGPIO(PADAPTER padapter, u8 index, u8 OutPutValue);
+#endif
+#ifdef CONFIG_MP_INCLUDED
+int FirmwareDownloadBT(IN PADAPTER Adapter, PRT_MP_FIRMWARE pFirmware);
+#endif
+void CCX_FwC2HTxRpt_8192f(PADAPTER padapter, u8 *pdata, u8 len);
+
+u8 MRateToHwRate8192F(u8 rate);
+u8 HwRateToMRate8192F(u8 rate);
+
+#if defined(CONFIG_CHECK_BT_HANG) && defined(CONFIG_BT_COEXIST)
+	void check_bt_status_work(void *data);
+#endif
+
+
+void rtl8192f_cal_txdesc_chksum(struct tx_desc *ptxdesc);
+
+#ifdef CONFIG_AMPDU_PRETX_CD
+void rtl8192f_pretx_cd_config(_adapter *adapter);
+#endif
+
+#ifdef CONFIG_PCI_HCI
+	BOOLEAN	InterruptRecognized8192FE(PADAPTER Adapter);
+	VOID	UpdateInterruptMask8192FE(PADAPTER Adapter, u32 AddMSR, u32 AddMSR1, u32 RemoveMSR, u32 RemoveMSR1);
+	VOID InitMAC_TRXBD_8192FE(PADAPTER Adapter);
+
+	u16 get_txbd_rw_reg(u16 ff_hwaddr);
+#endif
+
+#endif
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/include/rtl8192f_led.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/rtl8192f_led.h
--- linux-5.6.3/3rdparty/rtl8821ce/include/rtl8192f_led.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/rtl8192f_led.h	2020-04-10 16:35:06.849661608 +0300
@@ -0,0 +1,42 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#ifndef __RTL8192F_LED_H__
+#define __RTL8192F_LED_H__
+
+#include <drv_conf.h>
+#include <osdep_service.h>
+#include <drv_types.h>
+
+#ifdef CONFIG_RTW_SW_LED
+/* ********************************************************************************
+ * Interface to manipulate LED objects.
+ * ******************************************************************************** */
+#ifdef CONFIG_USB_HCI
+void rtl8192fu_InitSwLeds(PADAPTER padapter);
+void rtl8192fu_DeInitSwLeds(PADAPTER padapter);
+#endif
+
+#ifdef CONFIG_SDIO_HCI
+void rtl8192fs_InitSwLeds(PADAPTER padapter);
+void rtl8192fs_DeInitSwLeds(PADAPTER padapter);
+#endif
+
+#ifdef CONFIG_PCI_HCI
+void rtl8192fe_InitSwLeds(PADAPTER padapter);
+void rtl8192fe_DeInitSwLeds(PADAPTER padapter);
+#endif
+#endif /*#ifdef CONFIG_RTW_SW_LED*/
+
+#endif
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/include/rtl8192f_recv.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/rtl8192f_recv.h
--- linux-5.6.3/3rdparty/rtl8821ce/include/rtl8192f_recv.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/rtl8192f_recv.h	2020-04-10 16:35:06.849661608 +0300
@@ -0,0 +1,111 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#ifndef __RTL8192F_RECV_H__
+#define __RTL8192F_RECV_H__
+
+#define RECV_BLK_SZ 512
+#define RECV_BLK_CNT 16
+#define RECV_BLK_TH RECV_BLK_CNT
+
+#if defined(CONFIG_USB_HCI)
+
+	#ifndef MAX_RECVBUF_SZ
+		#ifdef PLATFORM_OS_CE
+			#define MAX_RECVBUF_SZ (8192+1024) /* 8K+1k */
+		#else
+			#ifndef CONFIG_MINIMAL_MEMORY_USAGE
+				/* #define MAX_RECVBUF_SZ (32768) */ /* 32k */
+				/* #define MAX_RECVBUF_SZ (16384) */ /* 16K */
+				/* #define MAX_RECVBUF_SZ (10240) */ /* 10K */
+				#ifdef CONFIG_PLATFORM_MSTAR
+					#define MAX_RECVBUF_SZ (8192) /* 8K */
+				#else
+					#define MAX_RECVBUF_SZ (32768) /* 32k */
+				#endif
+				/* #define MAX_RECVBUF_SZ (8192+1024) */ /* 8K+1k */
+			#else
+				#define MAX_RECVBUF_SZ (4000) /* about 4K */
+			#endif
+		#endif
+	#endif /* !MAX_RECVBUF_SZ */
+
+#elif defined(CONFIG_PCI_HCI)
+	#define MAX_RECVBUF_SZ (4000) /* about 4K */
+
+#elif defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
+
+	#define MAX_RECVBUF_SZ (RX_DMA_BOUNDARY_8192F + 1)
+
+#endif
+
+/* Rx smooth factor */
+#define	Rx_Smooth_Factor (20)
+
+#ifdef CONFIG_SDIO_HCI
+	#ifndef CONFIG_SDIO_RX_COPY
+		#undef MAX_RECVBUF_SZ
+		#define MAX_RECVBUF_SZ	(RX_DMA_SIZE_8192F - RX_DMA_RESERVED_SIZE_8192F)
+	#endif /* !CONFIG_SDIO_RX_COPY */
+#endif /* CONFIG_SDIO_HCI */
+
+/*-----------------------------------------------------------------*/
+/*	RTL8192F RX BUFFER DESC                                      */
+/*-----------------------------------------------------------------*/
+/*DWORD 0*/
+#define SET_RX_BUFFER_DESC_DATA_LENGTH_8192F(__pRxStatusDesc, __Value)		SET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 0, 14, __Value)
+#define SET_RX_BUFFER_DESC_LS_8192F(__pRxStatusDesc, __Value)	SET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 15, 1, __Value)
+#define SET_RX_BUFFER_DESC_FS_8192F(__pRxStatusDesc, __Value)		SET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 16, 1, __Value)
+#define SET_RX_BUFFER_DESC_TOTAL_LENGTH_8192F(__pRxStatusDesc, __Value)		SET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 16, 15, __Value)
+
+#define GET_RX_BUFFER_DESC_OWN_8192F(__pRxStatusDesc)		LE_BITS_TO_4BYTE(__pRxStatusDesc, 31, 1)
+#define GET_RX_BUFFER_DESC_LS_8192F(__pRxStatusDesc)		LE_BITS_TO_4BYTE(__pRxStatusDesc, 15, 1)
+#define GET_RX_BUFFER_DESC_FS_8192F(__pRxStatusDesc)		LE_BITS_TO_4BYTE(__pRxStatusDesc, 16, 1)
+#ifdef USING_RX_TAG
+	#define GET_RX_BUFFER_DESC_RX_TAG_8192F(__pRxStatusDesc)		LE_BITS_TO_4BYTE(__pRxStatusDesc, 16, 13)
+#else
+	#define GET_RX_BUFFER_DESC_TOTAL_LENGTH_8192F(__pRxStatusDesc)		LE_BITS_TO_4BYTE(__pRxStatusDesc, 16, 15)
+#endif
+
+/*DWORD 1*/
+#define SET_RX_BUFFER_PHYSICAL_LOW_8192F(__pRxStatusDesc, __Value)		SET_BITS_TO_LE_4BYTE(__pRxStatusDesc+4, 0, 32, __Value)
+
+/*DWORD 2*/
+#ifdef CONFIG_64BIT_DMA
+	#define SET_RX_BUFFER_PHYSICAL_HIGH_8192F(__pRxStatusDesc, __Value)		SET_BITS_TO_LE_4BYTE(__pRxStatusDesc+8, 0, 32, __Value)
+#else
+	#define SET_RX_BUFFER_PHYSICAL_HIGH_8192F(__pRxStatusDesc, __Value)
+#endif
+
+
+#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
+	s32 rtl8192fs_init_recv_priv(PADAPTER padapter);
+	void rtl8192fs_free_recv_priv(PADAPTER padapter);
+	s32 rtl8192fs_recv_hdl(_adapter *padapter);
+#endif
+
+#ifdef CONFIG_USB_HCI
+	int rtl8192fu_init_recv_priv(_adapter *padapter);
+	void rtl8192fu_free_recv_priv(_adapter *padapter);
+	void rtl8192fu_init_recvbuf(_adapter *padapter, struct recv_buf *precvbuf);
+#endif
+
+#ifdef CONFIG_PCI_HCI
+	s32 rtl8192fe_init_recv_priv(_adapter *padapter);
+	void rtl8192fe_free_recv_priv(_adapter *padapter);
+#endif
+
+void rtl8192f_query_rx_desc_status(union recv_frame *precvframe, u8 *pdesc);
+
+#endif /* __RTL8192F_RECV_H__ */
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/include/rtl8192f_rf.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/rtl8192f_rf.h
--- linux-5.6.3/3rdparty/rtl8821ce/include/rtl8192f_rf.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/rtl8192f_rf.h	2020-04-10 16:35:06.849661608 +0300
@@ -0,0 +1,22 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2012 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#ifndef __RTL8192F_RF_H__
+#define __RTL8192F_RF_H__
+
+int PHY_RF6052_Config8192F(IN PADAPTER pdapter);
+
+void PHY_RF6052SetBandwidth8192F(IN PADAPTER Adapter, IN enum channel_width Bandwidth);
+
+#endif/* __RTL8192F_RF_H__ */
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/include/rtl8192f_spec.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/rtl8192f_spec.h
--- linux-5.6.3/3rdparty/rtl8821ce/include/rtl8192f_spec.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/rtl8192f_spec.h	2020-04-10 16:35:06.849661608 +0300
@@ -0,0 +1,534 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#ifndef __RTL8192F_SPEC_H__
+#define __RTL8192F_SPEC_H__
+
+#include <drv_conf.h>
+
+
+#define HAL_NAV_UPPER_UNIT_8192F		128		/* micro-second */
+
+/* -----------------------------------------------------
+ *
+ *	0x0000h ~ 0x00FFh	System Configuration
+ *
+ * ----------------------------------------------------- */
+#define REG_SYS_ISO_CTRL_8192F			0x0000	/* 2 Byte */
+#define REG_SYS_FUNC_EN_8192F			0x0002	/* 2 Byte */
+#define REG_APS_FSMCO_8192F			0x0004	/* 4 Byte */
+#define REG_SYS_CLKR_8192F				0x0008	/* 2 Byte */
+#define REG_9346CR_8192F				0x000A	/* 2 Byte */
+#define REG_EE_VPD_8192F				0x000C	/* 2 Byte */
+#define REG_AFE_MISC_8192F				0x0010	/* 1 Byte */
+#define REG_SPS0_CTRL_8192F				0x0011	/* 7 Byte */
+#define REG_SPS_OCP_CFG_8192F			0x0018	/* 4 Byte */
+#define REG_RSV_CTRL_8192F				0x001C	/* 3 Byte */
+#define REG_RF_CTRL_8192F				0x001F	/* 1 Byte */
+#define REG_LPLDO_CTRL_8192F			0x0023	/* 1 Byte */
+#define REG_AFE_XTAL_CTRL_8192F		0x0024	/* 4 Byte */
+#define REG_AFE_PLL_CTRL_8192F			0x0028	/* 4 Byte */
+#define REG_MAC_PLL_CTRL_EXT_8192F		0x002c	/* 4 Byte */
+#define REG_EFUSE_CTRL_8192F			0x0030
+#define REG_EFUSE_TEST_8192F			0x0034
+#define REG_PWR_DATA_8192F				0x0038
+#define REG_CAL_TIMER_8192F				0x003C
+#define REG_ACLK_MON_8192F				0x003E
+#define REG_GPIO_MUXCFG_8192F			0x0040
+#define REG_GPIO_IO_SEL_8192F			0x0042
+#define REG_MAC_PINMUX_CFG_8192F		0x0043
+#define REG_GPIO_PIN_CTRL_8192F			0x0044
+#define REG_GPIO_INTM_8192F				0x0048
+#define REG_LEDCFG0_8192F				0x004C
+#define REG_LEDCFG1_8192F				0x004D
+#define REG_LEDCFG2_8192F				0x004E
+#define REG_LEDCFG3_8192F				0x004F
+#define REG_FSIMR_8192F					0x0050
+#define REG_FSISR_8192F					0x0054
+#define REG_HSIMR_8192F					0x0058
+#define REG_HSISR_8192F					0x005c
+#define REG_GPIO_EXT_CTRL				0x0060
+#define REG_PAD_CTRL1_8192F		0x0064
+#define REG_MULTI_FUNC_CTRL_8192F		0x0068
+#define REG_GPIO_STATUS_8192F			0x006C
+#define REG_SDIO_CTRL_8192F				0x0070
+#define REG_OPT_CTRL_8192F				0x0074
+#define REG_AFE_CTRL_4_8192F		0x0078
+#define REG_MCUFWDL_8192F				0x0080
+#define REG_8051FW_CTRL_8192F			0x0080
+#define REG_HMEBOX_DBG_0_8192F	0x0088
+#define REG_HMEBOX_DBG_1_8192F	0x008A
+#define REG_HMEBOX_DBG_2_8192F	0x008C
+#define REG_HMEBOX_DBG_3_8192F	0x008E
+#define REG_WLLPS_CTRL		0x0090
+#define REG_HIMR0_8192F					0x00B0
+#define REG_HISR0_8192F				0x00B4
+#define REG_HIMR1_8192F					0x00B8
+#define REG_HISR1_8192F					0x00BC
+#define REG_PMC_DBG_CTRL2_8192F			0x00CC
+#define	REG_EFUSE_BURN_GNT_8192F		0x00CF
+#define REG_HPON_FSM_8192F				0x00EC
+#define REG_SYS_CFG1_8192F				0x00F0
+#define REG_SYS_CFG2_8192F				0x00FC
+#define REG_ROM_VERSION					0x00FD
+
+/* -----------------------------------------------------
+ *
+ *	0x0100h ~ 0x01FFh	MACTOP General Configuration
+ *
+ * ----------------------------------------------------- */
+#define REG_CR_8192F						0x0100
+#define REG_PBP_8192F					0x0104
+#define REG_PKT_BUFF_ACCESS_CTRL_8192F	0x0106
+#define REG_TRXDMA_CTRL_8192F			0x010C
+#define REG_TRXFF_BNDY_8192F			0x0114
+#define REG_TRXFF_STATUS_8192F			0x0118
+#define REG_RXFF_PTR_8192F				0x011C
+#define REG_CPWM_8192F					0x012C
+#define REG_FWIMR_8192F					0x0130
+#define REG_FWISR_8192F					0x0134
+#define REG_FTIMR_8192F					0x0138
+#define REG_PKTBUF_DBG_CTRL_8192F		0x0140
+#define REG_RXPKTBUF_CTRL_8192F		0x0142
+#define REG_PKTBUF_DBG_DATA_L_8192F	0x0144
+#define REG_PKTBUF_DBG_DATA_H_8192F	0x0148
+
+#define REG_TC0_CTRL_8192F				0x0150
+#define REG_TC1_CTRL_8192F				0x0154
+#define REG_TC2_CTRL_8192F				0x0158
+#define REG_TC3_CTRL_8192F				0x015C
+#define REG_TC4_CTRL_8192F				0x0160
+#define REG_TCUNIT_BASE_8192F			0x0164
+#define REG_RSVD3_8192F					0x0168
+#define REG_C2HEVT_CMD_ID_8192F	0x01A0
+#define REG_C2HEVT_CMD_SEQ_88XX		0x01A1
+#define REG_C2hEVT_CMD_CONTENT_88XX	0x01A2
+#define REG_C2HEVT_CMD_LEN_8192F        0x01AE
+#define REG_C2HEVT_CLEAR_8192F			0x01AF
+#define REG_MCUTST_1_8192F				0x01C0
+#define REG_WOWLAN_WAKE_REASON 0x01C7
+#define REG_FMETHR_8192F				0x01C8
+#define REG_HMETFR_8192F				0x01CC
+#define REG_HMEBOX_0_8192F				0x01D0
+#define REG_HMEBOX_1_8192F				0x01D4
+#define REG_HMEBOX_2_8192F				0x01D8
+#define REG_HMEBOX_3_8192F				0x01DC
+#define REG_LLT_INIT_8192F				0x01E0
+#define REG_HMEBOX_EXT0_8192F			0x01F0
+#define REG_HMEBOX_EXT1_8192F			0x01F4
+#define REG_HMEBOX_EXT2_8192F			0x01F8
+#define REG_HMEBOX_EXT3_8192F			0x01FC
+
+/* -----------------------------------------------------
+ *
+ *	0x0200h ~ 0x027Fh	TXDMA Configuration
+ *
+ * ----------------------------------------------------- */
+#define REG_RQPN_8192F					0x0200
+#define REG_FIFOPAGE_8192F				0x0204
+#define REG_DWBCN0_CTRL_8192F			REG_TDECTRL
+#define REG_TXDMA_OFFSET_CHK_8192F	0x020C
+#define REG_TXDMA_STATUS_8192F		0x0210
+#define REG_RQPN_NPQ_8192F			0x0214
+#define REG_DWBCN1_CTRL_8192F			0x0228
+#define REG_RQPN_EXQ1_EXQ2			0x0230
+
+/* -----------------------------------------------------
+ *
+ *	0x0280h ~ 0x02FFh	RXDMA Configuration
+ *
+ * ----------------------------------------------------- */
+#define REG_RXDMA_AGG_PG_TH_8192F		0x0280
+#define REG_FW_UPD_RDPTR_8192F		0x0284 /* FW shall update this register before FW write RXPKT_RELEASE_POLL to 1 */
+#define REG_RXDMA_CONTROL_8192F		0x0286 /* Control the RX DMA. */
+#define REG_RXDMA_STATUS_8192F			0x0288
+#define REG_RXDMA_MODE_CTRL_8192F		0x0290
+#define REG_EARLY_MODE_CONTROL_8192F	0x02BC
+#define REG_RSVD5_8192F					0x02F0
+#define REG_RSVD6_8192F					0x02F4
+
+/* -----------------------------------------------------
+ *
+ *	0x0300h ~ 0x03FFh	PCIe
+ *
+ * ----------------------------------------------------- */
+#define	REG_PCIE_CTRL_REG_8192F		0x0300
+#define	REG_INT_MIG_8192F				0x0304	/* Interrupt Migration */
+#define	REG_BCNQ_TXBD_DESA_8192F		0x0308	/* TX Beacon Descriptor Address */
+#define	REG_MGQ_TXBD_DESA_8192F			0x0310	/* TX Manage Queue Descriptor Address */
+#define	REG_VOQ_TXBD_DESA_8192F			0x0318	/* TX VO Queue Descriptor Address */
+#define	REG_VIQ_TXBD_DESA_8192F			0x0320	/* TX VI Queue Descriptor Address */
+#define	REG_BEQ_TXBD_DESA_8192F			0x0328	/* TX BE Queue Descriptor Address */
+#define	REG_BKQ_TXBD_DESA_8192F			0x0330	/* TX BK Queue Descriptor Address */
+#define	REG_RXQ_RXBD_DESA_8192F			0x0338	/* RX Queue	Descriptor Address */
+#define REG_HI0Q_TXBD_DESA_8192F		0x0340
+#define REG_HI1Q_TXBD_DESA_8192F		0x0348
+#define REG_HI2Q_TXBD_DESA_8192F		0x0350
+#define REG_HI3Q_TXBD_DESA_8192F		0x0358
+#define REG_HI4Q_TXBD_DESA_8192F		0x0360
+#define REG_HI5Q_TXBD_DESA_8192F		0x0368
+#define REG_HI6Q_TXBD_DESA_8192F		0x0370
+#define REG_HI7Q_TXBD_DESA_8192F		0x0378
+#define	REG_MGQ_TXBD_NUM_8192F			0x0380
+#define	REG_RX_RXBD_NUM_8192F			0x0382
+#define	REG_VOQ_TXBD_NUM_8192F			0x0384
+#define	REG_VIQ_TXBD_NUM_8192F			0x0386
+#define	REG_BEQ_TXBD_NUM_8192F			0x0388
+#define	REG_BKQ_TXBD_NUM_8192F			0x038A
+#define	REG_HI0Q_TXBD_NUM_8192F			0x038C
+#define	REG_HI1Q_TXBD_NUM_8192F			0x038E
+#define	REG_HI2Q_TXBD_NUM_8192F			0x0390
+#define	REG_HI3Q_TXBD_NUM_8192F			0x0392
+#define	REG_HI4Q_TXBD_NUM_8192F			0x0394
+#define	REG_HI5Q_TXBD_NUM_8192F			0x0396
+#define	REG_HI6Q_TXBD_NUM_8192F			0x0398
+#define	REG_HI7Q_TXBD_NUM_8192F			0x039A
+#define	REG_TSFTIMER_HCI_8192F			0x039C
+#define	REG_BD_RW_PTR_CLR_8192F			0x039C
+
+/* Read Write Point */
+#define	REG_VOQ_TXBD_IDX_8192F			0x03A0
+#define	REG_VIQ_TXBD_IDX_8192F			0x03A4
+#define	REG_BEQ_TXBD_IDX_8192F			0x03A8
+#define	REG_BKQ_TXBD_IDX_8192F			0x03AC
+#define	REG_MGQ_TXBD_IDX_8192F			0x03B0
+#define	REG_RXQ_TXBD_IDX_8192F			0x03B4
+#define	REG_HI0Q_TXBD_IDX_8192F			0x03B8
+#define	REG_HI1Q_TXBD_IDX_8192F			0x03BC
+#define	REG_HI2Q_TXBD_IDX_8192F			0x03C0
+#define	REG_HI3Q_TXBD_IDX_8192F			0x03C4
+#define	REG_HI4Q_TXBD_IDX_8192F			0x03C8
+#define	REG_HI5Q_TXBD_IDX_8192F			0x03CC
+#define	REG_HI6Q_TXBD_IDX_8192F			0x03D0
+#define	REG_HI7Q_TXBD_IDX_8192F			0x03D4
+#define	REG_DBI_WDATA_V1_8192F			0x03E8
+#define	REG_DBI_RDATA_V1_8192F			0x03EC
+#define	REG_DBI_FLAG_V1_8192F			0x03F0
+#define REG_MDIO_V1_8192F			0x03F4
+#define REG_HCI_MIX_CFG_8192F			0x03FC
+#define REG_PCIE_HCPWM_8192FE				0x03D8
+#define REG_PCIE_HRPWM_8192FE				0x03DC
+#define REG_PCIE_MIX_CFG_8192F				0x03F8
+
+/* -----------------------------------------------------
+ *
+ *	0x0400h ~ 0x047Fh	Protocol Configuration
+ *
+ * ----------------------------------------------------- */
+#define REG_QUEUELIST_INFO0_8192F		0x0400
+#define REG_QUEUELIST_INFO1_8192F		0x0404
+#define REG_QUEUELIST_INFO2_8192F		0x0414
+#define REG_TXPKT_EMPTY_8192F			0x0418
+
+#define REG_FWHW_TXQ_CTRL_8192F		0x0420
+#define REG_HWSEQ_CTRL_8192F			0x0423
+#define REG_TXPKTBUF_BCNQ_BDNY_8192F	0x0424
+#define REG_TXPKTBUF_MGQ_BDNY_8192F	0x0425
+#define REG_LIFECTRL_CTRL_8192F			0x0426
+#define REG_MULTI_BCNQ_OFFSET_8192F	0x0427
+#define REG_SPEC_SIFS_8192F				0x0428
+#define REG_RL_8192F						0x042A
+#define REG_TXBF_CTRL_8192F				0x042C
+#define REG_DARFRC_8192F				0x0430
+#define REG_RARFRC_8192F				0x0438
+#define REG_RRSR_8192F					0x0440
+#define REG_ARFR0_8192F					0x0444
+#define REG_ARFR1_8192F					0x044C
+#define REG_CCK_CHECK_8192F				0x0454
+#define REG_AMPDU_MAX_TIME_8192F		0x0456
+#define REG_TXPKTBUF_BCNQ_BDNY1_8192F	0x0457
+
+#define REG_AMPDU_MAX_LENGTH_8192F	0x0458
+#define REG_TXPKTBUF_WMAC_LBK_BF_HD_8192F	0x045D
+#define REG_NDPA_OPT_CTRL_8192F		0x045F
+#define REG_FAST_EDCA_CTRL_8192F		0x0460
+#define REG_RD_RESP_PKT_TH_8192F		0x0463
+#define REG_DATA_SC_8192F				0x0483
+#define REG_TXRPT_START_OFFSET		0x04AC
+#define REG_POWER_STAGE1_8192F		0x04B4
+#define REG_POWER_STAGE2_8192F		0x04B8
+#define REG_AMPDU_BURST_MODE_8192F	0x04BC
+#define REG_PKT_VO_VI_LIFE_TIME_8192F	0x04C0
+#define REG_PKT_BE_BK_LIFE_TIME_8192F	0x04C2
+#define REG_STBC_SETTING_8192F			0x04C4
+#define REG_HT_SINGLE_AMPDU_8192F		0x04C7
+#define REG_PROT_MODE_CTRL_8192F		0x04C8
+#define REG_MAX_AGGR_NUM_8192F		0x04CA
+#define REG_RTS_MAX_AGGR_NUM_8192F	0x04CB
+#define REG_BAR_MODE_CTRL_8192F		0x04CC
+#define REG_RA_TRY_RATE_AGG_LMT_8192F	0x04CF
+#define REG_MACID_PKT_DROP0_8192F		0x04D0
+#define REG_MACID_PKT_SLEEP_8192F		0x04D4
+#define REG_PRECNT_CTRL_8192F			0x04E5
+/* -----------------------------------------------------
+ *
+ *	0x0500h ~ 0x05FFh	EDCA Configuration
+ *
+ * ----------------------------------------------------- */
+#define REG_EDCA_VO_PARAM_8192F		0x0500
+#define REG_EDCA_VI_PARAM_8192F		0x0504
+#define REG_EDCA_BE_PARAM_8192F		0x0508
+#define REG_EDCA_BK_PARAM_8192F		0x050C
+#define REG_BCNTCFG_8192F				0x0510
+#define REG_PIFS_8192F					0x0512
+#define REG_RDG_PIFS_8192F				0x0513
+#define REG_SIFS_CTX_8192F				0x0514
+#define REG_SIFS_TRX_8192F				0x0516
+#define REG_AGGR_BREAK_TIME_8192F		0x051A
+#define REG_SLOT_8192F					0x051B
+#define REG_TX_PTCL_CTRL_8192F			0x0520
+#define REG_TXPAUSE_8192F				0x0522
+#define REG_DIS_TXREQ_CLR_8192F		0x0523
+#define REG_RD_CTRL_8192F				0x0524
+/*
+ * Format for offset 540h-542h:
+ *	[3:0]:   TBTT prohibit setup in unit of 32us. The time for HW getting beacon content before TBTT.
+ *	[7:4]:   Reserved.
+ *	[19:8]:  TBTT prohibit hold in unit of 32us. The time for HW holding to send the beacon packet.
+ *	[23:20]: Reserved
+ * Description:
+ *	              |
+ * |<--Setup--|--Hold------------>|
+ *	--------------|----------------------
+ * |
+ * TBTT
+ * Note: We cannot update beacon content to HW or send any AC packets during the time between Setup and Hold.
+ * Described by Designer Tim and Bruce, 2011-01-14.
+ *   */
+#define REG_TBTT_PROHIBIT_8192F			0x0540
+#define REG_RD_NAV_NXT_8192F			0x0544
+#define REG_NAV_PROT_LEN_8192F			0x0546
+#define REG_BCN_CTRL_8192F				0x0550
+#define REG_BCN_CTRL_1_8192F			0x0551
+#define REG_MBID_NUM_8192F				0x0552
+#define REG_DUAL_TSF_RST_8192F			0x0553
+#define REG_BCN_INTERVAL_8192F			0x0554
+#define REG_DRVERLYINT_8192F			0x0558
+#define REG_BCNDMATIM_8192F			0x0559
+#define REG_ATIMWND_8192F				0x055A
+#define REG_USTIME_TSF_8192F			0x055C
+#define REG_BCN_MAX_ERR_8192F			0x055D
+#define REG_RXTSF_OFFSET_CCK_8192F		0x055E
+#define REG_RXTSF_OFFSET_OFDM_8192F	0x055F	
+#define REG_TSFTR_8192F					0x0560
+#define REG_CTWND_8192F					0x0572
+#define REG_SECONDARY_CCA_CTRL_8192F	0x0577
+#define REG_PSTIMER_8192F				0x0580
+#define REG_TIMER0_8192F				0x0584
+#define REG_TIMER1_8192F				0x0588
+#define REG_ACMHWCTRL_8192F			0x05C0
+#define REG_SCH_TXCMD_8192F			0x05F8
+
+/* -----------------------------------------------------
+ *
+ *	0x0600h ~ 0x07FFh	WMAC Configuration
+ *
+ * ----------------------------------------------------- */
+#define REG_MAC_CR_8192F				0x0600
+#define REG_TCR_8192F					0x0604
+#define REG_RCR_8192F					0x0608
+#define REG_RX_PKT_LIMIT_8192F			0x060C
+#define REG_RX_DLK_TIME_8192F			0x060D
+#define REG_RX_DRVINFO_SZ_8192F	0x060F
+
+#define REG_MACID_8192F					0x0610
+#define REG_BSSID_8192F					0x0618
+#define REG_MAR_8192F					0x0620
+#define REG_MBIDCAMCFG_8192F			0x0628
+
+
+#define REG_USTIME_EDCA_8192F			0x0638
+#define REG_MAC_SPEC_SIFS_8192F		0x063A
+#define REG_RESP_SIFP_CCK_8192F			0x063C
+#define REG_RESP_SIFS_OFDM_8192F		0x063E
+#define REG_ACKTO_8192F					0x0640
+#define REG_CTS2TO_8192F				0x0641
+#define REG_EIFS_8192F					0x0642
+
+#define REG_NAV_UPPER_8192F			0x0652	/* unit of 128*/
+#define REG_TRXPTCL_CTL_8192F			0x0668
+
+/* Security*/
+#define REG_CAMCMD_8192F				0x0670
+#define REG_CAMWRITE_8192F				0x0674
+#define REG_CAMREAD_8192F				0x0678
+#define REG_CAMDBG_8192F				0x067C
+#define REG_SECCFG_8192F				0x0680
+
+/* Power */
+#define REG_WOW_CTRL_8192F				0x0690
+#define REG_PS_RX_INFO_8192F			0x0692
+#define REG_UAPSD_TID_8192F				0x0693
+#define REG_WKFMCAM_CMD_8192F			0x0698
+#define REG_WKFMCAM_NUM_8192F			0x0698
+#define REG_WKFMCAM_RWD_8192F			0x069C
+#define REG_RXFLTMAP0_8192F				0x06A0
+#define REG_RXFLTMAP1_8192F				0x06A2
+#define REG_RXFLTMAP2_8192F				0x06A4
+#define REG_BCN_PSR_RPT_8192F			0x06A8
+#define REG_BT_COEX_TABLE_8192F		0x06C0
+#define REG_BFMER0_INFO_8192F			0x06E4
+#define REG_BFMER1_INFO_8192F			0x06EC
+#define REG_CSI_RPT_PARAM_BW20_8192F	0x06F4
+#define REG_CSI_RPT_PARAM_BW40_8192F	0x06F8
+#define REG_CSI_RPT_PARAM_BW80_8192F	0x06FC
+
+/* Hardware Port 2 */
+#define REG_MACID1_8192F				0x0700
+#define REG_BSSID1_8192F				0x0708
+#define REG_BFMEE_SEL_8192F				0x0714
+#define REG_SND_PTCL_CTRL_8192F		0x0718
+
+/* LTR */
+#define REG_LTR_CTRL_BASIC_8192F		0x07A4
+#define REG_LTR_IDLE_LATENCY_V1_8192F		0x0798
+#define REG_LTR_ACTIVE_LATENCY_V1_8192F	0x079C
+
+
+/* ************************************************************
+ * SDIO Bus Specification
+ * ************************************************************ */
+
+/* -----------------------------------------------------
+ * SDIO CMD Address Mapping
+ * ----------------------------------------------------- */
+
+/* -----------------------------------------------------
+ * I/O bus domain (Host)
+ * ----------------------------------------------------- */
+/*SDIO Host Interrupt Mask Register */
+#define SDIO_HIMR_CRCERR_MSK			BIT(31)
+/* SDIO Host Interrupt Service Routine */
+#define SDIO_HISR_HEISR_IND_INT		BIT(28)
+#define SDIO_HISR_HSISR2_IND_INT		BIT(29)
+#define SDIO_HISR_HSISR3_IND_INT		BIT(30)
+#define SDIO_HISR_SDIO_CRCERR			BIT(31)
+/* -----------------------------------------------------
+ * SDIO register
+ * ----------------------------------------------------- */
+#define SDIO_REG_HCPWM1_8192F	0x038/* HCI Current Power Mode 1 */
+#define SDIO_REG_FREE_TXPG1_8192F		0x0020 /* Free Tx Buffer Page1*/
+#define SDIO_REG_FREE_TXPG2_8192F		0x0024 /* Free Tx Buffer Page1*/
+#define SDIO_REG_FREE_TXPG3_8192F		0x0028
+#define SDIO_REG_AC_OQT_FREEPG_8192F		0x002A
+#define SDIO_REG_NOAC_OQT_FREEPG_8192F		0x002B
+/* ****************************************************************************
+ *	8192F Regsiter Bit and Content definition
+ * **************************************************************************** */
+
+#define BIT_USB_RXDMA_AGG_EN	BIT(31)
+#define RXDMA_AGG_MODE_EN		BIT(1)
+
+#ifdef CONFIG_WOWLAN
+	#define RXPKT_RELEASE_POLL		BIT(16)
+	#define RXDMA_IDLE				BIT(17)
+	#define RW_RELEASE_EN			BIT(18)
+#endif
+
+#ifdef CONFIG_AMPDU_PRETX_CD
+/*#define BIT_ERRORHDL_INT			BIT(2)*/
+/*#define BIT_MACTX_ERR_3			BIT(4)*/
+#define BIT_PRE_TX_CMD_8192F		BIT(6)
+#define BIT_EN_PRECNT_8192F		BIT(11)
+#endif
+/* SDIO Host Interrupt Service Routine */
+#define SDIO_HISR_HEISR_IND_INT	BIT(28)
+#define SDIO_HISR_HSISR2_IND_INT	BIT(29)
+#define SDIO_HISR_HSISR3_IND_INT	BIT(30)
+#define SDIO_HISR_SDIO_CRCERR		BIT(31)
+
+/* PCIE Host Interrupt Mask Register (HIMR) */
+#ifdef CONFIG_PCI_HCI
+/* ----------------------------------------------------------------------------
+ *   * 8192F IMR/ISR bits							(offset 0xB0,  8bits)
+ *     * ---------------------------------------------------------------------------- */
+
+#define IMR_DISABLED_8192F					0
+/* IMR DW0(0x00B0-00B3) Bit 0-31 */
+#define IMR_TIMER2_8192F					BIT(31)         /* Timeout interrupt 2 */
+#define IMR_TIMER1_8192F					BIT(30)		/* Timeout interrupt 1 */
+#define IMR_PSTIMEOUT_8192F				BIT(29)		/* Power Save Time Out Interrupt */
+#define IMR_GTINT4_8192F					BIT(28)		/* When GTIMER4 expires, this bit is set to 1 */
+#define IMR_GTINT3_8192F					BIT(27)		/* When GTIMER3 expires, this bit is set to 1 */
+#define IMR_TXBCN0ERR_8192F				BIT(26)		/* Transmit Beacon0 Error */
+#define IMR_TXBCN0OK_8192F				BIT(25)		/* Transmit Beacon0 OK */
+#define IMR_TSF_BIT32_TOGGLE_8192F		BIT(24)		/* TSF Timer BIT32 toggle indication interrupt */
+#define IMR_BCNDMAINT0_8192F				BIT(20)		/* Beacon DMA Interrupt 0 */
+#define IMR_BCNDERR0_8192F				BIT(16)		/* Beacon Queue DMA OK0 */
+#define IMR_HSISR_IND_ON_INT_8192F		BIT(15)		/* HSISR Indicator (HSIMR & HSISR is true, this bit is set to 1) */
+#define IMR_BCNDMAINT_E_8192F				BIT(14)		/* Beacon DMA Interrupt Extension for Win7 */
+#define IMR_ATIMEND_8192F					BIT(12)         /* CTWidnow End or ATIM Window End */
+#define IMR_C2HCMD_8192F					BIT(10)		/* CPU to Host Command INT status, Write 1 clear */
+#define IMR_CPWM2_8192F					BIT(9)          /* CPU power mode exchange INT status, Write 1 clear */
+#define IMR_CPWM_8192F						BIT(8)		/* CPU power mode exchange INT status, Write 1 clear */
+#define IMR_HIGHDOK_8192F					BIT(7)		/* High Queue DMA OK */
+#define IMR_MGNTDOK_8192F					BIT(6)		/* Management Queue DMA OK */
+#define IMR_BKDOK_8192F					BIT(5)		/* AC_BK DMA OK */
+#define IMR_BEDOK_8192F					BIT(4)		/* AC_BE DMA OK */
+#define IMR_VIDOK_8192F					BIT(3)		/* AC_VI DMA OK */
+#define IMR_VODOK_8192F					BIT(2)		/* AC_VO DMA OK */
+#define IMR_RDU_8192F						BIT(1)		/* Rx Descriptor Unavailable */
+#define IMR_ROK_8192F						BIT(0)		/* Receive DMA OK */
+
+/* IMR DW1(0x00B4-00B7) Bit 0-31 */
+#define IMR_MCUERR_8192F					BIT(28)
+#define IMR_BCNDMAINT7_8192F				BIT(27) 		/* Beacon DMA Interrupt 7 */
+#define IMR_BCNDMAINT6_8192F				BIT(26)		/* Beacon DMA Interrupt 6 */
+#define IMR_BCNDMAINT5_8192F				BIT(25)		/* Beacon DMA Interrupt 5 */
+#define IMR_BCNDMAINT4_8192F				BIT(24)		/* Beacon DMA Interrupt 4 */
+#define IMR_BCNDMAINT3_8192F				BIT(23)		/* Beacon DMA Interrupt 3 */
+#define IMR_BCNDMAINT2_8192F				BIT(22)		/* Beacon DMA Interrupt 2 */
+#define IMR_BCNDMAINT1_8192F 				BIT(21)		/* Beacon DMA Interrupt 1 */
+#define IMR_BCNDOK7_8192F 					BIT(20)		/* Beacon Queue DMA OK Interrup 7 */
+#define IMR_BCNDOK6_8192F					BIT(19) 		/* Beacon Queue DMA OK Interrup 6 */
+#define IMR_BCNDOK5_8192F					BIT(18)		/* Beacon Queue DMA OK Interrup 5 */
+#define IMR_BCNDOK4_8192F					BIT(17)		/* Beacon Queue DMA OK Interrup 4 */
+#define IMR_BCNDOK3_8192F					BIT(16)		/* Beacon Queue DMA OK Interrup 3 */
+#define IMR_BCNDOK2_8192F					BIT(15)		/* Beacon Queue DMA OK Interrup 2 */
+#define IMR_BCNDOK1_8192F					BIT(14)		/* Beacon Queue DMA OK Interrup 1 */
+#define IMR_ATIMEND_E_8192F				BIT(13)		/* ATIM Window End Extension for Win7 */
+#define IMR_TXERR_8192F					BIT(11)		/* Tx Error Flag Interrupt status, write 1 clear. */
+#define IMR_RXERR_8192F					BIT(10)		/* Rx Error Flag INT status, Write 1 clear */
+#define IMR_TXFOVW_8192F					BIT(9)		/* Transmit FIFO Overflow */
+#define IMR_RXFOVW_8192F 					BIT(8)		/* Receive FIFO Overflow */
+
+/* #define IMR_RX_MASK			(IMR_ROK_8192F|IMR_RDU_8192F|IMR_RXFOVW_8192F) */
+#define IMR_TX_MASK			(IMR_VODOK_8192F | IMR_VIDOK_8192F | IMR_BEDOK_8192F | IMR_BKDOK_8192F | IMR_MGNTDOK_8192F | IMR_HIGHDOK_8192F)
+#define RT_BCN_INT_MASKS		(IMR_BCNDMAINT0_8192F | IMR_TXBCN0OK_8192F | IMR_TXBCN0ERR_8192F | IMR_BCNDERR0_8192F)
+#define RT_AC_INT_MASKS		(IMR_VIDOK_8192F | IMR_VODOK_8192F | IMR_BEDOK_8192F | IMR_BKDOK_8192F)
+#endif /* CONFIG_PCI_HCI */
+
+/* 2 HSISR
+ * interrupt mask which needs to clear */
+#define MASK_HSISR_CLEAR		(HSISR_GPIO12_0_INT |\
+		HSISR_SPS_OCP_INT |\
+		HSISR_RON_INT |\
+		HSISR_PDNINT |\
+		HSISR_GPIO9_INT)
+
+#define _TXDMA_HIQ_MAP_8192F(x)			(((x) & 0x7) << 19)
+#define _TXDMA_MGQ_MAP_8192F(x)			(((x) & 0x7) << 16)
+#define _TXDMA_BKQ_MAP_8192F(x)			(((x) & 0x7) << 13)
+#define _TXDMA_BEQ_MAP_8192F(x)			(((x) & 0x7) << 10)
+#define _TXDMA_VIQ_MAP_8192F(x)			(((x) & 0x7) << 7)
+#define _TXDMA_VOQ_MAP_8192F(x)			(((x) & 0x7) << 4)
+
+/*mac queue info*/
+#define QUEUE_TOTAL_NUM	20/*reg414h : 0~f ac queue 0x10~0x13MGQ HIQ BCNQ CMDQ*/
+#define QUEUE_ACQ_NUM		16 
+#define QUEUE_INDEX_MGQ		0x10
+#define QUEUE_INDEX_HIQ		0x11
+#define QUEUE_INDEX_BCNQ	0x12
+#define QUEUE_INDEX_CMDQ	0x13
+#endif /* __RTL8192F_SPEC_H__ */
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/include/rtl8192f_sreset.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/rtl8192f_sreset.h
--- linux-5.6.3/3rdparty/rtl8821ce/include/rtl8192f_sreset.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/rtl8192f_sreset.h	2020-04-10 16:35:06.849661608 +0300
@@ -0,0 +1,24 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#ifndef _RTL8192F_SRESET_H_
+#define _RTL8192F_SRESET_H_
+
+#include <rtw_sreset.h>
+
+#ifdef DBG_CONFIG_ERROR_DETECT
+	extern void rtl8192f_sreset_xmit_status_check(_adapter *padapter);
+	extern void rtl8192f_sreset_linked_status_check(_adapter *padapter);
+#endif /* DBG_CONFIG_ERROR_DETECT */
+#endif /* _RTL8192F_SRESET_H_ */
\ Ingen nyrad vid filslut
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/include/rtl8192f_xmit.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/rtl8192f_xmit.h
--- linux-5.6.3/3rdparty/rtl8821ce/include/rtl8192f_xmit.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/rtl8192f_xmit.h	2020-04-10 16:35:06.849661608 +0300
@@ -0,0 +1,531 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#ifndef __RTL8192F_XMIT_H__
+#define __RTL8192F_XMIT_H__
+
+
+#define MAX_TID (15)
+
+
+#ifndef __INC_HAL8192FDESC_H
+#define __INC_HAL8192FDESC_H
+
+#define RX_STATUS_DESC_SIZE_8192F		24
+#define RX_DRV_INFO_SIZE_UNIT_8192F 	8
+
+
+/* DWORD 0 */
+#define SET_RX_STATUS_DESC_PKT_LEN_8192F(__pRxStatusDesc, __Value) \
+	SET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 0, 14, __Value)
+#define SET_RX_STATUS_DESC_EOR_8192F(__pRxStatusDesc, __Value) \
+	SET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 30, 1, __Value)
+#define SET_RX_STATUS_DESC_OWN_8192F(__pRxStatusDesc, __Value) \
+	SET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 31, 1, __Value)
+
+#define GET_RX_STATUS_DESC_PKT_LEN_8192F(__pRxStatusDesc) \
+	LE_BITS_TO_4BYTE(__pRxStatusDesc, 0, 14)
+#define GET_RX_STATUS_DESC_CRC32_8192F(__pRxStatusDesc) \
+	LE_BITS_TO_4BYTE(__pRxStatusDesc, 14, 1)
+#define GET_RX_STATUS_DESC_ICV_8192F(__pRxStatusDesc) \
+	LE_BITS_TO_4BYTE(__pRxStatusDesc, 15, 1)
+#define GET_RX_STATUS_DESC_DRVINFO_SIZE_8192F(__pRxStatusDesc) \
+	LE_BITS_TO_4BYTE(__pRxStatusDesc, 16, 4)
+#define GET_RX_STATUS_DESC_SECURITY_8192F(__pRxStatusDesc) \
+	LE_BITS_TO_4BYTE(__pRxStatusDesc, 20, 3)
+#define GET_RX_STATUS_DESC_QOS_8192F(__pRxStatusDesc) \
+	LE_BITS_TO_4BYTE(__pRxStatusDesc, 23, 1)
+#define GET_RX_STATUS_DESC_SHIFT_8192F(__pRxStatusDesc) \
+	LE_BITS_TO_4BYTE(__pRxStatusDesc, 24, 2)
+#define GET_RX_STATUS_DESC_PHY_STATUS_8192F(__pRxStatusDesc) \
+	LE_BITS_TO_4BYTE(__pRxStatusDesc, 26, 1)
+#define GET_RX_STATUS_DESC_SWDEC_8192F(__pRxStatusDesc) \
+	LE_BITS_TO_4BYTE(__pRxStatusDesc, 27, 1)
+#define GET_RX_STATUS_DESC_EOR_8192F(__pRxStatusDesc) \
+	LE_BITS_TO_4BYTE(__pRxStatusDesc, 30, 1)
+#define GET_RX_STATUS_DESC_OWN_8192F(__pRxStatusDesc) \
+	LE_BITS_TO_4BYTE(__pRxStatusDesc, 31, 1)
+
+/* DWORD 1 */
+#define GET_RX_STATUS_DESC_MACID_8192F(__pRxDesc) \
+	LE_BITS_TO_4BYTE(__pRxDesc+4, 0, 7)
+#define GET_RX_STATUS_DESC_TID_8192F(__pRxDesc) \
+	LE_BITS_TO_4BYTE(__pRxDesc+4, 8, 4)
+#define GET_RX_STATUS_DESC_AMSDU_8192F(__pRxDesc) \
+	LE_BITS_TO_4BYTE(__pRxDesc+4, 13, 1)
+#define GET_RX_STATUS_DESC_RXID_MATCH_8192F(__pRxDesc) \
+	LE_BITS_TO_4BYTE(__pRxDesc+4, 14, 1)
+#define GET_RX_STATUS_DESC_PAGGR_8192F(__pRxDesc) \
+	LE_BITS_TO_4BYTE(__pRxDesc+4, 15, 1)
+#define GET_RX_STATUS_DESC_A1_FIT_8192F(__pRxDesc) \
+	LE_BITS_TO_4BYTE(__pRxDesc+4, 16, 4)
+#define GET_RX_STATUS_DESC_CHKERR_8192F(__pRxDesc) \
+	LE_BITS_TO_4BYTE(__pRxDesc+4, 20, 1)
+#define GET_RX_STATUS_DESC_IPVER_8192F(__pRxDesc) \
+	LE_BITS_TO_4BYTE(__pRxDesc+4, 21, 1)
+#define GET_RX_STATUS_DESC_IS_TCPUDP__8192F(__pRxDesc) \
+	LE_BITS_TO_4BYTE(__pRxDesc+4, 22, 1)
+#define GET_RX_STATUS_DESC_CHK_VLD_8192F(__pRxDesc) \
+	LE_BITS_TO_4BYTE(__pRxDesc+4, 23, 1)
+#define GET_RX_STATUS_DESC_PAM_8192F(__pRxDesc) \
+	LE_BITS_TO_4BYTE(__pRxDesc+4, 24, 1)
+#define GET_RX_STATUS_DESC_PWR_8192F(__pRxDesc) \
+	LE_BITS_TO_4BYTE(__pRxDesc+4, 25, 1)
+#define GET_RX_STATUS_DESC_MORE_DATA_8192F(__pRxDesc) \
+	LE_BITS_TO_4BYTE(__pRxDesc+4, 26, 1)
+#define GET_RX_STATUS_DESC_MORE_FRAG_8192F(__pRxDesc) \
+	LE_BITS_TO_4BYTE(__pRxDesc+4, 27, 1)
+#define GET_RX_STATUS_DESC_TYPE_8192F(__pRxDesc) \
+	LE_BITS_TO_4BYTE(__pRxDesc+4, 28, 2)
+#define GET_RX_STATUS_DESC_MC_8192F(__pRxDesc) \
+	LE_BITS_TO_4BYTE(__pRxDesc+4, 30, 1)
+#define GET_RX_STATUS_DESC_BC_8192F(__pRxDesc) \
+	LE_BITS_TO_4BYTE(__pRxDesc+4, 31, 1)
+
+/* DWORD 2 */
+#define GET_RX_STATUS_DESC_SEQ_8192F(__pRxStatusDesc) \
+	LE_BITS_TO_4BYTE(__pRxStatusDesc+8, 0, 12)
+#define GET_RX_STATUS_DESC_FRAG_8192F(__pRxStatusDesc) \
+	LE_BITS_TO_4BYTE(__pRxStatusDesc+8, 12, 4)
+#define GET_RX_STATUS_DESC_RX_IS_QOS_8192F(__pRxStatusDesc) \
+	LE_BITS_TO_4BYTE(__pRxStatusDesc+8, 16, 1)
+#define GET_RX_STATUS_DESC_WLANHD_IV_LEN_8192F(__pRxStatusDesc) \
+	LE_BITS_TO_4BYTE(__pRxStatusDesc+8, 18, 6)
+#define GET_RX_STATUS_DESC_RPT_SEL_8192F(__pRxStatusDesc) \
+	LE_BITS_TO_4BYTE(__pRxStatusDesc+8, 28, 1)
+#define GET_RX_STATUS_DESC_FCS_OK_8192F(__pRxStatusDesc) \
+	LE_BITS_TO_4BYTE(__pRxStatusDesc+8, 31, 1)
+
+/* DWORD 3 */
+#define GET_RX_STATUS_DESC_RX_RATE_8192F(__pRxStatusDesc) \
+	LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 0, 7)
+#define GET_RX_STATUS_DESC_HTC_8192F(__pRxStatusDesc) \
+	LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 10, 1)
+#define GET_RX_STATUS_DESC_EOSP_8192F(__pRxStatusDesc) \
+	LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 11, 1)
+#define GET_RX_STATUS_DESC_BSSID_FIT_8192F(__pRxStatusDesc) \
+	LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 12, 2)
+#ifdef CONFIG_USB_RX_AGGREGATION
+#define GET_RX_STATUS_DESC_USB_AGG_PKTNUM_8192F(__pRxStatusDesc) \
+	LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 16, 8)
+#endif
+#define GET_RX_STATUS_DESC_PATTERN_MATCH_8192F(__pRxDesc) \
+	LE_BITS_TO_4BYTE(__pRxDesc+12, 29, 1)
+#define GET_RX_STATUS_DESC_UNICAST_MATCH_8192F(__pRxDesc) \
+	LE_BITS_TO_4BYTE(__pRxDesc+12, 30, 1)
+#define GET_RX_STATUS_DESC_MAGIC_MATCH_8192F(__pRxDesc) \
+	LE_BITS_TO_4BYTE(__pRxDesc+12, 31, 1)
+
+/* DWORD 6 */
+#define GET_RX_STATUS_DESC_MATCH_ID_8192F(__pRxDesc) \
+	LE_BITS_TO_4BYTE(__pRxDesc+16, 0, 7)
+
+/* DWORD 5 */
+#define GET_RX_STATUS_DESC_TSFL_8192F(__pRxStatusDesc) \
+	LE_BITS_TO_4BYTE(__pRxStatusDesc+20, 0, 32)
+
+#define GET_RX_STATUS_DESC_BUFF_ADDR64_8192F(__pRxDesc) \
+	LE_BITS_TO_4BYTE(__pRxDesc+28, 0, 32)
+
+
+
+/* Dword 0, rsvd: bit26, bit28 */
+#define GET_TX_DESC_OWN_8192F(__pTxDesc)\
+	LE_BITS_TO_4BYTE(__pTxDesc, 31, 1)
+
+#define SET_TX_DESC_PKT_SIZE_8192F(__pTxDesc, __Value) \
+	SET_BITS_TO_LE_4BYTE(__pTxDesc, 0, 16, __Value)
+#define SET_TX_DESC_OFFSET_8192F(__pTxDesc, __Value) \
+	SET_BITS_TO_LE_4BYTE(__pTxDesc, 16, 8, __Value)
+#define SET_TX_DESC_BMC_8192F(__pTxDesc, __Value) \
+	SET_BITS_TO_LE_4BYTE(__pTxDesc, 24, 1, __Value)
+#define SET_TX_DESC_HTC_8192F(__pTxDesc, __Value) \
+	SET_BITS_TO_LE_4BYTE(__pTxDesc, 25, 1, __Value)
+#define SET_TX_DESC_AMSDU_PAD_EN_8192F(__pTxDesc, __Value) \
+	SET_BITS_TO_LE_4BYTE(__pTxDesc, 27, 1, __Value)
+#define SET_TX_DESC_NO_ACM_8192F(__pTxDesc, __Value) \
+	SET_BITS_TO_LE_4BYTE(__pTxDesc, 29, 1, __Value)
+#define SET_TX_DESC_GF_8192F(__pTxDesc, __Value) \
+	SET_BITS_TO_LE_4BYTE(__pTxDesc, 30, 1, __Value)
+
+/* Dword 1 */
+#define SET_TX_DESC_MACID_8192F(__pTxDesc, __Value) \
+	SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 0, 7, __Value)
+#define SET_TX_DESC_QUEUE_SEL_8192F(__pTxDesc, __Value) \
+	SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 8, 5, __Value)
+#define SET_TX_DESC_RDG_NAV_EXT_8192F(__pTxDesc, __Value) \
+	SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 13, 1, __Value)
+#define SET_TX_DESC_LSIG_TXOP_EN_8192F(__pTxDesc, __Value) \
+	SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 14, 1, __Value)
+#define SET_TX_DESC_PIFS_8192F(__pTxDesc, __Value) \
+	SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 15, 1, __Value)
+#define SET_TX_DESC_RATE_ID_8192F(__pTxDesc, __Value) \
+	SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 16, 5, __Value)
+#define SET_TX_DESC_EN_DESC_ID_8192F(__pTxDesc, __Value) \
+	SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 21, 1, __Value)
+#define SET_TX_DESC_SEC_TYPE_8192F(__pTxDesc, __Value) \
+	SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 22, 2, __Value)
+#define SET_TX_DESC_PKT_OFFSET_8192F(__pTxDesc, __Value) \
+	SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 24, 5, __Value)
+#define SET_TX_DESC_MORE_DATA_8192F(__pTxDesc, __Value) \
+	SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 29, 1, __Value)
+
+/* Dword 2 ADD HW_DIG*/
+#define SET_TX_DESC_PAID_92F(__pTxDesc, __Value) \
+	SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 0, 9, __Value)
+#define SET_TX_DESC_CCA_RTS_8192F(__pTxDesc, __Value) \
+	SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 10, 2, __Value)
+#define SET_TX_DESC_AGG_ENABLE_8192F(__pTxDesc, __Value) \
+	SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 12, 1, __Value)
+#define SET_TX_DESC_RDG_ENABLE_8192F(__pTxDesc, __Value) \
+	SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 13, 1, __Value)
+#define SET_TX_DESC_NULL0_8192F(__pTxDesc, __Value) \
+	SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 14, 1, __Value)
+#define SET_TX_DESC_NULL1_8192F(__pTxDesc, __Value) \
+	SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 15, 1, __Value)
+#define SET_TX_DESC_BK_8192F(__pTxDesc, __Value) \
+	SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 16, 1, __Value)
+#define SET_TX_DESC_MORE_FRAG_8192F(__pTxDesc, __Value) \
+	SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 17, 1, __Value)
+#define SET_TX_DESC_RAW_8192F(__pTxDesc, __Value) \
+	SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 18, 1, __Value)
+#define SET_TX_DESC_CCX_8192F(__pTxDesc, __Value) \
+	SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 19, 1, __Value)
+#define SET_TX_DESC_AMPDU_DENSITY_8192F(__pTxDesc, __Value) \
+	SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 20, 3, __Value)
+#define SET_TX_DESC_BT_INT_8192F(__pTxDesc, __Value) \
+	SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 23, 1, __Value)
+#define SET_TX_DESC_HW_DIG_8192F(__pTxDesc, __Value) \
+	SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 24, 7, __Value)
+
+/* Dword 3 */
+#define SET_TX_DESC_HWSEQ_SEL_8192F(__pTxDesc, __Value) \
+	SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 6, 2, __Value)
+#define SET_TX_DESC_USE_RATE_8192F(__pTxDesc, __Value) \
+	SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 8, 1, __Value)
+#define SET_TX_DESC_DISABLE_RTS_FB_8192F(__pTxDesc, __Value) \
+	SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 9, 1, __Value)
+#define SET_TX_DESC_DISABLE_FB_8192F(__pTxDesc, __Value) \
+	SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 10, 1, __Value)
+#define SET_TX_DESC_CTS2SELF_8192F(__pTxDesc, __Value) \
+	SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 11, 1, __Value)
+#define SET_TX_DESC_RTS_ENABLE_8192F(__pTxDesc, __Value) \
+	SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 12, 1, __Value)
+#define SET_TX_DESC_HW_RTS_ENABLE_8192F(__pTxDesc, __Value) \
+	SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 13, 1, __Value)
+#define SET_TX_DESC_CHK_EN_92F(__pTxDesc, __Value) \
+	SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 14, 1, __Value)
+#define SET_TX_DESC_NAV_USE_HDR_8192F(__pTxDesc, __Value) \
+	SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 15, 1, __Value)
+#define SET_TX_DESC_USE_MAX_LEN_8192F(__pTxDesc, __Value) \
+	SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 16, 1, __Value)
+#define SET_TX_DESC_MAX_AGG_NUM_8192F(__pTxDesc, __Value) \
+	SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 17, 5, __Value)
+#define SET_TX_DESC_NDPA_8192F(__pTxDesc, __Value) \
+	SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 22, 2, __Value)
+#define SET_TX_DESC_AMPDU_MAX_TIME_8192F(__pTxDesc, __Value) \
+	SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 24, 8, __Value)
+
+/* Dword 4 */
+#define SET_TX_DESC_TX_RATE_8192F(__pTxDesc, __Value) \
+	SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 0, 7, __Value)
+#define SET_TX_DESC_TX_TRY_RATE_8192F(__pTxDesc, __Value) \
+	SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 7, 1, __Value)
+#define SET_TX_DESC_DATA_RATE_FB_LIMIT_8192F(__pTxDesc, __Value) \
+	SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 8, 5, __Value)
+#define SET_TX_DESC_RTS_RATE_FB_LIMIT_8192F(__pTxDesc, __Value) \
+	SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 13, 4, __Value)
+#define SET_TX_DESC_RETRY_LIMIT_ENABLE_8192F(__pTxDesc, __Value) \
+	SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 17, 1, __Value)
+#define SET_TX_DESC_DATA_RETRY_LIMIT_8192F(__pTxDesc, __Value) \
+	SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 18, 6, __Value)
+#define SET_TX_DESC_RTS_RATE_8192F(__pTxDesc, __Value) \
+	SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 24, 5, __Value)
+#define SET_TX_DESC_PCTS_EN_8192F(__pTxDesc, __Value) \
+	SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 29, 1, __Value)
+#define SET_TX_DESC_PCTS_MASK_IDX_8192F(__pTxDesc, __Value) \
+	SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 30, 2, __Value)
+
+/* Dword 5 */
+#define SET_TX_DESC_DATA_SC_8192F(__pTxDesc, __Value) \
+	SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 0, 4, __Value)
+#define SET_TX_DESC_DATA_SHORT_8192F(__pTxDesc, __Value) \
+	SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 4, 1, __Value)
+#define SET_TX_DESC_DATA_BW_8192F(__pTxDesc, __Value) \
+	SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 5, 2, __Value)
+#define SET_TX_DESC_DATA_LDPC_8192F(__pTxDesc, __Value) \
+	SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 7, 1, __Value)
+#define SET_TX_DESC_DATA_STBC_8192F(__pTxDesc, __Value) \
+	SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 8, 2, __Value)
+#define SET_TX_DESC_RTS_STBC_8192F(__pTxDesc, __Value) \
+	SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 10, 2, __Value)
+#define SET_TX_DESC_RTS_SHORT_8192F(__pTxDesc, __Value) \
+	SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 12, 1, __Value)
+#define SET_TX_DESC_RTS_SC_8192F(__pTxDesc, __Value) \
+	SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 13, 4, __Value)
+#define SET_TX_DESC_PORT_ID_8192F(__pTxDesc, __Value) \
+	SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 21, 1, __Value)
+#define SET_TX_DESC_DROP_ID_8192F(__pTxDesc, __Value) \
+	SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 22, 2, __Value)
+#define SET_TX_DESC_PATH_A_EN_8192F(__pTxDesc, __Value) \
+	SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 24, 1, __Value)
+#define SET_TX_DESC_PATH_B_EN_8192F(__pTxDesc, __Value) \
+	SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 25, 1, __Value)
+#define SET_TX_DESC_TXPWR_OF_SET_8192F(__pTxDesc, __Value) \
+	SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 28, 3, __Value)
+
+/* Dword 6 */
+#define SET_TX_DESC_SW_DEFINE_8192F(__pTxDesc, __Value) \
+	SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 0, 12, __Value)
+#define SET_TX_DESC_MBSSID_8192F(__pTxDesc, __Value) \
+	SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 12, 4, __Value)
+#define SET_TX_DESC_RF_SEL_8192F(__pTxDesc, __Value) \
+	SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 16, 3, __Value)
+
+/* Dword 7 */
+#ifdef CONFIG_PCI_HCI
+#define SET_TX_DESC_TX_BUFFER_SIZE_8192F(__pTxDesc, __Value) \
+	SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 0, 16, __Value)
+#endif
+
+#ifdef CONFIG_USB_HCI
+#define SET_TX_DESC_TX_DESC_CHECKSUM_8192F(__pTxDesc, __Value) \
+	SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 0, 16, __Value)
+#endif
+
+#ifdef CONFIG_SDIO_HCI
+#define SET_TX_DESC_TX_TIMESTAMP_8192F(__pTxDesc, __Value) \
+	SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 6, 18, __Value)
+#endif
+
+#define SET_TX_DESC_USB_TXAGG_NUM_8192F(__pTxDesc, __Value) \
+	SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 24, 8, __Value)
+
+/* Dword 8 */
+#define SET_TX_DESC_RTS_RC_8192F(__pTxDesc, __Value) \
+	SET_BITS_TO_LE_4BYTE(__pTxDesc+32, 0, 6, __Value)
+#define SET_TX_DESC_BAR_RC_8192F(__pTxDesc, __Value) \
+	SET_BITS_TO_LE_4BYTE(__pTxDesc+32, 6, 2, __Value)
+#define SET_TX_DESC_DATA_RC_8192F(__pTxDesc, __Value) \
+	SET_BITS_TO_LE_4BYTE(__pTxDesc+32, 8, 6, __Value)
+#define SET_TX_DESC_HWSEQ_EN_8192F(__pTxDesc, __Value) \
+	SET_BITS_TO_LE_4BYTE(__pTxDesc+32, 15, 1, __Value)
+#define SET_TX_DESC_NEXTHEADPAGE_8192F(__pTxDesc, __Value) \
+	SET_BITS_TO_LE_4BYTE(__pTxDesc+32, 16, 8, __Value)
+#define SET_TX_DESC_TAILPAGE_8192F(__pTxDesc, __Value) \
+	SET_BITS_TO_LE_4BYTE(__pTxDesc+32, 24, 8, __Value)
+
+/* Dword 9 */
+#define SET_TX_DESC_PADDING_LEN_8192F(__pTxDesc, __Value) \
+	SET_BITS_TO_LE_4BYTE(__pTxDesc+36, 0, 11, __Value)
+#define SET_TX_DESC_SEQ_8192F(__pTxDesc, __Value) \
+	SET_BITS_TO_LE_4BYTE(__pTxDesc+36, 12, 12, __Value)
+#define SET_TX_DESC_FINAL_DATA_RATE_8192F(__pTxDesc, __Value) \
+	SET_BITS_TO_LE_4BYTE(__pTxDesc+36, 24, 8, __Value)
+
+
+#define SET_EARLYMODE_PKTNUM_8192F(__pAddr, __Value)					SET_BITS_TO_LE_4BYTE(__pAddr, 0, 4, __Value)
+#define SET_EARLYMODE_LEN0_8192F(__pAddr, __Value)					SET_BITS_TO_LE_4BYTE(__pAddr, 4, 15, __Value)
+#define SET_EARLYMODE_LEN1_1_8192F(__pAddr, __Value)					SET_BITS_TO_LE_4BYTE(__pAddr, 19, 13, __Value)
+#define SET_EARLYMODE_LEN1_2_8192F(__pAddr, __Value)					SET_BITS_TO_LE_4BYTE(__pAddr+4, 0, 2, __Value)
+#define SET_EARLYMODE_LEN2_8192F(__pAddr, __Value)					SET_BITS_TO_LE_4BYTE(__pAddr+4, 2, 15,	__Value)
+#define SET_EARLYMODE_LEN3_8192F(__pAddr, __Value)					SET_BITS_TO_LE_4BYTE(__pAddr+4, 17, 15, __Value)
+
+
+/*-----------------------------------------------------------------*/
+/*	RTL8192F TX BUFFER DESC                                      */
+/*-----------------------------------------------------------------*/
+#ifdef CONFIG_64BIT_DMA
+	#define SET_TXBUFFER_DESC_LEN_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc+((__Offset)*16), 0, 16, __Valeu)
+	#define SET_TXBUFFER_DESC_AMSDU_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc+((__Offset)*16), 31, 1, __Valeu)
+	#define SET_TXBUFFER_DESC_ADD_LOW_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc+((__Offset)*16)+4, 0, 32, __Valeu)
+	#define SET_TXBUFFER_DESC_ADD_HIGT_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc+((__Offset)*16)+8, 0, 32, __Valeu)
+#else
+	#define SET_TXBUFFER_DESC_LEN_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc+(__Offset*8), 0, 16, __Valeu)
+	#define SET_TXBUFFER_DESC_AMSDU_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc+(__Offset*8), 31, 1, __Valeu)
+	#define SET_TXBUFFER_DESC_ADD_LOW_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc+(__Offset*8)+4, 0, 32, __Valeu)
+	#define SET_TXBUFFER_DESC_ADD_HIGT_WITH_OFFSET(__pTxDesc, __Offset, __Valeu)	/* 64 BIT mode only */
+#endif
+/* ********************************************************* */
+
+/* 64 bits  -- 32 bits */
+/* =======     ======= */
+/* Dword 0     0 */
+#define SET_TX_BUFF_DESC_LEN_0_8192F(__pTxDesc, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc, 0, 14, __Valeu)
+#define SET_TX_BUFF_DESC_PSB_8192F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 16, 15, __Value)
+#define SET_TX_BUFF_DESC_OWN_8192F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 31, 1, __Value)
+
+/* Dword 1     1 */
+#define SET_TX_BUFF_DESC_ADDR_LOW_0_8192F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 0, 32, __Value)
+#define GET_TX_BUFF_DESC_ADDR_LOW_0_8192F(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc+4, 0, 32)
+/* Dword 2     NA */
+#define SET_TX_BUFF_DESC_ADDR_HIGH_0_8192F(__pTxDesc, __Value) SET_TXBUFFER_DESC_ADD_HIGT_WITH_OFFSET(__pTxDesc, 0, __Value)
+#ifdef CONFIG_64BIT_DMA
+	#define GET_TX_BUFF_DESC_ADDR_HIGH_0_8192F(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc+8, 0, 32)
+#else
+	#define GET_TX_BUFF_DESC_ADDR_HIGH_0_8192F(__pTxDesc) 0
+#endif
+/* Dword 3     NA */
+/* RESERVED 0 */
+/* Dword 4     2 */
+#define SET_TX_BUFF_DESC_LEN_1_8192F(__pTxDesc, __Value) SET_TXBUFFER_DESC_LEN_WITH_OFFSET(__pTxDesc, 1, __Value)
+#define SET_TX_BUFF_DESC_AMSDU_1_8192F(__pTxDesc, __Value) SET_TXBUFFER_DESC_AMSDU_WITH_OFFSET(__pTxDesc, 1, __Value)
+/* Dword 5     3 */
+#define SET_TX_BUFF_DESC_ADDR_LOW_1_8192F(__pTxDesc, __Value) SET_TXBUFFER_DESC_ADD_LOW_WITH_OFFSET(__pTxDesc, 1, __Value)
+/* Dword 6     NA */
+#define SET_TX_BUFF_DESC_ADDR_HIGH_1_8192F(__pTxDesc, __Value) SET_TXBUFFER_DESC_ADD_HIGT_WITH_OFFSET(__pTxDesc, 1, __Value)
+/* Dword 7     NA */
+/*RESERVED 0 */
+/* Dword 8     4 */
+#define SET_TX_BUFF_DESC_LEN_2_8192F(__pTxDesc, __Value) SET_TXBUFFER_DESC_LEN_WITH_OFFSET(__pTxDesc, 2, __Value)
+#define SET_TX_BUFF_DESC_AMSDU_2_8192F(__pTxDesc, __Value) SET_TXBUFFER_DESC_AMSDU_WITH_OFFSET(__pTxDesc, 2, __Value)
+/* Dword 9     5 */
+#define SET_TX_BUFF_DESC_ADDR_LOW_2_8192F(__pTxDesc, __Value) SET_TXBUFFER_DESC_ADD_LOW_WITH_OFFSET(__pTxDesc, 2, __Value)
+/* Dword 10    NA */
+#define SET_TX_BUFF_DESC_ADDR_HIGH_2_8192F(__pTxDesc, __Value) SET_TXBUFFER_DESC_ADD_HIGT_WITH_OFFSET(__pTxDesc, 2, __Value)
+/* Dword 11    NA */
+/*RESERVED 0 */
+/* Dword 12    6 */
+#define SET_TX_BUFF_DESC_LEN_3_8192F(__pTxDesc, __Value) SET_TXBUFFER_DESC_LEN_WITH_OFFSET(__pTxDesc, 3, __Value)
+#define SET_TX_BUFF_DESC_AMSDU_3_8192F(__pTxDesc, __Value) SET_TXBUFFER_DESC_AMSDU_WITH_OFFSET(__pTxDesc, 3, __Value)
+/* Dword 13    7 */
+#define SET_TX_BUFF_DESC_ADDR_LOW_3_8192F(__pTxDesc, __Value) SET_TXBUFFER_DESC_ADD_LOW_WITH_OFFSET(__pTxDesc, 3, __Value)
+/* Dword 14    NA */
+#define SET_TX_BUFF_DESC_ADDR_HIGH_3_8192F(__pTxDesc, __Value) SET_TXBUFFER_DESC_ADD_HIGT_WITH_OFFSET(__pTxDesc, 3, __Value)
+/* Dword 15    NA */
+/*RESERVED 0 */
+
+
+#endif
+/* -----------------------------------------------------------
+ *
+ *	Rate
+ *
+ * -----------------------------------------------------------
+ * CCK Rates, TxHT = 0 */
+#define DESC8192F_RATE1M				0x00
+#define DESC8192F_RATE2M				0x01
+#define DESC8192F_RATE5_5M				0x02
+#define DESC8192F_RATE11M				0x03
+
+/* OFDM Rates, TxHT = 0 */
+#define DESC8192F_RATE6M				0x04
+#define DESC8192F_RATE9M				0x05
+#define DESC8192F_RATE12M				0x06
+#define DESC8192F_RATE18M				0x07
+#define DESC8192F_RATE24M				0x08
+#define DESC8192F_RATE36M				0x09
+#define DESC8192F_RATE48M				0x0a
+#define DESC8192F_RATE54M				0x0b
+
+/* MCS Rates, TxHT = 1 */
+#define DESC8192F_RATEMCS0				0x0c
+#define DESC8192F_RATEMCS1				0x0d
+#define DESC8192F_RATEMCS2				0x0e
+#define DESC8192F_RATEMCS3				0x0f
+#define DESC8192F_RATEMCS4				0x10
+#define DESC8192F_RATEMCS5				0x11
+#define DESC8192F_RATEMCS6				0x12
+#define DESC8192F_RATEMCS7				0x13
+#define DESC8192F_RATEMCS8				0x14
+#define DESC8192F_RATEMCS9				0x15
+#define DESC8192F_RATEMCS10		0x16
+#define DESC8192F_RATEMCS11		0x17
+#define DESC8192F_RATEMCS12		0x18
+#define DESC8192F_RATEMCS13		0x19
+#define DESC8192F_RATEMCS14		0x1a
+#define DESC8192F_RATEMCS15		0x1b
+#define DESC8192F_RATEVHTSS1MCS0		0x2c
+#define DESC8192F_RATEVHTSS1MCS1		0x2d
+#define DESC8192F_RATEVHTSS1MCS2		0x2e
+#define DESC8192F_RATEVHTSS1MCS3		0x2f
+#define DESC8192F_RATEVHTSS1MCS4		0x30
+#define DESC8192F_RATEVHTSS1MCS5		0x31
+#define DESC8192F_RATEVHTSS1MCS6		0x32
+#define DESC8192F_RATEVHTSS1MCS7		0x33
+#define DESC8192F_RATEVHTSS1MCS8		0x34
+#define DESC8192F_RATEVHTSS1MCS9		0x35
+#define DESC8192F_RATEVHTSS2MCS0		0x36
+#define DESC8192F_RATEVHTSS2MCS1		0x37
+#define DESC8192F_RATEVHTSS2MCS2		0x38
+#define DESC8192F_RATEVHTSS2MCS3		0x39
+#define DESC8192F_RATEVHTSS2MCS4		0x3a
+#define DESC8192F_RATEVHTSS2MCS5		0x3b
+#define DESC8192F_RATEVHTSS2MCS6		0x3c
+#define DESC8192F_RATEVHTSS2MCS7		0x3d
+#define DESC8192F_RATEVHTSS2MCS8		0x3e
+#define DESC8192F_RATEVHTSS2MCS9		0x3f
+
+
+#define	RX_HAL_IS_CCK_RATE_8192F(pDesc)\
+	(GET_RX_STATUS_DESC_RX_RATE_8192F(pDesc) == DESC8192F_RATE1M || \
+	 GET_RX_STATUS_DESC_RX_RATE_8192F(pDesc) == DESC8192F_RATE2M || \
+	 GET_RX_STATUS_DESC_RX_RATE_8192F(pDesc) == DESC8192F_RATE5_5M || \
+	 GET_RX_STATUS_DESC_RX_RATE_8192F(pDesc) == DESC8192F_RATE11M)
+
+#ifdef CONFIG_TRX_BD_ARCH
+	struct tx_desc;
+#endif
+
+void rtl8192f_cal_txdesc_chksum(struct tx_desc *ptxdesc);
+void rtl8192f_update_txdesc(struct xmit_frame *pxmitframe, u8 *pmem);
+void rtl8192f_fill_txdesc_sectype(struct pkt_attrib *pattrib, struct tx_desc *ptxdesc);
+void rtl8192f_fill_txdesc_vcs(PADAPTER padapter, struct pkt_attrib *pattrib, struct tx_desc *ptxdesc);
+void rtl8192f_fill_txdesc_phy(PADAPTER padapter, struct pkt_attrib *pattrib, struct tx_desc *ptxdesc);
+void rtl8192f_fill_fake_txdesc(PADAPTER padapter, u8 *pDesc, u32 BufferLen, u8 IsPsPoll, u8 IsBTQosNull, u8 bDataFrame);
+
+#if defined(CONFIG_CONCURRENT_MODE)
+	void fill_txdesc_force_bmc_camid(struct pkt_attrib *pattrib, u8 *ptxdesc);
+#endif
+void fill_txdesc_bmc_tx_rate(struct pkt_attrib *pattrib, u8 *ptxdesc);
+
+#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
+	s32 rtl8192fs_init_xmit_priv(PADAPTER padapter);
+	void rtl8192fs_free_xmit_priv(PADAPTER padapter);
+	s32 rtl8192fs_hal_xmit(PADAPTER padapter, struct xmit_frame *pxmitframe);
+	s32 rtl8192fs_mgnt_xmit(PADAPTER padapter, struct xmit_frame *pmgntframe);
+	s32	rtl8192fs_hal_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe);
+	s32 rtl8192fs_xmit_buf_handler(PADAPTER padapter);
+	thread_return rtl8192fs_xmit_thread(thread_context context);
+	#define hal_xmit_handler rtl8192fs_xmit_buf_handler
+#endif
+
+#ifdef CONFIG_USB_HCI
+	s32 rtl8192fu_init_xmit_priv(PADAPTER padapter);
+	void rtl8192fu_free_xmit_priv(PADAPTER padapter);
+	s32 rtl8192fu_hal_xmit(PADAPTER padapter, struct xmit_frame *pxmitframe);
+	s32 rtl8192fu_mgnt_xmit(PADAPTER padapter, struct xmit_frame *pmgntframe);
+	s32	 rtl8192fu_hal_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe);
+	s32 rtl8192fu_xmit_buf_handler(PADAPTER padapter);
+	#define hal_xmit_handler rtl8192fu_xmit_buf_handler
+	void rtl8192fu_xmit_tasklet(void *priv);
+	s32 rtl8192fu_xmitframe_complete(_adapter *padapter, struct xmit_priv *pxmitpriv, struct xmit_buf *pxmitbuf);
+	void _dbg_dump_tx_info(_adapter	*padapter,int frame_tag,struct tx_desc *ptxdesc);
+#endif
+
+#ifdef CONFIG_PCI_HCI
+	s32 rtl8192fe_init_xmit_priv(PADAPTER padapter);
+	void rtl8192fe_free_xmit_priv(PADAPTER padapter);
+	struct xmit_buf *rtl8192fe_dequeue_xmitbuf(struct rtw_tx_ring *ring);
+	void    rtl8192fe_xmitframe_resume(_adapter *padapter);
+	s32 rtl8192fe_hal_xmit(PADAPTER padapter, struct xmit_frame *pxmitframe);
+	s32 rtl8192fe_mgnt_xmit(PADAPTER padapter, struct xmit_frame *pmgntframe);
+	s32     rtl8192fe_hal_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe);
+	void rtl8192fe_xmit_tasklet(void *priv);
+#endif
+
+u8	BWMapping_8192F(PADAPTER Adapter, struct pkt_attrib *pattrib);
+u8	SCMapping_8192F(PADAPTER Adapter, struct pkt_attrib	*pattrib);
+
+#endif
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/include/rtl8703b_cmd.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/rtl8703b_cmd.h
--- linux-5.6.3/3rdparty/rtl8821ce/include/rtl8703b_cmd.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/rtl8703b_cmd.h	2020-04-10 16:35:06.849661608 +0300
@@ -0,0 +1,205 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#ifndef __RTL8703B_CMD_H__
+#define __RTL8703B_CMD_H__
+
+/* ---------------------------------------------------------------------------------------------------------
+ * ----------------------------------    H2C CMD DEFINITION    ------------------------------------------------
+ * --------------------------------------------------------------------------------------------------------- */
+
+enum h2c_cmd_8703B {
+	/* Common Class: 000 */
+	H2C_8703B_RSVD_PAGE = 0x00,
+	H2C_8703B_MEDIA_STATUS_RPT = 0x01,
+	H2C_8703B_SCAN_ENABLE = 0x02,
+	H2C_8703B_KEEP_ALIVE = 0x03,
+	H2C_8703B_DISCON_DECISION = 0x04,
+	H2C_8703B_PSD_OFFLOAD = 0x05,
+	H2C_8703B_AP_OFFLOAD = 0x08,
+	H2C_8703B_BCN_RSVDPAGE = 0x09,
+	H2C_8703B_PROBERSP_RSVDPAGE = 0x0A,
+	H2C_8703B_FCS_RSVDPAGE = 0x10,
+	H2C_8703B_FCS_INFO = 0x11,
+	H2C_8703B_AP_WOW_GPIO_CTRL = 0x13,
+
+	/* PoweSave Class: 001 */
+	H2C_8703B_SET_PWR_MODE = 0x20,
+	H2C_8703B_PS_TUNING_PARA = 0x21,
+	H2C_8703B_PS_TUNING_PARA2 = 0x22,
+	H2C_8703B_P2P_LPS_PARAM = 0x23,
+	H2C_8703B_P2P_PS_OFFLOAD = 0x24,
+	H2C_8703B_PS_SCAN_ENABLE = 0x25,
+	H2C_8703B_SAP_PS_ = 0x26,
+	H2C_8703B_INACTIVE_PS_ = 0x27, /* Inactive_PS */
+	H2C_8703B_FWLPS_IN_IPS_ = 0x28,
+
+	/* Dynamic Mechanism Class: 010 */
+	H2C_8703B_MACID_CFG = 0x40,
+	H2C_8703B_TXBF = 0x41,
+	H2C_8703B_RSSI_SETTING = 0x42,
+	H2C_8703B_AP_REQ_TXRPT = 0x43,
+	H2C_8703B_INIT_RATE_COLLECT = 0x44,
+	H2C_8703B_RA_PARA_ADJUST = 0x46,
+
+	/* BT Class: 011 */
+	H2C_8703B_B_TYPE_TDMA = 0x60,
+	H2C_8703B_BT_INFO = 0x61,
+	H2C_8703B_FORCE_BT_TXPWR = 0x62,
+	H2C_8703B_BT_IGNORE_WLANACT = 0x63,
+	H2C_8703B_DAC_SWING_VALUE = 0x64,
+	H2C_8703B_ANT_SEL_RSV = 0x65,
+	H2C_8703B_WL_OPMODE = 0x66,
+	H2C_8703B_BT_MP_OPER = 0x67,
+	H2C_8703B_BT_CONTROL = 0x68,
+	H2C_8703B_BT_WIFI_CTRL = 0x69,
+	H2C_8703B_BT_FW_PATCH = 0x6A,
+	H2C_8703B_BT_WLAN_CALIBRATION = 0x6D,
+
+	/* WOWLAN Class: 100 */
+	H2C_8703B_WOWLAN = 0x80,
+	H2C_8703B_REMOTE_WAKE_CTRL = 0x81,
+	H2C_8703B_AOAC_GLOBAL_INFO = 0x82,
+	H2C_8703B_AOAC_RSVD_PAGE = 0x83,
+	H2C_8703B_AOAC_RSVD_PAGE2 = 0x84,
+	H2C_8703B_D0_SCAN_OFFLOAD_CTRL = 0x85,
+	H2C_8703B_D0_SCAN_OFFLOAD_INFO = 0x86,
+	H2C_8703B_CHNL_SWITCH_OFFLOAD = 0x87,
+	H2C_8703B_P2P_OFFLOAD_RSVD_PAGE = 0x8A,
+	H2C_8703B_P2P_OFFLOAD = 0x8B,
+
+	H2C_8703B_RESET_TSF = 0xC0,
+	H2C_8703B_MAXID,
+};
+
+/* ---------------------------------------------------------------------------------------------------------
+ * ----------------------------------    H2C CMD CONTENT    --------------------------------------------------
+ * ---------------------------------------------------------------------------------------------------------
+ * _RSVDPAGE_LOC_CMD_0x00 */
+#define SET_8703B_H2CCMD_RSVDPAGE_LOC_PROBE_RSP(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
+#define SET_8703B_H2CCMD_RSVDPAGE_LOC_PSPOLL(__pH2CCmd, __Value)				SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 8, __Value)
+#define SET_8703B_H2CCMD_RSVDPAGE_LOC_NULL_DATA(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value)
+#define SET_8703B_H2CCMD_RSVDPAGE_LOC_QOS_NULL_DATA(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 8, __Value)
+#define SET_8703B_H2CCMD_RSVDPAGE_LOC_BT_QOS_NULL_DATA(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 0, 8, __Value)
+
+/* _KEEP_ALIVE_CMD_0x03 */
+#define SET_8703B_H2CCMD_KEEPALIVE_PARM_ENABLE(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 1, __Value)
+#define SET_8703B_H2CCMD_KEEPALIVE_PARM_ADOPT(__pH2CCmd, __Value)				SET_BITS_TO_LE_1BYTE(__pH2CCmd, 1, 1, __Value)
+#define SET_8703B_H2CCMD_KEEPALIVE_PARM_PKT_TYPE(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE(__pH2CCmd, 2, 1, __Value)
+#define SET_8703B_H2CCMD_KEEPALIVE_PARM_CHECK_PERIOD(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 0, 8, __Value)
+
+/* _DISCONNECT_DECISION_CMD_0x04 */
+#define SET_8703B_H2CCMD_DISCONDECISION_PARM_ENABLE(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 1, __Value)
+#define SET_8703B_H2CCMD_DISCONDECISION_PARM_ADOPT(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE(__pH2CCmd, 1, 1, __Value)
+#define SET_8703B_H2CCMD_DISCONDECISION_PARM_CHECK_PERIOD(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 0, 8, __Value)
+#define SET_8703B_H2CCMD_DISCONDECISION_PARM_TRY_PKT_NUM(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 0, 8, __Value)
+
+/* _PWR_MOD_CMD_0x20 */
+#define SET_8703B_H2CCMD_PWRMODE_PARM_MODE(__pH2CCmd, __Value)				SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
+#define SET_8703B_H2CCMD_PWRMODE_PARM_RLBM(__pH2CCmd, __Value)				SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 4, __Value)
+#define SET_8703B_H2CCMD_PWRMODE_PARM_SMART_PS(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 4, 4, __Value)
+#define SET_8703B_H2CCMD_PWRMODE_PARM_BCN_PASS_TIME(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value)
+#define SET_8703B_H2CCMD_PWRMODE_PARM_ALL_QUEUE_UAPSD(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 8, __Value)
+#define SET_8703B_H2CCMD_PWRMODE_PARM_BCN_EARLY_C2H_RPT(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 2, 1, __Value)
+#define SET_8703B_H2CCMD_PWRMODE_PARM_PWR_STATE(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 0, 8, __Value)
+
+#define GET_8703B_H2CCMD_PWRMODE_PARM_MODE(__pH2CCmd)					LE_BITS_TO_1BYTE(__pH2CCmd, 0, 8)
+
+/* _PS_TUNE_PARAM_CMD_0x21 */
+#define SET_8703B_H2CCMD_PSTUNE_PARM_BCN_TO_LIMIT(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
+#define SET_8703B_H2CCMD_PSTUNE_PARM_DTIM_TIMEOUT(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 0, 8, __Value)
+#define SET_8703B_H2CCMD_PSTUNE_PARM_ADOPT(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 0, 1, __Value)
+#define SET_8703B_H2CCMD_PSTUNE_PARM_PS_TIMEOUT(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 1, 7, __Value)
+#define SET_8703B_H2CCMD_PSTUNE_PARM_DTIM_PERIOD(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE(__pH2CCmd+3, 0, 8, __Value)
+
+/* _MACID_CFG_CMD_0x40 */
+#define SET_8703B_H2CCMD_MACID_CFG_MACID(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
+#define SET_8703B_H2CCMD_MACID_CFG_RAID(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 0, 5, __Value)
+#define SET_8703B_H2CCMD_MACID_CFG_SGI_EN(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 7, 1, __Value)
+#define SET_8703B_H2CCMD_MACID_CFG_BW(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 0, 2, __Value)
+#define SET_8703B_H2CCMD_MACID_CFG_NO_UPDATE(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 3, 1, __Value)
+#define SET_8703B_H2CCMD_MACID_CFG_VHT_EN(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 4, 2, __Value)
+#define SET_8703B_H2CCMD_MACID_CFG_DISPT(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 6, 1, __Value)
+#define SET_8703B_H2CCMD_MACID_CFG_DISRA(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 7, 1, __Value)
+#define SET_8703B_H2CCMD_MACID_CFG_RATE_MASK0(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd+3, 0, 8, __Value)
+#define SET_8703B_H2CCMD_MACID_CFG_RATE_MASK1(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd+4, 0, 8, __Value)
+#define SET_8703B_H2CCMD_MACID_CFG_RATE_MASK2(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd+5, 0, 8, __Value)
+#define SET_8703B_H2CCMD_MACID_CFG_RATE_MASK3(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd+6, 0, 8, __Value)
+
+/* _RSSI_SETTING_CMD_0x42 */
+#define SET_8703B_H2CCMD_RSSI_SETTING_MACID(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
+#define SET_8703B_H2CCMD_RSSI_SETTING_RSSI(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 0, 7, __Value)
+#define SET_8703B_H2CCMD_RSSI_SETTING_ULDL_STATE(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd+3, 0, 8, __Value)
+
+/* _AP_REQ_TXRPT_CMD_0x43 */
+#define SET_8703B_H2CCMD_APREQRPT_PARM_MACID1(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
+#define SET_8703B_H2CCMD_APREQRPT_PARM_MACID2(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 0, 8, __Value)
+
+/* _FORCE_BT_TXPWR_CMD_0x62 */
+#define SET_8703B_H2CCMD_BT_PWR_IDX(__pH2CCmd, __Value)							SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
+
+/* _FORCE_BT_MP_OPER_CMD_0x67 */
+#define SET_8703B_H2CCMD_BT_MPOPER_VER(__pH2CCmd, __Value)							SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 4, __Value)
+#define SET_8703B_H2CCMD_BT_MPOPER_REQNUM(__pH2CCmd, __Value)							SET_BITS_TO_LE_1BYTE(__pH2CCmd, 4, 4, __Value)
+#define SET_8703B_H2CCMD_BT_MPOPER_IDX(__pH2CCmd, __Value)							SET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 0, 8, __Value)
+#define SET_8703B_H2CCMD_BT_MPOPER_PARAM1(__pH2CCmd, __Value)							SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 0, 8, __Value)
+#define SET_8703B_H2CCMD_BT_MPOPER_PARAM2(__pH2CCmd, __Value)							SET_BITS_TO_LE_1BYTE(__pH2CCmd+3, 0, 8, __Value)
+#define SET_8703B_H2CCMD_BT_MPOPER_PARAM3(__pH2CCmd, __Value)							SET_BITS_TO_LE_1BYTE(__pH2CCmd+4, 0, 8, __Value)
+
+/* _BT_FW_PATCH_0x6A */
+#define SET_8703B_H2CCMD_BT_FW_PATCH_SIZE(__pH2CCmd, __Value)					SET_BITS_TO_LE_2BYTE((pu1Byte)(__pH2CCmd), 0, 16, __Value)
+#define SET_8703B_H2CCMD_BT_FW_PATCH_ADDR0(__pH2CCmd, __Value)					SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value)
+#define SET_8703B_H2CCMD_BT_FW_PATCH_ADDR1(__pH2CCmd, __Value)					SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 8, __Value)
+#define SET_8703B_H2CCMD_BT_FW_PATCH_ADDR2(__pH2CCmd, __Value)					SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 0, 8, __Value)
+#define SET_8703B_H2CCMD_BT_FW_PATCH_ADDR3(__pH2CCmd, __Value)					SET_BITS_TO_LE_1BYTE((__pH2CCmd)+5, 0, 8, __Value)
+
+/* ---------------------------------------------------------------------------------------------------------
+ * -------------------------------------------    Structure    --------------------------------------------------
+ * --------------------------------------------------------------------------------------------------------- */
+
+
+/* ---------------------------------------------------------------------------------------------------------
+ * ----------------------------------    Function Statement     --------------------------------------------------
+ * --------------------------------------------------------------------------------------------------------- */
+
+/* host message to firmware cmd */
+void rtl8703b_set_FwPwrMode_cmd(PADAPTER padapter, u8 Mode);
+void rtl8703b_set_FwJoinBssRpt_cmd(PADAPTER padapter, u8 mstatus);
+void rtl8703b_fw_try_ap_cmd(PADAPTER padapter, u32 need_ack);
+/* s32 rtl8703b_set_lowpwr_lps_cmd(PADAPTER padapter, u8 enable); */
+void rtl8703b_set_FwPsTuneParam_cmd(PADAPTER padapter);
+void rtl8703b_set_FwBtMpOper_cmd(PADAPTER padapter, u8 idx, u8 ver, u8 reqnum, u8 *param);
+void rtl8703b_download_rsvd_page(PADAPTER padapter, u8 mstatus);
+#ifdef CONFIG_BT_COEXIST
+	void rtl8703b_download_BTCoex_AP_mode_rsvd_page(PADAPTER padapter);
+#endif /* CONFIG_BT_COEXIST */
+#ifdef CONFIG_P2P
+	void rtl8703b_set_p2p_ps_offload_cmd(PADAPTER padapter, u8 p2p_ps_state);
+#endif /* CONFIG_P2P */
+
+#ifdef CONFIG_TDLS
+	#ifdef CONFIG_TDLS_CH_SW
+		void rtl8703b_set_BcnEarly_C2H_Rpt_cmd(PADAPTER padapter, u8 enable);
+	#endif
+#endif
+
+#ifdef CONFIG_P2P_WOWLAN
+	void rtl8703b_set_p2p_wowlan_offload_cmd(PADAPTER padapter);
+#endif
+
+void rtl8703b_set_FwPwrModeInIPS_cmd(PADAPTER padapter, u8 cmd_param);
+
+s32 FillH2CCmd8703B(PADAPTER padapter, u8 ElementID, u32 CmdLen, u8 *pCmdBuffer);
+u8 GetTxBufferRsvdPageNum8703B(_adapter *padapter, bool wowlan);
+#endif
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/include/rtl8703b_dm.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/rtl8703b_dm.h
--- linux-5.6.3/3rdparty/rtl8821ce/include/rtl8703b_dm.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/rtl8703b_dm.h	2020-04-10 16:35:06.849661608 +0300
@@ -0,0 +1,39 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#ifndef __RTL8703B_DM_H__
+#define __RTL8703B_DM_H__
+/* ************************************************************
+ * Description:
+ *
+ * This file is for 8703B dynamic mechanism only
+ *
+ *
+ * ************************************************************ */
+
+/* ************************************************************
+ * structure and define
+ * ************************************************************ */
+
+/* ************************************************************
+ * function prototype
+ * ************************************************************ */
+
+void rtl8703b_init_dm_priv(PADAPTER padapter);
+void rtl8703b_deinit_dm_priv(PADAPTER padapter);
+
+void rtl8703b_InitHalDm(PADAPTER padapter);
+void rtl8703b_HalDmWatchDog(PADAPTER padapter);
+
+#endif
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/include/rtl8703b_hal.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/rtl8703b_hal.h
--- linux-5.6.3/3rdparty/rtl8821ce/include/rtl8703b_hal.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/rtl8703b_hal.h	2020-04-10 16:35:06.849661608 +0300
@@ -0,0 +1,266 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#ifndef __RTL8703B_HAL_H__
+#define __RTL8703B_HAL_H__
+
+#include "hal_data.h"
+
+#include "rtl8703b_spec.h"
+#include "rtl8703b_rf.h"
+#include "rtl8703b_dm.h"
+#include "rtl8703b_recv.h"
+#include "rtl8703b_xmit.h"
+#include "rtl8703b_cmd.h"
+#include "rtl8703b_led.h"
+#include "Hal8703BPwrSeq.h"
+#include "Hal8703BPhyReg.h"
+#include "Hal8703BPhyCfg.h"
+#ifdef DBG_CONFIG_ERROR_DETECT
+	#include "rtl8703b_sreset.h"
+#endif
+
+#define FW_8703B_SIZE			0x8000
+#define FW_8703B_START_ADDRESS	0x1000
+#define FW_8703B_END_ADDRESS		0x1FFF /* 0x5FFF */
+
+#define IS_FW_HEADER_EXIST_8703B(_pFwHdr)	((le16_to_cpu(_pFwHdr->Signature) & 0xFFF0) == 0x03B0)
+
+typedef struct _RT_FIRMWARE {
+	FIRMWARE_SOURCE	eFWSource;
+#ifdef CONFIG_EMBEDDED_FWIMG
+	u8			*szFwBuffer;
+#else
+	u8			szFwBuffer[FW_8703B_SIZE];
+#endif
+	u32			ulFwLength;
+} RT_FIRMWARE_8703B, *PRT_FIRMWARE_8703B;
+
+/*
+ * This structure must be cared byte-ordering
+ *
+ * Added by tynli. 2009.12.04. */
+typedef struct _RT_8703B_FIRMWARE_HDR {
+	/* 8-byte alinment required */
+
+	/* --- LONG WORD 0 ---- */
+	u16		Signature;	/* 92C0: test chip; 92C, 88C0: test chip; 88C1: MP A-cut; 92C1: MP A-cut */
+	u8		Category;	/* AP/NIC and USB/PCI */
+	u8		Function;	/* Reserved for different FW function indcation, for further use when driver needs to download different FW in different conditions */
+	u16		Version;		/* FW Version */
+	u16		Subversion;	/* FW Subversion, default 0x00 */
+
+	/* --- LONG WORD 1 ---- */
+	u8		Month;	/* Release time Month field */
+	u8		Date;	/* Release time Date field */
+	u8		Hour;	/* Release time Hour field */
+	u8		Minute;	/* Release time Minute field */
+	u16		RamCodeSize;	/* The size of RAM code */
+	u16		Rsvd2;
+
+	/* --- LONG WORD 2 ---- */
+	u32		SvnIdx;	/* The SVN entry index */
+	u32		Rsvd3;
+
+	/* --- LONG WORD 3 ---- */
+	u32		Rsvd4;
+	u32		Rsvd5;
+} RT_8703B_FIRMWARE_HDR, *PRT_8703B_FIRMWARE_HDR;
+
+#define DRIVER_EARLY_INT_TIME_8703B		0x05
+#define BCN_DMA_ATIME_INT_TIME_8703B		0x02
+
+/* for 8703B
+ * TX 32K, RX 16K, Page size 128B for TX, 8B for RX */
+#define PAGE_SIZE_TX_8703B			128
+#define PAGE_SIZE_RX_8703B			8
+
+#define TX_DMA_SIZE_8703B			0x8000	/* 32K(TX) */
+#define RX_DMA_SIZE_8703B			0x4000	/* 16K(RX) */
+
+#ifdef CONFIG_WOWLAN
+	#define RESV_FMWF	(WKFMCAM_SIZE * MAX_WKFM_CAM_NUM) /* 16 entries, for each is 24 bytes*/
+#else
+	#define RESV_FMWF	0
+#endif
+
+#ifdef CONFIG_FW_C2H_DEBUG
+	#define RX_DMA_RESERVED_SIZE_8703B	0x100	/* 256B, reserved for c2h debug message */
+#else
+	#define RX_DMA_RESERVED_SIZE_8703B	0x80	/* 128B, reserved for tx report */
+#endif
+#define RX_DMA_BOUNDARY_8703B		(RX_DMA_SIZE_8703B - RX_DMA_RESERVED_SIZE_8703B - 1)
+
+
+/* Note: We will divide number of page equally for each queue other than public queue! */
+
+/* For General Reserved Page Number(Beacon Queue is reserved page)
+ * Beacon:MAX_BEACON_LEN/PAGE_SIZE_TX_8703B
+ * PS-Poll:1, Null Data:1,Qos Null Data:1,BT Qos Null Data:1,CTS-2-SELF,LTE QoS Null*/
+
+#define BCNQ_PAGE_NUM_8703B		(MAX_BEACON_LEN/PAGE_SIZE_TX_8703B + 6) /*0x08*/
+
+/* For WoWLan , more reserved page
+ * ARP Rsp:1, RWC:1, GTK Info:1,GTK RSP:2,GTK EXT MEM:2, AOAC rpt: 1 PNO: 6
+ * NS offload: 2NDP info: 1
+ */
+#ifdef CONFIG_WOWLAN
+	#define WOWLAN_PAGE_NUM_8703B	0x0b
+#else
+	#define WOWLAN_PAGE_NUM_8703B	0x00
+#endif
+
+#ifdef CONFIG_PNO_SUPPORT
+	#undef WOWLAN_PAGE_NUM_8703B
+	#define WOWLAN_PAGE_NUM_8703B	0x15
+#endif
+
+#ifdef CONFIG_AP_WOWLAN
+	#define AP_WOWLAN_PAGE_NUM_8703B	0x02
+#endif
+
+#define TX_TOTAL_PAGE_NUMBER_8703B	(0xFF - BCNQ_PAGE_NUM_8703B - WOWLAN_PAGE_NUM_8703B)
+#define TX_PAGE_BOUNDARY_8703B		(TX_TOTAL_PAGE_NUMBER_8703B + 1)
+
+#define WMM_NORMAL_TX_TOTAL_PAGE_NUMBER_8703B	TX_TOTAL_PAGE_NUMBER_8703B
+#define WMM_NORMAL_TX_PAGE_BOUNDARY_8703B		(WMM_NORMAL_TX_TOTAL_PAGE_NUMBER_8703B + 1)
+
+/* For Normal Chip Setting
+ * (HPQ + LPQ + NPQ + PUBQ) shall be TX_TOTAL_PAGE_NUMBER_8703B */
+#define NORMAL_PAGE_NUM_HPQ_8703B		0x0C
+#define NORMAL_PAGE_NUM_LPQ_8703B		0x02
+#define NORMAL_PAGE_NUM_NPQ_8703B		0x02
+
+/* Note: For Normal Chip Setting, modify later */
+#define WMM_NORMAL_PAGE_NUM_HPQ_8703B		0x30
+#define WMM_NORMAL_PAGE_NUM_LPQ_8703B		0x20
+#define WMM_NORMAL_PAGE_NUM_NPQ_8703B		0x20
+
+
+#include "HalVerDef.h"
+#include "hal_com.h"
+
+#define EFUSE_OOB_PROTECT_BYTES		15
+
+#define HAL_EFUSE_MEMORY
+
+#define HWSET_MAX_SIZE_8703B			256
+#define EFUSE_REAL_CONTENT_LEN_8703B		256
+#define EFUSE_MAP_LEN_8703B				512
+#define EFUSE_MAX_SECTION_8703B			64
+
+#define EFUSE_IC_ID_OFFSET			506	/* For some inferiority IC purpose. added by Roger, 2009.09.02. */
+#define AVAILABLE_EFUSE_ADDR(addr)	(addr < EFUSE_REAL_CONTENT_LEN_8703B)
+
+#define EFUSE_ACCESS_ON			0x69
+#define EFUSE_ACCESS_OFF			0x00
+
+/* ********************************************************
+ *			EFUSE for BT definition
+ * ******************************************************** */
+#define BANK_NUM		1
+#define EFUSE_BT_REAL_BANK_CONTENT_LEN	128
+#define EFUSE_BT_REAL_CONTENT_LEN		(EFUSE_BT_REAL_BANK_CONTENT_LEN * BANK_NUM)
+#define EFUSE_BT_MAP_LEN				1024	/* 1k bytes */
+#define EFUSE_BT_MAX_SECTION			(EFUSE_BT_MAP_LEN / 8)
+#define EFUSE_PROTECT_BYTES_BANK		16
+
+typedef enum tag_Package_Definition {
+	PACKAGE_DEFAULT,
+	PACKAGE_QFN68,
+	PACKAGE_TFBGA90,
+	PACKAGE_TFBGA80,
+	PACKAGE_TFBGA79
+} PACKAGE_TYPE_E;
+
+#define INCLUDE_MULTI_FUNC_BT(_Adapter)		(GET_HAL_DATA(_Adapter)->MultiFunc & RT_MULTI_FUNC_BT)
+#define INCLUDE_MULTI_FUNC_GPS(_Adapter)	(GET_HAL_DATA(_Adapter)->MultiFunc & RT_MULTI_FUNC_GPS)
+
+/* rtl8703b_hal_init.c */
+s32 rtl8703b_FirmwareDownload(PADAPTER padapter, BOOLEAN  bUsedWoWLANFw);
+void rtl8703b_FirmwareSelfReset(PADAPTER padapter);
+void rtl8703b_InitializeFirmwareVars(PADAPTER padapter);
+
+void rtl8703b_InitAntenna_Selection(PADAPTER padapter);
+void rtl8703b_DeinitAntenna_Selection(PADAPTER padapter);
+void rtl8703b_CheckAntenna_Selection(PADAPTER padapter);
+void rtl8703b_init_default_value(PADAPTER padapter);
+
+s32 rtl8703b_InitLLTTable(PADAPTER padapter);
+
+s32 CardDisableHWSM(PADAPTER padapter, u8 resetMCU);
+s32 CardDisableWithoutHWSM(PADAPTER padapter);
+
+/* EFuse */
+u8 GetEEPROMSize8703B(PADAPTER padapter);
+void Hal_InitPGData(PADAPTER padapter, u8 *PROMContent);
+void Hal_EfuseParseIDCode(PADAPTER padapter, u8 *hwinfo);
+void Hal_EfuseParseTxPowerInfo_8703B(PADAPTER padapter, u8 *PROMContent, BOOLEAN AutoLoadFail);
+void Hal_EfuseParseBTCoexistInfo_8703B(PADAPTER padapter, u8 *hwinfo, BOOLEAN AutoLoadFail);
+void Hal_EfuseParseEEPROMVer_8703B(PADAPTER padapter, u8 *hwinfo, BOOLEAN AutoLoadFail);
+void Hal_EfuseParseChnlPlan_8703B(PADAPTER padapter, u8 *hwinfo, BOOLEAN AutoLoadFail);
+void Hal_EfuseParseCustomerID_8703B(PADAPTER padapter, u8 *hwinfo, BOOLEAN AutoLoadFail);
+void Hal_EfuseParseAntennaDiversity_8703B(PADAPTER padapter, u8 *hwinfo, BOOLEAN AutoLoadFail);
+void Hal_EfuseParseXtal_8703B(PADAPTER pAdapter, u8 *hwinfo, u8 AutoLoadFail);
+void Hal_EfuseParseThermalMeter_8703B(PADAPTER padapter, u8 *hwinfo, u8 AutoLoadFail);
+VOID Hal_EfuseParseVoltage_8703B(PADAPTER pAdapter, u8 *hwinfo, BOOLEAN	AutoLoadFail);
+VOID Hal_EfuseParseBoardType_8703B(PADAPTER Adapter,	u8	*PROMContent, BOOLEAN AutoloadFail);
+
+void rtl8703b_set_hal_ops(struct hal_ops *pHalFunc);
+void init_hal_spec_8703b(_adapter *adapter);
+u8 SetHwReg8703B(PADAPTER padapter, u8 variable, u8 *val);
+void GetHwReg8703B(PADAPTER padapter, u8 variable, u8 *val);
+u8 SetHalDefVar8703B(PADAPTER padapter, HAL_DEF_VARIABLE variable, void *pval);
+u8 GetHalDefVar8703B(PADAPTER padapter, HAL_DEF_VARIABLE variable, void *pval);
+
+/* register */
+void rtl8703b_InitBeaconParameters(PADAPTER padapter);
+void rtl8703b_InitBeaconMaxError(PADAPTER padapter, u8 InfraMode);
+void	_InitBurstPktLen_8703BS(PADAPTER Adapter);
+void _InitLTECoex_8703BS(PADAPTER Adapter);
+void _InitMacAPLLSetting_8703B(PADAPTER Adapter);
+void _8051Reset8703(PADAPTER padapter);
+#ifdef CONFIG_WOWLAN
+	void Hal_DetectWoWMode(PADAPTER pAdapter);
+#endif /* CONFIG_WOWLAN */
+
+void rtl8703b_start_thread(_adapter *padapter);
+void rtl8703b_stop_thread(_adapter *padapter);
+
+#if defined(CONFIG_CHECK_BT_HANG) && defined(CONFIG_BT_COEXIST)
+	void rtl8703bs_init_checkbthang_workqueue(_adapter *adapter);
+	void rtl8703bs_free_checkbthang_workqueue(_adapter *adapter);
+	void rtl8703bs_cancle_checkbthang_workqueue(_adapter *adapter);
+	void rtl8703bs_hal_check_bt_hang(_adapter *adapter);
+#endif
+
+#ifdef CONFIG_GPIO_WAKEUP
+	void HalSetOutPutGPIO(PADAPTER padapter, u8 index, u8 OutPutValue);
+#endif
+#ifdef CONFIG_MP_INCLUDED
+int FirmwareDownloadBT(IN PADAPTER Adapter, PRT_MP_FIRMWARE pFirmware);
+#endif
+void CCX_FwC2HTxRpt_8703b(PADAPTER padapter, u8 *pdata, u8 len);
+
+u8 MRateToHwRate8703B(u8  rate);
+u8 HwRateToMRate8703B(u8	 rate);
+
+void Hal_ReadRFGainOffset(PADAPTER pAdapter, u8 *hwinfo, BOOLEAN AutoLoadFail);
+
+#ifdef CONFIG_PCI_HCI
+	BOOLEAN	InterruptRecognized8703BE(PADAPTER Adapter);
+	VOID	UpdateInterruptMask8703BE(PADAPTER Adapter, u32 AddMSR, u32 AddMSR1, u32 RemoveMSR, u32 RemoveMSR1);
+#endif
+
+#endif
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/include/rtl8703b_led.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/rtl8703b_led.h
--- linux-5.6.3/3rdparty/rtl8821ce/include/rtl8703b_led.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/rtl8703b_led.h	2020-04-10 16:35:06.849661608 +0300
@@ -0,0 +1,44 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#ifndef __RTL8703B_LED_H__
+#define __RTL8703B_LED_H__
+
+#include <drv_conf.h>
+#include <osdep_service.h>
+#include <drv_types.h>
+
+#ifdef CONFIG_RTW_SW_LED
+/* ********************************************************************************
+ * Interface to manipulate LED objects.
+ * ******************************************************************************** */
+#ifdef CONFIG_USB_HCI
+	void rtl8703bu_InitSwLeds(PADAPTER padapter);
+	void rtl8703bu_DeInitSwLeds(PADAPTER padapter);
+#endif
+#ifdef CONFIG_SDIO_HCI
+	void rtl8703bs_InitSwLeds(PADAPTER padapter);
+	void rtl8703bs_DeInitSwLeds(PADAPTER padapter);
+#endif
+#ifdef CONFIG_GSPI_HCI
+	void rtl8703bs_InitSwLeds(PADAPTER padapter);
+	void rtl8703bs_DeInitSwLeds(PADAPTER padapter);
+#endif
+#ifdef CONFIG_PCI_HCI
+	void rtl8703be_InitSwLeds(PADAPTER padapter);
+	void rtl8703be_DeInitSwLeds(PADAPTER padapter);
+#endif
+
+#endif/*CONFIG_RTW_SW_LED*/
+#endif /*__RTL8703B_LED_H__*/
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/include/rtl8703b_recv.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/rtl8703b_recv.h
--- linux-5.6.3/3rdparty/rtl8821ce/include/rtl8703b_recv.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/rtl8703b_recv.h	2020-04-10 16:35:06.849661608 +0300
@@ -0,0 +1,86 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#ifndef __RTL8703B_RECV_H__
+#define __RTL8703B_RECV_H__
+
+#define RECV_BLK_SZ 512
+#define RECV_BLK_CNT 16
+#define RECV_BLK_TH RECV_BLK_CNT
+
+#if defined(CONFIG_USB_HCI)
+
+	#ifndef MAX_RECVBUF_SZ
+		#ifdef PLATFORM_OS_CE
+			#define MAX_RECVBUF_SZ (8192+1024) /* 8K+1k */
+		#else
+			#ifndef CONFIG_MINIMAL_MEMORY_USAGE
+				/* #define MAX_RECVBUF_SZ (32768) */ /* 32k */
+				/* #define MAX_RECVBUF_SZ (16384) */ /* 16K */
+				/* #define MAX_RECVBUF_SZ (10240) */ /* 10K */
+				#ifdef CONFIG_PLATFORM_MSTAR
+					#define MAX_RECVBUF_SZ (8192) /* 8K */
+				#else
+					#define MAX_RECVBUF_SZ (15360) /* 15k < 16k */
+				#endif
+				/* #define MAX_RECVBUF_SZ (8192+1024) */ /* 8K+1k */
+			#else
+				#define MAX_RECVBUF_SZ (4000) /* about 4K */
+			#endif
+		#endif
+	#endif /* !MAX_RECVBUF_SZ */
+
+#elif defined(CONFIG_PCI_HCI)
+	/* #ifndef CONFIG_MINIMAL_MEMORY_USAGE */
+	/*	#define MAX_RECVBUF_SZ (9100) */
+	/* #else */
+	#define MAX_RECVBUF_SZ (4000) /* about 4K
+	* #endif */
+
+
+#elif defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
+
+	#define MAX_RECVBUF_SZ (RX_DMA_SIZE_8703B - RX_DMA_RESERVED_SIZE_8703B)
+
+#endif
+
+/* Rx smooth factor */
+#define	Rx_Smooth_Factor (20)
+
+#ifdef CONFIG_SDIO_HCI
+	#ifndef CONFIG_SDIO_RX_COPY
+		#undef MAX_RECVBUF_SZ
+		#define MAX_RECVBUF_SZ	(RX_DMA_SIZE_8703B - RX_DMA_RESERVED_SIZE_8703B)
+	#endif /* !CONFIG_SDIO_RX_COPY */
+#endif /* CONFIG_SDIO_HCI */
+
+#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
+	s32 rtl8703bs_init_recv_priv(PADAPTER padapter);
+	void rtl8703bs_free_recv_priv(PADAPTER padapter);
+#endif
+
+#ifdef CONFIG_USB_HCI
+	int rtl8703bu_init_recv_priv(_adapter *padapter);
+	void rtl8703bu_free_recv_priv(_adapter *padapter);
+	void rtl8703bu_init_recvbuf(_adapter *padapter, struct recv_buf *precvbuf);
+#endif
+
+#ifdef CONFIG_PCI_HCI
+	s32 rtl8703be_init_recv_priv(PADAPTER padapter);
+	void rtl8703be_free_recv_priv(PADAPTER padapter);
+#endif
+
+void rtl8703b_query_rx_desc_status(union recv_frame *precvframe, u8 *pdesc);
+
+#endif /* __RTL8703B_RECV_H__ */
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/include/rtl8703b_rf.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/rtl8703b_rf.h
--- linux-5.6.3/3rdparty/rtl8821ce/include/rtl8703b_rf.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/rtl8703b_rf.h	2020-04-10 16:35:06.849661608 +0300
@@ -0,0 +1,25 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#ifndef __RTL8703B_RF_H__
+#define __RTL8703B_RF_H__
+
+int	PHY_RF6052_Config8703B(IN	PADAPTER		Adapter);
+
+VOID
+PHY_RF6052SetBandwidth8703B(
+	IN	PADAPTER				Adapter,
+	IN	enum channel_width		Bandwidth);
+
+#endif
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/include/rtl8703b_spec.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/rtl8703b_spec.h
--- linux-5.6.3/3rdparty/rtl8821ce/include/rtl8703b_spec.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/rtl8703b_spec.h	2020-04-10 16:35:06.849661608 +0300
@@ -0,0 +1,464 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#ifndef __RTL8703B_SPEC_H__
+#define __RTL8703B_SPEC_H__
+
+#include <drv_conf.h>
+
+
+#define HAL_NAV_UPPER_UNIT_8703B		128		/* micro-second */
+
+/* -----------------------------------------------------
+ *
+ *	0x0000h ~ 0x00FFh	System Configuration
+ *
+ * ----------------------------------------------------- */
+#define REG_SYS_ISO_CTRL_8703B			0x0000	/* 2 Byte */
+#define REG_SYS_FUNC_EN_8703B			0x0002	/* 2 Byte */
+#define REG_APS_FSMCO_8703B			0x0004	/* 4 Byte */
+#define REG_SYS_CLKR_8703B				0x0008	/* 2 Byte */
+#define REG_9346CR_8703B				0x000A	/* 2 Byte */
+#define REG_EE_VPD_8703B				0x000C	/* 2 Byte */
+#define REG_AFE_MISC_8703B				0x0010	/* 1 Byte */
+#define REG_SPS0_CTRL_8703B				0x0011	/* 7 Byte */
+#define REG_SPS_OCP_CFG_8703B			0x0018	/* 4 Byte */
+#define REG_RSV_CTRL_8703B				0x001C	/* 3 Byte */
+#define REG_RF_CTRL_8703B				0x001F	/* 1 Byte */
+#define REG_LPLDO_CTRL_8703B			0x0023	/* 1 Byte */
+#define REG_AFE_XTAL_CTRL_8703B		0x0024	/* 4 Byte */
+#define REG_AFE_PLL_CTRL_8703B			0x0028	/* 4 Byte */
+#define REG_MAC_PLL_CTRL_EXT_8703B		0x002c	/* 4 Byte */
+#define REG_EFUSE_CTRL_8703B			0x0030
+#define REG_EFUSE_TEST_8703B			0x0034
+#define REG_PWR_DATA_8703B				0x0038
+#define REG_CAL_TIMER_8703B				0x003C
+#define REG_ACLK_MON_8703B				0x003E
+#define REG_GPIO_MUXCFG_8703B			0x0040
+#define REG_GPIO_IO_SEL_8703B			0x0042
+#define REG_MAC_PINMUX_CFG_8703B		0x0043
+#define REG_GPIO_PIN_CTRL_8703B			0x0044
+#define REG_GPIO_INTM_8703B				0x0048
+#define REG_LEDCFG0_8703B				0x004C
+#define REG_LEDCFG1_8703B				0x004D
+#define REG_LEDCFG2_8703B				0x004E
+#define REG_LEDCFG3_8703B				0x004F
+#define REG_FSIMR_8703B					0x0050
+#define REG_FSISR_8703B					0x0054
+#define REG_HSIMR_8703B					0x0058
+#define REG_HSISR_8703B					0x005c
+#define REG_GPIO_EXT_CTRL				0x0060
+#define REG_PAD_CTRL1_8703B		0x0064
+#define REG_MULTI_FUNC_CTRL_8703B		0x0068
+#define REG_GPIO_STATUS_8703B			0x006C
+#define REG_SDIO_CTRL_8703B				0x0070
+#define REG_OPT_CTRL_8703B				0x0074
+#define REG_AFE_CTRL_4_8703B		0x0078
+#define REG_MCUFWDL_8703B				0x0080
+#define REG_HMEBOX_DBG_0_8703B	0x0088
+#define REG_HMEBOX_DBG_1_8703B	0x008A
+#define REG_HMEBOX_DBG_2_8703B	0x008C
+#define REG_HMEBOX_DBG_3_8703B	0x008E
+#define REG_HIMR0_8703B					0x00B0
+#define REG_HISR0_8703B					0x00B4
+#define REG_HIMR1_8703B					0x00B8
+#define REG_HISR1_8703B					0x00BC
+#define REG_PMC_DBG_CTRL2_8703B			0x00CC
+#define	REG_EFUSE_BURN_GNT_8703B		0x00CF
+#define REG_HPON_FSM_8703B				0x00EC
+#define REG_SYS_CFG_8703B				0x00F0
+#define REG_SYS_CFG1_8703B				0x00FC
+#define REG_ROM_VERSION					0x00FD
+
+/* -----------------------------------------------------
+ *
+ *	0x0100h ~ 0x01FFh	MACTOP General Configuration
+ *
+ * ----------------------------------------------------- */
+#define REG_C2HEVT_CMD_ID_8703B	0x01A0
+#define REG_C2HEVT_CMD_SEQ_88XX		0x01A1
+#define REG_C2hEVT_CMD_CONTENT_88XX	0x01A2
+#define REG_C2HEVT_CMD_LEN_8703B        0x01AE
+#define REG_C2HEVT_CMD_LEN_88XX		REG_C2HEVT_CMD_LEN_8703B
+#define REG_C2HEVT_CLEAR_8703B			0x01AF
+#define REG_MCUTST_1_8703B				0x01C0
+#define REG_WOWLAN_WAKE_REASON 0x01C7
+#define REG_FMETHR_8703B				0x01C8
+#define REG_HMETFR_8703B				0x01CC
+#define REG_HMEBOX_0_8703B				0x01D0
+#define REG_HMEBOX_1_8703B				0x01D4
+#define REG_HMEBOX_2_8703B				0x01D8
+#define REG_HMEBOX_3_8703B				0x01DC
+#define REG_LLT_INIT_8703B				0x01E0
+#define REG_HMEBOX_EXT0_8703B			0x01F0
+#define REG_HMEBOX_EXT1_8703B			0x01F4
+#define REG_HMEBOX_EXT2_8703B			0x01F8
+#define REG_HMEBOX_EXT3_8703B			0x01FC
+
+/* -----------------------------------------------------
+ *
+ *	0x0200h ~ 0x027Fh	TXDMA Configuration
+ *
+ * ----------------------------------------------------- */
+#define REG_RQPN_8703B					0x0200
+#define REG_FIFOPAGE_8703B				0x0204
+#define REG_DWBCN0_CTRL_8703B			REG_TDECTRL
+#define REG_TXDMA_OFFSET_CHK_8703B	0x020C
+#define REG_TXDMA_STATUS_8703B		0x0210
+#define REG_RQPN_NPQ_8703B			0x0214
+#define REG_DWBCN1_CTRL_8703B			0x0228
+
+
+/* -----------------------------------------------------
+ *
+ *	0x0280h ~ 0x02FFh	RXDMA Configuration
+ *
+ * ----------------------------------------------------- */
+#define REG_RXDMA_AGG_PG_TH_8703B		0x0280
+#define REG_FW_UPD_RDPTR_8703B		0x0284 /* FW shall update this register before FW write RXPKT_RELEASE_POLL to 1 */
+#define REG_RXDMA_CONTROL_8703B		0x0286 /* Control the RX DMA. */
+#define REG_RXPKT_NUM_8703B			0x0287 /* The number of packets in RXPKTBUF.	 */
+#define REG_RXDMA_STATUS_8703B			0x0288
+#define REG_RXDMA_MODE_CTRL_8703B		0x0290
+#define REG_EARLY_MODE_CONTROL_8703B	0x02BC
+#define REG_RSVD5_8703B					0x02F0
+#define REG_RSVD6_8703B					0x02F4
+
+/* -----------------------------------------------------
+ *
+ *	0x0300h ~ 0x03FFh	PCIe
+ *
+ * ----------------------------------------------------- */
+#define	REG_PCIE_CTRL_REG_8703B		0x0300
+#define	REG_INT_MIG_8703B				0x0304	/* Interrupt Migration */
+#define	REG_BCNQ_DESA_8703B			0x0308	/* TX Beacon Descriptor Address */
+#define	REG_HQ_DESA_8703B				0x0310	/* TX High Queue Descriptor Address */
+#define	REG_MGQ_DESA_8703B			0x0318	/* TX Manage Queue Descriptor Address */
+#define	REG_VOQ_DESA_8703B			0x0320	/* TX VO Queue Descriptor Address */
+#define	REG_VIQ_DESA_8703B				0x0328	/* TX VI Queue Descriptor Address */
+#define	REG_BEQ_DESA_8703B			0x0330	/* TX BE Queue Descriptor Address */
+#define	REG_BKQ_DESA_8703B			0x0338	/* TX BK Queue Descriptor Address */
+#define	REG_RX_DESA_8703B				0x0340	/* RX Queue	Descriptor Address */
+#define	REG_DBI_WDATA_8703B			0x0348	/* DBI Write Data */
+#define	REG_DBI_RDATA_8703B			0x034C	/* DBI Read Data */
+#define	REG_DBI_ADDR_8703B				0x0350	/* DBI Address */
+#define	REG_DBI_FLAG_8703B				0x0352	/* DBI Read/Write Flag */
+#define	REG_MDIO_WDATA_8703B		0x0354	/* MDIO for Write PCIE PHY */
+#define	REG_MDIO_RDATA_8703B			0x0356	/* MDIO for Reads PCIE PHY */
+#define	REG_MDIO_CTL_8703B			0x0358	/* MDIO for Control */
+#define	REG_DBG_SEL_8703B				0x0360	/* Debug Selection Register */
+#define	REG_PCIE_HRPWM_8703B			0x0361	/* PCIe RPWM */
+#define	REG_PCIE_HCPWM_8703B			0x0363	/* PCIe CPWM */
+#define	REG_PCIE_MULTIFET_CTRL_8703B	0x036A	/* PCIE Multi-Fethc Control */
+
+/* -----------------------------------------------------
+ *
+ *	0x0400h ~ 0x047Fh	Protocol Configuration
+ *
+ * ----------------------------------------------------- */
+#define REG_VOQ_INFORMATION_8703B		0x0400
+#define REG_VIQ_INFORMATION_8703B		0x0404
+#define REG_BEQ_INFORMATION_8703B		0x0408
+#define REG_BKQ_INFORMATION_8703B		0x040C
+#define REG_MGQ_INFORMATION_8703B		0x0410
+#define REG_HGQ_INFORMATION_8703B		0x0414
+#define REG_BCNQ_INFORMATION_8703B	0x0418
+#define REG_TXPKT_EMPTY_8703B			0x041A
+
+#define REG_FWHW_TXQ_CTRL_8703B		0x0420
+#define REG_HWSEQ_CTRL_8703B			0x0423
+#define REG_TXPKTBUF_BCNQ_BDNY_8703B	0x0424
+#define REG_TXPKTBUF_MGQ_BDNY_8703B	0x0425
+#define REG_LIFECTRL_CTRL_8703B			0x0426
+#define REG_MULTI_BCNQ_OFFSET_8703B	0x0427
+#define REG_SPEC_SIFS_8703B				0x0428
+#define REG_RL_8703B						0x042A
+#define REG_TXBF_CTRL_8703B				0x042C
+#define REG_DARFRC_8703B				0x0430
+#define REG_RARFRC_8703B				0x0438
+#define REG_RRSR_8703B					0x0440
+#define REG_ARFR0_8703B					0x0444
+#define REG_ARFR1_8703B					0x044C
+#define REG_CCK_CHECK_8703B				0x0454
+#define REG_AMPDU_MAX_TIME_8703B		0x0456
+#define REG_TXPKTBUF_BCNQ_BDNY1_8703B	0x0457
+
+#define REG_AMPDU_MAX_LENGTH_8703B	0x0458
+#define REG_TXPKTBUF_WMAC_LBK_BF_HD_8703B	0x045D
+#define REG_NDPA_OPT_CTRL_8703B		0x045F
+#define REG_FAST_EDCA_CTRL_8703B		0x0460
+#define REG_RD_RESP_PKT_TH_8703B		0x0463
+#define REG_DATA_SC_8703B				0x0483
+#ifdef CONFIG_WOWLAN
+	#define REG_TXPKTBUF_IV_LOW             0x0484
+	#define REG_TXPKTBUF_IV_HIGH            0x0488
+#endif
+#define REG_TXRPT_START_OFFSET		0x04AC
+#define REG_POWER_STAGE1_8703B		0x04B4
+#define REG_POWER_STAGE2_8703B		0x04B8
+#define REG_AMPDU_BURST_MODE_8703B	0x04BC
+#define REG_PKT_VO_VI_LIFE_TIME_8703B	0x04C0
+#define REG_PKT_BE_BK_LIFE_TIME_8703B	0x04C2
+#define REG_STBC_SETTING_8703B			0x04C4
+#define REG_HT_SINGLE_AMPDU_8703B		0x04C7
+#define REG_PROT_MODE_CTRL_8703B		0x04C8
+#define REG_MAX_AGGR_NUM_8703B		0x04CA
+#define REG_RTS_MAX_AGGR_NUM_8703B	0x04CB
+#define REG_BAR_MODE_CTRL_8703B		0x04CC
+#define REG_RA_TRY_RATE_AGG_LMT_8703B	0x04CF
+#define REG_MACID_PKT_DROP0_8703B		0x04D0
+#define REG_MACID_PKT_SLEEP_8703B		0x04D4
+
+/* -----------------------------------------------------
+ *
+ *	0x0500h ~ 0x05FFh	EDCA Configuration
+ *
+ * ----------------------------------------------------- */
+#define REG_EDCA_VO_PARAM_8703B		0x0500
+#define REG_EDCA_VI_PARAM_8703B		0x0504
+#define REG_EDCA_BE_PARAM_8703B		0x0508
+#define REG_EDCA_BK_PARAM_8703B		0x050C
+#define REG_BCNTCFG_8703B				0x0510
+#define REG_PIFS_8703B					0x0512
+#define REG_RDG_PIFS_8703B				0x0513
+#define REG_SIFS_CTX_8703B				0x0514
+#define REG_SIFS_TRX_8703B				0x0516
+#define REG_AGGR_BREAK_TIME_8703B		0x051A
+#define REG_SLOT_8703B					0x051B
+#define REG_TX_PTCL_CTRL_8703B			0x0520
+#define REG_TXPAUSE_8703B				0x0522
+#define REG_DIS_TXREQ_CLR_8703B		0x0523
+#define REG_RD_CTRL_8703B				0x0524
+/*
+ * Format for offset 540h-542h:
+ *	[3:0]:   TBTT prohibit setup in unit of 32us. The time for HW getting beacon content before TBTT.
+ *	[7:4]:   Reserved.
+ *	[19:8]:  TBTT prohibit hold in unit of 32us. The time for HW holding to send the beacon packet.
+ *	[23:20]: Reserved
+ * Description:
+ *	              |
+ * |<--Setup--|--Hold------------>|
+ *	--------------|----------------------
+ * |
+ * TBTT
+ * Note: We cannot update beacon content to HW or send any AC packets during the time between Setup and Hold.
+ * Described by Designer Tim and Bruce, 2011-01-14.
+ *   */
+#define REG_TBTT_PROHIBIT_8703B			0x0540
+#define REG_RD_NAV_NXT_8703B			0x0544
+#define REG_NAV_PROT_LEN_8703B			0x0546
+#define REG_BCN_CTRL_8703B				0x0550
+#define REG_BCN_CTRL_1_8703B			0x0551
+#define REG_MBID_NUM_8703B				0x0552
+#define REG_DUAL_TSF_RST_8703B			0x0553
+#define REG_BCN_INTERVAL_8703B			0x0554
+#define REG_DRVERLYINT_8703B			0x0558
+#define REG_BCNDMATIM_8703B			0x0559
+#define REG_ATIMWND_8703B				0x055A
+#define REG_USTIME_TSF_8703B			0x055C
+#define REG_BCN_MAX_ERR_8703B			0x055D
+#define REG_RXTSF_OFFSET_CCK_8703B		0x055E
+#define REG_RXTSF_OFFSET_OFDM_8703B	0x055F
+#define REG_TSFTR_8703B					0x0560
+#define REG_CTWND_8703B					0x0572
+#define REG_SECONDARY_CCA_CTRL_8703B	0x0577
+#define REG_PSTIMER_8703B				0x0580
+#define REG_TIMER0_8703B				0x0584
+#define REG_TIMER1_8703B				0x0588
+#define REG_ACMHWCTRL_8703B			0x05C0
+#define REG_SCH_TXCMD_8703B			0x05F8
+
+/* -----------------------------------------------------
+ *
+ *	0x0600h ~ 0x07FFh	WMAC Configuration
+ *
+ * ----------------------------------------------------- */
+#define REG_MAC_CR_8703B				0x0600
+#define REG_TCR_8703B					0x0604
+#define REG_RCR_8703B					0x0608
+#define REG_RX_PKT_LIMIT_8703B			0x060C
+#define REG_RX_DLK_TIME_8703B			0x060D
+#define REG_RX_DRVINFO_SZ_8703B		0x060F
+
+#define REG_MACID_8703B					0x0610
+#define REG_BSSID_8703B					0x0618
+#define REG_MAR_8703B					0x0620
+#define REG_MBIDCAMCFG_8703B			0x0628
+#define REG_WOWLAN_GTK_DBG1	0x630
+#define REG_WOWLAN_GTK_DBG2	0x634
+
+#define REG_USTIME_EDCA_8703B			0x0638
+#define REG_MAC_SPEC_SIFS_8703B		0x063A
+#define REG_RESP_SIFP_CCK_8703B			0x063C
+#define REG_RESP_SIFS_OFDM_8703B		0x063E
+#define REG_ACKTO_8703B					0x0640
+#define REG_CTS2TO_8703B				0x0641
+#define REG_EIFS_8703B					0x0642
+
+#define REG_NAV_UPPER_8703B			0x0652	/* unit of 128 */
+#define REG_TRXPTCL_CTL_8703B			0x0668
+
+/* Security */
+#define REG_CAMCMD_8703B				0x0670
+#define REG_CAMWRITE_8703B				0x0674
+#define REG_CAMREAD_8703B				0x0678
+#define REG_CAMDBG_8703B				0x067C
+#define REG_SECCFG_8703B				0x0680
+
+/* Power */
+#define REG_WOW_CTRL_8703B				0x0690
+#define REG_PS_RX_INFO_8703B			0x0692
+#define REG_UAPSD_TID_8703B				0x0693
+#define REG_WKFMCAM_CMD_8703B			0x0698
+#define REG_WKFMCAM_NUM_8703B			0x0698
+#define REG_WKFMCAM_RWD_8703B			0x069C
+#define REG_RXFLTMAP0_8703B				0x06A0
+#define REG_RXFLTMAP1_8703B				0x06A2
+#define REG_RXFLTMAP2_8703B				0x06A4
+#define REG_BCN_PSR_RPT_8703B			0x06A8
+#define REG_BT_COEX_TABLE_8703B		0x06C0
+#define REG_BFMER0_INFO_8703B			0x06E4
+#define REG_BFMER1_INFO_8703B			0x06EC
+#define REG_CSI_RPT_PARAM_BW20_8703B	0x06F4
+#define REG_CSI_RPT_PARAM_BW40_8703B	0x06F8
+#define REG_CSI_RPT_PARAM_BW80_8703B	0x06FC
+
+/* Hardware Port 2 */
+#define REG_MACID1_8703B				0x0700
+#define REG_BSSID1_8703B				0x0708
+#define REG_BFMEE_SEL_8703B				0x0714
+#define REG_SND_PTCL_CTRL_8703B		0x0718
+
+/* LTE_COEX */
+#define REG_LTECOEX_CTRL			0x07C0
+#define REG_LTECOEX_WRITE_DATA		0x07C4
+#define REG_LTECOEX_READ_DATA		0x07C8
+#define REG_LTECOEX_PATH_CONTROL	0x70
+
+/* ************************************************************
+ * SDIO Bus Specification
+ * ************************************************************ */
+
+/* -----------------------------------------------------
+ * SDIO CMD Address Mapping
+ * ----------------------------------------------------- */
+
+/* -----------------------------------------------------
+ * I/O bus domain (Host)
+ * ----------------------------------------------------- */
+
+/* -----------------------------------------------------
+ * SDIO register
+ * ----------------------------------------------------- */
+#define SDIO_REG_HCPWM1_8703B	0x025 /* HCI Current Power Mode 1 */
+
+
+/* ****************************************************************************
+ *	8703 Regsiter Bit and Content definition
+ * **************************************************************************** */
+
+#define BIT_USB_RXDMA_AGG_EN	BIT(31)
+#define RXDMA_AGG_MODE_EN		BIT(1)
+
+#ifdef CONFIG_WOWLAN
+	#define RXPKT_RELEASE_POLL		BIT(16)
+	#define RXDMA_IDLE				BIT(17)
+	#define RW_RELEASE_EN			BIT(18)
+#endif
+
+/* 2 HSISR
+ * interrupt mask which needs to clear */
+#define MASK_HSISR_CLEAR		(HSISR_GPIO12_0_INT |\
+		HSISR_SPS_OCP_INT |\
+		HSISR_RON_INT |\
+		HSISR_PDNINT |\
+		HSISR_GPIO9_INT)
+
+
+/* ----------------------------------------------------------------------------
+ * 8703B REG_CCK_CHECK						(offset 0x454)
+ * ---------------------------------------------------------------------------- */
+#define BIT_BCN_PORT_SEL		BIT(5)
+
+#ifdef CONFIG_RF_POWER_TRIM
+
+	#ifdef CONFIG_RTL8703B
+		#define EEPROM_RF_GAIN_OFFSET			0xC1
+	#endif
+
+	#define EEPROM_RF_GAIN_VAL				0x1F6
+#endif /*CONFIG_RF_POWER_TRIM*/
+
+
+/* ----------------------------------------------------------------------------
+ * 8195 IMR/ISR bits						(offset 0xB0,  8bits)
+ * ---------------------------------------------------------------------------- */
+#define	IMR_DISABLED_8703B					0
+/* IMR DW0(0x00B0-00B3) Bit 0-31 */
+#define	IMR_TIMER2_8703B					BIT(31)		/* Timeout interrupt 2 */
+#define	IMR_TIMER1_8703B					BIT(30)		/* Timeout interrupt 1	 */
+#define	IMR_PSTIMEOUT_8703B				BIT(29)		/* Power Save Time Out Interrupt */
+#define	IMR_GTINT4_8703B					BIT(28)		/* When GTIMER4 expires, this bit is set to 1	 */
+#define	IMR_GTINT3_8703B					BIT(27)		/* When GTIMER3 expires, this bit is set to 1	 */
+#define	IMR_TXBCN0ERR_8703B				BIT(26)		/* Transmit Beacon0 Error			 */
+#define	IMR_TXBCN0OK_8703B				BIT(25)		/* Transmit Beacon0 OK			 */
+#define	IMR_TSF_BIT32_TOGGLE_8703B		BIT(24)		/* TSF Timer BIT32 toggle indication interrupt			 */
+#define	IMR_BCNDMAINT0_8703B				BIT(20)		/* Beacon DMA Interrupt 0			 */
+#define	IMR_BCNDERR0_8703B				BIT(16)		/* Beacon Queue DMA OK0			 */
+#define	IMR_HSISR_IND_ON_INT_8703B		BIT(15)		/* HSISR Indicator (HSIMR & HSISR is true, this bit is set to 1) */
+#define	IMR_BCNDMAINT_E_8703B			BIT(14)		/* Beacon DMA Interrupt Extension for Win7			 */
+#define	IMR_ATIMEND_8703B				BIT(12)		/* CTWidnow End or ATIM Window End */
+#define	IMR_C2HCMD_8703B					BIT(10)		/* CPU to Host Command INT Status, Write 1 clear	 */
+#define	IMR_CPWM2_8703B					BIT(9)			/* CPU power Mode exchange INT Status, Write 1 clear	 */
+#define	IMR_CPWM_8703B					BIT(8)			/* CPU power Mode exchange INT Status, Write 1 clear	 */
+#define	IMR_HIGHDOK_8703B				BIT(7)			/* High Queue DMA OK	 */
+#define	IMR_MGNTDOK_8703B				BIT(6)			/* Management Queue DMA OK	 */
+#define	IMR_BKDOK_8703B					BIT(5)			/* AC_BK DMA OK		 */
+#define	IMR_BEDOK_8703B					BIT(4)			/* AC_BE DMA OK	 */
+#define	IMR_VIDOK_8703B					BIT(3)			/* AC_VI DMA OK		 */
+#define	IMR_VODOK_8703B					BIT(2)			/* AC_VO DMA OK	 */
+#define	IMR_RDU_8703B					BIT(1)			/* Rx Descriptor Unavailable	 */
+#define	IMR_ROK_8703B					BIT(0)			/* Receive DMA OK */
+
+/* IMR DW1(0x00B4-00B7) Bit 0-31 */
+#define	IMR_BCNDMAINT7_8703B				BIT(27)		/* Beacon DMA Interrupt 7 */
+#define	IMR_BCNDMAINT6_8703B				BIT(26)		/* Beacon DMA Interrupt 6 */
+#define	IMR_BCNDMAINT5_8703B				BIT(25)		/* Beacon DMA Interrupt 5 */
+#define	IMR_BCNDMAINT4_8703B				BIT(24)		/* Beacon DMA Interrupt 4 */
+#define	IMR_BCNDMAINT3_8703B				BIT(23)		/* Beacon DMA Interrupt 3 */
+#define	IMR_BCNDMAINT2_8703B				BIT(22)		/* Beacon DMA Interrupt 2 */
+#define	IMR_BCNDMAINT1_8703B				BIT(21)		/* Beacon DMA Interrupt 1 */
+#define	IMR_BCNDOK7_8703B					BIT(20)		/* Beacon Queue DMA OK Interrupt 7 */
+#define	IMR_BCNDOK6_8703B					BIT(19)		/* Beacon Queue DMA OK Interrupt 6 */
+#define	IMR_BCNDOK5_8703B					BIT(18)		/* Beacon Queue DMA OK Interrupt 5 */
+#define	IMR_BCNDOK4_8703B					BIT(17)		/* Beacon Queue DMA OK Interrupt 4 */
+#define	IMR_BCNDOK3_8703B					BIT(16)		/* Beacon Queue DMA OK Interrupt 3 */
+#define	IMR_BCNDOK2_8703B					BIT(15)		/* Beacon Queue DMA OK Interrupt 2 */
+#define	IMR_BCNDOK1_8703B					BIT(14)		/* Beacon Queue DMA OK Interrupt 1 */
+#define	IMR_ATIMEND_E_8703B				BIT(13)		/* ATIM Window End Extension for Win7 */
+#define	IMR_TXERR_8703B					BIT(11)		/* Tx Error Flag Interrupt Status, write 1 clear. */
+#define	IMR_RXERR_8703B					BIT(10)		/* Rx Error Flag INT Status, Write 1 clear */
+#define	IMR_TXFOVW_8703B					BIT(9)			/* Transmit FIFO Overflow */
+#define	IMR_RXFOVW_8703B					BIT(8)			/* Receive FIFO Overflow */
+
+#ifdef CONFIG_PCI_HCI
+	/* #define IMR_RX_MASK		(IMR_ROK_8703B|IMR_RDU_8703B|IMR_RXFOVW_8703B) */
+	#define IMR_TX_MASK			(IMR_VODOK_8703B | IMR_VIDOK_8703B | IMR_BEDOK_8703B | IMR_BKDOK_8703B | IMR_MGNTDOK_8703B | IMR_HIGHDOK_8703B)
+
+	#define RT_BCN_INT_MASKS	(IMR_BCNDMAINT0_8703B | IMR_TXBCN0OK_8703B | IMR_TXBCN0ERR_8703B | IMR_BCNDERR0_8703B)
+
+	#define RT_AC_INT_MASKS	(IMR_VIDOK_8703B | IMR_VODOK_8703B | IMR_BEDOK_8703B | IMR_BKDOK_8703B)
+#endif
+
+#endif /* __RTL8703B_SPEC_H__ */
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/include/rtl8703b_sreset.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/rtl8703b_sreset.h
--- linux-5.6.3/3rdparty/rtl8821ce/include/rtl8703b_sreset.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/rtl8703b_sreset.h	2020-04-10 16:35:06.849661608 +0300
@@ -0,0 +1,24 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#ifndef _RTL8703B_SRESET_H_
+#define _RTL8703B_SRESET_H_
+
+#include <rtw_sreset.h>
+
+#ifdef DBG_CONFIG_ERROR_DETECT
+	extern void rtl8703b_sreset_xmit_status_check(_adapter *padapter);
+	extern void rtl8703b_sreset_linked_status_check(_adapter *padapter);
+#endif
+#endif
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/include/rtl8703b_xmit.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/rtl8703b_xmit.h
--- linux-5.6.3/3rdparty/rtl8821ce/include/rtl8703b_xmit.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/rtl8703b_xmit.h	2020-04-10 16:35:06.849661608 +0300
@@ -0,0 +1,335 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#ifndef __RTL8703B_XMIT_H__
+#define __RTL8703B_XMIT_H__
+
+
+#define MAX_TID (15)
+
+
+#ifndef __INC_HAL8703BDESC_H
+	#define __INC_HAL8703BDESC_H
+
+	#define RX_STATUS_DESC_SIZE_8703B		24
+	#define RX_DRV_INFO_SIZE_UNIT_8703B 8
+
+
+	/* DWORD 0 */
+	#define SET_RX_STATUS_DESC_PKT_LEN_8703B(__pRxStatusDesc, __Value)		SET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 0, 14, __Value)
+	#define SET_RX_STATUS_DESC_EOR_8703B(__pRxStatusDesc, __Value)		SET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 30, 1, __Value)
+	#define SET_RX_STATUS_DESC_OWN_8703B(__pRxStatusDesc, __Value)		SET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 31, 1, __Value)
+
+	#define GET_RX_STATUS_DESC_PKT_LEN_8703B(__pRxStatusDesc)			LE_BITS_TO_4BYTE(__pRxStatusDesc, 0, 14)
+	#define GET_RX_STATUS_DESC_CRC32_8703B(__pRxStatusDesc)		LE_BITS_TO_4BYTE(__pRxStatusDesc, 14, 1)
+	#define GET_RX_STATUS_DESC_ICV_8703B(__pRxStatusDesc)				LE_BITS_TO_4BYTE(__pRxStatusDesc, 15, 1)
+	#define GET_RX_STATUS_DESC_DRVINFO_SIZE_8703B(__pRxStatusDesc)		LE_BITS_TO_4BYTE(__pRxStatusDesc, 16, 4)
+	#define GET_RX_STATUS_DESC_SECURITY_8703B(__pRxStatusDesc)			LE_BITS_TO_4BYTE(__pRxStatusDesc, 20, 3)
+	#define GET_RX_STATUS_DESC_QOS_8703B(__pRxStatusDesc)				LE_BITS_TO_4BYTE(__pRxStatusDesc, 23, 1)
+	#define GET_RX_STATUS_DESC_SHIFT_8703B(__pRxStatusDesc)		LE_BITS_TO_4BYTE(__pRxStatusDesc, 24, 2)
+	#define GET_RX_STATUS_DESC_PHY_STATUS_8703B(__pRxStatusDesc)			LE_BITS_TO_4BYTE(__pRxStatusDesc, 26, 1)
+	#define GET_RX_STATUS_DESC_SWDEC_8703B(__pRxStatusDesc)		LE_BITS_TO_4BYTE(__pRxStatusDesc, 27, 1)
+	#define GET_RX_STATUS_DESC_LAST_SEG_8703B(__pRxStatusDesc)			LE_BITS_TO_4BYTE(__pRxStatusDesc, 28, 1)
+	#define GET_RX_STATUS_DESC_FIRST_SEG_8703B(__pRxStatusDesc)		LE_BITS_TO_4BYTE(__pRxStatusDesc, 29, 1)
+	#define GET_RX_STATUS_DESC_EOR_8703B(__pRxStatusDesc)				LE_BITS_TO_4BYTE(__pRxStatusDesc, 30, 1)
+	#define GET_RX_STATUS_DESC_OWN_8703B(__pRxStatusDesc)				LE_BITS_TO_4BYTE(__pRxStatusDesc, 31, 1)
+
+	/* DWORD 1 */
+	#define GET_RX_STATUS_DESC_MACID_8703B(__pRxDesc)					LE_BITS_TO_4BYTE(__pRxDesc+4, 0, 7)
+	#define GET_RX_STATUS_DESC_TID_8703B(__pRxDesc)					LE_BITS_TO_4BYTE(__pRxDesc+4, 8, 4)
+	#define GET_RX_STATUS_DESC_AMSDU_8703B(__pRxDesc)					LE_BITS_TO_4BYTE(__pRxDesc+4, 13, 1)
+	#define GET_RX_STATUS_DESC_RXID_MATCH_8703B(__pRxDesc)		LE_BITS_TO_4BYTE(__pRxDesc+4, 14, 1)
+	#define GET_RX_STATUS_DESC_PAGGR_8703B(__pRxDesc)				LE_BITS_TO_4BYTE(__pRxDesc+4, 15, 1)
+	#define GET_RX_STATUS_DESC_A1_FIT_8703B(__pRxDesc)				LE_BITS_TO_4BYTE(__pRxDesc+4, 16, 4)
+	#define GET_RX_STATUS_DESC_CHKERR_8703B(__pRxDesc)				LE_BITS_TO_4BYTE(__pRxDesc+4, 20, 1)
+	#define GET_RX_STATUS_DESC_IPVER_8703B(__pRxDesc)			LE_BITS_TO_4BYTE(__pRxDesc+4, 21, 1)
+	#define GET_RX_STATUS_DESC_IS_TCPUDP__8703B(__pRxDesc)		LE_BITS_TO_4BYTE(__pRxDesc+4, 22, 1)
+	#define GET_RX_STATUS_DESC_CHK_VLD_8703B(__pRxDesc)	LE_BITS_TO_4BYTE(__pRxDesc+4, 23, 1)
+	#define GET_RX_STATUS_DESC_PAM_8703B(__pRxDesc)			LE_BITS_TO_4BYTE(__pRxDesc+4, 24, 1)
+	#define GET_RX_STATUS_DESC_PWR_8703B(__pRxDesc)			LE_BITS_TO_4BYTE(__pRxDesc+4, 25, 1)
+	#define GET_RX_STATUS_DESC_MORE_DATA_8703B(__pRxDesc)			LE_BITS_TO_4BYTE(__pRxDesc+4, 26, 1)
+	#define GET_RX_STATUS_DESC_MORE_FRAG_8703B(__pRxDesc)			LE_BITS_TO_4BYTE(__pRxDesc+4, 27, 1)
+	#define GET_RX_STATUS_DESC_TYPE_8703B(__pRxDesc)			LE_BITS_TO_4BYTE(__pRxDesc+4, 28, 2)
+	#define GET_RX_STATUS_DESC_MC_8703B(__pRxDesc)				LE_BITS_TO_4BYTE(__pRxDesc+4, 30, 1)
+	#define GET_RX_STATUS_DESC_BC_8703B(__pRxDesc)				LE_BITS_TO_4BYTE(__pRxDesc+4, 31, 1)
+
+	/* DWORD 2 */
+	#define GET_RX_STATUS_DESC_SEQ_8703B(__pRxStatusDesc)					LE_BITS_TO_4BYTE(__pRxStatusDesc+8, 0, 12)
+	#define GET_RX_STATUS_DESC_FRAG_8703B(__pRxStatusDesc)				LE_BITS_TO_4BYTE(__pRxStatusDesc+8, 12, 4)
+	#define GET_RX_STATUS_DESC_RX_IS_QOS_8703B(__pRxStatusDesc)		LE_BITS_TO_4BYTE(__pRxStatusDesc+8, 16, 1)
+	#define GET_RX_STATUS_DESC_WLANHD_IV_LEN_8703B(__pRxStatusDesc)	LE_BITS_TO_4BYTE(__pRxStatusDesc+8, 18, 6)
+	#define GET_RX_STATUS_DESC_RPT_SEL_8703B(__pRxStatusDesc)			LE_BITS_TO_4BYTE(__pRxStatusDesc+8, 28, 1)
+
+	/* DWORD 3 */
+	#define GET_RX_STATUS_DESC_RX_RATE_8703B(__pRxStatusDesc)				LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 0, 7)
+	#define GET_RX_STATUS_DESC_HTC_8703B(__pRxStatusDesc)					LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 10, 1)
+	#define GET_RX_STATUS_DESC_EOSP_8703B(__pRxStatusDesc)					LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 11, 1)
+	#define GET_RX_STATUS_DESC_BSSID_FIT_8703B(__pRxStatusDesc)		LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 12, 2)
+	#ifdef CONFIG_USB_RX_AGGREGATION
+		#define GET_RX_STATUS_DESC_USB_AGG_PKTNUM_8703B(__pRxStatusDesc)	LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 16, 8)
+	#endif
+	#define GET_RX_STATUS_DESC_PATTERN_MATCH_8703B(__pRxDesc)			LE_BITS_TO_4BYTE(__pRxDesc+12, 29, 1)
+	#define GET_RX_STATUS_DESC_UNICAST_MATCH_8703B(__pRxDesc)			LE_BITS_TO_4BYTE(__pRxDesc+12, 30, 1)
+	#define GET_RX_STATUS_DESC_MAGIC_MATCH_8703B(__pRxDesc)		LE_BITS_TO_4BYTE(__pRxDesc+12, 31, 1)
+
+	/* DWORD 6 */
+	#define GET_RX_STATUS_DESC_SPLCP_8703B(__pRxDesc)			LE_BITS_TO_4BYTE(__pRxDesc+16, 0, 1)
+	#define GET_RX_STATUS_DESC_LDPC_8703B(__pRxDesc)			LE_BITS_TO_4BYTE(__pRxDesc+16, 1, 1)
+	#define GET_RX_STATUS_DESC_STBC_8703B(__pRxDesc)			LE_BITS_TO_4BYTE(__pRxDesc+16, 2, 1)
+	#define GET_RX_STATUS_DESC_BW_8703B(__pRxDesc)			LE_BITS_TO_4BYTE(__pRxDesc+16, 4, 2)
+
+	/* DWORD 5 */
+	#define GET_RX_STATUS_DESC_TSFL_8703B(__pRxStatusDesc)				LE_BITS_TO_4BYTE(__pRxStatusDesc+20, 0, 32)
+
+	#define GET_RX_STATUS_DESC_BUFF_ADDR_8703B(__pRxDesc)		LE_BITS_TO_4BYTE(__pRxDesc+24, 0, 32)
+	#define GET_RX_STATUS_DESC_BUFF_ADDR64_8703B(__pRxDesc)		LE_BITS_TO_4BYTE(__pRxDesc+28, 0, 32)
+
+	#define SET_RX_STATUS_DESC_BUFF_ADDR_8703B(__pRxDesc, __Value)	SET_BITS_TO_LE_4BYTE(__pRxDesc+24, 0, 32, __Value)
+
+
+	/* Dword 0 */
+	#define GET_TX_DESC_OWN_8703B(__pTxDesc)				LE_BITS_TO_4BYTE(__pTxDesc, 31, 1)
+
+	#define SET_TX_DESC_PKT_SIZE_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 0, 16, __Value)
+	#define SET_TX_DESC_OFFSET_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 16, 8, __Value)
+	#define SET_TX_DESC_BMC_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 24, 1, __Value)
+	#define SET_TX_DESC_HTC_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 25, 1, __Value)
+	#define SET_TX_DESC_LAST_SEG_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 26, 1, __Value)
+	#define SET_TX_DESC_FIRST_SEG_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 27, 1, __Value)
+	#define SET_TX_DESC_LINIP_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 28, 1, __Value)
+	#define SET_TX_DESC_NO_ACM_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 29, 1, __Value)
+	#define SET_TX_DESC_GF_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 30, 1, __Value)
+	#define SET_TX_DESC_OWN_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 31, 1, __Value)
+
+	/* Dword 1 */
+	#define SET_TX_DESC_MACID_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 0, 7, __Value)
+	#define SET_TX_DESC_QUEUE_SEL_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 8, 5, __Value)
+	#define SET_TX_DESC_RDG_NAV_EXT_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 13, 1, __Value)
+	#define SET_TX_DESC_LSIG_TXOP_EN_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 14, 1, __Value)
+	#define SET_TX_DESC_PIFS_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 15, 1, __Value)
+	#define SET_TX_DESC_RATE_ID_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 16, 5, __Value)
+	#define SET_TX_DESC_EN_DESC_ID_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 21, 1, __Value)
+	#define SET_TX_DESC_SEC_TYPE_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 22, 2, __Value)
+	#define SET_TX_DESC_PKT_OFFSET_8703B(__pTxDesc, __Value)		SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 24, 5, __Value)
+
+
+	/* Dword 2 */
+	#define SET_TX_DESC_PAID_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 0,  9, __Value)
+	#define SET_TX_DESC_CCA_RTS_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 10, 2, __Value)
+	#define SET_TX_DESC_AGG_ENABLE_8703B(__pTxDesc, __Value)		SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 12, 1, __Value)
+	#define SET_TX_DESC_RDG_ENABLE_8703B(__pTxDesc, __Value)		SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 13, 1, __Value)
+	#define SET_TX_DESC_AGG_BREAK_8703B(__pTxDesc, __Value)				SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 16, 1, __Value)
+	#define SET_TX_DESC_MORE_FRAG_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 17, 1, __Value)
+	#define SET_TX_DESC_RAW_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 18, 1, __Value)
+	#define SET_TX_DESC_SPE_RPT_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 19, 1, __Value)
+	#define SET_TX_DESC_AMPDU_DENSITY_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 20, 3, __Value)
+	#define SET_TX_DESC_BT_INT_8703B(__pTxDesc, __Value)			SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 23, 1, __Value)
+	#define SET_TX_DESC_GID_8703B(__pTxDesc, __Value)			SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 24, 6, __Value)
+
+
+	/* Dword 3 */
+	#define SET_TX_DESC_WHEADER_LEN_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 0, 4, __Value)
+	#define SET_TX_DESC_CHK_EN_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 4, 1, __Value)
+	#define SET_TX_DESC_EARLY_MODE_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 5, 1, __Value)
+	#define SET_TX_DESC_HWSEQ_SEL_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 6, 2, __Value)
+	#define SET_TX_DESC_USE_RATE_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 8, 1, __Value)
+	#define SET_TX_DESC_DISABLE_RTS_FB_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 9, 1, __Value)
+	#define SET_TX_DESC_DISABLE_FB_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 10, 1, __Value)
+	#define SET_TX_DESC_CTS2SELF_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 11, 1, __Value)
+	#define SET_TX_DESC_RTS_ENABLE_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 12, 1, __Value)
+	#define SET_TX_DESC_HW_RTS_ENABLE_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 13, 1, __Value)
+	#define SET_TX_DESC_NAV_USE_HDR_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 15, 1, __Value)
+	#define SET_TX_DESC_USE_MAX_LEN_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 16, 1, __Value)
+	#define SET_TX_DESC_MAX_AGG_NUM_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 17, 5, __Value)
+	#define SET_TX_DESC_NDPA_8703B(__pTxDesc, __Value)		SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 22, 2, __Value)
+	#define SET_TX_DESC_AMPDU_MAX_TIME_8703B(__pTxDesc, __Value)		SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 24, 8, __Value)
+
+	/* Dword 4 */
+	#define SET_TX_DESC_TX_RATE_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 0, 7, __Value)
+	#define SET_TX_DESC_DATA_RATE_FB_LIMIT_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 8, 5, __Value)
+	#define SET_TX_DESC_RTS_RATE_FB_LIMIT_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 13, 4, __Value)
+	#define SET_TX_DESC_RETRY_LIMIT_ENABLE_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 17, 1, __Value)
+	#define SET_TX_DESC_DATA_RETRY_LIMIT_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 18, 6, __Value)
+	#define SET_TX_DESC_RTS_RATE_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 24, 5, __Value)
+
+
+	/* Dword 5 */
+	#define SET_TX_DESC_DATA_SC_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 0, 4, __Value)
+	#define SET_TX_DESC_DATA_SHORT_8703B(__pTxDesc, __Value)	SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 4, 1, __Value)
+	#define SET_TX_DESC_DATA_BW_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 5, 2, __Value)
+	#define SET_TX_DESC_DATA_LDPC_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 7, 1, __Value)
+	#define SET_TX_DESC_DATA_STBC_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 8, 2, __Value)
+	#define SET_TX_DESC_CTROL_STBC_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 10, 2, __Value)
+	#define SET_TX_DESC_RTS_SHORT_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 12, 1, __Value)
+	#define SET_TX_DESC_RTS_SC_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 13, 4, __Value)
+
+
+	/* Dword 6 */
+	#define SET_TX_DESC_SW_DEFINE_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 0, 12, __Value)
+	#define SET_TX_DESC_MBSSID_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 12, 4, __Value)
+	#define SET_TX_DESC_ANTSEL_A_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 16, 3, __Value)
+	#define SET_TX_DESC_ANTSEL_B_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 19, 3, __Value)
+	#define SET_TX_DESC_ANTSEL_C_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 22, 3, __Value)
+	#define SET_TX_DESC_ANTSEL_D_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 25, 3, __Value)
+
+	/* Dword 7 */
+	#ifdef CONFIG_PCI_HCI
+		#define SET_TX_DESC_TX_BUFFER_SIZE_8703B(__pTxDesc, __Value)		SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 0, 16, __Value)
+	#endif /*CONFIG_PCI_HCI*/
+	#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_USB_HCI)
+		#define SET_TX_DESC_TX_DESC_CHECKSUM_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 0, 16, __Value)
+	#endif
+	#define SET_TX_DESC_USB_TXAGG_NUM_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 24, 8, __Value)
+	#ifdef CONFIG_SDIO_HCI
+		#define SET_TX_DESC_SDIO_TXSEQ_8703B(__pTxDesc, __Value)			SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 16, 8, __Value)
+	#endif
+
+	/* Dword 8 */
+	#define SET_TX_DESC_HWSEQ_EN_8703B(__pTxDesc, __Value)			SET_BITS_TO_LE_4BYTE(__pTxDesc+32, 15, 1, __Value)
+
+	/* Dword 9 */
+	#define SET_TX_DESC_SEQ_8703B(__pTxDesc, __Value)					SET_BITS_TO_LE_4BYTE(__pTxDesc+36, 12, 12, __Value)
+
+	/* Dword 10 */
+	#define SET_TX_DESC_TX_BUFFER_ADDRESS_8703B(__pTxDesc, __Value)	SET_BITS_TO_LE_4BYTE(__pTxDesc+40, 0, 32, __Value)
+	#define GET_TX_DESC_TX_BUFFER_ADDRESS_8703B(__pTxDesc)	LE_BITS_TO_4BYTE(__pTxDesc+40, 0, 32)
+
+	/* Dword 11 */
+	#define SET_TX_DESC_NEXT_DESC_ADDRESS_8703B(__pTxDesc, __Value)	SET_BITS_TO_LE_4BYTE(__pTxDesc+48, 0, 32, __Value)
+
+
+	#define SET_EARLYMODE_PKTNUM_8703B(__pAddr, __Value)					SET_BITS_TO_LE_4BYTE(__pAddr, 0, 4, __Value)
+	#define SET_EARLYMODE_LEN0_8703B(__pAddr, __Value)					SET_BITS_TO_LE_4BYTE(__pAddr, 4, 15, __Value)
+	#define SET_EARLYMODE_LEN1_1_8703B(__pAddr, __Value)					SET_BITS_TO_LE_4BYTE(__pAddr, 19, 13, __Value)
+	#define SET_EARLYMODE_LEN1_2_8703B(__pAddr, __Value)					SET_BITS_TO_LE_4BYTE(__pAddr+4, 0, 2, __Value)
+	#define SET_EARLYMODE_LEN2_8703B(__pAddr, __Value)					SET_BITS_TO_LE_4BYTE(__pAddr+4, 2, 15,	__Value)
+	#define SET_EARLYMODE_LEN3_8703B(__pAddr, __Value)					SET_BITS_TO_LE_4BYTE(__pAddr+4, 17, 15, __Value)
+
+#endif
+/* -----------------------------------------------------------
+ *
+ *	Rate
+ *
+ * -----------------------------------------------------------
+ * CCK Rates, TxHT = 0 */
+#define DESC8703B_RATE1M				0x00
+#define DESC8703B_RATE2M				0x01
+#define DESC8703B_RATE5_5M				0x02
+#define DESC8703B_RATE11M				0x03
+
+/* OFDM Rates, TxHT = 0 */
+#define DESC8703B_RATE6M				0x04
+#define DESC8703B_RATE9M				0x05
+#define DESC8703B_RATE12M				0x06
+#define DESC8703B_RATE18M				0x07
+#define DESC8703B_RATE24M				0x08
+#define DESC8703B_RATE36M				0x09
+#define DESC8703B_RATE48M				0x0a
+#define DESC8703B_RATE54M				0x0b
+
+/* MCS Rates, TxHT = 1 */
+#define DESC8703B_RATEMCS0				0x0c
+#define DESC8703B_RATEMCS1				0x0d
+#define DESC8703B_RATEMCS2				0x0e
+#define DESC8703B_RATEMCS3				0x0f
+#define DESC8703B_RATEMCS4				0x10
+#define DESC8703B_RATEMCS5				0x11
+#define DESC8703B_RATEMCS6				0x12
+#define DESC8703B_RATEMCS7				0x13
+#define DESC8703B_RATEMCS8				0x14
+#define DESC8703B_RATEMCS9				0x15
+#define DESC8703B_RATEMCS10		0x16
+#define DESC8703B_RATEMCS11		0x17
+#define DESC8703B_RATEMCS12		0x18
+#define DESC8703B_RATEMCS13		0x19
+#define DESC8703B_RATEMCS14		0x1a
+#define DESC8703B_RATEMCS15		0x1b
+#define DESC8703B_RATEVHTSS1MCS0		0x2c
+#define DESC8703B_RATEVHTSS1MCS1		0x2d
+#define DESC8703B_RATEVHTSS1MCS2		0x2e
+#define DESC8703B_RATEVHTSS1MCS3		0x2f
+#define DESC8703B_RATEVHTSS1MCS4		0x30
+#define DESC8703B_RATEVHTSS1MCS5		0x31
+#define DESC8703B_RATEVHTSS1MCS6		0x32
+#define DESC8703B_RATEVHTSS1MCS7		0x33
+#define DESC8703B_RATEVHTSS1MCS8		0x34
+#define DESC8703B_RATEVHTSS1MCS9		0x35
+#define DESC8703B_RATEVHTSS2MCS0		0x36
+#define DESC8703B_RATEVHTSS2MCS1		0x37
+#define DESC8703B_RATEVHTSS2MCS2		0x38
+#define DESC8703B_RATEVHTSS2MCS3		0x39
+#define DESC8703B_RATEVHTSS2MCS4		0x3a
+#define DESC8703B_RATEVHTSS2MCS5		0x3b
+#define DESC8703B_RATEVHTSS2MCS6		0x3c
+#define DESC8703B_RATEVHTSS2MCS7		0x3d
+#define DESC8703B_RATEVHTSS2MCS8		0x3e
+#define DESC8703B_RATEVHTSS2MCS9		0x3f
+
+
+#define	RX_HAL_IS_CCK_RATE_8703B(pDesc)\
+	(GET_RX_STATUS_DESC_RX_RATE_8703B(pDesc) == DESC8703B_RATE1M || \
+	 GET_RX_STATUS_DESC_RX_RATE_8703B(pDesc) == DESC8703B_RATE2M || \
+	 GET_RX_STATUS_DESC_RX_RATE_8703B(pDesc) == DESC8703B_RATE5_5M || \
+	 GET_RX_STATUS_DESC_RX_RATE_8703B(pDesc) == DESC8703B_RATE11M)
+
+
+void rtl8703b_update_txdesc(struct xmit_frame *pxmitframe, u8 *pmem);
+void rtl8703b_fill_fake_txdesc(PADAPTER padapter, u8 *pDesc, u32 BufferLen, u8 IsPsPoll, u8 IsBTQosNull, u8 bDataFrame);
+#if defined(CONFIG_CONCURRENT_MODE)
+	void fill_txdesc_force_bmc_camid(struct pkt_attrib *pattrib, u8 *ptxdesc);
+#endif
+void fill_txdesc_bmc_tx_rate(struct pkt_attrib *pattrib, u8 *ptxdesc);
+
+#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
+	s32 rtl8703bs_init_xmit_priv(PADAPTER padapter);
+	void rtl8703bs_free_xmit_priv(PADAPTER padapter);
+	s32 rtl8703bs_hal_xmit(PADAPTER padapter, struct xmit_frame *pxmitframe);
+	s32 rtl8703bs_mgnt_xmit(PADAPTER padapter, struct xmit_frame *pmgntframe);
+	s32	rtl8703bs_hal_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe);
+	s32 rtl8703bs_xmit_buf_handler(PADAPTER padapter);
+	thread_return rtl8703bs_xmit_thread(thread_context context);
+	#define hal_xmit_handler rtl8703bs_xmit_buf_handler
+#endif
+
+#ifdef CONFIG_USB_HCI
+	s32 rtl8703bu_xmit_buf_handler(PADAPTER padapter);
+	#define hal_xmit_handler rtl8703bu_xmit_buf_handler
+
+
+	s32 rtl8703bu_init_xmit_priv(PADAPTER padapter);
+	void rtl8703bu_free_xmit_priv(PADAPTER padapter);
+	s32 rtl8703bu_hal_xmit(PADAPTER padapter, struct xmit_frame *pxmitframe);
+	s32 rtl8703bu_mgnt_xmit(PADAPTER padapter, struct xmit_frame *pmgntframe);
+	s32	 rtl8703bu_hal_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe);
+	/* s32 rtl8812au_xmit_buf_handler(PADAPTER padapter); */
+	void rtl8703bu_xmit_tasklet(void *priv);
+	s32 rtl8703bu_xmitframe_complete(_adapter *padapter, struct xmit_priv *pxmitpriv, struct xmit_buf *pxmitbuf);
+	void _dbg_dump_tx_info(_adapter	*padapter, int frame_tag, struct tx_desc *ptxdesc);
+#endif
+
+#ifdef CONFIG_PCI_HCI
+	s32 rtl8703be_init_xmit_priv(PADAPTER padapter);
+	void rtl8703be_free_xmit_priv(PADAPTER padapter);
+	struct xmit_buf *rtl8703be_dequeue_xmitbuf(struct rtw_tx_ring *ring);
+	void	rtl8703be_xmitframe_resume(_adapter *padapter);
+	s32 rtl8703be_hal_xmit(PADAPTER padapter, struct xmit_frame *pxmitframe);
+	s32 rtl8703be_mgnt_xmit(PADAPTER padapter, struct xmit_frame *pmgntframe);
+	s32	rtl8703be_hal_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe);
+	void rtl8703be_xmit_tasklet(void *priv);
+#endif
+
+u8	BWMapping_8703B(PADAPTER Adapter, struct pkt_attrib *pattrib);
+u8	SCMapping_8703B(PADAPTER Adapter, struct pkt_attrib	*pattrib);
+
+#endif
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/include/rtl8710b_cmd.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/rtl8710b_cmd.h
--- linux-5.6.3/3rdparty/rtl8821ce/include/rtl8710b_cmd.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/rtl8710b_cmd.h	2020-04-10 16:35:06.849661608 +0300
@@ -0,0 +1,175 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#ifndef __RTL8710B_CMD_H__
+#define __RTL8710B_CMD_H__
+
+/* ---------------------------------------------------------------------------------------------------------
+ * ----------------------------------    H2C CMD DEFINITION    ------------------------------------------------
+ * --------------------------------------------------------------------------------------------------------- */
+
+enum h2c_cmd_8710B {
+	/* Common Class: 000 */
+	H2C_8710B_RSVD_PAGE = 0x00,
+	H2C_8710B_MEDIA_STATUS_RPT = 0x01,
+	H2C_8710B_SCAN_ENABLE = 0x02,
+	H2C_8710B_KEEP_ALIVE = 0x03,
+	H2C_8710B_DISCON_DECISION = 0x04,
+	H2C_8710B_PSD_OFFLOAD = 0x05,
+	H2C_8710B_AP_OFFLOAD = 0x08,
+	H2C_8710B_BCN_RSVDPAGE = 0x09,
+	H2C_8710B_PROBERSP_RSVDPAGE = 0x0A,
+	H2C_8710B_FCS_RSVDPAGE = 0x10,
+	H2C_8710B_FCS_INFO = 0x11,
+	H2C_8710B_AP_WOW_GPIO_CTRL = 0x13,
+
+	/* PoweSave Class: 001 */
+	H2C_8710B_SET_PWR_MODE = 0x20,
+	H2C_8710B_PS_TUNING_PARA = 0x21,
+	H2C_8710B_PS_TUNING_PARA2 = 0x22,
+	H2C_8710B_P2P_LPS_PARAM = 0x23,
+	H2C_8710B_P2P_PS_OFFLOAD = 0x24,
+	H2C_8710B_PS_SCAN_ENABLE = 0x25,
+	H2C_8710B_SAP_PS_ = 0x26,
+	H2C_8710B_INACTIVE_PS_ = 0x27, /* Inactive_PS */
+	H2C_8710B_FWLPS_IN_IPS_ = 0x28,
+
+	/* Dynamic Mechanism Class: 010 */
+	H2C_8710B_MACID_CFG = 0x40,
+	H2C_8710B_TXBF = 0x41,
+	H2C_8710B_RSSI_SETTING = 0x42,
+	H2C_8710B_AP_REQ_TXRPT = 0x43,
+	H2C_8710B_INIT_RATE_COLLECT = 0x44,
+	H2C_8710B_RA_PARA_ADJUST = 0x46,
+
+	/* WOWLAN Class: 100 */
+	H2C_8710B_WOWLAN = 0x80,
+	H2C_8710B_REMOTE_WAKE_CTRL = 0x81,
+	H2C_8710B_AOAC_GLOBAL_INFO = 0x82,
+	H2C_8710B_AOAC_RSVD_PAGE = 0x83,
+	H2C_8710B_AOAC_RSVD_PAGE2 = 0x84,
+	H2C_8710B_D0_SCAN_OFFLOAD_CTRL = 0x85,
+	H2C_8710B_D0_SCAN_OFFLOAD_INFO = 0x86,
+	H2C_8710B_CHNL_SWITCH_OFFLOAD = 0x87,
+	H2C_8710B_P2P_OFFLOAD_RSVD_PAGE = 0x8A,
+	H2C_8710B_P2P_OFFLOAD = 0x8B,
+
+	H2C_8710B_RESET_TSF = 0xC0,
+	H2C_8710B_MAXID,
+};
+
+/* ---------------------------------------------------------------------------------------------------------
+ * ----------------------------------    H2C CMD CONTENT    --------------------------------------------------
+ * ---------------------------------------------------------------------------------------------------------
+ * _RSVDPAGE_LOC_CMD_0x00 */
+#define SET_8710B_H2CCMD_RSVDPAGE_LOC_PROBE_RSP(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
+#define SET_8710B_H2CCMD_RSVDPAGE_LOC_PSPOLL(__pH2CCmd, __Value)				SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 8, __Value)
+#define SET_8710B_H2CCMD_RSVDPAGE_LOC_NULL_DATA(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value)
+#define SET_8710B_H2CCMD_RSVDPAGE_LOC_QOS_NULL_DATA(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 8, __Value)
+#define SET_8710B_H2CCMD_RSVDPAGE_LOC_BT_QOS_NULL_DATA(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 0, 8, __Value)
+
+/* _PWR_MOD_CMD_0x20 */
+#define SET_8710B_H2CCMD_PWRMODE_PARM_MODE(__pH2CCmd, __Value)				SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
+#define SET_8710B_H2CCMD_PWRMODE_PARM_RLBM(__pH2CCmd, __Value)				SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 4, __Value)
+#define SET_8710B_H2CCMD_PWRMODE_PARM_SMART_PS(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 4, 4, __Value)
+#define SET_8710B_H2CCMD_PWRMODE_PARM_BCN_PASS_TIME(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value)
+#define SET_8710B_H2CCMD_PWRMODE_PARM_ALL_QUEUE_UAPSD(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 8, __Value)
+#define SET_8710B_H2CCMD_PWRMODE_PARM_BCN_EARLY_C2H_RPT(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 2, 1, __Value)
+#define SET_8710B_H2CCMD_PWRMODE_PARM_PWR_STATE(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 0, 8, __Value)
+
+#define GET_8710B_H2CCMD_PWRMODE_PARM_MODE(__pH2CCmd)					LE_BITS_TO_1BYTE(__pH2CCmd, 0, 8)
+
+/* _PS_TUNE_PARAM_CMD_0x21 */
+#define SET_8710B_H2CCMD_PSTUNE_PARM_BCN_TO_LIMIT(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
+#define SET_8710B_H2CCMD_PSTUNE_PARM_DTIM_TIMEOUT(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 0, 8, __Value)
+#define SET_8710B_H2CCMD_PSTUNE_PARM_ADOPT(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 0, 1, __Value)
+#define SET_8710B_H2CCMD_PSTUNE_PARM_PS_TIMEOUT(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 1, 7, __Value)
+#define SET_8710B_H2CCMD_PSTUNE_PARM_DTIM_PERIOD(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE(__pH2CCmd+3, 0, 8, __Value)
+
+/* _MACID_CFG_CMD_0x40 */
+#define SET_8710B_H2CCMD_MACID_CFG_MACID(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
+#define SET_8710B_H2CCMD_MACID_CFG_RAID(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 0, 5, __Value)
+#define SET_8710B_H2CCMD_MACID_CFG_SGI_EN(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 7, 1, __Value)
+#define SET_8710B_H2CCMD_MACID_CFG_BW(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 0, 2, __Value)
+#define SET_8710B_H2CCMD_MACID_CFG_NO_UPDATE(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 3, 1, __Value)
+#define SET_8710B_H2CCMD_MACID_CFG_VHT_EN(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 4, 2, __Value)
+#define SET_8710B_H2CCMD_MACID_CFG_DISPT(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 6, 1, __Value)
+#define SET_8710B_H2CCMD_MACID_CFG_DISRA(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 7, 1, __Value)
+#define SET_8710B_H2CCMD_MACID_CFG_RATE_MASK0(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd+3, 0, 8, __Value)
+#define SET_8710B_H2CCMD_MACID_CFG_RATE_MASK1(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd+4, 0, 8, __Value)
+#define SET_8710B_H2CCMD_MACID_CFG_RATE_MASK2(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd+5, 0, 8, __Value)
+#define SET_8710B_H2CCMD_MACID_CFG_RATE_MASK3(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd+6, 0, 8, __Value)
+
+/* _RSSI_SETTING_CMD_0x42 */
+#define SET_8710B_H2CCMD_RSSI_SETTING_MACID(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
+#define SET_8710B_H2CCMD_RSSI_SETTING_RSSI(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 0, 7, __Value)
+#define SET_8710B_H2CCMD_RSSI_SETTING_ULDL_STATE(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd+3, 0, 8, __Value)
+
+/* _AP_REQ_TXRPT_CMD_0x43 */
+#define SET_8710B_H2CCMD_APREQRPT_PARM_MACID1(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
+#define SET_8710B_H2CCMD_APREQRPT_PARM_MACID2(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 0, 8, __Value)
+
+/* _FORCE_BT_TXPWR_CMD_0x62 */
+#define SET_8710B_H2CCMD_BT_PWR_IDX(__pH2CCmd, __Value)							SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
+
+/* _FORCE_BT_MP_OPER_CMD_0x67 */
+#define SET_8710B_H2CCMD_BT_MPOPER_VER(__pH2CCmd, __Value)							SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 4, __Value)
+#define SET_8710B_H2CCMD_BT_MPOPER_REQNUM(__pH2CCmd, __Value)							SET_BITS_TO_LE_1BYTE(__pH2CCmd, 4, 4, __Value)
+#define SET_8710B_H2CCMD_BT_MPOPER_IDX(__pH2CCmd, __Value)							SET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 0, 8, __Value)
+#define SET_8710B_H2CCMD_BT_MPOPER_PARAM1(__pH2CCmd, __Value)							SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 0, 8, __Value)
+#define SET_8710B_H2CCMD_BT_MPOPER_PARAM2(__pH2CCmd, __Value)							SET_BITS_TO_LE_1BYTE(__pH2CCmd+3, 0, 8, __Value)
+#define SET_8710B_H2CCMD_BT_MPOPER_PARAM3(__pH2CCmd, __Value)							SET_BITS_TO_LE_1BYTE(__pH2CCmd+4, 0, 8, __Value)
+
+/* _BT_FW_PATCH_0x6A */
+#define SET_8710B_H2CCMD_BT_FW_PATCH_SIZE(__pH2CCmd, __Value)					SET_BITS_TO_LE_2BYTE((pu1Byte)(__pH2CCmd), 0, 16, __Value)
+#define SET_8710B_H2CCMD_BT_FW_PATCH_ADDR0(__pH2CCmd, __Value)					SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value)
+#define SET_8710B_H2CCMD_BT_FW_PATCH_ADDR1(__pH2CCmd, __Value)					SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 8, __Value)
+#define SET_8710B_H2CCMD_BT_FW_PATCH_ADDR2(__pH2CCmd, __Value)					SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 0, 8, __Value)
+#define SET_8710B_H2CCMD_BT_FW_PATCH_ADDR3(__pH2CCmd, __Value)					SET_BITS_TO_LE_1BYTE((__pH2CCmd)+5, 0, 8, __Value)
+
+/* ---------------------------------------------------------------------------------------------------------
+ * -------------------------------------------    Structure    --------------------------------------------------
+ * --------------------------------------------------------------------------------------------------------- */
+
+
+/* ---------------------------------------------------------------------------------------------------------
+ * ----------------------------------    Function Statement     --------------------------------------------------
+ * --------------------------------------------------------------------------------------------------------- */
+
+/* host message to firmware cmd */
+void rtl8710b_set_FwPwrMode_cmd(PADAPTER padapter, u8 Mode);
+void rtl8710b_set_FwJoinBssRpt_cmd(PADAPTER padapter, u8 mstatus);
+/* s32 rtl8710b_set_lowpwr_lps_cmd(PADAPTER padapter, u8 enable); */
+void rtl8710b_set_FwPsTuneParam_cmd(PADAPTER padapter);
+void rtl8710b_download_rsvd_page(PADAPTER padapter, u8 mstatus);
+#ifdef CONFIG_BT_COEXIST
+	void rtl8710b_download_BTCoex_AP_mode_rsvd_page(PADAPTER padapter);
+#endif /* CONFIG_BT_COEXIST */
+#ifdef CONFIG_P2P
+	void rtl8710b_set_p2p_ps_offload_cmd(PADAPTER padapter, u8 p2p_ps_state);
+#endif /* CONFIG_P2P */
+
+#ifdef CONFIG_TDLS
+#ifdef CONFIG_TDLS_CH_SW
+void rtl8710b_set_BcnEarly_C2H_Rpt_cmd(PADAPTER padapter, u8 enable);
+#endif
+#endif
+
+#ifdef CONFIG_P2P_WOWLAN
+	void rtl8710b_set_p2p_wowlan_offload_cmd(PADAPTER padapter);
+#endif
+
+s32 FillH2CCmd8710B(PADAPTER padapter, u8 ElementID, u32 CmdLen, u8 *pCmdBuffer);
+u8 GetTxBufferRsvdPageNum8710B(_adapter *padapter, bool wowlan);
+#endif
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/include/rtl8710b_dm.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/rtl8710b_dm.h
--- linux-5.6.3/3rdparty/rtl8821ce/include/rtl8710b_dm.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/rtl8710b_dm.h	2020-04-10 16:35:06.849661608 +0300
@@ -0,0 +1,39 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#ifndef __RTL8710B_DM_H__
+#define __RTL8710B_DM_H__
+/* ************************************************************
+ * Description:
+ *
+ * This file is for 8710B dynamic mechanism only
+ *
+ *
+ * ************************************************************ */
+
+/* ************************************************************
+ * structure and define
+ * ************************************************************ */
+
+/* ************************************************************
+ * function prototype
+ * ************************************************************ */
+
+void rtl8710b_init_dm_priv(PADAPTER padapter);
+void rtl8710b_deinit_dm_priv(PADAPTER padapter);
+
+void rtl8710b_InitHalDm(PADAPTER padapter);
+void rtl8710b_HalDmWatchDog(PADAPTER padapter);
+
+#endif
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/include/rtl8710b_hal.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/rtl8710b_hal.h
--- linux-5.6.3/3rdparty/rtl8821ce/include/rtl8710b_hal.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/rtl8710b_hal.h	2020-04-10 16:35:06.849661608 +0300
@@ -0,0 +1,277 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#ifndef __RTL8710B_HAL_H__
+#define __RTL8710B_HAL_H__
+
+#include "hal_data.h"
+
+#include "rtl8710b_spec.h"
+#include "rtl8710b_rf.h"
+#include "rtl8710b_dm.h"
+#include "rtl8710b_recv.h"
+#include "rtl8710b_xmit.h"
+#include "rtl8710b_cmd.h"
+#include "rtl8710b_led.h"
+#include "Hal8710BPwrSeq.h"
+#include "Hal8710BPhyReg.h"
+#include "Hal8710BPhyCfg.h"
+#ifdef DBG_CONFIG_ERROR_DETECT
+	#include "rtl8710b_sreset.h"
+#endif
+#ifdef CONFIG_LPS_POFF
+	#include "rtl8710b_lps_poff.h"
+#endif
+
+#define FW_8710B_SIZE		0x8000
+#define FW_8710B_START_ADDRESS	0x1000
+#define FW_8710B_END_ADDRESS	0x1FFF /* 0x5FFF */
+
+typedef struct _RT_FIRMWARE {
+	FIRMWARE_SOURCE	eFWSource;
+#ifdef CONFIG_EMBEDDED_FWIMG
+	u8			*szFwBuffer;
+#else
+	u8			szFwBuffer[FW_8710B_SIZE];
+#endif
+	u32			ulFwLength;
+} RT_FIRMWARE_8710B, *PRT_FIRMWARE_8710B;
+
+/*
+ * This structure must be cared byte-ordering
+ *
+ * Added by tynli. 2009.12.04. */
+typedef struct _RT_8710B_FIRMWARE_HDR {
+	/* 8-byte alinment required */
+
+	/* --- LONG WORD 0 ---- */
+	u16		Signature;	/* 92C0: test chip; 92C, 88C0: test chip; 88C1: MP A-cut; 92C1: MP A-cut */
+	u8		Category;	/* AP/NIC and USB/PCI */
+	u8		Function;	/* Reserved for different FW function indcation, for further use when driver needs to download different FW in different conditions */
+	u16		Version;		/* FW Version */
+	u16		Subversion;	/* FW Subversion, default 0x00 */
+
+	/* --- LONG WORD 1 ---- */
+	u8		Month;	/* Release time Month field */
+	u8		Date;	/* Release time Date field */
+	u8		Hour;	/* Release time Hour field */
+	u8		Minute;	/* Release time Minute field */
+	u16		RamCodeSize;	/* The size of RAM code */
+	u16		Rsvd2;
+
+	/* --- LONG WORD 2 ---- */
+	u32		SvnIdx;	/* The SVN entry index */
+	u32		Rsvd3;
+
+	/* --- LONG WORD 3 ---- */
+	u32		Rsvd4;
+	u32		Rsvd5;
+} RT_8710B_FIRMWARE_HDR, *PRT_8710B_FIRMWARE_HDR;
+
+#define DRIVER_EARLY_INT_TIME_8710B		0x05
+#define BCN_DMA_ATIME_INT_TIME_8710B		0x02
+
+/* for 8710B
+ * TX 32K, RX 16K, Page size 128B for TX, 8B for RX */
+#define PAGE_SIZE_TX_8710B			128
+#define PAGE_SIZE_RX_8710B			8
+
+#define TX_DMA_SIZE_8710B			0x8000	/* 32K(TX) */
+#define RX_DMA_SIZE_8710B			0x4000	/* 16K(RX) */
+
+#ifdef CONFIG_WOWLAN
+	#define RESV_FMWF	(WKFMCAM_SIZE * MAX_WKFM_CAM_NUM) /* 16 entries, for each is 24 bytes*/
+#else
+	#define RESV_FMWF	0
+#endif
+
+#ifdef CONFIG_FW_C2H_DEBUG
+	#define RX_DMA_RESERVED_SIZE_8710B	0x100	/* 256B, reserved for c2h debug message */
+#else
+	#define RX_DMA_RESERVED_SIZE_8710B	0x80	/* 128B, reserved for tx report */
+#endif
+#define RX_DMA_BOUNDARY_8710B\
+	(RX_DMA_SIZE_8710B - RX_DMA_RESERVED_SIZE_8710B - 1)
+
+
+/* Note: We will divide number of page equally for each queue other than public queue! */
+
+/* For General Reserved Page Number(Beacon Queue is reserved page)
+ * Beacon:MAX_BEACON_LEN/PAGE_SIZE_TX_8710B
+ * PS-Poll:1, Null Data:1,Qos Null Data:1,BT Qos Null Data:1,CTS-2-SELF,LTE QoS Null*/
+#define BCNQ_PAGE_NUM_8710B	(MAX_BEACON_LEN/PAGE_SIZE_TX_8710B + 6) /*0x08*/
+
+
+/* For WoWLan , more reserved page
+ * ARP Rsp:1, RWC:1, GTK Info:1,GTK RSP:2,GTK EXT MEM:2, AOAC rpt 1, PNO: 6
+ * NS offload: 2 NDP info: 1
+ */
+#ifdef CONFIG_WOWLAN
+	#define WOWLAN_PAGE_NUM_8710B	0x0b
+#else
+	#define WOWLAN_PAGE_NUM_8710B	0x00
+#endif
+
+#ifdef CONFIG_PNO_SUPPORT
+	#undef WOWLAN_PAGE_NUM_8710B
+	#define WOWLAN_PAGE_NUM_8710B	0x15
+#endif
+
+#ifdef CONFIG_AP_WOWLAN
+	#define AP_WOWLAN_PAGE_NUM_8710B	0x02
+#endif
+
+#define TX_TOTAL_PAGE_NUMBER_8710B\
+	(0xFF - BCNQ_PAGE_NUM_8710B -WOWLAN_PAGE_NUM_8710B)
+#define TX_PAGE_BOUNDARY_8710B		(TX_TOTAL_PAGE_NUMBER_8710B + 1)
+
+#define WMM_NORMAL_TX_TOTAL_PAGE_NUMBER_8710B	TX_TOTAL_PAGE_NUMBER_8710B
+#define WMM_NORMAL_TX_PAGE_BOUNDARY_8710B\
+	(WMM_NORMAL_TX_TOTAL_PAGE_NUMBER_8710B + 1)
+
+/* For Normal Chip Setting
+ * (HPQ + LPQ + NPQ + PUBQ) shall be TX_TOTAL_PAGE_NUMBER_8710B */
+#define NORMAL_PAGE_NUM_HPQ_8710B		0x0C
+#define NORMAL_PAGE_NUM_LPQ_8710B		0x02
+#define NORMAL_PAGE_NUM_NPQ_8710B		0x02
+#define NORMAL_PAGE_NUM_EPQ_8710B		0x04
+
+/* Note: For Normal Chip Setting, modify later */
+#define WMM_NORMAL_PAGE_NUM_HPQ_8710B		0x30
+#define WMM_NORMAL_PAGE_NUM_LPQ_8710B		0x20
+#define WMM_NORMAL_PAGE_NUM_NPQ_8710B		0x20
+#define WMM_NORMAL_PAGE_NUM_EPQ_8710B		0x00
+
+
+#include "HalVerDef.h"
+#include "hal_com.h"
+
+#define EFUSE_OOB_PROTECT_BYTES (96 + 1)
+
+#define HAL_EFUSE_MEMORY
+#define HWSET_MAX_SIZE_8710B                512
+#define EFUSE_REAL_CONTENT_LEN_8710B        512
+#define EFUSE_MAP_LEN_8710B                 512
+#define EFUSE_MAX_SECTION_8710B             64
+
+/* For some inferiority IC purpose. added by Roger, 2009.09.02.*/
+#define EFUSE_IC_ID_OFFSET			506
+#define AVAILABLE_EFUSE_ADDR(addr)	(addr < EFUSE_REAL_CONTENT_LEN_8710B)
+
+#define EFUSE_ACCESS_ON	0x69
+#define EFUSE_ACCESS_OFF	0x00
+
+#define   PACKAGE_QFN32_S           0
+#define   PACKAGE_QFN48M_S        1    //definiton 8188GU Dongle Package, Efuse Physical Address 0xF8 = 0xFE
+#define   PACKAGE_QFN48_S  	       2
+#define   PACKAGE_QFN64_S  	       3     
+#define   PACKAGE_QFN32_U  		4    
+#define   PACKAGE_QFN48M_U  	5   //definiton 8188GU Dongle Package, Efuse Physical Address 0xF8 = 0xEE
+#define   PACKAGE_QFN48_U  		6 
+#define   PACKAGE_QFN68_U  		7
+
+typedef enum _PACKAGE_TYPE_E
+{
+    PACKAGE_DEFAULT,
+    PACKAGE_QFN68,
+    PACKAGE_TFBGA90,
+    PACKAGE_TFBGA80,
+    PACKAGE_TFBGA79
+}PACKAGE_TYPE_E;
+
+#define INCLUDE_MULTI_FUNC_GPS(_Adapter) \
+	(GET_HAL_DATA(_Adapter)->MultiFunc & RT_MULTI_FUNC_GPS)
+
+#ifdef CONFIG_FILE_FWIMG
+	extern char *rtw_fw_file_path;
+	extern char *rtw_fw_wow_file_path;
+	#ifdef CONFIG_MP_INCLUDED
+		extern char *rtw_fw_mp_bt_file_path;
+	#endif /* CONFIG_MP_INCLUDED */
+#endif /* CONFIG_FILE_FWIMG */
+
+/* rtl8710b_hal_init.c */
+s32 rtl8710b_FirmwareDownload(PADAPTER padapter, BOOLEAN  bUsedWoWLANFw);
+void rtl8710b_FirmwareSelfReset(PADAPTER padapter);
+void rtl8710b_InitializeFirmwareVars(PADAPTER padapter);
+
+void rtl8710b_InitAntenna_Selection(PADAPTER padapter);
+void rtl8710b_DeinitAntenna_Selection(PADAPTER padapter);
+void rtl8710b_CheckAntenna_Selection(PADAPTER padapter);
+void rtl8710b_init_default_value(PADAPTER padapter);
+
+
+u32 indirect_read32_8710b(PADAPTER padapter, u32 regaddr);
+VOID indirect_write32_8710b(PADAPTER padapter, u32 regaddr, u32 data);
+u32 hal_query_syson_reg_8710b(PADAPTER padapter, u32 regaddr, u32 bitmask);
+VOID hal_set_syson_reg_8710b(PADAPTER padapter, u32 regaddr, u32 bitmask, u32 data);
+#define HAL_SetSYSOnReg hal_set_syson_reg_8710b
+
+
+/* EFuse */
+u8 GetEEPROMSize8710B(PADAPTER padapter);
+
+#if 0
+void Hal_InitPGData(PADAPTER padapter, u8 *PROMContent);
+void Hal_EfuseParseIDCode(PADAPTER padapter, u8 *hwinfo);
+void Hal_EfuseParseTxPowerInfo_8710B(PADAPTER padapter,
+				     u8 *PROMContent, BOOLEAN AutoLoadFail);
+void Hal_EfuseParseEEPROMVer_8710B(PADAPTER padapter,
+				   u8 *hwinfo, BOOLEAN AutoLoadFail);
+void Hal_EfuseParsePackageType_8710B(PADAPTER pAdapter,
+				     u8 *hwinfo, BOOLEAN AutoLoadFail);
+void Hal_EfuseParseChnlPlan_8710B(PADAPTER padapter,
+				  u8 *hwinfo, BOOLEAN AutoLoadFail);
+void Hal_EfuseParseCustomerID_8710B(PADAPTER padapter,
+				    u8 *hwinfo, BOOLEAN AutoLoadFail);
+void Hal_EfuseParseAntennaDiversity_8710B(PADAPTER padapter,
+		u8 *hwinfo, BOOLEAN AutoLoadFail);
+void Hal_EfuseParseXtal_8710B(PADAPTER pAdapter,
+			      u8 *hwinfo, u8 AutoLoadFail);
+void Hal_EfuseParseThermalMeter_8710B(PADAPTER padapter,
+				      u8 *hwinfo, u8 AutoLoadFail);
+VOID Hal_EfuseParseBoardType_8710B(PADAPTER Adapter,
+				   u8	*PROMContent, BOOLEAN AutoloadFail);
+#endif
+
+void rtl8710b_set_hal_ops(struct hal_ops *pHalFunc);
+void init_hal_spec_8710b(_adapter *adapter);
+u8 SetHwReg8710B(PADAPTER padapter, u8 variable, u8 *val);
+void GetHwReg8710B(PADAPTER padapter, u8 variable, u8 *val);
+u8 SetHalDefVar8710B(PADAPTER padapter, HAL_DEF_VARIABLE variable, void *pval);
+u8 GetHalDefVar8710B(PADAPTER padapter, HAL_DEF_VARIABLE variable, void *pval);
+
+/* register */
+void rtl8710b_InitBeaconParameters(PADAPTER padapter);
+void rtl8710b_InitBeaconMaxError(PADAPTER padapter, u8 InfraMode);
+void _8051Reset8710(PADAPTER padapter);
+
+void rtl8710b_start_thread(_adapter *padapter);
+void rtl8710b_stop_thread(_adapter *padapter);
+
+#ifdef CONFIG_GPIO_WAKEUP
+	void HalSetOutPutGPIO(PADAPTER padapter, u8 index, u8 OutPutValue);
+#endif
+
+void CCX_FwC2HTxRpt_8710b(PADAPTER padapter, u8 *pdata, u8 len);
+
+u8 MRateToHwRate8710B(u8 rate);
+u8 HwRateToMRate8710B(u8 rate);
+
+#ifdef CONFIG_USB_HCI
+	void rtl8710b_cal_txdesc_chksum(struct tx_desc *ptxdesc);
+#endif
+
+
+#endif
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/include/rtl8710b_led.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/rtl8710b_led.h
--- linux-5.6.3/3rdparty/rtl8821ce/include/rtl8710b_led.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/rtl8710b_led.h	2020-04-10 16:35:06.849661608 +0300
@@ -0,0 +1,44 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#ifndef __RTL8710B_LED_H__
+#define __RTL8710B_LED_H__
+
+#include <drv_conf.h>
+#include <osdep_service.h>
+#include <drv_types.h>
+
+#ifdef CONFIG_RTW_SW_LED
+/* ********************************************************************************
+ * Interface to manipulate LED objects.
+ * ******************************************************************************** */
+#ifdef CONFIG_USB_HCI
+	void rtl8710bu_InitSwLeds(PADAPTER padapter);
+	void rtl8710bu_DeInitSwLeds(PADAPTER padapter);
+#endif
+#ifdef CONFIG_SDIO_HCI
+	void rtl8710bs_InitSwLeds(PADAPTER padapter);
+	void rtl8710bs_DeInitSwLeds(PADAPTER padapter);
+#endif
+#ifdef CONFIG_GSPI_HCI
+	void rtl8710bs_InitSwLeds(PADAPTER padapter);
+	void rtl8710bs_DeInitSwLeds(PADAPTER padapter);
+#endif
+#ifdef CONFIG_PCI_HCI
+	void rtl8710be_InitSwLeds(PADAPTER padapter);
+	void rtl8710be_DeInitSwLeds(PADAPTER padapter);
+#endif
+
+#endif /*#ifdef CONFIG_RTW_SW_LED*/
+#endif
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/include/rtl8710b_lps_poff.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/rtl8710b_lps_poff.h
--- linux-5.6.3/3rdparty/rtl8821ce/include/rtl8710b_lps_poff.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/rtl8710b_lps_poff.h	2020-04-10 16:35:06.849661608 +0300
@@ -0,0 +1,56 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+
+/******************************************** CONST  ************************/
+#define NUM_OF_REGISTER_BANK	13
+#define NUM_OF_TOTAL_DWORD (NUM_OF_REGISTER_BANK * 64)
+#define TOTAL_LEN_FOR_HIOE ((NUM_OF_TOTAL_DWORD + 1) * 8)
+#define LPS_POFF_STATIC_FILE_LEN (TOTAL_LEN_FOR_HIOE + TXDESC_SIZE)
+#define LPS_POFF_DYNAMIC_FILE_LEN	(512 + TXDESC_SIZE)
+/******************************************** CONST  ************************/
+
+/******************************************** MACRO   ************************/
+/* HOIE Entry Definition */
+#define SET_HOIE_ENTRY_LOW_DATA(__pHOIE, __Value) \
+	SET_BITS_TO_LE_4BYTE((__pHOIE),	0, 16, __Value)
+#define SET_HOIE_ENTRY_HIGH_DATA(__pHOIE, __Value) \
+	SET_BITS_TO_LE_4BYTE((__pHOIE), 16, 16, __Value)
+#define SET_HOIE_ENTRY_MODE_SELECT(__pHOIE, __Value) \
+	SET_BITS_TO_LE_4BYTE((__pHOIE)+4, 0, 1, __Value)
+#define SET_HOIE_ENTRY_ADDRESS(__pHOIE, __Value) \
+	SET_BITS_TO_LE_4BYTE((__pHOIE)+4, 1, 14, __Value)
+#define SET_HOIE_ENTRY_BYTE_MASK(__pHOIE, __Value) \
+	SET_BITS_TO_LE_4BYTE((__pHOIE)+4, 15, 4, __Value)
+#define SET_HOIE_ENTRY_IO_LOCK(__pHOIE, __Value) \
+	SET_BITS_TO_LE_4BYTE((__pHOIE)+4, 19, 1, __Value)
+#define SET_HOIE_ENTRY_RD_EN(__pHOIE, __Value) \
+	SET_BITS_TO_LE_4BYTE((__pHOIE)+4, 20, 1, __Value)
+#define SET_HOIE_ENTRY_WR_EN(__pHOIE, __Value) \
+	SET_BITS_TO_LE_4BYTE((__pHOIE)+4, 21, 1, __Value)
+#define SET_HOIE_ENTRY_RAW_RW(__pHOIE, __Value) \
+	SET_BITS_TO_LE_4BYTE((__pHOIE)+4, 22, 1, __Value)
+#define SET_HOIE_ENTRY_RAW(__pHOIE, __Value) \
+	SET_BITS_TO_LE_4BYTE((__pHOIE)+4, 23, 1, __Value)
+#define SET_HOIE_ENTRY_IO_DELAY(__pHOIE, __Value) \
+	SET_BITS_TO_LE_4BYTE((__pHOIE)+4, 24, 8, __Value)
+
+/*********************Function Definition*******************************************/
+void rtl8710b_lps_poff_init(PADAPTER padapter);
+void rtl8710b_lps_poff_deinit(PADAPTER padapter);
+bool rtl8710b_lps_poff_get_txbndy_status(PADAPTER padapter);
+void rtl8710b_lps_poff_h2c_ctrl(PADAPTER padapter, u8 enable);
+void rtl8710b_lps_poff_set_ps_mode(PADAPTER padapter, bool bEnterLPS);
+bool rtl8710b_lps_poff_get_status(PADAPTER padapter);
+void rtl8710b_lps_poff_wow(PADAPTER padapter);
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/include/rtl8710b_recv.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/rtl8710b_recv.h
--- linux-5.6.3/3rdparty/rtl8821ce/include/rtl8710b_recv.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/rtl8710b_recv.h	2020-04-10 16:35:06.849661608 +0300
@@ -0,0 +1,85 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#ifndef __RTL8710B_RECV_H__
+#define __RTL8710B_RECV_H__
+
+#define RECV_BLK_SZ 512
+#define RECV_BLK_CNT 16
+#define RECV_BLK_TH RECV_BLK_CNT
+
+#if defined(CONFIG_USB_HCI)
+	#ifndef MAX_RECVBUF_SZ
+		#ifdef PLATFORM_OS_CE
+			#define MAX_RECVBUF_SZ (8192+1024) /* 8K+1k */
+		#else
+			#ifdef CONFIG_MINIMAL_MEMORY_USAGE
+				#define MAX_RECVBUF_SZ (4000) /* about 4K */
+			#else
+				#ifdef CONFIG_PLATFORM_MSTAR
+					#define MAX_RECVBUF_SZ (8192) /* 8K */
+				#elif defined(CONFIG_PLATFORM_HISILICON)
+					#define MAX_RECVBUF_SZ (16384) /* 16k */
+				#else
+					#define MAX_RECVBUF_SZ (15360) /* 15k < 16k */
+					/* #define MAX_RECVBUF_SZ (32768) */ /* 32k */
+					/* #define MAX_RECVBUF_SZ (20480) */ /* 20K */
+					/* #define MAX_RECVBUF_SZ (10240)  */ /* 10K */
+					/* #define MAX_RECVBUF_SZ (16384) */ /* 16k - 92E RX BUF :16K */
+				#endif
+			#endif
+		#endif
+	#endif /* !MAX_RECVBUF_SZ */
+#endif
+
+/* Rx smooth factor */
+#define	Rx_Smooth_Factor (20)
+
+/*-----------------------------------------------------------------*/
+/*	RTL8710B RX BUFFER DESC                                      */
+/*-----------------------------------------------------------------*/
+/*DWORD 0*/
+#define SET_RX_BUFFER_DESC_DATA_LENGTH_8710B(__pRxStatusDesc, __Value)		SET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 0, 14, __Value)
+#define SET_RX_BUFFER_DESC_LS_8710B(__pRxStatusDesc, __Value)	SET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 15, 1, __Value)
+#define SET_RX_BUFFER_DESC_FS_8710B(__pRxStatusDesc, __Value)		SET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 16, 1, __Value)
+#define SET_RX_BUFFER_DESC_TOTAL_LENGTH_8710B(__pRxStatusDesc, __Value)		SET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 16, 15, __Value)
+
+#define GET_RX_BUFFER_DESC_OWN_8710B(__pRxStatusDesc)		LE_BITS_TO_4BYTE(__pRxStatusDesc, 31, 1)
+#define GET_RX_BUFFER_DESC_LS_8710B(__pRxStatusDesc)		LE_BITS_TO_4BYTE(__pRxStatusDesc, 15, 1)
+#define GET_RX_BUFFER_DESC_FS_8710B(__pRxStatusDesc)		LE_BITS_TO_4BYTE(__pRxStatusDesc, 16, 1)
+#ifdef USING_RX_TAG
+	#define GET_RX_BUFFER_DESC_RX_TAG_8710B(__pRxStatusDesc)		LE_BITS_TO_4BYTE(__pRxStatusDesc, 16, 13)
+#else
+	#define GET_RX_BUFFER_DESC_TOTAL_LENGTH_8710B(__pRxStatusDesc)		LE_BITS_TO_4BYTE(__pRxStatusDesc, 16, 15)
+#endif
+
+/*DWORD 1*/
+#define SET_RX_BUFFER_PHYSICAL_LOW_8710B(__pRxStatusDesc, __Value)		SET_BITS_TO_LE_4BYTE(__pRxStatusDesc+4, 0, 32, __Value)
+
+/*DWORD 2*/
+#ifdef CONFIG_64BIT_DMA
+	#define SET_RX_BUFFER_PHYSICAL_HIGH_8710B(__pRxStatusDesc, __Value)		SET_BITS_TO_LE_4BYTE(__pRxStatusDesc+8, 0, 32, __Value)
+#else
+	#define SET_RX_BUFFER_PHYSICAL_HIGH_8710B(__pRxStatusDesc, __Value)
+#endif
+
+#ifdef CONFIG_USB_HCI
+	int rtl8710bu_init_recv_priv(_adapter *padapter);
+	void rtl8710bu_free_recv_priv(_adapter *padapter);
+	void rtl8710bu_init_recvbuf(_adapter *padapter, struct recv_buf *precvbuf);
+#endif
+
+void rtl8710b_query_rx_desc_status(union recv_frame *precvframe, u8 *pdesc);
+
+#endif /* __RTL8710B_RECV_H__ */
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/include/rtl8710b_rf.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/rtl8710b_rf.h
--- linux-5.6.3/3rdparty/rtl8821ce/include/rtl8710b_rf.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/rtl8710b_rf.h	2020-04-10 16:35:06.849661608 +0300
@@ -0,0 +1,20 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#ifndef __RTL8710B_RF_H__
+#define __RTL8710B_RF_H__
+
+int PHY_RF6052_Config8710B(IN PADAPTER pdapter);
+
+#endif
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/include/rtl8710b_spec.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/rtl8710b_spec.h
--- linux-5.6.3/3rdparty/rtl8821ce/include/rtl8710b_spec.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/rtl8710b_spec.h	2020-04-10 16:35:06.849661608 +0300
@@ -0,0 +1,481 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#ifndef __RTL8710B_SPEC_H__
+#define __RTL8710B_SPEC_H__
+
+#include <drv_conf.h>
+
+
+#define HAL_NAV_UPPER_UNIT_8710B		128		/* micro-second */
+
+/* -----------------------------------------------------
+ *
+ *	0x0000h ~ 0x00FFh	System Configuration
+ *
+ * ----------------------------------------------------- */
+#define REG_SYS_ISO_CTRL_8710B			0x0000	/* 2 Byte */
+#define REG_APS_FSMCO_8710B			0x0004	/* 4 Byte */
+#define REG_SYS_CLKR_8710B				0x0008	/* 2 Byte */
+#define REG_9346CR_8710B				0x000A	/* 2 Byte */
+#define REG_EE_VPD_8710B				0x000C	/* 2 Byte */
+#define REG_AFE_MISC_8710B				0x0010	/* 1 Byte */
+#define REG_SPS0_CTRL_8710B				0x0011	/* 7 Byte */
+#define REG_SPS_OCP_CFG_8710B			0x0018	/* 4 Byte */
+#define REG_RSV_CTRL_8710B				0x001C	/* 3 Byte */
+#define REG_RF_CTRL_8710B				0x001F	/* 1 Byte */
+#define REG_LPLDO_CTRL_8710B			0x0023	/* 1 Byte */
+#define REG_AFE_XTAL_CTRL_8710B		0x0024	/* 4 Byte */
+#define REG_AFE_PLL_CTRL_8710B			0x0028	/* 4 Byte */
+#define REG_MAC_PLL_CTRL_EXT_8710B		0x002c	/* 4 Byte */
+#define REG_EFUSE_CTRL_8710B			0x0030
+#define REG_EFUSE_TEST_8710B			0x0034
+#define REG_PWR_DATA_8710B				0x0038
+#define REG_CAL_TIMER_8710B				0x003C
+#define REG_ACLK_MON_8710B				0x003E
+#define REG_GPIO_MUXCFG_8710B			0x0040
+#define REG_GPIO_IO_SEL_8710B			0x0042
+#define REG_MAC_PINMUX_CFG_8710B		0x0043
+#define REG_GPIO_PIN_CTRL_8710B			0x0044
+#define REG_GPIO_INTM_8710B				0x0048
+#define REG_LEDCFG0_8710B				0x004C
+#define REG_LEDCFG1_8710B				0x004D
+#define REG_LEDCFG2_8710B				0x004E
+#define REG_LEDCFG3_8710B				0x004F
+#define REG_FSIMR_8710B					0x0050
+#define REG_FSISR_8710B					0x0054
+#define REG_HSIMR_8710B					0x0058
+#define REG_HSISR_8710B					0x005c
+#define REG_GPIO_EXT_CTRL				0x0060
+#define REG_PAD_CTRL1_8710B		0x0064
+#define REG_MULTI_FUNC_CTRL_8710B		0x0068
+#define REG_GPIO_STATUS_8710B			0x006C
+#define REG_SDIO_CTRL_8710B				0x0070
+#define REG_OPT_CTRL_8710B				0x0074
+#define REG_AFE_CTRL_4_8710B		0x0078
+#define REG_MCUFWDL_8710B				0x0080
+#define REG_8051FW_CTRL_8710B			0x0080
+#define REG_HMEBOX_DBG_0_8710B	0x0088
+#define REG_HMEBOX_DBG_1_8710B	0x008A
+#define REG_HMEBOX_DBG_2_8710B	0x008C
+#define REG_HMEBOX_DBG_3_8710B	0x008E
+#define REG_WLLPS_CTRL		0x0090
+
+#define REG_PMC_DBG_CTRL2_8710B			0x00CC
+#define	REG_EFUSE_BURN_GNT_8710B		0x00CF
+#define REG_HPON_FSM_8710B				0x00EC
+#define REG_SYS_CFG1_8710B				0x00F0
+#define REG_SYS_CFG_8710B				0x00FC
+#define REG_ROM_VERSION					0x00FD
+
+/* -----------------------------------------------------
+ *
+ *	0x0100h ~ 0x01FFh	MACTOP General Configuration
+ *
+ * ----------------------------------------------------- */
+#define REG_C2HEVT_CMD_ID_8710B	0x01A0
+#define REG_C2HEVT_CMD_SEQ_88XX		0x01A1
+#define REG_C2hEVT_CMD_CONTENT_88XX	0x01A2
+#define REG_C2HEVT_CMD_LEN_8710B        0x01AE
+#define REG_C2HEVT_CLEAR_8710B			0x01AF
+#define REG_MCUTST_1_8710B				0x01C0
+#define REG_WOWLAN_WAKE_REASON 0x01C7
+#define REG_FMETHR_8710B				0x01C8
+#define REG_HMETFR_8710B				0x01CC
+#define REG_HMEBOX_0_8710B				0x01D0
+#define REG_HMEBOX_1_8710B				0x01D4
+#define REG_HMEBOX_2_8710B				0x01D8
+#define REG_HMEBOX_3_8710B				0x01DC
+#define REG_LLT_INIT_8710B				0x01E0
+#define REG_HMEBOX_EXT0_8710B			0x01F0
+#define REG_HMEBOX_EXT1_8710B			0x01F4
+#define REG_HMEBOX_EXT2_8710B			0x01F8
+#define REG_HMEBOX_EXT3_8710B			0x01FC
+
+/* -----------------------------------------------------
+ *
+ *	0x0200h ~ 0x027Fh	TXDMA Configuration
+ *
+ * ----------------------------------------------------- */
+#define REG_RQPN_8710B					0x0200
+#define REG_FIFOPAGE_8710B				0x0204
+#define REG_DWBCN0_CTRL_8710B			REG_TDECTRL
+#define REG_TXDMA_OFFSET_CHK_8710B	0x020C
+#define REG_TXDMA_STATUS_8710B		0x0210
+#define REG_RQPN_NPQ_8710B			0x0214
+#define REG_DWBCN1_CTRL_8710B			0x0228
+
+
+/* -----------------------------------------------------
+ *
+ *	0x0280h ~ 0x02FFh	RXDMA Configuration
+ *
+ * ----------------------------------------------------- */
+#define REG_RXDMA_AGG_PG_TH_8710B		0x0280
+#define REG_FW_UPD_RDPTR_8710B		0x0284 /* FW shall update this register before FW write RXPKT_RELEASE_POLL to 1 */
+#define REG_RXDMA_CONTROL_8710B		0x0286 /* Control the RX DMA. */
+#define REG_RXDMA_STATUS_8710B			0x0288
+#define REG_RXDMA_MODE_CTRL_8710B		0x0290
+#define REG_EARLY_MODE_CONTROL_8710B	0x02BC
+#define REG_RSVD5_8710B					0x02F0
+#define REG_RSVD6_8710B					0x02F4
+
+/* -----------------------------------------------------
+ *
+ *	0x0300h ~ 0x03FFh	PCIe
+ *
+ * ----------------------------------------------------- */
+#define	REG_PCIE_CTRL_REG_8710B			0x0300
+#define	REG_INT_MIG_8710B				0x0304	/* Interrupt Migration */
+#define	REG_BCNQ_TXBD_DESA_8710B		0x0308	/* TX Beacon Descriptor Address */
+#define	REG_MGQ_TXBD_DESA_8710B			0x0310	/* TX Manage Queue Descriptor Address */
+#define	REG_VOQ_TXBD_DESA_8710B			0x0318	/* TX VO Queue Descriptor Address */
+#define	REG_VIQ_TXBD_DESA_8710B			0x0320	/* TX VI Queue Descriptor Address */
+#define	REG_BEQ_TXBD_DESA_8710B			0x0328	/* TX BE Queue Descriptor Address */
+#define	REG_BKQ_TXBD_DESA_8710B			0x0330	/* TX BK Queue Descriptor Address */
+#define	REG_RXQ_RXBD_DESA_8710B			0x0338	/* RX Queue	Descriptor Address */
+#define REG_HI0Q_TXBD_DESA_8710B		0x0340
+#define REG_HI1Q_TXBD_DESA_8710B		0x0348
+#define REG_HI2Q_TXBD_DESA_8710B		0x0350
+#define REG_HI3Q_TXBD_DESA_8710B		0x0358
+#define REG_HI4Q_TXBD_DESA_8710B		0x0360
+#define REG_HI5Q_TXBD_DESA_8710B		0x0368
+#define REG_HI6Q_TXBD_DESA_8710B		0x0370
+#define REG_HI7Q_TXBD_DESA_8710B		0x0378
+#define	REG_MGQ_TXBD_NUM_8710B			0x0380
+#define	REG_RX_RXBD_NUM_8710B			0x0382
+#define	REG_VOQ_TXBD_NUM_8710B			0x0384
+#define	REG_VIQ_TXBD_NUM_8710B			0x0386
+#define	REG_BEQ_TXBD_NUM_8710B			0x0388
+#define	REG_BKQ_TXBD_NUM_8710B			0x038A
+#define	REG_HI0Q_TXBD_NUM_8710B			0x038C
+#define	REG_HI1Q_TXBD_NUM_8710B			0x038E
+#define	REG_HI2Q_TXBD_NUM_8710B			0x0390
+#define	REG_HI3Q_TXBD_NUM_8710B			0x0392
+#define	REG_HI4Q_TXBD_NUM_8710B			0x0394
+#define	REG_HI5Q_TXBD_NUM_8710B			0x0396
+#define	REG_HI6Q_TXBD_NUM_8710B			0x0398
+#define	REG_HI7Q_TXBD_NUM_8710B			0x039A
+#define	REG_TSFTIMER_HCI_8710B			0x039C
+#define	REG_BD_RW_PTR_CLR_8710B			0x039C
+
+/* Read Write Point */
+#define	REG_VOQ_TXBD_IDX_8710B			0x03A0
+#define	REG_VIQ_TXBD_IDX_8710B			0x03A4
+#define	REG_BEQ_TXBD_IDX_8710B			0x03A8
+#define	REG_BKQ_TXBD_IDX_8710B			0x03AC
+#define	REG_MGQ_TXBD_IDX_8710B			0x03B0
+#define	REG_RXQ_TXBD_IDX_8710B			0x03B4
+#define	REG_HI0Q_TXBD_IDX_8710B			0x03B8
+#define	REG_HI1Q_TXBD_IDX_8710B			0x03BC
+#define	REG_HI2Q_TXBD_IDX_8710B			0x03C0
+#define	REG_HI3Q_TXBD_IDX_8710B			0x03C4
+#define	REG_HI4Q_TXBD_IDX_8710B			0x03C8
+#define	REG_HI5Q_TXBD_IDX_8710B			0x03CC
+#define	REG_HI6Q_TXBD_IDX_8710B			0x03D0
+#define	REG_HI7Q_TXBD_IDX_8710B			0x03D4
+
+#define	REG_PCIE_HCPWM_8710BE			0x03D8 /* ?????? */
+#define	REG_PCIE_HRPWM_8710BE			0x03DC	/* PCIe RPWM  ?????? */
+#define	REG_DBI_WDATA_V1_8710B			0x03E8
+#define	REG_DBI_RDATA_V1_8710B			0x03EC
+#define	REG_DBI_FLAG_V1_8710B			0x03F0
+#define REG_MDIO_V1_8710B				0x03F4
+#define REG_PCIE_MIX_CFG_8710B			0x03F8
+#define REG_HCI_MIX_CFG_8710B			0x03FC
+
+/* -----------------------------------------------------
+ *
+ *	0x0400h ~ 0x047Fh	Protocol Configuration
+ *
+ * ----------------------------------------------------- */
+#define REG_VOQ_INFORMATION_8710B		0x0400
+#define REG_VIQ_INFORMATION_8710B		0x0404
+#define REG_BEQ_INFORMATION_8710B		0x0408
+#define REG_BKQ_INFORMATION_8710B		0x040C
+#define REG_MGQ_INFORMATION_8710B		0x0410
+#define REG_HGQ_INFORMATION_8710B		0x0414
+#define REG_BCNQ_INFORMATION_8710B	0x0418
+#define REG_TXPKT_EMPTY_8710B			0x041A
+
+#define REG_FWHW_TXQ_CTRL_8710B		0x0420
+#define REG_HWSEQ_CTRL_8710B			0x0423
+#define REG_TXPKTBUF_BCNQ_BDNY_8710B	0x0424
+#define REG_TXPKTBUF_MGQ_BDNY_8710B	0x0425
+#define REG_LIFECTRL_CTRL_8710B			0x0426
+#define REG_MULTI_BCNQ_OFFSET_8710B	0x0427
+#define REG_SPEC_SIFS_8710B				0x0428
+#define REG_RL_8710B						0x042A
+#define REG_TXBF_CTRL_8710B				0x042C
+#define REG_DARFRC_8710B				0x0430
+#define REG_RARFRC_8710B				0x0438
+#define REG_RRSR_8710B					0x0440
+#define REG_ARFR0_8710B					0x0444
+#define REG_ARFR1_8710B					0x044C
+#define REG_CCK_CHECK_8710B				0x0454
+#define REG_AMPDU_MAX_TIME_8710B		0x0456
+#define REG_TXPKTBUF_BCNQ_BDNY1_8710B	0x0457
+
+#define REG_AMPDU_MAX_LENGTH_8710B	0x0458
+#define REG_TXPKTBUF_WMAC_LBK_BF_HD_8710B	0x045D
+#define REG_NDPA_OPT_CTRL_8710B		0x045F
+#define REG_FAST_EDCA_CTRL_8710B		0x0460
+#define REG_RD_RESP_PKT_TH_8710B		0x0463
+#define REG_DATA_SC_8710B				0x0483
+#ifdef CONFIG_WOWLAN
+	#define REG_TXPKTBUF_IV_LOW             0x0484
+	#define REG_TXPKTBUF_IV_HIGH            0x0488
+#endif
+#define REG_TXRPT_START_OFFSET		0x04AC
+#define REG_POWER_STAGE1_8710B		0x04B4
+#define REG_POWER_STAGE2_8710B		0x04B8
+#define REG_AMPDU_BURST_MODE_8710B	0x04BC
+#define REG_PKT_VO_VI_LIFE_TIME_8710B	0x04C0
+#define REG_PKT_BE_BK_LIFE_TIME_8710B	0x04C2
+#define REG_STBC_SETTING_8710B			0x04C4
+#define REG_HT_SINGLE_AMPDU_8710B		0x04C7
+#define REG_PROT_MODE_CTRL_8710B		0x04C8
+#define REG_MAX_AGGR_NUM_8710B		0x04CA
+#define REG_RTS_MAX_AGGR_NUM_8710B	0x04CB
+#define REG_BAR_MODE_CTRL_8710B		0x04CC
+#define REG_RA_TRY_RATE_AGG_LMT_8710B	0x04CF
+#define REG_MACID_PKT_DROP0_8710B		0x04D0
+#define REG_MACID_PKT_SLEEP_8710B		0x04D4
+
+/* -----------------------------------------------------
+ *
+ *	0x0500h ~ 0x05FFh	EDCA Configuration
+ *
+ * ----------------------------------------------------- */
+#define REG_EDCA_VO_PARAM_8710B		0x0500
+#define REG_EDCA_VI_PARAM_8710B		0x0504
+#define REG_EDCA_BE_PARAM_8710B		0x0508
+#define REG_EDCA_BK_PARAM_8710B		0x050C
+#define REG_BCNTCFG_8710B				0x0510
+#define REG_PIFS_8710B					0x0512
+#define REG_RDG_PIFS_8710B				0x0513
+#define REG_SIFS_CTX_8710B				0x0514
+#define REG_SIFS_TRX_8710B				0x0516
+#define REG_AGGR_BREAK_TIME_8710B		0x051A
+#define REG_SLOT_8710B					0x051B
+#define REG_TX_PTCL_CTRL_8710B			0x0520
+#define REG_TXPAUSE_8710B				0x0522
+#define REG_DIS_TXREQ_CLR_8710B		0x0523
+#define REG_RD_CTRL_8710B				0x0524
+/*
+ * Format for offset 540h-542h:
+ *	[3:0]:   TBTT prohibit setup in unit of 32us. The time for HW getting beacon content before TBTT.
+ *	[7:4]:   Reserved.
+ *	[19:8]:  TBTT prohibit hold in unit of 32us. The time for HW holding to send the beacon packet.
+ *	[23:20]: Reserved
+ * Description:
+ *	              |
+ * |<--Setup--|--Hold------------>|
+ *	--------------|----------------------
+ * |
+ * TBTT
+ * Note: We cannot update beacon content to HW or send any AC packets during the time between Setup and Hold.
+ * Described by Designer Tim and Bruce, 2011-01-14.
+ *   */
+#define REG_TBTT_PROHIBIT_8710B			0x0540
+#define REG_RD_NAV_NXT_8710B			0x0544
+#define REG_NAV_PROT_LEN_8710B			0x0546
+#define REG_BCN_CTRL_8710B				0x0550
+#define REG_BCN_CTRL_1_8710B			0x0551
+#define REG_MBID_NUM_8710B				0x0552
+#define REG_DUAL_TSF_RST_8710B			0x0553
+#define REG_BCN_INTERVAL_8710B			0x0554
+#define REG_DRVERLYINT_8710B			0x0558
+#define REG_BCNDMATIM_8710B			0x0559
+#define REG_ATIMWND_8710B				0x055A
+#define REG_USTIME_TSF_8710B			0x055C
+#define REG_BCN_MAX_ERR_8710B			0x055D
+#define REG_RXTSF_OFFSET_CCK_8710B		0x055E
+#define REG_RXTSF_OFFSET_OFDM_8710B	0x055F
+#define REG_TSFTR_8710B					0x0560
+#define REG_CTWND_8710B					0x0572
+#define REG_SECONDARY_CCA_CTRL_8710B	0x0577
+#define REG_PSTIMER_8710B				0x0580
+#define REG_TIMER0_8710B				0x0584
+#define REG_TIMER1_8710B				0x0588
+#define REG_ACMHWCTRL_8710B			0x05C0
+#define REG_SCH_TXCMD_8710B			0x05F8
+
+/* -----------------------------------------------------
+ *
+ *	0x0600h ~ 0x07FFh	WMAC Configuration
+ *
+ * ----------------------------------------------------- */
+#define REG_MAC_CR_8710B				0x0600
+#define REG_TCR_8710B					0x0604
+#define REG_RCR_8710B					0x0608
+#define REG_RX_PKT_LIMIT_8710B			0x060C
+#define REG_RX_DLK_TIME_8710B			0x060D
+#define REG_RX_DRVINFO_SZ_8710B		0x060F
+
+#define REG_MACID_8710B					0x0610
+#define REG_BSSID_8710B					0x0618
+#define REG_MAR_8710B					0x0620
+#define REG_MBIDCAMCFG_8710B			0x0628
+#define REG_WOWLAN_GTK_DBG1	0x630
+#define REG_WOWLAN_GTK_DBG2	0x634
+
+#define REG_USTIME_EDCA_8710B			0x0638
+#define REG_MAC_SPEC_SIFS_8710B		0x063A
+#define REG_RESP_SIFP_CCK_8710B			0x063C
+#define REG_RESP_SIFS_OFDM_8710B		0x063E
+#define REG_ACKTO_8710B					0x0640
+#define REG_CTS2TO_8710B				0x0641
+#define REG_EIFS_8710B					0x0642
+
+#define REG_NAV_UPPER_8710B			0x0652	/* unit of 128 */
+#define REG_TRXPTCL_CTL_8710B			0x0668
+
+/* Security */
+#define REG_CAMCMD_8710B				0x0670
+#define REG_CAMWRITE_8710B				0x0674
+#define REG_CAMREAD_8710B				0x0678
+#define REG_CAMDBG_8710B				0x067C
+#define REG_SECCFG_8710B				0x0680
+
+/* Power */
+#define REG_WOW_CTRL_8710B				0x0690
+#define REG_PS_RX_INFO_8710B			0x0692
+#define REG_UAPSD_TID_8710B				0x0693
+#define REG_WKFMCAM_CMD_8710B			0x0698
+#define REG_WKFMCAM_NUM_8710B			0x0698
+#define REG_WKFMCAM_RWD_8710B			0x069C
+#define REG_RXFLTMAP0_8710B				0x06A0
+#define REG_RXFLTMAP1_8710B				0x06A2
+#define REG_RXFLTMAP2_8710B				0x06A4
+#define REG_BCN_PSR_RPT_8710B			0x06A8
+#define REG_BT_COEX_TABLE_8710B		0x06C0
+#define REG_BFMER0_INFO_8710B			0x06E4
+#define REG_BFMER1_INFO_8710B			0x06EC
+#define REG_CSI_RPT_PARAM_BW20_8710B	0x06F4
+#define REG_CSI_RPT_PARAM_BW40_8710B	0x06F8
+#define REG_CSI_RPT_PARAM_BW80_8710B	0x06FC
+
+/* Hardware Port 2 */
+#define REG_MACID1_8710B				0x0700
+#define REG_BSSID1_8710B				0x0708
+#define REG_BFMEE_SEL_8710B				0x0714
+#define REG_SND_PTCL_CTRL_8710B		0x0718
+
+/* LTR */
+#define REG_LTR_CTRL_BASIC_8710B		0x07A4
+#define REG_LTR_IDLE_LATENCY_V1_8710B		0x0798
+#define REG_LTR_ACTIVE_LATENCY_V1_8710B		0x079C
+
+/* LTE_COEX */
+#define REG_LTECOEX_CTRL			0x07C0
+#define REG_LTECOEX_WRITE_DATA		0x07C4
+#define REG_LTECOEX_READ_DATA		0x07C8
+#define REG_LTECOEX_PATH_CONTROL	0x70
+
+/* Other */
+#define REG_USB_ACCESS_TIMEOUT 0xFE4C
+
+/* -----------------------------------------------------
+ * SYSON_REG_SPEC
+ * ----------------------------------------------------- */
+#define SYSON_REG_BASE_ADDR_8710B 0x40000000
+#define REG_SYS_XTAL_CTRL0	0x0060
+#define REG_SYS_SYSTEM_CFG0 0x1F0
+#define REG_SYS_SYSTEM_CFG1 0x1F4
+#define REG_SYS_SYSTEM_CFG2 0x1F8
+#define REG_SYS_EEPROM_CTRL0 0x0E0
+
+
+/* -----------------------------------------------------
+ * Indirect_R/W_SPEC
+ * ----------------------------------------------------- */
+#define NORMAL_REG_READ_OFFSET 0x83000000
+#define NORMAL_REG_WRITE_OFFSET 0x84000000
+#define EFUSE_READ_OFFSET 0x85000000
+#define EFUSE_WRITE_OFFSET 0x86000000
+
+
+/* -----------------------------------------------------
+ * PAGE0_WLANON_REG_SPEC
+ * ----------------------------------------------------- */
+#define PAGE0_OFFSET 0x0 // WLANON_PAGE0_REG needs to add an offset.
+
+
+
+/* ****************************************************************************
+ *	8723 Regsiter Bit and Content definition
+ * **************************************************************************** */
+ 
+ /* -----------------------------------------------------
+ * REG_SYS_SYSTEM_CFG0 
+ * ----------------------------------------------------- */
+#define BIT_RTL_ID_8710B BIT(16)
+
+#define BIT_MASK_CHIP_VER_8710B 0xf
+#define BIT_GET_CHIP_VER_8710B(x) ((x) & BIT_MASK_CHIP_VER_8710B)
+
+#define BIT_SHIFT_VENDOR_ID_8710B 4
+#define BIT_MASK_VENDOR_ID_8710B 0xf
+#define BIT_GET_VENDOR_ID_8710B(x) (((x) >> BIT_SHIFT_VENDOR_ID_8710B) & BIT_MASK_VENDOR_ID_8710B)
+
+ /* -----------------------------------------------------
+ * REG_SYS_SYSTEM_CFG1 
+ * ----------------------------------------------------- */
+#define BIT_SPSLDO_SEL_8710B BIT(25)
+
+ /* -----------------------------------------------------
+ * REG_SYS_SYSTEM_CFG2 
+ * ----------------------------------------------------- */
+#define BIT_MASK_RF_RL_ID_8710B 0xf
+#define BIT_GET_RF_RL_ID_8710B(x) ((x) & BIT_MASK_RF_RL_ID_8710B)
+
+ /* -----------------------------------------------------
+ * REG_SYS_SYSTEM_CFG2 
+ * ----------------------------------------------------- */
+#define BIT_EERPOMSEL_8710B BIT(4)
+#define BIT_AUTOLOAD_SUS_8710B BIT(5)
+
+
+ /* -----------------------------------------------------
+ * Other
+ * ----------------------------------------------------- */
+
+
+#define BIT_USB_RXDMA_AGG_EN	BIT(31)
+#define RXDMA_AGG_MODE_EN		BIT(1)
+
+#ifdef CONFIG_WOWLAN
+	#define RXPKT_RELEASE_POLL		BIT(16)
+	#define RXDMA_IDLE				BIT(17)
+	#define RW_RELEASE_EN			BIT(18)
+#endif
+
+/* 2 HSISR
+ * interrupt mask which needs to clear */
+#define MASK_HSISR_CLEAR		(HSISR_GPIO12_0_INT |\
+		HSISR_SPS_OCP_INT |\
+		HSISR_RON_INT |\
+		HSISR_PDNINT |\
+		HSISR_GPIO9_INT)
+
+#ifdef CONFIG_RF_POWER_TRIM
+	#ifdef CONFIG_RTL8710B
+		#define EEPROM_RF_GAIN_OFFSET			0xC1
+	#endif
+
+	#define EEPROM_RF_GAIN_VAL				0x1F6
+#endif /*CONFIG_RF_POWER_TRIM*/
+
+#endif /* __RTL8710B_SPEC_H__ */
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/include/rtl8710b_sreset.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/rtl8710b_sreset.h
--- linux-5.6.3/3rdparty/rtl8821ce/include/rtl8710b_sreset.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/rtl8710b_sreset.h	2020-04-10 16:35:06.849661608 +0300
@@ -0,0 +1,24 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#ifndef _RTL8710B_SRESET_H_
+#define _RTL8710B_SRESET_H_
+
+#include <rtw_sreset.h>
+
+#ifdef DBG_CONFIG_ERROR_DETECT
+	extern void rtl8710b_sreset_xmit_status_check(_adapter *padapter);
+	extern void rtl8710b_sreset_linked_status_check(_adapter *padapter);
+#endif
+#endif
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/include/rtl8710b_xmit.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/rtl8710b_xmit.h
--- linux-5.6.3/3rdparty/rtl8821ce/include/rtl8710b_xmit.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/rtl8710b_xmit.h	2020-04-10 16:35:06.849661608 +0300
@@ -0,0 +1,522 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#ifndef __RTL8710B_XMIT_H__
+#define __RTL8710B_XMIT_H__
+
+
+#define MAX_TID (15)
+
+
+#ifndef __INC_HAL8710BDESC_H
+#define __INC_HAL8710BDESC_H
+
+#define RX_STATUS_DESC_SIZE_8710B		24
+#define RX_DRV_INFO_SIZE_UNIT_8710B 8
+
+
+/* DWORD 0 */
+#define SET_RX_STATUS_DESC_PKT_LEN_8710B(__pRxStatusDesc, __Value) \
+	SET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 0, 14, __Value)
+#define SET_RX_STATUS_DESC_EOR_8710B(__pRxStatusDesc, __Value) \
+	SET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 30, 1, __Value)
+#define SET_RX_STATUS_DESC_OWN_8710B(__pRxStatusDesc, __Value) \
+	SET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 31, 1, __Value)
+
+#define GET_RX_STATUS_DESC_PKT_LEN_8710B(__pRxStatusDesc) \
+	LE_BITS_TO_4BYTE(__pRxStatusDesc, 0, 14)
+#define GET_RX_STATUS_DESC_CRC32_8710B(__pRxStatusDesc) \
+	LE_BITS_TO_4BYTE(__pRxStatusDesc, 14, 1)
+#define GET_RX_STATUS_DESC_ICV_8710B(__pRxStatusDesc) \
+	LE_BITS_TO_4BYTE(__pRxStatusDesc, 15, 1)
+#define GET_RX_STATUS_DESC_DRVINFO_SIZE_8710B(__pRxStatusDesc) \
+	LE_BITS_TO_4BYTE(__pRxStatusDesc, 16, 4)
+#define GET_RX_STATUS_DESC_SECURITY_8710B(__pRxStatusDesc) \
+	LE_BITS_TO_4BYTE(__pRxStatusDesc, 20, 3)
+#define GET_RX_STATUS_DESC_QOS_8710B(__pRxStatusDesc) \
+	LE_BITS_TO_4BYTE(__pRxStatusDesc, 23, 1)
+#define GET_RX_STATUS_DESC_SHIFT_8710B(__pRxStatusDesc) \
+	LE_BITS_TO_4BYTE(__pRxStatusDesc, 24, 2)
+#define GET_RX_STATUS_DESC_PHY_STATUS_8710B(__pRxStatusDesc) \
+	LE_BITS_TO_4BYTE(__pRxStatusDesc, 26, 1)
+#define GET_RX_STATUS_DESC_SWDEC_8710B(__pRxStatusDesc) \
+	LE_BITS_TO_4BYTE(__pRxStatusDesc, 27, 1)
+#define GET_RX_STATUS_DESC_EOR_8710B(__pRxStatusDesc) \
+	LE_BITS_TO_4BYTE(__pRxStatusDesc, 30, 1)
+#define GET_RX_STATUS_DESC_OWN_8710B(__pRxStatusDesc) \
+	LE_BITS_TO_4BYTE(__pRxStatusDesc, 31, 1)
+
+/* DWORD 1 */
+#define GET_RX_STATUS_DESC_MACID_8710B(__pRxDesc) \
+	LE_BITS_TO_4BYTE(__pRxDesc+4, 0, 7)
+#define GET_RX_STATUS_DESC_TID_8710B(__pRxDesc) \
+	LE_BITS_TO_4BYTE(__pRxDesc+4, 8, 4)
+#define GET_RX_STATUS_DESC_AMSDU_8710B(__pRxDesc) \
+	LE_BITS_TO_4BYTE(__pRxDesc+4, 13, 1)
+#define GET_RX_STATUS_DESC_RXID_MATCH_8710B(__pRxDesc) \
+	LE_BITS_TO_4BYTE(__pRxDesc+4, 14, 1)
+#define GET_RX_STATUS_DESC_PAGGR_8710B(__pRxDesc) \
+	LE_BITS_TO_4BYTE(__pRxDesc+4, 15, 1)
+#define GET_RX_STATUS_DESC_A1_FIT_8710B(__pRxDesc) \
+	LE_BITS_TO_4BYTE(__pRxDesc+4, 16, 4)
+#define GET_RX_STATUS_DESC_CHKERR_8710B(__pRxDesc) \
+	LE_BITS_TO_4BYTE(__pRxDesc+4, 20, 1)
+#define GET_RX_STATUS_DESC_IPVER_8710B(__pRxDesc) \
+	LE_BITS_TO_4BYTE(__pRxDesc+4, 21, 1)
+#define GET_RX_STATUS_DESC_IS_TCPUDP__8710B(__pRxDesc) \
+	LE_BITS_TO_4BYTE(__pRxDesc+4, 22, 1)
+#define GET_RX_STATUS_DESC_CHK_VLD_8710B(__pRxDesc) \
+	LE_BITS_TO_4BYTE(__pRxDesc+4, 23, 1)
+#define GET_RX_STATUS_DESC_PAM_8710B(__pRxDesc) \
+	LE_BITS_TO_4BYTE(__pRxDesc+4, 24, 1)
+#define GET_RX_STATUS_DESC_PWR_8710B(__pRxDesc) \
+	LE_BITS_TO_4BYTE(__pRxDesc+4, 25, 1)
+#define GET_RX_STATUS_DESC_MORE_DATA_8710B(__pRxDesc) \
+	LE_BITS_TO_4BYTE(__pRxDesc+4, 26, 1)
+#define GET_RX_STATUS_DESC_MORE_FRAG_8710B(__pRxDesc) \
+	LE_BITS_TO_4BYTE(__pRxDesc+4, 27, 1)
+#define GET_RX_STATUS_DESC_TYPE_8710B(__pRxDesc) \
+	LE_BITS_TO_4BYTE(__pRxDesc+4, 28, 2)
+#define GET_RX_STATUS_DESC_MC_8710B(__pRxDesc) \
+	LE_BITS_TO_4BYTE(__pRxDesc+4, 30, 1)
+#define GET_RX_STATUS_DESC_BC_8710B(__pRxDesc) \
+	LE_BITS_TO_4BYTE(__pRxDesc+4, 31, 1)
+
+/* DWORD 2 */
+#define GET_RX_STATUS_DESC_SEQ_8710B(__pRxStatusDesc) \
+	LE_BITS_TO_4BYTE(__pRxStatusDesc+8, 0, 12)
+#define GET_RX_STATUS_DESC_FRAG_8710B(__pRxStatusDesc) \
+	LE_BITS_TO_4BYTE(__pRxStatusDesc+8, 12, 4)
+#define GET_RX_STATUS_DESC_RX_IS_QOS_8710B(__pRxStatusDesc) \
+	LE_BITS_TO_4BYTE(__pRxStatusDesc+8, 16, 1)
+#define GET_RX_STATUS_DESC_WLANHD_IV_LEN_8710B(__pRxStatusDesc) \
+	LE_BITS_TO_4BYTE(__pRxStatusDesc+8, 18, 6)
+#define GET_RX_STATUS_DESC_RPT_SEL_8710B(__pRxStatusDesc) \
+	LE_BITS_TO_4BYTE(__pRxStatusDesc+8, 28, 1)
+#define GET_RX_STATUS_DESC_FCS_OK_8710B(__pRxStatusDesc) \
+	LE_BITS_TO_4BYTE(__pRxStatusDesc+8, 31, 1)
+
+/* DWORD 3 */
+#define GET_RX_STATUS_DESC_RX_RATE_8710B(__pRxStatusDesc) \
+	LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 0, 7)
+#define GET_RX_STATUS_DESC_HTC_8710B(__pRxStatusDesc) \
+	LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 10, 1)
+#define GET_RX_STATUS_DESC_EOSP_8710B(__pRxStatusDesc) \
+	LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 11, 1)
+#define GET_RX_STATUS_DESC_BSSID_FIT_8710B(__pRxStatusDesc) \
+	LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 12, 2)
+#ifdef CONFIG_USB_RX_AGGREGATION
+#define GET_RX_STATUS_DESC_USB_AGG_PKTNUM_8710B(__pRxStatusDesc) \
+	LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 16, 8)
+#endif
+#define GET_RX_STATUS_DESC_PATTERN_MATCH_8710B(__pRxDesc) \
+	LE_BITS_TO_4BYTE(__pRxDesc+12, 29, 1)
+#define GET_RX_STATUS_DESC_UNICAST_MATCH_8710B(__pRxDesc) \
+	LE_BITS_TO_4BYTE(__pRxDesc+12, 30, 1)
+#define GET_RX_STATUS_DESC_MAGIC_MATCH_8710B(__pRxDesc) \
+	LE_BITS_TO_4BYTE(__pRxDesc+12, 31, 1)
+
+/* DWORD 6 */
+#define GET_RX_STATUS_DESC_MATCH_ID_8710B(__pRxDesc) \
+	LE_BITS_TO_4BYTE(__pRxDesc+16, 0, 7)
+
+/* DWORD 5 */
+#define GET_RX_STATUS_DESC_TSFL_8710B(__pRxStatusDesc) \
+	LE_BITS_TO_4BYTE(__pRxStatusDesc+20, 0, 32)
+
+#define GET_RX_STATUS_DESC_BUFF_ADDR_8710B(__pRxDesc) \
+	LE_BITS_TO_4BYTE(__pRxDesc+24, 0, 32)
+#define GET_RX_STATUS_DESC_BUFF_ADDR64_8710B(__pRxDesc) \
+	LE_BITS_TO_4BYTE(__pRxDesc+28, 0, 32)
+
+#define SET_RX_STATUS_DESC_BUFF_ADDR_8710B(__pRxDesc, __Value) \
+	SET_BITS_TO_LE_4BYTE(__pRxDesc+24, 0, 32, __Value)
+
+
+/* Dword 0, rsvd: bit26, bit28 */
+#define GET_TX_DESC_OWN_8710B(__pTxDesc)\
+	LE_BITS_TO_4BYTE(__pTxDesc, 31, 1)
+
+#define SET_TX_DESC_PKT_SIZE_8710B(__pTxDesc, __Value) \
+	SET_BITS_TO_LE_4BYTE(__pTxDesc, 0, 16, __Value)
+#define SET_TX_DESC_OFFSET_8710B(__pTxDesc, __Value) \
+	SET_BITS_TO_LE_4BYTE(__pTxDesc, 16, 8, __Value)
+#define SET_TX_DESC_BMC_8710B(__pTxDesc, __Value) \
+	SET_BITS_TO_LE_4BYTE(__pTxDesc, 24, 1, __Value)
+#define SET_TX_DESC_HTC_8710B(__pTxDesc, __Value) \
+	SET_BITS_TO_LE_4BYTE(__pTxDesc, 25, 1, __Value)
+#define SET_TX_DESC_AMSDU_PAD_EN_8710B(__pTxDesc, __Value) \
+	SET_BITS_TO_LE_4BYTE(__pTxDesc, 27, 1, __Value)
+#define SET_TX_DESC_NO_ACM_8710B(__pTxDesc, __Value) \
+	SET_BITS_TO_LE_4BYTE(__pTxDesc, 29, 1, __Value)
+#define SET_TX_DESC_GF_8710B(__pTxDesc, __Value) \
+	SET_BITS_TO_LE_4BYTE(__pTxDesc, 30, 1, __Value)
+
+/* Dword 1 */
+#define SET_TX_DESC_MACID_8710B(__pTxDesc, __Value) \
+	SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 0, 7, __Value)
+#define SET_TX_DESC_QUEUE_SEL_8710B(__pTxDesc, __Value) \
+	SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 8, 5, __Value)
+#define SET_TX_DESC_RDG_NAV_EXT_8710B(__pTxDesc, __Value) \
+	SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 13, 1, __Value)
+#define SET_TX_DESC_LSIG_TXOP_EN_8710B(__pTxDesc, __Value) \
+	SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 14, 1, __Value)
+#define SET_TX_DESC_PIFS_8710B(__pTxDesc, __Value) \
+	SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 15, 1, __Value)
+#define SET_TX_DESC_RATE_ID_8710B(__pTxDesc, __Value) \
+	SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 16, 5, __Value)
+#define SET_TX_DESC_EN_DESC_ID_8710B(__pTxDesc, __Value) \
+	SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 21, 1, __Value)
+#define SET_TX_DESC_SEC_TYPE_8710B(__pTxDesc, __Value) \
+	SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 22, 2, __Value)
+#define SET_TX_DESC_PKT_OFFSET_8710B(__pTxDesc, __Value) \
+	SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 24, 5, __Value)
+#define SET_TX_DESC_MORE_DATA_8710B(__pTxDesc, __Value) \
+	SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 29, 1, __Value)
+
+/* Dword 2  remove P_AID, G_ID field*/
+#define SET_TX_DESC_CCA_RTS_8710B(__pTxDesc, __Value) \
+	SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 10, 2, __Value)
+#define SET_TX_DESC_AGG_ENABLE_8710B(__pTxDesc, __Value) \
+	SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 12, 1, __Value)
+#define SET_TX_DESC_RDG_ENABLE_8710B(__pTxDesc, __Value) \
+	SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 13, 1, __Value)
+#define SET_TX_DESC_NULL0_8710B(__pTxDesc, __Value) \
+	SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 14, 1, __Value)
+#define SET_TX_DESC_NULL1_8710B(__pTxDesc, __Value) \
+	SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 15, 1, __Value)
+#define SET_TX_DESC_BK_8710B(__pTxDesc, __Value) \
+	SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 16, 1, __Value)
+#define SET_TX_DESC_MORE_FRAG_8710B(__pTxDesc, __Value) \
+	SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 17, 1, __Value)
+#define SET_TX_DESC_RAW_8710B(__pTxDesc, __Value) \
+	SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 18, 1, __Value)
+#define SET_TX_DESC_CCX_8710B(__pTxDesc, __Value) \
+	SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 19, 1, __Value)
+#define SET_TX_DESC_AMPDU_DENSITY_8710B(__pTxDesc, __Value) \
+	SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 20, 3, __Value)
+#define SET_TX_DESC_BT_INT_8710B(__pTxDesc, __Value) \
+	SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 23, 1, __Value)
+#define SET_TX_DESC_FTM_EN_8710B(__pTxDesc, __Value) \
+	SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 30, 1, __Value)
+
+/* Dword 3 */
+#define SET_TX_DESC_NAV_USE_HDR_8710B(__pTxDesc, __Value) \
+	SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 5, 1, __Value)
+#define SET_TX_DESC_HWSEQ_SEL_8710B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 6, 2, __Value)
+#define SET_TX_DESC_USE_RATE_8710B(__pTxDesc, __Value) \
+	SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 8, 1, __Value)
+#define SET_TX_DESC_DISABLE_RTS_FB_8710B(__pTxDesc, __Value) \
+	SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 9, 1, __Value)
+#define SET_TX_DESC_DISABLE_FB_8710B(__pTxDesc, __Value) \
+	SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 10, 1, __Value)
+#define SET_TX_DESC_CTS2SELF_8710B(__pTxDesc, __Value) \
+	SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 11, 1, __Value)
+#define SET_TX_DESC_RTS_ENABLE_8710B(__pTxDesc, __Value) \
+	SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 12, 1, __Value)
+#define SET_TX_DESC_HW_RTS_ENABLE_8710B(__pTxDesc, __Value) \
+	SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 13, 1, __Value)
+#define SET_TX_DESC_PORT_ID_8710B(__pTxDesc, __Value) \
+	SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 14, 2, __Value)
+#define SET_TX_DESC_USE_MAX_LEN_8710B(__pTxDesc, __Value) \
+	SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 16, 1, __Value)
+#define SET_TX_DESC_MAX_AGG_NUM_8710B(__pTxDesc, __Value) \
+	SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 17, 5, __Value)
+#define SET_TX_DESC_AMPDU_MAX_TIME_8710B(__pTxDesc, __Value) \
+	SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 24, 8, __Value)
+
+/* Dword 4 */
+#define SET_TX_DESC_TX_RATE_8710B(__pTxDesc, __Value) \
+	SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 0, 7, __Value)
+#define SET_TX_DESC_TX_TRY_RATE_8710B(__pTxDesc, __Value) \
+	SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 7, 1, __Value)
+#define SET_TX_DESC_DATA_RATE_FB_LIMIT_8710B(__pTxDesc, __Value) \
+	SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 8, 5, __Value)
+#define SET_TX_DESC_RTS_RATE_FB_LIMIT_8710B(__pTxDesc, __Value) \
+	SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 13, 4, __Value)
+#define SET_TX_DESC_RETRY_LIMIT_ENABLE_8710B(__pTxDesc, __Value) \
+	SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 17, 1, __Value)
+#define SET_TX_DESC_DATA_RETRY_LIMIT_8710B(__pTxDesc, __Value) \
+	SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 18, 6, __Value)
+#define SET_TX_DESC_RTS_RATE_8710B(__pTxDesc, __Value) \
+	SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 24, 5, __Value)
+#define SET_TX_DESC_PCTS_EN_8710B(__pTxDesc, __Value) \
+	SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 29, 1, __Value)
+#define SET_TX_DESC_PCTS_MASK_IDX_8710B(__pTxDesc, __Value) \
+	SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 30, 2, __Value)
+
+/* Dword 5 */
+#define SET_TX_DESC_DATA_SC_8710B(__pTxDesc, __Value) \
+	SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 0, 4, __Value)
+#define SET_TX_DESC_DATA_SHORT_8710B(__pTxDesc, __Value) \
+	SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 4, 1, __Value)
+#define SET_TX_DESC_DATA_BW_8710B(__pTxDesc, __Value) \
+	SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 5, 2, __Value)
+#define SET_TX_DESC_DATA_STBC_8710B(__pTxDesc, __Value) \
+	SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 8, 2, __Value)
+#define SET_TX_DESC_RTS_STBC_8710B(__pTxDesc, __Value) \
+	SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 10, 2, __Value)
+#define SET_TX_DESC_RTS_SHORT_8710B(__pTxDesc, __Value) \
+	SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 12, 1, __Value)
+#define SET_TX_DESC_RTS_SC_8710B(__pTxDesc, __Value) \
+	SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 13, 4, __Value)
+#define SET_TX_DESC_PATH_A_EN_8710B(__pTxDesc, __Value) \
+	SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 24, 1, __Value)
+#define SET_TX_DESC_TXPWR_OF_SET_8710B(__pTxDesc, __Value) \
+	SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 28, 3, __Value)
+
+/* Dword 6 */
+#define SET_TX_DESC_SW_DEFINE_8710B(__pTxDesc, __Value) \
+	SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 0, 12, __Value)
+#define SET_TX_DESC_MBSSID_8710B(__pTxDesc, __Value) \
+	SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 12, 4, __Value)
+#define SET_TX_DESC_RF_SEL_8710B(__pTxDesc, __Value) \
+	SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 16, 3, __Value)
+
+/* Dword 7 */
+#ifdef CONFIG_PCI_HCI
+#define SET_TX_DESC_TX_BUFFER_SIZE_8710B(__pTxDesc, __Value) \
+	SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 0, 16, __Value)
+#endif
+
+#ifdef CONFIG_USB_HCI
+#define SET_TX_DESC_TX_DESC_CHECKSUM_8710B(__pTxDesc, __Value) \
+	SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 0, 16, __Value)
+#endif
+
+#ifdef CONFIG_SDIO_HCI
+#define SET_TX_DESC_TX_TIMESTAMP_8710B(__pTxDesc, __Value) \
+	SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 6, 18, __Value)
+#endif
+
+#define SET_TX_DESC_USB_TXAGG_NUM_8710B(__pTxDesc, __Value) \
+	SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 24, 8, __Value)
+
+/* Dword 8 */
+#define SET_TX_DESC_RTS_RC_8710B(__pTxDesc, __Value) \
+	SET_BITS_TO_LE_4BYTE(__pTxDesc+32, 0, 6, __Value)
+#define SET_TX_DESC_BAR_RC_8710B(__pTxDesc, __Value) \
+	SET_BITS_TO_LE_4BYTE(__pTxDesc+32, 6, 2, __Value)
+#define SET_TX_DESC_DATA_RC_8710B(__pTxDesc, __Value) \
+	SET_BITS_TO_LE_4BYTE(__pTxDesc+32, 8, 6, __Value)
+#define SET_TX_DESC_HWSEQ_EN_8710B(__pTxDesc, __Value) \
+	SET_BITS_TO_LE_4BYTE(__pTxDesc+32, 15, 1, __Value)
+#define SET_TX_DESC_NEXTHEADPAGE_8710B(__pTxDesc, __Value) \
+	SET_BITS_TO_LE_4BYTE(__pTxDesc+32, 16, 8, __Value)
+#define SET_TX_DESC_TAILPAGE_8710B(__pTxDesc, __Value) \
+	SET_BITS_TO_LE_4BYTE(__pTxDesc+32, 24, 8, __Value)
+
+/* Dword 9 */
+#define SET_TX_DESC_PADDING_LEN_8710B(__pTxDesc, __Value) \
+	SET_BITS_TO_LE_4BYTE(__pTxDesc+36, 0, 11, __Value)
+#define SET_TX_DESC_SEQ_8710B(__pTxDesc, __Value) \
+	SET_BITS_TO_LE_4BYTE(__pTxDesc+36, 12, 12, __Value)
+#define SET_TX_DESC_FINAL_DATA_RATE_8710B(__pTxDesc, __Value) \
+	SET_BITS_TO_LE_4BYTE(__pTxDesc+36, 24, 8, __Value)
+
+
+#define SET_EARLYMODE_PKTNUM_8710B(__pAddr, __Value)					SET_BITS_TO_LE_4BYTE(__pAddr, 0, 4, __Value)
+#define SET_EARLYMODE_LEN0_8710B(__pAddr, __Value)					SET_BITS_TO_LE_4BYTE(__pAddr, 4, 15, __Value)
+#define SET_EARLYMODE_LEN1_1_8710B(__pAddr, __Value)					SET_BITS_TO_LE_4BYTE(__pAddr, 19, 13, __Value)
+#define SET_EARLYMODE_LEN1_2_8710B(__pAddr, __Value)					SET_BITS_TO_LE_4BYTE(__pAddr+4, 0, 2, __Value)
+#define SET_EARLYMODE_LEN2_8710B(__pAddr, __Value)					SET_BITS_TO_LE_4BYTE(__pAddr+4, 2, 15,	__Value)
+#define SET_EARLYMODE_LEN3_8710B(__pAddr, __Value)					SET_BITS_TO_LE_4BYTE(__pAddr+4, 17, 15, __Value)
+
+
+/*-----------------------------------------------------------------*/
+/*	RTL8710B TX BUFFER DESC                                      */
+/*-----------------------------------------------------------------*/
+#ifdef CONFIG_64BIT_DMA
+	#define SET_TXBUFFER_DESC_LEN_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc+((__Offset)*16), 0, 16, __Valeu)
+	#define SET_TXBUFFER_DESC_AMSDU_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc+((__Offset)*16), 31, 1, __Valeu)
+	#define SET_TXBUFFER_DESC_ADD_LOW_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc+((__Offset)*16)+4, 0, 32, __Valeu)
+	#define SET_TXBUFFER_DESC_ADD_HIGT_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc+((__Offset)*16)+8, 0, 32, __Valeu)
+#else
+	#define SET_TXBUFFER_DESC_LEN_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc+(__Offset*8), 0, 16, __Valeu)
+	#define SET_TXBUFFER_DESC_AMSDU_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc+(__Offset*8), 31, 1, __Valeu)
+	#define SET_TXBUFFER_DESC_ADD_LOW_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc+(__Offset*8)+4, 0, 32, __Valeu)
+	#define SET_TXBUFFER_DESC_ADD_HIGT_WITH_OFFSET(__pTxDesc, __Offset, __Valeu)	/* 64 BIT mode only */
+#endif
+/* ********************************************************* */
+
+/* 64 bits  -- 32 bits */
+/* =======     ======= */
+/* Dword 0     0 */
+#define SET_TX_BUFF_DESC_LEN_0_8710B(__pTxDesc, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc, 0, 14, __Valeu)
+#define SET_TX_BUFF_DESC_PSB_8710B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 16, 15, __Value)
+#define SET_TX_BUFF_DESC_OWN_8710B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 31, 1, __Value)
+
+/* Dword 1     1 */
+#define SET_TX_BUFF_DESC_ADDR_LOW_0_8710B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 0, 32, __Value)
+#define GET_TX_BUFF_DESC_ADDR_LOW_0_8710B(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc+4, 0, 32)
+/* Dword 2     NA */
+#define SET_TX_BUFF_DESC_ADDR_HIGH_0_8710B(__pTxDesc, __Value) SET_TXBUFFER_DESC_ADD_HIGT_WITH_OFFSET(__pTxDesc, 0, __Value)
+#ifdef CONFIG_64BIT_DMA
+	#define GET_TX_BUFF_DESC_ADDR_HIGH_0_8710B(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc+8, 0, 32)
+#else
+	#define GET_TX_BUFF_DESC_ADDR_HIGH_0_8710B(__pTxDesc) 0
+#endif
+/* Dword 3     NA */
+/* RESERVED 0 */
+/* Dword 4     2 */
+#define SET_TX_BUFF_DESC_LEN_1_8710B(__pTxDesc, __Value) SET_TXBUFFER_DESC_LEN_WITH_OFFSET(__pTxDesc, 1, __Value)
+#define SET_TX_BUFF_DESC_AMSDU_1_8710B(__pTxDesc, __Value) SET_TXBUFFER_DESC_AMSDU_WITH_OFFSET(__pTxDesc, 1, __Value)
+/* Dword 5     3 */
+#define SET_TX_BUFF_DESC_ADDR_LOW_1_8710B(__pTxDesc, __Value) SET_TXBUFFER_DESC_ADD_LOW_WITH_OFFSET(__pTxDesc, 1, __Value)
+/* Dword 6     NA */
+#define SET_TX_BUFF_DESC_ADDR_HIGH_1_8710B(__pTxDesc, __Value) SET_TXBUFFER_DESC_ADD_HIGT_WITH_OFFSET(__pTxDesc, 1, __Value)
+/* Dword 7     NA */
+/*RESERVED 0 */
+/* Dword 8     4 */
+#define SET_TX_BUFF_DESC_LEN_2_8710B(__pTxDesc, __Value) SET_TXBUFFER_DESC_LEN_WITH_OFFSET(__pTxDesc, 2, __Value)
+#define SET_TX_BUFF_DESC_AMSDU_2_8710B(__pTxDesc, __Value) SET_TXBUFFER_DESC_AMSDU_WITH_OFFSET(__pTxDesc, 2, __Value)
+/* Dword 9     5 */
+#define SET_TX_BUFF_DESC_ADDR_LOW_2_8710B(__pTxDesc, __Value) SET_TXBUFFER_DESC_ADD_LOW_WITH_OFFSET(__pTxDesc, 2, __Value)
+/* Dword 10    NA */
+#define SET_TX_BUFF_DESC_ADDR_HIGH_2_8710B(__pTxDesc, __Value) SET_TXBUFFER_DESC_ADD_HIGT_WITH_OFFSET(__pTxDesc, 2, __Value)
+/* Dword 11    NA */
+/*RESERVED 0 */
+/* Dword 12    6 */
+#define SET_TX_BUFF_DESC_LEN_3_8710B(__pTxDesc, __Value) SET_TXBUFFER_DESC_LEN_WITH_OFFSET(__pTxDesc, 3, __Value)
+#define SET_TX_BUFF_DESC_AMSDU_3_8710B(__pTxDesc, __Value) SET_TXBUFFER_DESC_AMSDU_WITH_OFFSET(__pTxDesc, 3, __Value)
+/* Dword 13    7 */
+#define SET_TX_BUFF_DESC_ADDR_LOW_3_8710B(__pTxDesc, __Value) SET_TXBUFFER_DESC_ADD_LOW_WITH_OFFSET(__pTxDesc, 3, __Value)
+/* Dword 14    NA */
+#define SET_TX_BUFF_DESC_ADDR_HIGH_3_8710B(__pTxDesc, __Value) SET_TXBUFFER_DESC_ADD_HIGT_WITH_OFFSET(__pTxDesc, 3, __Value)
+/* Dword 15    NA */
+/*RESERVED 0 */
+
+
+#endif
+/* -----------------------------------------------------------
+ *
+ *	Rate
+ *
+ * -----------------------------------------------------------
+ * CCK Rates, TxHT = 0 */
+#define DESC8710B_RATE1M				0x00
+#define DESC8710B_RATE2M				0x01
+#define DESC8710B_RATE5_5M				0x02
+#define DESC8710B_RATE11M				0x03
+
+/* OFDM Rates, TxHT = 0 */
+#define DESC8710B_RATE6M				0x04
+#define DESC8710B_RATE9M				0x05
+#define DESC8710B_RATE12M				0x06
+#define DESC8710B_RATE18M				0x07
+#define DESC8710B_RATE24M				0x08
+#define DESC8710B_RATE36M				0x09
+#define DESC8710B_RATE48M				0x0a
+#define DESC8710B_RATE54M				0x0b
+
+/* MCS Rates, TxHT = 1 */
+#define DESC8710B_RATEMCS0				0x0c
+#define DESC8710B_RATEMCS1				0x0d
+#define DESC8710B_RATEMCS2				0x0e
+#define DESC8710B_RATEMCS3				0x0f
+#define DESC8710B_RATEMCS4				0x10
+#define DESC8710B_RATEMCS5				0x11
+#define DESC8710B_RATEMCS6				0x12
+#define DESC8710B_RATEMCS7				0x13
+#define DESC8710B_RATEMCS8				0x14
+#define DESC8710B_RATEMCS9				0x15
+#define DESC8710B_RATEMCS10		0x16
+#define DESC8710B_RATEMCS11		0x17
+#define DESC8710B_RATEMCS12		0x18
+#define DESC8710B_RATEMCS13		0x19
+#define DESC8710B_RATEMCS14		0x1a
+#define DESC8710B_RATEMCS15		0x1b
+#define DESC8710B_RATEVHTSS1MCS0		0x2c
+#define DESC8710B_RATEVHTSS1MCS1		0x2d
+#define DESC8710B_RATEVHTSS1MCS2		0x2e
+#define DESC8710B_RATEVHTSS1MCS3		0x2f
+#define DESC8710B_RATEVHTSS1MCS4		0x30
+#define DESC8710B_RATEVHTSS1MCS5		0x31
+#define DESC8710B_RATEVHTSS1MCS6		0x32
+#define DESC8710B_RATEVHTSS1MCS7		0x33
+#define DESC8710B_RATEVHTSS1MCS8		0x34
+#define DESC8710B_RATEVHTSS1MCS9		0x35
+#define DESC8710B_RATEVHTSS2MCS0		0x36
+#define DESC8710B_RATEVHTSS2MCS1		0x37
+#define DESC8710B_RATEVHTSS2MCS2		0x38
+#define DESC8710B_RATEVHTSS2MCS3		0x39
+#define DESC8710B_RATEVHTSS2MCS4		0x3a
+#define DESC8710B_RATEVHTSS2MCS5		0x3b
+#define DESC8710B_RATEVHTSS2MCS6		0x3c
+#define DESC8710B_RATEVHTSS2MCS7		0x3d
+#define DESC8710B_RATEVHTSS2MCS8		0x3e
+#define DESC8710B_RATEVHTSS2MCS9		0x3f
+
+
+#define	RX_HAL_IS_CCK_RATE_8710B(pDesc)\
+	(GET_RX_STATUS_DESC_RX_RATE_8710B(pDesc) == DESC8710B_RATE1M || \
+	 GET_RX_STATUS_DESC_RX_RATE_8710B(pDesc) == DESC8710B_RATE2M || \
+	 GET_RX_STATUS_DESC_RX_RATE_8710B(pDesc) == DESC8710B_RATE5_5M || \
+	 GET_RX_STATUS_DESC_RX_RATE_8710B(pDesc) == DESC8710B_RATE11M)
+
+#ifdef CONFIG_TRX_BD_ARCH
+	struct tx_desc;
+#endif
+
+void rtl8710b_cal_txdesc_chksum(struct tx_desc *ptxdesc);
+void rtl8710b_update_txdesc(struct xmit_frame *pxmitframe, u8 *pmem);
+void rtl8710b_fill_txdesc_sectype(struct pkt_attrib *pattrib, struct tx_desc *ptxdesc);
+void rtl8710b_fill_txdesc_vcs(PADAPTER padapter, struct pkt_attrib *pattrib, struct tx_desc *ptxdesc);
+void rtl8710b_fill_txdesc_phy(PADAPTER padapter, struct pkt_attrib *pattrib, struct tx_desc *ptxdesc);
+void rtl8710b_fill_fake_txdesc(PADAPTER padapter, u8 *pDesc, u32 BufferLen, u8 IsPsPoll, u8 IsBTQosNull, u8 bDataFrame);
+
+#if defined(CONFIG_CONCURRENT_MODE)
+	void fill_txdesc_force_bmc_camid(struct pkt_attrib *pattrib, u8 *ptxdesc);
+#endif
+void fill_txdesc_bmc_tx_rate(struct pkt_attrib *pattrib, u8 *ptxdesc);
+
+#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
+	s32 rtl8710bs_init_xmit_priv(PADAPTER padapter);
+	void rtl8710bs_free_xmit_priv(PADAPTER padapter);
+	s32 rtl8710bs_hal_xmit(PADAPTER padapter, struct xmit_frame *pxmitframe);
+	s32 rtl8710bs_mgnt_xmit(PADAPTER padapter, struct xmit_frame *pmgntframe);
+	s32	rtl8710bs_hal_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe);
+	s32 rtl8710bs_xmit_buf_handler(PADAPTER padapter);
+	thread_return rtl8710bs_xmit_thread(thread_context context);
+	#define hal_xmit_handler rtl8710bs_xmit_buf_handler
+#endif
+
+#ifdef CONFIG_USB_HCI
+	s32 rtl8710bu_xmit_buf_handler(PADAPTER padapter);
+	#define hal_xmit_handler rtl8710bu_xmit_buf_handler
+	s32 rtl8710bu_init_xmit_priv(PADAPTER padapter);
+	void rtl8710bu_free_xmit_priv(PADAPTER padapter);
+	s32 rtl8710bu_hal_xmit(PADAPTER padapter, struct xmit_frame *pxmitframe);
+	s32 rtl8710bu_mgnt_xmit(PADAPTER padapter, struct xmit_frame *pmgntframe);
+	s32	 rtl8710bu_hal_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe);
+	void rtl8710bu_xmit_tasklet(void *priv);
+	s32 rtl8710bu_xmitframe_complete(_adapter *padapter, struct xmit_priv *pxmitpriv, struct xmit_buf *pxmitbuf);
+	void _dbg_dump_tx_info(_adapter	*padapter, int frame_tag, struct tx_desc *ptxdesc);
+#endif
+
+#ifdef CONFIG_PCI_HCI
+	s32 rtl8710be_init_xmit_priv(PADAPTER padapter);
+	void rtl8710be_free_xmit_priv(PADAPTER padapter);
+	struct xmit_buf *rtl8710be_dequeue_xmitbuf(struct rtw_tx_ring *ring);
+	void	rtl8710be_xmitframe_resume(_adapter *padapter);
+	s32 rtl8710be_hal_xmit(PADAPTER padapter, struct xmit_frame *pxmitframe);
+	s32 rtl8710be_mgnt_xmit(PADAPTER padapter, struct xmit_frame *pmgntframe);
+	s32	rtl8710be_hal_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe);
+	void rtl8710be_xmit_tasklet(void *priv);
+#endif
+
+u8	BWMapping_8710B(PADAPTER Adapter, struct pkt_attrib *pattrib);
+u8	SCMapping_8710B(PADAPTER Adapter, struct pkt_attrib	*pattrib);
+
+#endif
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/include/rtl8723b_cmd.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/rtl8723b_cmd.h
--- linux-5.6.3/3rdparty/rtl8821ce/include/rtl8723b_cmd.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/rtl8723b_cmd.h	2020-04-10 16:35:06.849661608 +0300
@@ -0,0 +1,205 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#ifndef __RTL8723B_CMD_H__
+#define __RTL8723B_CMD_H__
+
+/* ---------------------------------------------------------------------------------------------------------
+ * ----------------------------------    H2C CMD DEFINITION    ------------------------------------------------
+ * --------------------------------------------------------------------------------------------------------- */
+
+enum h2c_cmd_8723B {
+	/* Common Class: 000 */
+	H2C_8723B_RSVD_PAGE = 0x00,
+	H2C_8723B_MEDIA_STATUS_RPT = 0x01,
+	H2C_8723B_SCAN_ENABLE = 0x02,
+	H2C_8723B_KEEP_ALIVE = 0x03,
+	H2C_8723B_DISCON_DECISION = 0x04,
+	H2C_8723B_PSD_OFFLOAD = 0x05,
+	H2C_8723B_AP_OFFLOAD = 0x08,
+	H2C_8723B_BCN_RSVDPAGE = 0x09,
+	H2C_8723B_PROBERSP_RSVDPAGE = 0x0A,
+	H2C_8723B_FCS_RSVDPAGE = 0x10,
+	H2C_8723B_FCS_INFO = 0x11,
+	H2C_8723B_AP_WOW_GPIO_CTRL = 0x13,
+
+	/* PoweSave Class: 001 */
+	H2C_8723B_SET_PWR_MODE = 0x20,
+	H2C_8723B_PS_TUNING_PARA = 0x21,
+	H2C_8723B_PS_TUNING_PARA2 = 0x22,
+	H2C_8723B_P2P_LPS_PARAM = 0x23,
+	H2C_8723B_P2P_PS_OFFLOAD = 0x24,
+	H2C_8723B_PS_SCAN_ENABLE = 0x25,
+	H2C_8723B_SAP_PS_ = 0x26,
+	H2C_8723B_INACTIVE_PS_ = 0x27, /* Inactive_PS */
+	H2C_8723B_FWLPS_IN_IPS_ = 0x28,
+
+	/* Dynamic Mechanism Class: 010 */
+	H2C_8723B_MACID_CFG = 0x40,
+	H2C_8723B_TXBF = 0x41,
+	H2C_8723B_RSSI_SETTING = 0x42,
+	H2C_8723B_AP_REQ_TXRPT = 0x43,
+	H2C_8723B_INIT_RATE_COLLECT = 0x44,
+	H2C_8723B_RA_PARA_ADJUST = 0x46,
+
+	/* BT Class: 011 */
+	H2C_8723B_B_TYPE_TDMA = 0x60,
+	H2C_8723B_BT_INFO = 0x61,
+	H2C_8723B_FORCE_BT_TXPWR = 0x62,
+	H2C_8723B_BT_IGNORE_WLANACT = 0x63,
+	H2C_8723B_DAC_SWING_VALUE = 0x64,
+	H2C_8723B_ANT_SEL_RSV = 0x65,
+	H2C_8723B_WL_OPMODE = 0x66,
+	H2C_8723B_BT_MP_OPER = 0x67,
+	H2C_8723B_BT_CONTROL = 0x68,
+	H2C_8723B_BT_WIFI_CTRL = 0x69,
+	H2C_8723B_BT_FW_PATCH = 0x6A,
+	H2C_8723B_BT_WLAN_CALIBRATION = 0x6D,
+
+	/* WOWLAN Class: 100 */
+	H2C_8723B_WOWLAN = 0x80,
+	H2C_8723B_REMOTE_WAKE_CTRL = 0x81,
+	H2C_8723B_AOAC_GLOBAL_INFO = 0x82,
+	H2C_8723B_AOAC_RSVD_PAGE = 0x83,
+	H2C_8723B_AOAC_RSVD_PAGE2 = 0x84,
+	H2C_8723B_D0_SCAN_OFFLOAD_CTRL = 0x85,
+	H2C_8723B_D0_SCAN_OFFLOAD_INFO = 0x86,
+	H2C_8723B_CHNL_SWITCH_OFFLOAD = 0x87,
+	H2C_8723B_P2P_OFFLOAD_RSVD_PAGE = 0x8A,
+	H2C_8723B_P2P_OFFLOAD = 0x8B,
+
+	H2C_8723B_RESET_TSF = 0xC0,
+	H2C_8723B_MAXID,
+};
+
+/* ---------------------------------------------------------------------------------------------------------
+ * ----------------------------------    H2C CMD CONTENT    --------------------------------------------------
+ * ---------------------------------------------------------------------------------------------------------
+ * _RSVDPAGE_LOC_CMD_0x00 */
+#define SET_8723B_H2CCMD_RSVDPAGE_LOC_PROBE_RSP(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
+#define SET_8723B_H2CCMD_RSVDPAGE_LOC_PSPOLL(__pH2CCmd, __Value)				SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 8, __Value)
+#define SET_8723B_H2CCMD_RSVDPAGE_LOC_NULL_DATA(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value)
+#define SET_8723B_H2CCMD_RSVDPAGE_LOC_QOS_NULL_DATA(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 8, __Value)
+#define SET_8723B_H2CCMD_RSVDPAGE_LOC_BT_QOS_NULL_DATA(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 0, 8, __Value)
+
+/* _KEEP_ALIVE_CMD_0x03 */
+#define SET_8723B_H2CCMD_KEEPALIVE_PARM_ENABLE(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 1, __Value)
+#define SET_8723B_H2CCMD_KEEPALIVE_PARM_ADOPT(__pH2CCmd, __Value)				SET_BITS_TO_LE_1BYTE(__pH2CCmd, 1, 1, __Value)
+#define SET_8723B_H2CCMD_KEEPALIVE_PARM_PKT_TYPE(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE(__pH2CCmd, 2, 1, __Value)
+#define SET_8723B_H2CCMD_KEEPALIVE_PARM_CHECK_PERIOD(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 0, 8, __Value)
+
+/* _DISCONNECT_DECISION_CMD_0x04 */
+#define SET_8723B_H2CCMD_DISCONDECISION_PARM_ENABLE(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 1, __Value)
+#define SET_8723B_H2CCMD_DISCONDECISION_PARM_ADOPT(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE(__pH2CCmd, 1, 1, __Value)
+#define SET_8723B_H2CCMD_DISCONDECISION_PARM_CHECK_PERIOD(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 0, 8, __Value)
+#define SET_8723B_H2CCMD_DISCONDECISION_PARM_TRY_PKT_NUM(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 0, 8, __Value)
+
+/* _PWR_MOD_CMD_0x20 */
+#define SET_8723B_H2CCMD_PWRMODE_PARM_MODE(__pH2CCmd, __Value)				SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
+#define SET_8723B_H2CCMD_PWRMODE_PARM_RLBM(__pH2CCmd, __Value)				SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 4, __Value)
+#define SET_8723B_H2CCMD_PWRMODE_PARM_SMART_PS(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 4, 4, __Value)
+#define SET_8723B_H2CCMD_PWRMODE_PARM_BCN_PASS_TIME(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value)
+#define SET_8723B_H2CCMD_PWRMODE_PARM_ALL_QUEUE_UAPSD(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 8, __Value)
+#define SET_8723B_H2CCMD_PWRMODE_PARM_BCN_EARLY_C2H_RPT(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 2, 1, __Value)
+#define SET_8723B_H2CCMD_PWRMODE_PARM_PWR_STATE(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 0, 8, __Value)
+
+#define GET_8723B_H2CCMD_PWRMODE_PARM_MODE(__pH2CCmd)					LE_BITS_TO_1BYTE(__pH2CCmd, 0, 8)
+
+/* _PS_TUNE_PARAM_CMD_0x21 */
+#define SET_8723B_H2CCMD_PSTUNE_PARM_BCN_TO_LIMIT(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
+#define SET_8723B_H2CCMD_PSTUNE_PARM_DTIM_TIMEOUT(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 0, 8, __Value)
+#define SET_8723B_H2CCMD_PSTUNE_PARM_ADOPT(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 0, 1, __Value)
+#define SET_8723B_H2CCMD_PSTUNE_PARM_PS_TIMEOUT(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 1, 7, __Value)
+#define SET_8723B_H2CCMD_PSTUNE_PARM_DTIM_PERIOD(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE(__pH2CCmd+3, 0, 8, __Value)
+
+/* _MACID_CFG_CMD_0x40 */
+#define SET_8723B_H2CCMD_MACID_CFG_MACID(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
+#define SET_8723B_H2CCMD_MACID_CFG_RAID(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 0, 5, __Value)
+#define SET_8723B_H2CCMD_MACID_CFG_SGI_EN(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 7, 1, __Value)
+#define SET_8723B_H2CCMD_MACID_CFG_BW(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 0, 2, __Value)
+#define SET_8723B_H2CCMD_MACID_CFG_NO_UPDATE(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 3, 1, __Value)
+#define SET_8723B_H2CCMD_MACID_CFG_VHT_EN(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 4, 2, __Value)
+#define SET_8723B_H2CCMD_MACID_CFG_DISPT(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 6, 1, __Value)
+#define SET_8723B_H2CCMD_MACID_CFG_DISRA(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 7, 1, __Value)
+#define SET_8723B_H2CCMD_MACID_CFG_RATE_MASK0(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd+3, 0, 8, __Value)
+#define SET_8723B_H2CCMD_MACID_CFG_RATE_MASK1(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd+4, 0, 8, __Value)
+#define SET_8723B_H2CCMD_MACID_CFG_RATE_MASK2(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd+5, 0, 8, __Value)
+#define SET_8723B_H2CCMD_MACID_CFG_RATE_MASK3(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd+6, 0, 8, __Value)
+
+/* _RSSI_SETTING_CMD_0x42 */
+#define SET_8723B_H2CCMD_RSSI_SETTING_MACID(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
+#define SET_8723B_H2CCMD_RSSI_SETTING_RSSI(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 0, 7, __Value)
+#define SET_8723B_H2CCMD_RSSI_SETTING_ULDL_STATE(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd+3, 0, 8, __Value)
+
+/* _AP_REQ_TXRPT_CMD_0x43 */
+#define SET_8723B_H2CCMD_APREQRPT_PARM_MACID1(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
+#define SET_8723B_H2CCMD_APREQRPT_PARM_MACID2(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 0, 8, __Value)
+
+/* _FORCE_BT_TXPWR_CMD_0x62 */
+#define SET_8723B_H2CCMD_BT_PWR_IDX(__pH2CCmd, __Value)							SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
+
+/* _FORCE_BT_MP_OPER_CMD_0x67 */
+#define SET_8723B_H2CCMD_BT_MPOPER_VER(__pH2CCmd, __Value)							SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 4, __Value)
+#define SET_8723B_H2CCMD_BT_MPOPER_REQNUM(__pH2CCmd, __Value)							SET_BITS_TO_LE_1BYTE(__pH2CCmd, 4, 4, __Value)
+#define SET_8723B_H2CCMD_BT_MPOPER_IDX(__pH2CCmd, __Value)							SET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 0, 8, __Value)
+#define SET_8723B_H2CCMD_BT_MPOPER_PARAM1(__pH2CCmd, __Value)							SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 0, 8, __Value)
+#define SET_8723B_H2CCMD_BT_MPOPER_PARAM2(__pH2CCmd, __Value)							SET_BITS_TO_LE_1BYTE(__pH2CCmd+3, 0, 8, __Value)
+#define SET_8723B_H2CCMD_BT_MPOPER_PARAM3(__pH2CCmd, __Value)							SET_BITS_TO_LE_1BYTE(__pH2CCmd+4, 0, 8, __Value)
+
+/* _BT_FW_PATCH_0x6A */
+#define SET_8723B_H2CCMD_BT_FW_PATCH_SIZE(__pH2CCmd, __Value)					SET_BITS_TO_LE_2BYTE((pu1Byte)(__pH2CCmd), 0, 16, __Value)
+#define SET_8723B_H2CCMD_BT_FW_PATCH_ADDR0(__pH2CCmd, __Value)					SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value)
+#define SET_8723B_H2CCMD_BT_FW_PATCH_ADDR1(__pH2CCmd, __Value)					SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 8, __Value)
+#define SET_8723B_H2CCMD_BT_FW_PATCH_ADDR2(__pH2CCmd, __Value)					SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 0, 8, __Value)
+#define SET_8723B_H2CCMD_BT_FW_PATCH_ADDR3(__pH2CCmd, __Value)					SET_BITS_TO_LE_1BYTE((__pH2CCmd)+5, 0, 8, __Value)
+
+/* ---------------------------------------------------------------------------------------------------------
+ * -------------------------------------------    Structure    --------------------------------------------------
+ * --------------------------------------------------------------------------------------------------------- */
+
+
+/* ---------------------------------------------------------------------------------------------------------
+ * ----------------------------------    Function Statement     --------------------------------------------------
+ * --------------------------------------------------------------------------------------------------------- */
+
+/* host message to firmware cmd */
+void rtl8723b_set_FwPwrMode_cmd(PADAPTER padapter, u8 Mode);
+void rtl8723b_set_FwJoinBssRpt_cmd(PADAPTER padapter, u8 mstatus);
+void rtl8723b_fw_try_ap_cmd(PADAPTER padapter, u32 need_ack);
+/* s32 rtl8723b_set_lowpwr_lps_cmd(PADAPTER padapter, u8 enable); */
+void rtl8723b_set_FwPsTuneParam_cmd(PADAPTER padapter);
+void rtl8723b_set_FwBtMpOper_cmd(PADAPTER padapter, u8 idx, u8 ver, u8 reqnum, u8 *param);
+void rtl8723b_download_rsvd_page(PADAPTER padapter, u8 mstatus);
+#ifdef CONFIG_BT_COEXIST
+	void rtl8723b_download_BTCoex_AP_mode_rsvd_page(PADAPTER padapter);
+#endif /* CONFIG_BT_COEXIST */
+#ifdef CONFIG_P2P
+	void rtl8723b_set_p2p_ps_offload_cmd(PADAPTER padapter, u8 p2p_ps_state);
+#endif /* CONFIG_P2P */
+
+#ifdef CONFIG_TDLS
+	#ifdef CONFIG_TDLS_CH_SW
+		void rtl8723b_set_BcnEarly_C2H_Rpt_cmd(PADAPTER padapter, u8 enable);
+	#endif
+#endif
+
+#ifdef CONFIG_P2P_WOWLAN
+	void rtl8723b_set_p2p_wowlan_offload_cmd(PADAPTER padapter);
+#endif
+
+void rtl8723b_set_FwPwrModeInIPS_cmd(PADAPTER padapter, u8 cmd_param);
+
+s32 FillH2CCmd8723B(PADAPTER padapter, u8 ElementID, u32 CmdLen, u8 *pCmdBuffer);
+u8 GetTxBufferRsvdPageNum8723B(_adapter *padapter, bool wowlan);
+#endif
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/include/rtl8723b_dm.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/rtl8723b_dm.h
--- linux-5.6.3/3rdparty/rtl8821ce/include/rtl8723b_dm.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/rtl8723b_dm.h	2020-04-10 16:35:06.849661608 +0300
@@ -0,0 +1,38 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#ifndef __RTL8723B_DM_H__
+#define __RTL8723B_DM_H__
+/* ************************************************************
+ * Description:
+ *
+ * This file is for 8723B dynamic mechanism only
+ *
+ *
+ * ************************************************************ */
+
+/* ************************************************************
+ * structure and define
+ * ************************************************************ */
+
+/* ************************************************************
+ * function prototype
+ * ************************************************************ */
+
+void rtl8723b_init_dm_priv(PADAPTER padapter);
+void rtl8723b_deinit_dm_priv(PADAPTER padapter);
+
+void rtl8723b_InitHalDm(PADAPTER padapter);
+void rtl8723b_HalDmWatchDog(PADAPTER padapter);
+#endif
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/include/rtl8723b_hal.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/rtl8723b_hal.h
--- linux-5.6.3/3rdparty/rtl8821ce/include/rtl8723b_hal.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/rtl8723b_hal.h	2020-04-10 16:35:06.849661608 +0300
@@ -0,0 +1,274 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#ifndef __RTL8723B_HAL_H__
+#define __RTL8723B_HAL_H__
+
+#include "hal_data.h"
+
+#include "rtl8723b_spec.h"
+#include "rtl8723b_rf.h"
+#include "rtl8723b_dm.h"
+#include "rtl8723b_recv.h"
+#include "rtl8723b_xmit.h"
+#include "rtl8723b_cmd.h"
+#include "rtl8723b_led.h"
+#include "Hal8723BPwrSeq.h"
+#include "Hal8723BPhyReg.h"
+#include "Hal8723BPhyCfg.h"
+#ifdef DBG_CONFIG_ERROR_DETECT
+	#include "rtl8723b_sreset.h"
+#endif
+
+#define FW_8723B_SIZE			0x8000
+#define FW_8723B_START_ADDRESS	0x1000
+#define FW_8723B_END_ADDRESS		0x1FFF /* 0x5FFF */
+
+#define IS_FW_HEADER_EXIST_8723B(_pFwHdr)	((le16_to_cpu(_pFwHdr->Signature) & 0xFFF0) == 0x5300)
+
+typedef struct _RT_FIRMWARE {
+	FIRMWARE_SOURCE	eFWSource;
+#ifdef CONFIG_EMBEDDED_FWIMG
+	u8			*szFwBuffer;
+#else
+	u8			szFwBuffer[FW_8723B_SIZE];
+#endif
+	u32			ulFwLength;
+} RT_FIRMWARE_8723B, *PRT_FIRMWARE_8723B;
+
+/*
+ * This structure must be cared byte-ordering
+ *
+ * Added by tynli. 2009.12.04. */
+typedef struct _RT_8723B_FIRMWARE_HDR {
+	/* 8-byte alinment required */
+
+	/* --- LONG WORD 0 ---- */
+	u16		Signature;	/* 92C0: test chip; 92C, 88C0: test chip; 88C1: MP A-cut; 92C1: MP A-cut */
+	u8		Category;	/* AP/NIC and USB/PCI */
+	u8		Function;	/* Reserved for different FW function indcation, for further use when driver needs to download different FW in different conditions */
+	u16		Version;		/* FW Version */
+	u16		Subversion;	/* FW Subversion, default 0x00 */
+
+	/* --- LONG WORD 1 ---- */
+	u8		Month;	/* Release time Month field */
+	u8		Date;	/* Release time Date field */
+	u8		Hour;	/* Release time Hour field */
+	u8		Minute;	/* Release time Minute field */
+	u16		RamCodeSize;	/* The size of RAM code */
+	u16		Rsvd2;
+
+	/* --- LONG WORD 2 ---- */
+	u32		SvnIdx;	/* The SVN entry index */
+	u32		Rsvd3;
+
+	/* --- LONG WORD 3 ---- */
+	u32		Rsvd4;
+	u32		Rsvd5;
+} RT_8723B_FIRMWARE_HDR, *PRT_8723B_FIRMWARE_HDR;
+
+#define DRIVER_EARLY_INT_TIME_8723B		0x05
+#define BCN_DMA_ATIME_INT_TIME_8723B		0x02
+
+/* for 8723B
+ * TX 32K, RX 16K, Page size 128B for TX, 8B for RX */
+#define PAGE_SIZE_TX_8723B			128
+#define PAGE_SIZE_RX_8723B			8
+
+#define TX_DMA_SIZE_8723B			0x8000	/* 32K(TX) */
+#define RX_DMA_SIZE_8723B			0x4000	/* 16K(RX) */
+
+#ifdef CONFIG_WOWLAN
+	#define RESV_FMWF	(WKFMCAM_SIZE * MAX_WKFM_CAM_NUM) /* 16 entries, for each is 24 bytes*/
+#else
+	#define RESV_FMWF	0
+#endif
+
+#ifdef CONFIG_FW_C2H_DEBUG
+	#define RX_DMA_RESERVED_SIZE_8723B	0x100	/* 256B, reserved for c2h debug message */
+#else
+	#define RX_DMA_RESERVED_SIZE_8723B	0x80	/* 128B, reserved for tx report */
+#endif
+#define RX_DMA_BOUNDARY_8723B		(RX_DMA_SIZE_8723B - RX_DMA_RESERVED_SIZE_8723B - 1)
+
+
+/* Note: We will divide number of page equally for each queue other than public queue! */
+
+/* For General Reserved Page Number(Beacon Queue is reserved page)
+ * Beacon:MAX_BEACON_LEN/PAGE_SIZE_TX_8723B
+ * PS-Poll:1, Null Data:1,Qos Null Data:1,BT Qos Null Data:1,CTS-2-SELF,LTE QoS Null*/
+#define BCNQ_PAGE_NUM_8723B		(MAX_BEACON_LEN / PAGE_SIZE_TX_8723B + 6) /*0x08*/
+
+
+/* For WoWLan , more reserved page
+ * ARP Rsp:1, RWC:1, GTK Info:1,GTK RSP:2,GTK EXT MEM:2, AOAC rpt: 1,PNO: 6
+ * NS offload: 2 NDP info: 1
+ */
+#ifdef CONFIG_WOWLAN
+	#define WOWLAN_PAGE_NUM_8723B	0x0b
+#else
+	#define WOWLAN_PAGE_NUM_8723B	0x00
+#endif
+
+#ifdef CONFIG_PNO_SUPPORT
+	#undef WOWLAN_PAGE_NUM_8723B
+	#define WOWLAN_PAGE_NUM_8723B	0x15
+#endif
+
+#ifdef CONFIG_AP_WOWLAN
+	#define AP_WOWLAN_PAGE_NUM_8723B	0x02
+#endif
+
+#define TX_TOTAL_PAGE_NUMBER_8723B	(0xFF - BCNQ_PAGE_NUM_8723B - WOWLAN_PAGE_NUM_8723B)
+#define TX_PAGE_BOUNDARY_8723B		(TX_TOTAL_PAGE_NUMBER_8723B + 1)
+
+#define WMM_NORMAL_TX_TOTAL_PAGE_NUMBER_8723B	TX_TOTAL_PAGE_NUMBER_8723B
+#define WMM_NORMAL_TX_PAGE_BOUNDARY_8723B		(WMM_NORMAL_TX_TOTAL_PAGE_NUMBER_8723B + 1)
+
+/* For Normal Chip Setting
+ * (HPQ + LPQ + NPQ + PUBQ) shall be TX_TOTAL_PAGE_NUMBER_8723B */
+#define NORMAL_PAGE_NUM_HPQ_8723B		0x0C
+#define NORMAL_PAGE_NUM_LPQ_8723B		0x02
+#define NORMAL_PAGE_NUM_NPQ_8723B		0x02
+#define NORMAL_PAGE_NUM_EPQ_8723B		0x04
+
+/* Note: For Normal Chip Setting, modify later */
+#define WMM_NORMAL_PAGE_NUM_HPQ_8723B		0x30
+#define WMM_NORMAL_PAGE_NUM_LPQ_8723B		0x20
+#define WMM_NORMAL_PAGE_NUM_NPQ_8723B		0x20
+#define WMM_NORMAL_PAGE_NUM_EPQ_8723B		0x00
+
+
+#include "HalVerDef.h"
+#include "hal_com.h"
+
+#define EFUSE_OOB_PROTECT_BYTES		15
+
+#define HAL_EFUSE_MEMORY
+
+#define HWSET_MAX_SIZE_8723B			512
+#define EFUSE_REAL_CONTENT_LEN_8723B		512
+#define EFUSE_MAP_LEN_8723B				512
+#define EFUSE_MAX_SECTION_8723B			64
+
+#define EFUSE_IC_ID_OFFSET			506	/* For some inferiority IC purpose. added by Roger, 2009.09.02. */
+#define AVAILABLE_EFUSE_ADDR(addr)	(addr < EFUSE_REAL_CONTENT_LEN_8723B)
+
+#define EFUSE_ACCESS_ON			0x69	/* For RTL8723 only. */
+#define EFUSE_ACCESS_OFF			0x00	/* For RTL8723 only. */
+
+/* ********************************************************
+ *			EFUSE for BT definition
+ * ******************************************************** */
+#define EFUSE_BT_REAL_BANK_CONTENT_LEN	512
+#define EFUSE_BT_REAL_CONTENT_LEN		1536	/* 512*3 */
+#define EFUSE_BT_MAP_LEN				1024	/* 1k bytes */
+#define EFUSE_BT_MAX_SECTION			128		/* 1024/8 */
+
+#define EFUSE_PROTECT_BYTES_BANK		16
+
+typedef enum tag_Package_Definition {
+	PACKAGE_DEFAULT,
+	PACKAGE_QFN68,
+	PACKAGE_TFBGA90,
+	PACKAGE_TFBGA80,
+	PACKAGE_TFBGA79
+} PACKAGE_TYPE_E;
+
+#define INCLUDE_MULTI_FUNC_BT(_Adapter)		(GET_HAL_DATA(_Adapter)->MultiFunc & RT_MULTI_FUNC_BT)
+#define INCLUDE_MULTI_FUNC_GPS(_Adapter)	(GET_HAL_DATA(_Adapter)->MultiFunc & RT_MULTI_FUNC_GPS)
+
+/* rtl8723a_hal_init.c */
+s32 rtl8723b_FirmwareDownload(PADAPTER padapter, BOOLEAN  bUsedWoWLANFw);
+void rtl8723b_FirmwareSelfReset(PADAPTER padapter);
+void rtl8723b_InitializeFirmwareVars(PADAPTER padapter);
+
+void rtl8723b_InitAntenna_Selection(PADAPTER padapter);
+void rtl8723b_DeinitAntenna_Selection(PADAPTER padapter);
+void rtl8723b_CheckAntenna_Selection(PADAPTER padapter);
+void rtl8723b_init_default_value(PADAPTER padapter);
+
+s32 rtl8723b_InitLLTTable(PADAPTER padapter);
+
+s32 CardDisableHWSM(PADAPTER padapter, u8 resetMCU);
+s32 CardDisableWithoutHWSM(PADAPTER padapter);
+
+/* EFuse */
+u8 GetEEPROMSize8723B(PADAPTER padapter);
+void Hal_InitPGData(PADAPTER padapter, u8 *PROMContent);
+void Hal_EfuseParseIDCode(PADAPTER padapter, u8 *hwinfo);
+void Hal_EfuseParseTxPowerInfo_8723B(PADAPTER padapter, u8 *PROMContent, BOOLEAN AutoLoadFail);
+void Hal_EfuseParseBTCoexistInfo_8723B(PADAPTER padapter, u8 *hwinfo, BOOLEAN AutoLoadFail);
+void Hal_EfuseParseEEPROMVer_8723B(PADAPTER padapter, u8 *hwinfo, BOOLEAN AutoLoadFail);
+void Hal_EfuseParseChnlPlan_8723B(PADAPTER padapter, u8 *hwinfo, BOOLEAN AutoLoadFail);
+void Hal_EfuseParseCustomerID_8723B(PADAPTER padapter, u8 *hwinfo, BOOLEAN AutoLoadFail);
+void Hal_EfuseParseAntennaDiversity_8723B(PADAPTER padapter, u8 *hwinfo, BOOLEAN AutoLoadFail);
+void Hal_EfuseParseXtal_8723B(PADAPTER pAdapter, u8 *hwinfo, u8 AutoLoadFail);
+void Hal_EfuseParseThermalMeter_8723B(PADAPTER padapter, u8 *hwinfo, u8 AutoLoadFail);
+VOID Hal_EfuseParsePackageType_8723B(PADAPTER pAdapter, u8 *hwinfo, BOOLEAN AutoLoadFail);
+VOID Hal_EfuseParseVoltage_8723B(PADAPTER pAdapter, u8 *hwinfo, BOOLEAN	AutoLoadFail);
+VOID Hal_EfuseParseBoardType_8723B(PADAPTER Adapter,	u8	*PROMContent, BOOLEAN AutoloadFail);
+
+void rtl8723b_set_hal_ops(struct hal_ops *pHalFunc);
+void init_hal_spec_8723b(_adapter *adapter);
+u8 SetHwReg8723B(PADAPTER padapter, u8 variable, u8 *val);
+void GetHwReg8723B(PADAPTER padapter, u8 variable, u8 *val);
+u8 SetHalDefVar8723B(PADAPTER padapter, HAL_DEF_VARIABLE variable, void *pval);
+u8 GetHalDefVar8723B(PADAPTER padapter, HAL_DEF_VARIABLE variable, void *pval);
+
+/* register */
+void rtl8723b_InitBeaconParameters(PADAPTER padapter);
+void rtl8723b_InitBeaconMaxError(PADAPTER padapter, u8 InfraMode);
+void	_InitBurstPktLen_8723BS(PADAPTER Adapter);
+void _8051Reset8723(PADAPTER padapter);
+#if defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN)
+	void Hal_DetectWoWMode(PADAPTER pAdapter);
+#endif /* CONFIG_WOWLAN */
+
+void rtl8723b_start_thread(_adapter *padapter);
+void rtl8723b_stop_thread(_adapter *padapter);
+
+#if defined(CONFIG_CHECK_BT_HANG) && defined(CONFIG_BT_COEXIST)
+	void rtl8723bs_init_checkbthang_workqueue(_adapter *adapter);
+	void rtl8723bs_free_checkbthang_workqueue(_adapter *adapter);
+	void rtl8723bs_cancle_checkbthang_workqueue(_adapter *adapter);
+	void rtl8723bs_hal_check_bt_hang(_adapter *adapter);
+#endif
+
+#ifdef CONFIG_GPIO_WAKEUP
+	void HalSetOutPutGPIO(PADAPTER padapter, u8 index, u8 OutPutValue);
+#endif
+#ifdef CONFIG_MP_INCLUDED
+int FirmwareDownloadBT(IN PADAPTER Adapter, PRT_MP_FIRMWARE pFirmware);
+#endif
+void CCX_FwC2HTxRpt_8723b(PADAPTER padapter, u8 *pdata, u8 len);
+
+u8 MRateToHwRate8723B(u8  rate);
+u8 HwRateToMRate8723B(u8	 rate);
+
+#ifdef CONFIG_RF_POWER_TRIM
+	void Hal_ReadRFGainOffset(PADAPTER pAdapter, u8 *hwinfo, BOOLEAN AutoLoadFail);
+#endif /*CONFIG_RF_POWER_TRIM*/
+
+#ifdef CONFIG_PCI_HCI
+	BOOLEAN	InterruptRecognized8723BE(PADAPTER Adapter);
+	VOID	UpdateInterruptMask8723BE(PADAPTER Adapter, u32 AddMSR, u32 AddMSR1, u32 RemoveMSR, u32 RemoveMSR1);
+#endif
+
+#ifdef CONFIG_GPIO_API
+int rtl8723b_GpioFuncCheck(PADAPTER adapter, u8 gpio_num);
+VOID rtl8723b_GpioMultiFuncReset(PADAPTER adapter, u8 gpio_num);
+#endif
+
+#endif
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/include/rtl8723b_led.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/rtl8723b_led.h
--- linux-5.6.3/3rdparty/rtl8821ce/include/rtl8723b_led.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/rtl8723b_led.h	2020-04-10 16:35:06.849661608 +0300
@@ -0,0 +1,44 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#ifndef __RTL8723B_LED_H__
+#define __RTL8723B_LED_H__
+
+#include <drv_conf.h>
+#include <osdep_service.h>
+#include <drv_types.h>
+
+#ifdef CONFIG_RTW_SW_LED
+/* ********************************************************************************
+ * Interface to manipulate LED objects.
+ * ******************************************************************************** */
+#ifdef CONFIG_USB_HCI
+	void rtl8723bu_InitSwLeds(PADAPTER padapter);
+	void rtl8723bu_DeInitSwLeds(PADAPTER padapter);
+#endif
+#ifdef CONFIG_SDIO_HCI
+	void rtl8723bs_InitSwLeds(PADAPTER padapter);
+	void rtl8723bs_DeInitSwLeds(PADAPTER padapter);
+#endif
+#ifdef CONFIG_GSPI_HCI
+	void rtl8723bs_InitSwLeds(PADAPTER padapter);
+	void rtl8723bs_DeInitSwLeds(PADAPTER padapter);
+#endif
+#ifdef CONFIG_PCI_HCI
+	void rtl8723be_InitSwLeds(PADAPTER padapter);
+	void rtl8723be_DeInitSwLeds(PADAPTER padapter);
+#endif
+
+#endif
+#endif/*CONFIG_RTW_SW_LED*/
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/include/rtl8723b_recv.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/rtl8723b_recv.h
--- linux-5.6.3/3rdparty/rtl8821ce/include/rtl8723b_recv.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/rtl8723b_recv.h	2020-04-10 16:35:06.849661608 +0300
@@ -0,0 +1,86 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#ifndef __RTL8723B_RECV_H__
+#define __RTL8723B_RECV_H__
+
+#define RECV_BLK_SZ 512
+#define RECV_BLK_CNT 16
+#define RECV_BLK_TH RECV_BLK_CNT
+
+#if defined(CONFIG_USB_HCI)
+
+	#ifndef MAX_RECVBUF_SZ
+		#ifdef PLATFORM_OS_CE
+			#define MAX_RECVBUF_SZ (8192+1024) /* 8K+1k */
+		#else
+			#ifndef CONFIG_MINIMAL_MEMORY_USAGE
+				/* #define MAX_RECVBUF_SZ (32768) */ /* 32k */
+				/* #define MAX_RECVBUF_SZ (16384) */ /* 16K */
+				/* #define MAX_RECVBUF_SZ (10240) */ /* 10K */
+				#ifdef CONFIG_PLATFORM_MSTAR
+					#define MAX_RECVBUF_SZ (8192) /* 8K */
+				#else
+					#define MAX_RECVBUF_SZ (15360) /* 15k < 16k */
+				#endif
+				/* #define MAX_RECVBUF_SZ (8192+1024) */ /* 8K+1k */
+			#else
+				#define MAX_RECVBUF_SZ (4000) /* about 4K */
+			#endif
+		#endif
+	#endif /* !MAX_RECVBUF_SZ */
+
+#elif defined(CONFIG_PCI_HCI)
+	/* #ifndef CONFIG_MINIMAL_MEMORY_USAGE */
+	/*	#define MAX_RECVBUF_SZ (9100) */
+	/* #else */
+	#define MAX_RECVBUF_SZ (4000) /* about 4K
+	* #endif */
+
+
+#elif defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
+
+	#define MAX_RECVBUF_SZ  (RX_DMA_SIZE_8723B - RX_DMA_RESERVED_SIZE_8723B)
+
+#endif
+
+/* Rx smooth factor */
+#define	Rx_Smooth_Factor (20)
+
+#ifdef CONFIG_SDIO_HCI
+	#ifndef CONFIG_SDIO_RX_COPY
+		#undef MAX_RECVBUF_SZ
+		#define MAX_RECVBUF_SZ	(RX_DMA_SIZE_8723B - RX_DMA_RESERVED_SIZE_8723B)
+	#endif /* !CONFIG_SDIO_RX_COPY */
+#endif /* CONFIG_SDIO_HCI */
+
+#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
+	s32 rtl8723bs_init_recv_priv(PADAPTER padapter);
+	void rtl8723bs_free_recv_priv(PADAPTER padapter);
+#endif
+
+#ifdef CONFIG_USB_HCI
+	int rtl8723bu_init_recv_priv(_adapter *padapter);
+	void rtl8723bu_free_recv_priv(_adapter *padapter);
+	void rtl8723bu_init_recvbuf(_adapter *padapter, struct recv_buf *precvbuf);
+#endif
+
+#ifdef CONFIG_PCI_HCI
+	s32 rtl8723be_init_recv_priv(PADAPTER padapter);
+	void rtl8723be_free_recv_priv(PADAPTER padapter);
+#endif
+
+void rtl8723b_query_rx_desc_status(union recv_frame *precvframe, u8 *pdesc);
+
+#endif /* __RTL8723B_RECV_H__ */
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/include/rtl8723b_rf.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/rtl8723b_rf.h
--- linux-5.6.3/3rdparty/rtl8821ce/include/rtl8723b_rf.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/rtl8723b_rf.h	2020-04-10 16:35:06.849661608 +0300
@@ -0,0 +1,25 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#ifndef __RTL8723B_RF_H__
+#define __RTL8723B_RF_H__
+
+int	PHY_RF6052_Config8723B(IN	PADAPTER		Adapter);
+
+VOID
+PHY_RF6052SetBandwidth8723B(
+	IN	PADAPTER				Adapter,
+	IN	enum channel_width		Bandwidth);
+
+#endif
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/include/rtl8723b_spec.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/rtl8723b_spec.h
--- linux-5.6.3/3rdparty/rtl8821ce/include/rtl8723b_spec.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/rtl8723b_spec.h	2020-04-10 16:35:06.849661608 +0300
@@ -0,0 +1,280 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#ifndef __RTL8723B_SPEC_H__
+#define __RTL8723B_SPEC_H__
+
+#include <drv_conf.h>
+
+
+#define HAL_NAV_UPPER_UNIT_8723B		128		/* micro-second */
+
+/* -----------------------------------------------------
+ *
+ *	0x0000h ~ 0x00FFh	System Configuration
+ *
+ * ----------------------------------------------------- */
+#define REG_RSV_CTRL_8723B				0x001C	/* 3 Byte */
+#define REG_BT_WIFI_ANTENNA_SWITCH_8723B	0x0038
+#define REG_HSISR_8723B					0x005c
+#define REG_PAD_CTRL1_8723B		0x0064
+#define REG_AFE_CTRL_4_8723B		0x0078
+#define REG_HMEBOX_DBG_0_8723B	0x0088
+#define REG_HMEBOX_DBG_1_8723B	0x008A
+#define REG_HMEBOX_DBG_2_8723B	0x008C
+#define REG_HMEBOX_DBG_3_8723B	0x008E
+#define REG_HIMR0_8723B					0x00B0
+#define REG_HISR0_8723B					0x00B4
+#define REG_HIMR1_8723B					0x00B8
+#define REG_HISR1_8723B					0x00BC
+#define REG_PMC_DBG_CTRL2_8723B			0x00CC
+
+/* -----------------------------------------------------
+ *
+ *	0x0100h ~ 0x01FFh	MACTOP General Configuration
+ *
+ * ----------------------------------------------------- */
+#define REG_C2HEVT_CMD_ID_8723B	0x01A0
+#define REG_C2HEVT_CMD_LEN_8723B	0x01AE
+#define REG_WOWLAN_WAKE_REASON 0x01C7
+#define REG_WOWLAN_GTK_DBG1	0x630
+#define REG_WOWLAN_GTK_DBG2	0x634
+
+#define REG_HMEBOX_EXT0_8723B			0x01F0
+#define REG_HMEBOX_EXT1_8723B			0x01F4
+#define REG_HMEBOX_EXT2_8723B			0x01F8
+#define REG_HMEBOX_EXT3_8723B			0x01FC
+
+/* -----------------------------------------------------
+ *
+ *	0x0200h ~ 0x027Fh	TXDMA Configuration
+ *
+ * ----------------------------------------------------- */
+
+/* -----------------------------------------------------
+ *
+ *	0x0280h ~ 0x02FFh	RXDMA Configuration
+ *
+ * ----------------------------------------------------- */
+#define REG_RXDMA_CONTROL_8723B		0x0286 /* Control the RX DMA. */
+#define REG_RXDMA_MODE_CTRL_8723B		0x0290
+
+/* -----------------------------------------------------
+ *
+ *	0x0300h ~ 0x03FFh	PCIe
+ *
+ * ----------------------------------------------------- */
+#define	REG_PCIE_CTRL_REG_8723B		0x0300
+#define	REG_INT_MIG_8723B				0x0304	/* Interrupt Migration */
+#define	REG_BCNQ_DESA_8723B			0x0308	/* TX Beacon Descriptor Address */
+#define	REG_HQ_DESA_8723B				0x0310	/* TX High Queue Descriptor Address */
+#define	REG_MGQ_DESA_8723B			0x0318	/* TX Manage Queue Descriptor Address */
+#define	REG_VOQ_DESA_8723B			0x0320	/* TX VO Queue Descriptor Address */
+#define	REG_VIQ_DESA_8723B				0x0328	/* TX VI Queue Descriptor Address */
+#define	REG_BEQ_DESA_8723B			0x0330	/* TX BE Queue Descriptor Address */
+#define	REG_BKQ_DESA_8723B			0x0338	/* TX BK Queue Descriptor Address */
+#define	REG_RX_DESA_8723B				0x0340	/* RX Queue	Descriptor Address */
+#define	REG_DBI_WDATA_8723B			0x0348	/* DBI Write Data */
+#define	REG_DBI_RDATA_8723B			0x034C	/* DBI Read Data */
+#define	REG_DBI_ADDR_8723B				0x0350	/* DBI Address */
+#define	REG_DBI_FLAG_8723B				0x0352	/* DBI Read/Write Flag */
+#define	REG_MDIO_WDATA_8723B		0x0354	/* MDIO for Write PCIE PHY */
+#define	REG_MDIO_RDATA_8723B			0x0356	/* MDIO for Reads PCIE PHY */
+#define	REG_MDIO_CTL_8723B			0x0358	/* MDIO for Control */
+#define	REG_DBG_SEL_8723B				0x0360	/* Debug Selection Register */
+#define	REG_PCIE_HRPWM_8723B			0x0361	/* PCIe RPWM */
+#define	REG_PCIE_HCPWM_8723B			0x0363	/* PCIe CPWM */
+#define	REG_PCIE_MULTIFET_CTRL_8723B	0x036A	/* PCIE Multi-Fethc Control */
+
+/* -----------------------------------------------------
+ *
+ *	0x0400h ~ 0x047Fh	Protocol Configuration
+ *
+ * ----------------------------------------------------- */
+#define REG_TXPKTBUF_BCNQ_BDNY_8723B	0x0424
+#define REG_TXPKTBUF_MGQ_BDNY_8723B	0x0425
+#define REG_TXPKTBUF_WMAC_LBK_BF_HD_8723B	0x045D
+#ifdef CONFIG_WOWLAN
+	#define REG_TXPKTBUF_IV_LOW             0x0484
+	#define REG_TXPKTBUF_IV_HIGH            0x0488
+#endif
+#define REG_AMPDU_BURST_MODE_8723B	0x04BC
+
+/* -----------------------------------------------------
+ *
+ *	0x0500h ~ 0x05FFh	EDCA Configuration
+ *
+ * ----------------------------------------------------- */
+#define REG_SECONDARY_CCA_CTRL_8723B	0x0577
+
+/* -----------------------------------------------------
+ *
+ *	0x0600h ~ 0x07FFh	WMAC Configuration
+ *
+ * ----------------------------------------------------- */
+
+
+/* ************************************************************
+ * SDIO Bus Specification
+ * ************************************************************ */
+
+/* -----------------------------------------------------
+ * SDIO CMD Address Mapping
+ * ----------------------------------------------------- */
+
+/* -----------------------------------------------------
+ * I/O bus domain (Host)
+ * ----------------------------------------------------- */
+
+/* -----------------------------------------------------
+ * SDIO register
+ * ----------------------------------------------------- */
+#define SDIO_REG_HCPWM1_8723B	0x025 /* HCI Current Power Mode 1 */
+
+
+/* ****************************************************************************
+ *	8723 Regsiter Bit and Content definition
+ * **************************************************************************** */
+
+/* 2 HSISR
+ * interrupt mask which needs to clear */
+#define MASK_HSISR_CLEAR		(HSISR_GPIO12_0_INT |\
+		HSISR_SPS_OCP_INT |\
+		HSISR_RON_INT |\
+		HSISR_PDNINT |\
+		HSISR_GPIO9_INT)
+
+/* -----------------------------------------------------
+ *
+ *	0x0100h ~ 0x01FFh	MACTOP General Configuration
+ *
+ * ----------------------------------------------------- */
+#undef IS_E_CUT
+#define IS_E_CUT(version)		FALSE
+#undef IS_F_CUT
+#define IS_F_CUT(version)		((GET_CVID_CUT_VERSION(version) == E_CUT_VERSION) ? TRUE : FALSE)
+
+/* -----------------------------------------------------
+ *
+ *	0x0200h ~ 0x027Fh	TXDMA Configuration
+ *
+ * ----------------------------------------------------- */
+
+/* -----------------------------------------------------
+ *
+ *	0x0280h ~ 0x02FFh	RXDMA Configuration
+ *
+ * ----------------------------------------------------- */
+#define BIT_USB_RXDMA_AGG_EN	BIT(31)
+#define RXDMA_AGG_MODE_EN		BIT(1)
+
+#ifdef CONFIG_WOWLAN
+	#define RXPKT_RELEASE_POLL		BIT(16)
+	#define RXDMA_IDLE				BIT(17)
+	#define RW_RELEASE_EN			BIT(18)
+#endif
+
+/* -----------------------------------------------------
+ *
+ *	0x0400h ~ 0x047Fh	Protocol Configuration
+ *
+ * ----------------------------------------------------- */
+
+/* ----------------------------------------------------------------------------
+ * 8723B REG_CCK_CHECK						(offset 0x454)
+ * ---------------------------------------------------------------------------- */
+#define BIT_BCN_PORT_SEL		BIT(5)
+
+/* -----------------------------------------------------
+ *
+ *	0x0500h ~ 0x05FFh	EDCA Configuration
+ *
+ * ----------------------------------------------------- */
+
+/* -----------------------------------------------------
+ *
+ *	0x0600h ~ 0x07FFh	WMAC Configuration
+ *
+ * ----------------------------------------------------- */
+#ifdef CONFIG_RF_POWER_TRIM
+
+	#ifdef CONFIG_RTL8723B
+		#define EEPROM_RF_GAIN_OFFSET			0xC1
+	#endif
+
+	#define EEPROM_RF_GAIN_VAL				0x1F6
+#endif /*CONFIG_RF_POWER_TRIM*/
+
+
+/* ----------------------------------------------------------------------------
+ * 8195 IMR/ISR bits						(offset 0xB0,  8bits)
+ * ---------------------------------------------------------------------------- */
+#define	IMR_DISABLED_8723B					0
+/* IMR DW0(0x00B0-00B3) Bit 0-31 */
+#define	IMR_TIMER2_8723B					BIT(31)		/* Timeout interrupt 2 */
+#define	IMR_TIMER1_8723B					BIT(30)		/* Timeout interrupt 1	 */
+#define	IMR_PSTIMEOUT_8723B				BIT(29)		/* Power Save Time Out Interrupt */
+#define	IMR_GTINT4_8723B					BIT(28)		/* When GTIMER4 expires, this bit is set to 1	 */
+#define	IMR_GTINT3_8723B					BIT(27)		/* When GTIMER3 expires, this bit is set to 1	 */
+#define	IMR_TXBCN0ERR_8723B				BIT(26)		/* Transmit Beacon0 Error			 */
+#define	IMR_TXBCN0OK_8723B				BIT(25)		/* Transmit Beacon0 OK			 */
+#define	IMR_TSF_BIT32_TOGGLE_8723B		BIT(24)		/* TSF Timer BIT(32) toggle indication interrupt			 */
+#define	IMR_BCNDMAINT0_8723B				BIT(20)		/* Beacon DMA Interrupt 0			 */
+#define	IMR_BCNDERR0_8723B				BIT(16)		/* Beacon Queue DMA OK0			 */
+#define	IMR_HSISR_IND_ON_INT_8723B		BIT(15)		/* HSISR Indicator (HSIMR & HSISR is true, this bit is set to 1) */
+#define	IMR_BCNDMAINT_E_8723B			BIT(14)		/* Beacon DMA Interrupt Extension for Win7			 */
+#define	IMR_ATIMEND_8723B				BIT(12)		/* CTWidnow End or ATIM Window End */
+#define	IMR_C2HCMD_8723B					BIT(10)		/* CPU to Host Command INT Status, Write 1 clear	 */
+#define	IMR_CPWM2_8723B					BIT(9)			/* CPU power Mode exchange INT Status, Write 1 clear	 */
+#define	IMR_CPWM_8723B					BIT(8)			/* CPU power Mode exchange INT Status, Write 1 clear	 */
+#define	IMR_HIGHDOK_8723B				BIT(7)			/* High Queue DMA OK	 */
+#define	IMR_MGNTDOK_8723B				BIT(6)			/* Management Queue DMA OK	 */
+#define	IMR_BKDOK_8723B					BIT(5)			/* AC_BK DMA OK		 */
+#define	IMR_BEDOK_8723B					BIT(4)			/* AC_BE DMA OK	 */
+#define	IMR_VIDOK_8723B					BIT(3)			/* AC_VI DMA OK		 */
+#define	IMR_VODOK_8723B					BIT(2)			/* AC_VO DMA OK	 */
+#define	IMR_RDU_8723B					BIT(1)			/* Rx Descriptor Unavailable	 */
+#define	IMR_ROK_8723B					BIT(0)			/* Receive DMA OK */
+
+/* IMR DW1(0x00B4-00B7) Bit 0-31 */
+#define	IMR_BCNDMAINT7_8723B				BIT(27)		/* Beacon DMA Interrupt 7 */
+#define	IMR_BCNDMAINT6_8723B				BIT(26)		/* Beacon DMA Interrupt 6 */
+#define	IMR_BCNDMAINT5_8723B				BIT(25)		/* Beacon DMA Interrupt 5 */
+#define	IMR_BCNDMAINT4_8723B				BIT(24)		/* Beacon DMA Interrupt 4 */
+#define	IMR_BCNDMAINT3_8723B				BIT(23)		/* Beacon DMA Interrupt 3 */
+#define	IMR_BCNDMAINT2_8723B				BIT(22)		/* Beacon DMA Interrupt 2 */
+#define	IMR_BCNDMAINT1_8723B				BIT(21)		/* Beacon DMA Interrupt 1 */
+#define	IMR_BCNDOK7_8723B					BIT(20)		/* Beacon Queue DMA OK Interrupt 7 */
+#define	IMR_BCNDOK6_8723B					BIT(19)		/* Beacon Queue DMA OK Interrupt 6 */
+#define	IMR_BCNDOK5_8723B					BIT(18)		/* Beacon Queue DMA OK Interrupt 5 */
+#define	IMR_BCNDOK4_8723B					BIT(17)		/* Beacon Queue DMA OK Interrupt 4 */
+#define	IMR_BCNDOK3_8723B					BIT(16)		/* Beacon Queue DMA OK Interrupt 3 */
+#define	IMR_BCNDOK2_8723B					BIT(15)		/* Beacon Queue DMA OK Interrupt 2 */
+#define	IMR_BCNDOK1_8723B					BIT(14)		/* Beacon Queue DMA OK Interrupt 1 */
+#define	IMR_ATIMEND_E_8723B				BIT(13)		/* ATIM Window End Extension for Win7 */
+#define	IMR_TXERR_8723B					BIT(11)		/* Tx Error Flag Interrupt Status, write 1 clear. */
+#define	IMR_RXERR_8723B					BIT(10)		/* Rx Error Flag INT Status, Write 1 clear */
+#define	IMR_TXFOVW_8723B					BIT(9)			/* Transmit FIFO Overflow */
+#define	IMR_RXFOVW_8723B					BIT(8)			/* Receive FIFO Overflow */
+
+#ifdef CONFIG_PCI_HCI
+	/* #define IMR_RX_MASK		(IMR_ROK_8723B|IMR_RDU_8723B|IMR_RXFOVW_8723B) */
+	#define IMR_TX_MASK			(IMR_VODOK_8723B | IMR_VIDOK_8723B | IMR_BEDOK_8723B | IMR_BKDOK_8723B | IMR_MGNTDOK_8723B | IMR_HIGHDOK_8723B)
+
+	#define RT_BCN_INT_MASKS	(IMR_BCNDMAINT0_8723B | IMR_TXBCN0OK_8723B | IMR_TXBCN0ERR_8723B | IMR_BCNDERR0_8723B)
+
+	#define RT_AC_INT_MASKS	(IMR_VIDOK_8723B | IMR_VODOK_8723B | IMR_BEDOK_8723B | IMR_BKDOK_8723B)
+#endif
+
+#endif /* __RTL8723B_SPEC_H__ */
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/include/rtl8723b_sreset.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/rtl8723b_sreset.h
--- linux-5.6.3/3rdparty/rtl8821ce/include/rtl8723b_sreset.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/rtl8723b_sreset.h	2020-04-10 16:35:06.849661608 +0300
@@ -0,0 +1,24 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#ifndef _RTL8723B_SRESET_H_
+#define _RTL8723B_SRESET_H_
+
+#include <rtw_sreset.h>
+
+#ifdef DBG_CONFIG_ERROR_DETECT
+	extern void rtl8723b_sreset_xmit_status_check(_adapter *padapter);
+	extern void rtl8723b_sreset_linked_status_check(_adapter *padapter);
+#endif
+#endif
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/include/rtl8723b_xmit.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/rtl8723b_xmit.h
--- linux-5.6.3/3rdparty/rtl8821ce/include/rtl8723b_xmit.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/rtl8723b_xmit.h	2020-04-10 16:35:06.849661608 +0300
@@ -0,0 +1,335 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#ifndef __RTL8723B_XMIT_H__
+#define __RTL8723B_XMIT_H__
+
+
+#define MAX_TID (15)
+
+
+#ifndef __INC_HAL8723BDESC_H
+	#define __INC_HAL8723BDESC_H
+
+	#define RX_STATUS_DESC_SIZE_8723B		24
+	#define RX_DRV_INFO_SIZE_UNIT_8723B 8
+
+
+	/* DWORD 0 */
+	#define SET_RX_STATUS_DESC_PKT_LEN_8723B(__pRxStatusDesc, __Value)		SET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 0, 14, __Value)
+	#define SET_RX_STATUS_DESC_EOR_8723B(__pRxStatusDesc, __Value)		SET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 30, 1, __Value)
+	#define SET_RX_STATUS_DESC_OWN_8723B(__pRxStatusDesc, __Value)		SET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 31, 1, __Value)
+
+	#define GET_RX_STATUS_DESC_PKT_LEN_8723B(__pRxStatusDesc)			LE_BITS_TO_4BYTE(__pRxStatusDesc, 0, 14)
+	#define GET_RX_STATUS_DESC_CRC32_8723B(__pRxStatusDesc)		LE_BITS_TO_4BYTE(__pRxStatusDesc, 14, 1)
+	#define GET_RX_STATUS_DESC_ICV_8723B(__pRxStatusDesc)				LE_BITS_TO_4BYTE(__pRxStatusDesc, 15, 1)
+	#define GET_RX_STATUS_DESC_DRVINFO_SIZE_8723B(__pRxStatusDesc)		LE_BITS_TO_4BYTE(__pRxStatusDesc, 16, 4)
+	#define GET_RX_STATUS_DESC_SECURITY_8723B(__pRxStatusDesc)			LE_BITS_TO_4BYTE(__pRxStatusDesc, 20, 3)
+	#define GET_RX_STATUS_DESC_QOS_8723B(__pRxStatusDesc)				LE_BITS_TO_4BYTE(__pRxStatusDesc, 23, 1)
+	#define GET_RX_STATUS_DESC_SHIFT_8723B(__pRxStatusDesc)		LE_BITS_TO_4BYTE(__pRxStatusDesc, 24, 2)
+	#define GET_RX_STATUS_DESC_PHY_STATUS_8723B(__pRxStatusDesc)			LE_BITS_TO_4BYTE(__pRxStatusDesc, 26, 1)
+	#define GET_RX_STATUS_DESC_SWDEC_8723B(__pRxStatusDesc)		LE_BITS_TO_4BYTE(__pRxStatusDesc, 27, 1)
+	#define GET_RX_STATUS_DESC_LAST_SEG_8723B(__pRxStatusDesc)			LE_BITS_TO_4BYTE(__pRxStatusDesc, 28, 1)
+	#define GET_RX_STATUS_DESC_FIRST_SEG_8723B(__pRxStatusDesc)		LE_BITS_TO_4BYTE(__pRxStatusDesc, 29, 1)
+	#define GET_RX_STATUS_DESC_EOR_8723B(__pRxStatusDesc)				LE_BITS_TO_4BYTE(__pRxStatusDesc, 30, 1)
+	#define GET_RX_STATUS_DESC_OWN_8723B(__pRxStatusDesc)				LE_BITS_TO_4BYTE(__pRxStatusDesc, 31, 1)
+
+	/* DWORD 1 */
+	#define GET_RX_STATUS_DESC_MACID_8723B(__pRxDesc)					LE_BITS_TO_4BYTE(__pRxDesc+4, 0, 7)
+	#define GET_RX_STATUS_DESC_TID_8723B(__pRxDesc)					LE_BITS_TO_4BYTE(__pRxDesc+4, 8, 4)
+	#define GET_RX_STATUS_DESC_AMSDU_8723B(__pRxDesc)					LE_BITS_TO_4BYTE(__pRxDesc+4, 13, 1)
+	#define GET_RX_STATUS_DESC_RXID_MATCH_8723B(__pRxDesc)		LE_BITS_TO_4BYTE(__pRxDesc+4, 14, 1)
+	#define GET_RX_STATUS_DESC_PAGGR_8723B(__pRxDesc)				LE_BITS_TO_4BYTE(__pRxDesc+4, 15, 1)
+	#define GET_RX_STATUS_DESC_A1_FIT_8723B(__pRxDesc)				LE_BITS_TO_4BYTE(__pRxDesc+4, 16, 4)
+	#define GET_RX_STATUS_DESC_CHKERR_8723B(__pRxDesc)				LE_BITS_TO_4BYTE(__pRxDesc+4, 20, 1)
+	#define GET_RX_STATUS_DESC_IPVER_8723B(__pRxDesc)			LE_BITS_TO_4BYTE(__pRxDesc+4, 21, 1)
+	#define GET_RX_STATUS_DESC_IS_TCPUDP__8723B(__pRxDesc)		LE_BITS_TO_4BYTE(__pRxDesc+4, 22, 1)
+	#define GET_RX_STATUS_DESC_CHK_VLD_8723B(__pRxDesc)	LE_BITS_TO_4BYTE(__pRxDesc+4, 23, 1)
+	#define GET_RX_STATUS_DESC_PAM_8723B(__pRxDesc)			LE_BITS_TO_4BYTE(__pRxDesc+4, 24, 1)
+	#define GET_RX_STATUS_DESC_PWR_8723B(__pRxDesc)			LE_BITS_TO_4BYTE(__pRxDesc+4, 25, 1)
+	#define GET_RX_STATUS_DESC_MORE_DATA_8723B(__pRxDesc)			LE_BITS_TO_4BYTE(__pRxDesc+4, 26, 1)
+	#define GET_RX_STATUS_DESC_MORE_FRAG_8723B(__pRxDesc)			LE_BITS_TO_4BYTE(__pRxDesc+4, 27, 1)
+	#define GET_RX_STATUS_DESC_TYPE_8723B(__pRxDesc)			LE_BITS_TO_4BYTE(__pRxDesc+4, 28, 2)
+	#define GET_RX_STATUS_DESC_MC_8723B(__pRxDesc)				LE_BITS_TO_4BYTE(__pRxDesc+4, 30, 1)
+	#define GET_RX_STATUS_DESC_BC_8723B(__pRxDesc)				LE_BITS_TO_4BYTE(__pRxDesc+4, 31, 1)
+
+	/* DWORD 2 */
+	#define GET_RX_STATUS_DESC_SEQ_8723B(__pRxStatusDesc)					LE_BITS_TO_4BYTE(__pRxStatusDesc+8, 0, 12)
+	#define GET_RX_STATUS_DESC_FRAG_8723B(__pRxStatusDesc)				LE_BITS_TO_4BYTE(__pRxStatusDesc+8, 12, 4)
+	#define GET_RX_STATUS_DESC_RX_IS_QOS_8723B(__pRxStatusDesc)		LE_BITS_TO_4BYTE(__pRxStatusDesc+8, 16, 1)
+	#define GET_RX_STATUS_DESC_WLANHD_IV_LEN_8723B(__pRxStatusDesc)	LE_BITS_TO_4BYTE(__pRxStatusDesc+8, 18, 6)
+	#define GET_RX_STATUS_DESC_RPT_SEL_8723B(__pRxStatusDesc)			LE_BITS_TO_4BYTE(__pRxStatusDesc+8, 28, 1)
+
+	/* DWORD 3 */
+	#define GET_RX_STATUS_DESC_RX_RATE_8723B(__pRxStatusDesc)				LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 0, 7)
+	#define GET_RX_STATUS_DESC_HTC_8723B(__pRxStatusDesc)					LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 10, 1)
+	#define GET_RX_STATUS_DESC_EOSP_8723B(__pRxStatusDesc)					LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 11, 1)
+	#define GET_RX_STATUS_DESC_BSSID_FIT_8723B(__pRxStatusDesc)		LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 12, 2)
+	#ifdef CONFIG_USB_RX_AGGREGATION
+		#define GET_RX_STATUS_DESC_USB_AGG_PKTNUM_8723B(__pRxStatusDesc)	LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 16, 8)
+	#endif
+	#define GET_RX_STATUS_DESC_PATTERN_MATCH_8723B(__pRxDesc)			LE_BITS_TO_4BYTE(__pRxDesc+12, 29, 1)
+	#define GET_RX_STATUS_DESC_UNICAST_MATCH_8723B(__pRxDesc)			LE_BITS_TO_4BYTE(__pRxDesc+12, 30, 1)
+	#define GET_RX_STATUS_DESC_MAGIC_MATCH_8723B(__pRxDesc)		LE_BITS_TO_4BYTE(__pRxDesc+12, 31, 1)
+
+	/* DWORD 6 */
+	#define GET_RX_STATUS_DESC_SPLCP_8723B(__pRxDesc)			LE_BITS_TO_4BYTE(__pRxDesc+16, 0, 1)
+	#define GET_RX_STATUS_DESC_LDPC_8723B(__pRxDesc)			LE_BITS_TO_4BYTE(__pRxDesc+16, 1, 1)
+	#define GET_RX_STATUS_DESC_STBC_8723B(__pRxDesc)			LE_BITS_TO_4BYTE(__pRxDesc+16, 2, 1)
+	#define GET_RX_STATUS_DESC_BW_8723B(__pRxDesc)			LE_BITS_TO_4BYTE(__pRxDesc+16, 4, 2)
+
+	/* DWORD 5 */
+	#define GET_RX_STATUS_DESC_TSFL_8723B(__pRxStatusDesc)				LE_BITS_TO_4BYTE(__pRxStatusDesc+20, 0, 32)
+
+	#define GET_RX_STATUS_DESC_BUFF_ADDR_8723B(__pRxDesc)		LE_BITS_TO_4BYTE(__pRxDesc+24, 0, 32)
+	#define GET_RX_STATUS_DESC_BUFF_ADDR64_8723B(__pRxDesc)		LE_BITS_TO_4BYTE(__pRxDesc+28, 0, 32)
+
+	#define SET_RX_STATUS_DESC_BUFF_ADDR_8723B(__pRxDesc, __Value)	SET_BITS_TO_LE_4BYTE(__pRxDesc+24, 0, 32, __Value)
+
+
+	/* Dword 0 */
+	#define GET_TX_DESC_OWN_8723B(__pTxDesc)				LE_BITS_TO_4BYTE(__pTxDesc, 31, 1)
+
+	#define SET_TX_DESC_PKT_SIZE_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 0, 16, __Value)
+	#define SET_TX_DESC_OFFSET_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 16, 8, __Value)
+	#define SET_TX_DESC_BMC_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 24, 1, __Value)
+	#define SET_TX_DESC_HTC_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 25, 1, __Value)
+	#define SET_TX_DESC_LAST_SEG_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 26, 1, __Value)
+	#define SET_TX_DESC_FIRST_SEG_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 27, 1, __Value)
+	#define SET_TX_DESC_LINIP_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 28, 1, __Value)
+	#define SET_TX_DESC_NO_ACM_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 29, 1, __Value)
+	#define SET_TX_DESC_GF_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 30, 1, __Value)
+	#define SET_TX_DESC_OWN_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 31, 1, __Value)
+
+	/* Dword 1 */
+	#define SET_TX_DESC_MACID_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 0, 7, __Value)
+	#define SET_TX_DESC_QUEUE_SEL_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 8, 5, __Value)
+	#define SET_TX_DESC_RDG_NAV_EXT_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 13, 1, __Value)
+	#define SET_TX_DESC_LSIG_TXOP_EN_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 14, 1, __Value)
+	#define SET_TX_DESC_PIFS_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 15, 1, __Value)
+	#define SET_TX_DESC_RATE_ID_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 16, 5, __Value)
+	#define SET_TX_DESC_EN_DESC_ID_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 21, 1, __Value)
+	#define SET_TX_DESC_SEC_TYPE_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 22, 2, __Value)
+	#define SET_TX_DESC_PKT_OFFSET_8723B(__pTxDesc, __Value)		SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 24, 5, __Value)
+
+
+	/* Dword 2 */
+	#define SET_TX_DESC_PAID_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 0,  9, __Value)
+	#define SET_TX_DESC_CCA_RTS_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 10, 2, __Value)
+	#define SET_TX_DESC_AGG_ENABLE_8723B(__pTxDesc, __Value)		SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 12, 1, __Value)
+	#define SET_TX_DESC_RDG_ENABLE_8723B(__pTxDesc, __Value)		SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 13, 1, __Value)
+	#define SET_TX_DESC_AGG_BREAK_8723B(__pTxDesc, __Value)				SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 16, 1, __Value)
+	#define SET_TX_DESC_MORE_FRAG_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 17, 1, __Value)
+	#define SET_TX_DESC_RAW_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 18, 1, __Value)
+	#define SET_TX_DESC_SPE_RPT_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 19, 1, __Value)
+	#define SET_TX_DESC_AMPDU_DENSITY_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 20, 3, __Value)
+	#define SET_TX_DESC_BT_INT_8723B(__pTxDesc, __Value)			SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 23, 1, __Value)
+	#define SET_TX_DESC_GID_8723B(__pTxDesc, __Value)			SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 24, 6, __Value)
+
+
+	/* Dword 3 */
+	#define SET_TX_DESC_WHEADER_LEN_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 0, 4, __Value)
+	#define SET_TX_DESC_CHK_EN_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 4, 1, __Value)
+	#define SET_TX_DESC_EARLY_MODE_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 5, 1, __Value)
+	#define SET_TX_DESC_HWSEQ_SEL_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 6, 2, __Value)
+	#define SET_TX_DESC_USE_RATE_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 8, 1, __Value)
+	#define SET_TX_DESC_DISABLE_RTS_FB_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 9, 1, __Value)
+	#define SET_TX_DESC_DISABLE_FB_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 10, 1, __Value)
+	#define SET_TX_DESC_CTS2SELF_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 11, 1, __Value)
+	#define SET_TX_DESC_RTS_ENABLE_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 12, 1, __Value)
+	#define SET_TX_DESC_HW_RTS_ENABLE_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 13, 1, __Value)
+	#define SET_TX_DESC_NAV_USE_HDR_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 15, 1, __Value)
+	#define SET_TX_DESC_USE_MAX_LEN_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 16, 1, __Value)
+	#define SET_TX_DESC_MAX_AGG_NUM_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 17, 5, __Value)
+	#define SET_TX_DESC_NDPA_8723B(__pTxDesc, __Value)		SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 22, 2, __Value)
+	#define SET_TX_DESC_AMPDU_MAX_TIME_8723B(__pTxDesc, __Value)		SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 24, 8, __Value)
+
+	/* Dword 4 */
+	#define SET_TX_DESC_TX_RATE_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 0, 7, __Value)
+	#define SET_TX_DESC_DATA_RATE_FB_LIMIT_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 8, 5, __Value)
+	#define SET_TX_DESC_RTS_RATE_FB_LIMIT_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 13, 4, __Value)
+	#define SET_TX_DESC_RETRY_LIMIT_ENABLE_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 17, 1, __Value)
+	#define SET_TX_DESC_DATA_RETRY_LIMIT_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 18, 6, __Value)
+	#define SET_TX_DESC_RTS_RATE_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 24, 5, __Value)
+
+
+	/* Dword 5 */
+	#define SET_TX_DESC_DATA_SC_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 0, 4, __Value)
+	#define SET_TX_DESC_DATA_SHORT_8723B(__pTxDesc, __Value)	SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 4, 1, __Value)
+	#define SET_TX_DESC_DATA_BW_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 5, 2, __Value)
+	#define SET_TX_DESC_DATA_LDPC_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 7, 1, __Value)
+	#define SET_TX_DESC_DATA_STBC_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 8, 2, __Value)
+	#define SET_TX_DESC_CTROL_STBC_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 10, 2, __Value)
+	#define SET_TX_DESC_RTS_SHORT_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 12, 1, __Value)
+	#define SET_TX_DESC_RTS_SC_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 13, 4, __Value)
+
+
+	/* Dword 6 */
+	#define SET_TX_DESC_SW_DEFINE_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 0, 12, __Value)
+	#define SET_TX_DESC_MBSSID_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 12, 4, __Value)
+	#define SET_TX_DESC_ANTSEL_A_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 16, 3, __Value)
+	#define SET_TX_DESC_ANTSEL_B_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 19, 3, __Value)
+	#define SET_TX_DESC_ANTSEL_C_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 22, 3, __Value)
+	#define SET_TX_DESC_ANTSEL_D_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 25, 3, __Value)
+
+	/* Dword 7 */
+	#ifdef CONFIG_PCI_HCI
+		#define SET_TX_DESC_TX_BUFFER_SIZE_8723B(__pTxDesc, __Value)		SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 0, 16, __Value)
+	#endif
+	#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_USB_HCI)
+		#define SET_TX_DESC_TX_DESC_CHECKSUM_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 0, 16, __Value)
+	#endif
+	#define SET_TX_DESC_USB_TXAGG_NUM_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 24, 8, __Value)
+	#ifdef CONFIG_SDIO_HCI
+		#define SET_TX_DESC_SDIO_TXSEQ_8723B(__pTxDesc, __Value)			SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 16, 8, __Value)
+	#endif
+
+	/* Dword 8 */
+	#define SET_TX_DESC_HWSEQ_EN_8723B(__pTxDesc, __Value)			SET_BITS_TO_LE_4BYTE(__pTxDesc+32, 15, 1, __Value)
+
+	/* Dword 9 */
+	#define SET_TX_DESC_SEQ_8723B(__pTxDesc, __Value)					SET_BITS_TO_LE_4BYTE(__pTxDesc+36, 12, 12, __Value)
+
+	/* Dword 10 */
+	#define SET_TX_DESC_TX_BUFFER_ADDRESS_8723B(__pTxDesc, __Value)	SET_BITS_TO_LE_4BYTE(__pTxDesc+40, 0, 32, __Value)
+	#define GET_TX_DESC_TX_BUFFER_ADDRESS_8723B(__pTxDesc)	LE_BITS_TO_4BYTE(__pTxDesc+40, 0, 32)
+
+	/* Dword 11 */
+	#define SET_TX_DESC_NEXT_DESC_ADDRESS_8723B(__pTxDesc, __Value)	SET_BITS_TO_LE_4BYTE(__pTxDesc+48, 0, 32, __Value)
+
+
+	#define SET_EARLYMODE_PKTNUM_8723B(__pAddr, __Value)					SET_BITS_TO_LE_4BYTE(__pAddr, 0, 4, __Value)
+	#define SET_EARLYMODE_LEN0_8723B(__pAddr, __Value)					SET_BITS_TO_LE_4BYTE(__pAddr, 4, 15, __Value)
+	#define SET_EARLYMODE_LEN1_1_8723B(__pAddr, __Value)					SET_BITS_TO_LE_4BYTE(__pAddr, 19, 13, __Value)
+	#define SET_EARLYMODE_LEN1_2_8723B(__pAddr, __Value)					SET_BITS_TO_LE_4BYTE(__pAddr+4, 0, 2, __Value)
+	#define SET_EARLYMODE_LEN2_8723B(__pAddr, __Value)					SET_BITS_TO_LE_4BYTE(__pAddr+4, 2, 15,	__Value)
+	#define SET_EARLYMODE_LEN3_8723B(__pAddr, __Value)					SET_BITS_TO_LE_4BYTE(__pAddr+4, 17, 15, __Value)
+
+#endif
+/* -----------------------------------------------------------
+ *
+ *	Rate
+ *
+ * -----------------------------------------------------------
+ * CCK Rates, TxHT = 0 */
+#define DESC8723B_RATE1M				0x00
+#define DESC8723B_RATE2M				0x01
+#define DESC8723B_RATE5_5M				0x02
+#define DESC8723B_RATE11M				0x03
+
+/* OFDM Rates, TxHT = 0 */
+#define DESC8723B_RATE6M				0x04
+#define DESC8723B_RATE9M				0x05
+#define DESC8723B_RATE12M				0x06
+#define DESC8723B_RATE18M				0x07
+#define DESC8723B_RATE24M				0x08
+#define DESC8723B_RATE36M				0x09
+#define DESC8723B_RATE48M				0x0a
+#define DESC8723B_RATE54M				0x0b
+
+/* MCS Rates, TxHT = 1 */
+#define DESC8723B_RATEMCS0				0x0c
+#define DESC8723B_RATEMCS1				0x0d
+#define DESC8723B_RATEMCS2				0x0e
+#define DESC8723B_RATEMCS3				0x0f
+#define DESC8723B_RATEMCS4				0x10
+#define DESC8723B_RATEMCS5				0x11
+#define DESC8723B_RATEMCS6				0x12
+#define DESC8723B_RATEMCS7				0x13
+#define DESC8723B_RATEMCS8				0x14
+#define DESC8723B_RATEMCS9				0x15
+#define DESC8723B_RATEMCS10		0x16
+#define DESC8723B_RATEMCS11		0x17
+#define DESC8723B_RATEMCS12		0x18
+#define DESC8723B_RATEMCS13		0x19
+#define DESC8723B_RATEMCS14		0x1a
+#define DESC8723B_RATEMCS15		0x1b
+#define DESC8723B_RATEVHTSS1MCS0		0x2c
+#define DESC8723B_RATEVHTSS1MCS1		0x2d
+#define DESC8723B_RATEVHTSS1MCS2		0x2e
+#define DESC8723B_RATEVHTSS1MCS3		0x2f
+#define DESC8723B_RATEVHTSS1MCS4		0x30
+#define DESC8723B_RATEVHTSS1MCS5		0x31
+#define DESC8723B_RATEVHTSS1MCS6		0x32
+#define DESC8723B_RATEVHTSS1MCS7		0x33
+#define DESC8723B_RATEVHTSS1MCS8		0x34
+#define DESC8723B_RATEVHTSS1MCS9		0x35
+#define DESC8723B_RATEVHTSS2MCS0		0x36
+#define DESC8723B_RATEVHTSS2MCS1		0x37
+#define DESC8723B_RATEVHTSS2MCS2		0x38
+#define DESC8723B_RATEVHTSS2MCS3		0x39
+#define DESC8723B_RATEVHTSS2MCS4		0x3a
+#define DESC8723B_RATEVHTSS2MCS5		0x3b
+#define DESC8723B_RATEVHTSS2MCS6		0x3c
+#define DESC8723B_RATEVHTSS2MCS7		0x3d
+#define DESC8723B_RATEVHTSS2MCS8		0x3e
+#define DESC8723B_RATEVHTSS2MCS9		0x3f
+
+
+#define	RX_HAL_IS_CCK_RATE_8723B(pDesc)\
+	(GET_RX_STATUS_DESC_RX_RATE_8723B(pDesc) == DESC8723B_RATE1M || \
+	 GET_RX_STATUS_DESC_RX_RATE_8723B(pDesc) == DESC8723B_RATE2M || \
+	 GET_RX_STATUS_DESC_RX_RATE_8723B(pDesc) == DESC8723B_RATE5_5M || \
+	 GET_RX_STATUS_DESC_RX_RATE_8723B(pDesc) == DESC8723B_RATE11M)
+
+
+void rtl8723b_update_txdesc(struct xmit_frame *pxmitframe, u8 *pmem);
+void rtl8723b_fill_fake_txdesc(PADAPTER padapter, u8 *pDesc, u32 BufferLen, u8 IsPsPoll, u8 IsBTQosNull, u8 bDataFrame);
+#if defined(CONFIG_CONCURRENT_MODE)
+	void fill_txdesc_force_bmc_camid(struct pkt_attrib *pattrib, u8 *ptxdesc);
+#endif
+void fill_txdesc_bmc_tx_rate(struct pkt_attrib *pattrib, u8 *ptxdesc);
+
+#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
+	s32 rtl8723bs_init_xmit_priv(PADAPTER padapter);
+	void rtl8723bs_free_xmit_priv(PADAPTER padapter);
+	s32 rtl8723bs_hal_xmit(PADAPTER padapter, struct xmit_frame *pxmitframe);
+	s32 rtl8723bs_mgnt_xmit(PADAPTER padapter, struct xmit_frame *pmgntframe);
+	s32	rtl8723bs_hal_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe);
+	s32 rtl8723bs_xmit_buf_handler(PADAPTER padapter);
+	thread_return rtl8723bs_xmit_thread(thread_context context);
+	#define hal_xmit_handler rtl8723bs_xmit_buf_handler
+#endif
+
+#ifdef CONFIG_USB_HCI
+	s32 rtl8723bu_xmit_buf_handler(PADAPTER padapter);
+	#define hal_xmit_handler rtl8723bu_xmit_buf_handler
+
+
+	s32 rtl8723bu_init_xmit_priv(PADAPTER padapter);
+	void rtl8723bu_free_xmit_priv(PADAPTER padapter);
+	s32 rtl8723bu_hal_xmit(PADAPTER padapter, struct xmit_frame *pxmitframe);
+	s32 rtl8723bu_mgnt_xmit(PADAPTER padapter, struct xmit_frame *pmgntframe);
+	s32	 rtl8723bu_hal_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe);
+	/* s32 rtl8812au_xmit_buf_handler(PADAPTER padapter); */
+	void rtl8723bu_xmit_tasklet(void *priv);
+	s32 rtl8723bu_xmitframe_complete(_adapter *padapter, struct xmit_priv *pxmitpriv, struct xmit_buf *pxmitbuf);
+	void _dbg_dump_tx_info(_adapter	*padapter, int frame_tag, struct tx_desc *ptxdesc);
+#endif
+
+#ifdef CONFIG_PCI_HCI
+	s32 rtl8723be_init_xmit_priv(PADAPTER padapter);
+	void rtl8723be_free_xmit_priv(PADAPTER padapter);
+	struct xmit_buf *rtl8723be_dequeue_xmitbuf(struct rtw_tx_ring *ring);
+	void	rtl8723be_xmitframe_resume(_adapter *padapter);
+	s32 rtl8723be_hal_xmit(PADAPTER padapter, struct xmit_frame *pxmitframe);
+	s32 rtl8723be_mgnt_xmit(PADAPTER padapter, struct xmit_frame *pmgntframe);
+	s32	rtl8723be_hal_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe);
+	void rtl8723be_xmit_tasklet(void *priv);
+#endif
+
+u8	BWMapping_8723B(PADAPTER Adapter, struct pkt_attrib *pattrib);
+u8	SCMapping_8723B(PADAPTER Adapter, struct pkt_attrib	*pattrib);
+
+#endif
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/include/rtl8723d_cmd.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/rtl8723d_cmd.h
--- linux-5.6.3/3rdparty/rtl8821ce/include/rtl8723d_cmd.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/rtl8723d_cmd.h	2020-04-10 16:35:06.850661655 +0300
@@ -0,0 +1,189 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#ifndef __RTL8723D_CMD_H__
+#define __RTL8723D_CMD_H__
+
+/* ---------------------------------------------------------------------------------------------------------
+ * ----------------------------------    H2C CMD DEFINITION    ------------------------------------------------
+ * --------------------------------------------------------------------------------------------------------- */
+
+enum h2c_cmd_8723D {
+	/* Common Class: 000 */
+	H2C_8723D_RSVD_PAGE = 0x00,
+	H2C_8723D_MEDIA_STATUS_RPT = 0x01,
+	H2C_8723D_SCAN_ENABLE = 0x02,
+	H2C_8723D_KEEP_ALIVE = 0x03,
+	H2C_8723D_DISCON_DECISION = 0x04,
+	H2C_8723D_PSD_OFFLOAD = 0x05,
+	H2C_8723D_AP_OFFLOAD = 0x08,
+	H2C_8723D_BCN_RSVDPAGE = 0x09,
+	H2C_8723D_PROBERSP_RSVDPAGE = 0x0A,
+	H2C_8723D_FCS_RSVDPAGE = 0x10,
+	H2C_8723D_FCS_INFO = 0x11,
+	H2C_8723D_AP_WOW_GPIO_CTRL = 0x13,
+
+	/* PoweSave Class: 001 */
+	H2C_8723D_SET_PWR_MODE = 0x20,
+	H2C_8723D_PS_TUNING_PARA = 0x21,
+	H2C_8723D_PS_TUNING_PARA2 = 0x22,
+	H2C_8723D_P2P_LPS_PARAM = 0x23,
+	H2C_8723D_P2P_PS_OFFLOAD = 0x24,
+	H2C_8723D_PS_SCAN_ENABLE = 0x25,
+	H2C_8723D_SAP_PS_ = 0x26,
+	H2C_8723D_INACTIVE_PS_ = 0x27, /* Inactive_PS */
+	H2C_8723D_FWLPS_IN_IPS_ = 0x28,
+
+	/* Dynamic Mechanism Class: 010 */
+	H2C_8723D_MACID_CFG = 0x40,
+	H2C_8723D_TXBF = 0x41,
+	H2C_8723D_RSSI_SETTING = 0x42,
+	H2C_8723D_AP_REQ_TXRPT = 0x43,
+	H2C_8723D_INIT_RATE_COLLECT = 0x44,
+	H2C_8723D_RA_PARA_ADJUST = 0x46,
+
+	/* BT Class: 011 */
+	H2C_8723D_B_TYPE_TDMA = 0x60,
+	H2C_8723D_BT_INFO = 0x61,
+	H2C_8723D_FORCE_BT_TXPWR = 0x62,
+	H2C_8723D_BT_IGNORE_WLANACT = 0x63,
+	H2C_8723D_DAC_SWING_VALUE = 0x64,
+	H2C_8723D_ANT_SEL_RSV = 0x65,
+	H2C_8723D_WL_OPMODE = 0x66,
+	H2C_8723D_BT_MP_OPER = 0x67,
+	H2C_8723D_BT_CONTROL = 0x68,
+	H2C_8723D_BT_WIFI_CTRL = 0x69,
+	H2C_8723D_BT_FW_PATCH = 0x6A,
+	H2C_8723D_BT_WLAN_CALIBRATION = 0x6D,
+
+	/* WOWLAN Class: 100 */
+	H2C_8723D_WOWLAN = 0x80,
+	H2C_8723D_REMOTE_WAKE_CTRL = 0x81,
+	H2C_8723D_AOAC_GLOBAL_INFO = 0x82,
+	H2C_8723D_AOAC_RSVD_PAGE = 0x83,
+	H2C_8723D_AOAC_RSVD_PAGE2 = 0x84,
+	H2C_8723D_D0_SCAN_OFFLOAD_CTRL = 0x85,
+	H2C_8723D_D0_SCAN_OFFLOAD_INFO = 0x86,
+	H2C_8723D_CHNL_SWITCH_OFFLOAD = 0x87,
+	H2C_8723D_P2P_OFFLOAD_RSVD_PAGE = 0x8A,
+	H2C_8723D_P2P_OFFLOAD = 0x8B,
+
+	H2C_8723D_RESET_TSF = 0xC0,
+	H2C_8723D_MAXID,
+};
+
+/* ---------------------------------------------------------------------------------------------------------
+ * ----------------------------------    H2C CMD CONTENT    --------------------------------------------------
+ * ---------------------------------------------------------------------------------------------------------
+ * _RSVDPAGE_LOC_CMD_0x00 */
+#define SET_8723D_H2CCMD_RSVDPAGE_LOC_PROBE_RSP(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
+#define SET_8723D_H2CCMD_RSVDPAGE_LOC_PSPOLL(__pH2CCmd, __Value)				SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 8, __Value)
+#define SET_8723D_H2CCMD_RSVDPAGE_LOC_NULL_DATA(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value)
+#define SET_8723D_H2CCMD_RSVDPAGE_LOC_QOS_NULL_DATA(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 8, __Value)
+#define SET_8723D_H2CCMD_RSVDPAGE_LOC_BT_QOS_NULL_DATA(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 0, 8, __Value)
+
+/* _PWR_MOD_CMD_0x20 */
+#define SET_8723D_H2CCMD_PWRMODE_PARM_MODE(__pH2CCmd, __Value)				SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
+#define SET_8723D_H2CCMD_PWRMODE_PARM_RLBM(__pH2CCmd, __Value)				SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 4, __Value)
+#define SET_8723D_H2CCMD_PWRMODE_PARM_SMART_PS(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 4, 4, __Value)
+#define SET_8723D_H2CCMD_PWRMODE_PARM_BCN_PASS_TIME(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value)
+#define SET_8723D_H2CCMD_PWRMODE_PARM_ALL_QUEUE_UAPSD(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 8, __Value)
+#define SET_8723D_H2CCMD_PWRMODE_PARM_BCN_EARLY_C2H_RPT(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 2, 1, __Value)
+#define SET_8723D_H2CCMD_PWRMODE_PARM_PWR_STATE(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 0, 8, __Value)
+
+#define GET_8723D_H2CCMD_PWRMODE_PARM_MODE(__pH2CCmd)					LE_BITS_TO_1BYTE(__pH2CCmd, 0, 8)
+
+/* _PS_TUNE_PARAM_CMD_0x21 */
+#define SET_8723D_H2CCMD_PSTUNE_PARM_BCN_TO_LIMIT(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
+#define SET_8723D_H2CCMD_PSTUNE_PARM_DTIM_TIMEOUT(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 0, 8, __Value)
+#define SET_8723D_H2CCMD_PSTUNE_PARM_ADOPT(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 0, 1, __Value)
+#define SET_8723D_H2CCMD_PSTUNE_PARM_PS_TIMEOUT(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 1, 7, __Value)
+#define SET_8723D_H2CCMD_PSTUNE_PARM_DTIM_PERIOD(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE(__pH2CCmd+3, 0, 8, __Value)
+
+/* _MACID_CFG_CMD_0x40 */
+#define SET_8723D_H2CCMD_MACID_CFG_MACID(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
+#define SET_8723D_H2CCMD_MACID_CFG_RAID(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 0, 5, __Value)
+#define SET_8723D_H2CCMD_MACID_CFG_SGI_EN(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 7, 1, __Value)
+#define SET_8723D_H2CCMD_MACID_CFG_BW(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 0, 2, __Value)
+#define SET_8723D_H2CCMD_MACID_CFG_NO_UPDATE(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 3, 1, __Value)
+#define SET_8723D_H2CCMD_MACID_CFG_VHT_EN(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 4, 2, __Value)
+#define SET_8723D_H2CCMD_MACID_CFG_DISPT(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 6, 1, __Value)
+#define SET_8723D_H2CCMD_MACID_CFG_DISRA(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 7, 1, __Value)
+#define SET_8723D_H2CCMD_MACID_CFG_RATE_MASK0(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd+3, 0, 8, __Value)
+#define SET_8723D_H2CCMD_MACID_CFG_RATE_MASK1(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd+4, 0, 8, __Value)
+#define SET_8723D_H2CCMD_MACID_CFG_RATE_MASK2(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd+5, 0, 8, __Value)
+#define SET_8723D_H2CCMD_MACID_CFG_RATE_MASK3(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd+6, 0, 8, __Value)
+
+/* _RSSI_SETTING_CMD_0x42 */
+#define SET_8723D_H2CCMD_RSSI_SETTING_MACID(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
+#define SET_8723D_H2CCMD_RSSI_SETTING_RSSI(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 0, 7, __Value)
+#define SET_8723D_H2CCMD_RSSI_SETTING_ULDL_STATE(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd+3, 0, 8, __Value)
+
+/* _AP_REQ_TXRPT_CMD_0x43 */
+#define SET_8723D_H2CCMD_APREQRPT_PARM_MACID1(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
+#define SET_8723D_H2CCMD_APREQRPT_PARM_MACID2(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 0, 8, __Value)
+
+/* _FORCE_BT_TXPWR_CMD_0x62 */
+#define SET_8723D_H2CCMD_BT_PWR_IDX(__pH2CCmd, __Value)							SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
+
+/* _FORCE_BT_MP_OPER_CMD_0x67 */
+#define SET_8723D_H2CCMD_BT_MPOPER_VER(__pH2CCmd, __Value)							SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 4, __Value)
+#define SET_8723D_H2CCMD_BT_MPOPER_REQNUM(__pH2CCmd, __Value)							SET_BITS_TO_LE_1BYTE(__pH2CCmd, 4, 4, __Value)
+#define SET_8723D_H2CCMD_BT_MPOPER_IDX(__pH2CCmd, __Value)							SET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 0, 8, __Value)
+#define SET_8723D_H2CCMD_BT_MPOPER_PARAM1(__pH2CCmd, __Value)							SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 0, 8, __Value)
+#define SET_8723D_H2CCMD_BT_MPOPER_PARAM2(__pH2CCmd, __Value)							SET_BITS_TO_LE_1BYTE(__pH2CCmd+3, 0, 8, __Value)
+#define SET_8723D_H2CCMD_BT_MPOPER_PARAM3(__pH2CCmd, __Value)							SET_BITS_TO_LE_1BYTE(__pH2CCmd+4, 0, 8, __Value)
+
+/* _BT_FW_PATCH_0x6A */
+#define SET_8723D_H2CCMD_BT_FW_PATCH_SIZE(__pH2CCmd, __Value)					SET_BITS_TO_LE_2BYTE((pu1Byte)(__pH2CCmd), 0, 16, __Value)
+#define SET_8723D_H2CCMD_BT_FW_PATCH_ADDR0(__pH2CCmd, __Value)					SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value)
+#define SET_8723D_H2CCMD_BT_FW_PATCH_ADDR1(__pH2CCmd, __Value)					SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 8, __Value)
+#define SET_8723D_H2CCMD_BT_FW_PATCH_ADDR2(__pH2CCmd, __Value)					SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 0, 8, __Value)
+#define SET_8723D_H2CCMD_BT_FW_PATCH_ADDR3(__pH2CCmd, __Value)					SET_BITS_TO_LE_1BYTE((__pH2CCmd)+5, 0, 8, __Value)
+
+/* ---------------------------------------------------------------------------------------------------------
+ * -------------------------------------------    Structure    --------------------------------------------------
+ * --------------------------------------------------------------------------------------------------------- */
+
+
+/* ---------------------------------------------------------------------------------------------------------
+ * ----------------------------------    Function Statement     --------------------------------------------------
+ * --------------------------------------------------------------------------------------------------------- */
+
+/* host message to firmware cmd */
+void rtl8723d_set_FwPwrMode_cmd(PADAPTER padapter, u8 Mode);
+void rtl8723d_set_FwJoinBssRpt_cmd(PADAPTER padapter, u8 mstatus);
+/* s32 rtl8723d_set_lowpwr_lps_cmd(PADAPTER padapter, u8 enable); */
+void rtl8723d_set_FwPsTuneParam_cmd(PADAPTER padapter);
+void rtl8723d_download_rsvd_page(PADAPTER padapter, u8 mstatus);
+#ifdef CONFIG_BT_COEXIST
+	void rtl8723d_download_BTCoex_AP_mode_rsvd_page(PADAPTER padapter);
+#endif /* CONFIG_BT_COEXIST */
+#ifdef CONFIG_P2P
+	void rtl8723d_set_p2p_ps_offload_cmd(PADAPTER padapter, u8 p2p_ps_state);
+#endif /* CONFIG_P2P */
+
+#ifdef CONFIG_TDLS
+#ifdef CONFIG_TDLS_CH_SW
+void rtl8723d_set_BcnEarly_C2H_Rpt_cmd(PADAPTER padapter, u8 enable);
+#endif
+#endif
+
+#ifdef CONFIG_P2P_WOWLAN
+	void rtl8723d_set_p2p_wowlan_offload_cmd(PADAPTER padapter);
+#endif
+
+s32 FillH2CCmd8723D(PADAPTER padapter, u8 ElementID, u32 CmdLen, u8 *pCmdBuffer);
+u8 GetTxBufferRsvdPageNum8723D(_adapter *padapter, bool wowlan);
+#endif
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/include/rtl8723d_dm.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/rtl8723d_dm.h
--- linux-5.6.3/3rdparty/rtl8821ce/include/rtl8723d_dm.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/rtl8723d_dm.h	2020-04-10 16:35:06.850661655 +0300
@@ -0,0 +1,39 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#ifndef __RTL8723D_DM_H__
+#define __RTL8723D_DM_H__
+/* ************************************************************
+ * Description:
+ *
+ * This file is for 8723D dynamic mechanism only
+ *
+ *
+ * ************************************************************ */
+
+/* ************************************************************
+ * structure and define
+ * ************************************************************ */
+
+/* ************************************************************
+ * function prototype
+ * ************************************************************ */
+
+void rtl8723d_init_dm_priv(PADAPTER padapter);
+void rtl8723d_deinit_dm_priv(PADAPTER padapter);
+
+void rtl8723d_InitHalDm(PADAPTER padapter);
+void rtl8723d_HalDmWatchDog(PADAPTER padapter);
+
+#endif
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/include/rtl8723d_hal.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/rtl8723d_hal.h
--- linux-5.6.3/3rdparty/rtl8821ce/include/rtl8723d_hal.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/rtl8723d_hal.h	2020-04-10 16:35:06.850661655 +0300
@@ -0,0 +1,303 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#ifndef __RTL8723D_HAL_H__
+#define __RTL8723D_HAL_H__
+
+#include "hal_data.h"
+
+#include "rtl8723d_spec.h"
+#include "rtl8723d_rf.h"
+#include "rtl8723d_dm.h"
+#include "rtl8723d_recv.h"
+#include "rtl8723d_xmit.h"
+#include "rtl8723d_cmd.h"
+#include "rtl8723d_led.h"
+#include "Hal8723DPwrSeq.h"
+#include "Hal8723DPhyReg.h"
+#include "Hal8723DPhyCfg.h"
+#ifdef DBG_CONFIG_ERROR_DETECT
+	#include "rtl8723d_sreset.h"
+#endif
+#ifdef CONFIG_LPS_POFF
+	#include "rtl8723d_lps_poff.h"
+#endif
+
+#define FW_8723D_SIZE		0x8000
+#define FW_8723D_START_ADDRESS	0x1000
+#define FW_8723D_END_ADDRESS	0x1FFF /* 0x5FFF */
+
+#define IS_FW_HEADER_EXIST_8723D(_pFwHdr)\
+	((le16_to_cpu(_pFwHdr->Signature) & 0xFFF0) == 0x23D0)
+
+typedef struct _RT_FIRMWARE {
+	FIRMWARE_SOURCE	eFWSource;
+#ifdef CONFIG_EMBEDDED_FWIMG
+	u8			*szFwBuffer;
+#else
+	u8			szFwBuffer[FW_8723D_SIZE];
+#endif
+	u32			ulFwLength;
+} RT_FIRMWARE_8723D, *PRT_FIRMWARE_8723D;
+
+/*
+ * This structure must be cared byte-ordering
+ *
+ * Added by tynli. 2009.12.04. */
+typedef struct _RT_8723D_FIRMWARE_HDR {
+	/* 8-byte alinment required */
+
+	/* --- LONG WORD 0 ---- */
+	u16		Signature;	/* 92C0: test chip; 92C, 88C0: test chip; 88C1: MP A-cut; 92C1: MP A-cut */
+	u8		Category;	/* AP/NIC and USB/PCI */
+	u8		Function;	/* Reserved for different FW function indcation, for further use when driver needs to download different FW in different conditions */
+	u16		Version;		/* FW Version */
+	u16		Subversion;	/* FW Subversion, default 0x00 */
+
+	/* --- LONG WORD 1 ---- */
+	u8		Month;	/* Release time Month field */
+	u8		Date;	/* Release time Date field */
+	u8		Hour;	/* Release time Hour field */
+	u8		Minute;	/* Release time Minute field */
+	u16		RamCodeSize;	/* The size of RAM code */
+	u16		Rsvd2;
+
+	/* --- LONG WORD 2 ---- */
+	u32		SvnIdx;	/* The SVN entry index */
+	u32		Rsvd3;
+
+	/* --- LONG WORD 3 ---- */
+	u32		Rsvd4;
+	u32		Rsvd5;
+} RT_8723D_FIRMWARE_HDR, *PRT_8723D_FIRMWARE_HDR;
+
+#define DRIVER_EARLY_INT_TIME_8723D		0x05
+#define BCN_DMA_ATIME_INT_TIME_8723D		0x02
+
+/* for 8723D
+ * TX 32K, RX 16K, Page size 128B for TX, 8B for RX */
+#define PAGE_SIZE_TX_8723D			128
+#define PAGE_SIZE_RX_8723D			8
+
+#define TX_DMA_SIZE_8723D			0x8000	/* 32K(TX) */
+#define RX_DMA_SIZE_8723D			0x4000	/* 16K(RX) */
+
+#ifdef CONFIG_WOWLAN
+	#define RESV_FMWF	(WKFMCAM_SIZE * MAX_WKFM_CAM_NUM) /* 16 entries, for each is 24 bytes*/
+#else
+	#define RESV_FMWF	0
+#endif
+
+#ifdef CONFIG_FW_C2H_DEBUG
+	#define RX_DMA_RESERVED_SIZE_8723D	0x100	/* 256B, reserved for c2h debug message */
+#else
+	#define RX_DMA_RESERVED_SIZE_8723D	0x80	/* 128B, reserved for tx report */
+#endif
+#define RX_DMA_BOUNDARY_8723D\
+	(RX_DMA_SIZE_8723D - RX_DMA_RESERVED_SIZE_8723D - 1)
+
+
+/* Note: We will divide number of page equally for each queue other than public queue! */
+
+/* For General Reserved Page Number(Beacon Queue is reserved page)
+ * Beacon:MAX_BEACON_LEN/PAGE_SIZE_TX_8723D
+ * PS-Poll:1, Null Data:1,Qos Null Data:1,BT Qos Null Data:1,CTS-2-SELF,LTE QoS Null*/
+
+#define BCNQ_PAGE_NUM_8723D		(MAX_BEACON_LEN/PAGE_SIZE_TX_8723D + 6) /*0x08*/
+
+/* For WoWLan , more reserved page
+ * ARP Rsp:1, RWC:1, GTK Info:1,GTK RSP:2,GTK EXT MEM:2, AOAC rpt 1, PNO: 6
+ * NS offload: 2 NDP info: 1
+ */
+#ifdef CONFIG_WOWLAN
+	#define WOWLAN_PAGE_NUM_8723D	0x0b
+#else
+	#define WOWLAN_PAGE_NUM_8723D	0x00
+#endif
+
+#ifdef CONFIG_PNO_SUPPORT
+	#undef WOWLAN_PAGE_NUM_8723D
+	#define WOWLAN_PAGE_NUM_8723D	0x15
+#endif
+
+#ifdef CONFIG_AP_WOWLAN
+	#define AP_WOWLAN_PAGE_NUM_8723D	0x02
+#endif
+
+#define TX_TOTAL_PAGE_NUMBER_8723D\
+	(0xFF - BCNQ_PAGE_NUM_8723D - WOWLAN_PAGE_NUM_8723D)
+#define TX_PAGE_BOUNDARY_8723D		(TX_TOTAL_PAGE_NUMBER_8723D + 1)
+
+#define WMM_NORMAL_TX_TOTAL_PAGE_NUMBER_8723D	TX_TOTAL_PAGE_NUMBER_8723D
+#define WMM_NORMAL_TX_PAGE_BOUNDARY_8723D\
+	(WMM_NORMAL_TX_TOTAL_PAGE_NUMBER_8723D + 1)
+
+/* For Normal Chip Setting
+ * (HPQ + LPQ + NPQ + PUBQ) shall be TX_TOTAL_PAGE_NUMBER_8723D */
+#define NORMAL_PAGE_NUM_HPQ_8723D		0x0C
+#define NORMAL_PAGE_NUM_LPQ_8723D		0x02
+#define NORMAL_PAGE_NUM_NPQ_8723D		0x02
+#define NORMAL_PAGE_NUM_EPQ_8723D		0x04
+
+/* Note: For Normal Chip Setting, modify later */
+#define WMM_NORMAL_PAGE_NUM_HPQ_8723D		0x30
+#define WMM_NORMAL_PAGE_NUM_LPQ_8723D		0x20
+#define WMM_NORMAL_PAGE_NUM_NPQ_8723D		0x20
+#define WMM_NORMAL_PAGE_NUM_EPQ_8723D		0x00
+
+
+#include "HalVerDef.h"
+#include "hal_com.h"
+
+#define EFUSE_OOB_PROTECT_BYTES (96 + 1)
+
+#define HAL_EFUSE_MEMORY
+#define HWSET_MAX_SIZE_8723D                512
+#define EFUSE_REAL_CONTENT_LEN_8723D        512
+#define EFUSE_MAP_LEN_8723D                 512
+#define EFUSE_MAX_SECTION_8723D             64
+
+/* For some inferiority IC purpose. added by Roger, 2009.09.02.*/
+#define EFUSE_IC_ID_OFFSET			506
+#define AVAILABLE_EFUSE_ADDR(addr)	(addr < EFUSE_REAL_CONTENT_LEN_8723D)
+
+#define EFUSE_ACCESS_ON		0x69
+#define EFUSE_ACCESS_OFF	0x00
+
+/* ********************************************************
+ *			EFUSE for BT definition
+ * ******************************************************** */
+#define BANK_NUM			1
+#define EFUSE_BT_REAL_BANK_CONTENT_LEN	128
+#define EFUSE_BT_REAL_CONTENT_LEN	\
+	(EFUSE_BT_REAL_BANK_CONTENT_LEN * BANK_NUM)
+#define EFUSE_BT_MAP_LEN		1024	/* 1k bytes */
+#define EFUSE_BT_MAX_SECTION		(EFUSE_BT_MAP_LEN / 8)
+#define EFUSE_PROTECT_BYTES_BANK	16
+
+typedef enum tag_Package_Definition {
+	PACKAGE_DEFAULT,
+	PACKAGE_QFN68,
+	PACKAGE_TFBGA90,
+	PACKAGE_TFBGA80,
+	PACKAGE_TFBGA79
+} PACKAGE_TYPE_E;
+
+#define INCLUDE_MULTI_FUNC_BT(_Adapter) \
+	(GET_HAL_DATA(_Adapter)->MultiFunc & RT_MULTI_FUNC_BT)
+#define INCLUDE_MULTI_FUNC_GPS(_Adapter) \
+	(GET_HAL_DATA(_Adapter)->MultiFunc & RT_MULTI_FUNC_GPS)
+
+#ifdef CONFIG_FILE_FWIMG
+	extern char *rtw_fw_file_path;
+	extern char *rtw_fw_wow_file_path;
+	#ifdef CONFIG_MP_INCLUDED
+		extern char *rtw_fw_mp_bt_file_path;
+	#endif /* CONFIG_MP_INCLUDED */
+#endif /* CONFIG_FILE_FWIMG */
+
+/* rtl8723d_hal_init.c */
+s32 rtl8723d_FirmwareDownload(PADAPTER padapter, BOOLEAN  bUsedWoWLANFw);
+void rtl8723d_FirmwareSelfReset(PADAPTER padapter);
+void rtl8723d_InitializeFirmwareVars(PADAPTER padapter);
+
+void rtl8723d_InitAntenna_Selection(PADAPTER padapter);
+void rtl8723d_DeinitAntenna_Selection(PADAPTER padapter);
+void rtl8723d_CheckAntenna_Selection(PADAPTER padapter);
+void rtl8723d_init_default_value(PADAPTER padapter);
+
+s32 rtl8723d_InitLLTTable(PADAPTER padapter);
+
+s32 CardDisableHWSM(PADAPTER padapter, u8 resetMCU);
+s32 CardDisableWithoutHWSM(PADAPTER padapter);
+
+/* EFuse */
+u8 GetEEPROMSize8723D(PADAPTER padapter);
+void Hal_InitPGData(PADAPTER padapter, u8 *PROMContent);
+void Hal_EfuseParseIDCode(PADAPTER padapter, u8 *hwinfo);
+void Hal_EfuseParseTxPowerInfo_8723D(PADAPTER padapter,
+				     u8 *PROMContent, BOOLEAN AutoLoadFail);
+void Hal_EfuseParseBTCoexistInfo_8723D(PADAPTER padapter,
+				       u8 *hwinfo, BOOLEAN AutoLoadFail);
+void Hal_EfuseParseEEPROMVer_8723D(PADAPTER padapter,
+				   u8 *hwinfo, BOOLEAN AutoLoadFail);
+void Hal_EfuseParseChnlPlan_8723D(PADAPTER padapter,
+				  u8 *hwinfo, BOOLEAN AutoLoadFail);
+void Hal_EfuseParseCustomerID_8723D(PADAPTER padapter,
+				    u8 *hwinfo, BOOLEAN AutoLoadFail);
+void Hal_EfuseParseAntennaDiversity_8723D(PADAPTER padapter,
+		u8 *hwinfo, BOOLEAN AutoLoadFail);
+void Hal_EfuseParseXtal_8723D(PADAPTER pAdapter,
+			      u8 *hwinfo, u8 AutoLoadFail);
+void Hal_EfuseParseThermalMeter_8723D(PADAPTER padapter,
+				      u8 *hwinfo, u8 AutoLoadFail);
+VOID Hal_EfuseParseVoltage_8723D(PADAPTER pAdapter,
+				 u8 *hwinfo, BOOLEAN	AutoLoadFail);
+VOID Hal_EfuseParseBoardType_8723D(PADAPTER Adapter,
+				   u8	*PROMContent, BOOLEAN AutoloadFail);
+
+void rtl8723d_set_hal_ops(struct hal_ops *pHalFunc);
+void init_hal_spec_8723d(_adapter *adapter);
+u8 SetHwReg8723D(PADAPTER padapter, u8 variable, u8 *val);
+void GetHwReg8723D(PADAPTER padapter, u8 variable, u8 *val);
+u8 SetHalDefVar8723D(PADAPTER padapter, HAL_DEF_VARIABLE variable, void *pval);
+u8 GetHalDefVar8723D(PADAPTER padapter, HAL_DEF_VARIABLE variable, void *pval);
+
+/* register */
+void rtl8723d_InitBeaconParameters(PADAPTER padapter);
+void rtl8723d_InitBeaconMaxError(PADAPTER padapter, u8 InfraMode);
+void _InitMacAPLLSetting_8723D(PADAPTER Adapter);
+void _8051Reset8723(PADAPTER padapter);
+#ifdef CONFIG_WOWLAN
+	void Hal_DetectWoWMode(PADAPTER pAdapter);
+#endif /* CONFIG_WOWLAN */
+
+void rtl8723d_start_thread(_adapter *padapter);
+void rtl8723d_stop_thread(_adapter *padapter);
+
+#if defined(CONFIG_CHECK_BT_HANG) && defined(CONFIG_BT_COEXIST)
+	void rtl8723ds_init_checkbthang_workqueue(_adapter *adapter);
+	void rtl8723ds_free_checkbthang_workqueue(_adapter *adapter);
+	void rtl8723ds_cancle_checkbthang_workqueue(_adapter *adapter);
+	void rtl8723ds_hal_check_bt_hang(_adapter *adapter);
+#endif
+
+#ifdef CONFIG_GPIO_WAKEUP
+	void HalSetOutPutGPIO(PADAPTER padapter, u8 index, u8 OutPutValue);
+#endif
+#ifdef CONFIG_MP_INCLUDED
+int FirmwareDownloadBT(IN PADAPTER Adapter, PRT_MP_FIRMWARE pFirmware);
+#endif
+void CCX_FwC2HTxRpt_8723d(PADAPTER padapter, u8 *pdata, u8 len);
+
+u8 MRateToHwRate8723D(u8 rate);
+u8 HwRateToMRate8723D(u8 rate);
+
+void Hal_ReadRFGainOffset(PADAPTER pAdapter, u8 *hwinfo, BOOLEAN AutoLoadFail);
+
+#if defined(CONFIG_CHECK_BT_HANG) && defined(CONFIG_BT_COEXIST)
+	void check_bt_status_work(void *data);
+#endif
+
+#ifdef CONFIG_USB_HCI
+	void rtl8723d_cal_txdesc_chksum(struct tx_desc *ptxdesc);
+#endif
+
+#ifdef CONFIG_PCI_HCI
+	BOOLEAN	InterruptRecognized8723DE(PADAPTER Adapter);
+	VOID	UpdateInterruptMask8723DE(PADAPTER Adapter, u32 AddMSR, u32 AddMSR1, u32 RemoveMSR, u32 RemoveMSR1);
+	u16 get_txbd_rw_reg(u16 ff_hwaddr);
+#endif
+
+#endif
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/include/rtl8723d_led.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/rtl8723d_led.h
--- linux-5.6.3/3rdparty/rtl8821ce/include/rtl8723d_led.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/rtl8723d_led.h	2020-04-10 16:35:06.850661655 +0300
@@ -0,0 +1,44 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#ifndef __RTL8723D_LED_H__
+#define __RTL8723D_LED_H__
+
+#include <drv_conf.h>
+#include <osdep_service.h>
+#include <drv_types.h>
+
+#ifdef CONFIG_RTW_SW_LED
+/* ********************************************************************************
+ * Interface to manipulate LED objects.
+ * ******************************************************************************** */
+#ifdef CONFIG_USB_HCI
+	void rtl8723du_InitSwLeds(PADAPTER padapter);
+	void rtl8723du_DeInitSwLeds(PADAPTER padapter);
+#endif
+#ifdef CONFIG_SDIO_HCI
+	void rtl8723ds_InitSwLeds(PADAPTER padapter);
+	void rtl8723ds_DeInitSwLeds(PADAPTER padapter);
+#endif
+#ifdef CONFIG_GSPI_HCI
+	void rtl8723ds_InitSwLeds(PADAPTER padapter);
+	void rtl8723ds_DeInitSwLeds(PADAPTER padapter);
+#endif
+#ifdef CONFIG_PCI_HCI
+	void rtl8723de_InitSwLeds(PADAPTER padapter);
+	void rtl8723de_DeInitSwLeds(PADAPTER padapter);
+#endif
+
+#endif /*#ifdef CONFIG_RTW_SW_LED*/
+#endif
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/include/rtl8723d_lps_poff.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/rtl8723d_lps_poff.h
--- linux-5.6.3/3rdparty/rtl8821ce/include/rtl8723d_lps_poff.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/rtl8723d_lps_poff.h	2020-04-10 16:35:06.850661655 +0300
@@ -0,0 +1,56 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+
+/******************************************** CONST  ************************/
+#define NUM_OF_REGISTER_BANK	13
+#define NUM_OF_TOTAL_DWORD (NUM_OF_REGISTER_BANK * 64)
+#define TOTAL_LEN_FOR_HIOE ((NUM_OF_TOTAL_DWORD + 1) * 8)
+#define LPS_POFF_STATIC_FILE_LEN (TOTAL_LEN_FOR_HIOE + TXDESC_SIZE)
+#define LPS_POFF_DYNAMIC_FILE_LEN	(512 + TXDESC_SIZE)
+/******************************************** CONST  ************************/
+
+/******************************************** MACRO   ************************/
+/* HOIE Entry Definition */
+#define SET_HOIE_ENTRY_LOW_DATA(__pHOIE, __Value) \
+	SET_BITS_TO_LE_4BYTE((__pHOIE),	0, 16, __Value)
+#define SET_HOIE_ENTRY_HIGH_DATA(__pHOIE, __Value) \
+	SET_BITS_TO_LE_4BYTE((__pHOIE), 16, 16, __Value)
+#define SET_HOIE_ENTRY_MODE_SELECT(__pHOIE, __Value) \
+	SET_BITS_TO_LE_4BYTE((__pHOIE)+4, 0, 1, __Value)
+#define SET_HOIE_ENTRY_ADDRESS(__pHOIE, __Value) \
+	SET_BITS_TO_LE_4BYTE((__pHOIE)+4, 1, 14, __Value)
+#define SET_HOIE_ENTRY_BYTE_MASK(__pHOIE, __Value) \
+	SET_BITS_TO_LE_4BYTE((__pHOIE)+4, 15, 4, __Value)
+#define SET_HOIE_ENTRY_IO_LOCK(__pHOIE, __Value) \
+	SET_BITS_TO_LE_4BYTE((__pHOIE)+4, 19, 1, __Value)
+#define SET_HOIE_ENTRY_RD_EN(__pHOIE, __Value) \
+	SET_BITS_TO_LE_4BYTE((__pHOIE)+4, 20, 1, __Value)
+#define SET_HOIE_ENTRY_WR_EN(__pHOIE, __Value) \
+	SET_BITS_TO_LE_4BYTE((__pHOIE)+4, 21, 1, __Value)
+#define SET_HOIE_ENTRY_RAW_RW(__pHOIE, __Value) \
+	SET_BITS_TO_LE_4BYTE((__pHOIE)+4, 22, 1, __Value)
+#define SET_HOIE_ENTRY_RAW(__pHOIE, __Value) \
+	SET_BITS_TO_LE_4BYTE((__pHOIE)+4, 23, 1, __Value)
+#define SET_HOIE_ENTRY_IO_DELAY(__pHOIE, __Value) \
+	SET_BITS_TO_LE_4BYTE((__pHOIE)+4, 24, 8, __Value)
+
+/*********************Function Definition*******************************************/
+void rtl8723d_lps_poff_init(PADAPTER padapter);
+void rtl8723d_lps_poff_deinit(PADAPTER padapter);
+bool rtl8723d_lps_poff_get_txbndy_status(PADAPTER padapter);
+void rtl8723d_lps_poff_h2c_ctrl(PADAPTER padapter, u8 enable);
+void rtl8723d_lps_poff_set_ps_mode(PADAPTER padapter, bool bEnterLPS);
+bool rtl8723d_lps_poff_get_status(PADAPTER padapter);
+void rtl8723d_lps_poff_wow(PADAPTER padapter);
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/include/rtl8723d_recv.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/rtl8723d_recv.h
--- linux-5.6.3/3rdparty/rtl8821ce/include/rtl8723d_recv.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/rtl8723d_recv.h	2020-04-10 16:35:06.850661655 +0300
@@ -0,0 +1,116 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#ifndef __RTL8723D_RECV_H__
+#define __RTL8723D_RECV_H__
+
+#define RECV_BLK_SZ 512
+#define RECV_BLK_CNT 16
+#define RECV_BLK_TH RECV_BLK_CNT
+
+#if defined(CONFIG_USB_HCI)
+
+	#ifndef MAX_RECVBUF_SZ
+		#ifdef PLATFORM_OS_CE
+			#define MAX_RECVBUF_SZ (8192+1024) /* 8K+1k */
+		#else
+			#ifndef CONFIG_MINIMAL_MEMORY_USAGE
+				/* #define MAX_RECVBUF_SZ (32768) */ /* 32k */
+				/* #define MAX_RECVBUF_SZ (16384) */ /* 16K */
+				/* #define MAX_RECVBUF_SZ (10240) */ /* 10K */
+				#ifdef CONFIG_PLATFORM_MSTAR
+					#define MAX_RECVBUF_SZ (8192) /* 8K */
+				#else
+					#define MAX_RECVBUF_SZ (15360) /* 15k < 16k */
+				#endif
+				/* #define MAX_RECVBUF_SZ (8192+1024) */ /* 8K+1k */
+			#else
+				#define MAX_RECVBUF_SZ (4000) /* about 4K */
+			#endif
+		#endif
+	#endif /* !MAX_RECVBUF_SZ */
+
+#elif defined(CONFIG_PCI_HCI)
+	/* #ifndef CONFIG_MINIMAL_MEMORY_USAGE */
+	/*	#define MAX_RECVBUF_SZ (9100) */
+	/* #else */
+	#define MAX_RECVBUF_SZ (4000) /* about 4K
+	* #endif */
+
+
+#elif defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
+
+	#define MAX_RECVBUF_SZ (RX_DMA_BOUNDARY_8723D + 1)
+
+#endif
+
+/* Rx smooth factor */
+#define	Rx_Smooth_Factor (20)
+
+#ifdef CONFIG_SDIO_HCI
+	#ifndef CONFIG_SDIO_RX_COPY
+		#undef MAX_RECVBUF_SZ
+		#define MAX_RECVBUF_SZ	(RX_DMA_SIZE_8723D - RX_DMA_RESERVED_SIZE_8723D)
+	#endif /* !CONFIG_SDIO_RX_COPY */
+#endif /* CONFIG_SDIO_HCI */
+
+/*-----------------------------------------------------------------*/
+/*	RTL8723D RX BUFFER DESC                                      */
+/*-----------------------------------------------------------------*/
+/*DWORD 0*/
+#define SET_RX_BUFFER_DESC_DATA_LENGTH_8723D(__pRxStatusDesc, __Value)		SET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 0, 14, __Value)
+#define SET_RX_BUFFER_DESC_LS_8723D(__pRxStatusDesc, __Value)	SET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 15, 1, __Value)
+#define SET_RX_BUFFER_DESC_FS_8723D(__pRxStatusDesc, __Value)		SET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 16, 1, __Value)
+#define SET_RX_BUFFER_DESC_TOTAL_LENGTH_8723D(__pRxStatusDesc, __Value)		SET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 16, 15, __Value)
+
+#define GET_RX_BUFFER_DESC_OWN_8723D(__pRxStatusDesc)		LE_BITS_TO_4BYTE(__pRxStatusDesc, 31, 1)
+#define GET_RX_BUFFER_DESC_LS_8723D(__pRxStatusDesc)		LE_BITS_TO_4BYTE(__pRxStatusDesc, 15, 1)
+#define GET_RX_BUFFER_DESC_FS_8723D(__pRxStatusDesc)		LE_BITS_TO_4BYTE(__pRxStatusDesc, 16, 1)
+#ifdef USING_RX_TAG
+	#define GET_RX_BUFFER_DESC_RX_TAG_8723D(__pRxStatusDesc)		LE_BITS_TO_4BYTE(__pRxStatusDesc, 16, 13)
+#else
+	#define GET_RX_BUFFER_DESC_TOTAL_LENGTH_8723D(__pRxStatusDesc)		LE_BITS_TO_4BYTE(__pRxStatusDesc, 16, 15)
+#endif
+
+/*DWORD 1*/
+#define SET_RX_BUFFER_PHYSICAL_LOW_8723D(__pRxStatusDesc, __Value)		SET_BITS_TO_LE_4BYTE(__pRxStatusDesc+4, 0, 32, __Value)
+
+/*DWORD 2*/
+#ifdef CONFIG_64BIT_DMA
+	#define SET_RX_BUFFER_PHYSICAL_HIGH_8723D(__pRxStatusDesc, __Value)		SET_BITS_TO_LE_4BYTE(__pRxStatusDesc+8, 0, 32, __Value)
+#else
+	#define SET_RX_BUFFER_PHYSICAL_HIGH_8723D(__pRxStatusDesc, __Value)
+#endif
+
+
+#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
+	s32 rtl8723ds_init_recv_priv(PADAPTER padapter);
+	void rtl8723ds_free_recv_priv(PADAPTER padapter);
+	s32 rtl8723ds_recv_hdl(_adapter *padapter);
+#endif
+
+#ifdef CONFIG_USB_HCI
+	int rtl8723du_init_recv_priv(_adapter *padapter);
+	void rtl8723du_free_recv_priv(_adapter *padapter);
+	void rtl8723du_init_recvbuf(_adapter *padapter, struct recv_buf *precvbuf);
+#endif
+
+#ifdef CONFIG_PCI_HCI
+	s32 rtl8723de_init_recv_priv(PADAPTER padapter);
+	void rtl8723de_free_recv_priv(PADAPTER padapter);
+#endif
+
+void rtl8723d_query_rx_desc_status(union recv_frame *precvframe, u8 *pdesc);
+
+#endif /* __RTL8723D_RECV_H__ */
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/include/rtl8723d_rf.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/rtl8723d_rf.h
--- linux-5.6.3/3rdparty/rtl8821ce/include/rtl8723d_rf.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/rtl8723d_rf.h	2020-04-10 16:35:06.850661655 +0300
@@ -0,0 +1,21 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#ifndef __RTL8723D_RF_H__
+#define __RTL8723D_RF_H__
+
+int PHY_RF6052_Config8723D(IN PADAPTER pdapter);
+
+void PHY_RF6052SetBandwidth8723D(IN PADAPTER Adapter, IN enum channel_width Bandwidth);
+#endif
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/include/rtl8723d_spec.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/rtl8723d_spec.h
--- linux-5.6.3/3rdparty/rtl8821ce/include/rtl8723d_spec.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/rtl8723d_spec.h	2020-04-10 16:35:06.850661655 +0300
@@ -0,0 +1,447 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#ifndef __RTL8723D_SPEC_H__
+#define __RTL8723D_SPEC_H__
+
+#include <drv_conf.h>
+
+
+#define HAL_NAV_UPPER_UNIT_8723D		128		/* micro-second */
+
+/* -----------------------------------------------------
+ *
+ *	0x0000h ~ 0x00FFh	System Configuration
+ *
+ * ----------------------------------------------------- */
+#define REG_SYS_ISO_CTRL_8723D			0x0000	/* 2 Byte */
+#define REG_SYS_FUNC_EN_8723D			0x0002	/* 2 Byte */
+#define REG_APS_FSMCO_8723D			0x0004	/* 4 Byte */
+#define REG_SYS_CLKR_8723D				0x0008	/* 2 Byte */
+#define REG_9346CR_8723D				0x000A	/* 2 Byte */
+#define REG_EE_VPD_8723D				0x000C	/* 2 Byte */
+#define REG_AFE_MISC_8723D				0x0010	/* 1 Byte */
+#define REG_SPS0_CTRL_8723D				0x0011	/* 7 Byte */
+#define REG_SPS_OCP_CFG_8723D			0x0018	/* 4 Byte */
+#define REG_RSV_CTRL_8723D				0x001C	/* 3 Byte */
+#define REG_RF_CTRL_8723D				0x001F	/* 1 Byte */
+#define REG_LPLDO_CTRL_8723D			0x0023	/* 1 Byte */
+#define REG_AFE_XTAL_CTRL_8723D		0x0024	/* 4 Byte */
+#define REG_AFE_PLL_CTRL_8723D			0x0028	/* 4 Byte */
+#define REG_MAC_PLL_CTRL_EXT_8723D		0x002c	/* 4 Byte */
+#define REG_EFUSE_CTRL_8723D			0x0030
+#define REG_EFUSE_TEST_8723D			0x0034
+#define REG_PWR_DATA_8723D				0x0038
+#define REG_CAL_TIMER_8723D				0x003C
+#define REG_ACLK_MON_8723D				0x003E
+#define REG_GPIO_MUXCFG_8723D			0x0040
+#define REG_GPIO_IO_SEL_8723D			0x0042
+#define REG_MAC_PINMUX_CFG_8723D		0x0043
+#define REG_GPIO_PIN_CTRL_8723D			0x0044
+#define REG_GPIO_INTM_8723D				0x0048
+#define REG_LEDCFG0_8723D				0x004C
+#define REG_LEDCFG1_8723D				0x004D
+#define REG_LEDCFG2_8723D				0x004E
+#define REG_LEDCFG3_8723D				0x004F
+#define REG_FSIMR_8723D					0x0050
+#define REG_FSISR_8723D					0x0054
+#define REG_HSIMR_8723D					0x0058
+#define REG_HSISR_8723D					0x005c
+#define REG_GPIO_EXT_CTRL				0x0060
+#define REG_PAD_CTRL1_8723D		0x0064
+#define REG_MULTI_FUNC_CTRL_8723D		0x0068
+#define REG_GPIO_STATUS_8723D			0x006C
+#define REG_SDIO_CTRL_8723D				0x0070
+#define REG_OPT_CTRL_8723D				0x0074
+#define REG_AFE_CTRL_4_8723D		0x0078
+#define REG_MCUFWDL_8723D				0x0080
+#define REG_8051FW_CTRL_8723D			0x0080
+#define REG_HMEBOX_DBG_0_8723D	0x0088
+#define REG_HMEBOX_DBG_1_8723D	0x008A
+#define REG_HMEBOX_DBG_2_8723D	0x008C
+#define REG_HMEBOX_DBG_3_8723D	0x008E
+#define REG_WLLPS_CTRL		0x0090
+#define REG_HIMR0_8723D					0x00B0
+#define REG_HISR0_8723D					0x00B4
+#define REG_HIMR1_8723D					0x00B8
+#define REG_HISR1_8723D					0x00BC
+#define REG_PMC_DBG_CTRL2_8723D			0x00CC
+#define	REG_EFUSE_BURN_GNT_8723D		0x00CF
+#define REG_HPON_FSM_8723D				0x00EC
+#define REG_SYS_CFG1_8723D				0x00F0
+#define REG_SYS_CFG_8723D				0x00FC
+#define REG_ROM_VERSION					0x00FD
+
+/* -----------------------------------------------------
+ *
+ *	0x0100h ~ 0x01FFh	MACTOP General Configuration
+ *
+ * ----------------------------------------------------- */
+#define REG_C2HEVT_CMD_ID_8723D	0x01A0
+#define REG_C2HEVT_CMD_SEQ_88XX		0x01A1
+#define REG_C2hEVT_CMD_CONTENT_88XX	0x01A2
+#define REG_C2HEVT_CMD_LEN_8723D        0x01AE
+#define REG_C2HEVT_CLEAR_8723D			0x01AF
+#define REG_MCUTST_1_8723D				0x01C0
+#define REG_WOWLAN_WAKE_REASON 0x01C7
+#define REG_FMETHR_8723D				0x01C8
+#define REG_HMETFR_8723D				0x01CC
+#define REG_HMEBOX_0_8723D				0x01D0
+#define REG_HMEBOX_1_8723D				0x01D4
+#define REG_HMEBOX_2_8723D				0x01D8
+#define REG_HMEBOX_3_8723D				0x01DC
+#define REG_LLT_INIT_8723D				0x01E0
+#define REG_HMEBOX_EXT0_8723D			0x01F0
+#define REG_HMEBOX_EXT1_8723D			0x01F4
+#define REG_HMEBOX_EXT2_8723D			0x01F8
+#define REG_HMEBOX_EXT3_8723D			0x01FC
+
+/* -----------------------------------------------------
+ *
+ *	0x0200h ~ 0x027Fh	TXDMA Configuration
+ *
+ * ----------------------------------------------------- */
+#define REG_RQPN_8723D					0x0200
+#define REG_FIFOPAGE_8723D				0x0204
+#define REG_DWBCN0_CTRL_8723D			REG_TDECTRL
+#define REG_TXDMA_OFFSET_CHK_8723D	0x020C
+#define REG_TXDMA_STATUS_8723D		0x0210
+#define REG_RQPN_NPQ_8723D			0x0214
+#define REG_DWBCN1_CTRL_8723D			0x0228
+
+
+/* -----------------------------------------------------
+ *
+ *	0x0280h ~ 0x02FFh	RXDMA Configuration
+ *
+ * ----------------------------------------------------- */
+#define REG_RXDMA_AGG_PG_TH_8723D		0x0280
+#define REG_FW_UPD_RDPTR_8723D		0x0284 /* FW shall update this register before FW write RXPKT_RELEASE_POLL to 1 */
+#define REG_RXDMA_CONTROL_8723D		0x0286 /* Control the RX DMA. */
+#define REG_RXDMA_STATUS_8723D			0x0288
+#define REG_RXDMA_MODE_CTRL_8723D		0x0290
+#define REG_EARLY_MODE_CONTROL_8723D	0x02BC
+#define REG_RSVD5_8723D					0x02F0
+#define REG_RSVD6_8723D					0x02F4
+
+/* -----------------------------------------------------
+ *
+ *	0x0300h ~ 0x03FFh	PCIe
+ *
+ * ----------------------------------------------------- */
+#define	REG_PCIE_CTRL_REG_8723D			0x0300
+#define	REG_INT_MIG_8723D				0x0304	/* Interrupt Migration */
+#define	REG_BCNQ_TXBD_DESA_8723D		0x0308	/* TX Beacon Descriptor Address */
+#define	REG_MGQ_TXBD_DESA_8723D			0x0310	/* TX Manage Queue Descriptor Address */
+#define	REG_VOQ_TXBD_DESA_8723D			0x0318	/* TX VO Queue Descriptor Address */
+#define	REG_VIQ_TXBD_DESA_8723D			0x0320	/* TX VI Queue Descriptor Address */
+#define	REG_BEQ_TXBD_DESA_8723D			0x0328	/* TX BE Queue Descriptor Address */
+#define	REG_BKQ_TXBD_DESA_8723D			0x0330	/* TX BK Queue Descriptor Address */
+#define	REG_RXQ_RXBD_DESA_8723D			0x0338	/* RX Queue	Descriptor Address */
+#define REG_HI0Q_TXBD_DESA_8723D		0x0340
+#define REG_HI1Q_TXBD_DESA_8723D		0x0348
+#define REG_HI2Q_TXBD_DESA_8723D		0x0350
+#define REG_HI3Q_TXBD_DESA_8723D		0x0358
+#define REG_HI4Q_TXBD_DESA_8723D		0x0360
+#define REG_HI5Q_TXBD_DESA_8723D		0x0368
+#define REG_HI6Q_TXBD_DESA_8723D		0x0370
+#define REG_HI7Q_TXBD_DESA_8723D		0x0378
+#define	REG_MGQ_TXBD_NUM_8723D			0x0380
+#define	REG_RX_RXBD_NUM_8723D			0x0382
+#define	REG_VOQ_TXBD_NUM_8723D			0x0384
+#define	REG_VIQ_TXBD_NUM_8723D			0x0386
+#define	REG_BEQ_TXBD_NUM_8723D			0x0388
+#define	REG_BKQ_TXBD_NUM_8723D			0x038A
+#define	REG_HI0Q_TXBD_NUM_8723D			0x038C
+#define	REG_HI1Q_TXBD_NUM_8723D			0x038E
+#define	REG_HI2Q_TXBD_NUM_8723D			0x0390
+#define	REG_HI3Q_TXBD_NUM_8723D			0x0392
+#define	REG_HI4Q_TXBD_NUM_8723D			0x0394
+#define	REG_HI5Q_TXBD_NUM_8723D			0x0396
+#define	REG_HI6Q_TXBD_NUM_8723D			0x0398
+#define	REG_HI7Q_TXBD_NUM_8723D			0x039A
+#define	REG_TSFTIMER_HCI_8723D			0x039C
+#define	REG_BD_RW_PTR_CLR_8723D			0x039C
+
+/* Read Write Point */
+#define	REG_VOQ_TXBD_IDX_8723D			0x03A0
+#define	REG_VIQ_TXBD_IDX_8723D			0x03A4
+#define	REG_BEQ_TXBD_IDX_8723D			0x03A8
+#define	REG_BKQ_TXBD_IDX_8723D			0x03AC
+#define	REG_MGQ_TXBD_IDX_8723D			0x03B0
+#define	REG_RXQ_TXBD_IDX_8723D			0x03B4
+#define	REG_HI0Q_TXBD_IDX_8723D			0x03B8
+#define	REG_HI1Q_TXBD_IDX_8723D			0x03BC
+#define	REG_HI2Q_TXBD_IDX_8723D			0x03C0
+#define	REG_HI3Q_TXBD_IDX_8723D			0x03C4
+#define	REG_HI4Q_TXBD_IDX_8723D			0x03C8
+#define	REG_HI5Q_TXBD_IDX_8723D			0x03CC
+#define	REG_HI6Q_TXBD_IDX_8723D			0x03D0
+#define	REG_HI7Q_TXBD_IDX_8723D			0x03D4
+
+#define	REG_PCIE_HCPWM_8723DE			0x03D8 /* ?????? */
+#define	REG_PCIE_HRPWM_8723DE			0x03DC	/* PCIe RPWM  ?????? */
+#define	REG_DBI_WDATA_V1_8723D			0x03E8
+#define	REG_DBI_RDATA_V1_8723D			0x03EC
+#define	REG_DBI_FLAG_V1_8723D			0x03F0
+#define REG_MDIO_V1_8723D				0x03F4
+#define REG_PCIE_MIX_CFG_8723D			0x03F8
+#define REG_HCI_MIX_CFG_8723D			0x03FC
+
+/* -----------------------------------------------------
+ *
+ *	0x0400h ~ 0x047Fh	Protocol Configuration
+ *
+ * ----------------------------------------------------- */
+#define REG_VOQ_INFORMATION_8723D		0x0400
+#define REG_VIQ_INFORMATION_8723D		0x0404
+#define REG_BEQ_INFORMATION_8723D		0x0408
+#define REG_BKQ_INFORMATION_8723D		0x040C
+#define REG_MGQ_INFORMATION_8723D		0x0410
+#define REG_HGQ_INFORMATION_8723D		0x0414
+#define REG_BCNQ_INFORMATION_8723D	0x0418
+#define REG_TXPKT_EMPTY_8723D			0x041A
+
+#define REG_FWHW_TXQ_CTRL_8723D		0x0420
+#define REG_HWSEQ_CTRL_8723D			0x0423
+#define REG_TXPKTBUF_BCNQ_BDNY_8723D	0x0424
+#define REG_TXPKTBUF_MGQ_BDNY_8723D	0x0425
+#define REG_LIFECTRL_CTRL_8723D			0x0426
+#define REG_MULTI_BCNQ_OFFSET_8723D	0x0427
+#define REG_SPEC_SIFS_8723D				0x0428
+#define REG_RL_8723D						0x042A
+#define REG_TXBF_CTRL_8723D				0x042C
+#define REG_DARFRC_8723D				0x0430
+#define REG_RARFRC_8723D				0x0438
+#define REG_RRSR_8723D					0x0440
+#define REG_ARFR0_8723D					0x0444
+#define REG_ARFR1_8723D					0x044C
+#define REG_CCK_CHECK_8723D				0x0454
+#define REG_AMPDU_MAX_TIME_8723D		0x0456
+#define REG_TXPKTBUF_BCNQ_BDNY1_8723D	0x0457
+
+#define REG_AMPDU_MAX_LENGTH_8723D	0x0458
+#define REG_TXPKTBUF_WMAC_LBK_BF_HD_8723D	0x045D
+#define REG_NDPA_OPT_CTRL_8723D		0x045F
+#define REG_FAST_EDCA_CTRL_8723D		0x0460
+#define REG_RD_RESP_PKT_TH_8723D		0x0463
+#define REG_DATA_SC_8723D				0x0483
+#ifdef CONFIG_WOWLAN
+	#define REG_TXPKTBUF_IV_LOW             0x0484
+	#define REG_TXPKTBUF_IV_HIGH            0x0488
+#endif
+#define REG_TXRPT_START_OFFSET		0x04AC
+#define REG_POWER_STAGE1_8723D		0x04B4
+#define REG_POWER_STAGE2_8723D		0x04B8
+#define REG_AMPDU_BURST_MODE_8723D	0x04BC
+#define REG_PKT_VO_VI_LIFE_TIME_8723D	0x04C0
+#define REG_PKT_BE_BK_LIFE_TIME_8723D	0x04C2
+#define REG_STBC_SETTING_8723D			0x04C4
+#define REG_HT_SINGLE_AMPDU_8723D		0x04C7
+#define REG_PROT_MODE_CTRL_8723D		0x04C8
+#define REG_MAX_AGGR_NUM_8723D		0x04CA
+#define REG_RTS_MAX_AGGR_NUM_8723D	0x04CB
+#define REG_BAR_MODE_CTRL_8723D		0x04CC
+#define REG_RA_TRY_RATE_AGG_LMT_8723D	0x04CF
+#define REG_MACID_PKT_DROP0_8723D		0x04D0
+#define REG_MACID_PKT_SLEEP_8723D		0x04D4
+
+/* -----------------------------------------------------
+ *
+ *	0x0500h ~ 0x05FFh	EDCA Configuration
+ *
+ * ----------------------------------------------------- */
+#define REG_EDCA_VO_PARAM_8723D		0x0500
+#define REG_EDCA_VI_PARAM_8723D		0x0504
+#define REG_EDCA_BE_PARAM_8723D		0x0508
+#define REG_EDCA_BK_PARAM_8723D		0x050C
+#define REG_BCNTCFG_8723D				0x0510
+#define REG_PIFS_8723D					0x0512
+#define REG_RDG_PIFS_8723D				0x0513
+#define REG_SIFS_CTX_8723D				0x0514
+#define REG_SIFS_TRX_8723D				0x0516
+#define REG_AGGR_BREAK_TIME_8723D		0x051A
+#define REG_SLOT_8723D					0x051B
+#define REG_TX_PTCL_CTRL_8723D			0x0520
+#define REG_TXPAUSE_8723D				0x0522
+#define REG_DIS_TXREQ_CLR_8723D		0x0523
+#define REG_RD_CTRL_8723D				0x0524
+/*
+ * Format for offset 540h-542h:
+ *	[3:0]:   TBTT prohibit setup in unit of 32us. The time for HW getting beacon content before TBTT.
+ *	[7:4]:   Reserved.
+ *	[19:8]:  TBTT prohibit hold in unit of 32us. The time for HW holding to send the beacon packet.
+ *	[23:20]: Reserved
+ * Description:
+ *	              |
+ * |<--Setup--|--Hold------------>|
+ *	--------------|----------------------
+ * |
+ * TBTT
+ * Note: We cannot update beacon content to HW or send any AC packets during the time between Setup and Hold.
+ * Described by Designer Tim and Bruce, 2011-01-14.
+ *   */
+#define REG_TBTT_PROHIBIT_8723D			0x0540
+#define REG_RD_NAV_NXT_8723D			0x0544
+#define REG_NAV_PROT_LEN_8723D			0x0546
+#define REG_BCN_CTRL_8723D				0x0550
+#define REG_BCN_CTRL_1_8723D			0x0551
+#define REG_MBID_NUM_8723D				0x0552
+#define REG_DUAL_TSF_RST_8723D			0x0553
+#define REG_BCN_INTERVAL_8723D			0x0554
+#define REG_DRVERLYINT_8723D			0x0558
+#define REG_BCNDMATIM_8723D			0x0559
+#define REG_ATIMWND_8723D				0x055A
+#define REG_USTIME_TSF_8723D			0x055C
+#define REG_BCN_MAX_ERR_8723D			0x055D
+#define REG_RXTSF_OFFSET_CCK_8723D		0x055E
+#define REG_RXTSF_OFFSET_OFDM_8723D	0x055F
+#define REG_TSFTR_8723D					0x0560
+#define REG_CTWND_8723D					0x0572
+#define REG_SECONDARY_CCA_CTRL_8723D	0x0577
+#define REG_PSTIMER_8723D				0x0580
+#define REG_TIMER0_8723D				0x0584
+#define REG_TIMER1_8723D				0x0588
+#define REG_ACMHWCTRL_8723D			0x05C0
+#define REG_SCH_TXCMD_8723D			0x05F8
+
+/* -----------------------------------------------------
+ *
+ *	0x0600h ~ 0x07FFh	WMAC Configuration
+ *
+ * ----------------------------------------------------- */
+#define REG_MAC_CR_8723D				0x0600
+#define REG_TCR_8723D					0x0604
+#define REG_RCR_8723D					0x0608
+#define REG_RX_PKT_LIMIT_8723D			0x060C
+#define REG_RX_DLK_TIME_8723D			0x060D
+#define REG_RX_DRVINFO_SZ_8723D		0x060F
+
+#define REG_MACID_8723D					0x0610
+#define REG_BSSID_8723D					0x0618
+#define REG_MAR_8723D					0x0620
+#define REG_MBIDCAMCFG_8723D			0x0628
+#define REG_WOWLAN_GTK_DBG1	0x630
+#define REG_WOWLAN_GTK_DBG2	0x634
+
+#define REG_USTIME_EDCA_8723D			0x0638
+#define REG_MAC_SPEC_SIFS_8723D		0x063A
+#define REG_RESP_SIFP_CCK_8723D			0x063C
+#define REG_RESP_SIFS_OFDM_8723D		0x063E
+#define REG_ACKTO_8723D					0x0640
+#define REG_CTS2TO_8723D				0x0641
+#define REG_EIFS_8723D					0x0642
+
+#define REG_NAV_UPPER_8723D			0x0652	/* unit of 128 */
+#define REG_TRXPTCL_CTL_8723D			0x0668
+
+/* Security */
+#define REG_CAMCMD_8723D				0x0670
+#define REG_CAMWRITE_8723D				0x0674
+#define REG_CAMREAD_8723D				0x0678
+#define REG_CAMDBG_8723D				0x067C
+#define REG_SECCFG_8723D				0x0680
+
+/* Power */
+#define REG_WOW_CTRL_8723D				0x0690
+#define REG_PS_RX_INFO_8723D			0x0692
+#define REG_UAPSD_TID_8723D				0x0693
+#define REG_WKFMCAM_CMD_8723D			0x0698
+#define REG_WKFMCAM_NUM_8723D			0x0698
+#define REG_WKFMCAM_RWD_8723D			0x069C
+#define REG_RXFLTMAP0_8723D				0x06A0
+#define REG_RXFLTMAP1_8723D				0x06A2
+#define REG_RXFLTMAP2_8723D				0x06A4
+#define REG_BCN_PSR_RPT_8723D			0x06A8
+#define REG_BT_COEX_TABLE_8723D		0x06C0
+#define REG_BFMER0_INFO_8723D			0x06E4
+#define REG_BFMER1_INFO_8723D			0x06EC
+#define REG_CSI_RPT_PARAM_BW20_8723D	0x06F4
+#define REG_CSI_RPT_PARAM_BW40_8723D	0x06F8
+#define REG_CSI_RPT_PARAM_BW80_8723D	0x06FC
+
+/* Hardware Port 2 */
+#define REG_MACID1_8723D				0x0700
+#define REG_BSSID1_8723D				0x0708
+#define REG_BFMEE_SEL_8723D				0x0714
+#define REG_SND_PTCL_CTRL_8723D		0x0718
+
+/* LTR */
+#define REG_LTR_CTRL_BASIC_8723D		0x07A4
+#define REG_LTR_IDLE_LATENCY_V1_8723D		0x0798
+#define REG_LTR_ACTIVE_LATENCY_V1_8723D		0x079C
+
+/* LTE_COEX */
+#define REG_LTECOEX_CTRL			0x07C0
+#define REG_LTECOEX_WRITE_DATA		0x07C4
+#define REG_LTECOEX_READ_DATA		0x07C8
+#define REG_LTECOEX_PATH_CONTROL	0x70
+
+/* ************************************************************
+ * SDIO Bus Specification
+ * ************************************************************ */
+
+/* -----------------------------------------------------
+ * SDIO CMD Address Mapping
+ * ----------------------------------------------------- */
+
+/* -----------------------------------------------------
+ * I/O bus domain (Host)
+ * ----------------------------------------------------- */
+
+/* -----------------------------------------------------
+ * SDIO register
+ * ----------------------------------------------------- */
+#define SDIO_REG_HCPWM1_8723D	0x025 /* HCI Current Power Mode 1 */
+
+
+/* ****************************************************************************
+ *	8723 Regsiter Bit and Content definition
+ * **************************************************************************** */
+
+#define BIT_USB_RXDMA_AGG_EN	BIT(31)
+#define RXDMA_AGG_MODE_EN		BIT(1)
+
+#ifdef CONFIG_WOWLAN
+	#define RXPKT_RELEASE_POLL		BIT(16)
+	#define RXDMA_IDLE				BIT(17)
+	#define RW_RELEASE_EN			BIT(18)
+#endif
+
+/* 2 HSISR
+ * interrupt mask which needs to clear */
+#define MASK_HSISR_CLEAR		(HSISR_GPIO12_0_INT |\
+		HSISR_SPS_OCP_INT |\
+		HSISR_RON_INT |\
+		HSISR_PDNINT |\
+		HSISR_GPIO9_INT)
+
+#ifdef CONFIG_RF_POWER_TRIM
+	#ifdef CONFIG_RTL8723D
+		#define EEPROM_RF_GAIN_OFFSET			0xC1
+	#endif
+
+	#define EEPROM_RF_GAIN_VAL				0x1F6
+#endif /*CONFIG_RF_POWER_TRIM*/
+
+#ifdef CONFIG_PCI_HCI
+	/* #define IMR_RX_MASK		(IMR_ROK_8723D|IMR_RDU_8723D|IMR_RXFOVW_8723D) */
+	#define IMR_TX_MASK			(IMR_VODOK_8723D | IMR_VIDOK_8723D | IMR_BEDOK_8723D | IMR_BKDOK_8723D | IMR_MGNTDOK_8723D | IMR_HIGHDOK_8723D)
+
+	#define RT_BCN_INT_MASKS	(IMR_BCNDMAINT0_8723D | IMR_TXBCN0OK_8723D | IMR_TXBCN0ERR_8723D | IMR_BCNDERR0_8723D)
+
+	#define RT_AC_INT_MASKS	(IMR_VIDOK_8723D | IMR_VODOK_8723D | IMR_BEDOK_8723D | IMR_BKDOK_8723D)
+#endif
+
+#endif /* __RTL8723D_SPEC_H__ */
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/include/rtl8723d_sreset.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/rtl8723d_sreset.h
--- linux-5.6.3/3rdparty/rtl8821ce/include/rtl8723d_sreset.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/rtl8723d_sreset.h	2020-04-10 16:35:06.850661655 +0300
@@ -0,0 +1,24 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#ifndef _RTL8723D_SRESET_H_
+#define _RTL8723D_SRESET_H_
+
+#include <rtw_sreset.h>
+
+#ifdef DBG_CONFIG_ERROR_DETECT
+	extern void rtl8723d_sreset_xmit_status_check(_adapter *padapter);
+	extern void rtl8723d_sreset_linked_status_check(_adapter *padapter);
+#endif
+#endif
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/include/rtl8723d_xmit.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/rtl8723d_xmit.h
--- linux-5.6.3/3rdparty/rtl8821ce/include/rtl8723d_xmit.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/rtl8723d_xmit.h	2020-04-10 16:35:06.850661655 +0300
@@ -0,0 +1,523 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#ifndef __RTL8723D_XMIT_H__
+#define __RTL8723D_XMIT_H__
+
+
+#define MAX_TID (15)
+
+
+#ifndef __INC_HAL8723DDESC_H
+#define __INC_HAL8723DDESC_H
+
+#define RX_STATUS_DESC_SIZE_8723D		24
+#define RX_DRV_INFO_SIZE_UNIT_8723D 8
+
+
+/* DWORD 0 */
+#define SET_RX_STATUS_DESC_PKT_LEN_8723D(__pRxStatusDesc, __Value) \
+	SET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 0, 14, __Value)
+#define SET_RX_STATUS_DESC_EOR_8723D(__pRxStatusDesc, __Value) \
+	SET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 30, 1, __Value)
+#define SET_RX_STATUS_DESC_OWN_8723D(__pRxStatusDesc, __Value) \
+	SET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 31, 1, __Value)
+
+#define GET_RX_STATUS_DESC_PKT_LEN_8723D(__pRxStatusDesc) \
+	LE_BITS_TO_4BYTE(__pRxStatusDesc, 0, 14)
+#define GET_RX_STATUS_DESC_CRC32_8723D(__pRxStatusDesc) \
+	LE_BITS_TO_4BYTE(__pRxStatusDesc, 14, 1)
+#define GET_RX_STATUS_DESC_ICV_8723D(__pRxStatusDesc) \
+	LE_BITS_TO_4BYTE(__pRxStatusDesc, 15, 1)
+#define GET_RX_STATUS_DESC_DRVINFO_SIZE_8723D(__pRxStatusDesc) \
+	LE_BITS_TO_4BYTE(__pRxStatusDesc, 16, 4)
+#define GET_RX_STATUS_DESC_SECURITY_8723D(__pRxStatusDesc) \
+	LE_BITS_TO_4BYTE(__pRxStatusDesc, 20, 3)
+#define GET_RX_STATUS_DESC_QOS_8723D(__pRxStatusDesc) \
+	LE_BITS_TO_4BYTE(__pRxStatusDesc, 23, 1)
+#define GET_RX_STATUS_DESC_SHIFT_8723D(__pRxStatusDesc) \
+	LE_BITS_TO_4BYTE(__pRxStatusDesc, 24, 2)
+#define GET_RX_STATUS_DESC_PHY_STATUS_8723D(__pRxStatusDesc) \
+	LE_BITS_TO_4BYTE(__pRxStatusDesc, 26, 1)
+#define GET_RX_STATUS_DESC_SWDEC_8723D(__pRxStatusDesc) \
+	LE_BITS_TO_4BYTE(__pRxStatusDesc, 27, 1)
+#define GET_RX_STATUS_DESC_EOR_8723D(__pRxStatusDesc) \
+	LE_BITS_TO_4BYTE(__pRxStatusDesc, 30, 1)
+#define GET_RX_STATUS_DESC_OWN_8723D(__pRxStatusDesc) \
+	LE_BITS_TO_4BYTE(__pRxStatusDesc, 31, 1)
+
+/* DWORD 1 */
+#define GET_RX_STATUS_DESC_MACID_8723D(__pRxDesc) \
+	LE_BITS_TO_4BYTE(__pRxDesc+4, 0, 7)
+#define GET_RX_STATUS_DESC_TID_8723D(__pRxDesc) \
+	LE_BITS_TO_4BYTE(__pRxDesc+4, 8, 4)
+#define GET_RX_STATUS_DESC_AMSDU_8723D(__pRxDesc) \
+	LE_BITS_TO_4BYTE(__pRxDesc+4, 13, 1)
+#define GET_RX_STATUS_DESC_RXID_MATCH_8723D(__pRxDesc) \
+	LE_BITS_TO_4BYTE(__pRxDesc+4, 14, 1)
+#define GET_RX_STATUS_DESC_PAGGR_8723D(__pRxDesc) \
+	LE_BITS_TO_4BYTE(__pRxDesc+4, 15, 1)
+#define GET_RX_STATUS_DESC_A1_FIT_8723D(__pRxDesc) \
+	LE_BITS_TO_4BYTE(__pRxDesc+4, 16, 4)
+#define GET_RX_STATUS_DESC_CHKERR_8723D(__pRxDesc) \
+	LE_BITS_TO_4BYTE(__pRxDesc+4, 20, 1)
+#define GET_RX_STATUS_DESC_IPVER_8723D(__pRxDesc) \
+	LE_BITS_TO_4BYTE(__pRxDesc+4, 21, 1)
+#define GET_RX_STATUS_DESC_IS_TCPUDP__8723D(__pRxDesc) \
+	LE_BITS_TO_4BYTE(__pRxDesc+4, 22, 1)
+#define GET_RX_STATUS_DESC_CHK_VLD_8723D(__pRxDesc) \
+	LE_BITS_TO_4BYTE(__pRxDesc+4, 23, 1)
+#define GET_RX_STATUS_DESC_PAM_8723D(__pRxDesc) \
+	LE_BITS_TO_4BYTE(__pRxDesc+4, 24, 1)
+#define GET_RX_STATUS_DESC_PWR_8723D(__pRxDesc) \
+	LE_BITS_TO_4BYTE(__pRxDesc+4, 25, 1)
+#define GET_RX_STATUS_DESC_MORE_DATA_8723D(__pRxDesc) \
+	LE_BITS_TO_4BYTE(__pRxDesc+4, 26, 1)
+#define GET_RX_STATUS_DESC_MORE_FRAG_8723D(__pRxDesc) \
+	LE_BITS_TO_4BYTE(__pRxDesc+4, 27, 1)
+#define GET_RX_STATUS_DESC_TYPE_8723D(__pRxDesc) \
+	LE_BITS_TO_4BYTE(__pRxDesc+4, 28, 2)
+#define GET_RX_STATUS_DESC_MC_8723D(__pRxDesc) \
+	LE_BITS_TO_4BYTE(__pRxDesc+4, 30, 1)
+#define GET_RX_STATUS_DESC_BC_8723D(__pRxDesc) \
+	LE_BITS_TO_4BYTE(__pRxDesc+4, 31, 1)
+
+/* DWORD 2 */
+#define GET_RX_STATUS_DESC_SEQ_8723D(__pRxStatusDesc) \
+	LE_BITS_TO_4BYTE(__pRxStatusDesc+8, 0, 12)
+#define GET_RX_STATUS_DESC_FRAG_8723D(__pRxStatusDesc) \
+	LE_BITS_TO_4BYTE(__pRxStatusDesc+8, 12, 4)
+#define GET_RX_STATUS_DESC_RX_IS_QOS_8723D(__pRxStatusDesc) \
+	LE_BITS_TO_4BYTE(__pRxStatusDesc+8, 16, 1)
+#define GET_RX_STATUS_DESC_WLANHD_IV_LEN_8723D(__pRxStatusDesc) \
+	LE_BITS_TO_4BYTE(__pRxStatusDesc+8, 18, 6)
+#define GET_RX_STATUS_DESC_RPT_SEL_8723D(__pRxStatusDesc) \
+	LE_BITS_TO_4BYTE(__pRxStatusDesc+8, 28, 1)
+#define GET_RX_STATUS_DESC_FCS_OK_8723D(__pRxStatusDesc) \
+	LE_BITS_TO_4BYTE(__pRxStatusDesc+8, 31, 1)
+
+/* DWORD 3 */
+#define GET_RX_STATUS_DESC_RX_RATE_8723D(__pRxStatusDesc) \
+	LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 0, 7)
+#define GET_RX_STATUS_DESC_HTC_8723D(__pRxStatusDesc) \
+	LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 10, 1)
+#define GET_RX_STATUS_DESC_EOSP_8723D(__pRxStatusDesc) \
+	LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 11, 1)
+#define GET_RX_STATUS_DESC_BSSID_FIT_8723D(__pRxStatusDesc) \
+	LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 12, 2)
+#ifdef CONFIG_USB_RX_AGGREGATION
+#define GET_RX_STATUS_DESC_USB_AGG_PKTNUM_8723D(__pRxStatusDesc) \
+	LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 16, 8)
+#endif
+#define GET_RX_STATUS_DESC_PATTERN_MATCH_8723D(__pRxDesc) \
+	LE_BITS_TO_4BYTE(__pRxDesc+12, 29, 1)
+#define GET_RX_STATUS_DESC_UNICAST_MATCH_8723D(__pRxDesc) \
+	LE_BITS_TO_4BYTE(__pRxDesc+12, 30, 1)
+#define GET_RX_STATUS_DESC_MAGIC_MATCH_8723D(__pRxDesc) \
+	LE_BITS_TO_4BYTE(__pRxDesc+12, 31, 1)
+
+/* DWORD 6 */
+#define GET_RX_STATUS_DESC_MATCH_ID_8723D(__pRxDesc) \
+	LE_BITS_TO_4BYTE(__pRxDesc+16, 0, 7)
+
+/* DWORD 5 */
+#define GET_RX_STATUS_DESC_TSFL_8723D(__pRxStatusDesc) \
+	LE_BITS_TO_4BYTE(__pRxStatusDesc+20, 0, 32)
+
+#define GET_RX_STATUS_DESC_BUFF_ADDR_8723D(__pRxDesc) \
+	LE_BITS_TO_4BYTE(__pRxDesc+24, 0, 32)
+#define GET_RX_STATUS_DESC_BUFF_ADDR64_8723D(__pRxDesc) \
+	LE_BITS_TO_4BYTE(__pRxDesc+28, 0, 32)
+
+#define SET_RX_STATUS_DESC_BUFF_ADDR_8723D(__pRxDesc, __Value) \
+	SET_BITS_TO_LE_4BYTE(__pRxDesc+24, 0, 32, __Value)
+
+
+/* Dword 0, rsvd: bit26, bit28 */
+#define GET_TX_DESC_OWN_8723D(__pTxDesc)\
+	LE_BITS_TO_4BYTE(__pTxDesc, 31, 1)
+
+#define SET_TX_DESC_PKT_SIZE_8723D(__pTxDesc, __Value) \
+	SET_BITS_TO_LE_4BYTE(__pTxDesc, 0, 16, __Value)
+#define SET_TX_DESC_OFFSET_8723D(__pTxDesc, __Value) \
+	SET_BITS_TO_LE_4BYTE(__pTxDesc, 16, 8, __Value)
+#define SET_TX_DESC_BMC_8723D(__pTxDesc, __Value) \
+	SET_BITS_TO_LE_4BYTE(__pTxDesc, 24, 1, __Value)
+#define SET_TX_DESC_HTC_8723D(__pTxDesc, __Value) \
+	SET_BITS_TO_LE_4BYTE(__pTxDesc, 25, 1, __Value)
+#define SET_TX_DESC_AMSDU_PAD_EN_8723D(__pTxDesc, __Value) \
+	SET_BITS_TO_LE_4BYTE(__pTxDesc, 27, 1, __Value)
+#define SET_TX_DESC_NO_ACM_8723D(__pTxDesc, __Value) \
+	SET_BITS_TO_LE_4BYTE(__pTxDesc, 29, 1, __Value)
+#define SET_TX_DESC_GF_8723D(__pTxDesc, __Value) \
+	SET_BITS_TO_LE_4BYTE(__pTxDesc, 30, 1, __Value)
+
+/* Dword 1 */
+#define SET_TX_DESC_MACID_8723D(__pTxDesc, __Value) \
+	SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 0, 7, __Value)
+#define SET_TX_DESC_QUEUE_SEL_8723D(__pTxDesc, __Value) \
+	SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 8, 5, __Value)
+#define SET_TX_DESC_RDG_NAV_EXT_8723D(__pTxDesc, __Value) \
+	SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 13, 1, __Value)
+#define SET_TX_DESC_LSIG_TXOP_EN_8723D(__pTxDesc, __Value) \
+	SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 14, 1, __Value)
+#define SET_TX_DESC_PIFS_8723D(__pTxDesc, __Value) \
+	SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 15, 1, __Value)
+#define SET_TX_DESC_RATE_ID_8723D(__pTxDesc, __Value) \
+	SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 16, 5, __Value)
+#define SET_TX_DESC_EN_DESC_ID_8723D(__pTxDesc, __Value) \
+	SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 21, 1, __Value)
+#define SET_TX_DESC_SEC_TYPE_8723D(__pTxDesc, __Value) \
+	SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 22, 2, __Value)
+#define SET_TX_DESC_PKT_OFFSET_8723D(__pTxDesc, __Value) \
+	SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 24, 5, __Value)
+#define SET_TX_DESC_MORE_DATA_8723D(__pTxDesc, __Value) \
+	SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 29, 1, __Value)
+
+/* Dword 2  remove P_AID, G_ID field*/
+#define SET_TX_DESC_CCA_RTS_8723D(__pTxDesc, __Value) \
+	SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 10, 2, __Value)
+#define SET_TX_DESC_AGG_ENABLE_8723D(__pTxDesc, __Value) \
+	SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 12, 1, __Value)
+#define SET_TX_DESC_RDG_ENABLE_8723D(__pTxDesc, __Value) \
+	SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 13, 1, __Value)
+#define SET_TX_DESC_NULL0_8723D(__pTxDesc, __Value) \
+	SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 14, 1, __Value)
+#define SET_TX_DESC_NULL1_8723D(__pTxDesc, __Value) \
+	SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 15, 1, __Value)
+#define SET_TX_DESC_BK_8723D(__pTxDesc, __Value) \
+	SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 16, 1, __Value)
+#define SET_TX_DESC_MORE_FRAG_8723D(__pTxDesc, __Value) \
+	SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 17, 1, __Value)
+#define SET_TX_DESC_RAW_8723D(__pTxDesc, __Value) \
+	SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 18, 1, __Value)
+#define SET_TX_DESC_CCX_8723D(__pTxDesc, __Value) \
+	SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 19, 1, __Value)
+#define SET_TX_DESC_AMPDU_DENSITY_8723D(__pTxDesc, __Value) \
+	SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 20, 3, __Value)
+#define SET_TX_DESC_BT_INT_8723D(__pTxDesc, __Value) \
+	SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 23, 1, __Value)
+#define SET_TX_DESC_FTM_EN_8723D(__pTxDesc, __Value) \
+	SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 30, 1, __Value)
+
+/* Dword 3 */
+#define SET_TX_DESC_HWSEQ_SEL_8723D(__pTxDesc, __Value) \
+	SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 6, 2, __Value)
+#define SET_TX_DESC_USE_RATE_8723D(__pTxDesc, __Value) \
+	SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 8, 1, __Value)
+#define SET_TX_DESC_DISABLE_RTS_FB_8723D(__pTxDesc, __Value) \
+	SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 9, 1, __Value)
+#define SET_TX_DESC_DISABLE_FB_8723D(__pTxDesc, __Value) \
+	SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 10, 1, __Value)
+#define SET_TX_DESC_CTS2SELF_8723D(__pTxDesc, __Value) \
+	SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 11, 1, __Value)
+#define SET_TX_DESC_RTS_ENABLE_8723D(__pTxDesc, __Value) \
+	SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 12, 1, __Value)
+#define SET_TX_DESC_HW_RTS_ENABLE_8723D(__pTxDesc, __Value) \
+	SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 13, 1, __Value)
+#define SET_TX_DESC_PORT_ID_8723D(__pTxDesc, __Value) \
+	SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 14, 2, __Value)
+#define SET_TX_DESC_NAV_USE_HDR_8723D(__pTxDesc, __Value) \
+	SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 15, 1, __Value)
+#define SET_TX_DESC_USE_MAX_LEN_8723D(__pTxDesc, __Value) \
+	SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 16, 1, __Value)
+#define SET_TX_DESC_MAX_AGG_NUM_8723D(__pTxDesc, __Value) \
+	SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 17, 5, __Value)
+#define SET_TX_DESC_AMPDU_MAX_TIME_8723D(__pTxDesc, __Value) \
+	SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 24, 8, __Value)
+
+/* Dword 4 */
+#define SET_TX_DESC_TX_RATE_8723D(__pTxDesc, __Value) \
+	SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 0, 7, __Value)
+#define SET_TX_DESC_TX_TRY_RATE_8723D(__pTxDesc, __Value) \
+	SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 7, 1, __Value)
+#define SET_TX_DESC_DATA_RATE_FB_LIMIT_8723D(__pTxDesc, __Value) \
+	SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 8, 5, __Value)
+#define SET_TX_DESC_RTS_RATE_FB_LIMIT_8723D(__pTxDesc, __Value) \
+	SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 13, 4, __Value)
+#define SET_TX_DESC_RETRY_LIMIT_ENABLE_8723D(__pTxDesc, __Value) \
+	SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 17, 1, __Value)
+#define SET_TX_DESC_DATA_RETRY_LIMIT_8723D(__pTxDesc, __Value) \
+	SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 18, 6, __Value)
+#define SET_TX_DESC_RTS_RATE_8723D(__pTxDesc, __Value) \
+	SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 24, 5, __Value)
+#define SET_TX_DESC_PCTS_EN_8723D(__pTxDesc, __Value) \
+	SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 29, 1, __Value)
+#define SET_TX_DESC_PCTS_MASK_IDX_8723D(__pTxDesc, __Value) \
+	SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 30, 2, __Value)
+
+/* Dword 5 */
+#define SET_TX_DESC_DATA_SC_8723D(__pTxDesc, __Value) \
+	SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 0, 4, __Value)
+#define SET_TX_DESC_DATA_SHORT_8723D(__pTxDesc, __Value) \
+	SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 4, 1, __Value)
+#define SET_TX_DESC_DATA_BW_8723D(__pTxDesc, __Value) \
+	SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 5, 2, __Value)
+#define SET_TX_DESC_DATA_STBC_8723D(__pTxDesc, __Value) \
+	SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 8, 2, __Value)
+#define SET_TX_DESC_RTS_STBC_8723D(__pTxDesc, __Value) \
+	SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 10, 2, __Value)
+#define SET_TX_DESC_RTS_SHORT_8723D(__pTxDesc, __Value) \
+	SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 12, 1, __Value)
+#define SET_TX_DESC_RTS_SC_8723D(__pTxDesc, __Value) \
+	SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 13, 4, __Value)
+#define SET_TX_DESC_PATH_A_EN_8723D(__pTxDesc, __Value) \
+	SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 24, 1, __Value)
+#define SET_TX_DESC_TXPWR_OF_SET_8723D(__pTxDesc, __Value) \
+	SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 28, 3, __Value)
+
+/* Dword 6 */
+#define SET_TX_DESC_SW_DEFINE_8723D(__pTxDesc, __Value) \
+	SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 0, 12, __Value)
+#define SET_TX_DESC_MBSSID_8723D(__pTxDesc, __Value) \
+	SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 12, 4, __Value)
+#define SET_TX_DESC_RF_SEL_8723D(__pTxDesc, __Value) \
+	SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 16, 3, __Value)
+
+/* Dword 7 */
+#ifdef CONFIG_PCI_HCI
+#define SET_TX_DESC_TX_BUFFER_SIZE_8723D(__pTxDesc, __Value) \
+	SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 0, 16, __Value)
+#endif
+
+#ifdef CONFIG_USB_HCI
+#define SET_TX_DESC_TX_DESC_CHECKSUM_8723D(__pTxDesc, __Value) \
+	SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 0, 16, __Value)
+#endif
+
+#ifdef CONFIG_SDIO_HCI
+#define SET_TX_DESC_TX_TIMESTAMP_8723D(__pTxDesc, __Value) \
+	SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 6, 18, __Value)
+#endif
+
+#define SET_TX_DESC_USB_TXAGG_NUM_8723D(__pTxDesc, __Value) \
+	SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 24, 8, __Value)
+
+/* Dword 8 */
+#define SET_TX_DESC_RTS_RC_8723D(__pTxDesc, __Value) \
+	SET_BITS_TO_LE_4BYTE(__pTxDesc+32, 0, 6, __Value)
+#define SET_TX_DESC_BAR_RC_8723D(__pTxDesc, __Value) \
+	SET_BITS_TO_LE_4BYTE(__pTxDesc+32, 6, 2, __Value)
+#define SET_TX_DESC_DATA_RC_8723D(__pTxDesc, __Value) \
+	SET_BITS_TO_LE_4BYTE(__pTxDesc+32, 8, 6, __Value)
+#define SET_TX_DESC_HWSEQ_EN_8723D(__pTxDesc, __Value) \
+	SET_BITS_TO_LE_4BYTE(__pTxDesc+32, 15, 1, __Value)
+#define SET_TX_DESC_NEXTHEADPAGE_8723D(__pTxDesc, __Value) \
+	SET_BITS_TO_LE_4BYTE(__pTxDesc+32, 16, 8, __Value)
+#define SET_TX_DESC_TAILPAGE_8723D(__pTxDesc, __Value) \
+	SET_BITS_TO_LE_4BYTE(__pTxDesc+32, 24, 8, __Value)
+
+/* Dword 9 */
+#define SET_TX_DESC_PADDING_LEN_8723D(__pTxDesc, __Value) \
+	SET_BITS_TO_LE_4BYTE(__pTxDesc+36, 0, 11, __Value)
+#define SET_TX_DESC_SEQ_8723D(__pTxDesc, __Value) \
+	SET_BITS_TO_LE_4BYTE(__pTxDesc+36, 12, 12, __Value)
+#define SET_TX_DESC_FINAL_DATA_RATE_8723D(__pTxDesc, __Value) \
+	SET_BITS_TO_LE_4BYTE(__pTxDesc+36, 24, 8, __Value)
+
+
+#define SET_EARLYMODE_PKTNUM_8723D(__pAddr, __Value)					SET_BITS_TO_LE_4BYTE(__pAddr, 0, 4, __Value)
+#define SET_EARLYMODE_LEN0_8723D(__pAddr, __Value)					SET_BITS_TO_LE_4BYTE(__pAddr, 4, 15, __Value)
+#define SET_EARLYMODE_LEN1_1_8723D(__pAddr, __Value)					SET_BITS_TO_LE_4BYTE(__pAddr, 19, 13, __Value)
+#define SET_EARLYMODE_LEN1_2_8723D(__pAddr, __Value)					SET_BITS_TO_LE_4BYTE(__pAddr+4, 0, 2, __Value)
+#define SET_EARLYMODE_LEN2_8723D(__pAddr, __Value)					SET_BITS_TO_LE_4BYTE(__pAddr+4, 2, 15,	__Value)
+#define SET_EARLYMODE_LEN3_8723D(__pAddr, __Value)					SET_BITS_TO_LE_4BYTE(__pAddr+4, 17, 15, __Value)
+
+
+/*-----------------------------------------------------------------*/
+/*	RTL8723D TX BUFFER DESC                                      */
+/*-----------------------------------------------------------------*/
+#ifdef CONFIG_64BIT_DMA
+	#define SET_TXBUFFER_DESC_LEN_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc+((__Offset)*16), 0, 16, __Valeu)
+	#define SET_TXBUFFER_DESC_AMSDU_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc+((__Offset)*16), 31, 1, __Valeu)
+	#define SET_TXBUFFER_DESC_ADD_LOW_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc+((__Offset)*16)+4, 0, 32, __Valeu)
+	#define SET_TXBUFFER_DESC_ADD_HIGT_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc+((__Offset)*16)+8, 0, 32, __Valeu)
+#else
+	#define SET_TXBUFFER_DESC_LEN_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc+(__Offset*8), 0, 16, __Valeu)
+	#define SET_TXBUFFER_DESC_AMSDU_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc+(__Offset*8), 31, 1, __Valeu)
+	#define SET_TXBUFFER_DESC_ADD_LOW_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc+(__Offset*8)+4, 0, 32, __Valeu)
+	#define SET_TXBUFFER_DESC_ADD_HIGT_WITH_OFFSET(__pTxDesc, __Offset, __Valeu)	/* 64 BIT mode only */
+#endif
+/* ********************************************************* */
+
+/* 64 bits  -- 32 bits */
+/* =======     ======= */
+/* Dword 0     0 */
+#define SET_TX_BUFF_DESC_LEN_0_8723D(__pTxDesc, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc, 0, 14, __Valeu)
+#define SET_TX_BUFF_DESC_PSB_8723D(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 16, 15, __Value)
+#define SET_TX_BUFF_DESC_OWN_8723D(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 31, 1, __Value)
+
+/* Dword 1     1 */
+#define SET_TX_BUFF_DESC_ADDR_LOW_0_8723D(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 0, 32, __Value)
+#define GET_TX_BUFF_DESC_ADDR_LOW_0_8723D(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc+4, 0, 32)
+/* Dword 2     NA */
+#define SET_TX_BUFF_DESC_ADDR_HIGH_0_8723D(__pTxDesc, __Value) SET_TXBUFFER_DESC_ADD_HIGT_WITH_OFFSET(__pTxDesc, 0, __Value)
+#ifdef CONFIG_64BIT_DMA
+	#define GET_TX_BUFF_DESC_ADDR_HIGH_0_8723D(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc+8, 0, 32)
+#else
+	#define GET_TX_BUFF_DESC_ADDR_HIGH_0_8723D(__pTxDesc) 0
+#endif
+/* Dword 3     NA */
+/* RESERVED 0 */
+/* Dword 4     2 */
+#define SET_TX_BUFF_DESC_LEN_1_8723D(__pTxDesc, __Value) SET_TXBUFFER_DESC_LEN_WITH_OFFSET(__pTxDesc, 1, __Value)
+#define SET_TX_BUFF_DESC_AMSDU_1_8723D(__pTxDesc, __Value) SET_TXBUFFER_DESC_AMSDU_WITH_OFFSET(__pTxDesc, 1, __Value)
+/* Dword 5     3 */
+#define SET_TX_BUFF_DESC_ADDR_LOW_1_8723D(__pTxDesc, __Value) SET_TXBUFFER_DESC_ADD_LOW_WITH_OFFSET(__pTxDesc, 1, __Value)
+/* Dword 6     NA */
+#define SET_TX_BUFF_DESC_ADDR_HIGH_1_8723D(__pTxDesc, __Value) SET_TXBUFFER_DESC_ADD_HIGT_WITH_OFFSET(__pTxDesc, 1, __Value)
+/* Dword 7     NA */
+/*RESERVED 0 */
+/* Dword 8     4 */
+#define SET_TX_BUFF_DESC_LEN_2_8723D(__pTxDesc, __Value) SET_TXBUFFER_DESC_LEN_WITH_OFFSET(__pTxDesc, 2, __Value)
+#define SET_TX_BUFF_DESC_AMSDU_2_8723D(__pTxDesc, __Value) SET_TXBUFFER_DESC_AMSDU_WITH_OFFSET(__pTxDesc, 2, __Value)
+/* Dword 9     5 */
+#define SET_TX_BUFF_DESC_ADDR_LOW_2_8723D(__pTxDesc, __Value) SET_TXBUFFER_DESC_ADD_LOW_WITH_OFFSET(__pTxDesc, 2, __Value)
+/* Dword 10    NA */
+#define SET_TX_BUFF_DESC_ADDR_HIGH_2_8723D(__pTxDesc, __Value) SET_TXBUFFER_DESC_ADD_HIGT_WITH_OFFSET(__pTxDesc, 2, __Value)
+/* Dword 11    NA */
+/*RESERVED 0 */
+/* Dword 12    6 */
+#define SET_TX_BUFF_DESC_LEN_3_8723D(__pTxDesc, __Value) SET_TXBUFFER_DESC_LEN_WITH_OFFSET(__pTxDesc, 3, __Value)
+#define SET_TX_BUFF_DESC_AMSDU_3_8723D(__pTxDesc, __Value) SET_TXBUFFER_DESC_AMSDU_WITH_OFFSET(__pTxDesc, 3, __Value)
+/* Dword 13    7 */
+#define SET_TX_BUFF_DESC_ADDR_LOW_3_8723D(__pTxDesc, __Value) SET_TXBUFFER_DESC_ADD_LOW_WITH_OFFSET(__pTxDesc, 3, __Value)
+/* Dword 14    NA */
+#define SET_TX_BUFF_DESC_ADDR_HIGH_3_8723D(__pTxDesc, __Value) SET_TXBUFFER_DESC_ADD_HIGT_WITH_OFFSET(__pTxDesc, 3, __Value)
+/* Dword 15    NA */
+/*RESERVED 0 */
+
+
+#endif
+/* -----------------------------------------------------------
+ *
+ *	Rate
+ *
+ * -----------------------------------------------------------
+ * CCK Rates, TxHT = 0 */
+#define DESC8723D_RATE1M				0x00
+#define DESC8723D_RATE2M				0x01
+#define DESC8723D_RATE5_5M				0x02
+#define DESC8723D_RATE11M				0x03
+
+/* OFDM Rates, TxHT = 0 */
+#define DESC8723D_RATE6M				0x04
+#define DESC8723D_RATE9M				0x05
+#define DESC8723D_RATE12M				0x06
+#define DESC8723D_RATE18M				0x07
+#define DESC8723D_RATE24M				0x08
+#define DESC8723D_RATE36M				0x09
+#define DESC8723D_RATE48M				0x0a
+#define DESC8723D_RATE54M				0x0b
+
+/* MCS Rates, TxHT = 1 */
+#define DESC8723D_RATEMCS0				0x0c
+#define DESC8723D_RATEMCS1				0x0d
+#define DESC8723D_RATEMCS2				0x0e
+#define DESC8723D_RATEMCS3				0x0f
+#define DESC8723D_RATEMCS4				0x10
+#define DESC8723D_RATEMCS5				0x11
+#define DESC8723D_RATEMCS6				0x12
+#define DESC8723D_RATEMCS7				0x13
+#define DESC8723D_RATEMCS8				0x14
+#define DESC8723D_RATEMCS9				0x15
+#define DESC8723D_RATEMCS10		0x16
+#define DESC8723D_RATEMCS11		0x17
+#define DESC8723D_RATEMCS12		0x18
+#define DESC8723D_RATEMCS13		0x19
+#define DESC8723D_RATEMCS14		0x1a
+#define DESC8723D_RATEMCS15		0x1b
+#define DESC8723D_RATEVHTSS1MCS0		0x2c
+#define DESC8723D_RATEVHTSS1MCS1		0x2d
+#define DESC8723D_RATEVHTSS1MCS2		0x2e
+#define DESC8723D_RATEVHTSS1MCS3		0x2f
+#define DESC8723D_RATEVHTSS1MCS4		0x30
+#define DESC8723D_RATEVHTSS1MCS5		0x31
+#define DESC8723D_RATEVHTSS1MCS6		0x32
+#define DESC8723D_RATEVHTSS1MCS7		0x33
+#define DESC8723D_RATEVHTSS1MCS8		0x34
+#define DESC8723D_RATEVHTSS1MCS9		0x35
+#define DESC8723D_RATEVHTSS2MCS0		0x36
+#define DESC8723D_RATEVHTSS2MCS1		0x37
+#define DESC8723D_RATEVHTSS2MCS2		0x38
+#define DESC8723D_RATEVHTSS2MCS3		0x39
+#define DESC8723D_RATEVHTSS2MCS4		0x3a
+#define DESC8723D_RATEVHTSS2MCS5		0x3b
+#define DESC8723D_RATEVHTSS2MCS6		0x3c
+#define DESC8723D_RATEVHTSS2MCS7		0x3d
+#define DESC8723D_RATEVHTSS2MCS8		0x3e
+#define DESC8723D_RATEVHTSS2MCS9		0x3f
+
+
+#define	RX_HAL_IS_CCK_RATE_8723D(pDesc)\
+	(GET_RX_STATUS_DESC_RX_RATE_8723D(pDesc) == DESC8723D_RATE1M || \
+	 GET_RX_STATUS_DESC_RX_RATE_8723D(pDesc) == DESC8723D_RATE2M || \
+	 GET_RX_STATUS_DESC_RX_RATE_8723D(pDesc) == DESC8723D_RATE5_5M || \
+	 GET_RX_STATUS_DESC_RX_RATE_8723D(pDesc) == DESC8723D_RATE11M)
+
+#ifdef CONFIG_TRX_BD_ARCH
+	struct tx_desc;
+#endif
+
+void rtl8723d_cal_txdesc_chksum(struct tx_desc *ptxdesc);
+void rtl8723d_update_txdesc(struct xmit_frame *pxmitframe, u8 *pmem);
+void rtl8723d_fill_txdesc_sectype(struct pkt_attrib *pattrib, struct tx_desc *ptxdesc);
+void rtl8723d_fill_txdesc_vcs(PADAPTER padapter, struct pkt_attrib *pattrib, struct tx_desc *ptxdesc);
+void rtl8723d_fill_txdesc_phy(PADAPTER padapter, struct pkt_attrib *pattrib, struct tx_desc *ptxdesc);
+void rtl8723d_fill_fake_txdesc(PADAPTER padapter, u8 *pDesc, u32 BufferLen, u8 IsPsPoll, u8 IsBTQosNull, u8 bDataFrame);
+
+#if defined(CONFIG_CONCURRENT_MODE)
+	void fill_txdesc_force_bmc_camid(struct pkt_attrib *pattrib, u8 *ptxdesc);
+#endif
+void fill_txdesc_bmc_tx_rate(struct pkt_attrib *pattrib, u8 *ptxdesc);
+
+#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
+	s32 rtl8723ds_init_xmit_priv(PADAPTER padapter);
+	void rtl8723ds_free_xmit_priv(PADAPTER padapter);
+	s32 rtl8723ds_hal_xmit(PADAPTER padapter, struct xmit_frame *pxmitframe);
+	s32 rtl8723ds_mgnt_xmit(PADAPTER padapter, struct xmit_frame *pmgntframe);
+	s32	rtl8723ds_hal_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe);
+	s32 rtl8723ds_xmit_buf_handler(PADAPTER padapter);
+	thread_return rtl8723ds_xmit_thread(thread_context context);
+	#define hal_xmit_handler rtl8723ds_xmit_buf_handler
+#endif
+
+#ifdef CONFIG_USB_HCI
+	s32 rtl8723du_xmit_buf_handler(PADAPTER padapter);
+	#define hal_xmit_handler rtl8723du_xmit_buf_handler
+	s32 rtl8723du_init_xmit_priv(PADAPTER padapter);
+	void rtl8723du_free_xmit_priv(PADAPTER padapter);
+	s32 rtl8723du_hal_xmit(PADAPTER padapter, struct xmit_frame *pxmitframe);
+	s32 rtl8723du_mgnt_xmit(PADAPTER padapter, struct xmit_frame *pmgntframe);
+	s32	 rtl8723du_hal_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe);
+	void rtl8723du_xmit_tasklet(void *priv);
+	s32 rtl8723du_xmitframe_complete(_adapter *padapter, struct xmit_priv *pxmitpriv, struct xmit_buf *pxmitbuf);
+	void _dbg_dump_tx_info(_adapter	*padapter, int frame_tag, struct tx_desc *ptxdesc);
+#endif
+
+#ifdef CONFIG_PCI_HCI
+	s32 rtl8723de_init_xmit_priv(PADAPTER padapter);
+	void rtl8723de_free_xmit_priv(PADAPTER padapter);
+	struct xmit_buf *rtl8723de_dequeue_xmitbuf(struct rtw_tx_ring *ring);
+	void	rtl8723de_xmitframe_resume(_adapter *padapter);
+	s32 rtl8723de_hal_xmit(PADAPTER padapter, struct xmit_frame *pxmitframe);
+	s32 rtl8723de_mgnt_xmit(PADAPTER padapter, struct xmit_frame *pmgntframe);
+	s32	rtl8723de_hal_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe);
+	void rtl8723de_xmit_tasklet(void *priv);
+#endif
+
+u8	BWMapping_8723D(PADAPTER Adapter, struct pkt_attrib *pattrib);
+u8	SCMapping_8723D(PADAPTER Adapter, struct pkt_attrib	*pattrib);
+
+#endif
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/include/rtl8812a_cmd.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/rtl8812a_cmd.h
--- linux-5.6.3/3rdparty/rtl8821ce/include/rtl8812a_cmd.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/rtl8812a_cmd.h	2020-04-10 16:35:06.850661655 +0300
@@ -0,0 +1,158 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#ifndef __RTL8812A_CMD_H__
+#define __RTL8812A_CMD_H__
+
+typedef enum _RTL8812_H2C_CMD {
+	H2C_8812_RSVDPAGE = 0,
+	H2C_8812_MSRRPT = 1,
+	H2C_8812_SCAN = 2,
+	H2C_8812_KEEP_ALIVE_CTRL = 3,
+	H2C_8812_DISCONNECT_DECISION = 4,
+
+	H2C_8812_INIT_OFFLOAD = 6,
+	H2C_8812_AP_OFFLOAD = 8,
+	H2C_8812_BCN_RSVDPAGE = 9,
+	H2C_8812_PROBERSP_RSVDPAGE = 10,
+
+	H2C_8812_SETPWRMODE = 0x20,
+	H2C_8812_PS_TUNING_PARA = 0x21,
+	H2C_8812_PS_TUNING_PARA2 = 0x22,
+	H2C_8812_PS_LPS_PARA = 0x23,
+	H2C_8812_P2P_PS_OFFLOAD = 0x24,
+	H2C_8812_INACTIVE_PS = 0x27,
+	H2C_8812_RA_MASK = 0x40,
+	H2C_8812_TxBF = 0x41,
+	H2C_8812_RSSI_REPORT = 0x42,
+	H2C_8812_IQ_CALIBRATION = 0x45,
+	H2C_8812_RA_PARA_ADJUST = 0x46,
+
+	H2C_8812_BT_FW_PATCH = 0x6a,
+
+	H2C_8812_WO_WLAN = 0x80,
+	H2C_8812_REMOTE_WAKE_CTRL = 0x81,
+	H2C_8812_AOAC_GLOBAL_INFO = 0x82,
+	H2C_8812_AOAC_RSVDPAGE = 0x83,
+	H2C_8812_FW_SWCHANNL = 0x87,
+
+	H2C_8812_TSF_RESET = 0xC0,
+
+	MAX_8812_H2CCMD
+} RTL8812_H2C_CMD;
+
+struct cmd_msg_parm {
+	u8 eid; /* element id */
+	u8 sz; /* sz */
+	u8 buf[6];
+};
+
+enum {
+	PWRS
+};
+
+struct H2C_SS_RFOFF_PARAM {
+	u8 ROFOn; /* 1: on, 0:off */
+	u16 gpio_period; /* unit: 1024 us */
+} __attribute__((packed));
+
+
+
+/* _RSVDPAGE_LOC_CMD0 */
+#define SET_8812_H2CCMD_RSVDPAGE_LOC_PROBE_RSP(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
+#define SET_8812_H2CCMD_RSVDPAGE_LOC_PSPOLL(__pH2CCmd, __Value)				SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 8, __Value)
+#define SET_8812_H2CCMD_RSVDPAGE_LOC_NULL_DATA(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value)
+#define SET_8812_H2CCMD_RSVDPAGE_LOC_QOS_NULL_DATA(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 8, __Value)
+#define SET_8812_H2CCMD_RSVDPAGE_LOC_BT_QOS_NULL_DATA(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 0, 8, __Value)
+
+/* _SETPWRMODE_PARM */
+#define SET_8812_H2CCMD_PWRMODE_PARM_MODE(__pH2CCmd, __Value)				SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
+#define SET_8812_H2CCMD_PWRMODE_PARM_RLBM(__pH2CCmd, __Value)				SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 4, __Value)
+#define SET_8812_H2CCMD_PWRMODE_PARM_SMART_PS(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 4, 4, __Value)
+#define SET_8812_H2CCMD_PWRMODE_PARM_BCN_PASS_TIME(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value)
+#define SET_8812_H2CCMD_PWRMODE_PARM_ALL_QUEUE_UAPSD(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 8, __Value)
+#define SET_8812_H2CCMD_PWRMODE_PARM_BCN_EARLY_C2H_RPT(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 2, 1, __Value)
+#define SET_8812_H2CCMD_PWRMODE_PARM_PWR_STATE(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 0, 8, __Value)
+
+#define GET_8812_H2CCMD_PWRMODE_PARM_MODE(__pH2CCmd)							LE_BITS_TO_1BYTE(__pH2CCmd, 0, 8)
+
+/* _P2P_PS_OFFLOAD */
+#define SET_8812_H2CCMD_P2P_PS_OFFLOAD_ENABLE(__pH2CCmd, __Value)				SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 1, __Value)
+#define SET_8812_H2CCMD_P2P_PS_OFFLOAD_ROLE(__pH2CCmd, __Value)				SET_BITS_TO_LE_1BYTE(__pH2CCmd, 1, 1, __Value)
+#define SET_8812_H2CCMD_P2P_PS_OFFLOAD_CTWINDOW_EN(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd, 2, 1, __Value)
+#define SET_8812_H2CCMD_P2P_PS_OFFLOAD_NOA0_EN(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE(__pH2CCmd, 3, 1, __Value)
+#define SET_8812_H2CCMD_P2P_PS_OFFLOAD_NOA1_EN(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE(__pH2CCmd, 4, 1, __Value)
+#define SET_8812_H2CCMD_P2P_PS_OFFLOAD_ALLSTASLEEP(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd, 5, 1, __Value)
+#define SET_8812_H2CCMD_P2P_PS_OFFLOAD_DISCOVERY(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE(__pH2CCmd, 6, 1, __Value)
+
+
+void	set_ra_ldpc_8812(struct cmn_sta_info *cmn_sta_info, BOOLEAN bLDPC);
+
+/* host message to firmware cmd */
+s32 fill_h2c_cmd_8812(PADAPTER padapter, u8 ElementID, u32 CmdLen, u8 *pCmdBuffer);
+void rtl8812_set_FwPwrMode_cmd(PADAPTER padapter, u8 PSMode);
+void rtl8812_set_FwJoinBssReport_cmd(PADAPTER padapter, u8 mstatus);
+u8 rtl8812_set_rssi_cmd(PADAPTER padapter, u8 *param);
+void rtl8812_set_wowlan_cmd(_adapter *padapter, u8 enable);
+u8 GetTxBufferRsvdPageNum8812(_adapter *padapter, bool wowlan);
+
+#ifdef CONFIG_BT_COEXIST
+void rtl8812a_download_BTCoex_AP_mode_rsvd_page(PADAPTER padapter);
+#endif /* CONFIG_BT_COEXIST */
+#ifdef CONFIG_P2P_PS
+void rtl8812_set_p2p_ps_offload_cmd(PADAPTER padapter, u8 p2p_ps_state);
+#endif /* CONFIG_P2P */
+
+#ifdef CONFIG_FWLPS_IN_IPS
+void rtl8812_set_FwPwrModeInIPS_cmd(PADAPTER padapter, u8 cmd_param);
+#endif
+
+#ifdef CONFIG_TDLS
+#ifdef CONFIG_TDLS_CH_SW
+void rtl8812_set_BcnEarly_C2H_Rpt_cmd(PADAPTER padapter, u8 enable);
+#endif
+#endif
+
+/* ------------------------------------
+ * C2H format
+ * ------------------------------------ */
+
+/* TX Beamforming */
+#define GET_8812_C2H_TXBF_ORIGINATE(_Header)			LE_BITS_TO_1BYTE(_Header, 0, 8)
+#define GET_8812_C2H_TXBF_MACID(_Header)				LE_BITS_TO_1BYTE((_Header + 1), 0, 8)
+
+
+
+/* / TX Feedback Content */
+#define	USEC_UNIT_FOR_8812_C2H_TX_RPT_QUEUE_TIME			256
+
+#define	GET_8812_C2H_TX_RPT_QUEUE_SELECT(_Header)			LE_BITS_TO_1BYTE((_Header + 0), 0, 5)
+#define	GET_8812_C2H_TX_RPT_PKT_BROCAST(_Header)			LE_BITS_TO_1BYTE((_Header + 0), 5, 1)
+#define	GET_8812_C2H_TX_RPT_LIFE_TIME_OVER(_Header)			LE_BITS_TO_1BYTE((_Header + 0), 6, 1)
+#define	GET_8812_C2H_TX_RPT_RETRY_OVER(_Header)				LE_BITS_TO_1BYTE((_Header + 0), 7, 1)
+#define	GET_8812_C2H_TX_RPT_MAC_ID(_Header)					LE_BITS_TO_1BYTE((_Header + 1), 0, 8)
+#define	GET_8812_C2H_TX_RPT_DATA_RETRY_CNT(_Header)		LE_BITS_TO_1BYTE((_Header + 2), 0, 6)
+#define	GET_8812_C2H_TX_RPT_QUEUE_TIME(_Header)				LE_BITS_TO_2BYTE((_Header + 3), 0, 16)	/* In unit of 256 microseconds. */
+#define	GET_8812_C2H_TX_RPT_FINAL_DATA_RATE(_Header)		LE_BITS_TO_1BYTE((_Header + 5), 0, 8)
+
+/* BT_FW_PATCH */
+#define SET_8812_H2CCMD_BT_FW_PATCH_SIZE(__pH2CCmd, __Value)					SET_BITS_TO_LE_2BYTE((pu1Byte)(__pH2CCmd), 0, 16, __Value)
+#define SET_8812_H2CCMD_BT_FW_PATCH_ADDR0(__pH2CCmd, __Value)					SET_BITS_TO_LE_1BYTE((pu1Byte)(__pH2CCmd)+2, 0, 8, __Value)
+#define SET_8812_H2CCMD_BT_FW_PATCH_ADDR1(__pH2CCmd, __Value)					SET_BITS_TO_LE_1BYTE((pu1Byte)(__pH2CCmd)+3, 0, 8, __Value)
+#define SET_8812_H2CCMD_BT_FW_PATCH_ADDR2(__pH2CCmd, __Value)					SET_BITS_TO_LE_1BYTE((pu1Byte)(__pH2CCmd)+4, 0, 8, __Value)
+#define SET_8812_H2CCMD_BT_FW_PATCH_ADDR3(__pH2CCmd, __Value)					SET_BITS_TO_LE_1BYTE((pu1Byte)(__pH2CCmd)+5, 0, 8, __Value)
+
+s32 c2h_handler_8812a(_adapter *adapter, u8 id, u8 seq, u8 plen, u8 *payload);
+
+#endif/* __RTL8812A_CMD_H__ */
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/include/rtl8812a_dm.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/rtl8812a_dm.h
--- linux-5.6.3/3rdparty/rtl8821ce/include/rtl8812a_dm.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/rtl8812a_dm.h	2020-04-10 16:35:06.850661655 +0300
@@ -0,0 +1,27 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#ifndef __RTL8812A_DM_H__
+#define __RTL8812A_DM_H__
+
+void rtl8812_init_dm_priv(IN PADAPTER Adapter);
+void rtl8812_deinit_dm_priv(IN PADAPTER Adapter);
+void rtl8812_InitHalDm(IN PADAPTER Adapter);
+void rtl8812_HalDmWatchDog(IN PADAPTER Adapter);
+
+/* VOID rtl8192c_dm_CheckTXPowerTracking(IN PADAPTER Adapter); */
+
+/* void rtl8192c_dm_RF_Saving(IN PADAPTER pAdapter, IN u8 bForceInNormal); */
+
+#endif
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/include/rtl8812a_hal.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/rtl8812a_hal.h
--- linux-5.6.3/3rdparty/rtl8821ce/include/rtl8812a_hal.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/rtl8812a_hal.h	2020-04-10 16:35:06.850661655 +0300
@@ -0,0 +1,369 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#ifndef __RTL8812A_HAL_H__
+#define __RTL8812A_HAL_H__
+
+/* #include "hal_com.h" */
+#include "hal_data.h"
+
+/* include HAL Related header after HAL Related compiling flags */
+#include "rtl8812a_spec.h"
+#include "rtl8812a_rf.h"
+#include "rtl8812a_dm.h"
+#include "rtl8812a_recv.h"
+#include "rtl8812a_xmit.h"
+#include "rtl8812a_cmd.h"
+#include "rtl8812a_led.h"
+#include "Hal8812PwrSeq.h"
+#include "Hal8821APwrSeq.h" /* for 8821A/8811A */
+#include "Hal8812PhyReg.h"
+#include "Hal8812PhyCfg.h"
+#ifdef DBG_CONFIG_ERROR_DETECT
+#include "rtl8812a_sreset.h"
+#endif
+
+/* ---------------------------------------------------------------------
+ *		RTL8812 Power Configuration CMDs for PCIe interface
+ * --------------------------------------------------------------------- */
+#define Rtl8812_NIC_PWR_ON_FLOW				rtl8812_power_on_flow
+#define Rtl8812_NIC_RF_OFF_FLOW				rtl8812_radio_off_flow
+#define Rtl8812_NIC_DISABLE_FLOW				rtl8812_card_disable_flow
+#define Rtl8812_NIC_ENABLE_FLOW				rtl8812_card_enable_flow
+#define Rtl8812_NIC_SUSPEND_FLOW				rtl8812_suspend_flow
+#define Rtl8812_NIC_RESUME_FLOW				rtl8812_resume_flow
+#define Rtl8812_NIC_PDN_FLOW					rtl8812_hwpdn_flow
+#define Rtl8812_NIC_LPS_ENTER_FLOW			rtl8812_enter_lps_flow
+#define Rtl8812_NIC_LPS_LEAVE_FLOW				rtl8812_leave_lps_flow
+
+/* ---------------------------------------------------------------------
+ *		RTL8821 Power Configuration CMDs for PCIe interface
+ * --------------------------------------------------------------------- */
+#define Rtl8821A_NIC_PWR_ON_FLOW				rtl8821A_power_on_flow
+#define Rtl8821A_NIC_RF_OFF_FLOW				rtl8821A_radio_off_flow
+#define Rtl8821A_NIC_DISABLE_FLOW				rtl8821A_card_disable_flow
+#define Rtl8821A_NIC_ENABLE_FLOW				rtl8821A_card_enable_flow
+#define Rtl8821A_NIC_SUSPEND_FLOW				rtl8821A_suspend_flow
+#define Rtl8821A_NIC_RESUME_FLOW				rtl8821A_resume_flow
+#define Rtl8821A_NIC_PDN_FLOW					rtl8821A_hwpdn_flow
+#define Rtl8821A_NIC_LPS_ENTER_FLOW			rtl8821A_enter_lps_flow
+#define Rtl8821A_NIC_LPS_LEAVE_FLOW			rtl8821A_leave_lps_flow
+
+
+#if 1 /* download firmware related data structure */
+#define FW_SIZE_8812			0x8000 /* Compatible with RTL8723 Maximal RAM code size 24K.   modified to 32k, TO compatible with 92d maximal fw size 32k */
+#define FW_START_ADDRESS		0x1000
+#define FW_END_ADDRESS		0x5FFF
+
+
+
+typedef struct _RT_FIRMWARE_8812 {
+	FIRMWARE_SOURCE	eFWSource;
+#ifdef CONFIG_EMBEDDED_FWIMG
+	u8			*szFwBuffer;
+#else
+	u8			szFwBuffer[FW_SIZE_8812];
+#endif
+	u32			ulFwLength;
+} RT_FIRMWARE_8812, *PRT_FIRMWARE_8812;
+
+/*
+ * This structure must be cared byte-ordering
+ *
+ * Added by tynli. 2009.12.04. */
+#define IS_FW_HEADER_EXIST_8812(_pFwHdr)	((GET_FIRMWARE_HDR_SIGNATURE_8812(_pFwHdr) & 0xFFF0) == 0x9500)
+
+#define IS_FW_HEADER_EXIST_8821(_pFwHdr)	((GET_FIRMWARE_HDR_SIGNATURE_8812(_pFwHdr) & 0xFFF0) == 0x2100)
+/* *****************************************************
+ *					Firmware Header(8-byte alinment required)
+ * *****************************************************
+ * --- LONG WORD 0 ---- */
+#define GET_FIRMWARE_HDR_SIGNATURE_8812(__FwHdr)		LE_BITS_TO_4BYTE(__FwHdr, 0, 16) /* 92C0: test chip; 92C, 88C0: test chip; 88C1: MP A-cut; 92C1: MP A-cut */
+#define GET_FIRMWARE_HDR_CATEGORY_8812(__FwHdr)		LE_BITS_TO_4BYTE(__FwHdr, 16, 8) /* AP/NIC and USB/PCI */
+#define GET_FIRMWARE_HDR_FUNCTION_8812(__FwHdr)		LE_BITS_TO_4BYTE(__FwHdr, 24, 8) /* Reserved for different FW function indcation, for further use when driver needs to download different FW in different conditions */
+#define GET_FIRMWARE_HDR_VERSION_8812(__FwHdr)		LE_BITS_TO_4BYTE(__FwHdr+4, 0, 16)/* FW Version */
+#define GET_FIRMWARE_HDR_SUB_VER_8812(__FwHdr)		LE_BITS_TO_4BYTE(__FwHdr+4, 16, 8) /* FW Subversion, default 0x00 */
+#define GET_FIRMWARE_HDR_RSVD1_8812(__FwHdr)			LE_BITS_TO_4BYTE(__FwHdr+4, 24, 8)
+
+/* --- LONG WORD 1 ---- */
+#define GET_FIRMWARE_HDR_MONTH_8812(__FwHdr)			LE_BITS_TO_4BYTE(__FwHdr+8, 0, 8) /* Release time Month field */
+#define GET_FIRMWARE_HDR_DATE_8812(__FwHdr)			LE_BITS_TO_4BYTE(__FwHdr+8, 8, 8) /* Release time Date field */
+#define GET_FIRMWARE_HDR_HOUR_8812(__FwHdr)			LE_BITS_TO_4BYTE(__FwHdr+8, 16, 8)/* Release time Hour field */
+#define GET_FIRMWARE_HDR_MINUTE_8812(__FwHdr)		LE_BITS_TO_4BYTE(__FwHdr+8, 24, 8)/* Release time Minute field */
+#define GET_FIRMWARE_HDR_ROMCODE_SIZE_8812(__FwHdr)	LE_BITS_TO_4BYTE(__FwHdr+12, 0, 16)/* The size of RAM code */
+#define GET_FIRMWARE_HDR_RSVD2_8812(__FwHdr)			LE_BITS_TO_4BYTE(__FwHdr+12, 16, 16)
+
+/* --- LONG WORD 2 ---- */
+#define GET_FIRMWARE_HDR_SVN_IDX_8812(__FwHdr)		LE_BITS_TO_4BYTE(__FwHdr+16, 0, 32)/* The SVN entry index */
+#define GET_FIRMWARE_HDR_RSVD3_8812(__FwHdr)			LE_BITS_TO_4BYTE(__FwHdr+20, 0, 32)
+
+/* --- LONG WORD 3 ---- */
+#define GET_FIRMWARE_HDR_RSVD4_8812(__FwHdr)			LE_BITS_TO_4BYTE(__FwHdr+24, 0, 32)
+#define GET_FIRMWARE_HDR_RSVD5_8812(__FwHdr)			LE_BITS_TO_4BYTE(__FwHdr+28, 0, 32)
+
+#endif /* download firmware related data structure */
+
+
+#define DRIVER_EARLY_INT_TIME_8812		0x05
+#define BCN_DMA_ATIME_INT_TIME_8812		0x02
+
+/* for 8812
+ * TX 128K, RX 16K, Page size 512B for TX, 128B for RX */
+#define MAX_RX_DMA_BUFFER_SIZE_8812	0x3E80 /* RX 16K */
+
+#ifdef CONFIG_WOWLAN
+	#define RESV_FMWF	(WKFMCAM_SIZE * MAX_WKFM_CAM_NUM) /* 16 entries, for each is 24 bytes*/
+#else
+	#define RESV_FMWF	0
+#endif
+
+#ifdef CONFIG_FW_C2H_DEBUG
+	#define RX_DMA_RESERVED_SIZE_8812	0x100	/* 256B, reserved for c2h debug message */
+#else
+	#define RX_DMA_RESERVED_SIZE_8812	0x0	/* 0B */
+#endif
+#define RX_DMA_BOUNDARY_8812		(MAX_RX_DMA_BUFFER_SIZE_8812 - RX_DMA_RESERVED_SIZE_8812 - 1)
+
+#define PAGE_SIZE_TX_8812A PAGE_SIZE_512
+
+/* Beacon:MAX_BEACON_LEN/PAGE_SIZE_TX_8812A
+ * PS-Poll:1, Null Data:1,Qos Null Data:1,BT Qos Null Data:1,CTS-2-SELF,LTE QoS Null*/
+#define BCNQ_PAGE_NUM_8812		(MAX_BEACON_LEN / PAGE_SIZE_TX_8812A + 6) /*0x07*/
+
+/* For WoWLan , more reserved page
+ * ARP Rsp:1, RWC:1, GTK Info:1,GTK RSP:1,GTK EXT MEM:1, AOAC rpt: 1,PNO: 6
+ * NS offload: 1 NDP info: 1
+ */
+#ifdef CONFIG_WOWLAN
+	#define WOWLAN_PAGE_NUM_8812	0x08
+#else
+	#define WOWLAN_PAGE_NUM_8812	0x00
+#endif
+
+
+#ifdef CONFIG_BEAMFORMER_FW_NDPA
+	#define FW_NDPA_PAGE_NUM	0x02
+#else
+	#define FW_NDPA_PAGE_NUM	0x00
+#endif
+
+#ifdef DBG_FW_DEBUG_MSG_PKT
+	#define FW_DBG_MSG_PKT_PAGE_NUM_8812	0x01
+#else
+	#define FW_DBG_MSG_PKT_PAGE_NUM_8812	0x00
+#endif /*DBG_FW_DEBUG_MSG_PKT*/
+
+#define TX_TOTAL_PAGE_NUMBER_8812	(0xFF - BCNQ_PAGE_NUM_8812 - WOWLAN_PAGE_NUM_8812 - FW_NDPA_PAGE_NUM - FW_DBG_MSG_PKT_PAGE_NUM_8812)
+#define TX_PAGE_BOUNDARY_8812			(TX_TOTAL_PAGE_NUMBER_8812 + 1)
+
+#define TX_PAGE_BOUNDARY_WOWLAN_8812		(0xFF - BCNQ_PAGE_NUM_8812 - WOWLAN_PAGE_NUM_8812 + 1)
+
+#define WMM_NORMAL_TX_TOTAL_PAGE_NUMBER_8812	TX_TOTAL_PAGE_NUMBER_8812
+#define WMM_NORMAL_TX_PAGE_BOUNDARY_8812		(WMM_NORMAL_TX_TOTAL_PAGE_NUMBER_8812 + 1)
+
+/* For Normal Chip Setting
+ * (HPQ + LPQ + NPQ + PUBQ) shall be TX_TOTAL_PAGE_NUMBER_8812 */
+#define NORMAL_PAGE_NUM_LPQ_8812				0x10
+#define NORMAL_PAGE_NUM_HPQ_8812			0x10
+#define NORMAL_PAGE_NUM_NPQ_8812			0x00
+
+#define WMM_NORMAL_PAGE_NUM_HPQ_8812		0x30
+#define WMM_NORMAL_PAGE_NUM_LPQ_8812		0x20
+#define WMM_NORMAL_PAGE_NUM_NPQ_8812		0x20
+
+
+/* for 8821A
+ * TX 64K, RX 16K, Page size 256B for TX, 128B for RX */
+#define PAGE_SIZE_TX_8821A					256
+#define PAGE_SIZE_RX_8821A					128
+
+#define MAX_RX_DMA_BUFFER_SIZE_8821			0x3E80 /* RX 16K */
+
+#ifdef CONFIG_FW_C2H_DEBUG
+	#define RX_DMA_RESERVED_SIZE_8821	0x100	/* 256B, reserved for c2h debug message */
+#else
+	#define RX_DMA_RESERVED_SIZE_8821	0x0	/* 0B */
+#endif
+#define RX_DMA_BOUNDARY_8821		(MAX_RX_DMA_BUFFER_SIZE_8821 - RX_DMA_RESERVED_SIZE_8821 - 1)
+
+/* Beacon:MAX_BEACON_LEN/PAGE_SIZE_TX_8821A
+ * PS-Poll:1, Null Data:1,Qos Null Data:1,BT Qos Null Data:1,CTS-2-SELF,LTE QoS Null*/
+
+#define BCNQ_PAGE_NUM_8821		(MAX_BEACON_LEN / PAGE_SIZE_TX_8821A + 6) /*0x08*/
+
+
+/* For WoWLan , more reserved page
+ * ARP Rsp:1, RWC:1, GTK Info:1,GTK RSP:1,GTK EXT MEM:1, PNO: 6 */
+#ifdef CONFIG_WOWLAN
+	#define WOWLAN_PAGE_NUM_8821	0x06
+#else
+	#define WOWLAN_PAGE_NUM_8821	0x00
+#endif
+
+#define TX_TOTAL_PAGE_NUMBER_8821	(0xFF - BCNQ_PAGE_NUM_8821 - WOWLAN_PAGE_NUM_8821)
+#define TX_PAGE_BOUNDARY_8821				(TX_TOTAL_PAGE_NUMBER_8821 + 1)
+/* #define TX_PAGE_BOUNDARY_WOWLAN_8821		0xE0 */
+
+#define WMM_NORMAL_TX_TOTAL_PAGE_NUMBER_8821	TX_TOTAL_PAGE_NUMBER_8821
+#define WMM_NORMAL_TX_PAGE_BOUNDARY_8821		(WMM_NORMAL_TX_TOTAL_PAGE_NUMBER_8821 + 1)
+
+
+/* (HPQ + LPQ + NPQ + PUBQ) shall be TX_TOTAL_PAGE_NUMBER */
+#define NORMAL_PAGE_NUM_LPQ_8821			0x08/* 0x10 */
+#define NORMAL_PAGE_NUM_HPQ_8821		0x08/* 0x10 */
+#define NORMAL_PAGE_NUM_NPQ_8821		0x00
+#define NORMAL_PAGE_NUM_EPQ_8821			0x04
+
+#define WMM_NORMAL_PAGE_NUM_HPQ_8821		0x30
+#define WMM_NORMAL_PAGE_NUM_LPQ_8821		0x20
+#define WMM_NORMAL_PAGE_NUM_NPQ_8821		0x20
+#define WMM_NORMAL_PAGE_NUM_EPQ_8821		0x00
+
+#define MCC_NORMAL_PAGE_NUM_HPQ_8821		0x10
+#define MCC_NORMAL_PAGE_NUM_LPQ_8821		0x10
+#define MCC_NORMAL_PAGE_NUM_NPQ_8821		0x10
+
+#define	EFUSE_HIDDEN_812AU					0
+#define	EFUSE_HIDDEN_812AU_VS				1
+#define	EFUSE_HIDDEN_812AU_VL				2
+#define	EFUSE_HIDDEN_812AU_VN				3
+
+#if 0
+#define EFUSE_REAL_CONTENT_LEN_JAGUAR		1024
+#define HWSET_MAX_SIZE_JAGUAR					1024
+#else
+#define EFUSE_REAL_CONTENT_LEN_JAGUAR		512
+#define HWSET_MAX_SIZE_JAGUAR					512
+#endif
+
+#define EFUSE_MAX_BANK_8812A					2
+#define EFUSE_MAP_LEN_JAGUAR					512
+#define EFUSE_MAX_SECTION_JAGUAR				64
+#define EFUSE_MAX_WORD_UNIT_JAGUAR			4
+#define EFUSE_IC_ID_OFFSET_JAGUAR				506	/* For some inferiority IC purpose. added by Roger, 2009.09.02. */
+#define AVAILABLE_EFUSE_ADDR_8812(addr)	(addr < EFUSE_REAL_CONTENT_LEN_JAGUAR)
+/* <Roger_Notes> To prevent out of boundary programming case, leave 1byte and program full section
+ * 9bytes + 1byt + 5bytes and pre 1byte.
+ * For worst case:
+ * | 2byte|----8bytes----|1byte|--7bytes--|  */ /* 92D */
+#define EFUSE_OOB_PROTECT_BYTES_JAGUAR		18	/* PG data exclude header, dummy 7 bytes frome CP test and reserved 1byte. */
+#define EFUSE_PROTECT_BYTES_BANK_JAGUAR		16
+
+#define INCLUDE_MULTI_FUNC_BT(_Adapter)	(GET_HAL_DATA(_Adapter)->MultiFunc & RT_MULTI_FUNC_BT)
+#define INCLUDE_MULTI_FUNC_GPS(_Adapter)	(GET_HAL_DATA(_Adapter)->MultiFunc & RT_MULTI_FUNC_GPS)
+
+/* #define IS_MULTI_FUNC_CHIP(_Adapter)	(((((PHAL_DATA_TYPE)(_Adapter->HalData))->MultiFunc) & (RT_MULTI_FUNC_BT|RT_MULTI_FUNC_GPS)) ? _TRUE : _FALSE) */
+
+/* #define RT_IS_FUNC_DISABLED(__pAdapter, __FuncBits) ( (__pAdapter)->DisabledFunctions & (__FuncBits) ) */
+#define HAL_EFUSE_MEMORY
+
+/* ********************************************************
+ *			EFUSE for BT definition
+ * ******************************************************** */
+#define BANK_NUM			2
+#define EFUSE_BT_REAL_BANK_CONTENT_LEN	512
+#define EFUSE_BT_REAL_CONTENT_LEN	\
+	(EFUSE_BT_REAL_BANK_CONTENT_LEN * BANK_NUM)
+#define EFUSE_BT_MAP_LEN		1024	/* 1k bytes */
+#define EFUSE_BT_MAX_SECTION		(EFUSE_BT_MAP_LEN / 8)
+#define EFUSE_PROTECT_BYTES_BANK	16
+
+#define AVAILABLE_EFUSE_ADDR(addr)	(addr < EFUSE_BT_REAL_CONTENT_LEN)
+
+#ifdef CONFIG_FILE_FWIMG
+extern char *rtw_fw_file_path;
+#ifdef CONFIG_WOWLAN
+extern char *rtw_fw_wow_file_path;
+#endif
+#ifdef CONFIG_MP_INCLUDED
+extern char *rtw_fw_mp_bt_file_path;
+#endif
+#endif
+
+
+/* rtl8812_hal_init.c */
+void	_8051Reset8812(PADAPTER padapter);
+s32	FirmwareDownload8812(PADAPTER Adapter, BOOLEAN bUsedWoWLANFw);
+void	InitializeFirmwareVars8812(PADAPTER padapter);
+
+s32	_LLTWrite_8812A(PADAPTER Adapter, u32 address, u32 data);
+s32	InitLLTTable8812A(PADAPTER padapter, u8 txpktbuf_bndy);
+void InitRDGSetting8812A(PADAPTER padapter);
+
+void CheckAutoloadState8812A(PADAPTER padapter);
+
+/* EFuse */
+u8	GetEEPROMSize8812A(PADAPTER padapter);
+void InitPGData8812A(PADAPTER padapter);
+void	Hal_EfuseParseIDCode8812A(PADAPTER padapter, u8 *hwinfo);
+void	Hal_ReadPROMVersion8812A(PADAPTER padapter, u8 *hwinfo, BOOLEAN AutoLoadFail);
+void	Hal_ReadTxPowerInfo8812A(PADAPTER padapter, u8 *hwinfo, BOOLEAN	AutoLoadFail);
+void	Hal_ReadBoardType8812A(PADAPTER pAdapter, u8 *hwinfo, BOOLEAN AutoLoadFail);
+void	Hal_ReadThermalMeter_8812A(PADAPTER	Adapter, u8 *PROMContent, BOOLEAN	AutoloadFail);
+void	Hal_ReadChannelPlan8812A(PADAPTER padapter, u8 *hwinfo, BOOLEAN AutoLoadFail);
+void	Hal_EfuseParseXtal_8812A(PADAPTER pAdapter, u8 *hwinfo, BOOLEAN AutoLoadFail);
+void	Hal_ReadAntennaDiversity8812A(PADAPTER pAdapter, u8 *PROMContent, BOOLEAN AutoLoadFail);
+void	Hal_ReadAmplifierType_8812A(PADAPTER Adapter, u8 *PROMContent, BOOLEAN AutoloadFail);
+void	Hal_ReadPAType_8821A(PADAPTER Adapter, u8 *PROMContent, BOOLEAN AutoloadFail);
+void	Hal_ReadRFEType_8812A(PADAPTER Adapter, u8 *PROMContent, BOOLEAN AutoloadFail);
+void	Hal_EfuseParseBTCoexistInfo8812A(PADAPTER Adapter, u8 *hwinfo, BOOLEAN AutoLoadFail);
+void	hal_ReadUsbType_8812AU(PADAPTER Adapter, u8 *PROMContent, BOOLEAN AutoloadFail);
+#ifdef CONFIG_MP_INCLUDED
+int	FirmwareDownloadBT(PADAPTER Adapter, PRT_MP_FIRMWARE pFirmware);
+#endif
+void	Hal_ReadRemoteWakeup_8812A(PADAPTER padapter, u8 *hwinfo, BOOLEAN AutoLoadFail);
+
+BOOLEAN HalDetectPwrDownMode8812(PADAPTER Adapter);
+void Hal_EfuseParseKFreeData_8821A(PADAPTER Adapter, u8 *PROMContent, BOOLEAN AutoloadFail);
+
+#ifdef CONFIG_WOWLAN
+void Hal_DetectWoWMode(PADAPTER pAdapter);
+#endif /* CONFIG_WOWLAN */
+
+void _InitBeaconParameters_8812A(PADAPTER padapter);
+void SetBeaconRelatedRegisters8812A(PADAPTER padapter);
+
+void ReadRFType8812A(PADAPTER padapter);
+void InitDefaultValue8821A(PADAPTER padapter);
+
+u8 SetHwReg8812A(PADAPTER padapter, u8 variable, u8 *pval);
+void GetHwReg8812A(PADAPTER padapter, u8 variable, u8 *pval);
+u8 SetHalDefVar8812A(PADAPTER padapter, HAL_DEF_VARIABLE variable, void *pval);
+u8 GetHalDefVar8812A(PADAPTER padapter, HAL_DEF_VARIABLE variable, void *pval);
+void rtl8812_set_hal_ops(struct hal_ops *pHalFunc);
+void init_hal_spec_8812a(_adapter *adapter);
+void init_hal_spec_8821a(_adapter *adapter);
+
+u32 upload_txpktbuf_8812au(_adapter *adapter, u8 *buf, u32 buflen);
+
+void rtl8812_start_thread(PADAPTER padapter);
+void rtl8812_stop_thread(PADAPTER padapter);
+
+#ifdef CONFIG_PCI_HCI
+BOOLEAN	InterruptRecognized8812AE(PADAPTER Adapter);
+VOID	UpdateInterruptMask8812AE(PADAPTER Adapter, u32 AddMSR, u32 AddMSR1, u32 RemoveMSR, u32 RemoveMSR1);
+VOID	InitTRXDescHwAddress8812AE(PADAPTER Adapter);
+#endif
+
+#ifdef CONFIG_BT_COEXIST
+void rtl8812a_combo_card_WifiOnlyHwInit(PADAPTER Adapter);
+#endif
+
+VOID
+Hal_PatchwithJaguar_8812(
+	IN PADAPTER				Adapter,
+	IN RT_MEDIA_STATUS		MediaStatus
+);
+
+#endif /* __RTL8188E_HAL_H__ */
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/include/rtl8812a_led.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/rtl8812a_led.h
--- linux-5.6.3/3rdparty/rtl8821ce/include/rtl8812a_led.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/rtl8812a_led.h	2020-04-10 16:35:06.850661655 +0300
@@ -0,0 +1,41 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#ifndef __RTL8812A_LED_H__
+#define __RTL8812A_LED_H__
+#ifdef CONFIG_RTW_LED
+#ifdef CONFIG_RTW_SW_LED
+/* ********************************************************************************
+ * Interface to manipulate LED objects.
+ * ******************************************************************************** */
+#ifdef CONFIG_USB_HCI
+void rtl8812au_InitSwLeds(PADAPTER padapter);
+void rtl8812au_DeInitSwLeds(PADAPTER padapter);
+#endif
+#ifdef CONFIG_PCI_HCI
+void rtl8812ae_InitSwLeds(PADAPTER padapter);
+void rtl8812ae_DeInitSwLeds(PADAPTER padapter);
+#endif
+#ifdef CONFIG_SDIO_HCI
+void rtl8821as_InitSwLeds(PADAPTER padapter);
+void rtl8821as_DeInitSwLeds(PADAPTER padapter);
+#endif
+#endif/*CONFIG_RTW_SW_LED*/
+#endif/*#ifdef CONFIG_RTW_LED*/
+
+#ifdef CONFIG_SDIO_HCI
+void rtl8821as_init_led_circuit(PADAPTER adapter);
+#endif
+
+#endif /*__RTL8812A_LED_H__*/
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/include/rtl8812a_recv.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/rtl8812a_recv.h
--- linux-5.6.3/3rdparty/rtl8821ce/include/rtl8812a_recv.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/rtl8812a_recv.h	2020-04-10 16:35:06.850661655 +0300
@@ -0,0 +1,153 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#ifndef __RTL8812A_RECV_H__
+#define __RTL8812A_RECV_H__
+
+#if defined(CONFIG_USB_HCI)
+
+	#ifndef MAX_RECVBUF_SZ
+		#ifdef PLATFORM_OS_CE
+			#define MAX_RECVBUF_SZ (8192+1024) /* 8K+1k */
+		#else
+			#ifndef CONFIG_MINIMAL_MEMORY_USAGE
+				#ifdef CONFIG_PREALLOC_RX_SKB_BUFFER
+					#define MAX_RECVBUF_SZ (rtw_rtkm_get_buff_size()) /*depend rtkm*/
+				#else
+					#define MAX_RECVBUF_SZ (32768)  /*32k*/
+				#endif
+				/* #define MAX_RECVBUF_SZ (24576) */ /* 24k */
+				/* #define MAX_RECVBUF_SZ (20480) */ /* 20K */
+				/* #define MAX_RECVBUF_SZ (10240) */ /* 10K */
+				/* #define MAX_RECVBUF_SZ (15360) */ /* 15k < 16k */
+				/* #define MAX_RECVBUF_SZ (8192+1024) */ /* 8K+1k */
+				#ifdef CONFIG_PLATFORM_NOVATEK_NT72668
+					#undef MAX_RECVBUF_SZ
+					#define MAX_RECVBUF_SZ (15360) /* 15k < 16k */
+				#endif /* CONFIG_PLATFORM_NOVATEK_NT72668 */
+			#else
+				#define MAX_RECVBUF_SZ (4000) /* about 4K */
+			#endif
+		#endif
+	#endif /* !MAX_RECVBUF_SZ */
+
+#elif defined(CONFIG_PCI_HCI)
+	/* #ifndef CONFIG_MINIMAL_MEMORY_USAGE */
+	/*	#define MAX_RECVBUF_SZ (9100) */
+	/* #else */
+	#define MAX_RECVBUF_SZ (4000) /* about 4K
+	* #endif */
+
+
+#elif defined(CONFIG_SDIO_HCI)
+
+	#define MAX_RECVBUF_SZ (RX_DMA_BOUNDARY_8821 + 1)
+
+#endif
+
+
+/* Rx smooth factor */
+#define Rx_Smooth_Factor (20)
+
+/* DWORD 0 */
+#define SET_RX_STATUS_DESC_PKT_LEN_8812(__pRxStatusDesc, __Value)		SET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 0, 14, __Value)
+#define SET_RX_STATUS_DESC_EOR_8812(__pRxStatusDesc, __Value)		SET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 30, 1, __Value)
+#define SET_RX_STATUS_DESC_OWN_8812(__pRxStatusDesc, __Value)		SET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 31, 1, __Value)
+
+#define GET_RX_STATUS_DESC_PKT_LEN_8812(__pRxStatusDesc)			LE_BITS_TO_4BYTE(__pRxStatusDesc, 0, 14)
+#define GET_RX_STATUS_DESC_CRC32_8812(__pRxStatusDesc)			LE_BITS_TO_4BYTE(__pRxStatusDesc, 14, 1)
+#define GET_RX_STATUS_DESC_ICV_8812(__pRxStatusDesc)				LE_BITS_TO_4BYTE(__pRxStatusDesc, 15, 1)
+#define GET_RX_STATUS_DESC_DRVINFO_SIZE_8812(__pRxStatusDesc)		LE_BITS_TO_4BYTE(__pRxStatusDesc, 16, 4)
+#define GET_RX_STATUS_DESC_SECURITY_8812(__pRxStatusDesc)			LE_BITS_TO_4BYTE(__pRxStatusDesc, 20, 3)
+#define GET_RX_STATUS_DESC_QOS_8812(__pRxStatusDesc)				LE_BITS_TO_4BYTE(__pRxStatusDesc, 23, 1)
+#define GET_RX_STATUS_DESC_SHIFT_8812(__pRxStatusDesc)			LE_BITS_TO_4BYTE(__pRxStatusDesc, 24, 2)
+#define GET_RX_STATUS_DESC_PHY_STATUS_8812(__pRxStatusDesc)			LE_BITS_TO_4BYTE(__pRxStatusDesc, 26, 1)
+#define GET_RX_STATUS_DESC_SWDEC_8812(__pRxStatusDesc)			LE_BITS_TO_4BYTE(__pRxStatusDesc, 27, 1)
+#define GET_RX_STATUS_DESC_LAST_SEG_8812(__pRxStatusDesc)			LE_BITS_TO_4BYTE(__pRxStatusDesc, 28, 1)
+#define GET_RX_STATUS_DESC_FIRST_SEG_8812(__pRxStatusDesc)			LE_BITS_TO_4BYTE(__pRxStatusDesc, 29, 1)
+#define GET_RX_STATUS_DESC_EOR_8812(__pRxStatusDesc)				LE_BITS_TO_4BYTE(__pRxStatusDesc, 30, 1)
+#define GET_RX_STATUS_DESC_OWN_8812(__pRxStatusDesc)				LE_BITS_TO_4BYTE(__pRxStatusDesc, 31, 1)
+
+/* DWORD 1 */
+#define GET_RX_STATUS_DESC_MACID_8812(__pRxDesc)					LE_BITS_TO_4BYTE(__pRxDesc+4, 0, 7)
+#define GET_RX_STATUS_DESC_TID_8812(__pRxDesc)					LE_BITS_TO_4BYTE(__pRxDesc+4, 8, 4)
+#define GET_RX_STATUS_DESC_AMSDU_8812(__pRxDesc)					LE_BITS_TO_4BYTE(__pRxDesc+4, 13, 1)
+#define GET_RX_STATUS_DESC_RXID_MATCH_8812(__pRxDesc)		LE_BITS_TO_4BYTE(__pRxDesc+4, 14, 1)
+#define GET_RX_STATUS_DESC_PAGGR_8812(__pRxDesc)				LE_BITS_TO_4BYTE(__pRxDesc+4, 15, 1)
+#define GET_RX_STATUS_DESC_A1_FIT_8812(__pRxDesc)				LE_BITS_TO_4BYTE(__pRxDesc+4, 16, 4)
+#define GET_RX_STATUS_DESC_CHKERR_8812(__pRxDesc)				LE_BITS_TO_4BYTE(__pRxDesc+4, 20, 1)
+#define GET_RX_STATUS_DESC_IPVER_8812(__pRxDesc)			LE_BITS_TO_4BYTE(__pRxDesc+4, 21, 1)
+#define GET_RX_STATUS_DESC_IS_TCPUDP__8812(__pRxDesc)		LE_BITS_TO_4BYTE(__pRxDesc+4, 22, 1)
+#define GET_RX_STATUS_DESC_CHK_VLD_8812(__pRxDesc)		LE_BITS_TO_4BYTE(__pRxDesc+4, 23, 1)
+#define GET_RX_STATUS_DESC_PAM_8812(__pRxDesc)				LE_BITS_TO_4BYTE(__pRxDesc+4, 24, 1)
+#define GET_RX_STATUS_DESC_PWR_8812(__pRxDesc)				LE_BITS_TO_4BYTE(__pRxDesc+4, 25, 1)
+#define GET_RX_STATUS_DESC_MORE_DATA_8812(__pRxDesc)			LE_BITS_TO_4BYTE(__pRxDesc+4, 26, 1)
+#define GET_RX_STATUS_DESC_MORE_FRAG_8812(__pRxDesc)			LE_BITS_TO_4BYTE(__pRxDesc+4, 27, 1)
+#define GET_RX_STATUS_DESC_TYPE_8812(__pRxDesc)			LE_BITS_TO_4BYTE(__pRxDesc+4, 28, 2)
+#define GET_RX_STATUS_DESC_MC_8812(__pRxDesc)				LE_BITS_TO_4BYTE(__pRxDesc+4, 30, 1)
+#define GET_RX_STATUS_DESC_BC_8812(__pRxDesc)				LE_BITS_TO_4BYTE(__pRxDesc+4, 31, 1)
+
+/* DWORD 2 */
+#define GET_RX_STATUS_DESC_SEQ_8812(__pRxStatusDesc)					LE_BITS_TO_4BYTE(__pRxStatusDesc+8, 0, 12)
+#define GET_RX_STATUS_DESC_FRAG_8812(__pRxStatusDesc)				LE_BITS_TO_4BYTE(__pRxStatusDesc+8, 12, 4)
+#define GET_RX_STATUS_DESC_RX_IS_QOS_8812(__pRxStatusDesc)			LE_BITS_TO_4BYTE(__pRxStatusDesc+8, 16, 1)
+#define GET_RX_STATUS_DESC_WLANHD_IV_LEN_8812(__pRxStatusDesc)		LE_BITS_TO_4BYTE(__pRxStatusDesc+8, 18, 6)
+#define GET_RX_STATUS_DESC_RPT_SEL_8812(__pRxStatusDesc)			LE_BITS_TO_4BYTE(__pRxStatusDesc+8, 28, 1)
+
+/* DWORD 3 */
+#define GET_RX_STATUS_DESC_RX_RATE_8812(__pRxStatusDesc)				LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 0, 7)
+#define GET_RX_STATUS_DESC_HTC_8812(__pRxStatusDesc)					LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 10, 1)
+#define GET_RX_STATUS_DESC_EOSP_8812(__pRxStatusDesc)					LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 11, 1)
+#define GET_RX_STATUS_DESC_BSSID_FIT_8812(__pRxStatusDesc)			LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 12, 2)
+#ifdef CONFIG_USB_RX_AGGREGATION
+#define GET_RX_STATUS_DESC_USB_AGG_PKTNUM_8812(__pRxStatusDesc)	LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 16, 8)
+#endif
+#define GET_RX_STATUS_DESC_PATTERN_MATCH_8812(__pRxDesc)			LE_BITS_TO_4BYTE(__pRxDesc+12, 29, 1)
+#define GET_RX_STATUS_DESC_UNICAST_MATCH_8812(__pRxDesc)			LE_BITS_TO_4BYTE(__pRxDesc+12, 30, 1)
+#define GET_RX_STATUS_DESC_MAGIC_MATCH_8812(__pRxDesc)			LE_BITS_TO_4BYTE(__pRxDesc+12, 31, 1)
+
+/* DWORD 6 */
+#define GET_RX_STATUS_DESC_SPLCP_8812(__pRxDesc)			LE_BITS_TO_4BYTE(__pRxDesc+16, 0, 1)
+#define GET_RX_STATUS_DESC_LDPC_8812(__pRxDesc)			LE_BITS_TO_4BYTE(__pRxDesc+16, 1, 1)
+#define GET_RX_STATUS_DESC_STBC_8812(__pRxDesc)			LE_BITS_TO_4BYTE(__pRxDesc+16, 2, 1)
+#define GET_RX_STATUS_DESC_BW_8812(__pRxDesc)			LE_BITS_TO_4BYTE(__pRxDesc+16, 4, 2)
+
+/* DWORD 5 */
+#define GET_RX_STATUS_DESC_TSFL_8812(__pRxStatusDesc)				LE_BITS_TO_4BYTE(__pRxStatusDesc+20, 0, 32)
+
+#define GET_RX_STATUS_DESC_BUFF_ADDR_8812(__pRxDesc)		LE_BITS_TO_4BYTE(__pRxDesc+24, 0, 32)
+#define GET_RX_STATUS_DESC_BUFF_ADDR64_8812(__pRxDesc)		LE_BITS_TO_4BYTE(__pRxDesc+28, 0, 32)
+
+#define SET_RX_STATUS_DESC_BUFF_ADDR_8812(__pRxDesc, __Value)	SET_BITS_TO_LE_4BYTE(__pRxDesc+24, 0, 32, __Value)
+
+
+#ifdef CONFIG_SDIO_HCI
+s32 InitRecvPriv8821AS(PADAPTER padapter);
+void FreeRecvPriv8821AS(PADAPTER padapter);
+#endif /* CONFIG_SDIO_HCI */
+
+#ifdef CONFIG_USB_HCI
+void rtl8812au_init_recvbuf(_adapter *padapter, struct recv_buf *precvbuf);
+s32 rtl8812au_init_recv_priv(PADAPTER padapter);
+void rtl8812au_free_recv_priv(PADAPTER padapter);
+#endif
+
+#ifdef CONFIG_PCI_HCI
+s32 rtl8812ae_init_recv_priv(PADAPTER padapter);
+void rtl8812ae_free_recv_priv(PADAPTER padapter);
+#endif
+
+void rtl8812_query_rx_desc_status(union recv_frame *precvframe, u8 *pdesc);
+
+#endif /* __RTL8812A_RECV_H__ */
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/include/rtl8812a_rf.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/rtl8812a_rf.h
--- linux-5.6.3/3rdparty/rtl8821ce/include/rtl8812a_rf.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/rtl8812a_rf.h	2020-04-10 16:35:06.850661655 +0300
@@ -0,0 +1,28 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#ifndef __RTL8812A_RF_H__
+#define __RTL8812A_RF_H__
+
+VOID
+PHY_RF6052SetBandwidth8812(
+	IN	PADAPTER				Adapter,
+	IN	enum channel_width		Bandwidth);
+
+
+int
+PHY_RF6052_Config_8812(
+	IN	PADAPTER	Adapter);
+
+#endif/* __RTL8188E_RF_H__ */
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/include/rtl8812a_spec.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/rtl8812a_spec.h
--- linux-5.6.3/3rdparty/rtl8821ce/include/rtl8812a_spec.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/rtl8812a_spec.h	2020-04-10 16:35:06.850661655 +0300
@@ -0,0 +1,263 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#ifndef __RTL8812A_SPEC_H__
+#define __RTL8812A_SPEC_H__
+
+#include <drv_conf.h>
+
+
+/* ************************************************************
+* 8812 Regsiter offset definition
+* ************************************************************ */
+
+/* ************************************************************
+*
+* ************************************************************ */
+
+/* -----------------------------------------------------
+*
+*	0x0000h ~ 0x00FFh	System Configuration
+*
+* ----------------------------------------------------- */
+#define REG_SYS_CLKR_8812A				0x0008
+#define REG_AFE_PLL_CTRL_8812A		0x0028
+#define REG_HSIMR_8812					0x0058
+#define REG_HSISR_8812					0x005c
+#define REG_GPIO_EXT_CTRL				0x0060
+#define REG_GPIO_STATUS_8812			0x006C
+#define REG_SDIO_CTRL_8812				0x0070
+#define REG_OPT_CTRL_8812				0x0074
+#define REG_RF_B_CTRL_8812				0x0076
+#define REG_FW_DRV_MSG_8812			0x0088
+#define REG_HMEBOX_E2_E3_8812			0x008C
+#define REG_HIMR0_8812					0x00B0
+#define REG_HISR0_8812					0x00B4
+#define REG_HIMR1_8812					0x00B8
+#define REG_HISR1_8812					0x00BC
+#define REG_EFUSE_BURN_GNT_8812		0x00CF
+#define REG_SYS_CFG1_8812				0x00FC
+
+/* -----------------------------------------------------
+*
+*	0x0100h ~ 0x01FFh	MACTOP General Configuration
+*
+* ----------------------------------------------------- */
+#define REG_CR_8812A					0x100
+#define REG_PKTBUF_DBG_ADDR			(REG_PKTBUF_DBG_CTRL)
+#define REG_RXPKTBUF_DBG				(REG_PKTBUF_DBG_CTRL+2)
+#define REG_TXPKTBUF_DBG				(REG_PKTBUF_DBG_CTRL+3)
+#define REG_WOWLAN_WAKE_REASON			REG_MCUTST_WOWLAN
+
+#define REG_RSVD3_8812					0x0168
+#define REG_C2HEVT_CMD_SEQ_88XX		0x01A1
+#define REG_C2hEVT_CMD_CONTENT_88XX	0x01A2
+#define REG_C2HEVT_CMD_LEN_88XX		0x01AE
+
+#define REG_HMEBOX_EXT0_8812			0x01F0
+#define REG_HMEBOX_EXT1_8812			0x01F4
+#define REG_HMEBOX_EXT2_8812			0x01F8
+#define REG_HMEBOX_EXT3_8812			0x01FC
+
+/* -----------------------------------------------------
+*
+*	0x0200h ~ 0x027Fh	TXDMA Configuration
+*
+* ----------------------------------------------------- */
+#define REG_DWBCN0_CTRL_8812				REG_TDECTRL
+#define REG_DWBCN1_CTRL_8812				0x0228
+
+/* -----------------------------------------------------
+*
+*	0x0280h ~ 0x02FFh	RXDMA Configuration
+*
+* ----------------------------------------------------- */
+#define REG_TDECTRL_8812A				0x0208
+#define REG_RXDMA_CONTROL_8812A		0x0286		/*Control the RX DMA.*/
+#define REG_RXDMA_PRO_8812			0x0290
+#define REG_EARLY_MODE_CONTROL_8812	0x02BC
+#define REG_RSVD5_8812					0x02F0
+#define REG_RSVD6_8812					0x02F4
+#define REG_RSVD7_8812					0x02F8
+#define REG_RSVD8_8812					0x02FC
+
+
+/* -----------------------------------------------------
+*
+*	0x0300h ~ 0x03FFh	PCIe
+*
+* ----------------------------------------------------- */
+#define	REG_PCIE_CTRL_REG_8812A			0x0300
+#define	REG_DBI_WDATA_8812			0x0348	/* DBI Write Data */
+#define	REG_DBI_RDATA_8812			0x034C	/* DBI Read Data */
+#define	REG_DBI_ADDR_8812			0x0350	/* DBI Address */
+#define	REG_DBI_FLAG_8812			0x0352	/* DBI Read/Write Flag */
+#define	REG_MDIO_WDATA_8812			0x0354	/* MDIO for Write PCIE PHY */
+#define	REG_MDIO_RDATA_8812			0x0356	/* MDIO for Reads PCIE PHY */
+#define	REG_MDIO_CTL_8812			0x0358	/* MDIO for Control */
+#define REG_PCIE_HRPWM_8812A			0x0361  /* PCIe RPWM */
+#define REG_PCIE_HCPWM_8812A			0x0363  /* PCIe CPWM */
+
+#define	REG_PCIE_MULTIFET_CTRL_8812	0x036A	/* PCIE Multi-Fethc Control */
+
+/* -----------------------------------------------------
+*
+*	0x0400h ~ 0x047Fh	Protocol Configuration
+*
+* ----------------------------------------------------- */
+#define REG_TXPKT_EMPTY_8812A			0x041A
+#define REG_FWHW_TXQ_CTRL_8812A		0x0420
+#define REG_TXBF_CTRL_8812A			0x042C
+#define REG_ARFR0_8812					0x0444
+#define REG_ARFR1_8812					0x044C
+#define REG_CCK_CHECK_8812				0x0454
+#define REG_AMPDU_MAX_TIME_8812		0x0456
+#define REG_TXPKTBUF_BCNQ_BDNY1_8812	0x0457
+
+#define REG_AMPDU_MAX_LENGTH_8812	0x0458
+#define REG_TXPKTBUF_WMAC_LBK_BF_HD_8812	0x045D
+#define REG_NDPA_OPT_CTRL_8812A		0x045F
+#define REG_DATA_SC_8812				0x0483
+#ifdef CONFIG_WOWLAN
+#define REG_TXPKTBUF_IV_LOW             0x0484
+#define REG_TXPKTBUF_IV_HIGH            0x0488
+#endif
+#define REG_ARFR2_8812					0x048C
+#define REG_ARFR3_8812					0x0494
+#define REG_TXRPT_START_OFFSET		0x04AC
+#define REG_AMPDU_BURST_MODE_8812	0x04BC
+#define REG_HT_SINGLE_AMPDU_8812		0x04C7
+#define REG_MACID_PKT_DROP0_8812		0x04D0
+
+/* -----------------------------------------------------
+*
+*	0x0500h ~ 0x05FFh	EDCA Configuration
+*
+* ----------------------------------------------------- */
+#define REG_TXPAUSE_8812A				0x0522
+#define REG_CTWND_8812					0x0572
+#define REG_SECONDARY_CCA_CTRL_8812	0x0577
+#define REG_SCH_TXCMD_8812A			0x05F8
+
+/* -----------------------------------------------------
+*
+*	0x0600h ~ 0x07FFh	WMAC Configuration
+*
+* ----------------------------------------------------- */
+#define REG_MAC_CR_8812				0x0600
+
+#define REG_MAC_TX_SM_STATE_8812		0x06B4
+
+/* Power */
+#define REG_BFMER0_INFO_8812A			0x06E4
+#define REG_BFMER1_INFO_8812A			0x06EC
+#define REG_CSI_RPT_PARAM_BW20_8812A	0x06F4
+#define REG_CSI_RPT_PARAM_BW40_8812A	0x06F8
+#define REG_CSI_RPT_PARAM_BW80_8812A	0x06FC
+
+/* Hardware Port 2 */
+#define REG_BFMEE_SEL_8812A			0x0714
+#define REG_SND_PTCL_CTRL_8812A		0x0718
+
+
+/* -----------------------------------------------------
+*
+*	Redifine register definition for compatibility
+*
+* ----------------------------------------------------- */
+
+/* TODO: use these definition when using REG_xxx naming rule.
+* NOTE: DO NOT Remove these definition. Use later. */
+#define	ISR_8812							REG_HISR0_8812
+
+/* ----------------------------------------------------------------------------
+* 8195 IMR/ISR bits						(offset 0xB0,  8bits)
+* ---------------------------------------------------------------------------- */
+#define	IMR_DISABLED_8812					0
+/* IMR DW0(0x00B0-00B3) Bit 0-31 */
+#define	IMR_TIMER2_8812					BIT31		/* Timeout interrupt 2 */
+#define	IMR_TIMER1_8812					BIT30		/* Timeout interrupt 1	 */
+#define	IMR_PSTIMEOUT_8812				BIT29		/* Power Save Time Out Interrupt */
+#define	IMR_GTINT4_8812					BIT28		/* When GTIMER4 expires, this bit is set to 1	 */
+#define	IMR_GTINT3_8812					BIT27		/* When GTIMER3 expires, this bit is set to 1	 */
+#define	IMR_TXBCN0ERR_8812				BIT26		/* Transmit Beacon0 Error			 */
+#define	IMR_TXBCN0OK_8812					BIT25		/* Transmit Beacon0 OK			 */
+#define	IMR_TSF_BIT32_TOGGLE_8812		BIT24		/* TSF Timer BIT32 toggle indication interrupt			 */
+#define	IMR_BCNDMAINT0_8812				BIT20		/* Beacon DMA Interrupt 0			 */
+#define	IMR_BCNDERR0_8812					BIT16		/* Beacon Queue DMA OK0			 */
+#define	IMR_HSISR_IND_ON_INT_8812		BIT15		/* HSISR Indicator (HSIMR & HSISR is true, this bit is set to 1) */
+#define	IMR_BCNDMAINT_E_8812				BIT14		/* Beacon DMA Interrupt Extension for Win7			 */
+#define	IMR_ATIMEND_8812					BIT12		/* CTWidnow End or ATIM Window End */
+#define	IMR_C2HCMD_8812					BIT10		/* CPU to Host Command INT Status, Write 1 clear	 */
+#define	IMR_CPWM2_8812					BIT9			/* CPU power Mode exchange INT Status, Write 1 clear	 */
+#define	IMR_CPWM_8812						BIT8			/* CPU power Mode exchange INT Status, Write 1 clear	 */
+#define	IMR_HIGHDOK_8812					BIT7			/* High Queue DMA OK	 */
+#define	IMR_MGNTDOK_8812					BIT6			/* Management Queue DMA OK	 */
+#define	IMR_BKDOK_8812					BIT5			/* AC_BK DMA OK		 */
+#define	IMR_BEDOK_8812					BIT4			/* AC_BE DMA OK	 */
+#define	IMR_VIDOK_8812					BIT3			/* AC_VI DMA OK		 */
+#define	IMR_VODOK_8812					BIT2			/* AC_VO DMA OK	 */
+#define	IMR_RDU_8812						BIT1			/* Rx Descriptor Unavailable	 */
+#define	IMR_ROK_8812						BIT0			/* Receive DMA OK */
+
+/* IMR DW1(0x00B4-00B7) Bit 0-31 */
+#define	IMR_BCNDMAINT7_8812				BIT27		/* Beacon DMA Interrupt 7 */
+#define	IMR_BCNDMAINT6_8812				BIT26		/* Beacon DMA Interrupt 6 */
+#define	IMR_BCNDMAINT5_8812				BIT25		/* Beacon DMA Interrupt 5 */
+#define	IMR_BCNDMAINT4_8812				BIT24		/* Beacon DMA Interrupt 4 */
+#define	IMR_BCNDMAINT3_8812				BIT23		/* Beacon DMA Interrupt 3 */
+#define	IMR_BCNDMAINT2_8812				BIT22		/* Beacon DMA Interrupt 2 */
+#define	IMR_BCNDMAINT1_8812				BIT21		/* Beacon DMA Interrupt 1 */
+#define	IMR_BCNDOK7_8812					BIT20		/* Beacon Queue DMA OK Interrup 7 */
+#define	IMR_BCNDOK6_8812					BIT19		/* Beacon Queue DMA OK Interrup 6 */
+#define	IMR_BCNDOK5_8812					BIT18		/* Beacon Queue DMA OK Interrup 5 */
+#define	IMR_BCNDOK4_8812					BIT17		/* Beacon Queue DMA OK Interrup 4 */
+#define	IMR_BCNDOK3_8812					BIT16		/* Beacon Queue DMA OK Interrup 3 */
+#define	IMR_BCNDOK2_8812					BIT15		/* Beacon Queue DMA OK Interrup 2 */
+#define	IMR_BCNDOK1_8812					BIT14		/* Beacon Queue DMA OK Interrup 1 */
+#define	IMR_ATIMEND_E_8812				BIT13		/* ATIM Window End Extension for Win7 */
+#define	IMR_TXERR_8812					BIT11		/* Tx Error Flag Interrupt Status, write 1 clear. */
+#define	IMR_RXERR_8812					BIT10		/* Rx Error Flag INT Status, Write 1 clear */
+#define	IMR_TXFOVW_8812					BIT9			/* Transmit FIFO Overflow */
+#define	IMR_RXFOVW_8812					BIT8			/* Receive FIFO Overflow */
+
+
+#ifdef CONFIG_PCI_HCI
+/* #define IMR_RX_MASK		(IMR_ROK_8812|IMR_RDU_8812|IMR_RXFOVW_8812) */
+#define IMR_TX_MASK			(IMR_VODOK_8812 | IMR_VIDOK_8812 | IMR_BEDOK_8812 | IMR_BKDOK_8812 | IMR_MGNTDOK_8812 | IMR_HIGHDOK_8812)
+
+#define RT_BCN_INT_MASKS	(IMR_BCNDMAINT0_8812 | IMR_TXBCN0OK_8812 | IMR_TXBCN0ERR_8812 | IMR_BCNDERR0_8812)
+
+#define RT_AC_INT_MASKS	(IMR_VIDOK_8812 | IMR_VODOK_8812 | IMR_BEDOK_8812 | IMR_BKDOK_8812)
+#endif
+
+
+/* ****************************************************************************
+* Regsiter Bit and Content definition
+* **************************************************************************** */
+
+/* 2 ACMHWCTRL 0x05C0 */
+#define	AcmHw_HwEn_8812				BIT(0)
+#define	AcmHw_VoqEn_8812				BIT(1)
+#define	AcmHw_ViqEn_8812				BIT(2)
+#define	AcmHw_BeqEn_8812				BIT(3)
+#define	AcmHw_VoqStatus_8812			BIT(5)
+#define	AcmHw_ViqStatus_8812			BIT(6)
+#define	AcmHw_BeqStatus_8812			BIT(7)
+
+#endif /* __RTL8812A_SPEC_H__ */
+
+#ifdef CONFIG_RTL8821A
+#include "rtl8821a_spec.h"
+#endif /* CONFIG_RTL8821A */
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/include/rtl8812a_sreset.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/rtl8812a_sreset.h
--- linux-5.6.3/3rdparty/rtl8821ce/include/rtl8812a_sreset.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/rtl8812a_sreset.h	2020-04-10 16:35:06.850661655 +0300
@@ -0,0 +1,24 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#ifndef _RTL88812A_SRESET_H_
+#define _RTL8812A_SRESET_H_
+
+#include <rtw_sreset.h>
+
+#ifdef DBG_CONFIG_ERROR_DETECT
+extern void rtl8812_sreset_xmit_status_check(_adapter *padapter);
+extern void rtl8812_sreset_linked_status_check(_adapter *padapter);
+#endif
+#endif
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/include/rtl8812a_xmit.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/rtl8812a_xmit.h
--- linux-5.6.3/3rdparty/rtl8821ce/include/rtl8812a_xmit.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/rtl8812a_xmit.h	2020-04-10 16:35:06.850661655 +0300
@@ -0,0 +1,367 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#ifndef __RTL8812A_XMIT_H__
+#define __RTL8812A_XMIT_H__
+
+
+/* For 88e early mode */
+#define SET_EARLYMODE_PKTNUM(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr, 0, 3, __Value)
+#define SET_EARLYMODE_LEN0(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr, 4, 12, __Value)
+#define SET_EARLYMODE_LEN1(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr, 16, 12, __Value)
+#define SET_EARLYMODE_LEN2_1(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr, 28, 4, __Value)
+#define SET_EARLYMODE_LEN2_2(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr+4, 0, 8, __Value)
+#define SET_EARLYMODE_LEN3(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr+4, 8, 12, __Value)
+#define SET_EARLYMODE_LEN4(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr+4, 20, 12, __Value)
+
+/*
+ * defined for TX DESC Operation
+ *   */
+
+#define MAX_TID (15)
+
+/* OFFSET 0 */
+#define OFFSET_SZ	0
+#define OFFSET_SHT	16
+#define BMC			BIT(24)
+#define LSG			BIT(26)
+#define FSG			BIT(27)
+#define OWN		BIT(31)
+
+
+/* OFFSET 4 */
+#define PKT_OFFSET_SZ		0
+#define QSEL_SHT			8
+#define RATE_ID_SHT			16
+#define NAVUSEHDR			BIT(20)
+#define SEC_TYPE_SHT		22
+#define PKT_OFFSET_SHT		26
+
+/* OFFSET 8 */
+#define AGG_EN				BIT(12)
+#define AGG_BK				BIT(16)
+#define AMPDU_DENSITY_SHT	20
+#define ANTSEL_A			BIT(24)
+#define ANTSEL_B			BIT(25)
+#define TX_ANT_CCK_SHT		26
+#define TX_ANTL_SHT			28
+#define TX_ANT_HT_SHT		30
+
+/* OFFSET 12 */
+#define SEQ_SHT				16
+#define EN_HWSEQ			BIT(31)
+
+/* OFFSET 16 */
+#define QOS					BIT(6)
+#define	HW_SSN				BIT(7)
+#define USERATE				BIT(8)
+#define DISDATAFB			BIT(10)
+#define CTS_2_SELF			BIT(11)
+#define	RTS_EN				BIT(12)
+#define	HW_RTS_EN			BIT(13)
+#define DATA_SHORT			BIT(24)
+#define PWR_STATUS_SHT	15
+#define DATA_SC_SHT		20
+#define DATA_BW				BIT(25)
+
+/* OFFSET 20 */
+#define	RTY_LMT_EN			BIT(17)
+
+/* OFFSET 20 */
+#define SGI					BIT(6)
+#define USB_TXAGG_NUM_SHT	24
+
+typedef struct txdescriptor_8812 {
+	/* Offset 0 */
+	u32 pktlen:16;
+	u32 offset:8;
+	u32 bmc:1;
+	u32 htc:1;
+	u32 ls:1;
+	u32 fs:1;
+	u32 linip:1;
+	u32 noacm:1;
+	u32 gf:1;
+	u32 own:1;
+
+	/* Offset 4 */
+	u32 macid:6;
+	u32 rsvd0406:2;
+	u32 qsel:5;
+	u32 rd_nav_ext:1;
+	u32 lsig_txop_en:1;
+	u32 pifs:1;
+	u32 rate_id:4;
+	u32 navusehdr:1;
+	u32 en_desc_id:1;
+	u32 sectype:2;
+	u32 rsvd0424:2;
+	u32 pkt_offset:5;	/* unit: 8 bytes */
+	u32 rsvd0431:1;
+
+	/* Offset 8 */
+	u32 rts_rc:6;
+	u32 data_rc:6;
+	u32 agg_en:1;
+	u32 rd_en:1;
+	u32 bar_rty_th:2;
+	u32 bk:1;
+	u32 morefrag:1;
+	u32 raw:1;
+	u32 ccx:1;
+	u32 ampdu_density:3;
+	u32 bt_null:1;
+	u32 ant_sel_a:1;
+	u32 ant_sel_b:1;
+	u32 tx_ant_cck:2;
+	u32 tx_antl:2;
+	u32 tx_ant_ht:2;
+
+	/* Offset 12 */
+	u32 nextheadpage:8;
+	u32 tailpage:8;
+	u32 seq:12;
+	u32 cpu_handle:1;
+	u32 tag1:1;
+	u32 trigger_int:1;
+	u32 hwseq_en:1;
+
+	/* Offset 16 */
+	u32 rtsrate:5;
+	u32 ap_dcfe:1;
+	u32 hwseq_sel:2;
+	u32 userate:1;
+	u32 disrtsfb:1;
+	u32 disdatafb:1;
+	u32 cts2self:1;
+	u32 rtsen:1;
+	u32 hw_rts_en:1;
+	u32 port_id:1;
+	u32 pwr_status:3;
+	u32 wait_dcts:1;
+	u32 cts2ap_en:1;
+	u32 data_sc:2;
+	u32 data_stbc:2;
+	u32 data_short:1;
+	u32 data_bw:1;
+	u32 rts_short:1;
+	u32 rts_bw:1;
+	u32 rts_sc:2;
+	u32 vcs_stbc:2;
+
+	/* Offset 20 */
+	u32 datarate:6;
+	u32 sgi:1;
+	u32 try_rate:1;
+	u32 data_ratefb_lmt:5;
+	u32 rts_ratefb_lmt:4;
+	u32 rty_lmt_en:1;
+	u32 data_rt_lmt:6;
+	u32 usb_txagg_num:8;
+
+	/* Offset 24 */
+	u32 txagg_a:5;
+	u32 txagg_b:5;
+	u32 use_max_len:1;
+	u32 max_agg_num:5;
+	u32 mcsg1_max_len:4;
+	u32 mcsg2_max_len:4;
+	u32 mcsg3_max_len:4;
+	u32 mcs7_sgi_max_len:4;
+
+	/* Offset 28 */
+	u32 checksum:16;	/* TxBuffSize(PCIe)/CheckSum(USB) */
+	u32 mcsg4_max_len:4;
+	u32 mcsg5_max_len:4;
+	u32 mcsg6_max_len:4;
+	u32 mcs15_sgi_max_len:4;
+
+	/* Offset 32 */
+	u32 rsvd32;
+
+	/* Offset 36 */
+	u32 rsvd36;
+} TXDESC_8812, *PTXDESC_8812;
+
+
+/* Dword 0 */
+#define GET_TX_DESC_OWN_8812(__pTxDesc)				LE_BITS_TO_4BYTE(__pTxDesc, 31, 1)
+#define SET_TX_DESC_PKT_SIZE_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 0, 16, __Value)
+#define SET_TX_DESC_OFFSET_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 16, 8, __Value)
+#define SET_TX_DESC_BMC_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 24, 1, __Value)
+#define SET_TX_DESC_HTC_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 25, 1, __Value)
+#define SET_TX_DESC_LAST_SEG_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 26, 1, __Value)
+#define SET_TX_DESC_FIRST_SEG_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 27, 1, __Value)
+#define SET_TX_DESC_LINIP_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 28, 1, __Value)
+#define SET_TX_DESC_NO_ACM_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 29, 1, __Value)
+#define SET_TX_DESC_GF_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 30, 1, __Value)
+#define SET_TX_DESC_OWN_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 31, 1, __Value)
+
+/* Dword 1 */
+#define SET_TX_DESC_MACID_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 0, 7, __Value)
+#define SET_TX_DESC_QUEUE_SEL_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 8, 5, __Value)
+#define SET_TX_DESC_RDG_NAV_EXT_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 13, 1, __Value)
+#define SET_TX_DESC_LSIG_TXOP_EN_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 14, 1, __Value)
+#define SET_TX_DESC_PIFS_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 15, 1, __Value)
+#define SET_TX_DESC_RATE_ID_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 16, 5, __Value)
+#define SET_TX_DESC_EN_DESC_ID_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 21, 1, __Value)
+#define SET_TX_DESC_SEC_TYPE_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 22, 2, __Value)
+#define SET_TX_DESC_PKT_OFFSET_8812(__pTxDesc, __Value)		SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 24, 5, __Value)
+
+/* Dword 2 */
+#define SET_TX_DESC_PAID_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 0,  9, __Value)
+#define SET_TX_DESC_CCA_RTS_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 10, 2, __Value)
+#define SET_TX_DESC_AGG_ENABLE_8812(__pTxDesc, __Value)		SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 12, 1, __Value)
+#define SET_TX_DESC_RDG_ENABLE_8812(__pTxDesc, __Value)		SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 13, 1, __Value)
+#define SET_TX_DESC_AGG_BREAK_8812(__pTxDesc, __Value)				SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 16, 1, __Value)
+#define SET_TX_DESC_MORE_FRAG_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 17, 1, __Value)
+#define SET_TX_DESC_RAW_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 18, 1, __Value)
+#define SET_TX_DESC_SPE_RPT_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 19, 1, __Value)
+#define SET_TX_DESC_AMPDU_DENSITY_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 20, 3, __Value)
+#define SET_TX_DESC_BT_INT_8812(__pTxDesc, __Value)			SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 23, 1, __Value)
+#define SET_TX_DESC_GID_8812(__pTxDesc, __Value)			SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 24, 6, __Value)
+
+/* Dword 3 */
+#define SET_TX_DESC_WHEADER_LEN_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 0, 4, __Value)
+#define SET_TX_DESC_CHK_EN_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 4, 1, __Value)
+#define SET_TX_DESC_EARLY_MODE_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 5, 1, __Value)
+#define SET_TX_DESC_HWSEQ_SEL_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 6, 2, __Value)
+#define SET_TX_DESC_USE_RATE_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 8, 1, __Value)
+#define SET_TX_DESC_DISABLE_RTS_FB_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 9, 1, __Value)
+#define SET_TX_DESC_DISABLE_FB_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 10, 1, __Value)
+#define SET_TX_DESC_CTS2SELF_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 11, 1, __Value)
+#define SET_TX_DESC_RTS_ENABLE_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 12, 1, __Value)
+#define SET_TX_DESC_HW_RTS_ENABLE_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 13, 1, __Value)
+#define SET_TX_DESC_NAV_USE_HDR_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 15, 1, __Value)
+#define SET_TX_DESC_USE_MAX_LEN_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 16, 1, __Value)
+#define SET_TX_DESC_MAX_AGG_NUM_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 17, 5, __Value)
+#define SET_TX_DESC_NDPA_8812(__pTxDesc, __Value)		SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 22, 2, __Value)
+#define SET_TX_DESC_AMPDU_MAX_TIME_8812(__pTxDesc, __Value)		SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 24, 8, __Value)
+
+/* Dword 4 */
+#define SET_TX_DESC_TX_RATE_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 0, 7, __Value)
+#define SET_TX_DESC_DATA_RATE_FB_LIMIT_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 8, 5, __Value)
+#define SET_TX_DESC_RTS_RATE_FB_LIMIT_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 13, 4, __Value)
+#define SET_TX_DESC_RETRY_LIMIT_ENABLE_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 17, 1, __Value)
+#define SET_TX_DESC_DATA_RETRY_LIMIT_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 18, 6, __Value)
+#define SET_TX_DESC_RTS_RATE_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 24, 5, __Value)
+
+/* Dword 5 */
+#define SET_TX_DESC_DATA_SC_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 0, 4, __Value)
+#define SET_TX_DESC_DATA_SHORT_8812(__pTxDesc, __Value)	SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 4, 1, __Value)
+#define SET_TX_DESC_DATA_BW_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 5, 2, __Value)
+#define SET_TX_DESC_DATA_LDPC_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 7, 1, __Value)
+#define SET_TX_DESC_DATA_STBC_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 8, 2, __Value)
+#define SET_TX_DESC_CTROL_STBC_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 10, 2, __Value)
+#define SET_TX_DESC_RTS_SHORT_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 12, 1, __Value)
+#define SET_TX_DESC_RTS_SC_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 13, 4, __Value)
+#define SET_TX_DESC_TX_ANT_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 24, 4, __Value)
+
+/* Dword 6 */
+#define SET_TX_DESC_SW_DEFINE_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 0, 12, __Value)
+#define SET_TX_DESC_ANTSEL_A_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 16, 3, __Value)
+#define SET_TX_DESC_ANTSEL_B_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 19, 3, __Value)
+#define SET_TX_DESC_ANTSEL_C_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 22, 3, __Value)
+#define SET_TX_DESC_ANTSEL_D_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 25, 3, __Value)
+#define SET_TX_DESC_MBSSID_8821(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 12, 4, __Value)
+
+/* Dword 7 */
+#define SET_TX_DESC_TX_BUFFER_SIZE_8812(__pTxDesc, __Value)		SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 0, 16, __Value)
+#define SET_TX_DESC_TX_DESC_CHECKSUM_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 0, 16, __Value)
+#define SET_TX_DESC_USB_TXAGG_NUM_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 24, 8, __Value)
+#ifdef CONFIG_SDIO_HCI
+#define SET_TX_DESC_SDIO_TXSEQ_8812(__pTxDesc, __Value)			SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 16, 8, __Value)
+#endif
+
+/* Dword 8 */
+#define SET_TX_DESC_HWSEQ_EN_8812(__pTxDesc, __Value)			SET_BITS_TO_LE_4BYTE(__pTxDesc+32, 15, 1, __Value)
+
+/* Dword 9 */
+#define SET_TX_DESC_SEQ_8812(__pTxDesc, __Value)					SET_BITS_TO_LE_4BYTE(__pTxDesc+36, 12, 12, __Value)
+
+/* Dword 10 */
+#define SET_TX_DESC_TX_BUFFER_ADDRESS_8812(__pTxDesc, __Value)	SET_BITS_TO_LE_4BYTE(__pTxDesc+40, 0, 32, __Value)
+#define GET_TX_DESC_TX_BUFFER_ADDRESS_8812(__pTxDesc)	LE_BITS_TO_4BYTE(__pTxDesc+40, 0, 32)
+
+/* Dword 11 */
+#define SET_TX_DESC_NEXT_DESC_ADDRESS_8812(__pTxDesc, __Value)	SET_BITS_TO_LE_4BYTE(__pTxDesc+48, 0, 32, __Value)
+
+
+#define SET_EARLYMODE_PKTNUM_8812(__pAddr, __Value)					SET_BITS_TO_LE_4BYTE(__pAddr, 0, 4, __Value)
+#define SET_EARLYMODE_LEN0_8812(__pAddr, __Value)					SET_BITS_TO_LE_4BYTE(__pAddr, 4, 15, __Value)
+#define SET_EARLYMODE_LEN1_1_8812(__pAddr, __Value)					SET_BITS_TO_LE_4BYTE(__pAddr, 19, 13, __Value)
+#define SET_EARLYMODE_LEN1_2_8812(__pAddr, __Value)					SET_BITS_TO_LE_4BYTE(__pAddr+4, 0, 2, __Value)
+#define SET_EARLYMODE_LEN2_8812(__pAddr, __Value)					SET_BITS_TO_LE_4BYTE(__pAddr+4, 2, 15,  __Value)
+#define SET_EARLYMODE_LEN3_8812(__pAddr, __Value)					SET_BITS_TO_LE_4BYTE(__pAddr+4, 17, 15, __Value)
+
+#ifdef CONFIG_TX_EARLY_MODE
+	#define USB_DUMMY_OFFSET		2
+#else
+	#define USB_DUMMY_OFFSET		1
+#endif
+#define USB_DUMMY_LENGTH		(USB_DUMMY_OFFSET * PACKET_OFFSET_SZ)
+
+
+void rtl8812a_cal_txdesc_chksum(u8 *ptxdesc);
+void rtl8812a_fill_fake_txdesc(PADAPTER	padapter, u8 *pDesc, u32 BufferLen, u8 IsPsPoll, u8	IsBTQosNull, u8 bDataFrame);
+void rtl8812a_fill_txdesc_sectype(struct pkt_attrib *pattrib, u8 *ptxdesc);
+void rtl8812a_fill_txdesc_vcs(PADAPTER padapter, struct pkt_attrib *pattrib, u8 *ptxdesc);
+void rtl8812a_fill_txdesc_phy(PADAPTER padapter, struct pkt_attrib *pattrib, u8 *ptxdesc);
+#if defined(CONFIG_CONCURRENT_MODE)
+void fill_txdesc_force_bmc_camid(struct pkt_attrib *pattrib, u8 *ptxdesc);
+#endif
+void fill_txdesc_bmc_tx_rate(struct pkt_attrib *pattrib, u8 *ptxdesc);
+
+#ifdef CONFIG_USB_HCI
+s32 rtl8812au_init_xmit_priv(PADAPTER padapter);
+void rtl8812au_free_xmit_priv(PADAPTER padapter);
+s32 rtl8812au_hal_xmit(PADAPTER padapter, struct xmit_frame *pxmitframe);
+s32 rtl8812au_mgnt_xmit(PADAPTER padapter, struct xmit_frame *pmgntframe);
+s32	 rtl8812au_hal_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe);
+s32 rtl8812au_xmit_buf_handler(PADAPTER padapter);
+void rtl8812au_xmit_tasklet(void *priv);
+s32 rtl8812au_xmitframe_complete(_adapter *padapter, struct xmit_priv *pxmitpriv, struct xmit_buf *pxmitbuf);
+#endif
+
+#ifdef CONFIG_PCI_HCI
+s32 rtl8812ae_init_xmit_priv(PADAPTER padapter);
+void rtl8812ae_free_xmit_priv(PADAPTER padapter);
+struct xmit_buf *rtl8812ae_dequeue_xmitbuf(struct rtw_tx_ring *ring);
+void	rtl8812ae_xmitframe_resume(_adapter *padapter);
+s32 rtl8812ae_hal_xmit(PADAPTER padapter, struct xmit_frame *pxmitframe);
+s32 rtl8812ae_mgnt_xmit(PADAPTER padapter, struct xmit_frame *pmgntframe);
+s32	rtl8812ae_hal_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe);
+void rtl8812ae_xmit_tasklet(void *priv);
+
+#ifdef CONFIG_XMIT_THREAD_MODE
+s32 rtl8812ae_xmit_buf_handler(_adapter *padapter);
+#endif
+
+#endif
+
+#ifdef CONFIG_TX_EARLY_MODE
+void UpdateEarlyModeInfo8812(struct xmit_priv *pxmitpriv, struct xmit_buf *pxmitbuf);
+#endif
+
+void _dbg_dump_tx_info(_adapter	*padapter, int frame_tag, u8 *ptxdesc);
+
+u8	BWMapping_8812(PADAPTER Adapter, struct pkt_attrib *pattrib);
+
+u8	SCMapping_8812(PADAPTER Adapter, struct pkt_attrib	*pattrib);
+
+#endif /* __RTL8812_XMIT_H__ */
+
+#ifdef CONFIG_RTL8821A
+#include "rtl8821a_xmit.h"
+#endif /* CONFIG_RTL8821A */
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/include/rtl8814a_cmd.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/rtl8814a_cmd.h
--- linux-5.6.3/3rdparty/rtl8821ce/include/rtl8814a_cmd.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/rtl8814a_cmd.h	2020-04-10 16:35:06.850661655 +0300
@@ -0,0 +1,162 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#ifndef __RTL8814A_CMD_H__
+#define __RTL8814A_CMD_H__
+#include "hal_com_h2c.h"
+
+/* _RSVDPAGE_LOC_CMD0 */
+#define SET_8814A_H2CCMD_RSVDPAGE_LOC_PROBE_RSP(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
+#define SET_8814A_H2CCMD_RSVDPAGE_LOC_PSPOLL(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 8, __Value)
+#define SET_8814A_H2CCMD_RSVDPAGE_LOC_NULL_DATA(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value)
+#define SET_8814A_H2CCMD_RSVDPAGE_LOC_QOS_NULL_DATA(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 8, __Value)
+#define SET_8814A_H2CCMD_RSVDPAGE_LOC_BT_QOS_NULL_DATA(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 0, 8, __Value)
+
+/* _SETPWRMODE_PARM */
+#define SET_8814A_H2CCMD_PWRMODE_PARM_MODE(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
+#define SET_8814A_H2CCMD_PWRMODE_PARM_RLBM(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 4, __Value)
+#define SET_8814A_H2CCMD_PWRMODE_PARM_SMART_PS(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 4, 4, __Value)
+#define SET_8814A_H2CCMD_PWRMODE_PARM_BCN_PASS_TIME(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value)
+#define SET_8814A_H2CCMD_PWRMODE_PARM_ALL_QUEUE_UAPSD(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 8, __Value)
+#define SET_8814A_H2CCMD_PWRMODE_PARM_BCN_EARLY_C2H_RPT(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 2, 1, __Value)
+#define SET_8814A_H2CCMD_PWRMODE_PARM_PWR_STATE(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 0, 8, __Value)
+
+#define GET_8814A_H2CCMD_PWRMODE_PARM_MODE(__pH2CCmd)					LE_BITS_TO_1BYTE(__pH2CCmd, 0, 8)
+
+
+/* _WoWLAN PARAM_CMD5 */
+#define SET_8814A_H2CCMD_WOWLAN_FUNC_ENABLE(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 1, __Value)
+#define SET_8814A_H2CCMD_WOWLAN_PATTERN_MATCH_ENABLE(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd, 1, 1, __Value)
+#define SET_8814A_H2CCMD_WOWLAN_MAGIC_PKT_ENABLE(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd, 2, 1, __Value)
+#define SET_8814A_H2CCMD_WOWLAN_UNICAST_PKT_ENABLE(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd, 3, 1, __Value)
+#define SET_8814A_H2CCMD_WOWLAN_ALL_PKT_DROP(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd, 4, 1, __Value)
+#define SET_8814A_H2CCMD_WOWLAN_GPIO_ACTIVE(__pH2CCmd, __Value)				SET_BITS_TO_LE_1BYTE(__pH2CCmd, 5, 1, __Value)
+#define SET_8814A_H2CCMD_WOWLAN_REKEY_WAKE_UP(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd, 6, 1, __Value)
+#define SET_8814A_H2CCMD_WOWLAN_DISCONNECT_WAKE_UP(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd, 7, 1, __Value)
+#define SET_8814A_H2CCMD_WOWLAN_GPIONUM(__pH2CCmd, __Value)					SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 8, __Value)
+#define SET_8814A_H2CCMD_WOWLAN_GPIO_DURATION(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value)
+
+
+/* WLANINFO_PARM */
+#define SET_8814A_H2CCMD_WLANINFO_PARM_OPMODE(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
+#define SET_8814A_H2CCMD_WLANINFO_PARM_CHANNEL(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 8, __Value)
+#define SET_8814A_H2CCMD_WLANINFO_PARM_BW40MHZ(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value)
+
+/* _REMOTE_WAKEUP_CMD7 */
+#define SET_8814A_H2CCMD_REMOTE_WAKECTRL_ENABLE(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 1, __Value)
+#define SET_8814A_H2CCMD_REMOTE_WAKE_CTRL_ARP_OFFLOAD_EN(__pH2CCmd, __Value)				SET_BITS_TO_LE_1BYTE(__pH2CCmd, 1, 1, __Value)
+#define SET_8814A_H2CCMD_REMOTE_WAKE_CTRL_NDP_OFFLOAD_EN(__pH2CCmd, __Value)				SET_BITS_TO_LE_1BYTE(__pH2CCmd, 2, 1, __Value)
+#define SET_8814A_H2CCMD_REMOTE_WAKE_CTRL_GTK_OFFLOAD_EN(__pH2CCmd, __Value)				SET_BITS_TO_LE_1BYTE(__pH2CCmd, 3, 1, __Value)
+
+
+/* _AP_OFFLOAD_CMD8 */
+#define SET_8814A_H2CCMD_AP_OFFLOAD_ON(__pH2CCmd, __Value)				SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
+#define SET_8814A_H2CCMD_AP_OFFLOAD_HIDDEN(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 8, __Value)
+#define SET_8814A_H2CCMD_AP_OFFLOAD_DENYANY(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value)
+#define SET_8814A_H2CCMD_AP_OFFLOAD_WAKEUP_EVT_RPT(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 8, __Value)
+
+/* _PWR_MOD_CMD20 */
+#define SET_88E_H2CCMD_PWRMODE_PARM_MODE(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
+#define SET_88E_H2CCMD_PWRMODE_PARM_RLBM(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 4, __Value)
+#define SET_88E_H2CCMD_PWRMODE_PARM_SMART_PS(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 4, 4, __Value)
+#define SET_88E_H2CCMD_PWRMODE_PARM_BCN_PASS_TIME(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value)
+#define SET_88E_H2CCMD_PWRMODE_PARM_ALL_QUEUE_UAPSD(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 8, __Value)
+#define SET_88E_H2CCMD_PWRMODE_PARM_PWR_STATE(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 0, 8, __Value)
+
+/*	AP_REQ_TXREP_CMD 0x43	*/
+#define SET_8814A_H2CCMD_TXREP_PARM_STA1(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
+#define SET_8814A_H2CCMD_TXREP_PARM_STA2(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 8, __Value)
+#define SET_8814A_H2CCMD_TXREP_PARM_RTY(__pH2CCmd, __Value)				SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 2, __Value)
+
+/*		C2H_AP_REQ_TXRPT		*/
+#define	GET_8814A_C2H_TC2H_APREQ_TXRPT_MACID1(_Header)			LE_BITS_TO_1BYTE((_Header + 0), 0, 8)
+#define	GET_8814A_C2H_TC2H_APREQ_TXRPT_TXOK1(_Header)			LE_BITS_TO_2BYTE((_Header + 1), 0, 16)
+#define	GET_8814A_C2H_TC2H_APREQ_TXRPT_TXFAIL1(_Header)			LE_BITS_TO_2BYTE((_Header + 3), 0, 16)
+#define	GET_8814A_C2H_TC2H_APREQ_TXRPT_INIRATE1(_Header)		LE_BITS_TO_1BYTE((_Header + 5), 0, 8)
+#define	GET_8814A_C2H_TC2H_APREQ_TXRPT_MACID2(_Header)			LE_BITS_TO_1BYTE((_Header + 6), 0, 8)
+#define	GET_8814A_C2H_TC2H_APREQ_TXRPT_TXOK2(_Header)			LE_BITS_TO_2BYTE((_Header + 7), 0, 16)
+#define	GET_8814A_C2H_TC2H_APREQ_TXRPT_TXFAIL2(_Header)			LE_BITS_TO_2BYTE((_Header + 9), 0, 16)
+#define	GET_8814A_C2H_TC2H_APREQ_TXRPT_INIRATE2(_Header)		LE_BITS_TO_1BYTE((_Header + 11), 0, 8)
+
+/*		C2H_SPC_STAT			*/
+#define	GET_8814A_C2H_SPC_STAT_IDX(_Header)						LE_BITS_TO_1BYTE((_Header + 0), 0, 8)
+	/*	Tip :TYPE_A data3 is msb and data0 is lsb	*/
+#define	GET_8814A_C2H_SPC_STAT_TYPEA_RETRY(_Header)				LE_BITS_TO_4BYTE((_Header + 1), 0, 32)
+#define	GET_8814A_C2H_SPC_STAT_TYPEB_PKT1(_Header)				LE_BITS_TO_2BYTE((_Header + 1), 0, 16)
+#define	GET_8814A_C2H_SPC_STAT_TYPEB_RETRY1(_Header)			LE_BITS_TO_2BYTE((_Header + 3), 0, 16)
+#define	GET_8814A_C2H_SPC_STAT_TYPEB_PKT2(_Header)				LE_BITS_TO_2BYTE((_Header + 5), 0, 16)
+#define	GET_8814A_C2H_SPC_STAT_TYPEB_RETRY2(_Header)			LE_BITS_TO_2BYTE((_Header + 7), 0, 16)
+
+/*BCNHWSEQ*/
+#define SET_8814A_H2CCMD_BCNHWSEQ_EN(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE((__pH2CCmd), 0, 1, __Value)
+#define SET_8814A_H2CCMD_BCNHWSEQ_BCN_NUMBER(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE((__pH2CCmd), 1, 3, __Value)
+#define SET_8814A_H2CCMD_BCNHWSEQ_HWSEQ(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE((__pH2CCmd), 6, 1, __Value)
+#define SET_8814A_H2CCMD_BCNHWSEQ_EXHWSEQ(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE((__pH2CCmd), 7, 1, __Value)
+#define SET_8814A_H2CCMD_BCNHWSEQ_PAGE(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 8, __Value)
+void rtl8814_fw_update_beacon_cmd(_adapter *padapter);
+
+/* TX Beamforming */
+#define GET_8814A_C2H_TXBF_ORIGINATE(_Header)			LE_BITS_TO_1BYTE(_Header, 0, 8)
+#define GET_8814A_C2H_TXBF_MACID(_Header)				LE_BITS_TO_1BYTE((_Header + 1), 0, 8)
+
+
+
+/* / TX Feedback Content */
+#define	USEC_UNIT_FOR_8814A_C2H_TX_RPT_QUEUE_TIME			256
+
+#define	GET_8814A_C2H_TX_RPT_QUEUE_SELECT(_Header)			LE_BITS_TO_1BYTE((_Header + 0), 0, 5)
+#define	GET_8814A_C2H_TX_RPT_PKT_BROCAST(_Header)			LE_BITS_TO_1BYTE((_Header + 0), 5, 1)
+#define	GET_8814A_C2H_TX_RPT_LIFE_TIME_OVER(_Header)			LE_BITS_TO_1BYTE((_Header + 0), 6, 1)
+#define	GET_8814A_C2H_TX_RPT_RETRY_OVER(_Header)				LE_BITS_TO_1BYTE((_Header + 0), 7, 1)
+#define	GET_8814A_C2H_TX_RPT_MAC_ID(_Header)					LE_BITS_TO_1BYTE((_Header + 1), 0, 8)
+#define	GET_8814A_C2H_TX_RPT_DATA_RETRY_CNT(_Header)		LE_BITS_TO_1BYTE((_Header + 2), 0, 6)
+#define	GET_8814A_C2H_TX_RPT_QUEUE_TIME(_Header)				LE_BITS_TO_2BYTE((_Header + 3), 0, 16)	/* In unit of 256 microseconds. */
+#define	GET_8814A_C2H_TX_RPT_FINAL_DATA_RATE(_Header)		LE_BITS_TO_1BYTE((_Header + 5), 0, 8)
+
+
+/* _P2P_PS_OFFLOAD */
+#define SET_8814A_H2CCMD_P2P_PS_OFFLOAD_ENABLE(__pH2CCmd, __Value)				SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 1, __Value)
+#define SET_8814A_H2CCMD_P2P_PS_OFFLOAD_ROLE(__pH2CCmd, __Value)				SET_BITS_TO_LE_1BYTE(__pH2CCmd, 1, 1, __Value)
+#define SET_8814A_H2CCMD_P2P_PS_OFFLOAD_CTWINDOW_EN(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd, 2, 1, __Value)
+#define SET_8814A_H2CCMD_P2P_PS_OFFLOAD_NOA0_EN(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE(__pH2CCmd, 3, 1, __Value)
+#define SET_8814A_H2CCMD_P2P_PS_OFFLOAD_NOA1_EN(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE(__pH2CCmd, 4, 1, __Value)
+#define SET_8814A_H2CCMD_P2P_PS_OFFLOAD_ALLSTASLEEP(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd, 5, 1, __Value)
+#define SET_8814A_H2CCMD_P2P_PS_OFFLOAD_DISCOVERY(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE(__pH2CCmd, 6, 1, __Value)
+
+s32 FillH2CCmd_8814(PADAPTER padapter, u8 ElementID, u32 CmdLen, u8 *pCmdBuffer);
+void rtl8814_set_wowlan_cmd(_adapter *padapter, u8 enable);
+void rtl8814_set_FwJoinBssReport_cmd(PADAPTER padapter, u8 mstatus);
+void rtl8814_set_FwPwrMode_cmd(PADAPTER padapter, u8 PSMode);
+u8 GetTxBufferRsvdPageNum8814(_adapter *padapter, bool wowlan);
+void rtl8814_req_txrpt_cmd(PADAPTER padapter, u8 macid);
+
+#ifdef CONFIG_TDLS
+	#ifdef CONFIG_TDLS_CH_SW
+		void rtl8814_set_BcnEarly_C2H_Rpt_cmd(PADAPTER padapter, u8 enable);
+	#endif
+#endif
+
+void
+Set_RA_LDPC_8814(
+	struct sta_info	*psta,
+	BOOLEAN			bLDPC
+);
+
+s32 c2h_handler_8814a(_adapter *adapter, u8 id, u8 seq, u8 plen, u8 *payload);
+
+#ifdef CONFIG_P2P_PS
+	void rtl8814_set_p2p_ps_offload_cmd(PADAPTER padapter, u8 p2p_ps_state);
+#endif /* CONFIG_P2P */
+
+#endif/* __RTL8814A_CMD_H__ */
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/include/rtl8814a_dm.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/rtl8814a_dm.h
--- linux-5.6.3/3rdparty/rtl8821ce/include/rtl8814a_dm.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/rtl8814a_dm.h	2020-04-10 16:35:06.850661655 +0300
@@ -0,0 +1,23 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#ifndef __RTL8814A_DM_H__
+#define __RTL8814A_DM_H__
+
+void rtl8814_init_dm_priv(IN PADAPTER Adapter);
+void rtl8814_deinit_dm_priv(IN PADAPTER Adapter);
+void rtl8814_InitHalDm(IN PADAPTER Adapter);
+void rtl8814_HalDmWatchDog(IN PADAPTER Adapter);
+
+#endif
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/include/rtl8814a_hal.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/rtl8814a_hal.h
--- linux-5.6.3/3rdparty/rtl8821ce/include/rtl8814a_hal.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/rtl8814a_hal.h	2020-04-10 16:35:06.850661655 +0300
@@ -0,0 +1,330 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#ifndef __RTL8814A_HAL_H__
+#define __RTL8814A_HAL_H__
+
+/* #include "hal_com.h" */
+#include "hal_data.h"
+
+/* include HAL Related header after HAL Related compiling flags */
+#include "rtl8814a_spec.h"
+#include "rtl8814a_rf.h"
+#include "rtl8814a_dm.h"
+#include "rtl8814a_recv.h"
+#include "rtl8814a_xmit.h"
+#include "rtl8814a_cmd.h"
+#include "rtl8814a_led.h"
+#include "Hal8814PwrSeq.h"
+#include "Hal8814PhyReg.h"
+#include "Hal8814PhyCfg.h"
+#ifdef DBG_CONFIG_ERROR_DETECT
+	#include "rtl8814a_sreset.h"
+#endif /* DBG_CONFIG_ERROR_DETECT */
+
+enum {
+	VOLTAGE_V25						= 0x03,
+	LDOE25_SHIFT					= 28 ,
+};
+/* max. iram is 64k , max dmen is 32k. Total = 96k = 0x18000*/
+#define FW_SIZE							0x18000
+#define FW_START_ADDRESS   0x1000
+typedef struct _RT_FIRMWARE_8814 {
+	FIRMWARE_SOURCE	eFWSource;
+#ifdef CONFIG_EMBEDDED_FWIMG
+	u8			*szFwBuffer;
+#else
+	u8			szFwBuffer[FW_SIZE];
+#endif
+	u32			ulFwLength;
+} RT_FIRMWARE_8814, *PRT_FIRMWARE_8814;
+
+#define PAGE_SIZE_TX_8814	PAGE_SIZE_128
+/* BCN rsvd_page_num = MAX_BEACON_LEN / PAGE_SIZE_TX_8814
+ * PS-Poll:1, Null Data:1,Qos Null Data:1,BT Qos Null Data:1,CTS-2-SELF,LTE QoS Null*/
+
+#define BCNQ_PAGE_NUM_8814		(MAX_BEACON_LEN / PAGE_SIZE_TX_8814 + 6) /*0x08*/
+
+#define Rtl8814A_NIC_PWR_ON_FLOW				rtl8814A_power_on_flow
+#define Rtl8814A_NIC_RF_OFF_FLOW				rtl8814A_radio_off_flow
+#define Rtl8814A_NIC_DISABLE_FLOW				rtl8814A_card_disable_flow
+#define Rtl8814A_NIC_ENABLE_FLOW				rtl8814A_card_enable_flow
+#define Rtl8814A_NIC_SUSPEND_FLOW				rtl8814A_suspend_flow
+#define Rtl8814A_NIC_RESUME_FLOW				rtl8814A_resume_flow
+#define Rtl8814A_NIC_PDN_FLOW					rtl8814A_hwpdn_flow
+#define Rtl8814A_NIC_LPS_ENTER_FLOW			rtl8814A_enter_lps_flow
+#define Rtl8814A_NIC_LPS_LEAVE_FLOW			rtl8814A_leave_lps_flow
+
+/* *****************************************************
+ *				New	Firmware Header(8-byte alinment required)
+ * *****************************************************
+ * --- LONG WORD 0 ---- */
+#define GET_FIRMWARE_HDR_SIGNATURE_3081(__FwHdr)		LE_BITS_TO_4BYTE(__FwHdr, 0, 16)
+#define GET_FIRMWARE_HDR_CATEGORY_3081(__FwHdr)		LE_BITS_TO_4BYTE(__FwHdr, 16, 8) /* AP/NIC and USB/PCI */
+#define GET_FIRMWARE_HDR_FUNCTION_3081(__FwHdr)			LE_BITS_TO_4BYTE(__FwHdr, 24, 8) /* Reserved for different FW function indcation, for further use when driver needs to download different FW in different conditions */
+#define GET_FIRMWARE_HDR_VERSION_3081(__FwHdr)			LE_BITS_TO_4BYTE(__FwHdr+4, 0, 16)/* FW Version */
+#define GET_FIRMWARE_HDR_SUB_VER_3081(__FwHdr)			LE_BITS_TO_4BYTE(__FwHdr+4, 16, 8) /* FW Subversion, default 0x00 */
+#define GET_FIRMWARE_HDR_SUB_IDX_3081(__FwHdr)			LE_BITS_TO_4BYTE(__FwHdr+4, 24, 8) /* FW Subversion Index */
+
+/* --- LONG WORD 1 ---- */
+#define GET_FIRMWARE_HDR_SVN_IDX_3081(__FwHdr)			LE_BITS_TO_4BYTE(__FwHdr+8, 0, 32)/* The SVN entry index */
+#define GET_FIRMWARE_HDR_RSVD1_3081(__FwHdr)			LE_BITS_TO_4BYTE(__FwHdr+12, 0, 32)
+
+/* --- LONG WORD 2 ---- */
+#define GET_FIRMWARE_HDR_MONTH_3081(__FwHdr)			LE_BITS_TO_4BYTE(__FwHdr+16, 0, 8) /* Release time Month field */
+#define GET_FIRMWARE_HDR_DATE_3081(__FwHdr)				LE_BITS_TO_4BYTE(__FwHdr+16, 8, 8) /* Release time Date field */
+#define GET_FIRMWARE_HDR_HOUR_3081(__FwHdr)				LE_BITS_TO_4BYTE(__FwHdr+16, 16, 8)/* Release time Hour field */
+#define GET_FIRMWARE_HDR_MINUTE_3081(__FwHdr)			LE_BITS_TO_4BYTE(__FwHdr+16, 24, 8)/* Release time Minute field */
+#define GET_FIRMWARE_HDR_YEAR_3081(__FwHdr)				LE_BITS_TO_4BYTE(__FwHdr+20, 0, 16)/* Release time Year field */
+#define GET_FIRMWARE_HDR_FOUNDRY_3081(__FwHdr)			LE_BITS_TO_4BYTE(__FwHdr+20, 16, 8)/* Release time Foundry field */
+#define GET_FIRMWARE_HDR_RSVD2_3081(__FwHdr)			LE_BITS_TO_4BYTE(__FwHdr+20, 24, 8)
+
+/* --- LONG WORD 3 ---- */
+#define GET_FIRMWARE_HDR_MEM_UASGE_DL_FROM_3081(__FwHdr)		LE_BITS_TO_4BYTE(__FwHdr+24, 0, 1)
+#define GET_FIRMWARE_HDR_MEM_UASGE_BOOT_FROM_3081(__FwHdr)	LE_BITS_TO_4BYTE(__FwHdr+24, 1, 1)
+#define GET_FIRMWARE_HDR_MEM_UASGE_BOOT_LOADER_3081(__FwHdr)LE_BITS_TO_4BYTE(__FwHdr+24, 2, 1)
+#define GET_FIRMWARE_HDR_MEM_UASGE_IRAM_3081(__FwHdr)			LE_BITS_TO_4BYTE(__FwHdr+24, 3, 1)
+#define GET_FIRMWARE_HDR_MEM_UASGE_ERAM_3081(__FwHdr)			LE_BITS_TO_4BYTE(__FwHdr+24, 4, 1)
+#define GET_FIRMWARE_HDR_MEM_UASGE_RSVD4_3081(__FwHdr)		LE_BITS_TO_4BYTE(__FwHdr+24, 5, 3)
+#define GET_FIRMWARE_HDR_RSVD3_3081(__FwHdr)					LE_BITS_TO_4BYTE(__FwHdr+24, 8, 8)
+#define GET_FIRMWARE_HDR_BOOT_LOADER_SZ_3081(__FwHdr)			LE_BITS_TO_4BYTE(__FwHdr+24, 16, 16)
+#define GET_FIRMWARE_HDR_RSVD5_3081(__FwHdr)					LE_BITS_TO_4BYTE(__FwHdr+28, 0, 32)
+
+/* --- LONG WORD 4 ---- */
+#define GET_FIRMWARE_HDR_TOTAL_DMEM_SZ_3081(__FwHdr)	LE_BITS_TO_4BYTE(__FwHdr+36, 0, 32)
+#define GET_FIRMWARE_HDR_FW_CFG_SZ_3081(__FwHdr)		LE_BITS_TO_4BYTE(__FwHdr+36, 0, 16)
+#define GET_FIRMWARE_HDR_FW_ATTR_SZ_3081(__FwHdr)		LE_BITS_TO_4BYTE(__FwHdr+36, 16, 16)
+
+/* --- LONG WORD 5 ---- */
+#define GET_FIRMWARE_HDR_IROM_3081(__FwHdr)				LE_BITS_TO_4BYTE(__FwHdr+40, 0, 32)
+#define GET_FIRMWARE_HDR_EROM_3081(__FwHdr)				LE_BITS_TO_4BYTE(__FwHdr+44, 0, 32)
+
+/* --- LONG WORD 6 ---- */
+#define GET_FIRMWARE_HDR_IRAM_SZ_3081(__FwHdr)			LE_BITS_TO_4BYTE(__FwHdr+48, 0, 32)
+#define GET_FIRMWARE_HDR_ERAM_SZ_3081(__FwHdr)			LE_BITS_TO_4BYTE(__FwHdr+52, 0, 32)
+
+/* --- LONG WORD 7 ---- */
+#define GET_FIRMWARE_HDR_RSVD6_3081(__FwHdr)			LE_BITS_TO_4BYTE(__FwHdr+56, 0, 32)
+#define GET_FIRMWARE_HDR_RSVD7_3081(__FwHdr)			LE_BITS_TO_4BYTE(__FwHdr+60, 0, 32)
+
+
+
+/*
+ * 2013/08/16 MH MOve from SDIO.h for common use.
+ *   */
+#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_USB_HCI)
+	#define TRX_SHARE_MODE_8814A				0	/* TRX Buffer Share Index */
+	#define BASIC_RXFF_SIZE_8814A				24576/* Basic RXFF Size is 24K = 24*1024 Unit: Byte */
+	#define TRX_SHARE_BUFF_UNIT_8814A			65536/* TRX Share Buffer unit Size 64K = 64*1024 Unit: Byte */
+	#define TRX_SHARE_BUFF_UNIT_PAGE_8814A	(TRX_SHARE_BUFF_UNIT_8814A/PAGE_SIZE_8814A)/* 512 Pages */
+
+	/* Origin: */
+	#define  HPQ_PGNUM_8814A					0x20	/* High Queue */
+	#define  LPQ_PGNUM_8814A					0x20	/* Low Queue */
+	#define  NPQ_PGNUM_8814A					0x20	/* Normal Queue */
+	#define  EPQ_PGNUM_8814A					0x20	/* Extra Queue */
+
+#else	/*  #if defined(CONFIG_SDIO_HCI) || defined(CONFIG_USB_HCI) */
+
+	#define  HPQ_PGNUM_8814A		20
+	#define  NPQ_PGNUM_8814A		20
+	#define  LPQ_PGNUM_8814A		20 /* 1972 */
+	#define  EPQ_PGNUM_8814A		20
+	#define  BCQ_PGNUM_8814A		32
+
+#endif /* #if defined(CONFIG_SDIO_HCI) || defined(CONFIG_USB_HCI) */
+
+#ifdef CONFIG_WOWLAN
+	#define WOWLAN_PAGE_NUM_8814	0x06
+#else
+	#define WOWLAN_PAGE_NUM_8814	0x00
+#endif
+
+#define PAGE_SIZE_8814A						128/* TXFF Page Size, Unit: Byte */
+#define MAX_RX_DMA_BUFFER_SIZE_8814A		0x5C00	/* BASIC_RXFF_SIZE_8814A + TRX_SHARE_MODE_8814A * TRX_SHARE_BUFF_UNIT_8814A */ /* Basic RXFF Size + ShareBuffer Size */
+#define TX_PAGE_BOUNDARY_8814A			TXPKT_PGNUM_8814A	/* Need to enlarge boundary, by KaiYuan */
+#define TX_PAGE_BOUNDARY_WOWLAN_8814A	TXPKT_PGNUM_8814A	/* TODO: 20130415 KaiYuan Check this value later */
+
+#ifdef CONFIG_FW_C2H_DEBUG
+	#define RX_DMA_RESERVED_SIZE_8814A	0x100	/* 256B, reserved for c2h debug message */
+#else
+	#define RX_DMA_RESERVED_SIZE_8814A	0x0	/* 0B */
+#endif
+#define RX_DMA_BOUNDARY_8814A		(MAX_RX_DMA_BUFFER_SIZE_8814A - RX_DMA_RESERVED_SIZE_8814A - 1)
+
+#define  TOTAL_PGNUM_8814A		2048
+#define  TXPKT_PGNUM_8814A		(2048 - BCNQ_PAGE_NUM_8814-WOWLAN_PAGE_NUM_8814)
+#define  PUB_PGNUM_8814A		(TXPKT_PGNUM_8814A-HPQ_PGNUM_8814A-NPQ_PGNUM_8814A-LPQ_PGNUM_8814A-EPQ_PGNUM_8814A)
+
+/* Note: For WMM Normal Chip Setting ,modify later */
+#define WMM_NORMAL_TX_TOTAL_PAGE_NUMBER_8814A	TX_PAGE_BOUNDARY_8814A
+#define WMM_NORMAL_TX_PAGE_BOUNDARY_8814A		(WMM_NORMAL_TX_TOTAL_PAGE_NUMBER_8814A + 1)
+
+#define DRIVER_EARLY_INT_TIME_8814		0x05
+#define BCN_DMA_ATIME_INT_TIME_8814		0x02
+
+
+#define MAX_PAGE_SIZE			4096	/* @ page : 4k bytes */
+
+#define EFUSE_MAX_SECTION_JAGUAR				64
+
+#define	HWSET_MAX_SIZE_8814A			512
+
+#define	EFUSE_REAL_CONTENT_LEN_8814A	1024
+#define	EFUSE_MAX_BANK_8814A		2
+
+#define	EFUSE_MAP_LEN_8814A			512
+#define	EFUSE_MAX_SECTION_8814A		64
+#define	EFUSE_MAX_WORD_UNIT_8814A		4
+#define	EFUSE_PROTECT_BYTES_BANK_8814A		16
+
+#define	EFUSE_IC_ID_OFFSET_8814A		506	/* For some inferiority IC purpose. added by Roger, 2009.09.02. */
+#define AVAILABLE_EFUSE_ADDR_8814A(addr)	(addr < EFUSE_REAL_CONTENT_LEN_8814A)
+
+/*-------------------------------------------------------------------------
+Chip specific
+-------------------------------------------------------------------------*/
+
+/* pic buffer descriptor */
+#if 1 /* according to the define in the rtw_xmit.h, rtw_recv.h */
+	#define RTL8814AE_SEG_NUM  TX_BUFFER_SEG_NUM /* 0:2 seg, 1: 4 seg, 2: 8 seg */
+	#define TX_DESC_NUM_8814A  TX_BD_NUM   /* 128 */
+	#define RX_DESC_NUM_8814A  PCI_MAX_RX_COUNT /* 128 */
+	#ifdef CONFIG_CONCURRENT_MODE
+		#define BE_QUEUE_TX_DESC_NUM_8814A  (TX_BD_NUM<<1)    /* 256 */
+	#else
+		#define BE_QUEUE_TX_DESC_NUM_8814A  (TX_BD_NUM+(TX_BD_NUM>>1)) /* 192 */
+	#endif
+#else
+	#define RTL8814AE_SEG_NUM  TX_BUFFER_SEG_NUM /* 0:2 seg, 1: 4 seg, 2: 8 seg */
+	#define TX_DESC_NUM_8814A  128 /* 1024//2048 change by ylb 20130624 */
+	#define RX_DESC_NUM_8814A  128 /* 1024 //512 change by ylb 20130624 */
+#endif
+
+/* <Roger_Notes> To prevent out of boundary programming case, leave 1byte and program full section
+ * 9bytes + 1byt + 5bytes and pre 1byte.
+ * For worst case:
+ * | 1byte|----8bytes----|1byte|--5bytes--|
+ * |         |            Reserved(14bytes)	      |
+ *   */
+#define	EFUSE_OOB_PROTECT_BYTES		15	/* PG data exclude header, dummy 6 bytes frome CP test and reserved 1byte. */
+
+#ifdef CONFIG_FILE_FWIMG
+extern char *rtw_fw_file_path;
+#ifdef CONFIG_WOWLAN
+extern char *rtw_fw_wow_file_path;
+#endif
+#ifdef CONFIG_MP_INCLUDED
+extern char *rtw_fw_mp_bt_file_path;
+#endif /* CONFIG_MP_INCLUDED */
+#endif /* CONFIG_FILE_FWIMG */
+
+/* rtl8814_hal_init.c */
+s32 FirmwareDownload8814A(PADAPTER	Adapter, BOOLEAN bUsedWoWLANFw);
+void	InitializeFirmwareVars8814(PADAPTER padapter);
+
+VOID
+Hal_InitEfuseVars_8814A(
+	IN	PADAPTER	Adapter
+);
+
+s32 InitLLTTable8814A(
+	IN	PADAPTER	Adapter
+);
+
+
+void InitRDGSetting8814A(PADAPTER padapter);
+
+/* void CheckAutoloadState8812A(PADAPTER padapter); */
+
+/* EFuse */
+u8	GetEEPROMSize8814A(PADAPTER padapter);
+VOID hal_InitPGData_8814A(
+ IN PADAPTER  padapter,
+ IN OUT u8   *PROMContent
+);
+
+void	hal_ReadPROMVersion8814A(PADAPTER padapter, u8 *hwinfo, BOOLEAN AutoLoadFail);
+void	hal_ReadTxPowerInfo8814A(PADAPTER padapter, u8 *hwinfo, BOOLEAN	AutoLoadFail);
+void	hal_ReadBoardType8814A(PADAPTER pAdapter, u8 *hwinfo, BOOLEAN AutoLoadFail);
+void	hal_ReadThermalMeter_8814A(PADAPTER	Adapter, u8 *PROMContent, BOOLEAN	AutoloadFail);
+void	hal_ReadChannelPlan8814A(PADAPTER padapter, u8 *hwinfo, BOOLEAN AutoLoadFail);
+void	hal_EfuseParseXtal_8814A(PADAPTER pAdapter, u8 *hwinfo, BOOLEAN AutoLoadFail);
+void	hal_ReadAntennaDiversity8814A(PADAPTER pAdapter, u8 *PROMContent, BOOLEAN AutoLoadFail);
+void	hal_Read_TRX_antenna_8814A(PADAPTER	Adapter, u8 *PROMContent, BOOLEAN AutoloadFail);
+VOID hal_ReadAmplifierType_8814A(
+	IN	PADAPTER		Adapter
+);
+VOID hal_ReadPAType_8814A(
+	IN	PADAPTER	Adapter,
+	IN	u8			*PROMContent,
+	IN	BOOLEAN		AutoloadFail,
+	OUT u8		*pPAType,
+	OUT u8		*pLNAType
+);
+
+void hal_ReadPowerTrackingType_8814A(PADAPTER Adapter, u8 *PROMContent, BOOLEAN AutoloadFail);
+
+void hal_GetRxGainOffset_8814A(
+	PADAPTER	Adapter,
+	pu1Byte		PROMContent,
+	BOOLEAN		AutoloadFail
+);
+void Hal_EfuseParseKFreeData_8814A(
+	IN		PADAPTER		Adapter,
+	IN		u8				*PROMContent,
+	IN		BOOLEAN			AutoloadFail);
+void	hal_ReadRFEType_8814A(PADAPTER Adapter, u8 *PROMContent, BOOLEAN AutoloadFail);
+void	hal_EfuseParseBTCoexistInfo8814A(PADAPTER Adapter, u8 *hwinfo, BOOLEAN AutoLoadFail);
+
+/* void	hal_ReadUsbType_8812AU(PADAPTER Adapter, u8 *PROMContent, BOOLEAN AutoloadFail);
+ * int	FirmwareDownloadBT(PADAPTER Adapter, PRT_MP_FIRMWARE pFirmware); */
+void	hal_ReadRemoteWakeup_8814A(PADAPTER padapter, u8 *hwinfo, BOOLEAN AutoLoadFail);
+u8	MgntQuery_NssTxRate(u16 Rate);
+
+/* BOOLEAN HalDetectPwrDownMode8812(PADAPTER Adapter); */
+
+#ifdef CONFIG_WOWLAN
+	void Hal_DetectWoWMode(PADAPTER pAdapter);
+#endif /* CONFIG_WOWLAN */
+
+void _InitBeaconParameters_8814A(PADAPTER padapter);
+void SetBeaconRelatedRegisters8814A(PADAPTER padapter);
+
+void ReadRFType8814A(PADAPTER padapter);
+void InitDefaultValue8814A(PADAPTER padapter);
+
+u8 SetHwReg8814A(PADAPTER padapter, u8 variable, u8 *pval);
+void GetHwReg8814A(PADAPTER padapter, u8 variable, u8 *pval);
+u8 SetHalDefVar8814A(PADAPTER padapter, HAL_DEF_VARIABLE variable, void *pval);
+u8 GetHalDefVar8814A(PADAPTER padapter, HAL_DEF_VARIABLE variable, void *pval);
+void rtl8814_set_hal_ops(struct hal_ops *pHalFunc);
+void init_hal_spec_8814a(_adapter *adapter);
+
+void rtl8814_start_thread(PADAPTER padapter);
+void rtl8814_stop_thread(PADAPTER padapter);
+
+
+#ifdef CONFIG_PCI_HCI
+	BOOLEAN	InterruptRecognized8814AE(PADAPTER Adapter);
+	VOID	UpdateInterruptMask8814AE(PADAPTER Adapter, u32 AddMSR, u32 AddMSR1, u32 RemoveMSR, u32 RemoveMSR1);
+	VOID	InitMAC_TRXBD_8814AE(PADAPTER Adapter);
+	u16	get_txbd_rw_reg(u16 ff_hwaddr);
+#endif
+
+#ifdef CONFIG_BT_COEXIST
+	void rtl8812a_combo_card_WifiOnlyHwInit(PADAPTER Adapter);
+#endif
+
+#endif /* __RTL8188E_HAL_H__ */
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/include/rtl8814a_led.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/rtl8814a_led.h
--- linux-5.6.3/3rdparty/rtl8821ce/include/rtl8814a_led.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/rtl8814a_led.h	2020-04-10 16:35:06.850661655 +0300
@@ -0,0 +1,36 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#ifndef __RTL8814A_LED_H__
+#define __RTL8814A_LED_H__
+
+#ifdef CONFIG_RTW_SW_LED
+/* ********************************************************************************
+ * Interface to manipulate LED objects.
+ * ******************************************************************************** */
+#ifdef CONFIG_USB_HCI
+	void rtl8814au_InitSwLeds(PADAPTER padapter);
+	void rtl8814au_DeInitSwLeds(PADAPTER padapter);
+#endif /* CONFIG_USB_HCI */
+#ifdef CONFIG_PCI_HCI
+	void rtl8814ae_InitSwLeds(PADAPTER padapter);
+	void rtl8814ae_DeInitSwLeds(PADAPTER padapter);
+#endif /* CONFIG_PCI_HCI */
+#ifdef CONFIG_SDIO_HCI
+	void rtl8814s_InitSwLeds(PADAPTER padapter);
+	void rtl8814s_DeInitSwLeds(PADAPTER padapter);
+#endif /* CONFIG_SDIO_HCI */
+
+#endif /* __RTL8814A_LED_H__ */
+#endif /*CONFIG_RTW_SW_LED*/
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/include/rtl8814a_recv.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/rtl8814a_recv.h
--- linux-5.6.3/3rdparty/rtl8821ce/include/rtl8814a_recv.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/rtl8814a_recv.h	2020-04-10 16:35:06.850661655 +0300
@@ -0,0 +1,186 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#ifndef __RTL8814A_RECV_H__
+#define __RTL8814A_RECV_H__
+
+#if defined(CONFIG_USB_HCI)
+
+	#ifndef MAX_RECVBUF_SZ
+		#ifdef PLATFORM_OS_CE
+			#define MAX_RECVBUF_SZ (8192+1024) /* 8K+1k */
+		#else
+			#ifndef CONFIG_MINIMAL_MEMORY_USAGE
+				#ifdef CONFIG_PLATFORM_MSTAR
+					#define MAX_RECVBUF_SZ (8192) /* 8K */
+				#else
+					#define MAX_RECVBUF_SZ (32768) /* 32k */
+				#endif
+				/* #define MAX_RECVBUF_SZ (24576) */ /* 24k */
+				/* #define MAX_RECVBUF_SZ (20480) */ /* 20K */
+				/* #define MAX_RECVBUF_SZ (10240) */ /* 10K */
+				/* #define MAX_RECVBUF_SZ (15360) */ /* 15k < 16k */
+				/* #define MAX_RECVBUF_SZ (8192+1024) */ /* 8K+1k */
+			#else
+				#define MAX_RECVBUF_SZ (4000) /* about 4K */
+			#endif
+		#endif
+	#endif /* !MAX_RECVBUF_SZ */
+
+#elif defined(CONFIG_PCI_HCI)
+	/* #ifndef CONFIG_MINIMAL_MEMORY_USAGE */
+	/*	#define MAX_RECVBUF_SZ (9100) */
+	/* #else */
+	#define MAX_RECVBUF_SZ (4000) /* about 4K
+	* #endif */
+
+
+#elif defined(CONFIG_SDIO_HCI)
+	#if 0
+		/* temp solution */
+		#ifdef CONFIG_SDIO_RX_COPY
+			#define MAX_RECVBUF_SZ (10240)
+		#else /*  !CONFIG_SDIO_RX_COPY */
+			#define MAX_RECVBUF_SZ	MAX_RX_DMA_BUFFER_SIZE_8821
+		#endif /*  !CONFIG_SDIO_RX_COPY */
+	#endif
+#endif
+
+
+/* RX buffer descriptor */
+/* DWORD 0 */
+#define SET_RX_BUFFER_DESC_DATA_LENGTH_8814A(__pRxStatusDesc, __Value)		SET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 0, 14, __Value)
+#define SET_RX_BUFFER_DESC_LS_8814A(__pRxStatusDesc, __Value)					SET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 14, 1, __Value)
+#define SET_RX_BUFFER_DESC_FS_8814A(__pRxStatusDesc, __Value)					SET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 15, 1, __Value)
+#define SET_RX_BUFFER_DESC_TOTAL_LENGTH_8814A(__pRxStatusDesc, __Value)		SET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 16, 16, __Value)
+
+#define GET_RX_BUFFER_DESC_OWN_8814A(__pRxStatusDesc)						LE_BITS_TO_4BYTE(__pRxStatusDesc, 31, 1)
+#define GET_RX_BUFFER_DESC_LS_8814A(__pRxStatusDesc)							LE_BITS_TO_4BYTE(__pRxStatusDesc, 14, 1)
+#define GET_RX_BUFFER_DESC_FS_8814A(__pRxStatusDesc)							LE_BITS_TO_4BYTE(__pRxStatusDesc, 15, 1)
+#define GET_RX_BUFFER_DESC_TOTAL_LENGTH_8814A(__pRxStatusDesc)				LE_BITS_TO_4BYTE(__pRxStatusDesc, 16, 15)
+
+/* DWORD 1 */
+#define SET_RX_BUFFER_PHYSICAL_LOW_8814A(__pRxStatusDesc, __Value)			SET_BITS_TO_LE_4BYTE(__pRxStatusDesc+4, 0, 32, __Value)
+#define GET_RX_BUFFER_PHYSICAL_LOW_8814A(__pRxStatusDesc)					LE_BITS_TO_4BYTE(__pRxStatusDesc+4, 0, 32)
+
+/* DWORD 2 */
+#define SET_RX_BUFFER_PHYSICAL_HIGH_8814A(__pRxStatusDesc, __Value)			SET_BITS_TO_LE_4BYTE(__pRxStatusDesc+8, 0, 32, __Value)
+
+/* DWORD 3*/ /* RESERVED */
+
+
+#if 0
+	/* =============
+	* RX Info
+	* ============== */
+#endif
+/* DWORD 0 */
+#define SET_RX_STATUS_DESC_PKT_LEN_8814A(__pRxStatusDesc, __Value)		SET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 0, 14, __Value)
+#define SET_RX_STATUS_DESC_EOR_8814A(__pRxStatusDesc, __Value)			SET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 30, 1, __Value)
+#define SET_RX_STATUS_DESC_OWN_8814AE(__pRxStatusDesc, __Value)		SET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 31, 1, __Value)
+
+#define GET_RX_STATUS_DESC_PKT_LEN_8814A(__pRxStatusDesc)				LE_BITS_TO_4BYTE(__pRxStatusDesc, 0, 14)
+#define GET_RX_STATUS_DESC_CRC32_8814A(__pRxStatusDesc)					LE_BITS_TO_4BYTE(__pRxStatusDesc, 14, 1)
+#define GET_RX_STATUS_DESC_ICV_8814A(__pRxStatusDesc)					LE_BITS_TO_4BYTE(__pRxStatusDesc, 15, 1)
+#define GET_RX_STATUS_DESC_DRVINFO_SIZE_8814A(__pRxStatusDesc)			LE_BITS_TO_4BYTE(__pRxStatusDesc, 16, 4)
+#define GET_RX_STATUS_DESC_SECURITY_8814A(__pRxStatusDesc)				LE_BITS_TO_4BYTE(__pRxStatusDesc, 20, 3)
+#define GET_RX_STATUS_DESC_QOS_8814A(__pRxStatusDesc)					LE_BITS_TO_4BYTE(__pRxStatusDesc, 23, 1)
+#define GET_RX_STATUS_DESC_SHIFT_8814A(__pRxStatusDesc)						LE_BITS_TO_4BYTE(__pRxStatusDesc, 24, 2)
+#define GET_RX_STATUS_DESC_PHY_STATUS_8814A(__pRxStatusDesc)				LE_BITS_TO_4BYTE(__pRxStatusDesc, 26, 1)
+#define GET_RX_STATUS_DESC_SWDEC_8814A(__pRxStatusDesc)						LE_BITS_TO_4BYTE(__pRxStatusDesc, 27, 1)
+#define GET_RX_STATUS_DESC_LAST_SEG_8814AE(__pRxStatusDesc)			LE_BITS_TO_4BYTE(__pRxStatusDesc, 28, 1)
+#define GET_RX_STATUS_DESC_EOR_8814A(__pRxStatusDesc)						LE_BITS_TO_4BYTE(__pRxStatusDesc, 30, 1)
+
+/* DWORD 1 */
+#define GET_RX_STATUS_DESC_MACID_8814A(__pRxStatusDesc)					LE_BITS_TO_4BYTE(__pRxStatusDesc+4, 0, 7)
+#define GET_RX_STATUS_DESC_EXT_SECTYPE_8814A(__pRxStatusDesc)				LE_BITS_TO_4BYTE(__pRxStatusDesc+4, 7, 1)/* 20130415 KaiYuan add for 8814 */
+#define GET_RX_STATUS_DESC_TID_8814A(__pRxStatusDesc)					LE_BITS_TO_4BYTE(__pRxStatusDesc+4, 8, 4)
+#define GET_RX_STATUS_DESC_MACID_VLD_8814A(__pRxStatusDesc)				LE_BITS_TO_4BYTE(__pRxStatusDesc+4, 12, 1)
+#define GET_RX_STATUS_DESC_AMSDU_8814A(__pRxStatusDesc)					LE_BITS_TO_4BYTE(__pRxStatusDesc+4, 13, 1)
+#define GET_RX_STATUS_DESC_RXID_MATCH_8814A(__pRxStatusDesc)				LE_BITS_TO_4BYTE(__pRxStatusDesc+4, 14, 1)
+#define GET_RX_STATUS_DESC_PAGGR_8814A(__pRxStatusDesc)						LE_BITS_TO_4BYTE(__pRxStatusDesc+4, 15, 1)
+#define GET_RX_STATUS_DESC_TCPOFFLOAD_CHKERR_8814A(__pRxStatusDesc)		LE_BITS_TO_4BYTE(__pRxStatusDesc+4, 20, 1)
+#define GET_RX_STATUS_DESC_TCPOFFLOAD_IPVER_8814A(__pRxStatusDesc)			LE_BITS_TO_4BYTE(__pRxStatusDesc+4, 21, 1)
+#define GET_RX_STATUS_DESC_TCPOFFLOAD_IS_TCPUDP_8814A(__pRxStatusDesc)		LE_BITS_TO_4BYTE(__pRxStatusDesc+4, 22, 1)
+#define GET_RX_STATUS_DESC_TCPOFFLOAD_CHK_VLD_8814A(__pRxStatusDesc)		LE_BITS_TO_4BYTE(__pRxStatusDesc+4, 23, 1)
+#define GET_RX_STATUS_DESC_PAM_8814A(__pRxStatusDesc)						LE_BITS_TO_4BYTE(__pRxStatusDesc+4, 24, 1)
+#define GET_RX_STATUS_DESC_PWR_8814A(__pRxStatusDesc)						LE_BITS_TO_4BYTE(__pRxStatusDesc+4, 25, 1)
+#define GET_RX_STATUS_DESC_MORE_DATA_8814A(__pRxStatusDesc)					LE_BITS_TO_4BYTE(__pRxStatusDesc+4, 26, 1)
+#define GET_RX_STATUS_DESC_MORE_FRAG_8814A(__pRxStatusDesc)					LE_BITS_TO_4BYTE(__pRxStatusDesc+4, 27, 1)
+#define GET_RX_STATUS_DESC_TYPE_8814A(__pRxStatusDesc)						LE_BITS_TO_4BYTE(__pRxStatusDesc+4, 28, 2)
+#define GET_RX_STATUS_DESC_FIRST_SEG_8814AE(__pRxStatusDesc)			LE_BITS_TO_4BYTE(__pRxStatusDesc, 29, 1)
+#define GET_RX_STATUS_DESC_EOR_8814AE(__pRxStatusDesc)				LE_BITS_TO_4BYTE(__pRxStatusDesc, 30, 1)
+#define GET_RX_STATUS_DESC_MC_8814A(__pRxStatusDesc)							LE_BITS_TO_4BYTE(__pRxStatusDesc+4, 30, 1)
+#define GET_RX_STATUS_DESC_BC_8814A(__pRxStatusDesc)							LE_BITS_TO_4BYTE(__pRxStatusDesc+4, 31, 1)
+
+/* DWORD 2 */
+#define GET_RX_STATUS_DESC_SEQ_8814A(__pRxStatusDesc)						LE_BITS_TO_4BYTE(__pRxStatusDesc+8, 0, 12)
+#define GET_RX_STATUS_DESC_FRAG_8814A(__pRxStatusDesc)						LE_BITS_TO_4BYTE(__pRxStatusDesc+8, 12, 4)
+#ifdef CONFIG_USB_RX_AGGREGATION
+	#define GET_RX_STATUS_DESC_USB_AGG_PKTNUM_8814A(__pRxStatusDesc)			LE_BITS_TO_4BYTE(__pRxStatusDesc+8, 16, 8)
+#else
+	#define GET_RX_STATUS_DESC_RX_IS_QOS_8814A(__pRxStatusDesc)					LE_BITS_TO_4BYTE(__pRxStatusDesc+8, 16, 1)
+#endif
+#define GET_RX_STATUS_DESC_WLANHD_IV_LEN_8814A(__pRxStatusDesc)			LE_BITS_TO_4BYTE(__pRxStatusDesc+8, 18, 6)
+#define GET_RX_STATUS_DESC_HWRSVD_8814A(__pRxStatusDesc)					LE_BITS_TO_4BYTE(__pRxStatusDesc+8, 24, 4)
+#define GET_RX_STATUS_C2H_8814A(__pRxStatusDesc)								LE_BITS_TO_4BYTE(__pRxStatusDesc+8, 28, 1)
+#define GET_RX_STATUS_DESC_FCS_OK_8814A(__pRxStatusDesc)					LE_BITS_TO_4BYTE(__pRxStatusDesc+8, 31, 1)
+
+/* DWORD 3 */
+#define GET_RX_STATUS_DESC_RX_RATE_8814A(__pRxStatusDesc)					LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 0, 7)
+#define GET_RX_STATUS_DESC_BSSID_FIT_H_8814A(__pRxStatusDesc)				LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 7, 3)/* 20130415 KaiYuan add for 8814 */
+#define GET_RX_STATUS_DESC_HTC_8814A(__pRxStatusDesc)						LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 10, 1)
+#define GET_RX_STATUS_DESC_EOSP_8814A(__pRxStatusDesc)						LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 11, 1)
+#define GET_RX_STATUS_DESC_BSSID_FIT_L_8814A(__pRxStatusDesc)				LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 12, 2)
+#define GET_RX_STATUS_DESC_DMA_AGG_NUM_8814A(__pRxStatusDesc)				LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 16, 8)/* 20130415 KaiYuan Check if it exist anymore */
+#define GET_RX_STATUS_DESC_PATTERN_MATCH_8814A(__pRxStatusDesc)			LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 29, 1)
+#define GET_RX_STATUS_DESC_UNICAST_8814A(__pRxStatusDesc)					LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 30, 1)
+#define GET_RX_STATUS_DESC_MAGIC_WAKE_8814A(__pRxStatusDesc)				LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 31, 1)
+
+/* DWORD 4 */
+#define GET_RX_STATUS_DESC_PATTERN_IDX_8814A(__pRxStatusDesc)				LE_BITS_TO_4BYTE(__pRxStatusDesc+16, 0, 8)
+#define GET_RX_STATUS_DESC_RX_EOF_8814A(__pRxStatusDesc)					LE_BITS_TO_4BYTE(__pRxStatusDesc+16, 8, 1)
+#define GET_RX_STATUS_DESC_RX_SCRAMBLER_8814A(__pRxStatusDesc)				LE_BITS_TO_4BYTE(__pRxStatusDesc+16, 9, 7)
+#define GET_RX_STATUS_DESC_RX_PRE_NDP_VLD_8814A(__pRxStatusDesc)			LE_BITS_TO_4BYTE(__pRxStatusDesc+16, 16, 1)
+#define GET_RX_STATUS_DESC_A1_FIT_8814A(__pRxStatusDesc)						LE_BITS_TO_4BYTE(__pRxStatusDesc+16, 24, 5)
+
+
+/* DWORD 5 */
+#define GET_RX_STATUS_DESC_TSFL_8814A(__pRxStatusDesc)						LE_BITS_TO_4BYTE(__pRxStatusDesc+20, 0, 32)
+
+
+/* Rx smooth factor */
+#define Rx_Smooth_Factor (20)
+
+#ifdef CONFIG_USB_HCI
+	s32 rtl8814au_init_recv_priv(PADAPTER padapter);
+	void rtl8814au_free_recv_priv(PADAPTER padapter);
+#endif
+
+#ifdef CONFIG_PCI_HCI
+	s32 rtl8814ae_init_recv_priv(PADAPTER padapter);
+	void rtl8814ae_free_recv_priv(PADAPTER padapter);
+#endif
+
+#if 0
+	/* temp solution */
+	#ifdef CONFIG_SDIO_HCI
+		s32 InitRecvPriv8821AS(PADAPTER padapter);
+		void FreeRecvPriv8821AS(PADAPTER padapter);
+	#endif /*  CONFIG_SDIO_HCI */
+#endif
+
+void rtl8814_query_rx_desc_status(union recv_frame *precvframe, u8 *pdesc);
+
+#endif /* __RTL8814A_RECV_H__ */
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/include/rtl8814a_rf.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/rtl8814a_rf.h
--- linux-5.6.3/3rdparty/rtl8821ce/include/rtl8814a_rf.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/rtl8814a_rf.h	2020-04-10 16:35:06.850661655 +0300
@@ -0,0 +1,28 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#ifndef __RTL8814A_RF_H__
+#define __RTL8814A_RF_H__
+
+VOID
+PHY_RF6052SetBandwidth8814A(
+	IN	PADAPTER				Adapter,
+	IN	enum channel_width		Bandwidth);
+
+
+int
+PHY_RF6052_Config_8814A(
+	IN	PADAPTER	Adapter);
+
+#endif/* __RTL8188E_RF_H__ */
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/include/rtl8814a_spec.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/rtl8814a_spec.h
--- linux-5.6.3/3rdparty/rtl8821ce/include/rtl8814a_spec.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/rtl8814a_spec.h	2020-04-10 16:35:06.850661655 +0300
@@ -0,0 +1,648 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#ifndef __RTL8814A_SPEC_H__
+#define __RTL8814A_SPEC_H__
+
+#include <drv_conf.h>
+
+
+/* ************************************************************
+ *
+ * ************************************************************ */
+
+/* -----------------------------------------------------
+ *
+ *	0x0000h ~ 0x00FFh	System Configuration
+ *
+ * ----------------------------------------------------- */
+#define REG_SYS_ISO_CTRL_8814A			0x0000	/* 2 Byte */
+#define REG_SYS_FUNC_EN_8814A			0x0002	/* 2 Byte */
+#define REG_SYS_PW_CTRL_8814A			0x0004	/* 4 Byte        */
+#define REG_SYS_CLKR_8814A				0x0008	/* 2 Byte */
+#define REG_SYS_EEPROM_CTRL_8814A		0x000A	/* 2 Byte        */
+#define REG_EE_VPD_8814A				0x000C	/* 2 Byte */
+#define REG_SYS_SWR_CTRL1_8814A			0x0010	/* 1 Byte */
+#define REG_SPS0_CTRL_8814A				0x0011	/* 7 Byte */
+#define REG_SYS_SWR_CTRL3_8814A			0x0018	/* 4 Byte */
+#define REG_RSV_CTRL_8814A				0x001C	/* 3 Byte */
+#define REG_RF_CTRL0_8814A				0x001F	/* 1 Byte */
+#define REG_RF_CTRL1_8814A				0x0020	/* 1 Byte */
+#define REG_RF_CTRL2_8814A				0x0021	/* 1 Byte */
+#define REG_LPLDO_CTRL_8814A			0x0023	/* 1 Byte */
+#define REG_AFE_CTRL1_8814A				0x0024	/* 4 Byte        */
+#define REG_AFE_CTRL2_8814A				0x0028	/* 4 Byte        */
+#define REG_AFE_CTRL3_8814A				0x002c	/* 4 Byte  */
+#define REG_EFUSE_CTRL_8814A			0x0030
+#define REG_LDO_EFUSE_CTRL_8814A		0x0034
+#define REG_PWR_DATA_8814A				0x0038
+#define REG_CAL_TIMER_8814A				0x003C
+#define REG_ACLK_MON_8814A				0x003E
+#define REG_GPIO_MUXCFG_8814A			0x0040
+#define REG_GPIO_IO_SEL_8814A			0x0042
+#define REG_MAC_PINMUX_CFG_8814A		0x0043
+#define REG_GPIO_PIN_CTRL_8814A			0x0044
+#define REG_GPIO_INTM_8814A				0x0048
+#define REG_LEDCFG0_8814A				0x004C
+#define REG_LEDCFG1_8814A				0x004D
+#define REG_LEDCFG2_8814A				0x004E
+#define REG_LEDCFG3_8814A				0x004F
+#define REG_FSIMR_8814A					0x0050
+#define REG_FSISR_8814A					0x0054
+#define REG_HSIMR_8814A					0x0058
+#define REG_HSISR_8814A					0x005c
+#define REG_GPIO_EXT_CTRL_8814A			0x0060
+#define REG_GPIO_STATUS_8814A			0x006C
+#define REG_SDIO_CTRL_8814A				0x0070
+#define REG_HCI_OPT_CTRL_8814A			0x0074
+#define REG_RF_CTRL3_8814A				0x0076	/* 1 Byte */
+#define REG_AFE_CTRL4_8814A				0x0078
+#define REG_8051FW_CTRL_8814A			0x0080
+#define REG_HIMR0_8814A					0x00B0
+#define REG_HISR0_8814A					0x00B4
+#define REG_HIMR1_8814A					0x00B8
+#define REG_HISR1_8814A					0x00BC
+#define REG_SYS_CFG1_8814A				0x00F0
+#define REG_SYS_CFG2_8814A				0x00FC
+#define REG_SYS_CFG3_8814A				0x1000
+
+/* -----------------------------------------------------
+ *
+ *	0x0100h ~ 0x01FFh	MACTOP General Configuration
+ *
+ * ----------------------------------------------------- */
+#define REG_CR_8814A						0x0100
+#define REG_PBP_8814A					0x0104
+#define REG_PKT_BUFF_ACCESS_CTRL_8814A	0x0106
+#define REG_TRXDMA_CTRL_8814A			0x010C
+#define REG_TRXFF_BNDY_8814A			0x0114
+#define REG_TRXFF_STATUS_8814A			0x0118
+#define REG_RXFF_PTR_8814A				0x011C
+#define REG_CPWM_8814A					0x012F
+#define REG_FWIMR_8814A					0x0130
+#define REG_FWISR_8814A					0x0134
+#define REG_FTIMR_8814A					0x0138
+#define REG_PKTBUF_DBG_CTRL_8814A		0x0140
+#define REG_RXPKTBUF_CTRL_8814A		0x0142
+#define REG_PKTBUF_DBG_DATA_L_8814A	0x0144
+#define REG_PKTBUF_DBG_DATA_H_8814A	0x0148
+
+#define REG_WOWLAN_WAKE_REASON			REG_MCUTST_WOWLAN
+
+#define REG_TC0_CTRL_8814A				0x0150
+#define REG_TC1_CTRL_8814A				0x0154
+#define REG_TC2_CTRL_8814A				0x0158
+#define REG_TC3_CTRL_8814A				0x015C
+#define REG_TC4_CTRL_8814A				0x0160
+#define REG_TCUNIT_BASE_8814A			0x0164
+#define REG_RSVD3_8814A					0x0168
+#define REG_C2HEVT_MSG_NORMAL_8814A	0x01A0
+#define REG_C2HEVT_CLEAR_8814A			0x01AF
+#define REG_MCUTST_1_8814A				0x01C0
+#define REG_MCUTST_WOWLAN_8814A		0x01C7
+#define REG_FMETHR_8814A				0x01C8
+#define REG_HMETFR_8814A				0x01CC
+#define REG_HMEBOX_0_8814A				0x01D0
+#define REG_HMEBOX_1_8814A				0x01D4
+#define REG_HMEBOX_2_8814A				0x01D8
+#define REG_HMEBOX_3_8814A				0x01DC
+#define REG_LLT_INIT_8814A				0x01E0
+#define REG_LLT_ADDR_8814A				0x01E4 /* 20130415 KaiYuan add for 8814 */
+#define REG_HMEBOX_EXT0_8814A			0x01F0
+#define REG_HMEBOX_EXT1_8814A			0x01F4
+#define REG_HMEBOX_EXT2_8814A			0x01F8
+#define REG_HMEBOX_EXT3_8814A			0x01FC
+
+/* -----------------------------------------------------
+ *
+ *	0x0200h ~ 0x027Fh	TXDMA Configuration
+ *
+ * ----------------------------------------------------- */
+#define REG_FIFOPAGE_CTRL_1_8814A			0x0200
+#define REG_FIFOPAGE_CTRL_2_8814A		0x0204
+#define REG_AUTO_LLT_8814A					0x0208
+#define REG_TXDMA_OFFSET_CHK_8814A	0x020C
+#define REG_TXDMA_STATUS_8814A			0x0210
+#define REG_RQPN_NPQ_8814A				0x0214
+#define REG_TQPNT1_8814A					0x0218
+#define REG_TQPNT2_8814A					0x021C
+#define REG_TQPNT3_8814A					0x0220
+#define REG_TQPNT4_8814A					0x0224
+#define REG_RQPN_CTRL_1_8814A				0x0228
+#define REG_RQPN_CTRL_2_8814A				0x022C
+#define REG_FIFOPAGE_INFO_1_8814A			0x0230
+#define REG_FIFOPAGE_INFO_2_8814A			0x0234
+#define REG_FIFOPAGE_INFO_3_8814A			0x0238
+#define REG_FIFOPAGE_INFO_4_8814A			0x023C
+#define REG_FIFOPAGE_INFO_5_8814A			0x0240
+
+
+/* -----------------------------------------------------
+ *
+ *	0x0280h ~ 0x02FFh	RXDMA Configuration
+ *
+ * ----------------------------------------------------- */
+#define REG_RXDMA_AGG_PG_TH_8814A		0x0280
+#define REG_RXPKT_NUM_8814A				0x0284 /* The number of packets in RXPKTBUF. */
+#define REG_RXDMA_CONTROL_8814A			0x0286 /* ?????? Control the RX DMA. */
+#define REG_RXDMA_STATUS_8814A			0x0288
+#define REG_RXDMA_MODE_8814A				0x0290 /* ?????? */
+#define REG_EARLY_MODE_CONTROL_8814A	0x02BC /* ?????? */
+#define REG_RSVD5_8814A					0x02F0 /* ?????? */
+
+
+/* -----------------------------------------------------
+ *
+ *	0x0300h ~ 0x03FFh	PCIe
+ *
+ * ----------------------------------------------------- */
+#define	REG_PCIE_CTRL_REG_8814A			0x0300
+#define	REG_INT_MIG_8814A				0x0304	/* Interrupt Migration */
+#define	REG_BCNQ_TXBD_DESA_8814A		0x0308	/* TX Beacon Descriptor Address */
+#define	REG_MGQ_TXBD_DESA_8814A			0x0310	/* TX Manage Queue Descriptor Address */
+#define	REG_VOQ_TXBD_DESA_8814A			0x0318	/* TX VO Queue Descriptor Address */
+#define	REG_VIQ_TXBD_DESA_8814A			0x0320	/* TX VI Queue Descriptor Address */
+#define	REG_BEQ_TXBD_DESA_8814A			0x0328	/* TX BE Queue Descriptor Address */
+#define	REG_BKQ_TXBD_DESA_8814A			0x0330	/* TX BK Queue Descriptor Address */
+#define	REG_RXQ_RXBD_DESA_8814A			0x0338	/* RX Queue	Descriptor Address */
+#define REG_HI0Q_TXBD_DESA_8814A		0x0340
+#define REG_HI1Q_TXBD_DESA_8814A		0x0348
+#define REG_HI2Q_TXBD_DESA_8814A		0x0350
+#define REG_HI3Q_TXBD_DESA_8814A		0x0358
+#define REG_HI4Q_TXBD_DESA_8814A		0x0360
+#define REG_HI5Q_TXBD_DESA_8814A		0x0368
+#define REG_HI6Q_TXBD_DESA_8814A		0x0370
+#define REG_HI7Q_TXBD_DESA_8814A		0x0378
+#define	REG_MGQ_TXBD_NUM_8814A			0x0380
+#define	REG_RX_RXBD_NUM_8814A			0x0382
+#define	REG_VOQ_TXBD_NUM_8814A			0x0384
+#define	REG_VIQ_TXBD_NUM_8814A			0x0386
+#define	REG_BEQ_TXBD_NUM_8814A			0x0388
+#define	REG_BKQ_TXBD_NUM_8814A			0x038A
+#define	REG_HI0Q_TXBD_NUM_8814A			0x038C
+#define	REG_HI1Q_TXBD_NUM_8814A			0x038E
+#define	REG_HI2Q_TXBD_NUM_8814A			0x0390
+#define	REG_HI3Q_TXBD_NUM_8814A			0x0392
+#define	REG_HI4Q_TXBD_NUM_8814A			0x0394
+#define	REG_HI5Q_TXBD_NUM_8814A			0x0396
+#define	REG_HI6Q_TXBD_NUM_8814A			0x0398
+#define	REG_HI7Q_TXBD_NUM_8814A			0x039A
+#define	REG_TSFTIMER_HCI_8814A			0x039C
+
+/* Read Write Point */
+#define	REG_VOQ_TXBD_IDX_8814A			0x03A0
+#define	REG_VIQ_TXBD_IDX_8814A			0x03A4
+#define	REG_BEQ_TXBD_IDX_8814A			0x03A8
+#define	REG_BKQ_TXBD_IDX_8814A			0x03AC
+#define	REG_MGQ_TXBD_IDX_8814A			0x03B0
+#define	REG_RXQ_TXBD_IDX_8814A			0x03B4
+#define	REG_HI0Q_TXBD_IDX_8814A			0x03B8
+#define	REG_HI1Q_TXBD_IDX_8814A			0x03BC
+#define	REG_HI2Q_TXBD_IDX_8814A			0x03C0
+#define	REG_HI3Q_TXBD_IDX_8814A			0x03C4
+#define	REG_HI4Q_TXBD_IDX_8814A			0x03C8
+#define	REG_HI5Q_TXBD_IDX_8814A			0x03CC
+#define	REG_HI6Q_TXBD_IDX_8814A			0x03D0
+#define	REG_HI7Q_TXBD_IDX_8814A			0x03D4
+#define REG_DBG_SEL_V1_8814A				0x03D8
+#define REG_PCIE_HRPWM1_V1_8814A			0x03D9
+#define REG_PCIE_HCPWM1_V1_8814A			0x03DA
+#define REG_PCIE_CTRL2_8814A				0x03DB
+#define REG_PCIE_HRPWM2_V1_8814A			0x03DC
+#define REG_PCIE_HCPWM2_V1_8814A			0x03DE
+#define REG_PCIE_H2C_MSG_V1_8814A		0x03E0
+#define REG_PCIE_C2H_MSG_V1_8814A		0x03E4
+#define REG_DBI_WDATA_V1_8814A			0x03E8
+#define REG_DBI_RDATA_V1_8814A			0x03EC
+#define REG_DBI_FLAG_V1_8814A				0x03F0
+#define REG_MDIO_V1_8814A					0x03F4
+#define REG_PCIE_MIX_CFG_8814A			0x03F8
+#define REG_DBG_8814A						0x03FC
+/* -----------------------------------------------------
+ *
+ *	0x0400h ~ 0x047Fh	Protocol Configuration
+ *
+ * ----------------------------------------------------- */
+#define REG_VOQ_INFORMATION_8814A		0x0400
+#define REG_VIQ_INFORMATION_8814A		0x0404
+#define REG_BEQ_INFORMATION_8814A		0x0408
+#define REG_BKQ_INFORMATION_8814A		0x040C
+#define REG_MGQ_INFORMATION_8814A		0x0410
+#define REG_HGQ_INFORMATION_8814A		0x0414
+#define REG_BCNQ_INFORMATION_8814A	0x0418
+#define REG_TXPKT_EMPTY_8814A			0x041A
+#define REG_CPU_MGQ_INFORMATION_8814A	0x041C
+#define REG_FWHW_TXQ_CTRL_8814A		0x0420
+#define REG_HWSEQ_CTRL_8814A			0x0423
+#define REG_TXPKTBUF_BCNQ_BDNY_8814A	0x0424
+/* #define REG_MGQ_BDNY_8814A				0x0425 */
+#define REG_LIFETIME_EN_8814A				0x0426
+/* #define REG_FW_FREE_TAIL_8814A			0x0427 */
+#define REG_SPEC_SIFS_8814A				0x0428
+#define REG_RETRY_LIMIT_8814A				0x042A
+#define REG_TXBF_CTRL_8814A				0x042C
+#define REG_DARFRC_8814A				0x0430
+#define REG_RARFRC_8814A				0x0438
+#define REG_RRSR_8814A					0x0440
+#define REG_ARFR0_8814A					0x0444
+#define REG_ARFR1_8814A					0x044C
+#define REG_CCK_CHECK_8814A				0x0454
+#define REG_AMPDU_MAX_TIME_8814A			0x0455
+#define REG_TXPKTBUF_BCNQ1_BDNY_8814A	0x0456
+#define REG_AMPDU_MAX_LENGTH_8814A	0x0458
+#define REG_ACQ_STOP_8814A				0x045C
+#define REG_NDPA_RATE_8814A				0x045D
+#define REG_TX_HANG_CTRL_8814A			0x045E
+#define REG_NDPA_OPT_CTRL_8814A		0x045F
+#define REG_FAST_EDCA_CTRL_8814A		0x0460
+#define REG_RD_RESP_PKT_TH_8814A		0x0463
+#define REG_CMDQ_INFO_8814A				0x0464
+#define REG_Q4_INFO_8814A					0x0468
+#define REG_Q5_INFO_8814A					0x046C
+#define REG_Q6_INFO_8814A					0x0470
+#define REG_Q7_INFO_8814A					0x0474
+#define REG_WMAC_LBK_BUF_HD_8814A		0x0478
+#define REG_MGQ_PGBNDY_8814A				0x047A
+#define REG_INIRTS_RATE_SEL_8814A			0x0480
+#define REG_BASIC_CFEND_RATE_8814A		0x0481
+#define REG_STBC_CFEND_RATE_8814A		0x0482
+#define REG_DATA_SC_8814A					0x0483
+#define REG_MACID_SLEEP3_8814A			0x0484
+#define REG_MACID_SLEEP1_8814A			0x0488
+#ifdef CONFIG_WOWLAN
+	#define REG_TXPKTBUF_IV_LOW				0x0484
+	#define REG_TXPKTBUF_IV_HIGH			0x0488
+#endif /* CONFIG_WOWLAN */
+#define REG_ARFR2_8814A					0x048C
+#define REG_ARFR3_8814A					0x0494
+#define REG_ARFR4_8814A					0x049C
+#define REG_ARFR5_8814A					0x04A4
+#define REG_TXRPT_START_OFFSET_8814A		0x04AC
+#define REG_TRYING_CNT_TH_8814A			0x04B0
+#define REG_POWER_STAGE1_8814A		0x04B4
+#define REG_POWER_STAGE2_8814A		0x04B8
+#define REG_SW_AMPDU_BURST_MODE_CTRL_8814A	0x04BC
+#define REG_PKT_LIFE_TIME_8814A			0x04C0
+#define REG_PKT_BE_BK_LIFE_TIME_8814A		0x04C2 /* ?????? */
+#define REG_STBC_SETTING_8814A			0x04C4
+#define REG_STBC_8814A						0x04C5
+#define REG_QUEUE_CTRL_8814A				0x04C6
+#define REG_SINGLE_AMPDU_CTRL_8814A		0x04C7
+#define REG_PROT_MODE_CTRL_8814A		0x04C8
+#define REG_MAX_AGGR_NUM_8814A		0x04CA
+#define REG_RTS_MAX_AGGR_NUM_8814A	0x04CB
+#define REG_BAR_MODE_CTRL_8814A		0x04CC
+#define REG_RA_TRY_RATE_AGG_LMT_8814A	0x04CF
+#define REG_MACID_SLEEP2_8814A			0x04D0
+#define REG_MACID_SLEEP0_8814A			0x04D4
+#define REG_HW_SEQ0_8814A				0x04D8
+#define REG_HW_SEQ1_8814A				0x04DA
+#define REG_HW_SEQ2_8814A				0x04DC
+#define REG_HW_SEQ3_8814A				0x04DE
+#define REG_NULL_PKT_STATUS_8814A			0x04E0
+#define REG_PTCL_ERR_STATUS_8814A			0x04E2
+#define REG_DROP_PKT_NUM_8814A			0x04EC
+#define REG_PTCL_TX_RPT_8814A				0x04F0
+#define REG_Dummy_8814A					0x04FC
+
+
+/* -----------------------------------------------------
+ *
+ *	0x0500h ~ 0x05FFh	EDCA Configuration
+ *
+ * ----------------------------------------------------- */
+#define REG_EDCA_VO_PARAM_8814A			0x0500
+#define REG_EDCA_VI_PARAM_8814A			0x0504
+#define REG_EDCA_BE_PARAM_8814A			0x0508
+#define REG_EDCA_BK_PARAM_8814A			0x050C
+#define REG_BCNTCFG_8814A					0x0510
+#define REG_PIFS_8814A						0x0512
+#define REG_RDG_PIFS_8814A					0x0513
+#define REG_SIFS_CTX_8814A					0x0514
+#define REG_SIFS_TRX_8814A					0x0516
+#define REG_AGGR_BREAK_TIME_8814A			0x051A
+#define REG_SLOT_8814A						0x051B
+#define REG_TX_PTCL_CTRL_8814A				0x0520
+#define REG_TXPAUSE_8814A					0x0522
+#define REG_DIS_TXREQ_CLR_8814A			0x0523
+#define REG_RD_CTRL_8814A					0x0524
+/*
+ * Format for offset 540h-542h:
+ *	[3:0]:   TBTT prohibit setup in unit of 32us. The time for HW getting beacon content before TBTT.
+ *	[7:4]:   Reserved.
+ *	[19:8]:  TBTT prohibit hold in unit of 32us. The time for HW holding to send the beacon packet.
+ *	[23:20]: Reserved
+ * Description:
+ *	              |
+ * |<--Setup--|--Hold------------>|
+ *	--------------|----------------------
+ * |
+ * TBTT
+ * Note: We cannot update beacon content to HW or send any AC packets during the time between Setup and Hold.
+ * Described by Designer Tim and Bruce, 2011-01-14.
+ *   */
+#define REG_TBTT_PROHIBIT_8814A			0x0540
+#define REG_RD_NAV_NXT_8814A				0x0544
+#define REG_NAV_PROT_LEN_8814A			0x0546
+#define REG_BCN_CTRL_8814A					0x0550
+#define REG_BCN_CTRL_1_8814A				0x0551
+#define REG_MBID_NUM_8814A				0x0552
+#define REG_DUAL_TSF_RST_8814A				0x0553
+#define REG_MBSSID_BCN_SPACE_8814A		0x0554
+#define REG_DRVERLYINT_8814A				0x0558
+#define REG_BCNDMATIM_8814A				0x0559
+#define REG_ATIMWND_8814A					0x055A
+#define REG_USTIME_TSF_8814A				0x055C
+#define REG_BCN_MAX_ERR_8814A				0x055D
+#define REG_RXTSF_OFFSET_CCK_8814A		0x055E
+#define REG_RXTSF_OFFSET_OFDM_8814A		0x055F
+#define REG_TSFTR_8814A						0x0560
+#define REG_CTWND_8814A					0x0572
+#define REG_SECONDARY_CCA_CTRL_8814A		0x0577 /* ?????? */
+#define REG_PSTIMER_8814A					0x0580
+#define REG_TIMER0_8814A					0x0584
+#define REG_TIMER1_8814A					0x0588
+#define REG_BCN_PREDL_ITV_8814A			0x058F	/* Pre download beacon interval */
+#define REG_ACMHWCTRL_8814A				0x05C0
+#define REG_P2P_RST_8814A				0x05F0
+
+/* -----------------------------------------------------
+ *
+ *	0x0600h ~ 0x07FFh	WMAC Configuration
+ *
+ * ----------------------------------------------------- */
+#define REG_MAC_CR_8814A					0x0600
+#define REG_TCR_8814A						0x0604
+#define REG_RCR_8814A						0x0608
+#define REG_RX_PKT_LIMIT_8814A				0x060C
+#define REG_RX_DLK_TIME_8814A				0x060D
+#define REG_RX_DRVINFO_SZ_8814A			0x060F
+
+#define REG_MACID_8814A					0x0610
+#define REG_BSSID_8814A						0x0618
+#define REG_MAR_8814A						0x0620
+#define REG_MBIDCAMCFG_8814A				0x0628
+
+#define REG_USTIME_EDCA_8814A				0x0638
+#define REG_MAC_SPEC_SIFS_8814A			0x063A
+#define REG_RESP_SIFP_CCK_8814A			0x063C
+#define REG_RESP_SIFS_OFDM_8814A			0x063E
+#define REG_ACKTO_8814A					0x0640
+#define REG_CTS2TO_8814A					0x0641
+#define REG_EIFS_8814A						0x0642
+
+#define	REG_NAV_UPPER_8814A				0x0652	/* unit of 128 */
+#define REG_TRXPTCL_CTL_8814A				0x0668
+
+/* Security */
+#define REG_CAMCMD_8814A					0x0670
+#define REG_CAMWRITE_8814A				0x0674
+#define REG_CAMREAD_8814A					0x0678
+#define REG_CAMDBG_8814A					0x067C
+#define REG_SECCFG_8814A					0x0680
+
+/* Power */
+#define REG_WOW_CTRL_8814A				0x0690
+#define REG_PS_RX_INFO_8814A				0x0692
+#define REG_UAPSD_TID_8814A				0x0693
+#define REG_WKFMCAM_NUM_8814A			0x0698
+#define REG_RXFLTMAP0_8814A				0x06A0
+#define REG_RXFLTMAP1_8814A				0x06A2
+#define REG_RXFLTMAP2_8814A				0x06A4
+#define REG_BCN_PSR_RPT_8814A				0x06A8
+#define REG_BT_COEX_TABLE_8814A			0x06C0
+#define REG_TX_DATA_RSP_RATE_8814A		0x06DE
+#define REG_ASSOCIATED_BFMER0_INFO_8814A	0x06E4
+#define REG_ASSOCIATED_BFMER1_INFO_8814A	0x06EC
+#define REG_CSI_RPT_PARAM_BW20_8814A		0x06F4
+#define REG_CSI_RPT_PARAM_BW40_8814A		0x06F8
+#define REG_CSI_RPT_PARAM_BW80_8814A		0x06FC
+
+/* Hardware Port 2 */
+#define REG_MACID1_8814A					0x0700
+#define REG_BSSID1_8814A					0x0708
+/* Hardware Port 3 */
+#define REG_MACID2_8814A					0x1620
+#define REG_BSSID2_8814A					0x1628
+/* Hardware Port 4 */
+#define REG_MACID3_8814A					0x1630
+#define REG_BSSID3_8814A					0x1638
+/* Hardware Port 5 */
+#define REG_MACID4_8814A					0x1640
+#define REG_BSSID4_8814A					0x1648
+
+#define REG_ASSOCIATED_BFMEE_SEL_8814A	0x0714
+#define REG_SND_PTCL_CTRL_8814A			0x0718
+#define REG_IQ_DUMP_8814A					0x07C0
+
+#define REG_CPU_DMEM_CON_8814A			0x1080
+
+/**** page 19 ****/
+/* TX BeamForming */
+#define	REG_BB_TXBF_ANT_SET_BF1				0x19ac
+#define	REG_BB_TXBF_ANT_SET_BF0				0x19b4
+
+/*	0x1200h ~ 0x12FFh	DDMA CTRL
+ *
+ * ----------------------------------------------------- */
+#define REG_DDMA_CH0SA                   0x1200
+#define REG_DDMA_CH0DA                   0x1204
+#define REG_DDMA_CH0CTRL                0x1208
+#define REG_DDMA_CH1SA                   0x1210
+#define REG_DDMA_CH1DA	0x1214
+#define REG_DDMA_CH1CTRL                0x1218
+#define REG_DDMA_CH2SA                   0x1220
+#define REG_DDMA_CH2DA                   0x1224
+#define REG_DDMA_CH2CTRL                0x1228
+#define REG_DDMA_CH3SA                   0x1230
+#define REG_DDMA_CH3DA                   0x1234
+#define REG_DDMA_CH3CTRL                0x1238
+#define REG_DDMA_CH4SA                   0x1240
+#define REG_DDMA_CH4DA                   0x1244
+#define REG_DDMA_CH4CTRL                0x1248
+#define REG_DDMA_CH5SA                   0x1250
+#define REG_DDMA_CH5DA                   0x1254
+#define REG_DDMA_CH5CTRL                0x1258
+#define REG_DDMA_INT_MSK                0x12E0
+#define REG_DDMA_CHSTATUS              0x12E8
+#define REG_DDMA_CHKSUM                 0x12F0
+#define REG_DDMA_MONITER                0x12FC
+
+#define REG_Q0_Q1_INFO_8814A		0x1400
+#define REG_Q2_Q3_INFO_8814A		0x1404
+#define REG_Q4_Q5_INFO_8814A		0x1408
+#define REG_Q6_Q7_INFO_8814A		0x140C
+#define REG_MGQ_HIQ_INFO_8814A	0x1410
+#define REG_CMDQ_BCNQ_INFO_8814A	0x1414
+
+#define DDMA_LEN_MASK		0x0001FFFF
+#define FW_CHKSUM_DUMMY_SZ		8
+#define DDMA_CH_CHKSUM_CNT		BIT(24)
+#define DDMA_RST_CHKSUM_STS		BIT(25)
+#define DDMA_MODE_BLOCK_CPU		BIT(26)
+#define DDMA_CHKSUM_FAIL			BIT(27)
+#define DDMA_DA_W_DISABLE			BIT(28)
+#define DDMA_CHKSUM_EN			BIT(29)
+#define DDMA_CH_OWN	BIT(31)
+
+
+/* 3081 FWDL */
+#define FWDL_EN                 BIT0
+#define IMEM_BOOT_DL_RDY        BIT1
+#define IMEM_BOOT_CHKSUM_FAIL   BIT2
+#define IMEM_DL_RDY             BIT3
+#define IMEM_CHKSUM_OK        BIT4
+#define DMEM_DL_RDY             BIT5
+#define DMEM_CHKSUM_OK        BIT6
+#define EMEM_DL_RDY             BIT7
+#define EMEM_CHKSUM_FAIL        BIT8
+#define EMEM_TXBUF_DL_RDY       BIT9
+#define EMEM_TXBUF_CHKSUM_FAIL  BIT10
+#define CPU_CLK_SWITCH_BUSY     BIT11
+#define CPU_CLK_SEL             (BIT12 | BIT13)
+#define FWDL_OK                 BIT14
+#define FW_INIT_RDY             BIT15
+#define R_EN_BOOT_FLASH         BIT20
+
+#define OCPBASE_IMEM_3081        0x00000000
+#define OCPBASE_DMEM_3081        0x00200000
+#define OCPBASE_RPTBUF_3081      0x18660000
+#define OCPBASE_RXBUF2_3081      0x18680000
+#define OCPBASE_RXBUF_3081       0x18700000
+#define OCPBASE_TXBUF_3081       0x18780000
+
+
+#define REG_FAST_EDCA_VOVI_SETTING_8814A 0x1448
+#define REG_FAST_EDCA_BEBK_SETTING_8814A 0x144C
+
+
+/* -----------------------------------------------------
+ *   */
+
+
+/* -----------------------------------------------------
+ *
+ *	Redifine 8192C register definition for compatibility
+ *
+ * ----------------------------------------------------- */
+
+/* TODO: use these definition when using REG_xxx naming rule.
+ * NOTE: DO NOT Remove these definition. Use later. */
+#define	EFUSE_CTRL_8814A					REG_EFUSE_CTRL_8814A		/* E-Fuse Control. */
+#define	EFUSE_TEST_8814A					REG_LDO_EFUSE_CTRL_8814A		/* E-Fuse Test. */
+#define	MSR_8814A							(REG_CR_8814A + 2)		/* Media Status register */
+#define	ISR_8814A							REG_HISR0_8814A
+#define	TSFR_8814A							REG_TSFTR_8814A			/* Timing Sync Function Timer Register. */
+
+#define PBP_8814A							REG_PBP_8814A
+
+/* Redifine MACID register, to compatible prior ICs. */
+#define	IDR0_8814A							REG_MACID_8814A			/* MAC ID Register, Offset 0x0050-0x0053 */
+#define	IDR4_8814A							(REG_MACID_8814A + 4)	/* MAC ID Register, Offset 0x0054-0x0055 */
+
+
+/*
+ * 9. Security Control Registers	(Offset: )
+ *   */
+#define	RWCAM_8814A						REG_CAMCMD_8814A		/* IN 8190 Data Sheet is called CAMcmd */
+#define	WCAMI_8814A						REG_CAMWRITE_8814A		/* Software write CAM input content */
+#define	RCAMO_8814A						REG_CAMREAD_8814A		/* Software read/write CAM config */
+#define	CAMDBG_8814A						REG_CAMDBG_8814A
+#define	SECR_8814A							REG_SECCFG_8814A		/* Security Configuration Register */
+
+
+/* ----------------------------------------------------------------------------
+ * 8195 IMR/ISR bits						(offset 0xB0,  8bits)
+ * ---------------------------------------------------------------------------- */
+#define	IMR_DISABLED_8814A					0
+/* IMR DW0(0x00B0-00B3) Bit 0-31 */
+#define	IMR_TIMER2_8814A					BIT31		/* Timeout interrupt 2 */
+#define	IMR_TIMER1_8814A					BIT30		/* Timeout interrupt 1	 */
+#define	IMR_PSTIMEOUT_8814A				BIT29		/* Power Save Time Out Interrupt */
+#define	IMR_GTINT4_8814A					BIT28		/* When GTIMER4 expires, this bit is set to 1	 */
+#define	IMR_GTINT3_8814A					BIT27		/* When GTIMER3 expires, this bit is set to 1	 */
+#define	IMR_TXBCN0ERR_8814A				BIT26		/* Transmit Beacon0 Error			 */
+#define	IMR_TXBCN0OK_8814A					BIT25		/* Transmit Beacon0 OK			 */
+#define	IMR_TSF_BIT32_TOGGLE_8814A		BIT24		/* TSF Timer BIT32 toggle indication interrupt			 */
+#define	IMR_BCNDMAINT0_8814A				BIT20		/* Beacon DMA Interrupt 0			 */
+#define	IMR_BCNDERR0_8814A					BIT16		/* Beacon Queue DMA OK0			 */
+#define	IMR_HSISR_IND_ON_INT_8814A		BIT15		/* HSISR Indicator (HSIMR & HSISR is true, this bit is set to 1) */
+#define	IMR_BCNDMAINT_E_8814A				BIT14		/* Beacon DMA Interrupt Extension for Win7			 */
+#define	IMR_ATIMEND_8814A					BIT12		/* CTWidnow End or ATIM Window End */
+#define	IMR_C2HCMD_8814A					BIT10		/* CPU to Host Command INT Status, Write 1 clear	 */
+#define	IMR_CPWM2_8814A					BIT9			/* CPU power Mode exchange INT Status, Write 1 clear	 */
+#define	IMR_CPWM_8814A						BIT8			/* CPU power Mode exchange INT Status, Write 1 clear	 */
+#define	IMR_HIGHDOK_8814A					BIT7			/* High Queue DMA OK	 */
+#define	IMR_MGNTDOK_8814A					BIT6			/* Management Queue DMA OK	 */
+#define	IMR_BKDOK_8814A					BIT5			/* AC_BK DMA OK		 */
+#define	IMR_BEDOK_8814A					BIT4			/* AC_BE DMA OK	 */
+#define	IMR_VIDOK_8814A					BIT3			/* AC_VI DMA OK		 */
+#define	IMR_VODOK_8814A					BIT2			/* AC_VO DMA OK	 */
+#define	IMR_RDU_8814A						BIT1			/* Rx Descriptor Unavailable	 */
+#define	IMR_ROK_8814A						BIT0			/* Receive DMA OK */
+
+/* IMR DW1(0x00B4-00B7) Bit 0-31 */
+#define	IMR_MCUERR_8814A						BIT28		/* Beacon DMA Interrupt 7 */
+#define	IMR_BCNDMAINT7_8814A				BIT27		/* Beacon DMA Interrupt 7 */
+#define	IMR_BCNDMAINT6_8814A				BIT26		/* Beacon DMA Interrupt 6 */
+#define	IMR_BCNDMAINT5_8814A				BIT25		/* Beacon DMA Interrupt 5 */
+#define	IMR_BCNDMAINT4_8814A				BIT24		/* Beacon DMA Interrupt 4 */
+#define	IMR_BCNDMAINT3_8814A				BIT23		/* Beacon DMA Interrupt 3 */
+#define	IMR_BCNDMAINT2_8814A				BIT22		/* Beacon DMA Interrupt 2 */
+#define	IMR_BCNDMAINT1_8814A				BIT21		/* Beacon DMA Interrupt 1 */
+#define	IMR_BCNDOK7_8814A					BIT20		/* Beacon Queue DMA OK Interrup 7 */
+#define	IMR_BCNDOK6_8814A					BIT19		/* Beacon Queue DMA OK Interrup 6 */
+#define	IMR_BCNDOK5_8814A					BIT18		/* Beacon Queue DMA OK Interrup 5 */
+#define	IMR_BCNDOK4_8814A					BIT17		/* Beacon Queue DMA OK Interrup 4 */
+#define	IMR_BCNDOK3_8814A					BIT16		/* Beacon Queue DMA OK Interrup 3 */
+#define	IMR_BCNDOK2_8814A					BIT15		/* Beacon Queue DMA OK Interrup 2 */
+#define	IMR_BCNDOK1_8814A					BIT14		/* Beacon Queue DMA OK Interrup 1 */
+#define	IMR_ATIMEND_E_8814A				BIT13		/* ATIM Window End Extension for Win7 */
+#define	IMR_TXERR_8814A					BIT11		/* Tx Error Flag Interrupt Status, write 1 clear. */
+#define	IMR_RXERR_8814A					BIT10		/* Rx Error Flag INT Status, Write 1 clear */
+#define	IMR_TXFOVW_8814A					BIT9			/* Transmit FIFO Overflow */
+#define	IMR_RXFOVW_8814A					BIT8			/* Receive FIFO Overflow */
+
+
+#ifdef CONFIG_PCI_HCI
+	#define IMR_TX_MASK			(IMR_VODOK_8814A | IMR_VIDOK_8814A | IMR_BEDOK_8814A | IMR_BKDOK_8814A | IMR_MGNTDOK_8814A | IMR_HIGHDOK_8814A)
+
+	#define RT_BCN_INT_MASKS	(IMR_BCNDMAINT0_8814A | IMR_TXBCN0OK_8814A | IMR_TXBCN0ERR_8814A | IMR_BCNDERR0_8814A)
+
+	#define RT_AC_INT_MASKS	(IMR_VIDOK_8814A | IMR_VODOK_8814A | IMR_BEDOK_8814A | IMR_BKDOK_8814A)
+#endif
+
+
+/*===================================================================
+=====================================================================
+Here the register defines are for 92C. When the define is as same with 92C,
+we will use the 92C's define for the consistency
+So the following defines for 92C is not entire!!!!!!
+=====================================================================
+=====================================================================*/
+
+
+/* -----------------------------------------------------
+ *
+ *	0xFE00h ~ 0xFE55h	USB Configuration
+ *
+ * ----------------------------------------------------- */
+
+/* 2 Special Option */
+#define USB_AGG_EN_8814A			BIT(7)
+#define REG_USB_HRPWM_U3			0xF052
+
+#define LAST_ENTRY_OF_TX_PKT_BUFFER_8814A       (2048-1)	/* 20130415 KaiYuan add for 8814 */
+
+#endif /* __RTL8814A_SPEC_H__ */
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/include/rtl8814a_sreset.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/rtl8814a_sreset.h
--- linux-5.6.3/3rdparty/rtl8821ce/include/rtl8814a_sreset.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/rtl8814a_sreset.h	2020-04-10 16:35:06.850661655 +0300
@@ -0,0 +1,24 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#ifndef _RTL88814A_SRESET_H_
+#define _RTL8814A_SRESET_H_
+
+#include <rtw_sreset.h>
+
+#ifdef DBG_CONFIG_ERROR_DETECT
+	extern void rtl8814_sreset_xmit_status_check(_adapter *padapter);
+	extern void rtl8814_sreset_linked_status_check(_adapter *padapter);
+#endif
+#endif
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/include/rtl8814a_xmit.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/rtl8814a_xmit.h
--- linux-5.6.3/3rdparty/rtl8821ce/include/rtl8814a_xmit.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/rtl8814a_xmit.h	2020-04-10 16:35:06.850661655 +0300
@@ -0,0 +1,311 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#ifndef __RTL8814A_XMIT_H__
+#define __RTL8814A_XMIT_H__
+
+typedef struct txdescriptor_8814 {
+	/* Offset 0 */
+	u32 pktlen:16;
+	u32 offset:8;
+	u32 bmc:1;
+	u32 htc:1;
+	u32 ls:1;
+} TXDESC_8814, *PTXDESC_8814;
+
+
+#define OFFSET_SZ	0
+#define OFFSET_SHT	16
+
+
+
+#ifdef CONFIG_SDIO_HCI
+	#define SET_TX_DESC_SDIO_TXSEQ_8814A(__pTxDesc, __Value)			SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 16, 8, __Value)
+#endif /* CONFIG_SDIO_HCI */
+
+/* -----------------------------------------------------------------
+ *	RTL8814A TX BUFFER DESC
+ * -----------------------------------------------------------------
+ *
+- Each TXBD has 4 segment.
+ -- For 32 bit, each segment is 8 bytes.
+ -- For 64 bit, each segment is 16 bytes.
+*/
+#if 0
+	#if 1 /* 32 bit */
+		#define SET_TX_EXTBUFF_DESC_LEN_8814A(__pTxDesc, __Value, __Set) SET_BITS_TO_LE_4BYTE(__pTxDesc+(__Set*8), 0, 16, __Value)
+		#define SET_TX_EXTBUFF_DESC_ADDR_LOW_8814A(__pTxDesc, __Value, __Set) SET_BITS_TO_LE_4BYTE(__pTxDesc+(__Set*8)+4, 0, 32, __Value)
+	#else /* 64 bit */
+		#define SET_TX_EXTBUFF_DESC_LEN_8814A(__pTxDesc, __Value, __Set) SET_BITS_TO_LE_4BYTE(__pTxDesc+(__Set*16), 0, 16, __Value)
+		#define SET_TX_EXTBUFF_DESC_ADDR_LOW_8814A(__pTxDesc, __Value, __Set) SET_BITS_TO_LE_4BYTE(__pTxDesc+(__Set*16)+4, 0, 32, __Value)
+	#endif
+	#define SET_TX_EXTBUFF_DESC_ADDR_HIGH_8814A(__pTxDesc, __Value, __Set) SET_BITS_TO_LE_4BYTE(__pTxDesc+(__Set*16)+8, 0, 32, __Value)
+#endif
+/*c2h-DWORD 2*/
+#define GET_RX_STATUS_DESC_RPT_SEL_8814A(__pRxDesc)			LE_BITS_TO_4BYTE(__pRxDesc+8, 28, 1)
+
+/* *********************************************************
+ * for Txfilldescroptor8814Ae, fill the desc content. */
+#if 1 /* 32 bit */
+	#define SET_TXBUFFER_DESC_LEN_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc+((__Offset)*8), 0, 16, __Valeu)
+	#define SET_TXBUFFER_DESC_AMSDU_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc+((__Offset)*8), 31, 1, __Valeu)
+	#define SET_TXBUFFER_DESC_ADD_LOW_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc+((__Offset)*8)+4, 0, 32, __Valeu)
+#else /* 64 bit */
+	#define SET_TXBUFFER_DESC_LEN_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc+((__Offset)*16), 0, 16, __Valeu)
+	#define SET_TXBUFFER_DESC_AMSDU_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc+((__Offset)*16), 31, 1, __Valeu)
+	#define SET_TXBUFFER_DESC_ADD_LOW_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc+((__Offset)*16)+4, 0, 32, __Valeu)
+#endif
+#define SET_TXBUFFER_DESC_ADD_HIGT_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc+((__Offset)*16)+8, 0, 32, __Valeu)
+
+/* ********************************************************* */
+
+/* TX buffer
+ * *************
+ * Dword 0 */
+#define SET_TX_BUFF_DESC_LEN_0_8814A(__pTxDesc, __Valeu)			SET_BITS_TO_LE_4BYTE(__pTxDesc, 0, 16, __Valeu)
+#define SET_TX_BUFF_DESC_PSB_8814A(__pTxDesc, __Value)			SET_BITS_TO_LE_4BYTE(__pTxDesc, 16, 15, __Value)
+#define SET_TX_BUFF_DESC_OWN_8814A(__pTxDesc, __Value)			SET_BITS_TO_LE_4BYTE(__pTxDesc, 31, 1, __Value)
+#define GET_TX_BUFF_DESC_OWN_8814A(__pTxDesc)				LE_BITS_TO_4BYTE(__pTxDesc, 31, 1)
+
+/* Dword 1 */
+#define SET_TX_BUFF_DESC_ADDR_LOW_0_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 0, 32, __Value)
+#define GET_TX_BUFF_DESC_ADDR_LOW_0_8814A(__pTxDesc)			LE_BITS_TO_4BYTE(__pTxDesc+4, 0, 32)
+/* Dword 2 */
+#define SET_TX_BUFF_DESC_ADDR_HIGH_0_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 0, 32, __Value)
+#define GET_TX_BUFF_DESC_ADDR_HIGH_0_8814A(__pTxDesc)			LE_BITS_TO_4BYTE(__pTxDesc+8, 0, 32)
+/* Dword 3 */ /* RESERVED 0 */
+
+#if 0 /* 64 bit */
+	/* Dword 4 */
+	#define SET_TX_BUFF_DESC_LEN_1_8814A(__pTxDesc, __Value)			SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 0, 16, __Value)
+	#define SET_TX_BUFF_DESC_AMSDU_1_8814A(__pTxDesc, __Value)		SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 31, 1, __Value)
+	/* Dword 5 */
+	#define SET_TX_BUFF_DESC_ADDR_LOW_1_8814A(__pTxDesc, __Value)	SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 0, 32, __Value)
+	/* Dword 6 */
+	#define SET_TX_BUFF_DESC_ADDR_HIGH_1_8814A(__pTxDesc, __Value)	SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 0, 32, __Value)
+	/* Dword 7 */ /* RESERVED 0 */
+	/* Dword 8 */
+	#define SET_TX_BUFF_DESC_LEN_2_8814A(__pTxDesc, __Value)			SET_BITS_TO_LE_4BYTE(__pTxDesc+32, 0, 16, __Value)
+	#define SET_TX_BUFF_DESC_AMSDU_2_8814A(__pTxDesc, __Value)		SET_BITS_TO_LE_4BYTE(__pTxDesc+32, 31, 1, __Value)
+	/* Dword 9 */
+	#define SET_TX_BUFF_DESC_ADDR_LOW_2_8814A(__pTxDesc, __Value)	SET_BITS_TO_LE_4BYTE(__pTxDesc+36, 0, 32, __Value)
+	/* Dword 10 */
+	#define SET_TX_BUFF_DESC_ADDR_HIGH_2_8814A(__pTxDesc, __Value)	SET_BITS_TO_LE_4BYTE(__pTxDesc+40, 0, 32, __Value)
+	/* Dword 11 */ /* RESERVED 0 */
+	/* Dword 12 */
+	#define SET_TX_BUFF_DESC_LEN_3_8814A(__pTxDesc, __Value)			SET_BITS_TO_LE_4BYTE(__pTxDesc+48, 0, 16, __Value)
+	#define SET_TX_BUFF_DESC_AMSDU_3_8814A(__pTxDesc, __Value)		SET_BITS_TO_LE_4BYTE(__pTxDesc+48, 31, 1, __Value)
+	/* Dword 13 */
+	#define SET_TX_BUFF_DESC_ADDR_LOW_3_8814A(__pTxDesc, __Value)	SET_BITS_TO_LE_4BYTE(__pTxDesc+52, 0, 32, __Value)
+	/* Dword 14 */
+	#define SET_TX_BUFF_DESC_ADDR_HIGH_3_8814A(__pTxDesc, __Value)	SET_BITS_TO_LE_4BYTE(__pTxDesc+56, 0, 32, __Value)
+	/* Dword 15 */ /* RESERVED 0 */
+#endif
+
+/* *****Desc content
+ * TX Info
+ * *************
+ * Dword 0 */
+#define SET_TX_DESC_PKT_SIZE_8814A(__pTxDesc, __Value)						SET_BITS_TO_LE_4BYTE(__pTxDesc, 0, 16, __Value)
+#define GET_TX_DESC_PKT_SIZE_8814A(__pTxDesc)									LE_BITS_TO_4BYTE(__pTxDesc, 0, 16)
+#define SET_TX_DESC_OFFSET_8814A(__pTxDesc, __Value)							SET_BITS_TO_LE_4BYTE(__pTxDesc, 16, 8, __Value)
+#define GET_TX_DESC_OFFSET_8814A(__pTxDesc)									LE_BITS_TO_4BYTE(__pTxDesc, 16, 8)
+#define SET_TX_DESC_BMC_8814A(__pTxDesc, __Value)							SET_BITS_TO_LE_4BYTE(__pTxDesc, 24, 1, __Value)
+#define SET_TX_DESC_HTC_8814A(__pTxDesc, __Value)								SET_BITS_TO_LE_4BYTE(__pTxDesc, 25, 1, __Value)
+#define SET_TX_DESC_LAST_SEG_8814A(__pTxDesc, __Value)						SET_BITS_TO_LE_4BYTE(__pTxDesc, 26, 1, __Value)
+#define SET_TX_DESC_LINIP_8814A(__pTxDesc, __Value)							SET_BITS_TO_LE_4BYTE(__pTxDesc, 28, 1, __Value)
+#define SET_TX_DESC_AMSDU_PAD_EN_8814A(__pTxDesc, __Value)					SET_BITS_TO_LE_4BYTE(__pTxDesc, 27, 1, __Value)
+#define SET_TX_DESC_NO_ACM_8814A(__pTxDesc, __Value)							SET_BITS_TO_LE_4BYTE(__pTxDesc, 29, 1, __Value)
+#define SET_TX_DESC_GF_8814A(__pTxDesc, __Value)								SET_BITS_TO_LE_4BYTE(__pTxDesc, 30, 1, __Value)
+#define SET_TX_DESC_DISQSELSEQ_8814A(__pTxDesc, __Value)						SET_BITS_TO_LE_4BYTE(__pTxDesc, 31, 1, __Value)
+
+/* Dword 1 */
+#define SET_TX_DESC_MACID_8814A(__pTxDesc, __Value)							SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 0, 7, __Value)
+#define SET_TX_DESC_QUEUE_SEL_8814A(__pTxDesc, __Value)						SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 8, 5, __Value)
+#define SET_TX_DESC_RDG_NAV_EXT_8814A(__pTxDesc, __Value)					SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 13, 1, __Value)
+#define SET_TX_DESC_LSIG_TXOP_EN_8814A(__pTxDesc, __Value)					SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 14, 1, __Value)
+#define SET_TX_DESC_PIFS_8814A(__pTxDesc, __Value)							SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 15, 1, __Value)
+#define SET_TX_DESC_RATE_ID_8814A(__pTxDesc, __Value)							SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 16, 5, __Value)
+#define SET_TX_DESC_EN_DESC_ID_8814A(__pTxDesc, __Value)						SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 21, 1, __Value)
+#define SET_TX_DESC_SEC_TYPE_8814A(__pTxDesc, __Value)						SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 22, 2, __Value)
+#define SET_TX_DESC_PKT_OFFSET_8814A(__pTxDesc, __Value)						SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 24, 5, __Value)
+#define SET_TX_DESC_MORE_DATA_8814A(__pTxDesc, __Value)						SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 29, 1, __Value)
+#define SET_TX_DESC_TXOP_PS_CAP_8814A(__pTxDesc, __Value)					SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 30, 1, __Value)
+#define SET_TX_DESC_TXOP_PS_MODE_8814A(__pTxDesc, __Value)					SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 31, 1, __Value)
+
+
+/* Dword 2 */
+#define SET_TX_DESC_PAID_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 0,  9, __Value)
+#define SET_TX_DESC_CCA_RTS_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 10, 2, __Value)
+#define SET_TX_DESC_AGG_ENABLE_8814A(__pTxDesc, __Value)		SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 12, 1, __Value)
+#define SET_TX_DESC_RDG_ENABLE_8814A(__pTxDesc, __Value)		SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 13, 1, __Value)
+#define SET_TX_DESC_NULL_0_8814A(__pTxDesc, __Value)		SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 14, 1, __Value)
+#define SET_TX_DESC_NULL_1_8814A(__pTxDesc, __Value)		SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 15, 1, __Value)
+#define SET_TX_DESC_BK_8814A(__pTxDesc, __Value)				SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 16, 1, __Value)
+#define SET_TX_DESC_MORE_FRAG_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 17, 1, __Value)
+#define GET_TX_DESC_MORE_FRAG_8814A(__pTxDesc)				LE_BITS_TO_4BYTE(__pTxDesc+8, 17, 1)
+#define SET_TX_DESC_RAW_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 18, 1, __Value)
+#define SET_TX_DESC_SPE_RPT_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 19, 1, __Value)
+#define SET_TX_DESC_AMPDU_DENSITY_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 20, 3, __Value)
+#define SET_TX_DESC_BT_NULL_8814A(__pTxDesc, __Value)			SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 23, 1, __Value)
+#define SET_TX_DESC_GID_8814A(__pTxDesc, __Value)			SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 24, 6, __Value)
+#define SET_TX_DESC_HW_AES_IV_8814A(__pTxDesc, __Value)			SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 31, 1, __Value)
+
+
+/* Dword 3 */
+#define SET_TX_DESC_WHEADER_LEN_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 0, 5, __Value)
+#define SET_TX_DESC_EARLY_RATE_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 5, 1, __Value)
+#define SET_TX_DESC_HW_SSN_SEL_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 6, 2, __Value)
+#define SET_TX_DESC_USE_RATE_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 8, 1, __Value)
+#define SET_TX_DESC_DISABLE_RTS_FB_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 9, 1, __Value)
+#define SET_TX_DESC_DISABLE_FB_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 10, 1, __Value)
+#define SET_TX_DESC_CTS2SELF_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 11, 1, __Value)
+#define SET_TX_DESC_RTS_ENABLE_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 12, 1, __Value)
+#define SET_TX_DESC_HW_RTS_ENABLE_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 13, 1, __Value)
+#define SET_TX_DESC_CHECK_EN_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 14, 1, __Value)
+#define SET_TX_DESC_NAV_USE_HDR_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 15, 1, __Value)
+#define SET_TX_DESC_USE_MAX_LEN_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 16, 1, __Value)
+#define SET_TX_DESC_MAX_AGG_NUM_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 17, 5, __Value)
+#define SET_TX_DESC_NDPA_8814A(__pTxDesc, __Value)		SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 22, 2, __Value)
+#define SET_TX_DESC_AMPDU_MAX_TIME_8814A(__pTxDesc, __Value)		SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 24, 8, __Value)
+
+/* Dword 4 */
+#define SET_TX_DESC_TX_RATE_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 0, 7, __Value)
+#define SET_TX_DESC_TRY_RATE_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 7, 1, __Value)
+#define SET_TX_DESC_DATA_RATE_FB_LIMIT_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 8, 5, __Value)
+#define SET_TX_DESC_RTS_RATE_FB_LIMIT_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 13, 4, __Value)
+#define SET_TX_DESC_RETRY_LIMIT_ENABLE_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 17, 1, __Value)
+#define SET_TX_DESC_DATA_RETRY_LIMIT_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 18, 6, __Value)
+#define SET_TX_DESC_RTS_RATE_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 24, 5, __Value)
+#define SET_TX_DESC_PCTS_ENABLE_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 29, 1, __Value)
+#define SET_TX_DESC_PCTS_MASK_IDX_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 30, 2, __Value)
+
+
+/* Dword 5 */
+#define SET_TX_DESC_DATA_SC_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 0, 4, __Value)
+#define SET_TX_DESC_DATA_SHORT_8814A(__pTxDesc, __Value)	SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 4, 1, __Value)
+#define SET_TX_DESC_DATA_BW_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 5, 2, __Value)
+#define SET_TX_DESC_DATA_LDPC_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 7, 1, __Value)
+#define SET_TX_DESC_DATA_STBC_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 8, 2, __Value)
+#define SET_TX_DESC_CTROL_STBC_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 10, 2, __Value)
+#define SET_TX_DESC_RTS_SHORT_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 12, 1, __Value)
+#define SET_TX_DESC_RTS_SC_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 13, 4, __Value)
+#define SET_TX_DESC_SIGNALING_TA_PKT_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 17, 1, __Value)
+#define SET_TX_DESC_PORT_ID_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 21, 3, __Value)/* 20130415 KaiYuan add for 8814 */
+#define SET_TX_DESC_TX_ANT_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 24, 4, __Value)
+#define SET_TX_DESC_TX_POWER_OFFSET_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 28, 3, __Value)
+
+/* Dword 6 */
+#define SET_TX_DESC_SW_DEFINE_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 0, 12, __Value)
+#define SET_TX_DESC_MBSSID_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 12, 4, __Value)
+#define SET_TX_DESC_ANTSEL_A_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 16, 3, __Value)
+#define SET_TX_DESC_ANTSEL_B_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 19, 3, __Value)
+#define SET_TX_DESC_ANT_MAPA_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 22, 2, __Value)
+#define SET_TX_DESC_ANT_MAPB_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 24, 2, __Value)
+#define SET_TX_DESC_ANT_MAPC_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 26, 2, __Value)
+#define SET_TX_DESC_ANT_MAPD_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 28, 2, __Value)
+
+
+/* Dword 7 */
+#ifdef CONFIG_PCI_HCI
+	#define SET_TX_DESC_TX_BUFFER_SIZE_8814A(__pTxDesc, __Value)		SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 0, 16, __Value)
+#endif
+#if defined(CONFIG_SDIO_HCI)|| defined(CONFIG_USB_HCI)
+	#define SET_TX_DESC_TX_DESC_CHECKSUM_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 0, 16, __Value)
+#endif
+#define SET_TX_DESC_NTX_MAP_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 20, 4, __Value)
+#define SET_TX_DESC_USB_TXAGG_NUM_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 24, 8, __Value)
+
+
+/* Dword 8 */
+#define SET_TX_DESC_RTS_RC_8814A(__pTxDesc, __Value)			SET_BITS_TO_LE_4BYTE(__pTxDesc+32, 0, 6, __Value)
+#define SET_TX_DESC_BAR_RTY_TH_8814A(__pTxDesc, __Value)			SET_BITS_TO_LE_4BYTE(__pTxDesc+32, 6, 2, __Value)
+#define SET_TX_DESC_DATA_RC_8814A(__pTxDesc, __Value)			SET_BITS_TO_LE_4BYTE(__pTxDesc+32, 8, 6, __Value)
+#define SET_TX_DESC_EN_HWEXSEQ_8814A(__pTxDesc, __Value)			SET_BITS_TO_LE_4BYTE(__pTxDesc+32, 14, 1, __Value)
+#define SET_TX_DESC_HWSEQ_EN_8814A(__pTxDesc, __Value)			SET_BITS_TO_LE_4BYTE(__pTxDesc+32, 15, 1, __Value)
+#if defined(CONFIG_PCI_HCI)|| defined(CONFIG_USB_HCI)
+	#define SET_TX_DESC_NEXT_HEAD_PAGE_L_8814A(__pTxDesc, __Value)(__pTxDesc, __Value)	SET_BITS_TO_LE_4BYTE(__pTxDesc+32, 16, 8, __Value)
+#endif
+#ifdef CONFIG_SDIO_HCI
+	#define SET_TX_DESC_SDIO_SEQ_8814A(__pTxDesc, __Value)(__pTxDesc, __Value) 			SET_BITS_TO_LE_4BYTE(__pTxDesc+32, 16, 8, __Value) /* 20130415 KaiYuan add for 8814AS */
+#endif
+#define SET_TX_DESC_TAIL_PAGE_L_8814A(__pTxDesc, __Value)(__pTxDesc, __Value)			SET_BITS_TO_LE_4BYTE(__pTxDesc+32, 24, 8, __Value)
+
+/* Dword 9 */
+#define SET_TX_DESC_PADDING_LENGTH_8814A(__pTxDesc, __Value)						SET_BITS_TO_LE_4BYTE(__pTxDesc+36, 0, 11, __Value)
+#define SET_TX_DESC_TXBF_PATH_8814A(__pTxDesc, __Value)								SET_BITS_TO_LE_4BYTE(__pTxDesc+36, 11, 1, __Value)
+#define SET_TX_DESC_SEQ_8814A(__pTxDesc, __Value)										SET_BITS_TO_LE_4BYTE(__pTxDesc+36, 12, 12, __Value)
+#define SET_TX_DESC_NEXT_HEAD_PAGE_H_8814A(__pTxDesc, __Value)(__pTxDesc, __Value)	SET_BITS_TO_LE_4BYTE(__pTxDesc+36, 24, 4, __Value)
+#define SET_TX_DESC_TAIL_PAGE_H_8814A(__pTxDesc, __Value)(__pTxDesc, __Value)			SET_BITS_TO_LE_4BYTE(__pTxDesc+36, 28, 4, __Value)
+
+
+
+#define SET_EARLYMODE_PKTNUM_8814A(__pAddr, __Value)					SET_BITS_TO_LE_4BYTE(__pAddr, 0, 4, __Value)
+#define SET_EARLYMODE_LEN0_8814A(__pAddr, __Value)					SET_BITS_TO_LE_4BYTE(__pAddr, 4, 15, __Value)
+#define SET_EARLYMODE_LEN1_1_8814A(__pAddr, __Value)					SET_BITS_TO_LE_4BYTE(__pAddr, 19, 13, __Value)
+#define SET_EARLYMODE_LEN1_2_8814A(__pAddr, __Value)					SET_BITS_TO_LE_4BYTE(__pAddr+4, 0, 2, __Value)
+#define SET_EARLYMODE_LEN2_8814A(__pAddr, __Value)					SET_BITS_TO_LE_4BYTE(__pAddr+4, 2, 15,  __Value)
+#define SET_EARLYMODE_LEN3_8814A(__pAddr, __Value)					SET_BITS_TO_LE_4BYTE(__pAddr+4, 17, 15, __Value)
+
+
+void rtl8814a_cal_txdesc_chksum(u8 *ptxdesc);
+void rtl8814a_fill_fake_txdesc(PADAPTER	padapter, u8 *pDesc, u32 BufferLen, u8 IsPsPoll, u8	IsBTQosNull, u8 bDataFrame);
+void rtl8814a_fill_txdesc_sectype(struct pkt_attrib *pattrib, u8 *ptxdesc);
+void rtl8814a_fill_txdesc_vcs(PADAPTER padapter, struct pkt_attrib *pattrib, u8 *ptxdesc);
+void rtl8814a_fill_txdesc_phy(PADAPTER padapter, struct pkt_attrib *pattrib, u8 *ptxdesc);
+#if defined(CONFIG_CONCURRENT_MODE)
+	void fill_txdesc_force_bmc_camid(struct pkt_attrib *pattrib, u8 *ptxdesc);
+#endif
+void fill_txdesc_bmc_tx_rate(struct pkt_attrib *pattrib, u8 *ptxdesc);
+
+#ifdef CONFIG_USB_HCI
+	s32 rtl8814au_init_xmit_priv(PADAPTER padapter);
+	void rtl8814au_free_xmit_priv(PADAPTER padapter);
+	s32 rtl8814au_hal_xmit(PADAPTER padapter, struct xmit_frame *pxmitframe);
+	s32 rtl8814au_mgnt_xmit(PADAPTER padapter, struct xmit_frame *pmgntframe);
+	s32	 rtl8814au_hal_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe);
+	s32 rtl8814au_xmit_buf_handler(PADAPTER padapter);
+	void rtl8814au_xmit_tasklet(void *priv);
+	s32 rtl8814au_xmitframe_complete(_adapter *padapter, struct xmit_priv *pxmitpriv, struct xmit_buf *pxmitbuf);
+#endif /* CONFIG_USB_HCI */
+
+#ifdef CONFIG_PCI_HCI
+	s32 rtl8814ae_init_xmit_priv(PADAPTER padapter);
+	void rtl8814ae_free_xmit_priv(PADAPTER padapter);
+	struct xmit_buf *rtl8814ae_dequeue_xmitbuf(struct rtw_tx_ring *ring);
+	void rtl8814ae_xmitframe_resume(_adapter *padapter);
+	s32 rtl8814ae_hal_xmit(PADAPTER padapter, struct xmit_frame *pxmitframe);
+	s32 rtl8814ae_mgnt_xmit(PADAPTER padapter, struct xmit_frame *pmgntframe);
+	s32	rtl8814ae_hal_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe);
+	void rtl8814ae_xmit_tasklet(void *priv);
+#ifdef CONFIG_XMIT_THREAD_MODE
+	s32 rtl8814ae_xmit_buf_handler(_adapter *padapter);
+#endif
+#endif
+
+void _dbg_dump_tx_info(_adapter	*padapter, int frame_tag, u8 *ptxdesc);
+u8
+SCMapping_8814(
+	IN	PADAPTER		Adapter,
+	IN	struct pkt_attrib	*pattrib
+);
+
+u8
+BWMapping_8814(
+	IN	PADAPTER		Adapter,
+	IN	struct pkt_attrib	*pattrib
+);
+
+
+#endif /* __RTL8814_XMIT_H__ */
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/include/rtl8821a_spec.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/rtl8821a_spec.h
--- linux-5.6.3/3rdparty/rtl8821ce/include/rtl8821a_spec.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/rtl8821a_spec.h	2020-04-10 16:35:06.850661655 +0300
@@ -0,0 +1,90 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2013 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#ifndef __RTL8821A_SPEC_H__
+#define __RTL8821A_SPEC_H__
+
+#include <drv_conf.h>
+/* This file should based on "hal_com_reg.h" */
+#include <hal_com_reg.h>
+/* Because 8812a and 8821a is the same serial,
+ * most of 8821a register definitions are the same as 8812a. */
+#include <rtl8812a_spec.h>
+
+
+/* ************************************************************
+ * 8821A Regsiter offset definition
+ * ************************************************************ */
+
+/* ************************************************************
+ * MAC register
+ * ************************************************************ */
+
+/* -----------------------------------------------------
+ *	0x0000h ~ 0x00FFh	System Configuration
+ * ----------------------------------------------------- */
+
+/* -----------------------------------------------------
+ *	0x0100h ~ 0x01FFh	MACTOP General Configuration
+ * ----------------------------------------------------- */
+#define REG_WOWLAN_WAKE_REASON          REG_MCUTST_WOWLAN
+
+/* -----------------------------------------------------
+ *	0x0200h ~ 0x027Fh	TXDMA Configuration
+ * ----------------------------------------------------- */
+
+/* -----------------------------------------------------
+ *	0x0280h ~ 0x02FFh	RXDMA Configuration
+ * ----------------------------------------------------- */
+
+/* -----------------------------------------------------
+ *	0x0300h ~ 0x03FFh	PCIe
+ * ----------------------------------------------------- */
+
+/* -----------------------------------------------------
+ *	0x0400h ~ 0x047Fh	Protocol Configuration
+ * ----------------------------------------------------- */
+
+/* -----------------------------------------------------
+ *	0x0500h ~ 0x05FFh	EDCA Configuration
+ * ----------------------------------------------------- */
+
+/* -----------------------------------------------------
+ *	0x0600h ~ 0x07FFh	WMAC Configuration
+ * ----------------------------------------------------- */
+
+
+/* ************************************************************
+ * SDIO Bus Specification
+ * ************************************************************ */
+
+/* -----------------------------------------------------
+ * SDIO CMD Address Mapping
+ * ----------------------------------------------------- */
+
+/* -----------------------------------------------------
+ * I/O bus domain (Host)
+ * ----------------------------------------------------- */
+
+/* -----------------------------------------------------
+ * SDIO register
+ * ----------------------------------------------------- */
+#define SDIO_REG_FREE_TXPG2		0x024
+#define SDIO_REG_HCPWM1_8821A	0x025
+
+/* ************************************************************
+ * Regsiter Bit and Content definition
+ * ************************************************************ */
+
+#endif /* __RTL8821A_SPEC_H__ */
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/include/rtl8821a_xmit.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/rtl8821a_xmit.h
--- linux-5.6.3/3rdparty/rtl8821ce/include/rtl8821a_xmit.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/rtl8821a_xmit.h	2020-04-10 16:35:06.850661655 +0300
@@ -0,0 +1,173 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2013 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#ifndef __RTL8821A_XMIT_H__
+#define __RTL8821A_XMIT_H__
+
+#include <drv_types.h>
+
+typedef struct txdescriptor_8821a {
+	/* Offset 0 */
+	u32 pktlen:16;
+	u32 offset:8;
+	u32 bmc:1;
+	u32 htc:1;
+	u32 rsvd0026:1;
+	u32 rsvd0027:1;
+	u32 linip:1;
+	u32 noacm:1;
+	u32 gf:1;
+	u32 rsvd0031:1;
+
+	/* Offset 4 */
+	u32 macid:7;
+	u32 rsvd0407:1;
+	u32 qsel:5;
+	u32 rdg_nav_ext:1;
+	u32 lsig_txop_en:1;
+	u32 pifs:1;
+	u32 rate_id:5;
+	u32 en_desc_id:1;
+	u32 sectype:2;
+	u32 pkt_offset:5; /* unit: 8 bytes */
+	u32 moredata:1;
+	u32 txop_ps_cap:1;
+	u32 txop_ps_mode:1;
+
+	/* Offset 8 */
+	u32 p_aid:9;
+	u32 rsvd0809:1;
+	u32 cca_rts:2;
+	u32 agg_en:1;
+	u32 rdg_en:1;
+	u32 null_0:1;
+	u32 null_1:1;
+	u32 bk:1;
+	u32 morefrag:1;
+	u32 raw:1;
+	u32 spe_rpt:1;
+	u32 ampdu_density:3;
+	u32 bt_null:1;
+	u32 g_id:6;
+	u32 rsvd0830:2;
+
+	/* Offset 12 */
+	u32 wheader_len:4;
+	u32 chk_en:1;
+	u32 early_rate:1;
+	u32 hw_ssn_sel:2;
+	u32 userate:1;
+	u32 disrtsfb:1;
+	u32 disdatafb:1;
+	u32 cts2self:1;
+	u32 rtsen:1;
+	u32 hw_rts_en:1;
+	u32 port_id:1;
+	u32 navusehdr:1;
+	u32 use_max_len:1;
+	u32 max_agg_num:5;
+	u32 ndpa:2;
+	u32 ampdu_max_time:8;
+
+	/* Offset 16 */
+	u32 datarate:7;
+	u32 try_rate:1;
+	u32 data_ratefb_lmt:5;
+	u32 rts_ratefb_lmt:4;
+	u32 rty_lmt_en:1;
+	u32 data_rt_lmt:6;
+	u32 rtsrate:5;
+	u32 pcts_en:1;
+	u32 pcts_mask_idx:2;
+
+	/* Offset 20 */
+	u32 data_sc:4;
+	u32 data_short:1;
+	u32 data_bw:2;
+	u32 data_ldpc:1;
+	u32 data_stbc:2;
+	u32 vcs_stbc:2;
+	u32 rts_short:1;
+	u32 rts_sc:4;
+	u32 rsvd2016:7;
+	u32 tx_ant:4;
+	u32 txpwr_offset:3;
+	u32 rsvd2031:1;
+
+	/* Offset 24 */
+	u32 sw_define:12;
+	u32 mbssid:4;
+	u32 antsel_A:3;
+	u32 antsel_B:3;
+	u32 antsel_C:3;
+	u32 antsel_D:3;
+	u32 rsvd2428:4;
+
+	/* Offset 28 */
+	u32 checksum:16;
+	u32 rsvd2816:8;
+	u32 usb_txagg_num:8;
+
+	/* Offset 32 */
+	u32 rts_rc:6;
+	u32 bar_rty_th:2;
+	u32 data_rc:6;
+	u32 rsvd3214:1;
+	u32 en_hwseq:1;
+	u32 nextneadpage:8;
+	u32 tailpage:8;
+
+	/* Offset 36 */
+	u32 padding_len:11;
+	u32 txbf_path:1;
+	u32 seq:12;
+	u32 final_data_rate:8;
+} TXDESC_8821A, *PTXDESC_8821A;
+
+#ifdef CONFIG_SDIO_HCI
+s32 InitXmitPriv8821AS(PADAPTER padapter);
+void FreeXmitPriv8821AS(PADAPTER padapter);
+s32 XmitBufHandler8821AS(PADAPTER padapter);
+s32 MgntXmit8821AS(PADAPTER padapter, struct xmit_frame *pmgntframe);
+s32	HalXmitNoLock8821AS(PADAPTER padapter, struct xmit_frame *pxmitframe);
+s32 HalXmit8821AS(PADAPTER padapter, struct xmit_frame *pxmitframe);
+#ifndef CONFIG_SDIO_TX_TASKLET
+thread_return XmitThread8821AS(thread_context context);
+#endif /* !CONFIG_SDIO_TX_TASKLET */
+#endif /* CONFIG_SDIO_HCI */
+
+#if 0
+#ifdef CONFIG_USB_HCI
+s32 rtl8821au_init_xmit_priv(PADAPTER padapter);
+void rtl8821au_free_xmit_priv(PADAPTER padapter);
+s32 rtl8821au_hal_xmit(PADAPTER padapter, struct xmit_frame *pxmitframe);
+s32 rtl8821au_mgnt_xmit(PADAPTER padapter, struct xmit_frame *pmgntframe);
+s32 rtl8821au_hal_xmitframe_enqueue(PADAPTER padapter, struct xmit_frame *pxmitframe);
+s32 rtl8821au_xmit_buf_handler(PADAPTER padapter);
+void rtl8821au_xmit_tasklet(void *priv);
+s32 rtl8821au_xmitframe_complete(PADAPTER padapter, struct xmit_priv *pxmitpriv, struct xmit_buf *pxmitbuf);
+#endif /* CONFIG_USB_HCI */
+
+#ifdef CONFIG_PCI_HCI
+s32 rtl8821e_init_xmit_priv(PADAPTER padapter);
+void rtl8821e_free_xmit_priv(PADAPTER padapter);
+struct xmit_buf *rtl8821e_dequeue_xmitbuf(struct rtw_tx_ring *ring);
+void rtl8821e_xmitframe_resume(PADAPTER padapter);
+s32 rtl8821e_hal_xmit(PADAPTER padapter, struct xmit_frame *pxmitframe);
+s32 rtl8821e_mgnt_xmit(PADAPTER padapter, struct xmit_frame *pmgntframe);
+void rtl8821e_xmit_tasklet(void *priv);
+#endif /* CONFIG_PCI_HCI */
+#endif
+
+#endif /* __RTL8821_XMIT_H__ */
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/include/rtl8821c_dm.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/rtl8821c_dm.h
--- linux-5.6.3/3rdparty/rtl8821ce/include/rtl8821c_dm.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/rtl8821c_dm.h	2020-04-10 16:35:06.850661655 +0300
@@ -0,0 +1,23 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2016 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#ifndef __RTL8812C_DM_H__
+#define __RTL8812C_DM_H__
+
+void rtl8821c_phy_init_dm_priv(PADAPTER);
+void rtl8821c_phy_deinit_dm_priv(PADAPTER);
+void rtl8821c_phy_init_haldm(PADAPTER);
+void rtl8821c_phy_haldm_watchdog(PADAPTER);
+
+#endif
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/include/rtl8821ce_hal.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/rtl8821ce_hal.h
--- linux-5.6.3/3rdparty/rtl8821ce/include/rtl8821ce_hal.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/rtl8821ce_hal.h	2020-04-10 16:35:06.850661655 +0300
@@ -0,0 +1,23 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2016 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#ifndef _RTL8821CE_HAL_H_
+#define _RTL8821CE_HAL_H_
+
+#include <drv_types.h>		/* PADAPTER */
+
+/* rtl8821ce_ops.c */
+void rtl8821ce_set_hal_ops(PADAPTER);
+
+#endif /* _RTL8821CE_HAL_H_ */
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/include/rtl8821c_hal.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/rtl8821c_hal.h
--- linux-5.6.3/3rdparty/rtl8821ce/include/rtl8821c_hal.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/rtl8821c_hal.h	2020-04-10 16:35:06.850661655 +0300
@@ -0,0 +1,84 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2016 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#ifndef _RTL8821C_HAL_H_
+#define _RTL8821C_HAL_H_
+
+#include <osdep_service.h>		/* BIT(x) */
+#include "../hal/halmac/halmac_api.h"	/* MAC REG definition */
+#include "hal_data.h"
+#include "rtl8821c_spec.h"
+#include "../hal/rtl8821c/hal8821c_fw.h"
+
+#ifdef CONFIG_USB_HCI
+#include <rtl8821cu_hal.h>
+#endif
+#ifdef CONFIG_SDIO_HCI
+#include <rtl8821cs_hal.h>
+#endif
+#ifdef CONFIG_PCI_HCI
+#include <rtl8821ce_hal.h>
+#endif
+
+#ifdef CONFIG_SUPPORT_TRX_SHARED
+#define FIFO_BLOCK_SIZE		32768 /*@Block size = 32K*/
+#define RX_FIFO_EXPANDING	(1 * FIFO_BLOCK_SIZE)
+#else
+#define RX_FIFO_EXPANDING	0
+#endif
+
+
+#if defined(CONFIG_USB_HCI)
+
+	#ifndef MAX_RECVBUF_SZ
+		#ifndef CONFIG_MINIMAL_MEMORY_USAGE
+			/* 8821C - RX FIFO :16K ,for RX agg DMA mode = 16K, Rx agg USB mode could large than 16k*/
+			/* #define MAX_RECVBUF_SZ		(16384 + RX_FIFO_EXPANDING)*/
+			/* For Max throughput issue , need to use USB AGG mode to replace DMA AGG mode*/
+			#define MAX_RECVBUF_SZ (32768)
+
+			/*#define MAX_RECVBUF_SZ_8821C (24576)*/ /* 24k*/
+			/*#define MAX_RECVBUF_SZ_8821C (20480)*/ /*20K*/
+			/*#define MAX_RECVBUF_SZ_8821C (10240) */ /*10K*/
+			/*#define MAX_RECVBUF_SZ_8821C (15360)*/ /*15k < 16k*/
+			/*#define MAX_RECVBUF_SZ_8821C (8192+1024)*/ /* 8K+1k*/
+		#else
+			#define MAX_RECVBUF_SZ (4096 + RX_FIFO_EXPANDING) /* about 4K */
+		#endif
+	#endif/* !MAX_RECVBUF_SZ*/
+
+#elif defined(CONFIG_PCI_HCI)
+	/*#ifndef CONFIG_MINIMAL_MEMORY_USAGE
+	#define MAX_RECVBUF_SZ (9100)
+	#else*/
+	#define MAX_RECVBUF_SZ (4096 + RX_FIFO_EXPANDING) /* about 4K */
+	/*#endif*/
+
+#elif defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
+	#define MAX_RECVBUF_SZ	(16384 + RX_FIFO_EXPANDING)
+#endif
+
+void init_hal_spec_rtl8821c(PADAPTER);
+/* MP Functions */
+#ifdef CONFIG_MP_INCLUDED
+void rtl8821c_prepare_mp_txdesc(PADAPTER, struct mp_priv *);	/* rtw_mp.c */
+void rtl8821c_mp_config_rfpath(PADAPTER);			/* hal_mp.c */
+#endif
+void rtl8821c_dl_rsvd_page(PADAPTER adapter, u8 mstatus);
+
+#ifdef CONFIG_PCI_HCI
+u16 get_txbd_rw_reg(u16 q_idx);
+#endif
+
+#endif /* _RTL8821C_HAL_H_ */
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/include/rtl8821cs_hal.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/rtl8821cs_hal.h
--- linux-5.6.3/3rdparty/rtl8821ce/include/rtl8821cs_hal.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/rtl8821cs_hal.h	2020-04-10 16:35:06.850661655 +0300
@@ -0,0 +1,23 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2016 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#ifndef _RTL8821CS_HAL_H_
+#define _RTL8821CS_HAL_H_
+
+#include <drv_types.h>		/* PADAPTER */
+
+/* rtl8821cs_ops.c */
+u8 rtl8821cs_set_hal_ops(PADAPTER);
+
+#endif /* _RTL8821CS_HAL_H_ */
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/include/rtl8821c_spec.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/rtl8821c_spec.h
--- linux-5.6.3/3rdparty/rtl8821ce/include/rtl8821c_spec.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/rtl8821c_spec.h	2020-04-10 16:35:06.850661655 +0300
@@ -0,0 +1,202 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2016 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#ifndef __RTL8821C_SPEC_H__
+#define __RTL8821C_SPEC_H__
+
+#define EFUSE_MAP_SIZE		HALMAC_EFUSE_SIZE_8821C
+
+/*
+ * MAC Register definition
+ */
+#define REG_AFE_XTAL_CTRL			REG_AFE_CTRL1_8821C	/* hal_com.c & phydm */
+#define REG_AFE_PLL_CTRL			REG_AFE_CTRL2_8821C	/* hal_com.c & phydm */
+#define REG_MAC_PHY_CTRL			REG_AFE_CTRL3_8821C	/* phydm only */
+#define REG_LEDCFG0					REG_LED_CFG_8821C	/* rtw_mp.c */
+#define MSR							(REG_CR_8821C + 2)	/* rtw_mp.c */
+#define MSR1						REG_CR_EXT_8821C	/* rtw_mp.c & hal_com.c */
+#define REG_C2HEVT_MSG_NORMAL		0x1A0			/* hal_com.c */
+#define REG_C2HEVT_CLEAR			0x1AF			/* hal_com.c */
+#define REG_BCN_CTRL_1				REG_BCN_CTRL_CLINT0_8821C/* hal_com.c */
+
+#define REG_WOWLAN_WAKE_REASON	0x01C7
+#define REG_GPIO_PIN_CTRL_2			REG_GPIO_EXT_CTRL_8821C
+
+/* RXERR_RPT, for rtw_mp.c */
+#define RXERR_TYPE_OFDM_PPDU		0
+#define RXERR_TYPE_OFDM_FALSE_ALARM	2
+#define RXERR_TYPE_OFDM_MPDU_OK		0
+#define RXERR_TYPE_OFDM_MPDU_FAIL	1
+#define RXERR_TYPE_CCK_PPDU		3
+#define RXERR_TYPE_CCK_FALSE_ALARM	5
+#define RXERR_TYPE_CCK_MPDU_OK		3
+#define RXERR_TYPE_CCK_MPDU_FAIL	4
+#define RXERR_TYPE_HT_PPDU		8
+#define RXERR_TYPE_HT_FALSE_ALARM	9
+#define RXERR_TYPE_HT_MPDU_TOTAL	6
+#define RXERR_TYPE_HT_MPDU_OK		6
+#define RXERR_TYPE_HT_MPDU_FAIL		7
+#define RXERR_TYPE_RX_FULL_DROP		10
+
+#define RXERR_COUNTER_MASK		BIT_MASK_RPT_COUNTER_8821C
+#define RXERR_RPT_RST			BIT_RXERR_RPT_RST_8821C
+#define _RXERR_RPT_SEL(type)		(BIT_RXERR_RPT_SEL_V1_3_0_8821C(type) \
+		| ((type & 0x10) ? BIT_RXERR_RPT_SEL_V1_4_8821C : 0))
+
+/*
+ * BB Register definition
+ */
+#define rPMAC_Reset				0x100	/* hal_mp.c */
+
+#define rFPGA0_RFMOD				0x800
+#define rFPGA0_TxInfo				0x804
+#define rOFDMCCKEN_Jaguar		0x808	/* hal_mp.c */
+#define rFPGA0_TxGainStage		0x80C	/* phydm only */
+#define rFPGA0_XA_HSSIParameter1	0x820	/* hal_mp.c */
+#define rFPGA0_XA_HSSIParameter2	0x824	/* hal_mp.c */
+#define rFPGA0_XB_HSSIParameter1	0x828	/* hal_mp.c */
+#define rFPGA0_XB_HSSIParameter2	0x82C	/* hal_mp.c */
+#define rTxAGC_B_Rate18_06		0x830
+#define rTxAGC_B_Rate54_24		0x834
+#define rTxAGC_B_CCK1_55_Mcs32	0x838
+#define rCCAonSec_Jaguar			0x838	/* hal_mp.c */
+#define rTxAGC_B_Mcs03_Mcs00		0x83C
+#define rTxAGC_B_Mcs07_Mcs04		0x848
+#define rTxAGC_B_Mcs11_Mcs08		0x84C
+#define rFPGA0_XA_RFInterfaceOE		0x860
+#define rFPGA0_XB_RFInterfaceOE		0x864
+#define rTxAGC_B_Mcs15_Mcs12		0x868
+#define rTxAGC_B_CCK11_A_CCK2_11	0x86C
+#define rFPGA0_XAB_RFInterfaceSW		0x870
+#define rFPGA0_XAB_RFParameter		0x878
+#define rFPGA0_AnalogParameter4		0x88C	/* hal_mp.c & phydm */
+#define rFPGA0_XB_LSSIReadBack		0x8A4	/* phydm */
+#define rHSSIRead_Jaguar				0x8B0	/* RF read addr (rtl8821c_phy.c) */
+
+#define	rC_TxScale_Jaguar2			0x181C  /* Pah_C TX scaling factor (hal_mp.c) */
+#define	rC_IGI_Jaguar2				0x1850	/* Initial Gain for path-C (hal_mp.c) */
+
+#define rFPGA1_TxInfo					0x90C	/* hal_mp.c */
+#define rSingleTone_ContTx_Jaguar		0x914	/* hal_mp.c */
+
+#define rCCK0_System					0xA00
+#define rCCK0_AFESetting				0xA04
+
+#define rCCK0_DSPParameter2			0xA1C
+#define rCCK0_TxFilter1				0xA20
+#define rCCK0_TxFilter2				0xA24
+#define rCCK0_DebugPort				0xA28
+#define rCCK0_FalseAlarmReport		0xA2C
+
+#define	rD_TxScale_Jaguar2			0x1A1C  /* Path_D TX scaling factor (hal_mp.c) */
+#define	rD_IGI_Jaguar2				0x1A50	/* Initial Gain for path-D (hal_mp.c) */
+
+#define rOFDM0_TRxPathEnable			0xC04
+#define rOFDM0_TRMuxPar				0xC08
+#define rA_TxScale_Jaguar				0xC1C	/* Pah_A TX scaling factor (hal_mp.c) */
+#define rOFDM0_RxDetector1			0xC30	/* rtw_mp.c */
+#define rOFDM0_ECCAThreshold			0xC4C	/* phydm only */
+#define rOFDM0_XAAGCCore1			0xC50	/* phydm only */
+#define rA_IGI_Jaguar					0xC50	/* Initial Gain for path-A (hal_mp.c) */
+#define rOFDM0_XBAGCCore1			0xC58	/* phydm only */
+#define rOFDM0_XATxIQImbalance		0xC80	/* phydm only */
+#define rA_LSSIWrite_Jaguar			0xC90	/* RF write addr, LSSI Parameter (rtl8821c_phy.c) */
+/* RFE */
+#define rA_RFE_Pinmux_Jaguar	0xCB0	/* hal_mp.c */
+#define	rB_RFE_Pinmux_Jaguar	0xEB0	/* Path_B RFE control pinmux */
+#define	rA_RFE_Inv_Jaguar		0xCB4	/* Path_A RFE cotrol */  
+#define	rB_RFE_Inv_Jaguar		0xEB4	/* Path_B RFE control */
+#define	rA_RFE_Jaguar			0xCB8 	/* Path_A RFE cotrol */  
+#define	rB_RFE_Jaguar			0xEB8	/* Path_B RFE control */
+#define	rA_RFE_Inverse_Jaguar	0xCBC	/* Path_A RFE control inverse */
+#define	rB_RFE_Inverse_Jaguar	0xEBC	/* Path_B RFE control inverse */
+#define	r_ANTSEL_SW_Jaguar		0x900	/* ANTSEL SW Control */
+#define	bMask_RFEInv_Jaguar	0x3FF00000
+#define	bMask_AntselPathFollow_Jaguar 0x00030000   
+
+#define rOFDM1_LSTF					0xD00
+#define rOFDM1_TRxPathEnable			0xD04	/* hal_mp.c */
+#define rA_PIRead_Jaguar				0xD04	/* RF readback with PI (rtl8821c_phy.c) */
+#define rA_SIRead_Jaguar				0xD08	/* RF readback with SI (rtl8821c_phy.c) */
+#define rB_PIRead_Jaguar				0xD44	/* RF readback with PI (rtl8821c_phy.c) */
+#define rB_SIRead_Jaguar				0xD48	/* RF readback with SI (rtl8821c_phy.c) */
+
+#define rTxAGC_A_Rate18_06			0xE00
+#define rTxAGC_A_Rate54_24			0xE04
+#define rTxAGC_A_CCK1_Mcs32			0xE08
+#define rTxAGC_A_Mcs03_Mcs00		0xE10
+#define rTxAGC_A_Mcs07_Mcs04		0xE14
+#define rTxAGC_A_Mcs11_Mcs08		0xE18
+#define rTxAGC_A_Mcs15_Mcs12		0xE1C
+#define rB_TxScale_Jaguar				0xE1C	/* Path_B TX scaling factor (hal_mp.c) */
+#define rB_IGI_Jaguar					0xE50	/* Initial Gain for path-B (hal_mp.c) */
+#define rB_LSSIWrite_Jaguar			0xE90	/* RF write addr, LSSI Parameter (rtl8821c_phy.c) */
+
+/* Page1(0x100) */
+#define bBBResetB					0x100
+
+/* Page8(0x800) */
+#define bCCKEn						0x1000000
+#define bOFDMEn						0x2000000
+/* Reg 0x80C rFPGA0_TxGainStage */
+#define bXBTxAGC						0xF00
+#define bXCTxAGC						0xF000
+#define bXDTxAGC						0xF0000
+
+/* PageA(0xA00) */
+#define bCCKBBMode					0x3
+
+#define bCCKScramble					0x8
+#define bCCKTxRate					0x3000
+
+/* General */
+#define bMaskByte0		0xFF		/* mp, rtw_odm.c & phydm */
+#define bMaskByte1		0xFF00		/* hal_mp.c & phydm */
+#define bMaskByte2		0xFF0000	/* hal_mp.c & phydm */
+#define bMaskByte3		0xFF000000	/* hal_mp.c & phydm */
+#define bMaskHWord		0xFFFF0000	/* hal_com.c, rtw_mp.c */
+#define bMaskLWord		0x0000FFFF	/* mp, hal_com.c & phydm */
+#define bMaskDWord		0xFFFFFFFF	/* mp, hal, rtw_odm.c & phydm */
+
+#define bEnable			0x1		/* hal_mp.c, rtw_mp.c */
+#define bDisable			0x0		/* rtw_mp.c */
+
+#define MAX_STALL_TIME		50		/* unit: us, hal_com_phycfg.c */
+
+#define Rx_Smooth_Factor		20		/* phydm only */
+
+/*
+ * RF Register definition
+ */
+#define RF_AC			0x00
+#define RF_AC_Jaguar		0x00	/* hal_mp.c */
+#define RF_CHNLBW		0x18	/* rtl8821c_phy.c */
+#define RF_0x52			0x52
+
+struct hw_port_reg {
+	u32 net_type;	/*reg_offset*/
+	u8 net_type_shift;
+	u32 macaddr;		/*reg_offset*/
+	u32 bssid;		/*reg_offset*/
+	u32 bcn_ctl;			/*reg_offset*/
+	u32 tsf_rst;			/*reg_offset*/
+	u8 tsf_rst_bit;
+	u32 bcn_space;		/*reg_offset*/
+	u8 bcn_space_shift;
+	u16 bcn_space_mask;
+	u32	ps_aid;			/*reg_offset*/
+	u32	ta;				/*reg_offset*/
+};
+
+#endif /* __RTL8192E_SPEC_H__ */
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/include/rtl8821cu_hal.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/rtl8821cu_hal.h
--- linux-5.6.3/3rdparty/rtl8821ce/include/rtl8821cu_hal.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/rtl8821cu_hal.h	2020-04-10 16:35:06.850661655 +0300
@@ -0,0 +1,24 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2016 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#ifndef _RTL8821CU_HAL_H_
+#define _RTL8821CU_HAL_H_
+
+#include <drv_types.h>		/* PADAPTER */
+
+/* rtl8821cu_ops.c */
+u8 rtl8821cu_set_hal_ops(PADAPTER);
+void rtl8821cu_set_hw_type(struct dvobj_priv *pdvobj);
+
+#endif /* _RTL8821CU_HAL_H_ */
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/include/rtl8822be_hal.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/rtl8822be_hal.h
--- linux-5.6.3/3rdparty/rtl8821ce/include/rtl8822be_hal.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/rtl8822be_hal.h	2020-04-10 16:35:06.850661655 +0300
@@ -0,0 +1,27 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2015 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#ifndef _RTL8822BE_HAL_H_
+#define _RTL8822BE_HAL_H_
+
+#include <drv_types.h>		/* PADAPTER */
+
+#define RT_BCN_INT_MASKS	(BIT20 | BIT25 | BIT26 | BIT16)
+
+/* rtl8822be_ops.c */
+void UpdateInterruptMask8822BE(PADAPTER, u32 AddMSR, u32 AddMSR1, u32 RemoveMSR, u32 RemoveMSR1);
+u16 get_txbd_rw_reg(u16 q_idx);
+
+
+#endif /* _RTL8822BE_HAL_H_ */
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/include/rtl8822b_hal.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/rtl8822b_hal.h
--- linux-5.6.3/3rdparty/rtl8821ce/include/rtl8822b_hal.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/rtl8822b_hal.h	2020-04-10 16:35:06.850661655 +0300
@@ -0,0 +1,230 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2015 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#ifndef _RTL8822B_HAL_H_
+#define _RTL8822B_HAL_H_
+
+#include <osdep_service.h>		/* BIT(x) */
+#include <drv_types.h>			/* PADAPTER */
+#include "../hal/halmac/halmac_api.h"	/* MAC REG definition */
+
+
+#ifdef CONFIG_SUPPORT_TRX_SHARED
+#define MAX_RECVBUF_SZ		46080	/* 45KB, TX: (256-64)KB */
+#else /* !CONFIG_SUPPORT_TRX_SHARED */
+#define MAX_RECVBUF_SZ		24576	/* 24KB, TX: 256KB */
+#endif /* !CONFIG_SUPPORT_TRX_SHARED */
+
+/*
+ * MAC Register definition
+ */
+#define REG_AFE_XTAL_CTRL	REG_AFE_CTRL1_8822B	/* hal_com.c & phydm */
+#define REG_AFE_PLL_CTRL	REG_AFE_CTRL2_8822B	/* hal_com.c & phydm */
+#define REG_MAC_PHY_CTRL	REG_AFE_CTRL3_8822B	/* phydm only */
+#define REG_LEDCFG0		REG_LED_CFG_8822B	/* rtw_mp.c */
+#define MSR			(REG_CR_8822B + 2)	/* rtw_mp.c & hal_com.c */
+#define MSR1			REG_CR_EXT_8822B	/* rtw_mp.c & hal_com.c */
+#define REG_C2HEVT_MSG_NORMAL	0x1A0			/* hal_com.c */
+#define REG_C2HEVT_CLEAR	0x1AF			/* hal_com.c */
+#define REG_BCN_CTRL_1		REG_BCN_CTRL_CLINT0_8822B	/* hal_com.c */
+
+#define REG_WOWLAN_WAKE_REASON	0x01C7 /* hal_com.c */
+#define REG_GPIO_PIN_CTRL_2		REG_GPIO_EXT_CTRL_8822B		/* hal_com.c */
+
+/* RXERR_RPT, for rtw_mp.c */
+#define RXERR_TYPE_OFDM_PPDU		0
+#define RXERR_TYPE_OFDM_FALSE_ALARM	2
+#define RXERR_TYPE_OFDM_MPDU_OK		0
+#define RXERR_TYPE_OFDM_MPDU_FAIL	1
+#define RXERR_TYPE_CCK_PPDU		3
+#define RXERR_TYPE_CCK_FALSE_ALARM	5
+#define RXERR_TYPE_CCK_MPDU_OK		3
+#define RXERR_TYPE_CCK_MPDU_FAIL	4
+#define RXERR_TYPE_HT_PPDU		8
+#define RXERR_TYPE_HT_FALSE_ALARM	9
+#define RXERR_TYPE_HT_MPDU_TOTAL	6
+#define RXERR_TYPE_HT_MPDU_OK		6
+#define RXERR_TYPE_HT_MPDU_FAIL		7
+#define RXERR_TYPE_RX_FULL_DROP		10
+
+#define RXERR_COUNTER_MASK		BIT_MASK_RPT_COUNTER_8822B
+#define RXERR_RPT_RST			BIT_RXERR_RPT_RST_8822B
+#define _RXERR_RPT_SEL(type)		(BIT_RXERR_RPT_SEL_V1_3_0_8822B(type) \
+					| ((type & 0x10) ? BIT_RXERR_RPT_SEL_V1_4_8822B : 0))
+
+/*
+ * BB Register definition
+ */
+#define rPMAC_Reset			0x100	/* hal_mp.c */
+
+#define	rFPGA0_RFMOD			0x800
+#define rFPGA0_TxInfo			0x804
+#define rOFDMCCKEN_Jaguar		0x808	/* hal_mp.c */
+#define rFPGA0_TxGainStage		0x80C	/* phydm only */
+#define rFPGA0_XA_HSSIParameter1	0x820	/* hal_mp.c */
+#define rFPGA0_XA_HSSIParameter2	0x824	/* hal_mp.c */
+#define rFPGA0_XB_HSSIParameter1	0x828	/* hal_mp.c */
+#define rFPGA0_XB_HSSIParameter2	0x82C	/* hal_mp.c */
+#define rTxAGC_B_Rate18_06		0x830
+#define rTxAGC_B_Rate54_24		0x834
+#define rTxAGC_B_CCK1_55_Mcs32		0x838
+#define rCCAonSec_Jaguar		0x838	/* hal_mp.c */
+#define rTxAGC_B_Mcs03_Mcs00		0x83C
+#define rTxAGC_B_Mcs07_Mcs04		0x848
+#define rTxAGC_B_Mcs11_Mcs08		0x84C
+#define rFPGA0_XA_RFInterfaceOE		0x860
+#define rFPGA0_XB_RFInterfaceOE		0x864
+#define rTxAGC_B_Mcs15_Mcs12		0x868
+#define rTxAGC_B_CCK11_A_CCK2_11	0x86C
+#define rFPGA0_XAB_RFInterfaceSW	0x870
+#define rFPGA0_XAB_RFParameter		0x878
+#define rFPGA0_AnalogParameter4		0x88C	/* hal_mp.c & phydm */
+#define rFPGA0_XB_LSSIReadBack		0x8A4	/* phydm */
+#define rHSSIRead_Jaguar		0x8B0	/* RF read addr (rtl8822b_phy.c) */
+
+#define	rC_TxScale_Jaguar2		0x181C  /* Pah_C TX scaling factor (hal_mp.c) */
+#define	rC_IGI_Jaguar2			0x1850	/* Initial Gain for path-C (hal_mp.c) */
+
+#define rFPGA1_TxInfo			0x90C	/* hal_mp.c */
+#define rSingleTone_ContTx_Jaguar	0x914	/* hal_mp.c */
+/* TX BeamForming */
+#define REG_BB_TX_PATH_SEL_1_8822B	0x93C	/* rtl8822b_phy.c */
+#define REG_BB_TX_PATH_SEL_2_8822B	0x940	/* rtl8822b_phy.c */
+
+/* TX BeamForming */
+#define REG_BB_TXBF_ANT_SET_BF1_8822B	0x19AC	/* rtl8822b_phy.c */
+#define REG_BB_TXBF_ANT_SET_BF0_8822B	0x19B4	/* rtl8822b_phy.c */
+
+#define rCCK0_System			0xA00
+#define rCCK0_AFESetting		0xA04
+
+#define rCCK0_DSPParameter2		0xA1C
+#define rCCK0_TxFilter1			0xA20
+#define rCCK0_TxFilter2			0xA24
+#define rCCK0_DebugPort			0xA28
+#define rCCK0_FalseAlarmReport		0xA2C
+
+#define	rD_TxScale_Jaguar2		0x1A1C  /* Path_D TX scaling factor (hal_mp.c) */
+#define	rD_IGI_Jaguar2			0x1A50	/* Initial Gain for path-D (hal_mp.c) */
+
+#define rOFDM0_TRxPathEnable		0xC04
+#define rOFDM0_TRMuxPar			0xC08
+#define rA_TxScale_Jaguar		0xC1C	/* Pah_A TX scaling factor (hal_mp.c) */
+#define rOFDM0_RxDetector1		0xC30	/* rtw_mp.c */
+#define rOFDM0_ECCAThreshold		0xC4C	/* phydm only */
+#define rOFDM0_XAAGCCore1		0xC50	/* phydm only */
+#define rA_IGI_Jaguar			0xC50	/* Initial Gain for path-A (hal_mp.c) */
+#define rOFDM0_XBAGCCore1		0xC58	/* phydm only */
+#define rOFDM0_XATxIQImbalance		0xC80	/* phydm only */
+#define rA_LSSIWrite_Jaguar		0xC90	/* RF write addr, LSSI Parameter (rtl8822b_phy.c) */
+
+#define rOFDM1_LSTF			0xD00
+#define rOFDM1_TRxPathEnable		0xD04	/* hal_mp.c */
+#define rA_PIRead_Jaguar		0xD04	/* RF readback with PI (rtl8822b_phy.c) */
+#define rA_SIRead_Jaguar		0xD08	/* RF readback with SI (rtl8822b_phy.c) */
+#define rB_PIRead_Jaguar		0xD44	/* RF readback with PI (rtl8822b_phy.c) */
+#define rB_SIRead_Jaguar		0xD48	/* RF readback with SI (rtl8822b_phy.c) */
+
+#define rTxAGC_A_Rate18_06		0xE00
+#define rTxAGC_A_Rate54_24		0xE04
+#define rTxAGC_A_CCK1_Mcs32		0xE08
+#define rTxAGC_A_Mcs03_Mcs00		0xE10
+#define rTxAGC_A_Mcs07_Mcs04		0xE14
+#define rTxAGC_A_Mcs11_Mcs08		0xE18
+#define rTxAGC_A_Mcs15_Mcs12		0xE1C
+#define rB_TxScale_Jaguar		0xE1C	/* Path_B TX scaling factor (hal_mp.c) */
+#define rB_IGI_Jaguar			0xE50	/* Initial Gain for path-B (hal_mp.c) */
+#define rB_LSSIWrite_Jaguar		0xE90	/* RF write addr, LSSI Parameter (rtl8822b_phy.c) */
+/* RFE */
+#define rA_RFE_Pinmux_Jaguar	0xCB0	/* hal_mp.c */
+#define	rB_RFE_Pinmux_Jaguar	0xEB0	/* Path_B RFE control pinmux */
+#define	rA_RFE_Inv_Jaguar		0xCB4	/* Path_A RFE cotrol */  
+#define	rB_RFE_Inv_Jaguar		0xEB4	/* Path_B RFE control */
+#define	rA_RFE_Jaguar			0xCB8 	/* Path_A RFE cotrol */  
+#define	rB_RFE_Jaguar			0xEB8	/* Path_B RFE control */
+#define	rA_RFE_Inverse_Jaguar	0xCBC	/* Path_A RFE control inverse */
+#define	rB_RFE_Inverse_Jaguar	0xEBC	/* Path_B RFE control inverse */
+#define	r_ANTSEL_SW_Jaguar		0x900	/* ANTSEL SW Control */
+#define	bMask_RFEInv_Jaguar	0x3FF00000
+#define	bMask_AntselPathFollow_Jaguar 0x00030000
+
+#define		rC_RFE_Pinmux_Jaguar	0x18B4	/* Path_C RFE cotrol pinmux*/
+#define		rD_RFE_Pinmux_Jaguar	0x1AB4	/* Path_D RFE cotrol pinmux*/
+#define		rA_RFE_Sel_Jaguar2		0x1990
+
+/* Page1(0x100) */
+#define bBBResetB			0x100
+
+/* Page8(0x800) */
+#define bCCKEn				0x1000000
+#define bOFDMEn				0x2000000
+/* Reg 0x80C rFPGA0_TxGainStage */
+#define bXBTxAGC			0xF00
+#define bXCTxAGC			0xF000
+#define bXDTxAGC			0xF0000
+
+/* PageA(0xA00) */
+#define bCCKBBMode			0x3
+
+#define bCCKScramble			0x8
+#define bCCKTxRate			0x3000
+
+/* General */
+#define bMaskByte0		0xFF		/* mp, rtw_odm.c & phydm */
+#define bMaskByte1		0xFF00		/* hal_mp.c & phydm */
+#define bMaskByte2		0xFF0000	/* hal_mp.c & phydm */
+#define bMaskByte3		0xFF000000	/* hal_mp.c & phydm */
+#define bMaskHWord		0xFFFF0000	/* hal_com.c, rtw_mp.c */
+#define bMaskLWord		0x0000FFFF	/* mp, hal_com.c & phydm */
+#define bMaskDWord		0xFFFFFFFF	/* mp, hal, rtw_odm.c & phydm */
+
+#define bEnable			0x1		/* hal_mp.c, rtw_mp.c */
+#define bDisable		0x0		/* rtw_mp.c */
+
+#define MAX_STALL_TIME		50		/* unit: us, hal_com_phycfg.c */
+
+#define Rx_Smooth_Factor	20		/* phydm only */
+
+/*
+ * RF Register definition
+ */
+#define RF_AC			0x00
+#define RF_AC_Jaguar		0x00	/* hal_mp.c */
+#define RF_CHNLBW		0x18	/* rtl8822b_phy.c */
+#define RF_ModeTableAddr	0x30	/* rtl8822b_phy.c */
+#define RF_ModeTableData0	0x31	/* rtl8822b_phy.c */
+#define RF_ModeTableData1	0x32	/* rtl8822b_phy.c */
+#define RF_0x52			0x52
+#define RF_WeLut_Jaguar		0xEF	/* rtl8822b_phy.c */
+
+/* General Functions */
+void rtl8822b_init_hal_spec(PADAPTER);				/* hal/hal_com.c */
+
+#ifdef CONFIG_MP_INCLUDED
+/* MP Functions */
+#include <rtw_mp.h>		/* struct mp_priv */
+void rtl8822b_prepare_mp_txdesc(PADAPTER, struct mp_priv *);	/* rtw_mp.c */
+void rtl8822b_mp_config_rfpath(PADAPTER);			/* hal_mp.c */
+#endif
+void hw_var_set_dl_rsvd_page(PADAPTER adapter, u8 mstatus);
+
+#ifdef CONFIG_USB_HCI
+#include <rtl8822bu_hal.h>
+#elif defined(CONFIG_SDIO_HCI)
+#include <rtl8822bs_hal.h>
+#elif defined(CONFIG_PCI_HCI)
+#include <rtl8822be_hal.h>
+#endif
+
+#endif /* _RTL8822B_HAL_H_ */
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/include/rtl8822bs_hal.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/rtl8822bs_hal.h
--- linux-5.6.3/3rdparty/rtl8821ce/include/rtl8822bs_hal.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/rtl8822bs_hal.h	2020-04-10 16:35:06.850661655 +0300
@@ -0,0 +1,31 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2015 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#ifndef _RTL8822BS_HAL_H_
+#define _RTL8822BS_HAL_H_
+
+#include <drv_types.h>		/* PADAPTER */
+
+/* rtl8822bs_ops.c */
+void rtl8822bs_set_hal_ops(PADAPTER);
+
+#if defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN)
+void rtl8822bs_disable_interrupt_but_cpwm2(PADAPTER adapter);
+#endif
+
+/* rtl8822bs_xmit.c */
+s32 rtl8822bs_dequeue_writeport(PADAPTER);
+#define _dequeue_writeport(a)	rtl8822bs_dequeue_writeport(a)
+
+#endif /* _RTL8822BS_HAL_H_ */
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/include/rtl8822bu_hal.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/rtl8822bu_hal.h
--- linux-5.6.3/3rdparty/rtl8821ce/include/rtl8822bu_hal.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/rtl8822bu_hal.h	2020-04-10 16:35:06.850661655 +0300
@@ -0,0 +1,65 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2015 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#ifndef _RTL8822BU_HAL_H_
+#define _RTL8822BU_HAL_H_
+
+#ifdef CONFIG_USB_HCI
+	#include <drv_types.h>		/* PADAPTER */
+
+	#ifdef CONFIG_USB_HCI
+		#ifdef USB_PACKET_OFFSET_SZ
+			#define PACKET_OFFSET_SZ (USB_PACKET_OFFSET_SZ)
+		#else
+			#define PACKET_OFFSET_SZ (8)
+		#endif
+		#define TXDESC_OFFSET (TXDESC_SIZE + PACKET_OFFSET_SZ)
+	#endif
+
+	/* undefine MAX_RECVBUF_SZ from rtl8822b_hal.h  */
+	#ifdef MAX_RECVBUF_SZ
+		#undef MAX_RECVBUF_SZ
+	#endif
+
+	/* recv_buffer must be large than usb agg size */
+	#ifndef MAX_RECVBUF_SZ
+		#ifdef PLATFORM_OS_CE
+			#define MAX_RECVBUF_SZ (8192+1024)
+		#else /* !PLATFORM_OS_CE */
+			#ifndef CONFIG_MINIMAL_MEMORY_USAGE
+				#ifdef CONFIG_PLATFORM_NOVATEK_NT72668
+				#define MAX_RECVBUF_SZ (15360) /* 15k */
+				#elif defined(CONFIG_PLATFORM_HISILICON)
+				/* use 16k to workaround for HISILICON platform */
+				#define MAX_RECVBUF_SZ (16384)
+				#else
+				#define MAX_RECVBUF_SZ (32768)
+				#endif
+			#else
+				#define MAX_RECVBUF_SZ (4000)
+			#endif
+		#endif /* PLATFORM_OS_CE */
+	#endif /* !MAX_RECVBUF_SZ */
+
+	/* rtl8822bu_ops.c */
+	void rtl8822bu_set_hal_ops(PADAPTER padapter);
+	void rtl8822bu_set_hw_type(struct dvobj_priv *pdvobj);
+
+	/* rtl8822bu_io.c */
+	void rtl8822bu_set_intf_ops(struct _io_ops *pops);
+
+#endif /* CONFIG_USB_HCI */
+
+
+#endif /* _RTL8822BU_HAL_H_ */
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/include/rtw_android.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/rtw_android.h
--- linux-5.6.3/3rdparty/rtl8821ce/include/rtw_android.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/rtw_android.h	2020-04-10 16:35:06.850661655 +0300
@@ -0,0 +1,111 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+
+#ifndef __RTW_ANDROID_H__
+#define __RTW_ANDROID_H__
+
+enum ANDROID_WIFI_CMD {
+	ANDROID_WIFI_CMD_START,
+	ANDROID_WIFI_CMD_STOP,
+	ANDROID_WIFI_CMD_SCAN_ACTIVE,
+	ANDROID_WIFI_CMD_SCAN_PASSIVE,
+	ANDROID_WIFI_CMD_RSSI,
+	ANDROID_WIFI_CMD_LINKSPEED,
+	ANDROID_WIFI_CMD_RXFILTER_START,
+	ANDROID_WIFI_CMD_RXFILTER_STOP,
+	ANDROID_WIFI_CMD_RXFILTER_ADD,
+	ANDROID_WIFI_CMD_RXFILTER_REMOVE,
+	ANDROID_WIFI_CMD_BTCOEXSCAN_START,
+	ANDROID_WIFI_CMD_BTCOEXSCAN_STOP,
+	ANDROID_WIFI_CMD_BTCOEXMODE,
+	ANDROID_WIFI_CMD_SETSUSPENDOPT,
+	ANDROID_WIFI_CMD_P2P_DEV_ADDR,
+	ANDROID_WIFI_CMD_SETFWPATH,
+	ANDROID_WIFI_CMD_SETBAND,
+	ANDROID_WIFI_CMD_GETBAND,
+	ANDROID_WIFI_CMD_COUNTRY,
+	ANDROID_WIFI_CMD_P2P_SET_NOA,
+	ANDROID_WIFI_CMD_P2P_GET_NOA,
+	ANDROID_WIFI_CMD_P2P_SET_PS,
+	ANDROID_WIFI_CMD_SET_AP_WPS_P2P_IE,
+
+	ANDROID_WIFI_CMD_MIRACAST,
+
+#ifdef CONFIG_PNO_SUPPORT
+	ANDROID_WIFI_CMD_PNOSSIDCLR_SET,
+	ANDROID_WIFI_CMD_PNOSETUP_SET,
+	ANDROID_WIFI_CMD_PNOENABLE_SET,
+	ANDROID_WIFI_CMD_PNODEBUG_SET,
+#endif
+
+	ANDROID_WIFI_CMD_MACADDR,
+
+	ANDROID_WIFI_CMD_BLOCK_SCAN,
+	ANDROID_WIFI_CMD_BLOCK,
+
+	ANDROID_WIFI_CMD_WFD_ENABLE,
+	ANDROID_WIFI_CMD_WFD_DISABLE,
+
+	ANDROID_WIFI_CMD_WFD_SET_TCPPORT,
+	ANDROID_WIFI_CMD_WFD_SET_MAX_TPUT,
+	ANDROID_WIFI_CMD_WFD_SET_DEVTYPE,
+	ANDROID_WIFI_CMD_CHANGE_DTIM,
+	ANDROID_WIFI_CMD_HOSTAPD_SET_MACADDR_ACL,
+	ANDROID_WIFI_CMD_HOSTAPD_ACL_ADD_STA,
+	ANDROID_WIFI_CMD_HOSTAPD_ACL_REMOVE_STA,
+#if defined(CONFIG_GTK_OL) && (LINUX_VERSION_CODE < KERNEL_VERSION(3, 1, 0))
+	ANDROID_WIFI_CMD_GTK_REKEY_OFFLOAD,
+#endif /* CONFIG_GTK_OL */
+	ANDROID_WIFI_CMD_P2P_DISABLE,
+	ANDROID_WIFI_CMD_SET_AEK,
+	ANDROID_WIFI_CMD_DRIVERVERSION,
+	ANDROID_WIFI_CMD_MAX
+};
+
+int rtw_android_cmdstr_to_num(char *cmdstr);
+int rtw_android_priv_cmd(struct net_device *net, struct ifreq *ifr, int cmd);
+
+#if defined(CONFIG_PNO_SUPPORT) && (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 0, 0))
+int rtw_android_pno_enable(struct net_device *net, int pno_enable);
+int rtw_android_cfg80211_pno_setup(struct net_device *net,
+		   struct cfg80211_ssid *ssid, int n_ssids, int interval);
+#endif
+
+#if defined(RTW_ENABLE_WIFI_CONTROL_FUNC)
+int rtw_android_wifictrl_func_add(void);
+void rtw_android_wifictrl_func_del(void);
+void *wl_android_prealloc(int section, unsigned long size);
+
+int wifi_get_irq_number(unsigned long *irq_flags_ptr);
+int wifi_set_power(int on, unsigned long msec);
+int wifi_get_mac_addr(unsigned char *buf);
+void *wifi_get_country_code(char *ccode);
+#else
+static inline int rtw_android_wifictrl_func_add(void)
+{
+	return 0;
+}
+static inline void rtw_android_wifictrl_func_del(void) {}
+#endif /* defined(RTW_ENABLE_WIFI_CONTROL_FUNC) */
+
+#ifdef CONFIG_GPIO_WAKEUP
+#ifdef CONFIG_PLATFORM_INTEL_BYT
+int wifi_configure_gpio(void);
+#endif /* CONFIG_PLATFORM_INTEL_BYT */
+void wifi_free_gpio(unsigned int gpio);
+#endif /* CONFIG_GPIO_WAKEUP */
+
+
+#endif /* __RTW_ANDROID_H__ */
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/include/rtw_ap.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/rtw_ap.h
--- linux-5.6.3/3rdparty/rtl8821ce/include/rtw_ap.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/rtw_ap.h	2020-04-10 16:35:06.850661655 +0300
@@ -0,0 +1,112 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#ifndef __RTW_AP_H_
+#define __RTW_AP_H_
+
+
+#ifdef CONFIG_AP_MODE
+
+/* external function */
+extern void rtw_indicate_sta_assoc_event(_adapter *padapter, struct sta_info *psta);
+extern void rtw_indicate_sta_disassoc_event(_adapter *padapter, struct sta_info *psta);
+
+
+void init_mlme_ap_info(_adapter *padapter);
+void free_mlme_ap_info(_adapter *padapter);
+u8 rtw_set_tim_ie(u8 dtim_cnt, u8 dtim_period
+	, const u8 *tim_bmp, u8 tim_bmp_len, u8 *tim_ie);
+/* void update_BCNTIM(_adapter *padapter); */
+void rtw_add_bcn_ie(_adapter *padapter, WLAN_BSSID_EX *pnetwork, u8 index, u8 *data, u8 len);
+void rtw_remove_bcn_ie(_adapter *padapter, WLAN_BSSID_EX *pnetwork, u8 index);
+void _update_beacon(_adapter *padapter, u8 ie_id, u8 *oui, u8 tx, const char *tag);
+#define update_beacon(adapter, ie_id, oui, tx) _update_beacon((adapter), (ie_id), (oui), (tx), __func__)
+
+void rtw_ap_update_sta_ra_info(_adapter *padapter, struct sta_info *psta);
+
+void expire_timeout_chk(_adapter *padapter);
+void update_sta_info_apmode(_adapter *padapter, struct sta_info *psta);
+void rtw_start_bss_hdl_after_chbw_decided(_adapter *adapter);
+void start_bss_network(_adapter *padapter, struct createbss_parm *parm);
+int rtw_check_beacon_data(_adapter *padapter, u8 *pbuf,  int len);
+void rtw_ap_restore_network(_adapter *padapter);
+
+#if CONFIG_RTW_MACADDR_ACL
+void rtw_macaddr_acl_init(_adapter *adapter, u8 period);
+void rtw_macaddr_acl_deinit(_adapter *adapter, u8 period);
+void rtw_macaddr_acl_clear(_adapter *adapter, u8 period);
+void rtw_set_macaddr_acl(_adapter *adapter, u8 period, int mode);
+int rtw_acl_add_sta(_adapter *adapter, u8 period, const u8 *addr);
+int rtw_acl_remove_sta(_adapter *adapter, u8 period, const u8 *addr);
+#endif /* CONFIG_RTW_MACADDR_ACL */
+
+u8 rtw_ap_set_sta_key(_adapter *adapter, const u8 *addr, u8 alg, const u8 *key, u8 keyid, u8 gk);
+u8 rtw_ap_set_pairwise_key(_adapter *padapter, struct sta_info *psta);
+int rtw_ap_set_group_key(_adapter *padapter, u8 *key, u8 alg, int keyid);
+int rtw_ap_set_wep_key(_adapter *padapter, u8 *key, u8 keylen, int keyid, u8 set_tx);
+
+#ifdef CONFIG_NATIVEAP_MLME
+void associated_clients_update(_adapter *padapter, u8 updated, u32 sta_info_type);
+void bss_cap_update_on_sta_join(_adapter *padapter, struct sta_info *psta);
+u8 bss_cap_update_on_sta_leave(_adapter *padapter, struct sta_info *psta);
+void sta_info_update(_adapter *padapter, struct sta_info *psta);
+void ap_sta_info_defer_update(_adapter *padapter, struct sta_info *psta);
+u8 ap_free_sta(_adapter *padapter, struct sta_info *psta, bool active, u16 reason, bool enqueue);
+int rtw_sta_flush(_adapter *padapter, bool enqueue);
+int rtw_ap_inform_ch_switch(_adapter *padapter, u8 new_ch, u8 ch_offset);
+void start_ap_mode(_adapter *padapter);
+void stop_ap_mode(_adapter *padapter);
+#endif
+
+void rtw_ap_update_bss_chbw(_adapter *adapter, WLAN_BSSID_EX *bss, u8 ch, u8 bw, u8 offset);
+u8 rtw_ap_chbw_decision(_adapter *adapter, u8 ifbmp, u8 excl_ifbmp
+	, s16 req_ch, s8 req_bw, s8 req_offset, u8 *ch, u8 *bw, u8 *offset, u8 *chbw_allow);
+
+#ifdef CONFIG_AUTO_AP_MODE
+void rtw_auto_ap_rx_msg_dump(_adapter *padapter, union recv_frame *precv_frame, u8 *ehdr_pos);
+extern void rtw_start_auto_ap(_adapter *adapter);
+#endif /* CONFIG_AUTO_AP_MODE */
+
+void rtw_ap_parse_sta_capability(_adapter *adapter, struct sta_info *sta, u8 *cap);
+u16 rtw_ap_parse_sta_supported_rates(_adapter *adapter, struct sta_info *sta, u8 *tlv_ies, u16 tlv_ies_len);
+u16 rtw_ap_parse_sta_security_ie(_adapter *adapter, struct sta_info *sta, struct rtw_ieee802_11_elems *elems);
+void rtw_ap_parse_sta_wmm_ie(_adapter *adapter, struct sta_info *sta, u8 *tlv_ies, u16 tlv_ies_len);
+void rtw_ap_parse_sta_ht_ie(_adapter *adapter, struct sta_info *sta, struct rtw_ieee802_11_elems *elems);
+void rtw_ap_parse_sta_vht_ie(_adapter *adapter, struct sta_info *sta, struct rtw_ieee802_11_elems *elems);
+
+void update_bmc_sta(_adapter *padapter);
+
+#ifdef CONFIG_BMC_TX_RATE_SELECT
+void rtw_update_bmc_sta_tx_rate(_adapter *adapter);
+#endif
+
+void rtw_process_ht_action_smps(_adapter *padapter, u8 *ta, u8 ctrl_field);
+void rtw_process_public_act_bsscoex(_adapter *padapter, u8 *pframe, uint frame_len);
+#ifdef CONFIG_80211N_HT
+int rtw_ht_operation_update(_adapter *padapter);
+#endif /* CONFIG_80211N_HT */
+u8 rtw_ap_sta_states_check(_adapter *adapter);
+
+#ifdef CONFIG_FW_HANDLE_TXBCN
+#define rtw_ap_get_nums(adapter)	(adapter_to_dvobj(adapter)->nr_ap_if)
+bool rtw_ap_nums_check(_adapter *adapter);
+#endif
+
+#ifdef CONFIG_SWTIMER_BASED_TXBCN
+void tx_beacon_handlder(struct dvobj_priv *pdvobj);
+void tx_beacon_timer_handlder(void *ctx);
+#endif /*CONFIG_SWTIMER_BASED_TXBCN*/
+
+#endif /* end of CONFIG_AP_MODE */
+#endif /*__RTW_AP_H_*/
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/include/rtw_beamforming.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/rtw_beamforming.h
--- linux-5.6.3/3rdparty/rtl8821ce/include/rtw_beamforming.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/rtw_beamforming.h	2020-04-10 16:35:06.850661655 +0300
@@ -0,0 +1,401 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#ifndef __RTW_BEAMFORMING_H_
+#define __RTW_BEAMFORMING_H_
+
+#ifdef CONFIG_BEAMFORMING
+
+#ifdef RTW_BEAMFORMING_VERSION_2
+#define MAX_NUM_BEAMFORMEE_SU	2
+#define MAX_NUM_BEAMFORMER_SU	2
+#define MAX_NUM_BEAMFORMEE_MU	6
+#define MAX_NUM_BEAMFORMER_MU	1
+
+#define MAX_BEAMFORMEE_ENTRY_NUM	(MAX_NUM_BEAMFORMEE_SU + MAX_NUM_BEAMFORMEE_MU)
+#define MAX_BEAMFORMER_ENTRY_NUM	(MAX_NUM_BEAMFORMER_SU + MAX_NUM_BEAMFORMER_MU)
+
+/* <Note> Need to be defined by IC */
+#define SU_SOUNDING_TIMEOUT	5	/* unit: ms */
+#define MU_SOUNDING_TIMEOUT	8	/* unit: ms */
+
+#define GET_BEAMFORM_INFO(adapter)	(&GET_HAL_DATA(adapter)->beamforming_info)
+#define GetInitSoundCnt(_SoundPeriod, _MinSoundPeriod)	((_SoundPeriod)/(_MinSoundPeriod))
+
+enum BEAMFORMING_CTRL_TYPE {
+	BEAMFORMING_CTRL_ENTER = 0,
+	BEAMFORMING_CTRL_LEAVE = 1,
+	BEAMFORMING_CTRL_START_PERIOD = 2,
+	BEAMFORMING_CTRL_END_PERIOD = 3,
+	BEAMFORMING_CTRL_SOUNDING_FAIL = 4,
+	BEAMFORMING_CTRL_SOUNDING_CLK = 5,
+	BEAMFORMING_CTRL_SET_GID_TABLE = 6,
+	BEAMFORMING_CTRL_SET_CSI_REPORT = 7,
+};
+
+enum _BEAMFORMING_STATE {
+	BEAMFORMING_STATE_IDLE,
+	BEAMFORMING_STATE_START,
+	BEAMFORMING_STATE_END,
+};
+
+/*
+ * typedef BEAMFORMING_CAP for phydm
+ */
+typedef enum beamforming_cap {
+	BEAMFORMING_CAP_NONE = 0x0,
+	BEAMFORMER_CAP_HT_EXPLICIT = 0x1,
+	BEAMFORMEE_CAP_HT_EXPLICIT = 0x2,
+	BEAMFORMER_CAP_VHT_SU = 0x4,			/* Self has er Cap, because Reg er  & peer ee */
+	BEAMFORMEE_CAP_VHT_SU = 0x8, 			/* Self has ee Cap, because Reg ee & peer er */
+	BEAMFORMER_CAP_VHT_MU = 0x10,			/* Self has er Cap, because Reg er & peer ee */
+	BEAMFORMEE_CAP_VHT_MU = 0x20,			/* Self has ee Cap, because Reg ee & peer er */
+	BEAMFORMER_CAP = 0x40,
+	BEAMFORMEE_CAP = 0x80,
+} BEAMFORMING_CAP;
+
+enum _BEAMFORM_ENTRY_HW_STATE {
+	BEAMFORM_ENTRY_HW_STATE_NONE,
+	BEAMFORM_ENTRY_HW_STATE_ADD_INIT,
+	BEAMFORM_ENTRY_HW_STATE_ADDING,
+	BEAMFORM_ENTRY_HW_STATE_ADDED,
+	BEAMFORM_ENTRY_HW_STATE_DELETE_INIT,
+	BEAMFORM_ENTRY_HW_STATE_DELETING,
+	BEAMFORM_ENTRY_HW_STATE_MAX
+};
+
+/* The sounding state is recorded by BFer. */
+enum _SOUNDING_STATE {
+	SOUNDING_STATE_NONE		= 0,
+	SOUNDING_STATE_INIT		= 1,
+	SOUNDING_STATE_SU_START		= 2,
+	SOUNDING_STATE_SU_SOUNDDOWN	= 3,
+	SOUNDING_STATE_MU_START		= 4,
+	SOUNDING_STATE_MU_SOUNDDOWN	= 5,
+	SOUNDING_STATE_SOUNDING_TIMEOUT	= 6,
+	SOUNDING_STATE_MAX
+};
+
+struct beamformee_entry {
+	u8 used;	/* _TRUE/_FALSE */
+	u8 txbf;
+	u8 sounding;
+	/* Used to construct AID field of NDPA packet */
+	u16 aid;
+	/* Used to Set Reg42C in IBSS mode */
+	u16 mac_id;
+	/* Used to fill Reg42C & Reg714 to compare with P_AID of Tx DESC */
+	u16 p_aid;
+	u8 g_id;
+	/* Used to fill Reg6E4 to fill Mac address of CSI report frame */
+	u8 mac_addr[ETH_ALEN];
+	/* Sounding BandWidth */
+	enum channel_width sound_bw;
+	u16 sound_period;
+
+	enum beamforming_cap cap;
+	enum _BEAMFORM_ENTRY_HW_STATE state;
+
+	/* The BFee need to be sounded when count to zero */
+	u8 SoundCnt;
+	u8 bCandidateSoundingPeer;
+	u8 bSoundingTimeout;
+	u8 bDeleteSounding;
+	/* Get the result through throughput and Tx rate from BB API */
+	u8 bApplySounding;
+
+	/* information for sounding judgement */
+	systime tx_timestamp;
+	u64 tx_bytes;
+
+	u16 LogStatusFailCnt:5;	/* 0~21 */
+	u16 DefaultCSICnt:5; /* 0~21 */
+	u8 CSIMatrix[327];
+	u16 CSIMatrixLen;
+
+	u8 NumofSoundingDim;
+
+	u8 comp_steering_num_of_bfer;
+
+
+	/* SU-MIMO */
+	u8 su_reg_index;
+
+	/* MU-MIMO */
+	u8 mu_reg_index;
+	u8 gid_valid[8];
+	u8 user_position[16];
+
+	/* For 8822B C-cut workaround */
+	/* If the flag set to _TRUE, do not sound this STA */
+	u8 bSuspendSUCap;
+};
+
+struct beamformer_entry {
+	u8 used;
+	/* p_aid of BFer entry is probably not used */
+	/* Used to fill Reg42C & Reg714 to compare with p_aid of Tx DESC */
+	u16 p_aid;
+	u8 g_id;
+	u8 mac_addr[ETH_ALEN];
+
+	enum beamforming_cap cap;
+	enum _BEAMFORM_ENTRY_HW_STATE state;
+
+	u8 NumofSoundingDim;
+
+	/* SU-MIMO */
+	u8 su_reg_index;
+
+	/* MU-MIMO */
+	u8 gid_valid[8];
+	u8 user_position[16];
+	u16 aid;
+};
+
+struct sounding_info {
+	u8 su_sounding_list[MAX_NUM_BEAMFORMEE_SU];
+	u8 mu_sounding_list[MAX_NUM_BEAMFORMEE_MU];
+
+	enum _SOUNDING_STATE state;
+	/*
+	 * su_bfee_curidx is index for beamforming_info.bfee_entry[]
+	 * range: 0~MAX_BEAMFORMEE_ENTRY_NUM
+	 */
+	u8 su_bfee_curidx;
+	u8 candidate_mu_bfee_cnt;
+
+	/* For sounding schedule maintenance */
+	u16 min_sounding_period;
+	/* Get from sounding list */
+	/* Ex: SU STA1, SU STA2, MU STA(1~n) => the value will be 2+1=3 */
+	u8 sound_remain_cnt_per_period;
+};
+
+struct _RT_CSI_INFO{
+	u8 Nc;
+	u8 Nr;
+	u8 Ng;
+	u8 CodeBook;
+	u8 ChnlWidth;
+	u8 bVHT;
+};
+
+struct beamforming_info {
+	enum beamforming_cap beamforming_cap;
+	enum _BEAMFORMING_STATE beamforming_state;
+	struct beamformee_entry bfee_entry[MAX_BEAMFORMEE_ENTRY_NUM];
+	struct beamformer_entry bfer_entry[MAX_BEAMFORMER_ENTRY_NUM];
+	u8 sounding_sequence;
+	u8 beamformee_su_cnt;
+	u8 beamformer_su_cnt;
+	u32 beamformee_su_reg_maping;
+	u32 beamformer_su_reg_maping;
+	/* For MU-MINO */
+	u8 beamformee_mu_cnt;
+	u8 beamformer_mu_cnt;
+	u32 beamformee_mu_reg_maping;
+	u8 first_mu_bfee_index;
+	u8 mu_bfer_curidx;
+	u8 cur_csi_rpt_rate;
+
+	struct sounding_info sounding_info;
+	/* schedule regular timer for sounding */
+	_timer sounding_timer;
+	/* moniter if soudning too long */
+	_timer sounding_timeout_timer;
+
+	/* For HW configuration */
+	u8 SetHalBFEnterOnDemandCnt;
+	u8 SetHalBFLeaveOnDemandCnt;
+	u8 SetHalSoundownOnDemandCnt;
+	u8 bSetBFHwConfigInProgess;
+
+	/*
+	 * Target CSI report info.
+	 * Keep the first SU CSI report info for 8822B HW bug workaround.
+	 */
+	u8 bEnableSUTxBFWorkAround;
+	struct _RT_CSI_INFO TargetCSIInfo;
+	/* Only peform sounding to the first SU BFee */
+	struct beamformee_entry *TargetSUBFee;
+
+	/* For debug */
+	s8 sounding_running;
+};
+
+enum beamforming_cap rtw_bf_bfee_get_entry_cap_by_macid(void *mlmepriv, u8 mac_id);
+struct beamformer_entry *rtw_bf_bfer_get_entry_by_addr(PADAPTER, u8 *ra);
+struct beamformee_entry *rtw_bf_bfee_get_entry_by_addr(PADAPTER, u8 *ra);
+void rtw_bf_get_ndpa_packet(PADAPTER, union recv_frame *);
+u32 rtw_bf_get_report_packet(PADAPTER, union recv_frame *);
+u8 rtw_bf_send_vht_gid_mgnt_packet(PADAPTER, u8 *ra, u8 *gid, u8 *position);
+void rtw_bf_get_vht_gid_mgnt_packet(PADAPTER, union recv_frame *);
+void rtw_bf_init(PADAPTER);
+void rtw_bf_cmd_hdl(PADAPTER, u8 type, u8 *pbuf);
+u8 rtw_bf_cmd(PADAPTER, s32 type, u8 *pbuf, s32 size, u8 enqueue);
+void rtw_bf_update_attrib(PADAPTER, struct pkt_attrib *, struct sta_info *);
+void rtw_bf_c2h_handler(PADAPTER, u8 id, u8 *buf, u8 buf_len);
+void rtw_bf_update_traffic(PADAPTER);
+
+/* Compatible with old function name, only for using outside rtw_beamforming.c */
+#define beamforming_get_entry_beam_cap_by_mac_id	rtw_bf_bfee_get_entry_cap_by_macid
+#define rtw_beamforming_get_ndpa_frame			rtw_bf_get_ndpa_packet
+#define rtw_beamforming_get_report_frame			rtw_bf_get_report_packet
+#define rtw_beamforming_get_vht_gid_mgnt_frame		rtw_bf_get_vht_gid_mgnt_packet
+#define beamforming_wk_hdl				rtw_bf_cmd_hdl
+#define beamforming_wk_cmd				rtw_bf_cmd
+#define update_attrib_txbf_info				rtw_bf_update_attrib
+
+#define HT_BF_CAP(adapter) ((adapter)->mlmepriv.htpriv.beamform_cap)
+#define VHT_BF_CAP(adapter) ((adapter)->mlmepriv.vhtpriv.beamform_cap)
+
+#define IS_HT_BEAMFORMEE(adapter) \
+		(HT_BF_CAP(adapter) & \
+		(BEAMFORMING_HT_BEAMFORMEE_ENABLE))
+
+#define IS_VHT_BEAMFORMEE(adapter) \
+		(VHT_BF_CAP(adapter) & \
+		(BEAMFORMING_VHT_BEAMFORMEE_ENABLE | \
+		 BEAMFORMING_VHT_MU_MIMO_STA_ENABLE))
+
+#define IS_BEAMFORMEE(adapter) (IS_HT_BEAMFORMEE(adapter) | \
+				IS_VHT_BEAMFORMEE(adapter))
+
+#else /* !RTW_BEAMFORMING_VERSION_2 */
+
+#if (BEAMFORMING_SUPPORT == 0) /*for diver defined beamforming*/
+#define BEAMFORMING_ENTRY_NUM		2
+#define GET_BEAMFORM_INFO(_pmlmepriv)	((struct beamforming_info *)(&(_pmlmepriv)->beamforming_info))
+
+
+typedef enum _BEAMFORMING_ENTRY_STATE {
+	BEAMFORMING_ENTRY_STATE_UNINITIALIZE,
+	BEAMFORMING_ENTRY_STATE_INITIALIZEING,
+	BEAMFORMING_ENTRY_STATE_INITIALIZED,
+	BEAMFORMING_ENTRY_STATE_PROGRESSING,
+	BEAMFORMING_ENTRY_STATE_PROGRESSED,
+} BEAMFORMING_ENTRY_STATE, *PBEAMFORMING_ENTRY_STATE;
+
+
+typedef enum _BEAMFORMING_STATE {
+	BEAMFORMING_STATE_IDLE,
+	BEAMFORMING_STATE_START,
+	BEAMFORMING_STATE_END,
+} BEAMFORMING_STATE, *PBEAMFORMING_STATE;
+
+
+typedef enum _BEAMFORMING_CAP {
+	BEAMFORMING_CAP_NONE = 0x0,
+	BEAMFORMER_CAP_HT_EXPLICIT = 0x1,
+	BEAMFORMEE_CAP_HT_EXPLICIT = 0x2,
+	BEAMFORMER_CAP_VHT_SU = 0x4,			/* Self has er Cap, because Reg er  & peer ee */
+	BEAMFORMEE_CAP_VHT_SU = 0x8, 			/* Self has ee Cap, because Reg ee & peer er */
+	BEAMFORMER_CAP = 0x10,
+	BEAMFORMEE_CAP = 0x20,
+} BEAMFORMING_CAP, *PBEAMFORMING_CAP;
+
+
+typedef enum _SOUNDING_MODE {
+	SOUNDING_SW_VHT_TIMER = 0x0,
+	SOUNDING_SW_HT_TIMER = 0x1,
+	SOUNDING_STOP_All_TIMER = 0x2,
+	SOUNDING_HW_VHT_TIMER = 0x3,
+	SOUNDING_HW_HT_TIMER = 0x4,
+	SOUNDING_STOP_OID_TIMER = 0x5,
+	SOUNDING_AUTO_VHT_TIMER = 0x6,
+	SOUNDING_AUTO_HT_TIMER = 0x7,
+	SOUNDING_FW_VHT_TIMER = 0x8,
+	SOUNDING_FW_HT_TIMER = 0x9,
+} SOUNDING_MODE, *PSOUNDING_MODE;
+
+struct beamforming_entry {
+	BOOLEAN	bUsed;
+	BOOLEAN	bSound;
+	u16	aid;			/* Used to construct AID field of NDPA packet. */
+	u16	mac_id;		/* Used to Set Reg42C in IBSS mode. */
+	u16	p_aid;		/* Used to fill Reg42C & Reg714 to compare with P_AID of Tx DESC. */
+	u16 g_id;
+	u8	mac_addr[ETH_ALEN];/* Used to fill Reg6E4 to fill Mac address of CSI report frame. */
+	enum channel_width	sound_bw;	/* Sounding BandWidth */
+	u16	sound_period;
+	BEAMFORMING_CAP	beamforming_entry_cap;
+	BEAMFORMING_ENTRY_STATE	beamforming_entry_state;
+	u8				ClockResetTimes;			/*Modified by Jeffery @2015-04-10*/
+	u8				PreLogSeq;				/*Modified by Jeffery @2015-03-30*/
+	u8				LogSeq;					/*Modified by Jeffery @2014-10-29*/
+	u16				LogRetryCnt:3;			/*Modified by Jeffery @2014-10-29*/
+	u16				LogSuccess:2;			/*Modified by Jeffery @2014-10-29*/
+
+	u8	LogStatusFailCnt;
+	u8	PreCsiReport[327];
+	u8	DefaultCsiCnt;
+	BOOLEAN	bDefaultCSI;
+};
+
+struct sounding_info {
+	u8				sound_idx;
+	enum channel_width	sound_bw;
+	SOUNDING_MODE	sound_mode;
+	u16				sound_period;
+};
+
+struct beamforming_info {
+	BEAMFORMING_CAP		beamforming_cap;
+	BEAMFORMING_STATE		beamforming_state;
+	struct beamforming_entry	beamforming_entry[BEAMFORMING_ENTRY_NUM];
+	u8						beamforming_cur_idx;
+	u8						beamforming_in_progress;
+	u8						sounding_sequence;
+	struct sounding_info		sounding_info;
+};
+
+struct rtw_ndpa_sta_info {
+	u16	aid:12;
+	u16	feedback_type:1;
+	u16	nc_index:3;
+};
+
+BEAMFORMING_CAP beamforming_get_entry_beam_cap_by_mac_id(PVOID pmlmepriv , u8 mac_id);
+void	beamforming_notify(PADAPTER adapter);
+BEAMFORMING_CAP beamforming_get_beamform_cap(struct beamforming_info	*pBeamInfo);
+
+BOOLEAN	beamforming_send_ht_ndpa_packet(PADAPTER Adapter, u8 *ra, enum channel_width bw, u8 qidx);
+BOOLEAN	beamforming_send_vht_ndpa_packet(PADAPTER Adapter, u8 *ra, u16 aid, enum channel_width bw, u8 qidx);
+
+void	beamforming_check_sounding_success(PADAPTER Adapter, BOOLEAN status);
+
+void	beamforming_watchdog(PADAPTER Adapter);
+#endif /*#if (BEAMFORMING_SUPPORT ==0)- for diver defined beamforming*/
+
+enum BEAMFORMING_CTRL_TYPE {
+	BEAMFORMING_CTRL_ENTER = 0,
+	BEAMFORMING_CTRL_LEAVE = 1,
+	BEAMFORMING_CTRL_START_PERIOD = 2,
+	BEAMFORMING_CTRL_END_PERIOD = 3,
+	BEAMFORMING_CTRL_SOUNDING_FAIL = 4,
+	BEAMFORMING_CTRL_SOUNDING_CLK = 5,
+};
+u32	rtw_beamforming_get_report_frame(PADAPTER	 Adapter, union recv_frame *precv_frame);
+void	rtw_beamforming_get_ndpa_frame(PADAPTER	 Adapter, union recv_frame *precv_frame);
+
+void	beamforming_wk_hdl(_adapter *padapter, u8 type, u8 *pbuf);
+u8	beamforming_wk_cmd(_adapter *padapter, s32 type, u8 *pbuf, s32 size, u8 enqueue);
+void update_attrib_txbf_info(_adapter *padapter, struct pkt_attrib *pattrib, struct sta_info *psta);
+
+#endif /* !RTW_BEAMFORMING_VERSION_2 */
+
+#endif /*#ifdef CONFIG_BEAMFORMING */
+
+#endif /*__RTW_BEAMFORMING_H_*/
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/include/rtw_br_ext.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/rtw_br_ext.h
--- linux-5.6.3/3rdparty/rtl8821ce/include/rtw_br_ext.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/rtw_br_ext.h	2020-04-10 16:35:06.850661655 +0300
@@ -0,0 +1,69 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#ifndef _RTW_BR_EXT_H_
+#define _RTW_BR_EXT_H_
+
+#if 1	/* rtw_wifi_driver */
+#define CL_IPV6_PASS	1
+#define MACADDRLEN		6
+#define _DEBUG_ERR		RTW_INFO
+#define _DEBUG_INFO		/* RTW_INFO */
+#define DEBUG_WARN		RTW_INFO
+#define DEBUG_INFO		/* RTW_INFO */
+#define DEBUG_ERR		RTW_INFO
+/* #define GET_MY_HWADDR		((GET_MIB(priv))->dot11OperationEntry.hwaddr) */
+#define GET_MY_HWADDR(padapter)		(adapter_mac_addr(padapter))
+#endif /* rtw_wifi_driver */
+
+#define NAT25_HASH_BITS		4
+#define NAT25_HASH_SIZE		(1 << NAT25_HASH_BITS)
+#define NAT25_AGEING_TIME	300
+
+#ifdef CL_IPV6_PASS
+	#define MAX_NETWORK_ADDR_LEN	17
+#else
+	#define MAX_NETWORK_ADDR_LEN	11
+#endif
+
+struct nat25_network_db_entry {
+	struct nat25_network_db_entry	*next_hash;
+	struct nat25_network_db_entry	**pprev_hash;
+	atomic_t						use_count;
+	unsigned char					macAddr[6];
+	unsigned long					ageing_timer;
+	unsigned char				networkAddr[MAX_NETWORK_ADDR_LEN];
+};
+
+enum NAT25_METHOD {
+	NAT25_MIN,
+	NAT25_CHECK,
+	NAT25_INSERT,
+	NAT25_LOOKUP,
+	NAT25_PARSE,
+	NAT25_MAX
+};
+
+struct br_ext_info {
+	unsigned int	nat25_disable;
+	unsigned int	macclone_enable;
+	unsigned int	dhcp_bcst_disable;
+	int		addPPPoETag;		/* 1: Add PPPoE relay-SID, 0: disable */
+	unsigned char	nat25_dmzMac[MACADDRLEN];
+	unsigned int	nat25sc_disable;
+};
+
+void nat25_db_cleanup(_adapter *priv);
+
+#endif /* _RTW_BR_EXT_H_ */
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/include/rtw_btcoex.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/rtw_btcoex.h
--- linux-5.6.3/3rdparty/rtl8821ce/include/rtw_btcoex.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/rtw_btcoex.h	2020-04-10 16:35:06.851661701 +0300
@@ -0,0 +1,455 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2013 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#ifdef CONFIG_BT_COEXIST
+
+#ifndef __RTW_BTCOEX_H__
+#define __RTW_BTCOEX_H__
+
+#include <drv_types.h>
+
+/* For H2C: H2C_BT_MP_OPER. Return status definition to the user layer */
+typedef enum _BT_CTRL_STATUS {
+	BT_STATUS_SUCCESS								= 0x00, /* Success */
+	BT_STATUS_BT_OP_SUCCESS							= 0x01, /* bt fw op execution success */
+	BT_STATUS_H2C_SUCCESS							= 0x02, /* H2c success */
+	BT_STATUS_H2C_FAIL								= 0x03, /* H2c fail */
+	BT_STATUS_H2C_LENGTH_EXCEEDED					= 0x04, /* H2c command length exceeded */
+	BT_STATUS_H2C_TIMTOUT							= 0x05, /* H2c timeout */
+	BT_STATUS_H2C_BT_NO_RSP							= 0x06, /* H2c sent, bt no rsp */
+	BT_STATUS_C2H_SUCCESS							= 0x07, /* C2h success */
+	BT_STATUS_C2H_REQNUM_MISMATCH					= 0x08, /* bt fw wrong rsp */
+	BT_STATUS_OPCODE_U_VERSION_MISMATCH				= 0x08, /* Upper layer OP code version mismatch. */
+	BT_STATUS_OPCODE_L_VERSION_MISMATCH				= 0x0a, /* Lower layer OP code version mismatch. */
+	BT_STATUS_UNKNOWN_OPCODE_U						= 0x0b, /* Unknown Upper layer OP code */
+	BT_STATUS_UNKNOWN_OPCODE_L						= 0x0c, /* Unknown Lower layer OP code */
+	BT_STATUS_PARAMETER_FORMAT_ERROR_U				= 0x0d, /* Wrong parameters sent by upper layer. */
+	BT_STATUS_PARAMETER_FORMAT_ERROR_L				= 0x0e, /* bt fw parameter format is not consistency */
+	BT_STATUS_PARAMETER_OUT_OF_RANGE_U				= 0x0f, /* uppery layer parameter value is out of range */
+	BT_STATUS_PARAMETER_OUT_OF_RANGE_L				= 0x10, /* bt fw parameter value is out of range */
+	BT_STATUS_UNKNOWN_STATUS_L						= 0x11, /* bt returned an defined status code */
+	BT_STATUS_UNKNOWN_STATUS_H						= 0x12, /* driver need to do error handle or not handle-well. */
+	BT_STATUS_WRONG_LEVEL							= 0x13, /* should be under passive level */
+	BT_STATUS_NOT_IMPLEMENT						= 0x14, /* op code not implemented yet */
+	BT_STATUS_BT_STACK_OP_SUCCESS					= 0x15, /* bt stack op execution success */
+	BT_STATUS_BT_STACK_NOT_SUPPORT					= 0x16, /* stack version not support this. */
+	BT_STATUS_BT_STACK_SEND_HCI_EVENT_FAIL			= 0x17, /* send hci event fail */
+	BT_STATUS_BT_STACK_NOT_BIND						= 0x18, /* stack not bind wifi driver */
+	BT_STATUS_BT_STACK_NO_RSP						= 0x19, /* stack doesn't have any rsp. */
+	BT_STATUS_MAX
+} BT_CTRL_STATUS, *PBT_CTRL_STATUS;
+
+typedef enum _BTCOEX_SUSPEND_STATE {
+	BTCOEX_SUSPEND_STATE_RESUME					= 0x0,
+	BTCOEX_SUSPEND_STATE_SUSPEND				= 0x1,
+	BTCOEX_SUSPEND_STATE_SUSPEND_KEEP_ANT		= 0x2,
+	BTCOEX_SUSPEND_STATE_MAX
+} BTCOEX_SUSPEND_STATE, *PBTCOEX_SUSPEND_STATE;
+
+#define SET_BT_MP_OPER_RET(OpCode, StatusCode)						((OpCode << 8) | StatusCode)
+#define GET_OP_CODE_FROM_BT_MP_OPER_RET(RetCode)					((RetCode & 0xF0) >> 8)
+#define GET_STATUS_CODE_FROM_BT_MP_OPER_RET(RetCode)				(RetCode & 0x0F)
+#define CHECK_STATUS_CODE_FROM_BT_MP_OPER_RET(RetCode, StatusCode)	(GET_STATUS_CODE_FROM_BT_MP_OPER_RET(RetCode) == StatusCode)
+
+#ifdef CONFIG_BT_COEXIST_SOCKET_TRX
+
+#define NETLINK_USER 31
+#define CONNECT_PORT 30000
+#define CONNECT_PORT_BT 30001
+#define KERNEL_SOCKET_OK 0x01
+#define NETLINK_SOCKET_OK 0x02
+
+#define OTHER 0
+#define RX_ATTEND_ACK 1
+#define RX_LEAVE_ACK 2
+#define RX_BT_LEAVE 3
+#define RX_INVITE_REQ 4
+#define RX_ATTEND_REQ 5
+#define RX_INVITE_RSP 6
+
+#define invite_req "INVITE_REQ"
+#define invite_rsp "INVITE_RSP"
+#define attend_req "ATTEND_REQ"
+#define attend_ack "ATTEND_ACK"
+#define wifi_leave "WIFI_LEAVE"
+#define leave_ack "LEAVE_ACK"
+#define bt_leave "BT_LEAVE"
+
+#define BT_INFO_NOTIFY_CMD 0x0106
+#define BT_INFO_LEN 8
+
+typedef struct _HCI_LINK_INFO {
+	u2Byte					ConnectHandle;
+	u1Byte					IncomingTrafficMode;
+	u1Byte					OutgoingTrafficMode;
+	u1Byte					BTProfile;
+	u1Byte					BTCoreSpec;
+	s1Byte					BT_RSSI;
+	u1Byte					TrafficProfile;
+	u1Byte					linkRole;
+} HCI_LINK_INFO, *PHCI_LINK_INFO;
+
+#define	MAX_BT_ACL_LINK_NUM				8
+
+typedef struct _HCI_EXT_CONFIG {
+	HCI_LINK_INFO				aclLink[MAX_BT_ACL_LINK_NUM];
+	u1Byte					btOperationCode;
+	u2Byte					CurrentConnectHandle;
+	u1Byte					CurrentIncomingTrafficMode;
+	u1Byte					CurrentOutgoingTrafficMode;
+
+	u1Byte					NumberOfACL;
+	u1Byte					NumberOfSCO;
+	u1Byte					CurrentBTStatus;
+	u2Byte					HCIExtensionVer;
+
+	BOOLEAN					bEnableWifiScanNotify;
+} HCI_EXT_CONFIG, *PHCI_EXT_CONFIG;
+
+typedef struct _HCI_PHY_LINK_BSS_INFO {
+	u2Byte						bdCap;			/* capability information */
+
+	/* Qos related. Added by Annie, 2005-11-01. */
+	/* BSS_QOS						BssQos;		 */
+
+} HCI_PHY_LINK_BSS_INFO, *PHCI_PHY_LINK_BSS_INFO;
+
+typedef enum _BT_CONNECT_TYPE {
+	BT_CONNECT_AUTH_REQ								= 0x00,
+	BT_CONNECT_AUTH_RSP								= 0x01,
+	BT_CONNECT_ASOC_REQ								= 0x02,
+	BT_CONNECT_ASOC_RSP								= 0x03,
+	BT_DISCONNECT										= 0x04
+} BT_CONNECT_TYPE, *PBT_CONNECT_TYPE;
+
+
+typedef struct _PACKET_IRP_HCIEVENT_DATA {
+	u8		EventCode;
+	u8		Length; /* total cmd length = extension event length+1(extension event code length) */
+	u8		Data[1]; /* byte1 is extension event code */
+} rtw_HCI_event;
+
+
+struct btinfo_8761ATV {
+	u8 cid;
+	u8 len;
+
+	u8 bConnection:1;
+	u8 bSCOeSCO:1;
+	u8 bInQPage:1;
+	u8 bACLBusy:1;
+	u8 bSCOBusy:1;
+	u8 bHID:1;
+	u8 bA2DP:1;
+	u8 bFTP:1;
+
+	u8 retry_cnt:4;
+	u8 rsvd_34:1;
+	u8 bPage:1;
+	u8 TRxMask:1;
+	u8 Sniff_attempt:1;
+
+	u8 rssi;
+
+	u8 A2dp_rate:1;
+	u8 ReInit:1;
+	u8 MaxPower:1;
+	u8 bEnIgnoreWlanAct:1;
+	u8 TxPowerLow:1;
+	u8 TxPowerHigh:1;
+	u8 eSCO_SCO:1;
+	u8 Master_Slave:1;
+
+	u8 ACL_TRx_TP_low;
+	u8 ACL_TRx_TP_high;
+};
+
+#define HCIOPCODE(_OCF, _OGF)     ((_OGF)<<10|(_OCF))
+#define HCIOPCODELOW(_OCF, _OGF)	(u8)(HCIOPCODE(_OCF, _OGF) & 0x00ff)
+#define HCIOPCODEHIGHT(_OCF, _OGF) (u8)(HCIOPCODE(_OCF, _OGF)>>8)
+#define HCI_OGF(opCode)  (unsigned char)((0xFC00 & (opCode)) >> 10)
+#define HCI_OCF(opCode)  (0x3FF & (opCode))
+
+
+typedef enum _HCI_STATUS {
+	HCI_STATUS_SUCCESS										= 0x00, /* Success */
+	HCI_STATUS_UNKNOW_HCI_CMD								= 0x01, /* Unknown HCI Command */
+	HCI_STATUS_UNKNOW_CONNECT_ID							= 0X02, /* Unknown Connection Identifier */
+	HCI_STATUS_HW_FAIL										= 0X03, /* Hardware Failure */
+	HCI_STATUS_PAGE_TIMEOUT									= 0X04, /* Page Timeout */
+	HCI_STATUS_AUTH_FAIL										= 0X05, /* Authentication Failure */
+	HCI_STATUS_PIN_OR_KEY_MISSING							= 0X06, /* PIN or Key Missing */
+	HCI_STATUS_MEM_CAP_EXCEED								= 0X07, /* Memory Capacity Exceeded */
+	HCI_STATUS_CONNECT_TIMEOUT								= 0X08, /* Connection Timeout */
+	HCI_STATUS_CONNECT_LIMIT									= 0X09, /* Connection Limit Exceeded */
+	HCI_STATUS_SYN_CONNECT_LIMIT								= 0X0a, /* Synchronous Connection Limit To A Device Exceeded */
+	HCI_STATUS_ACL_CONNECT_EXISTS							= 0X0b, /* ACL Connection Already Exists */
+	HCI_STATUS_CMD_DISALLOW									= 0X0c, /* Command Disallowed */
+	HCI_STATUS_CONNECT_RJT_LIMIT_RESOURCE					= 0X0d, /* Connection Rejected due to Limited Resources */
+	HCI_STATUS_CONNECT_RJT_SEC_REASON						= 0X0e, /* Connection Rejected Due To Security Reasons */
+	HCI_STATUS_CONNECT_RJT_UNACCEPT_BD_ADDR				= 0X0f, /* Connection Rejected due to Unacceptable BD_ADDR */
+	HCI_STATUS_CONNECT_ACCEPT_TIMEOUT						= 0X10, /* Connection Accept Timeout Exceeded */
+	HCI_STATUS_UNSUPPORT_FEATURE_PARA_VALUE				= 0X11, /* Unsupported Feature or Parameter Value */
+	HCI_STATUS_INVALID_HCI_CMD_PARA_VALUE					= 0X12, /* Invalid HCI Command Parameters */
+	HCI_STATUS_REMOTE_USER_TERMINATE_CONNECT				= 0X13, /* Remote User Terminated Connection */
+	HCI_STATUS_REMOTE_DEV_TERMINATE_LOW_RESOURCE			= 0X14, /* Remote Device Terminated Connection due to Low Resources */
+	HCI_STATUS_REMOTE_DEV_TERMINATE_CONNECT_POWER_OFF	= 0X15, /* Remote Device Terminated Connection due to Power Off */
+	HCI_STATUS_CONNECT_TERMINATE_LOCAL_HOST				= 0X16, /* Connection Terminated By Local Host */
+	HCI_STATUS_REPEATE_ATTEMPT								= 0X17, /* Repeated Attempts */
+	HCI_STATUS_PAIR_NOT_ALLOW								= 0X18, /* Pairing Not Allowed */
+	HCI_STATUS_UNKNOW_LMP_PDU								= 0X19, /* Unknown LMP PDU */
+	HCI_STATUS_UNSUPPORT_REMOTE_LMP_FEATURE				= 0X1a, /* Unsupported Remote Feature / Unsupported LMP Feature */
+	HCI_STATUS_SOC_OFFSET_REJECT								= 0X1b, /* SCO Offset Rejected */
+	HCI_STATUS_SOC_INTERVAL_REJECT							= 0X1c, /* SCO Interval Rejected */
+	HCI_STATUS_SOC_AIR_MODE_REJECT							= 0X1d, /* SCO Air Mode Rejected */
+	HCI_STATUS_INVALID_LMP_PARA								= 0X1e, /* Invalid LMP Parameters */
+	HCI_STATUS_UNSPECIFIC_ERROR								= 0X1f, /* Unspecified Error */
+	HCI_STATUS_UNSUPPORT_LMP_PARA_VALUE					= 0X20, /* Unsupported LMP Parameter Value */
+	HCI_STATUS_ROLE_CHANGE_NOT_ALLOW						= 0X21, /* Role Change Not Allowed */
+	HCI_STATUS_LMP_RESPONSE_TIMEOUT							= 0X22, /* LMP Response Timeout */
+	HCI_STATUS_LMP_ERROR_TRANSACTION_COLLISION				= 0X23, /* LMP Error Transaction Collision */
+	HCI_STATUS_LMP_PDU_NOT_ALLOW							= 0X24, /* LMP PDU Not Allowed */
+	HCI_STATUS_ENCRYPTION_MODE_NOT_ALLOW					= 0X25, /* Encryption Mode Not Acceptable */
+	HCI_STATUS_LINK_KEY_CAN_NOT_CHANGE						= 0X26, /* Link Key Can Not be Changed */
+	HCI_STATUS_REQUEST_QOS_NOT_SUPPORT						= 0X27, /* Requested QoS Not Supported */
+	HCI_STATUS_INSTANT_PASSED								= 0X28, /* Instant Passed */
+	HCI_STATUS_PAIRING_UNIT_KEY_NOT_SUPPORT					= 0X29, /* Pairing With Unit Key Not Supported */
+	HCI_STATUS_DIFFERENT_TRANSACTION_COLLISION				= 0X2a, /* Different Transaction Collision */
+	HCI_STATUS_RESERVE_1										= 0X2b, /* Reserved */
+	HCI_STATUS_QOS_UNACCEPT_PARA							= 0X2c, /* QoS Unacceptable Parameter */
+	HCI_STATUS_QOS_REJECT										= 0X2d, /* QoS Rejected */
+	HCI_STATUS_CHNL_CLASSIFICATION_NOT_SUPPORT				= 0X2e, /* Channel Classification Not Supported */
+	HCI_STATUS_INSUFFICIENT_SECURITY							= 0X2f, /* Insufficient Security */
+	HCI_STATUS_PARA_OUT_OF_RANGE							= 0x30, /* Parameter Out Of Mandatory Range */
+	HCI_STATUS_RESERVE_2										= 0X31, /* Reserved */
+	HCI_STATUS_ROLE_SWITCH_PENDING							= 0X32, /* Role Switch Pending */
+	HCI_STATUS_RESERVE_3										= 0X33, /* Reserved */
+	HCI_STATUS_RESERVE_SOLT_VIOLATION						= 0X34, /* Reserved Slot Violation */
+	HCI_STATUS_ROLE_SWITCH_FAIL								= 0X35, /* Role Switch Failed */
+	HCI_STATUS_EXTEND_INQUIRY_RSP_TOO_LARGE				= 0X36, /* Extended Inquiry Response Too Large */
+	HCI_STATUS_SEC_SIMPLE_PAIRING_NOT_SUPPORT				= 0X37, /* Secure Simple Pairing Not Supported By Host. */
+	HCI_STATUS_HOST_BUSY_PAIRING								= 0X38, /* Host Busy - Pairing */
+	HCI_STATUS_CONNECT_REJ_NOT_SUIT_CHNL_FOUND			= 0X39, /* Connection Rejected due to No Suitable Channel Found */
+	HCI_STATUS_CONTROLLER_BUSY								= 0X3a /* CONTROLLER BUSY */
+} RTW_HCI_STATUS;
+
+#define HCI_EVENT_COMMAND_COMPLETE					0x0e
+
+#define OGF_EXTENSION									0X3f
+typedef enum HCI_EXTENSION_COMMANDS {
+	HCI_SET_ACL_LINK_DATA_FLOW_MODE				= 0x0010,
+	HCI_SET_ACL_LINK_STATUS							= 0x0020,
+	HCI_SET_SCO_LINK_STATUS							= 0x0030,
+	HCI_SET_RSSI_VALUE								= 0x0040,
+	HCI_SET_CURRENT_BLUETOOTH_STATUS				= 0x0041,
+
+	/* The following is for RTK8723 */
+	HCI_EXTENSION_VERSION_NOTIFY					= 0x0100,
+	HCI_LINK_STATUS_NOTIFY							= 0x0101,
+	HCI_BT_OPERATION_NOTIFY							= 0x0102,
+	HCI_ENABLE_WIFI_SCAN_NOTIFY						= 0x0103,
+	HCI_QUERY_RF_STATUS								= 0x0104,
+	HCI_BT_ABNORMAL_NOTIFY							= 0x0105,
+	HCI_BT_INFO_NOTIFY								= 0x0106,
+	HCI_BT_COEX_NOTIFY								= 0x0107,
+	HCI_BT_PATCH_VERSION_NOTIFY						= 0x0108,
+	HCI_BT_AFH_MAP_NOTIFY							= 0x0109,
+	HCI_BT_REGISTER_VALUE_NOTIFY					= 0x010a,
+
+	/* The following is for IVT */
+	HCI_WIFI_CURRENT_CHANNEL						= 0x0300,
+	HCI_WIFI_CURRENT_BANDWIDTH						= 0x0301,
+	HCI_WIFI_CONNECTION_STATUS						= 0x0302
+} RTW_HCI_EXT_CMD;
+
+#define HCI_EVENT_EXTENSION_RTK						0xfe
+typedef enum HCI_EXTENSION_EVENT_RTK {
+	HCI_EVENT_EXT_WIFI_SCAN_NOTIFY								= 0x01,
+	HCI_EVENT_EXT_WIFI_RF_STATUS_NOTIFY						= 0x02,
+	HCI_EVENT_EXT_BT_INFO_CONTROL								= 0x03,
+	HCI_EVENT_EXT_BT_COEX_CONTROL								= 0x04
+} RTW_HCI_EXT_EVENT;
+
+typedef enum _BT_TRAFFIC_MODE {
+	BT_MOTOR_EXT_BE		= 0x00, /* Best Effort. Default. for HCRP, PAN, SDP, RFCOMM-based profiles like FTP,OPP, SPP, DUN, etc. */
+	BT_MOTOR_EXT_GUL		= 0x01, /* Guaranteed Latency. This type of traffic is used e.g. for HID and AVRCP. */
+	BT_MOTOR_EXT_GUB		= 0X02, /* Guaranteed Bandwidth. */
+	BT_MOTOR_EXT_GULB	= 0X03  /* Guaranteed Latency and Bandwidth. for A2DP and VDP. */
+} BT_TRAFFIC_MODE;
+
+typedef enum _BT_TRAFFIC_MODE_PROFILE {
+	BT_PROFILE_NONE,
+	BT_PROFILE_A2DP,
+	BT_PROFILE_PAN	,
+	BT_PROFILE_HID,
+	BT_PROFILE_SCO
+} BT_TRAFFIC_MODE_PROFILE;
+
+typedef enum _HCI_EXT_BT_OPERATION {
+	HCI_BT_OP_NONE				= 0x0,
+	HCI_BT_OP_INQUIRY_START		= 0x1,
+	HCI_BT_OP_INQUIRY_FINISH		= 0x2,
+	HCI_BT_OP_PAGING_START		= 0x3,
+	HCI_BT_OP_PAGING_SUCCESS		= 0x4,
+	HCI_BT_OP_PAGING_UNSUCCESS	= 0x5,
+	HCI_BT_OP_PAIRING_START		= 0x6,
+	HCI_BT_OP_PAIRING_FINISH		= 0x7,
+	HCI_BT_OP_BT_DEV_ENABLE		= 0x8,
+	HCI_BT_OP_BT_DEV_DISABLE		= 0x9,
+	HCI_BT_OP_MAX
+} HCI_EXT_BT_OPERATION, *PHCI_EXT_BT_OPERATION;
+
+typedef struct _BT_MGNT {
+	BOOLEAN				bBTConnectInProgress;
+	BOOLEAN				bLogLinkInProgress;
+	BOOLEAN				bPhyLinkInProgress;
+	BOOLEAN				bPhyLinkInProgressStartLL;
+	u1Byte				BtCurrentPhyLinkhandle;
+	u2Byte				BtCurrentLogLinkhandle;
+	u1Byte				CurrentConnectEntryNum;
+	u1Byte				DisconnectEntryNum;
+	u1Byte				CurrentBTConnectionCnt;
+	BT_CONNECT_TYPE		BTCurrentConnectType;
+	BT_CONNECT_TYPE		BTReceiveConnectPkt;
+	u1Byte				BTAuthCount;
+	u1Byte				BTAsocCount;
+	BOOLEAN				bStartSendSupervisionPkt;
+	BOOLEAN				BtOperationOn;
+	BOOLEAN				BTNeedAMPStatusChg;
+	BOOLEAN				JoinerNeedSendAuth;
+	HCI_PHY_LINK_BSS_INFO	bssDesc;
+	HCI_EXT_CONFIG		ExtConfig;
+	BOOLEAN				bNeedNotifyAMPNoCap;
+	BOOLEAN				bCreateSpportQos;
+	BOOLEAN				bSupportProfile;
+	u1Byte				BTChannel;
+	BOOLEAN				CheckChnlIsSuit;
+	BOOLEAN				bBtScan;
+	BOOLEAN				btLogoTest;
+	BOOLEAN				bRfStatusNotified;
+	BOOLEAN				bBtRsvedPageDownload;
+} BT_MGNT, *PBT_MGNT;
+
+struct bt_coex_info {
+	/* For Kernel Socket */
+	struct socket *udpsock;
+	struct sockaddr_in wifi_sockaddr; /*wifi socket*/
+	struct sockaddr_in bt_sockaddr;/* BT socket */
+	struct sock *sk_store;/*back up socket for UDP RX int*/
+
+	/* store which socket is OK */
+	u8 sock_open;
+
+	u8 BT_attend;
+	u8 is_exist; /* socket exist */
+	BT_MGNT BtMgnt;
+	struct workqueue_struct *btcoex_wq;
+	struct delayed_work recvmsg_work;
+};
+#endif /* CONFIG_BT_COEXIST_SOCKET_TRX */
+
+#define	PACKET_NORMAL			0
+#define	PACKET_DHCP				1
+#define	PACKET_ARP				2
+#define	PACKET_EAPOL			3
+
+void rtw_btcoex_Initialize(PADAPTER);
+void rtw_btcoex_PowerOnSetting(PADAPTER padapter);
+void rtw_btcoex_AntInfoSetting(PADAPTER padapter);
+void rtw_btcoex_PowerOffSetting(PADAPTER padapter);
+void rtw_btcoex_PreLoadFirmware(PADAPTER padapter);
+void rtw_btcoex_HAL_Initialize(PADAPTER padapter, u8 bWifiOnly);
+void rtw_btcoex_IpsNotify(PADAPTER, u8 type);
+void rtw_btcoex_LpsNotify(PADAPTER, u8 type);
+void rtw_btcoex_ScanNotify(PADAPTER, u8 type);
+void rtw_btcoex_ConnectNotify(PADAPTER, u8 action);
+void rtw_btcoex_MediaStatusNotify(PADAPTER, u8 mediaStatus);
+void rtw_btcoex_SpecialPacketNotify(PADAPTER, u8 pktType);
+void rtw_btcoex_IQKNotify(PADAPTER padapter, u8 state);
+void rtw_btcoex_BtInfoNotify(PADAPTER, u8 length, u8 *tmpBuf);
+void rtw_btcoex_BtMpRptNotify(PADAPTER, u8 length, u8 *tmpBuf);
+void rtw_btcoex_SuspendNotify(PADAPTER, u8 state);
+void rtw_btcoex_HaltNotify(PADAPTER);
+void rtw_btcoex_switchband_notify(u8 under_scan, u8 band_type);
+void rtw_btcoex_WlFwDbgInfoNotify(PADAPTER padapter, u8* tmpBuf, u8 length);
+void rtw_btcoex_rx_rate_change_notify(PADAPTER padapter, u8 is_data_frame, u8 rate_id);
+void rtw_btcoex_SwitchBtTRxMask(PADAPTER);
+void rtw_btcoex_Switch(PADAPTER, u8 enable);
+u8 rtw_btcoex_IsBtDisabled(PADAPTER);
+void rtw_btcoex_Handler(PADAPTER);
+s32 rtw_btcoex_IsBTCoexRejectAMPDU(PADAPTER padapter);
+s32 rtw_btcoex_IsBTCoexCtrlAMPDUSize(PADAPTER);
+u32 rtw_btcoex_GetAMPDUSize(PADAPTER);
+void rtw_btcoex_SetManualControl(PADAPTER, u8 bmanual);
+u8 rtw_btcoex_1Ant(PADAPTER);
+u8 rtw_btcoex_IsBtControlLps(PADAPTER);
+u8 rtw_btcoex_IsLpsOn(PADAPTER);
+u8 rtw_btcoex_RpwmVal(PADAPTER);
+u8 rtw_btcoex_LpsVal(PADAPTER);
+u32 rtw_btcoex_GetRaMask(PADAPTER);
+void rtw_btcoex_RecordPwrMode(PADAPTER, u8 *pCmdBuf, u8 cmdLen);
+void rtw_btcoex_DisplayBtCoexInfo(PADAPTER, u8 *pbuf, u32 bufsize);
+void rtw_btcoex_SetDBG(PADAPTER, u32 *pDbgModule);
+u32 rtw_btcoex_GetDBG(PADAPTER, u8 *pStrBuf, u32 bufSize);
+u8 rtw_btcoex_IncreaseScanDeviceNum(PADAPTER);
+u8 rtw_btcoex_IsBtLinkExist(PADAPTER);
+void rtw_btcoex_pta_off_on_notify(PADAPTER padapter, u8 bBTON);
+
+#ifdef CONFIG_RF4CE_COEXIST
+void rtw_btcoex_SetRf4ceLinkState(PADAPTER padapter, u8 state);
+u8 rtw_btcoex_GetRf4ceLinkState(PADAPTER padapter);
+#endif
+
+#ifdef CONFIG_BT_COEXIST_SOCKET_TRX
+void rtw_btcoex_SetBtPatchVersion(PADAPTER padapter, u16 btHciVer, u16 btPatchVer);
+void rtw_btcoex_SetHciVersion(PADAPTER  padapter, u16 hciVersion);
+void rtw_btcoex_StackUpdateProfileInfo(void);
+void rtw_btcoex_init_socket(_adapter *padapter);
+void rtw_btcoex_close_socket(_adapter *padapter);
+void rtw_btcoex_dump_tx_msg(u8 *tx_msg, u8 len, u8 *msg_name);
+u8 rtw_btcoex_sendmsgbysocket(_adapter *padapter, u8 *msg, u8 msg_size, bool force);
+u8 rtw_btcoex_create_kernel_socket(_adapter *padapter);
+void rtw_btcoex_close_kernel_socket(_adapter *padapter);
+void rtw_btcoex_recvmsgbysocket(void *data);
+u16 rtw_btcoex_parse_recv_data(u8 *msg, u8 msg_size);
+u8 rtw_btcoex_btinfo_cmd(PADAPTER padapter, u8 *pbuf, u16 length);
+void rtw_btcoex_parse_hci_cmd(_adapter *padapter, u8 *cmd, u16 len);
+void rtw_btcoex_SendEventExtBtCoexControl(PADAPTER Adapter, u8 bNeedDbgRsp, u8 dataLen, void *pData);
+void rtw_btcoex_SendEventExtBtInfoControl(PADAPTER Adapter, u8 dataLen, void *pData);
+void rtw_btcoex_SendScanNotify(PADAPTER padapter, u8 scanType);
+#define BT_SendEventExtBtCoexControl(Adapter, bNeedDbgRsp, dataLen, pData) rtw_btcoex_SendEventExtBtCoexControl(Adapter, bNeedDbgRsp, dataLen, pData)
+#define BT_SendEventExtBtInfoControl(Adapter, dataLen, pData) rtw_btcoex_SendEventExtBtInfoControl(Adapter, dataLen, pData)
+#endif /* CONFIG_BT_COEXIST_SOCKET_TRX */
+u16 rtw_btcoex_btreg_read(PADAPTER padapter, u8 type, u16 addr, u32 *data);
+u16 rtw_btcoex_btreg_write(PADAPTER padapter, u8 type, u16 addr, u16 val);
+u8 rtw_btcoex_get_bt_coexist(PADAPTER padapter);
+u8 rtw_btcoex_get_chip_type(PADAPTER padapter);
+u8 rtw_btcoex_get_pg_ant_num(PADAPTER padapter);
+u8 rtw_btcoex_get_pg_single_ant_path(PADAPTER padapter);
+u8 rtw_btcoex_get_pg_rfe_type(PADAPTER padapter);
+u8 rtw_btcoex_is_tfbga_package_type(PADAPTER padapter);
+u8 rtw_btcoex_get_ant_div_cfg(PADAPTER padapter);
+
+/* ==================================================
+ * Below Functions are called by BT-Coex
+ * ================================================== */
+void rtw_btcoex_rx_ampdu_apply(PADAPTER padapter);
+void rtw_btcoex_LPS_Enter(PADAPTER padapter);
+u8 rtw_btcoex_LPS_Leave(PADAPTER padapter);
+
+#endif /* __RTW_BTCOEX_H__ */
+#endif /* CONFIG_BT_COEXIST */
+
+void rtw_btcoex_set_ant_info(PADAPTER padapter);
+
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/include/rtw_btcoex_wifionly.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/rtw_btcoex_wifionly.h
--- linux-5.6.3/3rdparty/rtl8821ce/include/rtw_btcoex_wifionly.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/rtw_btcoex_wifionly.h	2020-04-10 16:35:06.851661701 +0300
@@ -0,0 +1,24 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2013 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#ifndef __RTW_BTCOEX_WIFIONLY_H__
+#define __RTW_BTCOEX_WIFIONLY_H__
+
+void rtw_btcoex_wifionly_switchband_notify(PADAPTER padapter);
+void rtw_btcoex_wifionly_scan_notify(PADAPTER padapter);
+void rtw_btcoex_wifionly_connect_notify(PADAPTER padapter);
+void rtw_btcoex_wifionly_hw_config(PADAPTER padapter);
+void rtw_btcoex_wifionly_initialize(PADAPTER padapter);
+void rtw_btcoex_wifionly_AntInfoSetting(PADAPTER padapter);
+#endif
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/include/rtw_bt_mp.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/rtw_bt_mp.h
--- linux-5.6.3/3rdparty/rtl8821ce/include/rtw_bt_mp.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/rtw_bt_mp.h	2020-04-10 16:35:06.851661701 +0300
@@ -0,0 +1,288 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+
+#ifndef __RTW_BT_MP_H
+#define __RTW_BT_MP_H
+
+
+#if (MP_DRIVER == 1)
+
+#pragma pack(1)
+
+/* definition for BT_UP_OP_BT_READY */
+#define	MP_BT_NOT_READY						0
+#define	MP_BT_READY							1
+
+/* definition for BT_UP_OP_BT_SET_MODE */
+typedef enum _MP_BT_MODE {
+	MP_BT_MODE_RF_TXRX_TEST_MODE							= 0,
+	MP_BT_MODE_BT20_DUT_TEST_MODE							= 1,
+	MP_BT_MODE_BT40_DIRECT_TEST_MODE						= 2,
+	MP_BT_MODE_CONNECT_TEST_MODE							= 3,
+	MP_BT_MODE_MAX
+} MP_BT_MODE, *PMP_BT_MODE;
+
+
+/* definition for BT_UP_OP_BT_SET_TX_RX_PARAMETER */
+typedef struct _BT_TXRX_PARAMETERS {
+	u1Byte		txrxChannel;
+	u4Byte		txrxTxPktCnt;
+	u1Byte		txrxTxPktInterval;
+	u1Byte		txrxPayloadType;
+	u1Byte		txrxPktType;
+	u2Byte		txrxPayloadLen;
+	u4Byte		txrxPktHeader;
+	u1Byte		txrxWhitenCoeff;
+	u1Byte		txrxBdaddr[6];
+	u1Byte		txrxTxGainIndex;
+} BT_TXRX_PARAMETERS, *PBT_TXRX_PARAMETERS;
+
+/* txrxPktType */
+typedef enum _MP_BT_PKT_TYPE {
+	MP_BT_PKT_DH1							= 0,
+	MP_BT_PKT_DH3							= 1,
+	MP_BT_PKT_DH5							= 2,
+	MP_BT_PKT_2DH1							= 3,
+	MP_BT_PKT_2DH3							= 4,
+	MP_BT_PKT_2DH5							= 5,
+	MP_BT_PKT_3DH1							= 6,
+	MP_BT_PKT_3DH3							= 7,
+	MP_BT_PKT_3DH5							= 8,
+	MP_BT_PKT_LE							= 9,
+	MP_BT_PKT_MAX
+} MP_BT_PKT_TYPE, *PMP_BT_PKT_TYPE;
+/* txrxPayloadType */
+typedef enum _MP_BT_PAYLOAD_TYPE {
+	MP_BT_PAYLOAD_01010101					= 0,
+	MP_BT_PAYLOAD_ALL_1						= 1,
+	MP_BT_PAYLOAD_ALL_0						= 2,
+	MP_BT_PAYLOAD_11110000					= 3,
+	MP_BT_PAYLOAD_PRBS9						= 4,
+	MP_BT_PAYLOAD_MAX						= 8,
+} MP_BT_PAYLOAD_TYPE, *PMP_BT_PAYLOAD_TYPE;
+
+
+/* definition for BT_UP_OP_BT_TEST_CTRL */
+typedef enum _MP_BT_TEST_CTRL {
+	MP_BT_TEST_STOP_ALL_TESTS						= 0,
+	MP_BT_TEST_START_RX_TEST						= 1,
+	MP_BT_TEST_START_PACKET_TX_TEST					= 2,
+	MP_BT_TEST_START_CONTINUOUS_TX_TEST			= 3,
+	MP_BT_TEST_START_INQUIRY_SCAN_TEST				= 4,
+	MP_BT_TEST_START_PAGE_SCAN_TEST					= 5,
+	MP_BT_TEST_START_INQUIRY_PAGE_SCAN_TEST			= 6,
+	MP_BT_TEST_START_LEGACY_CONNECT_TEST			= 7,
+	MP_BT_TEST_START_LE_CONNECT_TEST_INITIATOR		= 8,
+	MP_BT_TEST_START_LE_CONNECT_TEST_ADVERTISER	= 9,
+	MP_BT_TEST_MAX
+} MP_BT_TEST_CTRL, *PMP_BT_TEST_CTRL;
+
+
+typedef enum _RTL_EXT_C2H_EVT {
+	EXT_C2H_WIFI_FW_ACTIVE_RSP = 0,
+	EXT_C2H_TRIG_BY_BT_FW = 1,
+	MAX_EXT_C2HEVENT
+} RTL_EXT_C2H_EVT;
+
+/* OP codes definition between the user layer and driver */
+typedef enum _BT_CTRL_OPCODE_UPPER {
+	BT_UP_OP_BT_READY										= 0x00,
+	BT_UP_OP_BT_SET_MODE									= 0x01,
+	BT_UP_OP_BT_SET_TX_RX_PARAMETER						= 0x02,
+	BT_UP_OP_BT_SET_GENERAL								= 0x03,
+	BT_UP_OP_BT_GET_GENERAL								= 0x04,
+	BT_UP_OP_BT_TEST_CTRL									= 0x05,
+	BT_UP_OP_TEST_BT										= 0x06,
+	BT_UP_OP_MAX
+} BT_CTRL_OPCODE_UPPER, *PBT_CTRL_OPCODE_UPPER;
+
+
+typedef enum _BT_SET_GENERAL {
+	BT_GSET_REG											= 0x00,
+	BT_GSET_RESET											= 0x01,
+	BT_GSET_TARGET_BD_ADDR									= 0x02,
+	BT_GSET_TX_PWR_FINETUNE								= 0x03,
+	BT_SET_TRACKING_INTERVAL								= 0x04,
+	BT_SET_THERMAL_METER									= 0x05,
+	BT_ENABLE_CFO_TRACKING									= 0x06,
+	BT_GSET_UPDATE_BT_PATCH								= 0x07,
+	BT_GSET_MAX
+} BT_SET_GENERAL, *PBT_SET_GENERAL;
+
+typedef enum _BT_GET_GENERAL {
+	BT_GGET_REG											= 0x00,
+	BT_GGET_STATUS											= 0x01,
+	BT_GGET_REPORT											= 0x02,
+	BT_GGET_AFH_MAP										= 0x03,
+	BT_GGET_AFH_STATUS										= 0x04,
+	BT_GGET_MAX
+} BT_GET_GENERAL, *PBT_GET_GENERAL;
+
+/* definition for BT_UP_OP_BT_SET_GENERAL */
+typedef enum _BT_REG_TYPE {
+	BT_REG_RF								= 0,
+	BT_REG_MODEM							= 1,
+	BT_REG_BLUEWIZE						= 2,
+	BT_REG_VENDOR							= 3,
+	BT_REG_LE								= 4,
+	BT_REG_MAX
+} BT_REG_TYPE, *PBT_REG_TYPE;
+
+/* definition for BT_LO_OP_GET_AFH_MAP */
+typedef enum _BT_AFH_MAP_TYPE {
+	BT_AFH_MAP_RESULT						= 0,
+	BT_AFH_MAP_WIFI_PSD_ONLY				= 1,
+	BT_AFH_MAP_WIFI_CH_BW_ONLY				= 2,
+	BT_AFH_MAP_BT_PSD_ONLY					= 3,
+	BT_AFH_MAP_HOST_CLASSIFICATION_ONLY	= 4,
+	BT_AFH_MAP_MAX
+} BT_AFH_MAP_TYPE, *PBT_AFH_MAP_TYPE;
+
+/* definition for BT_UP_OP_BT_GET_GENERAL */
+typedef enum _BT_REPORT_TYPE {
+	BT_REPORT_RX_PACKET_CNT				= 0,
+	BT_REPORT_RX_ERROR_BITS				= 1,
+	BT_REPORT_RSSI							= 2,
+	BT_REPORT_CFO_HDR_QUALITY				= 3,
+	BT_REPORT_CONNECT_TARGET_BD_ADDR		= 4,
+	BT_REPORT_MAX
+} BT_REPORT_TYPE, *PBT_REPORT_TYPE;
+
+VOID
+MPTBT_Test(
+	IN	PADAPTER	Adapter,
+	IN	u1Byte		opCode,
+	IN	u1Byte		byte1,
+	IN	u1Byte		byte2,
+	IN	u1Byte		byte3
+);
+
+NDIS_STATUS
+MPTBT_SendOidBT(
+	IN	PADAPTER		pAdapter,
+	IN	PVOID			InformationBuffer,
+	IN	ULONG			InformationBufferLength,
+	OUT	PULONG			BytesRead,
+	OUT	PULONG			BytesNeeded
+);
+
+VOID
+MPTBT_FwC2hBtMpCtrl(
+	PADAPTER	Adapter,
+	pu1Byte	tmpBuf,
+	u1Byte		length
+);
+
+void MPh2c_timeout_handle(void *FunctionContext);
+
+VOID mptbt_BtControlProcess(
+	PADAPTER	Adapter,
+	PVOID		pInBuf
+);
+
+#define	BT_H2C_MAX_RETRY								1
+#define	BT_MAX_C2H_LEN								20
+
+typedef struct _BT_REQ_CMD {
+	UCHAR       opCodeVer;
+	UCHAR       OpCode;
+	USHORT      paraLength;
+	UCHAR       pParamStart[100];
+} BT_REQ_CMD, *PBT_REQ_CMD;
+
+typedef struct _BT_RSP_CMD {
+	USHORT      status;
+	USHORT      paraLength;
+	UCHAR       pParamStart[100];
+} BT_RSP_CMD, *PBT_RSP_CMD;
+
+
+typedef struct _BT_H2C {
+	u1Byte	opCodeVer:4;
+	u1Byte	reqNum:4;
+	u1Byte	opCode;
+	u1Byte	buf[100];
+} BT_H2C, *PBT_H2C;
+
+
+
+typedef struct _BT_EXT_C2H {
+	u1Byte	extendId;
+	u1Byte	statusCode:4;
+	u1Byte	retLen:4;
+	u1Byte	opCodeVer:4;
+	u1Byte	reqNum:4;
+	u1Byte	buf[100];
+} BT_EXT_C2H, *PBT_EXT_C2H;
+
+
+typedef enum _BT_OPCODE_STATUS {
+	BT_OP_STATUS_SUCCESS									= 0x00, /* Success */
+	BT_OP_STATUS_VERSION_MISMATCH							= 0x01,
+	BT_OP_STATUS_UNKNOWN_OPCODE								= 0x02,
+	BT_OP_STATUS_ERROR_PARAMETER							= 0x03,
+	BT_OP_STATUS_MAX
+} BT_OPCODE_STATUS, *PBT_OPCODE_STATUS;
+
+
+
+/* OP codes definition between driver and bt fw */
+typedef enum _BT_CTRL_OPCODE_LOWER {
+	BT_LO_OP_GET_BT_VERSION									= 0x00,
+	BT_LO_OP_RESET												= 0x01,
+	BT_LO_OP_TEST_CTRL											= 0x02,
+	BT_LO_OP_SET_BT_MODE										= 0x03,
+	BT_LO_OP_SET_CHNL_TX_GAIN									= 0x04,
+	BT_LO_OP_SET_PKT_TYPE_LEN									= 0x05,
+	BT_LO_OP_SET_PKT_CNT_L_PL_TYPE								= 0x06,
+	BT_LO_OP_SET_PKT_CNT_H_PKT_INTV							= 0x07,
+	BT_LO_OP_SET_PKT_HEADER									= 0x08,
+	BT_LO_OP_SET_WHITENCOEFF									= 0x09,
+	BT_LO_OP_SET_BD_ADDR_L										= 0x0a,
+	BT_LO_OP_SET_BD_ADDR_H										= 0x0b,
+	BT_LO_OP_WRITE_REG_ADDR									= 0x0c,
+	BT_LO_OP_WRITE_REG_VALUE									= 0x0d,
+	BT_LO_OP_GET_BT_STATUS										= 0x0e,
+	BT_LO_OP_GET_BD_ADDR_L										= 0x0f,
+	BT_LO_OP_GET_BD_ADDR_H										= 0x10,
+	BT_LO_OP_READ_REG											= 0x11,
+	BT_LO_OP_SET_TARGET_BD_ADDR_L								= 0x12,
+	BT_LO_OP_SET_TARGET_BD_ADDR_H								= 0x13,
+	BT_LO_OP_SET_TX_POWER_CALIBRATION							= 0x14,
+	BT_LO_OP_GET_RX_PKT_CNT_L									= 0x15,
+	BT_LO_OP_GET_RX_PKT_CNT_H									= 0x16,
+	BT_LO_OP_GET_RX_ERROR_BITS_L								= 0x17,
+	BT_LO_OP_GET_RX_ERROR_BITS_H								= 0x18,
+	BT_LO_OP_GET_RSSI											= 0x19,
+	BT_LO_OP_GET_CFO_HDR_QUALITY_L								= 0x1a,
+	BT_LO_OP_GET_CFO_HDR_QUALITY_H								= 0x1b,
+	BT_LO_OP_GET_TARGET_BD_ADDR_L								= 0x1c,
+	BT_LO_OP_GET_TARGET_BD_ADDR_H								= 0x1d,
+	BT_LO_OP_GET_AFH_MAP_L										= 0x1e,
+	BT_LO_OP_GET_AFH_MAP_M										= 0x1f,
+	BT_LO_OP_GET_AFH_MAP_H										= 0x20,
+	BT_LO_OP_GET_AFH_STATUS									= 0x21,
+	BT_LO_OP_SET_TRACKING_INTERVAL								= 0x22,
+	BT_LO_OP_SET_THERMAL_METER									= 0x23,
+	BT_LO_OP_ENABLE_CFO_TRACKING								= 0x24,
+	BT_LO_OP_MAX
+} BT_CTRL_OPCODE_LOWER, *PBT_CTRL_OPCODE_LOWER;
+
+
+
+
+#endif  /* #if(MP_DRIVER == 1) */
+
+#endif /*  #ifndef __INC_MPT_BT_H */
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/include/rtw_byteorder.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/rtw_byteorder.h
--- linux-5.6.3/3rdparty/rtl8821ce/include/rtw_byteorder.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/rtw_byteorder.h	2020-04-10 16:35:06.851661701 +0300
@@ -0,0 +1,33 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#ifndef _RTL871X_BYTEORDER_H_
+#define _RTL871X_BYTEORDER_H_
+
+
+#if defined(CONFIG_LITTLE_ENDIAN) && defined (CONFIG_BIG_ENDIAN)
+	#error "Shall be CONFIG_LITTLE_ENDIAN or CONFIG_BIG_ENDIAN, but not both!\n"
+#endif
+
+#if defined(CONFIG_LITTLE_ENDIAN)
+	#ifndef CONFIG_PLATFORM_MSTAR389
+		#include <byteorder/little_endian.h>
+	#endif
+#elif defined (CONFIG_BIG_ENDIAN)
+	#include <byteorder/big_endian.h>
+#else
+	#  error "Must be LITTLE/BIG Endian Host"
+#endif
+
+#endif /* _RTL871X_BYTEORDER_H_ */
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/include/rtw_cmd.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/rtw_cmd.h
--- linux-5.6.3/3rdparty/rtl8821ce/include/rtw_cmd.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/rtw_cmd.h	2020-04-10 16:35:06.851661701 +0300
@@ -0,0 +1,1328 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#ifndef __RTW_CMD_H_
+#define __RTW_CMD_H_
+
+
+#define C2H_MEM_SZ (16*1024)
+
+#ifndef CONFIG_RTL8711FW
+
+#define FREE_CMDOBJ_SZ	128
+
+#define MAX_CMDSZ	1024
+#define MAX_RSPSZ	512
+#define MAX_EVTSZ	1024
+
+#ifdef PLATFORM_OS_CE
+	#define CMDBUFF_ALIGN_SZ 4
+#else
+	#define CMDBUFF_ALIGN_SZ 512
+#endif
+
+struct cmd_obj {
+	_adapter *padapter;
+	u16	cmdcode;
+	u8	res;
+	u8	*parmbuf;
+	u32	cmdsz;
+	u8	*rsp;
+	u32	rspsz;
+	struct submit_ctx *sctx;
+	u8 no_io;
+	/* _sema 	cmd_sem; */
+	_list	list;
+};
+
+/* cmd flags */
+enum {
+	RTW_CMDF_DIRECTLY = BIT0,
+	RTW_CMDF_WAIT_ACK = BIT1,
+};
+
+struct cmd_priv {
+	_sema	cmd_queue_sema;
+	/* _sema	cmd_done_sema; */
+	_sema	start_cmdthread_sema;
+
+	_queue	cmd_queue;
+	u8	cmd_seq;
+	u8	*cmd_buf;	/* shall be non-paged, and 4 bytes aligned */
+	u8	*cmd_allocated_buf;
+	u8	*rsp_buf;	/* shall be non-paged, and 4 bytes aligned		 */
+	u8	*rsp_allocated_buf;
+	u32	cmd_issued_cnt;
+	u32	cmd_done_cnt;
+	u32	rsp_cnt;
+	ATOMIC_T cmdthd_running;
+	/* u8 cmdthd_running; */
+
+	_adapter *padapter;
+	_mutex sctx_mutex;
+};
+
+#ifdef CONFIG_EVENT_THREAD_MODE
+struct evt_obj {
+	u16	evtcode;
+	u8	res;
+	u8	*parmbuf;
+	u32	evtsz;
+	_list	list;
+};
+#endif
+
+struct	evt_priv {
+#ifdef CONFIG_EVENT_THREAD_MODE
+	_sema	evt_notify;
+
+	_queue	evt_queue;
+#endif
+
+#ifdef CONFIG_FW_C2H_REG
+	#define CONFIG_C2H_WK
+#endif
+
+#ifdef CONFIG_C2H_WK
+	_workitem c2h_wk;
+	bool c2h_wk_alive;
+	struct rtw_cbuf *c2h_queue;
+	#define C2H_QUEUE_MAX_LEN 10
+#endif
+
+#ifdef CONFIG_H2CLBK
+	_sema	lbkevt_done;
+	u8	lbkevt_limit;
+	u8	lbkevt_num;
+	u8	*cmdevt_parm;
+#endif
+	ATOMIC_T event_seq;
+	u8	*evt_buf;	/* shall be non-paged, and 4 bytes aligned		 */
+	u8	*evt_allocated_buf;
+	u32	evt_done_cnt;
+#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
+	u8	*c2h_mem;
+	u8	*allocated_c2h_mem;
+#ifdef PLATFORM_OS_XP
+	PMDL	pc2h_mdl;
+#endif
+#endif
+
+};
+
+#define init_h2fwcmd_w_parm_no_rsp(pcmd, pparm, code) \
+	do {\
+		_rtw_init_listhead(&pcmd->list);\
+		pcmd->cmdcode = code;\
+		pcmd->parmbuf = (u8 *)(pparm);\
+		pcmd->cmdsz = sizeof (*pparm);\
+		pcmd->rsp = NULL;\
+		pcmd->rspsz = 0;\
+	} while (0)
+
+#define init_h2fwcmd_w_parm_no_parm_rsp(pcmd, code) \
+	do {\
+		_rtw_init_listhead(&pcmd->list);\
+		pcmd->cmdcode = code;\
+		pcmd->parmbuf = NULL;\
+		pcmd->cmdsz = 0;\
+		pcmd->rsp = NULL;\
+		pcmd->rspsz = 0;\
+	} while (0)
+
+struct P2P_PS_Offload_t {
+	u8 Offload_En:1;
+	u8 role:1; /* 1: Owner, 0: Client */
+	u8 CTWindow_En:1;
+	u8 NoA0_En:1;
+	u8 NoA1_En:1;
+	u8 AllStaSleep:1; /* Only valid in Owner */
+	u8 discovery:1;
+	u8 rsvd:1;
+};
+
+struct P2P_PS_CTWPeriod_t {
+	u8 CTWPeriod;	/* TU */
+};
+
+#ifdef CONFIG_P2P_WOWLAN
+
+struct P2P_WoWlan_Offload_t {
+	u8 Disconnect_Wkup_Drv:1;
+	u8 role:2;
+	u8 Wps_Config[2];
+};
+
+#endif /* CONFIG_P2P_WOWLAN */
+
+extern u32 rtw_enqueue_cmd(struct cmd_priv *pcmdpriv, struct cmd_obj *obj);
+extern struct cmd_obj *rtw_dequeue_cmd(struct cmd_priv *pcmdpriv);
+extern void rtw_free_cmd_obj(struct cmd_obj *pcmd);
+
+#ifdef CONFIG_EVENT_THREAD_MODE
+extern u32 rtw_enqueue_evt(struct evt_priv *pevtpriv, struct evt_obj *obj);
+extern struct evt_obj *rtw_dequeue_evt(_queue *queue);
+extern void rtw_free_evt_obj(struct evt_obj *pcmd);
+#endif
+
+void rtw_stop_cmd_thread(_adapter *adapter);
+thread_return rtw_cmd_thread(thread_context context);
+
+extern u32 rtw_init_cmd_priv(struct cmd_priv *pcmdpriv);
+extern void rtw_free_cmd_priv(struct cmd_priv *pcmdpriv);
+
+extern u32 rtw_init_evt_priv(struct evt_priv *pevtpriv);
+extern void rtw_free_evt_priv(struct evt_priv *pevtpriv);
+extern void rtw_cmd_clr_isr(struct cmd_priv *pcmdpriv);
+extern void rtw_evt_notify_isr(struct evt_priv *pevtpriv);
+#ifdef CONFIG_P2P
+u8 p2p_protocol_wk_cmd(_adapter *padapter, int intCmdType);
+
+#ifdef CONFIG_IOCTL_CFG80211
+struct p2p_roch_parm {
+	u64 cookie;
+	struct wireless_dev *wdev;
+	struct ieee80211_channel ch;
+	enum nl80211_channel_type ch_type;
+	unsigned int duration;
+};
+
+u8 p2p_roch_cmd(_adapter *adapter
+	, u64 cookie, struct wireless_dev *wdev
+	, struct ieee80211_channel *ch, enum nl80211_channel_type ch_type
+	, unsigned int duration
+	, u8 flags
+);
+u8 p2p_cancel_roch_cmd(_adapter *adapter, u64 cookie, struct wireless_dev *wdev, u8 flags);
+
+#endif /* CONFIG_IOCTL_CFG80211 */
+#endif /* CONFIG_P2P */
+
+#ifdef CONFIG_IOCTL_CFG80211 
+u8 rtw_mgnt_tx_cmd(_adapter *adapter, u8 tx_ch, u8 no_cck, const u8 *buf, size_t len, int wait_ack, u8 flags);
+struct mgnt_tx_parm {
+	u8 tx_ch;
+	u8 no_cck;
+	const u8 *buf;
+	size_t len;
+	int wait_ack;
+};
+#endif
+
+#else
+/* #include <ieee80211.h> */
+#endif	/* CONFIG_RTL8711FW */
+
+enum rtw_drvextra_cmd_id {
+	NONE_WK_CID,
+	STA_MSTATUS_RPT_WK_CID,
+	DYNAMIC_CHK_WK_CID,
+	DM_CTRL_WK_CID,
+	PBC_POLLING_WK_CID,
+	POWER_SAVING_CTRL_WK_CID,/* IPS,AUTOSuspend */
+	LPS_CTRL_WK_CID,
+	ANT_SELECT_WK_CID,
+	P2P_PS_WK_CID,
+	P2P_PROTO_WK_CID,
+	CHECK_HIQ_WK_CID,/* for softap mode, check hi queue if empty */
+	INTEl_WIDI_WK_CID,
+	C2H_WK_CID,
+	RTP_TIMER_CFG_WK_CID,
+	RESET_SECURITYPRIV, /* add for CONFIG_IEEE80211W, none 11w also can use */
+	FREE_ASSOC_RESOURCES, /* add for CONFIG_IEEE80211W, none 11w also can use */
+	DM_IN_LPS_WK_CID,
+	DM_RA_MSK_WK_CID, /* add for STA update RAMask when bandwith change. */
+	BEAMFORMING_WK_CID,
+	LPS_CHANGE_DTIM_CID,
+	BTINFO_WK_CID,
+	DFS_RADAR_DETECT_WK_CID,
+	DFS_RADAR_DETECT_EN_DEC_WK_CID,
+	SESSION_TRACKER_WK_CID,
+	EN_HW_UPDATE_TSF_WK_CID,
+	PERIOD_TSF_UPDATE_END_WK_CID,
+	TEST_H2C_CID,
+	MP_CMD_WK_CID,
+	CUSTOMER_STR_WK_CID,
+#ifdef CONFIG_RTW_REPEATER_SON
+	RSON_SCAN_WK_CID,
+#endif
+	MGNT_TX_WK_CID,
+#ifdef CONFIG_MCC_MODE
+	MCC_SET_DURATION_WK_CID,
+#endif /* CONFIG_MCC_MODE */
+	REQ_PER_CMD_WK_CID,
+	MAX_WK_CID
+};
+
+enum LPS_CTRL_TYPE {
+	LPS_CTRL_SCAN = 0,
+	LPS_CTRL_JOINBSS = 1,
+	LPS_CTRL_CONNECT = 2,
+	LPS_CTRL_DISCONNECT = 3,
+	LPS_CTRL_SPECIAL_PACKET = 4,
+	LPS_CTRL_LEAVE = 5,
+	LPS_CTRL_TRAFFIC_BUSY = 6,
+	LPS_CTRL_TX_TRAFFIC_LEAVE = 7,
+	LPS_CTRL_RX_TRAFFIC_LEAVE = 8,
+	LPS_CTRL_ENTER = 9,
+	LPS_CTRL_LEAVE_CFG80211_PWRMGMT = 10,
+};
+
+enum STAKEY_TYPE {
+	GROUP_KEY		= 0,
+	UNICAST_KEY		= 1,
+	TDLS_KEY		= 2,
+};
+
+enum RFINTFS {
+	SWSI,
+	HWSI,
+	HWPI,
+};
+
+/*
+Caller Mode: Infra, Ad-HoC(C)
+
+Notes: To enter USB suspend mode
+
+Command Mode
+
+*/
+struct usb_suspend_parm {
+	u32 action;/* 1: sleep, 0:resume */
+};
+
+/*
+Caller Mode: Infra, Ad-HoC
+
+Notes: To join a known BSS.
+
+Command-Event Mode
+
+*/
+
+/*
+Caller Mode: Infra, Ad-Hoc
+
+Notes: To join the specified bss
+
+Command Event Mode
+
+*/
+struct joinbss_parm {
+	WLAN_BSSID_EX network;
+};
+
+/*
+Caller Mode: Infra, Ad-HoC(C)
+
+Notes: To disconnect the current associated BSS
+
+Command Mode
+
+*/
+struct disconnect_parm {
+	u32 deauth_timeout_ms;
+};
+
+/*
+Caller Mode: AP, Ad-HoC(M)
+
+Notes: To create a BSS
+
+Command Mode
+*/
+struct createbss_parm {
+	bool adhoc;
+
+	/* used by AP/Mesh mode now */
+	u8 ifbmp;
+	u8 excl_ifbmp;
+	s16 req_ch;
+	s8 req_bw;
+	s8 req_offset;
+};
+
+#if 0
+/* Caller Mode: AP, Ad-HoC, Infra */
+/* Notes: To set the NIC mode of RTL8711 */
+/* Command Mode */
+/* The definition of mode: */
+
+#define IW_MODE_AUTO	0	/*  Let the driver decides which AP to join */
+#define IW_MODE_ADHOC	1	/*  Single cell network (Ad-Hoc Clients) */
+#define IW_MODE_INFRA	2	/*  Multi cell network, roaming, .. */
+#define IW_MODE_MASTER	3	/*  Synchronisation master or Access Point */
+#define IW_MODE_REPEAT	4	/*  Wireless Repeater (forwarder) */
+#define IW_MODE_SECOND	5	/*  Secondary master/repeater (backup) */
+#define IW_MODE_MONITOR	6	/*  Passive monitor (listen only) */
+#endif
+
+struct	setopmode_parm {
+	u8	mode;
+	u8	rsvd[3];
+};
+
+/*
+Caller Mode: AP, Ad-HoC, Infra
+
+Notes: To ask RTL8711 performing site-survey
+
+Command-Event Mode
+
+*/
+
+#define RTW_SSID_SCAN_AMOUNT 9 /* for WEXT_CSCAN_AMOUNT 9 */
+#define RTW_CHANNEL_SCAN_AMOUNT (14+37)
+struct sitesurvey_parm {
+	sint scan_mode;	/* active: 1, passive: 0 */
+	/* sint bsslimit;	// 1 ~ 48 */
+	u8 ssid_num;
+	u8 ch_num;
+	NDIS_802_11_SSID ssid[RTW_SSID_SCAN_AMOUNT];
+	struct rtw_ieee80211_channel ch[RTW_CHANNEL_SCAN_AMOUNT];
+
+	u32 token; 	/* 80211k use it to identify caller */
+	u16 duration;	/* 0: use default, otherwise: channel scan time */
+	u8 igi;		/* 0: use defalut */
+	u8 bw;		/* 0: use default */
+};
+
+/*
+Caller Mode: Any
+
+Notes: To set the auth type of RTL8711. open/shared/802.1x
+
+Command Mode
+
+*/
+struct setauth_parm {
+	u8 mode;  /* 0: legacy open, 1: legacy shared 2: 802.1x */
+	u8 _1x;   /* 0: PSK, 1: TLS */
+	u8 rsvd[2];
+};
+
+/*
+Caller Mode: Infra
+
+a. algorithm: wep40, wep104, tkip & aes
+b. keytype: grp key/unicast key
+c. key contents
+
+when shared key ==> keyid is the camid
+when 802.1x ==> keyid [0:1] ==> grp key
+when 802.1x ==> keyid > 2 ==> unicast key
+
+*/
+struct setkey_parm {
+	u8	algorithm;	/* encryption algorithm, could be none, wep40, TKIP, CCMP, wep104 */
+	u8	keyid;
+	u8	set_tx;		/* 1: main tx key for wep. 0: other key. */
+	u8	key[16];	/* this could be 40 or 104 */
+};
+
+/*
+When in AP or Ad-Hoc mode, this is used to
+allocate an sw/hw entry for a newly associated sta.
+
+Command
+
+when shared key ==> algorithm/keyid
+
+*/
+struct set_stakey_parm {
+	u8 addr[ETH_ALEN];
+	u8 algorithm;
+	u8 keyid;
+	u8 key[16];
+	u8 gk;
+};
+
+struct set_stakey_rsp {
+	u8	addr[ETH_ALEN];
+	u8	keyid;
+	u8	rsvd;
+};
+
+/*
+Caller Ad-Hoc/AP
+
+Command -Rsp(AID == CAMID) mode
+
+This is to force fw to add an sta_data entry per driver's request.
+
+FW will write an cam entry associated with it.
+
+*/
+struct set_assocsta_parm {
+	u8	addr[ETH_ALEN];
+};
+
+struct set_assocsta_rsp {
+	u8	cam_id;
+	u8	rsvd[3];
+};
+
+/*
+	Caller Ad-Hoc/AP
+	Command mode
+	This is to force fw to del an sta_data entry per driver's request
+	FW will invalidate the cam entry associated with it.
+*/
+struct del_assocsta_parm {
+	u8	addr[ETH_ALEN];
+};
+
+/*
+Caller Mode: AP/Ad-HoC(M)
+
+Notes: To notify fw that given staid has changed its power state
+
+Command Mode
+
+*/
+struct setstapwrstate_parm {
+	u8	staid;
+	u8	status;
+	u8	hwaddr[6];
+};
+
+/*
+Caller Mode: Any
+
+Notes: To setup the basic rate of RTL8711
+
+Command Mode
+
+*/
+struct	setbasicrate_parm {
+	u8	basicrates[NumRates];
+};
+
+/*
+Caller Mode: Any
+
+Notes: To read the current basic rate
+
+Command-Rsp Mode
+
+*/
+struct getbasicrate_parm {
+	u32 rsvd;
+};
+
+struct getbasicrate_rsp {
+	u8 basicrates[NumRates];
+};
+
+/*
+Caller Mode: Any
+
+Notes: To setup the data rate of RTL8711
+
+Command Mode
+
+*/
+struct setdatarate_parm {
+#ifdef MP_FIRMWARE_OFFLOAD
+	u32	curr_rateidx;
+#else
+	u8	mac_id;
+	u8	datarates[NumRates];
+#endif
+};
+
+/*
+Caller Mode: Any
+
+Notes: To read the current data rate
+
+Command-Rsp Mode
+
+*/
+struct getdatarate_parm {
+	u32 rsvd;
+
+};
+struct getdatarate_rsp {
+	u8 datarates[NumRates];
+};
+
+/*
+Caller Mode: Any
+
+Notes: To set the channel/modem/band
+This command will be used when channel/modem/band is changed.
+
+Command Mode
+
+*/
+struct	setphy_parm {
+	u8	rfchannel;
+	u8	modem;
+};
+
+/*
+Caller Mode: Any
+
+Notes: To get the current setting of channel/modem/band
+
+Command-Rsp Mode
+
+*/
+struct	getphy_parm {
+	u32 rsvd;
+
+};
+struct	getphy_rsp {
+	u8	rfchannel;
+	u8	modem;
+};
+
+struct readBB_parm {
+	u8	offset;
+};
+struct readBB_rsp {
+	u8	value;
+};
+
+struct readTSSI_parm {
+	u8	offset;
+};
+struct readTSSI_rsp {
+	u8	value;
+};
+
+struct readMAC_parm {
+	u8 len;
+	u32	addr;
+};
+
+struct writeBB_parm {
+	u8	offset;
+	u8	value;
+};
+
+struct readRF_parm {
+	u8	offset;
+};
+struct readRF_rsp {
+	u32	value;
+};
+
+struct writeRF_parm {
+	u32	offset;
+	u32	value;
+};
+
+struct getrfintfs_parm {
+	u8	rfintfs;
+};
+
+
+struct Tx_Beacon_param {
+	WLAN_BSSID_EX network;
+};
+
+/*
+	Notes: This command is used for H2C/C2H loopback testing
+
+	mac[0] == 0
+	==> CMD mode, return H2C_SUCCESS.
+	The following condition must be ture under CMD mode
+		mac[1] == mac[4], mac[2] == mac[3], mac[0]=mac[5]= 0;
+		s0 == 0x1234, s1 == 0xabcd, w0 == 0x78563412, w1 == 0x5aa5def7;
+		s2 == (b1 << 8 | b0);
+
+	mac[0] == 1
+	==> CMD_RSP mode, return H2C_SUCCESS_RSP
+
+	The rsp layout shall be:
+	rsp:			parm:
+		mac[0]  =   mac[5];
+		mac[1]  =   mac[4];
+		mac[2]  =   mac[3];
+		mac[3]  =   mac[2];
+		mac[4]  =   mac[1];
+		mac[5]  =   mac[0];
+		s0		=   s1;
+		s1		=   swap16(s0);
+		w0		=	swap32(w1);
+		b0		=	b1
+		s2		=	s0 + s1
+		b1		=	b0
+		w1		=	w0
+
+	mac[0] ==	2
+	==> CMD_EVENT mode, return	H2C_SUCCESS
+	The event layout shall be:
+	event:			parm:
+		mac[0]  =   mac[5];
+		mac[1]  =   mac[4];
+		mac[2]  =   event's sequence number, starting from 1 to parm's marc[3]
+		mac[3]  =   mac[2];
+		mac[4]  =   mac[1];
+		mac[5]  =   mac[0];
+		s0		=   swap16(s0) - event.mac[2];
+		s1		=   s1 + event.mac[2];
+		w0		=	swap32(w0);
+		b0		=	b1
+		s2		=	s0 + event.mac[2]
+		b1		=	b0
+		w1		=	swap32(w1) - event.mac[2];
+
+		parm->mac[3] is the total event counts that host requested.
+
+
+	event will be the same with the cmd's param.
+
+*/
+
+#ifdef CONFIG_H2CLBK
+
+struct seth2clbk_parm {
+	u8 mac[6];
+	u16	s0;
+	u16	s1;
+	u32	w0;
+	u8	b0;
+	u16  s2;
+	u8	b1;
+	u32	w1;
+};
+
+struct geth2clbk_parm {
+	u32 rsv;
+};
+
+struct geth2clbk_rsp {
+	u8	mac[6];
+	u16	s0;
+	u16	s1;
+	u32	w0;
+	u8	b0;
+	u16	s2;
+	u8	b1;
+	u32	w1;
+};
+
+#endif	/* CONFIG_H2CLBK */
+
+/* CMD param Formart for driver extra cmd handler */
+struct drvextra_cmd_parm {
+	int ec_id; /* extra cmd id */
+	int type; /* Can use this field as the type id or command size */
+	int size; /* buffer size */
+	unsigned char *pbuf;
+};
+
+/*------------------- Below are used for RF/BB tunning ---------------------*/
+
+struct	setantenna_parm {
+	u8	tx_antset;
+	u8	rx_antset;
+	u8	tx_antenna;
+	u8	rx_antenna;
+};
+
+struct	enrateadaptive_parm {
+	u32	en;
+};
+
+struct settxagctbl_parm {
+	u32	txagc[MAX_RATES_LENGTH];
+};
+
+struct gettxagctbl_parm {
+	u32 rsvd;
+};
+struct gettxagctbl_rsp {
+	u32	txagc[MAX_RATES_LENGTH];
+};
+
+struct setagcctrl_parm {
+	u32	agcctrl;		/* 0: pure hw, 1: fw */
+};
+
+
+struct setssup_parm	{
+	u32	ss_ForceUp[MAX_RATES_LENGTH];
+};
+
+struct getssup_parm	{
+	u32 rsvd;
+};
+struct getssup_rsp	{
+	u8	ss_ForceUp[MAX_RATES_LENGTH];
+};
+
+
+struct setssdlevel_parm	{
+	u8	ss_DLevel[MAX_RATES_LENGTH];
+};
+
+struct getssdlevel_parm	{
+	u32 rsvd;
+};
+struct getssdlevel_rsp	{
+	u8	ss_DLevel[MAX_RATES_LENGTH];
+};
+
+struct setssulevel_parm	{
+	u8	ss_ULevel[MAX_RATES_LENGTH];
+};
+
+struct getssulevel_parm	{
+	u32 rsvd;
+};
+struct getssulevel_rsp	{
+	u8	ss_ULevel[MAX_RATES_LENGTH];
+};
+
+
+struct	setcountjudge_parm {
+	u8	count_judge[MAX_RATES_LENGTH];
+};
+
+struct	getcountjudge_parm {
+	u32 rsvd;
+};
+struct	getcountjudge_rsp {
+	u8	count_judge[MAX_RATES_LENGTH];
+};
+
+
+struct setratable_parm {
+	u8 ss_ForceUp[NumRates];
+	u8 ss_ULevel[NumRates];
+	u8 ss_DLevel[NumRates];
+	u8 count_judge[NumRates];
+};
+
+struct getratable_parm {
+	uint rsvd;
+};
+struct getratable_rsp {
+	u8 ss_ForceUp[NumRates];
+	u8 ss_ULevel[NumRates];
+	u8 ss_DLevel[NumRates];
+	u8 count_judge[NumRates];
+};
+
+
+/* to get TX,RX retry count */
+struct gettxretrycnt_parm {
+	unsigned int rsvd;
+};
+struct gettxretrycnt_rsp {
+	unsigned long tx_retrycnt;
+};
+
+struct getrxretrycnt_parm {
+	unsigned int rsvd;
+};
+struct getrxretrycnt_rsp {
+	unsigned long rx_retrycnt;
+};
+
+/* to get BCNOK,BCNERR count */
+struct getbcnokcnt_parm {
+	unsigned int rsvd;
+};
+struct getbcnokcnt_rsp {
+	unsigned long  bcnokcnt;
+};
+
+struct getbcnerrcnt_parm {
+	unsigned int rsvd;
+};
+struct getbcnerrcnt_rsp {
+	unsigned long bcnerrcnt;
+};
+
+/* to get current TX power level */
+struct getcurtxpwrlevel_parm {
+	unsigned int rsvd;
+};
+struct getcurtxpwrlevel_rsp {
+	unsigned short tx_power;
+};
+
+struct setprobereqextraie_parm {
+	unsigned char e_id;
+	unsigned char ie_len;
+	unsigned char ie[0];
+};
+
+struct setassocreqextraie_parm {
+	unsigned char e_id;
+	unsigned char ie_len;
+	unsigned char ie[0];
+};
+
+struct setproberspextraie_parm {
+	unsigned char e_id;
+	unsigned char ie_len;
+	unsigned char ie[0];
+};
+
+struct setassocrspextraie_parm {
+	unsigned char e_id;
+	unsigned char ie_len;
+	unsigned char ie[0];
+};
+
+
+struct addBaReq_parm {
+	unsigned int tid;
+	u8	addr[ETH_ALEN];
+};
+
+struct addBaRsp_parm {
+	unsigned int tid;
+	unsigned int start_seq;
+	u8 addr[ETH_ALEN];
+	u8 status;
+	u8 size;
+};
+
+/*H2C Handler index: 46 */
+struct set_ch_parm {
+	u8 ch;
+	u8 bw;
+	u8 ch_offset;
+};
+
+#ifdef MP_FIRMWARE_OFFLOAD
+/*H2C Handler index: 47 */
+struct SetTxPower_parm {
+	u8 TxPower;
+};
+
+/*H2C Handler index: 48 */
+struct SwitchAntenna_parm {
+	u16 antenna_tx;
+	u16 antenna_rx;
+	/*	R_ANTENNA_SELECT_CCK cck_txrx; */
+	u8 cck_txrx;
+};
+
+/*H2C Handler index: 49 */
+struct SetCrystalCap_parm {
+	u32 curr_crystalcap;
+};
+
+/*H2C Handler index: 50 */
+struct SetSingleCarrierTx_parm {
+	u8 bStart;
+};
+
+/*H2C Handler index: 51 */
+struct SetSingleToneTx_parm {
+	u8 bStart;
+	u8 curr_rfpath;
+};
+
+/*H2C Handler index: 52 */
+struct SetCarrierSuppressionTx_parm {
+	u8 bStart;
+	u32 curr_rateidx;
+};
+
+/*H2C Handler index: 53 */
+struct SetContinuousTx_parm {
+	u8 bStart;
+	u8 CCK_flag; /*1:CCK 2:OFDM*/
+	u32 curr_rateidx;
+};
+
+/*H2C Handler index: 54 */
+struct SwitchBandwidth_parm {
+	u8 curr_bandwidth;
+};
+
+#endif	/* MP_FIRMWARE_OFFLOAD */
+
+/*H2C Handler index: 59 */
+struct SetChannelPlan_param {
+	const struct country_chplan *country_ent;
+	u8 channel_plan;
+};
+
+/*H2C Handler index: 60 */
+struct LedBlink_param {
+	PVOID	 pLed;
+};
+
+/*H2C Handler index: 62 */
+struct TDLSoption_param {
+	u8 addr[ETH_ALEN];
+	u8 option;
+};
+
+/*H2C Handler index: 64 */
+struct RunInThread_param {
+	void (*func)(void *);
+	void *context;
+};
+
+
+#define GEN_CMD_CODE(cmd)	cmd ## _CMD_
+
+
+/*
+
+Result:
+0x00: success
+0x01: sucess, and check Response.
+0x02: cmd ignored due to duplicated sequcne number
+0x03: cmd dropped due to invalid cmd code
+0x04: reserved.
+
+*/
+
+#define H2C_RSP_OFFSET			512
+
+#define H2C_SUCCESS			0x00
+#define H2C_SUCCESS_RSP			0x01
+#define H2C_DUPLICATED			0x02
+#define H2C_DROPPED			0x03
+#define H2C_PARAMETERS_ERROR		0x04
+#define H2C_REJECTED			0x05
+#define H2C_CMD_OVERFLOW		0x06
+#define H2C_RESERVED			0x07
+#define H2C_ENQ_HEAD			0x08
+#define H2C_ENQ_HEAD_FAIL		0x09
+#define H2C_CMD_FAIL			0x0A
+
+extern u8 rtw_setassocsta_cmd(_adapter  *padapter, u8 *mac_addr);
+extern u8 rtw_setstandby_cmd(_adapter *padapter, uint action);
+void rtw_init_sitesurvey_parm(_adapter *padapter, struct sitesurvey_parm *pparm);
+u8 rtw_sitesurvey_cmd(_adapter *padapter, struct sitesurvey_parm *pparm);
+u8 rtw_create_ibss_cmd(_adapter *adapter, int flags);
+u8 rtw_startbss_cmd(_adapter *adapter, int flags);
+
+#define REQ_CH_NONE		-1
+#define REQ_BW_NONE		-1
+#define REQ_BW_ORI		-2
+#define REQ_OFFSET_NONE	-1
+
+u8 rtw_change_bss_chbw_cmd(_adapter *adapter, int flags
+	, u8 ifbmp, u8 excl_ifbmp, s16 req_ch, s8 req_bw, s8 req_offset);
+
+extern u8 rtw_setphy_cmd(_adapter  *padapter, u8 modem, u8 ch);
+
+struct sta_info;
+extern u8 rtw_setstakey_cmd(_adapter  *padapter, struct sta_info *sta, u8 key_type, bool enqueue);
+extern u8 rtw_clearstakey_cmd(_adapter *padapter, struct sta_info *sta, u8 enqueue);
+
+extern u8 rtw_joinbss_cmd(_adapter  *padapter, struct wlan_network *pnetwork);
+u8 rtw_disassoc_cmd(_adapter *padapter, u32 deauth_timeout_ms, int flags);
+extern u8 rtw_setopmode_cmd(_adapter  *padapter, NDIS_802_11_NETWORK_INFRASTRUCTURE networktype, u8 flags);
+extern u8 rtw_setdatarate_cmd(_adapter  *padapter, u8 *rateset);
+extern u8 rtw_setbasicrate_cmd(_adapter  *padapter, u8 *rateset);
+extern u8 rtw_getmacreg_cmd(_adapter *padapter, u8 len, u32 addr);
+extern void rtw_usb_catc_trigger_cmd(_adapter *padapter, const char *caller);
+extern u8 rtw_setbbreg_cmd(_adapter *padapter, u8 offset, u8 val);
+extern u8 rtw_setrfreg_cmd(_adapter *padapter, u8 offset, u32 val);
+extern u8 rtw_getbbreg_cmd(_adapter *padapter, u8 offset, u8 *pval);
+extern u8 rtw_getrfreg_cmd(_adapter *padapter, u8 offset, u8 *pval);
+extern u8 rtw_setrfintfs_cmd(_adapter  *padapter, u8 mode);
+extern u8 rtw_setrttbl_cmd(_adapter  *padapter, struct setratable_parm *prate_table);
+extern u8 rtw_getrttbl_cmd(_adapter  *padapter, struct getratable_rsp *pval);
+
+extern u8 rtw_gettssi_cmd(_adapter  *padapter, u8 offset, u8 *pval);
+extern u8 rtw_setfwdig_cmd(_adapter *padapter, u8 type);
+extern u8 rtw_setfwra_cmd(_adapter *padapter, u8 type);
+
+extern u8 rtw_addbareq_cmd(_adapter *padapter, u8 tid, u8 *addr);
+extern u8 rtw_addbarsp_cmd(_adapter *padapter, u8 *addr, u16 tid, u8 status, u8 size, u16 start_seq);
+/* add for CONFIG_IEEE80211W, none 11w also can use */
+extern u8 rtw_reset_securitypriv_cmd(_adapter *padapter);
+extern u8 rtw_free_assoc_resources_cmd(_adapter *padapter, u8 lock_scanned_queue, int flags);
+extern u8 rtw_dynamic_chk_wk_cmd(_adapter *adapter);
+
+u8 rtw_lps_ctrl_wk_cmd(_adapter *padapter, u8 lps_ctrl_type, u8 enqueue);
+u8 rtw_dm_in_lps_wk_cmd(_adapter *padapter);
+u8 rtw_lps_change_dtim_cmd(_adapter *padapter, u8 dtim);
+
+#if (RATE_ADAPTIVE_SUPPORT == 1)
+u8 rtw_rpt_timer_cfg_cmd(_adapter *padapter, u16 minRptTime);
+#endif
+
+#ifdef CONFIG_ANTENNA_DIVERSITY
+extern  u8 rtw_antenna_select_cmd(_adapter *padapter, u8 antenna, u8 enqueue);
+#endif
+
+u8 rtw_dm_ra_mask_wk_cmd(_adapter *padapter, u8 *psta);
+
+extern u8 rtw_ps_cmd(_adapter *padapter);
+
+#ifdef CONFIG_DFS
+void rtw_dfs_ch_switch_hdl(struct dvobj_priv *dvobj);
+#endif
+
+#ifdef CONFIG_AP_MODE
+u8 rtw_chk_hi_queue_cmd(_adapter *padapter);
+#ifdef CONFIG_DFS_MASTER
+u8 rtw_dfs_rd_cmd(_adapter *adapter, bool enqueue);
+void rtw_dfs_rd_timer_hdl(void *ctx);
+void rtw_dfs_rd_en_decision(_adapter *adapter, u8 mlme_act, u8 excl_ifbmp);
+u8 rtw_dfs_rd_en_decision_cmd(_adapter *adapter);
+#endif /* CONFIG_DFS_MASTER */
+#endif /* CONFIG_AP_MODE */
+
+#ifdef CONFIG_BT_COEXIST
+u8 rtw_btinfo_cmd(PADAPTER padapter, u8 *pbuf, u16 length);
+#endif
+
+u8 rtw_test_h2c_cmd(_adapter *adapter, u8 *buf, u8 len);
+
+u8 rtw_enable_hw_update_tsf_cmd(_adapter *padapter);
+u8 rtw_periodic_tsf_update_end_cmd(_adapter *adapter);
+
+u8 rtw_set_chbw_cmd(_adapter *padapter, u8 ch, u8 bw, u8 ch_offset, u8 flags);
+
+u8 rtw_set_chplan_cmd(_adapter *adapter, int flags, u8 chplan, u8 swconfig);
+u8 rtw_set_country_cmd(_adapter *adapter, int flags, const char *country_code, u8 swconfig);
+
+extern u8 rtw_led_blink_cmd(_adapter *padapter, PVOID pLed);
+extern u8 rtw_set_csa_cmd(_adapter *adapter);
+extern u8 rtw_tdls_cmd(_adapter *padapter, u8 *addr, u8 option);
+
+u8 rtw_mp_cmd(_adapter *adapter, u8 mp_cmd_id, u8 flags);
+
+#ifdef CONFIG_RTW_CUSTOMER_STR
+u8 rtw_customer_str_req_cmd(_adapter *adapter);
+u8 rtw_customer_str_write_cmd(_adapter *adapter, const u8 *cstr);
+#endif
+
+#ifdef CONFIG_FW_C2H_REG
+u8 rtw_c2h_reg_wk_cmd(_adapter *adapter, u8 *c2h_evt);
+#endif
+#ifdef CONFIG_FW_C2H_PKT
+u8 rtw_c2h_packet_wk_cmd(_adapter *adapter, u8 *c2h_evt, u16 length);
+#endif
+
+#ifdef CONFIG_RTW_REPEATER_SON
+#define RSON_SCAN_PROCESS		10
+#define RSON_SCAN_DISABLE		11
+u8 rtw_rson_scan_wk_cmd(_adapter *adapter, int op);
+#endif
+
+u8 rtw_run_in_thread_cmd(PADAPTER padapter, void (*func)(void *), void *context);
+
+u8 session_tracker_chk_cmd(_adapter *adapter, struct sta_info *sta);
+u8 session_tracker_add_cmd(_adapter *adapter, struct sta_info *sta, u8 *local_naddr, u8 *local_port, u8 *remote_naddr, u8 *remote_port);
+u8 session_tracker_del_cmd(_adapter *adapter, struct sta_info *sta, u8 *local_naddr, u8 *local_port, u8 *remote_naddr, u8 *remote_port);
+
+#if defined(CONFIG_RTW_MESH) && defined(RTW_PER_CMD_SUPPORT_FW)
+u8 rtw_req_per_cmd(_adapter * adapter);
+#endif
+
+u8 rtw_drvextra_cmd_hdl(_adapter *padapter, unsigned char *pbuf);
+
+extern void rtw_survey_cmd_callback(_adapter  *padapter, struct cmd_obj *pcmd);
+extern void rtw_disassoc_cmd_callback(_adapter  *padapter, struct cmd_obj *pcmd);
+extern void rtw_joinbss_cmd_callback(_adapter  *padapter, struct cmd_obj *pcmd);
+void rtw_create_ibss_post_hdl(_adapter *padapter, int status);
+extern void rtw_getbbrfreg_cmdrsp_callback(_adapter  *padapter, struct cmd_obj *pcmd);
+extern void rtw_readtssi_cmdrsp_callback(_adapter	*padapter,  struct cmd_obj *pcmd);
+
+extern void rtw_setstaKey_cmdrsp_callback(_adapter  *padapter,  struct cmd_obj *pcmd);
+extern void rtw_setassocsta_cmdrsp_callback(_adapter  *padapter,  struct cmd_obj *pcmd);
+extern void rtw_getrttbl_cmdrsp_callback(_adapter  *padapter,  struct cmd_obj *pcmd);
+extern void rtw_getmacreg_cmdrsp_callback(_adapter *padapter,  struct cmd_obj *pcmd);
+
+
+struct _cmd_callback {
+	u32	cmd_code;
+	void (*callback)(_adapter  *padapter, struct cmd_obj *cmd);
+};
+
+enum rtw_h2c_cmd {
+	GEN_CMD_CODE(_Read_MACREG) ,	/*0*/
+	GEN_CMD_CODE(_Write_MACREG) ,
+	GEN_CMD_CODE(_Read_BBREG) ,
+	GEN_CMD_CODE(_Write_BBREG) ,
+	GEN_CMD_CODE(_Read_RFREG) ,
+	GEN_CMD_CODE(_Write_RFREG) , /*5*/
+	GEN_CMD_CODE(_Read_EEPROM) ,
+	GEN_CMD_CODE(_Write_EEPROM) ,
+	GEN_CMD_CODE(_Read_EFUSE) ,
+	GEN_CMD_CODE(_Write_EFUSE) ,
+
+	GEN_CMD_CODE(_Read_CAM) ,	/*10*/
+	GEN_CMD_CODE(_Write_CAM) ,
+	GEN_CMD_CODE(_setBCNITV),
+	GEN_CMD_CODE(_setMBIDCFG),
+	GEN_CMD_CODE(_JoinBss),   /*14*/
+	GEN_CMD_CODE(_DisConnect) , /*15*/
+	GEN_CMD_CODE(_CreateBss) ,
+	GEN_CMD_CODE(_SetOpMode) ,
+	GEN_CMD_CODE(_SiteSurvey),  /*18*/
+	GEN_CMD_CODE(_SetAuth) ,
+
+	GEN_CMD_CODE(_SetKey) ,	/*20*/
+	GEN_CMD_CODE(_SetStaKey) ,
+	GEN_CMD_CODE(_SetAssocSta) ,
+	GEN_CMD_CODE(_DelAssocSta) ,
+	GEN_CMD_CODE(_SetStaPwrState) ,
+	GEN_CMD_CODE(_SetBasicRate) , /*25*/
+	GEN_CMD_CODE(_GetBasicRate) ,
+	GEN_CMD_CODE(_SetDataRate) ,
+	GEN_CMD_CODE(_GetDataRate) ,
+	GEN_CMD_CODE(_SetPhyInfo) ,
+
+	GEN_CMD_CODE(_GetPhyInfo) ,	/*30*/
+	GEN_CMD_CODE(_SetPhy) ,
+	GEN_CMD_CODE(_GetPhy) ,
+	GEN_CMD_CODE(_readRssi) ,
+	GEN_CMD_CODE(_readGain) ,
+	GEN_CMD_CODE(_SetAtim) , /*35*/
+	GEN_CMD_CODE(_SetPwrMode) ,
+	GEN_CMD_CODE(_JoinbssRpt),
+	GEN_CMD_CODE(_SetRaTable) ,
+	GEN_CMD_CODE(_GetRaTable) ,
+
+	GEN_CMD_CODE(_GetCCXReport), /*40*/
+	GEN_CMD_CODE(_GetDTMReport),
+	GEN_CMD_CODE(_GetTXRateStatistics),
+	GEN_CMD_CODE(_SetUsbSuspend),
+	GEN_CMD_CODE(_SetH2cLbk),
+	GEN_CMD_CODE(_AddBAReq) , /*45*/
+	GEN_CMD_CODE(_SetChannel), /*46*/
+	GEN_CMD_CODE(_SetTxPower),
+	GEN_CMD_CODE(_SwitchAntenna),
+	GEN_CMD_CODE(_SetCrystalCap),
+	GEN_CMD_CODE(_SetSingleCarrierTx), /*50*/
+
+	GEN_CMD_CODE(_SetSingleToneTx),/*51*/
+	GEN_CMD_CODE(_SetCarrierSuppressionTx),
+	GEN_CMD_CODE(_SetContinuousTx),
+	GEN_CMD_CODE(_SwitchBandwidth), /*54*/
+	GEN_CMD_CODE(_TX_Beacon), /*55*/
+
+	GEN_CMD_CODE(_Set_MLME_EVT), /*56*/
+	GEN_CMD_CODE(_Set_Drv_Extra), /*57*/
+	GEN_CMD_CODE(_Set_H2C_MSG), /*58*/
+
+	GEN_CMD_CODE(_SetChannelPlan), /*59*/
+	GEN_CMD_CODE(_LedBlink), /*60*/
+
+	GEN_CMD_CODE(_SetChannelSwitch), /*61*/
+	GEN_CMD_CODE(_TDLS), /*62*/
+	GEN_CMD_CODE(_ChkBMCSleepq), /*63*/
+
+	GEN_CMD_CODE(_RunInThreadCMD), /*64*/
+	GEN_CMD_CODE(_AddBARsp) , /*65*/
+	GEN_CMD_CODE(_RM_POST_EVENT), /*66*/
+
+	MAX_H2CCMD
+};
+
+#define _GetMACReg_CMD_ _Read_MACREG_CMD_
+#define _SetMACReg_CMD_ _Write_MACREG_CMD_
+#define _GetBBReg_CMD_		_Read_BBREG_CMD_
+#define _SetBBReg_CMD_		_Write_BBREG_CMD_
+#define _GetRFReg_CMD_		_Read_RFREG_CMD_
+#define _SetRFReg_CMD_		_Write_RFREG_CMD_
+
+#ifdef _RTW_CMD_C_
+struct _cmd_callback	rtw_cmd_callback[] = {
+	{GEN_CMD_CODE(_Read_MACREG), &rtw_getmacreg_cmdrsp_callback}, /*0*/
+	{GEN_CMD_CODE(_Write_MACREG), NULL},
+	{GEN_CMD_CODE(_Read_BBREG), &rtw_getbbrfreg_cmdrsp_callback},
+	{GEN_CMD_CODE(_Write_BBREG), NULL},
+	{GEN_CMD_CODE(_Read_RFREG), &rtw_getbbrfreg_cmdrsp_callback},
+	{GEN_CMD_CODE(_Write_RFREG), NULL}, /*5*/
+	{GEN_CMD_CODE(_Read_EEPROM), NULL},
+	{GEN_CMD_CODE(_Write_EEPROM), NULL},
+	{GEN_CMD_CODE(_Read_EFUSE), NULL},
+	{GEN_CMD_CODE(_Write_EFUSE), NULL},
+
+	{GEN_CMD_CODE(_Read_CAM),	NULL},	/*10*/
+	{GEN_CMD_CODE(_Write_CAM),	 NULL},
+	{GEN_CMD_CODE(_setBCNITV), NULL},
+	{GEN_CMD_CODE(_setMBIDCFG), NULL},
+	{GEN_CMD_CODE(_JoinBss), &rtw_joinbss_cmd_callback},  /*14*/
+	{GEN_CMD_CODE(_DisConnect), &rtw_disassoc_cmd_callback}, /*15*/
+	{GEN_CMD_CODE(_CreateBss), NULL},
+	{GEN_CMD_CODE(_SetOpMode), NULL},
+	{GEN_CMD_CODE(_SiteSurvey), &rtw_survey_cmd_callback}, /*18*/
+	{GEN_CMD_CODE(_SetAuth), NULL},
+
+	{GEN_CMD_CODE(_SetKey), NULL},	/*20*/
+	{GEN_CMD_CODE(_SetStaKey), &rtw_setstaKey_cmdrsp_callback},
+	{GEN_CMD_CODE(_SetAssocSta), &rtw_setassocsta_cmdrsp_callback},
+	{GEN_CMD_CODE(_DelAssocSta), NULL},
+	{GEN_CMD_CODE(_SetStaPwrState), NULL},
+	{GEN_CMD_CODE(_SetBasicRate), NULL}, /*25*/
+	{GEN_CMD_CODE(_GetBasicRate), NULL},
+	{GEN_CMD_CODE(_SetDataRate), NULL},
+	{GEN_CMD_CODE(_GetDataRate), NULL},
+	{GEN_CMD_CODE(_SetPhyInfo), NULL},
+
+	{GEN_CMD_CODE(_GetPhyInfo), NULL}, /*30*/
+	{GEN_CMD_CODE(_SetPhy), NULL},
+	{GEN_CMD_CODE(_GetPhy), NULL},
+	{GEN_CMD_CODE(_readRssi), NULL},
+	{GEN_CMD_CODE(_readGain), NULL},
+	{GEN_CMD_CODE(_SetAtim), NULL}, /*35*/
+	{GEN_CMD_CODE(_SetPwrMode), NULL},
+	{GEN_CMD_CODE(_JoinbssRpt), NULL},
+	{GEN_CMD_CODE(_SetRaTable), NULL},
+	{GEN_CMD_CODE(_GetRaTable) , NULL},
+
+	{GEN_CMD_CODE(_GetCCXReport), NULL}, /*40*/
+	{GEN_CMD_CODE(_GetDTMReport),	NULL},
+	{GEN_CMD_CODE(_GetTXRateStatistics), NULL},
+	{GEN_CMD_CODE(_SetUsbSuspend), NULL},
+	{GEN_CMD_CODE(_SetH2cLbk), NULL},
+	{GEN_CMD_CODE(_AddBAReq), NULL}, /*45*/
+	{GEN_CMD_CODE(_SetChannel), NULL},		/*46*/
+	{GEN_CMD_CODE(_SetTxPower), NULL},
+	{GEN_CMD_CODE(_SwitchAntenna), NULL},
+	{GEN_CMD_CODE(_SetCrystalCap), NULL},
+	{GEN_CMD_CODE(_SetSingleCarrierTx), NULL},	/*50*/
+
+	{GEN_CMD_CODE(_SetSingleToneTx), NULL}, /*51*/
+	{GEN_CMD_CODE(_SetCarrierSuppressionTx), NULL},
+	{GEN_CMD_CODE(_SetContinuousTx), NULL},
+	{GEN_CMD_CODE(_SwitchBandwidth), NULL},		/*54*/
+	{GEN_CMD_CODE(_TX_Beacon), NULL},/*55*/
+
+	{GEN_CMD_CODE(_Set_MLME_EVT), NULL},/*56*/
+	{GEN_CMD_CODE(_Set_Drv_Extra), NULL},/*57*/
+	{GEN_CMD_CODE(_Set_H2C_MSG), NULL},/*58*/
+	{GEN_CMD_CODE(_SetChannelPlan), NULL},/*59*/
+	{GEN_CMD_CODE(_LedBlink), NULL},/*60*/
+
+	{GEN_CMD_CODE(_SetChannelSwitch), NULL},/*61*/
+	{GEN_CMD_CODE(_TDLS), NULL},/*62*/
+	{GEN_CMD_CODE(_ChkBMCSleepq), NULL}, /*63*/
+
+	{GEN_CMD_CODE(_RunInThreadCMD), NULL},/*64*/
+	{GEN_CMD_CODE(_AddBARsp), NULL}, /*65*/
+	{GEN_CMD_CODE(_RM_POST_EVENT), NULL}, /*66*/
+};
+#endif
+
+#define CMD_FMT "cmd=%d,%d,%d"
+#define CMD_ARG(cmd) \
+	(cmd)->cmdcode, \
+	(cmd)->cmdcode == GEN_CMD_CODE(_Set_Drv_Extra) ? ((struct drvextra_cmd_parm *)(cmd)->parmbuf)->ec_id : ((cmd)->cmdcode == GEN_CMD_CODE(_Set_MLME_EVT) ? ((struct C2HEvent_Header *)(cmd)->parmbuf)->ID : 0), \
+	(cmd)->cmdcode == GEN_CMD_CODE(_Set_Drv_Extra) ? ((struct drvextra_cmd_parm *)(cmd)->parmbuf)->type : 0
+
+#endif /* _CMD_H_ */
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/include/rtw_debug.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/rtw_debug.h
--- linux-5.6.3/3rdparty/rtl8821ce/include/rtw_debug.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/rtw_debug.h	2020-04-10 16:35:06.851661701 +0300
@@ -0,0 +1,628 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#ifndef __RTW_DEBUG_H__
+#define __RTW_DEBUG_H__
+
+/* driver log level*/
+enum {
+	_DRV_NONE_ = 0,
+	_DRV_ALWAYS_ = 1,
+	_DRV_ERR_ = 2,
+	_DRV_WARNING_ = 3,
+	_DRV_INFO_ = 4,
+	_DRV_DEBUG_ = 5,
+	_DRV_MAX_ = 6
+};
+
+#define DRIVER_PREFIX "RTW: "
+
+#ifdef PLATFORM_OS_CE
+extern void rtl871x_cedbg(const char *fmt, ...);
+#endif
+
+#ifdef PLATFORM_WINDOWS
+	#define RTW_PRINT do {} while (0)
+	#define RTW_ERR do {} while (0)
+	#define RTW_WARN do {} while (0)
+	#define RTW_INFO do {} while (0)
+	#define RTW_DBG do {} while (0)
+	#define RTW_PRINT_SEL do {} while (0)
+	#define _RTW_PRINT do {} while (0)
+	#define _RTW_ERR do {} while (0)
+	#define _RTW_WARN do {} while (0)
+	#define _RTW_INFO do {} while (0)
+	#define _RTW_DBG do {} while (0)
+	#define _RTW_PRINT_SEL do {} while (0)
+#else
+	#define RTW_PRINT(x, ...) do {} while (0)
+	#define RTW_ERR(x, ...) do {} while (0)
+	#define RTW_WARN(x,...) do {} while (0)
+	#define RTW_INFO(x,...) do {} while (0)
+	#define RTW_DBG(x,...) do {} while (0)
+	#define RTW_PRINT_SEL(x,...) do {} while (0)
+	#define _RTW_PRINT(x, ...) do {} while (0)
+	#define _RTW_ERR(x, ...) do {} while (0)
+	#define _RTW_WARN(x,...) do {} while (0)
+	#define _RTW_INFO(x,...) do {} while (0)
+	#define _RTW_DBG(x,...) do {} while (0)
+	#define _RTW_PRINT_SEL(x,...) do {} while (0)
+#endif
+
+#define RTW_INFO_DUMP(_TitleString, _HexData, _HexDataLen) do {} while (0)
+#define RTW_DBG_DUMP(_TitleString, _HexData, _HexDataLen) do {} while (0)
+#define RTW_PRINT_DUMP(_TitleString, _HexData, _HexDataLen) do {} while (0)
+
+#define RTW_DBG_EXPR(EXPR) do {} while (0)
+
+#define RTW_DBGDUMP 0 /* 'stream' for _dbgdump */
+
+
+
+#undef _dbgdump
+#undef _seqdump
+
+#if defined(PLATFORM_WINDOWS) && defined(PLATFORM_OS_XP)
+	#define _dbgdump DbgPrint
+	#define KERN_CONT
+	#define _seqdump(sel, fmt, arg...) _dbgdump(fmt, ##arg)
+#elif defined(PLATFORM_WINDOWS) && defined(PLATFORM_OS_CE)
+	#define _dbgdump rtl871x_cedbg
+	#define KERN_CONT
+	#define _seqdump(sel, fmt, arg...) _dbgdump(fmt, ##arg)
+#elif defined PLATFORM_LINUX
+	#define _dbgdump printk
+	#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 24))
+	#define KERN_CONT
+	#endif
+	#define _seqdump seq_printf
+#elif defined PLATFORM_FREEBSD
+	#define _dbgdump printf
+	#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 24))
+	#define KERN_CONT
+	#endif
+	#define _seqdump(sel, fmt, arg...) _dbgdump(fmt, ##arg)
+#endif
+
+void RTW_BUF_DUMP_SEL(uint _loglevel, void *sel, u8 *_titlestring,
+								bool _idx_show, const u8 *_hexdata, int _hexdatalen);
+
+#ifdef CONFIG_RTW_DEBUG
+
+#ifndef _OS_INTFS_C_
+extern uint rtw_drv_log_level;
+#endif
+
+#if defined(_dbgdump)
+
+/* with driver-defined prefix */
+#undef RTW_PRINT
+#define RTW_PRINT(fmt, arg...)     \
+	do {\
+		if (_DRV_ALWAYS_ <= rtw_drv_log_level) {\
+			_dbgdump(DRIVER_PREFIX fmt, ##arg);\
+		} \
+	} while (0)
+
+#undef RTW_ERR
+#define RTW_ERR(fmt, arg...)     \
+	do {\
+		if (_DRV_ERR_ <= rtw_drv_log_level) {\
+			_dbgdump(DRIVER_PREFIX"ERROR " fmt, ##arg);\
+		} \
+	} while (0)
+
+
+#undef RTW_WARN
+#define RTW_WARN(fmt, arg...)     \
+	do {\
+		if (_DRV_WARNING_ <= rtw_drv_log_level) {\
+			_dbgdump(DRIVER_PREFIX"WARN " fmt, ##arg);\
+		} \
+	} while (0)
+
+#undef RTW_INFO
+#define RTW_INFO(fmt, arg...)     \
+	do {\
+		if (_DRV_INFO_ <= rtw_drv_log_level) {\
+			_dbgdump(DRIVER_PREFIX fmt, ##arg);\
+		} \
+	} while (0)
+
+
+#undef RTW_DBG
+#define RTW_DBG(fmt, arg...)     \
+	do {\
+		if (_DRV_DEBUG_ <= rtw_drv_log_level) {\
+			_dbgdump(DRIVER_PREFIX fmt, ##arg);\
+		} \
+	} while (0)
+
+#undef RTW_INFO_DUMP
+#define RTW_INFO_DUMP(_TitleString, _HexData, _HexDataLen)	\
+	RTW_BUF_DUMP_SEL(_DRV_INFO_, RTW_DBGDUMP, _TitleString, _FALSE, _HexData, _HexDataLen)
+
+#undef RTW_DBG_DUMP
+#define RTW_DBG_DUMP(_TitleString, _HexData, _HexDataLen)	\
+	RTW_BUF_DUMP_SEL(_DRV_DEBUG_, RTW_DBGDUMP, _TitleString, _FALSE, _HexData, _HexDataLen)
+
+
+#undef RTW_PRINT_DUMP
+#define RTW_PRINT_DUMP(_TitleString, _HexData, _HexDataLen)	\
+	RTW_BUF_DUMP_SEL(_DRV_ALWAYS_, RTW_DBGDUMP, _TitleString, _FALSE, _HexData, _HexDataLen)
+
+/* without driver-defined prefix */
+#undef _RTW_PRINT
+#define _RTW_PRINT(fmt, arg...)     \
+	do {\
+		if (_DRV_ALWAYS_ <= rtw_drv_log_level) {\
+			_dbgdump(KERN_CONT fmt, ##arg);\
+		} \
+	} while (0)
+
+#undef _RTW_ERR
+#define _RTW_ERR(fmt, arg...)     \
+	do {\
+		if (_DRV_ERR_ <= rtw_drv_log_level) {\
+			_dbgdump(KERN_CONT fmt, ##arg);\
+		} \
+	} while (0)
+
+
+#undef _RTW_WARN
+#define _RTW_WARN(fmt, arg...)     \
+	do {\
+		if (_DRV_WARNING_ <= rtw_drv_log_level) {\
+			_dbgdump(KERN_CONT fmt, ##arg);\
+		} \
+	} while (0)
+
+#undef _RTW_INFO
+#define _RTW_INFO(fmt, arg...)     \
+	do {\
+		if (_DRV_INFO_ <= rtw_drv_log_level) {\
+			_dbgdump(KERN_CONT fmt, ##arg);\
+		} \
+	} while (0)
+
+#undef _RTW_DBG
+#define _RTW_DBG(fmt, arg...)     \
+	do {\
+		if (_DRV_DEBUG_ <= rtw_drv_log_level) {\
+			_dbgdump(KERN_CONT fmt, ##arg);\
+		} \
+	} while (0)
+
+
+/* other debug APIs */
+#undef RTW_DBG_EXPR
+#define RTW_DBG_EXPR(EXPR) do { if (_DRV_DEBUG_ <= rtw_drv_log_level) EXPR; } while (0)
+
+#endif /* defined(_dbgdump) */
+#endif /* CONFIG_RTW_DEBUG */
+
+
+#if defined(_seqdump)
+/* dump message to selected 'stream' with driver-defined prefix */
+#undef RTW_PRINT_SEL
+#define RTW_PRINT_SEL(sel, fmt, arg...) \
+	do {\
+		if (sel == RTW_DBGDUMP)\
+			RTW_PRINT(fmt, ##arg); \
+		else {\
+			_seqdump(sel, fmt, ##arg) /*rtw_warn_on(1)*/; \
+		} \
+	} while (0)
+
+/* dump message to selected 'stream' */
+#undef _RTW_PRINT_SEL
+#define _RTW_PRINT_SEL(sel, fmt, arg...) \
+	do {\
+		if (sel == RTW_DBGDUMP)\
+			_RTW_PRINT(fmt, ##arg); \
+		else {\
+			_seqdump(sel, fmt, ##arg) /*rtw_warn_on(1)*/; \
+		} \
+	} while (0)
+
+/* dump message to selected 'stream' */
+#undef RTW_DUMP_SEL
+#define RTW_DUMP_SEL(sel, _HexData, _HexDataLen) \
+	RTW_BUF_DUMP_SEL(_DRV_ALWAYS_, sel, NULL, _FALSE, _HexData, _HexDataLen)
+
+#define RTW_MAP_DUMP_SEL(sel, _TitleString, _HexData, _HexDataLen) \
+	RTW_BUF_DUMP_SEL(_DRV_ALWAYS_, sel, _TitleString, _TRUE, _HexData, _HexDataLen)
+#endif /* defined(_seqdump) */
+
+
+#ifdef CONFIG_DBG_COUNTER
+	#define DBG_COUNTER(counter) counter++
+#else
+	#define DBG_COUNTER(counter)
+#endif
+
+void dump_drv_version(void *sel);
+void dump_log_level(void *sel);
+void dump_drv_cfg(void *sel);
+
+#ifdef CONFIG_SDIO_HCI
+void sd_f0_reg_dump(void *sel, _adapter *adapter);
+void sdio_local_reg_dump(void *sel, _adapter *adapter);
+#endif /* CONFIG_SDIO_HCI */
+
+void mac_reg_dump(void *sel, _adapter *adapter);
+void bb_reg_dump(void *sel, _adapter *adapter);
+void bb_reg_dump_ex(void *sel, _adapter *adapter);
+void rf_reg_dump(void *sel, _adapter *adapter);
+
+void rtw_sink_rtp_seq_dbg(_adapter *adapter, u8 *ehdr_pos);
+
+struct sta_info;
+void sta_rx_reorder_ctl_dump(void *sel, struct sta_info *sta);
+
+struct dvobj_priv;
+void dump_tx_rate_bmp(void *sel, struct dvobj_priv *dvobj);
+void dump_adapters_status(void *sel, struct dvobj_priv *dvobj);
+
+struct sec_cam_ent;
+void dump_sec_cam_ent(void *sel, struct sec_cam_ent *ent, int id);
+void dump_sec_cam_ent_title(void *sel, u8 has_id);
+void dump_sec_cam(void *sel, _adapter *adapter);
+void dump_sec_cam_cache(void *sel, _adapter *adapter);
+
+#ifdef CONFIG_PROC_DEBUG
+ssize_t proc_set_write_reg(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);
+int proc_get_read_reg(struct seq_file *m, void *v);
+ssize_t proc_set_read_reg(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);
+
+int proc_get_fwstate(struct seq_file *m, void *v);
+int proc_get_sec_info(struct seq_file *m, void *v);
+int proc_get_mlmext_state(struct seq_file *m, void *v);
+#ifdef CONFIG_LAYER2_ROAMING
+int proc_get_roam_flags(struct seq_file *m, void *v);
+ssize_t proc_set_roam_flags(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);
+int proc_get_roam_param(struct seq_file *m, void *v);
+ssize_t proc_set_roam_param(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);
+ssize_t proc_set_roam_tgt_addr(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);
+#endif /* CONFIG_LAYER2_ROAMING */
+#ifdef CONFIG_RTW_80211R
+int proc_get_ft_flags(struct seq_file *m, void *v);
+ssize_t proc_set_ft_flags(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);
+#endif
+int proc_get_qos_option(struct seq_file *m, void *v);
+int proc_get_ht_option(struct seq_file *m, void *v);
+int proc_get_rf_info(struct seq_file *m, void *v);
+int proc_get_scan_param(struct seq_file *m, void *v);
+ssize_t proc_set_scan_param(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);
+int proc_get_scan_abort(struct seq_file *m, void *v);
+#ifdef CONFIG_RTW_REPEATER_SON
+int proc_get_rson_data(struct seq_file *m, void *v);
+ssize_t proc_set_rson_data(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);
+#endif
+int proc_get_survey_info(struct seq_file *m, void *v);
+ssize_t proc_set_survey_info(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);
+int proc_get_ap_info(struct seq_file *m, void *v);
+#ifdef ROKU_PRIVATE
+int proc_get_infra_ap(struct seq_file *m, void *v);
+#endif /* ROKU_PRIVATE */
+ssize_t proc_reset_trx_info(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);
+int proc_get_trx_info(struct seq_file *m, void *v);
+ssize_t proc_set_tx_power_offset(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);
+int proc_get_tx_power_offset(struct seq_file *m, void *v);
+int proc_get_rate_ctl(struct seq_file *m, void *v);
+int proc_get_wifi_spec(struct seq_file *m, void *v);
+ssize_t proc_set_rate_ctl(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);
+int proc_get_bw_ctl(struct seq_file *m, void *v);
+ssize_t proc_set_bw_ctl(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);
+#ifdef DBG_RX_COUNTER_DUMP
+int proc_get_rx_cnt_dump(struct seq_file *m, void *v);
+ssize_t proc_set_rx_cnt_dump(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);
+#endif
+
+#ifdef CONFIG_AP_MODE
+int proc_get_bmc_tx_rate(struct seq_file *m, void *v);
+ssize_t proc_set_bmc_tx_rate(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);
+#endif /*CONFIG_AP_MODE*/
+
+int proc_get_ps_dbg_info(struct seq_file *m, void *v);
+ssize_t proc_set_ps_dbg_info(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);
+
+bool rtw_fwdl_test_trigger_chksum_fail(void);
+bool rtw_fwdl_test_trigger_wintint_rdy_fail(void);
+ssize_t proc_set_fwdl_test_case(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);
+bool rtw_del_rx_ampdu_test_trigger_no_tx_fail(void);
+ssize_t proc_set_del_rx_ampdu_test_case(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);
+u32 rtw_get_wait_hiq_empty_ms(void);
+ssize_t proc_set_wait_hiq_empty(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);
+void rtw_sta_linking_test_set_start(void);
+bool rtw_sta_linking_test_wait_done(void);
+bool rtw_sta_linking_test_force_fail(void);
+ssize_t proc_set_sta_linking_test(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);
+#ifdef CONFIG_AP_MODE
+u16 rtw_ap_linking_test_force_auth_fail(void);
+u16 rtw_ap_linking_test_force_asoc_fail(void);
+ssize_t proc_set_ap_linking_test(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);
+#endif
+
+int proc_get_rx_stat(struct seq_file *m, void *v);
+int proc_get_tx_stat(struct seq_file *m, void *v);
+#ifdef CONFIG_AP_MODE
+int proc_get_all_sta_info(struct seq_file *m, void *v);
+#endif /* CONFIG_AP_MODE */
+
+#ifdef DBG_MEMORY_LEAK
+int proc_get_malloc_cnt(struct seq_file *m, void *v);
+#endif /* DBG_MEMORY_LEAK */
+
+#ifdef CONFIG_FIND_BEST_CHANNEL
+int proc_get_best_channel(struct seq_file *m, void *v);
+ssize_t proc_set_best_channel(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);
+#endif /* CONFIG_FIND_BEST_CHANNEL */
+
+int proc_get_trx_info_debug(struct seq_file *m, void *v);
+
+#ifdef CONFIG_HUAWEI_PROC
+int proc_get_huawei_trx_info(struct seq_file *m, void *v);
+#endif
+
+int proc_get_rx_signal(struct seq_file *m, void *v);
+ssize_t proc_set_rx_signal(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);
+int proc_get_hw_status(struct seq_file *m, void *v);
+ssize_t proc_set_hw_status(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);
+int proc_get_mac_rptbuf(struct seq_file *m, void *v);
+
+#ifdef CONFIG_80211N_HT
+int proc_get_ht_enable(struct seq_file *m, void *v);
+ssize_t proc_set_ht_enable(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);
+
+int proc_get_bw_mode(struct seq_file *m, void *v);
+ssize_t proc_set_bw_mode(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);
+
+int proc_get_ampdu_enable(struct seq_file *m, void *v);
+ssize_t proc_set_ampdu_enable(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);
+
+void dump_regsty_rx_ampdu_size_limit(void *sel, _adapter *adapter);
+int proc_get_rx_ampdu(struct seq_file *m, void *v);
+ssize_t proc_set_rx_ampdu(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);
+
+void rtw_dump_dft_phy_cap(void *sel, _adapter *adapter);
+void rtw_get_dft_phy_cap(void *sel, _adapter *adapter);
+void rtw_dump_drv_phy_cap(void *sel, _adapter *adapter);
+
+int proc_get_rx_stbc(struct seq_file *m, void *v);
+ssize_t proc_set_rx_stbc(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);
+int proc_get_stbc_cap(struct seq_file *m, void *v);
+ssize_t proc_set_stbc_cap(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);
+int proc_get_ldpc_cap(struct seq_file *m, void *v);
+ssize_t proc_set_ldpc_cap(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);
+#ifdef CONFIG_BEAMFORMING
+int proc_get_txbf_cap(struct seq_file *m, void *v);
+ssize_t proc_set_txbf_cap(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);
+#endif
+int proc_get_rx_ampdu_factor(struct seq_file *m, void *v);
+ssize_t proc_set_rx_ampdu_factor(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);
+
+int proc_get_tx_max_agg_num(struct seq_file *m, void *v);
+ssize_t proc_set_tx_max_agg_num(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);
+
+int proc_get_rx_ampdu_density(struct seq_file *m, void *v);
+ssize_t proc_set_rx_ampdu_density(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);
+
+int proc_get_tx_ampdu_density(struct seq_file *m, void *v);
+ssize_t proc_set_tx_ampdu_density(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);
+
+#ifdef CONFIG_TX_AMSDU
+int proc_get_tx_amsdu(struct seq_file *m, void *v);
+ssize_t proc_set_tx_amsdu(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);
+int proc_get_tx_amsdu_rate(struct seq_file *m, void *v);
+ssize_t proc_set_tx_amsdu_rate(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);
+#endif
+#endif /* CONFIG_80211N_HT */
+
+int proc_get_en_fwps(struct seq_file *m, void *v);
+ssize_t proc_set_en_fwps(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);
+
+#if 0
+int proc_get_two_path_rssi(struct seq_file *m, void *v);
+int proc_get_rssi_disp(struct seq_file *m, void *v);
+ssize_t proc_set_rssi_disp(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);
+#endif
+
+#ifdef CONFIG_BT_COEXIST
+int proc_get_btcoex_dbg(struct seq_file *m, void *v);
+ssize_t proc_set_btcoex_dbg(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);
+int proc_get_btcoex_info(struct seq_file *m, void *v);
+#ifdef CONFIG_RF4CE_COEXIST
+int proc_get_rf4ce_state(struct seq_file *m, void *v);
+ssize_t proc_set_rf4ce_state(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);
+#endif
+#endif /* CONFIG_BT_COEXIST */
+
+#if defined(DBG_CONFIG_ERROR_DETECT)
+int proc_get_sreset(struct seq_file *m, void *v);
+ssize_t proc_set_sreset(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);
+#endif /* DBG_CONFIG_ERROR_DETECT */
+
+int proc_get_odm_adaptivity(struct seq_file *m, void *v);
+ssize_t proc_set_odm_adaptivity(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);
+
+#ifdef CONFIG_DBG_COUNTER
+int proc_get_rx_logs(struct seq_file *m, void *v);
+int proc_get_tx_logs(struct seq_file *m, void *v);
+int proc_get_int_logs(struct seq_file *m, void *v);
+#endif
+
+#ifdef CONFIG_PCI_HCI
+int proc_get_rx_ring(struct seq_file *m, void *v);
+int proc_get_tx_ring(struct seq_file *m, void *v);
+int proc_get_pci_aspm(struct seq_file *m, void *v);
+int proc_get_pci_conf_space(struct seq_file *m, void *v);
+ssize_t proc_set_pci_conf_space(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);
+
+int proc_get_pci_bridge_conf_space(struct seq_file *m, void *v);
+ssize_t proc_set_pci_bridge_conf_space(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);
+
+
+#ifdef DBG_TXBD_DESC_DUMP
+int proc_get_tx_ring_ext(struct seq_file *m, void *v);
+ssize_t proc_set_tx_ring_ext(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);
+#endif
+#endif
+
+#ifdef CONFIG_WOWLAN
+int proc_get_pattern_info(struct seq_file *m, void *v);
+ssize_t proc_set_pattern_info(struct file *file, const char __user *buffer,
+		size_t count, loff_t *pos, void *data);
+int proc_get_wakeup_event(struct seq_file *m, void *v);
+ssize_t proc_set_wakeup_event(struct file *file, const char __user *buffer,
+		size_t count, loff_t *pos, void *data);
+int proc_get_wakeup_reason(struct seq_file *m, void *v);
+#endif
+
+#ifdef CONFIG_GPIO_WAKEUP
+int proc_get_wowlan_gpio_info(struct seq_file *m, void *v);
+ssize_t proc_set_wowlan_gpio_info(struct file *file, const char __user *buffer,
+		size_t count, loff_t *pos, void *data);
+#endif /*CONFIG_GPIO_WAKEUP*/
+
+#ifdef CONFIG_P2P_WOWLAN
+int proc_get_p2p_wowlan_info(struct seq_file *m, void *v);
+#endif /* CONFIG_P2P_WOWLAN */
+
+int proc_get_new_bcn_max(struct seq_file *m, void *v);
+ssize_t proc_set_new_bcn_max(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);
+
+#ifdef CONFIG_POWER_SAVING
+int proc_get_ps_info(struct seq_file *m, void *v);
+#ifdef CONFIG_WMMPS_STA	
+int proc_get_wmmps_info(struct seq_file *m, void *v);
+ssize_t proc_set_wmmps_info(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);
+#endif /* CONFIG_WMMPS_STA */
+#endif /* CONFIG_POWER_SAVING */
+
+#ifdef CONFIG_TDLS
+int proc_get_tdls_enable(struct seq_file *m, void *v);
+ssize_t proc_set_tdls_enable(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);
+int proc_get_tdls_info(struct seq_file *m, void *v);
+#endif
+
+int proc_get_monitor(struct seq_file *m, void *v);
+ssize_t proc_set_monitor(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);
+
+#ifdef DBG_XMIT_BLOCK
+int proc_get_xmit_block(struct seq_file *m, void *v);
+ssize_t proc_set_xmit_block(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);
+#endif
+
+#ifdef CONFIG_PREALLOC_RX_SKB_BUFFER
+int proc_get_rtkm_info(struct seq_file *m, void *v);
+#endif /* CONFIG_PREALLOC_RX_SKB_BUFFER */
+
+#ifdef CONFIG_IEEE80211W
+ssize_t proc_set_tx_sa_query(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);
+int proc_get_tx_sa_query(struct seq_file *m, void *v);
+ssize_t proc_set_tx_deauth(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);
+int proc_get_tx_deauth(struct seq_file *m, void *v);
+ssize_t proc_set_tx_auth(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);
+int proc_get_tx_auth(struct seq_file *m, void *v);
+#endif /* CONFIG_IEEE80211W */
+
+#endif /* CONFIG_PROC_DEBUG */
+
+int proc_get_efuse_map(struct seq_file *m, void *v);
+ssize_t proc_set_efuse_map(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);
+
+#ifdef CONFIG_MCC_MODE
+int proc_get_mcc_info(struct seq_file *m, void *v);
+ssize_t proc_set_mcc_enable(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);
+ssize_t proc_set_mcc_duration(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);
+ssize_t proc_set_mcc_single_tx_criteria(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);
+ssize_t proc_set_mcc_ap_bw20_target_tp(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);
+ssize_t proc_set_mcc_ap_bw40_target_tp(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);
+ssize_t proc_set_mcc_ap_bw80_target_tp(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);
+ssize_t proc_set_mcc_sta_bw20_target_tp(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);
+ssize_t proc_set_mcc_sta_bw40_target_tp(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);
+ssize_t proc_set_mcc_sta_bw80_target_tp(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);
+int proc_get_mcc_policy_table(struct seq_file *m, void *v);
+#endif /* CONFIG_MCC_MODE */
+
+int proc_get_ack_timeout(struct seq_file *m, void *v);
+ssize_t proc_set_ack_timeout(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);
+
+int proc_get_fw_offload(struct seq_file *m, void *v);
+ssize_t proc_set_fw_offload(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);
+
+#ifdef CONFIG_FW_HANDLE_TXBCN
+ssize_t proc_set_fw_tbtt_rpt(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);
+int proc_get_fw_tbtt_rpt(struct seq_file *m, void *v);
+#endif
+
+#ifdef CONFIG_DBG_RF_CAL
+int proc_get_iqk_info(struct seq_file *m, void *v);
+ssize_t proc_set_iqk(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);
+int proc_get_lck_info(struct seq_file *m, void *v);
+ssize_t proc_set_lck(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);
+#endif /*CONFIG_DBG_RF_CAL*/
+
+#ifdef CONFIG_LPS_CHK_BY_TP
+ssize_t proc_set_lps_chk_tp(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);
+int proc_get_lps_chk_tp(struct seq_file *m, void *v);
+#endif
+
+#define _drv_always_		1
+#define _drv_emerg_			2
+#define _drv_alert_			3
+#define _drv_crit_			4
+#define _drv_err_			5
+#define _drv_warning_		6
+#define _drv_notice_		7
+#define _drv_info_			8
+#define _drv_dump_			9
+#define _drv_debug_			10
+
+#define _module_rtl871x_xmit_c_		BIT(0)
+#define _module_xmit_osdep_c_		BIT(1)
+#define _module_rtl871x_recv_c_		BIT(2)
+#define _module_recv_osdep_c_		BIT(3)
+#define _module_rtl871x_mlme_c_		BIT(4)
+#define _module_mlme_osdep_c_		BIT(5)
+#define _module_rtl871x_sta_mgt_c_		BIT(6)
+#define _module_rtl871x_cmd_c_			BIT(7)
+#define _module_cmd_osdep_c_		BIT(8)
+#define _module_rtl871x_io_c_				BIT(9)
+#define _module_io_osdep_c_		BIT(10)
+#define _module_os_intfs_c_			BIT(11)
+#define _module_rtl871x_security_c_		BIT(12)
+#define _module_rtl871x_eeprom_c_			BIT(13)
+#define _module_hal_init_c_		BIT(14)
+#define _module_hci_hal_init_c_		BIT(15)
+#define _module_rtl871x_ioctl_c_		BIT(16)
+#define _module_rtl871x_ioctl_set_c_		BIT(17)
+#define _module_rtl871x_ioctl_query_c_	BIT(18)
+#define _module_rtl871x_pwrctrl_c_			BIT(19)
+#define _module_hci_intfs_c_			BIT(20)
+#define _module_hci_ops_c_			BIT(21)
+#define _module_osdep_service_c_			BIT(22)
+#define _module_mp_			BIT(23)
+#define _module_hci_ops_os_c_			BIT(24)
+#define _module_rtl871x_ioctl_os_c		BIT(25)
+#define _module_rtl8712_cmd_c_		BIT(26)
+/* #define _module_efuse_			BIT(27) */
+#define	_module_rtl8192c_xmit_c_ BIT(28)
+#define _module_hal_xmit_c_	BIT(28)
+#define _module_efuse_			BIT(29)
+#define _module_rtl8712_recv_c_		BIT(30)
+#define _module_rtl8712_led_c_		BIT(31)
+
+#endif /* __RTW_DEBUG_H__ */
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/include/rtw_eeprom.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/rtw_eeprom.h
--- linux-5.6.3/3rdparty/rtl8821ce/include/rtw_eeprom.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/rtw_eeprom.h	2020-04-10 16:35:06.851661701 +0300
@@ -0,0 +1,116 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#ifndef __RTW_EEPROM_H__
+#define __RTW_EEPROM_H__
+
+
+#define	RTL8712_EEPROM_ID			0x8712
+/* #define	EEPROM_MAX_SIZE			256 */
+
+#define	HWSET_MAX_SIZE_128		128
+#define	HWSET_MAX_SIZE_256		256
+#define	HWSET_MAX_SIZE_512		512
+#define HWSET_MAX_SIZE_1024		1024
+
+#define	EEPROM_MAX_SIZE			HWSET_MAX_SIZE_1024
+
+#define	CLOCK_RATE					50			/* 100us		 */
+
+/* - EEPROM opcodes */
+#define EEPROM_READ_OPCODE		06
+#define EEPROM_WRITE_OPCODE		05
+#define EEPROM_ERASE_OPCODE		07
+#define EEPROM_EWEN_OPCODE		19      /* Erase/write enable */
+#define EEPROM_EWDS_OPCODE		16      /* Erase/write disable */
+
+/* Country codes */
+#define USA							0x555320
+#define EUROPE						0x1 /* temp, should be provided later	 */
+#define JAPAN						0x2 /* temp, should be provided later */
+
+/*
+ * Customer ID, note that:
+ * This variable is initiailzed through EEPROM or registry,
+ * however, its definition may be different with that in EEPROM for
+ * EEPROM size consideration. So, we have to perform proper translation between them.
+ * Besides, CustomerID of registry has precedence of that of EEPROM.
+ * defined below. 060703, by rcnjko.
+ *   */
+typedef enum _RT_CUSTOMER_ID {
+	RT_CID_DEFAULT = 0,
+	RT_CID_8187_ALPHA0 = 1,
+	RT_CID_8187_SERCOMM_PS = 2,
+	RT_CID_8187_HW_LED = 3,
+	RT_CID_8187_NETGEAR = 4,
+	RT_CID_WHQL = 5,
+	RT_CID_819x_CAMEO  = 6,
+	RT_CID_819x_RUNTOP = 7,
+	RT_CID_819x_Senao = 8,
+	RT_CID_TOSHIBA = 9,	/* Merge by Jacken, 2008/01/31. */
+	RT_CID_819x_Netcore = 10,
+	RT_CID_Nettronix = 11,
+	RT_CID_DLINK = 12,
+	RT_CID_PRONET = 13,
+	RT_CID_COREGA = 14,
+	RT_CID_CHINA_MOBILE = 15,
+	RT_CID_819x_ALPHA = 16,
+	RT_CID_819x_Sitecom = 17,
+	RT_CID_CCX = 18, /* It's set under CCX logo test and isn't demanded for CCX functions, but for test behavior like retry limit and tx report. By Bruce, 2009-02-17. */
+	RT_CID_819X_LENOVO = 19,
+	RT_CID_819x_QMI = 20,
+	RT_CID_819x_Edimax_Belkin = 21,
+	RT_CID_819x_Sercomm_Belkin = 22,
+	RT_CID_819x_CAMEO1 = 23,
+	RT_CID_819x_MSI = 24,
+	RT_CID_819X_ACER = 25,
+	RT_CID_819x_AzWave_ASUS = 26,
+	RT_CID_819x_AzWave = 27, /* For AzWave in PCIe, The ID is AzWave use and not only Asus */
+	RT_CID_819x_HP = 28,
+	RT_CID_819x_WNC_COREGA = 29,
+	RT_CID_819x_Arcadyan_Belkin = 30,
+	RT_CID_819x_SAMSUNG = 31,
+	RT_CID_819x_CLEVO = 32,
+	RT_CID_819x_DELL = 33,
+	RT_CID_819x_PRONETS = 34,
+	RT_CID_819x_Edimax_ASUS = 35,
+	RT_CID_NETGEAR = 36,
+	RT_CID_PLANEX = 37,
+	RT_CID_CC_C = 38,
+	RT_CID_819x_Xavi = 39,
+	RT_CID_LENOVO_CHINA = 40,
+	RT_CID_INTEL_CHINA = 41,
+	RT_CID_TPLINK_HPWR = 42,
+	RT_CID_819x_Sercomm_Netgear = 43,
+	RT_CID_819x_ALPHA_Dlink = 44,/* add by ylb 20121012 for customer led for alpha */
+	RT_CID_WNC_NEC = 45,/* add by page for NEC */
+	RT_CID_DNI_BUFFALO = 46,/* add by page for NEC */
+} RT_CUSTOMER_ID, *PRT_CUSTOMER_ID;
+
+extern void eeprom_write16(_adapter *padapter, u16 reg, u16 data);
+extern u16 eeprom_read16(_adapter *padapter, u16 reg);
+extern void read_eeprom_content(_adapter *padapter);
+extern void eeprom_read_sz(_adapter *padapter, u16 reg, u8 *data, u32 sz);
+
+extern void read_eeprom_content_by_attrib(_adapter	*padapter);
+
+#ifdef PLATFORM_LINUX
+#ifdef CONFIG_ADAPTOR_INFO_CACHING_FILE
+extern int isAdaptorInfoFileValid(void);
+extern int storeAdaptorInfoFile(char *path, u8 *efuse_data);
+extern int retriveAdaptorInfoFile(char *path, u8 *efuse_data);
+#endif /* CONFIG_ADAPTOR_INFO_CACHING_FILE */
+#endif /* PLATFORM_LINUX */
+
+#endif /* __RTL871X_EEPROM_H__ */
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/include/rtw_efuse.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/rtw_efuse.h
--- linux-5.6.3/3rdparty/rtl8821ce/include/rtw_efuse.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/rtw_efuse.h	2020-04-10 16:35:06.851661701 +0300
@@ -0,0 +1,255 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#ifndef __RTW_EFUSE_H__
+#define __RTW_EFUSE_H__
+
+
+#define	EFUSE_ERROE_HANDLE		1
+
+#define	PG_STATE_HEADER		0x01
+#define	PG_STATE_WORD_0		0x02
+#define	PG_STATE_WORD_1		0x04
+#define	PG_STATE_WORD_2		0x08
+#define	PG_STATE_WORD_3		0x10
+#define	PG_STATE_DATA			0x20
+
+#define	PG_SWBYTE_H			0x01
+#define	PG_SWBYTE_L			0x02
+
+#define	PGPKT_DATA_SIZE		8
+
+#define	EFUSE_WIFI				0
+#define	EFUSE_BT				1
+
+enum _EFUSE_DEF_TYPE {
+	TYPE_EFUSE_MAX_SECTION				= 0,
+	TYPE_EFUSE_REAL_CONTENT_LEN			= 1,
+	TYPE_AVAILABLE_EFUSE_BYTES_BANK		= 2,
+	TYPE_AVAILABLE_EFUSE_BYTES_TOTAL	= 3,
+	TYPE_EFUSE_MAP_LEN					= 4,
+	TYPE_EFUSE_PROTECT_BYTES_BANK		= 5,
+	TYPE_EFUSE_CONTENT_LEN_BANK			= 6,
+};
+
+#define		EFUSE_MAX_MAP_LEN		1024
+
+#define		EFUSE_MAX_HW_SIZE		1024
+#define		EFUSE_MAX_SECTION_BASE	16
+#define		EFUSE_MAX_SECTION_NUM	128
+#define		EFUSE_MAX_BANK_SIZE		512
+
+/*RTL8822B 8821C BT EFUSE Define 1 BANK 128 size logical map 1024*/
+#ifdef RTW_HALMAC
+#define BANK_NUM		1
+#define EFUSE_BT_REAL_BANK_CONTENT_LEN	128
+#define EFUSE_BT_REAL_CONTENT_LEN		(EFUSE_BT_REAL_BANK_CONTENT_LEN * BANK_NUM)
+#define EFUSE_BT_MAP_LEN				1024	/* 1k bytes */
+#define EFUSE_BT_MAX_SECTION			(EFUSE_BT_MAP_LEN / 8)
+#define EFUSE_PROTECT_BYTES_BANK		16
+#define AVAILABLE_EFUSE_ADDR(addr)	(addr < EFUSE_BT_REAL_CONTENT_LEN)
+#endif
+
+#define EXT_HEADER(header) ((header & 0x1F) == 0x0F)
+#define ALL_WORDS_DISABLED(wde)	((wde & 0x0F) == 0x0F)
+#define GET_HDR_OFFSET_2_0(header) ((header & 0xE0) >> 5)
+
+#define		EFUSE_REPEAT_THRESHOLD_			3
+
+#define IS_MASKED_MP(ic, txt, offset) (EFUSE_IsAddressMasked_MP_##ic##txt(offset))
+#define IS_MASKED_TC(ic, txt, offset) (EFUSE_IsAddressMasked_TC_##ic##txt(offset))
+#define GET_MASK_ARRAY_LEN_MP(ic, txt) (EFUSE_GetArrayLen_MP_##ic##txt())
+#define GET_MASK_ARRAY_LEN_TC(ic, txt) (EFUSE_GetArrayLen_TC_##ic##txt())
+#define GET_MASK_ARRAY_MP(ic, txt, offset) (EFUSE_GetMaskArray_MP_##ic##txt(offset))
+#define GET_MASK_ARRAY_TC(ic, txt, offset) (EFUSE_GetMaskArray_TC_##ic##txt(offset))
+
+
+#define IS_MASKED(ic, txt, offset) (IS_MASKED_MP(ic, txt, offset))
+#define GET_MASK_ARRAY_LEN(ic, txt) (GET_MASK_ARRAY_LEN_MP(ic, txt))
+#define GET_MASK_ARRAY(ic, txt, out) do { GET_MASK_ARRAY_MP(ic, txt, out); } while (0)
+
+/* *********************************************
+ *	The following is for BT Efuse definition
+ * ********************************************* */
+#define		EFUSE_BT_MAX_MAP_LEN		1024
+#define		EFUSE_MAX_BANK			4
+#define		EFUSE_MAX_BT_BANK		(EFUSE_MAX_BANK-1)
+/* *********************************************
+ *--------------------------Define Parameters-------------------------------*/
+#define		EFUSE_MAX_WORD_UNIT			4
+
+/*------------------------------Define structure----------------------------*/
+typedef struct PG_PKT_STRUCT_A {
+	u8 offset;
+	u8 word_en;
+	u8 data[8];
+	u8 word_cnts;
+} PGPKT_STRUCT, *PPGPKT_STRUCT;
+
+typedef enum {
+	ERR_SUCCESS = 0,
+	ERR_DRIVER_FAILURE,
+	ERR_IO_FAILURE,
+	ERR_WI_TIMEOUT,
+	ERR_WI_BUSY,
+	ERR_BAD_FORMAT,
+	ERR_INVALID_DATA,
+	ERR_NOT_ENOUGH_SPACE,
+	ERR_WRITE_PROTECT,
+	ERR_READ_BACK_FAIL,
+	ERR_OUT_OF_RANGE
+} ERROR_CODE;
+
+/*------------------------------Define structure----------------------------*/
+typedef struct _EFUSE_HAL {
+	u8	fakeEfuseBank;
+	u32	fakeEfuseUsedBytes;
+	u8	fakeEfuseContent[EFUSE_MAX_HW_SIZE];
+	u8	fakeEfuseInitMap[EFUSE_MAX_MAP_LEN];
+	u8	fakeEfuseModifiedMap[EFUSE_MAX_MAP_LEN];
+	u32	EfuseUsedBytes;
+	u8	EfuseUsedPercentage;
+
+	u16	BTEfuseUsedBytes;
+	u8	BTEfuseUsedPercentage;
+	u8	BTEfuseContent[EFUSE_MAX_BT_BANK][EFUSE_MAX_HW_SIZE];
+	u8	BTEfuseInitMap[EFUSE_BT_MAX_MAP_LEN];
+	u8	BTEfuseModifiedMap[EFUSE_BT_MAX_MAP_LEN];
+
+	u16	fakeBTEfuseUsedBytes;
+	u8	fakeBTEfuseContent[EFUSE_MAX_BT_BANK][EFUSE_MAX_HW_SIZE];
+	u8	fakeBTEfuseInitMap[EFUSE_BT_MAX_MAP_LEN];
+	u8	fakeBTEfuseModifiedMap[EFUSE_BT_MAX_MAP_LEN];
+
+	/* EFUSE Configuration, initialized in HAL_CmnInitPGData(). */
+	const u16  MaxSecNum_WiFi;
+	const u16  MaxSecNum_BT;
+	const u16  WordUnit;
+	const u16  PhysicalLen_WiFi;
+	const u16  PhysicalLen_BT;
+	const u16  LogicalLen_WiFi;
+	const u16  LogicalLen_BT;
+	const u16  BankSize;
+	const u16  TotalBankNum;
+	const u16  BankNum_WiFi;
+	const u16  BankNum_BT;
+	const u16  OOBProtectBytes;
+	const u16  ProtectBytes;
+	const u16  BankAvailBytes;
+	const u16  TotalAvailBytes_WiFi;
+	const u16  TotalAvailBytes_BT;
+	const u16  HeaderRetry;
+	const u16  DataRetry;
+
+	ERROR_CODE	  Status;
+
+} EFUSE_HAL, *PEFUSE_HAL;
+
+extern u8 maskfileBuffer[64];
+
+/*------------------------Export global variable----------------------------*/
+extern u8 fakeEfuseBank;
+extern u32 fakeEfuseUsedBytes;
+extern u8 fakeEfuseContent[];
+extern u8 fakeEfuseInitMap[];
+extern u8 fakeEfuseModifiedMap[];
+
+extern u32 BTEfuseUsedBytes;
+extern u8 BTEfuseContent[EFUSE_MAX_BT_BANK][EFUSE_MAX_HW_SIZE];
+extern u8 BTEfuseInitMap[];
+extern u8 BTEfuseModifiedMap[];
+
+extern u32 fakeBTEfuseUsedBytes;
+extern u8 fakeBTEfuseContent[EFUSE_MAX_BT_BANK][EFUSE_MAX_HW_SIZE];
+extern u8 fakeBTEfuseInitMap[];
+extern u8 fakeBTEfuseModifiedMap[];
+/*------------------------Export global variable----------------------------*/
+#define		MAX_SEGMENT_SIZE			200
+#define		MAX_SEGMENT_NUM			200
+#define		MAX_BUF_SIZE				(MAX_SEGMENT_SIZE*MAX_SEGMENT_NUM)
+#define		TMP_BUF_SIZE				100
+#define		rtprintf					dcmd_Store_Return_Buf
+
+u8	efuse_bt_GetCurrentSize(PADAPTER padapter, u16 *size);
+u16	efuse_bt_GetMaxSize(PADAPTER padapter);
+u16 efuse_GetavailableSize(PADAPTER adapter);
+
+u8	efuse_GetCurrentSize(PADAPTER padapter, u16 *size);
+u16	efuse_GetMaxSize(PADAPTER padapter);
+u8	rtw_efuse_access(PADAPTER padapter, u8 bRead, u16 start_addr, u16 cnts, u8 *data);
+u8	rtw_efuse_bt_access(PADAPTER adapter, u8 write, u16 addr, u16 cnts, u8 *data);
+
+u8	rtw_efuse_mask_map_read(PADAPTER padapter, u16 addr, u16 cnts, u8 *data);
+u8	rtw_efuse_map_read(PADAPTER padapter, u16 addr, u16 cnts, u8 *data);
+u8	rtw_efuse_map_write(PADAPTER padapter, u16 addr, u16 cnts, u8 *data);
+u8	rtw_BT_efuse_map_read(PADAPTER padapter, u16 addr, u16 cnts, u8 *data);
+u8	rtw_BT_efuse_map_write(PADAPTER padapter, u16 addr, u16 cnts, u8 *data);
+
+u16	Efuse_GetCurrentSize(PADAPTER pAdapter, u8 efuseType, BOOLEAN bPseudoTest);
+u8	Efuse_CalculateWordCnts(u8 word_en);
+void	ReadEFuseByte(PADAPTER Adapter, u16 _offset, u8 *pbuf, BOOLEAN bPseudoTest) ;
+void	EFUSE_GetEfuseDefinition(PADAPTER pAdapter, u8 efuseType, u8 type, void *pOut, BOOLEAN bPseudoTest);
+u8	efuse_OneByteRead(PADAPTER pAdapter, u16 addr, u8 *data, BOOLEAN	 bPseudoTest);
+#define efuse_onebyte_read(adapter, addr, data, pseudo_test) efuse_OneByteRead((adapter), (addr), (data), (pseudo_test))
+
+u8	efuse_OneByteWrite(PADAPTER pAdapter, u16 addr, u8 data, BOOLEAN	 bPseudoTest);
+
+void	BTEfuse_PowerSwitch(PADAPTER pAdapter, u8	bWrite, u8	 PwrState);
+void	Efuse_PowerSwitch(PADAPTER pAdapter, u8	bWrite, u8	 PwrState);
+int	Efuse_PgPacketRead(PADAPTER pAdapter, u8 offset, u8 *data, BOOLEAN bPseudoTest);
+int	Efuse_PgPacketWrite(PADAPTER pAdapter, u8 offset, u8 word_en, u8 *data, BOOLEAN bPseudoTest);
+void	efuse_WordEnableDataRead(u8 word_en, u8 *sourdata, u8 *targetdata);
+u8	Efuse_WordEnableDataWrite(PADAPTER pAdapter, u16 efuse_addr, u8 word_en, u8 *data, BOOLEAN bPseudoTest);
+void	EFUSE_ShadowMapUpdate(PADAPTER pAdapter, u8 efuseType, BOOLEAN bPseudoTest);
+void	EFUSE_ShadowRead(PADAPTER pAdapter, u8 Type, u16 Offset, u32 *Value);
+#define efuse_logical_map_read(adapter, type, offset, value) EFUSE_ShadowRead((adapter), (type), (offset), (value))
+
+BOOLEAN rtw_file_efuse_IsMasked(PADAPTER pAdapter, u16 Offset);
+BOOLEAN efuse_IsMasked(PADAPTER pAdapter, u16 Offset);
+
+VOID	hal_ReadEFuse_BT_logic_map(
+	PADAPTER	padapter,
+	u16			_offset,
+	u16			_size_byte,
+	u8			*pbuf
+);
+u8	EfusePgPacketWrite_BT(
+	PADAPTER	pAdapter,
+	u8			offset,
+	u8			word_en,
+	u8			*pData,
+	u8			bPseudoTest);
+u16 rtw_get_efuse_mask_arraylen(PADAPTER pAdapter);
+void rtw_efuse_mask_array(PADAPTER pAdapter, u8 *pArray);
+void rtw_efuse_analyze(PADAPTER	padapter, u8 Type, u8 Fake);
+
+#define MAC_HIDDEN_MAX_BW_NUM 8
+extern const u8 _mac_hidden_max_bw_to_hal_bw_cap[];
+#define mac_hidden_max_bw_to_hal_bw_cap(max_bw) (((max_bw) >= MAC_HIDDEN_MAX_BW_NUM) ? 0 : _mac_hidden_max_bw_to_hal_bw_cap[(max_bw)])
+
+#define MAC_HIDDEN_PROTOCOL_NUM 4
+extern const u8 _mac_hidden_proto_to_hal_proto_cap[];
+#define mac_hidden_proto_to_hal_proto_cap(proto) (((proto) >= MAC_HIDDEN_PROTOCOL_NUM) ? 0 : _mac_hidden_proto_to_hal_proto_cap[(proto)])
+
+u8 mac_hidden_wl_func_to_hal_wl_func(u8 func);
+
+#ifdef PLATFORM_LINUX
+u8 rtw_efuse_file_read(PADAPTER padapter, u8 *filepatch, u8 *buf, u32 len);
+#ifdef CONFIG_EFUSE_CONFIG_FILE
+u32 rtw_read_efuse_from_file(const char *path, u8 *buf, int map_size);
+u32 rtw_read_macaddr_from_file(const char *path, u8 *buf);
+#endif /* CONFIG_EFUSE_CONFIG_FILE */
+#endif /* PLATFORM_LINUX */
+
+#endif
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/include/rtw_event.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/rtw_event.h
--- linux-5.6.3/3rdparty/rtl8821ce/include/rtw_event.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/rtw_event.h	2020-04-10 16:35:06.851661701 +0300
@@ -0,0 +1,130 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#ifndef _RTW_EVENT_H_
+#define _RTW_EVENT_H_
+
+#ifdef CONFIG_H2CLBK
+	#include <h2clbk.h>
+#endif
+
+/*
+Used to report a bss has been scanned
+
+*/
+struct survey_event	{
+	WLAN_BSSID_EX bss;
+};
+
+/*
+Used to report that the requested site survey has been done.
+
+bss_cnt indicates the number of bss that has been reported.
+
+
+*/
+struct surveydone_event {
+	unsigned int	bss_cnt;
+
+};
+
+/*
+Used to report the link result of joinning the given bss
+
+
+join_res:
+-1: authentication fail
+-2: association fail
+> 0: TID
+
+*/
+struct joinbss_event {
+	struct	wlan_network	network;
+};
+
+/*
+Used to report a given STA has joinned the created BSS.
+It is used in AP/Ad-HoC(M) mode.
+
+
+*/
+struct stassoc_event {
+	unsigned char macaddr[6];
+};
+
+struct stadel_event {
+	unsigned char macaddr[6];
+	unsigned char rsvd[2]; /* for reason */
+	unsigned char locally_generated;
+	int mac_id;
+};
+
+struct addba_event {
+	unsigned int tid;
+};
+
+struct wmm_event {
+	unsigned char wmm;
+};
+
+#ifdef CONFIG_H2CLBK
+struct c2hlbk_event {
+	unsigned char mac[6];
+	unsigned short	s0;
+	unsigned short	s1;
+	unsigned int	w0;
+	unsigned char	b0;
+	unsigned short  s2;
+	unsigned char	b1;
+	unsigned int	w1;
+};
+#endif/* CONFIG_H2CLBK */
+
+#define GEN_EVT_CODE(event)	event ## _EVT_
+
+
+
+struct fwevent {
+	u32	parmsize;
+	void (*event_callback)(_adapter *dev, u8 *pbuf);
+};
+
+
+#define C2HEVENT_SZ			32
+
+struct event_node {
+	unsigned char *node;
+	unsigned char evt_code;
+	unsigned short evt_sz;
+	volatile int	*caller_ff_tail;
+	int	caller_ff_sz;
+};
+
+struct c2hevent_queue {
+	volatile int	head;
+	volatile int	tail;
+	struct	event_node	nodes[C2HEVENT_SZ];
+	unsigned char	seq;
+};
+
+#define NETWORK_QUEUE_SZ	4
+
+struct network_queue {
+	volatile int	head;
+	volatile int	tail;
+	WLAN_BSSID_EX networks[NETWORK_QUEUE_SZ];
+};
+
+
+#endif /* _WLANEVENT_H_ */
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/include/rtw_ht.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/rtw_ht.h
--- linux-5.6.3/3rdparty/rtl8821ce/include/rtw_ht.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/rtw_ht.h	2020-04-10 16:35:06.851661701 +0300
@@ -0,0 +1,217 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#ifndef _RTW_HT_H_
+#define _RTW_HT_H_
+
+#define HT_CAP_IE_LEN 26
+#define HT_OP_IE_LEN 22
+
+struct ht_priv {
+	u8	ht_option;
+	u8	ampdu_enable;/* for enable Tx A-MPDU */
+	u8	tx_amsdu_enable;/* for enable Tx A-MSDU */
+	u8	bss_coexist;/* for 20/40 Bss coexist */
+
+	/* u8	baddbareq_issued[16]; */
+	u32	tx_amsdu_maxlen; /* 1: 8k, 0:4k ; default:8k, for tx */
+	u32	rx_ampdu_maxlen; /* for rx reordering ctrl win_sz, updated when join_callback. */
+
+	u8	rx_ampdu_min_spacing;
+
+	u8	ch_offset;/* PRIME_CHNL_OFFSET */
+	u8	sgi_20m;
+	u8	sgi_40m;
+
+	/* for processing Tx A-MPDU */
+	u8	agg_enable_bitmap;
+	/* u8	ADDBA_retry_count; */
+	u8	candidate_tid_bitmap;
+
+	u8	ldpc_cap;
+	u8	stbc_cap;
+	u8	beamform_cap;
+	u8	smps_cap; /*spatial multiplexing power save mode. 0:static SMPS, 1:dynamic SMPS, 3:SMPS disabled, 2:reserved*/
+
+	u8 op_present:1; /* ht_op is present */
+
+	struct rtw_ieee80211_ht_cap ht_cap;
+	u8 ht_op[HT_OP_IE_LEN];
+
+};
+
+#ifdef ROKU_PRIVATE
+struct ht_priv_infra_ap {
+
+	/*Infra mode, only store AP's info , not intersection of STA and AP*/
+	u8	channel_width_infra_ap;
+	u8	sgi_20m_infra_ap;
+	u8	sgi_40m_infra_ap;
+	u8	ldpc_cap_infra_ap;
+	u8	stbc_cap_infra_ap;
+	u8	MCS_set_infra_ap[16];
+	u8	Rx_ss_infra_ap;
+	u16	rx_highest_data_rate_infra_ap;
+};
+#endif /* ROKU_PRIVATE */
+
+typedef enum AGGRE_SIZE {
+	HT_AGG_SIZE_8K = 0,
+	HT_AGG_SIZE_16K = 1,
+	HT_AGG_SIZE_32K = 2,
+	HT_AGG_SIZE_64K = 3,
+	VHT_AGG_SIZE_128K = 4,
+	VHT_AGG_SIZE_256K = 5,
+	VHT_AGG_SIZE_512K = 6,
+	VHT_AGG_SIZE_1024K = 7,
+} AGGRE_SIZE_E, *PAGGRE_SIZE_E;
+
+#define	LDPC_HT_ENABLE_RX			BIT0
+#define	LDPC_HT_ENABLE_TX			BIT1
+#define	LDPC_HT_TEST_TX_ENABLE		BIT2
+#define	LDPC_HT_CAP_TX				BIT3
+
+#define	STBC_HT_ENABLE_RX			BIT0
+#define	STBC_HT_ENABLE_TX			BIT1
+#define	STBC_HT_TEST_TX_ENABLE		BIT2
+#define	STBC_HT_CAP_TX				BIT3
+
+/* ------------------------------------------------------------
+ * The HT Control field
+ * ------------------------------------------------------------ */
+#define SET_HT_CTRL_CSI_STEERING(_pEleStart, _val)			SET_BITS_TO_LE_1BYTE(((u8 *)(_pEleStart))+2, 6, 2, _val)
+#define SET_HT_CTRL_NDP_ANNOUNCEMENT(_pEleStart, _val)		SET_BITS_TO_LE_1BYTE(((u8 *)(_pEleStart))+3, 0, 1, _val)
+#define GET_HT_CTRL_NDP_ANNOUNCEMENT(_pEleStart)			LE_BITS_TO_1BYTE(((u8 *)(_pEleStart))+3, 0, 1)
+
+/* 20/40 BSS Coexist */
+#define SET_EXT_CAPABILITY_ELE_BSS_COEXIST(_pEleStart, _val)	SET_BITS_TO_LE_1BYTE(((u8 *)(_pEleStart)), 0, 1, _val)
+#define GET_EXT_CAPABILITY_ELE_BSS_COEXIST(_pEleStart)			LE_BITS_TO_1BYTE(((u8 *)(_pEleStart)), 0, 1)
+
+/* HT Capabilities Info field */
+#define HT_CAP_ELE_CAP_INFO(_pEleStart)					((u8 *)(_pEleStart))
+#define GET_HT_CAP_ELE_LDPC_CAP(_pEleStart)				LE_BITS_TO_1BYTE(((u8 *)(_pEleStart)), 0, 1)
+#define GET_HT_CAP_ELE_CHL_WIDTH(_pEleStart)			LE_BITS_TO_1BYTE(((u8 *)(_pEleStart)), 1, 1)
+#define GET_HT_CAP_ELE_SM_PS(_pEleStart)				LE_BITS_TO_1BYTE(((u8 *)(_pEleStart)), 2, 2)
+#define GET_HT_CAP_ELE_GREENFIELD(_pEleStart)			LE_BITS_TO_1BYTE(((u8 *)(_pEleStart)), 4, 1)
+#define GET_HT_CAP_ELE_SHORT_GI20M(_pEleStart)			LE_BITS_TO_1BYTE(((u8 *)(_pEleStart)), 5, 1)
+#define GET_HT_CAP_ELE_SHORT_GI40M(_pEleStart)			LE_BITS_TO_1BYTE(((u8 *)(_pEleStart)), 6, 1)
+#define GET_HT_CAP_ELE_TX_STBC(_pEleStart)				LE_BITS_TO_1BYTE(((u8 *)(_pEleStart)), 7, 1)
+#define GET_HT_CAP_ELE_RX_STBC(_pEleStart)				LE_BITS_TO_1BYTE(((u8 *)(_pEleStart))+1, 0, 2)
+#define GET_HT_CAP_ELE_DELAYED_BA(_pEleStart)			LE_BITS_TO_1BYTE(((u8 *)(_pEleStart))+1, 2, 1)
+#define GET_HT_CAP_ELE_MAX_AMSDU_LENGTH(_pEleStart)		LE_BITS_TO_1BYTE(((u8 *)(_pEleStart))+1, 3, 1)
+#define GET_HT_CAP_ELE_DSSS_CCK_40M(_pEleStart)			LE_BITS_TO_1BYTE(((u8 *)(_pEleStart))+1, 4, 1)
+#define GET_HT_CAP_ELE_FORTY_INTOLERANT(_pEleStart)		LE_BITS_TO_1BYTE(((u8 *)(_pEleStart))+1, 6, 1)
+#define GET_HT_CAP_ELE_LSIG_TXOP_PROTECT(_pEleStart)	LE_BITS_TO_1BYTE(((u8 *)(_pEleStart))+1, 7, 1)
+
+#define SET_HT_CAP_ELE_LDPC_CAP(_pEleStart, _val)			SET_BITS_TO_LE_1BYTE(((u8 *)(_pEleStart)), 0, 1, _val)
+#define SET_HT_CAP_ELE_CHL_WIDTH(_pEleStart, _val)			SET_BITS_TO_LE_1BYTE(((u8 *)(_pEleStart)), 1, 1, _val)
+#define SET_HT_CAP_ELE_SM_PS(_pEleStart, _val)				SET_BITS_TO_LE_1BYTE(((u8 *)(_pEleStart)), 2, 2, _val)
+#define SET_HT_CAP_ELE_GREENFIELD(_pEleStart, _val)			SET_BITS_TO_LE_1BYTE(((u8 *)(_pEleStart)), 4, 1, _val)
+#define SET_HT_CAP_ELE_SHORT_GI20M(_pEleStart, _val)		SET_BITS_TO_LE_1BYTE(((u8 *)(_pEleStart)), 5, 1, _val)
+#define SET_HT_CAP_ELE_SHORT_GI40M(_pEleStart, _val)		SET_BITS_TO_LE_1BYTE(((u8 *)(_pEleStart)), 6, 1, _val)
+#define SET_HT_CAP_ELE_TX_STBC(_pEleStart, _val)			SET_BITS_TO_LE_1BYTE(((u8 *)(_pEleStart)), 7, 1, _val)
+#define SET_HT_CAP_ELE_RX_STBC(_pEleStart, _val)			SET_BITS_TO_LE_1BYTE(((u8 *)(_pEleStart)) + 1, 0, 2, _val)
+#define SET_HT_CAP_ELE_DELAYED_BA(_pEleStart, _val)			SET_BITS_TO_LE_1BYTE(((u8 *)(_pEleStart)) + 1, 2, 1, _val)
+#define SET_HT_CAP_ELE_MAX_AMSDU_LENGTH(_pEleStart, _val)	SET_BITS_TO_LE_1BYTE(((u8 *)(_pEleStart)) + 1, 3, 1, _val)
+#define SET_HT_CAP_ELE_DSSS_CCK_40M(_pEleStart, _val)		SET_BITS_TO_LE_1BYTE(((u8 *)(_pEleStart)) + 1, 4, 1, _val)
+#define SET_HT_CAP_ELE_FORTY_INTOLERANT(_pEleStart, _val)	SET_BITS_TO_LE_1BYTE(((u8 *)(_pEleStart)) + 1, 6, 1, _val)
+#define SET_HT_CAP_ELE_LSIG_TXOP_PROTECT(_pEleStart, _val)	SET_BITS_TO_LE_1BYTE(((u8 *)(_pEleStart)) + 1, 7, 1, _val)
+
+/* A-MPDU Parameters field */
+#define HT_CAP_ELE_AMPDU_PARA(_pEleStart)				(((u8 *)(_pEleStart))+2)
+#define GET_HT_CAP_ELE_MAX_AMPDU_LEN_EXP(_pEleStart)	LE_BITS_TO_1BYTE(((u8 *)(_pEleStart))+2, 0, 2)
+#define GET_HT_CAP_ELE_MIN_MPDU_S_SPACE(_pEleStart)		LE_BITS_TO_1BYTE(((u8 *)(_pEleStart))+2, 2, 3)
+
+#define HT_AMPDU_PARA_FMT "%02x " \
+	"MAX AMPDU len:%u bytes, MIN MPDU Start Spacing:%u"
+
+#define HT_AMPDU_PARA_ARG(x) \
+	*((u8 *)(x)) \
+	, (1 << (13+GET_HT_CAP_ELE_MAX_AMPDU_LEN_EXP(((u8 *)x)-2)))-1 \
+	, GET_HT_CAP_ELE_MIN_MPDU_S_SPACE(((u8 *)x)-2)
+
+#define SET_HT_CAP_ELE_MAX_AMPDU_LEN_EXP(_pEleStart, _val)	SET_BITS_TO_LE_1BYTE(((u8 *)(_pEleStart)) + 2, 0, 2, _val)
+#define SET_HT_CAP_ELE_MIN_MPDU_S_SPACE(_pEleStart, _val)	SET_BITS_TO_LE_1BYTE(((u8 *)(_pEleStart)) + 2, 2, 3, _val)
+
+/* Supported MCS Set field */
+#define HT_CAP_ELE_SUP_MCS_SET(_pEleStart)				(((u8 *)(_pEleStart))+3)
+#define HT_CAP_ELE_RX_MCS_MAP(_pEleStart)				HT_CAP_ELE_SUP_MCS_SET(_pEleStart)
+#define GET_HT_CAP_ELE_RX_HIGHEST_DATA_RATE(_pEleStart)	LE_BITS_TO_2BYTE(((u8 *)(_pEleStart))+13, 0, 10)
+#define GET_HT_CAP_ELE_TX_MCS_DEF(_pEleStart)			LE_BITS_TO_1BYTE(((u8 *)(_pEleStart))+15, 0, 1)
+#define GET_HT_CAP_ELE_TRX_MCS_NEQ(_pEleStart)			LE_BITS_TO_1BYTE(((u8 *)(_pEleStart))+15, 1, 1)
+#define GET_HT_CAP_ELE_TX_MAX_SS(_pEleStart)			LE_BITS_TO_1BYTE(((u8 *)(_pEleStart))+15, 2, 2)
+#define GET_HT_CAP_ELE_TX_UEQM(_pEleStart)				LE_BITS_TO_1BYTE(((u8 *)(_pEleStart))+15, 4, 1)
+
+#define HT_RX_MCS_BMP_FMT "%02x %02x %02x %02x %02x%02x%02x%02x%02x%02x"
+#define HT_RX_MCS_BMP_ARG(x) ((u8 *)(x))[0], ((u8 *)(x))[1], ((u8 *)(x))[2], ((u8 *)(x))[3], ((u8 *)(x))[4], ((u8 *)(x))[5], \
+	((u8 *)(x))[6], ((u8 *)(x))[7], ((u8 *)(x))[8], ((u8 *)(x))[9]
+
+#define HT_SUP_MCS_SET_FMT HT_RX_MCS_BMP_FMT \
+	/* "\n%02x%02x%02x%02x%02x%02x" */\
+	" %uMbps %s%s%s"
+#define HT_SUP_MCS_SET_ARG(x) HT_RX_MCS_BMP_ARG(x) \
+	/*,((u8 *)(x))[10], ((u8 *)(x))[11], ((u8 *)(x))[12], ((u8 *)(x))[13], ((u8 *)(x))[14], ((u8 *)(x))[15] */\
+	, GET_HT_CAP_ELE_RX_HIGHEST_DATA_RATE(((u8 *)x)-3) \
+	, GET_HT_CAP_ELE_TX_MCS_DEF(((u8 *)x)-3) ? "TX_MCS_DEF " : "" \
+	, GET_HT_CAP_ELE_TRX_MCS_NEQ(((u8 *)x)-3) ? "TRX_MCS_NEQ " : "" \
+	, GET_HT_CAP_ELE_TX_UEQM(((u8 *)x)-3) ? "TX_UEQM " : ""
+
+/* TXBF Capabilities */
+#define SET_HT_CAP_TXBF_RECEIVE_NDP_CAP(_pEleStart, _val)				SET_BITS_TO_LE_4BYTE(((u8 *)(_pEleStart))+21, 3, 1, ((u8)_val))
+#define SET_HT_CAP_TXBF_TRANSMIT_NDP_CAP(_pEleStart, _val)				SET_BITS_TO_LE_4BYTE(((u8 *)(_pEleStart))+21, 4, 1, ((u8)_val))
+#define SET_HT_CAP_TXBF_EXPLICIT_COMP_STEERING_CAP(_pEleStart, _val)	SET_BITS_TO_LE_4BYTE(((u8 *)(_pEleStart))+21, 10, 1, ((u8)_val))
+#define SET_HT_CAP_TXBF_EXPLICIT_COMP_FEEDBACK_CAP(_pEleStart, _val)	SET_BITS_TO_LE_4BYTE(((u8 *)(_pEleStart))+21, 15, 2, ((u8)_val))
+#define SET_HT_CAP_TXBF_COMP_STEERING_NUM_ANTENNAS(_pEleStart, _val)	SET_BITS_TO_LE_4BYTE(((u8 *)(_pEleStart))+21, 23, 2, ((u8)_val))
+#define SET_HT_CAP_TXBF_CHNL_ESTIMATION_NUM_ANTENNAS(_pEleStart, _val)	SET_BITS_TO_LE_4BYTE(((u8 *)(_pEleStart))+21, 27, 2, ((u8)_val))
+
+
+#define GET_HT_CAP_TXBF_EXPLICIT_COMP_STEERING_CAP(_pEleStart)			LE_BITS_TO_4BYTE(((u8 *)(_pEleStart))+21, 10, 1)
+#define GET_HT_CAP_TXBF_EXPLICIT_COMP_FEEDBACK_CAP(_pEleStart)			LE_BITS_TO_4BYTE(((u8 *)(_pEleStart))+21, 15, 2)
+#define GET_HT_CAP_TXBF_COMP_STEERING_NUM_ANTENNAS(_pEleStart)		LE_BITS_TO_4BYTE(((u8 *)(_pEleStart))+21, 23, 2)
+#define GET_HT_CAP_TXBF_CHNL_ESTIMATION_NUM_ANTENNAS(_pEleStart)		LE_BITS_TO_4BYTE(((u8 *)(_pEleStart))+21, 27, 2)
+
+/* HT Operation element */
+
+#define GET_HT_OP_ELE_PRI_CHL(_pEleStart)					LE_BITS_TO_1BYTE(((u8 *)(_pEleStart)), 0, 8)
+#define SET_HT_OP_ELE_PRI_CHL(_pEleStart, _val)				SET_BITS_TO_LE_1BYTE(((u8 *)(_pEleStart)), 0, 8, _val)
+
+/* HT Operation Info field */
+#define HT_OP_ELE_OP_INFO(_pEleStart)						(((u8 *)(_pEleStart)) + 1)
+#define GET_HT_OP_ELE_2ND_CHL_OFFSET(_pEleStart)			LE_BITS_TO_1BYTE(((u8 *)(_pEleStart)) + 1, 0, 2)
+#define GET_HT_OP_ELE_STA_CHL_WIDTH(_pEleStart)				LE_BITS_TO_1BYTE(((u8 *)(_pEleStart)) + 1, 2, 1)
+#define GET_HT_OP_ELE_RIFS_MODE(_pEleStart)					LE_BITS_TO_1BYTE(((u8 *)(_pEleStart)) + 1, 3, 1)
+#define GET_HT_OP_ELE_HT_PROTECT(_pEleStart)				LE_BITS_TO_1BYTE(((u8 *)(_pEleStart)) + 2, 0, 2)
+#define GET_HT_OP_ELE_NON_GREEN_PRESENT(_pEleStart)			LE_BITS_TO_1BYTE(((u8 *)(_pEleStart)) + 2, 2, 1)
+#define GET_HT_OP_ELE_OBSS_NON_HT_PRESENT(_pEleStart)		LE_BITS_TO_1BYTE(((u8 *)(_pEleStart)) + 2, 4, 1)
+#define GET_HT_OP_ELE_DUAL_BEACON(_pEleStart)				LE_BITS_TO_1BYTE(((u8 *)(_pEleStart)) + 4, 6, 1)
+#define GET_HT_OP_ELE_DUAL_CTS(_pEleStart)					LE_BITS_TO_1BYTE(((u8 *)(_pEleStart)) + 4, 7, 1)
+#define GET_HT_OP_ELE_STBC_BEACON(_pEleStart)				LE_BITS_TO_1BYTE(((u8 *)(_pEleStart)) + 5, 0, 1)
+#define GET_HT_OP_ELE_LSIG_TXOP_PROTECT(_pEleStart)			LE_BITS_TO_1BYTE(((u8 *)(_pEleStart)) + 5, 1, 1)
+#define GET_HT_OP_ELE_PCO_ACTIVE(_pEleStart)				LE_BITS_TO_1BYTE(((u8 *)(_pEleStart)) + 5, 2, 1)
+#define GET_HT_OP_ELE_PCO_PHASE(_pEleStart)					LE_BITS_TO_1BYTE(((u8 *)(_pEleStart)) + 5, 3, 1)
+
+#define SET_HT_OP_ELE_2ND_CHL_OFFSET(_pEleStart, _val)		SET_BITS_TO_LE_1BYTE(((u8 *)(_pEleStart)) + 1, 0, 2, _val)
+#define SET_HT_OP_ELE_STA_CHL_WIDTH(_pEleStart, _val)		SET_BITS_TO_LE_1BYTE(((u8 *)(_pEleStart)) + 1, 2, 1, _val)
+#define SET_HT_OP_ELE_RIFS_MODE(_pEleStart, _val)			SET_BITS_TO_LE_1BYTE(((u8 *)(_pEleStart)) + 1, 3, 1, _val)
+#define SET_HT_OP_ELE_HT_PROTECT(_pEleStart, _val)			SET_BITS_TO_LE_1BYTE(((u8 *)(_pEleStart)) + 2, 0, 2, _val)
+#define SET_HT_OP_ELE_NON_GREEN_PRESENT(_pEleStart, _val)	SET_BITS_TO_LE_1BYTE(((u8 *)(_pEleStart)) + 2, 2, 1, _val)
+#define SET_HT_OP_ELE_OBSS_NON_HT_PRESENT(_pEleStart, _val)	SET_BITS_TO_LE_1BYTE(((u8 *)(_pEleStart)) + 2, 4, 1, _val)
+#define SET_HT_OP_ELE_DUAL_BEACON(_pEleStart, _val)			SET_BITS_TO_LE_1BYTE(((u8 *)(_pEleStart)) + 4, 6, 1, _val)
+#define SET_HT_OP_ELE_DUAL_CTS(_pEleStart, _val)			SET_BITS_TO_LE_1BYTE(((u8 *)(_pEleStart)) + 4, 7, 1, _val)
+#define SET_HT_OP_ELE_STBC_BEACON(_pEleStart, _val)			SET_BITS_TO_LE_1BYTE(((u8 *)(_pEleStart)) + 5, 0, 1, _val)
+#define SET_HT_OP_ELE_LSIG_TXOP_PROTECT(_pEleStart, _val)	SET_BITS_TO_LE_1BYTE(((u8 *)(_pEleStart)) + 5, 1, 1, _val)
+#define SET_HT_OP_ELE_PCO_ACTIVE(_pEleStart, _val)			SET_BITS_TO_LE_1BYTE(((u8 *)(_pEleStart)) + 5, 2, 1, _val)
+#define SET_HT_OP_ELE_PCO_PHASE(_pEleStart, _val)			SET_BITS_TO_LE_1BYTE(((u8 *)(_pEleStart)) + 5, 3, 1, _val)
+
+#endif /* _RTL871X_HT_H_ */
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/include/rtw_ioctl.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/rtw_ioctl.h
--- linux-5.6.3/3rdparty/rtl8821ce/include/rtw_ioctl.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/rtw_ioctl.h	2020-04-10 16:35:06.851661701 +0300
@@ -0,0 +1,319 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#ifndef _RTW_IOCTL_H_
+#define _RTW_IOCTL_H_
+
+#ifndef PLATFORM_WINDOWS
+/*	00 - Success
+*	11 - Error */
+#define STATUS_SUCCESS				(0x00000000L)
+#define STATUS_PENDING				(0x00000103L)
+
+#define STATUS_UNSUCCESSFUL			(0xC0000001L)
+#define STATUS_INSUFFICIENT_RESOURCES		(0xC000009AL)
+#define STATUS_NOT_SUPPORTED			(0xC00000BBL)
+
+#define NDIS_STATUS_SUCCESS			((NDIS_STATUS)STATUS_SUCCESS)
+#define NDIS_STATUS_PENDING			((NDIS_STATUS)STATUS_PENDING)
+#define NDIS_STATUS_NOT_RECOGNIZED		((NDIS_STATUS)0x00010001L)
+#define NDIS_STATUS_NOT_COPIED			((NDIS_STATUS)0x00010002L)
+#define NDIS_STATUS_NOT_ACCEPTED		((NDIS_STATUS)0x00010003L)
+#define NDIS_STATUS_CALL_ACTIVE			((NDIS_STATUS)0x00010007L)
+
+#define NDIS_STATUS_FAILURE			((NDIS_STATUS)STATUS_UNSUCCESSFUL)
+#define NDIS_STATUS_RESOURCES			((NDIS_STATUS)STATUS_INSUFFICIENT_RESOURCES)
+#define NDIS_STATUS_CLOSING			((NDIS_STATUS)0xC0010002L)
+#define NDIS_STATUS_BAD_VERSION			((NDIS_STATUS)0xC0010004L)
+#define NDIS_STATUS_BAD_CHARACTERISTICS		((NDIS_STATUS)0xC0010005L)
+#define NDIS_STATUS_ADAPTER_NOT_FOUND		((NDIS_STATUS)0xC0010006L)
+#define NDIS_STATUS_OPEN_FAILED			((NDIS_STATUS)0xC0010007L)
+#define NDIS_STATUS_DEVICE_FAILED		((NDIS_STATUS)0xC0010008L)
+#define NDIS_STATUS_MULTICAST_FULL		((NDIS_STATUS)0xC0010009L)
+#define NDIS_STATUS_MULTICAST_EXISTS		((NDIS_STATUS)0xC001000AL)
+#define NDIS_STATUS_MULTICAST_NOT_FOUND		((NDIS_STATUS)0xC001000BL)
+#define NDIS_STATUS_REQUEST_ABORTED		((NDIS_STATUS)0xC001000CL)
+#define NDIS_STATUS_RESET_IN_PROGRESS		((NDIS_STATUS)0xC001000DL)
+#define NDIS_STATUS_CLOSING_INDICATING		((NDIS_STATUS)0xC001000EL)
+#define NDIS_STATUS_NOT_SUPPORTED		((NDIS_STATUS)STATUS_NOT_SUPPORTED)
+#define NDIS_STATUS_INVALID_PACKET		((NDIS_STATUS)0xC001000FL)
+#define NDIS_STATUS_OPEN_LIST_FULL		((NDIS_STATUS)0xC0010010L)
+#define NDIS_STATUS_ADAPTER_NOT_READY		((NDIS_STATUS)0xC0010011L)
+#define NDIS_STATUS_ADAPTER_NOT_OPEN		((NDIS_STATUS)0xC0010012L)
+#define NDIS_STATUS_NOT_INDICATING		((NDIS_STATUS)0xC0010013L)
+#define NDIS_STATUS_INVALID_LENGTH		((NDIS_STATUS)0xC0010014L)
+#define NDIS_STATUS_INVALID_DATA		((NDIS_STATUS)0xC0010015L)
+#define NDIS_STATUS_BUFFER_TOO_SHORT		((NDIS_STATUS)0xC0010016L)
+#define NDIS_STATUS_INVALID_OID			((NDIS_STATUS)0xC0010017L)
+#define NDIS_STATUS_ADAPTER_REMOVED		((NDIS_STATUS)0xC0010018L)
+#define NDIS_STATUS_UNSUPPORTED_MEDIA		((NDIS_STATUS)0xC0010019L)
+#define NDIS_STATUS_GROUP_ADDRESS_IN_USE	((NDIS_STATUS)0xC001001AL)
+#define NDIS_STATUS_FILE_NOT_FOUND		((NDIS_STATUS)0xC001001BL)
+#define NDIS_STATUS_ERROR_READING_FILE		((NDIS_STATUS)0xC001001CL)
+#define NDIS_STATUS_ALREADY_MAPPED		((NDIS_STATUS)0xC001001DL)
+#define NDIS_STATUS_RESOURCE_CONFLICT		((NDIS_STATUS)0xC001001EL)
+#define NDIS_STATUS_NO_CABLE			((NDIS_STATUS)0xC001001FL)
+
+#define NDIS_STATUS_INVALID_SAP			((NDIS_STATUS)0xC0010020L)
+#define NDIS_STATUS_SAP_IN_USE			((NDIS_STATUS)0xC0010021L)
+#define NDIS_STATUS_INVALID_ADDRESS		((NDIS_STATUS)0xC0010022L)
+#define NDIS_STATUS_VC_NOT_ACTIVATED		((NDIS_STATUS)0xC0010023L)
+#define NDIS_STATUS_DEST_OUT_OF_ORDER		((NDIS_STATUS)0xC0010024L)  /* cause 27 */
+#define NDIS_STATUS_VC_NOT_AVAILABLE		((NDIS_STATUS)0xC0010025L)  /* cause 35, 45 */
+#define NDIS_STATUS_CELLRATE_NOT_AVAILABLE	((NDIS_STATUS)0xC0010026L)  /* cause 37 */
+#define NDIS_STATUS_INCOMPATABLE_QOS		((NDIS_STATUS)0xC0010027L)  /* cause 49 */
+#define NDIS_STATUS_AAL_PARAMS_UNSUPPORTED	((NDIS_STATUS)0xC0010028L)  /* cause 93 */
+#define NDIS_STATUS_NO_ROUTE_TO_DESTINATION	((NDIS_STATUS)0xC0010029L)  /* cause 3 */
+#endif /* #ifndef PLATFORM_WINDOWS */
+
+
+#ifndef OID_802_11_CAPABILITY
+	#define OID_802_11_CAPABILITY                   0x0d010122
+#endif
+
+#ifndef OID_802_11_PMKID
+	#define OID_802_11_PMKID                        0x0d010123
+#endif
+
+
+/* For DDK-defined OIDs */
+#define OID_NDIS_SEG1	0x00010100
+#define OID_NDIS_SEG2	0x00010200
+#define OID_NDIS_SEG3	0x00020100
+#define OID_NDIS_SEG4	0x01010100
+#define OID_NDIS_SEG5	0x01020100
+#define OID_NDIS_SEG6	0x01020200
+#define OID_NDIS_SEG7	0xFD010100
+#define OID_NDIS_SEG8	0x0D010100
+#define OID_NDIS_SEG9	0x0D010200
+#define OID_NDIS_SEG10	0x0D020200
+
+#define SZ_OID_NDIS_SEG1		  23
+#define SZ_OID_NDIS_SEG2		    3
+#define SZ_OID_NDIS_SEG3		    6
+#define SZ_OID_NDIS_SEG4		    6
+#define SZ_OID_NDIS_SEG5		    4
+#define SZ_OID_NDIS_SEG6		    8
+#define SZ_OID_NDIS_SEG7		    7
+#define SZ_OID_NDIS_SEG8		  36
+#define SZ_OID_NDIS_SEG9		  24
+#define SZ_OID_NDIS_SEG10		  19
+
+/* For Realtek-defined OIDs */
+#define OID_MP_SEG1		0xFF871100
+#define OID_MP_SEG2		0xFF818000
+
+#define OID_MP_SEG3		0xFF818700
+#define OID_MP_SEG4		0xFF011100
+
+enum oid_type {
+	QUERY_OID,
+	SET_OID
+};
+
+struct oid_funs_node {
+	unsigned int oid_start; /* the starting number for OID */
+	unsigned int oid_end; /* the ending number for OID */
+	struct oid_obj_priv *node_array;
+	unsigned int array_sz; /* the size of node_array */
+	int query_counter; /* count the number of query hits for this segment  */
+	int set_counter; /* count the number of set hits for this segment  */
+};
+
+struct oid_par_priv {
+	void		*adapter_context;
+	NDIS_OID	oid;
+	void		*information_buf;
+	u32		information_buf_len;
+	u32		*bytes_rw;
+	u32		*bytes_needed;
+	enum oid_type	type_of_oid;
+	u32		dbg;
+};
+
+struct oid_obj_priv {
+	unsigned char	dbg; /* 0: without OID debug message  1: with OID debug message */
+	NDIS_STATUS(*oidfuns)(struct oid_par_priv *poid_par_priv);
+};
+
+#if (defined(CONFIG_MP_INCLUDED) && defined(_RTW_MP_IOCTL_C_)) || \
+	(defined(PLATFORM_WINDOWS) && defined(_RTW_IOCTL_RTL_C_))
+static NDIS_STATUS oid_null_function(struct oid_par_priv *poid_par_priv)
+{
+	return NDIS_STATUS_SUCCESS;
+}
+#endif
+
+#ifdef PLATFORM_WINDOWS
+
+int TranslateNdisPsToRtPs(IN NDIS_802_11_POWER_MODE	ndisPsMode);
+
+/* OID Handler for Segment 1 */
+NDIS_STATUS oid_gen_supported_list_hdl(struct oid_par_priv *poid_par_priv);
+NDIS_STATUS oid_gen_hardware_status_hdl(struct oid_par_priv *poid_par_priv);
+NDIS_STATUS oid_gen_media_supported_hdl(struct oid_par_priv *poid_par_priv);
+NDIS_STATUS oid_gen_media_in_use_hdl(struct oid_par_priv *poid_par_priv);
+NDIS_STATUS oid_gen_maximum_lookahead_hdl(struct oid_par_priv *poid_par_priv);
+NDIS_STATUS oid_gen_maximum_frame_size_hdl(struct oid_par_priv *poid_par_priv);
+NDIS_STATUS oid_gen_link_speed_hdl(struct oid_par_priv *poid_par_priv);
+NDIS_STATUS oid_gen_transmit_buffer_space_hdl(struct oid_par_priv *poid_par_priv);
+NDIS_STATUS oid_gen_receive_buffer_space_hdl(struct oid_par_priv *poid_par_priv);
+NDIS_STATUS oid_gen_transmit_block_size_hdl(struct oid_par_priv *poid_par_priv);
+NDIS_STATUS oid_gen_receive_block_size_hdl(struct oid_par_priv *poid_par_priv);
+NDIS_STATUS oid_gen_vendor_id_hdl(struct oid_par_priv *poid_par_priv);
+NDIS_STATUS oid_gen_vendor_description_hdl(struct oid_par_priv *poid_par_priv);
+NDIS_STATUS oid_gen_current_packet_filter_hdl(struct oid_par_priv *poid_par_priv);
+NDIS_STATUS oid_gen_current_lookahead_hdl(struct oid_par_priv *poid_par_priv);
+NDIS_STATUS oid_gen_driver_version_hdl(struct oid_par_priv *poid_par_priv);
+NDIS_STATUS oid_gen_maximum_total_size_hdl(struct oid_par_priv *poid_par_priv);
+NDIS_STATUS oid_gen_protocol_options_hdl(struct oid_par_priv *poid_par_priv);
+NDIS_STATUS oid_gen_mac_options_hdl(struct oid_par_priv *poid_par_priv);
+NDIS_STATUS oid_gen_media_connect_status_hdl(struct oid_par_priv *poid_par_priv);
+NDIS_STATUS oid_gen_maximum_send_packets_hdl(struct oid_par_priv *poid_par_priv);
+NDIS_STATUS oid_gen_vendor_driver_version_hdl(struct oid_par_priv *poid_par_priv);
+
+
+/* OID Handler for Segment 2 */
+NDIS_STATUS oid_gen_physical_medium_hdl(struct oid_par_priv *poid_par_priv);
+
+/* OID Handler for Segment 3 */
+NDIS_STATUS oid_gen_xmit_ok_hdl(struct oid_par_priv *poid_par_priv);
+NDIS_STATUS oid_gen_rcv_ok_hdl(struct oid_par_priv *poid_par_priv);
+NDIS_STATUS oid_gen_xmit_error_hdl(struct oid_par_priv *poid_par_priv);
+NDIS_STATUS oid_gen_rcv_error_hdl(struct oid_par_priv *poid_par_priv);
+NDIS_STATUS oid_gen_rcv_no_buffer_hdl(struct oid_par_priv *poid_par_priv);
+
+
+/* OID Handler for Segment 4 */
+NDIS_STATUS oid_802_3_permanent_address_hdl(struct oid_par_priv *poid_par_priv);
+NDIS_STATUS oid_802_3_current_address_hdl(struct oid_par_priv *poid_par_priv);
+NDIS_STATUS oid_802_3_multicast_list_hdl(struct oid_par_priv *poid_par_priv);
+NDIS_STATUS oid_802_3_maximum_list_size_hdl(struct oid_par_priv *poid_par_priv);
+NDIS_STATUS oid_802_3_mac_options_hdl(struct oid_par_priv *poid_par_priv);
+
+
+
+/* OID Handler for Segment 5 */
+NDIS_STATUS oid_802_3_rcv_error_alignment_hdl(struct oid_par_priv *poid_par_priv);
+NDIS_STATUS oid_802_3_xmit_one_collision_hdl(struct oid_par_priv *poid_par_priv);
+NDIS_STATUS oid_802_3_xmit_more_collisions_hdl(struct oid_par_priv *poid_par_priv);
+
+
+/* OID Handler for Segment 6 */
+NDIS_STATUS oid_802_3_xmit_deferred_hdl(struct oid_par_priv *poid_par_priv);
+NDIS_STATUS oid_802_3_xmit_max_collisions_hdl(struct oid_par_priv *poid_par_priv);
+NDIS_STATUS oid_802_3_rcv_overrun_hdl(struct oid_par_priv *poid_par_priv);
+NDIS_STATUS oid_802_3_xmit_underrun_hdl(struct oid_par_priv *poid_par_priv);
+NDIS_STATUS oid_802_3_xmit_heartbeat_failure_hdl(struct oid_par_priv *poid_par_priv);
+NDIS_STATUS oid_802_3_xmit_times_crs_lost_hdl(struct oid_par_priv *poid_par_priv);
+NDIS_STATUS oid_802_3_xmit_late_collisions_hdl(struct oid_par_priv *poid_par_priv);
+
+
+
+/* OID Handler for Segment 7 */
+NDIS_STATUS oid_pnp_capabilities_hdl(struct oid_par_priv *poid_par_priv);
+NDIS_STATUS oid_pnp_set_power_hdl(struct oid_par_priv *poid_par_priv);
+NDIS_STATUS oid_pnp_query_power_hdl(struct oid_par_priv *poid_par_priv);
+NDIS_STATUS oid_pnp_add_wake_up_pattern_hdl(struct oid_par_priv *poid_par_priv);
+NDIS_STATUS oid_pnp_remove_wake_up_pattern_hdl(struct oid_par_priv *poid_par_priv);
+NDIS_STATUS oid_pnp_wake_up_pattern_list_hdl(struct oid_par_priv *poid_par_priv);
+NDIS_STATUS oid_pnp_enable_wake_up_hdl(struct oid_par_priv *poid_par_priv);
+
+
+
+/* OID Handler for Segment 8 */
+NDIS_STATUS oid_802_11_bssid_hdl(struct oid_par_priv *poid_par_priv);
+NDIS_STATUS oid_802_11_ssid_hdl(struct oid_par_priv *poid_par_priv);
+NDIS_STATUS oid_802_11_infrastructure_mode_hdl(struct oid_par_priv *poid_par_priv);
+NDIS_STATUS oid_802_11_add_wep_hdl(struct oid_par_priv *poid_par_priv);
+NDIS_STATUS oid_802_11_remove_wep_hdl(struct oid_par_priv *poid_par_priv);
+NDIS_STATUS oid_802_11_disassociate_hdl(struct oid_par_priv *poid_par_priv);
+NDIS_STATUS oid_802_11_authentication_mode_hdl(struct oid_par_priv *poid_par_priv);
+NDIS_STATUS oid_802_11_privacy_filter_hdl(struct oid_par_priv *poid_par_priv);
+NDIS_STATUS oid_802_11_bssid_list_scan_hdl(struct oid_par_priv *poid_par_priv);
+NDIS_STATUS oid_802_11_encryption_status_hdl(struct oid_par_priv *poid_par_priv);
+NDIS_STATUS oid_802_11_reload_defaults_hdl(struct oid_par_priv *poid_par_priv);
+NDIS_STATUS oid_802_11_add_key_hdl(struct oid_par_priv *poid_par_priv);
+NDIS_STATUS oid_802_11_remove_key_hdl(struct oid_par_priv *poid_par_priv);
+NDIS_STATUS oid_802_11_association_information_hdl(struct oid_par_priv *poid_par_priv);
+NDIS_STATUS oid_802_11_test_hdl(struct oid_par_priv *poid_par_priv);
+NDIS_STATUS oid_802_11_media_stream_mode_hdl(struct oid_par_priv *poid_par_priv);
+NDIS_STATUS oid_802_11_capability_hdl(struct oid_par_priv *poid_par_priv);
+NDIS_STATUS oid_802_11_pmkid_hdl(struct oid_par_priv *poid_par_priv);
+
+
+
+
+
+/* OID Handler for Segment 9 */
+NDIS_STATUS oid_802_11_network_types_supported_hdl(struct oid_par_priv *poid_par_priv);
+NDIS_STATUS oid_802_11_network_type_in_use_hdl(struct oid_par_priv *poid_par_priv);
+NDIS_STATUS oid_802_11_tx_power_level_hdl(struct oid_par_priv *poid_par_priv);
+NDIS_STATUS oid_802_11_rssi_hdl(struct oid_par_priv *poid_par_priv);
+NDIS_STATUS oid_802_11_rssi_trigger_hdl(struct oid_par_priv *poid_par_priv);
+NDIS_STATUS oid_802_11_fragmentation_threshold_hdl(struct oid_par_priv *poid_par_priv);
+NDIS_STATUS oid_802_11_rts_threshold_hdl(struct oid_par_priv *poid_par_priv);
+NDIS_STATUS oid_802_11_number_of_antennas_hdl(struct oid_par_priv *poid_par_priv);
+NDIS_STATUS oid_802_11_rx_antenna_selected_hdl(struct oid_par_priv *poid_par_priv);
+NDIS_STATUS oid_802_11_tx_antenna_selected_hdl(struct oid_par_priv *poid_par_priv);
+NDIS_STATUS oid_802_11_supported_rates_hdl(struct oid_par_priv *poid_par_priv);
+NDIS_STATUS oid_802_11_desired_rates_hdl(struct oid_par_priv *poid_par_priv);
+NDIS_STATUS oid_802_11_configuration_hdl(struct oid_par_priv *poid_par_priv);
+NDIS_STATUS oid_802_11_power_mode_hdl(struct oid_par_priv *poid_par_priv);
+NDIS_STATUS oid_802_11_bssid_list_hdl(struct oid_par_priv *poid_par_priv);
+
+
+/* OID Handler for Segment 10 */
+NDIS_STATUS oid_802_11_statistics_hdl(struct oid_par_priv *poid_par_priv);
+
+
+/* OID Handler for Segment ED */
+NDIS_STATUS oid_rt_mh_vender_id_hdl(struct oid_par_priv *poid_par_priv);
+
+void Set_802_3_MULTICAST_LIST(ADAPTER *pAdapter, UCHAR *MCListbuf, ULONG MCListlen, BOOLEAN bAcceptAllMulticast);
+
+#endif/* end of PLATFORM_WINDOWS */
+
+#if defined(PLATFORM_LINUX) && defined(CONFIG_WIRELESS_EXT)
+extern struct iw_handler_def  rtw_handlers_def;
+#endif
+
+extern void rtw_request_wps_pbc_event(_adapter *padapter);
+
+extern	NDIS_STATUS drv_query_info(
+	IN	_nic_hdl		MiniportAdapterContext,
+	IN	NDIS_OID		Oid,
+	IN	void			*InformationBuffer,
+	IN	u32			InformationBufferLength,
+	OUT	u32			*BytesWritten,
+	OUT	u32			*BytesNeeded
+);
+
+extern	NDIS_STATUS	drv_set_info(
+	IN	_nic_hdl		MiniportAdapterContext,
+	IN	NDIS_OID		Oid,
+	IN	void			*InformationBuffer,
+	IN	u32			InformationBufferLength,
+	OUT	u32			*BytesRead,
+	OUT	u32			*BytesNeeded
+);
+
+#ifdef CONFIG_APPEND_VENDOR_IE_ENABLE
+extern int rtw_vendor_ie_get_raw_data(struct net_device *, u32, char *, u32);
+extern int rtw_vendor_ie_get_data(struct net_device*, int , char*);
+extern int rtw_vendor_ie_get(struct net_device *, struct iw_request_info *, union iwreq_data *, char *);
+extern int rtw_vendor_ie_set(struct net_device*, struct iw_request_info*, union iwreq_data*, char*);
+#endif
+
+#endif /*  #ifndef __INC_CEINFO_ */
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/include/rtw_ioctl_query.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/rtw_ioctl_query.h
--- linux-5.6.3/3rdparty/rtl8821ce/include/rtw_ioctl_query.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/rtw_ioctl_query.h	2020-04-10 16:35:06.851661701 +0300
@@ -0,0 +1,25 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#ifndef _RTW_IOCTL_QUERY_H_
+#define _RTW_IOCTL_QUERY_H_
+
+
+#ifdef PLATFORM_WINDOWS
+u8 query_802_11_capability(_adapter	*padapter, u8 *pucBuf, u32 *pulOutLen);
+u8 query_802_11_association_information(_adapter *padapter, PNDIS_802_11_ASSOCIATION_INFORMATION pAssocInfo);
+#endif
+
+
+#endif
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/include/rtw_ioctl_rtl.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/rtw_ioctl_rtl.h
--- linux-5.6.3/3rdparty/rtl8821ce/include/rtw_ioctl_rtl.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/rtw_ioctl_rtl.h	2020-04-10 16:35:06.851661701 +0300
@@ -0,0 +1,75 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#ifndef _RTW_IOCTL_RTL_H_
+#define _RTW_IOCTL_RTL_H_
+
+
+/* ************** oid_rtl_seg_01_01 ************** */
+NDIS_STATUS oid_rt_get_signal_quality_hdl(struct oid_par_priv *poid_par_priv);/* 84 */
+NDIS_STATUS oid_rt_get_small_packet_crc_hdl(struct oid_par_priv *poid_par_priv);
+NDIS_STATUS oid_rt_get_middle_packet_crc_hdl(struct oid_par_priv *poid_par_priv);
+NDIS_STATUS oid_rt_get_large_packet_crc_hdl(struct oid_par_priv *poid_par_priv);
+NDIS_STATUS oid_rt_get_tx_retry_hdl(struct oid_par_priv *poid_par_priv);
+NDIS_STATUS oid_rt_get_rx_retry_hdl(struct oid_par_priv *poid_par_priv);
+NDIS_STATUS oid_rt_get_rx_total_packet_hdl(struct oid_par_priv *poid_par_priv);
+NDIS_STATUS oid_rt_get_tx_beacon_ok_hdl(struct oid_par_priv *poid_par_priv);
+NDIS_STATUS oid_rt_get_tx_beacon_err_hdl(struct oid_par_priv *poid_par_priv);
+
+NDIS_STATUS oid_rt_pro_set_fw_dig_state_hdl(struct oid_par_priv *poid_par_priv);	/* 8a */
+NDIS_STATUS oid_rt_pro_set_fw_ra_state_hdl(struct oid_par_priv *poid_par_priv);	/* 8b */
+
+NDIS_STATUS oid_rt_get_rx_icv_err_hdl(struct oid_par_priv *poid_par_priv);/* 93 */
+NDIS_STATUS oid_rt_set_encryption_algorithm_hdl(struct oid_par_priv *poid_par_priv);
+NDIS_STATUS oid_rt_get_preamble_mode_hdl(struct oid_par_priv *poid_par_priv);
+NDIS_STATUS oid_rt_get_ap_ip_hdl(struct oid_par_priv *poid_par_priv);
+NDIS_STATUS oid_rt_get_channelplan_hdl(struct oid_par_priv *poid_par_priv);
+NDIS_STATUS oid_rt_set_channelplan_hdl(struct oid_par_priv *poid_par_priv);
+NDIS_STATUS oid_rt_set_preamble_mode_hdl(struct oid_par_priv *poid_par_priv);
+NDIS_STATUS oid_rt_set_bcn_intvl_hdl(struct oid_par_priv *poid_par_priv);
+NDIS_STATUS oid_rt_dedicate_probe_hdl(struct oid_par_priv *poid_par_priv);
+NDIS_STATUS oid_rt_get_total_tx_bytes_hdl(struct oid_par_priv *poid_par_priv);
+NDIS_STATUS oid_rt_get_total_rx_bytes_hdl(struct oid_par_priv *poid_par_priv);
+NDIS_STATUS oid_rt_current_tx_power_level_hdl(struct oid_par_priv *poid_par_priv);
+NDIS_STATUS oid_rt_get_enc_key_mismatch_count_hdl(struct oid_par_priv *poid_par_priv);
+NDIS_STATUS oid_rt_get_enc_key_match_count_hdl(struct oid_par_priv *poid_par_priv);
+NDIS_STATUS oid_rt_get_channel_hdl(struct oid_par_priv *poid_par_priv);
+NDIS_STATUS oid_rt_get_hardware_radio_off_hdl(struct oid_par_priv *poid_par_priv);
+NDIS_STATUS oid_rt_get_key_mismatch_hdl(struct oid_par_priv *poid_par_priv);
+NDIS_STATUS oid_rt_supported_wireless_mode_hdl(struct oid_par_priv *poid_par_priv);
+NDIS_STATUS oid_rt_get_channel_list_hdl(struct oid_par_priv *poid_par_priv);
+NDIS_STATUS oid_rt_get_scan_in_progress_hdl(struct oid_par_priv *poid_par_priv);
+NDIS_STATUS oid_rt_forced_data_rate_hdl(struct oid_par_priv *poid_par_priv);
+NDIS_STATUS oid_rt_wireless_mode_for_scan_list_hdl(struct oid_par_priv *poid_par_priv);
+NDIS_STATUS oid_rt_get_bss_wireless_mode_hdl(struct oid_par_priv *poid_par_priv);
+NDIS_STATUS oid_rt_scan_with_magic_packet_hdl(struct oid_par_priv *poid_par_priv);
+
+/* **************  oid_rtl_seg_01_03 section start ************** */
+NDIS_STATUS oid_rt_ap_get_associated_station_list_hdl(struct oid_par_priv *poid_par_priv);
+NDIS_STATUS oid_rt_ap_switch_into_ap_mode_hdl(struct oid_par_priv *poid_par_priv);
+NDIS_STATUS oid_rt_ap_supported_hdl(struct oid_par_priv *poid_par_priv);
+NDIS_STATUS oid_rt_ap_set_passphrase_hdl(struct oid_par_priv *poid_par_priv);
+
+/* oid_rtl_seg_01_11 */
+NDIS_STATUS oid_rt_pro_rf_write_registry_hdl(struct oid_par_priv *poid_par_priv);
+NDIS_STATUS oid_rt_pro_rf_read_registry_hdl(struct oid_par_priv *poid_par_priv);
+
+/* **************  oid_rtl_seg_03_00 section start **************  */
+NDIS_STATUS oid_rt_get_connect_state_hdl(struct oid_par_priv *poid_par_priv);
+NDIS_STATUS oid_rt_set_default_key_id_hdl(struct oid_par_priv *poid_par_priv);
+
+
+
+
+#endif
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/include/rtw_ioctl_set.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/rtw_ioctl_set.h
--- linux-5.6.3/3rdparty/rtl8821ce/include/rtw_ioctl_set.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/rtw_ioctl_set.h	2020-04-10 16:35:06.851661701 +0300
@@ -0,0 +1,67 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#ifndef __RTW_IOCTL_SET_H_
+#define __RTW_IOCTL_SET_H_
+
+
+typedef u8 NDIS_802_11_PMKID_VALUE[16];
+
+typedef struct _BSSIDInfo {
+	NDIS_802_11_MAC_ADDRESS  BSSID;
+	NDIS_802_11_PMKID_VALUE  PMKID;
+} BSSIDInfo, *PBSSIDInfo;
+
+
+#ifdef PLATFORM_OS_XP
+typedef struct _NDIS_802_11_PMKID {
+	u32	Length;
+	u32	BSSIDInfoCount;
+	BSSIDInfo BSSIDInfo[1];
+} NDIS_802_11_PMKID, *PNDIS_802_11_PMKID;
+#endif
+
+
+#ifdef PLATFORM_WINDOWS
+u8 rtw_set_802_11_reload_defaults(_adapter *padapter, NDIS_802_11_RELOAD_DEFAULTS reloadDefaults);
+u8 rtw_set_802_11_test(_adapter *padapter, NDIS_802_11_TEST *test);
+u8 rtw_set_802_11_pmkid(_adapter *pdapter, NDIS_802_11_PMKID *pmkid);
+
+u8 rtw_pnp_set_power_sleep(_adapter *padapter);
+u8 rtw_pnp_set_power_wakeup(_adapter *padapter);
+
+void rtw_pnp_resume_wk(void *context);
+void rtw_pnp_sleep_wk(void *context);
+
+#endif
+
+u8 rtw_set_802_11_authentication_mode(_adapter *pdapter, NDIS_802_11_AUTHENTICATION_MODE authmode);
+u8 rtw_set_802_11_bssid(_adapter *padapter, u8 *bssid);
+u8 rtw_set_802_11_add_wep(_adapter *padapter, NDIS_802_11_WEP *wep);
+u8 rtw_set_802_11_disassociate(_adapter *padapter);
+u8 rtw_set_802_11_bssid_list_scan(_adapter *padapter, struct sitesurvey_parm *pparm);
+u8 rtw_set_802_11_infrastructure_mode(_adapter *padapter, NDIS_802_11_NETWORK_INFRASTRUCTURE networktype);
+u8 rtw_set_802_11_ssid(_adapter *padapter, NDIS_802_11_SSID *ssid);
+u8 rtw_set_802_11_connect(_adapter *padapter, u8 *bssid, NDIS_802_11_SSID *ssid);
+
+u8 rtw_validate_bssid(u8 *bssid);
+u8 rtw_validate_ssid(NDIS_802_11_SSID *ssid);
+
+u16 rtw_get_cur_max_rate(_adapter *adapter);
+int rtw_set_scan_mode(_adapter *adapter, RT_SCAN_TYPE scan_mode);
+int rtw_set_channel_plan(_adapter *adapter, u8 channel_plan);
+int rtw_set_country(_adapter *adapter, const char *country_code);
+int rtw_set_band(_adapter *adapter, u8 band);
+
+#endif
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/include/rtw_io.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/rtw_io.h
--- linux-5.6.3/3rdparty/rtl8821ce/include/rtw_io.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/rtw_io.h	2020-04-10 16:35:06.851661701 +0300
@@ -0,0 +1,569 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+
+#ifndef _RTW_IO_H_
+#define _RTW_IO_H_
+
+#define NUM_IOREQ		8
+
+#ifdef PLATFORM_WINDOWS
+	#define MAX_PROT_SZ	64
+#endif
+#ifdef PLATFORM_LINUX
+	#define MAX_PROT_SZ	(64-16)
+#endif
+
+#define _IOREADY			0
+#define _IO_WAIT_COMPLETE   1
+#define _IO_WAIT_RSP        2
+
+/* IO COMMAND TYPE */
+#define _IOSZ_MASK_		(0x7F)
+#define _IO_WRITE_		BIT(7)
+#define _IO_FIXED_		BIT(8)
+#define _IO_BURST_		BIT(9)
+#define _IO_BYTE_		BIT(10)
+#define _IO_HW_			BIT(11)
+#define _IO_WORD_		BIT(12)
+#define _IO_SYNC_		BIT(13)
+#define _IO_CMDMASK_	(0x1F80)
+
+
+/*
+	For prompt mode accessing, caller shall free io_req
+	Otherwise, io_handler will free io_req
+*/
+
+
+
+/* IO STATUS TYPE */
+#define _IO_ERR_		BIT(2)
+#define _IO_SUCCESS_	BIT(1)
+#define _IO_DONE_		BIT(0)
+
+
+#define IO_RD32			(_IO_SYNC_ | _IO_WORD_)
+#define IO_RD16			(_IO_SYNC_ | _IO_HW_)
+#define IO_RD8			(_IO_SYNC_ | _IO_BYTE_)
+
+#define IO_RD32_ASYNC	(_IO_WORD_)
+#define IO_RD16_ASYNC	(_IO_HW_)
+#define IO_RD8_ASYNC	(_IO_BYTE_)
+
+#define IO_WR32			(_IO_WRITE_ | _IO_SYNC_ | _IO_WORD_)
+#define IO_WR16			(_IO_WRITE_ | _IO_SYNC_ | _IO_HW_)
+#define IO_WR8			(_IO_WRITE_ | _IO_SYNC_ | _IO_BYTE_)
+
+#define IO_WR32_ASYNC	(_IO_WRITE_ | _IO_WORD_)
+#define IO_WR16_ASYNC	(_IO_WRITE_ | _IO_HW_)
+#define IO_WR8_ASYNC	(_IO_WRITE_ | _IO_BYTE_)
+
+/*
+
+	Only Sync. burst accessing is provided.
+
+*/
+
+#define IO_WR_BURST(x)		(_IO_WRITE_ | _IO_SYNC_ | _IO_BURST_ | ((x) & _IOSZ_MASK_))
+#define IO_RD_BURST(x)		(_IO_SYNC_ | _IO_BURST_ | ((x) & _IOSZ_MASK_))
+
+
+
+/* below is for the intf_option bit defition... */
+
+#define _INTF_ASYNC_	BIT(0)	/* support async io */
+
+struct intf_priv;
+struct intf_hdl;
+struct io_queue;
+
+struct _io_ops {
+	u8(*_read8)(struct intf_hdl *pintfhdl, u32 addr);
+	u16(*_read16)(struct intf_hdl *pintfhdl, u32 addr);
+	u32(*_read32)(struct intf_hdl *pintfhdl, u32 addr);
+
+	int (*_write8)(struct intf_hdl *pintfhdl, u32 addr, u8 val);
+	int (*_write16)(struct intf_hdl *pintfhdl, u32 addr, u16 val);
+	int (*_write32)(struct intf_hdl *pintfhdl, u32 addr, u32 val);
+	int (*_writeN)(struct intf_hdl *pintfhdl, u32 addr, u32 length, u8 *pdata);
+
+	int (*_write8_async)(struct intf_hdl *pintfhdl, u32 addr, u8 val);
+	int (*_write16_async)(struct intf_hdl *pintfhdl, u32 addr, u16 val);
+	int (*_write32_async)(struct intf_hdl *pintfhdl, u32 addr, u32 val);
+
+	void (*_read_mem)(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *pmem);
+	void (*_write_mem)(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *pmem);
+
+	void (*_sync_irp_protocol_rw)(struct io_queue *pio_q);
+
+	u32(*_read_interrupt)(struct intf_hdl *pintfhdl, u32 addr);
+
+	u32(*_read_port)(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *pmem);
+	u32(*_write_port)(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *pmem);
+
+	u32(*_write_scsi)(struct intf_hdl *pintfhdl, u32 cnt, u8 *pmem);
+
+	void (*_read_port_cancel)(struct intf_hdl *pintfhdl);
+	void (*_write_port_cancel)(struct intf_hdl *pintfhdl);
+
+#ifdef CONFIG_SDIO_HCI
+	u8(*_sd_f0_read8)(struct intf_hdl *pintfhdl, u32 addr);
+#ifdef CONFIG_SDIO_INDIRECT_ACCESS
+	u8(*_sd_iread8)(struct intf_hdl *pintfhdl, u32 addr);
+	u16(*_sd_iread16)(struct intf_hdl *pintfhdl, u32 addr);
+	u32(*_sd_iread32)(struct intf_hdl *pintfhdl, u32 addr);
+	int (*_sd_iwrite8)(struct intf_hdl *pintfhdl, u32 addr, u8 val);
+	int (*_sd_iwrite16)(struct intf_hdl *pintfhdl, u32 addr, u16 val);
+	int (*_sd_iwrite32)(struct intf_hdl *pintfhdl, u32 addr, u32 val);
+#endif /* CONFIG_SDIO_INDIRECT_ACCESS */
+#endif
+
+};
+
+struct io_req {
+	_list	list;
+	u32	addr;
+	volatile u32	val;
+	u32	command;
+	u32	status;
+	u8	*pbuf;
+	_sema	sema;
+
+#ifdef PLATFORM_OS_CE
+#ifdef CONFIG_USB_HCI
+	/* URB handler for rtw_write_mem */
+	USB_TRANSFER usb_transfer_write_mem;
+#endif
+#endif
+
+	void (*_async_io_callback)(_adapter *padater, struct io_req *pio_req, u8 *cnxt);
+	u8 *cnxt;
+
+#ifdef PLATFORM_OS_XP
+	PMDL pmdl;
+	PIRP  pirp;
+
+#ifdef CONFIG_SDIO_HCI
+	PSDBUS_REQUEST_PACKET sdrp;
+#endif
+
+#endif
+
+
+};
+
+struct	intf_hdl {
+
+#if 0
+	u32	intf_option;
+	u32	bus_status;
+	u32	do_flush;
+	u8	*adapter;
+	u8	*intf_dev;
+	struct intf_priv	*pintfpriv;
+	u8	cnt;
+	void (*intf_hdl_init)(u8 *priv);
+	void (*intf_hdl_unload)(u8 *priv);
+	void (*intf_hdl_open)(u8 *priv);
+	void (*intf_hdl_close)(u8 *priv);
+	struct	_io_ops	io_ops;
+	/* u8 intf_status;//moved to struct intf_priv */
+	u16 len;
+	u16 done_len;
+#endif
+	_adapter *padapter;
+	struct dvobj_priv *pintf_dev;/*	pointer to &(padapter->dvobjpriv); */
+
+	struct _io_ops	io_ops;
+
+};
+
+struct reg_protocol_rd {
+
+#ifdef CONFIG_LITTLE_ENDIAN
+
+	/* DW1 */
+	u32		NumOfTrans:4;
+	u32		Reserved1:4;
+	u32		Reserved2:24;
+	/* DW2 */
+	u32		ByteCount:7;
+	u32		WriteEnable:1;		/* 0:read, 1:write */
+	u32		FixOrContinuous:1;	/* 0:continuous, 1: Fix */
+	u32		BurstMode:1;
+	u32		Byte1Access:1;
+	u32		Byte2Access:1;
+	u32		Byte4Access:1;
+	u32		Reserved3:3;
+	u32		Reserved4:16;
+	/* DW3 */
+	u32		BusAddress;
+	/* DW4 */
+	/* u32		Value; */
+#else
+
+
+	/* DW1 */
+	u32 Reserved1:4;
+	u32 NumOfTrans:4;
+
+	u32 Reserved2:24;
+
+	/* DW2 */
+	u32 WriteEnable:1;
+	u32 ByteCount:7;
+
+
+	u32 Reserved3:3;
+	u32 Byte4Access:1;
+
+	u32 Byte2Access:1;
+	u32 Byte1Access:1;
+	u32 BurstMode:1;
+	u32 FixOrContinuous:1;
+
+	u32 Reserved4:16;
+
+	/* DW3 */
+	u32		BusAddress;
+
+	/* DW4 */
+	/* u32		Value; */
+
+#endif
+
+};
+
+
+struct reg_protocol_wt {
+
+
+#ifdef CONFIG_LITTLE_ENDIAN
+
+	/* DW1 */
+	u32		NumOfTrans:4;
+	u32		Reserved1:4;
+	u32		Reserved2:24;
+	/* DW2 */
+	u32		ByteCount:7;
+	u32		WriteEnable:1;		/* 0:read, 1:write */
+	u32		FixOrContinuous:1;	/* 0:continuous, 1: Fix */
+	u32		BurstMode:1;
+	u32		Byte1Access:1;
+	u32		Byte2Access:1;
+	u32		Byte4Access:1;
+	u32		Reserved3:3;
+	u32		Reserved4:16;
+	/* DW3 */
+	u32		BusAddress;
+	/* DW4 */
+	u32		Value;
+
+#else
+	/* DW1 */
+	u32 Reserved1:4;
+	u32 NumOfTrans:4;
+
+	u32 Reserved2:24;
+
+	/* DW2 */
+	u32 WriteEnable:1;
+	u32 ByteCount:7;
+
+	u32 Reserved3:3;
+	u32 Byte4Access:1;
+
+	u32 Byte2Access:1;
+	u32 Byte1Access:1;
+	u32 BurstMode:1;
+	u32 FixOrContinuous:1;
+
+	u32 Reserved4:16;
+
+	/* DW3 */
+	u32		BusAddress;
+
+	/* DW4 */
+	u32		Value;
+
+#endif
+
+};
+#ifdef CONFIG_PCI_HCI
+#define MAX_CONTINUAL_IO_ERR 4
+#endif
+
+#ifdef CONFIG_USB_HCI
+#define MAX_CONTINUAL_IO_ERR 4
+#endif
+
+#ifdef CONFIG_SDIO_HCI
+#define SD_IO_TRY_CNT (8)
+#define MAX_CONTINUAL_IO_ERR SD_IO_TRY_CNT
+#endif
+
+#ifdef CONFIG_GSPI_HCI
+#define SD_IO_TRY_CNT (8)
+#define MAX_CONTINUAL_IO_ERR SD_IO_TRY_CNT
+#endif
+
+
+int rtw_inc_and_chk_continual_io_error(struct dvobj_priv *dvobj);
+void rtw_reset_continual_io_error(struct dvobj_priv *dvobj);
+
+/*
+Below is the data structure used by _io_handler
+
+*/
+
+struct io_queue {
+	_lock	lock;
+	_list	free_ioreqs;
+	_list		pending;		/* The io_req list that will be served in the single protocol read/write.	 */
+	_list		processing;
+	u8	*free_ioreqs_buf; /* 4-byte aligned */
+	u8	*pallocated_free_ioreqs_buf;
+	struct	intf_hdl	intf;
+};
+
+struct io_priv {
+
+	_adapter *padapter;
+
+	struct intf_hdl intf;
+
+};
+
+extern uint ioreq_flush(_adapter *adapter, struct io_queue *ioqueue);
+extern void sync_ioreq_enqueue(struct io_req *preq, struct io_queue *ioqueue);
+extern uint sync_ioreq_flush(_adapter *adapter, struct io_queue *ioqueue);
+
+
+extern uint free_ioreq(struct io_req *preq, struct io_queue *pio_queue);
+extern struct io_req *alloc_ioreq(struct io_queue *pio_q);
+
+extern uint register_intf_hdl(u8 *dev, struct intf_hdl *pintfhdl);
+extern void unregister_intf_hdl(struct intf_hdl *pintfhdl);
+
+extern void _rtw_attrib_read(_adapter *adapter, u32 addr, u32 cnt, u8 *pmem);
+extern void _rtw_attrib_write(_adapter *adapter, u32 addr, u32 cnt, u8 *pmem);
+
+extern u8 _rtw_read8(_adapter *adapter, u32 addr);
+extern u16 _rtw_read16(_adapter *adapter, u32 addr);
+extern u32 _rtw_read32(_adapter *adapter, u32 addr);
+extern void _rtw_read_mem(_adapter *adapter, u32 addr, u32 cnt, u8 *pmem);
+extern void _rtw_read_port(_adapter *adapter, u32 addr, u32 cnt, u8 *pmem);
+extern void _rtw_read_port_cancel(_adapter *adapter);
+
+
+extern int _rtw_write8(_adapter *adapter, u32 addr, u8 val);
+extern int _rtw_write16(_adapter *adapter, u32 addr, u16 val);
+extern int _rtw_write32(_adapter *adapter, u32 addr, u32 val);
+extern int _rtw_writeN(_adapter *adapter, u32 addr, u32 length, u8 *pdata);
+
+#ifdef CONFIG_SDIO_HCI
+u8 _rtw_sd_f0_read8(_adapter *adapter, u32 addr);
+#ifdef CONFIG_SDIO_INDIRECT_ACCESS
+u8 _rtw_sd_iread8(_adapter *adapter, u32 addr);
+u16 _rtw_sd_iread16(_adapter *adapter, u32 addr);
+u32 _rtw_sd_iread32(_adapter *adapter, u32 addr);
+int _rtw_sd_iwrite8(_adapter *adapter, u32 addr, u8 val);
+int _rtw_sd_iwrite16(_adapter *adapter, u32 addr, u16 val);
+int _rtw_sd_iwrite32(_adapter *adapter, u32 addr, u32 val);
+#endif /* CONFIG_SDIO_INDIRECT_ACCESS */
+#endif /* CONFIG_SDIO_HCI */
+
+extern int _rtw_write8_async(_adapter *adapter, u32 addr, u8 val);
+extern int _rtw_write16_async(_adapter *adapter, u32 addr, u16 val);
+extern int _rtw_write32_async(_adapter *adapter, u32 addr, u32 val);
+
+extern void _rtw_write_mem(_adapter *adapter, u32 addr, u32 cnt, u8 *pmem);
+extern u32 _rtw_write_port(_adapter *adapter, u32 addr, u32 cnt, u8 *pmem);
+u32 _rtw_write_port_and_wait(_adapter *adapter, u32 addr, u32 cnt, u8 *pmem, int timeout_ms);
+extern void _rtw_write_port_cancel(_adapter *adapter);
+
+#ifdef DBG_IO
+struct rtw_io_sniff_ent;
+const char *rtw_io_sniff_ent_get_tag(const struct rtw_io_sniff_ent *ent);
+const struct rtw_io_sniff_ent *match_read_sniff(_adapter *adapter, u32 addr, u16 len, u32 val);
+const struct rtw_io_sniff_ent *match_write_sniff(_adapter *adapter, u32 addr, u16 len, u32 val);
+bool match_rf_read_sniff_ranges(_adapter *adapter, u8 path, u32 addr, u32 mask);
+bool match_rf_write_sniff_ranges(_adapter *adapter, u8 path, u32 addr, u32 mask);
+
+extern u8 dbg_rtw_read8(_adapter *adapter, u32 addr, const char *caller, const int line);
+extern u16 dbg_rtw_read16(_adapter *adapter, u32 addr, const char *caller, const int line);
+extern u32 dbg_rtw_read32(_adapter *adapter, u32 addr, const char *caller, const int line);
+
+extern int dbg_rtw_write8(_adapter *adapter, u32 addr, u8 val, const char *caller, const int line);
+extern int dbg_rtw_write16(_adapter *adapter, u32 addr, u16 val, const char *caller, const int line);
+extern int dbg_rtw_write32(_adapter *adapter, u32 addr, u32 val, const char *caller, const int line);
+extern int dbg_rtw_writeN(_adapter *adapter, u32 addr , u32 length , u8 *data, const char *caller, const int line);
+
+#ifdef CONFIG_SDIO_HCI
+u8 dbg_rtw_sd_f0_read8(_adapter *adapter, u32 addr, const char *caller, const int line);
+#ifdef CONFIG_SDIO_INDIRECT_ACCESS
+u8 dbg_rtw_sd_iread8(_adapter *adapter, u32 addr, const char *caller, const int line);
+u16 dbg_rtw_sd_iread16(_adapter *adapter, u32 addr, const char *caller, const int line);
+u32 dbg_rtw_sd_iread32(_adapter *adapter, u32 addr, const char *caller, const int line);
+int dbg_rtw_sd_iwrite8(_adapter *adapter, u32 addr, u8 val, const char *caller, const int line);
+int dbg_rtw_sd_iwrite16(_adapter *adapter, u32 addr, u16 val, const char *caller, const int line);
+int dbg_rtw_sd_iwrite32(_adapter *adapter, u32 addr, u32 val, const char *caller, const int line);
+#endif /* CONFIG_SDIO_INDIRECT_ACCESS */
+#endif /* CONFIG_SDIO_HCI */
+
+#define rtw_read8(adapter, addr) dbg_rtw_read8((adapter), (addr), __FUNCTION__, __LINE__)
+#define rtw_read16(adapter, addr) dbg_rtw_read16((adapter), (addr), __FUNCTION__, __LINE__)
+#define rtw_read32(adapter, addr) dbg_rtw_read32((adapter), (addr), __FUNCTION__, __LINE__)
+#define rtw_read_mem(adapter, addr, cnt, mem) _rtw_read_mem((adapter), (addr), (cnt), (mem))
+#define rtw_read_port(adapter, addr, cnt, mem) _rtw_read_port((adapter), (addr), (cnt), (mem))
+#define rtw_read_port_cancel(adapter) _rtw_read_port_cancel((adapter))
+
+#define  rtw_write8(adapter, addr, val) dbg_rtw_write8((adapter), (addr), (val), __FUNCTION__, __LINE__)
+#define  rtw_write16(adapter, addr, val) dbg_rtw_write16((adapter), (addr), (val), __FUNCTION__, __LINE__)
+#define  rtw_write32(adapter, addr, val) dbg_rtw_write32((adapter), (addr), (val), __FUNCTION__, __LINE__)
+#define  rtw_writeN(adapter, addr, length, data) dbg_rtw_writeN((adapter), (addr), (length), (data), __FUNCTION__, __LINE__)
+
+#define rtw_write8_async(adapter, addr, val) _rtw_write8_async((adapter), (addr), (val))
+#define rtw_write16_async(adapter, addr, val) _rtw_write16_async((adapter), (addr), (val))
+#define rtw_write32_async(adapter, addr, val) _rtw_write32_async((adapter), (addr), (val))
+
+#define rtw_write_mem(adapter, addr, cnt, mem) _rtw_write_mem((adapter), addr, cnt, mem)
+#define rtw_write_port(adapter, addr, cnt, mem) _rtw_write_port(adapter, addr, cnt, mem)
+#define rtw_write_port_and_wait(adapter, addr, cnt, mem, timeout_ms) _rtw_write_port_and_wait((adapter), (addr), (cnt), (mem), (timeout_ms))
+#define rtw_write_port_cancel(adapter) _rtw_write_port_cancel(adapter)
+
+#ifdef CONFIG_SDIO_HCI
+#define rtw_sd_f0_read8(adapter, addr) dbg_rtw_sd_f0_read8((adapter), (addr), __func__, __LINE__)
+#ifdef CONFIG_SDIO_INDIRECT_ACCESS
+#define rtw_sd_iread8(adapter, addr) dbg_rtw_sd_iread8((adapter), (addr), __func__, __LINE__)
+#define rtw_sd_iread16(adapter, addr) dbg_rtw_sd_iread16((adapter), (addr), __func__, __LINE__)
+#define rtw_sd_iread32(adapter, addr) dbg_rtw_sd_iread32((adapter), (addr), __func__, __LINE__)
+#define rtw_sd_iwrite8(adapter, addr, val) dbg_rtw_sd_iwrite8((adapter), (addr), (val), __func__, __LINE__)
+#define rtw_sd_iwrite16(adapter, addr, val) dbg_rtw_sd_iwrite16((adapter), (addr), (val), __func__, __LINE__)
+#define rtw_sd_iwrite32(adapter, addr, val) dbg_rtw_sd_iwrite32((adapter), (addr), (val), __func__, __LINE__)
+#endif /* CONFIG_SDIO_INDIRECT_ACCESS */
+#endif /* CONFIG_SDIO_HCI */
+
+#else /* DBG_IO */
+#define rtw_read8(adapter, addr) _rtw_read8((adapter), (addr))
+#define rtw_read16(adapter, addr) _rtw_read16((adapter), (addr))
+#define rtw_read32(adapter, addr) _rtw_read32((adapter), (addr))
+#define rtw_read_mem(adapter, addr, cnt, mem) _rtw_read_mem((adapter), (addr), (cnt), (mem))
+#define rtw_read_port(adapter, addr, cnt, mem) _rtw_read_port((adapter), (addr), (cnt), (mem))
+#define rtw_read_port_cancel(adapter) _rtw_read_port_cancel((adapter))
+
+#define  rtw_write8(adapter, addr, val) _rtw_write8((adapter), (addr), (val))
+#define  rtw_write16(adapter, addr, val) _rtw_write16((adapter), (addr), (val))
+#define  rtw_write32(adapter, addr, val) _rtw_write32((adapter), (addr), (val))
+#define  rtw_writeN(adapter, addr, length, data) _rtw_writeN((adapter), (addr), (length), (data))
+
+#define rtw_write8_async(adapter, addr, val) _rtw_write8_async((adapter), (addr), (val))
+#define rtw_write16_async(adapter, addr, val) _rtw_write16_async((adapter), (addr), (val))
+#define rtw_write32_async(adapter, addr, val) _rtw_write32_async((adapter), (addr), (val))
+
+#define rtw_write_mem(adapter, addr, cnt, mem) _rtw_write_mem((adapter), (addr), (cnt), (mem))
+#define rtw_write_port(adapter, addr, cnt, mem) _rtw_write_port((adapter), (addr), (cnt), (mem))
+#define rtw_write_port_and_wait(adapter, addr, cnt, mem, timeout_ms) _rtw_write_port_and_wait((adapter), (addr), (cnt), (mem), (timeout_ms))
+#define rtw_write_port_cancel(adapter) _rtw_write_port_cancel((adapter))
+
+#ifdef CONFIG_SDIO_HCI
+#define rtw_sd_f0_read8(adapter, addr) _rtw_sd_f0_read8((adapter), (addr))
+#ifdef CONFIG_SDIO_INDIRECT_ACCESS
+#define rtw_sd_iread8(adapter, addr) _rtw_sd_iread8((adapter), (addr))
+#define rtw_sd_iread16(adapter, addr) _rtw_sd_iread16((adapter), (addr))
+#define rtw_sd_iread32(adapter, addr) _rtw_sd_iread32((adapter), (addr))
+#define rtw_sd_iwrite8(adapter, addr, val) _rtw_sd_iwrite8((adapter), (addr), (val))
+#define rtw_sd_iwrite16(adapter, addr, val) _rtw_sd_iwrite16((adapter), (addr), (val))
+#define rtw_sd_iwrite32(adapter, addr, val) _rtw_sd_iwrite32((adapter), (addr), (val))
+#endif /* CONFIG_SDIO_INDIRECT_ACCESS */
+#endif /* CONFIG_SDIO_HCI */
+
+#endif /* DBG_IO */
+
+extern void rtw_write_scsi(_adapter *adapter, u32 cnt, u8 *pmem);
+
+/* ioreq */
+extern void ioreq_read8(_adapter *adapter, u32 addr, u8 *pval);
+extern void ioreq_read16(_adapter *adapter, u32 addr, u16 *pval);
+extern void ioreq_read32(_adapter *adapter, u32 addr, u32 *pval);
+extern void ioreq_write8(_adapter *adapter, u32 addr, u8 val);
+extern void ioreq_write16(_adapter *adapter, u32 addr, u16 val);
+extern void ioreq_write32(_adapter *adapter, u32 addr, u32 val);
+
+
+extern uint async_read8(_adapter *adapter, u32 addr, u8 *pbuff,
+	void (*_async_io_callback)(_adapter *padater, struct io_req *pio_req, u8 *cnxt), u8 *cnxt);
+extern uint async_read16(_adapter *adapter, u32 addr,  u8 *pbuff,
+	void (*_async_io_callback)(_adapter *padater, struct io_req *pio_req, u8 *cnxt), u8 *cnxt);
+extern uint async_read32(_adapter *adapter, u32 addr,  u8 *pbuff,
+	void (*_async_io_callback)(_adapter *padater, struct io_req *pio_req, u8 *cnxt), u8 *cnxt);
+
+extern void async_read_mem(_adapter *adapter, u32 addr, u32 cnt, u8 *pmem);
+extern void async_read_port(_adapter *adapter, u32 addr, u32 cnt, u8 *pmem);
+
+extern void async_write8(_adapter *adapter, u32 addr, u8 val,
+	void (*_async_io_callback)(_adapter *padater, struct io_req *pio_req, u8 *cnxt), u8 *cnxt);
+extern void async_write16(_adapter *adapter, u32 addr, u16 val,
+	void (*_async_io_callback)(_adapter *padater, struct io_req *pio_req, u8 *cnxt), u8 *cnxt);
+extern void async_write32(_adapter *adapter, u32 addr, u32 val,
+	void (*_async_io_callback)(_adapter *padater, struct io_req *pio_req, u8 *cnxt), u8 *cnxt);
+
+extern void async_write_mem(_adapter *adapter, u32 addr, u32 cnt, u8 *pmem);
+extern void async_write_port(_adapter *adapter, u32 addr, u32 cnt, u8 *pmem);
+
+
+int rtw_init_io_priv(_adapter *padapter, void (*set_intf_ops)(_adapter *padapter, struct _io_ops *pops));
+
+
+extern uint alloc_io_queue(_adapter *adapter);
+extern void free_io_queue(_adapter *adapter);
+extern void async_bus_io(struct io_queue *pio_q);
+extern void bus_sync_io(struct io_queue *pio_q);
+extern u32 _ioreq2rwmem(struct io_queue *pio_q);
+extern void dev_power_down(_adapter *Adapter, u8 bpwrup);
+
+/*
+#define RTL_R8(reg)		rtw_read8(padapter, reg)
+#define RTL_R16(reg)            rtw_read16(padapter, reg)
+#define RTL_R32(reg)            rtw_read32(padapter, reg)
+#define RTL_W8(reg, val8)       rtw_write8(padapter, reg, val8)
+#define RTL_W16(reg, val16)     rtw_write16(padapter, reg, val16)
+#define RTL_W32(reg, val32)     rtw_write32(padapter, reg, val32)
+*/
+
+/*
+#define RTL_W8_ASYNC(reg, val8) rtw_write32_async(padapter, reg, val8)
+#define RTL_W16_ASYNC(reg, val16) rtw_write32_async(padapter, reg, val16)
+#define RTL_W32_ASYNC(reg, val32) rtw_write32_async(padapter, reg, val32)
+
+#define RTL_WRITE_BB(reg, val32)	phy_SetUsbBBReg(padapter, reg, val32)
+#define RTL_READ_BB(reg)	phy_QueryUsbBBReg(padapter, reg)
+*/
+
+#define PlatformEFIOWrite1Byte(_a, _b, _c)		\
+	rtw_write8(_a, _b, _c)
+#define PlatformEFIOWrite2Byte(_a, _b, _c)		\
+	rtw_write16(_a, _b, _c)
+#define PlatformEFIOWrite4Byte(_a, _b, _c)		\
+	rtw_write32(_a, _b, _c)
+
+#define PlatformEFIORead1Byte(_a, _b)		\
+	rtw_read8(_a, _b)
+#define PlatformEFIORead2Byte(_a, _b)		\
+	rtw_read16(_a, _b)
+#define PlatformEFIORead4Byte(_a, _b)		\
+	rtw_read32(_a, _b)
+
+#endif /* _RTL8711_IO_H_ */
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/include/rtw_iol.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/rtw_iol.h
--- linux-5.6.3/3rdparty/rtl8821ce/include/rtw_iol.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/rtw_iol.h	2020-04-10 16:35:06.851661701 +0300
@@ -0,0 +1,131 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#ifndef __RTW_IOL_H_
+#define __RTW_IOL_H_
+
+
+struct xmit_frame	*rtw_IOL_accquire_xmit_frame(ADAPTER *adapter);
+int rtw_IOL_append_cmds(struct xmit_frame *xmit_frame, u8 *IOL_cmds, u32 cmd_len);
+int rtw_IOL_append_LLT_cmd(struct xmit_frame *xmit_frame, u8 page_boundary);
+int rtw_IOL_exec_cmds_sync(ADAPTER *adapter, struct xmit_frame *xmit_frame, u32 max_wating_ms, u32 bndy_cnt);
+bool rtw_IOL_applied(ADAPTER *adapter);
+int rtw_IOL_append_DELAY_US_cmd(struct xmit_frame *xmit_frame, u16 us);
+int rtw_IOL_append_DELAY_MS_cmd(struct xmit_frame *xmit_frame, u16 ms);
+int rtw_IOL_append_END_cmd(struct xmit_frame *xmit_frame);
+
+
+#ifdef CONFIG_IOL_NEW_GENERATION
+#define IOREG_CMD_END_LEN	4
+
+struct ioreg_cfg {
+	u8	length;
+	u8	cmd_id;
+	u16	address;
+	u32	data;
+	u32  mask;
+};
+enum ioreg_cmd {
+	IOREG_CMD_LLT			= 0x01,
+	IOREG_CMD_REFUSE		= 0x02,
+	IOREG_CMD_EFUSE_PATH = 0x03,
+	IOREG_CMD_WB_REG		= 0x04,
+	IOREG_CMD_WW_REG	= 0x05,
+	IOREG_CMD_WD_REG	= 0x06,
+	IOREG_CMD_W_RF		= 0x07,
+	IOREG_CMD_DELAY_US	= 0x10,
+	IOREG_CMD_DELAY_MS	= 0x11,
+	IOREG_CMD_END		= 0xFF,
+};
+void read_efuse_from_txpktbuf(ADAPTER *adapter, int bcnhead, u8 *content, u16 *size);
+
+int _rtw_IOL_append_WB_cmd(struct xmit_frame *xmit_frame, u16 addr, u8 value, u8 mask);
+int _rtw_IOL_append_WW_cmd(struct xmit_frame *xmit_frame, u16 addr, u16 value, u16 mask);
+int _rtw_IOL_append_WD_cmd(struct xmit_frame *xmit_frame, u16 addr, u32 value, u32 mask);
+int _rtw_IOL_append_WRF_cmd(struct xmit_frame *xmit_frame, u8 rf_path, u16 addr, u32 value, u32 mask);
+#define rtw_IOL_append_WB_cmd(xmit_frame, addr, value, mask) _rtw_IOL_append_WB_cmd((xmit_frame), (addr), (value), (mask))
+#define rtw_IOL_append_WW_cmd(xmit_frame, addr, value, mask) _rtw_IOL_append_WW_cmd((xmit_frame), (addr), (value), (mask))
+#define rtw_IOL_append_WD_cmd(xmit_frame, addr, value, mask) _rtw_IOL_append_WD_cmd((xmit_frame), (addr), (value), (mask))
+#define rtw_IOL_append_WRF_cmd(xmit_frame, rf_path, addr, value, mask) _rtw_IOL_append_WRF_cmd((xmit_frame), (rf_path), (addr), (value), (mask))
+
+u8 rtw_IOL_cmd_boundary_handle(struct xmit_frame *pxmit_frame);
+void  rtw_IOL_cmd_buf_dump(ADAPTER *Adapter, int buf_len, u8 *pbuf);
+
+#ifdef CONFIG_IOL_IOREG_CFG_DBG
+struct cmd_cmp {
+	u16 addr;
+	u32 value;
+};
+#endif
+
+#else /* CONFIG_IOL_NEW_GENERATION */
+
+typedef struct _io_offload_cmd {
+	u8 rsvd0;
+	u8 cmd;
+	u16 address;
+	u32 value;
+} IO_OFFLOAD_CMD, IOL_CMD;
+
+#define IOL_CMD_LLT			0x00
+/* #define IOL_CMD_R_EFUSE	0x01 */
+#define IOL_CMD_WB_REG		0x02
+#define IOL_CMD_WW_REG	0x03
+#define IOL_CMD_WD_REG		0x04
+/* #define IOL_CMD_W_RF		0x05 */
+#define IOL_CMD_DELAY_US	0x80
+#define IOL_CMD_DELAY_MS	0x81
+/* #define IOL_CMD_DELAY_S	0x82 */
+#define IOL_CMD_END			0x83
+
+/*****************************************************
+CMD					Address			Value
+(B1)					(B2/B3:H/L addr)	(B4:B7 : MSB:LSB)
+******************************************************
+IOL_CMD_LLT			-				B7: PGBNDY
+IOL_CMD_R_EFUSE	-				-
+IOL_CMD_WB_REG		0x0~0xFFFF		B7
+IOL_CMD_WW_REG	0x0~0xFFFF		B6~B7
+IOL_CMD_WD_REG	0x0~0xFFFF		B4~B7
+IOL_CMD_W_RF		RF Reg			B5~B7
+IOL_CMD_DELAY_US	-				B6~B7
+IOL_CMD_DELAY_MS	-				B6~B7
+IOL_CMD_DELAY_S	-				B6~B7
+IOL_CMD_END		-				-
+******************************************************/
+int _rtw_IOL_append_WB_cmd(struct xmit_frame *xmit_frame, u16 addr, u8 value);
+int _rtw_IOL_append_WW_cmd(struct xmit_frame *xmit_frame, u16 addr, u16 value);
+int _rtw_IOL_append_WD_cmd(struct xmit_frame *xmit_frame, u16 addr, u32 value);
+
+
+int rtw_IOL_exec_cmd_array_sync(PADAPTER adapter, u8 *IOL_cmds, u32 cmd_num, u32 max_wating_ms);
+int rtw_IOL_exec_empty_cmds_sync(ADAPTER *adapter, u32 max_wating_ms);
+
+#ifdef DBG_IO
+int dbg_rtw_IOL_append_WB_cmd(struct xmit_frame *xmit_frame, u16 addr, u8 value, const char *caller, const int line);
+int dbg_rtw_IOL_append_WW_cmd(struct xmit_frame *xmit_frame, u16 addr, u16 value, const char *caller, const int line);
+int dbg_rtw_IOL_append_WD_cmd(struct xmit_frame *xmit_frame, u16 addr, u32 value, const char *caller, const int line);
+#define rtw_IOL_append_WB_cmd(xmit_frame, addr, value) dbg_rtw_IOL_append_WB_cmd((xmit_frame), (addr), (value), __FUNCTION__, __LINE__)
+#define rtw_IOL_append_WW_cmd(xmit_frame, addr, value) dbg_rtw_IOL_append_WW_cmd((xmit_frame), (addr), (value), __FUNCTION__, __LINE__)
+#define rtw_IOL_append_WD_cmd(xmit_frame, addr, value) dbg_rtw_IOL_append_WD_cmd((xmit_frame), (addr), (value), __FUNCTION__, __LINE__)
+#else
+#define rtw_IOL_append_WB_cmd(xmit_frame, addr, value) _rtw_IOL_append_WB_cmd((xmit_frame), (addr), (value))
+#define rtw_IOL_append_WW_cmd(xmit_frame, addr, value) _rtw_IOL_append_WW_cmd((xmit_frame), (addr), (value))
+#define rtw_IOL_append_WD_cmd(xmit_frame, addr, value) _rtw_IOL_append_WD_cmd((xmit_frame), (addr), (value))
+#endif /* DBG_IO */
+#endif /* CONFIG_IOL_NEW_GENERATION */
+
+
+
+#endif /* __RTW_IOL_H_ */
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/include/rtw_mcc.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/rtw_mcc.h
--- linux-5.6.3/3rdparty/rtl8821ce/include/rtw_mcc.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/rtw_mcc.h	2020-04-10 16:35:06.851661701 +0300
@@ -0,0 +1,271 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2015 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#ifdef CONFIG_MCC_MODE
+
+#ifndef _RTW_MCC_H_
+#define _RTW_MCC_H_
+
+#include <drv_types.h> /* PADAPTER */
+
+#define MCC_STATUS_PROCESS_MCC_START_SETTING BIT0
+#define MCC_STATUS_PROCESS_MCC_STOP_SETTING BIT1
+#define MCC_STATUS_NEED_MCC BIT2
+#define MCC_STATUS_DOING_MCC BIT3
+
+
+#define MCC_SWCH_FW_EARLY_TIME 10 /* ms */
+#define MCC_EXPIRE_TIME 50 /* ms */
+#define MCC_TOLERANCE_TIME 2 /* 2*2 = 4s */
+#define MCC_UPDATE_PARAMETER_THRESHOLD 5 /* ms */
+
+#define MCC_ROLE_STA_GC_MGMT_QUEUE_MACID 0
+#define MCC_ROLE_SOFTAP_GO_MGMT_QUEUE_MACID 1
+
+/* Lower for stop, Higher for start */
+#define MCC_SETCMD_STATUS_STOP_DISCONNECT 0x0
+#define MCC_SETCMD_STATUS_STOP_SCAN_START 0x1
+#define MCC_SETCMD_STATUS_START_CONNECT 0x80
+#define MCC_SETCMD_STATUS_START_SCAN_DONE 0x81
+
+/*
+* depenad platform or customer requirement(TP unit:Mbps),
+* must be provided by PM or sales or product document
+* too large value means not to limit tx bytes (current for ap mode)
+* NOTE: following values ref from test results
+*/
+#define MCC_AP_BW20_TARGET_TX_TP (300)
+#define MCC_AP_BW40_TARGET_TX_TP (300)
+#define MCC_AP_BW80_TARGET_TX_TP (300)
+#define MCC_STA_BW20_TARGET_TX_TP (35)
+#define MCC_STA_BW40_TARGET_TX_TP (70)
+#define MCC_STA_BW80_TARGET_TX_TP (140)
+#define MCC_SINGLE_TX_CRITERIA 5 /* Mbps */
+
+#define MAX_MCC_NUM 2
+
+#define MCC_STOP(adapter) (adapter->mcc_adapterpriv.mcc_tx_stop)
+#define MCC_EN(adapter) (adapter_to_dvobj(adapter)->mcc_objpriv.en_mcc)
+#define SET_MCC_EN_FLAG(adapter, flag)\
+	do { \
+		adapter_to_dvobj(adapter)->mcc_objpriv.en_mcc = (flag); \
+	} while (0)
+#define SET_MCC_DURATION(adapter, val)\
+	do { \
+		adapter_to_dvobj(adapter)->mcc_objpriv.duration = (val); \
+	} while (0)
+#define SET_MCC_RUNTIME_DURATION(adapter, flag)\
+	do { \
+		adapter_to_dvobj(adapter)->mcc_objpriv.enable_runtime_duration = (flag); \
+	} while (0)
+/* Represent Channel Tx Null setting */
+enum mcc_channel_tx_null {
+	MCC_ENABLE_TX_NULL = 0,
+	MCC_DISABLE_TX_NULL = 1,
+};
+
+/* Represent C2H Report setting */
+enum mcc_c2h_report {
+	MCC_C2H_REPORT_DISABLE = 0,
+	MCC_C2H_REPORT_FAIL_STATUS = 1,
+	MCC_C2H_REPORT_ALL_STATUS = 2,
+};
+
+/* Represent Channel Scan */
+enum mcc_channel_scan {
+	MCC_CHIDX = 0,
+	MCC_SCANCH_RSVD_LOC = 1,
+};
+
+/* Represent FW status report of channel switch */
+enum mcc_status_rpt {
+	MCC_RPT_SUCCESS = 0,
+	MCC_RPT_TXNULL_FAIL = 1,
+	MCC_RPT_STOPMCC = 2,
+	MCC_RPT_READY = 3,
+	MCC_RPT_SWICH_CHANNEL_NOTIFY = 7,
+	MCC_RPT_UPDATE_NOA_START_TIME = 8,
+	MCC_RPT_TSF = 9,
+	MCC_RPT_MAX,
+};
+
+enum mcc_role {
+	MCC_ROLE_STA = 0,
+	MCC_ROLE_AP = 1,
+	MCC_ROLE_GC = 2,
+	MCC_ROLE_GO = 3,
+	MCC_ROLE_MAX,
+};
+
+struct mcc_iqk_backup {
+	u16 TX_X;
+	u16 TX_Y;
+	u16 RX_X;
+	u16 RX_Y;
+};
+
+enum MCC_DURATION_SETTING {
+	MCC_DURATION_MAPPING = 0,
+	MCC_DURATION_DIRECET = 1,
+};
+
+enum MCC_SCHED_MODE {
+	MCC_FAIR_SCHEDULE = 0,
+	MCC_FAVOE_STA = 1,
+	MCC_FAVOE_P2P = 2,
+};
+
+/*  mcc data for adapter */
+struct mcc_adapter_priv {
+	u8 order;		/* FW document, softap/AP must be 0 */
+	enum mcc_role role;			/* MCC role(AP,STA,GO,GC) */
+	u8 mcc_duration; /* channel stay period, UNIT:1TU */
+
+	/* flow control */
+	u8 mcc_tx_stop;				/* check if tp stop or not */
+	u8 mcc_tp_limit;				/* check if tp limit or not */
+	u32 mcc_target_tx_bytes_to_port;		/* customer require  */
+	u32 mcc_tx_bytes_to_port;	/* already tx to tx fifo (write port) */
+
+	/* data from kernel to check if enqueue data or netif stop queue */
+	u32 mcc_tp;
+	u64 mcc_tx_bytes_from_kernel;
+	u64 mcc_last_tx_bytes_from_kernel;
+
+	/* Backup IQK value for MCC */
+	struct mcc_iqk_backup mcc_iqk_arr[MAX_RF_PATH];
+
+	/* mgmt queue macid to avoid RA issue */
+	u8 mgmt_queue_macid;
+
+	/* set macid bitmap to let fw know which macid should be tx pause */
+	/* all interface share total 16 macid */
+	u16 mcc_macid_bitmap;
+
+	/* use for NoA start time (unit: mircoseconds) */
+	u32 noa_start_time;
+
+	u8 p2p_go_noa_ie[MAX_P2P_IE_LEN];
+	u32 p2p_go_noa_ie_len;
+	u64 tsf;
+#ifdef CONFIG_TDLS
+	u8 backup_tdls_en;
+#endif /* CONFIG_TDLS */
+
+	u8 null_early;
+	u8 null_rty_num;
+};
+
+struct mcc_obj_priv {
+	u8 en_mcc; /* enable MCC or not */
+	u8 duration; /* store duration(%) from registry, for primary adapter */
+	u8 interval;
+	u8 start_time;
+	u8 mcc_c2h_status;
+	u8 cur_mcc_success_cnt; /* used for check mcc switch channel success */
+	u8 prev_mcc_success_cnt; /* used for check mcc switch channel success */
+	u8 mcc_tolerance_time; /* used for detect mcc switch channel success */
+	u8 mcc_loc_rsvd_paga[MAX_MCC_NUM];  /* mcc rsvd page */
+	u8 mcc_status; /* mcc status stop or start .... */
+	u8 policy_index;
+	u8 mcc_stop_threshold;
+	u8 current_order;
+	u8 last_tsfdiff;
+	systime mcc_launch_time; /* mcc launch time, used for starting detect mcc switch channel success */
+	_mutex mcc_mutex;
+	_lock mcc_lock;
+	PADAPTER iface[MAX_MCC_NUM]; /* by order, use for mcc parameter cmd */
+	struct submit_ctx mcc_sctx;
+	struct submit_ctx mcc_tsf_req_sctx;
+	_mutex mcc_tsf_req_mutex;
+	u8 mcc_tsf_req_sctx_order; /* record current order for mcc_tsf_req_sctx */
+#ifdef CONFIG_MCC_MODE_V2
+	u8 mcc_iqk_value_rsvd_page[3];
+#endif /* CONFIG_MCC_MODE_V2 */
+	u8 mcc_pwr_idx_rsvd_page[MAX_MCC_NUM];
+	u8 enable_runtime_duration;
+	u32 backup_phydm_ability;
+	/* for LG */
+	u8 mchan_sched_mode;
+};
+
+/* backup IQK val */
+void rtw_hal_mcc_restore_iqk_val(PADAPTER padapter);
+
+/* check mcc status */
+u8 rtw_hal_check_mcc_status(PADAPTER padapter, u8 mcc_status);
+
+/* set mcc status */
+void rtw_hal_set_mcc_status(PADAPTER padapter, u8 mcc_status);
+
+/* clear mcc status */
+void rtw_hal_clear_mcc_status(PADAPTER padapter, u8 mcc_status);
+
+/* dl mcc rsvd page */
+u8 rtw_hal_dl_mcc_fw_rsvd_page(_adapter *adapter, u8 *pframe, u16 *index
+	, u8 tx_desc, u32 page_size, u8 *total_page_num, RSVDPAGE_LOC *rsvd_page_loc, u8 *page_num);
+
+/* handle C2H */
+void rtw_hal_mcc_c2h_handler(PADAPTER padapter, u8 buflen, u8 *tmpBuf);
+
+/* switch channel successfully or not */
+void rtw_hal_mcc_sw_status_check(PADAPTER padapter);
+
+/* change some scan flags under site survey */
+u8 rtw_hal_mcc_change_scan_flag(PADAPTER padapter, u8 *ch, u8 *bw, u8 *offset);
+
+/* record data kernel TX to driver to check MCC concurrent TX  */
+void rtw_hal_mcc_calc_tx_bytes_from_kernel(PADAPTER padapter, u32 len);
+
+/* record data to port to let driver do flow ctrl  */
+void rtw_hal_mcc_calc_tx_bytes_to_port(PADAPTER padapter, u32 len);
+
+/* check stop write port or not  */
+u8 rtw_hal_mcc_stop_tx_bytes_to_port(PADAPTER padapter);
+
+u8 rtw_hal_set_mcc_setting_scan_start(PADAPTER padapter);
+
+u8 rtw_hal_set_mcc_setting_scan_complete(PADAPTER padapter);
+
+u8 rtw_hal_set_mcc_setting_start_bss_network(PADAPTER padapter, u8 chbw_grouped);
+
+u8 rtw_hal_set_mcc_setting_disconnect(PADAPTER padapter);
+
+u8 rtw_hal_set_mcc_setting_join_done_chk_ch(PADAPTER padapter);
+
+u8 rtw_hal_set_mcc_setting_chk_start_clnt_join(PADAPTER padapter, u8 *ch, u8 *bw, u8 *offset, u8 chbw_allow);
+
+void rtw_hal_dump_mcc_info(void *sel, struct dvobj_priv *dvobj);
+
+void update_mcc_mgntframe_attrib(_adapter *padapter, struct pkt_attrib *pattrib);
+
+u8 rtw_hal_mcc_link_status_chk(_adapter *padapter, const char *msg);
+
+void rtw_hal_mcc_issue_null_data(_adapter *padapter, u8 chbw_allow, u8 ps_mode);
+
+u8 *rtw_hal_mcc_append_go_p2p_ie(PADAPTER padapter, u8 *pframe, u32 *len);
+
+void rtw_hal_dump_mcc_policy_table(void *sel);
+
+void rtw_hal_mcc_update_macid_bitmap(PADAPTER padapter, int mac_id, u8 add);
+
+void rtw_hal_mcc_process_noa(PADAPTER padapter);
+
+void rtw_hal_mcc_parameter_init(PADAPTER padapter);
+
+u8 rtw_set_mcc_duration_hdl(PADAPTER adapter, u8 type, const u8 *val);
+
+u8 rtw_set_mcc_duration_cmd(_adapter *adapter, u8 type, u8 val);
+#endif /* _RTW_MCC_H_ */
+#endif /* CONFIG_MCC_MODE */
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/include/rtw_mem.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/rtw_mem.h
--- linux-5.6.3/3rdparty/rtl8821ce/include/rtw_mem.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/rtw_mem.h	2020-04-10 16:35:06.851661701 +0300
@@ -0,0 +1,36 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#ifndef __RTW_MEM_H__
+#define __RTW_MEM_H__
+
+#include <drv_conf.h>
+#include <basic_types.h>
+#include <osdep_service.h>
+
+#ifdef CONFIG_PLATFORM_MSTAR_HIGH
+	#define MAX_RTKM_RECVBUF_SZ (31744) /* 31k */
+#else
+	#define MAX_RTKM_RECVBUF_SZ (15360) /* 15k */
+#endif /* CONFIG_PLATFORM_MSTAR_HIGH */
+#define MAX_RTKM_NR_PREALLOC_RECV_SKB 16
+
+u16 rtw_rtkm_get_buff_size(void);
+u8 rtw_rtkm_get_nr_recv_skb(void);
+struct u8 *rtw_alloc_revcbuf_premem(void);
+struct sk_buff *rtw_alloc_skb_premem(u16 in_size);
+int rtw_free_skb_premem(struct sk_buff *pskb);
+
+
+#endif /* __RTW_MEM_H__ */
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/include/rtw_mi.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/rtw_mi.h
--- linux-5.6.3/3rdparty/rtl8821ce/include/rtw_mi.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/rtw_mi.h	2020-04-10 16:35:06.851661701 +0300
@@ -0,0 +1,306 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#ifndef __RTW_MI_H_
+#define __RTW_MI_H_
+
+void rtw_mi_update_union_chan_inf(_adapter *adapter, u8 ch, u8 offset , u8 bw);
+u8 rtw_mi_stayin_union_ch_chk(_adapter *adapter);
+u8 rtw_mi_stayin_union_band_chk(_adapter *adapter);
+
+int rtw_mi_get_ch_setting_union_by_ifbmp(struct dvobj_priv *dvobj, u8 ifbmp, u8 *ch, u8 *bw, u8 *offset);
+int rtw_mi_get_ch_setting_union(_adapter *adapter, u8 *ch, u8 *bw, u8 *offset);
+int rtw_mi_get_ch_setting_union_no_self(_adapter *adapter, u8 *ch, u8 *bw, u8 *offset);
+
+struct mi_state {
+	u8 sta_num;			/* WIFI_STATION_STATE */
+	u8 ld_sta_num;		/* WIFI_STATION_STATE && _FW_LINKED */
+	u8 lg_sta_num;		/* WIFI_STATION_STATE && _FW_UNDER_LINKING */
+#ifdef CONFIG_TDLS
+	u8 ld_tdls_num;		/* adapter.tdlsinfo.link_established */
+#endif
+#ifdef CONFIG_AP_MODE
+	u8 ap_num;			/* WIFI_AP_STATE && _FW_LINKED */
+	u8 starting_ap_num;	/*WIFI_FW_AP_STATE*/
+	u8 ld_ap_num;		/* WIFI_AP_STATE && _FW_LINKED && asoc_sta_count > 2 */
+#endif
+	u8 adhoc_num;		/* (WIFI_ADHOC_STATE | WIFI_ADHOC_MASTER_STATE) && _FW_LINKED */
+	u8 ld_adhoc_num;	/* (WIFI_ADHOC_STATE | WIFI_ADHOC_MASTER_STATE) && _FW_LINKED && asoc_sta_count > 2 */
+#ifdef CONFIG_RTW_MESH
+	u8 mesh_num;		/* WIFI_MESH_STATE &&  _FW_LINKED */
+	u8 ld_mesh_num;		/* WIFI_MESH_STATE &&  _FW_LINKED && asoc_sta_count > 2 */
+#endif
+	u8 scan_num;		/* WIFI_SITE_MONITOR */
+	u8 scan_enter_num;	/* WIFI_SITE_MONITOR && !SCAN_DISABLE && !SCAN_BACK_OP */
+	u8 uwps_num;		/* WIFI_UNDER_WPS */
+#ifdef CONFIG_IOCTL_CFG80211
+	#ifdef CONFIG_P2P
+	u8 roch_num;
+	#endif
+	u8 mgmt_tx_num;
+#endif
+#ifdef CONFIG_P2P
+	u8 p2p_device_num;
+	u8 p2p_gc;
+	u8 p2p_go;
+#endif
+	u8 union_ch;
+	u8 union_bw;
+	u8 union_offset;
+};
+
+#define MSTATE_STA_NUM(_mstate)			((_mstate)->sta_num)
+#define MSTATE_STA_LD_NUM(_mstate)		((_mstate)->ld_sta_num)
+#define MSTATE_STA_LG_NUM(_mstate)		((_mstate)->lg_sta_num)
+
+#ifdef CONFIG_TDLS
+#define MSTATE_TDLS_LD_NUM(_mstate)		((_mstate)->ld_tdls_num)
+#else
+#define MSTATE_TDLS_LD_NUM(_mstate)		0
+#endif
+
+#ifdef CONFIG_AP_MODE
+#define MSTATE_AP_NUM(_mstate)			((_mstate)->ap_num)
+#define MSTATE_AP_STARTING_NUM(_mstate)	((_mstate)->starting_ap_num)
+#define MSTATE_AP_LD_NUM(_mstate)		((_mstate)->ld_ap_num)
+#else
+#define MSTATE_AP_NUM(_mstate)			0
+#define MSTATE_AP_STARTING_NUM(_mstate) 0
+#define MSTATE_AP_LD_NUM(_mstate)		0
+#endif
+
+#define MSTATE_ADHOC_NUM(_mstate)		((_mstate)->adhoc_num)
+#define MSTATE_ADHOC_LD_NUM(_mstate)	((_mstate)->ld_adhoc_num)
+
+#ifdef CONFIG_RTW_MESH
+#define MSTATE_MESH_NUM(_mstate)		((_mstate)->mesh_num)
+#define MSTATE_MESH_LD_NUM(_mstate)		((_mstate)->ld_mesh_num)
+#else
+#define MSTATE_MESH_NUM(_mstate)		0
+#define MSTATE_MESH_LD_NUM(_mstate)		0
+#endif
+
+#define MSTATE_SCAN_NUM(_mstate)		((_mstate)->scan_num)
+#define MSTATE_SCAN_ENTER_NUM(_mstate)	((_mstate)->scan_enter_num)
+#define MSTATE_WPS_NUM(_mstate)			((_mstate)->uwps_num)
+
+#if defined(CONFIG_IOCTL_CFG80211) && defined(CONFIG_P2P)
+#define MSTATE_ROCH_NUM(_mstate)		((_mstate)->roch_num)
+#else
+#define MSTATE_ROCH_NUM(_mstate)		0
+#endif
+
+#ifdef CONFIG_P2P
+#define MSTATE_P2P_DV_NUM(_mstate)		((_mstate)->p2p_device_num)
+#define MSTATE_P2P_GC_NUM(_mstate)		((_mstate)->p2p_gc)
+#define MSTATE_P2P_GO_NUM(_mstate)		((_mstate)->p2p_go)
+#else
+#define MSTATE_P2P_DV_NUM(_mstate)		0
+#define MSTATE_P2P_GC_NUM(_mstate)		0
+#define MSTATE_P2P_GO_NUM(_mstate)		0
+#endif
+
+#if defined(CONFIG_IOCTL_CFG80211)
+#define MSTATE_MGMT_TX_NUM(_mstate)		((_mstate)->mgmt_tx_num)
+#else
+#define MSTATE_MGMT_TX_NUM(_mstate)		0
+#endif
+
+#define MSTATE_U_CH(_mstate)			((_mstate)->union_ch)
+#define MSTATE_U_BW(_mstate)			((_mstate)->union_bw)
+#define MSTATE_U_OFFSET(_mstate)		((_mstate)->union_offset)
+
+#define rtw_mi_get_union_chan(adapter)	adapter_to_dvobj(adapter)->iface_state.union_ch
+#define rtw_mi_get_union_bw(adapter)		adapter_to_dvobj(adapter)->iface_state.union_bw
+#define rtw_mi_get_union_offset(adapter)	adapter_to_dvobj(adapter)->iface_state.union_offset
+
+#define rtw_mi_get_assoced_sta_num(adapter)	DEV_STA_LD_NUM(adapter_to_dvobj(adapter))
+#define rtw_mi_get_ap_num(adapter)			DEV_AP_NUM(adapter_to_dvobj(adapter))
+#define rtw_mi_get_mesh_num(adapter)		DEV_MESH_NUM(adapter_to_dvobj(adapter))
+u8 rtw_mi_get_assoc_if_num(_adapter *adapter);
+
+/* For now, not return union_ch/bw/offset */
+void rtw_mi_status_by_ifbmp(struct dvobj_priv *dvobj, u8 ifbmp, struct mi_state *mstate);
+void rtw_mi_status(_adapter *adapter, struct mi_state *mstate);
+void rtw_mi_status_no_self(_adapter *adapter, struct mi_state *mstate);
+void rtw_mi_status_no_others(_adapter *adapter, struct mi_state *mstate);
+
+/* For now, not handle union_ch/bw/offset */
+void rtw_mi_status_merge(struct mi_state *d, struct mi_state *a);
+
+void rtw_mi_update_iface_status(struct mlme_priv *pmlmepriv, sint state);
+
+u8 rtw_mi_netif_stop_queue(_adapter *padapter);
+u8 rtw_mi_buddy_netif_stop_queue(_adapter *padapter);
+
+u8 rtw_mi_netif_wake_queue(_adapter *padapter);
+u8 rtw_mi_buddy_netif_wake_queue(_adapter *padapter);
+
+u8 rtw_mi_netif_carrier_on(_adapter *padapter);
+u8 rtw_mi_buddy_netif_carrier_on(_adapter *padapter);
+u8 rtw_mi_netif_carrier_off(_adapter *padapter);
+u8 rtw_mi_buddy_netif_carrier_off(_adapter *padapter);
+
+u8 rtw_mi_netif_caroff_qstop(_adapter *padapter);
+u8 rtw_mi_buddy_netif_caroff_qstop(_adapter *padapter);
+u8 rtw_mi_netif_caron_qstart(_adapter *padapter);
+u8 rtw_mi_buddy_netif_caron_qstart(_adapter *padapter);
+
+void rtw_mi_scan_abort(_adapter *adapter, bool bwait);
+void rtw_mi_buddy_scan_abort(_adapter *adapter, bool bwait);
+u32 rtw_mi_start_drv_threads(_adapter *adapter);
+u32 rtw_mi_buddy_start_drv_threads(_adapter *adapter);
+void rtw_mi_stop_drv_threads(_adapter *adapter);
+void rtw_mi_buddy_stop_drv_threads(_adapter *adapter);
+void rtw_mi_cancel_all_timer(_adapter *adapter);
+void rtw_mi_buddy_cancel_all_timer(_adapter *adapter);
+void rtw_mi_reset_drv_sw(_adapter *adapter);
+void rtw_mi_buddy_reset_drv_sw(_adapter *adapter);
+
+extern void rtw_intf_start(_adapter *adapter);
+extern void rtw_intf_stop(_adapter *adapter);
+void rtw_mi_intf_start(_adapter *adapter);
+void rtw_mi_buddy_intf_start(_adapter *adapter);
+void rtw_mi_intf_stop(_adapter *adapter);
+void rtw_mi_buddy_intf_stop(_adapter *adapter);
+
+#ifdef CONFIG_NEW_NETDEV_HDL
+u8 rtw_mi_hal_iface_init(_adapter *padapter);
+#endif
+void rtw_mi_suspend_free_assoc_resource(_adapter *adapter);
+void rtw_mi_buddy_suspend_free_assoc_resource(_adapter *adapter);
+
+#ifdef CONFIG_SET_SCAN_DENY_TIMER
+void rtw_mi_set_scan_deny(_adapter *adapter, u32 ms);
+void rtw_mi_buddy_set_scan_deny(_adapter *adapter, u32 ms);
+#else
+#define rtw_mi_set_scan_deny(adapter, ms) do {} while (0)
+#define rtw_mi_buddy_set_scan_deny(adapter, ms) do {} while (0)
+#endif
+
+u8 rtw_mi_is_scan_deny(_adapter *adapter);
+u8 rtw_mi_buddy_is_scan_deny(_adapter *adapter);
+
+void rtw_mi_beacon_update(_adapter *padapter);
+void rtw_mi_buddy_beacon_update(_adapter *padapter);
+
+void rtw_mi_hal_dump_macaddr(_adapter *padapter);
+void rtw_mi_buddy_hal_dump_macaddr(_adapter *padapter);
+
+#ifdef CONFIG_PCI_HCI
+void rtw_mi_xmit_tasklet_schedule(_adapter *padapter);
+void rtw_mi_buddy_xmit_tasklet_schedule(_adapter *padapter);
+#endif
+
+u8 rtw_mi_busy_traffic_check(_adapter *padapter, bool check_sc_interval);
+u8 rtw_mi_buddy_busy_traffic_check(_adapter *padapter, bool check_sc_interval);
+
+u8 rtw_mi_check_mlmeinfo_state(_adapter *padapter, u32 state);
+u8 rtw_mi_buddy_check_mlmeinfo_state(_adapter *padapter, u32 state);
+
+u8 rtw_mi_check_fwstate(_adapter *padapter, sint state);
+u8 rtw_mi_buddy_check_fwstate(_adapter *padapter, sint state);
+enum {
+	MI_LINKED,
+	MI_ASSOC,
+	MI_UNDER_WPS,
+	MI_AP_MODE,
+	MI_AP_ASSOC,
+	MI_ADHOC,
+	MI_ADHOC_ASSOC,
+	MI_MESH,
+	MI_MESH_ASSOC,
+	MI_STA_NOLINK, /* this is misleading, but not used now */
+	MI_STA_LINKED,
+	MI_STA_LINKING,
+};
+u8 rtw_mi_check_status(_adapter *adapter, u8 type);
+
+void dump_dvobj_mi_status(void *sel, const char *fun_name, _adapter *adapter);
+#ifdef DBG_IFACE_STATUS
+#define DBG_IFACE_STATUS_DUMP(adapter)	dump_dvobj_mi_status(RTW_DBGDUMP, __func__, adapter)
+#endif
+void dump_mi_status(void *sel, struct dvobj_priv *dvobj);
+
+u8 rtw_mi_traffic_statistics(_adapter *padapter);
+u8 rtw_mi_check_miracast_enabled(_adapter *padapter);
+
+#ifdef CONFIG_XMIT_THREAD_MODE
+u8 rtw_mi_check_pending_xmitbuf(_adapter *padapter);
+u8 rtw_mi_buddy_check_pending_xmitbuf(_adapter *padapter);
+#endif
+
+#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
+#ifdef CONFIG_RTL8822B
+	#include <rtl8822b_hal.h>
+#else
+	extern s32 _dequeue_writeport(PADAPTER padapter);
+#endif
+u8 rtw_mi_dequeue_writeport(_adapter *padapter);
+u8 rtw_mi_buddy_dequeue_writeport(_adapter *padapter);
+#endif
+
+void rtw_mi_adapter_reset(_adapter *padapter);
+void rtw_mi_buddy_adapter_reset(_adapter *padapter);
+
+u8 rtw_mi_dynamic_check_timer_handlder(_adapter *padapter);
+u8 rtw_mi_buddy_dynamic_check_timer_handlder(_adapter *padapter);
+
+extern void rtw_iface_dynamic_chk_wk_hdl(_adapter *padapter);
+u8 rtw_mi_dynamic_chk_wk_hdl(_adapter *padapter);
+u8 rtw_mi_buddy_dynamic_chk_wk_hdl(_adapter *padapter);
+
+u8 rtw_mi_os_xmit_schedule(_adapter *padapter);
+u8 rtw_mi_buddy_os_xmit_schedule(_adapter *padapter);
+
+u8 rtw_mi_report_survey_event(_adapter *padapter, union recv_frame *precv_frame);
+u8 rtw_mi_buddy_report_survey_event(_adapter *padapter, union recv_frame *precv_frame);
+
+extern void sreset_start_adapter(_adapter *padapter);
+extern void sreset_stop_adapter(_adapter *padapter);
+u8 rtw_mi_sreset_adapter_hdl(_adapter *padapter, u8 bstart);
+u8 rtw_mi_buddy_sreset_adapter_hdl(_adapter *padapter, u8 bstart);
+#if defined(DBG_CONFIG_ERROR_RESET) && defined(CONFIG_CONCURRENT_MODE)
+void rtw_mi_ap_info_restore(_adapter *adapter);
+#endif
+
+u8 rtw_mi_tx_beacon_hdl(_adapter *padapter);
+u8 rtw_mi_buddy_tx_beacon_hdl(_adapter *padapter);
+
+u8 rtw_mi_set_tx_beacon_cmd(_adapter *padapter);
+u8 rtw_mi_buddy_set_tx_beacon_cmd(_adapter *padapter);
+
+#ifdef CONFIG_P2P
+u8 rtw_mi_p2p_chk_state(_adapter *padapter, enum P2P_STATE p2p_state);
+u8 rtw_mi_buddy_p2p_chk_state(_adapter *padapter, enum P2P_STATE p2p_state);
+u8 rtw_mi_stay_in_p2p_mode(_adapter *padapter);
+u8 rtw_mi_buddy_stay_in_p2p_mode(_adapter *padapter);
+#endif
+
+_adapter *rtw_get_iface_by_id(_adapter *padapter, u8 iface_id);
+_adapter *rtw_get_iface_by_macddr(_adapter *padapter, const u8 *mac_addr);
+_adapter *rtw_get_iface_by_hwport(_adapter *padapter, u8 hw_port);
+
+void rtw_mi_buddy_clone_bcmc_packet(_adapter *padapter, union recv_frame *precvframe, u8 *pphy_status);
+
+#ifdef CONFIG_PCI_HCI
+/*API be create temporary for MI, caller is interrupt-handler, PCIE's interrupt handler cannot apply to multi-AP*/
+_adapter *rtw_mi_get_ap_adapter(_adapter *padapter);
+#endif
+
+u8 rtw_mi_get_ld_sta_ifbmp(_adapter *adapter);
+u8 rtw_mi_get_ap_mesh_ifbmp(_adapter *adapter);
+void rtw_mi_update_ap_bmc_camid(_adapter *padapter, u8 camid_a, u8 camid_b);
+
+#endif /*__RTW_MI_H_*/
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/include/rtw_mlme_ext.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/rtw_mlme_ext.h
--- linux-5.6.3/3rdparty/rtl8821ce/include/rtw_mlme_ext.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/rtw_mlme_ext.h	2020-04-10 16:35:06.851661701 +0300
@@ -0,0 +1,1280 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#ifndef __RTW_MLME_EXT_H_
+#define __RTW_MLME_EXT_H_
+
+
+/*	Commented by Albert 20101105
+ *	Increase the SURVEY_TO value from 100 to 150  ( 100ms to 150ms )
+ *	The Realtek 8188CE SoftAP will spend around 100ms to send the probe response after receiving the probe request.
+ *	So, this driver tried to extend the dwell time for each scanning channel.
+ *	This will increase the chance to receive the probe response from SoftAP. */
+#define SURVEY_TO		(100)
+
+#define REAUTH_TO		(300) /* (50) */
+#define REASSOC_TO		(300) /* (50) */
+/* #define DISCONNECT_TO	(3000) */
+#define ADDBA_TO			(2000)
+
+#define LINKED_TO (1) /* unit:2 sec, 1x2 = 2 sec */
+
+#define REAUTH_LIMIT	(4)
+#define REASSOC_LIMIT	(4)
+#define READDBA_LIMIT	(2)
+
+#ifdef CONFIG_GSPI_HCI
+	#define ROAMING_LIMIT	5
+#else
+	#define ROAMING_LIMIT	8
+#endif
+/* #define	IOCMD_REG0		0x10250370 */
+/* #define	IOCMD_REG1		0x10250374 */
+/* #define	IOCMD_REG2		0x10250378 */
+
+/* #define	FW_DYNAMIC_FUN_SWITCH	0x10250364 */
+
+/* #define	WRITE_BB_CMD		0xF0000001 */
+/* #define	SET_CHANNEL_CMD	0xF3000000 */
+/* #define	UPDATE_RA_CMD	0xFD0000A2 */
+
+#define _HW_STATE_NOLINK_		0x00
+#define _HW_STATE_ADHOC_		0x01
+#define _HW_STATE_STATION_	0x02
+#define _HW_STATE_AP_			0x03
+#define _HW_STATE_MONITOR_ 0x04
+
+
+#define		_1M_RATE_	0
+#define		_2M_RATE_	1
+#define		_5M_RATE_	2
+#define		_11M_RATE_	3
+#define		_6M_RATE_	4
+#define		_9M_RATE_	5
+#define		_12M_RATE_	6
+#define		_18M_RATE_	7
+#define		_24M_RATE_	8
+#define		_36M_RATE_	9
+#define		_48M_RATE_	10
+#define		_54M_RATE_	11
+
+/********************************************************
+MCS rate definitions
+*********************************************************/
+#define MCS_RATE_1R	(0x000000ff)
+#define MCS_RATE_2R	(0x0000ffff)
+#define MCS_RATE_3R	(0x00ffffff)
+#define MCS_RATE_4R	(0xffffffff)
+#define MCS_RATE_2R_13TO15_OFF	(0x00001fff)
+
+
+extern unsigned char RTW_WPA_OUI[];
+extern unsigned char WMM_OUI[];
+extern unsigned char WPS_OUI[];
+extern unsigned char WFD_OUI[];
+extern unsigned char P2P_OUI[];
+
+extern unsigned char WMM_INFO_OUI[];
+extern unsigned char WMM_PARA_OUI[];
+
+typedef struct _RT_CHANNEL_PLAN {
+	unsigned char	Channel[MAX_CHANNEL_NUM];
+	unsigned char	Len;
+} RT_CHANNEL_PLAN, *PRT_CHANNEL_PLAN;
+
+enum Associated_AP {
+	atherosAP	= 0,
+	broadcomAP	= 1,
+	ciscoAP		= 2,
+	marvellAP	= 3,
+	ralinkAP	= 4,
+	realtekAP	= 5,
+	airgocapAP	= 6,
+	unknownAP	= 7,
+	maxAP,
+};
+
+typedef enum _HT_IOT_PEER {
+	HT_IOT_PEER_UNKNOWN			= 0,
+	HT_IOT_PEER_REALTEK			= 1,
+	HT_IOT_PEER_REALTEK_92SE		= 2,
+	HT_IOT_PEER_BROADCOM		= 3,
+	HT_IOT_PEER_RALINK			= 4,
+	HT_IOT_PEER_ATHEROS			= 5,
+	HT_IOT_PEER_CISCO				= 6,
+	HT_IOT_PEER_MERU				= 7,
+	HT_IOT_PEER_MARVELL			= 8,
+	HT_IOT_PEER_REALTEK_SOFTAP 	= 9,/* peer is RealTek SOFT_AP, by Bohn, 2009.12.17 */
+	HT_IOT_PEER_SELF_SOFTAP 		= 10, /* Self is SoftAP */
+	HT_IOT_PEER_AIRGO				= 11,
+	HT_IOT_PEER_INTEL				= 12,
+	HT_IOT_PEER_RTK_APCLIENT		= 13,
+	HT_IOT_PEER_REALTEK_81XX		= 14,
+	HT_IOT_PEER_REALTEK_WOW		= 15,
+	HT_IOT_PEER_REALTEK_JAGUAR_BCUTAP = 16,
+	HT_IOT_PEER_REALTEK_JAGUAR_CCUTAP = 17,
+	HT_IOT_PEER_MAX				= 18
+} HT_IOT_PEER_E, *PHTIOT_PEER_E;
+
+
+typedef enum _RT_HT_INF0_CAP {
+	RT_HT_CAP_USE_TURBO_AGGR = 0x01,
+	RT_HT_CAP_USE_LONG_PREAMBLE = 0x02,
+	RT_HT_CAP_USE_AMPDU = 0x04,
+	RT_HT_CAP_USE_WOW = 0x8,
+	RT_HT_CAP_USE_SOFTAP = 0x10,
+	RT_HT_CAP_USE_92SE = 0x20,
+	RT_HT_CAP_USE_88C_92C = 0x40,
+	RT_HT_CAP_USE_AP_CLIENT_MODE = 0x80,	/* AP team request to reserve this bit, by Emily */
+} RT_HT_INF0_CAPBILITY, *PRT_HT_INF0_CAPBILITY;
+
+typedef enum _RT_HT_INF1_CAP {
+	RT_HT_CAP_USE_VIDEO_CLIENT = 0x01,
+	RT_HT_CAP_USE_JAGUAR_BCUT = 0x02,
+	RT_HT_CAP_USE_JAGUAR_CCUT = 0x04,
+} RT_HT_INF1_CAPBILITY, *PRT_HT_INF1_CAPBILITY;
+
+struct mlme_handler {
+	unsigned int   num;
+	char *str;
+	unsigned int (*func)(_adapter *padapter, union recv_frame *precv_frame);
+};
+
+struct action_handler {
+	unsigned int   num;
+	char *str;
+	unsigned int (*func)(_adapter *padapter, union recv_frame *precv_frame);
+};
+
+enum SCAN_STATE {
+	SCAN_DISABLE = 0,
+	SCAN_START = 1,
+	SCAN_PS_ANNC_WAIT = 2,
+	SCAN_ENTER = 3,
+	SCAN_PROCESS = 4,
+
+	/* backop */
+	SCAN_BACKING_OP = 5,
+	SCAN_BACK_OP = 6,
+	SCAN_LEAVING_OP = 7,
+	SCAN_LEAVE_OP = 8,
+
+	/* SW antenna diversity (before linked) */
+	SCAN_SW_ANTDIV_BL = 9,
+
+	/* legacy p2p */
+	SCAN_TO_P2P_LISTEN = 10,
+	SCAN_P2P_LISTEN = 11,
+
+	SCAN_COMPLETE = 12,
+	SCAN_STATE_MAX,
+};
+
+const char *scan_state_str(u8 state);
+
+enum ss_backop_flag {
+	SS_BACKOP_EN = BIT0, /* backop when linked */
+	SS_BACKOP_EN_NL = BIT1, /* backop even when no linked */
+
+	SS_BACKOP_PS_ANNC = BIT4,
+	SS_BACKOP_TX_RESUME = BIT5,
+};
+
+struct ss_res {
+	u8 state;
+	u8 next_state; /* will set to state on next cmd hdl */
+	int	bss_cnt;
+	int	channel_idx;
+#ifdef CONFIG_DFS
+	u8 dfs_ch_ssid_scan;
+#endif
+	int	scan_mode;
+	u16 scan_ch_ms;
+	u32 scan_timeout_ms;
+	u8 rx_ampdu_accept;
+	u8 rx_ampdu_size;
+	u8 igi_scan;
+	u8 igi_before_scan; /* used for restoring IGI value without enable DIG & FA_CNT */
+#ifdef CONFIG_SCAN_BACKOP
+	u8 backop_flags_sta; /* policy for station mode*/
+	#ifdef CONFIG_AP_MODE
+	u8 backop_flags_ap; /* policy for ap mode */
+	#endif
+	#ifdef CONFIG_RTW_MESH
+	u8 backop_flags_mesh; /* policy for mesh mode */
+	#endif
+	u8 backop_flags; /* per backop runtime decision */
+	u8 scan_cnt;
+	u8 scan_cnt_max;
+	systime backop_time; /* the start time of backop */
+	u16 backop_ms;
+#endif
+#if defined(CONFIG_ANTENNA_DIVERSITY) || defined(DBG_SCAN_SW_ANTDIV_BL)
+	u8 is_sw_antdiv_bl_scan;
+#endif
+	u8 ssid_num;
+	u8 ch_num;
+	NDIS_802_11_SSID ssid[RTW_SSID_SCAN_AMOUNT];
+	struct rtw_ieee80211_channel ch[RTW_CHANNEL_SCAN_AMOUNT];
+
+	u32 token; 	/* 0: use to identify caller */
+	u16 duration;	/* 0: use default */
+	u8 igi;		/* 0: use defalut */
+	u8 bw;		/* 0: use default */
+};
+
+/* #define AP_MODE				0x0C */
+/* #define STATION_MODE	0x08 */
+/* #define AD_HOC_MODE		0x04 */
+/* #define NO_LINK_MODE	0x00 */
+
+#define	WIFI_FW_NULL_STATE			_HW_STATE_NOLINK_
+#define	WIFI_FW_STATION_STATE		_HW_STATE_STATION_
+#define	WIFI_FW_AP_STATE				_HW_STATE_AP_
+#define	WIFI_FW_ADHOC_STATE			_HW_STATE_ADHOC_
+
+#define WIFI_FW_PRE_LINK			0x00000800
+#define	WIFI_FW_AUTH_NULL			0x00000100
+#define	WIFI_FW_AUTH_STATE			0x00000200
+#define	WIFI_FW_AUTH_SUCCESS			0x00000400
+
+#define	WIFI_FW_ASSOC_STATE			0x00002000
+#define	WIFI_FW_ASSOC_SUCCESS		0x00004000
+
+#define	WIFI_FW_LINKING_STATE		(WIFI_FW_AUTH_NULL | WIFI_FW_AUTH_STATE | WIFI_FW_AUTH_SUCCESS | WIFI_FW_ASSOC_STATE)
+
+#ifdef CONFIG_TDLS
+enum TDLS_option {
+	TDLS_ESTABLISHED = 1,
+	TDLS_ISSUE_PTI,
+	TDLS_CH_SW_RESP,
+	TDLS_CH_SW_PREPARE,
+	TDLS_CH_SW_START,
+	TDLS_CH_SW_TO_OFF_CHNL,
+	TDLS_CH_SW_TO_BASE_CHNL_UNSOLICITED,
+	TDLS_CH_SW_TO_BASE_CHNL,
+	TDLS_CH_SW_END_TO_BASE_CHNL,
+	TDLS_CH_SW_END,
+	TDLS_RS_RCR,
+	TDLS_TEARDOWN_STA,
+	TDLS_TEARDOWN_STA_NO_WAIT,
+	TDLS_TEARDOWN_STA_LOCALLY,
+	TDLS_TEARDOWN_STA_LOCALLY_POST,
+	maxTDLS,
+};
+
+#endif /* CONFIG_TDLS */
+
+/*
+ * Usage:
+ * When one iface acted as AP mode and the other iface is STA mode and scanning,
+ * it should switch back to AP's operating channel periodically.
+ * Parameters info:
+ * When the driver scanned RTW_SCAN_NUM_OF_CH channels, it would switch back to AP's operating channel for
+ * RTW_BACK_OP_CH_MS milliseconds.
+ * Example:
+ * For chip supports 2.4G + 5GHz and AP mode is operating in channel 1,
+ * RTW_SCAN_NUM_OF_CH is 8, RTW_BACK_OP_CH_MS is 300
+ * When it's STA mode gets set_scan command,
+ * it would
+ * 1. Doing the scan on channel 1.2.3.4.5.6.7.8
+ * 2. Back to channel 1 for 300 milliseconds
+ * 3. Go through doing site survey on channel 9.10.11.36.40.44.48.52
+ * 4. Back to channel 1 for 300 milliseconds
+ * 5. ... and so on, till survey done.
+ */
+#if defined(CONFIG_ATMEL_RC_PATCH)
+	#define RTW_SCAN_NUM_OF_CH 2
+	#define RTW_BACK_OP_CH_MS 200
+#else
+	#define RTW_SCAN_NUM_OF_CH 3
+	#define RTW_BACK_OP_CH_MS 400
+#endif
+
+#define RTW_IP_ADDR_LEN 4
+#define RTW_IPv6_ADDR_LEN 16
+
+struct mlme_ext_info {
+	u32	state;
+#ifdef CONFIG_MI_WITH_MBSSID_CAM
+	u8	hw_media_state;
+#endif
+	u32	reauth_count;
+	u32	reassoc_count;
+	u32	link_count;
+	u32	auth_seq;
+	u32	auth_algo;	/* 802.11 auth, could be open, shared, auto */
+	u16 auth_status;
+	u32	authModeToggle;
+	u32	enc_algo;/* encrypt algorithm; */
+	u32	key_index;	/* this is only valid for legendary wep, 0~3 for key id. */
+	u32	iv;
+	u8	chg_txt[128];
+	u16	aid;
+	u16	bcn_interval;
+	u16	capability;
+	u8	assoc_AP_vendor;
+	u8	slotTime;
+	u8	preamble_mode;
+	u8	WMM_enable;
+	u8	ERP_enable;
+	u8	ERP_IE;
+	u8	HT_enable;
+	u8	HT_caps_enable;
+	u8	HT_info_enable;
+	u8	HT_protection;
+	u8	turboMode_cts2self;
+	u8	turboMode_rtsen;
+	u8	SM_PS;
+	u8	agg_enable_bitmap;
+	u8	ADDBA_retry_count;
+	u8	candidate_tid_bitmap;
+	u8	dialogToken;
+	/* Accept ADDBA Request */
+	BOOLEAN bAcceptAddbaReq;
+	u8	bwmode_updated;
+	u8	hidden_ssid_mode;
+	u8	VHT_enable;
+
+	u8 ip_addr[RTW_IP_ADDR_LEN];
+	u8 ip6_addr[RTW_IPv6_ADDR_LEN];
+
+	struct ADDBA_request		ADDBA_req;
+	struct WMM_para_element	WMM_param;
+	struct HT_caps_element	HT_caps;
+	struct HT_info_element		HT_info;
+	WLAN_BSSID_EX			network;/* join network or bss_network, if in ap mode, it is the same to cur_network.network */
+#ifdef ROKU_PRIVATE
+	/*infra mode, store supported rates from AssocRsp*/
+	NDIS_802_11_RATES_EX	SupportedRates_infra_ap;
+	u8 ht_vht_received;/*ht_vht_received used to show debug msg BIT(0):HT BIT(1):VHT */
+#endif /* ROKU_PRIVATE */
+};
+
+/* The channel information about this channel including joining, scanning, and power constraints. */
+typedef struct _RT_CHANNEL_INFO {
+	u8				ChannelNum;		/* The channel number. */
+	RT_SCAN_TYPE	ScanType;		/* Scan type such as passive or active scan. */
+	/* u16				ScanPeriod;		 */ /* Listen time in millisecond in this channel. */
+	/* s32				MaxTxPwrDbm;	 */ /* Max allowed tx power. */
+	/* u32				ExInfo;			 */ /* Extended Information for this channel. */
+#ifdef CONFIG_FIND_BEST_CHANNEL
+	u32				rx_count;
+#endif
+#ifdef CONFIG_DFS
+	#ifdef CONFIG_DFS_MASTER
+	systime non_ocp_end_time;
+	#endif
+	u8 hidden_bss_cnt; /* per scan count */
+#endif
+} RT_CHANNEL_INFO, *PRT_CHANNEL_INFO;
+
+#define CAC_TIME_MS (60*1000)
+#define CAC_TIME_CE_MS (10*60*1000)
+#define NON_OCP_TIME_MS (30*60*1000)
+
+#ifdef CONFIG_TXPWR_LIMIT
+void rtw_txpwr_init_regd(struct rf_ctl_t *rfctl);
+#endif
+void rtw_rfctl_init(_adapter *adapter);
+void rtw_rfctl_deinit(_adapter *adapter);
+
+#ifdef CONFIG_DFS_MASTER
+struct rf_ctl_t;
+#define CH_IS_NON_OCP(rt_ch_info) (rtw_time_after((rt_ch_info)->non_ocp_end_time, rtw_get_current_time()))
+bool rtw_is_cac_reset_needed(struct rf_ctl_t *rfctl, u8 ch, u8 bw, u8 offset);
+bool _rtw_rfctl_overlap_radar_detect_ch(struct rf_ctl_t *rfctl, u8 ch, u8 bw, u8 offset);
+bool rtw_rfctl_overlap_radar_detect_ch(struct rf_ctl_t *rfctl);
+bool rtw_rfctl_is_tx_blocked_by_ch_waiting(struct rf_ctl_t *rfctl);
+bool rtw_chset_is_chbw_non_ocp(RT_CHANNEL_INFO *ch_set, u8 ch, u8 bw, u8 offset);
+bool rtw_chset_is_ch_non_ocp(RT_CHANNEL_INFO *ch_set, u8 ch);
+void rtw_chset_update_non_ocp(RT_CHANNEL_INFO *ch_set, u8 ch, u8 bw, u8 offset);
+void rtw_chset_update_non_ocp_ms(RT_CHANNEL_INFO *ch_set, u8 ch, u8 bw, u8 offset, int ms);
+u32 rtw_get_ch_waiting_ms(struct rf_ctl_t *rfctl, u8 ch, u8 bw, u8 offset, u32 *r_non_ocp_ms, u32 *r_cac_ms);
+void rtw_reset_cac(struct rf_ctl_t *rfctl, u8 ch, u8 bw, u8 offset);
+u32 rtw_force_stop_cac(struct rf_ctl_t *rfctl, u32 timeout_ms);
+#else
+#define CH_IS_NON_OCP(rt_ch_info) 0
+#define rtw_chset_is_chbw_non_ocp(ch_set, ch, bw, offset) _FALSE
+#define rtw_chset_is_ch_non_ocp(ch_set, ch) _FALSE
+#define rtw_rfctl_is_tx_blocked_by_ch_waiting(rfctl) _FALSE
+#endif
+
+enum {
+	RTW_CHF_2G = BIT0,
+	RTW_CHF_5G = BIT1,
+	RTW_CHF_DFS = BIT2,
+	RTW_CHF_LONG_CAC = BIT3,
+	RTW_CHF_NON_DFS = BIT4,
+	RTW_CHF_NON_LONG_CAC = BIT5,
+	RTW_CHF_NON_OCP = BIT6,
+};
+
+bool rtw_choose_shortest_waiting_ch(struct rf_ctl_t *rfctl, u8 sel_ch, u8 max_bw
+	, u8 *dec_ch, u8 *dec_bw, u8 *dec_offset
+	, u8 d_flags, u8 cur_ch, u8 same_band_prefer, u8 mesh_only);
+
+void dump_chset(void *sel, RT_CHANNEL_INFO *ch_set);
+void dump_cur_chset(void *sel, struct rf_ctl_t *rfctl);
+
+int rtw_chset_search_ch(RT_CHANNEL_INFO *ch_set, const u32 ch);
+u8 rtw_chset_is_chbw_valid(RT_CHANNEL_INFO *ch_set, u8 ch, u8 bw, u8 offset);
+void rtw_chset_sync_chbw(RT_CHANNEL_INFO *ch_set, u8 *req_ch, u8 *req_bw, u8 *req_offset
+	, u8 *g_ch, u8 *g_bw, u8 *g_offset);
+
+bool rtw_mlme_band_check(_adapter *adapter, const u32 ch);
+
+
+enum {
+	BAND_24G = BIT0,
+	BAND_5G = BIT1,
+};
+void RTW_SET_SCAN_BAND_SKIP(_adapter *padapter, int skip_band);
+void RTW_CLR_SCAN_BAND_SKIP(_adapter *padapter, int skip_band);
+int RTW_GET_SCAN_BAND_SKIP(_adapter *padapter);
+
+bool rtw_mlme_ignore_chan(_adapter *adapter, const u32 ch);
+
+/* P2P_MAX_REG_CLASSES - Maximum number of regulatory classes */
+#define P2P_MAX_REG_CLASSES 10
+
+/* P2P_MAX_REG_CLASS_CHANNELS - Maximum number of channels per regulatory class */
+#define P2P_MAX_REG_CLASS_CHANNELS 20
+
+/* struct p2p_channels - List of supported channels */
+struct p2p_channels {
+	/* struct p2p_reg_class - Supported regulatory class */
+	struct p2p_reg_class {
+		/* reg_class - Regulatory class (IEEE 802.11-2007, Annex J) */
+		u8 reg_class;
+
+		/* channel - Supported channels */
+		u8 channel[P2P_MAX_REG_CLASS_CHANNELS];
+
+		/* channels - Number of channel entries in use */
+		size_t channels;
+	} reg_class[P2P_MAX_REG_CLASSES];
+
+	/* reg_classes - Number of reg_class entries in use */
+	size_t reg_classes;
+};
+
+struct p2p_oper_class_map {
+	enum hw_mode {IEEE80211G, IEEE80211A} mode;
+	u8 op_class;
+	u8 min_chan;
+	u8 max_chan;
+	u8 inc;
+	enum { BW20, BW40PLUS, BW40MINUS } bw;
+};
+
+struct mlme_ext_priv {
+	_adapter	*padapter;
+	u8	mlmeext_init;
+	ATOMIC_T		event_seq;
+	u16	mgnt_seq;
+#ifdef CONFIG_IEEE80211W
+	u16	sa_query_seq;
+#endif
+	/* struct fw_priv 	fwpriv; */
+
+	unsigned char	cur_channel;
+	unsigned char	cur_bwmode;
+	unsigned char	cur_ch_offset;/* PRIME_CHNL_OFFSET */
+	unsigned char	cur_wireless_mode;	/* NETWORK_TYPE */
+
+	unsigned char	basicrate[NumRates];
+	unsigned char	datarate[NumRates];
+#ifdef CONFIG_80211N_HT
+	unsigned char default_supported_mcs_set[16];
+#endif
+
+	struct ss_res		sitesurvey_res;
+	struct mlme_ext_info	mlmext_info;/* for sta/adhoc mode, including current scanning/connecting/connected related info.
+                                                      * for ap mode, network includes ap's cap_info */
+	_timer		survey_timer;
+	_timer		link_timer;
+
+#ifdef CONFIG_RTW_REPEATER_SON
+	_timer		rson_scan_timer;
+#endif
+#ifdef CONFIG_RTW_80211R
+	_timer		ft_link_timer;
+	_timer		ft_roam_timer;
+#endif
+
+	systime last_scan_time;
+	u8	scan_abort;
+	u8 join_abort;
+	u8	tx_rate; /* TXRATE when USERATE is set. */
+
+	u32	retry; /* retry for issue probereq */
+
+	u64 TSFValue;
+	u32 bcn_cnt;
+	u32 last_bcn_cnt;
+	u8 cur_bcn_cnt;/*2s*/
+	u8 dtim;/*DTIM Period*/
+#ifdef DBG_RX_BCN
+	u8 tim[4];
+#endif
+#ifdef CONFIG_BCN_RECV_TIME
+	u16 bcn_rx_time;
+#endif
+#ifdef CONFIG_AP_MODE
+	unsigned char bstart_bss;
+#endif
+
+#ifdef CONFIG_80211D
+	u8 update_channel_plan_by_ap_done;
+#endif
+	/* recv_decache check for Action_public frame */
+	u8 action_public_dialog_token;
+	u16	 action_public_rxseq;
+
+	/* #ifdef CONFIG_ACTIVE_KEEP_ALIVE_CHECK */
+	u8 active_keep_alive_check;
+	/* #endif */
+#ifdef DBG_FIXED_CHAN
+	u8 fixed_chan;
+#endif
+
+	u8 tsf_update_required:1;
+	u8 en_hw_update_tsf:1; /* set hw sync bcn tsf register or not */
+	systime tsf_update_pause_stime;
+	u8 tsf_update_pause_factor; /* num of bcn intervals to stay TSF update pause status */
+	u8 tsf_update_restore_factor; /* num of bcn interval to stay TSF update restore status */
+};
+
+struct support_rate_handler {
+	u8 rate;
+	bool basic;
+	bool existence;
+};
+
+static inline u8 check_mlmeinfo_state(struct mlme_ext_priv *plmeext, sint state)
+{
+	if ((plmeext->mlmext_info.state & 0x03) == state)
+		return _TRUE;
+
+	return _FALSE;
+}
+
+void sitesurvey_set_offch_state(_adapter *adapter, u8 scan_state);
+
+#define mlmeext_msr(mlmeext) ((mlmeext)->mlmext_info.state & 0x03)
+#define mlmeext_scan_state(mlmeext) ((mlmeext)->sitesurvey_res.state)
+#define mlmeext_scan_state_str(mlmeext) scan_state_str((mlmeext)->sitesurvey_res.state)
+#define mlmeext_chk_scan_state(mlmeext, _state) ((mlmeext)->sitesurvey_res.state == (_state))
+#define mlmeext_set_scan_state(mlmeext, _state) \
+	do { \
+		((mlmeext)->sitesurvey_res.state = (_state)); \
+		((mlmeext)->sitesurvey_res.next_state = (_state)); \
+		rtw_mi_update_iface_status(&((container_of(mlmeext, _adapter, mlmeextpriv)->mlmepriv)), 0); \
+		/* RTW_INFO("set_scan_state:%s\n", scan_state_str(_state)); */ \
+		sitesurvey_set_offch_state(container_of(mlmeext, _adapter, mlmeextpriv), _state); \
+	} while (0)
+
+#define mlmeext_scan_next_state(mlmeext) ((mlmeext)->sitesurvey_res.next_state)
+#define mlmeext_set_scan_next_state(mlmeext, _state) \
+	do { \
+		((mlmeext)->sitesurvey_res.next_state = (_state)); \
+		/* RTW_INFO("set_scan_next_state:%s\n", scan_state_str(_state)); */ \
+	} while (0)
+
+#ifdef CONFIG_SCAN_BACKOP
+#define mlmeext_scan_backop_flags(mlmeext) ((mlmeext)->sitesurvey_res.backop_flags)
+#define mlmeext_chk_scan_backop_flags(mlmeext, flags) ((mlmeext)->sitesurvey_res.backop_flags & (flags))
+#define mlmeext_assign_scan_backop_flags(mlmeext, flags) \
+	do { \
+		((mlmeext)->sitesurvey_res.backop_flags = (flags)); \
+		RTW_INFO("assign_scan_backop_flags:0x%02x\n", (mlmeext)->sitesurvey_res.backop_flags); \
+	} while (0)
+
+#define mlmeext_scan_backop_flags_sta(mlmeext) ((mlmeext)->sitesurvey_res.backop_flags_sta)
+#define mlmeext_chk_scan_backop_flags_sta(mlmeext, flags) ((mlmeext)->sitesurvey_res.backop_flags_sta & (flags))
+#define mlmeext_assign_scan_backop_flags_sta(mlmeext, flags) \
+	do { \
+		((mlmeext)->sitesurvey_res.backop_flags_sta = (flags)); \
+	} while (0)
+#else
+#define mlmeext_scan_backop_flags(mlmeext) (0)
+#define mlmeext_chk_scan_backop_flags(mlmeext, flags) (0)
+#define mlmeext_assign_scan_backop_flags(mlmeext, flags) do {} while (0)
+
+#define mlmeext_scan_backop_flags_sta(mlmeext) (0)
+#define mlmeext_chk_scan_backop_flags_sta(mlmeext, flags) (0)
+#define mlmeext_assign_scan_backop_flags_sta(mlmeext, flags) do {} while (0)
+#endif /* CONFIG_SCAN_BACKOP */
+
+#if defined(CONFIG_SCAN_BACKOP) && defined(CONFIG_AP_MODE)
+#define mlmeext_scan_backop_flags_ap(mlmeext) ((mlmeext)->sitesurvey_res.backop_flags_ap)
+#define mlmeext_chk_scan_backop_flags_ap(mlmeext, flags) ((mlmeext)->sitesurvey_res.backop_flags_ap & (flags))
+#define mlmeext_assign_scan_backop_flags_ap(mlmeext, flags) \
+	do { \
+		((mlmeext)->sitesurvey_res.backop_flags_ap = (flags)); \
+	} while (0)
+#else
+#define mlmeext_scan_backop_flags_ap(mlmeext) (0)
+#define mlmeext_chk_scan_backop_flags_ap(mlmeext, flags) (0)
+#define mlmeext_assign_scan_backop_flags_ap(mlmeext, flags) do {} while (0)
+#endif /* defined(CONFIG_SCAN_BACKOP) && defined(CONFIG_AP_MODE) */
+
+#if defined(CONFIG_SCAN_BACKOP) && defined(CONFIG_RTW_MESH)
+#define mlmeext_scan_backop_flags_mesh(mlmeext) ((mlmeext)->sitesurvey_res.backop_flags_mesh)
+#define mlmeext_chk_scan_backop_flags_mesh(mlmeext, flags) ((mlmeext)->sitesurvey_res.backop_flags_mesh & (flags))
+#define mlmeext_assign_scan_backop_flags_mesh(mlmeext, flags) \
+	do { \
+		((mlmeext)->sitesurvey_res.backop_flags_mesh = (flags)); \
+	} while (0)
+#else
+#define mlmeext_scan_backop_flags_mesh(mlmeext) (0)
+#define mlmeext_chk_scan_backop_flags_mesh(mlmeext, flags) (0)
+#define mlmeext_assign_scan_backop_flags_mesh(mlmeext, flags) do {} while (0)
+#endif /* defined(CONFIG_SCAN_BACKOP) && defined(CONFIG_RTW_MESH) */
+
+u32 rtw_scan_timeout_decision(_adapter *padapter);
+
+void init_mlme_default_rate_set(_adapter *padapter);
+int init_mlme_ext_priv(_adapter *padapter);
+int init_hw_mlme_ext(_adapter *padapter);
+void free_mlme_ext_priv(struct mlme_ext_priv *pmlmeext);
+extern struct xmit_frame *alloc_mgtxmitframe(struct xmit_priv *pxmitpriv);
+struct xmit_frame *alloc_mgtxmitframe_once(struct xmit_priv *pxmitpriv);
+
+/* void fill_fwpriv(_adapter * padapter, struct fw_priv *pfwpriv); */
+u8 judge_network_type(_adapter *padapter, unsigned char *rate, int ratelen);
+void get_rate_set(_adapter *padapter, unsigned char *pbssrate, int *bssrate_len);
+void set_mcs_rate_by_mask(u8 *mcs_set, u32 mask);
+void UpdateBrateTbl(_adapter *padapter, u8 *mBratesOS);
+void UpdateBrateTblForSoftAP(u8 *bssrateset, u32 bssratelen);
+void change_band_update_ie(_adapter *padapter, WLAN_BSSID_EX *pnetwork, u8 ch);
+
+void Set_MSR(_adapter *padapter, u8 type);
+
+u8 rtw_get_oper_ch(_adapter *adapter);
+void rtw_set_oper_ch(_adapter *adapter, u8 ch);
+u8 rtw_get_oper_bw(_adapter *adapter);
+void rtw_set_oper_bw(_adapter *adapter, u8 bw);
+u8 rtw_get_oper_choffset(_adapter *adapter);
+void rtw_set_oper_choffset(_adapter *adapter, u8 offset);
+u8	rtw_get_center_ch(u8 channel, u8 chnl_bw, u8 chnl_offset);
+systime rtw_get_on_oper_ch_time(_adapter *adapter);
+systime rtw_get_on_cur_ch_time(_adapter *adapter);
+
+u8 rtw_get_offset_by_chbw(u8 ch, u8 bw, u8 *r_offset);
+
+void set_channel_bwmode(_adapter *padapter, unsigned char channel, unsigned char channel_offset, unsigned short bwmode);
+
+unsigned int decide_wait_for_beacon_timeout(unsigned int bcn_interval);
+
+void _clear_cam_entry(_adapter *padapter, u8 entry);
+void write_cam_from_cache(_adapter *adapter, u8 id);
+void rtw_sec_cam_swap(_adapter *adapter, u8 cam_id_a, u8 cam_id_b);
+void rtw_clean_dk_section(_adapter *adapter);
+void rtw_clean_hw_dk_cam(_adapter *adapter);
+
+/* modify both HW and cache */
+void write_cam(_adapter *padapter, u8 id, u16 ctrl, u8 *mac, u8 *key);
+void clear_cam_entry(_adapter *padapter, u8 id);
+
+/* modify cache only */
+void write_cam_cache(_adapter *adapter, u8 id, u16 ctrl, u8 *mac, u8 *key);
+void clear_cam_cache(_adapter *adapter, u8 id);
+
+void invalidate_cam_all(_adapter *padapter);
+void CAM_empty_entry(PADAPTER Adapter, u8 ucIndex);
+
+void flush_all_cam_entry(_adapter *padapter);
+
+BOOLEAN IsLegal5GChannel(PADAPTER Adapter, u8 channel);
+
+void site_survey(_adapter *padapter, u8 survey_channel, RT_SCAN_TYPE ScanType);
+u8 collect_bss_info(_adapter *padapter, union recv_frame *precv_frame, WLAN_BSSID_EX *bssid);
+void update_network(WLAN_BSSID_EX *dst, WLAN_BSSID_EX *src, _adapter *padapter, bool update_ie);
+
+u8 *get_my_bssid(WLAN_BSSID_EX *pnetwork);
+u16 get_beacon_interval(WLAN_BSSID_EX *bss);
+
+int is_client_associated_to_ap(_adapter *padapter);
+int is_client_associated_to_ibss(_adapter *padapter);
+int is_IBSS_empty(_adapter *padapter);
+
+unsigned char check_assoc_AP(u8 *pframe, uint len);
+void get_assoc_AP_Vendor(char *vendor, u8 assoc_AP_vendor);
+#ifdef CONFIG_80211AC_VHT
+unsigned char get_vht_mu_bfer_cap(u8 *pframe, uint len);
+#endif
+
+int WMM_param_handler(_adapter *padapter, PNDIS_802_11_VARIABLE_IEs	pIE);
+#ifdef CONFIG_WFD
+void rtw_process_wfd_ie(_adapter *adapter, u8 *ie, u8 ie_len, const char *tag);
+void rtw_process_wfd_ies(_adapter *adapter, u8 *ies, u8 ies_len, const char *tag);
+#endif
+void WMMOnAssocRsp(_adapter *padapter);
+
+void HT_caps_handler(_adapter *padapter, PNDIS_802_11_VARIABLE_IEs pIE);
+#ifdef ROKU_PRIVATE
+void HT_caps_handler_infra_ap(_adapter *padapter, PNDIS_802_11_VARIABLE_IEs pIE);
+#endif
+void HT_info_handler(_adapter *padapter, PNDIS_802_11_VARIABLE_IEs pIE);
+void HTOnAssocRsp(_adapter *padapter);
+
+#ifdef ROKU_PRIVATE
+void Supported_rate_infra_ap(_adapter *padapter, PNDIS_802_11_VARIABLE_IEs pIE);
+void Extended_Supported_rate_infra_ap(_adapter *padapter, PNDIS_802_11_VARIABLE_IEs pIE);
+#endif
+
+void ERP_IE_handler(_adapter *padapter, PNDIS_802_11_VARIABLE_IEs pIE);
+void VCS_update(_adapter *padapter, struct sta_info *psta);
+void	update_ldpc_stbc_cap(struct sta_info *psta);
+
+bool rtw_validate_value(u16 EID, u8 *p, u16 len);
+bool hidden_ssid_ap(WLAN_BSSID_EX *snetwork);
+void rtw_absorb_ssid_ifneed(_adapter *padapter, WLAN_BSSID_EX *bssid, u8 *pframe);
+int rtw_get_bcn_keys(ADAPTER *Adapter, u8 *pframe, u32 packet_len,
+		struct beacon_keys *recv_beacon);
+int validate_beacon_len(u8 *pframe, uint len);
+void rtw_dump_bcn_keys(struct beacon_keys *recv_beacon);
+int rtw_check_bcn_info(ADAPTER *Adapter, u8 *pframe, u32 packet_len);
+void update_beacon_info(_adapter *padapter, u8 *pframe, uint len, struct sta_info *psta);
+#ifdef CONFIG_DFS
+void process_csa_ie(_adapter *padapter, u8 *ies, uint ies_len);
+#endif /* CONFIG_DFS */
+void update_capinfo(PADAPTER Adapter, u16 updateCap);
+void update_wireless_mode(_adapter *padapter);
+void update_tx_basic_rate(_adapter *padapter, u8 modulation);
+void update_sta_basic_rate(struct sta_info *psta, u8 wireless_mode);
+int rtw_ies_get_supported_rate(u8 *ies, uint ies_len, u8 *rate_set, u8 *rate_num);
+
+/* for sta/adhoc mode */
+void update_sta_info(_adapter *padapter, struct sta_info *psta);
+unsigned int update_basic_rate(unsigned char *ptn, unsigned int ptn_sz);
+unsigned int update_supported_rate(unsigned char *ptn, unsigned int ptn_sz);
+void Update_RA_Entry(_adapter *padapter, struct sta_info *psta);
+void set_sta_rate(_adapter *padapter, struct sta_info *psta);
+
+unsigned int receive_disconnect(_adapter *padapter, unsigned char *MacAddr, unsigned short reason, u8 locally_generated);
+
+unsigned char get_highest_rate_idx(u64 mask);
+unsigned char get_lowest_rate_idx_ex(u64 mask, int start_bit);
+#define get_lowest_rate_idx(mask) get_lowest_rate_idx_ex(mask, 0)
+
+int support_short_GI(_adapter *padapter, struct HT_caps_element *pHT_caps, u8 bwmode);
+unsigned int is_ap_in_tkip(_adapter *padapter);
+unsigned int is_ap_in_wep(_adapter *padapter);
+unsigned int should_forbid_n_rate(_adapter *padapter);
+
+void parsing_eapol_packet(_adapter *padapter, u8 *key_payload, struct sta_info *psta, u8 trx_type);
+
+bool _rtw_camctl_chk_cap(_adapter *adapter, u8 cap);
+void _rtw_camctl_set_flags(_adapter *adapter, u32 flags);
+void rtw_camctl_set_flags(_adapter *adapter, u32 flags);
+void _rtw_camctl_clr_flags(_adapter *adapter, u32 flags);
+void rtw_camctl_clr_flags(_adapter *adapter, u32 flags);
+bool _rtw_camctl_chk_flags(_adapter *adapter, u32 flags);
+
+struct sec_cam_bmp;
+void dump_sec_cam_map(void *sel, struct sec_cam_bmp *map, u8 max_num);
+void rtw_sec_cam_map_clr_all(struct sec_cam_bmp *map);
+
+bool _rtw_camid_is_gk(_adapter *adapter, u8 cam_id);
+bool rtw_camid_is_gk(_adapter *adapter, u8 cam_id);
+s16 rtw_camid_search(_adapter *adapter, u8 *addr, s16 kid, s8 gk);
+s16 rtw_camid_alloc(_adapter *adapter, struct sta_info *sta, u8 kid, u8 gk, bool *used);
+void rtw_camid_free(_adapter *adapter, u8 cam_id);
+u8 rtw_get_sec_camid(_adapter *adapter, u8 max_bk_key_num, u8 *sec_key_id);
+
+struct macid_bmp;
+struct macid_ctl_t;
+void dump_macid_map(void *sel, struct macid_bmp *map, u8 max_num);
+bool rtw_macid_is_set(struct macid_bmp *map, u8 id);
+void rtw_macid_map_clr(struct macid_bmp *map, u8 id);
+bool rtw_macid_is_used(struct macid_ctl_t *macid_ctl, u8 id);
+bool rtw_macid_is_bmc(struct macid_ctl_t *macid_ctl, u8 id);
+u8 rtw_macid_get_iface_bmp(struct macid_ctl_t *macid_ctl, u8 id);
+bool rtw_macid_is_iface_shared(struct macid_ctl_t *macid_ctl, u8 id);
+bool rtw_macid_is_iface_specific(struct macid_ctl_t *macid_ctl, u8 id, _adapter *adapter);
+s8 rtw_macid_get_ch_g(struct macid_ctl_t *macid_ctl, u8 id);
+void rtw_alloc_macid(_adapter *padapter, struct sta_info *psta);
+void rtw_release_macid(_adapter *padapter, struct sta_info *psta);
+u8 rtw_search_max_mac_id(_adapter *padapter);
+void rtw_macid_ctl_set_h2c_msr(struct macid_ctl_t *macid_ctl, u8 id, u8 h2c_msr);
+void rtw_macid_ctl_set_bw(struct macid_ctl_t *macid_ctl, u8 id, u8 bw);
+void rtw_macid_ctl_set_vht_en(struct macid_ctl_t *macid_ctl, u8 id, u8 en);
+void rtw_macid_ctl_set_rate_bmp0(struct macid_ctl_t *macid_ctl, u8 id, u32 bmp);
+void rtw_macid_ctl_set_rate_bmp1(struct macid_ctl_t *macid_ctl, u8 id, u32 bmp);
+void rtw_macid_ctl_init_sleep_reg(struct macid_ctl_t *macid_ctl, u16 m0, u16 m1, u16 m2, u16 m3);
+void rtw_macid_ctl_init(struct macid_ctl_t *macid_ctl);
+void rtw_macid_ctl_deinit(struct macid_ctl_t *macid_ctl);
+u8 rtw_iface_bcmc_id_get(_adapter *padapter);
+void rtw_iface_bcmc_id_set(_adapter *padapter, u8 mac_id);
+#if defined(DBG_CONFIG_ERROR_RESET) && defined(CONFIG_CONCURRENT_MODE)
+void rtw_iface_bcmc_sec_cam_map_restore(_adapter *adapter);
+#endif
+bool rtw_bmp_is_set(const u8 *bmp, u8 bmp_len, u8 id);
+void rtw_bmp_set(u8 *bmp, u8 bmp_len, u8 id);
+void rtw_bmp_clear(u8 *bmp, u8 bmp_len, u8 id);
+bool rtw_bmp_not_empty(const u8 *bmp, u8 bmp_len);
+bool rtw_bmp_not_empty_exclude_bit0(const u8 *bmp, u8 bmp_len);
+
+#ifdef CONFIG_AP_MODE
+bool rtw_tim_map_is_set(_adapter *padapter, const u8 *map, u8 id);
+void rtw_tim_map_set(_adapter *padapter, u8 *map, u8 id);
+void rtw_tim_map_clear(_adapter *padapter, u8 *map, u8 id);
+bool rtw_tim_map_anyone_be_set(_adapter *padapter, const u8 *map);
+bool rtw_tim_map_anyone_be_set_exclude_aid0(_adapter *padapter, const u8 *map);
+#endif /* CONFIG_AP_MODE */
+
+u32 report_join_res(_adapter *padapter, int aid_res, u16 status);
+void report_survey_event(_adapter *padapter, union recv_frame *precv_frame);
+void report_surveydone_event(_adapter *padapter);
+u32 report_del_sta_event(_adapter *padapter, unsigned char *MacAddr, unsigned short reason, bool enqueue, u8 locally_generated);
+void report_add_sta_event(_adapter *padapter, unsigned char *MacAddr);
+bool rtw_port_switch_chk(_adapter *adapter);
+void report_wmm_edca_update(_adapter *padapter);
+
+void beacon_timing_control(_adapter *padapter);
+u8 chk_bmc_sleepq_cmd(_adapter *padapter);
+extern u8 set_tx_beacon_cmd(_adapter *padapter);
+unsigned int setup_beacon_frame(_adapter *padapter, unsigned char *beacon_frame);
+void update_mgnt_tx_rate(_adapter *padapter, u8 rate);
+void update_monitor_frame_attrib(_adapter *padapter, struct pkt_attrib *pattrib);
+void update_mgntframe_attrib(_adapter *padapter, struct pkt_attrib *pattrib);
+void update_mgntframe_attrib_addr(_adapter *padapter, struct xmit_frame *pmgntframe);
+void dump_mgntframe(_adapter *padapter, struct xmit_frame *pmgntframe);
+s32 dump_mgntframe_and_wait(_adapter *padapter, struct xmit_frame *pmgntframe, int timeout_ms);
+s32 dump_mgntframe_and_wait_ack(_adapter *padapter, struct xmit_frame *pmgntframe);
+s32 dump_mgntframe_and_wait_ack_timeout(_adapter *padapter, struct xmit_frame *pmgntframe, int timeout_ms);
+
+#ifdef CONFIG_P2P
+int get_reg_classes_full_count(struct p2p_channels *channel_list);
+void issue_probersp_p2p(_adapter *padapter, unsigned char *da);
+void issue_p2p_provision_request(_adapter *padapter, u8 *pssid, u8 ussidlen, u8 *pdev_raddr);
+void issue_p2p_GO_request(_adapter *padapter, u8 *raddr);
+void issue_probereq_p2p(_adapter *padapter, u8 *da);
+int issue_probereq_p2p_ex(_adapter *adapter, u8 *da, int try_cnt, int wait_ms);
+void issue_p2p_invitation_response(_adapter *padapter, u8 *raddr, u8 dialogToken, u8 success);
+void issue_p2p_invitation_request(_adapter *padapter, u8 *raddr);
+#endif /* CONFIG_P2P */
+void issue_beacon(_adapter *padapter, int timeout_ms);
+void issue_probersp(_adapter *padapter, unsigned char *da, u8 is_valid_p2p_probereq);
+void _issue_assocreq(_adapter *padapter, u8 is_assoc);
+void issue_assocreq(_adapter *padapter);
+void issue_reassocreq(_adapter *padapter);
+void issue_asocrsp(_adapter *padapter, unsigned short status, struct sta_info *pstat, int pkt_type);
+void issue_auth(_adapter *padapter, struct sta_info *psta, unsigned short status);
+void issue_probereq(_adapter *padapter, const NDIS_802_11_SSID *pssid, const u8 *da);
+s32 issue_probereq_ex(_adapter *padapter, const NDIS_802_11_SSID *pssid, const u8 *da, u8 ch, bool append_wps, int try_cnt, int wait_ms);
+int issue_nulldata(_adapter *padapter, unsigned char *da, unsigned int power_mode, int try_cnt, int wait_ms);
+int issue_qos_nulldata(_adapter *padapter, unsigned char *da, u16 tid, u8 ps, int try_cnt, int wait_ms);
+int issue_deauth(_adapter *padapter, unsigned char *da, unsigned short reason);
+int issue_deauth_ex(_adapter *padapter, u8 *da, unsigned short reason, int try_cnt, int wait_ms);
+void issue_action_spct_ch_switch(_adapter *padapter, u8 *ra, u8 new_ch, u8 ch_offset);
+void issue_addba_req(_adapter *adapter, unsigned char *ra, u8 tid);
+void issue_addba_rsp(_adapter *adapter, unsigned char *ra, u8 tid, u16 status, u8 size);
+u8 issue_addba_rsp_wait_ack(_adapter *adapter, unsigned char *ra, u8 tid, u16 status, u8 size, int try_cnt, int wait_ms);
+void issue_del_ba(_adapter *adapter, unsigned char *ra, u8 tid, u16 reason, u8 initiator);
+int issue_del_ba_ex(_adapter *adapter, unsigned char *ra, u8 tid, u16 reason, u8 initiator, int try_cnt, int wait_ms);
+void issue_action_BSSCoexistPacket(_adapter *padapter);
+
+#ifdef CONFIG_IEEE80211W
+void issue_action_SA_Query(_adapter *padapter, unsigned char *raddr, unsigned char action, unsigned short tid, u8 key_type);
+int issue_deauth_11w(_adapter *padapter, unsigned char *da, unsigned short reason, u8 key_type);
+#endif /* CONFIG_IEEE80211W */
+int issue_action_SM_PS(_adapter *padapter ,  unsigned char *raddr , u8 NewMimoPsMode);
+int issue_action_SM_PS_wait_ack(_adapter *padapter, unsigned char *raddr, u8 NewMimoPsMode, int try_cnt, int wait_ms);
+
+unsigned int send_delba_sta_tid(_adapter *adapter, u8 initiator, struct sta_info *sta, u8 tid, u8 force);
+unsigned int send_delba_sta_tid_wait_ack(_adapter *adapter, u8 initiator, struct sta_info *sta, u8 tid, u8 force);
+
+unsigned int send_delba(_adapter *padapter, u8 initiator, u8 *addr);
+unsigned int send_beacon(_adapter *padapter);
+
+void start_clnt_assoc(_adapter *padapter);
+void start_clnt_auth(_adapter *padapter);
+void start_clnt_join(_adapter *padapter);
+void start_create_ibss(_adapter *padapter);
+
+unsigned int OnAssocReq(_adapter *padapter, union recv_frame *precv_frame);
+unsigned int OnAssocRsp(_adapter *padapter, union recv_frame *precv_frame);
+unsigned int OnProbeReq(_adapter *padapter, union recv_frame *precv_frame);
+unsigned int OnProbeRsp(_adapter *padapter, union recv_frame *precv_frame);
+unsigned int DoReserved(_adapter *padapter, union recv_frame *precv_frame);
+unsigned int OnBeacon(_adapter *padapter, union recv_frame *precv_frame);
+unsigned int OnAtim(_adapter *padapter, union recv_frame *precv_frame);
+unsigned int OnDisassoc(_adapter *padapter, union recv_frame *precv_frame);
+unsigned int OnAuth(_adapter *padapter, union recv_frame *precv_frame);
+unsigned int OnAuthClient(_adapter *padapter, union recv_frame *precv_frame);
+unsigned int OnDeAuth(_adapter *padapter, union recv_frame *precv_frame);
+unsigned int OnAction(_adapter *padapter, union recv_frame *precv_frame);
+
+unsigned int on_action_spct(_adapter *padapter, union recv_frame *precv_frame);
+unsigned int OnAction_qos(_adapter *padapter, union recv_frame *precv_frame);
+unsigned int OnAction_dls(_adapter *padapter, union recv_frame *precv_frame);
+#ifdef CONFIG_RTW_WNM
+unsigned int on_action_wnm(_adapter *adapter, union recv_frame *rframe);
+#endif
+
+#define RX_AMPDU_ACCEPT_INVALID 0xFF
+#define RX_AMPDU_SIZE_INVALID 0xFF
+
+enum rx_ampdu_reason {
+	RX_AMPDU_DRV_FIXED = 1,
+	RX_AMPDU_BTCOEX = 2, /* not used, because BTCOEX has its own variable management */
+	RX_AMPDU_DRV_SCAN = 3,
+};
+u8 rtw_rx_ampdu_size(_adapter *adapter);
+bool rtw_rx_ampdu_is_accept(_adapter *adapter);
+bool rtw_rx_ampdu_set_size(_adapter *adapter, u8 size, u8 reason);
+bool rtw_rx_ampdu_set_accept(_adapter *adapter, u8 accept, u8 reason);
+u8 rx_ampdu_apply_sta_tid(_adapter *adapter, struct sta_info *sta, u8 tid, u8 accept, u8 size);
+u8 rx_ampdu_size_sta_limit(_adapter *adapter, struct sta_info *sta);
+u8 rx_ampdu_apply_sta(_adapter *adapter, struct sta_info *sta, u8 accept, u8 size);
+u16 rtw_rx_ampdu_apply(_adapter *adapter);
+
+unsigned int OnAction_back(_adapter *padapter, union recv_frame *precv_frame);
+unsigned int on_action_public(_adapter *padapter, union recv_frame *precv_frame);
+unsigned int OnAction_ft(_adapter *padapter, union recv_frame *precv_frame);
+unsigned int OnAction_ht(_adapter *padapter, union recv_frame *precv_frame);
+#ifdef CONFIG_IEEE80211W
+unsigned int OnAction_sa_query(_adapter *padapter, union recv_frame *precv_frame);
+#endif /* CONFIG_IEEE80211W */
+unsigned int on_action_rm(_adapter *padapter, union recv_frame *precv_frame);
+unsigned int OnAction_wmm(_adapter *padapter, union recv_frame *precv_frame);
+unsigned int OnAction_vht(_adapter *padapter, union recv_frame *precv_frame);
+unsigned int OnAction_p2p(_adapter *padapter, union recv_frame *precv_frame);
+
+#ifdef CONFIG_RTW_80211R
+void rtw_ft_update_bcn(_adapter *padapter, union recv_frame *precv_frame);
+void rtw_ft_start_clnt_join(_adapter *padapter);
+u8 rtw_ft_update_rsnie(_adapter *padapter, u8 bwrite, 
+	struct pkt_attrib *pattrib, u8 **pframe);
+void rtw_ft_build_auth_req_ies(_adapter *padapter, 
+	struct pkt_attrib *pattrib, u8 **pframe);
+void rtw_ft_build_assoc_req_ies(_adapter *padapter, 
+	u8 is_reassoc, struct pkt_attrib *pattrib, u8 **pframe);
+u8 rtw_ft_update_auth_rsp_ies(_adapter *padapter, u8 *pframe, u32 len);
+void rtw_ft_start_roam(_adapter *padapter, u8 *pTargetAddr);
+void rtw_ft_issue_action_req(_adapter *padapter, u8 *pTargetAddr);
+void rtw_ft_report_evt(_adapter *padapter);
+void rtw_ft_report_reassoc_evt(_adapter *padapter, u8 *pMacAddr);
+void rtw_ft_link_timer_hdl(void *ctx);
+void rtw_ft_roam_timer_hdl(void *ctx);
+void rtw_ft_roam_status_reset(_adapter *padapter);
+#endif
+#ifdef CONFIG_RTW_WNM
+void rtw_wnm_roam_scan_hdl(void *ctx);
+void rtw_wnm_process_btm_req(_adapter *padapter,  u8* pframe, u32 frame_len);
+void rtw_wnm_reset_btm_candidate(struct roam_nb_info *pnb);
+void rtw_wnm_reset_btm_state(_adapter *padapter);
+void rtw_wnm_issue_action(_adapter *padapter, u8 action, u8 reason);
+#endif
+#if defined(CONFIG_RTW_WNM) || defined(CONFIG_RTW_80211K)
+u32 rtw_wnm_btm_candidates_survey(_adapter *padapter, u8* pframe, u32 elem_len, u8 is_preference);
+#endif
+void mlmeext_joinbss_event_callback(_adapter *padapter, int join_res);
+void mlmeext_sta_del_event_callback(_adapter *padapter);
+void mlmeext_sta_add_event_callback(_adapter *padapter, struct sta_info *psta);
+
+void linked_status_chk(_adapter *padapter, u8 from_timer);
+
+#define rtw_get_bcn_cnt(adapter)	(adapter->mlmeextpriv.cur_bcn_cnt)
+void rtw_collect_bcn_info(_adapter *adapter);
+
+void _linked_info_dump(_adapter *padapter);
+
+void survey_timer_hdl(void *ctx);
+#ifdef CONFIG_RTW_REPEATER_SON
+void rson_timer_hdl(void *ctx);
+#endif
+void link_timer_hdl(void *ctx);
+void addba_timer_hdl(void *ctx);
+#ifdef CONFIG_IEEE80211W
+void sa_query_timer_hdl(void *ctx);
+#endif /* CONFIG_IEEE80211W */
+#if 0
+void reauth_timer_hdl(_adapter *padapter);
+void reassoc_timer_hdl(_adapter *padapter);
+#endif
+
+#define set_survey_timer(mlmeext, ms) \
+	do { \
+		/*RTW_INFO("%s set_survey_timer(%p, %d)\n", __FUNCTION__, (mlmeext), (ms));*/ \
+		_set_timer(&(mlmeext)->survey_timer, (ms)); \
+	} while (0)
+
+#define set_link_timer(mlmeext, ms) \
+	do { \
+		/*RTW_INFO("%s set_link_timer(%p, %d)\n", __FUNCTION__, (mlmeext), (ms));*/ \
+		_set_timer(&(mlmeext)->link_timer, (ms)); \
+	} while (0)
+
+bool rtw_is_basic_rate_cck(u8 rate);
+bool rtw_is_basic_rate_ofdm(u8 rate);
+bool rtw_is_basic_rate_mix(u8 rate);
+
+extern int cckrates_included(unsigned char *rate, int ratelen);
+extern int cckratesonly_included(unsigned char *rate, int ratelen);
+
+extern void process_addba_req(_adapter *padapter, u8 *paddba_req, u8 *addr);
+
+extern void update_TSF(struct mlme_ext_priv *pmlmeext, u8 *pframe, uint len);
+extern void correct_TSF(_adapter *padapter, u8 mlme_state);
+#ifdef CONFIG_BCN_RECV_TIME
+void rtw_rx_bcn_time_update(_adapter *adapter, uint bcn_len, u8 data_rate);
+#endif
+extern u8 traffic_status_watchdog(_adapter *padapter, u8 from_timer);
+
+void rtw_process_bar_frame(_adapter *padapter, union recv_frame *precv_frame);
+void rtw_join_done_chk_ch(_adapter *padapter, int join_res);
+
+int rtw_chk_start_clnt_join(_adapter *padapter, u8 *ch, u8 *bw, u8 *offset);
+
+#ifdef CONFIG_PLATFORM_ARM_SUN8I
+	#define BUSY_TRAFFIC_SCAN_DENY_PERIOD	8000
+#else
+	#define BUSY_TRAFFIC_SCAN_DENY_PERIOD	12000
+#endif
+
+struct cmd_hdl {
+	uint	parmsize;
+	u8(*h2cfuns)(struct _ADAPTER *padapter, u8 *pbuf);
+};
+
+void rtw_leave_opch(_adapter *adapter);
+void rtw_back_opch(_adapter *adapter);
+
+u8 read_macreg_hdl(_adapter *padapter, u8 *pbuf);
+u8 write_macreg_hdl(_adapter *padapter, u8 *pbuf);
+u8 read_bbreg_hdl(_adapter *padapter, u8 *pbuf);
+u8 write_bbreg_hdl(_adapter *padapter, u8 *pbuf);
+u8 read_rfreg_hdl(_adapter *padapter, u8 *pbuf);
+u8 write_rfreg_hdl(_adapter *padapter, u8 *pbuf);
+
+
+u8 NULL_hdl(_adapter *padapter, u8 *pbuf);
+u8 join_cmd_hdl(_adapter *padapter, u8 *pbuf);
+u8 disconnect_hdl(_adapter *padapter, u8 *pbuf);
+u8 createbss_hdl(_adapter *padapter, u8 *pbuf);
+u8 setopmode_hdl(_adapter *padapter, u8 *pbuf);
+u8 sitesurvey_cmd_hdl(_adapter *padapter, u8 *pbuf);
+u8 setauth_hdl(_adapter *padapter, u8 *pbuf);
+u8 setkey_hdl(_adapter *padapter, u8 *pbuf);
+u8 set_stakey_hdl(_adapter *padapter, u8 *pbuf);
+u8 set_assocsta_hdl(_adapter *padapter, u8 *pbuf);
+u8 del_assocsta_hdl(_adapter *padapter, u8 *pbuf);
+u8 add_ba_hdl(_adapter *padapter, unsigned char *pbuf);
+u8 add_ba_rsp_hdl(_adapter *padapter, unsigned char *pbuf);
+
+void rtw_ap_wep_pk_setting(_adapter *adapter, struct sta_info *psta);
+
+u8 mlme_evt_hdl(_adapter *padapter, unsigned char *pbuf);
+u8 h2c_msg_hdl(_adapter *padapter, unsigned char *pbuf);
+u8 chk_bmc_sleepq_hdl(_adapter *padapter, unsigned char *pbuf);
+u8 tx_beacon_hdl(_adapter *padapter, unsigned char *pbuf);
+u8 rtw_set_chbw_hdl(_adapter *padapter, u8 *pbuf);
+u8 set_chplan_hdl(_adapter *padapter, unsigned char *pbuf);
+u8 led_blink_hdl(_adapter *padapter, unsigned char *pbuf);
+u8 set_csa_hdl(_adapter *padapter, unsigned char *pbuf);	/* Kurt: Handling DFS channel switch announcement ie. */
+u8 tdls_hdl(_adapter *padapter, unsigned char *pbuf);
+u8 run_in_thread_hdl(_adapter *padapter, u8 *pbuf);
+u8 rtw_getmacreg_hdl(_adapter *padapter, u8 *pbuf);
+
+#define GEN_DRV_CMD_HANDLER(size, cmd)	{size, &cmd ## _hdl},
+#define GEN_MLME_EXT_HANDLER(size, cmd)	{size, cmd},
+
+#ifdef _RTW_CMD_C_
+
+struct cmd_hdl wlancmds[] = {
+	GEN_DRV_CMD_HANDLER(sizeof(struct readMAC_parm), rtw_getmacreg) /*0*/
+	GEN_DRV_CMD_HANDLER(0, NULL)
+	GEN_DRV_CMD_HANDLER(0, NULL)
+	GEN_DRV_CMD_HANDLER(0, NULL)
+	GEN_DRV_CMD_HANDLER(0, NULL)
+	GEN_DRV_CMD_HANDLER(0, NULL)
+	GEN_MLME_EXT_HANDLER(0, NULL)
+	GEN_MLME_EXT_HANDLER(0, NULL)
+	GEN_MLME_EXT_HANDLER(0, NULL)
+	GEN_MLME_EXT_HANDLER(0, NULL)
+	GEN_MLME_EXT_HANDLER(0, NULL) /*10*/
+	GEN_MLME_EXT_HANDLER(0, NULL)
+	GEN_MLME_EXT_HANDLER(0, NULL)
+	GEN_MLME_EXT_HANDLER(0, NULL)
+	GEN_MLME_EXT_HANDLER(sizeof(struct joinbss_parm), join_cmd_hdl)  /*14*/
+	GEN_MLME_EXT_HANDLER(sizeof(struct disconnect_parm), disconnect_hdl)
+	GEN_MLME_EXT_HANDLER(sizeof(struct createbss_parm), createbss_hdl)
+	GEN_MLME_EXT_HANDLER(sizeof(struct setopmode_parm), setopmode_hdl)
+	GEN_MLME_EXT_HANDLER(sizeof(struct sitesurvey_parm), sitesurvey_cmd_hdl)  /*18*/
+	GEN_MLME_EXT_HANDLER(sizeof(struct setauth_parm), setauth_hdl)
+	GEN_MLME_EXT_HANDLER(sizeof(struct setkey_parm), setkey_hdl)  /*20*/
+	GEN_MLME_EXT_HANDLER(sizeof(struct set_stakey_parm), set_stakey_hdl)
+	GEN_MLME_EXT_HANDLER(sizeof(struct set_assocsta_parm), NULL)
+	GEN_MLME_EXT_HANDLER(sizeof(struct del_assocsta_parm), NULL)
+	GEN_MLME_EXT_HANDLER(sizeof(struct setstapwrstate_parm), NULL)
+	GEN_MLME_EXT_HANDLER(sizeof(struct setbasicrate_parm), NULL)
+	GEN_MLME_EXT_HANDLER(sizeof(struct getbasicrate_parm), NULL)
+	GEN_MLME_EXT_HANDLER(sizeof(struct setdatarate_parm), NULL)
+	GEN_MLME_EXT_HANDLER(sizeof(struct getdatarate_parm), NULL)
+	GEN_MLME_EXT_HANDLER(0, NULL)
+	GEN_MLME_EXT_HANDLER(0, NULL)   /*30*/
+	GEN_MLME_EXT_HANDLER(sizeof(struct setphy_parm), NULL)
+	GEN_MLME_EXT_HANDLER(sizeof(struct getphy_parm), NULL)
+	GEN_MLME_EXT_HANDLER(0, NULL)
+	GEN_MLME_EXT_HANDLER(0, NULL)
+	GEN_MLME_EXT_HANDLER(0, NULL)
+	GEN_MLME_EXT_HANDLER(0, NULL)
+	GEN_MLME_EXT_HANDLER(0, NULL)
+	GEN_MLME_EXT_HANDLER(0, NULL)
+	GEN_MLME_EXT_HANDLER(0, NULL)
+	GEN_MLME_EXT_HANDLER(0, NULL)	/*40*/
+	GEN_MLME_EXT_HANDLER(0, NULL)
+	GEN_MLME_EXT_HANDLER(0, NULL)
+	GEN_MLME_EXT_HANDLER(0, NULL)
+	GEN_MLME_EXT_HANDLER(0, NULL)
+	GEN_MLME_EXT_HANDLER(sizeof(struct addBaReq_parm), add_ba_hdl)
+	GEN_MLME_EXT_HANDLER(sizeof(struct set_ch_parm), rtw_set_chbw_hdl) /* 46 */
+	GEN_MLME_EXT_HANDLER(0, NULL)
+	GEN_MLME_EXT_HANDLER(0, NULL)
+	GEN_MLME_EXT_HANDLER(0, NULL)
+	GEN_MLME_EXT_HANDLER(0, NULL) /*50*/
+	GEN_MLME_EXT_HANDLER(0, NULL)
+	GEN_MLME_EXT_HANDLER(0, NULL)
+	GEN_MLME_EXT_HANDLER(0, NULL)
+	GEN_MLME_EXT_HANDLER(0, NULL)
+	GEN_MLME_EXT_HANDLER(sizeof(struct Tx_Beacon_param), tx_beacon_hdl) /*55*/
+
+	GEN_MLME_EXT_HANDLER(0, mlme_evt_hdl) /*56*/
+	GEN_MLME_EXT_HANDLER(0, rtw_drvextra_cmd_hdl) /*57*/
+
+	GEN_MLME_EXT_HANDLER(0, h2c_msg_hdl) /*58*/
+	GEN_MLME_EXT_HANDLER(sizeof(struct SetChannelPlan_param), set_chplan_hdl) /*59*/
+	GEN_MLME_EXT_HANDLER(sizeof(struct LedBlink_param), led_blink_hdl) /*60*/
+
+	GEN_MLME_EXT_HANDLER(0, set_csa_hdl) /*61*/
+	GEN_MLME_EXT_HANDLER(sizeof(struct TDLSoption_param), tdls_hdl) /*62*/
+	GEN_MLME_EXT_HANDLER(0, chk_bmc_sleepq_hdl) /*63*/
+	GEN_MLME_EXT_HANDLER(sizeof(struct RunInThread_param), run_in_thread_hdl) /*64*/
+	GEN_MLME_EXT_HANDLER(sizeof(struct addBaRsp_parm), add_ba_rsp_hdl) /* 65 */
+	GEN_MLME_EXT_HANDLER(sizeof(struct rm_event), rm_post_event_hdl) /* 66 */
+};
+
+#endif
+
+struct C2HEvent_Header {
+
+#ifdef CONFIG_LITTLE_ENDIAN
+
+	unsigned int len:16;
+	unsigned int ID:8;
+	unsigned int seq:8;
+
+#elif defined(CONFIG_BIG_ENDIAN)
+
+	unsigned int seq:8;
+	unsigned int ID:8;
+	unsigned int len:16;
+
+#else
+
+#  error "Must be LITTLE or BIG Endian"
+
+#endif
+
+	unsigned int rsvd;
+
+};
+
+void rtw_dummy_event_callback(_adapter *adapter , u8 *pbuf);
+void rtw_fwdbg_event_callback(_adapter *adapter , u8 *pbuf);
+
+enum rtw_c2h_event {
+	GEN_EVT_CODE(_Read_MACREG) = 0, /*0*/
+	GEN_EVT_CODE(_Read_BBREG),
+	GEN_EVT_CODE(_Read_RFREG),
+	GEN_EVT_CODE(_Read_EEPROM),
+	GEN_EVT_CODE(_Read_EFUSE),
+	GEN_EVT_CODE(_Read_CAM),			/*5*/
+	GEN_EVT_CODE(_Get_BasicRate),
+	GEN_EVT_CODE(_Get_DataRate),
+	GEN_EVT_CODE(_Survey),	 /*8*/
+	GEN_EVT_CODE(_SurveyDone),	 /*9*/
+
+	GEN_EVT_CODE(_JoinBss) , /*10*/
+	GEN_EVT_CODE(_AddSTA),
+	GEN_EVT_CODE(_DelSTA),
+	GEN_EVT_CODE(_AtimDone) ,
+	GEN_EVT_CODE(_TX_Report),
+	GEN_EVT_CODE(_CCX_Report),			/*15*/
+	GEN_EVT_CODE(_DTM_Report),
+	GEN_EVT_CODE(_TX_Rate_Statistics),
+	GEN_EVT_CODE(_C2HLBK),
+	GEN_EVT_CODE(_FWDBG),
+	GEN_EVT_CODE(_C2HFEEDBACK),               /*20*/
+	GEN_EVT_CODE(_ADDBA),
+	GEN_EVT_CODE(_C2HBCN),
+	GEN_EVT_CODE(_ReportPwrState),		/* filen: only for PCIE, USB	 */
+	GEN_EVT_CODE(_CloseRF),				/* filen: only for PCIE, work around ASPM */
+	GEN_EVT_CODE(_WMM),					/*25*/
+#ifdef CONFIG_IEEE80211W
+	GEN_EVT_CODE(_TimeoutSTA),
+#endif /* CONFIG_IEEE80211W */
+#ifdef CONFIG_RTW_80211R
+	GEN_EVT_CODE(_FT_REASSOC),
+#endif
+	MAX_C2HEVT
+};
+
+
+#ifdef _RTW_MLME_EXT_C_
+
+static struct fwevent wlanevents[] = {
+	{0, rtw_dummy_event_callback},	/*0*/
+	{0, NULL},
+	{0, NULL},
+	{0, NULL},
+	{0, NULL},
+	{0, NULL},
+	{0, NULL},
+	{0, NULL},
+	{0, &rtw_survey_event_callback},		/*8*/
+	{sizeof(struct surveydone_event), &rtw_surveydone_event_callback},	/*9*/
+
+	{0, &rtw_joinbss_event_callback},		/*10*/
+	{sizeof(struct stassoc_event), &rtw_stassoc_event_callback},
+	{sizeof(struct stadel_event), &rtw_stadel_event_callback},
+	{0, &rtw_atimdone_event_callback},
+	{0, rtw_dummy_event_callback},
+	{0, NULL},	/*15*/
+	{0, NULL},
+	{0, NULL},
+	{0, NULL},
+	{0, rtw_fwdbg_event_callback},
+	{0, NULL},	 /*20*/
+	{0, NULL},
+	{0, NULL},
+	{0, &rtw_cpwm_event_callback},
+	{0, NULL},
+	{0, &rtw_wmm_event_callback}, /*25*/
+#ifdef CONFIG_IEEE80211W
+	{sizeof(struct stadel_event), &rtw_sta_timeout_event_callback},
+#endif /* CONFIG_IEEE80211W */
+#ifdef CONFIG_RTW_80211R
+	{sizeof(struct stassoc_event), &rtw_ft_reassoc_event_callback},
+#endif
+};
+
+#endif/* _RTW_MLME_EXT_C_ */
+
+#endif
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/include/rtw_mlme.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/rtw_mlme.h
--- linux-5.6.3/3rdparty/rtl8821ce/include/rtw_mlme.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/rtw_mlme.h	2020-04-10 16:35:06.851661701 +0300
@@ -0,0 +1,1421 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#ifndef __RTW_MLME_H_
+#define __RTW_MLME_H_
+
+
+#define	MAX_BSS_CNT	128
+/* #define   MAX_JOIN_TIMEOUT	2000 */
+/* #define   MAX_JOIN_TIMEOUT	2500 */
+#define   MAX_JOIN_TIMEOUT	6500
+
+/*	Commented by Albert 20101105
+ *	Increase the scanning timeout because of increasing the SURVEY_TO value. */
+
+
+#ifdef PALTFORM_OS_WINCE
+#define	SCANQUEUE_LIFETIME 12000000 /* unit:us */
+#else
+#define	SCANQUEUE_LIFETIME 20000 /* 20sec, unit:msec */
+#endif
+
+#define WIFI_NULL_STATE					0x00000000
+#define WIFI_ASOC_STATE					0x00000001 /* Linked */
+#define WIFI_REASOC_STATE				0x00000002
+#define WIFI_SLEEP_STATE				0x00000004
+#define WIFI_STATION_STATE				0x00000008
+#define WIFI_AP_STATE					0x00000010
+#define WIFI_ADHOC_STATE				0x00000020
+#define WIFI_ADHOC_MASTER_STATE			0x00000040
+#define WIFI_UNDER_LINKING				0x00000080
+#define WIFI_UNDER_WPS					0x00000100
+#define WIFI_MESH_STATE					0x00000200
+#define WIFI_STA_ALIVE_CHK_STATE		0x00000400
+#define WIFI_SITE_MONITOR				0x00000800 /* under site surveying */
+#define WIFI_WDS						0x00001000
+#define WIFI_WDS_RX_BEACON				0x00002000 /* already rx WDS AP beacon */
+#define WIFI_AUTOCONF					0x00004000
+#define WIFI_AUTOCONF_IND				0x00008000
+#define WIFI_MP_STATE					0x00010000
+#define WIFI_MP_CTX_BACKGROUND			0x00020000 /* in continuous tx background */
+#define WIFI_MP_CTX_ST					0x00040000 /* in continuous tx with single-tone */
+#define WIFI_MP_CTX_BACKGROUND_PENDING	0x00080000 /* pending in continuous tx background due to out of skb */
+#define WIFI_MP_CTX_CCK_HW				0x00100000 /* in continuous tx */
+#define WIFI_MP_CTX_CCK_CS				0x00200000 /* in continuous tx with carrier suppression */
+#define WIFI_MP_LPBK_STATE				0x00400000
+#define WIFI_OP_CH_SWITCHING			0x00800000
+#define WIFI_UNDER_KEY_HANDSHAKE	0x01000000
+/*#define WIFI_UNDEFINED_STATE			0x02000000*/
+/*#define WIFI_UNDEFINED_STATE			0x04000000*/
+/*#define WIFI_UNDEFINED_STATE			0x08000000*/
+/*#define WIFI_UNDEFINED_STATE			0x10000000*/
+/*#define WIFI_UNDEFINED_STATE			0x20000000*/
+/*#define WIFI_UNDEFINED_STATE			0x40000000*/
+#define WIFI_MONITOR_STATE				0x80000000
+
+#define MIRACAST_DISABLED	0
+#define MIRACAST_SOURCE		BIT0
+#define MIRACAST_SINK		BIT1
+
+#define MIRACAST_MODE_REVERSE(mode) \
+	((((mode) & MIRACAST_SOURCE) ? MIRACAST_SINK : 0) | (((mode) & MIRACAST_SINK) ? MIRACAST_SOURCE : 0))
+
+bool is_miracast_enabled(_adapter *adapter);
+bool rtw_chk_miracast_mode(_adapter *adapter, u8 mode);
+const char *get_miracast_mode_str(int mode);
+void rtw_wfd_st_switch(struct sta_info *sta, bool on);
+
+#define MLME_STATE(adapter) get_fwstate(&((adapter)->mlmepriv))
+#define CHK_MLME_STATE(adapter, state) check_fwstate(&((adapter)->mlmepriv), (state))
+
+#define MLME_IS_NULL(adapter) CHK_MLME_STATE(adapter, WIFI_NULL_STATE)
+#define MLME_IS_STA(adapter) CHK_MLME_STATE(adapter, WIFI_STATION_STATE)
+#define MLME_IS_AP(adapter) CHK_MLME_STATE(adapter, WIFI_AP_STATE)
+#define MLME_IS_ADHOC(adapter) CHK_MLME_STATE(adapter, WIFI_ADHOC_STATE)
+#define MLME_IS_ADHOC_MASTER(adapter) CHK_MLME_STATE(adapter, WIFI_ADHOC_MASTER_STATE)
+#define MLME_IS_MESH(adapter) CHK_MLME_STATE(adapter, WIFI_MESH_STATE)
+#define MLME_IS_MONITOR(adapter) CHK_MLME_STATE(adapter, WIFI_MONITOR_STATE)
+#define MLME_IS_MP(adapter) CHK_MLME_STATE(adapter, WIFI_MP_STATE)
+#ifdef CONFIG_P2P
+	#define MLME_IS_PD(adapter) rtw_p2p_chk_role(&(adapter)->wdinfo, P2P_ROLE_DEVICE)
+	#define MLME_IS_GC(adapter) rtw_p2p_chk_role(&(adapter)->wdinfo, P2P_ROLE_CLIENT)
+	#define MLME_IS_GO(adapter) rtw_p2p_chk_role(&(adapter)->wdinfo, P2P_ROLE_GO)
+#else /* !CONFIG_P2P */
+	#define MLME_IS_PD(adapter) 0
+	#define MLME_IS_GC(adapter) 0
+	#define MLME_IS_GO(adapter) 0
+#endif /* !CONFIG_P2P */
+
+#define MLME_IS_MSRC(adapter) rtw_chk_miracast_mode((adapter), MIRACAST_SOURCE)
+#define MLME_IS_MSINK(adapter) rtw_chk_miracast_mode((adapter), MIRACAST_SINK)
+
+#define MLME_IS_SCAN(adapter) CHK_MLME_STATE(adapter, WIFI_SITE_MONITOR)
+#define MLME_IS_LINKING(adapter) CHK_MLME_STATE(adapter, WIFI_UNDER_LINKING)
+#define MLME_IS_ASOC(adapter) CHK_MLME_STATE(adapter, WIFI_ASOC_STATE)
+#define MLME_IS_OPCH_SW(adapter) CHK_MLME_STATE(adapter, WIFI_OP_CH_SWITCHING)
+#define MLME_IS_WPS(adapter) CHK_MLME_STATE(adapter, WIFI_UNDER_WPS)
+
+#if defined(CONFIG_IOCTL_CFG80211) && defined(CONFIG_P2P)
+#define MLME_IS_ROCH(adapter) (rtw_cfg80211_get_is_roch(adapter) == _TRUE)
+#else
+#define MLME_IS_ROCH(adapter) 0
+#endif
+
+#ifdef CONFIG_IOCTL_CFG80211
+#define MLME_IS_MGMT_TX(adapter) rtw_cfg80211_get_is_mgmt_tx(adapter)
+#else
+#define MLME_IS_MGMT_TX(adapter) 0
+#endif
+
+#define MLME_STATE_FMT "%s%s%s%s%s%s%s%s%s%s%s%s"
+#define MLME_STATE_ARG(adapter) \
+	MLME_IS_STA((adapter)) ? (MLME_IS_GC((adapter)) ? " GC" : " STA") : \
+	MLME_IS_AP((adapter)) ? (MLME_IS_GO((adapter)) ? " GO" : " AP") : \
+	MLME_IS_ADHOC((adapter)) ? " ADHOC" : \
+	MLME_IS_ADHOC_MASTER((adapter)) ? " ADHOC_M" : \
+	MLME_IS_MESH((adapter)) ? " MESH" : \
+	MLME_IS_MONITOR((adapter)) ? " MONITOR" : \
+	MLME_IS_MP((adapter)) ? " MP" : "", \
+	MLME_IS_PD((adapter)) ? " PD" : "", \
+	MLME_IS_MSRC((adapter)) ? " MSRC" : "", \
+	MLME_IS_MSINK((adapter)) ? " MSINK" : "", \
+	MLME_IS_SCAN((adapter)) ? " SCAN" : "", \
+	MLME_IS_LINKING((adapter)) ? " LINKING" : "", \
+	MLME_IS_ASOC((adapter)) ? " ASOC" : "", \
+	MLME_IS_OPCH_SW((adapter)) ? " OPCH_SW" : "", \
+	MLME_IS_WPS((adapter)) ? " WPS" : "", \
+	MLME_IS_ROCH((adapter)) ? " ROCH" : "", \
+	MLME_IS_MGMT_TX((adapter)) ? " MGMT_TX" : "", \
+	(MLME_STATE((adapter)) & WIFI_SLEEP_STATE) ? " SLEEP" : ""
+
+enum {
+	MLME_ACTION_UNKNOWN,
+	MLME_ACTION_NONE,
+	MLME_SCAN_ENABLE, /* WIFI_SITE_MONITOR */
+	MLME_SCAN_ENTER, /* WIFI_SITE_MONITOR && !SCAN_DISABLE && !SCAN_BACK_OP */
+	MLME_SCAN_DONE, /*  WIFI_SITE_MONITOR && (SCAN_DISABLE || SCAN_BACK_OP) */
+	MLME_SCAN_DISABLE, /* WIFI_SITE_MONITOR is going to be cleared */
+	MLME_STA_CONNECTING,
+	MLME_STA_CONNECTED,
+	MLME_STA_DISCONNECTED,
+	MLME_TDLS_LINKED,
+	MLME_TDLS_NOLINK,
+	MLME_AP_STARTED,
+	MLME_AP_STOPPED,
+	MLME_ADHOC_STARTED,
+	MLME_ADHOC_STOPPED,
+	MLME_MESH_STARTED,
+	MLME_MESH_STOPPED,
+	MLME_OPCH_SWITCH,
+};
+
+#define _FW_UNDER_LINKING	WIFI_UNDER_LINKING
+#define _FW_LINKED			WIFI_ASOC_STATE
+#define _FW_UNDER_SURVEY	WIFI_SITE_MONITOR
+
+
+enum dot11AuthAlgrthmNum {
+	dot11AuthAlgrthm_Open = 0,
+	dot11AuthAlgrthm_Shared,
+	dot11AuthAlgrthm_8021X,
+	dot11AuthAlgrthm_Auto,
+	dot11AuthAlgrthm_WAPI,
+	dot11AuthAlgrthm_MaxNum
+};
+
+/* Scan type including active and passive scan. */
+typedef enum _RT_SCAN_TYPE {
+	SCAN_PASSIVE,
+	SCAN_ACTIVE,
+	SCAN_MIX,
+} RT_SCAN_TYPE, *PRT_SCAN_TYPE;
+
+#define WIFI_FREQUENCY_BAND_AUTO 0
+#define WIFI_FREQUENCY_BAND_5GHZ 1
+#define WIFI_FREQUENCY_BAND_2GHZ 2
+
+#define rtw_band_valid(band) ((band) <= WIFI_FREQUENCY_BAND_2GHZ)
+
+enum DriverInterface {
+	DRIVER_WEXT =  1,
+	DRIVER_CFG80211 = 2
+};
+
+enum SCAN_RESULT_TYPE {
+	SCAN_RESULT_P2P_ONLY = 0,		/*	Will return all the P2P devices. */
+	SCAN_RESULT_ALL = 1,			/*	Will return all the scanned device, include AP. */
+	SCAN_RESULT_WFD_TYPE = 2		/*	Will just return the correct WFD device. */
+									/*	If this device is Miracast sink device, it will just return all the Miracast source devices. */
+};
+
+/*
+
+there are several "locks" in mlme_priv,
+since mlme_priv is a shared resource between many threads,
+like ISR/Call-Back functions, the OID handlers, and even timer functions.
+
+
+Each _queue has its own locks, already.
+Other items are protected by mlme_priv.lock.
+
+To avoid possible dead lock, any thread trying to modifiying mlme_priv
+SHALL not lock up more than one locks at a time!
+
+*/
+
+
+#define traffic_threshold	10
+#define	traffic_scan_period	500
+
+typedef struct _RT_LINK_DETECT_T {
+	u32				NumTxOkInPeriod;
+	u32				NumRxOkInPeriod;
+	u32				NumRxUnicastOkInPeriod;
+	BOOLEAN			bBusyTraffic;
+	BOOLEAN			bTxBusyTraffic;
+	BOOLEAN			bRxBusyTraffic;
+	BOOLEAN			bHigherBusyTraffic; /* For interrupt migration purpose. */
+	BOOLEAN			bHigherBusyRxTraffic; /* We may disable Tx interrupt according as Rx traffic. */
+	BOOLEAN			bHigherBusyTxTraffic; /* We may disable Tx interrupt according as Tx traffic. */
+	/* u8 TrafficBusyState; */
+	u8 TrafficTransitionCount;
+	u32 LowPowerTransitionCount;
+} RT_LINK_DETECT_T, *PRT_LINK_DETECT_T;
+
+struct profile_info {
+	u8	ssidlen;
+	u8	ssid[WLAN_SSID_MAXLEN];
+	u8	peermac[ETH_ALEN];
+};
+
+struct tx_invite_req_info {
+	u8					token;
+	u8					benable;
+	u8					go_ssid[WLAN_SSID_MAXLEN];
+	u8					ssidlen;
+	u8					go_bssid[ETH_ALEN];
+	u8					peer_macaddr[ETH_ALEN];
+	u8					operating_ch;	/*	This information will be set by using the p2p_set op_ch=x */
+	u8					peer_ch;		/*	The listen channel for peer P2P device */
+
+};
+
+struct tx_invite_resp_info {
+	u8					token;	/*	Used to record the dialog token of p2p invitation request frame. */
+};
+
+#ifdef CONFIG_WFD
+
+struct wifi_display_info {
+	u16							wfd_enable;			/*	Eanble/Disable the WFD function. */
+	u16							init_rtsp_ctrlport;	/* init value of rtsp_ctrlport when WFD enable */
+	u16							rtsp_ctrlport;		/* TCP port number at which the this WFD device listens for RTSP messages, 0 when WFD disable */
+	u16							tdls_rtsp_ctrlport;	/* rtsp_ctrlport used by tdls, will sync when rtsp_ctrlport is changed by user */
+	u16							peer_rtsp_ctrlport;	/*	TCP port number at which the peer WFD device listens for RTSP messages */
+													/*	This filed should be filled when receiving the gropu negotiation request */
+
+	u8							peer_session_avail;	/*	WFD session is available or not for the peer wfd device. */
+													/*	This variable will be set when sending the provisioning discovery request to peer WFD device. */
+													/*	And this variable will be reset when it is read by using the iwpriv p2p_get wfd_sa command. */
+	u8							ip_address[4];
+	u8							peer_ip_address[4];
+	u8							wfd_pc;				/*	WFD preferred connection */
+													/*	0 -> Prefer to use the P2P for WFD connection on peer side. */
+													/*	1 -> Prefer to use the TDLS for WFD connection on peer side. */
+
+	u8							wfd_device_type;	/*	WFD Device Type */
+													/*	0 -> WFD Source Device */
+													/*	1 -> WFD Primary Sink Device */
+	enum	SCAN_RESULT_TYPE	scan_result_type;	/*	Used when P2P is enable. This parameter will impact the scan result. */
+	u8 op_wfd_mode;
+	u8 stack_wfd_mode;
+};
+#endif /* CONFIG_WFD */
+
+struct tx_provdisc_req_info {
+	u16					wps_config_method_request;	/*	Used when sending the provisioning request frame */
+	u16					peer_channel_num[2];		/*	The channel number which the receiver stands. */
+	NDIS_802_11_SSID	ssid;
+	u8					peerDevAddr[ETH_ALEN];		/*	Peer device address */
+	u8					peerIFAddr[ETH_ALEN];		/*	Peer interface address */
+	u8					benable;					/*	This provision discovery request frame is trigger to send or not */
+};
+
+struct rx_provdisc_req_info {	/* When peer device issue prov_disc_req first, we should store the following informations */
+	u8					peerDevAddr[ETH_ALEN];		/*	Peer device address */
+	u8					strconfig_method_desc_of_prov_disc_req[4];	/*	description for the config method located in the provisioning discovery request frame.	 */
+																	/*	The UI must know this information to know which config method the remote p2p device is requiring. */
+};
+
+struct tx_nego_req_info {
+	u16					peer_channel_num[2];		/*	The channel number which the receiver stands. */
+	u8					peerDevAddr[ETH_ALEN];		/*	Peer device address */
+	u8					benable;					/*	This negoitation request frame is trigger to send or not */
+	u8					peer_ch;					/*	The listen channel for peer P2P device */
+};
+
+struct group_id_info {
+	u8					go_device_addr[ETH_ALEN];	/*	The GO's device address of this P2P group */
+	u8					ssid[WLAN_SSID_MAXLEN];		/*	The SSID of this P2P group */
+};
+
+struct scan_limit_info {
+	u8					scan_op_ch_only;			/*	When this flag is set, the driver should just scan the operation channel */
+#ifndef CONFIG_P2P_OP_CHK_SOCIAL_CH
+	u8					operation_ch[2];				/*	Store the operation channel of invitation request frame */
+#else
+	u8					operation_ch[5];				/*	Store additional channel 1,6,11  for Android 4.2 IOT & Nexus 4 */
+#endif /* CONFIG_P2P_OP_CHK_SOCIAL_CH */
+};
+
+#ifdef CONFIG_IOCTL_CFG80211
+struct cfg80211_wifidirect_info {
+	_timer					remain_on_ch_timer;
+	u8						restore_channel;
+	struct ieee80211_channel	remain_on_ch_channel;
+	enum nl80211_channel_type	remain_on_ch_type;
+	ATOMIC_T ro_ch_cookie_gen;
+	u64 remain_on_ch_cookie;
+	bool is_ro_ch;
+	struct wireless_dev *ro_ch_wdev;
+	systime last_ro_ch_time; /* this will be updated at the beginning and end of ro_ch */
+};
+#endif /* CONFIG_IOCTL_CFG80211 */
+
+#ifdef CONFIG_P2P_WOWLAN
+
+enum P2P_WOWLAN_RECV_FRAME_TYPE {
+	P2P_WOWLAN_RECV_NEGO_REQ = 0,
+	P2P_WOWLAN_RECV_INVITE_REQ = 1,
+	P2P_WOWLAN_RECV_PROVISION_REQ = 2,
+};
+
+struct p2p_wowlan_info {
+
+	u8						is_trigger;
+	enum P2P_WOWLAN_RECV_FRAME_TYPE	wowlan_recv_frame_type;
+	u8						wowlan_peer_addr[ETH_ALEN];
+	u16						wowlan_peer_wpsconfig;
+	u8						wowlan_peer_is_persistent;
+	u8						wowlan_peer_invitation_type;
+};
+
+#endif /* CONFIG_P2P_WOWLAN */
+
+struct wifidirect_info {
+	_adapter				*padapter;
+	_timer					find_phase_timer;
+	_timer					restore_p2p_state_timer;
+
+	/*	Used to do the scanning. After confirming the peer is availalble, the driver transmits the P2P frame to peer. */
+	_timer					pre_tx_scan_timer;
+	_timer					reset_ch_sitesurvey;
+	_timer					reset_ch_sitesurvey2;	/*	Just for resetting the scan limit function by using p2p nego */
+#ifdef CONFIG_CONCURRENT_MODE
+	/*	Used to switch the channel between legacy AP and listen state. */
+	_timer					ap_p2p_switch_timer;
+#endif
+	struct tx_provdisc_req_info	tx_prov_disc_info;
+	struct rx_provdisc_req_info rx_prov_disc_info;
+	struct tx_invite_req_info	invitereq_info;
+	struct profile_info			profileinfo[P2P_MAX_PERSISTENT_GROUP_NUM];	/*	Store the profile information of persistent group */
+	struct tx_invite_resp_info	inviteresp_info;
+	struct tx_nego_req_info	nego_req_info;
+	struct group_id_info		groupid_info;	/*	Store the group id information when doing the group negotiation handshake. */
+	struct scan_limit_info		rx_invitereq_info;	/*	Used for get the limit scan channel from the Invitation procedure */
+	struct scan_limit_info		p2p_info;		/*	Used for get the limit scan channel from the P2P negotiation handshake */
+#ifdef CONFIG_WFD
+	struct wifi_display_info		*wfd_info;
+#endif
+
+#ifdef CONFIG_P2P_WOWLAN
+	struct p2p_wowlan_info		p2p_wow_info;
+#endif /* CONFIG_P2P_WOWLAN */
+
+	enum P2P_ROLE			role;
+	enum P2P_STATE			pre_p2p_state;
+	enum P2P_STATE			p2p_state;
+	u8						device_addr[ETH_ALEN];	/*	The device address should be the mac address of this device. */
+	u8						interface_addr[ETH_ALEN];
+	u8						social_chan[4];
+	u8						listen_channel;
+	u8						operating_channel;
+	u8						listen_dwell;		/*	This value should be between 1 and 3 */
+	u8						support_rate[8];
+	u8						p2p_wildcard_ssid[P2P_WILDCARD_SSID_LEN];
+	u8						intent;		/*	should only include the intent value. */
+	u8						p2p_peer_interface_addr[ETH_ALEN];
+	u8						p2p_peer_device_addr[ETH_ALEN];
+	u8						peer_intent;	/*	Included the intent value and tie breaker value. */
+	u8						device_name[WPS_MAX_DEVICE_NAME_LEN];	/*	Device name for displaying on searching device screen */
+	u16						device_name_len;
+	u8						profileindex;	/*	Used to point to the index of profileinfo array */
+	u8						peer_operating_ch;
+	u8						find_phase_state_exchange_cnt;
+	u16						device_password_id_for_nego;	/*	The device password ID for group negotation */
+	u8						negotiation_dialog_token;
+	u8						nego_ssid[WLAN_SSID_MAXLEN];	/*	SSID information for group negotitation */
+	u8						nego_ssidlen;
+	u8						p2p_group_ssid[WLAN_SSID_MAXLEN];
+	u8						p2p_group_ssid_len;
+	u8						persistent_supported;		/*	Flag to know the persistent function should be supported or not. */
+														/*	In the Sigma test, the Sigma will provide this enable from the sta_set_p2p CAPI. */
+														/*	0: disable */
+														/*	1: enable */
+	u8						session_available;			/*	Flag to set the WFD session available to enable or disable "by Sigma" */
+														/*	In the Sigma test, the Sigma will disable the session available by using the sta_preset CAPI. */
+														/*	0: disable */
+														/*	1: enable */
+
+	u8						wfd_tdls_enable;			/*	Flag to enable or disable the TDLS by WFD Sigma */
+														/*	0: disable */
+														/*	1: enable */
+	u8						wfd_tdls_weaksec;			/*	Flag to enable or disable the weak security function for TDLS by WFD Sigma */
+														/*	0: disable */
+														/*	In this case, the driver can't issue the tdsl setup request frame. */
+														/*	1: enable */
+														/*	In this case, the driver can issue the tdls setup request frame */
+														/*	even the current security is weak security. */
+
+	enum	P2P_WPSINFO		ui_got_wps_info;			/*	This field will store the WPS value (PIN value or PBC) that UI had got from the user. */
+	u16						supported_wps_cm;			/*	This field describes the WPS config method which this driver supported. */
+														/*	The value should be the combination of config method defined in page104 of WPS v2.0 spec.	 */
+	u8						external_uuid;				/* UUID flag */
+	u8						uuid[16];					/* UUID */
+	uint						channel_list_attr_len;	/*	This field will contain the length of body of P2P Channel List attribute of group negotitation response frame. */
+	u8						channel_list_attr[100];		/*	This field will contain the body of P2P Channel List attribute of group negotitation response frame. */
+														/*	We will use the channel_cnt and channel_list fields when constructing the group negotitation confirm frame. */
+	u8						driver_interface;			/*	Indicate DRIVER_WEXT or DRIVER_CFG80211 */
+
+#ifdef CONFIG_CONCURRENT_MODE
+	u16						ext_listen_interval;	/*	The interval to be available with legacy AP (ms) */
+	u16						ext_listen_period;	/*	The time period to be available for P2P listen state (ms) */
+#endif
+#ifdef CONFIG_P2P_PS
+	enum P2P_PS_MODE		p2p_ps_mode; /* indicate p2p ps mode */
+	enum P2P_PS_STATE		p2p_ps_state; /* indicate p2p ps state */
+	u8						noa_index; /* Identifies and instance of Notice of Absence timing. */
+	u8						ctwindow; /* Client traffic window. A period of time in TU after TBTT. */
+	u8						opp_ps; /* opportunistic power save. */
+	u8						noa_num; /* number of NoA descriptor in P2P IE. */
+	u8						noa_count[P2P_MAX_NOA_NUM]; /* Count for owner, Type of client. */
+	u32						noa_duration[P2P_MAX_NOA_NUM]; /* Max duration for owner, preferred or min acceptable duration for client. */
+	u32						noa_interval[P2P_MAX_NOA_NUM]; /* Length of interval for owner, preferred or max acceptable interval of client. */
+	u32						noa_start_time[P2P_MAX_NOA_NUM]; /* schedule expressed in terms of the lower 4 bytes of the TSF timer. */
+#endif /* CONFIG_P2P_PS */
+};
+
+struct tdls_ss_record {	/* signal strength record */
+	u8		macaddr[ETH_ALEN];
+	u8		RxPWDBAll;
+	u8		is_tdls_sta;	/* _TRUE: direct link sta, _FALSE: else */
+};
+
+struct tdls_temp_mgmt {
+	u8	initiator;	/* 0: None, 1: we initiate, 2: peer initiate */
+	u8	peer_addr[ETH_ALEN];
+};
+
+#ifdef CONFIG_TDLS_CH_SW
+struct tdls_ch_switch {
+	u32	ch_sw_state;
+	ATOMIC_T	chsw_on;
+	u8	addr[ETH_ALEN];
+	u8	off_ch_num;
+	u8	ch_offset;
+	u32	cur_time;
+	u8	delay_switch_back;
+	u8	dump_stack;
+	struct submit_ctx	chsw_sctx;
+};
+#endif
+
+struct tdls_info {
+	u8					ap_prohibited;
+	u8					ch_switch_prohibited;
+	u8					link_established;
+	u8					sta_cnt;
+	u8					sta_maximum;	/* 1:tdls sta is equal (NUM_STA-1), reach max direct link number; 0: else; */
+	struct tdls_ss_record	ss_record;
+#ifdef CONFIG_TDLS_CH_SW
+	struct tdls_ch_switch	chsw_info;
+#endif
+
+	u8					ch_sensing;
+	u8					cur_channel;
+	u8					collect_pkt_num[MAX_CHANNEL_NUM];
+	_lock				cmd_lock;
+	_lock				hdl_lock;
+	u8					watchdog_count;
+	u8					dev_discovered;		/* WFD_TDLS: for sigma test */
+
+	/* Let wpa_supplicant to setup*/
+	u8					driver_setup;
+#ifdef CONFIG_WFD
+	struct wifi_display_info		*wfd_info;
+#endif
+
+	struct submit_ctx	*tdls_sctx;
+};
+
+struct tdls_txmgmt {
+	u8 peer[ETH_ALEN];
+	u8 action_code;
+	u8 dialog_token;
+	u16 status_code;
+	u8 *buf;
+	size_t len;
+};
+
+/* used for mlme_priv.roam_flags */
+enum {
+	RTW_ROAM_ON_EXPIRED = BIT0,
+	RTW_ROAM_ON_RESUME = BIT1,
+	RTW_ROAM_ACTIVE = BIT2,
+};
+
+struct beacon_keys {
+	u8 ssid[IW_ESSID_MAX_SIZE];
+	u32 ssid_len;
+	u8 bcn_channel;
+	u16 ht_cap_info;
+	u8 ht_info_infos_0_sco; /* bit0 & bit1 in infos[0] is second channel offset */
+	int encryp_protocol;
+	int pairwise_cipher;
+	int group_cipher;
+	int is_8021x;
+};
+#ifdef CONFIG_RTW_80211R
+#define RTW_FT_ACTION_REQ_LMT	4
+#define RTW_FT_MAX_IE_SZ	256
+
+enum _rtw_ft_sta_status {
+	RTW_FT_UNASSOCIATED_STA = 0,
+	RTW_FT_AUTHENTICATING_STA,
+	RTW_FT_AUTHENTICATED_STA,
+	RTW_FT_ASSOCIATING_STA,
+	RTW_FT_ASSOCIATED_STA,
+	RTW_FT_REQUESTING_STA,
+	RTW_FT_REQUESTED_STA,
+	RTW_FT_CONFIRMED_STA,
+	RTW_FT_UNSPECIFIED_STA
+};
+
+#define rtw_ft_chk_status(a, s) \
+	((a)->mlmepriv.ft_roam.ft_status == (s))
+
+#define rtw_ft_roam_status(a, s)	\
+	((rtw_to_roam(a) > 0) && rtw_ft_chk_status(a, s))
+
+#define rtw_ft_authed_sta(a)	\
+	((rtw_ft_chk_status(a, RTW_FT_AUTHENTICATED_STA)) ||	\
+	(rtw_ft_chk_status(a, RTW_FT_ASSOCIATING_STA)) ||	\
+	(rtw_ft_chk_status(a, RTW_FT_ASSOCIATED_STA)))
+
+#define rtw_ft_set_status(a, s) \
+	do { \
+		((a)->mlmepriv.ft_roam.ft_status = (s)); \
+	} while (0)
+
+#define rtw_ft_lock_set_status(a, s, irq) \
+	do { \
+		_enter_critical_bh(&(a)->mlmepriv.lock, ((_irqL *)(irq)));	\
+		((a)->mlmepriv.ft_roam.ft_status = (s));	\
+		_exit_critical_bh(&(a)->mlmepriv.lock, ((_irqL *)(irq)));	\
+	} while (0)
+
+#define rtw_ft_reset_status(a) \
+	do { \
+		((a)->mlmepriv.ft_roam.ft_status = RTW_FT_UNASSOCIATED_STA); \
+	} while (0)
+
+enum rtw_ft_capability {
+	RTW_FT_EN = BIT0,
+	RTW_FT_OTD_EN = BIT1,
+	RTW_FT_PEER_EN = BIT2,
+	RTW_FT_PEER_OTD_EN = BIT3,
+	RTW_FT_BTM_ROAM = BIT4,
+};
+
+#define rtw_ft_chk_flags(a, f) \
+	((a)->mlmepriv.ft_roam.ft_flags & (f))
+
+#define rtw_ft_set_flags(a, f) \
+	do { \
+		((a)->mlmepriv.ft_roam.ft_flags |= (f)); \
+	} while (0)
+
+#define rtw_ft_clr_flags(a, f) \
+	do { \
+		((a)->mlmepriv.ft_roam.ft_flags &= ~(f)); \
+	} while (0)
+
+#define rtw_ft_roam(a)	\
+	((rtw_to_roam(a) > 0) && rtw_ft_chk_flags(a, RTW_FT_PEER_EN))
+	
+#define rtw_ft_valid_akm(a, t)	\
+	((rtw_ft_chk_flags(a, RTW_FT_EN)) && \
+	(((t) == 3) || ((t) == 4)))
+
+#define rtw_ft_roam_expired(a, r)	\
+	((rtw_chk_roam_flags(a, RTW_ROAM_ON_EXPIRED)) \
+	&& (r == WLAN_REASON_ACTIVE_ROAM))
+
+#define rtw_ft_otd_roam_en(a)	\
+	((rtw_ft_chk_flags(a, RTW_FT_OTD_EN))	\
+	&& ((a)->mlmepriv.ft_roam.ft_roam_on_expired == _FALSE)	\
+	&& ((a)->mlmepriv.ft_roam.ft_cap & 0x01))
+	
+#define rtw_ft_otd_roam(a) \
+	rtw_ft_chk_flags(a, RTW_FT_PEER_OTD_EN)
+
+#define rtw_ft_valid_otd_candidate(a, p)	\
+	((rtw_ft_chk_flags(a, RTW_FT_OTD_EN)) 	\
+	&& ((rtw_ft_chk_flags(a, RTW_FT_PEER_OTD_EN)	\
+	&& ((*((p)+4) & 0x01) == 0))	\
+	|| ((rtw_ft_chk_flags(a, RTW_FT_PEER_OTD_EN) == 0)	\
+	&& (*((p)+4) & 0x01))))
+
+struct ft_roam_info {
+	u16	mdid;
+	u8	ft_cap;	
+	/*b0: FT over DS, b1: Resource Req Protocol Cap, b2~b7: Reserved*/
+	u8	updated_ft_ies[RTW_FT_MAX_IE_SZ];
+	u16	updated_ft_ies_len;
+	u8	ft_action[RTW_FT_MAX_IE_SZ];
+	u16	ft_action_len;
+	struct cfg80211_ft_event_params ft_event;
+	u8	ft_roam_on_expired;
+	u8	ft_flags;
+	u32 ft_status;
+	u32 ft_req_retry_cnt;
+	bool ft_updated_bcn;	
+};
+#endif
+
+#ifdef CONFIG_LAYER2_ROAMING
+#if defined(CONFIG_RTW_WNM) || defined(CONFIG_RTW_80211K)
+#define RTW_RRM_NB_RPT_EN		BIT(1)
+#define RTW_MAX_NB_RPT_NUM	8
+
+#define rtw_roam_busy_scan(a, nb)	\
+	(((a)->mlmepriv.LinkDetectInfo.bBusyTraffic == _TRUE) && \
+	(((a)->mlmepriv.ch_cnt) < ((nb)->nb_rpt_ch_list_num)))
+
+#define rtw_wnm_btm_preference_cap(a) \
+	((a)->mlmepriv.nb_info.preference_en == _TRUE)
+
+#define rtw_wnm_btm_diff_bss(a) \
+	((rtw_wnm_btm_preference_cap(a)) && \
+	(is_zero_mac_addr((a)->mlmepriv.nb_info.roam_target_addr) == _FALSE) && \
+	(_rtw_memcmp((a)->mlmepriv.nb_info.roam_target_addr,\
+		(a)->mlmepriv.cur_network.network.MacAddress, ETH_ALEN) == _FALSE))
+
+#define rtw_wnm_btm_roam_candidate(a, c) \
+	((rtw_wnm_btm_preference_cap(a)) && \
+	(is_zero_mac_addr((a)->mlmepriv.nb_info.roam_target_addr) == _FALSE) && \
+	(_rtw_memcmp((a)->mlmepriv.nb_info.roam_target_addr,\
+		(c)->network.MacAddress, ETH_ALEN)))
+
+#define rtw_wnm_set_ext_cap_btm(_pEleStart, _val) \
+	SET_BITS_TO_LE_1BYTE(((u8 *)(_pEleStart))+2, 3, 1, _val)
+
+#define wnm_btm_bss_term_inc(p) (*((u8 *)((p)+3)) & BSS_TERMINATION_INCLUDED)
+
+#define wnm_btm_ess_disassoc_im(p) (*((u8 *)((p)+3)) & ESS_DISASSOC_IMMINENT)
+
+#define wnm_btm_req_mode(p) (*((u8 *)((p)+3)))
+
+#define wnm_btm_disassoc_timer(p) (*((u16 *)((p)+4)))
+
+#define wnm_btm_valid_interval(p) (*((u8 *)((p)+6)))
+
+#define wnm_btm_term_duration_offset(p) ((p)+7)
+
+/*IEEE Std 80211k Figure 7-95b Neighbor Report element format*/
+struct nb_rpt_hdr {
+	u8 id; /*0x34: Neighbor Report Element ID*/
+	u8 len;
+	u8 bssid[ETH_ALEN];
+	u32 bss_info;
+	u8 reg_class;
+	u8 ch_num;
+	u8 phy_type;	
+};
+
+/*IEEE Std 80211v, Figure 7-95e2�XBSS Termination Duration subelement field format */
+struct btm_term_duration {
+	u8 id;
+	u8 len;
+	u64 tsf;
+	u16 duration;
+};
+
+/*IEEE Std 80211v, Figure 7-101n8�XBSS Transition Management Request frame body format */
+struct btm_req_hdr {
+	u8 req_mode;
+	u16 disassoc_timer;
+	u8 validity_interval;
+	struct btm_term_duration term_duration;
+};
+
+/*IEEE Std 80211v,  Table 7-43b Optional Subelement IDs for Neighbor Report*/
+/* BSS Transition Candidate Preference */
+#define WNM_BTM_CAND_PREF_SUBEID 0x03
+
+/* BSS Termination Duration */
+#define WNM_BTM_TERM_DUR_SUBEID		0x04
+
+struct wnm_btm_cant {
+	struct nb_rpt_hdr nb_rpt;
+	u8 preference;	/* BSS Transition Candidate Preference */
+};
+
+enum rtw_btm_req_mod {
+	PREFERRED_CANDIDATE_LIST_INCLUDED = BIT0,
+	ABRIDGED = BIT1,
+	DISASSOC_IMMINENT = BIT2,
+	BSS_TERMINATION_INCLUDED = BIT3,
+	ESS_DISASSOC_IMMINENT = BIT4,
+};
+
+struct roam_nb_info {
+	struct nb_rpt_hdr nb_rpt[RTW_MAX_NB_RPT_NUM];
+	struct rtw_ieee80211_channel nb_rpt_ch_list[RTW_MAX_NB_RPT_NUM];
+	bool	nb_rpt_valid;
+	u8	nb_rpt_ch_list_num;
+	u8 preference_en;
+	u8 roam_target_addr[ETH_ALEN];
+	u32	last_nb_rpt_entries;
+	bool	nb_rpt_is_same;
+	_timer roam_scan_timer;
+};
+#endif	/* defined(CONFIG_RTW_WNM) || defined(CONFIG_RTW_80211K) */
+#endif
+
+struct mlme_priv {
+
+	_lock	lock;
+	sint	fw_state;	/* shall we protect this variable? maybe not necessarily... */
+	u8	to_join; /* flag */
+	u16 join_status;
+#ifdef CONFIG_LAYER2_ROAMING
+	u8 to_roam; /* roaming trying times */
+	struct wlan_network *roam_network; /* the target of active roam */
+	u8 roam_flags;
+	u8 roam_rssi_diff_th; /* rssi difference threshold for active scan candidate selection */
+	u32 roam_scan_int; 		/* scan interval for active roam (Unit:2 second)*/
+	u32 roam_scanr_exp_ms; /* scan result expire time in ms  for roam */
+	u8 roam_tgt_addr[ETH_ALEN]; /* request to roam to speicific target without other consideration */
+	u8 roam_rssi_threshold;
+	systime last_roaming;
+	bool need_to_roam;
+#endif
+
+	u8	*nic_hdl;
+	u32	max_bss_cnt;		/*	The size of scan queue	*/
+	_list		*pscanned;
+	_queue	free_bss_pool;
+	_queue	scanned_queue;
+	u8		*free_bss_buf;
+	u32	num_of_scanned;
+
+	NDIS_802_11_SSID	assoc_ssid;
+	u8	assoc_bssid[6];
+
+	struct wlan_network	cur_network;
+	struct wlan_network *cur_network_scanned;
+
+	/* bcn check info */
+	struct beacon_keys cur_beacon_keys; /* save current beacon keys */
+#ifdef CONFIG_BCN_CNT_CONFIRM_HDL
+	struct beacon_keys new_beacon_keys; /* save new beacon keys */
+	u8 new_beacon_cnts; /* if new_beacon_cnts >= threshold, ap beacon is changed */
+#endif
+
+#ifdef CONFIG_ARP_KEEP_ALIVE
+	/* for arp offload keep alive */
+	u8 bGetGateway;
+	u8	GetGatewayTryCnt;
+	u8	gw_mac_addr[ETH_ALEN];
+	u8	gw_ip[4];
+#endif
+
+	/* uint wireless_mode; no used, remove it */
+
+	u32	auto_scan_int_ms;
+
+	_timer assoc_timer;
+
+	uint assoc_by_bssid;
+	uint assoc_by_rssi;
+
+	_timer scan_to_timer; /* driver itself handles scan_timeout status. */
+	systime scan_start_time; /* used to evaluate the time spent in scanning */
+
+#ifdef CONFIG_SET_SCAN_DENY_TIMER
+	_timer set_scan_deny_timer;
+	ATOMIC_T set_scan_deny; /* 0: allowed, 1: deny */
+#endif
+	u8 wpa_phase;/*wpa_phase after wps finished*/
+
+	struct qos_priv qospriv;
+
+#ifdef CONFIG_80211N_HT
+
+	/* Number of non-HT AP/stations */
+	int num_sta_no_ht;
+
+	/* Number of HT AP/stations 20 MHz */
+	/* int num_sta_ht_20mhz; */
+
+
+	int num_FortyMHzIntolerant;
+
+	struct ht_priv	htpriv;
+
+#endif
+
+#ifdef CONFIG_80211AC_VHT
+	struct vht_priv	vhtpriv;
+#ifdef ROKU_PRIVATE
+	/*infra mode, used to store AP's info*/
+	struct vht_priv_infra_ap vhtpriv_infra_ap;
+#endif /* ROKU_PRIVATE */
+#endif
+
+#ifdef ROKU_PRIVATE
+	struct ht_priv_infra_ap htpriv_infra_ap;
+#endif /* ROKU_PRIVATE */
+
+#ifdef CONFIG_BEAMFORMING
+#ifndef RTW_BEAMFORMING_VERSION_2
+#if (BEAMFORMING_SUPPORT == 0)/*for driver beamforming*/
+	struct beamforming_info	beamforming_info;
+#endif
+#endif /* !RTW_BEAMFORMING_VERSION_2 */
+#endif
+
+#ifdef CONFIG_RTW_80211R
+	struct ft_roam_info ft_roam;
+#endif
+#if defined(CONFIG_RTW_WNM) || defined(CONFIG_RTW_80211K)
+	struct roam_nb_info nb_info;
+	u8 ch_cnt;
+#endif
+
+	RT_LINK_DETECT_T	LinkDetectInfo;
+
+	u8	acm_mask; /* for wmm acm mask */
+	RT_SCAN_TYPE	scan_mode; /* active: 1, passive: 0 */
+
+	u8 *wps_probe_req_ie;
+	u32 wps_probe_req_ie_len;
+
+	u8 ext_capab_ie_data[8];/*currently for ap mode only*/
+	u8 ext_capab_ie_len;
+
+#if defined(CONFIG_AP_MODE) && defined (CONFIG_NATIVEAP_MLME)
+	/* Number of associated Non-ERP stations (i.e., stations using 802.11b
+	 * in 802.11g BSS) */
+	int num_sta_non_erp;
+
+	/* Number of associated stations that do not support Short Slot Time */
+	int num_sta_no_short_slot_time;
+
+	/* Number of associated stations that do not support Short Preamble */
+	int num_sta_no_short_preamble;
+
+	ATOMIC_T olbc; /* Overlapping Legacy BSS Condition (Legacy b/g)*/
+
+	/* Number of HT associated stations that do not support greenfield */
+	int num_sta_ht_no_gf;
+
+	/* Number of associated non-HT stations */
+	/* int num_sta_no_ht; */
+
+	/* Number of HT associated stations 20 MHz */
+	int num_sta_ht_20mhz;
+
+	/* number of associated stations 40MHz intolerant */
+	int num_sta_40mhz_intolerant;
+
+	/* Overlapping BSS information */
+	ATOMIC_T olbc_ht;
+
+#ifdef CONFIG_80211N_HT
+	int ht_20mhz_width_req;
+	int ht_intolerant_ch_reported;
+	u16 ht_op_mode;
+	u8 sw_to_20mhz; /*switch to 20Mhz BW*/
+#endif /* CONFIG_80211N_HT */
+
+#ifdef CONFIG_RTW_80211R
+	u8 *auth_rsp;
+	u32 auth_rsp_len;
+#endif
+	u8 *assoc_req;
+	u32 assoc_req_len;
+
+	u8 *assoc_rsp;
+	u32 assoc_rsp_len;
+
+	/* u8 *wps_probe_req_ie; */
+	/* u32 wps_probe_req_ie_len; */
+
+	u8 *wps_beacon_ie;
+	u32 wps_beacon_ie_len;
+
+	u8 *wps_probe_resp_ie;
+	u32 wps_probe_resp_ie_len;
+
+	u8 *wps_assoc_resp_ie;
+	u32 wps_assoc_resp_ie_len;
+
+	u8 *p2p_beacon_ie;
+	u32 p2p_beacon_ie_len;
+
+	u8 *p2p_probe_req_ie;
+	u32 p2p_probe_req_ie_len;
+
+	u8 *p2p_probe_resp_ie;
+	u32 p2p_probe_resp_ie_len;
+
+	u8 *p2p_go_probe_resp_ie;		/* for GO */
+	u32 p2p_go_probe_resp_ie_len;	/* for GO */
+
+	u8 *p2p_assoc_req_ie;
+	u32 p2p_assoc_req_ie_len;
+
+	u8 *p2p_assoc_resp_ie;
+	u32 p2p_assoc_resp_ie_len;
+
+	_lock	bcn_update_lock;
+	u8		update_bcn;
+
+	u8 ori_ch;
+	u8 ori_bw;
+	u8 ori_offset;
+	#ifdef CONFIG_80211AC_VHT
+	u8 ori_vht_en;
+	#endif
+#endif /* #if defined (CONFIG_AP_MODE) && defined (CONFIG_NATIVEAP_MLME) */
+
+#if defined(CONFIG_WFD) && defined(CONFIG_IOCTL_CFG80211)
+	u8 *wfd_beacon_ie;
+	u32 wfd_beacon_ie_len;
+
+	u8 *wfd_probe_req_ie;
+	u32 wfd_probe_req_ie_len;
+
+	u8 *wfd_probe_resp_ie;
+	u32 wfd_probe_resp_ie_len;
+
+	u8 *wfd_go_probe_resp_ie;		/* for GO */
+	u32 wfd_go_probe_resp_ie_len;	/* for GO */
+
+	u8 *wfd_assoc_req_ie;
+	u32 wfd_assoc_req_ie_len;
+
+	u8 *wfd_assoc_resp_ie;
+	u32 wfd_assoc_resp_ie_len;
+#endif
+
+#ifdef RTK_DMP_PLATFORM
+	/* DMP kobject_hotplug function  signal need in passive level */
+	_workitem	Linkup_workitem;
+	_workitem	Linkdown_workitem;
+#endif
+
+#ifdef CONFIG_INTEL_WIDI
+	int	widi_state;
+	int	listen_state;
+	_timer	listen_timer;
+	ATOMIC_T	rx_probe_rsp; /* 1:receive probe respone from RDS source. */
+	u8	*l2sdTaBuffer;
+	u8	channel_idx;
+	u8	group_cnt;	/* In WiDi 3.5, they specified another scan algo. for WFD/RDS co-existed */
+	u8	sa_ext[L2SDTA_SERVICE_VE_LEN];
+
+	u8	widi_enable;
+	/**
+	 * For WiDi 4; upper layer would set
+	 * p2p_primary_device_type_category_id
+	 * p2p_primary_device_type_sub_category_id
+	 * p2p_secondary_device_type_category_id
+	 * p2p_secondary_device_type_sub_category_id
+	 */
+	u16	p2p_pdt_cid;
+	u16	p2p_pdt_scid;
+	u8	num_p2p_sdt;
+	u16	p2p_sdt_cid[MAX_NUM_P2P_SDT];
+	u16	p2p_sdt_scid[MAX_NUM_P2P_SDT];
+	u8	p2p_reject_disable;	/* When starting NL80211 wpa_supplicant/hostapd, it will call netdev_close */
+							/* such that it will cause p2p disabled. Use this flag to reject. */
+#endif /* CONFIG_INTEL_WIDI */
+	systime lastscantime;
+#ifdef CONFIG_CONCURRENT_MODE
+	u8	scanning_via_buddy_intf;
+#endif
+
+#ifdef CONFIG_APPEND_VENDOR_IE_ENABLE
+	u32 vendor_ie_mask[WLAN_MAX_VENDOR_IE_NUM];
+	u8 vendor_ie[WLAN_MAX_VENDOR_IE_NUM][WLAN_MAX_VENDOR_IE_LEN];
+	u32 vendor_ielen[WLAN_MAX_VENDOR_IE_NUM];
+#endif
+};
+
+#define mlme_set_scan_to_timer(mlme, ms) \
+	do { \
+		/* RTW_INFO("%s set_scan_to_timer(%p, %d)\n", __FUNCTION__, (mlme), (ms)); */ \
+		_set_timer(&(mlme)->scan_to_timer, (ms)); \
+	} while (0)
+
+#define rtw_mlme_set_auto_scan_int(adapter, ms) \
+	do { \
+		adapter->mlmepriv.auto_scan_int_ms = ms; \
+	} while (0)
+
+#define RTW_AUTO_SCAN_REASON_UNSPECIFIED		0
+#define RTW_AUTO_SCAN_REASON_2040_BSS			BIT0
+#define RTW_AUTO_SCAN_REASON_ACS				BIT1
+#define RTW_AUTO_SCAN_REASON_ROAM				BIT2
+#define RTW_AUTO_SCAN_REASON_MESH_OFFCH_CAND	BIT3
+
+void rtw_mlme_reset_auto_scan_int(_adapter *adapter, u8 *reason);
+
+#ifdef CONFIG_AP_MODE
+
+struct hostapd_priv {
+	_adapter *padapter;
+
+#ifdef CONFIG_HOSTAPD_MLME
+	struct net_device *pmgnt_netdev;
+	struct usb_anchor anchored;
+#endif
+
+};
+
+extern int hostapd_mode_init(_adapter *padapter);
+extern void hostapd_mode_unload(_adapter *padapter);
+#endif
+
+
+extern void rtw_joinbss_event_prehandle(_adapter *adapter, u8 *pbuf, u16 status);
+extern void rtw_survey_event_callback(_adapter *adapter, u8 *pbuf);
+extern void rtw_surveydone_event_callback(_adapter *adapter, u8 *pbuf);
+extern void rtw_joinbss_event_callback(_adapter *adapter, u8 *pbuf);
+extern void rtw_stassoc_event_callback(_adapter *adapter, u8 *pbuf);
+extern void rtw_stadel_event_callback(_adapter *adapter, u8 *pbuf);
+void rtw_sta_mstatus_disc_rpt(_adapter *adapter, u8 mac_id);
+void rtw_sta_mstatus_report(_adapter *adapter);
+extern void rtw_atimdone_event_callback(_adapter *adapter, u8 *pbuf);
+extern void rtw_cpwm_event_callback(_adapter *adapter, u8 *pbuf);
+extern void rtw_wmm_event_callback(PADAPTER padapter, u8 *pbuf);
+#ifdef CONFIG_IEEE80211W
+void rtw_sta_timeout_event_callback(_adapter *adapter, u8 *pbuf);
+#endif /* CONFIG_IEEE80211W */
+#ifdef CONFIG_RTW_80211R
+void rtw_ft_info_init(struct ft_roam_info *pft);
+u8 rtw_ft_chk_roaming_candidate(_adapter *padapter, 
+	struct wlan_network *competitor);
+void rtw_ft_update_stainfo(_adapter *padapter, WLAN_BSSID_EX *pnetwork);
+void rtw_ft_reassoc_event_callback(_adapter *padapter, u8 *pbuf);
+#endif
+#if defined(CONFIG_RTW_WNM) || defined(CONFIG_RTW_80211K)
+void rtw_roam_nb_info_init(_adapter *padapter);
+#endif
+
+thread_return event_thread(thread_context context);
+
+extern void rtw_free_network_queue(_adapter *adapter, u8 isfreeall);
+extern int rtw_init_mlme_priv(_adapter *adapter);/* (struct mlme_priv *pmlmepriv); */
+
+extern void rtw_free_mlme_priv(struct mlme_priv *pmlmepriv);
+
+
+extern sint rtw_select_and_join_from_scanned_queue(struct mlme_priv *pmlmepriv);
+extern sint rtw_set_key(_adapter *adapter, struct security_priv *psecuritypriv, sint keyid, u8 set_tx, bool enqueue);
+extern sint rtw_set_auth(_adapter *adapter, struct security_priv *psecuritypriv);
+
+__inline static u8 *get_bssid(struct mlme_priv *pmlmepriv)
+{
+	/* if sta_mode:pmlmepriv->cur_network.network.MacAddress=> bssid */
+	/* if adhoc_mode:pmlmepriv->cur_network.network.MacAddress=> ibss mac address */
+	return pmlmepriv->cur_network.network.MacAddress;
+}
+
+__inline static sint check_fwstate(struct mlme_priv *pmlmepriv, sint state)
+{
+	if ((state == WIFI_NULL_STATE) &&
+		(pmlmepriv->fw_state == WIFI_NULL_STATE))
+		return _TRUE;
+
+	if (pmlmepriv->fw_state & state)
+		return _TRUE;
+
+	return _FALSE;
+}
+
+__inline static sint get_fwstate(struct mlme_priv *pmlmepriv)
+{
+	return pmlmepriv->fw_state;
+}
+
+/*
+ * No Limit on the calling context,
+ * therefore set it to be the critical section...
+ *
+ * ### NOTE:#### (!!!!)
+ * MUST TAKE CARE THAT BEFORE CALLING THIS FUNC, YOU SHOULD HAVE LOCKED pmlmepriv->lock
+ */
+extern void rtw_mi_update_iface_status(struct mlme_priv *pmlmepriv, sint state);
+
+static inline void set_fwstate(struct mlme_priv *pmlmepriv, sint state)
+{
+	pmlmepriv->fw_state |= state;
+	rtw_mi_update_iface_status(pmlmepriv, state);
+}
+static inline void init_fwstate(struct mlme_priv *pmlmepriv, sint state)
+{
+	pmlmepriv->fw_state = state;
+	rtw_mi_update_iface_status(pmlmepriv, state);
+}
+
+static inline void _clr_fwstate_(struct mlme_priv *pmlmepriv, sint state)
+{
+	pmlmepriv->fw_state &= ~state;
+	rtw_mi_update_iface_status(pmlmepriv, state);
+}
+
+/*
+ * No Limit on the calling context,
+ * therefore set it to be the critical section...
+ */
+static inline void clr_fwstate(struct mlme_priv *pmlmepriv, sint state)
+{
+	_irqL irqL;
+
+	_enter_critical_bh(&pmlmepriv->lock, &irqL);
+	_clr_fwstate_(pmlmepriv, state);
+	_exit_critical_bh(&pmlmepriv->lock, &irqL);
+}
+
+static inline void up_scanned_network(struct mlme_priv *pmlmepriv)
+{
+	_irqL irqL;
+
+	_enter_critical_bh(&pmlmepriv->lock, &irqL);
+	pmlmepriv->num_of_scanned++;
+	_exit_critical_bh(&pmlmepriv->lock, &irqL);
+}
+u8 rtw_is_adapter_up(_adapter *padapter);
+
+__inline static void down_scanned_network(struct mlme_priv *pmlmepriv)
+{
+	_irqL irqL;
+
+	_enter_critical_bh(&pmlmepriv->lock, &irqL);
+	pmlmepriv->num_of_scanned--;
+	_exit_critical_bh(&pmlmepriv->lock, &irqL);
+}
+
+__inline static void set_scanned_network_val(struct mlme_priv *pmlmepriv, sint val)
+{
+	_irqL irqL;
+
+	_enter_critical_bh(&pmlmepriv->lock, &irqL);
+	pmlmepriv->num_of_scanned = val;
+	_exit_critical_bh(&pmlmepriv->lock, &irqL);
+}
+
+extern u16 rtw_get_capability(WLAN_BSSID_EX *bss);
+extern bool rtw_update_scanned_network(_adapter *adapter, WLAN_BSSID_EX *target);
+extern void rtw_disconnect_hdl_under_linked(_adapter *adapter, struct sta_info *psta, u8 free_assoc);
+extern void rtw_generate_random_ibss(u8 *pibss);
+struct wlan_network *_rtw_find_network(_queue *scanned_queue, const u8 *addr);
+struct wlan_network *rtw_find_network(_queue *scanned_queue, const u8 *addr);
+extern struct wlan_network *rtw_get_oldest_wlan_network(_queue *scanned_queue);
+struct wlan_network *_rtw_find_same_network(_queue *scanned_queue, struct wlan_network *network);
+struct wlan_network *rtw_find_same_network(_queue *scanned_queue, struct wlan_network *network);
+
+extern void rtw_free_assoc_resources(_adapter *adapter, u8 lock_scanned_queue);
+extern void rtw_indicate_disconnect(_adapter *adapter, u16 reason, u8 locally_generated);
+extern void rtw_indicate_connect(_adapter *adapter);
+void rtw_indicate_scan_done(_adapter *padapter, bool aborted);
+
+void rtw_drv_scan_by_self(_adapter *padapter, u8 reason);
+void rtw_scan_wait_completed(_adapter *adapter);
+u32 rtw_scan_abort_timeout(_adapter *adapter, u32 timeout_ms);
+void rtw_scan_abort_no_wait(_adapter *adapter);
+void rtw_scan_abort(_adapter *adapter);
+u32 rtw_join_abort_timeout(_adapter *adapter, u32 timeout_ms);
+
+extern int rtw_restruct_sec_ie(_adapter *adapter, u8 *out_ie);
+#ifdef CONFIG_WMMPS_STA
+void rtw_uapsd_use_default_setting(_adapter *padapter);
+bool rtw_is_wmmps_mode(_adapter *padapter);
+#endif /* CONFIG_WMMPS_STA */
+extern int rtw_restruct_wmm_ie(_adapter *adapter, u8 *in_ie, u8 *out_ie, uint in_len, uint initial_out_len);
+extern void rtw_init_registrypriv_dev_network(_adapter *adapter);
+
+extern void rtw_update_registrypriv_dev_network(_adapter *adapter);
+
+extern void rtw_get_encrypt_decrypt_from_registrypriv(_adapter *adapter);
+
+extern void rtw_join_timeout_handler(void *ctx);
+extern void rtw_scan_timeout_handler(void *ctx);
+
+extern void rtw_dynamic_check_timer_handlder(void *ctx);
+extern void rtw_iface_dynamic_check_timer_handlder(_adapter *adapter);
+
+enum {
+	SS_DENY_MP_MODE,
+	SS_DENY_RSON_SCANING,
+	SS_DENY_BLOCK_SCAN,
+	SS_DENY_BY_DRV,
+	SS_DENY_SELF_AP_UNDER_WPS,
+	SS_DENY_SELF_AP_UNDER_LINKING,
+	SS_DENY_SELF_AP_UNDER_SURVEY,
+	/*SS_DENY_SELF_STA_UNDER_WPS,*/
+	SS_DENY_SELF_STA_UNDER_LINKING,
+	SS_DENY_SELF_STA_UNDER_SURVEY,
+	SS_DENY_BUDDY_UNDER_LINK_WPS,
+	SS_DENY_BUDDY_UNDER_SURVEY,
+	SS_DENY_BUSY_TRAFFIC,
+	SS_ALLOW,
+#ifdef DBG_LA_MODE
+	SS_DENY_LA_MODE,
+#endif
+};
+
+u8 _rtw_sitesurvey_condition_check(const char *caller, _adapter *adapter, bool check_sc_interval);
+#define rtw_sitesurvey_condition_check(adapter, check_sc_interval) _rtw_sitesurvey_condition_check(__func__, adapter, check_sc_interval)
+
+#ifdef CONFIG_SET_SCAN_DENY_TIMER
+bool rtw_is_scan_deny(_adapter *adapter);
+void rtw_clear_scan_deny(_adapter *adapter);
+void rtw_set_scan_deny_timer_hdl(void *ctx);
+void rtw_set_scan_deny(_adapter *adapter, u32 ms);
+#else
+#define rtw_is_scan_deny(adapter) _FALSE
+#define rtw_clear_scan_deny(adapter) do {} while (0)
+#define rtw_set_scan_deny(adapter, ms) do {} while (0)
+#endif
+
+void rtw_free_mlme_priv_ie_data(struct mlme_priv *pmlmepriv);
+
+#define MLME_BEACON_IE			0
+#define MLME_PROBE_REQ_IE		1
+#define MLME_PROBE_RESP_IE		2
+#define MLME_GO_PROBE_RESP_IE	3
+#define MLME_ASSOC_REQ_IE		4
+#define MLME_ASSOC_RESP_IE		5
+
+#if defined(CONFIG_WFD) && defined(CONFIG_IOCTL_CFG80211)
+int rtw_mlme_update_wfd_ie_data(struct mlme_priv *mlme, u8 type, u8 *ie, u32 ie_len);
+#endif
+
+
+/* extern struct wlan_network* _rtw_dequeue_network(_queue *queue); */
+
+extern struct wlan_network *_rtw_alloc_network(struct mlme_priv *pmlmepriv);
+
+
+extern void _rtw_free_network(struct mlme_priv *pmlmepriv, struct wlan_network *pnetwork, u8 isfreeall);
+extern void _rtw_free_network_nolock(struct mlme_priv *pmlmepriv, struct wlan_network *pnetwork);
+
+extern void _rtw_free_network_queue(_adapter *padapter, u8 isfreeall);
+
+extern sint rtw_if_up(_adapter *padapter);
+
+sint rtw_linked_check(_adapter *padapter);
+
+u8 *rtw_get_capability_from_ie(u8 *ie);
+u8 *rtw_get_timestampe_from_ie(u8 *ie);
+u8 *rtw_get_beacon_interval_from_ie(u8 *ie);
+
+
+void rtw_joinbss_reset(_adapter *padapter);
+
+#ifdef CONFIG_80211N_HT
+void	rtw_ht_use_default_setting(_adapter *padapter);
+void rtw_build_wmm_ie_ht(_adapter *padapter, u8 *out_ie, uint *pout_len);
+unsigned int rtw_restructure_ht_ie(_adapter *padapter, u8 *in_ie, u8 *out_ie, uint in_len, uint *pout_len, u8 channel);
+void rtw_update_ht_cap(_adapter *padapter, u8 *pie, uint ie_len, u8 channel);
+void rtw_issue_addbareq_cmd(_adapter *padapter, struct xmit_frame *pxmitframe);
+void rtw_append_exented_cap(_adapter *padapter, u8 *out_ie, uint *pout_len);
+#endif
+
+int rtw_is_same_ibss(_adapter *adapter, struct wlan_network *pnetwork);
+int is_same_network(WLAN_BSSID_EX *src, WLAN_BSSID_EX *dst, u8 feature);
+
+#ifdef CONFIG_LAYER2_ROAMING
+#define rtw_roam_flags(adapter) ((adapter)->mlmepriv.roam_flags)
+#define rtw_chk_roam_flags(adapter, flags) ((adapter)->mlmepriv.roam_flags & flags)
+#define rtw_clr_roam_flags(adapter, flags) \
+	do { \
+		((adapter)->mlmepriv.roam_flags &= ~flags); \
+	} while (0)
+
+#define rtw_set_roam_flags(adapter, flags) \
+	do { \
+		((adapter)->mlmepriv.roam_flags |= flags); \
+	} while (0)
+
+#define rtw_assign_roam_flags(adapter, flags) \
+	do { \
+		((adapter)->mlmepriv.roam_flags = flags); \
+	} while (0)
+
+void _rtw_roaming(_adapter *adapter, struct wlan_network *tgt_network);
+void rtw_roaming(_adapter *adapter, struct wlan_network *tgt_network);
+void rtw_set_to_roam(_adapter *adapter, u8 to_roam);
+u8 rtw_dec_to_roam(_adapter *adapter);
+u8 rtw_to_roam(_adapter *adapter);
+int rtw_select_roaming_candidate(struct mlme_priv *pmlmepriv);
+#else
+#define rtw_roam_flags(adapter) 0
+#define rtw_chk_roam_flags(adapter, flags) 0
+#define rtw_clr_roam_flags(adapter, flags) do {} while (0)
+#define rtw_set_roam_flags(adapter, flags) do {} while (0)
+#define rtw_assign_roam_flags(adapter, flags) do {} while (0)
+#define _rtw_roaming(adapter, tgt_network) do {} while (0)
+#define rtw_roaming(adapter, tgt_network) do {} while (0)
+#define rtw_set_to_roam(adapter, to_roam) do {} while (0)
+#define rtw_dec_to_roam(adapter) 0
+#define rtw_to_roam(adapter) 0
+#define rtw_select_roaming_candidate(mlme) _FAIL
+#endif /* CONFIG_LAYER2_ROAMING */
+
+bool rtw_adjust_chbw(_adapter *adapter, u8 req_ch, u8 *req_bw, u8 *req_offset);
+
+struct sta_media_status_rpt_cmd_parm {
+	struct sta_info *sta;
+	bool connected;
+};
+
+void rtw_sta_media_status_rpt(_adapter *adapter, struct sta_info *sta, bool connected);
+u8 rtw_sta_media_status_rpt_cmd(_adapter *adapter, struct sta_info *sta, bool connected);
+void rtw_sta_media_status_rpt_cmd_hdl(_adapter *adapter, struct sta_media_status_rpt_cmd_parm *parm);
+void rtw_sta_traffic_info(void *sel, _adapter *adapter);
+
+#ifdef CONFIG_INTEL_PROXIM
+void rtw_proxim_enable(_adapter *padapter);
+void rtw_proxim_disable(_adapter *padapter);
+void rtw_proxim_send_packet(_adapter *padapter, u8 *pbuf, u16 len, u8 m_rate);
+#endif /* CONFIG_INTEL_PROXIM */
+
+#define GET_ARP_HTYPE(_arp)	BE_BITS_TO_2BYTE(((u8 *)(_arp)) + 0, 0, 16)
+#define GET_ARP_PTYPE(_arp)	BE_BITS_TO_2BYTE(((u8 *)(_arp)) + 2, 0, 16)
+#define GET_ARP_HLEN(_arp)	BE_BITS_TO_1BYTE(((u8 *)(_arp)) + 4, 0, 8)
+#define GET_ARP_PLEN(_arp)	BE_BITS_TO_1BYTE(((u8 *)(_arp)) + 5, 0, 8)
+#define GET_ARP_OPER(_arp)	BE_BITS_TO_2BYTE(((u8 *)(_arp)) + 6, 0, 16)
+
+#define SET_ARP_HTYPE(_arp, _val)	SET_BITS_TO_BE_2BYTE(((u8 *)(_arp)) + 0, 0, 16, _val)
+#define SET_ARP_PTYPE(_arp, _val)	SET_BITS_TO_BE_2BYTE(((u8 *)(_arp)) + 2, 0, 16, _val)
+#define SET_ARP_HLEN(_arp, _val)	SET_BITS_TO_BE_1BYTE(((u8 *)(_arp)) + 4, 0, 8, _val)
+#define SET_ARP_PLEN(_arp, _val)	SET_BITS_TO_BE_1BYTE(((u8 *)(_arp)) + 5, 0, 8, _val)
+#define SET_ARP_OPER(_arp, _val)	SET_BITS_TO_BE_2BYTE(((u8 *)(_arp)) + 6, 0, 16, _val)
+
+#define ARP_SHA(_arp, _hlen, _plen)	(((u8 *)(_arp)) + 8)
+#define ARP_SPA(_arp, _hlen, _plen)	(((u8 *)(_arp)) + 8 + (_hlen))
+#define ARP_THA(_arp, _hlen, _plen)	(((u8 *)(_arp)) + 8 + (_hlen) + (_plen))
+#define ARP_TPA(_arp, _hlen, _plen)	(((u8 *)(_arp)) + 8 + 2 * (_hlen) + (_plen))
+
+#define ARP_SENDER_MAC_ADDR(_arp)	ARP_SHA(_arp, ETH_ALEN, RTW_IP_ADDR_LEN)
+#define ARP_SENDER_IP_ADDR(_arp)	ARP_SPA(_arp, ETH_ALEN, RTW_IP_ADDR_LEN)
+#define ARP_TARGET_MAC_ADDR(_arp)	ARP_THA(_arp, ETH_ALEN, RTW_IP_ADDR_LEN)
+#define ARP_TARGET_IP_ADDR(_arp)	ARP_TPA(_arp, ETH_ALEN, RTW_IP_ADDR_LEN)
+
+#define GET_ARP_SENDER_MAC_ADDR(_arp, _val)	_rtw_memcpy(_val, ARP_SENDER_MAC_ADDR(_arp), ETH_ALEN)
+#define GET_ARP_SENDER_IP_ADDR(_arp, _val)	_rtw_memcpy(_val, ARP_SENDER_IP_ADDR(_arp), RTW_IP_ADDR_LEN)
+#define GET_ARP_TARGET_MAC_ADDR(_arp, _val)	_rtw_memcpy(_val, ARP_TARGET_MAC_ADDR(_arp), ETH_ALEN)
+#define GET_ARP_TARGET_IP_ADDR(_arp, _val)	_rtw_memcpy(_val, ARP_TARGET_IP_ADDR(_arp), RTW_IP_ADDR_LEN)
+
+#define SET_ARP_SENDER_MAC_ADDR(_arp, _val)	_rtw_memcpy(ARP_SENDER_MAC_ADDR(_arp), _val, ETH_ALEN)
+#define SET_ARP_SENDER_IP_ADDR(_arp, _val)	_rtw_memcpy(ARP_SENDER_IP_ADDR(_arp), _val, RTW_IP_ADDR_LEN)
+#define SET_ARP_TARGET_MAC_ADDR(_arp, _val)	_rtw_memcpy(ARP_TARGET_MAC_ADDR(_arp), _val, ETH_ALEN)
+#define SET_ARP_TARGET_IP_ADDR(_arp, _val)	_rtw_memcpy(ARP_TARGET_IP_ADDR(_arp), _val, RTW_IP_ADDR_LEN)
+
+void dump_arp_pkt(void *sel, u8 *da, u8 *sa, u8 *arp, bool tx);
+
+#define IPV4_SRC(_iphdr)			(((u8 *)(_iphdr)) + 12)
+#define IPV4_DST(_iphdr)			(((u8 *)(_iphdr)) + 16)
+#define GET_IPV4_IHL(_iphdr)		BE_BITS_TO_1BYTE(((u8 *)(_iphdr)) + 0, 0, 4)
+#define GET_IPV4_PROTOCOL(_iphdr)	BE_BITS_TO_1BYTE(((u8 *)(_iphdr)) + 9, 0, 8)
+#define GET_IPV4_SRC(_iphdr)		BE_BITS_TO_4BYTE(((u8 *)(_iphdr)) + 12, 0, 32)
+#define GET_IPV4_DST(_iphdr)		BE_BITS_TO_4BYTE(((u8 *)(_iphdr)) + 16, 0, 32)
+
+#define GET_UDP_SRC(_udphdr)			BE_BITS_TO_2BYTE(((u8 *)(_udphdr)) + 0, 0, 16)
+#define GET_UDP_DST(_udphdr)			BE_BITS_TO_2BYTE(((u8 *)(_udphdr)) + 2, 0, 16)
+
+#define TCP_SRC(_tcphdr)				(((u8 *)(_tcphdr)) + 0)
+#define TCP_DST(_tcphdr)				(((u8 *)(_tcphdr)) + 2)
+#define GET_TCP_SRC(_tcphdr)			BE_BITS_TO_2BYTE(((u8 *)(_tcphdr)) + 0, 0, 16)
+#define GET_TCP_DST(_tcphdr)			BE_BITS_TO_2BYTE(((u8 *)(_tcphdr)) + 2, 0, 16)
+#define GET_TCP_SEQ(_tcphdr)			BE_BITS_TO_4BYTE(((u8 *)(_tcphdr)) + 4, 0, 32)
+#define GET_TCP_ACK_SEQ(_tcphdr)		BE_BITS_TO_4BYTE(((u8 *)(_tcphdr)) + 8, 0, 32)
+#define GET_TCP_DOFF(_tcphdr)			BE_BITS_TO_1BYTE(((u8 *)(_tcphdr)) + 12, 4, 4)
+#define GET_TCP_FIN(_tcphdr)			BE_BITS_TO_1BYTE(((u8 *)(_tcphdr)) + 13, 0, 1)
+#define GET_TCP_SYN(_tcphdr)			BE_BITS_TO_1BYTE(((u8 *)(_tcphdr)) + 13, 1, 1)
+#define GET_TCP_RST(_tcphdr)			BE_BITS_TO_1BYTE(((u8 *)(_tcphdr)) + 13, 2, 1)
+#define GET_TCP_PSH(_tcphdr)			BE_BITS_TO_1BYTE(((u8 *)(_tcphdr)) + 13, 3, 1)
+#define GET_TCP_ACK(_tcphdr)			BE_BITS_TO_1BYTE(((u8 *)(_tcphdr)) + 13, 4, 1)
+#define GET_TCP_URG(_tcphdr)			BE_BITS_TO_1BYTE(((u8 *)(_tcphdr)) + 13, 5, 1)
+#define GET_TCP_ECE(_tcphdr)			BE_BITS_TO_1BYTE(((u8 *)(_tcphdr)) + 13, 6, 1)
+#define GET_TCP_CWR(_tcphdr)			BE_BITS_TO_1BYTE(((u8 *)(_tcphdr)) + 13, 7, 1)
+
+#endif /* __RTL871X_MLME_H_ */
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/include/rtw_mp.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/rtw_mp.h
--- linux-5.6.3/3rdparty/rtl8821ce/include/rtw_mp.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/rtw_mp.h	2020-04-10 16:35:06.851661701 +0300
@@ -0,0 +1,938 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#ifndef _RTW_MP_H_
+#define _RTW_MP_H_
+
+#define RTWPRIV_VER_INFO	1
+
+#define MAX_MP_XMITBUF_SZ	2048
+#define NR_MP_XMITFRAME		8
+
+struct mp_xmit_frame {
+	_list	list;
+
+	struct pkt_attrib attrib;
+
+	_pkt *pkt;
+
+	int frame_tag;
+
+	_adapter *padapter;
+
+#ifdef CONFIG_USB_HCI
+
+	/* insert urb, irp, and irpcnt info below... */
+	/* max frag_cnt = 8 */
+
+	u8 *mem_addr;
+	u32 sz[8];
+
+#if defined(PLATFORM_OS_XP) || defined(PLATFORM_LINUX)
+	PURB pxmit_urb[8];
+#endif
+
+#ifdef PLATFORM_OS_XP
+	PIRP pxmit_irp[8];
+#endif
+
+	u8 bpending[8];
+	sint ac_tag[8];
+	sint last[8];
+	uint irpcnt;
+	uint fragcnt;
+#endif /* CONFIG_USB_HCI */
+
+	uint mem[(MAX_MP_XMITBUF_SZ >> 2)];
+};
+
+struct mp_wiparam {
+	u32 bcompleted;
+	u32 act_type;
+	u32 io_offset;
+	u32 io_value;
+};
+
+typedef void(*wi_act_func)(void *padapter);
+
+#ifdef PLATFORM_WINDOWS
+struct mp_wi_cntx {
+	u8 bmpdrv_unload;
+
+	/* Work Item */
+	NDIS_WORK_ITEM mp_wi;
+	NDIS_EVENT mp_wi_evt;
+	_lock mp_wi_lock;
+	u8 bmp_wi_progress;
+	wi_act_func curractfunc;
+	/* Variable needed in each implementation of CurrActFunc. */
+	struct mp_wiparam param;
+};
+#endif
+
+struct mp_tx {
+	u8 stop;
+	u32 count, sended;
+	u8 payload;
+	struct pkt_attrib attrib;
+	/* struct tx_desc desc; */
+	/* u8 resvdtx[7]; */
+	u8 desc[TXDESC_SIZE];
+	u8 *pallocated_buf;
+	u8 *buf;
+	u32 buf_size, write_size;
+	_thread_hdl_ PktTxThread;
+};
+
+#define MP_MAX_LINES		1000
+#define MP_MAX_LINES_BYTES	256
+
+
+typedef struct _RT_PMAC_PKT_INFO {
+	UCHAR			MCS;
+	UCHAR			Nss;
+	UCHAR			Nsts;
+	UINT			N_sym;
+	UCHAR			SIGA2B3;
+} RT_PMAC_PKT_INFO, *PRT_PMAC_PKT_INFO;
+
+typedef struct _RT_PMAC_TX_INFO {
+	u8			bEnPMacTx:1;		/* 0: Disable PMac 1: Enable PMac */
+	u8			Mode:3;				/* 0: Packet TX 3:Continuous TX */
+	u8			Ntx:4;				/* 0-7 */
+	u8			TX_RATE;			/* MPT_RATE_E */
+	u8			TX_RATE_HEX;
+	u8			TX_SC;
+	u8			bSGI:1;
+	u8			bSPreamble:1;
+	u8			bSTBC:1;
+	u8			bLDPC:1;
+	u8			NDP_sound:1;
+	u8			BandWidth:3;		/* 0: 20 1:40 2:80Mhz */
+	u8			m_STBC;			/* bSTBC + 1 */
+	USHORT			PacketPeriod;
+	UINT		PacketCount;
+	UINT		PacketLength;
+	u8			PacketPattern;
+	USHORT			SFD;
+	u8			SignalField;
+	u8			ServiceField;
+	USHORT			LENGTH;
+	u8			CRC16[2];
+	u8			LSIG[3];
+	u8			HT_SIG[6];
+	u8			VHT_SIG_A[6];
+	u8			VHT_SIG_B[4];
+	u8			VHT_SIG_B_CRC;
+	u8			VHT_Delimiter[4];
+	u8			MacAddress[6];
+} RT_PMAC_TX_INFO, *PRT_PMAC_TX_INFO;
+
+
+typedef VOID (*MPT_WORK_ITEM_HANDLER)(IN PVOID Adapter);
+typedef struct _MPT_CONTEXT {
+	/* Indicate if we have started Mass Production Test. */
+	BOOLEAN			bMassProdTest;
+
+	/* Indicate if the driver is unloading or unloaded. */
+	BOOLEAN			bMptDrvUnload;
+
+	_sema			MPh2c_Sema;
+	_timer			MPh2c_timeout_timer;
+	/* Event used to sync H2c for BT control */
+
+	BOOLEAN		MptH2cRspEvent;
+	BOOLEAN		MptBtC2hEvent;
+	BOOLEAN		bMPh2c_timeout;
+
+	/* 8190 PCI does not support NDIS_WORK_ITEM. */
+	/* Work Item for Mass Production Test. */
+	/* NDIS_WORK_ITEM	MptWorkItem;
+	*	RT_WORK_ITEM		MptWorkItem; */
+	/* Event used to sync the case unloading driver and MptWorkItem is still in progress.
+	*	NDIS_EVENT		MptWorkItemEvent; */
+	/* To protect the following variables.
+	*	NDIS_SPIN_LOCK		MptWorkItemSpinLock; */
+	/* Indicate a MptWorkItem is scheduled and not yet finished. */
+	BOOLEAN			bMptWorkItemInProgress;
+	/* An instance which implements function and context of MptWorkItem. */
+	MPT_WORK_ITEM_HANDLER	CurrMptAct;
+
+	/* 1=Start, 0=Stop from UI. */
+	ULONG			MptTestStart;
+	/* _TEST_MODE, defined in MPT_Req2.h */
+	ULONG			MptTestItem;
+	/* Variable needed in each implementation of CurrMptAct. */
+	ULONG			MptActType;	/* Type of action performed in CurrMptAct. */
+	/* The Offset of IO operation is depend of MptActType. */
+	ULONG			MptIoOffset;
+	/* The Value of IO operation is depend of MptActType. */
+	ULONG			MptIoValue;
+	/* The RfPath of IO operation is depend of MptActType. */
+
+	ULONG			mpt_rf_path;
+
+
+	WIRELESS_MODE		MptWirelessModeToSw;	/* Wireless mode to switch. */
+	u8			MptChannelToSw;	/* Channel to switch. */
+	u8			MptInitGainToSet;	/* Initial gain to set. */
+	/* ULONG			bMptAntennaA;		 */ /* TRUE if we want to use antenna A. */
+	ULONG			MptBandWidth;		/* bandwidth to switch. */
+
+	ULONG			mpt_rate_index;/* rate index. */
+
+	/* Register value kept for Single Carrier Tx test. */
+	u8			btMpCckTxPower;
+	/* Register value kept for Single Carrier Tx test. */
+	u8			btMpOfdmTxPower;
+	/* For MP Tx Power index */
+	u8			TxPwrLevel[4];	/* rf-A, rf-B*/
+	u32			RegTxPwrLimit;
+	/* Content of RCR Regsiter for Mass Production Test. */
+	ULONG			MptRCR;
+	/* TRUE if we only receive packets with specific pattern. */
+	BOOLEAN			bMptFilterPattern;
+	/* Rx OK count, statistics used in Mass Production Test. */
+	ULONG			MptRxOkCnt;
+	/* Rx CRC32 error count, statistics used in Mass Production Test. */
+	ULONG			MptRxCrcErrCnt;
+
+	BOOLEAN			bCckContTx;	/* TRUE if we are in CCK Continuous Tx test. */
+	BOOLEAN			bOfdmContTx;	/* TRUE if we are in OFDM Continuous Tx test. */
+		/* TRUE if we have start Continuous Tx test. */
+	BOOLEAN			is_start_cont_tx;
+
+	/* TRUE if we are in Single Carrier Tx test. */
+	BOOLEAN			bSingleCarrier;
+	/* TRUE if we are in Carrier Suppression Tx Test. */
+
+	BOOLEAN			is_carrier_suppression;
+
+	/* TRUE if we are in Single Tone Tx test. */
+
+	BOOLEAN			is_single_tone;
+
+
+	/* ACK counter asked by K.Y.. */
+	BOOLEAN			bMptEnableAckCounter;
+	ULONG			MptAckCounter;
+
+	/* SD3 Willis For 8192S to save 1T/2T RF table for ACUT	Only fro ACUT delete later ~~~! */
+	/* s1Byte		BufOfLines[2][MAX_LINES_HWCONFIG_TXT][MAX_BYTES_LINE_HWCONFIG_TXT]; */
+	/* s1Byte			BufOfLines[2][MP_MAX_LINES][MP_MAX_LINES_BYTES]; */
+	/* s4Byte			RfReadLine[2]; */
+
+	u8		APK_bound[2];	/* for APK	path A/path B */
+	BOOLEAN		bMptIndexEven;
+
+	u8		backup0xc50;
+	u8		backup0xc58;
+	u8		backup0xc30;
+	u8		backup0x52_RF_A;
+	u8		backup0x52_RF_B;
+
+	u4Byte			backup0x58_RF_A;
+	u4Byte			backup0x58_RF_B;
+
+	u1Byte			h2cReqNum;
+	u1Byte			c2hBuf[32];
+
+	u1Byte          btInBuf[100];
+	ULONG			mptOutLen;
+	u1Byte          mptOutBuf[100];
+	RT_PMAC_TX_INFO	PMacTxInfo;
+	RT_PMAC_PKT_INFO	PMacPktInfo;
+	u8 HWTxmode;
+
+	BOOLEAN			bldpc;
+	BOOLEAN			bstbc;
+} MPT_CONTEXT, *PMPT_CONTEXT;
+/* #endif */
+
+
+/* #define RTPRIV_IOCTL_MP					( SIOCIWFIRSTPRIV + 0x17) */
+enum {
+	WRITE_REG = 1,
+	READ_REG,
+	WRITE_RF,
+	READ_RF,
+	MP_START,
+	MP_STOP,
+	MP_RATE,
+	MP_CHANNEL,
+	MP_CHL_OFFSET,
+	MP_BANDWIDTH,
+	MP_TXPOWER,
+	MP_ANT_TX,
+	MP_ANT_RX,
+	MP_CTX,
+	MP_QUERY,
+	MP_ARX,
+	MP_PSD,
+	MP_PWRTRK,
+	MP_THER,
+	MP_IOCTL,
+	EFUSE_GET,
+	EFUSE_SET,
+	MP_RESET_STATS,
+	MP_DUMP,
+	MP_PHYPARA,
+	MP_SetRFPathSwh,
+	MP_QueryDrvStats,
+	CTA_TEST,
+	MP_DISABLE_BT_COEXIST,
+	MP_PwrCtlDM,
+	MP_GETVER,
+	MP_MON,
+	EFUSE_MASK,
+	EFUSE_FILE,
+	MP_TX,
+	MP_RX,
+	MP_IQK,
+	MP_LCK,
+	MP_HW_TX_MODE,
+	MP_GET_TXPOWER_INX,
+	MP_CUSTOMER_STR,
+	MP_PWRLMT,
+	MP_PWRBYRATE,
+	BT_EFUSE_FILE,
+	MP_SetBT,
+	MP_SWRFPath,
+	MP_NULL,
+#ifdef CONFIG_APPEND_VENDOR_IE_ENABLE
+	VENDOR_IE_SET ,
+	VENDOR_IE_GET ,
+#endif
+#ifdef CONFIG_WOWLAN
+	MP_WOW_ENABLE,
+	MP_WOW_SET_PATTERN,
+#endif
+#ifdef CONFIG_AP_WOWLAN
+	MP_AP_WOW_ENABLE,
+#endif
+	MP_SD_IREAD,
+	MP_SD_IWRITE,
+};
+
+struct mp_priv {
+	_adapter *papdater;
+
+	/* Testing Flag */
+	u32 mode;/* 0 for normal type packet, 1 for loopback packet (16bytes TXCMD) */
+
+	u32 prev_fw_state;
+
+	/* OID cmd handler */
+	struct mp_wiparam workparam;
+	/*	u8 act_in_progress; */
+
+	/* Tx Section */
+	u8 TID;
+	u32 tx_pktcount;
+	u32 pktInterval;
+	u32 pktLength;
+	struct mp_tx tx;
+
+	/* Rx Section */
+	u32 rx_bssidpktcount;
+	u32 rx_pktcount;
+	u32 rx_pktcount_filter_out;
+	u32 rx_crcerrpktcount;
+	u32 rx_pktloss;
+	BOOLEAN  rx_bindicatePkt;
+	struct recv_stat rxstat;
+	BOOLEAN brx_filter_beacon;
+
+	/* RF/BB relative */
+	u8 channel;
+	u8 bandwidth;
+	u8 prime_channel_offset;
+	u8 txpoweridx;
+	u8 rateidx;
+	u32 preamble;
+	/*	u8 modem; */
+	u32 CrystalCap;
+	/*	u32 curr_crystalcap; */
+
+	u16 antenna_tx;
+	u16 antenna_rx;
+	/*	u8 curr_rfpath; */
+
+	u8 check_mp_pkt;
+
+	u8 bSetTxPower;
+	/*	uint ForcedDataRate; */
+	u8 mp_dm;
+	u8 mac_filter[ETH_ALEN];
+	u8 bmac_filter;
+
+	/* RF PATH Setting for WLG WLA BTG BT */
+	u8 rf_path_cfg;
+
+	struct wlan_network mp_network;
+	NDIS_802_11_MAC_ADDRESS network_macaddr;
+
+#ifdef PLATFORM_WINDOWS
+	u32 rx_testcnt;
+	u32 rx_testcnt1;
+	u32 rx_testcnt2;
+	u32 tx_testcnt;
+	u32 tx_testcnt1;
+
+	struct mp_wi_cntx wi_cntx;
+
+	u8 h2c_result;
+	u8 h2c_seqnum;
+	u16 h2c_cmdcode;
+	u8 h2c_resp_parambuf[512];
+	_lock h2c_lock;
+	_lock wkitm_lock;
+	u32 h2c_cmdcnt;
+	NDIS_EVENT h2c_cmd_evt;
+	NDIS_EVENT c2h_set;
+	NDIS_EVENT h2c_clr;
+	NDIS_EVENT cpwm_int;
+
+	NDIS_EVENT scsir_full_evt;
+	NDIS_EVENT scsiw_empty_evt;
+#endif
+
+	u8 *pallocated_mp_xmitframe_buf;
+	u8 *pmp_xmtframe_buf;
+	_queue free_mp_xmitqueue;
+	u32 free_mp_xmitframe_cnt;
+	BOOLEAN bSetRxBssid;
+	BOOLEAN bTxBufCkFail;
+	BOOLEAN bRTWSmbCfg;
+	BOOLEAN bloopback;
+	BOOLEAN bloadefusemap;
+	BOOLEAN bloadBTefusemap;
+
+	MPT_CONTEXT	mpt_ctx;
+
+
+	u8		*TXradomBuffer;
+	u8		CureFuseBTCoex;
+};
+
+typedef struct _IOCMD_STRUCT_ {
+	u8	cmdclass;
+	u16	value;
+	u8	index;
+} IOCMD_STRUCT;
+
+struct rf_reg_param {
+	u32 path;
+	u32 offset;
+	u32 value;
+};
+
+struct bb_reg_param {
+	u32 offset;
+	u32 value;
+};
+
+typedef struct _MP_FIRMWARE {
+	FIRMWARE_SOURCE eFWSource;
+#ifdef CONFIG_EMBEDDED_FWIMG
+	u8		*szFwBuffer;
+#else
+	u8			szFwBuffer[0x8000];
+#endif
+	u32		ulFwLength;
+} RT_MP_FIRMWARE, *PRT_MP_FIRMWARE;
+
+
+
+
+/* *********************************************************************** */
+
+#define LOWER	_TRUE
+#define RAISE	_FALSE
+
+/* Hardware Registers */
+#if 0
+#if 0
+#define IOCMD_CTRL_REG			0x102502C0
+#define IOCMD_DATA_REG			0x102502C4
+#else
+#define IOCMD_CTRL_REG			0x10250370
+#define IOCMD_DATA_REG			0x10250374
+#endif
+
+#define IOCMD_GET_THERMAL_METER		0xFD000028
+
+#define IOCMD_CLASS_BB_RF		0xF0
+#define IOCMD_BB_READ_IDX		0x00
+#define IOCMD_BB_WRITE_IDX		0x01
+#define IOCMD_RF_READ_IDX		0x02
+#define IOCMD_RF_WRIT_IDX		0x03
+#endif
+#define BB_REG_BASE_ADDR		0x800
+
+/* MP variables */
+#if 0
+#define _2MAC_MODE_	0
+#define _LOOPBOOK_MODE_	1
+#endif
+typedef enum _MP_MODE_ {
+	MP_OFF,
+	MP_ON,
+	MP_ERR,
+	MP_CONTINUOUS_TX,
+	MP_SINGLE_CARRIER_TX,
+	MP_CARRIER_SUPPRISSION_TX,
+	MP_SINGLE_TONE_TX,
+	MP_PACKET_TX,
+	MP_PACKET_RX
+} MP_MODE;
+
+typedef enum _TEST_MODE {
+	TEST_NONE                 ,
+	PACKETS_TX                ,
+	PACKETS_RX                ,
+	CONTINUOUS_TX             ,
+	OFDM_Single_Tone_TX       ,
+	CCK_Carrier_Suppression_TX
+} TEST_MODE;
+
+
+typedef enum _MPT_BANDWIDTH {
+	MPT_BW_20MHZ = 0,
+	MPT_BW_40MHZ_DUPLICATE = 1,
+	MPT_BW_40MHZ_ABOVE = 2,
+	MPT_BW_40MHZ_BELOW = 3,
+	MPT_BW_40MHZ = 4,
+	MPT_BW_80MHZ = 5,
+	MPT_BW_80MHZ_20_ABOVE = 6,
+	MPT_BW_80MHZ_20_BELOW = 7,
+	MPT_BW_80MHZ_20_BOTTOM = 8,
+	MPT_BW_80MHZ_20_TOP = 9,
+	MPT_BW_80MHZ_40_ABOVE = 10,
+	MPT_BW_80MHZ_40_BELOW = 11,
+} MPT_BANDWIDTHE, *PMPT_BANDWIDTH;
+
+#define MAX_RF_PATH_NUMS	RF_PATH_MAX
+
+
+extern u8 mpdatarate[NumRates];
+
+/* MP set force data rate base on the definition. */
+typedef enum _MPT_RATE_INDEX {
+	/* CCK rate. */
+	MPT_RATE_1M = 1 ,	/* 0 */
+	MPT_RATE_2M,
+	MPT_RATE_55M,
+	MPT_RATE_11M,	/* 3 */
+
+	/* OFDM rate. */
+	MPT_RATE_6M,	/* 4 */
+	MPT_RATE_9M,
+	MPT_RATE_12M,
+	MPT_RATE_18M,
+	MPT_RATE_24M,
+	MPT_RATE_36M,
+	MPT_RATE_48M,
+	MPT_RATE_54M,	/* 11 */
+
+	/* HT rate. */
+	MPT_RATE_MCS0,	/* 12 */
+	MPT_RATE_MCS1,
+	MPT_RATE_MCS2,
+	MPT_RATE_MCS3,
+	MPT_RATE_MCS4,
+	MPT_RATE_MCS5,
+	MPT_RATE_MCS6,
+	MPT_RATE_MCS7,	/* 19 */
+	MPT_RATE_MCS8,
+	MPT_RATE_MCS9,
+	MPT_RATE_MCS10,
+	MPT_RATE_MCS11,
+	MPT_RATE_MCS12,
+	MPT_RATE_MCS13,
+	MPT_RATE_MCS14,
+	MPT_RATE_MCS15,	/* 27 */
+	MPT_RATE_MCS16,
+	MPT_RATE_MCS17, /*  #29 */
+	MPT_RATE_MCS18,
+	MPT_RATE_MCS19,
+	MPT_RATE_MCS20,
+	MPT_RATE_MCS21,
+	MPT_RATE_MCS22, /*  #34 */
+	MPT_RATE_MCS23,
+	MPT_RATE_MCS24,
+	MPT_RATE_MCS25,
+	MPT_RATE_MCS26,
+	MPT_RATE_MCS27, /*  #39 */
+	MPT_RATE_MCS28, /*  #40 */
+	MPT_RATE_MCS29, /*  #41 */
+	MPT_RATE_MCS30, /*  #42 */
+	MPT_RATE_MCS31, /*  #43 */
+	/* VHT rate. Total: 20*/
+	MPT_RATE_VHT1SS_MCS0 = 100,/*  #44*/
+	MPT_RATE_VHT1SS_MCS1, /*  # */
+	MPT_RATE_VHT1SS_MCS2,
+	MPT_RATE_VHT1SS_MCS3,
+	MPT_RATE_VHT1SS_MCS4,
+	MPT_RATE_VHT1SS_MCS5,
+	MPT_RATE_VHT1SS_MCS6, /*  # */
+	MPT_RATE_VHT1SS_MCS7,
+	MPT_RATE_VHT1SS_MCS8,
+	MPT_RATE_VHT1SS_MCS9, /* #53 */
+	MPT_RATE_VHT2SS_MCS0, /* #54 */
+	MPT_RATE_VHT2SS_MCS1,
+	MPT_RATE_VHT2SS_MCS2,
+	MPT_RATE_VHT2SS_MCS3,
+	MPT_RATE_VHT2SS_MCS4,
+	MPT_RATE_VHT2SS_MCS5,
+	MPT_RATE_VHT2SS_MCS6,
+	MPT_RATE_VHT2SS_MCS7,
+	MPT_RATE_VHT2SS_MCS8,
+	MPT_RATE_VHT2SS_MCS9, /* #63 */
+	MPT_RATE_VHT3SS_MCS0,
+	MPT_RATE_VHT3SS_MCS1,
+	MPT_RATE_VHT3SS_MCS2,
+	MPT_RATE_VHT3SS_MCS3,
+	MPT_RATE_VHT3SS_MCS4,
+	MPT_RATE_VHT3SS_MCS5,
+	MPT_RATE_VHT3SS_MCS6, /*  #126 */
+	MPT_RATE_VHT3SS_MCS7,
+	MPT_RATE_VHT3SS_MCS8,
+	MPT_RATE_VHT3SS_MCS9,
+	MPT_RATE_VHT4SS_MCS0,
+	MPT_RATE_VHT4SS_MCS1, /*  #131 */
+	MPT_RATE_VHT4SS_MCS2,
+	MPT_RATE_VHT4SS_MCS3,
+	MPT_RATE_VHT4SS_MCS4,
+	MPT_RATE_VHT4SS_MCS5,
+	MPT_RATE_VHT4SS_MCS6, /*  #136 */
+	MPT_RATE_VHT4SS_MCS7,
+	MPT_RATE_VHT4SS_MCS8,
+	MPT_RATE_VHT4SS_MCS9,
+	MPT_RATE_LAST
+} MPT_RATE_E, *PMPT_RATE_E;
+
+#define MAX_TX_PWR_INDEX_N_MODE 64	/* 0x3F */
+
+#define MPT_IS_CCK_RATE(_value)		(MPT_RATE_1M <= _value && _value <= MPT_RATE_11M)
+#define MPT_IS_OFDM_RATE(_value)	(MPT_RATE_6M <= _value && _value <= MPT_RATE_54M)
+#define MPT_IS_HT_RATE(_value)		(MPT_RATE_MCS0 <= _value && _value <= MPT_RATE_MCS31)
+#define MPT_IS_HT_1S_RATE(_value)	(MPT_RATE_MCS0 <= _value && _value <= MPT_RATE_MCS7)
+#define MPT_IS_HT_2S_RATE(_value)	(MPT_RATE_MCS8 <= _value && _value <= MPT_RATE_MCS15)
+#define MPT_IS_HT_3S_RATE(_value)	(MPT_RATE_MCS16 <= _value && _value <= MPT_RATE_MCS23)
+#define MPT_IS_HT_4S_RATE(_value)	(MPT_RATE_MCS24 <= _value && _value <= MPT_RATE_MCS31)
+
+#define MPT_IS_VHT_RATE(_value)		(MPT_RATE_VHT1SS_MCS0 <= _value && _value <= MPT_RATE_VHT4SS_MCS9)
+#define MPT_IS_VHT_1S_RATE(_value)	(MPT_RATE_VHT1SS_MCS0 <= _value && _value <= MPT_RATE_VHT1SS_MCS9)
+#define MPT_IS_VHT_2S_RATE(_value)	(MPT_RATE_VHT2SS_MCS0 <= _value && _value <= MPT_RATE_VHT2SS_MCS9)
+#define MPT_IS_VHT_3S_RATE(_value)	(MPT_RATE_VHT3SS_MCS0 <= _value && _value <= MPT_RATE_VHT3SS_MCS9)
+#define MPT_IS_VHT_4S_RATE(_value)	(MPT_RATE_VHT4SS_MCS0 <= _value && _value <= MPT_RATE_VHT4SS_MCS9)
+
+#define MPT_IS_2SS_RATE(_rate) ((MPT_RATE_MCS8 <= _rate && _rate <= MPT_RATE_MCS15) || \
+	(MPT_RATE_VHT2SS_MCS0 <= _rate && _rate <= MPT_RATE_VHT2SS_MCS9))
+#define MPT_IS_3SS_RATE(_rate) ((MPT_RATE_MCS16 <= _rate && _rate <= MPT_RATE_MCS23) || \
+	(MPT_RATE_VHT3SS_MCS0 <= _rate && _rate <= MPT_RATE_VHT3SS_MCS9))
+#define MPT_IS_4SS_RATE(_rate) ((MPT_RATE_MCS24 <= _rate && _rate <= MPT_RATE_MCS31) || \
+	(MPT_RATE_VHT4SS_MCS0 <= _rate && _rate <= MPT_RATE_VHT4SS_MCS9))
+
+typedef enum _POWER_MODE_ {
+	POWER_LOW = 0,
+	POWER_NORMAL
+} POWER_MODE;
+
+/* The following enumeration is used to define the value of Reg0xD00[30:28] or JaguarReg0x914[18:16]. */
+typedef enum _OFDM_TX_MODE {
+	OFDM_ALL_OFF		= 0,
+	OFDM_ContinuousTx	= 1,
+	OFDM_SingleCarrier	= 2,
+	OFDM_SingleTone	= 4,
+} OFDM_TX_MODE;
+
+
+#define RX_PKT_BROADCAST	1
+#define RX_PKT_DEST_ADDR	2
+#define RX_PKT_PHY_MATCH	3
+
+typedef enum _ENCRY_CTRL_STATE_ {
+	HW_CONTROL,		/* hw encryption& decryption */
+	SW_CONTROL,		/* sw encryption& decryption */
+	HW_ENCRY_SW_DECRY,	/* hw encryption & sw decryption */
+	SW_ENCRY_HW_DECRY	/* sw encryption & hw decryption */
+} ENCRY_CTRL_STATE;
+
+typedef enum	_MPT_TXPWR_DEF {
+	MPT_CCK,
+	MPT_OFDM, /* L and HT OFDM */
+	MPT_OFDM_AND_HT,
+	MPT_HT,
+	MPT_VHT
+} MPT_TXPWR_DEF;
+
+
+#define IS_MPT_HT_RATE(_rate)			(_rate >= MPT_RATE_MCS0 && _rate <= MPT_RATE_MCS31)
+#define IS_MPT_VHT_RATE(_rate)			(_rate >= MPT_RATE_VHT1SS_MCS0 && _rate <= MPT_RATE_VHT4SS_MCS9)
+#define IS_MPT_CCK_RATE(_rate)			(_rate >= MPT_RATE_1M && _rate <= MPT_RATE_11M)
+#define IS_MPT_OFDM_RATE(_rate)			(_rate >= MPT_RATE_6M && _rate <= MPT_RATE_54M)
+/*************************************************************************/
+#if 0
+extern struct mp_xmit_frame *alloc_mp_xmitframe(struct mp_priv *pmp_priv);
+extern int free_mp_xmitframe(struct xmit_priv *pxmitpriv, struct mp_xmit_frame *pmp_xmitframe);
+#endif
+
+extern s32 init_mp_priv(PADAPTER padapter);
+extern void free_mp_priv(struct mp_priv *pmp_priv);
+extern s32 MPT_InitializeAdapter(PADAPTER padapter, u8 Channel);
+extern void MPT_DeInitAdapter(PADAPTER padapter);
+extern s32 mp_start_test(PADAPTER padapter);
+extern void mp_stop_test(PADAPTER padapter);
+
+extern u32 _read_rfreg(PADAPTER padapter, u8 rfpath, u32 addr, u32 bitmask);
+extern void _write_rfreg(PADAPTER padapter, u8 rfpath, u32 addr, u32 bitmask, u32 val);
+
+extern u32 read_macreg(_adapter *padapter, u32 addr, u32 sz);
+extern void write_macreg(_adapter *padapter, u32 addr, u32 val, u32 sz);
+extern u32 read_bbreg(_adapter *padapter, u32 addr, u32 bitmask);
+extern void write_bbreg(_adapter *padapter, u32 addr, u32 bitmask, u32 val);
+extern u32 read_rfreg(PADAPTER padapter, u8 rfpath, u32 addr);
+extern void write_rfreg(PADAPTER padapter, u8 rfpath, u32 addr, u32 val);
+#ifdef CONFIG_ANTENNA_DIVERSITY
+u8 rtw_mp_set_antdiv(PADAPTER padapter, BOOLEAN bMain);
+#endif
+void	SetChannel(PADAPTER pAdapter);
+void	SetBandwidth(PADAPTER pAdapter);
+int	SetTxPower(PADAPTER pAdapter);
+void	SetAntenna(PADAPTER pAdapter);
+void	SetDataRate(PADAPTER pAdapter);
+void	SetAntenna(PADAPTER pAdapter);
+s32	SetThermalMeter(PADAPTER pAdapter, u8 target_ther);
+void	GetThermalMeter(PADAPTER pAdapter, u8 *value);
+void	SetContinuousTx(PADAPTER pAdapter, u8 bStart);
+void	SetSingleCarrierTx(PADAPTER pAdapter, u8 bStart);
+void	SetSingleToneTx(PADAPTER pAdapter, u8 bStart);
+void	SetCarrierSuppressionTx(PADAPTER pAdapter, u8 bStart);
+void	PhySetTxPowerLevel(PADAPTER pAdapter);
+void	fill_txdesc_for_mp(PADAPTER padapter, u8 *ptxdesc);
+void	SetPacketTx(PADAPTER padapter);
+void	SetPacketRx(PADAPTER pAdapter, u8 bStartRx, u8 bAB);
+void	ResetPhyRxPktCount(PADAPTER pAdapter);
+u32	GetPhyRxPktReceived(PADAPTER pAdapter);
+u32	GetPhyRxPktCRC32Error(PADAPTER pAdapter);
+s32	SetPowerTracking(PADAPTER padapter, u8 enable);
+void	GetPowerTracking(PADAPTER padapter, u8 *enable);
+u32	mp_query_psd(PADAPTER pAdapter, u8 *data);
+void	rtw_mp_trigger_iqk(PADAPTER padapter);
+void	rtw_mp_trigger_lck(PADAPTER padapter);
+u8 rtw_mp_mode_check(PADAPTER padapter);
+
+
+void hal_mpt_SwitchRfSetting(PADAPTER pAdapter);
+s32 hal_mpt_SetPowerTracking(PADAPTER padapter, u8 enable);
+void hal_mpt_GetPowerTracking(PADAPTER padapter, u8 *enable);
+void hal_mpt_CCKTxPowerAdjust(PADAPTER Adapter, BOOLEAN bInCH14);
+void hal_mpt_SetChannel(PADAPTER pAdapter);
+void hal_mpt_SetBandwidth(PADAPTER pAdapter);
+void hal_mpt_SetTxPower(PADAPTER pAdapter);
+void hal_mpt_SetDataRate(PADAPTER pAdapter);
+void hal_mpt_SetAntenna(PADAPTER pAdapter);
+s32 hal_mpt_SetThermalMeter(PADAPTER pAdapter, u8 target_ther);
+void hal_mpt_TriggerRFThermalMeter(PADAPTER pAdapter);
+u8 hal_mpt_ReadRFThermalMeter(PADAPTER pAdapter);
+void hal_mpt_GetThermalMeter(PADAPTER pAdapter, u8 *value);
+void hal_mpt_SetContinuousTx(PADAPTER pAdapter, u8 bStart);
+void hal_mpt_SetSingleCarrierTx(PADAPTER pAdapter, u8 bStart);
+void hal_mpt_SetSingleToneTx(PADAPTER pAdapter, u8 bStart);
+void hal_mpt_SetCarrierSuppressionTx(PADAPTER pAdapter, u8 bStart);
+void mpt_ProSetPMacTx(PADAPTER	Adapter);
+void MP_PHY_SetRFPathSwitch(PADAPTER pAdapter , BOOLEAN bMain);
+void mp_phy_switch_rf_path_set(PADAPTER pAdapter , u8 *pstate);
+u8 MP_PHY_QueryRFPathSwitch(PADAPTER pAdapter);
+ULONG mpt_ProQueryCalTxPower(PADAPTER	pAdapter, u8 RfPath);
+void MPT_PwrCtlDM(PADAPTER padapter, u32 bstart);
+u8 mpt_to_mgnt_rate(u32	MptRateIdx);
+u8 rtw_mpRateParseFunc(PADAPTER pAdapter, u8 *targetStr);
+u32 mp_join(PADAPTER padapter, u8 mode);
+u32 hal_mpt_query_phytxok(PADAPTER	pAdapter);
+
+void
+PMAC_Get_Pkt_Param(
+	PRT_PMAC_TX_INFO	pPMacTxInfo,
+	PRT_PMAC_PKT_INFO	pPMacPktInfo
+);
+void
+CCK_generator(
+	PRT_PMAC_TX_INFO	pPMacTxInfo,
+	PRT_PMAC_PKT_INFO	pPMacPktInfo
+);
+void
+PMAC_Nsym_generator(
+	PRT_PMAC_TX_INFO	pPMacTxInfo,
+	PRT_PMAC_PKT_INFO	pPMacPktInfo
+);
+void
+L_SIG_generator(
+	UINT	N_SYM,		/* Max: 750*/
+	PRT_PMAC_TX_INFO	pPMacTxInfo,
+	PRT_PMAC_PKT_INFO	pPMacPktInfo
+);
+
+void HT_SIG_generator(
+	PRT_PMAC_TX_INFO	pPMacTxInfo,
+	PRT_PMAC_PKT_INFO	pPMacPktInfo);
+
+void VHT_SIG_A_generator(
+	PRT_PMAC_TX_INFO	pPMacTxInfo,
+	PRT_PMAC_PKT_INFO	pPMacPktInfo);
+
+void VHT_SIG_B_generator(
+	PRT_PMAC_TX_INFO	pPMacTxInfo);
+
+void VHT_Delimiter_generator(
+	PRT_PMAC_TX_INFO	pPMacTxInfo);
+
+
+int rtw_mp_write_reg(struct net_device *dev,
+		struct iw_request_info *info,
+		struct iw_point *wrqu, char *extra);
+int rtw_mp_read_reg(struct net_device *dev,
+		struct iw_request_info *info,
+		struct iw_point *wrqu, char *extra);
+int rtw_mp_write_rf(struct net_device *dev,
+		struct iw_request_info *info,
+		struct iw_point *wrqu, char *extra);
+int rtw_mp_read_rf(struct net_device *dev,
+		struct iw_request_info *info,
+		struct iw_point *wrqu, char *extra);
+int rtw_mp_start(struct net_device *dev,
+		struct iw_request_info *info,
+		struct iw_point *wrqu, char *extra);
+int rtw_mp_stop(struct net_device *dev,
+		struct iw_request_info *info,
+		struct iw_point *wrqu, char *extra);
+int rtw_mp_rate(struct net_device *dev,
+		struct iw_request_info *info,
+		struct iw_point *wrqu, char *extra);
+int rtw_mp_channel(struct net_device *dev,
+		struct iw_request_info *info,
+		struct iw_point *wrqu, char *extra);
+int rtw_mp_ch_offset(struct net_device *dev,
+		struct iw_request_info *info,
+		struct iw_point *wrqu, char *extra);
+int rtw_mp_bandwidth(struct net_device *dev,
+		struct iw_request_info *info,
+		struct iw_point *wrqu, char *extra);
+int rtw_mp_txpower_index(struct net_device *dev,
+		struct iw_request_info *info,
+		struct iw_point *wrqu, char *extra);
+int rtw_mp_txpower(struct net_device *dev,
+		struct iw_request_info *info,
+		struct iw_point *wrqu, char *extra);
+int rtw_mp_txpower(struct net_device *dev,
+		struct iw_request_info *info,
+		struct iw_point *wrqu, char *extra);
+int rtw_mp_ant_tx(struct net_device *dev,
+		struct iw_request_info *info,
+		struct iw_point *wrqu, char *extra);
+int rtw_mp_ant_rx(struct net_device *dev,
+		struct iw_request_info *info,
+		struct iw_point *wrqu, char *extra);
+int rtw_set_ctx_destAddr(struct net_device *dev,
+		struct iw_request_info *info,
+		struct iw_point *wrqu, char *extra);
+int rtw_mp_ctx(struct net_device *dev,
+		struct iw_request_info *info,
+		struct iw_point *wrqu, char *extra);
+int rtw_mp_disable_bt_coexist(struct net_device *dev,
+		struct iw_request_info *info,
+		union iwreq_data *wrqu, char *extra);
+int rtw_mp_disable_bt_coexist(struct net_device *dev,
+		struct iw_request_info *info,
+		union iwreq_data *wrqu, char *extra);
+int rtw_mp_arx(struct net_device *dev,
+		struct iw_request_info *info,
+		struct iw_point *wrqu, char *extra);
+int rtw_mp_trx_query(struct net_device *dev,
+		struct iw_request_info *info,
+		struct iw_point *wrqu, char *extra);
+int rtw_mp_pwrtrk(struct net_device *dev,
+		struct iw_request_info *info,
+		struct iw_point *wrqu, char *extra);
+int rtw_mp_psd(struct net_device *dev,
+		struct iw_request_info *info,
+		struct iw_point *wrqu, char *extra);
+int rtw_mp_thermal(struct net_device *dev,
+		struct iw_request_info *info,
+		struct iw_point *wrqu, char *extra);
+int rtw_mp_reset_stats(struct net_device *dev,
+		struct iw_request_info *info,
+		struct iw_point *wrqu, char *extra);
+int rtw_mp_dump(struct net_device *dev,
+		struct iw_request_info *info,
+		struct iw_point *wrqu, char *extra);
+int rtw_mp_phypara(struct net_device *dev,
+		struct iw_request_info *info,
+		struct iw_point *wrqu, char *extra);
+int rtw_mp_SetRFPath(struct net_device *dev,
+		struct iw_request_info *info,
+		struct iw_point *wrqu, char *extra);
+int rtw_mp_switch_rf_path(struct net_device *dev,
+			struct iw_request_info *info,
+			struct iw_point *wrqu, char *extra);
+int rtw_mp_QueryDrv(struct net_device *dev,
+		struct iw_request_info *info,
+		union iwreq_data *wrqu, char *extra);
+int rtw_mp_PwrCtlDM(struct net_device *dev,
+		struct iw_request_info *info,
+		struct iw_point *wrqu, char *extra);
+int rtw_mp_getver(struct net_device *dev,
+		struct iw_request_info *info,
+		union iwreq_data *wrqu, char *extra);
+int rtw_mp_mon(struct net_device *dev,
+		struct iw_request_info *info,
+		union iwreq_data *wrqu, char *extra);
+int rtw_mp_pwrlmt(struct net_device *dev,
+		struct iw_request_info *info,
+		union iwreq_data *wrqu, char *extra);
+int rtw_mp_pwrbyrate(struct net_device *dev,
+		struct iw_request_info *info,
+		union iwreq_data *wrqu, char *extra);
+int rtw_efuse_mask_file(struct net_device *dev,
+		struct iw_request_info *info,
+		union iwreq_data *wrqu, char *extra);
+int rtw_efuse_file_map(struct net_device *dev,
+		struct iw_request_info *info,
+		union iwreq_data *wrqu, char *extra);
+int rtw_bt_efuse_file_map(struct net_device *dev,
+		struct iw_request_info *info,
+		union iwreq_data *wrqu, char *extra);
+int rtw_mp_SetBT(struct net_device *dev,
+		struct iw_request_info *info,
+		union iwreq_data *wrqu, char *extra);
+int rtw_mp_pretx_proc(PADAPTER padapter, u8 bStartTest, char *extra);
+int rtw_mp_tx(struct net_device *dev,
+		struct iw_request_info *info,
+		union iwreq_data *wrqu, char *extra);
+int rtw_mp_rx(struct net_device *dev,
+		struct iw_request_info *info,
+		union iwreq_data *wrqu, char *extra);
+int rtw_mp_hwtx(struct net_device *dev,
+		struct iw_request_info *info,
+		union iwreq_data *wrqu, char *extra);
+u8 HwRateToMPTRate(u8 rate);
+int rtw_mp_iqk(struct net_device *dev,
+		 struct iw_request_info *info,
+		 struct iw_point *wrqu, char *extra);
+int rtw_mp_lck(struct net_device *dev,
+		struct iw_request_info *info,
+		struct iw_point *wrqu, char *extra);
+#endif /* _RTW_MP_H_ */
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/include/rtw_mp_ioctl.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/rtw_mp_ioctl.h
--- linux-5.6.3/3rdparty/rtl8821ce/include/rtw_mp_ioctl.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/rtw_mp_ioctl.h	2020-04-10 16:35:06.852661748 +0300
@@ -0,0 +1,570 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#ifndef _RTW_MP_IOCTL_H_
+#define _RTW_MP_IOCTL_H_
+
+#include <mp_custom_oid.h>
+#include <rtw_mp.h>
+
+#if 0
+#define TESTFWCMDNUMBER			1000000
+#define TEST_H2CINT_WAIT_TIME		500
+#define TEST_C2HINT_WAIT_TIME		500
+#define HCI_TEST_SYSCFG_HWMASK		1
+#define _BUSCLK_40M			(4 << 2)
+#endif
+/* ------------------------------------------------------------------------------ */
+typedef struct CFG_DBG_MSG_STRUCT {
+	u32 DebugLevel;
+	u32 DebugComponent_H32;
+	u32 DebugComponent_L32;
+} CFG_DBG_MSG_STRUCT, *PCFG_DBG_MSG_STRUCT;
+
+typedef struct _RW_REG {
+	u32 offset;
+	u32 width;
+	u32 value;
+} mp_rw_reg, RW_Reg, *pRW_Reg;
+
+/* for OID_RT_PRO_READ16_EEPROM & OID_RT_PRO_WRITE16_EEPROM */
+typedef struct _EEPROM_RW_PARAM {
+	u32 offset;
+	u16 value;
+} eeprom_rw_param, EEPROM_RWParam, *pEEPROM_RWParam;
+
+typedef struct _EFUSE_ACCESS_STRUCT_ {
+	u16	start_addr;
+	u16	cnts;
+	u8	data[0];
+} EFUSE_ACCESS_STRUCT, *PEFUSE_ACCESS_STRUCT;
+
+typedef struct _BURST_RW_REG {
+	u32 offset;
+	u32 len;
+	u8 Data[256];
+} burst_rw_reg, Burst_RW_Reg, *pBurst_RW_Reg;
+
+typedef struct _USB_VendorReq {
+	u8	bRequest;
+	u16	wValue;
+	u16	wIndex;
+	u16	wLength;
+	u8	u8Dir;/* 0:OUT, 1:IN */
+	u8	u8InData;
+} usb_vendor_req, USB_VendorReq, *pUSB_VendorReq;
+
+typedef struct _DR_VARIABLE_STRUCT_ {
+	u8 offset;
+	u32 variable;
+} DR_VARIABLE_STRUCT;
+
+/* int mp_start_joinbss(_adapter *padapter, NDIS_802_11_SSID *pssid); */
+
+/* void _irqlevel_changed_(_irqL *irqlevel, BOOLEANunsigned char bLower); */
+#ifdef PLATFORM_OS_XP
+static void _irqlevel_changed_(_irqL *irqlevel, u8 bLower)
+{
+
+	if (bLower == LOWER) {
+		*irqlevel = KeGetCurrentIrql();
+
+		if (*irqlevel > PASSIVE_LEVEL)
+			KeLowerIrql(PASSIVE_LEVEL);
+	} else {
+		if (KeGetCurrentIrql() == PASSIVE_LEVEL)
+			KeRaiseIrql(DISPATCH_LEVEL, irqlevel);
+	}
+
+}
+#else
+#define _irqlevel_changed_(a, b)
+#endif
+
+/* oid_rtl_seg_81_80_00 */
+NDIS_STATUS oid_rt_pro_set_data_rate_hdl(struct oid_par_priv *poid_par_priv);
+NDIS_STATUS oid_rt_pro_start_test_hdl(struct oid_par_priv *poid_par_priv);
+NDIS_STATUS oid_rt_pro_stop_test_hdl(struct oid_par_priv *poid_par_priv);
+NDIS_STATUS oid_rt_pro_set_channel_direct_call_hdl(struct oid_par_priv *poid_par_priv);
+NDIS_STATUS oid_rt_pro_set_antenna_bb_hdl(struct oid_par_priv *poid_par_priv);
+NDIS_STATUS oid_rt_pro_set_tx_power_control_hdl(struct oid_par_priv *poid_par_priv);
+/* oid_rtl_seg_81_80_20 */
+NDIS_STATUS oid_rt_pro_query_tx_packet_sent_hdl(struct oid_par_priv *poid_par_priv);
+NDIS_STATUS oid_rt_pro_query_rx_packet_received_hdl(struct oid_par_priv *poid_par_priv);
+NDIS_STATUS oid_rt_pro_query_rx_packet_crc32_error_hdl(struct oid_par_priv *poid_par_priv);
+
+NDIS_STATUS oid_rt_pro_reset_tx_packet_sent_hdl(struct oid_par_priv *poid_par_priv);
+NDIS_STATUS oid_rt_pro_reset_rx_packet_received_hdl(struct oid_par_priv *poid_par_priv);
+NDIS_STATUS oid_rt_pro_set_modulation_hdl(struct oid_par_priv *poid_par_priv);
+
+NDIS_STATUS oid_rt_pro_set_continuous_tx_hdl(struct oid_par_priv *poid_par_priv);
+NDIS_STATUS oid_rt_pro_set_single_carrier_tx_hdl(struct oid_par_priv *poid_par_priv);
+NDIS_STATUS oid_rt_pro_set_carrier_suppression_tx_hdl(struct oid_par_priv *poid_par_priv);
+NDIS_STATUS oid_rt_pro_set_single_tone_tx_hdl(struct oid_par_priv *poid_par_priv);
+
+
+/* oid_rtl_seg_81_87 */
+NDIS_STATUS oid_rt_pro_write_bb_reg_hdl(struct oid_par_priv *poid_par_priv);
+NDIS_STATUS oid_rt_pro_read_bb_reg_hdl(struct oid_par_priv *poid_par_priv);
+
+NDIS_STATUS oid_rt_pro_write_rf_reg_hdl(struct oid_par_priv *poid_par_priv);
+NDIS_STATUS oid_rt_pro_read_rf_reg_hdl(struct oid_par_priv *poid_par_priv);
+
+
+/* oid_rtl_seg_81_85 */
+NDIS_STATUS oid_rt_wireless_mode_hdl(struct oid_par_priv *poid_par_priv);
+
+
+/* oid_rtl_seg_87_11_00 */
+NDIS_STATUS oid_rt_pro8711_join_bss_hdl(struct oid_par_priv *poid_par_priv);
+NDIS_STATUS oid_rt_pro_read_register_hdl(struct oid_par_priv *poid_par_priv);
+NDIS_STATUS oid_rt_pro_write_register_hdl(struct oid_par_priv *poid_par_priv);
+NDIS_STATUS oid_rt_pro_burst_read_register_hdl(struct oid_par_priv *poid_par_priv);
+NDIS_STATUS oid_rt_pro_burst_write_register_hdl(struct oid_par_priv *poid_par_priv);
+NDIS_STATUS oid_rt_pro_write_txcmd_hdl(struct oid_par_priv *poid_par_priv);
+NDIS_STATUS oid_rt_pro_read16_eeprom_hdl(struct oid_par_priv *poid_par_priv);
+NDIS_STATUS oid_rt_pro_write16_eeprom_hdl(struct oid_par_priv *poid_par_priv);
+NDIS_STATUS oid_rt_pro8711_wi_poll_hdl(struct oid_par_priv *poid_par_priv);
+NDIS_STATUS oid_rt_pro8711_pkt_loss_hdl(struct oid_par_priv *poid_par_priv);
+NDIS_STATUS oid_rt_rd_attrib_mem_hdl(struct oid_par_priv *poid_par_priv);
+NDIS_STATUS oid_rt_wr_attrib_mem_hdl(struct oid_par_priv *poid_par_priv);
+NDIS_STATUS  oid_rt_pro_set_rf_intfs_hdl(struct oid_par_priv *poid_par_priv);
+NDIS_STATUS oid_rt_poll_rx_status_hdl(struct oid_par_priv *poid_par_priv);
+/* oid_rtl_seg_87_11_20 */
+NDIS_STATUS oid_rt_pro_cfg_debug_message_hdl(struct oid_par_priv *poid_par_priv);
+NDIS_STATUS oid_rt_pro_set_data_rate_ex_hdl(struct oid_par_priv *poid_par_priv);
+NDIS_STATUS oid_rt_pro_set_basic_rate_hdl(struct oid_par_priv *poid_par_priv);
+NDIS_STATUS oid_rt_pro_read_tssi_hdl(struct oid_par_priv *poid_par_priv);
+NDIS_STATUS oid_rt_pro_set_power_tracking_hdl(struct oid_par_priv *poid_par_priv);
+/* oid_rtl_seg_87_11_50 */
+NDIS_STATUS oid_rt_pro_qry_pwrstate_hdl(struct oid_par_priv *poid_par_priv);
+NDIS_STATUS oid_rt_pro_set_pwrstate_hdl(struct oid_par_priv *poid_par_priv);
+/* oid_rtl_seg_87_11_F0 */
+NDIS_STATUS oid_rt_pro_h2c_set_rate_table_hdl(struct oid_par_priv *poid_par_priv);
+NDIS_STATUS oid_rt_pro_h2c_get_rate_table_hdl(struct oid_par_priv *poid_par_priv);
+
+
+/* oid_rtl_seg_87_12_00 */
+NDIS_STATUS oid_rt_pro_encryption_ctrl_hdl(struct oid_par_priv *poid_par_priv);
+NDIS_STATUS oid_rt_pro_add_sta_info_hdl(struct oid_par_priv *poid_par_priv);
+NDIS_STATUS oid_rt_pro_dele_sta_info_hdl(struct oid_par_priv *poid_par_priv);
+NDIS_STATUS oid_rt_pro_query_dr_variable_hdl(struct oid_par_priv *poid_par_priv);
+NDIS_STATUS oid_rt_pro_rx_packet_type_hdl(struct oid_par_priv *poid_par_priv);
+
+NDIS_STATUS oid_rt_pro_read_efuse_hdl(struct oid_par_priv *poid_par_priv);
+NDIS_STATUS oid_rt_pro_write_efuse_hdl(struct oid_par_priv *poid_par_priv);
+NDIS_STATUS oid_rt_pro_rw_efuse_pgpkt_hdl(struct oid_par_priv *poid_par_priv);
+NDIS_STATUS oid_rt_get_efuse_current_size_hdl(struct oid_par_priv *poid_par_priv);
+NDIS_STATUS oid_rt_pro_efuse_hdl(struct oid_par_priv *poid_par_priv);
+NDIS_STATUS oid_rt_pro_efuse_map_hdl(struct oid_par_priv *poid_par_priv);
+
+NDIS_STATUS oid_rt_set_bandwidth_hdl(struct oid_par_priv *poid_par_priv);
+NDIS_STATUS oid_rt_set_crystal_cap_hdl(struct oid_par_priv *poid_par_priv);
+NDIS_STATUS oid_rt_set_rx_packet_type_hdl(struct oid_par_priv *poid_par_priv);
+NDIS_STATUS oid_rt_get_efuse_max_size_hdl(struct oid_par_priv *poid_par_priv);
+NDIS_STATUS oid_rt_pro_set_tx_agc_offset_hdl(struct oid_par_priv *poid_par_priv);
+
+NDIS_STATUS oid_rt_pro_set_pkt_test_mode_hdl(struct oid_par_priv *poid_par_priv);
+
+NDIS_STATUS oid_rt_get_thermal_meter_hdl(struct oid_par_priv *poid_par_priv);
+
+NDIS_STATUS oid_rt_reset_phy_rx_packet_count_hdl(struct oid_par_priv *poid_par_priv);
+NDIS_STATUS oid_rt_get_phy_rx_packet_received_hdl(struct oid_par_priv *poid_par_priv);
+NDIS_STATUS oid_rt_get_phy_rx_packet_crc32_error_hdl(struct oid_par_priv *poid_par_priv);
+
+NDIS_STATUS oid_rt_set_power_down_hdl(struct oid_par_priv *poid_par_priv);
+
+NDIS_STATUS oid_rt_get_power_mode_hdl(struct oid_par_priv *poid_par_priv);
+
+NDIS_STATUS oid_rt_pro_trigger_gpio_hdl(struct oid_par_priv *poid_par_priv);
+
+#ifdef _RTW_MP_IOCTL_C_
+
+const struct oid_obj_priv oid_rtl_seg_81_80_00[] = {
+	{1, &oid_null_function},			/* 0x00	OID_RT_PRO_RESET_DUT */
+	{1, &oid_rt_pro_set_data_rate_hdl},		/* 0x01 */
+	{1, &oid_rt_pro_start_test_hdl},		/* 0x02 */
+	{1, &oid_rt_pro_stop_test_hdl},			/* 0x03 */
+	{1, &oid_null_function},			/* 0x04	OID_RT_PRO_SET_PREAMBLE */
+	{1, &oid_null_function},			/* 0x05	OID_RT_PRO_SET_SCRAMBLER */
+	{1, &oid_null_function},			/* 0x06	OID_RT_PRO_SET_FILTER_BB */
+	{1, &oid_null_function},			/* 0x07	OID_RT_PRO_SET_MANUAL_DIVERSITY_BB */
+	{1, &oid_rt_pro_set_channel_direct_call_hdl},	/* 0x08 */
+	{1, &oid_null_function},			/* 0x09	OID_RT_PRO_SET_SLEEP_MODE_DIRECT_CALL */
+	{1, &oid_null_function},			/* 0x0A	OID_RT_PRO_SET_WAKE_MODE_DIRECT_CALL */
+	{1, &oid_rt_pro_set_continuous_tx_hdl},		/* 0x0B	OID_RT_PRO_SET_TX_CONTINUOUS_DIRECT_CALL */
+	{1, &oid_rt_pro_set_single_carrier_tx_hdl},	/* 0x0C	OID_RT_PRO_SET_SINGLE_CARRIER_TX_CONTINUOUS */
+	{1, &oid_null_function},			/* 0x0D	OID_RT_PRO_SET_TX_ANTENNA_BB */
+	{1, &oid_rt_pro_set_antenna_bb_hdl},		/* 0x0E */
+	{1, &oid_null_function},			/* 0x0F	OID_RT_PRO_SET_CR_SCRAMBLER */
+	{1, &oid_null_function},			/* 0x10	OID_RT_PRO_SET_CR_NEW_FILTER */
+	{1, &oid_rt_pro_set_tx_power_control_hdl},	/* 0x11	OID_RT_PRO_SET_TX_POWER_CONTROL */
+	{1, &oid_null_function},			/* 0x12	OID_RT_PRO_SET_CR_TX_CONFIG */
+	{1, &oid_null_function},			/* 0x13	OID_RT_PRO_GET_TX_POWER_CONTROL */
+	{1, &oid_null_function},			/* 0x14	OID_RT_PRO_GET_CR_SIGNAL_QUALITY */
+	{1, &oid_null_function},			/* 0x15	OID_RT_PRO_SET_CR_SETPOINT */
+	{1, &oid_null_function},			/* 0x16	OID_RT_PRO_SET_INTEGRATOR */
+	{1, &oid_null_function},			/* 0x17	OID_RT_PRO_SET_SIGNAL_QUALITY */
+	{1, &oid_null_function},			/* 0x18	OID_RT_PRO_GET_INTEGRATOR */
+	{1, &oid_null_function},			/* 0x19	OID_RT_PRO_GET_SIGNAL_QUALITY */
+	{1, &oid_null_function},			/* 0x1A	OID_RT_PRO_QUERY_EEPROM_TYPE */
+	{1, &oid_null_function},			/* 0x1B	OID_RT_PRO_WRITE_MAC_ADDRESS */
+	{1, &oid_null_function},			/* 0x1C	OID_RT_PRO_READ_MAC_ADDRESS */
+	{1, &oid_null_function},			/* 0x1D	OID_RT_PRO_WRITE_CIS_DATA */
+	{1, &oid_null_function},			/* 0x1E	OID_RT_PRO_READ_CIS_DATA */
+	{1, &oid_null_function}				/* 0x1F	OID_RT_PRO_WRITE_POWER_CONTROL */
+
+};
+
+const struct oid_obj_priv oid_rtl_seg_81_80_20[] = {
+	{1, &oid_null_function},			/* 0x20	OID_RT_PRO_READ_POWER_CONTROL */
+	{1, &oid_null_function},			/* 0x21	OID_RT_PRO_WRITE_EEPROM */
+	{1, &oid_null_function},			/* 0x22	OID_RT_PRO_READ_EEPROM */
+	{1, &oid_rt_pro_reset_tx_packet_sent_hdl},	/* 0x23 */
+	{1, &oid_rt_pro_query_tx_packet_sent_hdl},	/* 0x24 */
+	{1, &oid_rt_pro_reset_rx_packet_received_hdl},	/* 0x25 */
+	{1, &oid_rt_pro_query_rx_packet_received_hdl},	/* 0x26 */
+	{1, &oid_rt_pro_query_rx_packet_crc32_error_hdl},	/* 0x27 */
+	{1, &oid_null_function},			/* 0x28	OID_RT_PRO_QUERY_CURRENT_ADDRESS */
+	{1, &oid_null_function},			/* 0x29	OID_RT_PRO_QUERY_PERMANENT_ADDRESS */
+	{1, &oid_null_function},			/* 0x2A	OID_RT_PRO_SET_PHILIPS_RF_PARAMETERS */
+	{1, &oid_rt_pro_set_carrier_suppression_tx_hdl},/* 0x2B	OID_RT_PRO_SET_CARRIER_SUPPRESSION_TX */
+	{1, &oid_null_function},			/* 0x2C	OID_RT_PRO_RECEIVE_PACKET */
+	{1, &oid_null_function},			/* 0x2D	OID_RT_PRO_WRITE_EEPROM_BYTE */
+	{1, &oid_null_function},			/* 0x2E	OID_RT_PRO_READ_EEPROM_BYTE */
+	{1, &oid_rt_pro_set_modulation_hdl}		/* 0x2F */
+
+};
+
+const struct oid_obj_priv oid_rtl_seg_81_80_40[] = {
+	{1, &oid_null_function},			/* 0x40 */
+	{1, &oid_null_function},			/* 0x41 */
+	{1, &oid_null_function},			/* 0x42 */
+	{1, &oid_rt_pro_set_single_tone_tx_hdl},	/* 0x43 */
+	{1, &oid_null_function},			/* 0x44 */
+	{1, &oid_null_function}				/* 0x45 */
+};
+
+const struct oid_obj_priv oid_rtl_seg_81_80_80[] = {
+	{1, &oid_null_function},			/* 0x80	OID_RT_DRIVER_OPTION */
+	{1, &oid_null_function},			/* 0x81	OID_RT_RF_OFF */
+	{1, &oid_null_function}				/* 0x82	OID_RT_AUTH_STATUS */
+
+};
+
+const struct oid_obj_priv oid_rtl_seg_81_85[] = {
+	{1, &oid_rt_wireless_mode_hdl}			/* 0x00	OID_RT_WIRELESS_MODE */
+};
+
+struct oid_obj_priv oid_rtl_seg_81_87[] = {
+	{1, &oid_null_function},			/* 0x80	OID_RT_PRO8187_WI_POLL */
+	{1, &oid_rt_pro_write_bb_reg_hdl},		/* 0x81 */
+	{1, &oid_rt_pro_read_bb_reg_hdl},		/* 0x82 */
+	{1, &oid_rt_pro_write_rf_reg_hdl},		/* 0x82 */
+	{1, &oid_rt_pro_read_rf_reg_hdl}		/* 0x83 */
+};
+
+struct oid_obj_priv oid_rtl_seg_87_11_00[] = {
+	{1, &oid_rt_pro8711_join_bss_hdl},		/* 0x00  */ /* S */
+	{1, &oid_rt_pro_read_register_hdl},		/* 0x01 */
+	{1, &oid_rt_pro_write_register_hdl},		/* 0x02 */
+	{1, &oid_rt_pro_burst_read_register_hdl},	/* 0x03 */
+	{1, &oid_rt_pro_burst_write_register_hdl},	/* 0x04 */
+	{1, &oid_rt_pro_write_txcmd_hdl},		/* 0x05 */
+	{1, &oid_rt_pro_read16_eeprom_hdl},		/* 0x06 */
+	{1, &oid_rt_pro_write16_eeprom_hdl},		/* 0x07 */
+	{1, &oid_null_function},			/* 0x08	OID_RT_PRO_H2C_SET_COMMAND */
+	{1, &oid_null_function},			/* 0x09	OID_RT_PRO_H2C_QUERY_RESULT */
+	{1, &oid_rt_pro8711_wi_poll_hdl},		/* 0x0A */
+	{1, &oid_rt_pro8711_pkt_loss_hdl},		/* 0x0B */
+	{1, &oid_rt_rd_attrib_mem_hdl},			/* 0x0C */
+	{1, &oid_rt_wr_attrib_mem_hdl},			/* 0x0D */
+	{1, &oid_null_function},			/* 0x0E */
+	{1, &oid_null_function},			/* 0x0F */
+	{1, &oid_null_function},			/* 0x10	OID_RT_PRO_H2C_CMD_MODE */
+	{1, &oid_null_function},			/* 0x11	OID_RT_PRO_H2C_CMD_RSP_MODE */
+	{1, &oid_null_function},			/* 0X12	OID_RT_PRO_WAIT_C2H_EVENT */
+	{1, &oid_null_function},			/* 0X13	OID_RT_PRO_RW_ACCESS_PROTOCOL_TEST */
+	{1, &oid_null_function},			/* 0X14	OID_RT_PRO_SCSI_ACCESS_TEST */
+	{1, &oid_null_function},			/* 0X15	OID_RT_PRO_SCSI_TCPIPOFFLOAD_OUT */
+	{1, &oid_null_function},			/* 0X16	OID_RT_PRO_SCSI_TCPIPOFFLOAD_IN */
+	{1, &oid_null_function},			/* 0X17	OID_RT_RRO_RX_PKT_VIA_IOCTRL */
+	{1, &oid_null_function},			/* 0X18	OID_RT_RRO_RX_PKTARRAY_VIA_IOCTRL */
+	{1, &oid_null_function},			/* 0X19	OID_RT_RPO_SET_PWRMGT_TEST */
+	{1, &oid_null_function},			/* 0X1A */
+	{1, &oid_null_function},			/* 0X1B	OID_RT_PRO_QRY_PWRMGT_TEST */
+	{1, &oid_null_function},			/* 0X1C	OID_RT_RPO_ASYNC_RWIO_TEST */
+	{1, &oid_null_function},			/* 0X1D	OID_RT_RPO_ASYNC_RWIO_POLL */
+	{1, &oid_rt_pro_set_rf_intfs_hdl},		/* 0X1E */
+	{1, &oid_rt_poll_rx_status_hdl}			/* 0X1F */
+};
+
+struct oid_obj_priv oid_rtl_seg_87_11_20[] = {
+	{1, &oid_rt_pro_cfg_debug_message_hdl},		/* 0x20 */
+	{1, &oid_rt_pro_set_data_rate_ex_hdl},		/* 0x21 */
+	{1, &oid_rt_pro_set_basic_rate_hdl},		/* 0x22 */
+	{1, &oid_rt_pro_read_tssi_hdl},			/* 0x23 */
+	{1, &oid_rt_pro_set_power_tracking_hdl}		/* 0x24 */
+};
+
+
+struct oid_obj_priv oid_rtl_seg_87_11_50[] = {
+	{1, &oid_rt_pro_qry_pwrstate_hdl},		/* 0x50 */
+	{1, &oid_rt_pro_set_pwrstate_hdl}		/* 0x51 */
+};
+
+struct oid_obj_priv oid_rtl_seg_87_11_80[] = {
+	{1, &oid_null_function}				/* 0x80 */
+};
+
+struct oid_obj_priv oid_rtl_seg_87_11_B0[] = {
+	{1, &oid_null_function}				/* 0xB0 */
+};
+
+struct oid_obj_priv oid_rtl_seg_87_11_F0[] = {
+	{1, &oid_null_function},			/* 0xF0 */
+	{1, &oid_null_function},			/* 0xF1 */
+	{1, &oid_null_function},			/* 0xF2 */
+	{1, &oid_null_function},			/* 0xF3 */
+	{1, &oid_null_function},			/* 0xF4 */
+	{1, &oid_null_function},			/* 0xF5 */
+	{1, &oid_null_function},			/* 0xF6 */
+	{1, &oid_null_function},			/* 0xF7 */
+	{1, &oid_null_function},			/* 0xF8 */
+	{1, &oid_null_function},			/* 0xF9 */
+	{1, &oid_null_function},			/* 0xFA */
+	{1, &oid_rt_pro_h2c_set_rate_table_hdl},	/* 0xFB */
+	{1, &oid_rt_pro_h2c_get_rate_table_hdl},	/* 0xFC */
+	{1, &oid_null_function},			/* 0xFD */
+	{1, &oid_null_function},			/* 0xFE	OID_RT_PRO_H2C_C2H_LBK_TEST */
+	{1, &oid_null_function}				/* 0xFF */
+
+};
+
+struct oid_obj_priv oid_rtl_seg_87_12_00[] = {
+	{1, &oid_rt_pro_encryption_ctrl_hdl},		/* 0x00	Q&S */
+	{1, &oid_rt_pro_add_sta_info_hdl},		/* 0x01	S */
+	{1, &oid_rt_pro_dele_sta_info_hdl},		/* 0x02	S */
+	{1, &oid_rt_pro_query_dr_variable_hdl},		/* 0x03	Q */
+	{1, &oid_rt_pro_rx_packet_type_hdl},		/* 0x04	Q,S */
+	{1, &oid_rt_pro_read_efuse_hdl},		/* 0x05	Q	OID_RT_PRO_READ_EFUSE */
+	{1, &oid_rt_pro_write_efuse_hdl},		/* 0x06	S	OID_RT_PRO_WRITE_EFUSE */
+	{1, &oid_rt_pro_rw_efuse_pgpkt_hdl},		/* 0x07	Q,S */
+	{1, &oid_rt_get_efuse_current_size_hdl},	/* 0x08 	Q */
+	{1, &oid_rt_set_bandwidth_hdl},			/* 0x09 */
+	{1, &oid_rt_set_crystal_cap_hdl},		/* 0x0a */
+	{1, &oid_rt_set_rx_packet_type_hdl},		/* 0x0b	S */
+	{1, &oid_rt_get_efuse_max_size_hdl},		/* 0x0c */
+	{1, &oid_rt_pro_set_tx_agc_offset_hdl},		/* 0x0d */
+	{1, &oid_rt_pro_set_pkt_test_mode_hdl},		/* 0x0e */
+	{1, &oid_null_function},			/* 0x0f		OID_RT_PRO_FOR_EVM_TEST_SETTING */
+	{1, &oid_rt_get_thermal_meter_hdl},		/* 0x10	Q	OID_RT_PRO_GET_THERMAL_METER */
+	{1, &oid_rt_reset_phy_rx_packet_count_hdl},	/* 0x11	S	OID_RT_RESET_PHY_RX_PACKET_COUNT */
+	{1, &oid_rt_get_phy_rx_packet_received_hdl},	/* 0x12	Q	OID_RT_GET_PHY_RX_PACKET_RECEIVED */
+	{1, &oid_rt_get_phy_rx_packet_crc32_error_hdl},	/* 0x13	Q	OID_RT_GET_PHY_RX_PACKET_CRC32_ERROR */
+	{1, &oid_rt_set_power_down_hdl},		/* 0x14	Q	OID_RT_SET_POWER_DOWN */
+	{1, &oid_rt_get_power_mode_hdl}			/* 0x15	Q	OID_RT_GET_POWER_MODE */
+};
+
+#else /* _RTL871X_MP_IOCTL_C_ */
+
+extern struct oid_obj_priv oid_rtl_seg_81_80_00[32];
+extern struct oid_obj_priv oid_rtl_seg_81_80_20[16];
+extern struct oid_obj_priv oid_rtl_seg_81_80_40[6];
+extern struct oid_obj_priv oid_rtl_seg_81_80_80[3];
+
+extern struct oid_obj_priv oid_rtl_seg_81_85[1];
+extern struct oid_obj_priv oid_rtl_seg_81_87[5];
+
+extern struct oid_obj_priv oid_rtl_seg_87_11_00[32];
+extern struct oid_obj_priv oid_rtl_seg_87_11_20[5];
+extern struct oid_obj_priv oid_rtl_seg_87_11_50[2];
+extern struct oid_obj_priv oid_rtl_seg_87_11_80[1];
+extern struct oid_obj_priv oid_rtl_seg_87_11_B0[1];
+extern struct oid_obj_priv oid_rtl_seg_87_11_F0[16];
+
+extern struct oid_obj_priv oid_rtl_seg_87_12_00[32];
+
+#endif /* _RTL871X_MP_IOCTL_C_ */
+
+struct rwreg_param {
+	u32 offset;
+	u32 width;
+	u32 value;
+};
+
+struct bbreg_param {
+	u32 offset;
+	u32 phymask;
+	u32 value;
+};
+/*
+struct rfchannel_param{
+	u32 ch;
+	u32 modem;
+};
+*/
+struct txpower_param {
+	u32 pwr_index;
+};
+
+
+struct datarate_param {
+	u32 rate_index;
+};
+
+
+struct rfintfs_parm {
+	u32 rfintfs;
+};
+
+typedef struct _mp_xmit_parm_ {
+	u8 enable;
+	u32 count;
+	u16 length;
+	u8 payload_type;
+	u8 da[ETH_ALEN];
+} MP_XMIT_PARM, *PMP_XMIT_PARM;
+
+struct mp_xmit_packet {
+	u32 len;
+	u32 mem[MAX_MP_XMITBUF_SZ >> 2];
+};
+
+struct psmode_param {
+	u32 ps_mode;
+	u32 smart_ps;
+};
+
+/* for OID_RT_PRO_READ16_EEPROM & OID_RT_PRO_WRITE16_EEPROM */
+struct eeprom_rw_param {
+	u32 offset;
+	u16 value;
+};
+
+struct mp_ioctl_handler {
+	u32 paramsize;
+	u32(*handler)(struct oid_par_priv *poid_par_priv);
+	u32 oid;
+};
+
+struct mp_ioctl_param {
+	u32 subcode;
+	u32 len;
+	u8 data[0];
+};
+
+#define GEN_MP_IOCTL_SUBCODE(code) _MP_IOCTL_ ## code ## _CMD_
+
+enum RTL871X_MP_IOCTL_SUBCODE {
+	GEN_MP_IOCTL_SUBCODE(MP_START),			/*0*/
+	GEN_MP_IOCTL_SUBCODE(MP_STOP),
+	GEN_MP_IOCTL_SUBCODE(READ_REG),
+	GEN_MP_IOCTL_SUBCODE(WRITE_REG),
+	GEN_MP_IOCTL_SUBCODE(READ_BB_REG),
+	GEN_MP_IOCTL_SUBCODE(WRITE_BB_REG),		/*5*/
+	GEN_MP_IOCTL_SUBCODE(READ_RF_REG),
+	GEN_MP_IOCTL_SUBCODE(WRITE_RF_REG),
+	GEN_MP_IOCTL_SUBCODE(SET_CHANNEL),
+	GEN_MP_IOCTL_SUBCODE(SET_TXPOWER),
+	GEN_MP_IOCTL_SUBCODE(SET_DATARATE),		/*10*/
+	GEN_MP_IOCTL_SUBCODE(SET_BANDWIDTH),
+	GEN_MP_IOCTL_SUBCODE(SET_ANTENNA),
+	GEN_MP_IOCTL_SUBCODE(CNTU_TX),
+	GEN_MP_IOCTL_SUBCODE(SC_TX),
+	GEN_MP_IOCTL_SUBCODE(CS_TX),			/*15*/
+	GEN_MP_IOCTL_SUBCODE(ST_TX),
+	GEN_MP_IOCTL_SUBCODE(IOCTL_XMIT_PACKET),
+	GEN_MP_IOCTL_SUBCODE(SET_RX_PKT_TYPE),
+	GEN_MP_IOCTL_SUBCODE(RESET_PHY_RX_PKT_CNT),
+	GEN_MP_IOCTL_SUBCODE(GET_PHY_RX_PKT_RECV),	/*20*/
+	GEN_MP_IOCTL_SUBCODE(GET_PHY_RX_PKT_ERROR),
+	GEN_MP_IOCTL_SUBCODE(READ16_EEPROM),
+	GEN_MP_IOCTL_SUBCODE(WRITE16_EEPROM),
+	GEN_MP_IOCTL_SUBCODE(EFUSE),
+	GEN_MP_IOCTL_SUBCODE(EFUSE_MAP),		/*25*/
+	GEN_MP_IOCTL_SUBCODE(GET_EFUSE_MAX_SIZE),
+	GEN_MP_IOCTL_SUBCODE(GET_EFUSE_CURRENT_SIZE),
+	GEN_MP_IOCTL_SUBCODE(GET_THERMAL_METER),
+	GEN_MP_IOCTL_SUBCODE(SET_PTM),
+	GEN_MP_IOCTL_SUBCODE(SET_POWER_DOWN),		/*30*/
+	GEN_MP_IOCTL_SUBCODE(TRIGGER_GPIO),
+	GEN_MP_IOCTL_SUBCODE(SET_DM_BT),		/*32*/
+	GEN_MP_IOCTL_SUBCODE(DEL_BA),			/*33*/
+	GEN_MP_IOCTL_SUBCODE(GET_WIFI_STATUS),	/*34*/
+	MAX_MP_IOCTL_SUBCODE,
+};
+
+u32 mp_ioctl_xmit_packet_hdl(struct oid_par_priv *poid_par_priv);
+
+#ifdef _RTW_MP_IOCTL_C_
+
+#define GEN_MP_IOCTL_HANDLER(sz, hdl, oid) {sz, hdl, oid},
+
+#define EXT_MP_IOCTL_HANDLER(sz, subcode, oid) {sz, mp_ioctl_ ## subcode ## _hdl, oid},
+
+
+struct mp_ioctl_handler mp_ioctl_hdl[] = {
+
+	/*0*/	GEN_MP_IOCTL_HANDLER(sizeof(u32), oid_rt_pro_start_test_hdl, OID_RT_PRO_START_TEST)
+	GEN_MP_IOCTL_HANDLER(sizeof(u32), oid_rt_pro_stop_test_hdl, OID_RT_PRO_STOP_TEST)
+
+	GEN_MP_IOCTL_HANDLER(sizeof(struct rwreg_param), oid_rt_pro_read_register_hdl, OID_RT_PRO_READ_REGISTER)
+	GEN_MP_IOCTL_HANDLER(sizeof(struct rwreg_param), oid_rt_pro_write_register_hdl, OID_RT_PRO_WRITE_REGISTER)
+	GEN_MP_IOCTL_HANDLER(sizeof(struct bb_reg_param), oid_rt_pro_read_bb_reg_hdl, OID_RT_PRO_READ_BB_REG)
+	/*5*/	GEN_MP_IOCTL_HANDLER(sizeof(struct bb_reg_param), oid_rt_pro_write_bb_reg_hdl, OID_RT_PRO_WRITE_BB_REG)
+	GEN_MP_IOCTL_HANDLER(sizeof(struct rf_reg_param), oid_rt_pro_read_rf_reg_hdl, OID_RT_PRO_RF_READ_REGISTRY)
+	GEN_MP_IOCTL_HANDLER(sizeof(struct rf_reg_param), oid_rt_pro_write_rf_reg_hdl, OID_RT_PRO_RF_WRITE_REGISTRY)
+
+	GEN_MP_IOCTL_HANDLER(sizeof(u32), oid_rt_pro_set_channel_direct_call_hdl, OID_RT_PRO_SET_CHANNEL_DIRECT_CALL)
+	GEN_MP_IOCTL_HANDLER(sizeof(struct txpower_param), oid_rt_pro_set_tx_power_control_hdl, OID_RT_PRO_SET_TX_POWER_CONTROL)
+	/*10*/	GEN_MP_IOCTL_HANDLER(sizeof(u32), oid_rt_pro_set_data_rate_hdl, OID_RT_PRO_SET_DATA_RATE)
+	GEN_MP_IOCTL_HANDLER(sizeof(u32), oid_rt_set_bandwidth_hdl, OID_RT_SET_BANDWIDTH)
+	GEN_MP_IOCTL_HANDLER(sizeof(u32), oid_rt_pro_set_antenna_bb_hdl, OID_RT_PRO_SET_ANTENNA_BB)
+
+	GEN_MP_IOCTL_HANDLER(sizeof(u32), oid_rt_pro_set_continuous_tx_hdl, OID_RT_PRO_SET_CONTINUOUS_TX)
+	GEN_MP_IOCTL_HANDLER(sizeof(u32), oid_rt_pro_set_single_carrier_tx_hdl, OID_RT_PRO_SET_SINGLE_CARRIER_TX)
+	/*15*/	GEN_MP_IOCTL_HANDLER(sizeof(u32), oid_rt_pro_set_carrier_suppression_tx_hdl, OID_RT_PRO_SET_CARRIER_SUPPRESSION_TX)
+	GEN_MP_IOCTL_HANDLER(sizeof(u32), oid_rt_pro_set_single_tone_tx_hdl, OID_RT_PRO_SET_SINGLE_TONE_TX)
+
+	EXT_MP_IOCTL_HANDLER(0, xmit_packet, 0)
+
+	GEN_MP_IOCTL_HANDLER(sizeof(u32), oid_rt_set_rx_packet_type_hdl, OID_RT_SET_RX_PACKET_TYPE)
+	GEN_MP_IOCTL_HANDLER(0, oid_rt_reset_phy_rx_packet_count_hdl, OID_RT_RESET_PHY_RX_PACKET_COUNT)
+	/*20*/	GEN_MP_IOCTL_HANDLER(sizeof(u32), oid_rt_get_phy_rx_packet_received_hdl, OID_RT_GET_PHY_RX_PACKET_RECEIVED)
+	GEN_MP_IOCTL_HANDLER(sizeof(u32), oid_rt_get_phy_rx_packet_crc32_error_hdl, OID_RT_GET_PHY_RX_PACKET_CRC32_ERROR)
+
+	GEN_MP_IOCTL_HANDLER(sizeof(struct eeprom_rw_param), NULL, 0)
+	GEN_MP_IOCTL_HANDLER(sizeof(struct eeprom_rw_param), NULL, 0)
+	GEN_MP_IOCTL_HANDLER(sizeof(EFUSE_ACCESS_STRUCT), oid_rt_pro_efuse_hdl, OID_RT_PRO_EFUSE)
+	/*25*/	GEN_MP_IOCTL_HANDLER(0, oid_rt_pro_efuse_map_hdl, OID_RT_PRO_EFUSE_MAP)
+	GEN_MP_IOCTL_HANDLER(sizeof(u32), oid_rt_get_efuse_max_size_hdl, OID_RT_GET_EFUSE_MAX_SIZE)
+	GEN_MP_IOCTL_HANDLER(sizeof(u32), oid_rt_get_efuse_current_size_hdl, OID_RT_GET_EFUSE_CURRENT_SIZE)
+
+	GEN_MP_IOCTL_HANDLER(sizeof(u32), oid_rt_get_thermal_meter_hdl, OID_RT_PRO_GET_THERMAL_METER)
+	GEN_MP_IOCTL_HANDLER(sizeof(u8), oid_rt_pro_set_power_tracking_hdl, OID_RT_PRO_SET_POWER_TRACKING)
+	/*30*/	GEN_MP_IOCTL_HANDLER(sizeof(u8), oid_rt_set_power_down_hdl, OID_RT_SET_POWER_DOWN)
+	/*31*/	GEN_MP_IOCTL_HANDLER(0, oid_rt_pro_trigger_gpio_hdl, 0)
+	GEN_MP_IOCTL_HANDLER(0, NULL, 0)
+	GEN_MP_IOCTL_HANDLER(0, NULL, 0)
+	GEN_MP_IOCTL_HANDLER(0, NULL, 0)
+};
+
+#else /* _RTW_MP_IOCTL_C_ */
+
+extern struct mp_ioctl_handler mp_ioctl_hdl[];
+
+#endif /* _RTW_MP_IOCTL_C_ */
+
+#endif
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/include/rtw_mp_phy_regdef.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/rtw_mp_phy_regdef.h
--- linux-5.6.3/3rdparty/rtl8821ce/include/rtw_mp_phy_regdef.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/rtw_mp_phy_regdef.h	2020-04-10 16:35:06.852661748 +0300
@@ -0,0 +1,1094 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+/*****************************************************************************
+ *
+ * Module:	__RTW_MP_PHY_REGDEF_H_
+ *
+ *
+ * Note:	1. Define PMAC/BB register map
+ *			2. Define RF register map
+ *			3. PMAC/BB register bit mask.
+ *			4. RF reg bit mask.
+ *			5. Other BB/RF relative definition.
+ *
+ *
+ * Export:	Constants, macro, functions(API), global variables(None).
+ *
+ * Abbrev:
+ *
+ * History:
+ *	Data			Who		Remark
+ *	08/07/2007	MHC		1. Porting from 9x series PHYCFG.h.
+ *						2. Reorganize code architecture.
+ *	09/25/2008	MH		1. Add RL6052 register definition
+ *
+ *****************************************************************************/
+#ifndef __RTW_MP_PHY_REGDEF_H_
+#define __RTW_MP_PHY_REGDEF_H_
+
+
+/*--------------------------Define Parameters-------------------------------*/
+
+/* ************************************************************
+ * 8192S Regsiter offset definition
+ * ************************************************************ */
+
+/*
+ * BB-PHY register PMAC 0x100 PHY 0x800 - 0xEFF
+ * 1. PMAC duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF
+ * 2. 0x800/0x900/0xA00/0xC00/0xD00/0xE00
+ * 3. RF register 0x00-2E
+ * 4. Bit Mask for BB/RF register
+ * 5. Other defintion for BB/RF R/W
+ *   */
+
+
+/*
+ * 1. PMAC duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF
+ * 1. Page1(0x100)
+ *   */
+#define		rPMAC_Reset					0x100
+#define		rPMAC_TxStart					0x104
+#define		rPMAC_TxLegacySIG				0x108
+#define		rPMAC_TxHTSIG1				0x10c
+#define		rPMAC_TxHTSIG2				0x110
+#define		rPMAC_PHYDebug				0x114
+#define		rPMAC_TxPacketNum				0x118
+#define		rPMAC_TxIdle					0x11c
+#define		rPMAC_TxMACHeader0			0x120
+#define		rPMAC_TxMACHeader1			0x124
+#define		rPMAC_TxMACHeader2			0x128
+#define		rPMAC_TxMACHeader3			0x12c
+#define		rPMAC_TxMACHeader4			0x130
+#define		rPMAC_TxMACHeader5			0x134
+#define		rPMAC_TxDataType				0x138
+#define		rPMAC_TxRandomSeed			0x13c
+#define		rPMAC_CCKPLCPPreamble			0x140
+#define		rPMAC_CCKPLCPHeader			0x144
+#define		rPMAC_CCKCRC16				0x148
+#define		rPMAC_OFDMRxCRC32OK			0x170
+#define		rPMAC_OFDMRxCRC32Er			0x174
+#define		rPMAC_OFDMRxParityEr			0x178
+#define		rPMAC_OFDMRxCRC8Er			0x17c
+#define		rPMAC_CCKCRxRC16Er			0x180
+#define		rPMAC_CCKCRxRC32Er			0x184
+#define		rPMAC_CCKCRxRC32OK			0x188
+#define		rPMAC_TxStatus					0x18c
+
+/*
+ * 2. Page2(0x200)
+ *
+ * The following two definition are only used for USB interface.
+ * #define		RF_BB_CMD_ADDR				0x02c0 */	/* RF/BB read/write command address.
+ * #define		RF_BB_CMD_DATA				0x02c4 */	/* RF/BB read/write command data. */
+
+/*
+ * 3. Page8(0x800)
+ *   */
+#define		rFPGA0_RFMOD				0x800	/* RF mode & CCK TxSC */ /* RF BW Setting?? */
+
+#define		rFPGA0_TxInfo				0x804	/* Status report?? */
+#define		rFPGA0_PSDFunction			0x808
+
+#define		rFPGA0_TxGainStage			0x80c	/* Set TX PWR init gain? */
+
+#define		rFPGA0_RFTiming1			0x810	/* Useless now */
+#define		rFPGA0_RFTiming2			0x814
+/* #define rFPGA0_XC_RFTiming		0x818 */
+/* #define rFPGA0_XD_RFTiming		0x81c */
+
+#define		rFPGA0_XA_HSSIParameter1		0x820	/* RF 3 wire register */
+#define		rFPGA0_XA_HSSIParameter2		0x824
+#define		rFPGA0_XB_HSSIParameter1		0x828
+#define		rFPGA0_XB_HSSIParameter2		0x82c
+#define		rFPGA0_XC_HSSIParameter1		0x830
+#define		rFPGA0_XC_HSSIParameter2		0x834
+#define		rFPGA0_XD_HSSIParameter1		0x838
+#define		rFPGA0_XD_HSSIParameter2		0x83c
+#define		rFPGA0_XA_LSSIParameter		0x840
+#define		rFPGA0_XB_LSSIParameter		0x844
+#define		rFPGA0_XC_LSSIParameter		0x848
+#define		rFPGA0_XD_LSSIParameter		0x84c
+
+#define		rFPGA0_RFWakeUpParameter		0x850	/* Useless now */
+#define		rFPGA0_RFSleepUpParameter		0x854
+
+#define		rFPGA0_XAB_SwitchControl		0x858	/* RF Channel switch */
+#define		rFPGA0_XCD_SwitchControl		0x85c
+
+#define		rFPGA0_XA_RFInterfaceOE		0x860	/* RF Channel switch */
+#define		rFPGA0_XB_RFInterfaceOE		0x864
+#define		rFPGA0_XC_RFInterfaceOE		0x868
+#define		rFPGA0_XD_RFInterfaceOE		0x86c
+
+#define		rFPGA0_XAB_RFInterfaceSW		0x870	/* RF Interface Software Control */
+#define		rFPGA0_XCD_RFInterfaceSW		0x874
+
+#define		rFPGA0_XAB_RFParameter		0x878	/* RF Parameter */
+#define		rFPGA0_XCD_RFParameter		0x87c
+
+#define		rFPGA0_AnalogParameter1		0x880	/* Crystal cap setting RF-R/W protection for parameter4?? */
+#define		rFPGA0_AnalogParameter2		0x884
+#define		rFPGA0_AnalogParameter3		0x888	/* Useless now */
+#define		rFPGA0_AnalogParameter4		0x88c
+
+#define		rFPGA0_XA_LSSIReadBack		0x8a0	/* Tranceiver LSSI Readback */
+#define		rFPGA0_XB_LSSIReadBack		0x8a4
+#define		rFPGA0_XC_LSSIReadBack		0x8a8
+#define		rFPGA0_XD_LSSIReadBack		0x8ac
+
+#define		rFPGA0_PSDReport				0x8b4	/* Useless now */
+#define		rFPGA0_XAB_RFInterfaceRB		0x8e0	/* Useless now */ /* RF Interface Readback Value */
+#define		rFPGA0_XCD_RFInterfaceRB		0x8e4	/* Useless now */
+
+/*
+ * 4. Page9(0x900)
+ *   */
+#define		rFPGA1_RFMOD				0x900	/* RF mode & OFDM TxSC */ /* RF BW Setting?? */
+
+#define		rFPGA1_TxBlock				0x904	/* Useless now */
+#define		rFPGA1_DebugSelect			0x908	/* Useless now */
+#define		rFPGA1_TxInfo				0x90c	/* Useless now */ /* Status report?? */
+#define	rS0S1_PathSwitch			0x948
+
+/*
+ * 5. PageA(0xA00)
+ *
+ * Set Control channel to upper or lower. These settings are required only for 40MHz */
+#define		rCCK0_System				0xa00
+
+#define		rCCK0_AFESetting			0xa04	/* Disable init gain now */ /* Select RX path by RSSI */
+#define		rCCK0_CCA					0xa08	/* Disable init gain now */ /* Init gain */
+
+#define		rCCK0_RxAGC1				0xa0c	/* AGC default value, saturation level  */ /* Antenna Diversity, RX AGC, LNA Threshold, RX LNA Threshold useless now. Not the same as 90 series */
+#define		rCCK0_RxAGC2				0xa10	/* AGC & DAGC */
+
+#define		rCCK0_RxHP					0xa14
+
+#define		rCCK0_DSPParameter1		0xa18	/* Timing recovery & Channel estimation threshold */
+#define		rCCK0_DSPParameter2		0xa1c	/* SQ threshold */
+
+#define		rCCK0_TxFilter1				0xa20
+#define		rCCK0_TxFilter2				0xa24
+#define		rCCK0_DebugPort			0xa28	/* debug port and Tx filter3 */
+#define		rCCK0_FalseAlarmReport		0xa2c	/* 0xa2d	useless now 0xa30-a4f channel report */
+#define		rCCK0_TRSSIReport		0xa50
+#define		rCCK0_RxReport            		0xa54  /* 0xa57 */
+#define		rCCK0_FACounterLower      	0xa5c  /* 0xa5b */
+#define		rCCK0_FACounterUpper      	0xa58  /* 0xa5c */
+
+/*
+ * 6. PageC(0xC00)
+ *   */
+#define		rOFDM0_LSTF				0xc00
+
+#define		rOFDM0_TRxPathEnable		0xc04
+#define		rOFDM0_TRMuxPar			0xc08
+#define		rOFDM0_TRSWIsolation		0xc0c
+
+#define		rOFDM0_XARxAFE			0xc10  /* RxIQ DC offset, Rx digital filter, DC notch filter */
+#define		rOFDM0_XARxIQImbalance    	0xc14  /* RxIQ imblance matrix */
+#define		rOFDM0_XBRxAFE		0xc18
+#define		rOFDM0_XBRxIQImbalance	0xc1c
+#define		rOFDM0_XCRxAFE		0xc20
+#define		rOFDM0_XCRxIQImbalance	0xc24
+#define		rOFDM0_XDRxAFE		0xc28
+#define		rOFDM0_XDRxIQImbalance	0xc2c
+
+#define		rOFDM0_RxDetector1			0xc30  /* PD, BW & SBD	 */ /* DM tune init gain */
+#define		rOFDM0_RxDetector2			0xc34  /* SBD & Fame Sync. */
+#define		rOFDM0_RxDetector3			0xc38  /* Frame Sync. */
+#define		rOFDM0_RxDetector4			0xc3c  /* PD, SBD, Frame Sync & Short-GI */
+
+#define		rOFDM0_RxDSP				0xc40  /* Rx Sync Path */
+#define		rOFDM0_CFOandDAGC		0xc44  /* CFO & DAGC */
+#define		rOFDM0_CCADropThreshold	0xc48 /* CCA Drop threshold */
+#define		rOFDM0_ECCAThreshold		0xc4c /* energy CCA */
+
+#define		rOFDM0_XAAGCCore1			0xc50	/* DIG  */
+#define		rOFDM0_XAAGCCore2			0xc54
+#define		rOFDM0_XBAGCCore1			0xc58
+#define		rOFDM0_XBAGCCore2			0xc5c
+#define		rOFDM0_XCAGCCore1			0xc60
+#define		rOFDM0_XCAGCCore2			0xc64
+#define		rOFDM0_XDAGCCore1			0xc68
+#define		rOFDM0_XDAGCCore2			0xc6c
+
+#define		rOFDM0_AGCParameter1			0xc70
+#define		rOFDM0_AGCParameter2			0xc74
+#define		rOFDM0_AGCRSSITable			0xc78
+#define		rOFDM0_HTSTFAGC				0xc7c
+
+#define		rOFDM0_XATxIQImbalance		0xc80	/* TX PWR TRACK and DIG */
+#define		rOFDM0_XATxAFE				0xc84
+#define		rOFDM0_XBTxIQImbalance		0xc88
+#define		rOFDM0_XBTxAFE				0xc8c
+#define		rOFDM0_XCTxIQImbalance		0xc90
+#define		rOFDM0_XCTxAFE			0xc94
+#define		rOFDM0_XDTxIQImbalance		0xc98
+#define		rOFDM0_XDTxAFE				0xc9c
+#define		rOFDM0_RxIQExtAnta			0xca0
+
+#define		rOFDM0_RxHPParameter			0xce0
+#define		rOFDM0_TxPseudoNoiseWgt		0xce4
+#define		rOFDM0_FrameSync				0xcf0
+#define		rOFDM0_DFSReport				0xcf4
+#define		rOFDM0_TxCoeff1				0xca4
+#define		rOFDM0_TxCoeff2				0xca8
+#define		rOFDM0_TxCoeff3				0xcac
+#define		rOFDM0_TxCoeff4				0xcb0
+#define		rOFDM0_TxCoeff5				0xcb4
+#define		rOFDM0_TxCoeff6				0xcb8
+
+
+/*
+ * 7. PageD(0xD00)
+ *   */
+#define		rOFDM1_LSTF					0xd00
+#define		rOFDM1_TRxPathEnable			0xd04
+
+#define		rOFDM1_CFO						0xd08	/* No setting now */
+#define		rOFDM1_CSI1					0xd10
+#define		rOFDM1_SBD						0xd14
+#define		rOFDM1_CSI2					0xd18
+#define		rOFDM1_CFOTracking			0xd2c
+#define		rOFDM1_TRxMesaure1			0xd34
+#define		rOFDM1_IntfDet					0xd3c
+#define		rOFDM1_PseudoNoiseStateAB		0xd50
+#define		rOFDM1_PseudoNoiseStateCD		0xd54
+#define		rOFDM1_RxPseudoNoiseWgt		0xd58
+
+#define		rOFDM_PHYCounter1				0xda0  /* cca, parity fail */
+#define		rOFDM_PHYCounter2				0xda4  /* rate illegal, crc8 fail */
+#define		rOFDM_PHYCounter3				0xda8  /* MCS not support */
+
+#define		rOFDM_ShortCFOAB				0xdac	/* No setting now */
+#define		rOFDM_ShortCFOCD				0xdb0
+#define		rOFDM_LongCFOAB				0xdb4
+#define		rOFDM_LongCFOCD				0xdb8
+#define		rOFDM_TailCFOAB				0xdbc
+#define		rOFDM_TailCFOCD				0xdc0
+#define		rOFDM_PWMeasure1		0xdc4
+#define		rOFDM_PWMeasure2		0xdc8
+#define		rOFDM_BWReport				0xdcc
+#define		rOFDM_AGCReport				0xdd0
+#define		rOFDM_RxSNR					0xdd4
+#define		rOFDM_RxEVMCSI				0xdd8
+#define		rOFDM_SIGReport				0xddc
+
+
+/*
+ * 8. PageE(0xE00)
+ *   */
+#define		rTxAGC_Rate18_06				0xe00
+#define		rTxAGC_Rate54_24				0xe04
+#define		rTxAGC_CCK_Mcs32				0xe08
+#define		rTxAGC_Mcs03_Mcs00			0xe10
+#define		rTxAGC_Mcs07_Mcs04			0xe14
+#define		rTxAGC_Mcs11_Mcs08			0xe18
+#define		rTxAGC_Mcs15_Mcs12			0xe1c
+
+/* Analog- control in RX_WAIT_CCA : REG: EE0 [Analog- Power & Control Register] */
+#define		rRx_Wait_CCCA					0xe70
+#define		rAnapar_Ctrl_BB					0xee0
+
+/*
+ * 7. RF Register 0x00-0x2E (RF 8256)
+ * RF-0222D 0x00-3F
+ *
+ * Zebra1 */
+#define RTL92SE_FPGA_VERIFY 0
+#define		rZebra1_HSSIEnable				0x0	/* Useless now */
+#define		rZebra1_TRxEnable1				0x1
+#define		rZebra1_TRxEnable2				0x2
+#define		rZebra1_AGC					0x4
+#define		rZebra1_ChargePump			0x5
+/* #if (RTL92SE_FPGA_VERIFY == 1) */
+#define		rZebra1_Channel				0x7	/* RF channel switch
+ * #else */
+
+/* #endif */
+#define		rZebra1_TxGain					0x8	/* Useless now */
+#define		rZebra1_TxLPF					0x9
+#define		rZebra1_RxLPF					0xb
+#define		rZebra1_RxHPFCorner			0xc
+
+/* Zebra4 */
+#define		rGlobalCtrl						0	/* Useless now */
+#define		rRTL8256_TxLPF					19
+#define		rRTL8256_RxLPF					11
+
+/* RTL8258 */
+#define		rRTL8258_TxLPF					0x11	/* Useless now */
+#define		rRTL8258_RxLPF					0x13
+#define		rRTL8258_RSSILPF				0xa
+
+/*
+ * RL6052 Register definition
+ *   */
+#define		RF_AC						0x00	/*  */
+
+#define		RF_IQADJ_G1				0x01	/*  */
+#define		RF_IQADJ_G2				0x02	/*  */
+#define		RF_POW_TRSW				0x05	/*  */
+
+#define		RF_GAIN_RX					0x06	/*  */
+#define		RF_GAIN_TX					0x07	/*  */
+
+#define		RF_TXM_IDAC				0x08	/*  */
+#define		RF_BS_IQGEN				0x0F	/*  */
+
+#define		RF_MODE1					0x10	/*  */
+#define		RF_MODE2					0x11	/*  */
+
+#define		RF_RX_AGC_HP				0x12	/*  */
+#define		RF_TX_AGC					0x13	/*  */
+#define		RF_BIAS						0x14	/*  */
+#define		RF_IPA						0x15	/*  */
+#define		RF_TXBIAS					0x16
+#define		RF_POW_ABILITY			0x17	/*  */
+#define		RF_MODE_AG				0x18	/*  */
+#define		rRfChannel					0x18	/* RF channel and BW switch */
+#define		RF_CHNLBW					0x18	/* RF channel and BW switch */
+#define		RF_TOP						0x19	/*  */
+
+#define		RF_RX_G1					0x1A	/*  */
+#define		RF_RX_G2					0x1B	/*  */
+
+#define		RF_RX_BB2					0x1C	/*  */
+#define		RF_RX_BB1					0x1D	/*  */
+
+#define		RF_RCK1					0x1E	/*  */
+#define		RF_RCK2					0x1F	/*  */
+
+#define		RF_TX_G1					0x20	/*  */
+#define		RF_TX_G2					0x21	/*  */
+#define		RF_TX_G3					0x22	/*  */
+
+#define		RF_TX_BB1					0x23	/*  */
+
+#define		RF_T_METER					0x24	/*  */
+
+#define		RF_SYN_G1					0x25	/* RF TX Power control */
+#define		RF_SYN_G2					0x26	/* RF TX Power control */
+#define		RF_SYN_G3					0x27	/* RF TX Power control */
+#define		RF_SYN_G4					0x28	/* RF TX Power control */
+#define		RF_SYN_G5					0x29	/* RF TX Power control */
+#define		RF_SYN_G6					0x2A	/* RF TX Power control */
+#define		RF_SYN_G7					0x2B	/* RF TX Power control */
+#define		RF_SYN_G8					0x2C	/* RF TX Power control */
+
+#define		RF_RCK_OS					0x30	/* RF TX PA control */
+
+#define		RF_TXPA_G1					0x31	/* RF TX PA control */
+#define		RF_TXPA_G2					0x32	/* RF TX PA control */
+#define		RF_TXPA_G3					0x33	/* RF TX PA control */
+
+/*
+ * Bit Mask
+ *
+ * 1. Page1(0x100) */
+#define		bBBResetB						0x100	/* Useless now? */
+#define		bGlobalResetB					0x200
+#define		bOFDMTxStart					0x4
+#define		bCCKTxStart						0x8
+#define		bCRC32Debug					0x100
+#define		bPMACLoopback					0x10
+#define		bTxLSIG							0xffffff
+#define		bOFDMTxRate					0xf
+#define		bOFDMTxReserved				0x10
+#define		bOFDMTxLength					0x1ffe0
+#define		bOFDMTxParity					0x20000
+#define		bTxHTSIG1						0xffffff
+#define		bTxHTMCSRate					0x7f
+#define		bTxHTBW						0x80
+#define		bTxHTLength					0xffff00
+#define		bTxHTSIG2						0xffffff
+#define		bTxHTSmoothing					0x1
+#define		bTxHTSounding					0x2
+#define		bTxHTReserved					0x4
+#define		bTxHTAggreation				0x8
+#define		bTxHTSTBC						0x30
+#define		bTxHTAdvanceCoding			0x40
+#define		bTxHTShortGI					0x80
+#define		bTxHTNumberHT_LTF			0x300
+#define		bTxHTCRC8						0x3fc00
+#define		bCounterReset					0x10000
+#define		bNumOfOFDMTx					0xffff
+#define		bNumOfCCKTx					0xffff0000
+#define		bTxIdleInterval					0xffff
+#define		bOFDMService					0xffff0000
+#define		bTxMACHeader					0xffffffff
+#define		bTxDataInit						0xff
+#define		bTxHTMode						0x100
+#define		bTxDataType					0x30000
+#define		bTxRandomSeed					0xffffffff
+#define		bCCKTxPreamble					0x1
+#define		bCCKTxSFD						0xffff0000
+#define		bCCKTxSIG						0xff
+#define		bCCKTxService					0xff00
+#define		bCCKLengthExt					0x8000
+#define		bCCKTxLength					0xffff0000
+#define		bCCKTxCRC16					0xffff
+#define		bCCKTxStatus					0x1
+#define		bOFDMTxStatus					0x2
+
+#define		IS_BB_REG_OFFSET_92S(_Offset)		((_Offset >= 0x800) && (_Offset <= 0xfff))
+
+/* 2. Page8(0x800) */
+#define		bRFMOD							0x1	/* Reg 0x800 rFPGA0_RFMOD */
+#define		bJapanMode						0x2
+#define		bCCKTxSC						0x30
+#define		bCCKEn							0x1000000
+#define		bOFDMEn						0x2000000
+
+#define		bOFDMRxADCPhase           		0x10000	/* Useless now */
+#define		bOFDMTxDACPhase		0x40000
+#define		bXATxAGC			0x3f
+
+#define		bXBTxAGC                  			0xf00	/* Reg 80c rFPGA0_TxGainStage */
+#define		bXCTxAGC			0xf000
+#define		bXDTxAGC			0xf0000
+
+#define		bPAStart                  			0xf0000000	/* Useless now */
+#define		bTRStart			0x00f00000
+#define		bRFStart			0x0000f000
+#define		bBBStart			0x000000f0
+#define		bBBCCKStart		0x0000000f
+#define		bPAEnd                    			0xf          /* Reg0x814 */
+#define		bTREnd			0x0f000000
+#define		bRFEnd			0x000f0000
+#define		bCCAMask                  			0x000000f0   /* T2R */
+#define		bR2RCCAMask		0x00000f00
+#define		bHSSI_R2TDelay		0xf8000000
+#define		bHSSI_T2RDelay		0xf80000
+#define		bContTxHSSI               		0x400     /* chane gain at continue Tx */
+#define		bIGFromCCK		0x200
+#define		bAGCAddress		0x3f
+#define		bRxHPTx			0x7000
+#define		bRxHPT2R			0x38000
+#define		bRxHPCCKIni		0xc0000
+#define		bAGCTxCode		0xc00000
+#define		bAGCRxCode		0x300000
+
+#define		b3WireDataLength          		0x800	/* Reg 0x820~84f rFPGA0_XA_HSSIParameter1 */
+#define		b3WireAddressLength		0x400
+
+#define		b3WireRFPowerDown         		0x1	/* Useless now
+ * #define bHWSISelect		0x8 */
+#define		b5GPAPEPolarity		0x40000000
+#define		b2GPAPEPolarity		0x80000000
+#define		bRFSW_TxDefaultAnt		0x3
+#define		bRFSW_TxOptionAnt		0x30
+#define		bRFSW_RxDefaultAnt		0x300
+#define		bRFSW_RxOptionAnt		0x3000
+#define		bRFSI_3WireData		0x1
+#define		bRFSI_3WireClock		0x2
+#define		bRFSI_3WireLoad		0x4
+#define		bRFSI_3WireRW		0x8
+#define		bRFSI_3Wire			0xf
+
+#define		bRFSI_RFENV               		0x10	/* Reg 0x870 rFPGA0_XAB_RFInterfaceSW */
+
+#define		bRFSI_TRSW                		0x20	/* Useless now */
+#define		bRFSI_TRSWB		0x40
+#define		bRFSI_ANTSW		0x100
+#define		bRFSI_ANTSWB		0x200
+#define		bRFSI_PAPE			0x400
+#define		bRFSI_PAPE5G		0x800
+#define		bBandSelect			0x1
+#define		bHTSIG2_GI			0x80
+#define		bHTSIG2_Smoothing		0x01
+#define		bHTSIG2_Sounding		0x02
+#define		bHTSIG2_Aggreaton		0x08
+#define		bHTSIG2_STBC		0x30
+#define		bHTSIG2_AdvCoding		0x40
+#define		bHTSIG2_NumOfHTLTF	0x300
+#define		bHTSIG2_CRC8		0x3fc
+#define		bHTSIG1_MCS		0x7f
+#define		bHTSIG1_BandWidth		0x80
+#define		bHTSIG1_HTLength		0xffff
+#define		bLSIG_Rate			0xf
+#define		bLSIG_Reserved		0x10
+#define		bLSIG_Length		0x1fffe
+#define		bLSIG_Parity			0x20
+#define		bCCKRxPhase		0x4
+#if (RTL92SE_FPGA_VERIFY == 1)
+	#define		bLSSIReadAddress          		0x3f000000   /* LSSI "Read" Address	 */ /* Reg 0x824 rFPGA0_XA_HSSIParameter2 */
+#else
+	#define		bLSSIReadAddress          		0x7f800000   /* T65 RF */
+#endif
+#define		bLSSIReadEdge             		0x80000000   /* LSSI "Read" edge signal */
+#if (RTL92SE_FPGA_VERIFY == 1)
+	#define		bLSSIReadBackData         		0xfff		/* Reg 0x8a0 rFPGA0_XA_LSSIReadBack */
+#else
+	#define		bLSSIReadBackData         		0xfffff		/* T65 RF */
+#endif
+#define		bLSSIReadOKFlag           		0x1000	/* Useless now */
+#define		bCCKSampleRate            		0x8       /* 0: 44MHz, 1:88MHz      		 */
+#define		bRegulator0Standby		0x1
+#define		bRegulatorPLLStandby		0x2
+#define		bRegulator1Standby		0x4
+#define		bPLLPowerUp		0x8
+#define		bDPLLPowerUp		0x10
+#define		bDA10PowerUp		0x20
+#define		bAD7PowerUp		0x200
+#define		bDA6PowerUp		0x2000
+#define		bXtalPowerUp		0x4000
+#define		b40MDClkPowerUP		0x8000
+#define		bDA6DebugMode		0x20000
+#define		bDA6Swing			0x380000
+
+#define		bADClkPhase               		0x4000000	/* Reg 0x880 rFPGA0_AnalogParameter1 20/40 CCK support switch 40/80 BB MHZ */
+
+#define		b80MClkDelay              		0x18000000	/* Useless */
+#define		bAFEWatchDogEnable		0x20000000
+
+#define		bXtalCap01                			0xc0000000	/* Reg 0x884 rFPGA0_AnalogParameter2 Crystal cap */
+#define		bXtalCap23			0x3
+#define		bXtalCap92x					0x0f000000
+#define		bXtalCap			0x0f000000
+
+#define		bIntDifClkEnable          		0x400	/* Useless */
+#define		bExtSigClkEnable		0x800
+#define		bBandgapMbiasPowerUp	0x10000
+#define		bAD11SHGain		0xc0000
+#define		bAD11InputRange		0x700000
+#define		bAD11OPCurrent		0x3800000
+#define		bIPathLoopback		0x4000000
+#define		bQPathLoopback		0x8000000
+#define		bAFELoopback		0x10000000
+#define		bDA10Swing		0x7e0
+#define		bDA10Reverse		0x800
+#define		bDAClkSource		0x1000
+#define		bAD7InputRange		0x6000
+#define		bAD7Gain			0x38000
+#define		bAD7OutputCMMode		0x40000
+#define		bAD7InputCMMode		0x380000
+#define		bAD7Current			0xc00000
+#define		bRegulatorAdjust		0x7000000
+#define		bAD11PowerUpAtTx		0x1
+#define		bDA10PSAtTx		0x10
+#define		bAD11PowerUpAtRx		0x100
+#define		bDA10PSAtRx		0x1000
+#define		bCCKRxAGCFormat		0x200
+#define		bPSDFFTSamplepPoint		0xc000
+#define		bPSDAverageNum		0x3000
+#define		bIQPathControl		0xc00
+#define		bPSDFreq			0x3ff
+#define		bPSDAntennaPath		0x30
+#define		bPSDIQSwitch		0x40
+#define		bPSDRxTrigger		0x400000
+#define		bPSDTxTrigger		0x80000000
+#define		bPSDSineToneScale		0x7f000000
+#define		bPSDReport			0xffff
+
+/* 3. Page9(0x900) */
+#define		bOFDMTxSC                 		0x30000000	/* Useless */
+#define		bCCKTxOn			0x1
+#define		bOFDMTxOn		0x2
+#define		bDebugPage                		0xfff  /* reset debug page and also HWord, LWord */
+#define		bDebugItem                		0xff   /* reset debug page and LWord */
+#define		bAntL			0x10
+#define		bAntNonHT				0x100
+#define		bAntHT1			0x1000
+#define		bAntHT2			0x10000
+#define		bAntHT1S1			0x100000
+#define		bAntNonHTS1		0x1000000
+
+/* 4. PageA(0xA00) */
+#define		bCCKBBMode                		0x3	/* Useless */
+#define		bCCKTxPowerSaving		0x80
+#define		bCCKRxPowerSaving		0x40
+
+#define		bCCKSideBand              		0x10	/* Reg 0xa00 rCCK0_System 20/40 switch */
+
+#define		bCCKScramble              		0x8	/* Useless */
+#define		bCCKAntDiversity			0x8000
+#define		bCCKCarrierRecovery		0x4000
+#define		bCCKTxRate			0x3000
+#define		bCCKDCCancel		0x0800
+#define		bCCKISICancel		0x0400
+#define		bCCKMatchFilter		0x0200
+#define		bCCKEqualizer		0x0100
+#define		bCCKPreambleDetect		0x800000
+#define		bCCKFastFalseCCA		0x400000
+#define		bCCKChEstStart		0x300000
+#define		bCCKCCACount		0x080000
+#define		bCCKcs_lim			0x070000
+#define		bCCKBistMode		0x80000000
+#define		bCCKCCAMask		0x40000000
+#define		bCCKTxDACPhase		0x4
+#define		bCCKRxADCPhase         	   	0x20000000   /* r_rx_clk */
+#define		bCCKr_cp_mode0		0x0100
+#define		bCCKTxDCOffset		0xf0
+#define		bCCKRxDCOffset		0xf
+#define		bCCKCCAMode		0xc000
+#define		bCCKFalseCS_lim		0x3f00
+#define		bCCKCS_ratio		0xc00000
+#define		bCCKCorgBit_sel		0x300000
+#define		bCCKPD_lim			0x0f0000
+#define		bCCKNewCCA		0x80000000
+#define		bCCKRxHPofIG		0x8000
+#define		bCCKRxIG			0x7f00
+#define		bCCKLNAPolarity		0x800000
+#define		bCCKRx1stGain		0x7f0000
+#define		bCCKRFExtend              		0x20000000 /* CCK Rx Iinital gain polarity */
+#define		bCCKRxAGCSatLevel		0x1f000000
+#define		bCCKRxAGCSatCount		0xe0
+#define		bCCKRxRFSettle            		0x1f       /* AGCsamp_dly */
+#define		bCCKFixedRxAGC		0x8000
+/* #define bCCKRxAGCFormat		0x4000 */   /* remove to HSSI register 0x824 */
+#define		bCCKAntennaPolarity		0x2000
+#define		bCCKTxFilterType		0x0c00
+#define		bCCKRxAGCReportType		0x0300
+#define		bCCKRxDAGCEn		0x80000000
+#define		bCCKRxDAGCPeriod		0x20000000
+#define		bCCKRxDAGCSatLevel		0x1f000000
+#define		bCCKTimingRecovery		0x800000
+#define		bCCKTxC0			0x3f0000
+#define		bCCKTxC1			0x3f000000
+#define		bCCKTxC2			0x3f
+#define		bCCKTxC3			0x3f00
+#define		bCCKTxC4			0x3f0000
+#define		bCCKTxC5			0x3f000000
+#define		bCCKTxC6			0x3f
+#define		bCCKTxC7			0x3f00
+#define		bCCKDebugPort		0xff0000
+#define		bCCKDACDebug		0x0f000000
+#define		bCCKFalseAlarmEnable		0x8000
+#define		bCCKFalseAlarmRead		0x4000
+#define		bCCKTRSSI			0x7f
+#define		bCCKRxAGCReport		0xfe
+#define		bCCKRxReport_AntSel		0x80000000
+#define		bCCKRxReport_MFOff		0x40000000
+#define		bCCKRxRxReport_SQLoss	0x20000000
+#define		bCCKRxReport_Pktloss		0x10000000
+#define		bCCKRxReport_Lockedbit	0x08000000
+#define		bCCKRxReport_RateError	0x04000000
+#define		bCCKRxReport_RxRate		0x03000000
+#define		bCCKRxFACounterLower	0xff
+#define		bCCKRxFACounterUpper	0xff000000
+#define		bCCKRxHPAGCStart		0xe000
+#define		bCCKRxHPAGCFinal		0x1c00
+#define		bCCKRxFalseAlarmEnable	0x8000
+#define		bCCKFACounterFreeze		0x4000
+#define		bCCKTxPathSel		0x10000000
+#define		bCCKDefaultRxPath		0xc000000
+#define		bCCKOptionRxPath		0x3000000
+
+/* 5. PageC(0xC00) */
+#define		bNumOfSTF                			0x3	/* Useless */
+#define		bShift_L			0xc0
+#define		bGI_TH			0xc
+#define		bRxPathA			0x1
+#define		bRxPathB			0x2
+#define		bRxPathC			0x4
+#define		bRxPathD			0x8
+#define		bTxPathA			0x1
+#define		bTxPathB			0x2
+#define		bTxPathC			0x4
+#define		bTxPathD			0x8
+#define		bTRSSIFreq			0x200
+#define		bADCBackoff			0x3000
+#define		bDFIRBackoff			0xc000
+#define		bTRSSILatchPhase		0x10000
+#define		bRxIDCOffset			0xff
+#define		bRxQDCOffset			0xff00
+#define		bRxDFIRMode		0x1800000
+#define		bRxDCNFType		0xe000000
+#define		bRXIQImb_A			0x3ff
+#define		bRXIQImb_B			0xfc00
+#define		bRXIQImb_C			0x3f0000
+#define		bRXIQImb_D			0xffc00000
+#define		bDC_dc_Notch		0x60000
+#define		bRxNBINotch			0x1f000000
+#define		bPD_TH			0xf
+#define		bPD_TH_Opt2		0xc000
+#define		bPWED_TH			0x700
+#define		bIfMF_Win_L			0x800
+#define		bPD_Option			0x1000
+#define		bMF_Win_L			0xe000
+#define		bBW_Search_L		0x30000
+#define		bwin_enh_L			0xc0000
+#define		bBW_TH			0x700000
+#define		bED_TH2			0x3800000
+#define		bBW_option			0x4000000
+#define		bRatio_TH			0x18000000
+#define		bWindow_L			0xe0000000
+#define		bSBD_Option			0x1
+#define		bFrame_TH			0x1c
+#define		bFS_Option			0x60
+#define		bDC_Slope_check		0x80
+#define		bFGuard_Counter_DC_L		0xe00
+#define		bFrame_Weight_Short		0x7000
+#define		bSub_Tune			0xe00000
+#define		bFrame_DC_Length		0xe000000
+#define		bSBD_start_offset		0x30000000
+#define		bFrame_TH_2		0x7
+#define		bFrame_GI2_TH		0x38
+#define		bGI2_Sync_en		0x40
+#define		bSarch_Short_Early		0x300
+#define		bSarch_Short_Late		0xc00
+#define		bSarch_GI2_Late		0x70000
+#define		bCFOAntSum		0x1
+#define		bCFOAcc			0x2
+#define		bCFOStartOffset		0xc
+#define		bCFOLookBack		0x70
+#define		bCFOSumWeight		0x80
+#define		bDAGCEnable			0x10000
+#define		bTXIQImb_A			0x3ff
+#define		bTXIQImb_B			0xfc00
+#define		bTXIQImb_C			0x3f0000
+#define		bTXIQImb_D			0xffc00000
+#define		bTxIDCOffset			0xff
+#define		bTxQDCOffset			0xff00
+#define		bTxDFIRMode		0x10000
+#define		bTxPesudoNoiseOn		0x4000000
+#define		bTxPesudoNoise_A		0xff
+#define		bTxPesudoNoise_B		0xff00
+#define		bTxPesudoNoise_C		0xff0000
+#define		bTxPesudoNoise_D		0xff000000
+#define		bCCADropOption		0x20000
+#define		bCCADropThres		0xfff00000
+#define		bEDCCA_H			0xf
+#define		bEDCCA_L			0xf0
+#define		bLambda_ED               0x300
+#define		bRxInitialGain           0x7f
+#define		bRxAntDivEn              0x80
+#define		bRxAGCAddressForLNA      0x7f00
+#define		bRxHighPowerFlow         0x8000
+#define		bRxAGCFreezeThres        0xc0000
+#define		bRxFreezeStep_AGC1       0x300000
+#define		bRxFreezeStep_AGC2       0xc00000
+#define		bRxFreezeStep_AGC3       0x3000000
+#define		bRxFreezeStep_AGC0       0xc000000
+#define		bRxRssi_Cmp_En           0x10000000
+#define		bRxQuickAGCEn            0x20000000
+#define		bRxAGCFreezeThresMode    0x40000000
+#define		bRxOverFlowCheckType     0x80000000
+#define		bRxAGCShift              0x7f
+#define		bTRSW_Tri_Only           0x80
+#define		bPowerThres              0x300
+#define		bRxAGCEn                 0x1
+#define		bRxAGCTogetherEn         0x2
+#define		bRxAGCMin                0x4
+#define		bRxHP_Ini                0x7
+#define		bRxHP_TRLNA              0x70
+#define		bRxHP_RSSI               0x700
+#define		bRxHP_BBP1               0x7000
+#define		bRxHP_BBP2               0x70000
+#define		bRxHP_BBP3               0x700000
+#define		bRSSI_H                  0x7f0000     /* the threshold for high power */
+#define		bRSSI_Gen                0x7f000000   /* the threshold for ant diversity */
+#define		bRxSettle_TRSW           0x7
+#define		bRxSettle_LNA            0x38
+#define		bRxSettle_RSSI           0x1c0
+#define		bRxSettle_BBP            0xe00
+#define		bRxSettle_RxHP           0x7000
+#define		bRxSettle_AntSW_RSSI     0x38000
+#define		bRxSettle_AntSW          0xc0000
+#define		bRxProcessTime_DAGC      0x300000
+#define		bRxSettle_HSSI           0x400000
+#define		bRxProcessTime_BBPPW     0x800000
+#define		bRxAntennaPowerShift     0x3000000
+#define		bRSSITableSelect         0xc000000
+#define		bRxHP_Final              0x7000000
+#define		bRxHTSettle_BBP          0x7
+#define		bRxHTSettle_HSSI         0x8
+#define		bRxHTSettle_RxHP         0x70
+#define		bRxHTSettle_BBPPW        0x80
+#define		bRxHTSettle_Idle         0x300
+#define		bRxHTSettle_Reserved     0x1c00
+#define		bRxHTRxHPEn              0x8000
+#define		bRxHTAGCFreezeThres      0x30000
+#define		bRxHTAGCTogetherEn       0x40000
+#define		bRxHTAGCMin              0x80000
+#define		bRxHTAGCEn               0x100000
+#define		bRxHTDAGCEn              0x200000
+#define		bRxHTRxHP_BBP            0x1c00000
+#define		bRxHTRxHP_Final          0xe0000000
+#define		bRxPWRatioTH             0x3
+#define		bRxPWRatioEn             0x4
+#define		bRxMFHold                0x3800
+#define		bRxPD_Delay_TH1          0x38
+#define		bRxPD_Delay_TH2          0x1c0
+#define		bRxPD_DC_COUNT_MAX       0x600
+/* #define bRxMF_Hold               0x3800 */
+#define		bRxPD_Delay_TH           0x8000
+#define		bRxProcess_Delay         0xf0000
+#define		bRxSearchrange_GI2_Early 0x700000
+#define		bRxFrame_Guard_Counter_L 0x3800000
+#define		bRxSGI_Guard_L           0xc000000
+#define		bRxSGI_Search_L          0x30000000
+#define		bRxSGI_TH                0xc0000000
+#define		bDFSCnt0                 0xff
+#define		bDFSCnt1                 0xff00
+#define		bDFSFlag                 0xf0000
+#define		bMFWeightSum             0x300000
+#define		bMinIdxTH                0x7f000000
+#define		bDAFormat                0x40000
+#define		bTxChEmuEnable           0x01000000
+#define		bTRSWIsolation_A         0x7f
+#define		bTRSWIsolation_B         0x7f00
+#define		bTRSWIsolation_C         0x7f0000
+#define		bTRSWIsolation_D         0x7f000000
+#define		bExtLNAGain              0x7c00
+
+/* 6. PageE(0xE00) */
+#define		bSTBCEn                  0x4	/* Useless */
+#define		bAntennaMapping          0x10
+#define		bNss                     0x20
+#define		bCFOAntSumD              0x200
+#define		bPHYCounterReset         0x8000000
+#define		bCFOReportGet            0x4000000
+#define		bOFDMContinueTx          0x10000000
+#define		bOFDMSingleCarrier       0x20000000
+#define		bOFDMSingleTone          0x40000000
+/* #define bRxPath1                 0x01 */
+/* #define bRxPath2                 0x02 */
+/* #define bRxPath3                 0x04 */
+/* #define bRxPath4                 0x08 */
+/* #define bTxPath1                 0x10 */
+/* #define bTxPath2                 0x20 */
+#define		bHTDetect                0x100
+#define		bCFOEn                   0x10000
+#define		bCFOValue                0xfff00000
+#define		bSigTone_Re              0x3f
+#define		bSigTone_Im              0x7f00
+#define		bCounter_CCA             0xffff
+#define		bCounter_ParityFail      0xffff0000
+#define		bCounter_RateIllegal     0xffff
+#define		bCounter_CRC8Fail        0xffff0000
+#define		bCounter_MCSNoSupport    0xffff
+#define		bCounter_FastSync        0xffff
+#define		bShortCFO                0xfff
+#define		bShortCFOTLength         12   /* total */
+#define		bShortCFOFLength         11   /* fraction */
+#define		bLongCFO                 0x7ff
+#define		bLongCFOTLength          11
+#define		bLongCFOFLength          11
+#define		bTailCFO                 0x1fff
+#define		bTailCFOTLength          13
+#define		bTailCFOFLength          12
+#define		bmax_en_pwdB             0xffff
+#define		bCC_power_dB             0xffff0000
+#define		bnoise_pwdB              0xffff
+#define		bPowerMeasTLength        10
+#define		bPowerMeasFLength        3
+#define		bRx_HT_BW                0x1
+#define		bRxSC                    0x6
+#define		bRx_HT                   0x8
+#define		bNB_intf_det_on          0x1
+#define		bIntf_win_len_cfg        0x30
+#define		bNB_Intf_TH_cfg          0x1c0
+#define		bRFGain                  0x3f
+#define		bTableSel                0x40
+#define		bTRSW                    0x80
+#define		bRxSNR_A                 0xff
+#define		bRxSNR_B                 0xff00
+#define		bRxSNR_C                 0xff0000
+#define		bRxSNR_D                 0xff000000
+#define		bSNREVMTLength           8
+#define		bSNREVMFLength           1
+#define		bCSI1st                  0xff
+#define		bCSI2nd                  0xff00
+#define		bRxEVM1st                0xff0000
+#define		bRxEVM2nd                0xff000000
+#define		bSIGEVM                  0xff
+#define		bPWDB                    0xff00
+#define		bSGIEN                   0x10000
+
+#define		bSFactorQAM1             0xf	/* Useless */
+#define		bSFactorQAM2             0xf0
+#define		bSFactorQAM3             0xf00
+#define		bSFactorQAM4             0xf000
+#define		bSFactorQAM5             0xf0000
+#define		bSFactorQAM6             0xf0000
+#define		bSFactorQAM7             0xf00000
+#define		bSFactorQAM8             0xf000000
+#define		bSFactorQAM9             0xf0000000
+#define		bCSIScheme               0x100000
+
+#define		bNoiseLvlTopSet          0x3	/* Useless */
+#define		bChSmooth                0x4
+#define		bChSmoothCfg1            0x38
+#define		bChSmoothCfg2            0x1c0
+#define		bChSmoothCfg3            0xe00
+#define		bChSmoothCfg4            0x7000
+#define		bMRCMode                 0x800000
+#define		bTHEVMCfg                0x7000000
+
+#define		bLoopFitType             0x1	/* Useless */
+#define		bUpdCFO                  0x40
+#define		bUpdCFOOffData           0x80
+#define		bAdvUpdCFO               0x100
+#define		bAdvTimeCtrl             0x800
+#define		bUpdClko                 0x1000
+#define		bFC                      0x6000
+#define		bTrackingMode            0x8000
+#define		bPhCmpEnable             0x10000
+#define		bUpdClkoLTF              0x20000
+#define		bComChCFO                0x40000
+#define		bCSIEstiMode             0x80000
+#define		bAdvUpdEqz               0x100000
+#define		bUChCfg                  0x7000000
+#define		bUpdEqz                  0x8000000
+
+#define		bTxAGCRate18_06			0x7f7f7f7f	/* Useless */
+#define		bTxAGCRate54_24			0x7f7f7f7f
+#define		bTxAGCRateMCS32			0x7f
+#define		bTxAGCRateCCK			0x7f00
+#define		bTxAGCRateMCS3_MCS0		0x7f7f7f7f
+#define		bTxAGCRateMCS7_MCS4		0x7f7f7f7f
+#define		bTxAGCRateMCS11_MCS8	0x7f7f7f7f
+#define		bTxAGCRateMCS15_MCS12	0x7f7f7f7f
+
+/* Rx Pseduo noise */
+#define		bRxPesudoNoiseOn         0x20000000	/* Useless */
+#define		bRxPesudoNoise_A         0xff
+#define		bRxPesudoNoise_B         0xff00
+#define		bRxPesudoNoise_C         0xff0000
+#define		bRxPesudoNoise_D         0xff000000
+#define		bPesudoNoiseState_A      0xffff
+#define		bPesudoNoiseState_B      0xffff0000
+#define		bPesudoNoiseState_C      0xffff
+#define		bPesudoNoiseState_D      0xffff0000
+
+/* 7. RF Register
+ * Zebra1 */
+#define		bZebra1_HSSIEnable        0x8		/* Useless */
+#define		bZebra1_TRxControl        0xc00
+#define		bZebra1_TRxGainSetting    0x07f
+#define		bZebra1_RxCorner          0xc00
+#define		bZebra1_TxChargePump      0x38
+#define		bZebra1_RxChargePump      0x7
+#define		bZebra1_ChannelNum        0xf80
+#define		bZebra1_TxLPFBW           0x400
+#define		bZebra1_RxLPFBW           0x600
+
+/* Zebra4 */
+#define		bRTL8256RegModeCtrl1      0x100	/* Useless */
+#define		bRTL8256RegModeCtrl0      0x40
+#define		bRTL8256_TxLPFBW          0x18
+#define		bRTL8256_RxLPFBW          0x600
+
+/* RTL8258 */
+#define		bRTL8258_TxLPFBW          0xc	/* Useless */
+#define		bRTL8258_RxLPFBW          0xc00
+#define		bRTL8258_RSSILPFBW        0xc0
+
+
+/*
+ * Other Definition
+ *   */
+
+/* byte endable for sb_write */
+#define		bByte0                    0x1	/* Useless */
+#define		bByte1                    0x2
+#define		bByte2                    0x4
+#define		bByte3                    0x8
+#define		bWord0                    0x3
+#define		bWord1                    0xc
+#define		bDWord                    0xf
+
+/* for PutRegsetting & GetRegSetting BitMask */
+#define		bMaskByte0		0xff	/* Reg 0xc50 rOFDM0_XAAGCCore~0xC6f */
+#define		bMaskByte1		0xff00
+#define		bMaskByte2		0xff0000
+#define		bMaskByte3		0xff000000
+#define		bMaskHWord	0xffff0000
+#define		bMaskLWord		0x0000ffff
+#define		bMaskDWord	0xffffffff
+#define		bMaskH4Bits		0xf0000000
+#define		bMaskH3Bytes	0xffffff00
+#define		bMaskOFDM_D	0xffc00000
+#define		bMaskCCK		0x3f3f3f3f
+#define		bMask12Bits		0xfff
+
+/* for PutRFRegsetting & GetRFRegSetting BitMask */
+#if (RTL92SE_FPGA_VERIFY == 1)
+/* #define		bMask12Bits               0xfff */	/* RF Reg mask bits */
+/* #define		bMask20Bits               0xfff */	/* RF Reg mask bits T65 RF */
+#define		bRFRegOffsetMask	0xfff
+#else
+/* #define		bMask12Bits               0xfffff */	/* RF Reg mask bits */
+/* #define		bMask20Bits               0xfffff */	/* RF Reg mask bits T65 RF */
+#define		bRFRegOffsetMask	0xfffff
+#endif
+#define		bEnable                   0x1	/* Useless */
+#define		bDisable                  0x0
+
+#define		LeftAntenna               0x0	/* Useless */
+#define		RightAntenna              0x1
+
+#define		tCheckTxStatus            500   /* 500ms */ /* Useless */
+#define		tUpdateRxCounter          100   /* 100ms */
+
+#define		rateCCK     0	/* Useless */
+#define		rateOFDM    1
+#define		rateHT      2
+
+/* define Register-End */
+#define		bPMAC_End                 0x1ff	/* Useless */
+#define		bFPGAPHY0_End             0x8ff
+#define		bFPGAPHY1_End             0x9ff
+#define		bCCKPHY0_End              0xaff
+#define		bOFDMPHY0_End             0xcff
+#define		bOFDMPHY1_End             0xdff
+
+/* define max debug item in each debug page
+ * #define bMaxItem_FPGA_PHY0        0x9
+ * #define bMaxItem_FPGA_PHY1        0x3
+ * #define bMaxItem_PHY_11B          0x16
+ * #define bMaxItem_OFDM_PHY0        0x29
+ * #define bMaxItem_OFDM_PHY1        0x0 */
+
+#define		bPMACControl	0x0		/* Useless */
+#define		bWMACControl	0x1
+#define		bWNICControl	0x2
+
+#if 0
+#define		ANTENNA_A	0x1	/* Useless */
+#define		ANTENNA_B	0x2
+#define		ANTENNA_AB	0x3	/* ANTENNA_A | ANTENNA_B */
+
+#define		ANTENNA_C	0x4
+#define		ANTENNA_D	0x8
+#endif
+
+#define RCR_AAP			BIT(0)				/* accept all physical address */
+#define RCR_APM			BIT(1)				/* accept physical match */
+#define RCR_AM			BIT(2)				/* accept multicast */
+#define RCR_AB			BIT(3)				/* accept broadcast */
+#define RCR_ACRC32		BIT(5)				/* accept error packet */
+#define RCR_9356SEL		BIT(6)
+#define RCR_AICV		BIT(9)				/* Accept ICV error packet */
+#define RCR_RXFTH0		(BIT(13) | BIT(14) | BIT(15))	/* Rx FIFO threshold */
+#define RCR_ADF			BIT(18)				/* Accept Data(frame type) frame */
+#define RCR_ACF			BIT(19)				/* Accept control frame */
+#define RCR_AMF			BIT(20)				/* Accept management frame */
+#define RCR_ADD3		BIT(21)
+#define RCR_APWRMGT		BIT(22)				/* Accept power management packet */
+#define RCR_CBSSID		BIT(23)				/* Accept BSSID match packet */
+#define RCR_ENMARP		BIT(28)				/* enable mac auto reset phy */
+#define RCR_EnCS1		BIT(29)				/* enable carrier sense method 1 */
+#define RCR_EnCS2		BIT(30)				/* enable carrier sense method 2 */
+#define RCR_OnlyErlPkt		BIT(31)				/* Rx Early mode is performed for packet size greater than 1536 */
+
+/*--------------------------Define Parameters-------------------------------*/
+
+
+#endif /* __INC_HAL8192SPHYREG_H */
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/include/rtw_odm.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/rtw_odm.h
--- linux-5.6.3/3rdparty/rtl8821ce/include/rtw_odm.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/rtw_odm.h	2020-04-10 16:35:06.852661748 +0300
@@ -0,0 +1,97 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2013 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#ifndef __RTW_ODM_H__
+#define __RTW_ODM_H__
+
+#include <drv_types.h>
+#include "../hal/phydm/phydm_types.h"
+/*
+* This file provides utilities/wrappers for rtw driver to use ODM
+*/
+typedef enum _HAL_PHYDM_OPS {
+	HAL_PHYDM_DIS_ALL_FUNC,
+	HAL_PHYDM_FUNC_SET,
+	HAL_PHYDM_FUNC_CLR,
+	HAL_PHYDM_ABILITY_BK,
+	HAL_PHYDM_ABILITY_RESTORE,
+	HAL_PHYDM_ABILITY_SET,
+	HAL_PHYDM_ABILITY_GET,
+} HAL_PHYDM_OPS;
+
+
+#define DYNAMIC_FUNC_DISABLE		(0x0)
+	u32 rtw_phydm_ability_ops(_adapter *adapter, HAL_PHYDM_OPS ops, u32 ability);
+
+#define rtw_phydm_func_disable_all(adapter)	\
+		rtw_phydm_ability_ops(adapter, HAL_PHYDM_DIS_ALL_FUNC, 0)
+
+#ifdef CONFIG_RTW_ACS
+#define rtw_phydm_func_for_offchannel(adapter) \
+		do { \
+			rtw_phydm_ability_ops(adapter, HAL_PHYDM_DIS_ALL_FUNC, 0); \
+			if (rtw_odm_adaptivity_needed(adapter)) \
+				rtw_phydm_ability_ops(adapter, HAL_PHYDM_FUNC_SET, ODM_BB_ADAPTIVITY); \
+			if (IS_ACS_ENABLE(adapter))\
+				rtw_phydm_ability_ops(adapter, HAL_PHYDM_FUNC_SET, ODM_BB_ENV_MONITOR); \
+		} while (0)
+#else
+#define rtw_phydm_func_for_offchannel(adapter) \
+		do { \
+			rtw_phydm_ability_ops(adapter, HAL_PHYDM_DIS_ALL_FUNC, 0); \
+			if (rtw_odm_adaptivity_needed(adapter)) \
+				rtw_phydm_ability_ops(adapter, HAL_PHYDM_FUNC_SET, ODM_BB_ADAPTIVITY); \
+		} while (0)
+#endif
+
+#define rtw_phydm_func_clr(adapter, ability)	\
+		rtw_phydm_ability_ops(adapter, HAL_PHYDM_FUNC_CLR, ability)
+
+#define rtw_phydm_ability_backup(adapter)	\
+		rtw_phydm_ability_ops(adapter, HAL_PHYDM_ABILITY_BK, 0)
+
+#define rtw_phydm_ability_restore(adapter)	\
+		rtw_phydm_ability_ops(adapter, HAL_PHYDM_ABILITY_RESTORE, 0)
+
+
+static inline u32 rtw_phydm_ability_get(_adapter *adapter)
+{
+	return rtw_phydm_ability_ops(adapter, HAL_PHYDM_ABILITY_GET, 0);
+}
+
+
+void rtw_odm_init_ic_type(_adapter *adapter);
+
+void rtw_odm_adaptivity_config_msg(void *sel, _adapter *adapter);
+
+bool rtw_odm_adaptivity_needed(_adapter *adapter);
+void rtw_odm_adaptivity_parm_msg(void *sel, _adapter *adapter);
+void rtw_odm_adaptivity_parm_set(_adapter *adapter, s8 th_l2h_ini, s8 th_edcca_hl_diff);
+void rtw_odm_get_perpkt_rssi(void *sel, _adapter *adapter);
+void rtw_odm_acquirespinlock(_adapter *adapter,	enum rt_spinlock_type type);
+void rtw_odm_releasespinlock(_adapter *adapter,	enum rt_spinlock_type type);
+
+u8 rtw_odm_get_dfs_domain(struct dvobj_priv *dvobj);
+u8 rtw_odm_dfs_domain_unknown(struct dvobj_priv *dvobj);
+#ifdef CONFIG_DFS_MASTER
+VOID rtw_odm_radar_detect_reset(_adapter *adapter);
+VOID rtw_odm_radar_detect_disable(_adapter *adapter);
+VOID rtw_odm_radar_detect_enable(_adapter *adapter);
+BOOLEAN rtw_odm_radar_detect(_adapter *adapter);
+u8 rtw_odm_radar_detect_polling_int_ms(struct dvobj_priv *dvobj);
+#endif /* CONFIG_DFS_MASTER */
+
+void rtw_odm_parse_rx_phy_status_chinfo(union recv_frame *rframe, u8 *phys);
+
+#endif /* __RTW_ODM_H__ */
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/include/rtw_p2p.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/rtw_p2p.h
--- linux-5.6.3/3rdparty/rtl8821ce/include/rtw_p2p.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/rtw_p2p.h	2020-04-10 16:35:06.852661748 +0300
@@ -0,0 +1,169 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#ifndef __RTW_P2P_H_
+#define __RTW_P2P_H_
+
+
+u32 build_beacon_p2p_ie(struct wifidirect_info *pwdinfo, u8 *pbuf);
+u32 build_probe_resp_p2p_ie(struct wifidirect_info *pwdinfo, u8 *pbuf);
+u32 build_prov_disc_request_p2p_ie(struct wifidirect_info *pwdinfo, u8 *pbuf, u8 *pssid, u8 ussidlen, u8 *pdev_raddr);
+u32 build_assoc_resp_p2p_ie(struct wifidirect_info *pwdinfo, u8 *pbuf, u8 status_code);
+u32 build_deauth_p2p_ie(struct wifidirect_info *pwdinfo, u8 *pbuf);
+#ifdef CONFIG_WFD
+int rtw_init_wifi_display_info(_adapter *padapter);
+void rtw_wfd_enable(_adapter *adapter, bool on);
+void rtw_wfd_set_ctrl_port(_adapter *adapter, u16 port);
+void rtw_tdls_wfd_enable(_adapter *adapter, bool on);
+
+u32 build_probe_req_wfd_ie(struct wifidirect_info *pwdinfo, u8 *pbuf);
+u32 build_probe_resp_wfd_ie(struct wifidirect_info *pwdinfo, u8 *pbuf, u8 tunneled);
+u32 build_beacon_wfd_ie(struct wifidirect_info *pwdinfo, u8 *pbuf);
+u32 build_nego_req_wfd_ie(struct wifidirect_info *pwdinfo, u8 *pbuf);
+u32 build_nego_resp_wfd_ie(struct wifidirect_info *pwdinfo, u8 *pbuf);
+u32 build_nego_confirm_wfd_ie(struct wifidirect_info *pwdinfo, u8 *pbuf);
+u32 build_invitation_req_wfd_ie(struct wifidirect_info *pwdinfo, u8 *pbuf);
+u32 build_invitation_resp_wfd_ie(struct wifidirect_info *pwdinfo, u8 *pbuf);
+u32 build_assoc_req_wfd_ie(struct wifidirect_info *pwdinfo, u8 *pbuf);
+u32 build_assoc_resp_wfd_ie(struct wifidirect_info *pwdinfo, u8 *pbuf);
+u32 build_provdisc_req_wfd_ie(struct wifidirect_info *pwdinfo, u8 *pbuf);
+u32 build_provdisc_resp_wfd_ie(struct wifidirect_info *pwdinfo, u8 *pbuf);
+
+u32 rtw_append_beacon_wfd_ie(_adapter *adapter, u8 *pbuf);
+u32 rtw_append_probe_req_wfd_ie(_adapter *adapter, u8 *pbuf);
+u32 rtw_append_probe_resp_wfd_ie(_adapter *adapter, u8 *pbuf);
+u32 rtw_append_assoc_req_wfd_ie(_adapter *adapter, u8 *pbuf);
+u32 rtw_append_assoc_resp_wfd_ie(_adapter *adapter, u8 *pbuf);
+#endif /*CONFIG_WFD */
+
+void rtw_xframe_chk_wfd_ie(struct xmit_frame *xframe);
+
+u32 process_probe_req_p2p_ie(struct wifidirect_info *pwdinfo, u8 *pframe, uint len);
+u32 process_assoc_req_p2p_ie(struct wifidirect_info *pwdinfo, u8 *pframe, uint len, struct sta_info *psta);
+u32 process_p2p_devdisc_req(struct wifidirect_info *pwdinfo, u8 *pframe, uint len);
+u32 process_p2p_devdisc_resp(struct wifidirect_info *pwdinfo, u8 *pframe, uint len);
+u8 process_p2p_provdisc_req(struct wifidirect_info *pwdinfo,  u8 *pframe, uint len);
+u8 process_p2p_provdisc_resp(struct wifidirect_info *pwdinfo,  u8 *pframe);
+u8 process_p2p_group_negotation_req(struct wifidirect_info *pwdinfo, u8 *pframe, uint len);
+u8 process_p2p_group_negotation_resp(struct wifidirect_info *pwdinfo, u8 *pframe, uint len);
+u8 process_p2p_group_negotation_confirm(struct wifidirect_info *pwdinfo, u8 *pframe, uint len);
+u8 process_p2p_presence_req(struct wifidirect_info *pwdinfo, u8 *pframe, uint len);
+int process_p2p_cross_connect_ie(PADAPTER padapter, u8 *IEs, u32 IELength);
+
+s32 p2p_protocol_wk_hdl(_adapter *padapter, int intCmdType, u8 *buf);
+
+#ifdef CONFIG_P2P_PS
+void	process_p2p_ps_ie(PADAPTER padapter, u8 *IEs, u32 IELength);
+void	p2p_ps_wk_hdl(_adapter *padapter, u8 p2p_ps_state);
+u8	p2p_ps_wk_cmd(_adapter *padapter, u8 p2p_ps_state, u8 enqueue);
+#endif /* CONFIG_P2P_PS */
+
+#ifdef CONFIG_IOCTL_CFG80211
+u8 roch_stay_in_cur_chan(_adapter *padapter);
+void rtw_init_cfg80211_wifidirect_info(_adapter	*padapter);
+int rtw_p2p_check_frames(_adapter *padapter, const u8 *buf, u32 len, u8 tx);
+#endif /* CONFIG_IOCTL_CFG80211 */
+
+void reset_global_wifidirect_info(_adapter *padapter);
+void rtw_init_wifidirect_timers(_adapter *padapter);
+void rtw_init_wifidirect_addrs(_adapter *padapter, u8 *dev_addr, u8 *iface_addr);
+void init_wifidirect_info(_adapter *padapter, enum P2P_ROLE role);
+int rtw_p2p_enable(_adapter *padapter, enum P2P_ROLE role);
+
+static inline void _rtw_p2p_set_state(struct wifidirect_info *wdinfo, enum P2P_STATE state)
+{
+	if (wdinfo->p2p_state != state) {
+		/* wdinfo->pre_p2p_state = wdinfo->p2p_state; */
+		wdinfo->p2p_state = state;
+	}
+}
+static inline void _rtw_p2p_set_pre_state(struct wifidirect_info *wdinfo, enum P2P_STATE state)
+{
+	if (wdinfo->pre_p2p_state != state)
+		wdinfo->pre_p2p_state = state;
+}
+#if 0
+static inline void _rtw_p2p_restore_state(struct wifidirect_info *wdinfo)
+{
+	if (wdinfo->pre_p2p_state != -1) {
+		wdinfo->p2p_state = wdinfo->pre_p2p_state;
+		wdinfo->pre_p2p_state = -1;
+	}
+}
+#endif
+void _rtw_p2p_set_role(struct wifidirect_info *wdinfo, enum P2P_ROLE role);
+
+static inline int _rtw_p2p_state(struct wifidirect_info *wdinfo)
+{
+	return wdinfo->p2p_state;
+}
+static inline int _rtw_p2p_pre_state(struct wifidirect_info *wdinfo)
+{
+	return wdinfo->pre_p2p_state;
+}
+static inline int _rtw_p2p_role(struct wifidirect_info *wdinfo)
+{
+	return wdinfo->role;
+}
+static inline bool _rtw_p2p_chk_state(struct wifidirect_info *wdinfo, enum P2P_STATE state)
+{
+	return wdinfo->p2p_state == state;
+}
+static inline bool _rtw_p2p_chk_role(struct wifidirect_info *wdinfo, enum P2P_ROLE role)
+{
+	return wdinfo->role == role;
+}
+
+#ifdef CONFIG_DBG_P2P
+void dbg_rtw_p2p_set_state(struct wifidirect_info *wdinfo, enum P2P_STATE state, const char *caller, int line);
+void dbg_rtw_p2p_set_pre_state(struct wifidirect_info *wdinfo, enum P2P_STATE state, const char *caller, int line);
+/* void dbg_rtw_p2p_restore_state(struct wifidirect_info *wdinfo, const char *caller, int line); */
+void dbg_rtw_p2p_set_role(struct wifidirect_info *wdinfo, enum P2P_ROLE role, const char *caller, int line);
+#define rtw_p2p_set_state(wdinfo, state) dbg_rtw_p2p_set_state(wdinfo, state, __FUNCTION__, __LINE__)
+#define rtw_p2p_set_pre_state(wdinfo, state) dbg_rtw_p2p_set_pre_state(wdinfo, state, __FUNCTION__, __LINE__)
+#define rtw_p2p_set_role(wdinfo, role) dbg_rtw_p2p_set_role(wdinfo, role, __FUNCTION__, __LINE__)
+/* #define rtw_p2p_restore_state(wdinfo) dbg_rtw_p2p_restore_state(wdinfo, __FUNCTION__, __LINE__) */
+#else /* CONFIG_DBG_P2P */
+#define rtw_p2p_set_state(wdinfo, state) _rtw_p2p_set_state(wdinfo, state)
+#define rtw_p2p_set_pre_state(wdinfo, state) _rtw_p2p_set_pre_state(wdinfo, state)
+#define rtw_p2p_set_role(wdinfo, role) _rtw_p2p_set_role(wdinfo, role)
+/* #define rtw_p2p_restore_state(wdinfo) _rtw_p2p_restore_state(wdinfo) */
+#endif /* CONFIG_DBG_P2P */
+
+#define rtw_p2p_state(wdinfo) _rtw_p2p_state(wdinfo)
+#define rtw_p2p_pre_state(wdinfo) _rtw_p2p_pre_state(wdinfo)
+#define rtw_p2p_role(wdinfo) _rtw_p2p_role(wdinfo)
+#define rtw_p2p_chk_state(wdinfo, state) _rtw_p2p_chk_state(wdinfo, state)
+#define rtw_p2p_chk_role(wdinfo, role) _rtw_p2p_chk_role(wdinfo, role)
+
+#define rtw_p2p_findphase_ex_set(wdinfo, value) \
+	(wdinfo)->find_phase_state_exchange_cnt = (value)
+
+#ifdef CONFIG_P2P
+/* is this find phase exchange for social channel scan? */
+#define rtw_p2p_findphase_ex_is_social(wdinfo)   \
+	(wdinfo)->find_phase_state_exchange_cnt >= P2P_FINDPHASE_EX_SOCIAL_FIRST
+
+/* should we need find phase exchange anymore? */
+#define rtw_p2p_findphase_ex_is_needed(wdinfo) \
+	((wdinfo)->find_phase_state_exchange_cnt < P2P_FINDPHASE_EX_MAX && \
+	 (wdinfo)->find_phase_state_exchange_cnt != P2P_FINDPHASE_EX_NONE && \
+	 !(wdinfo)->rx_invitereq_info.scan_op_ch_only && \
+	 !(wdinfo)->p2p_info.scan_op_ch_only)
+#else
+#define rtw_p2p_findphase_ex_is_social(wdinfo) 0
+#define rtw_p2p_findphase_ex_is_needed(wdinfo) 0
+#endif /* CONFIG_P2P */
+
+#endif
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/include/rtw_pwrctrl.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/rtw_pwrctrl.h
--- linux-5.6.3/3rdparty/rtl8821ce/include/rtw_pwrctrl.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/rtw_pwrctrl.h	2020-04-10 16:35:06.852661748 +0300
@@ -0,0 +1,608 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#ifndef __RTW_PWRCTRL_H_
+#define __RTW_PWRCTRL_H_
+
+
+#define FW_PWR0	0
+#define FW_PWR1	1
+#define FW_PWR2	2
+#define FW_PWR3	3
+
+
+#define HW_PWR0	7
+#define HW_PWR1	6
+#define HW_PWR2	2
+#define HW_PWR3	0
+#define HW_PWR4	8
+
+#define FW_PWRMSK	0x7
+
+
+#define XMIT_ALIVE	BIT(0)
+#define RECV_ALIVE	BIT(1)
+#define CMD_ALIVE	BIT(2)
+#define EVT_ALIVE	BIT(3)
+#ifdef CONFIG_BT_COEXIST
+#define BTCOEX_ALIVE	BIT(4)
+#endif /* CONFIG_BT_COEXIST */
+
+#ifdef CONFIG_WOWLAN
+	#ifdef CONFIG_PLATFORM_ANDROID_INTEL_X86
+		/* TCP/ICMP/UDP multicast with specific IP addr */
+		#define DEFAULT_PATTERN_NUM 4
+	#else
+		/* TCP/ICMP */
+		#define DEFAULT_PATTERN_NUM 3
+	#endif
+
+#ifdef CONFIG_WOW_PATTERN_HW_CAM	/* Frame Mask Cam number for pattern match */
+#define MAX_WKFM_CAM_NUM	12
+#else
+#define MAX_WKFM_CAM_NUM	16
+#endif
+
+#define MAX_WKFM_SIZE	16 /* (16 bytes for WKFM bit mask, 16*8 = 128 bits) */
+#define MAX_WKFM_PATTERN_SIZE	128
+#define WKFMCAM_ADDR_NUM 6
+#define WKFMCAM_SIZE 24 /* each entry need 6*4 bytes */
+enum pattern_type {
+	PATTERN_BROADCAST = 0,
+	PATTERN_MULTICAST,
+	PATTERN_UNICAST,
+	PATTERN_VALID,
+	PATTERN_INVALID,
+};
+
+typedef struct rtl_priv_pattern {
+	int len;
+	char content[MAX_WKFM_PATTERN_SIZE];
+	char mask[MAX_WKFM_SIZE];
+} rtl_priv_pattern_t;
+
+#endif /* CONFIG_WOWLAN */
+
+enum Power_Mgnt {
+	PS_MODE_ACTIVE	= 0	,
+	PS_MODE_MIN			,
+	PS_MODE_MAX			,
+	PS_MODE_DTIM			,	/* PS_MODE_SELF_DEFINED */
+	PS_MODE_VOIP			,
+	PS_MODE_UAPSD_WMM	,
+	PS_MODE_UAPSD			,
+	PS_MODE_IBSS			,
+	PS_MODE_WWLAN		,
+	PM_Radio_Off			,
+	PM_Card_Disable		,
+	PS_MODE_NUM,
+};
+
+enum lps_level {
+	LPS_NORMAL = 0,
+	LPS_LCLK,
+	LPS_PG,
+	LPS_LEVEL_MAX,
+};
+
+#ifdef CONFIG_PNO_SUPPORT
+#define MAX_PNO_LIST_COUNT 16
+#define MAX_SCAN_LIST_COUNT 14	/* 2.4G only */
+#define MAX_HIDDEN_AP 8		/* 8 hidden AP */
+#endif
+
+/*
+	BIT[2:0] = HW state
+	BIT[3] = Protocol PS state,   0: register active state , 1: register sleep state
+	BIT[4] = sub-state
+*/
+
+#define PS_DPS				BIT(0)
+#define PS_LCLK				(PS_DPS)
+#define PS_RF_OFF			BIT(1)
+#define PS_ALL_ON			BIT(2)
+#define PS_ST_ACTIVE		BIT(3)
+
+#define PS_ISR_ENABLE		BIT(4)
+#define PS_IMR_ENABLE		BIT(5)
+#define PS_ACK				BIT(6)
+#define PS_TOGGLE			BIT(7)
+
+#define PS_STATE_MASK		(0x0F)
+#define PS_STATE_HW_MASK	(0x07)
+#define PS_SEQ_MASK			(0xc0)
+
+#define PS_STATE(x)		(PS_STATE_MASK & (x))
+#define PS_STATE_HW(x)	(PS_STATE_HW_MASK & (x))
+#define PS_SEQ(x)		(PS_SEQ_MASK & (x))
+
+#define PS_STATE_S0		(PS_DPS)
+#define PS_STATE_S1		(PS_LCLK)
+#define PS_STATE_S2		(PS_RF_OFF)
+#define PS_STATE_S3		(PS_ALL_ON)
+#define PS_STATE_S4		((PS_ST_ACTIVE) | (PS_ALL_ON))
+
+
+#define PS_IS_RF_ON(x)	((x) & (PS_ALL_ON))
+#define PS_IS_ACTIVE(x)	((x) & (PS_ST_ACTIVE))
+#define CLR_PS_STATE(x)	((x) = ((x) & (0xF0)))
+
+
+struct reportpwrstate_parm {
+	unsigned char mode;
+	unsigned char state; /* the CPWM value */
+	unsigned short rsvd;
+};
+
+
+typedef _sema _pwrlock;
+
+
+__inline static void _init_pwrlock(_pwrlock *plock)
+{
+	_rtw_init_sema(plock, 1);
+}
+
+__inline static void _free_pwrlock(_pwrlock *plock)
+{
+	_rtw_free_sema(plock);
+}
+
+
+__inline static void _enter_pwrlock(_pwrlock *plock)
+{
+	_rtw_down_sema(plock);
+}
+
+
+__inline static void _exit_pwrlock(_pwrlock *plock)
+{
+	_rtw_up_sema(plock);
+}
+
+#define LPS_DELAY_MS	1000 /* 1 sec */
+
+#define EXE_PWR_NONE	0x01
+#define EXE_PWR_IPS		0x02
+#define EXE_PWR_LPS		0x04
+
+/* RF state. */
+typedef enum _rt_rf_power_state {
+	rf_on,		/* RF is on after RFSleep or RFOff */
+	rf_sleep,	/* 802.11 Power Save mode */
+	rf_off,		/* HW/SW Radio OFF or Inactive Power Save */
+	/* =====Add the new RF state above this line===== */
+	rf_max
+} rt_rf_power_state;
+
+/* RF Off Level for IPS or HW/SW radio off */
+#define	RT_RF_OFF_LEVL_ASPM			BIT(0)	/* PCI ASPM */
+#define	RT_RF_OFF_LEVL_CLK_REQ		BIT(1)	/* PCI clock request */
+#define	RT_RF_OFF_LEVL_PCI_D3			BIT(2)	/* PCI D3 mode */
+#define	RT_RF_OFF_LEVL_HALT_NIC		BIT(3)	/* NIC halt, re-initialize hw parameters */
+#define	RT_RF_OFF_LEVL_FREE_FW		BIT(4)	/* FW free, re-download the FW */
+#define	RT_RF_OFF_LEVL_FW_32K		BIT(5)	/* FW in 32k */
+#define	RT_RF_PS_LEVEL_ALWAYS_ASPM	BIT(6)	/* Always enable ASPM and Clock Req in initialization. */
+#define	RT_RF_LPS_DISALBE_2R			BIT(30)	/* When LPS is on, disable 2R if no packet is received or transmittd. */
+#define	RT_RF_LPS_LEVEL_ASPM			BIT(31)	/* LPS with ASPM */
+
+#define	RT_IN_PS_LEVEL(ppsc, _PS_FLAG)		((ppsc->cur_ps_level & _PS_FLAG) ? _TRUE : _FALSE)
+#define	RT_CLEAR_PS_LEVEL(ppsc, _PS_FLAG)	(ppsc->cur_ps_level &= (~(_PS_FLAG)))
+#define	RT_SET_PS_LEVEL(ppsc, _PS_FLAG)		(ppsc->cur_ps_level |= _PS_FLAG)
+
+/* ASPM OSC Control bit, added by Roger, 2013.03.29. */
+#define	RT_PCI_ASPM_OSC_IGNORE		0	 /* PCI ASPM ignore OSC control in default */
+#define	RT_PCI_ASPM_OSC_ENABLE		BIT0 /* PCI ASPM controlled by OS according to ACPI Spec 5.0 */
+#define	RT_PCI_ASPM_OSC_DISABLE		BIT1 /* PCI ASPM controlled by driver or BIOS, i.e., force enable ASPM */
+
+
+enum _PS_BBRegBackup_ {
+	PSBBREG_RF0 = 0,
+	PSBBREG_RF1,
+	PSBBREG_RF2,
+	PSBBREG_AFE0,
+	PSBBREG_TOTALCNT
+};
+
+enum { /* for ips_mode */
+	IPS_NONE = 0,
+	IPS_NORMAL,
+	IPS_LEVEL_2,
+	IPS_NUM
+};
+
+/* Design for pwrctrl_priv.ips_deny, 32 bits for 32 reasons at most */
+typedef enum _PS_DENY_REASON {
+	PS_DENY_DRV_INITIAL = 0,
+	PS_DENY_SCAN,
+	PS_DENY_JOIN,
+	PS_DENY_DISCONNECT,
+	PS_DENY_SUSPEND,
+	PS_DENY_IOCTL,
+	PS_DENY_MGNT_TX,
+	PS_DENY_MONITOR_MODE,
+	PS_DENY_BEAMFORMING,		/* Beamforming */
+	PS_DENY_DRV_REMOVE = 30,
+	PS_DENY_OTHERS = 31
+} PS_DENY_REASON;
+
+#ifdef CONFIG_PNO_SUPPORT
+typedef struct pno_nlo_info {
+	u32 fast_scan_period;				/* Fast scan period */
+	u8	ssid_num;				/* number of entry */
+	u8	hidden_ssid_num;
+	u32	slow_scan_period;			/* slow scan period */
+	u32	fast_scan_iterations;			/* Fast scan iterations */
+	u8	ssid_length[MAX_PNO_LIST_COUNT];	/* SSID Length Array */
+	u8	ssid_cipher_info[MAX_PNO_LIST_COUNT];	/* Cipher information for security */
+	u8	ssid_channel_info[MAX_PNO_LIST_COUNT];	/* channel information */
+	u8	loc_probe_req[MAX_HIDDEN_AP];		/* loc_probeReq */
+} pno_nlo_info_t;
+
+typedef struct pno_ssid {
+	u32		SSID_len;
+	u8		SSID[32];
+} pno_ssid_t;
+
+typedef struct pno_ssid_list {
+	pno_ssid_t	node[MAX_PNO_LIST_COUNT];
+} pno_ssid_list_t;
+
+typedef struct pno_scan_channel_info {
+	u8	channel;
+	u8	tx_power;
+	u8	timeout;
+	u8	active;				/* set 1 means active scan, or pasivite scan. */
+} pno_scan_channel_info_t;
+
+typedef struct pno_scan_info {
+	u8	enableRFE;			/* Enable RFE */
+	u8	period_scan_time;		/* exclusive with fast_scan_period and slow_scan_period */
+	u8	periodScan;			/* exclusive with fast_scan_period and slow_scan_period */
+	u8	orig_80_offset;			/* original channel 80 offset */
+	u8	orig_40_offset;			/* original channel 40 offset */
+	u8	orig_bw;			/* original bandwidth */
+	u8	orig_ch;			/* original channel */
+	u8	channel_num;			/* number of channel */
+	u64	rfe_type;			/* rfe_type && 0x00000000000000ff */
+	pno_scan_channel_info_t ssid_channel_info[MAX_SCAN_LIST_COUNT];
+} pno_scan_info_t;
+#endif /* CONFIG_PNO_SUPPORT */
+
+#ifdef CONFIG_LPS_POFF
+/* Driver context for LPS 32K Close IO Power */
+typedef struct lps_poff_info {
+	bool	bEn;
+	u8	*pStaticFile;
+	u8	*pDynamicFile;
+	u32	ConfFileOffset;
+	u32	tx_bndy_static;
+	u32	tx_bndy_dynamic;
+	u16	ConfLenForPTK;
+	u16	ConfLenForGTK;
+	ATOMIC_T bEnterPOFF;
+	ATOMIC_T bTxBoundInProgress;
+	ATOMIC_T bSetPOFFParm;
+} lps_poff_info_t;
+#endif /*CONFIG_LPS_POFF*/
+
+struct aoac_report {
+	u8 iv[8];
+	u8 replay_counter_eapol_key[8];
+	u8 group_key[32];
+	u8 key_index;
+	u8 security_type;
+	u8 wow_pattern_idx;
+	u8 version_info;
+	u8 rekey_ok:1;
+	u8 dummy:7;
+	u8 reserved[3];
+	u8 rxptk_iv[8];
+	u8 rxgtk_iv[4][8];
+};
+
+struct pwrctrl_priv {
+	_pwrlock	lock;
+	_pwrlock	check_32k_lock;
+	volatile u8 rpwm; /* requested power state for fw */
+	volatile u8 cpwm; /* fw current power state. updated when 1. read from HCPWM 2. driver lowers power level */
+	volatile u8 tog; /* toggling */
+	volatile u8 cpwm_tog; /* toggling */
+	u8 rpwm_retry;
+
+	u8	pwr_mode;
+	u8	smart_ps;
+	u8	bcn_ant_mode;
+	u8	dtim;
+#ifdef CONFIG_LPS_CHK_BY_TP
+	u8	lps_chk_by_tp;
+	u16	lps_tx_tp_th;/*Mbps*/
+	u16	lps_rx_tp_th;/*Mbps*/
+	u16	lps_bi_tp_th;/*Mbps*//*TRX TP*/
+	int	lps_chk_cnt_th;
+	int	lps_chk_cnt;
+	u32	lps_tx_pkts;
+	u32	lps_rx_pkts;
+
+#endif
+
+#ifdef CONFIG_WMMPS_STA
+	u8 wmm_smart_ps;
+#endif /* CONFIG_WMMPS_STA */	
+
+	u32	alives;
+	_workitem cpwm_event;
+	_workitem dma_event; /*for handle un-synchronized tx dma*/
+#ifdef CONFIG_LPS_RPWM_TIMER
+	u8 brpwmtimeout;
+	_workitem rpwmtimeoutwi;
+	_timer pwr_rpwm_timer;
+#endif /* CONFIG_LPS_RPWM_TIMER */
+	u8	bpower_saving; /* for LPS/IPS */
+
+	u8	b_hw_radio_off;
+	u8	reg_rfoff;
+	u8	reg_pdnmode; /* powerdown mode */
+	u32	rfoff_reason;
+
+	/* RF OFF Level */
+	u32	cur_ps_level;
+	u32	reg_rfps_level;
+
+	uint	ips_enter_cnts;
+	uint	ips_leave_cnts;
+	uint	lps_enter_cnts;
+	uint	lps_leave_cnts;
+
+	u8	ips_mode;
+	u8	ips_org_mode;
+	u8	ips_mode_req; /* used to accept the mode setting request, will update to ipsmode later */
+	uint bips_processing;
+	systime ips_deny_time; /* will deny IPS when system time is smaller than this */
+	u8 pre_ips_type;/* 0: default flow, 1: carddisbale flow */
+
+	/* ps_deny: if 0, power save is free to go; otherwise deny all kinds of power save. */
+	/* Use PS_DENY_REASON to decide reason. */
+	/* Don't access this variable directly without control function, */
+	/* and this variable should be protected by lock. */
+	u32 ps_deny;
+
+	u8 ps_processing; /* temporarily used to mark whether in rtw_ps_processor */
+
+	u8 fw_psmode_iface_id;
+	u8	bLeisurePs;
+	u8	LpsIdleCount;
+	u8	power_mgnt;
+	u8	org_power_mgnt;
+	u8	bFwCurrentInPSMode;
+	systime	DelayLPSLastTimeStamp;
+	s32		pnp_current_pwr_state;
+	u8		pnp_bstop_trx;
+
+	#ifdef CONFIG_AUTOSUSPEND
+	int		ps_flag; /* used by autosuspend */
+	u8		bInternalAutoSuspend;
+	#endif
+	u8		bInSuspend;
+#ifdef CONFIG_BT_COEXIST
+	u8		bAutoResume;
+	u8		autopm_cnt;
+#endif
+	u8		bSupportRemoteWakeup;
+	u8		wowlan_wake_reason;
+	u8		wowlan_last_wake_reason;
+	u8		wowlan_ap_mode;
+	u8		wowlan_mode;
+	u8		wowlan_p2p_mode;
+	u8		wowlan_pno_enable;
+	u8		wowlan_in_resume;
+
+#ifdef CONFIG_GPIO_WAKEUP
+	u8		is_high_active;
+#endif /* CONFIG_GPIO_WAKEUP */
+	u8		hst2dev_high_active;
+#ifdef CONFIG_WOWLAN
+	bool		default_patterns_en;
+#ifdef CONFIG_IPV6
+	u8		wowlan_ns_offload_en;
+#endif /*CONFIG_IPV6*/
+	u8		wowlan_txpause_status;
+	u8		wowlan_pattern_idx;
+	u64		wowlan_fw_iv;
+	struct rtl_priv_pattern	patterns[MAX_WKFM_CAM_NUM];
+#ifdef CONFIG_PNO_SUPPORT
+	u8		pno_inited;
+	pno_nlo_info_t	*pnlo_info;
+	pno_scan_info_t	*pscan_info;
+	pno_ssid_list_t	*pno_ssid_list;
+#endif /* CONFIG_PNO_SUPPORT */
+#ifdef CONFIG_WOW_PATTERN_HW_CAM
+	_mutex	wowlan_pattern_cam_mutex;
+#endif
+	u8		wowlan_aoac_rpt_loc;
+	struct aoac_report wowlan_aoac_rpt;
+	u8		wowlan_dis_lps;/*for debug purpose*/
+#endif /* CONFIG_WOWLAN */
+	_timer	pwr_state_check_timer;
+	int		pwr_state_check_interval;
+	u8		pwr_state_check_cnts;
+
+
+	rt_rf_power_state	rf_pwrstate;/* cur power state, only for IPS */
+	/* rt_rf_power_state	current_rfpwrstate; */
+	rt_rf_power_state	change_rfpwrstate;
+
+	u8		bHWPowerdown; /* power down mode selection. 0:radio off, 1:power down */
+	u8		bHWPwrPindetect; /* come from registrypriv.hwpwrp_detect. enable power down function. 0:disable, 1:enable */
+	u8		bkeepfwalive;
+	u8		brfoffbyhw;
+	unsigned long PS_BBRegBackup[PSBBREG_TOTALCNT];
+
+#ifdef CONFIG_RESUME_IN_WORKQUEUE
+	struct workqueue_struct *rtw_workqueue;
+	_workitem resume_work;
+#endif
+
+#ifdef CONFIG_HAS_EARLYSUSPEND
+	struct early_suspend early_suspend;
+	u8 do_late_resume;
+#endif /* CONFIG_HAS_EARLYSUSPEND */
+
+#ifdef CONFIG_ANDROID_POWER
+	android_early_suspend_t early_suspend;
+	u8 do_late_resume;
+#endif
+
+#ifdef CONFIG_INTEL_PROXIM
+	u8	stored_power_mgnt;
+#endif
+
+#ifdef CONFIG_LPS_POFF
+	lps_poff_info_t	*plps_poff_info;
+#endif
+	u8 lps_level_bk;
+	u8 lps_level; /*LPS_NORMAL,LPA_CG,LPS_PG*/
+#ifdef CONFIG_LPS_PG
+	u8 lpspg_rsvd_page_locate;
+	u8 blpspg_info_up;
+#endif
+	u8 current_lps_hw_port_id;
+
+#ifdef CONFIG_RTW_CFGVEDNOR_LLSTATS
+	systime radio_on_start_time;
+	systime pwr_saving_start_time;
+	u32 pwr_saving_time;
+	u32 on_time;
+	u32 tx_time;
+	u32 rx_time;
+#endif /* CONFIG_RTW_CFGVEDNOR_LLSTATS */
+
+};
+
+#define rtw_get_ips_mode_req(pwrctl) \
+	(pwrctl)->ips_mode_req
+
+#define rtw_ips_mode_req(pwrctl, ips_mode) \
+	(pwrctl)->ips_mode_req = (ips_mode)
+
+#define RTW_PWR_STATE_CHK_INTERVAL 2000
+
+#define _rtw_set_pwr_state_check_timer(pwrctl, ms) \
+	do { \
+		/*RTW_INFO("%s _rtw_set_pwr_state_check_timer(%p, %d)\n", __FUNCTION__, (pwrctl), (ms));*/ \
+		_set_timer(&(pwrctl)->pwr_state_check_timer, (ms)); \
+	} while (0)
+
+#define rtw_set_pwr_state_check_timer(pwrctl) \
+	_rtw_set_pwr_state_check_timer((pwrctl), (pwrctl)->pwr_state_check_interval)
+
+extern void rtw_init_pwrctrl_priv(_adapter *adapter);
+extern void rtw_free_pwrctrl_priv(_adapter *adapter);
+
+#ifdef CONFIG_LPS_LCLK
+s32 rtw_register_task_alive(PADAPTER, u32 task);
+void rtw_unregister_task_alive(PADAPTER, u32 task);
+extern s32 rtw_register_tx_alive(PADAPTER padapter);
+extern void rtw_unregister_tx_alive(PADAPTER padapter);
+extern s32 rtw_register_rx_alive(PADAPTER padapter);
+extern void rtw_unregister_rx_alive(PADAPTER padapter);
+extern s32 rtw_register_cmd_alive(PADAPTER padapter);
+extern void rtw_unregister_cmd_alive(PADAPTER padapter);
+extern s32 rtw_register_evt_alive(PADAPTER padapter);
+extern void rtw_unregister_evt_alive(PADAPTER padapter);
+extern void cpwm_int_hdl(PADAPTER padapter, struct reportpwrstate_parm *preportpwrstate);
+extern void LPS_Leave_check(PADAPTER padapter);
+#endif
+
+extern void LeaveAllPowerSaveMode(PADAPTER Adapter);
+extern void LeaveAllPowerSaveModeDirect(PADAPTER Adapter);
+#ifdef CONFIG_IPS
+void _ips_enter(_adapter *padapter);
+void ips_enter(_adapter *padapter);
+int _ips_leave(_adapter *padapter);
+int ips_leave(_adapter *padapter);
+#endif
+
+void rtw_ps_processor(_adapter *padapter);
+
+#ifdef CONFIG_AUTOSUSPEND
+int autoresume_enter(_adapter *padapter);
+#endif
+#ifdef SUPPORT_HW_RFOFF_DETECTED
+rt_rf_power_state RfOnOffDetect(IN	PADAPTER pAdapter);
+#endif
+
+
+#ifdef DBG_CHECK_FW_PS_STATE
+int rtw_fw_ps_state(PADAPTER padapter);
+#endif
+
+#ifdef CONFIG_LPS
+s32 LPS_RF_ON_check(PADAPTER padapter, u32 delay_ms);
+void LPS_Enter(PADAPTER padapter, const char *msg);
+void LPS_Leave(PADAPTER padapter, const char *msg);
+#ifdef CONFIG_CHECK_LEAVE_LPS
+#ifdef CONFIG_LPS_CHK_BY_TP
+void traffic_check_for_leave_lps_by_tp(PADAPTER padapter, u8 tx, struct sta_info *sta);
+#endif
+void traffic_check_for_leave_lps(PADAPTER padapter, u8 tx, u32 tx_packets);
+#endif /*CONFIG_CHECK_LEAVE_LPS*/
+void rtw_set_ps_mode(PADAPTER padapter, u8 ps_mode, u8 smart_ps, u8 bcn_ant_mode, const char *msg);
+void rtw_set_fw_in_ips_mode(PADAPTER padapter, u8 enable);
+u8 rtw_set_rpwm(_adapter *padapter, u8 val8);
+void rtw_wow_lps_level_decide(_adapter *adapter, u8 wow_en);
+#endif
+
+#ifdef CONFIG_RESUME_IN_WORKQUEUE
+void rtw_resume_in_workqueue(struct pwrctrl_priv *pwrpriv);
+#endif /* CONFIG_RESUME_IN_WORKQUEUE */
+
+#if defined(CONFIG_HAS_EARLYSUSPEND) || defined(CONFIG_ANDROID_POWER)
+bool rtw_is_earlysuspend_registered(struct pwrctrl_priv *pwrpriv);
+bool rtw_is_do_late_resume(struct pwrctrl_priv *pwrpriv);
+void rtw_set_do_late_resume(struct pwrctrl_priv *pwrpriv, bool enable);
+void rtw_register_early_suspend(struct pwrctrl_priv *pwrpriv);
+void rtw_unregister_early_suspend(struct pwrctrl_priv *pwrpriv);
+#else
+#define rtw_is_earlysuspend_registered(pwrpriv) _FALSE
+#define rtw_is_do_late_resume(pwrpriv) _FALSE
+#define rtw_set_do_late_resume(pwrpriv, enable) do {} while (0)
+#define rtw_register_early_suspend(pwrpriv) do {} while (0)
+#define rtw_unregister_early_suspend(pwrpriv) do {} while (0)
+#endif /* CONFIG_HAS_EARLYSUSPEND || CONFIG_ANDROID_POWER */
+
+u8 rtw_interface_ps_func(_adapter *padapter, HAL_INTF_PS_FUNC efunc_id, u8 *val);
+void rtw_set_ips_deny(_adapter *padapter, u32 ms);
+int _rtw_pwr_wakeup(_adapter *padapter, u32 ips_deffer_ms, const char *caller);
+#define rtw_pwr_wakeup(adapter) _rtw_pwr_wakeup(adapter, RTW_PWR_STATE_CHK_INTERVAL, __FUNCTION__)
+#define rtw_pwr_wakeup_ex(adapter, ips_deffer_ms) _rtw_pwr_wakeup(adapter, ips_deffer_ms, __FUNCTION__)
+int rtw_pm_set_ips(_adapter *padapter, u8 mode);
+int rtw_pm_set_lps(_adapter *padapter, u8 mode);
+int rtw_pm_set_lps_level(_adapter *padapter, u8 level);
+
+void rtw_ps_deny(PADAPTER padapter, PS_DENY_REASON reason);
+void rtw_ps_deny_cancel(PADAPTER padapter, PS_DENY_REASON reason);
+u32 rtw_ps_deny_get(PADAPTER padapter);
+
+#if defined(CONFIG_WOWLAN)
+void rtw_get_current_ip_address(PADAPTER padapter, u8 *pcurrentip);
+void rtw_get_sec_iv(PADAPTER padapter, u8 *pcur_dot11txpn, u8 *StaAddr);
+bool rtw_check_pattern_valid(u8 *input, u8 len);
+bool rtw_wowlan_parser_pattern_cmd(u8 *input, char *pattern,
+				int *pattern_len, char *bit_mask);
+void rtw_wow_pattern_sw_reset(_adapter *adapter);
+u8 rtw_set_default_pattern(_adapter *adapter);
+void rtw_wow_pattern_sw_dump(_adapter *adapter);
+#endif /* CONFIG_WOWLAN */
+#endif /* __RTL871X_PWRCTRL_H_ */
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/include/rtw_qos.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/rtw_qos.h
--- linux-5.6.3/3rdparty/rtl8821ce/include/rtw_qos.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/rtw_qos.h	2020-04-10 16:35:06.852661748 +0300
@@ -0,0 +1,66 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+
+
+#ifndef _RTW_QOS_H_
+#define _RTW_QOS_H_
+
+#define DRV_CFG_UAPSD_VO 	BIT0
+#define DRV_CFG_UAPSD_VI 	BIT1
+#define DRV_CFG_UAPSD_BK 	BIT2
+#define DRV_CFG_UAPSD_BE 	BIT3
+
+#define WMM_IE_UAPSD_VO 	BIT0
+#define WMM_IE_UAPSD_VI 	BIT1
+#define WMM_IE_UAPSD_BK 	BIT2
+#define WMM_IE_UAPSD_BE 	BIT3
+
+#define WMM_TID0 	BIT0
+#define WMM_TID1 	BIT1
+#define WMM_TID2 	BIT2
+#define WMM_TID3 	BIT3
+#define WMM_TID4 	BIT4
+#define WMM_TID5 	BIT5
+#define WMM_TID6 	BIT6
+#define WMM_TID7 	BIT7
+
+#define AP_SUPPORTED_UAPSD BIT7
+/* TC = Traffic Category,  TID0~7 represents TC */
+#define BIT_MASK_TID_TC 0xff
+/* TS = Traffic Stream,  TID8~15 represents TS */
+#define BIT_MASK_TID_TS 0xff00
+#define ALL_TID_TC_SUPPORTED_UAPSD 0xff
+
+struct	qos_priv	{
+
+	unsigned int	  qos_option;	/* bit mask option: u-apsd, s-apsd, ts, block ack...		 */
+
+#ifdef CONFIG_WMMPS_STA
+	/* uapsd (unscheduled automatic power-save delivery) = a kind of wmmps */
+	u8 uapsd_max_sp_len;
+	/* declare uapsd_tid as a bitmap for the uapsd setting of TID 0~15 */
+	u16 uapsd_tid;
+	/* declare uapsd_tid_delivery_enabled as a bitmap for the delivery-enabled setting of TID 0~7 */
+	u8 uapsd_tid_delivery_enabled;
+	/* declare uapsd_tid_trigger_enabled as a bitmap for the trigger-enabled setting of TID 0~7 */
+	u8 uapsd_tid_trigger_enabled;
+	/* declare uapsd_ap_supported to record whether the connected ap  supports uapsd or not */
+	u8 uapsd_ap_supported;
+#endif /* CONFIG_WMMPS_STA */	
+
+};
+
+
+#endif /* _RTL871X_QOS_H_ */
\ Ingen nyrad vid filslut
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/include/rtw_recv.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/rtw_recv.h
--- linux-5.6.3/3rdparty/rtl8821ce/include/rtw_recv.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/rtw_recv.h	2020-04-10 16:35:06.852661748 +0300
@@ -0,0 +1,878 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#ifndef _RTW_RECV_H_
+#define _RTW_RECV_H_
+
+#define RTW_RX_MSDU_ACT_NONE		0
+#define RTW_RX_MSDU_ACT_INDICATE	BIT0
+#define RTW_RX_MSDU_ACT_FORWARD		BIT1
+
+#ifdef PLATFORM_OS_XP
+	#ifdef CONFIG_SDIO_HCI
+		#define NR_RECVBUFF 1024/* 512 */ /* 128 */
+	#else
+		#define NR_RECVBUFF (16)
+	#endif
+#elif defined(PLATFORM_OS_CE)
+	#ifdef CONFIG_SDIO_HCI
+		#define NR_RECVBUFF (128)
+	#else
+		#define NR_RECVBUFF (4)
+	#endif
+#else /* PLATFORM_LINUX /PLATFORM_BSD */
+
+	#ifdef CONFIG_SINGLE_RECV_BUF
+		#define NR_RECVBUFF (1)
+	#else
+		#if defined(CONFIG_GSPI_HCI)
+			#define NR_RECVBUFF (32)
+		#elif defined(CONFIG_SDIO_HCI)
+			#define NR_RECVBUFF (8)
+		#else
+			#define NR_RECVBUFF (8)
+		#endif
+	#endif /* CONFIG_SINGLE_RECV_BUF */
+	#ifdef CONFIG_PREALLOC_RX_SKB_BUFFER
+		#define NR_PREALLOC_RECV_SKB (rtw_rtkm_get_nr_recv_skb()>>1)
+	#else /*!CONFIG_PREALLOC_RX_SKB_BUFFER */
+		#define NR_PREALLOC_RECV_SKB 8
+	#endif /* CONFIG_PREALLOC_RX_SKB_BUFFER */
+
+	#ifdef CONFIG_RTW_NAPI
+		#define RTL_NAPI_WEIGHT (32)
+	#endif
+#endif
+
+#if defined(CONFIG_RTL8821C) && defined(CONFIG_SDIO_HCI) && defined(CONFIG_RECV_THREAD_MODE)
+	#ifdef NR_RECVBUFF
+	#undef NR_RECVBUFF
+	#define NR_RECVBUFF (32)
+	#endif
+#endif
+
+#define NR_RECVFRAME 256
+
+#define RXFRAME_ALIGN	8
+#define RXFRAME_ALIGN_SZ	(1<<RXFRAME_ALIGN)
+
+#define DRVINFO_SZ	4 /* unit is 8bytes */
+
+#define MAX_RXFRAME_CNT	512
+#define MAX_RX_NUMBLKS		(32)
+#define RECVFRAME_HDR_ALIGN 128
+#define MAX_CONTINUAL_NORXPACKET_COUNT 4    /*  In MAX_CONTINUAL_NORXPACKET_COUNT*2 sec  , no rx traffict would issue DELBA*/
+
+#define PHY_RSSI_SLID_WIN_MAX				100
+#define PHY_LINKQUALITY_SLID_WIN_MAX		20
+
+
+#define SNAP_SIZE sizeof(struct ieee80211_snap_hdr)
+
+#define RX_MPDU_QUEUE				0
+#define RX_CMD_QUEUE				1
+#define RX_MAX_QUEUE				2
+
+#define MAX_SUBFRAME_COUNT	64
+/* Bridge-Tunnel header (for EtherTypes ETH_P_AARP and ETH_P_IPX) */
+extern u8 rtw_bridge_tunnel_header[];
+extern u8 rtw_rfc1042_header[];
+
+/* for Rx reordering buffer control */
+struct recv_reorder_ctrl {
+	_adapter	*padapter;
+	u8 tid;
+	u8 enable;
+	u16 indicate_seq;/* =wstart_b, init_value=0xffff */
+	u16 wend_b;
+	u8 wsize_b;
+	u8 ampdu_size;
+	_queue pending_recvframe_queue;
+	_timer reordering_ctrl_timer;
+	u8 bReorderWaiting;
+};
+
+struct	stainfo_rxcache	{
+	u16	tid_rxseq[16];
+	u8 iv[16][8];
+	u8 last_tid;
+#if 0
+	unsigned short	tid0_rxseq;
+	unsigned short	tid1_rxseq;
+	unsigned short	tid2_rxseq;
+	unsigned short	tid3_rxseq;
+	unsigned short	tid4_rxseq;
+	unsigned short	tid5_rxseq;
+	unsigned short	tid6_rxseq;
+	unsigned short	tid7_rxseq;
+	unsigned short	tid8_rxseq;
+	unsigned short	tid9_rxseq;
+	unsigned short	tid10_rxseq;
+	unsigned short	tid11_rxseq;
+	unsigned short	tid12_rxseq;
+	unsigned short	tid13_rxseq;
+	unsigned short	tid14_rxseq;
+	unsigned short	tid15_rxseq;
+#endif
+};
+
+
+struct smooth_rssi_data {
+	u32	elements[100];	/* array to store values */
+	u32	index;			/* index to current array to store */
+	u32	total_num;		/* num of valid elements */
+	u32	total_val;		/* sum of valid elements */
+};
+
+struct signal_stat {
+	u8	update_req;		/* used to indicate */
+	u8	avg_val;		/* avg of valid elements */
+	u32	total_num;		/* num of valid elements */
+	u32	total_val;		/* sum of valid elements	 */
+};
+
+struct rx_raw_rssi {
+	u8 data_rate;
+	u8 pwdball;
+	s8 pwr_all;
+
+	u8 mimo_signal_strength[4];/* in 0~100 index */
+	u8 mimo_signal_quality[4];
+
+	s8 ofdm_pwr[4];
+	u8 ofdm_snr[4];
+};
+
+
+#include "cmn_info/rtw_sta_info.h"
+
+struct rx_pkt_attrib	{
+	u16	pkt_len;
+	u8	physt;
+	u8	drvinfo_sz;
+	u8	shift_sz;
+	u8	hdrlen; /* the WLAN Header Len */
+	u8	to_fr_ds;
+	u8	amsdu;
+	u8	qos;
+	u8	priority;
+	u8	pw_save;
+	u8	mdata;
+	u16	seq_num;
+	u8	frag_num;
+	u8	mfrag;
+	u8	order;
+	u8	privacy; /* in frame_ctrl field */
+	u8	bdecrypted;
+	u8	encrypt; /* when 0 indicate no encrypt. when non-zero, indicate the encrypt algorith */
+	u8	iv_len;
+	u8	icv_len;
+	u8	crc_err;
+	u8	icv_err;
+
+	u16	eth_type;
+
+	u8	dst[ETH_ALEN];
+	u8	src[ETH_ALEN];
+	u8	ta[ETH_ALEN];
+	u8	ra[ETH_ALEN];
+	u8	bssid[ETH_ALEN];
+#ifdef CONFIG_RTW_MESH
+	u8	msa[ETH_ALEN]; /* mesh sa */
+	u8	mda[ETH_ALEN]; /* mesh da */
+	u8 mesh_ctrl_present;
+	u8	mesh_ctrl_len; /* length of mesh control field */
+#endif
+
+	u8	ack_policy;
+
+	u8	key_index;
+
+	u8	data_rate;
+	u8 ch; /* RX channel */
+	u8	bw;
+	u8	stbc;
+	u8	ldpc;
+	u8	sgi;
+	u8	pkt_rpt_type;
+	u32 tsfl;
+	u32	MacIDValidEntry[2];	/* 64 bits present 64 entry. */
+	u8	ppdu_cnt;
+	u32 	free_cnt;		/* free run counter */
+	struct phydm_phyinfo_struct phy_info;
+};
+
+#ifdef CONFIG_RTW_MESH
+#define RATTRIB_GET_MCTRL_LEN(rattrib) ((rattrib)->mesh_ctrl_len)
+#else
+#define RATTRIB_GET_MCTRL_LEN(rattrib) 0
+#endif
+
+/* These definition is used for Rx packet reordering. */
+#define SN_LESS(a, b)		(((a-b) & 0x800) != 0)
+#define SN_EQUAL(a, b)	(a == b)
+/* #define REORDER_WIN_SIZE	128 */
+/* #define REORDER_ENTRY_NUM	128 */
+#define REORDER_WAIT_TIME	(50) /* (ms) */
+
+#if defined(CONFIG_PLATFORM_RTK390X) && defined(CONFIG_USB_HCI)
+	#define RECVBUFF_ALIGN_SZ 32
+#else
+	#define RECVBUFF_ALIGN_SZ 8
+#endif
+
+#ifdef CONFIG_TRX_BD_ARCH
+	#define RX_WIFI_INFO_SIZE	24
+#elif (defined(CONFIG_RTL8192E) || defined(CONFIG_RTL8814A) || defined(CONFIG_RTL8822B)) && defined(CONFIG_PCI_HCI)
+	#define RXBD_SIZE	sizeof(struct recv_stat)
+#endif
+
+#define RXDESC_SIZE	24
+#define RXDESC_OFFSET RXDESC_SIZE
+
+#ifdef CONFIG_TRX_BD_ARCH
+struct rx_buf_desc {
+	/* RX has exactly one segment */
+#ifdef CONFIG_64BIT_DMA
+	unsigned int dword[4];
+#else
+	unsigned int dword[2];
+#endif
+};
+
+struct recv_stat {
+	unsigned int rxdw[8];
+};
+#else
+struct recv_stat {
+	unsigned int rxdw0;
+
+	unsigned int rxdw1;
+
+#if !((defined(CONFIG_RTL8192E) || defined(CONFIG_RTL8814A) || defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C)) && defined(CONFIG_PCI_HCI))  /* exclude 8192ee, 8814ae, 8822be, 8821ce */
+	unsigned int rxdw2;
+
+	unsigned int rxdw3;
+#endif
+
+#ifndef BUF_DESC_ARCH
+	unsigned int rxdw4;
+
+	unsigned int rxdw5;
+
+#ifdef CONFIG_PCI_HCI
+	unsigned int rxdw6;
+
+	unsigned int rxdw7;
+#endif
+#endif /* if BUF_DESC_ARCH is defined, rx_buf_desc occupy 4 double words */
+};
+#endif
+
+#define EOR BIT(30)
+
+#ifdef CONFIG_PCI_HCI
+#define PCI_MAX_RX_QUEUE		1/* MSDU packet queue, Rx Command Queue */
+#define PCI_MAX_RX_COUNT		128
+#ifdef CONFIG_TRX_BD_ARCH
+#define RX_BD_NUM				PCI_MAX_RX_COUNT	/* alias */
+#endif
+
+struct rtw_rx_ring {
+#ifdef CONFIG_TRX_BD_ARCH
+	struct rx_buf_desc	*buf_desc;
+#else
+	struct recv_stat	*desc;
+#endif
+	dma_addr_t		dma;
+	unsigned int		idx;
+	struct sk_buff	*rx_buf[PCI_MAX_RX_COUNT];
+};
+#endif
+
+
+
+/*
+accesser of recv_priv: rtw_recv_entry(dispatch / passive level); recv_thread(passive) ; returnpkt(dispatch)
+; halt(passive) ;
+
+using enter_critical section to protect
+*/
+
+#ifndef DBG_RX_BH_TRACKING
+#define DBG_RX_BH_TRACKING 0
+#endif
+
+struct recv_priv {
+	_lock	lock;
+
+#ifdef CONFIG_RECV_THREAD_MODE
+	_sema	recv_sema;
+
+#endif
+
+	/* _queue	blk_strms[MAX_RX_NUMBLKS];    */ /* keeping the block ack frame until return ack */
+	_queue	free_recv_queue;
+	_queue	recv_pending_queue;
+	_queue	uc_swdec_pending_queue;
+
+
+	u8 *pallocated_frame_buf;
+	u8 *precv_frame_buf;
+
+	uint free_recvframe_cnt;
+
+	#if DBG_RX_BH_TRACKING
+	u32 rx_bh_stage;
+	u32 rx_bh_buf_dq_cnt;
+	void *rx_bh_lbuf;
+	void *rx_bh_cbuf;
+	void *rx_bh_cbuf_data;
+	u32 rx_bh_cbuf_dlen;
+	u32 rx_bh_cbuf_pos;
+	void *rx_bh_cframe;
+	#endif
+
+	_adapter	*adapter;
+
+#ifdef PLATFORM_WINDOWS
+	_nic_hdl  RxPktPoolHdl;
+	_nic_hdl  RxBufPoolHdl;
+
+#ifdef PLATFORM_OS_XP
+	PMDL	pbytecnt_mdl;
+#endif
+	uint	counter; /* record the number that up-layer will return to drv; only when counter==0 can we  release recv_priv */
+	NDIS_EVENT	recv_resource_evt ;
+#endif
+
+
+	u32 is_any_non_be_pkts;
+
+	u64	rx_bytes;
+	u64	rx_pkts;
+	u64	rx_drop;
+
+	u64 dbg_rx_drop_count;
+	u64 dbg_rx_ampdu_drop_count;
+	u64 dbg_rx_ampdu_forced_indicate_count;
+	u64 dbg_rx_ampdu_loss_count;
+	u64 dbg_rx_dup_mgt_frame_drop_count;
+	u64 dbg_rx_ampdu_window_shift_cnt;
+	u64 dbg_rx_conflic_mac_addr_cnt;
+
+	uint  rx_icv_err;
+	uint  rx_largepacket_crcerr;
+	uint  rx_smallpacket_crcerr;
+	uint  rx_middlepacket_crcerr;
+
+#ifdef CONFIG_USB_HCI
+	/* u8 *pallocated_urb_buf; */
+	_sema allrxreturnevt;
+	uint	ff_hwaddr;
+	ATOMIC_T	rx_pending_cnt;
+
+#ifdef CONFIG_USB_INTERRUPT_IN_PIPE
+#ifdef PLATFORM_LINUX
+	PURB	int_in_urb;
+#endif
+
+	u8	*int_in_buf;
+#endif /* CONFIG_USB_INTERRUPT_IN_PIPE */
+
+#endif
+#if defined(PLATFORM_LINUX) || defined(PLATFORM_FREEBSD)
+#ifdef PLATFORM_FREEBSD
+	struct task irq_prepare_beacon_tasklet;
+	struct task recv_tasklet;
+#else /* PLATFORM_FREEBSD */
+	struct tasklet_struct irq_prepare_beacon_tasklet;
+	struct tasklet_struct recv_tasklet;
+#endif /* PLATFORM_FREEBSD */
+	struct sk_buff_head free_recv_skb_queue;
+	struct sk_buff_head rx_skb_queue;
+#ifdef CONFIG_RTW_NAPI
+		struct sk_buff_head rx_napi_skb_queue;
+#endif 
+#ifdef CONFIG_RX_INDICATE_QUEUE
+	struct task rx_indicate_tasklet;
+	struct ifqueue rx_indicate_queue;
+#endif /* CONFIG_RX_INDICATE_QUEUE */
+
+#endif /* defined(PLATFORM_LINUX) || defined(PLATFORM_FREEBSD) */
+
+	u8 *pallocated_recv_buf;
+	u8 *precv_buf;    /* 4 alignment */
+	_queue	free_recv_buf_queue;
+	u32	free_recv_buf_queue_cnt;
+
+#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI) || defined(CONFIG_USB_HCI)
+	_queue	recv_buf_pending_queue;
+#endif
+
+#ifdef CONFIG_PCI_HCI
+	/* Rx */
+	struct rtw_rx_ring	rx_ring[PCI_MAX_RX_QUEUE];
+	int rxringcount;	/* size should be PCI_MAX_RX_QUEUE */
+	u16	rxbuffersize;
+#endif
+
+	/* For display the phy informatiom */
+	u8 is_signal_dbg;	/* for debug */
+	u8 signal_strength_dbg;	/* for debug */
+
+	u8 signal_strength;
+	u8 signal_qual;
+	s8 rssi;	/* translate_percentage_to_dbm(ptarget_wlan->network.PhyInfo.SignalStrength); */
+	struct rx_raw_rssi raw_rssi_info;
+	/* s8 rxpwdb;	 */
+	/* int RxSNRdB[2]; */
+	/* s8 RxRssi[2]; */
+	/* int FalseAlmCnt_all; */
+
+
+#ifdef CONFIG_NEW_SIGNAL_STAT_PROCESS
+	_timer signal_stat_timer;
+	u32 signal_stat_sampling_interval;
+	/* u32 signal_stat_converging_constant; */
+	struct signal_stat signal_qual_data;
+	struct signal_stat signal_strength_data;
+#else /* CONFIG_NEW_SIGNAL_STAT_PROCESS */
+	struct smooth_rssi_data signal_qual_data;
+	struct smooth_rssi_data signal_strength_data;
+#endif /* CONFIG_NEW_SIGNAL_STAT_PROCESS */
+	u16 sink_udpport, pre_rtp_rxseq, cur_rtp_rxseq;
+
+	BOOLEAN store_law_data_flag;
+};
+
+#define RX_BH_STG_UNKNOWN		0
+#define RX_BH_STG_HDL_ENTER		1
+#define RX_BH_STG_HDL_EXIT		2
+#define RX_BH_STG_NEW_BUF		3
+#define RX_BH_STG_NEW_FRAME		4
+#define RX_BH_STG_NORMAL_RX		5
+#define RX_BH_STG_NORMAL_RX_END	6
+#define RX_BH_STG_C2H			7
+#define RX_BH_STG_C2H_END		8
+
+#if DBG_RX_BH_TRACKING
+void rx_bh_tk_set_stage(struct recv_priv *recv, u32 s);
+void rx_bh_tk_set_buf(struct recv_priv *recv, void *buf, void *data, u32 dlen);
+void rx_bh_tk_set_buf_pos(struct recv_priv *recv, void *pos);
+void rx_bh_tk_set_frame(struct recv_priv *recv, void *frame);
+void dump_rx_bh_tk(void *sel, struct recv_priv *recv);
+#else
+#define rx_bh_tk_set_stage(recv, s) do {} while (0)
+#define rx_bh_tk_set_buf(recv, buf, data, dlen) do {} while (0)
+#define rx_bh_tk_set_buf_pos(recv, pos) do {} while (0)
+#define rx_bh_tk_set_frame(recv, frame) do {} while (0)
+#define dump_rx_bh_tk(sel, recv) do {} while (0)
+#endif
+
+#ifdef CONFIG_NEW_SIGNAL_STAT_PROCESS
+#define rtw_set_signal_stat_timer(recvpriv) _set_timer(&(recvpriv)->signal_stat_timer, (recvpriv)->signal_stat_sampling_interval)
+#endif /* CONFIG_NEW_SIGNAL_STAT_PROCESS */
+
+struct sta_recv_priv {
+
+	_lock	lock;
+	sint	option;
+
+	/* _queue	blk_strms[MAX_RX_NUMBLKS]; */
+	_queue defrag_q;	 /* keeping the fragment frame until defrag */
+
+	struct	stainfo_rxcache rxcache;
+	u16	bmc_tid_rxseq[16];
+	u16	nonqos_rxseq;
+	u16	nonqos_bmc_rxseq;
+
+	/* uint	sta_rx_bytes; */
+	/* uint	sta_rx_pkts; */
+	/* uint	sta_rx_fail; */
+
+};
+
+
+struct recv_buf {
+	_list list;
+
+	_lock recvbuf_lock;
+
+	u32	ref_cnt;
+
+	PADAPTER adapter;
+
+	u8	*pbuf;
+	u8	*pallocated_buf;
+
+	u32	len;
+	u8	*phead;
+	u8	*pdata;
+	u8	*ptail;
+	u8	*pend;
+
+#ifdef CONFIG_USB_HCI
+
+#if defined(PLATFORM_OS_XP) || defined(PLATFORM_LINUX) || defined(PLATFORM_FREEBSD)
+	PURB	purb;
+	dma_addr_t dma_transfer_addr;	/* (in) dma addr for transfer_buffer */
+	u32 alloc_sz;
+#endif
+
+#ifdef PLATFORM_OS_XP
+	PIRP		pirp;
+#endif
+
+#ifdef PLATFORM_OS_CE
+	USB_TRANSFER	usb_transfer_read_port;
+#endif
+
+	u8  irp_pending;
+	int  transfer_len;
+
+#endif
+
+#if defined(PLATFORM_LINUX)
+	_pkt *pskb;
+#elif defined(PLATFORM_FREEBSD) /* skb solution */
+	struct sk_buff *pskb;
+#endif
+};
+
+
+/*
+	head  ----->
+
+		data  ----->
+
+			payload
+
+		tail  ----->
+
+
+	end   ----->
+
+	len = (unsigned int )(tail - data);
+
+*/
+struct recv_frame_hdr {
+	_list	list;
+	_pkt *pkt;
+
+	_adapter  *adapter;
+
+	u8 fragcnt;
+
+	int frame_tag;
+
+	struct rx_pkt_attrib attrib;
+
+	uint  len;
+	u8 *rx_head;
+	u8 *rx_data;
+	u8 *rx_tail;
+	u8 *rx_end;
+
+	void *precvbuf;
+
+
+	/*  */
+	struct sta_info *psta;
+
+	/* for A-MPDU Rx reordering buffer control */
+	struct recv_reorder_ctrl *preorder_ctrl;
+
+#ifdef CONFIG_WAPI_SUPPORT
+	u8 UserPriority;
+	u8 WapiTempPN[16];
+	u8 WapiSrcAddr[6];
+	u8 bWapiCheckPNInDecrypt;
+	u8 bIsWaiPacket;
+#endif
+
+};
+
+
+union recv_frame {
+
+	union {
+		_list list;
+		struct recv_frame_hdr hdr;
+		uint mem[RECVFRAME_HDR_ALIGN >> 2];
+	} u;
+
+	/* uint mem[MAX_RXSZ>>2]; */
+
+};
+
+bool rtw_rframe_del_wfd_ie(union recv_frame *rframe, u8 ies_offset);
+
+typedef enum _RX_PACKET_TYPE {
+	NORMAL_RX,/* Normal rx packet */
+	TX_REPORT1,/* CCX */
+	TX_REPORT2,/* TX RPT */
+	HIS_REPORT,/* USB HISR RPT */
+	C2H_PACKET
+} RX_PACKET_TYPE, *PRX_PACKET_TYPE;
+
+extern union recv_frame *_rtw_alloc_recvframe(_queue *pfree_recv_queue);   /* get a free recv_frame from pfree_recv_queue */
+extern union recv_frame *rtw_alloc_recvframe(_queue *pfree_recv_queue);   /* get a free recv_frame from pfree_recv_queue */
+extern void rtw_init_recvframe(union recv_frame *precvframe , struct recv_priv *precvpriv);
+extern int	 rtw_free_recvframe(union recv_frame *precvframe, _queue *pfree_recv_queue);
+
+#define rtw_dequeue_recvframe(queue) rtw_alloc_recvframe(queue)
+extern int _rtw_enqueue_recvframe(union recv_frame *precvframe, _queue *queue);
+extern int rtw_enqueue_recvframe(union recv_frame *precvframe, _queue *queue);
+
+extern void rtw_free_recvframe_queue(_queue *pframequeue,  _queue *pfree_recv_queue);
+u32 rtw_free_uc_swdec_pending_queue(_adapter *adapter);
+
+sint rtw_enqueue_recvbuf_to_head(struct recv_buf *precvbuf, _queue *queue);
+sint rtw_enqueue_recvbuf(struct recv_buf *precvbuf, _queue *queue);
+struct recv_buf *rtw_dequeue_recvbuf(_queue *queue);
+
+#if defined(CONFIG_80211N_HT) && defined(CONFIG_RECV_REORDERING_CTRL)
+void rtw_reordering_ctrl_timeout_handler(void *pcontext);
+#endif
+
+void rx_query_phy_status(union recv_frame *rframe, u8 *phy_stat);
+int rtw_inc_and_chk_continual_no_rx_packet(struct sta_info *sta, int tid_index);
+void rtw_reset_continual_no_rx_packet(struct sta_info *sta, int tid_index);
+
+#ifdef CONFIG_RECV_THREAD_MODE
+thread_return rtw_recv_thread(thread_context context);
+#endif
+
+__inline static u8 *get_rxmem(union recv_frame *precvframe)
+{
+	/* always return rx_head... */
+	if (precvframe == NULL)
+		return NULL;
+
+	return precvframe->u.hdr.rx_head;
+}
+
+__inline static u8 *get_rx_status(union recv_frame *precvframe)
+{
+
+	return get_rxmem(precvframe);
+
+}
+
+__inline static u8 *get_recvframe_data(union recv_frame *precvframe)
+{
+
+	/* alwasy return rx_data */
+	if (precvframe == NULL)
+		return NULL;
+
+	return precvframe->u.hdr.rx_data;
+
+}
+
+__inline static u8 *recvframe_push(union recv_frame *precvframe, sint sz)
+{
+	/* append data before rx_data */
+
+	/* add data to the start of recv_frame
+	*
+	*      This function extends the used data area of the recv_frame at the buffer
+	*      start. rx_data must be still larger than rx_head, after pushing.
+	*/
+
+	if (precvframe == NULL)
+		return NULL;
+
+
+	precvframe->u.hdr.rx_data -= sz ;
+	if (precvframe->u.hdr.rx_data < precvframe->u.hdr.rx_head) {
+		precvframe->u.hdr.rx_data += sz ;
+		return NULL;
+	}
+
+	precvframe->u.hdr.len += sz;
+
+	return precvframe->u.hdr.rx_data;
+
+}
+
+
+__inline static u8 *recvframe_pull(union recv_frame *precvframe, sint sz)
+{
+	/* rx_data += sz; move rx_data sz bytes  hereafter */
+
+	/* used for extract sz bytes from rx_data, update rx_data and return the updated rx_data to the caller */
+
+
+	if (precvframe == NULL)
+		return NULL;
+
+
+	precvframe->u.hdr.rx_data += sz;
+
+	if (precvframe->u.hdr.rx_data > precvframe->u.hdr.rx_tail) {
+		precvframe->u.hdr.rx_data -= sz;
+		return NULL;
+	}
+
+	precvframe->u.hdr.len -= sz;
+
+	return precvframe->u.hdr.rx_data;
+
+}
+
+__inline static u8 *recvframe_put(union recv_frame *precvframe, sint sz)
+{
+	/* rx_tai += sz; move rx_tail sz bytes  hereafter */
+
+	/* used for append sz bytes from ptr to rx_tail, update rx_tail and return the updated rx_tail to the caller */
+	/* after putting, rx_tail must be still larger than rx_end. */
+	unsigned char *prev_rx_tail;
+
+	/* RTW_INFO("recvframe_put: len=%d\n", sz); */
+
+	if (precvframe == NULL)
+		return NULL;
+
+	prev_rx_tail = precvframe->u.hdr.rx_tail;
+
+	precvframe->u.hdr.rx_tail += sz;
+
+	if (precvframe->u.hdr.rx_tail > precvframe->u.hdr.rx_end) {
+		precvframe->u.hdr.rx_tail -= sz;
+		return NULL;
+	}
+
+	precvframe->u.hdr.len += sz;
+
+	return precvframe->u.hdr.rx_tail;
+
+}
+
+
+
+__inline static u8 *recvframe_pull_tail(union recv_frame *precvframe, sint sz)
+{
+	/* rmv data from rx_tail (by yitsen) */
+
+	/* used for extract sz bytes from rx_end, update rx_end and return the updated rx_end to the caller */
+	/* after pulling, rx_end must be still larger than rx_data. */
+
+	if (precvframe == NULL)
+		return NULL;
+
+	precvframe->u.hdr.rx_tail -= sz;
+
+	if (precvframe->u.hdr.rx_tail < precvframe->u.hdr.rx_data) {
+		precvframe->u.hdr.rx_tail += sz;
+		return NULL;
+	}
+
+	precvframe->u.hdr.len -= sz;
+
+	return precvframe->u.hdr.rx_tail;
+
+}
+
+
+
+__inline static _buffer *get_rxbuf_desc(union recv_frame *precvframe)
+{
+	_buffer *buf_desc;
+
+	if (precvframe == NULL)
+		return NULL;
+#ifdef PLATFORM_WINDOWS
+	NdisQueryPacket(precvframe->u.hdr.pkt, NULL, NULL, &buf_desc, NULL);
+#endif
+
+	return buf_desc;
+}
+
+
+__inline static union recv_frame *rxmem_to_recvframe(u8 *rxmem)
+{
+	/* due to the design of 2048 bytes alignment of recv_frame, we can reference the union recv_frame */
+	/* from any given member of recv_frame. */
+	/* rxmem indicates the any member/address in recv_frame */
+
+	return (union recv_frame *)(((SIZE_PTR)rxmem >> RXFRAME_ALIGN) << RXFRAME_ALIGN);
+
+}
+
+__inline static union recv_frame *pkt_to_recvframe(_pkt *pkt)
+{
+
+	u8 *buf_star;
+	union recv_frame *precv_frame;
+#ifdef PLATFORM_WINDOWS
+	_buffer *buf_desc;
+	uint len;
+
+	NdisQueryPacket(pkt, NULL, NULL, &buf_desc, &len);
+	NdisQueryBufferSafe(buf_desc, &buf_star, &len, HighPagePriority);
+#endif
+	precv_frame = rxmem_to_recvframe((unsigned char *)buf_star);
+
+	return precv_frame;
+}
+
+__inline static u8 *pkt_to_recvmem(_pkt *pkt)
+{
+	/* return the rx_head */
+
+	union recv_frame *precv_frame = pkt_to_recvframe(pkt);
+
+	return	precv_frame->u.hdr.rx_head;
+
+}
+
+__inline static u8 *pkt_to_recvdata(_pkt *pkt)
+{
+	/* return the rx_data */
+
+	union recv_frame *precv_frame = pkt_to_recvframe(pkt);
+
+	return	precv_frame->u.hdr.rx_data;
+
+}
+
+
+__inline static sint get_recvframe_len(union recv_frame *precvframe)
+{
+	return precvframe->u.hdr.len;
+}
+
+
+__inline static s32 translate_percentage_to_dbm(u32 SignalStrengthIndex)
+{
+	s32	SignalPower; /* in dBm. */
+
+	/* Translate to dBm (x=y-100) */
+	SignalPower = SignalStrengthIndex - 100;
+	return SignalPower;
+}
+
+struct sta_info;
+
+extern void _rtw_init_sta_recv_priv(struct sta_recv_priv *psta_recvpriv);
+
+extern void  mgt_dispatcher(_adapter *padapter, union recv_frame *precv_frame);
+
+u8 adapter_allow_bmc_data_rx(_adapter *adapter);
+s32 pre_recv_entry(union recv_frame *precvframe, u8 *pphy_status);
+void count_rx_stats(_adapter *padapter, union recv_frame *prframe, struct sta_info *sta);
+
+#endif
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/include/rtw_rf.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/rtw_rf.h
--- linux-5.6.3/3rdparty/rtl8821ce/include/rtw_rf.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/rtw_rf.h	2020-04-10 16:35:06.852661748 +0300
@@ -0,0 +1,238 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#ifndef	__RTW_RF_H_
+#define __RTW_RF_H_
+
+#define NumRates	(13)
+#define	B_MODE_RATE_NUM	(4)
+#define	G_MODE_RATE_NUM	(8)
+#define	G_MODE_BASIC_RATE_NUM	(3)
+/* slot time for 11g */
+#define SHORT_SLOT_TIME					9
+#define NON_SHORT_SLOT_TIME				20
+
+#define CENTER_CH_2G_40M_NUM	9
+#define CENTER_CH_2G_NUM		14
+#define CENTER_CH_5G_20M_NUM	28	/* 20M center channels */
+#define CENTER_CH_5G_40M_NUM	14	/* 40M center channels */
+#define CENTER_CH_5G_80M_NUM	7	/* 80M center channels */
+#define CENTER_CH_5G_160M_NUM	3	/* 160M center channels */
+#define CENTER_CH_5G_ALL_NUM	(CENTER_CH_5G_20M_NUM + CENTER_CH_5G_40M_NUM + CENTER_CH_5G_80M_NUM)
+
+#define	MAX_CHANNEL_NUM_2G	CENTER_CH_2G_NUM
+#define	MAX_CHANNEL_NUM_5G	CENTER_CH_5G_20M_NUM
+#define	MAX_CHANNEL_NUM		(MAX_CHANNEL_NUM_2G + MAX_CHANNEL_NUM_5G)
+
+extern u8 center_ch_2g[CENTER_CH_2G_NUM];
+extern u8 center_ch_2g_40m[CENTER_CH_2G_40M_NUM];
+
+u8 center_chs_2g_num(u8 bw);
+u8 center_chs_2g(u8 bw, u8 id);
+
+extern u8 center_ch_5g_20m[CENTER_CH_5G_20M_NUM];
+extern u8 center_ch_5g_40m[CENTER_CH_5G_40M_NUM];
+extern u8 center_ch_5g_20m_40m[CENTER_CH_5G_20M_NUM + CENTER_CH_5G_40M_NUM];
+extern u8 center_ch_5g_80m[CENTER_CH_5G_80M_NUM];
+extern u8 center_ch_5g_all[CENTER_CH_5G_ALL_NUM];
+
+u8 center_chs_5g_num(u8 bw);
+u8 center_chs_5g(u8 bw, u8 id);
+
+u8 rtw_get_scch_by_cch_offset(u8 cch, u8 bw, u8 offset);
+
+u8 rtw_get_op_chs_by_cch_bw(u8 cch, u8 bw, u8 **op_chs, u8 *op_ch_num);
+
+u8 rtw_get_ch_group(u8 ch, u8 *group, u8 *cck_group);
+
+typedef enum _CAPABILITY {
+	cESS			= 0x0001,
+	cIBSS			= 0x0002,
+	cPollable		= 0x0004,
+	cPollReq			= 0x0008,
+	cPrivacy		= 0x0010,
+	cShortPreamble	= 0x0020,
+	cPBCC			= 0x0040,
+	cChannelAgility	= 0x0080,
+	cSpectrumMgnt	= 0x0100,
+	cQos			= 0x0200,	/* For HCCA, use with CF-Pollable and CF-PollReq */
+	cShortSlotTime	= 0x0400,
+	cAPSD			= 0x0800,
+	cRM				= 0x1000,	/* RRM (Radio Request Measurement) */
+	cDSSS_OFDM	= 0x2000,
+	cDelayedBA		= 0x4000,
+	cImmediateBA	= 0x8000,
+} CAPABILITY, *PCAPABILITY;
+
+enum	_REG_PREAMBLE_MODE {
+	PREAMBLE_LONG	= 1,
+	PREAMBLE_AUTO	= 2,
+	PREAMBLE_SHORT	= 3,
+};
+
+#define rf_path_char(path) (((path) >= RF_PATH_MAX) ? 'X' : 'A' + (path))
+
+/* Bandwidth Offset */
+#define HAL_PRIME_CHNL_OFFSET_DONT_CARE	0
+#define HAL_PRIME_CHNL_OFFSET_LOWER	1
+#define HAL_PRIME_CHNL_OFFSET_UPPER	2
+
+typedef enum _BAND_TYPE {
+	BAND_ON_2_4G = 0,
+	BAND_ON_5G = 1,
+	BAND_ON_BOTH = 2,
+	BAND_MAX = 3,
+} BAND_TYPE, *PBAND_TYPE;
+
+extern const char *const _band_str[];
+#define band_str(band) (((band) >= BAND_MAX) ? _band_str[BAND_MAX] : _band_str[(band)])
+
+extern const u8 _band_to_band_cap[];
+#define band_to_band_cap(band) (((band) >= BAND_MAX) ? _band_to_band_cap[BAND_MAX] : _band_to_band_cap[(band)])
+
+
+extern const char *const _ch_width_str[];
+#define ch_width_str(bw) (((bw) < CHANNEL_WIDTH_MAX) ? _ch_width_str[(bw)] : "CHANNEL_WIDTH_MAX")
+
+extern const u8 _ch_width_to_bw_cap[];
+#define ch_width_to_bw_cap(bw) (((bw) < CHANNEL_WIDTH_MAX) ? _ch_width_to_bw_cap[(bw)] : 0)
+
+/*
+ * Represent Extention Channel Offset in HT Capabilities
+ * This is available only in 40Mhz mode.
+ *   */
+typedef enum _EXTCHNL_OFFSET {
+	EXTCHNL_OFFSET_NO_EXT = 0,
+	EXTCHNL_OFFSET_UPPER = 1,
+	EXTCHNL_OFFSET_NO_DEF = 2,
+	EXTCHNL_OFFSET_LOWER = 3,
+} EXTCHNL_OFFSET, *PEXTCHNL_OFFSET;
+
+typedef enum _VHT_DATA_SC {
+	VHT_DATA_SC_DONOT_CARE = 0,
+	VHT_DATA_SC_20_UPPER_OF_80MHZ = 1,
+	VHT_DATA_SC_20_LOWER_OF_80MHZ = 2,
+	VHT_DATA_SC_20_UPPERST_OF_80MHZ = 3,
+	VHT_DATA_SC_20_LOWEST_OF_80MHZ = 4,
+	VHT_DATA_SC_20_RECV1 = 5,
+	VHT_DATA_SC_20_RECV2 = 6,
+	VHT_DATA_SC_20_RECV3 = 7,
+	VHT_DATA_SC_20_RECV4 = 8,
+	VHT_DATA_SC_40_UPPER_OF_80MHZ = 9,
+	VHT_DATA_SC_40_LOWER_OF_80MHZ = 10,
+} VHT_DATA_SC, *PVHT_DATA_SC_E;
+
+typedef enum _PROTECTION_MODE {
+	PROTECTION_MODE_AUTO = 0,
+	PROTECTION_MODE_FORCE_ENABLE = 1,
+	PROTECTION_MODE_FORCE_DISABLE = 2,
+} PROTECTION_MODE, *PPROTECTION_MODE;
+
+#define RF_TYPE_VALID(rf_type) (rf_type < RF_TYPE_MAX)
+
+extern const u8 _rf_type_to_rf_tx_cnt[];
+#define rf_type_to_rf_tx_cnt(rf_type) (RF_TYPE_VALID(rf_type) ? _rf_type_to_rf_tx_cnt[rf_type] : 0)
+
+extern const u8 _rf_type_to_rf_rx_cnt[];
+#define rf_type_to_rf_rx_cnt(rf_type) (RF_TYPE_VALID(rf_type) ? _rf_type_to_rf_rx_cnt[rf_type] : 0)
+
+int rtw_ch2freq(int chan);
+int rtw_freq2ch(int freq);
+bool rtw_chbw_to_freq_range(u8 ch, u8 bw, u8 offset, u32 *hi, u32 *lo);
+
+struct rf_ctl_t;
+
+typedef enum _REGULATION_TXPWR_LMT {
+	TXPWR_LMT_NONE = 0, /* no limit */
+	TXPWR_LMT_FCC = 1,
+	TXPWR_LMT_MKK = 2,
+	TXPWR_LMT_ETSI = 3,
+	TXPWR_LMT_IC = 4,
+	TXPWR_LMT_KCC = 5,
+	TXPWR_LMT_ACMA = 6,
+	TXPWR_LMT_CHILE = 7,
+	TXPWR_LMT_WW = 8, /* smallest of all available limit, keep last */
+} REGULATION_TXPWR_LMT;
+
+extern const char *const _regd_str[];
+#define regd_str(regd) (((regd) > TXPWR_LMT_WW) ? _regd_str[TXPWR_LMT_WW] : _regd_str[(regd)])
+
+#ifdef CONFIG_TXPWR_LIMIT
+struct regd_exc_ent {
+	_list list;
+	char country[2];
+	u8 domain;
+	char regd_name[0];
+};
+
+void dump_regd_exc_list(void *sel, struct rf_ctl_t *rfctl);
+void rtw_regd_exc_add_with_nlen(struct rf_ctl_t *rfctl, const char *country, u8 domain, const char *regd_name, u32 nlen);
+void rtw_regd_exc_add(struct rf_ctl_t *rfctl, const char *country, u8 domain, const char *regd_name);
+struct regd_exc_ent *_rtw_regd_exc_search(struct rf_ctl_t *rfctl, const char *country, u8 domain);
+struct regd_exc_ent *rtw_regd_exc_search(struct rf_ctl_t *rfctl, const char *country, u8 domain);
+void rtw_regd_exc_list_free(struct rf_ctl_t *rfctl);
+
+void dump_txpwr_lmt(void *sel, _adapter *adapter);
+void rtw_txpwr_lmt_add_with_nlen(struct rf_ctl_t *rfctl, const char *regd_name, u32 nlen
+	, u8 band, u8 bw, u8 tlrs, u8 ntx_idx, u8 ch_idx, s8 lmt);
+void rtw_txpwr_lmt_add(struct rf_ctl_t *rfctl, const char *regd_name
+	, u8 band, u8 bw, u8 tlrs, u8 ntx_idx, u8 ch_idx, s8 lmt);
+struct txpwr_lmt_ent *_rtw_txpwr_lmt_get_by_name(struct rf_ctl_t *rfctl, const char *regd_name);
+struct txpwr_lmt_ent *rtw_txpwr_lmt_get_by_name(struct rf_ctl_t *rfctl, const char *regd_name);
+void rtw_txpwr_lmt_list_free(struct rf_ctl_t *rfctl);
+#endif /* CONFIG_TXPWR_LIMIT */
+
+#define BB_GAIN_2G 0
+#ifdef CONFIG_IEEE80211_BAND_5GHZ
+#define BB_GAIN_5GLB1 1
+#define BB_GAIN_5GLB2 2
+#define BB_GAIN_5GMB1 3
+#define BB_GAIN_5GMB2 4
+#define BB_GAIN_5GHB 5
+#endif
+
+#ifdef CONFIG_IEEE80211_BAND_5GHZ
+#define BB_GAIN_NUM 6
+#else
+#define BB_GAIN_NUM 1
+#endif
+
+int rtw_ch_to_bb_gain_sel(int ch);
+void rtw_rf_set_tx_gain_offset(_adapter *adapter, u8 path, s8 offset);
+void rtw_rf_apply_tx_gain_offset(_adapter *adapter, u8 ch);
+
+/* only check channel ranges */
+#define rtw_is_2g_ch(ch) (ch >= 1 && ch <= 14)
+#define rtw_is_5g_ch(ch) ((ch) >= 36 && (ch) <= 177)
+#define rtw_is_same_band(a, b) \
+	((rtw_is_2g_ch(a) && rtw_is_2g_ch(b)) \
+	|| (rtw_is_5g_ch(a) && rtw_is_5g_ch(b)))
+
+#define rtw_is_5g_band1(ch) ((ch) >= 36 && (ch) <= 48)
+#define rtw_is_5g_band2(ch) ((ch) >= 52 && (ch) <= 64)
+#define rtw_is_5g_band3(ch) ((ch) >= 100 && (ch) <= 144)
+#define rtw_is_5g_band4(ch) ((ch) >= 149 && (ch) <= 177)
+#define rtw_is_same_5g_band(a, b) \
+	((rtw_is_5g_band1(a) && rtw_is_5g_band1(b)) \
+	|| (rtw_is_5g_band2(a) && rtw_is_5g_band2(b)) \
+	|| (rtw_is_5g_band3(a) && rtw_is_5g_band3(b)) \
+	|| (rtw_is_5g_band4(a) && rtw_is_5g_band4(b)))
+
+u8 rtw_is_dfs_range(u32 hi, u32 lo);
+u8 rtw_is_dfs_ch(u8 ch);
+u8 rtw_is_dfs_chbw(u8 ch, u8 bw, u8 offset);
+bool rtw_is_long_cac_range(u32 hi, u32 lo, u8 dfs_region);
+bool rtw_is_long_cac_ch(u8 ch, u8 bw, u8 offset, u8 dfs_region);
+
+#endif /* _RTL8711_RF_H_ */
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/include/rtw_rm_fsm.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/rtw_rm_fsm.h
--- linux-5.6.3/3rdparty/rtl8821ce/include/rtw_rm_fsm.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/rtw_rm_fsm.h	2020-04-10 16:35:06.852661748 +0300
@@ -0,0 +1,389 @@
+
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+
+#ifndef __RTW_RM_FSM_H_
+#define __RTW_RM_FSM_H_
+
+#ifdef CONFIG_RTW_80211K
+
+#define RM_SUPPORT_IWPRIV_DBG	1
+#define RM_MORE_DBG_MSG		0
+
+#define DBG_BCN_REQ_DETAIL	0
+#define DBG_BCN_REQ_WILDCARD	0
+#define DBG_BCN_REQ_SSID	0
+#define DBG_BCN_REQ_SSID_NAME	"RealKungFu"
+
+#define RM_REQ_TIMEOUT		10000	/* 10 seconds */
+#define RM_MEAS_TIMEOUT		10000	/* 10 seconds */
+#define RM_REPT_SCAN_INTVL	5000	/*  5 seconds */
+#define RM_REPT_POLL_INTVL	2000	/*  2 seconds */
+#define RM_COND_INTVL		2000	/*  2 seconds */
+#define RM_SCAN_DENY_TIMES	10
+#define RM_BUSY_TRAFFIC_TIMES	10
+#define RM_WAIT_BUSY_TIMEOUT	1000	/*  1 seconds */
+
+#define MEAS_REQ_MOD_PARALLEL	BIT(0)
+#define MEAS_REQ_MOD_ENABLE	BIT(1)
+#define MEAS_REQ_MOD_REQUEST	BIT(2)
+#define MEAS_REQ_MOD_REPORT	BIT(3)
+#define MEAS_REQ_MOD_DUR_MAND	BIT(4)
+
+#define MEAS_REP_MOD_LATE	BIT(0)
+#define MEAS_REP_MOD_INCAP	BIT(1)
+#define MEAS_REP_MOD_REFUSE	BIT(2)
+
+#define RM_MASTER		BIT(0)	/* STA who issue meas_req */
+#define RM_SLAVE		0	/* STA who do measurement */
+
+#define CLOCK_UNIT		10	/* ms */
+#define RTW_MAX_NB_RPT_IE_NUM	16
+
+#define RM_GET_AID(rmid)	((rmid&0xffff0000)>>16)
+#define RM_IS_ID_FOR_ALL(rmid)	(rmid&RM_ALL_MEAS)
+
+/*
+ * define the following channels as the max channels in each channel plan.
+ * 2G, total 14 chnls
+ * {1,2,3,4,5,6,7,8,9,10,11,12,13,14}
+ * 5G, total 25 chnls
+ * {36,40,44,48,52,56,60,64,100,104,108,112,116,120,124,128,132,136,140,144,149,153,157,161,165}
+ */
+#define	MAX_OP_CHANNEL_SET_NUM	11
+typedef struct _RT_OPERATING_CLASS {
+	int	global_op_class;
+	int	Len;
+	u16	Channel[MAX_OP_CHANNEL_SET_NUM];
+} RT_OPERATING_CLASS, *PRT_OPERATING_CLASS;
+
+/* IEEE 802.11-2012 Table 8-59 Measurement Type definitions
+*  for measurement request
+*  modify rm_meas_type_req_name() when adding new type
+*/
+enum meas_type_of_req {
+	basic_req,	/* spectrum measurement */
+	cca_req,
+	rpi_histo_req,
+	ch_load_req,
+	noise_histo_req,
+	bcn_req,
+	frame_req,
+	sta_statis_req,
+	lci_req,
+	meas_type_req_max,
+};
+
+/* IEEE 802.11-2012 Table 8-81 Measurement Type definitions
+*  for measurement report
+*  modify rm_type_rep_name() when adding new type
+*/
+enum meas_type_of_rep {
+	basic_rep,	/* spectrum measurement */
+	cca_rep,
+	rpi_histo_rep,
+	ch_load_rep,	/* radio measurement */
+	noise_histo_rep,
+	bcn_rep,
+	frame_rep,
+	sta_statis_rep,	/* Radio measurement and WNM */
+	lci_rep,
+	meas_type_rep_max
+};
+
+/*
+* Beacon request
+*/
+/* IEEE 802.11-2012 Table 8-64 Measurement mode for Beacon Request element */
+enum bcn_req_meas_mode {
+	bcn_req_passive,
+	bcn_req_active,
+	bcn_req_bcn_table
+};
+
+/* IEEE 802.11-2012 Table 8-65 optional subelement IDs for Beacon Request */
+enum bcn_req_opt_sub_id{
+	bcn_req_ssid = 0,		/* len 0-32 */
+	bcn_req_rep_info = 1,		/* len 2 */
+	bcn_req_rep_detail = 2,		/* len 1 */
+	bcn_req_req = 10,		/* len 0-237 */
+	bcn_req_ac_ch_rep = 51		/* len 1-237 */
+};
+
+/* IEEE 802.11-2012 Table 8-66 Reporting condition of Beacon Report */
+enum bcn_rep_cound_id{
+	bcn_rep_cond_immediately,	/* default */
+	bcn_req_cond_rcpi_greater,
+	bcn_req_cond_rcpi_less,
+	bcn_req_cond_rsni_greater,
+	bcn_req_cond_rsni_less,
+	bcn_req_cond_max
+};
+
+struct opt_rep_info {
+	u8 cond;
+	u8 threshold;
+};
+
+#define BCN_REQ_OPT_MAX_NUM		16
+struct bcn_req_opt {
+	/* all req cmd id */
+	u8 opt_id[BCN_REQ_OPT_MAX_NUM];
+	u8 opt_id_num;
+	u8 rep_detail;
+	NDIS_802_11_SSID ssid;
+
+	/* bcn report condition */
+	struct opt_rep_info rep_cond;
+
+	/* 0:default(Report to be issued after each measurement) */
+	u8 *req_start;	/*id : 10 request;start  */
+	u8 req_len;	/*id : 10 request;length */
+};
+
+/*
+* channel load
+*/
+/* IEEE 802.11-2012 Table 8-60 optional subelement IDs for channel load request */
+enum ch_load_opt_sub_id{
+	ch_load_rsvd,
+	ch_load_rep_info
+};
+
+/* IEEE 802.11-2012 Table 8-61 Reporting condition for channel load Report */
+enum ch_load_cound_id{
+	ch_load_cond_immediately,	/* default */
+	ch_load_cond_anpi_equal_greater,
+	ch_load_cond_anpi_equal_less,
+	ch_load_cond_max
+};
+
+/*
+* Noise histogram
+*/
+/* IEEE 802.11-2012 Table 8-62 optional subelement IDs for noise histogram */
+enum noise_histo_opt_sub_id{
+	noise_histo_rsvd,
+	noise_histo_rep_info
+};
+
+/* IEEE 802.11-2012 Table 8-63 Reporting condition for noise historgarm Report */
+enum noise_histo_cound_id{
+	noise_histo_cond_immediately,	/* default */
+	noise_histo_cond_anpi_equal_greater,
+	noise_histo_cond_anpi_equal_less,
+	noise_histo_cond_max
+};
+
+struct meas_req_opt {
+	/* report condition */
+	struct opt_rep_info rep_cond;
+};
+
+/*
+* State machine
+*/
+
+enum RM_STATE {
+	RM_ST_IDLE,
+	RM_ST_DO_MEAS,
+	RM_ST_WAIT_MEAS,
+	RM_ST_SEND_REPORT,
+	RM_ST_RECV_REPORT,
+	RM_ST_END,
+	RM_ST_MAX
+};
+
+struct rm_meas_req {
+	u8 category;
+	u8 action_code;		/* T8-206  */
+	u8 diag_token;
+	u16 rpt;
+
+	u8 e_id;
+	u8 len;
+	u8 m_token;
+	u8 m_mode;		/* req:F8-105, rep:F8-141 */
+	u8 m_type;		/* T8-59 */
+	u8 op_class;
+	u8 ch_num;
+	u16 rand_intvl;		/* units of TU */
+	u16 meas_dur;		/* units of TU */
+
+	u8 bssid[6];		/* for bcn_req */
+
+	u8 *pssid;
+	u8 *opt_s_elem_start;
+	int opt_s_elem_len;
+
+	union {
+		struct bcn_req_opt bcn;
+		struct meas_req_opt clm;
+		struct meas_req_opt nhm;
+	}opt;
+
+	struct rtw_ieee80211_channel ch_set[MAX_OP_CHANNEL_SET_NUM];
+	u8 ch_set_ch_amount;
+};
+
+struct rm_meas_rep {
+	u8 category;
+	u8 action_code;		/* T8-206  */
+	u8 diag_token;
+
+	u8 e_id;		/* T8-54, 38 request; 39 report */
+	u8 len;
+	u8 m_token;
+	u8 m_mode;		/* req:F8-105, rep:F8-141 */
+	u8 m_type;		/* T8-59 */
+	u8 op_class;
+	u8 ch_num;
+
+	u8 ch_load;
+	u8 anpi;
+	u8 ipi[11];
+
+	u16 rpt;
+	u8 bssid[6];		/* for bcn_req */
+};
+
+#define MAX_BUF_NUM	128
+struct data_buf {
+	u8 *pbuf;
+	u16 len;
+};
+
+struct rm_obj {
+
+	/* aid << 16 
+		|diag_token << 8
+		|B(1) 1/0:All_AID/UNIC
+		|B(0) 1/0:RM_MASTER/RM_SLAVE */
+	u32 rmid;
+
+	enum RM_STATE state;
+	struct rm_meas_req q;
+	struct rm_meas_rep p;
+	struct sta_info *psta;
+	struct rm_clock *pclock;
+
+	/* meas report */
+	u64 meas_start_time;
+	u64 meas_end_time;
+	int wait_busy;
+	u8 poll_mode;
+
+	struct data_buf buf[MAX_BUF_NUM];
+
+	_list list;
+};
+
+/*
+* Measurement
+*/
+struct opt_subelement {
+	u8 id;
+	u8 length;
+	u8 *data;
+};
+
+/* 802.11-2012 Table 8-206 Radio Measurment Action field */
+enum rm_action_code {
+	RM_ACT_RADIO_MEAS_REQ,
+	RM_ACT_RADIO_MEAS_REP,
+	RM_ACT_LINK_MEAS_REQ,
+	RM_ACT_LINK_MEAS_REP,
+	RM_ACT_NB_REP_REQ,	/* 4 */
+	RM_ACT_NB_REP_RESP,
+	RM_ACT_RESV,
+	RM_ACT_MAX
+};
+
+/* 802.11-2012 Table 8-119 RM Enabled Capabilities definition */
+enum rm_cap_en {
+	RM_LINK_MEAS_CAP_EN,
+	RM_NB_REP_CAP_EN,		/* neighbor report */
+	RM_PARAL_MEAS_CAP_EN,		/* parallel report */
+	RM_REPEAT_MEAS_CAP_EN,
+	RM_BCN_PASSIVE_MEAS_CAP_EN,
+	RM_BCN_ACTIVE_MEAS_CAP_EN,
+	RM_BCN_TABLE_MEAS_CAP_EN,
+	RM_BCN_MEAS_REP_COND_CAP_EN,	/* conditions */
+
+	RM_FRAME_MEAS_CAP_EN,
+	RM_CH_LOAD_CAP_EN,
+	RM_NOISE_HISTO_CAP_EN,		/* noise historgram */
+	RM_STATIS_MEAS_CAP_EN,		/* statistics */
+	RM_LCI_MEAS_CAP_EN,		/* 12 */
+	RM_LCI_AMIMUTH_CAP_EN,
+	RM_TRANS_STREAM_CAT_MEAS_CAP_EN,
+	RM_TRIG_TRANS_STREAM_CAT_MEAS_CAP_EN,
+
+	RM_AP_CH_REP_CAP_EN,
+	RM_RM_MIB_CAP_EN,
+	RM_OP_CH_MAX_MEAS_DUR0,		/* 18-20 */
+	RM_OP_CH_MAX_MEAS_DUR1,
+	RM_OP_CH_MAX_MEAS_DUR2,
+	RM_NONOP_CH_MAX_MEAS_DUR0,	/* 21-23 */
+	RM_NONOP_CH_MAX_MEAS_DUR1,
+	RM_NONOP_CH_MAX_MEAS_DUR2,
+
+	RM_MEAS_PILOT_CAP0,		/* 24-26 */
+	RM_MEAS_PILOT_CAP1,
+	RM_MEAS_PILOT_CAP2,
+	RM_MEAS_PILOT_TRANS_INFO_CAP_EN,
+	RM_NB_REP_TSF_OFFSET_CAP_EN,
+	RM_RCPI_MEAS_CAP_EN,		/* 29 */
+	RM_RSNI_MEAS_CAP_EN,
+	RM_BSS_AVG_ACCESS_DELAY_CAP_EN,
+
+	RM_AVALB_ADMIS_CAPACITY_CAP_EN,
+	RM_ANT_CAP_EN,
+	RM_RSVD,			/* 34-39 */
+	RM_MAX
+};
+
+char *rm_state_name(enum RM_STATE state);
+char *rm_event_name(enum RM_EV_ID evid);
+char *rm_type_req_name(u8 meas_type);
+int _rm_post_event(_adapter *padapter, u32 rmid, enum RM_EV_ID evid);
+int rm_enqueue_rmobj(_adapter *padapter, struct rm_obj *obj, bool to_head);
+
+void rm_free_rmobj(struct rm_obj *prm);
+struct rm_obj *rm_alloc_rmobj(_adapter *padapter);
+struct rm_obj *rm_get_rmobj(_adapter *padapter, u32 rmid);
+struct sta_info *rm_get_psta(_adapter *padapter, u32 rmid);
+
+int retrieve_radio_meas_result(struct rm_obj *prm);
+int rm_radio_meas_report_cond(struct rm_obj *prm);
+int rm_recv_radio_mens_req(_adapter *padapter,
+	union recv_frame *precv_frame,struct sta_info *psta);
+int rm_recv_radio_mens_rep(_adapter *padapter,
+	union recv_frame *precv_frame, struct sta_info *psta);
+int rm_radio_mens_nb_rep(_adapter *padapter,
+	union recv_frame *precv_frame, struct sta_info *psta);
+int issue_null_reply(struct rm_obj *prm);
+int issue_beacon_rep(struct rm_obj *prm);
+int issue_nb_req(struct rm_obj *prm);
+int issue_radio_meas_req(struct rm_obj *prm);
+int issue_radio_meas_rep(struct rm_obj *prm);
+
+void rm_set_rep_mode(struct rm_obj *prm, u8 mode);
+
+int ready_for_scan(struct rm_obj *prm);
+int rm_sitesurvey(struct rm_obj *prm);
+
+#endif /*CONFIG_RTW_80211K*/
+#endif /*__RTW_RM_FSM_H_*/
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/include/rtw_rm.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/rtw_rm.h
--- linux-5.6.3/3rdparty/rtl8821ce/include/rtw_rm.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/rtw_rm.h	2020-04-10 16:35:06.852661748 +0300
@@ -0,0 +1,88 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+
+#ifndef __RTW_RM_H_
+#define __RTW_RM_H_
+
+u8 rm_post_event_hdl(_adapter *padapter, u8 *pbuf);
+
+#define RM_TIMER_NUM 		32
+#define RM_ALL_MEAS		BIT(1)
+#define RM_ID_FOR_ALL(aid)	((aid<<16)|RM_ALL_MEAS)
+
+#define RM_CAP_ARG(x) ((u8 *)(x))[4], ((u8 *)(x))[3], ((u8 *)(x))[2], ((u8 *)(x))[1], ((u8 *)(x))[0]
+#define RM_CAP_FMT "%02x %02x%02x %02x%02x"
+
+/* remember to modify rm_event_name() when adding new event */
+enum RM_EV_ID {
+	RM_EV_state_in,
+	RM_EV_busy_timer_expire,
+	RM_EV_delay_timer_expire,
+	RM_EV_meas_timer_expire,
+	RM_EV_retry_timer_expire,
+	RM_EV_repeat_delay_expire,
+	RM_EV_request_timer_expire,
+	RM_EV_wait_report,
+	RM_EV_start_meas,
+	RM_EV_survey_done,
+	RM_EV_recv_rep,
+	RM_EV_cancel,
+	RM_EV_state_out,
+	RM_EV_max
+};
+
+struct rm_event {
+	u32 rmid;
+	enum RM_EV_ID evid;
+	_list list;
+};
+
+#ifdef CONFIG_RTW_80211K
+
+struct rm_clock {
+	struct rm_obj *prm;
+	ATOMIC_T counter;
+	enum RM_EV_ID evid;
+};
+
+struct rm_priv {
+	u8 enable;
+	_queue ev_queue;
+	_queue rm_queue;
+	_timer rm_timer;
+
+	struct rm_clock clock[RM_TIMER_NUM];
+	u8 rm_en_cap_def[5];
+	u8 rm_en_cap_assoc[5];
+
+	/* rm debug */
+	void *prm_sel;
+};
+
+int rtw_init_rm(_adapter *padapter);
+int rtw_free_rm_priv(_adapter *padapter);
+
+unsigned int rm_on_action(_adapter *padapter, union recv_frame *precv_frame);
+void RM_IE_handler(_adapter *padapter, PNDIS_802_11_VARIABLE_IEs pIE);
+void rtw_ap_parse_sta_rm_en_cap(_adapter *padapter,
+	struct sta_info *psta, struct rtw_ieee802_11_elems *elems);
+
+int rm_post_event(_adapter *padapter, u32 rmid, enum RM_EV_ID evid);
+void rm_handler(_adapter *padapter, struct rm_event *pev);
+
+u8 rm_add_nb_req(_adapter *padapter, struct sta_info *psta);
+
+#endif /*CONFIG_RTW_80211K */
+#endif /* __RTW_RM_H_ */
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/include/rtw_rson.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/rtw_rson.h
--- linux-5.6.3/3rdparty/rtl8821ce/include/rtw_rson.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/rtw_rson.h	2020-04-10 16:35:06.852661748 +0300
@@ -0,0 +1,61 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
+ *
+ *
+ ******************************************************************************/
+#ifndef __RTW_RSON_H_
+#define __RTW_RSON_H_
+
+
+#define RTW_RSON_VER						1
+
+#define RTW_RSON_SCORE_NOTSUP			0x0
+#define RTW_RSON_SCORE_NOTCNNT			0x1
+#define RTW_RSON_SCORE_MAX				0xFF
+#define RTW_RSON_HC_NOTREADY			0xFF
+#define RTW_RSON_HC_ROOT				0x0
+#define RTW_RSON_ALLOWCONNECT			0x1
+#define RTW_RSON_DENYCONNECT			0x0
+
+
+
+/*	for rtw self-origanization spec 1	*/
+struct rtw_rson_struct {
+	u8 ver;
+	u32 id;
+	u8 hopcnt;
+	u8 connectible;
+	u8 loading;
+	u8 res[16];
+} __attribute__((__packed__));
+
+void init_rtw_rson_data(struct dvobj_priv *dvobj);
+void rtw_rson_get_property_str(_adapter *padapter, char *rson_data_str);
+int rtw_rson_set_property(_adapter *padapter, char *field, char *value);
+int rtw_rson_choose(struct wlan_network **candidate, struct wlan_network *competitor);
+int rtw_get_rson_struct(WLAN_BSSID_EX *bssid, struct  rtw_rson_struct *rson_data);
+u8 rtw_cal_rson_score(struct rtw_rson_struct *cand_rson_data, NDIS_802_11_RSSI  Rssi);
+void rtw_rson_handle_ie(WLAN_BSSID_EX *bssid, u8 ie_offset);
+u32 rtw_rson_append_ie(_adapter *padapter, unsigned char *pframe, u32 *len);
+void rtw_rson_do_disconnect(_adapter *padapter);
+void rtw_rson_join_done(_adapter *padapter);
+int rtw_rson_isupdate_roamcan(struct mlme_priv *mlme, struct wlan_network **candidate, struct wlan_network *competitor);
+void rtw_rson_show_survey_info(struct seq_file *m, _list *plist, _list *phead);
+u8 rtw_rson_ap_check_sta(_adapter *padapter, u8 *pframe, uint pkt_len, unsigned short ie_offset);
+u8 rtw_rson_scan_wk_cmd(_adapter *padapter, int op);
+void rtw_rson_scan_cmd_hdl(_adapter *padapter, int op);
+#endif /* __RTW_RSON_H_ */
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/include/rtw_sdio.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/rtw_sdio.h
--- linux-5.6.3/3rdparty/rtl8821ce/include/rtw_sdio.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/rtw_sdio.h	2020-04-10 16:35:06.852661748 +0300
@@ -0,0 +1,26 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2015 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#ifndef _RTW_SDIO_H_
+#define _RTW_SDIO_H_
+
+#include <drv_types.h>		/* struct dvobj_priv and etc. */
+
+u8 rtw_sdio_read_cmd52(struct dvobj_priv *, u32 addr, void *buf, size_t len);
+u8 rtw_sdio_read_cmd53(struct dvobj_priv *, u32 addr, void *buf, size_t len);
+u8 rtw_sdio_write_cmd52(struct dvobj_priv *, u32 addr, void *buf, size_t len);
+u8 rtw_sdio_write_cmd53(struct dvobj_priv *, u32 addr, void *buf, size_t len);
+u8 rtw_sdio_f0_read(struct dvobj_priv *, u32 addr, void *buf, size_t len);
+
+#endif /* _RTW_SDIO_H_ */
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/include/rtw_security.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/rtw_security.h
--- linux-5.6.3/3rdparty/rtl8821ce/include/rtw_security.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/rtw_security.h	2020-04-10 16:35:06.852661748 +0300
@@ -0,0 +1,497 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#ifndef __RTW_SECURITY_H_
+#define __RTW_SECURITY_H_
+
+
+#define _NO_PRIVACY_		0x0
+#define _WEP40_				0x1
+#define _TKIP_				0x2
+#define _TKIP_WTMIC_		0x3
+#define _AES_				0x4
+#define _WEP104_			0x5
+#define _SMS4_				0x06
+#define _WEP_WPA_MIXED_		0x07 /* WEP + WPA */
+#define _BIP_				0x8
+
+/* 802.11W use wrong key */
+#define IEEE80211W_RIGHT_KEY	0x0
+#define IEEE80211W_WRONG_KEY	0x1
+#define IEEE80211W_NO_KEY		0x2
+
+#define CCMPH_2_PN(ch)	((ch) & 0x000000000000ffff) \
+			| (((ch) & 0xffffffff00000000) >> 16)
+
+#define is_wep_enc(alg) (((alg) == _WEP40_) || ((alg) == _WEP104_))
+
+const char *security_type_str(u8 value);
+
+#define _WPA_IE_ID_	0xdd
+#define _WPA2_IE_ID_	0x30
+
+#define SHA256_MAC_LEN 32
+#define AES_BLOCK_SIZE 16
+#define AES_PRIV_SIZE (4 * 44)
+
+#define RTW_KEK_LEN 16
+#define RTW_KCK_LEN 16
+#define RTW_TKIP_MIC_LEN 8
+#define RTW_REPLAY_CTR_LEN 8
+
+#define INVALID_SEC_MAC_CAM_ID	0xFF
+
+typedef enum {
+	ENCRYP_PROTOCOL_OPENSYS,   /* open system */
+	ENCRYP_PROTOCOL_WEP,       /* WEP */
+	ENCRYP_PROTOCOL_WPA,       /* WPA */
+	ENCRYP_PROTOCOL_WPA2,      /* WPA2 */
+	ENCRYP_PROTOCOL_WAPI,      /* WAPI: Not support in this version */
+	ENCRYP_PROTOCOL_MAX
+} ENCRYP_PROTOCOL_E;
+
+
+#ifndef Ndis802_11AuthModeWPA2
+#define Ndis802_11AuthModeWPA2 (Ndis802_11AuthModeWPANone + 1)
+#endif
+
+#ifndef Ndis802_11AuthModeWPA2PSK
+#define Ndis802_11AuthModeWPA2PSK (Ndis802_11AuthModeWPANone + 2)
+#endif
+
+union pn48	{
+
+	u64	val;
+
+#ifdef CONFIG_LITTLE_ENDIAN
+
+struct {
+	u8 TSC0;
+	u8 TSC1;
+	u8 TSC2;
+	u8 TSC3;
+	u8 TSC4;
+	u8 TSC5;
+	u8 TSC6;
+	u8 TSC7;
+} _byte_;
+
+#elif defined(CONFIG_BIG_ENDIAN)
+
+struct {
+	u8 TSC7;
+	u8 TSC6;
+	u8 TSC5;
+	u8 TSC4;
+	u8 TSC3;
+	u8 TSC2;
+	u8 TSC1;
+	u8 TSC0;
+} _byte_;
+
+#endif
+
+};
+
+union Keytype {
+	u8   skey[16];
+	u32    lkey[4];
+};
+
+
+typedef struct _RT_PMKID_LIST {
+	u8						bUsed;
+	u8						Bssid[6];
+	u8						PMKID[16];
+	u8						SsidBuf[33];
+	u8						*ssid_octet;
+	u16						ssid_length;
+} RT_PMKID_LIST, *PRT_PMKID_LIST;
+
+
+struct security_priv {
+	u32	  dot11AuthAlgrthm;		/* 802.11 auth, could be open, shared, 8021x and authswitch */
+	u32	  dot11PrivacyAlgrthm;	/* This specify the privacy for shared auth. algorithm. */
+
+	/* WEP */
+	u32	  dot11PrivacyKeyIndex;	/* this is only valid for legendary wep, 0~3 for key id. (tx key index) */
+	union Keytype dot11DefKey[6];			/* this is only valid for def. key	 */
+	u32	dot11DefKeylen[6];
+	u8	dot11Def_camid[6];
+	u8 	key_mask; /* use to restore wep key after hal_init */
+
+	u32 dot118021XGrpPrivacy;	/* This specify the privacy algthm. used for Grp key */
+	u32	dot118021XGrpKeyid;		/* key id used for Grp Key ( tx key index) */
+	union Keytype	dot118021XGrpKey[6];	/* 802.1x Group Key, for inx0 and inx1	 */
+	union Keytype	dot118021XGrptxmickey[6];
+	union Keytype	dot118021XGrprxmickey[6];
+	union pn48		dot11Grptxpn;			/* PN48 used for Grp Key xmit. */
+	union pn48		dot11Grprxpn;			/* PN48 used for Grp Key recv. */
+	u8				iv_seq[4][8];
+#ifdef CONFIG_IEEE80211W
+	u32	dot11wBIPKeyid;						/* key id used for BIP Key ( tx key index) */
+	union Keytype	dot11wBIPKey[6];		/* BIP Key, for index4 and index5 */
+	union pn48		dot11wBIPtxpn;			/* PN48 used for BIP xmit. */
+	union pn48		dot11wBIPrxpn;			/* PN48 used for BIP recv. */
+#endif /* CONFIG_IEEE80211W */
+#ifdef CONFIG_AP_MODE
+	/* extend security capabilities for AP_MODE */
+	unsigned int dot8021xalg;/* 0:disable, 1:psk, 2:802.1x */
+	unsigned int wpa_psk;/* 0:disable, bit(0): WPA, bit(1):WPA2 */
+	unsigned int wpa_group_cipher;
+	unsigned int wpa2_group_cipher;
+	unsigned int wpa_pairwise_cipher;
+	unsigned int wpa2_pairwise_cipher;
+	u8 mfp_opt;
+#endif
+#ifdef CONFIG_CONCURRENT_MODE
+	u8	dot118021x_bmc_cam_id;
+#endif
+	/*IEEE802.11-2012 Std. Table 8-101 AKM Suite Selectors*/
+	u32	rsn_akm_suite_type;
+
+	u8 wps_ie[MAX_WPS_IE_LEN];/* added in assoc req */
+	int wps_ie_len;
+
+
+	u8	binstallGrpkey;
+#ifdef CONFIG_GTK_OL
+	u8	binstallKCK_KEK;
+#endif /* CONFIG_GTK_OL */
+#ifdef CONFIG_IEEE80211W
+	u8	binstallBIPkey;
+#endif /* CONFIG_IEEE80211W */
+	u8	busetkipkey;
+	u8	bcheck_grpkey;
+	u8	bgrpkey_handshake;
+
+	/* u8	packet_cnt; */ /* unused, removed */
+
+	s32	sw_encrypt;/* from registry_priv */
+	s32	sw_decrypt;/* from registry_priv */
+
+	s32 	hw_decrypted;/* if the rx packets is hw_decrypted==_FALSE, it means the hw has not been ready. */
+
+
+	/* keeps the auth_type & enc_status from upper layer ioctl(wpa_supplicant or wzc) */
+	u32 ndisauthtype;	/* NDIS_802_11_AUTHENTICATION_MODE */
+	u32 ndisencryptstatus;	/* NDIS_802_11_ENCRYPTION_STATUS */
+
+	NDIS_802_11_WEP ndiswep;
+#ifdef PLATFORM_WINDOWS
+	u8 KeyMaterial[16];/* variable length depending on above field. */
+#endif
+
+	u8 assoc_info[600];
+	u8 szofcapability[256]; /* for wpa2 usage */
+	u8 oidassociation[512]; /* for wpa/wpa2 usage */
+	u8 authenticator_ie[256];  /* store ap security information element */
+	u8 supplicant_ie[256];  /* store sta security information element */
+
+
+	/* for tkip countermeasure */
+	systime last_mic_err_time;
+	u8	btkip_countermeasure;
+	u8	btkip_wait_report;
+	systime btkip_countermeasure_time;
+
+	/* --------------------------------------------------------------------------- */
+	/* For WPA2 Pre-Authentication. */
+	/* --------------------------------------------------------------------------- */
+	/* u8				RegEnablePreAuth;				 */ /* Default value: Pre-Authentication enabled or not, from registry "EnablePreAuth". Added by Annie, 2005-11-01. */
+	/* u8				EnablePreAuthentication;			 */ /* Current Value: Pre-Authentication enabled or not. */
+	RT_PMKID_LIST		PMKIDList[NUM_PMKID_CACHE];	/* Renamed from PreAuthKey[NUM_PRE_AUTH_KEY]. Annie, 2006-10-13. */
+	u8				PMKIDIndex;
+	/* u32				PMKIDCount;						 */ /* Added by Annie, 2006-10-13. */
+	/* u8				szCapability[256];				 */ /* For WPA2-PSK using zero-config, by Annie, 2005-09-20. */
+
+	u8 bWepDefaultKeyIdxSet;
+
+#define DBG_SW_SEC_CNT
+#ifdef DBG_SW_SEC_CNT
+	u64 wep_sw_enc_cnt_bc;
+	u64 wep_sw_enc_cnt_mc;
+	u64 wep_sw_enc_cnt_uc;
+	u64 wep_sw_dec_cnt_bc;
+	u64 wep_sw_dec_cnt_mc;
+	u64 wep_sw_dec_cnt_uc;
+
+	u64 tkip_sw_enc_cnt_bc;
+	u64 tkip_sw_enc_cnt_mc;
+	u64 tkip_sw_enc_cnt_uc;
+	u64 tkip_sw_dec_cnt_bc;
+	u64 tkip_sw_dec_cnt_mc;
+	u64 tkip_sw_dec_cnt_uc;
+
+	u64 aes_sw_enc_cnt_bc;
+	u64 aes_sw_enc_cnt_mc;
+	u64 aes_sw_enc_cnt_uc;
+	u64 aes_sw_dec_cnt_bc;
+	u64 aes_sw_dec_cnt_mc;
+	u64 aes_sw_dec_cnt_uc;
+#endif /* DBG_SW_SEC_CNT */
+};
+
+#ifdef CONFIG_IEEE80211W
+#define SEC_IS_BIP_KEY_INSTALLED(sec) ((sec)->binstallBIPkey)
+#else
+#define SEC_IS_BIP_KEY_INSTALLED(sec) _FALSE
+#endif
+
+struct _sha256_state {
+	u64 length;
+	u32 state[8], curlen;
+	u8 buf[64];
+};
+
+#define GET_ENCRY_ALGO(psecuritypriv, psta, encry_algo, bmcst)\
+	do {\
+		switch (psecuritypriv->dot11AuthAlgrthm) {\
+		case dot11AuthAlgrthm_Open:\
+		case dot11AuthAlgrthm_Shared:\
+		case dot11AuthAlgrthm_Auto:\
+			encry_algo = (u8)psecuritypriv->dot11PrivacyAlgrthm;\
+			break;\
+		case dot11AuthAlgrthm_8021X:\
+			if (bmcst)\
+				encry_algo = (u8)psecuritypriv->dot118021XGrpPrivacy;\
+			else\
+				encry_algo = (u8) psta->dot118021XPrivacy;\
+			break;\
+		case dot11AuthAlgrthm_WAPI:\
+			encry_algo = (u8)psecuritypriv->dot11PrivacyAlgrthm;\
+			break;\
+		} \
+	} while (0)
+
+#define _AES_IV_LEN_ 8
+
+#define SET_ICE_IV_LEN(iv_len, icv_len, encrypt)\
+	do {\
+		switch (encrypt) {\
+		case _WEP40_:\
+		case _WEP104_:\
+			iv_len = 4;\
+			icv_len = 4;\
+			break;\
+		case _TKIP_:\
+			iv_len = 8;\
+			icv_len = 4;\
+			break;\
+		case _AES_:\
+			iv_len = 8;\
+			icv_len = 8;\
+			break;\
+		case _SMS4_:\
+			iv_len = 18;\
+			icv_len = 16;\
+			break;\
+		default:\
+			iv_len = 0;\
+			icv_len = 0;\
+			break;\
+		} \
+	} while (0)
+
+
+#define GET_TKIP_PN(iv, dot11txpn)\
+	do {\
+		dot11txpn._byte_.TSC0 = iv[2];\
+		dot11txpn._byte_.TSC1 = iv[0];\
+		dot11txpn._byte_.TSC2 = iv[4];\
+		dot11txpn._byte_.TSC3 = iv[5];\
+		dot11txpn._byte_.TSC4 = iv[6];\
+		dot11txpn._byte_.TSC5 = iv[7];\
+	} while (0)
+
+
+#define ROL32(A, n)	(((A) << (n)) | (((A)>>(32-(n)))  & ((1UL << (n)) - 1)))
+#define ROR32(A, n)	ROL32((A), 32-(n))
+
+struct mic_data {
+	u32  K0, K1;         /* Key */
+	u32  L, R;           /* Current state */
+	u32  M;              /* Message accumulator (single word) */
+	u32     nBytesInM;      /*  # bytes in M */
+};
+
+extern const u32 Te0[256];
+extern const u32 Te1[256];
+extern const u32 Te2[256];
+extern const u32 Te3[256];
+extern const u32 Te4[256];
+extern const u32 Td0[256];
+extern const u32 Td1[256];
+extern const u32 Td2[256];
+extern const u32 Td3[256];
+extern const u32 Td4[256];
+extern const u32 rcon[10];
+extern const u8 Td4s[256];
+extern const u8 rcons[10];
+
+#define RCON(i) (rcons[(i)] << 24)
+
+static inline u32 rotr(u32 val, int bits)
+{
+	return (val >> bits) | (val << (32 - bits));
+}
+
+#define TE0(i) Te0[((i) >> 24) & 0xff]
+#define TE1(i) rotr(Te0[((i) >> 16) & 0xff], 8)
+#define TE2(i) rotr(Te0[((i) >> 8) & 0xff], 16)
+#define TE3(i) rotr(Te0[(i) & 0xff], 24)
+#define TE41(i) ((Te0[((i) >> 24) & 0xff] << 8) & 0xff000000)
+#define TE42(i) (Te0[((i) >> 16) & 0xff] & 0x00ff0000)
+#define TE43(i) (Te0[((i) >> 8) & 0xff] & 0x0000ff00)
+#define TE44(i) ((Te0[(i) & 0xff] >> 8) & 0x000000ff)
+#define TE421(i) ((Te0[((i) >> 16) & 0xff] << 8) & 0xff000000)
+#define TE432(i) (Te0[((i) >> 8) & 0xff] & 0x00ff0000)
+#define TE443(i) (Te0[(i) & 0xff] & 0x0000ff00)
+#define TE414(i) ((Te0[((i) >> 24) & 0xff] >> 8) & 0x000000ff)
+#define TE4(i) ((Te0[(i)] >> 8) & 0x000000ff)
+
+#define TD0(i) Td0[((i) >> 24) & 0xff]
+#define TD1(i) rotr(Td0[((i) >> 16) & 0xff], 8)
+#define TD2(i) rotr(Td0[((i) >> 8) & 0xff], 16)
+#define TD3(i) rotr(Td0[(i) & 0xff], 24)
+#define TD41(i) (Td4s[((i) >> 24) & 0xff] << 24)
+#define TD42(i) (Td4s[((i) >> 16) & 0xff] << 16)
+#define TD43(i) (Td4s[((i) >> 8) & 0xff] << 8)
+#define TD44(i) (Td4s[(i) & 0xff])
+#define TD0_(i) Td0[(i) & 0xff]
+#define TD1_(i) rotr(Td0[(i) & 0xff], 8)
+#define TD2_(i) rotr(Td0[(i) & 0xff], 16)
+#define TD3_(i) rotr(Td0[(i) & 0xff], 24)
+
+#define GETU32(pt) (((u32)(pt)[0] << 24) ^ ((u32)(pt)[1] << 16) ^ \
+			((u32)(pt)[2] <<  8) ^ ((u32)(pt)[3]))
+
+#define PUTU32(ct, st) { \
+		(ct)[0] = (u8)((st) >> 24); (ct)[1] = (u8)((st) >> 16); \
+		(ct)[2] = (u8)((st) >>  8); (ct)[3] = (u8)(st); }
+
+#define WPA_GET_BE32(a) ((((u32) (a)[0]) << 24) | (((u32) (a)[1]) << 16) | \
+			 (((u32) (a)[2]) << 8) | ((u32) (a)[3]))
+
+#define WPA_PUT_LE16(a, val)			\
+	do {					\
+		(a)[1] = ((u16) (val)) >> 8;	\
+		(a)[0] = ((u16) (val)) & 0xff;	\
+	} while (0)
+
+#define WPA_PUT_BE32(a, val)					\
+	do {							\
+		(a)[0] = (u8) ((((u32) (val)) >> 24) & 0xff);	\
+		(a)[1] = (u8) ((((u32) (val)) >> 16) & 0xff);	\
+		(a)[2] = (u8) ((((u32) (val)) >> 8) & 0xff);	\
+		(a)[3] = (u8) (((u32) (val)) & 0xff);		\
+	} while (0)
+
+#define WPA_PUT_BE64(a, val)				\
+	do {						\
+		(a)[0] = (u8) (((u64) (val)) >> 56);	\
+		(a)[1] = (u8) (((u64) (val)) >> 48);	\
+		(a)[2] = (u8) (((u64) (val)) >> 40);	\
+		(a)[3] = (u8) (((u64) (val)) >> 32);	\
+		(a)[4] = (u8) (((u64) (val)) >> 24);	\
+		(a)[5] = (u8) (((u64) (val)) >> 16);	\
+		(a)[6] = (u8) (((u64) (val)) >> 8);	\
+		(a)[7] = (u8) (((u64) (val)) & 0xff);	\
+	} while (0)
+
+/* the K array */
+static const unsigned long K[64] = {
+	0x428a2f98UL, 0x71374491UL, 0xb5c0fbcfUL, 0xe9b5dba5UL, 0x3956c25bUL,
+	0x59f111f1UL, 0x923f82a4UL, 0xab1c5ed5UL, 0xd807aa98UL, 0x12835b01UL,
+	0x243185beUL, 0x550c7dc3UL, 0x72be5d74UL, 0x80deb1feUL, 0x9bdc06a7UL,
+	0xc19bf174UL, 0xe49b69c1UL, 0xefbe4786UL, 0x0fc19dc6UL, 0x240ca1ccUL,
+	0x2de92c6fUL, 0x4a7484aaUL, 0x5cb0a9dcUL, 0x76f988daUL, 0x983e5152UL,
+	0xa831c66dUL, 0xb00327c8UL, 0xbf597fc7UL, 0xc6e00bf3UL, 0xd5a79147UL,
+	0x06ca6351UL, 0x14292967UL, 0x27b70a85UL, 0x2e1b2138UL, 0x4d2c6dfcUL,
+	0x53380d13UL, 0x650a7354UL, 0x766a0abbUL, 0x81c2c92eUL, 0x92722c85UL,
+	0xa2bfe8a1UL, 0xa81a664bUL, 0xc24b8b70UL, 0xc76c51a3UL, 0xd192e819UL,
+	0xd6990624UL, 0xf40e3585UL, 0x106aa070UL, 0x19a4c116UL, 0x1e376c08UL,
+	0x2748774cUL, 0x34b0bcb5UL, 0x391c0cb3UL, 0x4ed8aa4aUL, 0x5b9cca4fUL,
+	0x682e6ff3UL, 0x748f82eeUL, 0x78a5636fUL, 0x84c87814UL, 0x8cc70208UL,
+	0x90befffaUL, 0xa4506cebUL, 0xbef9a3f7UL, 0xc67178f2UL
+};
+
+
+/* Various logical functions */
+#define RORc(x, y) \
+	(((((unsigned long) (x) & 0xFFFFFFFFUL) >> (unsigned long) ((y) & 31)) | \
+	  ((unsigned long) (x) << (unsigned long) (32 - ((y) & 31)))) & 0xFFFFFFFFUL)
+#define Ch(x, y, z)       (z ^ (x & (y ^ z)))
+#define Maj(x, y, z)      (((x | y) & z) | (x & y))
+#define S(x, n)         RORc((x), (n))
+#define R(x, n)         (((x) & 0xFFFFFFFFUL)>>(n))
+#define Sigma0(x)       (S(x, 2) ^ S(x, 13) ^ S(x, 22))
+#define Sigma1(x)       (S(x, 6) ^ S(x, 11) ^ S(x, 25))
+#define Gamma0(x)       (S(x, 7) ^ S(x, 18) ^ R(x, 3))
+#define Gamma1(x)       (S(x, 17) ^ S(x, 19) ^ R(x, 10))
+#ifndef MIN
+#define MIN(x, y) (((x) < (y)) ? (x) : (y))
+#endif
+#ifdef CONFIG_IEEE80211W
+int omac1_aes_128(const u8 *key, const u8 *data, size_t data_len, u8 *mac);
+#endif /* CONFIG_IEEE80211W */
+#ifdef CONFIG_RTW_MESH_AEK
+int aes_siv_encrypt(const u8 *key, const u8 *pw, size_t pwlen
+	, size_t num_elem, const u8 *addr[], const size_t *len, u8 *out);
+int aes_siv_decrypt(const u8 *key, const u8 *iv_crypt, size_t iv_c_len
+	, size_t num_elem, const u8 *addr[], const size_t *len, u8 *out);
+#endif
+void rtw_secmicsetkey(struct mic_data *pmicdata, u8 *key);
+void rtw_secmicappendbyte(struct mic_data *pmicdata, u8 b);
+void rtw_secmicappend(struct mic_data *pmicdata, u8 *src, u32 nBytes);
+void rtw_secgetmic(struct mic_data *pmicdata, u8 *dst);
+
+void rtw_seccalctkipmic(
+	u8 *key,
+	u8 *header,
+	u8 *data,
+	u32 data_len,
+	u8 *Miccode,
+	u8   priority);
+
+u32 rtw_aes_encrypt(_adapter *padapter, u8 *pxmitframe);
+u32 rtw_tkip_encrypt(_adapter *padapter, u8 *pxmitframe);
+void rtw_wep_encrypt(_adapter *padapter, u8  *pxmitframe);
+
+u32 rtw_aes_decrypt(_adapter *padapter, u8  *precvframe);
+u32 rtw_tkip_decrypt(_adapter *padapter, u8  *precvframe);
+void rtw_wep_decrypt(_adapter *padapter, u8  *precvframe);
+#ifdef CONFIG_IEEE80211W
+u32	rtw_BIP_verify(_adapter *padapter, u8 *whdr_pos, sint flen
+	, const u8 *key, u16 id, u64* ipn);
+#endif
+#ifdef CONFIG_TDLS
+void wpa_tdls_generate_tpk(_adapter *padapter, PVOID sta);
+int wpa_tdls_ftie_mic(u8 *kck, u8 trans_seq,
+			u8 *lnkid, u8 *rsnie, u8 *timeoutie, u8 *ftie,
+			u8 *mic);
+int wpa_tdls_teardown_ftie_mic(u8 *kck, u8 *lnkid, u16 reason,
+			u8 dialog_token, u8 trans_seq, u8 *ftie, u8 *mic);
+int tdls_verify_mic(u8 *kck, u8 trans_seq,
+			u8 *lnkid, u8 *rsnie, u8 *timeoutie, u8 *ftie);
+#endif /* CONFIG_TDLS */
+
+void rtw_sec_restore_wep_key(_adapter *adapter);
+u8 rtw_handle_tkip_countermeasure(_adapter *adapter, const char *caller);
+
+#ifdef CONFIG_WOWLAN
+u16 rtw_calc_crc(u8  *pdata, int length);
+#endif /*CONFIG_WOWLAN*/
+
+#endif /* __RTL871X_SECURITY_H_ */
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/include/rtw_sreset.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/rtw_sreset.h
--- linux-5.6.3/3rdparty/rtl8821ce/include/rtw_sreset.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/rtw_sreset.h	2020-04-10 16:35:06.852661748 +0300
@@ -0,0 +1,66 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#ifndef _RTW_SRESET_H_
+#define _RTW_SRESET_H_
+
+/* #include <drv_types.h> */
+
+enum {
+	SRESET_TGP_NULL = 0,
+	SRESET_TGP_XMIT_STATUS = 1,
+	SRESET_TGP_LINK_STATUS = 2,
+	SRESET_TGP_INFO = 99,
+};
+
+struct sreset_priv {
+	_mutex	silentreset_mutex;
+	u8	silent_reset_inprogress;
+	u8	Wifi_Error_Status;
+	systime last_tx_time;
+	systime last_tx_complete_time;
+
+	s32 dbg_trigger_point;
+	u64 self_dect_tx_cnt;
+	u64 self_dect_rx_cnt;
+	u64 self_dect_fw_cnt;
+	u64 tx_dma_status_cnt;
+	u64 rx_dma_status_cnt;
+	u8 rx_cnt;
+	u8 self_dect_fw;
+	u8 self_dect_case;
+	u16 last_mac_rxff_ptr;
+	u8 dbg_sreset_ctrl;
+};
+
+
+
+#define	WIFI_STATUS_SUCCESS		0
+#define	USB_VEN_REQ_CMD_FAIL	BIT0
+#define	USB_READ_PORT_FAIL		BIT1
+#define	USB_WRITE_PORT_FAIL		BIT2
+#define	WIFI_MAC_TXDMA_ERROR	BIT3
+#define   WIFI_TX_HANG				BIT4
+#define	WIFI_RX_HANG				BIT5
+#define	WIFI_IF_NOT_EXIST			BIT6
+
+void sreset_init_value(_adapter *padapter);
+void sreset_reset_value(_adapter *padapter);
+u8 sreset_get_wifi_status(_adapter *padapter);
+void sreset_set_wifi_error_status(_adapter *padapter, u32 status);
+void sreset_set_trigger_point(_adapter *padapter, s32 tgp);
+bool sreset_inprogress(_adapter *padapter);
+void sreset_reset(_adapter *padapter);
+
+#endif
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/include/rtw_tdls.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/rtw_tdls.h
--- linux-5.6.3/3rdparty/rtl8821ce/include/rtw_tdls.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/rtw_tdls.h	2020-04-10 16:35:06.852661748 +0300
@@ -0,0 +1,185 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#ifndef __RTW_TDLS_H_
+#define __RTW_TDLS_H_
+
+
+#ifdef CONFIG_TDLS
+/* TDLS STA state */
+
+
+/* TDLS Diect Link Establishment */
+#define	TDLS_STATE_NONE				0x00000000		/* Default state */
+#define	TDLS_INITIATOR_STATE		BIT(28)			/* 0x10000000 */
+#define	TDLS_RESPONDER_STATE		BIT(29)			/* 0x20000000 */
+#define	TDLS_LINKED_STATE			BIT(30)			/* 0x40000000 */
+/* TDLS PU Buffer STA */
+#define	TDLS_WAIT_PTR_STATE			BIT(24)			/* 0x01000000 */	/* Waiting peer's TDLS_PEER_TRAFFIC_RESPONSE frame */
+/* TDLS Check ALive */
+#define	TDLS_ALIVE_STATE			BIT(20)			/* 0x00100000 */	/* Check if peer sta is alived. */
+/* TDLS Channel Switch */
+#define	TDLS_CH_SWITCH_PREPARE_STATE	BIT(15)			/* 0x00008000 */
+#define	TDLS_CH_SWITCH_ON_STATE			BIT(16)			/* 0x00010000 */
+#define	TDLS_PEER_AT_OFF_STATE			BIT(17)			/* 0x00020000 */	/* Could send pkt on target ch */
+#define	TDLS_CH_SW_INITIATOR_STATE		BIT(18)			/* 0x00040000 */	/* Avoid duplicated or unconditional ch. switch rsp. */
+#define	TDLS_WAIT_CH_RSP_STATE			BIT(19)			/* 0x00080000 */	/* Wait Ch. response as we are TDLS channel switch initiator */
+
+
+#define	TDLS_TPK_RESEND_COUNT			86400	/*Unit: seconds */
+#define	TDLS_CH_SWITCH_TIME				15
+#define	TDLS_CH_SWITCH_TIMEOUT			30
+#define	TDLS_CH_SWITCH_OPER_OFFLOAD_TIMEOUT	10
+#define	TDLS_SIGNAL_THRESH			0x20
+#define	TDLS_WATCHDOG_PERIOD		10	/* Periodically sending tdls discovery request in TDLS_WATCHDOG_PERIOD * 2 sec */
+#define	TDLS_HANDSHAKE_TIME			3000
+#define	TDLS_PTI_TIME				7000
+
+#define TDLS_CH_SW_STAY_ON_BASE_CHNL_TIMEOUT	20		/* ms */
+#define TDLS_CH_SW_MONITOR_TIMEOUT				2000	/*ms */
+
+#define TDLS_MIC_LEN 16
+#define WPA_NONCE_LEN 32
+#define TDLS_TIMEOUT_LEN 4
+
+enum TDLS_CH_SW_CHNL {
+	TDLS_CH_SW_BASE_CHNL = 0,
+	TDLS_CH_SW_OFF_CHNL
+};
+
+#define TDLS_MIC_CTRL_LEN 2
+#define TDLS_FTIE_DATA_LEN (TDLS_MIC_CTRL_LEN + TDLS_MIC_LEN + \
+							WPA_NONCE_LEN + WPA_NONCE_LEN)
+struct wpa_tdls_ftie {
+	u8 ie_type; /* FTIE */
+	u8 ie_len;
+	union {
+		struct {
+			u8 mic_ctrl[TDLS_MIC_CTRL_LEN];
+			u8 mic[TDLS_MIC_LEN];
+			u8 Anonce[WPA_NONCE_LEN]; /* Responder Nonce in TDLS */
+			u8 Snonce[WPA_NONCE_LEN]; /* Initiator Nonce in TDLS */
+		};
+		struct {
+			u8 data[TDLS_FTIE_DATA_LEN];
+		};
+	};
+	/* followed by optional elements */
+} ;
+
+struct wpa_tdls_lnkid {
+	u8 ie_type; /* Link Identifier IE */
+	u8 ie_len;
+	u8 bssid[ETH_ALEN];
+	u8 init_sta[ETH_ALEN];
+	u8 resp_sta[ETH_ALEN];
+} ;
+
+static u8 TDLS_RSNIE[20] = {	0x01, 0x00,	/* Version shall be set to 1 */
+				0x00, 0x0f, 0xac, 0x07,	/* Group sipher suite */
+				0x01, 0x00,	/* Pairwise cipher suite count */
+	0x00, 0x0f, 0xac, 0x04,	/* Pairwise cipher suite list; CCMP only */
+				0x01, 0x00,	/* AKM suite count */
+				0x00, 0x0f, 0xac, 0x07,	/* TPK Handshake */
+				0x0c, 0x02,
+				/* PMKID shall not be present */
+			   };
+
+static u8 TDLS_WMMIE[] = {0x00, 0x50, 0xf2, 0x02, 0x00, 0x01, 0x00};	/* Qos info all set zero */
+
+static u8 TDLS_WMM_PARAM_IE[] = {0x00, 0x00, 0x03, 0xa4, 0x00, 0x00, 0x27, 0xa4, 0x00, 0x00, 0x42, 0x43, 0x5e, 0x00, 0x62, 0x32, 0x2f, 0x00};
+
+static u8 TDLS_EXT_CAPIE[] = {0x00, 0x00, 0x00, 0x50, 0x20, 0x00, 0x00, 0x00};	/* bit(28), bit(30), bit(37) */
+
+/* SRC: Supported Regulatory Classes */
+static u8 TDLS_SRC[] = { 0x01, 0x01, 0x02, 0x03, 0x04, 0x0c, 0x16, 0x17, 0x18, 0x19, 0x1b, 0x1c, 0x1d, 0x1e, 0x20, 0x21 };
+
+int check_ap_tdls_prohibited(u8 *pframe, u8 pkt_len);
+int check_ap_tdls_ch_switching_prohibited(u8 *pframe, u8 pkt_len);
+
+void rtw_set_tdls_enable(_adapter *padapter, u8 enable);
+u8 rtw_is_tdls_enabled(_adapter *padapter);
+u8 rtw_is_tdls_sta_existed(_adapter *padapter);
+u8 rtw_tdls_is_setup_allowed(_adapter *padapter);
+#ifdef CONFIG_TDLS_CH_SW
+u8 rtw_tdls_is_chsw_allowed(_adapter *padapter);
+#endif
+
+void rtw_tdls_set_link_established(_adapter *adapter, bool en);
+void rtw_reset_tdls_info(_adapter *padapter);
+int rtw_init_tdls_info(_adapter *padapter);
+void rtw_free_tdls_info(struct tdls_info *ptdlsinfo);
+void rtw_free_all_tdls_sta(_adapter *padapter, u8 enqueue_cmd);
+void rtw_enable_tdls_func(_adapter *padapter);
+void rtw_disable_tdls_func(_adapter *padapter, u8 enqueue_cmd);
+int issue_nulldata_to_TDLS_peer_STA(_adapter *padapter, unsigned char *da, unsigned int power_mode, int try_cnt, int wait_ms);
+void rtw_init_tdls_timer(_adapter *padapter, struct sta_info *psta);
+void	rtw_cancel_tdls_timer(struct sta_info *psta);
+void rtw_tdls_teardown_pre_hdl(_adapter *padapter, struct sta_info *psta);
+void rtw_tdls_teardown_post_hdl(_adapter *padapter, struct sta_info *psta, u8 enqueue_cmd);
+
+#ifdef CONFIG_TDLS_CH_SW
+void rtw_tdls_set_ch_sw_oper_control(_adapter *padapter, u8 enable);
+void rtw_tdls_ch_sw_back_to_base_chnl(_adapter *padapter);
+s32 rtw_tdls_do_ch_sw(_adapter *padapter, struct sta_info *ptdls_sta, u8 chnl_type, u8 channel, u8 channel_offset, u16 bwmode, u16 ch_switch_time);
+void rtw_tdls_chsw_oper_done(_adapter *padapter);
+#endif
+
+#ifdef CONFIG_WFD
+int issue_tunneled_probe_req(_adapter *padapter);
+int issue_tunneled_probe_rsp(_adapter *padapter, union recv_frame *precv_frame);
+#endif /* CONFIG_WFD */
+int issue_tdls_dis_req(_adapter *padapter, struct tdls_txmgmt *ptxmgmt);
+int issue_tdls_setup_req(_adapter *padapter, struct tdls_txmgmt *ptxmgmt, int wait_ack);
+int issue_tdls_setup_rsp(_adapter *padapter, struct tdls_txmgmt *ptxmgmt);
+int issue_tdls_setup_cfm(_adapter *padapter, struct tdls_txmgmt *ptxmgmt);
+int issue_tdls_dis_rsp(_adapter *padapter, struct tdls_txmgmt *ptxmgmt, u8 privacy);
+int issue_tdls_teardown(_adapter *padapter, struct tdls_txmgmt *ptxmgmt, u8 wait_ack);
+int issue_tdls_peer_traffic_rsp(_adapter *padapter, struct sta_info *psta, struct tdls_txmgmt *ptxmgmt);
+int issue_tdls_peer_traffic_indication(_adapter *padapter, struct sta_info *psta);
+#ifdef CONFIG_TDLS_CH_SW
+int issue_tdls_ch_switch_req(_adapter *padapter, struct sta_info *ptdls_sta);
+int issue_tdls_ch_switch_rsp(_adapter *padapter, struct tdls_txmgmt *ptxmgmt, int wait_ack);
+#endif
+sint On_TDLS_Dis_Rsp(_adapter *adapter, union recv_frame *precv_frame);
+sint On_TDLS_Setup_Req(_adapter *adapter, union recv_frame *precv_frame, struct sta_info *ptdls_sta);
+int On_TDLS_Setup_Rsp(_adapter *adapter, union recv_frame *precv_frame, struct sta_info *ptdls_sta);
+int On_TDLS_Setup_Cfm(_adapter *adapter, union recv_frame *precv_frame, struct sta_info *ptdls_sta);
+int On_TDLS_Dis_Req(_adapter *adapter, union recv_frame *precv_frame);
+int On_TDLS_Teardown(_adapter *adapter, union recv_frame *precv_frame, struct sta_info *ptdls_sta);
+int On_TDLS_Peer_Traffic_Indication(_adapter *adapter, union recv_frame *precv_frame, struct sta_info *ptdls_sta);
+int On_TDLS_Peer_Traffic_Rsp(_adapter *adapter, union recv_frame *precv_frame, struct sta_info *ptdls_sta);
+#ifdef CONFIG_TDLS_CH_SW
+sint On_TDLS_Ch_Switch_Req(_adapter *adapter, union recv_frame *precv_frame, struct sta_info *ptdls_sta);
+sint On_TDLS_Ch_Switch_Rsp(_adapter *adapter, union recv_frame *precv_frame, struct sta_info *ptdls_sta);
+void rtw_build_tdls_ch_switch_req_ies(_adapter *padapter, struct xmit_frame *pxmitframe, u8 *pframe, struct tdls_txmgmt *ptxmgmt, struct sta_info *ptdls_sta);
+void rtw_build_tdls_ch_switch_rsp_ies(_adapter *padapter, struct xmit_frame *pxmitframe, u8 *pframe, struct tdls_txmgmt *ptxmgmt, struct sta_info *ptdls_sta);
+#endif
+void rtw_build_tdls_setup_req_ies(_adapter *padapter, struct xmit_frame *pxmitframe, u8 *pframe, struct tdls_txmgmt *ptxmgmt, struct sta_info *ptdls_sta);
+void rtw_build_tdls_setup_rsp_ies(_adapter *padapter, struct xmit_frame *pxmitframe, u8 *pframe, struct tdls_txmgmt *ptxmgmt, struct sta_info *ptdls_sta);
+void rtw_build_tdls_setup_cfm_ies(_adapter *padapter, struct xmit_frame *pxmitframe, u8 *pframe, struct tdls_txmgmt *ptxmgmt, struct sta_info *ptdls_sta);
+void rtw_build_tdls_teardown_ies(_adapter *padapter, struct xmit_frame *pxmitframe, u8 *pframe, struct tdls_txmgmt *ptxmgmt, struct sta_info *ptdls_sta);
+void rtw_build_tdls_dis_req_ies(_adapter *padapter, struct xmit_frame *pxmitframe, u8 *pframe, struct tdls_txmgmt *ptxmgmt);
+void rtw_build_tdls_dis_rsp_ies(_adapter *padapter, struct xmit_frame *pxmitframe, u8 *pframe, struct tdls_txmgmt *ptxmgmt, u8 privacy);
+void rtw_build_tdls_peer_traffic_rsp_ies(_adapter *padapter, struct xmit_frame *pxmitframe, u8 *pframe, struct tdls_txmgmt *ptxmgmt, struct sta_info *ptdls_sta);
+void rtw_build_tdls_peer_traffic_indication_ies(_adapter *padapter, struct xmit_frame *pxmitframe, u8 *pframe, struct tdls_txmgmt *ptxmgmt, struct sta_info *ptdls_sta);
+void rtw_build_tunneled_probe_req_ies(_adapter *padapter, struct xmit_frame *pxmitframe, u8 *pframe);
+void rtw_build_tunneled_probe_rsp_ies(_adapter *padapter, struct xmit_frame *pxmitframe, u8 *pframe);
+
+int rtw_tdls_is_driver_setup(_adapter *padapter);
+void rtw_tdls_set_key(_adapter *padapter, struct sta_info *ptdls_sta);
+const char *rtw_tdls_action_txt(enum TDLS_ACTION_FIELD action);
+#endif /* CONFIG_TDLS */
+
+#endif
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/include/rtw_wapi.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/rtw_wapi.h
--- linux-5.6.3/3rdparty/rtl8821ce/include/rtw_wapi.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/rtw_wapi.h	2020-04-10 16:35:06.852661748 +0300
@@ -0,0 +1,230 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2016 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#ifndef __INC_WAPI_H
+#define __INC_WAPI_H
+
+
+#define CONFIG_WAPI_SW_SMS4
+#define WAPI_DEBUG
+
+#define SMS4_MIC_LEN                16
+#define WAPI_EXT_LEN                18
+#define MAX_WAPI_IE_LEN		    256
+#define sMacHdrLng				24		/* octets in data header, no WEP */
+
+#ifdef WAPI_DEBUG
+
+/* WAPI trace debug */
+extern u32 wapi_debug_component;
+
+static inline void dump_buf(u8 *buf, u32 len)
+{
+	u32 i;
+	printk("-----------------Len %d----------------\n", len);
+	for (i = 0; i < len; i++)
+		printk("%2.2x-", *(buf + i));
+	printk("\n");
+}
+
+#define WAPI_TRACE(component, x, args...) \
+	do { if (wapi_debug_component & (component)) \
+			printk(KERN_DEBUG "WAPI" ":" x "" , \
+			       ##args);\
+	} while (0);
+
+#define WAPI_DATA(component, x, buf, len) \
+	do { if (wapi_debug_component & (component)) { \
+			printk("%s:\n", x);\
+			dump_buf((buf), (len)); } \
+	} while (0);
+
+#define RT_ASSERT_RET(_Exp)								\
+	if (!(_Exp)) {									\
+		printk("RTWLAN: ");					\
+		printk("Assertion failed! %s,%s, line=%d\n", \
+		       #_Exp, __FUNCTION__, __LINE__);          \
+		return;						\
+	}
+#define RT_ASSERT_RET_VALUE(_Exp, Ret)								\
+	if (!(_Exp)) {									\
+		printk("RTWLAN: ");					\
+		printk("Assertion failed! %s,%s, line=%d\n", \
+		       #_Exp, __FUNCTION__, __LINE__);          \
+		return Ret;						\
+	}
+
+#else
+#define RT_ASSERT_RET(_Exp) do {} while (0)
+#define RT_ASSERT_RET_VALUE(_Exp, Ret) do {} while (0)
+#define WAPI_TRACE(component, x, args...) do {} while (0)
+#define WAPI_DATA(component, x, buf, len) do {} while (0)
+#endif
+
+
+enum WAPI_DEBUG {
+	WAPI_INIT				= 1,
+	WAPI_API				= 1 << 1,
+	WAPI_TX				= 1 << 2,
+	WAPI_RX				= 1 << 3,
+	WAPI_MLME				= 1 << 4,
+	WAPI_IOCTL				= 1 << 5,
+	WAPI_ERR			= 1 << 31
+};
+
+#define			WAPI_MAX_BKID_NUM				4
+#define			WAPI_MAX_STAINFO_NUM			4
+#define			WAPI_CAM_ENTRY_NUM			14	/* 28/2 = 14 */
+
+typedef struct  _RT_WAPI_BKID {
+	struct list_head	list;
+	u8				bkid[16];
+} RT_WAPI_BKID, *PRT_WAPI_BKID;
+
+typedef struct  _RT_WAPI_KEY {
+	u8			dataKey[16];
+	u8			micKey[16];
+	u8			keyId;
+	bool			bSet;
+	bool             bTxEnable;
+} RT_WAPI_KEY, *PRT_WAPI_KEY;
+
+typedef enum _RT_WAPI_PACKET_TYPE {
+	WAPI_NONE = 0,
+	WAPI_PREAUTHENTICATE = 1,
+	WAPI_STAKEY_REQUEST = 2,
+	WAPI_AUTHENTICATE_ACTIVE = 3,
+	WAPI_ACCESS_AUTHENTICATE_REQUEST = 4,
+	WAPI_ACCESS_AUTHENTICATE_RESPONSE = 5,
+	WAPI_CERTIFICATE_AUTHENTICATE_REQUEST = 6,
+	WAPI_CERTIFICATE_AUTHENTICATE_RESPONSE = 7,
+	WAPI_USK_REQUEST = 8,
+	WAPI_USK_RESPONSE = 9,
+	WAPI_USK_CONFIRM = 10,
+	WAPI_MSK_NOTIFICATION = 11,
+	WAPI_MSK_RESPONSE = 12
+} RT_WAPI_PACKET_TYPE;
+
+typedef struct	_RT_WAPI_STA_INFO {
+	struct list_head		list;
+	u8					PeerMacAddr[6];
+	RT_WAPI_KEY		      wapiUsk;
+	RT_WAPI_KEY		      wapiUskUpdate;
+	RT_WAPI_KEY		      wapiMsk;
+	RT_WAPI_KEY		      wapiMskUpdate;
+	u8					lastRxUnicastPN[16];
+	u8					lastTxUnicastPN[16];
+	u8					lastRxMulticastPN[16];
+	u8					lastRxUnicastPNBEQueue[16];
+	u8					lastRxUnicastPNBKQueue[16];
+	u8					lastRxUnicastPNVIQueue[16];
+	u8					lastRxUnicastPNVOQueue[16];
+	bool					bSetkeyOk;
+	bool					bAuthenticateInProgress;
+	bool					bAuthenticatorInUpdata;
+} RT_WAPI_STA_INFO, *PRT_WAPI_STA_INFO;
+
+/* Added for HW wapi en/decryption */
+typedef struct _RT_WAPI_CAM_ENTRY {
+	/* RT_LIST_ENTRY		list; */
+	u8			IsUsed;
+	u8			entry_idx;/* for cam entry */
+	u8			keyidx;	/* 0 or 1,new or old key */
+	u8			PeerMacAddr[6];
+	u8			type;	/* should be 110,wapi */
+} RT_WAPI_CAM_ENTRY, *PRT_WAPI_CAM_ENTRY;
+
+typedef struct _RT_WAPI_T {
+	/* BKID */
+	RT_WAPI_BKID		wapiBKID[WAPI_MAX_BKID_NUM];
+	struct list_head		wapiBKIDIdleList;
+	struct list_head		wapiBKIDStoreList;
+	/* Key for Tx Multicast/Broadcast */
+	RT_WAPI_KEY		      wapiTxMsk;
+
+	/* sec related */
+	u8				lastTxMulticastPN[16];
+	/* STA list */
+	RT_WAPI_STA_INFO	wapiSta[WAPI_MAX_STAINFO_NUM];
+	struct list_head		wapiSTAIdleList;
+	struct list_head		wapiSTAUsedList;
+	/*  */
+	bool				bWapiEnable;
+
+	/* store WAPI IE */
+	u8				wapiIE[256];
+	u8				wapiIELength;
+	bool				bWapiPSK;
+	/* last sequece number for wai packet */
+	u16				wapiSeqnumAndFragNum;
+	int extra_prefix_len;
+	int extra_postfix_len;
+
+	RT_WAPI_CAM_ENTRY	wapiCamEntry[WAPI_CAM_ENTRY_NUM];
+} RT_WAPI_T, *PRT_WAPI_T;
+
+typedef struct _WLAN_HEADER_WAPI_EXTENSION {
+	u8      KeyIdx;
+	u8      Reserved;
+	u8      PN[16];
+} WLAN_HEADER_WAPI_EXTENSION, *PWLAN_HEADER_WAPI_EXTENSION;
+
+u32 WapiComparePN(u8 *PN1, u8 *PN2);
+
+
+void rtw_wapi_init(_adapter *padapter);
+
+void rtw_wapi_free(_adapter *padapter);
+
+void rtw_wapi_disable_tx(_adapter *padapter);
+
+u8 rtw_wapi_is_wai_packet(_adapter *padapter, u8 *pkt_data);
+
+void rtw_wapi_update_info(_adapter *padapter, union recv_frame *precv_frame);
+
+u8 rtw_wapi_check_for_drop(_adapter *padapter, union recv_frame *precv_frame, u8 *ehdr_ops);
+
+void rtw_build_probe_resp_wapi_ie(_adapter *padapter, unsigned char *pframe, struct pkt_attrib *pattrib);
+
+void rtw_build_beacon_wapi_ie(_adapter *padapter, unsigned char *pframe, struct pkt_attrib *pattrib);
+
+void rtw_build_assoc_req_wapi_ie(_adapter *padapter, unsigned char *pframe, struct pkt_attrib *pattrib);
+
+void rtw_wapi_on_assoc_ok(_adapter *padapter, PNDIS_802_11_VARIABLE_IEs pIE);
+
+void rtw_wapi_return_one_sta_info(_adapter *padapter, u8 *MacAddr);
+
+void rtw_wapi_return_all_sta_info(_adapter *padapter);
+
+void rtw_wapi_clear_cam_entry(_adapter *padapter, u8 *pMacAddr);
+
+void rtw_wapi_clear_all_cam_entry(_adapter *padapter);
+
+void rtw_wapi_set_key(_adapter *padapter, RT_WAPI_KEY *pWapiKey, RT_WAPI_STA_INFO *pWapiSta, u8 bGroupKey, u8 bUseDefaultKey);
+
+int rtw_wapi_create_event_send(_adapter *padapter, u8 EventId, u8 *MacAddr, u8 *Buff, u16 BufLen);
+
+u32	rtw_sms4_encrypt(_adapter *padapter, u8 *pxmitframe);
+
+u32	rtw_sms4_decrypt(_adapter *padapter, u8 *precvframe);
+
+void rtw_wapi_get_iv(_adapter *padapter, u8 *pRA, u8 *IV);
+
+u8 WapiIncreasePN(u8 *PN, u8 AddCount);
+
+bool rtw_wapi_drop_for_key_absent(_adapter *padapter, u8 *pRA);
+
+void rtw_wapi_set_set_encryption(_adapter *padapter, struct ieee_param *param);
+
+#endif
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/include/rtw_version.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/rtw_version.h
--- linux-5.6.3/3rdparty/rtl8821ce/include/rtw_version.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/rtw_version.h	2020-04-10 16:35:06.852661748 +0300
@@ -0,0 +1,2 @@
+#define DRIVERVERSION	"v5.5.2_34066.20200325_COEX20180712-3232"
+#define BTCOEXVERSION	"COEX20180712-3232"
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/include/rtw_vht.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/rtw_vht.h
--- linux-5.6.3/3rdparty/rtl8821ce/include/rtw_vht.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/rtw_vht.h	2020-04-10 16:35:06.852661748 +0300
@@ -0,0 +1,176 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#ifndef _RTW_VHT_H_
+#define _RTW_VHT_H_
+
+#define VHT_CAP_IE_LEN 12
+#define VHT_OP_IE_LEN 5
+
+#define	LDPC_VHT_ENABLE_RX			BIT0
+#define	LDPC_VHT_ENABLE_TX			BIT1
+#define	LDPC_VHT_TEST_TX_ENABLE		BIT2
+#define	LDPC_VHT_CAP_TX				BIT3
+
+#define	STBC_VHT_ENABLE_RX			BIT0
+#define	STBC_VHT_ENABLE_TX			BIT1
+#define	STBC_VHT_TEST_TX_ENABLE		BIT2
+#define	STBC_VHT_CAP_TX				BIT3
+
+/* VHT capability info */
+#define SET_VHT_CAPABILITY_ELE_MAX_MPDU_LENGTH(_pEleStart, _val)			SET_BITS_TO_LE_1BYTE(_pEleStart, 0, 2, _val)
+#define SET_VHT_CAPABILITY_ELE_CHL_WIDTH(_pEleStart, _val)			SET_BITS_TO_LE_1BYTE(_pEleStart, 2, 2, _val)
+#define SET_VHT_CAPABILITY_ELE_RX_LDPC(_pEleStart, _val)			SET_BITS_TO_LE_1BYTE(_pEleStart, 4, 1, _val)
+#define SET_VHT_CAPABILITY_ELE_SHORT_GI80M(_pEleStart, _val)				SET_BITS_TO_LE_1BYTE(_pEleStart, 5, 1, _val)
+#define SET_VHT_CAPABILITY_ELE_SHORT_GI160M(_pEleStart, _val)				SET_BITS_TO_LE_1BYTE(_pEleStart, 6, 1, _val)
+#define SET_VHT_CAPABILITY_ELE_TX_STBC(_pEleStart, _val)				SET_BITS_TO_LE_1BYTE(_pEleStart, 7, 1, _val)
+#define SET_VHT_CAPABILITY_ELE_RX_STBC(_pEleStart, _val)				SET_BITS_TO_LE_1BYTE((_pEleStart)+1, 0, 3, _val)
+#define SET_VHT_CAPABILITY_ELE_SU_BFER(_pEleStart, _val)				SET_BITS_TO_LE_1BYTE((_pEleStart)+1, 3, 1, _val)
+#define SET_VHT_CAPABILITY_ELE_SU_BFEE(_pEleStart, _val)				SET_BITS_TO_LE_1BYTE((_pEleStart)+1, 4, 1, _val)
+#define SET_VHT_CAPABILITY_ELE_BFER_ANT_SUPP(_pEleStart, _val)				SET_BITS_TO_LE_1BYTE((_pEleStart)+1, 5, 3, _val)
+#define SET_VHT_CAPABILITY_ELE_SOUNDING_DIMENSIONS(_pEleStart, _val)				SET_BITS_TO_LE_1BYTE((_pEleStart)+2, 0, 3, _val)
+
+#define SET_VHT_CAPABILITY_ELE_MU_BFER(_pEleStart, _val)				SET_BITS_TO_LE_1BYTE((_pEleStart)+2, 3, 1, _val)
+#define SET_VHT_CAPABILITY_ELE_MU_BFEE(_pEleStart, _val)				SET_BITS_TO_LE_1BYTE((_pEleStart)+2, 4, 1, _val)
+#define SET_VHT_CAPABILITY_ELE_TXOP_PS(_pEleStart, _val)				SET_BITS_TO_LE_1BYTE((_pEleStart)+2, 5, 1, _val)
+#define SET_VHT_CAPABILITY_ELE_HTC_VHT(_pEleStart, _val)				SET_BITS_TO_LE_1BYTE((_pEleStart)+2, 6, 1, _val)
+#define SET_VHT_CAPABILITY_ELE_MAX_RXAMPDU_FACTOR(_pEleStart, _val)		SET_BITS_TO_LE_2BYTE((_pEleStart)+2, 7, 3, _val) /* B23~B25 */
+#define SET_VHT_CAPABILITY_ELE_LINK_ADAPTION(_pEleStart, _val)				SET_BITS_TO_LE_1BYTE((_pEleStart)+2, 2, 2, _val)
+#define SET_VHT_CAPABILITY_ELE_MCS_RX_MAP(_pEleStart, _val)				SET_BITS_TO_LE_2BYTE((_pEleStart)+4, 0, 16, _val)   /* B0~B15 indicate Rx MCS MAP, we write 0 to indicate MCS0~7. by page */
+#define SET_VHT_CAPABILITY_ELE_MCS_RX_HIGHEST_RATE(_pEleStart, _val)				SET_BITS_TO_LE_2BYTE((_pEleStart)+6, 0, 13, _val)
+#define SET_VHT_CAPABILITY_ELE_MCS_TX_MAP(_pEleStart, _val)				SET_BITS_TO_LE_2BYTE((_pEleStart)+8, 0, 16, _val)   /* B0~B15 indicate Tx MCS MAP, we write 0 to indicate MCS0~7. by page */
+#define SET_VHT_CAPABILITY_ELE_MCS_TX_HIGHEST_RATE(_pEleStart, _val)				SET_BITS_TO_LE_2BYTE((_pEleStart)+10, 0, 13, _val)
+
+
+#define GET_VHT_CAPABILITY_ELE_MAX_MPDU_LENGTH(_pEleStart)			LE_BITS_TO_1BYTE(_pEleStart, 0, 2)
+#define GET_VHT_CAPABILITY_ELE_CHL_WIDTH(_pEleStart)				LE_BITS_TO_1BYTE(_pEleStart, 2, 2)
+#define GET_VHT_CAPABILITY_ELE_RX_LDPC(_pEleStart)			LE_BITS_TO_1BYTE(_pEleStart, 4, 1)
+#define GET_VHT_CAPABILITY_ELE_SHORT_GI80M(_pEleStart)				LE_BITS_TO_1BYTE(_pEleStart, 5, 1)
+#define GET_VHT_CAPABILITY_ELE_SHORT_GI160M(_pEleStart)				LE_BITS_TO_1BYTE(_pEleStart, 6, 1)
+#define GET_VHT_CAPABILITY_ELE_TX_STBC(_pEleStart)				LE_BITS_TO_1BYTE(_pEleStart, 7, 1)
+#define GET_VHT_CAPABILITY_ELE_RX_STBC(_pEleStart)				LE_BITS_TO_1BYTE((_pEleStart)+1, 0, 3)
+#define GET_VHT_CAPABILITY_ELE_SU_BFER(_pEleStart)					LE_BITS_TO_1BYTE((_pEleStart)+1, 3, 1)
+#define GET_VHT_CAPABILITY_ELE_SU_BFEE(_pEleStart)					LE_BITS_TO_1BYTE((_pEleStart)+1, 4, 1)
+/*phydm-beamforming*/
+#define GET_VHT_CAPABILITY_ELE_SU_BFEE_STS_CAP(_pEleStart)	LE_BITS_TO_2BYTE((_pEleStart)+1, 5, 3)
+#define GET_VHT_CAPABILITY_ELE_SU_BFER_SOUND_DIM_NUM(_pEleStart)	LE_BITS_TO_2BYTE((_pEleStart)+2, 0, 3)
+#define GET_VHT_CAPABILITY_ELE_MU_BFER(_pEleStart)				LE_BITS_TO_1BYTE((_pEleStart)+2, 3, 1)
+#define GET_VHT_CAPABILITY_ELE_MU_BFEE(_pEleStart)				LE_BITS_TO_1BYTE((_pEleStart)+2, 4, 1)
+#define GET_VHT_CAPABILITY_ELE_TXOP_PS(_pEleStart)				LE_BITS_TO_1BYTE((_pEleStart)+2, 5, 1)
+#define GET_VHT_CAPABILITY_ELE_MAX_RXAMPDU_FACTOR(_pEleStart)	LE_BITS_TO_2BYTE((_pEleStart)+2, 7, 3)
+#define GET_VHT_CAPABILITY_ELE_RX_MCS(_pEleStart)					       ((_pEleStart)+4)
+#define GET_VHT_CAPABILITY_ELE_MCS_RX_HIGHEST_RATE(_pEleStart)			LE_BITS_TO_2BYTE((_pEleStart)+6, 0, 13)
+#define GET_VHT_CAPABILITY_ELE_TX_MCS(_pEleStart)					       ((_pEleStart)+8)
+#define GET_VHT_CAPABILITY_ELE_MCS_TX_HIGHEST_RATE(_pEleStart)			LE_BITS_TO_2BYTE((_pEleStart)+10, 0, 13)
+
+
+/* VHT Operation Information Element */
+#define SET_VHT_OPERATION_ELE_CHL_WIDTH(_pEleStart, _val)			SET_BITS_TO_LE_1BYTE(_pEleStart, 0, 8, _val)
+#define SET_VHT_OPERATION_ELE_CHL_CENTER_FREQ1(_pEleStart, _val)			SET_BITS_TO_LE_1BYTE(_pEleStart+1, 0, 8, _val)
+#define SET_VHT_OPERATION_ELE_CHL_CENTER_FREQ2(_pEleStart, _val)			SET_BITS_TO_LE_1BYTE(_pEleStart+2, 0, 8, _val)
+#define SET_VHT_OPERATION_ELE_BASIC_MCS_SET(_pEleStart, _val)			SET_BITS_TO_LE_2BYTE((_pEleStart)+3, 0, 16, _val)
+
+#define GET_VHT_OPERATION_ELE_CHL_WIDTH(_pEleStart)		LE_BITS_TO_1BYTE(_pEleStart, 0, 8)
+#define GET_VHT_OPERATION_ELE_CENTER_FREQ1(_pEleStart)	LE_BITS_TO_1BYTE((_pEleStart)+1, 0, 8)
+#define GET_VHT_OPERATION_ELE_CENTER_FREQ2(_pEleStart)     LE_BITS_TO_1BYTE((_pEleStart)+2, 0, 8)
+
+/* VHT Operating Mode */
+#define SET_VHT_OPERATING_MODE_FIELD_CHNL_WIDTH(_pEleStart, _val)		SET_BITS_TO_LE_1BYTE(_pEleStart, 0, 2, _val)
+#define SET_VHT_OPERATING_MODE_FIELD_RX_NSS(_pEleStart, _val)			SET_BITS_TO_LE_1BYTE(_pEleStart, 4, 3, _val)
+#define SET_VHT_OPERATING_MODE_FIELD_RX_NSS_TYPE(_pEleStart, _val)	SET_BITS_TO_LE_1BYTE(_pEleStart, 7, 1, _val)
+#define GET_VHT_OPERATING_MODE_FIELD_CHNL_WIDTH(_pEleStart)			LE_BITS_TO_1BYTE(_pEleStart, 0, 2)
+#define GET_VHT_OPERATING_MODE_FIELD_RX_NSS(_pEleStart)				LE_BITS_TO_1BYTE(_pEleStart, 4, 3)
+#define GET_VHT_OPERATING_MODE_FIELD_RX_NSS_TYPE(_pEleStart)		LE_BITS_TO_1BYTE(_pEleStart, 7, 1)
+
+#define SET_EXT_CAPABILITY_ELE_OP_MODE_NOTIF(_pEleStart, _val)			SET_BITS_TO_LE_1BYTE((_pEleStart)+7, 6, 1, _val)
+#define GET_EXT_CAPABILITY_ELE_OP_MODE_NOTIF(_pEleStart)				LE_BITS_TO_1BYTE((_pEleStart)+7, 6, 1)
+
+#define VHT_MAX_MPDU_LEN_MAX 3
+extern const u16 _vht_max_mpdu_len[];
+#define vht_max_mpdu_len(val) (((val) >= VHT_MAX_MPDU_LEN_MAX) ? _vht_max_mpdu_len[VHT_MAX_MPDU_LEN_MAX] : _vht_max_mpdu_len[(val)])
+
+#define VHT_SUP_CH_WIDTH_SET_MAX 3
+extern const u8 _vht_sup_ch_width_set_to_bw_cap[];
+#define vht_sup_ch_width_set_to_bw_cap(set) (((set) >= VHT_SUP_CH_WIDTH_SET_MAX) ? _vht_sup_ch_width_set_to_bw_cap[VHT_SUP_CH_WIDTH_SET_MAX] : _vht_sup_ch_width_set_to_bw_cap[(set)])
+extern const char *const _vht_sup_ch_width_set_str[];
+#define vht_sup_ch_width_set_str(set) (((set) >= VHT_SUP_CH_WIDTH_SET_MAX) ? _vht_sup_ch_width_set_str[VHT_SUP_CH_WIDTH_SET_MAX] : _vht_sup_ch_width_set_str[(set)])
+
+#define VHT_MAX_AMPDU_LEN(f) ((1 << (13 + f)) - 1)
+void dump_vht_cap_ie(void *sel, const u8 *ie, u32 ie_len);
+
+#define VHT_OP_CH_WIDTH_MAX 4
+extern const char *const _vht_op_ch_width_str[];
+#define vht_op_ch_width_str(ch_width) (((ch_width) >= VHT_OP_CH_WIDTH_MAX) ? _vht_op_ch_width_str[VHT_OP_CH_WIDTH_MAX] : _vht_op_ch_width_str[(ch_width)])
+
+void dump_vht_op_ie(void *sel, const u8 *ie, u32 ie_len);
+
+struct vht_priv {
+	u8	vht_option;
+
+	u8	ldpc_cap;
+	u8	stbc_cap;
+	u16	beamform_cap;
+	u8	ap_is_mu_bfer;
+
+	u8	sgi_80m;/* short GI */
+	u8	ampdu_len;
+
+	u8	vht_highest_rate;
+	u8	vht_mcs_map[2];
+
+	u8 op_present:1; /* vht_op is present */
+	u8 notify_present:1; /* vht_op_mode_notify is present */
+
+	u8 vht_cap[32];
+	u8 vht_op[VHT_OP_IE_LEN];
+	u8 vht_op_mode_notify;
+};
+
+#ifdef ROKU_PRIVATE
+struct vht_priv_infra_ap {
+
+	/* Infra mode, only store for AP's info, not intersection of STA and AP*/
+	u8	ldpc_cap_infra_ap;
+	u8	stbc_cap_infra_ap;
+	u16	beamform_cap_infra_ap;
+	u8	vht_mcs_map_infra_ap[2];
+	u8	vht_mcs_map_tx_infra_ap[2];
+	u8	channel_width_infra_ap;
+	u8	number_of_streams_infra_ap;
+};
+#endif /* ROKU_PRIVATE */
+
+u8	rtw_get_vht_highest_rate(u8 *pvht_mcs_map);
+u16	rtw_vht_mcs_to_data_rate(u8 bw, u8 short_GI, u8 vht_mcs_rate);
+u64	rtw_vht_mcs_map_to_bitmap(u8 *mcs_map, u8 nss);
+void	rtw_vht_use_default_setting(_adapter *padapter);
+u32	rtw_build_vht_operation_ie(_adapter *padapter, u8 *pbuf, u8 channel);
+u32	rtw_build_vht_op_mode_notify_ie(_adapter *padapter, u8 *pbuf, u8 bw);
+u32	rtw_build_vht_cap_ie(_adapter *padapter, u8 *pbuf);
+void	update_sta_vht_info_apmode(_adapter *padapter, PVOID psta);
+void	update_hw_vht_param(_adapter *padapter);
+void	VHT_caps_handler(_adapter *padapter, PNDIS_802_11_VARIABLE_IEs pIE);
+#ifdef ROKU_PRIVATE
+void	VHT_caps_handler_infra_ap(_adapter *padapter, PNDIS_802_11_VARIABLE_IEs pIE);
+#endif /* ROKU_PRIVATE */
+void	VHT_operation_handler(_adapter *padapter, PNDIS_802_11_VARIABLE_IEs pIE);
+void	rtw_process_vht_op_mode_notify(_adapter *padapter, u8 *pframe, PVOID sta);
+u32	rtw_restructure_vht_ie(_adapter *padapter, u8 *in_ie, u8 *out_ie, uint in_len, uint *pout_len);
+void	VHTOnAssocRsp(_adapter *padapter);
+u8	rtw_vht_mcsmap_to_nss(u8 *pvht_mcs_map);
+void rtw_vht_nss_to_mcsmap(u8 nss, u8 *target_mcs_map, u8 *cur_mcs_map);
+void rtw_vht_ies_attach(_adapter *padapter, WLAN_BSSID_EX *pcur_network);
+void rtw_vht_ies_detach(_adapter *padapter, WLAN_BSSID_EX *pcur_network);
+void rtw_check_for_vht20(_adapter *adapter, u8 *ies, int ies_len);
+#endif /* _RTW_VHT_H_ */
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/include/rtw_wifi_regd.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/rtw_wifi_regd.h
--- linux-5.6.3/3rdparty/rtl8821ce/include/rtw_wifi_regd.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/rtw_wifi_regd.h	2020-04-10 16:35:06.852661748 +0300
@@ -0,0 +1,34 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2009-2010 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+
+#ifndef __RTW_WIFI_REGD_H__
+#define __RTW_WIFI_REGD_H__
+
+struct country_code_to_enum_rd {
+	u16 countrycode;
+	const char *iso_name;
+};
+
+enum country_code_type_t {
+	COUNTRY_CODE_USER = 0,
+
+	/*add new channel plan above this line */
+	COUNTRY_CODE_MAX
+};
+
+void rtw_regd_apply_flags(struct wiphy *wiphy);
+int rtw_regd_init(struct wiphy *wiphy);
+
+#endif /* __RTW_WIFI_REGD_H__ */
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/include/rtw_xmit.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/rtw_xmit.h
--- linux-5.6.3/3rdparty/rtl8821ce/include/rtw_xmit.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/rtw_xmit.h	2020-04-10 16:35:06.852661748 +0300
@@ -0,0 +1,1051 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#ifndef _RTW_XMIT_H_
+#define _RTW_XMIT_H_
+
+
+#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
+	#ifdef CONFIG_TX_AGGREGATION
+		#define MAX_XMITBUF_SZ	(20480)	/* 20k */
+		/* #define SDIO_TX_AGG_MAX	5 */
+	#else
+		#define MAX_XMITBUF_SZ (1664)
+		#define SDIO_TX_AGG_MAX	1
+	#endif
+
+	#if defined CONFIG_SDIO_HCI
+		#define NR_XMITBUFF	(16)
+		#define SDIO_TX_DIV_NUM (2)
+	#endif
+	#if defined(CONFIG_GSPI_HCI)
+		#define NR_XMITBUFF	(128)
+	#endif
+
+#elif defined (CONFIG_USB_HCI)
+
+	#ifdef CONFIG_USB_TX_AGGREGATION
+		#if defined(CONFIG_PLATFORM_ARM_SUNxI) || defined(CONFIG_PLATFORM_ARM_SUN6I) || defined(CONFIG_PLATFORM_ARM_SUN7I) || defined(CONFIG_PLATFORM_ARM_SUN8I) || defined(CONFIG_PLATFORM_ARM_SUN50IW1P1)
+			#define MAX_XMITBUF_SZ (12288)  /* 12k 1536*8 */
+		#elif defined (CONFIG_PLATFORM_MSTAR)
+			#define MAX_XMITBUF_SZ	7680	/* 7.5k */
+		#else
+			#define MAX_XMITBUF_SZ	(20480)	/* 20k */
+		#endif
+	#else
+		#define MAX_XMITBUF_SZ	(2048)
+	#endif
+
+	#ifdef CONFIG_SINGLE_XMIT_BUF
+		#define NR_XMITBUFF	(1)
+	#else
+		#define NR_XMITBUFF	(4)
+	#endif /* CONFIG_SINGLE_XMIT_BUF */
+#elif defined (CONFIG_PCI_HCI)
+#ifdef CONFIG_TX_AMSDU
+	#define MAX_XMITBUF_SZ	(3500)
+#else
+	#define MAX_XMITBUF_SZ	(1664)
+#endif
+	#define NR_XMITBUFF	(128)
+#endif
+
+#ifdef PLATFORM_OS_CE
+	#define XMITBUF_ALIGN_SZ 4
+#else
+	#ifdef CONFIG_PCI_HCI
+		#define XMITBUF_ALIGN_SZ 4
+	#else
+		#ifdef USB_XMITBUF_ALIGN_SZ
+			#define XMITBUF_ALIGN_SZ (USB_XMITBUF_ALIGN_SZ)
+		#else
+			#define XMITBUF_ALIGN_SZ 512
+		#endif
+	#endif
+#endif
+
+/* xmit extension buff defination */
+#define MAX_XMIT_EXTBUF_SZ	(1536)
+
+#ifdef CONFIG_SINGLE_XMIT_BUF
+	#define NR_XMIT_EXTBUFF	(1)
+#else
+	#define NR_XMIT_EXTBUFF	(32)
+#endif
+
+#ifdef CONFIG_RTL8812A
+	#define MAX_CMDBUF_SZ	(512 * 18)
+#elif defined(CONFIG_RTL8723D) && defined(CONFIG_LPS_POFF)
+	#define MAX_CMDBUF_SZ	(128*70) /*(8960)*/
+#else
+	#define MAX_CMDBUF_SZ	(5120)	/* (4096) */
+#endif
+
+#define MAX_BEACON_LEN	512
+
+#define MAX_NUMBLKS		(1)
+
+#define XMIT_VO_QUEUE (0)
+#define XMIT_VI_QUEUE (1)
+#define XMIT_BE_QUEUE (2)
+#define XMIT_BK_QUEUE (3)
+
+#define VO_QUEUE_INX		0
+#define VI_QUEUE_INX		1
+#define BE_QUEUE_INX		2
+#define BK_QUEUE_INX		3
+#define BCN_QUEUE_INX		4
+#define MGT_QUEUE_INX		5
+#define HIGH_QUEUE_INX		6
+#define TXCMD_QUEUE_INX	7
+
+#define HW_QUEUE_ENTRY	8
+
+#ifdef CONFIG_PCI_HCI
+	#ifdef CONFIG_TRX_BD_ARCH
+		#define TX_BD_NUM			(128+1)	/* +1 result from ring buffer */
+	#else
+		#define TXDESC_NUM			128
+	#endif
+#endif
+
+#define WEP_IV(pattrib_iv, dot11txpn, keyidx)\
+	do {\
+		dot11txpn.val = (dot11txpn.val == 0xffffff) ? 0 : (dot11txpn.val + 1);\
+		pattrib_iv[0] = dot11txpn._byte_.TSC0;\
+		pattrib_iv[1] = dot11txpn._byte_.TSC1;\
+		pattrib_iv[2] = dot11txpn._byte_.TSC2;\
+		pattrib_iv[3] = ((keyidx & 0x3)<<6);\
+	} while (0)
+
+
+#define TKIP_IV(pattrib_iv, dot11txpn, keyidx)\
+	do {\
+		dot11txpn.val = dot11txpn.val == 0xffffffffffffULL ? 0 : (dot11txpn.val + 1);\
+		pattrib_iv[0] = dot11txpn._byte_.TSC1;\
+		pattrib_iv[1] = (dot11txpn._byte_.TSC1 | 0x20) & 0x7f;\
+		pattrib_iv[2] = dot11txpn._byte_.TSC0;\
+		pattrib_iv[3] = BIT(5) | ((keyidx & 0x3)<<6);\
+		pattrib_iv[4] = dot11txpn._byte_.TSC2;\
+		pattrib_iv[5] = dot11txpn._byte_.TSC3;\
+		pattrib_iv[6] = dot11txpn._byte_.TSC4;\
+		pattrib_iv[7] = dot11txpn._byte_.TSC5;\
+	} while (0)
+
+#define AES_IV(pattrib_iv, dot11txpn, keyidx)\
+	do {\
+		dot11txpn.val = dot11txpn.val == 0xffffffffffffULL ? 0 : (dot11txpn.val + 1);\
+		pattrib_iv[0] = dot11txpn._byte_.TSC0;\
+		pattrib_iv[1] = dot11txpn._byte_.TSC1;\
+		pattrib_iv[2] = 0;\
+		pattrib_iv[3] = BIT(5) | ((keyidx & 0x3)<<6);\
+		pattrib_iv[4] = dot11txpn._byte_.TSC2;\
+		pattrib_iv[5] = dot11txpn._byte_.TSC3;\
+		pattrib_iv[6] = dot11txpn._byte_.TSC4;\
+		pattrib_iv[7] = dot11txpn._byte_.TSC5;\
+	} while (0)
+
+/* Check if AMPDU Tx is supported or not. If it is supported,
+* it need to check "amsdu in ampdu" is supported or not.
+* (ampdu_en, amsdu_ampdu_en) =
+* (0, x) : AMPDU is not enable, but AMSDU is valid to send.
+* (1, 0) : AMPDU is enable, AMSDU in AMPDU is not enable. So, AMSDU is not valid to send.
+* (1, 1) : AMPDU and AMSDU in AMPDU are enable. So, AMSDU is valid to send.
+*/
+#define IS_AMSDU_AMPDU_NOT_VALID(pattrib)\
+	 ((pattrib->ampdu_en == _TRUE) && (pattrib->amsdu_ampdu_en == _FALSE))
+
+#define IS_AMSDU_AMPDU_VALID(pattrib)\
+	 !((pattrib->ampdu_en == _TRUE) && (pattrib->amsdu_ampdu_en == _FALSE))
+
+#define HWXMIT_ENTRY	4
+
+/* For Buffer Descriptor ring architecture */
+#if defined(BUF_DESC_ARCH) || defined(CONFIG_TRX_BD_ARCH)
+	#if defined(CONFIG_RTL8192E)
+		#define TX_BUFFER_SEG_NUM	1 /* 0:2 seg, 1: 4 seg, 2: 8 seg. */
+	#elif defined(CONFIG_RTL8814A)
+		#define TX_BUFFER_SEG_NUM	1 /* 0:2 seg, 1: 4 seg, 2: 8 seg. */
+	#else
+		#define TX_BUFFER_SEG_NUM	1 /* 0:2 seg, 1: 4 seg, 2: 8 seg. */
+	#endif
+#endif
+
+#if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A) ||\
+	defined(CONFIG_RTL8723B) || defined(CONFIG_RTL8192E) ||\
+	defined(CONFIG_RTL8814A) || defined(CONFIG_RTL8703B) ||\
+	defined(CONFIG_RTL8188F) || defined(CONFIG_RTL8188GTV) || defined(CONFIG_RTL8723D) ||\
+	defined(CONFIG_RTL8710B) || defined(CONFIG_RTL8192F)
+	#define TXDESC_SIZE 40
+#elif defined(CONFIG_RTL8822B)
+	#define TXDESC_SIZE 48		/* HALMAC_TX_DESC_SIZE_8822B */
+#elif defined(CONFIG_RTL8821C)
+	#define TXDESC_SIZE 48		/* HALMAC_TX_DESC_SIZE_8821C */
+#else
+	#define TXDESC_SIZE 32 /* old IC (ex: 8188E) */
+#endif
+
+#ifdef CONFIG_TX_EARLY_MODE
+	#define EARLY_MODE_INFO_SIZE	8
+#endif
+
+
+#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
+	#define TXDESC_OFFSET TXDESC_SIZE
+#endif
+
+#ifdef CONFIG_USB_HCI
+	#ifdef USB_PACKET_OFFSET_SZ
+		#define PACKET_OFFSET_SZ (USB_PACKET_OFFSET_SZ)
+	#else
+		#define PACKET_OFFSET_SZ (8)
+	#endif
+	#define TXDESC_OFFSET (TXDESC_SIZE + PACKET_OFFSET_SZ)
+#endif
+
+#ifdef CONFIG_PCI_HCI
+	#if defined(CONFIG_RTL8192E) || defined(CONFIG_RTL8814A) || defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C) || defined(CONFIG_TRX_BD_ARCH)
+		/* this section is defined for buffer descriptor ring architecture */
+		#define TX_WIFI_INFO_SIZE (TXDESC_SIZE) /* it may add 802.11 hdr or others... */
+		/* tx desc and payload are in the same buf */
+		#define TXDESC_OFFSET (TX_WIFI_INFO_SIZE)
+	#else
+		/* tx desc and payload are NOT in the same buf */
+		#define TXDESC_OFFSET (0)
+		/* 8188ee/8723be/8812ae/8821ae has extra PCI DMA info in tx desc */
+		#define TX_DESC_NEXT_DESC_OFFSET	(TXDESC_SIZE + 8)
+	#endif
+#endif /* CONFIG_PCI_HCI */
+
+enum TXDESC_SC {
+	SC_DONT_CARE = 0x00,
+	SC_UPPER = 0x01,
+	SC_LOWER = 0x02,
+	SC_DUPLICATE = 0x03
+};
+
+#ifdef CONFIG_PCI_HCI
+	#ifndef CONFIG_TRX_BD_ARCH	/* CONFIG_TRX_BD_ARCH doesn't need this */
+		#define TXDESC_64_BYTES
+	#endif
+#elif defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A) || defined(CONFIG_RTL8723B) \
+	|| defined(CONFIG_RTL8188F) || defined(CONFIG_RTL8188GTV) || defined(CONFIG_RTL8723D) \
+	|| defined(CONFIG_RTL8192F)
+	#define TXDESC_40_BYTES
+#endif
+
+#ifdef CONFIG_TRX_BD_ARCH
+struct tx_buf_desc {
+#ifdef CONFIG_64BIT_DMA
+#define TX_BUFFER_SEG_SIZE	4	/* in unit of DWORD */
+#else
+#define TX_BUFFER_SEG_SIZE	2	/* in unit of DWORD */
+#endif
+	unsigned int dword[TX_BUFFER_SEG_SIZE * (2 << TX_BUFFER_SEG_NUM)];
+} __packed;
+#elif (defined(CONFIG_RTL8192E) || defined(CONFIG_RTL8814A) || defined(CONFIG_RTL8822B)) && defined(CONFIG_PCI_HCI) /* 8192ee or 8814ae */
+/* 8192EE_TODO */
+struct tx_desc {
+	unsigned int txdw0;
+	unsigned int txdw1;
+	unsigned int txdw2;
+	unsigned int txdw3;
+	unsigned int txdw4;
+	unsigned int txdw5;
+	unsigned int txdw6;
+	unsigned int txdw7;
+};
+#else
+struct tx_desc {
+	unsigned int txdw0;
+	unsigned int txdw1;
+	unsigned int txdw2;
+	unsigned int txdw3;
+	unsigned int txdw4;
+	unsigned int txdw5;
+	unsigned int txdw6;
+	unsigned int txdw7;
+
+#if defined(TXDESC_40_BYTES) || defined(TXDESC_64_BYTES)
+	unsigned int txdw8;
+	unsigned int txdw9;
+#endif /* TXDESC_40_BYTES */
+
+#ifdef TXDESC_64_BYTES
+	unsigned int txdw10;
+	unsigned int txdw11;
+
+	/* 2008/05/15 MH Because PCIE HW memory R/W 4K limit. And now,  our descriptor */
+	/* size is 40 bytes. If you use more than 102 descriptor( 103*40>4096), HW will execute */
+	/* memoryR/W CRC error. And then all DMA fetch will fail. We must decrease descriptor */
+	/* number or enlarge descriptor size as 64 bytes. */
+	unsigned int txdw12;
+	unsigned int txdw13;
+	unsigned int txdw14;
+	unsigned int txdw15;
+#endif
+};
+#endif
+
+#ifndef CONFIG_TRX_BD_ARCH
+union txdesc {
+	struct tx_desc txdesc;
+	unsigned int value[TXDESC_SIZE >> 2];
+};
+#endif
+
+#ifdef CONFIG_PCI_HCI
+#define PCI_MAX_TX_QUEUE_COUNT	8	/* == HW_QUEUE_ENTRY */
+
+struct rtw_tx_ring {
+	unsigned char	qid;
+#ifdef CONFIG_TRX_BD_ARCH
+	struct tx_buf_desc	*buf_desc;
+#else
+	struct tx_desc	*desc;
+#endif
+	dma_addr_t	dma;
+	unsigned int	idx;
+	unsigned int	entries;
+	_queue		queue;
+	u32		qlen;
+#ifdef CONFIG_TRX_BD_ARCH
+	u16		hw_rp_cache;
+#endif
+};
+
+#ifdef DBG_TXBD_DESC_DUMP
+
+#define TX_BAK_FRMAE_CNT	10
+#define TX_BAK_DESC_LEN	48	/* byte */
+#define TX_BAK_DATA_LEN		30	/* byte */
+
+struct rtw_tx_desc_backup {
+	int tx_bak_rp;
+	int tx_bak_wp;
+	u8 tx_bak_desc[TX_BAK_DESC_LEN];
+	u8 tx_bak_data_hdr[TX_BAK_DATA_LEN];
+	u8 tx_desc_size;
+};
+#endif
+#endif
+
+struct	hw_xmit	{
+	/* _lock xmit_lock; */
+	/* _list	pending; */
+	_queue *sta_queue;
+	/* struct hw_txqueue *phwtxqueue; */
+	/* sint	txcmdcnt; */
+	int	accnt;
+};
+
+#if 0
+struct pkt_attrib {
+	u8	type;
+	u8	subtype;
+	u8	bswenc;
+	u8	dhcp_pkt;
+	u16	ether_type;
+	int	pktlen;		/* the original 802.3 pkt raw_data len (not include ether_hdr data) */
+	int	pkt_hdrlen;	/* the original 802.3 pkt header len */
+	int	hdrlen;		/* the WLAN Header Len */
+	int	nr_frags;
+	int	last_txcmdsz;
+	int	encrypt;	/* when 0 indicate no encrypt. when non-zero, indicate the encrypt algorith */
+	u8	iv[8];
+	int	iv_len;
+	u8	icv[8];
+	int	icv_len;
+	int	priority;
+	int	ack_policy;
+	int	mac_id;
+	int	vcs_mode;	/* virtual carrier sense method */
+
+	u8	dst[ETH_ALEN];
+	u8	src[ETH_ALEN];
+	u8	ta[ETH_ALEN];
+	u8	ra[ETH_ALEN];
+
+	u8	key_idx;
+
+	u8	qos_en;
+	u8	ht_en;
+	u8	raid;/* rate adpative id */
+	u8	bwmode;
+	u8	ch_offset;/* PRIME_CHNL_OFFSET */
+	u8	sgi;/* short GI */
+	u8	ampdu_en;/* tx ampdu enable */
+	u8	mdata;/* more data bit */
+	u8	eosp;
+
+	u8	triggered;/* for ap mode handling Power Saving sta */
+
+	u32	qsel;
+	u16	seqnum;
+
+	struct sta_info *psta;
+};
+#else
+/* reduce size */
+struct pkt_attrib {
+	u8	type;
+	u8	subtype;
+	u8	bswenc;
+	u8	dhcp_pkt;
+	u16	ether_type;
+	u16	seqnum;
+	u8	hw_ssn_sel;	/* for HW_SEQ0,1,2,3 */
+	u16	pkt_hdrlen;	/* the original 802.3 pkt header len */
+	u16	hdrlen;		/* the WLAN Header Len */
+	u32	pktlen;		/* the original 802.3 pkt raw_data len (not include ether_hdr data) */
+	u32	last_txcmdsz;
+	u8	nr_frags;
+	u8	encrypt;	/* when 0 indicate no encrypt. when non-zero, indicate the encrypt algorith */
+#if defined(CONFIG_CONCURRENT_MODE)
+	u8	bmc_camid;
+#endif
+	u8	iv_len;
+	u8	icv_len;
+	u8	iv[18];
+	u8	icv[16];
+	u8	priority;
+	u8	ack_policy;
+	u8	mac_id;
+	u8	vcs_mode;	/* virtual carrier sense method */
+	u8	dst[ETH_ALEN];
+	u8	src[ETH_ALEN];
+	u8	ta[ETH_ALEN];
+	u8	ra[ETH_ALEN];
+#ifdef CONFIG_RTW_MESH
+	u8	mda[ETH_ALEN];	/* mesh da */
+	u8	msa[ETH_ALEN];	/* mesh sa */
+	u8	meshctrl_len;	/* Length of Mesh Control field */
+	u8	mesh_frame_mode;
+	#if CONFIG_RTW_MESH_DATA_BMC_TO_UC
+	u8 mb2u;
+	#endif
+	u8 mfwd_ttl;
+	u32 mseq;
+#endif
+#ifdef CONFIG_TX_CSUM_OFFLOAD
+	u8	hw_csum;
+#endif
+	u8	key_idx;
+	u8	qos_en;
+	u8	ht_en;
+	u8	raid;/* rate adpative id */
+	u8	bwmode;
+	u8	ch_offset;/* PRIME_CHNL_OFFSET */
+	u8	sgi;/* short GI */
+	u8	ampdu_en;/* tx ampdu enable */
+	u8	ampdu_spacing; /* ampdu_min_spacing for peer sta's rx */
+	u8	amsdu;
+	u8	amsdu_ampdu_en;/* tx amsdu in ampdu enable */
+	u8	mdata;/* more data bit */
+	u8	pctrl;/* per packet txdesc control enable */
+	u8	triggered;/* for ap mode handling Power Saving sta */
+	u8	qsel;
+	u8	order;/* order bit */
+	u8	eosp;
+	u8	rate;
+	u8	intel_proxim;
+	u8	retry_ctrl;
+	u8   mbssid;
+	u8	ldpc;
+	u8	stbc;
+#ifdef CONFIG_WMMPS_STA
+	u8	trigger_frame;
+#endif /* CONFIG_WMMPS_STA */
+	
+	struct sta_info *psta;
+
+	u8 rtsen;
+	u8 cts2self;
+	union Keytype	dot11tkiptxmickey;
+	/* union Keytype	dot11tkiprxmickey; */
+	union Keytype	dot118021x_UncstKey;
+
+#ifdef CONFIG_TDLS
+	u8 direct_link;
+	struct sta_info *ptdls_sta;
+#endif /* CONFIG_TDLS */
+	u8 key_type;
+
+	u8 icmp_pkt;
+
+#ifdef CONFIG_BEAMFORMING
+	u16 txbf_p_aid;/*beamforming Partial_AID*/
+	u16 txbf_g_id;/*beamforming Group ID*/
+
+	/*
+	 * 2'b00: Unicast NDPA
+	 * 2'b01: Broadcast NDPA
+	 * 2'b10: Beamforming Report Poll
+	 * 2'b11: Final Beamforming Report Poll
+	 */
+	u8 bf_pkt_type;
+#endif
+
+};
+#endif
+
+#ifdef CONFIG_RTW_MESH
+#define XATTRIB_GET_MCTRL_LEN(xattrib) ((xattrib)->meshctrl_len)
+#else
+#define XATTRIB_GET_MCTRL_LEN(xattrib) 0
+#endif
+
+#ifdef CONFIG_TX_AMSDU
+enum {
+	RTW_AMSDU_TIMER_UNSET = 0,
+	RTW_AMSDU_TIMER_SETTING,
+	RTW_AMSDU_TIMER_TIMEOUT,
+};
+#endif
+
+#define WLANHDR_OFFSET	64
+
+#define NULL_FRAMETAG		(0x0)
+#define DATA_FRAMETAG		0x01
+#define L2_FRAMETAG		0x02
+#define MGNT_FRAMETAG		0x03
+#define AMSDU_FRAMETAG	0x04
+
+#define EII_FRAMETAG		0x05
+#define IEEE8023_FRAMETAG  0x06
+
+#define MP_FRAMETAG		0x07
+
+#define TXAGG_FRAMETAG	0x08
+
+enum {
+	XMITBUF_DATA = 0,
+	XMITBUF_MGNT = 1,
+	XMITBUF_CMD = 2,
+};
+
+bool rtw_xmit_ac_blocked(_adapter *adapter);
+
+struct  submit_ctx {
+	systime submit_time; /* */
+	u32 timeout_ms; /* <0: not synchronous, 0: wait forever, >0: up to ms waiting */
+	int status; /* status for operation */
+#ifdef PLATFORM_LINUX
+	struct completion done;
+#endif
+};
+
+enum {
+	RTW_SCTX_SUBMITTED = -1,
+	RTW_SCTX_DONE_SUCCESS = 0,
+	RTW_SCTX_DONE_UNKNOWN,
+	RTW_SCTX_DONE_TIMEOUT,
+	RTW_SCTX_DONE_BUF_ALLOC,
+	RTW_SCTX_DONE_BUF_FREE,
+	RTW_SCTX_DONE_WRITE_PORT_ERR,
+	RTW_SCTX_DONE_TX_DESC_NA,
+	RTW_SCTX_DONE_TX_DENY,
+	RTW_SCTX_DONE_CCX_PKT_FAIL,
+	RTW_SCTX_DONE_DRV_STOP,
+	RTW_SCTX_DONE_DEV_REMOVE,
+	RTW_SCTX_DONE_CMD_ERROR,
+	RTW_SCTX_DONE_CMD_DROP,
+	RTX_SCTX_CSTR_WAIT_RPT2,
+};
+
+
+void rtw_sctx_init(struct submit_ctx *sctx, int timeout_ms);
+int rtw_sctx_wait(struct submit_ctx *sctx, const char *msg);
+void rtw_sctx_done_err(struct submit_ctx **sctx, int status);
+void rtw_sctx_done(struct submit_ctx **sctx);
+
+struct xmit_buf {
+	_list	list;
+
+	_adapter *padapter;
+
+	u8 *pallocated_buf;
+
+	u8 *pbuf;
+
+	void *priv_data;
+
+	u16 buf_tag; /* 0: Normal xmitbuf, 1: extension xmitbuf, 2:cmd xmitbuf */
+	u16 flags;
+	u32 alloc_sz;
+
+	u32  len;
+
+	struct submit_ctx *sctx;
+
+#ifdef CONFIG_USB_HCI
+
+	/* u32 sz[8]; */
+	u32	ff_hwaddr;
+#ifdef RTW_HALMAC
+	u8 bulkout_id; /* for halmac */
+#endif /* RTW_HALMAC */
+
+#if defined(PLATFORM_OS_XP) || defined(PLATFORM_LINUX) || defined(PLATFORM_FREEBSD)
+	PURB	pxmit_urb[8];
+	dma_addr_t dma_transfer_addr;	/* (in) dma addr for transfer_buffer */
+#endif
+
+#ifdef PLATFORM_OS_XP
+	PIRP		pxmit_irp[8];
+#endif
+
+#ifdef PLATFORM_OS_CE
+	USB_TRANSFER	usb_transfer_write_port;
+#endif
+
+	u8 bpending[8];
+
+	sint last[8];
+
+#endif
+
+#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
+	u8 *phead;
+	u8 *pdata;
+	u8 *ptail;
+	u8 *pend;
+	u32 ff_hwaddr;
+	u8	pg_num;
+	u8	agg_num;
+#ifdef PLATFORM_OS_XP
+	PMDL pxmitbuf_mdl;
+	PIRP  pxmitbuf_irp;
+	PSDBUS_REQUEST_PACKET pxmitbuf_sdrp;
+#endif
+#endif
+
+#ifdef CONFIG_PCI_HCI
+#ifdef CONFIG_TRX_BD_ARCH
+	/*struct tx_buf_desc *buf_desc;*/
+#else
+	struct tx_desc *desc;
+#endif
+#endif
+
+#if defined(DBG_XMIT_BUF) || defined(DBG_XMIT_BUF_EXT)
+	u8 no;
+#endif
+
+};
+
+
+struct xmit_frame {
+	_list	list;
+
+	struct pkt_attrib attrib;
+
+	_pkt *pkt;
+
+	int	frame_tag;
+
+	_adapter *padapter;
+
+	u8	*buf_addr;
+
+	struct xmit_buf *pxmitbuf;
+
+#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
+	u8	pg_num;
+	u8	agg_num;
+#endif
+
+#ifdef CONFIG_USB_HCI
+#ifdef CONFIG_USB_TX_AGGREGATION
+	u8	agg_num;
+#endif
+	s8	pkt_offset;
+#endif
+
+#ifdef CONFIG_XMIT_ACK
+	u8 ack_report;
+#endif
+
+	u8 *alloc_addr; /* the actual address this xmitframe allocated */
+	u8 ext_tag; /* 0:data, 1:mgmt */
+
+};
+
+struct tx_servq {
+	_list	tx_pending;
+	_queue	sta_pending;
+	int qcnt;
+};
+
+
+struct sta_xmit_priv {
+	_lock	lock;
+	sint	option;
+	sint	apsd_setting;	/* When bit mask is on, the associated edca queue supports APSD. */
+
+
+	/* struct tx_servq blk_q[MAX_NUMBLKS]; */
+	struct tx_servq	be_q;			/* priority == 0,3 */
+	struct tx_servq	bk_q;			/* priority == 1,2 */
+	struct tx_servq	vi_q;			/* priority == 4,5 */
+	struct tx_servq	vo_q;			/* priority == 6,7 */
+	_list	legacy_dz;
+	_list  apsd;
+
+	u16 txseq_tid[16];
+
+	/* uint	sta_tx_bytes; */
+	/* u64	sta_tx_pkts; */
+	/* uint	sta_tx_fail; */
+
+
+};
+
+
+struct	hw_txqueue	{
+	volatile sint	head;
+	volatile sint	tail;
+	volatile sint 	free_sz;	/* in units of 64 bytes */
+	volatile sint      free_cmdsz;
+	volatile sint	 txsz[8];
+	uint	ff_hwaddr;
+	uint	cmd_hwaddr;
+	sint	ac_tag;
+};
+
+struct agg_pkt_info {
+	u16 offset;
+	u16 pkt_len;
+};
+
+enum cmdbuf_type {
+	CMDBUF_BEACON = 0x00,
+	CMDBUF_RSVD,
+	CMDBUF_MAX
+};
+
+u8 rtw_get_hwseq_no(_adapter *padapter);
+
+struct	xmit_priv	{
+
+	_lock	lock;
+
+	_sema	xmit_sema;
+
+	/* _queue	blk_strms[MAX_NUMBLKS]; */
+	_queue	be_pending;
+	_queue	bk_pending;
+	_queue	vi_pending;
+	_queue	vo_pending;
+	_queue	bm_pending;
+
+	/* _queue	legacy_dz_queue; */
+	/* _queue	apsd_queue; */
+
+	u8 *pallocated_frame_buf;
+	u8 *pxmit_frame_buf;
+	uint free_xmitframe_cnt;
+	_queue	free_xmit_queue;
+
+	/* uint mapping_addr; */
+	/* uint pkt_sz; */
+
+	u8 *xframe_ext_alloc_addr;
+	u8 *xframe_ext;
+	uint free_xframe_ext_cnt;
+	_queue free_xframe_ext_queue;
+
+	/* struct	hw_txqueue	be_txqueue; */
+	/* struct	hw_txqueue	bk_txqueue; */
+	/* struct	hw_txqueue	vi_txqueue; */
+	/* struct	hw_txqueue	vo_txqueue; */
+	/* struct	hw_txqueue	bmc_txqueue; */
+
+	uint	frag_len;
+
+	_adapter	*adapter;
+
+	u8   vcs_setting;
+	u8	vcs;
+	u8	vcs_type;
+	/* u16  rts_thresh; */
+
+	u64	tx_bytes;
+	u64	tx_pkts;
+	u64	tx_drop;
+	u64	last_tx_pkts;
+
+	struct hw_xmit *hwxmits;
+	u8	hwxmit_entry;
+
+	u8	wmm_para_seq[4];/* sequence for wmm ac parameter strength from large to small. it's value is 0->vo, 1->vi, 2->be, 3->bk. */
+
+#ifdef CONFIG_USB_HCI
+	_sema	tx_retevt;/* all tx return event; */
+	u8		txirp_cnt;
+
+#ifdef PLATFORM_OS_CE
+	USB_TRANSFER	usb_transfer_write_port;
+	/*	USB_TRANSFER	usb_transfer_write_mem; */
+#endif
+#ifdef PLATFORM_LINUX
+	struct tasklet_struct xmit_tasklet;
+#endif
+#ifdef PLATFORM_FREEBSD
+	struct task xmit_tasklet;
+#endif
+	/* per AC pending irp */
+	int beq_cnt;
+	int bkq_cnt;
+	int viq_cnt;
+	int voq_cnt;
+
+#endif
+
+#ifdef CONFIG_PCI_HCI
+	/* Tx */
+	struct rtw_tx_ring	tx_ring[PCI_MAX_TX_QUEUE_COUNT];
+	int	txringcount[PCI_MAX_TX_QUEUE_COUNT];
+	u8 	beaconDMAing;		/* flag of indicating beacon is transmiting to HW by DMA */
+#ifdef PLATFORM_LINUX
+	struct tasklet_struct xmit_tasklet;
+#endif
+#endif
+
+#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
+#ifdef CONFIG_SDIO_TX_TASKLET
+#ifdef PLATFORM_LINUX
+	struct tasklet_struct xmit_tasklet;
+#endif /* PLATFORM_LINUX */
+#else
+	_thread_hdl_	SdioXmitThread;
+	_sema		SdioXmitSema;
+#endif /* CONFIG_SDIO_TX_TASKLET */
+#endif /* CONFIG_SDIO_HCI */
+
+	_queue free_xmitbuf_queue;
+	_queue pending_xmitbuf_queue;
+	u8 *pallocated_xmitbuf;
+	u8 *pxmitbuf;
+	uint free_xmitbuf_cnt;
+
+	_queue free_xmit_extbuf_queue;
+	u8 *pallocated_xmit_extbuf;
+	u8 *pxmit_extbuf;
+	uint free_xmit_extbuf_cnt;
+
+	struct xmit_buf	pcmd_xmitbuf[CMDBUF_MAX];
+	u8   hw_ssn_seq_no;/* mapping to REG_HW_SEQ 0,1,2,3 */
+	u16	nqos_ssn;
+#ifdef CONFIG_TX_EARLY_MODE
+
+#ifdef CONFIG_SDIO_HCI
+#define MAX_AGG_PKT_NUM 20
+#else
+#define MAX_AGG_PKT_NUM 256 /* Max tx ampdu coounts		 */
+#endif
+
+	struct agg_pkt_info agg_pkt[MAX_AGG_PKT_NUM];
+#endif
+
+#ifdef CONFIG_XMIT_ACK
+	int	ack_tx;
+	_mutex ack_tx_mutex;
+	struct submit_ctx ack_tx_ops;
+	u8 seq_no;
+#endif
+
+#ifdef CONFIG_TX_AMSDU
+	_timer amsdu_vo_timer;
+	u8 amsdu_vo_timeout;
+
+	_timer amsdu_vi_timer;
+	u8 amsdu_vi_timeout;
+
+	_timer amsdu_be_timer;
+	u8 amsdu_be_timeout;
+
+	_timer amsdu_bk_timer;
+	u8 amsdu_bk_timeout;
+
+	u32 amsdu_debug_set_timer;
+	u32 amsdu_debug_timeout;
+	u32 amsdu_debug_coalesce_one;
+	u32 amsdu_debug_coalesce_two;
+
+#endif
+#ifdef DBG_TXBD_DESC_DUMP
+	BOOLEAN	 dump_txbd_desc;
+#endif
+	_lock lock_sctx;
+
+};
+
+extern struct xmit_frame *__rtw_alloc_cmdxmitframe(struct xmit_priv *pxmitpriv,
+		enum cmdbuf_type buf_type);
+#define rtw_alloc_cmdxmitframe(p) __rtw_alloc_cmdxmitframe(p, CMDBUF_RSVD)
+#if defined(CONFIG_RTL8192E) && defined(CONFIG_PCI_HCI)
+extern struct xmit_frame *__rtw_alloc_cmdxmitframe_8192ee(struct xmit_priv *pxmitpriv,
+		enum cmdbuf_type buf_type);
+#define rtw_alloc_bcnxmitframe(p) __rtw_alloc_cmdxmitframe_8192ee(p, CMDBUF_BEACON)
+#elif defined(CONFIG_RTL8822B) && defined(CONFIG_PCI_HCI)
+extern struct xmit_frame *__rtw_alloc_cmdxmitframe_8822be(struct xmit_priv *pxmitpriv,
+		enum cmdbuf_type buf_type);
+#define rtw_alloc_bcnxmitframe(p) __rtw_alloc_cmdxmitframe_8822be(p, CMDBUF_BEACON)
+#elif defined(CONFIG_RTL8821C) && defined(CONFIG_PCI_HCI)
+extern struct xmit_frame *__rtw_alloc_cmdxmitframe_8821ce(struct xmit_priv *pxmitpriv,
+		enum cmdbuf_type buf_type);
+#define rtw_alloc_bcnxmitframe(p) __rtw_alloc_cmdxmitframe_8821ce(p, CMDBUF_BEACON)
+#else
+#define rtw_alloc_bcnxmitframe(p) __rtw_alloc_cmdxmitframe(p, CMDBUF_BEACON)
+#endif
+
+extern struct xmit_buf *rtw_alloc_xmitbuf_ext(struct xmit_priv *pxmitpriv);
+extern s32 rtw_free_xmitbuf_ext(struct xmit_priv *pxmitpriv, struct xmit_buf *pxmitbuf);
+
+extern struct xmit_buf *rtw_alloc_xmitbuf(struct xmit_priv *pxmitpriv);
+extern s32 rtw_free_xmitbuf(struct xmit_priv *pxmitpriv, struct xmit_buf *pxmitbuf);
+
+void rtw_count_tx_stats(_adapter *padapter, struct xmit_frame *pxmitframe, int sz);
+extern void rtw_update_protection(_adapter *padapter, u8 *ie, uint ie_len);
+
+#ifdef CONFIG_WMMPS_STA
+static void update_attrib_trigger_frame_info(_adapter *padapter, struct pkt_attrib *pattrib);
+#endif /* CONFIG_WMMPS_STA */
+
+extern s32 rtw_make_wlanhdr(_adapter *padapter, u8 *hdr, struct pkt_attrib *pattrib);
+extern s32 rtw_put_snap(u8 *data, u16 h_proto);
+
+extern struct xmit_frame *rtw_alloc_xmitframe(struct xmit_priv *pxmitpriv);
+struct xmit_frame *rtw_alloc_xmitframe_ext(struct xmit_priv *pxmitpriv);
+struct xmit_frame *rtw_alloc_xmitframe_once(struct xmit_priv *pxmitpriv);
+extern s32 rtw_free_xmitframe(struct xmit_priv *pxmitpriv, struct xmit_frame *pxmitframe);
+extern void rtw_free_xmitframe_queue(struct xmit_priv *pxmitpriv, _queue *pframequeue);
+struct tx_servq *rtw_get_sta_pending(_adapter *padapter, struct sta_info *psta, sint up, u8 *ac);
+extern s32 rtw_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe);
+extern struct xmit_frame *rtw_dequeue_xframe(struct xmit_priv *pxmitpriv, struct hw_xmit *phwxmit_i, sint entry);
+
+extern s32 rtw_xmit_classifier(_adapter *padapter, struct xmit_frame *pxmitframe);
+extern u32 rtw_calculate_wlan_pkt_size_by_attribue(struct pkt_attrib *pattrib);
+#define rtw_wlan_pkt_size(f) rtw_calculate_wlan_pkt_size_by_attribue(&f->attrib)
+extern s32 rtw_xmitframe_coalesce(_adapter *padapter, _pkt *pkt, struct xmit_frame *pxmitframe);
+#if defined(CONFIG_IEEE80211W) || defined(CONFIG_RTW_MESH)
+extern s32 rtw_mgmt_xmitframe_coalesce(_adapter *padapter, _pkt *pkt, struct xmit_frame *pxmitframe);
+#endif
+#ifdef CONFIG_TDLS
+extern struct tdls_txmgmt *ptxmgmt;
+s32 rtw_xmit_tdls_coalesce(_adapter *padapter, struct xmit_frame *pxmitframe, struct tdls_txmgmt *ptxmgmt);
+s32 update_tdls_attrib(_adapter *padapter, struct pkt_attrib *pattrib);
+#endif
+s32 _rtw_init_hw_txqueue(struct hw_txqueue *phw_txqueue, u8 ac_tag);
+void _rtw_init_sta_xmit_priv(struct sta_xmit_priv *psta_xmitpriv);
+
+
+s32 rtw_txframes_pending(_adapter *padapter);
+s32 rtw_txframes_sta_ac_pending(_adapter *padapter, struct pkt_attrib *pattrib);
+void rtw_init_hwxmits(struct hw_xmit *phwxmit, sint entry);
+
+
+s32 _rtw_init_xmit_priv(struct xmit_priv *pxmitpriv, _adapter *padapter);
+void _rtw_free_xmit_priv(struct xmit_priv *pxmitpriv);
+
+
+void rtw_alloc_hwxmits(_adapter *padapter);
+void rtw_free_hwxmits(_adapter *padapter);
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 24))
+s32 rtw_monitor_xmit_entry(struct sk_buff *skb, struct net_device *ndev);
+#endif
+s32 rtw_xmit_posthandle(_adapter *padapter, struct xmit_frame *pxmitframe, _pkt *pkt);
+s32 rtw_xmit(_adapter *padapter, _pkt **pkt);
+bool xmitframe_hiq_filter(struct xmit_frame *xmitframe);
+#if defined(CONFIG_AP_MODE) || defined(CONFIG_TDLS)
+sint xmitframe_enqueue_for_sleeping_sta(_adapter *padapter, struct xmit_frame *pxmitframe);
+void stop_sta_xmit(_adapter *padapter, struct sta_info *psta);
+void wakeup_sta_to_xmit(_adapter *padapter, struct sta_info *psta);
+void xmit_delivery_enabled_frames(_adapter *padapter, struct sta_info *psta);
+#endif
+
+u8 rtw_get_tx_bw_mode(_adapter *adapter, struct sta_info *sta);
+
+void rtw_get_adapter_tx_rate_bmp_by_bw(_adapter *adapter, u8 bw, u16 *r_bmp_cck_ofdm, u32 *r_bmp_ht, u32 *r_bmp_vht);
+void rtw_update_tx_rate_bmp(struct dvobj_priv *dvobj);
+u16 rtw_get_tx_rate_bmp_cck_ofdm(struct dvobj_priv *dvobj);
+u32 rtw_get_tx_rate_bmp_ht_by_bw(struct dvobj_priv *dvobj, u8 bw);
+u32 rtw_get_tx_rate_bmp_vht_by_bw(struct dvobj_priv *dvobj, u8 bw);
+u8 rtw_get_tx_bw_bmp_of_ht_rate(struct dvobj_priv *dvobj, u8 rate, u8 max_bw);
+u8 rtw_get_tx_bw_bmp_of_vht_rate(struct dvobj_priv *dvobj, u8 rate, u8 max_bw);
+
+u8 query_ra_short_GI(struct sta_info *psta, u8 bw);
+
+u8	qos_acm(u8 acm_mask, u8 priority);
+
+#ifdef CONFIG_XMIT_THREAD_MODE
+void	enqueue_pending_xmitbuf(struct xmit_priv *pxmitpriv, struct xmit_buf *pxmitbuf);
+void enqueue_pending_xmitbuf_to_head(struct xmit_priv *pxmitpriv, struct xmit_buf *pxmitbuf);
+struct xmit_buf	*dequeue_pending_xmitbuf(struct xmit_priv *pxmitpriv);
+struct xmit_buf	*select_and_dequeue_pending_xmitbuf(_adapter *padapter);
+sint	check_pending_xmitbuf(struct xmit_priv *pxmitpriv);
+thread_return	rtw_xmit_thread(thread_context context);
+#endif
+
+#ifdef CONFIG_TX_AMSDU
+extern void rtw_amsdu_vo_timeout_handler(void *FunctionContext);
+extern void rtw_amsdu_vi_timeout_handler(void *FunctionContext);
+extern void rtw_amsdu_be_timeout_handler(void *FunctionContext);
+extern void rtw_amsdu_bk_timeout_handler(void *FunctionContext);
+
+extern u8 rtw_amsdu_get_timer_status(_adapter *padapter, u8 priority);
+extern void rtw_amsdu_set_timer_status(_adapter *padapter, u8 priority, u8 status);
+extern void rtw_amsdu_set_timer(_adapter *padapter, u8 priority);
+extern void rtw_amsdu_cancel_timer(_adapter *padapter, u8 priority);
+
+extern s32 rtw_xmitframe_coalesce_amsdu(_adapter *padapter, struct xmit_frame *pxmitframe, struct xmit_frame *pxmitframe_queue);	
+extern s32 check_amsdu(struct xmit_frame *pxmitframe);
+extern s32 check_amsdu_tx_support(_adapter *padapter);
+extern struct xmit_frame *rtw_get_xframe(struct xmit_priv *pxmitpriv, int *num_frame);
+#endif
+
+#ifdef DBG_TXBD_DESC_DUMP
+void rtw_tx_desc_backup(_adapter *padapter, struct xmit_frame *pxmitframe, u8 desc_size, u8 hwq);
+void rtw_tx_desc_backup_reset(void);
+u8 rtw_get_tx_desc_backup(_adapter *padapter, u8 hwq, struct rtw_tx_desc_backup **pbak);
+#endif
+
+u32	rtw_get_ff_hwaddr(struct xmit_frame	*pxmitframe);
+
+#ifdef CONFIG_XMIT_ACK
+int rtw_ack_tx_wait(struct xmit_priv *pxmitpriv, u32 timeout_ms);
+void rtw_ack_tx_done(struct xmit_priv *pxmitpriv, int status);
+#endif /* CONFIG_XMIT_ACK */
+
+enum XMIT_BLOCK_REASON {
+	XMIT_BLOCK_NONE = 0,
+	XMIT_BLOCK_REDLMEM = BIT0, /*LPS-PG*/
+	XMIT_BLOCK_SUSPEND = BIT1, /*WOW*/
+	XMIT_BLOCK_MAX = 0xFF,
+};
+void rtw_init_xmit_block(_adapter *padapter);
+void rtw_deinit_xmit_block(_adapter *padapter);
+
+#ifdef DBG_XMIT_BLOCK
+void dump_xmit_block(void *sel, _adapter *padapter);
+#endif
+void rtw_set_xmit_block(_adapter *padapter, enum XMIT_BLOCK_REASON reason);
+void rtw_clr_xmit_block(_adapter *padapter, enum XMIT_BLOCK_REASON reason);
+bool rtw_is_xmit_blocked(_adapter *padapter);
+
+/* include after declaring struct xmit_buf, in order to avoid warning */
+#include <xmit_osdep.h>
+
+#endif /* _RTL871X_XMIT_H_ */
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/include/sdio_hal.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/sdio_hal.h
--- linux-5.6.3/3rdparty/rtl8821ce/include/sdio_hal.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/sdio_hal.h	2020-04-10 16:35:06.852661748 +0300
@@ -0,0 +1,57 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#ifndef __SDIO_HAL_H__
+#define __SDIO_HAL_H__
+
+void sd_int_dpc(PADAPTER padapter);
+u8 rtw_set_hal_ops(_adapter *padapter);
+
+#ifdef CONFIG_RTL8188E
+void rtl8188es_set_hal_ops(PADAPTER padapter);
+#endif
+
+#ifdef CONFIG_RTL8723B
+void rtl8723bs_set_hal_ops(PADAPTER padapter);
+#endif
+
+#ifdef CONFIG_RTL8821A
+void rtl8821as_set_hal_ops(PADAPTER padapter);
+#endif
+
+#ifdef CONFIG_RTL8192E
+void rtl8192es_set_hal_ops(PADAPTER padapter);
+#endif
+
+#ifdef CONFIG_RTL8703B
+void rtl8703bs_set_hal_ops(PADAPTER padapter);
+#endif
+
+#ifdef CONFIG_RTL8723D
+void rtl8723ds_set_hal_ops(PADAPTER padapter);
+#endif
+
+#ifdef CONFIG_RTL8188F
+void rtl8188fs_set_hal_ops(PADAPTER padapter);
+#endif
+
+#ifdef CONFIG_RTL8188GTV
+void rtl8188gtvs_set_hal_ops(PADAPTER padapter);
+#endif
+
+#ifdef CONFIG_RTL8192F
+void rtl8192fs_set_hal_ops(PADAPTER padapter);
+#endif
+
+#endif /* __SDIO_HAL_H__ */
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/include/sdio_ops_ce.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/sdio_ops_ce.h
--- linux-5.6.3/3rdparty/rtl8821ce/include/sdio_ops_ce.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/sdio_ops_ce.h	2020-04-10 16:35:06.852661748 +0300
@@ -0,0 +1,49 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#ifndef _SDIO_OPS_WINCE_H_
+#define _SDIO_OPS_WINCE_H_
+
+#include <drv_conf.h>
+#include <osdep_service.h>
+#include <drv_types.h>
+#include <osdep_intf.h>
+
+
+#ifdef PLATFORM_OS_CE
+
+
+extern u8 sdbus_cmd52r_ce(struct intf_priv *pintfpriv, u32 addr);
+
+
+extern void sdbus_cmd52w_ce(struct intf_priv *pintfpriv, u32 addr, u8 val8);
+
+
+uint sdbus_read_blocks_to_membuf_ce(struct intf_priv *pintfpriv, u32 addr, u32 cnt, u8 *pbuf);
+
+extern uint sdbus_read_bytes_to_membuf_ce(struct intf_priv *pintfpriv, u32 addr, u32 cnt, u8 *pbuf);
+
+
+extern uint sdbus_write_blocks_from_membuf_ce(struct intf_priv *pintfpriv, u32 addr, u32 cnt, u8 *pbuf, u8 async);
+
+extern uint sdbus_write_bytes_from_membuf_ce(struct intf_priv *pintfpriv, u32 addr, u32 cnt, u8 *pbuf);
+extern u8 sdbus_func1cmd52r_ce(struct intf_priv *pintfpriv, u32 addr);
+extern void sdbus_func1cmd52w_ce(struct intf_priv *pintfpriv, u32 addr, u8 val8);
+extern uint sdbus_read_reg(struct intf_priv *pintfpriv, u32 addr, u32 cnt, void *pdata);
+extern uint sdbus_write_reg(struct intf_priv *pintfpriv, u32 addr, u32 cnt, void *pdata);
+extern void sdio_read_int(_adapter *padapter, u32 addr, u8 sz, void *pdata);
+
+#endif
+
+#endif
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/include/sdio_ops.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/sdio_ops.h
--- linux-5.6.3/3rdparty/rtl8821ce/include/sdio_ops.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/sdio_ops.h	2020-04-10 16:35:06.852661748 +0300
@@ -0,0 +1,224 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#ifndef __SDIO_OPS_H__
+#define __SDIO_OPS_H__
+
+
+/* Follow mac team suggestion, default I/O fail return value is 0xFF */
+#define SDIO_ERR_VAL8	0xFF
+#define SDIO_ERR_VAL16	0xFFFF
+#define SDIO_ERR_VAL32	0xFFFFFFFF
+
+#ifdef PLATFORM_LINUX
+#include <sdio_ops_linux.h>
+#endif
+
+#ifdef PLATFORM_WINDOWS
+
+#ifdef PLATFORM_OS_XP
+#include <sdio_ops_xp.h>
+struct async_context {
+	PMDL pmdl;
+	PSDBUS_REQUEST_PACKET sdrp;
+	unsigned char *r_buf;
+	unsigned char *padapter;
+};
+#endif
+
+#ifdef PLATFORM_OS_CE
+#include <sdio_ops_ce.h>
+#endif
+
+#endif /* PLATFORM_WINDOWS */
+
+
+extern void sdio_set_intf_ops(_adapter *padapter, struct _io_ops *pops);
+void dump_sdio_card_info(void *sel, struct dvobj_priv *dvobj);
+
+u32 sdio_init(struct dvobj_priv *dvobj);
+void sdio_deinit(struct dvobj_priv *dvobj);
+int sdio_alloc_irq(struct dvobj_priv *dvobj);
+void sdio_free_irq(struct dvobj_priv *dvobj);
+
+#if 0
+extern void sdio_func1cmd52_read(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *rmem);
+extern void sdio_func1cmd52_write(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *wmem);
+#endif
+extern u8 SdioLocalCmd52Read1Byte(PADAPTER padapter, u32 addr);
+extern void SdioLocalCmd52Write1Byte(PADAPTER padapter, u32 addr, u8 v);
+extern s32 _sdio_local_read(PADAPTER padapter, u32 addr, u32 cnt, u8 *pbuf);
+extern s32 sdio_local_read(PADAPTER padapter, u32 addr, u32 cnt, u8 *pbuf);
+extern s32 _sdio_local_write(PADAPTER padapter, u32 addr, u32 cnt, u8 *pbuf);
+extern s32 sdio_local_write(PADAPTER padapter, u32 addr, u32 cnt, u8 *pbuf);
+
+u32 _sdio_read32(PADAPTER padapter, u32 addr);
+s32 _sdio_write32(PADAPTER padapter, u32 addr, u32 val);
+
+extern void sd_int_hdl(PADAPTER padapter);
+extern u8 CheckIPSStatus(PADAPTER padapter);
+
+#ifdef CONFIG_RTL8188E
+extern void InitInterrupt8188ESdio(PADAPTER padapter);
+extern void EnableInterrupt8188ESdio(PADAPTER padapter);
+extern void DisableInterrupt8188ESdio(PADAPTER padapter);
+extern void UpdateInterruptMask8188ESdio(PADAPTER padapter, u32 AddMSR, u32 RemoveMSR);
+extern u8 HalQueryTxBufferStatus8189ESdio(PADAPTER padapter);
+extern u8 HalQueryTxOQTBufferStatus8189ESdio(PADAPTER padapter);
+extern void ClearInterrupt8188ESdio(PADAPTER padapter);
+#endif /* CONFIG_RTL8188E */
+
+#ifdef CONFIG_RTL8821A
+extern void InitInterrupt8821AS(PADAPTER padapter);
+extern void EnableInterrupt8821AS(PADAPTER padapter);
+extern void DisableInterrupt8821AS(PADAPTER padapter);
+extern u8 HalQueryTxBufferStatus8821AS(PADAPTER padapter);
+extern u8 HalQueryTxOQTBufferStatus8821ASdio(PADAPTER padapter);
+#if defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN)
+void ClearInterrupt8821AS(PADAPTER padapter);
+#endif /* defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN) */
+#endif /* CONFIG_RTL8821A */
+
+#if defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN)
+#if defined(CONFIG_RTL8821C) || defined(CONFIG_RTL8822B)
+u8 rtw_hal_enable_cpwm2(_adapter *adapter);
+#endif
+extern u8 RecvOnePkt(PADAPTER padapter);
+#endif /* CONFIG_WOWLAN */
+#ifdef CONFIG_RTL8723B
+extern void InitInterrupt8723BSdio(PADAPTER padapter);
+extern void InitSysInterrupt8723BSdio(PADAPTER padapter);
+extern void EnableInterrupt8723BSdio(PADAPTER padapter);
+extern void DisableInterrupt8723BSdio(PADAPTER padapter);
+extern u8 HalQueryTxBufferStatus8723BSdio(PADAPTER padapter);
+extern u8 HalQueryTxOQTBufferStatus8723BSdio(PADAPTER padapter);
+#if defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN)
+extern void DisableInterruptButCpwm28723BSdio(PADAPTER padapter);
+extern void ClearInterrupt8723BSdio(PADAPTER padapter);
+#endif /* CONFIG_WOWLAN */
+#endif
+
+
+#ifdef CONFIG_RTL8192E
+extern void InitInterrupt8192ESdio(PADAPTER padapter);
+extern void EnableInterrupt8192ESdio(PADAPTER padapter);
+extern void DisableInterrupt8192ESdio(PADAPTER padapter);
+extern void UpdateInterruptMask8192ESdio(PADAPTER padapter, u32 AddMSR, u32 RemoveMSR);
+extern u8 HalQueryTxBufferStatus8192ESdio(PADAPTER padapter);
+extern u8 HalQueryTxOQTBufferStatus8192ESdio(PADAPTER padapter);
+extern void ClearInterrupt8192ESdio(PADAPTER padapter);
+#endif /* CONFIG_RTL8192E */
+
+#ifdef CONFIG_RTL8703B
+extern void InitInterrupt8703BSdio(PADAPTER padapter);
+extern void InitSysInterrupt8703BSdio(PADAPTER padapter);
+extern void EnableInterrupt8703BSdio(PADAPTER padapter);
+extern void DisableInterrupt8703BSdio(PADAPTER padapter);
+extern u8 HalQueryTxBufferStatus8703BSdio(PADAPTER padapter);
+extern u8 HalQueryTxOQTBufferStatus8703BSdio(PADAPTER padapter);
+#if defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN)
+extern void DisableInterruptButCpwm28703BSdio(PADAPTER padapter);
+extern void ClearInterrupt8703BSdio(PADAPTER padapter);
+#endif /* CONFIG_WOWLAN */
+#endif
+
+#ifdef CONFIG_RTL8723D
+extern void InitInterrupt8723DSdio(PADAPTER padapter);
+extern void InitSysInterrupt8723DSdio(PADAPTER padapter);
+extern void EnableInterrupt8723DSdio(PADAPTER padapter);
+extern void DisableInterrupt8723DSdio(PADAPTER padapter);
+extern u8 HalQueryTxBufferStatus8723DSdio(PADAPTER padapter);
+extern u8 HalQueryTxOQTBufferStatus8723DSdio(PADAPTER padapter);
+#if defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN)
+extern void DisableInterruptButCpwm28723dSdio(PADAPTER padapter);
+extern void ClearInterrupt8723DSdio(PADAPTER padapter);
+#endif /* CONFIG_WOWLAN */
+#endif
+
+#ifdef CONFIG_RTL8192F
+extern void InitInterrupt8192FSdio(PADAPTER padapter);
+extern void InitSysInterrupt8192FSdio(PADAPTER padapter);
+extern void EnableInterrupt8192FSdio(PADAPTER padapter);
+extern void DisableInterrupt8192FSdio(PADAPTER padapter);
+extern void UpdateInterruptMask8192FSdio(PADAPTER padapter, u32 AddMSR, u32 RemoveMSR);
+extern u8 HalQueryTxBufferStatus8192FSdio(PADAPTER padapter);
+extern u8 HalQueryTxOQTBufferStatus8192FSdio(PADAPTER padapter);
+#if defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN)
+extern void DisableInterruptButCpwm2192fSdio(PADAPTER padapter);
+extern void ClearInterrupt8192FSdio(PADAPTER padapter);
+#endif /* CONFIG_WOWLAN */
+#endif
+
+#ifdef CONFIG_RTL8188F
+extern void InitInterrupt8188FSdio(PADAPTER padapter);
+extern void InitSysInterrupt8188FSdio(PADAPTER padapter);
+extern void EnableInterrupt8188FSdio(PADAPTER padapter);
+extern void DisableInterrupt8188FSdio(PADAPTER padapter);
+extern u8 HalQueryTxBufferStatus8188FSdio(PADAPTER padapter);
+extern u8 HalQueryTxOQTBufferStatus8188FSdio(PADAPTER padapter);
+#if defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN)
+extern void DisableInterruptButCpwm28188FSdio(PADAPTER padapter);
+extern void ClearInterrupt8188FSdio(PADAPTER padapter);
+#endif /* defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN) */
+#endif
+
+#ifdef CONFIG_RTL8188GTV
+extern void InitInterrupt8188GTVSdio(PADAPTER padapter);
+extern void InitSysInterrupt8188GTVSdio(PADAPTER padapter);
+extern void EnableInterrupt8188GTVSdio(PADAPTER padapter);
+extern void DisableInterrupt8188GTVSdio(PADAPTER padapter);
+extern u8 HalQueryTxBufferStatus8188GTVSdio(PADAPTER padapter);
+extern u8 HalQueryTxOQTBufferStatus8188GTVSdio(PADAPTER padapter);
+#if defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN)
+extern void DisableInterruptButCpwm28188GTVSdio(PADAPTER padapter);
+extern void ClearInterrupt8188GTVSdio(PADAPTER padapter);
+#endif /* defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN) */
+#endif
+
+/**
+ * rtw_sdio_get_block_size() - Get block size of SDIO transfer
+ * @d		struct dvobj_priv*
+ *
+ * The unit of return value is byte.
+ */
+static inline u32 rtw_sdio_get_block_size(struct dvobj_priv *d)
+{
+	return d->intf_data.block_transfer_len;
+}
+
+/**
+ * rtw_sdio_cmd53_align_size() - Align size to one CMD53 could complete
+ * @d		struct dvobj_priv*
+ * @len		length to align
+ *
+ * Adjust len to align block size, and the new size could be transfered by one
+ * CMD53.
+ * If len < block size, it would keep original value, otherwise the value
+ * would be rounded up by block size.
+ *
+ * Return adjusted length.
+ */
+static inline size_t rtw_sdio_cmd53_align_size(struct dvobj_priv *d, size_t len)
+{
+	u32 blk_sz;
+
+
+	blk_sz = rtw_sdio_get_block_size(d);
+	if (len <= blk_sz)
+		return len;
+
+	return _RND(len, blk_sz);
+}
+
+#endif /* !__SDIO_OPS_H__ */
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/include/sdio_ops_linux.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/sdio_ops_linux.h
--- linux-5.6.3/3rdparty/rtl8821ce/include/sdio_ops_linux.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/sdio_ops_linux.h	2020-04-10 16:35:06.852661748 +0300
@@ -0,0 +1,58 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#ifndef __SDIO_OPS_LINUX_H__
+#define __SDIO_OPS_LINUX_H__
+
+#ifndef RTW_HALMAC
+u8 sd_f0_read8(struct intf_hdl *pintfhdl, u32 addr, s32 *err);
+void sd_f0_write8(struct intf_hdl *pintfhdl, u32 addr, u8 v, s32 *err);
+
+s32 _sd_cmd52_read(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *pdata);
+s32 _sd_cmd52_write(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *pdata);
+s32 sd_cmd52_read(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *pdata);
+s32 sd_cmd52_write(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *pdata);
+
+u8 _sd_read8(struct intf_hdl *pintfhdl, u32 addr, s32 *err);
+u8 sd_read8(struct intf_hdl *pintfhdl, u32 addr, s32 *err);
+u16 sd_read16(struct intf_hdl *pintfhdl, u32 addr, s32 *err);
+u32 _sd_read32(struct intf_hdl *pintfhdl, u32 addr, s32 *err);
+u32 sd_read32(struct intf_hdl *pintfhdl, u32 addr, s32 *err);
+void sd_write8(struct intf_hdl *pintfhdl, u32 addr, u8 v, s32 *err);
+void sd_write16(struct intf_hdl *pintfhdl, u32 addr, u16 v, s32 *err);
+void _sd_write32(struct intf_hdl *pintfhdl, u32 addr, u32 v, s32 *err);
+void sd_write32(struct intf_hdl *pintfhdl, u32 addr, u32 v, s32 *err);
+#endif /* RTW_HALMAC */
+
+bool rtw_is_sdio30(_adapter *adapter);
+
+/* The unit of return value is Hz */
+static inline u32 rtw_sdio_get_clock(struct dvobj_priv *d)
+{
+	return d->intf_data.clock;
+}
+
+s32 _sd_read(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, void *pdata);
+s32 sd_read(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, void *pdata);
+s32 _sd_write(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, void *pdata);
+s32 sd_write(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, void *pdata);
+
+void rtw_sdio_set_irq_thd(struct dvobj_priv *dvobj, _thread_hdl_ thd_hdl);
+int __must_check rtw_sdio_raw_read(struct dvobj_priv *d, unsigned int addr,
+				void *buf, size_t len, bool fixed);
+int __must_check rtw_sdio_raw_write(struct dvobj_priv *d, unsigned int addr,
+				void *buf, size_t len, bool fixed);
+
+#endif /* __SDIO_OPS_LINUX_H__ */
+
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/include/sdio_ops_xp.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/sdio_ops_xp.h
--- linux-5.6.3/3rdparty/rtl8821ce/include/sdio_ops_xp.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/sdio_ops_xp.h	2020-04-10 16:35:06.852661748 +0300
@@ -0,0 +1,49 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#ifndef _SDIO_OPS_XP_H_
+#define _SDIO_OPS_XP_H_
+
+#include <drv_conf.h>
+#include <osdep_service.h>
+#include <drv_types.h>
+#include <osdep_intf.h>
+
+
+#ifdef PLATFORM_OS_XP
+
+
+extern u8 sdbus_cmd52r_xp(struct intf_priv *pintfpriv, u32 addr);
+
+
+extern void sdbus_cmd52w_xp(struct intf_priv *pintfpriv, u32 addr, u8 val8);
+
+
+uint sdbus_read_blocks_to_membuf_xp(struct intf_priv *pintfpriv, u32 addr, u32 cnt, u8 *pbuf);
+
+extern uint sdbus_read_bytes_to_membuf_xp(struct intf_priv *pintfpriv, u32 addr, u32 cnt, u8 *pbuf);
+
+
+extern uint sdbus_write_blocks_from_membuf_xp(struct intf_priv *pintfpriv, u32 addr, u32 cnt, u8 *pbuf, u8 async);
+
+extern uint sdbus_write_bytes_from_membuf_xp(struct intf_priv *pintfpriv, u32 addr, u32 cnt, u8 *pbuf);
+extern u8 sdbus_func1cmd52r_xp(struct intf_priv *pintfpriv, u32 addr);
+extern void sdbus_func1cmd52w_xp(struct intf_priv *pintfpriv, u32 addr, u8 val8);
+extern uint sdbus_read_reg(struct intf_priv *pintfpriv, u32 addr, u32 cnt, void *pdata);
+extern uint sdbus_write_reg(struct intf_priv *pintfpriv, u32 addr, u32 cnt, void *pdata);
+extern void sdio_read_int(_adapter *padapter, u32 addr, u8 sz, void *pdata);
+
+#endif
+
+#endif
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/include/sdio_osintf.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/sdio_osintf.h
--- linux-5.6.3/3rdparty/rtl8821ce/include/sdio_osintf.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/sdio_osintf.h	2020-04-10 16:35:06.852661748 +0300
@@ -0,0 +1,25 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#ifndef __SDIO_OSINTF_H__
+#define __SDIO_OSINTF_H__
+
+
+#ifdef PLATFORM_OS_CE
+extern NDIS_STATUS ce_sd_get_dev_hdl(PADAPTER padapter);
+SD_API_STATUS ce_sd_int_callback(SD_DEVICE_HANDLE hDevice, PADAPTER padapter);
+extern void sd_setup_irs(PADAPTER padapter);
+#endif
+
+#endif
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/include/sta_info.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/sta_info.h
--- linux-5.6.3/3rdparty/rtl8821ce/include/sta_info.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/sta_info.h	2020-04-10 16:35:06.852661748 +0300
@@ -0,0 +1,741 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#ifndef __STA_INFO_H_
+#define __STA_INFO_H_
+
+#include <cmn_info/rtw_sta_info.h>
+
+#define IBSS_START_MAC_ID	2
+#define NUM_STA MACID_NUM_SW_LIMIT
+
+#ifndef CONFIG_RTW_MACADDR_ACL
+	#define CONFIG_RTW_MACADDR_ACL 1
+#endif
+
+#ifndef CONFIG_RTW_PRE_LINK_STA
+	#define CONFIG_RTW_PRE_LINK_STA 0
+#endif
+
+#define NUM_ACL 16
+
+#define RTW_ACL_PERIOD_DEV 0
+#define RTW_ACL_PERIOD_BSS 1
+#define RTW_ACL_PERIOD_NUM 2
+
+#define RTW_ACL_MODE_DISABLED				0
+#define RTW_ACL_MODE_ACCEPT_UNLESS_LISTED	1
+#define RTW_ACL_MODE_DENY_UNLESS_LISTED		2
+#define RTW_ACL_MODE_MAX					3
+
+#if CONFIG_RTW_MACADDR_ACL
+extern const char *const _acl_period_str[RTW_ACL_PERIOD_NUM];
+#define acl_period_str(mode) (((mode) >= RTW_ACL_PERIOD_NUM) ? "INVALID" : _acl_period_str[(mode)])
+extern const char *const _acl_mode_str[RTW_ACL_MODE_MAX];
+#define acl_mode_str(mode) (((mode) >= RTW_ACL_MODE_MAX) ? "INVALID" : _acl_mode_str[(mode)])
+#endif
+
+#ifndef RTW_PRE_LINK_STA_NUM
+	#define RTW_PRE_LINK_STA_NUM 8
+#endif
+
+struct pre_link_sta_node_t {
+	u8 valid;
+	u8 addr[ETH_ALEN];
+};
+
+struct pre_link_sta_ctl_t {
+	_lock lock;
+	u8 num;
+	struct pre_link_sta_node_t node[RTW_PRE_LINK_STA_NUM];
+};
+
+#ifdef CONFIG_TDLS
+#define MAX_ALLOWED_TDLS_STA_NUM	4
+#endif
+
+enum sta_info_update_type {
+	STA_INFO_UPDATE_NONE = 0,
+	STA_INFO_UPDATE_BW = BIT(0),
+	STA_INFO_UPDATE_RATE = BIT(1),
+	STA_INFO_UPDATE_PROTECTION_MODE = BIT(2),
+	STA_INFO_UPDATE_CAP = BIT(3),
+	STA_INFO_UPDATE_HT_CAP = BIT(4),
+	STA_INFO_UPDATE_VHT_CAP = BIT(5),
+	STA_INFO_UPDATE_ALL = STA_INFO_UPDATE_BW
+			      | STA_INFO_UPDATE_RATE
+			      | STA_INFO_UPDATE_PROTECTION_MODE
+			      | STA_INFO_UPDATE_CAP
+			      | STA_INFO_UPDATE_HT_CAP
+			      | STA_INFO_UPDATE_VHT_CAP,
+	STA_INFO_UPDATE_MAX
+};
+
+struct rtw_wlan_acl_node {
+	_list		        list;
+	u8       addr[ETH_ALEN];
+	u8       valid;
+};
+
+struct wlan_acl_pool {
+	int mode;
+	int num;
+	struct rtw_wlan_acl_node aclnode[NUM_ACL];
+	_queue	acl_node_q;
+};
+
+struct	stainfo_stats	{
+	systime last_rx_time;
+
+	u64 rx_mgnt_pkts;
+	u64 rx_beacon_pkts;
+	u64 rx_probereq_pkts;
+	u64 rx_probersp_pkts; /* unicast to self */
+	u64 rx_probersp_bm_pkts;
+	u64 rx_probersp_uo_pkts; /* unicast to others */
+	u64 rx_ctrl_pkts;
+	u64 rx_data_pkts;
+	u64 rx_data_bc_pkts;
+	u64 rx_data_mc_pkts;
+	u64 rx_data_qos_pkts[TID_NUM]; /* unicast only */
+
+	u64	last_rx_mgnt_pkts;
+	u64 last_rx_beacon_pkts;
+	u64 last_rx_probereq_pkts;
+	u64 last_rx_probersp_pkts; /* unicast to self */
+	u64 last_rx_probersp_bm_pkts;
+	u64 last_rx_probersp_uo_pkts; /* unicast to others */
+	u64	last_rx_ctrl_pkts;
+	u64	last_rx_data_pkts;
+	u64 last_rx_data_bc_pkts;
+	u64 last_rx_data_mc_pkts;
+	u64 last_rx_data_qos_pkts[TID_NUM]; /* unicast only */
+
+#ifdef CONFIG_TDLS
+	u64 rx_tdls_disc_rsp_pkts;
+	u64 last_rx_tdls_disc_rsp_pkts;
+#endif
+
+	u64	rx_bytes;
+	u64	rx_bc_bytes;
+	u64	rx_mc_bytes;
+	u64	last_rx_bytes;
+	u64 last_rx_bc_bytes;
+	u64 last_rx_mc_bytes;
+	u64	rx_drops; /* TBD */
+	u32 rx_tp_kbits;
+	u32 smooth_rx_tp_kbits;
+
+	u64	tx_pkts;
+	u64	last_tx_pkts;
+
+	u64	tx_bytes;
+	u64	last_tx_bytes;
+	u64 tx_drops; /* TBD */
+	u32 tx_tp_kbits;
+	u32 smooth_tx_tp_kbits;
+
+#ifdef CONFIG_LPS_CHK_BY_TP
+	u64 acc_tx_bytes;
+	u64 acc_rx_bytes;
+#endif
+
+	/* unicast only */
+	u64 last_rx_data_uc_pkts; /* For Read & Clear requirement in proc_get_rx_stat() */
+	u32 duplicate_cnt;	/* Read & Clear, in proc_get_rx_stat() */
+	u32 rxratecnt[128];	/* Read & Clear, in proc_get_rx_stat() */
+	u32 tx_ok_cnt;		/* Read & Clear, in proc_get_tx_stat() */
+	u32 tx_fail_cnt;	/* Read & Clear, in proc_get_tx_stat() */
+	u32 tx_retry_cnt;	/* Read & Clear, in proc_get_tx_stat() */
+#ifdef CONFIG_RTW_MESH
+	u32 rx_hwmp_pkts;
+	u32 last_rx_hwmp_pkts;
+#endif
+};
+
+#ifndef DBG_SESSION_TRACKER
+#define DBG_SESSION_TRACKER 0
+#endif
+
+/* session tracker status */
+#define ST_STATUS_NONE		0
+#define ST_STATUS_CHECK		BIT0
+#define ST_STATUS_ESTABLISH	BIT1
+#define ST_STATUS_EXPIRE	BIT2
+
+#define ST_EXPIRE_MS (10 * 1000)
+
+struct session_tracker {
+	_list list; /* session_tracker_queue */
+	u32 local_naddr;
+	u16 local_port;
+	u32 remote_naddr;
+	u16 remote_port;
+	systime set_time;
+	u8 status;
+};
+
+/* session tracker cmd */
+#define ST_CMD_ADD 0
+#define ST_CMD_DEL 1
+#define ST_CMD_CHK 2
+
+struct st_cmd_parm {
+	u8 cmd;
+	struct sta_info *sta;
+	u32 local_naddr; /* TODO: IPV6 */
+	u16 local_port;
+	u32 remote_naddr; /* TODO: IPV6 */
+	u16 remote_port;
+};
+
+typedef bool (*st_match_rule)(_adapter *adapter, u8 *local_naddr, u8 *local_port, u8 *remote_naddr, u8 *remote_port);
+
+struct st_register {
+	u8 s_proto;
+	st_match_rule rule;
+};
+
+#define SESSION_TRACKER_REG_ID_WFD 0
+#define SESSION_TRACKER_REG_ID_NUM 1
+
+struct st_ctl_t {
+	struct st_register reg[SESSION_TRACKER_REG_ID_NUM];
+	_queue tracker_q;
+};
+
+void rtw_st_ctl_init(struct st_ctl_t *st_ctl);
+void rtw_st_ctl_deinit(struct st_ctl_t *st_ctl);
+void rtw_st_ctl_register(struct st_ctl_t *st_ctl, u8 st_reg_id, struct st_register *reg);
+void rtw_st_ctl_unregister(struct st_ctl_t *st_ctl, u8 st_reg_id);
+bool rtw_st_ctl_chk_reg_s_proto(struct st_ctl_t *st_ctl, u8 s_proto);
+bool rtw_st_ctl_chk_reg_rule(struct st_ctl_t *st_ctl, _adapter *adapter, u8 *local_naddr, u8 *local_port, u8 *remote_naddr, u8 *remote_port);
+void rtw_st_ctl_rx(struct sta_info *sta, u8 *ehdr_pos);
+void dump_st_ctl(void *sel, struct st_ctl_t *st_ctl);
+
+#ifdef CONFIG_TDLS
+struct TDLS_PeerKey {
+	u8 kck[16]; /* TPK-KCK */
+	u8 tk[16]; /* TPK-TK; only CCMP will be used */
+} ;
+#endif /* CONFIG_TDLS */
+
+#ifdef DBG_RX_DFRAME_RAW_DATA
+struct sta_recv_dframe_info {
+
+	u8 sta_data_rate;
+	u8 sta_sgi;
+	u8 sta_bw_mode;
+	s8 sta_mimo_signal_strength[4];
+	s8 sta_RxPwr[4];
+	u8 sta_ofdm_snr[4];
+};
+#endif
+
+#ifdef CONFIG_RTW_MESH
+struct mesh_plink_ent;
+struct rtw_ewma_err_rate {
+	unsigned long internal;
+};
+
+/* Mesh airtime link metrics parameters */
+struct rtw_atlm_param {
+	struct rtw_ewma_err_rate err_rate; /* Now is PACKET error rate */
+	u16 data_rate; /* The unit is 100Kbps */
+	u16 total_pkt;
+	u16 overhead; /* Channel access overhead */
+};
+#endif
+
+struct sta_info {
+
+	_lock	lock;
+	_list	list; /* free_sta_queue */
+	_list	hash_list; /* sta_hash */
+	/* _list asoc_list; */ /* 20061114 */
+	/* _list sleep_list; */ /* sleep_q */
+	/* _list wakeup_list; */ /* wakeup_q */
+	_adapter *padapter;
+	struct cmn_sta_info cmn;
+
+	struct sta_xmit_priv sta_xmitpriv;
+	struct sta_recv_priv sta_recvpriv;
+
+#ifdef DBG_RX_DFRAME_RAW_DATA
+	struct sta_recv_dframe_info  sta_dframe_info;
+	struct sta_recv_dframe_info  sta_dframe_info_bmc;
+#endif
+	_queue sleep_q;
+	unsigned int sleepq_len;
+
+	uint state;
+	uint qos_option;
+	u16 hwseq;
+
+#ifdef CONFIG_RTW_80211K
+	u8 rm_en_cap[5];
+	u8 rm_diag_token;
+#endif /* CONFIG_RTW_80211K */
+
+	uint	ieee8021x_blocked;	/* 0: allowed, 1:blocked */
+	uint	dot118021XPrivacy; /* aes, tkip... */
+	union Keytype	dot11tkiptxmickey;
+	union Keytype	dot11tkiprxmickey;
+	union Keytype	dot118021x_UncstKey;
+	union pn48		dot11txpn;			/* PN48 used for Unicast xmit */
+	union pn48		dot11rxpn;			/* PN48 used for Unicast recv. */
+#ifdef CONFIG_RTW_MESH
+	/* peer's GTK, RX only */
+	u8 group_privacy;
+	u8 gtk_bmp;
+	union Keytype gtk;
+	union pn48 gtk_pn;
+	#ifdef CONFIG_IEEE80211W
+	/* peer's IGTK, RX only */
+	u8 igtk_bmp;
+	u8 igtk_id;
+	union Keytype igtk;
+	union pn48 igtk_pn;
+	#endif /* CONFIG_IEEE80211W */
+#endif /* CONFIG_RTW_MESH */
+#ifdef CONFIG_GTK_OL
+	u8 kek[RTW_KEK_LEN];
+	u8 kck[RTW_KCK_LEN];
+	u8 replay_ctr[RTW_REPLAY_CTR_LEN];
+#endif /* CONFIG_GTK_OL */
+#ifdef CONFIG_IEEE80211W
+	_timer dot11w_expire_timer;
+#endif /* CONFIG_IEEE80211W */
+
+	u8	bssrateset[16];
+	u32	bssratelen;
+
+	u8	cts2self;
+	u8	rtsen;
+
+	u8	init_rate;
+	u8	wireless_mode;	/* NETWORK_TYPE */
+
+	struct stainfo_stats sta_stats;
+
+#ifdef CONFIG_TDLS
+	u32	tdls_sta_state;
+	u8	SNonce[32];
+	u8	ANonce[32];
+	u32	TDLS_PeerKey_Lifetime;
+	u32	TPK_count;
+	_timer	TPK_timer;
+	struct TDLS_PeerKey	tpk;
+#ifdef CONFIG_TDLS_CH_SW
+	u16	ch_switch_time;
+	u16	ch_switch_timeout;
+	/* u8	option; */
+	_timer	ch_sw_timer;
+	_timer	delay_timer;
+	_timer	stay_on_base_chnl_timer;
+	_timer	ch_sw_monitor_timer;
+#endif
+	_timer handshake_timer;
+	u8 alive_count;
+	_timer	pti_timer;
+	u8	TDLS_RSNIE[20];	/* Save peer's RSNIE, used for sending TDLS_SETUP_RSP */
+#endif /* CONFIG_TDLS */
+
+	/* for A-MPDU TX, ADDBA timeout check	 */
+	_timer addba_retry_timer;
+
+	/* for A-MPDU Rx reordering buffer control */
+	struct recv_reorder_ctrl recvreorder_ctrl[TID_NUM];
+	ATOMIC_T continual_no_rx_packet[TID_NUM];
+	/* for A-MPDU Tx */
+	/* unsigned char		ampdu_txen_bitmap; */
+	u16	BA_starting_seqctrl[16];
+
+
+#ifdef CONFIG_80211N_HT
+	struct ht_priv	htpriv;
+#endif
+
+#ifdef CONFIG_80211AC_VHT
+	struct vht_priv	vhtpriv;
+#endif
+
+	/* Notes:	 */
+	/* STA_Mode: */
+	/* curr_network(mlme_priv/security_priv/qos/ht) + sta_info: (STA & AP) CAP/INFO	 */
+	/* scan_q: AP CAP/INFO */
+
+	/* AP_Mode: */
+	/* curr_network(mlme_priv/security_priv/qos/ht) : AP CAP/INFO */
+	/* sta_info: (AP & STA) CAP/INFO */
+
+	unsigned int expire_to;
+
+#ifdef CONFIG_AP_MODE
+
+	_list asoc_list;
+	_list auth_list;
+
+	unsigned int auth_seq;
+	unsigned int authalg;
+	unsigned char chg_txt[128];
+
+	u16 capability;
+	int flags;
+
+	int dot8021xalg;/* 0:disable, 1:psk, 2:802.1x */
+	int wpa_psk;/* 0:disable, bit(0): WPA, bit(1):WPA2 */
+	int wpa_group_cipher;
+	int wpa2_group_cipher;
+	int wpa_pairwise_cipher;
+	int wpa2_pairwise_cipher;
+
+	u8 bpairwise_key_installed;
+#ifdef CONFIG_RTW_80211R
+	u8 ft_pairwise_key_installed;
+#endif
+
+#ifdef CONFIG_NATIVEAP_MLME
+	u8 wpa_ie[32];
+
+	u8 nonerp_set;
+	u8 no_short_slot_time_set;
+	u8 no_short_preamble_set;
+	u8 no_ht_gf_set;
+	u8 no_ht_set;
+	u8 ht_20mhz_set;
+	u8 ht_40mhz_intolerant;
+#endif /* CONFIG_NATIVEAP_MLME */
+
+#ifdef CONFIG_ATMEL_RC_PATCH
+	u8 flag_atmel_rc;
+#endif
+
+	u8 qos_info;
+
+	u8 max_sp_len;
+	u8 uapsd_bk;/* BIT(0): Delivery enabled, BIT(1): Trigger enabled */
+	u8 uapsd_be;
+	u8 uapsd_vi;
+	u8 uapsd_vo;
+
+	u8 has_legacy_ac;
+	unsigned int sleepq_ac_len;
+
+#ifdef CONFIG_P2P
+	/* p2p priv data */
+	u8 is_p2p_device;
+	u8 p2p_status_code;
+
+	/* p2p client info */
+	u8 dev_addr[ETH_ALEN];
+	/* u8 iface_addr[ETH_ALEN]; */ /* = hwaddr[ETH_ALEN] */
+	u8 dev_cap;
+	u16 config_methods;
+	u8 primary_dev_type[8];
+	u8 num_of_secdev_type;
+	u8 secdev_types_list[32];/* 32/8 == 4; */
+	u16 dev_name_len;
+	u8 dev_name[32];
+#endif /* CONFIG_P2P */
+
+#ifdef CONFIG_WFD
+	u8 op_wfd_mode;
+#endif
+
+#ifdef CONFIG_TX_MCAST2UNI
+	u8 under_exist_checking;
+#endif /* CONFIG_TX_MCAST2UNI */
+
+	u8 keep_alive_trycnt;
+
+#ifdef CONFIG_AUTO_AP_MODE
+	u8 isrc; /* this device is rc */
+	u16 pid; /* pairing id */
+#endif
+
+#endif /* CONFIG_AP_MODE	 */
+
+#ifdef CONFIG_RTW_MESH
+	struct mesh_plink_ent *plink;
+
+	u8 local_mps;
+	u8 peer_mps;
+	u8 nonpeer_mps;
+
+	struct rtw_atlm_param metrics;
+#endif
+
+#ifdef CONFIG_IOCTL_CFG80211
+	u8 *passoc_req;
+	u32 assoc_req_len;
+#endif
+
+	u8		IOTPeer;			/* Enum value.	HT_IOT_PEER_E */
+#ifdef CONFIG_LPS_PG
+	u8		lps_pg_rssi_lv;
+#endif
+
+	/* To store the sequence number of received management frame */
+	u16 RxMgmtFrameSeqNum;
+
+	struct st_ctl_t st_ctl;
+	u8 max_agg_num_minimal_record; /*keep minimal tx desc max_agg_num setting*/
+	u8 curr_rx_rate;
+	u8 curr_rx_rate_bmc;
+};
+
+#ifdef CONFIG_RTW_MESH
+#define STA_SET_MESH_PLINK(sta, link) (sta)->plink = link
+#else
+#define STA_SET_MESH_PLINK(sta, link) do {} while (0)
+#endif
+
+#define sta_tx_pkts(sta) \
+	(sta->sta_stats.tx_pkts)
+
+#define sta_last_tx_pkts(sta) \
+	(sta->sta_stats.last_tx_pkts)
+
+#define sta_rx_pkts(sta) \
+	(sta->sta_stats.rx_mgnt_pkts \
+	 + sta->sta_stats.rx_ctrl_pkts \
+	 + sta->sta_stats.rx_data_pkts)
+
+#define sta_last_rx_pkts(sta) \
+	(sta->sta_stats.last_rx_mgnt_pkts \
+	 + sta->sta_stats.last_rx_ctrl_pkts \
+	 + sta->sta_stats.last_rx_data_pkts)
+
+#define sta_rx_data_pkts(sta) (sta->sta_stats.rx_data_pkts)
+#define sta_last_rx_data_pkts(sta) (sta->sta_stats.last_rx_data_pkts)
+
+#define sta_rx_data_uc_pkts(sta) (sta->sta_stats.rx_data_pkts - sta->sta_stats.rx_data_bc_pkts - sta->sta_stats.rx_data_mc_pkts)
+#define sta_last_rx_data_uc_pkts(sta) (sta->sta_stats.last_rx_data_pkts - sta->sta_stats.last_rx_data_bc_pkts - sta->sta_stats.last_rx_data_mc_pkts)
+
+#define sta_rx_data_qos_pkts(sta, i) \
+	(sta->sta_stats.rx_data_qos_pkts[i])
+
+#define sta_last_rx_data_qos_pkts(sta, i) \
+	(sta->sta_stats.last_rx_data_qos_pkts[i])
+
+#define sta_rx_mgnt_pkts(sta) \
+	(sta->sta_stats.rx_mgnt_pkts)
+
+#define sta_last_rx_mgnt_pkts(sta) \
+	(sta->sta_stats.last_rx_mgnt_pkts)
+
+#define sta_rx_beacon_pkts(sta) \
+	(sta->sta_stats.rx_beacon_pkts)
+
+#define sta_last_rx_beacon_pkts(sta) \
+	(sta->sta_stats.last_rx_beacon_pkts)
+
+#define sta_rx_probereq_pkts(sta) \
+	(sta->sta_stats.rx_probereq_pkts)
+
+#define sta_last_rx_probereq_pkts(sta) \
+	(sta->sta_stats.last_rx_probereq_pkts)
+
+#define sta_rx_probersp_pkts(sta) \
+	(sta->sta_stats.rx_probersp_pkts)
+
+#define sta_last_rx_probersp_pkts(sta) \
+	(sta->sta_stats.last_rx_probersp_pkts)
+
+#define sta_rx_probersp_bm_pkts(sta) \
+	(sta->sta_stats.rx_probersp_bm_pkts)
+
+#define sta_last_rx_probersp_bm_pkts(sta) \
+	(sta->sta_stats.last_rx_probersp_bm_pkts)
+
+#define sta_rx_probersp_uo_pkts(sta) \
+	(sta->sta_stats.rx_probersp_uo_pkts)
+
+#define sta_last_rx_probersp_uo_pkts(sta) \
+	(sta->sta_stats.last_rx_probersp_uo_pkts)
+
+#ifdef CONFIG_RTW_MESH
+#define update_last_rx_hwmp_pkts(sta) \
+	do { \
+		sta->sta_stats.last_rx_hwmp_pkts = sta->sta_stats.rx_hwmp_pkts; \
+	} while(0)
+#else
+#define update_last_rx_hwmp_pkts(sta) do {} while(0)
+#endif
+
+#define sta_update_last_rx_pkts(sta) \
+	do { \
+		int __i; \
+		\
+		sta->sta_stats.last_rx_mgnt_pkts = sta->sta_stats.rx_mgnt_pkts; \
+		sta->sta_stats.last_rx_beacon_pkts = sta->sta_stats.rx_beacon_pkts; \
+		sta->sta_stats.last_rx_probereq_pkts = sta->sta_stats.rx_probereq_pkts; \
+		sta->sta_stats.last_rx_probersp_pkts = sta->sta_stats.rx_probersp_pkts; \
+		sta->sta_stats.last_rx_probersp_bm_pkts = sta->sta_stats.rx_probersp_bm_pkts; \
+		sta->sta_stats.last_rx_probersp_uo_pkts = sta->sta_stats.rx_probersp_uo_pkts; \
+		sta->sta_stats.last_rx_ctrl_pkts = sta->sta_stats.rx_ctrl_pkts; \
+		update_last_rx_hwmp_pkts(sta); \
+		\
+		sta->sta_stats.last_rx_data_pkts = sta->sta_stats.rx_data_pkts; \
+		sta->sta_stats.last_rx_data_bc_pkts = sta->sta_stats.rx_data_bc_pkts; \
+		sta->sta_stats.last_rx_data_mc_pkts = sta->sta_stats.rx_data_mc_pkts; \
+		for (__i = 0; __i < TID_NUM; __i++) \
+			sta->sta_stats.last_rx_data_qos_pkts[__i] = sta->sta_stats.rx_data_qos_pkts[__i]; \
+	} while (0)
+
+#define STA_RX_PKTS_ARG(sta) \
+	sta->sta_stats.rx_mgnt_pkts \
+	, sta->sta_stats.rx_ctrl_pkts \
+	, sta->sta_stats.rx_data_pkts
+
+#define STA_LAST_RX_PKTS_ARG(sta) \
+	sta->sta_stats.last_rx_mgnt_pkts \
+	, sta->sta_stats.last_rx_ctrl_pkts \
+	, sta->sta_stats.last_rx_data_pkts
+
+#define STA_RX_PKTS_DIFF_ARG(sta) \
+	sta->sta_stats.rx_mgnt_pkts - sta->sta_stats.last_rx_mgnt_pkts \
+	, sta->sta_stats.rx_ctrl_pkts - sta->sta_stats.last_rx_ctrl_pkts \
+	, sta->sta_stats.rx_data_pkts - sta->sta_stats.last_rx_data_pkts
+
+#define STA_PKTS_FMT "(m:%llu, c:%llu, d:%llu)"
+
+#define sta_rx_uc_bytes(sta) (sta->sta_stats.rx_bytes - sta->sta_stats.rx_bc_bytes - sta->sta_stats.rx_mc_bytes)
+#define sta_last_rx_uc_bytes(sta) (sta->sta_stats.last_rx_bytes - sta->sta_stats.last_rx_bc_bytes - sta->sta_stats.last_rx_mc_bytes)
+
+#ifdef CONFIG_WFD
+#define STA_OP_WFD_MODE(sta) (sta)->op_wfd_mode
+#define STA_SET_OP_WFD_MODE(sta, mode) (sta)->op_wfd_mode = (mode)
+#else
+#define STA_OP_WFD_MODE(sta) 0
+#define STA_SET_OP_WFD_MODE(sta, mode) do {} while (0)
+#endif
+
+#define AID_BMP_LEN(max_aid) ((max_aid + 1) / 8 + (((max_aid + 1) % 8) ? 1 : 0))
+
+struct	sta_priv {
+
+	u8 *pallocated_stainfo_buf;
+	u8 *pstainfo_buf;
+	_queue	free_sta_queue;
+
+	_lock sta_hash_lock;
+	_list   sta_hash[NUM_STA];
+	int asoc_sta_count;
+	_queue sleep_q;
+	_queue wakeup_q;
+
+	_adapter *padapter;
+
+	u32 adhoc_expire_to;
+
+#ifdef CONFIG_AP_MODE
+	_list asoc_list;
+	_list auth_list;
+	_lock asoc_list_lock;
+	_lock auth_list_lock;
+	u8 asoc_list_cnt;
+	u8 auth_list_cnt;
+
+	unsigned int auth_to;  /* sec, time to expire in authenticating. */
+	unsigned int assoc_to; /* sec, time to expire before associating. */
+	unsigned int expire_to; /* sec , time to expire after associated. */
+
+	/*
+	* pointers to STA info; based on allocated AID or NULL if AID free
+	* AID is in the range 1-2007, so sta_aid[0] corresponders to AID 1
+	*/
+	struct sta_info **sta_aid;
+	u16 max_aid;
+	u16 started_aid; /* started AID for allocation search */
+	bool rr_aid; /* round robin AID allocation, will modify started_aid */
+	u8 aid_bmp_len; /* in byte */
+	u8 *sta_dz_bitmap;
+	u8 *tim_bitmap;
+
+	u16 max_num_sta;
+
+#if CONFIG_RTW_MACADDR_ACL
+	struct wlan_acl_pool acl_list[RTW_ACL_PERIOD_NUM];
+#endif
+
+	#if CONFIG_RTW_PRE_LINK_STA
+	struct pre_link_sta_ctl_t pre_link_sta_ctl;
+	#endif
+
+#endif /* CONFIG_AP_MODE */
+
+#ifdef CONFIG_ATMEL_RC_PATCH
+	u8 atmel_rc_pattern[6];
+#endif
+	u8 c2h_sta_mac[ETH_ALEN];
+	u8 c2h_adapter_id;
+	struct submit_ctx *gotc2h;
+};
+
+
+__inline static u32 wifi_mac_hash(const u8 *mac)
+{
+	u32 x;
+
+	x = mac[0];
+	x = (x << 2) ^ mac[1];
+	x = (x << 2) ^ mac[2];
+	x = (x << 2) ^ mac[3];
+	x = (x << 2) ^ mac[4];
+	x = (x << 2) ^ mac[5];
+
+	x ^= x >> 8;
+	x  = x & (NUM_STA - 1);
+
+	return x;
+}
+
+
+extern u32	_rtw_init_sta_priv(struct sta_priv *pstapriv);
+extern u32	_rtw_free_sta_priv(struct sta_priv *pstapriv);
+
+#define stainfo_offset_valid(offset) (offset < NUM_STA && offset >= 0)
+int rtw_stainfo_offset(struct sta_priv *stapriv, struct sta_info *sta);
+struct sta_info *rtw_get_stainfo_by_offset(struct sta_priv *stapriv, int offset);
+
+extern struct sta_info *rtw_alloc_stainfo(struct	sta_priv *pstapriv, const u8 *hwaddr);
+extern u32	rtw_free_stainfo(_adapter *padapter , struct sta_info *psta);
+extern void rtw_free_all_stainfo(_adapter *padapter);
+extern struct sta_info *rtw_get_stainfo(struct sta_priv *pstapriv, const u8 *hwaddr);
+extern u32 rtw_init_bcmc_stainfo(_adapter *padapter);
+extern struct sta_info *rtw_get_bcmc_stainfo(_adapter *padapter);
+
+#ifdef CONFIG_AP_MODE
+u16 rtw_aid_alloc(_adapter *adapter, struct sta_info *sta);
+void dump_aid_status(void *sel, _adapter *adapter);
+#endif
+
+#if CONFIG_RTW_MACADDR_ACL
+extern u8 rtw_access_ctrl(_adapter *adapter, const u8 *mac_addr);
+void dump_macaddr_acl(void *sel, _adapter *adapter);
+#endif
+
+bool rtw_is_pre_link_sta(struct sta_priv *stapriv, u8 *addr);
+#if CONFIG_RTW_PRE_LINK_STA
+struct sta_info *rtw_pre_link_sta_add(struct sta_priv *stapriv, u8 *hwaddr);
+void rtw_pre_link_sta_del(struct sta_priv *stapriv, u8 *hwaddr);
+void rtw_pre_link_sta_ctl_reset(struct sta_priv *stapriv);
+void rtw_pre_link_sta_ctl_init(struct sta_priv *stapriv);
+void rtw_pre_link_sta_ctl_deinit(struct sta_priv *stapriv);
+void dump_pre_link_sta_ctl(void *sel, struct sta_priv *stapriv);
+#endif /* CONFIG_RTW_PRE_LINK_STA */
+
+#endif /* _STA_INFO_H_ */
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/include/usb_hal.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/usb_hal.h
--- linux-5.6.3/3rdparty/rtl8821ce/include/usb_hal.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/usb_hal.h	2020-04-10 16:35:06.852661748 +0300
@@ -0,0 +1,74 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#ifndef __USB_HAL_H__
+#define __USB_HAL_H__
+
+int usb_init_recv_priv(_adapter *padapter, u16 ini_in_buf_sz);
+void usb_free_recv_priv(_adapter *padapter, u16 ini_in_buf_sz);
+#ifdef CONFIG_FW_C2H_REG
+void usb_c2h_hisr_hdl(_adapter *adapter, u8 *buf);
+#endif
+
+u8 rtw_set_hal_ops(_adapter *padapter);
+
+#ifdef CONFIG_RTL8188E
+void rtl8188eu_set_hal_ops(_adapter *padapter);
+#endif
+
+#if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A)
+void rtl8812au_set_hal_ops(_adapter *padapter);
+#endif
+
+#ifdef CONFIG_RTL8192E
+void rtl8192eu_set_hal_ops(_adapter *padapter);
+#endif
+
+
+#ifdef CONFIG_RTL8723B
+void rtl8723bu_set_hal_ops(_adapter *padapter);
+#endif
+
+#ifdef CONFIG_RTL8814A
+void rtl8814au_set_hal_ops(_adapter *padapter);
+#endif /* CONFIG_RTL8814A */
+
+#ifdef CONFIG_RTL8188F
+void rtl8188fu_set_hal_ops(_adapter *padapter);
+#endif
+
+#ifdef CONFIG_RTL8188GTV
+void rtl8188gtvu_set_hal_ops(_adapter *padapter);
+#endif
+
+#ifdef CONFIG_RTL8703B
+void rtl8703bu_set_hal_ops(_adapter *padapter);
+#endif
+
+#ifdef CONFIG_RTL8723D
+void rtl8723du_set_hal_ops(_adapter *padapter);
+#endif
+
+#ifdef CONFIG_RTL8710B
+void rtl8710bu_set_hal_ops(_adapter *padapter);
+#endif
+
+#ifdef CONFIG_RTL8192F
+void rtl8192fu_set_hal_ops(_adapter *padapter);
+#endif /* CONFIG_RTL8192F */
+
+#ifdef CONFIG_INTEL_PROXIM
+extern _adapter  *rtw_usb_get_sw_pointer(void);
+#endif /* CONFIG_INTEL_PROXIM */
+#endif /* __USB_HAL_H__ */
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/include/usb_ops.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/usb_ops.h
--- linux-5.6.3/3rdparty/rtl8821ce/include/usb_ops.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/usb_ops.h	2020-04-10 16:35:06.852661748 +0300
@@ -0,0 +1,153 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#ifndef __USB_OPS_H_
+#define __USB_OPS_H_
+
+
+#define REALTEK_USB_VENQT_READ		0xC0
+#define REALTEK_USB_VENQT_WRITE	0x40
+#define REALTEK_USB_VENQT_CMD_REQ	0x05
+#define REALTEK_USB_VENQT_CMD_IDX	0x00
+#define REALTEK_USB_IN_INT_EP_IDX	1
+
+enum {
+	VENDOR_WRITE = 0x00,
+	VENDOR_READ = 0x01,
+};
+#define ALIGNMENT_UNIT				16
+#define MAX_VENDOR_REQ_CMD_SIZE	254		/* 8188cu SIE Support */
+#define MAX_USB_IO_CTL_SIZE		(MAX_VENDOR_REQ_CMD_SIZE + ALIGNMENT_UNIT)
+
+#ifdef PLATFORM_LINUX
+#include <usb_ops_linux.h>
+#endif /* PLATFORM_LINUX */
+
+#ifdef CONFIG_RTL8188E
+void rtl8188eu_set_hw_type(struct dvobj_priv *pdvobj);
+#ifdef CONFIG_SUPPORT_USB_INT
+void interrupt_handler_8188eu(_adapter *padapter, u16 pkt_len, u8 *pbuf);
+#endif
+#endif
+
+#if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A)
+void rtl8812au_set_hw_type(struct dvobj_priv *pdvobj);
+#ifdef CONFIG_SUPPORT_USB_INT
+void interrupt_handler_8812au(_adapter *padapter, u16 pkt_len, u8 *pbuf);
+#endif
+#endif
+
+#ifdef CONFIG_RTL8814A
+void rtl8814au_set_hw_type(struct dvobj_priv *pdvobj);
+#ifdef CONFIG_SUPPORT_USB_INT
+void interrupt_handler_8814au(_adapter *padapter, u16 pkt_len, u8 *pbuf);
+#endif
+#endif /* CONFIG_RTL8814 */
+
+#ifdef CONFIG_RTL8192E
+void rtl8192eu_set_hw_type(struct dvobj_priv *pdvobj);
+#ifdef CONFIG_SUPPORT_USB_INT
+void interrupt_handler_8192eu(_adapter *padapter, u16 pkt_len, u8 *pbuf);
+#endif
+
+#endif
+
+#ifdef CONFIG_RTL8188F
+void rtl8188fu_set_hw_type(struct dvobj_priv *pdvobj);
+#ifdef CONFIG_SUPPORT_USB_INT
+void interrupt_handler_8188fu(_adapter *padapter, u16 pkt_len, u8 *pbuf);
+#endif
+#endif
+
+#ifdef CONFIG_RTL8188GTV
+void rtl8188gtvu_set_hw_type(struct dvobj_priv *pdvobj);
+#ifdef CONFIG_SUPPORT_USB_INT
+void interrupt_handler_8188gtvu(_adapter *padapter, u16 pkt_len, u8 *pbuf);
+#endif
+#endif
+
+#ifdef CONFIG_RTL8723B
+void rtl8723bu_set_hw_type(struct dvobj_priv *pdvobj);
+#ifdef CONFIG_SUPPORT_USB_INT
+void interrupt_handler_8723bu(_adapter *padapter, u16 pkt_len, u8 *pbuf);
+#endif
+#endif
+
+#ifdef CONFIG_RTL8703B
+void rtl8703bu_set_hw_type(struct dvobj_priv *pdvobj);
+#ifdef CONFIG_SUPPORT_USB_INT
+void interrupt_handler_8703bu(_adapter *padapter, u16 pkt_len, u8 *pbuf);
+#endif /* CONFIG_SUPPORT_USB_INT */
+#endif /* CONFIG_RTL8703B */
+
+void usb_set_intf_ops(_adapter *padapter, struct _io_ops *pops);
+
+#ifdef CONFIG_RTL8723D
+void rtl8723du_set_hw_type(struct dvobj_priv *pdvobj);
+void rtl8723du_set_intf_ops(struct _io_ops *pops);
+void rtl8723du_recv_tasklet(void *priv);
+void rtl8723du_xmit_tasklet(void *priv);
+#ifdef CONFIG_SUPPORT_USB_INT
+void interrupt_handler_8723du(_adapter *padapter, u16 pkt_len, u8 *pbuf);
+#endif /* CONFIG_SUPPORT_USB_INT */
+#endif /* CONFIG_RTL8723D */
+
+#ifdef CONFIG_RTL8710B
+void rtl8710bu_set_hw_type(struct dvobj_priv *pdvobj);
+void rtl8710bu_set_intf_ops(struct _io_ops *pops);
+void rtl8710bu_recv_tasklet(void *priv);
+void rtl8710bu_xmit_tasklet(void *priv);
+#ifdef CONFIG_SUPPORT_USB_INT
+void interrupt_handler_8710bu(_adapter *padapter, u16 pkt_len, u8 *pbuf);
+#endif /* CONFIG_SUPPORT_USB_INT */
+#endif /* CONFIG_RTL8710B */
+
+#ifdef CONFIG_RTL8192F
+void rtl8192fu_set_hw_type(struct dvobj_priv *pdvobj);
+void rtl8192fu_xmit_tasklet(void *priv);
+#ifdef CONFIG_SUPPORT_USB_INT
+void rtl8192fu_interrupt_handler(_adapter *padapter, u16 pkt_len, u8 *pbuf);
+#endif /* CONFIG_SUPPORT_USB_INT */
+#endif /* CONFIG_RTL8192F */
+
+enum RTW_USB_SPEED {
+	RTW_USB_SPEED_UNKNOWN	= 0,
+	RTW_USB_SPEED_1_1	= 1,
+	RTW_USB_SPEED_2		= 2,
+	RTW_USB_SPEED_3		= 3,
+};
+
+#define IS_FULL_SPEED_USB(Adapter)	(adapter_to_dvobj(Adapter)->usb_speed == RTW_USB_SPEED_1_1)
+#define IS_HIGH_SPEED_USB(Adapter)	(adapter_to_dvobj(Adapter)->usb_speed == RTW_USB_SPEED_2)
+#define IS_SUPER_SPEED_USB(Adapter)	(adapter_to_dvobj(Adapter)->usb_speed == RTW_USB_SPEED_3)
+
+#define USB_SUPER_SPEED_BULK_SIZE	1024	/* usb 3.0 */
+#define USB_HIGH_SPEED_BULK_SIZE	512		/* usb 2.0 */
+#define USB_FULL_SPEED_BULK_SIZE	64		/* usb 1.1 */
+
+static inline u8 rtw_usb_bulk_size_boundary(_adapter *padapter, int buf_len)
+{
+	u8 rst = _TRUE;
+
+	if (IS_SUPER_SPEED_USB(padapter))
+		rst = (0 == (buf_len) % USB_SUPER_SPEED_BULK_SIZE) ? _TRUE : _FALSE;
+	else if (IS_HIGH_SPEED_USB(padapter))
+		rst = (0 == (buf_len) % USB_HIGH_SPEED_BULK_SIZE) ? _TRUE : _FALSE;
+	else
+		rst = (0 == (buf_len) % USB_FULL_SPEED_BULK_SIZE) ? _TRUE : _FALSE;
+	return rst;
+}
+
+
+#endif /* __USB_OPS_H_ */
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/include/usb_ops_linux.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/usb_ops_linux.h
--- linux-5.6.3/3rdparty/rtl8821ce/include/usb_ops_linux.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/usb_ops_linux.h	2020-04-10 16:35:06.852661748 +0300
@@ -0,0 +1,98 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#ifndef __USB_OPS_LINUX_H__
+#define __USB_OPS_LINUX_H__
+
+#define VENDOR_CMD_MAX_DATA_LEN	254
+#define FW_START_ADDRESS	0x1000
+
+#define RTW_USB_CONTROL_MSG_TIMEOUT_TEST	10/* ms */
+#define RTW_USB_CONTROL_MSG_TIMEOUT	500/* ms */
+
+#define RECV_BULK_IN_ADDR		0x80/* assign by drv, not real address */
+#define RECV_INT_IN_ADDR		0x81/* assign by drv, not real address */
+
+#define INTERRUPT_MSG_FORMAT_LEN 60
+
+#if defined(CONFIG_VENDOR_REQ_RETRY) && defined(CONFIG_USB_VENDOR_REQ_MUTEX)
+	/* vendor req retry should be in the situation when each vendor req is atomically submitted from others */
+	#define MAX_USBCTRL_VENDORREQ_TIMES	10
+#else
+	#define MAX_USBCTRL_VENDORREQ_TIMES	1
+#endif
+
+#define RTW_USB_BULKOUT_TIMEOUT	5000/* ms */
+
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 5, 0)) || (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 18))
+#define _usbctrl_vendorreq_async_callback(urb, regs)	_usbctrl_vendorreq_async_callback(urb)
+#define usb_bulkout_zero_complete(purb, regs)	usb_bulkout_zero_complete(purb)
+#define usb_write_mem_complete(purb, regs)	usb_write_mem_complete(purb)
+#define usb_write_port_complete(purb, regs)	usb_write_port_complete(purb)
+#define usb_read_port_complete(purb, regs)	usb_read_port_complete(purb)
+#define usb_read_interrupt_complete(purb, regs)	usb_read_interrupt_complete(purb)
+#endif
+
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 12))
+#define rtw_usb_control_msg(dev, pipe, request, requesttype, value, index, data, size, timeout_ms) \
+	usb_control_msg((dev), (pipe), (request), (requesttype), (value), (index), (data), (size), (timeout_ms))
+#define rtw_usb_bulk_msg(usb_dev, pipe, data, len, actual_length, timeout_ms) \
+	usb_bulk_msg((usb_dev), (pipe), (data), (len), (actual_length), (timeout_ms))
+#else
+#define rtw_usb_control_msg(dev, pipe, request, requesttype, value, index, data, size, timeout_ms) \
+	usb_control_msg((dev), (pipe), (request), (requesttype), (value), (index), (data), (size), \
+		((timeout_ms) == 0) || ((timeout_ms) * HZ / 1000 > 0) ? ((timeout_ms) * HZ / 1000) : 1)
+#define rtw_usb_bulk_msg(usb_dev, pipe, data, len, actual_length, timeout_ms) \
+	usb_bulk_msg((usb_dev), (pipe), (data), (len), (actual_length), \
+		((timeout_ms) == 0) || ((timeout_ms) * HZ / 1000 > 0) ? ((timeout_ms) * HZ / 1000) : 1)
+#endif
+
+
+#ifdef CONFIG_USB_SUPPORT_ASYNC_VDN_REQ
+int usb_async_write8(struct intf_hdl *pintfhdl, u32 addr, u8 val);
+int usb_async_write16(struct intf_hdl *pintfhdl, u32 addr, u16 val);
+int usb_async_write32(struct intf_hdl *pintfhdl, u32 addr, u32 val);
+#endif /* CONFIG_USB_SUPPORT_ASYNC_VDN_REQ */
+
+unsigned int ffaddr2pipehdl(struct dvobj_priv *pdvobj, u32 addr);
+
+void usb_read_mem(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *rmem);
+void usb_write_mem(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *wmem);
+
+void usb_read_port_cancel(struct intf_hdl *pintfhdl);
+
+u32 usb_write_port(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *wmem);
+void usb_write_port_cancel(struct intf_hdl *pintfhdl);
+
+int usbctrl_vendorreq(struct intf_hdl *pintfhdl, u8 request, u16 value, u16 index, void *pdata, u16 len, u8 requesttype);
+#ifdef CONFIG_USB_SUPPORT_ASYNC_VDN_REQ
+int _usbctrl_vendorreq_async_write(struct usb_device *udev, u8 request,
+		u16 value, u16 index, void *pdata, u16 len, u8 requesttype);
+#endif /* CONFIG_USB_SUPPORT_ASYNC_VDN_REQ */
+
+u8 usb_read8(struct intf_hdl *pintfhdl, u32 addr);
+u16 usb_read16(struct intf_hdl *pintfhdl, u32 addr);
+u32 usb_read32(struct intf_hdl *pintfhdl, u32 addr);
+int usb_write8(struct intf_hdl *pintfhdl, u32 addr, u8 val);
+int usb_write16(struct intf_hdl *pintfhdl, u32 addr, u16 val);
+int usb_write32(struct intf_hdl *pintfhdl, u32 addr, u32 val);
+int usb_writeN(struct intf_hdl *pintfhdl, u32 addr, u32 length, u8 *pdata);
+u32 usb_read_port(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *rmem);
+void usb_recv_tasklet(void *priv);
+
+#ifdef CONFIG_USB_INTERRUPT_IN_PIPE
+void usb_read_interrupt_complete(struct urb *purb, struct pt_regs *regs);
+u32 usb_read_interrupt(struct intf_hdl *pintfhdl, u32 addr);
+#endif
+#endif
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/include/usb_osintf.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/usb_osintf.h
--- linux-5.6.3/3rdparty/rtl8821ce/include/usb_osintf.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/usb_osintf.h	2020-04-10 16:35:06.853661795 +0300
@@ -0,0 +1,26 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#ifndef __USB_OSINTF_H
+#define __USB_OSINTF_H
+
+#include <usb_vendor_req.h>
+
+#define USBD_HALTED(Status) ((ULONG)(Status) >> 30 == 3)
+
+
+u8 usbvendorrequest(struct dvobj_priv *pdvobjpriv, RT_USB_BREQUEST brequest, RT_USB_WVALUE wvalue, u8 windex, void *data, u8 datalen, u8 isdirectionin);
+
+
+#endif
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/include/usb_vendor_req.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/usb_vendor_req.h
--- linux-5.6.3/3rdparty/rtl8821ce/include/usb_vendor_req.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/usb_vendor_req.h	2020-04-10 16:35:06.853661795 +0300
@@ -0,0 +1,56 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#ifndef _USB_VENDOR_REQUEST_H_
+#define _USB_VENDOR_REQUEST_H_
+
+/* 4	Set/Get Register related wIndex/Data */
+#define	RT_USB_RESET_MASK_OFF		0
+#define	RT_USB_RESET_MASK_ON		1
+#define	RT_USB_SLEEP_MASK_OFF		0
+#define	RT_USB_SLEEP_MASK_ON		1
+#define	RT_USB_LDO_ON				1
+#define	RT_USB_LDO_OFF				0
+
+/* 4	Set/Get SYSCLK related	wValue or Data */
+#define	RT_USB_SYSCLK_32KHZ		0
+#define	RT_USB_SYSCLK_40MHZ		1
+#define	RT_USB_SYSCLK_60MHZ		2
+
+
+typedef enum _RT_USB_BREQUEST {
+	RT_USB_SET_REGISTER		= 1,
+	RT_USB_SET_SYSCLK		= 2,
+	RT_USB_GET_SYSCLK		= 3,
+	RT_USB_GET_REGISTER		= 4
+} RT_USB_BREQUEST;
+
+
+typedef enum _RT_USB_WVALUE {
+	RT_USB_RESET_MASK	=	1,
+	RT_USB_SLEEP_MASK	=	2,
+	RT_USB_USB_HRCPWM	=	3,
+	RT_USB_LDO			=	4,
+	RT_USB_BOOT_TYPE	=	5
+} RT_USB_WVALUE;
+
+
+#if 0
+BOOLEAN usbvendorrequest(PCE_USB_DEVICE	CEdevice, RT_USB_BREQUEST bRequest, RT_USB_WVALUE wValue, UCHAR wIndex, PVOID Data, UCHAR DataLength, BOOLEAN isDirectionIn);
+BOOLEAN CEusbGetStatusRequest(PCE_USB_DEVICE CEdevice, IN USHORT Op, IN USHORT Index, PVOID Data);
+BOOLEAN CEusbFeatureRequest(PCE_USB_DEVICE CEdevice, IN USHORT Op, IN USHORT FeatureSelector, IN USHORT Index);
+BOOLEAN CEusbGetDescriptorRequest(PCE_USB_DEVICE CEdevice, IN short urbLength, IN UCHAR DescriptorType, IN UCHAR Index, IN USHORT LanguageId, IN PVOID  TransferBuffer, IN ULONG TransferBufferLength);
+#endif
+
+#endif
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/include/wifi.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/wifi.h
--- linux-5.6.3/3rdparty/rtl8821ce/include/wifi.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/wifi.h	2020-04-10 16:35:06.853661795 +0300
@@ -0,0 +1,1418 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#ifndef _WIFI_H_
+#define _WIFI_H_
+
+
+#ifndef BIT
+#define BIT(x)	(1 << (x))
+#endif
+
+
+#define WLAN_ETHHDR_LEN		14
+#define WLAN_ETHADDR_LEN	6
+#define WLAN_IEEE_OUI_LEN	3
+#define WLAN_ADDR_LEN		6
+#define WLAN_CRC_LEN		4
+#define WLAN_BSSID_LEN		6
+#define WLAN_BSS_TS_LEN		8
+#define WLAN_HDR_A3_LEN		24
+#define WLAN_HDR_A4_LEN		30
+#define WLAN_HDR_A3_QOS_LEN	26
+#define WLAN_HDR_A4_QOS_LEN	32
+#define WLAN_SSID_MAXLEN	32
+#define WLAN_DATA_MAXLEN	2312
+
+#define WLAN_A3_PN_OFFSET	24
+#define WLAN_A4_PN_OFFSET	30
+
+#define WLAN_MIN_ETHFRM_LEN	60
+#define WLAN_MAX_ETHFRM_LEN	1514
+#define WLAN_ETHHDR_LEN		14
+#define WLAN_WMM_LEN		24
+#define VENDOR_NAME_LEN		20
+
+#ifdef CONFIG_APPEND_VENDOR_IE_ENABLE
+#define WLAN_MAX_VENDOR_IE_LEN 255
+#define WLAN_MAX_VENDOR_IE_NUM 5
+#define WIFI_BEACON_VENDOR_IE_BIT BIT(0)
+#define WIFI_PROBEREQ_VENDOR_IE_BIT BIT(1)
+#define WIFI_PROBERESP_VENDOR_IE_BIT BIT(2)
+#define WIFI_ASSOCREQ_VENDOR_IE_BIT BIT(3)
+#define WIFI_ASSOCRESP_VENDOR_IE_BIT BIT(4)
+#endif
+
+#define P80211CAPTURE_VERSION	0x80211001
+
+/* This value is tested by WiFi 11n Test Plan 5.2.3.
+ * This test verifies the WLAN NIC can update the NAV through sending the CTS with large duration. */
+#define	WiFiNavUpperUs				30000	/* 30 ms */
+
+#ifdef GREEN_HILL
+#pragma pack(1)
+#endif
+
+enum WIFI_FRAME_TYPE {
+	WIFI_MGT_TYPE  =	(0),
+	WIFI_CTRL_TYPE =	(BIT(2)),
+	WIFI_DATA_TYPE =	(BIT(3)),
+	WIFI_QOS_DATA_TYPE	= (BIT(7) | BIT(3)),	/* !< QoS Data	 */
+};
+
+enum WIFI_FRAME_SUBTYPE {
+
+	/* below is for mgt frame */
+	WIFI_ASSOCREQ       = (0 | WIFI_MGT_TYPE),
+	WIFI_ASSOCRSP       = (BIT(4) | WIFI_MGT_TYPE),
+	WIFI_REASSOCREQ     = (BIT(5) | WIFI_MGT_TYPE),
+	WIFI_REASSOCRSP     = (BIT(5) | BIT(4) | WIFI_MGT_TYPE),
+	WIFI_PROBEREQ       = (BIT(6) | WIFI_MGT_TYPE),
+	WIFI_PROBERSP       = (BIT(6) | BIT(4) | WIFI_MGT_TYPE),
+	WIFI_BEACON         = (BIT(7) | WIFI_MGT_TYPE),
+	WIFI_ATIM           = (BIT(7) | BIT(4) | WIFI_MGT_TYPE),
+	WIFI_DISASSOC       = (BIT(7) | BIT(5) | WIFI_MGT_TYPE),
+	WIFI_AUTH           = (BIT(7) | BIT(5) | BIT(4) | WIFI_MGT_TYPE),
+	WIFI_DEAUTH         = (BIT(7) | BIT(6) | WIFI_MGT_TYPE),
+	WIFI_ACTION         = (BIT(7) | BIT(6) | BIT(4) | WIFI_MGT_TYPE),
+	WIFI_ACTION_NOACK = (BIT(7) | BIT(6) | BIT(5) | WIFI_MGT_TYPE),
+
+	/* below is for control frame */
+	WIFI_BF_REPORT_POLL = (BIT(6) | WIFI_CTRL_TYPE),
+	WIFI_NDPA         = (BIT(6) | BIT(4) | WIFI_CTRL_TYPE),
+	WIFI_BAR            = (BIT(7) | WIFI_CTRL_TYPE),
+	WIFI_PSPOLL         = (BIT(7) | BIT(5) | WIFI_CTRL_TYPE),
+	WIFI_RTS            = (BIT(7) | BIT(5) | BIT(4) | WIFI_CTRL_TYPE),
+	WIFI_CTS            = (BIT(7) | BIT(6) | WIFI_CTRL_TYPE),
+	WIFI_ACK            = (BIT(7) | BIT(6) | BIT(4) | WIFI_CTRL_TYPE),
+	WIFI_CFEND          = (BIT(7) | BIT(6) | BIT(5) | WIFI_CTRL_TYPE),
+	WIFI_CFEND_CFACK    = (BIT(7) | BIT(6) | BIT(5) | BIT(4) | WIFI_CTRL_TYPE),
+
+	/* below is for data frame */
+	WIFI_DATA           = (0 | WIFI_DATA_TYPE),
+	WIFI_DATA_CFACK     = (BIT(4) | WIFI_DATA_TYPE),
+	WIFI_DATA_CFPOLL    = (BIT(5) | WIFI_DATA_TYPE),
+	WIFI_DATA_CFACKPOLL = (BIT(5) | BIT(4) | WIFI_DATA_TYPE),
+	WIFI_DATA_NULL      = (BIT(6) | WIFI_DATA_TYPE),
+	WIFI_CF_ACK         = (BIT(6) | BIT(4) | WIFI_DATA_TYPE),
+	WIFI_CF_POLL        = (BIT(6) | BIT(5) | WIFI_DATA_TYPE),
+	WIFI_CF_ACKPOLL     = (BIT(6) | BIT(5) | BIT(4) | WIFI_DATA_TYPE),
+	WIFI_QOS_DATA_NULL	= (BIT(6) | WIFI_QOS_DATA_TYPE),
+};
+
+enum WIFI_REASON_CODE	{
+	_RSON_RESERVED_					= 0,
+	_RSON_UNSPECIFIED_				= 1,
+	_RSON_AUTH_NO_LONGER_VALID_		= 2,
+	_RSON_DEAUTH_STA_LEAVING_		= 3,
+	_RSON_INACTIVITY_				= 4,
+	_RSON_UNABLE_HANDLE_			= 5,
+	_RSON_CLS2_						= 6,
+	_RSON_CLS3_						= 7,
+	_RSON_DISAOC_STA_LEAVING_		= 8,
+	_RSON_ASOC_NOT_AUTH_			= 9,
+
+	/* WPA reason */
+	_RSON_INVALID_IE_				= 13,
+	_RSON_MIC_FAILURE_				= 14,
+	_RSON_4WAY_HNDSHK_TIMEOUT_		= 15,
+	_RSON_GROUP_KEY_UPDATE_TIMEOUT_	= 16,
+	_RSON_DIFF_IE_					= 17,
+	_RSON_MLTCST_CIPHER_NOT_VALID_	= 18,
+	_RSON_UNICST_CIPHER_NOT_VALID_	= 19,
+	_RSON_AKMP_NOT_VALID_			= 20,
+	_RSON_UNSUPPORT_RSNE_VER_		= 21,
+	_RSON_INVALID_RSNE_CAP_			= 22,
+	_RSON_IEEE_802DOT1X_AUTH_FAIL_	= 23,
+
+	/* belowing are Realtek definition */
+	_RSON_PMK_NOT_AVAILABLE_		= 24,
+	_RSON_TDLS_TEAR_TOOFAR_			= 25,
+	_RSON_TDLS_TEAR_UN_RSN_			= 26,
+};
+
+/* Reason codes (IEEE 802.11-2007, 7.3.1.7, Table 7-22) */
+#if 0
+#define WLAN_REASON_UNSPECIFIED 1
+#define WLAN_REASON_PREV_AUTH_NOT_VALID 2
+#define WLAN_REASON_DEAUTH_LEAVING 3
+#define WLAN_REASON_DISASSOC_DUE_TO_INACTIVITY 4
+#define WLAN_REASON_DISASSOC_AP_BUSY 5
+#define WLAN_REASON_CLASS2_FRAME_FROM_NONAUTH_STA 6
+#define WLAN_REASON_CLASS3_FRAME_FROM_NONASSOC_STA 7
+#define WLAN_REASON_DISASSOC_STA_HAS_LEFT 8
+#define WLAN_REASON_STA_REQ_ASSOC_WITHOUT_AUTH 9
+#endif
+/* IEEE 802.11h */
+#define WLAN_REASON_PWR_CAPABILITY_NOT_VALID 10
+#define WLAN_REASON_SUPPORTED_CHANNEL_NOT_VALID 11
+#if 0
+/* IEEE 802.11i */
+#define WLAN_REASON_INVALID_IE 13
+#define WLAN_REASON_MICHAEL_MIC_FAILURE 14
+#define WLAN_REASON_4WAY_HANDSHAKE_TIMEOUT 15
+#define WLAN_REASON_GROUP_KEY_UPDATE_TIMEOUT 16
+#define WLAN_REASON_IE_IN_4WAY_DIFFERS 17
+#define WLAN_REASON_GROUP_CIPHER_NOT_VALID 18
+#define WLAN_REASON_PAIRWISE_CIPHER_NOT_VALID 19
+#define WLAN_REASON_AKMP_NOT_VALID 20
+#define WLAN_REASON_UNSUPPORTED_RSN_IE_VERSION 21
+#define WLAN_REASON_INVALID_RSN_IE_CAPAB 22
+#define WLAN_REASON_IEEE_802_1X_AUTH_FAILED 23
+#define WLAN_REASON_CIPHER_SUITE_REJECTED 24
+#endif
+
+enum WIFI_STATUS_CODE {
+	_STATS_SUCCESSFUL_			= 0,
+	_STATS_FAILURE_				= 1,
+	_STATS_SEC_DISABLED_			= 5,
+	_STATS_NOT_IN_SAME_BSS_		= 7,
+	_STATS_CAP_FAIL_			= 10,
+	_STATS_NO_ASOC_				= 11,
+	_STATS_OTHER_				= 12,
+	_STATS_NO_SUPP_ALG_			= 13,
+	_STATS_OUT_OF_AUTH_SEQ_		= 14,
+	_STATS_CHALLENGE_FAIL_		= 15,
+	_STATS_AUTH_TIMEOUT_		= 16,
+	_STATS_UNABLE_HANDLE_STA_	= 17,
+	_STATS_RATE_FAIL_			= 18,
+	_STATS_REFUSED_TEMPORARILY_ = 30,
+	_STATS_DECLINE_REQ_			= 37,
+	_STATS_INVALID_PARAMETERS_	= 38,
+	_STATS_INVALID_RSNIE_			= 72,
+};
+
+/* Status codes (IEEE 802.11-2007, 7.3.1.9, Table 7-23) */
+#if 0
+#define WLAN_STATUS_SUCCESS 0
+#define WLAN_STATUS_UNSPECIFIED_FAILURE 1
+#define WLAN_STATUS_CAPS_UNSUPPORTED 10
+#define WLAN_STATUS_REASSOC_NO_ASSOC 11
+#define WLAN_STATUS_ASSOC_DENIED_UNSPEC 12
+#define WLAN_STATUS_NOT_SUPPORTED_AUTH_ALG 13
+#define WLAN_STATUS_UNKNOWN_AUTH_TRANSACTION 14
+#define WLAN_STATUS_CHALLENGE_FAIL 15
+#define WLAN_STATUS_AUTH_TIMEOUT 16
+#define WLAN_STATUS_AP_UNABLE_TO_HANDLE_NEW_STA 17
+#define WLAN_STATUS_ASSOC_DENIED_RATES 18
+#endif
+/* entended */
+/* IEEE 802.11b */
+#define WLAN_STATUS_ASSOC_DENIED_NOSHORT 19
+#define WLAN_STATUS_ASSOC_DENIED_NOPBCC 20
+#define WLAN_STATUS_ASSOC_DENIED_NOAGILITY 21
+/* IEEE 802.11h */
+#define WLAN_STATUS_SPEC_MGMT_REQUIRED 22
+#define WLAN_STATUS_PWR_CAPABILITY_NOT_VALID 23
+#define WLAN_STATUS_SUPPORTED_CHANNEL_NOT_VALID 24
+/* IEEE 802.11g */
+#define WLAN_STATUS_ASSOC_DENIED_NO_SHORT_SLOT_TIME 25
+#define WLAN_STATUS_ASSOC_DENIED_NO_ER_PBCC 26
+#define WLAN_STATUS_ASSOC_DENIED_NO_DSSS_OFDM 27
+/* IEEE 802.11w */
+#define WLAN_STATUS_ASSOC_REJECTED_TEMPORARILY 30
+#define WLAN_STATUS_ROBUST_MGMT_FRAME_POLICY_VIOLATION 31
+/* IEEE 802.11i */
+#define WLAN_STATUS_INVALID_IE 40
+#define WLAN_STATUS_GROUP_CIPHER_NOT_VALID 41
+#define WLAN_STATUS_PAIRWISE_CIPHER_NOT_VALID 42
+#define WLAN_STATUS_AKMP_NOT_VALID 43
+#define WLAN_STATUS_UNSUPPORTED_RSN_IE_VERSION 44
+#define WLAN_STATUS_INVALID_RSN_IE_CAPAB 45
+#define WLAN_STATUS_CIPHER_REJECTED_PER_POLICY 46
+#define WLAN_STATUS_TS_NOT_CREATED 47
+#define WLAN_STATUS_DIRECT_LINK_NOT_ALLOWED 48
+#define WLAN_STATUS_DEST_STA_NOT_PRESENT 49
+#define WLAN_STATUS_DEST_STA_NOT_QOS_STA 50
+#define WLAN_STATUS_ASSOC_DENIED_LISTEN_INT_TOO_LARGE 51
+/* IEEE 802.11r */
+#define WLAN_STATUS_INVALID_FT_ACTION_FRAME_COUNT 52
+#define WLAN_STATUS_INVALID_PMKID 53
+#define WLAN_STATUS_INVALID_MDIE 54
+#define WLAN_STATUS_INVALID_FTIE 55
+
+
+enum WIFI_REG_DOMAIN {
+	DOMAIN_FCC		= 1,
+	DOMAIN_IC		= 2,
+	DOMAIN_ETSI		= 3,
+	DOMAIN_SPAIN	= 4,
+	DOMAIN_FRANCE	= 5,
+	DOMAIN_MKK		= 6,
+	DOMAIN_ISRAEL	= 7,
+	DOMAIN_MKK1		= 8,
+	DOMAIN_MKK2		= 9,
+	DOMAIN_MKK3		= 10,
+	DOMAIN_MAX
+};
+
+#define _TO_DS_		BIT(8)
+#define _FROM_DS_	BIT(9)
+#define _MORE_FRAG_	BIT(10)
+#define _RETRY_		BIT(11)
+#define _PWRMGT_	BIT(12)
+#define _MORE_DATA_	BIT(13)
+#define _PRIVACY_	BIT(14)
+#define _ORDER_			BIT(15)
+
+#define SetToDs(pbuf)	\
+	do	{	\
+		*(unsigned short *)(pbuf) |= cpu_to_le16(_TO_DS_); \
+	} while (0)
+
+#define GetToDs(pbuf)	(((*(unsigned short *)(pbuf)) & le16_to_cpu(_TO_DS_)) != 0)
+
+#define ClearToDs(pbuf)	\
+	do	{	\
+		*(unsigned short *)(pbuf) &= (~cpu_to_le16(_TO_DS_)); \
+	} while (0)
+
+#define SetFrDs(pbuf)	\
+	do	{	\
+		*(unsigned short *)(pbuf) |= cpu_to_le16(_FROM_DS_); \
+	} while (0)
+
+#define GetFrDs(pbuf)	(((*(unsigned short *)(pbuf)) & le16_to_cpu(_FROM_DS_)) != 0)
+
+#define ClearFrDs(pbuf)	\
+	do	{	\
+		*(unsigned short *)(pbuf) &= (~cpu_to_le16(_FROM_DS_)); \
+	} while (0)
+
+#define get_tofr_ds(pframe)	((GetToDs(pframe) << 1) | GetFrDs(pframe))
+
+
+#define SetMFrag(pbuf)	\
+	do	{	\
+		*(unsigned short *)(pbuf) |= cpu_to_le16(_MORE_FRAG_); \
+	} while (0)
+
+#define GetMFrag(pbuf)	(((*(unsigned short *)(pbuf)) & le16_to_cpu(_MORE_FRAG_)) != 0)
+
+#define ClearMFrag(pbuf)	\
+	do	{	\
+		*(unsigned short *)(pbuf) &= (~cpu_to_le16(_MORE_FRAG_)); \
+	} while (0)
+
+#define SetRetry(pbuf)	\
+	do	{	\
+		*(unsigned short *)(pbuf) |= cpu_to_le16(_RETRY_); \
+	} while (0)
+
+#define GetRetry(pbuf)	(((*(unsigned short *)(pbuf)) & le16_to_cpu(_RETRY_)) != 0)
+
+#define ClearRetry(pbuf)	\
+	do	{	\
+		*(unsigned short *)(pbuf) &= (~cpu_to_le16(_RETRY_)); \
+	} while (0)
+
+#define SetPwrMgt(pbuf)	\
+	do	{	\
+		*(unsigned short *)(pbuf) |= cpu_to_le16(_PWRMGT_); \
+	} while (0)
+
+#define GetPwrMgt(pbuf)	(((*(unsigned short *)(pbuf)) & le16_to_cpu(_PWRMGT_)) != 0)
+
+#define ClearPwrMgt(pbuf)	\
+	do	{	\
+		*(unsigned short *)(pbuf) &= (~cpu_to_le16(_PWRMGT_)); \
+	} while (0)
+
+#define SetMData(pbuf)	\
+	do	{	\
+		*(unsigned short *)(pbuf) |= cpu_to_le16(_MORE_DATA_); \
+	} while (0)
+
+#define GetMData(pbuf)	(((*(unsigned short *)(pbuf)) & le16_to_cpu(_MORE_DATA_)) != 0)
+
+#define ClearMData(pbuf)	\
+	do	{	\
+		*(unsigned short *)(pbuf) &= (~cpu_to_le16(_MORE_DATA_)); \
+	} while (0)
+
+#define SetPrivacy(pbuf)	\
+	do	{	\
+		*(unsigned short *)(pbuf) |= cpu_to_le16(_PRIVACY_); \
+	} while (0)
+
+#define GetPrivacy(pbuf)	(((*(unsigned short *)(pbuf)) & le16_to_cpu(_PRIVACY_)) != 0)
+
+#define ClearPrivacy(pbuf)	\
+	do	{	\
+		*(unsigned short *)(pbuf) &= (~cpu_to_le16(_PRIVACY_)); \
+	} while (0)
+
+
+#define GetOrder(pbuf)	(((*(unsigned short *)(pbuf)) & le16_to_cpu(_ORDER_)) != 0)
+
+#define GetFrameType(pbuf)	(le16_to_cpu(*(unsigned short *)(pbuf)) & (BIT(3) | BIT(2)))
+
+#define SetFrameType(pbuf, type)	\
+	do {	\
+		*(unsigned short *)(pbuf) &= __constant_cpu_to_le16(~(BIT(3) | BIT(2))); \
+		*(unsigned short *)(pbuf) |= __constant_cpu_to_le16(type); \
+	} while (0)
+
+#define get_frame_sub_type(pbuf)	(cpu_to_le16(*(unsigned short *)(pbuf)) & (BIT(7) | BIT(6) | BIT(5) | BIT(4) | BIT(3) | BIT(2)))
+
+
+#define set_frame_sub_type(pbuf, type) \
+	do {    \
+		*(unsigned short *)(pbuf) &= cpu_to_le16(~(BIT(7) | BIT(6) | BIT(5) | BIT(4) | BIT(3) | BIT(2))); \
+		*(unsigned short *)(pbuf) |= cpu_to_le16(type); \
+	} while (0)
+
+
+#define GetSequence(pbuf)	(cpu_to_le16(*(unsigned short *)((SIZE_PTR)(pbuf) + 22)) >> 4)
+
+#define GetFragNum(pbuf)	(cpu_to_le16(*(unsigned short *)((SIZE_PTR)(pbuf) + 22)) & 0x0f)
+
+#define GetTupleCache(pbuf)	(cpu_to_le16(*(unsigned short *)((SIZE_PTR)(pbuf) + 22)))
+
+#define SetFragNum(pbuf, num) \
+	do {    \
+		*(unsigned short *)((SIZE_PTR)(pbuf) + 22) = \
+			((*(unsigned short *)((SIZE_PTR)(pbuf) + 22)) & le16_to_cpu(~(0x000f))) | \
+				cpu_to_le16(0x0f & (num));     \
+	} while (0)
+
+#define SetSeqNum(pbuf, num) \
+	do {    \
+		*(unsigned short *)((SIZE_PTR)(pbuf) + 22) = \
+			((*(unsigned short *)((SIZE_PTR)(pbuf) + 22)) & le16_to_cpu((unsigned short)~0xfff0)) | \
+			le16_to_cpu((unsigned short)(0xfff0 & (num << 4))); \
+	} while (0)
+
+#define set_duration(pbuf, dur) \
+	do {    \
+		*(unsigned short *)((SIZE_PTR)(pbuf) + 2) = cpu_to_le16(0xffff & (dur)); \
+	} while (0)
+
+
+/* QoS control field */
+#define SetPriority(qc, tid)	SET_BITS_TO_LE_2BYTE(((u8 *)(qc)), 0, 4, tid)
+#define SetEOSP(qc, eosp)		SET_BITS_TO_LE_2BYTE(((u8 *)(qc)), 4, 1, eosp)
+#define SetAckpolicy(qc, ack)	SET_BITS_TO_LE_2BYTE(((u8 *)(qc)), 5, 2, ack)
+#define SetAMsdu(qc, amsdu)		SET_BITS_TO_LE_2BYTE(((u8 *)(qc)), 7, 1, amsdu)
+
+#define GetPriority(qc)		LE_BITS_TO_2BYTE(((u8 *)(qc)), 0, 4)
+#define GetEOSP(qc)			LE_BITS_TO_2BYTE(((u8 *)(qc)), 4, 1)
+#define GetAckpolicy(qc)	LE_BITS_TO_2BYTE(((u8 *)(qc)), 5, 2)
+#define GetAMsdu(qc)		LE_BITS_TO_2BYTE(((u8 *)(qc)), 7, 1)
+
+/* QoS control field (MSTA only) */
+#define set_mctrl_present(qc, p)	SET_BITS_TO_LE_2BYTE(((u8 *)(qc)), 8, 1, p)
+#define set_mps_lv(qc, lv)			SET_BITS_TO_LE_2BYTE(((u8 *)(qc)), 9, 1, lv)
+#define set_rspi(qc, rspi)			SET_BITS_TO_LE_2BYTE(((u8 *)(qc)), 10, 1, rspi)
+
+#define get_mctrl_present(qc)	LE_BITS_TO_2BYTE(((u8 *)(qc)), 8, 1)
+#define get_mps_lv(qc)			LE_BITS_TO_2BYTE(((u8 *)(qc)), 9, 1)
+#define get_rspi(qc)			LE_BITS_TO_2BYTE(((u8 *)(qc)), 10, 1)
+
+
+#define GetAid(pbuf)	(cpu_to_le16(*(unsigned short *)((SIZE_PTR)(pbuf) + 2)) & 0x3fff)
+
+#define GetTid(pbuf)	(cpu_to_le16(*(unsigned short *)((SIZE_PTR)(pbuf) + (((GetToDs(pbuf)<<1) | GetFrDs(pbuf)) == 3 ? 30 : 24))) & 0x000f)
+
+#define GetAddr1Ptr(pbuf)	((unsigned char *)((SIZE_PTR)(pbuf) + 4))
+
+#define get_addr2_ptr(pbuf)	((unsigned char *)((SIZE_PTR)(pbuf) + 10))
+
+#define GetAddr3Ptr(pbuf)	((unsigned char *)((SIZE_PTR)(pbuf) + 16))
+
+#define GetAddr4Ptr(pbuf)	((unsigned char *)((SIZE_PTR)(pbuf) + 24))
+
+
+#define MacAddr_isBcst(addr) \
+	(\
+	 ((addr[0] == 0xff) && (addr[1] == 0xff) && \
+	  (addr[2] == 0xff) && (addr[3] == 0xff) && \
+	  (addr[4] == 0xff) && (addr[5] == 0xff)) ? _TRUE : _FALSE \
+	)
+
+__inline static int IS_MCAST(const u8 *da)
+{
+	if ((*da) & 0x01)
+		return _TRUE;
+	else
+		return _FALSE;
+}
+
+__inline static unsigned char *get_ra(unsigned char *pframe)
+{
+	unsigned char	*ra;
+	ra = GetAddr1Ptr(pframe);
+	return ra;
+}
+__inline static unsigned char *get_ta(unsigned char *pframe)
+{
+	unsigned char	*ta;
+	ta = get_addr2_ptr(pframe);
+	return ta;
+}
+
+/* can't apply to mesh mode */
+__inline static unsigned char *get_da(unsigned char *pframe)
+{
+	unsigned char	*da;
+	unsigned int	to_fr_ds	= (GetToDs(pframe) << 1) | GetFrDs(pframe);
+
+	switch (to_fr_ds) {
+	case 0x00:	/* ToDs=0, FromDs=0 */
+		da = GetAddr1Ptr(pframe);
+		break;
+	case 0x01:	/* ToDs=0, FromDs=1 */
+		da = GetAddr1Ptr(pframe);
+		break;
+	case 0x02:	/* ToDs=1, FromDs=0 */
+		da = GetAddr3Ptr(pframe);
+		break;
+	default:	/* ToDs=1, FromDs=1 */
+		da = GetAddr3Ptr(pframe);
+		break;
+	}
+
+	return da;
+}
+
+/* can't apply to mesh mode */
+__inline static unsigned char *get_sa(unsigned char *pframe)
+{
+	unsigned char	*sa;
+	unsigned int	to_fr_ds	= (GetToDs(pframe) << 1) | GetFrDs(pframe);
+
+	switch (to_fr_ds) {
+	case 0x00:	/* ToDs=0, FromDs=0 */
+		sa = get_addr2_ptr(pframe);
+		break;
+	case 0x01:	/* ToDs=0, FromDs=1 */
+		sa = GetAddr3Ptr(pframe);
+		break;
+	case 0x02:	/* ToDs=1, FromDs=0 */
+		sa = get_addr2_ptr(pframe);
+		break;
+	default:	/* ToDs=1, FromDs=1 */
+		sa = GetAddr4Ptr(pframe);
+		break;
+	}
+
+	return sa;
+}
+
+/* can't apply to mesh mode */
+__inline static unsigned char *get_hdr_bssid(unsigned char *pframe)
+{
+	unsigned char	*sa = NULL;
+	unsigned int	to_fr_ds	= (GetToDs(pframe) << 1) | GetFrDs(pframe);
+
+	switch (to_fr_ds) {
+	case 0x00:	/* ToDs=0, FromDs=0 */
+		sa = GetAddr3Ptr(pframe);
+		break;
+	case 0x01:	/* ToDs=0, FromDs=1 */
+		sa = get_addr2_ptr(pframe);
+		break;
+	case 0x02:	/* ToDs=1, FromDs=0 */
+		sa = GetAddr1Ptr(pframe);
+		break;
+	case 0x03:	/* ToDs=1, FromDs=1 */
+		sa = GetAddr1Ptr(pframe);
+		break;
+	}
+
+	return sa;
+}
+
+
+__inline static int IsFrameTypeCtrl(unsigned char *pframe)
+{
+	if (WIFI_CTRL_TYPE == GetFrameType(pframe))
+		return _TRUE;
+	else
+		return _FALSE;
+}
+static inline int IsFrameTypeMgnt(unsigned char *pframe)
+{
+	if (GetFrameType(pframe) == WIFI_MGT_TYPE)
+		return _TRUE;
+	else
+		return _FALSE;
+}
+static inline int IsFrameTypeData(unsigned char *pframe)
+{
+	if (GetFrameType(pframe) == WIFI_DATA_TYPE)
+		return _TRUE;
+	else
+		return _FALSE;
+}
+
+
+/*-----------------------------------------------------------------------------
+			Below is for the security related definition
+------------------------------------------------------------------------------*/
+#define _RESERVED_FRAME_TYPE_	0
+#define _SKB_FRAME_TYPE_		2
+#define _PRE_ALLOCMEM_			1
+#define _PRE_ALLOCHDR_			3
+#define _PRE_ALLOCLLCHDR_		4
+#define _PRE_ALLOCICVHDR_		5
+#define _PRE_ALLOCMICHDR_		6
+
+#define _SIFSTIME_				((priv->pmib->dot11BssType.net_work_type&WIRELESS_11A) ? 16 : 10)
+#define _ACKCTSLNG_				14	/* 14 bytes long, including crclng */
+#define _CRCLNG_				4
+
+#define _ASOCREQ_IE_OFFSET_		4	/* excluding wlan_hdr */
+#define	_ASOCRSP_IE_OFFSET_		6
+#define _REASOCREQ_IE_OFFSET_	10
+#define _REASOCRSP_IE_OFFSET_	6
+#define _PROBEREQ_IE_OFFSET_	0
+#define	_PROBERSP_IE_OFFSET_	12
+#define _AUTH_IE_OFFSET_		6
+#define _DEAUTH_IE_OFFSET_		0
+#define _BEACON_IE_OFFSET_		12
+#define _PUBLIC_ACTION_IE_OFFSET_	8
+
+#define _FIXED_IE_LENGTH_			_BEACON_IE_OFFSET_
+
+#define _SSID_IE_				0
+#define _SUPPORTEDRATES_IE_	1
+#define _DSSET_IE_				3
+#define _TIM_IE_					5
+#define _IBSS_PARA_IE_			6
+#define _COUNTRY_IE_			7
+#define _CHLGETXT_IE_			16
+#define _SUPPORTED_CH_IE_		36
+#define _CH_SWTICH_ANNOUNCE_	37	/* Secondary Channel Offset */
+#define	_MEAS_REQ_IE_		38
+#define	_MEAS_RSP_IE_		39
+#define _RSN_IE_2_				48
+#define _SSN_IE_1_					221
+#define _ERPINFO_IE_			42
+#define _EXT_SUPPORTEDRATES_IE_	50
+
+#define _HT_CAPABILITY_IE_			45
+#define _MDIE_					54
+#define _FTIE_					55
+#define _TIMEOUT_ITVL_IE_			56
+#define _SRC_IE_				59
+#define _HT_EXTRA_INFO_IE_			61
+#define _HT_ADD_INFO_IE_			61 /* _HT_EXTRA_INFO_IE_ */
+#define _WAPI_IE_				68
+#define _EID_RRM_EN_CAP_IE_			70
+
+
+/* #define EID_BSSCoexistence			72 */ /* 20/40 BSS Coexistence
+ * #define EID_BSSIntolerantChlReport	73 */
+#define _RIC_Descriptor_IE_			75
+#ifdef CONFIG_IEEE80211W
+#define _MME_IE_					76 /* 802.11w Management MIC element */
+#endif /* CONFIG_IEEE80211W */
+#define _LINK_ID_IE_					101
+#define _CH_SWITCH_TIMING_		104
+#define _PTI_BUFFER_STATUS_		106
+#define _EXT_CAP_IE_				127
+#define _VENDOR_SPECIFIC_IE_		221
+
+#define	_RESERVED47_				47
+
+typedef	enum _ELEMENT_ID {
+	EID_SsId					= 0, /* service set identifier (0:32) */
+	EID_SupRates				= 1, /* supported rates (1:8) */
+	EID_FHParms				= 2, /* FH parameter set (5) */
+	EID_DSParms				= 3, /* DS parameter set (1) */
+	EID_CFParms				= 4, /* CF parameter set (6) */
+	EID_Tim						= 5, /* Traffic Information Map (4:254) */
+	EID_IbssParms				= 6, /* IBSS parameter set (2) */
+	EID_Country					= 7, /* */
+
+	/* Form 7.3.2: Information elements in 802.11E/D13.0, page 46. */
+	EID_QBSSLoad				= 11,
+	EID_EDCAParms				= 12,
+	EID_TSpec					= 13,
+	EID_TClass					= 14,
+	EID_Schedule				= 15,
+	/*  */
+
+	EID_Ctext					= 16, /* challenge text*/
+	EID_POWER_CONSTRAINT		= 32, /* Power Constraint*/
+
+	/* vivi for WIFITest, 802.11h AP, 20100427 */
+	/* 2010/12/26 MH The definition we can declare always!! */
+	EID_PowerCap				= 33,
+	EID_SupportedChannels		= 36,
+	EID_ChlSwitchAnnounce		= 37,
+
+	EID_MeasureRequest			= 38, /* Measurement Request */
+	EID_MeasureReport			= 39, /* Measurement Report */
+
+	EID_ERPInfo				= 42,
+
+	/* Form 7.3.2: Information elements in 802.11E/D13.0, page 46. */
+	EID_TSDelay				= 43,
+	EID_TCLASProc				= 44,
+	EID_HTCapability			= 45,
+	EID_QoSCap					= 46,
+	/*  */
+
+	EID_WPA2					= 48,
+	EID_ExtSupRates			= 50,
+
+	EID_FTIE					= 55, /* Defined in 802.11r */
+	EID_Timeout				= 56, /* Defined in 802.11r */
+
+	EID_SupRegulatory			= 59, /* Supported Requlatory Classes 802.11y */
+	EID_HTInfo					= 61,
+	EID_SecondaryChnlOffset		= 62,
+
+	EID_BSSCoexistence			= 72, /* 20/40 BSS Coexistence */
+	EID_BSSIntolerantChlReport	= 73,
+	EID_OBSS					= 74, /* Overlapping BSS Scan Parameters */
+
+	EID_LinkIdentifier			= 101, /* Defined in 802.11z */
+	EID_WakeupSchedule		= 102, /* Defined in 802.11z */
+	EID_ChnlSwitchTimeing		= 104, /* Defined in 802.11z */
+	EID_PTIControl				= 105, /* Defined in 802.11z */
+	EID_PUBufferStatus			= 106, /* Defined in 802.11z */
+
+	EID_EXTCapability			= 127, /* Extended Capabilities */
+	/* From S19:Aironet IE and S21:AP IP address IE in CCX v1.13, p16 and p18. */
+	EID_Aironet					= 133, /* 0x85: Aironet Element for Cisco CCX */
+	EID_CiscoIP					= 149, /* 0x95: IP Address IE for Cisco CCX */
+
+	EID_CellPwr					= 150, /* 0x96: Cell Power Limit IE. Ref. 0x96. */
+
+	EID_CCKM					= 156,
+
+	EID_Vendor					= 221, /* 0xDD: Vendor Specific */
+
+	EID_WAPI					= 68,
+	EID_VHTCapability 			= 191, /* Based on 802.11ac D2.0 */
+	EID_VHTOperation 			= 192, /* Based on 802.11ac D2.0 */
+	EID_AID						= 197, /* Based on 802.11ac D4.0 */
+	EID_OpModeNotification		= 199, /* Based on 802.11ac D3.0 */
+} ELEMENT_ID, *PELEMENT_ID;
+
+/* ---------------------------------------------------------------------------
+					Below is the fixed elements...
+-----------------------------------------------------------------------------*/
+#define _AUTH_ALGM_NUM_			2
+#define _AUTH_SEQ_NUM_			2
+#define _BEACON_ITERVAL_		2
+#define _CAPABILITY_			2
+#define _CURRENT_APADDR_		6
+#define _LISTEN_INTERVAL_		2
+#define _RSON_CODE_				2
+#define _ASOC_ID_				2
+#define _STATUS_CODE_			2
+#define _TIMESTAMP_				8
+
+#define AUTH_ODD_TO				0
+#define AUTH_EVEN_TO			1
+
+#define WLAN_ETHCONV_ENCAP		1
+#define WLAN_ETHCONV_RFC1042	2
+#define WLAN_ETHCONV_8021h		3
+
+#define cap_ESS BIT(0)
+#define cap_IBSS BIT(1)
+#define cap_CFPollable BIT(2)
+#define cap_CFRequest BIT(3)
+#define cap_Privacy BIT(4)
+#define cap_ShortPremble BIT(5)
+#define cap_PBCC	BIT(6)
+#define cap_ChAgility	BIT(7)
+#define cap_SpecMgmt	BIT(8)
+#define cap_QoS	BIT(9)
+#define cap_ShortSlot	BIT(10)
+
+/*-----------------------------------------------------------------------------
+				Below is the definition for 802.11i / 802.1x
+------------------------------------------------------------------------------*/
+#define _IEEE8021X_MGT_			1		/* WPA */
+#define _IEEE8021X_PSK_			2		/* WPA with pre-shared key */
+
+#if 0
+#define _NO_PRIVACY_			0
+#define _WEP_40_PRIVACY_		1
+#define _TKIP_PRIVACY_			2
+#define _WRAP_PRIVACY_			3
+#define _CCMP_PRIVACY_			4
+#define _WEP_104_PRIVACY_		5
+#define _WEP_WPA_MIXED_PRIVACY_ 6	/*  WEP + WPA */
+#endif
+
+#define _MME_IE_LENGTH_  18
+
+/*-----------------------------------------------------------------------------
+				Below is the definition for WMM
+------------------------------------------------------------------------------*/
+#define _WMM_IE_Length_				7  /* for WMM STA */
+#define _WMM_Para_Element_Length_		24
+
+
+/*-----------------------------------------------------------------------------
+				Below is the definition for 802.11n
+------------------------------------------------------------------------------*/
+
+/* #ifdef CONFIG_80211N_HT */
+
+#define set_order_bit(pbuf)	\
+		do	{	\
+			*(unsigned short *)(pbuf) |= cpu_to_le16(_ORDER_); \
+		} while (0)
+
+
+
+#define GetOrderBit(pbuf)	(((*(unsigned short *)(pbuf)) & le16_to_cpu(_ORDER_)) != 0)
+
+#define ACT_CAT_VENDOR				0x7F/* 127 */
+
+/**
+ * struct rtw_ieee80211_bar - HT Block Ack Request
+ *
+ * This structure refers to "HT BlockAckReq" as
+ * described in 802.11n draft section 7.2.1.7.1
+ */
+#if defined(PLATFORM_LINUX) || defined(CONFIG_RTL8712FW)
+struct rtw_ieee80211_bar {
+	unsigned short frame_control;
+	unsigned short duration;
+	unsigned char ra[6];
+	unsigned char ta[6];
+	unsigned short control;
+	unsigned short start_seq_num;
+} __attribute__((packed));
+#endif
+
+/* 802.11 BAR control masks */
+#define IEEE80211_BAR_CTRL_ACK_POLICY_NORMAL     0x0000
+#define IEEE80211_BAR_CTRL_CBMTID_COMPRESSED_BA  0x0004
+
+
+#if defined(PLATFORM_LINUX) || defined(CONFIG_RTL8712FW) || defined(PLATFORM_FREEBSD)
+
+
+
+/**
+* struct rtw_ieee80211_ht_cap - HT capabilities
+*
+* This structure refers to "HT capabilities element" as
+* described in 802.11n draft section 7.3.2.52
+*/
+
+struct rtw_ieee80211_ht_cap {
+	unsigned short	cap_info;
+	unsigned char	ampdu_params_info;
+	unsigned char	supp_mcs_set[16];
+	unsigned short	extended_ht_cap_info;
+	unsigned int		tx_BF_cap_info;
+	unsigned char	       antenna_selection_info;
+} __attribute__((packed));
+
+/**
+ * struct rtw_ieee80211_ht_cap - HT additional information
+ *
+ * This structure refers to "HT information element" as
+ * described in 802.11n draft section 7.3.2.53
+ */
+#ifndef CONFIG_IEEE80211_HT_ADDT_INFO
+struct ieee80211_ht_addt_info {
+	unsigned char	control_chan;
+	unsigned char		ht_param;
+	unsigned short	operation_mode;
+	unsigned short	stbc_param;
+	unsigned char		basic_set[16];
+} __attribute__((packed));
+#endif
+
+struct HT_caps_element {
+	union {
+		struct {
+			unsigned short	HT_caps_info;
+			unsigned char	AMPDU_para;
+			unsigned char	MCS_rate[16];
+			unsigned short	HT_ext_caps;
+			unsigned int	Beamforming_caps;
+			unsigned char	ASEL_caps;
+		} HT_cap_element;
+		unsigned char HT_cap[26];
+	} u;
+} __attribute__((packed));
+
+struct HT_info_element {
+	unsigned char	primary_channel;
+	unsigned char	infos[5];
+	unsigned char	MCS_rate[16];
+}  __attribute__((packed));
+
+struct AC_param {
+	unsigned char		ACI_AIFSN;
+	unsigned char		CW;
+	unsigned short	TXOP_limit;
+}  __attribute__((packed));
+
+struct WMM_para_element {
+	unsigned char		QoS_info;
+	unsigned char		reserved;
+	struct AC_param	ac_param[4];
+}  __attribute__((packed));
+
+struct ADDBA_request {
+	unsigned char		dialog_token;
+	unsigned short	BA_para_set;
+	unsigned short	BA_timeout_value;
+	unsigned short	BA_starting_seqctrl;
+}  __attribute__((packed));
+
+
+
+#endif
+
+
+#ifdef PLATFORM_WINDOWS
+
+#pragma pack(1)
+
+struct rtw_ieee80211_ht_cap {
+	unsigned short	cap_info;
+	unsigned char	ampdu_params_info;
+	unsigned char	supp_mcs_set[16];
+	unsigned short	extended_ht_cap_info;
+	unsigned int		tx_BF_cap_info;
+	unsigned char	       antenna_selection_info;
+};
+
+
+struct ieee80211_ht_addt_info {
+	unsigned char	control_chan;
+	unsigned char		ht_param;
+	unsigned short	operation_mode;
+	unsigned short	stbc_param;
+	unsigned char		basic_set[16];
+};
+
+struct HT_caps_element {
+	union {
+		struct {
+			unsigned short	HT_caps_info;
+			unsigned char	AMPDU_para;
+			unsigned char	MCS_rate[16];
+			unsigned short	HT_ext_caps;
+			unsigned int	Beamforming_caps;
+			unsigned char	ASEL_caps;
+		} HT_cap_element;
+		unsigned char HT_cap[26];
+	};
+};
+
+struct HT_info_element {
+	unsigned char	primary_channel;
+	unsigned char	infos[5];
+	unsigned char	MCS_rate[16];
+};
+
+struct AC_param {
+	unsigned char		ACI_AIFSN;
+	unsigned char		CW;
+	unsigned short	TXOP_limit;
+};
+
+struct WMM_para_element {
+	unsigned char		QoS_info;
+	unsigned char		reserved;
+	struct AC_param	ac_param[4];
+};
+
+struct ADDBA_request {
+	unsigned char		dialog_token;
+	unsigned short	BA_para_set;
+	unsigned short	BA_timeout_value;
+	unsigned short	BA_starting_seqctrl;
+};
+
+
+#pragma pack()
+
+#endif
+
+typedef enum _HT_CAP_AMPDU_FACTOR {
+	MAX_AMPDU_FACTOR_8K		= 0,
+	MAX_AMPDU_FACTOR_16K	= 1,
+	MAX_AMPDU_FACTOR_32K	= 2,
+	MAX_AMPDU_FACTOR_64K	= 3,
+} HT_CAP_AMPDU_FACTOR;
+
+typedef enum _VHT_CAP_AMPDU_FACTOR {
+	MAX_AMPDU_FACTOR_128K = 4,
+	MAX_AMPDU_FACTOR_256K = 5,
+	MAX_AMPDU_FACTOR_512K = 6,
+	MAX_AMPDU_FACTOR_1M = 7,
+} VHT_CAP_AMPDU_FACTOR;
+
+
+typedef enum _HT_CAP_AMPDU_DENSITY {
+	AMPDU_DENSITY_VALUE_0 = 0 , /* For no restriction */
+	AMPDU_DENSITY_VALUE_1 = 1 , /* For 1/4 us */
+	AMPDU_DENSITY_VALUE_2 = 2 , /* For 1/2 us */
+	AMPDU_DENSITY_VALUE_3 = 3 , /* For 1 us */
+	AMPDU_DENSITY_VALUE_4 = 4 , /* For 2 us */
+	AMPDU_DENSITY_VALUE_5 = 5 , /* For 4 us */
+	AMPDU_DENSITY_VALUE_6 = 6 , /* For 8 us */
+	AMPDU_DENSITY_VALUE_7 = 7 , /* For 16 us */
+} HT_CAP_AMPDU_DENSITY;
+
+/* 802.11n HT capabilities masks */
+#define IEEE80211_HT_CAP_LDPC_CODING		0x0001
+#define IEEE80211_HT_CAP_SUP_WIDTH		0x0002
+#define IEEE80211_HT_CAP_SM_PS			0x000C
+#define IEEE80211_HT_CAP_GRN_FLD		0x0010
+#define IEEE80211_HT_CAP_SGI_20			0x0020
+#define IEEE80211_HT_CAP_SGI_40			0x0040
+#define IEEE80211_HT_CAP_TX_STBC			0x0080
+#define IEEE80211_HT_CAP_RX_STBC_1R		0x0100
+#define IEEE80211_HT_CAP_RX_STBC_2R		0x0200
+#define IEEE80211_HT_CAP_RX_STBC_3R		0x0300
+#define IEEE80211_HT_CAP_DELAY_BA		0x0400
+#define IEEE80211_HT_CAP_MAX_AMSDU		0x0800
+#define IEEE80211_HT_CAP_DSSSCCK40		0x1000
+#define RTW_IEEE80211_HT_CAP_40MHZ_INTOLERANT	((u16) BIT(14))
+/* 802.11n HT capability AMPDU settings */
+#define IEEE80211_HT_CAP_AMPDU_FACTOR		0x03
+#define IEEE80211_HT_CAP_AMPDU_DENSITY		0x1C
+/* 802.11n HT capability MSC set */
+#define IEEE80211_SUPP_MCS_SET_UEQM		4
+#define IEEE80211_HT_CAP_MAX_STREAMS		4
+#define IEEE80211_SUPP_MCS_SET_LEN		10
+/* maximum streams the spec allows */
+#define IEEE80211_HT_CAP_MCS_TX_DEFINED		0x01
+#define IEEE80211_HT_CAP_MCS_TX_RX_DIFF		0x02
+#define IEEE80211_HT_CAP_MCS_TX_STREAMS		0x0C
+#define IEEE80211_HT_CAP_MCS_TX_UEQM		0x10
+/* 802.11n HT capability TXBF capability */
+#define IEEE80211_HT_CAP_TXBF_RX_NDP		0x00000008
+#define IEEE80211_HT_CAP_TXBF_TX_NDP		0x00000010
+#define IEEE80211_HT_CAP_TXBF_EXPLICIT_COMP_STEERING_CAP	0x00000400
+
+/* 802.11n HT IE masks */
+#define IEEE80211_HT_IE_CHA_SEC_OFFSET		0x03
+#define IEEE80211_HT_IE_CHA_SEC_NONE		0x00
+#define IEEE80211_HT_IE_CHA_SEC_ABOVE		0x01
+#define IEEE80211_HT_IE_CHA_SEC_BELOW		0x03
+#define IEEE80211_HT_IE_CHA_WIDTH		0x04
+#define IEEE80211_HT_IE_HT_PROTECTION		0x0003
+#define IEEE80211_HT_IE_NON_GF_STA_PRSNT	0x0004
+#define IEEE80211_HT_IE_NON_HT_STA_PRSNT	0x0010
+
+/* block-ack parameters */
+#define IEEE80211_ADDBA_PARAM_POLICY_MASK 0x0002
+#define IEEE80211_ADDBA_PARAM_TID_MASK 0x003C
+#define RTW_IEEE80211_ADDBA_PARAM_BUF_SIZE_MASK 0xFFC0
+#define IEEE80211_DELBA_PARAM_TID_MASK 0xF000
+#define IEEE80211_DELBA_PARAM_INITIATOR_MASK 0x0800
+
+/*
+ * A-PMDU buffer sizes
+ * According to IEEE802.11n spec size varies from 8K to 64K (in powers of 2)
+ */
+#define IEEE80211_MIN_AMPDU_BUF 0x8
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(4,19,0)
+#define IEEE80211_MAX_AMPDU_BUF_HT 0x40
+#define IEEE80211_MAX_AMPDU_BUF 0x100
+#else
+#define IEEE80211_MAX_AMPDU_BUF 0x40
+#endif
+
+
+/* Spatial Multiplexing Power Save Modes */
+#define WLAN_HT_CAP_SM_PS_STATIC		0
+#define WLAN_HT_CAP_SM_PS_DYNAMIC	1
+#define WLAN_HT_CAP_SM_PS_INVALID	2
+#define WLAN_HT_CAP_SM_PS_DISABLED	3
+
+
+#define OP_MODE_PURE                    0
+#define OP_MODE_MAY_BE_LEGACY_STAS      1
+#define OP_MODE_20MHZ_HT_STA_ASSOCED    2
+#define OP_MODE_MIXED                   3
+
+#define HT_INFO_HT_PARAM_SECONDARY_CHNL_OFF_MASK	((u8) BIT(0) | BIT(1))
+#define HT_INFO_HT_PARAM_SECONDARY_CHNL_ABOVE		((u8) BIT(0))
+#define HT_INFO_HT_PARAM_SECONDARY_CHNL_BELOW		((u8) BIT(0) | BIT(1))
+#define HT_INFO_HT_PARAM_REC_TRANS_CHNL_WIDTH		((u8) BIT(2))
+#define HT_INFO_HT_PARAM_RIFS_MODE			((u8) BIT(3))
+#define HT_INFO_HT_PARAM_CTRL_ACCESS_ONLY		((u8) BIT(4))
+#define HT_INFO_HT_PARAM_SRV_INTERVAL_GRANULARITY	((u8) BIT(5))
+
+#define HT_INFO_OPERATION_MODE_OP_MODE_MASK	\
+	((u16) (0x0001 | 0x0002))
+#define HT_INFO_OPERATION_MODE_OP_MODE_OFFSET		0
+#define HT_INFO_OPERATION_MODE_NON_GF_DEVS_PRESENT	((u8) BIT(2))
+#define HT_INFO_OPERATION_MODE_TRANSMIT_BURST_LIMIT	((u8) BIT(3))
+#define HT_INFO_OPERATION_MODE_NON_HT_STA_PRESENT	((u8) BIT(4))
+
+#define HT_INFO_STBC_PARAM_DUAL_BEACON			((u16) BIT(6))
+#define HT_INFO_STBC_PARAM_DUAL_STBC_PROTECT		((u16) BIT(7))
+#define HT_INFO_STBC_PARAM_SECONDARY_BCN		((u16) BIT(8))
+#define HT_INFO_STBC_PARAM_LSIG_TXOP_PROTECT_ALLOWED	((u16) BIT(9))
+#define HT_INFO_STBC_PARAM_PCO_ACTIVE			((u16) BIT(10))
+#define HT_INFO_STBC_PARAM_PCO_PHASE			((u16) BIT(11))
+
+
+
+/* #endif */
+
+/*	===============WPS Section=============== */
+/*	For WPSv1.0 */
+#define WPSOUI							0x0050f204
+/*	WPS attribute ID */
+#define WPS_ATTR_VER1					0x104A
+#define WPS_ATTR_SIMPLE_CONF_STATE	0x1044
+#define WPS_ATTR_RESP_TYPE			0x103B
+#define WPS_ATTR_UUID_E				0x1047
+#define WPS_ATTR_MANUFACTURER		0x1021
+#define WPS_ATTR_MODEL_NAME			0x1023
+#define WPS_ATTR_MODEL_NUMBER		0x1024
+#define WPS_ATTR_SERIAL_NUMBER		0x1042
+#define WPS_ATTR_PRIMARY_DEV_TYPE	0x1054
+#define WPS_ATTR_SEC_DEV_TYPE_LIST	0x1055
+#define WPS_ATTR_DEVICE_NAME			0x1011
+#define WPS_ATTR_CONF_METHOD			0x1008
+#define WPS_ATTR_RF_BANDS				0x103C
+#define WPS_ATTR_DEVICE_PWID			0x1012
+#define WPS_ATTR_REQUEST_TYPE			0x103A
+#define WPS_ATTR_ASSOCIATION_STATE	0x1002
+#define WPS_ATTR_CONFIG_ERROR			0x1009
+#define WPS_ATTR_VENDOR_EXT			0x1049
+#define WPS_ATTR_SELECTED_REGISTRAR	0x1041
+
+/*	Value of WPS attribute "WPS_ATTR_DEVICE_NAME */
+#define WPS_MAX_DEVICE_NAME_LEN		32
+
+/*	Value of WPS Request Type Attribute */
+#define WPS_REQ_TYPE_ENROLLEE_INFO_ONLY			0x00
+#define WPS_REQ_TYPE_ENROLLEE_OPEN_8021X		0x01
+#define WPS_REQ_TYPE_REGISTRAR					0x02
+#define WPS_REQ_TYPE_WLAN_MANAGER_REGISTRAR	0x03
+
+/*	Value of WPS Response Type Attribute */
+#define WPS_RESPONSE_TYPE_INFO_ONLY	0x00
+#define WPS_RESPONSE_TYPE_8021X		0x01
+#define WPS_RESPONSE_TYPE_REGISTRAR	0x02
+#define WPS_RESPONSE_TYPE_AP			0x03
+
+/*	Value of WPS WiFi Simple Configuration State Attribute */
+#define WPS_WSC_STATE_NOT_CONFIG	0x01
+#define WPS_WSC_STATE_CONFIG			0x02
+
+/*	Value of WPS Version Attribute */
+#define WPS_VERSION_1					0x10
+
+/*	Value of WPS Configuration Method Attribute */
+#define WPS_CONFIG_METHOD_FLASH		0x0001
+#define WPS_CONFIG_METHOD_ETHERNET	0x0002
+#define WPS_CONFIG_METHOD_LABEL		0x0004
+#define WPS_CONFIG_METHOD_DISPLAY	0x0008
+#define WPS_CONFIG_METHOD_E_NFC		0x0010
+#define WPS_CONFIG_METHOD_I_NFC		0x0020
+#define WPS_CONFIG_METHOD_NFC		0x0040
+#define WPS_CONFIG_METHOD_PBC		0x0080
+#define WPS_CONFIG_METHOD_KEYPAD	0x0100
+#define WPS_CONFIG_METHOD_VPBC		0x0280
+#define WPS_CONFIG_METHOD_PPBC		0x0480
+#define WPS_CONFIG_METHOD_VDISPLAY	0x2008
+#define WPS_CONFIG_METHOD_PDISPLAY	0x4008
+
+/*	Value of Category ID of WPS Primary Device Type Attribute */
+#define WPS_PDT_CID_DISPLAYS			0x0007
+#define WPS_PDT_CID_MULIT_MEDIA		0x0008
+#define WPS_PDT_CID_RTK_WIDI			WPS_PDT_CID_MULIT_MEDIA
+
+/*	Value of Sub Category ID of WPS Primary Device Type Attribute */
+#define WPS_PDT_SCID_MEDIA_SERVER	0x0005
+#define WPS_PDT_SCID_RTK_DMP			WPS_PDT_SCID_MEDIA_SERVER
+
+/*	Value of Device Password ID */
+#define WPS_DPID_PIN					0x0000
+#define WPS_DPID_USER_SPEC			0x0001
+#define WPS_DPID_MACHINE_SPEC			0x0002
+#define WPS_DPID_REKEY					0x0003
+#define WPS_DPID_PBC					0x0004
+#define WPS_DPID_REGISTRAR_SPEC		0x0005
+
+/*	Value of WPS RF Bands Attribute */
+#define WPS_RF_BANDS_2_4_GHZ		0x01
+#define WPS_RF_BANDS_5_GHZ		0x02
+
+/*	Value of WPS Association State Attribute */
+#define WPS_ASSOC_STATE_NOT_ASSOCIATED			0x00
+#define WPS_ASSOC_STATE_CONNECTION_SUCCESS		0x01
+#define WPS_ASSOC_STATE_CONFIGURATION_FAILURE	0x02
+#define WPS_ASSOC_STATE_ASSOCIATION_FAILURE		0x03
+#define WPS_ASSOC_STATE_IP_FAILURE				0x04
+
+/*	=====================P2P Section===================== */
+/*	For P2P */
+#define	P2POUI							0x506F9A09
+
+/*	P2P Attribute ID */
+#define	P2P_ATTR_STATUS					0x00
+#define	P2P_ATTR_MINOR_REASON_CODE		0x01
+#define	P2P_ATTR_CAPABILITY				0x02
+#define	P2P_ATTR_DEVICE_ID				0x03
+#define	P2P_ATTR_GO_INTENT				0x04
+#define	P2P_ATTR_CONF_TIMEOUT			0x05
+#define	P2P_ATTR_LISTEN_CH				0x06
+#define	P2P_ATTR_GROUP_BSSID				0x07
+#define	P2P_ATTR_EX_LISTEN_TIMING		0x08
+#define	P2P_ATTR_INTENDED_IF_ADDR		0x09
+#define	P2P_ATTR_MANAGEABILITY			0x0A
+#define	P2P_ATTR_CH_LIST					0x0B
+#define	P2P_ATTR_NOA						0x0C
+#define	P2P_ATTR_DEVICE_INFO				0x0D
+#define	P2P_ATTR_GROUP_INFO				0x0E
+#define	P2P_ATTR_GROUP_ID					0x0F
+#define	P2P_ATTR_INTERFACE				0x10
+#define	P2P_ATTR_OPERATING_CH			0x11
+#define	P2P_ATTR_INVITATION_FLAGS		0x12
+
+/*	Value of Status Attribute */
+#define	P2P_STATUS_SUCCESS						0x00
+#define	P2P_STATUS_FAIL_INFO_UNAVAILABLE		0x01
+#define	P2P_STATUS_FAIL_INCOMPATIBLE_PARAM		0x02
+#define	P2P_STATUS_FAIL_LIMIT_REACHED			0x03
+#define	P2P_STATUS_FAIL_INVALID_PARAM			0x04
+#define	P2P_STATUS_FAIL_REQUEST_UNABLE			0x05
+#define	P2P_STATUS_FAIL_PREVOUS_PROTO_ERR		0x06
+#define	P2P_STATUS_FAIL_NO_COMMON_CH			0x07
+#define	P2P_STATUS_FAIL_UNKNOWN_P2PGROUP		0x08
+#define	P2P_STATUS_FAIL_BOTH_GOINTENT_15		0x09
+#define	P2P_STATUS_FAIL_INCOMPATIBLE_PROVSION	0x0A
+#define	P2P_STATUS_FAIL_USER_REJECT				0x0B
+
+/*	Value of Inviation Flags Attribute */
+#define	P2P_INVITATION_FLAGS_PERSISTENT			BIT(0)
+
+#define	DMP_P2P_DEVCAP_SUPPORT	(P2P_DEVCAP_SERVICE_DISCOVERY | \
+				 P2P_DEVCAP_CLIENT_DISCOVERABILITY | \
+				 P2P_DEVCAP_CONCURRENT_OPERATION | \
+				 P2P_DEVCAP_INVITATION_PROC)
+
+#define	DMP_P2P_GRPCAP_SUPPORT	(P2P_GRPCAP_INTRABSS)
+
+/*	Value of Device Capability Bitmap */
+#define	P2P_DEVCAP_SERVICE_DISCOVERY		BIT(0)
+#define	P2P_DEVCAP_CLIENT_DISCOVERABILITY	BIT(1)
+#define	P2P_DEVCAP_CONCURRENT_OPERATION	BIT(2)
+#define	P2P_DEVCAP_INFRA_MANAGED			BIT(3)
+#define	P2P_DEVCAP_DEVICE_LIMIT				BIT(4)
+#define	P2P_DEVCAP_INVITATION_PROC			BIT(5)
+
+/*	Value of Group Capability Bitmap */
+#define	P2P_GRPCAP_GO							BIT(0)
+#define	P2P_GRPCAP_PERSISTENT_GROUP			BIT(1)
+#define	P2P_GRPCAP_GROUP_LIMIT				BIT(2)
+#define	P2P_GRPCAP_INTRABSS					BIT(3)
+#define	P2P_GRPCAP_CROSS_CONN				BIT(4)
+#define	P2P_GRPCAP_PERSISTENT_RECONN		BIT(5)
+#define	P2P_GRPCAP_GROUP_FORMATION			BIT(6)
+
+/*	P2P Public Action Frame ( Management Frame ) */
+#define	P2P_PUB_ACTION_ACTION				0x09
+
+/*	P2P Public Action Frame Type */
+#define	P2P_GO_NEGO_REQ						0
+#define	P2P_GO_NEGO_RESP						1
+#define	P2P_GO_NEGO_CONF						2
+#define	P2P_INVIT_REQ							3
+#define	P2P_INVIT_RESP							4
+#define	P2P_DEVDISC_REQ						5
+#define	P2P_DEVDISC_RESP						6
+#define	P2P_PROVISION_DISC_REQ				7
+#define	P2P_PROVISION_DISC_RESP				8
+
+/*	P2P Action Frame Type */
+#define	P2P_NOTICE_OF_ABSENCE	0
+#define	P2P_PRESENCE_REQUEST		1
+#define	P2P_PRESENCE_RESPONSE	2
+#define	P2P_GO_DISC_REQUEST		3
+
+
+#define	P2P_MAX_PERSISTENT_GROUP_NUM		10
+
+#define	P2P_PROVISIONING_SCAN_CNT			3
+
+#define	P2P_WILDCARD_SSID_LEN				7
+
+#define	P2P_FINDPHASE_EX_NONE				0	/* default value, used when: (1)p2p disabed or (2)p2p enabled but only do 1 scan phase */
+#define	P2P_FINDPHASE_EX_FULL				1	/* used when p2p enabled and want to do 1 scan phase and P2P_FINDPHASE_EX_MAX-1 find phase */
+#define	P2P_FINDPHASE_EX_SOCIAL_FIRST		(P2P_FINDPHASE_EX_FULL+1)
+#define	P2P_FINDPHASE_EX_MAX					4
+#define	P2P_FINDPHASE_EX_SOCIAL_LAST		P2P_FINDPHASE_EX_MAX
+
+#define	P2P_PROVISION_TIMEOUT				5000	/*	5 seconds timeout for sending the provision discovery request */
+#define	P2P_CONCURRENT_PROVISION_TIMEOUT	3000	/*	3 seconds timeout for sending the provision discovery request under concurrent mode */
+#define	P2P_GO_NEGO_TIMEOUT					5000	/*	5 seconds timeout for receiving the group negotation response */
+#define	P2P_CONCURRENT_GO_NEGO_TIMEOUT		3000	/*	3 seconds timeout for sending the negotiation request under concurrent mode */
+#define	P2P_TX_PRESCAN_TIMEOUT				100		/*	100ms */
+#define	P2P_INVITE_TIMEOUT					5000	/*	5 seconds timeout for sending the invitation request */
+#define	P2P_CONCURRENT_INVITE_TIMEOUT		3000	/*	3 seconds timeout for sending the invitation request under concurrent mode */
+#define	P2P_RESET_SCAN_CH						25000	/*	25 seconds timeout to reset the scan channel (based on channel plan) */
+#define	P2P_MAX_INTENT						15
+
+#define	P2P_MAX_NOA_NUM						2
+
+/*	WPS Configuration Method */
+#define	WPS_CM_NONE							0x0000
+#define	WPS_CM_LABEL							0x0004
+#define	WPS_CM_DISPLYA						0x0008
+#define	WPS_CM_EXTERNAL_NFC_TOKEN			0x0010
+#define	WPS_CM_INTEGRATED_NFC_TOKEN		0x0020
+#define	WPS_CM_NFC_INTERFACE					0x0040
+#define	WPS_CM_PUSH_BUTTON					0x0080
+#define	WPS_CM_KEYPAD						0x0100
+#define	WPS_CM_SW_PUHS_BUTTON				0x0280
+#define	WPS_CM_HW_PUHS_BUTTON				0x0480
+#define	WPS_CM_SW_DISPLAY_PIN				0x2008
+#define	WPS_CM_LCD_DISPLAY_PIN				0x4008
+
+enum P2P_ROLE {
+	P2P_ROLE_DISABLE = 0,
+	P2P_ROLE_DEVICE = 1,
+	P2P_ROLE_CLIENT = 2,
+	P2P_ROLE_GO = 3
+};
+
+enum P2P_STATE {
+	P2P_STATE_NONE = 0,							/*	P2P disable */
+	P2P_STATE_IDLE = 1,								/*	P2P had enabled and do nothing ,  buddy adapters is linked */
+	P2P_STATE_LISTEN = 2,							/*	In pure listen state */
+	P2P_STATE_SCAN = 3,							/*	In scan phase */
+	P2P_STATE_FIND_PHASE_LISTEN = 4,				/*	In the listen state of find phase */
+	P2P_STATE_FIND_PHASE_SEARCH = 5,				/*	In the search state of find phase */
+	P2P_STATE_TX_PROVISION_DIS_REQ = 6,			/*	In P2P provisioning discovery */
+	P2P_STATE_RX_PROVISION_DIS_RSP = 7,
+	P2P_STATE_RX_PROVISION_DIS_REQ = 8,
+	P2P_STATE_GONEGO_ING = 9,						/*	Doing the group owner negoitation handshake */
+	P2P_STATE_GONEGO_OK = 10,						/*	finish the group negoitation handshake with success */
+	P2P_STATE_GONEGO_FAIL = 11,					/*	finish the group negoitation handshake with failure */
+	P2P_STATE_RECV_INVITE_REQ_MATCH = 12,		/*	receiving the P2P Inviation request and match with the profile. */
+	P2P_STATE_PROVISIONING_ING = 13,				/*	Doing the P2P WPS */
+	P2P_STATE_PROVISIONING_DONE = 14,			/*	Finish the P2P WPS */
+	P2P_STATE_TX_INVITE_REQ = 15,					/*	Transmit the P2P Invitation request */
+	P2P_STATE_RX_INVITE_RESP_OK = 16,				/*	Receiving the P2P Invitation response */
+	P2P_STATE_RECV_INVITE_REQ_DISMATCH = 17,	/*	receiving the P2P Inviation request and dismatch with the profile. */
+	P2P_STATE_RECV_INVITE_REQ_GO = 18,			/*	receiving the P2P Inviation request and this wifi is GO. */
+	P2P_STATE_RECV_INVITE_REQ_JOIN = 19,			/*	receiving the P2P Inviation request to join an existing P2P Group. */
+	P2P_STATE_RX_INVITE_RESP_FAIL = 20,			/*	recveing the P2P Inviation response with failure */
+	P2P_STATE_RX_INFOR_NOREADY = 21,			/* receiving p2p negoitation response with information is not available */
+	P2P_STATE_TX_INFOR_NOREADY = 22,			/* sending p2p negoitation response with information is not available */
+};
+
+enum P2P_WPSINFO {
+	P2P_NO_WPSINFO						= 0,
+	P2P_GOT_WPSINFO_PEER_DISPLAY_PIN	= 1,
+	P2P_GOT_WPSINFO_SELF_DISPLAY_PIN	= 2,
+	P2P_GOT_WPSINFO_PBC					= 3,
+};
+
+#define	P2P_PRIVATE_IOCTL_SET_LEN		64
+
+enum P2P_PROTO_WK_ID {
+	P2P_FIND_PHASE_WK = 0,
+	P2P_RESTORE_STATE_WK = 1,
+	P2P_PRE_TX_PROVDISC_PROCESS_WK = 2,
+	P2P_PRE_TX_NEGOREQ_PROCESS_WK = 3,
+	P2P_PRE_TX_INVITEREQ_PROCESS_WK = 4,
+	P2P_AP_P2P_CH_SWITCH_PROCESS_WK = 5,
+	P2P_RO_CH_WK = 6,
+	P2P_CANCEL_RO_CH_WK = 7,
+};
+
+#ifdef CONFIG_P2P_PS
+enum P2P_PS_STATE {
+	P2P_PS_DISABLE = 0,
+	P2P_PS_ENABLE = 1,
+	P2P_PS_SCAN = 2,
+	P2P_PS_SCAN_DONE = 3,
+	P2P_PS_ALLSTASLEEP = 4, /* for P2P GO */
+};
+
+enum P2P_PS_MODE {
+	P2P_PS_NONE = 0,
+	P2P_PS_CTWINDOW = 1,
+	P2P_PS_NOA	 = 2,
+	P2P_PS_MIX = 3, /* CTWindow and NoA */
+};
+#endif /* CONFIG_P2P_PS */
+
+/*	=====================WFD Section=====================
+ *	For Wi-Fi Display */
+#define	WFD_ATTR_DEVICE_INFO			0x00
+#define	WFD_ATTR_ASSOC_BSSID			0x01
+#define	WFD_ATTR_COUPLED_SINK_INFO	0x06
+#define	WFD_ATTR_LOCAL_IP_ADDR		0x08
+#define	WFD_ATTR_SESSION_INFO		0x09
+#define	WFD_ATTR_ALTER_MAC			0x0a
+
+/*	For WFD Device Information Attribute */
+#define	WFD_DEVINFO_SOURCE					0x0000
+#define	WFD_DEVINFO_PSINK					0x0001
+#define	WFD_DEVINFO_SSINK					0x0002
+#define	WFD_DEVINFO_DUAL					0x0003
+
+#define	WFD_DEVINFO_SESSION_AVAIL			0x0010
+#define	WFD_DEVINFO_WSD						0x0040
+#define	WFD_DEVINFO_PC_TDLS					0x0080
+#define	WFD_DEVINFO_HDCP_SUPPORT			0x0100
+
+#define IP_MCAST_MAC(mac)		((mac[0] == 0x01) && (mac[1] == 0x00) && (mac[2] == 0x5e))
+#define ICMPV6_MCAST_MAC(mac)	((mac[0] == 0x33) && (mac[1] == 0x33) && (mac[2] != 0xff))
+
+#ifdef CONFIG_IOCTL_CFG80211
+/* Regulatroy Domain */
+struct regd_pair_mapping {
+	u16 reg_dmnenum;
+	u16 reg_5ghz_ctl;
+	u16 reg_2ghz_ctl;
+};
+
+struct rtw_regulatory {
+	char alpha2[2];
+	u16 country_code;
+	u16 max_power_level;
+	u32 tp_scale;
+	u16 current_rd;
+	u16 current_rd_ext;
+	int16_t power_limit;
+	struct regd_pair_mapping *regpair;
+};
+#endif
+
+#ifdef CONFIG_WAPI_SUPPORT
+#ifndef IW_AUTH_WAPI_VERSION_1
+#define IW_AUTH_WAPI_VERSION_1		0x00000008
+#endif
+#ifndef IW_AUTH_KEY_MGMT_WAPI_PSK
+#define IW_AUTH_KEY_MGMT_WAPI_PSK	0x04
+#endif
+#ifndef IW_AUTH_WAPI_ENABLED
+#define IW_AUTH_WAPI_ENABLED		0x20
+#endif
+#ifndef IW_ENCODE_ALG_SM4
+#define IW_ENCODE_ALG_SM4			0x20
+#endif
+#endif
+
+#endif /* _WIFI_H_ */
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/include/wlan_bssdef.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/wlan_bssdef.h
--- linux-5.6.3/3rdparty/rtl8821ce/include/wlan_bssdef.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/wlan_bssdef.h	2020-04-10 16:35:06.853661795 +0300
@@ -0,0 +1,705 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#ifndef __WLAN_BSSDEF_H__
+#define __WLAN_BSSDEF_H__
+
+
+#define MAX_IE_SZ	768
+
+
+#ifdef PLATFORM_LINUX
+
+#define NDIS_802_11_LENGTH_SSID         32
+#define NDIS_802_11_LENGTH_RATES        8
+#define NDIS_802_11_LENGTH_RATES_EX     16
+
+typedef unsigned char   NDIS_802_11_MAC_ADDRESS[ETH_ALEN];
+typedef long    		NDIS_802_11_RSSI;           /* in dBm */
+typedef unsigned char   NDIS_802_11_RATES[NDIS_802_11_LENGTH_RATES];        /* Set of 8 data rates */
+typedef unsigned char   NDIS_802_11_RATES_EX[NDIS_802_11_LENGTH_RATES_EX];  /* Set of 16 data rates */
+
+
+typedef  ULONG  NDIS_802_11_KEY_INDEX;
+typedef unsigned long long NDIS_802_11_KEY_RSC;
+
+
+typedef struct _NDIS_802_11_SSID {
+	ULONG  SsidLength;
+	UCHAR  Ssid[32];
+} NDIS_802_11_SSID, *PNDIS_802_11_SSID;
+
+typedef enum _NDIS_802_11_NETWORK_TYPE {
+	Ndis802_11FH,
+	Ndis802_11DS,
+	Ndis802_11OFDM5,
+	Ndis802_11OFDM24,
+	Ndis802_11NetworkTypeMax    /* not a real type, defined as an upper bound */
+} NDIS_802_11_NETWORK_TYPE, *PNDIS_802_11_NETWORK_TYPE;
+
+typedef struct _NDIS_802_11_CONFIGURATION_FH {
+	ULONG           Length;             /* Length of structure */
+	ULONG           HopPattern;         /* As defined by 802.11, MSB set */
+	ULONG           HopSet;             /* to one if non-802.11 */
+	ULONG           DwellTime;          /* units are Kusec */
+} NDIS_802_11_CONFIGURATION_FH, *PNDIS_802_11_CONFIGURATION_FH;
+
+
+/*
+	FW will only save the channel number in DSConfig.
+	ODI Handler will convert the channel number to freq. number.
+*/
+typedef struct _NDIS_802_11_CONFIGURATION {
+	ULONG           Length;             /* Length of structure */
+	ULONG           BeaconPeriod;       /* units are Kusec */
+	ULONG           ATIMWindow;         /* units are Kusec */
+	ULONG           DSConfig;           /* channel number */
+	NDIS_802_11_CONFIGURATION_FH    FHConfig;
+} NDIS_802_11_CONFIGURATION, *PNDIS_802_11_CONFIGURATION;
+
+
+
+typedef enum _NDIS_802_11_NETWORK_INFRASTRUCTURE {
+	Ndis802_11IBSS,
+	Ndis802_11Infrastructure,
+	Ndis802_11AutoUnknown,
+	Ndis802_11InfrastructureMax,     /* Not a real value, defined as upper bound */
+	Ndis802_11APMode,
+	Ndis802_11Monitor,
+	Ndis802_11_mesh,
+} NDIS_802_11_NETWORK_INFRASTRUCTURE, *PNDIS_802_11_NETWORK_INFRASTRUCTURE;
+
+
+
+
+
+typedef struct _NDIS_802_11_FIXED_IEs {
+	UCHAR  Timestamp[8];
+	USHORT  BeaconInterval;
+	USHORT  Capabilities;
+} NDIS_802_11_FIXED_IEs, *PNDIS_802_11_FIXED_IEs;
+
+
+
+typedef struct _NDIS_802_11_VARIABLE_IEs {
+	UCHAR  ElementID;
+	UCHAR  Length;
+	UCHAR  data[1];
+} NDIS_802_11_VARIABLE_IEs, *PNDIS_802_11_VARIABLE_IEs;
+
+
+
+/*
+
+
+
+Length is the 4 bytes multiples of the sume of
+	sizeof (NDIS_802_11_MAC_ADDRESS) + 2 + sizeof (NDIS_802_11_SSID) + sizeof (ULONG)
++   sizeof (NDIS_802_11_RSSI) + sizeof (NDIS_802_11_NETWORK_TYPE) + sizeof (NDIS_802_11_CONFIGURATION)
++   sizeof (NDIS_802_11_RATES_EX) + IELength
+
+Except the IELength, all other fields are fixed length. Therefore, we can define a marco to present the
+partial sum.
+
+*/
+#if 0
+typedef struct _NDIS_WLAN_BSSID_EX {
+	ULONG  Length;
+	NDIS_802_11_MAC_ADDRESS  MacAddress;
+	UCHAR  Reserved[2];/* [0]: IS beacon frame, [1]:optimum_antenna=>For antenna diversity; */
+	NDIS_802_11_SSID  Ssid;
+	ULONG  Privacy;
+	NDIS_802_11_RSSI  Rssi;
+	NDIS_802_11_NETWORK_TYPE  NetworkTypeInUse;
+	NDIS_802_11_CONFIGURATION  Configuration;
+	NDIS_802_11_NETWORK_INFRASTRUCTURE  InfrastructureMode;
+	NDIS_802_11_RATES_EX  SupportedRates;
+	ULONG  IELength;
+	UCHAR  IEs[MAX_IE_SZ];	/* (timestamp, beacon interval, and capability information) */
+} NDIS_WLAN_BSSID_EX, *PNDIS_WLAN_BSSID_EX;
+
+
+typedef struct _NDIS_802_11_BSSID_LIST_EX {
+	ULONG  NumberOfItems;
+	NDIS_WLAN_BSSID_EX  Bssid[1];
+} NDIS_802_11_BSSID_LIST_EX, *PNDIS_802_11_BSSID_LIST_EX;
+#endif
+
+typedef enum _NDIS_802_11_AUTHENTICATION_MODE {
+	Ndis802_11AuthModeOpen,
+	Ndis802_11AuthModeShared,
+	Ndis802_11AuthModeAutoSwitch,
+	Ndis802_11AuthModeWPA,
+	Ndis802_11AuthModeWPAPSK,
+	Ndis802_11AuthModeWPANone,
+	Ndis802_11AuthModeWAPI,
+	Ndis802_11AuthModeMax               /* Not a real mode, defined as upper bound */
+} NDIS_802_11_AUTHENTICATION_MODE, *PNDIS_802_11_AUTHENTICATION_MODE;
+
+typedef enum _NDIS_802_11_WEP_STATUS {
+	Ndis802_11WEPEnabled,
+	Ndis802_11Encryption1Enabled = Ndis802_11WEPEnabled,
+	Ndis802_11WEPDisabled,
+	Ndis802_11EncryptionDisabled = Ndis802_11WEPDisabled,
+	Ndis802_11WEPKeyAbsent,
+	Ndis802_11Encryption1KeyAbsent = Ndis802_11WEPKeyAbsent,
+	Ndis802_11WEPNotSupported,
+	Ndis802_11EncryptionNotSupported = Ndis802_11WEPNotSupported,
+	Ndis802_11Encryption2Enabled,
+	Ndis802_11Encryption2KeyAbsent,
+	Ndis802_11Encryption3Enabled,
+	Ndis802_11Encryption3KeyAbsent,
+	Ndis802_11_EncrypteionWAPI
+} NDIS_802_11_WEP_STATUS, *PNDIS_802_11_WEP_STATUS,
+NDIS_802_11_ENCRYPTION_STATUS, *PNDIS_802_11_ENCRYPTION_STATUS;
+
+
+#define NDIS_802_11_AI_REQFI_CAPABILITIES      1
+#define NDIS_802_11_AI_REQFI_LISTENINTERVAL    2
+#define NDIS_802_11_AI_REQFI_CURRENTAPADDRESS  4
+
+#define NDIS_802_11_AI_RESFI_CAPABILITIES      1
+#define NDIS_802_11_AI_RESFI_STATUSCODE        2
+#define NDIS_802_11_AI_RESFI_ASSOCIATIONID     4
+
+typedef struct _NDIS_802_11_AI_REQFI {
+	USHORT Capabilities;
+	USHORT ListenInterval;
+	NDIS_802_11_MAC_ADDRESS  CurrentAPAddress;
+} NDIS_802_11_AI_REQFI, *PNDIS_802_11_AI_REQFI;
+
+typedef struct _NDIS_802_11_AI_RESFI {
+	USHORT Capabilities;
+	USHORT StatusCode;
+	USHORT AssociationId;
+} NDIS_802_11_AI_RESFI, *PNDIS_802_11_AI_RESFI;
+
+typedef struct _NDIS_802_11_ASSOCIATION_INFORMATION {
+	ULONG                   Length;
+	USHORT                  AvailableRequestFixedIEs;
+	NDIS_802_11_AI_REQFI    RequestFixedIEs;
+	ULONG                   RequestIELength;
+	ULONG                   OffsetRequestIEs;
+	USHORT                  AvailableResponseFixedIEs;
+	NDIS_802_11_AI_RESFI    ResponseFixedIEs;
+	ULONG                   ResponseIELength;
+	ULONG                   OffsetResponseIEs;
+} NDIS_802_11_ASSOCIATION_INFORMATION, *PNDIS_802_11_ASSOCIATION_INFORMATION;
+
+typedef enum _NDIS_802_11_RELOAD_DEFAULTS {
+	Ndis802_11ReloadWEPKeys
+} NDIS_802_11_RELOAD_DEFAULTS, *PNDIS_802_11_RELOAD_DEFAULTS;
+
+
+/* Key mapping keys require a BSSID */
+typedef struct _NDIS_802_11_KEY {
+	ULONG           Length;             /* Length of this structure */
+	ULONG           KeyIndex;
+	ULONG           KeyLength;          /* length of key in bytes */
+	NDIS_802_11_MAC_ADDRESS BSSID;
+	NDIS_802_11_KEY_RSC KeyRSC;
+	UCHAR           KeyMaterial[32];     /* variable length depending on above field */
+} NDIS_802_11_KEY, *PNDIS_802_11_KEY;
+
+typedef struct _NDIS_802_11_REMOVE_KEY {
+	ULONG                   Length;        /* Length of this structure */
+	ULONG                   KeyIndex;
+	NDIS_802_11_MAC_ADDRESS BSSID;
+} NDIS_802_11_REMOVE_KEY, *PNDIS_802_11_REMOVE_KEY;
+
+typedef struct _NDIS_802_11_WEP {
+	ULONG     Length;        /* Length of this structure */
+	ULONG     KeyIndex;      /* 0 is the per-client key, 1-N are the global keys */
+	ULONG     KeyLength;     /* length of key in bytes */
+	UCHAR     KeyMaterial[16];/* variable length depending on above field */
+} NDIS_802_11_WEP, *PNDIS_802_11_WEP;
+
+typedef struct _NDIS_802_11_AUTHENTICATION_REQUEST {
+	ULONG Length;            /* Length of structure */
+	NDIS_802_11_MAC_ADDRESS Bssid;
+	ULONG Flags;
+} NDIS_802_11_AUTHENTICATION_REQUEST, *PNDIS_802_11_AUTHENTICATION_REQUEST;
+
+typedef enum _NDIS_802_11_STATUS_TYPE {
+	Ndis802_11StatusType_Authentication,
+	Ndis802_11StatusType_MediaStreamMode,
+	Ndis802_11StatusType_PMKID_CandidateList,
+	Ndis802_11StatusTypeMax    /* not a real type, defined as an upper bound */
+} NDIS_802_11_STATUS_TYPE, *PNDIS_802_11_STATUS_TYPE;
+
+typedef struct _NDIS_802_11_STATUS_INDICATION {
+	NDIS_802_11_STATUS_TYPE StatusType;
+} NDIS_802_11_STATUS_INDICATION, *PNDIS_802_11_STATUS_INDICATION;
+
+/* mask for authentication/integrity fields */
+#define NDIS_802_11_AUTH_REQUEST_AUTH_FIELDS        0x0f
+#define NDIS_802_11_AUTH_REQUEST_REAUTH			0x01
+#define NDIS_802_11_AUTH_REQUEST_KEYUPDATE		0x02
+#define NDIS_802_11_AUTH_REQUEST_PAIRWISE_ERROR		0x06
+#define NDIS_802_11_AUTH_REQUEST_GROUP_ERROR		0x0E
+
+/* MIC check time, 60 seconds. */
+#define MIC_CHECK_TIME	60000000
+
+typedef struct _NDIS_802_11_AUTHENTICATION_EVENT {
+	NDIS_802_11_STATUS_INDICATION       Status;
+	NDIS_802_11_AUTHENTICATION_REQUEST  Request[1];
+} NDIS_802_11_AUTHENTICATION_EVENT, *PNDIS_802_11_AUTHENTICATION_EVENT;
+
+typedef struct _NDIS_802_11_TEST {
+	ULONG Length;
+	ULONG Type;
+	union {
+		NDIS_802_11_AUTHENTICATION_EVENT AuthenticationEvent;
+		NDIS_802_11_RSSI RssiTrigger;
+	} tt;
+} NDIS_802_11_TEST, *PNDIS_802_11_TEST;
+
+
+#endif /* end of #ifdef PLATFORM_LINUX */
+
+#ifdef PLATFORM_FREEBSD
+
+#define NDIS_802_11_LENGTH_SSID         32
+#define NDIS_802_11_LENGTH_RATES        8
+#define NDIS_802_11_LENGTH_RATES_EX     16
+
+typedef unsigned char   NDIS_802_11_MAC_ADDRESS[ETH_ALEN];
+typedef long    		NDIS_802_11_RSSI;           /* in dBm */
+typedef unsigned char   NDIS_802_11_RATES[NDIS_802_11_LENGTH_RATES];        /* Set of 8 data rates */
+typedef unsigned char   NDIS_802_11_RATES_EX[NDIS_802_11_LENGTH_RATES_EX];  /* Set of 16 data rates */
+
+
+typedef  ULONG  NDIS_802_11_KEY_INDEX;
+typedef unsigned long long NDIS_802_11_KEY_RSC;
+
+
+typedef struct _NDIS_802_11_SSID {
+	ULONG  SsidLength;
+	UCHAR  Ssid[32];
+} NDIS_802_11_SSID, *PNDIS_802_11_SSID;
+
+typedef enum _NDIS_802_11_NETWORK_TYPE {
+	Ndis802_11FH,
+	Ndis802_11DS,
+	Ndis802_11OFDM5,
+	Ndis802_11OFDM24,
+	Ndis802_11NetworkTypeMax    /* not a real type, defined as an upper bound */
+} NDIS_802_11_NETWORK_TYPE, *PNDIS_802_11_NETWORK_TYPE;
+
+typedef struct _NDIS_802_11_CONFIGURATION_FH {
+	ULONG           Length;             /* Length of structure */
+	ULONG           HopPattern;         /* As defined by 802.11, MSB set */
+	ULONG           HopSet;             /* to one if non-802.11 */
+	ULONG           DwellTime;          /* units are Kusec */
+} NDIS_802_11_CONFIGURATION_FH, *PNDIS_802_11_CONFIGURATION_FH;
+
+
+/*
+	FW will only save the channel number in DSConfig.
+	ODI Handler will convert the channel number to freq. number.
+*/
+typedef struct _NDIS_802_11_CONFIGURATION {
+	ULONG           Length;             /* Length of structure */
+	ULONG           BeaconPeriod;       /* units are Kusec */
+	ULONG           ATIMWindow;         /* units are Kusec */
+	ULONG           DSConfig;           /* channel number */
+	NDIS_802_11_CONFIGURATION_FH    FHConfig;
+} NDIS_802_11_CONFIGURATION, *PNDIS_802_11_CONFIGURATION;
+
+
+
+typedef enum _NDIS_802_11_NETWORK_INFRASTRUCTURE {
+	Ndis802_11IBSS,
+	Ndis802_11Infrastructure,
+	Ndis802_11AutoUnknown,
+	Ndis802_11InfrastructureMax,     /* Not a real value, defined as upper bound */
+	Ndis802_11APMode
+} NDIS_802_11_NETWORK_INFRASTRUCTURE, *PNDIS_802_11_NETWORK_INFRASTRUCTURE;
+
+
+
+
+
+typedef struct _NDIS_802_11_FIXED_IEs {
+	UCHAR  Timestamp[8];
+	USHORT  BeaconInterval;
+	USHORT  Capabilities;
+} NDIS_802_11_FIXED_IEs, *PNDIS_802_11_FIXED_IEs;
+
+
+
+typedef struct _NDIS_802_11_VARIABLE_IEs {
+	UCHAR  ElementID;
+	UCHAR  Length;
+	UCHAR  data[1];
+} NDIS_802_11_VARIABLE_IEs, *PNDIS_802_11_VARIABLE_IEs;
+
+
+
+/*
+
+
+
+Length is the 4 bytes multiples of the sume of
+	sizeof (NDIS_802_11_MAC_ADDRESS) + 2 + sizeof (NDIS_802_11_SSID) + sizeof (ULONG)
++   sizeof (NDIS_802_11_RSSI) + sizeof (NDIS_802_11_NETWORK_TYPE) + sizeof (NDIS_802_11_CONFIGURATION)
++   sizeof (NDIS_802_11_RATES_EX) + IELength
+
+Except the IELength, all other fields are fixed length. Therefore, we can define a marco to present the
+partial sum.
+
+*/
+#if 0
+typedef struct _NDIS_WLAN_BSSID_EX {
+	ULONG  Length;
+	NDIS_802_11_MAC_ADDRESS  MacAddress;
+	UCHAR  Reserved[2];/* [0]: IS beacon frame, [1]:optimum_antenna=>For antenna diversity; */
+	NDIS_802_11_SSID  Ssid;
+	ULONG  Privacy;
+	NDIS_802_11_RSSI  Rssi;
+	NDIS_802_11_NETWORK_TYPE  NetworkTypeInUse;
+	NDIS_802_11_CONFIGURATION  Configuration;
+	NDIS_802_11_NETWORK_INFRASTRUCTURE  InfrastructureMode;
+	NDIS_802_11_RATES_EX  SupportedRates;
+	ULONG  IELength;
+	UCHAR  IEs[MAX_IE_SZ];	/* (timestamp, beacon interval, and capability information) */
+} NDIS_WLAN_BSSID_EX, *PNDIS_WLAN_BSSID_EX;
+
+
+typedef struct _NDIS_802_11_BSSID_LIST_EX {
+	ULONG  NumberOfItems;
+	NDIS_WLAN_BSSID_EX  Bssid[1];
+} NDIS_802_11_BSSID_LIST_EX, *PNDIS_802_11_BSSID_LIST_EX;
+#endif
+
+typedef enum _NDIS_802_11_AUTHENTICATION_MODE {
+	Ndis802_11AuthModeOpen,
+	Ndis802_11AuthModeShared,
+	Ndis802_11AuthModeAutoSwitch,
+	Ndis802_11AuthModeWPA,
+	Ndis802_11AuthModeWPAPSK,
+	Ndis802_11AuthModeWPANone,
+	Ndis802_11AuthModeMax               /* Not a real mode, defined as upper bound */
+} NDIS_802_11_AUTHENTICATION_MODE, *PNDIS_802_11_AUTHENTICATION_MODE;
+
+typedef enum _NDIS_802_11_WEP_STATUS {
+	Ndis802_11WEPEnabled,
+	Ndis802_11Encryption1Enabled = Ndis802_11WEPEnabled,
+	Ndis802_11WEPDisabled,
+	Ndis802_11EncryptionDisabled = Ndis802_11WEPDisabled,
+	Ndis802_11WEPKeyAbsent,
+	Ndis802_11Encryption1KeyAbsent = Ndis802_11WEPKeyAbsent,
+	Ndis802_11WEPNotSupported,
+	Ndis802_11EncryptionNotSupported = Ndis802_11WEPNotSupported,
+	Ndis802_11Encryption2Enabled,
+	Ndis802_11Encryption2KeyAbsent,
+	Ndis802_11Encryption3Enabled,
+	Ndis802_11Encryption3KeyAbsent
+} NDIS_802_11_WEP_STATUS, *PNDIS_802_11_WEP_STATUS,
+NDIS_802_11_ENCRYPTION_STATUS, *PNDIS_802_11_ENCRYPTION_STATUS;
+
+
+#define NDIS_802_11_AI_REQFI_CAPABILITIES      1
+#define NDIS_802_11_AI_REQFI_LISTENINTERVAL    2
+#define NDIS_802_11_AI_REQFI_CURRENTAPADDRESS  4
+
+#define NDIS_802_11_AI_RESFI_CAPABILITIES      1
+#define NDIS_802_11_AI_RESFI_STATUSCODE        2
+#define NDIS_802_11_AI_RESFI_ASSOCIATIONID     4
+
+typedef struct _NDIS_802_11_AI_REQFI {
+	USHORT Capabilities;
+	USHORT ListenInterval;
+	NDIS_802_11_MAC_ADDRESS  CurrentAPAddress;
+} NDIS_802_11_AI_REQFI, *PNDIS_802_11_AI_REQFI;
+
+typedef struct _NDIS_802_11_AI_RESFI {
+	USHORT Capabilities;
+	USHORT StatusCode;
+	USHORT AssociationId;
+} NDIS_802_11_AI_RESFI, *PNDIS_802_11_AI_RESFI;
+
+typedef struct _NDIS_802_11_ASSOCIATION_INFORMATION {
+	ULONG                   Length;
+	USHORT                  AvailableRequestFixedIEs;
+	NDIS_802_11_AI_REQFI    RequestFixedIEs;
+	ULONG                   RequestIELength;
+	ULONG                   OffsetRequestIEs;
+	USHORT                  AvailableResponseFixedIEs;
+	NDIS_802_11_AI_RESFI    ResponseFixedIEs;
+	ULONG                   ResponseIELength;
+	ULONG                   OffsetResponseIEs;
+} NDIS_802_11_ASSOCIATION_INFORMATION, *PNDIS_802_11_ASSOCIATION_INFORMATION;
+
+typedef enum _NDIS_802_11_RELOAD_DEFAULTS {
+	Ndis802_11ReloadWEPKeys
+} NDIS_802_11_RELOAD_DEFAULTS, *PNDIS_802_11_RELOAD_DEFAULTS;
+
+
+/* Key mapping keys require a BSSID */
+typedef struct _NDIS_802_11_KEY {
+	ULONG           Length;             /* Length of this structure */
+	ULONG           KeyIndex;
+	ULONG           KeyLength;          /* length of key in bytes */
+	NDIS_802_11_MAC_ADDRESS BSSID;
+	NDIS_802_11_KEY_RSC KeyRSC;
+	UCHAR           KeyMaterial[32];     /* variable length depending on above field */
+} NDIS_802_11_KEY, *PNDIS_802_11_KEY;
+
+typedef struct _NDIS_802_11_REMOVE_KEY {
+	ULONG                   Length;        /* Length of this structure */
+	ULONG                   KeyIndex;
+	NDIS_802_11_MAC_ADDRESS BSSID;
+} NDIS_802_11_REMOVE_KEY, *PNDIS_802_11_REMOVE_KEY;
+
+typedef struct _NDIS_802_11_WEP {
+	ULONG     Length;        /* Length of this structure */
+	ULONG     KeyIndex;      /* 0 is the per-client key, 1-N are the global keys */
+	ULONG     KeyLength;     /* length of key in bytes */
+	UCHAR     KeyMaterial[16];/* variable length depending on above field */
+} NDIS_802_11_WEP, *PNDIS_802_11_WEP;
+
+typedef struct _NDIS_802_11_AUTHENTICATION_REQUEST {
+	ULONG Length;            /* Length of structure */
+	NDIS_802_11_MAC_ADDRESS Bssid;
+	ULONG Flags;
+} NDIS_802_11_AUTHENTICATION_REQUEST, *PNDIS_802_11_AUTHENTICATION_REQUEST;
+
+typedef enum _NDIS_802_11_STATUS_TYPE {
+	Ndis802_11StatusType_Authentication,
+	Ndis802_11StatusType_MediaStreamMode,
+	Ndis802_11StatusType_PMKID_CandidateList,
+	Ndis802_11StatusTypeMax    /* not a real type, defined as an upper bound */
+} NDIS_802_11_STATUS_TYPE, *PNDIS_802_11_STATUS_TYPE;
+
+typedef struct _NDIS_802_11_STATUS_INDICATION {
+	NDIS_802_11_STATUS_TYPE StatusType;
+} NDIS_802_11_STATUS_INDICATION, *PNDIS_802_11_STATUS_INDICATION;
+
+/* mask for authentication/integrity fields */
+#define NDIS_802_11_AUTH_REQUEST_AUTH_FIELDS        0x0f
+#define NDIS_802_11_AUTH_REQUEST_REAUTH			0x01
+#define NDIS_802_11_AUTH_REQUEST_KEYUPDATE		0x02
+#define NDIS_802_11_AUTH_REQUEST_PAIRWISE_ERROR		0x06
+#define NDIS_802_11_AUTH_REQUEST_GROUP_ERROR		0x0E
+
+/* MIC check time, 60 seconds. */
+#define MIC_CHECK_TIME	60000000
+
+typedef struct _NDIS_802_11_AUTHENTICATION_EVENT {
+	NDIS_802_11_STATUS_INDICATION       Status;
+	NDIS_802_11_AUTHENTICATION_REQUEST  Request[1];
+} NDIS_802_11_AUTHENTICATION_EVENT, *PNDIS_802_11_AUTHENTICATION_EVENT;
+
+typedef struct _NDIS_802_11_TEST {
+	ULONG Length;
+	ULONG Type;
+	union {
+		NDIS_802_11_AUTHENTICATION_EVENT AuthenticationEvent;
+		NDIS_802_11_RSSI RssiTrigger;
+	} tt;
+} NDIS_802_11_TEST, *PNDIS_802_11_TEST;
+
+
+#endif /* PLATFORM_FREEBSD */
+#ifndef Ndis802_11APMode
+#define Ndis802_11APMode (Ndis802_11InfrastructureMax+1)
+#endif
+
+typedef struct _WLAN_PHY_INFO {
+	u8	SignalStrength;/* (in percentage) */
+	u8	SignalQuality;/* (in percentage) */
+	u8	Optimum_antenna;  /* for Antenna diversity */
+	u8	is_cck_rate;	/* 1:cck_rate */
+	s8	rx_snr[4];
+#ifdef CONFIG_RTW_80211K
+	u32	free_cnt; 	/* freerun counter */
+	u8	rm_en_cap[5];
+#endif
+} WLAN_PHY_INFO, *PWLAN_PHY_INFO;
+
+typedef struct _WLAN_BCN_INFO {
+	/* these infor get from rtw_get_encrypt_info when
+	 *	 * translate scan to UI */
+	u8 encryp_protocol;/* ENCRYP_PROTOCOL_E: OPEN/WEP/WPA/WPA2/WAPI */
+	int group_cipher; /* WPA/WPA2 group cipher */
+	int pairwise_cipher;/* //WPA/WPA2/WEP pairwise cipher */
+	int is_8021x;
+
+	/* bwmode 20/40 and ch_offset UP/LOW */
+	unsigned short	ht_cap_info;
+	unsigned char	ht_info_infos_0;
+} WLAN_BCN_INFO, *PWLAN_BCN_INFO;
+
+enum bss_type {
+	BSS_TYPE_UNDEF,
+	BSS_TYPE_BCN = 1,
+	BSS_TYPE_PROB_REQ = 2,
+	BSS_TYPE_PROB_RSP = 3,
+};
+
+/* temporally add #pragma pack for structure alignment issue of
+*   WLAN_BSSID_EX and get_WLAN_BSSID_EX_sz()
+*/
+#ifdef PLATFORM_WINDOWS
+#pragma pack(push)
+#pragma pack(1)
+#endif
+typedef struct _WLAN_BSSID_EX {
+	ULONG  Length;
+	NDIS_802_11_MAC_ADDRESS  MacAddress;
+	UCHAR  Reserved[2];/* [0]: IS beacon frame , bss_type*/
+	NDIS_802_11_SSID  Ssid;
+	NDIS_802_11_SSID  mesh_id;
+	ULONG  Privacy;
+	NDIS_802_11_RSSI  Rssi;/* (in dBM,raw data ,get from PHY) */
+	NDIS_802_11_NETWORK_TYPE  NetworkTypeInUse;
+	NDIS_802_11_CONFIGURATION  Configuration;
+	NDIS_802_11_NETWORK_INFRASTRUCTURE  InfrastructureMode;
+	NDIS_802_11_RATES_EX  SupportedRates;
+	WLAN_PHY_INFO	PhyInfo;
+	ULONG  IELength;
+	UCHAR  IEs[MAX_IE_SZ];	/* (timestamp, beacon interval, and capability information) */
+}
+#ifndef PLATFORM_WINDOWS
+__attribute__((packed))
+#endif
+WLAN_BSSID_EX, *PWLAN_BSSID_EX;
+#ifdef PLATFORM_WINDOWS
+#pragma pack(pop)
+#endif
+
+#define BSS_EX_IES(bss_ex) ((bss_ex)->IEs)
+#define BSS_EX_IES_LEN(bss_ex) ((bss_ex)->IELength)
+#define BSS_EX_FIXED_IE_OFFSET(bss_ex) ((bss_ex)->Reserved[0] == BSS_TYPE_PROB_REQ ? 0 : 12)
+#define BSS_EX_TLV_IES(bss_ex) (BSS_EX_IES((bss_ex)) + BSS_EX_FIXED_IE_OFFSET((bss_ex)))
+#define BSS_EX_TLV_IES_LEN(bss_ex) (BSS_EX_IES_LEN((bss_ex)) - BSS_EX_FIXED_IE_OFFSET((bss_ex)))
+
+__inline  static uint get_WLAN_BSSID_EX_sz(WLAN_BSSID_EX *bss)
+{
+#if 0
+	uint t_len;
+
+	t_len = sizeof(ULONG)
+		+ sizeof(NDIS_802_11_MAC_ADDRESS)
+		+ 2
+		+ sizeof(NDIS_802_11_SSID)
+		+ sizeof(ULONG)
+		+ sizeof(NDIS_802_11_RSSI)
+		+ sizeof(NDIS_802_11_NETWORK_TYPE)
+		+ sizeof(NDIS_802_11_CONFIGURATION)
+		+ sizeof(NDIS_802_11_NETWORK_INFRASTRUCTURE)
+		+ sizeof(NDIS_802_11_RATES_EX)
+		/* all new member add here */
+		+ sizeof(WLAN_PHY_INFO)
+		/* all new member add here */
+		+ sizeof(ULONG)
+		+ bss->IELength;
+	return t_len;
+#else
+	return sizeof(WLAN_BSSID_EX) - MAX_IE_SZ + bss->IELength;
+#endif
+}
+
+struct	wlan_network {
+	_list	list;
+	int	network_type;	/* refer to ieee80211.h for WIRELESS_11A/B/G */
+	int	fixed;			/* set to fixed when not to be removed as site-surveying */
+	systime last_scanned; /* timestamp for the network */
+#ifdef CONFIG_RTW_MESH
+#if CONFIG_RTW_MESH_ACNODE_PREVENT
+	systime acnode_stime;
+	systime acnode_notify_etime;
+#endif
+#endif
+	int	aid;			/* will only be valid when a BSS is joinned. */
+	int	join_res;
+	WLAN_BSSID_EX	network; /* must be the last item */
+	WLAN_BCN_INFO	BcnInfo;
+#ifdef PLATFORM_WINDOWS
+	unsigned char  iebuf[MAX_IE_SZ];
+#endif
+
+};
+
+enum VRTL_CARRIER_SENSE {
+	DISABLE_VCS,
+	ENABLE_VCS,
+	AUTO_VCS
+};
+
+enum VCS_TYPE {
+	NONE_VCS,
+	RTS_CTS,
+	CTS_TO_SELF
+};
+
+
+
+
+#define PWR_CAM 0
+#define PWR_MINPS 1
+#define PWR_MAXPS 2
+#define PWR_UAPSD 3
+#define PWR_VOIP 4
+
+
+enum UAPSD_MAX_SP {
+	NO_LIMIT,
+	TWO_MSDU,
+	FOUR_MSDU,
+	SIX_MSDU
+};
+
+
+/* john */
+#define NUM_PRE_AUTH_KEY 16
+#define NUM_PMKID_CACHE NUM_PRE_AUTH_KEY
+
+/*
+*	WPA2
+*/
+
+#ifndef PLATFORM_OS_CE
+typedef struct _PMKID_CANDIDATE {
+	NDIS_802_11_MAC_ADDRESS BSSID;
+	ULONG Flags;
+} PMKID_CANDIDATE, *PPMKID_CANDIDATE;
+
+typedef struct _NDIS_802_11_PMKID_CANDIDATE_LIST {
+	ULONG Version;       /* Version of the structure */
+	ULONG NumCandidates; /* No. of pmkid candidates */
+	PMKID_CANDIDATE CandidateList[1];
+} NDIS_802_11_PMKID_CANDIDATE_LIST, *PNDIS_802_11_PMKID_CANDIDATE_LIST;
+
+
+typedef struct _NDIS_802_11_AUTHENTICATION_ENCRYPTION {
+	NDIS_802_11_AUTHENTICATION_MODE AuthModeSupported;
+	NDIS_802_11_ENCRYPTION_STATUS EncryptStatusSupported;
+
+} NDIS_802_11_AUTHENTICATION_ENCRYPTION, *PNDIS_802_11_AUTHENTICATION_ENCRYPTION;
+
+typedef struct _NDIS_802_11_CAPABILITY {
+	ULONG  Length;
+	ULONG  Version;
+	ULONG  NoOfPMKIDs;
+	ULONG  NoOfAuthEncryptPairsSupported;
+	NDIS_802_11_AUTHENTICATION_ENCRYPTION AuthenticationEncryptionSupported[1];
+
+} NDIS_802_11_CAPABILITY, *PNDIS_802_11_CAPABILITY;
+#endif
+
+
+#endif /* #ifndef WLAN_BSSDEF_H_ */
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/include/xmit_osdep.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/xmit_osdep.h
--- linux-5.6.3/3rdparty/rtl8821ce/include/xmit_osdep.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/include/xmit_osdep.h	2020-04-10 16:35:06.853661795 +0300
@@ -0,0 +1,94 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#ifndef __XMIT_OSDEP_H_
+#define __XMIT_OSDEP_H_
+
+
+struct pkt_file {
+	_pkt *pkt;
+	SIZE_T pkt_len;	 /* the remainder length of the open_file */
+	_buffer *cur_buffer;
+	u8 *buf_start;
+	u8 *cur_addr;
+	SIZE_T buf_len;
+};
+
+#ifdef PLATFORM_WINDOWS
+
+#ifdef PLATFORM_OS_XP
+#ifdef CONFIG_USB_HCI
+#include <usb.h>
+#include <usbdlib.h>
+#include <usbioctl.h>
+#endif
+#endif
+
+#ifdef CONFIG_GSPI_HCI
+	#define NR_XMITFRAME     64
+#else
+	#define NR_XMITFRAME     128
+#endif
+
+#define ETH_ALEN	6
+
+extern NDIS_STATUS rtw_xmit_entry(
+	IN _nic_hdl		cnxt,
+	IN NDIS_PACKET		*pkt,
+	IN UINT				flags
+);
+
+#endif /* PLATFORM_WINDOWS */
+
+#ifdef PLATFORM_FREEBSD
+#define NR_XMITFRAME	256
+extern int rtw_xmit_entry(_pkt *pkt, _nic_hdl pnetdev);
+extern void rtw_xmit_entry_wrap(struct ifnet *pifp);
+#endif /* PLATFORM_FREEBSD */
+
+#ifdef PLATFORM_LINUX
+
+#define NR_XMITFRAME	256
+
+struct xmit_priv;
+struct pkt_attrib;
+struct sta_xmit_priv;
+struct xmit_frame;
+struct xmit_buf;
+
+extern int _rtw_xmit_entry(_pkt *pkt, _nic_hdl pnetdev);
+extern int rtw_xmit_entry(_pkt *pkt, _nic_hdl pnetdev);
+
+#endif /* PLATFORM_LINUX */
+
+void rtw_os_xmit_schedule(_adapter *padapter);
+
+int rtw_os_xmit_resource_alloc(_adapter *padapter, struct xmit_buf *pxmitbuf, u32 alloc_sz, u8 flag);
+void rtw_os_xmit_resource_free(_adapter *padapter, struct xmit_buf *pxmitbuf, u32 free_sz, u8 flag);
+
+extern void rtw_set_tx_chksum_offload(_pkt *pkt, struct pkt_attrib *pattrib);
+
+extern uint rtw_remainder_len(struct pkt_file *pfile);
+extern void _rtw_open_pktfile(_pkt *pkt, struct pkt_file *pfile);
+extern uint _rtw_pktfile_read(struct pkt_file *pfile, u8 *rmem, uint rlen);
+extern sint rtw_endofpktfile(struct pkt_file *pfile);
+
+extern void rtw_os_pkt_complete(_adapter *padapter, _pkt *pkt);
+extern void rtw_os_xmit_complete(_adapter *padapter, struct xmit_frame *pxframe);
+
+void rtw_os_wake_queue_at_free_stainfo(_adapter *padapter, int *qcnt_freed);
+
+void dump_os_queue(void *sel, _adapter *padapter);
+
+#endif /* __XMIT_OSDEP_H_ */
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/Kconfig linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/Kconfig
--- linux-5.6.3/3rdparty/rtl8821ce/Kconfig	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/Kconfig	2020-04-10 16:35:06.768657826 +0300
@@ -0,0 +1,6 @@
+config RTL8821CE
+	tristate "Realtek 8821C PCI WiFi"
+	depends on PCI
+	---help---
+	  Help message of RTL8821CE
+
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/Makefile linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/Makefile
--- linux-5.6.3/3rdparty/rtl8821ce/Makefile	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/Makefile	2020-04-10 16:35:06.768657826 +0300
@@ -0,0 +1,2313 @@
+EXTRA_CFLAGS += $(USER_EXTRA_CFLAGS)
+EXTRA_CFLAGS += -O1
+#EXTRA_CFLAGS += -O3
+#EXTRA_CFLAGS += -Wall
+#EXTRA_CFLAGS += -Wextra
+#EXTRA_CFLAGS += -Werror
+#EXTRA_CFLAGS += -pedantic
+#EXTRA_CFLAGS += -Wshadow -Wpointer-arith -Wcast-qual -Wstrict-prototypes -Wmissing-prototypes
+
+EXTRA_CFLAGS += -Wno-vla
+EXTRA_CFLAGS += -Wno-unused-variable
+EXTRA_CFLAGS += -Wno-unused-value
+EXTRA_CFLAGS += -Wno-unused-label
+EXTRA_CFLAGS += -Wno-unused-parameter
+EXTRA_CFLAGS += -Wno-unused-function
+EXTRA_CFLAGS += -Wno-unused
+#EXTRA_CFLAGS += -Wno-uninitialized
+
+GCC_VER_49 := $(shell echo `$(CC) -dumpversion | cut -f1-2 -d.` \>= 4.9 | bc )
+ifeq ($(GCC_VER_49),1)
+EXTRA_CFLAGS += -Wno-date-time	# Fix compile error && warning on gcc 4.9 and later
+endif
+
+ifeq (,$(srctree))
+    # make processing
+    export TopDIR ?= $(shell pwd)
+else
+    # dkms processing or in tree compilation
+    export TopDIR ?= $(srctree)/$(src)
+endif
+
+EXTRA_CFLAGS += -I$(TopDIR)/include
+
+EXTRA_LDFLAGS += --strip-debug
+
+CONFIG_AUTOCFG_CP = n
+
+########################## WIFI IC ############################
+CONFIG_MULTIDRV = n
+CONFIG_RTL8188E = n
+CONFIG_RTL8812A = n
+CONFIG_RTL8821A = n
+CONFIG_RTL8192E = n
+CONFIG_RTL8723B = n
+CONFIG_RTL8814A = n
+CONFIG_RTL8723C = n
+CONFIG_RTL8188F = n
+CONFIG_RTL8188GTV = n
+CONFIG_RTL8822B = n
+CONFIG_RTL8723D = n
+CONFIG_RTL8821C = y
+CONFIG_RTL8710B = n
+CONFIG_RTL8192F = n
+######################### Interface ###########################
+CONFIG_USB_HCI = n
+CONFIG_PCI_HCI = y
+CONFIG_SDIO_HCI = n
+CONFIG_GSPI_HCI = n
+########################## Features ###########################
+CONFIG_MP_INCLUDED = y
+CONFIG_POWER_SAVING = y
+CONFIG_USB_AUTOSUSPEND = n
+CONFIG_HW_PWRP_DETECTION = n
+CONFIG_WIFI_TEST = n
+CONFIG_BT_COEXIST = y
+CONFIG_INTEL_WIDI = n
+CONFIG_WAPI_SUPPORT = n
+CONFIG_EFUSE_CONFIG_FILE = y
+CONFIG_EXT_CLK = n
+CONFIG_TRAFFIC_PROTECT = n
+CONFIG_LOAD_PHY_PARA_FROM_FILE = y
+CONFIG_TXPWR_BY_RATE_EN = auto
+CONFIG_TXPWR_LIMIT_EN = auto
+CONFIG_RTW_CHPLAN = 0xFF
+CONFIG_RTW_ADAPTIVITY_EN = disable
+CONFIG_RTW_ADAPTIVITY_MODE = normal
+CONFIG_SIGNAL_SCALE_MAPPING = n
+CONFIG_80211W = n
+CONFIG_REDUCE_TX_CPU_LOADING = n
+CONFIG_BR_EXT = y
+CONFIG_TDLS = n
+CONFIG_WIFI_MONITOR = n
+CONFIG_MCC_MODE = n
+CONFIG_APPEND_VENDOR_IE_ENABLE = n
+CONFIG_RTW_NAPI = y
+CONFIG_RTW_GRO = y
+CONFIG_RTW_NETIF_SG = y
+CONFIG_TX_CSUM_OFFLOAD = n
+CONFIG_RTW_IPCAM_APPLICATION = n
+CONFIG_RTW_REPEATER_SON = n
+CONFIG_RTW_WIFI_HAL = n
+CONFIG_ICMP_VOQ = n
+########################## Debug ###########################
+CONFIG_RTW_DEBUG = n
+# default log level is _DRV_INFO_ = 4,
+# please refer to "How_to_set_driver_debug_log_level.doc" to set the available level.
+CONFIG_RTW_LOG_LEVEL = 4
+######################## Wake On Lan ##########################
+CONFIG_WOWLAN = n
+#bit2: deauth, bit1: unicast, bit0: magic pkt.
+CONFIG_WAKEUP_TYPE = 0x7
+CONFIG_GPIO_WAKEUP = n
+CONFIG_WAKEUP_GPIO_IDX = default
+CONFIG_HIGH_ACTIVE_DEV2HST = n
+######### only for USB #########
+CONFIG_ONE_PIN_GPIO = n
+CONFIG_HIGH_ACTIVE_HST2DEV = n
+CONFIG_PNO_SUPPORT = n
+CONFIG_PNO_SET_DEBUG = n
+CONFIG_AP_WOWLAN = n
+######### Notify SDIO Host Keep Power During Syspend ##########
+CONFIG_RTW_SDIO_PM_KEEP_POWER = y
+###################### MP HW TX MODE FOR VHT #######################
+CONFIG_MP_VHT_HW_TX_MODE = n
+###################### Platform Related #######################
+CONFIG_PLATFORM_I386_PC = y
+CONFIG_PLATFORM_ANDROID_X86 = n
+CONFIG_PLATFORM_ANDROID_INTEL_X86 = n
+CONFIG_PLATFORM_JB_X86 = n
+CONFIG_PLATFORM_ARM_S3C2K4 = n
+CONFIG_PLATFORM_ARM_PXA2XX = n
+CONFIG_PLATFORM_ARM_S3C6K4 = n
+CONFIG_PLATFORM_MIPS_RMI = n
+CONFIG_PLATFORM_RTD2880B = n
+CONFIG_PLATFORM_MIPS_AR9132 = n
+CONFIG_PLATFORM_RTK_DMP = n
+CONFIG_PLATFORM_MIPS_PLM = n
+CONFIG_PLATFORM_MSTAR389 = n
+CONFIG_PLATFORM_MT53XX = n
+CONFIG_PLATFORM_ARM_MX51_241H = n
+CONFIG_PLATFORM_FS_MX61 = n
+CONFIG_PLATFORM_ACTIONS_ATJ227X = n
+CONFIG_PLATFORM_TEGRA3_CARDHU = n
+CONFIG_PLATFORM_TEGRA4_DALMORE = n
+CONFIG_PLATFORM_ARM_TCC8900 = n
+CONFIG_PLATFORM_ARM_TCC8920 = n
+CONFIG_PLATFORM_ARM_TCC8920_JB42 = n
+CONFIG_PLATFORM_ARM_TCC8930_JB42 = n
+CONFIG_PLATFORM_ARM_RK2818 = n
+CONFIG_PLATFORM_ARM_RK3066 = n
+CONFIG_PLATFORM_ARM_RK3188 = n
+CONFIG_PLATFORM_ARM_URBETTER = n
+CONFIG_PLATFORM_ARM_TI_PANDA = n
+CONFIG_PLATFORM_MIPS_JZ4760 = n
+CONFIG_PLATFORM_DMP_PHILIPS = n
+CONFIG_PLATFORM_MSTAR_TITANIA12 = n
+CONFIG_PLATFORM_MSTAR = n
+CONFIG_PLATFORM_SZEBOOK = n
+CONFIG_PLATFORM_ARM_SUNxI = n
+CONFIG_PLATFORM_ARM_SUN6I = n
+CONFIG_PLATFORM_ARM_SUN7I = n
+CONFIG_PLATFORM_ARM_SUN8I_W3P1 = n
+CONFIG_PLATFORM_ARM_SUN8I_W5P1 = n
+CONFIG_PLATFORM_ACTIONS_ATM702X = n
+CONFIG_PLATFORM_ACTIONS_ATV5201 = n
+CONFIG_PLATFORM_ACTIONS_ATM705X = n
+CONFIG_PLATFORM_ARM_SUN50IW1P1 = n
+CONFIG_PLATFORM_ARM_RTD299X = n
+CONFIG_PLATFORM_ARM_LGE = n
+CONFIG_PLATFORM_ARM_SPREADTRUM_6820 = n
+CONFIG_PLATFORM_ARM_SPREADTRUM_8810 = n
+CONFIG_PLATFORM_ARM_WMT = n
+CONFIG_PLATFORM_TI_DM365 = n
+CONFIG_PLATFORM_MOZART = n
+CONFIG_PLATFORM_RTK119X = n
+CONFIG_PLATFORM_RTK119X_AM = n
+CONFIG_PLATFORM_RTK129X = n
+CONFIG_PLATFORM_RTK390X = n
+CONFIG_PLATFORM_NOVATEK_NT72668 = n
+CONFIG_PLATFORM_HISILICON = n
+CONFIG_PLATFORM_HISILICON_HI3798 = n
+CONFIG_PLATFORM_NV_TK1 = n
+CONFIG_PLATFORM_NV_TK1_UBUNTU = n
+CONFIG_PLATFORM_RTL8197D = n
+CONFIG_PLATFORM_AML_S905 = n
+CONFIG_PLATFORM_ZTE_ZX296716 = n
+########### CUSTOMER ################################
+CONFIG_CUSTOMER_HUAWEI_GENERAL = n
+
+CONFIG_DRVEXT_MODULE = n
+
+########### COMMON  #################################
+ifeq ($(CONFIG_GSPI_HCI), y)
+HCI_NAME = gspi
+endif
+
+ifeq ($(CONFIG_SDIO_HCI), y)
+HCI_NAME = sdio
+endif
+
+ifeq ($(CONFIG_USB_HCI), y)
+HCI_NAME = usb
+endif
+
+ifeq ($(CONFIG_PCI_HCI), y)
+HCI_NAME = pci
+endif
+
+
+_OS_INTFS_FILES :=	os_dep/osdep_service.o \
+			os_dep/linux/os_intfs.o \
+			os_dep/linux/$(HCI_NAME)_intf.o \
+			os_dep/linux/$(HCI_NAME)_ops_linux.o \
+			os_dep/linux/ioctl_linux.o \
+			os_dep/linux/xmit_linux.o \
+			os_dep/linux/mlme_linux.o \
+			os_dep/linux/recv_linux.o \
+			os_dep/linux/ioctl_cfg80211.o \
+			os_dep/linux/rtw_cfgvendor.o \
+			os_dep/linux/wifi_regd.o \
+			os_dep/linux/rtw_android.o \
+			os_dep/linux/rtw_proc.o \
+			os_dep/linux/rtw_rhashtable.o
+
+ifeq ($(CONFIG_MP_INCLUDED), y)
+_OS_INTFS_FILES += os_dep/linux/ioctl_mp.o
+endif
+
+ifeq ($(CONFIG_SDIO_HCI), y)
+_OS_INTFS_FILES += os_dep/linux/custom_gpio_linux.o
+_OS_INTFS_FILES += os_dep/linux/$(HCI_NAME)_ops_linux.o
+endif
+
+ifeq ($(CONFIG_GSPI_HCI), y)
+_OS_INTFS_FILES += os_dep/linux/custom_gpio_linux.o
+_OS_INTFS_FILES += os_dep/linux/$(HCI_NAME)_ops_linux.o
+endif
+
+
+_HAL_INTFS_FILES :=	hal/hal_intf.o \
+			hal/hal_com.o \
+			hal/hal_com_phycfg.o \
+			hal/hal_phy.o \
+			hal/hal_dm.o \
+			hal/hal_dm_acs.o \
+			hal/hal_btcoex_wifionly.o \
+			hal/hal_btcoex.o \
+			hal/hal_mp.o \
+			hal/hal_mcc.o \
+			hal/hal_hci/hal_$(HCI_NAME).o \
+			hal/led/hal_led.o \
+			hal/led/hal_$(HCI_NAME)_led.o
+
+
+EXTRA_CFLAGS += -I$(TopDIR)/platform
+_PLATFORM_FILES := platform/platform_ops.o
+
+EXTRA_CFLAGS += -I$(TopDIR)/hal/btc
+
+########### HAL_RTL8188E #################################
+ifeq ($(CONFIG_RTL8188E), y)
+
+RTL871X = rtl8188e
+ifeq ($(CONFIG_SDIO_HCI), y)
+MODULE_NAME = 8189es
+endif
+
+ifeq ($(CONFIG_GSPI_HCI), y)
+MODULE_NAME = 8189es
+endif
+
+ifeq ($(CONFIG_USB_HCI), y)
+MODULE_NAME = 8188eu
+endif
+
+ifeq ($(CONFIG_PCI_HCI), y)
+MODULE_NAME = 8188ee
+endif
+EXTRA_CFLAGS += -DCONFIG_RTL8188E
+
+_HAL_INTFS_FILES +=	hal/HalPwrSeqCmd.o \
+					hal/$(RTL871X)/Hal8188EPwrSeq.o\
+					hal/$(RTL871X)/$(RTL871X)_xmit.o\
+					hal/$(RTL871X)/$(RTL871X)_sreset.o
+
+_HAL_INTFS_FILES +=	hal/$(RTL871X)/$(RTL871X)_hal_init.o \
+			hal/$(RTL871X)/$(RTL871X)_phycfg.o \
+			hal/$(RTL871X)/$(RTL871X)_rf6052.o \
+			hal/$(RTL871X)/$(RTL871X)_dm.o \
+			hal/$(RTL871X)/$(RTL871X)_rxdesc.o \
+			hal/$(RTL871X)/$(RTL871X)_cmd.o \
+			hal/$(RTL871X)/hal8188e_s_fw.o \
+			hal/$(RTL871X)/hal8188e_t_fw.o \
+			hal/$(RTL871X)/$(HCI_NAME)/$(HCI_NAME)_halinit.o \
+			hal/$(RTL871X)/$(HCI_NAME)/rtl$(MODULE_NAME)_led.o \
+			hal/$(RTL871X)/$(HCI_NAME)/rtl$(MODULE_NAME)_xmit.o \
+			hal/$(RTL871X)/$(HCI_NAME)/rtl$(MODULE_NAME)_recv.o
+
+ifeq ($(CONFIG_SDIO_HCI), y)
+_HAL_INTFS_FILES += hal/$(RTL871X)/$(HCI_NAME)/$(HCI_NAME)_ops.o
+else
+ifeq ($(CONFIG_GSPI_HCI), y)
+_HAL_INTFS_FILES += hal/$(RTL871X)/$(HCI_NAME)/$(HCI_NAME)_ops.o
+else
+_HAL_INTFS_FILES += hal/$(RTL871X)/$(HCI_NAME)/$(HCI_NAME)_ops_linux.o
+endif
+endif
+
+ifeq ($(CONFIG_USB_HCI), y)
+_HAL_INTFS_FILES +=hal/efuse/$(RTL871X)/HalEfuseMask8188E_USB.o
+endif
+ifeq ($(CONFIG_PCI_HCI), y)
+_HAL_INTFS_FILES +=hal/efuse/$(RTL871X)/HalEfuseMask8188E_PCIE.o
+endif
+ifeq ($(CONFIG_SDIO_HCI), y)
+_HAL_INTFS_FILES +=hal/efuse/$(RTL871X)/HalEfuseMask8188E_SDIO.o
+endif
+
+endif
+
+########### HAL_RTL8192E #################################
+ifeq ($(CONFIG_RTL8192E), y)
+
+RTL871X = rtl8192e
+ifeq ($(CONFIG_SDIO_HCI), y)
+MODULE_NAME = 8192es
+endif
+
+ifeq ($(CONFIG_USB_HCI), y)
+MODULE_NAME = 8192eu
+endif
+
+ifeq ($(CONFIG_PCI_HCI), y)
+MODULE_NAME = 8192ee
+endif
+EXTRA_CFLAGS += -DCONFIG_RTL8192E
+_HAL_INTFS_FILES += hal/HalPwrSeqCmd.o \
+					hal/$(RTL871X)/Hal8192EPwrSeq.o\
+					hal/$(RTL871X)/$(RTL871X)_xmit.o\
+					hal/$(RTL871X)/$(RTL871X)_sreset.o
+
+_HAL_INTFS_FILES +=	hal/$(RTL871X)/$(RTL871X)_hal_init.o \
+			hal/$(RTL871X)/$(RTL871X)_phycfg.o \
+			hal/$(RTL871X)/$(RTL871X)_rf6052.o \
+			hal/$(RTL871X)/$(RTL871X)_dm.o \
+			hal/$(RTL871X)/$(RTL871X)_rxdesc.o \
+			hal/$(RTL871X)/$(RTL871X)_cmd.o \
+			hal/$(RTL871X)/hal8192e_fw.o \
+			hal/$(RTL871X)/$(HCI_NAME)/$(HCI_NAME)_halinit.o \
+			hal/$(RTL871X)/$(HCI_NAME)/rtl$(MODULE_NAME)_led.o \
+			hal/$(RTL871X)/$(HCI_NAME)/rtl$(MODULE_NAME)_xmit.o \
+			hal/$(RTL871X)/$(HCI_NAME)/rtl$(MODULE_NAME)_recv.o
+
+ifeq ($(CONFIG_SDIO_HCI), y)
+_HAL_INTFS_FILES += hal/$(RTL871X)/$(HCI_NAME)/$(HCI_NAME)_ops.o
+else
+ifeq ($(CONFIG_GSPI_HCI), y)
+_HAL_INTFS_FILES += hal/$(RTL871X)/$(HCI_NAME)/$(HCI_NAME)_ops.o
+else
+_HAL_INTFS_FILES += hal/$(RTL871X)/$(HCI_NAME)/$(HCI_NAME)_ops_linux.o
+endif
+endif
+
+ifeq ($(CONFIG_USB_HCI), y)
+_HAL_INTFS_FILES +=hal/efuse/$(RTL871X)/HalEfuseMask8192E_USB.o
+endif
+ifeq ($(CONFIG_PCI_HCI), y)
+_HAL_INTFS_FILES +=hal/efuse/$(RTL871X)/HalEfuseMask8192E_PCIE.o
+endif
+ifeq ($(CONFIG_SDIO_HCI), y)
+_HAL_INTFS_FILES +=hal/efuse/$(RTL871X)/HalEfuseMask8192E_SDIO.o
+endif
+
+ifeq ($(CONFIG_BT_COEXIST), y)
+_BTC_FILES += hal/btc/halbtc8192e1ant.o \
+				hal/btc/halbtc8192e2ant.o
+endif
+
+endif
+
+########### HAL_RTL8812A_RTL8821A #################################
+
+ifneq ($(CONFIG_RTL8812A)_$(CONFIG_RTL8821A), n_n)
+
+RTL871X = rtl8812a
+ifeq ($(CONFIG_USB_HCI), y)
+MODULE_NAME = 8812au
+endif
+ifeq ($(CONFIG_PCI_HCI), y)
+MODULE_NAME = 8812ae
+endif
+ifeq ($(CONFIG_SDIO_HCI), y)
+MODULE_NAME = 8812as
+endif
+
+_HAL_INTFS_FILES +=  hal/HalPwrSeqCmd.o \
+					hal/$(RTL871X)/Hal8812PwrSeq.o \
+					hal/$(RTL871X)/Hal8821APwrSeq.o\
+					hal/$(RTL871X)/$(RTL871X)_xmit.o\
+					hal/$(RTL871X)/$(RTL871X)_sreset.o
+
+_HAL_INTFS_FILES +=	hal/$(RTL871X)/$(RTL871X)_hal_init.o \
+			hal/$(RTL871X)/$(RTL871X)_phycfg.o \
+			hal/$(RTL871X)/$(RTL871X)_rf6052.o \
+			hal/$(RTL871X)/$(RTL871X)_dm.o \
+			hal/$(RTL871X)/$(RTL871X)_rxdesc.o \
+			hal/$(RTL871X)/$(RTL871X)_cmd.o \
+			hal/$(RTL871X)/$(HCI_NAME)/$(HCI_NAME)_halinit.o \
+			hal/$(RTL871X)/$(HCI_NAME)/rtl$(MODULE_NAME)_led.o \
+			hal/$(RTL871X)/$(HCI_NAME)/rtl$(MODULE_NAME)_xmit.o \
+			hal/$(RTL871X)/$(HCI_NAME)/rtl$(MODULE_NAME)_recv.o
+
+ifeq ($(CONFIG_SDIO_HCI), y)
+_HAL_INTFS_FILES += hal/$(RTL871X)/$(HCI_NAME)/$(HCI_NAME)_ops.o
+else
+ifeq ($(CONFIG_GSPI_HCI), y)
+_HAL_INTFS_FILES += hal/$(RTL871X)/$(HCI_NAME)/$(HCI_NAME)_ops.o
+else
+_HAL_INTFS_FILES += hal/$(RTL871X)/$(HCI_NAME)/$(HCI_NAME)_ops_linux.o
+endif
+endif
+
+ifeq ($(CONFIG_RTL8812A), y)
+ifeq ($(CONFIG_USB_HCI), y)
+_HAL_INTFS_FILES +=hal/efuse/$(RTL871X)/HalEfuseMask8812A_USB.o
+endif
+ifeq ($(CONFIG_PCI_HCI), y)
+_HAL_INTFS_FILES +=hal/efuse/$(RTL871X)/HalEfuseMask8812A_PCIE.o
+endif
+endif
+ifeq ($(CONFIG_RTL8821A), y)
+ifeq ($(CONFIG_USB_HCI), y)
+_HAL_INTFS_FILES +=hal/efuse/$(RTL871X)/HalEfuseMask8821A_USB.o
+endif
+ifeq ($(CONFIG_PCI_HCI), y)
+_HAL_INTFS_FILES +=hal/efuse/$(RTL871X)/HalEfuseMask8821A_PCIE.o
+endif
+ifeq ($(CONFIG_SDIO_HCI), y)
+_HAL_INTFS_FILES +=hal/efuse/$(RTL871X)/HalEfuseMask8821A_SDIO.o
+endif
+endif
+
+ifeq ($(CONFIG_RTL8812A), y)
+EXTRA_CFLAGS += -DCONFIG_RTL8812A
+_HAL_INTFS_FILES +=	hal/rtl8812a/hal8812a_fw.o
+endif
+
+ifeq ($(CONFIG_RTL8821A), y)
+
+ifeq ($(CONFIG_RTL8812A), n)
+
+RTL871X = rtl8821a
+ifeq ($(CONFIG_USB_HCI), y)
+ifeq ($(CONFIG_BT_COEXIST), y)
+MODULE_NAME := 8821au
+else
+MODULE_NAME := 8811au
+endif
+endif
+ifeq ($(CONFIG_PCI_HCI), y)
+MODULE_NAME := 8821ae
+endif
+ifeq ($(CONFIG_SDIO_HCI), y)
+MODULE_NAME := 8821as
+endif
+
+endif
+
+EXTRA_CFLAGS += -DCONFIG_RTL8821A
+
+_HAL_INTFS_FILES +=	hal/rtl8812a/hal8821a_fw.o
+
+endif
+
+ifeq ($(CONFIG_BT_COEXIST), y)
+ifeq ($(CONFIG_RTL8812A), y)
+_BTC_FILES += hal/btc/halbtc8812a1ant.o \
+				hal/btc/halbtc8812a2ant.o
+endif
+ifeq ($(CONFIG_RTL8821A), y)
+_BTC_FILES += hal/btc/halbtc8821a1ant.o \
+				hal/btc/halbtc8821a2ant.o
+endif
+endif
+
+endif
+
+########### HAL_RTL8723B #################################
+ifeq ($(CONFIG_RTL8723B), y)
+
+RTL871X = rtl8723b
+ifeq ($(CONFIG_USB_HCI), y)
+MODULE_NAME = 8723bu
+endif
+ifeq ($(CONFIG_PCI_HCI), y)
+MODULE_NAME = 8723be
+endif
+ifeq ($(CONFIG_SDIO_HCI), y)
+MODULE_NAME = 8723bs
+endif
+
+EXTRA_CFLAGS += -DCONFIG_RTL8723B
+
+_HAL_INTFS_FILES += hal/HalPwrSeqCmd.o \
+					hal/$(RTL871X)/Hal8723BPwrSeq.o\
+					hal/$(RTL871X)/$(RTL871X)_sreset.o
+
+_HAL_INTFS_FILES +=	hal/$(RTL871X)/$(RTL871X)_hal_init.o \
+			hal/$(RTL871X)/$(RTL871X)_phycfg.o \
+			hal/$(RTL871X)/$(RTL871X)_rf6052.o \
+			hal/$(RTL871X)/$(RTL871X)_dm.o \
+			hal/$(RTL871X)/$(RTL871X)_rxdesc.o \
+			hal/$(RTL871X)/$(RTL871X)_cmd.o \
+			hal/$(RTL871X)/hal8723b_fw.o
+
+_HAL_INTFS_FILES +=	\
+			hal/$(RTL871X)/$(HCI_NAME)/$(HCI_NAME)_halinit.o \
+			hal/$(RTL871X)/$(HCI_NAME)/rtl$(MODULE_NAME)_led.o \
+			hal/$(RTL871X)/$(HCI_NAME)/rtl$(MODULE_NAME)_xmit.o \
+			hal/$(RTL871X)/$(HCI_NAME)/rtl$(MODULE_NAME)_recv.o
+
+ifeq ($(CONFIG_PCI_HCI), y)
+_HAL_INTFS_FILES += hal/$(RTL871X)/$(HCI_NAME)/$(HCI_NAME)_ops_linux.o
+else
+_HAL_INTFS_FILES += hal/$(RTL871X)/$(HCI_NAME)/$(HCI_NAME)_ops.o
+endif
+
+ifeq ($(CONFIG_USB_HCI), y)
+_HAL_INTFS_FILES +=hal/efuse/$(RTL871X)/HalEfuseMask8723B_USB.o
+endif
+ifeq ($(CONFIG_PCI_HCI), y)
+_HAL_INTFS_FILES +=hal/efuse/$(RTL871X)/HalEfuseMask8723B_PCIE.o
+endif
+ifeq ($(CONFIG_SDIO_HCI), y)
+_HAL_INTFS_FILES +=hal/efuse/$(RTL871X)/HalEfuseMask8723B_SDIO.o
+endif
+
+_BTC_FILES += hal/btc/halbtc8723bwifionly.o
+ifeq ($(CONFIG_BT_COEXIST), y)
+_BTC_FILES += hal/btc/halbtc8723b1ant.o \
+				hal/btc/halbtc8723b2ant.o
+endif
+
+endif
+
+########### HAL_RTL8814A #################################
+ifeq ($(CONFIG_RTL8814A), y)
+## ADD NEW VHT MP HW TX MODE ##
+#EXTRA_CFLAGS += -DCONFIG_MP_VHT_HW_TX_MODE
+#CONFIG_MP_VHT_HW_TX_MODE = y
+##########################################
+RTL871X = rtl8814a
+ifeq ($(CONFIG_USB_HCI), y)
+MODULE_NAME = 8814au
+endif
+ifeq ($(CONFIG_PCI_HCI), y)
+MODULE_NAME = 8814ae
+endif
+ifeq ($(CONFIG_SDIO_HCI), y)
+MODULE_NAME = 8814as
+endif
+
+EXTRA_CFLAGS += -DCONFIG_RTL8814A
+
+_HAL_INTFS_FILES +=  hal/HalPwrSeqCmd.o \
+					hal/$(RTL871X)/Hal8814PwrSeq.o \
+					hal/$(RTL871X)/$(RTL871X)_xmit.o\
+					hal/$(RTL871X)/$(RTL871X)_sreset.o
+
+_HAL_INTFS_FILES +=	hal/$(RTL871X)/$(RTL871X)_hal_init.o \
+			hal/$(RTL871X)/$(RTL871X)_phycfg.o \
+			hal/$(RTL871X)/$(RTL871X)_rf6052.o \
+			hal/$(RTL871X)/$(RTL871X)_dm.o \
+			hal/$(RTL871X)/$(RTL871X)_rxdesc.o \
+			hal/$(RTL871X)/$(RTL871X)_cmd.o \
+			hal/$(RTL871X)/hal8814a_fw.o
+
+
+_HAL_INTFS_FILES +=	\
+			hal/$(RTL871X)/$(HCI_NAME)/$(HCI_NAME)_halinit.o \
+			hal/$(RTL871X)/$(HCI_NAME)/rtl$(MODULE_NAME)_led.o \
+			hal/$(RTL871X)/$(HCI_NAME)/rtl$(MODULE_NAME)_xmit.o \
+			hal/$(RTL871X)/$(HCI_NAME)/rtl$(MODULE_NAME)_recv.o
+
+ifeq ($(CONFIG_SDIO_HCI), y)
+_HAL_INTFS_FILES += hal/$(RTL871X)/$(HCI_NAME)/$(HCI_NAME)_ops.o
+else
+ifeq ($(CONFIG_GSPI_HCI), y)
+_HAL_INTFS_FILES += hal/$(RTL871X)/$(HCI_NAME)/$(HCI_NAME)_ops.o
+else
+_HAL_INTFS_FILES += hal/$(RTL871X)/$(HCI_NAME)/$(HCI_NAME)_ops_linux.o
+endif
+endif
+
+ifeq ($(CONFIG_USB_HCI), y)
+_HAL_INTFS_FILES +=hal/efuse/$(RTL871X)/HalEfuseMask8814A_USB.o
+endif
+ifeq ($(CONFIG_PCI_HCI), y)
+_HAL_INTFS_FILES +=hal/efuse/$(RTL871X)/HalEfuseMask8814A_PCIE.o
+endif
+
+endif
+
+########### HAL_RTL8723C #################################
+ifeq ($(CONFIG_RTL8723C), y)
+
+RTL871X = rtl8703b
+ifeq ($(CONFIG_USB_HCI), y)
+MODULE_NAME = 8723cu
+MODULE_SUB_NAME = 8703bu
+endif
+ifeq ($(CONFIG_PCI_HCI), y)
+MODULE_NAME = 8723ce
+MODULE_SUB_NAME = 8703be
+endif
+ifeq ($(CONFIG_SDIO_HCI), y)
+MODULE_NAME = 8723cs
+MODULE_SUB_NAME = 8703bs
+endif
+
+EXTRA_CFLAGS += -DCONFIG_RTL8703B
+
+_HAL_INTFS_FILES += hal/HalPwrSeqCmd.o \
+					hal/$(RTL871X)/Hal8703BPwrSeq.o\
+					hal/$(RTL871X)/$(RTL871X)_sreset.o
+
+_HAL_INTFS_FILES +=	hal/$(RTL871X)/$(RTL871X)_hal_init.o \
+			hal/$(RTL871X)/$(RTL871X)_phycfg.o \
+			hal/$(RTL871X)/$(RTL871X)_rf6052.o \
+			hal/$(RTL871X)/$(RTL871X)_dm.o \
+			hal/$(RTL871X)/$(RTL871X)_rxdesc.o \
+			hal/$(RTL871X)/$(RTL871X)_cmd.o \
+			hal/$(RTL871X)/hal8703b_fw.o
+
+_HAL_INTFS_FILES +=	\
+			hal/$(RTL871X)/$(HCI_NAME)/$(HCI_NAME)_halinit.o \
+			hal/$(RTL871X)/$(HCI_NAME)/rtl$(MODULE_SUB_NAME)_led.o \
+			hal/$(RTL871X)/$(HCI_NAME)/rtl$(MODULE_SUB_NAME)_xmit.o \
+			hal/$(RTL871X)/$(HCI_NAME)/rtl$(MODULE_SUB_NAME)_recv.o
+
+ifeq ($(CONFIG_PCI_HCI), y)
+_HAL_INTFS_FILES += hal/$(RTL871X)/$(HCI_NAME)/$(HCI_NAME)_ops_linux.o
+else
+_HAL_INTFS_FILES += hal/$(RTL871X)/$(HCI_NAME)/$(HCI_NAME)_ops.o
+endif
+
+ifeq ($(CONFIG_USB_HCI), y)
+_HAL_INTFS_FILES +=hal/efuse/$(RTL871X)/HalEfuseMask8703B_USB.o
+endif
+ifeq ($(CONFIG_PCI_HCI), y)
+_HAL_INTFS_FILES +=hal/efuse/$(RTL871X)/HalEfuseMask8703B_PCIE.o
+endif
+
+ifeq ($(CONFIG_BT_COEXIST), y)
+_BTC_FILES += hal/btc/halbtc8703b1ant.o
+endif
+
+endif
+
+########### HAL_RTL8723D #################################
+ifeq ($(CONFIG_RTL8723D), y)
+
+RTL871X = rtl8723d
+ifeq ($(CONFIG_USB_HCI), y)
+MODULE_NAME = 8723du
+MODULE_SUB_NAME = 8723du
+endif
+ifeq ($(CONFIG_PCI_HCI), y)
+MODULE_NAME = 8723de
+MODULE_SUB_NAME = 8723de
+endif
+ifeq ($(CONFIG_SDIO_HCI), y)
+MODULE_NAME = 8723ds
+MODULE_SUB_NAME = 8723ds
+endif
+
+EXTRA_CFLAGS += -DCONFIG_RTL8723D
+
+_HAL_INTFS_FILES += hal/HalPwrSeqCmd.o \
+					hal/$(RTL871X)/Hal8723DPwrSeq.o\
+					hal/$(RTL871X)/$(RTL871X)_sreset.o
+
+_HAL_INTFS_FILES +=	hal/$(RTL871X)/$(RTL871X)_hal_init.o \
+			hal/$(RTL871X)/$(RTL871X)_phycfg.o \
+			hal/$(RTL871X)/$(RTL871X)_rf6052.o \
+			hal/$(RTL871X)/$(RTL871X)_dm.o \
+			hal/$(RTL871X)/$(RTL871X)_rxdesc.o \
+			hal/$(RTL871X)/$(RTL871X)_cmd.o \
+			hal/$(RTL871X)/hal8723d_fw.o \
+			hal/$(RTL871X)/$(RTL871X)_lps_poff.o
+
+
+_HAL_INTFS_FILES +=	\
+			hal/$(RTL871X)/$(HCI_NAME)/$(HCI_NAME)_halinit.o \
+			hal/$(RTL871X)/$(HCI_NAME)/rtl$(MODULE_SUB_NAME)_led.o \
+			hal/$(RTL871X)/$(HCI_NAME)/rtl$(MODULE_SUB_NAME)_xmit.o \
+			hal/$(RTL871X)/$(HCI_NAME)/rtl$(MODULE_SUB_NAME)_recv.o
+
+ifeq ($(CONFIG_PCI_HCI), y)
+_HAL_INTFS_FILES += hal/$(RTL871X)/$(HCI_NAME)/$(HCI_NAME)_ops_linux.o
+else
+_HAL_INTFS_FILES += hal/$(RTL871X)/$(HCI_NAME)/$(HCI_NAME)_ops.o
+endif
+
+ifeq ($(CONFIG_USB_HCI), y)
+_HAL_INTFS_FILES +=hal/efuse/$(RTL871X)/HalEfuseMask8723D_USB.o
+endif
+ifeq ($(CONFIG_PCI_HCI), y)
+_HAL_INTFS_FILES +=hal/efuse/$(RTL871X)/HalEfuseMask8723D_PCIE.o
+endif
+
+ifeq ($(CONFIG_BT_COEXIST), y)
+_BTC_FILES += hal/btc/halbtc8723d1ant.o \
+				hal/btc/halbtc8723d2ant.o
+endif
+
+endif
+
+########### HAL_RTL8188F #################################
+ifeq ($(CONFIG_RTL8188F), y)
+
+RTL871X = rtl8188f
+ifeq ($(CONFIG_USB_HCI), y)
+MODULE_NAME = 8188fu
+endif
+ifeq ($(CONFIG_PCI_HCI), y)
+MODULE_NAME = 8188fe
+endif
+ifeq ($(CONFIG_SDIO_HCI), y)
+MODULE_NAME = 8189fs
+endif
+
+EXTRA_CFLAGS += -DCONFIG_RTL8188F
+
+_HAL_INTFS_FILES += hal/HalPwrSeqCmd.o \
+					hal/$(RTL871X)/Hal8188FPwrSeq.o\
+					hal/$(RTL871X)/$(RTL871X)_sreset.o
+
+_HAL_INTFS_FILES +=	hal/$(RTL871X)/$(RTL871X)_hal_init.o \
+			hal/$(RTL871X)/$(RTL871X)_phycfg.o \
+			hal/$(RTL871X)/$(RTL871X)_rf6052.o \
+			hal/$(RTL871X)/$(RTL871X)_dm.o \
+			hal/$(RTL871X)/$(RTL871X)_rxdesc.o \
+			hal/$(RTL871X)/$(RTL871X)_cmd.o \
+			hal/$(RTL871X)/hal8188f_fw.o
+
+_HAL_INTFS_FILES +=	\
+			hal/$(RTL871X)/$(HCI_NAME)/$(HCI_NAME)_halinit.o \
+			hal/$(RTL871X)/$(HCI_NAME)/rtl$(MODULE_NAME)_led.o \
+			hal/$(RTL871X)/$(HCI_NAME)/rtl$(MODULE_NAME)_xmit.o \
+			hal/$(RTL871X)/$(HCI_NAME)/rtl$(MODULE_NAME)_recv.o
+
+ifeq ($(CONFIG_PCI_HCI), y)
+_HAL_INTFS_FILES += hal/$(RTL871X)/$(HCI_NAME)/$(HCI_NAME)_ops_linux.o
+else
+_HAL_INTFS_FILES += hal/$(RTL871X)/$(HCI_NAME)/$(HCI_NAME)_ops.o
+endif
+
+ifeq ($(CONFIG_USB_HCI), y)
+_HAL_INTFS_FILES +=hal/efuse/$(RTL871X)/HalEfuseMask8188F_USB.o
+endif
+
+ifeq ($(CONFIG_SDIO_HCI), y)
+_HAL_INTFS_FILES +=hal/efuse/$(RTL871X)/HalEfuseMask8188F_SDIO.o
+endif
+
+endif
+
+########### HAL_RTL8188GTV #################################
+ifeq ($(CONFIG_RTL8188GTV), y)
+
+RTL871X = rtl8188gtv
+ifeq ($(CONFIG_USB_HCI), y)
+MODULE_NAME = 8188gtvu
+endif
+ifeq ($(CONFIG_SDIO_HCI), y)
+MODULE_NAME = 8189gtvs
+endif
+
+EXTRA_CFLAGS += -DCONFIG_RTL8188GTV
+
+_HAL_INTFS_FILES += hal/HalPwrSeqCmd.o \
+					hal/$(RTL871X)/Hal8188GTVPwrSeq.o\
+					hal/$(RTL871X)/$(RTL871X)_sreset.o
+
+_HAL_INTFS_FILES +=	hal/$(RTL871X)/$(RTL871X)_hal_init.o \
+			hal/$(RTL871X)/$(RTL871X)_phycfg.o \
+			hal/$(RTL871X)/$(RTL871X)_rf6052.o \
+			hal/$(RTL871X)/$(RTL871X)_dm.o \
+			hal/$(RTL871X)/$(RTL871X)_rxdesc.o \
+			hal/$(RTL871X)/$(RTL871X)_cmd.o \
+			hal/$(RTL871X)/hal8188gtv_fw.o
+
+_HAL_INTFS_FILES +=	\
+			hal/$(RTL871X)/$(HCI_NAME)/$(HCI_NAME)_halinit.o \
+			hal/$(RTL871X)/$(HCI_NAME)/rtl$(MODULE_NAME)_led.o \
+			hal/$(RTL871X)/$(HCI_NAME)/rtl$(MODULE_NAME)_xmit.o \
+			hal/$(RTL871X)/$(HCI_NAME)/rtl$(MODULE_NAME)_recv.o
+
+ifeq ($(CONFIG_PCI_HCI), y)
+_HAL_INTFS_FILES += hal/$(RTL871X)/$(HCI_NAME)/$(HCI_NAME)_ops_linux.o
+else
+_HAL_INTFS_FILES += hal/$(RTL871X)/$(HCI_NAME)/$(HCI_NAME)_ops.o
+endif
+
+ifeq ($(CONFIG_USB_HCI), y)
+_HAL_INTFS_FILES +=hal/efuse/$(RTL871X)/HalEfuseMask8188GTV_USB.o
+endif
+
+ifeq ($(CONFIG_SDIO_HCI), y)
+_HAL_INTFS_FILES +=hal/efuse/$(RTL871X)/HalEfuseMask8188GTV_SDIO.o
+endif
+
+endif
+
+########### HAL_RTL8822B #################################
+ifeq ($(CONFIG_RTL8822B), y)
+RTL871X := rtl8822b
+ifeq ($(CONFIG_USB_HCI), y)
+ifeq ($(CONFIG_BT_COEXIST), n)
+MODULE_NAME = 8812bu
+else
+MODULE_NAME = 88x2bu
+endif
+endif
+ifeq ($(CONFIG_PCI_HCI), y)
+MODULE_NAME = 88x2be
+endif
+ifeq ($(CONFIG_SDIO_HCI), y)
+MODULE_NAME = 88x2bs
+endif
+
+endif
+########### HAL_RTL8821C #################################
+ifeq ($(CONFIG_RTL8821C), y)
+RTL871X := rtl8821c
+ifeq ($(CONFIG_USB_HCI), y)
+MODULE_NAME = 8821cu
+endif
+ifeq ($(CONFIG_PCI_HCI), y)
+MODULE_NAME = 8821ce
+endif
+ifeq ($(CONFIG_SDIO_HCI), y)
+MODULE_NAME = 8821cs
+endif
+
+endif
+
+########### HAL_RTL8710B #################################
+ifeq ($(CONFIG_RTL8710B), y)
+
+RTL871X = rtl8710b
+ifeq ($(CONFIG_USB_HCI), y)
+MODULE_NAME = 8710bu
+MODULE_SUB_NAME = 8710bu
+endif
+
+EXTRA_CFLAGS += -DCONFIG_RTL8710B
+
+_HAL_INTFS_FILES += hal/HalPwrSeqCmd.o \
+					hal/$(RTL871X)/Hal8710BPwrSeq.o\
+					hal/$(RTL871X)/$(RTL871X)_sreset.o
+
+_HAL_INTFS_FILES +=	hal/$(RTL871X)/$(RTL871X)_hal_init.o \
+			hal/$(RTL871X)/$(RTL871X)_phycfg.o \
+			hal/$(RTL871X)/$(RTL871X)_rf6052.o \
+			hal/$(RTL871X)/$(RTL871X)_dm.o \
+			hal/$(RTL871X)/$(RTL871X)_rxdesc.o \
+			hal/$(RTL871X)/$(RTL871X)_cmd.o \
+			hal/$(RTL871X)/hal8710b_fw.o \
+			hal/$(RTL871X)/$(RTL871X)_lps_poff.o
+
+
+_HAL_INTFS_FILES +=	\
+			hal/$(RTL871X)/$(HCI_NAME)/$(HCI_NAME)_halinit.o \
+			hal/$(RTL871X)/$(HCI_NAME)/rtl$(MODULE_SUB_NAME)_led.o \
+			hal/$(RTL871X)/$(HCI_NAME)/rtl$(MODULE_SUB_NAME)_xmit.o \
+			hal/$(RTL871X)/$(HCI_NAME)/rtl$(MODULE_SUB_NAME)_recv.o
+
+_HAL_INTFS_FILES += hal/$(RTL871X)/$(HCI_NAME)/$(HCI_NAME)_ops.o
+
+ifeq ($(CONFIG_USB_HCI), y)
+_HAL_INTFS_FILES +=hal/efuse/$(RTL871X)/HalEfuseMask8710B_USB.o
+endif
+
+endif
+
+########### HAL_RTL8192F #################################
+ifeq ($(CONFIG_RTL8192F), y)
+
+RTL871X = rtl8192f
+ifeq ($(CONFIG_USB_HCI), y)
+MODULE_NAME = 8192fu
+MODULE_SUB_NAME = 8192fu
+endif
+ifeq ($(CONFIG_PCI_HCI), y)
+MODULE_NAME = 8192fe
+MODULE_SUB_NAME = 8192fe
+endif
+ifeq ($(CONFIG_SDIO_HCI), y)
+MODULE_NAME = 8192fs
+MODULE_SUB_NAME = 8192fs
+endif
+
+EXTRA_CFLAGS += -DCONFIG_RTL8192F
+
+_HAL_INTFS_FILES += hal/HalPwrSeqCmd.o \
+					hal/$(RTL871X)/Hal8192FPwrSeq.o\
+					hal/$(RTL871X)/$(RTL871X)_sreset.o
+
+_HAL_INTFS_FILES +=	hal/$(RTL871X)/$(RTL871X)_hal_init.o \
+			hal/$(RTL871X)/$(RTL871X)_phycfg.o \
+			hal/$(RTL871X)/$(RTL871X)_rf6052.o \
+			hal/$(RTL871X)/$(RTL871X)_dm.o \
+			hal/$(RTL871X)/$(RTL871X)_rxdesc.o \
+			hal/$(RTL871X)/$(RTL871X)_cmd.o \
+			hal/$(RTL871X)/hal8192f_fw.o \
+			hal/$(RTL871X)/$(RTL871X)_lps_poff.o
+
+
+_HAL_INTFS_FILES +=	\
+			hal/$(RTL871X)/$(HCI_NAME)/$(HCI_NAME)_halinit.o \
+			hal/$(RTL871X)/$(HCI_NAME)/rtl$(MODULE_SUB_NAME)_led.o \
+			hal/$(RTL871X)/$(HCI_NAME)/rtl$(MODULE_SUB_NAME)_xmit.o \
+			hal/$(RTL871X)/$(HCI_NAME)/rtl$(MODULE_SUB_NAME)_recv.o
+
+ifeq ($(CONFIG_PCI_HCI), y)
+_HAL_INTFS_FILES += hal/$(RTL871X)/$(HCI_NAME)/$(HCI_NAME)_ops_linux.o
+else
+_HAL_INTFS_FILES += hal/$(RTL871X)/$(HCI_NAME)/$(HCI_NAME)_ops.o
+endif
+
+ifeq ($(CONFIG_SDIO_HCI), y)
+_HAL_INTFS_FILES += hal/efuse/$(RTL871X)/HalEfuseMask8192F_SDIO.o
+endif
+
+ifeq ($(CONFIG_USB_HCI), y)
+_HAL_INTFS_FILES += hal/efuse/$(RTL871X)/HalEfuseMask8192F_USB.o
+endif
+
+ifeq ($(CONFIG_PCI_HCI), y)
+_HAL_INTFS_FILES += hal/efuse/$(RTL871X)/HalEfuseMask8192F_PCIE.o
+endif
+
+endif
+########### AUTO_CFG  #################################
+
+ifeq ($(CONFIG_AUTOCFG_CP), y)
+
+ifeq ($(CONFIG_MULTIDRV), y)
+$(shell cp $(TopDIR)/autoconf_multidrv_$(HCI_NAME)_linux.h $(TopDIR)/include/autoconf.h)
+else
+ifeq ($(CONFIG_RTL8188E)$(CONFIG_SDIO_HCI),yy)
+$(shell cp $(TopDIR)/autoconf_rtl8189e_$(HCI_NAME)_linux.h $(TopDIR)/include/autoconf.h)
+else ifeq ($(CONFIG_RTL8188F)$(CONFIG_SDIO_HCI),yy)
+$(shell cp $(TopDIR)/autoconf_rtl8189f_$(HCI_NAME)_linux.h $(TopDIR)/include/autoconf.h)
+else ifeq ($(CONFIG_RTL8723C),y)
+$(shell cp $(TopDIR)/autoconf_rtl8723c_$(HCI_NAME)_linux.h $(TopDIR)/include/autoconf.h)
+else
+$(shell cp $(TopDIR)/autoconf_$(RTL871X)_$(HCI_NAME)_linux.h $(TopDIR)/include/autoconf.h)
+endif
+endif
+
+endif
+
+########### END OF PATH  #################################
+
+ifeq ($(CONFIG_USB_HCI), y)
+ifeq ($(CONFIG_USB_AUTOSUSPEND), y)
+EXTRA_CFLAGS += -DCONFIG_USB_AUTOSUSPEND
+endif
+endif
+
+ifeq ($(CONFIG_MP_INCLUDED), y)
+#MODULE_NAME := $(MODULE_NAME)_mp
+EXTRA_CFLAGS += -DCONFIG_MP_INCLUDED
+endif
+
+ifeq ($(CONFIG_POWER_SAVING), y)
+EXTRA_CFLAGS += -DCONFIG_POWER_SAVING
+endif
+
+ifeq ($(CONFIG_HW_PWRP_DETECTION), y)
+EXTRA_CFLAGS += -DCONFIG_HW_PWRP_DETECTION
+endif
+
+ifeq ($(CONFIG_WIFI_TEST), y)
+EXTRA_CFLAGS += -DCONFIG_WIFI_TEST
+endif
+
+ifeq ($(CONFIG_BT_COEXIST), y)
+EXTRA_CFLAGS += -DCONFIG_BT_COEXIST
+endif
+
+ifeq ($(CONFIG_INTEL_WIDI), y)
+EXTRA_CFLAGS += -DCONFIG_INTEL_WIDI
+endif
+
+ifeq ($(CONFIG_WAPI_SUPPORT), y)
+EXTRA_CFLAGS += -DCONFIG_WAPI_SUPPORT
+endif
+
+
+ifeq ($(CONFIG_EFUSE_CONFIG_FILE), y)
+EXTRA_CFLAGS += -DCONFIG_EFUSE_CONFIG_FILE
+
+#EFUSE_MAP_PATH
+USER_EFUSE_MAP_PATH ?=
+ifneq ($(USER_EFUSE_MAP_PATH),)
+EXTRA_CFLAGS += -DEFUSE_MAP_PATH=\"$(USER_EFUSE_MAP_PATH)\"
+else ifeq ($(MODULE_NAME), 8189es)
+EXTRA_CFLAGS += -DEFUSE_MAP_PATH=\"/system/etc/wifi/wifi_efuse_8189e.map\"
+else ifeq ($(MODULE_NAME), 8723bs)
+EXTRA_CFLAGS += -DEFUSE_MAP_PATH=\"/system/etc/wifi/wifi_efuse_8723bs.map\"
+else
+EXTRA_CFLAGS += -DEFUSE_MAP_PATH=\"/system/etc/wifi/wifi_efuse_$(MODULE_NAME).map\"
+endif
+
+#WIFIMAC_PATH
+USER_WIFIMAC_PATH ?=
+ifneq ($(USER_WIFIMAC_PATH),)
+EXTRA_CFLAGS += -DWIFIMAC_PATH=\"$(USER_WIFIMAC_PATH)\"
+else
+EXTRA_CFLAGS += -DWIFIMAC_PATH=\"/data/wifimac.txt\"
+endif
+
+endif
+
+ifeq ($(CONFIG_EXT_CLK), y)
+EXTRA_CFLAGS += -DCONFIG_EXT_CLK
+endif
+
+ifeq ($(CONFIG_TRAFFIC_PROTECT), y)
+EXTRA_CFLAGS += -DCONFIG_TRAFFIC_PROTECT
+endif
+
+ifeq ($(CONFIG_LOAD_PHY_PARA_FROM_FILE), y)
+EXTRA_CFLAGS += -DCONFIG_LOAD_PHY_PARA_FROM_FILE
+#EXTRA_CFLAGS += -DREALTEK_CONFIG_PATH_WITH_IC_NAME_FOLDER
+EXTRA_CFLAGS += -DREALTEK_CONFIG_PATH=\"/lib/firmware/\"
+endif
+
+ifeq ($(CONFIG_TXPWR_BY_RATE_EN), n)
+EXTRA_CFLAGS += -DCONFIG_TXPWR_BY_RATE_EN=0
+else ifeq ($(CONFIG_TXPWR_BY_RATE_EN), y)
+EXTRA_CFLAGS += -DCONFIG_TXPWR_BY_RATE_EN=1
+else ifeq ($(CONFIG_TXPWR_BY_RATE_EN), auto)
+EXTRA_CFLAGS += -DCONFIG_TXPWR_BY_RATE_EN=2
+endif
+
+ifeq ($(CONFIG_TXPWR_LIMIT_EN), n)
+EXTRA_CFLAGS += -DCONFIG_TXPWR_LIMIT_EN=0
+else ifeq ($(CONFIG_TXPWR_LIMIT_EN), y)
+EXTRA_CFLAGS += -DCONFIG_TXPWR_LIMIT_EN=1
+else ifeq ($(CONFIG_TXPWR_LIMIT_EN), auto)
+EXTRA_CFLAGS += -DCONFIG_TXPWR_LIMIT_EN=2
+endif
+
+ifneq ($(CONFIG_RTW_CHPLAN), 0xFF)
+EXTRA_CFLAGS += -DCONFIG_RTW_CHPLAN=$(CONFIG_RTW_CHPLAN)
+endif
+
+ifeq ($(CONFIG_CALIBRATE_TX_POWER_BY_REGULATORY), y)
+EXTRA_CFLAGS += -DCONFIG_CALIBRATE_TX_POWER_BY_REGULATORY
+endif
+
+ifeq ($(CONFIG_CALIBRATE_TX_POWER_TO_MAX), y)
+EXTRA_CFLAGS += -DCONFIG_CALIBRATE_TX_POWER_TO_MAX
+endif
+
+ifeq ($(CONFIG_RTW_ADAPTIVITY_EN), disable)
+EXTRA_CFLAGS += -DCONFIG_RTW_ADAPTIVITY_EN=0
+else ifeq ($(CONFIG_RTW_ADAPTIVITY_EN), enable)
+EXTRA_CFLAGS += -DCONFIG_RTW_ADAPTIVITY_EN=1
+endif
+
+ifeq ($(CONFIG_RTW_ADAPTIVITY_MODE), normal)
+EXTRA_CFLAGS += -DCONFIG_RTW_ADAPTIVITY_MODE=0
+else ifeq ($(CONFIG_RTW_ADAPTIVITY_MODE), carrier_sense)
+EXTRA_CFLAGS += -DCONFIG_RTW_ADAPTIVITY_MODE=1
+endif
+
+ifeq ($(CONFIG_SIGNAL_SCALE_MAPPING), y)
+EXTRA_CFLAGS += -DCONFIG_SIGNAL_SCALE_MAPPING
+endif
+
+ifeq ($(CONFIG_80211W), y)
+EXTRA_CFLAGS += -DCONFIG_IEEE80211W
+endif
+
+ifeq ($(CONFIG_WOWLAN), y)
+EXTRA_CFLAGS += -DCONFIG_WOWLAN -DRTW_WAKEUP_EVENT=$(CONFIG_WAKEUP_TYPE)
+ifeq ($(CONFIG_SDIO_HCI), y)
+EXTRA_CFLAGS += -DCONFIG_RTW_SDIO_PM_KEEP_POWER
+endif
+endif
+
+ifeq ($(CONFIG_AP_WOWLAN), y)
+EXTRA_CFLAGS += -DCONFIG_AP_WOWLAN
+ifeq ($(CONFIG_SDIO_HCI), y)
+EXTRA_CFLAGS += -DCONFIG_RTW_SDIO_PM_KEEP_POWER
+endif
+endif
+
+ifeq ($(CONFIG_PNO_SUPPORT), y)
+EXTRA_CFLAGS += -DCONFIG_PNO_SUPPORT
+ifeq ($(CONFIG_PNO_SET_DEBUG), y)
+EXTRA_CFLAGS += -DCONFIG_PNO_SET_DEBUG
+endif
+endif
+
+ifeq ($(CONFIG_GPIO_WAKEUP), y)
+EXTRA_CFLAGS += -DCONFIG_GPIO_WAKEUP
+ifeq ($(CONFIG_ONE_PIN_GPIO), y)
+EXTRA_CFLAGS += -DCONFIG_RTW_ONE_PIN_GPIO
+endif
+ifeq ($(CONFIG_HIGH_ACTIVE_DEV2HST), y)
+EXTRA_CFLAGS += -DHIGH_ACTIVE_DEV2HST=1
+else
+EXTRA_CFLAGS += -DHIGH_ACTIVE_DEV2HST=0
+endif
+endif
+
+ifeq ($(CONFIG_HIGH_ACTIVE_HST2DEV), y)
+EXTRA_CFLAGS += -DHIGH_ACTIVE_HST2DEV=1
+else
+EXTRA_CFLAGS += -DHIGH_ACTIVE_HST2DEV=0
+endif
+
+ifneq ($(CONFIG_WAKEUP_GPIO_IDX), default)
+EXTRA_CFLAGS += -DWAKEUP_GPIO_IDX=$(CONFIG_WAKEUP_GPIO_IDX)
+endif
+
+ifeq ($(CONFIG_RTW_SDIO_PM_KEEP_POWER), y)
+ifeq ($(CONFIG_SDIO_HCI), y)
+EXTRA_CFLAGS += -DCONFIG_RTW_SDIO_PM_KEEP_POWER
+endif
+endif
+
+ifeq ($(CONFIG_REDUCE_TX_CPU_LOADING), y)
+EXTRA_CFLAGS += -DCONFIG_REDUCE_TX_CPU_LOADING
+endif
+
+ifeq ($(CONFIG_BR_EXT), y)
+BR_NAME = br0
+EXTRA_CFLAGS += -DCONFIG_BR_EXT
+EXTRA_CFLAGS += '-DCONFIG_BR_EXT_BRNAME="'$(BR_NAME)'"'
+endif
+
+
+ifeq ($(CONFIG_TDLS), y)
+EXTRA_CFLAGS += -DCONFIG_TDLS
+endif
+
+ifeq ($(CONFIG_WIFI_MONITOR), y)
+EXTRA_CFLAGS += -DCONFIG_WIFI_MONITOR
+endif
+
+ifeq ($(CONFIG_MCC_MODE), y)
+EXTRA_CFLAGS += -DCONFIG_MCC_MODE
+endif
+
+ifeq ($(CONFIG_RTW_NAPI), y)
+EXTRA_CFLAGS += -DCONFIG_RTW_NAPI
+endif
+
+ifeq ($(CONFIG_RTW_GRO), y)
+EXTRA_CFLAGS += -DCONFIG_RTW_GRO
+endif
+
+ifeq ($(CONFIG_RTW_REPEATER_SON), y)
+EXTRA_CFLAGS += -DCONFIG_RTW_REPEATER_SON
+endif
+
+ifeq ($(CONFIG_RTW_IPCAM_APPLICATION), y)
+EXTRA_CFLAGS += -DCONFIG_RTW_IPCAM_APPLICATION
+ifeq ($(CONFIG_WIFI_MONITOR), n)
+EXTRA_CFLAGS += -DCONFIG_WIFI_MONITOR
+endif
+endif
+
+ifeq ($(CONFIG_RTW_NETIF_SG), y)
+EXTRA_CFLAGS += -DCONFIG_RTW_NETIF_SG
+endif
+
+ifeq ($(CONFIG_TX_CSUM_OFFLOAD), y)
+EXTRA_CFLAGS += -DCONFIG_TX_CSUM_OFFLOAD
+endif
+
+ifeq ($(CONFIG_ICMP_VOQ), y)
+EXTRA_CFLAGS += -DCONFIG_ICMP_VOQ
+endif
+
+ifeq ($(CONFIG_RTW_WIFI_HAL), y)
+#EXTRA_CFLAGS += -DCONFIG_RTW_WIFI_HAL_DEBUG
+EXTRA_CFLAGS += -DCONFIG_RTW_WIFI_HAL
+EXTRA_CFLAGS += -DCONFIG_RTW_CFGVEDNOR_LLSTATS
+EXTRA_CFLAGS += -DCONFIG_RTW_CFGVENDOR_RANDOM_MAC_OUI
+EXTRA_CFLAGS += -DCONFIG_RTW_CFGVEDNOR_RSSIMONITOR
+EXTRA_CFLAGS += -DCONFIG_RTW_CFGVENDOR_WIFI_LOGGER
+endif
+
+ifeq ($(CONFIG_MP_VHT_HW_TX_MODE), y)
+EXTRA_CFLAGS += -DCONFIG_MP_VHT_HW_TX_MODE
+ifeq ($(CONFIG_PLATFORM_I386_PC), y)
+## For I386 X86 ToolChain use Hardware FLOATING
+EXTRA_CFLAGS += -mhard-float
+else
+## For ARM ToolChain use Hardware FLOATING
+EXTRA_CFLAGS += -mfloat-abi=hard
+endif
+endif
+
+ifeq ($(CONFIG_APPEND_VENDOR_IE_ENABLE), y)
+EXTRA_CFLAGS += -DCONFIG_APPEND_VENDOR_IE_ENABLE
+endif
+
+ifeq ($(CONFIG_RTW_DEBUG), y)
+EXTRA_CFLAGS += -DCONFIG_RTW_DEBUG
+EXTRA_CFLAGS += -DRTW_LOG_LEVEL=$(CONFIG_RTW_LOG_LEVEL)
+endif
+
+EXTRA_CFLAGS += -DDM_ODM_SUPPORT_TYPE=0x04
+
+ifeq ($(CONFIG_PLATFORM_I386_PC), y)
+EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN
+EXTRA_CFLAGS += -DCONFIG_IOCTL_CFG80211 -DRTW_USE_CFG80211_STA_EVENT
+SUBARCH := $(shell uname -m | sed -e s/i.86/i386/)
+ARCH ?= $(SUBARCH)
+CROSS_COMPILE ?=
+KVER  := $(shell uname -r)
+KSRC := /lib/modules/$(KVER)/build
+MODDESTDIR := /lib/modules/$(KVER)/kernel/drivers/net/wireless/
+INSTALL_PREFIX :=
+STAGINGMODDIR := /lib/modules/$(KVER)/kernel/drivers/staging
+endif
+
+ifeq ($(CONFIG_PLATFORM_NV_TK1), y)
+EXTRA_CFLAGS += -DCONFIG_PLATFORM_NV_TK1
+EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN
+# default setting for Android 4.1, 4.2
+EXTRA_CFLAGS += -DCONFIG_IOCTL_CFG80211 -DRTW_USE_CFG80211_STA_EVENT
+EXTRA_CFLAGS += -DCONFIG_CONCURRENT_MODE
+EXTRA_CFLAGS += -DCONFIG_P2P_IPS -DCONFIG_PLATFORM_ANDROID
+# Enable this for Android 5.0
+EXTRA_CFLAGS += -DCONFIG_RADIO_WORK
+EXTRA_CFLAGS += -DRTW_VENDOR_EXT_SUPPORT
+EXTRA_CFLAGS += -DRTW_ENABLE_WIFI_CONTROL_FUNC
+ARCH ?= arm
+
+CROSS_COMPILE := /mnt/newdisk/android_sdk/nvidia_tk1/android_L/prebuilts/gcc/linux-x86/arm/arm-eabi-4.8/bin/arm-eabi-
+KSRC :=/mnt/newdisk/android_sdk/nvidia_tk1/android_L/out/target/product/shieldtablet/obj/KERNEL/
+MODULE_NAME = wlan
+endif
+
+ifeq ($(CONFIG_PLATFORM_NV_TK1_UBUNTU), y)
+EXTRA_CFLAGS += -DCONFIG_PLATFORM_NV_TK1
+EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN
+EXTRA_CFLAGS += -DCONFIG_IOCTL_CFG80211 -DRTW_USE_CFG80211_STA_EVENT
+
+ARCH ?= arm
+
+CROSS_COMPILE ?=
+KVER := $(shell uname -r)
+KSRC := /lib/modules/$(KVER)/build
+MODDESTDIR := /lib/modules/$(KVER)/kernel/drivers/net/wireless/
+INSTALL_PREFIX :=
+endif
+
+ifeq ($(CONFIG_PLATFORM_ACTIONS_ATM702X), y)
+EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN -DCONFIG_PLATFORM_ANDROID -DCONFIG_PLATFORM_ACTIONS_ATM702X
+#ARCH := arm
+ARCH := $(R_ARCH)
+#CROSS_COMPILE := arm-none-linux-gnueabi-
+CROSS_COMPILE := $(R_CROSS_COMPILE)
+KVER:= 3.4.0
+#KSRC := ../../../../build/out/kernel
+KSRC := $(KERNEL_BUILD_PATH)
+MODULE_NAME :=wlan
+endif
+
+
+ifeq ($(CONFIG_PLATFORM_ACTIONS_ATM705X), y)
+EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN
+#EXTRA_CFLAGS += -DRTW_ENABLE_WIFI_CONTROL_FUNC
+# default setting for Android 4.1, 4.2, 4.3, 4.4
+EXTRA_CFLAGS += -DCONFIG_PLATFORM_ACTIONS_ATM705X
+EXTRA_CFLAGS += -DCONFIG_CONCURRENT_MODE
+EXTRA_CFLAGS += -DCONFIG_IOCTL_CFG80211 -DRTW_USE_CFG80211_STA_EVENT
+
+# Enable this for Android 5.0
+EXTRA_CFLAGS += -DCONFIG_RADIO_WORK
+
+ifeq ($(CONFIG_SDIO_HCI), y)
+EXTRA_CFLAGS += -DCONFIG_PLATFORM_OPS
+_PLATFORM_FILES += platform/platform_arm_act_sdio.o
+endif
+
+ARCH := arm
+CROSS_COMPILE := /opt/arm-2011.09/bin/arm-none-linux-gnueabi-
+KSRC := /home/android_sdk/Action-semi/705a_android_L/android/kernel
+endif
+
+ifeq ($(CONFIG_PLATFORM_ARM_SUN50IW1P1), y)
+EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN
+EXTRA_CFLAGS += -DCONFIG_PLATFORM_ARM_SUN50IW1P1
+EXTRA_CFLAGS += -DCONFIG_TRAFFIC_PROTECT
+# default setting for Android 4.1, 4.2
+EXTRA_CFLAGS += -DCONFIG_CONCURRENT_MODE
+EXTRA_CFLAGS += -DCONFIG_IOCTL_CFG80211 -DRTW_USE_CFG80211_STA_EVENT
+EXTRA_CFLAGS += -DCONFIG_RESUME_IN_WORKQUEUE
+EXTRA_CFLAGS += -DCONFIG_PLATFORM_OPS
+
+# Enable this for Android 5.0
+EXTRA_CFLAGS += -DCONFIG_RADIO_WORK
+
+ifeq ($(CONFIG_USB_HCI), y)
+EXTRA_CFLAGS += -DCONFIG_USE_USB_BUFFER_ALLOC_TX
+_PLATFORM_FILES += platform/platform_ARM_SUNxI_usb.o
+endif
+ifeq ($(CONFIG_SDIO_HCI), y)
+_PLATFORM_FILES += platform/platform_ARM_SUN50IW1P1_sdio.o
+endif
+
+ARCH := arm64
+# ===Cross compile setting for Android 5.1(64) SDK ===
+CROSS_COMPILE := /home/android_sdk/Allwinner/a64/android-51/lichee/out/sun50iw1p1/android/common/buildroot/external-toolchain/bin/aarch64-linux-gnu-
+KSRC :=/home/android_sdk/Allwinner/a64/android-51/lichee/linux-3.10/
+endif
+
+ifeq ($(CONFIG_PLATFORM_TI_AM3517), y)
+EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN -DCONFIG_PLATFORM_ANDROID -DCONFIG_PLATFORM_SHUTTLE
+CROSS_COMPILE := arm-eabi-
+KSRC := $(shell pwd)/../../../Android/kernel
+ARCH := arm
+endif
+
+ifeq ($(CONFIG_PLATFORM_MSTAR_TITANIA12), y)
+EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN -DCONFIG_PLATFORM_MSTAR -DCONFIG_PLATFORM_MSTAR_TITANIA12
+ARCH:=mips
+CROSS_COMPILE:= /usr/src/Mstar_kernel/mips-4.3/bin/mips-linux-gnu-
+KVER:= 2.6.28.9
+KSRC:= /usr/src/Mstar_kernel/2.6.28.9/
+endif
+
+ifeq ($(CONFIG_PLATFORM_MSTAR), y)
+EXTRA_CFLAGS += -DCONFIG_CONCURRENT_MODE
+EXTRA_CFLAGS += -DCONFIG_IOCTL_CFG80211 -DRTW_USE_CFG80211_STA_EVENT
+EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN
+EXTRA_CFLAGS += -DCONFIG_PLATFORM_MSTAR
+EXTRA_CFLAGS += -DCONFIG_PLATFORM_MSTAR_HIGH
+ifeq ($(CONFIG_USB_HCI), y)
+EXTRA_CFLAGS += -DCONFIG_USE_USB_BUFFER_ALLOC_TX -DCONFIG_FIX_NR_BULKIN_BUFFER
+endif
+ARCH:=arm
+CROSS_COMPILE:= /usr/src/bin/arm-none-linux-gnueabi-
+KVER:= 3.1.10
+KSRC:= /usr/src/Mstar_kernel/3.1.10/
+endif
+
+ifeq ($(CONFIG_PLATFORM_ANDROID_X86), y)
+EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN
+SUBARCH := $(shell uname -m | sed -e s/i.86/i386/)
+ARCH := $(SUBARCH)
+CROSS_COMPILE := /media/DATA-2/android-x86/ics-x86_20120130/prebuilt/linux-x86/toolchain/i686-unknown-linux-gnu-4.2.1/bin/i686-unknown-linux-gnu-
+KSRC := /media/DATA-2/android-x86/ics-x86_20120130/out/target/product/generic_x86/obj/kernel
+MODULE_NAME :=wlan
+endif
+
+ifeq ($(CONFIG_PLATFORM_ANDROID_INTEL_X86), y)
+EXTRA_CFLAGS += -DCONFIG_PLATFORM_ANDROID_INTEL_X86
+EXTRA_CFLAGS += -DCONFIG_PLATFORM_INTEL_BYT
+EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN -DCONFIG_PLATFORM_ANDROID
+EXTRA_CFLAGS += -DCONFIG_CONCURRENT_MODE
+EXTRA_CFLAGS += -DCONFIG_IOCTL_CFG80211 -DRTW_USE_CFG80211_STA_EVENT
+EXTRA_CFLAGS += -DCONFIG_SKIP_SIGNAL_SCALE_MAPPING
+ifeq ($(CONFIG_SDIO_HCI), y)
+EXTRA_CFLAGS += -DCONFIG_RESUME_IN_WORKQUEUE
+endif
+endif
+
+ifeq ($(CONFIG_PLATFORM_JB_X86), y)
+EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN
+EXTRA_CFLAGS += -DCONFIG_CONCURRENT_MODE
+EXTRA_CFLAGS += -DCONFIG_IOCTL_CFG80211 -DRTW_USE_CFG80211_STA_EVENT
+SUBARCH := $(shell uname -m | sed -e s/i.86/i386/)
+ARCH := $(SUBARCH)
+CROSS_COMPILE := /home/android_sdk/android-x86_JB/prebuilts/gcc/linux-x86/x86/i686-linux-android-4.7/bin/i686-linux-android-
+KSRC := /home/android_sdk/android-x86_JB/out/target/product/x86/obj/kernel/
+MODULE_NAME :=wlan
+endif
+
+ifeq ($(CONFIG_PLATFORM_ARM_PXA2XX), y)
+EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN
+ARCH := arm
+CROSS_COMPILE := arm-none-linux-gnueabi-
+KVER  := 2.6.34.1
+KSRC ?= /usr/src/linux-2.6.34.1
+endif
+
+ifeq ($(CONFIG_PLATFORM_ARM_S3C2K4), y)
+EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN
+ARCH := arm
+CROSS_COMPILE := arm-linux-
+KVER  := 2.6.24.7_$(ARCH)
+KSRC := /usr/src/kernels/linux-$(KVER)
+endif
+
+ifeq ($(CONFIG_PLATFORM_ARM_S3C6K4), y)
+EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN
+ARCH := arm
+CROSS_COMPILE := arm-none-linux-gnueabi-
+KVER  := 2.6.34.1
+KSRC ?= /usr/src/linux-2.6.34.1
+endif
+
+ifeq ($(CONFIG_PLATFORM_RTD2880B), y)
+EXTRA_CFLAGS += -DCONFIG_BIG_ENDIAN -DCONFIG_PLATFORM_RTD2880B
+ARCH:=
+CROSS_COMPILE:=
+KVER:=
+KSRC:=
+endif
+
+ifeq ($(CONFIG_PLATFORM_MIPS_RMI), y)
+EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN
+ARCH:=mips
+CROSS_COMPILE:=mipsisa32r2-uclibc-
+KVER:=
+KSRC:= /root/work/kernel_realtek
+endif
+
+ifeq ($(CONFIG_PLATFORM_MIPS_PLM), y)
+EXTRA_CFLAGS += -DCONFIG_BIG_ENDIAN
+ARCH:=mips
+CROSS_COMPILE:=mipsisa32r2-uclibc-
+KVER:=
+KSRC:= /root/work/kernel_realtek
+endif
+
+ifeq ($(CONFIG_PLATFORM_MSTAR389), y)
+EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN -DCONFIG_PLATFORM_MSTAR389
+ARCH:=mips
+CROSS_COMPILE:= mips-linux-gnu-
+KVER:= 2.6.28.10
+KSRC:= /home/mstar/mstar_linux/2.6.28.9/
+endif
+
+ifeq ($(CONFIG_PLATFORM_MIPS_AR9132), y)
+EXTRA_CFLAGS += -DCONFIG_BIG_ENDIAN
+ARCH := mips
+CROSS_COMPILE := mips-openwrt-linux-
+KSRC := /home/alex/test_openwrt/tmp/linux-2.6.30.9
+endif
+
+ifeq ($(CONFIG_PLATFORM_DMP_PHILIPS), y)
+EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN -DRTK_DMP_PLATFORM
+ARCH := mips
+#CROSS_COMPILE:=/usr/local/msdk-4.3.6-mips-EL-2.6.12.6-0.9.30.3/bin/mipsel-linux-
+CROSS_COMPILE:=/usr/local/toolchain_mipsel/bin/mipsel-linux-
+KSRC ?=/usr/local/Jupiter/linux-2.6.12
+endif
+
+ifeq ($(CONFIG_PLATFORM_RTK_DMP), y)
+EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN -DRTK_DMP_PLATFORM  -DCONFIG_WIRELESS_EXT
+EXTRA_CFLAGS += -DCONFIG_PLATFORM_OPS
+ifeq ($(CONFIG_USB_HCI), y)
+_PLATFORM_FILES += platform/platform_RTK_DMP_usb.o
+endif
+ARCH:=mips
+CROSS_COMPILE:=mipsel-linux-
+KVER:=
+KSRC ?= /usr/src/DMP_Kernel/jupiter/linux-2.6.12
+endif
+
+ifeq ($(CONFIG_PLATFORM_MT53XX), y)
+EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN -DCONFIG_PLATFORM_MT53XX
+ARCH:= arm
+CROSS_COMPILE:= arm11_mtk_le-
+KVER:= 2.6.27
+KSRC?= /proj/mtk00802/BD_Compare/BDP/Dev/BDP_V301/BDP_Linux/linux-2.6.27
+endif
+
+ifeq ($(CONFIG_PLATFORM_ARM_MX51_241H), y)
+EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN -DCONFIG_WISTRON_PLATFORM
+ARCH := arm
+CROSS_COMPILE := /opt/freescale/usr/local/gcc-4.1.2-glibc-2.5-nptl-3/arm-none-linux-gnueabi/bin/arm-none-linux-gnueabi-
+KVER  := 2.6.31
+KSRC ?= /lib/modules/2.6.31-770-g0e46b52/source
+endif
+
+ifeq ($(CONFIG_PLATFORM_FS_MX61), y)
+EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN
+ARCH := arm
+CROSS_COMPILE := /home/share/CusEnv/FreeScale/arm-eabi-4.4.3/bin/arm-eabi-
+KSRC ?= /home/share/CusEnv/FreeScale/FS_kernel_env
+endif
+
+
+
+ifeq ($(CONFIG_PLATFORM_ACTIONS_ATJ227X), y)
+EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN -DCONFIG_PLATFORM_ACTIONS_ATJ227X
+ARCH := mips
+CROSS_COMPILE := /home/cnsd4/project/actions/tools-2.6.27/bin/mipsel-linux-gnu-
+KVER  := 2.6.27
+KSRC := /home/cnsd4/project/actions/linux-2.6.27.28
+endif
+
+ifeq ($(CONFIG_PLATFORM_TI_DM365), y)
+EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN -DCONFIG_PLATFORM_TI_DM365
+EXTRA_CFLAGS += -DCONFIG_USE_USB_BUFFER_ALLOC_RX
+EXTRA_CFLAGS += -DCONFIG_SINGLE_XMIT_BUF -DCONFIG_SINGLE_RECV_BUF
+ARCH := arm
+#CROSS_COMPILE := /home/cnsd4/Appro/mv_pro_5.0/montavista/pro/devkit/arm/v5t_le/bin/arm_v5t_le-
+#KSRC := /home/cnsd4/Appro/mv_pro_5.0/montavista/pro/devkit/lsp/ti-davinci/linux-dm365
+CROSS_COMPILE := /opt/montavista/pro5.0/devkit/arm/v5t_le/bin/arm-linux-
+KSRC:= /home/vivotek/lsp/DM365/kernel_platform/kernel/linux-2.6.18
+KERNELOUTPUT := ${PRODUCTDIR}/tmp
+KVER  := 2.6.18
+endif
+
+ifeq ($(CONFIG_PLATFORM_MOZART), y)
+EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN -DCONFIG_PLATFORM_MOZART
+ARCH := arm
+CROSS_COMPILE := /home/vivotek/lsp/mozart3v2/Mozart3e_Toolchain/build_arm_nofpu/usr/bin/arm-linux-
+KVER  := $(shell uname -r)
+KSRC:= /opt/Vivotek/lsp/mozart3v2/kernel_platform/kernel/mozart_kernel-1.17
+KERNELOUTPUT := /home/pink/sample/ODM/IP8136W-VINT/tmp/kernel
+endif
+
+ifeq ($(CONFIG_PLATFORM_TEGRA3_CARDHU), y)
+EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN
+# default setting for Android 4.1, 4.2
+EXTRA_CFLAGS += -DRTW_ENABLE_WIFI_CONTROL_FUNC
+EXTRA_CFLAGS += -DCONFIG_CONCURRENT_MODE
+EXTRA_CFLAGS += -DCONFIG_IOCTL_CFG80211 -DRTW_USE_CFG80211_STA_EVENT
+ARCH := arm
+CROSS_COMPILE := /home/android_sdk/nvidia/tegra-16r3-partner-android-4.1_20120723/prebuilt/linux-x86/toolchain/arm-eabi-4.4.3/bin/arm-eabi-
+KSRC := /home/android_sdk/nvidia/tegra-16r3-partner-android-4.1_20120723/out/target/product/cardhu/obj/KERNEL
+MODULE_NAME := wlan
+endif
+
+ifeq ($(CONFIG_PLATFORM_TEGRA4_DALMORE), y)
+EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN
+# default setting for Android 4.1, 4.2
+EXTRA_CFLAGS += -DRTW_ENABLE_WIFI_CONTROL_FUNC
+EXTRA_CFLAGS += -DCONFIG_CONCURRENT_MODE
+EXTRA_CFLAGS += -DCONFIG_IOCTL_CFG80211 -DRTW_USE_CFG80211_STA_EVENT
+ARCH := arm
+CROSS_COMPILE := /home/android_sdk/nvidia/tegra-17r9-partner-android-4.2-dalmore_20130131/prebuilts/gcc/linux-x86/arm/arm-eabi-4.6/bin/arm-eabi-
+KSRC := /home/android_sdk/nvidia/tegra-17r9-partner-android-4.2-dalmore_20130131/out/target/product/dalmore/obj/KERNEL
+MODULE_NAME := wlan
+endif
+
+ifeq ($(CONFIG_PLATFORM_ARM_TCC8900), y)
+EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN
+ARCH := arm
+CROSS_COMPILE := /home/android_sdk/Telechips/SDK_2304_20110613/prebuilt/linux-x86/toolchain/arm-eabi-4.4.3/bin/arm-eabi-
+KSRC := /home/android_sdk/Telechips/SDK_2304_20110613/kernel
+MODULE_NAME := wlan
+endif
+
+ifeq ($(CONFIG_PLATFORM_ARM_TCC8920), y)
+EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN
+ARCH := arm
+CROSS_COMPILE := /home/android_sdk/Telechips/v12.06_r1-tcc-android-4.0.4/prebuilt/linux-x86/toolchain/arm-eabi-4.4.3/bin/arm-eabi-
+KSRC := /home/android_sdk/Telechips/v12.06_r1-tcc-android-4.0.4/kernel
+MODULE_NAME := wlan
+endif
+
+ifeq ($(CONFIG_PLATFORM_ARM_TCC8920_JB42), y)
+EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN
+# default setting for Android 4.1, 4.2
+EXTRA_CFLAGS += -DCONFIG_CONCURRENT_MODE
+EXTRA_CFLAGS += -DCONFIG_IOCTL_CFG80211 -DRTW_USE_CFG80211_STA_EVENT
+ARCH := arm
+CROSS_COMPILE := /home/android_sdk/Telechips/v13.03_r1-tcc-android-4.2.2_ds_patched/prebuilts/gcc/linux-x86/arm/arm-eabi-4.6/bin/arm-eabi-
+KSRC := /home/android_sdk/Telechips/v13.03_r1-tcc-android-4.2.2_ds_patched/kernel
+MODULE_NAME := wlan
+endif
+
+ifeq ($(CONFIG_PLATFORM_ARM_RK2818), y)
+EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN -DCONFIG_PLATFORM_ANDROID -DCONFIG_PLATFORM_ROCKCHIPS
+ARCH := arm
+CROSS_COMPILE := /usr/src/release_fae_version/toolchain/arm-eabi-4.4.0/bin/arm-eabi-
+KSRC := /usr/src/release_fae_version/kernel25_A7_281x
+MODULE_NAME := wlan
+endif
+
+ifeq ($(CONFIG_PLATFORM_ARM_RK3188), y)
+EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN -DCONFIG_PLATFORM_ANDROID -DCONFIG_PLATFORM_ROCKCHIPS
+# default setting for Android 4.1, 4.2, 4.3, 4.4
+EXTRA_CFLAGS += -DCONFIG_IOCTL_CFG80211 -DRTW_USE_CFG80211_STA_EVENT
+EXTRA_CFLAGS += -DCONFIG_CONCURRENT_MODE
+# default setting for Power control
+EXTRA_CFLAGS += -DRTW_ENABLE_WIFI_CONTROL_FUNC
+EXTRA_CFLAGS += -DRTW_SUPPORT_PLATFORM_SHUTDOWN
+# default setting for Special function
+ARCH := arm
+CROSS_COMPILE := /home/android_sdk/Rockchip/Rk3188/prebuilts/gcc/linux-x86/arm/arm-eabi-4.6/bin/arm-eabi-
+KSRC := /home/android_sdk/Rockchip/Rk3188/kernel
+MODULE_NAME := wlan
+endif
+
+ifeq ($(CONFIG_PLATFORM_ARM_RK3066), y)
+EXTRA_CFLAGS += -DCONFIG_PLATFORM_ARM_RK3066
+EXTRA_CFLAGS += -DRTW_ENABLE_WIFI_CONTROL_FUNC
+EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN
+EXTRA_CFLAGS += -DCONFIG_CONCURRENT_MODE
+EXTRA_CFLAGS += -DCONFIG_IOCTL_CFG80211
+ifeq ($(CONFIG_SDIO_HCI), y)
+EXTRA_CFLAGS += -DRTW_SUPPORT_PLATFORM_SHUTDOWN
+endif
+EXTRA_CFLAGS += -fno-pic
+ARCH := arm
+CROSS_COMPILE := /home/android_sdk/Rockchip/rk3066_20130607/prebuilts/gcc/linux-x86/arm/arm-linux-androideabi-4.6/bin/arm-linux-androideabi-
+#CROSS_COMPILE := /home/android_sdk/Rockchip/Rk3066sdk/prebuilts/gcc/linux-x86/arm/arm-linux-androideabi-4.6/bin/arm-linux-androideabi-
+KSRC := /home/android_sdk/Rockchip/Rk3066sdk/kernel
+MODULE_NAME :=wlan
+endif
+
+ifeq ($(CONFIG_PLATFORM_ARM_URBETTER), y)
+EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN #-DCONFIG_MINIMAL_MEMORY_USAGE
+ARCH := arm
+CROSS_COMPILE := /media/DATA-1/urbetter/arm-2009q3/bin/arm-none-linux-gnueabi-
+KSRC := /media/DATA-1/urbetter/ics-urbetter/kernel
+MODULE_NAME := wlan
+endif
+
+ifeq ($(CONFIG_PLATFORM_ARM_TI_PANDA), y)
+EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN #-DCONFIG_MINIMAL_MEMORY_USAGE
+ARCH := arm
+#CROSS_COMPILE := /media/DATA-1/aosp/ics-aosp_20111227/prebuilt/linux-x86/toolchain/arm-eabi-4.4.3/bin/arm-eabi-
+#KSRC := /media/DATA-1/aosp/android-omap-panda-3.0_20120104
+CROSS_COMPILE := /media/DATA-1/android-4.0/prebuilt/linux-x86/toolchain/arm-eabi-4.4.3/bin/arm-eabi-
+KSRC := /media/DATA-1/android-4.0/panda_kernel/omap
+MODULE_NAME := wlan
+endif
+
+ifeq ($(CONFIG_PLATFORM_MIPS_JZ4760), y)
+EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN -DCONFIG_MINIMAL_MEMORY_USAGE
+ARCH ?= mips
+CROSS_COMPILE ?= /mnt/sdb5/Ingenic/Umido/mips-4.3/bin/mips-linux-gnu-
+KSRC ?= /mnt/sdb5/Ingenic/Umido/kernel
+endif
+
+ifeq ($(CONFIG_PLATFORM_SZEBOOK), y)
+EXTRA_CFLAGS += -DCONFIG_BIG_ENDIAN
+ARCH:=arm
+CROSS_COMPILE:=/opt/crosstool2/bin/armeb-unknown-linux-gnueabi-
+KVER:= 2.6.31.6
+KSRC:= ../code/linux-2.6.31.6-2020/
+endif
+
+ifeq ($(CONFIG_PLATFORM_ARM_SUNxI), y)
+EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN
+EXTRA_CFLAGS += -DCONFIG_PLATFORM_ARM_SUNxI
+# default setting for Android 4.1, 4.2
+EXTRA_CFLAGS += -DCONFIG_CONCURRENT_MODE
+EXTRA_CFLAGS += -DCONFIG_IOCTL_CFG80211 -DRTW_USE_CFG80211_STA_EVENT
+
+EXTRA_CFLAGS += -DCONFIG_PLATFORM_OPS
+ifeq ($(CONFIG_USB_HCI), y)
+EXTRA_CFLAGS += -DCONFIG_USE_USB_BUFFER_ALLOC_TX
+_PLATFORM_FILES += platform/platform_ARM_SUNxI_usb.o
+endif
+ifeq ($(CONFIG_SDIO_HCI), y)
+# default setting for A10-EVB mmc0
+#EXTRA_CFLAGS += -DCONFIG_WITS_EVB_V13
+_PLATFORM_FILES += platform/platform_ARM_SUNxI_sdio.o
+endif
+
+ARCH := arm
+#CROSS_COMPILE := arm-none-linux-gnueabi-
+CROSS_COMPILE=/home/android_sdk/Allwinner/a10/android-jb42/lichee-jb42/buildroot/output/external-toolchain/bin/arm-none-linux-gnueabi-
+KVER  := 3.0.8
+#KSRC:= ../lichee/linux-3.0/
+KSRC=/home/android_sdk/Allwinner/a10/android-jb42/lichee-jb42/linux-3.0
+endif
+
+ifeq ($(CONFIG_PLATFORM_ARM_SUN6I), y)
+EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN
+EXTRA_CFLAGS += -DCONFIG_PLATFORM_ARM_SUN6I
+EXTRA_CFLAGS += -DCONFIG_TRAFFIC_PROTECT
+# default setting for Android 4.1, 4.2, 4.3, 4.4
+EXTRA_CFLAGS += -DCONFIG_CONCURRENT_MODE
+EXTRA_CFLAGS += -DCONFIG_IOCTL_CFG80211 -DRTW_USE_CFG80211_STA_EVENT
+EXTRA_CFLAGS +=  -DCONFIG_QOS_OPTIMIZATION
+
+EXTRA_CFLAGS += -DCONFIG_PLATFORM_OPS
+ifeq ($(CONFIG_USB_HCI), y)
+EXTRA_CFLAGS += -DCONFIG_USE_USB_BUFFER_ALLOC_TX
+_PLATFORM_FILES += platform/platform_ARM_SUNxI_usb.o
+endif
+ifeq ($(CONFIG_SDIO_HCI), y)
+# default setting for A31-EVB mmc0
+EXTRA_CFLAGS += -DCONFIG_A31_EVB
+_PLATFORM_FILES += platform/platform_ARM_SUNnI_sdio.o
+endif
+
+ARCH := arm
+#Android-JB42
+#CROSS_COMPILE := /home/android_sdk/Allwinner/a31/android-jb42/lichee/buildroot/output/external-toolchain/bin/arm-linux-gnueabi-
+#KSRC :=/home/android_sdk/Allwinner/a31/android-jb42/lichee/linux-3.3
+#ifeq ($(CONFIG_USB_HCI), y)
+#MODULE_NAME := 8188eu_sw
+#endif
+# ==== Cross compile setting for kitkat-a3x_v4.5 =====
+CROSS_COMPILE := /home/android_sdk/Allwinner/a31/kitkat-a3x_v4.5/lichee/buildroot/output/external-toolchain/bin/arm-linux-gnueabi-
+KSRC :=/home/android_sdk/Allwinner/a31/kitkat-a3x_v4.5/lichee/linux-3.3
+endif
+
+ifeq ($(CONFIG_PLATFORM_ARM_SUN7I), y)
+EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN
+EXTRA_CFLAGS += -DCONFIG_PLATFORM_ARM_SUN7I
+EXTRA_CFLAGS += -DCONFIG_TRAFFIC_PROTECT
+# default setting for Android 4.1, 4.2, 4.3, 4.4
+EXTRA_CFLAGS += -DCONFIG_CONCURRENT_MODE
+EXTRA_CFLAGS += -DCONFIG_IOCTL_CFG80211 -DRTW_USE_CFG80211_STA_EVENT
+EXTRA_CFLAGS +=  -DCONFIG_QOS_OPTIMIZATION
+
+EXTRA_CFLAGS += -DCONFIG_PLATFORM_OPS
+ifeq ($(CONFIG_USB_HCI), y)
+EXTRA_CFLAGS += -DCONFIG_USE_USB_BUFFER_ALLOC_TX
+_PLATFORM_FILES += platform/platform_ARM_SUNxI_usb.o
+endif
+ifeq ($(CONFIG_SDIO_HCI), y)
+_PLATFORM_FILES += platform/platform_ARM_SUNnI_sdio.o
+endif
+
+ARCH := arm
+# ===Cross compile setting for Android 4.2 SDK ===
+#CROSS_COMPILE := /home/android_sdk/Allwinner/a20_evb/lichee/out/android/common/buildroot/external-toolchain/bin/arm-linux-gnueabi-
+#KSRC := /home/android_sdk/Allwinner/a20_evb/lichee/linux-3.3
+# ==== Cross compile setting for Android 4.3 SDK =====
+#CROSS_COMPILE := /home/android_sdk/Allwinner/a20/android-jb43/lichee/out/android/common/buildroot/external-toolchain/bin/arm-linux-gnueabi-
+#KSRC := /home/android_sdk/Allwinner/a20/android-jb43/lichee/linux-3.4
+# ==== Cross compile setting for kitkat-a20_v4.4 =====
+CROSS_COMPILE := /home/android_sdk/Allwinner/a20/kitkat-a20_v4.4/lichee/out/android/common/buildroot/external-toolchain/bin/arm-linux-gnueabi-
+KSRC := /home/android_sdk/Allwinner/a20/kitkat-a20_v4.4/lichee/linux-3.4
+endif
+
+ifeq ($(CONFIG_PLATFORM_ARM_SUN8I_W3P1), y)
+EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN
+EXTRA_CFLAGS += -DCONFIG_PLATFORM_ARM_SUN8I
+EXTRA_CFLAGS += -DCONFIG_PLATFORM_ARM_SUN8I_W3P1
+EXTRA_CFLAGS += -DCONFIG_TRAFFIC_PROTECT
+# default setting for Android 4.1, 4.2
+EXTRA_CFLAGS += -DCONFIG_CONCURRENT_MODE
+EXTRA_CFLAGS += -DCONFIG_IOCTL_CFG80211 -DRTW_USE_CFG80211_STA_EVENT
+
+EXTRA_CFLAGS += -DCONFIG_PLATFORM_OPS
+ifeq ($(CONFIG_USB_HCI), y)
+EXTRA_CFLAGS += -DCONFIG_USE_USB_BUFFER_ALLOC_TX
+_PLATFORM_FILES += platform/platform_ARM_SUNxI_usb.o
+endif
+ifeq ($(CONFIG_SDIO_HCI), y)
+_PLATFORM_FILES += platform/platform_ARM_SUNnI_sdio.o
+endif
+
+ARCH := arm
+# ===Cross compile setting for Android 4.2 SDK ===
+#CROSS_COMPILE := /home/android_sdk/Allwinner/a23/android-jb42/lichee/out/android/common/buildroot/external-toolchain/bin/arm-linux-gnueabi-
+#KSRC :=/home/android_sdk/Allwinner/a23/android-jb42/lichee/linux-3.4
+# ===Cross compile setting for Android 4.4 SDK ===
+CROSS_COMPILE := /home/android_sdk/Allwinner/a23/android-kk44/lichee/out/android/common/buildroot/external-toolchain/bin/arm-linux-gnueabi-
+KSRC :=/home/android_sdk/Allwinner/a23/android-kk44/lichee/linux-3.4
+endif
+
+ifeq ($(CONFIG_PLATFORM_ARM_SUN8I_W5P1), y)
+EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN
+EXTRA_CFLAGS += -DCONFIG_PLATFORM_ARM_SUN8I
+EXTRA_CFLAGS += -DCONFIG_PLATFORM_ARM_SUN8I_W5P1
+EXTRA_CFLAGS += -DCONFIG_TRAFFIC_PROTECT
+# default setting for Android 4.1, 4.2
+EXTRA_CFLAGS += -DCONFIG_CONCURRENT_MODE
+EXTRA_CFLAGS += -DCONFIG_IOCTL_CFG80211 -DRTW_USE_CFG80211_STA_EVENT
+
+# Enable this for Android 5.0
+EXTRA_CFLAGS += -DCONFIG_RADIO_WORK
+
+EXTRA_CFLAGS += -DCONFIG_PLATFORM_OPS
+ifeq ($(CONFIG_USB_HCI), y)
+EXTRA_CFLAGS += -DCONFIG_USE_USB_BUFFER_ALLOC_TX
+_PLATFORM_FILES += platform/platform_ARM_SUNxI_usb.o
+endif
+ifeq ($(CONFIG_SDIO_HCI), y)
+_PLATFORM_FILES += platform/platform_ARM_SUNnI_sdio.o
+endif
+
+ARCH := arm
+# ===Cross compile setting for Android L SDK ===
+CROSS_COMPILE := /home/android_sdk/Allwinner/a33/android-L/lichee/out/sun8iw5p1/android/common/buildroot/external-toolchain/bin/arm-linux-gnueabi-
+KSRC :=/home/android_sdk/Allwinner/a33/android-L/lichee/linux-3.4
+endif
+
+ifeq ($(CONFIG_PLATFORM_ACTIONS_ATV5201), y)
+EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN -DCONFIG_PLATFORM_ACTIONS_ATV5201
+EXTRA_CFLAGS += -DCONFIG_SDIO_DISABLE_RXFIFO_POLLING_LOOP
+ARCH := mips
+CROSS_COMPILE := mipsel-linux-gnu-
+KVER  := $(KERNEL_VER)
+KSRC:= $(CFGDIR)/../../kernel/linux-$(KERNEL_VER)
+endif
+
+ifeq ($(CONFIG_PLATFORM_ARM_RTD299X), y)
+EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN
+EXTRA_CFLAGS += -DCONFIG_CONCURRENT_MODE
+EXTRA_CFLAGS += -DCONFIG_IOCTL_CFG80211 -DRTW_USE_CFG80211_STA_EVENT
+ifeq ($(CONFIG_ANDROID), y)
+# Enable this for Android 5.0
+EXTRA_CFLAGS += -DCONFIG_RADIO_WORK
+endif
+#ARCH, CROSS_COMPILE, KSRC,and  MODDESTDIR are provided by external makefile
+INSTALL_PREFIX :=
+endif
+
+ifeq ($(CONFIG_PLATFORM_ARM_RTD299X_LG), y)
+EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN
+EXTRA_CFLAGS += -DCONFIG_IOCTL_CFG80211 -DRTW_USE_CFG80211_STA_EVENT
+EXTRA_CFLAGS += -DCONFIG_CONCURRENT_MODE
+EXTRA_CFLAGS += -DRTW_P2P_GROUP_INTERFACE=1
+EXTRA_CFLAGS += -DCONFIG_IFACE_NUMBER=3
+#EXTRA_CFLAGS += -DCONFIG_FIX_HWPORT
+EXTRA_CFLAGS += -DLGE_PRIVATE
+EXTRA_CFLAGS += -DPURE_SUPPLICANT
+EXTRA_CFLAGS += -DCONFIG_CUSTOMIZED_COUNTRY_CHPLAN_MAP -DCONFIG_RTW_IOCTL_SET_COUNTRY
+EXTRA_CFLAGS += -DDBG_RX_DFRAME_RAW_DATA
+EXTRA_CFLAGS += -DRTW_REDUCE_SCAN_SWITCH_CH_TIME
+ARCH ?= arm
+KVER ?=
+
+ifneq ($(PLATFORM), WEBOS)
+$(info PLATFORM is empty)
+CROSS_COMPILE ?= /mnt/newdisk/LGE/arm-lg115x-linux-gnueabi-4.8-2016.03-x86_64/bin/arm-lg115x-linux-gnueabi-
+KSRC ?= /mnt/newdisk/LGE/linux-rockhopper_k3lp_drd4tv_423
+endif
+
+CROSS_COMPILE ?=
+KSRC ?= $(LINUX_SRC)
+INSTALL_PREFIX ?=
+endif
+
+ifeq ($(CONFIG_PLATFORM_HISILICON), y)
+EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN -DCONFIG_PLATFORM_HISILICON
+ifeq ($(SUPPORT_CONCURRENT),y)
+EXTRA_CFLAGS += -DCONFIG_CONCURRENT_MODE
+endif
+EXTRA_CFLAGS += -DCONFIG_IOCTL_CFG80211 -DRTW_USE_CFG80211_STA_EVENT
+ARCH := arm
+ifeq ($(CROSS_COMPILE),)
+       CROSS_COMPILE = arm-hisiv200-linux-
+endif
+MODULE_NAME := rtl8192eu
+ifeq ($(KSRC),)
+       KSRC := ../../../../../../kernel/linux-3.4.y
+endif
+endif
+
+ifeq ($(CONFIG_PLATFORM_HISILICON_HI3798), y)
+EXTRA_CFLAGS += -DCONFIG_PLATFORM_HISILICON
+EXTRA_CFLAGS += -DCONFIG_PLATFORM_HISILICON_HI3798
+EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN
+# default setting for Android
+EXTRA_CFLAGS += -DCONFIG_CONCURRENT_MODE
+EXTRA_CFLAGS += -DCONFIG_IOCTL_CFG80211
+EXTRA_CFLAGS += -DRTW_USE_CFG80211_STA_EVENT
+# default setting for Android 5.x and later
+#EXTRA_CFLAGS += -DCONFIG_RADIO_WORK
+
+# If system could power on and recognize Wi-Fi SDIO automatically,
+# platfrom operations are not necessary.
+#ifeq ($(CONFIG_SDIO_HCI), y)
+#EXTRA_CFLAGS += -DCONFIG_PLATFORM_OPS
+#_PLATFORM_FILES += platform/platform_hisilicon_hi3798_sdio.o
+#EXTRA_CFLAGS += -DCONFIG_HISI_SDIO_ID=1
+#endif
+
+ARCH ?= arm
+CROSS_COMPILE ?= /HiSTBAndroidV600R003C00SPC021_git_0512/device/hisilicon/bigfish/sdk/tools/linux/toolchains/arm-histbv310-linux/bin/arm-histbv310-linux-
+ifndef KSRC
+KSRC := /HiSTBAndroidV600R003C00SPC021_git_0512/device/hisilicon/bigfish/sdk/source/kernel/linux-3.18.y
+KSRC += O=/HiSTBAndroidV600R003C00SPC021_git_0512/out/target/product/Hi3798MV200/obj/KERNEL_OBJ
+endif
+
+ifeq ($(CONFIG_RTL8822B), y)
+ifeq ($(CONFIG_SDIO_HCI), y)
+CONFIG_RTL8822BS ?= m
+USER_MODULE_NAME := rtl8822bs
+endif
+endif
+
+endif
+
+# Platform setting
+ifeq ($(CONFIG_PLATFORM_ARM_SPREADTRUM_6820), y)
+ifeq ($(CONFIG_ANDROID_2X), y)
+EXTRA_CFLAGS += -DANDROID_2X
+endif
+EXTRA_CFLAGS += -DCONFIG_PLATFORM_SPRD
+EXTRA_CFLAGS += -DPLATFORM_SPREADTRUM_6820
+EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN
+ifeq ($(RTL871X), rtl8188e)
+EXTRA_CFLAGS += -DSOFTAP_PS_DURATION=50
+endif
+ifeq ($(CONFIG_SDIO_HCI), y)
+EXTRA_CFLAGS += -DCONFIG_PLATFORM_OPS
+_PLATFORM_FILES += platform/platform_sprd_sdio.o
+endif
+endif
+
+ifeq ($(CONFIG_PLATFORM_ARM_SPREADTRUM_8810), y)
+ifeq ($(CONFIG_ANDROID_2X), y)
+EXTRA_CFLAGS += -DANDROID_2X
+endif
+EXTRA_CFLAGS += -DCONFIG_PLATFORM_SPRD
+EXTRA_CFLAGS += -DPLATFORM_SPREADTRUM_8810
+EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN
+ifeq ($(RTL871X), rtl8188e)
+EXTRA_CFLAGS += -DSOFTAP_PS_DURATION=50
+endif
+ifeq ($(CONFIG_SDIO_HCI), y)
+EXTRA_CFLAGS += -DCONFIG_PLATFORM_OPS
+_PLATFORM_FILES += platform/platform_sprd_sdio.o
+endif
+endif
+
+ifeq ($(CONFIG_PLATFORM_ARM_WMT), y)
+EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN
+EXTRA_CFLAGS += -DCONFIG_CONCURRENT_MODE
+EXTRA_CFLAGS += -DCONFIG_IOCTL_CFG80211 -DRTW_USE_CFG80211_STA_EVENT
+EXTRA_CFLAGS += -DCONFIG_PLATFORM_OPS
+ifeq ($(CONFIG_SDIO_HCI), y)
+_PLATFORM_FILES += platform/platform_ARM_WMT_sdio.o
+endif
+ARCH := arm
+CROSS_COMPILE := /home/android_sdk/WonderMedia/wm8880-android4.4/toolchain/arm_201103_gcc4.5.2/mybin/arm_1103_le-
+KSRC := /home/android_sdk/WonderMedia/wm8880-android4.4/kernel4.4/
+MODULE_NAME :=8189es_kk
+endif
+
+ifeq ($(CONFIG_PLATFORM_RTK119X), y)
+EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN
+#EXTRA_CFLAGS += -DCONFIG_PLATFORM_ARM_SUN7I
+EXTRA_CFLAGS += -DCONFIG_TRAFFIC_PROTECT
+# default setting for Android 4.1, 4.2
+EXTRA_CFLAGS += -DCONFIG_CONCURRENT_MODE
+EXTRA_CFLAGS += -DCONFIG_IOCTL_CFG80211 -DRTW_USE_CFG80211_STA_EVENT
+#EXTRA_CFLAGS +=  -DCONFIG_QOS_OPTIMIZATION
+EXTRA_CFLAGS += -DCONFIG_QOS_OPTIMIZATION
+
+#EXTRA_CFLAGS += -DCONFIG_#PLATFORM_OPS
+ifeq ($(CONFIG_USB_HCI), y)
+EXTRA_CFLAGS += -DCONFIG_USE_USB_BUFFER_ALLOC_TX
+#_PLATFORM_FILES += platform/platform_ARM_SUNxI_usb.o
+endif
+ifeq ($(CONFIG_SDIO_HCI), y)
+_PLATFORM_FILES += platform/platform_ARM_SUNnI_sdio.o
+endif
+
+ARCH := arm
+
+# ==== Cross compile setting for Android 4.4 SDK =====
+#CROSS_COMPILE := arm-linux-gnueabihf-
+KVER  := 3.10.24
+#KSRC :=/home/android_sdk/Allwinner/a20/android-kitkat44/lichee/linux-3.4
+CROSS_COMPILE := /home/realtek/software_phoenix/phoenix/toolchain/usr/local/arm-2013.11/bin/arm-linux-gnueabihf-
+KSRC := /home/realtek/software_phoenix/linux-kernel
+MODULE_NAME := 8192eu
+
+endif
+
+ifeq ($(CONFIG_PLATFORM_RTK119X_AM), y)
+EXTRA_CFLAGS += -DCONFIG_PLATFORM_RTK119X_AM
+EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN
+EXTRA_CFLAGS += -DCONFIG_TRAFFIC_PROTECT
+EXTRA_CFLAGS += -DCONFIG_CONCURRENT_MODE -DCONFIG_FULL_CH_IN_P2P_HANDSHAKE
+EXTRA_CFLAGS += -DCONFIG_IFACE_NUMBER=3
+EXTRA_CFLAGS += -DCONFIG_IOCTL_CFG80211 -DRTW_USE_CFG80211_STA_EVENT
+
+ifeq ($(CONFIG_USB_HCI), y)
+EXTRA_CFLAGS += -DCONFIG_USE_USB_BUFFER_ALLOC_TX
+endif
+
+ARCH := arm
+
+#CROSS_COMPILE := arm-linux-gnueabihf-
+KVER  := 3.10.24
+#KSRC :=
+CROSS_COMPILE :=
+endif
+
+ifeq ($(CONFIG_PLATFORM_RTK129X), y)
+EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN
+EXTRA_CFLAGS += -DRTK_129X_PLATFORM
+EXTRA_CFLAGS += -DCONFIG_TRAFFIC_PROTECT
+# default setting for Android 4.1, 4.2
+EXTRA_CFLAGS += -DCONFIG_CONCURRENT_MODE
+EXTRA_CFLAGS += -DCONFIG_IOCTL_CFG80211 -DRTW_USE_CFG80211_STA_EVENT
+#EXTRA_CFLAGS += -DCONFIG_P2P_IPS -DCONFIG_QOS_OPTIMIZATION
+EXTRA_CFLAGS += -DCONFIG_QOS_OPTIMIZATION
+# Enable this for Android 5.0
+EXTRA_CFLAGS += -DCONFIG_RADIO_WORK
+ifeq ($(CONFIG_RTL8821C)$(CONFIG_SDIO_HCI),yy)
+EXTRA_CFLAGS += -DCONFIG_WAKEUP_GPIO_INPUT_MODE
+EXTRA_CFLAGS += -DCONFIG_BT_WAKE_HST_OPEN_DRAIN
+endif
+EXTRA_CFLAGS += -Wno-error=date-time
+# default setting for Android 7.0
+ifeq ($(RTK_ANDROID_VERSION), nougat)
+EXTRA_CFLAGS += -DRTW_P2P_GROUP_INTERFACE=1
+endif
+#EXTRA_CFLAGS += -DCONFIG_#PLATFORM_OPS
+ifeq ($(CONFIG_USB_HCI), y)
+EXTRA_CFLAGS += -DCONFIG_USE_USB_BUFFER_ALLOC_TX
+endif
+
+ARCH := arm64
+
+# ==== Cross compile setting for Android 4.4 SDK =====
+#CROSS_COMPILE := arm-linux-gnueabihf-
+#KVER  := 4.1.10
+#CROSS_COMPILE := $(CROSS)
+#KSRC := $(LINUX_KERNEL_PATH)
+CROSS_COMPILE := /home/android_sdk/DHC/trunk-6.0.0_r1-QA160627/phoenix/toolchain/asdk64-4.9.4-a53-EL-3.10-g2.19-a64nt-160307/bin/asdk64-linux-
+KSRC := /home/android_sdk/DHC/trunk-6.0.0_r1-QA160627/linux-kernel
+endif
+
+ifeq ($(CONFIG_PLATFORM_RTK390X), y)
+EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN
+EXTRA_CFLAGS += -DCONFIG_PLATFORM_RTK390X
+EXTRA_CFLAGS += -DCONFIG_IOCTL_CFG80211 -DRTW_USE_CFG80211_STA_EVENT
+EXTRA_CFLAGS += -DCONFIG_RTW_NETIF_SG
+ifeq ($(CONFIG_USB_HCI), y)
+EXTRA_CFLAGS += -DCONFIG_USE_USB_BUFFER_ALLOC_TX
+endif
+
+ARCH:=rlx
+
+CROSS_COMPILE:=mips-linux-
+KSRC:= /home/realtek/share/Develop/IPCAM_SDK/RealSil/rts3901_sdk_v1.2_vanilla/linux-3.10
+
+endif
+
+ifeq ($(CONFIG_PLATFORM_NOVATEK_NT72668), y)
+EXTRA_CFLAGS += -DCONFIG_PLATFORM_NOVATEK_NT72668
+EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN
+EXTRA_CFLAGS += -DCONFIG_CONCURRENT_MODE
+EXTRA_CFLAGS += -DCONFIG_IOCTL_CFG80211 -DRTW_USE_CFG80211_STA_EVENT
+EXTRA_CFLAGS += -DCONFIG_USE_USB_BUFFER_ALLOC_RX
+EXTRA_CFLAGS += -DCONFIG_USE_USB_BUFFER_ALLOC_TX
+ARCH ?= arm
+CROSS_COMPILE := arm-linux-gnueabihf-
+KVER := 3.8.0
+KSRC := /Custom/Novatek/TCL/linux-3.8_header
+#KSRC := $(KERNELDIR)
+endif
+
+ifeq ($(CONFIG_PLATFORM_ARM_TCC8930_JB42), y)
+EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN
+# default setting for Android 4.1, 4.2
+EXTRA_CFLAGS += -DCONFIG_CONCURRENT_MODE
+EXTRA_CFLAGS += -DCONFIG_IOCTL_CFG80211 -DRTW_USE_CFG80211_STA_EVENT
+ARCH := arm
+CROSS_COMPILE := /home/android_sdk/Telechips/v13.05_r1-tcc-android-4.2.2_tcc893x-evm_build/prebuilts/gcc/linux-x86/arm/arm-eabi-4.6/bin/arm-eabi-
+KSRC := /home/android_sdk/Telechips/v13.05_r1-tcc-android-4.2.2_tcc893x-evm_build/kernel
+MODULE_NAME := wlan
+endif
+
+ifeq ($(CONFIG_PLATFORM_RTL8197D), y)
+EXTRA_CFLAGS += -DCONFIG_BIG_ENDIAN -DCONFIG_PLATFORM_RTL8197D
+export DIR_LINUX=$(shell pwd)/../SDK/rlxlinux-sdk321-v50/linux-2.6.30
+ARCH ?= rlx
+CROSS_COMPILE:= $(DIR_LINUX)/../toolchain/rsdk-1.5.5-5281-EB-2.6.30-0.9.30.3-110714/bin/rsdk-linux-
+KSRC := $(DIR_LINUX)
+endif
+
+ifeq ($(CONFIG_PLATFORM_AML_S905), y)
+EXTRA_CFLAGS += -DCONFIG_PLATFORM_AML_S905
+EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN -fno-pic
+# default setting for Android
+EXTRA_CFLAGS += -DCONFIG_CONCURRENT_MODE
+EXTRA_CFLAGS += -DCONFIG_IOCTL_CFG80211
+EXTRA_CFLAGS += -DRTW_USE_CFG80211_STA_EVENT
+# default setting for Android 5.x and later
+EXTRA_CFLAGS += -DCONFIG_RADIO_WORK
+
+ifeq ($(CONFIG_SDIO_HCI), y)
+EXTRA_CFLAGS += -DCONFIG_PLATFORM_OPS
+_PLATFORM_FILES += platform/platform_aml_s905_sdio.o
+endif
+
+ARCH ?= arm64
+CROSS_COMPILE ?= /4.4_S905L_8822bs_compile/gcc-linaro-aarch64-linux-gnu-4.9-2014.09_linux/bin/aarch64-linux-gnu-
+ifndef KSRC
+KSRC := /4.4_S905L_8822bs_compile/common
+# To locate output files in a separate directory.
+KSRC += O=/4.4_S905L_8822bs_compile/KERNEL_OBJ
+endif
+
+ifeq ($(CONFIG_RTL8822B), y)
+ifeq ($(CONFIG_SDIO_HCI), y)
+CONFIG_RTL8822BS ?= m
+USER_MODULE_NAME := 8822bs
+endif
+endif
+
+endif
+
+ifeq ($(CONFIG_PLATFORM_ZTE_ZX296716), y)
+EXTRA_CFLAGS += -Wno-error=date-time
+EXTRA_CFLAGS += -DCONFIG_PLATFORM_ZTE_ZX296716
+EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN
+# default setting for Android
+EXTRA_CFLAGS += -DCONFIG_CONCURRENT_MODE
+EXTRA_CFLAGS += -DCONFIG_IOCTL_CFG80211
+EXTRA_CFLAGS += -DRTW_USE_CFG80211_STA_EVENT
+# default setting for Android 5.x and later
+#EXTRA_CFLAGS += -DCONFIG_RADIO_WORK
+
+ifeq ($(CONFIG_SDIO_HCI), y)
+# mark this temporarily
+#EXTRA_CFLAGS += -DCONFIG_PLATFORM_OPS
+#_PLATFORM_FILES += platform/platform_zte_zx296716_sdio.o
+endif
+
+ARCH ?= arm64
+CROSS_COMPILE ?=
+KSRC ?=
+
+ifeq ($(CONFIG_RTL8822B), y)
+ifeq ($(CONFIG_SDIO_HCI), y)
+CONFIG_RTL8822BS ?= m
+USER_MODULE_NAME := 8822bs
+endif
+endif
+
+endif
+
+########### CUSTOMER ################################
+ifeq ($(CONFIG_CUSTOMER_HUAWEI_GENERAL), y)
+CONFIG_CUSTOMER_HUAWEI = y
+endif
+
+ifeq ($(CONFIG_CUSTOMER_HUAWEI), y)
+EXTRA_CFLAGS += -DCONFIG_HUAWEI_PROC
+endif
+
+ifeq ($(CONFIG_MULTIDRV), y)
+
+ifeq ($(CONFIG_SDIO_HCI), y)
+MODULE_NAME := rtw_sdio
+endif
+
+ifeq ($(CONFIG_USB_HCI), y)
+MODULE_NAME := rtw_usb
+endif
+
+ifeq ($(CONFIG_PCI_HCI), y)
+MODULE_NAME := rtw_pci
+endif
+
+
+endif
+
+USER_MODULE_NAME ?=
+ifneq ($(USER_MODULE_NAME),)
+MODULE_NAME := $(USER_MODULE_NAME)
+endif
+
+ifneq ($(KERNELRELEASE),)
+
+########### this part for *.mk ############################
+include $(TopDIR)/hal/phydm/phydm.mk
+
+########### HAL_RTL8822B #################################
+ifeq ($(CONFIG_RTL8822B), y)
+include $(TopDIR)/rtl8822b.mk
+endif
+
+########### HAL_RTL8821C #################################
+ifeq ($(CONFIG_RTL8821C), y)
+include $(TopDIR)/rtl8821c.mk
+endif
+
+rtk_core :=	core/rtw_cmd.o \
+		core/rtw_security.o \
+		core/rtw_debug.o \
+		core/rtw_io.o \
+		core/rtw_ioctl_query.o \
+		core/rtw_ioctl_set.o \
+		core/rtw_ieee80211.o \
+		core/rtw_mlme.o \
+		core/rtw_mlme_ext.o \
+		core/rtw_mi.o \
+		core/rtw_wlan_util.o \
+		core/rtw_vht.o \
+		core/rtw_pwrctrl.o \
+		core/rtw_rf.o \
+		core/rtw_chplan.o \
+		core/rtw_recv.o \
+		core/rtw_sta_mgt.o \
+		core/rtw_ap.o \
+		core/mesh/rtw_mesh.o \
+		core/mesh/rtw_mesh_pathtbl.o \
+		core/mesh/rtw_mesh_hwmp.o \
+		core/rtw_xmit.o	\
+		core/rtw_p2p.o \
+		core/rtw_rson.o \
+		core/rtw_tdls.o \
+		core/rtw_br_ext.o \
+		core/rtw_iol.o \
+		core/rtw_sreset.o \
+		core/rtw_btcoex_wifionly.o \
+		core/rtw_btcoex.o \
+		core/rtw_beamforming.o \
+		core/rtw_odm.o \
+		core/rtw_rm.o \
+		core/rtw_rm_fsm.o \
+		core/efuse/rtw_efuse.o
+
+ifeq ($(CONFIG_SDIO_HCI), y)
+rtk_core += core/rtw_sdio.o
+endif
+
+$(MODULE_NAME)-y += $(rtk_core)
+
+$(MODULE_NAME)-$(CONFIG_INTEL_WIDI) += core/rtw_intel_widi.o
+
+$(MODULE_NAME)-$(CONFIG_WAPI_SUPPORT) += core/rtw_wapi.o	\
+					core/rtw_wapi_sms4.o
+
+$(MODULE_NAME)-y += $(_OS_INTFS_FILES)
+$(MODULE_NAME)-y += $(_HAL_INTFS_FILES)
+$(MODULE_NAME)-y += $(_PHYDM_FILES)
+$(MODULE_NAME)-y += $(_BTC_FILES)
+$(MODULE_NAME)-y += $(_PLATFORM_FILES)
+
+$(MODULE_NAME)-$(CONFIG_MP_INCLUDED) += core/rtw_mp.o
+
+ifeq ($(CONFIG_RTL8723B), y)
+$(MODULE_NAME)-$(CONFIG_MP_INCLUDED)+= core/rtw_bt_mp.o
+endif
+
+obj-$(CONFIG_RTL8821CE) := $(MODULE_NAME).o
+
+else
+
+export CONFIG_RTL8821CE = m
+
+all: modules
+
+modules:
+	$(MAKE) ARCH=$(ARCH) CROSS_COMPILE=$(CROSS_COMPILE) -C $(KSRC) M=$(shell pwd)  modules
+
+strip:
+	$(CROSS_COMPILE)strip $(MODULE_NAME).ko --strip-unneeded
+
+install:
+	install -p -m 644 $(MODULE_NAME).ko  $(MODDESTDIR)
+	/sbin/depmod -a ${KVER}
+
+uninstall:
+	rm -f $(MODDESTDIR)/$(MODULE_NAME).ko
+	/sbin/depmod -a ${KVER}
+
+backup_rtlwifi:
+	@echo "Making backup rtlwifi drivers"
+ifneq (,$(wildcard $(STAGINGMODDIR)/rtl*))
+	@tar cPf $(wildcard $(STAGINGMODDIR))/backup_rtlwifi_driver.tar $(wildcard $(STAGINGMODDIR)/rtl*)
+	@rm -rf $(wildcard $(STAGINGMODDIR)/rtl*)
+endif
+ifneq (,$(wildcard $(MODDESTDIR)realtek))
+	@tar cPf $(MODDESTDIR)backup_rtlwifi_driver.tar $(MODDESTDIR)realtek
+	@rm -fr $(MODDESTDIR)realtek
+endif
+ifneq (,$(wildcard $(MODDESTDIR)rtl*))
+	@tar cPf $(MODDESTDIR)../backup_rtlwifi_driver.tar $(wildcard $(MODDESTDIR)rtl*)
+	@rm -fr $(wildcard $(MODDESTDIR)rtl*)
+endif
+	@/sbin/depmod -a ${KVER}
+	@echo "Please reboot your system"
+
+restore_rtlwifi:
+	@echo "Restoring backups"
+ifneq (,$(wildcard $(STAGINGMODDIR)/backup_rtlwifi_driver.tar))
+	@tar xPf $(STAGINGMODDIR)/backup_rtlwifi_driver.tar
+	@rm $(STAGINGMODDIR)/backup_rtlwifi_driver.tar
+endif
+ifneq (,$(wildcard $(MODDESTDIR)backup_rtlwifi_driver.tar))
+	@tar xPf $(MODDESTDIR)backup_rtlwifi_driver.tar
+	@rm $(MODDESTDIR)backup_rtlwifi_driver.tar
+endif
+ifneq (,$(wildcard $(MODDESTDIR)../backup_rtlwifi_driver.tar))
+	@tar xPf $(MODDESTDIR)../backup_rtlwifi_driver.tar
+	@rm $(MODDESTDIR)../backup_rtlwifi_driver.tar
+endif
+	@/sbin/depmod -a ${KVER}
+	@echo "Please reboot your system"
+
+config_r:
+	@echo "make config"
+	/bin/bash script/Configure script/config.in
+
+
+.PHONY: modules clean
+
+clean:
+	#$(MAKE) -C $(KSRC) M=$(shell pwd) clean
+	cd hal ; rm -fr */*/*/*.mod.c */*/*/*.mod */*/*/*.o */*/*/.*.cmd */*/*/*.ko
+	cd hal ; rm -fr */*/*.mod.c */*/*.mod */*/*.o */*/.*.cmd */*/*.ko
+	cd hal ; rm -fr */*.mod.c */*.mod */*.o */.*.cmd */*.ko
+	cd hal ; rm -fr *.mod.c *.mod *.o .*.cmd *.ko
+	cd core ; rm -fr */*.mod.c */*.mod */*.o */.*.cmd */*.ko
+	cd core ; rm -fr *.mod.c *.mod *.o .*.cmd *.ko
+	cd os_dep/linux ; rm -fr *.mod.c *.mod *.o .*.cmd *.ko
+	cd os_dep ; rm -fr *.mod.c *.mod *.o .*.cmd *.ko
+	cd platform ; rm -fr *.mod.c *.mod *.o .*.cmd *.ko
+	rm -fr Module.symvers ; rm -fr Module.markers ; rm -fr modules.order
+	rm -fr *.mod.c *.mod *.o .*.cmd *.ko *~
+	rm -fr .tmp_versions
+endif
+
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/os_dep/linux/custom_gpio_linux.c linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/os_dep/linux/custom_gpio_linux.c
--- linux-5.6.3/3rdparty/rtl8821ce/os_dep/linux/custom_gpio_linux.c	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/os_dep/linux/custom_gpio_linux.c	2020-04-10 16:35:06.853661795 +0300
@@ -0,0 +1,340 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#include "drv_types.h"
+
+#ifdef CONFIG_PLATFORM_SPRD
+
+/* gspi func & GPIO define */
+#include <mach/gpio.h>/* 0915 */
+#include <mach/board.h>
+
+#if !(defined ANDROID_2X)
+
+#ifdef CONFIG_RTL8188E
+#include <mach/regulator.h>
+#include <linux/regulator/consumer.h>
+#endif /* CONFIG_RTL8188E */
+
+#ifndef GPIO_WIFI_POWER
+#define GPIO_WIFI_POWER -1
+#endif /* !GPIO_WIFI_POWER */
+
+#ifndef GPIO_WIFI_RESET
+#define GPIO_WIFI_RESET -1
+#endif /* !GPIO_WIFI_RESET */
+
+#ifndef GPIO_WIFI_PWDN
+#define GPIO_WIFI_PWDN -1
+#endif /* !GPIO_WIFI_RESET */
+#ifdef CONFIG_GSPI_HCI
+extern unsigned int oob_irq;
+#endif /* CONFIG_GSPI_HCI */
+
+#ifdef CONFIG_SDIO_HCI
+extern int rtw_mp_mode;
+#else /* !CONFIG_SDIO_HCI */
+#endif /* !CONFIG_SDIO_HCI */
+
+int rtw_wifi_gpio_init(void)
+{
+#ifdef CONFIG_GSPI_HCI
+	if (GPIO_WIFI_IRQ > 0) {
+		gpio_request(GPIO_WIFI_IRQ, "oob_irq");
+		gpio_direction_input(GPIO_WIFI_IRQ);
+
+		oob_irq = gpio_to_irq(GPIO_WIFI_IRQ);
+
+		RTW_INFO("%s oob_irq:%d\n", __func__, oob_irq);
+	}
+#endif
+	if (GPIO_WIFI_RESET > 0)
+		gpio_request(GPIO_WIFI_RESET , "wifi_rst");
+	if (GPIO_WIFI_POWER > 0)
+		gpio_request(GPIO_WIFI_POWER, "wifi_power");
+
+#ifdef CONFIG_SDIO_HCI
+#if (defined(CONFIG_RTL8723B)) && (MP_DRIVER == 1)
+	if (rtw_mp_mode == 1) {
+		RTW_INFO("%s GPIO_BT_RESET pin special for mp_test\n", __func__);
+		if (GPIO_BT_RESET > 0)
+			gpio_request(GPIO_BT_RESET , "bt_rst");
+	}
+#endif
+#endif
+	return 0;
+}
+
+int rtw_wifi_gpio_deinit(void)
+{
+#ifdef CONFIG_GSPI_HCI
+	if (GPIO_WIFI_IRQ > 0)
+		gpio_free(GPIO_WIFI_IRQ);
+#endif
+	if (GPIO_WIFI_RESET > 0)
+		gpio_free(GPIO_WIFI_RESET);
+	if (GPIO_WIFI_POWER > 0)
+		gpio_free(GPIO_WIFI_POWER);
+
+#ifdef CONFIG_SDIO_HCI
+#if (defined(CONFIG_RTL8723B)) && (MP_DRIVER == 1)
+	if (rtw_mp_mode == 1) {
+		RTW_INFO("%s GPIO_BT_RESET pin special for mp_test\n", __func__);
+		if (GPIO_BT_RESET > 0)
+			gpio_free(GPIO_BT_RESET);
+	}
+#endif
+#endif
+	return 0;
+}
+
+/* Customer function to control hw specific wlan gpios */
+void rtw_wifi_gpio_wlan_ctrl(int onoff)
+{
+	switch (onoff) {
+	case WLAN_PWDN_OFF:
+		RTW_INFO("%s: call customer specific GPIO(%d) to set wifi power down pin to 0\n",
+			 __FUNCTION__, GPIO_WIFI_RESET);
+
+#ifndef CONFIG_DONT_BUS_SCAN
+		if (GPIO_WIFI_RESET > 0)
+			gpio_direction_output(GPIO_WIFI_RESET , 0);
+#endif
+		break;
+
+	case WLAN_PWDN_ON:
+		RTW_INFO("%s: callc customer specific GPIO(%d) to set wifi power down pin to 1\n",
+			 __FUNCTION__, GPIO_WIFI_RESET);
+
+		if (GPIO_WIFI_RESET > 0)
+			gpio_direction_output(GPIO_WIFI_RESET , 1);
+		break;
+
+	case WLAN_POWER_OFF:
+		break;
+
+	case WLAN_POWER_ON:
+		break;
+#ifdef CONFIG_SDIO_HCI
+#if (defined(CONFIG_RTL8723B)) && (MP_DRIVER == 1)
+	case WLAN_BT_PWDN_OFF:
+		if (rtw_mp_mode == 1) {
+			RTW_INFO("%s: call customer specific GPIO to set wifi power down pin to 0\n",
+				 __FUNCTION__);
+			if (GPIO_BT_RESET > 0)
+				gpio_direction_output(GPIO_BT_RESET , 0);
+		}
+		break;
+
+	case WLAN_BT_PWDN_ON:
+		if (rtw_mp_mode == 1) {
+			RTW_INFO("%s: callc customer specific GPIO to set wifi power down pin to 1 %x\n",
+				 __FUNCTION__, GPIO_BT_RESET);
+
+			if (GPIO_BT_RESET > 0)
+				gpio_direction_output(GPIO_BT_RESET , 1);
+		}
+		break;
+#endif
+#endif
+	}
+}
+
+#else /* ANDROID_2X */
+
+#include <mach/ldo.h>
+
+#ifdef CONFIG_RTL8188E
+extern int sprd_3rdparty_gpio_wifi_power;
+#endif
+extern int sprd_3rdparty_gpio_wifi_pwd;
+#if  defined(CONFIG_RTL8723B)
+extern int sprd_3rdparty_gpio_bt_reset;
+#endif
+
+int rtw_wifi_gpio_init(void)
+{
+#if defined(CONFIG_RTL8723B)
+	if (sprd_3rdparty_gpio_bt_reset > 0)
+		gpio_direction_output(sprd_3rdparty_gpio_bt_reset, 1);
+#endif
+
+	return 0;
+}
+
+int rtw_wifi_gpio_deinit(void)
+{
+	return 0;
+}
+
+/* Customer function to control hw specific wlan gpios */
+void rtw_wifi_gpio_wlan_ctrl(int onoff)
+{
+	switch (onoff) {
+	case WLAN_PWDN_OFF:
+		RTW_INFO("%s: call customer specific GPIO to set wifi power down pin to 0\n",
+			 __FUNCTION__);
+		if (sprd_3rdparty_gpio_wifi_pwd > 0)
+			gpio_set_value(sprd_3rdparty_gpio_wifi_pwd, 0);
+
+		if (sprd_3rdparty_gpio_wifi_pwd == 60) {
+			RTW_INFO("%s: turn off VSIM2 2.8V\n", __func__);
+			LDO_TurnOffLDO(LDO_LDO_SIM2);
+		}
+		break;
+
+	case WLAN_PWDN_ON:
+		RTW_INFO("%s: callc customer specific GPIO to set wifi power down pin to 1\n",
+			 __FUNCTION__);
+		if (sprd_3rdparty_gpio_wifi_pwd == 60) {
+			RTW_INFO("%s: turn on VSIM2 2.8V\n", __func__);
+			LDO_SetVoltLevel(LDO_LDO_SIM2, LDO_VOLT_LEVEL0);
+			LDO_TurnOnLDO(LDO_LDO_SIM2);
+		}
+		if (sprd_3rdparty_gpio_wifi_pwd > 0)
+			gpio_set_value(sprd_3rdparty_gpio_wifi_pwd, 1);
+		break;
+
+	case WLAN_POWER_OFF:
+#ifdef CONFIG_RTL8188E
+#ifdef CONFIG_WIF1_LDO
+		RTW_INFO("%s: turn off VDD-WIFI0 1.2V\n", __FUNCTION__);
+		LDO_TurnOffLDO(LDO_LDO_WIF1);
+#endif /* CONFIG_WIF1_LDO */
+
+		RTW_INFO("%s: turn off VDD-WIFI0 3.3V\n", __FUNCTION__);
+		LDO_TurnOffLDO(LDO_LDO_WIF0);
+
+		RTW_INFO("%s: call customer specific GPIO(%d) to turn off wifi power\n",
+			 __FUNCTION__, sprd_3rdparty_gpio_wifi_power);
+		if (sprd_3rdparty_gpio_wifi_power != 65535)
+			gpio_set_value(sprd_3rdparty_gpio_wifi_power, 0);
+#endif
+		break;
+
+	case WLAN_POWER_ON:
+#ifdef CONFIG_RTL8188E
+		RTW_INFO("%s: call customer specific GPIO(%d) to turn on wifi power\n",
+			 __FUNCTION__, sprd_3rdparty_gpio_wifi_power);
+		if (sprd_3rdparty_gpio_wifi_power != 65535)
+			gpio_set_value(sprd_3rdparty_gpio_wifi_power, 1);
+
+		RTW_INFO("%s: turn on VDD-WIFI0 3.3V\n", __FUNCTION__);
+		LDO_TurnOnLDO(LDO_LDO_WIF0);
+		LDO_SetVoltLevel(LDO_LDO_WIF0, LDO_VOLT_LEVEL1);
+
+#ifdef CONFIG_WIF1_LDO
+		RTW_INFO("%s: turn on VDD-WIFI1 1.2V\n", __func__);
+		LDO_TurnOnLDO(LDO_LDO_WIF1);
+		LDO_SetVoltLevel(LDO_LDO_WIF1, LDO_VOLT_LEVEL3);
+#endif /* CONFIG_WIF1_LDO */
+#endif
+		break;
+
+	case WLAN_BT_PWDN_OFF:
+		RTW_INFO("%s: call customer specific GPIO to set bt power down pin to 0\n",
+			 __FUNCTION__);
+#if defined(CONFIG_RTL8723B)
+		if (sprd_3rdparty_gpio_bt_reset > 0)
+			gpio_set_value(sprd_3rdparty_gpio_bt_reset, 0);
+#endif
+		break;
+
+	case WLAN_BT_PWDN_ON:
+		RTW_INFO("%s: callc customer specific GPIO to set bt power down pin to 1\n",
+			 __FUNCTION__);
+#if defined(CONFIG_RTL8723B)
+		if (sprd_3rdparty_gpio_bt_reset > 0)
+			gpio_set_value(sprd_3rdparty_gpio_bt_reset, 1);
+#endif
+		break;
+	}
+}
+#endif /* ANDROID_2X */
+
+#elif defined(CONFIG_PLATFORM_ARM_RK3066)
+#include <mach/iomux.h>
+
+#define GPIO_WIFI_IRQ		RK30_PIN2_PC2
+extern unsigned int oob_irq;
+int rtw_wifi_gpio_init(void)
+{
+#ifdef CONFIG_GSPI_HCI
+	if (GPIO_WIFI_IRQ > 0) {
+		rk30_mux_api_set(GPIO2C2_LCDC1DATA18_SMCBLSN1_HSADCDATA5_NAME, GPIO2C_GPIO2C2);/* jacky_test */
+		gpio_request(GPIO_WIFI_IRQ, "oob_irq");
+		gpio_direction_input(GPIO_WIFI_IRQ);
+
+		oob_irq = gpio_to_irq(GPIO_WIFI_IRQ);
+
+		RTW_INFO("%s oob_irq:%d\n", __func__, oob_irq);
+	}
+#endif
+	return 0;
+}
+
+
+int rtw_wifi_gpio_deinit(void)
+{
+#ifdef CONFIG_GSPI_HCI
+	if (GPIO_WIFI_IRQ > 0)
+		gpio_free(GPIO_WIFI_IRQ);
+#endif
+	return 0;
+}
+
+void rtw_wifi_gpio_wlan_ctrl(int onoff)
+{
+}
+
+#ifdef CONFIG_GPIO_API
+/* this is a demo for extending GPIO pin[7] as interrupt mode */
+struct net_device *rtl_net;
+extern int rtw_register_gpio_interrupt(struct net_device *netdev, int gpio_num, void(*callback)(u8 level));
+extern int rtw_disable_gpio_interrupt(struct net_device *netdev, int gpio_num);
+void gpio_int(u8 is_high)
+{
+	RTW_INFO("%s level=%d\n", __func__, is_high);
+}
+int register_net_gpio_init(void)
+{
+	rtl_net = dev_get_by_name(&init_net, "wlan0");
+	if (!rtl_net) {
+		RTW_PRINT("rtl_net init fail!\n");
+		return -1;
+	}
+	return rtw_register_gpio_interrupt(rtl_net, 7, gpio_int);
+}
+int unregister_net_gpio_init(void)
+{
+	rtl_net = dev_get_by_name(&init_net, "wlan0");
+	if (!rtl_net) {
+		RTW_PRINT("rtl_net init fail!\n");
+		return -1;
+	}
+	return rtw_disable_gpio_interrupt(rtl_net, 7);
+}
+#endif
+
+#else
+
+int rtw_wifi_gpio_init(void)
+{
+	return 0;
+}
+
+void rtw_wifi_gpio_wlan_ctrl(int onoff)
+{
+}
+#endif /* CONFIG_PLATFORM_SPRD */
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/os_dep/linux/ioctl_cfg80211.c linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/os_dep/linux/ioctl_cfg80211.c
--- linux-5.6.3/3rdparty/rtl8821ce/os_dep/linux/ioctl_cfg80211.c	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/os_dep/linux/ioctl_cfg80211.c	2020-04-10 16:35:06.854661842 +0300
@@ -0,0 +1,9977 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#define  _IOCTL_CFG80211_C_
+
+#include <drv_types.h>
+#include <hal_data.h>
+
+#ifdef CONFIG_IOCTL_CFG80211
+
+#ifndef DBG_RTW_CFG80211_STA_PARAM
+#define DBG_RTW_CFG80211_STA_PARAM 0
+#endif
+
+#ifndef DBG_RTW_CFG80211_MESH_CONF
+#define DBG_RTW_CFG80211_MESH_CONF 0
+#endif
+
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 0, 0))
+#define STATION_INFO_INACTIVE_TIME	BIT(NL80211_STA_INFO_INACTIVE_TIME)
+#define STATION_INFO_LLID			BIT(NL80211_STA_INFO_LLID)
+#define STATION_INFO_PLID			BIT(NL80211_STA_INFO_PLID)
+#define STATION_INFO_PLINK_STATE	BIT(NL80211_STA_INFO_PLINK_STATE)
+#define STATION_INFO_SIGNAL			BIT(NL80211_STA_INFO_SIGNAL)
+#define STATION_INFO_TX_BITRATE		BIT(NL80211_STA_INFO_TX_BITRATE)
+#define STATION_INFO_RX_PACKETS		BIT(NL80211_STA_INFO_RX_PACKETS)
+#define STATION_INFO_TX_PACKETS		BIT(NL80211_STA_INFO_TX_PACKETS)
+#define STATION_INFO_TX_FAILED		BIT(NL80211_STA_INFO_TX_FAILED)
+#define STATION_INFO_LOCAL_PM		BIT(NL80211_STA_INFO_LOCAL_PM)
+#define STATION_INFO_PEER_PM		BIT(NL80211_STA_INFO_PEER_PM)
+#define STATION_INFO_NONPEER_PM		BIT(NL80211_STA_INFO_NONPEER_PM)
+#define STATION_INFO_ASSOC_REQ_IES	0
+#endif /* Linux kernel >= 4.0.0 */
+
+#include <rtw_wifi_regd.h>
+
+#define RTW_MAX_MGMT_TX_CNT (8)
+#define RTW_MAX_MGMT_TX_MS_GAS (500)
+
+#define RTW_SCAN_IE_LEN_MAX      2304
+#define RTW_MAX_REMAIN_ON_CHANNEL_DURATION 5000 /* ms */
+#define RTW_MAX_NUM_PMKIDS 4
+
+#define RTW_CH_MAX_2G_CHANNEL               14      /* Max channel in 2G band */
+
+#ifdef CONFIG_WAPI_SUPPORT
+
+#ifndef WLAN_CIPHER_SUITE_SMS4
+#define WLAN_CIPHER_SUITE_SMS4          0x00147201
+#endif
+
+#ifndef WLAN_AKM_SUITE_WAPI_PSK
+#define WLAN_AKM_SUITE_WAPI_PSK         0x000FAC04
+#endif
+
+#ifndef WLAN_AKM_SUITE_WAPI_CERT
+#define WLAN_AKM_SUITE_WAPI_CERT        0x000FAC12
+#endif
+
+#ifndef NL80211_WAPI_VERSION_1
+#define NL80211_WAPI_VERSION_1          (1 << 2)
+#endif
+
+#endif /* CONFIG_WAPI_SUPPORT */
+
+#ifdef CONFIG_RTW_80211R
+#define WLAN_AKM_SUITE_FT_8021X		0x000FAC03
+#define WLAN_AKM_SUITE_FT_PSK			0x000FAC04
+#endif
+
+/*
+ * In the current design of Wi-Fi driver, it will return success to the system (e.g. supplicant) 
+ * when Wi-Fi driver decides to abort the scan request in the scan flow by default.
+ * Defining this flag makes Wi-Fi driver to return -EBUSY to the system if Wi-Fi driver is too busy to do the scan.
+ */
+#ifndef CONFIG_NOTIFY_SCAN_ABORT_WITH_BUSY
+	#define CONFIG_NOTIFY_SCAN_ABORT_WITH_BUSY 0
+#endif
+
+static const u32 rtw_cipher_suites[] = {
+	WLAN_CIPHER_SUITE_WEP40,
+	WLAN_CIPHER_SUITE_WEP104,
+	WLAN_CIPHER_SUITE_TKIP,
+	WLAN_CIPHER_SUITE_CCMP,
+#ifdef CONFIG_WAPI_SUPPORT
+	WLAN_CIPHER_SUITE_SMS4,
+#endif /* CONFIG_WAPI_SUPPORT */
+#ifdef CONFIG_IEEE80211W
+	WLAN_CIPHER_SUITE_AES_CMAC,
+#endif /* CONFIG_IEEE80211W */
+};
+
+#define RATETAB_ENT(_rate, _rateid, _flags) \
+	{								\
+		.bitrate	= (_rate),				\
+		.hw_value	= (_rateid),				\
+		.flags		= (_flags),				\
+	}
+
+#define CHAN2G(_channel, _freq, _flags) {			\
+		.band			= NL80211_BAND_2GHZ,		\
+		.center_freq		= (_freq),			\
+		.hw_value		= (_channel),			\
+		.flags			= (_flags),			\
+		.max_antenna_gain	= 0,				\
+		.max_power		= 30,				\
+	}
+
+#define CHAN5G(_channel, _flags) {				\
+		.band			= NL80211_BAND_5GHZ,		\
+		.center_freq		= 5000 + (5 * (_channel)),	\
+		.hw_value		= (_channel),			\
+		.flags			= (_flags),			\
+		.max_antenna_gain	= 0,				\
+		.max_power		= 30,				\
+	}
+
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 0, 0))
+/* if wowlan is not supported, kernel generate a disconnect at each suspend
+ * cf: /net/wireless/sysfs.c, so register a stub wowlan.
+ * Moreover wowlan has to be enabled via a the nl80211_set_wowlan callback.
+ * (from user space, e.g. iw phy0 wowlan enable)
+ */
+static const struct wiphy_wowlan_support wowlan_stub = {
+	.flags = WIPHY_WOWLAN_ANY,
+	.n_patterns = 0,
+	.pattern_max_len = 0,
+	.pattern_min_len = 0,
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 10, 0))
+	.max_pkt_offset = 0,
+#endif
+};
+#endif
+
+static struct ieee80211_rate rtw_rates[] = {
+	RATETAB_ENT(10,  0x1,   0),
+	RATETAB_ENT(20,  0x2,   0),
+	RATETAB_ENT(55,  0x4,   0),
+	RATETAB_ENT(110, 0x8,   0),
+	RATETAB_ENT(60,  0x10,  0),
+	RATETAB_ENT(90,  0x20,  0),
+	RATETAB_ENT(120, 0x40,  0),
+	RATETAB_ENT(180, 0x80,  0),
+	RATETAB_ENT(240, 0x100, 0),
+	RATETAB_ENT(360, 0x200, 0),
+	RATETAB_ENT(480, 0x400, 0),
+	RATETAB_ENT(540, 0x800, 0),
+};
+
+#define rtw_a_rates		(rtw_rates + 4)
+#define RTW_A_RATES_NUM	8
+#define rtw_g_rates		(rtw_rates + 0)
+#define RTW_G_RATES_NUM	12
+
+/* from center_ch_2g */
+static struct ieee80211_channel rtw_2ghz_channels[MAX_CHANNEL_NUM_2G] = {
+	CHAN2G(1, 2412, 0),
+	CHAN2G(2, 2417, 0),
+	CHAN2G(3, 2422, 0),
+	CHAN2G(4, 2427, 0),
+	CHAN2G(5, 2432, 0),
+	CHAN2G(6, 2437, 0),
+	CHAN2G(7, 2442, 0),
+	CHAN2G(8, 2447, 0),
+	CHAN2G(9, 2452, 0),
+	CHAN2G(10, 2457, 0),
+	CHAN2G(11, 2462, 0),
+	CHAN2G(12, 2467, 0),
+	CHAN2G(13, 2472, 0),
+	CHAN2G(14, 2484, 0),
+};
+
+/* from center_ch_5g_20m */
+static struct ieee80211_channel rtw_5ghz_a_channels[MAX_CHANNEL_NUM_5G] = {
+	CHAN5G(36, 0),	CHAN5G(40, 0),	CHAN5G(44, 0),	CHAN5G(48, 0),
+
+	CHAN5G(52, 0),	CHAN5G(56, 0),	CHAN5G(60, 0),	CHAN5G(64, 0),
+
+	CHAN5G(100, 0),	CHAN5G(104, 0),	CHAN5G(108, 0),	CHAN5G(112, 0),
+	CHAN5G(116, 0),	CHAN5G(120, 0),	CHAN5G(124, 0),	CHAN5G(128, 0),
+	CHAN5G(132, 0),	CHAN5G(136, 0),	CHAN5G(140, 0),	CHAN5G(144, 0),
+
+	CHAN5G(149, 0),	CHAN5G(153, 0),	CHAN5G(157, 0),	CHAN5G(161, 0),
+	CHAN5G(165, 0),	CHAN5G(169, 0),	CHAN5G(173, 0),	CHAN5G(177, 0),
+};
+
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 29))
+static const char *nl80211_channel_type_str(enum nl80211_channel_type ctype)
+{
+	switch (ctype) {
+	case NL80211_CHAN_NO_HT:
+		return "NO_HT";
+	case NL80211_CHAN_HT20:
+		return "HT20";
+	case NL80211_CHAN_HT40MINUS:
+		return "HT40-";
+	case NL80211_CHAN_HT40PLUS:
+		return "HT40+";
+	default:
+		return "INVALID";
+	};
+}
+
+static enum nl80211_channel_type rtw_chbw_to_nl80211_channel_type(u8 ch, u8 bw, u8 offset, u8 ht)
+{
+	rtw_warn_on(!ht && (bw >= CHANNEL_WIDTH_40 || offset != HAL_PRIME_CHNL_OFFSET_DONT_CARE));
+
+	if (!ht)
+		return NL80211_CHAN_NO_HT;
+	if (bw >= CHANNEL_WIDTH_40) {
+		if (offset == HAL_PRIME_CHNL_OFFSET_UPPER)
+			return NL80211_CHAN_HT40MINUS;
+		else if (offset == HAL_PRIME_CHNL_OFFSET_LOWER)
+			return NL80211_CHAN_HT40PLUS;
+		else
+			rtw_warn_on(1);
+	}
+	return NL80211_CHAN_HT20;
+}
+
+static void rtw_get_chbw_from_nl80211_channel_type(struct ieee80211_channel *chan, enum nl80211_channel_type ctype, u8 *ht, u8 *ch, u8 *bw, u8 *offset)
+{
+	int pri_freq;
+
+	pri_freq = rtw_ch2freq(chan->hw_value);
+	if (!pri_freq) {
+		RTW_INFO("invalid channel:%d\n", chan->hw_value);
+		rtw_warn_on(1);
+		*ch = 0;
+		return;
+	}
+	*ch = chan->hw_value;
+
+	switch (ctype) {
+	case NL80211_CHAN_NO_HT:
+		*ht = 0;
+		*bw = CHANNEL_WIDTH_20;
+		*offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
+		break;
+	case NL80211_CHAN_HT20:
+		*ht = 1;
+		*bw = CHANNEL_WIDTH_20;
+		*offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
+		break;
+	case NL80211_CHAN_HT40MINUS:
+		*ht = 1;
+		*bw = CHANNEL_WIDTH_40;
+		*offset = HAL_PRIME_CHNL_OFFSET_UPPER;
+		break;
+	case NL80211_CHAN_HT40PLUS:
+		*ht = 1;
+		*bw = CHANNEL_WIDTH_40;
+		*offset = HAL_PRIME_CHNL_OFFSET_LOWER;
+		break;
+	default:
+		*ht = 0;
+		*bw = CHANNEL_WIDTH_20;
+		*offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
+		RTW_INFO("unsupported ctype:%s\n", nl80211_channel_type_str(ctype));
+		rtw_warn_on(1);
+	};
+}
+#endif /* (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 29)) */
+
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 8, 0))
+static const char *nl80211_chan_width_str(enum nl80211_chan_width cwidth)
+{
+	switch (cwidth) {
+	case NL80211_CHAN_WIDTH_20_NOHT:
+		return "20_NOHT";
+	case NL80211_CHAN_WIDTH_20:
+		return "20";
+	case NL80211_CHAN_WIDTH_40:
+		return "40";
+	case NL80211_CHAN_WIDTH_80:
+		return "80";
+	case NL80211_CHAN_WIDTH_80P80:
+		return "80+80";
+	case NL80211_CHAN_WIDTH_160:
+		return "160";
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 11, 0))
+	case NL80211_CHAN_WIDTH_5:
+		return "5";
+	case NL80211_CHAN_WIDTH_10:
+		return "10";
+#endif
+	default:
+		return "INVALID";
+	};
+}
+
+static u8 rtw_chbw_to_cfg80211_chan_def(struct wiphy *wiphy, struct cfg80211_chan_def *chdef, u8 ch, u8 bw, u8 offset, u8 ht)
+{
+	int freq, cfreq;
+	struct ieee80211_channel *chan;
+	u8 ret = _FAIL;
+
+	freq = rtw_ch2freq(ch);
+	if (!freq)
+		goto exit;
+
+	cfreq = rtw_get_center_ch(ch, bw, offset);
+	if (!cfreq)
+		goto exit;
+	cfreq = rtw_ch2freq(cfreq);
+	if (!cfreq)
+		goto exit;
+
+	chan = ieee80211_get_channel(wiphy, freq);
+	if (!chan)
+		goto exit;
+
+	if (bw == CHANNEL_WIDTH_20) 
+		chdef->width = ht ? NL80211_CHAN_WIDTH_20 : NL80211_CHAN_WIDTH_20_NOHT;
+	else if (bw == CHANNEL_WIDTH_40)
+		chdef->width = NL80211_CHAN_WIDTH_40;
+	else if (bw == CHANNEL_WIDTH_80)
+		chdef->width = NL80211_CHAN_WIDTH_80;
+	else if (bw == CHANNEL_WIDTH_160)
+		chdef->width = NL80211_CHAN_WIDTH_160;
+	else {
+		rtw_warn_on(1);
+		goto exit;
+	}
+
+	chdef->chan = chan;
+	chdef->center_freq1 = cfreq;
+	chdef->center_freq2 = 0;
+
+	ret = _SUCCESS;
+
+exit:
+	return ret;
+}
+
+static void rtw_get_chbw_from_cfg80211_chan_def(struct cfg80211_chan_def *chdef, u8 *ht, u8 *ch, u8 *bw, u8 *offset)
+{
+	int pri_freq;
+	struct ieee80211_channel *chan = chdef->chan;
+
+	pri_freq = rtw_ch2freq(chan->hw_value);
+	if (!pri_freq) {
+		RTW_INFO("invalid channel:%d\n", chan->hw_value);
+		rtw_warn_on(1);
+		*ch = 0;
+		return;
+	}		
+
+	switch (chdef->width) {
+	case NL80211_CHAN_WIDTH_20_NOHT:
+		*ht = 0;
+		*bw = CHANNEL_WIDTH_20;
+		*offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
+		*ch = chan->hw_value;
+		break;
+	case NL80211_CHAN_WIDTH_20:
+		*ht = 1;
+		*bw = CHANNEL_WIDTH_20;
+		*offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
+		*ch = chan->hw_value;
+		break;
+	case NL80211_CHAN_WIDTH_40:
+		*ht = 1;
+		*bw = CHANNEL_WIDTH_40;
+		*offset = pri_freq > chdef->center_freq1 ? HAL_PRIME_CHNL_OFFSET_UPPER : HAL_PRIME_CHNL_OFFSET_LOWER;
+		if (rtw_get_offset_by_chbw(chan->hw_value, *bw, offset))
+			*ch = chan->hw_value;
+		break;
+	case NL80211_CHAN_WIDTH_80:
+		*ht = 1;
+		*bw = CHANNEL_WIDTH_80;
+		if (rtw_get_offset_by_chbw(chan->hw_value, *bw, offset))
+			*ch = chan->hw_value;
+		break;
+	case NL80211_CHAN_WIDTH_160:
+		*ht = 1;
+		*bw = CHANNEL_WIDTH_160;
+		if (rtw_get_offset_by_chbw(chan->hw_value, *bw, offset))
+			*ch = chan->hw_value;
+		break;
+	case NL80211_CHAN_WIDTH_80P80:
+	#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 11, 0))
+	case NL80211_CHAN_WIDTH_5:
+	case NL80211_CHAN_WIDTH_10:
+	#endif
+	default:
+		*ht = 0;
+		*bw = CHANNEL_WIDTH_20;
+		*offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
+		RTW_INFO("unsupported cwidth:%s\n", nl80211_chan_width_str(chdef->width));
+		rtw_warn_on(1);
+	};
+}
+#endif /* (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 8, 0)) */
+
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 5, 0))
+u8 rtw_cfg80211_ch_switch_notify(_adapter *adapter, u8 ch, u8 bw, u8 offset, u8 ht)
+{
+	struct wiphy *wiphy = adapter_to_wiphy(adapter);
+	u8 ret = _SUCCESS;
+
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 8, 0))
+	struct cfg80211_chan_def chdef;
+
+	ret = rtw_chbw_to_cfg80211_chan_def(wiphy, &chdef, ch, bw, offset, ht);
+	if (ret != _SUCCESS)
+		goto exit;
+
+	cfg80211_ch_switch_notify(adapter->pnetdev, &chdef);
+
+#else
+	int freq = rtw_ch2freq(ch);
+	enum nl80211_channel_type ctype;
+
+	if (!freq) {
+		ret = _FAIL;
+		goto exit;
+	}
+
+	ctype = rtw_chbw_to_nl80211_channel_type(ch, bw, offset, ht);
+	cfg80211_ch_switch_notify(adapter->pnetdev, freq, ctype);
+#endif
+
+exit:
+	return ret;
+}
+#endif /* (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 5, 0)) */
+
+void rtw_2g_channels_init(struct ieee80211_channel *channels)
+{
+	_rtw_memcpy((void *)channels, (void *)rtw_2ghz_channels, sizeof(rtw_2ghz_channels));
+}
+
+void rtw_5g_channels_init(struct ieee80211_channel *channels)
+{
+	_rtw_memcpy((void *)channels, (void *)rtw_5ghz_a_channels, sizeof(rtw_5ghz_a_channels));
+}
+
+void rtw_2g_rates_init(struct ieee80211_rate *rates)
+{
+	_rtw_memcpy(rates, rtw_g_rates,
+		sizeof(struct ieee80211_rate) * RTW_G_RATES_NUM
+	);
+}
+
+void rtw_5g_rates_init(struct ieee80211_rate *rates)
+{
+	_rtw_memcpy(rates, rtw_a_rates,
+		sizeof(struct ieee80211_rate) * RTW_A_RATES_NUM
+	);
+}
+
+struct ieee80211_supported_band *rtw_spt_band_alloc(BAND_TYPE band)
+{
+	struct ieee80211_supported_band *spt_band = NULL;
+	int n_channels, n_bitrates;
+
+	if (band == BAND_ON_2_4G) {
+		n_channels = MAX_CHANNEL_NUM_2G;
+		n_bitrates = RTW_G_RATES_NUM;
+	} else if (band == BAND_ON_5G) {
+		n_channels = MAX_CHANNEL_NUM_5G;
+		n_bitrates = RTW_A_RATES_NUM;
+	} else
+		goto exit;
+
+	spt_band = (struct ieee80211_supported_band *)rtw_zmalloc(
+		sizeof(struct ieee80211_supported_band)
+		+ sizeof(struct ieee80211_channel) * n_channels
+		+ sizeof(struct ieee80211_rate) * n_bitrates
+	);
+	if (!spt_band)
+		goto exit;
+
+	spt_band->channels = (struct ieee80211_channel *)(((u8 *)spt_band) + sizeof(struct ieee80211_supported_band));
+	spt_band->bitrates = (struct ieee80211_rate *)(((u8 *)spt_band->channels) + sizeof(struct ieee80211_channel) * n_channels);
+	spt_band->band = rtw_band_to_nl80211_band(band);
+	spt_band->n_channels = n_channels;
+	spt_band->n_bitrates = n_bitrates;
+
+	if (band == BAND_ON_2_4G) {
+		rtw_2g_channels_init(spt_band->channels);
+		rtw_2g_rates_init(spt_band->bitrates);
+	} else if (band == BAND_ON_5G) {
+		rtw_5g_channels_init(spt_band->channels);
+		rtw_5g_rates_init(spt_band->bitrates);
+	}
+
+	/* spt_band.ht_cap */
+
+exit:
+
+	return spt_band;
+}
+
+void rtw_spt_band_free(struct ieee80211_supported_band *spt_band)
+{
+	u32 size = 0;
+
+	if (!spt_band)
+		return;
+
+	if (spt_band->band == NL80211_BAND_2GHZ) {
+		size = sizeof(struct ieee80211_supported_band)
+			+ sizeof(struct ieee80211_channel) * MAX_CHANNEL_NUM_2G
+			+ sizeof(struct ieee80211_rate) * RTW_G_RATES_NUM;
+	} else if (spt_band->band == NL80211_BAND_5GHZ) {
+		size = sizeof(struct ieee80211_supported_band)
+			+ sizeof(struct ieee80211_channel) * MAX_CHANNEL_NUM_5G
+			+ sizeof(struct ieee80211_rate) * RTW_A_RATES_NUM;
+	} else {
+
+	}
+	rtw_mfree((u8 *)spt_band, size);
+}
+
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) || defined(COMPAT_KERNEL_RELEASE)
+static const struct ieee80211_txrx_stypes
+	rtw_cfg80211_default_mgmt_stypes[NUM_NL80211_IFTYPES] = {
+	[NL80211_IFTYPE_ADHOC] = {
+		.tx = 0xffff,
+		.rx = BIT(IEEE80211_STYPE_ACTION >> 4)
+	},
+	[NL80211_IFTYPE_STATION] = {
+		.tx = 0xffff,
+		.rx = BIT(IEEE80211_STYPE_ACTION >> 4) |
+		BIT(IEEE80211_STYPE_PROBE_REQ >> 4)
+	},
+	[NL80211_IFTYPE_AP] = {
+		.tx = 0xffff,
+		.rx = BIT(IEEE80211_STYPE_ASSOC_REQ >> 4) |
+		BIT(IEEE80211_STYPE_REASSOC_REQ >> 4) |
+		BIT(IEEE80211_STYPE_PROBE_REQ >> 4) |
+		BIT(IEEE80211_STYPE_DISASSOC >> 4) |
+		BIT(IEEE80211_STYPE_AUTH >> 4) |
+		BIT(IEEE80211_STYPE_DEAUTH >> 4) |
+		BIT(IEEE80211_STYPE_ACTION >> 4)
+	},
+	[NL80211_IFTYPE_AP_VLAN] = {
+		/* copy AP */
+		.tx = 0xffff,
+		.rx = BIT(IEEE80211_STYPE_ASSOC_REQ >> 4) |
+		BIT(IEEE80211_STYPE_REASSOC_REQ >> 4) |
+		BIT(IEEE80211_STYPE_PROBE_REQ >> 4) |
+		BIT(IEEE80211_STYPE_DISASSOC >> 4) |
+		BIT(IEEE80211_STYPE_AUTH >> 4) |
+		BIT(IEEE80211_STYPE_DEAUTH >> 4) |
+		BIT(IEEE80211_STYPE_ACTION >> 4)
+	},
+	[NL80211_IFTYPE_P2P_CLIENT] = {
+		.tx = 0xffff,
+		.rx = BIT(IEEE80211_STYPE_ACTION >> 4) |
+		BIT(IEEE80211_STYPE_PROBE_REQ >> 4)
+	},
+	[NL80211_IFTYPE_P2P_GO] = {
+		.tx = 0xffff,
+		.rx = BIT(IEEE80211_STYPE_ASSOC_REQ >> 4) |
+		BIT(IEEE80211_STYPE_REASSOC_REQ >> 4) |
+		BIT(IEEE80211_STYPE_PROBE_REQ >> 4) |
+		BIT(IEEE80211_STYPE_DISASSOC >> 4) |
+		BIT(IEEE80211_STYPE_AUTH >> 4) |
+		BIT(IEEE80211_STYPE_DEAUTH >> 4) |
+		BIT(IEEE80211_STYPE_ACTION >> 4)
+	},
+#if defined(RTW_DEDICATED_P2P_DEVICE)
+	[NL80211_IFTYPE_P2P_DEVICE] = {
+		.tx = 0xffff,
+		.rx = BIT(IEEE80211_STYPE_ACTION >> 4) |
+			BIT(IEEE80211_STYPE_PROBE_REQ >> 4)
+	},
+#endif
+#if defined(CONFIG_RTW_MESH)
+	[NL80211_IFTYPE_MESH_POINT] = {
+		.tx = 0xffff,
+		.rx = BIT(IEEE80211_STYPE_ACTION >> 4)
+			| BIT(IEEE80211_STYPE_AUTH >> 4)
+	},
+#endif
+
+};
+#endif
+
+NDIS_802_11_NETWORK_INFRASTRUCTURE nl80211_iftype_to_rtw_network_type(enum nl80211_iftype type)
+{
+	switch (type) {
+	case NL80211_IFTYPE_ADHOC:
+		return Ndis802_11IBSS;
+
+	#if defined(CONFIG_P2P) && ((LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) || defined(COMPAT_KERNEL_RELEASE))
+	case NL80211_IFTYPE_P2P_CLIENT:
+	#endif
+	case NL80211_IFTYPE_STATION:
+		return Ndis802_11Infrastructure;
+
+#ifdef CONFIG_AP_MODE
+	#if defined(CONFIG_P2P) && ((LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) || defined(COMPAT_KERNEL_RELEASE))
+	case NL80211_IFTYPE_P2P_GO:
+	#endif
+	case NL80211_IFTYPE_AP:
+		return Ndis802_11APMode;
+#endif
+
+#ifdef CONFIG_RTW_MESH
+	case NL80211_IFTYPE_MESH_POINT:
+		return Ndis802_11_mesh;
+#endif
+
+	case NL80211_IFTYPE_MONITOR:
+		return Ndis802_11Monitor;
+
+	default:
+		return Ndis802_11InfrastructureMax;
+	}
+}
+
+u32 nl80211_iftype_to_rtw_mlme_state(enum nl80211_iftype type)
+{
+	switch (type) {
+	case NL80211_IFTYPE_ADHOC:
+		return WIFI_ADHOC_STATE;
+
+	#if defined(CONFIG_P2P) && ((LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) || defined(COMPAT_KERNEL_RELEASE))
+	case NL80211_IFTYPE_P2P_CLIENT:
+	#endif
+	case NL80211_IFTYPE_STATION:
+		return WIFI_STATION_STATE;
+
+#ifdef CONFIG_AP_MODE
+	#if defined(CONFIG_P2P) && ((LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) || defined(COMPAT_KERNEL_RELEASE))
+	case NL80211_IFTYPE_P2P_GO:
+	#endif
+	case NL80211_IFTYPE_AP:
+		return WIFI_AP_STATE;
+#endif
+
+#ifdef CONFIG_RTW_MESH
+	case NL80211_IFTYPE_MESH_POINT:
+		return WIFI_MESH_STATE;
+#endif
+
+	case NL80211_IFTYPE_MONITOR:
+		return WIFI_MONITOR_STATE;
+
+	default:
+		return WIFI_NULL_STATE;
+	}
+}
+
+static int rtw_cfg80211_sync_iftype(_adapter *adapter)
+{
+	struct wireless_dev *rtw_wdev = adapter->rtw_wdev;
+
+	if (!(nl80211_iftype_to_rtw_mlme_state(rtw_wdev->iftype) & MLME_STATE(adapter))) {
+		/* iftype and mlme state is not syc */
+		NDIS_802_11_NETWORK_INFRASTRUCTURE network_type;
+
+		network_type = nl80211_iftype_to_rtw_network_type(rtw_wdev->iftype);
+		if (network_type != Ndis802_11InfrastructureMax) {
+			if (rtw_pwr_wakeup(adapter) == _FAIL) {
+				RTW_WARN(FUNC_ADPT_FMT" call rtw_pwr_wakeup fail\n", FUNC_ADPT_ARG(adapter));
+				return _FAIL;
+			}
+
+			rtw_set_802_11_infrastructure_mode(adapter, network_type);
+			rtw_setopmode_cmd(adapter, network_type, RTW_CMDF_WAIT_ACK);
+		} else {
+			rtw_warn_on(1);
+			RTW_WARN(FUNC_ADPT_FMT" iftype:%u is not support\n", FUNC_ADPT_ARG(adapter), rtw_wdev->iftype);
+			return _FAIL;
+		}
+	}
+
+	return _SUCCESS;
+}
+
+static u64 rtw_get_systime_us(void)
+{
+	return ktime_to_us(ktime_get_boottime());
+}
+
+/* Try to remove non target BSS's SR to reduce PBC overlap rate */
+static int rtw_cfg80211_clear_wps_sr_of_non_target_bss(_adapter *padapter, struct wlan_network *pnetwork, struct cfg80211_ssid *req_ssid)
+{
+	int ret = 0;
+	u8 *psr = NULL, sr = 0;
+	NDIS_802_11_SSID *pssid = &pnetwork->network.Ssid;
+	u32 wpsielen = 0;
+	u8 *wpsie = NULL;
+
+	if (pssid->SsidLength == req_ssid->ssid_len
+		&& _rtw_memcmp(pssid->Ssid, req_ssid->ssid, req_ssid->ssid_len) == _TRUE)
+		goto exit;
+
+	wpsie = rtw_get_wps_ie(pnetwork->network.IEs + _FIXED_IE_LENGTH_
+		, pnetwork->network.IELength - _FIXED_IE_LENGTH_, NULL, &wpsielen);
+	if (wpsie && wpsielen > 0)
+		psr = rtw_get_wps_attr_content(wpsie, wpsielen, WPS_ATTR_SELECTED_REGISTRAR, &sr, NULL);
+
+	if (psr && sr) {
+		if (0)
+			RTW_INFO("clear sr of non target bss:%s("MAC_FMT")\n"
+				, pssid->Ssid, MAC_ARG(pnetwork->network.MacAddress));
+		*psr = 0; /* clear sr */
+		ret = 1;
+	}
+
+exit:
+	return ret;
+}
+
+#define MAX_BSSINFO_LEN 1000
+struct cfg80211_bss *rtw_cfg80211_inform_bss(_adapter *padapter, struct wlan_network *pnetwork)
+{
+	struct ieee80211_channel *notify_channel;
+	struct cfg80211_bss *bss = NULL;
+	/* struct ieee80211_supported_band *band;       */
+	u16 channel;
+	u32 freq;
+	u64 notify_timestamp;
+	u16 notify_capability;
+	u16 notify_interval;
+	u8 *notify_ie;
+	size_t notify_ielen;
+	s32 notify_signal;
+	/* u8 buf[MAX_BSSINFO_LEN]; */
+
+	u8 *pbuf;
+	size_t buf_size = MAX_BSSINFO_LEN;
+	size_t len, bssinf_len = 0;
+	struct rtw_ieee80211_hdr *pwlanhdr;
+	unsigned short *fctrl;
+	u8	bc_addr[] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
+
+	struct wireless_dev *wdev = padapter->rtw_wdev;
+	struct wiphy *wiphy = wdev->wiphy;
+	struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
+
+	pbuf = rtw_zmalloc(buf_size);
+	if (pbuf == NULL) {
+		RTW_INFO("%s pbuf allocate failed  !!\n", __FUNCTION__);
+		return bss;
+	}
+
+	/* RTW_INFO("%s\n", __func__); */
+
+	bssinf_len = pnetwork->network.IELength + sizeof(struct rtw_ieee80211_hdr_3addr);
+	if (bssinf_len > buf_size) {
+		RTW_INFO("%s IE Length too long > %zu byte\n", __FUNCTION__, buf_size);
+		goto exit;
+	}
+
+#ifndef CONFIG_WAPI_SUPPORT
+	{
+		u16 wapi_len = 0;
+
+		if (rtw_get_wapi_ie(pnetwork->network.IEs, pnetwork->network.IELength, NULL, &wapi_len) > 0) {
+			if (wapi_len > 0) {
+				RTW_INFO("%s, no support wapi!\n", __FUNCTION__);
+				goto exit;
+			}
+		}
+	}
+#endif /* !CONFIG_WAPI_SUPPORT */
+
+	channel = pnetwork->network.Configuration.DSConfig;
+	freq = rtw_ch2freq(channel);
+	notify_channel = ieee80211_get_channel(wiphy, freq);
+
+	if (0)
+		notify_timestamp = le64_to_cpu(*(u64 *)rtw_get_timestampe_from_ie(pnetwork->network.IEs));
+	else
+		notify_timestamp = rtw_get_systime_us();
+
+	notify_interval = le16_to_cpu(*(u16 *)rtw_get_beacon_interval_from_ie(pnetwork->network.IEs));
+	notify_capability = le16_to_cpu(*(u16 *)rtw_get_capability_from_ie(pnetwork->network.IEs));
+
+	notify_ie = pnetwork->network.IEs + _FIXED_IE_LENGTH_;
+	notify_ielen = pnetwork->network.IELength - _FIXED_IE_LENGTH_;
+
+	/* We've set wiphy's signal_type as CFG80211_SIGNAL_TYPE_MBM: signal strength in mBm (100*dBm) */
+	if (check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE &&
+		is_same_network(&pmlmepriv->cur_network.network, &pnetwork->network, 0)) {
+		notify_signal = 100 * translate_percentage_to_dbm(padapter->recvpriv.signal_strength); /* dbm */
+	} else {
+		notify_signal = 100 * translate_percentage_to_dbm(pnetwork->network.PhyInfo.SignalStrength); /* dbm */
+	}
+
+#if 0
+	RTW_INFO("bssid: "MAC_FMT"\n", MAC_ARG(pnetwork->network.MacAddress));
+	RTW_INFO("Channel: %d(%d)\n", channel, freq);
+	RTW_INFO("Capability: %X\n", notify_capability);
+	RTW_INFO("Beacon interval: %d\n", notify_interval);
+	RTW_INFO("Signal: %d\n", notify_signal);
+	RTW_INFO("notify_timestamp: %llu\n", notify_timestamp);
+#endif
+
+	/* pbuf = buf; */
+
+	pwlanhdr = (struct rtw_ieee80211_hdr *)pbuf;
+	fctrl = &(pwlanhdr->frame_ctl);
+	*(fctrl) = 0;
+
+	SetSeqNum(pwlanhdr, 0/*pmlmeext->mgnt_seq*/);
+	/* pmlmeext->mgnt_seq++; */
+
+	if (pnetwork->network.Reserved[0] == BSS_TYPE_BCN) { /* WIFI_BEACON */
+		_rtw_memcpy(pwlanhdr->addr1, bc_addr, ETH_ALEN);
+		set_frame_sub_type(pbuf, WIFI_BEACON);
+	} else {
+		_rtw_memcpy(pwlanhdr->addr1, adapter_mac_addr(padapter), ETH_ALEN);
+		set_frame_sub_type(pbuf, WIFI_PROBERSP);
+	}
+
+	_rtw_memcpy(pwlanhdr->addr2, pnetwork->network.MacAddress, ETH_ALEN);
+	_rtw_memcpy(pwlanhdr->addr3, pnetwork->network.MacAddress, ETH_ALEN);
+
+
+	/* pbuf += sizeof(struct rtw_ieee80211_hdr_3addr); */
+	len = sizeof(struct rtw_ieee80211_hdr_3addr);
+	_rtw_memcpy((pbuf + len), pnetwork->network.IEs, pnetwork->network.IELength);
+	*((u64 *)(pbuf + len)) = cpu_to_le64(notify_timestamp);
+
+	len += pnetwork->network.IELength;
+
+	#if defined(CONFIG_P2P) && 0
+	if(rtw_get_p2p_ie(pnetwork->network.IEs+12, pnetwork->network.IELength-12, NULL, NULL))
+		RTW_INFO("%s, got p2p_ie\n", __func__);
+	#endif
+
+#if 1
+	bss = cfg80211_inform_bss_frame(wiphy, notify_channel, (struct ieee80211_mgmt *)pbuf,
+					len, notify_signal, GFP_ATOMIC);
+#else
+
+	bss = cfg80211_inform_bss(wiphy, notify_channel, (const u8 *)pnetwork->network.MacAddress,
+		notify_timestamp, notify_capability, notify_interval, notify_ie,
+		notify_ielen, notify_signal, GFP_ATOMIC/*GFP_KERNEL*/);
+#endif
+
+	if (unlikely(!bss)) {
+		RTW_INFO(FUNC_ADPT_FMT" bss NULL\n", FUNC_ADPT_ARG(padapter));
+		goto exit;
+	}
+
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 38))
+#ifndef COMPAT_KERNEL_RELEASE
+	/* patch for cfg80211, update beacon ies to information_elements */
+	if (pnetwork->network.Reserved[0] == BSS_TYPE_BCN) { /* WIFI_BEACON */
+
+		if (bss->len_information_elements != bss->len_beacon_ies) {
+			bss->information_elements = bss->beacon_ies;
+			bss->len_information_elements =  bss->len_beacon_ies;
+		}
+	}
+#endif /* COMPAT_KERNEL_RELEASE */
+#endif /* LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 38) */
+
+#if 0
+	{
+		if (bss->information_elements == bss->proberesp_ies) {
+			if (bss->len_information_elements !=  bss->len_proberesp_ies)
+				RTW_INFO("error!, len_information_elements != bss->len_proberesp_ies\n");
+		} else if (bss->len_information_elements <  bss->len_beacon_ies) {
+			bss->information_elements = bss->beacon_ies;
+			bss->len_information_elements =  bss->len_beacon_ies;
+		}
+	}
+#endif
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(3, 9, 0)
+	cfg80211_put_bss(wiphy, bss);
+#else
+	cfg80211_put_bss(bss);
+#endif
+
+exit:
+	if (pbuf)
+		rtw_mfree(pbuf, buf_size);
+	return bss;
+
+}
+
+/*
+	Check the given bss is valid by kernel API cfg80211_get_bss()
+	@padapter : the given adapter
+
+	return _TRUE if bss is valid,  _FALSE for not found.
+*/
+int rtw_cfg80211_check_bss(_adapter *padapter)
+{
+	WLAN_BSSID_EX  *pnetwork = &(padapter->mlmeextpriv.mlmext_info.network);
+	struct cfg80211_bss *bss = NULL;
+	struct ieee80211_channel *notify_channel = NULL;
+	u32 freq;
+
+	if (!(pnetwork) || !(padapter->rtw_wdev))
+		return _FALSE;
+
+	freq = rtw_ch2freq(pnetwork->Configuration.DSConfig);
+	notify_channel = ieee80211_get_channel(padapter->rtw_wdev->wiphy, freq);
+	bss = cfg80211_get_bss(padapter->rtw_wdev->wiphy, notify_channel,
+			pnetwork->MacAddress, pnetwork->Ssid.Ssid,
+			pnetwork->Ssid.SsidLength,
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 1, 0)
+			pnetwork->InfrastructureMode == Ndis802_11Infrastructure?IEEE80211_BSS_TYPE_ESS:IEEE80211_BSS_TYPE_IBSS,
+			IEEE80211_PRIVACY(pnetwork->Privacy));
+#else
+			pnetwork->InfrastructureMode == Ndis802_11Infrastructure?WLAN_CAPABILITY_ESS:WLAN_CAPABILITY_IBSS, pnetwork->InfrastructureMode == Ndis802_11Infrastructure?WLAN_CAPABILITY_ESS:WLAN_CAPABILITY_IBSS);
+#endif
+
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(3, 9, 0)
+	cfg80211_put_bss(padapter->rtw_wdev->wiphy, bss);
+#else
+	cfg80211_put_bss(bss);
+#endif
+
+	return bss != NULL;
+}
+
+void rtw_cfg80211_ibss_indicate_connect(_adapter *padapter)
+{
+	struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
+	struct wlan_network  *cur_network = &(pmlmepriv->cur_network);
+	struct wireless_dev *pwdev = padapter->rtw_wdev;
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 15, 0))
+	struct wiphy *wiphy = pwdev->wiphy;
+	int freq = 2412;
+	struct ieee80211_channel *notify_channel;
+#endif
+
+	RTW_INFO(FUNC_ADPT_FMT"\n", FUNC_ADPT_ARG(padapter));
+
+	if (pwdev->iftype != NL80211_IFTYPE_ADHOC)
+		return;
+
+	if (!rtw_cfg80211_check_bss(padapter)) {
+		WLAN_BSSID_EX  *pnetwork = &(padapter->mlmeextpriv.mlmext_info.network);
+		struct wlan_network *scanned = pmlmepriv->cur_network_scanned;
+
+		if (check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE) == _TRUE) {
+
+			_rtw_memcpy(&cur_network->network, pnetwork, sizeof(WLAN_BSSID_EX));
+			if (cur_network) {
+				if (!rtw_cfg80211_inform_bss(padapter, cur_network))
+					RTW_INFO(FUNC_ADPT_FMT" inform fail !!\n", FUNC_ADPT_ARG(padapter));
+				else
+					RTW_INFO(FUNC_ADPT_FMT" inform success !!\n", FUNC_ADPT_ARG(padapter));
+			} else {
+				RTW_INFO("cur_network is not exist!!!\n");
+				return ;
+			}
+		} else {
+			if (scanned == NULL)
+				rtw_warn_on(1);
+
+			if (_rtw_memcmp(&(scanned->network.Ssid), &(pnetwork->Ssid), sizeof(NDIS_802_11_SSID)) == _TRUE
+				&& _rtw_memcmp(scanned->network.MacAddress, pnetwork->MacAddress, sizeof(NDIS_802_11_MAC_ADDRESS)) == _TRUE
+			) {
+				if (!rtw_cfg80211_inform_bss(padapter, scanned))
+					RTW_INFO(FUNC_ADPT_FMT" inform fail !!\n", FUNC_ADPT_ARG(padapter));
+				else {
+					/* RTW_INFO(FUNC_ADPT_FMT" inform success !!\n", FUNC_ADPT_ARG(padapter)); */
+				}
+			} else {
+				RTW_INFO("scanned & pnetwork compare fail\n");
+				rtw_warn_on(1);
+			}
+		}
+
+		if (!rtw_cfg80211_check_bss(padapter))
+			RTW_PRINT(FUNC_ADPT_FMT" BSS not found !!\n", FUNC_ADPT_ARG(padapter));
+	}
+	/* notify cfg80211 that device joined an IBSS */
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 15, 0))
+	freq = rtw_ch2freq(cur_network->network.Configuration.DSConfig);
+	if (1)
+		RTW_INFO("chan: %d, freq: %d\n", cur_network->network.Configuration.DSConfig, freq);
+	notify_channel = ieee80211_get_channel(wiphy, freq);
+	cfg80211_ibss_joined(padapter->pnetdev, cur_network->network.MacAddress, notify_channel, GFP_ATOMIC);
+#else
+	cfg80211_ibss_joined(padapter->pnetdev, cur_network->network.MacAddress, GFP_ATOMIC);
+#endif
+}
+
+void rtw_cfg80211_indicate_connect(_adapter *padapter)
+{
+	struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
+	struct wlan_network  *cur_network = &(pmlmepriv->cur_network);
+	struct wireless_dev *pwdev = padapter->rtw_wdev;
+	struct rtw_wdev_priv *pwdev_priv = adapter_wdev_data(padapter);
+	_irqL irqL;
+#ifdef CONFIG_P2P
+	struct wifidirect_info *pwdinfo = &(padapter->wdinfo);
+#endif
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 12, 0)
+	struct cfg80211_roam_info roam_info ={};
+#endif
+
+	RTW_INFO(FUNC_ADPT_FMT"\n", FUNC_ADPT_ARG(padapter));
+	if (pwdev->iftype != NL80211_IFTYPE_STATION
+		#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) || defined(COMPAT_KERNEL_RELEASE)
+		&& pwdev->iftype != NL80211_IFTYPE_P2P_CLIENT
+		#endif
+	)
+		return;
+
+	if (!MLME_IS_STA(padapter))
+		return;
+
+#ifdef CONFIG_P2P
+	if (pwdinfo->driver_interface == DRIVER_CFG80211) {
+		#if !RTW_P2P_GROUP_INTERFACE
+		if (!rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE)) {
+			rtw_p2p_set_pre_state(pwdinfo, rtw_p2p_state(pwdinfo));
+			rtw_p2p_set_role(pwdinfo, P2P_ROLE_CLIENT);
+			rtw_p2p_set_state(pwdinfo, P2P_STATE_GONEGO_OK);
+			RTW_INFO("%s, role=%d, p2p_state=%d, pre_p2p_state=%d\n", __func__, rtw_p2p_role(pwdinfo), rtw_p2p_state(pwdinfo), rtw_p2p_pre_state(pwdinfo));
+		}
+		#endif
+	}
+#endif /* CONFIG_P2P */
+
+	if (check_fwstate(pmlmepriv, WIFI_MONITOR_STATE) != _TRUE) {
+		WLAN_BSSID_EX  *pnetwork = &(padapter->mlmeextpriv.mlmext_info.network);
+		struct wlan_network *scanned = pmlmepriv->cur_network_scanned;
+
+		/* RTW_INFO(FUNC_ADPT_FMT" BSS not found\n", FUNC_ADPT_ARG(padapter)); */
+
+		if (scanned == NULL) {
+			rtw_warn_on(1);
+			goto check_bss;
+		}
+
+		if (_rtw_memcmp(scanned->network.MacAddress, pnetwork->MacAddress, sizeof(NDIS_802_11_MAC_ADDRESS)) == _TRUE
+			&& _rtw_memcmp(&(scanned->network.Ssid), &(pnetwork->Ssid), sizeof(NDIS_802_11_SSID)) == _TRUE
+		) {
+			if (!rtw_cfg80211_inform_bss(padapter, scanned))
+				RTW_INFO(FUNC_ADPT_FMT" inform fail !!\n", FUNC_ADPT_ARG(padapter));
+			else {
+				/* RTW_INFO(FUNC_ADPT_FMT" inform success !!\n", FUNC_ADPT_ARG(padapter)); */
+			}
+		} else {
+			RTW_INFO("scanned: %s("MAC_FMT"), cur: %s("MAC_FMT")\n",
+				scanned->network.Ssid.Ssid, MAC_ARG(scanned->network.MacAddress),
+				pnetwork->Ssid.Ssid, MAC_ARG(pnetwork->MacAddress)
+			);
+			rtw_warn_on(1);
+		}
+	}
+
+check_bss:
+	if (!rtw_cfg80211_check_bss(padapter))
+		RTW_PRINT(FUNC_ADPT_FMT" BSS not found !!\n", FUNC_ADPT_ARG(padapter));
+
+	_enter_critical_bh(&pwdev_priv->connect_req_lock, &irqL);
+
+	if (rtw_to_roam(padapter) > 0) {
+		#if LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 39) || defined(COMPAT_KERNEL_RELEASE)
+		struct wiphy *wiphy = pwdev->wiphy;
+		struct ieee80211_channel *notify_channel;
+		u32 freq;
+		u16 channel = cur_network->network.Configuration.DSConfig;
+
+		freq = rtw_ch2freq(channel);
+		notify_channel = ieee80211_get_channel(wiphy, freq);
+		#endif
+
+		#if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 12, 0)
+		roam_info.bssid = cur_network->network.MacAddress;
+		roam_info.req_ie = pmlmepriv->assoc_req + sizeof(struct rtw_ieee80211_hdr_3addr) + 2;
+		roam_info.req_ie_len = pmlmepriv->assoc_req_len - sizeof(struct rtw_ieee80211_hdr_3addr) - 2;
+		roam_info.resp_ie = pmlmepriv->assoc_rsp + sizeof(struct rtw_ieee80211_hdr_3addr) + 6;
+		roam_info.resp_ie_len = pmlmepriv->assoc_rsp_len - sizeof(struct rtw_ieee80211_hdr_3addr) - 6;
+
+		cfg80211_roamed(padapter->pnetdev, &roam_info, GFP_ATOMIC);
+		#else
+		cfg80211_roamed(padapter->pnetdev
+			#if LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 39) || defined(COMPAT_KERNEL_RELEASE)
+			, notify_channel
+			#endif
+			, cur_network->network.MacAddress
+			, pmlmepriv->assoc_req + sizeof(struct rtw_ieee80211_hdr_3addr) + 2
+			, pmlmepriv->assoc_req_len - sizeof(struct rtw_ieee80211_hdr_3addr) - 2
+			, pmlmepriv->assoc_rsp + sizeof(struct rtw_ieee80211_hdr_3addr) + 6
+			, pmlmepriv->assoc_rsp_len - sizeof(struct rtw_ieee80211_hdr_3addr) - 6
+			, GFP_ATOMIC);
+		#endif /*LINUX_VERSION_CODE >= KERNEL_VERSION(4, 12, 0)*/
+
+		RTW_INFO(FUNC_ADPT_FMT" call cfg80211_roamed\n", FUNC_ADPT_ARG(padapter));
+
+#ifdef CONFIG_RTW_80211R
+		if (rtw_ft_roam(padapter))
+			rtw_ft_set_status(padapter, RTW_FT_ASSOCIATED_STA);
+#endif
+	} else {
+		#if LINUX_VERSION_CODE < KERNEL_VERSION(3, 11, 0) || defined(COMPAT_KERNEL_RELEASE)
+		RTW_INFO("pwdev->sme_state(b)=%d\n", pwdev->sme_state);
+		#endif
+
+		if (check_fwstate(pmlmepriv, WIFI_MONITOR_STATE) != _TRUE)
+			rtw_cfg80211_connect_result(pwdev, cur_network->network.MacAddress
+				, pmlmepriv->assoc_req + sizeof(struct rtw_ieee80211_hdr_3addr) + 2
+				, pmlmepriv->assoc_req_len - sizeof(struct rtw_ieee80211_hdr_3addr) - 2
+				, pmlmepriv->assoc_rsp + sizeof(struct rtw_ieee80211_hdr_3addr) + 6
+				, pmlmepriv->assoc_rsp_len - sizeof(struct rtw_ieee80211_hdr_3addr) - 6
+				, WLAN_STATUS_SUCCESS, GFP_ATOMIC);
+		#if LINUX_VERSION_CODE < KERNEL_VERSION(3, 11, 0) || defined(COMPAT_KERNEL_RELEASE)
+		RTW_INFO("pwdev->sme_state(a)=%d\n", pwdev->sme_state);
+		#endif
+	}
+
+	rtw_wdev_free_connect_req(pwdev_priv);
+
+	_exit_critical_bh(&pwdev_priv->connect_req_lock, &irqL);
+}
+
+void rtw_cfg80211_indicate_disconnect(_adapter *padapter, u16 reason, u8 locally_generated)
+{
+	struct wireless_dev *pwdev = padapter->rtw_wdev;
+	struct rtw_wdev_priv *pwdev_priv = adapter_wdev_data(padapter);
+	_irqL irqL;
+#ifdef CONFIG_P2P
+	struct wifidirect_info *pwdinfo = &(padapter->wdinfo);
+#endif
+
+	RTW_INFO(FUNC_ADPT_FMT"\n", FUNC_ADPT_ARG(padapter));
+
+	/*always replace privated definitions with wifi reserved value 0*/
+	if (WLAN_REASON_IS_PRIVATE(reason))
+		reason = 0;
+
+	if (pwdev->iftype != NL80211_IFTYPE_STATION
+		#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) || defined(COMPAT_KERNEL_RELEASE)
+		&& pwdev->iftype != NL80211_IFTYPE_P2P_CLIENT
+		#endif
+	)
+		return;
+
+	if (!MLME_IS_STA(padapter))
+		return;
+
+#ifdef CONFIG_P2P
+	if (pwdinfo->driver_interface == DRIVER_CFG80211) {
+		if (!rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE)) {
+			rtw_p2p_set_state(pwdinfo, rtw_p2p_pre_state(pwdinfo));
+
+			#if RTW_P2P_GROUP_INTERFACE
+			#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) || defined(COMPAT_KERNEL_RELEASE)
+			if (pwdev->iftype != NL80211_IFTYPE_P2P_CLIENT)
+			#endif
+			#endif
+				rtw_p2p_set_role(pwdinfo, P2P_ROLE_DEVICE);
+
+			RTW_INFO("%s, role=%d, p2p_state=%d, pre_p2p_state=%d\n", __func__, rtw_p2p_role(pwdinfo), rtw_p2p_state(pwdinfo), rtw_p2p_pre_state(pwdinfo));
+		}
+	}
+#endif /* CONFIG_P2P */
+
+	_enter_critical_bh(&pwdev_priv->connect_req_lock, &irqL);
+
+	if (padapter->ndev_unregistering || !rtw_wdev_not_indic_disco(pwdev_priv)) {
+		#if LINUX_VERSION_CODE < KERNEL_VERSION(3, 11, 0) || defined(COMPAT_KERNEL_RELEASE)
+		RTW_INFO("pwdev->sme_state(b)=%d\n", pwdev->sme_state);
+
+		if (pwdev->sme_state == CFG80211_SME_CONNECTING) {
+			RTW_INFO(FUNC_ADPT_FMT" call cfg80211_connect_result\n", FUNC_ADPT_ARG(padapter));
+			rtw_cfg80211_connect_result(pwdev, NULL, NULL, 0, NULL, 0,
+				reason, GFP_ATOMIC);
+		} else if (pwdev->sme_state == CFG80211_SME_CONNECTED) {
+			RTW_INFO(FUNC_ADPT_FMT" call cfg80211_disconnected\n", FUNC_ADPT_ARG(padapter));
+			rtw_cfg80211_disconnected(pwdev, reason, NULL, 0, locally_generated, GFP_ATOMIC);
+		}
+
+		RTW_INFO("pwdev->sme_state(a)=%d\n", pwdev->sme_state);
+		#else
+		if (pwdev_priv->connect_req) {
+			RTW_INFO(FUNC_ADPT_FMT" call cfg80211_connect_result\n", FUNC_ADPT_ARG(padapter));
+			rtw_cfg80211_connect_result(pwdev, NULL, NULL, 0, NULL, 0,
+				reason, GFP_ATOMIC);
+		} else {
+			RTW_INFO(FUNC_ADPT_FMT" call cfg80211_disconnected\n", FUNC_ADPT_ARG(padapter));
+			rtw_cfg80211_disconnected(pwdev, reason, NULL, 0, locally_generated, GFP_ATOMIC);
+		}
+		#endif
+	}
+
+	rtw_wdev_free_connect_req(pwdev_priv);
+
+	_exit_critical_bh(&pwdev_priv->connect_req_lock, &irqL);
+}
+
+
+#ifdef CONFIG_AP_MODE
+static int rtw_cfg80211_ap_set_encryption(struct net_device *dev, struct ieee_param *param)
+{
+	int ret = 0;
+	u32 wep_key_idx, wep_key_len;
+	struct sta_info *psta = NULL, *pbcmc_sta = NULL;
+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
+	struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
+	struct security_priv *psecuritypriv = &(padapter->securitypriv);
+	struct sta_priv *pstapriv = &padapter->stapriv;
+
+	RTW_INFO("%s\n", __FUNCTION__);
+
+	param->u.crypt.err = 0;
+	param->u.crypt.alg[IEEE_CRYPT_ALG_NAME_LEN - 1] = '\0';
+
+	if (is_broadcast_mac_addr(param->sta_addr)) {
+		if (param->u.crypt.idx >= WEP_KEYS
+			#ifdef CONFIG_IEEE80211W
+			&& param->u.crypt.idx > BIP_MAX_KEYID
+			#endif
+		) {
+			ret = -EINVAL;
+			goto exit;
+		}
+	} else {
+		psta = rtw_get_stainfo(pstapriv, param->sta_addr);
+		if (!psta) {
+			ret = -EINVAL;
+			RTW_INFO(FUNC_ADPT_FMT", sta "MAC_FMT" not found\n"
+				, FUNC_ADPT_ARG(padapter), MAC_ARG(param->sta_addr));
+			goto exit;
+		}
+	}
+
+	if (strcmp(param->u.crypt.alg, "none") == 0 && (psta == NULL)) {
+		/* todo:clear default encryption keys */
+
+		RTW_INFO("clear default encryption keys, keyid=%d\n", param->u.crypt.idx);
+
+		goto exit;
+	}
+
+
+	if (strcmp(param->u.crypt.alg, "WEP") == 0 && (psta == NULL)) {
+		RTW_INFO("r871x_set_encryption, crypt.alg = WEP\n");
+
+		wep_key_idx = param->u.crypt.idx;
+		wep_key_len = param->u.crypt.key_len;
+
+		RTW_INFO("r871x_set_encryption, wep_key_idx=%d, len=%d\n", wep_key_idx, wep_key_len);
+
+		if ((wep_key_idx >= WEP_KEYS) || (wep_key_len <= 0)) {
+			ret = -EINVAL;
+			goto exit;
+		}
+
+		if (wep_key_len > 0)
+			wep_key_len = wep_key_len <= 5 ? 5 : 13;
+
+		if (psecuritypriv->bWepDefaultKeyIdxSet == 0) {
+			/* wep default key has not been set, so use this key index as default key. */
+
+			psecuritypriv->dot11AuthAlgrthm = dot11AuthAlgrthm_Auto;
+			psecuritypriv->ndisencryptstatus = Ndis802_11Encryption1Enabled;
+			psecuritypriv->dot11PrivacyAlgrthm = _WEP40_;
+			psecuritypriv->dot118021XGrpPrivacy = _WEP40_;
+
+			if (wep_key_len == 13) {
+				psecuritypriv->dot11PrivacyAlgrthm = _WEP104_;
+				psecuritypriv->dot118021XGrpPrivacy = _WEP104_;
+			}
+
+			psecuritypriv->dot11PrivacyKeyIndex = wep_key_idx;
+		}
+
+		_rtw_memcpy(&(psecuritypriv->dot11DefKey[wep_key_idx].skey[0]), param->u.crypt.key, wep_key_len);
+
+		psecuritypriv->dot11DefKeylen[wep_key_idx] = wep_key_len;
+
+		rtw_ap_set_wep_key(padapter, param->u.crypt.key, wep_key_len, wep_key_idx, 1);
+
+		goto exit;
+
+	}
+
+	if (!psta) { /* group key */
+		if (param->u.crypt.set_tx == 0) { /* group key, TX only */
+			if (strcmp(param->u.crypt.alg, "WEP") == 0) {
+				RTW_INFO(FUNC_ADPT_FMT" set WEP TX GTK idx:%u, len:%u\n"
+					, FUNC_ADPT_ARG(padapter), param->u.crypt.idx, param->u.crypt.key_len);
+				_rtw_memcpy(psecuritypriv->dot118021XGrpKey[param->u.crypt.idx].skey,  param->u.crypt.key, (param->u.crypt.key_len > 16 ? 16 : param->u.crypt.key_len));
+				psecuritypriv->dot118021XGrpPrivacy = _WEP40_;
+				if (param->u.crypt.key_len == 13)
+					psecuritypriv->dot118021XGrpPrivacy = _WEP104_;
+
+			} else if (strcmp(param->u.crypt.alg, "TKIP") == 0) {
+				RTW_INFO(FUNC_ADPT_FMT" set TKIP TX GTK idx:%u, len:%u\n"
+					, FUNC_ADPT_ARG(padapter), param->u.crypt.idx, param->u.crypt.key_len);
+				psecuritypriv->dot118021XGrpPrivacy = _TKIP_;
+				_rtw_memcpy(psecuritypriv->dot118021XGrpKey[param->u.crypt.idx].skey,  param->u.crypt.key, (param->u.crypt.key_len > 16 ? 16 : param->u.crypt.key_len));
+				/* set mic key */
+				_rtw_memcpy(psecuritypriv->dot118021XGrptxmickey[param->u.crypt.idx].skey, &(param->u.crypt.key[16]), 8);
+				_rtw_memcpy(psecuritypriv->dot118021XGrprxmickey[param->u.crypt.idx].skey, &(param->u.crypt.key[24]), 8);
+				psecuritypriv->busetkipkey = _TRUE;
+
+			} else if (strcmp(param->u.crypt.alg, "CCMP") == 0) {
+				RTW_INFO(FUNC_ADPT_FMT" set CCMP TX GTK idx:%u, len:%u\n"
+					, FUNC_ADPT_ARG(padapter), param->u.crypt.idx, param->u.crypt.key_len);
+				psecuritypriv->dot118021XGrpPrivacy = _AES_;
+				_rtw_memcpy(psecuritypriv->dot118021XGrpKey[param->u.crypt.idx].skey,  param->u.crypt.key, (param->u.crypt.key_len > 16 ? 16 : param->u.crypt.key_len));
+
+			#ifdef CONFIG_IEEE80211W
+			} else if (strcmp(param->u.crypt.alg, "BIP") == 0) {
+				RTW_INFO(FUNC_ADPT_FMT" set TX IGTK idx:%u, len:%u\n"
+					, FUNC_ADPT_ARG(padapter), param->u.crypt.idx, param->u.crypt.key_len);
+				_rtw_memcpy(padapter->securitypriv.dot11wBIPKey[param->u.crypt.idx].skey, param->u.crypt.key, (param->u.crypt.key_len > 16 ? 16 : param->u.crypt.key_len));
+				padapter->securitypriv.dot11wBIPKeyid = param->u.crypt.idx;
+				psecuritypriv->dot11wBIPtxpn.val = RTW_GET_LE64(param->u.crypt.seq);
+				padapter->securitypriv.binstallBIPkey = _TRUE;
+				goto exit;
+			#endif /* CONFIG_IEEE80211W */
+
+			} else if (strcmp(param->u.crypt.alg, "none") == 0) {
+				RTW_INFO(FUNC_ADPT_FMT" clear group key, idx:%u\n"
+					, FUNC_ADPT_ARG(padapter), param->u.crypt.idx);
+				psecuritypriv->dot118021XGrpPrivacy = _NO_PRIVACY_;
+			} else {
+				RTW_WARN(FUNC_ADPT_FMT" set group key, not support\n"
+					, FUNC_ADPT_ARG(padapter));
+				goto exit;
+			}
+
+			psecuritypriv->dot118021XGrpKeyid = param->u.crypt.idx;
+			pbcmc_sta = rtw_get_bcmc_stainfo(padapter);
+			if (pbcmc_sta) {
+				pbcmc_sta->dot11txpn.val = RTW_GET_LE64(param->u.crypt.seq);
+				pbcmc_sta->ieee8021x_blocked = _FALSE;
+				pbcmc_sta->dot118021XPrivacy = psecuritypriv->dot118021XGrpPrivacy; /* rx will use bmc_sta's dot118021XPrivacy			 */
+			}
+			psecuritypriv->binstallGrpkey = _TRUE;
+			psecuritypriv->dot11PrivacyAlgrthm = psecuritypriv->dot118021XGrpPrivacy;/* !!! */
+
+			rtw_ap_set_group_key(padapter, param->u.crypt.key, psecuritypriv->dot118021XGrpPrivacy, param->u.crypt.idx);
+		}
+
+		goto exit;
+
+	}
+
+	if (psecuritypriv->dot11AuthAlgrthm == dot11AuthAlgrthm_8021X && psta) { /* psk/802_1x */
+		if (param->u.crypt.set_tx == 1) {
+			/* pairwise key */
+			_rtw_memcpy(psta->dot118021x_UncstKey.skey,  param->u.crypt.key, (param->u.crypt.key_len > 16 ? 16 : param->u.crypt.key_len));
+
+			if (strcmp(param->u.crypt.alg, "WEP") == 0) {
+				RTW_INFO(FUNC_ADPT_FMT" set WEP PTK of "MAC_FMT" idx:%u, len:%u\n"
+					, FUNC_ADPT_ARG(padapter), MAC_ARG(psta->cmn.mac_addr)
+					, param->u.crypt.idx, param->u.crypt.key_len);
+				psta->dot118021XPrivacy = _WEP40_;
+				if (param->u.crypt.key_len == 13)
+					psta->dot118021XPrivacy = _WEP104_;
+
+			} else if (strcmp(param->u.crypt.alg, "TKIP") == 0) {
+				RTW_INFO(FUNC_ADPT_FMT" set TKIP PTK of "MAC_FMT" idx:%u, len:%u\n"
+					, FUNC_ADPT_ARG(padapter), MAC_ARG(psta->cmn.mac_addr)
+					, param->u.crypt.idx, param->u.crypt.key_len);
+				psta->dot118021XPrivacy = _TKIP_;
+				/* set mic key */
+				_rtw_memcpy(psta->dot11tkiptxmickey.skey, &(param->u.crypt.key[16]), 8);
+				_rtw_memcpy(psta->dot11tkiprxmickey.skey, &(param->u.crypt.key[24]), 8);
+				psecuritypriv->busetkipkey = _TRUE;
+
+			} else if (strcmp(param->u.crypt.alg, "CCMP") == 0) {
+				RTW_INFO(FUNC_ADPT_FMT" set CCMP PTK of "MAC_FMT" idx:%u, len:%u\n"
+					, FUNC_ADPT_ARG(padapter), MAC_ARG(psta->cmn.mac_addr)
+					, param->u.crypt.idx, param->u.crypt.key_len);
+				psta->dot118021XPrivacy = _AES_;
+
+			} else if (strcmp(param->u.crypt.alg, "none") == 0) {
+				RTW_INFO(FUNC_ADPT_FMT" clear pairwise key of "MAC_FMT" idx:%u\n"
+					, FUNC_ADPT_ARG(padapter), MAC_ARG(psta->cmn.mac_addr)
+					, param->u.crypt.idx);
+				psta->dot118021XPrivacy = _NO_PRIVACY_;
+			} else {
+				RTW_WARN(FUNC_ADPT_FMT" set pairwise key of "MAC_FMT", not support\n"
+					, FUNC_ADPT_ARG(padapter), MAC_ARG(psta->cmn.mac_addr));
+				goto exit;
+			}
+
+			psta->dot11txpn.val = RTW_GET_LE64(param->u.crypt.seq);
+			psta->dot11rxpn.val = RTW_GET_LE64(param->u.crypt.seq);
+			psta->ieee8021x_blocked = _FALSE;
+
+			if (psta->dot118021XPrivacy != _NO_PRIVACY_) {
+				psta->bpairwise_key_installed = _TRUE;
+
+				/* WPA2 key-handshake has completed */
+				if (psecuritypriv->ndisauthtype == Ndis802_11AuthModeWPA2PSK)
+					psta->state &= (~WIFI_UNDER_KEY_HANDSHAKE);
+			}
+
+			rtw_ap_set_pairwise_key(padapter, psta);
+		} else {
+			/* peer's group key, RX only */
+			#ifdef CONFIG_RTW_MESH
+			if (strcmp(param->u.crypt.alg, "CCMP") == 0) {
+				RTW_INFO(FUNC_ADPT_FMT" set CCMP GTK of "MAC_FMT", idx:%u, len:%u\n"
+					, FUNC_ADPT_ARG(padapter), MAC_ARG(psta->cmn.mac_addr)
+					, param->u.crypt.idx, param->u.crypt.key_len);
+				psta->group_privacy = _AES_;
+				_rtw_memcpy(psta->gtk.skey, param->u.crypt.key, (param->u.crypt.key_len > 16 ? 16 : param->u.crypt.key_len));
+				psta->gtk_bmp |= BIT(param->u.crypt.idx);
+				psta->gtk_pn.val = RTW_GET_LE64(param->u.crypt.seq);
+
+			#ifdef CONFIG_IEEE80211W
+			} else if (strcmp(param->u.crypt.alg, "BIP") == 0) {
+				RTW_INFO(FUNC_ADPT_FMT" set IGTK of "MAC_FMT", idx:%u, len:%u\n"
+					, FUNC_ADPT_ARG(padapter), MAC_ARG(psta->cmn.mac_addr)
+					, param->u.crypt.idx, param->u.crypt.key_len);
+				_rtw_memcpy(psta->igtk.skey, param->u.crypt.key, (param->u.crypt.key_len > 16 ? 16 : param->u.crypt.key_len));
+				psta->igtk_bmp |= BIT(param->u.crypt.idx);
+				psta->igtk_id = param->u.crypt.idx;
+				psta->igtk_pn.val = RTW_GET_LE64(param->u.crypt.seq);
+				goto exit;
+			#endif /* CONFIG_IEEE80211W */
+
+			} else if (strcmp(param->u.crypt.alg, "none") == 0) {
+				RTW_INFO(FUNC_ADPT_FMT" clear group key of "MAC_FMT", idx:%u\n"
+					, FUNC_ADPT_ARG(padapter), MAC_ARG(psta->cmn.mac_addr)
+					, param->u.crypt.idx);
+				psta->group_privacy = _NO_PRIVACY_;
+				psta->gtk_bmp &= ~BIT(param->u.crypt.idx);
+			} else
+			#endif /* CONFIG_RTW_MESH */
+			{
+				RTW_WARN(FUNC_ADPT_FMT" set group key of "MAC_FMT", not support\n"
+					, FUNC_ADPT_ARG(padapter), MAC_ARG(psta->cmn.mac_addr));
+				goto exit;
+			}
+
+			#ifdef CONFIG_RTW_MESH
+			rtw_ap_set_sta_key(padapter, psta->cmn.mac_addr, psta->group_privacy
+				, param->u.crypt.key, param->u.crypt.idx, 1);
+			#endif
+		}
+
+	}
+
+exit:
+	return ret;
+}
+#endif /* CONFIG_AP_MODE */
+
+static int rtw_cfg80211_set_encryption(struct net_device *dev, struct ieee_param *param)
+{
+	int ret = 0;
+	u32 wep_key_idx, wep_key_len;
+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
+	struct mlme_priv	*pmlmepriv = &padapter->mlmepriv;
+	struct security_priv *psecuritypriv = &padapter->securitypriv;
+#ifdef CONFIG_P2P
+	struct wifidirect_info *pwdinfo = &padapter->wdinfo;
+#endif /* CONFIG_P2P */
+
+	RTW_INFO("%s\n", __func__);
+
+	param->u.crypt.err = 0;
+	param->u.crypt.alg[IEEE_CRYPT_ALG_NAME_LEN - 1] = '\0';
+
+	if (is_broadcast_mac_addr(param->sta_addr)) {
+		if (param->u.crypt.idx >= WEP_KEYS
+			#ifdef CONFIG_IEEE80211W
+			&& param->u.crypt.idx > BIP_MAX_KEYID
+			#endif
+		) {
+			ret = -EINVAL;
+			goto exit;
+		}
+	} else {
+#ifdef CONFIG_WAPI_SUPPORT
+		if (strcmp(param->u.crypt.alg, "SMS4"))
+#endif
+		{
+			ret = -EINVAL;
+			goto exit;
+		}
+	}
+
+	if (strcmp(param->u.crypt.alg, "WEP") == 0) {
+		RTW_INFO("wpa_set_encryption, crypt.alg = WEP\n");
+
+		wep_key_idx = param->u.crypt.idx;
+		wep_key_len = param->u.crypt.key_len;
+
+		if ((wep_key_idx >= WEP_KEYS) || (wep_key_len <= 0)) {
+			ret = -EINVAL;
+			goto exit;
+		}
+
+		if (psecuritypriv->bWepDefaultKeyIdxSet == 0) {
+			/* wep default key has not been set, so use this key index as default key. */
+
+			wep_key_len = wep_key_len <= 5 ? 5 : 13;
+
+			psecuritypriv->ndisencryptstatus = Ndis802_11Encryption1Enabled;
+			psecuritypriv->dot11PrivacyAlgrthm = _WEP40_;
+			psecuritypriv->dot118021XGrpPrivacy = _WEP40_;
+
+			if (wep_key_len == 13) {
+				psecuritypriv->dot11PrivacyAlgrthm = _WEP104_;
+				psecuritypriv->dot118021XGrpPrivacy = _WEP104_;
+			}
+
+			psecuritypriv->dot11PrivacyKeyIndex = wep_key_idx;
+		}
+
+		_rtw_memcpy(&(psecuritypriv->dot11DefKey[wep_key_idx].skey[0]), param->u.crypt.key, wep_key_len);
+
+		psecuritypriv->dot11DefKeylen[wep_key_idx] = wep_key_len;
+
+		rtw_set_key(padapter, psecuritypriv, wep_key_idx, 0, _TRUE);
+
+		goto exit;
+	}
+
+	if (padapter->securitypriv.dot11AuthAlgrthm == dot11AuthAlgrthm_8021X) { /* 802_1x */
+		struct sta_info *psta, *pbcmc_sta;
+		struct sta_priv *pstapriv = &padapter->stapriv;
+
+		/* RTW_INFO("%s, : dot11AuthAlgrthm == dot11AuthAlgrthm_8021X\n", __func__); */
+
+		if (check_fwstate(pmlmepriv, WIFI_STATION_STATE | WIFI_MP_STATE) == _TRUE) { /* sta mode */
+#ifdef CONFIG_RTW_80211R
+			if (rtw_ft_roam(padapter))
+				psta = rtw_get_stainfo(pstapriv, pmlmepriv->assoc_bssid);
+			else
+#endif
+				psta = rtw_get_stainfo(pstapriv, get_bssid(pmlmepriv));
+			if (psta == NULL) {
+				/* DEBUG_ERR( ("Set wpa_set_encryption: Obtain Sta_info fail\n")); */
+				RTW_INFO("%s, : Obtain Sta_info fail\n", __func__);
+			} else {
+				/* Jeff: don't disable ieee8021x_blocked while clearing key */
+				if (strcmp(param->u.crypt.alg, "none") != 0)
+					psta->ieee8021x_blocked = _FALSE;
+
+				if ((padapter->securitypriv.ndisencryptstatus == Ndis802_11Encryption2Enabled) ||
+				    (padapter->securitypriv.ndisencryptstatus ==  Ndis802_11Encryption3Enabled))
+					psta->dot118021XPrivacy = padapter->securitypriv.dot11PrivacyAlgrthm;
+
+				if (param->u.crypt.set_tx == 1) { /* pairwise key */
+					RTW_INFO(FUNC_ADPT_FMT" set %s PTK idx:%u, len:%u\n"
+						, FUNC_ADPT_ARG(padapter), param->u.crypt.alg, param->u.crypt.idx, param->u.crypt.key_len);
+					_rtw_memcpy(psta->dot118021x_UncstKey.skey,  param->u.crypt.key, (param->u.crypt.key_len > 16 ? 16 : param->u.crypt.key_len));
+					if (strcmp(param->u.crypt.alg, "TKIP") == 0) { /* set mic key */
+						_rtw_memcpy(psta->dot11tkiptxmickey.skey, &(param->u.crypt.key[16]), 8);
+						_rtw_memcpy(psta->dot11tkiprxmickey.skey, &(param->u.crypt.key[24]), 8);
+						padapter->securitypriv.busetkipkey = _FALSE;
+					}
+					psta->dot11txpn.val = RTW_GET_LE64(param->u.crypt.seq);
+					psta->dot11rxpn.val = RTW_GET_LE64(param->u.crypt.seq);
+					psta->bpairwise_key_installed = _TRUE;
+					#ifdef CONFIG_RTW_80211R
+					psta->ft_pairwise_key_installed = _TRUE;
+					#endif
+					rtw_setstakey_cmd(padapter, psta, UNICAST_KEY, _TRUE);
+
+				} else { /* group key */
+					if (strcmp(param->u.crypt.alg, "TKIP") == 0 || strcmp(param->u.crypt.alg, "CCMP") == 0) {
+						RTW_INFO(FUNC_ADPT_FMT" set %s GTK idx:%u, len:%u\n"
+							, FUNC_ADPT_ARG(padapter), param->u.crypt.alg, param->u.crypt.idx, param->u.crypt.key_len);
+						_rtw_memcpy(padapter->securitypriv.dot118021XGrpKey[param->u.crypt.idx].skey,  param->u.crypt.key,
+							(param->u.crypt.key_len > 16 ? 16 : param->u.crypt.key_len));
+						_rtw_memcpy(padapter->securitypriv.dot118021XGrptxmickey[param->u.crypt.idx].skey, &(param->u.crypt.key[16]), 8);
+						_rtw_memcpy(padapter->securitypriv.dot118021XGrprxmickey[param->u.crypt.idx].skey, &(param->u.crypt.key[24]), 8);
+						padapter->securitypriv.binstallGrpkey = _TRUE;
+						if (param->u.crypt.idx < 4) 
+							_rtw_memcpy(padapter->securitypriv.iv_seq[param->u.crypt.idx], param->u.crypt.seq, 8);							
+						padapter->securitypriv.dot118021XGrpKeyid = param->u.crypt.idx;
+						rtw_set_key(padapter, &padapter->securitypriv, param->u.crypt.idx, 1, _TRUE);
+
+					#ifdef CONFIG_IEEE80211W
+					} else if (strcmp(param->u.crypt.alg, "BIP") == 0) {
+						RTW_INFO(FUNC_ADPT_FMT" set IGTK idx:%u, len:%u\n"
+							, FUNC_ADPT_ARG(padapter), param->u.crypt.idx, param->u.crypt.key_len);
+						_rtw_memcpy(padapter->securitypriv.dot11wBIPKey[param->u.crypt.idx].skey,  param->u.crypt.key,
+							(param->u.crypt.key_len > 16 ? 16 : param->u.crypt.key_len));
+						psecuritypriv->dot11wBIPKeyid = param->u.crypt.idx;
+						psecuritypriv->dot11wBIPrxpn.val = RTW_GET_LE64(param->u.crypt.seq);
+						psecuritypriv->binstallBIPkey = _TRUE;
+					#endif /* CONFIG_IEEE80211W */
+
+					}
+
+#ifdef CONFIG_P2P
+					if (pwdinfo->driver_interface == DRIVER_CFG80211) {
+						if (rtw_p2p_chk_state(pwdinfo, P2P_STATE_PROVISIONING_ING))
+							rtw_p2p_set_state(pwdinfo, P2P_STATE_PROVISIONING_DONE);
+					}
+#endif /* CONFIG_P2P */
+
+					/* WPA/WPA2 key-handshake has completed */
+					clr_fwstate(pmlmepriv, WIFI_UNDER_KEY_HANDSHAKE);
+
+				}
+			}
+
+			pbcmc_sta = rtw_get_bcmc_stainfo(padapter);
+			if (pbcmc_sta == NULL) {
+				/* DEBUG_ERR( ("Set OID_802_11_ADD_KEY: bcmc stainfo is null\n")); */
+			} else {
+				/* Jeff: don't disable ieee8021x_blocked while clearing key */
+				if (strcmp(param->u.crypt.alg, "none") != 0)
+					pbcmc_sta->ieee8021x_blocked = _FALSE;
+
+				if ((padapter->securitypriv.ndisencryptstatus == Ndis802_11Encryption2Enabled) ||
+				    (padapter->securitypriv.ndisencryptstatus ==  Ndis802_11Encryption3Enabled))
+					pbcmc_sta->dot118021XPrivacy = padapter->securitypriv.dot11PrivacyAlgrthm;
+			}
+		} else if (check_fwstate(pmlmepriv, WIFI_ADHOC_STATE)) { /* adhoc mode */
+		}
+	}
+
+	#ifdef CONFIG_WAPI_SUPPORT
+	if (strcmp(param->u.crypt.alg, "SMS4") == 0)
+		rtw_wapi_set_set_encryption(padapter, param);
+	#endif
+
+exit:
+
+	RTW_INFO("%s, ret=%d\n", __func__, ret);
+
+
+	return ret;
+}
+
+static int cfg80211_rtw_add_key(struct wiphy *wiphy, struct net_device *ndev
+	, u8 key_index
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) || defined(COMPAT_KERNEL_RELEASE)
+	, bool pairwise
+#endif
+	, const u8 *mac_addr, struct key_params *params)
+{
+	char *alg_name;
+	u32 param_len;
+	struct ieee_param *param = NULL;
+	int ret = 0;
+	_adapter *padapter = (_adapter *)rtw_netdev_priv(ndev);
+	struct wireless_dev *rtw_wdev = padapter->rtw_wdev;
+	struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
+#ifdef CONFIG_TDLS
+	struct sta_info *ptdls_sta;
+#endif /* CONFIG_TDLS */
+
+	if (mac_addr)
+		RTW_INFO(FUNC_NDEV_FMT" adding key for %pM\n", FUNC_NDEV_ARG(ndev), mac_addr);
+	RTW_INFO(FUNC_NDEV_FMT" cipher=0x%x\n", FUNC_NDEV_ARG(ndev), params->cipher);
+	RTW_INFO(FUNC_NDEV_FMT" key_len=%d, key_index=%d\n", FUNC_NDEV_ARG(ndev), params->key_len, key_index);
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) || defined(COMPAT_KERNEL_RELEASE)
+	RTW_INFO(FUNC_NDEV_FMT" pairwise=%d\n", FUNC_NDEV_ARG(ndev), pairwise);
+#endif
+
+	if (rtw_cfg80211_sync_iftype(padapter) != _SUCCESS) {
+		ret = -ENOTSUPP;
+		goto addkey_end;
+	}
+
+	param_len = sizeof(struct ieee_param) + params->key_len;
+	param = rtw_malloc(param_len);
+	if (param == NULL)
+		return -1;
+
+	_rtw_memset(param, 0, param_len);
+
+	param->cmd = IEEE_CMD_SET_ENCRYPTION;
+	_rtw_memset(param->sta_addr, 0xff, ETH_ALEN);
+
+	switch (params->cipher) {
+	case IW_AUTH_CIPHER_NONE:
+		/* todo: remove key */
+		/* remove = 1;	 */
+		alg_name = "none";
+		break;
+	case WLAN_CIPHER_SUITE_WEP40:
+	case WLAN_CIPHER_SUITE_WEP104:
+		alg_name = "WEP";
+		break;
+	case WLAN_CIPHER_SUITE_TKIP:
+		alg_name = "TKIP";
+		break;
+	case WLAN_CIPHER_SUITE_CCMP:
+		alg_name = "CCMP";
+		break;
+#ifdef CONFIG_IEEE80211W
+	case WLAN_CIPHER_SUITE_AES_CMAC:
+		alg_name = "BIP";
+		break;
+#endif /* CONFIG_IEEE80211W */
+#ifdef CONFIG_WAPI_SUPPORT
+	case WLAN_CIPHER_SUITE_SMS4:
+		alg_name = "SMS4";
+		if (pairwise == NL80211_KEYTYPE_PAIRWISE) {
+			if (key_index != 0 && key_index != 1) {
+				ret = -ENOTSUPP;
+				goto addkey_end;
+			}
+			_rtw_memcpy((void *)param->sta_addr, (void *)mac_addr, ETH_ALEN);
+		} else
+			RTW_INFO("mac_addr is null\n");
+		RTW_INFO("rtw_wx_set_enc_ext: SMS4 case\n");
+		break;
+#endif
+
+	default:
+		ret = -ENOTSUPP;
+		goto addkey_end;
+	}
+
+	strncpy((char *)param->u.crypt.alg, alg_name, IEEE_CRYPT_ALG_NAME_LEN);
+
+
+	if (!mac_addr || is_broadcast_ether_addr(mac_addr)
+		#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) || defined(COMPAT_KERNEL_RELEASE)
+		|| !pairwise
+		#endif
+	) {
+		param->u.crypt.set_tx = 0; /* for wpa/wpa2 group key */
+	} else {
+		param->u.crypt.set_tx = 1; /* for wpa/wpa2 pairwise key */
+	}
+
+	param->u.crypt.idx = key_index;
+
+	if (params->seq_len && params->seq) {
+		_rtw_memcpy(param->u.crypt.seq, (u8 *)params->seq, params->seq_len);
+		RTW_INFO(FUNC_NDEV_FMT" seq_len:%u, seq:0x%llx\n", FUNC_NDEV_ARG(ndev)
+			, params->seq_len, RTW_GET_LE64(param->u.crypt.seq));
+	}
+
+	if (params->key_len && params->key) {
+		param->u.crypt.key_len = params->key_len;
+		_rtw_memcpy(param->u.crypt.key, (u8 *)params->key, params->key_len);
+	}
+
+	if (check_fwstate(pmlmepriv, WIFI_STATION_STATE) == _TRUE) {
+#ifdef CONFIG_TDLS
+		if (rtw_tdls_is_driver_setup(padapter) == _FALSE && mac_addr) {
+			ptdls_sta = rtw_get_stainfo(&padapter->stapriv, (void *)mac_addr);
+			if (ptdls_sta != NULL && ptdls_sta->tdls_sta_state) {
+				_rtw_memcpy(ptdls_sta->tpk.tk, params->key, params->key_len);
+				rtw_tdls_set_key(padapter, ptdls_sta);
+				goto addkey_end;
+			}
+		}
+#endif /* CONFIG_TDLS */
+		ret = rtw_cfg80211_set_encryption(ndev, param);
+	} else if (MLME_IS_AP(padapter) || MLME_IS_MESH(padapter)) {
+#ifdef CONFIG_AP_MODE
+		if (mac_addr)
+			_rtw_memcpy(param->sta_addr, (void *)mac_addr, ETH_ALEN);
+
+		ret = rtw_cfg80211_ap_set_encryption(ndev, param);
+#endif
+	} else if (check_fwstate(pmlmepriv, WIFI_ADHOC_STATE) == _TRUE
+		|| check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE) == _TRUE
+	) {
+		/* RTW_INFO("@@@@@@@@@@ fw_state=0x%x, iftype=%d\n", pmlmepriv->fw_state, rtw_wdev->iftype); */
+		ret = rtw_cfg80211_set_encryption(ndev, param);
+	} else
+		RTW_INFO("error! fw_state=0x%x, iftype=%d\n", pmlmepriv->fw_state, rtw_wdev->iftype);
+
+
+addkey_end:
+	if (param)
+		rtw_mfree(param, param_len);
+
+	return ret;
+
+}
+
+static int cfg80211_rtw_get_key(struct wiphy *wiphy, struct net_device *ndev
+	, u8 keyid
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) || defined(COMPAT_KERNEL_RELEASE)
+	, bool pairwise
+#endif
+	, const u8 *mac_addr, void *cookie
+	, void (*callback)(void *cookie, struct key_params *))
+{
+#define GET_KEY_PARAM_FMT_S " keyid=%d"
+#define GET_KEY_PARAM_ARG_S , keyid
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) || defined(COMPAT_KERNEL_RELEASE)
+	#define GET_KEY_PARAM_FMT_2_6_37 ", pairwise=%d"
+	#define GET_KEY_PARAM_ARG_2_6_37 , pairwise
+#else
+	#define GET_KEY_PARAM_FMT_2_6_37 ""
+	#define GET_KEY_PARAM_ARG_2_6_37
+#endif
+#define GET_KEY_PARAM_FMT_E ", addr=%pM"
+#define GET_KEY_PARAM_ARG_E , mac_addr
+
+	_adapter *adapter = (_adapter *)rtw_netdev_priv(ndev);
+	struct security_priv *sec = &adapter->securitypriv;
+	struct sta_priv *stapriv = &adapter->stapriv;
+	struct sta_info *sta = NULL;
+	u32 cipher = _NO_PRIVACY_;
+	union Keytype *key = NULL;
+	u8 key_len = 0;
+	u64 *pn = NULL;
+	u8 pn_len = 0;
+	u8 pn_val[8] = {0};
+
+	struct key_params params;
+	int ret = -ENOENT;
+
+	if (keyid >= WEP_KEYS
+		#ifdef CONFIG_IEEE80211W
+		&& keyid > BIP_MAX_KEYID
+		#endif
+	)
+		goto exit;
+
+	if (!mac_addr || is_broadcast_ether_addr(mac_addr)
+		#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) || defined(COMPAT_KERNEL_RELEASE)
+		|| (MLME_IS_STA(adapter) && !pairwise)
+		#endif
+	) {	
+		/* WEP key, TX GTK/IGTK, RX GTK/IGTK(for STA mode) */
+		if (is_wep_enc(sec->dot118021XGrpPrivacy)) {
+			if (keyid >= WEP_KEYS)
+				goto exit;
+			if (!(sec->key_mask & BIT(keyid)))
+				goto exit;
+			cipher = sec->dot118021XGrpPrivacy;
+			key = &sec->dot11DefKey[keyid];
+		} else {
+			if (keyid < WEP_KEYS) {
+				if (sec->binstallGrpkey != _TRUE)
+					goto exit;
+				cipher = sec->dot118021XGrpPrivacy;
+				key = &sec->dot118021XGrpKey[keyid];
+				sta = rtw_get_bcmc_stainfo(adapter);
+				if (sta)
+					pn = &sta->dot11txpn.val;
+			#ifdef CONFIG_IEEE80211W
+			} else if (keyid < BIP_MAX_KEYID) {
+				if (SEC_IS_BIP_KEY_INSTALLED(sec) != _TRUE)
+					goto exit;
+				cipher = _BIP_;
+				key = &sec->dot11wBIPKey[keyid];
+				pn = &sec->dot11wBIPtxpn.val;
+			#endif
+			}
+		}
+	} else {
+		/* Pairwise key, RX GTK/IGTK for specific peer */
+		sta = rtw_get_stainfo(stapriv, mac_addr);
+		if (!sta)
+			goto exit;
+
+		if (keyid < WEP_KEYS && pairwise) {
+			if (sta->bpairwise_key_installed != _TRUE)
+				goto exit;
+			cipher = sta->dot118021XPrivacy;
+			key = &sta->dot118021x_UncstKey;
+		#ifdef CONFIG_RTW_MESH
+		} else if (keyid < WEP_KEYS && !pairwise) {
+			if (!(sta->gtk_bmp & BIT(keyid)))
+				goto exit;
+			cipher = sta->group_privacy;
+			key = &sta->gtk;
+		#ifdef CONFIG_IEEE80211W
+		} else if (keyid < BIP_MAX_KEYID && !pairwise) {
+			if (!(sta->igtk_bmp & BIT(keyid)))
+				goto exit;
+			cipher = _BIP_;
+			key = &sta->igtk;
+			pn = &sta->igtk_pn.val;
+		#endif
+		#endif /* CONFIG_RTW_MESH */
+		}
+	}
+
+	if (!key)
+		goto exit;
+
+	if (cipher == _WEP40_) {
+		cipher = WLAN_CIPHER_SUITE_WEP40;
+		key_len = sec->dot11DefKeylen[keyid];
+	} else if (cipher == _WEP104_) {
+		cipher = WLAN_CIPHER_SUITE_WEP104;
+		key_len = sec->dot11DefKeylen[keyid];
+	} else if (cipher == _TKIP_) {
+		cipher = WLAN_CIPHER_SUITE_TKIP;
+		key_len = 16;
+	} else if (cipher == _AES_) {
+		cipher = WLAN_CIPHER_SUITE_CCMP;
+		key_len = 16;
+	#ifdef CONFIG_IEEE80211W
+	} else if (cipher == _BIP_) {
+		cipher = WLAN_CIPHER_SUITE_AES_CMAC;
+		key_len = 16;
+	#endif
+	} else {
+		RTW_WARN(FUNC_NDEV_FMT" unknown cipher:%u\n", FUNC_NDEV_ARG(ndev), cipher);
+		rtw_warn_on(1);
+		goto exit;
+	}
+
+	if (pn) {
+		*((u64 *)pn_val) = cpu_to_le64(*pn);
+		pn_len = 6;
+	}
+
+	ret = 0;
+	
+exit:
+	RTW_INFO(FUNC_NDEV_FMT
+		GET_KEY_PARAM_FMT_S
+		GET_KEY_PARAM_FMT_2_6_37
+		GET_KEY_PARAM_FMT_E
+		" ret %d\n", FUNC_NDEV_ARG(ndev)
+		GET_KEY_PARAM_ARG_S
+		GET_KEY_PARAM_ARG_2_6_37
+		GET_KEY_PARAM_ARG_E
+		, ret);
+	if (pn)
+		RTW_INFO(FUNC_NDEV_FMT " seq:0x%llx\n", FUNC_NDEV_ARG(ndev), *pn);
+
+	if (ret == 0) {
+		_rtw_memset(&params, 0, sizeof(params));
+
+		params.cipher = cipher;
+		params.key = key->skey;
+		params.key_len = key_len;
+		if (pn) {
+			params.seq = pn_val;
+			params.seq_len = pn_len;
+		}
+
+		callback(cookie, &params);
+	}
+
+	return ret;
+}
+
+static int cfg80211_rtw_del_key(struct wiphy *wiphy, struct net_device *ndev,
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) || defined(COMPAT_KERNEL_RELEASE)
+				u8 key_index, bool pairwise, const u8 *mac_addr)
+#else	/* (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) */
+				u8 key_index, const u8 *mac_addr)
+#endif /* (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) */
+{
+	_adapter *padapter = (_adapter *)rtw_netdev_priv(ndev);
+	struct security_priv *psecuritypriv = &padapter->securitypriv;
+
+	RTW_INFO(FUNC_NDEV_FMT" key_index=%d, addr=%pM\n", FUNC_NDEV_ARG(ndev), key_index, mac_addr);
+
+	if (key_index == psecuritypriv->dot11PrivacyKeyIndex) {
+		/* clear the flag of wep default key set. */
+		psecuritypriv->bWepDefaultKeyIdxSet = 0;
+	}
+
+	return 0;
+}
+
+static int cfg80211_rtw_set_default_key(struct wiphy *wiphy,
+	struct net_device *ndev, u8 key_index
+	#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 38)) || defined(COMPAT_KERNEL_RELEASE)
+	, bool unicast, bool multicast
+	#endif
+)
+{
+	_adapter *padapter = (_adapter *)rtw_netdev_priv(ndev);
+	struct security_priv *psecuritypriv = &padapter->securitypriv;
+
+#define SET_DEF_KEY_PARAM_FMT " key_index=%d"
+#define SET_DEF_KEY_PARAM_ARG , key_index
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 38)) || defined(COMPAT_KERNEL_RELEASE)
+	#define SET_DEF_KEY_PARAM_FMT_2_6_38 ", unicast=%d, multicast=%d"
+	#define SET_DEF_KEY_PARAM_ARG_2_6_38 , unicast, multicast
+#else
+	#define SET_DEF_KEY_PARAM_FMT_2_6_38 ""
+	#define SET_DEF_KEY_PARAM_ARG_2_6_38
+#endif
+
+	RTW_INFO(FUNC_NDEV_FMT
+		SET_DEF_KEY_PARAM_FMT
+		SET_DEF_KEY_PARAM_FMT_2_6_38
+		"\n", FUNC_NDEV_ARG(ndev)
+		SET_DEF_KEY_PARAM_ARG
+		SET_DEF_KEY_PARAM_ARG_2_6_38
+	);
+
+	if ((key_index < WEP_KEYS) && ((psecuritypriv->dot11PrivacyAlgrthm == _WEP40_) || (psecuritypriv->dot11PrivacyAlgrthm == _WEP104_))) { /* set wep default key */
+		psecuritypriv->ndisencryptstatus = Ndis802_11Encryption1Enabled;
+
+		psecuritypriv->dot11PrivacyKeyIndex = key_index;
+
+		psecuritypriv->dot11PrivacyAlgrthm = _WEP40_;
+		psecuritypriv->dot118021XGrpPrivacy = _WEP40_;
+		if (psecuritypriv->dot11DefKeylen[key_index] == 13) {
+			psecuritypriv->dot11PrivacyAlgrthm = _WEP104_;
+			psecuritypriv->dot118021XGrpPrivacy = _WEP104_;
+		}
+
+		psecuritypriv->bWepDefaultKeyIdxSet = 1; /* set the flag to represent that wep default key has been set */
+	}
+
+	return 0;
+
+}
+
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 30))
+int cfg80211_rtw_set_default_mgmt_key(struct wiphy *wiphy,
+	struct net_device *ndev, u8 key_index)
+{
+#define SET_DEF_KEY_PARAM_FMT " key_index=%d"
+#define SET_DEF_KEY_PARAM_ARG , key_index
+
+	RTW_INFO(FUNC_NDEV_FMT
+		SET_DEF_KEY_PARAM_FMT
+		"\n", FUNC_NDEV_ARG(ndev)
+		SET_DEF_KEY_PARAM_ARG
+	);
+
+	return 0;
+}
+#endif
+
+#if defined(CONFIG_GTK_OL) && (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 1, 0))
+static int cfg80211_rtw_set_rekey_data(struct wiphy *wiphy,
+	struct net_device *ndev,
+	struct cfg80211_gtk_rekey_data *data)
+{
+	/*int i;*/
+	struct sta_info *psta;
+	_adapter *padapter = (_adapter *)rtw_netdev_priv(ndev);
+	struct mlme_priv   *pmlmepriv = &padapter->mlmepriv;
+	struct sta_priv *pstapriv = &padapter->stapriv;
+	struct security_priv *psecuritypriv = &(padapter->securitypriv);
+
+	psta = rtw_get_stainfo(pstapriv, get_bssid(pmlmepriv));
+	if (psta == NULL) {
+		RTW_INFO("%s, : Obtain Sta_info fail\n", __func__);
+		return -1;
+	}
+
+	_rtw_memcpy(psta->kek, data->kek, NL80211_KEK_LEN);
+	/*printk("\ncfg80211_rtw_set_rekey_data KEK:");
+	for(i=0;i<NL80211_KEK_LEN; i++)
+		printk(" %02x ", psta->kek[i]);*/
+	_rtw_memcpy(psta->kck, data->kck, NL80211_KCK_LEN);
+	/*printk("\ncfg80211_rtw_set_rekey_data KCK:");
+	for(i=0;i<NL80211_KCK_LEN; i++)
+		printk(" %02x ", psta->kck[i]);*/
+	_rtw_memcpy(psta->replay_ctr, data->replay_ctr, NL80211_REPLAY_CTR_LEN);
+	psecuritypriv->binstallKCK_KEK = _TRUE;
+	/*printk("\nREPLAY_CTR: ");
+	for(i=0;i<RTW_REPLAY_CTR_LEN; i++)
+		printk(" %02x ", psta->replay_ctr[i]);*/
+
+	return 0;
+}
+#endif /*CONFIG_GTK_OL*/
+
+#ifdef CONFIG_RTW_MESH
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 9, 0))
+static enum nl80211_mesh_power_mode rtw_mesh_ps_to_nl80211_mesh_power_mode(u8 ps)
+{
+	if (ps == RTW_MESH_PS_UNKNOWN)
+		return NL80211_MESH_POWER_UNKNOWN;
+	if (ps == RTW_MESH_PS_ACTIVE)
+		return NL80211_MESH_POWER_ACTIVE;
+	if (ps == RTW_MESH_PS_LSLEEP)
+		return NL80211_MESH_POWER_LIGHT_SLEEP;
+	if (ps == RTW_MESH_PS_DSLEEP)
+		return NL80211_MESH_POWER_DEEP_SLEEP;
+
+	rtw_warn_on(1);
+	return NL80211_MESH_POWER_UNKNOWN;
+}
+#endif
+
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 0, 0))
+enum nl80211_plink_state rtw_plink_state_to_nl80211_plink_state(u8 plink_state)
+{
+	if (plink_state == RTW_MESH_PLINK_UNKNOWN)
+		return NUM_NL80211_PLINK_STATES;
+	if (plink_state == RTW_MESH_PLINK_LISTEN)
+		return NL80211_PLINK_LISTEN;
+	if (plink_state == RTW_MESH_PLINK_OPN_SNT)
+		return NL80211_PLINK_OPN_SNT;
+	if (plink_state == RTW_MESH_PLINK_OPN_RCVD)
+		return NL80211_PLINK_OPN_RCVD;
+	if (plink_state == RTW_MESH_PLINK_CNF_RCVD)
+		return NL80211_PLINK_CNF_RCVD;
+	if (plink_state == RTW_MESH_PLINK_ESTAB)
+		return NL80211_PLINK_ESTAB;
+	if (plink_state == RTW_MESH_PLINK_HOLDING)
+		return NL80211_PLINK_HOLDING;
+	if (plink_state == RTW_MESH_PLINK_BLOCKED)
+		return NL80211_PLINK_BLOCKED;
+
+	rtw_warn_on(1);
+	return NUM_NL80211_PLINK_STATES;
+}
+
+u8 nl80211_plink_state_to_rtw_plink_state(enum nl80211_plink_state plink_state)
+{
+	if (plink_state == NL80211_PLINK_LISTEN)
+		return RTW_MESH_PLINK_LISTEN;
+	if (plink_state == NL80211_PLINK_OPN_SNT)
+		return RTW_MESH_PLINK_OPN_SNT;
+	if (plink_state == NL80211_PLINK_OPN_RCVD)
+		return RTW_MESH_PLINK_OPN_RCVD;
+	if (plink_state == NL80211_PLINK_CNF_RCVD)
+		return RTW_MESH_PLINK_CNF_RCVD;
+	if (plink_state == NL80211_PLINK_ESTAB)
+		return RTW_MESH_PLINK_ESTAB;
+	if (plink_state == NL80211_PLINK_HOLDING)
+		return RTW_MESH_PLINK_HOLDING;
+	if (plink_state == NL80211_PLINK_BLOCKED)
+		return RTW_MESH_PLINK_BLOCKED;
+
+	rtw_warn_on(1);
+	return RTW_MESH_PLINK_UNKNOWN;
+}
+#endif
+
+static void rtw_cfg80211_fill_mesh_only_sta_info(struct mesh_plink_ent *plink, struct sta_info *sta, struct station_info *sinfo)
+{
+	sinfo->filled |= STATION_INFO_LLID;
+	sinfo->llid = plink->llid;
+	sinfo->filled |= STATION_INFO_PLID;
+	sinfo->plid = plink->plid;
+	sinfo->filled |= STATION_INFO_PLINK_STATE;
+	sinfo->plink_state = rtw_plink_state_to_nl80211_plink_state(plink->plink_state);
+	if (!sta && plink->scanned) {
+		sinfo->filled |= STATION_INFO_SIGNAL;
+		sinfo->signal = translate_percentage_to_dbm(plink->scanned->network.PhyInfo.SignalStrength);
+		sinfo->filled |= STATION_INFO_INACTIVE_TIME;
+		if (plink->plink_state == RTW_MESH_PLINK_UNKNOWN)
+			sinfo->inactive_time = 0 - 1;
+		else
+			sinfo->inactive_time = rtw_get_passing_time_ms(plink->scanned->last_scanned);
+	}
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 9, 0))
+	if (sta) {
+		sinfo->filled |= STATION_INFO_LOCAL_PM;
+		sinfo->local_pm = rtw_mesh_ps_to_nl80211_mesh_power_mode(sta->local_mps);
+		sinfo->filled |= STATION_INFO_PEER_PM;
+		sinfo->peer_pm = rtw_mesh_ps_to_nl80211_mesh_power_mode(sta->peer_mps);
+		sinfo->filled |= STATION_INFO_NONPEER_PM;
+		sinfo->nonpeer_pm = rtw_mesh_ps_to_nl80211_mesh_power_mode(sta->nonpeer_mps);
+	}
+#endif
+}
+#endif /* CONFIG_RTW_MESH */
+
+static int cfg80211_rtw_get_station(struct wiphy *wiphy,
+	struct net_device *ndev,
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 16, 0))
+	u8 *mac,
+#else
+	const u8 *mac,
+#endif
+	struct station_info *sinfo)
+{
+	int ret = 0;
+	_adapter *padapter = (_adapter *)rtw_netdev_priv(ndev);
+	struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
+	struct sta_info *psta = NULL;
+	struct sta_priv *pstapriv = &padapter->stapriv;
+#ifdef CONFIG_RTW_MESH
+	struct mesh_plink_ent *plink = NULL;
+#endif
+
+	sinfo->filled = 0;
+
+	if (!mac) {
+		RTW_INFO(FUNC_NDEV_FMT" mac==%p\n", FUNC_NDEV_ARG(ndev), mac);
+		ret = -ENOENT;
+		goto exit;
+	}
+
+	psta = rtw_get_stainfo(pstapriv, mac);
+#ifdef CONFIG_RTW_MESH
+	if (MLME_IS_MESH(padapter)) {
+		if (psta)
+			plink = psta->plink;
+		if (!plink)
+			plink = rtw_mesh_plink_get(padapter, mac);
+	}
+#endif /* CONFIG_RTW_MESH */
+
+	if ((!MLME_IS_MESH(padapter) && !psta)
+		#ifdef CONFIG_RTW_MESH
+		|| (MLME_IS_MESH(padapter) && !plink)
+		#endif
+	) {
+		RTW_INFO(FUNC_NDEV_FMT" no sta info for mac="MAC_FMT"\n"
+			, FUNC_NDEV_ARG(ndev), MAC_ARG(mac));
+		ret = -ENOENT;
+		goto exit;
+	}
+
+#ifdef CONFIG_DEBUG_CFG80211
+	RTW_INFO(FUNC_NDEV_FMT" mac="MAC_FMT"\n", FUNC_NDEV_ARG(ndev), MAC_ARG(mac));
+#endif
+
+	/* for infra./P2PClient mode */
+	if (check_fwstate(pmlmepriv, WIFI_STATION_STATE)
+		&& check_fwstate(pmlmepriv, _FW_LINKED)
+	) {
+		struct wlan_network  *cur_network = &(pmlmepriv->cur_network);
+
+		if (_rtw_memcmp((u8 *)mac, cur_network->network.MacAddress, ETH_ALEN) == _FALSE) {
+			RTW_INFO("%s, mismatch bssid="MAC_FMT"\n", __func__, MAC_ARG(cur_network->network.MacAddress));
+			ret = -ENOENT;
+			goto exit;
+		}
+
+		sinfo->filled |= STATION_INFO_SIGNAL;
+		sinfo->signal = translate_percentage_to_dbm(padapter->recvpriv.signal_strength);
+
+		sinfo->filled |= STATION_INFO_TX_BITRATE;
+		sinfo->txrate.legacy = rtw_get_cur_max_rate(padapter);
+	}
+
+	if (psta) {
+		if (check_fwstate(pmlmepriv, WIFI_STATION_STATE) == _FALSE
+			|| check_fwstate(pmlmepriv, _FW_LINKED) == _FALSE
+		) {
+			sinfo->filled |= STATION_INFO_SIGNAL;
+			sinfo->signal = translate_percentage_to_dbm(psta->cmn.rssi_stat.rssi);
+		}
+		sinfo->filled |= STATION_INFO_INACTIVE_TIME;
+		sinfo->inactive_time = rtw_get_passing_time_ms(psta->sta_stats.last_rx_time);
+		sinfo->filled |= STATION_INFO_RX_PACKETS;
+		sinfo->rx_packets = sta_rx_data_pkts(psta);
+		sinfo->filled |= STATION_INFO_TX_PACKETS;
+		sinfo->tx_packets = psta->sta_stats.tx_pkts;
+		sinfo->filled |= STATION_INFO_TX_FAILED;
+		sinfo->tx_failed = psta->sta_stats.tx_fail_cnt;
+	}
+
+#ifdef CONFIG_RTW_MESH
+	if (MLME_IS_MESH(padapter))
+		rtw_cfg80211_fill_mesh_only_sta_info(plink, psta, sinfo);
+#endif
+
+exit:
+	return ret;
+}
+
+extern int netdev_open(struct net_device *pnetdev);
+
+#if 0
+enum nl80211_iftype {
+	NL80211_IFTYPE_UNSPECIFIED,
+	NL80211_IFTYPE_ADHOC, /* 1 */
+	NL80211_IFTYPE_STATION, /* 2 */
+	NL80211_IFTYPE_AP, /* 3 */
+	NL80211_IFTYPE_AP_VLAN,
+	NL80211_IFTYPE_WDS,
+	NL80211_IFTYPE_MONITOR, /* 6 */
+	NL80211_IFTYPE_MESH_POINT,
+	NL80211_IFTYPE_P2P_CLIENT, /* 8 */
+	NL80211_IFTYPE_P2P_GO, /* 9 */
+	/* keep last */
+	NUM_NL80211_IFTYPES,
+	NL80211_IFTYPE_MAX = NUM_NL80211_IFTYPES - 1
+};
+#endif
+static int cfg80211_rtw_change_iface(struct wiphy *wiphy,
+				     struct net_device *ndev,
+				     enum nl80211_iftype type,
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 12, 0))
+				     u32 *flags,
+#endif
+				     struct vif_params *params)
+{
+	enum nl80211_iftype old_type;
+	NDIS_802_11_NETWORK_INFRASTRUCTURE networkType;
+	_adapter *padapter = (_adapter *)rtw_netdev_priv(ndev);
+	struct wireless_dev *rtw_wdev = padapter->rtw_wdev;
+	struct mlme_ext_priv	*pmlmeext = &(padapter->mlmeextpriv);
+#ifdef CONFIG_P2P
+	struct wifidirect_info *pwdinfo = &(padapter->wdinfo);
+	u8 is_p2p = _FALSE;
+#endif
+	int ret = 0;
+	u8 change = _FALSE;
+
+	RTW_INFO(FUNC_NDEV_FMT" type=%d, hw_port:%d\n", FUNC_NDEV_ARG(ndev), type, padapter->hw_port);
+
+	if (adapter_to_dvobj(padapter)->processing_dev_remove == _TRUE) {
+		ret = -EPERM;
+		goto exit;
+	}
+
+
+	RTW_INFO(FUNC_NDEV_FMT" call netdev_open\n", FUNC_NDEV_ARG(ndev));
+	if (netdev_open(ndev) != 0) {
+		RTW_INFO(FUNC_NDEV_FMT" call netdev_open fail\n", FUNC_NDEV_ARG(ndev));
+		ret = -EPERM;
+		goto exit;
+	}
+
+
+	if (_FAIL == rtw_pwr_wakeup(padapter)) {
+		RTW_INFO(FUNC_NDEV_FMT" call rtw_pwr_wakeup fail\n", FUNC_NDEV_ARG(ndev));
+		ret = -EPERM;
+		goto exit;
+	}
+
+	old_type = rtw_wdev->iftype;
+	RTW_INFO(FUNC_NDEV_FMT" old_iftype=%d, new_iftype=%d\n",
+		FUNC_NDEV_ARG(ndev), old_type, type);
+
+	if (old_type != type) {
+		change = _TRUE;
+		pmlmeext->action_public_rxseq = 0xffff;
+		pmlmeext->action_public_dialog_token = 0xff;
+	}
+
+	/* initial default type */
+	ndev->type = ARPHRD_ETHER;
+
+	/*
+	 * Disable Power Save in moniter mode,
+	 * and enable it after leaving moniter mode.
+	 */
+	if (type == NL80211_IFTYPE_MONITOR) {
+		rtw_ps_deny(padapter, PS_DENY_MONITOR_MODE);
+		LeaveAllPowerSaveMode(padapter);
+	} else if (old_type == NL80211_IFTYPE_MONITOR) {
+		/* driver in moniter mode in last time */
+		rtw_ps_deny_cancel(padapter, PS_DENY_MONITOR_MODE);
+	}
+
+	switch (type) {
+	case NL80211_IFTYPE_ADHOC:
+		networkType = Ndis802_11IBSS;
+		break;
+
+	#if defined(CONFIG_P2P) && ((LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) || defined(COMPAT_KERNEL_RELEASE))
+	case NL80211_IFTYPE_P2P_CLIENT:
+		is_p2p = _TRUE;
+		__attribute__((__fallthrough__));
+	#endif
+	case NL80211_IFTYPE_STATION:
+		networkType = Ndis802_11Infrastructure;
+
+		#ifdef CONFIG_P2P
+		if (change && pwdinfo->driver_interface == DRIVER_CFG80211) {
+			if (is_p2p == _TRUE)
+				rtw_p2p_enable(padapter, P2P_ROLE_CLIENT);
+			#if !RTW_P2P_GROUP_INTERFACE
+			else if (rtw_p2p_chk_role(pwdinfo, P2P_ROLE_CLIENT)
+					|| rtw_p2p_chk_role(pwdinfo, P2P_ROLE_GO)
+			) {
+				/* it means remove GC/GO and change mode from GC/GO to station(P2P DEVICE) */
+				rtw_p2p_set_role(pwdinfo, P2P_ROLE_DEVICE);
+			}
+			#endif
+		}
+		#endif /* CONFIG_P2P */
+
+		break;
+
+	#if defined(CONFIG_P2P) && ((LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) || defined(COMPAT_KERNEL_RELEASE))
+	case NL80211_IFTYPE_P2P_GO:
+		is_p2p = _TRUE;
+		__attribute__((__fallthrough__));
+	#endif
+	case NL80211_IFTYPE_AP:
+		networkType = Ndis802_11APMode;
+
+		#ifdef CONFIG_P2P
+		if (change && pwdinfo->driver_interface == DRIVER_CFG80211) {
+			if (is_p2p == _TRUE)
+				rtw_p2p_enable(padapter, P2P_ROLE_GO);
+			#if !RTW_P2P_GROUP_INTERFACE
+			else if (!rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE)) {
+				/* it means P2P Group created, we will be GO and change mode from  P2P DEVICE to AP(GO) */
+				rtw_p2p_set_role(pwdinfo, P2P_ROLE_GO);
+			}
+			#endif
+		}
+		#endif /* CONFIG_P2P */
+
+		break;
+
+#ifdef CONFIG_RTW_MESH
+	case NL80211_IFTYPE_MESH_POINT:
+		networkType = Ndis802_11_mesh;
+		break;
+#endif
+
+	case NL80211_IFTYPE_MONITOR:
+		networkType = Ndis802_11Monitor;
+#if 0
+		ndev->type = ARPHRD_IEEE80211; /* IEEE 802.11 : 801 */
+#endif
+		ndev->type = ARPHRD_IEEE80211_RADIOTAP; /* IEEE 802.11 + radiotap header : 803 */
+		break;
+	default:
+		ret = -EOPNOTSUPP;
+		goto exit;
+	}
+
+	rtw_wdev->iftype = type;
+
+	if (rtw_set_802_11_infrastructure_mode(padapter, networkType) == _FALSE) {
+		rtw_wdev->iftype = old_type;
+		ret = -EPERM;
+		goto exit;
+	}
+
+	rtw_setopmode_cmd(padapter, networkType, RTW_CMDF_WAIT_ACK);
+
+exit:
+
+	RTW_INFO(FUNC_NDEV_FMT" ret:%d\n", FUNC_NDEV_ARG(ndev), ret);
+	return ret;
+}
+
+void rtw_cfg80211_indicate_scan_done(_adapter *adapter, bool aborted)
+{
+	struct rtw_wdev_priv *pwdev_priv = adapter_wdev_data(adapter);
+	_irqL	irqL;
+
+#if (KERNEL_VERSION(4, 7, 0) <= LINUX_VERSION_CODE)
+	struct cfg80211_scan_info info;
+
+	memset(&info, 0, sizeof(info));
+	info.aborted = aborted;
+#endif
+
+	_enter_critical_bh(&pwdev_priv->scan_req_lock, &irqL);
+	if (pwdev_priv->scan_request != NULL) {
+		#ifdef CONFIG_DEBUG_CFG80211
+		RTW_INFO("%s with scan req\n", __FUNCTION__);
+		#endif
+
+		/* avoid WARN_ON(request != wiphy_to_dev(request->wiphy)->scan_req); */
+		if (pwdev_priv->scan_request->wiphy != pwdev_priv->rtw_wdev->wiphy)
+			RTW_INFO("error wiphy compare\n");
+		else
+#if (KERNEL_VERSION(4, 7, 0) <= LINUX_VERSION_CODE)
+			cfg80211_scan_done(pwdev_priv->scan_request, &info);
+#else
+			cfg80211_scan_done(pwdev_priv->scan_request, aborted);
+#endif
+
+		pwdev_priv->scan_request = NULL;
+	} else {
+		#ifdef CONFIG_DEBUG_CFG80211
+		RTW_INFO("%s without scan req\n", __FUNCTION__);
+		#endif
+	}
+	_exit_critical_bh(&pwdev_priv->scan_req_lock, &irqL);
+}
+
+u32 rtw_cfg80211_wait_scan_req_empty(_adapter *adapter, u32 timeout_ms)
+{
+	struct rtw_wdev_priv *wdev_priv = adapter_wdev_data(adapter);
+	u8 empty = _FALSE;
+	systime start;
+	u32 pass_ms;
+
+	start = rtw_get_current_time();
+
+	while (rtw_get_passing_time_ms(start) <= timeout_ms) {
+
+		if (RTW_CANNOT_RUN(adapter))
+			break;
+
+		if (!wdev_priv->scan_request) {
+			empty = _TRUE;
+			break;
+		}
+
+		rtw_msleep_os(10);
+	}
+
+	pass_ms = rtw_get_passing_time_ms(start);
+
+	if (empty == _FALSE && pass_ms > timeout_ms)
+		RTW_PRINT(FUNC_ADPT_FMT" pass_ms:%u, timeout\n"
+			, FUNC_ADPT_ARG(adapter), pass_ms);
+
+	return pass_ms;
+}
+
+void rtw_cfg80211_unlink_bss(_adapter *padapter, struct wlan_network *pnetwork)
+{
+	struct wireless_dev *pwdev = padapter->rtw_wdev;
+	struct wiphy *wiphy = pwdev->wiphy;
+	struct cfg80211_bss *bss = NULL;
+	WLAN_BSSID_EX select_network = pnetwork->network;
+
+	bss = cfg80211_get_bss(wiphy, NULL/*notify_channel*/,
+		select_network.MacAddress, select_network.Ssid.Ssid,
+		select_network.Ssid.SsidLength,
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 1, 0)
+		select_network.InfrastructureMode == Ndis802_11Infrastructure?IEEE80211_BSS_TYPE_ESS:IEEE80211_BSS_TYPE_IBSS,
+		IEEE80211_PRIVACY(select_network.Privacy));
+#else
+		select_network.InfrastructureMode == Ndis802_11Infrastructure?WLAN_CAPABILITY_ESS:WLAN_CAPABILITY_IBSS,
+		select_network.InfrastructureMode == Ndis802_11Infrastructure?WLAN_CAPABILITY_ESS:WLAN_CAPABILITY_IBSS);
+#endif
+
+	if (bss) {
+		cfg80211_unlink_bss(wiphy, bss);
+		RTW_INFO("%s(): cfg80211_unlink %s!!\n", __func__, select_network.Ssid.Ssid);
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(3, 9, 0)
+		cfg80211_put_bss(padapter->rtw_wdev->wiphy, bss);
+#else
+		cfg80211_put_bss(bss);
+#endif
+	}
+	return;
+}
+
+/* if target wps scan ongoing, target_ssid is filled */
+int rtw_cfg80211_is_target_wps_scan(struct cfg80211_scan_request *scan_req, struct cfg80211_ssid *target_ssid)
+{
+	int ret = 0;
+
+	if (scan_req->n_ssids != 1
+		|| scan_req->ssids[0].ssid_len == 0
+		|| scan_req->n_channels != 1
+	)
+		goto exit;
+
+	/* under target WPS scan */
+	_rtw_memcpy(target_ssid, scan_req->ssids, sizeof(struct cfg80211_ssid));
+	ret = 1;
+
+exit:
+	return ret;
+}
+
+static void _rtw_cfg80211_surveydone_event_callback(_adapter *padapter, struct cfg80211_scan_request *scan_req)
+{
+	struct rf_ctl_t *rfctl = adapter_to_rfctl(padapter);
+	RT_CHANNEL_INFO *chset = rfctl->channel_set;
+	_irqL	irqL;
+	_list					*plist, *phead;
+	struct	mlme_priv	*pmlmepriv = &(padapter->mlmepriv);
+	_queue				*queue	= &(pmlmepriv->scanned_queue);
+	struct	wlan_network	*pnetwork = NULL;
+	struct rtw_wdev_priv *pwdev_priv = adapter_wdev_data(padapter);
+	struct cfg80211_ssid target_ssid;
+	u8 target_wps_scan = 0;
+	u8 ch;
+
+#ifdef CONFIG_DEBUG_CFG80211
+	RTW_INFO("%s\n", __func__);
+#endif
+
+	if (scan_req)
+		target_wps_scan = rtw_cfg80211_is_target_wps_scan(scan_req, &target_ssid);
+	else {
+		_enter_critical_bh(&pwdev_priv->scan_req_lock, &irqL);
+		if (pwdev_priv->scan_request != NULL)
+			target_wps_scan = rtw_cfg80211_is_target_wps_scan(pwdev_priv->scan_request, &target_ssid);
+		_exit_critical_bh(&pwdev_priv->scan_req_lock, &irqL);
+	}
+
+	_enter_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);
+
+	phead = get_list_head(queue);
+	plist = get_next(phead);
+
+	while (1) {
+		if (rtw_end_of_queue_search(phead, plist) == _TRUE)
+			break;
+
+		pnetwork = LIST_CONTAINOR(plist, struct wlan_network, list);
+		ch = pnetwork->network.Configuration.DSConfig;
+
+		/* report network only if the current channel set contains the channel to which this network belongs */
+		if (rtw_chset_search_ch(chset, ch) >= 0
+			&& rtw_mlme_band_check(padapter, ch) == _TRUE
+			&& _TRUE == rtw_validate_ssid(&(pnetwork->network.Ssid))
+			&& (!IS_DFS_SLAVE_WITH_RD(rfctl)
+				|| rtw_odm_dfs_domain_unknown(rfctl_to_dvobj(rfctl))
+				|| !rtw_chset_is_ch_non_ocp(chset, ch))
+		) {
+			if (target_wps_scan)
+				rtw_cfg80211_clear_wps_sr_of_non_target_bss(padapter, pnetwork, &target_ssid);
+			rtw_cfg80211_inform_bss(padapter, pnetwork);
+		}
+#if 0
+		/* check ralink testbed RSN IE length */
+		{
+			if (_rtw_memcmp(pnetwork->network.Ssid.Ssid, "Ralink_11n_AP", 13)) {
+				uint ie_len = 0;
+				u8 *p = NULL;
+				p = rtw_get_ie(pnetwork->network.IEs + _BEACON_IE_OFFSET_, _RSN_IE_2_, &ie_len, (pnetwork->network.IELength - _BEACON_IE_OFFSET_));
+				RTW_INFO("ie_len=%d\n", ie_len);
+			}
+		}
+#endif
+		plist = get_next(plist);
+
+	}
+
+	_exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);
+}
+
+inline void rtw_cfg80211_surveydone_event_callback(_adapter *padapter)
+{
+	_rtw_cfg80211_surveydone_event_callback(padapter, NULL);
+}
+
+static int rtw_cfg80211_set_probe_req_wpsp2pie(_adapter *padapter, char *buf, int len)
+{
+	int ret = 0;
+	uint wps_ielen = 0;
+	u8 *wps_ie;
+	u32	p2p_ielen = 0;
+	u8 *p2p_ie;
+	u32	wfd_ielen = 0;
+	u8 *wfd_ie;
+	struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
+
+#ifdef CONFIG_DEBUG_CFG80211
+	RTW_INFO("%s, ielen=%d\n", __func__, len);
+#endif
+
+	if (len > 0) {
+		wps_ie = rtw_get_wps_ie(buf, len, NULL, &wps_ielen);
+		if (wps_ie) {
+			#ifdef CONFIG_DEBUG_CFG80211
+			RTW_INFO("probe_req_wps_ielen=%d\n", wps_ielen);
+			#endif
+
+			if (pmlmepriv->wps_probe_req_ie) {
+				u32 free_len = pmlmepriv->wps_probe_req_ie_len;
+				pmlmepriv->wps_probe_req_ie_len = 0;
+				rtw_mfree(pmlmepriv->wps_probe_req_ie, free_len);
+				pmlmepriv->wps_probe_req_ie = NULL;
+			}
+
+			pmlmepriv->wps_probe_req_ie = rtw_malloc(wps_ielen);
+			if (pmlmepriv->wps_probe_req_ie == NULL) {
+				RTW_INFO("%s()-%d: rtw_malloc() ERROR!\n", __FUNCTION__, __LINE__);
+				return -EINVAL;
+
+			}
+			_rtw_memcpy(pmlmepriv->wps_probe_req_ie, wps_ie, wps_ielen);
+			pmlmepriv->wps_probe_req_ie_len = wps_ielen;
+		}
+
+		/* buf += wps_ielen; */
+		/* len -= wps_ielen; */
+
+		#ifdef CONFIG_P2P
+		p2p_ie = rtw_get_p2p_ie(buf, len, NULL, &p2p_ielen);
+		if (p2p_ie) {
+			struct wifidirect_info *wdinfo = &padapter->wdinfo;
+			u32 attr_contentlen = 0;
+			u8 listen_ch_attr[5];
+
+			#ifdef CONFIG_DEBUG_CFG80211
+			RTW_INFO("probe_req_p2p_ielen=%d\n", p2p_ielen);
+			#endif
+
+			if (pmlmepriv->p2p_probe_req_ie) {
+				u32 free_len = pmlmepriv->p2p_probe_req_ie_len;
+				pmlmepriv->p2p_probe_req_ie_len = 0;
+				rtw_mfree(pmlmepriv->p2p_probe_req_ie, free_len);
+				pmlmepriv->p2p_probe_req_ie = NULL;
+			}
+
+			pmlmepriv->p2p_probe_req_ie = rtw_malloc(p2p_ielen);
+			if (pmlmepriv->p2p_probe_req_ie == NULL) {
+				RTW_INFO("%s()-%d: rtw_malloc() ERROR!\n", __FUNCTION__, __LINE__);
+				return -EINVAL;
+
+			}
+			_rtw_memcpy(pmlmepriv->p2p_probe_req_ie, p2p_ie, p2p_ielen);
+			pmlmepriv->p2p_probe_req_ie_len = p2p_ielen;
+
+			if (rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_LISTEN_CH, (u8 *)listen_ch_attr, (uint *) &attr_contentlen)
+				&& attr_contentlen == 5) {
+				if (wdinfo->listen_channel !=  listen_ch_attr[4]) {
+					RTW_INFO(FUNC_ADPT_FMT" listen channel - country:%c%c%c, class:%u, ch:%u\n",
+						FUNC_ADPT_ARG(padapter), listen_ch_attr[0], listen_ch_attr[1], listen_ch_attr[2],
+						listen_ch_attr[3], listen_ch_attr[4]);
+					wdinfo->listen_channel = listen_ch_attr[4];
+				}
+			}
+		}
+		#endif /* CONFIG_P2P */
+
+		#ifdef CONFIG_WFD
+		wfd_ie = rtw_get_wfd_ie(buf, len, NULL, &wfd_ielen);
+		if (wfd_ie) {
+			#ifdef CONFIG_DEBUG_CFG80211
+			RTW_INFO("probe_req_wfd_ielen=%d\n", wfd_ielen);
+			#endif
+
+			if (rtw_mlme_update_wfd_ie_data(pmlmepriv, MLME_PROBE_REQ_IE, wfd_ie, wfd_ielen) != _SUCCESS)
+				return -EINVAL;
+		}
+		#endif /* CONFIG_WFD */
+	}
+
+	return ret;
+
+}
+
+#ifdef CONFIG_CONCURRENT_MODE
+u8 rtw_cfg80211_scan_via_buddy(_adapter *padapter, struct cfg80211_scan_request *request)
+{
+	int i;
+	u8 ret = _FALSE;
+	_adapter *iface = NULL;
+	_irqL	irqL;
+	struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
+	struct rtw_wdev_priv *pwdev_priv = adapter_wdev_data(padapter);
+	struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
+
+	for (i = 0; i < dvobj->iface_nums; i++) {
+		struct mlme_priv *buddy_mlmepriv;
+		struct rtw_wdev_priv *buddy_wdev_priv;
+
+		iface = dvobj->padapters[i];
+		if (iface == NULL)
+			continue;
+
+		if (iface == padapter)
+			continue;
+
+		if (rtw_is_adapter_up(iface) == _FALSE)
+			continue;
+
+		buddy_mlmepriv = &iface->mlmepriv;
+		if (!check_fwstate(buddy_mlmepriv, _FW_UNDER_SURVEY))
+			continue;
+
+		buddy_wdev_priv = adapter_wdev_data(iface);
+		_enter_critical_bh(&pwdev_priv->scan_req_lock, &irqL);
+		_enter_critical_bh(&buddy_wdev_priv->scan_req_lock, &irqL);
+		if (buddy_wdev_priv->scan_request) {
+			pmlmepriv->scanning_via_buddy_intf = _TRUE;
+			_enter_critical_bh(&pmlmepriv->lock, &irqL);
+			set_fwstate(pmlmepriv, _FW_UNDER_SURVEY);
+			_exit_critical_bh(&pmlmepriv->lock, &irqL);
+			pwdev_priv->scan_request = request;
+			ret = _TRUE;
+		}
+		_exit_critical_bh(&buddy_wdev_priv->scan_req_lock, &irqL);
+		_exit_critical_bh(&pwdev_priv->scan_req_lock, &irqL);
+
+		if (ret == _TRUE)
+			goto exit;
+	}
+
+exit:
+	return ret;
+}
+
+void rtw_cfg80211_indicate_scan_done_for_buddy(_adapter *padapter, bool bscan_aborted)
+{
+	int i;
+	u8 ret = 0;
+	_adapter *iface = NULL;
+	_irqL	irqL;
+	struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
+	struct mlme_priv *mlmepriv;
+	struct rtw_wdev_priv *wdev_priv;
+	bool indicate_buddy_scan;
+
+	for (i = 0; i < dvobj->iface_nums; i++) {
+		iface = dvobj->padapters[i];
+		if ((iface) && rtw_is_adapter_up(iface)) {
+
+			if (iface == padapter)
+				continue;
+
+			mlmepriv = &(iface->mlmepriv);
+			wdev_priv = adapter_wdev_data(iface);
+
+			indicate_buddy_scan = _FALSE;
+			_enter_critical_bh(&wdev_priv->scan_req_lock, &irqL);
+			if (mlmepriv->scanning_via_buddy_intf == _TRUE) {
+				mlmepriv->scanning_via_buddy_intf = _FALSE;
+				clr_fwstate(mlmepriv, _FW_UNDER_SURVEY);
+				if (wdev_priv->scan_request)
+					indicate_buddy_scan = _TRUE;
+			}
+			_exit_critical_bh(&wdev_priv->scan_req_lock, &irqL);
+
+			if (indicate_buddy_scan == _TRUE) {
+				rtw_cfg80211_surveydone_event_callback(iface);
+				rtw_indicate_scan_done(iface, bscan_aborted);
+			}
+
+		}
+	}
+}
+#endif /* CONFIG_CONCURRENT_MODE */
+
+static int cfg80211_rtw_scan(struct wiphy *wiphy
+	#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 6, 0))
+	, struct net_device *ndev
+	#endif
+	, struct cfg80211_scan_request *request)
+{
+	int i;
+	u8 _status = _FALSE;
+	int ret = 0;
+	struct sitesurvey_parm parm;
+	_irqL	irqL;
+	u8 survey_times = 3;
+	u8 survey_times_for_one_ch = 6;
+	struct cfg80211_ssid *ssids = request->ssids;
+	int social_channel = 0, j = 0;
+	bool need_indicate_scan_done = _FALSE;
+	bool ps_denied = _FALSE;
+	u8 ssc_chk;
+	_adapter *padapter;
+	struct wireless_dev *wdev;
+	struct rtw_wdev_priv *pwdev_priv;
+	struct mlme_priv *pmlmepriv;
+#ifdef CONFIG_P2P
+	struct wifidirect_info *pwdinfo;
+#endif /* CONFIG_P2P */
+
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 6, 0))
+	wdev = request->wdev;
+	#if defined(RTW_DEDICATED_P2P_DEVICE)
+	if (wdev == wiphy_to_pd_wdev(wiphy))
+		padapter = wiphy_to_adapter(wiphy);
+	else
+	#endif
+	if (wdev_to_ndev(wdev))
+		padapter = (_adapter *)rtw_netdev_priv(wdev_to_ndev(wdev));
+	else {
+		ret = -EINVAL;
+		goto exit;
+	}
+#else
+	if (ndev == NULL) {
+		ret = -EINVAL;
+		goto exit;
+	}
+	padapter = (_adapter *)rtw_netdev_priv(ndev);
+	wdev = ndev_to_wdev(ndev);
+#endif
+
+	pwdev_priv = adapter_wdev_data(padapter);
+	pmlmepriv = &padapter->mlmepriv;
+#ifdef CONFIG_P2P
+	pwdinfo = &(padapter->wdinfo);
+#endif /* CONFIG_P2P */
+
+	RTW_INFO(FUNC_ADPT_FMT"%s\n", FUNC_ADPT_ARG(padapter)
+		, wdev == wiphy_to_pd_wdev(wiphy) ? " PD" : "");
+
+#if 1
+	ssc_chk = rtw_sitesurvey_condition_check(padapter, _TRUE);
+
+	if (ssc_chk == SS_DENY_MP_MODE)
+		goto bypass_p2p_chk;
+#ifdef DBG_LA_MODE
+	if (ssc_chk == SS_DENY_LA_MODE)
+		goto bypass_p2p_chk;
+#endif
+#ifdef CONFIG_P2P
+	if (pwdinfo->driver_interface == DRIVER_CFG80211) {
+		if (ssids->ssid != NULL
+			&& _rtw_memcmp(ssids->ssid, "DIRECT-", 7)
+			&& rtw_get_p2p_ie((u8 *)request->ie, request->ie_len, NULL, NULL)
+		) {
+			if (rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE))
+				rtw_p2p_enable(padapter, P2P_ROLE_DEVICE);
+			else {
+				rtw_p2p_set_pre_state(pwdinfo, rtw_p2p_state(pwdinfo));
+				#ifdef CONFIG_DEBUG_CFG80211
+				RTW_INFO("%s, role=%d, p2p_state=%d\n", __func__, rtw_p2p_role(pwdinfo), rtw_p2p_state(pwdinfo));
+				#endif
+			}
+			rtw_p2p_set_state(pwdinfo, P2P_STATE_LISTEN);
+
+			if (request->n_channels == 3 &&
+				request->channels[0]->hw_value == 1 &&
+				request->channels[1]->hw_value == 6 &&
+				request->channels[2]->hw_value == 11
+			)
+				social_channel = 1;
+		}
+	}
+#endif /*CONFIG_P2P*/
+
+	if (request->ie && request->ie_len > 0)
+		rtw_cfg80211_set_probe_req_wpsp2pie(padapter, (u8 *)request->ie, request->ie_len);
+
+bypass_p2p_chk:
+
+	switch (ssc_chk) {
+		case SS_ALLOW :
+			break;
+
+		case SS_DENY_MP_MODE:
+			ret = -EPERM;
+			goto exit;
+		#ifdef DBG_LA_MODE
+		case SS_DENY_LA_MODE:
+			ret = -EPERM;
+			goto exit;
+		#endif
+		#ifdef CONFIG_RTW_REPEATER_SON
+		case SS_DENY_RSON_SCANING :
+		#endif
+		case SS_DENY_BLOCK_SCAN :
+		case SS_DENY_SELF_AP_UNDER_WPS :
+		case SS_DENY_SELF_AP_UNDER_LINKING :
+		case SS_DENY_SELF_AP_UNDER_SURVEY :
+		case SS_DENY_SELF_STA_UNDER_SURVEY :
+		#ifdef CONFIG_CONCURRENT_MODE
+		case SS_DENY_BUDDY_UNDER_LINK_WPS :
+		#endif
+		case SS_DENY_BUSY_TRAFFIC :
+			need_indicate_scan_done = _TRUE;
+			goto check_need_indicate_scan_done;
+
+		case SS_DENY_BY_DRV :
+			#if CONFIG_NOTIFY_SCAN_ABORT_WITH_BUSY
+			ret = -EBUSY;
+			goto exit;
+			#else
+			need_indicate_scan_done = _TRUE;
+			goto check_need_indicate_scan_done;
+			#endif
+			break;
+
+		case SS_DENY_SELF_STA_UNDER_LINKING :
+			ret = -EBUSY;
+			goto check_need_indicate_scan_done;
+
+		#ifdef CONFIG_CONCURRENT_MODE
+		case SS_DENY_BUDDY_UNDER_SURVEY :
+			{
+				bool scan_via_buddy = rtw_cfg80211_scan_via_buddy(padapter, request);
+
+				if (scan_via_buddy == _FALSE)
+					need_indicate_scan_done = _TRUE;
+
+				goto check_need_indicate_scan_done;
+			}
+		#endif
+
+		default :
+			RTW_ERR("site survey check code (%d) unknown\n", ssc_chk);
+			need_indicate_scan_done = _TRUE;
+			goto check_need_indicate_scan_done;
+	}
+
+	rtw_ps_deny(padapter, PS_DENY_SCAN);
+	ps_denied = _TRUE;
+	if (_FAIL == rtw_pwr_wakeup(padapter)) {
+		need_indicate_scan_done = _TRUE;
+		goto check_need_indicate_scan_done;
+	}
+
+#else
+
+
+#ifdef CONFIG_MP_INCLUDED
+	if (rtw_mp_mode_check(padapter)) {
+		RTW_INFO("MP mode block Scan request\n");
+		ret = -EPERM;
+		goto exit;
+	}
+#endif
+
+#ifdef CONFIG_P2P
+	if (pwdinfo->driver_interface == DRIVER_CFG80211) {
+		if (ssids->ssid != NULL
+			&& _rtw_memcmp(ssids->ssid, "DIRECT-", 7)
+			&& rtw_get_p2p_ie((u8 *)request->ie, request->ie_len, NULL, NULL)
+		) {
+			if (rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE))
+				rtw_p2p_enable(padapter, P2P_ROLE_DEVICE);
+			else {
+				rtw_p2p_set_pre_state(pwdinfo, rtw_p2p_state(pwdinfo));
+				#ifdef CONFIG_DEBUG_CFG80211
+				RTW_INFO("%s, role=%d, p2p_state=%d\n", __func__, rtw_p2p_role(pwdinfo), rtw_p2p_state(pwdinfo));
+				#endif
+			}
+			rtw_p2p_set_state(pwdinfo, P2P_STATE_LISTEN);
+
+			if (request->n_channels == 3 &&
+				request->channels[0]->hw_value == 1 &&
+				request->channels[1]->hw_value == 6 &&
+				request->channels[2]->hw_value == 11
+			)
+				social_channel = 1;
+		}
+	}
+#endif /*CONFIG_P2P*/
+
+	if (request->ie && request->ie_len > 0)
+		rtw_cfg80211_set_probe_req_wpsp2pie(padapter, (u8 *)request->ie, request->ie_len);
+
+#ifdef CONFIG_RTW_REPEATER_SON
+	if (padapter->rtw_rson_scanstage == RSON_SCAN_PROCESS) {
+		RTW_INFO(FUNC_ADPT_FMT" blocking scan for under rson scanning process\n", FUNC_ADPT_ARG(padapter));
+		need_indicate_scan_done = _TRUE;
+		goto check_need_indicate_scan_done;
+	}
+#endif
+
+	if (adapter_wdev_data(padapter)->block_scan == _TRUE) {
+		RTW_INFO(FUNC_ADPT_FMT" wdev_priv.block_scan is set\n", FUNC_ADPT_ARG(padapter));
+		need_indicate_scan_done = _TRUE;
+		goto check_need_indicate_scan_done;
+	}
+
+	rtw_ps_deny(padapter, PS_DENY_SCAN);
+	ps_denied = _TRUE;
+	if (_FAIL == rtw_pwr_wakeup(padapter)) {
+		need_indicate_scan_done = _TRUE;
+		goto check_need_indicate_scan_done;
+	}
+
+	if (rtw_is_scan_deny(padapter)) {
+		RTW_INFO(FUNC_ADPT_FMT	": scan deny\n", FUNC_ADPT_ARG(padapter));
+#if CONFIG_NOTIFY_SCAN_ABORT_WITH_BUSY
+		ret = -EBUSY;
+		goto exit;
+#else
+		need_indicate_scan_done = _TRUE;
+		goto check_need_indicate_scan_done;
+#endif
+	}
+
+	/* check fw state*/
+	if (check_fwstate(pmlmepriv, WIFI_AP_STATE) == _TRUE) {
+
+#ifdef CONFIG_DEBUG_CFG80211
+		RTW_INFO(FUNC_ADPT_FMT" under WIFI_AP_STATE\n", FUNC_ADPT_ARG(padapter));
+#endif
+
+		if (check_fwstate(pmlmepriv, WIFI_UNDER_WPS | _FW_UNDER_SURVEY | _FW_UNDER_LINKING) == _TRUE) {
+			RTW_INFO("%s, fwstate=0x%x\n", __func__, pmlmepriv->fw_state);
+
+			if (check_fwstate(pmlmepriv, WIFI_UNDER_WPS))
+				RTW_INFO("AP mode process WPS\n");
+
+			need_indicate_scan_done = _TRUE;
+			goto check_need_indicate_scan_done;
+		}
+	}
+
+	if (check_fwstate(pmlmepriv, _FW_UNDER_SURVEY) == _TRUE) {
+		RTW_INFO("%s, fwstate=0x%x\n", __func__, pmlmepriv->fw_state);
+		need_indicate_scan_done = _TRUE;
+		goto check_need_indicate_scan_done;
+	} else if (check_fwstate(pmlmepriv, _FW_UNDER_LINKING) == _TRUE) {
+		RTW_INFO("%s, fwstate=0x%x\n", __func__, pmlmepriv->fw_state);
+		ret = -EBUSY;
+		goto check_need_indicate_scan_done;
+	}
+
+#ifdef CONFIG_CONCURRENT_MODE
+	if (rtw_mi_buddy_check_fwstate(padapter, _FW_UNDER_LINKING | WIFI_UNDER_WPS)) {
+		RTW_INFO("%s exit due to buddy_intf's mlme state under linking or wps\n", __func__);
+		need_indicate_scan_done = _TRUE;
+		goto check_need_indicate_scan_done;
+
+	} else if (rtw_mi_buddy_check_fwstate(padapter, _FW_UNDER_SURVEY)) {
+		bool scan_via_buddy = rtw_cfg80211_scan_via_buddy(padapter, request);
+
+		if (scan_via_buddy == _FALSE)
+			need_indicate_scan_done = _TRUE;
+
+		goto check_need_indicate_scan_done;
+	}
+#endif /* CONFIG_CONCURRENT_MODE */
+
+	/* busy traffic check*/
+	if (rtw_mi_busy_traffic_check(padapter, _TRUE)) {
+		need_indicate_scan_done = _TRUE;
+		goto check_need_indicate_scan_done;
+	}
+#endif
+
+#ifdef CONFIG_P2P
+	if (!rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE) && !rtw_p2p_chk_state(pwdinfo, P2P_STATE_IDLE)) {
+		rtw_p2p_set_state(pwdinfo, P2P_STATE_FIND_PHASE_SEARCH);
+
+		if (social_channel == 0)
+			rtw_p2p_findphase_ex_set(pwdinfo, P2P_FINDPHASE_EX_NONE);
+		else
+			rtw_p2p_findphase_ex_set(pwdinfo, P2P_FINDPHASE_EX_SOCIAL_LAST);
+	}
+#endif /* CONFIG_P2P */
+
+	rtw_init_sitesurvey_parm(padapter, &parm);
+
+	/* parsing request ssids, n_ssids */
+	for (i = 0; i < request->n_ssids && i < RTW_SSID_SCAN_AMOUNT; i++) {
+		#ifdef CONFIG_DEBUG_CFG80211
+		RTW_INFO("ssid=%s, len=%d\n", ssids[i].ssid, ssids[i].ssid_len);
+		#endif
+		_rtw_memcpy(&parm.ssid[i].Ssid, ssids[i].ssid, ssids[i].ssid_len);
+		parm.ssid[i].SsidLength = ssids[i].ssid_len;
+	}
+	parm.ssid_num = i;
+
+	/* parsing channels, n_channels */
+	for (i = 0; i < request->n_channels && i < RTW_CHANNEL_SCAN_AMOUNT; i++) {
+		#ifdef CONFIG_DEBUG_CFG80211
+		RTW_INFO(FUNC_ADPT_FMT CHAN_FMT"\n", FUNC_ADPT_ARG(padapter), CHAN_ARG(request->channels[i]));
+		#endif
+		parm.ch[i].hw_value = request->channels[i]->hw_value;
+		parm.ch[i].flags = request->channels[i]->flags;
+	}
+	parm.ch_num = i;
+
+	if (request->n_channels == 1) {
+		for (i = 1; i < survey_times_for_one_ch; i++)
+			_rtw_memcpy(&parm.ch[i], &parm.ch[0], sizeof(struct rtw_ieee80211_channel));
+		parm.ch_num = survey_times_for_one_ch;
+	} else if (request->n_channels <= 4) {
+		for (j = request->n_channels - 1; j >= 0; j--)
+			for (i = 0; i < survey_times; i++)
+				_rtw_memcpy(&parm.ch[j * survey_times + i], &parm.ch[j], sizeof(struct rtw_ieee80211_channel));
+		parm.ch_num = survey_times * request->n_channels;
+	}
+
+	_enter_critical_bh(&pwdev_priv->scan_req_lock, &irqL);
+	_enter_critical_bh(&pmlmepriv->lock, &irqL);
+	_status = rtw_sitesurvey_cmd(padapter, &parm);
+	if (_status == _SUCCESS)
+		pwdev_priv->scan_request = request;
+	else
+		ret = -1;
+	_exit_critical_bh(&pmlmepriv->lock, &irqL);
+	_exit_critical_bh(&pwdev_priv->scan_req_lock, &irqL);
+
+check_need_indicate_scan_done:
+	if (_TRUE == need_indicate_scan_done) {
+#if (KERNEL_VERSION(4, 7, 0) <= LINUX_VERSION_CODE)
+		struct cfg80211_scan_info info;
+
+		memset(&info, 0, sizeof(info));
+		info.aborted = 0;
+#endif
+
+		_rtw_cfg80211_surveydone_event_callback(padapter, request);
+#if (KERNEL_VERSION(4, 7, 0) <= LINUX_VERSION_CODE)
+		cfg80211_scan_done(request, &info);
+#else
+		cfg80211_scan_done(request, 0);
+#endif
+	}
+
+cancel_ps_deny:
+	if (ps_denied == _TRUE)
+		rtw_ps_deny_cancel(padapter, PS_DENY_SCAN);
+
+exit:
+	return ret;
+
+}
+
+static int cfg80211_rtw_set_wiphy_params(struct wiphy *wiphy, u32 changed)
+{
+#if 0
+	struct iwm_priv *iwm = wiphy_to_iwm(wiphy);
+
+	if (changed & WIPHY_PARAM_RTS_THRESHOLD &&
+	    (iwm->conf.rts_threshold != wiphy->rts_threshold)) {
+		int ret;
+
+		iwm->conf.rts_threshold = wiphy->rts_threshold;
+
+		ret = iwm_umac_set_config_fix(iwm, UMAC_PARAM_TBL_CFG_FIX,
+				CFG_RTS_THRESHOLD,
+				iwm->conf.rts_threshold);
+		if (ret < 0)
+			return ret;
+	}
+
+	if (changed & WIPHY_PARAM_FRAG_THRESHOLD &&
+	    (iwm->conf.frag_threshold != wiphy->frag_threshold)) {
+		int ret;
+
+		iwm->conf.frag_threshold = wiphy->frag_threshold;
+
+		ret = iwm_umac_set_config_fix(iwm, UMAC_PARAM_TBL_FA_CFG_FIX,
+				CFG_FRAG_THRESHOLD,
+				iwm->conf.frag_threshold);
+		if (ret < 0)
+			return ret;
+	}
+#endif
+	RTW_INFO("%s\n", __func__);
+	return 0;
+}
+
+
+
+static int rtw_cfg80211_set_wpa_version(struct security_priv *psecuritypriv, u32 wpa_version)
+{
+	RTW_INFO("%s, wpa_version=%d\n", __func__, wpa_version);
+
+	if (!wpa_version) {
+		psecuritypriv->ndisauthtype = Ndis802_11AuthModeOpen;
+		return 0;
+	}
+
+
+	if (wpa_version & (NL80211_WPA_VERSION_1 | NL80211_WPA_VERSION_2))
+		psecuritypriv->ndisauthtype = Ndis802_11AuthModeWPAPSK;
+
+#if 0
+	if (wpa_version & NL80211_WPA_VERSION_2)
+		psecuritypriv->ndisauthtype = Ndis802_11AuthModeWPA2PSK;
+#endif
+
+	#ifdef CONFIG_WAPI_SUPPORT
+	if (wpa_version & NL80211_WAPI_VERSION_1)
+		psecuritypriv->ndisauthtype = Ndis802_11AuthModeWAPI;
+	#endif
+
+	return 0;
+
+}
+
+static int rtw_cfg80211_set_auth_type(struct security_priv *psecuritypriv,
+		enum nl80211_auth_type sme_auth_type)
+{
+	RTW_INFO("%s, nl80211_auth_type=%d\n", __func__, sme_auth_type);
+
+
+	switch (sme_auth_type) {
+	case NL80211_AUTHTYPE_AUTOMATIC:
+
+		psecuritypriv->dot11AuthAlgrthm = dot11AuthAlgrthm_Auto;
+
+		break;
+	case NL80211_AUTHTYPE_OPEN_SYSTEM:
+
+		psecuritypriv->dot11AuthAlgrthm = dot11AuthAlgrthm_Open;
+
+		if (psecuritypriv->ndisauthtype > Ndis802_11AuthModeWPA)
+			psecuritypriv->dot11AuthAlgrthm = dot11AuthAlgrthm_8021X;
+
+#ifdef CONFIG_WAPI_SUPPORT
+		if (psecuritypriv->ndisauthtype == Ndis802_11AuthModeWAPI)
+			psecuritypriv->dot11AuthAlgrthm = dot11AuthAlgrthm_WAPI;
+#endif
+
+		break;
+	case NL80211_AUTHTYPE_SHARED_KEY:
+
+		psecuritypriv->dot11AuthAlgrthm = dot11AuthAlgrthm_Shared;
+
+		psecuritypriv->ndisencryptstatus = Ndis802_11Encryption1Enabled;
+
+
+		break;
+	default:
+		psecuritypriv->dot11AuthAlgrthm = dot11AuthAlgrthm_Open;
+		/* return -ENOTSUPP; */
+	}
+
+	return 0;
+
+}
+
+static int rtw_cfg80211_set_cipher(struct security_priv *psecuritypriv, u32 cipher, bool ucast)
+{
+	u32 ndisencryptstatus = Ndis802_11EncryptionDisabled;
+
+	u32 *profile_cipher = ucast ? &psecuritypriv->dot11PrivacyAlgrthm :
+		&psecuritypriv->dot118021XGrpPrivacy;
+
+	RTW_INFO("%s, ucast=%d, cipher=0x%x\n", __func__, ucast, cipher);
+
+
+	if (!cipher) {
+		*profile_cipher = _NO_PRIVACY_;
+		psecuritypriv->ndisencryptstatus = ndisencryptstatus;
+		return 0;
+	}
+
+	switch (cipher) {
+	case IW_AUTH_CIPHER_NONE:
+		*profile_cipher = _NO_PRIVACY_;
+		ndisencryptstatus = Ndis802_11EncryptionDisabled;
+#ifdef CONFIG_WAPI_SUPPORT
+		if (psecuritypriv->dot11PrivacyAlgrthm == _SMS4_)
+			*profile_cipher = _SMS4_;
+#endif
+		break;
+	case WLAN_CIPHER_SUITE_WEP40:
+		*profile_cipher = _WEP40_;
+		ndisencryptstatus = Ndis802_11Encryption1Enabled;
+		break;
+	case WLAN_CIPHER_SUITE_WEP104:
+		*profile_cipher = _WEP104_;
+		ndisencryptstatus = Ndis802_11Encryption1Enabled;
+		break;
+	case WLAN_CIPHER_SUITE_TKIP:
+		*profile_cipher = _TKIP_;
+		ndisencryptstatus = Ndis802_11Encryption2Enabled;
+		break;
+	case WLAN_CIPHER_SUITE_CCMP:
+		*profile_cipher = _AES_;
+		ndisencryptstatus = Ndis802_11Encryption3Enabled;
+		break;
+#ifdef CONFIG_WAPI_SUPPORT
+	case WLAN_CIPHER_SUITE_SMS4:
+		*profile_cipher = _SMS4_;
+		ndisencryptstatus = Ndis802_11_EncrypteionWAPI;
+		break;
+#endif
+	default:
+		RTW_INFO("Unsupported cipher: 0x%x\n", cipher);
+		return -ENOTSUPP;
+	}
+
+	if (ucast) {
+		psecuritypriv->ndisencryptstatus = ndisencryptstatus;
+
+		/* if(psecuritypriv->dot11PrivacyAlgrthm >= _AES_) */
+		/*	psecuritypriv->ndisauthtype = Ndis802_11AuthModeWPA2PSK; */
+	}
+
+	return 0;
+}
+
+static int rtw_cfg80211_set_key_mgt(struct security_priv *psecuritypriv, u32 key_mgt)
+{
+	RTW_INFO("%s, key_mgt=0x%x\n", __func__, key_mgt);
+
+	if (key_mgt == WLAN_AKM_SUITE_8021X) {
+		/* *auth_type = UMAC_AUTH_TYPE_8021X; */
+		psecuritypriv->dot11AuthAlgrthm = dot11AuthAlgrthm_8021X;
+		psecuritypriv->rsn_akm_suite_type = 1;
+	} else if (key_mgt == WLAN_AKM_SUITE_PSK) {
+		psecuritypriv->dot11AuthAlgrthm = dot11AuthAlgrthm_8021X;
+		psecuritypriv->rsn_akm_suite_type = 2;
+	}
+#ifdef CONFIG_WAPI_SUPPORT
+	else if (key_mgt == WLAN_AKM_SUITE_WAPI_PSK)
+		psecuritypriv->dot11AuthAlgrthm = dot11AuthAlgrthm_WAPI;
+	else if (key_mgt == WLAN_AKM_SUITE_WAPI_CERT)
+		psecuritypriv->dot11AuthAlgrthm = dot11AuthAlgrthm_WAPI;
+#endif
+#ifdef CONFIG_RTW_80211R
+	else if (key_mgt == WLAN_AKM_SUITE_FT_8021X) {
+		psecuritypriv->dot11AuthAlgrthm = dot11AuthAlgrthm_8021X;
+		psecuritypriv->rsn_akm_suite_type = 3;
+	} else if (key_mgt == WLAN_AKM_SUITE_FT_PSK) {
+		psecuritypriv->dot11AuthAlgrthm = dot11AuthAlgrthm_8021X;
+		psecuritypriv->rsn_akm_suite_type = 4;
+	}
+#endif
+	else {
+		RTW_INFO("Invalid key mgt: 0x%x\n", key_mgt);
+		/* return -EINVAL; */
+	}
+
+	return 0;
+}
+
+static int rtw_cfg80211_set_wpa_ie(_adapter *padapter, u8 *pie, size_t ielen)
+{
+	u8 *buf = NULL, *pos = NULL;
+	int group_cipher = 0, pairwise_cipher = 0;
+	u8 mfp_opt = MFP_NO;
+	int ret = 0;
+	int wpa_ielen = 0;
+	int wpa2_ielen = 0;
+	u8 *pwpa, *pwpa2;
+	u8 null_addr[] = {0, 0, 0, 0, 0, 0};
+
+	if (pie == NULL || !ielen) {
+		/* Treat this as normal case, but need to clear WIFI_UNDER_WPS */
+		_clr_fwstate_(&padapter->mlmepriv, WIFI_UNDER_WPS);
+		goto exit;
+	}
+
+	if (ielen > MAX_WPA_IE_LEN + MAX_WPS_IE_LEN + MAX_P2P_IE_LEN) {
+		ret = -EINVAL;
+		goto exit;
+	}
+
+	buf = rtw_zmalloc(ielen);
+	if (buf == NULL) {
+		ret =  -ENOMEM;
+		goto exit;
+	}
+
+	_rtw_memcpy(buf, pie , ielen);
+
+	RTW_INFO("set wpa_ie(length:%zu):\n", ielen);
+	RTW_INFO_DUMP(NULL, buf, ielen);
+
+	pos = buf;
+	if (ielen < RSN_HEADER_LEN) {
+		ret  = -1;
+		goto exit;
+	}
+
+	pwpa = rtw_get_wpa_ie(buf, &wpa_ielen, ielen);
+	if (pwpa && wpa_ielen > 0) {
+		if (rtw_parse_wpa_ie(pwpa, wpa_ielen + 2, &group_cipher, &pairwise_cipher, NULL) == _SUCCESS) {
+			padapter->securitypriv.dot11AuthAlgrthm = dot11AuthAlgrthm_8021X;
+			padapter->securitypriv.ndisauthtype = Ndis802_11AuthModeWPAPSK;
+			_rtw_memcpy(padapter->securitypriv.supplicant_ie, &pwpa[0], wpa_ielen + 2);
+
+			RTW_INFO("got wpa_ie, wpa_ielen:%u\n", wpa_ielen);
+		}
+	}
+
+	pwpa2 = rtw_get_wpa2_ie(buf, &wpa2_ielen, ielen);
+	if (pwpa2 && wpa2_ielen > 0) {
+		if (rtw_parse_wpa2_ie(pwpa2, wpa2_ielen + 2, &group_cipher, &pairwise_cipher, NULL, &mfp_opt) == _SUCCESS) {
+			padapter->securitypriv.dot11AuthAlgrthm = dot11AuthAlgrthm_8021X;
+			padapter->securitypriv.ndisauthtype = Ndis802_11AuthModeWPA2PSK;
+			_rtw_memcpy(padapter->securitypriv.supplicant_ie, &pwpa2[0], wpa2_ielen + 2);
+
+			RTW_INFO("got wpa2_ie, wpa2_ielen:%u\n", wpa2_ielen);
+		}
+	}
+
+	if (group_cipher == 0)
+		group_cipher = WPA_CIPHER_NONE;
+	if (pairwise_cipher == 0)
+		pairwise_cipher = WPA_CIPHER_NONE;
+
+	switch (group_cipher) {
+	case WPA_CIPHER_NONE:
+		padapter->securitypriv.dot118021XGrpPrivacy = _NO_PRIVACY_;
+		padapter->securitypriv.ndisencryptstatus = Ndis802_11EncryptionDisabled;
+		break;
+	case WPA_CIPHER_WEP40:
+		padapter->securitypriv.dot118021XGrpPrivacy = _WEP40_;
+		padapter->securitypriv.ndisencryptstatus = Ndis802_11Encryption1Enabled;
+		break;
+	case WPA_CIPHER_TKIP:
+		padapter->securitypriv.dot118021XGrpPrivacy = _TKIP_;
+		padapter->securitypriv.ndisencryptstatus = Ndis802_11Encryption2Enabled;
+		break;
+	case WPA_CIPHER_CCMP:
+		padapter->securitypriv.dot118021XGrpPrivacy = _AES_;
+		padapter->securitypriv.ndisencryptstatus = Ndis802_11Encryption3Enabled;
+		break;
+	case WPA_CIPHER_WEP104:
+		padapter->securitypriv.dot118021XGrpPrivacy = _WEP104_;
+		padapter->securitypriv.ndisencryptstatus = Ndis802_11Encryption1Enabled;
+		break;
+	}
+
+	switch (pairwise_cipher) {
+	case WPA_CIPHER_NONE:
+		padapter->securitypriv.dot11PrivacyAlgrthm = _NO_PRIVACY_;
+		padapter->securitypriv.ndisencryptstatus = Ndis802_11EncryptionDisabled;
+		break;
+	case WPA_CIPHER_WEP40:
+		padapter->securitypriv.dot11PrivacyAlgrthm = _WEP40_;
+		padapter->securitypriv.ndisencryptstatus = Ndis802_11Encryption1Enabled;
+		break;
+	case WPA_CIPHER_TKIP:
+		padapter->securitypriv.dot11PrivacyAlgrthm = _TKIP_;
+		padapter->securitypriv.ndisencryptstatus = Ndis802_11Encryption2Enabled;
+		break;
+	case WPA_CIPHER_CCMP:
+		padapter->securitypriv.dot11PrivacyAlgrthm = _AES_;
+		padapter->securitypriv.ndisencryptstatus = Ndis802_11Encryption3Enabled;
+		break;
+	case WPA_CIPHER_WEP104:
+		padapter->securitypriv.dot11PrivacyAlgrthm = _WEP104_;
+		padapter->securitypriv.ndisencryptstatus = Ndis802_11Encryption1Enabled;
+		break;
+	}
+
+	if (mfp_opt == MFP_INVALID) {
+		RTW_INFO(FUNC_ADPT_FMT" invalid MFP setting\n", FUNC_ADPT_ARG(padapter));
+		ret = -EINVAL;
+		goto exit;
+	}
+	padapter->securitypriv.mfp_opt = mfp_opt;
+
+	{/* handle wps_ie */
+		uint wps_ielen;
+		u8 *wps_ie;
+
+		wps_ie = rtw_get_wps_ie(buf, ielen, NULL, &wps_ielen);
+		if (wps_ie && wps_ielen > 0) {
+			RTW_INFO("got wps_ie, wps_ielen:%u\n", wps_ielen);
+			padapter->securitypriv.wps_ie_len = wps_ielen < MAX_WPS_IE_LEN ? wps_ielen : MAX_WPS_IE_LEN;
+			_rtw_memcpy(padapter->securitypriv.wps_ie, wps_ie, padapter->securitypriv.wps_ie_len);
+			set_fwstate(&padapter->mlmepriv, WIFI_UNDER_WPS);
+		} else
+			_clr_fwstate_(&padapter->mlmepriv, WIFI_UNDER_WPS);
+	}
+
+	#ifdef CONFIG_P2P
+	{/* check p2p_ie for assoc req; */
+		uint p2p_ielen = 0;
+		u8 *p2p_ie;
+		struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
+
+		p2p_ie = rtw_get_p2p_ie(buf, ielen, NULL, &p2p_ielen);
+		if (p2p_ie) {
+			#ifdef CONFIG_DEBUG_CFG80211
+			RTW_INFO("%s p2p_assoc_req_ielen=%d\n", __FUNCTION__, p2p_ielen);
+			#endif
+
+			if (pmlmepriv->p2p_assoc_req_ie) {
+				u32 free_len = pmlmepriv->p2p_assoc_req_ie_len;
+				pmlmepriv->p2p_assoc_req_ie_len = 0;
+				rtw_mfree(pmlmepriv->p2p_assoc_req_ie, free_len);
+				pmlmepriv->p2p_assoc_req_ie = NULL;
+			}
+
+			pmlmepriv->p2p_assoc_req_ie = rtw_malloc(p2p_ielen);
+			if (pmlmepriv->p2p_assoc_req_ie == NULL) {
+				RTW_INFO("%s()-%d: rtw_malloc() ERROR!\n", __FUNCTION__, __LINE__);
+				goto exit;
+			}
+			_rtw_memcpy(pmlmepriv->p2p_assoc_req_ie, p2p_ie, p2p_ielen);
+			pmlmepriv->p2p_assoc_req_ie_len = p2p_ielen;
+		}
+	}
+	#endif /* CONFIG_P2P */
+
+	#ifdef CONFIG_WFD
+	{
+		uint wfd_ielen = 0;
+		u8 *wfd_ie;
+		struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
+
+		wfd_ie = rtw_get_wfd_ie(buf, ielen, NULL, &wfd_ielen);
+		if (wfd_ie) {
+			#ifdef CONFIG_DEBUG_CFG80211
+			RTW_INFO("%s wfd_assoc_req_ielen=%d\n", __FUNCTION__, wfd_ielen);
+			#endif
+
+			if (rtw_mlme_update_wfd_ie_data(pmlmepriv, MLME_ASSOC_REQ_IE, wfd_ie, wfd_ielen) != _SUCCESS)
+				goto exit;
+		}
+	}
+	#endif /* CONFIG_WFD */
+
+	/* TKIP and AES disallow multicast packets until installing group key */
+	if (padapter->securitypriv.dot11PrivacyAlgrthm == _TKIP_
+		|| padapter->securitypriv.dot11PrivacyAlgrthm == _TKIP_WTMIC_
+		|| padapter->securitypriv.dot11PrivacyAlgrthm == _AES_)
+		/* WPS open need to enable multicast */
+		/* || check_fwstate(&padapter->mlmepriv, WIFI_UNDER_WPS) == _TRUE) */
+		rtw_hal_set_hwreg(padapter, HW_VAR_OFF_RCR_AM, null_addr);
+
+
+exit:
+	if (buf)
+		rtw_mfree(buf, ielen);
+	if (ret)
+		_clr_fwstate_(&padapter->mlmepriv, WIFI_UNDER_WPS);
+
+	return ret;
+}
+
+static int cfg80211_rtw_join_ibss(struct wiphy *wiphy, struct net_device *ndev,
+				  struct cfg80211_ibss_params *params)
+{
+	_adapter *padapter = (_adapter *)rtw_netdev_priv(ndev);
+	NDIS_802_11_SSID ndis_ssid;
+	struct security_priv *psecuritypriv = &padapter->securitypriv;
+	struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 8, 0))
+	struct cfg80211_chan_def *pch_def;
+#endif
+	struct ieee80211_channel *pch;
+	int ret = 0;
+
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 8, 0))
+	pch_def = (struct cfg80211_chan_def *)(&params->chandef);
+	pch = (struct ieee80211_channel *) pch_def->chan;
+#elif (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 31))
+	pch = (struct ieee80211_channel *)(params->channel);
+#endif
+
+	if (!params->ssid || !params->ssid_len) {
+		ret = -EINVAL;
+		goto exit;
+	}
+
+	if (params->ssid_len > IW_ESSID_MAX_SIZE) {
+		ret = -E2BIG;
+		goto exit;
+	}
+
+	rtw_ps_deny(padapter, PS_DENY_JOIN);
+	if (_FAIL == rtw_pwr_wakeup(padapter)) {
+		ret = -EPERM;
+		goto cancel_ps_deny;
+	}
+
+#ifdef CONFIG_CONCURRENT_MODE
+	if (rtw_mi_buddy_check_fwstate(padapter, _FW_UNDER_LINKING)) {
+		RTW_INFO("%s, but buddy_intf is under linking\n", __FUNCTION__);
+		ret = -EINVAL;
+		goto cancel_ps_deny;
+	}
+	rtw_mi_buddy_scan_abort(padapter, _TRUE); /* OR rtw_mi_scan_abort(padapter, _TRUE);*/
+#endif /*CONFIG_CONCURRENT_MODE*/
+
+
+	_rtw_memset(&ndis_ssid, 0, sizeof(NDIS_802_11_SSID));
+	ndis_ssid.SsidLength = params->ssid_len;
+	_rtw_memcpy(ndis_ssid.Ssid, (u8 *)params->ssid, params->ssid_len);
+
+	/* RTW_INFO("ssid=%s, len=%zu\n", ndis_ssid.Ssid, params->ssid_len); */
+
+	psecuritypriv->ndisencryptstatus = Ndis802_11EncryptionDisabled;
+	psecuritypriv->dot11PrivacyAlgrthm = _NO_PRIVACY_;
+	psecuritypriv->dot118021XGrpPrivacy = _NO_PRIVACY_;
+	psecuritypriv->dot11AuthAlgrthm = dot11AuthAlgrthm_Open; /* open system */
+	psecuritypriv->ndisauthtype = Ndis802_11AuthModeOpen;
+
+	ret = rtw_cfg80211_set_auth_type(psecuritypriv, NL80211_AUTHTYPE_OPEN_SYSTEM);
+	rtw_set_802_11_authentication_mode(padapter, psecuritypriv->ndisauthtype);
+
+	RTW_INFO("%s: center_freq = %d\n", __func__, pch->center_freq);
+	pmlmeext->cur_channel = rtw_freq2ch(pch->center_freq);
+
+	if (rtw_set_802_11_ssid(padapter, &ndis_ssid) == _FALSE) {
+		ret = -1;
+		goto cancel_ps_deny;
+	}
+
+cancel_ps_deny:
+	rtw_ps_deny_cancel(padapter, PS_DENY_JOIN);
+exit:
+	return ret;
+}
+
+static int cfg80211_rtw_leave_ibss(struct wiphy *wiphy, struct net_device *ndev)
+{
+	_adapter *padapter = (_adapter *)rtw_netdev_priv(ndev);
+	struct wireless_dev *rtw_wdev = padapter->rtw_wdev;
+	enum nl80211_iftype old_type;
+	int ret = 0;
+
+	RTW_INFO(FUNC_NDEV_FMT"\n", FUNC_NDEV_ARG(ndev));
+
+#if (RTW_CFG80211_BLOCK_STA_DISCON_EVENT & RTW_CFG80211_BLOCK_DISCON_WHEN_DISCONNECT)
+	rtw_wdev_set_not_indic_disco(adapter_wdev_data(padapter), 1);
+#endif
+
+	old_type = rtw_wdev->iftype;
+
+	rtw_set_to_roam(padapter, 0);
+
+	if (check_fwstate(&padapter->mlmepriv, _FW_LINKED)) {
+		rtw_scan_abort(padapter);
+		LeaveAllPowerSaveMode(padapter);
+
+		rtw_wdev->iftype = NL80211_IFTYPE_STATION;
+
+		if (rtw_set_802_11_infrastructure_mode(padapter, Ndis802_11Infrastructure) == _FALSE) {
+			rtw_wdev->iftype = old_type;
+			ret = -EPERM;
+			goto leave_ibss;
+		}
+		rtw_setopmode_cmd(padapter, Ndis802_11Infrastructure, RTW_CMDF_WAIT_ACK);
+	}
+
+leave_ibss:
+#if (RTW_CFG80211_BLOCK_STA_DISCON_EVENT & RTW_CFG80211_BLOCK_DISCON_WHEN_DISCONNECT)
+	rtw_wdev_set_not_indic_disco(adapter_wdev_data(padapter), 0);
+#endif
+
+	return 0;
+}
+
+bool rtw_cfg80211_is_connect_requested(_adapter *adapter)
+{
+	struct rtw_wdev_priv *pwdev_priv = adapter_wdev_data(adapter);
+	_irqL irqL;
+	bool requested;
+
+	_enter_critical_bh(&pwdev_priv->connect_req_lock, &irqL);
+	requested = pwdev_priv->connect_req ? 1 : 0;
+	_exit_critical_bh(&pwdev_priv->connect_req_lock, &irqL);
+
+	return requested;
+}
+
+static int _rtw_disconnect(struct wiphy *wiphy, struct net_device *ndev)
+{
+	_adapter *padapter = (_adapter *)rtw_netdev_priv(ndev);
+
+
+	/* if(check_fwstate(&padapter->mlmepriv, _FW_LINKED)) */
+	{
+		rtw_scan_abort(padapter);
+		rtw_join_abort_timeout(padapter, 300);
+		LeaveAllPowerSaveMode(padapter);
+		rtw_disassoc_cmd(padapter, 500, RTW_CMDF_WAIT_ACK);
+#ifdef CONFIG_RTW_REPEATER_SON
+		rtw_rson_do_disconnect(padapter);
+#endif
+		RTW_INFO("%s...call rtw_indicate_disconnect\n", __func__);
+
+		rtw_free_assoc_resources_cmd(padapter, _TRUE, RTW_CMDF_WAIT_ACK);
+
+		/* indicate locally_generated = 0 when suspend */
+		#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 2, 0))
+		rtw_indicate_disconnect(padapter, 0, wiphy->dev.power.is_prepared ? _FALSE : _TRUE);
+		#else
+		/*
+		* for kernel < 4.2, DISCONNECT event is hardcoded with
+		* NL80211_ATTR_DISCONNECTED_BY_AP=1 in NL80211 layer
+		* no need to judge if under suspend
+		*/
+		rtw_indicate_disconnect(padapter, 0, _TRUE);
+		#endif
+
+		rtw_pwr_wakeup(padapter);
+	}
+	return 0;
+}
+
+static int cfg80211_rtw_connect(struct wiphy *wiphy, struct net_device *ndev,
+				struct cfg80211_connect_params *sme)
+{
+	int ret = 0;
+	NDIS_802_11_AUTHENTICATION_MODE authmode;
+	NDIS_802_11_SSID ndis_ssid;
+	/* u8 matched_by_bssid=_FALSE; */
+	/* u8 matched_by_ssid=_FALSE; */
+	_adapter *padapter = (_adapter *)rtw_netdev_priv(ndev);
+	struct security_priv *psecuritypriv = &padapter->securitypriv;
+	struct rtw_wdev_priv *pwdev_priv = adapter_wdev_data(padapter);
+	struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
+	_irqL irqL;
+
+#if (RTW_CFG80211_BLOCK_STA_DISCON_EVENT & RTW_CFG80211_BLOCK_DISCON_WHEN_CONNECT)
+	rtw_wdev_set_not_indic_disco(pwdev_priv, 1);
+#endif
+
+	RTW_INFO("=>"FUNC_NDEV_FMT" - Start to Connection\n", FUNC_NDEV_ARG(ndev));
+	RTW_INFO("privacy=%d, key=%p, key_len=%d, key_idx=%d, auth_type=%d\n",
+		sme->privacy, sme->key, sme->key_len, sme->key_idx, sme->auth_type);
+
+	if (pwdev_priv->block == _TRUE) {
+		ret = -EBUSY;
+		RTW_INFO("%s wdev_priv.block is set\n", __FUNCTION__);
+		goto exit;
+	}
+
+       if (check_fwstate(pmlmepriv, _FW_LINKED | _FW_UNDER_LINKING) == _TRUE) {
+
+		_rtw_disconnect(wiphy, ndev);
+		RTW_INFO("%s disconnect before connecting! fw_state=0x%x\n",
+			__FUNCTION__, pmlmepriv->fw_state);
+	}
+
+#ifdef CONFIG_PLATFORM_MSTAR_SCAN_BEFORE_CONNECT
+	printk("MStar Android!\n");
+	if (pwdev_priv->bandroid_scan == _FALSE) {
+#ifdef CONFIG_P2P
+		struct wifidirect_info *pwdinfo = &(padapter->wdinfo);
+		if (rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE))
+#endif /* CONFIG_P2P */
+		{
+			ret = -EBUSY;
+			printk("Android hasn't attached yet!\n");
+			goto exit;
+		}
+	}
+#endif
+
+	if (!sme->ssid || !sme->ssid_len) {
+		ret = -EINVAL;
+		goto exit;
+	}
+
+	if (sme->ssid_len > IW_ESSID_MAX_SIZE) {
+		ret = -E2BIG;
+		goto exit;
+	}
+
+	rtw_ps_deny(padapter, PS_DENY_JOIN);
+	if (_FAIL == rtw_pwr_wakeup(padapter)) {
+		ret = -EPERM;
+		goto cancel_ps_deny;
+	}
+
+	rtw_mi_scan_abort(padapter, _TRUE);
+
+	rtw_join_abort_timeout(padapter, 300);
+#ifdef CONFIG_CONCURRENT_MODE
+	if (rtw_mi_buddy_check_fwstate(padapter, _FW_UNDER_LINKING)) {
+		ret = -EINVAL;
+		goto cancel_ps_deny;
+	}
+#endif
+
+	_rtw_memset(&ndis_ssid, 0, sizeof(NDIS_802_11_SSID));
+	ndis_ssid.SsidLength = sme->ssid_len;
+	_rtw_memcpy(ndis_ssid.Ssid, (u8 *)sme->ssid, sme->ssid_len);
+
+	RTW_INFO("ssid=%s, len=%zu\n", ndis_ssid.Ssid, sme->ssid_len);
+
+
+	if (sme->bssid)
+		RTW_INFO("bssid="MAC_FMT"\n", MAC_ARG(sme->bssid));
+
+
+	psecuritypriv->ndisencryptstatus = Ndis802_11EncryptionDisabled;
+	psecuritypriv->dot11PrivacyAlgrthm = _NO_PRIVACY_;
+	psecuritypriv->dot118021XGrpPrivacy = _NO_PRIVACY_;
+	psecuritypriv->dot11AuthAlgrthm = dot11AuthAlgrthm_Open; /* open system */
+	psecuritypriv->ndisauthtype = Ndis802_11AuthModeOpen;
+
+#ifdef CONFIG_WAPI_SUPPORT
+	padapter->wapiInfo.bWapiEnable = false;
+#endif
+
+	ret = rtw_cfg80211_set_wpa_version(psecuritypriv, sme->crypto.wpa_versions);
+	if (ret < 0)
+		goto cancel_ps_deny;
+
+#ifdef CONFIG_WAPI_SUPPORT
+	if (sme->crypto.wpa_versions & NL80211_WAPI_VERSION_1) {
+		padapter->wapiInfo.bWapiEnable = true;
+		padapter->wapiInfo.extra_prefix_len = WAPI_EXT_LEN;
+		padapter->wapiInfo.extra_postfix_len = SMS4_MIC_LEN;
+	}
+#endif
+
+	ret = rtw_cfg80211_set_auth_type(psecuritypriv, sme->auth_type);
+
+#ifdef CONFIG_WAPI_SUPPORT
+	if (psecuritypriv->dot11AuthAlgrthm == dot11AuthAlgrthm_WAPI)
+		padapter->mlmeextpriv.mlmext_info.auth_algo = psecuritypriv->dot11AuthAlgrthm;
+#endif
+
+
+	if (ret < 0)
+		goto cancel_ps_deny;
+
+	RTW_INFO("%s, ie_len=%zu\n", __func__, sme->ie_len);
+
+	ret = rtw_cfg80211_set_wpa_ie(padapter, (u8 *)sme->ie, sme->ie_len);
+	if (ret < 0)
+		goto cancel_ps_deny;
+
+	if (sme->crypto.n_ciphers_pairwise) {
+		ret = rtw_cfg80211_set_cipher(psecuritypriv, sme->crypto.ciphers_pairwise[0], _TRUE);
+		if (ret < 0)
+			goto cancel_ps_deny;
+	}
+
+	/* For WEP Shared auth */
+	if (sme->key_len > 0 && sme->key) {
+		u32 wep_key_idx, wep_key_len, wep_total_len;
+		NDIS_802_11_WEP	*pwep = NULL;
+		RTW_INFO("%s(): Shared/Auto WEP\n", __FUNCTION__);
+
+		wep_key_idx = sme->key_idx;
+		wep_key_len = sme->key_len;
+
+		if (sme->key_idx > WEP_KEYS) {
+			ret = -EINVAL;
+			goto cancel_ps_deny;
+		}
+
+		if (wep_key_len > 0) {
+			wep_key_len = wep_key_len <= 5 ? 5 : 13;
+			wep_total_len = wep_key_len + FIELD_OFFSET(NDIS_802_11_WEP, KeyMaterial);
+			pwep = (NDIS_802_11_WEP *) rtw_malloc(wep_total_len);
+			if (pwep == NULL) {
+				RTW_INFO(" wpa_set_encryption: pwep allocate fail !!!\n");
+				ret = -ENOMEM;
+				goto cancel_ps_deny;
+			}
+
+			_rtw_memset(pwep, 0, wep_total_len);
+
+			pwep->KeyLength = wep_key_len;
+			pwep->Length = wep_total_len;
+
+			if (wep_key_len == 13) {
+				padapter->securitypriv.dot11PrivacyAlgrthm = _WEP104_;
+				padapter->securitypriv.dot118021XGrpPrivacy = _WEP104_;
+			}
+		} else {
+			ret = -EINVAL;
+			goto cancel_ps_deny;
+		}
+
+		pwep->KeyIndex = wep_key_idx;
+		pwep->KeyIndex |= 0x80000000;
+
+		_rtw_memcpy(pwep->KeyMaterial, (void *)sme->key, pwep->KeyLength);
+
+		if (rtw_set_802_11_add_wep(padapter, pwep) == (u8)_FAIL)
+			ret = -EOPNOTSUPP ;
+
+		if (pwep)
+			rtw_mfree((u8 *)pwep, wep_total_len);
+
+		if (ret < 0)
+			goto cancel_ps_deny;
+	}
+
+	ret = rtw_cfg80211_set_cipher(psecuritypriv, sme->crypto.cipher_group, _FALSE);
+	if (ret < 0)
+		return ret;
+
+	if (sme->crypto.n_akm_suites) {
+		ret = rtw_cfg80211_set_key_mgt(psecuritypriv, sme->crypto.akm_suites[0]);
+		if (ret < 0)
+			goto cancel_ps_deny;
+	}
+#ifdef CONFIG_8011R
+	else {
+		/*It could be a connection without RSN IEs*/
+		psecuritypriv->rsn_akm_suite_type = 0;
+	}
+#endif
+
+#ifdef CONFIG_WAPI_SUPPORT
+	if (sme->crypto.akm_suites[0] == WLAN_AKM_SUITE_WAPI_PSK)
+		padapter->wapiInfo.bWapiPSK = true;
+	else if (sme->crypto.akm_suites[0] == WLAN_AKM_SUITE_WAPI_CERT)
+		padapter->wapiInfo.bWapiPSK = false;
+#endif
+
+	authmode = psecuritypriv->ndisauthtype;
+	rtw_set_802_11_authentication_mode(padapter, authmode);
+
+	/* rtw_set_802_11_encryption_mode(padapter, padapter->securitypriv.ndisencryptstatus); */
+
+	if (rtw_set_802_11_connect(padapter, (u8 *)sme->bssid, &ndis_ssid) == _FALSE) {
+		ret = -1;
+		goto cancel_ps_deny;
+	}
+
+
+	_enter_critical_bh(&pwdev_priv->connect_req_lock, &irqL);
+
+	if (pwdev_priv->connect_req) {
+		rtw_wdev_free_connect_req(pwdev_priv);
+		RTW_INFO(FUNC_NDEV_FMT" free existing connect_req\n", FUNC_NDEV_ARG(ndev));
+	}
+
+	pwdev_priv->connect_req = (struct cfg80211_connect_params *)rtw_malloc(sizeof(*pwdev_priv->connect_req));
+	if (pwdev_priv->connect_req)
+		_rtw_memcpy(pwdev_priv->connect_req, sme, sizeof(*pwdev_priv->connect_req));
+	else
+		RTW_WARN(FUNC_NDEV_FMT" alloc connect_req fail\n", FUNC_NDEV_ARG(ndev));
+
+	_exit_critical_bh(&pwdev_priv->connect_req_lock, &irqL);
+
+	RTW_INFO("set ssid:dot11AuthAlgrthm=%d, dot11PrivacyAlgrthm=%d, dot118021XGrpPrivacy=%d\n", psecuritypriv->dot11AuthAlgrthm, psecuritypriv->dot11PrivacyAlgrthm,
+		psecuritypriv->dot118021XGrpPrivacy);
+
+cancel_ps_deny:
+	rtw_ps_deny_cancel(padapter, PS_DENY_JOIN);
+
+exit:
+	RTW_INFO("<=%s, ret %d\n", __FUNCTION__, ret);
+
+#if (RTW_CFG80211_BLOCK_STA_DISCON_EVENT & RTW_CFG80211_BLOCK_DISCON_WHEN_CONNECT)
+	rtw_wdev_set_not_indic_disco(pwdev_priv, 0);
+#endif
+
+	return ret;
+}
+
+static int cfg80211_rtw_disconnect(struct wiphy *wiphy, struct net_device *ndev,
+				   u16 reason_code)
+{
+	_adapter *padapter = (_adapter *)rtw_netdev_priv(ndev);
+
+	RTW_INFO(FUNC_NDEV_FMT" - Start to Disconnect\n", FUNC_NDEV_ARG(ndev));
+
+#if (RTW_CFG80211_BLOCK_STA_DISCON_EVENT & RTW_CFG80211_BLOCK_DISCON_WHEN_DISCONNECT)
+	#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 11, 0))
+	if (!wiphy->dev.power.is_prepared)
+	#endif
+		rtw_wdev_set_not_indic_disco(adapter_wdev_data(padapter), 1);
+#endif
+
+	rtw_set_to_roam(padapter, 0);
+
+	/* if(check_fwstate(&padapter->mlmepriv, _FW_LINKED)) */
+	{
+		_rtw_disconnect(wiphy, ndev);
+	}
+
+#if (RTW_CFG80211_BLOCK_STA_DISCON_EVENT & RTW_CFG80211_BLOCK_DISCON_WHEN_DISCONNECT)
+	rtw_wdev_set_not_indic_disco(adapter_wdev_data(padapter), 0);
+#endif
+
+	RTW_INFO(FUNC_NDEV_FMT" return 0\n", FUNC_NDEV_ARG(ndev));
+	return 0;
+}
+
+static int cfg80211_rtw_set_txpower(struct wiphy *wiphy,
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 8, 0))
+	struct wireless_dev *wdev,
+#endif
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 36)) || defined(COMPAT_KERNEL_RELEASE)
+	enum nl80211_tx_power_setting type, int mbm)
+#else
+	enum tx_power_setting type, int dbm)
+#endif
+{
+#if 0
+	struct iwm_priv *iwm = wiphy_to_iwm(wiphy);
+	int ret;
+
+	switch (type) {
+	case NL80211_TX_POWER_AUTOMATIC:
+		return 0;
+	case NL80211_TX_POWER_FIXED:
+		if (mbm < 0 || (mbm % 100))
+			return -EOPNOTSUPP;
+
+		if (!test_bit(IWM_STATUS_READY, &iwm->status))
+			return 0;
+
+		ret = iwm_umac_set_config_fix(iwm, UMAC_PARAM_TBL_CFG_FIX,
+					      CFG_TX_PWR_LIMIT_USR,
+					      MBM_TO_DBM(mbm) * 2);
+		if (ret < 0)
+			return ret;
+
+		return iwm_tx_power_trigger(iwm);
+	default:
+		IWM_ERR(iwm, "Unsupported power type: %d\n", type);
+		return -EOPNOTSUPP;
+	}
+#endif
+	RTW_INFO("%s\n", __func__);
+	return 0;
+}
+
+static int cfg80211_rtw_get_txpower(struct wiphy *wiphy,
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 8, 0))
+	struct wireless_dev *wdev,
+#endif
+	int *dbm)
+{
+	RTW_INFO("%s\n", __func__);
+
+	*dbm = (12);
+
+	return 0;
+}
+
+inline bool rtw_cfg80211_pwr_mgmt(_adapter *adapter)
+{
+	struct rtw_wdev_priv *rtw_wdev_priv = adapter_wdev_data(adapter);
+	return rtw_wdev_priv->power_mgmt;
+}
+
+static int cfg80211_rtw_set_power_mgmt(struct wiphy *wiphy,
+				       struct net_device *ndev,
+				       bool enabled, int timeout)
+{
+	_adapter *padapter = (_adapter *)rtw_netdev_priv(ndev);
+	struct rtw_wdev_priv *rtw_wdev_priv = adapter_wdev_data(padapter);
+
+	RTW_INFO(FUNC_NDEV_FMT" enabled:%u, timeout:%d\n", FUNC_NDEV_ARG(ndev),
+		enabled, timeout);
+
+	rtw_wdev_priv->power_mgmt = enabled;
+
+#ifdef CONFIG_LPS
+	if (!enabled)
+		rtw_lps_ctrl_wk_cmd(padapter, LPS_CTRL_LEAVE_CFG80211_PWRMGMT, 1);
+#endif
+
+	return 0;
+}
+
+static int cfg80211_rtw_set_pmksa(struct wiphy *wiphy,
+				  struct net_device *ndev,
+				  struct cfg80211_pmksa *pmksa)
+{
+	u8	index, blInserted = _FALSE;
+	_adapter *padapter = (_adapter *)rtw_netdev_priv(ndev);
+	struct mlme_priv *mlme = &padapter->mlmepriv;
+	struct security_priv	*psecuritypriv = &padapter->securitypriv;
+	u8	strZeroMacAddress[ETH_ALEN] = { 0x00 };
+
+	RTW_INFO(FUNC_NDEV_FMT" "MAC_FMT" "KEY_FMT"\n", FUNC_NDEV_ARG(ndev)
+		, MAC_ARG(pmksa->bssid), KEY_ARG(pmksa->pmkid));
+
+	if (_rtw_memcmp((u8 *)pmksa->bssid, strZeroMacAddress, ETH_ALEN) == _TRUE)
+		return -EINVAL;
+
+	if (check_fwstate(mlme, _FW_LINKED) == _FALSE) {
+		RTW_INFO(FUNC_NDEV_FMT" not set pmksa cause not in linked state\n", FUNC_NDEV_ARG(ndev));
+		return -EINVAL;
+	}
+
+	blInserted = _FALSE;
+
+	/* overwrite PMKID */
+	for (index = 0 ; index < NUM_PMKID_CACHE; index++) {
+		if (_rtw_memcmp(psecuritypriv->PMKIDList[index].Bssid, (u8 *)pmksa->bssid, ETH_ALEN) == _TRUE) {
+			/* BSSID is matched, the same AP => rewrite with new PMKID. */
+			RTW_INFO(FUNC_NDEV_FMT" BSSID exists in the PMKList.\n", FUNC_NDEV_ARG(ndev));
+
+			_rtw_memcpy(psecuritypriv->PMKIDList[index].PMKID, (u8 *)pmksa->pmkid, WLAN_PMKID_LEN);
+			psecuritypriv->PMKIDList[index].bUsed = _TRUE;
+			psecuritypriv->PMKIDIndex = index + 1;
+			blInserted = _TRUE;
+			break;
+		}
+	}
+
+	if (!blInserted) {
+		/* Find a new entry */
+		RTW_INFO(FUNC_NDEV_FMT" Use the new entry index = %d for this PMKID.\n",
+			FUNC_NDEV_ARG(ndev), psecuritypriv->PMKIDIndex);
+
+		_rtw_memcpy(psecuritypriv->PMKIDList[psecuritypriv->PMKIDIndex].Bssid, (u8 *)pmksa->bssid, ETH_ALEN);
+		_rtw_memcpy(psecuritypriv->PMKIDList[psecuritypriv->PMKIDIndex].PMKID, (u8 *)pmksa->pmkid, WLAN_PMKID_LEN);
+
+		psecuritypriv->PMKIDList[psecuritypriv->PMKIDIndex].bUsed = _TRUE;
+		psecuritypriv->PMKIDIndex++ ;
+		if (psecuritypriv->PMKIDIndex == 16)
+			psecuritypriv->PMKIDIndex = 0;
+	}
+
+	return 0;
+}
+
+static int cfg80211_rtw_del_pmksa(struct wiphy *wiphy,
+				  struct net_device *ndev,
+				  struct cfg80211_pmksa *pmksa)
+{
+	u8	index, bMatched = _FALSE;
+	_adapter *padapter = (_adapter *)rtw_netdev_priv(ndev);
+	struct security_priv	*psecuritypriv = &padapter->securitypriv;
+
+	RTW_INFO(FUNC_NDEV_FMT" "MAC_FMT" "KEY_FMT"\n", FUNC_NDEV_ARG(ndev)
+		, MAC_ARG(pmksa->bssid), KEY_ARG(pmksa->pmkid));
+
+	for (index = 0 ; index < NUM_PMKID_CACHE; index++) {
+		if (_rtw_memcmp(psecuritypriv->PMKIDList[index].Bssid, (u8 *)pmksa->bssid, ETH_ALEN) == _TRUE) {
+			/* BSSID is matched, the same AP => Remove this PMKID information and reset it. */
+			_rtw_memset(psecuritypriv->PMKIDList[index].Bssid, 0x00, ETH_ALEN);
+			_rtw_memset(psecuritypriv->PMKIDList[index].PMKID, 0x00, WLAN_PMKID_LEN);
+			psecuritypriv->PMKIDList[index].bUsed = _FALSE;
+			bMatched = _TRUE;
+			RTW_INFO(FUNC_NDEV_FMT" clear id:%hhu\n", FUNC_NDEV_ARG(ndev), index);
+			break;
+		}
+	}
+
+	if (_FALSE == bMatched) {
+		RTW_INFO(FUNC_NDEV_FMT" do not have matched BSSID\n"
+			, FUNC_NDEV_ARG(ndev));
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+static int cfg80211_rtw_flush_pmksa(struct wiphy *wiphy,
+				    struct net_device *ndev)
+{
+	_adapter *padapter = (_adapter *)rtw_netdev_priv(ndev);
+	struct security_priv	*psecuritypriv = &padapter->securitypriv;
+
+	RTW_INFO(FUNC_NDEV_FMT"\n", FUNC_NDEV_ARG(ndev));
+
+	_rtw_memset(&psecuritypriv->PMKIDList[0], 0x00, sizeof(RT_PMKID_LIST) * NUM_PMKID_CACHE);
+	psecuritypriv->PMKIDIndex = 0;
+
+	return 0;
+}
+
+#ifdef CONFIG_AP_MODE
+void rtw_cfg80211_indicate_sta_assoc(_adapter *padapter, u8 *pmgmt_frame, uint frame_len)
+{
+#if !defined(RTW_USE_CFG80211_STA_EVENT) && !defined(COMPAT_KERNEL_RELEASE)
+	s32 freq;
+	int channel;
+	struct wireless_dev *pwdev = padapter->rtw_wdev;
+	struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv);
+#endif
+	struct net_device *ndev = padapter->pnetdev;
+
+	RTW_INFO(FUNC_ADPT_FMT"\n", FUNC_ADPT_ARG(padapter));
+
+#if defined(RTW_USE_CFG80211_STA_EVENT) || defined(COMPAT_KERNEL_RELEASE)
+	{
+		struct station_info sinfo;
+		u8 ie_offset;
+		if (get_frame_sub_type(pmgmt_frame) == WIFI_ASSOCREQ)
+			ie_offset = _ASOCREQ_IE_OFFSET_;
+		else /* WIFI_REASSOCREQ */
+			ie_offset = _REASOCREQ_IE_OFFSET_;
+
+		memset(&sinfo, 0, sizeof(sinfo));
+		sinfo.filled = STATION_INFO_ASSOC_REQ_IES;
+		sinfo.assoc_req_ies = pmgmt_frame + WLAN_HDR_A3_LEN + ie_offset;
+		sinfo.assoc_req_ies_len = frame_len - WLAN_HDR_A3_LEN - ie_offset;
+		cfg80211_new_sta(ndev, get_addr2_ptr(pmgmt_frame), &sinfo, GFP_ATOMIC);
+	}
+#else /* defined(RTW_USE_CFG80211_STA_EVENT) */
+	channel = pmlmeext->cur_channel;
+	freq = rtw_ch2freq(channel);
+
+	#ifdef COMPAT_KERNEL_RELEASE
+	rtw_cfg80211_rx_mgmt(pwdev, freq, 0, pmgmt_frame, frame_len, GFP_ATOMIC);
+	#elif (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) && !defined(CONFIG_CFG80211_FORCE_COMPATIBLE_2_6_37_UNDER)
+	rtw_cfg80211_rx_mgmt(pwdev, freq, 0, pmgmt_frame, frame_len, GFP_ATOMIC);
+	#else /* COMPAT_KERNEL_RELEASE */
+	{
+		/* to avoid WARN_ON(wdev->iftype != NL80211_IFTYPE_STATION)  when calling cfg80211_send_rx_assoc() */
+		#ifndef CONFIG_PLATFORM_MSTAR
+		pwdev->iftype = NL80211_IFTYPE_STATION;
+		#endif /* CONFIG_PLATFORM_MSTAR */
+		RTW_INFO("iftype=%d before call cfg80211_send_rx_assoc()\n", pwdev->iftype);
+		rtw_cfg80211_send_rx_assoc(padapter, NULL, pmgmt_frame, frame_len);
+		RTW_INFO("iftype=%d after call cfg80211_send_rx_assoc()\n", pwdev->iftype);
+		pwdev->iftype = NL80211_IFTYPE_AP;
+		/* cfg80211_rx_action(padapter->pnetdev, freq, pmgmt_frame, frame_len, GFP_ATOMIC); */
+	}
+	#endif /* COMPAT_KERNEL_RELEASE */
+#endif /* defined(RTW_USE_CFG80211_STA_EVENT) */
+
+}
+
+void rtw_cfg80211_indicate_sta_disassoc(_adapter *padapter, const u8 *da, unsigned short reason)
+{
+#if !defined(RTW_USE_CFG80211_STA_EVENT) && !defined(COMPAT_KERNEL_RELEASE)
+	s32 freq;
+	int channel;
+	u8 *pmgmt_frame;
+	uint frame_len;
+	struct rtw_ieee80211_hdr *pwlanhdr;
+	unsigned short *fctrl;
+	u8 mgmt_buf[128] = {0};
+	struct mlme_ext_priv	*pmlmeext = &(padapter->mlmeextpriv);
+	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
+	struct wireless_dev *wdev = padapter->rtw_wdev;
+#endif
+	struct net_device *ndev = padapter->pnetdev;
+
+	RTW_INFO(FUNC_ADPT_FMT"\n", FUNC_ADPT_ARG(padapter));
+
+#if defined(RTW_USE_CFG80211_STA_EVENT) || defined(COMPAT_KERNEL_RELEASE)
+	cfg80211_del_sta(ndev, da, GFP_ATOMIC);
+#else /* defined(RTW_USE_CFG80211_STA_EVENT) */
+	channel = pmlmeext->cur_channel;
+	freq = rtw_ch2freq(channel);
+
+	pmgmt_frame = mgmt_buf;
+	pwlanhdr = (struct rtw_ieee80211_hdr *)pmgmt_frame;
+
+	fctrl = &(pwlanhdr->frame_ctl);
+	*(fctrl) = 0;
+
+	_rtw_memcpy(pwlanhdr->addr1, adapter_mac_addr(padapter), ETH_ALEN);
+	_rtw_memcpy(pwlanhdr->addr2, da, ETH_ALEN);
+	_rtw_memcpy(pwlanhdr->addr3, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN);
+
+	SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq);
+	pmlmeext->mgnt_seq++;
+	set_frame_sub_type(pmgmt_frame, WIFI_DEAUTH);
+
+	pmgmt_frame += sizeof(struct rtw_ieee80211_hdr_3addr);
+	frame_len = sizeof(struct rtw_ieee80211_hdr_3addr);
+
+	reason = cpu_to_le16(reason);
+	pmgmt_frame = rtw_set_fixed_ie(pmgmt_frame, _RSON_CODE_ , (unsigned char *)&reason, &frame_len);
+
+	#ifdef COMPAT_KERNEL_RELEASE
+	rtw_cfg80211_rx_mgmt(wdev, freq, 0, mgmt_buf, frame_len, GFP_ATOMIC);
+	#elif (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) && !defined(CONFIG_CFG80211_FORCE_COMPATIBLE_2_6_37_UNDER)
+	rtw_cfg80211_rx_mgmt(wdev, freq, 0, mgmt_buf, frame_len, GFP_ATOMIC);
+	#else /* COMPAT_KERNEL_RELEASE */
+	cfg80211_send_disassoc(padapter->pnetdev, mgmt_buf, frame_len);
+	/* cfg80211_rx_action(padapter->pnetdev, freq, mgmt_buf, frame_len, GFP_ATOMIC); */
+	#endif /* COMPAT_KERNEL_RELEASE */
+#endif /* defined(RTW_USE_CFG80211_STA_EVENT) */
+}
+
+static int rtw_cfg80211_monitor_if_open(struct net_device *ndev)
+{
+	int ret = 0;
+
+	RTW_INFO("%s\n", __func__);
+
+	return ret;
+}
+
+static int rtw_cfg80211_monitor_if_close(struct net_device *ndev)
+{
+	int ret = 0;
+
+	RTW_INFO("%s\n", __func__);
+
+	return ret;
+}
+
+static int rtw_cfg80211_monitor_if_xmit_entry(struct sk_buff *skb, struct net_device *ndev)
+{
+	int ret = 0;
+	int rtap_len;
+	int qos_len = 0;
+	int dot11_hdr_len = 24;
+	int snap_len = 6;
+	unsigned char *pdata;
+	u16 frame_ctl;
+	unsigned char src_mac_addr[ETH_ALEN];
+	unsigned char dst_mac_addr[ETH_ALEN];
+	struct rtw_ieee80211_hdr *dot11_hdr;
+	struct ieee80211_radiotap_header *rtap_hdr;
+	_adapter *padapter = (_adapter *)rtw_netdev_priv(ndev);
+#ifdef CONFIG_DFS_MASTER
+	struct rf_ctl_t *rfctl = adapter_to_rfctl(padapter);
+#endif
+
+	RTW_INFO(FUNC_NDEV_FMT"\n", FUNC_NDEV_ARG(ndev));
+
+	if (skb)
+		rtw_mstat_update(MSTAT_TYPE_SKB, MSTAT_ALLOC_SUCCESS, skb->truesize);
+
+	if (IS_CH_WAITING(rfctl)) {
+		#ifdef CONFIG_DFS_MASTER
+		if (rtw_rfctl_overlap_radar_detect_ch(rfctl))
+			goto fail;
+		#endif
+	}
+
+	if (unlikely(skb->len < sizeof(struct ieee80211_radiotap_header)))
+		goto fail;
+
+	rtap_hdr = (struct ieee80211_radiotap_header *)skb->data;
+	if (unlikely(rtap_hdr->it_version))
+		goto fail;
+
+	rtap_len = ieee80211_get_radiotap_len(skb->data);
+	if (unlikely(skb->len < rtap_len))
+		goto fail;
+
+	if (rtap_len != 14) {
+		RTW_INFO("radiotap len (should be 14): %d\n", rtap_len);
+		goto fail;
+	}
+
+	/* Skip the ratio tap header */
+	skb_pull(skb, rtap_len);
+
+	dot11_hdr = (struct rtw_ieee80211_hdr *)skb->data;
+	frame_ctl = le16_to_cpu(dot11_hdr->frame_ctl);
+	/* Check if the QoS bit is set */
+	if ((frame_ctl & RTW_IEEE80211_FCTL_FTYPE) == RTW_IEEE80211_FTYPE_DATA) {
+		/* Check if this ia a Wireless Distribution System (WDS) frame
+		 * which has 4 MAC addresses
+		 */
+		if (dot11_hdr->frame_ctl & 0x0080)
+			qos_len = 2;
+		if ((dot11_hdr->frame_ctl & 0x0300) == 0x0300)
+			dot11_hdr_len += 6;
+
+		memcpy(dst_mac_addr, dot11_hdr->addr1, sizeof(dst_mac_addr));
+		memcpy(src_mac_addr, dot11_hdr->addr2, sizeof(src_mac_addr));
+
+		/* Skip the 802.11 header, QoS (if any) and SNAP, but leave spaces for
+		 * for two MAC addresses
+		 */
+		skb_pull(skb, dot11_hdr_len + qos_len + snap_len - sizeof(src_mac_addr) * 2);
+		pdata = (unsigned char *)skb->data;
+		memcpy(pdata, dst_mac_addr, sizeof(dst_mac_addr));
+		memcpy(pdata + sizeof(dst_mac_addr), src_mac_addr, sizeof(src_mac_addr));
+
+		RTW_INFO("should be eapol packet\n");
+
+		/* Use the real net device to transmit the packet */
+		ret = _rtw_xmit_entry(skb, padapter->pnetdev);
+
+		return ret;
+
+	} else if ((frame_ctl & (RTW_IEEE80211_FCTL_FTYPE | RTW_IEEE80211_FCTL_STYPE))
+		== (RTW_IEEE80211_FTYPE_MGMT | RTW_IEEE80211_STYPE_ACTION)
+	) {
+		/* only for action frames */
+		struct xmit_frame		*pmgntframe;
+		struct pkt_attrib	*pattrib;
+		unsigned char	*pframe;
+		/* u8 category, action, OUI_Subtype, dialogToken=0; */
+		/* unsigned char	*frame_body; */
+		struct rtw_ieee80211_hdr *pwlanhdr;
+		struct xmit_priv	*pxmitpriv = &(padapter->xmitpriv);
+		struct mlme_ext_priv	*pmlmeext = &(padapter->mlmeextpriv);
+		u8 *buf = skb->data;
+		u32 len = skb->len;
+		u8 category, action;
+		int type = -1;
+
+		if (rtw_action_frame_parse(buf, len, &category, &action) == _FALSE) {
+			RTW_INFO(FUNC_NDEV_FMT" frame_control:0x%x\n", FUNC_NDEV_ARG(ndev),
+				le16_to_cpu(((struct rtw_ieee80211_hdr_3addr *)buf)->frame_ctl));
+			goto fail;
+		}
+
+		RTW_INFO("RTW_Tx:da="MAC_FMT" via "FUNC_NDEV_FMT"\n",
+			MAC_ARG(GetAddr1Ptr(buf)), FUNC_NDEV_ARG(ndev));
+		#ifdef CONFIG_P2P
+		type = rtw_p2p_check_frames(padapter, buf, len, _TRUE);
+		if (type >= 0)
+			goto dump;
+		#endif
+		if (category == RTW_WLAN_CATEGORY_PUBLIC)
+			RTW_INFO("RTW_Tx:%s\n", action_public_str(action));
+		else
+			RTW_INFO("RTW_Tx:category(%u), action(%u)\n", category, action);
+
+dump:
+		/* starting alloc mgmt frame to dump it */
+		pmgntframe = alloc_mgtxmitframe(pxmitpriv);
+		if (pmgntframe == NULL)
+			goto fail;
+
+		/* update attribute */
+		pattrib = &pmgntframe->attrib;
+		update_mgntframe_attrib(padapter, pattrib);
+		pattrib->retry_ctrl = _FALSE;
+
+		_rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET);
+
+		pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET;
+
+		_rtw_memcpy(pframe, (void *)buf, len);
+		pattrib->pktlen = len;
+
+#ifdef CONFIG_P2P
+		if (type >= 0)
+			rtw_xframe_chk_wfd_ie(pmgntframe);
+#endif /* CONFIG_P2P */
+
+		pwlanhdr = (struct rtw_ieee80211_hdr *)pframe;
+		/* update seq number */
+		pmlmeext->mgnt_seq = GetSequence(pwlanhdr);
+		pattrib->seqnum = pmlmeext->mgnt_seq;
+		pmlmeext->mgnt_seq++;
+
+
+		pattrib->last_txcmdsz = pattrib->pktlen;
+
+		dump_mgntframe(padapter, pmgntframe);
+
+	} else
+		RTW_INFO("frame_ctl=0x%x\n", frame_ctl & (RTW_IEEE80211_FCTL_FTYPE | RTW_IEEE80211_FCTL_STYPE));
+
+
+fail:
+
+	rtw_skb_free(skb);
+
+	return 0;
+
+}
+
+static void rtw_cfg80211_monitor_if_set_multicast_list(struct net_device *ndev)
+{
+	RTW_INFO("%s\n", __func__);
+}
+
+static int rtw_cfg80211_monitor_if_set_mac_address(struct net_device *ndev, void *addr)
+{
+	int ret = 0;
+
+	RTW_INFO("%s\n", __func__);
+
+	return ret;
+}
+
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 29))
+static const struct net_device_ops rtw_cfg80211_monitor_if_ops = {
+	.ndo_open = rtw_cfg80211_monitor_if_open,
+	.ndo_stop = rtw_cfg80211_monitor_if_close,
+	.ndo_start_xmit = rtw_cfg80211_monitor_if_xmit_entry,
+	#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 2, 0))
+	.ndo_set_multicast_list = rtw_cfg80211_monitor_if_set_multicast_list,
+	#endif
+	.ndo_set_mac_address = rtw_cfg80211_monitor_if_set_mac_address,
+};
+#endif
+
+static int rtw_cfg80211_add_monitor_if(_adapter *padapter, char *name, struct net_device **ndev)
+{
+	int ret = 0;
+	struct net_device *mon_ndev = NULL;
+	struct wireless_dev *mon_wdev = NULL;
+	struct rtw_netdev_priv_indicator *pnpi;
+	struct rtw_wdev_priv *pwdev_priv = adapter_wdev_data(padapter);
+
+	if (!name) {
+		RTW_INFO(FUNC_ADPT_FMT" without specific name\n", FUNC_ADPT_ARG(padapter));
+		ret = -EINVAL;
+		goto out;
+	}
+
+	if (pwdev_priv->pmon_ndev) {
+		RTW_INFO(FUNC_ADPT_FMT" monitor interface exist: "NDEV_FMT"\n",
+			FUNC_ADPT_ARG(padapter), NDEV_ARG(pwdev_priv->pmon_ndev));
+		ret = -EBUSY;
+		goto out;
+	}
+
+	mon_ndev = alloc_etherdev(sizeof(struct rtw_netdev_priv_indicator));
+	if (!mon_ndev) {
+		RTW_INFO(FUNC_ADPT_FMT" allocate ndev fail\n", FUNC_ADPT_ARG(padapter));
+		ret = -ENOMEM;
+		goto out;
+	}
+
+	mon_ndev->type = ARPHRD_IEEE80211_RADIOTAP;
+	strncpy(mon_ndev->name, name, IFNAMSIZ);
+	mon_ndev->name[IFNAMSIZ - 1] = 0;
+#if (LINUX_VERSION_CODE > KERNEL_VERSION(4, 11, 8))
+	mon_ndev->priv_destructor = rtw_ndev_destructor;
+#else
+	mon_ndev->destructor = rtw_ndev_destructor;
+#endif
+
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 29))
+	mon_ndev->netdev_ops = &rtw_cfg80211_monitor_if_ops;
+#else
+	mon_ndev->open = rtw_cfg80211_monitor_if_open;
+	mon_ndev->stop = rtw_cfg80211_monitor_if_close;
+	mon_ndev->hard_start_xmit = rtw_cfg80211_monitor_if_xmit_entry;
+	mon_ndev->set_mac_address = rtw_cfg80211_monitor_if_set_mac_address;
+#endif
+
+	pnpi = netdev_priv(mon_ndev);
+	pnpi->priv = padapter;
+	pnpi->sizeof_priv = sizeof(_adapter);
+
+	/*  wdev */
+	mon_wdev = (struct wireless_dev *)rtw_zmalloc(sizeof(struct wireless_dev));
+	if (!mon_wdev) {
+		RTW_INFO(FUNC_ADPT_FMT" allocate mon_wdev fail\n", FUNC_ADPT_ARG(padapter));
+		ret = -ENOMEM;
+		goto out;
+	}
+
+	mon_wdev->wiphy = padapter->rtw_wdev->wiphy;
+	mon_wdev->netdev = mon_ndev;
+	mon_wdev->iftype = NL80211_IFTYPE_MONITOR;
+	mon_ndev->ieee80211_ptr = mon_wdev;
+
+	ret = register_netdevice(mon_ndev);
+	if (ret)
+		goto out;
+
+	*ndev = pwdev_priv->pmon_ndev = mon_ndev;
+	_rtw_memcpy(pwdev_priv->ifname_mon, name, IFNAMSIZ + 1);
+
+out:
+	if (ret && mon_wdev) {
+		rtw_mfree((u8 *)mon_wdev, sizeof(struct wireless_dev));
+		mon_wdev = NULL;
+	}
+
+	if (ret && mon_ndev) {
+		free_netdev(mon_ndev);
+		*ndev = mon_ndev = NULL;
+	}
+
+	return ret;
+}
+
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 6, 0))
+static struct wireless_dev *
+#elif (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 38)) || defined(COMPAT_KERNEL_RELEASE)
+static struct net_device *
+#else
+static int
+#endif
+	cfg80211_rtw_add_virtual_intf(
+		struct wiphy *wiphy,
+		#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 7, 0))
+		const char *name,
+		#else
+		char *name,
+		#endif
+		#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 1, 0))
+		unsigned char name_assign_type,
+		#endif
+		enum nl80211_iftype type,
+		#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 12, 0))
+		u32 *flags,
+		#endif
+		struct vif_params *params)
+{
+	int ret = 0;
+	struct wireless_dev *wdev = NULL;
+	struct net_device *ndev = NULL;
+	_adapter *padapter;
+	struct dvobj_priv *dvobj = wiphy_to_dvobj(wiphy);
+
+	rtw_set_rtnl_lock_holder(dvobj, current);
+
+	RTW_INFO(FUNC_WIPHY_FMT" name:%s, type:%d\n", FUNC_WIPHY_ARG(wiphy), name, type);
+
+	switch (type) {
+	case NL80211_IFTYPE_MONITOR:
+		padapter = wiphy_to_adapter(wiphy); /* TODO: get ap iface ? */
+		ret = rtw_cfg80211_add_monitor_if(padapter, (char *)name, &ndev);
+		if (ret == 0)
+			wdev = ndev->ieee80211_ptr;
+		break;
+
+#if defined(CONFIG_P2P) && ((LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) || defined(COMPAT_KERNEL_RELEASE))
+	case NL80211_IFTYPE_P2P_CLIENT:
+	case NL80211_IFTYPE_P2P_GO:
+#endif
+	case NL80211_IFTYPE_STATION:
+	case NL80211_IFTYPE_AP:
+#ifdef CONFIG_RTW_MESH
+	case NL80211_IFTYPE_MESH_POINT:
+#endif
+		padapter = dvobj_get_unregisterd_adapter(dvobj);
+		if (!padapter) {
+			RTW_WARN("adapter pool empty!\n");
+			ret = -ENODEV;
+			break;
+		}
+		if (rtw_os_ndev_init(padapter, name) != _SUCCESS) {
+			RTW_WARN("ndev init fail!\n");
+			ret = -ENODEV;
+			break;
+		}
+		#if defined(CONFIG_P2P) && ((LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) || defined(COMPAT_KERNEL_RELEASE))
+		if (type == NL80211_IFTYPE_P2P_CLIENT || type == NL80211_IFTYPE_P2P_GO)
+			rtw_p2p_enable(padapter, P2P_ROLE_DEVICE);
+		#endif
+		ndev = padapter->pnetdev;
+		wdev = ndev->ieee80211_ptr;
+		break;
+
+#if defined(CONFIG_P2P) && defined(RTW_DEDICATED_P2P_DEVICE)
+	case NL80211_IFTYPE_P2P_DEVICE:
+		ret = rtw_pd_iface_alloc(wiphy, name, &wdev);
+		break;
+#endif
+
+	case NL80211_IFTYPE_ADHOC:
+	case NL80211_IFTYPE_AP_VLAN:
+	case NL80211_IFTYPE_WDS:
+	default:
+		ret = -ENODEV;
+		RTW_INFO("Unsupported interface type\n");
+		break;
+	}
+
+	if (ndev)
+		RTW_INFO(FUNC_WIPHY_FMT" ndev:%p, ret:%d\n", FUNC_WIPHY_ARG(wiphy), ndev, ret);
+	else
+		RTW_INFO(FUNC_WIPHY_FMT" wdev:%p, ret:%d\n", FUNC_WIPHY_ARG(wiphy), wdev, ret);
+
+	rtw_set_rtnl_lock_holder(dvobj, NULL);
+
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 6, 0))
+	return wdev ? wdev : ERR_PTR(ret);
+#elif (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 38)) || defined(COMPAT_KERNEL_RELEASE)
+	return ndev ? ndev : ERR_PTR(ret);
+#else
+	return ret;
+#endif
+}
+
+static int cfg80211_rtw_del_virtual_intf(struct wiphy *wiphy,
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 6, 0))
+	struct wireless_dev *wdev
+#else
+	struct net_device *ndev
+#endif
+)
+{
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 6, 0))
+	struct net_device *ndev = wdev_to_ndev(wdev);
+#endif
+	int ret = 0;
+	struct dvobj_priv *dvobj = wiphy_to_dvobj(wiphy);
+	_adapter *adapter;
+	struct rtw_wdev_priv *pwdev_priv;
+
+	rtw_set_rtnl_lock_holder(dvobj, current);
+
+	if (ndev) {
+		adapter = (_adapter *)rtw_netdev_priv(ndev);
+		pwdev_priv = adapter_wdev_data(adapter);
+
+		if (ndev == pwdev_priv->pmon_ndev) {
+			unregister_netdevice(ndev);
+			pwdev_priv->pmon_ndev = NULL;
+			pwdev_priv->ifname_mon[0] = '\0';
+			RTW_INFO(FUNC_NDEV_FMT" remove monitor ndev\n", FUNC_NDEV_ARG(ndev));
+		} else {
+			RTW_INFO(FUNC_NDEV_FMT" unregister ndev\n", FUNC_NDEV_ARG(ndev));
+			rtw_os_ndev_unregister(adapter);
+		}
+	} else
+#if defined(CONFIG_P2P) && defined(RTW_DEDICATED_P2P_DEVICE)
+	if (wdev->iftype == NL80211_IFTYPE_P2P_DEVICE) {
+		if (wdev == wiphy_to_pd_wdev(wiphy))
+			rtw_pd_iface_free(wiphy);
+		else {
+			RTW_ERR(FUNC_WIPHY_FMT" unknown P2P Device wdev:%p\n", FUNC_WIPHY_ARG(wiphy), wdev);
+			rtw_warn_on(1);
+		}
+	} else
+#endif
+	{
+		ret = -EINVAL;
+		goto exit;
+	}
+
+exit:
+	rtw_set_rtnl_lock_holder(dvobj, NULL);
+	return ret;
+}
+
+static int rtw_add_beacon(_adapter *adapter, const u8 *head, size_t head_len, const u8 *tail, size_t tail_len)
+{
+	int ret = 0;
+	u8 *pbuf = NULL;
+	uint len, wps_ielen = 0;
+	uint p2p_ielen = 0;
+	u8 got_p2p_ie = _FALSE;
+	struct mlme_priv *pmlmepriv = &(adapter->mlmepriv);
+	/* struct sta_priv *pstapriv = &padapter->stapriv; */
+
+
+	RTW_INFO("%s beacon_head_len=%zu, beacon_tail_len=%zu\n", __FUNCTION__, head_len, tail_len);
+
+
+	if (check_fwstate(pmlmepriv, WIFI_AP_STATE) != _TRUE)
+		return -EINVAL;
+
+	if (head_len < 24)
+		return -EINVAL;
+
+	#ifdef CONFIG_FW_HANDLE_TXBCN
+	if (!rtw_ap_nums_check(adapter)) {
+		RTW_ERR(FUNC_ADPT_FMT"failed, con't support over %d BCN\n", FUNC_ADPT_ARG(adapter), CONFIG_LIMITED_AP_NUM);
+		return -EINVAL;
+	}
+	#endif /*CONFIG_FW_HANDLE_TXBCN*/
+
+	pbuf = rtw_zmalloc(head_len + tail_len);
+	if (!pbuf)
+		return -ENOMEM;
+
+
+	/* _rtw_memcpy(&pstapriv->max_num_sta, param->u.bcn_ie.reserved, 2); */
+
+	/* if((pstapriv->max_num_sta>NUM_STA) || (pstapriv->max_num_sta<=0)) */
+	/*	pstapriv->max_num_sta = NUM_STA; */
+
+
+	_rtw_memcpy(pbuf, (void *)head + 24, head_len - 24); /* 24=beacon header len. */
+	_rtw_memcpy(pbuf + head_len - 24, (void *)tail, tail_len);
+
+	len = head_len + tail_len - 24;
+
+	/* check wps ie if inclued */
+	if (rtw_get_wps_ie(pbuf + _FIXED_IE_LENGTH_, len - _FIXED_IE_LENGTH_, NULL, &wps_ielen))
+		RTW_INFO("add bcn, wps_ielen=%d\n", wps_ielen);
+
+#ifdef CONFIG_P2P
+	if (adapter->wdinfo.driver_interface == DRIVER_CFG80211) {
+		/* check p2p if enable */
+		if (rtw_get_p2p_ie(pbuf + _FIXED_IE_LENGTH_, len - _FIXED_IE_LENGTH_, NULL, &p2p_ielen)) {
+			struct wifidirect_info *pwdinfo = &(adapter->wdinfo);
+
+			RTW_INFO("got p2p_ie, len=%d\n", p2p_ielen);
+
+			got_p2p_ie = _TRUE;
+
+			if (rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE)) {
+				RTW_INFO("Enable P2P function for the first time\n");
+				rtw_p2p_enable(adapter, P2P_ROLE_GO);
+
+				adapter->stapriv.expire_to = 3; /* 3x2 = 6 sec in p2p mode */
+			} else {
+				RTW_INFO("enter GO Mode, p2p_ielen=%d\n", p2p_ielen);
+
+				rtw_p2p_set_role(pwdinfo, P2P_ROLE_GO);
+				rtw_p2p_set_state(pwdinfo, P2P_STATE_GONEGO_OK);
+				pwdinfo->intent = 15;
+			}
+		}
+	}
+#endif /* CONFIG_P2P */
+
+	/* pbss_network->IEs will not include p2p_ie, wfd ie */
+	rtw_ies_remove_ie(pbuf, &len, _BEACON_IE_OFFSET_, _VENDOR_SPECIFIC_IE_, P2P_OUI, 4);
+	rtw_ies_remove_ie(pbuf, &len, _BEACON_IE_OFFSET_, _VENDOR_SPECIFIC_IE_, WFD_OUI, 4);
+
+	if (rtw_check_beacon_data(adapter, pbuf,  len) == _SUCCESS) {
+#ifdef CONFIG_P2P
+		/* check p2p if enable */
+		if (got_p2p_ie == _TRUE) {
+			struct mlme_ext_priv *pmlmeext = &adapter->mlmeextpriv;
+			struct wifidirect_info *pwdinfo = &(adapter->wdinfo);
+			pwdinfo->operating_channel = pmlmeext->cur_channel;
+		}
+#endif /* CONFIG_P2P */
+		ret = 0;
+	} else
+		ret = -EINVAL;
+
+
+	rtw_mfree(pbuf, head_len + tail_len);
+
+	return ret;
+}
+
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 4, 0)) && !defined(COMPAT_KERNEL_RELEASE)
+static int cfg80211_rtw_add_beacon(struct wiphy *wiphy, struct net_device *ndev,
+		struct beacon_parameters *info)
+{
+	int ret = 0;
+	_adapter *adapter = (_adapter *)rtw_netdev_priv(ndev);
+
+	RTW_INFO(FUNC_NDEV_FMT"\n", FUNC_NDEV_ARG(ndev));
+
+	if (rtw_cfg80211_sync_iftype(adapter) != _SUCCESS) {
+		ret = -ENOTSUPP;
+		goto exit;
+	}
+	rtw_mi_scan_abort(adapter, _TRUE);
+	rtw_mi_buddy_set_scan_deny(adapter, 300);
+	ret = rtw_add_beacon(adapter, info->head, info->head_len, info->tail, info->tail_len);
+
+exit:
+	return ret;
+}
+
+static int cfg80211_rtw_set_beacon(struct wiphy *wiphy, struct net_device *ndev,
+		struct beacon_parameters *info)
+{
+	_adapter *adapter = (_adapter *)rtw_netdev_priv(ndev);
+	struct mlme_ext_priv *pmlmeext = &(adapter->mlmeextpriv);
+
+	RTW_INFO(FUNC_NDEV_FMT"\n", FUNC_NDEV_ARG(ndev));
+
+	pmlmeext->bstart_bss = _TRUE;
+
+	cfg80211_rtw_add_beacon(wiphy, ndev, info);
+
+	return 0;
+}
+
+static int	cfg80211_rtw_del_beacon(struct wiphy *wiphy, struct net_device *ndev)
+{
+	_adapter *adapter = (_adapter *)rtw_netdev_priv(ndev);
+
+	RTW_INFO(FUNC_NDEV_FMT"\n", FUNC_NDEV_ARG(ndev));
+
+	rtw_set_802_11_infrastructure_mode(adapter, Ndis802_11Infrastructure);
+	rtw_setopmode_cmd(adapter, Ndis802_11Infrastructure, RTW_CMDF_WAIT_ACK);
+
+	return 0;
+}
+#else
+static int cfg80211_rtw_start_ap(struct wiphy *wiphy, struct net_device *ndev,
+		struct cfg80211_ap_settings *settings)
+{
+	int ret = 0;
+	_adapter *adapter = (_adapter *)rtw_netdev_priv(ndev);
+
+	RTW_INFO(FUNC_NDEV_FMT" hidden_ssid:%d, auth_type:%d\n", FUNC_NDEV_ARG(ndev),
+		settings->hidden_ssid, settings->auth_type);
+
+	if (rtw_cfg80211_sync_iftype(adapter) != _SUCCESS) {
+		ret = -ENOTSUPP;
+		goto exit;
+	}
+	rtw_mi_scan_abort(adapter, _TRUE);
+	rtw_mi_buddy_set_scan_deny(adapter, 300);
+	ret = rtw_add_beacon(adapter, settings->beacon.head, settings->beacon.head_len,
+		settings->beacon.tail, settings->beacon.tail_len);
+
+	adapter->mlmeextpriv.mlmext_info.hidden_ssid_mode = settings->hidden_ssid;
+
+	if (settings->ssid && settings->ssid_len) {
+		WLAN_BSSID_EX *pbss_network = &adapter->mlmepriv.cur_network.network;
+		WLAN_BSSID_EX *pbss_network_ext = &adapter->mlmeextpriv.mlmext_info.network;
+
+		if (0)
+			RTW_INFO(FUNC_ADPT_FMT" ssid:(%s,%zu), from ie:(%s,%d)\n", FUNC_ADPT_ARG(adapter),
+				settings->ssid, settings->ssid_len,
+				pbss_network->Ssid.Ssid, pbss_network->Ssid.SsidLength);
+
+		_rtw_memcpy(pbss_network->Ssid.Ssid, (void *)settings->ssid, settings->ssid_len);
+		pbss_network->Ssid.SsidLength = settings->ssid_len;
+		_rtw_memcpy(pbss_network_ext->Ssid.Ssid, (void *)settings->ssid, settings->ssid_len);
+		pbss_network_ext->Ssid.SsidLength = settings->ssid_len;
+
+		if (0)
+			RTW_INFO(FUNC_ADPT_FMT" after ssid:(%s,%d), (%s,%d)\n", FUNC_ADPT_ARG(adapter),
+				pbss_network->Ssid.Ssid, pbss_network->Ssid.SsidLength,
+				pbss_network_ext->Ssid.Ssid, pbss_network_ext->Ssid.SsidLength);
+	}
+
+exit:
+	return ret;
+}
+
+static int cfg80211_rtw_change_beacon(struct wiphy *wiphy, struct net_device *ndev,
+		struct cfg80211_beacon_data *info)
+{
+	int ret = 0;
+	_adapter *adapter = (_adapter *)rtw_netdev_priv(ndev);
+
+	RTW_INFO(FUNC_NDEV_FMT"\n", FUNC_NDEV_ARG(ndev));
+
+	ret = rtw_add_beacon(adapter, info->head, info->head_len, info->tail, info->tail_len);
+
+	return ret;
+}
+
+static int cfg80211_rtw_stop_ap(struct wiphy *wiphy, struct net_device *ndev)
+{
+	_adapter *adapter = (_adapter *)rtw_netdev_priv(ndev);
+
+	RTW_INFO(FUNC_NDEV_FMT"\n", FUNC_NDEV_ARG(ndev));
+
+	rtw_set_802_11_infrastructure_mode(adapter, Ndis802_11Infrastructure);
+	rtw_setopmode_cmd(adapter, Ndis802_11Infrastructure, RTW_CMDF_WAIT_ACK);
+
+	return 0;
+}
+#endif /* (LINUX_VERSION_CODE < KERNEL_VERSION(3, 4, 0)) */
+
+#if CONFIG_RTW_MACADDR_ACL && (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 9, 0))
+static int cfg80211_rtw_set_mac_acl(struct wiphy *wiphy, struct net_device *ndev,
+		const struct cfg80211_acl_data *params)
+{
+	_adapter *adapter = (_adapter *)rtw_netdev_priv(ndev);
+	u8 acl_mode = RTW_ACL_MODE_DISABLED;
+	int ret = -1;
+	int i;
+
+	if (!params) {
+		RTW_WARN(FUNC_ADPT_FMT" params NULL\n", FUNC_ADPT_ARG(adapter));
+		rtw_macaddr_acl_clear(adapter, RTW_ACL_PERIOD_BSS);
+		goto exit;
+	}
+
+	RTW_INFO(FUNC_ADPT_FMT" acl_policy:%d, entry_num:%d\n"
+		, FUNC_ADPT_ARG(adapter), params->acl_policy, params->n_acl_entries);
+
+	if (params->acl_policy == NL80211_ACL_POLICY_ACCEPT_UNLESS_LISTED)
+		acl_mode = RTW_ACL_MODE_ACCEPT_UNLESS_LISTED;
+	else if (params->acl_policy == NL80211_ACL_POLICY_DENY_UNLESS_LISTED)
+		acl_mode = RTW_ACL_MODE_DENY_UNLESS_LISTED;
+
+	rtw_macaddr_acl_clear(adapter, RTW_ACL_PERIOD_BSS);
+
+	rtw_set_macaddr_acl(adapter, RTW_ACL_PERIOD_BSS, acl_mode);
+
+	for (i = 0; i < params->n_acl_entries; i++)
+		rtw_acl_add_sta(adapter, RTW_ACL_PERIOD_BSS, params->mac_addrs[i].addr);
+
+	ret = 0;
+
+exit:
+	return ret;
+}
+#endif /* CONFIG_RTW_MACADDR_ACL && (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 9, 0)) */
+
+const char *_nl80211_sta_flags_str[] = {
+	"INVALID",
+	"AUTHORIZED",
+	"SHORT_PREAMBLE",
+	"WME",
+	"MFP",
+	"AUTHENTICATED",
+	"TDLS_PEER",
+	"ASSOCIATED",
+};
+
+#define nl80211_sta_flags_str(_f) ((_f <= NL80211_STA_FLAG_MAX) ? _nl80211_sta_flags_str[_f] : _nl80211_sta_flags_str[0])
+
+const char *_nl80211_plink_state_str[] = {
+	"LISTEN",
+	"OPN_SNT",
+	"OPN_RCVD",
+	"CNF_RCVD",
+	"ESTAB",
+	"HOLDING",
+	"BLOCKED",
+	"UNKNOWN",
+};
+
+#define nl80211_plink_state_str(_s) ((_s < NUM_NL80211_PLINK_STATES) ? _nl80211_plink_state_str[_s] : _nl80211_plink_state_str[NUM_NL80211_PLINK_STATES])
+
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 10, 0))
+#define NL80211_PLINK_ACTION_NO_ACTION PLINK_ACTION_INVALID
+#define NL80211_PLINK_ACTION_OPEN PLINK_ACTION_OPEN
+#define NL80211_PLINK_ACTION_BLOCK PLINK_ACTION_BLOCK
+#define NUM_NL80211_PLINK_ACTIONS 3
+#endif
+
+const char *_nl80211_plink_actions_str[] = {
+	"NO_ACTION",
+	"OPEN",
+	"BLOCK",
+	"UNKNOWN",
+};
+
+#define nl80211_plink_actions_str(_a) ((_a < NUM_NL80211_PLINK_ACTIONS) ? _nl80211_plink_actions_str[_a] : _nl80211_plink_actions_str[NUM_NL80211_PLINK_ACTIONS])
+
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 9, 0))
+const char *_nl80211_mesh_power_mode_str[] = {
+	"UNKNOWN",
+	"ACTIVE",
+	"LIGHT_SLEEP",
+	"DEEP_SLEEP",
+};
+
+#define nl80211_mesh_power_mode_str(_p) ((_p <= NL80211_MESH_POWER_MAX) ? _nl80211_mesh_power_mode_str[_p] : _nl80211_mesh_power_mode_str[0])
+#endif
+
+void dump_station_parameters(void *sel, struct wiphy *wiphy, const struct station_parameters *params)
+{
+#if DBG_RTW_CFG80211_STA_PARAM
+	if (params->supported_rates_len) {
+		#define SUPP_RATES_BUF_LEN (3 * RTW_G_RATES_NUM + 1)
+		int i;
+		char supp_rates_buf[SUPP_RATES_BUF_LEN] = {0};
+		u8 cnt = 0;
+
+		rtw_warn_on(params->supported_rates_len > RTW_G_RATES_NUM);
+
+		for (i = 0; i < params->supported_rates_len; i++) {
+			if (i >= RTW_G_RATES_NUM)
+				break;
+			cnt += snprintf(supp_rates_buf + cnt, SUPP_RATES_BUF_LEN - cnt -1
+				, "%02X ", params->supported_rates[i]);
+			if (cnt >= SUPP_RATES_BUF_LEN - 1)
+				break;
+		}
+
+		RTW_PRINT_SEL(sel, "supported_rates:%s\n", supp_rates_buf);
+	}
+
+	if (params->vlan)
+		RTW_PRINT_SEL(sel, "vlan:"NDEV_FMT"\n", NDEV_ARG(params->vlan));
+
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 31))
+	if (params->sta_flags_mask) {
+		#define STA_FLAGS_BUF_LEN 128
+		int i = 0;
+		char sta_flags_buf[STA_FLAGS_BUF_LEN] = {0};
+		u8 cnt = 0;
+
+		for (i = 1; i <= NL80211_STA_FLAG_MAX; i++) {
+			if (params->sta_flags_mask & BIT(i)) {
+				cnt += snprintf(sta_flags_buf + cnt, STA_FLAGS_BUF_LEN - cnt -1, "%s=%u "
+					, nl80211_sta_flags_str(i), (params->sta_flags_set & BIT(i)) ? 1 : 0);
+				if (cnt >= STA_FLAGS_BUF_LEN - 1)
+					break;
+			}
+		}
+
+		RTW_PRINT_SEL(sel, "sta_flags:%s\n", sta_flags_buf);
+	}
+#else
+	u32 station_flags;
+	#error "TBD\n"
+#endif
+
+	if (params->listen_interval != -1)
+		RTW_PRINT_SEL(sel, "listen_interval:%d\n", params->listen_interval);
+
+	if (params->aid)
+		RTW_PRINT_SEL(sel, "aid:%u\n", params->aid);
+
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 8, 0))
+	if (params->peer_aid)
+		RTW_PRINT_SEL(sel, "peer_aid:%u\n", params->peer_aid);
+#endif
+
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 26))
+	if (params->plink_action != NL80211_PLINK_ACTION_NO_ACTION)
+		RTW_PRINT_SEL(sel, "plink_action:%s\n", nl80211_plink_actions_str(params->plink_action));
+#endif
+
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 0, 0))
+	#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 10, 0))
+	if (params->sta_modify_mask & STATION_PARAM_APPLY_PLINK_STATE)
+	#endif
+		RTW_PRINT_SEL(sel, "plink_state:%s\n"
+			, nl80211_plink_state_str(params->plink_state));
+#endif
+
+#if 0 /* TODO */
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 28))
+	const struct ieee80211_ht_cap *ht_capa;
+#endif
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 8, 0))
+	const struct ieee80211_vht_cap *vht_capa;
+#endif
+#endif
+
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 2, 0))
+	if (params->sta_modify_mask & STATION_PARAM_APPLY_UAPSD)
+		RTW_PRINT_SEL(sel, "uapsd_queues:0x%02x\n", params->uapsd_queues);
+	if (params->max_sp)
+		RTW_PRINT_SEL(sel, "max_sp:%u\n", params->max_sp);
+#endif
+
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 9, 0))
+	if (params->local_pm != NL80211_MESH_POWER_UNKNOWN) {
+		RTW_PRINT_SEL(sel, "local_pm:%s\n"
+			, nl80211_mesh_power_mode_str(params->local_pm));
+	}
+
+	if (params->sta_modify_mask & STATION_PARAM_APPLY_CAPABILITY)
+		RTW_PRINT_SEL(sel, "capability:0x%04x\n", params->capability);
+
+#if 0 /* TODO */
+	const u8 *ext_capab;
+	u8 ext_capab_len;
+#endif
+#endif
+
+#if 0 /* TODO */
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 13, 0))
+	const u8 *supported_channels;
+	u8 supported_channels_len;
+	const u8 *supported_oper_classes;
+	u8 supported_oper_classes_len;
+#endif
+
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 14, 0))
+	u8 opmode_notif;
+	bool opmode_notif_used;
+#endif
+
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 7, 0))
+	int support_p2p_ps;
+#endif
+#endif
+#endif /* DBG_RTW_CFG80211_STA_PARAM */
+}
+
+static int	cfg80211_rtw_add_station(struct wiphy *wiphy, struct net_device *ndev,
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 16, 0))
+	u8 *mac,
+#else
+	const u8 *mac,
+#endif
+	struct station_parameters *params)
+{
+	int ret = 0;
+	_adapter *padapter = (_adapter *)rtw_netdev_priv(ndev);
+#if defined(CONFIG_TDLS) || defined(CONFIG_RTW_MESH)
+	struct sta_priv *pstapriv = &padapter->stapriv;
+#endif
+#ifdef CONFIG_TDLS
+	struct sta_info *psta;
+#endif /* CONFIG_TDLS */
+
+	RTW_INFO(FUNC_NDEV_FMT" mac:"MAC_FMT"\n", FUNC_NDEV_ARG(ndev), MAC_ARG(mac));
+
+#if CONFIG_RTW_MACADDR_ACL
+	if (rtw_access_ctrl(padapter, mac) == _FALSE) {
+		RTW_INFO(FUNC_NDEV_FMT" deny by macaddr ACL\n", FUNC_NDEV_ARG(ndev));
+		ret = -EINVAL;
+		goto exit;
+	}
+#endif
+
+	dump_station_parameters(RTW_DBGDUMP, wiphy, params);
+
+#ifdef CONFIG_RTW_MESH
+	if (MLME_IS_MESH(padapter)) {
+		struct rtw_mesh_cfg *mcfg = &padapter->mesh_cfg;
+		struct rtw_mesh_info *minfo = &padapter->mesh_info;
+		struct mesh_plink_pool *plink_ctl = &minfo->plink_ctl;
+		struct mesh_plink_ent *plink = NULL;
+		struct wlan_network *scanned = NULL;
+		bool acnode = 0;
+		u8 add_new_sta = 0, probe_req = 0;
+		_irqL irqL;
+
+		if (params->plink_state != NL80211_PLINK_LISTEN) {
+			RTW_WARN(FUNC_NDEV_FMT" %s\n", FUNC_NDEV_ARG(ndev), nl80211_plink_state_str(params->plink_state));
+			rtw_warn_on(1);
+		}
+		if (!params->aid || params->aid > pstapriv->max_aid) {
+			RTW_WARN(FUNC_NDEV_FMT" invalid aid:%u\n", FUNC_NDEV_ARG(ndev), params->aid);
+			rtw_warn_on(1);
+			ret = -EINVAL;
+			goto exit;
+		}
+
+		_enter_critical_bh(&(plink_ctl->lock), &irqL);
+
+		plink = _rtw_mesh_plink_get(padapter, mac);
+		if (plink)
+			goto release_plink_ctl;
+
+		#if CONFIG_RTW_MESH_PEER_BLACKLIST
+		if (rtw_mesh_peer_blacklist_search(padapter, mac)) {
+			RTW_INFO(FUNC_NDEV_FMT" deny by peer blacklist\n"
+				, FUNC_NDEV_ARG(ndev));
+			ret = -EINVAL;
+			goto release_plink_ctl;
+		}
+		#endif
+
+		scanned = rtw_find_network(&padapter->mlmepriv.scanned_queue, mac);
+		if (!scanned
+			|| rtw_get_passing_time_ms(scanned->last_scanned) >= mcfg->peer_sel_policy.scanr_exp_ms
+		) {
+			if (!scanned)
+				RTW_INFO(FUNC_NDEV_FMT" corresponding network not found\n", FUNC_NDEV_ARG(ndev));
+			else
+				RTW_INFO(FUNC_NDEV_FMT" corresponding network too old\n", FUNC_NDEV_ARG(ndev));
+
+			if (adapter_to_rfctl(padapter)->offch_state == OFFCHS_NONE)
+				probe_req = 1;
+
+			ret = -EINVAL;
+			goto release_plink_ctl;
+		}
+
+		#if CONFIG_RTW_MESH_ACNODE_PREVENT
+		if (plink_ctl->acnode_rsvd)
+			acnode = rtw_mesh_scanned_is_acnode_confirmed(padapter, scanned);
+		#endif
+
+		/* wpa_supplicant's auto peer will initiate peering when candidate peer is reported without max_peer_links consideration */
+		if (plink_ctl->num >= mcfg->max_peer_links + acnode ? 1 : 0) {
+			RTW_INFO(FUNC_NDEV_FMT" exceed max_peer_links:%u%s\n"
+				, FUNC_NDEV_ARG(ndev), mcfg->max_peer_links, acnode ? " acn" : "");
+			ret = -EINVAL;
+			goto release_plink_ctl;
+		}
+
+		if (!rtw_bss_is_candidate_mesh_peer(&padapter->mlmepriv.cur_network.network, &scanned->network, 1, 1)) {
+			RTW_WARN(FUNC_NDEV_FMT" corresponding network is not candidate with same ch\n"
+				, FUNC_NDEV_ARG(ndev));
+			ret = -EINVAL;
+			goto release_plink_ctl;
+		}
+
+		#if CONFIG_RTW_MESH_CTO_MGATE_BLACKLIST
+		if (!rtw_mesh_cto_mgate_network_filter(padapter, scanned)) {
+			RTW_INFO(FUNC_NDEV_FMT" peer filtered out by cto_mgate check\n"
+				, FUNC_NDEV_ARG(ndev));
+			ret = -EINVAL;
+			goto release_plink_ctl;
+		}
+		#endif
+
+		if (_rtw_mesh_plink_add(padapter, mac) == _SUCCESS) {
+			/* hook corresponding network in scan queue */
+			plink = _rtw_mesh_plink_get(padapter, mac);
+			plink->aid = params->aid;
+			plink->scanned = scanned;
+
+			#if CONFIG_RTW_MESH_ACNODE_PREVENT
+			if (acnode) {
+				RTW_INFO(FUNC_ADPT_FMT" acnode "MAC_FMT"\n"
+				, FUNC_ADPT_ARG(padapter), MAC_ARG(scanned->network.MacAddress));
+			}
+			#endif
+
+			add_new_sta = 1;
+		} else {
+			RTW_WARN(FUNC_NDEV_FMT" rtw_mesh_plink_add not success\n"
+				, FUNC_NDEV_ARG(ndev));
+			ret = -EINVAL;
+		}
+release_plink_ctl:
+		_exit_critical_bh(&(plink_ctl->lock), &irqL);
+
+		if (probe_req)
+			issue_probereq(padapter, &padapter->mlmepriv.cur_network.network.mesh_id, mac);
+
+		if (add_new_sta) {
+			struct station_info sinfo;
+
+			#ifdef CONFIG_DFS_MASTER
+			if (IS_UNDER_CAC(adapter_to_rfctl(padapter)))
+				rtw_force_stop_cac(adapter_to_rfctl(padapter), 300);
+			#endif
+
+			/* indicate new sta */
+			_rtw_memset(&sinfo, 0, sizeof(sinfo));
+			cfg80211_new_sta(ndev, mac, &sinfo, GFP_ATOMIC);
+		}
+		goto exit;
+	}
+#endif /* CONFIG_RTW_MESH */
+
+#ifdef CONFIG_TDLS
+	psta = rtw_get_stainfo(pstapriv, (u8 *)mac);
+	if (psta == NULL) {
+		psta = rtw_alloc_stainfo(pstapriv, (u8 *)mac);
+		if (psta == NULL) {
+			RTW_INFO("[%s] Alloc station for "MAC_FMT" fail\n", __FUNCTION__, MAC_ARG(mac));
+			ret = -EOPNOTSUPP;
+			goto exit;
+		}
+	}
+#endif /* CONFIG_TDLS */
+
+exit:
+	return ret;
+}
+
+static int	cfg80211_rtw_del_station(struct wiphy *wiphy, struct net_device *ndev,
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 16, 0))
+	u8 *mac
+#elif (LINUX_VERSION_CODE < KERNEL_VERSION(3, 19, 0))
+	const u8 *mac
+#else
+	struct station_del_parameters *params
+#endif
+)
+{
+	int ret = 0;
+	_irqL irqL;
+	_list	*phead, *plist;
+	u8 updated = _FALSE;
+	const u8 *target_mac;
+	struct sta_info *psta = NULL;
+	_adapter *padapter = (_adapter *)rtw_netdev_priv(ndev);
+	struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
+	struct sta_priv *pstapriv = &padapter->stapriv;
+
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 19, 0))
+	target_mac = mac;
+#else
+	target_mac = params->mac;
+#endif
+
+	RTW_INFO("+"FUNC_NDEV_FMT" mac=%pM\n", FUNC_NDEV_ARG(ndev), target_mac);
+
+	if (check_fwstate(pmlmepriv, (_FW_LINKED | WIFI_AP_STATE | WIFI_MESH_STATE)) != _TRUE) {
+		RTW_INFO("%s, fw_state != FW_LINKED|WIFI_AP_STATE|WIFI_MESH_STATE\n", __func__);
+		return -EINVAL;
+	}
+
+
+	if (!target_mac) {
+		RTW_INFO("flush all sta, and cam_entry\n");
+
+		flush_all_cam_entry(padapter);	/* clear CAM */
+
+#ifdef CONFIG_AP_MODE
+		ret = rtw_sta_flush(padapter, _TRUE);
+#endif
+		return ret;
+	}
+
+
+	RTW_INFO("free sta macaddr =" MAC_FMT "\n", MAC_ARG(target_mac));
+
+	if (target_mac[0] == 0xff && target_mac[1] == 0xff &&
+	    target_mac[2] == 0xff && target_mac[3] == 0xff &&
+	    target_mac[4] == 0xff && target_mac[5] == 0xff)
+		return -EINVAL;
+
+
+	_enter_critical_bh(&pstapriv->asoc_list_lock, &irqL);
+
+	phead = &pstapriv->asoc_list;
+	plist = get_next(phead);
+
+	/* check asoc_queue */
+	while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) {
+		psta = LIST_CONTAINOR(plist, struct sta_info, asoc_list);
+
+		plist = get_next(plist);
+
+		if (_rtw_memcmp((u8 *)target_mac, psta->cmn.mac_addr, ETH_ALEN)) {
+			if (psta->dot8021xalg == 1 && psta->bpairwise_key_installed == _FALSE)
+				RTW_INFO("%s, sta's dot8021xalg = 1 and key_installed = _FALSE\n", __func__);
+			else {
+				RTW_INFO("free psta=%p, aid=%d\n", psta, psta->cmn.aid);
+
+				rtw_list_delete(&psta->asoc_list);
+				pstapriv->asoc_list_cnt--;
+				STA_SET_MESH_PLINK(psta, NULL);
+
+				/* _exit_critical_bh(&pstapriv->asoc_list_lock, &irqL); */
+				if (MLME_IS_AP(padapter))
+					updated = ap_free_sta(padapter, psta, _TRUE, WLAN_REASON_PREV_AUTH_NOT_VALID, _TRUE);
+				else
+					updated = ap_free_sta(padapter, psta, _TRUE, WLAN_REASON_DEAUTH_LEAVING, _TRUE);
+				/* _enter_critical_bh(&pstapriv->asoc_list_lock, &irqL); */
+
+				psta = NULL;
+
+				break;
+			}
+
+		}
+
+	}
+
+	_exit_critical_bh(&pstapriv->asoc_list_lock, &irqL);
+
+	associated_clients_update(padapter, updated, STA_INFO_UPDATE_ALL);
+
+#ifdef CONFIG_RTW_MESH
+	if (MLME_IS_MESH(padapter))
+		rtw_mesh_plink_del(padapter, target_mac);
+#endif
+
+	RTW_INFO("-"FUNC_NDEV_FMT"\n", FUNC_NDEV_ARG(ndev));
+
+	return ret;
+
+}
+
+static int	cfg80211_rtw_change_station(struct wiphy *wiphy, struct net_device *ndev,
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 16, 0))
+	u8 *mac,
+#else
+	const u8 *mac,
+#endif
+	struct station_parameters *params)
+{
+#ifdef CONFIG_RTW_MESH
+	_adapter *adapter = (_adapter *)rtw_netdev_priv(ndev);
+	struct sta_priv *stapriv = &adapter->stapriv;
+	struct sta_info *sta = NULL;
+	_irqL irqL;
+#endif
+	int ret = 0;
+
+	RTW_INFO(FUNC_NDEV_FMT" mac:"MAC_FMT"\n", FUNC_NDEV_ARG(ndev), MAC_ARG(mac));
+
+	dump_station_parameters(RTW_DBGDUMP, wiphy, params);
+
+#ifdef CONFIG_RTW_MESH
+	if (MLME_IS_MESH(adapter)) {
+		enum cfg80211_station_type sta_type = CFG80211_STA_MESH_PEER_USER;
+		struct rtw_mesh_info *minfo = &adapter->mesh_info;
+		struct mesh_plink_pool *plink_ctl = &minfo->plink_ctl;
+		struct mesh_plink_ent *plink = NULL;
+		_irqL irqL2;
+		struct sta_info *del_sta = NULL;
+
+		ret = cfg80211_check_station_change(wiphy, params, sta_type);
+		if (ret) {
+			RTW_INFO("cfg80211_check_station_change return %d\n", ret);
+			goto exit;
+		}
+
+		_enter_critical_bh(&(plink_ctl->lock), &irqL2);
+
+		plink = _rtw_mesh_plink_get(adapter, mac);
+		if (!plink) {
+			ret = -ENOENT;
+			goto release_plink_ctl;
+		}
+
+		plink->plink_state = nl80211_plink_state_to_rtw_plink_state(params->plink_state);
+
+		#if CONFIG_RTW_MESH_ACNODE_PREVENT
+		if (params->plink_state == NL80211_PLINK_OPN_SNT
+			#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 10, 0))
+			&& (params->sta_modify_mask & STATION_PARAM_APPLY_PLINK_STATE)
+			#endif
+		) {
+			if (rtw_mesh_scanned_is_acnode_confirmed(adapter, plink->scanned)
+				&& rtw_mesh_acnode_prevent_allow_sacrifice(adapter)
+			) {
+				struct sta_info *sac = rtw_mesh_acnode_prevent_pick_sacrifice(adapter);
+
+				if (sac) {
+					del_sta = sac;
+					_enter_critical_bh(&stapriv->asoc_list_lock, &irqL);
+					if (!rtw_is_list_empty(&del_sta->asoc_list)) {
+						rtw_list_delete(&del_sta->asoc_list);
+						stapriv->asoc_list_cnt--;
+						STA_SET_MESH_PLINK(del_sta, NULL);
+					}
+					_exit_critical_bh(&stapriv->asoc_list_lock, &irqL);
+					RTW_INFO(FUNC_ADPT_FMT" sacrifice "MAC_FMT" for acnode\n"
+						, FUNC_ADPT_ARG(adapter), MAC_ARG(del_sta->cmn.mac_addr));
+				}
+			}
+		} else
+		#endif
+		if ((params->plink_state == NL80211_PLINK_OPN_RCVD
+				|| params->plink_state == NL80211_PLINK_CNF_RCVD
+				|| params->plink_state == NL80211_PLINK_ESTAB)
+			#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 10, 0))
+			&& (params->sta_modify_mask & STATION_PARAM_APPLY_PLINK_STATE)
+			#endif
+		) {
+			sta = rtw_get_stainfo(stapriv, mac);
+			if (!sta) {
+				sta = rtw_alloc_stainfo(stapriv, mac);
+				if (!sta)
+					goto release_plink_ctl;
+			}
+
+			if (params->plink_state == NL80211_PLINK_ESTAB) {
+				if (rtw_mesh_peer_establish(adapter, plink, sta) != _SUCCESS) {
+					rtw_free_stainfo(adapter, sta);
+					ret = -ENOENT;
+					goto release_plink_ctl;
+				}
+			}
+		}
+		else if (params->plink_state == NL80211_PLINK_HOLDING
+			#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 10, 0))
+			&& (params->sta_modify_mask & STATION_PARAM_APPLY_PLINK_STATE)
+			#endif
+		) {
+			del_sta = rtw_get_stainfo(stapriv, mac);
+			if (!del_sta)
+				goto release_plink_ctl;
+
+			_enter_critical_bh(&stapriv->asoc_list_lock, &irqL);
+			if (!rtw_is_list_empty(&del_sta->asoc_list)) {
+				rtw_list_delete(&del_sta->asoc_list);
+				stapriv->asoc_list_cnt--;
+				STA_SET_MESH_PLINK(del_sta, NULL);
+			}
+			_exit_critical_bh(&stapriv->asoc_list_lock, &irqL);
+		}
+
+release_plink_ctl:
+		_exit_critical_bh(&(plink_ctl->lock), &irqL2);
+
+		if (del_sta) {
+			u8 sta_addr[ETH_ALEN];
+			u8 updated = _FALSE;
+			
+			_rtw_memcpy(sta_addr, del_sta->cmn.mac_addr, ETH_ALEN);
+			updated = ap_free_sta(adapter, del_sta, 0, 0, 1);
+			rtw_mesh_expire_peer(stapriv->padapter, sta_addr);
+
+			associated_clients_update(adapter, updated, STA_INFO_UPDATE_ALL);
+		}
+	}
+#endif /* CONFIG_RTW_MESH */
+
+exit:
+	return ret;
+}
+
+struct sta_info *rtw_sta_info_get_by_idx(struct sta_priv *pstapriv, const int idx, u8 *asoc_list_num)
+{
+	_list	*phead, *plist;
+	struct sta_info *psta = NULL;
+	int i = 0;
+
+	phead = &pstapriv->asoc_list;
+	plist = get_next(phead);
+
+	/* check asoc_queue */
+	while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) {
+		if (idx == i)
+			psta = LIST_CONTAINOR(plist, struct sta_info, asoc_list);
+		plist = get_next(plist);
+		i++;
+	}
+
+	if (asoc_list_num)
+		*asoc_list_num = i;
+
+	return psta;
+}
+
+static int	cfg80211_rtw_dump_station(struct wiphy *wiphy, struct net_device *ndev,
+		int idx, u8 *mac, struct station_info *sinfo)
+{
+#define DBG_DUMP_STATION 0
+
+	int ret = 0;
+	_irqL irqL;
+	_adapter *padapter = (_adapter *)rtw_netdev_priv(ndev);
+	struct sta_priv *pstapriv = &padapter->stapriv;
+	struct sta_info *psta = NULL;
+#ifdef CONFIG_RTW_MESH
+	struct mesh_plink_ent *plink = NULL;
+#endif
+	u8 asoc_list_num;
+
+	if (DBG_DUMP_STATION)
+		RTW_INFO(FUNC_NDEV_FMT"\n", FUNC_NDEV_ARG(ndev));
+
+	_enter_critical_bh(&pstapriv->asoc_list_lock, &irqL);
+	psta = rtw_sta_info_get_by_idx(pstapriv, idx, &asoc_list_num);
+	_exit_critical_bh(&pstapriv->asoc_list_lock, &irqL);
+
+#ifdef CONFIG_RTW_MESH
+	if (MLME_IS_MESH(padapter)) {
+		if (psta)
+			plink = psta->plink;
+		if (!plink)
+			plink = rtw_mesh_plink_get_no_estab_by_idx(padapter, idx - asoc_list_num);
+	}
+#endif /* CONFIG_RTW_MESH */
+
+	if ((!MLME_IS_MESH(padapter) && !psta)
+		#ifdef CONFIG_RTW_MESH
+		|| (MLME_IS_MESH(padapter) && !plink)
+		#endif
+	) {
+		if (DBG_DUMP_STATION)
+			RTW_INFO(FUNC_NDEV_FMT" end with idx:%d\n", FUNC_NDEV_ARG(ndev), idx);
+		ret = -ENOENT;
+		goto exit;
+	}
+
+	if (psta)
+		_rtw_memcpy(mac, psta->cmn.mac_addr, ETH_ALEN);
+	#ifdef CONFIG_RTW_MESH
+	else
+		_rtw_memcpy(mac, plink->addr, ETH_ALEN);
+	#endif
+	
+	sinfo->filled = 0;
+
+	if (psta) {
+		sinfo->filled |= STATION_INFO_SIGNAL;
+		sinfo->signal = translate_percentage_to_dbm(psta->cmn.rssi_stat.rssi);
+		sinfo->filled |= STATION_INFO_INACTIVE_TIME;
+		sinfo->inactive_time = rtw_get_passing_time_ms(psta->sta_stats.last_rx_time);
+	}
+
+#ifdef CONFIG_RTW_MESH
+	if (MLME_IS_MESH(padapter))
+		rtw_cfg80211_fill_mesh_only_sta_info(plink, psta, sinfo);
+#endif
+
+exit:
+	return ret;
+}
+
+static int	cfg80211_rtw_change_bss(struct wiphy *wiphy, struct net_device *ndev,
+		struct bss_parameters *params)
+{
+	RTW_INFO(FUNC_NDEV_FMT"\n", FUNC_NDEV_ARG(ndev));
+/*
+	RTW_INFO("use_cts_prot=%d\n", params->use_cts_prot);
+	RTW_INFO("use_short_preamble=%d\n", params->use_short_preamble);
+	RTW_INFO("use_short_slot_time=%d\n", params->use_short_slot_time);
+	RTW_INFO("ap_isolate=%d\n", params->ap_isolate);
+
+	RTW_INFO("basic_rates_len=%d\n", params->basic_rates_len);
+	for(i = 0; i < params->basic_rates_len; i++)
+		RTW_INFO("basic_rates=%d\n", params->basic_rates[i]);
+*/
+	return 0;
+
+}
+
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 29))
+static int	cfg80211_rtw_set_txq_params(struct wiphy *wiphy
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 2, 0))
+	, struct net_device *ndev
+#endif
+	, struct ieee80211_txq_params *params)
+{
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 2, 0))
+	_adapter *padapter = rtw_netdev_priv(ndev);
+#else
+	_adapter *padapter = wiphy_to_adapter(wiphy);
+#endif
+	struct mlme_ext_priv	*pmlmeext = &padapter->mlmeextpriv;
+	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
+	u8	ac, AIFS, ECWMin, ECWMax, aSifsTime;
+	u16	TXOP;
+	u8	shift_count = 0;
+	u32	acParm;
+
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 5, 0))
+	ac = params->ac;
+#else
+	ac = params->queue;
+#endif
+
+#if 0
+	RTW_INFO("ac=%d\n", ac);
+	RTW_INFO("txop=%u\n", params->txop);
+	RTW_INFO("cwmin=%u\n", params->cwmin);
+	RTW_INFO("cwmax=%u\n", params->cwmax);
+	RTW_INFO("aifs=%u\n", params->aifs);
+#endif
+
+	if (is_supported_5g(pmlmeext->cur_wireless_mode) ||
+	    (pmlmeext->cur_wireless_mode & WIRELESS_11_24N))
+		aSifsTime = 16;
+	else
+		aSifsTime = 10;
+
+	AIFS = params->aifs * pmlmeinfo->slotTime + aSifsTime;
+
+	while ((params->cwmin + 1) >> shift_count != 1) {
+		shift_count++;
+		if (shift_count == 15)
+			break;
+	}
+
+	ECWMin = shift_count;
+
+	shift_count = 0;
+	while ((params->cwmax + 1) >> shift_count != 1) {
+		shift_count++;
+		if (shift_count == 15)
+			break;
+	}
+
+	ECWMax = shift_count;
+
+	TXOP = le16_to_cpu(params->txop);
+
+	acParm = AIFS | (ECWMin << 8) | (ECWMax << 12) | (TXOP << 16);
+
+	switch (ac) {
+	case NL80211_TXQ_Q_VO:
+		RTW_INFO(FUNC_NDEV_FMT" AC_VO = 0x%08x\n", FUNC_ADPT_ARG(padapter), acParm);
+		rtw_hal_set_hwreg(padapter, HW_VAR_AC_PARAM_VO, (u8 *)(&acParm));
+		break;
+
+	case NL80211_TXQ_Q_VI:
+		RTW_INFO(FUNC_NDEV_FMT" AC_VI = 0x%08x\n", FUNC_ADPT_ARG(padapter), acParm);
+		rtw_hal_set_hwreg(padapter, HW_VAR_AC_PARAM_VI, (u8 *)(&acParm));
+		break;
+
+	case NL80211_TXQ_Q_BE:
+		RTW_INFO(FUNC_NDEV_FMT" AC_BE = 0x%08x\n", FUNC_ADPT_ARG(padapter), acParm);
+		rtw_hal_set_hwreg(padapter, HW_VAR_AC_PARAM_BE, (u8 *)(&acParm));
+		break;
+
+	case NL80211_TXQ_Q_BK:
+		RTW_INFO(FUNC_NDEV_FMT" AC_BK = 0x%08x\n", FUNC_ADPT_ARG(padapter), acParm);
+		rtw_hal_set_hwreg(padapter, HW_VAR_AC_PARAM_BK, (u8 *)(&acParm));
+		break;
+
+	default:
+		break;
+	}
+
+	return 0;
+}
+#endif /* (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 29)) */
+
+static int	cfg80211_rtw_set_channel(struct wiphy *wiphy
+	#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 35))
+	, struct net_device *ndev
+	#endif
+	, struct ieee80211_channel *chan, enum nl80211_channel_type channel_type)
+{
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 35))
+	_adapter *padapter = (_adapter *)rtw_netdev_priv(ndev);
+#else
+	_adapter *padapter = wiphy_to_adapter(wiphy);
+#endif
+	int chan_target = (u8) ieee80211_frequency_to_channel(chan->center_freq);
+	int chan_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
+	int chan_width = CHANNEL_WIDTH_20;
+
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 35))
+	RTW_INFO(FUNC_NDEV_FMT"\n", FUNC_NDEV_ARG(ndev));
+#endif
+
+	switch (channel_type) {
+	case NL80211_CHAN_NO_HT:
+	case NL80211_CHAN_HT20:
+		chan_width = CHANNEL_WIDTH_20;
+		chan_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
+		break;
+	case NL80211_CHAN_HT40MINUS:
+		chan_width = CHANNEL_WIDTH_40;
+		chan_offset = HAL_PRIME_CHNL_OFFSET_UPPER;
+		break;
+	case NL80211_CHAN_HT40PLUS:
+		chan_width = CHANNEL_WIDTH_40;
+		chan_offset = HAL_PRIME_CHNL_OFFSET_LOWER;
+		break;
+	default:
+		chan_width = CHANNEL_WIDTH_20;
+		chan_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
+		break;
+	}
+
+	RTW_INFO(FUNC_ADPT_FMT" ch:%d bw:%d, offset:%d\n"
+		, FUNC_ADPT_ARG(padapter), chan_target, chan_width, chan_offset);
+
+	rtw_set_chbw_cmd(padapter, chan_target, chan_width, chan_offset, RTW_CMDF_WAIT_ACK);
+
+	return 0;
+}
+
+static int cfg80211_rtw_set_monitor_channel(struct wiphy *wiphy
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 8, 0))
+	, struct cfg80211_chan_def *chandef
+#else
+	, struct ieee80211_channel *chan
+	, enum nl80211_channel_type channel_type
+#endif
+)
+{
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 8, 0))
+	struct ieee80211_channel *chan = chandef->chan;
+#endif
+
+	_adapter *padapter = wiphy_to_adapter(wiphy);
+	int target_channal = chan->hw_value;
+	int target_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
+	int target_width = CHANNEL_WIDTH_20;
+
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 8, 0))
+#ifdef CONFIG_DEBUG_CFG80211
+	RTW_INFO("center_freq %u Mhz ch %u width %u freq1 %u freq2 %u\n"
+		, chan->center_freq
+		, chan->hw_value
+		, chandef->width
+		, chandef->center_freq1
+		, chandef->center_freq2);
+#endif /* CONFIG_DEBUG_CFG80211 */
+
+	switch (chandef->width) {
+	case NL80211_CHAN_WIDTH_20_NOHT:
+	case NL80211_CHAN_WIDTH_20:
+		target_width = CHANNEL_WIDTH_20;
+		target_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
+		break;
+	case NL80211_CHAN_WIDTH_40:
+		target_width = CHANNEL_WIDTH_40;
+		if (chandef->center_freq1 > chan->center_freq)
+			target_offset = HAL_PRIME_CHNL_OFFSET_LOWER;
+		else
+			target_offset = HAL_PRIME_CHNL_OFFSET_UPPER;
+		break;
+	case NL80211_CHAN_WIDTH_80:
+		target_width = CHANNEL_WIDTH_80;
+		target_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
+		break;
+	case NL80211_CHAN_WIDTH_80P80:
+		target_width = CHANNEL_WIDTH_80_80;
+		target_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
+		break;
+	case NL80211_CHAN_WIDTH_160:
+		target_width = CHANNEL_WIDTH_160;
+		target_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
+		break;
+
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 11, 0))
+	case NL80211_CHAN_WIDTH_5:
+	case NL80211_CHAN_WIDTH_10:
+#endif
+	default:
+		target_width = CHANNEL_WIDTH_20;
+		target_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
+		break;
+	}
+#else
+#ifdef CONFIG_DEBUG_CFG80211
+	RTW_INFO("center_freq %u Mhz ch %u channel_type %u\n"
+		, chan->center_freq
+		, chan->hw_value
+		, channel_type);
+#endif /* CONFIG_DEBUG_CFG80211 */
+
+	switch (channel_type) {
+	case NL80211_CHAN_NO_HT:
+	case NL80211_CHAN_HT20:
+		target_width = CHANNEL_WIDTH_20;
+		target_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
+		break;
+	case NL80211_CHAN_HT40MINUS:
+		target_width = CHANNEL_WIDTH_40;
+		target_offset = HAL_PRIME_CHNL_OFFSET_UPPER;
+		break;
+	case NL80211_CHAN_HT40PLUS:
+		target_width = CHANNEL_WIDTH_40;
+		target_offset = HAL_PRIME_CHNL_OFFSET_LOWER;
+		break;
+	default:
+		target_width = CHANNEL_WIDTH_20;
+		target_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
+		break;
+	}
+#endif
+	RTW_INFO(FUNC_ADPT_FMT" ch:%d bw:%d, offset:%d\n"
+		, FUNC_ADPT_ARG(padapter), target_channal, target_width, target_offset);
+
+	rtw_set_chbw_cmd(padapter, target_channal, target_width, target_offset, RTW_CMDF_WAIT_ACK);
+
+	return 0;
+}
+
+static int	cfg80211_rtw_auth(struct wiphy *wiphy, struct net_device *ndev,
+		struct cfg80211_auth_request *req)
+{
+	RTW_INFO(FUNC_NDEV_FMT"\n", FUNC_NDEV_ARG(ndev));
+
+	return 0;
+}
+
+static int	cfg80211_rtw_assoc(struct wiphy *wiphy, struct net_device *ndev,
+		struct cfg80211_assoc_request *req)
+{
+	RTW_INFO(FUNC_NDEV_FMT"\n", FUNC_NDEV_ARG(ndev));
+
+	return 0;
+}
+#endif /* CONFIG_AP_MODE */
+
+void rtw_cfg80211_rx_probe_request(_adapter *adapter, union recv_frame *rframe)
+{
+	struct wireless_dev *wdev = adapter->rtw_wdev;
+	u8 *frame = get_recvframe_data(rframe);
+	uint frame_len = rframe->u.hdr.len;
+	s32 freq;
+	u8 ch, sch = rtw_get_oper_ch(adapter);
+
+	ch = rframe->u.hdr.attrib.ch ? rframe->u.hdr.attrib.ch : sch;
+	freq = rtw_ch2freq(ch);
+
+#ifdef CONFIG_DEBUG_CFG80211
+	RTW_INFO("RTW_Rx: probe request, ch=%d(%d), ta="MAC_FMT"\n"
+		, ch, sch, MAC_ARG(get_addr2_ptr(frame)));
+#endif
+
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,37)) || defined(COMPAT_KERNEL_RELEASE)
+	rtw_cfg80211_rx_mgmt(wdev, freq, 0, frame, frame_len, GFP_ATOMIC);
+#else
+	cfg80211_rx_action(adapter->pnetdev, freq, frame, frame_len, GFP_ATOMIC);
+#endif
+}
+
+void rtw_cfg80211_rx_action_p2p(_adapter *adapter, union recv_frame *rframe)
+{
+	struct wireless_dev *wdev = adapter->rtw_wdev;
+	u8 *frame = get_recvframe_data(rframe);
+	uint frame_len = rframe->u.hdr.len;
+	s32 freq;
+	u8 ch, sch = rtw_get_oper_ch(adapter);
+	u8 category, action;
+	int type;
+
+	ch = rframe->u.hdr.attrib.ch ? rframe->u.hdr.attrib.ch : sch;
+	freq = rtw_ch2freq(ch);
+
+	RTW_INFO("RTW_Rx:ch=%d(%d), ta="MAC_FMT"\n"
+		, ch, sch, MAC_ARG(get_addr2_ptr(frame)));
+#ifdef CONFIG_P2P
+	type = rtw_p2p_check_frames(adapter, frame, frame_len, _FALSE);
+	if (type >= 0)
+		goto indicate;
+#endif
+	rtw_action_frame_parse(frame, frame_len, &category, &action);
+	RTW_INFO("RTW_Rx:category(%u), action(%u)\n", category, action);
+
+indicate:
+
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) || defined(COMPAT_KERNEL_RELEASE)
+	rtw_cfg80211_rx_mgmt(wdev, freq, 0, frame, frame_len, GFP_ATOMIC);
+#else
+	cfg80211_rx_action(adapter->pnetdev, freq, frame, frame_len, GFP_ATOMIC);
+#endif
+}
+
+void rtw_cfg80211_rx_p2p_action_public(_adapter *adapter, union recv_frame *rframe)
+{
+	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
+	struct wireless_dev *wdev = adapter->rtw_wdev;
+	struct rtw_wdev_priv *pwdev_priv = adapter_wdev_data(adapter);
+	u8 *frame = get_recvframe_data(rframe);
+	uint frame_len = rframe->u.hdr.len;
+	s32 freq;
+	u8 ch, sch = rtw_get_oper_ch(adapter);
+	u8 category, action;
+	int type;
+
+	ch = rframe->u.hdr.attrib.ch ? rframe->u.hdr.attrib.ch : sch;
+	freq = rtw_ch2freq(ch);
+
+	RTW_INFO("RTW_Rx:ch=%d(%d), ta="MAC_FMT"\n"
+		, ch, sch, MAC_ARG(get_addr2_ptr(frame)));
+	#ifdef CONFIG_P2P
+	type = rtw_p2p_check_frames(adapter, frame, frame_len, _FALSE);
+	if (type >= 0) {
+		switch (type) {
+		case P2P_GO_NEGO_CONF:
+			if (0) {
+				RTW_INFO(FUNC_ADPT_FMT" Nego confirm. state=%u, status=%u, iaddr="MAC_FMT"\n"
+					, FUNC_ADPT_ARG(adapter), pwdev_priv->nego_info.state, pwdev_priv->nego_info.status
+					, MAC_ARG(pwdev_priv->nego_info.iface_addr));
+			}
+			if (pwdev_priv->nego_info.state == 2
+				&& pwdev_priv->nego_info.status == 0
+				&& rtw_check_invalid_mac_address(pwdev_priv->nego_info.iface_addr, _FALSE) == _FALSE
+			) {
+				_adapter *intended_iface = dvobj_get_adapter_by_addr(dvobj, pwdev_priv->nego_info.iface_addr);
+
+				if (intended_iface) {
+					RTW_INFO(FUNC_ADPT_FMT" Nego confirm. Allow only "ADPT_FMT" to scan for 2000 ms\n"
+						, FUNC_ADPT_ARG(adapter), ADPT_ARG(intended_iface));
+					/* allow only intended_iface to do scan for 2000 ms */
+					rtw_mi_set_scan_deny(adapter, 2000);
+					rtw_clear_scan_deny(intended_iface);
+				}
+			}
+			break;
+		case P2P_PROVISION_DISC_RESP:
+		case P2P_INVIT_RESP:
+			rtw_clear_scan_deny(adapter);
+			#if !RTW_P2P_GROUP_INTERFACE
+			rtw_mi_buddy_set_scan_deny(adapter, 2000);
+			#endif
+			break;
+		}
+		goto indicate;
+	}
+	#endif
+	rtw_action_frame_parse(frame, frame_len, &category, &action);
+	RTW_INFO("RTW_Rx:category(%u), action(%u)\n", category, action);
+
+indicate:
+	#if defined(RTW_DEDICATED_P2P_DEVICE)
+	if (rtw_cfg80211_redirect_pd_wdev(dvobj_to_wiphy(dvobj), get_ra(frame), &wdev))
+		if (0)
+			RTW_INFO("redirect to pd_wdev:%p\n", wdev);
+	#endif
+
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) || defined(COMPAT_KERNEL_RELEASE)
+	rtw_cfg80211_rx_mgmt(wdev, freq, 0, frame, frame_len, GFP_ATOMIC);
+#else
+	cfg80211_rx_action(adapter->pnetdev, freq, frame, frame_len, GFP_ATOMIC);
+#endif
+}
+
+void rtw_cfg80211_rx_action(_adapter *adapter, union recv_frame *rframe, const char *msg)
+{
+	struct wireless_dev *wdev = adapter->rtw_wdev;
+	u8 *frame = get_recvframe_data(rframe);
+	uint frame_len = rframe->u.hdr.len;
+	s32 freq;
+	u8 ch, sch = rtw_get_oper_ch(adapter);
+	u8 category, action;
+	int type = -1;
+
+	ch = rframe->u.hdr.attrib.ch ? rframe->u.hdr.attrib.ch : sch;
+	freq = rtw_ch2freq(ch);
+
+	RTW_INFO("RTW_Rx:ch=%d(%d), ta="MAC_FMT"\n"
+		, ch, sch, MAC_ARG(get_addr2_ptr(frame)));
+
+#ifdef CONFIG_RTW_MESH
+	if (MLME_IS_MESH(adapter)) {
+		type = rtw_mesh_check_frames_rx(adapter, frame, frame_len);
+		if (type >= 0)
+			goto indicate;
+	}
+#endif
+	rtw_action_frame_parse(frame, frame_len, &category, &action);
+	if (category == RTW_WLAN_CATEGORY_PUBLIC) {
+		if (action == ACT_PUBLIC_GAS_INITIAL_REQ) {
+			rtw_mi_set_scan_deny(adapter, 200);
+			rtw_mi_scan_abort(adapter, _FALSE); /*rtw_scan_abort_no_wait*/
+		}
+	}
+
+indicate:
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) || defined(COMPAT_KERNEL_RELEASE)
+	rtw_cfg80211_rx_mgmt(wdev, freq, 0, frame, frame_len, GFP_ATOMIC);
+#else
+	cfg80211_rx_action(adapter->pnetdev, freq, frame, frame_len, GFP_ATOMIC);
+#endif
+
+	if (type == -1) {
+		if (msg)
+			RTW_INFO("RTW_Rx:%s\n", msg);
+		else
+			RTW_INFO("RTW_Rx:category(%u), action(%u)\n", category, action);
+	}
+}
+
+#ifdef CONFIG_RTW_80211K
+void rtw_cfg80211_rx_rrm_action(_adapter *adapter, union recv_frame *rframe)
+{
+	struct wireless_dev *wdev = adapter->rtw_wdev;
+	u8 *frame = get_recvframe_data(rframe);
+	uint frame_len = rframe->u.hdr.len;
+	s32 freq;
+	u8 ch, sch = rtw_get_oper_ch(adapter);
+
+	ch = rframe->u.hdr.attrib.ch ? rframe->u.hdr.attrib.ch : sch;
+	freq = rtw_ch2freq(ch);
+
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) || defined(COMPAT_KERNEL_RELEASE)
+	rtw_cfg80211_rx_mgmt(wdev, freq, 0, frame, frame_len, GFP_ATOMIC);
+#else
+	cfg80211_rx_action(adapter->pnetdev, freq, frame, frame_len, GFP_ATOMIC);
+#endif
+	RTW_INFO("RTW_Rx:ch=%d(%d), ta="MAC_FMT"\n"
+		, ch, sch, MAC_ARG(get_addr2_ptr(frame)));
+}
+#endif /* CONFIG_RTW_80211K */
+
+void rtw_cfg80211_rx_mframe(_adapter *adapter, union recv_frame *rframe, const char *msg)
+{
+	struct wireless_dev *wdev = adapter->rtw_wdev;
+	u8 *frame = get_recvframe_data(rframe);
+	uint frame_len = rframe->u.hdr.len;
+	s32 freq;
+	u8 ch, sch = rtw_get_oper_ch(adapter);
+
+	ch = rframe->u.hdr.attrib.ch ? rframe->u.hdr.attrib.ch : sch;
+	freq = rtw_ch2freq(ch);
+
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) || defined(COMPAT_KERNEL_RELEASE)
+	rtw_cfg80211_rx_mgmt(wdev, freq, 0, frame, frame_len, GFP_ATOMIC);
+#else
+	cfg80211_rx_action(adapter->pnetdev, freq, frame, frame_len, GFP_ATOMIC);
+#endif
+
+	RTW_INFO("RTW_Rx:ch=%d(%d), ta="MAC_FMT"\n", ch, sch, MAC_ARG(get_addr2_ptr(frame)));
+	#ifdef CONFIG_RTW_MESH
+	if (!rtw_sae_check_frames(adapter, frame, frame_len, _FALSE))
+	#endif
+	{
+		if (msg)
+			RTW_INFO("RTW_Rx:%s\n", msg);
+		else
+			RTW_INFO("RTW_Rx:frame_control:0x%02x\n", le16_to_cpu(((struct rtw_ieee80211_hdr_3addr *)rframe)->frame_ctl));
+	}
+}
+
+#ifdef CONFIG_P2P
+void rtw_cfg80211_issue_p2p_provision_request(_adapter *padapter, const u8 *buf, size_t len)
+{
+	u16	wps_devicepassword_id = 0x0000;
+	uint	wps_devicepassword_id_len = 0;
+	u8			wpsie[255] = { 0x00 }, p2p_ie[255] = { 0x00 };
+	uint			p2p_ielen = 0;
+	uint			wpsielen = 0;
+	u32	devinfo_contentlen = 0;
+	u8	devinfo_content[64] = { 0x00 };
+	u16	capability = 0;
+	uint capability_len = 0;
+
+	unsigned char category = RTW_WLAN_CATEGORY_PUBLIC;
+	u8			action = P2P_PUB_ACTION_ACTION;
+	u8			dialogToken = 1;
+	u32			p2poui = cpu_to_be32(P2POUI);
+	u8			oui_subtype = P2P_PROVISION_DISC_REQ;
+	u32			p2pielen = 0;
+#ifdef CONFIG_WFD
+	u32					wfdielen = 0;
+#endif
+
+	struct xmit_frame			*pmgntframe;
+	struct pkt_attrib			*pattrib;
+	unsigned char					*pframe;
+	struct rtw_ieee80211_hdr	*pwlanhdr;
+	unsigned short				*fctrl;
+	struct xmit_priv			*pxmitpriv = &(padapter->xmitpriv);
+	struct mlme_ext_priv	*pmlmeext = &(padapter->mlmeextpriv);
+
+	struct wifidirect_info *pwdinfo = &(padapter->wdinfo);
+	u8 *frame_body = (unsigned char *)(buf + sizeof(struct rtw_ieee80211_hdr_3addr));
+	size_t frame_body_len = len - sizeof(struct rtw_ieee80211_hdr_3addr);
+
+
+	RTW_INFO("[%s] In\n", __FUNCTION__);
+
+	/* prepare for building provision_request frame	 */
+	_rtw_memcpy(pwdinfo->tx_prov_disc_info.peerIFAddr, GetAddr1Ptr(buf), ETH_ALEN);
+	_rtw_memcpy(pwdinfo->tx_prov_disc_info.peerDevAddr, GetAddr1Ptr(buf), ETH_ALEN);
+
+	pwdinfo->tx_prov_disc_info.wps_config_method_request = WPS_CM_PUSH_BUTTON;
+
+	rtw_get_wps_ie(frame_body + _PUBLIC_ACTION_IE_OFFSET_, frame_body_len - _PUBLIC_ACTION_IE_OFFSET_, wpsie, &wpsielen);
+	rtw_get_wps_attr_content(wpsie, wpsielen, WPS_ATTR_DEVICE_PWID, (u8 *) &wps_devicepassword_id, &wps_devicepassword_id_len);
+	wps_devicepassword_id = be16_to_cpu(wps_devicepassword_id);
+
+	switch (wps_devicepassword_id) {
+	case WPS_DPID_PIN:
+		pwdinfo->tx_prov_disc_info.wps_config_method_request = WPS_CM_LABEL;
+		break;
+	case WPS_DPID_USER_SPEC:
+		pwdinfo->tx_prov_disc_info.wps_config_method_request = WPS_CM_DISPLYA;
+		break;
+	case WPS_DPID_MACHINE_SPEC:
+		break;
+	case WPS_DPID_REKEY:
+		break;
+	case WPS_DPID_PBC:
+		pwdinfo->tx_prov_disc_info.wps_config_method_request = WPS_CM_PUSH_BUTTON;
+		break;
+	case WPS_DPID_REGISTRAR_SPEC:
+		pwdinfo->tx_prov_disc_info.wps_config_method_request = WPS_CM_KEYPAD;
+		break;
+	default:
+		break;
+	}
+
+
+	if (rtw_get_p2p_ie(frame_body + _PUBLIC_ACTION_IE_OFFSET_, frame_body_len - _PUBLIC_ACTION_IE_OFFSET_, p2p_ie, &p2p_ielen)) {
+
+		rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_DEVICE_INFO, devinfo_content, &devinfo_contentlen);
+		rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_CAPABILITY, (u8 *)&capability, &capability_len);
+
+	}
+
+
+	/* start to build provision_request frame	 */
+	_rtw_memset(wpsie, 0, sizeof(wpsie));
+	_rtw_memset(p2p_ie, 0, sizeof(p2p_ie));
+	p2p_ielen = 0;
+
+	pmgntframe = alloc_mgtxmitframe(pxmitpriv);
+	if (pmgntframe == NULL)
+		return;
+
+
+	/* update attribute */
+	pattrib = &pmgntframe->attrib;
+	update_mgntframe_attrib(padapter, pattrib);
+
+	_rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET);
+
+	pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET;
+	pwlanhdr = (struct rtw_ieee80211_hdr *)pframe;
+
+	fctrl = &(pwlanhdr->frame_ctl);
+	*(fctrl) = 0;
+
+	_rtw_memcpy(pwlanhdr->addr1, pwdinfo->tx_prov_disc_info.peerDevAddr, ETH_ALEN);
+	_rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN);
+	_rtw_memcpy(pwlanhdr->addr3, pwdinfo->tx_prov_disc_info.peerDevAddr, ETH_ALEN);
+
+	SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq);
+	pmlmeext->mgnt_seq++;
+	set_frame_sub_type(pframe, WIFI_ACTION);
+
+	pframe += sizeof(struct rtw_ieee80211_hdr_3addr);
+	pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr);
+
+	pframe = rtw_set_fixed_ie(pframe, 1, &(category), &(pattrib->pktlen));
+	pframe = rtw_set_fixed_ie(pframe, 1, &(action), &(pattrib->pktlen));
+	pframe = rtw_set_fixed_ie(pframe, 4, (unsigned char *) &(p2poui), &(pattrib->pktlen));
+	pframe = rtw_set_fixed_ie(pframe, 1, &(oui_subtype), &(pattrib->pktlen));
+	pframe = rtw_set_fixed_ie(pframe, 1, &(dialogToken), &(pattrib->pktlen));
+
+
+	/* build_prov_disc_request_p2p_ie	 */
+	/*	P2P OUI */
+	p2pielen = 0;
+	p2p_ie[p2pielen++] = 0x50;
+	p2p_ie[p2pielen++] = 0x6F;
+	p2p_ie[p2pielen++] = 0x9A;
+	p2p_ie[p2pielen++] = 0x09;	/*	WFA P2P v1.0 */
+
+	/*	Commented by Albert 20110301 */
+	/*	According to the P2P Specification, the provision discovery request frame should contain 3 P2P attributes */
+	/*	1. P2P Capability */
+	/*	2. Device Info */
+	/*	3. Group ID ( When joining an operating P2P Group ) */
+
+	/*	P2P Capability ATTR */
+	/*	Type:	 */
+	p2p_ie[p2pielen++] = P2P_ATTR_CAPABILITY;
+
+	/*	Length: */
+	/* *(u16*) ( p2pie + p2pielen ) = cpu_to_le16( 0x0002 ); */
+	RTW_PUT_LE16(p2p_ie + p2pielen, 0x0002);
+	p2pielen += 2;
+
+	/*	Value: */
+	/*	Device Capability Bitmap, 1 byte */
+	/*	Group Capability Bitmap, 1 byte */
+	_rtw_memcpy(p2p_ie + p2pielen, &capability, 2);
+	p2pielen += 2;
+
+
+	/*	Device Info ATTR */
+	/*	Type: */
+	p2p_ie[p2pielen++] = P2P_ATTR_DEVICE_INFO;
+
+	/*	Length: */
+	/*	21->P2P Device Address (6bytes) + Config Methods (2bytes) + Primary Device Type (8bytes)  */
+	/*	+ NumofSecondDevType (1byte) + WPS Device Name ID field (2bytes) + WPS Device Name Len field (2bytes) */
+	/* *(u16*) ( p2pie + p2pielen ) = cpu_to_le16( 21 + pwdinfo->device_name_len ); */
+	RTW_PUT_LE16(p2p_ie + p2pielen, devinfo_contentlen);
+	p2pielen += 2;
+
+	/*	Value: */
+	_rtw_memcpy(p2p_ie + p2pielen, devinfo_content, devinfo_contentlen);
+	p2pielen += devinfo_contentlen;
+
+
+	pframe = rtw_set_ie(pframe, _VENDOR_SPECIFIC_IE_, p2pielen, (unsigned char *) p2p_ie, &p2p_ielen);
+	/* p2pielen = build_prov_disc_request_p2p_ie( pwdinfo, pframe, NULL, 0, pwdinfo->tx_prov_disc_info.peerDevAddr); */
+	/* pframe += p2pielen; */
+	pattrib->pktlen += p2p_ielen;
+
+	wpsielen = 0;
+	/*	WPS OUI */
+	*(u32 *)(wpsie) = cpu_to_be32(WPSOUI);
+	wpsielen += 4;
+
+	/*	WPS version */
+	/*	Type: */
+	*(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_ATTR_VER1);
+	wpsielen += 2;
+
+	/*	Length: */
+	*(u16 *)(wpsie + wpsielen) = cpu_to_be16(0x0001);
+	wpsielen += 2;
+
+	/*	Value: */
+	wpsie[wpsielen++] = WPS_VERSION_1;	/*	Version 1.0 */
+
+	/*	Config Method */
+	/*	Type: */
+	*(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_ATTR_CONF_METHOD);
+	wpsielen += 2;
+
+	/*	Length: */
+	*(u16 *)(wpsie + wpsielen) = cpu_to_be16(0x0002);
+	wpsielen += 2;
+
+	/*	Value: */
+	*(u16 *)(wpsie + wpsielen) = cpu_to_be16(pwdinfo->tx_prov_disc_info.wps_config_method_request);
+	wpsielen += 2;
+
+	pframe = rtw_set_ie(pframe, _VENDOR_SPECIFIC_IE_, wpsielen, (unsigned char *) wpsie, &pattrib->pktlen);
+
+
+#ifdef CONFIG_WFD
+	wfdielen = build_provdisc_req_wfd_ie(pwdinfo, pframe);
+	pframe += wfdielen;
+	pattrib->pktlen += wfdielen;
+#endif
+
+	pattrib->last_txcmdsz = pattrib->pktlen;
+
+	/* dump_mgntframe(padapter, pmgntframe); */
+	if (dump_mgntframe_and_wait_ack(padapter, pmgntframe) != _SUCCESS)
+		RTW_INFO("%s, ack to\n", __func__);
+
+	#if 0
+	if(wps_devicepassword_id == WPS_DPID_REGISTRAR_SPEC) {
+		RTW_INFO("waiting for p2p peer key-in PIN CODE\n");
+		rtw_msleep_os(15000); /* 15 sec for key in PIN CODE, workaround for GS2 before issuing Nego Req. */
+	}
+	#endif
+
+}
+
+#ifdef CONFIG_RTW_80211R
+static s32 cfg80211_rtw_update_ft_ies(struct wiphy *wiphy,
+	struct net_device *ndev,
+	struct cfg80211_update_ft_ies_params *ftie)
+{
+	_adapter *padapter = NULL;
+	struct mlme_priv *pmlmepriv = NULL;
+	struct ft_roam_info *pft_roam = NULL;
+	_irqL irqL;
+	u8 *p;
+	u8 *pie = NULL;
+	u32 ie_len = 0;
+
+	if (ndev == NULL)
+		return  -EINVAL;
+
+	padapter = (_adapter *)rtw_netdev_priv(ndev);
+	pmlmepriv = &(padapter->mlmepriv);
+	pft_roam = &(pmlmepriv->ft_roam);
+
+	p = (u8 *)ftie->ie;
+	if (ftie->ie_len <= sizeof(pft_roam->updated_ft_ies)) {
+		_enter_critical_bh(&pmlmepriv->lock, &irqL);
+		_rtw_memcpy(pft_roam->updated_ft_ies, ftie->ie, ftie->ie_len);
+		pft_roam->updated_ft_ies_len = ftie->ie_len;
+		_exit_critical_bh(&pmlmepriv->lock, &irqL);
+	} else {
+		RTW_ERR("FTIEs parsing fail!\n");
+		return -EINVAL;
+	}
+
+	if (rtw_ft_roam_status(padapter, RTW_FT_AUTHENTICATED_STA)) {
+		RTW_PRINT("auth success, start reassoc\n");
+		rtw_ft_lock_set_status(padapter, RTW_FT_ASSOCIATING_STA, &irqL);
+		start_clnt_assoc(padapter);
+	}
+
+	return 0;
+}
+#endif
+
+inline void rtw_cfg80211_set_is_roch(_adapter *adapter, bool val)
+{
+	adapter->cfg80211_wdinfo.is_ro_ch = val;
+	rtw_mi_update_iface_status(&(adapter->mlmepriv), 0);
+}
+
+inline bool rtw_cfg80211_get_is_roch(_adapter *adapter)
+{
+	return adapter->cfg80211_wdinfo.is_ro_ch;
+}
+
+inline bool rtw_cfg80211_is_ro_ch_once(_adapter *adapter)
+{
+	return adapter->cfg80211_wdinfo.last_ro_ch_time ? 1 : 0;
+}
+
+inline void rtw_cfg80211_set_last_ro_ch_time(_adapter *adapter)
+{
+	adapter->cfg80211_wdinfo.last_ro_ch_time = rtw_get_current_time();
+
+	if (!adapter->cfg80211_wdinfo.last_ro_ch_time)
+		adapter->cfg80211_wdinfo.last_ro_ch_time++;
+}
+
+inline s32 rtw_cfg80211_get_last_ro_ch_passing_ms(_adapter *adapter)
+{
+	return rtw_get_passing_time_ms(adapter->cfg80211_wdinfo.last_ro_ch_time);
+}
+
+static s32 cfg80211_rtw_remain_on_channel(struct wiphy *wiphy,
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 6, 0))
+	struct wireless_dev *wdev,
+#else
+	struct net_device *ndev,
+#endif
+	struct ieee80211_channel *channel,
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 8, 0))
+	enum nl80211_channel_type channel_type,
+#endif
+	unsigned int duration, u64 *cookie)
+{
+	s32 err = 0;
+	u8 remain_ch = (u8) ieee80211_frequency_to_channel(channel->center_freq);
+	_adapter *padapter = NULL;
+	struct rtw_wdev_priv *pwdev_priv;
+	struct wifidirect_info *pwdinfo;
+	struct cfg80211_wifidirect_info *pcfg80211_wdinfo;
+#ifdef CONFIG_CONCURRENT_MODE
+	u8 is_p2p_find = _FALSE;
+#endif
+
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 6, 0))
+	#if defined(RTW_DEDICATED_P2P_DEVICE)
+	if (wdev == wiphy_to_pd_wdev(wiphy))
+		padapter = wiphy_to_adapter(wiphy);
+	else
+	#endif
+	if (wdev_to_ndev(wdev))
+		padapter = (_adapter *)rtw_netdev_priv(wdev_to_ndev(wdev));
+	else {
+		err = -EINVAL;
+		goto exit;
+	}
+#else
+	struct wireless_dev *wdev;
+
+	if (ndev == NULL) {
+		err = -EINVAL;
+		goto exit;
+	}
+	padapter = (_adapter *)rtw_netdev_priv(ndev);
+	wdev = ndev_to_wdev(ndev);
+#endif
+
+	pwdev_priv = adapter_wdev_data(padapter);
+	pwdinfo = &padapter->wdinfo;
+	pcfg80211_wdinfo = &padapter->cfg80211_wdinfo;
+#ifdef CONFIG_CONCURRENT_MODE
+	is_p2p_find = (duration < (pwdinfo->ext_listen_interval)) ? _TRUE : _FALSE;
+#endif
+
+	*cookie = ATOMIC_INC_RETURN(&pcfg80211_wdinfo->ro_ch_cookie_gen);
+
+	RTW_INFO(FUNC_ADPT_FMT"%s ch:%u duration:%d, cookie:0x%llx\n"
+		, FUNC_ADPT_ARG(padapter), wdev == wiphy_to_pd_wdev(wiphy) ? " PD" : ""
+		, remain_ch, duration, *cookie);
+
+	if (rtw_chset_search_ch(adapter_to_chset(padapter), remain_ch) < 0) {
+		RTW_WARN(FUNC_ADPT_FMT" invalid ch:%u\n", FUNC_ADPT_ARG(padapter), remain_ch);
+		err = -EFAULT;
+		goto exit;
+	}
+
+#ifdef CONFIG_MP_INCLUDED
+	if (rtw_mp_mode_check(padapter)) {
+		RTW_INFO("MP mode block remain_on_channel request\n");
+		err = -EFAULT;
+		goto exit;
+	}
+#endif
+
+	if (_FAIL == rtw_pwr_wakeup(padapter)) {
+		err = -EFAULT;
+		goto exit;
+	}
+
+	rtw_scan_abort(padapter);
+#ifdef CONFIG_CONCURRENT_MODE
+	/*don't scan_abort during p2p_listen.*/
+	if (is_p2p_find)
+		rtw_mi_buddy_scan_abort(padapter, _TRUE);
+#endif /*CONFIG_CONCURRENT_MODE*/
+
+	if (rtw_cfg80211_get_is_roch(padapter) == _TRUE) {
+		_cancel_timer_ex(&padapter->cfg80211_wdinfo.remain_on_ch_timer);
+		p2p_cancel_roch_cmd(padapter, 0, NULL, RTW_CMDF_WAIT_ACK);
+	}
+
+	/* if(!rtw_p2p_chk_role(pwdinfo, P2P_ROLE_CLIENT) && !rtw_p2p_chk_role(pwdinfo, P2P_ROLE_GO)) */
+	if (rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE)) {
+		rtw_p2p_enable(padapter, P2P_ROLE_DEVICE);
+		padapter->wdinfo.listen_channel = remain_ch;
+		RTW_INFO(FUNC_ADPT_FMT" init listen_channel %u\n"
+			, FUNC_ADPT_ARG(padapter), padapter->wdinfo.listen_channel);
+	} else if (rtw_p2p_chk_state(pwdinfo , P2P_STATE_LISTEN)
+		&& (time_after_eq(rtw_get_current_time(), pwdev_priv->probe_resp_ie_update_time)
+			&& rtw_get_passing_time_ms(pwdev_priv->probe_resp_ie_update_time) < 50)
+	) {
+		if (padapter->wdinfo.listen_channel != remain_ch) {
+			padapter->wdinfo.listen_channel = remain_ch;
+			RTW_INFO(FUNC_ADPT_FMT" update listen_channel %u\n"
+				, FUNC_ADPT_ARG(padapter), padapter->wdinfo.listen_channel);
+		}
+	} else {
+		rtw_p2p_set_pre_state(pwdinfo, rtw_p2p_state(pwdinfo));
+#ifdef CONFIG_DEBUG_CFG80211
+		RTW_INFO("%s, role=%d, p2p_state=%d\n", __func__, rtw_p2p_role(pwdinfo), rtw_p2p_state(pwdinfo));
+#endif
+	}
+
+	rtw_p2p_set_state(pwdinfo, P2P_STATE_LISTEN);
+
+	#ifdef RTW_ROCH_DURATION_ENLARGE
+	if (duration < 400)
+		duration = duration * 3; /* extend from exper */
+	#endif
+
+#if defined(RTW_ROCH_BACK_OP) && defined(CONFIG_CONCURRENT_MODE)
+	if (rtw_mi_check_status(padapter, MI_LINKED)) {
+		if (is_p2p_find) /* p2p_find , duration<1000 */
+			duration = duration + pwdinfo->ext_listen_interval;
+		else /* p2p_listen, duration=5000 */
+			duration = pwdinfo->ext_listen_interval + (pwdinfo->ext_listen_interval / 4);
+	}
+#endif /*defined (RTW_ROCH_BACK_OP) && defined(CONFIG_CONCURRENT_MODE) */
+
+	rtw_cfg80211_set_is_roch(padapter, _TRUE);
+	pcfg80211_wdinfo->ro_ch_wdev = wdev;
+	pcfg80211_wdinfo->remain_on_ch_cookie = *cookie;
+	rtw_cfg80211_set_last_ro_ch_time(padapter);
+	_rtw_memcpy(&pcfg80211_wdinfo->remain_on_ch_channel, channel, sizeof(struct ieee80211_channel));
+	#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 8, 0))
+	pcfg80211_wdinfo->remain_on_ch_type = channel_type;
+	#endif
+	pcfg80211_wdinfo->restore_channel = rtw_get_oper_ch(padapter);
+
+	p2p_roch_cmd(padapter, *cookie, wdev, channel, pcfg80211_wdinfo->remain_on_ch_type,
+		duration, RTW_CMDF_WAIT_ACK);
+
+	rtw_cfg80211_ready_on_channel(wdev, *cookie, channel, channel_type, duration, GFP_KERNEL);
+exit:
+	return err;
+}
+
+static s32 cfg80211_rtw_cancel_remain_on_channel(struct wiphy *wiphy,
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 6, 0))
+	struct wireless_dev *wdev,
+#else
+	struct net_device *ndev,
+#endif
+	u64 cookie)
+{
+	s32 err = 0;
+	_adapter *padapter;
+	struct rtw_wdev_priv *pwdev_priv;
+	struct wifidirect_info *pwdinfo;
+	struct cfg80211_wifidirect_info *pcfg80211_wdinfo;
+
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 6, 0))
+	#if defined(RTW_DEDICATED_P2P_DEVICE)
+	if (wdev == wiphy_to_pd_wdev(wiphy))
+		padapter = wiphy_to_adapter(wiphy);
+	else
+	#endif
+	if (wdev_to_ndev(wdev))
+		padapter = (_adapter *)rtw_netdev_priv(wdev_to_ndev(wdev));
+	else {
+		err = -EINVAL;
+		goto exit;
+	}
+#else
+	struct wireless_dev *wdev;
+
+	if (ndev == NULL) {
+		err = -EINVAL;
+		goto exit;
+	}
+	padapter = (_adapter *)rtw_netdev_priv(ndev);
+	wdev = ndev_to_wdev(ndev);
+#endif
+
+	pwdev_priv = adapter_wdev_data(padapter);
+	pwdinfo = &padapter->wdinfo;
+	pcfg80211_wdinfo = &padapter->cfg80211_wdinfo;
+
+	RTW_INFO(FUNC_ADPT_FMT"%s cookie:0x%llx\n"
+		, FUNC_ADPT_ARG(padapter), wdev == wiphy_to_pd_wdev(wiphy) ? " PD" : ""
+		, cookie);
+
+	if (rtw_cfg80211_get_is_roch(padapter) == _TRUE) {
+		_cancel_timer_ex(&padapter->cfg80211_wdinfo.remain_on_ch_timer);
+		p2p_cancel_roch_cmd(padapter, cookie, wdev, RTW_CMDF_WAIT_ACK);
+	}
+
+exit:
+	return err;
+}
+
+inline int rtw_cfg80211_iface_has_p2p_group_cap(_adapter *adapter)
+{
+#if RTW_P2P_GROUP_INTERFACE
+	if (is_primary_adapter(adapter))
+		return 0;
+#endif
+	return 1;
+}
+
+inline int rtw_cfg80211_is_p2p_scan(_adapter *adapter)
+{
+#if RTW_P2P_GROUP_INTERFACE
+	if (rtw_cfg80211_iface_has_p2p_group_cap(adapter))
+#endif
+	{
+		struct wifidirect_info *wdinfo = &adapter->wdinfo;
+
+		return rtw_p2p_chk_state(wdinfo, P2P_STATE_SCAN)
+			|| rtw_p2p_chk_state(wdinfo, P2P_STATE_FIND_PHASE_SEARCH);
+	}
+
+#if RTW_P2P_GROUP_INTERFACE
+	#if defined(RTW_DEDICATED_P2P_DEVICE)
+	if (wiphy_to_pd_wdev(adapter_to_wiphy(adapter))) /* pd_wdev exist */
+		return rtw_cfg80211_is_scan_by_pd_wdev(adapter);
+	#endif
+	{
+		/*
+		* For 2 RTW_P2P_GROUP_INTERFACE cases:
+		* 1. RTW_DEDICATED_P2P_DEVICE defined but upper layer don't use pd_wdev or
+		* 2. RTW_DEDICATED_P2P_DEVICE not defined
+		*/
+		struct rtw_wdev_priv *wdev_data = adapter_wdev_data(adapter);
+		_irqL irqL;
+		int is_p2p_scan = 0;
+
+		_enter_critical_bh(&wdev_data->scan_req_lock, &irqL);
+		if (wdev_data->scan_request
+			&& wdev_data->scan_request->ssids
+			&& wdev_data->scan_request->ie
+		) {
+			if (_rtw_memcmp(wdev_data->scan_request->ssids->ssid, "DIRECT-", 7)
+				&& rtw_get_p2p_ie((u8 *)wdev_data->scan_request->ie, wdev_data->scan_request->ie_len, NULL, NULL))
+				is_p2p_scan = 1;
+		}
+		_exit_critical_bh(&wdev_data->scan_req_lock, &irqL);
+
+		return is_p2p_scan;
+	}
+#endif
+}
+
+#if defined(RTW_DEDICATED_P2P_DEVICE)
+int rtw_pd_iface_alloc(struct wiphy *wiphy, const char *name, struct wireless_dev **pd_wdev)
+{
+	struct rtw_wiphy_data *wiphy_data = rtw_wiphy_priv(wiphy);
+	struct wireless_dev *wdev = NULL;
+	struct rtw_netdev_priv_indicator *npi;
+	_adapter *primary_adpt = wiphy_to_adapter(wiphy);
+	int ret = 0;
+
+	if (wiphy_data->pd_wdev) {
+		RTW_WARN(FUNC_WIPHY_FMT" pd_wdev already exists\n", FUNC_WIPHY_ARG(wiphy));
+		ret = -EBUSY;
+		goto exit;
+	}
+
+	wdev = (struct wireless_dev *)rtw_zmalloc(sizeof(struct wireless_dev));
+	if (!wdev) {
+		RTW_WARN(FUNC_WIPHY_FMT" allocate wdev fail\n", FUNC_WIPHY_ARG(wiphy));
+		ret = -ENOMEM;
+		goto exit;
+	}
+
+	wdev->wiphy = wiphy;
+	wdev->iftype = NL80211_IFTYPE_P2P_DEVICE;
+	_rtw_memcpy(wdev->address, adapter_mac_addr(primary_adpt), ETH_ALEN);
+
+	wiphy_data->pd_wdev = wdev;
+	*pd_wdev = wdev;
+
+	RTW_INFO(FUNC_WIPHY_FMT" pd_wdev:%p, addr="MAC_FMT" added\n"
+		, FUNC_WIPHY_ARG(wiphy), wdev, MAC_ARG(wdev_address(wdev)));
+
+exit:
+	if (ret && wdev) {
+		rtw_mfree((u8 *)wdev, sizeof(struct wireless_dev));
+		wdev = NULL;
+	}
+
+	return ret;
+}
+
+void rtw_pd_iface_free(struct wiphy *wiphy)
+{
+	struct dvobj_priv *dvobj = wiphy_to_dvobj(wiphy);
+	struct rtw_wiphy_data *wiphy_data = rtw_wiphy_priv(wiphy);
+	u8 rtnl_lock_needed;
+
+	if (!wiphy_data->pd_wdev)
+		goto exit;
+
+	RTW_INFO(FUNC_WIPHY_FMT" pd_wdev:%p, addr="MAC_FMT"\n"
+		, FUNC_WIPHY_ARG(wiphy), wiphy_data->pd_wdev
+		, MAC_ARG(wdev_address(wiphy_data->pd_wdev)));
+
+	rtnl_lock_needed = rtw_rtnl_lock_needed(dvobj);
+	if (rtnl_lock_needed)
+		rtnl_lock();
+	cfg80211_unregister_wdev(wiphy_data->pd_wdev);
+	if (rtnl_lock_needed)
+		rtnl_unlock();
+
+	rtw_mfree((u8 *)wiphy_data->pd_wdev, sizeof(struct wireless_dev));
+	wiphy_data->pd_wdev = NULL;
+
+exit:
+	return;
+}
+
+static int cfg80211_rtw_start_p2p_device(struct wiphy *wiphy, struct wireless_dev *wdev)
+{
+	_adapter *adapter = wiphy_to_adapter(wiphy);
+
+	RTW_INFO(FUNC_WIPHY_FMT" wdev=%p\n", FUNC_WIPHY_ARG(wiphy), wdev);
+
+	rtw_p2p_enable(adapter, P2P_ROLE_DEVICE);
+	return 0;
+}
+
+static void cfg80211_rtw_stop_p2p_device(struct wiphy *wiphy, struct wireless_dev *wdev)
+{
+	_adapter *adapter = wiphy_to_adapter(wiphy);
+
+	RTW_INFO(FUNC_WIPHY_FMT" wdev=%p\n", FUNC_WIPHY_ARG(wiphy), wdev);
+
+	if (rtw_cfg80211_is_p2p_scan(adapter))
+		rtw_scan_abort(adapter);
+
+	rtw_p2p_enable(adapter, P2P_ROLE_DISABLE);
+}
+
+inline int rtw_cfg80211_redirect_pd_wdev(struct wiphy *wiphy, u8 *ra, struct wireless_dev **wdev)
+{
+	struct wireless_dev *pd_wdev = wiphy_to_pd_wdev(wiphy);
+
+	if (pd_wdev && pd_wdev != *wdev
+		&& _rtw_memcmp(wdev_address(pd_wdev), ra, ETH_ALEN) == _TRUE
+	) {
+		*wdev = pd_wdev;
+		return 1;
+	}
+	return 0;
+}
+
+inline int rtw_cfg80211_is_scan_by_pd_wdev(_adapter *adapter)
+{
+	struct wiphy *wiphy = adapter_to_wiphy(adapter);
+	struct rtw_wdev_priv *wdev_data = adapter_wdev_data(adapter);
+	struct wireless_dev *wdev = NULL;
+	_irqL irqL;
+
+	_enter_critical_bh(&wdev_data->scan_req_lock, &irqL);
+	if (wdev_data->scan_request)
+		wdev = wdev_data->scan_request->wdev;
+	_exit_critical_bh(&wdev_data->scan_req_lock, &irqL);
+
+	if (wdev && wdev == wiphy_to_pd_wdev(wiphy))
+		return 1;
+
+	return 0;
+}
+#endif /* RTW_DEDICATED_P2P_DEVICE */
+#endif /* CONFIG_P2P */
+
+inline void rtw_cfg80211_set_is_mgmt_tx(_adapter *adapter, u8 val)
+{
+	struct rtw_wdev_priv *wdev_priv = adapter_wdev_data(adapter);
+
+	wdev_priv->is_mgmt_tx = val;
+	rtw_mi_update_iface_status(&(adapter->mlmepriv), 0);
+}
+
+inline u8 rtw_cfg80211_get_is_mgmt_tx(_adapter *adapter)
+{
+	struct rtw_wdev_priv *wdev_priv = adapter_wdev_data(adapter);
+
+	return wdev_priv->is_mgmt_tx;
+}
+
+static int _cfg80211_rtw_mgmt_tx(_adapter *padapter, u8 tx_ch, u8 no_cck, const u8 *buf, size_t len, int wait_ack)
+{
+	struct xmit_frame	*pmgntframe;
+	struct pkt_attrib	*pattrib;
+	unsigned char	*pframe;
+	int ret = _FAIL;
+	bool ack = _TRUE;
+	struct rtw_ieee80211_hdr *pwlanhdr;
+#if defined(RTW_ROCH_BACK_OP) && defined(CONFIG_P2P) && defined(CONFIG_CONCURRENT_MODE)
+	struct rtw_wdev_priv *pwdev_priv = adapter_wdev_data(padapter);
+#endif
+	struct xmit_priv	*pxmitpriv = &(padapter->xmitpriv);
+	struct mlme_ext_priv	*pmlmeext = &(padapter->mlmeextpriv);
+	u8 u_ch = rtw_mi_get_union_chan(padapter);
+	u8 leave_op = 0;
+#ifdef CONFIG_P2P
+	struct cfg80211_wifidirect_info *pcfg80211_wdinfo = &padapter->cfg80211_wdinfo;
+	#ifdef CONFIG_CONCURRENT_MODE
+	struct wifidirect_info *pwdinfo = &padapter->wdinfo;
+	#endif
+#endif
+
+	rtw_cfg80211_set_is_mgmt_tx(padapter, 1);
+
+#ifdef CONFIG_BT_COEXIST
+	rtw_btcoex_ScanNotify(padapter, _TRUE);
+#endif
+
+#ifdef CONFIG_P2P
+	if (rtw_cfg80211_get_is_roch(padapter) == _TRUE) {
+		#ifdef CONFIG_CONCURRENT_MODE
+		if (!check_fwstate(&padapter->mlmepriv, _FW_LINKED)) {
+			RTW_INFO("%s, extend ro ch time\n", __func__);
+			_set_timer(&padapter->cfg80211_wdinfo.remain_on_ch_timer, pwdinfo->ext_listen_period);
+		}
+		#endif /* CONFIG_CONCURRENT_MODE */
+	}
+#endif /* CONFIG_P2P */
+
+#ifdef CONFIG_MCC_MODE
+	if (MCC_EN(padapter)) {
+		if (rtw_hal_check_mcc_status(padapter, MCC_STATUS_DOING_MCC))
+			/* don't set channel, issue frame directly */
+			goto issue_mgmt_frame;
+	}
+#endif /* CONFIG_MCC_MODE */
+
+	if (rtw_mi_check_status(padapter, MI_LINKED)
+		&& tx_ch != u_ch
+	) {
+		rtw_leave_opch(padapter);
+		leave_op = 1;
+
+		#if defined(RTW_ROCH_BACK_OP) && defined(CONFIG_P2P) && defined(CONFIG_CONCURRENT_MODE)
+		if (rtw_cfg80211_get_is_roch(padapter)
+			&& ATOMIC_READ(&pwdev_priv->switch_ch_to) == 1
+		) {
+			u16 ext_listen_period;
+
+			if (check_fwstate(&padapter->mlmepriv, _FW_LINKED))
+				ext_listen_period = 500;
+			else
+				ext_listen_period = pwdinfo->ext_listen_period;
+			ATOMIC_SET(&pwdev_priv->switch_ch_to, 0);
+			_set_timer(&pwdinfo->ap_p2p_switch_timer, ext_listen_period);
+			RTW_INFO("%s, set switch ch timer, period=%d\n", __func__, ext_listen_period);
+		}
+		#endif /* RTW_ROCH_BACK_OP && CONFIG_P2P && CONFIG_CONCURRENT_MODE */
+	}
+
+	if (tx_ch != rtw_get_oper_ch(padapter))
+		set_channel_bwmode(padapter, tx_ch, HAL_PRIME_CHNL_OFFSET_DONT_CARE, CHANNEL_WIDTH_20);
+
+issue_mgmt_frame:
+	/* starting alloc mgmt frame to dump it */
+	pmgntframe = alloc_mgtxmitframe(pxmitpriv);
+	if (pmgntframe == NULL) {
+		/* ret = -ENOMEM; */
+		ret = _FAIL;
+		goto exit;
+	}
+
+	/* update attribute */
+	pattrib = &pmgntframe->attrib;
+	update_mgntframe_attrib(padapter, pattrib);
+
+	if (no_cck && IS_CCK_RATE(pattrib->rate)) {
+		/* force OFDM 6M rate*/
+		pattrib->rate = MGN_6M;
+		pattrib->raid = rtw_get_mgntframe_raid(padapter, WIRELESS_11G);
+	}
+
+	pattrib->retry_ctrl = _FALSE;
+
+	_rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET);
+
+	pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET;
+
+	_rtw_memcpy(pframe, (void *)buf, len);
+	pattrib->pktlen = len;
+
+	pwlanhdr = (struct rtw_ieee80211_hdr *)pframe;
+	/* update seq number */
+	pmlmeext->mgnt_seq = GetSequence(pwlanhdr);
+	pattrib->seqnum = pmlmeext->mgnt_seq;
+	pmlmeext->mgnt_seq++;
+
+#ifdef CONFIG_P2P
+	rtw_xframe_chk_wfd_ie(pmgntframe);
+#endif /* CONFIG_P2P */
+
+	pattrib->last_txcmdsz = pattrib->pktlen;
+
+	if (wait_ack) {
+		if (dump_mgntframe_and_wait_ack(padapter, pmgntframe) != _SUCCESS) {
+			ack = _FALSE;
+			ret = _FAIL;
+
+#ifdef CONFIG_DEBUG_CFG80211
+			RTW_INFO("%s, ack == _FAIL\n", __func__);
+#endif
+		} else {
+
+#ifdef CONFIG_XMIT_ACK
+			if (!MLME_IS_MESH(padapter)) /* TODO: remove this sleep for all mode */
+				rtw_msleep_os(50);
+#endif
+#ifdef CONFIG_DEBUG_CFG80211
+			RTW_INFO("%s, ack=%d, ok!\n", __func__, ack);
+#endif
+			ret = _SUCCESS;
+		}
+	} else {
+		dump_mgntframe(padapter, pmgntframe);
+		ret = _SUCCESS;
+	}
+
+exit:
+	#ifdef CONFIG_P2P
+	if (rtw_cfg80211_get_is_roch(padapter)
+		&& !roch_stay_in_cur_chan(padapter)
+		&& pcfg80211_wdinfo->remain_on_ch_channel.hw_value != u_ch
+	) {
+		/* roch is ongoing, switch back to rch */
+		if (pcfg80211_wdinfo->remain_on_ch_channel.hw_value != tx_ch)
+			set_channel_bwmode(padapter, pcfg80211_wdinfo->remain_on_ch_channel.hw_value
+				, HAL_PRIME_CHNL_OFFSET_DONT_CARE, CHANNEL_WIDTH_20);
+	} else
+	#endif
+	if (leave_op) {
+		if (rtw_mi_check_status(padapter, MI_LINKED)) {
+			u8 u_bw = rtw_mi_get_union_bw(padapter);
+			u8 u_offset = rtw_mi_get_union_offset(padapter);
+
+			set_channel_bwmode(padapter, u_ch, u_offset, u_bw);
+		}
+		rtw_back_opch(padapter);
+	}
+
+	rtw_cfg80211_set_is_mgmt_tx(padapter, 0);
+
+#ifdef CONFIG_BT_COEXIST
+	rtw_btcoex_ScanNotify(padapter, _FALSE);
+#endif
+
+#ifdef CONFIG_DEBUG_CFG80211
+	RTW_INFO("%s, ret=%d\n", __func__, ret);
+#endif
+
+	return ret;
+
+}
+
+u8 rtw_mgnt_tx_handler(_adapter *adapter, u8 *buf)
+{
+	u8 rst = H2C_CMD_FAIL;
+	struct mgnt_tx_parm *mgnt_parm = (struct mgnt_tx_parm *)buf;
+
+	if (_cfg80211_rtw_mgmt_tx(adapter, mgnt_parm->tx_ch, mgnt_parm->no_cck,
+		mgnt_parm->buf, mgnt_parm->len, mgnt_parm->wait_ack) == _SUCCESS)
+		rst = H2C_SUCCESS;
+
+	return rst;
+}
+
+static int cfg80211_rtw_mgmt_tx(struct wiphy *wiphy,
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 6, 0))
+	struct wireless_dev *wdev,
+#else
+	struct net_device *ndev,
+#endif
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 14, 0)) || defined(COMPAT_KERNEL_RELEASE)
+	struct ieee80211_channel *chan,
+	#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 38)) || defined(COMPAT_KERNEL_RELEASE)
+	bool offchan,
+	#endif
+	#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 34)) && (LINUX_VERSION_CODE < KERNEL_VERSION(3, 8, 0))
+	enum nl80211_channel_type channel_type,
+	#endif
+	#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 36)) && (LINUX_VERSION_CODE < KERNEL_VERSION(3, 8, 0))
+	bool channel_type_valid,
+	#endif
+	#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 38)) || defined(COMPAT_KERNEL_RELEASE)
+	unsigned int wait,
+	#endif
+	const u8 *buf, size_t len,
+	#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 2, 0))
+	bool no_cck,
+	#endif
+	#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 3, 0))
+	bool dont_wait_for_ack,
+	#endif
+#else
+	struct cfg80211_mgmt_tx_params *params,
+#endif
+	u64 *cookie)
+{
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 14, 0)) || defined(COMPAT_KERNEL_RELEASE)
+	struct ieee80211_channel *chan = params->chan;
+	const u8 *buf = params->buf;
+	size_t len = params->len;
+	bool no_cck = params->no_cck;
+#endif
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 2, 0))
+	bool no_cck = 0;
+#endif
+	int ret = 0;
+	u8 tx_ret;
+	int wait_ack = 1;
+	const u8 *dump_buf = buf;
+	size_t dump_len = len;
+	u32 dump_limit = RTW_MAX_MGMT_TX_CNT;
+	u32 dump_cnt = 0;
+	u32 sleep_ms = 0;
+	u32 retry_guarantee_ms = 0;
+	bool ack = _TRUE;
+	u8 tx_ch;
+	u8 category, action;
+	u8 frame_styp;
+#ifdef CONFIG_P2P
+	u8 is_p2p = 0;
+#endif
+	int type = (-1);
+	systime start = rtw_get_current_time();
+	_adapter *padapter;
+	struct dvobj_priv *dvobj;
+	struct rtw_wdev_priv *pwdev_priv;
+	struct rf_ctl_t *rfctl;
+
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 6, 0))
+	#if defined(RTW_DEDICATED_P2P_DEVICE)
+	if (wdev == wiphy_to_pd_wdev(wiphy))
+		padapter = wiphy_to_adapter(wiphy);
+	else
+	#endif
+	if (wdev_to_ndev(wdev))
+		padapter = (_adapter *)rtw_netdev_priv(wdev_to_ndev(wdev));
+	else {
+		ret = -EINVAL;
+		goto exit;
+	}
+#else
+	struct wireless_dev *wdev;
+
+	if (ndev == NULL) {
+		ret = -EINVAL;
+		goto exit;
+	}
+	padapter = (_adapter *)rtw_netdev_priv(ndev);
+	wdev = ndev_to_wdev(ndev);
+#endif
+
+	if (chan == NULL) {
+		ret = -EINVAL;
+		goto exit;
+	}
+
+	rfctl = adapter_to_rfctl(padapter);
+	tx_ch = (u8)ieee80211_frequency_to_channel(chan->center_freq);
+	if (IS_CH_WAITING(rfctl)) {
+		#ifdef CONFIG_DFS_MASTER
+		if (_rtw_rfctl_overlap_radar_detect_ch(rfctl, tx_ch, CHANNEL_WIDTH_20, HAL_PRIME_CHNL_OFFSET_DONT_CARE)) {
+			ret = -EINVAL;
+			goto exit;
+		}
+		#endif
+	}
+
+	dvobj = adapter_to_dvobj(padapter);
+	pwdev_priv = adapter_wdev_data(padapter);
+
+	/* cookie generation */
+	*cookie = pwdev_priv->mgmt_tx_cookie++;
+
+#ifdef CONFIG_DEBUG_CFG80211
+	RTW_INFO(FUNC_ADPT_FMT"%s len=%zu, ch=%d"
+		#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 34)) && (LINUX_VERSION_CODE < KERNEL_VERSION(3, 8, 0))
+		", ch_type=%d"
+		#endif
+		#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 36)) && (LINUX_VERSION_CODE < KERNEL_VERSION(3, 8, 0))
+		", channel_type_valid=%d"
+		#endif
+		"\n", FUNC_ADPT_ARG(padapter), wdev == wiphy_to_pd_wdev(wiphy) ? " PD" : ""
+		, len, tx_ch
+		#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 34)) && (LINUX_VERSION_CODE < KERNEL_VERSION(3, 8, 0))
+		, channel_type
+		#endif
+		#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 34)) && (LINUX_VERSION_CODE < KERNEL_VERSION(3, 8, 0))
+		, channel_type_valid
+		#endif
+	);
+#endif /* CONFIG_DEBUG_CFG80211 */
+
+	/* indicate ack before issue frame to avoid racing with rsp frame */
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) || defined(COMPAT_KERNEL_RELEASE)
+	rtw_cfg80211_mgmt_tx_status(wdev, *cookie, buf, len, ack, GFP_KERNEL);
+#elif (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 34) && LINUX_VERSION_CODE <= KERNEL_VERSION(2, 6, 36))
+	cfg80211_action_tx_status(ndev, *cookie, buf, len, ack, GFP_KERNEL);
+#endif
+
+	frame_styp = le16_to_cpu(((struct rtw_ieee80211_hdr_3addr *)buf)->frame_ctl) & IEEE80211_FCTL_STYPE;
+	if (IEEE80211_STYPE_PROBE_RESP == frame_styp) {
+#ifdef CONFIG_DEBUG_CFG80211
+		RTW_INFO("RTW_Tx: probe_resp tx_ch=%d, no_cck=%u, da="MAC_FMT"\n", tx_ch, no_cck, MAC_ARG(GetAddr1Ptr(buf)));
+#endif /* CONFIG_DEBUG_CFG80211 */
+		wait_ack = 0;
+		goto dump;
+	}
+#ifdef CONFIG_RTW_MESH
+	else if (frame_styp == RTW_IEEE80211_STYPE_AUTH) {
+		RTW_INFO("RTW_Tx:tx_ch=%d, no_cck=%u, da="MAC_FMT"\n", tx_ch, no_cck, MAC_ARG(GetAddr1Ptr(buf)));
+		if (!rtw_sae_check_frames(padapter, buf, len, _TRUE))
+			RTW_INFO("RTW_Tx:AUTH\n");
+		dump_limit = 1;
+		goto dump;
+	}
+#endif
+
+	if (rtw_action_frame_parse(buf, len, &category, &action) == _FALSE) {
+		RTW_INFO(FUNC_ADPT_FMT" frame_control:0x%02x\n", FUNC_ADPT_ARG(padapter),
+			le16_to_cpu(((struct rtw_ieee80211_hdr_3addr *)buf)->frame_ctl));
+		goto exit;
+	}
+
+	RTW_INFO("RTW_Tx:tx_ch=%d, no_cck=%u, da="MAC_FMT"\n", tx_ch, no_cck, MAC_ARG(GetAddr1Ptr(buf)));
+#ifdef CONFIG_P2P
+	type = rtw_p2p_check_frames(padapter, buf, len, _TRUE);
+	if (type >= 0) {
+		is_p2p = 1;
+		no_cck = 1; /* force no CCK for P2P frames */
+		goto dump;
+	}
+#endif
+#ifdef CONFIG_RTW_MESH
+	if (MLME_IS_MESH(padapter)) {
+		type = rtw_mesh_check_frames_tx(padapter, &dump_buf, &dump_len);
+		if (type >= 0) {
+			dump_limit = 1;
+			goto dump;
+		}
+	}
+#endif
+	if (category == RTW_WLAN_CATEGORY_PUBLIC) {
+		RTW_INFO("RTW_Tx:%s\n", action_public_str(action));
+		switch (action) {
+		case ACT_PUBLIC_GAS_INITIAL_REQ:
+		case ACT_PUBLIC_GAS_INITIAL_RSP:
+			sleep_ms = 50;
+			retry_guarantee_ms = RTW_MAX_MGMT_TX_MS_GAS;
+			break;
+		}
+	}
+#ifdef CONFIG_RTW_80211K
+	else if (category == RTW_WLAN_CATEGORY_RADIO_MEAS)
+		RTW_INFO("RTW_Tx: RRM Action\n");
+#endif
+	else
+		RTW_INFO("RTW_Tx:category(%u), action(%u)\n", category, action);
+
+dump:
+
+	rtw_ps_deny(padapter, PS_DENY_MGNT_TX);
+	if (_FAIL == rtw_pwr_wakeup(padapter)) {
+		ret = -EFAULT;
+		goto cancel_ps_deny;
+	}
+
+	while (1) {
+		dump_cnt++;
+
+		rtw_mi_set_scan_deny(padapter, 1000);
+		rtw_mi_scan_abort(padapter, _TRUE);
+		tx_ret = rtw_mgnt_tx_cmd(padapter, tx_ch, no_cck, dump_buf, dump_len, wait_ack, RTW_CMDF_WAIT_ACK);
+		if (tx_ret == _SUCCESS
+			|| (dump_cnt >= dump_limit && rtw_get_passing_time_ms(start) >= retry_guarantee_ms))
+			break;
+
+		if (sleep_ms > 0)
+			rtw_msleep_os(sleep_ms);
+	}
+
+	if (tx_ret != _SUCCESS || dump_cnt > 1) {
+		RTW_INFO(FUNC_ADPT_FMT" %s (%d/%d) in %d ms\n", FUNC_ADPT_ARG(padapter),
+			tx_ret == _SUCCESS ? "OK" : "FAIL", dump_cnt, dump_limit, rtw_get_passing_time_ms(start));
+	}
+
+#ifdef CONFIG_P2P
+	if (is_p2p) {
+		switch (type) {
+		case P2P_GO_NEGO_CONF:
+			if (0) {
+				RTW_INFO(FUNC_ADPT_FMT" Nego confirm. state=%u, status=%u, iaddr="MAC_FMT"\n"
+					, FUNC_ADPT_ARG(padapter), pwdev_priv->nego_info.state, pwdev_priv->nego_info.status
+					, MAC_ARG(pwdev_priv->nego_info.iface_addr));
+			}
+			if (pwdev_priv->nego_info.state == 2
+				&& pwdev_priv->nego_info.status == 0
+				&& rtw_check_invalid_mac_address(pwdev_priv->nego_info.iface_addr, _FALSE) == _FALSE
+			) {
+				_adapter *intended_iface = dvobj_get_adapter_by_addr(dvobj, pwdev_priv->nego_info.iface_addr);
+
+				if (intended_iface) {
+					RTW_INFO(FUNC_ADPT_FMT" Nego confirm. Allow only "ADPT_FMT" to scan for 2000 ms\n"
+						, FUNC_ADPT_ARG(padapter), ADPT_ARG(intended_iface));
+					/* allow only intended_iface to do scan for 2000 ms */
+					rtw_mi_set_scan_deny(padapter, 2000);
+					rtw_clear_scan_deny(intended_iface);
+				}
+			}
+			break;
+		case P2P_INVIT_RESP:
+			if (pwdev_priv->invit_info.flags & BIT(0)
+				&& pwdev_priv->invit_info.status == 0
+			) {
+				rtw_clear_scan_deny(padapter);
+				RTW_INFO(FUNC_ADPT_FMT" agree with invitation of persistent group\n",
+					FUNC_ADPT_ARG(padapter));
+				#if !RTW_P2P_GROUP_INTERFACE
+				rtw_mi_buddy_set_scan_deny(padapter, 5000);
+				#endif
+				rtw_pwr_wakeup_ex(padapter, 5000);
+			}
+			break;
+		}
+	}
+#endif /* CONFIG_P2P */
+
+cancel_ps_deny:
+	rtw_ps_deny_cancel(padapter, PS_DENY_MGNT_TX);
+
+	if (dump_buf != buf)
+		rtw_mfree((u8 *)dump_buf, dump_len);
+exit:
+	return ret;
+}
+
+static void cfg80211_rtw_mgmt_frame_register(struct wiphy *wiphy,
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 6, 0))
+	struct wireless_dev *wdev,
+#else
+	struct net_device *ndev,
+#endif
+	u16 frame_type, bool reg)
+{
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 6, 0))
+	struct net_device *ndev = wdev_to_ndev(wdev);
+#endif
+	_adapter *adapter;
+
+	struct rtw_wdev_priv *pwdev_priv;
+
+	if (ndev == NULL)
+		goto exit;
+
+	adapter = (_adapter *)rtw_netdev_priv(ndev);
+	pwdev_priv = adapter_wdev_data(adapter);
+
+#ifdef CONFIG_DEBUG_CFG80211
+	RTW_INFO(FUNC_ADPT_FMT" frame_type:%x, reg:%d\n", FUNC_ADPT_ARG(adapter),
+		frame_type, reg);
+#endif
+
+	/* Wait QC Verify */
+	return;
+
+	switch (frame_type) {
+	case IEEE80211_STYPE_PROBE_REQ: /* 0x0040 */
+		SET_CFG80211_REPORT_MGMT(pwdev_priv, IEEE80211_STYPE_PROBE_REQ, reg);
+		break;
+	case IEEE80211_STYPE_ACTION: /* 0x00D0 */
+		SET_CFG80211_REPORT_MGMT(pwdev_priv, IEEE80211_STYPE_ACTION, reg);
+		break;
+	default:
+		break;
+	}
+
+exit:
+	return;
+}
+
+#if defined(CONFIG_TDLS) && (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 2, 0))
+static int cfg80211_rtw_tdls_mgmt(struct wiphy *wiphy,
+	struct net_device *ndev,
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 16, 0))
+	const u8 *peer,
+#else
+	u8 *peer,
+#endif
+	u8 action_code,
+	u8 dialog_token,
+	u16 status_code,
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 15, 0))
+	u32 peer_capability,
+#endif
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 17, 0))
+	bool initiator,
+#endif
+	const u8 *buf,
+	size_t len)
+{
+	_adapter *padapter = (_adapter *)rtw_netdev_priv(ndev);
+	struct mlme_ext_priv	*pmlmeext = &padapter->mlmeextpriv;
+	struct mlme_ext_info	*pmlmeinfo = &pmlmeext->mlmext_info;
+	int ret = 0;
+	struct tdls_txmgmt txmgmt;
+
+	if (hal_chk_wl_func(padapter, WL_FUNC_TDLS) == _FALSE) {
+		RTW_INFO("Discard tdls action:%d, since hal doesn't support tdls\n", action_code);
+		goto discard;
+	}
+
+	if (rtw_is_tdls_enabled(padapter) == _FALSE) {
+		RTW_INFO("TDLS is not enabled\n");
+		goto discard;
+	}
+
+	if (rtw_tdls_is_driver_setup(padapter)) {
+		RTW_INFO("Discard tdls action:%d, let driver to set up direct link\n", action_code);
+		goto discard;
+	}
+
+	_rtw_memset(&txmgmt, 0x00, sizeof(struct tdls_txmgmt));
+	_rtw_memcpy(txmgmt.peer, peer, ETH_ALEN);
+	txmgmt.action_code = action_code;
+	txmgmt.dialog_token = dialog_token;
+	txmgmt.status_code = status_code;
+	txmgmt.len = len;
+	txmgmt.buf = (u8 *)rtw_malloc(txmgmt.len);
+	if (txmgmt.buf == NULL) {
+		ret = -ENOMEM;
+		goto bad;
+	}
+	_rtw_memcpy(txmgmt.buf, (void *)buf, txmgmt.len);
+
+	/* Debug purpose */
+#if 1
+	RTW_INFO("%s %d\n", __FUNCTION__, __LINE__);
+	RTW_INFO("peer:"MAC_FMT", action code:%d, dialog:%d, status code:%d\n",
+		MAC_ARG(txmgmt.peer), txmgmt.action_code,
+		txmgmt.dialog_token, txmgmt.status_code);
+	if (txmgmt.len > 0) {
+		int i = 0;
+		for (; i < len; i++)
+			printk("%02x ", *(txmgmt.buf + i));
+		RTW_INFO("len:%d\n", (u32)txmgmt.len);
+	}
+#endif
+
+	switch (txmgmt.action_code) {
+	case TDLS_SETUP_REQUEST:
+		issue_tdls_setup_req(padapter, &txmgmt, _TRUE);
+		break;
+	case TDLS_SETUP_RESPONSE:
+		issue_tdls_setup_rsp(padapter, &txmgmt);
+		break;
+	case TDLS_SETUP_CONFIRM:
+		issue_tdls_setup_cfm(padapter, &txmgmt);
+		break;
+	case TDLS_TEARDOWN:
+		issue_tdls_teardown(padapter, &txmgmt, _TRUE);
+		break;
+	case TDLS_DISCOVERY_REQUEST:
+		issue_tdls_dis_req(padapter, &txmgmt);
+		break;
+	case TDLS_DISCOVERY_RESPONSE:
+		issue_tdls_dis_rsp(padapter, &txmgmt, pmlmeinfo->enc_algo ? _TRUE : _FALSE);
+		break;
+	}
+
+bad:
+	if (txmgmt.buf)
+		rtw_mfree(txmgmt.buf, txmgmt.len);
+
+discard:
+	return ret;
+}
+
+static int cfg80211_rtw_tdls_oper(struct wiphy *wiphy,
+	struct net_device *ndev,
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 16, 0))
+	const u8 *peer,
+#else
+	u8 *peer,
+#endif
+	enum nl80211_tdls_operation oper)
+{
+	_adapter *padapter = (_adapter *)rtw_netdev_priv(ndev);
+	struct tdls_info *ptdlsinfo = &padapter->tdlsinfo;
+	struct tdls_txmgmt	txmgmt;
+	struct sta_info *ptdls_sta = NULL;
+
+	RTW_INFO(FUNC_NDEV_FMT", nl80211_tdls_operation:%d\n", FUNC_NDEV_ARG(ndev), oper);
+
+	if (hal_chk_wl_func(padapter, WL_FUNC_TDLS) == _FALSE) {
+		RTW_INFO("Discard tdls oper:%d, since hal doesn't support tdls\n", oper);
+		return 0;
+	}
+
+	if (rtw_is_tdls_enabled(padapter) == _FALSE) {
+		RTW_INFO("TDLS is not enabled\n");
+		return 0;
+	}
+
+#ifdef CONFIG_LPS
+	rtw_lps_ctrl_wk_cmd(padapter, LPS_CTRL_LEAVE, 1);
+#endif /* CONFIG_LPS */
+
+	_rtw_memset(&txmgmt, 0x00, sizeof(struct tdls_txmgmt));
+	if (peer)
+		_rtw_memcpy(txmgmt.peer, peer, ETH_ALEN);
+
+	if (rtw_tdls_is_driver_setup(padapter)) {
+		/* these two cases are done by driver itself */
+		if (oper == NL80211_TDLS_ENABLE_LINK || oper == NL80211_TDLS_DISABLE_LINK)
+			return 0;
+	}
+
+	switch (oper) {
+	case NL80211_TDLS_DISCOVERY_REQ:
+		issue_tdls_dis_req(padapter, &txmgmt);
+		break;
+	case NL80211_TDLS_SETUP:
+#ifdef CONFIG_WFD
+		if (_AES_ != padapter->securitypriv.dot11PrivacyAlgrthm) {
+			if (padapter->wdinfo.wfd_tdls_weaksec == _TRUE)
+				issue_tdls_setup_req(padapter, &txmgmt, _TRUE);
+			else
+				RTW_INFO("[%s] Current link is not AES, SKIP sending the tdls setup request!!\n", __FUNCTION__);
+		} else
+#endif /* CONFIG_WFD */
+		{
+			issue_tdls_setup_req(padapter, &txmgmt, _TRUE);
+		}
+		break;
+	case NL80211_TDLS_TEARDOWN:
+		ptdls_sta = rtw_get_stainfo(&(padapter->stapriv), txmgmt.peer);
+		if (ptdls_sta != NULL) {
+			txmgmt.status_code = _RSON_TDLS_TEAR_UN_RSN_;
+			issue_tdls_teardown(padapter, &txmgmt, _TRUE);
+		} else
+			RTW_INFO("TDLS peer not found\n");
+		break;
+	case NL80211_TDLS_ENABLE_LINK:
+		RTW_INFO(FUNC_NDEV_FMT", NL80211_TDLS_ENABLE_LINK;mac:"MAC_FMT"\n", FUNC_NDEV_ARG(ndev), MAC_ARG(peer));
+		ptdls_sta = rtw_get_stainfo(&(padapter->stapriv), (u8 *)peer);
+		if (ptdls_sta != NULL) {
+			rtw_tdls_set_link_established(padapter, _TRUE);
+			ptdls_sta->tdls_sta_state |= TDLS_LINKED_STATE;
+			ptdls_sta->state |= _FW_LINKED;
+			rtw_tdls_cmd(padapter, txmgmt.peer, TDLS_ESTABLISHED);
+		}
+		break;
+	case NL80211_TDLS_DISABLE_LINK:
+		RTW_INFO(FUNC_NDEV_FMT", NL80211_TDLS_DISABLE_LINK;mac:"MAC_FMT"\n", FUNC_NDEV_ARG(ndev), MAC_ARG(peer));
+		ptdls_sta = rtw_get_stainfo(&(padapter->stapriv), (u8 *)peer);
+		if (ptdls_sta != NULL) {
+			rtw_tdls_teardown_pre_hdl(padapter, ptdls_sta);
+			rtw_tdls_cmd(padapter, (u8 *)peer, TDLS_TEARDOWN_STA_LOCALLY_POST);
+		}
+		break;
+	}
+	return 0;
+}
+#endif /* CONFIG_TDLS */
+
+#if defined(CONFIG_RTW_MESH) && (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 38))
+
+#if DBG_RTW_CFG80211_MESH_CONF
+#define LEGACY_RATES_STR_LEN (RTW_G_RATES_NUM * 5 + 1)
+int get_legacy_rates_str(struct wiphy *wiphy, enum nl80211_band band, u32 mask, char *buf)
+{
+	int i;
+	int cnt = 0;
+
+	for (i = 0; i < wiphy->bands[band]->n_bitrates; i++) {
+		if (mask & BIT(i)) {
+			cnt += snprintf(buf + cnt, LEGACY_RATES_STR_LEN - cnt -1, "%d.%d "
+				, wiphy->bands[band]->bitrates[i].bitrate / 10
+				, wiphy->bands[band]->bitrates[i].bitrate % 10);
+			if (cnt >= LEGACY_RATES_STR_LEN - 1)
+				break;
+		}
+	}
+
+	return cnt;
+}
+
+void dump_mesh_setup(void *sel, struct wiphy *wiphy, const struct mesh_setup *setup)
+{
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 6, 0))
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 8, 0))
+	struct cfg80211_chan_def *chdef = (struct cfg80211_chan_def *)(&setup->chandef);
+#endif
+	struct ieee80211_channel *chan;
+#endif
+
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 8, 0))
+	chan = (struct ieee80211_channel *)chdef->chan;
+#elif (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 6, 0))
+	chan = (struct ieee80211_channel *)setup->channel;
+#endif
+
+	RTW_PRINT_SEL(sel, "mesh_id:\"%s\", len:%u\n", setup->mesh_id, setup->mesh_id_len);
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 5, 0))
+	RTW_PRINT_SEL(sel, "sync_method:%u\n", setup->sync_method);
+#endif
+	RTW_PRINT_SEL(sel, "path_sel_proto:%u, path_metric:%u\n", setup->path_sel_proto, setup->path_metric);
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 11, 0))
+	RTW_PRINT_SEL(sel, "auth_id:%u\n", setup->auth_id);
+#endif
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 0, 0))
+	if (setup->ie && setup->ie_len) {
+		RTW_PRINT_SEL(sel, "ie:%p, len:%u\n", setup->ie, setup->ie_len);
+		dump_ies(RTW_DBGDUMP, setup->ie, setup->ie_len);
+	}
+#else
+	if (setup->vendor_ie && setup->vendor_ie_len) {
+		RTW_PRINT_SEL(sel, "ie:%p, len:%u\n", setup->vendor_ie, setup->vendor_ie_len);
+		dump_ies(RTW_DBGDUMP, setup->vendor_ie, setup->vendor_ie_len);
+	}
+#endif
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 0, 0))
+	RTW_PRINT_SEL(sel, "is_authenticated:%d, is_secure:%d\n", setup->is_authenticated, setup->is_secure);
+#endif
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 10, 0))
+	RTW_PRINT_SEL(sel, "user_mpm:%d\n", setup->user_mpm);
+#endif
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 9, 0))
+	RTW_PRINT_SEL(sel, "dtim_period:%u, beacon_interval:%u\n", setup->dtim_period, setup->beacon_interval);
+#endif
+
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 6, 0))
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 8, 0))
+	RTW_PRINT_SEL(sel, "center_freq:%u, ch:%u, width:%s, cfreq1:%u, cfreq2:%u\n"
+		, chan->center_freq, chan->hw_value, nl80211_chan_width_str(chdef->width), chdef->center_freq1, chdef->center_freq2);
+#else
+	RTW_PRINT_SEL(sel, "center_freq:%u, ch:%u, channel_type:%s\n"
+		, chan->center_freq, chan->hw_value, nl80211_channel_type_str(setup->channel_type));
+#endif
+#endif
+
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 3, 0))
+	if (setup->mcast_rate[chan->band]) {
+		RTW_PRINT_SEL(sel, "mcast_rate:%d.%d\n"
+			, wiphy->bands[chan->band]->bitrates[setup->mcast_rate[chan->band] - 1].bitrate / 10
+			, wiphy->bands[chan->band]->bitrates[setup->mcast_rate[chan->band] - 1].bitrate % 10
+		);
+	}
+#endif
+
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 11, 0))
+	if (setup->basic_rates) {
+		char buf[LEGACY_RATES_STR_LEN] = {0};
+
+		get_legacy_rates_str(wiphy, chan->band, setup->basic_rates, buf);
+		RTW_PRINT_SEL(sel, "basic_rates:%s\n", buf);
+	}
+#endif
+
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 9, 0))
+	if (setup->beacon_rate.control[chan->band].legacy) {
+		char buf[LEGACY_RATES_STR_LEN] = {0};
+
+		get_legacy_rates_str(wiphy, chan->band, setup->beacon_rate.control[chan->band].legacy, buf);
+		RTW_PRINT_SEL(sel, "beacon_rate.legacy:%s\n", buf);
+	}
+	if (*((u32 *)&(setup->beacon_rate.control[chan->band].ht_mcs[0]))
+		|| *((u32 *)&(setup->beacon_rate.control[chan->band].ht_mcs[4]))
+		|| *((u16 *)&(setup->beacon_rate.control[chan->band].ht_mcs[8]))
+	) {
+		RTW_PRINT_SEL(sel, "beacon_rate.ht_mcs:"HT_RX_MCS_BMP_FMT"\n"
+			, HT_RX_MCS_BMP_ARG(setup->beacon_rate.control[chan->band].ht_mcs));
+	}
+
+	if (setup->beacon_rate.control[chan->band].vht_mcs[0]
+		|| setup->beacon_rate.control[chan->band].vht_mcs[1]
+		|| setup->beacon_rate.control[chan->band].vht_mcs[2]
+		|| setup->beacon_rate.control[chan->band].vht_mcs[3]
+	) {
+		int i;
+
+		for (i = 0; i < 4; i++) {/* parsing up to 4SS */
+			u16 mcs_mask = setup->beacon_rate.control[chan->band].vht_mcs[i];
+
+			RTW_PRINT_SEL(sel, "beacon_rate.vht_mcs[%d]:%s\n", i
+				, mcs_mask == 0x00FF ? "0~7" : mcs_mask == 0x01FF ? "0~8" : mcs_mask == 0x03FF ? "0~9" : "invalid");
+		}
+	}
+
+	if (setup->beacon_rate.control[chan->band].gi) {
+		RTW_PRINT_SEL(sel, "beacon_rate.gi:%s\n"
+			, setup->beacon_rate.control[chan->band].gi == NL80211_TXRATE_FORCE_SGI ? "SGI" :
+				setup->beacon_rate.control[chan->band].gi == NL80211_TXRATE_FORCE_LGI ? "LGI" : "invalid"
+		);
+	}
+#endif
+}
+
+void dump_mesh_config(void *sel, const struct mesh_config *conf)
+{
+	RTW_PRINT_SEL(sel, "dot11MeshRetryTimeout:%u\n", conf->dot11MeshRetryTimeout);
+	RTW_PRINT_SEL(sel, "dot11MeshConfirmTimeout:%u\n", conf->dot11MeshConfirmTimeout);
+	RTW_PRINT_SEL(sel, "dot11MeshHoldingTimeout:%u\n", conf->dot11MeshHoldingTimeout);
+	RTW_PRINT_SEL(sel, "dot11MeshMaxPeerLinks:%u\n", conf->dot11MeshMaxPeerLinks);
+	RTW_PRINT_SEL(sel, "dot11MeshMaxRetries:%u\n", conf->dot11MeshMaxRetries);
+	RTW_PRINT_SEL(sel, "dot11MeshTTL:%u\n", conf->dot11MeshTTL);
+	RTW_PRINT_SEL(sel, "element_ttl:%u\n", conf->element_ttl);
+	RTW_PRINT_SEL(sel, "auto_open_plinks:%d\n", conf->auto_open_plinks);
+
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 5, 0))
+	RTW_PRINT_SEL(sel, "dot11MeshNbrOffsetMaxNeighbor:%u\n", conf->dot11MeshNbrOffsetMaxNeighbor);
+#endif
+
+	RTW_PRINT_SEL(sel, "dot11MeshHWMPmaxPREQretries:%u\n", conf->dot11MeshHWMPmaxPREQretries);
+	RTW_PRINT_SEL(sel, "path_refresh_time:%u\n", conf->path_refresh_time);
+	RTW_PRINT_SEL(sel, "min_discovery_timeout:%u\n", conf->min_discovery_timeout);
+	RTW_PRINT_SEL(sel, "dot11MeshHWMPactivePathTimeout:%u\n", conf->dot11MeshHWMPactivePathTimeout);
+	RTW_PRINT_SEL(sel, "dot11MeshHWMPpreqMinInterval:%u\n", conf->dot11MeshHWMPpreqMinInterval);	
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 3, 0))
+	RTW_PRINT_SEL(sel, "dot11MeshHWMPperrMinInterval:%u\n", conf->dot11MeshHWMPperrMinInterval);
+#endif
+	RTW_PRINT_SEL(sel, "dot11MeshHWMPnetDiameterTraversalTime:%u\n", conf->dot11MeshHWMPnetDiameterTraversalTime);
+	RTW_PRINT_SEL(sel, "dot11MeshHWMPRootMode:%u\n", conf->dot11MeshHWMPRootMode);
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 2, 0))
+	RTW_PRINT_SEL(sel, "dot11MeshHWMPRannInterval:%u\n", conf->dot11MeshHWMPRannInterval);
+	RTW_PRINT_SEL(sel, "dot11MeshGateAnnouncementProtocol:%d\n", conf->dot11MeshGateAnnouncementProtocol);
+#endif
+
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 4, 0))
+	RTW_PRINT_SEL(sel, "dot11MeshForwarding:%d\n", conf->dot11MeshForwarding);
+	RTW_PRINT_SEL(sel, "rssi_threshold:%d\n", conf->rssi_threshold);
+#endif
+	
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 5, 0))
+	RTW_PRINT_SEL(sel, "ht_opmode:0x%04x\n", conf->ht_opmode);
+#endif
+	
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 6, 0))
+	RTW_PRINT_SEL(sel, "dot11MeshHWMPactivePathToRootTimeout:%u\n", conf->dot11MeshHWMPactivePathToRootTimeout);
+	RTW_PRINT_SEL(sel, "dot11MeshHWMProotInterval:%u\n", conf->dot11MeshHWMProotInterval);
+	RTW_PRINT_SEL(sel, "dot11MeshHWMPconfirmationInterval:%u\n", conf->dot11MeshHWMPconfirmationInterval);
+#endif
+
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 9, 0))
+	RTW_PRINT_SEL(sel, "power_mode:%s\n", nl80211_mesh_power_mode_str(conf->power_mode));
+	RTW_PRINT_SEL(sel, "dot11MeshAwakeWindowDuration:%u\n", conf->dot11MeshAwakeWindowDuration);
+#endif
+	
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 11, 0))
+	RTW_PRINT_SEL(sel, "plink_timeout:%u\n", conf->plink_timeout);
+#endif
+}
+#endif /* DBG_RTW_CFG80211_MESH_CONF */
+
+static void rtw_cfg80211_mesh_info_set_profile(struct rtw_mesh_info *minfo, const struct mesh_setup *setup)
+{
+	_rtw_memcpy(minfo->mesh_id, setup->mesh_id, setup->mesh_id_len);
+	minfo->mesh_id_len = setup->mesh_id_len;
+	minfo->mesh_pp_id = setup->path_sel_proto;
+	minfo->mesh_pm_id = setup->path_metric;
+	minfo->mesh_cc_id = 0;
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 5, 0))
+	minfo->mesh_sp_id = setup->sync_method;
+#endif
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 11, 0))
+	minfo->mesh_auth_id = setup->auth_id;
+#else
+	if (setup->is_authenticated) {
+		u8 *rsn_ie;
+		sint rsn_ie_len;
+		struct rsne_info info;
+		u8 *akm;
+		u8 AKM_SUITE_SAE[4] = {0x00, 0x0F, 0xAC, 0x08};
+
+		rsn_ie = rtw_get_ie(setup->ie, WLAN_EID_RSN, &rsn_ie_len, setup->ie_len);
+		if (!rsn_ie || !rsn_ie_len) {
+			rtw_warn_on(1);
+			return;
+		}
+
+		if (rtw_rsne_info_parse(rsn_ie, rsn_ie_len + 2, &info) != _SUCCESS) {
+			rtw_warn_on(1);
+			return;
+		}
+
+		if (!info.akm_list || !info.akm_cnt) {
+			rtw_warn_on(1);
+			return;
+		}
+
+		akm = info.akm_list;
+		while (akm < info.akm_list + info.akm_cnt * 4) {
+			if (_rtw_memcmp(akm, AKM_SUITE_SAE, 4) == _TRUE) {
+				minfo->mesh_auth_id = 0x01;
+				break;
+			}
+		}
+
+		if (!minfo->mesh_auth_id) {
+			rtw_warn_on(1);
+			return;
+		}
+	}
+#endif
+}
+
+static inline bool chk_mesh_attr(enum nl80211_meshconf_params parm, u32 mask)
+{
+	return (mask >> (parm - 1)) & 0x1;
+}
+
+static void rtw_cfg80211_mesh_cfg_set(_adapter *adapter, const struct mesh_config *conf, u32 mask)
+{
+	struct rtw_mesh_cfg *mcfg = &adapter->mesh_cfg;
+
+#if 0 /* driver MPM */
+	if (chk_mesh_attr(NL80211_MESHCONF_RETRY_TIMEOUT, mask));
+	if (chk_mesh_attr(NL80211_MESHCONF_CONFIRM_TIMEOUT, mask));
+	if (chk_mesh_attr(NL80211_MESHCONF_HOLDING_TIMEOUT, mask));
+	if (chk_mesh_attr(NL80211_MESHCONF_MAX_PEER_LINKS, mask));
+	if (chk_mesh_attr(NL80211_MESHCONF_MAX_RETRIES, mask));
+#endif
+
+	if (chk_mesh_attr(NL80211_MESHCONF_TTL, mask))
+		mcfg->dot11MeshTTL = conf->dot11MeshTTL;
+	if (chk_mesh_attr(NL80211_MESHCONF_ELEMENT_TTL, mask))
+		mcfg->element_ttl = conf->element_ttl;
+
+#if 0 /* driver MPM */
+	if (chk_mesh_attr(NL80211_MESHCONF_AUTO_OPEN_PLINKS, mask));
+#endif
+
+#if 0 /* TBD: synchronization */
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 5, 0))
+	if (chk_mesh_attr(NL80211_MESHCONF_SYNC_OFFSET_MAX_NEIGHBOR, mask));
+#endif
+#endif
+
+	if (chk_mesh_attr(NL80211_MESHCONF_HWMP_MAX_PREQ_RETRIES, mask))
+		mcfg->dot11MeshHWMPmaxPREQretries = conf->dot11MeshHWMPmaxPREQretries;
+	if (chk_mesh_attr(NL80211_MESHCONF_PATH_REFRESH_TIME, mask))
+		mcfg->path_refresh_time = conf->path_refresh_time;
+	if (chk_mesh_attr(NL80211_MESHCONF_MIN_DISCOVERY_TIMEOUT, mask))
+		mcfg->min_discovery_timeout = conf->min_discovery_timeout;
+	if (chk_mesh_attr(NL80211_MESHCONF_HWMP_ACTIVE_PATH_TIMEOUT, mask))
+		mcfg->dot11MeshHWMPactivePathTimeout = conf->dot11MeshHWMPactivePathTimeout;
+	if (chk_mesh_attr(NL80211_MESHCONF_HWMP_PREQ_MIN_INTERVAL, mask))
+		mcfg->dot11MeshHWMPpreqMinInterval = conf->dot11MeshHWMPpreqMinInterval;
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 3, 0))
+	if (chk_mesh_attr(NL80211_MESHCONF_HWMP_PERR_MIN_INTERVAL, mask))
+		mcfg->dot11MeshHWMPperrMinInterval = conf->dot11MeshHWMPperrMinInterval;
+#endif
+	if (chk_mesh_attr(NL80211_MESHCONF_HWMP_NET_DIAM_TRVS_TIME, mask))
+		mcfg->dot11MeshHWMPnetDiameterTraversalTime = conf->dot11MeshHWMPnetDiameterTraversalTime;
+
+	if (chk_mesh_attr(NL80211_MESHCONF_HWMP_ROOTMODE, mask))
+		mcfg->dot11MeshHWMPRootMode = conf->dot11MeshHWMPRootMode;
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 2, 0))
+	if (chk_mesh_attr(NL80211_MESHCONF_GATE_ANNOUNCEMENTS, mask))
+		mcfg->dot11MeshGateAnnouncementProtocol = conf->dot11MeshGateAnnouncementProtocol;
+	/* our current gate annc implementation rides on root annc with gate annc bit in PREQ flags */
+	if (mcfg->dot11MeshGateAnnouncementProtocol
+		&& mcfg->dot11MeshHWMPRootMode <= RTW_IEEE80211_ROOTMODE_ROOT
+	) {
+		mcfg->dot11MeshHWMPRootMode = RTW_IEEE80211_PROACTIVE_RANN;
+		RTW_INFO(ADPT_FMT" enable PROACTIVE_RANN becaue gate annc is needed\n", ADPT_ARG(adapter));
+	}
+	if (chk_mesh_attr(NL80211_MESHCONF_HWMP_RANN_INTERVAL, mask))
+		mcfg->dot11MeshHWMPRannInterval = conf->dot11MeshHWMPRannInterval;
+#endif
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 4, 0))
+	if (chk_mesh_attr(NL80211_MESHCONF_FORWARDING, mask))
+		mcfg->dot11MeshForwarding = conf->dot11MeshForwarding;
+
+	if (chk_mesh_attr(NL80211_MESHCONF_RSSI_THRESHOLD, mask))
+		mcfg->rssi_threshold = conf->rssi_threshold;
+#endif
+
+#if 0 /* controlled by driver */
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 5, 0))
+	if (chk_mesh_attr(NL80211_MESHCONF_HT_OPMODE, mask));
+#endif
+#endif
+	
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 6, 0))
+	if (chk_mesh_attr(NL80211_MESHCONF_HWMP_PATH_TO_ROOT_TIMEOUT, mask))
+		mcfg->dot11MeshHWMPactivePathToRootTimeout = conf->dot11MeshHWMPactivePathToRootTimeout;
+	if (chk_mesh_attr(NL80211_MESHCONF_HWMP_ROOT_INTERVAL, mask))
+		mcfg->dot11MeshHWMProotInterval = conf->dot11MeshHWMProotInterval;
+	if (chk_mesh_attr(NL80211_MESHCONF_HWMP_CONFIRMATION_INTERVAL, mask))
+		mcfg->dot11MeshHWMPconfirmationInterval = conf->dot11MeshHWMPconfirmationInterval;	
+#endif
+
+#if 0 /* TBD */
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 9, 0))
+	if (chk_mesh_attr(NL80211_MESHCONF_POWER_MODE, mask));
+	if (chk_mesh_attr(NL80211_MESHCONF_AWAKE_WINDOW, mask));
+#endif
+#endif
+
+#if 0 /* driver MPM */
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 11, 0))
+	if (chk_mesh_attr(NL80211_MESHCONF_PLINK_TIMEOUT, mask));
+#endif
+#endif
+}
+
+u8 *rtw_cfg80211_construct_mesh_beacon_ies(struct wiphy *wiphy, _adapter *adapter
+	, const struct mesh_config *conf, const struct mesh_setup *setup
+	, uint *ies_len)
+{
+	struct rtw_mesh_info *minfo = &adapter->mesh_info;
+	struct rtw_mesh_cfg *mcfg = &adapter->mesh_cfg;
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 6, 0))
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 8, 0))
+	struct cfg80211_chan_def *chdef = (struct cfg80211_chan_def *)(&setup->chandef);
+#endif
+	struct ieee80211_channel *chan;
+	u8 ch, bw, offset;
+#endif
+	uint len;
+	u8 n_bitrates;
+	u8 ht = 0;
+	u8 vht = 0;
+	u8 *rsn_ie = NULL;
+	sint rsn_ie_len = 0;
+	u8 *ies = NULL, *c;
+	u8 supported_rates[RTW_G_RATES_NUM] = {0};
+	int i;
+
+	*ies_len = 0;
+
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 8, 0))
+	chan = (struct ieee80211_channel *)chdef->chan;
+#elif (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 6, 0))
+	chan = (struct ieee80211_channel *)setup->channel;
+#endif
+
+	n_bitrates = wiphy->bands[chan->band]->n_bitrates;
+
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 6, 0))
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 8, 0))
+	rtw_get_chbw_from_cfg80211_chan_def(chdef, &ht, &ch, &bw, &offset);
+#else
+	rtw_get_chbw_from_nl80211_channel_type(chan, setup->channel_type, &ht, &ch, &bw, &offset);
+#endif
+	if (!ch)
+		goto exit;
+	
+#if defined(CONFIG_80211AC_VHT) && (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 6, 0))
+	vht = ht && ch > 14 && bw >= CHANNEL_WIDTH_80; /* VHT40/VHT20? */
+#endif
+
+	RTW_INFO(FUNC_ADPT_FMT" => ch:%u,%u,%u, ht:%u, vht:%u\n"
+		, FUNC_ADPT_ARG(adapter), ch, bw, offset, ht, vht);
+#endif
+
+	rsn_ie = rtw_get_ie(setup->ie, WLAN_EID_RSN, &rsn_ie_len, setup->ie_len);
+	if (rsn_ie && !rsn_ie_len) {
+		rtw_warn_on(1);
+		rsn_ie = NULL;
+	}
+
+	len = _BEACON_IE_OFFSET_
+		+ 2 /* 0-length SSID */
+		+ (n_bitrates >= 8 ? 8 : n_bitrates) + 2 /* Supported Rates */
+		+ 3 /* DS parameter set */
+		+ 6 /* TIM  */
+		+ (n_bitrates > 8 ? n_bitrates - 8 + 2 : 0) /* Extended Supported Rates */
+		+ (rsn_ie ? rsn_ie_len + 2 : 0) /* RSN */
+		#if defined(CONFIG_80211N_HT)
+		+ (ht ? HT_CAP_IE_LEN + 2 + HT_OP_IE_LEN + 2 : 0) /* HT */
+		#endif
+		#if defined(CONFIG_80211AC_VHT) && (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 6, 0))
+		+ (vht ? VHT_CAP_IE_LEN + 2 + VHT_OP_IE_LEN + 2 : 0) /* VHT */
+		#endif
+		+ minfo->mesh_id_len + 2 /* Mesh ID */
+		+ 9 /* Mesh configuration */
+		;
+
+	ies = rtw_zmalloc(len);
+	if (!ies)
+		goto exit;
+
+	/* timestamp */
+	c = ies + 8;
+
+	/* beacon interval */
+	RTW_PUT_LE16(c , setup->beacon_interval);
+	c += 2;
+
+	/* capability */
+	if (rsn_ie)
+		*((u16 *)c) |= cpu_to_le16(cap_Privacy);
+	c += 2;
+
+	/* SSID */
+	c = rtw_set_ie(c, WLAN_EID_SSID, 0, NULL, NULL);
+
+	/* Supported Rates */
+	for (i = 0; i < n_bitrates; i++) {
+		supported_rates[i] = wiphy->bands[chan->band]->bitrates[i].bitrate / 5;
+		#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 11, 0))
+		if (setup->basic_rates & BIT(i))
+		#else
+		if (rtw_is_basic_rate_mix(supported_rates[i]))
+		#endif
+			supported_rates[i] |= IEEE80211_BASIC_RATE_MASK;
+	}
+	c = rtw_set_ie(c, WLAN_EID_SUPP_RATES, (n_bitrates >= 8 ? 8 : n_bitrates), supported_rates, NULL);
+
+	/* DS parameter set */
+	c = rtw_set_ie(c, WLAN_EID_DS_PARAMS, 1, &ch, NULL);
+
+	/* TIM */
+	*c = WLAN_EID_TIM;
+	*(c + 1) = 4;
+	c += 6;
+	//c = rtw_set_ie(c, _TIM_IE_, 4, NULL, NULL);
+
+	/* Extended Supported Rates */
+	if (n_bitrates > 8)
+		c = rtw_set_ie(c, WLAN_EID_EXT_SUPP_RATES, n_bitrates - 8, supported_rates + 8, NULL);
+
+	/* RSN */
+	if (rsn_ie)
+		c = rtw_set_ie(c, WLAN_EID_RSN, rsn_ie_len, rsn_ie + 2, NULL);
+
+#if defined(CONFIG_80211N_HT)
+	if (ht) {
+		struct ieee80211_sta_ht_cap *sta_ht_cap = &wiphy->bands[chan->band]->ht_cap;
+		u8 ht_cap[HT_CAP_IE_LEN];
+		u8 ht_op[HT_OP_IE_LEN];
+
+		_rtw_memset(ht_cap, 0, HT_CAP_IE_LEN);
+		_rtw_memset(ht_op, 0, HT_OP_IE_LEN);
+
+		/* WLAN_EID_HT_CAP */
+		RTW_PUT_LE16(HT_CAP_ELE_CAP_INFO(ht_cap), sta_ht_cap->cap);
+		SET_HT_CAP_ELE_MAX_AMPDU_LEN_EXP(ht_cap, sta_ht_cap->ampdu_factor);
+		SET_HT_CAP_ELE_MIN_MPDU_S_SPACE(ht_cap, sta_ht_cap->ampdu_density);
+		_rtw_memcpy(HT_CAP_ELE_SUP_MCS_SET(ht_cap), &sta_ht_cap->mcs, 16);
+		c = rtw_set_ie(c, WLAN_EID_HT_CAP, HT_CAP_IE_LEN, ht_cap, NULL);
+
+		/* WLAN_EID_HT_OPERATION */
+		SET_HT_OP_ELE_PRI_CHL(ht_op, ch);
+		switch (offset) {
+		case HAL_PRIME_CHNL_OFFSET_LOWER:
+			SET_HT_OP_ELE_2ND_CHL_OFFSET(ht_op, SCA);
+			break;
+		case HAL_PRIME_CHNL_OFFSET_UPPER:
+			SET_HT_OP_ELE_2ND_CHL_OFFSET(ht_op, SCB);
+			break;
+		case HAL_PRIME_CHNL_OFFSET_DONT_CARE:
+		default:
+			SET_HT_OP_ELE_2ND_CHL_OFFSET(ht_op, SCN);
+			break;
+		}
+		if (bw >= CHANNEL_WIDTH_40)
+			SET_HT_OP_ELE_STA_CHL_WIDTH(ht_op, 1);
+		else
+			SET_HT_OP_ELE_STA_CHL_WIDTH(ht_op, 0);
+		c = rtw_set_ie(c, WLAN_EID_HT_OPERATION, HT_OP_IE_LEN, ht_op, NULL);
+	}
+#endif /* defined(CONFIG_80211N_HT) */
+
+#if defined(CONFIG_80211AC_VHT) && (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 6, 0))
+	if (vht) {
+		struct ieee80211_sta_vht_cap *sta_vht_cap = &wiphy->bands[chan->band]->vht_cap;
+		u8 vht_cap[VHT_CAP_IE_LEN];
+		u8 vht_op[VHT_OP_IE_LEN];
+		u8 cch = rtw_get_center_ch(ch, bw, offset);
+
+		_rtw_memset(vht_op, 0, VHT_OP_IE_LEN);
+
+		/* WLAN_EID_VHT_CAPABILITY */
+		_rtw_memcpy(vht_cap, &sta_vht_cap->cap, 4);
+		_rtw_memcpy(vht_cap + 4, &sta_vht_cap->vht_mcs, 8);
+		c = rtw_set_ie(c, WLAN_EID_VHT_CAPABILITY, VHT_CAP_IE_LEN, vht_cap, NULL);
+
+		/* WLAN_EID_VHT_OPERATION */
+		if (bw < CHANNEL_WIDTH_80) {
+			SET_VHT_OPERATION_ELE_CHL_WIDTH(vht_op, 0);
+			SET_VHT_OPERATION_ELE_CHL_CENTER_FREQ1(vht_op, 0);
+			SET_VHT_OPERATION_ELE_CHL_CENTER_FREQ2(vht_op, 0);
+		} else if (bw == CHANNEL_WIDTH_80) {
+			SET_VHT_OPERATION_ELE_CHL_WIDTH(vht_op, 1);
+			SET_VHT_OPERATION_ELE_CHL_CENTER_FREQ1(vht_op, cch);
+			SET_VHT_OPERATION_ELE_CHL_CENTER_FREQ2(vht_op, 0);
+		} else {
+			RTW_ERR(FUNC_ADPT_FMT" unsupported BW:%u\n", FUNC_ADPT_ARG(adapter), bw);
+			rtw_warn_on(1);
+			rtw_mfree(ies, len);
+			goto exit;
+		}
+
+		/* Hard code 1 stream, MCS0-7 is a min Basic VHT MCS rates */
+		vht_op[3] = 0xfc;
+		vht_op[4] = 0xff;
+		c = rtw_set_ie(c, WLAN_EID_VHT_OPERATION, VHT_OP_IE_LEN, vht_op, NULL);
+	}
+#endif /* defined(CONFIG_80211AC_VHT) && (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 6, 0)) */
+
+	/* Mesh ID */
+	c = rtw_set_ie_mesh_id(c, NULL, minfo->mesh_id, minfo->mesh_id_len);
+
+	/* Mesh configuration */
+	c = rtw_set_ie_mesh_config(c, NULL
+		, minfo->mesh_pp_id
+		, minfo->mesh_pm_id
+		, minfo->mesh_cc_id
+		, minfo->mesh_sp_id
+		, minfo->mesh_auth_id
+		, 0, 0, 0
+		, 1
+		, 0, 0
+		, mcfg->dot11MeshForwarding
+		, 0, 0, 0
+	);
+
+#if DBG_RTW_CFG80211_MESH_CONF
+	RTW_INFO(FUNC_ADPT_FMT" ies_len:%u\n", FUNC_ADPT_ARG(adapter), len);
+	dump_ies(RTW_DBGDUMP, ies + _BEACON_IE_OFFSET_, len - _BEACON_IE_OFFSET_);
+#endif
+
+exit:
+	if (ies)
+		*ies_len = len;
+	return ies;
+}
+
+static int cfg80211_rtw_get_mesh_config(struct wiphy *wiphy, struct net_device *dev
+	, struct mesh_config *conf)
+{
+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
+	struct rtw_mesh_cfg *mesh_cfg = &adapter->mesh_cfg;
+	int ret = 0;
+
+	RTW_INFO(FUNC_ADPT_FMT"\n", FUNC_ADPT_ARG(adapter));
+
+	/* driver MPM */
+	conf->dot11MeshRetryTimeout = 0;
+	conf->dot11MeshConfirmTimeout = 0;
+	conf->dot11MeshHoldingTimeout = 0;
+	conf->dot11MeshMaxPeerLinks = mesh_cfg->max_peer_links;
+	conf->dot11MeshMaxRetries = 0;
+
+	conf->dot11MeshTTL = mesh_cfg->dot11MeshTTL;
+	conf->element_ttl = mesh_cfg->element_ttl;
+
+	/* driver MPM */
+	conf->auto_open_plinks = 0;
+
+	/* TBD: synchronization */
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 5, 0))
+	conf->dot11MeshNbrOffsetMaxNeighbor = 0;
+#endif
+
+	conf->dot11MeshHWMPmaxPREQretries = mesh_cfg->dot11MeshHWMPmaxPREQretries;
+	conf->path_refresh_time = mesh_cfg->path_refresh_time;
+	conf->min_discovery_timeout = mesh_cfg->min_discovery_timeout;
+	conf->dot11MeshHWMPactivePathTimeout = mesh_cfg->dot11MeshHWMPactivePathTimeout;
+	conf->dot11MeshHWMPpreqMinInterval = mesh_cfg->dot11MeshHWMPpreqMinInterval;
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 3, 0))
+	conf->dot11MeshHWMPperrMinInterval = mesh_cfg->dot11MeshHWMPperrMinInterval;
+#endif
+	conf->dot11MeshHWMPnetDiameterTraversalTime = mesh_cfg->dot11MeshHWMPnetDiameterTraversalTime;
+	conf->dot11MeshHWMPRootMode = mesh_cfg->dot11MeshHWMPRootMode;
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 2, 0))
+	conf->dot11MeshHWMPRannInterval = mesh_cfg->dot11MeshHWMPRannInterval;
+#endif
+	conf->dot11MeshGateAnnouncementProtocol = mesh_cfg->dot11MeshGateAnnouncementProtocol;
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 4, 0))
+	conf->dot11MeshForwarding = mesh_cfg->dot11MeshForwarding;
+	conf->rssi_threshold = mesh_cfg->rssi_threshold;
+#endif
+
+	/* TBD */
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 5, 0))
+	conf->ht_opmode = 0xffff;
+#endif
+
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 6, 0))
+	conf->dot11MeshHWMPactivePathToRootTimeout = mesh_cfg->dot11MeshHWMPactivePathToRootTimeout;
+	conf->dot11MeshHWMProotInterval = mesh_cfg->dot11MeshHWMProotInterval;
+	conf->dot11MeshHWMPconfirmationInterval = mesh_cfg->dot11MeshHWMPconfirmationInterval;
+#endif
+
+	/* TBD: power save */
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 9, 0))
+	conf->power_mode = NL80211_MESH_POWER_ACTIVE;
+	conf->dot11MeshAwakeWindowDuration = 0;
+#endif
+
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 11, 0))
+	conf->plink_timeout = mesh_cfg->plink_timeout;
+#endif
+
+	return ret;
+}
+
+static void rtw_mbss_info_change_notify(_adapter *adapter, bool minfo_changed, bool need_work)
+{
+	if (need_work)
+		rtw_mesh_work(&adapter->mesh_work);
+}
+
+static int cfg80211_rtw_update_mesh_config(struct wiphy *wiphy, struct net_device *dev
+	, u32 mask, const struct mesh_config *nconf)
+{
+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
+	int ret = 0;
+	bool minfo_changed = _FALSE, need_work = _FALSE;
+
+	RTW_INFO(FUNC_ADPT_FMT" mask:0x%08x\n", FUNC_ADPT_ARG(adapter), mask);
+
+	rtw_cfg80211_mesh_cfg_set(adapter, nconf, mask);
+	update_beacon(adapter, WLAN_EID_MESH_CONFIG, NULL, _TRUE);
+#if CONFIG_RTW_MESH_CTO_MGATE_CARRIER
+	if (rtw_mesh_cto_mgate_required(adapter))
+		rtw_netif_carrier_off(adapter->pnetdev);
+	else
+		rtw_netif_carrier_on(adapter->pnetdev);
+#endif
+	need_work = rtw_ieee80211_mesh_root_setup(adapter);
+
+	rtw_mbss_info_change_notify(adapter, minfo_changed, need_work);
+
+	return ret;
+}
+
+static int cfg80211_rtw_join_mesh(struct wiphy *wiphy, struct net_device *dev,
+	const struct mesh_config *conf, const struct mesh_setup *setup)
+{
+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
+	u8 *ies = NULL;
+	uint ies_len;
+	int ret = 0;
+
+	RTW_INFO(FUNC_ADPT_FMT"\n", FUNC_ADPT_ARG(adapter));
+
+#if DBG_RTW_CFG80211_MESH_CONF
+	RTW_INFO(FUNC_ADPT_FMT" mesh_setup:\n", FUNC_ADPT_ARG(adapter));
+	dump_mesh_setup(RTW_DBGDUMP, wiphy, setup);
+	RTW_INFO(FUNC_ADPT_FMT" mesh_config:\n", FUNC_ADPT_ARG(adapter));
+	dump_mesh_config(RTW_DBGDUMP, conf);
+#endif
+
+	if (rtw_cfg80211_sync_iftype(adapter) != _SUCCESS) {
+		ret = -ENOTSUPP;
+		goto exit;
+	}
+
+	/* initialization */
+	rtw_mesh_init_mesh_info(adapter);
+
+	/* apply cfg80211 settings*/
+	rtw_cfg80211_mesh_info_set_profile(&adapter->mesh_info, setup);
+	rtw_cfg80211_mesh_cfg_set(adapter, conf, 0xFFFFFFFF);
+
+	/* apply cfg80211 settings (join only) */
+	rtw_mesh_cfg_init_max_peer_links(adapter, conf->dot11MeshMaxPeerLinks);
+	#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 11, 0))
+	rtw_mesh_cfg_init_plink_timeout(adapter, conf->plink_timeout);
+	#endif
+
+	rtw_ieee80211_mesh_root_setup(adapter);
+
+	ies = rtw_cfg80211_construct_mesh_beacon_ies(wiphy, adapter, conf, setup, &ies_len);
+	if (!ies) {
+		ret = -EINVAL;
+		goto exit;
+	}
+
+	/* start mbss */
+	if (rtw_check_beacon_data(adapter, ies,  ies_len) != _SUCCESS) {
+		ret = -EINVAL;
+		goto exit;
+	}
+	
+	rtw_mesh_work(&adapter->mesh_work);
+
+exit:
+	if (ies)
+		rtw_mfree(ies, ies_len);
+	if (ret)
+		rtw_mesh_deinit_mesh_info(adapter);
+
+	return ret;
+}
+
+static int cfg80211_rtw_leave_mesh(struct wiphy *wiphy, struct net_device *dev)
+{
+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
+	int ret = 0;
+
+	RTW_INFO(FUNC_ADPT_FMT"\n", FUNC_ADPT_ARG(adapter));
+
+	rtw_mesh_deinit_mesh_info(adapter);
+
+	rtw_set_802_11_infrastructure_mode(adapter, Ndis802_11Infrastructure);
+	rtw_setopmode_cmd(adapter, Ndis802_11Infrastructure, RTW_CMDF_WAIT_ACK);
+
+	return ret;
+}
+
+static int cfg80211_rtw_add_mpath(struct wiphy *wiphy, struct net_device *dev
+	#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 16, 0))
+	, const u8 *dst, const u8 *next_hop
+	#else
+	, u8 *dst, u8 *next_hop
+	#endif
+)
+{
+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
+	struct sta_priv *stapriv = &adapter->stapriv;
+	struct sta_info *sta;
+	struct rtw_mesh_path *mpath;
+	int ret = 0;
+
+	rtw_rcu_read_lock();
+
+	sta = rtw_get_stainfo(stapriv, next_hop);
+	if (!sta) {
+		ret = -ENOENT;
+		goto exit;
+	}
+
+	mpath = rtw_mesh_path_add(adapter, dst);
+	if (!mpath) {
+		ret = -ENOENT;
+		goto exit;
+	}
+
+	rtw_mesh_path_fix_nexthop(mpath, sta);
+
+exit:
+	rtw_rcu_read_unlock();
+
+	return ret;
+}
+
+static int cfg80211_rtw_del_mpath(struct wiphy *wiphy, struct net_device *dev
+	#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 16, 0))
+	, const u8 *dst
+	#else
+	, u8 *dst
+	#endif
+)
+{
+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
+	int ret = 0;
+
+	if (dst) {
+		if (rtw_mesh_path_del(adapter, dst)) {
+			ret = -ENOENT;
+			goto exit;
+		}
+	} else {
+		rtw_mesh_path_flush_by_iface(adapter);
+	}	
+
+exit:
+	return ret;
+}
+
+static int cfg80211_rtw_change_mpath(struct wiphy *wiphy, struct net_device *dev
+	#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 16, 0))
+	, const u8 *dst, const u8 *next_hop
+	#else
+	, u8 *dst, u8 *next_hop
+	#endif
+)
+{
+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
+	struct sta_priv *stapriv = &adapter->stapriv;
+	struct sta_info *sta;
+	struct rtw_mesh_path *mpath;
+	int ret = 0;
+
+	rtw_rcu_read_lock();
+
+	sta = rtw_get_stainfo(stapriv, next_hop);
+	if (!sta) {
+		ret = -ENOENT;
+		goto exit;
+	}
+
+	mpath = rtw_mesh_path_lookup(adapter, dst);
+	if (!mpath) {
+		ret = -ENOENT;
+		goto exit;
+	}
+
+	rtw_mesh_path_fix_nexthop(mpath, sta);
+
+exit:
+	rtw_rcu_read_unlock();
+
+	return ret;
+}
+
+static void rtw_cfg80211_mpath_set_pinfo(struct rtw_mesh_path *mpath, u8 *next_hop, struct mpath_info *pinfo)
+{
+	struct sta_info *next_hop_sta = rtw_rcu_dereference(mpath->next_hop);
+
+	if (next_hop_sta)
+		_rtw_memcpy(next_hop, next_hop_sta->cmn.mac_addr, ETH_ALEN);
+	else
+		_rtw_memset(next_hop, 0, ETH_ALEN);
+
+	_rtw_memset(pinfo, 0, sizeof(*pinfo));
+
+	pinfo->generation = mpath->adapter->mesh_info.mesh_paths_generation;
+
+	pinfo->filled = 0
+		| MPATH_INFO_FRAME_QLEN
+		| MPATH_INFO_SN
+		| MPATH_INFO_METRIC
+		| MPATH_INFO_EXPTIME
+		| MPATH_INFO_DISCOVERY_TIMEOUT
+		| MPATH_INFO_DISCOVERY_RETRIES
+		| MPATH_INFO_FLAGS
+		;
+
+	pinfo->frame_qlen = mpath->frame_queue_len;
+	pinfo->sn = mpath->sn;
+	pinfo->metric = mpath->metric;
+	if (rtw_time_after(mpath->exp_time, rtw_get_current_time()))
+		pinfo->exptime = rtw_get_remaining_time_ms(mpath->exp_time);
+	pinfo->discovery_timeout = rtw_systime_to_ms(mpath->discovery_timeout);
+	pinfo->discovery_retries = mpath->discovery_retries;
+	if (mpath->flags & RTW_MESH_PATH_ACTIVE)
+		pinfo->flags |= NL80211_MPATH_FLAG_ACTIVE;
+	if (mpath->flags & RTW_MESH_PATH_RESOLVING)
+		pinfo->flags |= NL80211_MPATH_FLAG_RESOLVING;
+	if (mpath->flags & RTW_MESH_PATH_SN_VALID)
+		pinfo->flags |= NL80211_MPATH_FLAG_SN_VALID;
+	if (mpath->flags & RTW_MESH_PATH_FIXED)
+		pinfo->flags |= NL80211_MPATH_FLAG_FIXED;
+	if (mpath->flags & RTW_MESH_PATH_RESOLVED)
+		pinfo->flags |= NL80211_MPATH_FLAG_RESOLVED;
+}
+
+static int cfg80211_rtw_get_mpath(struct wiphy *wiphy, struct net_device *dev, u8 *dst, u8 *next_hop, struct mpath_info *pinfo)
+{
+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
+	struct rtw_mesh_path *mpath;
+	int ret = 0;
+
+	rtw_rcu_read_lock();
+
+	mpath = rtw_mesh_path_lookup(adapter, dst);
+	if (!mpath) {
+		ret = -ENOENT;
+		goto exit;
+	}
+
+	rtw_cfg80211_mpath_set_pinfo(mpath, next_hop, pinfo);
+
+exit:
+	rtw_rcu_read_unlock();
+
+	return ret;
+}
+
+static int cfg80211_rtw_dump_mpath(struct wiphy *wiphy, struct net_device *dev, int idx, u8 *dst, u8 *next_hop, struct mpath_info *pinfo)
+{
+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
+	struct rtw_mesh_path *mpath;
+	int ret = 0;
+
+	rtw_rcu_read_lock();
+
+	mpath = rtw_mesh_path_lookup_by_idx(adapter, idx);
+	if (!mpath) {
+		ret = -ENOENT;
+		goto exit;
+	}
+
+	_rtw_memcpy(dst, mpath->dst, ETH_ALEN);
+	rtw_cfg80211_mpath_set_pinfo(mpath, next_hop, pinfo);
+
+exit:
+	rtw_rcu_read_unlock();
+
+	return ret;
+}
+
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 19, 0))
+static void rtw_cfg80211_mpp_set_pinfo(struct rtw_mesh_path *mpath, u8 *mpp, struct mpath_info *pinfo)
+{
+	_rtw_memcpy(mpp, mpath->mpp, ETH_ALEN);
+
+	_rtw_memset(pinfo, 0, sizeof(*pinfo));
+	pinfo->generation = mpath->adapter->mesh_info.mpp_paths_generation;
+}
+
+static int cfg80211_rtw_get_mpp(struct wiphy *wiphy, struct net_device *dev, u8 *dst, u8 *mpp, struct mpath_info *pinfo)
+{
+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
+	struct rtw_mesh_path *mpath;
+	int ret = 0;
+
+	rtw_rcu_read_lock();
+
+	mpath = rtw_mpp_path_lookup(adapter, dst);
+	if (!mpath) {
+		ret = -ENOENT;
+		goto exit;
+	}
+
+	rtw_cfg80211_mpp_set_pinfo(mpath, mpp, pinfo);
+
+exit:
+	rtw_rcu_read_unlock();
+
+	return ret;
+}
+
+static int cfg80211_rtw_dump_mpp(struct wiphy *wiphy, struct net_device *dev, int idx, u8 *dst, u8 *mpp, struct mpath_info *pinfo)
+{
+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
+	struct rtw_mesh_path *mpath;
+	int ret = 0;
+
+	rtw_rcu_read_lock();
+
+	mpath = rtw_mpp_path_lookup_by_idx(adapter, idx);
+	if (!mpath) {
+		ret = -ENOENT;
+		goto exit;
+	}
+
+	_rtw_memcpy(dst, mpath->dst, ETH_ALEN);
+	rtw_cfg80211_mpp_set_pinfo(mpath, mpp, pinfo);
+
+exit:
+	rtw_rcu_read_unlock();
+
+	return ret;
+}
+#endif /* (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 19, 0)) */
+
+#endif /* defined(CONFIG_RTW_MESH) */
+
+#if defined(CONFIG_PNO_SUPPORT) && (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 0, 0))
+static int cfg80211_rtw_sched_scan_start(struct wiphy *wiphy,
+		struct net_device *dev,
+		struct cfg80211_sched_scan_request *request)
+{
+
+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
+	struct	mlme_priv	*pmlmepriv = &(padapter->mlmepriv);
+	struct cfg80211_ssid *ssids;
+	int n_ssids = 0;
+	int interval = 0;
+	int i = 0;
+	u8 ret;
+
+	if (padapter->bup == _FALSE) {
+		RTW_INFO("%s: net device is down.\n", __func__);
+		return -EIO;
+	}
+
+	if (check_fwstate(pmlmepriv, _FW_UNDER_SURVEY) == _TRUE ||
+		check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE  ||
+		check_fwstate(pmlmepriv, _FW_UNDER_LINKING) == _TRUE) {
+		RTW_INFO("%s: device is busy.\n", __func__);
+		rtw_scan_abort(padapter);
+	}
+
+	if (request == NULL) {
+		RTW_INFO("%s: invalid cfg80211_requests parameters.\n", __func__);
+		return -EINVAL;
+	}
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(3, 2, 0)
+
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 4, 0)
+	interval = request->scan_plans->interval;
+#else
+	interval = request->interval;
+#endif
+	n_ssids = request->n_match_sets;
+	ssids = (struct cfg80211_ssid *)rtw_zmalloc(n_ssids * sizeof(struct cfg80211_ssid));
+	if(ssids == NULL) {
+		RTW_ERR("Fail to allocate ssids for PNO\n");
+		return -ENOMEM;
+	}
+	for (i=0;i<request->n_match_sets;i++) {
+			ssids[i].ssid_len = request->match_sets[i].ssid.ssid_len;
+			memcpy(ssids[i].ssid, request->match_sets[i].ssid.ssid,
+					request->match_sets[i].ssid.ssid_len);
+	}
+#else
+	interval = request->interval;
+	n_ssids = request->n_ssids;
+	ssids = request->ssids;
+#endif
+ret = rtw_android_cfg80211_pno_setup(dev, ssids,
+			n_ssids, interval);
+	if (ret < 0) {
+		RTW_INFO("%s ret: %d\n", __func__, ret);
+		goto exit;
+	}
+
+	ret = rtw_android_pno_enable(dev, _TRUE);
+	if (ret < 0) {
+		RTW_INFO("%s ret: %d\n", __func__, ret);
+		goto exit;
+	}
+exit:
+	return ret;
+}
+
+static int cfg80211_rtw_sched_scan_stop(struct wiphy *wiphy,
+		struct net_device *dev)
+{
+	return rtw_android_pno_enable(dev, _FALSE);
+}
+
+int	cfg80211_rtw_suspend(struct wiphy *wiphy, struct cfg80211_wowlan *wow) {
+	RTW_DBG("==> %s\n",__func__);
+	RTW_DBG("<== %s\n",__func__);
+	return 0;
+}
+
+int	cfg80211_rtw_resume(struct wiphy *wiphy) {
+
+	_adapter *padapter;
+	struct pwrctrl_priv *pwrpriv;
+	struct mlme_priv *pmlmepriv;
+	padapter = wiphy_to_adapter(wiphy);
+	pwrpriv = adapter_to_pwrctl(padapter);
+	pmlmepriv = &padapter->mlmepriv;
+	struct sitesurvey_parm parm;
+	int i, len;
+
+
+	RTW_DBG("==> %s\n",__func__);
+	if (pwrpriv->wowlan_last_wake_reason == RX_PNO) {
+
+		struct rtw_wdev_priv *pwdev_priv = adapter_wdev_data(padapter);
+		_irqL irqL;
+		int PNOWakeupScanWaitCnt = 0;
+
+		rtw_cfg80211_disconnected(padapter->rtw_wdev, 0, NULL, 0, 1, GFP_ATOMIC);
+
+		rtw_init_sitesurvey_parm(padapter, &parm);
+		for (i=0;i<pwrpriv->pnlo_info->ssid_num && i < RTW_SSID_SCAN_AMOUNT; i++) {
+			len = pwrpriv->pno_ssid_list->node[i].SSID_len;
+			_rtw_memcpy(&parm.ssid[i].Ssid, pwrpriv->pno_ssid_list->node[i].SSID, len);
+			parm.ssid[i].SsidLength = len;
+		}
+		parm.ssid_num = pwrpriv->pnlo_info->ssid_num;
+
+		_enter_critical_bh(&pmlmepriv->lock, &irqL);
+		//This modification fix PNO wakeup reconnect issue with hidden SSID AP.
+		//rtw_sitesurvey_cmd(padapter, NULL);
+		rtw_sitesurvey_cmd(padapter, &parm);
+		_exit_critical_bh(&pmlmepriv->lock, &irqL);
+		
+		for (PNOWakeupScanWaitCnt = 0; PNOWakeupScanWaitCnt < 10; PNOWakeupScanWaitCnt++) {
+			if(check_fwstate(pmlmepriv, _FW_UNDER_SURVEY) == _FALSE)
+				break;
+			rtw_msleep_os(1000);
+		}
+		
+		_enter_critical_bh(&pmlmepriv->lock, &irqL);
+		cfg80211_sched_scan_results(padapter->rtw_wdev->wiphy);
+		_exit_critical_bh(&pmlmepriv->lock, &irqL);
+
+	}
+	RTW_DBG("<== %s\n",__func__);
+	return 0;
+	
+}
+#endif /* CONFIG_PNO_SUPPORT */
+
+static int rtw_cfg80211_set_beacon_wpsp2pie(struct net_device *ndev, char *buf, int len)
+{
+	int ret = 0;
+	uint wps_ielen = 0;
+	u8 *wps_ie;
+	u32	p2p_ielen = 0;
+	u8 wps_oui[8] = {0x0, 0x50, 0xf2, 0x04};
+	u8 *p2p_ie;
+	u32	wfd_ielen = 0;
+	u8 *wfd_ie;
+	_adapter *padapter = (_adapter *)rtw_netdev_priv(ndev);
+	struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
+	struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv);
+
+	RTW_INFO(FUNC_NDEV_FMT" ielen=%d\n", FUNC_NDEV_ARG(ndev), len);
+
+	if (len > 0) {
+		wps_ie = rtw_get_wps_ie(buf, len, NULL, &wps_ielen);
+		if (wps_ie) {
+			#ifdef CONFIG_DEBUG_CFG80211
+			RTW_INFO("bcn_wps_ielen=%d\n", wps_ielen);
+			#endif
+
+			if (pmlmepriv->wps_beacon_ie) {
+				u32 free_len = pmlmepriv->wps_beacon_ie_len;
+				pmlmepriv->wps_beacon_ie_len = 0;
+				rtw_mfree(pmlmepriv->wps_beacon_ie, free_len);
+				pmlmepriv->wps_beacon_ie = NULL;
+			}
+
+			pmlmepriv->wps_beacon_ie = rtw_malloc(wps_ielen);
+			if (pmlmepriv->wps_beacon_ie == NULL) {
+				RTW_INFO("%s()-%d: rtw_malloc() ERROR!\n", __FUNCTION__, __LINE__);
+				return -EINVAL;
+
+			}
+
+			_rtw_memcpy(pmlmepriv->wps_beacon_ie, wps_ie, wps_ielen);
+			pmlmepriv->wps_beacon_ie_len = wps_ielen;
+
+			update_beacon(padapter, _VENDOR_SPECIFIC_IE_, wps_oui, _TRUE);
+
+		}
+
+		/* buf += wps_ielen; */
+		/* len -= wps_ielen; */
+
+		#ifdef CONFIG_P2P
+		p2p_ie = rtw_get_p2p_ie(buf, len, NULL, &p2p_ielen);
+		if (p2p_ie) {
+			#ifdef CONFIG_DEBUG_CFG80211
+			RTW_INFO("bcn_p2p_ielen=%d\n", p2p_ielen);
+			#endif
+
+			if (pmlmepriv->p2p_beacon_ie) {
+				u32 free_len = pmlmepriv->p2p_beacon_ie_len;
+				pmlmepriv->p2p_beacon_ie_len = 0;
+				rtw_mfree(pmlmepriv->p2p_beacon_ie, free_len);
+				pmlmepriv->p2p_beacon_ie = NULL;
+			}
+
+			pmlmepriv->p2p_beacon_ie = rtw_malloc(p2p_ielen);
+			if (pmlmepriv->p2p_beacon_ie == NULL) {
+				RTW_INFO("%s()-%d: rtw_malloc() ERROR!\n", __FUNCTION__, __LINE__);
+				return -EINVAL;
+
+			}
+
+			_rtw_memcpy(pmlmepriv->p2p_beacon_ie, p2p_ie, p2p_ielen);
+			pmlmepriv->p2p_beacon_ie_len = p2p_ielen;
+
+		}
+		#endif /* CONFIG_P2P */
+
+
+		#ifdef CONFIG_WFD
+		wfd_ie = rtw_get_wfd_ie(buf, len, NULL, &wfd_ielen);
+		if (wfd_ie) {
+			#ifdef CONFIG_DEBUG_CFG80211
+			RTW_INFO("bcn_wfd_ielen=%d\n", wfd_ielen);
+			#endif
+
+			if (rtw_mlme_update_wfd_ie_data(pmlmepriv, MLME_BEACON_IE, wfd_ie, wfd_ielen) != _SUCCESS)
+				return -EINVAL;
+		}
+		#endif /* CONFIG_WFD */
+
+		pmlmeext->bstart_bss = _TRUE;
+
+	}
+
+	return ret;
+
+}
+
+static int rtw_cfg80211_set_probe_resp_wpsp2pie(struct net_device *net, char *buf, int len)
+{
+	int ret = 0;
+	uint wps_ielen = 0;
+	u8 *wps_ie;
+	u32	p2p_ielen = 0;
+	u8 *p2p_ie;
+	u32	wfd_ielen = 0;
+	u8 *wfd_ie;
+	_adapter *padapter = (_adapter *)rtw_netdev_priv(net);
+	struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
+
+#ifdef CONFIG_DEBUG_CFG80211
+	RTW_INFO("%s, ielen=%d\n", __func__, len);
+#endif
+
+	if (len > 0) {
+		wps_ie = rtw_get_wps_ie(buf, len, NULL, &wps_ielen);
+		if (wps_ie) {
+			uint	attr_contentlen = 0;
+			u16	uconfig_method, *puconfig_method = NULL;
+
+			#ifdef CONFIG_DEBUG_CFG80211
+			RTW_INFO("probe_resp_wps_ielen=%d\n", wps_ielen);
+			#endif
+
+			if (check_fwstate(pmlmepriv, WIFI_UNDER_WPS)) {
+				u8 sr = 0;
+				rtw_get_wps_attr_content(wps_ie,  wps_ielen, WPS_ATTR_SELECTED_REGISTRAR, (u8 *)(&sr), NULL);
+
+				if (sr != 0)
+					RTW_INFO("%s, got sr\n", __func__);
+				else {
+					RTW_INFO("GO mode process WPS under site-survey,  sr no set\n");
+					return ret;
+				}
+			}
+
+			if (pmlmepriv->wps_probe_resp_ie) {
+				u32 free_len = pmlmepriv->wps_probe_resp_ie_len;
+				pmlmepriv->wps_probe_resp_ie_len = 0;
+				rtw_mfree(pmlmepriv->wps_probe_resp_ie, free_len);
+				pmlmepriv->wps_probe_resp_ie = NULL;
+			}
+
+			pmlmepriv->wps_probe_resp_ie = rtw_malloc(wps_ielen);
+			if (pmlmepriv->wps_probe_resp_ie == NULL) {
+				RTW_INFO("%s()-%d: rtw_malloc() ERROR!\n", __FUNCTION__, __LINE__);
+				return -EINVAL;
+
+			}
+
+			/* add PUSH_BUTTON config_method by driver self in wpsie of probe_resp at GO Mode */
+			puconfig_method = (u16 *)rtw_get_wps_attr_content(wps_ie, wps_ielen, WPS_ATTR_CONF_METHOD , NULL, &attr_contentlen);
+			if (puconfig_method != NULL) {
+				/* struct registry_priv *pregistrypriv = &padapter->registrypriv; */
+				struct wireless_dev *wdev = padapter->rtw_wdev;
+
+				#ifdef CONFIG_DEBUG_CFG80211
+				/* printk("config_method in wpsie of probe_resp = 0x%x\n", be16_to_cpu(*puconfig_method)); */
+				#endif
+
+				#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) || defined(COMPAT_KERNEL_RELEASE)
+				/* for WIFI-DIRECT LOGO 4.2.2, AUTO GO can't set PUSH_BUTTON flags */
+				if (wdev->iftype == NL80211_IFTYPE_P2P_GO) {
+					uconfig_method = WPS_CM_PUSH_BUTTON;
+					uconfig_method = cpu_to_be16(uconfig_method);
+
+					*puconfig_method &= ~uconfig_method;
+				}
+				#endif
+			}
+
+			_rtw_memcpy(pmlmepriv->wps_probe_resp_ie, wps_ie, wps_ielen);
+			pmlmepriv->wps_probe_resp_ie_len = wps_ielen;
+
+		}
+
+		/* buf += wps_ielen; */
+		/* len -= wps_ielen; */
+
+		#ifdef CONFIG_P2P
+		p2p_ie = rtw_get_p2p_ie(buf, len, NULL, &p2p_ielen);
+		if (p2p_ie) {
+			u8 is_GO = _FALSE;
+			u32 attr_contentlen = 0;
+			u16 cap_attr = 0;
+
+			#ifdef CONFIG_DEBUG_CFG80211
+			RTW_INFO("probe_resp_p2p_ielen=%d\n", p2p_ielen);
+			#endif
+
+			/* Check P2P Capability ATTR */
+			if (rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_CAPABILITY, (u8 *)&cap_attr, (uint *) &attr_contentlen)) {
+				u8 grp_cap = 0;
+				/* RTW_INFO( "[%s] Got P2P Capability Attr!!\n", __FUNCTION__ ); */
+				cap_attr = le16_to_cpu(cap_attr);
+				grp_cap = (u8)((cap_attr >> 8) & 0xff);
+
+				is_GO = (grp_cap & BIT(0)) ? _TRUE : _FALSE;
+
+				if (is_GO)
+					RTW_INFO("Got P2P Capability Attr, grp_cap=0x%x, is_GO\n", grp_cap);
+			}
+
+
+			if (is_GO == _FALSE) {
+				if (pmlmepriv->p2p_probe_resp_ie) {
+					u32 free_len = pmlmepriv->p2p_probe_resp_ie_len;
+					pmlmepriv->p2p_probe_resp_ie_len = 0;
+					rtw_mfree(pmlmepriv->p2p_probe_resp_ie, free_len);
+					pmlmepriv->p2p_probe_resp_ie = NULL;
+				}
+
+				pmlmepriv->p2p_probe_resp_ie = rtw_malloc(p2p_ielen);
+				if (pmlmepriv->p2p_probe_resp_ie == NULL) {
+					RTW_INFO("%s()-%d: rtw_malloc() ERROR!\n", __FUNCTION__, __LINE__);
+					return -EINVAL;
+
+				}
+				_rtw_memcpy(pmlmepriv->p2p_probe_resp_ie, p2p_ie, p2p_ielen);
+				pmlmepriv->p2p_probe_resp_ie_len = p2p_ielen;
+			} else {
+				if (pmlmepriv->p2p_go_probe_resp_ie) {
+					u32 free_len = pmlmepriv->p2p_go_probe_resp_ie_len;
+					pmlmepriv->p2p_go_probe_resp_ie_len = 0;
+					rtw_mfree(pmlmepriv->p2p_go_probe_resp_ie, free_len);
+					pmlmepriv->p2p_go_probe_resp_ie = NULL;
+				}
+
+				pmlmepriv->p2p_go_probe_resp_ie = rtw_malloc(p2p_ielen);
+				if (pmlmepriv->p2p_go_probe_resp_ie == NULL) {
+					RTW_INFO("%s()-%d: rtw_malloc() ERROR!\n", __FUNCTION__, __LINE__);
+					return -EINVAL;
+
+				}
+				_rtw_memcpy(pmlmepriv->p2p_go_probe_resp_ie, p2p_ie, p2p_ielen);
+				pmlmepriv->p2p_go_probe_resp_ie_len = p2p_ielen;
+			}
+
+		}
+		#endif /* CONFIG_P2P */
+
+
+		#ifdef CONFIG_WFD
+		wfd_ie = rtw_get_wfd_ie(buf, len, NULL, &wfd_ielen);
+		if (wfd_ie) {
+			#ifdef CONFIG_DEBUG_CFG80211
+			RTW_INFO("probe_resp_wfd_ielen=%d\n", wfd_ielen);
+			#endif
+
+			if (rtw_mlme_update_wfd_ie_data(pmlmepriv, MLME_PROBE_RESP_IE, wfd_ie, wfd_ielen) != _SUCCESS)
+				return -EINVAL;
+		}
+		#endif /* CONFIG_WFD */
+
+	}
+
+	return ret;
+
+}
+
+static int rtw_cfg80211_set_assoc_resp_wpsp2pie(struct net_device *net, char *buf, int len)
+{
+	int ret = 0;
+	_adapter *padapter = (_adapter *)rtw_netdev_priv(net);
+	struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
+	u8 *ie;
+	u32 ie_len;
+
+	RTW_INFO("%s, ielen=%d\n", __func__, len);
+
+	if (len <= 0)
+		goto exit;
+
+	ie = rtw_get_wps_ie(buf, len, NULL, &ie_len);
+	if (ie && ie_len) {
+		if (pmlmepriv->wps_assoc_resp_ie) {
+			u32 free_len = pmlmepriv->wps_assoc_resp_ie_len;
+
+			pmlmepriv->wps_assoc_resp_ie_len = 0;
+			rtw_mfree(pmlmepriv->wps_assoc_resp_ie, free_len);
+			pmlmepriv->wps_assoc_resp_ie = NULL;
+		}
+
+		pmlmepriv->wps_assoc_resp_ie = rtw_malloc(ie_len);
+		if (pmlmepriv->wps_assoc_resp_ie == NULL) {
+			RTW_INFO("%s()-%d: rtw_malloc() ERROR!\n", __FUNCTION__, __LINE__);
+			return -EINVAL;
+		}
+		_rtw_memcpy(pmlmepriv->wps_assoc_resp_ie, ie, ie_len);
+		pmlmepriv->wps_assoc_resp_ie_len = ie_len;
+	}
+
+	ie = rtw_get_p2p_ie(buf, len, NULL, &ie_len);
+	if (ie && ie_len) {
+		if (pmlmepriv->p2p_assoc_resp_ie) {
+			u32 free_len = pmlmepriv->p2p_assoc_resp_ie_len;
+
+			pmlmepriv->p2p_assoc_resp_ie_len = 0;
+			rtw_mfree(pmlmepriv->p2p_assoc_resp_ie, free_len);
+			pmlmepriv->p2p_assoc_resp_ie = NULL;
+		}
+
+		pmlmepriv->p2p_assoc_resp_ie = rtw_malloc(ie_len);
+		if (pmlmepriv->p2p_assoc_resp_ie == NULL) {
+			RTW_INFO("%s()-%d: rtw_malloc() ERROR!\n", __FUNCTION__, __LINE__);
+			return -EINVAL;
+		}
+		_rtw_memcpy(pmlmepriv->p2p_assoc_resp_ie, ie, ie_len);
+		pmlmepriv->p2p_assoc_resp_ie_len = ie_len;
+	}
+
+#ifdef CONFIG_WFD
+	ie = rtw_get_wfd_ie(buf, len, NULL, &ie_len);
+	if (rtw_mlme_update_wfd_ie_data(pmlmepriv, MLME_ASSOC_RESP_IE, ie, ie_len) != _SUCCESS)
+		return -EINVAL;
+#endif
+
+exit:
+	return ret;
+}
+
+int rtw_cfg80211_set_mgnt_wpsp2pie(struct net_device *net, char *buf, int len,
+	int type)
+{
+	int ret = 0;
+	uint wps_ielen = 0;
+	u32	p2p_ielen = 0;
+
+#ifdef CONFIG_DEBUG_CFG80211
+	RTW_INFO("%s, ielen=%d\n", __func__, len);
+#endif
+
+	if ((rtw_get_wps_ie(buf, len, NULL, &wps_ielen) && (wps_ielen > 0))
+		#ifdef CONFIG_P2P
+		|| (rtw_get_p2p_ie(buf, len, NULL, &p2p_ielen) && (p2p_ielen > 0))
+		#endif
+	) {
+		if (net != NULL) {
+			switch (type) {
+			case 0x1: /* BEACON */
+				ret = rtw_cfg80211_set_beacon_wpsp2pie(net, buf, len);
+				break;
+			case 0x2: /* PROBE_RESP */
+				ret = rtw_cfg80211_set_probe_resp_wpsp2pie(net, buf, len);
+				#ifdef CONFIG_P2P
+				if (ret == 0)
+					adapter_wdev_data((_adapter *)rtw_netdev_priv(net))->probe_resp_ie_update_time = rtw_get_current_time();
+				#endif
+				break;
+			case 0x4: /* ASSOC_RESP */
+				ret = rtw_cfg80211_set_assoc_resp_wpsp2pie(net, buf, len);
+				break;
+			}
+		}
+	}
+
+	return ret;
+
+}
+
+#ifdef CONFIG_80211N_HT
+static void rtw_cfg80211_init_ht_capab_ex(_adapter *padapter
+	, struct ieee80211_sta_ht_cap *ht_cap, BAND_TYPE band, u8 rf_type)
+{
+	struct registry_priv *pregistrypriv = &padapter->registrypriv;
+	struct mlme_priv	*pmlmepriv = &padapter->mlmepriv;
+	struct ht_priv		*phtpriv = &pmlmepriv->htpriv;
+	u8 stbc_rx_enable = _FALSE;
+
+	rtw_ht_use_default_setting(padapter);
+
+	/* RX LDPC */
+	if (TEST_FLAG(phtpriv->ldpc_cap, LDPC_HT_ENABLE_RX))
+		ht_cap->cap |= IEEE80211_HT_CAP_LDPC_CODING;
+
+	/* TX STBC */
+	if (TEST_FLAG(phtpriv->stbc_cap, STBC_HT_ENABLE_TX))
+		ht_cap->cap |= IEEE80211_HT_CAP_TX_STBC;
+
+	/* RX STBC */
+	if (TEST_FLAG(phtpriv->stbc_cap, STBC_HT_ENABLE_RX)) {
+		/*rtw_rx_stbc 0: disable, bit(0):enable 2.4g, bit(1):enable 5g*/
+		if (band == BAND_ON_2_4G)
+			stbc_rx_enable = (pregistrypriv->rx_stbc & BIT(0)) ? _TRUE : _FALSE;
+		if (band == BAND_ON_5G)
+			stbc_rx_enable = (pregistrypriv->rx_stbc & BIT(1)) ? _TRUE : _FALSE;
+
+		if (stbc_rx_enable) {
+			switch (rf_type) {
+			case RF_1T1R:
+				ht_cap->cap |= IEEE80211_HT_CAP_RX_STBC_1R;/*RX STBC One spatial stream*/
+				break;
+
+			case RF_2T2R:
+			case RF_1T2R:
+				ht_cap->cap |= IEEE80211_HT_CAP_RX_STBC_1R;/* Only one spatial-stream STBC RX is supported */
+				break;
+			case RF_3T3R:
+			case RF_3T4R:
+			case RF_4T4R:
+				ht_cap->cap |= IEEE80211_HT_CAP_RX_STBC_1R;/* Only one spatial-stream STBC RX is supported */
+				break;
+			default:
+				RTW_INFO("[warning] rf_type %d is not expected\n", rf_type);
+				break;
+			}
+		}
+	}
+}
+
+static void rtw_cfg80211_init_ht_capab(_adapter *padapter
+	, struct ieee80211_sta_ht_cap *ht_cap, BAND_TYPE band, u8 rf_type)
+{
+	struct registry_priv *regsty = &padapter->registrypriv;
+	struct hal_spec_t *hal_spec = GET_HAL_SPEC(padapter);
+	u8 rx_nss = 0;
+
+	if (!regsty->ht_enable || !is_supported_ht(regsty->wireless_mode))
+		return;
+
+	ht_cap->ht_supported = 1;
+
+	ht_cap->cap = IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
+				IEEE80211_HT_CAP_SGI_40 | IEEE80211_HT_CAP_SGI_20 |
+				IEEE80211_HT_CAP_DSSSCCK40 | IEEE80211_HT_CAP_MAX_AMSDU;
+	rtw_cfg80211_init_ht_capab_ex(padapter, ht_cap, band, rf_type);
+
+	/*
+	 *Maximum length of AMPDU that the STA can receive.
+	 *Length = 2 ^ (13 + max_ampdu_length_exp) - 1 (octets)
+	 */
+	ht_cap->ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K;
+
+	/*Minimum MPDU start spacing , */
+	ht_cap->ampdu_density = IEEE80211_HT_MPDU_DENSITY_16;
+
+	ht_cap->mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED;
+
+	rx_nss = rtw_min(rf_type_to_rf_rx_cnt(rf_type), hal_spec->rx_nss_num);
+	switch (rx_nss) {
+	case 1:
+		ht_cap->mcs.rx_mask[0] = 0xFF;
+		break;
+	case 2:
+		ht_cap->mcs.rx_mask[0] = 0xFF;
+		ht_cap->mcs.rx_mask[1] = 0xFF;
+		break;
+	case 3:
+		ht_cap->mcs.rx_mask[0] = 0xFF;
+		ht_cap->mcs.rx_mask[1] = 0xFF;
+		ht_cap->mcs.rx_mask[2] = 0xFF;
+		break;
+	case 4:
+		ht_cap->mcs.rx_mask[0] = 0xFF;
+		ht_cap->mcs.rx_mask[1] = 0xFF;
+		ht_cap->mcs.rx_mask[2] = 0xFF;
+		ht_cap->mcs.rx_mask[3] = 0xFF;
+		break;
+	default:
+		rtw_warn_on(1);
+		RTW_INFO("%s, error rf_type=%d\n", __func__, rf_type);
+	};
+
+	ht_cap->mcs.rx_highest = cpu_to_le16(
+		rtw_mcs_rate(rf_type
+			, hal_is_bw_support(padapter, CHANNEL_WIDTH_40)
+			, hal_is_bw_support(padapter, CHANNEL_WIDTH_40) ? ht_cap->cap & IEEE80211_HT_CAP_SGI_40 : ht_cap->cap & IEEE80211_HT_CAP_SGI_20
+			, ht_cap->mcs.rx_mask) / 10);
+}
+#endif /* CONFIG_80211N_HT */
+
+#if defined(CONFIG_80211AC_VHT) && (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 6, 0))
+static void rtw_cfg80211_init_vht_capab(_adapter *padapter
+	, struct ieee80211_sta_vht_cap *sta_vht_cap, BAND_TYPE band, u8 rf_type)
+{
+	struct registry_priv *regsty = &padapter->registrypriv;
+	u8 vht_cap_ie[2 + 12] = {0};
+
+	if (!REGSTY_IS_11AC_ENABLE(regsty) || !is_supported_vht(regsty->wireless_mode))
+		return;
+
+	rtw_vht_use_default_setting(padapter);
+	rtw_build_vht_cap_ie(padapter, vht_cap_ie);
+
+	sta_vht_cap->vht_supported = 1;
+
+	_rtw_memcpy(&sta_vht_cap->cap, vht_cap_ie + 2, 4);
+	_rtw_memcpy(&sta_vht_cap->vht_mcs, vht_cap_ie + 2 + 4, 8);
+}
+#endif /* defined(CONFIG_80211AC_VHT) && (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 6, 0)) */
+
+void rtw_cfg80211_init_wdev_data(_adapter *padapter)
+{
+#ifdef CONFIG_CONCURRENT_MODE
+	struct rtw_wdev_priv *pwdev_priv = adapter_wdev_data(padapter);
+
+	ATOMIC_SET(&pwdev_priv->switch_ch_to, 1);
+#endif
+}
+
+void rtw_cfg80211_init_wiphy(_adapter *padapter)
+{
+	u8 rf_type;
+	struct ieee80211_supported_band *band;
+	struct wireless_dev *pwdev = padapter->rtw_wdev;
+	struct wiphy *wiphy = pwdev->wiphy;
+
+	rtw_hal_get_hwreg(padapter, HW_VAR_RF_TYPE, (u8 *)(&rf_type));
+
+	RTW_INFO("%s:rf_type=%d\n", __func__, rf_type);
+
+	if (IsSupported24G(padapter->registrypriv.wireless_mode)) {
+		band = wiphy->bands[NL80211_BAND_2GHZ];
+		if (band) {
+			#if defined(CONFIG_80211N_HT)
+			rtw_cfg80211_init_ht_capab(padapter, &band->ht_cap, BAND_ON_2_4G, rf_type);
+			#endif
+		}
+	}
+#ifdef CONFIG_IEEE80211_BAND_5GHZ
+	if (is_supported_5g(padapter->registrypriv.wireless_mode)) {
+		band = wiphy->bands[NL80211_BAND_5GHZ];
+		if (band) {
+			#if defined(CONFIG_80211N_HT)
+			rtw_cfg80211_init_ht_capab(padapter, &band->ht_cap, BAND_ON_5G, rf_type);
+			#endif
+			#if defined(CONFIG_80211AC_VHT) && (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 6, 0))
+			rtw_cfg80211_init_vht_capab(padapter, &band->vht_cap, BAND_ON_5G, rf_type);
+			#endif
+		}
+	}
+#endif
+
+	/* copy mac_addr to wiphy */
+	_rtw_memcpy(wiphy->perm_addr, adapter_mac_addr(padapter), ETH_ALEN);
+
+}
+
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 0, 0))
+struct ieee80211_iface_limit rtw_limits[] = {
+	{
+		.max = 2,
+		.types = BIT(NL80211_IFTYPE_STATION)
+			#if defined(CONFIG_P2P) && ((LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) || defined(COMPAT_KERNEL_RELEASE))
+			| BIT(NL80211_IFTYPE_P2P_CLIENT)
+			#endif
+	},
+	#ifdef CONFIG_AP_MODE
+	{
+		.max = 1,
+		.types = BIT(NL80211_IFTYPE_AP)
+			#if defined(CONFIG_P2P) && ((LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) || defined(COMPAT_KERNEL_RELEASE))
+			| BIT(NL80211_IFTYPE_P2P_GO)
+			#endif
+	},
+	#endif
+	#if defined(RTW_DEDICATED_P2P_DEVICE)
+	{
+		.max = 1,
+		.types = BIT(NL80211_IFTYPE_P2P_DEVICE)
+	},
+	#endif
+	#if defined(CONFIG_RTW_MESH)
+	{
+		.max = 1,
+		.types = BIT(NL80211_IFTYPE_MESH_POINT)
+	},
+	#endif
+};
+
+struct ieee80211_iface_combination rtw_combinations[] = {
+	{
+		.limits = rtw_limits,
+		.n_limits = ARRAY_SIZE(rtw_limits),
+		#if defined(RTW_DEDICATED_P2P_DEVICE)
+		.max_interfaces = 3,
+		#else
+		.max_interfaces = 2,
+		#endif
+		.num_different_channels = 1,
+	},
+};
+#endif /* (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 0, 0)) */
+
+static void rtw_cfg80211_preinit_wiphy(_adapter *adapter, struct wiphy *wiphy)
+{
+	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
+	struct registry_priv *regsty = dvobj_to_regsty(dvobj);
+
+	wiphy->signal_type = CFG80211_SIGNAL_TYPE_MBM;
+
+	wiphy->max_scan_ssids = RTW_SSID_SCAN_AMOUNT;
+	wiphy->max_scan_ie_len = RTW_SCAN_IE_LEN_MAX;
+	wiphy->max_num_pmkids = RTW_MAX_NUM_PMKIDS;
+
+#if CONFIG_RTW_MACADDR_ACL && (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 9, 0))
+	wiphy->max_acl_mac_addrs = NUM_ACL;
+#endif
+
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 38)) || defined(COMPAT_KERNEL_RELEASE)
+	wiphy->max_remain_on_channel_duration = RTW_MAX_REMAIN_ON_CHANNEL_DURATION;
+#endif
+
+	wiphy->interface_modes =	BIT(NL80211_IFTYPE_STATION)
+								| BIT(NL80211_IFTYPE_ADHOC)
+#ifdef CONFIG_AP_MODE
+								| BIT(NL80211_IFTYPE_AP)
+								#ifdef CONFIG_WIFI_MONITOR
+								| BIT(NL80211_IFTYPE_MONITOR)
+								#endif
+#endif
+#if defined(CONFIG_P2P) && ((LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) || defined(COMPAT_KERNEL_RELEASE))
+								| BIT(NL80211_IFTYPE_P2P_CLIENT)
+								| BIT(NL80211_IFTYPE_P2P_GO)
+								#if defined(RTW_DEDICATED_P2P_DEVICE)
+								| BIT(NL80211_IFTYPE_P2P_DEVICE)
+								#endif
+#endif
+#ifdef CONFIG_RTW_MESH
+								| BIT(NL80211_IFTYPE_MESH_POINT) /* 2.6.26 */
+#endif
+								;
+
+#if defined(CONFIG_ANDROID) && !defined(RTW_SINGLE_WIPHY)
+        if (is_primary_adapter(adapter)) {
+                wiphy->interface_modes &= ~(BIT(NL80211_IFTYPE_P2P_GO) | BIT(NL80211_IFTYPE_P2P_CLIENT));
+                RTW_INFO("%s primary- don't set p2p capability\n", __func__);
+        }
+#endif
+
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) || defined(COMPAT_KERNEL_RELEASE)
+#ifdef CONFIG_AP_MODE
+	wiphy->mgmt_stypes = rtw_cfg80211_default_mgmt_stypes;
+#endif /* CONFIG_AP_MODE */
+#endif
+
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 0, 0))
+	#ifdef CONFIG_WIFI_MONITOR
+	wiphy->software_iftypes |= BIT(NL80211_IFTYPE_MONITOR);
+	#endif
+#endif
+
+#if defined(RTW_SINGLE_WIPHY) && (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 0, 0))
+	wiphy->iface_combinations = rtw_combinations;
+	wiphy->n_iface_combinations = ARRAY_SIZE(rtw_combinations);
+#endif
+
+	wiphy->cipher_suites = rtw_cipher_suites;
+	wiphy->n_cipher_suites = ARRAY_SIZE(rtw_cipher_suites);
+
+	if (IsSupported24G(adapter->registrypriv.wireless_mode))
+		wiphy->bands[NL80211_BAND_2GHZ] = rtw_spt_band_alloc(BAND_ON_2_4G);
+
+#ifdef CONFIG_IEEE80211_BAND_5GHZ
+	if (is_supported_5g(adapter->registrypriv.wireless_mode))
+		wiphy->bands[NL80211_BAND_5GHZ] = rtw_spt_band_alloc(BAND_ON_5G);
+#endif
+
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 38) && LINUX_VERSION_CODE < KERNEL_VERSION(3, 0, 0))
+	wiphy->flags |= WIPHY_FLAG_SUPPORTS_SEPARATE_DEFAULT_KEYS;
+#endif
+
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 3, 0))
+	wiphy->flags |= WIPHY_FLAG_HAS_REMAIN_ON_CHANNEL;
+	wiphy->flags |= WIPHY_FLAG_HAVE_AP_SME;
+	/* remove WIPHY_FLAG_OFFCHAN_TX, because we not support this feature */
+	/* wiphy->flags |= WIPHY_FLAG_OFFCHAN_TX | WIPHY_FLAG_HAVE_AP_SME; */
+#endif
+
+#if defined(CONFIG_PM) && (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 0, 0) && \
+			   LINUX_VERSION_CODE < KERNEL_VERSION(4, 12, 0))
+	wiphy->flags |= WIPHY_FLAG_SUPPORTS_SCHED_SCAN;
+#ifdef CONFIG_PNO_SUPPORT
+	wiphy->max_sched_scan_ssids = MAX_PNO_LIST_COUNT;
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(3, 2, 0)
+	wiphy->max_match_sets = MAX_PNO_LIST_COUNT;
+#endif
+#endif
+#endif
+
+#if defined(CONFIG_PM) && (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 0, 0))
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 11, 0))
+	wiphy->wowlan = wowlan_stub;
+#else
+	wiphy->wowlan = &wowlan_stub;
+#endif
+#endif
+
+#if defined(CONFIG_TDLS) && (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 2, 0))
+	wiphy->flags |= WIPHY_FLAG_SUPPORTS_TDLS;
+#ifndef CONFIG_TDLS_DRIVER_SETUP
+	wiphy->flags |= WIPHY_FLAG_TDLS_EXTERNAL_SETUP;	/* Driver handles key exchange */
+	wiphy->flags |= NL80211_ATTR_HT_CAPABILITY;
+#endif /* CONFIG_TDLS_DRIVER_SETUP */
+#endif /* CONFIG_TDLS */
+
+	if (regsty->power_mgnt != PS_MODE_ACTIVE)
+		wiphy->flags |= WIPHY_FLAG_PS_ON_BY_DEFAULT;
+	else
+		wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
+
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 2, 0))
+	/* wiphy->flags |= WIPHY_FLAG_SUPPORTS_FW_ROAM; */
+#endif
+
+#ifdef CONFIG_RTW_MESH
+	wiphy->flags |= 0
+		#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37))
+		| WIPHY_FLAG_IBSS_RSN
+		#endif
+		#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 0, 0))
+		| WIPHY_FLAG_MESH_AUTH
+		#endif
+		;
+
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 3, 0))
+	wiphy->features |= 0
+		#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 10, 0))
+		| NL80211_FEATURE_USERSPACE_MPM
+		#endif
+		;
+#endif /* (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 3, 0)) */
+#endif /* CONFIG_RTW_MESH */
+}
+
+#ifdef CONFIG_RFKILL_POLL
+void rtw_cfg80211_init_rfkill(struct wiphy *wiphy)
+{
+	wiphy_rfkill_set_hw_state(wiphy, 0);
+	wiphy_rfkill_start_polling(wiphy);
+}
+
+void rtw_cfg80211_deinit_rfkill(struct wiphy *wiphy)
+{
+	wiphy_rfkill_stop_polling(wiphy);
+}
+
+static void cfg80211_rtw_rfkill_poll(struct wiphy *wiphy)
+{
+	_adapter *padapter = NULL;
+	bool blocked = _FALSE;
+	u8 valid = 0;
+
+	padapter = wiphy_to_adapter(wiphy);
+
+	if (adapter_to_dvobj(padapter)->processing_dev_remove == _TRUE) {
+		/*RTW_INFO("cfg80211_rtw_rfkill_poll: device is removed!\n");*/
+		return;
+	}
+
+	blocked = rtw_hal_rfkill_poll(padapter, &valid);
+	/*RTW_INFO("cfg80211_rtw_rfkill_poll: valid=%d, blocked=%d\n",
+			valid, blocked);*/
+
+	if (valid)
+		wiphy_rfkill_set_hw_state(wiphy, blocked);
+}
+#endif
+
+#if defined(CONFIG_RTW_HOSTAPD_ACS) && (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 33))
+
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) && (LINUX_VERSION_CODE < KERNEL_VERSION(4, 0, 0))
+#define SURVEY_INFO_TIME			SURVEY_INFO_CHANNEL_TIME
+#define SURVEY_INFO_TIME_BUSY		SURVEY_INFO_CHANNEL_TIME_BUSY
+#define SURVEY_INFO_TIME_EXT_BUSY	SURVEY_INFO_CHANNEL_TIME_EXT_BUSY
+#define SURVEY_INFO_TIME_RX			SURVEY_INFO_CHANNEL_TIME_RX
+#define SURVEY_INFO_TIME_TX			SURVEY_INFO_CHANNEL_TIME_TX
+#endif
+
+#ifdef CONFIG_FIND_BEST_CHANNEL
+static void rtw_cfg80211_set_survey_info_with_find_best_channel(struct wiphy *wiphy
+	, struct net_device *netdev, int idx, struct survey_info *info)
+{
+	_adapter *adapter = (_adapter *)rtw_netdev_priv(netdev);
+	struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter);
+	RT_CHANNEL_INFO *ch_set = rfctl->channel_set;
+	u8 ch_num = rfctl->max_chan_nums;
+	u32 total_rx_cnt = 0;
+	int i;
+
+	s8 noise = -50;		/*channel noise in dBm. This and all following fields are optional */
+	u64 time = 100;		/*amount of time in ms the radio was turn on (on the channel)*/
+	u64 time_busy = 0;	/*amount of time the primary channel was sensed busy*/
+
+	info->filled  = SURVEY_INFO_NOISE_DBM
+		#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37))
+		| SURVEY_INFO_TIME | SURVEY_INFO_TIME_BUSY
+		#endif
+		;
+
+	for (i = 0; i < ch_num; i++)
+		total_rx_cnt += ch_set[i].rx_count;
+
+	time_busy = ch_set[idx].rx_count * time / total_rx_cnt;
+	noise += ch_set[idx].rx_count * 50 / total_rx_cnt;
+
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37))
+	#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 0, 0))
+	info->channel_time = time;
+	info->channel_time_busy = time_busy;
+	#else
+	info->time = time;
+	info->time_busy = time_busy;
+	#endif
+#endif
+	info->noise = noise;
+
+	/* reset if final channel is got */
+	if (idx == ch_num - 1) {
+		for (i = 0; i < ch_num; i++)
+			ch_set[i].rx_count = 0;
+	}
+}
+#endif /* CONFIG_FIND_BEST_CHANNEL */
+
+#if defined(CONFIG_RTW_ACS) && defined(CONFIG_BACKGROUND_NOISE_MONITOR)
+static void rtw_cfg80211_set_survey_info_with_clm(PADAPTER padapter, int idx, struct survey_info *pinfo)
+{
+	s8 noise = -50;			/*channel noise in dBm. This and all following fields are optional */
+	u64 time = SURVEY_TO;	/*amount of time in ms the radio was turn on (on the channel)*/
+	u64 time_busy = 0;		/*amount of time the primary channel was sensed busy*/
+	u8 chan = (u8)idx;
+
+	if ((idx < 0) || (pinfo == NULL))
+		return;
+
+	pinfo->filled  = SURVEY_INFO_NOISE_DBM
+		#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37))
+		| SURVEY_INFO_TIME | SURVEY_INFO_TIME_BUSY
+		#endif
+		;
+
+	time_busy = rtw_acs_get_clm_ratio_by_ch_idx(padapter, chan);
+	noise = rtw_noise_query_by_chan_idx(padapter, chan);
+	/* RTW_INFO("%s: ch-idx:%d time=%llu(ms), time_busy=%llu(ms), noise=%d(dbm)\n", __func__, idx, time, time_busy, noise); */
+
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37))
+	#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 0, 0))
+	pinfo->channel_time = time;
+	pinfo->channel_time_busy = time_busy;
+	#else
+	pinfo->time = time;
+	pinfo->time_busy = time_busy;
+	#endif
+#endif
+	pinfo->noise = noise;
+}
+#endif
+
+int rtw_hostapd_acs_dump_survey(struct wiphy *wiphy, struct net_device *netdev, int idx, struct survey_info *info)
+{
+	PADAPTER padapter = (_adapter *)rtw_netdev_priv(netdev);
+	struct rf_ctl_t *rfctl = adapter_to_rfctl(padapter);
+	RT_CHANNEL_INFO *pch_set = rfctl->channel_set;
+	u8 max_chan_nums = rfctl->max_chan_nums;
+	u32 freq = 0;
+	u8 ret = 0;
+	u16 channel = 0;
+
+	if (!netdev || !info) {
+		RTW_INFO("%s: invial parameters.\n", __func__);
+		return -EINVAL;
+	}
+
+	_rtw_memset(info, 0, sizeof(struct survey_info));
+	if (padapter->bup == _FALSE) {
+		RTW_INFO("%s: net device is down.\n", __func__);
+		return -EIO;
+	}
+
+	if (idx >= max_chan_nums)
+		return -ENOENT;
+
+	channel = pch_set[idx].ChannelNum;
+	freq = rtw_ch2freq(channel);
+	info->channel = ieee80211_get_channel(wiphy, freq);
+	/* RTW_INFO("%s: channel %d, freq %d\n", __func__, channel, freq); */
+
+	if (!info->channel)
+		return -EINVAL;
+
+	if (info->channel->flags == IEEE80211_CHAN_DISABLED)
+		return ret;
+
+#ifdef CONFIG_FIND_BEST_CHANNEL
+	rtw_cfg80211_set_survey_info_with_find_best_channel(wiphy, netdev, idx, info);
+#elif defined(CONFIG_RTW_ACS) && defined(CONFIG_BACKGROUND_NOISE_MONITOR)
+	rtw_cfg80211_set_survey_info_with_clm(padapter, idx, info);
+#else
+	RTW_ERR("%s: unknown acs operation!\n", __func__); 
+#endif
+
+	return ret;
+}
+#endif /* defined(CONFIG_RTW_HOSTAPD_ACS) && (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 33)) */
+
+static struct cfg80211_ops rtw_cfg80211_ops = {
+	.change_virtual_intf = cfg80211_rtw_change_iface,
+	.add_key = cfg80211_rtw_add_key,
+	.get_key = cfg80211_rtw_get_key,
+	.del_key = cfg80211_rtw_del_key,
+	.set_default_key = cfg80211_rtw_set_default_key,
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 30))
+	.set_default_mgmt_key = cfg80211_rtw_set_default_mgmt_key,
+#endif
+#if defined(CONFIG_GTK_OL) && (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 1, 0))
+	.set_rekey_data = cfg80211_rtw_set_rekey_data,
+#endif /*CONFIG_GTK_OL*/
+	.get_station = cfg80211_rtw_get_station,
+	.scan = cfg80211_rtw_scan,
+	.set_wiphy_params = cfg80211_rtw_set_wiphy_params,
+	.connect = cfg80211_rtw_connect,
+	.disconnect = cfg80211_rtw_disconnect,
+	.join_ibss = cfg80211_rtw_join_ibss,
+	.leave_ibss = cfg80211_rtw_leave_ibss,
+	.set_tx_power = cfg80211_rtw_set_txpower,
+	.get_tx_power = cfg80211_rtw_get_txpower,
+	.set_power_mgmt = cfg80211_rtw_set_power_mgmt,
+	.set_pmksa = cfg80211_rtw_set_pmksa,
+	.del_pmksa = cfg80211_rtw_del_pmksa,
+	.flush_pmksa = cfg80211_rtw_flush_pmksa,
+
+#ifdef CONFIG_AP_MODE
+	.add_virtual_intf = cfg80211_rtw_add_virtual_intf,
+	.del_virtual_intf = cfg80211_rtw_del_virtual_intf,
+
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 4, 0)) && !defined(COMPAT_KERNEL_RELEASE)
+	.add_beacon = cfg80211_rtw_add_beacon,
+	.set_beacon = cfg80211_rtw_set_beacon,
+	.del_beacon = cfg80211_rtw_del_beacon,
+#else
+	.start_ap = cfg80211_rtw_start_ap,
+	.change_beacon = cfg80211_rtw_change_beacon,
+	.stop_ap = cfg80211_rtw_stop_ap,
+#endif
+
+#if CONFIG_RTW_MACADDR_ACL && (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 9, 0))
+	.set_mac_acl = cfg80211_rtw_set_mac_acl,
+#endif
+
+	.add_station = cfg80211_rtw_add_station,
+	.del_station = cfg80211_rtw_del_station,
+	.change_station = cfg80211_rtw_change_station,
+	.dump_station = cfg80211_rtw_dump_station,
+	.change_bss = cfg80211_rtw_change_bss,
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 29))
+	.set_txq_params = cfg80211_rtw_set_txq_params,
+#endif
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 6, 0))
+	.set_channel = cfg80211_rtw_set_channel,
+#endif
+	/* .auth = cfg80211_rtw_auth, */
+	/* .assoc = cfg80211_rtw_assoc,	 */
+#endif /* CONFIG_AP_MODE */
+
+#if defined(CONFIG_RTW_MESH) && (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 38))
+	.get_mesh_config = cfg80211_rtw_get_mesh_config,
+	.update_mesh_config = cfg80211_rtw_update_mesh_config,
+	.join_mesh = cfg80211_rtw_join_mesh,
+	.leave_mesh = cfg80211_rtw_leave_mesh,
+	.add_mpath = cfg80211_rtw_add_mpath,
+	.del_mpath = cfg80211_rtw_del_mpath,
+	.change_mpath = cfg80211_rtw_change_mpath,
+	.get_mpath = cfg80211_rtw_get_mpath,
+	.dump_mpath = cfg80211_rtw_dump_mpath,
+	#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 19, 0))
+	.get_mpp = cfg80211_rtw_get_mpp,
+	.dump_mpp = cfg80211_rtw_dump_mpp,
+	#endif
+#endif
+
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 6, 0))
+	.set_monitor_channel = cfg80211_rtw_set_monitor_channel,
+#endif
+
+#ifdef CONFIG_P2P
+	.remain_on_channel = cfg80211_rtw_remain_on_channel,
+	.cancel_remain_on_channel = cfg80211_rtw_cancel_remain_on_channel,
+	#if defined(RTW_DEDICATED_P2P_DEVICE)
+	.start_p2p_device = cfg80211_rtw_start_p2p_device,
+	.stop_p2p_device = cfg80211_rtw_stop_p2p_device,
+	#endif
+#endif /* CONFIG_P2P */
+
+#ifdef CONFIG_RTW_80211R
+	.update_ft_ies = cfg80211_rtw_update_ft_ies,
+#endif
+
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) || defined(COMPAT_KERNEL_RELEASE)
+	.mgmt_tx = cfg80211_rtw_mgmt_tx,
+	.mgmt_frame_register = cfg80211_rtw_mgmt_frame_register,
+#elif (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 34) && LINUX_VERSION_CODE <= KERNEL_VERSION(2, 6, 35))
+	.action = cfg80211_rtw_mgmt_tx,
+#endif
+
+#if defined(CONFIG_TDLS) && (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 2, 0))
+	.tdls_mgmt = cfg80211_rtw_tdls_mgmt,
+	.tdls_oper = cfg80211_rtw_tdls_oper,
+#endif /* CONFIG_TDLS */
+
+#if defined(CONFIG_PNO_SUPPORT) && (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 0, 0))
+	.sched_scan_start = cfg80211_rtw_sched_scan_start,
+	.sched_scan_stop = cfg80211_rtw_sched_scan_stop,
+	.suspend = cfg80211_rtw_suspend,
+	.resume = cfg80211_rtw_resume,
+#endif /* CONFIG_PNO_SUPPORT */
+#ifdef CONFIG_RFKILL_POLL
+	.rfkill_poll = cfg80211_rtw_rfkill_poll,
+#endif
+#if defined(CONFIG_RTW_HOSTAPD_ACS) && (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 33))
+	.dump_survey = rtw_hostapd_acs_dump_survey,
+#endif
+};
+
+struct wiphy *rtw_wiphy_alloc(_adapter *padapter, struct device *dev)
+{
+	struct wiphy *wiphy;
+	struct rtw_wiphy_data *wiphy_data;
+
+	/* wiphy */
+	wiphy = wiphy_new(&rtw_cfg80211_ops, sizeof(struct rtw_wiphy_data));
+	if (!wiphy) {
+		RTW_INFO("Couldn't allocate wiphy device\n");
+		goto exit;
+	}
+	set_wiphy_dev(wiphy, dev);
+
+	/* wiphy_data */
+	wiphy_data = rtw_wiphy_priv(wiphy);
+	wiphy_data->dvobj = adapter_to_dvobj(padapter);
+#ifndef RTW_SINGLE_WIPHY
+	wiphy_data->adapter = padapter;
+#endif
+
+	rtw_cfg80211_preinit_wiphy(padapter, wiphy);
+
+	RTW_INFO(FUNC_WIPHY_FMT"\n", FUNC_WIPHY_ARG(wiphy));
+
+exit:
+	return wiphy;
+}
+
+void rtw_wiphy_free(struct wiphy *wiphy)
+{
+	if (!wiphy)
+		return;
+
+	RTW_INFO(FUNC_WIPHY_FMT"\n", FUNC_WIPHY_ARG(wiphy));
+
+	if (wiphy->bands[NL80211_BAND_2GHZ]) {
+		rtw_spt_band_free(wiphy->bands[NL80211_BAND_2GHZ]);
+		wiphy->bands[NL80211_BAND_2GHZ] = NULL;
+	}
+	if (wiphy->bands[NL80211_BAND_5GHZ]) {
+		rtw_spt_band_free(wiphy->bands[NL80211_BAND_5GHZ]);
+		wiphy->bands[NL80211_BAND_5GHZ] = NULL;
+	}
+
+	wiphy_free(wiphy);
+}
+
+int rtw_wiphy_register(struct wiphy *wiphy)
+{
+	RTW_INFO(FUNC_WIPHY_FMT"\n", FUNC_WIPHY_ARG(wiphy));
+
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 14, 0)) || defined(RTW_VENDOR_EXT_SUPPORT)
+	rtw_cfgvendor_attach(wiphy);
+#endif
+
+	rtw_regd_init(wiphy);
+
+	return wiphy_register(wiphy);
+}
+
+void rtw_wiphy_unregister(struct wiphy *wiphy)
+{
+	RTW_INFO(FUNC_WIPHY_FMT"\n", FUNC_WIPHY_ARG(wiphy));
+
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 14, 0)) || defined(RTW_VENDOR_EXT_SUPPORT)
+	rtw_cfgvendor_detach(wiphy);
+#endif
+
+	#if defined(RTW_DEDICATED_P2P_DEVICE)
+	rtw_pd_iface_free(wiphy);
+	#endif
+
+	return wiphy_unregister(wiphy);
+}
+
+int rtw_wdev_alloc(_adapter *padapter, struct wiphy *wiphy)
+{
+	int ret = 0;
+	struct net_device *pnetdev = padapter->pnetdev;
+	struct wireless_dev *wdev;
+	struct rtw_wdev_priv *pwdev_priv;
+
+	RTW_INFO("%s(padapter=%p)\n", __func__, padapter);
+
+	/*  wdev */
+	wdev = (struct wireless_dev *)rtw_zmalloc(sizeof(struct wireless_dev));
+	if (!wdev) {
+		RTW_INFO("Couldn't allocate wireless device\n");
+		ret = -ENOMEM;
+		goto exit;
+	}
+	wdev->wiphy = wiphy;
+	wdev->netdev = pnetdev;
+	wdev->iftype = NL80211_IFTYPE_STATION;
+	padapter->rtw_wdev = wdev;
+	pnetdev->ieee80211_ptr = wdev;
+
+	/* init pwdev_priv */
+	pwdev_priv = adapter_wdev_data(padapter);
+	pwdev_priv->rtw_wdev = wdev;
+	pwdev_priv->pmon_ndev = NULL;
+	pwdev_priv->ifname_mon[0] = '\0';
+	pwdev_priv->padapter = padapter;
+	pwdev_priv->scan_request = NULL;
+	_rtw_spinlock_init(&pwdev_priv->scan_req_lock);
+	pwdev_priv->connect_req = NULL;
+	_rtw_spinlock_init(&pwdev_priv->connect_req_lock);
+
+	pwdev_priv->p2p_enabled = _FALSE;
+	pwdev_priv->probe_resp_ie_update_time = rtw_get_current_time();
+	pwdev_priv->provdisc_req_issued = _FALSE;
+	rtw_wdev_invit_info_init(&pwdev_priv->invit_info);
+	rtw_wdev_nego_info_init(&pwdev_priv->nego_info);
+
+	pwdev_priv->bandroid_scan = _FALSE;
+
+	if (padapter->registrypriv.power_mgnt != PS_MODE_ACTIVE)
+		pwdev_priv->power_mgmt = _TRUE;
+	else
+		pwdev_priv->power_mgmt = _FALSE;
+
+	_rtw_mutex_init(&pwdev_priv->roch_mutex);
+
+#ifdef CONFIG_CONCURRENT_MODE
+	ATOMIC_SET(&pwdev_priv->switch_ch_to, 1);
+#endif
+
+#ifdef CONFIG_RTW_CFGVEDNOR_RSSIMONITOR
+        pwdev_priv->rssi_monitor_enable = 0;
+        pwdev_priv->rssi_monitor_max = 0;
+        pwdev_priv->rssi_monitor_min = 0;
+#endif
+
+
+exit:
+	return ret;
+}
+
+void rtw_wdev_free(struct wireless_dev *wdev)
+{
+	if (!wdev)
+		return;
+
+	RTW_INFO("%s(wdev=%p)\n", __func__, wdev);
+
+	if (wdev_to_ndev(wdev)) {
+		_adapter *adapter = (_adapter *)rtw_netdev_priv(wdev_to_ndev(wdev));
+		struct rtw_wdev_priv *wdev_priv = adapter_wdev_data(adapter);
+		_irqL irqL;
+
+		_rtw_spinlock_free(&wdev_priv->scan_req_lock);
+
+		_enter_critical_bh(&wdev_priv->connect_req_lock, &irqL);
+		rtw_wdev_free_connect_req(wdev_priv);
+		_exit_critical_bh(&wdev_priv->connect_req_lock, &irqL);
+		_rtw_spinlock_free(&wdev_priv->connect_req_lock);
+
+		_rtw_mutex_free(&wdev_priv->roch_mutex);
+	}
+
+	rtw_mfree((u8 *)wdev, sizeof(struct wireless_dev));
+}
+
+void rtw_wdev_unregister(struct wireless_dev *wdev)
+{
+	struct net_device *ndev;
+	_adapter *adapter;
+	struct rtw_wdev_priv *pwdev_priv;
+
+	if (!wdev)
+		return;
+
+	RTW_INFO("%s(wdev=%p)\n", __func__, wdev);
+
+	ndev = wdev_to_ndev(wdev);
+	if (!ndev)
+		return;
+
+	adapter = (_adapter *)rtw_netdev_priv(ndev);
+	pwdev_priv = adapter_wdev_data(adapter);
+
+	rtw_cfg80211_indicate_scan_done(adapter, _TRUE);
+
+	#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 11, 0)) || defined(COMPAT_KERNEL_RELEASE)
+	if (wdev->current_bss) {
+		RTW_INFO(FUNC_ADPT_FMT" clear current_bss by cfg80211_disconnected\n", FUNC_ADPT_ARG(adapter));
+		rtw_cfg80211_indicate_disconnect(adapter, 0, 1);
+	}
+	#endif
+
+	if (pwdev_priv->pmon_ndev) {
+		RTW_INFO("%s, unregister monitor interface\n", __func__);
+		unregister_netdev(pwdev_priv->pmon_ndev);
+	}
+}
+
+int rtw_cfg80211_ndev_res_alloc(_adapter *adapter)
+{
+	int ret = _FAIL;
+
+#if !defined(RTW_SINGLE_WIPHY)
+	struct wiphy *wiphy;
+	struct device *dev = dvobj_to_dev(adapter_to_dvobj(adapter));
+
+	wiphy = rtw_wiphy_alloc(adapter, dev);
+	if (wiphy == NULL)
+		goto exit;
+
+	adapter->wiphy = wiphy;
+#endif
+
+	if (rtw_wdev_alloc(adapter, adapter_to_wiphy(adapter)) == 0)
+		ret = _SUCCESS;
+
+#if !defined(RTW_SINGLE_WIPHY)
+	if (ret != _SUCCESS) {
+		rtw_wiphy_free(wiphy);
+		adapter->wiphy = NULL;
+	}
+#endif
+
+exit:
+	return ret;
+}
+
+void rtw_cfg80211_ndev_res_free(_adapter *adapter)
+{
+	rtw_wdev_free(adapter->rtw_wdev);
+	adapter->rtw_wdev = NULL;
+#if !defined(RTW_SINGLE_WIPHY)
+	rtw_wiphy_free(adapter_to_wiphy(adapter));
+	adapter->wiphy = NULL;
+#endif
+}
+
+int rtw_cfg80211_ndev_res_register(_adapter *adapter)
+{
+	int ret = _FAIL;
+
+#if !defined(RTW_SINGLE_WIPHY)
+	if (rtw_wiphy_register(adapter_to_wiphy(adapter)) < 0) {
+		RTW_INFO("%s rtw_wiphy_register fail for if%d\n", __func__, (adapter->iface_id + 1));
+		goto exit;
+	}
+
+#ifdef CONFIG_RFKILL_POLL
+	rtw_cfg80211_init_rfkill(adapter_to_wiphy(adapter));
+#endif
+#endif
+
+	ret = _SUCCESS;
+
+exit:
+	return ret;
+}
+
+void rtw_cfg80211_ndev_res_unregister(_adapter *adapter)
+{
+	rtw_wdev_unregister(adapter->rtw_wdev);
+}
+
+int rtw_cfg80211_dev_res_alloc(struct dvobj_priv *dvobj)
+{
+	int ret = _FAIL;
+
+#if defined(RTW_SINGLE_WIPHY)
+	struct wiphy *wiphy;
+	struct device *dev = dvobj_to_dev(dvobj);
+
+	wiphy = rtw_wiphy_alloc(dvobj_get_primary_adapter(dvobj), dev);
+	if (wiphy == NULL)
+		goto exit;
+
+	dvobj->wiphy = wiphy;
+#endif
+
+	ret = _SUCCESS;
+
+exit:
+	return ret;
+}
+
+void rtw_cfg80211_dev_res_free(struct dvobj_priv *dvobj)
+{
+#if defined(RTW_SINGLE_WIPHY)
+	rtw_wiphy_free(dvobj_to_wiphy(dvobj));
+	dvobj->wiphy = NULL;
+#endif
+}
+
+int rtw_cfg80211_dev_res_register(struct dvobj_priv *dvobj)
+{
+	int ret = _FAIL;
+
+#if defined(RTW_SINGLE_WIPHY)
+	if (rtw_wiphy_register(dvobj_to_wiphy(dvobj)) != 0)
+		goto exit;
+
+#ifdef CONFIG_RFKILL_POLL
+	rtw_cfg80211_init_rfkill(dvobj_to_wiphy(dvobj));
+#endif
+#endif
+
+	ret = _SUCCESS;
+
+exit:
+	return ret;
+}
+
+void rtw_cfg80211_dev_res_unregister(struct dvobj_priv *dvobj)
+{
+#if defined(RTW_SINGLE_WIPHY)
+#ifdef CONFIG_RFKILL_POLL
+	rtw_cfg80211_deinit_rfkill(dvobj_to_wiphy(dvobj));
+#endif
+	rtw_wiphy_unregister(dvobj_to_wiphy(dvobj));
+#endif
+}
+
+#endif /* CONFIG_IOCTL_CFG80211 */
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/os_dep/linux/ioctl_cfg80211.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/os_dep/linux/ioctl_cfg80211.h
--- linux-5.6.3/3rdparty/rtl8821ce/os_dep/linux/ioctl_cfg80211.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/os_dep/linux/ioctl_cfg80211.h	2020-04-10 16:35:06.854661842 +0300
@@ -0,0 +1,409 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#ifndef __IOCTL_CFG80211_H__
+#define __IOCTL_CFG80211_H__
+
+#define RTW_CFG80211_BLOCK_DISCON_WHEN_CONNECT		BIT0
+#define RTW_CFG80211_BLOCK_DISCON_WHEN_DISCONNECT	BIT1
+
+#ifndef RTW_CFG80211_BLOCK_STA_DISCON_EVENT
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 2, 0))
+#define RTW_CFG80211_BLOCK_STA_DISCON_EVENT (RTW_CFG80211_BLOCK_DISCON_WHEN_CONNECT)
+#else
+#define RTW_CFG80211_BLOCK_STA_DISCON_EVENT (RTW_CFG80211_BLOCK_DISCON_WHEN_CONNECT | RTW_CFG80211_BLOCK_DISCON_WHEN_DISCONNECT)
+#endif
+#endif
+
+#if defined(RTW_USE_CFG80211_STA_EVENT)
+	#undef CONFIG_CFG80211_FORCE_COMPATIBLE_2_6_37_UNDER
+#endif
+
+#ifndef RTW_P2P_GROUP_INTERFACE
+	#define RTW_P2P_GROUP_INTERFACE 0
+#endif
+
+/*
+* (RTW_P2P_GROUP_INTERFACE, RTW_DEDICATED_P2P_DEVICE)
+* (0, 0): wlan0 + p2p0(PD+PG)
+* (1, 0): wlan0(with PD) + dynamic PGs
+* (1, 1): wlan0 (with dynamic PD wdev) + dynamic PGs
+*/
+
+#if RTW_P2P_GROUP_INTERFACE
+	#ifndef CONFIG_RTW_DYNAMIC_NDEV
+		#define CONFIG_RTW_DYNAMIC_NDEV
+	#endif
+	#ifndef RTW_SINGLE_WIPHY
+		#define RTW_SINGLE_WIPHY
+	#endif
+	#ifndef CONFIG_RADIO_WORK
+		#define CONFIG_RADIO_WORK
+	#endif
+	#ifndef RTW_DEDICATED_P2P_DEVICE
+		#define RTW_DEDICATED_P2P_DEVICE
+	#endif
+#endif
+
+#ifndef CONFIG_RADIO_WORK
+#define RTW_ROCH_DURATION_ENLARGE
+#define RTW_ROCH_BACK_OP
+#endif
+
+#if !defined(CONFIG_P2P) && RTW_P2P_GROUP_INTERFACE
+	#error "RTW_P2P_GROUP_INTERFACE can't be enabled when CONFIG_P2P is disabled\n"
+#endif
+
+#if !RTW_P2P_GROUP_INTERFACE && defined(RTW_DEDICATED_P2P_DEVICE)
+	#error "RTW_DEDICATED_P2P_DEVICE can't be enabled when RTW_P2P_GROUP_INTERFACE is disabled\n"
+#endif
+
+#if defined(RTW_DEDICATED_P2P_DEVICE) && (LINUX_VERSION_CODE < KERNEL_VERSION(3, 7, 0))
+	#error "RTW_DEDICATED_P2P_DEVICE can't be enabled when kernel < 3.7.0\n"
+#endif
+
+#ifdef CONFIG_RTW_MESH
+	#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 10, 0))
+		#error "CONFIG_RTW_MESH can't be enabled when kernel < 3.10.0\n"
+	#endif
+#endif
+
+struct rtw_wdev_invit_info {
+	u8 state; /* 0: req, 1:rep */
+	u8 peer_mac[ETH_ALEN];
+	u8 group_bssid[ETH_ALEN];
+	u8 active;
+	u8 token;
+	u8 flags;
+	u8 status;
+	u8 req_op_ch;
+	u8 rsp_op_ch;
+};
+
+#define rtw_wdev_invit_info_init(invit_info) \
+	do { \
+		(invit_info)->state = 0xff; \
+		_rtw_memset((invit_info)->peer_mac, 0, ETH_ALEN); \
+		_rtw_memset((invit_info)->group_bssid, 0, ETH_ALEN); \
+		(invit_info)->active = 0xff; \
+		(invit_info)->token = 0; \
+		(invit_info)->flags = 0x00; \
+		(invit_info)->status = 0xff; \
+		(invit_info)->req_op_ch = 0; \
+		(invit_info)->rsp_op_ch = 0; \
+	} while (0)
+
+struct rtw_wdev_nego_info {
+	u8 state; /* 0: req, 1:rep, 2:conf */
+	u8 iface_addr[ETH_ALEN];
+	u8 peer_mac[ETH_ALEN];
+	u8 peer_iface_addr[ETH_ALEN];
+	u8 active;
+	u8 token;
+	u8 status;
+	u8 req_intent;
+	u8 req_op_ch;
+	u8 req_listen_ch;
+	u8 rsp_intent;
+	u8 rsp_op_ch;
+	u8 conf_op_ch;
+};
+
+#define rtw_wdev_nego_info_init(nego_info) \
+	do { \
+		(nego_info)->state = 0xff; \
+		_rtw_memset((nego_info)->iface_addr, 0, ETH_ALEN); \
+		_rtw_memset((nego_info)->peer_mac, 0, ETH_ALEN); \
+		_rtw_memset((nego_info)->peer_iface_addr, 0, ETH_ALEN); \
+		(nego_info)->active = 0xff; \
+		(nego_info)->token = 0; \
+		(nego_info)->status = 0xff; \
+		(nego_info)->req_intent = 0xff; \
+		(nego_info)->req_op_ch = 0; \
+		(nego_info)->req_listen_ch = 0; \
+		(nego_info)->rsp_intent = 0xff; \
+		(nego_info)->rsp_op_ch = 0; \
+		(nego_info)->conf_op_ch = 0; \
+	} while (0)
+
+struct rtw_wdev_priv {
+	struct wireless_dev *rtw_wdev;
+
+	_adapter *padapter;
+
+	#if RTW_CFG80211_BLOCK_STA_DISCON_EVENT
+	u8 not_indic_disco;
+	#endif
+
+	struct cfg80211_scan_request *scan_request;
+	_lock scan_req_lock;
+
+	struct cfg80211_connect_params *connect_req;
+	_lock connect_req_lock;
+
+	struct net_device *pmon_ndev;/* for monitor interface */
+	char ifname_mon[IFNAMSIZ + 1]; /* interface name for monitor interface */
+
+	u8 p2p_enabled;
+	systime probe_resp_ie_update_time;
+
+	u8 provdisc_req_issued;
+
+	struct rtw_wdev_invit_info invit_info;
+	struct rtw_wdev_nego_info nego_info;
+
+	u8 bandroid_scan;
+	bool block;
+	bool block_scan;
+	bool power_mgmt;
+
+	/* report mgmt_frame registered */
+	u16 report_mgmt;
+
+	u8 is_mgmt_tx;
+	u16 mgmt_tx_cookie;
+
+	_mutex roch_mutex;
+
+#ifdef CONFIG_CONCURRENT_MODE
+	ATOMIC_T switch_ch_to;
+#endif
+
+#ifdef CONFIG_RTW_CFGVENDOR_RANDOM_MAC_OUI
+	u8 pno_mac_addr[ETH_ALEN];
+	u16 pno_scan_seq_num;
+#endif
+
+#ifdef CONFIG_RTW_CFGVEDNOR_RSSIMONITOR
+        s8 rssi_monitor_max;
+        s8 rssi_monitor_min;
+        u8 rssi_monitor_enable;
+#endif
+
+};
+
+bool rtw_cfg80211_is_connect_requested(_adapter *adapter);
+
+#if RTW_CFG80211_BLOCK_STA_DISCON_EVENT
+#define rtw_wdev_not_indic_disco(rtw_wdev_data) ((rtw_wdev_data)->not_indic_disco)
+#define rtw_wdev_set_not_indic_disco(rtw_wdev_data, val) do { (rtw_wdev_data)->not_indic_disco = (val); } while (0)
+#else
+#define rtw_wdev_not_indic_disco(rtw_wdev_data) 0
+#define rtw_wdev_set_not_indic_disco(rtw_wdev_data, val) do {} while (0)
+#endif
+
+#define rtw_wdev_free_connect_req(rtw_wdev_data) \
+	do { \
+		if ((rtw_wdev_data)->connect_req) { \
+			rtw_mfree((u8 *)(rtw_wdev_data)->connect_req, sizeof(*(rtw_wdev_data)->connect_req)); \
+			(rtw_wdev_data)->connect_req = NULL; \
+		} \
+	} while (0)
+
+#define wdev_to_ndev(w) ((w)->netdev)
+#define wdev_to_wiphy(w) ((w)->wiphy)
+#define ndev_to_wdev(n) ((n)->ieee80211_ptr)
+
+struct rtw_wiphy_data {
+	struct dvobj_priv *dvobj;
+
+#ifndef RTW_SINGLE_WIPHY
+	_adapter *adapter;
+#endif
+
+#if defined(RTW_DEDICATED_P2P_DEVICE)
+	struct wireless_dev *pd_wdev; /* P2P device wdev */
+#endif
+};
+
+#define rtw_wiphy_priv(wiphy) ((struct rtw_wiphy_data *)wiphy_priv(wiphy))
+#define wiphy_to_dvobj(wiphy) (((struct rtw_wiphy_data *)wiphy_priv(wiphy))->dvobj)
+#ifdef RTW_SINGLE_WIPHY
+#define wiphy_to_adapter(wiphy) (dvobj_get_primary_adapter(wiphy_to_dvobj(wiphy)))
+#else
+#define wiphy_to_adapter(wiphy) (((struct rtw_wiphy_data *)wiphy_priv(wiphy))->adapter)
+#endif
+
+#if defined(RTW_DEDICATED_P2P_DEVICE)
+#define wiphy_to_pd_wdev(wiphy) (rtw_wiphy_priv(wiphy)->pd_wdev)
+#else
+#define wiphy_to_pd_wdev(wiphy) NULL
+#endif
+
+#define WIPHY_FMT "%s"
+#define WIPHY_ARG(wiphy) wiphy_name(wiphy)
+#define FUNC_WIPHY_FMT "%s("WIPHY_FMT")"
+#define FUNC_WIPHY_ARG(wiphy) __func__, WIPHY_ARG(wiphy)
+
+#define SET_CFG80211_REPORT_MGMT(w, t, v) (w->report_mgmt |= (v ? BIT(t >> 4) : 0))
+#define GET_CFG80211_REPORT_MGMT(w, t) ((w->report_mgmt & BIT(t >> 4)) > 0)
+
+struct wiphy *rtw_wiphy_alloc(_adapter *padapter, struct device *dev);
+void rtw_wiphy_free(struct wiphy *wiphy);
+int rtw_wiphy_register(struct wiphy *wiphy);
+void rtw_wiphy_unregister(struct wiphy *wiphy);
+
+int rtw_wdev_alloc(_adapter *padapter, struct wiphy *wiphy);
+void rtw_wdev_free(struct wireless_dev *wdev);
+void rtw_wdev_unregister(struct wireless_dev *wdev);
+
+int rtw_cfg80211_ndev_res_alloc(_adapter *adapter);
+void rtw_cfg80211_ndev_res_free(_adapter *adapter);
+int rtw_cfg80211_ndev_res_register(_adapter *adapter);
+void rtw_cfg80211_ndev_res_unregister(_adapter *adapter);
+
+int rtw_cfg80211_dev_res_alloc(struct dvobj_priv *dvobj);
+void rtw_cfg80211_dev_res_free(struct dvobj_priv *dvobj);
+int rtw_cfg80211_dev_res_register(struct dvobj_priv *dvobj);
+void rtw_cfg80211_dev_res_unregister(struct dvobj_priv *dvobj);
+
+void rtw_cfg80211_init_wdev_data(_adapter *padapter);
+void rtw_cfg80211_init_wiphy(_adapter *padapter);
+
+void rtw_cfg80211_unlink_bss(_adapter *padapter, struct wlan_network *pnetwork);
+void rtw_cfg80211_surveydone_event_callback(_adapter *padapter);
+struct cfg80211_bss *rtw_cfg80211_inform_bss(_adapter *padapter, struct wlan_network *pnetwork);
+int rtw_cfg80211_check_bss(_adapter *padapter);
+void rtw_cfg80211_ibss_indicate_connect(_adapter *padapter);
+void rtw_cfg80211_indicate_connect(_adapter *padapter);
+void rtw_cfg80211_indicate_disconnect(_adapter *padapter, u16 reason, u8 locally_generated);
+void rtw_cfg80211_indicate_scan_done(_adapter *adapter, bool aborted);
+u32 rtw_cfg80211_wait_scan_req_empty(_adapter *adapter, u32 timeout_ms);
+
+#ifdef CONFIG_CONCURRENT_MODE
+u8 rtw_cfg80211_scan_via_buddy(_adapter *padapter, struct cfg80211_scan_request *request);
+void rtw_cfg80211_indicate_scan_done_for_buddy(_adapter *padapter, bool bscan_aborted);
+#endif
+
+#ifdef CONFIG_AP_MODE
+void rtw_cfg80211_indicate_sta_assoc(_adapter *padapter, u8 *pmgmt_frame, uint frame_len);
+void rtw_cfg80211_indicate_sta_disassoc(_adapter *padapter, const u8 *da, unsigned short reason);
+#endif /* CONFIG_AP_MODE */
+
+#ifdef CONFIG_P2P
+void rtw_cfg80211_set_is_roch(_adapter *adapter, bool val);
+bool rtw_cfg80211_get_is_roch(_adapter *adapter);
+bool rtw_cfg80211_is_ro_ch_once(_adapter *adapter);
+void rtw_cfg80211_set_last_ro_ch_time(_adapter *adapter);
+s32 rtw_cfg80211_get_last_ro_ch_passing_ms(_adapter *adapter);
+
+int rtw_cfg80211_iface_has_p2p_group_cap(_adapter *adapter);
+int rtw_cfg80211_is_p2p_scan(_adapter *adapter);
+#if defined(RTW_DEDICATED_P2P_DEVICE)
+int rtw_cfg80211_redirect_pd_wdev(struct wiphy *wiphy, u8 *ra, struct wireless_dev **wdev);
+int rtw_cfg80211_is_scan_by_pd_wdev(_adapter *adapter);
+int rtw_pd_iface_alloc(struct wiphy *wiphy, const char *name, struct wireless_dev **pd_wdev);
+void rtw_pd_iface_free(struct wiphy *wiphy);
+#endif
+#endif /* CONFIG_P2P */
+
+void rtw_cfg80211_set_is_mgmt_tx(_adapter *adapter, u8 val);
+u8 rtw_cfg80211_get_is_mgmt_tx(_adapter *adapter);
+u8 rtw_mgnt_tx_handler(_adapter *adapter, u8 *buf);
+
+void rtw_cfg80211_issue_p2p_provision_request(_adapter *padapter, const u8 *buf, size_t len);
+
+void rtw_cfg80211_rx_p2p_action_public(_adapter *padapter, union recv_frame *rframe);
+void rtw_cfg80211_rx_action_p2p(_adapter *padapter, union recv_frame *rframe);
+void rtw_cfg80211_rx_action(_adapter *adapter, union recv_frame *rframe, const char *msg);
+void rtw_cfg80211_rx_mframe(_adapter *adapter, union recv_frame *rframe, const char *msg);
+void rtw_cfg80211_rx_probe_request(_adapter *padapter, union recv_frame *rframe);
+
+int rtw_cfg80211_set_mgnt_wpsp2pie(struct net_device *net, char *buf, int len, int type);
+
+bool rtw_cfg80211_pwr_mgmt(_adapter *adapter);
+#ifdef CONFIG_RTW_80211K
+void rtw_cfg80211_rx_rrm_action(_adapter *adapter, union recv_frame *rframe);
+#endif
+
+#ifdef CONFIG_RFKILL_POLL
+void rtw_cfg80211_init_rfkill(struct wiphy *wiphy);
+void rtw_cfg80211_deinit_rfkill(struct wiphy *wiphy);
+#endif
+
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 4, 0))  && !defined(COMPAT_KERNEL_RELEASE)
+#define rtw_cfg80211_rx_mgmt(wdev, freq, sig_dbm, buf, len, gfp) cfg80211_rx_mgmt(wdev_to_ndev(wdev), freq, buf, len, gfp)
+#elif (LINUX_VERSION_CODE < KERNEL_VERSION(3, 6, 0))
+#define rtw_cfg80211_rx_mgmt(wdev, freq, sig_dbm, buf, len, gfp) cfg80211_rx_mgmt(wdev_to_ndev(wdev), freq, sig_dbm, buf, len, gfp)
+#elif (LINUX_VERSION_CODE < KERNEL_VERSION(3, 12, 0))
+#define rtw_cfg80211_rx_mgmt(wdev, freq, sig_dbm, buf, len, gfp) cfg80211_rx_mgmt(wdev, freq, sig_dbm, buf, len, gfp)
+#elif (LINUX_VERSION_CODE < KERNEL_VERSION(3 , 18 , 0))
+#define rtw_cfg80211_rx_mgmt(wdev , freq , sig_dbm , buf , len , gfp) cfg80211_rx_mgmt(wdev , freq , sig_dbm , buf , len , 0 , gfp)
+#else
+#define rtw_cfg80211_rx_mgmt(wdev , freq , sig_dbm , buf , len , gfp) cfg80211_rx_mgmt(wdev , freq , sig_dbm , buf , len , 0)
+#endif
+
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 4, 0))  && !defined(COMPAT_KERNEL_RELEASE)
+#define rtw_cfg80211_send_rx_assoc(adapter, bss, buf, len) cfg80211_send_rx_assoc((adapter)->pnetdev, buf, len)
+#else
+#define rtw_cfg80211_send_rx_assoc(adapter, bss, buf, len) cfg80211_send_rx_assoc((adapter)->pnetdev, bss, buf, len)
+#endif
+
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 6, 0))
+#define rtw_cfg80211_mgmt_tx_status(wdev, cookie, buf, len, ack, gfp) cfg80211_mgmt_tx_status(wdev_to_ndev(wdev), cookie, buf, len, ack, gfp)
+#else
+#define rtw_cfg80211_mgmt_tx_status(wdev, cookie, buf, len, ack, gfp) cfg80211_mgmt_tx_status(wdev, cookie, buf, len, ack, gfp)
+#endif
+
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 6, 0))
+#define rtw_cfg80211_ready_on_channel(wdev, cookie, chan, channel_type, duration, gfp)  cfg80211_ready_on_channel(wdev_to_ndev(wdev), cookie, chan, channel_type, duration, gfp)
+#define rtw_cfg80211_remain_on_channel_expired(wdev, cookie, chan, chan_type, gfp) cfg80211_remain_on_channel_expired(wdev_to_ndev(wdev), cookie, chan, chan_type, gfp)
+#elif (LINUX_VERSION_CODE < KERNEL_VERSION(3, 8, 0))
+#define rtw_cfg80211_ready_on_channel(wdev, cookie, chan, channel_type, duration, gfp)  cfg80211_ready_on_channel(wdev, cookie, chan, channel_type, duration, gfp)
+#define rtw_cfg80211_remain_on_channel_expired(wdev, cookie, chan, chan_type, gfp) cfg80211_remain_on_channel_expired(wdev, cookie, chan, chan_type, gfp)
+#else
+#define rtw_cfg80211_ready_on_channel(wdev, cookie, chan, channel_type, duration, gfp)  cfg80211_ready_on_channel(wdev, cookie, chan, duration, gfp)
+#define rtw_cfg80211_remain_on_channel_expired(wdev, cookie, chan, chan_type, gfp) cfg80211_remain_on_channel_expired(wdev, cookie, chan, gfp)
+#endif
+
+#define rtw_cfg80211_connect_result(wdev, bssid, req_ie, req_ie_len, resp_ie, resp_ie_len, status, gfp) cfg80211_connect_result(wdev_to_ndev(wdev), bssid, req_ie, req_ie_len, resp_ie, resp_ie_len, status, gfp)
+
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 2, 0))
+#define rtw_cfg80211_disconnected(wdev, reason, ie, ie_len, locally_generated, gfp) cfg80211_disconnected(wdev_to_ndev(wdev), reason, ie, ie_len, gfp)
+#else
+#define rtw_cfg80211_disconnected(wdev, reason, ie, ie_len, locally_generated, gfp) cfg80211_disconnected(wdev_to_ndev(wdev), reason, ie, ie_len, locally_generated, gfp)
+#endif
+
+#ifdef CONFIG_RTW_80211R
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 10, 0))
+#define rtw_cfg80211_ft_event(adapter, parm)  cfg80211_ft_event((adapter)->pnetdev, parm)
+#else
+	#error "Cannot support FT for KERNEL_VERSION < 3.10\n"
+#endif
+#endif
+
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 0, 0))
+#define rtw_cfg80211_notify_new_peer_candidate(wdev, addr, ie, ie_len, gfp) cfg80211_notify_new_peer_candidate(wdev_to_ndev(wdev), addr, ie, ie_len, gfp)
+#endif
+
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 5, 0))
+u8 rtw_cfg80211_ch_switch_notify(_adapter *adapter, u8 ch, u8 bw, u8 offset, u8 ht);
+#endif
+
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 26)) && (LINUX_VERSION_CODE < KERNEL_VERSION(4, 7, 0))
+#define NL80211_BAND_2GHZ IEEE80211_BAND_2GHZ
+#define NL80211_BAND_5GHZ IEEE80211_BAND_5GHZ
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 6, 0))
+#define NL80211_BAND_60GHZ IEEE80211_BAND_60GHZ
+#endif
+#define NUM_NL80211_BANDS IEEE80211_NUM_BANDS
+#endif
+
+#define rtw_band_to_nl80211_band(band) \
+	(band == BAND_ON_2_4G) ? NL80211_BAND_2GHZ : \
+	(band == BAND_ON_5G) ? NL80211_BAND_5GHZ : NUM_NL80211_BANDS
+
+#include "rtw_cfgvendor.h"
+
+#endif /* __IOCTL_CFG80211_H__ */
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/os_dep/linux/ioctl_linux.c linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/os_dep/linux/ioctl_linux.c
--- linux-5.6.3/3rdparty/rtl8821ce/os_dep/linux/ioctl_linux.c	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/os_dep/linux/ioctl_linux.c	2020-04-10 16:35:06.855661888 +0300
@@ -0,0 +1,12868 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#define _IOCTL_LINUX_C_
+
+#include <drv_types.h>
+#include <rtw_mp.h>
+#include <rtw_mp_ioctl.h>
+#include "../../hal/phydm/phydm_precomp.h"
+#ifdef RTW_HALMAC
+#include "../../hal/hal_halmac.h"
+#endif
+
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 27))
+#define  iwe_stream_add_event(a, b, c, d, e)  iwe_stream_add_event(b, c, d, e)
+#define  iwe_stream_add_point(a, b, c, d, e)  iwe_stream_add_point(b, c, d, e)
+#endif
+
+#ifdef CONFIG_80211N_HT
+extern int rtw_ht_enable;
+#endif
+
+
+#define RTL_IOCTL_WPA_SUPPLICANT	(SIOCIWFIRSTPRIV+30)
+
+#define SCAN_ITEM_SIZE 768
+#define MAX_CUSTOM_LEN 64
+#define RATE_COUNT 4
+#define MAX_SCAN_BUFFER_LEN 65535
+
+#ifdef CONFIG_GLOBAL_UI_PID
+extern int ui_pid[3];
+#endif
+
+/* combo scan */
+#define WEXT_CSCAN_AMOUNT 9
+#define WEXT_CSCAN_BUF_LEN		360
+#define WEXT_CSCAN_HEADER		"CSCAN S\x01\x00\x00S\x00"
+#define WEXT_CSCAN_HEADER_SIZE		12
+#define WEXT_CSCAN_SSID_SECTION		'S'
+#define WEXT_CSCAN_CHANNEL_SECTION	'C'
+#define WEXT_CSCAN_NPROBE_SECTION	'N'
+#define WEXT_CSCAN_ACTV_DWELL_SECTION	'A'
+#define WEXT_CSCAN_PASV_DWELL_SECTION	'P'
+#define WEXT_CSCAN_HOME_DWELL_SECTION	'H'
+#define WEXT_CSCAN_TYPE_SECTION		'T'
+
+
+extern u8 key_2char2num(u8 hch, u8 lch);
+extern u8 str_2char2num(u8 hch, u8 lch);
+extern void macstr2num(u8 *dst, u8 *src);
+extern u8 convert_ip_addr(u8 hch, u8 mch, u8 lch);
+
+u32 rtw_rates[] = {1000000, 2000000, 5500000, 11000000,
+	6000000, 9000000, 12000000, 18000000, 24000000, 36000000, 48000000, 54000000};
+
+static const char *const iw_operation_mode[] = {
+	"Auto", "Ad-Hoc", "Managed",  "Master", "Repeater", "Secondary", "Monitor"
+};
+
+/**
+ * hwaddr_aton - Convert ASCII string to MAC address
+ * @txt: MAC address as a string (e.g., "00:11:22:33:44:55")
+ * @addr: Buffer for the MAC address (ETH_ALEN = 6 bytes)
+ * Returns: 0 on success, -1 on failure (e.g., string not a MAC address)
+ */
+static int hwaddr_aton_i(const char *txt, u8 *addr)
+{
+	int i;
+
+	for (i = 0; i < 6; i++) {
+		int a, b;
+
+		a = hex2num_i(*txt++);
+		if (a < 0)
+			return -1;
+		b = hex2num_i(*txt++);
+		if (b < 0)
+			return -1;
+		*addr++ = (a << 4) | b;
+		if (i < 5 && *txt++ != ':')
+			return -1;
+	}
+
+	return 0;
+}
+
+static void indicate_wx_custom_event(_adapter *padapter, char *msg)
+{
+	u8 *buff;
+	union iwreq_data wrqu;
+
+	if (strlen(msg) > IW_CUSTOM_MAX) {
+		RTW_INFO("%s strlen(msg):%zu > IW_CUSTOM_MAX:%u\n", __FUNCTION__ , strlen(msg), IW_CUSTOM_MAX);
+		return;
+	}
+
+	buff = rtw_zmalloc(IW_CUSTOM_MAX + 1);
+	if (!buff)
+		return;
+
+	_rtw_memcpy(buff, msg, strlen(msg));
+
+	_rtw_memset(&wrqu, 0, sizeof(wrqu));
+	wrqu.data.length = strlen(msg);
+
+	RTW_INFO("%s %s\n", __FUNCTION__, buff);
+#ifndef CONFIG_IOCTL_CFG80211
+	wireless_send_event(padapter->pnetdev, IWEVCUSTOM, &wrqu, buff);
+#endif
+
+	rtw_mfree(buff, IW_CUSTOM_MAX + 1);
+
+}
+
+
+static void request_wps_pbc_event(_adapter *padapter)
+{
+	u8 *buff, *p;
+	union iwreq_data wrqu;
+
+
+	buff = rtw_malloc(IW_CUSTOM_MAX);
+	if (!buff)
+		return;
+
+	_rtw_memset(buff, 0, IW_CUSTOM_MAX);
+
+	p = buff;
+
+	p += sprintf(p, "WPS_PBC_START.request=TRUE");
+
+	_rtw_memset(&wrqu, 0, sizeof(wrqu));
+
+	wrqu.data.length = p - buff;
+
+	wrqu.data.length = (wrqu.data.length < IW_CUSTOM_MAX) ? wrqu.data.length : IW_CUSTOM_MAX;
+
+	RTW_INFO("%s\n", __FUNCTION__);
+
+#ifndef CONFIG_IOCTL_CFG80211
+	wireless_send_event(padapter->pnetdev, IWEVCUSTOM, &wrqu, buff);
+#endif
+
+	if (buff)
+		rtw_mfree(buff, IW_CUSTOM_MAX);
+
+}
+
+#ifdef CONFIG_SUPPORT_HW_WPS_PBC
+void rtw_request_wps_pbc_event(_adapter *padapter)
+{
+#ifdef RTK_DMP_PLATFORM
+#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 12))
+	kobject_uevent(&padapter->pnetdev->dev.kobj, KOBJ_NET_PBC);
+#else
+	kobject_hotplug(&padapter->pnetdev->class_dev.kobj, KOBJ_NET_PBC);
+#endif
+#else
+
+	if (padapter->pid[0] == 0) {
+		/*	0 is the default value and it means the application monitors the HW PBC doesn't privde its pid to driver. */
+		return;
+	}
+
+	rtw_signal_process(padapter->pid[0], SIGUSR1);
+
+#endif
+
+	rtw_led_control(padapter, LED_CTL_START_WPS_BOTTON);
+}
+#endif/* #ifdef CONFIG_SUPPORT_HW_WPS_PBC */
+
+void indicate_wx_scan_complete_event(_adapter *padapter)
+{
+	union iwreq_data wrqu;
+
+	_rtw_memset(&wrqu, 0, sizeof(union iwreq_data));
+
+	/* RTW_INFO("+rtw_indicate_wx_scan_complete_event\n"); */
+#ifndef CONFIG_IOCTL_CFG80211
+	wireless_send_event(padapter->pnetdev, SIOCGIWSCAN, &wrqu, NULL);
+#endif
+}
+
+
+void rtw_indicate_wx_assoc_event(_adapter *padapter)
+{
+	union iwreq_data wrqu;
+	struct	mlme_priv *pmlmepriv = &padapter->mlmepriv;
+	struct mlme_ext_priv	*pmlmeext = &padapter->mlmeextpriv;
+	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
+	WLAN_BSSID_EX		*pnetwork = (WLAN_BSSID_EX *)(&(pmlmeinfo->network));
+
+	_rtw_memset(&wrqu, 0, sizeof(union iwreq_data));
+
+	wrqu.ap_addr.sa_family = ARPHRD_ETHER;
+
+	if (check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE) == _TRUE)
+		_rtw_memcpy(wrqu.ap_addr.sa_data, pnetwork->MacAddress, ETH_ALEN);
+	else
+		_rtw_memcpy(wrqu.ap_addr.sa_data, pmlmepriv->cur_network.network.MacAddress, ETH_ALEN);
+
+	RTW_PRINT("assoc success\n");
+#ifndef CONFIG_IOCTL_CFG80211
+	wireless_send_event(padapter->pnetdev, SIOCGIWAP, &wrqu, NULL);
+#endif
+}
+
+void rtw_indicate_wx_disassoc_event(_adapter *padapter)
+{
+	union iwreq_data wrqu;
+
+	_rtw_memset(&wrqu, 0, sizeof(union iwreq_data));
+
+	wrqu.ap_addr.sa_family = ARPHRD_ETHER;
+	_rtw_memset(wrqu.ap_addr.sa_data, 0, ETH_ALEN);
+
+#ifndef CONFIG_IOCTL_CFG80211
+	RTW_PRINT("indicate disassoc\n");
+	wireless_send_event(padapter->pnetdev, SIOCGIWAP, &wrqu, NULL);
+#endif
+}
+
+/*
+uint	rtw_is_cckrates_included(u8 *rate)
+{
+		u32	i = 0;
+
+		while(rate[i]!=0)
+		{
+			if  (  (((rate[i]) & 0x7f) == 2)	|| (((rate[i]) & 0x7f) == 4) ||
+			(((rate[i]) & 0x7f) == 11)  || (((rate[i]) & 0x7f) == 22) )
+			return _TRUE;
+			i++;
+		}
+
+		return _FALSE;
+}
+
+uint	rtw_is_cckratesonly_included(u8 *rate)
+{
+	u32 i = 0;
+
+	while(rate[i]!=0)
+	{
+			if  (  (((rate[i]) & 0x7f) != 2) && (((rate[i]) & 0x7f) != 4) &&
+				(((rate[i]) & 0x7f) != 11)  && (((rate[i]) & 0x7f) != 22) )
+			return _FALSE;
+			i++;
+	}
+
+	return _TRUE;
+}
+*/
+
+static int search_p2p_wfd_ie(_adapter *padapter,
+		struct iw_request_info *info, struct wlan_network *pnetwork,
+		char *start, char *stop)
+{
+#ifdef CONFIG_P2P
+	struct wifidirect_info	*pwdinfo = &padapter->wdinfo;
+#ifdef CONFIG_WFD
+	if (SCAN_RESULT_ALL == pwdinfo->wfd_info->scan_result_type) {
+
+	} else if ((SCAN_RESULT_P2P_ONLY == pwdinfo->wfd_info->scan_result_type) ||
+		(SCAN_RESULT_WFD_TYPE == pwdinfo->wfd_info->scan_result_type))
+#endif /* CONFIG_WFD */
+	{
+		if (!rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE)) {
+			u32	blnGotP2PIE = _FALSE;
+
+			/*	User is doing the P2P device discovery */
+			/*	The prefix of SSID should be "DIRECT-" and the IE should contains the P2P IE. */
+			/*	If not, the driver should ignore this AP and go to the next AP. */
+
+			/*	Verifying the SSID */
+			if (_rtw_memcmp(pnetwork->network.Ssid.Ssid, pwdinfo->p2p_wildcard_ssid, P2P_WILDCARD_SSID_LEN)) {
+				u32	p2pielen = 0;
+
+				/*	Verifying the P2P IE */
+				if (rtw_bss_ex_get_p2p_ie(&pnetwork->network, NULL, &p2pielen))
+					blnGotP2PIE = _TRUE;
+			}
+
+			if (blnGotP2PIE == _FALSE)
+				return _FALSE;
+
+		}
+	}
+
+#ifdef CONFIG_WFD
+	if (SCAN_RESULT_WFD_TYPE == pwdinfo->wfd_info->scan_result_type) {
+		u32	blnGotWFD = _FALSE;
+		u8 *wfd_ie;
+		uint wfd_ielen = 0;
+
+		wfd_ie = rtw_bss_ex_get_wfd_ie(&pnetwork->network, NULL, &wfd_ielen);
+		if (wfd_ie) {
+			u8 *wfd_devinfo;
+			uint wfd_devlen;
+
+			wfd_devinfo = rtw_get_wfd_attr_content(wfd_ie, wfd_ielen, WFD_ATTR_DEVICE_INFO, NULL, &wfd_devlen);
+			if (wfd_devinfo) {
+				if (pwdinfo->wfd_info->wfd_device_type == WFD_DEVINFO_PSINK) {
+					/*	the first two bits will indicate the WFD device type */
+					if ((wfd_devinfo[1] & 0x03) == WFD_DEVINFO_SOURCE) {
+						/*	If this device is Miracast PSink device, the scan reuslt should just provide the Miracast source. */
+						blnGotWFD = _TRUE;
+					}
+				} else if (pwdinfo->wfd_info->wfd_device_type == WFD_DEVINFO_SOURCE) {
+					/*	the first two bits will indicate the WFD device type */
+					if ((wfd_devinfo[1] & 0x03) == WFD_DEVINFO_PSINK) {
+						/*	If this device is Miracast source device, the scan reuslt should just provide the Miracast PSink. */
+						/*	Todo: How about the SSink?! */
+						blnGotWFD = _TRUE;
+					}
+				}
+			}
+		}
+
+		if (blnGotWFD == _FALSE)
+			return _FALSE;
+	}
+#endif /* CONFIG_WFD */
+
+#endif /* CONFIG_P2P */
+	return _TRUE;
+}
+static inline char *iwe_stream_mac_addr_proess(_adapter *padapter,
+		struct iw_request_info *info, struct wlan_network *pnetwork,
+		char *start, char *stop, struct iw_event *iwe)
+{
+	/*  AP MAC address */
+	iwe->cmd = SIOCGIWAP;
+	iwe->u.ap_addr.sa_family = ARPHRD_ETHER;
+
+	_rtw_memcpy(iwe->u.ap_addr.sa_data, pnetwork->network.MacAddress, ETH_ALEN);
+	start = iwe_stream_add_event(info, start, stop, iwe, IW_EV_ADDR_LEN);
+	return start;
+}
+static inline char *iwe_stream_essid_proess(_adapter *padapter,
+		struct iw_request_info *info, struct wlan_network *pnetwork,
+		char *start, char *stop, struct iw_event *iwe)
+{
+
+	/* Add the ESSID */
+	iwe->cmd = SIOCGIWESSID;
+	iwe->u.data.flags = 1;
+	iwe->u.data.length = min((u16)pnetwork->network.Ssid.SsidLength, (u16)32);
+	start = iwe_stream_add_point(info, start, stop, iwe, pnetwork->network.Ssid.Ssid);
+	return start;
+}
+
+static inline char *iwe_stream_chan_process(_adapter *padapter,
+		struct iw_request_info *info, struct wlan_network *pnetwork,
+		char *start, char *stop, struct iw_event *iwe)
+{
+	if (pnetwork->network.Configuration.DSConfig < 1 /*|| pnetwork->network.Configuration.DSConfig>14*/)
+		pnetwork->network.Configuration.DSConfig = 1;
+
+	/* Add frequency/channel */
+	iwe->cmd = SIOCGIWFREQ;
+	iwe->u.freq.m = rtw_ch2freq(pnetwork->network.Configuration.DSConfig) * 100000;
+	iwe->u.freq.e = 1;
+	iwe->u.freq.i = pnetwork->network.Configuration.DSConfig;
+	start = iwe_stream_add_event(info, start, stop, iwe, IW_EV_FREQ_LEN);
+	return start;
+}
+static inline char *iwe_stream_mode_process(_adapter *padapter,
+		struct iw_request_info *info, struct wlan_network *pnetwork,
+		char *start, char *stop, struct iw_event *iwe, u16 cap)
+{
+	/* Add mode */
+	if (cap & (WLAN_CAPABILITY_IBSS | WLAN_CAPABILITY_BSS)) {
+		iwe->cmd = SIOCGIWMODE;
+		if (cap & WLAN_CAPABILITY_BSS)
+			iwe->u.mode = IW_MODE_MASTER;
+		else
+			iwe->u.mode = IW_MODE_ADHOC;
+
+		start = iwe_stream_add_event(info, start, stop, iwe, IW_EV_UINT_LEN);
+	}
+	return start;
+}
+static inline char *iwe_stream_encryption_process(_adapter *padapter,
+		struct iw_request_info *info, struct wlan_network *pnetwork,
+		char *start, char *stop, struct iw_event *iwe, u16 cap)
+{
+
+	/* Add encryption capability */
+	iwe->cmd = SIOCGIWENCODE;
+	if (cap & WLAN_CAPABILITY_PRIVACY)
+		iwe->u.data.flags = IW_ENCODE_ENABLED | IW_ENCODE_NOKEY;
+	else
+		iwe->u.data.flags = IW_ENCODE_DISABLED;
+	iwe->u.data.length = 0;
+	start = iwe_stream_add_point(info, start, stop, iwe, pnetwork->network.Ssid.Ssid);
+	return start;
+
+}
+
+static inline char *iwe_stream_protocol_process(_adapter *padapter,
+		struct iw_request_info *info, struct wlan_network *pnetwork,
+		char *start, char *stop, struct iw_event *iwe)
+{
+	u16 ht_cap = _FALSE, vht_cap = _FALSE;
+	u32 ht_ielen = 0, vht_ielen = 0;
+	char *p;
+	u8 ie_offset = (pnetwork->network.Reserved[0] == BSS_TYPE_PROB_REQ ? 0 : 12); /* Probe Request	 */
+
+#ifdef CONFIG_80211N_HT
+	/* parsing HT_CAP_IE	 */
+	if(padapter->registrypriv.ht_enable && is_supported_ht(padapter->registrypriv.wireless_mode)) {
+		p = rtw_get_ie(&pnetwork->network.IEs[ie_offset], _HT_CAPABILITY_IE_, &ht_ielen, pnetwork->network.IELength - ie_offset);
+		if (p && ht_ielen > 0)
+			ht_cap = _TRUE;
+	}
+#endif
+
+#ifdef CONFIG_80211AC_VHT
+	/* parsing VHT_CAP_IE */
+	if(padapter->registrypriv.wireless_mode & WIRELESS_11AC) {
+		p = rtw_get_ie(&pnetwork->network.IEs[ie_offset], EID_VHTCapability, &vht_ielen, pnetwork->network.IELength - ie_offset);
+		if (p && vht_ielen > 0)
+			vht_cap = _TRUE;
+	}
+#endif
+	/* Add the protocol name */
+	iwe->cmd = SIOCGIWNAME;
+	if ((rtw_is_cckratesonly_included((u8 *)&pnetwork->network.SupportedRates)) == _TRUE) {
+		if (ht_cap == _TRUE)
+			snprintf(iwe->u.name, IFNAMSIZ, "IEEE 802.11bn");
+		else
+			snprintf(iwe->u.name, IFNAMSIZ, "IEEE 802.11b");
+	} else if ((rtw_is_cckrates_included((u8 *)&pnetwork->network.SupportedRates)) == _TRUE) {
+		if (ht_cap == _TRUE)
+			snprintf(iwe->u.name, IFNAMSIZ, "IEEE 802.11bgn");
+		else
+			snprintf(iwe->u.name, IFNAMSIZ, "IEEE 802.11bg");
+	} else {
+		if (pnetwork->network.Configuration.DSConfig > 14) {
+			#ifdef CONFIG_80211AC_VHT
+			if (vht_cap == _TRUE)
+				snprintf(iwe->u.name, IFNAMSIZ, "IEEE 802.11AC");
+			else
+			#endif
+			{
+				if (ht_cap == _TRUE)
+					snprintf(iwe->u.name, IFNAMSIZ, "IEEE 802.11an");
+				else
+					snprintf(iwe->u.name, IFNAMSIZ, "IEEE 802.11a");
+			}
+		} else {
+			if (ht_cap == _TRUE)
+				snprintf(iwe->u.name, IFNAMSIZ, "IEEE 802.11gn");
+			else
+				snprintf(iwe->u.name, IFNAMSIZ, "IEEE 802.11g");
+		}
+	}
+	start = iwe_stream_add_event(info, start, stop, iwe, IW_EV_CHAR_LEN);
+	return start;
+}
+
+static inline char *iwe_stream_rate_process(_adapter *padapter,
+		struct iw_request_info *info, struct wlan_network *pnetwork,
+		char *start, char *stop, struct iw_event *iwe)
+{
+	u32 ht_ielen = 0, vht_ielen = 0;
+	char *p;
+	u16 max_rate = 0, rate, ht_cap = _FALSE, vht_cap = _FALSE;
+	u32 i = 0;
+	u8 bw_40MHz = 0, short_GI = 0, bw_160MHz = 0, vht_highest_rate = 0;
+	u16 mcs_rate = 0, vht_data_rate = 0;
+	char custom[MAX_CUSTOM_LEN] = {0};
+	u8 ie_offset = (pnetwork->network.Reserved[0] == BSS_TYPE_PROB_REQ ? 0 : 12); /* Probe Request	 */
+
+	/* parsing HT_CAP_IE	 */
+	if(is_supported_ht(padapter->registrypriv.wireless_mode)) {
+		p = rtw_get_ie(&pnetwork->network.IEs[ie_offset], _HT_CAPABILITY_IE_, &ht_ielen, pnetwork->network.IELength - ie_offset);
+		if (p && ht_ielen > 0) {
+			struct rtw_ieee80211_ht_cap *pht_capie;
+			ht_cap = _TRUE;
+			pht_capie = (struct rtw_ieee80211_ht_cap *)(p + 2);
+			_rtw_memcpy(&mcs_rate , pht_capie->supp_mcs_set, 2);
+			bw_40MHz = (pht_capie->cap_info & IEEE80211_HT_CAP_SUP_WIDTH) ? 1 : 0;
+			short_GI = (pht_capie->cap_info & (IEEE80211_HT_CAP_SGI_20 | IEEE80211_HT_CAP_SGI_40)) ? 1 : 0;
+		}
+	}
+#ifdef CONFIG_80211AC_VHT
+	/* parsing VHT_CAP_IE */
+	if(padapter->registrypriv.wireless_mode & WIRELESS_11AC){
+		p = rtw_get_ie(&pnetwork->network.IEs[ie_offset], EID_VHTCapability, &vht_ielen, pnetwork->network.IELength - ie_offset);
+		if (p && vht_ielen > 0) {
+			u8	mcs_map[2];
+
+			vht_cap = _TRUE;
+			bw_160MHz = GET_VHT_CAPABILITY_ELE_CHL_WIDTH(p + 2);
+			if (bw_160MHz)
+				short_GI = GET_VHT_CAPABILITY_ELE_SHORT_GI160M(p + 2);
+			else
+				short_GI = GET_VHT_CAPABILITY_ELE_SHORT_GI80M(p + 2);
+
+			_rtw_memcpy(mcs_map, GET_VHT_CAPABILITY_ELE_TX_MCS(p + 2), 2);
+
+			vht_highest_rate = rtw_get_vht_highest_rate(mcs_map);
+			vht_data_rate = rtw_vht_mcs_to_data_rate(CHANNEL_WIDTH_80, short_GI, vht_highest_rate);
+		}
+	}
+#endif
+
+	/*Add basic and extended rates */
+	p = custom;
+	p += snprintf(p, MAX_CUSTOM_LEN - (p - custom), " Rates (Mb/s): ");
+	while (pnetwork->network.SupportedRates[i] != 0) {
+		rate = pnetwork->network.SupportedRates[i] & 0x7F;
+		if (rate > max_rate)
+			max_rate = rate;
+		p += snprintf(p, MAX_CUSTOM_LEN - (p - custom),
+			      "%d%s ", rate >> 1, (rate & 1) ? ".5" : "");
+		i++;
+	}
+#ifdef CONFIG_80211AC_VHT
+	if (vht_cap == _TRUE)
+		max_rate = vht_data_rate;
+	else
+#endif
+		if (ht_cap == _TRUE) {
+			if (mcs_rate & 0x8000) /* MCS15 */
+				max_rate = (bw_40MHz) ? ((short_GI) ? 300 : 270) : ((short_GI) ? 144 : 130);
+
+			else if (mcs_rate & 0x0080) /* MCS7 */
+				max_rate = (bw_40MHz) ? ((short_GI) ? 150 : 135) : ((short_GI) ? 72 : 65);
+			else { /* default MCS7 */
+				/* RTW_INFO("wx_get_scan, mcs_rate_bitmap=0x%x\n", mcs_rate); */
+				max_rate = (bw_40MHz) ? ((short_GI) ? 150 : 135) : ((short_GI) ? 72 : 65);
+			}
+
+			max_rate = max_rate * 2; /* Mbps/2;		 */
+		}
+
+	iwe->cmd = SIOCGIWRATE;
+	iwe->u.bitrate.fixed = iwe->u.bitrate.disabled = 0;
+	iwe->u.bitrate.value = max_rate * 500000;
+	start = iwe_stream_add_event(info, start, stop, iwe, IW_EV_PARAM_LEN);
+	return start ;
+}
+
+static inline char *iwe_stream_wpa_wpa2_process(_adapter *padapter,
+		struct iw_request_info *info, struct wlan_network *pnetwork,
+		char *start, char *stop, struct iw_event *iwe)
+{
+	int buf_size = MAX_WPA_IE_LEN * 2;
+	/* u8 pbuf[buf_size]={0};	 */
+	u8 *pbuf = rtw_zmalloc(buf_size);
+
+	u8 wpa_ie[255] = {0}, rsn_ie[255] = {0};
+	u16 i, wpa_len = 0, rsn_len = 0;
+	u8 *p;
+	sint out_len = 0;
+
+
+	if (pbuf) {
+		p = pbuf;
+
+		/* parsing WPA/WPA2 IE */
+		if (pnetwork->network.Reserved[0] != BSS_TYPE_PROB_REQ) { /* Probe Request */
+			out_len = rtw_get_sec_ie(pnetwork->network.IEs , pnetwork->network.IELength, rsn_ie, &rsn_len, wpa_ie, &wpa_len);
+
+			if (wpa_len > 0) {
+
+				_rtw_memset(pbuf, 0, buf_size);
+				p += sprintf(p, "wpa_ie=");
+				for (i = 0; i < wpa_len; i++)
+					p += sprintf(p, "%02x", wpa_ie[i]);
+
+				if (wpa_len > 100) {
+					printk("-----------------Len %d----------------\n", wpa_len);
+					for (i = 0; i < wpa_len; i++)
+						printk("%02x ", wpa_ie[i]);
+					printk("\n");
+					printk("-----------------Len %d----------------\n", wpa_len);
+				}
+
+				_rtw_memset(iwe, 0, sizeof(*iwe));
+				iwe->cmd = IWEVCUSTOM;
+				iwe->u.data.length = strlen(pbuf);
+				start = iwe_stream_add_point(info, start, stop, iwe, pbuf);
+
+				_rtw_memset(iwe, 0, sizeof(*iwe));
+				iwe->cmd = IWEVGENIE;
+				iwe->u.data.length = wpa_len;
+				start = iwe_stream_add_point(info, start, stop, iwe, wpa_ie);
+			}
+			if (rsn_len > 0) {
+
+				_rtw_memset(pbuf, 0, buf_size);
+				p += sprintf(p, "rsn_ie=");
+				for (i = 0; i < rsn_len; i++)
+					p += sprintf(p, "%02x", rsn_ie[i]);
+				_rtw_memset(iwe, 0, sizeof(*iwe));
+				iwe->cmd = IWEVCUSTOM;
+				iwe->u.data.length = strlen(pbuf);
+				start = iwe_stream_add_point(info, start, stop, iwe, pbuf);
+
+				_rtw_memset(iwe, 0, sizeof(*iwe));
+				iwe->cmd = IWEVGENIE;
+				iwe->u.data.length = rsn_len;
+				start = iwe_stream_add_point(info, start, stop, iwe, rsn_ie);
+			}
+		}
+
+		rtw_mfree(pbuf, buf_size);
+	}
+	return start;
+}
+
+static inline char *iwe_stream_wps_process(_adapter *padapter,
+		struct iw_request_info *info, struct wlan_network *pnetwork,
+		char *start, char *stop, struct iw_event *iwe)
+{
+	/* parsing WPS IE */
+	uint cnt = 0, total_ielen;
+	u8 *wpsie_ptr = NULL;
+	uint wps_ielen = 0;
+	u8 ie_offset = (pnetwork->network.Reserved[0] == BSS_TYPE_PROB_REQ ? 0 : 12);
+
+	u8 *ie_ptr = pnetwork->network.IEs + ie_offset;
+	total_ielen = pnetwork->network.IELength - ie_offset;
+
+	if (pnetwork->network.Reserved[0] == BSS_TYPE_PROB_REQ) { /* Probe Request */
+		ie_ptr = pnetwork->network.IEs;
+		total_ielen = pnetwork->network.IELength;
+	} else { /* Beacon or Probe Respones */
+		ie_ptr = pnetwork->network.IEs + _FIXED_IE_LENGTH_;
+		total_ielen = pnetwork->network.IELength - _FIXED_IE_LENGTH_;
+	}
+	while (cnt < total_ielen) {
+		if (rtw_is_wps_ie(&ie_ptr[cnt], &wps_ielen) && (wps_ielen > 2)) {
+			wpsie_ptr = &ie_ptr[cnt];
+			iwe->cmd = IWEVGENIE;
+			iwe->u.data.length = (u16)wps_ielen;
+			start = iwe_stream_add_point(info, start, stop, iwe, wpsie_ptr);
+		}
+		cnt += ie_ptr[cnt + 1] + 2; /* goto next */
+	}
+	return start;
+}
+
+static inline char *iwe_stream_wapi_process(_adapter *padapter,
+		struct iw_request_info *info, struct wlan_network *pnetwork,
+		char *start, char *stop, struct iw_event *iwe)
+{
+#ifdef CONFIG_WAPI_SUPPORT
+	char *p;
+
+	if (pnetwork->network.Reserved[0] != BSS_TYPE_PROB_REQ) { /* Probe Request */
+		sint out_len_wapi = 0;
+		/* here use static for stack size */
+		static u8 buf_wapi[MAX_WAPI_IE_LEN * 2] = {0};
+		static u8 wapi_ie[MAX_WAPI_IE_LEN] = {0};
+		u16 wapi_len = 0;
+		u16  i;
+
+		out_len_wapi = rtw_get_wapi_ie(pnetwork->network.IEs , pnetwork->network.IELength, wapi_ie, &wapi_len);
+
+		RTW_INFO("rtw_wx_get_scan: %s ", pnetwork->network.Ssid.Ssid);
+		RTW_INFO("rtw_wx_get_scan: ssid = %d ", wapi_len);
+
+
+		if (wapi_len > 0) {
+			p = buf_wapi;
+			/* _rtw_memset(buf_wapi, 0, MAX_WAPI_IE_LEN*2); */
+			p += sprintf(p, "wapi_ie=");
+			for (i = 0; i < wapi_len; i++)
+				p += sprintf(p, "%02x", wapi_ie[i]);
+
+			_rtw_memset(iwe, 0, sizeof(*iwe));
+			iwe->cmd = IWEVCUSTOM;
+			iwe->u.data.length = strlen(buf_wapi);
+			start = iwe_stream_add_point(info, start, stop, iwe, buf_wapi);
+
+			_rtw_memset(iwe, 0, sizeof(*iwe));
+			iwe->cmd = IWEVGENIE;
+			iwe->u.data.length = wapi_len;
+			start = iwe_stream_add_point(info, start, stop, iwe, wapi_ie);
+		}
+	}
+#endif/* #ifdef CONFIG_WAPI_SUPPORT */
+	return start;
+}
+
+static inline char   *iwe_stream_rssi_process(_adapter *padapter,
+		struct iw_request_info *info, struct wlan_network *pnetwork,
+		char *start, char *stop, struct iw_event *iwe)
+{
+	u8 ss, sq;
+	struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
+#ifdef CONFIG_BACKGROUND_NOISE_MONITOR
+	s16 noise = 0;
+#endif
+
+	/* Add quality statistics */
+	iwe->cmd = IWEVQUAL;
+	iwe->u.qual.updated = IW_QUAL_QUAL_UPDATED | IW_QUAL_LEVEL_UPDATED
+#ifdef CONFIG_BACKGROUND_NOISE_MONITOR
+			      | IW_QUAL_NOISE_UPDATED
+#else
+			      | IW_QUAL_NOISE_INVALID
+#endif
+#ifdef CONFIG_SIGNAL_DISPLAY_DBM
+			      | IW_QUAL_DBM
+#endif
+			      ;
+
+	if (check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE &&
+	    is_same_network(&pmlmepriv->cur_network.network, &pnetwork->network, 0)) {
+		ss = padapter->recvpriv.signal_strength;
+		sq = padapter->recvpriv.signal_qual;
+	} else {
+		ss = pnetwork->network.PhyInfo.SignalStrength;
+		sq = pnetwork->network.PhyInfo.SignalQuality;
+	}
+
+
+#ifdef CONFIG_SIGNAL_DISPLAY_DBM
+	iwe->u.qual.level = (u8) translate_percentage_to_dbm(ss); /* dbm */
+#else
+	iwe->u.qual.level = (u8)ss; /* % */
+#endif
+
+	iwe->u.qual.qual = (u8)sq;   /* signal quality */
+
+#ifdef CONFIG_PLATFORM_ROCKCHIPS
+	iwe->u.qual.noise = -100; /* noise level suggest by zhf@rockchips */
+#else
+#ifdef CONFIG_BACKGROUND_NOISE_MONITOR
+	if (IS_NM_ENABLE(padapter)) {
+		noise = rtw_noise_query_by_chan_num(padapter, pnetwork->network.Configuration.DSConfig);
+		#ifndef CONFIG_SIGNAL_DISPLAY_DBM
+		noise = translate_dbm_to_percentage(noise);/*percentage*/
+		#endif
+		iwe->u.qual.noise = noise;
+	}
+#else
+	iwe->u.qual.noise = 0; /* noise level */
+#endif
+#endif /* CONFIG_PLATFORM_ROCKCHIPS */
+
+	/* RTW_INFO("iqual=%d, ilevel=%d, inoise=%d, iupdated=%d\n", iwe.u.qual.qual, iwe.u.qual.level , iwe.u.qual.noise, iwe.u.qual.updated); */
+
+	start = iwe_stream_add_event(info, start, stop, iwe, IW_EV_QUAL_LEN);
+	return start;
+}
+
+static inline char   *iwe_stream_net_rsv_process(_adapter *padapter,
+		struct iw_request_info *info, struct wlan_network *pnetwork,
+		char *start, char *stop, struct iw_event *iwe)
+{
+	u8 buf[32] = {0};
+	u8 *p, *pos;
+	p = buf;
+	pos = pnetwork->network.Reserved;
+
+	p += sprintf(p, "fm=%02X%02X", pos[1], pos[0]);
+	_rtw_memset(iwe, 0, sizeof(*iwe));
+	iwe->cmd = IWEVCUSTOM;
+	iwe->u.data.length = strlen(buf);
+	start = iwe_stream_add_point(info, start, stop, iwe, buf);
+	return start;
+}
+
+static char *translate_scan(_adapter *padapter,
+		struct iw_request_info *info, struct wlan_network *pnetwork,
+		char *start, char *stop)
+{
+	struct iw_event iwe;
+	u16 cap = 0;
+	_rtw_memset(&iwe, 0, sizeof(iwe));
+
+	if (_FALSE == search_p2p_wfd_ie(padapter, info, pnetwork, start, stop))
+		return start;
+
+	start = iwe_stream_mac_addr_proess(padapter, info, pnetwork, start, stop, &iwe);
+	start = iwe_stream_essid_proess(padapter, info, pnetwork, start, stop, &iwe);
+	start = iwe_stream_protocol_process(padapter, info, pnetwork, start, stop, &iwe);
+	if (pnetwork->network.Reserved[0] == BSS_TYPE_PROB_REQ) /* Probe Request */
+		cap = 0;
+	else {
+		_rtw_memcpy((u8 *)&cap, rtw_get_capability_from_ie(pnetwork->network.IEs), 2);
+		cap = le16_to_cpu(cap);
+	}
+
+	start = iwe_stream_mode_process(padapter, info, pnetwork, start, stop, &iwe, cap);
+	start = iwe_stream_chan_process(padapter, info, pnetwork, start, stop, &iwe);
+	start = iwe_stream_encryption_process(padapter, info, pnetwork, start, stop, &iwe, cap);
+	start = iwe_stream_rate_process(padapter, info, pnetwork, start, stop, &iwe);
+	start = iwe_stream_wpa_wpa2_process(padapter, info, pnetwork, start, stop, &iwe);
+	start = iwe_stream_wps_process(padapter, info, pnetwork, start, stop, &iwe);
+	start = iwe_stream_wapi_process(padapter, info, pnetwork, start, stop, &iwe);
+	start = iwe_stream_rssi_process(padapter, info, pnetwork, start, stop, &iwe);
+	start = iwe_stream_net_rsv_process(padapter, info, pnetwork, start, stop, &iwe);
+
+	return start;
+}
+
+static int wpa_set_auth_algs(struct net_device *dev, u32 value)
+{
+	_adapter *padapter = (_adapter *) rtw_netdev_priv(dev);
+	int ret = 0;
+
+	if ((value & AUTH_ALG_SHARED_KEY) && (value & AUTH_ALG_OPEN_SYSTEM)) {
+		RTW_INFO("wpa_set_auth_algs, AUTH_ALG_SHARED_KEY and  AUTH_ALG_OPEN_SYSTEM [value:0x%x]\n", value);
+		padapter->securitypriv.ndisencryptstatus = Ndis802_11Encryption1Enabled;
+		padapter->securitypriv.ndisauthtype = Ndis802_11AuthModeAutoSwitch;
+		padapter->securitypriv.dot11AuthAlgrthm = dot11AuthAlgrthm_Auto;
+	} else if (value & AUTH_ALG_SHARED_KEY) {
+		RTW_INFO("wpa_set_auth_algs, AUTH_ALG_SHARED_KEY  [value:0x%x]\n", value);
+		padapter->securitypriv.ndisencryptstatus = Ndis802_11Encryption1Enabled;
+
+#ifdef CONFIG_PLATFORM_MT53XX
+		padapter->securitypriv.ndisauthtype = Ndis802_11AuthModeAutoSwitch;
+		padapter->securitypriv.dot11AuthAlgrthm = dot11AuthAlgrthm_Auto;
+#else
+		padapter->securitypriv.ndisauthtype = Ndis802_11AuthModeShared;
+		padapter->securitypriv.dot11AuthAlgrthm = dot11AuthAlgrthm_Shared;
+#endif
+	} else if (value & AUTH_ALG_OPEN_SYSTEM) {
+		RTW_INFO("wpa_set_auth_algs, AUTH_ALG_OPEN_SYSTEM\n");
+		/* padapter->securitypriv.ndisencryptstatus = Ndis802_11EncryptionDisabled; */
+		if (padapter->securitypriv.ndisauthtype < Ndis802_11AuthModeWPAPSK) {
+#ifdef CONFIG_PLATFORM_MT53XX
+			padapter->securitypriv.ndisauthtype = Ndis802_11AuthModeAutoSwitch;
+			padapter->securitypriv.dot11AuthAlgrthm = dot11AuthAlgrthm_Auto;
+#else
+			padapter->securitypriv.ndisauthtype = Ndis802_11AuthModeOpen;
+			padapter->securitypriv.dot11AuthAlgrthm = dot11AuthAlgrthm_Open;
+#endif
+		}
+
+	} else if (value & AUTH_ALG_LEAP)
+		RTW_INFO("wpa_set_auth_algs, AUTH_ALG_LEAP\n");
+	else {
+		RTW_INFO("wpa_set_auth_algs, error!\n");
+		ret = -EINVAL;
+	}
+
+	return ret;
+
+}
+
+static int wpa_set_encryption(struct net_device *dev, struct ieee_param *param, u32 param_len)
+{
+	int ret = 0;
+	u32 wep_key_idx, wep_key_len;
+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
+	struct mlme_priv	*pmlmepriv = &padapter->mlmepriv;
+	struct security_priv *psecuritypriv = &padapter->securitypriv;
+#ifdef CONFIG_P2P
+	struct wifidirect_info *pwdinfo = &padapter->wdinfo;
+#endif /* CONFIG_P2P */
+
+
+	param->u.crypt.err = 0;
+	param->u.crypt.alg[IEEE_CRYPT_ALG_NAME_LEN - 1] = '\0';
+
+	if (param_len < (u32)((u8 *) param->u.crypt.key - (u8 *) param) + param->u.crypt.key_len) {
+		ret =  -EINVAL;
+		goto exit;
+	}
+
+	if (param->sta_addr[0] == 0xff && param->sta_addr[1] == 0xff &&
+	    param->sta_addr[2] == 0xff && param->sta_addr[3] == 0xff &&
+	    param->sta_addr[4] == 0xff && param->sta_addr[5] == 0xff) {
+
+		if (param->u.crypt.idx >= WEP_KEYS
+#ifdef CONFIG_IEEE80211W
+		    && param->u.crypt.idx > BIP_MAX_KEYID
+#endif /* CONFIG_IEEE80211W */
+		   ) {
+			ret = -EINVAL;
+			goto exit;
+		}
+	} else {
+#ifdef CONFIG_WAPI_SUPPORT
+		if (strcmp(param->u.crypt.alg, "SMS4"))
+#endif
+		{
+			ret = -EINVAL;
+			goto exit;
+		}
+	}
+
+	if (strcmp(param->u.crypt.alg, "WEP") == 0) {
+		RTW_INFO("wpa_set_encryption, crypt.alg = WEP\n");
+
+		wep_key_idx = param->u.crypt.idx;
+		wep_key_len = param->u.crypt.key_len;
+
+		if ((wep_key_idx >= WEP_KEYS) || (wep_key_len <= 0)) {
+			ret = -EINVAL;
+			goto exit;
+		}
+
+		if (psecuritypriv->bWepDefaultKeyIdxSet == 0) {
+			/* wep default key has not been set, so use this key index as default key.*/
+
+			wep_key_len = wep_key_len <= 5 ? 5 : 13;
+
+			psecuritypriv->ndisencryptstatus = Ndis802_11Encryption1Enabled;
+			psecuritypriv->dot11PrivacyAlgrthm = _WEP40_;
+			psecuritypriv->dot118021XGrpPrivacy = _WEP40_;
+
+			if (wep_key_len == 13) {
+				psecuritypriv->dot11PrivacyAlgrthm = _WEP104_;
+				psecuritypriv->dot118021XGrpPrivacy = _WEP104_;
+			}
+
+			psecuritypriv->dot11PrivacyKeyIndex = wep_key_idx;
+		}
+
+		_rtw_memcpy(&(psecuritypriv->dot11DefKey[wep_key_idx].skey[0]), param->u.crypt.key, wep_key_len);
+
+		psecuritypriv->dot11DefKeylen[wep_key_idx] = wep_key_len;
+
+		psecuritypriv->key_mask |= BIT(wep_key_idx);
+
+		padapter->mlmeextpriv.mlmext_info.key_index = wep_key_idx;
+		goto exit;
+	}
+
+	if (padapter->securitypriv.dot11AuthAlgrthm == dot11AuthAlgrthm_8021X) { /* 802_1x */
+		struct sta_info *psta, *pbcmc_sta;
+		struct sta_priv *pstapriv = &padapter->stapriv;
+
+		if (check_fwstate(pmlmepriv, WIFI_STATION_STATE | WIFI_MP_STATE) == _TRUE) { /* sta mode */
+			psta = rtw_get_stainfo(pstapriv, get_bssid(pmlmepriv));
+			if (psta == NULL) {
+				/* DEBUG_ERR( ("Set wpa_set_encryption: Obtain Sta_info fail\n")); */
+			} else {
+				/* Jeff: don't disable ieee8021x_blocked while clearing key */
+				if (strcmp(param->u.crypt.alg, "none") != 0)
+					psta->ieee8021x_blocked = _FALSE;
+
+				if ((padapter->securitypriv.ndisencryptstatus == Ndis802_11Encryption2Enabled) ||
+				    (padapter->securitypriv.ndisencryptstatus ==  Ndis802_11Encryption3Enabled))
+					psta->dot118021XPrivacy = padapter->securitypriv.dot11PrivacyAlgrthm;
+
+				if (param->u.crypt.set_tx == 1) { /* pairwise key */
+					RTW_INFO(FUNC_ADPT_FMT" set %s PTK idx:%u, len:%u\n"
+						, FUNC_ADPT_ARG(padapter), param->u.crypt.alg, param->u.crypt.idx, param->u.crypt.key_len);
+					_rtw_memcpy(psta->dot118021x_UncstKey.skey,  param->u.crypt.key, (param->u.crypt.key_len > 16 ? 16 : param->u.crypt.key_len));
+					if (strcmp(param->u.crypt.alg, "TKIP") == 0) { /* set mic key */
+						_rtw_memcpy(psta->dot11tkiptxmickey.skey, &(param->u.crypt.key[16]), 8);
+						_rtw_memcpy(psta->dot11tkiprxmickey.skey, &(param->u.crypt.key[24]), 8);
+						padapter->securitypriv.busetkipkey = _FALSE;
+					}
+					psta->dot11txpn.val = RTW_GET_LE64(param->u.crypt.seq);
+					psta->dot11rxpn.val = RTW_GET_LE64(param->u.crypt.seq);
+					psta->bpairwise_key_installed = _TRUE;
+					rtw_setstakey_cmd(padapter, psta, UNICAST_KEY, _TRUE);
+
+				} else { /* group key */
+					if (strcmp(param->u.crypt.alg, "TKIP") == 0 || strcmp(param->u.crypt.alg, "CCMP") == 0) {
+						RTW_INFO(FUNC_ADPT_FMT" set %s GTK idx:%u, len:%u\n"
+							, FUNC_ADPT_ARG(padapter), param->u.crypt.alg, param->u.crypt.idx, param->u.crypt.key_len);
+						_rtw_memcpy(padapter->securitypriv.dot118021XGrpKey[param->u.crypt.idx].skey,  param->u.crypt.key,
+							(param->u.crypt.key_len > 16 ? 16 : param->u.crypt.key_len));
+						/* only TKIP group key need to install this */
+						if (param->u.crypt.key_len > 16) {
+							_rtw_memcpy(padapter->securitypriv.dot118021XGrptxmickey[param->u.crypt.idx].skey, &(param->u.crypt.key[16]), 8);
+							_rtw_memcpy(padapter->securitypriv.dot118021XGrprxmickey[param->u.crypt.idx].skey, &(param->u.crypt.key[24]), 8);
+						}
+						padapter->securitypriv.binstallGrpkey = _TRUE;
+						if (param->u.crypt.idx < 4)
+							_rtw_memcpy(padapter->securitypriv.iv_seq[param->u.crypt.idx], param->u.crypt.seq, 8);
+						padapter->securitypriv.dot118021XGrpKeyid = param->u.crypt.idx;
+						rtw_set_key(padapter, &padapter->securitypriv, param->u.crypt.idx, 1, _TRUE);
+
+					#ifdef CONFIG_IEEE80211W
+					} else if (strcmp(param->u.crypt.alg, "BIP") == 0) {
+						RTW_INFO(FUNC_ADPT_FMT" set IGTK idx:%u, len:%u\n"
+							, FUNC_ADPT_ARG(padapter), param->u.crypt.idx, param->u.crypt.key_len);
+						_rtw_memcpy(padapter->securitypriv.dot11wBIPKey[param->u.crypt.idx].skey,  param->u.crypt.key,
+							(param->u.crypt.key_len > 16 ? 16 : param->u.crypt.key_len));
+						psecuritypriv->dot11wBIPKeyid = param->u.crypt.idx;
+						psecuritypriv->dot11wBIPrxpn.val = RTW_GET_LE64(param->u.crypt.seq);
+						psecuritypriv->binstallBIPkey = _TRUE;
+					#endif /* CONFIG_IEEE80211W */
+
+					}
+
+#ifdef CONFIG_P2P
+					if (rtw_p2p_chk_state(pwdinfo, P2P_STATE_PROVISIONING_ING))
+						rtw_p2p_set_state(pwdinfo, P2P_STATE_PROVISIONING_DONE);
+#endif /* CONFIG_P2P */
+
+					/* WPA/WPA2 key-handshake has completed */
+					clr_fwstate(pmlmepriv, WIFI_UNDER_KEY_HANDSHAKE);
+				}
+			}
+
+			pbcmc_sta = rtw_get_bcmc_stainfo(padapter);
+			if (pbcmc_sta == NULL) {
+				/* DEBUG_ERR( ("Set OID_802_11_ADD_KEY: bcmc stainfo is null\n")); */
+			} else {
+				/* Jeff: don't disable ieee8021x_blocked while clearing key */
+				if (strcmp(param->u.crypt.alg, "none") != 0)
+					pbcmc_sta->ieee8021x_blocked = _FALSE;
+
+				if ((padapter->securitypriv.ndisencryptstatus == Ndis802_11Encryption2Enabled) ||
+				    (padapter->securitypriv.ndisencryptstatus ==  Ndis802_11Encryption3Enabled))
+					pbcmc_sta->dot118021XPrivacy = padapter->securitypriv.dot11PrivacyAlgrthm;
+			}
+		} else if (check_fwstate(pmlmepriv, WIFI_ADHOC_STATE)) { /* adhoc mode */
+		}
+	}
+
+#ifdef CONFIG_WAPI_SUPPORT
+	if (strcmp(param->u.crypt.alg, "SMS4") == 0)
+		rtw_wapi_set_set_encryption(padapter, param);
+#endif
+
+exit:
+
+
+	return ret;
+}
+
+static int rtw_set_wpa_ie(_adapter *padapter, char *pie, unsigned short ielen)
+{
+	u8 *buf = NULL, *pos = NULL;
+	int group_cipher = 0, pairwise_cipher = 0;
+	u8 mfp_opt = MFP_NO;
+	int ret = 0;
+	u8 null_addr[] = {0, 0, 0, 0, 0, 0};
+#ifdef CONFIG_P2P
+	struct wifidirect_info *pwdinfo = &padapter->wdinfo;
+#endif /* CONFIG_P2P */
+
+	if ((ielen > MAX_WPA_IE_LEN) || (pie == NULL)) {
+		_clr_fwstate_(&padapter->mlmepriv, WIFI_UNDER_WPS);
+		if (pie == NULL)
+			return ret;
+		else
+			return -EINVAL;
+	}
+
+	if (ielen) {
+		buf = rtw_zmalloc(ielen);
+		if (buf == NULL) {
+			ret =  -ENOMEM;
+			goto exit;
+		}
+
+		_rtw_memcpy(buf, pie , ielen);
+
+		/* dump */
+		{
+			int i;
+			RTW_INFO("\n wpa_ie(length:%d):\n", ielen);
+			for (i = 0; i < ielen; i = i + 8)
+				RTW_INFO("0x%.2x 0x%.2x 0x%.2x 0x%.2x 0x%.2x 0x%.2x 0x%.2x 0x%.2x\n", buf[i], buf[i + 1], buf[i + 2], buf[i + 3], buf[i + 4], buf[i + 5], buf[i + 6], buf[i + 7]);
+		}
+
+		pos = buf;
+		if (ielen < RSN_HEADER_LEN) {
+			ret  = -1;
+			goto exit;
+		}
+
+		if (rtw_parse_wpa_ie(buf, ielen, &group_cipher, &pairwise_cipher, NULL) == _SUCCESS) {
+			padapter->securitypriv.dot11AuthAlgrthm = dot11AuthAlgrthm_8021X;
+			padapter->securitypriv.ndisauthtype = Ndis802_11AuthModeWPAPSK;
+			_rtw_memcpy(padapter->securitypriv.supplicant_ie, &buf[0], ielen);
+		}
+
+		if (rtw_parse_wpa2_ie(buf, ielen, &group_cipher, &pairwise_cipher, NULL, &mfp_opt) == _SUCCESS) {
+			padapter->securitypriv.dot11AuthAlgrthm = dot11AuthAlgrthm_8021X;
+			padapter->securitypriv.ndisauthtype = Ndis802_11AuthModeWPA2PSK;
+			_rtw_memcpy(padapter->securitypriv.supplicant_ie, &buf[0], ielen);
+		}
+
+		if (group_cipher == 0)
+			group_cipher = WPA_CIPHER_NONE;
+		if (pairwise_cipher == 0)
+			pairwise_cipher = WPA_CIPHER_NONE;
+
+		switch (group_cipher) {
+		case WPA_CIPHER_NONE:
+			padapter->securitypriv.dot118021XGrpPrivacy = _NO_PRIVACY_;
+			padapter->securitypriv.ndisencryptstatus = Ndis802_11EncryptionDisabled;
+			break;
+		case WPA_CIPHER_WEP40:
+			padapter->securitypriv.dot118021XGrpPrivacy = _WEP40_;
+			padapter->securitypriv.ndisencryptstatus = Ndis802_11Encryption1Enabled;
+			break;
+		case WPA_CIPHER_TKIP:
+			padapter->securitypriv.dot118021XGrpPrivacy = _TKIP_;
+			padapter->securitypriv.ndisencryptstatus = Ndis802_11Encryption2Enabled;
+			break;
+		case WPA_CIPHER_CCMP:
+			padapter->securitypriv.dot118021XGrpPrivacy = _AES_;
+			padapter->securitypriv.ndisencryptstatus = Ndis802_11Encryption3Enabled;
+			break;
+		case WPA_CIPHER_WEP104:
+			padapter->securitypriv.dot118021XGrpPrivacy = _WEP104_;
+			padapter->securitypriv.ndisencryptstatus = Ndis802_11Encryption1Enabled;
+			break;
+		}
+
+		switch (pairwise_cipher) {
+		case WPA_CIPHER_NONE:
+			padapter->securitypriv.dot11PrivacyAlgrthm = _NO_PRIVACY_;
+			padapter->securitypriv.ndisencryptstatus = Ndis802_11EncryptionDisabled;
+			break;
+		case WPA_CIPHER_WEP40:
+			padapter->securitypriv.dot11PrivacyAlgrthm = _WEP40_;
+			padapter->securitypriv.ndisencryptstatus = Ndis802_11Encryption1Enabled;
+			break;
+		case WPA_CIPHER_TKIP:
+			padapter->securitypriv.dot11PrivacyAlgrthm = _TKIP_;
+			padapter->securitypriv.ndisencryptstatus = Ndis802_11Encryption2Enabled;
+			break;
+		case WPA_CIPHER_CCMP:
+			padapter->securitypriv.dot11PrivacyAlgrthm = _AES_;
+			padapter->securitypriv.ndisencryptstatus = Ndis802_11Encryption3Enabled;
+			break;
+		case WPA_CIPHER_WEP104:
+			padapter->securitypriv.dot11PrivacyAlgrthm = _WEP104_;
+			padapter->securitypriv.ndisencryptstatus = Ndis802_11Encryption1Enabled;
+			break;
+		}
+
+		if (mfp_opt == MFP_INVALID) {
+			RTW_INFO(FUNC_ADPT_FMT" invalid MFP setting\n", FUNC_ADPT_ARG(padapter));
+			ret = -EINVAL;
+			goto exit;
+		}
+		padapter->securitypriv.mfp_opt = mfp_opt;
+
+		_clr_fwstate_(&padapter->mlmepriv, WIFI_UNDER_WPS);
+		{/* set wps_ie	 */
+			u16 cnt = 0;
+			u8 eid, wps_oui[4] = {0x0, 0x50, 0xf2, 0x04};
+
+			while (cnt < ielen) {
+				eid = buf[cnt];
+
+				if ((eid == _VENDOR_SPECIFIC_IE_) && (_rtw_memcmp(&buf[cnt + 2], wps_oui, 4) == _TRUE)) {
+					RTW_INFO("SET WPS_IE\n");
+
+					padapter->securitypriv.wps_ie_len = ((buf[cnt + 1] + 2) < MAX_WPS_IE_LEN) ? (buf[cnt + 1] + 2) : MAX_WPS_IE_LEN;
+
+					_rtw_memcpy(padapter->securitypriv.wps_ie, &buf[cnt], padapter->securitypriv.wps_ie_len);
+
+					set_fwstate(&padapter->mlmepriv, WIFI_UNDER_WPS);
+
+#ifdef CONFIG_P2P
+					if (rtw_p2p_chk_state(pwdinfo, P2P_STATE_GONEGO_OK))
+						rtw_p2p_set_state(pwdinfo, P2P_STATE_PROVISIONING_ING);
+#endif /* CONFIG_P2P */
+					cnt += buf[cnt + 1] + 2;
+
+					break;
+				} else {
+					cnt += buf[cnt + 1] + 2; /* goto next	 */
+				}
+			}
+		}
+	}
+
+	/* TKIP and AES disallow multicast packets until installing group key */
+	if (padapter->securitypriv.dot11PrivacyAlgrthm == _TKIP_
+	    || padapter->securitypriv.dot11PrivacyAlgrthm == _TKIP_WTMIC_
+	    || padapter->securitypriv.dot11PrivacyAlgrthm == _AES_)
+		/* WPS open need to enable multicast
+		 * || check_fwstate(&padapter->mlmepriv, WIFI_UNDER_WPS) == _TRUE) */
+		rtw_hal_set_hwreg(padapter, HW_VAR_OFF_RCR_AM, null_addr);
+
+
+exit:
+
+	if (buf)
+		rtw_mfree(buf, ielen);
+
+	return ret;
+}
+
+static int rtw_wx_get_name(struct net_device *dev,
+			   struct iw_request_info *info,
+			   union iwreq_data *wrqu, char *extra)
+{
+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
+	u32 ht_ielen = 0;
+	char *p;
+	u8 ht_cap = _FALSE, vht_cap = _FALSE;
+	struct	mlme_priv	*pmlmepriv = &(padapter->mlmepriv);
+	WLAN_BSSID_EX  *pcur_bss = &pmlmepriv->cur_network.network;
+	NDIS_802_11_RATES_EX *prates = NULL;
+
+
+
+	if (check_fwstate(pmlmepriv, _FW_LINKED | WIFI_ADHOC_MASTER_STATE) == _TRUE) {
+		/* parsing HT_CAP_IE */
+		if( is_supported_ht(padapter->registrypriv.wireless_mode)&&(padapter->registrypriv.ht_enable)) {
+			p = rtw_get_ie(&pcur_bss->IEs[12], _HT_CAPABILITY_IE_, &ht_ielen, pcur_bss->IELength - 12);
+			if (p && ht_ielen > 0 )
+				ht_cap = _TRUE;
+		}
+#ifdef CONFIG_80211AC_VHT
+		if ((padapter->registrypriv.wireless_mode & WIRELESS_11AC) &&
+			(pmlmepriv->vhtpriv.vht_option == _TRUE))
+			vht_cap = _TRUE;
+#endif
+
+		prates = &pcur_bss->SupportedRates;
+		if (rtw_is_cckratesonly_included((u8 *)prates) == _TRUE) {
+			if (ht_cap == _TRUE)
+				snprintf(wrqu->name, IFNAMSIZ, "IEEE 802.11bn");
+			else
+				snprintf(wrqu->name, IFNAMSIZ, "IEEE 802.11b");
+		} else if ((rtw_is_cckrates_included((u8 *)prates)) == _TRUE) {
+			if (ht_cap == _TRUE)
+				snprintf(wrqu->name, IFNAMSIZ, "IEEE 802.11bgn");
+			else {
+				if(padapter->registrypriv.wireless_mode & WIRELESS_11G)
+					snprintf(wrqu->name, IFNAMSIZ, "IEEE 802.11bg");
+				else
+					snprintf(wrqu->name, IFNAMSIZ, "IEEE 802.11b");
+			}
+		} else {
+			if (pcur_bss->Configuration.DSConfig > 14) {
+#ifdef CONFIG_80211AC_VHT
+				if (vht_cap == _TRUE)
+					snprintf(wrqu->name, IFNAMSIZ, "IEEE 802.11AC");
+				else
+#endif
+				{
+					if (ht_cap == _TRUE)
+						snprintf(wrqu->name, IFNAMSIZ, "IEEE 802.11an");
+					else
+						snprintf(wrqu->name, IFNAMSIZ, "IEEE 802.11a");
+				}
+			} else {
+				if (ht_cap == _TRUE)
+					snprintf(wrqu->name, IFNAMSIZ, "IEEE 802.11gn");
+				else
+					snprintf(wrqu->name, IFNAMSIZ, "IEEE 802.11g");
+			}
+		}
+	} else {
+		/* prates = &padapter->registrypriv.dev_network.SupportedRates; */
+		/* snprintf(wrqu->name, IFNAMSIZ, "IEEE 802.11g"); */
+		snprintf(wrqu->name, IFNAMSIZ, "unassociated");
+	}
+
+
+	return 0;
+}
+
+static int rtw_wx_set_freq(struct net_device *dev,
+			   struct iw_request_info *info,
+			   union iwreq_data *wrqu, char *extra)
+{
+
+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
+	int exp = 1, freq = 0, div = 0;
+
+	rtw_ps_deny(padapter, PS_DENY_IOCTL);
+	if (rtw_pwr_wakeup(padapter) == _FALSE)
+		goto exit;
+	if (wrqu->freq.m <= 1000) {
+		if (wrqu->freq.flags == IW_FREQ_AUTO) {
+			if (rtw_chset_search_ch(adapter_to_chset(padapter), wrqu->freq.m) > 0) {
+				padapter->mlmeextpriv.cur_channel = wrqu->freq.m;
+				RTW_INFO("%s: channel is auto, set to channel %d\n", __func__, wrqu->freq.m);
+			} else {
+				padapter->mlmeextpriv.cur_channel = 1;
+				RTW_INFO("%s: channel is auto, Channel Plan don't match just set to channel 1\n", __func__);
+			}
+		} else {
+			padapter->mlmeextpriv.cur_channel = wrqu->freq.m;
+			RTW_INFO("%s: set to channel %d\n", __func__, padapter->mlmeextpriv.cur_channel);
+		}
+	} else {
+		while (wrqu->freq.e) {
+			exp *= 10;
+			wrqu->freq.e--;
+		}
+
+		freq = wrqu->freq.m;
+
+		while (!(freq % 10)) {
+			freq /= 10;
+			exp *= 10;
+		}
+
+		/* freq unit is MHz here */
+		div = 1000000 / exp;
+
+		if (div)
+			freq /= div;
+		else {
+			div = exp / 1000000;
+			freq *= div;
+		}
+
+		/* If freq is invalid, rtw_freq2ch() will return channel 1 */
+		padapter->mlmeextpriv.cur_channel = rtw_freq2ch(freq);
+		RTW_INFO("%s: set to channel %d\n", __func__, padapter->mlmeextpriv.cur_channel);
+	}
+	set_channel_bwmode(padapter, padapter->mlmeextpriv.cur_channel, HAL_PRIME_CHNL_OFFSET_DONT_CARE, CHANNEL_WIDTH_20);
+exit:
+	rtw_ps_deny_cancel(padapter, PS_DENY_IOCTL);
+
+	return 0;
+}
+
+static int rtw_wx_get_freq(struct net_device *dev,
+			   struct iw_request_info *info,
+			   union iwreq_data *wrqu, char *extra)
+{
+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
+	struct	mlme_priv	*pmlmepriv = &(padapter->mlmepriv);
+	WLAN_BSSID_EX  *pcur_bss = &pmlmepriv->cur_network.network;
+
+	if (check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE && check_fwstate(pmlmepriv, WIFI_MONITOR_STATE) != _TRUE) {
+
+		wrqu->freq.m = rtw_ch2freq(pcur_bss->Configuration.DSConfig) * 100000;
+		wrqu->freq.e = 1;
+		wrqu->freq.i = pcur_bss->Configuration.DSConfig;
+
+	} else {
+		wrqu->freq.m = rtw_ch2freq(padapter->mlmeextpriv.cur_channel) * 100000;
+		wrqu->freq.e = 1;
+		wrqu->freq.i = padapter->mlmeextpriv.cur_channel;
+	}
+
+	return 0;
+}
+
+static int rtw_wx_set_mode(struct net_device *dev, struct iw_request_info *a,
+			   union iwreq_data *wrqu, char *b)
+{
+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
+	struct	mlme_priv	*pmlmepriv = &(padapter->mlmepriv);
+	NDIS_802_11_NETWORK_INFRASTRUCTURE networkType ;
+	int ret = 0;
+
+
+	if (_FAIL == rtw_pwr_wakeup(padapter)) {
+		ret = -EPERM;
+		goto exit;
+	}
+
+	if (!rtw_is_hw_init_completed(padapter)) {
+		ret = -EPERM;
+		goto exit;
+	}
+
+	/* initial default type */
+	dev->type = ARPHRD_ETHER;
+
+	if (wrqu->mode == IW_MODE_MONITOR) {
+		rtw_ps_deny(padapter, PS_DENY_MONITOR_MODE);
+		LeaveAllPowerSaveMode(padapter);
+	} else {
+		rtw_ps_deny_cancel(padapter, PS_DENY_MONITOR_MODE);
+	}
+
+	switch (wrqu->mode) {
+	case IW_MODE_MONITOR:
+		networkType = Ndis802_11Monitor;
+#if 0
+		dev->type = ARPHRD_IEEE80211; /* IEEE 802.11 : 801 */
+#endif
+
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 24))
+		dev->type = ARPHRD_IEEE80211_RADIOTAP; /* IEEE 802.11 + radiotap header : 803 */
+		RTW_INFO("set_mode = IW_MODE_MONITOR\n");
+#else
+		RTW_INFO("kernel version < 2.6.24 not support IW_MODE_MONITOR\n");
+#endif
+		break;
+
+	case IW_MODE_AUTO:
+		networkType = Ndis802_11AutoUnknown;
+		RTW_INFO("set_mode = IW_MODE_AUTO\n");
+		break;
+	case IW_MODE_ADHOC:
+		networkType = Ndis802_11IBSS;
+		RTW_INFO("set_mode = IW_MODE_ADHOC\n");
+		break;
+	case IW_MODE_MASTER:
+		networkType = Ndis802_11APMode;
+		RTW_INFO("set_mode = IW_MODE_MASTER\n");
+		break;
+	case IW_MODE_INFRA:
+		networkType = Ndis802_11Infrastructure;
+		RTW_INFO("set_mode = IW_MODE_INFRA\n");
+		break;
+
+	default:
+		ret = -EINVAL;;
+		goto exit;
+	}
+
+	if (rtw_set_802_11_infrastructure_mode(padapter, networkType) == _FALSE) {
+
+		ret = -EPERM;
+		goto exit;
+
+	}
+
+	rtw_setopmode_cmd(padapter, networkType, RTW_CMDF_WAIT_ACK);
+
+	if (check_fwstate(pmlmepriv, WIFI_MONITOR_STATE) == _TRUE)
+		rtw_indicate_connect(padapter);
+
+exit:
+
+
+	return ret;
+
+}
+
+static int rtw_wx_get_mode(struct net_device *dev, struct iw_request_info *a,
+			   union iwreq_data *wrqu, char *b)
+{
+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
+	struct	mlme_priv	*pmlmepriv = &(padapter->mlmepriv);
+
+
+
+	if (check_fwstate(pmlmepriv, WIFI_STATION_STATE) == _TRUE)
+		wrqu->mode = IW_MODE_INFRA;
+	else if ((check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE) == _TRUE) ||
+		 (check_fwstate(pmlmepriv, WIFI_ADHOC_STATE) == _TRUE))
+
+		wrqu->mode = IW_MODE_ADHOC;
+	else if (check_fwstate(pmlmepriv, WIFI_AP_STATE) == _TRUE)
+		wrqu->mode = IW_MODE_MASTER;
+	else if (check_fwstate(pmlmepriv, WIFI_MONITOR_STATE) == _TRUE)
+		wrqu->mode = IW_MODE_MONITOR;
+	else
+		wrqu->mode = IW_MODE_AUTO;
+
+
+	return 0;
+
+}
+
+
+static int rtw_wx_set_pmkid(struct net_device *dev,
+			    struct iw_request_info *a,
+			    union iwreq_data *wrqu, char *extra)
+{
+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
+	u8          j, blInserted = _FALSE;
+	int         intReturn = _FALSE;
+	struct security_priv *psecuritypriv = &padapter->securitypriv;
+	struct iw_pmksa  *pPMK = (struct iw_pmksa *) extra;
+	u8     strZeroMacAddress[ETH_ALEN] = { 0x00 };
+	u8     strIssueBssid[ETH_ALEN] = { 0x00 };
+
+#if 0
+	struct iw_pmksa {
+		__u32   cmd;
+		struct sockaddr bssid;
+		__u8    pmkid[IW_PMKID_LEN];   /* IW_PMKID_LEN=16 */
+	}
+	There are the BSSID information in the bssid.sa_data array.
+	If cmd is IW_PMKSA_FLUSH, it means the wpa_suppplicant wants to clear all the PMKID information.
+	If cmd is IW_PMKSA_ADD, it means the wpa_supplicant wants to add a PMKID / BSSID to driver.
+	If cmd is IW_PMKSA_REMOVE, it means the wpa_supplicant wants to remove a PMKID / BSSID from driver.
+#endif
+
+	_rtw_memcpy(strIssueBssid, pPMK->bssid.sa_data, ETH_ALEN);
+	if (pPMK->cmd == IW_PMKSA_ADD) {
+		RTW_INFO("[rtw_wx_set_pmkid] IW_PMKSA_ADD!\n");
+		if (_rtw_memcmp(strIssueBssid, strZeroMacAddress, ETH_ALEN) == _TRUE)
+			return intReturn ;
+		else
+			intReturn = _TRUE;
+		blInserted = _FALSE;
+
+		/* overwrite PMKID */
+		for (j = 0 ; j < NUM_PMKID_CACHE; j++) {
+			if (_rtw_memcmp(psecuritypriv->PMKIDList[j].Bssid, strIssueBssid, ETH_ALEN) == _TRUE) {
+				/* BSSID is matched, the same AP => rewrite with new PMKID. */
+
+				RTW_INFO("[rtw_wx_set_pmkid] BSSID exists in the PMKList.\n");
+
+				_rtw_memcpy(psecuritypriv->PMKIDList[j].PMKID, pPMK->pmkid, IW_PMKID_LEN);
+				psecuritypriv->PMKIDList[j].bUsed = _TRUE;
+				psecuritypriv->PMKIDIndex = j + 1;
+				blInserted = _TRUE;
+				break;
+			}
+		}
+
+		if (!blInserted) {
+			/* Find a new entry */
+			RTW_INFO("[rtw_wx_set_pmkid] Use the new entry index = %d for this PMKID.\n",
+				 psecuritypriv->PMKIDIndex);
+
+			_rtw_memcpy(psecuritypriv->PMKIDList[psecuritypriv->PMKIDIndex].Bssid, strIssueBssid, ETH_ALEN);
+			_rtw_memcpy(psecuritypriv->PMKIDList[psecuritypriv->PMKIDIndex].PMKID, pPMK->pmkid, IW_PMKID_LEN);
+
+			psecuritypriv->PMKIDList[psecuritypriv->PMKIDIndex].bUsed = _TRUE;
+			psecuritypriv->PMKIDIndex++ ;
+			if (psecuritypriv->PMKIDIndex == 16)
+				psecuritypriv->PMKIDIndex = 0;
+		}
+	} else if (pPMK->cmd == IW_PMKSA_REMOVE) {
+		RTW_INFO("[rtw_wx_set_pmkid] IW_PMKSA_REMOVE!\n");
+		intReturn = _TRUE;
+		for (j = 0 ; j < NUM_PMKID_CACHE; j++) {
+			if (_rtw_memcmp(psecuritypriv->PMKIDList[j].Bssid, strIssueBssid, ETH_ALEN) == _TRUE) {
+				/* BSSID is matched, the same AP => Remove this PMKID information and reset it. */
+				_rtw_memset(psecuritypriv->PMKIDList[j].Bssid, 0x00, ETH_ALEN);
+				psecuritypriv->PMKIDList[j].bUsed = _FALSE;
+				break;
+			}
+		}
+	} else if (pPMK->cmd == IW_PMKSA_FLUSH) {
+		RTW_INFO("[rtw_wx_set_pmkid] IW_PMKSA_FLUSH!\n");
+		_rtw_memset(&psecuritypriv->PMKIDList[0], 0x00, sizeof(RT_PMKID_LIST) * NUM_PMKID_CACHE);
+		psecuritypriv->PMKIDIndex = 0;
+		intReturn = _TRUE;
+	}
+	return intReturn ;
+}
+
+static int rtw_wx_get_sens(struct net_device *dev,
+			   struct iw_request_info *info,
+			   union iwreq_data *wrqu, char *extra)
+{
+#ifdef CONFIG_PLATFORM_ROCKCHIPS
+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
+	struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
+
+	/*
+	*  20110311 Commented by Jeff
+	*  For rockchip platform's wpa_driver_wext_get_rssi
+	*/
+	if (check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE) {
+		/* wrqu->sens.value=-padapter->recvpriv.signal_strength; */
+		wrqu->sens.value = -padapter->recvpriv.rssi;
+		/* RTW_INFO("%s: %d\n", __FUNCTION__, wrqu->sens.value); */
+		wrqu->sens.fixed = 0; /* no auto select */
+	} else
+#endif
+	{
+		wrqu->sens.value = 0;
+		wrqu->sens.fixed = 0;	/* no auto select */
+		wrqu->sens.disabled = 1;
+	}
+	return 0;
+}
+
+static int rtw_wx_get_range(struct net_device *dev,
+			    struct iw_request_info *info,
+			    union iwreq_data *wrqu, char *extra)
+{
+	struct iw_range *range = (struct iw_range *)extra;
+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
+	struct rf_ctl_t *rfctl = adapter_to_rfctl(padapter);
+	u16 val;
+	int i;
+
+
+
+	wrqu->data.length = sizeof(*range);
+	_rtw_memset(range, 0, sizeof(*range));
+
+	/* Let's try to keep this struct in the same order as in
+	 * linux/include/wireless.h
+	 */
+
+	/* TODO: See what values we can set, and remove the ones we can't
+	 * set, or fill them with some default data.
+	 */
+
+	/* ~5 Mb/s real (802.11b) */
+	range->throughput = 5 * 1000 * 1000;
+
+	/* TODO: Not used in 802.11b?
+	*	range->min_nwid;	 Minimal NWID we are able to set  */
+	/* TODO: Not used in 802.11b?
+	*	range->max_nwid;	 Maximal NWID we are able to set  */
+
+	/* Old Frequency (backward compat - moved lower ) */
+	/*	range->old_num_channels;
+	 *	range->old_num_frequency;
+	 * 	range->old_freq[6];  Filler to keep "version" at the same offset  */
+
+	/* signal level threshold range */
+
+	/* Quality of link & SNR stuff */
+	/* Quality range (link, level, noise)
+	 * If the quality is absolute, it will be in the range [0 ; max_qual],
+	 * if the quality is dBm, it will be in the range [max_qual ; 0].
+	 * Don't forget that we use 8 bit arithmetics...
+	 *
+	 * If percentage range is 0~100
+	 * Signal strength dbm range logical is -100 ~ 0
+	 * but usually value is -90 ~ -20
+	 */
+	range->max_qual.qual = 100;
+#ifdef CONFIG_SIGNAL_DISPLAY_DBM
+	range->max_qual.level = (u8)-100;
+	range->max_qual.noise = (u8)-100;
+	range->max_qual.updated = IW_QUAL_ALL_UPDATED; /* Updated all three */
+	range->max_qual.updated |= IW_QUAL_DBM;
+#else /* !CONFIG_SIGNAL_DISPLAY_DBM */
+	/* percent values between 0 and 100. */
+	range->max_qual.level = 100;
+	range->max_qual.noise = 100;
+	range->max_qual.updated = IW_QUAL_ALL_UPDATED; /* Updated all three */
+#endif /* !CONFIG_SIGNAL_DISPLAY_DBM */
+
+	/* This should contain the average/typical values of the quality
+	 * indicator. This should be the threshold between a "good" and
+	 * a "bad" link (example : monitor going from green to orange).
+	 * Currently, user space apps like quality monitors don't have any
+	 * way to calibrate the measurement. With this, they can split
+	 * the range between 0 and max_qual in different quality level
+	 * (using a geometric subdivision centered on the average).
+	 * I expect that people doing the user space apps will feedback
+	 * us on which value we need to put in each driver... */
+	range->avg_qual.qual = 92; /* > 8% missed beacons is 'bad' */
+#ifdef CONFIG_SIGNAL_DISPLAY_DBM
+	/* TODO: Find real 'good' to 'bad' threshold value for RSSI */
+	range->avg_qual.level = (u8)-70;
+	range->avg_qual.noise = 0;
+	range->avg_qual.updated = IW_QUAL_ALL_UPDATED; /* Updated all three */
+	range->avg_qual.updated |= IW_QUAL_DBM;
+#else /* !CONFIG_SIGNAL_DISPLAY_DBM */
+	/* TODO: Find real 'good' to 'bad' threshol value for RSSI */
+	range->avg_qual.level = 30;
+	range->avg_qual.noise = 100;
+	range->avg_qual.updated = IW_QUAL_ALL_UPDATED; /* Updated all three */
+#endif /* !CONFIG_SIGNAL_DISPLAY_DBM */
+
+	range->num_bitrates = RATE_COUNT;
+
+	for (i = 0; i < RATE_COUNT && i < IW_MAX_BITRATES; i++)
+		range->bitrate[i] = rtw_rates[i];
+
+	range->min_frag = MIN_FRAG_THRESHOLD;
+	range->max_frag = MAX_FRAG_THRESHOLD;
+
+	range->pm_capa = 0;
+
+	range->we_version_compiled = WIRELESS_EXT;
+	range->we_version_source = 16;
+
+	/*	range->retry_capa;	 What retry options are supported
+	 *	range->retry_flags;	 How to decode max/min retry limit
+	 *	range->r_time_flags;	 How to decode max/min retry life
+	 *	range->min_retry;	 Minimal number of retries
+	 *	range->max_retry;	 Maximal number of retries
+	 *	range->min_r_time;	 Minimal retry lifetime
+	 *	range->max_r_time;	 Maximal retry lifetime  */
+
+	for (i = 0, val = 0; i < rfctl->max_chan_nums; i++) {
+
+		/* Include only legal frequencies for some countries */
+		if (rfctl->channel_set[i].ChannelNum != 0) {
+			range->freq[val].i = rfctl->channel_set[i].ChannelNum;
+			range->freq[val].m = rtw_ch2freq(rfctl->channel_set[i].ChannelNum) * 100000;
+			range->freq[val].e = 1;
+			val++;
+		}
+
+		if (val == IW_MAX_FREQUENCIES)
+			break;
+	}
+
+	range->num_channels = val;
+	range->num_frequency = val;
+
+	/* Commented by Albert 2009/10/13
+	 * The following code will proivde the security capability to network manager.
+	 * If the driver doesn't provide this capability to network manager,
+	 * the WPA/WPA2 routers can't be choosen in the network manager. */
+
+	/*
+	#define IW_SCAN_CAPA_NONE		0x00
+	#define IW_SCAN_CAPA_ESSID		0x01
+	#define IW_SCAN_CAPA_BSSID		0x02
+	#define IW_SCAN_CAPA_CHANNEL	0x04
+	#define IW_SCAN_CAPA_MODE		0x08
+	#define IW_SCAN_CAPA_RATE		0x10
+	#define IW_SCAN_CAPA_TYPE		0x20
+	#define IW_SCAN_CAPA_TIME		0x40
+	*/
+
+#if WIRELESS_EXT > 17
+	range->enc_capa = IW_ENC_CAPA_WPA | IW_ENC_CAPA_WPA2 |
+			  IW_ENC_CAPA_CIPHER_TKIP | IW_ENC_CAPA_CIPHER_CCMP;
+#endif
+
+#ifdef IW_SCAN_CAPA_ESSID /* WIRELESS_EXT > 21 */
+	range->scan_capa = IW_SCAN_CAPA_ESSID | IW_SCAN_CAPA_TYPE | IW_SCAN_CAPA_BSSID |
+		   IW_SCAN_CAPA_CHANNEL | IW_SCAN_CAPA_MODE | IW_SCAN_CAPA_RATE;
+#endif
+
+
+
+	return 0;
+
+}
+
+/* set bssid flow
+ * s1. rtw_set_802_11_infrastructure_mode()
+ * s2. rtw_set_802_11_authentication_mode()
+ * s3. set_802_11_encryption_mode()
+ * s4. rtw_set_802_11_bssid() */
+static int rtw_wx_set_wap(struct net_device *dev,
+			  struct iw_request_info *info,
+			  union iwreq_data *awrq,
+			  char *extra)
+{
+	_irqL	irqL;
+	uint ret = 0;
+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
+	struct sockaddr *temp = (struct sockaddr *)awrq;
+	struct	mlme_priv	*pmlmepriv = &(padapter->mlmepriv);
+	_list	*phead;
+	u8 *dst_bssid, *src_bssid;
+	_queue	*queue	= &(pmlmepriv->scanned_queue);
+	struct	wlan_network	*pnetwork = NULL;
+	NDIS_802_11_AUTHENTICATION_MODE	authmode;
+
+	/*
+	#ifdef CONFIG_CONCURRENT_MODE
+		if(padapter->adapter_type > PRIMARY_IFACE)
+		{
+			ret = -EINVAL;
+			goto exit;
+		}
+	#endif
+	*/
+
+#ifdef CONFIG_CONCURRENT_MODE
+	if (rtw_mi_buddy_check_fwstate(padapter, _FW_UNDER_SURVEY | _FW_UNDER_LINKING) == _TRUE) {
+		RTW_INFO("set bssid, but buddy_intf is under scanning or linking\n");
+
+		ret = -EINVAL;
+
+		goto exit;
+	}
+#endif
+
+	rtw_ps_deny(padapter, PS_DENY_JOIN);
+	if (_FAIL == rtw_pwr_wakeup(padapter)) {
+		ret = -1;
+		goto cancel_ps_deny;
+	}
+
+	if (!padapter->bup) {
+		ret = -1;
+		goto cancel_ps_deny;
+	}
+
+
+	if (temp->sa_family != ARPHRD_ETHER) {
+		ret = -EINVAL;
+		goto cancel_ps_deny;
+	}
+
+	authmode = padapter->securitypriv.ndisauthtype;
+	_enter_critical_bh(&queue->lock, &irqL);
+	phead = get_list_head(queue);
+	pmlmepriv->pscanned = get_next(phead);
+
+	while (1) {
+
+		if ((rtw_end_of_queue_search(phead, pmlmepriv->pscanned)) == _TRUE) {
+#if 0
+			ret = -EINVAL;
+			goto cancel_ps_deny;
+
+			if (check_fwstate(pmlmepriv, WIFI_ADHOC_STATE) == _TRUE) {
+				rtw_set_802_11_bssid(padapter, temp->sa_data);
+				goto cancel_ps_deny;
+			} else {
+				ret = -EINVAL;
+				goto cancel_ps_deny;
+			}
+#endif
+
+			break;
+		}
+
+		pnetwork = LIST_CONTAINOR(pmlmepriv->pscanned, struct wlan_network, list);
+
+		pmlmepriv->pscanned = get_next(pmlmepriv->pscanned);
+
+		dst_bssid = pnetwork->network.MacAddress;
+
+		src_bssid = temp->sa_data;
+
+		if ((_rtw_memcmp(dst_bssid, src_bssid, ETH_ALEN)) == _TRUE) {
+			if (!rtw_set_802_11_infrastructure_mode(padapter, pnetwork->network.InfrastructureMode)) {
+				ret = -1;
+				_exit_critical_bh(&queue->lock, &irqL);
+				goto cancel_ps_deny;
+			}
+
+			break;
+		}
+
+	}
+	_exit_critical_bh(&queue->lock, &irqL);
+
+	rtw_set_802_11_authentication_mode(padapter, authmode);
+	/* set_802_11_encryption_mode(padapter, padapter->securitypriv.ndisencryptstatus); */
+	if (rtw_set_802_11_bssid(padapter, temp->sa_data) == _FALSE) {
+		ret = -1;
+		goto cancel_ps_deny;
+	}
+
+cancel_ps_deny:
+	rtw_ps_deny_cancel(padapter, PS_DENY_JOIN);
+
+exit:
+	return ret;
+}
+
+static int rtw_wx_get_wap(struct net_device *dev,
+			  struct iw_request_info *info,
+			  union iwreq_data *wrqu, char *extra)
+{
+
+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
+	struct	mlme_priv	*pmlmepriv = &(padapter->mlmepriv);
+	WLAN_BSSID_EX  *pcur_bss = &pmlmepriv->cur_network.network;
+
+	wrqu->ap_addr.sa_family = ARPHRD_ETHER;
+
+	_rtw_memset(wrqu->ap_addr.sa_data, 0, ETH_ALEN);
+
+
+
+	if (((check_fwstate(pmlmepriv, _FW_LINKED)) == _TRUE) ||
+	    ((check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE)) == _TRUE) ||
+	    ((check_fwstate(pmlmepriv, WIFI_AP_STATE)) == _TRUE))
+
+		_rtw_memcpy(wrqu->ap_addr.sa_data, pcur_bss->MacAddress, ETH_ALEN);
+	else
+		_rtw_memset(wrqu->ap_addr.sa_data, 0, ETH_ALEN);
+
+
+	return 0;
+
+}
+
+static int rtw_wx_set_mlme(struct net_device *dev,
+			   struct iw_request_info *info,
+			   union iwreq_data *wrqu, char *extra)
+{
+#if 0
+	/* SIOCSIWMLME data */
+	struct	iw_mlme {
+		__u16		cmd; /* IW_MLME_* */
+		__u16		reason_code;
+		struct sockaddr	addr;
+	};
+#endif
+
+	int ret = 0;
+	u16 reason;
+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
+	struct iw_mlme *mlme = (struct iw_mlme *) extra;
+
+
+	if (mlme == NULL)
+		return -1;
+
+	RTW_INFO("%s\n", __FUNCTION__);
+
+	reason = cpu_to_le16(mlme->reason_code);
+
+
+	RTW_INFO("%s, cmd=%d, reason=%d\n", __FUNCTION__, mlme->cmd, reason);
+
+
+	switch (mlme->cmd) {
+	case IW_MLME_DEAUTH:
+		if (!rtw_set_802_11_disassociate(padapter))
+			ret = -1;
+		break;
+
+	case IW_MLME_DISASSOC:
+		if (!rtw_set_802_11_disassociate(padapter))
+			ret = -1;
+
+		break;
+
+	default:
+		return -EOPNOTSUPP;
+	}
+#ifdef CONFIG_RTW_REPEATER_SON
+	rtw_rson_do_disconnect(padapter);
+#endif
+	return ret;
+}
+
+static int rtw_wx_set_scan(struct net_device *dev, struct iw_request_info *a,
+			   union iwreq_data *wrqu, char *extra)
+{
+	u8 _status = _FALSE;
+	int ret = 0;
+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
+	/*struct mlme_priv *pmlmepriv = &padapter->mlmepriv;*/
+	struct sitesurvey_parm parm;
+	u8 ssc_chk;
+#ifdef CONFIG_P2P
+	struct wifidirect_info *pwdinfo = &(padapter->wdinfo);
+#endif /* CONFIG_P2P */
+
+#ifdef DBG_IOCTL
+	RTW_INFO("DBG_IOCTL %s:%d\n", __FUNCTION__, __LINE__);
+#endif
+
+#if 1
+	ssc_chk = rtw_sitesurvey_condition_check(padapter, _FALSE);
+
+	#ifdef CONFIG_DOSCAN_IN_BUSYTRAFFIC
+	if ((ssc_chk != SS_ALLOW) && (ssc_chk != SS_DENY_BUSY_TRAFFIC))
+	#else
+	/* When Busy Traffic, driver do not site survey. So driver return success. */
+	/* wpa_supplicant will not issue SIOCSIWSCAN cmd again after scan timeout. */
+	/* modify by thomas 2011-02-22. */
+	if (ssc_chk != SS_ALLOW)
+	#endif
+	{
+		if (ssc_chk == SS_DENY_MP_MODE)
+			ret = -EPERM;
+		#ifdef DBG_LA_MODE
+		else if (ssc_chk == SS_DENY_LA_MODE)
+			ret = -EPERM;
+		#endif
+		else
+			indicate_wx_scan_complete_event(padapter);
+
+		goto exit;
+	} else
+		RTW_INFO(FUNC_ADPT_FMT"\n", FUNC_ADPT_ARG(padapter));
+
+	rtw_ps_deny(padapter, PS_DENY_SCAN);
+	if (_FAIL == rtw_pwr_wakeup(padapter)) {
+		ret = -1;
+		goto cancel_ps_deny;
+	}
+	if (!rtw_is_adapter_up(padapter)) {
+		ret = -1;
+		goto cancel_ps_deny;
+	}
+#else
+
+#ifdef CONFIG_MP_INCLUDED
+	if (rtw_mp_mode_check(padapter)) {
+		RTW_INFO("MP mode block Scan request\n");
+		ret = -EPERM;
+		goto exit;
+	}
+#endif
+	if (rtw_is_scan_deny(padapter)) {
+		indicate_wx_scan_complete_event(padapter);
+		goto exit;
+	}
+
+	rtw_ps_deny(padapter, PS_DENY_SCAN);
+	if (_FAIL == rtw_pwr_wakeup(padapter)) {
+		ret = -1;
+		goto cancel_ps_deny;
+	}
+
+	if (!rtw_is_adapter_up(padapter)) {
+		ret = -1;
+		goto cancel_ps_deny;
+	}
+
+#ifndef CONFIG_DOSCAN_IN_BUSYTRAFFIC
+	/* When Busy Traffic, driver do not site survey. So driver return success. */
+	/* wpa_supplicant will not issue SIOCSIWSCAN cmd again after scan timeout. */
+	/* modify by thomas 2011-02-22. */
+	if (rtw_mi_busy_traffic_check(padapter, _FALSE)) {
+		indicate_wx_scan_complete_event(padapter);
+		goto cancel_ps_deny;
+	}
+#endif
+#ifdef CONFIG_RTW_REPEATER_SON
+	if (padapter->rtw_rson_scanstage == RSON_SCAN_PROCESS) {
+		RTW_INFO(FUNC_ADPT_FMT" blocking scan for under rson scanning process\n", FUNC_ADPT_ARG(padapter));
+		indicate_wx_scan_complete_event(padapter);
+		goto cancel_ps_deny;
+	}
+#endif
+	if (check_fwstate(pmlmepriv, WIFI_AP_STATE) && check_fwstate(pmlmepriv, WIFI_UNDER_WPS)) {
+		RTW_INFO("AP mode process WPS\n");
+		indicate_wx_scan_complete_event(padapter);
+		goto cancel_ps_deny;
+	}
+
+	if (check_fwstate(pmlmepriv, _FW_UNDER_SURVEY | _FW_UNDER_LINKING) == _TRUE) {
+		indicate_wx_scan_complete_event(padapter);
+		goto cancel_ps_deny;
+	}
+
+#ifdef CONFIG_CONCURRENT_MODE
+	if (rtw_mi_buddy_check_fwstate(padapter,
+		       _FW_UNDER_SURVEY | _FW_UNDER_LINKING | WIFI_UNDER_WPS)) {
+
+		indicate_wx_scan_complete_event(padapter);
+		goto cancel_ps_deny;
+	}
+#endif
+#endif
+
+#ifdef CONFIG_P2P
+	if (pwdinfo->p2p_state != P2P_STATE_NONE) {
+		rtw_p2p_set_pre_state(pwdinfo, rtw_p2p_state(pwdinfo));
+		rtw_p2p_set_state(pwdinfo, P2P_STATE_FIND_PHASE_SEARCH);
+		rtw_p2p_findphase_ex_set(pwdinfo, P2P_FINDPHASE_EX_FULL);
+		rtw_free_network_queue(padapter, _TRUE);
+	}
+#endif /* CONFIG_P2P */
+
+#if WIRELESS_EXT >= 17
+	if (wrqu->data.length == sizeof(struct iw_scan_req)) {
+		struct iw_scan_req *req = (struct iw_scan_req *)extra;
+
+		if (wrqu->data.flags & IW_SCAN_THIS_ESSID) {
+			int len = min((int)req->essid_len, IW_ESSID_MAX_SIZE);
+
+			rtw_init_sitesurvey_parm(padapter, &parm);
+			_rtw_memcpy(&parm.ssid[0].Ssid, &req->essid, len);
+			parm.ssid[0].SsidLength = len;
+			parm.ssid_num = 1;
+
+			RTW_INFO("IW_SCAN_THIS_ESSID, ssid=%s, len=%d\n", req->essid, req->essid_len);
+
+			_status = rtw_set_802_11_bssid_list_scan(padapter, &parm);
+
+		} else if (req->scan_type == IW_SCAN_TYPE_PASSIVE)
+			RTW_INFO("rtw_wx_set_scan, req->scan_type == IW_SCAN_TYPE_PASSIVE\n");
+
+	} else
+#endif
+
+		if (wrqu->data.length >= WEXT_CSCAN_HEADER_SIZE
+		    && _rtw_memcmp(extra, WEXT_CSCAN_HEADER, WEXT_CSCAN_HEADER_SIZE) == _TRUE
+		   ) {
+			int len = wrqu->data.length - WEXT_CSCAN_HEADER_SIZE;
+			char *pos = extra + WEXT_CSCAN_HEADER_SIZE;
+			char section;
+			char sec_len;
+			int ssid_index = 0;
+
+			/* RTW_INFO("%s COMBO_SCAN header is recognized\n", __FUNCTION__); */
+			rtw_init_sitesurvey_parm(padapter, &parm);
+
+			while (len >= 1) {
+				section = *(pos++);
+				len -= 1;
+
+				switch (section) {
+				case WEXT_CSCAN_SSID_SECTION:
+					/* RTW_INFO("WEXT_CSCAN_SSID_SECTION\n"); */
+					if (len < 1) {
+						len = 0;
+						break;
+					}
+
+					sec_len = *(pos++);
+					len -= 1;
+
+					if (sec_len > 0 && sec_len <= len) {
+
+						parm.ssid[ssid_index].SsidLength = sec_len;
+						_rtw_memcpy(&parm.ssid[ssid_index].Ssid, pos, sec_len);
+
+						/* RTW_INFO("%s COMBO_SCAN with specific parm.ssid:%s, %d\n", __FUNCTION__ */
+						/*	, parm.ssid[ssid_index].Ssid, parm.ssid[ssid_index].SsidLength); */
+						ssid_index++;
+					}
+
+					pos += sec_len;
+					len -= sec_len;
+					break;
+
+
+				case WEXT_CSCAN_CHANNEL_SECTION:
+					/* RTW_INFO("WEXT_CSCAN_CHANNEL_SECTION\n"); */
+					pos += 1;
+					len -= 1;
+					break;
+				case WEXT_CSCAN_ACTV_DWELL_SECTION:
+					/* RTW_INFO("WEXT_CSCAN_ACTV_DWELL_SECTION\n"); */
+					pos += 2;
+					len -= 2;
+					break;
+				case WEXT_CSCAN_PASV_DWELL_SECTION:
+					/* RTW_INFO("WEXT_CSCAN_PASV_DWELL_SECTION\n"); */
+					pos += 2;
+					len -= 2;
+					break;
+				case WEXT_CSCAN_HOME_DWELL_SECTION:
+					/* RTW_INFO("WEXT_CSCAN_HOME_DWELL_SECTION\n"); */
+					pos += 2;
+					len -= 2;
+					break;
+				case WEXT_CSCAN_TYPE_SECTION:
+					/* RTW_INFO("WEXT_CSCAN_TYPE_SECTION\n"); */
+					pos += 1;
+					len -= 1;
+					break;
+#if 0
+				case WEXT_CSCAN_NPROBE_SECTION:
+					RTW_INFO("WEXT_CSCAN_NPROBE_SECTION\n");
+					break;
+#endif
+
+				default:
+					/* RTW_INFO("Unknown CSCAN section %c\n", section); */
+					len = 0; /* stop parsing */
+				}
+				/* RTW_INFO("len:%d\n", len); */
+
+			}
+			parm.ssid_num = ssid_index;
+
+			/* jeff: it has still some scan paramater to parse, we only do this now... */
+			_status = rtw_set_802_11_bssid_list_scan(padapter, &parm);
+
+		} else
+
+			_status = rtw_set_802_11_bssid_list_scan(padapter, NULL);
+
+	if (_status == _FALSE)
+		ret = -1;
+
+cancel_ps_deny:
+	rtw_ps_deny_cancel(padapter, PS_DENY_SCAN);
+
+exit:
+#ifdef DBG_IOCTL
+	RTW_INFO("DBG_IOCTL %s:%d return %d\n", __FUNCTION__, __LINE__, ret);
+#endif
+
+	return ret;
+}
+
+static int rtw_wx_get_scan(struct net_device *dev, struct iw_request_info *a,
+			   union iwreq_data *wrqu, char *extra)
+{
+	_irqL	irqL;
+	_list					*plist, *phead;
+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
+	struct rf_ctl_t *rfctl = adapter_to_rfctl(padapter);
+	RT_CHANNEL_INFO *chset = rfctl->channel_set;
+	struct	mlme_priv	*pmlmepriv = &(padapter->mlmepriv);
+	_queue				*queue	= &(pmlmepriv->scanned_queue);
+	struct	wlan_network	*pnetwork = NULL;
+	char *ev = extra;
+	char *stop = ev + wrqu->data.length;
+	u32 ret = 0;
+	u32 wait_for_surveydone;
+	sint wait_status;
+	u8 ch;
+
+#ifdef CONFIG_P2P
+	struct	wifidirect_info	*pwdinfo = &padapter->wdinfo;
+#endif /* CONFIG_P2P */
+
+
+#ifdef DBG_IOCTL
+	RTW_INFO("DBG_IOCTL %s:%d\n", __FUNCTION__, __LINE__);
+#endif
+
+	if (adapter_to_pwrctl(padapter)->brfoffbyhw && rtw_is_drv_stopped(padapter)) {
+		ret = -EINVAL;
+		goto exit;
+	}
+
+#ifdef CONFIG_P2P
+	if (!rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE))
+		wait_for_surveydone = 200;
+	else {
+		/*	P2P is disabled */
+		wait_for_surveydone = 100;
+	}
+#else
+	{
+		wait_for_surveydone = 100;
+	}
+#endif /* CONFIG_P2P */
+
+#if 1 /* Wireless Extension use EAGAIN to try */
+	wait_status = _FW_UNDER_SURVEY
+#ifndef CONFIG_ANDROID
+		      | _FW_UNDER_LINKING
+#endif
+		      ;
+
+	while (check_fwstate(pmlmepriv, wait_status) == _TRUE)
+		return -EAGAIN;
+#else
+	wait_status = _FW_UNDER_SURVEY
+#ifndef CONFIG_ANDROID
+		      | _FW_UNDER_LINKING
+#endif
+		      ;
+
+	while (check_fwstate(pmlmepriv, wait_status) == _TRUE) {
+		rtw_msleep_os(30);
+		cnt++;
+		if (cnt > wait_for_surveydone)
+			break;
+	}
+#endif
+	_enter_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);
+
+	phead = get_list_head(queue);
+	plist = get_next(phead);
+
+	while (1) {
+		if (rtw_end_of_queue_search(phead, plist) == _TRUE)
+			break;
+
+		if ((stop - ev) < SCAN_ITEM_SIZE) {
+			if(wrqu->data.length == MAX_SCAN_BUFFER_LEN){ /*max buffer len defined by iwlist*/
+				ret = 0;
+				RTW_INFO("%s: Scan results incomplete\n", __FUNCTION__);
+				break;
+			}
+			ret = -E2BIG;
+			break;
+		}
+
+		pnetwork = LIST_CONTAINOR(plist, struct wlan_network, list);
+		ch = pnetwork->network.Configuration.DSConfig;
+
+		/* report network only if the current channel set contains the channel to which this network belongs */
+		if (rtw_chset_search_ch(chset, ch) >= 0
+			&& rtw_mlme_band_check(padapter, ch) == _TRUE
+			&& _TRUE == rtw_validate_ssid(&(pnetwork->network.Ssid))
+			&& (!IS_DFS_SLAVE_WITH_RD(rfctl)
+				|| rtw_odm_dfs_domain_unknown(rfctl_to_dvobj(rfctl))
+				|| !rtw_chset_is_ch_non_ocp(chset, ch))
+		)
+			ev = translate_scan(padapter, a, pnetwork, ev, stop);
+
+		plist = get_next(plist);
+
+	}
+
+	_exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);
+
+	wrqu->data.length = ev - extra;
+	wrqu->data.flags = 0;
+
+exit:
+
+
+#ifdef DBG_IOCTL
+	RTW_INFO("DBG_IOCTL %s:%d return %d\n", __FUNCTION__, __LINE__, ret);
+#endif
+
+	return ret ;
+
+}
+
+/* set ssid flow
+ * s1. rtw_set_802_11_infrastructure_mode()
+ * s2. set_802_11_authenticaion_mode()
+ * s3. set_802_11_encryption_mode()
+ * s4. rtw_set_802_11_ssid() */
+static int rtw_wx_set_essid(struct net_device *dev,
+			    struct iw_request_info *a,
+			    union iwreq_data *wrqu, char *extra)
+{
+	_irqL irqL;
+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
+	struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
+	_queue *queue = &pmlmepriv->scanned_queue;
+	_list *phead;
+	struct wlan_network *pnetwork = NULL;
+	NDIS_802_11_AUTHENTICATION_MODE authmode;
+	NDIS_802_11_SSID ndis_ssid;
+	u8 *dst_ssid, *src_ssid;
+
+	uint ret = 0, len;
+
+
+#ifdef DBG_IOCTL
+	RTW_INFO("DBG_IOCTL %s:%d\n", __FUNCTION__, __LINE__);
+#endif
+#ifdef CONFIG_WEXT_DONT_JOIN_BYSSID
+	RTW_INFO("%s: CONFIG_WEXT_DONT_JOIN_BYSSID be defined!! only allow bssid joining\n", __func__);
+	return -EPERM;
+#endif
+
+#if WIRELESS_EXT <= 20
+	if ((wrqu->essid.length - 1) > IW_ESSID_MAX_SIZE) {
+#else
+	if (wrqu->essid.length > IW_ESSID_MAX_SIZE) {
+#endif
+		ret = -E2BIG;
+		goto exit;
+	}
+
+
+
+	rtw_ps_deny(padapter, PS_DENY_JOIN);
+	if (_FAIL == rtw_pwr_wakeup(padapter)) {
+		ret = -1;
+		goto cancel_ps_deny;
+	}
+
+	if (!padapter->bup) {
+		ret = -1;
+		goto cancel_ps_deny;
+	}
+
+	if (check_fwstate(pmlmepriv, WIFI_AP_STATE)) {
+		ret = -1;
+		goto cancel_ps_deny;
+	}
+
+#ifdef CONFIG_CONCURRENT_MODE
+	if (rtw_mi_buddy_check_fwstate(padapter, _FW_UNDER_SURVEY | _FW_UNDER_LINKING)) {
+		RTW_INFO("set ssid, but buddy_intf is under scanning or linking\n");
+		ret = -EINVAL;
+		goto cancel_ps_deny;
+	}
+#endif
+	authmode = padapter->securitypriv.ndisauthtype;
+	RTW_INFO("=>%s\n", __FUNCTION__);
+	if (wrqu->essid.flags && wrqu->essid.length) {
+		/* Commented by Albert 20100519 */
+		/* We got the codes in "set_info" function of iwconfig source code. */
+		/*	========================================= */
+		/*	wrq.u.essid.length = strlen(essid) + 1; */
+		/*	if(we_kernel_version > 20) */
+		/*		wrq.u.essid.length--; */
+		/*	========================================= */
+		/*	That means, if the WIRELESS_EXT less than or equal to 20, the correct ssid len should subtract 1. */
+#if WIRELESS_EXT <= 20
+		len = ((wrqu->essid.length - 1) < IW_ESSID_MAX_SIZE) ? (wrqu->essid.length - 1) : IW_ESSID_MAX_SIZE;
+#else
+		len = (wrqu->essid.length < IW_ESSID_MAX_SIZE) ? wrqu->essid.length : IW_ESSID_MAX_SIZE;
+#endif
+
+		if (wrqu->essid.length != 33)
+			RTW_INFO("ssid=%s, len=%d\n", extra, wrqu->essid.length);
+
+		_rtw_memset(&ndis_ssid, 0, sizeof(NDIS_802_11_SSID));
+		ndis_ssid.SsidLength = len;
+		_rtw_memcpy(ndis_ssid.Ssid, extra, len);
+		src_ssid = ndis_ssid.Ssid;
+
+		_enter_critical_bh(&queue->lock, &irqL);
+		phead = get_list_head(queue);
+		pmlmepriv->pscanned = get_next(phead);
+
+		while (1) {
+			if (rtw_end_of_queue_search(phead, pmlmepriv->pscanned) == _TRUE) {
+#if 0
+				if (check_fwstate(pmlmepriv, WIFI_ADHOC_STATE) == _TRUE) {
+					rtw_set_802_11_ssid(padapter, &ndis_ssid);
+
+					goto cancel_ps_deny;
+				} else {
+					ret = -EINVAL;
+					goto cancel_ps_deny;
+				}
+#endif
+
+				break;
+			}
+
+			pnetwork = LIST_CONTAINOR(pmlmepriv->pscanned, struct wlan_network, list);
+
+			pmlmepriv->pscanned = get_next(pmlmepriv->pscanned);
+
+			dst_ssid = pnetwork->network.Ssid.Ssid;
+
+
+			if ((_rtw_memcmp(dst_ssid, src_ssid, ndis_ssid.SsidLength) == _TRUE) &&
+			    (pnetwork->network.Ssid.SsidLength == ndis_ssid.SsidLength)) {
+
+				if (check_fwstate(pmlmepriv, WIFI_ADHOC_STATE) == _TRUE) {
+					if (pnetwork->network.InfrastructureMode != pmlmepriv->cur_network.network.InfrastructureMode)
+						continue;
+				}
+
+				if (rtw_set_802_11_infrastructure_mode(padapter, pnetwork->network.InfrastructureMode) == _FALSE) {
+					ret = -1;
+					_exit_critical_bh(&queue->lock, &irqL);
+					goto cancel_ps_deny;
+				}
+
+				break;
+			}
+		}
+		_exit_critical_bh(&queue->lock, &irqL);
+		rtw_set_802_11_authentication_mode(padapter, authmode);
+		/* set_802_11_encryption_mode(padapter, padapter->securitypriv.ndisencryptstatus); */
+		if (rtw_set_802_11_ssid(padapter, &ndis_ssid) == _FALSE) {
+			ret = -1;
+			goto cancel_ps_deny;
+		}
+	}
+
+cancel_ps_deny:
+	rtw_ps_deny_cancel(padapter, PS_DENY_JOIN);
+
+exit:
+	RTW_INFO("<=%s, ret %d\n", __FUNCTION__, ret);
+
+#ifdef DBG_IOCTL
+	RTW_INFO("DBG_IOCTL %s:%d return %d\n", __FUNCTION__, __LINE__, ret);
+#endif
+
+
+	return ret;
+}
+
+static int rtw_wx_get_essid(struct net_device *dev,
+			    struct iw_request_info *a,
+			    union iwreq_data *wrqu, char *extra)
+{
+	u32 len, ret = 0;
+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
+	struct	mlme_priv	*pmlmepriv = &(padapter->mlmepriv);
+	WLAN_BSSID_EX  *pcur_bss = &pmlmepriv->cur_network.network;
+
+
+
+	if ((check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE) ||
+	    (check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE) == _TRUE)) {
+		len = pcur_bss->Ssid.SsidLength;
+
+		wrqu->essid.length = len;
+
+		_rtw_memcpy(extra, pcur_bss->Ssid.Ssid, len);
+
+		wrqu->essid.flags = 1;
+	} else {
+		ret = -1;
+		goto exit;
+	}
+
+exit:
+
+
+	return ret;
+
+}
+
+static int rtw_wx_set_rate(struct net_device *dev,
+			   struct iw_request_info *a,
+			   union iwreq_data *wrqu, char *extra)
+{
+	int	i, ret = 0;
+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
+	u8	datarates[NumRates];
+	u32	target_rate = wrqu->bitrate.value;
+	u32	fixed = wrqu->bitrate.fixed;
+	u32	ratevalue = 0;
+	u8 mpdatarate[NumRates] = {11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0, 0xff};
+
+
+
+	if (target_rate == -1) {
+		ratevalue = 11;
+		goto set_rate;
+	}
+	target_rate = target_rate / 100000;
+
+	switch (target_rate) {
+	case 10:
+		ratevalue = 0;
+		break;
+	case 20:
+		ratevalue = 1;
+		break;
+	case 55:
+		ratevalue = 2;
+		break;
+	case 60:
+		ratevalue = 3;
+		break;
+	case 90:
+		ratevalue = 4;
+		break;
+	case 110:
+		ratevalue = 5;
+		break;
+	case 120:
+		ratevalue = 6;
+		break;
+	case 180:
+		ratevalue = 7;
+		break;
+	case 240:
+		ratevalue = 8;
+		break;
+	case 360:
+		ratevalue = 9;
+		break;
+	case 480:
+		ratevalue = 10;
+		break;
+	case 540:
+		ratevalue = 11;
+		break;
+	default:
+		ratevalue = 11;
+		break;
+	}
+
+set_rate:
+
+	for (i = 0; i < NumRates; i++) {
+		if (ratevalue == mpdatarate[i]) {
+			datarates[i] = mpdatarate[i];
+			if (fixed == 0)
+				break;
+		} else
+			datarates[i] = 0xff;
+
+	}
+
+	if (rtw_setdatarate_cmd(padapter, datarates) != _SUCCESS) {
+		ret = -1;
+	}
+
+
+	return ret;
+}
+
+static int rtw_wx_get_rate(struct net_device *dev,
+			   struct iw_request_info *info,
+			   union iwreq_data *wrqu, char *extra)
+{
+	u16 max_rate = 0;
+
+	max_rate = rtw_get_cur_max_rate((_adapter *)rtw_netdev_priv(dev));
+
+	if (max_rate == 0)
+		return -EPERM;
+
+	wrqu->bitrate.fixed = 0;	/* no auto select */
+	wrqu->bitrate.value = max_rate * 100000;
+
+	return 0;
+}
+
+static int rtw_wx_set_rts(struct net_device *dev,
+			  struct iw_request_info *info,
+			  union iwreq_data *wrqu, char *extra)
+{
+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
+
+
+	if (wrqu->rts.disabled)
+		padapter->registrypriv.rts_thresh = 2347;
+	else {
+		if (wrqu->rts.value < 0 ||
+		    wrqu->rts.value > 2347)
+			return -EINVAL;
+
+		padapter->registrypriv.rts_thresh = wrqu->rts.value;
+	}
+
+	RTW_INFO("%s, rts_thresh=%d\n", __func__, padapter->registrypriv.rts_thresh);
+
+
+	return 0;
+
+}
+
+static int rtw_wx_get_rts(struct net_device *dev,
+			  struct iw_request_info *info,
+			  union iwreq_data *wrqu, char *extra)
+{
+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
+
+
+	RTW_INFO("%s, rts_thresh=%d\n", __func__, padapter->registrypriv.rts_thresh);
+
+	wrqu->rts.value = padapter->registrypriv.rts_thresh;
+	wrqu->rts.fixed = 0;	/* no auto select */
+	/* wrqu->rts.disabled = (wrqu->rts.value == DEFAULT_RTS_THRESHOLD); */
+
+
+	return 0;
+}
+
+static int rtw_wx_set_frag(struct net_device *dev,
+			   struct iw_request_info *info,
+			   union iwreq_data *wrqu, char *extra)
+{
+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
+
+
+	if (wrqu->frag.disabled)
+		padapter->xmitpriv.frag_len = MAX_FRAG_THRESHOLD;
+	else {
+		if (wrqu->frag.value < MIN_FRAG_THRESHOLD ||
+		    wrqu->frag.value > MAX_FRAG_THRESHOLD)
+			return -EINVAL;
+
+		padapter->xmitpriv.frag_len = wrqu->frag.value & ~0x1;
+	}
+
+	RTW_INFO("%s, frag_len=%d\n", __func__, padapter->xmitpriv.frag_len);
+
+
+	return 0;
+
+}
+
+static int rtw_wx_get_frag(struct net_device *dev,
+			   struct iw_request_info *info,
+			   union iwreq_data *wrqu, char *extra)
+{
+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
+
+
+	RTW_INFO("%s, frag_len=%d\n", __func__, padapter->xmitpriv.frag_len);
+
+	wrqu->frag.value = padapter->xmitpriv.frag_len;
+	wrqu->frag.fixed = 0;	/* no auto select */
+	/* wrqu->frag.disabled = (wrqu->frag.value == DEFAULT_FRAG_THRESHOLD); */
+
+
+	return 0;
+}
+
+static int rtw_wx_get_retry(struct net_device *dev,
+			    struct iw_request_info *info,
+			    union iwreq_data *wrqu, char *extra)
+{
+	/* _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); */
+
+
+	wrqu->retry.value = 7;
+	wrqu->retry.fixed = 0;	/* no auto select */
+	wrqu->retry.disabled = 1;
+
+	return 0;
+
+}
+
+#if 0
+	#define IW_ENCODE_INDEX		0x00FF	/* Token index (if needed) */
+	#define IW_ENCODE_FLAGS		0xFF00	/* Flags defined below */
+	#define IW_ENCODE_MODE		0xF000	/* Modes defined below */
+	#define IW_ENCODE_DISABLED	0x8000	/* Encoding disabled */
+	#define IW_ENCODE_ENABLED	0x0000	/* Encoding enabled */
+	#define IW_ENCODE_RESTRICTED	0x4000	/* Refuse non-encoded packets */
+	#define IW_ENCODE_OPEN		0x2000	/* Accept non-encoded packets */
+	#define IW_ENCODE_NOKEY		0x0800  /* Key is write only, so not present */
+	#define IW_ENCODE_TEMP		0x0400  /* Temporary key */
+	/*
+	iwconfig wlan0 key on->flags = 0x6001->maybe it means auto
+	iwconfig wlan0 key off->flags = 0x8800
+	iwconfig wlan0 key open->flags = 0x2800
+	iwconfig wlan0 key open 1234567890->flags = 0x2000
+	iwconfig wlan0 key restricted->flags = 0x4800
+	iwconfig wlan0 key open [3] 1234567890->flags = 0x2003
+	iwconfig wlan0 key restricted [2] 1234567890->flags = 0x4002
+	iwconfig wlan0 key open [3] -> flags = 0x2803
+	iwconfig wlan0 key restricted [2] -> flags = 0x4802
+	*/
+#endif
+
+static int rtw_wx_set_enc(struct net_device *dev,
+			  struct iw_request_info *info,
+			  union iwreq_data *wrqu, char *keybuf)
+{
+	u32 key, ret = 0;
+	u32 keyindex_provided;
+	NDIS_802_11_WEP	 wep;
+	NDIS_802_11_AUTHENTICATION_MODE authmode;
+
+	struct iw_point *erq = &(wrqu->encoding);
+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
+	struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter);
+	RTW_INFO("+rtw_wx_set_enc, flags=0x%x\n", erq->flags);
+
+	_rtw_memset(&wep, 0, sizeof(NDIS_802_11_WEP));
+
+	key = erq->flags & IW_ENCODE_INDEX;
+
+
+	if (erq->flags & IW_ENCODE_DISABLED) {
+		RTW_INFO("EncryptionDisabled\n");
+		padapter->securitypriv.ndisencryptstatus = Ndis802_11EncryptionDisabled;
+		padapter->securitypriv.dot11PrivacyAlgrthm = _NO_PRIVACY_;
+		padapter->securitypriv.dot118021XGrpPrivacy = _NO_PRIVACY_;
+		padapter->securitypriv.dot11AuthAlgrthm = dot11AuthAlgrthm_Open; /* open system */
+		authmode = Ndis802_11AuthModeOpen;
+		padapter->securitypriv.ndisauthtype = authmode;
+
+		goto exit;
+	}
+
+	if (key) {
+		if (key > WEP_KEYS)
+			return -EINVAL;
+		key--;
+		keyindex_provided = 1;
+	} else {
+		keyindex_provided = 0;
+		key = padapter->securitypriv.dot11PrivacyKeyIndex;
+		RTW_INFO("rtw_wx_set_enc, key=%d\n", key);
+	}
+
+	/* set authentication mode	 */
+	if (erq->flags & IW_ENCODE_OPEN) {
+		RTW_INFO("rtw_wx_set_enc():IW_ENCODE_OPEN\n");
+		padapter->securitypriv.ndisencryptstatus = Ndis802_11Encryption1Enabled;/* Ndis802_11EncryptionDisabled; */
+
+#ifdef CONFIG_PLATFORM_MT53XX
+		padapter->securitypriv.dot11AuthAlgrthm = dot11AuthAlgrthm_Auto;
+#else
+		padapter->securitypriv.dot11AuthAlgrthm = dot11AuthAlgrthm_Open;
+#endif
+
+		padapter->securitypriv.dot11PrivacyAlgrthm = _NO_PRIVACY_;
+		padapter->securitypriv.dot118021XGrpPrivacy = _NO_PRIVACY_;
+		authmode = Ndis802_11AuthModeOpen;
+		padapter->securitypriv.ndisauthtype = authmode;
+	} else if (erq->flags & IW_ENCODE_RESTRICTED) {
+		RTW_INFO("rtw_wx_set_enc():IW_ENCODE_RESTRICTED\n");
+		padapter->securitypriv.ndisencryptstatus = Ndis802_11Encryption1Enabled;
+
+#ifdef CONFIG_PLATFORM_MT53XX
+		padapter->securitypriv.dot11AuthAlgrthm = dot11AuthAlgrthm_Auto;
+#else
+		padapter->securitypriv.dot11AuthAlgrthm = dot11AuthAlgrthm_Shared;
+#endif
+
+		padapter->securitypriv.dot11PrivacyAlgrthm = _WEP40_;
+		padapter->securitypriv.dot118021XGrpPrivacy = _WEP40_;
+		authmode = Ndis802_11AuthModeShared;
+		padapter->securitypriv.ndisauthtype = authmode;
+	} else {
+		RTW_INFO("rtw_wx_set_enc():erq->flags=0x%x\n", erq->flags);
+
+		padapter->securitypriv.ndisencryptstatus = Ndis802_11Encryption1Enabled;/* Ndis802_11EncryptionDisabled; */
+		padapter->securitypriv.dot11AuthAlgrthm = dot11AuthAlgrthm_Open; /* open system */
+		padapter->securitypriv.dot11PrivacyAlgrthm = _NO_PRIVACY_;
+		padapter->securitypriv.dot118021XGrpPrivacy = _NO_PRIVACY_;
+		authmode = Ndis802_11AuthModeOpen;
+		padapter->securitypriv.ndisauthtype = authmode;
+	}
+
+	wep.KeyIndex = key;
+	if (erq->length > 0) {
+		wep.KeyLength = erq->length <= 5 ? 5 : 13;
+
+		wep.Length = wep.KeyLength + FIELD_OFFSET(NDIS_802_11_WEP, KeyMaterial);
+	} else {
+		wep.KeyLength = 0 ;
+
+		if (keyindex_provided == 1) { /* set key_id only, no given KeyMaterial(erq->length==0). */
+			padapter->securitypriv.dot11PrivacyKeyIndex = key;
+
+			RTW_INFO("(keyindex_provided == 1), keyid=%d, key_len=%d\n", key, padapter->securitypriv.dot11DefKeylen[key]);
+
+			switch (padapter->securitypriv.dot11DefKeylen[key]) {
+			case 5:
+				padapter->securitypriv.dot11PrivacyAlgrthm = _WEP40_;
+				break;
+			case 13:
+				padapter->securitypriv.dot11PrivacyAlgrthm = _WEP104_;
+				break;
+			default:
+				padapter->securitypriv.dot11PrivacyAlgrthm = _NO_PRIVACY_;
+				break;
+			}
+
+			goto exit;
+
+		}
+
+	}
+
+	wep.KeyIndex |= 0x80000000;
+
+	_rtw_memcpy(wep.KeyMaterial, keybuf, wep.KeyLength);
+
+	if (rtw_set_802_11_add_wep(padapter, &wep) == _FALSE) {
+		if (rf_on == pwrpriv->rf_pwrstate)
+			ret = -EOPNOTSUPP;
+		goto exit;
+	}
+
+exit:
+
+
+	return ret;
+
+}
+
+static int rtw_wx_get_enc(struct net_device *dev,
+			  struct iw_request_info *info,
+			  union iwreq_data *wrqu, char *keybuf)
+{
+	uint key, ret = 0;
+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
+	struct iw_point *erq = &(wrqu->encoding);
+	struct	mlme_priv	*pmlmepriv = &(padapter->mlmepriv);
+
+
+	if (check_fwstate(pmlmepriv, _FW_LINKED) != _TRUE) {
+		if (check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE) != _TRUE) {
+			erq->length = 0;
+			erq->flags |= IW_ENCODE_DISABLED;
+			return 0;
+		}
+	}
+
+
+	key = erq->flags & IW_ENCODE_INDEX;
+
+	if (key) {
+		if (key > WEP_KEYS)
+			return -EINVAL;
+		key--;
+	} else
+		key = padapter->securitypriv.dot11PrivacyKeyIndex;
+
+	erq->flags = key + 1;
+
+	/* if(padapter->securitypriv.ndisauthtype == Ndis802_11AuthModeOpen) */
+	/* { */
+	/* erq->flags |= IW_ENCODE_OPEN; */
+	/* }	  */
+
+	switch (padapter->securitypriv.ndisencryptstatus) {
+	case Ndis802_11EncryptionNotSupported:
+	case Ndis802_11EncryptionDisabled:
+
+		erq->length = 0;
+		erq->flags |= IW_ENCODE_DISABLED;
+
+		break;
+
+	case Ndis802_11Encryption1Enabled:
+
+		erq->length = padapter->securitypriv.dot11DefKeylen[key];
+
+		if (erq->length) {
+			_rtw_memcpy(keybuf, padapter->securitypriv.dot11DefKey[key].skey, padapter->securitypriv.dot11DefKeylen[key]);
+
+			erq->flags |= IW_ENCODE_ENABLED;
+
+			if (padapter->securitypriv.ndisauthtype == Ndis802_11AuthModeOpen)
+				erq->flags |= IW_ENCODE_OPEN;
+			else if (padapter->securitypriv.ndisauthtype == Ndis802_11AuthModeShared)
+				erq->flags |= IW_ENCODE_RESTRICTED;
+		} else {
+			erq->length = 0;
+			erq->flags |= IW_ENCODE_DISABLED;
+		}
+
+		break;
+
+	case Ndis802_11Encryption2Enabled:
+	case Ndis802_11Encryption3Enabled:
+
+		erq->length = 16;
+		erq->flags |= (IW_ENCODE_ENABLED | IW_ENCODE_OPEN | IW_ENCODE_NOKEY);
+
+		break;
+
+	default:
+		erq->length = 0;
+		erq->flags |= IW_ENCODE_DISABLED;
+
+		break;
+
+	}
+
+
+	return ret;
+
+}
+
+static int rtw_wx_get_power(struct net_device *dev,
+			    struct iw_request_info *info,
+			    union iwreq_data *wrqu, char *extra)
+{
+	/* _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); */
+
+	wrqu->power.value = 0;
+	wrqu->power.fixed = 0;	/* no auto select */
+	wrqu->power.disabled = 1;
+
+	return 0;
+
+}
+
+static int rtw_wx_set_gen_ie(struct net_device *dev,
+			     struct iw_request_info *info,
+			     union iwreq_data *wrqu, char *extra)
+{
+	int ret;
+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
+
+	ret = rtw_set_wpa_ie(padapter, extra, wrqu->data.length);
+
+	return ret;
+}
+
+static int rtw_wx_set_auth(struct net_device *dev,
+			   struct iw_request_info *info,
+			   union iwreq_data *wrqu, char *extra)
+{
+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
+	struct iw_param *param = (struct iw_param *)&(wrqu->param);
+#ifdef CONFIG_WAPI_SUPPORT
+#ifndef CONFIG_IOCTL_CFG80211
+	struct mlme_ext_priv	*pmlmeext = &padapter->mlmeextpriv;
+	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
+	struct security_priv *psecuritypriv = &padapter->securitypriv;
+	u32 value = param->value;
+#endif
+#endif
+	int ret = 0;
+
+	switch (param->flags & IW_AUTH_INDEX) {
+
+	case IW_AUTH_WPA_VERSION:
+#ifdef CONFIG_WAPI_SUPPORT
+#ifndef CONFIG_IOCTL_CFG80211
+		padapter->wapiInfo.bWapiEnable = false;
+		if (value == IW_AUTH_WAPI_VERSION_1) {
+			padapter->wapiInfo.bWapiEnable = true;
+			psecuritypriv->dot11PrivacyAlgrthm = _SMS4_;
+			psecuritypriv->dot118021XGrpPrivacy = _SMS4_;
+			psecuritypriv->dot11AuthAlgrthm = dot11AuthAlgrthm_WAPI;
+			pmlmeinfo->auth_algo = psecuritypriv->dot11AuthAlgrthm;
+			padapter->wapiInfo.extra_prefix_len = WAPI_EXT_LEN;
+			padapter->wapiInfo.extra_postfix_len = SMS4_MIC_LEN;
+		}
+#endif
+#endif
+		break;
+	case IW_AUTH_CIPHER_PAIRWISE:
+
+		break;
+	case IW_AUTH_CIPHER_GROUP:
+
+		break;
+	case IW_AUTH_KEY_MGMT:
+#ifdef CONFIG_WAPI_SUPPORT
+#ifndef CONFIG_IOCTL_CFG80211
+		RTW_INFO("rtw_wx_set_auth: IW_AUTH_KEY_MGMT case\n");
+		if (value == IW_AUTH_KEY_MGMT_WAPI_PSK)
+			padapter->wapiInfo.bWapiPSK = true;
+		else
+			padapter->wapiInfo.bWapiPSK = false;
+		RTW_INFO("rtw_wx_set_auth: IW_AUTH_KEY_MGMT bwapipsk %d\n", padapter->wapiInfo.bWapiPSK);
+#endif
+#endif
+		/*
+		 *  ??? does not use these parameters
+		 */
+		break;
+
+	case IW_AUTH_TKIP_COUNTERMEASURES: {
+		if (param->value) {
+			/* wpa_supplicant is enabling the tkip countermeasure. */
+			padapter->securitypriv.btkip_countermeasure = _TRUE;
+		} else {
+			/* wpa_supplicant is disabling the tkip countermeasure. */
+			padapter->securitypriv.btkip_countermeasure = _FALSE;
+		}
+		break;
+	}
+	case IW_AUTH_DROP_UNENCRYPTED: {
+		/* HACK:
+		 *
+		 * wpa_supplicant calls set_wpa_enabled when the driver
+		 * is loaded and unloaded, regardless of if WPA is being
+		 * used.  No other calls are made which can be used to
+		 * determine if encryption will be used or not prior to
+		 * association being expected.  If encryption is not being
+		 * used, drop_unencrypted is set to false, else true -- we
+		 * can use this to determine if the CAP_PRIVACY_ON bit should
+		 * be set.
+		 */
+
+		if (padapter->securitypriv.ndisencryptstatus == Ndis802_11Encryption1Enabled) {
+			break;/* it means init value, or using wep, ndisencryptstatus = Ndis802_11Encryption1Enabled, */
+			/* then it needn't reset it; */
+		}
+
+		if (param->value) {
+			padapter->securitypriv.ndisencryptstatus = Ndis802_11EncryptionDisabled;
+			padapter->securitypriv.dot11PrivacyAlgrthm = _NO_PRIVACY_;
+			padapter->securitypriv.dot118021XGrpPrivacy = _NO_PRIVACY_;
+			padapter->securitypriv.dot11AuthAlgrthm = dot11AuthAlgrthm_Open; /* open system */
+			padapter->securitypriv.ndisauthtype = Ndis802_11AuthModeOpen;
+		}
+
+		break;
+	}
+
+	case IW_AUTH_80211_AUTH_ALG:
+
+#if defined(CONFIG_ANDROID) || 1
+		/*
+		 *  It's the starting point of a link layer connection using wpa_supplicant
+		*/
+		if (check_fwstate(&padapter->mlmepriv, _FW_LINKED)) {
+			LeaveAllPowerSaveMode(padapter);
+			rtw_disassoc_cmd(padapter, 500, RTW_CMDF_WAIT_ACK);
+			RTW_INFO("%s...call rtw_indicate_disconnect\n ", __FUNCTION__);
+			rtw_indicate_disconnect(padapter, 0, _FALSE);
+			rtw_free_assoc_resources_cmd(padapter, _TRUE, RTW_CMDF_WAIT_ACK);
+		}
+#endif
+
+
+		ret = wpa_set_auth_algs(dev, (u32)param->value);
+
+		break;
+
+	case IW_AUTH_WPA_ENABLED:
+
+		/* if(param->value) */
+		/* padapter->securitypriv.dot11AuthAlgrthm = dot11AuthAlgrthm_8021X; */ /* 802.1x */
+		/* else */
+		/* padapter->securitypriv.dot11AuthAlgrthm = dot11AuthAlgrthm_Open; */ /* open system */
+
+		/* _disassociate(priv); */
+
+		break;
+
+	case IW_AUTH_RX_UNENCRYPTED_EAPOL:
+		/* ieee->ieee802_1x = param->value; */
+		break;
+
+	case IW_AUTH_PRIVACY_INVOKED:
+		/* ieee->privacy_invoked = param->value; */
+		break;
+
+#ifdef CONFIG_WAPI_SUPPORT
+#ifndef CONFIG_IOCTL_CFG80211
+	case IW_AUTH_WAPI_ENABLED:
+		break;
+#endif
+#endif
+
+	default:
+		return -EOPNOTSUPP;
+
+	}
+
+	return ret;
+
+}
+
+static int rtw_wx_set_enc_ext(struct net_device *dev,
+			      struct iw_request_info *info,
+			      union iwreq_data *wrqu, char *extra)
+{
+	char *alg_name;
+	u32 param_len;
+	struct ieee_param *param = NULL;
+	struct iw_point *pencoding = &wrqu->encoding;
+	struct iw_encode_ext *pext = (struct iw_encode_ext *)extra;
+	int ret = 0;
+
+	param_len = sizeof(struct ieee_param) + pext->key_len;
+	param = (struct ieee_param *)rtw_malloc(param_len);
+	if (param == NULL)
+		return -1;
+
+	_rtw_memset(param, 0, param_len);
+
+	param->cmd = IEEE_CMD_SET_ENCRYPTION;
+	_rtw_memset(param->sta_addr, 0xff, ETH_ALEN);
+
+
+	switch (pext->alg) {
+	case IW_ENCODE_ALG_NONE:
+		/* todo: remove key */
+		/* remove = 1;	 */
+		alg_name = "none";
+		break;
+	case IW_ENCODE_ALG_WEP:
+		alg_name = "WEP";
+		break;
+	case IW_ENCODE_ALG_TKIP:
+		alg_name = "TKIP";
+		break;
+	case IW_ENCODE_ALG_CCMP:
+		alg_name = "CCMP";
+		break;
+#ifdef CONFIG_IEEE80211W
+	case IW_ENCODE_ALG_AES_CMAC:
+		alg_name = "BIP";
+		break;
+#endif /* CONFIG_IEEE80211W */
+#ifdef CONFIG_WAPI_SUPPORT
+#ifndef CONFIG_IOCTL_CFG80211
+	case IW_ENCODE_ALG_SM4:
+		alg_name = "SMS4";
+		_rtw_memcpy(param->sta_addr, pext->addr.sa_data, ETH_ALEN);
+		RTW_INFO("rtw_wx_set_enc_ext: SMS4 case\n");
+		break;
+#endif
+#endif
+	default:
+		ret = -1;
+		goto exit;
+	}
+
+	strncpy((char *)param->u.crypt.alg, alg_name, IEEE_CRYPT_ALG_NAME_LEN);
+
+	if (pext->ext_flags & IW_ENCODE_EXT_SET_TX_KEY)
+		param->u.crypt.set_tx = 1;
+
+	/* cliW: WEP does not have group key
+	 * just not checking GROUP key setting
+	 */
+	if ((pext->alg != IW_ENCODE_ALG_WEP) &&
+	    ((pext->ext_flags & IW_ENCODE_EXT_GROUP_KEY)
+#ifdef CONFIG_IEEE80211W
+	     || (pext->ext_flags & IW_ENCODE_ALG_AES_CMAC)
+#endif /* CONFIG_IEEE80211W */
+	    ))
+		param->u.crypt.set_tx = 0;
+
+	param->u.crypt.idx = (pencoding->flags & 0x00FF) - 1 ;
+
+	if (pext->ext_flags & IW_ENCODE_EXT_RX_SEQ_VALID) {
+#ifdef CONFIG_WAPI_SUPPORT
+#ifndef CONFIG_IOCTL_CFG80211
+		if (pext->alg == IW_ENCODE_ALG_SM4)
+			_rtw_memcpy(param->u.crypt.seq, pext->rx_seq, 16);
+		else
+#endif /* CONFIG_IOCTL_CFG80211 */
+#endif /* CONFIG_WAPI_SUPPORT */
+			_rtw_memcpy(param->u.crypt.seq, pext->rx_seq, 8);
+	}
+
+	if (pext->key_len) {
+		param->u.crypt.key_len = pext->key_len;
+		/* _rtw_memcpy(param + 1, pext + 1, pext->key_len); */
+		_rtw_memcpy(param->u.crypt.key, pext + 1, pext->key_len);
+	}
+
+	if (pencoding->flags & IW_ENCODE_DISABLED) {
+		/* todo: remove key */
+		/* remove = 1; */
+	}
+
+	ret =  wpa_set_encryption(dev, param, param_len);
+
+exit:
+	if (param)
+		rtw_mfree((u8 *)param, param_len);
+
+	return ret;
+}
+
+
+static int rtw_wx_get_nick(struct net_device *dev,
+			   struct iw_request_info *info,
+			   union iwreq_data *wrqu, char *extra)
+{
+	/* _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); */
+	/* struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); */
+	/* struct security_priv *psecuritypriv = &padapter->securitypriv; */
+
+	if (extra) {
+		wrqu->data.length = 14;
+		wrqu->data.flags = 1;
+		_rtw_memcpy(extra, "<WIFI@REALTEK>", 14);
+	}
+
+	/* rtw_signal_process(pid, SIGUSR1); */ /* for test */
+
+	/* dump debug info here	 */
+#if 0
+	u32 dot11AuthAlgrthm;		/*  802.11 auth, could be open, shared, and 8021x */
+	u32 dot11PrivacyAlgrthm;	/*  This specify the privacy for shared auth. algorithm. */
+	u32 dot118021XGrpPrivacy;	/*  This specify the privacy algthm. used for Grp key */
+	u32 ndisauthtype;
+	u32 ndisencryptstatus;
+#endif
+
+	/* RTW_INFO("auth_alg=0x%x, enc_alg=0x%x, auth_type=0x%x, enc_type=0x%x\n",  */
+	/*		psecuritypriv->dot11AuthAlgrthm, psecuritypriv->dot11PrivacyAlgrthm, */
+	/*		psecuritypriv->ndisauthtype, psecuritypriv->ndisencryptstatus); */
+
+	/* RTW_INFO("enc_alg=0x%x\n", psecuritypriv->dot11PrivacyAlgrthm); */
+	/* RTW_INFO("auth_type=0x%x\n", psecuritypriv->ndisauthtype); */
+	/* RTW_INFO("enc_type=0x%x\n", psecuritypriv->ndisencryptstatus); */
+
+#if 0
+	RTW_INFO("dbg(0x210)=0x%x\n", rtw_read32(padapter, 0x210));
+	RTW_INFO("dbg(0x608)=0x%x\n", rtw_read32(padapter, 0x608));
+	RTW_INFO("dbg(0x280)=0x%x\n", rtw_read32(padapter, 0x280));
+	RTW_INFO("dbg(0x284)=0x%x\n", rtw_read32(padapter, 0x284));
+	RTW_INFO("dbg(0x288)=0x%x\n", rtw_read32(padapter, 0x288));
+
+	RTW_INFO("dbg(0x664)=0x%x\n", rtw_read32(padapter, 0x664));
+
+
+	RTW_INFO("\n");
+
+	RTW_INFO("dbg(0x430)=0x%x\n", rtw_read32(padapter, 0x430));
+	RTW_INFO("dbg(0x438)=0x%x\n", rtw_read32(padapter, 0x438));
+
+	RTW_INFO("dbg(0x440)=0x%x\n", rtw_read32(padapter, 0x440));
+
+	RTW_INFO("dbg(0x458)=0x%x\n", rtw_read32(padapter, 0x458));
+
+	RTW_INFO("dbg(0x484)=0x%x\n", rtw_read32(padapter, 0x484));
+	RTW_INFO("dbg(0x488)=0x%x\n", rtw_read32(padapter, 0x488));
+
+	RTW_INFO("dbg(0x444)=0x%x\n", rtw_read32(padapter, 0x444));
+	RTW_INFO("dbg(0x448)=0x%x\n", rtw_read32(padapter, 0x448));
+	RTW_INFO("dbg(0x44c)=0x%x\n", rtw_read32(padapter, 0x44c));
+	RTW_INFO("dbg(0x450)=0x%x\n", rtw_read32(padapter, 0x450));
+#endif
+
+	return 0;
+
+}
+
+static int rtw_wx_read32(struct net_device *dev,
+			 struct iw_request_info *info,
+			 union iwreq_data *wrqu, char *extra)
+{
+	PADAPTER padapter;
+	struct iw_point *p;
+	u16 len;
+	u32 addr;
+	u32 data32;
+	u32 bytes;
+	u8 *ptmp;
+	int ret;
+
+
+	ret = 0;
+	padapter = (PADAPTER)rtw_netdev_priv(dev);
+	p = &wrqu->data;
+	len = p->length;
+	if (0 == len)
+		return -EINVAL;
+
+	ptmp = (u8 *)rtw_malloc(len);
+	if (NULL == ptmp)
+		return -ENOMEM;
+
+	if (copy_from_user(ptmp, p->pointer, len)) {
+		ret = -EFAULT;
+		goto exit;
+	}
+
+	bytes = 0;
+	addr = 0;
+	sscanf(ptmp, "%d,%x", &bytes, &addr);
+
+	switch (bytes) {
+	case 1:
+		data32 = rtw_read8(padapter, addr);
+		sprintf(extra, "0x%02X", data32);
+		break;
+	case 2:
+		data32 = rtw_read16(padapter, addr);
+		sprintf(extra, "0x%04X", data32);
+		break;
+	case 4:
+		data32 = rtw_read32(padapter, addr);
+		sprintf(extra, "0x%08X", data32);
+		break;
+
+	#if defined(CONFIG_SDIO_HCI) && defined(CONFIG_SDIO_INDIRECT_ACCESS) && defined(DBG_SDIO_INDIRECT_ACCESS)
+	case 11:
+		data32 = rtw_sd_iread8(padapter, addr);
+		sprintf(extra, "0x%02X", data32);
+		break;
+	case 12:
+		data32 = rtw_sd_iread16(padapter, addr);
+		sprintf(extra, "0x%04X", data32);
+		break;
+	case 14:
+		data32 = rtw_sd_iread32(padapter, addr);
+		sprintf(extra, "0x%08X", data32);
+		break;
+	#endif
+	default:
+		RTW_INFO("%s: usage> read [bytes],[address(hex)]\n", __func__);
+		ret = -EINVAL;
+		goto exit;
+	}
+	RTW_INFO("%s: addr=0x%08X data=%s\n", __func__, addr, extra);
+
+exit:
+	rtw_mfree(ptmp, len);
+
+	return 0;
+}
+
+static int rtw_wx_write32(struct net_device *dev,
+			  struct iw_request_info *info,
+			  union iwreq_data *wrqu, char *extra)
+{
+	PADAPTER padapter = (PADAPTER)rtw_netdev_priv(dev);
+
+	u32 addr;
+	u32 data32;
+	u32 bytes;
+
+
+	bytes = 0;
+	addr = 0;
+	data32 = 0;
+	sscanf(extra, "%d,%x,%x", &bytes, &addr, &data32);
+
+	switch (bytes) {
+	case 1:
+		rtw_write8(padapter, addr, (u8)data32);
+		RTW_INFO("%s: addr=0x%08X data=0x%02X\n", __func__, addr, (u8)data32);
+		break;
+	case 2:
+		rtw_write16(padapter, addr, (u16)data32);
+		RTW_INFO("%s: addr=0x%08X data=0x%04X\n", __func__, addr, (u16)data32);
+		break;
+	case 4:
+		rtw_write32(padapter, addr, data32);
+		RTW_INFO("%s: addr=0x%08X data=0x%08X\n", __func__, addr, data32);
+		break;
+	default:
+		RTW_INFO("%s: usage> write [bytes],[address(hex)],[data(hex)]\n", __func__);
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+static int rtw_wx_read_rf(struct net_device *dev,
+			  struct iw_request_info *info,
+			  union iwreq_data *wrqu, char *extra)
+{
+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
+	u32 path, addr, data32;
+
+
+	path = *(u32 *)extra;
+	addr = *((u32 *)extra + 1);
+	data32 = rtw_hal_read_rfreg(padapter, path, addr, 0xFFFFF);
+	/*	RTW_INFO("%s: path=%d addr=0x%02x data=0x%05x\n", __func__, path, addr, data32); */
+	/*
+	 * IMPORTANT!!
+	 * Only when wireless private ioctl is at odd order,
+	 * "extra" would be copied to user space.
+	 */
+	sprintf(extra, "0x%05x", data32);
+
+	return 0;
+}
+
+static int rtw_wx_write_rf(struct net_device *dev,
+			   struct iw_request_info *info,
+			   union iwreq_data *wrqu, char *extra)
+{
+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
+	u32 path, addr, data32;
+
+
+	path = *(u32 *)extra;
+	addr = *((u32 *)extra + 1);
+	data32 = *((u32 *)extra + 2);
+	/*	RTW_INFO("%s: path=%d addr=0x%02x data=0x%05x\n", __func__, path, addr, data32); */
+	rtw_hal_write_rfreg(padapter, path, addr, 0xFFFFF, data32);
+
+	return 0;
+}
+
+static int rtw_wx_priv_null(struct net_device *dev, struct iw_request_info *a,
+			    union iwreq_data *wrqu, char *b)
+{
+	return -1;
+}
+
+#ifdef CONFIG_RTW_80211K
+extern void rm_dbg_cmd(_adapter *padapter, char *s);
+static int rtw_wx_priv_rrm(struct net_device *dev, struct iw_request_info *a,
+			    union iwreq_data *wrqu, char *b)
+{
+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
+	u32 path, addr, data32;
+
+
+	rm_dbg_cmd(padapter, b);
+	wrqu->data.length = strlen(b);
+
+	return 0;
+}
+#endif
+
+static int dummy(struct net_device *dev, struct iw_request_info *a,
+		 union iwreq_data *wrqu, char *b)
+{
+	/* _adapter *padapter = (_adapter *)rtw_netdev_priv(dev);	 */
+	/* struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); */
+
+	/* RTW_INFO("cmd_code=%x, fwstate=0x%x\n", a->cmd, get_fwstate(pmlmepriv)); */
+
+	return -1;
+
+}
+
+static int rtw_wx_set_channel_plan(struct net_device *dev,
+				   struct iw_request_info *info,
+				   union iwreq_data *wrqu, char *extra)
+{
+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
+	u8 channel_plan_req = (u8)(*((int *)wrqu));
+
+	if (_SUCCESS != rtw_set_channel_plan(padapter, channel_plan_req))
+		return -EPERM;
+
+	return 0;
+}
+
+static int rtw_wx_set_mtk_wps_probe_ie(struct net_device *dev,
+				       struct iw_request_info *a,
+				       union iwreq_data *wrqu, char *b)
+{
+#ifdef CONFIG_PLATFORM_MT53XX
+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
+	struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
+
+#endif
+	return 0;
+}
+
+static int rtw_wx_get_sensitivity(struct net_device *dev,
+				  struct iw_request_info *info,
+				  union iwreq_data *wrqu, char *buf)
+{
+#ifdef CONFIG_PLATFORM_MT53XX
+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
+
+	/*	Modified by Albert 20110914 */
+	/*	This is in dbm format for MTK platform. */
+	wrqu->qual.level = padapter->recvpriv.rssi;
+	RTW_INFO(" level = %u\n",  wrqu->qual.level);
+#endif
+	return 0;
+}
+
+static int rtw_wx_set_mtk_wps_ie(struct net_device *dev,
+				 struct iw_request_info *info,
+				 union iwreq_data *wrqu, char *extra)
+{
+#ifdef CONFIG_PLATFORM_MT53XX
+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
+
+	return rtw_set_wpa_ie(padapter, wrqu->data.pointer, wrqu->data.length);
+#else
+	return 0;
+#endif
+}
+
+static void rtw_dbg_mode_hdl(_adapter *padapter, u32 id, u8 *pdata, u32 len)
+{
+	pRW_Reg	RegRWStruct;
+	struct rf_reg_param *prfreg;
+	u8 path;
+	u8 offset;
+	u32 value;
+
+	RTW_INFO("%s\n", __FUNCTION__);
+
+	switch (id) {
+	case GEN_MP_IOCTL_SUBCODE(MP_START):
+		RTW_INFO("871x_driver is only for normal mode, can't enter mp mode\n");
+		break;
+	case GEN_MP_IOCTL_SUBCODE(READ_REG):
+		RegRWStruct = (pRW_Reg)pdata;
+		switch (RegRWStruct->width) {
+		case 1:
+			RegRWStruct->value = rtw_read8(padapter, RegRWStruct->offset);
+			break;
+		case 2:
+			RegRWStruct->value = rtw_read16(padapter, RegRWStruct->offset);
+			break;
+		case 4:
+			RegRWStruct->value = rtw_read32(padapter, RegRWStruct->offset);
+			break;
+		default:
+			break;
+		}
+
+		break;
+	case GEN_MP_IOCTL_SUBCODE(WRITE_REG):
+		RegRWStruct = (pRW_Reg)pdata;
+		switch (RegRWStruct->width) {
+		case 1:
+			rtw_write8(padapter, RegRWStruct->offset, (u8)RegRWStruct->value);
+			break;
+		case 2:
+			rtw_write16(padapter, RegRWStruct->offset, (u16)RegRWStruct->value);
+			break;
+		case 4:
+			rtw_write32(padapter, RegRWStruct->offset, (u32)RegRWStruct->value);
+			break;
+		default:
+			break;
+		}
+
+		break;
+	case GEN_MP_IOCTL_SUBCODE(READ_RF_REG):
+
+		prfreg = (struct rf_reg_param *)pdata;
+
+		path = (u8)prfreg->path;
+		offset = (u8)prfreg->offset;
+
+		value = rtw_hal_read_rfreg(padapter, path, offset, 0xffffffff);
+
+		prfreg->value = value;
+
+		break;
+	case GEN_MP_IOCTL_SUBCODE(WRITE_RF_REG):
+
+		prfreg = (struct rf_reg_param *)pdata;
+
+		path = (u8)prfreg->path;
+		offset = (u8)prfreg->offset;
+		value = prfreg->value;
+
+		rtw_hal_write_rfreg(padapter, path, offset, 0xffffffff, value);
+
+		break;
+	case GEN_MP_IOCTL_SUBCODE(TRIGGER_GPIO):
+		RTW_INFO("==> trigger gpio 0\n");
+		rtw_hal_set_hwreg(padapter, HW_VAR_TRIGGER_GPIO_0, 0);
+		break;
+#ifdef CONFIG_BT_COEXIST
+	case GEN_MP_IOCTL_SUBCODE(SET_DM_BT):
+		RTW_INFO("==> set dm_bt_coexist:%x\n", *(u8 *)pdata);
+		rtw_hal_set_hwreg(padapter, HW_VAR_BT_SET_COEXIST, pdata);
+		break;
+	case GEN_MP_IOCTL_SUBCODE(DEL_BA):
+		RTW_INFO("==> delete ba:%x\n", *(u8 *)pdata);
+		rtw_hal_set_hwreg(padapter, HW_VAR_BT_ISSUE_DELBA, pdata);
+		break;
+#endif
+#ifdef DBG_CONFIG_ERROR_DETECT
+	case GEN_MP_IOCTL_SUBCODE(GET_WIFI_STATUS):
+		*pdata = rtw_hal_sreset_get_wifi_status(padapter);
+		break;
+#endif
+
+	default:
+		break;
+	}
+
+}
+#ifdef MP_IOCTL_HDL
+static int rtw_mp_ioctl_hdl(struct net_device *dev, struct iw_request_info *info,
+			    union iwreq_data *wrqu, char *extra)
+{
+	int ret = 0;
+	u32 BytesRead, BytesWritten, BytesNeeded;
+	struct oid_par_priv	oid_par;
+	struct mp_ioctl_handler	*phandler;
+	struct mp_ioctl_param	*poidparam;
+	uint status = 0;
+	u16 len;
+	u8 *pparmbuf = NULL, bset;
+	PADAPTER padapter = (PADAPTER)rtw_netdev_priv(dev);
+	struct iw_point *p = &wrqu->data;
+
+	/* RTW_INFO("+rtw_mp_ioctl_hdl\n"); */
+
+	/* mutex_lock(&ioctl_mutex); */
+
+	if ((!p->length) || (!p->pointer)) {
+		ret = -EINVAL;
+		goto _rtw_mp_ioctl_hdl_exit;
+	}
+
+	pparmbuf = NULL;
+	bset = (u8)(p->flags & 0xFFFF);
+	len = p->length;
+	pparmbuf = (u8 *)rtw_malloc(len);
+	if (pparmbuf == NULL) {
+		ret = -ENOMEM;
+		goto _rtw_mp_ioctl_hdl_exit;
+	}
+
+	if (copy_from_user(pparmbuf, p->pointer, len)) {
+		ret = -EFAULT;
+		goto _rtw_mp_ioctl_hdl_exit;
+	}
+
+	poidparam = (struct mp_ioctl_param *)pparmbuf;
+
+	if (poidparam->subcode >= MAX_MP_IOCTL_SUBCODE) {
+		ret = -EINVAL;
+		goto _rtw_mp_ioctl_hdl_exit;
+	}
+
+	/* RTW_INFO("%s: %d\n", __func__, poidparam->subcode); */
+#ifdef CONFIG_MP_INCLUDED
+	if (padapter->registrypriv.mp_mode == 1) {
+		phandler = mp_ioctl_hdl + poidparam->subcode;
+
+		if ((phandler->paramsize != 0) && (poidparam->len < phandler->paramsize)) {
+			ret = -EINVAL;
+			goto _rtw_mp_ioctl_hdl_exit;
+		}
+
+		if (phandler->handler) {
+			oid_par.adapter_context = padapter;
+			oid_par.oid = phandler->oid;
+			oid_par.information_buf = poidparam->data;
+			oid_par.information_buf_len = poidparam->len;
+			oid_par.dbg = 0;
+
+			BytesWritten = 0;
+			BytesNeeded = 0;
+
+			if (bset) {
+				oid_par.bytes_rw = &BytesRead;
+				oid_par.bytes_needed = &BytesNeeded;
+				oid_par.type_of_oid = SET_OID;
+			} else {
+				oid_par.bytes_rw = &BytesWritten;
+				oid_par.bytes_needed = &BytesNeeded;
+				oid_par.type_of_oid = QUERY_OID;
+			}
+
+			status = phandler->handler(&oid_par);
+
+			/* todo:check status, BytesNeeded, etc. */
+		} else {
+			RTW_INFO("rtw_mp_ioctl_hdl(): err!, subcode=%d, oid=%d, handler=%p\n",
+				poidparam->subcode, phandler->oid, phandler->handler);
+			ret = -EFAULT;
+			goto _rtw_mp_ioctl_hdl_exit;
+		}
+	} else
+#endif
+	{
+		rtw_dbg_mode_hdl(padapter, poidparam->subcode, poidparam->data, poidparam->len);
+	}
+
+	if (bset == 0x00) {/* query info */
+		if (copy_to_user(p->pointer, pparmbuf, len))
+			ret = -EFAULT;
+	}
+
+	if (status) {
+		ret = -EFAULT;
+		goto _rtw_mp_ioctl_hdl_exit;
+	}
+
+_rtw_mp_ioctl_hdl_exit:
+
+	if (pparmbuf)
+		rtw_mfree(pparmbuf, len);
+
+	/* mutex_unlock(&ioctl_mutex); */
+
+	return ret;
+}
+#endif
+static int rtw_get_ap_info(struct net_device *dev,
+			   struct iw_request_info *info,
+			   union iwreq_data *wrqu, char *extra)
+{
+	int ret = 0;
+	u32 cnt = 0, wpa_ielen;
+	_irqL	irqL;
+	_list	*plist, *phead;
+	unsigned char *pbuf;
+	u8 bssid[ETH_ALEN];
+	char data[32];
+	struct wlan_network *pnetwork = NULL;
+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
+	struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
+	_queue *queue = &(pmlmepriv->scanned_queue);
+	struct iw_point *pdata = &wrqu->data;
+
+	RTW_INFO("+rtw_get_aplist_info\n");
+
+	if (rtw_is_drv_stopped(padapter) || (pdata == NULL)) {
+		ret = -EINVAL;
+		goto exit;
+	}
+
+	while ((check_fwstate(pmlmepriv, (_FW_UNDER_SURVEY | _FW_UNDER_LINKING))) == _TRUE) {
+		rtw_msleep_os(30);
+		cnt++;
+		if (cnt > 100)
+			break;
+	}
+
+
+	/* pdata->length = 0; */ /* ?	 */
+	pdata->flags = 0;
+	if (pdata->length >= 32) {
+		if (copy_from_user(data, pdata->pointer, 32)) {
+			ret = -EINVAL;
+			goto exit;
+		}
+	} else {
+		ret = -EINVAL;
+		goto exit;
+	}
+
+	_enter_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);
+
+	phead = get_list_head(queue);
+	plist = get_next(phead);
+
+	while (1) {
+		if (rtw_end_of_queue_search(phead, plist) == _TRUE)
+			break;
+
+
+		pnetwork = LIST_CONTAINOR(plist, struct wlan_network, list);
+
+		/* if(hwaddr_aton_i(pdata->pointer, bssid)) */
+		if (hwaddr_aton_i(data, bssid)) {
+			RTW_INFO("Invalid BSSID '%s'.\n", (u8 *)data);
+			_exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);
+			return -EINVAL;
+		}
+
+
+		if (_rtw_memcmp(bssid, pnetwork->network.MacAddress, ETH_ALEN) == _TRUE) { /* BSSID match, then check if supporting wpa/wpa2 */
+			RTW_INFO("BSSID:" MAC_FMT "\n", MAC_ARG(bssid));
+
+			pbuf = rtw_get_wpa_ie(&pnetwork->network.IEs[12], &wpa_ielen, pnetwork->network.IELength - 12);
+			if (pbuf && (wpa_ielen > 0)) {
+				pdata->flags = 1;
+				break;
+			}
+
+			pbuf = rtw_get_wpa2_ie(&pnetwork->network.IEs[12], &wpa_ielen, pnetwork->network.IELength - 12);
+			if (pbuf && (wpa_ielen > 0)) {
+				pdata->flags = 2;
+				break;
+			}
+
+		}
+
+		plist = get_next(plist);
+
+	}
+
+	_exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);
+
+	if (pdata->length >= 34) {
+		if (copy_to_user((u8 *)pdata->pointer + 32, (u8 *)&pdata->flags, 1)) {
+			ret = -EINVAL;
+			goto exit;
+		}
+	}
+
+exit:
+
+	return ret;
+
+}
+
+static int rtw_set_pid(struct net_device *dev,
+		       struct iw_request_info *info,
+		       union iwreq_data *wrqu, char *extra)
+{
+
+	int ret = 0;
+	_adapter *padapter = rtw_netdev_priv(dev);
+	int *pdata = (int *)wrqu;
+	int selector;
+
+	if (rtw_is_drv_stopped(padapter) || (pdata == NULL)) {
+		ret = -EINVAL;
+		goto exit;
+	}
+
+	selector = *pdata;
+	if (selector < 3 && selector >= 0) {
+		padapter->pid[selector] = *(pdata + 1);
+#ifdef CONFIG_GLOBAL_UI_PID
+		ui_pid[selector] = *(pdata + 1);
+#endif
+		RTW_INFO("%s set pid[%d]=%d\n", __FUNCTION__, selector , padapter->pid[selector]);
+	} else
+		RTW_INFO("%s selector %d error\n", __FUNCTION__, selector);
+
+exit:
+
+	return ret;
+
+}
+
+static int rtw_wps_start(struct net_device *dev,
+			 struct iw_request_info *info,
+			 union iwreq_data *wrqu, char *extra)
+{
+
+	int ret = 0;
+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
+	struct iw_point *pdata = &wrqu->data;
+	u32   u32wps_start = 0;
+	unsigned int uintRet = 0;
+
+	if (RTW_CANNOT_RUN(padapter) || (NULL == pdata)) {
+		ret = -EINVAL;
+		goto exit;
+	}
+
+	uintRet = copy_from_user((void *) &u32wps_start, pdata->pointer, 4);
+	if (u32wps_start == 0)
+		u32wps_start = *extra;
+
+	RTW_INFO("[%s] wps_start = %d\n", __FUNCTION__, u32wps_start);
+
+	if (u32wps_start == 1)   /* WPS Start */
+		rtw_led_control(padapter, LED_CTL_START_WPS);
+	else if (u32wps_start == 2)   /* WPS Stop because of wps success */
+		rtw_led_control(padapter, LED_CTL_STOP_WPS);
+	else if (u32wps_start == 3)   /* WPS Stop because of wps fail */
+		rtw_led_control(padapter, LED_CTL_STOP_WPS_FAIL);
+
+#ifdef CONFIG_INTEL_WIDI
+	process_intel_widi_wps_status(padapter, u32wps_start);
+#endif /* CONFIG_INTEL_WIDI */
+
+exit:
+
+	return ret;
+
+}
+
+#ifdef CONFIG_P2P
+static int rtw_wext_p2p_enable(struct net_device *dev,
+			       struct iw_request_info *info,
+			       union iwreq_data *wrqu, char *extra)
+{
+
+	int ret = 0;
+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
+	struct wifidirect_info *pwdinfo = &(padapter->wdinfo);
+	struct mlme_ext_priv	*pmlmeext = &padapter->mlmeextpriv;
+	enum P2P_ROLE init_role = P2P_ROLE_DISABLE;
+
+	if (*extra == '0')
+		init_role = P2P_ROLE_DISABLE;
+	else if (*extra == '1')
+		init_role = P2P_ROLE_DEVICE;
+	else if (*extra == '2')
+		init_role = P2P_ROLE_CLIENT;
+	else if (*extra == '3')
+		init_role = P2P_ROLE_GO;
+
+	if (_FAIL == rtw_p2p_enable(padapter, init_role)) {
+		ret = -EFAULT;
+		goto exit;
+	}
+
+	/* set channel/bandwidth */
+	if (init_role != P2P_ROLE_DISABLE) {
+		u8 channel, ch_offset;
+		u16 bwmode;
+
+		if (rtw_p2p_chk_state(pwdinfo, P2P_STATE_LISTEN)) {
+			/*	Stay at the listen state and wait for discovery. */
+			channel = pwdinfo->listen_channel;
+			pwdinfo->operating_channel = pwdinfo->listen_channel;
+			ch_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
+			bwmode = CHANNEL_WIDTH_20;
+		}
+#ifdef CONFIG_CONCURRENT_MODE
+		else if (rtw_p2p_chk_state(pwdinfo, P2P_STATE_IDLE)) {
+
+			_set_timer(&pwdinfo->ap_p2p_switch_timer, pwdinfo->ext_listen_interval);
+
+			channel = rtw_mi_get_union_chan(padapter);
+			ch_offset = rtw_mi_get_union_offset(padapter);
+			bwmode = rtw_mi_get_union_bw(padapter);
+
+			pwdinfo->operating_channel = channel;
+		}
+#endif
+		else {
+			pwdinfo->operating_channel = pmlmeext->cur_channel;
+
+			channel = pwdinfo->operating_channel;
+			ch_offset = pmlmeext->cur_ch_offset;
+			bwmode = pmlmeext->cur_bwmode;
+		}
+
+		set_channel_bwmode(padapter, channel, ch_offset, bwmode);
+	}
+
+exit:
+	return ret;
+
+}
+
+static int rtw_p2p_set_go_nego_ssid(struct net_device *dev,
+				    struct iw_request_info *info,
+				    union iwreq_data *wrqu, char *extra)
+{
+
+	int ret = 0;
+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
+	struct wifidirect_info *pwdinfo = &(padapter->wdinfo);
+
+	RTW_INFO("[%s] ssid = %s, len = %zu\n", __FUNCTION__, extra, strlen(extra));
+	_rtw_memcpy(pwdinfo->nego_ssid, extra, strlen(extra));
+	pwdinfo->nego_ssidlen = strlen(extra);
+
+	return ret;
+
+}
+
+
+static int rtw_p2p_set_intent(struct net_device *dev,
+			      struct iw_request_info *info,
+			      union iwreq_data *wrqu, char *extra)
+{
+	int							ret = 0;
+	_adapter						*padapter = (_adapter *)rtw_netdev_priv(dev);
+	struct wifidirect_info			*pwdinfo = &(padapter->wdinfo);
+	u8							intent = pwdinfo->intent;
+
+	extra[wrqu->data.length] = 0x00;
+
+	intent = rtw_atoi(extra);
+
+	if (intent <= 15)
+		pwdinfo->intent = intent;
+	else
+		ret = -1;
+
+	RTW_INFO("[%s] intent = %d\n", __FUNCTION__, intent);
+
+	return ret;
+
+}
+
+static int rtw_p2p_set_listen_ch(struct net_device *dev,
+				 struct iw_request_info *info,
+				 union iwreq_data *wrqu, char *extra)
+{
+
+	int ret = 0;
+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
+	struct wifidirect_info *pwdinfo = &(padapter->wdinfo);
+	u8	listen_ch = pwdinfo->listen_channel;	/*	Listen channel number */
+
+	extra[wrqu->data.length] = 0x00;
+	listen_ch = rtw_atoi(extra);
+
+	if ((listen_ch == 1) || (listen_ch == 6) || (listen_ch == 11)) {
+		pwdinfo->listen_channel = listen_ch;
+		set_channel_bwmode(padapter, pwdinfo->listen_channel, HAL_PRIME_CHNL_OFFSET_DONT_CARE, CHANNEL_WIDTH_20);
+	} else
+		ret = -1;
+
+	RTW_INFO("[%s] listen_ch = %d\n", __FUNCTION__, pwdinfo->listen_channel);
+
+	return ret;
+
+}
+
+static int rtw_p2p_set_op_ch(struct net_device *dev,
+			     struct iw_request_info *info,
+			     union iwreq_data *wrqu, char *extra)
+{
+	/*	Commented by Albert 20110524
+	 *	This function is used to set the operating channel if the driver will become the group owner */
+
+	int ret = 0;
+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
+	struct wifidirect_info *pwdinfo = &(padapter->wdinfo);
+	u8	op_ch = pwdinfo->operating_channel;	/*	Operating channel number */
+
+	extra[wrqu->data.length] = 0x00;
+
+	op_ch = (u8) rtw_atoi(extra);
+	if (op_ch > 0)
+		pwdinfo->operating_channel = op_ch;
+	else
+		ret = -1;
+
+	RTW_INFO("[%s] op_ch = %d\n", __FUNCTION__, pwdinfo->operating_channel);
+
+	return ret;
+
+}
+
+
+static int rtw_p2p_profilefound(struct net_device *dev,
+				struct iw_request_info *info,
+				union iwreq_data *wrqu, char *extra)
+{
+
+	int ret = 0;
+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
+	struct wifidirect_info *pwdinfo = &(padapter->wdinfo);
+
+	/*	Comment by Albert 2010/10/13 */
+	/*	Input data format: */
+	/*	Ex:  0 */
+	/*	Ex:  1XX:XX:XX:XX:XX:XXYYSSID */
+	/*	0 => Reflush the profile record list. */
+	/*	1 => Add the profile list */
+	/*	XX:XX:XX:XX:XX:XX => peer's MAC Address ( ex: 00:E0:4C:00:00:01 ) */
+	/*	YY => SSID Length */
+	/*	SSID => SSID for persistence group */
+
+	RTW_INFO("[%s] In value = %s, len = %d\n", __FUNCTION__, extra, wrqu->data.length - 1);
+
+
+	/*	The upper application should pass the SSID to driver by using this rtw_p2p_profilefound function. */
+	if (!rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE)) {
+		if (extra[0] == '0') {
+			/*	Remove all the profile information of wifidirect_info structure. */
+			_rtw_memset(&pwdinfo->profileinfo[0], 0x00, sizeof(struct profile_info) * P2P_MAX_PERSISTENT_GROUP_NUM);
+			pwdinfo->profileindex = 0;
+		} else {
+			if (pwdinfo->profileindex >= P2P_MAX_PERSISTENT_GROUP_NUM)
+				ret = -1;
+			else {
+				int jj, kk;
+
+				/*	Add this profile information into pwdinfo->profileinfo */
+				/*	Ex:  1XX:XX:XX:XX:XX:XXYYSSID */
+				for (jj = 0, kk = 1; jj < ETH_ALEN; jj++, kk += 3)
+					pwdinfo->profileinfo[pwdinfo->profileindex].peermac[jj] = key_2char2num(extra[kk], extra[kk + 1]);
+
+				/* pwdinfo->profileinfo[pwdinfo->profileindex].ssidlen = ( extra[18] - '0' ) * 10 + ( extra[19] - '0' ); */
+				/* _rtw_memcpy( pwdinfo->profileinfo[pwdinfo->profileindex].ssid, &extra[20], pwdinfo->profileinfo[pwdinfo->profileindex].ssidlen ); */
+				pwdinfo->profileindex++;
+			}
+		}
+	}
+
+	return ret;
+
+}
+
+static int rtw_p2p_setDN(struct net_device *dev,
+			 struct iw_request_info *info,
+			 union iwreq_data *wrqu, char *extra)
+{
+
+	int ret = 0;
+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
+	struct wifidirect_info *pwdinfo = &(padapter->wdinfo);
+
+
+	RTW_INFO("[%s] %s %d\n", __FUNCTION__, extra, wrqu->data.length - 1);
+	_rtw_memset(pwdinfo->device_name, 0x00, WPS_MAX_DEVICE_NAME_LEN);
+	_rtw_memcpy(pwdinfo->device_name, extra, wrqu->data.length - 1);
+	pwdinfo->device_name_len = wrqu->data.length - 1;
+
+	return ret;
+
+}
+
+
+static int rtw_p2p_get_status(struct net_device *dev,
+			      struct iw_request_info *info,
+			      union iwreq_data *wrqu, char *extra)
+{
+
+	int ret = 0;
+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
+	struct wifidirect_info	*pwdinfo = &(padapter->wdinfo);
+
+	if (padapter->bShowGetP2PState) {
+		RTW_INFO("[%s] Role = %d, Status = %d, peer addr = %.2X:%.2X:%.2X:%.2X:%.2X:%.2X\n", __FUNCTION__, rtw_p2p_role(pwdinfo), rtw_p2p_state(pwdinfo),
+			pwdinfo->p2p_peer_interface_addr[0], pwdinfo->p2p_peer_interface_addr[1], pwdinfo->p2p_peer_interface_addr[2],
+			pwdinfo->p2p_peer_interface_addr[3], pwdinfo->p2p_peer_interface_addr[4], pwdinfo->p2p_peer_interface_addr[5]);
+	}
+
+	/*	Commented by Albert 2010/10/12 */
+	/*	Because of the output size limitation, I had removed the "Role" information. */
+	/*	About the "Role" information, we will use the new private IOCTL to get the "Role" information. */
+	sprintf(extra, "\n\nStatus=%.2d\n", rtw_p2p_state(pwdinfo));
+	wrqu->data.length = strlen(extra);
+
+	return ret;
+
+}
+
+/*	Commented by Albert 20110520
+ *	This function will return the config method description
+ *	This config method description will show us which config method the remote P2P device is intented to use
+ *	by sending the provisioning discovery request frame. */
+
+static int rtw_p2p_get_req_cm(struct net_device *dev,
+			      struct iw_request_info *info,
+			      union iwreq_data *wrqu, char *extra)
+{
+
+	int ret = 0;
+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
+	struct wifidirect_info	*pwdinfo = &(padapter->wdinfo);
+
+	sprintf(extra, "\n\nCM=%s\n", pwdinfo->rx_prov_disc_info.strconfig_method_desc_of_prov_disc_req);
+	wrqu->data.length = strlen(extra);
+	return ret;
+
+}
+
+
+static int rtw_p2p_get_role(struct net_device *dev,
+			    struct iw_request_info *info,
+			    union iwreq_data *wrqu, char *extra)
+{
+
+	int ret = 0;
+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
+	struct wifidirect_info	*pwdinfo = &(padapter->wdinfo);
+
+	RTW_INFO("[%s] Role = %d, Status = %d, peer addr = %.2X:%.2X:%.2X:%.2X:%.2X:%.2X\n", __FUNCTION__, rtw_p2p_role(pwdinfo), rtw_p2p_state(pwdinfo),
+		pwdinfo->p2p_peer_interface_addr[0], pwdinfo->p2p_peer_interface_addr[1], pwdinfo->p2p_peer_interface_addr[2],
+		pwdinfo->p2p_peer_interface_addr[3], pwdinfo->p2p_peer_interface_addr[4], pwdinfo->p2p_peer_interface_addr[5]);
+
+	sprintf(extra, "\n\nRole=%.2d\n", rtw_p2p_role(pwdinfo));
+	wrqu->data.length = strlen(extra);
+	return ret;
+
+}
+
+
+static int rtw_p2p_get_peer_ifaddr(struct net_device *dev,
+				   struct iw_request_info *info,
+				   union iwreq_data *wrqu, char *extra)
+{
+
+	int ret = 0;
+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
+	struct wifidirect_info	*pwdinfo = &(padapter->wdinfo);
+
+
+	RTW_INFO("[%s] Role = %d, Status = %d, peer addr = %.2X:%.2X:%.2X:%.2X:%.2X:%.2X\n", __FUNCTION__, rtw_p2p_role(pwdinfo), rtw_p2p_state(pwdinfo),
+		pwdinfo->p2p_peer_interface_addr[0], pwdinfo->p2p_peer_interface_addr[1], pwdinfo->p2p_peer_interface_addr[2],
+		pwdinfo->p2p_peer_interface_addr[3], pwdinfo->p2p_peer_interface_addr[4], pwdinfo->p2p_peer_interface_addr[5]);
+
+	sprintf(extra, "\nMAC %.2X:%.2X:%.2X:%.2X:%.2X:%.2X",
+		pwdinfo->p2p_peer_interface_addr[0], pwdinfo->p2p_peer_interface_addr[1], pwdinfo->p2p_peer_interface_addr[2],
+		pwdinfo->p2p_peer_interface_addr[3], pwdinfo->p2p_peer_interface_addr[4], pwdinfo->p2p_peer_interface_addr[5]);
+	wrqu->data.length = strlen(extra);
+	return ret;
+
+}
+
+static int rtw_p2p_get_peer_devaddr(struct net_device *dev,
+				    struct iw_request_info *info,
+				    union iwreq_data *wrqu, char *extra)
+
+{
+
+	int ret = 0;
+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
+	struct wifidirect_info	*pwdinfo = &(padapter->wdinfo);
+
+	RTW_INFO("[%s] Role = %d, Status = %d, peer addr = %.2X:%.2X:%.2X:%.2X:%.2X:%.2X\n", __FUNCTION__, rtw_p2p_role(pwdinfo), rtw_p2p_state(pwdinfo),
+		pwdinfo->rx_prov_disc_info.peerDevAddr[0], pwdinfo->rx_prov_disc_info.peerDevAddr[1],
+		pwdinfo->rx_prov_disc_info.peerDevAddr[2], pwdinfo->rx_prov_disc_info.peerDevAddr[3],
+		pwdinfo->rx_prov_disc_info.peerDevAddr[4], pwdinfo->rx_prov_disc_info.peerDevAddr[5]);
+	sprintf(extra, "\n%.2X%.2X%.2X%.2X%.2X%.2X",
+		pwdinfo->rx_prov_disc_info.peerDevAddr[0], pwdinfo->rx_prov_disc_info.peerDevAddr[1],
+		pwdinfo->rx_prov_disc_info.peerDevAddr[2], pwdinfo->rx_prov_disc_info.peerDevAddr[3],
+		pwdinfo->rx_prov_disc_info.peerDevAddr[4], pwdinfo->rx_prov_disc_info.peerDevAddr[5]);
+	wrqu->data.length = strlen(extra);
+	return ret;
+
+}
+
+static int rtw_p2p_get_peer_devaddr_by_invitation(struct net_device *dev,
+		struct iw_request_info *info,
+		union iwreq_data *wrqu, char *extra)
+
+{
+
+	int ret = 0;
+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
+	struct wifidirect_info	*pwdinfo = &(padapter->wdinfo);
+
+	RTW_INFO("[%s] Role = %d, Status = %d, peer addr = %.2X:%.2X:%.2X:%.2X:%.2X:%.2X\n", __FUNCTION__, rtw_p2p_role(pwdinfo), rtw_p2p_state(pwdinfo),
+		pwdinfo->p2p_peer_device_addr[0], pwdinfo->p2p_peer_device_addr[1],
+		pwdinfo->p2p_peer_device_addr[2], pwdinfo->p2p_peer_device_addr[3],
+		pwdinfo->p2p_peer_device_addr[4], pwdinfo->p2p_peer_device_addr[5]);
+	sprintf(extra, "\nMAC %.2X:%.2X:%.2X:%.2X:%.2X:%.2X",
+		pwdinfo->p2p_peer_device_addr[0], pwdinfo->p2p_peer_device_addr[1],
+		pwdinfo->p2p_peer_device_addr[2], pwdinfo->p2p_peer_device_addr[3],
+		pwdinfo->p2p_peer_device_addr[4], pwdinfo->p2p_peer_device_addr[5]);
+	wrqu->data.length = strlen(extra);
+	return ret;
+
+}
+
+static int rtw_p2p_get_groupid(struct net_device *dev,
+			       struct iw_request_info *info,
+			       union iwreq_data *wrqu, char *extra)
+
+{
+
+	int ret = 0;
+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
+	struct wifidirect_info	*pwdinfo = &(padapter->wdinfo);
+
+	sprintf(extra, "\n%.2X:%.2X:%.2X:%.2X:%.2X:%.2X %s",
+		pwdinfo->groupid_info.go_device_addr[0], pwdinfo->groupid_info.go_device_addr[1],
+		pwdinfo->groupid_info.go_device_addr[2], pwdinfo->groupid_info.go_device_addr[3],
+		pwdinfo->groupid_info.go_device_addr[4], pwdinfo->groupid_info.go_device_addr[5],
+		pwdinfo->groupid_info.ssid);
+	wrqu->data.length = strlen(extra);
+	return ret;
+
+}
+
+static int rtw_p2p_get_op_ch(struct net_device *dev,
+			     struct iw_request_info *info,
+			     union iwreq_data *wrqu, char *extra)
+
+{
+
+	int ret = 0;
+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
+	struct wifidirect_info	*pwdinfo = &(padapter->wdinfo);
+
+
+	RTW_INFO("[%s] Op_ch = %02x\n", __FUNCTION__, pwdinfo->operating_channel);
+
+	sprintf(extra, "\n\nOp_ch=%.2d\n", pwdinfo->operating_channel);
+	wrqu->data.length = strlen(extra);
+	return ret;
+
+}
+
+static int rtw_p2p_get_wps_configmethod(struct net_device *dev,
+					struct iw_request_info *info,
+			union iwreq_data *wrqu, char *extra, char *subcmd)
+{
+
+	int ret = 0;
+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
+	u8 peerMAC[ETH_ALEN] = { 0x00 };
+	struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
+	_irqL irqL;
+	_list *plist, *phead;
+	_queue *queue = &(pmlmepriv->scanned_queue);
+	struct wlan_network *pnetwork = NULL;
+	u8 blnMatch = 0;
+	u16	attr_content = 0;
+	uint attr_contentlen = 0;
+	u8	attr_content_str[P2P_PRIVATE_IOCTL_SET_LEN] = { 0x00 };
+
+	/*	Commented by Albert 20110727 */
+	/*	The input data is the MAC address which the application wants to know its WPS config method. */
+	/*	After knowing its WPS config method, the application can decide the config method for provisioning discovery. */
+	/*	Format: iwpriv wlanx p2p_get_wpsCM 00:E0:4C:00:00:05 */
+
+	RTW_INFO("[%s] data = %s\n", __FUNCTION__, subcmd);
+
+	macstr2num(peerMAC, subcmd);
+
+	_enter_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);
+
+	phead = get_list_head(queue);
+	plist = get_next(phead);
+
+	while (1) {
+		if (rtw_end_of_queue_search(phead, plist) == _TRUE)
+			break;
+
+		pnetwork = LIST_CONTAINOR(plist, struct wlan_network, list);
+		if (_rtw_memcmp(pnetwork->network.MacAddress, peerMAC, ETH_ALEN)) {
+			u8 *wpsie;
+			uint	wpsie_len = 0;
+
+			/*	The mac address is matched. */
+
+			wpsie = rtw_get_wps_ie_from_scan_queue(&pnetwork->network.IEs[0], pnetwork->network.IELength, NULL, &wpsie_len, pnetwork->network.Reserved[0]);
+			if (wpsie) {
+				rtw_get_wps_attr_content(wpsie, wpsie_len, WPS_ATTR_CONF_METHOD, (u8 *)&attr_content, &attr_contentlen);
+				if (attr_contentlen) {
+					attr_content = be16_to_cpu(attr_content);
+					sprintf(attr_content_str, "\n\nM=%.4d", attr_content);
+					blnMatch = 1;
+				}
+			}
+
+			break;
+		}
+
+		plist = get_next(plist);
+
+	}
+
+	_exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);
+
+	if (!blnMatch)
+		sprintf(attr_content_str, "\n\nM=0000");
+
+	wrqu->data.length = strlen(attr_content_str);
+	_rtw_memcpy(extra, attr_content_str, wrqu->data.length);
+
+	return ret;
+
+}
+
+#ifdef CONFIG_WFD
+static int rtw_p2p_get_peer_wfd_port(struct net_device *dev,
+				     struct iw_request_info *info,
+				     union iwreq_data *wrqu, char *extra)
+{
+
+	int ret = 0;
+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
+	struct wifidirect_info	*pwdinfo = &(padapter->wdinfo);
+
+	RTW_INFO("[%s] p2p_state = %d\n", __FUNCTION__, rtw_p2p_state(pwdinfo));
+
+	sprintf(extra, "\n\nPort=%d\n", pwdinfo->wfd_info->peer_rtsp_ctrlport);
+	RTW_INFO("[%s] remote port = %d\n", __FUNCTION__, pwdinfo->wfd_info->peer_rtsp_ctrlport);
+
+	wrqu->data.length = strlen(extra);
+	return ret;
+
+}
+
+static int rtw_p2p_get_peer_wfd_preferred_connection(struct net_device *dev,
+		struct iw_request_info *info,
+		union iwreq_data *wrqu, char *extra)
+{
+
+	int ret = 0;
+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
+	struct wifidirect_info	*pwdinfo = &(padapter->wdinfo);
+
+	sprintf(extra, "\n\nwfd_pc=%d\n", pwdinfo->wfd_info->wfd_pc);
+	RTW_INFO("[%s] wfd_pc = %d\n", __FUNCTION__, pwdinfo->wfd_info->wfd_pc);
+
+	wrqu->data.length = strlen(extra);
+	pwdinfo->wfd_info->wfd_pc = _FALSE;	/*	Reset the WFD preferred connection to P2P */
+	return ret;
+
+}
+
+static int rtw_p2p_get_peer_wfd_session_available(struct net_device *dev,
+		struct iw_request_info *info,
+		union iwreq_data *wrqu, char *extra)
+{
+
+	int ret = 0;
+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
+	struct wifidirect_info	*pwdinfo = &(padapter->wdinfo);
+
+	sprintf(extra, "\n\nwfd_sa=%d\n", pwdinfo->wfd_info->peer_session_avail);
+	RTW_INFO("[%s] wfd_sa = %d\n", __FUNCTION__, pwdinfo->wfd_info->peer_session_avail);
+
+	wrqu->data.length = strlen(extra);
+	pwdinfo->wfd_info->peer_session_avail = _TRUE;	/*	Reset the WFD session available */
+	return ret;
+
+}
+#endif /* CONFIG_WFD */
+
+static int rtw_p2p_get_go_device_address(struct net_device *dev,
+		struct iw_request_info *info,
+		union iwreq_data *wrqu, char *extra, char *subcmd)
+{
+
+	int ret = 0;
+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
+	u8 peerMAC[ETH_ALEN] = { 0x00 };
+	struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
+	_irqL irqL;
+	_list *plist, *phead;
+	_queue *queue	= &(pmlmepriv->scanned_queue);
+	struct wlan_network *pnetwork = NULL;
+	u8 blnMatch = 0;
+	u8 *p2pie;
+	uint p2pielen = 0, attr_contentlen = 0;
+	u8 attr_content[100] = { 0x00 };
+	u8 go_devadd_str[P2P_PRIVATE_IOCTL_SET_LEN] = { 0x00 };
+
+	/*	Commented by Albert 20121209 */
+	/*	The input data is the GO's interface address which the application wants to know its device address. */
+	/*	Format: iwpriv wlanx p2p_get2 go_devadd=00:E0:4C:00:00:05 */
+
+	RTW_INFO("[%s] data = %s\n", __FUNCTION__, subcmd);
+
+	macstr2num(peerMAC, subcmd);
+
+	_enter_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);
+
+	phead = get_list_head(queue);
+	plist = get_next(phead);
+
+	while (1) {
+		if (rtw_end_of_queue_search(phead, plist) == _TRUE)
+			break;
+
+		pnetwork = LIST_CONTAINOR(plist, struct wlan_network, list);
+		if (_rtw_memcmp(pnetwork->network.MacAddress, peerMAC, ETH_ALEN)) {
+			/*	Commented by Albert 2011/05/18 */
+			/*	Match the device address located in the P2P IE */
+			/*	This is for the case that the P2P device address is not the same as the P2P interface address. */
+
+			p2pie = rtw_bss_ex_get_p2p_ie(&pnetwork->network, NULL, &p2pielen);
+			if (p2pie) {
+				while (p2pie) {
+					/*	The P2P Device ID attribute is included in the Beacon frame. */
+					/*	The P2P Device Info attribute is included in the probe response frame. */
+
+					_rtw_memset(attr_content, 0x00, 100);
+					if (rtw_get_p2p_attr_content(p2pie, p2pielen, P2P_ATTR_DEVICE_ID, attr_content, &attr_contentlen)) {
+						/*	Handle the P2P Device ID attribute of Beacon first */
+						blnMatch = 1;
+						break;
+
+					} else if (rtw_get_p2p_attr_content(p2pie, p2pielen, P2P_ATTR_DEVICE_INFO, attr_content, &attr_contentlen)) {
+						/*	Handle the P2P Device Info attribute of probe response */
+						blnMatch = 1;
+						break;
+					}
+
+					/* Get the next P2P IE */
+					p2pie = rtw_get_p2p_ie(p2pie + p2pielen, BSS_EX_TLV_IES_LEN(&pnetwork->network) - (p2pie + p2pielen - BSS_EX_TLV_IES(&pnetwork->network)), NULL, &p2pielen);
+				}
+			}
+		}
+
+		plist = get_next(plist);
+
+	}
+
+	_exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);
+
+	if (!blnMatch)
+		sprintf(go_devadd_str, "\n\ndev_add=NULL");
+	else {
+		sprintf(go_devadd_str, "\n\ndev_add=%.2X:%.2X:%.2X:%.2X:%.2X:%.2X",
+			attr_content[0], attr_content[1], attr_content[2], attr_content[3], attr_content[4], attr_content[5]);
+	}
+
+	wrqu->data.length = strlen(go_devadd_str);
+	_rtw_memcpy(extra, go_devadd_str, wrqu->data.length);
+
+	return ret;
+
+}
+
+static int rtw_p2p_get_device_type(struct net_device *dev,
+				   struct iw_request_info *info,
+			   union iwreq_data *wrqu, char *extra, char *subcmd)
+{
+
+	int ret = 0;
+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
+	u8 peerMAC[ETH_ALEN] = { 0x00 };
+	struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
+	_irqL irqL;
+	_list *plist, *phead;
+	_queue *queue = &(pmlmepriv->scanned_queue);
+	struct wlan_network *pnetwork = NULL;
+	u8 blnMatch = 0;
+	u8 dev_type[8] = { 0x00 };
+	uint dev_type_len = 0;
+	u8 dev_type_str[P2P_PRIVATE_IOCTL_SET_LEN] = { 0x00 };    /* +9 is for the str "dev_type=", we have to clear it at wrqu->data.pointer */
+
+	/*	Commented by Albert 20121209 */
+	/*	The input data is the MAC address which the application wants to know its device type. */
+	/*	Such user interface could know the device type. */
+	/*	Format: iwpriv wlanx p2p_get2 dev_type=00:E0:4C:00:00:05 */
+
+	RTW_INFO("[%s] data = %s\n", __FUNCTION__, subcmd);
+
+	macstr2num(peerMAC, subcmd);
+
+	_enter_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);
+
+	phead = get_list_head(queue);
+	plist = get_next(phead);
+
+	while (1) {
+		if (rtw_end_of_queue_search(phead, plist) == _TRUE)
+			break;
+
+		pnetwork = LIST_CONTAINOR(plist, struct wlan_network, list);
+		if (_rtw_memcmp(pnetwork->network.MacAddress, peerMAC, ETH_ALEN)) {
+			u8 *wpsie;
+			uint	wpsie_len = 0;
+
+			/*	The mac address is matched. */
+
+			wpsie = rtw_get_wps_ie_from_scan_queue(&pnetwork->network.IEs[0], pnetwork->network.IELength, NULL, &wpsie_len, pnetwork->network.Reserved[0]);
+			if (wpsie) {
+				rtw_get_wps_attr_content(wpsie, wpsie_len, WPS_ATTR_PRIMARY_DEV_TYPE, dev_type, &dev_type_len);
+				if (dev_type_len) {
+					u16	type = 0;
+
+					_rtw_memcpy(&type, dev_type, 2);
+					type = be16_to_cpu(type);
+					sprintf(dev_type_str, "\n\nN=%.2d", type);
+					blnMatch = 1;
+				}
+			}
+			break;
+		}
+
+		plist = get_next(plist);
+
+	}
+
+	_exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);
+
+	if (!blnMatch)
+		sprintf(dev_type_str, "\n\nN=00");
+
+	wrqu->data.length = strlen(dev_type_str);
+	_rtw_memcpy(extra, dev_type_str, wrqu->data.length);
+
+	return ret;
+
+}
+
+static int rtw_p2p_get_device_name(struct net_device *dev,
+				   struct iw_request_info *info,
+			   union iwreq_data *wrqu, char *extra, char *subcmd)
+{
+
+	int ret = 0;
+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
+	u8 peerMAC[ETH_ALEN] = { 0x00 };
+	struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
+	_irqL irqL;
+	_list *plist, *phead;
+	_queue *queue = &(pmlmepriv->scanned_queue);
+	struct wlan_network *pnetwork = NULL;
+	u8 blnMatch = 0;
+	u8 dev_name[WPS_MAX_DEVICE_NAME_LEN] = { 0x00 };
+	uint dev_len = 0;
+	u8 dev_name_str[P2P_PRIVATE_IOCTL_SET_LEN] = { 0x00 };
+
+	/*	Commented by Albert 20121225 */
+	/*	The input data is the MAC address which the application wants to know its device name. */
+	/*	Such user interface could show peer device's device name instead of ssid. */
+	/*	Format: iwpriv wlanx p2p_get2 devN=00:E0:4C:00:00:05 */
+
+	RTW_INFO("[%s] data = %s\n", __FUNCTION__, subcmd);
+
+	macstr2num(peerMAC, subcmd);
+
+	_enter_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);
+
+	phead = get_list_head(queue);
+	plist = get_next(phead);
+
+	while (1) {
+		if (rtw_end_of_queue_search(phead, plist) == _TRUE)
+			break;
+
+		pnetwork = LIST_CONTAINOR(plist, struct wlan_network, list);
+		if (_rtw_memcmp(pnetwork->network.MacAddress, peerMAC, ETH_ALEN)) {
+			u8 *wpsie;
+			uint	wpsie_len = 0;
+
+			/*	The mac address is matched. */
+
+			wpsie = rtw_get_wps_ie_from_scan_queue(&pnetwork->network.IEs[0], pnetwork->network.IELength, NULL, &wpsie_len, pnetwork->network.Reserved[0]);
+			if (wpsie) {
+				rtw_get_wps_attr_content(wpsie, wpsie_len, WPS_ATTR_DEVICE_NAME, dev_name, &dev_len);
+				if (dev_len) {
+					sprintf(dev_name_str, "\n\nN=%s", dev_name);
+					blnMatch = 1;
+				}
+			}
+			break;
+		}
+
+		plist = get_next(plist);
+
+	}
+
+	_exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);
+
+	if (!blnMatch)
+		sprintf(dev_name_str, "\n\nN=0000");
+
+	wrqu->data.length = strlen(dev_name_str);
+	_rtw_memcpy(extra, dev_name_str, wrqu->data.length);
+
+	return ret;
+
+}
+
+static int rtw_p2p_get_invitation_procedure(struct net_device *dev,
+		struct iw_request_info *info,
+		union iwreq_data *wrqu, char *extra, char *subcmd)
+{
+
+	int ret = 0;
+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
+	u8 peerMAC[ETH_ALEN] = { 0x00 };
+	struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
+	_irqL irqL;
+	_list *plist, *phead;
+	_queue *queue	= &(pmlmepriv->scanned_queue);
+	struct wlan_network *pnetwork = NULL;
+	u8 blnMatch = 0;
+	u8 *p2pie;
+	uint p2pielen = 0, attr_contentlen = 0;
+	u8 attr_content[2] = { 0x00 };
+	u8 inv_proc_str[P2P_PRIVATE_IOCTL_SET_LEN] = { 0x00 };
+
+	/*	Commented by Ouden 20121226 */
+	/*	The application wants to know P2P initation procedure is support or not. */
+	/*	Format: iwpriv wlanx p2p_get2 InvProc=00:E0:4C:00:00:05 */
+
+	RTW_INFO("[%s] data = %s\n", __FUNCTION__, subcmd);
+
+	macstr2num(peerMAC, subcmd);
+
+	_enter_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);
+
+	phead = get_list_head(queue);
+	plist = get_next(phead);
+
+	while (1) {
+		if (rtw_end_of_queue_search(phead, plist) == _TRUE)
+			break;
+
+		pnetwork = LIST_CONTAINOR(plist, struct wlan_network, list);
+		if (_rtw_memcmp(pnetwork->network.MacAddress, peerMAC, ETH_ALEN)) {
+			/*	Commented by Albert 20121226 */
+			/*	Match the device address located in the P2P IE */
+			/*	This is for the case that the P2P device address is not the same as the P2P interface address. */
+
+			p2pie = rtw_bss_ex_get_p2p_ie(&pnetwork->network, NULL, &p2pielen);
+			if (p2pie) {
+				while (p2pie) {
+					/* _rtw_memset( attr_content, 0x00, 2); */
+					if (rtw_get_p2p_attr_content(p2pie, p2pielen, P2P_ATTR_CAPABILITY, attr_content, &attr_contentlen)) {
+						/*	Handle the P2P capability attribute */
+						blnMatch = 1;
+						break;
+
+					}
+
+					/* Get the next P2P IE */
+					p2pie = rtw_get_p2p_ie(p2pie + p2pielen, BSS_EX_TLV_IES_LEN(&pnetwork->network) - (p2pie + p2pielen - BSS_EX_TLV_IES(&pnetwork->network)), NULL, &p2pielen);
+				}
+			}
+		}
+
+		plist = get_next(plist);
+
+	}
+
+	_exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);
+
+	if (!blnMatch)
+		sprintf(inv_proc_str, "\nIP=-1");
+	else {
+		if ((attr_content[0] & 0x20) == 0x20)
+			sprintf(inv_proc_str, "\nIP=1");
+		else
+			sprintf(inv_proc_str, "\nIP=0");
+	}
+
+	wrqu->data.length = strlen(inv_proc_str);
+	_rtw_memcpy(extra, inv_proc_str, wrqu->data.length);
+
+	return ret;
+
+}
+
+static int rtw_p2p_connect(struct net_device *dev,
+			   struct iw_request_info *info,
+			   union iwreq_data *wrqu, char *extra)
+{
+
+	int ret = 0;
+	_adapter				*padapter = (_adapter *)rtw_netdev_priv(dev);
+	struct wifidirect_info	*pwdinfo = &(padapter->wdinfo);
+	u8					peerMAC[ETH_ALEN] = { 0x00 };
+	int					jj, kk;
+	struct mlme_priv		*pmlmepriv = &padapter->mlmepriv;
+	_irqL				irqL;
+	_list					*plist, *phead;
+	_queue				*queue	= &(pmlmepriv->scanned_queue);
+	struct	wlan_network	*pnetwork = NULL;
+	uint					uintPeerChannel = 0;
+
+	/*	Commented by Albert 20110304 */
+	/*	The input data contains two informations. */
+	/*	1. First information is the MAC address which wants to formate with */
+	/*	2. Second information is the WPS PINCode or "pbc" string for push button method */
+	/*	Format: 00:E0:4C:00:00:05 */
+	/*	Format: 00:E0:4C:00:00:05 */
+
+	RTW_INFO("[%s] data = %s\n", __FUNCTION__, extra);
+
+	if (pwdinfo->p2p_state == P2P_STATE_NONE) {
+		RTW_INFO("[%s] WiFi Direct is disable!\n", __FUNCTION__);
+		return ret;
+	}
+
+#ifdef CONFIG_INTEL_WIDI
+	if (check_fwstate(pmlmepriv, _FW_UNDER_SURVEY) == _TRUE) {
+		RTW_INFO("[%s] WiFi is under survey!\n", __FUNCTION__);
+		return ret;
+	}
+#endif /* CONFIG_INTEL_WIDI	 */
+
+	if (pwdinfo->ui_got_wps_info == P2P_NO_WPSINFO)
+		return -1;
+
+	for (jj = 0, kk = 0; jj < ETH_ALEN; jj++, kk += 3)
+		peerMAC[jj] = key_2char2num(extra[kk], extra[kk + 1]);
+
+	_enter_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);
+
+	phead = get_list_head(queue);
+	plist = get_next(phead);
+
+	while (1) {
+		if (rtw_end_of_queue_search(phead, plist) == _TRUE)
+			break;
+
+		pnetwork = LIST_CONTAINOR(plist, struct wlan_network, list);
+		if (_rtw_memcmp(pnetwork->network.MacAddress, peerMAC, ETH_ALEN)) {
+			if (pnetwork->network.Configuration.DSConfig != 0)
+				uintPeerChannel = pnetwork->network.Configuration.DSConfig;
+			else if (pwdinfo->nego_req_info.peer_ch != 0)
+				uintPeerChannel = pnetwork->network.Configuration.DSConfig = pwdinfo->nego_req_info.peer_ch;
+			else {
+				/* Unexpected case */
+				uintPeerChannel = 0;
+				RTW_INFO("%s  uintPeerChannel = 0\n", __func__);
+			}
+			break;
+		}
+
+		plist = get_next(plist);
+
+	}
+
+	_exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);
+
+	if (uintPeerChannel) {
+#ifdef CONFIG_CONCURRENT_MODE
+		if (rtw_mi_check_status(padapter, MI_LINKED))
+			_cancel_timer_ex(&pwdinfo->ap_p2p_switch_timer);
+#endif /* CONFIG_CONCURRENT_MODE */
+
+		_rtw_memset(&pwdinfo->nego_req_info, 0x00, sizeof(struct tx_nego_req_info));
+		_rtw_memset(&pwdinfo->groupid_info, 0x00, sizeof(struct group_id_info));
+
+		pwdinfo->nego_req_info.peer_channel_num[0] = uintPeerChannel;
+		_rtw_memcpy(pwdinfo->nego_req_info.peerDevAddr, pnetwork->network.MacAddress, ETH_ALEN);
+		pwdinfo->nego_req_info.benable = _TRUE;
+
+		_cancel_timer_ex(&pwdinfo->restore_p2p_state_timer);
+		if (rtw_p2p_state(pwdinfo) != P2P_STATE_GONEGO_OK) {
+			/*	Restore to the listen state if the current p2p state is not nego OK */
+			rtw_p2p_set_state(pwdinfo, P2P_STATE_LISTEN);
+		}
+
+		rtw_p2p_set_pre_state(pwdinfo, rtw_p2p_state(pwdinfo));
+		rtw_p2p_set_state(pwdinfo, P2P_STATE_GONEGO_ING);
+
+#ifdef CONFIG_CONCURRENT_MODE
+		if (rtw_mi_check_status(padapter, MI_LINKED)) {
+			u8 union_ch = rtw_mi_get_union_chan(padapter);
+			u8 union_bw = rtw_mi_get_union_bw(padapter);
+			u8 union_offset = rtw_mi_get_union_offset(padapter);
+
+			set_channel_bwmode(padapter, union_ch, union_offset, union_bw);
+			rtw_leave_opch(padapter);
+		}
+#endif /* CONFIG_CONCURRENT_MODE */
+
+		RTW_INFO("[%s] Start PreTx Procedure!\n", __FUNCTION__);
+		_set_timer(&pwdinfo->pre_tx_scan_timer, P2P_TX_PRESCAN_TIMEOUT);
+#ifdef CONFIG_CONCURRENT_MODE
+		if (rtw_mi_check_status(padapter, MI_LINKED))
+			_set_timer(&pwdinfo->restore_p2p_state_timer, P2P_CONCURRENT_GO_NEGO_TIMEOUT);
+		else
+			_set_timer(&pwdinfo->restore_p2p_state_timer, P2P_GO_NEGO_TIMEOUT);
+#else
+		_set_timer(&pwdinfo->restore_p2p_state_timer, P2P_GO_NEGO_TIMEOUT);
+#endif /* CONFIG_CONCURRENT_MODE		 */
+
+	} else {
+		RTW_INFO("[%s] Not Found in Scanning Queue~\n", __FUNCTION__);
+#ifdef CONFIG_INTEL_WIDI
+		_cancel_timer_ex(&pwdinfo->restore_p2p_state_timer);
+		rtw_p2p_set_state(pwdinfo, P2P_STATE_FIND_PHASE_SEARCH);
+		rtw_p2p_findphase_ex_set(pwdinfo, P2P_FINDPHASE_EX_NONE);
+		rtw_free_network_queue(padapter, _TRUE);
+		/**
+		 * For WiDi, if we can't find candidate device in scanning queue,
+		 * driver will do scanning itself
+		 */
+		_enter_critical_bh(&pmlmepriv->lock, &irqL);
+		rtw_sitesurvey_cmd(padapter, NULL);
+		_exit_critical_bh(&pmlmepriv->lock, &irqL);
+#endif /* CONFIG_INTEL_WIDI */
+		ret = -1;
+	}
+exit:
+	return ret;
+}
+
+static int rtw_p2p_invite_req(struct net_device *dev,
+			      struct iw_request_info *info,
+			      union iwreq_data *wrqu, char *extra)
+{
+
+	int ret = 0;
+	_adapter					*padapter = (_adapter *)rtw_netdev_priv(dev);
+	struct wifidirect_info		*pwdinfo = &(padapter->wdinfo);
+	int						jj, kk;
+	struct mlme_priv			*pmlmepriv = &padapter->mlmepriv;
+	_list						*plist, *phead;
+	_queue					*queue	= &(pmlmepriv->scanned_queue);
+	struct	wlan_network		*pnetwork = NULL;
+	uint						uintPeerChannel = 0;
+	u8						attr_content[50] = { 0x00 };
+	u8						*p2pie;
+	uint						p2pielen = 0, attr_contentlen = 0;
+	_irqL					irqL;
+	struct tx_invite_req_info	*pinvite_req_info = &pwdinfo->invitereq_info;
+
+	/*	Commented by Albert 20120321 */
+	/*	The input data contains two informations. */
+	/*	1. First information is the P2P device address which you want to send to.	 */
+	/*	2. Second information is the group id which combines with GO's mac address, space and GO's ssid. */
+	/*	Command line sample: iwpriv wlan0 p2p_set invite="00:11:22:33:44:55 00:E0:4C:00:00:05 DIRECT-xy" */
+	/*	Format: 00:11:22:33:44:55 00:E0:4C:00:00:05 DIRECT-xy */
+
+	RTW_INFO("[%s] data = %s\n", __FUNCTION__, extra);
+
+	if (wrqu->data.length <=  37) {
+		RTW_INFO("[%s] Wrong format!\n", __FUNCTION__);
+		return ret;
+	}
+
+	if (rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE)) {
+		RTW_INFO("[%s] WiFi Direct is disable!\n", __FUNCTION__);
+		return ret;
+	} else {
+		/*	Reset the content of struct tx_invite_req_info */
+		pinvite_req_info->benable = _FALSE;
+		_rtw_memset(pinvite_req_info->go_bssid, 0x00, ETH_ALEN);
+		_rtw_memset(pinvite_req_info->go_ssid, 0x00, WLAN_SSID_MAXLEN);
+		pinvite_req_info->ssidlen = 0x00;
+		pinvite_req_info->operating_ch = pwdinfo->operating_channel;
+		_rtw_memset(pinvite_req_info->peer_macaddr, 0x00, ETH_ALEN);
+		pinvite_req_info->token = 3;
+	}
+
+	for (jj = 0, kk = 0; jj < ETH_ALEN; jj++, kk += 3)
+		pinvite_req_info->peer_macaddr[jj] = key_2char2num(extra[kk], extra[kk + 1]);
+
+	_enter_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);
+
+	phead = get_list_head(queue);
+	plist = get_next(phead);
+
+	while (1) {
+		if (rtw_end_of_queue_search(phead, plist) == _TRUE)
+			break;
+
+		pnetwork = LIST_CONTAINOR(plist, struct wlan_network, list);
+
+		/*	Commented by Albert 2011/05/18 */
+		/*	Match the device address located in the P2P IE */
+		/*	This is for the case that the P2P device address is not the same as the P2P interface address. */
+
+		p2pie = rtw_bss_ex_get_p2p_ie(&pnetwork->network, NULL, &p2pielen);
+		if (p2pie) {
+			/*	The P2P Device ID attribute is included in the Beacon frame. */
+			/*	The P2P Device Info attribute is included in the probe response frame. */
+
+			if (rtw_get_p2p_attr_content(p2pie, p2pielen, P2P_ATTR_DEVICE_ID, attr_content, &attr_contentlen)) {
+				/*	Handle the P2P Device ID attribute of Beacon first */
+				if (_rtw_memcmp(attr_content, pinvite_req_info->peer_macaddr, ETH_ALEN)) {
+					uintPeerChannel = pnetwork->network.Configuration.DSConfig;
+					break;
+				}
+			} else if (rtw_get_p2p_attr_content(p2pie, p2pielen, P2P_ATTR_DEVICE_INFO, attr_content, &attr_contentlen)) {
+				/*	Handle the P2P Device Info attribute of probe response */
+				if (_rtw_memcmp(attr_content, pinvite_req_info->peer_macaddr, ETH_ALEN)) {
+					uintPeerChannel = pnetwork->network.Configuration.DSConfig;
+					break;
+				}
+			}
+
+		}
+
+		plist = get_next(plist);
+
+	}
+
+	_exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);
+
+#ifdef CONFIG_WFD
+	if (hal_chk_wl_func(padapter, WL_FUNC_MIRACAST) && uintPeerChannel) {
+		struct wifi_display_info *pwfd_info = pwdinfo->wfd_info;
+		u8 *wfd_ie;
+		uint wfd_ielen = 0;
+
+		wfd_ie = rtw_bss_ex_get_wfd_ie(&pnetwork->network, NULL, &wfd_ielen);
+		if (wfd_ie) {
+			u8 *wfd_devinfo;
+			uint wfd_devlen;
+
+			RTW_INFO("[%s] Found WFD IE!\n", __FUNCTION__);
+			wfd_devinfo = rtw_get_wfd_attr_content(wfd_ie, wfd_ielen, WFD_ATTR_DEVICE_INFO, NULL, &wfd_devlen);
+			if (wfd_devinfo) {
+				u16	wfd_devinfo_field = 0;
+
+				/*	Commented by Albert 20120319 */
+				/*	The first two bytes are the WFD device information field of WFD device information subelement. */
+				/*	In big endian format. */
+				wfd_devinfo_field = RTW_GET_BE16(wfd_devinfo);
+				if (wfd_devinfo_field & WFD_DEVINFO_SESSION_AVAIL)
+					pwfd_info->peer_session_avail = _TRUE;
+				else
+					pwfd_info->peer_session_avail = _FALSE;
+			}
+		}
+
+		if (_FALSE == pwfd_info->peer_session_avail) {
+			RTW_INFO("[%s] WFD Session not avaiable!\n", __FUNCTION__);
+			goto exit;
+		}
+	}
+#endif /* CONFIG_WFD */
+
+	if (uintPeerChannel) {
+#ifdef CONFIG_CONCURRENT_MODE
+		if (rtw_mi_check_status(padapter, MI_LINKED))
+			_cancel_timer_ex(&pwdinfo->ap_p2p_switch_timer);
+#endif /* CONFIG_CONCURRENT_MODE */
+
+		/*	Store the GO's bssid */
+		for (jj = 0, kk = 18; jj < ETH_ALEN; jj++, kk += 3)
+			pinvite_req_info->go_bssid[jj] = key_2char2num(extra[kk], extra[kk + 1]);
+
+		/*	Store the GO's ssid */
+		pinvite_req_info->ssidlen = wrqu->data.length - 36;
+		_rtw_memcpy(pinvite_req_info->go_ssid, &extra[36], (u32) pinvite_req_info->ssidlen);
+		pinvite_req_info->benable = _TRUE;
+		pinvite_req_info->peer_ch = uintPeerChannel;
+
+		rtw_p2p_set_pre_state(pwdinfo, rtw_p2p_state(pwdinfo));
+		rtw_p2p_set_state(pwdinfo, P2P_STATE_TX_INVITE_REQ);
+
+#ifdef CONFIG_CONCURRENT_MODE
+		if (rtw_mi_check_status(padapter, MI_LINKED)) {
+			u8 union_ch = rtw_mi_get_union_chan(padapter);
+			u8 union_bw = rtw_mi_get_union_bw(padapter);
+			u8 union_offset = rtw_mi_get_union_offset(padapter);
+
+			set_channel_bwmode(padapter, union_ch, union_offset, union_bw);
+			rtw_leave_opch(padapter);
+
+		} else
+			set_channel_bwmode(padapter, uintPeerChannel, HAL_PRIME_CHNL_OFFSET_DONT_CARE, CHANNEL_WIDTH_20);
+#else
+		set_channel_bwmode(padapter, uintPeerChannel, HAL_PRIME_CHNL_OFFSET_DONT_CARE, CHANNEL_WIDTH_20);
+#endif/*CONFIG_CONCURRENT_MODE*/
+
+		_set_timer(&pwdinfo->pre_tx_scan_timer, P2P_TX_PRESCAN_TIMEOUT);
+
+#ifdef CONFIG_CONCURRENT_MODE
+		if (rtw_mi_check_status(padapter, MI_LINKED))
+			_set_timer(&pwdinfo->restore_p2p_state_timer, P2P_CONCURRENT_INVITE_TIMEOUT);
+		else
+			_set_timer(&pwdinfo->restore_p2p_state_timer, P2P_INVITE_TIMEOUT);
+#else
+		_set_timer(&pwdinfo->restore_p2p_state_timer, P2P_INVITE_TIMEOUT);
+#endif /* CONFIG_CONCURRENT_MODE		 */
+
+
+	} else
+		RTW_INFO("[%s] NOT Found in the Scanning Queue!\n", __FUNCTION__);
+exit:
+
+	return ret;
+
+}
+
+static int rtw_p2p_set_persistent(struct net_device *dev,
+				  struct iw_request_info *info,
+				  union iwreq_data *wrqu, char *extra)
+{
+
+	int ret = 0;
+	_adapter					*padapter = (_adapter *)rtw_netdev_priv(dev);
+	struct wifidirect_info		*pwdinfo = &(padapter->wdinfo);
+
+	/*	Commented by Albert 20120328 */
+	/*	The input data is 0 or 1 */
+	/*	0: disable persistent group functionality */
+	/*	1: enable persistent group founctionality */
+
+	RTW_INFO("[%s] data = %s\n", __FUNCTION__, extra);
+
+	if (rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE)) {
+		RTW_INFO("[%s] WiFi Direct is disable!\n", __FUNCTION__);
+		return ret;
+	} else {
+		if (extra[0] == '0')	/*	Disable the persistent group function. */
+			pwdinfo->persistent_supported = _FALSE;
+		else if (extra[0] == '1')	/*	Enable the persistent group function. */
+			pwdinfo->persistent_supported = _TRUE;
+		else
+			pwdinfo->persistent_supported = _FALSE;
+	}
+	printk("[%s] persistent_supported = %d\n", __FUNCTION__, pwdinfo->persistent_supported);
+
+exit:
+
+	return ret;
+
+}
+
+static int uuid_str2bin(const char *str, u8 *bin)
+{
+	const char *pos;
+	u8 *opos;
+
+	pos = str;
+	opos = bin;
+
+	if (hexstr2bin(pos, opos, 4))
+		return -1;
+	pos += 8;
+	opos += 4;
+
+	if (*pos++ != '-' || hexstr2bin(pos, opos, 2))
+		return -1;
+	pos += 4;
+	opos += 2;
+
+	if (*pos++ != '-' || hexstr2bin(pos, opos, 2))
+		return -1;
+	pos += 4;
+	opos += 2;
+
+	if (*pos++ != '-' || hexstr2bin(pos, opos, 2))
+		return -1;
+	pos += 4;
+	opos += 2;
+
+	if (*pos++ != '-' || hexstr2bin(pos, opos, 6))
+		return -1;
+
+	return 0;
+}
+
+static int rtw_p2p_set_wps_uuid(struct net_device *dev,
+				struct iw_request_info *info,
+				union iwreq_data *wrqu, char *extra)
+{
+
+	int ret = 0;
+	_adapter				*padapter = (_adapter *)rtw_netdev_priv(dev);
+	struct wifidirect_info			*pwdinfo = &(padapter->wdinfo);
+
+	RTW_INFO("[%s] data = %s\n", __FUNCTION__, extra);
+
+	if ((36 == strlen(extra)) && (uuid_str2bin(extra, pwdinfo->uuid) == 0))
+		pwdinfo->external_uuid = 1;
+	else {
+		pwdinfo->external_uuid = 0;
+		ret = -EINVAL;
+	}
+
+	return ret;
+
+}
+#ifdef CONFIG_WFD
+static int rtw_p2p_set_pc(struct net_device *dev,
+			  struct iw_request_info *info,
+			  union iwreq_data *wrqu, char *extra)
+{
+
+	int ret = 0;
+	_adapter				*padapter = (_adapter *)rtw_netdev_priv(dev);
+	struct wifidirect_info	*pwdinfo = &(padapter->wdinfo);
+	u8					peerMAC[ETH_ALEN] = { 0x00 };
+	int					jj, kk;
+	struct mlme_priv		*pmlmepriv = &padapter->mlmepriv;
+	_list					*plist, *phead;
+	_queue				*queue	= &(pmlmepriv->scanned_queue);
+	struct	wlan_network	*pnetwork = NULL;
+	u8					attr_content[50] = { 0x00 };
+	u8 *p2pie;
+	uint					p2pielen = 0, attr_contentlen = 0;
+	_irqL				irqL;
+	uint					uintPeerChannel = 0;
+
+	struct wifi_display_info	*pwfd_info = pwdinfo->wfd_info;
+
+	/*	Commented by Albert 20120512 */
+	/*	1. Input information is the MAC address which wants to know the Preferred Connection bit (PC bit) */
+	/*	Format: 00:E0:4C:00:00:05 */
+
+	RTW_INFO("[%s] data = %s\n", __FUNCTION__, extra);
+
+	if (rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE)) {
+		RTW_INFO("[%s] WiFi Direct is disable!\n", __FUNCTION__);
+		return ret;
+	}
+
+	for (jj = 0, kk = 0; jj < ETH_ALEN; jj++, kk += 3)
+		peerMAC[jj] = key_2char2num(extra[kk], extra[kk + 1]);
+
+	_enter_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);
+
+	phead = get_list_head(queue);
+	plist = get_next(phead);
+
+	while (1) {
+		if (rtw_end_of_queue_search(phead, plist) == _TRUE)
+			break;
+
+		pnetwork = LIST_CONTAINOR(plist, struct wlan_network, list);
+
+		/*	Commented by Albert 2011/05/18 */
+		/*	Match the device address located in the P2P IE */
+		/*	This is for the case that the P2P device address is not the same as the P2P interface address. */
+
+		p2pie = rtw_bss_ex_get_p2p_ie(&pnetwork->network, NULL, &p2pielen);
+		if (p2pie) {
+			/*	The P2P Device ID attribute is included in the Beacon frame. */
+			/*	The P2P Device Info attribute is included in the probe response frame. */
+			printk("[%s] Got P2P IE\n", __FUNCTION__);
+			if (rtw_get_p2p_attr_content(p2pie, p2pielen, P2P_ATTR_DEVICE_ID, attr_content, &attr_contentlen)) {
+				/*	Handle the P2P Device ID attribute of Beacon first */
+				printk("[%s] P2P_ATTR_DEVICE_ID\n", __FUNCTION__);
+				if (_rtw_memcmp(attr_content, peerMAC, ETH_ALEN)) {
+					uintPeerChannel = pnetwork->network.Configuration.DSConfig;
+					break;
+				}
+			} else if (rtw_get_p2p_attr_content(p2pie, p2pielen, P2P_ATTR_DEVICE_INFO, attr_content, &attr_contentlen)) {
+				/*	Handle the P2P Device Info attribute of probe response */
+				printk("[%s] P2P_ATTR_DEVICE_INFO\n", __FUNCTION__);
+				if (_rtw_memcmp(attr_content, peerMAC, ETH_ALEN)) {
+					uintPeerChannel = pnetwork->network.Configuration.DSConfig;
+					break;
+				}
+			}
+
+		}
+
+		plist = get_next(plist);
+
+	}
+
+	_exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);
+	printk("[%s] channel = %d\n", __FUNCTION__, uintPeerChannel);
+
+	if (uintPeerChannel) {
+		u8 *wfd_ie;
+		uint wfd_ielen = 0;
+
+		wfd_ie = rtw_bss_ex_get_wfd_ie(&pnetwork->network, NULL, &wfd_ielen);
+		if (wfd_ie) {
+			u8 *wfd_devinfo;
+			uint wfd_devlen;
+
+			RTW_INFO("[%s] Found WFD IE!\n", __FUNCTION__);
+			wfd_devinfo = rtw_get_wfd_attr_content(wfd_ie, wfd_ielen, WFD_ATTR_DEVICE_INFO, NULL, &wfd_devlen);
+			if (wfd_devinfo) {
+				u16	wfd_devinfo_field = 0;
+
+				/*	Commented by Albert 20120319 */
+				/*	The first two bytes are the WFD device information field of WFD device information subelement. */
+				/*	In big endian format. */
+				wfd_devinfo_field = RTW_GET_BE16(wfd_devinfo);
+				if (wfd_devinfo_field & WFD_DEVINFO_PC_TDLS)
+					pwfd_info->wfd_pc = _TRUE;
+				else
+					pwfd_info->wfd_pc = _FALSE;
+			}
+		}
+	} else
+		RTW_INFO("[%s] NOT Found in the Scanning Queue!\n", __FUNCTION__);
+
+exit:
+
+	return ret;
+
+}
+
+static int rtw_p2p_set_wfd_device_type(struct net_device *dev,
+				       struct iw_request_info *info,
+				       union iwreq_data *wrqu, char *extra)
+{
+
+	int ret = 0;
+	_adapter					*padapter = (_adapter *)rtw_netdev_priv(dev);
+	struct wifidirect_info		*pwdinfo = &(padapter->wdinfo);
+	struct wifi_display_info		*pwfd_info = pwdinfo->wfd_info;
+
+	/*	Commented by Albert 20120328 */
+	/*	The input data is 0 or 1 */
+	/*	0: specify to Miracast source device */
+	/*	1 or others: specify to Miracast sink device (display device) */
+
+	RTW_INFO("[%s] data = %s\n", __FUNCTION__, extra);
+
+	if (extra[0] == '0')	/*	Set to Miracast source device. */
+		pwfd_info->wfd_device_type = WFD_DEVINFO_SOURCE;
+	else					/*	Set to Miracast sink device. */
+		pwfd_info->wfd_device_type = WFD_DEVINFO_PSINK;
+
+exit:
+
+	return ret;
+
+}
+
+static int rtw_p2p_set_wfd_enable(struct net_device *dev,
+				  struct iw_request_info *info,
+				  union iwreq_data *wrqu, char *extra)
+{
+	/*	Commented by Kurt 20121206
+	 *	This function is used to set wfd enabled */
+
+	int ret = 0;
+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
+	struct wifidirect_info *pwdinfo = &(padapter->wdinfo);
+
+	if (*extra == '0')
+		rtw_wfd_enable(padapter, 0);
+	else if (*extra == '1')
+		rtw_wfd_enable(padapter, 1);
+
+	RTW_INFO("[%s] wfd_enable = %d\n", __FUNCTION__, pwdinfo->wfd_info->wfd_enable);
+
+	return ret;
+
+}
+
+static int rtw_p2p_set_driver_iface(struct net_device *dev,
+				    struct iw_request_info *info,
+				    union iwreq_data *wrqu, char *extra)
+{
+	/*	Commented by Kurt 20121206
+	 *	This function is used to set driver iface is WEXT or CFG80211 */
+	int ret = 0;
+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
+	struct wifidirect_info *pwdinfo = &(padapter->wdinfo);
+
+	if (*extra == '1') {
+		pwdinfo->driver_interface = DRIVER_WEXT;
+		RTW_INFO("[%s] driver_interface = WEXT\n", __FUNCTION__);
+	} else if (*extra == '2') {
+		pwdinfo->driver_interface = DRIVER_CFG80211;
+		RTW_INFO("[%s] driver_interface = CFG80211\n", __FUNCTION__);
+	}
+
+	return ret;
+
+}
+
+/*	To set the WFD session available to enable or disable */
+static int rtw_p2p_set_sa(struct net_device *dev,
+			  struct iw_request_info *info,
+			  union iwreq_data *wrqu, char *extra)
+{
+
+	int ret = 0;
+	_adapter					*padapter = (_adapter *)rtw_netdev_priv(dev);
+	struct wifidirect_info		*pwdinfo = &(padapter->wdinfo);
+
+	RTW_INFO("[%s] data = %s\n", __FUNCTION__, extra);
+
+	if (0) {
+		RTW_INFO("[%s] WiFi Direct is disable!\n", __FUNCTION__);
+		return ret;
+	} else {
+		if (extra[0] == '0')	/*	Disable the session available. */
+			pwdinfo->session_available = _FALSE;
+		else if (extra[0] == '1')	/*	Enable the session available. */
+			pwdinfo->session_available = _TRUE;
+		else
+			pwdinfo->session_available = _FALSE;
+	}
+	printk("[%s] session available = %d\n", __FUNCTION__, pwdinfo->session_available);
+
+exit:
+
+	return ret;
+
+}
+#endif /* CONFIG_WFD */
+
+static int rtw_p2p_prov_disc(struct net_device *dev,
+			     struct iw_request_info *info,
+			     union iwreq_data *wrqu, char *extra)
+{
+	int ret = 0;
+	_adapter				*padapter = (_adapter *)rtw_netdev_priv(dev);
+	struct wifidirect_info	*pwdinfo = &(padapter->wdinfo);
+	u8					peerMAC[ETH_ALEN] = { 0x00 };
+	int					jj, kk;
+	struct mlme_priv		*pmlmepriv = &padapter->mlmepriv;
+	_list					*plist, *phead;
+	_queue				*queue	= &(pmlmepriv->scanned_queue);
+	struct	wlan_network	*pnetwork = NULL;
+	uint					uintPeerChannel = 0;
+	u8					attr_content[100] = { 0x00 };
+	u8 *p2pie;
+	uint					p2pielen = 0, attr_contentlen = 0;
+	_irqL				irqL;
+
+	/*	Commented by Albert 20110301 */
+	/*	The input data contains two informations. */
+	/*	1. First information is the MAC address which wants to issue the provisioning discovery request frame. */
+	/*	2. Second information is the WPS configuration method which wants to discovery */
+	/*	Format: 00:E0:4C:00:00:05_display */
+	/*	Format: 00:E0:4C:00:00:05_keypad */
+	/*	Format: 00:E0:4C:00:00:05_pbc */
+	/*	Format: 00:E0:4C:00:00:05_label */
+
+	RTW_INFO("[%s] data = %s\n", __FUNCTION__, extra);
+
+	if (pwdinfo->p2p_state == P2P_STATE_NONE) {
+		RTW_INFO("[%s] WiFi Direct is disable!\n", __FUNCTION__);
+		return ret;
+	} else {
+#ifdef CONFIG_INTEL_WIDI
+		if (check_fwstate(pmlmepriv, _FW_UNDER_SURVEY) == _TRUE) {
+			RTW_INFO("[%s] WiFi is under survey!\n", __FUNCTION__);
+			return ret;
+		}
+#endif /* CONFIG_INTEL_WIDI */
+
+		/*	Reset the content of struct tx_provdisc_req_info excluded the wps_config_method_request. */
+		_rtw_memset(pwdinfo->tx_prov_disc_info.peerDevAddr, 0x00, ETH_ALEN);
+		_rtw_memset(pwdinfo->tx_prov_disc_info.peerIFAddr, 0x00, ETH_ALEN);
+		_rtw_memset(&pwdinfo->tx_prov_disc_info.ssid, 0x00, sizeof(NDIS_802_11_SSID));
+		pwdinfo->tx_prov_disc_info.peer_channel_num[0] = 0;
+		pwdinfo->tx_prov_disc_info.peer_channel_num[1] = 0;
+		pwdinfo->tx_prov_disc_info.benable = _FALSE;
+	}
+
+	for (jj = 0, kk = 0; jj < ETH_ALEN; jj++, kk += 3)
+		peerMAC[jj] = key_2char2num(extra[kk], extra[kk + 1]);
+
+	if (_rtw_memcmp(&extra[18], "display", 7))
+		pwdinfo->tx_prov_disc_info.wps_config_method_request = WPS_CM_DISPLYA;
+	else if (_rtw_memcmp(&extra[18], "keypad", 7))
+		pwdinfo->tx_prov_disc_info.wps_config_method_request = WPS_CM_KEYPAD;
+	else if (_rtw_memcmp(&extra[18], "pbc", 3))
+		pwdinfo->tx_prov_disc_info.wps_config_method_request = WPS_CM_PUSH_BUTTON;
+	else if (_rtw_memcmp(&extra[18], "label", 5))
+		pwdinfo->tx_prov_disc_info.wps_config_method_request = WPS_CM_LABEL;
+	else {
+		RTW_INFO("[%s] Unknown WPS config methodn", __FUNCTION__);
+		return ret ;
+	}
+
+	_enter_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);
+
+	phead = get_list_head(queue);
+	plist = get_next(phead);
+
+	while (1) {
+		if (rtw_end_of_queue_search(phead, plist) == _TRUE)
+			break;
+
+		if (uintPeerChannel != 0)
+			break;
+
+		pnetwork = LIST_CONTAINOR(plist, struct wlan_network, list);
+
+		/*	Commented by Albert 2011/05/18 */
+		/*	Match the device address located in the P2P IE */
+		/*	This is for the case that the P2P device address is not the same as the P2P interface address. */
+
+		p2pie = rtw_bss_ex_get_p2p_ie(&pnetwork->network, NULL, &p2pielen);
+		if (p2pie) {
+			while (p2pie) {
+				/*	The P2P Device ID attribute is included in the Beacon frame. */
+				/*	The P2P Device Info attribute is included in the probe response frame. */
+
+				if (rtw_get_p2p_attr_content(p2pie, p2pielen, P2P_ATTR_DEVICE_ID, attr_content, &attr_contentlen)) {
+					/*	Handle the P2P Device ID attribute of Beacon first */
+					if (_rtw_memcmp(attr_content, peerMAC, ETH_ALEN)) {
+						uintPeerChannel = pnetwork->network.Configuration.DSConfig;
+						break;
+					}
+				} else if (rtw_get_p2p_attr_content(p2pie, p2pielen, P2P_ATTR_DEVICE_INFO, attr_content, &attr_contentlen)) {
+					/*	Handle the P2P Device Info attribute of probe response */
+					if (_rtw_memcmp(attr_content, peerMAC, ETH_ALEN)) {
+						uintPeerChannel = pnetwork->network.Configuration.DSConfig;
+						break;
+					}
+				}
+
+				/* Get the next P2P IE */
+				p2pie = rtw_get_p2p_ie(p2pie + p2pielen, BSS_EX_TLV_IES_LEN(&pnetwork->network) - (p2pie + p2pielen - BSS_EX_TLV_IES(&pnetwork->network)), NULL, &p2pielen);
+			}
+
+		}
+
+#ifdef CONFIG_INTEL_WIDI
+		/* Some Intel WiDi source may not provide P2P IE, */
+		/* so we could only compare mac addr by 802.11 Source Address */
+		if (pmlmepriv->widi_state == INTEL_WIDI_STATE_WFD_CONNECTION
+		    && uintPeerChannel == 0) {
+			if (_rtw_memcmp(pnetwork->network.MacAddress, peerMAC, ETH_ALEN)) {
+				uintPeerChannel = pnetwork->network.Configuration.DSConfig;
+				break;
+			}
+		}
+#endif /* CONFIG_INTEL_WIDI */
+
+		plist = get_next(plist);
+
+	}
+
+	_exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);
+
+	if (uintPeerChannel) {
+#ifdef CONFIG_WFD
+		if (hal_chk_wl_func(padapter, WL_FUNC_MIRACAST)) {
+			struct wifi_display_info *pwfd_info = pwdinfo->wfd_info;
+			u8 *wfd_ie;
+			uint wfd_ielen = 0;
+
+			wfd_ie = rtw_bss_ex_get_wfd_ie(&pnetwork->network, NULL, &wfd_ielen);
+			if (wfd_ie) {
+				u8 *wfd_devinfo;
+				uint wfd_devlen;
+
+				RTW_INFO("[%s] Found WFD IE!\n", __FUNCTION__);
+				wfd_devinfo = rtw_get_wfd_attr_content(wfd_ie, wfd_ielen, WFD_ATTR_DEVICE_INFO, NULL, &wfd_devlen);
+				if (wfd_devinfo) {
+					u16	wfd_devinfo_field = 0;
+
+					/*	Commented by Albert 20120319 */
+					/*	The first two bytes are the WFD device information field of WFD device information subelement. */
+					/*	In big endian format. */
+					wfd_devinfo_field = RTW_GET_BE16(wfd_devinfo);
+					if (wfd_devinfo_field & WFD_DEVINFO_SESSION_AVAIL)
+						pwfd_info->peer_session_avail = _TRUE;
+					else
+						pwfd_info->peer_session_avail = _FALSE;
+				}
+			}
+
+			if (_FALSE == pwfd_info->peer_session_avail) {
+				RTW_INFO("[%s] WFD Session not avaiable!\n", __FUNCTION__);
+				goto exit;
+			}
+		}
+#endif /* CONFIG_WFD */
+
+		RTW_INFO("[%s] peer channel: %d!\n", __FUNCTION__, uintPeerChannel);
+#ifdef CONFIG_CONCURRENT_MODE
+		if (rtw_mi_check_status(padapter, MI_LINKED))
+			_cancel_timer_ex(&pwdinfo->ap_p2p_switch_timer);
+#endif /* CONFIG_CONCURRENT_MODE */
+		_rtw_memcpy(pwdinfo->tx_prov_disc_info.peerIFAddr, pnetwork->network.MacAddress, ETH_ALEN);
+		_rtw_memcpy(pwdinfo->tx_prov_disc_info.peerDevAddr, peerMAC, ETH_ALEN);
+		pwdinfo->tx_prov_disc_info.peer_channel_num[0] = (u16) uintPeerChannel;
+		pwdinfo->tx_prov_disc_info.benable = _TRUE;
+		rtw_p2p_set_pre_state(pwdinfo, rtw_p2p_state(pwdinfo));
+		rtw_p2p_set_state(pwdinfo, P2P_STATE_TX_PROVISION_DIS_REQ);
+
+		if (rtw_p2p_chk_role(pwdinfo, P2P_ROLE_CLIENT))
+			_rtw_memcpy(&pwdinfo->tx_prov_disc_info.ssid, &pnetwork->network.Ssid, sizeof(NDIS_802_11_SSID));
+		else if (rtw_p2p_chk_role(pwdinfo, P2P_ROLE_DEVICE) || rtw_p2p_chk_role(pwdinfo, P2P_ROLE_GO)) {
+			_rtw_memcpy(pwdinfo->tx_prov_disc_info.ssid.Ssid, pwdinfo->p2p_wildcard_ssid, P2P_WILDCARD_SSID_LEN);
+			pwdinfo->tx_prov_disc_info.ssid.SsidLength = P2P_WILDCARD_SSID_LEN;
+		}
+
+#ifdef CONFIG_CONCURRENT_MODE
+		if (rtw_mi_check_status(padapter, MI_LINKED)) {
+			u8 union_ch = rtw_mi_get_union_chan(padapter);
+			u8 union_bw = rtw_mi_get_union_bw(padapter);
+			u8 union_offset = rtw_mi_get_union_offset(padapter);
+
+			set_channel_bwmode(padapter, union_ch, union_offset, union_bw);
+			rtw_leave_opch(padapter);
+
+		} else
+			set_channel_bwmode(padapter, uintPeerChannel, HAL_PRIME_CHNL_OFFSET_DONT_CARE, CHANNEL_WIDTH_20);
+#else
+		set_channel_bwmode(padapter, uintPeerChannel, HAL_PRIME_CHNL_OFFSET_DONT_CARE, CHANNEL_WIDTH_20);
+#endif
+
+		_set_timer(&pwdinfo->pre_tx_scan_timer, P2P_TX_PRESCAN_TIMEOUT);
+
+#ifdef CONFIG_CONCURRENT_MODE
+		if (rtw_mi_check_status(padapter, MI_LINKED))
+			_set_timer(&pwdinfo->restore_p2p_state_timer, P2P_CONCURRENT_PROVISION_TIMEOUT);
+		else
+			_set_timer(&pwdinfo->restore_p2p_state_timer, P2P_PROVISION_TIMEOUT);
+#else
+		_set_timer(&pwdinfo->restore_p2p_state_timer, P2P_PROVISION_TIMEOUT);
+#endif /* CONFIG_CONCURRENT_MODE		 */
+
+	} else {
+		RTW_INFO("[%s] NOT Found in the Scanning Queue!\n", __FUNCTION__);
+#ifdef CONFIG_INTEL_WIDI
+		_cancel_timer_ex(&pwdinfo->restore_p2p_state_timer);
+		rtw_p2p_set_state(pwdinfo, P2P_STATE_FIND_PHASE_SEARCH);
+		rtw_p2p_findphase_ex_set(pwdinfo, P2P_FINDPHASE_EX_NONE);
+		rtw_free_network_queue(padapter, _TRUE);
+		_enter_critical_bh(&pmlmepriv->lock, &irqL);
+		rtw_sitesurvey_cmd(padapter, NULL);
+		_exit_critical_bh(&pmlmepriv->lock, &irqL);
+#endif /* CONFIG_INTEL_WIDI */
+	}
+exit:
+
+	return ret;
+
+}
+
+/*	Added by Albert 20110328
+ *	This function is used to inform the driver the user had specified the pin code value or pbc
+ *	to application. */
+
+static int rtw_p2p_got_wpsinfo(struct net_device *dev,
+			       struct iw_request_info *info,
+			       union iwreq_data *wrqu, char *extra)
+{
+
+	int ret = 0;
+	_adapter				*padapter = (_adapter *)rtw_netdev_priv(dev);
+	struct wifidirect_info	*pwdinfo = &(padapter->wdinfo);
+
+
+	RTW_INFO("[%s] data = %s\n", __FUNCTION__, extra);
+	/*	Added by Albert 20110328 */
+	/*	if the input data is P2P_NO_WPSINFO -> reset the wpsinfo */
+	/*	if the input data is P2P_GOT_WPSINFO_PEER_DISPLAY_PIN -> the utility just input the PIN code got from the peer P2P device. */
+	/*	if the input data is P2P_GOT_WPSINFO_SELF_DISPLAY_PIN -> the utility just got the PIN code from itself. */
+	/*	if the input data is P2P_GOT_WPSINFO_PBC -> the utility just determine to use the PBC */
+
+	if (*extra == '0')
+		pwdinfo->ui_got_wps_info = P2P_NO_WPSINFO;
+	else if (*extra == '1')
+		pwdinfo->ui_got_wps_info = P2P_GOT_WPSINFO_PEER_DISPLAY_PIN;
+	else if (*extra == '2')
+		pwdinfo->ui_got_wps_info = P2P_GOT_WPSINFO_SELF_DISPLAY_PIN;
+	else if (*extra == '3')
+		pwdinfo->ui_got_wps_info = P2P_GOT_WPSINFO_PBC;
+	else
+		pwdinfo->ui_got_wps_info = P2P_NO_WPSINFO;
+
+	return ret;
+
+}
+
+#endif /* CONFIG_P2P */
+
+static int rtw_p2p_set(struct net_device *dev,
+		       struct iw_request_info *info,
+		       union iwreq_data *wrqu, char *extra)
+{
+	int ret = 0;
+#ifdef CONFIG_P2P
+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
+
+	RTW_INFO("[%s] extra = %s\n", __FUNCTION__, extra);
+
+	if (_rtw_memcmp(extra, "enable=", 7))
+		rtw_wext_p2p_enable(dev, info, wrqu, &extra[7]);
+	else if (_rtw_memcmp(extra, "setDN=", 6)) {
+		wrqu->data.length -= 6;
+		rtw_p2p_setDN(dev, info, wrqu, &extra[6]);
+	} else if (_rtw_memcmp(extra, "profilefound=", 13)) {
+		wrqu->data.length -= 13;
+		rtw_p2p_profilefound(dev, info, wrqu, &extra[13]);
+	} else if (_rtw_memcmp(extra, "prov_disc=", 10)) {
+		wrqu->data.length -= 10;
+		rtw_p2p_prov_disc(dev, info, wrqu, &extra[10]);
+	} else if (_rtw_memcmp(extra, "nego=", 5)) {
+		wrqu->data.length -= 5;
+		rtw_p2p_connect(dev, info, wrqu, &extra[5]);
+	} else if (_rtw_memcmp(extra, "intent=", 7)) {
+		/*	Commented by Albert 2011/03/23 */
+		/*	The wrqu->data.length will include the null character */
+		/*	So, we will decrease 7 + 1 */
+		wrqu->data.length -= 8;
+		rtw_p2p_set_intent(dev, info, wrqu, &extra[7]);
+	} else if (_rtw_memcmp(extra, "ssid=", 5)) {
+		wrqu->data.length -= 5;
+		rtw_p2p_set_go_nego_ssid(dev, info, wrqu, &extra[5]);
+	} else if (_rtw_memcmp(extra, "got_wpsinfo=", 12)) {
+		wrqu->data.length -= 12;
+		rtw_p2p_got_wpsinfo(dev, info, wrqu, &extra[12]);
+	} else if (_rtw_memcmp(extra, "listen_ch=", 10)) {
+		/*	Commented by Albert 2011/05/24 */
+		/*	The wrqu->data.length will include the null character */
+		/*	So, we will decrease (10 + 1)	 */
+		wrqu->data.length -= 11;
+		rtw_p2p_set_listen_ch(dev, info, wrqu, &extra[10]);
+	} else if (_rtw_memcmp(extra, "op_ch=", 6)) {
+		/*	Commented by Albert 2011/05/24 */
+		/*	The wrqu->data.length will include the null character */
+		/*	So, we will decrease (6 + 1)	 */
+		wrqu->data.length -= 7;
+		rtw_p2p_set_op_ch(dev, info, wrqu, &extra[6]);
+	} else if (_rtw_memcmp(extra, "invite=", 7)) {
+		wrqu->data.length -= 8;
+		rtw_p2p_invite_req(dev, info, wrqu, &extra[7]);
+	} else if (_rtw_memcmp(extra, "persistent=", 11)) {
+		wrqu->data.length -= 11;
+		rtw_p2p_set_persistent(dev, info, wrqu, &extra[11]);
+	} else if (_rtw_memcmp(extra, "uuid=", 5)) {
+		wrqu->data.length -= 5;
+		ret = rtw_p2p_set_wps_uuid(dev, info, wrqu, &extra[5]);
+	}
+
+#ifdef CONFIG_WFD
+	if (hal_chk_wl_func(padapter, WL_FUNC_MIRACAST)) {
+		if (_rtw_memcmp(extra, "sa=", 3)) {
+			/* sa: WFD Session Available information */
+			wrqu->data.length -= 3;
+			rtw_p2p_set_sa(dev, info, wrqu, &extra[3]);
+		} else if (_rtw_memcmp(extra, "pc=", 3)) {
+			/* pc: WFD Preferred Connection */
+			wrqu->data.length -= 3;
+			rtw_p2p_set_pc(dev, info, wrqu, &extra[3]);
+		} else if (_rtw_memcmp(extra, "wfd_type=", 9)) {
+			wrqu->data.length -= 9;
+			rtw_p2p_set_wfd_device_type(dev, info, wrqu, &extra[9]);
+		} else if (_rtw_memcmp(extra, "wfd_enable=", 11)) {
+			wrqu->data.length -= 11;
+			rtw_p2p_set_wfd_enable(dev, info, wrqu, &extra[11]);
+		} else if (_rtw_memcmp(extra, "driver_iface=", 13)) {
+			wrqu->data.length -= 13;
+			rtw_p2p_set_driver_iface(dev, info, wrqu, &extra[13]);
+		}
+	}
+#endif /* CONFIG_WFD */
+
+#endif /* CONFIG_P2P */
+
+	return ret;
+
+}
+
+static int rtw_p2p_get(struct net_device *dev,
+		       struct iw_request_info *info,
+		       union iwreq_data *wrqu, char *extra)
+{
+	int ret = 0;
+#ifdef CONFIG_P2P
+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
+
+	if (padapter->bShowGetP2PState)
+		RTW_INFO("[%s] extra = %s\n", __FUNCTION__, (char *) wrqu->data.pointer);
+
+	if (_rtw_memcmp(wrqu->data.pointer, "status", 6))
+		rtw_p2p_get_status(dev, info, wrqu, extra);
+	else if (_rtw_memcmp(wrqu->data.pointer, "role", 4))
+		rtw_p2p_get_role(dev, info, wrqu, extra);
+	else if (_rtw_memcmp(wrqu->data.pointer, "peer_ifa", 8))
+		rtw_p2p_get_peer_ifaddr(dev, info, wrqu, extra);
+	else if (_rtw_memcmp(wrqu->data.pointer, "req_cm", 6))
+		rtw_p2p_get_req_cm(dev, info, wrqu, extra);
+	else if (_rtw_memcmp(wrqu->data.pointer, "peer_deva", 9)) {
+		/*	Get the P2P device address when receiving the provision discovery request frame. */
+		rtw_p2p_get_peer_devaddr(dev, info, wrqu, extra);
+	} else if (_rtw_memcmp(wrqu->data.pointer, "group_id", 8))
+		rtw_p2p_get_groupid(dev, info, wrqu, extra);
+	else if (_rtw_memcmp(wrqu->data.pointer, "inv_peer_deva", 13)) {
+		/*	Get the P2P device address when receiving the P2P Invitation request frame. */
+		rtw_p2p_get_peer_devaddr_by_invitation(dev, info, wrqu, extra);
+	} else if (_rtw_memcmp(wrqu->data.pointer, "op_ch", 5))
+		rtw_p2p_get_op_ch(dev, info, wrqu, extra);
+
+#ifdef CONFIG_WFD
+	if (hal_chk_wl_func(padapter, WL_FUNC_MIRACAST)) {
+		if (_rtw_memcmp(wrqu->data.pointer, "peer_port", 9))
+			rtw_p2p_get_peer_wfd_port(dev, info, wrqu, extra);
+		else if (_rtw_memcmp(wrqu->data.pointer, "wfd_sa", 6))
+			rtw_p2p_get_peer_wfd_session_available(dev, info, wrqu, extra);
+		else if (_rtw_memcmp(wrqu->data.pointer, "wfd_pc", 6))
+			rtw_p2p_get_peer_wfd_preferred_connection(dev, info, wrqu, extra);
+	}
+#endif /* CONFIG_WFD */
+
+#endif /* CONFIG_P2P */
+
+	return ret;
+
+}
+
+static int rtw_p2p_get2(struct net_device *dev,
+			struct iw_request_info *info,
+			union iwreq_data *wrqu, char *extra)
+{
+
+	int ret = 0;
+
+#ifdef CONFIG_P2P
+
+	int length = wrqu->data.length;
+	char *buffer = (u8 *)rtw_malloc(length);
+
+	if (buffer == NULL) {
+		ret = -ENOMEM;
+		goto bad;
+	}
+
+	if (copy_from_user(buffer, wrqu->data.pointer, wrqu->data.length)) {
+		ret = -EFAULT;
+		goto bad;
+	}
+
+	RTW_INFO("[%s] buffer = %s\n", __FUNCTION__, buffer);
+
+	if (_rtw_memcmp(buffer, "wpsCM=", 6))
+		ret = rtw_p2p_get_wps_configmethod(dev, info, wrqu, extra, &buffer[6]);
+	else if (_rtw_memcmp(buffer, "devN=", 5))
+		ret = rtw_p2p_get_device_name(dev, info, wrqu, extra, &buffer[5]);
+	else if (_rtw_memcmp(buffer, "dev_type=", 9))
+		ret = rtw_p2p_get_device_type(dev, info, wrqu, extra, &buffer[9]);
+	else if (_rtw_memcmp(buffer, "go_devadd=", 10))
+		ret = rtw_p2p_get_go_device_address(dev, info, wrqu, extra, &buffer[10]);
+	else if (_rtw_memcmp(buffer, "InvProc=", 8))
+		ret = rtw_p2p_get_invitation_procedure(dev, info, wrqu, extra, &buffer[8]);
+	else {
+		snprintf(extra, sizeof("Command not found."), "Command not found.");
+		wrqu->data.length = strlen(extra);
+	}
+
+bad:
+	if (buffer)
+		rtw_mfree(buffer, length);
+
+#endif /* CONFIG_P2P */
+
+	return ret;
+
+}
+
+static int rtw_cta_test_start(struct net_device *dev,
+			      struct iw_request_info *info,
+			      union iwreq_data *wrqu, char *extra)
+{
+	int ret = 0;
+	_adapter	*padapter = (_adapter *)rtw_netdev_priv(dev);
+	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(padapter);
+
+	RTW_INFO("%s %s\n", __func__, extra);
+	if (!strcmp(extra, "1"))
+		hal_data->in_cta_test = 1;
+	else
+		hal_data->in_cta_test = 0;
+
+	rtw_hal_rcr_set_chk_bssid(padapter, MLME_ACTION_NONE);
+
+	return ret;
+}
+
+extern int rtw_change_ifname(_adapter *padapter, const char *ifname);
+static int rtw_rereg_nd_name(struct net_device *dev,
+			     struct iw_request_info *info,
+			     union iwreq_data *wrqu, char *extra)
+{
+	int ret = 0;
+	_adapter *padapter = rtw_netdev_priv(dev);
+	struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
+	struct rereg_nd_name_data *rereg_priv = &padapter->rereg_nd_name_priv;
+	char new_ifname[IFNAMSIZ];
+
+	if (rereg_priv->old_ifname[0] == 0) {
+		char *reg_ifname;
+#ifdef CONFIG_CONCURRENT_MODE
+		if (padapter->isprimary)
+			reg_ifname = padapter->registrypriv.ifname;
+		else
+#endif
+			reg_ifname = padapter->registrypriv.if2name;
+
+		strncpy(rereg_priv->old_ifname, reg_ifname, IFNAMSIZ);
+		rereg_priv->old_ifname[IFNAMSIZ - 1] = 0;
+	}
+
+	/* RTW_INFO("%s wrqu->data.length:%d\n", __FUNCTION__, wrqu->data.length); */
+	if (wrqu->data.length > IFNAMSIZ)
+		return -EFAULT;
+
+	if (copy_from_user(new_ifname, wrqu->data.pointer, IFNAMSIZ))
+		return -EFAULT;
+
+	if (0 == strcmp(rereg_priv->old_ifname, new_ifname))
+		return ret;
+
+	RTW_INFO("%s new_ifname:%s\n", __FUNCTION__, new_ifname);
+	rtw_set_rtnl_lock_holder(dvobj, current);
+	ret = rtw_change_ifname(padapter, new_ifname);
+	rtw_set_rtnl_lock_holder(dvobj, NULL);
+	if (0 != ret)
+		goto exit;
+
+	if (_rtw_memcmp(rereg_priv->old_ifname, "disable%d", 9) == _TRUE) {
+		/* rtw_ips_mode_req(&padapter->pwrctrlpriv, rereg_priv->old_ips_mode); */
+	}
+
+	strncpy(rereg_priv->old_ifname, new_ifname, IFNAMSIZ);
+	rereg_priv->old_ifname[IFNAMSIZ - 1] = 0;
+
+	if (_rtw_memcmp(new_ifname, "disable%d", 9) == _TRUE) {
+
+		RTW_INFO("%s disable\n", __FUNCTION__);
+		/* free network queue for Android's timming issue */
+		rtw_free_network_queue(padapter, _TRUE);
+
+		/* the interface is being "disabled", we can do deeper IPS */
+		/* rereg_priv->old_ips_mode = rtw_get_ips_mode_req(&padapter->pwrctrlpriv); */
+		/* rtw_ips_mode_req(&padapter->pwrctrlpriv, IPS_NORMAL); */
+	}
+exit:
+	return ret;
+
+}
+
+#ifdef CONFIG_IOL
+#include <rtw_iol.h>
+#endif
+#ifdef CONFIG_BACKGROUND_NOISE_MONITOR
+#include "../../hal/hal_dm_acs.h"
+#endif
+#ifdef DBG_CMD_QUEUE
+u8 dump_cmd_id = 0;
+#endif
+
+static int rtw_dbg_port(struct net_device *dev,
+			struct iw_request_info *info,
+			union iwreq_data *wrqu, char *extra)
+{
+	_irqL irqL;
+	int ret = 0;
+	u8 major_cmd, minor_cmd;
+	u16 arg;
+	u32 extra_arg, *pdata, val32;
+	struct sta_info *psta;
+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
+	struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
+	struct mlme_ext_priv	*pmlmeext = &padapter->mlmeextpriv;
+	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
+	struct security_priv *psecuritypriv = &padapter->securitypriv;
+	struct wlan_network *cur_network = &(pmlmepriv->cur_network);
+	struct sta_priv *pstapriv = &padapter->stapriv;
+
+
+	pdata = (u32 *)&wrqu->data;
+
+	val32 = *pdata;
+	arg = (u16)(val32 & 0x0000ffff);
+	major_cmd = (u8)(val32 >> 24);
+	minor_cmd = (u8)((val32 >> 16) & 0x00ff);
+
+	extra_arg = *(pdata + 1);
+
+	switch (major_cmd) {
+	case 0x70: /* read_reg */
+		switch (minor_cmd) {
+		case 1:
+			RTW_INFO("rtw_read8(0x%x)=0x%02x\n", arg, rtw_read8(padapter, arg));
+			break;
+		case 2:
+			RTW_INFO("rtw_read16(0x%x)=0x%04x\n", arg, rtw_read16(padapter, arg));
+			break;
+		case 4:
+			RTW_INFO("rtw_read32(0x%x)=0x%08x\n", arg, rtw_read32(padapter, arg));
+			break;
+		}
+		break;
+	case 0x71: /* write_reg */
+		switch (minor_cmd) {
+		case 1:
+			rtw_write8(padapter, arg, extra_arg);
+			RTW_INFO("rtw_write8(0x%x)=0x%02x\n", arg, rtw_read8(padapter, arg));
+			break;
+		case 2:
+			rtw_write16(padapter, arg, extra_arg);
+			RTW_INFO("rtw_write16(0x%x)=0x%04x\n", arg, rtw_read16(padapter, arg));
+			break;
+		case 4:
+			rtw_write32(padapter, arg, extra_arg);
+			RTW_INFO("rtw_write32(0x%x)=0x%08x\n", arg, rtw_read32(padapter, arg));
+			break;
+		}
+		break;
+	case 0x72: /* read_bb */
+		RTW_INFO("read_bbreg(0x%x)=0x%x\n", arg, rtw_hal_read_bbreg(padapter, arg, 0xffffffff));
+		break;
+	case 0x73: /* write_bb */
+		rtw_hal_write_bbreg(padapter, arg, 0xffffffff, extra_arg);
+		RTW_INFO("write_bbreg(0x%x)=0x%x\n", arg, rtw_hal_read_bbreg(padapter, arg, 0xffffffff));
+		break;
+	case 0x74: /* read_rf */
+		RTW_INFO("read RF_reg path(0x%02x),offset(0x%x),value(0x%08x)\n", minor_cmd, arg, rtw_hal_read_rfreg(padapter, minor_cmd, arg, 0xffffffff));
+		break;
+	case 0x75: /* write_rf */
+		rtw_hal_write_rfreg(padapter, minor_cmd, arg, 0xffffffff, extra_arg);
+		RTW_INFO("write RF_reg path(0x%02x),offset(0x%x),value(0x%08x)\n", minor_cmd, arg, rtw_hal_read_rfreg(padapter, minor_cmd, arg, 0xffffffff));
+		break;
+
+	case 0x76:
+		switch (minor_cmd) {
+		case 0x00: /* normal mode, */
+			padapter->recvpriv.is_signal_dbg = 0;
+			break;
+		case 0x01: /* dbg mode */
+			padapter->recvpriv.is_signal_dbg = 1;
+			extra_arg = extra_arg > 100 ? 100 : extra_arg;
+			padapter->recvpriv.signal_strength_dbg = extra_arg;
+			break;
+		}
+		break;
+	case 0x78: /* IOL test */
+		switch (minor_cmd) {
+		#ifdef CONFIG_IOL
+		case 0x04: { /* LLT table initialization test */
+			u8 page_boundary = 0xf9;
+			{
+				struct xmit_frame	*xmit_frame;
+
+				xmit_frame = rtw_IOL_accquire_xmit_frame(padapter);
+				if (xmit_frame == NULL) {
+					ret = -ENOMEM;
+					break;
+				}
+
+				rtw_IOL_append_LLT_cmd(xmit_frame, page_boundary);
+
+
+				if (_SUCCESS != rtw_IOL_exec_cmds_sync(padapter, xmit_frame, 500, 0))
+					ret = -EPERM;
+			}
+		}
+			break;
+		case 0x05: { /* blink LED test */
+			u16 reg = 0x4c;
+			u32 blink_num = 50;
+			u32 blink_delay_ms = 200;
+			int i;
+
+			{
+				struct xmit_frame	*xmit_frame;
+
+				xmit_frame = rtw_IOL_accquire_xmit_frame(padapter);
+				if (xmit_frame == NULL) {
+					ret = -ENOMEM;
+					break;
+				}
+
+				for (i = 0; i < blink_num; i++) {
+					#ifdef CONFIG_IOL_NEW_GENERATION
+					rtw_IOL_append_WB_cmd(xmit_frame, reg, 0x00, 0xff);
+					rtw_IOL_append_DELAY_MS_cmd(xmit_frame, blink_delay_ms);
+					rtw_IOL_append_WB_cmd(xmit_frame, reg, 0x08, 0xff);
+					rtw_IOL_append_DELAY_MS_cmd(xmit_frame, blink_delay_ms);
+					#else
+					rtw_IOL_append_WB_cmd(xmit_frame, reg, 0x00);
+					rtw_IOL_append_DELAY_MS_cmd(xmit_frame, blink_delay_ms);
+					rtw_IOL_append_WB_cmd(xmit_frame, reg, 0x08);
+					rtw_IOL_append_DELAY_MS_cmd(xmit_frame, blink_delay_ms);
+					#endif
+				}
+				if (_SUCCESS != rtw_IOL_exec_cmds_sync(padapter, xmit_frame, (blink_delay_ms * blink_num * 2) + 200, 0))
+					ret = -EPERM;
+			}
+		}
+			break;
+
+		case 0x06: { /* continuous wirte byte test */
+			u16 reg = arg;
+			u16 start_value = 0;
+			u32 write_num = extra_arg;
+			int i;
+			u8 final;
+
+			{
+				struct xmit_frame	*xmit_frame;
+
+				xmit_frame = rtw_IOL_accquire_xmit_frame(padapter);
+				if (xmit_frame == NULL) {
+					ret = -ENOMEM;
+					break;
+				}
+
+				for (i = 0; i < write_num; i++) {
+					#ifdef CONFIG_IOL_NEW_GENERATION
+					rtw_IOL_append_WB_cmd(xmit_frame, reg, i + start_value, 0xFF);
+					#else
+					rtw_IOL_append_WB_cmd(xmit_frame, reg, i + start_value);
+					#endif
+				}
+				if (_SUCCESS != rtw_IOL_exec_cmds_sync(padapter, xmit_frame, 5000, 0))
+					ret = -EPERM;
+			}
+
+			final = rtw_read8(padapter, reg);
+			if (start_value + write_num - 1 == final)
+				RTW_INFO("continuous IOL_CMD_WB_REG to 0x%x %u times Success, start:%u, final:%u\n", reg, write_num, start_value, final);
+			else
+				RTW_INFO("continuous IOL_CMD_WB_REG to 0x%x %u times Fail, start:%u, final:%u\n", reg, write_num, start_value, final);
+		}
+			break;
+
+		case 0x07: { /* continuous wirte word test */
+			u16 reg = arg;
+			u16 start_value = 200;
+			u32 write_num = extra_arg;
+
+			int i;
+			u16 final;
+
+			{
+				struct xmit_frame	*xmit_frame;
+
+				xmit_frame = rtw_IOL_accquire_xmit_frame(padapter);
+				if (xmit_frame == NULL) {
+					ret = -ENOMEM;
+					break;
+				}
+
+				for (i = 0; i < write_num; i++) {
+					#ifdef CONFIG_IOL_NEW_GENERATION
+					rtw_IOL_append_WW_cmd(xmit_frame, reg, i + start_value, 0xFFFF);
+					#else
+					rtw_IOL_append_WW_cmd(xmit_frame, reg, i + start_value);
+					#endif
+				}
+				if (_SUCCESS != rtw_IOL_exec_cmds_sync(padapter, xmit_frame, 5000, 0))
+					ret = -EPERM;
+			}
+
+			final = rtw_read16(padapter, reg);
+			if (start_value + write_num - 1 == final)
+				RTW_INFO("continuous IOL_CMD_WW_REG to 0x%x %u times Success, start:%u, final:%u\n", reg, write_num, start_value, final);
+			else
+				RTW_INFO("continuous IOL_CMD_WW_REG to 0x%x %u times Fail, start:%u, final:%u\n", reg, write_num, start_value, final);
+		}
+			break;
+
+		case 0x08: { /* continuous wirte dword test */
+			u16 reg = arg;
+			u32 start_value = 0x110000c7;
+			u32 write_num = extra_arg;
+
+			int i;
+			u32 final;
+
+			{
+				struct xmit_frame	*xmit_frame;
+
+				xmit_frame = rtw_IOL_accquire_xmit_frame(padapter);
+				if (xmit_frame == NULL) {
+					ret = -ENOMEM;
+					break;
+				}
+
+				for (i = 0; i < write_num; i++) {
+					#ifdef CONFIG_IOL_NEW_GENERATION
+					rtw_IOL_append_WD_cmd(xmit_frame, reg, i + start_value, 0xFFFFFFFF);
+					#else
+					rtw_IOL_append_WD_cmd(xmit_frame, reg, i + start_value);
+					#endif
+				}
+				if (_SUCCESS != rtw_IOL_exec_cmds_sync(padapter, xmit_frame, 5000, 0))
+					ret = -EPERM;
+
+			}
+
+			final = rtw_read32(padapter, reg);
+			if (start_value + write_num - 1 == final)
+				RTW_INFO("continuous IOL_CMD_WD_REG to 0x%x %u times Success, start:%u, final:%u\n", reg, write_num, start_value, final);
+			else
+				RTW_INFO("continuous IOL_CMD_WD_REG to 0x%x %u times Fail, start:%u, final:%u\n", reg, write_num, start_value, final);
+		}
+			break;
+		#endif /* CONFIG_IOL */
+		}
+		break;
+	case 0x79: {
+		/*
+		* dbg 0x79000000 [value], set RESP_TXAGC to + value, value:0~15
+		* dbg 0x79010000 [value], set RESP_TXAGC to - value, value:0~15
+		*/
+		u8 value =  extra_arg & 0x0f;
+		u8 sign = minor_cmd;
+		u16 write_value = 0;
+
+		RTW_INFO("%s set RESP_TXAGC to %s %u\n", __func__, sign ? "minus" : "plus", value);
+
+		if (sign)
+			value = value | 0x10;
+
+		write_value = value | (value << 5);
+		rtw_write16(padapter, 0x6d9, write_value);
+	}
+		break;
+	case 0x7a:
+		receive_disconnect(padapter, pmlmeinfo->network.MacAddress
+				   , WLAN_REASON_EXPIRATION_CHK, _FALSE);
+		break;
+	case 0x7F:
+		switch (minor_cmd) {
+		case 0x0:
+			RTW_INFO("fwstate=0x%x\n", get_fwstate(pmlmepriv));
+			break;
+		case 0x01:
+			RTW_INFO("auth_alg=0x%x, enc_alg=0x%x, auth_type=0x%x, enc_type=0x%x\n",
+				psecuritypriv->dot11AuthAlgrthm, psecuritypriv->dot11PrivacyAlgrthm,
+				psecuritypriv->ndisauthtype, psecuritypriv->ndisencryptstatus);
+			break;
+		case 0x03:
+			RTW_INFO("qos_option=%d\n", pmlmepriv->qospriv.qos_option);
+#ifdef CONFIG_80211N_HT
+			RTW_INFO("ht_option=%d\n", pmlmepriv->htpriv.ht_option);
+#endif /* CONFIG_80211N_HT */
+			break;
+		case 0x04:
+			RTW_INFO("cur_ch=%d\n", pmlmeext->cur_channel);
+			RTW_INFO("cur_bw=%d\n", pmlmeext->cur_bwmode);
+			RTW_INFO("cur_ch_off=%d\n", pmlmeext->cur_ch_offset);
+
+			RTW_INFO("oper_ch=%d\n", rtw_get_oper_ch(padapter));
+			RTW_INFO("oper_bw=%d\n", rtw_get_oper_bw(padapter));
+			RTW_INFO("oper_ch_offet=%d\n", rtw_get_oper_choffset(padapter));
+
+			break;
+		case 0x05:
+			psta = rtw_get_stainfo(pstapriv, cur_network->network.MacAddress);
+			if (psta) {
+				RTW_INFO("SSID=%s\n", cur_network->network.Ssid.Ssid);
+				RTW_INFO("sta's macaddr:" MAC_FMT "\n", MAC_ARG(psta->cmn.mac_addr));
+				RTW_INFO("cur_channel=%d, cur_bwmode=%d, cur_ch_offset=%d\n", pmlmeext->cur_channel, pmlmeext->cur_bwmode, pmlmeext->cur_ch_offset);
+				RTW_INFO("rtsen=%d, cts2slef=%d\n", psta->rtsen, psta->cts2self);
+				RTW_INFO("state=0x%x, aid=%d, macid=%d, raid=%d\n",
+					psta->state, psta->cmn.aid, psta->cmn.mac_id, psta->cmn.ra_info.rate_id);
+#ifdef CONFIG_80211N_HT
+				RTW_INFO("qos_en=%d, ht_en=%d, init_rate=%d\n", psta->qos_option, psta->htpriv.ht_option, psta->init_rate);
+				RTW_INFO("bwmode=%d, ch_offset=%d, sgi_20m=%d,sgi_40m=%d\n"
+					, psta->cmn.bw_mode, psta->htpriv.ch_offset, psta->htpriv.sgi_20m, psta->htpriv.sgi_40m);
+				RTW_INFO("ampdu_enable = %d\n", psta->htpriv.ampdu_enable);
+				RTW_INFO("agg_enable_bitmap=%x, candidate_tid_bitmap=%x\n", psta->htpriv.agg_enable_bitmap, psta->htpriv.candidate_tid_bitmap);
+#endif /* CONFIG_80211N_HT */
+
+				sta_rx_reorder_ctl_dump(RTW_DBGDUMP, psta);
+			} else
+				RTW_INFO("can't get sta's macaddr, cur_network's macaddr:" MAC_FMT "\n", MAC_ARG(cur_network->network.MacAddress));
+			break;
+		case 0x06: {
+				u64 tsf = 0;
+
+				tsf = rtw_hal_get_tsftr_by_port(padapter, extra_arg);
+				RTW_INFO(" PORT-%d TSF :%21lld\n", extra_arg, tsf);
+		}
+			break;
+		case 0x07:
+			RTW_INFO("bSurpriseRemoved=%s, bDriverStopped=%s\n"
+				, rtw_is_surprise_removed(padapter) ? "True" : "False"
+				, rtw_is_drv_stopped(padapter) ? "True" : "False");
+			break;
+		case 0x08: {
+			struct xmit_priv *pxmitpriv = &padapter->xmitpriv;
+			struct recv_priv  *precvpriv = &padapter->recvpriv;
+
+			RTW_INFO("free_xmitbuf_cnt=%d, free_xmitframe_cnt=%d"
+				", free_xmit_extbuf_cnt=%d, free_xframe_ext_cnt=%d"
+				 ", free_recvframe_cnt=%d\n",
+				pxmitpriv->free_xmitbuf_cnt, pxmitpriv->free_xmitframe_cnt,
+				pxmitpriv->free_xmit_extbuf_cnt, pxmitpriv->free_xframe_ext_cnt,
+				 precvpriv->free_recvframe_cnt);
+#ifdef CONFIG_USB_HCI
+			RTW_INFO("rx_urb_pending_cn=%d\n", ATOMIC_READ(&(precvpriv->rx_pending_cnt)));
+#endif
+		}
+			break;
+		case 0x09: {
+			int i;
+			_list	*plist, *phead;
+
+#ifdef CONFIG_AP_MODE
+			RTW_INFO_DUMP("sta_dz_bitmap:", pstapriv->sta_dz_bitmap, pstapriv->aid_bmp_len);
+			RTW_INFO_DUMP("tim_bitmap:", pstapriv->tim_bitmap, pstapriv->aid_bmp_len);
+#endif
+			_enter_critical_bh(&pstapriv->sta_hash_lock, &irqL);
+
+			for (i = 0; i < NUM_STA; i++) {
+				phead = &(pstapriv->sta_hash[i]);
+				plist = get_next(phead);
+
+				while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) {
+					psta = LIST_CONTAINOR(plist, struct sta_info, hash_list);
+
+					plist = get_next(plist);
+
+					if (extra_arg == psta->cmn.aid) {
+						RTW_INFO("sta's macaddr:" MAC_FMT "\n", MAC_ARG(psta->cmn.mac_addr));
+						RTW_INFO("rtsen=%d, cts2slef=%d\n", psta->rtsen, psta->cts2self);
+						RTW_INFO("state=0x%x, aid=%d, macid=%d, raid=%d\n",
+							psta->state, psta->cmn.aid, psta->cmn.mac_id, psta->cmn.ra_info.rate_id);
+#ifdef CONFIG_80211N_HT
+						RTW_INFO("qos_en=%d, ht_en=%d, init_rate=%d\n", psta->qos_option, psta->htpriv.ht_option, psta->init_rate);
+						RTW_INFO("bwmode=%d, ch_offset=%d, sgi_20m=%d,sgi_40m=%d\n",
+							psta->cmn.bw_mode, psta->htpriv.ch_offset, psta->htpriv.sgi_20m,
+							psta->htpriv.sgi_40m);
+						RTW_INFO("ampdu_enable = %d\n", psta->htpriv.ampdu_enable);
+						RTW_INFO("agg_enable_bitmap=%x, candidate_tid_bitmap=%x\n", psta->htpriv.agg_enable_bitmap, psta->htpriv.candidate_tid_bitmap);
+#endif /* CONFIG_80211N_HT */
+
+#ifdef CONFIG_AP_MODE
+						RTW_INFO("capability=0x%x\n", psta->capability);
+						RTW_INFO("flags=0x%x\n", psta->flags);
+						RTW_INFO("wpa_psk=0x%x\n", psta->wpa_psk);
+						RTW_INFO("wpa2_group_cipher=0x%x\n", psta->wpa2_group_cipher);
+						RTW_INFO("wpa2_pairwise_cipher=0x%x\n", psta->wpa2_pairwise_cipher);
+						RTW_INFO("qos_info=0x%x\n", psta->qos_info);
+#endif
+						RTW_INFO("dot118021XPrivacy=0x%x\n", psta->dot118021XPrivacy);
+
+						sta_rx_reorder_ctl_dump(RTW_DBGDUMP, psta);
+					}
+
+				}
+			}
+
+			_exit_critical_bh(&pstapriv->sta_hash_lock, &irqL);
+
+		}
+			break;
+
+		case 0x0b: { /* Enable=1, Disable=0 driver control vrtl_carrier_sense. */
+			/* u8 driver_vcs_en; */ /* Enable=1, Disable=0 driver control vrtl_carrier_sense. */
+			/* u8 driver_vcs_type; */ /* force 0:disable VCS, 1:RTS-CTS, 2:CTS-to-self when vcs_en=1. */
+
+			if (arg == 0) {
+				RTW_INFO("disable driver ctrl vcs\n");
+				padapter->driver_vcs_en = 0;
+			} else if (arg == 1) {
+				RTW_INFO("enable driver ctrl vcs = %d\n", extra_arg);
+				padapter->driver_vcs_en = 1;
+
+				if (extra_arg > 2)
+					padapter->driver_vcs_type = 1;
+				else
+					padapter->driver_vcs_type = extra_arg;
+			}
+		}
+			break;
+		case 0x0c: { /* dump rx/tx packet */
+			if (arg == 0) {
+				RTW_INFO("dump rx packet (%d)\n", extra_arg);
+				/* pHalData->bDumpRxPkt =extra_arg;						 */
+				rtw_hal_set_def_var(padapter, HAL_DEF_DBG_DUMP_RXPKT, &(extra_arg));
+			} else if (arg == 1) {
+				RTW_INFO("dump tx packet (%d)\n", extra_arg);
+				rtw_hal_set_def_var(padapter, HAL_DEF_DBG_DUMP_TXPKT, &(extra_arg));
+			}
+		}
+			break;
+		case 0x0e: {
+			if (arg == 0) {
+				RTW_INFO("disable driver ctrl rx_ampdu_factor\n");
+				padapter->driver_rx_ampdu_factor = 0xFF;
+			} else if (arg == 1) {
+
+				RTW_INFO("enable driver ctrl rx_ampdu_factor = %d\n", extra_arg);
+
+				if (extra_arg > 0x03)
+					padapter->driver_rx_ampdu_factor = 0xFF;
+				else
+					padapter->driver_rx_ampdu_factor = extra_arg;
+			}
+		}
+			break;
+		#ifdef DBG_CONFIG_ERROR_DETECT
+		case 0x0f: {
+			if (extra_arg == 0) {
+				RTW_INFO("###### silent reset test.......#####\n");
+				rtw_hal_sreset_reset(padapter);
+			} else {
+				HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(padapter);
+				struct sreset_priv *psrtpriv = &pHalData->srestpriv;
+				psrtpriv->dbg_trigger_point = extra_arg;
+			}
+
+		}
+			break;
+		case 0x15: {
+			struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter);
+			RTW_INFO("==>silent resete cnts:%d\n", pwrpriv->ips_enter_cnts);
+		}
+			break;
+
+		#endif
+
+		case 0x10: /* driver version display */
+			dump_drv_version(RTW_DBGDUMP);
+			break;
+		case 0x11: { /* dump linked status */
+			int pre_mode;
+			pre_mode = padapter->bLinkInfoDump;
+			/* linked_info_dump(padapter,extra_arg); */
+			if (extra_arg == 1 || (extra_arg == 0 && pre_mode == 1)) /* not consider pwr_saving 0: */
+				padapter->bLinkInfoDump = extra_arg;
+
+			else if ((extra_arg == 2) || (extra_arg == 0 && pre_mode == 2)) { /* consider power_saving */
+				/* RTW_INFO("linked_info_dump =%s\n", (padapter->bLinkInfoDump)?"enable":"disable") */
+				linked_info_dump(padapter, extra_arg);
+			}
+
+
+
+		}
+			break;
+#ifdef CONFIG_80211N_HT
+		case 0x12: { /* set rx_stbc */
+			struct registry_priv	*pregpriv = &padapter->registrypriv;
+			/* 0: disable, bit(0):enable 2.4g, bit(1):enable 5g, 0x3: enable both 2.4g and 5g */
+			/* default is set to enable 2.4GHZ for IOT issue with bufflao's AP at 5GHZ */
+			if (pregpriv && (extra_arg == 0 || extra_arg == 1 || extra_arg == 2 || extra_arg == 3)) {
+				pregpriv->rx_stbc = extra_arg;
+				RTW_INFO("set rx_stbc=%d\n", pregpriv->rx_stbc);
+			} else
+				RTW_INFO("get rx_stbc=%d\n", pregpriv->rx_stbc);
+
+		}
+			break;
+		case 0x13: { /* set ampdu_enable */
+			struct registry_priv	*pregpriv = &padapter->registrypriv;
+			/* 0: disable, 0x1:enable */
+			if (pregpriv && extra_arg < 2) {
+				pregpriv->ampdu_enable = extra_arg;
+				RTW_INFO("set ampdu_enable=%d\n", pregpriv->ampdu_enable);
+			} else
+				RTW_INFO("get ampdu_enable=%d\n", pregpriv->ampdu_enable);
+
+		}
+			break;
+#endif
+		case 0x14: { /* get wifi_spec */
+			struct registry_priv	*pregpriv = &padapter->registrypriv;
+			RTW_INFO("get wifi_spec=%d\n", pregpriv->wifi_spec);
+
+		}
+			break;
+
+#ifdef DBG_FIXED_CHAN
+		case 0x17: {
+			struct mlme_ext_priv	*pmlmeext = &(padapter->mlmeextpriv);
+			printk("===>  Fixed channel to %d\n", extra_arg);
+			pmlmeext->fixed_chan = extra_arg;
+
+		}
+			break;
+#endif
+#ifdef CONFIG_80211N_HT
+		case 0x19: {
+			struct registry_priv	*pregistrypriv = &padapter->registrypriv;
+			/* extra_arg : */
+			/* BIT0: Enable VHT LDPC Rx, BIT1: Enable VHT LDPC Tx, */
+			/* BIT4: Enable HT LDPC Rx, BIT5: Enable HT LDPC Tx */
+			if (arg == 0) {
+				RTW_INFO("driver disable LDPC\n");
+				pregistrypriv->ldpc_cap = 0x00;
+			} else if (arg == 1) {
+				RTW_INFO("driver set LDPC cap = 0x%x\n", extra_arg);
+				pregistrypriv->ldpc_cap = (u8)(extra_arg & 0x33);
+			}
+		}
+			break;
+		case 0x1a: {
+			struct registry_priv	*pregistrypriv = &padapter->registrypriv;
+			/* extra_arg : */
+			/* BIT0: Enable VHT STBC Rx, BIT1: Enable VHT STBC Tx, */
+			/* BIT4: Enable HT STBC Rx, BIT5: Enable HT STBC Tx */
+			if (arg == 0) {
+				RTW_INFO("driver disable STBC\n");
+				pregistrypriv->stbc_cap = 0x00;
+			} else if (arg == 1) {
+				RTW_INFO("driver set STBC cap = 0x%x\n", extra_arg);
+				pregistrypriv->stbc_cap = (u8)(extra_arg & 0x33);
+			}
+		}
+			break;
+#endif /* CONFIG_80211N_HT */
+		case 0x1b: {
+			struct registry_priv	*pregistrypriv = &padapter->registrypriv;
+
+			if (arg == 0) {
+				RTW_INFO("disable driver ctrl max_rx_rate, reset to default_rate_set\n");
+				init_mlme_default_rate_set(padapter);
+#ifdef CONFIG_80211N_HT
+				pregistrypriv->ht_enable = (u8)rtw_ht_enable;
+#endif /* CONFIG_80211N_HT */
+			} else if (arg == 1) {
+
+				int i;
+				u8 max_rx_rate;
+
+				RTW_INFO("enable driver ctrl max_rx_rate = 0x%x\n", extra_arg);
+
+				max_rx_rate = (u8)extra_arg;
+
+				if (max_rx_rate < 0xc) { /* max_rx_rate < MSC0->B or G -> disable HT */
+#ifdef CONFIG_80211N_HT
+					pregistrypriv->ht_enable = 0;
+#endif /* CONFIG_80211N_HT */
+					for (i = 0; i < NumRates; i++) {
+						if (pmlmeext->datarate[i] > max_rx_rate)
+							pmlmeext->datarate[i] = 0xff;
+					}
+
+				}
+#ifdef CONFIG_80211N_HT
+				else if (max_rx_rate < 0x1c) { /* mcs0~mcs15 */
+					u32 mcs_bitmap = 0x0;
+
+					for (i = 0; i < ((max_rx_rate + 1) - 0xc); i++)
+						mcs_bitmap |= BIT(i);
+
+					set_mcs_rate_by_mask(pmlmeext->default_supported_mcs_set, mcs_bitmap);
+				}
+#endif /* CONFIG_80211N_HT							 */
+			}
+		}
+			break;
+		case 0x1c: { /* enable/disable driver control AMPDU Density for peer sta's rx */
+			if (arg == 0) {
+				RTW_INFO("disable driver ctrl ampdu density\n");
+				padapter->driver_ampdu_spacing = 0xFF;
+			} else if (arg == 1) {
+
+				RTW_INFO("enable driver ctrl ampdu density = %d\n", extra_arg);
+
+				if (extra_arg > 0x07)
+					padapter->driver_ampdu_spacing = 0xFF;
+				else
+					padapter->driver_ampdu_spacing = extra_arg;
+			}
+		}
+			break;
+#ifdef CONFIG_BACKGROUND_NOISE_MONITOR
+		case 0x1e: {
+			RTW_INFO("===========================================\n");
+			rtw_noise_measure_curchan(padapter);
+			RTW_INFO("===========================================\n");
+		}
+			break;
+#endif
+
+
+#if defined(CONFIG_SDIO_HCI) && defined(CONFIG_SDIO_INDIRECT_ACCESS) && defined(DBG_SDIO_INDIRECT_ACCESS)
+		case 0x1f:
+			{
+				int i, j = 0, test_cnts = 0;
+				static u8 test_code = 0x5A;
+				static u32 data_misatch_cnt = 0, d_acc_err_cnt = 0;
+
+				u32 d_data, i_data;
+				u32 imr;
+
+				test_cnts = extra_arg;
+				for (i = 0; i < test_cnts; i++) {
+					if (RTW_CANNOT_IO(padapter))
+						break;
+
+					rtw_write8(padapter, 0x07, test_code);
+
+					d_data = rtw_read32(padapter, 0x04);
+					imr =  rtw_read32(padapter, 0x10250014);
+					rtw_write32(padapter, 0x10250014, 0);
+					rtw_msleep_os(50);
+
+					i_data = rtw_sd_iread32(padapter, 0x04);
+
+					rtw_write32(padapter, 0x10250014, imr);
+
+					if (d_data != i_data) {
+						data_misatch_cnt++;
+						RTW_ERR("d_data :0x%08x, i_data : 0x%08x\n", d_data, i_data);
+					}
+
+					if (test_code != (i_data >> 24)) {
+						d_acc_err_cnt++;
+						rtw_write8(padapter, 0x07, 0xAA);
+						RTW_ERR("test_code :0x%02x, i_data : 0x%08x\n", test_code, i_data);
+					}
+					if ((j++) == 100) {
+						rtw_msleep_os(2000);
+						RTW_INFO(" Indirect access testing..........%d/%d\n", i, test_cnts);
+						j = 0;
+					}
+
+					test_code = ~test_code;
+					rtw_msleep_os(50);
+				}
+				RTW_INFO("========Indirect access test=========\n");
+				RTW_INFO(" test_cnts = %d\n", test_cnts);
+				RTW_INFO(" direct & indirect read32 data missatch cnts = %d\n", data_misatch_cnt);
+				RTW_INFO(" indirect rdata is not equal to wdata cnts = %d\n", d_acc_err_cnt);
+				RTW_INFO("========Indirect access test=========\n\n");
+				data_misatch_cnt = d_acc_err_cnt = 0;
+
+			}
+			break;
+#endif
+		case 0x20:
+			{
+				if (arg == 0xAA) {
+					u8 page_offset, page_num;
+
+					page_offset = (u8)(extra_arg >> 16);
+					page_num = (u8)(extra_arg & 0xFF);
+					rtw_dump_rsvd_page(RTW_DBGDUMP, padapter, page_offset, page_num);
+				}
+#ifdef CONFIG_SUPPORT_FIFO_DUMP
+				else {
+					u8 fifo_sel;
+					u32 addr, size;
+
+					fifo_sel = (u8)(arg & 0x0F);
+					addr = (extra_arg >> 16) & 0xFFFF;
+					size = extra_arg & 0xFFFF;
+					rtw_dump_fifo(RTW_DBGDUMP, padapter, fifo_sel, addr, size);
+				}
+#endif
+			}
+			break;
+
+		case 0x23: {
+			RTW_INFO("turn %s the bNotifyChannelChange Variable\n", (extra_arg == 1) ? "on" : "off");
+			padapter->bNotifyChannelChange = extra_arg;
+			break;
+		}
+		case 0x24: {
+#ifdef CONFIG_P2P
+			RTW_INFO("turn %s the bShowGetP2PState Variable\n", (extra_arg == 1) ? "on" : "off");
+			padapter->bShowGetP2PState = extra_arg;
+#endif /* CONFIG_P2P */
+			break;
+		}
+#ifdef CONFIG_GPIO_API
+		case 0x25: { /* Get GPIO register */
+			/*
+			* dbg 0x7f250000 [gpio_num], Get gpio value, gpio_num:0~7
+			*/
+
+			u8 value;
+			RTW_INFO("Read GPIO Value  extra_arg = %d\n", extra_arg);
+			value = rtw_hal_get_gpio(padapter, extra_arg);
+			RTW_INFO("Read GPIO Value = %d\n", value);
+			break;
+		}
+		case 0x26: { /* Set GPIO direction */
+
+			/* dbg 0x7f26000x [y], Set gpio direction,
+			* x: gpio_num,4~7  y: indicate direction, 0~1
+			*/
+
+			int value;
+			RTW_INFO("Set GPIO Direction! arg = %d ,extra_arg=%d\n", arg , extra_arg);
+			value = rtw_hal_config_gpio(padapter, arg, extra_arg);
+			RTW_INFO("Set GPIO Direction %s\n", (value == -1) ? "Fail!!!" : "Success");
+			break;
+		}
+		case 0x27: { /* Set GPIO output direction value */
+			/*
+			* dbg 0x7f27000x [y], Set gpio output direction value,
+			* x: gpio_num,4~7  y: indicate direction, 0~1
+			*/
+
+			int value;
+			RTW_INFO("Set GPIO Value! arg = %d ,extra_arg=%d\n", arg , extra_arg);
+			value = rtw_hal_set_gpio_output_value(padapter, arg, extra_arg);
+			RTW_INFO("Set GPIO Value %s\n", (value == -1) ? "Fail!!!" : "Success");
+			break;
+		}
+#endif
+#ifdef DBG_CMD_QUEUE
+		case 0x28: {
+			dump_cmd_id = extra_arg;
+			RTW_INFO("dump_cmd_id:%d\n", dump_cmd_id);
+		}
+			break;
+#endif /* DBG_CMD_QUEUE */
+		case 0xaa: {
+			if ((extra_arg & 0x7F) > 0x3F)
+				extra_arg = 0xFF;
+			RTW_INFO("chang data rate to :0x%02x\n", extra_arg);
+			padapter->fix_rate = extra_arg;
+		}
+			break;
+		case 0xdd: { /* registers dump , 0 for mac reg,1 for bb reg, 2 for rf reg */
+			if (extra_arg == 0)
+				mac_reg_dump(RTW_DBGDUMP, padapter);
+			else if (extra_arg == 1)
+				bb_reg_dump(RTW_DBGDUMP, padapter);
+			else if (extra_arg == 2)
+				rf_reg_dump(RTW_DBGDUMP, padapter);
+			else if (extra_arg == 11)
+				bb_reg_dump_ex(RTW_DBGDUMP, padapter);
+		}
+			break;
+
+		case 0xee: {
+			RTW_INFO(" === please control /proc  to trun on/off PHYDM func ===\n");
+		}
+			break;
+
+		case 0xfd:
+			rtw_write8(padapter, 0xc50, arg);
+			RTW_INFO("wr(0xc50)=0x%x\n", rtw_read8(padapter, 0xc50));
+			rtw_write8(padapter, 0xc58, arg);
+			RTW_INFO("wr(0xc58)=0x%x\n", rtw_read8(padapter, 0xc58));
+			break;
+		case 0xfe:
+			RTW_INFO("rd(0xc50)=0x%x\n", rtw_read8(padapter, 0xc50));
+			RTW_INFO("rd(0xc58)=0x%x\n", rtw_read8(padapter, 0xc58));
+			break;
+		case 0xff: {
+			RTW_INFO("dbg(0x210)=0x%x\n", rtw_read32(padapter, 0x210));
+			RTW_INFO("dbg(0x608)=0x%x\n", rtw_read32(padapter, 0x608));
+			RTW_INFO("dbg(0x280)=0x%x\n", rtw_read32(padapter, 0x280));
+			RTW_INFO("dbg(0x284)=0x%x\n", rtw_read32(padapter, 0x284));
+			RTW_INFO("dbg(0x288)=0x%x\n", rtw_read32(padapter, 0x288));
+
+			RTW_INFO("dbg(0x664)=0x%x\n", rtw_read32(padapter, 0x664));
+
+
+			RTW_INFO("\n");
+
+			RTW_INFO("dbg(0x430)=0x%x\n", rtw_read32(padapter, 0x430));
+			RTW_INFO("dbg(0x438)=0x%x\n", rtw_read32(padapter, 0x438));
+
+			RTW_INFO("dbg(0x440)=0x%x\n", rtw_read32(padapter, 0x440));
+
+			RTW_INFO("dbg(0x458)=0x%x\n", rtw_read32(padapter, 0x458));
+
+			RTW_INFO("dbg(0x484)=0x%x\n", rtw_read32(padapter, 0x484));
+			RTW_INFO("dbg(0x488)=0x%x\n", rtw_read32(padapter, 0x488));
+
+			RTW_INFO("dbg(0x444)=0x%x\n", rtw_read32(padapter, 0x444));
+			RTW_INFO("dbg(0x448)=0x%x\n", rtw_read32(padapter, 0x448));
+			RTW_INFO("dbg(0x44c)=0x%x\n", rtw_read32(padapter, 0x44c));
+			RTW_INFO("dbg(0x450)=0x%x\n", rtw_read32(padapter, 0x450));
+		}
+			break;
+		}
+		break;
+	default:
+		RTW_INFO("error dbg cmd!\n");
+		break;
+	}
+
+
+	return ret;
+
+}
+
+static int wpa_set_param(struct net_device *dev, u8 name, u32 value)
+{
+	uint ret = 0;
+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
+
+	switch (name) {
+	case IEEE_PARAM_WPA_ENABLED:
+
+		padapter->securitypriv.dot11AuthAlgrthm = dot11AuthAlgrthm_8021X; /* 802.1x */
+
+		/* ret = ieee80211_wpa_enable(ieee, value); */
+
+		switch ((value) & 0xff) {
+		case 1: /* WPA */
+			padapter->securitypriv.ndisauthtype = Ndis802_11AuthModeWPAPSK; /* WPA_PSK */
+			padapter->securitypriv.ndisencryptstatus = Ndis802_11Encryption2Enabled;
+			break;
+		case 2: /* WPA2 */
+			padapter->securitypriv.ndisauthtype = Ndis802_11AuthModeWPA2PSK; /* WPA2_PSK */
+			padapter->securitypriv.ndisencryptstatus = Ndis802_11Encryption3Enabled;
+			break;
+		}
+
+
+		break;
+
+	case IEEE_PARAM_TKIP_COUNTERMEASURES:
+		/* ieee->tkip_countermeasures=value; */
+		break;
+
+	case IEEE_PARAM_DROP_UNENCRYPTED: {
+		/* HACK:
+		 *
+		 * wpa_supplicant calls set_wpa_enabled when the driver
+		 * is loaded and unloaded, regardless of if WPA is being
+		 * used.  No other calls are made which can be used to
+		 * determine if encryption will be used or not prior to
+		 * association being expected.  If encryption is not being
+		 * used, drop_unencrypted is set to false, else true -- we
+		 * can use this to determine if the CAP_PRIVACY_ON bit should
+		 * be set.
+		 */
+
+#if 0
+		struct ieee80211_security sec = {
+			.flags = SEC_ENABLED,
+			.enabled = value,
+		};
+		ieee->drop_unencrypted = value;
+		/* We only change SEC_LEVEL for open mode. Others
+		 * are set by ipw_wpa_set_encryption.
+		 */
+		if (!value) {
+			sec.flags |= SEC_LEVEL;
+			sec.level = SEC_LEVEL_0;
+		} else {
+			sec.flags |= SEC_LEVEL;
+			sec.level = SEC_LEVEL_1;
+		}
+		if (ieee->set_security)
+			ieee->set_security(ieee->dev, &sec);
+#endif
+		break;
+
+	}
+	case IEEE_PARAM_PRIVACY_INVOKED:
+
+		/* ieee->privacy_invoked=value; */
+
+		break;
+
+	case IEEE_PARAM_AUTH_ALGS:
+
+		ret = wpa_set_auth_algs(dev, value);
+
+		break;
+
+	case IEEE_PARAM_IEEE_802_1X:
+
+		/* ieee->ieee802_1x=value;		 */
+
+		break;
+
+	case IEEE_PARAM_WPAX_SELECT:
+
+		/* added for WPA2 mixed mode */
+		/*RTW_WARN("------------------------>wpax value = %x\n", value);*/
+		/*
+		spin_lock_irqsave(&ieee->wpax_suitlist_lock,flags);
+		ieee->wpax_type_set = 1;
+		ieee->wpax_type_notify = value;
+		spin_unlock_irqrestore(&ieee->wpax_suitlist_lock,flags);
+		*/
+
+		break;
+
+	default:
+
+
+
+		ret = -EOPNOTSUPP;
+
+
+		break;
+
+	}
+
+	return ret;
+
+}
+
+static int wpa_mlme(struct net_device *dev, u32 command, u32 reason)
+{
+	int ret = 0;
+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
+
+	switch (command) {
+	case IEEE_MLME_STA_DEAUTH:
+
+		if (!rtw_set_802_11_disassociate(padapter))
+			ret = -1;
+
+		break;
+
+	case IEEE_MLME_STA_DISASSOC:
+
+		if (!rtw_set_802_11_disassociate(padapter))
+			ret = -1;
+
+		break;
+
+	default:
+		ret = -EOPNOTSUPP;
+		break;
+	}
+#ifdef CONFIG_RTW_REPEATER_SON
+	rtw_rson_do_disconnect(padapter);
+#endif
+	return ret;
+
+}
+
+static int wpa_supplicant_ioctl(struct net_device *dev, struct iw_point *p)
+{
+	struct ieee_param *param;
+	uint ret = 0;
+
+	/* down(&ieee->wx_sem);	 */
+
+	if (p->length < sizeof(struct ieee_param) || !p->pointer) {
+		ret = -EINVAL;
+		goto out;
+	}
+
+	param = (struct ieee_param *)rtw_malloc(p->length);
+	if (param == NULL) {
+		ret = -ENOMEM;
+		goto out;
+	}
+
+	if (copy_from_user(param, p->pointer, p->length)) {
+		rtw_mfree((u8 *)param, p->length);
+		ret = -EFAULT;
+		goto out;
+	}
+
+	switch (param->cmd) {
+
+	case IEEE_CMD_SET_WPA_PARAM:
+		ret = wpa_set_param(dev, param->u.wpa_param.name, param->u.wpa_param.value);
+		break;
+
+	case IEEE_CMD_SET_WPA_IE:
+		/* ret = wpa_set_wpa_ie(dev, param, p->length); */
+		ret =  rtw_set_wpa_ie((_adapter *)rtw_netdev_priv(dev), (char *)param->u.wpa_ie.data, (u16)param->u.wpa_ie.len);
+		break;
+
+	case IEEE_CMD_SET_ENCRYPTION:
+		ret = wpa_set_encryption(dev, param, p->length);
+		break;
+
+	case IEEE_CMD_MLME:
+		ret = wpa_mlme(dev, param->u.mlme.command, param->u.mlme.reason_code);
+		break;
+
+	default:
+		RTW_INFO("Unknown WPA supplicant request: %d\n", param->cmd);
+		ret = -EOPNOTSUPP;
+		break;
+
+	}
+
+	if (ret == 0 && copy_to_user(p->pointer, param, p->length))
+		ret = -EFAULT;
+
+	rtw_mfree((u8 *)param, p->length);
+
+out:
+
+	/* up(&ieee->wx_sem); */
+
+	return ret;
+
+}
+
+#ifdef CONFIG_AP_MODE
+static int rtw_set_encryption(struct net_device *dev, struct ieee_param *param, u32 param_len)
+{
+	int ret = 0;
+	u32 wep_key_idx, wep_key_len, wep_total_len;
+	NDIS_802_11_WEP	*pwep = NULL;
+	struct sta_info *psta = NULL, *pbcmc_sta = NULL;
+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
+	struct mlme_priv	*pmlmepriv = &padapter->mlmepriv;
+	struct security_priv *psecuritypriv = &(padapter->securitypriv);
+	struct sta_priv *pstapriv = &padapter->stapriv;
+
+	RTW_INFO("%s\n", __FUNCTION__);
+
+	param->u.crypt.err = 0;
+	param->u.crypt.alg[IEEE_CRYPT_ALG_NAME_LEN - 1] = '\0';
+
+	/* sizeof(struct ieee_param) = 64 bytes; */
+	/* if (param_len !=  (u32) ((u8 *) param->u.crypt.key - (u8 *) param) + param->u.crypt.key_len) */
+	if (param_len !=  sizeof(struct ieee_param) + param->u.crypt.key_len) {
+		ret =  -EINVAL;
+		goto exit;
+	}
+
+	if (param->sta_addr[0] == 0xff && param->sta_addr[1] == 0xff &&
+	    param->sta_addr[2] == 0xff && param->sta_addr[3] == 0xff &&
+	    param->sta_addr[4] == 0xff && param->sta_addr[5] == 0xff) {
+		if (param->u.crypt.idx >= WEP_KEYS
+#ifdef CONFIG_IEEE80211W
+		    && param->u.crypt.idx > BIP_MAX_KEYID
+#endif /* CONFIG_IEEE80211W */
+		   ) {
+			ret = -EINVAL;
+			goto exit;
+		}
+	} else {
+		psta = rtw_get_stainfo(pstapriv, param->sta_addr);
+		if (!psta) {
+			/* ret = -EINVAL; */
+			RTW_INFO("rtw_set_encryption(), sta has already been removed or never been added\n");
+			goto exit;
+		}
+	}
+
+	if (strcmp(param->u.crypt.alg, "none") == 0 && (psta == NULL)) {
+		/* todo:clear default encryption keys */
+
+		psecuritypriv->dot11AuthAlgrthm = dot11AuthAlgrthm_Open;
+		psecuritypriv->ndisencryptstatus = Ndis802_11EncryptionDisabled;
+		psecuritypriv->dot11PrivacyAlgrthm = _NO_PRIVACY_;
+		psecuritypriv->dot118021XGrpPrivacy = _NO_PRIVACY_;
+
+		RTW_INFO("clear default encryption keys, keyid=%d\n", param->u.crypt.idx);
+
+		goto exit;
+	}
+
+
+	if (strcmp(param->u.crypt.alg, "WEP") == 0 && (psta == NULL)) {
+		RTW_INFO("r871x_set_encryption, crypt.alg = WEP\n");
+
+		wep_key_idx = param->u.crypt.idx;
+		wep_key_len = param->u.crypt.key_len;
+
+		RTW_INFO("r871x_set_encryption, wep_key_idx=%d, len=%d\n", wep_key_idx, wep_key_len);
+
+		if ((wep_key_idx >= WEP_KEYS) || (wep_key_len <= 0)) {
+			ret = -EINVAL;
+			goto exit;
+		}
+
+
+		if (wep_key_len > 0) {
+			wep_key_len = wep_key_len <= 5 ? 5 : 13;
+			wep_total_len = wep_key_len + FIELD_OFFSET(NDIS_802_11_WEP, KeyMaterial);
+			pwep = (NDIS_802_11_WEP *)rtw_malloc(wep_total_len);
+			if (pwep == NULL) {
+				RTW_INFO(" r871x_set_encryption: pwep allocate fail !!!\n");
+				goto exit;
+			}
+
+			_rtw_memset(pwep, 0, wep_total_len);
+
+			pwep->KeyLength = wep_key_len;
+			pwep->Length = wep_total_len;
+
+		}
+
+		pwep->KeyIndex = wep_key_idx;
+
+		_rtw_memcpy(pwep->KeyMaterial,  param->u.crypt.key, pwep->KeyLength);
+
+		if (param->u.crypt.set_tx) {
+			RTW_INFO("wep, set_tx=1\n");
+
+			psecuritypriv->dot11AuthAlgrthm = dot11AuthAlgrthm_Auto;
+			psecuritypriv->ndisencryptstatus = Ndis802_11Encryption1Enabled;
+			psecuritypriv->dot11PrivacyAlgrthm = _WEP40_;
+			psecuritypriv->dot118021XGrpPrivacy = _WEP40_;
+
+			if (pwep->KeyLength == 13) {
+				psecuritypriv->dot11PrivacyAlgrthm = _WEP104_;
+				psecuritypriv->dot118021XGrpPrivacy = _WEP104_;
+			}
+
+
+			psecuritypriv->dot11PrivacyKeyIndex = wep_key_idx;
+
+			_rtw_memcpy(&(psecuritypriv->dot11DefKey[wep_key_idx].skey[0]), pwep->KeyMaterial, pwep->KeyLength);
+
+			psecuritypriv->dot11DefKeylen[wep_key_idx] = pwep->KeyLength;
+
+			rtw_ap_set_wep_key(padapter, pwep->KeyMaterial, pwep->KeyLength, wep_key_idx, 1);
+		} else {
+			RTW_INFO("wep, set_tx=0\n");
+
+			/* don't update "psecuritypriv->dot11PrivacyAlgrthm" and  */
+			/* "psecuritypriv->dot11PrivacyKeyIndex=keyid", but can rtw_set_key to cam */
+
+			_rtw_memcpy(&(psecuritypriv->dot11DefKey[wep_key_idx].skey[0]), pwep->KeyMaterial, pwep->KeyLength);
+
+			psecuritypriv->dot11DefKeylen[wep_key_idx] = pwep->KeyLength;
+
+			rtw_ap_set_wep_key(padapter, pwep->KeyMaterial, pwep->KeyLength, wep_key_idx, 0);
+		}
+
+		goto exit;
+
+	}
+
+
+	if (!psta && check_fwstate(pmlmepriv, WIFI_AP_STATE)) /*  */ { /* group key */
+		if (param->u.crypt.set_tx == 1) {
+			if (strcmp(param->u.crypt.alg, "WEP") == 0) {
+				RTW_INFO(FUNC_ADPT_FMT" set WEP TX GTK idx:%u, len:%u\n"
+					, FUNC_ADPT_ARG(padapter), param->u.crypt.idx, param->u.crypt.key_len);
+				_rtw_memcpy(psecuritypriv->dot118021XGrpKey[param->u.crypt.idx].skey,  param->u.crypt.key, (param->u.crypt.key_len > 16 ? 16 : param->u.crypt.key_len));
+				psecuritypriv->dot118021XGrpPrivacy = _WEP40_;
+				if (param->u.crypt.key_len == 13)
+					psecuritypriv->dot118021XGrpPrivacy = _WEP104_;
+
+			} else if (strcmp(param->u.crypt.alg, "TKIP") == 0) {
+				RTW_INFO(FUNC_ADPT_FMT" set TKIP TX GTK idx:%u, len:%u\n"
+					, FUNC_ADPT_ARG(padapter), param->u.crypt.idx, param->u.crypt.key_len);
+				psecuritypriv->dot118021XGrpPrivacy = _TKIP_;
+				_rtw_memcpy(psecuritypriv->dot118021XGrpKey[param->u.crypt.idx].skey,  param->u.crypt.key, (param->u.crypt.key_len > 16 ? 16 : param->u.crypt.key_len));
+				/* set mic key */
+				_rtw_memcpy(psecuritypriv->dot118021XGrptxmickey[param->u.crypt.idx].skey, &(param->u.crypt.key[16]), 8);
+				_rtw_memcpy(psecuritypriv->dot118021XGrprxmickey[param->u.crypt.idx].skey, &(param->u.crypt.key[24]), 8);
+				psecuritypriv->busetkipkey = _TRUE;
+
+			} else if (strcmp(param->u.crypt.alg, "CCMP") == 0) {
+				RTW_INFO(FUNC_ADPT_FMT" set CCMP TX GTK idx:%u, len:%u\n"
+					, FUNC_ADPT_ARG(padapter), param->u.crypt.idx, param->u.crypt.key_len);
+				psecuritypriv->dot118021XGrpPrivacy = _AES_;
+				_rtw_memcpy(psecuritypriv->dot118021XGrpKey[param->u.crypt.idx].skey,  param->u.crypt.key, (param->u.crypt.key_len > 16 ? 16 : param->u.crypt.key_len));
+
+			#ifdef CONFIG_IEEE80211W
+			} else if (strcmp(param->u.crypt.alg, "BIP") == 0) {
+				RTW_INFO(FUNC_ADPT_FMT" set TX IGTK idx:%u, len:%u\n"
+					, FUNC_ADPT_ARG(padapter), param->u.crypt.idx, param->u.crypt.key_len);
+				_rtw_memcpy(padapter->securitypriv.dot11wBIPKey[param->u.crypt.idx].skey, param->u.crypt.key, (param->u.crypt.key_len > 16 ? 16 : param->u.crypt.key_len));
+				psecuritypriv->dot11wBIPKeyid = param->u.crypt.idx;
+				psecuritypriv->dot11wBIPtxpn.val = RTW_GET_LE64(param->u.crypt.seq);
+				psecuritypriv->binstallBIPkey = _TRUE;
+				goto exit;
+			#endif /* CONFIG_IEEE80211W */
+
+			} else if (strcmp(param->u.crypt.alg, "none") == 0) {
+				RTW_INFO(FUNC_ADPT_FMT" clear group key, idx:%u\n"
+					, FUNC_ADPT_ARG(padapter), param->u.crypt.idx);
+				psecuritypriv->dot118021XGrpPrivacy = _NO_PRIVACY_;
+			} else {
+				RTW_WARN(FUNC_ADPT_FMT" set group key, not support\n"
+					, FUNC_ADPT_ARG(padapter));
+				goto exit;
+			}
+
+			psecuritypriv->dot118021XGrpKeyid = param->u.crypt.idx;
+			pbcmc_sta = rtw_get_bcmc_stainfo(padapter);
+			if (pbcmc_sta) {
+				pbcmc_sta->dot11txpn.val = RTW_GET_LE64(param->u.crypt.seq);
+				pbcmc_sta->ieee8021x_blocked = _FALSE;
+				pbcmc_sta->dot118021XPrivacy = psecuritypriv->dot118021XGrpPrivacy; /* rx will use bmc_sta's dot118021XPrivacy			 */
+			}
+			psecuritypriv->binstallGrpkey = _TRUE;
+			psecuritypriv->dot11PrivacyAlgrthm = psecuritypriv->dot118021XGrpPrivacy;/* !!! */
+
+			rtw_ap_set_group_key(padapter, param->u.crypt.key, psecuritypriv->dot118021XGrpPrivacy, param->u.crypt.idx);
+		}
+
+		goto exit;
+
+	}
+
+	if (psecuritypriv->dot11AuthAlgrthm == dot11AuthAlgrthm_8021X && psta) { /* psk/802_1x */
+		if (check_fwstate(pmlmepriv, WIFI_AP_STATE)) {
+			if (param->u.crypt.set_tx == 1) {
+				_rtw_memcpy(psta->dot118021x_UncstKey.skey,  param->u.crypt.key, (param->u.crypt.key_len > 16 ? 16 : param->u.crypt.key_len));
+
+				if (strcmp(param->u.crypt.alg, "WEP") == 0) {
+					RTW_INFO(FUNC_ADPT_FMT" set WEP PTK of "MAC_FMT" idx:%u, len:%u\n"
+						, FUNC_ADPT_ARG(padapter), MAC_ARG(psta->cmn.mac_addr)
+						, param->u.crypt.idx, param->u.crypt.key_len);
+					psta->dot118021XPrivacy = _WEP40_;
+					if (param->u.crypt.key_len == 13)
+						psta->dot118021XPrivacy = _WEP104_;
+
+				} else if (strcmp(param->u.crypt.alg, "TKIP") == 0) {
+					RTW_INFO(FUNC_ADPT_FMT" set TKIP PTK of "MAC_FMT" idx:%u, len:%u\n"
+						, FUNC_ADPT_ARG(padapter), MAC_ARG(psta->cmn.mac_addr)
+						, param->u.crypt.idx, param->u.crypt.key_len);
+					psta->dot118021XPrivacy = _TKIP_;
+					/* set mic key */
+					_rtw_memcpy(psta->dot11tkiptxmickey.skey, &(param->u.crypt.key[16]), 8);
+					_rtw_memcpy(psta->dot11tkiprxmickey.skey, &(param->u.crypt.key[24]), 8);
+					psecuritypriv->busetkipkey = _TRUE;
+
+				} else if (strcmp(param->u.crypt.alg, "CCMP") == 0) {
+					RTW_INFO(FUNC_ADPT_FMT" set CCMP PTK of "MAC_FMT" idx:%u, len:%u\n"
+						, FUNC_ADPT_ARG(padapter), MAC_ARG(psta->cmn.mac_addr)
+						, param->u.crypt.idx, param->u.crypt.key_len);
+					psta->dot118021XPrivacy = _AES_;
+
+				} else if (strcmp(param->u.crypt.alg, "none") == 0) {
+					RTW_INFO(FUNC_ADPT_FMT" clear pairwise key of "MAC_FMT" idx:%u\n"
+						, FUNC_ADPT_ARG(padapter), MAC_ARG(psta->cmn.mac_addr)
+						, param->u.crypt.idx);
+					psta->dot118021XPrivacy = _NO_PRIVACY_;
+
+				} else {
+					RTW_WARN(FUNC_ADPT_FMT" set pairwise key of "MAC_FMT", not support\n"
+						, FUNC_ADPT_ARG(padapter), MAC_ARG(psta->cmn.mac_addr));
+					goto exit;
+				}
+
+				psta->dot11txpn.val = RTW_GET_LE64(param->u.crypt.seq);
+				psta->dot11rxpn.val = RTW_GET_LE64(param->u.crypt.seq);
+				psta->ieee8021x_blocked = _FALSE;
+
+				if (psta->dot118021XPrivacy != _NO_PRIVACY_) {
+					psta->bpairwise_key_installed = _TRUE;
+
+					/* WPA2 key-handshake has completed */
+					if (psecuritypriv->ndisauthtype == Ndis802_11AuthModeWPA2PSK)
+						psta->state &= (~WIFI_UNDER_KEY_HANDSHAKE);
+				}
+
+				rtw_ap_set_pairwise_key(padapter, psta);
+			} else {
+				RTW_WARN(FUNC_ADPT_FMT" set group key of "MAC_FMT", not support\n"
+					, FUNC_ADPT_ARG(padapter), MAC_ARG(psta->cmn.mac_addr));
+				goto exit;
+			}
+
+		}
+
+	}
+
+exit:
+
+	if (pwep)
+		rtw_mfree((u8 *)pwep, wep_total_len);
+
+	return ret;
+
+}
+
+static int rtw_set_beacon(struct net_device *dev, struct ieee_param *param, int len)
+{
+	int ret = 0;
+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
+	struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
+	struct sta_priv *pstapriv = &padapter->stapriv;
+	unsigned char *pbuf = param->u.bcn_ie.buf;
+
+
+	RTW_INFO("%s, len=%d\n", __FUNCTION__, len);
+
+	if (check_fwstate(pmlmepriv, WIFI_AP_STATE) != _TRUE)
+		return -EINVAL;
+
+	_rtw_memcpy(&pstapriv->max_num_sta, param->u.bcn_ie.reserved, 2);
+
+	if ((pstapriv->max_num_sta > NUM_STA) || (pstapriv->max_num_sta <= 0))
+		pstapriv->max_num_sta = NUM_STA;
+
+
+	if (rtw_check_beacon_data(padapter, pbuf, (len - 12 - 2)) == _SUCCESS) /* 12 = param header, 2:no packed */
+		ret = 0;
+	else
+		ret = -EINVAL;
+
+
+	return ret;
+
+}
+
+static int rtw_hostapd_sta_flush(struct net_device *dev)
+{
+	/* _irqL irqL; */
+	/* _list	*phead, *plist; */
+	int ret = 0;
+	/* struct sta_info *psta = NULL; */
+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
+	/* struct sta_priv *pstapriv = &padapter->stapriv; */
+
+	RTW_INFO("%s\n", __FUNCTION__);
+
+	flush_all_cam_entry(padapter);	/* clear CAM */
+#ifdef CONFIG_AP_MODE
+	ret = rtw_sta_flush(padapter, _TRUE);
+#endif
+	return ret;
+
+}
+
+static int rtw_add_sta(struct net_device *dev, struct ieee_param *param)
+{
+	int ret = 0;
+	struct sta_info *psta = NULL;
+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
+	struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
+	struct sta_priv *pstapriv = &padapter->stapriv;
+
+	RTW_INFO("rtw_add_sta(aid=%d)=" MAC_FMT "\n", param->u.add_sta.aid, MAC_ARG(param->sta_addr));
+
+	if (check_fwstate(pmlmepriv, (_FW_LINKED | WIFI_AP_STATE)) != _TRUE)
+		return -EINVAL;
+
+	if (param->sta_addr[0] == 0xff && param->sta_addr[1] == 0xff &&
+	    param->sta_addr[2] == 0xff && param->sta_addr[3] == 0xff &&
+	    param->sta_addr[4] == 0xff && param->sta_addr[5] == 0xff)
+		return -EINVAL;
+
+#if 0
+	psta = rtw_get_stainfo(pstapriv, param->sta_addr);
+	if (psta) {
+		RTW_INFO("rtw_add_sta(), free has been added psta=%p\n", psta);
+		/* _enter_critical_bh(&(pstapriv->sta_hash_lock), &irqL);		 */
+		rtw_free_stainfo(padapter,  psta);
+		/* _exit_critical_bh(&(pstapriv->sta_hash_lock), &irqL); */
+
+		psta = NULL;
+	}
+#endif
+	/* psta = rtw_alloc_stainfo(pstapriv, param->sta_addr); */
+	psta = rtw_get_stainfo(pstapriv, param->sta_addr);
+	if (psta) {
+		int flags = param->u.add_sta.flags;
+
+		/* RTW_INFO("rtw_add_sta(), init sta's variables, psta=%p\n", psta); */
+
+		psta->cmn.aid = param->u.add_sta.aid;/* aid=1~2007 */
+
+		_rtw_memcpy(psta->bssrateset, param->u.add_sta.tx_supp_rates, 16);
+
+
+		/* check wmm cap. */
+		if (WLAN_STA_WME & flags)
+			psta->qos_option = 1;
+		else
+			psta->qos_option = 0;
+
+		if (pmlmepriv->qospriv.qos_option == 0)
+			psta->qos_option = 0;
+
+
+#ifdef CONFIG_80211N_HT
+		/* chec 802.11n ht cap. */
+		if (padapter->registrypriv.ht_enable &&
+			is_supported_ht(padapter->registrypriv.wireless_mode) &&
+			(WLAN_STA_HT & flags)) {
+			psta->htpriv.ht_option = _TRUE;
+			psta->qos_option = 1;
+			_rtw_memcpy((void *)&psta->htpriv.ht_cap, (void *)&param->u.add_sta.ht_cap, sizeof(struct rtw_ieee80211_ht_cap));
+		} else
+			psta->htpriv.ht_option = _FALSE;
+
+		if (pmlmepriv->htpriv.ht_option == _FALSE)
+			psta->htpriv.ht_option = _FALSE;
+
+#endif
+
+
+		update_sta_info_apmode(padapter, psta);
+
+
+	} else
+		ret = -ENOMEM;
+
+	return ret;
+
+}
+
+static int rtw_del_sta(struct net_device *dev, struct ieee_param *param)
+{
+	_irqL irqL;
+	int ret = 0;
+	struct sta_info *psta = NULL;
+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
+	struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
+	struct sta_priv *pstapriv = &padapter->stapriv;
+
+	RTW_INFO("rtw_del_sta=" MAC_FMT "\n", MAC_ARG(param->sta_addr));
+
+	if (check_fwstate(pmlmepriv, (_FW_LINKED | WIFI_AP_STATE)) != _TRUE)
+		return -EINVAL;
+
+	if (param->sta_addr[0] == 0xff && param->sta_addr[1] == 0xff &&
+	    param->sta_addr[2] == 0xff && param->sta_addr[3] == 0xff &&
+	    param->sta_addr[4] == 0xff && param->sta_addr[5] == 0xff)
+		return -EINVAL;
+
+	psta = rtw_get_stainfo(pstapriv, param->sta_addr);
+	if (psta) {
+		u8 updated = _FALSE;
+
+		/* RTW_INFO("free psta=%p, aid=%d\n", psta, psta->cmn.aid); */
+
+		_enter_critical_bh(&pstapriv->asoc_list_lock, &irqL);
+		if (rtw_is_list_empty(&psta->asoc_list) == _FALSE) {
+			rtw_list_delete(&psta->asoc_list);
+			pstapriv->asoc_list_cnt--;
+			updated = ap_free_sta(padapter, psta, _TRUE, WLAN_REASON_DEAUTH_LEAVING, _TRUE);
+
+		}
+		_exit_critical_bh(&pstapriv->asoc_list_lock, &irqL);
+
+		associated_clients_update(padapter, updated, STA_INFO_UPDATE_ALL);
+
+		psta = NULL;
+
+	} else {
+		RTW_INFO("rtw_del_sta(), sta has already been removed or never been added\n");
+
+		/* ret = -1; */
+	}
+
+
+	return ret;
+
+}
+
+static int rtw_ioctl_get_sta_data(struct net_device *dev, struct ieee_param *param, int len)
+{
+	int ret = 0;
+	struct sta_info *psta = NULL;
+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
+	struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
+	struct sta_priv *pstapriv = &padapter->stapriv;
+	struct ieee_param_ex *param_ex = (struct ieee_param_ex *)param;
+	struct sta_data *psta_data = (struct sta_data *)param_ex->data;
+
+	RTW_INFO("rtw_ioctl_get_sta_info, sta_addr: " MAC_FMT "\n", MAC_ARG(param_ex->sta_addr));
+
+	if (check_fwstate(pmlmepriv, (_FW_LINKED | WIFI_AP_STATE)) != _TRUE)
+		return -EINVAL;
+
+	if (param_ex->sta_addr[0] == 0xff && param_ex->sta_addr[1] == 0xff &&
+	    param_ex->sta_addr[2] == 0xff && param_ex->sta_addr[3] == 0xff &&
+	    param_ex->sta_addr[4] == 0xff && param_ex->sta_addr[5] == 0xff)
+		return -EINVAL;
+
+	psta = rtw_get_stainfo(pstapriv, param_ex->sta_addr);
+	if (psta) {
+#if 0
+		struct {
+			u16 aid;
+			u16 capability;
+			int flags;
+			u32 sta_set;
+			u8 tx_supp_rates[16];
+			u32 tx_supp_rates_len;
+			struct rtw_ieee80211_ht_cap ht_cap;
+			u64	rx_pkts;
+			u64	rx_bytes;
+			u64	rx_drops;
+			u64	tx_pkts;
+			u64	tx_bytes;
+			u64	tx_drops;
+		} get_sta;
+#endif
+		psta_data->aid = (u16)psta->cmn.aid;
+		psta_data->capability = psta->capability;
+		psta_data->flags = psta->flags;
+
+		/*
+				nonerp_set : BIT(0)
+				no_short_slot_time_set : BIT(1)
+				no_short_preamble_set : BIT(2)
+				no_ht_gf_set : BIT(3)
+				no_ht_set : BIT(4)
+				ht_20mhz_set : BIT(5)
+		*/
+
+		psta_data->sta_set = ((psta->nonerp_set) |
+				      (psta->no_short_slot_time_set << 1) |
+				      (psta->no_short_preamble_set << 2) |
+				      (psta->no_ht_gf_set << 3) |
+				      (psta->no_ht_set << 4) |
+				      (psta->ht_20mhz_set << 5));
+
+		psta_data->tx_supp_rates_len =  psta->bssratelen;
+		_rtw_memcpy(psta_data->tx_supp_rates, psta->bssrateset, psta->bssratelen);
+#ifdef CONFIG_80211N_HT
+		if(padapter->registrypriv.ht_enable && is_supported_ht(padapter->registrypriv.wireless_mode))
+			_rtw_memcpy(&psta_data->ht_cap, &psta->htpriv.ht_cap, sizeof(struct rtw_ieee80211_ht_cap));
+#endif /* CONFIG_80211N_HT */
+		psta_data->rx_pkts = psta->sta_stats.rx_data_pkts;
+		psta_data->rx_bytes = psta->sta_stats.rx_bytes;
+		psta_data->rx_drops = psta->sta_stats.rx_drops;
+
+		psta_data->tx_pkts = psta->sta_stats.tx_pkts;
+		psta_data->tx_bytes = psta->sta_stats.tx_bytes;
+		psta_data->tx_drops = psta->sta_stats.tx_drops;
+
+
+	} else
+		ret = -1;
+
+	return ret;
+
+}
+
+static int rtw_get_sta_wpaie(struct net_device *dev, struct ieee_param *param)
+{
+	int ret = 0;
+	struct sta_info *psta = NULL;
+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
+	struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
+	struct sta_priv *pstapriv = &padapter->stapriv;
+
+	RTW_INFO("rtw_get_sta_wpaie, sta_addr: " MAC_FMT "\n", MAC_ARG(param->sta_addr));
+
+	if (check_fwstate(pmlmepriv, (_FW_LINKED | WIFI_AP_STATE)) != _TRUE)
+		return -EINVAL;
+
+	if (param->sta_addr[0] == 0xff && param->sta_addr[1] == 0xff &&
+	    param->sta_addr[2] == 0xff && param->sta_addr[3] == 0xff &&
+	    param->sta_addr[4] == 0xff && param->sta_addr[5] == 0xff)
+		return -EINVAL;
+
+	psta = rtw_get_stainfo(pstapriv, param->sta_addr);
+	if (psta) {
+		if ((psta->wpa_ie[0] == WLAN_EID_RSN) || (psta->wpa_ie[0] == WLAN_EID_GENERIC)) {
+			int wpa_ie_len;
+			int copy_len;
+
+			wpa_ie_len = psta->wpa_ie[1];
+
+			copy_len = ((wpa_ie_len + 2) > sizeof(psta->wpa_ie)) ? (sizeof(psta->wpa_ie)) : (wpa_ie_len + 2);
+
+			param->u.wpa_ie.len = copy_len;
+
+			_rtw_memcpy(param->u.wpa_ie.reserved, psta->wpa_ie, copy_len);
+		} else {
+			/* ret = -1; */
+			RTW_INFO("sta's wpa_ie is NONE\n");
+		}
+	} else
+		ret = -1;
+
+	return ret;
+
+}
+
+static int rtw_set_wps_beacon(struct net_device *dev, struct ieee_param *param, int len)
+{
+	int ret = 0;
+	unsigned char wps_oui[4] = {0x0, 0x50, 0xf2, 0x04};
+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
+	struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
+	struct mlme_ext_priv	*pmlmeext = &(padapter->mlmeextpriv);
+	int ie_len;
+
+	RTW_INFO("%s, len=%d\n", __FUNCTION__, len);
+
+	if (check_fwstate(pmlmepriv, WIFI_AP_STATE) != _TRUE)
+		return -EINVAL;
+
+	ie_len = len - 12 - 2; /* 12 = param header, 2:no packed */
+
+
+	if (pmlmepriv->wps_beacon_ie) {
+		rtw_mfree(pmlmepriv->wps_beacon_ie, pmlmepriv->wps_beacon_ie_len);
+		pmlmepriv->wps_beacon_ie = NULL;
+	}
+
+	if (ie_len > 0) {
+		pmlmepriv->wps_beacon_ie = rtw_malloc(ie_len);
+		pmlmepriv->wps_beacon_ie_len = ie_len;
+		if (pmlmepriv->wps_beacon_ie == NULL) {
+			RTW_INFO("%s()-%d: rtw_malloc() ERROR!\n", __FUNCTION__, __LINE__);
+			return -EINVAL;
+		}
+
+		_rtw_memcpy(pmlmepriv->wps_beacon_ie, param->u.bcn_ie.buf, ie_len);
+
+		update_beacon(padapter, _VENDOR_SPECIFIC_IE_, wps_oui, _TRUE);
+
+		pmlmeext->bstart_bss = _TRUE;
+
+	}
+
+
+	return ret;
+
+}
+
+static int rtw_set_wps_probe_resp(struct net_device *dev, struct ieee_param *param, int len)
+{
+	int ret = 0;
+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
+	struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
+	int ie_len;
+
+	RTW_INFO("%s, len=%d\n", __FUNCTION__, len);
+
+	if (check_fwstate(pmlmepriv, WIFI_AP_STATE) != _TRUE)
+		return -EINVAL;
+
+	ie_len = len - 12 - 2; /* 12 = param header, 2:no packed */
+
+
+	if (pmlmepriv->wps_probe_resp_ie) {
+		rtw_mfree(pmlmepriv->wps_probe_resp_ie, pmlmepriv->wps_probe_resp_ie_len);
+		pmlmepriv->wps_probe_resp_ie = NULL;
+	}
+
+	if (ie_len > 0) {
+		pmlmepriv->wps_probe_resp_ie = rtw_malloc(ie_len);
+		pmlmepriv->wps_probe_resp_ie_len = ie_len;
+		if (pmlmepriv->wps_probe_resp_ie == NULL) {
+			RTW_INFO("%s()-%d: rtw_malloc() ERROR!\n", __FUNCTION__, __LINE__);
+			return -EINVAL;
+		}
+		_rtw_memcpy(pmlmepriv->wps_probe_resp_ie, param->u.bcn_ie.buf, ie_len);
+	}
+
+
+	return ret;
+
+}
+
+static int rtw_set_wps_assoc_resp(struct net_device *dev, struct ieee_param *param, int len)
+{
+	int ret = 0;
+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
+	struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
+	int ie_len;
+
+	RTW_INFO("%s, len=%d\n", __FUNCTION__, len);
+
+	if (check_fwstate(pmlmepriv, WIFI_AP_STATE) != _TRUE)
+		return -EINVAL;
+
+	ie_len = len - 12 - 2; /* 12 = param header, 2:no packed */
+
+
+	if (pmlmepriv->wps_assoc_resp_ie) {
+		rtw_mfree(pmlmepriv->wps_assoc_resp_ie, pmlmepriv->wps_assoc_resp_ie_len);
+		pmlmepriv->wps_assoc_resp_ie = NULL;
+	}
+
+	if (ie_len > 0) {
+		pmlmepriv->wps_assoc_resp_ie = rtw_malloc(ie_len);
+		pmlmepriv->wps_assoc_resp_ie_len = ie_len;
+		if (pmlmepriv->wps_assoc_resp_ie == NULL) {
+			RTW_INFO("%s()-%d: rtw_malloc() ERROR!\n", __FUNCTION__, __LINE__);
+			return -EINVAL;
+		}
+
+		_rtw_memcpy(pmlmepriv->wps_assoc_resp_ie, param->u.bcn_ie.buf, ie_len);
+	}
+
+
+	return ret;
+
+}
+
+static int rtw_set_hidden_ssid(struct net_device *dev, struct ieee_param *param, int len)
+{
+	int ret = 0;
+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
+	struct mlme_priv *mlmepriv = &(adapter->mlmepriv);
+	struct mlme_ext_priv	*mlmeext = &(adapter->mlmeextpriv);
+	struct mlme_ext_info	*mlmeinfo = &(mlmeext->mlmext_info);
+	int ie_len;
+	u8 *ssid_ie;
+	char ssid[NDIS_802_11_LENGTH_SSID + 1];
+	sint ssid_len = 0;
+	u8 ignore_broadcast_ssid;
+
+	if (check_fwstate(mlmepriv, WIFI_AP_STATE) != _TRUE)
+		return -EPERM;
+
+	if (param->u.bcn_ie.reserved[0] != 0xea)
+		return -EINVAL;
+
+	mlmeinfo->hidden_ssid_mode = ignore_broadcast_ssid = param->u.bcn_ie.reserved[1];
+
+	ie_len = len - 12 - 2; /* 12 = param header, 2:no packed */
+	ssid_ie = rtw_get_ie(param->u.bcn_ie.buf,  WLAN_EID_SSID, &ssid_len, ie_len);
+
+	if (ssid_ie && ssid_len > 0 && ssid_len <= NDIS_802_11_LENGTH_SSID) {
+		WLAN_BSSID_EX *pbss_network = &mlmepriv->cur_network.network;
+		WLAN_BSSID_EX *pbss_network_ext = &mlmeinfo->network;
+
+		_rtw_memcpy(ssid, ssid_ie + 2, ssid_len);
+		ssid[ssid_len] = 0x0;
+
+		if (0)
+			RTW_INFO(FUNC_ADPT_FMT" ssid:(%s,%d), from ie:(%s,%d), (%s,%d)\n", FUNC_ADPT_ARG(adapter),
+				ssid, ssid_len,
+				pbss_network->Ssid.Ssid, pbss_network->Ssid.SsidLength,
+				pbss_network_ext->Ssid.Ssid, pbss_network_ext->Ssid.SsidLength);
+
+		_rtw_memcpy(pbss_network->Ssid.Ssid, (void *)ssid, ssid_len);
+		pbss_network->Ssid.SsidLength = ssid_len;
+		_rtw_memcpy(pbss_network_ext->Ssid.Ssid, (void *)ssid, ssid_len);
+		pbss_network_ext->Ssid.SsidLength = ssid_len;
+
+		if (0)
+			RTW_INFO(FUNC_ADPT_FMT" after ssid:(%s,%d), (%s,%d)\n", FUNC_ADPT_ARG(adapter),
+				pbss_network->Ssid.Ssid, pbss_network->Ssid.SsidLength,
+				pbss_network_ext->Ssid.Ssid, pbss_network_ext->Ssid.SsidLength);
+	}
+
+	RTW_INFO(FUNC_ADPT_FMT" ignore_broadcast_ssid:%d, %s,%d\n", FUNC_ADPT_ARG(adapter),
+		ignore_broadcast_ssid, ssid, ssid_len);
+
+	return ret;
+}
+
+#if CONFIG_RTW_MACADDR_ACL
+static int rtw_ioctl_acl_remove_sta(struct net_device *dev, struct ieee_param *param, int len)
+{
+	int ret = 0;
+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
+	struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
+
+	if (check_fwstate(pmlmepriv, WIFI_AP_STATE) != _TRUE)
+		return -EINVAL;
+
+	if (param->sta_addr[0] == 0xff && param->sta_addr[1] == 0xff &&
+	    param->sta_addr[2] == 0xff && param->sta_addr[3] == 0xff &&
+	    param->sta_addr[4] == 0xff && param->sta_addr[5] == 0xff)
+		return -EINVAL;
+
+	ret = rtw_acl_remove_sta(padapter, RTW_ACL_PERIOD_BSS, param->sta_addr);
+
+	return ret;
+
+}
+
+static int rtw_ioctl_acl_add_sta(struct net_device *dev, struct ieee_param *param, int len)
+{
+	int ret = 0;
+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
+	struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
+
+	if (check_fwstate(pmlmepriv, WIFI_AP_STATE) != _TRUE)
+		return -EINVAL;
+
+	if (param->sta_addr[0] == 0xff && param->sta_addr[1] == 0xff &&
+	    param->sta_addr[2] == 0xff && param->sta_addr[3] == 0xff &&
+	    param->sta_addr[4] == 0xff && param->sta_addr[5] == 0xff)
+		return -EINVAL;
+
+	ret = rtw_acl_add_sta(padapter, RTW_ACL_PERIOD_BSS, param->sta_addr);
+
+	return ret;
+
+}
+
+static int rtw_ioctl_set_macaddr_acl(struct net_device *dev, struct ieee_param *param, int len)
+{
+	int ret = 0;
+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
+	struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
+
+	if (check_fwstate(pmlmepriv, WIFI_AP_STATE) != _TRUE)
+		return -EINVAL;
+
+	rtw_set_macaddr_acl(padapter, RTW_ACL_PERIOD_BSS, param->u.mlme.command);
+
+	return ret;
+}
+#endif /* CONFIG_RTW_MACADDR_ACL */
+
+static int rtw_hostapd_ioctl(struct net_device *dev, struct iw_point *p)
+{
+	struct ieee_param *param;
+	int ret = 0;
+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
+
+	/* RTW_INFO("%s\n", __FUNCTION__); */
+
+	/*
+	* this function is expect to call in master mode, which allows no power saving
+	* so, we just check hw_init_completed
+	*/
+
+	if (!rtw_is_hw_init_completed(padapter)) {
+		ret = -EPERM;
+		goto out;
+	}
+
+
+	/* if (p->length < sizeof(struct ieee_param) || !p->pointer){ */
+	if (!p->pointer) {
+		ret = -EINVAL;
+		goto out;
+	}
+
+	param = (struct ieee_param *)rtw_malloc(p->length);
+	if (param == NULL) {
+		ret = -ENOMEM;
+		goto out;
+	}
+
+	if (copy_from_user(param, p->pointer, p->length)) {
+		rtw_mfree((u8 *)param, p->length);
+		ret = -EFAULT;
+		goto out;
+	}
+
+	/* RTW_INFO("%s, cmd=%d\n", __FUNCTION__, param->cmd); */
+
+	switch (param->cmd) {
+	case RTL871X_HOSTAPD_FLUSH:
+
+		ret = rtw_hostapd_sta_flush(dev);
+
+		break;
+
+	case RTL871X_HOSTAPD_ADD_STA:
+
+		ret = rtw_add_sta(dev, param);
+
+		break;
+
+	case RTL871X_HOSTAPD_REMOVE_STA:
+
+		ret = rtw_del_sta(dev, param);
+
+		break;
+
+	case RTL871X_HOSTAPD_SET_BEACON:
+
+		ret = rtw_set_beacon(dev, param, p->length);
+
+		break;
+
+	case RTL871X_SET_ENCRYPTION:
+
+		ret = rtw_set_encryption(dev, param, p->length);
+
+		break;
+
+	case RTL871X_HOSTAPD_GET_WPAIE_STA:
+
+		ret = rtw_get_sta_wpaie(dev, param);
+
+		break;
+
+	case RTL871X_HOSTAPD_SET_WPS_BEACON:
+
+		ret = rtw_set_wps_beacon(dev, param, p->length);
+
+		break;
+
+	case RTL871X_HOSTAPD_SET_WPS_PROBE_RESP:
+
+		ret = rtw_set_wps_probe_resp(dev, param, p->length);
+
+		break;
+
+	case RTL871X_HOSTAPD_SET_WPS_ASSOC_RESP:
+
+		ret = rtw_set_wps_assoc_resp(dev, param, p->length);
+
+		break;
+
+	case RTL871X_HOSTAPD_SET_HIDDEN_SSID:
+
+		ret = rtw_set_hidden_ssid(dev, param, p->length);
+
+		break;
+
+	case RTL871X_HOSTAPD_GET_INFO_STA:
+
+		ret = rtw_ioctl_get_sta_data(dev, param, p->length);
+
+		break;
+
+#if CONFIG_RTW_MACADDR_ACL
+	case RTL871X_HOSTAPD_SET_MACADDR_ACL:
+		ret = rtw_ioctl_set_macaddr_acl(dev, param, p->length);
+		break;
+	case RTL871X_HOSTAPD_ACL_ADD_STA:
+		ret = rtw_ioctl_acl_add_sta(dev, param, p->length);
+		break;
+	case RTL871X_HOSTAPD_ACL_REMOVE_STA:
+		ret = rtw_ioctl_acl_remove_sta(dev, param, p->length);
+		break;
+#endif /* CONFIG_RTW_MACADDR_ACL */
+
+	default:
+		RTW_INFO("Unknown hostapd request: %d\n", param->cmd);
+		ret = -EOPNOTSUPP;
+		break;
+
+	}
+
+	if (ret == 0 && copy_to_user(p->pointer, param, p->length))
+		ret = -EFAULT;
+
+
+	rtw_mfree((u8 *)param, p->length);
+
+out:
+
+	return ret;
+
+}
+#endif
+
+static int rtw_wx_set_priv(struct net_device *dev,
+			   struct iw_request_info *info,
+			   union iwreq_data *awrq,
+			   char *extra)
+{
+
+#ifdef CONFIG_DEBUG_RTW_WX_SET_PRIV
+	char *ext_dbg;
+#endif
+
+	int ret = 0;
+	int len = 0;
+	char *ext;
+#ifdef CONFIG_ANDROID
+	int i;
+#endif
+
+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
+	struct iw_point *dwrq = (struct iw_point *)awrq;
+
+	if (dwrq->length == 0)
+		return -EFAULT;
+
+	len = dwrq->length;
+	ext = rtw_vmalloc(len);
+	if (!ext)
+		return -ENOMEM;
+
+	if (copy_from_user(ext, dwrq->pointer, len)) {
+		rtw_vmfree(ext, len);
+		return -EFAULT;
+	}
+
+
+
+#ifdef CONFIG_DEBUG_RTW_WX_SET_PRIV
+	ext_dbg = rtw_vmalloc(len);
+	if (!ext_dbg) {
+		rtw_vmfree(ext, len);
+		return -ENOMEM;
+	}
+
+	_rtw_memcpy(ext_dbg, ext, len);
+#endif
+
+	/* added for wps2.0 @20110524 */
+	if (dwrq->flags == 0x8766 && len > 8) {
+		u32 cp_sz;
+		struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
+		u8 *probereq_wpsie = ext;
+		int probereq_wpsie_len = len;
+		u8 wps_oui[4] = {0x0, 0x50, 0xf2, 0x04};
+
+		if ((_VENDOR_SPECIFIC_IE_ == probereq_wpsie[0]) &&
+		    (_rtw_memcmp(&probereq_wpsie[2], wps_oui, 4) == _TRUE)) {
+			cp_sz = probereq_wpsie_len > MAX_WPS_IE_LEN ? MAX_WPS_IE_LEN : probereq_wpsie_len;
+
+			if (pmlmepriv->wps_probe_req_ie) {
+				u32 free_len = pmlmepriv->wps_probe_req_ie_len;
+				pmlmepriv->wps_probe_req_ie_len = 0;
+				rtw_mfree(pmlmepriv->wps_probe_req_ie, free_len);
+				pmlmepriv->wps_probe_req_ie = NULL;
+			}
+
+			pmlmepriv->wps_probe_req_ie = rtw_malloc(cp_sz);
+			if (pmlmepriv->wps_probe_req_ie == NULL) {
+				printk("%s()-%d: rtw_malloc() ERROR!\n", __FUNCTION__, __LINE__);
+				ret =  -EINVAL;
+				goto FREE_EXT;
+
+			}
+
+			_rtw_memcpy(pmlmepriv->wps_probe_req_ie, probereq_wpsie, cp_sz);
+			pmlmepriv->wps_probe_req_ie_len = cp_sz;
+
+		}
+
+		goto FREE_EXT;
+
+	}
+
+	if (len >= WEXT_CSCAN_HEADER_SIZE
+		&& _rtw_memcmp(ext, WEXT_CSCAN_HEADER, WEXT_CSCAN_HEADER_SIZE) == _TRUE
+	) {
+		ret = rtw_wx_set_scan(dev, info, awrq, ext);
+		goto FREE_EXT;
+	}
+
+#ifdef CONFIG_ANDROID
+	/* RTW_INFO("rtw_wx_set_priv: %s req=%s\n", dev->name, ext); */
+
+	i = rtw_android_cmdstr_to_num(ext);
+
+	switch (i) {
+	case ANDROID_WIFI_CMD_START:
+		indicate_wx_custom_event(padapter, "START");
+		break;
+	case ANDROID_WIFI_CMD_STOP:
+		indicate_wx_custom_event(padapter, "STOP");
+		break;
+	case ANDROID_WIFI_CMD_RSSI: {
+		struct	mlme_priv	*pmlmepriv = &(padapter->mlmepriv);
+		struct	wlan_network	*pcur_network = &pmlmepriv->cur_network;
+
+		if (check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE)
+			sprintf(ext, "%s rssi %d", pcur_network->network.Ssid.Ssid, padapter->recvpriv.rssi);
+		else
+			sprintf(ext, "OK");
+	}
+		break;
+	case ANDROID_WIFI_CMD_LINKSPEED: {
+		u16 mbps = rtw_get_cur_max_rate(padapter) / 10;
+		sprintf(ext, "LINKSPEED %d", mbps);
+	}
+		break;
+	case ANDROID_WIFI_CMD_MACADDR:
+		sprintf(ext, "MACADDR = " MAC_FMT, MAC_ARG(dev->dev_addr));
+		break;
+	case ANDROID_WIFI_CMD_SCAN_ACTIVE: {
+		/* rtw_set_scan_mode(padapter, SCAN_ACTIVE); */
+		sprintf(ext, "OK");
+	}
+		break;
+	case ANDROID_WIFI_CMD_SCAN_PASSIVE: {
+		/* rtw_set_scan_mode(padapter, SCAN_PASSIVE); */
+		sprintf(ext, "OK");
+	}
+		break;
+
+	case ANDROID_WIFI_CMD_COUNTRY: {
+		char country_code[10];
+		sscanf(ext, "%*s %s", country_code);
+		rtw_set_country(padapter, country_code);
+		sprintf(ext, "OK");
+	}
+		break;
+	default:
+		#ifdef CONFIG_DEBUG_RTW_WX_SET_PRIV
+		RTW_INFO("%s: %s unknowned req=%s\n", __FUNCTION__,
+			dev->name, ext_dbg);
+		#endif
+
+		sprintf(ext, "OK");
+
+	}
+
+	if (copy_to_user(dwrq->pointer, ext, min(dwrq->length, (u16)(strlen(ext) + 1))))
+		ret = -EFAULT;
+
+#ifdef CONFIG_DEBUG_RTW_WX_SET_PRIV
+	RTW_INFO("%s: %s req=%s rep=%s dwrq->length=%d, strlen(ext)+1=%d\n", __FUNCTION__,
+		dev->name, ext_dbg , ext, dwrq->length, (u16)(strlen(ext) + 1));
+#endif
+#endif /* end of CONFIG_ANDROID */
+
+
+FREE_EXT:
+
+	rtw_vmfree(ext, len);
+	#ifdef CONFIG_DEBUG_RTW_WX_SET_PRIV
+	rtw_vmfree(ext_dbg, len);
+	#endif
+
+	/* RTW_INFO("rtw_wx_set_priv: (SIOCSIWPRIV) %s ret=%d\n",  */
+	/*		dev->name, ret); */
+
+	return ret;
+
+}
+#ifdef CONFIG_WOWLAN
+static int rtw_wowlan_ctrl(struct net_device *dev,
+			   struct iw_request_info *info,
+			   union iwreq_data *wrqu, char *extra)
+{
+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
+	struct wowlan_ioctl_param poidparam;
+	struct pwrctrl_priv *pwrctrlpriv = adapter_to_pwrctl(padapter);
+	struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
+	struct sta_info	*psta = NULL;
+	int ret = 0;
+	systime start_time = rtw_get_current_time();
+	poidparam.subcode = 0;
+
+	RTW_INFO("+rtw_wowlan_ctrl: %s\n", extra);
+
+	if (!check_fwstate(pmlmepriv, _FW_LINKED) &&
+	    check_fwstate(pmlmepriv, WIFI_STATION_STATE)) {
+#ifdef CONFIG_PNO_SUPPORT
+		pwrctrlpriv->wowlan_pno_enable = _TRUE;
+#else
+		RTW_INFO("[%s] WARNING: Please Connect With AP First!!\n", __func__);
+		goto _rtw_wowlan_ctrl_exit_free;
+#endif /* CONFIG_PNO_SUPPORT */
+	}
+
+	if (check_fwstate(pmlmepriv, _FW_UNDER_SURVEY))
+		rtw_scan_abort(padapter);
+
+	if (_rtw_memcmp(extra, "enable", 6))
+
+
+		rtw_suspend_common(padapter);
+
+	else if (_rtw_memcmp(extra, "disable", 7)) {
+#ifdef CONFIG_USB_HCI
+		RTW_ENABLE_FUNC(padapter, DF_RX_BIT);
+		RTW_ENABLE_FUNC(padapter, DF_TX_BIT);
+#endif
+		rtw_resume_common(padapter);
+
+#ifdef CONFIG_PNO_SUPPORT
+		pwrctrlpriv->wowlan_pno_enable = _FALSE;
+#endif /* CONFIG_PNO_SUPPORT */
+
+	} else {
+		RTW_INFO("[%s] Invalid Parameter.\n", __func__);
+		goto _rtw_wowlan_ctrl_exit_free;
+	}
+	/* mutex_lock(&ioctl_mutex); */
+_rtw_wowlan_ctrl_exit_free:
+	RTW_INFO("-rtw_wowlan_ctrl( subcode = %d)\n", poidparam.subcode);
+	RTW_PRINT("%s in %d ms\n", __func__,
+		  rtw_get_passing_time_ms(start_time));
+_rtw_wowlan_ctrl_exit:
+	return ret;
+}
+
+/*
+ * IP filter This pattern if for a frame containing a ip packet:
+ * AA:AA:AA:AA:AA:AA:BB:BB:BB:BB:BB:BB:CC:CC:DD:-:-:-:-:-:-:-:-:EE:-:-:FF:FF:FF:FF:GG:GG:GG:GG:HH:HH:II:II
+ *
+ * A: Ethernet destination address
+ * B: Ethernet source address
+ * C: Ethernet protocol type
+ * D: IP header VER+Hlen, use: 0x45 (4 is for ver 4, 5 is for len 20)
+ * E: IP protocol
+ * F: IP source address ( 192.168.0.4: C0:A8:00:2C )
+ * G: IP destination address ( 192.168.0.4: C0:A8:00:2C )
+ * H: Source port (1024: 04:00)
+ * I: Destination port (1024: 04:00)
+ */
+
+static int rtw_wowlan_set_pattern(struct net_device *dev,
+				  struct iw_request_info *info,
+				  union iwreq_data *wrqu, char *extra)
+{
+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
+	struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter);
+	struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
+	struct wowlan_ioctl_param poidparam;
+	int ret = 0, len = 0, i = 0;
+	systime start_time = rtw_get_current_time();
+	u8 input[wrqu->data.length];
+	u8 index = 0;
+
+	poidparam.subcode = 0;
+
+	if (!check_fwstate(pmlmepriv, _FW_LINKED) &&
+	    check_fwstate(pmlmepriv, WIFI_STATION_STATE)) {
+		ret = -EFAULT;
+		RTW_INFO("Please Connect With AP First!!\n");
+		goto _rtw_wowlan_set_pattern_exit;
+	}
+
+	if (wrqu->data.length <= 0) {
+		ret = -EFAULT;
+		RTW_INFO("ERROR: parameter length <= 0\n");
+		goto _rtw_wowlan_set_pattern_exit;
+	} else {
+		/* set pattern */
+		if (copy_from_user(input,
+				   wrqu->data.pointer, wrqu->data.length))
+			return -EFAULT;
+		/* leave PS first */
+		rtw_ps_deny(padapter, PS_DENY_IOCTL);
+		LeaveAllPowerSaveModeDirect(padapter);
+		if (strncmp(input, "pattern=", 8) == 0) {
+			if (pwrpriv->wowlan_pattern_idx >= MAX_WKFM_CAM_NUM) {
+				RTW_INFO("WARNING: priv-pattern is full(idx: %d)\n",
+					 pwrpriv->wowlan_pattern_idx);
+				RTW_INFO("WARNING: please clean priv-pattern first\n");
+				ret = -EINVAL;
+				goto _rtw_wowlan_set_pattern_exit;
+			} else {
+				index = pwrpriv->wowlan_pattern_idx;
+				ret = rtw_wowlan_parser_pattern_cmd(input,
+					    pwrpriv->patterns[index].content,
+					    &pwrpriv->patterns[index].len,
+					    pwrpriv->patterns[index].mask);
+
+				if (ret == _TRUE)
+					pwrpriv->wowlan_pattern_idx++;
+			}
+		} else if (strncmp(input, "clean", 5) == 0) {
+			poidparam.subcode = WOWLAN_PATTERN_CLEAN;
+			rtw_hal_set_hwreg(padapter,
+					  HW_VAR_WOWLAN, (u8 *)&poidparam);
+		} else if (strncmp(input, "show", 4) == 0) {
+			rtw_wow_pattern_cam_dump(padapter);
+			rtw_wow_pattern_sw_dump(padapter);
+		} else {
+			RTW_INFO("ERROR: incorrect parameter!\n");
+			ret = -EINVAL;
+		}
+		rtw_ps_deny_cancel(padapter, PS_DENY_IOCTL);
+	}
+_rtw_wowlan_set_pattern_exit:
+	return ret;
+}
+#endif /* CONFIG_WOWLAN */
+
+#ifdef CONFIG_AP_WOWLAN
+static int rtw_ap_wowlan_ctrl(struct net_device *dev,
+			      struct iw_request_info *info,
+			      union iwreq_data *wrqu, char *extra)
+{
+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
+	struct wowlan_ioctl_param poidparam;
+	struct pwrctrl_priv *pwrctrlpriv = adapter_to_pwrctl(padapter);
+	struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
+	struct sta_info	*psta = NULL;
+	int ret = 0;
+	systime start_time = rtw_get_current_time();
+	poidparam.subcode = 0;
+
+	RTW_INFO("+rtw_ap_wowlan_ctrl: %s\n", extra);
+
+	if (!check_fwstate(pmlmepriv, WIFI_AP_STATE)) {
+		RTW_INFO("[%s] It is not AP mode!!\n", __func__);
+		goto _rtw_ap_wowlan_ctrl_exit_free;
+	}
+
+	if (_rtw_memcmp(extra, "enable", 6)) {
+
+		pwrctrlpriv->wowlan_ap_mode = _TRUE;
+
+		rtw_suspend_common(padapter);
+	} else if (_rtw_memcmp(extra, "disable", 7)) {
+#ifdef CONFIG_USB_HCI
+		RTW_ENABLE_FUNC(padapter, DF_RX_BIT);
+		RTW_ENABLE_FUNC(padapter, DF_TX_BIT);
+#endif
+		rtw_resume_common(padapter);
+	} else {
+		RTW_INFO("[%s] Invalid Parameter.\n", __func__);
+		goto _rtw_ap_wowlan_ctrl_exit_free;
+	}
+	/* mutex_lock(&ioctl_mutex); */
+_rtw_ap_wowlan_ctrl_exit_free:
+	RTW_INFO("-rtw_ap_wowlan_ctrl( subcode = %d)\n", poidparam.subcode);
+	RTW_PRINT("%s in %d ms\n", __func__,
+		  rtw_get_passing_time_ms(start_time));
+_rtw_ap_wowlan_ctrl_exit:
+	return ret;
+}
+#endif /* CONFIG_AP_WOWLAN */
+
+static int rtw_pm_set(struct net_device *dev,
+		      struct iw_request_info *info,
+		      union iwreq_data *wrqu, char *extra)
+{
+	int ret = 0;
+	unsigned	mode = 0;
+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
+
+	RTW_INFO("[%s] extra = %s\n", __FUNCTION__, extra);
+
+	if (_rtw_memcmp(extra, "lps=", 4)) {
+		sscanf(extra + 4, "%u", &mode);
+		ret = rtw_pm_set_lps(padapter, mode);
+	} else if (_rtw_memcmp(extra, "ips=", 4)) {
+		sscanf(extra + 4, "%u", &mode);
+		ret = rtw_pm_set_ips(padapter, mode);
+	} else if (_rtw_memcmp(extra, "lps_level=", 10)) {
+		if (sscanf(extra + 10, "%u", &mode) > 0)
+			ret = rtw_pm_set_lps_level(padapter, mode);
+	} else
+		ret = -EINVAL;
+
+	return ret;
+}
+#ifdef CONFIG_APPEND_VENDOR_IE_ENABLE
+
+int rtw_vendor_ie_get_raw_data(struct net_device *dev, u32 vendor_ie_num,
+							   char *extra, u32 length)
+{
+	int j;
+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
+	struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
+	u32 vendor_ie_mask = 0;
+	char *pstring;
+
+	if (vendor_ie_num >= WLAN_MAX_VENDOR_IE_NUM) {
+		RTW_INFO("[%s] only support %d vendor ie\n", __func__ ,
+				 WLAN_MAX_VENDOR_IE_NUM);
+		return -EFAULT;
+	}
+
+	if (pmlmepriv->vendor_ielen[vendor_ie_num] == 0) {
+		RTW_INFO("[%s]  Fail, vendor_ie_num: %d is not set\n", __func__,
+				 vendor_ie_num);
+		return -EFAULT;
+	}
+
+	if (length < 2 * pmlmepriv->vendor_ielen[vendor_ie_num] + 5) {
+		RTW_INFO("[%s]  Fail, buffer size is too small\n", __func__);
+		return -EFAULT;
+	}
+
+	vendor_ie_mask = pmlmepriv->vendor_ie_mask[vendor_ie_num];
+	_rtw_memset(extra, 0, length);
+
+	pstring = extra;
+	pstring += sprintf(pstring, "%d,%x,", vendor_ie_num, vendor_ie_mask);
+
+	for (j = 0; j < pmlmepriv->vendor_ielen[vendor_ie_num]; j++)
+		pstring += sprintf(pstring, "%02x", pmlmepriv->vendor_ie[vendor_ie_num][j]);
+
+	length = pstring - extra;
+	return length;
+}
+
+int rtw_vendor_ie_get_data(struct net_device *dev, int vendor_ie_num, char *extra)
+{
+	int j;
+	char *pstring;
+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
+	struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
+	u32 vendor_ie_mask = 0;
+	__u16 length = 0;
+
+	vendor_ie_mask = pmlmepriv->vendor_ie_mask[vendor_ie_num];
+	pstring = extra;
+	pstring += sprintf(pstring , "\nVendor IE num %d , Mask:%x " , vendor_ie_num , vendor_ie_mask);
+
+	if (vendor_ie_mask & WIFI_BEACON_VENDOR_IE_BIT)
+		pstring += sprintf(pstring , "[Beacon]");
+	if (vendor_ie_mask & WIFI_PROBEREQ_VENDOR_IE_BIT)
+		pstring += sprintf(pstring , "[Probe Req]");
+	if (vendor_ie_mask & WIFI_PROBERESP_VENDOR_IE_BIT)
+		pstring += sprintf(pstring , "[Probe Resp]");
+	if (vendor_ie_mask & WIFI_ASSOCREQ_VENDOR_IE_BIT)
+		pstring += sprintf(pstring , "[Assoc Req]");
+	if (vendor_ie_mask & WIFI_ASSOCRESP_VENDOR_IE_BIT)
+		pstring += sprintf(pstring , "[Assoc Resp]");
+
+	pstring += sprintf(pstring , "\nVendor IE:\n");
+	for (j = 0 ; j < pmlmepriv->vendor_ielen[vendor_ie_num]  ; j++)
+		pstring += sprintf(pstring , "%02x" , pmlmepriv->vendor_ie[vendor_ie_num][j]);
+
+	length = pstring - extra;
+	return length;
+
+}
+
+int rtw_vendor_ie_get(struct net_device *dev, struct iw_request_info *info, union iwreq_data *wrqu, char *extra)
+{
+	int ret = 0, vendor_ie_num = 0, cmdlen;
+	struct iw_point *p;
+	u8 *ptmp;
+
+	p = &wrqu->data;
+	cmdlen = p->length;
+	if (0 == cmdlen)
+		return -EINVAL;
+
+	ptmp = (u8 *)rtw_malloc(cmdlen);
+	if (NULL == ptmp)
+		return -ENOMEM;
+
+	if (copy_from_user(ptmp, p->pointer, cmdlen)) {
+		ret = -EFAULT;
+		goto exit;
+	}
+	ret = sscanf(ptmp , "%d", &vendor_ie_num);
+	if (vendor_ie_num > WLAN_MAX_VENDOR_IE_NUM - 1) {
+		ret = -EFAULT;
+		goto exit;
+	}
+
+	wrqu->data.length = rtw_vendor_ie_get_data(dev, vendor_ie_num, extra);
+
+exit:
+	rtw_mfree(ptmp, cmdlen);
+
+	return 0;
+}
+
+int rtw_vendor_ie_set(struct net_device *dev, struct iw_request_info *info, union iwreq_data *wrqu, char *extra)
+{
+	int ret = 0, i , len = 0 , totoal_ie_len = 0 , total_ie_len_byte = 0;
+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
+	struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
+	u32 vendor_ie_mask = 0;
+	u32 vendor_ie_num = 0;
+	u32 id, elen;
+
+	ret = sscanf(extra, "%d,%x,%*s", &vendor_ie_num , &vendor_ie_mask);
+	if (strrchr(extra , ','))
+		extra = strrchr(extra , ',') + 1;
+	else
+		return -EINVAL;
+	totoal_ie_len = strlen(extra);
+	RTW_INFO("[%s] vendor_ie_num = %d , vendor_ie_mask = %x , vendor_ie = %s , len = %d\n", __func__ , vendor_ie_num , vendor_ie_mask , extra  , totoal_ie_len);
+
+	if (vendor_ie_num  > WLAN_MAX_VENDOR_IE_NUM - 1) {
+		RTW_INFO("[%s] only support %d vendor ie\n", __func__ , WLAN_MAX_VENDOR_IE_NUM);
+		return -EFAULT;
+	}
+
+	if (totoal_ie_len > WLAN_MAX_VENDOR_IE_LEN) {
+		RTW_INFO("[%s] Fail , not support ie length extend %d\n", __func__ , WLAN_MAX_VENDOR_IE_LEN);
+		return -EFAULT;
+	}
+
+	if (vendor_ie_mask == 0) {
+		RTW_INFO("[%s] Clear vendor_ie_num %d group\n", __func__ , vendor_ie_num);
+		goto _clear_path;
+	}
+
+	if (totoal_ie_len % 2 != 0) {
+		RTW_INFO("[%s]  Fail , IE length = %zu is odd\n" , __func__ , strlen(extra));
+		return -EFAULT;
+	}
+
+	if (totoal_ie_len > 0) {
+		for (i = 0  ; i < strlen(extra) ; i += 2) {
+			pmlmepriv->vendor_ie[vendor_ie_num][len] = key_2char2num(extra[i] , extra[i + 1]);
+			if (len == 0) {
+				id = pmlmepriv->vendor_ie[vendor_ie_num][len];
+				if (id != WLAN_EID_VENDOR_SPECIFIC) {
+					RTW_INFO("[%s] Fail , VENDOR SPECIFIC IE ID \"%x\" was not correct\n", __func__ , id);
+					goto _clear_path;
+				}
+			} else if (len == 1) {
+				total_ie_len_byte = (totoal_ie_len / 2) - 2;
+				elen = pmlmepriv->vendor_ie[vendor_ie_num][len];
+				if (elen != total_ie_len_byte) {
+					RTW_INFO("[%s] Fail , Input IE length = \"%d\"(hex:%x) bytes , not match input total IE context length \"%d\" bytes\n", __func__ , elen , elen ,
+						 total_ie_len_byte);
+					goto _clear_path;
+				}
+			}
+			len++;
+		}
+		pmlmepriv->vendor_ielen[vendor_ie_num] = len;
+	} else
+		pmlmepriv->vendor_ielen[vendor_ie_num] = 0;
+
+
+
+	if (vendor_ie_mask & WIFI_BEACON_VENDOR_IE_BIT)
+		RTW_INFO("[%s] Beacon append vendor ie\n", __func__);
+	if (vendor_ie_mask & WIFI_PROBEREQ_VENDOR_IE_BIT)
+		RTW_INFO("[%s] Probe Req append vendor ie\n", __func__);
+	if (vendor_ie_mask & WIFI_PROBERESP_VENDOR_IE_BIT)
+		RTW_INFO("[%s] Probe Resp  append vendor ie\n", __func__);
+	if (vendor_ie_mask & WIFI_ASSOCREQ_VENDOR_IE_BIT)
+		RTW_INFO("[%s] Assoc Req append vendor ie\n", __func__);
+	if (vendor_ie_mask & WIFI_ASSOCRESP_VENDOR_IE_BIT)
+		RTW_INFO("[%s] Assoc Resp append vendor ie\n", __func__);
+
+	pmlmepriv->vendor_ie_mask[vendor_ie_num] = vendor_ie_mask;
+
+	return ret;
+
+_clear_path:
+	_rtw_memset(pmlmepriv->vendor_ie[vendor_ie_num] , 0 , sizeof(u32) * WLAN_MAX_VENDOR_IE_LEN);
+	pmlmepriv->vendor_ielen[vendor_ie_num] = 0;
+	pmlmepriv->vendor_ie_mask[vendor_ie_num] = 0;
+	return -EFAULT;
+}
+#endif
+
+static int rtw_mp_efuse_get(struct net_device *dev,
+			    struct iw_request_info *info,
+			    union iwreq_data *wdata, char *extra)
+{
+	PADAPTER padapter = rtw_netdev_priv(dev);
+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(padapter);
+
+	PEFUSE_HAL pEfuseHal;
+	struct iw_point *wrqu;
+
+	u8 ips_mode = IPS_NUM; /* init invalid value */
+	u8 lps_mode = PS_MODE_NUM; /* init invalid value */
+	struct pwrctrl_priv *pwrctrlpriv ;
+	u8 *data = NULL;
+	u8 *rawdata = NULL;
+	char *pch, *ptmp, *token, *tmp[3] = {0x00, 0x00, 0x00};
+	u16 i = 0, j = 0, mapLen = 0, addr = 0, cnts = 0;
+	u16 max_available_len = 0, raw_cursize = 0, raw_maxsize = 0;
+	u16 mask_len;
+	u8 mask_buf[64] = "";
+	int err;
+	char *pextra = NULL;
+#ifdef CONFIG_IOL
+	u8 org_fw_iol = padapter->registrypriv.fw_iol;/* 0:Disable, 1:enable, 2:by usb speed */
+#endif
+
+	wrqu = (struct iw_point *)wdata;
+	pwrctrlpriv = adapter_to_pwrctl(padapter);
+	pEfuseHal = &pHalData->EfuseHal;
+
+	err = 0;
+	data = rtw_zmalloc(EFUSE_BT_MAX_MAP_LEN);
+	if (data == NULL) {
+		err = -ENOMEM;
+		goto exit;
+	}
+	rawdata = rtw_zmalloc(EFUSE_BT_MAX_MAP_LEN);
+	if (rawdata == NULL) {
+		err = -ENOMEM;
+		goto exit;
+	}
+
+	if (copy_from_user(extra, wrqu->pointer, wrqu->length)) {
+		err = -EFAULT;
+		goto exit;
+	}
+
+	*(extra + wrqu->length) = '\0';
+
+#ifdef CONFIG_LPS
+	lps_mode = pwrctrlpriv->power_mgnt;/* keep org value */
+	rtw_pm_set_lps(padapter, PS_MODE_ACTIVE);
+#endif
+
+#ifdef CONFIG_IPS
+	ips_mode = pwrctrlpriv->ips_mode;/* keep org value */
+	rtw_pm_set_ips(padapter, IPS_NONE);
+#endif
+
+	pch = extra;
+	RTW_INFO("%s: in=%s\n", __FUNCTION__, extra);
+
+	i = 0;
+	/* mac 16 "00e04c871200" rmap,00,2 */
+	while ((token = strsep(&pch, ",")) != NULL) {
+		if (i > 2)
+			break;
+		tmp[i] = token;
+		i++;
+	}
+#ifdef CONFIG_IOL
+	padapter->registrypriv.fw_iol = 0;/* 0:Disable, 1:enable, 2:by usb speed */
+#endif
+
+	if (strcmp(tmp[0], "status") == 0) {
+		sprintf(extra, "Load File efuse=%s,Load File MAC=%s"
+			, pHalData->efuse_file_status == EFUSE_FILE_FAILED ? "FAIL" : "OK"
+			, pHalData->macaddr_file_status == MACADDR_FILE_FAILED ? "FAIL" : "OK"
+		       );
+		goto exit;
+	} else if (strcmp(tmp[0], "drvmap") == 0) {
+		static u8 drvmaporder = 0;
+		u8 *efuse;
+		u32 shift, cnt;
+		u32 blksz = 0x200; /* The size of one time show, default 512 */
+		EFUSE_GetEfuseDefinition(padapter, EFUSE_WIFI, TYPE_EFUSE_MAP_LEN, (void *)&mapLen, _FALSE);
+
+		efuse = pHalData->efuse_eeprom_data;
+
+		shift = blksz * drvmaporder;
+		efuse += shift;
+		cnt = mapLen - shift;
+
+		if (cnt > blksz) {
+			cnt = blksz;
+			drvmaporder++;
+		} else
+			drvmaporder = 0;
+
+		sprintf(extra, "\n");
+		for (i = 0; i < cnt; i += 16) {
+			pextra = extra + strlen(extra);
+			pextra += sprintf(pextra, "0x%02x\t", shift + i);
+			for (j = 0; j < 8; j++)
+				pextra += sprintf(pextra, "%02X ", efuse[i + j]);
+			pextra += sprintf(pextra, "\t");
+			for (; j < 16; j++)
+				pextra += sprintf(pextra, "%02X ", efuse[i + j]);
+			pextra += sprintf(pextra, "\n");
+		}
+		if ((shift + cnt) < mapLen)
+			pextra += sprintf(pextra, "\t...more (left:%d/%d)\n", mapLen-(shift + cnt), mapLen);
+
+	} else if (strcmp(tmp[0], "realmap") == 0) {
+		static u8 order = 0;
+		u8 *efuse;
+		u32 shift, cnt;
+		u32 blksz = 0x200; /* The size of one time show, default 512 */
+
+		EFUSE_GetEfuseDefinition(padapter, EFUSE_WIFI, TYPE_EFUSE_MAP_LEN , (void *)&mapLen, _FALSE);
+		efuse = pEfuseHal->fakeEfuseInitMap;
+		if (rtw_efuse_mask_map_read(padapter, 0, mapLen, efuse) == _FAIL) {
+			RTW_INFO("%s: read realmap Fail!!\n", __FUNCTION__);
+			err = -EFAULT;
+			goto exit;
+		}
+
+#if 0
+		RTW_INFO("OFFSET\tVALUE(hex)\n");
+		for (i = 0; i < mapLen; i += 16) {
+			RTW_INFO("0x%02x\t", i);
+			for (j = 0; j < 8; j++)
+				RTW_INFO("%02X ", efuse[i + j]);
+			RTW_INFO("\t");
+			for (; j < 16; j++)
+				RTW_INFO("%02X ", efuse[i + j]);
+			RTW_INFO("\n");
+		}
+		RTW_INFO("\n");
+#endif
+
+		shift = blksz * order;
+		efuse += shift;
+		cnt = mapLen - shift;
+		if (cnt > blksz) {
+			cnt = blksz;
+			order++;
+		} else
+			order = 0;
+
+		sprintf(extra, "\n");
+		for (i = 0; i < cnt; i += 16) {
+			pextra = extra + strlen(extra);
+			pextra += sprintf(pextra, "0x%02x\t", shift + i);
+			for (j = 0; j < 8; j++)
+				pextra += sprintf(pextra, "%02X ", efuse[i + j]);
+			pextra += sprintf(pextra, "\t");
+			for (; j < 16; j++)
+				pextra += sprintf(pextra, "%02X ", efuse[i + j]);
+			pextra += sprintf(pextra, "\n");
+		}
+		if ((shift + cnt) < mapLen)
+			pextra += sprintf(pextra, "\t...more (left:%d/%d)\n", mapLen-(shift + cnt), mapLen);
+	} else if (strcmp(tmp[0], "rmap") == 0) {
+		if ((tmp[1] == NULL) || (tmp[2] == NULL)) {
+			RTW_INFO("%s: rmap Fail!! Parameters error!\n", __FUNCTION__);
+			err = -EINVAL;
+			goto exit;
+		}
+
+		/* rmap addr cnts */
+		addr = simple_strtoul(tmp[1], &ptmp, 16);
+		RTW_INFO("%s: addr=%x\n", __FUNCTION__, addr);
+
+		cnts = simple_strtoul(tmp[2], &ptmp, 10);
+		if (cnts == 0) {
+			RTW_INFO("%s: rmap Fail!! cnts error!\n", __FUNCTION__);
+			err = -EINVAL;
+			goto exit;
+		}
+		RTW_INFO("%s: cnts=%d\n", __FUNCTION__, cnts);
+
+		EFUSE_GetEfuseDefinition(padapter, EFUSE_WIFI, TYPE_EFUSE_MAP_LEN , (PVOID)&max_available_len, _FALSE);
+		if ((addr + cnts) > max_available_len) {
+			RTW_INFO("%s: addr(0x%X)+cnts(%d) parameter error!\n", __FUNCTION__, addr, cnts);
+			err = -EINVAL;
+			goto exit;
+		}
+
+		if (rtw_efuse_mask_map_read(padapter, addr, cnts, data) == _FAIL) {
+			RTW_INFO("%s: rtw_efuse_mask_map_read error!\n", __func__);
+			err = -EFAULT;
+			goto exit;
+		}
+
+		/*		RTW_INFO("%s: data={", __FUNCTION__); */
+		*extra = 0;
+		pextra = extra;
+		for (i = 0; i < cnts; i++) {
+			/*			RTW_INFO("0x%02x ", data[i]); */
+			pextra += sprintf(pextra, "0x%02X ", data[i]);
+		}
+		/*		RTW_INFO("}\n"); */
+	} else if (strcmp(tmp[0], "realraw") == 0) {
+		static u8 raw_order = 0;
+		u32 shift, cnt;
+		u32 blksz = 0x200; /* The size of one time show, default 512 */
+
+		addr = 0;
+		EFUSE_GetEfuseDefinition(padapter, EFUSE_WIFI, TYPE_EFUSE_REAL_CONTENT_LEN , (PVOID)&mapLen, _FALSE);
+		RTW_INFO("Real content len = %d\n",mapLen );
+
+		if (rtw_efuse_access(padapter, _FALSE, addr, mapLen, rawdata) == _FAIL) {
+			RTW_INFO("%s: rtw_efuse_access Fail!!\n", __func__);
+			err = -EFAULT;
+			goto exit;
+		}
+
+		_rtw_memset(extra, '\0', strlen(extra));
+
+		shift = blksz * raw_order;
+		rawdata += shift;
+		cnt = mapLen - shift;
+		if (cnt > blksz) {
+			cnt = blksz;
+			raw_order++;
+		} else
+			raw_order = 0;
+
+		sprintf(extra, "\n");
+		for (i = 0; i < cnt; i += 16) {
+			pextra = extra + strlen(extra);
+			pextra += sprintf(pextra, "0x%02x\t", shift + i);
+			for (j = 0; j < 8; j++)
+				pextra += sprintf(pextra, "%02X ", rawdata[i + j]);
+			pextra += sprintf(pextra, "\t");
+			for (; j < 16; j++)
+				pextra += sprintf(pextra, "%02X ", rawdata[i + j]);
+			pextra += sprintf(pextra, "\n");
+		}
+		if ((shift + cnt) < mapLen)
+			pextra += sprintf(pextra, "\t...more (left:%d/%d)\n", mapLen-(shift + cnt), mapLen);
+
+	} else if (strcmp(tmp[0], "btrealraw") == 0) {
+		static u8 bt_raw_order = 0;
+		u32 shift, cnt;
+		u32 blksz = 0x200; /* The size of one time show, default 512 */
+
+		addr = 0;
+		EFUSE_GetEfuseDefinition(padapter, EFUSE_BT, TYPE_EFUSE_REAL_CONTENT_LEN, (PVOID)&mapLen, _FALSE);
+		RTW_INFO("Real content len = %d\n", mapLen);
+#ifdef RTW_HALMAC
+		if (rtw_efuse_bt_access(padapter, _FALSE, 0, mapLen, rawdata) == _FAIL) {
+			RTW_INFO("%s: rtw_efuse_access Fail!!\n", __func__);
+			err = -EFAULT;
+			goto exit;
+		}
+#else
+		rtw_write8(padapter, 0x35, 0x1);
+
+		if (rtw_efuse_access(padapter, _FALSE, addr, mapLen, rawdata) == _FAIL) {
+			RTW_INFO("%s: rtw_efuse_access Fail!!\n", __func__);
+			err = -EFAULT;
+			goto exit;
+		}
+#endif
+		_rtw_memset(extra, '\0', strlen(extra));
+
+		shift = blksz * bt_raw_order;
+		rawdata += shift;
+		cnt = mapLen - shift;
+		if (cnt > blksz) {
+			cnt = blksz;
+			bt_raw_order++;
+		} else
+			bt_raw_order = 0;
+
+		sprintf(extra, "\n");
+		for (i = 0; i < cnt; i += 16) {
+			pextra = extra + strlen(extra);
+			pextra += sprintf(pextra, "0x%02x\t", shift + i);
+			for (j = 0; j < 8; j++)
+				pextra += sprintf(pextra, "%02X ", rawdata[i + j]);
+			pextra += sprintf(pextra, "\t");
+			for (; j < 16; j++)
+				pextra += sprintf(pextra, "%02X ", rawdata[i + j]);
+			pextra += sprintf(pextra, "\n");
+		}
+		if ((shift + cnt) < mapLen)
+			pextra += sprintf(pextra, "\t...more (left:%d/%d)\n", mapLen-(shift + cnt), mapLen);
+
+	} else if (strcmp(tmp[0], "mac") == 0) {
+		if (hal_efuse_macaddr_offset(padapter) == -1) {
+			err = -EFAULT;
+			goto exit;
+		}
+
+		addr = hal_efuse_macaddr_offset(padapter);
+		cnts = 6;
+
+		EFUSE_GetEfuseDefinition(padapter, EFUSE_WIFI, TYPE_EFUSE_MAP_LEN, (PVOID)&max_available_len, _FALSE);
+		if ((addr + cnts) > max_available_len) {
+			RTW_INFO("%s: addr(0x%02x)+cnts(%d) parameter error!\n", __FUNCTION__, addr, cnts);
+			err = -EFAULT;
+			goto exit;
+		}
+
+		if (rtw_efuse_mask_map_read(padapter, addr, cnts, data) == _FAIL) {
+			RTW_INFO("%s: rtw_efuse_mask_map_read error!\n", __func__);
+			err = -EFAULT;
+			goto exit;
+		}
+
+		/*		RTW_INFO("%s: MAC address={", __FUNCTION__); */
+		*extra = 0;
+		pextra = extra;
+		for (i = 0; i < cnts; i++) {
+			/*			RTW_INFO("%02X", data[i]); */
+			pextra += sprintf(pextra, "%02X", data[i]);
+			if (i != (cnts - 1)) {
+				/*				RTW_INFO(":"); */
+				pextra += sprintf(pextra, ":");
+			}
+		}
+		/*		RTW_INFO("}\n"); */
+	} else if (strcmp(tmp[0], "vidpid") == 0) {
+#ifdef CONFIG_RTL8188E
+#ifdef CONFIG_USB_HCI
+		addr = EEPROM_VID_88EU;
+#endif
+#ifdef CONFIG_PCI_HCI
+		addr = EEPROM_VID_88EE;
+#endif
+#endif /* CONFIG_RTL8188E */
+
+#ifdef CONFIG_RTL8192E
+#ifdef CONFIG_USB_HCI
+		addr = EEPROM_VID_8192EU;
+#endif
+#ifdef CONFIG_PCI_HCI
+		addr = EEPROM_VID_8192EE;
+#endif
+#endif /* CONFIG_RTL8192E */
+#ifdef CONFIG_RTL8723B
+		addr = EEPROM_VID_8723BU;
+#endif /* CONFIG_RTL8192E */
+
+#ifdef CONFIG_RTL8188F
+		addr = EEPROM_VID_8188FU;
+#endif /* CONFIG_RTL8188F */
+
+#ifdef CONFIG_RTL8188GTV
+		addr = EEPROM_VID_8188GTVU;
+#endif
+
+#ifdef CONFIG_RTL8703B
+#ifdef CONFIG_USB_HCI
+		addr = EEPROM_VID_8703BU;
+#endif
+#endif /* CONFIG_RTL8703B */
+
+#ifdef CONFIG_RTL8723D
+#ifdef CONFIG_USB_HCI
+		addr = EEPROM_VID_8723DU;
+#endif /* CONFIG_USB_HCI */
+#endif /* CONFIG_RTL8723D */
+
+		cnts = 4;
+
+		EFUSE_GetEfuseDefinition(padapter, EFUSE_WIFI, TYPE_EFUSE_MAP_LEN, (PVOID)&max_available_len, _FALSE);
+		if ((addr + cnts) > max_available_len) {
+			RTW_INFO("%s: addr(0x%02x)+cnts(%d) parameter error!\n", __FUNCTION__, addr, cnts);
+			err = -EFAULT;
+			goto exit;
+		}
+		if (rtw_efuse_mask_map_read(padapter, addr, cnts, data) == _FAIL) {
+			RTW_INFO("%s: rtw_efuse_access error!!\n", __FUNCTION__);
+			err = -EFAULT;
+			goto exit;
+		}
+
+		/*		RTW_INFO("%s: {VID,PID}={", __FUNCTION__); */
+		*extra = 0;
+		pextra = extra;
+		for (i = 0; i < cnts; i++) {
+			/*			RTW_INFO("0x%02x", data[i]); */
+			pextra += sprintf(pextra, "0x%02X", data[i]);
+			if (i != (cnts - 1)) {
+				/*				RTW_INFO(","); */
+				pextra += sprintf(pextra, ",");
+			}
+		}
+		/*		RTW_INFO("}\n"); */
+	} else if (strcmp(tmp[0], "ableraw") == 0) {
+#ifdef RTW_HALMAC
+		raw_maxsize = efuse_GetavailableSize(padapter);
+#else
+		efuse_GetCurrentSize(padapter, &raw_cursize);
+		raw_maxsize = efuse_GetMaxSize(padapter);
+#endif
+		sprintf(extra, "[available raw size]= %d bytes\n", raw_maxsize - raw_cursize);
+	} else if (strcmp(tmp[0], "btableraw") == 0) {
+		efuse_bt_GetCurrentSize(padapter, &raw_cursize);
+		raw_maxsize = efuse_bt_GetMaxSize(padapter);
+		sprintf(extra, "[available raw size]= %d bytes\n", raw_maxsize - raw_cursize);
+	} else if (strcmp(tmp[0], "btfmap") == 0) {
+
+		BTEfuse_PowerSwitch(padapter, 1, _TRUE);
+
+		mapLen = EFUSE_BT_MAX_MAP_LEN;
+		if (rtw_BT_efuse_map_read(padapter, 0, mapLen, pEfuseHal->BTEfuseInitMap) == _FAIL) {
+			RTW_INFO("%s: rtw_BT_efuse_map_read Fail!!\n", __FUNCTION__);
+			err = -EFAULT;
+			goto exit;
+		}
+
+		/*		RTW_INFO("OFFSET\tVALUE(hex)\n"); */
+		sprintf(extra, "\n");
+		for (i = 0; i < 512; i += 16) { /* set 512 because the iwpriv's extra size have limit 0x7FF */
+			/*			RTW_INFO("0x%03x\t", i); */
+			pextra = extra + strlen(extra);
+			pextra += sprintf(pextra, "0x%03x\t", i);
+			for (j = 0; j < 8; j++) {
+				/*				RTW_INFO("%02X ", pEfuseHal->BTEfuseInitMap[i+j]); */
+				pextra += sprintf(pextra, "%02X ", pEfuseHal->BTEfuseInitMap[i+j]);
+			}
+			/*			RTW_INFO("\t"); */
+			pextra += sprintf(pextra, "\t");
+			for (; j < 16; j++) {
+				/*				RTW_INFO("%02X ", pEfuseHal->BTEfuseInitMap[i+j]); */
+				pextra += sprintf(pextra, "%02X ", pEfuseHal->BTEfuseInitMap[i+j]);
+			}
+			/*			RTW_INFO("\n"); */
+			pextra += sprintf(pextra, "\n");
+		}
+		/*		RTW_INFO("\n"); */
+	} else if (strcmp(tmp[0], "btbmap") == 0) {
+		BTEfuse_PowerSwitch(padapter, 1, _TRUE);
+
+		mapLen = EFUSE_BT_MAX_MAP_LEN;
+		if (rtw_BT_efuse_map_read(padapter, 0, mapLen, pEfuseHal->BTEfuseInitMap) == _FAIL) {
+			RTW_INFO("%s: rtw_BT_efuse_map_read Fail!!\n", __FUNCTION__);
+			err = -EFAULT;
+			goto exit;
+		}
+
+		/*		RTW_INFO("OFFSET\tVALUE(hex)\n"); */
+		sprintf(extra, "\n");
+		for (i = 512; i < 1024 ; i += 16) {
+			/*			RTW_INFO("0x%03x\t", i); */
+			pextra = extra + strlen(extra);
+			pextra += sprintf(pextra, "0x%03x\t", i);
+			for (j = 0; j < 8; j++) {
+				/*				RTW_INFO("%02X ", data[i+j]); */
+				pextra += sprintf(pextra, "%02X ", pEfuseHal->BTEfuseInitMap[i+j]);
+			}
+			/*			RTW_INFO("\t"); */
+			pextra += sprintf(pextra, "\t");
+			for (; j < 16; j++) {
+				/*				RTW_INFO("%02X ", data[i+j]); */
+				pextra += sprintf(pextra, "%02X ", pEfuseHal->BTEfuseInitMap[i+j]);
+			}
+			/*			RTW_INFO("\n"); */
+			pextra += sprintf(pextra, "\n");
+		}
+		/*		RTW_INFO("\n"); */
+	} else if (strcmp(tmp[0], "btrmap") == 0) {
+		u8 BTStatus;
+
+		rtw_write8(padapter, 0xa3, 0x05); /* For 8723AB ,8821S ? */
+		BTStatus = rtw_read8(padapter, 0xa0);
+
+		RTW_INFO("%s: Check 0xa0 BT Status =0x%x\n", __FUNCTION__, BTStatus);
+		if (BTStatus != 0x04) {
+			sprintf(extra, "BT Status not Active ,can't to read BT eFuse\n");
+			goto exit;
+		}
+
+		if ((tmp[1] == NULL) || (tmp[2] == NULL)) {
+			err = -EINVAL;
+			goto exit;
+		}
+
+		BTEfuse_PowerSwitch(padapter, 1, _TRUE);
+
+		/* rmap addr cnts */
+		addr = simple_strtoul(tmp[1], &ptmp, 16);
+		RTW_INFO("%s: addr=0x%X\n", __FUNCTION__, addr);
+
+		cnts = simple_strtoul(tmp[2], &ptmp, 10);
+		if (cnts == 0) {
+			RTW_INFO("%s: btrmap Fail!! cnts error!\n", __FUNCTION__);
+			err = -EINVAL;
+			goto exit;
+		}
+		RTW_INFO("%s: cnts=%d\n", __FUNCTION__, cnts);
+#ifndef RTW_HALMAC
+		EFUSE_GetEfuseDefinition(padapter, EFUSE_BT, TYPE_EFUSE_MAP_LEN, (PVOID)&max_available_len, _FALSE);
+		if ((addr + cnts) > max_available_len) {
+			RTW_INFO("%s: addr(0x%X)+cnts(%d) parameter error!\n", __FUNCTION__, addr, cnts);
+			err = -EFAULT;
+			goto exit;
+		}
+#endif
+		if (rtw_BT_efuse_map_read(padapter, addr, cnts, data) == _FAIL) {
+			RTW_INFO("%s: rtw_BT_efuse_map_read error!!\n", __FUNCTION__);
+			err = -EFAULT;
+			goto exit;
+		}
+
+		*extra = 0;
+		pextra = extra;
+		/*		RTW_INFO("%s: bt efuse data={", __FUNCTION__); */
+		for (i = 0; i < cnts; i++) {
+			/*			RTW_INFO("0x%02x ", data[i]); */
+			pextra += sprintf(pextra, " 0x%02X ", data[i]);
+		}
+		/*		RTW_INFO("}\n"); */
+		RTW_INFO(FUNC_ADPT_FMT ": BT MAC=[%s]\n", FUNC_ADPT_ARG(padapter), extra);
+	} else if (strcmp(tmp[0], "btffake") == 0) {
+		/*		RTW_INFO("OFFSET\tVALUE(hex)\n"); */
+		sprintf(extra, "\n");
+		for (i = 0; i < 512; i += 16) {
+			/*			RTW_INFO("0x%03x\t", i); */
+			pextra = extra + strlen(extra);
+			pextra += sprintf(pextra, "0x%03x\t", i);
+			for (j = 0; j < 8; j++) {
+				/*				RTW_INFO("%02X ", pEfuseHal->fakeBTEfuseModifiedMap[i+j]); */
+				pextra += sprintf(pextra, "%02X ", pEfuseHal->fakeBTEfuseModifiedMap[i+j]);
+			}
+			/*			RTW_INFO("\t"); */
+			pextra += sprintf(pextra, "\t");
+			for (; j < 16; j++) {
+				/*				RTW_INFO("%02X ", pEfuseHal->fakeBTEfuseModifiedMap[i+j]); */
+				pextra += sprintf(pextra, "%02X ", pEfuseHal->fakeBTEfuseModifiedMap[i+j]);
+			}
+			/*			RTW_INFO("\n"); */
+			pextra += sprintf(pextra, "\n");
+		}
+		/*		RTW_INFO("\n"); */
+	} else if (strcmp(tmp[0], "btbfake") == 0) {
+		/*		RTW_INFO("OFFSET\tVALUE(hex)\n"); */
+		sprintf(extra, "\n");
+		for (i = 512; i < 1024; i += 16) {
+			/*			RTW_INFO("0x%03x\t", i); */
+			pextra = extra + strlen(extra);
+			pextra += sprintf(pextra, "0x%03x\t", i);
+			for (j = 0; j < 8; j++) {
+				/*				RTW_INFO("%02X ", pEfuseHal->fakeBTEfuseModifiedMap[i+j]); */
+				pextra += sprintf(pextra, "%02X ", pEfuseHal->fakeBTEfuseModifiedMap[i+j]);
+			}
+			/*			RTW_INFO("\t"); */
+			pextra += sprintf(pextra, "\t");
+			for (; j < 16; j++) {
+				/*				RTW_INFO("%02X ", pEfuseHal->fakeBTEfuseModifiedMap[i+j]); */
+				pextra += sprintf(pextra, "%02X ", pEfuseHal->fakeBTEfuseModifiedMap[i+j]);
+			}
+			/*			RTW_INFO("\n"); */
+			pextra += sprintf(pextra, "\n");
+		}
+		/*		RTW_INFO("\n"); */
+	} else if (strcmp(tmp[0], "wlrfkmap") == 0) {
+		static u8 fk_order = 0;
+		u8 *efuse;
+		u32 shift, cnt;
+		u32 blksz = 0x200; /* The size of one time show, default 512 */
+
+		EFUSE_GetEfuseDefinition(padapter, EFUSE_WIFI, TYPE_EFUSE_MAP_LEN , (void *)&mapLen, _FALSE);
+		efuse = pEfuseHal->fakeEfuseModifiedMap;
+
+		shift = blksz * fk_order;
+		efuse += shift;
+		cnt = mapLen - shift;
+		if (cnt > blksz) {
+			cnt = blksz;
+			fk_order++;
+		} else
+			fk_order = 0;
+
+		sprintf(extra, "\n");
+		for (i = 0; i < cnt; i += 16) {
+			pextra = extra + strlen(extra);
+			pextra += sprintf(pextra, "0x%02x\t", shift + i);
+			for (j = 0; j < 8; j++)
+				pextra += sprintf(pextra, "%02X ", efuse[i + j]);
+			pextra += sprintf(pextra, "\t");
+			for (; j < 16; j++)
+				pextra += sprintf(pextra, "%02X ", efuse[i + j]);
+			pextra += sprintf(pextra, "\n");
+		}
+		if ((shift + cnt) < mapLen)
+			pextra += sprintf(pextra, "\t...more\n");
+
+	} else if (strcmp(tmp[0], "wlrfkrmap") == 0) {
+		if ((tmp[1] == NULL) || (tmp[2] == NULL)) {
+			RTW_INFO("%s: rmap Fail!! Parameters error!\n", __FUNCTION__);
+			err = -EINVAL;
+			goto exit;
+		}
+		/* rmap addr cnts */
+		addr = simple_strtoul(tmp[1], &ptmp, 16);
+		RTW_INFO("%s: addr=%x\n", __FUNCTION__, addr);
+
+		cnts = simple_strtoul(tmp[2], &ptmp, 10);
+		if (cnts == 0) {
+			RTW_INFO("%s: rmap Fail!! cnts error!\n", __FUNCTION__);
+			err = -EINVAL;
+			goto exit;
+		}
+		RTW_INFO("%s: cnts=%d\n", __FUNCTION__, cnts);
+
+		/*		RTW_INFO("%s: data={", __FUNCTION__); */
+		*extra = 0;
+		pextra = extra;
+		for (i = 0; i < cnts; i++) {
+			RTW_INFO("wlrfkrmap = 0x%02x\n", pEfuseHal->fakeEfuseModifiedMap[addr + i]);
+			pextra += sprintf(pextra, "0x%02X ", pEfuseHal->fakeEfuseModifiedMap[addr+i]);
+		}
+	} else if (strcmp(tmp[0], "btrfkrmap") == 0) {
+		if ((tmp[1] == NULL) || (tmp[2] == NULL)) {
+			RTW_INFO("%s: rmap Fail!! Parameters error!\n", __FUNCTION__);
+			err = -EINVAL;
+			goto exit;
+		}
+		/* rmap addr cnts */
+		addr = simple_strtoul(tmp[1], &ptmp, 16);
+		RTW_INFO("%s: addr=%x\n", __FUNCTION__, addr);
+
+		cnts = simple_strtoul(tmp[2], &ptmp, 10);
+		if (cnts == 0) {
+			RTW_INFO("%s: rmap Fail!! cnts error!\n", __FUNCTION__);
+			err = -EINVAL;
+			goto exit;
+		}
+		RTW_INFO("%s: cnts=%d\n", __FUNCTION__, cnts);
+
+		/*		RTW_INFO("%s: data={", __FUNCTION__); */
+		*extra = 0;
+		pextra = extra;
+		for (i = 0; i < cnts; i++) {
+			RTW_INFO("wlrfkrmap = 0x%02x\n", pEfuseHal->fakeBTEfuseModifiedMap[addr + i]);
+			pextra += sprintf(pextra, "0x%02X ", pEfuseHal->fakeBTEfuseModifiedMap[addr+i]);
+		}
+	} else if (strcmp(tmp[0], "mask") == 0) {
+		*extra = 0;
+		mask_len = sizeof(u8) * rtw_get_efuse_mask_arraylen(padapter);
+		rtw_efuse_mask_array(padapter, mask_buf);
+
+		if (padapter->registrypriv.bFileMaskEfuse == _TRUE)
+			_rtw_memcpy(mask_buf, maskfileBuffer, mask_len);
+
+		sprintf(extra, "\n");
+		pextra = extra + strlen(extra);
+		for (i = 0; i < mask_len; i++)
+			pextra += sprintf(pextra, "0x%02X\n", mask_buf[i]);
+
+	} else
+		sprintf(extra, "Command not found!");
+
+exit:
+	if (data)
+		rtw_mfree(data, EFUSE_BT_MAX_MAP_LEN);
+	if (rawdata)
+		rtw_mfree(rawdata, EFUSE_BT_MAX_MAP_LEN);
+	if (!err)
+		wrqu->length = strlen(extra);
+
+	if (padapter->registrypriv.mp_mode == 0) {
+#ifdef CONFIG_IPS
+		rtw_pm_set_ips(padapter, ips_mode);
+#endif /* CONFIG_IPS */
+
+#ifdef CONFIG_LPS
+		rtw_pm_set_lps(padapter, lps_mode);
+#endif /* CONFIG_LPS */
+	}
+
+#ifdef CONFIG_IOL
+	padapter->registrypriv.fw_iol = org_fw_iol;/* 0:Disable, 1:enable, 2:by usb speed */
+#endif
+	return err;
+}
+
+
+#ifdef CONFIG_MP_INCLUDED
+static int rtw_mp_efuse_set(struct net_device *dev,
+			    struct iw_request_info *info,
+			    union iwreq_data *wdata, char *extra)
+{
+	struct iw_point *wrqu;
+	PADAPTER padapter;
+	struct pwrctrl_priv *pwrctrlpriv ;
+	PHAL_DATA_TYPE pHalData;
+	PEFUSE_HAL pEfuseHal;
+	struct hal_ops *pHalFunc;
+	struct mp_priv *pmp_priv;
+
+	u8 ips_mode = IPS_NUM; /* init invalid value */
+	u8 lps_mode = PS_MODE_NUM; /* init invalid value */
+	u32 i = 0, j = 0, jj, kk;
+	u8 *setdata = NULL;
+	u8 *ShadowMapBT = NULL;
+	u8 *ShadowMapWiFi = NULL;
+	u8 *setrawdata = NULL;
+	char *pch, *ptmp, *token, *tmp[3] = {0x00, 0x00, 0x00};
+	u16 addr = 0xFF, cnts = 0, BTStatus = 0 , max_available_len = 0;
+	u16 wifimaplen;
+	int err;
+	boolean bcmpchk = _TRUE;
+
+
+	wrqu = (struct iw_point *)wdata;
+	padapter = rtw_netdev_priv(dev);
+	pwrctrlpriv = adapter_to_pwrctl(padapter);
+	pHalData = GET_HAL_DATA(padapter);
+	pEfuseHal = &pHalData->EfuseHal;
+	pHalFunc = &padapter->hal_func;
+	pmp_priv = &padapter->mppriv;
+
+	err = 0;
+
+	if (copy_from_user(extra, wrqu->pointer, wrqu->length))
+		return -EFAULT;
+
+	*(extra + wrqu->length) = '\0';
+
+	EFUSE_GetEfuseDefinition(padapter, EFUSE_WIFI, TYPE_EFUSE_MAP_LEN , (void *)&wifimaplen, _FALSE);
+
+	setdata = rtw_zmalloc(1024);
+	if (setdata == NULL) {
+		err = -ENOMEM;
+		goto exit;
+	}
+	ShadowMapBT = rtw_malloc(EFUSE_BT_MAX_MAP_LEN);
+	if (ShadowMapBT == NULL) {
+		err = -ENOMEM;
+		goto exit;
+	}
+	ShadowMapWiFi = rtw_malloc(wifimaplen);
+	if (ShadowMapWiFi == NULL) {
+		err = -ENOMEM;
+		goto exit;
+	}
+	setrawdata = rtw_malloc(EFUSE_MAX_SIZE);
+	if (setrawdata == NULL) {
+		err = -ENOMEM;
+		goto exit;
+	}
+
+#ifdef CONFIG_LPS
+	lps_mode = pwrctrlpriv->power_mgnt;/* keep org value */
+	rtw_pm_set_lps(padapter, PS_MODE_ACTIVE);
+#endif
+
+#ifdef CONFIG_IPS
+	ips_mode = pwrctrlpriv->ips_mode;/* keep org value */
+	rtw_pm_set_ips(padapter, IPS_NONE);
+#endif
+
+	pch = extra;
+	RTW_INFO("%s: in=%s\n", __FUNCTION__, extra);
+
+	i = 0;
+	while ((token = strsep(&pch, ",")) != NULL) {
+		if (i > 2)
+			break;
+		tmp[i] = token;
+		i++;
+	}
+
+	/* tmp[0],[1],[2] */
+	/* wmap,addr,00e04c871200 */
+	if (strcmp(tmp[0], "wmap") == 0) {
+		if ((tmp[1] == NULL) || (tmp[2] == NULL)) {
+			err = -EINVAL;
+			goto exit;
+		}
+
+#ifndef RTW_HALMAC
+		/* unknown bug workaround, need to fix later */
+		addr = 0x1ff;
+		rtw_write8(padapter, EFUSE_CTRL + 1, (addr & 0xff));
+		rtw_msleep_os(10);
+		rtw_write8(padapter, EFUSE_CTRL + 2, ((addr >> 8) & 0x03));
+		rtw_msleep_os(10);
+		rtw_write8(padapter, EFUSE_CTRL + 3, 0x72);
+		rtw_msleep_os(10);
+		rtw_read8(padapter, EFUSE_CTRL);
+#endif /* RTW_HALMAC */
+
+		addr = simple_strtoul(tmp[1], &ptmp, 16);
+		addr &= 0xFFF;
+
+		cnts = strlen(tmp[2]);
+		if (cnts % 2) {
+			err = -EINVAL;
+			goto exit;
+		}
+		cnts /= 2;
+		if (cnts == 0) {
+			err = -EINVAL;
+			goto exit;
+		}
+
+		RTW_INFO("%s: addr=0x%X\n", __FUNCTION__, addr);
+		RTW_INFO("%s: cnts=%d\n", __FUNCTION__, cnts);
+		RTW_INFO("%s: map data=%s\n", __FUNCTION__, tmp[2]);
+
+		for (jj = 0, kk = 0; jj < cnts; jj++, kk += 2)
+			setdata[jj] = key_2char2num(tmp[2][kk], tmp[2][kk + 1]);
+
+		EFUSE_GetEfuseDefinition(padapter, EFUSE_WIFI, TYPE_EFUSE_MAP_LEN, (PVOID)&max_available_len, _FALSE);
+
+		if ((addr + cnts) > max_available_len) {
+			RTW_INFO("%s: addr(0x%X)+cnts(%d) parameter error!\n", __FUNCTION__, addr, cnts);
+			err = -EFAULT;
+			goto exit;
+		}
+
+		if (rtw_efuse_map_write(padapter, addr, cnts, setdata) == _FAIL) {
+			RTW_INFO("%s: rtw_efuse_map_write error!!\n", __FUNCTION__);
+			err = -EFAULT;
+			goto exit;
+		}
+		*extra = 0;
+		RTW_INFO("%s: after rtw_efuse_map_write to _rtw_memcmp\n", __func__);
+		if (rtw_efuse_mask_map_read(padapter, addr, cnts, ShadowMapWiFi) == _SUCCESS) {
+			if (_rtw_memcmp((void *)ShadowMapWiFi , (void *)setdata, cnts)) {
+				RTW_INFO("%s: WiFi write map afterf compare success\n", __FUNCTION__);
+				sprintf(extra, "WiFi write map compare OK\n");
+				err = 0;
+				goto exit;
+			} else {
+				sprintf(extra, "WiFi write map compare FAIL\n");
+				RTW_INFO("%s: WiFi write map compare Fail\n", __FUNCTION__);
+				err = 0;
+				goto exit;
+			}
+		}
+	} else if (strcmp(tmp[0], "wraw") == 0) {
+		if ((tmp[1] == NULL) || (tmp[2] == NULL)) {
+			err = -EINVAL;
+			goto exit;
+		}
+
+		addr = simple_strtoul(tmp[1], &ptmp, 16);
+		addr &= 0xFFF;
+
+		cnts = strlen(tmp[2]);
+		if (cnts % 2) {
+			err = -EINVAL;
+			goto exit;
+		}
+		cnts /= 2;
+		if (cnts == 0) {
+			err = -EINVAL;
+			goto exit;
+		}
+
+		RTW_INFO("%s: addr=0x%X\n", __FUNCTION__, addr);
+		RTW_INFO("%s: cnts=%d\n", __FUNCTION__, cnts);
+		RTW_INFO("%s: raw data=%s\n", __FUNCTION__, tmp[2]);
+
+		for (jj = 0, kk = 0; jj < cnts; jj++, kk += 2)
+			setrawdata[jj] = key_2char2num(tmp[2][kk], tmp[2][kk + 1]);
+
+		if (rtw_efuse_access(padapter, _TRUE, addr, cnts, setrawdata) == _FAIL) {
+			RTW_INFO("%s: rtw_efuse_access error!!\n", __FUNCTION__);
+			err = -EFAULT;
+			goto exit;
+		}
+	} else if (strcmp(tmp[0], "btwraw") == 0) {
+		if ((tmp[1] == NULL) || (tmp[2] == NULL)) {
+			err = -EINVAL;
+			goto exit;
+		}
+
+		addr = simple_strtoul(tmp[1], &ptmp, 16);
+		addr &= 0xFFF;
+
+		cnts = strlen(tmp[2]);
+		if (cnts % 2) {
+			err = -EINVAL;
+			goto exit;
+		}
+		cnts /= 2;
+		if (cnts == 0) {
+			err = -EINVAL;
+			goto exit;
+		}
+
+		RTW_INFO("%s: addr=0x%X\n", __FUNCTION__, addr);
+		RTW_INFO("%s: cnts=%d\n", __FUNCTION__, cnts);
+		RTW_INFO("%s: raw data=%s\n", __FUNCTION__, tmp[2]);
+
+		for (jj = 0, kk = 0; jj < cnts; jj++, kk += 2)
+			setrawdata[jj] = key_2char2num(tmp[2][kk], tmp[2][kk + 1]);
+#ifdef RTW_HALMAC
+		if (rtw_efuse_bt_access(padapter, _TRUE, addr, cnts, setrawdata) == _FAIL) {
+			RTW_INFO("%s: rtw_efuse_access error!!\n", __FUNCTION__);
+			err = -EFAULT;
+			goto exit;
+		}
+#else
+		rtw_write8(padapter, 0x35, 1); /* switch bank 1 (BT)*/
+		if (rtw_efuse_access(padapter, _TRUE, addr, cnts, setrawdata) == _FAIL) {
+			RTW_INFO("%s: rtw_efuse_access error!!\n", __FUNCTION__);
+			rtw_write8(padapter, 0x35, 0); /* switch bank 0 (WiFi)*/
+			err = -EFAULT;
+			goto exit;
+		}
+		rtw_write8(padapter, 0x35, 0); /* switch bank 0 (WiFi)*/
+#endif
+	} else if (strcmp(tmp[0], "mac") == 0) {
+		if (tmp[1] == NULL) {
+			err = -EINVAL;
+			goto exit;
+		}
+
+		/* mac,00e04c871200 */
+
+		if (hal_efuse_macaddr_offset(padapter) == -1) {
+			err = -EFAULT;
+			goto exit;
+		}
+
+		addr = hal_efuse_macaddr_offset(padapter);
+		cnts = strlen(tmp[1]);
+		if (cnts % 2) {
+			err = -EINVAL;
+			goto exit;
+		}
+		cnts /= 2;
+		if (cnts == 0) {
+			err = -EINVAL;
+			goto exit;
+		}
+		if (cnts > 6) {
+			RTW_INFO("%s: error data for mac addr=\"%s\"\n", __FUNCTION__, tmp[1]);
+			err = -EFAULT;
+			goto exit;
+		}
+
+		RTW_INFO("%s: addr=0x%X\n", __FUNCTION__, addr);
+		RTW_INFO("%s: cnts=%d\n", __FUNCTION__, cnts);
+		RTW_INFO("%s: MAC address=%s\n", __FUNCTION__, tmp[1]);
+
+		for (jj = 0, kk = 0; jj < cnts; jj++, kk += 2)
+			setdata[jj] = key_2char2num(tmp[1][kk], tmp[1][kk + 1]);
+
+		EFUSE_GetEfuseDefinition(padapter, EFUSE_WIFI, TYPE_EFUSE_MAP_LEN, (PVOID)&max_available_len, _FALSE);
+
+		if ((addr + cnts) > max_available_len) {
+			RTW_INFO("%s: addr(0x%X)+cnts(%d) parameter error!\n", __FUNCTION__, addr, cnts);
+			err = -EFAULT;
+			goto exit;
+		}
+
+		if (rtw_efuse_map_write(padapter, addr, cnts, setdata) == _FAIL) {
+			RTW_INFO("%s: rtw_efuse_map_write error!!\n", __FUNCTION__);
+			err = -EFAULT;
+			goto exit;
+		}
+	} else if (strcmp(tmp[0], "vidpid") == 0) {
+		if (tmp[1] == NULL) {
+			err = -EINVAL;
+			goto exit;
+		}
+
+		/* pidvid,da0b7881		 */
+#ifdef CONFIG_RTL8188E
+#ifdef CONFIG_USB_HCI
+		addr = EEPROM_VID_88EU;
+#endif
+#ifdef CONFIG_PCI_HCI
+		addr = EEPROM_VID_88EE;
+#endif
+#endif /* CONFIG_RTL8188E */
+
+#ifdef CONFIG_RTL8192E
+#ifdef CONFIG_USB_HCI
+		addr = EEPROM_VID_8192EU;
+#endif
+#ifdef CONFIG_PCI_HCI
+		addr = EEPROM_VID_8192EE;
+#endif
+#endif /* CONFIG_RTL8188E */
+
+#ifdef CONFIG_RTL8723B
+		addr = EEPROM_VID_8723BU;
+#endif
+
+#ifdef CONFIG_RTL8188F
+		addr = EEPROM_VID_8188FU;
+#endif
+
+#ifdef CONFIG_RTL8188GTV
+		addr = EEPROM_VID_8188GTVU;
+#endif
+
+#ifdef CONFIG_RTL8703B
+#ifdef CONFIG_USB_HCI
+		addr = EEPROM_VID_8703BU;
+#endif /* CONFIG_USB_HCI */
+#endif /* CONFIG_RTL8703B */
+
+#ifdef CONFIG_RTL8723D
+#ifdef CONFIG_USB_HCI
+		addr = EEPROM_VID_8723DU;
+#endif /* CONFIG_USB_HCI */
+#endif /* CONFIG_RTL8723D */
+
+		cnts = strlen(tmp[1]);
+		if (cnts % 2) {
+			err = -EINVAL;
+			goto exit;
+		}
+		cnts /= 2;
+		if (cnts == 0) {
+			err = -EINVAL;
+			goto exit;
+		}
+
+		RTW_INFO("%s: addr=0x%X\n", __FUNCTION__, addr);
+		RTW_INFO("%s: cnts=%d\n", __FUNCTION__, cnts);
+		RTW_INFO("%s: VID/PID=%s\n", __FUNCTION__, tmp[1]);
+
+		for (jj = 0, kk = 0; jj < cnts; jj++, kk += 2)
+			setdata[jj] = key_2char2num(tmp[1][kk], tmp[1][kk + 1]);
+
+		EFUSE_GetEfuseDefinition(padapter, EFUSE_WIFI, TYPE_EFUSE_MAP_LEN, (PVOID)&max_available_len, _FALSE);
+		if ((addr + cnts) > max_available_len) {
+			RTW_INFO("%s: addr(0x%X)+cnts(%d) parameter error!\n", __FUNCTION__, addr, cnts);
+			err = -EFAULT;
+			goto exit;
+		}
+
+		if (rtw_efuse_map_write(padapter, addr, cnts, setdata) == _FAIL) {
+			RTW_INFO("%s: rtw_efuse_map_write error!!\n", __FUNCTION__);
+			err = -EFAULT;
+			goto exit;
+		}
+	} else if (strcmp(tmp[0], "wldumpfake") == 0) {
+		if (wifimaplen > EFUSE_MAX_MAP_LEN)
+			cnts = EFUSE_MAX_MAP_LEN;
+		else
+			cnts = wifimaplen;
+		if (rtw_efuse_mask_map_read(padapter, 0, cnts, pEfuseHal->fakeEfuseModifiedMap) == _SUCCESS)
+			RTW_INFO("%s: WiFi hw efuse dump to Fake map success\n", __func__);
+		else {
+			RTW_INFO("%s: WiFi hw efuse dump to Fake map Fail\n", __func__);
+			err = -EFAULT;
+		}
+	} else if (strcmp(tmp[0], "btwmap") == 0) {
+		rtw_write8(padapter, 0xa3, 0x05); /* For 8723AB ,8821S ? */
+		BTStatus = rtw_read8(padapter, 0xa0);
+		RTW_INFO("%s: btwmap before read 0xa0 BT Status =0x%x\n", __FUNCTION__, BTStatus);
+		if (BTStatus != 0x04) {
+			sprintf(extra, "BT Status not Active ,can't do Write\n");
+			goto exit;
+		}
+
+		if ((tmp[1] == NULL) || (tmp[2] == NULL)) {
+			err = -EINVAL;
+			goto exit;
+		}
+
+#ifndef RTW_HALMAC
+		BTEfuse_PowerSwitch(padapter, 1, _TRUE);
+		addr = 0x1ff;
+		rtw_write8(padapter, EFUSE_CTRL + 1, (addr & 0xff));
+		rtw_msleep_os(10);
+		rtw_write8(padapter, EFUSE_CTRL + 2, ((addr >> 8) & 0x03));
+		rtw_msleep_os(10);
+		rtw_write8(padapter, EFUSE_CTRL + 3, 0x72);
+		rtw_msleep_os(10);
+		rtw_read8(padapter, EFUSE_CTRL);
+		BTEfuse_PowerSwitch(padapter, 1, _FALSE);
+#endif /* RTW_HALMAC */
+
+		addr = simple_strtoul(tmp[1], &ptmp, 16);
+		addr &= 0xFFF;
+
+		cnts = strlen(tmp[2]);
+		if (cnts % 2) {
+			err = -EINVAL;
+			goto exit;
+		}
+		cnts /= 2;
+		if (cnts == 0) {
+			err = -EINVAL;
+			goto exit;
+		}
+
+		RTW_INFO("%s: addr=0x%X\n", __FUNCTION__, addr);
+		RTW_INFO("%s: cnts=%d\n", __FUNCTION__, cnts);
+		RTW_INFO("%s: BT data=%s\n", __FUNCTION__, tmp[2]);
+
+		for (jj = 0, kk = 0; jj < cnts; jj++, kk += 2)
+			setdata[jj] = key_2char2num(tmp[2][kk], tmp[2][kk + 1]);
+#ifndef RTW_HALMAC
+		EFUSE_GetEfuseDefinition(padapter, EFUSE_BT, TYPE_EFUSE_MAP_LEN, (PVOID)&max_available_len, _FALSE);
+		if ((addr + cnts) > max_available_len) {
+			RTW_INFO("%s: addr(0x%X)+cnts(%d) parameter error!\n", __FUNCTION__, addr, cnts);
+			err = -EFAULT;
+			goto exit;
+		}
+#endif
+		if (rtw_BT_efuse_map_write(padapter, addr, cnts, setdata) == _FAIL) {
+			RTW_INFO("%s: rtw_BT_efuse_map_write error!!\n", __FUNCTION__);
+			err = -EFAULT;
+			goto exit;
+		}
+		*extra = 0;
+		RTW_INFO("%s: after rtw_BT_efuse_map_write to _rtw_memcmp\n", __FUNCTION__);
+		if ((rtw_BT_efuse_map_read(padapter, addr, cnts, ShadowMapBT) == _SUCCESS)) {
+			if (_rtw_memcmp((void *)ShadowMapBT , (void *)setdata, cnts)) {
+				RTW_INFO("%s: BT write map compare OK BTStatus=0x%x\n", __FUNCTION__, BTStatus);
+				sprintf(extra, "BT write map compare OK");
+				err = 0;
+				goto exit;
+			} else {
+				sprintf(extra, "BT write map compare FAIL");
+				RTW_INFO("%s: BT write map compare FAIL BTStatus=0x%x\n", __FUNCTION__, BTStatus);
+				err = 0;
+				goto exit;
+			}
+		}
+	} else if (strcmp(tmp[0], "btwfake") == 0) {
+		if ((tmp[1] == NULL) || (tmp[2] == NULL)) {
+			err = -EINVAL;
+			goto exit;
+		}
+
+		addr = simple_strtoul(tmp[1], &ptmp, 16);
+		addr &= 0xFFF;
+
+		cnts = strlen(tmp[2]);
+		if (cnts % 2) {
+			err = -EINVAL;
+			goto exit;
+		}
+		cnts /= 2;
+		if (cnts == 0) {
+			err = -EINVAL;
+			goto exit;
+		}
+
+		RTW_INFO("%s: addr=0x%X\n", __FUNCTION__, addr);
+		RTW_INFO("%s: cnts=%d\n", __FUNCTION__, cnts);
+		RTW_INFO("%s: BT tmp data=%s\n", __FUNCTION__, tmp[2]);
+
+		for (jj = 0, kk = 0; jj < cnts; jj++, kk += 2)
+			pEfuseHal->fakeBTEfuseModifiedMap[addr + jj] = key_2char2num(tmp[2][kk], tmp[2][kk + 1]);
+	} else if (strcmp(tmp[0], "btdumpfake") == 0) {
+		if (rtw_BT_efuse_map_read(padapter, 0, EFUSE_BT_MAX_MAP_LEN, pEfuseHal->fakeBTEfuseModifiedMap) == _SUCCESS)
+			RTW_INFO("%s: BT read all map success\n", __FUNCTION__);
+		else {
+			RTW_INFO("%s: BT read all map Fail!\n", __FUNCTION__);
+			err = -EFAULT;
+		}
+	} else if (strcmp(tmp[0], "btfk2map") == 0) {
+		rtw_write8(padapter, 0xa3, 0x05);
+		BTStatus = rtw_read8(padapter, 0xa0);
+		RTW_INFO("%s: btwmap before read 0xa0 BT Status =0x%x\n", __FUNCTION__, BTStatus);
+		if (BTStatus != 0x04) {
+			sprintf(extra, "BT Status not Active Write FAIL\n");
+			goto exit;
+		}
+#ifndef RTW_HALMAC
+		BTEfuse_PowerSwitch(padapter, 1, _TRUE);
+		addr = 0x1ff;
+		rtw_write8(padapter, EFUSE_CTRL + 1, (addr & 0xff));
+		rtw_msleep_os(10);
+		rtw_write8(padapter, EFUSE_CTRL + 2, ((addr >> 8) & 0x03));
+		rtw_msleep_os(10);
+		rtw_write8(padapter, EFUSE_CTRL + 3, 0x72);
+		rtw_msleep_os(10);
+		rtw_read8(padapter, EFUSE_CTRL);
+		BTEfuse_PowerSwitch(padapter, 1, _FALSE);
+#endif /* RTW_HALMAC */
+		_rtw_memcpy(pEfuseHal->BTEfuseModifiedMap, pEfuseHal->fakeBTEfuseModifiedMap, EFUSE_BT_MAX_MAP_LEN);
+
+		if (rtw_BT_efuse_map_write(padapter, 0x00, EFUSE_BT_MAX_MAP_LEN, pEfuseHal->fakeBTEfuseModifiedMap) == _FAIL) {
+			RTW_INFO("%s: rtw_BT_efuse_map_write error!\n", __FUNCTION__);
+			err = -EFAULT;
+			goto exit;
+		}
+
+		RTW_INFO("pEfuseHal->fakeBTEfuseModifiedMap OFFSET\tVALUE(hex)\n");
+		for (i = 0; i < EFUSE_BT_MAX_MAP_LEN; i += 16) {
+			printk("0x%02x\t", i);
+			for (j = 0; j < 8; j++)
+				printk("%02X ", pEfuseHal->fakeBTEfuseModifiedMap[i + j]);
+			printk("\t");
+
+			for (; j < 16; j++)
+				printk("%02X ", pEfuseHal->fakeBTEfuseModifiedMap[i + j]);
+			printk("\n");
+		}
+		printk("\n");
+#if 1
+		err = -EFAULT;
+		RTW_INFO("%s: rtw_BT_efuse_map_read _rtw_memcmp\n", __FUNCTION__);
+		if ((rtw_BT_efuse_map_read(padapter, 0x00, EFUSE_BT_MAX_MAP_LEN, pEfuseHal->fakeBTEfuseInitMap) == _SUCCESS)) {
+			if (_rtw_memcmp((void *)pEfuseHal->fakeBTEfuseModifiedMap, (void *)pEfuseHal->fakeBTEfuseInitMap, EFUSE_BT_MAX_MAP_LEN)) {
+				sprintf(extra, "BT write map compare OK");
+				RTW_INFO("%s: BT write map afterf compare success BTStatus=0x%x\n", __FUNCTION__, BTStatus);
+				err = 0;
+				goto exit;
+			} else {
+				sprintf(extra, "BT write map compare FAIL");
+				if (rtw_BT_efuse_map_write(padapter, 0x00, EFUSE_BT_MAX_MAP_LEN, pEfuseHal->fakeBTEfuseModifiedMap) == _FAIL)
+					RTW_INFO("%s: rtw_BT_efuse_map_write compare error,retry = %d!\n", __FUNCTION__, i);
+
+				if (rtw_BT_efuse_map_read(padapter, EFUSE_BT, EFUSE_BT_MAX_MAP_LEN, pEfuseHal->fakeBTEfuseInitMap) == _SUCCESS) {
+					RTW_INFO("pEfuseHal->fakeBTEfuseInitMap OFFSET\tVALUE(hex)\n");
+
+					for (i = 0; i < EFUSE_BT_MAX_MAP_LEN; i += 16) {
+						printk("0x%02x\t", i);
+						for (j = 0; j < 8; j++)
+							printk("%02X ", pEfuseHal->fakeBTEfuseInitMap[i + j]);
+						printk("\t");
+						for (; j < 16; j++)
+							printk("%02X ", pEfuseHal->fakeBTEfuseInitMap[i + j]);
+						printk("\n");
+					}
+					printk("\n");
+				}
+				RTW_INFO("%s: BT write map afterf compare not match to write efuse try write Map again , BTStatus=0x%x\n", __FUNCTION__, BTStatus);
+				goto exit;
+			}
+		}
+#endif
+
+	} else if (strcmp(tmp[0], "wlfk2map") == 0) {
+		*extra = 0;
+
+		if (padapter->registrypriv.bFileMaskEfuse != _TRUE && pmp_priv->bloadefusemap == _TRUE) {
+			RTW_INFO("%s: File eFuse mask file not to be loaded\n", __FUNCTION__);
+			sprintf(extra, "Not load eFuse mask file yet, Please use the efuse_mask CMD, now remove the interface !!!!\n");
+			rtw_set_surprise_removed(padapter);
+			err = 0;
+			goto exit;
+		}
+
+		if (wifimaplen > EFUSE_MAX_MAP_LEN)
+			cnts = EFUSE_MAX_MAP_LEN;
+		else
+			cnts = wifimaplen;
+		if (rtw_efuse_map_write(padapter, 0x00, cnts, pEfuseHal->fakeEfuseModifiedMap) == _FAIL) {
+			RTW_INFO("%s: rtw_efuse_map_write fakeEfuseModifiedMap error!\n", __FUNCTION__);
+			err = -EFAULT;
+			goto exit;
+		}
+
+		if (rtw_efuse_mask_map_read(padapter, 0x00, wifimaplen, ShadowMapWiFi) == _SUCCESS) {
+			addr = 0x00;
+			err = _TRUE;
+
+			for (i = 0; i < cnts; i++) {
+				if (padapter->registrypriv.boffefusemask == 0) {
+					if (padapter->registrypriv.bFileMaskEfuse == _TRUE) {
+						if (rtw_file_efuse_IsMasked(padapter, addr + i) == _TRUE)	/*use file efuse mask. */
+							bcmpchk = _FALSE;
+					} else {
+						if (efuse_IsMasked(padapter, addr + i) == _TRUE)
+							bcmpchk = _FALSE;
+					}
+				}
+
+				if (bcmpchk == _TRUE) {
+					RTW_INFO("compare readMapWiFi[0x%02x] = %x, ModifiedMap = %x\n", addr + i, ShadowMapWiFi[ addr + i], pEfuseHal->fakeEfuseModifiedMap[addr + i]);
+					if (_rtw_memcmp((void *) &ShadowMapWiFi[addr + i], (void *)&pEfuseHal->fakeEfuseModifiedMap[addr + i], 1) == _FALSE){
+						err = _FALSE;
+						break;
+					}
+				}
+				bcmpchk = _TRUE;
+			}
+		}
+
+		if (err) {
+			RTW_INFO("%s: WiFi write map afterf compare OK\n", __FUNCTION__);
+			sprintf(extra, "WiFi write map compare OK\n");
+			err = 0;
+			goto exit;
+		} else {
+			sprintf(extra, "WiFi write map compare FAIL\n");
+			RTW_INFO("%s: WiFi write map compare Fail\n", __FUNCTION__);
+			err = 0;
+			goto exit;
+		}
+	} else if (strcmp(tmp[0], "wlwfake") == 0) {
+		if ((tmp[1] == NULL) || (tmp[2] == NULL)) {
+			err = -EINVAL;
+			goto exit;
+		}
+
+		addr = simple_strtoul(tmp[1], &ptmp, 16);
+		addr &= 0xFFF;
+
+		cnts = strlen(tmp[2]);
+		if (cnts % 2) {
+			err = -EINVAL;
+			goto exit;
+		}
+		cnts /= 2;
+		if (cnts == 0) {
+			err = -EINVAL;
+			goto exit;
+		}
+
+		RTW_INFO("%s: addr=0x%X\n", __FUNCTION__, addr);
+		RTW_INFO("%s: cnts=%d\n", __FUNCTION__, cnts);
+		RTW_INFO("%s: map tmp data=%s\n", __FUNCTION__, tmp[2]);
+
+		for (jj = 0, kk = 0; jj < cnts; jj++, kk += 2)
+			pEfuseHal->fakeEfuseModifiedMap[addr + jj] = key_2char2num(tmp[2][kk], tmp[2][kk + 1]);
+		_rtw_memset(extra, '\0', strlen(extra));
+		sprintf(extra, "wlwfake OK\n");
+
+	}
+	else if (strcmp(tmp[0], "wfakemac") == 0) {
+		if (tmp[1] == NULL) {
+			err = -EINVAL;
+			goto exit;
+		}
+		/* wfakemac,00e04c871200 */
+		if (hal_efuse_macaddr_offset(padapter) == -1) {
+			err = -EFAULT;
+			goto exit;
+		}
+
+		addr = hal_efuse_macaddr_offset(padapter);
+		cnts = strlen(tmp[1]);
+		if (cnts % 2) {
+			err = -EINVAL;
+			goto exit;
+		}
+		cnts /= 2;
+		if (cnts == 0) {
+			err = -EINVAL;
+			goto exit;
+		}
+		if (cnts > 6) {
+			RTW_INFO("%s: error data for mac addr=\"%s\"\n", __FUNCTION__, tmp[1]);
+			err = -EFAULT;
+			goto exit;
+		}
+
+		RTW_INFO("%s: addr=0x%X\n", __FUNCTION__, addr);
+		RTW_INFO("%s: cnts=%d\n", __FUNCTION__, cnts);
+		RTW_INFO("%s: MAC address=%s\n", __FUNCTION__, tmp[1]);
+
+		for (jj = 0, kk = 0; jj < cnts; jj++, kk += 2)
+			pEfuseHal->fakeEfuseModifiedMap[addr + jj] = key_2char2num(tmp[1][kk], tmp[1][kk + 1]);
+
+		_rtw_memset(extra, '\0', strlen(extra));
+		sprintf(extra, "write mac addr to fake map OK\n");
+	} else if(strcmp(tmp[0], "update") == 0) {
+		RTW_INFO("To Use new eFuse map\n");
+		/*step read efuse/eeprom data and get mac_addr*/
+		rtw_hal_read_chip_info(padapter);
+		/* set mac addr*/
+		rtw_macaddr_cfg(adapter_mac_addr(padapter), get_hal_mac_addr(padapter));
+		_rtw_memcpy(padapter->pnetdev->dev_addr, get_hal_mac_addr(padapter), ETH_ALEN); /* set mac addr to net_device */
+
+#ifdef CONFIG_P2P
+		rtw_init_wifidirect_addrs(padapter, adapter_mac_addr(padapter), adapter_mac_addr(padapter));
+#endif
+#ifdef CONFIG_MI_WITH_MBSSID_CAM
+		rtw_hal_change_macaddr_mbid(padapter, adapter_mac_addr(padapter));
+#else
+		rtw_hal_set_hwreg(padapter, HW_VAR_MAC_ADDR, adapter_mac_addr(padapter)); /* set mac addr to mac register */
+#endif
+		/*pHalFunc->hal_deinit(padapter);*/
+		if (pHalFunc->hal_init(padapter) == _FAIL) {
+			err = -EINVAL;
+			goto exit;
+		}
+		_rtw_memset(extra, '\0', strlen(extra));
+		sprintf(extra, "eFuse Update OK\n");
+	} else if (strcmp(tmp[0], "analyze") == 0) {
+
+		rtw_efuse_analyze(padapter, EFUSE_WIFI, 0);
+		_rtw_memset(extra, '\0', strlen(extra));
+		sprintf(extra, "eFuse Analyze OK,please to check kernel log\n");
+	}
+exit:
+	if (setdata)
+		rtw_mfree(setdata, 1024);
+	if (ShadowMapBT)
+		rtw_mfree(ShadowMapBT, EFUSE_BT_MAX_MAP_LEN);
+	if (ShadowMapWiFi)
+		rtw_mfree(ShadowMapWiFi, wifimaplen);
+	if (setrawdata)
+		rtw_mfree(setrawdata, EFUSE_MAX_SIZE);
+
+	wrqu->length = strlen(extra);
+
+	if (padapter->registrypriv.mp_mode == 0) {
+#ifdef CONFIG_IPS
+		rtw_pm_set_ips(padapter, ips_mode);
+#endif /* CONFIG_IPS */
+
+#ifdef CONFIG_LPS
+		rtw_pm_set_lps(padapter, lps_mode);
+#endif /* CONFIG_LPS */
+	}
+
+	return err;
+}
+
+#ifdef CONFIG_RTW_CUSTOMER_STR
+static int rtw_mp_customer_str(
+	struct net_device *dev,
+	struct iw_request_info *info,
+	union iwreq_data *wrqu, char *extra)
+{
+	_adapter *adapter = rtw_netdev_priv(dev);
+	u32 len;
+	u8 *pbuf = NULL, *pch;
+	char *ptmp;
+	u8 param[RTW_CUSTOMER_STR_LEN];
+	u8 count = 0;
+	u8 tmp;
+	u8 i;
+	u32 pos;
+	u8 ret;
+	u8 read = 0;
+
+	if (adapter->registrypriv.mp_mode != 1
+		|| !adapter->registrypriv.mp_customer_str)
+		return -EFAULT;
+
+	len = wrqu->data.length + 1;
+
+	pbuf = (u8 *)rtw_zmalloc(len);
+	if (pbuf == NULL) {
+		RTW_WARN("%s: no memory!\n", __func__);
+		return -ENOMEM;
+	}
+
+	if (copy_from_user(pbuf, wrqu->data.pointer, wrqu->data.length)) {
+		rtw_mfree(pbuf, len);
+		RTW_WARN("%s: copy from user fail!\n", __func__);
+		return -EFAULT;
+	}
+	RTW_INFO("%s: string=\"%s\"\n", __func__, pbuf);
+
+	ptmp = (char *)pbuf;
+	pch = strsep(&ptmp, ",");
+	if ((pch == NULL) || (strlen(pch) == 0)) {
+		rtw_mfree(pbuf, len);
+		RTW_INFO("%s: parameter error(no cmd)!\n", __func__);
+		return -EFAULT;
+	}
+
+	_rtw_memset(param, 0xFF, RTW_CUSTOMER_STR_LEN);
+
+	if (strcmp(pch, "read") == 0) {
+		read = 1;
+		ret = rtw_hal_customer_str_read(adapter, param);
+
+	} else if (strcmp(pch, "write") == 0) {
+		do {
+			pch = strsep(&ptmp, ":");
+			if ((pch == NULL) || (strlen(pch) == 0))
+				break;
+			if (strlen(pch) != 2
+				|| IsHexDigit(*pch) == _FALSE
+				|| IsHexDigit(*(pch + 1)) == _FALSE
+				|| sscanf(pch, "%hhx", &tmp) != 1
+			) {
+				RTW_WARN("%s: invalid 8-bit hex!\n", __func__);
+				rtw_mfree(pbuf, len);
+				return -EFAULT;
+			}
+
+			param[count++] = tmp;
+
+		} while (count < RTW_CUSTOMER_STR_LEN);
+
+		if (count == 0) {
+			rtw_mfree(pbuf, len);
+			RTW_WARN("%s: no input!\n", __func__);
+			return -EFAULT;
+		}
+		ret = rtw_hal_customer_str_write(adapter, param);
+	} else {
+		rtw_mfree(pbuf, len);
+		RTW_INFO("%s: parameter error(unknown cmd)!\n", __func__);
+		return -EFAULT;
+	}
+
+	pos = sprintf(extra, "%s: ", read ? "read" : "write");
+	if (read == 0 || ret == _SUCCESS) {
+		for (i = 0; i < RTW_CUSTOMER_STR_LEN; i++)
+			pos += sprintf(extra + pos, "%02x:", param[i]);
+		extra[pos] = 0;
+		pos--;
+	}
+	pos += sprintf(extra + pos, " %s", ret == _SUCCESS ? "OK" : "FAIL");
+
+	wrqu->data.length = strlen(extra) + 1;
+
+free_buf:
+	rtw_mfree(pbuf, len);
+	return 0;
+}
+#endif /* CONFIG_RTW_CUSTOMER_STR */
+
+static int rtw_priv_mp_set(struct net_device *dev,
+			   struct iw_request_info *info,
+			   union iwreq_data *wdata, char *extra)
+{
+
+	struct iw_point *wrqu = (struct iw_point *)wdata;
+	u32 subcmd = wrqu->flags;
+#ifdef CONFIG_CONCURRENT_MODE
+	PADAPTER padapter = rtw_netdev_priv(dev);
+#endif
+
+	if (!is_primary_adapter(padapter)) {
+		RTW_INFO("MP mode only primary Adapter support\n");
+		return -EIO;
+	}
+
+	switch (subcmd) {
+	case CTA_TEST:
+		RTW_INFO("set CTA_TEST\n");
+		rtw_cta_test_start(dev, info, wdata, extra);
+		break;
+	case MP_DISABLE_BT_COEXIST:
+		RTW_INFO("set case MP_DISABLE_BT_COEXIST\n");
+		rtw_mp_disable_bt_coexist(dev, info, wdata, extra);
+		break;
+	case MP_IQK:
+		RTW_INFO("set MP_IQK\n");
+		rtw_mp_iqk(dev, info, wrqu, extra);
+		break;
+	case MP_LCK:
+		RTW_INFO("set MP_LCK\n");
+		rtw_mp_lck(dev, info, wrqu, extra);
+	break;
+
+	default:
+		return -EIO;
+	}
+
+	return 0;
+}
+
+static int rtw_priv_mp_get(struct net_device *dev,
+			   struct iw_request_info *info,
+			   union iwreq_data *wdata, char *extra)
+{
+
+	struct iw_point *wrqu = (struct iw_point *)wdata;
+	u32 subcmd = wrqu->flags;
+#ifdef CONFIG_CONCURRENT_MODE
+	PADAPTER padapter = rtw_netdev_priv(dev);
+#endif
+
+	if (!is_primary_adapter(padapter)) {
+		RTW_INFO("MP mode only primary Adapter support\n");
+		return -EIO;
+	}
+
+	switch (subcmd) {
+	case MP_START:
+		RTW_INFO("set case mp_start\n");
+		rtw_mp_start(dev, info, wrqu, extra);
+		break;
+	case MP_STOP:
+		RTW_INFO("set case mp_stop\n");
+		rtw_mp_stop(dev, info, wrqu, extra);
+		break;
+	case MP_BANDWIDTH:
+		RTW_INFO("set case mp_bandwidth\n");
+		rtw_mp_bandwidth(dev, info, wrqu, extra);
+		break;
+	case MP_RESET_STATS:
+		RTW_INFO("set case MP_RESET_STATS\n");
+		rtw_mp_reset_stats(dev, info, wrqu, extra);
+		break;
+	case MP_SetRFPathSwh:
+		RTW_INFO("set MP_SetRFPathSwitch\n");
+		rtw_mp_SetRFPath(dev, info, wrqu, extra);
+		break;
+	case WRITE_REG:
+		rtw_mp_write_reg(dev, info, wrqu, extra);
+		break;
+	case WRITE_RF:
+		rtw_mp_write_rf(dev, info, wrqu, extra);
+		break;
+	case MP_PHYPARA:
+		RTW_INFO("mp_get  MP_PHYPARA\n");
+		rtw_mp_phypara(dev, info, wrqu, extra);
+		break;
+	case MP_CHANNEL:
+		RTW_INFO("set case mp_channel\n");
+		rtw_mp_channel(dev , info, wrqu, extra);
+		break;
+    	case  MP_CHL_OFFSET:
+       		RTW_INFO("set case mp_ch_offset\n");
+        	rtw_mp_ch_offset(dev , info, wrqu, extra);
+        	break;
+	case READ_REG:
+		RTW_INFO("mp_get  READ_REG\n");
+		rtw_mp_read_reg(dev, info, wrqu, extra);
+		break;
+	case READ_RF:
+		RTW_INFO("mp_get  READ_RF\n");
+		rtw_mp_read_rf(dev, info, wrqu, extra);
+		break;
+	case MP_RATE:
+		RTW_INFO("set case mp_rate\n");
+		rtw_mp_rate(dev, info, wrqu, extra);
+		break;
+	case MP_TXPOWER:
+		RTW_INFO("set case MP_TXPOWER\n");
+		rtw_mp_txpower(dev, info, wrqu, extra);
+		break;
+	case MP_ANT_TX:
+		RTW_INFO("set case MP_ANT_TX\n");
+		rtw_mp_ant_tx(dev, info, wrqu, extra);
+		break;
+	case MP_ANT_RX:
+		RTW_INFO("set case MP_ANT_RX\n");
+		rtw_mp_ant_rx(dev, info, wrqu, extra);
+		break;
+	case MP_QUERY:
+		rtw_mp_trx_query(dev, info, wrqu, extra);
+		break;
+	case MP_CTX:
+		RTW_INFO("set case MP_CTX\n");
+		rtw_mp_ctx(dev, info, wrqu, extra);
+		break;
+	case MP_ARX:
+		RTW_INFO("set case MP_ARX\n");
+		rtw_mp_arx(dev, info, wrqu, extra);
+		break;
+	case MP_DUMP:
+		RTW_INFO("set case MP_DUMP\n");
+		rtw_mp_dump(dev, info, wrqu, extra);
+		break;
+	case MP_PSD:
+		RTW_INFO("set case MP_PSD\n");
+		rtw_mp_psd(dev, info, wrqu, extra);
+		break;
+	case MP_THER:
+		RTW_INFO("set case MP_THER\n");
+		rtw_mp_thermal(dev, info, wrqu, extra);
+		break;
+	case MP_PwrCtlDM:
+		RTW_INFO("set MP_PwrCtlDM\n");
+		rtw_mp_PwrCtlDM(dev, info, wrqu, extra);
+		break;
+	case MP_QueryDrvStats:
+		RTW_INFO("mp_get MP_QueryDrvStats\n");
+		rtw_mp_QueryDrv(dev, info, wdata, extra);
+		break;
+	case MP_PWRTRK:
+		RTW_INFO("set case MP_PWRTRK\n");
+		rtw_mp_pwrtrk(dev, info, wrqu, extra);
+		break;
+#ifdef CONFIG_MP_INCLUDED
+	case EFUSE_SET:
+		RTW_INFO("set case efuse set\n");
+		rtw_mp_efuse_set(dev, info, wdata, extra);
+		break;
+#endif
+	case EFUSE_GET:
+		RTW_INFO("efuse get EFUSE_GET\n");
+		rtw_mp_efuse_get(dev, info, wdata, extra);
+		break;
+	case MP_GET_TXPOWER_INX:
+		RTW_INFO("mp_get MP_GET_TXPOWER_INX\n");
+		rtw_mp_txpower_index(dev, info, wrqu, extra);
+		break;
+	case MP_GETVER:
+		RTW_INFO("mp_get MP_GETVER\n");
+		rtw_mp_getver(dev, info, wdata, extra);
+		break;
+	case MP_MON:
+		RTW_INFO("mp_get MP_MON\n");
+		rtw_mp_mon(dev, info, wdata, extra);
+		break;
+	case EFUSE_MASK:
+		RTW_INFO("mp_get EFUSE_MASK\n");
+		rtw_efuse_mask_file(dev, info, wdata, extra);
+		break;
+	case  EFUSE_FILE:
+		RTW_INFO("mp_get EFUSE_FILE\n");
+		rtw_efuse_file_map(dev, info, wdata, extra);
+		break;
+	case  MP_TX:
+		RTW_INFO("mp_get MP_TX\n");
+		rtw_mp_tx(dev, info, wdata, extra);
+		break;
+	case  MP_RX:
+		RTW_INFO("mp_get MP_RX\n");
+		rtw_mp_rx(dev, info, wdata, extra);
+		break;
+	case MP_HW_TX_MODE:
+		RTW_INFO("mp_get MP_HW_TX_MODE\n");
+		rtw_mp_hwtx(dev, info, wdata, extra);
+		break;
+#ifdef CONFIG_RTW_CUSTOMER_STR
+	case MP_CUSTOMER_STR:
+		RTW_INFO("customer str\n");
+		rtw_mp_customer_str(dev, info, wdata, extra);
+		break;
+#endif
+	case MP_PWRLMT:
+		RTW_INFO("mp_get MP_SETPWRLMT\n");
+		rtw_mp_pwrlmt(dev, info, wdata, extra);
+		break;
+	case MP_PWRBYRATE:
+		RTW_INFO("mp_get MP_SETPWRBYRATE\n");
+		rtw_mp_pwrbyrate(dev, info, wdata, extra);
+		break;
+	case  BT_EFUSE_FILE:
+		RTW_INFO("mp_get BT EFUSE_FILE\n");
+		rtw_bt_efuse_file_map(dev, info, wdata, extra);
+		break;
+	case  MP_SWRFPath:
+		RTW_INFO("mp_get MP_SWRFPath\n");
+		rtw_mp_switch_rf_path(dev, info, wrqu, extra);
+		break;
+	default:
+		return -EIO;
+	}
+
+	return 0;
+}
+#endif /*#if defined(CONFIG_MP_INCLUDED)*/
+
+
+#ifdef CONFIG_SDIO_INDIRECT_ACCESS
+#define DBG_MP_SDIO_INDIRECT_ACCESS 1
+static int rtw_mp_sd_iread(struct net_device *dev
+			   , struct iw_request_info *info
+			   , struct iw_point *wrqu
+			   , char *extra)
+{
+	char input[16];
+	u8 width;
+	unsigned long addr;
+	u32 ret = 0;
+	PADAPTER padapter = rtw_netdev_priv(dev);
+
+	if (wrqu->length > 16) {
+		RTW_INFO(FUNC_ADPT_FMT" wrqu->length:%d\n", FUNC_ADPT_ARG(padapter), wrqu->length);
+		ret = -EINVAL;
+		goto exit;
+	}
+
+	if (copy_from_user(input, wrqu->pointer, wrqu->length)) {
+		RTW_INFO(FUNC_ADPT_FMT" copy_from_user fail\n", FUNC_ADPT_ARG(padapter));
+		ret = -EFAULT;
+		goto exit;
+	}
+
+	_rtw_memset(extra, 0, wrqu->length);
+
+	if (sscanf(input, "%hhu,%lx", &width, &addr) != 2) {
+		RTW_INFO(FUNC_ADPT_FMT" sscanf fail\n", FUNC_ADPT_ARG(padapter));
+		ret = -EINVAL;
+		goto exit;
+	}
+
+	if (addr > 0x3FFF) {
+		RTW_INFO(FUNC_ADPT_FMT" addr:0x%lx\n", FUNC_ADPT_ARG(padapter), addr);
+		ret = -EINVAL;
+		goto exit;
+	}
+
+	if (DBG_MP_SDIO_INDIRECT_ACCESS)
+		RTW_INFO(FUNC_ADPT_FMT" width:%u, addr:0x%lx\n", FUNC_ADPT_ARG(padapter), width, addr);
+
+	switch (width) {
+	case 1:
+		sprintf(extra, "0x%02x", rtw_sd_iread8(padapter, addr));
+		wrqu->length = strlen(extra);
+		break;
+	case 2:
+		sprintf(extra, "0x%04x", rtw_sd_iread16(padapter, addr));
+		wrqu->length = strlen(extra);
+		break;
+	case 4:
+		sprintf(extra, "0x%08x", rtw_sd_iread32(padapter, addr));
+		wrqu->length = strlen(extra);
+		break;
+	default:
+		wrqu->length = 0;
+		ret = -EINVAL;
+		break;
+	}
+
+exit:
+	return ret;
+}
+
+static int rtw_mp_sd_iwrite(struct net_device *dev
+			    , struct iw_request_info *info
+			    , struct iw_point *wrqu
+			    , char *extra)
+{
+	char width;
+	unsigned long addr, data;
+	int ret = 0;
+	PADAPTER padapter = rtw_netdev_priv(dev);
+	char input[32];
+
+	if (wrqu->length > 32) {
+		RTW_INFO(FUNC_ADPT_FMT" wrqu->length:%d\n", FUNC_ADPT_ARG(padapter), wrqu->length);
+		ret = -EINVAL;
+		goto exit;
+	}
+
+	if (copy_from_user(input, wrqu->pointer, wrqu->length)) {
+		RTW_INFO(FUNC_ADPT_FMT" copy_from_user fail\n", FUNC_ADPT_ARG(padapter));
+		ret = -EFAULT;
+		goto exit;
+	}
+
+	_rtw_memset(extra, 0, wrqu->length);
+
+	if (sscanf(input, "%hhu,%lx,%lx", &width, &addr, &data) != 3) {
+		RTW_INFO(FUNC_ADPT_FMT" sscanf fail\n", FUNC_ADPT_ARG(padapter));
+		ret = -EINVAL;
+		goto exit;
+	}
+
+	if (addr > 0x3FFF) {
+		RTW_INFO(FUNC_ADPT_FMT" addr:0x%lx\n", FUNC_ADPT_ARG(padapter), addr);
+		ret = -EINVAL;
+		goto exit;
+	}
+
+	if (DBG_MP_SDIO_INDIRECT_ACCESS)
+		RTW_INFO(FUNC_ADPT_FMT" width:%u, addr:0x%lx, data:0x%lx\n", FUNC_ADPT_ARG(padapter), width, addr, data);
+
+	switch (width) {
+	case 1:
+		if (data > 0xFF) {
+			ret = -EINVAL;
+			break;
+		}
+		rtw_sd_iwrite8(padapter, addr, data);
+		break;
+	case 2:
+		if (data > 0xFFFF) {
+			ret = -EINVAL;
+			break;
+		}
+		rtw_sd_iwrite16(padapter, addr, data);
+		break;
+	case 4:
+		rtw_sd_iwrite32(padapter, addr, data);
+		break;
+	default:
+		wrqu->length = 0;
+		ret = -EINVAL;
+		break;
+	}
+
+exit:
+	return ret;
+}
+#endif /* CONFIG_SDIO_INDIRECT_ACCESS */
+
+static int rtw_priv_set(struct net_device *dev,
+			struct iw_request_info *info,
+			union iwreq_data *wdata, char *extra)
+{
+	struct iw_point *wrqu = (struct iw_point *)wdata;
+	u32 subcmd = wrqu->flags;
+	PADAPTER padapter = rtw_netdev_priv(dev);
+
+	if (padapter == NULL)
+		return -ENETDOWN;
+
+	if (padapter->bup == _FALSE) {
+		RTW_INFO(" %s fail =>(padapter->bup == _FALSE )\n", __FUNCTION__);
+		return -ENETDOWN;
+	}
+
+	if (RTW_CANNOT_RUN(padapter)) {
+		RTW_INFO("%s fail =>(bSurpriseRemoved == _TRUE) || ( bDriverStopped == _TRUE)\n", __func__);
+		return -ENETDOWN;
+	}
+
+	if (extra == NULL) {
+		wrqu->length = 0;
+		return -EIO;
+	}
+
+	if (subcmd < MP_NULL) {
+#ifdef CONFIG_MP_INCLUDED
+		rtw_priv_mp_set(dev, info, wdata, extra);
+#endif
+		return 0;
+	}
+
+	switch (subcmd) {
+#ifdef CONFIG_WOWLAN
+	case MP_WOW_ENABLE:
+		RTW_INFO("set case MP_WOW_ENABLE: %s\n", extra);
+
+		rtw_wowlan_ctrl(dev, info, wdata, extra);
+		break;
+	case MP_WOW_SET_PATTERN:
+		RTW_INFO("set case MP_WOW_SET_PATTERN: %s\n", extra);
+		rtw_wowlan_set_pattern(dev, info, wdata, extra);
+		break;
+#endif
+#ifdef CONFIG_AP_WOWLAN
+	case MP_AP_WOW_ENABLE:
+		RTW_INFO("set case MP_AP_WOW_ENABLE: %s\n", extra);
+		rtw_ap_wowlan_ctrl(dev, info, wdata, extra);
+		break;
+#endif
+#ifdef CONFIG_APPEND_VENDOR_IE_ENABLE
+	case VENDOR_IE_SET:
+		RTW_INFO("set case VENDOR_IE_SET\n");
+		rtw_vendor_ie_set(dev , info , wdata , extra);
+		break;
+#endif
+	default:
+		return -EIO;
+	}
+
+	return 0;
+}
+
+
+static int rtw_priv_get(struct net_device *dev,
+			struct iw_request_info *info,
+			union iwreq_data *wdata, char *extra)
+{
+	struct iw_point *wrqu = (struct iw_point *)wdata;
+	u32 subcmd = wrqu->flags;
+	PADAPTER padapter = rtw_netdev_priv(dev);
+
+
+	if (padapter == NULL)
+		return -ENETDOWN;
+
+	if (padapter->bup == _FALSE) {
+		RTW_INFO(" %s fail =>(padapter->bup == _FALSE )\n", __FUNCTION__);
+		return -ENETDOWN;
+	}
+
+	if (RTW_CANNOT_RUN(padapter)) {
+		RTW_INFO("%s fail =>(padapter->bSurpriseRemoved == _TRUE) || ( padapter->bDriverStopped == _TRUE)\n", __func__);
+		return -ENETDOWN;
+	}
+
+	if (extra == NULL) {
+		wrqu->length = 0;
+		return -EIO;
+	}
+
+	if (subcmd < MP_NULL) {
+#ifdef CONFIG_MP_INCLUDED
+		rtw_priv_mp_get(dev, info, wdata, extra);
+#endif
+		return 0;
+	}
+
+	switch (subcmd) {
+#if defined(CONFIG_RTL8723B)
+	case MP_SetBT:
+		RTW_INFO("set MP_SetBT\n");
+		rtw_mp_SetBT(dev, info, wdata, extra);
+		break;
+#endif
+#ifdef CONFIG_SDIO_INDIRECT_ACCESS
+	case MP_SD_IREAD:
+		rtw_mp_sd_iread(dev, info, wrqu, extra);
+		break;
+	case MP_SD_IWRITE:
+		rtw_mp_sd_iwrite(dev, info, wrqu, extra);
+		break;
+#endif
+#ifdef CONFIG_APPEND_VENDOR_IE_ENABLE
+	case VENDOR_IE_GET:
+		RTW_INFO("get case VENDOR_IE_GET\n");
+		rtw_vendor_ie_get(dev , info , wdata , extra);
+		break;
+#endif
+	default:
+		return -EIO;
+	}
+
+	rtw_msleep_os(10); /* delay 5ms for sending pkt before exit adb shell operation */
+	return 0;
+}
+
+
+
+static int rtw_wx_tdls_wfd_enable(struct net_device *dev,
+				  struct iw_request_info *info,
+				  union iwreq_data *wrqu, char *extra)
+{
+	int ret = 0;
+
+#ifdef CONFIG_TDLS
+#ifdef CONFIG_WFD
+
+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
+
+	RTW_INFO("[%s] %s %d\n", __FUNCTION__, extra, wrqu->data.length - 1);
+
+	if (extra[0] == '0')
+		rtw_tdls_wfd_enable(padapter, 0);
+	else
+		rtw_tdls_wfd_enable(padapter, 1);
+
+#endif /* CONFIG_WFD */
+#endif /* CONFIG_TDLS */
+
+	return ret;
+}
+
+static int rtw_tdls_weaksec(struct net_device *dev,
+			    struct iw_request_info *info,
+			    union iwreq_data *wrqu, char *extra)
+{
+	int ret = 0;
+
+#ifdef CONFIG_TDLS
+
+	u8 i, j;
+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
+
+	RTW_INFO("[%s] %s %d\n", __FUNCTION__, extra, wrqu->data.length - 1);
+
+	if (extra[0] == '0')
+		padapter->wdinfo.wfd_tdls_weaksec = 0;
+	else
+		padapter->wdinfo.wfd_tdls_weaksec = 1;
+
+#endif /* CONFIG_TDLS */
+
+	return ret;
+}
+
+
+static int rtw_tdls_enable(struct net_device *dev,
+			   struct iw_request_info *info,
+			   union iwreq_data *wrqu, char *extra)
+{
+	int ret = 0;
+
+#ifdef CONFIG_TDLS
+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
+
+	RTW_INFO("[%s] %s %d\n", __FUNCTION__, extra, wrqu->data.length - 1);
+
+	if (extra[0] == '0')
+		rtw_disable_tdls_func(padapter, _TRUE);
+	else if (extra[0] == '1')
+		rtw_enable_tdls_func(padapter);
+#endif /* CONFIG_TDLS */
+
+	return ret;
+}
+
+static int rtw_tdls_setup(struct net_device *dev,
+			  struct iw_request_info *info,
+			  union iwreq_data *wrqu, char *extra)
+{
+	int ret = 0;
+#ifdef CONFIG_TDLS
+	u8 i, j;
+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
+	struct tdls_txmgmt txmgmt;
+#ifdef CONFIG_WFD
+	struct wifidirect_info *pwdinfo = &(padapter->wdinfo);
+#endif /* CONFIG_WFD */
+
+	RTW_INFO("[%s] %s %d\n", __FUNCTION__, extra, wrqu->data.length - 1);
+
+	if (wrqu->data.length - 1 != 17) {
+		RTW_INFO("[%s] length:%d != 17\n", __FUNCTION__, (wrqu->data.length - 1));
+		return ret;
+	}
+
+	_rtw_memset(&txmgmt, 0x00, sizeof(struct tdls_txmgmt));
+	for (i = 0, j = 0 ; i < ETH_ALEN; i++, j += 3)
+		txmgmt.peer[i] = key_2char2num(*(extra + j), *(extra + j + 1));
+
+#ifdef CONFIG_WFD
+	if (_AES_ != padapter->securitypriv.dot11PrivacyAlgrthm) {
+		/* Weak Security situation with AP. */
+		if (0 == pwdinfo->wfd_tdls_weaksec)	{
+			/* Can't send the tdls setup request out!! */
+			RTW_INFO("[%s] Current link is not AES, "
+				"SKIP sending the tdls setup request!!\n", __FUNCTION__);
+		} else
+			issue_tdls_setup_req(padapter, &txmgmt, _TRUE);
+	} else
+#endif /* CONFIG_WFD */
+	{
+		issue_tdls_setup_req(padapter, &txmgmt, _TRUE);
+	}
+#endif /* CONFIG_TDLS */
+
+	return ret;
+}
+
+static int rtw_tdls_teardown(struct net_device *dev,
+			     struct iw_request_info *info,
+			     union iwreq_data *wrqu, char *extra)
+{
+	int ret = 0;
+
+#ifdef CONFIG_TDLS
+
+	u8 i, j;
+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
+	struct sta_info *ptdls_sta = NULL;
+	struct tdls_txmgmt txmgmt;
+
+	RTW_INFO("[%s] %s %d\n", __FUNCTION__, extra, wrqu->data.length - 1);
+
+	if (wrqu->data.length - 1 != 17 && wrqu->data.length - 1 != 19) {
+		RTW_INFO("[%s] length:%d != 17 or 19\n",
+			 __FUNCTION__, (wrqu->data.length - 1));
+		return ret;
+	}
+
+	_rtw_memset(&txmgmt, 0x00, sizeof(struct tdls_txmgmt));
+	for (i = 0, j = 0; i < ETH_ALEN; i++, j += 3)
+		txmgmt.peer[i] = key_2char2num(*(extra + j), *(extra + j + 1));
+
+	ptdls_sta = rtw_get_stainfo(&(padapter->stapriv), txmgmt.peer);
+
+	if (ptdls_sta != NULL) {
+		txmgmt.status_code = _RSON_TDLS_TEAR_UN_RSN_;
+		if (wrqu->data.length - 1 == 19)
+			issue_tdls_teardown(padapter, &txmgmt, _FALSE);
+		else
+			issue_tdls_teardown(padapter, &txmgmt, _TRUE);
+	} else
+		RTW_INFO("TDLS peer not found\n");
+#endif /* CONFIG_TDLS */
+
+	return ret;
+}
+
+static int rtw_tdls_discovery(struct net_device *dev,
+			      struct iw_request_info *info,
+			      union iwreq_data *wrqu, char *extra)
+{
+	int ret = 0;
+
+#ifdef CONFIG_TDLS
+
+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
+	struct tdls_txmgmt	txmgmt;
+	int i = 0, j = 0;
+
+	RTW_INFO("[%s] %s %d\n", __FUNCTION__, extra, wrqu->data.length - 1);
+
+	_rtw_memset(&txmgmt, 0x00, sizeof(struct tdls_txmgmt));
+	for (i = 0, j = 0 ; i < ETH_ALEN; i++, j += 3)
+		txmgmt.peer[i] = key_2char2num(*(extra + j), *(extra + j + 1));
+
+	issue_tdls_dis_req(padapter, &txmgmt);
+
+#endif /* CONFIG_TDLS */
+
+	return ret;
+}
+
+static int rtw_tdls_ch_switch(struct net_device *dev,
+			      struct iw_request_info *info,
+			      union iwreq_data *wrqu, char *extra)
+{
+	int ret = 0;
+
+#ifdef CONFIG_TDLS
+#ifdef CONFIG_TDLS_CH_SW
+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
+	struct tdls_ch_switch *pchsw_info = &padapter->tdlsinfo.chsw_info;
+	u8 i, j;
+	struct sta_info *ptdls_sta = NULL;
+	u8 take_care_iqk;
+
+	RTW_INFO("[%s] %s %d\n", __FUNCTION__, extra, wrqu->data.length - 1);
+
+	if (rtw_tdls_is_chsw_allowed(padapter) == _FALSE) {
+		RTW_INFO("TDLS channel switch is not allowed\n");
+		return ret;
+	}
+
+	for (i = 0, j = 0 ; i < ETH_ALEN; i++, j += 3)
+		pchsw_info->addr[i] = key_2char2num(*(extra + j), *(extra + j + 1));
+
+	ptdls_sta = rtw_get_stainfo(&padapter->stapriv, pchsw_info->addr);
+	if (ptdls_sta == NULL)
+		return ret;
+
+	pchsw_info->ch_sw_state |= TDLS_CH_SW_INITIATOR_STATE;
+
+	if (ptdls_sta != NULL) {
+		if (pchsw_info->off_ch_num == 0)
+			pchsw_info->off_ch_num = 11;
+	} else
+		RTW_INFO("TDLS peer not found\n");
+
+	rtw_pm_set_lps(padapter, PS_MODE_ACTIVE);
+
+	rtw_hal_get_hwreg(padapter, HW_VAR_CH_SW_NEED_TO_TAKE_CARE_IQK_INFO, &take_care_iqk);
+	if (take_care_iqk == _TRUE) {
+		u8 central_chnl;
+		u8 bw_mode;
+
+		bw_mode = (pchsw_info->ch_offset) ? CHANNEL_WIDTH_40 : CHANNEL_WIDTH_20;
+		central_chnl = rtw_get_center_ch(pchsw_info->off_ch_num, bw_mode, pchsw_info->ch_offset);
+		if (rtw_hal_ch_sw_iqk_info_search(padapter, central_chnl, bw_mode) >= 0)
+			rtw_tdls_cmd(padapter, ptdls_sta->cmn.mac_addr, TDLS_CH_SW_START);
+		else
+			rtw_tdls_cmd(padapter, ptdls_sta->cmn.mac_addr, TDLS_CH_SW_PREPARE);
+	} else
+		rtw_tdls_cmd(padapter, ptdls_sta->cmn.mac_addr, TDLS_CH_SW_START);
+
+	/* issue_tdls_ch_switch_req(padapter, ptdls_sta); */
+	/* RTW_INFO("issue tdls ch switch req\n"); */
+
+#endif /* CONFIG_TDLS_CH_SW */
+#endif /* CONFIG_TDLS */
+
+	return ret;
+}
+
+static int rtw_tdls_ch_switch_off(struct net_device *dev,
+				  struct iw_request_info *info,
+				  union iwreq_data *wrqu, char *extra)
+{
+	int ret = 0;
+
+#ifdef CONFIG_TDLS
+#ifdef CONFIG_TDLS_CH_SW
+
+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
+	struct tdls_ch_switch *pchsw_info = &padapter->tdlsinfo.chsw_info;
+	u8 i, j, mac_addr[ETH_ALEN];
+	struct sta_info *ptdls_sta = NULL;
+	struct tdls_txmgmt txmgmt;
+
+	_rtw_memset(&txmgmt, 0x00, sizeof(struct tdls_txmgmt));
+
+	RTW_INFO("[%s] %s %d\n", __FUNCTION__, extra, wrqu->data.length - 1);
+
+	if (rtw_tdls_is_chsw_allowed(padapter) == _FALSE) {
+		RTW_INFO("TDLS channel switch is not allowed\n");
+		return ret;
+	}
+
+	if (wrqu->data.length >= 17) {
+		for (i = 0, j = 0 ; i < ETH_ALEN; i++, j += 3)
+			mac_addr[i] = key_2char2num(*(extra + j), *(extra + j + 1));
+		ptdls_sta = rtw_get_stainfo(&padapter->stapriv, mac_addr);
+	}
+
+	if (ptdls_sta == NULL)
+		return ret;
+
+	rtw_tdls_cmd(padapter, ptdls_sta->cmn.mac_addr, TDLS_CH_SW_END_TO_BASE_CHNL);
+
+	pchsw_info->ch_sw_state &= ~(TDLS_CH_SW_INITIATOR_STATE |
+				     TDLS_CH_SWITCH_ON_STATE |
+				     TDLS_PEER_AT_OFF_STATE);
+	_rtw_memset(pchsw_info->addr, 0x00, ETH_ALEN);
+
+	ptdls_sta->ch_switch_time = 0;
+	ptdls_sta->ch_switch_timeout = 0;
+	_cancel_timer_ex(&ptdls_sta->ch_sw_timer);
+	_cancel_timer_ex(&ptdls_sta->delay_timer);
+	_cancel_timer_ex(&ptdls_sta->stay_on_base_chnl_timer);
+	_cancel_timer_ex(&ptdls_sta->ch_sw_monitor_timer);
+
+	rtw_pm_set_lps(padapter, PS_MODE_MAX);
+#endif /* CONFIG_TDLS_CH_SW */
+#endif /* CONFIG_TDLS */
+
+	return ret;
+}
+
+static int rtw_tdls_dump_ch(struct net_device *dev,
+			    struct iw_request_info *info,
+			    union iwreq_data *wrqu, char *extra)
+{
+	int ret = 0;
+
+#ifdef CONFIG_TDLS
+#ifdef CONFIG_TDLS_CH_SW
+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
+	struct tdls_info *ptdlsinfo = &padapter->tdlsinfo;
+
+	RTW_INFO("[%s] dump_stack:%s\n", __FUNCTION__, extra);
+
+	extra[wrqu->data.length] = 0x00;
+	ptdlsinfo->chsw_info.dump_stack = rtw_atoi(extra);
+
+	return ret;
+
+#endif
+#endif /* CONFIG_TDLS */
+
+	return ret;
+}
+
+static int rtw_tdls_off_ch_num(struct net_device *dev,
+			       struct iw_request_info *info,
+			       union iwreq_data *wrqu, char *extra)
+{
+	int ret = 0;
+
+#ifdef CONFIG_TDLS
+#ifdef CONFIG_TDLS_CH_SW
+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
+	struct tdls_info *ptdlsinfo = &padapter->tdlsinfo;
+
+	RTW_INFO("[%s] off_ch_num:%s\n", __FUNCTION__, extra);
+
+	extra[wrqu->data.length] = 0x00;
+	ptdlsinfo->chsw_info.off_ch_num = rtw_atoi(extra);
+
+	return ret;
+
+#endif
+#endif /* CONFIG_TDLS */
+
+	return ret;
+}
+
+static int rtw_tdls_ch_offset(struct net_device *dev,
+			      struct iw_request_info *info,
+			      union iwreq_data *wrqu, char *extra)
+{
+	int ret = 0;
+
+#ifdef CONFIG_TDLS
+#ifdef CONFIG_TDLS_CH_SW
+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
+	struct tdls_info *ptdlsinfo = &padapter->tdlsinfo;
+
+	RTW_INFO("[%s] ch_offset:%s\n", __FUNCTION__, extra);
+
+	extra[wrqu->data.length] = 0x00;
+	switch (rtw_atoi(extra)) {
+	case SCA:
+		ptdlsinfo->chsw_info.ch_offset = HAL_PRIME_CHNL_OFFSET_LOWER;
+		break;
+
+	case SCB:
+		ptdlsinfo->chsw_info.ch_offset = HAL_PRIME_CHNL_OFFSET_UPPER;
+		break;
+
+	default:
+		ptdlsinfo->chsw_info.ch_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
+		break;
+	}
+
+	return ret;
+
+#endif
+#endif /* CONFIG_TDLS */
+
+	return ret;
+}
+
+static int rtw_tdls_pson(struct net_device *dev,
+			 struct iw_request_info *info,
+			 union iwreq_data *wrqu, char *extra)
+{
+	int ret = 0;
+
+#ifdef CONFIG_TDLS
+
+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
+	u8 i, j, mac_addr[ETH_ALEN];
+	struct sta_info *ptdls_sta = NULL;
+
+	RTW_INFO("[%s] %s %d\n", __FUNCTION__, extra, wrqu->data.length - 1);
+
+	for (i = 0, j = 0; i < ETH_ALEN; i++, j += 3)
+		mac_addr[i] = key_2char2num(*(extra + j), *(extra + j + 1));
+
+	ptdls_sta = rtw_get_stainfo(&padapter->stapriv, mac_addr);
+
+	issue_nulldata_to_TDLS_peer_STA(padapter, ptdls_sta->cmn.mac_addr, 1, 3, 500);
+
+#endif /* CONFIG_TDLS */
+
+	return ret;
+}
+
+static int rtw_tdls_psoff(struct net_device *dev,
+			  struct iw_request_info *info,
+			  union iwreq_data *wrqu, char *extra)
+{
+	int ret = 0;
+
+#ifdef CONFIG_TDLS
+
+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
+	u8 i, j, mac_addr[ETH_ALEN];
+	struct sta_info *ptdls_sta = NULL;
+
+	RTW_INFO("[%s] %s %d\n", __FUNCTION__, extra, wrqu->data.length - 1);
+
+	for (i = 0, j = 0; i < ETH_ALEN; i++, j += 3)
+		mac_addr[i] = key_2char2num(*(extra + j), *(extra + j + 1));
+
+	ptdls_sta = rtw_get_stainfo(&padapter->stapriv, mac_addr);
+
+	if (ptdls_sta)
+		issue_nulldata_to_TDLS_peer_STA(padapter, ptdls_sta->cmn.mac_addr, 0, 3, 500);
+
+#endif /* CONFIG_TDLS */
+
+	return ret;
+}
+
+static int rtw_tdls_setip(struct net_device *dev,
+			  struct iw_request_info *info,
+			  union iwreq_data *wrqu, char *extra)
+{
+	int ret = 0;
+
+#ifdef CONFIG_TDLS
+#ifdef CONFIG_WFD
+
+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
+	struct tdls_info *ptdlsinfo = &padapter->tdlsinfo;
+	struct wifi_display_info *pwfd_info = ptdlsinfo->wfd_info;
+	u8 i = 0, j = 0, k = 0, tag = 0;
+
+	RTW_INFO("[%s] %s %d\n", __FUNCTION__, extra, wrqu->data.length - 1);
+
+	while (i < 4) {
+		for (j = 0; j < 4; j++) {
+			if (*(extra + j + tag) == '.' || *(extra + j + tag) == '\0') {
+				if (j == 1)
+					pwfd_info->ip_address[i] = convert_ip_addr('0', '0', *(extra + (j - 1) + tag));
+				if (j == 2)
+					pwfd_info->ip_address[i] = convert_ip_addr('0', *(extra + (j - 2) + tag), *(extra + (j - 1) + tag));
+				if (j == 3)
+					pwfd_info->ip_address[i] = convert_ip_addr(*(extra + (j - 3) + tag), *(extra + (j - 2) + tag), *(extra + (j - 1) + tag));
+
+				tag += j + 1;
+				break;
+			}
+		}
+		i++;
+	}
+
+	RTW_INFO("[%s] Set IP = %u.%u.%u.%u\n", __FUNCTION__,
+		 ptdlsinfo->wfd_info->ip_address[0],
+		 ptdlsinfo->wfd_info->ip_address[1],
+		 ptdlsinfo->wfd_info->ip_address[2],
+		 ptdlsinfo->wfd_info->ip_address[3]);
+
+#endif /* CONFIG_WFD */
+#endif /* CONFIG_TDLS */
+
+	return ret;
+}
+
+static int rtw_tdls_getip(struct net_device *dev,
+			  struct iw_request_info *info,
+			  union iwreq_data *wrqu, char *extra)
+{
+	int ret = 0;
+
+#ifdef CONFIG_TDLS
+#ifdef CONFIG_WFD
+
+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
+	struct tdls_info *ptdlsinfo = &padapter->tdlsinfo;
+	struct wifi_display_info *pwfd_info = ptdlsinfo->wfd_info;
+
+	RTW_INFO("[%s]\n", __FUNCTION__);
+
+	sprintf(extra, "\n\n%u.%u.%u.%u\n",
+		pwfd_info->peer_ip_address[0], pwfd_info->peer_ip_address[1],
+		pwfd_info->peer_ip_address[2], pwfd_info->peer_ip_address[3]);
+
+	RTW_INFO("[%s] IP=%u.%u.%u.%u\n", __FUNCTION__,
+		 pwfd_info->peer_ip_address[0], pwfd_info->peer_ip_address[1],
+		 pwfd_info->peer_ip_address[2], pwfd_info->peer_ip_address[3]);
+
+	wrqu->data.length = strlen(extra);
+
+#endif /* CONFIG_WFD */
+#endif /* CONFIG_TDLS */
+
+	return ret;
+}
+
+static int rtw_tdls_getport(struct net_device *dev,
+			    struct iw_request_info *info,
+			    union iwreq_data *wrqu, char *extra)
+{
+
+	int ret = 0;
+
+#ifdef CONFIG_TDLS
+#ifdef CONFIG_WFD
+
+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
+	struct tdls_info *ptdlsinfo = &padapter->tdlsinfo;
+	struct wifi_display_info *pwfd_info = ptdlsinfo->wfd_info;
+
+	RTW_INFO("[%s]\n", __FUNCTION__);
+
+	sprintf(extra, "\n\n%d\n", pwfd_info->peer_rtsp_ctrlport);
+	RTW_INFO("[%s] remote port = %d\n",
+		 __FUNCTION__, pwfd_info->peer_rtsp_ctrlport);
+
+	wrqu->data.length = strlen(extra);
+
+#endif /* CONFIG_WFD */
+#endif /* CONFIG_TDLS */
+
+	return ret;
+
+}
+
+/* WFDTDLS, for sigma test */
+static int rtw_tdls_dis_result(struct net_device *dev,
+			       struct iw_request_info *info,
+			       union iwreq_data *wrqu, char *extra)
+{
+
+	int ret = 0;
+
+#ifdef CONFIG_TDLS
+#ifdef CONFIG_WFD
+
+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
+	struct tdls_info *ptdlsinfo = &padapter->tdlsinfo;
+
+	RTW_INFO("[%s]\n", __FUNCTION__);
+
+	if (ptdlsinfo->dev_discovered == _TRUE) {
+		sprintf(extra, "\n\nDis=1\n");
+		ptdlsinfo->dev_discovered = _FALSE;
+	}
+
+	wrqu->data.length = strlen(extra);
+
+#endif /* CONFIG_WFD */
+#endif /* CONFIG_TDLS */
+
+	return ret;
+
+}
+
+/* WFDTDLS, for sigma test */
+static int rtw_wfd_tdls_status(struct net_device *dev,
+			       struct iw_request_info *info,
+			       union iwreq_data *wrqu, char *extra)
+{
+
+	int ret = 0;
+
+#ifdef CONFIG_TDLS
+
+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
+	struct tdls_info *ptdlsinfo = &padapter->tdlsinfo;
+
+	RTW_INFO("[%s]\n", __FUNCTION__);
+
+	sprintf(extra, "\nlink_established:%d\n"
+		"sta_cnt:%d\n"
+		"sta_maximum:%d\n"
+		"cur_channel:%d\n"
+		"tdls_enable:%d"
+#ifdef CONFIG_TDLS_CH_SW
+		"ch_sw_state:%08x\n"
+		"chsw_on:%d\n"
+		"off_ch_num:%d\n"
+		"cur_time:%d\n"
+		"ch_offset:%d\n"
+		"delay_swtich_back:%d"
+#endif
+		,
+		ptdlsinfo->link_established, ptdlsinfo->sta_cnt,
+		ptdlsinfo->sta_maximum, ptdlsinfo->cur_channel,
+		rtw_is_tdls_enabled(padapter)
+#ifdef CONFIG_TDLS_CH_SW
+		,
+		ptdlsinfo->chsw_info.ch_sw_state,
+		ATOMIC_READ(&padapter->tdlsinfo.chsw_info.chsw_on),
+		ptdlsinfo->chsw_info.off_ch_num,
+		ptdlsinfo->chsw_info.cur_time,
+		ptdlsinfo->chsw_info.ch_offset,
+		ptdlsinfo->chsw_info.delay_switch_back
+#endif
+	       );
+
+	wrqu->data.length = strlen(extra);
+
+#endif /* CONFIG_TDLS */
+
+	return ret;
+
+}
+
+static int rtw_tdls_getsta(struct net_device *dev,
+			   struct iw_request_info *info,
+			   union iwreq_data *wrqu, char *extra)
+{
+
+	int ret = 0;
+#ifdef CONFIG_TDLS
+	u8 i, j;
+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
+	u8 addr[ETH_ALEN] = {0};
+	char charmac[17];
+	struct sta_info *ptdls_sta = NULL;
+
+	RTW_INFO("[%s] %s %d\n", __FUNCTION__,
+		 (char *)wrqu->data.pointer, wrqu->data.length - 1);
+
+	if (copy_from_user(charmac, wrqu->data.pointer + 9, 17)) {
+		ret = -EFAULT;
+		goto exit;
+	}
+
+	RTW_INFO("[%s] %d, charmac:%s\n", __FUNCTION__, __LINE__, charmac);
+	for (i = 0, j = 0 ; i < ETH_ALEN; i++, j += 3)
+		addr[i] = key_2char2num(*(charmac + j), *(charmac + j + 1));
+
+	RTW_INFO("[%s] %d, charmac:%s, addr:"MAC_FMT"\n",
+		 __FUNCTION__, __LINE__, charmac, MAC_ARG(addr));
+	ptdls_sta = rtw_get_stainfo(&padapter->stapriv, addr);
+	if (ptdls_sta) {
+		sprintf(extra, "\n\ntdls_sta_state=0x%08x\n", ptdls_sta->tdls_sta_state);
+		RTW_INFO("\n\ntdls_sta_state=%d\n", ptdls_sta->tdls_sta_state);
+	} else {
+		sprintf(extra, "\n\nNot found this sta\n");
+		RTW_INFO("\n\nNot found this sta\n");
+	}
+	wrqu->data.length = strlen(extra);
+
+#endif /* CONFIG_TDLS */
+exit:
+	return ret;
+
+}
+
+static int rtw_tdls_get_best_ch(struct net_device *dev,
+				struct iw_request_info *info,
+				union iwreq_data *wrqu, char *extra)
+{
+#ifdef CONFIG_FIND_BEST_CHANNEL
+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
+	struct rf_ctl_t *rfctl = adapter_to_rfctl(padapter);
+	u32 i, best_channel_24G = 1, best_channel_5G = 36, index_24G = 0, index_5G = 0;
+
+	for (i = 0; i < rfctl->max_chan_nums && rfctl->channel_set[i].ChannelNum != 0; i++) {
+		if (rfctl->channel_set[i].ChannelNum == 1)
+			index_24G = i;
+		if (rfctl->channel_set[i].ChannelNum == 36)
+			index_5G = i;
+	}
+
+	for (i = 0; i < rfctl->max_chan_nums && rfctl->channel_set[i].ChannelNum != 0; i++) {
+		/* 2.4G */
+		if (rfctl->channel_set[i].ChannelNum == 6 || rfctl->channel_set[i].ChannelNum == 11) {
+			if (rfctl->channel_set[i].rx_count < rfctl->channel_set[index_24G].rx_count) {
+				index_24G = i;
+				best_channel_24G = rfctl->channel_set[i].ChannelNum;
+			}
+		}
+
+		/* 5G */
+		if (rfctl->channel_set[i].ChannelNum >= 36
+		    && rfctl->channel_set[i].ChannelNum < 140) {
+			/* Find primary channel */
+			if (((rfctl->channel_set[i].ChannelNum - 36) % 8 == 0)
+			    && (rfctl->channel_set[i].rx_count < rfctl->channel_set[index_5G].rx_count)) {
+				index_5G = i;
+				best_channel_5G = rfctl->channel_set[i].ChannelNum;
+			}
+		}
+
+		if (rfctl->channel_set[i].ChannelNum >= 149
+		    && rfctl->channel_set[i].ChannelNum < 165) {
+			/* Find primary channel */
+			if (((rfctl->channel_set[i].ChannelNum - 149) % 8 == 0)
+			    && (rfctl->channel_set[i].rx_count < rfctl->channel_set[index_5G].rx_count)) {
+				index_5G = i;
+				best_channel_5G = rfctl->channel_set[i].ChannelNum;
+			}
+		}
+#if 1 /* debug */
+		RTW_INFO("The rx cnt of channel %3d = %d\n",
+			 rfctl->channel_set[i].ChannelNum,
+			 rfctl->channel_set[i].rx_count);
+#endif
+	}
+
+	sprintf(extra, "\nbest_channel_24G = %d\n", best_channel_24G);
+	RTW_INFO("best_channel_24G = %d\n", best_channel_24G);
+
+	if (index_5G != 0) {
+		sprintf(extra, "best_channel_5G = %d\n", best_channel_5G);
+		RTW_INFO("best_channel_5G = %d\n", best_channel_5G);
+	}
+
+	wrqu->data.length = strlen(extra);
+
+#endif
+
+	return 0;
+
+}
+
+static int rtw_tdls(struct net_device *dev,
+		    struct iw_request_info *info,
+		    union iwreq_data *wrqu, char *extra)
+{
+	int ret = 0;
+
+#ifdef CONFIG_TDLS
+
+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
+
+	RTW_INFO("[%s] extra = %s\n", __FUNCTION__, extra);
+
+	if (hal_chk_wl_func(padapter, WL_FUNC_TDLS) == _FALSE) {
+		RTW_INFO("Discard tdls oper since hal doesn't support tdls\n");
+		return 0;
+	}
+
+	if (rtw_is_tdls_enabled(padapter) == _FALSE) {
+		RTW_INFO("TDLS is not enabled\n");
+		return 0;
+	}
+
+	/* WFD Sigma will use the tdls enable command to let the driver know we want to test the tdls now! */
+
+	if (hal_chk_wl_func(padapter, WL_FUNC_MIRACAST)) {
+		if (_rtw_memcmp(extra, "wfdenable=", 10)) {
+			wrqu->data.length -= 10;
+			rtw_wx_tdls_wfd_enable(dev, info, wrqu, &extra[10]);
+			return ret;
+		}
+	}
+
+	if (_rtw_memcmp(extra, "weaksec=", 8)) {
+		wrqu->data.length -= 8;
+		rtw_tdls_weaksec(dev, info, wrqu, &extra[8]);
+		return ret;
+	} else if (_rtw_memcmp(extra, "tdlsenable=", 11)) {
+		wrqu->data.length -= 11;
+		rtw_tdls_enable(dev, info, wrqu, &extra[11]);
+		return ret;
+	}
+
+	if (_rtw_memcmp(extra, "setup=", 6)) {
+		wrqu->data.length -= 6;
+		rtw_tdls_setup(dev, info, wrqu, &extra[6]);
+	} else if (_rtw_memcmp(extra, "tear=", 5)) {
+		wrqu->data.length -= 5;
+		rtw_tdls_teardown(dev, info, wrqu, &extra[5]);
+	} else if (_rtw_memcmp(extra, "dis=", 4)) {
+		wrqu->data.length -= 4;
+		rtw_tdls_discovery(dev, info, wrqu, &extra[4]);
+	} else if (_rtw_memcmp(extra, "swoff=", 6)) {
+		wrqu->data.length -= 6;
+		rtw_tdls_ch_switch_off(dev, info, wrqu, &extra[6]);
+	} else if (_rtw_memcmp(extra, "sw=", 3)) {
+		wrqu->data.length -= 3;
+		rtw_tdls_ch_switch(dev, info, wrqu, &extra[3]);
+	} else if (_rtw_memcmp(extra, "dumpstack=", 10)) {
+		wrqu->data.length -= 10;
+		rtw_tdls_dump_ch(dev, info, wrqu, &extra[10]);
+	} else if (_rtw_memcmp(extra, "offchnum=", 9)) {
+		wrqu->data.length -= 9;
+		rtw_tdls_off_ch_num(dev, info, wrqu, &extra[9]);
+	} else if (_rtw_memcmp(extra, "choffset=", 9)) {
+		wrqu->data.length -= 9;
+		rtw_tdls_ch_offset(dev, info, wrqu, &extra[9]);
+	} else if (_rtw_memcmp(extra, "pson=", 5)) {
+		wrqu->data.length -= 5;
+		rtw_tdls_pson(dev, info, wrqu, &extra[5]);
+	} else if (_rtw_memcmp(extra, "psoff=", 6)) {
+		wrqu->data.length -= 6;
+		rtw_tdls_psoff(dev, info, wrqu, &extra[6]);
+	}
+
+#ifdef CONFIG_WFD
+	if (hal_chk_wl_func(padapter, WL_FUNC_MIRACAST)) {
+		if (_rtw_memcmp(extra, "setip=", 6)) {
+			wrqu->data.length -= 6;
+			rtw_tdls_setip(dev, info, wrqu, &extra[6]);
+		} else if (_rtw_memcmp(extra, "tprobe=", 6))
+			issue_tunneled_probe_req((_adapter *)rtw_netdev_priv(dev));
+	}
+#endif /* CONFIG_WFD */
+
+#endif /* CONFIG_TDLS */
+
+	return ret;
+}
+
+
+static int rtw_tdls_get(struct net_device *dev,
+			struct iw_request_info *info,
+			union iwreq_data *wrqu, char *extra)
+{
+	int ret = 0;
+
+#ifdef CONFIG_TDLS
+
+	RTW_INFO("[%s] extra = %s\n", __FUNCTION__, (char *) wrqu->data.pointer);
+
+	if (_rtw_memcmp(wrqu->data.pointer, "ip", 2))
+		rtw_tdls_getip(dev, info, wrqu, extra);
+	else if (_rtw_memcmp(wrqu->data.pointer, "port", 4))
+		rtw_tdls_getport(dev, info, wrqu, extra);
+	/* WFDTDLS, for sigma test */
+	else if (_rtw_memcmp(wrqu->data.pointer, "dis", 3))
+		rtw_tdls_dis_result(dev, info, wrqu, extra);
+	else if (_rtw_memcmp(wrqu->data.pointer, "status", 6))
+		rtw_wfd_tdls_status(dev, info, wrqu, extra);
+	else if (_rtw_memcmp(wrqu->data.pointer, "tdls_sta=", 9))
+		rtw_tdls_getsta(dev, info, wrqu, extra);
+	else if (_rtw_memcmp(wrqu->data.pointer, "best_ch", 7))
+		rtw_tdls_get_best_ch(dev, info, wrqu, extra);
+#endif /* CONFIG_TDLS */
+
+	return ret;
+}
+
+
+
+
+
+#ifdef CONFIG_INTEL_WIDI
+static int rtw_widi_set(struct net_device *dev,
+			struct iw_request_info *info,
+			union iwreq_data *wrqu, char *extra)
+{
+	int ret = 0;
+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
+
+	process_intel_widi_cmd(padapter, extra);
+
+	return ret;
+}
+
+static int rtw_widi_set_probe_request(struct net_device *dev,
+				      struct iw_request_info *info,
+				      union iwreq_data *wrqu, char *extra)
+{
+	int	ret = 0;
+	u8	*pbuf = NULL;
+	_adapter	*padapter = (_adapter *)rtw_netdev_priv(dev);
+
+	pbuf = rtw_malloc(sizeof(l2_msg_t));
+	if (pbuf) {
+		if (copy_from_user(pbuf, wrqu->data.pointer, wrqu->data.length))
+			ret = -EFAULT;
+		/* _rtw_memcpy(pbuf, wrqu->data.pointer, wrqu->data.length); */
+
+		if (wrqu->data.flags == 0)
+			intel_widi_wk_cmd(padapter, INTEL_WIDI_ISSUE_PROB_WK, pbuf, sizeof(l2_msg_t));
+		else if (wrqu->data.flags == 1)
+			rtw_set_wfd_rds_sink_info(padapter, (l2_msg_t *)pbuf);
+	}
+	return ret;
+}
+#endif /* CONFIG_INTEL_WIDI */
+
+#ifdef CONFIG_MAC_LOOPBACK_DRIVER
+
+#if defined(CONFIG_RTL8188E)
+#include <rtl8188e_hal.h>
+extern void rtl8188e_cal_txdesc_chksum(struct tx_desc *ptxdesc);
+#define cal_txdesc_chksum rtl8188e_cal_txdesc_chksum
+#ifdef CONFIG_SDIO_HCI || defined(CONFIG_GSPI_HCI)
+extern void rtl8188es_fill_default_txdesc(struct xmit_frame *pxmitframe, u8 *pbuf);
+#define fill_default_txdesc rtl8188es_fill_default_txdesc
+#endif /* CONFIG_SDIO_HCI */
+#endif /* CONFIG_RTL8188E */
+#if defined(CONFIG_RTL8723B)
+extern void rtl8723b_cal_txdesc_chksum(struct tx_desc *ptxdesc);
+#define cal_txdesc_chksum rtl8723b_cal_txdesc_chksum
+extern void rtl8723b_fill_default_txdesc(struct xmit_frame *pxmitframe, u8 *pbuf);
+#define fill_default_txdesc rtl8723b_fill_default_txdesc
+#endif /* CONFIG_RTL8723B */
+
+#if defined(CONFIG_RTL8703B)
+/* extern void rtl8703b_cal_txdesc_chksum(struct tx_desc *ptxdesc); */
+#define cal_txdesc_chksum rtl8703b_cal_txdesc_chksum
+/* extern void rtl8703b_fill_default_txdesc(struct xmit_frame *pxmitframe, u8 *pbuf); */
+#define fill_default_txdesc rtl8703b_fill_default_txdesc
+#endif /* CONFIG_RTL8703B */
+
+#if defined(CONFIG_RTL8723D)
+/* extern void rtl8723d_cal_txdesc_chksum(struct tx_desc *ptxdesc); */
+#define cal_txdesc_chksum rtl8723d_cal_txdesc_chksum
+/* extern void rtl8723d_fill_default_txdesc(struct xmit_frame *pxmitframe, u8 *pbuf); */
+#define fill_default_txdesc rtl8723d_fill_default_txdesc
+#endif /* CONFIG_RTL8723D */
+
+#if defined(CONFIG_RTL8710B)
+#define cal_txdesc_chksum rtl8710b_cal_txdesc_chksum
+#define fill_default_txdesc rtl8710b_fill_default_txdesc
+#endif /* CONFIG_RTL8710B */
+
+#if defined(CONFIG_RTL8192E)
+extern void rtl8192e_cal_txdesc_chksum(struct tx_desc *ptxdesc);
+#define cal_txdesc_chksum rtl8192e_cal_txdesc_chksum
+#ifdef CONFIG_SDIO_HCI || defined(CONFIG_GSPI_HCI)
+extern void rtl8192es_fill_default_txdesc(struct xmit_frame *pxmitframe, u8 *pbuf);
+#define fill_default_txdesc rtl8192es_fill_default_txdesc
+#endif /* CONFIG_SDIO_HCI */
+#endif /* CONFIG_RTL8192E */
+
+#if defined(CONFIG_RTL8192F)
+/* extern void rtl8192f_cal_txdesc_chksum(struct tx_desc *ptxdesc); */
+#define cal_txdesc_chksum rtl8192f_cal_txdesc_chksum
+/* extern void rtl8192f_fill_default_txdesc(struct xmit_frame *pxmitframe, u8 *pbuf); */
+#define fill_default_txdesc rtl8192f_fill_default_txdesc
+#endif /* CONFIG_RTL8192F */
+
+static s32 initLoopback(PADAPTER padapter)
+{
+	PLOOPBACKDATA ploopback;
+
+
+	if (padapter->ploopback == NULL) {
+		ploopback = (PLOOPBACKDATA)rtw_zmalloc(sizeof(LOOPBACKDATA));
+		if (ploopback == NULL)
+			return -ENOMEM;
+
+		_rtw_init_sema(&ploopback->sema, 0);
+		ploopback->bstop = _TRUE;
+		ploopback->cnt = 0;
+		ploopback->size = 300;
+		_rtw_memset(ploopback->msg, 0, sizeof(ploopback->msg));
+
+		padapter->ploopback = ploopback;
+	}
+
+	return 0;
+}
+
+static void freeLoopback(PADAPTER padapter)
+{
+	PLOOPBACKDATA ploopback;
+
+
+	ploopback = padapter->ploopback;
+	if (ploopback) {
+		rtw_mfree((u8 *)ploopback, sizeof(LOOPBACKDATA));
+		padapter->ploopback = NULL;
+	}
+}
+
+static s32 initpseudoadhoc(PADAPTER padapter)
+{
+	NDIS_802_11_NETWORK_INFRASTRUCTURE networkType;
+	s32 err;
+
+	networkType = Ndis802_11IBSS;
+	err = rtw_set_802_11_infrastructure_mode(padapter, networkType);
+	if (err == _FALSE)
+		return _FAIL;
+
+	err = rtw_setopmode_cmd(padapter, networkType, RTW_CMDF_WAIT_ACK);
+	if (err == _FAIL)
+		return _FAIL;
+
+	return _SUCCESS;
+}
+
+static s32 createpseudoadhoc(PADAPTER padapter)
+{
+	NDIS_802_11_AUTHENTICATION_MODE authmode;
+	struct mlme_priv *pmlmepriv;
+	NDIS_802_11_SSID *passoc_ssid;
+	WLAN_BSSID_EX *pdev_network;
+	u8 *pibss;
+	u8 ssid[] = "pseduo_ad-hoc";
+	s32 err;
+	_irqL irqL;
+
+
+	pmlmepriv = &padapter->mlmepriv;
+
+	authmode = Ndis802_11AuthModeOpen;
+	err = rtw_set_802_11_authentication_mode(padapter, authmode);
+	if (err == _FALSE)
+		return _FAIL;
+
+	passoc_ssid = &pmlmepriv->assoc_ssid;
+	_rtw_memset(passoc_ssid, 0, sizeof(NDIS_802_11_SSID));
+	passoc_ssid->SsidLength = sizeof(ssid) - 1;
+	_rtw_memcpy(passoc_ssid->Ssid, ssid, passoc_ssid->SsidLength);
+
+	pdev_network = &padapter->registrypriv.dev_network;
+	pibss = padapter->registrypriv.dev_network.MacAddress;
+	_rtw_memcpy(&pdev_network->Ssid, passoc_ssid, sizeof(NDIS_802_11_SSID));
+
+	rtw_update_registrypriv_dev_network(padapter);
+	rtw_generate_random_ibss(pibss);
+
+	_enter_critical_bh(&pmlmepriv->lock, &irqL);
+	/*pmlmepriv->fw_state = WIFI_ADHOC_MASTER_STATE;*/
+	init_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE);
+
+	_exit_critical_bh(&pmlmepriv->lock, &irqL);
+
+#if 0
+	err = rtw_create_ibss_cmd(padapter, 0);
+	if (err == _FAIL)
+		return _FAIL;
+#else
+	{
+		struct wlan_network *pcur_network;
+		struct sta_info *psta;
+
+		/* 3  create a new psta */
+		pcur_network = &pmlmepriv->cur_network;
+
+		/* clear psta in the cur_network, if any */
+		psta = rtw_get_stainfo(&padapter->stapriv, pcur_network->network.MacAddress);
+		if (psta)
+			rtw_free_stainfo(padapter, psta);
+
+		psta = rtw_alloc_stainfo(&padapter->stapriv, pibss);
+		if (psta == NULL)
+			return _FAIL;
+
+		/* 3  join psudo AdHoc */
+		pcur_network->join_res = 1;
+		pcur_network->aid = psta->cmn.aid = 1;
+		_rtw_memcpy(&pcur_network->network, pdev_network, get_WLAN_BSSID_EX_sz(pdev_network));
+
+		/* set msr to WIFI_FW_ADHOC_STATE */
+		padapter->hw_port = HW_PORT0;
+		Set_MSR(padapter, WIFI_FW_ADHOC_STATE);
+
+	}
+#endif
+
+	return _SUCCESS;
+}
+
+static struct xmit_frame *createloopbackpkt(PADAPTER padapter, u32 size)
+{
+	struct xmit_priv *pxmitpriv;
+	struct xmit_frame *pframe;
+	struct xmit_buf *pxmitbuf;
+	struct pkt_attrib *pattrib;
+	struct tx_desc *desc;
+	u8 *pkt_start, *pkt_end, *ptr;
+	struct rtw_ieee80211_hdr *hdr;
+	s32 bmcast;
+	_irqL irqL;
+
+
+	if ((TXDESC_SIZE + WLANHDR_OFFSET + size) > MAX_XMITBUF_SZ)
+		return NULL;
+
+	pxmitpriv = &padapter->xmitpriv;
+	pframe = NULL;
+
+	/* 2 1. allocate xmit frame */
+	pframe = rtw_alloc_xmitframe(pxmitpriv);
+	if (pframe == NULL)
+		return NULL;
+	pframe->padapter = padapter;
+
+	/* 2 2. allocate xmit buffer */
+	_enter_critical_bh(&pxmitpriv->lock, &irqL);
+	pxmitbuf = rtw_alloc_xmitbuf(pxmitpriv);
+	_exit_critical_bh(&pxmitpriv->lock, &irqL);
+	if (pxmitbuf == NULL) {
+		rtw_free_xmitframe(pxmitpriv, pframe);
+		return NULL;
+	}
+
+	pframe->pxmitbuf = pxmitbuf;
+	pframe->buf_addr = pxmitbuf->pbuf;
+	pxmitbuf->priv_data = pframe;
+
+	/* 2 3. update_attrib() */
+	pattrib = &pframe->attrib;
+
+	/* init xmitframe attribute */
+	_rtw_memset(pattrib, 0, sizeof(struct pkt_attrib));
+
+	pattrib->ether_type = 0x8723;
+	_rtw_memcpy(pattrib->src, adapter_mac_addr(padapter), ETH_ALEN);
+	_rtw_memcpy(pattrib->ta, pattrib->src, ETH_ALEN);
+	_rtw_memset(pattrib->dst, 0xFF, ETH_ALEN);
+	_rtw_memcpy(pattrib->ra, pattrib->dst, ETH_ALEN);
+
+	/*	pattrib->dhcp_pkt = 0;
+	 *	pattrib->pktlen = 0; */
+	pattrib->ack_policy = 0;
+	/*	pattrib->pkt_hdrlen = ETH_HLEN; */
+	pattrib->hdrlen = WLAN_HDR_A3_LEN;
+	pattrib->subtype = WIFI_DATA;
+	pattrib->priority = 0;
+	pattrib->qsel = pattrib->priority;
+	/*	do_queue_select(padapter, pattrib); */
+	pattrib->nr_frags = 1;
+	pattrib->encrypt = 0;
+	pattrib->bswenc = _FALSE;
+	pattrib->qos_en = _FALSE;
+
+	bmcast = IS_MCAST(pattrib->ra);
+	if (bmcast)
+		pattrib->psta = rtw_get_bcmc_stainfo(padapter);
+	else
+		pattrib->psta = rtw_get_stainfo(&padapter->stapriv, get_bssid(&padapter->mlmepriv));
+
+	pattrib->mac_id = pattrib->psta->cmn.mac_id;
+	pattrib->pktlen = size;
+	pattrib->last_txcmdsz = pattrib->hdrlen + pattrib->pktlen;
+
+	/* 2 4. fill TX descriptor */
+	desc = (struct tx_desc *)pframe->buf_addr;
+	_rtw_memset(desc, 0, TXDESC_SIZE);
+
+	fill_default_txdesc(pframe, (u8 *)desc);
+
+	/* Hw set sequence number */
+	((PTXDESC)desc)->hwseq_en = 0; /* HWSEQ_EN, 0:disable, 1:enable
+ * ((PTXDESC)desc)->hwseq_sel = 0;  */ /* HWSEQ_SEL */
+
+	((PTXDESC)desc)->disdatafb = 1;
+
+	/* convert to little endian */
+	desc->txdw0 = cpu_to_le32(desc->txdw0);
+	desc->txdw1 = cpu_to_le32(desc->txdw1);
+	desc->txdw2 = cpu_to_le32(desc->txdw2);
+	desc->txdw3 = cpu_to_le32(desc->txdw3);
+	desc->txdw4 = cpu_to_le32(desc->txdw4);
+	desc->txdw5 = cpu_to_le32(desc->txdw5);
+	desc->txdw6 = cpu_to_le32(desc->txdw6);
+	desc->txdw7 = cpu_to_le32(desc->txdw7);
+#ifdef CONFIG_PCI_HCI
+	desc->txdw8 = cpu_to_le32(desc->txdw8);
+	desc->txdw9 = cpu_to_le32(desc->txdw9);
+	desc->txdw10 = cpu_to_le32(desc->txdw10);
+	desc->txdw11 = cpu_to_le32(desc->txdw11);
+	desc->txdw12 = cpu_to_le32(desc->txdw12);
+	desc->txdw13 = cpu_to_le32(desc->txdw13);
+	desc->txdw14 = cpu_to_le32(desc->txdw14);
+	desc->txdw15 = cpu_to_le32(desc->txdw15);
+#endif
+
+	cal_txdesc_chksum(desc);
+
+	/* 2 5. coalesce */
+	pkt_start = pframe->buf_addr + TXDESC_SIZE;
+	pkt_end = pkt_start + pattrib->last_txcmdsz;
+
+	/* 3 5.1. make wlan header, make_wlanhdr() */
+	hdr = (struct rtw_ieee80211_hdr *)pkt_start;
+	set_frame_sub_type(&hdr->frame_ctl, pattrib->subtype);
+	_rtw_memcpy(hdr->addr1, pattrib->dst, ETH_ALEN); /* DA */
+	_rtw_memcpy(hdr->addr2, pattrib->src, ETH_ALEN); /* SA */
+	_rtw_memcpy(hdr->addr3, get_bssid(&padapter->mlmepriv), ETH_ALEN); /* RA, BSSID */
+
+	/* 3 5.2. make payload */
+	ptr = pkt_start + pattrib->hdrlen;
+	get_random_bytes(ptr, pkt_end - ptr);
+
+	pxmitbuf->len = TXDESC_SIZE + pattrib->last_txcmdsz;
+	pxmitbuf->ptail += pxmitbuf->len;
+
+	return pframe;
+}
+
+static void freeloopbackpkt(PADAPTER padapter, struct xmit_frame *pframe)
+{
+	struct xmit_priv *pxmitpriv;
+	struct xmit_buf *pxmitbuf;
+
+
+	pxmitpriv = &padapter->xmitpriv;
+	pxmitbuf = pframe->pxmitbuf;
+
+	rtw_free_xmitframe(pxmitpriv, pframe);
+	rtw_free_xmitbuf(pxmitpriv, pxmitbuf);
+}
+
+static void printdata(u8 *pbuf, u32 len)
+{
+	u32 i, val;
+
+
+	for (i = 0; (i + 4) <= len; i += 4) {
+		printk("%08X", *(u32 *)(pbuf + i));
+		if ((i + 4) & 0x1F)
+			printk(" ");
+		else
+			printk("\n");
+	}
+
+	if (i < len) {
+#ifdef CONFIG_BIG_ENDIAN
+		for (; i < len, i++)
+			printk("%02X", pbuf + i);
+#else /* CONFIG_LITTLE_ENDIAN */
+#if 0
+		val = 0;
+		_rtw_memcpy(&val, pbuf + i, len - i);
+		printk("%8X", val);
+#else
+		u8 str[9];
+		u8 n;
+		val = 0;
+		n = len - i;
+		_rtw_memcpy(&val, pbuf + i, n);
+		sprintf(str, "%08X", val);
+		n = (4 - n) * 2;
+		printk("%8s", str + n);
+#endif
+#endif /* CONFIG_LITTLE_ENDIAN */
+	}
+	printk("\n");
+}
+
+static u8 pktcmp(PADAPTER padapter, u8 *txbuf, u32 txsz, u8 *rxbuf, u32 rxsz)
+{
+	PHAL_DATA_TYPE phal;
+	struct recv_stat *prxstat;
+	struct recv_stat report;
+	PRXREPORT prxreport;
+	u32 drvinfosize;
+	u32 rxpktsize;
+	u8 fcssize;
+	u8 ret = _FALSE;
+
+	prxstat = (struct recv_stat *)rxbuf;
+	report.rxdw0 = le32_to_cpu(prxstat->rxdw0);
+	report.rxdw1 = le32_to_cpu(prxstat->rxdw1);
+	report.rxdw2 = le32_to_cpu(prxstat->rxdw2);
+	report.rxdw3 = le32_to_cpu(prxstat->rxdw3);
+	report.rxdw4 = le32_to_cpu(prxstat->rxdw4);
+	report.rxdw5 = le32_to_cpu(prxstat->rxdw5);
+
+	prxreport = (PRXREPORT)&report;
+	drvinfosize = prxreport->drvinfosize << 3;
+	rxpktsize = prxreport->pktlen;
+
+	phal = GET_HAL_DATA(padapter);
+	if (rtw_hal_rcr_check(padapter, RCR_APPFCS))
+		fcssize = IEEE80211_FCS_LEN;
+	else
+		fcssize = 0;
+
+	if ((txsz - TXDESC_SIZE) != (rxpktsize - fcssize)) {
+		RTW_INFO("%s: ERROR! size not match tx/rx=%d/%d !\n",
+			 __func__, txsz - TXDESC_SIZE, rxpktsize - fcssize);
+		ret = _FALSE;
+	} else {
+		ret = _rtw_memcmp(txbuf + TXDESC_SIZE, \
+				  rxbuf + RXDESC_SIZE + drvinfosize, \
+				  txsz - TXDESC_SIZE);
+		if (ret == _FALSE)
+			RTW_INFO("%s: ERROR! pkt content mismatch!\n", __func__);
+	}
+
+	if (ret == _FALSE) {
+		RTW_INFO("\n%s: TX PKT total=%d, desc=%d, content=%d\n",
+			 __func__, txsz, TXDESC_SIZE, txsz - TXDESC_SIZE);
+		RTW_INFO("%s: TX DESC size=%d\n", __func__, TXDESC_SIZE);
+		printdata(txbuf, TXDESC_SIZE);
+		RTW_INFO("%s: TX content size=%d\n", __func__, txsz - TXDESC_SIZE);
+		printdata(txbuf + TXDESC_SIZE, txsz - TXDESC_SIZE);
+
+		RTW_INFO("\n%s: RX PKT read=%d offset=%d(%d,%d) content=%d\n",
+			__func__, rxsz, RXDESC_SIZE + drvinfosize, RXDESC_SIZE, drvinfosize, rxpktsize);
+		if (rxpktsize != 0) {
+			RTW_INFO("%s: RX DESC size=%d\n", __func__, RXDESC_SIZE);
+			printdata(rxbuf, RXDESC_SIZE);
+			RTW_INFO("%s: RX drvinfo size=%d\n", __func__, drvinfosize);
+			printdata(rxbuf + RXDESC_SIZE, drvinfosize);
+			RTW_INFO("%s: RX content size=%d\n", __func__, rxpktsize);
+			printdata(rxbuf + RXDESC_SIZE + drvinfosize, rxpktsize);
+		} else {
+			RTW_INFO("%s: RX data size=%d\n", __func__, rxsz);
+			printdata(rxbuf, rxsz);
+		}
+	}
+
+	return ret;
+}
+
+thread_return lbk_thread(thread_context context)
+{
+	s32 err;
+	PADAPTER padapter;
+	PLOOPBACKDATA ploopback;
+	struct xmit_frame *pxmitframe;
+	u32 cnt, ok, fail, headerlen;
+	u32 pktsize;
+	u32 ff_hwaddr;
+
+
+	padapter = (PADAPTER)context;
+	ploopback = padapter->ploopback;
+	if (ploopback == NULL)
+		return -1;
+	cnt = 0;
+	ok = 0;
+	fail = 0;
+
+	daemonize("%s", "RTW_LBK_THREAD");
+	allow_signal(SIGTERM);
+
+	do {
+		if (ploopback->size == 0) {
+			get_random_bytes(&pktsize, 4);
+			pktsize = (pktsize % 1535) + 1; /* 1~1535 */
+		} else
+			pktsize = ploopback->size;
+
+		pxmitframe = createloopbackpkt(padapter, pktsize);
+		if (pxmitframe == NULL) {
+			sprintf(ploopback->msg, "loopback FAIL! 3. create Packet FAIL!");
+			break;
+		}
+
+		ploopback->txsize = TXDESC_SIZE + pxmitframe->attrib.last_txcmdsz;
+		_rtw_memcpy(ploopback->txbuf, pxmitframe->buf_addr, ploopback->txsize);
+		ff_hwaddr = rtw_get_ff_hwaddr(pxmitframe);
+		cnt++;
+		RTW_INFO("%s: wirte port cnt=%d size=%d\n", __func__, cnt, ploopback->txsize);
+		pxmitframe->pxmitbuf->pdata = ploopback->txbuf;
+		rtw_write_port(padapter, ff_hwaddr, ploopback->txsize, (u8 *)pxmitframe->pxmitbuf);
+
+		/* wait for rx pkt */
+		_rtw_down_sema(&ploopback->sema);
+
+		err = pktcmp(padapter, ploopback->txbuf, ploopback->txsize, ploopback->rxbuf, ploopback->rxsize);
+		if (err == _TRUE)
+			ok++;
+		else
+			fail++;
+
+		ploopback->txsize = 0;
+		_rtw_memset(ploopback->txbuf, 0, 0x8000);
+		ploopback->rxsize = 0;
+		_rtw_memset(ploopback->rxbuf, 0, 0x8000);
+
+		freeloopbackpkt(padapter, pxmitframe);
+		pxmitframe = NULL;
+
+		flush_signals_thread();
+
+		if ((ploopback->bstop == _TRUE) ||
+		    ((ploopback->cnt != 0) && (ploopback->cnt == cnt))) {
+			u32 ok_rate, fail_rate, all;
+			all = cnt;
+			ok_rate = (ok * 100) / all;
+			fail_rate = (fail * 100) / all;
+			sprintf(ploopback->msg, \
+				"loopback result: ok=%d%%(%d/%d),error=%d%%(%d/%d)", \
+				ok_rate, ok, all, fail_rate, fail, all);
+			break;
+		}
+	} while (1);
+
+	ploopback->bstop = _TRUE;
+
+	thread_exit(NULL);
+	return 0;
+}
+
+static void loopbackTest(PADAPTER padapter, u32 cnt, u32 size, u8 *pmsg)
+{
+	PLOOPBACKDATA ploopback;
+	u32 len;
+	s32 err;
+
+
+	ploopback = padapter->ploopback;
+
+	if (ploopback) {
+		if (ploopback->bstop == _FALSE) {
+			ploopback->bstop = _TRUE;
+			_rtw_up_sema(&ploopback->sema);
+		}
+		len = 0;
+		do {
+			len = strlen(ploopback->msg);
+			if (len)
+				break;
+			rtw_msleep_os(1);
+		} while (1);
+		_rtw_memcpy(pmsg, ploopback->msg, len + 1);
+		freeLoopback(padapter);
+
+		return;
+	}
+
+	/* disable dynamic algorithm	 */
+	rtw_phydm_ability_backup(padapter);
+	rtw_phydm_func_disable_all(padapter);
+
+	/* create pseudo ad-hoc connection */
+	err = initpseudoadhoc(padapter);
+	if (err == _FAIL) {
+		sprintf(pmsg, "loopback FAIL! 1.1 init ad-hoc FAIL!");
+		return;
+	}
+
+	err = createpseudoadhoc(padapter);
+	if (err == _FAIL) {
+		sprintf(pmsg, "loopback FAIL! 1.2 create ad-hoc master FAIL!");
+		return;
+	}
+
+	err = initLoopback(padapter);
+	if (err) {
+		sprintf(pmsg, "loopback FAIL! 2. init FAIL! error code=%d", err);
+		return;
+	}
+
+	ploopback = padapter->ploopback;
+
+	ploopback->bstop = _FALSE;
+	ploopback->cnt = cnt;
+	ploopback->size = size;
+	ploopback->lbkthread = kthread_run(lbk_thread, padapter, "RTW_LBK_THREAD");
+	if (IS_ERR(padapter->lbkthread)) {
+		freeLoopback(padapter);
+		ploopback->lbkthread = NULL;
+		sprintf(pmsg, "loopback start FAIL! cnt=%d", cnt);
+		return;
+	}
+
+	sprintf(pmsg, "loopback start! cnt=%d", cnt);
+}
+#endif /* CONFIG_MAC_LOOPBACK_DRIVER */
+
+static int rtw_test(
+	struct net_device *dev,
+	struct iw_request_info *info,
+	union iwreq_data *wrqu, char *extra)
+{
+	u32 len;
+	u8 *pbuf, *pch;
+	char *ptmp;
+	u8 *delim = ",";
+	PADAPTER padapter = rtw_netdev_priv(dev);
+
+
+	RTW_INFO("+%s\n", __func__);
+	len = wrqu->data.length;
+
+	pbuf = (u8 *)rtw_zmalloc(len + 1);
+	if (pbuf == NULL) {
+		RTW_INFO("%s: no memory!\n", __func__);
+		return -ENOMEM;
+	}
+
+	if (copy_from_user(pbuf, wrqu->data.pointer, len)) {
+		rtw_mfree(pbuf, len + 1);
+		RTW_INFO("%s: copy from user fail!\n", __func__);
+		return -EFAULT;
+	}
+
+	pbuf[len] = '\0';
+
+	RTW_INFO("%s: string=\"%s\"\n", __func__, pbuf);
+
+	ptmp = (char *)pbuf;
+	pch = strsep(&ptmp, delim);
+	if ((pch == NULL) || (strlen(pch) == 0)) {
+		rtw_mfree(pbuf, len);
+		RTW_INFO("%s: parameter error(level 1)!\n", __func__);
+		return -EFAULT;
+	}
+
+#ifdef CONFIG_MAC_LOOPBACK_DRIVER
+	if (strcmp(pch, "loopback") == 0) {
+		s32 cnt = 0;
+		u32 size = 64;
+
+		pch = strsep(&ptmp, delim);
+		if ((pch == NULL) || (strlen(pch) == 0)) {
+			rtw_mfree(pbuf, len);
+			RTW_INFO("%s: parameter error(level 2)!\n", __func__);
+			return -EFAULT;
+		}
+
+		sscanf(pch, "%d", &cnt);
+		RTW_INFO("%s: loopback cnt=%d\n", __func__, cnt);
+
+		pch = strsep(&ptmp, delim);
+		if ((pch == NULL) || (strlen(pch) == 0)) {
+			rtw_mfree(pbuf, len);
+			RTW_INFO("%s: parameter error(level 2)!\n", __func__);
+			return -EFAULT;
+		}
+
+		sscanf(pch, "%d", &size);
+		RTW_INFO("%s: loopback size=%d\n", __func__, size);
+
+		loopbackTest(padapter, cnt, size, extra);
+		wrqu->data.length = strlen(extra) + 1;
+
+		goto free_buf;
+	}
+#endif
+
+
+#ifdef CONFIG_BT_COEXIST
+	if (strcmp(pch, "bton") == 0) {
+		rtw_btcoex_SetManualControl(padapter, _FALSE);
+		goto free_buf;
+	} else if (strcmp(pch, "btoff") == 0) {
+		rtw_btcoex_SetManualControl(padapter, _TRUE);
+		goto free_buf;
+	}
+#endif
+
+	if (strcmp(pch, "h2c") == 0) {
+		u8 param[8];
+		u8 count = 0;
+		u32 tmp;
+		u8 i;
+		u32 pos;
+		u8 ret;
+
+		do {
+			pch = strsep(&ptmp, delim);
+			if ((pch == NULL) || (strlen(pch) == 0))
+				break;
+
+			sscanf(pch, "%x", &tmp);
+			param[count++] = (u8)tmp;
+		} while (count < 8);
+
+		if (count == 0) {
+			rtw_mfree(pbuf, len);
+			RTW_INFO("%s: parameter error(level 2)!\n", __func__);
+			return -EFAULT;
+		}
+
+		ret = rtw_test_h2c_cmd(padapter, param, count);
+
+		pos = sprintf(extra, "H2C ID=0x%02x content=", param[0]);
+		for (i = 1; i < count; i++)
+			pos += sprintf(extra + pos, "%02x,", param[i]);
+		extra[pos] = 0;
+		pos--;
+		pos += sprintf(extra + pos, " %s", ret == _FAIL ? "FAIL" : "OK");
+
+		wrqu->data.length = strlen(extra) + 1;
+
+		goto free_buf;
+	}
+
+free_buf:
+	rtw_mfree(pbuf, len);
+	return 0;
+}
+
+static iw_handler rtw_handlers[] = {
+	NULL,					/* SIOCSIWCOMMIT */
+	rtw_wx_get_name,		/* SIOCGIWNAME */
+	dummy,					/* SIOCSIWNWID */
+	dummy,					/* SIOCGIWNWID */
+	rtw_wx_set_freq,		/* SIOCSIWFREQ */
+	rtw_wx_get_freq,		/* SIOCGIWFREQ */
+	rtw_wx_set_mode,		/* SIOCSIWMODE */
+	rtw_wx_get_mode,		/* SIOCGIWMODE */
+	dummy,					/* SIOCSIWSENS */
+	rtw_wx_get_sens,		/* SIOCGIWSENS */
+	NULL,					/* SIOCSIWRANGE */
+	rtw_wx_get_range,		/* SIOCGIWRANGE */
+	rtw_wx_set_priv,		/* SIOCSIWPRIV */
+	NULL,					/* SIOCGIWPRIV */
+	NULL,					/* SIOCSIWSTATS */
+	NULL,					/* SIOCGIWSTATS */
+	dummy,					/* SIOCSIWSPY */
+	dummy,					/* SIOCGIWSPY */
+	NULL,					/* SIOCGIWTHRSPY */
+	NULL,					/* SIOCWIWTHRSPY */
+	rtw_wx_set_wap,		/* SIOCSIWAP */
+	rtw_wx_get_wap,		/* SIOCGIWAP */
+	rtw_wx_set_mlme,		/* request MLME operation; uses struct iw_mlme */
+	dummy,					/* SIOCGIWAPLIST -- depricated */
+	rtw_wx_set_scan,		/* SIOCSIWSCAN */
+	rtw_wx_get_scan,		/* SIOCGIWSCAN */
+	rtw_wx_set_essid,		/* SIOCSIWESSID */
+	rtw_wx_get_essid,		/* SIOCGIWESSID */
+	dummy,					/* SIOCSIWNICKN */
+	rtw_wx_get_nick,		/* SIOCGIWNICKN */
+	NULL,					/* -- hole -- */
+	NULL,					/* -- hole -- */
+	rtw_wx_set_rate,		/* SIOCSIWRATE */
+	rtw_wx_get_rate,		/* SIOCGIWRATE */
+	rtw_wx_set_rts,			/* SIOCSIWRTS */
+	rtw_wx_get_rts,			/* SIOCGIWRTS */
+	rtw_wx_set_frag,		/* SIOCSIWFRAG */
+	rtw_wx_get_frag,		/* SIOCGIWFRAG */
+	dummy,					/* SIOCSIWTXPOW */
+	dummy,					/* SIOCGIWTXPOW */
+	dummy,					/* SIOCSIWRETRY */
+	rtw_wx_get_retry,		/* SIOCGIWRETRY */
+	rtw_wx_set_enc,			/* SIOCSIWENCODE */
+	rtw_wx_get_enc,			/* SIOCGIWENCODE */
+	dummy,					/* SIOCSIWPOWER */
+	rtw_wx_get_power,		/* SIOCGIWPOWER */
+	NULL,					/*---hole---*/
+	NULL,					/*---hole---*/
+	rtw_wx_set_gen_ie,		/* SIOCSIWGENIE */
+	NULL,					/* SIOCGWGENIE */
+	rtw_wx_set_auth,		/* SIOCSIWAUTH */
+	NULL,					/* SIOCGIWAUTH */
+	rtw_wx_set_enc_ext,		/* SIOCSIWENCODEEXT */
+	NULL,					/* SIOCGIWENCODEEXT */
+	rtw_wx_set_pmkid,		/* SIOCSIWPMKSA */
+	NULL,					/*---hole---*/
+};
+
+
+static const struct iw_priv_args rtw_private_args[] = {
+	{
+		SIOCIWFIRSTPRIV + 0x0,
+		IW_PRIV_TYPE_CHAR | 0x7FF, 0, "write"
+	},
+	{
+		SIOCIWFIRSTPRIV + 0x1,
+		IW_PRIV_TYPE_CHAR | 0x7FF,
+		IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_FIXED | IFNAMSIZ, "read"
+	},
+	{
+		SIOCIWFIRSTPRIV + 0x2, 0, 0, "driver_ext"
+	},
+	{
+		SIOCIWFIRSTPRIV + 0x3, 0, 0, "mp_ioctl"
+	},
+	{
+		SIOCIWFIRSTPRIV + 0x4,
+		IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 1, 0, "apinfo"
+	},
+	{
+		SIOCIWFIRSTPRIV + 0x5,
+		IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 2, 0, "setpid"
+	},
+	{
+		SIOCIWFIRSTPRIV + 0x6,
+		IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 1, 0, "wps_start"
+	},
+	/* for PLATFORM_MT53XX	 */
+	{
+		SIOCIWFIRSTPRIV + 0x7,
+		IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 1, 0, "get_sensitivity"
+	},
+	{
+		SIOCIWFIRSTPRIV + 0x8,
+		IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 1, 0, "wps_prob_req_ie"
+	},
+	{
+		SIOCIWFIRSTPRIV + 0x9,
+		IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 1, 0, "wps_assoc_req_ie"
+	},
+
+	/* for RTK_DMP_PLATFORM	 */
+	{
+		SIOCIWFIRSTPRIV + 0xA,
+		IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 1, 0, "channel_plan"
+	},
+
+	{
+		SIOCIWFIRSTPRIV + 0xB,
+		IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 2, 0, "dbg"
+	},
+	{
+		SIOCIWFIRSTPRIV + 0xC,
+		IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 3, 0, "rfw"
+	},
+	{
+		SIOCIWFIRSTPRIV + 0xD,
+		IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 2, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_FIXED | IFNAMSIZ, "rfr"
+	},
+#if 0
+	{
+		SIOCIWFIRSTPRIV + 0xE, 0, 0, "wowlan_ctrl"
+	},
+#endif
+	{
+		SIOCIWFIRSTPRIV + 0x10,
+		IW_PRIV_TYPE_CHAR | 1024, 0, "p2p_set"
+	},
+	{
+		SIOCIWFIRSTPRIV + 0x11,
+		IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK , "p2p_get"
+	},
+	{
+		SIOCIWFIRSTPRIV + 0x12, 0, 0, "NULL"
+	},
+	{
+		SIOCIWFIRSTPRIV + 0x13,
+		IW_PRIV_TYPE_CHAR | 64, IW_PRIV_TYPE_CHAR | 64 , "p2p_get2"
+	},
+	{
+		SIOCIWFIRSTPRIV + 0x14,
+		IW_PRIV_TYPE_CHAR  | 64, 0, "tdls"
+	},
+	{
+		SIOCIWFIRSTPRIV + 0x15,
+		IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | 1024 , "tdls_get"
+	},
+	{
+		SIOCIWFIRSTPRIV + 0x16,
+		IW_PRIV_TYPE_CHAR | 64, 0, "pm_set"
+	},
+#ifdef CONFIG_RTW_80211K
+	{
+		SIOCIWFIRSTPRIV + 0x17,
+		IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | 1024 , "rrm"
+	},
+#endif
+	{SIOCIWFIRSTPRIV + 0x18, IW_PRIV_TYPE_CHAR | IFNAMSIZ , 0 , "rereg_nd_name"},
+#ifdef CONFIG_MP_INCLUDED
+	{SIOCIWFIRSTPRIV + 0x1A, IW_PRIV_TYPE_CHAR | 1024, 0,  "NULL"},
+	{SIOCIWFIRSTPRIV + 0x1B, IW_PRIV_TYPE_CHAR | 128, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "NULL"},
+#else
+	{SIOCIWFIRSTPRIV + 0x1A, IW_PRIV_TYPE_CHAR | 1024, 0,  "NULL"},
+	{SIOCIWFIRSTPRIV + 0x1B, IW_PRIV_TYPE_CHAR | 128, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "efuse_get"},
+#endif
+	{
+		SIOCIWFIRSTPRIV + 0x1D,
+		IW_PRIV_TYPE_CHAR | 40, IW_PRIV_TYPE_CHAR | 0x7FF, "test"
+	},
+
+#ifdef CONFIG_INTEL_WIDI
+	{
+		SIOCIWFIRSTPRIV + 0x1E,
+		IW_PRIV_TYPE_CHAR | 1024, 0, "widi_set"
+	},
+	{
+		SIOCIWFIRSTPRIV + 0x1F,
+		IW_PRIV_TYPE_CHAR | 128, 0, "widi_prob_req"
+	},
+#endif /* CONFIG_INTEL_WIDI */
+
+	{ SIOCIWFIRSTPRIV + 0x0E, IW_PRIV_TYPE_CHAR | 1024, 0 , ""},  /* set  */
+	{ SIOCIWFIRSTPRIV + 0x0F, IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK , ""},/* get
+ * --- sub-ioctls definitions --- */
+
+#ifdef CONFIG_APPEND_VENDOR_IE_ENABLE
+	{ VENDOR_IE_SET, IW_PRIV_TYPE_CHAR | 1024 , 0 , "vendor_ie_set" },
+	{ VENDOR_IE_GET, IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "vendor_ie_get" },
+#endif
+#if defined(CONFIG_RTL8723B)
+	{ MP_SetBT, IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_setbt" },
+	{ MP_DISABLE_BT_COEXIST, IW_PRIV_TYPE_CHAR | 1024, 0, "mp_disa_btcoex"},
+#endif
+#ifdef CONFIG_WOWLAN
+	{ MP_WOW_ENABLE , IW_PRIV_TYPE_CHAR | 1024, 0, "wow_mode" },
+	{ MP_WOW_SET_PATTERN , IW_PRIV_TYPE_CHAR | 1024, 0, "wow_set_pattern" },
+#endif
+#ifdef CONFIG_AP_WOWLAN
+	{ MP_AP_WOW_ENABLE , IW_PRIV_TYPE_CHAR | 1024, 0, "ap_wow_mode" }, /* set  */
+#endif
+#ifdef CONFIG_SDIO_INDIRECT_ACCESS
+	{ MP_SD_IREAD, IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "sd_iread" },
+	{ MP_SD_IWRITE, IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "sd_iwrite" },
+#endif
+};
+
+
+static const struct iw_priv_args rtw_mp_private_args[] = {
+	/* --- sub-ioctls definitions --- */
+#ifdef CONFIG_MP_INCLUDED
+	{ MP_START , IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_start" },
+	{ MP_PHYPARA, IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_phypara" },
+	{ MP_STOP , IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_stop" },
+	{ MP_CHANNEL , IW_PRIV_TYPE_CHAR | 1024 , IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_channel" },
+	{ MP_CHL_OFFSET , IW_PRIV_TYPE_CHAR | 1024 , IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_ch_offset" },
+	{ MP_BANDWIDTH , IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_bandwidth"},
+	{ MP_RATE , IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_rate" },
+	{ MP_RESET_STATS , IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_reset_stats"},
+	{ MP_QUERY , IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK , "mp_query"},
+	{ READ_REG , IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "read_reg" },
+	{ MP_RATE , IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_rate" },
+	{ READ_RF , IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "read_rf" },
+	{ MP_PSD , IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_psd"},
+	{ MP_DUMP, IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_dump" },
+	{ MP_TXPOWER , IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_txpower"},
+	{ MP_ANT_TX , IW_PRIV_TYPE_CHAR | 1024,  IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_ant_tx"},
+	{ MP_ANT_RX , IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_ant_rx"},
+	{ WRITE_REG , IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "write_reg" },
+	{ WRITE_RF , IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "write_rf" },
+	{ MP_CTX , IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_ctx"},
+	{ MP_ARX , IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_arx"},
+	{ MP_THER , IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_ther"},
+	{ EFUSE_SET, IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "efuse_set" },
+	{ EFUSE_GET, IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "efuse_get" },
+	{ MP_PWRTRK , IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_pwrtrk"},
+	{ MP_QueryDrvStats, IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_drvquery" },
+	{ MP_IOCTL, IW_PRIV_TYPE_CHAR | 1024, 0, "mp_ioctl"},
+	{ MP_SetRFPathSwh, IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_setrfpath" },
+	{ MP_PwrCtlDM, IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_pwrctldm" },
+	{ MP_GET_TXPOWER_INX, IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_get_txpower" },
+	{ MP_GETVER, IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_priv_ver" },
+	{ MP_MON, IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_mon" },
+	{ EFUSE_MASK, IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "efuse_mask" },
+	{ EFUSE_FILE, IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "efuse_file" },
+	{ MP_TX, IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_tx" },
+	{ MP_RX, IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_rx" },
+	{ MP_HW_TX_MODE, IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_hxtx" },
+	{ MP_PWRLMT, IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_pwrlmt" },
+	{ MP_PWRBYRATE, IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_pwrbyrate" },
+	{ CTA_TEST, IW_PRIV_TYPE_CHAR | 1024, 0, "cta_test"},
+	{ MP_IQK, IW_PRIV_TYPE_CHAR | 1024, 0, "mp_iqk"},
+	{ MP_LCK, IW_PRIV_TYPE_CHAR | 1024, 0, "mp_lck"},
+	{ BT_EFUSE_FILE, IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "bt_efuse_file" },
+	{ MP_SWRFPath, IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_swrfpath" },
+#ifdef CONFIG_RTW_CUSTOMER_STR
+	{ MP_CUSTOMER_STR, IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "customer_str" },
+#endif
+
+#endif /* CONFIG_MP_INCLUDED */
+};
+
+static iw_handler rtw_private_handler[] = {
+	rtw_wx_write32,					/* 0x00 */
+	rtw_wx_read32,					/* 0x01 */
+	NULL,					/* 0x02 */
+#ifdef MP_IOCTL_HDL
+	rtw_mp_ioctl_hdl,				/* 0x03 */
+#else
+	rtw_wx_priv_null,
+#endif
+	/* for MM DTV platform */
+	rtw_get_ap_info,					/* 0x04 */
+
+	rtw_set_pid,						/* 0x05 */
+	rtw_wps_start,					/* 0x06 */
+
+	/* for PLATFORM_MT53XX */
+	rtw_wx_get_sensitivity,			/* 0x07 */
+	rtw_wx_set_mtk_wps_probe_ie,	/* 0x08 */
+	rtw_wx_set_mtk_wps_ie,			/* 0x09 */
+
+	/* for RTK_DMP_PLATFORM
+	 * Set Channel depend on the country code */
+	rtw_wx_set_channel_plan,		/* 0x0A */
+
+	rtw_dbg_port,					/* 0x0B */
+	rtw_wx_write_rf,					/* 0x0C */
+	rtw_wx_read_rf,					/* 0x0D */
+
+	rtw_priv_set,					/*0x0E*/
+	rtw_priv_get,					/*0x0F*/
+
+	rtw_p2p_set,					/* 0x10 */
+	rtw_p2p_get,					/* 0x11 */
+	NULL,							/* 0x12 */
+	rtw_p2p_get2,					/* 0x13 */
+
+	rtw_tdls,						/* 0x14 */
+	rtw_tdls_get,					/* 0x15 */
+
+	rtw_pm_set,						/* 0x16 */
+#ifdef CONFIG_RTW_80211K
+	rtw_wx_priv_rrm,				/* 0x17 */
+#else
+	rtw_wx_priv_null,				/* 0x17 */
+#endif
+	rtw_rereg_nd_name,				/* 0x18 */
+	rtw_wx_priv_null,				/* 0x19 */
+#ifdef CONFIG_MP_INCLUDED
+	rtw_wx_priv_null,				/* 0x1A */
+	rtw_wx_priv_null,				/* 0x1B */
+#else
+	rtw_wx_priv_null,				/* 0x1A */
+	rtw_mp_efuse_get,				/* 0x1B */
+#endif
+	NULL,							/* 0x1C is reserved for hostapd */
+	rtw_test,						/* 0x1D */
+#ifdef CONFIG_INTEL_WIDI
+	rtw_widi_set,					/* 0x1E */
+	rtw_widi_set_probe_request,		/* 0x1F */
+#endif /* CONFIG_INTEL_WIDI */
+};
+
+#if WIRELESS_EXT >= 17
+static struct iw_statistics *rtw_get_wireless_stats(struct net_device *dev)
+{
+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
+	struct iw_statistics *piwstats = &padapter->iwstats;
+	int tmp_level = 0;
+	int tmp_qual = 0;
+	int tmp_noise = 0;
+
+	if (check_fwstate(&padapter->mlmepriv, _FW_LINKED) != _TRUE) {
+		piwstats->qual.qual = 0;
+		piwstats->qual.level = 0;
+		piwstats->qual.noise = 0;
+		/* RTW_INFO("No link  level:%d, qual:%d, noise:%d\n", tmp_level, tmp_qual, tmp_noise); */
+	} else {
+#ifdef CONFIG_SIGNAL_DISPLAY_DBM
+		tmp_level = translate_percentage_to_dbm(padapter->recvpriv.signal_strength);
+#else
+		tmp_level = padapter->recvpriv.signal_strength;
+#endif
+
+		tmp_qual = padapter->recvpriv.signal_qual;
+		#ifdef CONFIG_BACKGROUND_NOISE_MONITOR
+		if (IS_NM_ENABLE(padapter)) {
+			tmp_noise = rtw_noise_measure_curchan(padapter);
+			#ifndef CONFIG_SIGNAL_DISPLAY_DBM
+			tmp_noise = translate_dbm_to_percentage(tmp_noise);/*percentage*/
+			#endif
+		}
+		#endif
+		/* RTW_INFO("level:%d, qual:%d, noise:%d, rssi (%d)\n", tmp_level, tmp_qual, tmp_noise,padapter->recvpriv.rssi); */
+
+		piwstats->qual.level = tmp_level;
+		piwstats->qual.qual = tmp_qual;
+		piwstats->qual.noise = tmp_noise;
+	}
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 14))
+	piwstats->qual.updated = IW_QUAL_ALL_UPDATED ;/* |IW_QUAL_DBM; */
+#else
+#ifdef RTK_DMP_PLATFORM
+	/* IW_QUAL_DBM= 0x8, if driver use this flag, wireless extension will show value of dbm. */
+	/* remove this flag for show percentage 0~100 */
+	piwstats->qual.updated = 0x07;
+#else
+	piwstats->qual.updated = 0x0f;
+#endif
+#endif
+
+#ifdef CONFIG_SIGNAL_DISPLAY_DBM
+	piwstats->qual.updated = piwstats->qual.updated | IW_QUAL_DBM;
+#endif
+
+	return &padapter->iwstats;
+}
+#endif
+
+#ifdef CONFIG_WIRELESS_EXT
+struct iw_handler_def rtw_handlers_def = {
+	.standard = rtw_handlers,
+	.num_standard = sizeof(rtw_handlers) / sizeof(iw_handler),
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 33)) || defined(CONFIG_WEXT_PRIV)
+	.private = rtw_private_handler,
+	.private_args = (struct iw_priv_args *)rtw_private_args,
+	.num_private = sizeof(rtw_private_handler) / sizeof(iw_handler),
+	.num_private_args = sizeof(rtw_private_args) / sizeof(struct iw_priv_args),
+#endif
+#if WIRELESS_EXT >= 17
+	.get_wireless_stats = rtw_get_wireless_stats,
+#endif
+};
+#endif
+
+/* copy from net/wireless/wext.c start
+ * ----------------------------------------------------------------
+ *
+ * Calculate size of private arguments
+ */
+static const char iw_priv_type_size[] = {
+	0,                              /* IW_PRIV_TYPE_NONE */
+	1,                              /* IW_PRIV_TYPE_BYTE */
+	1,                              /* IW_PRIV_TYPE_CHAR */
+	0,                              /* Not defined */
+	sizeof(__u32),                  /* IW_PRIV_TYPE_INT */
+	sizeof(struct iw_freq),         /* IW_PRIV_TYPE_FLOAT */
+	sizeof(struct sockaddr),        /* IW_PRIV_TYPE_ADDR */
+	0,                              /* Not defined */
+};
+
+static int get_priv_size(__u16 args)
+{
+	int num = args & IW_PRIV_SIZE_MASK;
+	int type = (args & IW_PRIV_TYPE_MASK) >> 12;
+
+	return num * iw_priv_type_size[type];
+}
+/* copy from net/wireless/wext.c end */
+
+
+static int _rtw_ioctl_wext_private(struct net_device *dev, union iwreq_data *wrq_data)
+{
+	int err = 0;
+	u8 *input = NULL;
+	u32 input_len = 0;
+	const char delim[] = " ";
+	u8 *output = NULL;
+	u32 output_len = 0;
+	u32 count = 0;
+	u8 *buffer = NULL;
+	u32 buffer_len = 0;
+	char *ptr = NULL;
+	u8 cmdname[17] = {0}; /* IFNAMSIZ+1 */
+	u32 cmdlen;
+	s32 len;
+	u8 *extra = NULL;
+	u32 extra_size = 0;
+
+	s32 k;
+	const iw_handler *priv;		/* Private ioctl */
+	const struct iw_priv_args *priv_args;	/* Private ioctl description */
+	const struct iw_priv_args *mp_priv_args;	/*MP Private ioctl description */
+	const struct iw_priv_args *sel_priv_args;	/*Selected Private ioctl description */
+	u32 num_priv;				/* Number of ioctl */
+	u32 num_priv_args;			/* Number of descriptions */
+	u32 num_mp_priv_args;			/*Number of MP descriptions */
+	u32 num_sel_priv_args;			/*Number of Selected descriptions */
+	iw_handler handler;
+	int temp;
+	int subcmd = 0;				/* sub-ioctl index */
+	int offset = 0;				/* Space for sub-ioctl index */
+
+	union iwreq_data wdata;
+
+	_rtw_memcpy(&wdata, wrq_data, sizeof(wdata));
+
+	input_len = wdata.data.length;
+	if (!input_len)
+		return -EINVAL;
+	input = rtw_zmalloc(input_len);
+	if (NULL == input)
+		return -ENOMEM;
+	if (copy_from_user(input, wdata.data.pointer, input_len)) {
+		err = -EFAULT;
+		goto exit;
+	}
+	input[input_len - 1] = '\0';
+	ptr = input;
+	len = input_len;
+
+	if (ptr == NULL) {
+		err = -EOPNOTSUPP;
+		goto exit;
+	}
+
+	sscanf(ptr, "%16s", cmdname);
+	cmdlen = strlen(cmdname);
+	RTW_INFO("%s: cmd=%s\n", __func__, cmdname);
+
+	/* skip command string */
+	if (cmdlen > 0)
+		cmdlen += 1; /* skip one space */
+	ptr += cmdlen;
+	len -= cmdlen;
+	RTW_INFO("%s: parameters=%s\n", __func__, ptr);
+
+	priv = rtw_private_handler;
+	priv_args = rtw_private_args;
+	mp_priv_args = rtw_mp_private_args;
+	num_priv = sizeof(rtw_private_handler) / sizeof(iw_handler);
+	num_priv_args = sizeof(rtw_private_args) / sizeof(struct iw_priv_args);
+	num_mp_priv_args = sizeof(rtw_mp_private_args) / sizeof(struct iw_priv_args);
+
+	if (num_priv_args == 0) {
+		err = -EOPNOTSUPP;
+		goto exit;
+	}
+
+	/* Search the correct ioctl */
+	k = -1;
+	sel_priv_args = priv_args;
+	num_sel_priv_args = num_priv_args;
+	while
+	((++k < num_sel_priv_args) && strcmp(sel_priv_args[k].name, cmdname))
+		;
+
+	/* If not found... */
+	if (k == num_sel_priv_args) {
+		k = -1;
+		sel_priv_args = mp_priv_args;
+		num_sel_priv_args = num_mp_priv_args;
+		while
+		((++k < num_sel_priv_args) && strcmp(sel_priv_args[k].name, cmdname))
+			;
+
+		if (k == num_sel_priv_args) {
+			err = -EOPNOTSUPP;
+			goto exit;
+		}
+	}
+
+	/* Watch out for sub-ioctls ! */
+	if (sel_priv_args[k].cmd < SIOCDEVPRIVATE) {
+		int j = -1;
+
+		/* Find the matching *real* ioctl */
+		while ((++j < num_priv_args) && ((priv_args[j].name[0] != '\0') ||
+			 (priv_args[j].set_args != sel_priv_args[k].set_args) ||
+			 (priv_args[j].get_args != sel_priv_args[k].get_args)))
+			;
+
+		/* If not found... */
+		if (j == num_priv_args) {
+			err = -EINVAL;
+			goto exit;
+		}
+
+		/* Save sub-ioctl number */
+		subcmd = sel_priv_args[k].cmd;
+		/* Reserve one int (simplify alignment issues) */
+		offset = sizeof(__u32);
+		/* Use real ioctl definition from now on */
+		k = j;
+	}
+
+	buffer = rtw_zmalloc(4096);
+	if (NULL == buffer) {
+		err = -ENOMEM;
+		goto exit;
+	}
+
+	if (k >= num_priv_args) {
+		err = -EINVAL;
+		goto exit;
+	}
+
+	/* If we have to set some data */
+	if ((priv_args[k].set_args & IW_PRIV_TYPE_MASK) &&
+	    (priv_args[k].set_args & IW_PRIV_SIZE_MASK)) {
+		u8 *str;
+
+		switch (priv_args[k].set_args & IW_PRIV_TYPE_MASK) {
+		case IW_PRIV_TYPE_BYTE:
+			/* Fetch args */
+			count = 0;
+			do {
+				str = strsep(&ptr, delim);
+				if (NULL == str)
+					break;
+				sscanf(str, "%i", &temp);
+				buffer[count++] = (u8)temp;
+			} while (1);
+			buffer_len = count;
+
+			/* Number of args to fetch */
+			wdata.data.length = count;
+			if (wdata.data.length > (priv_args[k].set_args & IW_PRIV_SIZE_MASK))
+				wdata.data.length = priv_args[k].set_args & IW_PRIV_SIZE_MASK;
+
+			break;
+
+		case IW_PRIV_TYPE_INT:
+			/* Fetch args */
+			count = 0;
+			do {
+				str = strsep(&ptr, delim);
+				if (NULL == str)
+					break;
+				sscanf(str, "%i", &temp);
+				((s32 *)buffer)[count++] = (s32)temp;
+			} while (1);
+			buffer_len = count * sizeof(s32);
+
+			/* Number of args to fetch */
+			wdata.data.length = count;
+			if (wdata.data.length > (priv_args[k].set_args & IW_PRIV_SIZE_MASK))
+				wdata.data.length = priv_args[k].set_args & IW_PRIV_SIZE_MASK;
+
+			break;
+
+		case IW_PRIV_TYPE_CHAR:
+			if (len > 0) {
+				/* Size of the string to fetch */
+				wdata.data.length = len;
+				if (wdata.data.length > (priv_args[k].set_args & IW_PRIV_SIZE_MASK))
+					wdata.data.length = priv_args[k].set_args & IW_PRIV_SIZE_MASK;
+
+				/* Fetch string */
+				_rtw_memcpy(buffer, ptr, wdata.data.length);
+			} else {
+				wdata.data.length = 1;
+				buffer[0] = '\0';
+			}
+			buffer_len = wdata.data.length;
+			break;
+
+		default:
+			RTW_INFO("%s: Not yet implemented...\n", __func__);
+			err = -1;
+			goto exit;
+		}
+
+		if ((priv_args[k].set_args & IW_PRIV_SIZE_FIXED) &&
+		    (wdata.data.length != (priv_args[k].set_args & IW_PRIV_SIZE_MASK))) {
+			RTW_INFO("%s: The command %s needs exactly %d argument(s)...\n",
+				__func__, cmdname, priv_args[k].set_args & IW_PRIV_SIZE_MASK);
+			err = -EINVAL;
+			goto exit;
+		}
+	}   /* if args to set */
+	else
+		wdata.data.length = 0L;
+
+	/* Those two tests are important. They define how the driver
+	* will have to handle the data */
+	if ((priv_args[k].set_args & IW_PRIV_SIZE_FIXED) &&
+	    ((get_priv_size(priv_args[k].set_args) + offset) <= IFNAMSIZ)) {
+		/* First case : all SET args fit within wrq */
+		if (offset)
+			wdata.mode = subcmd;
+		_rtw_memcpy(wdata.name + offset, buffer, IFNAMSIZ - offset);
+	} else {
+		if ((priv_args[k].set_args == 0) &&
+		    (priv_args[k].get_args & IW_PRIV_SIZE_FIXED) &&
+		    (get_priv_size(priv_args[k].get_args) <= IFNAMSIZ)) {
+			/* Second case : no SET args, GET args fit within wrq */
+			if (offset)
+				wdata.mode = subcmd;
+		} else {
+			/* Third case : args won't fit in wrq, or variable number of args */
+			if (copy_to_user(wdata.data.pointer, buffer, buffer_len)) {
+				err = -EFAULT;
+				goto exit;
+			}
+			wdata.data.flags = subcmd;
+		}
+	}
+
+	rtw_mfree(input, input_len);
+	input = NULL;
+
+	extra_size = 0;
+	if (IW_IS_SET(priv_args[k].cmd)) {
+		/* Size of set arguments */
+		extra_size = get_priv_size(priv_args[k].set_args);
+
+		/* Does it fits in iwr ? */
+		if ((priv_args[k].set_args & IW_PRIV_SIZE_FIXED) &&
+		    ((extra_size + offset) <= IFNAMSIZ))
+			extra_size = 0;
+	} else {
+		/* Size of get arguments */
+		extra_size = get_priv_size(priv_args[k].get_args);
+
+		/* Does it fits in iwr ? */
+		if ((priv_args[k].get_args & IW_PRIV_SIZE_FIXED) &&
+		    (extra_size <= IFNAMSIZ))
+			extra_size = 0;
+	}
+
+	if (extra_size == 0) {
+		extra = (u8 *)&wdata;
+		rtw_mfree(buffer, 4096);
+		buffer = NULL;
+	} else
+		extra = buffer;
+
+	handler = priv[priv_args[k].cmd - SIOCIWFIRSTPRIV];
+	err = handler(dev, NULL, &wdata, extra);
+
+	/* If we have to get some data */
+	if ((priv_args[k].get_args & IW_PRIV_TYPE_MASK) &&
+	    (priv_args[k].get_args & IW_PRIV_SIZE_MASK)) {
+		int j;
+		int n = 0;	/* number of args */
+		u8 str[20] = {0};
+
+		/* Check where is the returned data */
+		if ((priv_args[k].get_args & IW_PRIV_SIZE_FIXED) &&
+		    (get_priv_size(priv_args[k].get_args) <= IFNAMSIZ))
+			n = priv_args[k].get_args & IW_PRIV_SIZE_MASK;
+		else
+			n = wdata.data.length;
+
+		output = rtw_zmalloc(4096);
+		if (NULL == output) {
+			err =  -ENOMEM;
+			goto exit;
+		}
+
+		switch (priv_args[k].get_args & IW_PRIV_TYPE_MASK) {
+		case IW_PRIV_TYPE_BYTE:
+			/* Display args */
+			for (j = 0; j < n; j++) {
+				sprintf(str, "%d  ", extra[j]);
+				len = strlen(str);
+				output_len = strlen(output);
+				if ((output_len + len + 1) > 4096) {
+					err = -E2BIG;
+					goto exit;
+				}
+				_rtw_memcpy(output + output_len, str, len);
+			}
+			break;
+
+		case IW_PRIV_TYPE_INT:
+			/* Display args */
+			for (j = 0; j < n; j++) {
+				sprintf(str, "%d  ", ((__s32 *)extra)[j]);
+				len = strlen(str);
+				output_len = strlen(output);
+				if ((output_len + len + 1) > 4096) {
+					err = -E2BIG;
+					goto exit;
+				}
+				_rtw_memcpy(output + output_len, str, len);
+			}
+			break;
+
+		case IW_PRIV_TYPE_CHAR:
+			/* Display args */
+			_rtw_memcpy(output, extra, n);
+			break;
+
+		default:
+			RTW_INFO("%s: Not yet implemented...\n", __func__);
+			err = -1;
+			goto exit;
+		}
+
+		output_len = strlen(output) + 1;
+		wrq_data->data.length = output_len;
+		if (copy_to_user(wrq_data->data.pointer, output, output_len)) {
+			err = -EFAULT;
+			goto exit;
+		}
+	}   /* if args to set */
+	else
+		wrq_data->data.length = 0;
+
+exit:
+	if (input)
+		rtw_mfree(input, input_len);
+	if (buffer)
+		rtw_mfree(buffer, 4096);
+	if (output)
+		rtw_mfree(output, 4096);
+
+	return err;
+}
+
+#ifdef CONFIG_COMPAT
+static int rtw_ioctl_compat_wext_private(struct net_device *dev, struct ifreq *rq)
+{
+	struct compat_iw_point iwp_compat;
+	union iwreq_data wrq_data;
+	int err = 0;
+	RTW_INFO("%s:...\n", __func__);
+	if (copy_from_user(&iwp_compat, rq->ifr_ifru.ifru_data, sizeof(struct compat_iw_point)))
+		return -EFAULT;
+
+	wrq_data.data.pointer = compat_ptr(iwp_compat.pointer);
+	wrq_data.data.length = iwp_compat.length;
+	wrq_data.data.flags = iwp_compat.flags;
+
+	err = _rtw_ioctl_wext_private(dev, &wrq_data);
+
+	iwp_compat.pointer = ptr_to_compat(wrq_data.data.pointer);
+	iwp_compat.length = wrq_data.data.length;
+	iwp_compat.flags = wrq_data.data.flags;
+	if (copy_to_user(rq->ifr_ifru.ifru_data, &iwp_compat, sizeof(struct compat_iw_point)))
+		return -EFAULT;
+
+	return err;
+}
+#endif /* CONFIG_COMPAT */
+
+static int rtw_ioctl_standard_wext_private(struct net_device *dev, struct ifreq *rq)
+{
+	struct iw_point *iwp;
+	union iwreq_data wrq_data;
+	int err = 0;
+	iwp = &wrq_data.data;
+	RTW_INFO("%s:...\n", __func__);
+	if (copy_from_user(iwp, rq->ifr_ifru.ifru_data, sizeof(struct iw_point)))
+		return -EFAULT;
+
+	err = _rtw_ioctl_wext_private(dev, &wrq_data);
+
+	if (copy_to_user(rq->ifr_ifru.ifru_data, iwp, sizeof(struct iw_point)))
+		return -EFAULT;
+
+	return err;
+}
+
+static int rtw_ioctl_wext_private(struct net_device *dev, struct ifreq *rq)
+{
+#ifdef CONFIG_COMPAT
+#if (KERNEL_VERSION(4, 6, 0) > LINUX_VERSION_CODE)
+	if (is_compat_task())
+#else
+	if (in_compat_syscall())
+#endif
+		return rtw_ioctl_compat_wext_private(dev, rq);
+	else
+#endif /* CONFIG_COMPAT */
+		return rtw_ioctl_standard_wext_private(dev, rq);
+}
+
+int rtw_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
+{
+	struct iwreq *wrq = (struct iwreq *)rq;
+	int ret = 0;
+
+	switch (cmd) {
+	case RTL_IOCTL_WPA_SUPPLICANT:
+		ret = wpa_supplicant_ioctl(dev, &wrq->u.data);
+		break;
+#ifdef CONFIG_AP_MODE
+	case RTL_IOCTL_HOSTAPD:
+		ret = rtw_hostapd_ioctl(dev, &wrq->u.data);
+		break;
+#ifdef CONFIG_WIRELESS_EXT
+	case SIOCSIWMODE:
+		ret = rtw_wx_set_mode(dev, NULL, &wrq->u, NULL);
+		break;
+#endif
+#endif /* CONFIG_AP_MODE */
+	case SIOCDEVPRIVATE:
+		ret = rtw_ioctl_wext_private(dev, rq);
+		break;
+	case (SIOCDEVPRIVATE+1):
+		ret = rtw_android_priv_cmd(dev, rq, cmd);
+		break;
+	default:
+		ret = -EOPNOTSUPP;
+		break;
+	}
+
+	return ret;
+}
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/os_dep/linux/ioctl_mp.c linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/os_dep/linux/ioctl_mp.c
--- linux-5.6.3/3rdparty/rtl8821ce/os_dep/linux/ioctl_mp.c	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/os_dep/linux/ioctl_mp.c	2020-04-10 16:35:06.855661888 +0300
@@ -0,0 +1,2658 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#if defined(CONFIG_MP_INCLUDED)
+
+#include <drv_types.h>
+#include <rtw_mp.h>
+#include <rtw_mp_ioctl.h>
+#include "../../hal/phydm/phydm_precomp.h"
+
+
+#if defined(CONFIG_RTL8723B)
+	#include <rtw_bt_mp.h>
+#endif
+
+/*
+ * Input Format: %s,%d,%d
+ *	%s is width, could be
+ *		"b" for 1 byte
+ *		"w" for WORD (2 bytes)
+ *		"dw" for DWORD (4 bytes)
+ *	1st %d is address(offset)
+ *	2st %d is data to write
+ */
+int rtw_mp_write_reg(struct net_device *dev,
+		     struct iw_request_info *info,
+		     struct iw_point *wrqu, char *extra)
+{
+	char *pch, *pnext;
+	char *width_str;
+	char width;
+	u32 addr, data;
+	int ret;
+	PADAPTER padapter = rtw_netdev_priv(dev);
+	char input[wrqu->length + 1];
+
+	_rtw_memset(input, 0, sizeof(input));
+
+	if (copy_from_user(input, wrqu->pointer, wrqu->length))
+		return -EFAULT;
+
+	input[wrqu->length] = '\0';
+
+	_rtw_memset(extra, 0, wrqu->length);
+
+	pch = input;
+
+	pnext = strpbrk(pch, " ,.-");
+	if (pnext == NULL)
+		return -EINVAL;
+	*pnext = 0;
+	width_str = pch;
+
+	pch = pnext + 1;
+	pnext = strpbrk(pch, " ,.-");
+	if (pnext == NULL)
+		return -EINVAL;
+	*pnext = 0;
+	/*addr = simple_strtoul(pch, &ptmp, 16);
+	_rtw_memset(buf, '\0', sizeof(buf));
+	_rtw_memcpy(buf, pch, pnext-pch);
+	ret = kstrtoul(buf, 16, &addr);*/
+	ret = sscanf(pch, "%x", &addr);
+	if (addr > 0x3FFF)
+		return -EINVAL;
+
+	pch = pnext + 1;
+	pnext = strpbrk(pch, " ,.-");
+	if ((pch - input) >= wrqu->length)
+		return -EINVAL;
+	/*data = simple_strtoul(pch, &ptmp, 16);*/
+	ret = sscanf(pch, "%x", &data);
+	RTW_INFO("data=%x,addr=%x\n", (u32)data, (u32)addr);
+	ret = 0;
+	width = width_str[0];
+	switch (width) {
+	case 'b':
+		/* 1 byte*/
+		if (data > 0xFF) {
+			ret = -EINVAL;
+			break;
+		}
+		rtw_write8(padapter, addr, data);
+		break;
+	case 'w':
+		/* 2 bytes*/
+		if (data > 0xFFFF) {
+			ret = -EINVAL;
+			break;
+		}
+		rtw_write16(padapter, addr, data);
+		break;
+	case 'd':
+		/* 4 bytes*/
+		rtw_write32(padapter, addr, data);
+		break;
+	default:
+		ret = -EINVAL;
+		break;
+	}
+
+	return ret;
+}
+
+
+/*
+ * Input Format: %s,%d
+ *	%s is width, could be
+ *		"b" for 1 byte
+ *		"w" for WORD (2 bytes)
+ *		"dw" for DWORD (4 bytes)
+ *	%d is address(offset)
+ *
+ * Return:
+ *	%d for data readed
+ */
+int rtw_mp_read_reg(struct net_device *dev,
+		    struct iw_request_info *info,
+		    struct iw_point *wrqu, char *extra)
+{
+	char input[wrqu->length + 1];
+	char *pch, *pnext;
+	char *width_str;
+	char width;
+	char data[20], tmp[20];
+	u32 addr = 0, strtout = 0;
+	u32 i = 0, j = 0, ret = 0, data32 = 0;
+	PADAPTER padapter = rtw_netdev_priv(dev);
+	char *pextra = extra;
+
+	if (wrqu->length > 128)
+		return -EFAULT;
+
+	_rtw_memset(input, 0, sizeof(input));
+	if (copy_from_user(input, wrqu->pointer, wrqu->length))
+		return -EFAULT;
+
+	input[wrqu->length] = '\0';
+	_rtw_memset(extra, 0, wrqu->length);
+	_rtw_memset(data, '\0', sizeof(data));
+	_rtw_memset(tmp, '\0', sizeof(tmp));
+	pch = input;
+	pnext = strpbrk(pch, " ,.-");
+	if (pnext == NULL)
+		return -EINVAL;
+	*pnext = 0;
+	width_str = pch;
+
+	pch = pnext + 1;
+
+	ret = sscanf(pch, "%x", &addr);
+	if (addr > 0x3FFF)
+		return -EINVAL;
+
+	ret = 0;
+	width = width_str[0];
+
+	switch (width) {
+	case 'b':
+		data32 = rtw_read8(padapter, addr);
+		RTW_INFO("%x\n", data32);
+		sprintf(extra, "%d", data32);
+		wrqu->length = strlen(extra);
+		break;
+	case 'w':
+		/* 2 bytes*/
+		sprintf(data, "%04x\n", rtw_read16(padapter, addr));
+
+		for (i = 0 ; i <= strlen(data) ; i++) {
+			if (i % 2 == 0) {
+				tmp[j] = ' ';
+				j++;
+			}
+			if (data[i] != '\0')
+				tmp[j] = data[i];
+
+			j++;
+		}
+		pch = tmp;
+		RTW_INFO("pch=%s", pch);
+
+		while (*pch != '\0') {
+			pnext = strpbrk(pch, " ");
+			if (!pnext || ((pnext - tmp) > 4))
+				break;
+
+			pnext++;
+			if (*pnext != '\0') {
+				/*strtout = simple_strtoul(pnext , &ptmp, 16);*/
+				ret = sscanf(pnext, "%x", &strtout);
+				pextra += sprintf(pextra, " %d", strtout);
+			} else
+				break;
+			pch = pnext;
+		}
+		wrqu->length = strlen(extra);
+		break;
+	case 'd':
+		/* 4 bytes */
+		sprintf(data, "%08x", rtw_read32(padapter, addr));
+		/*add read data format blank*/
+		for (i = 0 ; i <= strlen(data) ; i++) {
+			if (i % 2 == 0) {
+				tmp[j] = ' ';
+				j++;
+			}
+			if (data[i] != '\0')
+				tmp[j] = data[i];
+
+			j++;
+		}
+		pch = tmp;
+		RTW_INFO("pch=%s", pch);
+
+		while (*pch != '\0') {
+			pnext = strpbrk(pch, " ");
+			if (!pnext)
+				break;
+
+			pnext++;
+			if (*pnext != '\0') {
+				ret = sscanf(pnext, "%x", &strtout);
+				pextra += sprintf(pextra, " %d", strtout);
+			} else
+				break;
+			pch = pnext;
+		}
+		wrqu->length = strlen(extra);
+		break;
+
+	default:
+		wrqu->length = 0;
+		ret = -EINVAL;
+		break;
+	}
+
+	return ret;
+}
+
+
+/*
+ * Input Format: %d,%x,%x
+ *	%d is RF path, should be smaller than MAX_RF_PATH_NUMS
+ *	1st %x is address(offset)
+ *	2st %x is data to write
+ */
+int rtw_mp_write_rf(struct net_device *dev,
+		    struct iw_request_info *info,
+		    struct iw_point *wrqu, char *extra)
+{
+
+	u32 path, addr, data;
+	int ret;
+	PADAPTER padapter = rtw_netdev_priv(dev);
+	char input[wrqu->length];
+
+
+	_rtw_memset(input, 0, wrqu->length);
+	if (copy_from_user(input, wrqu->pointer, wrqu->length))
+		return -EFAULT;
+
+
+	ret = sscanf(input, "%d,%x,%x", &path, &addr, &data);
+	if (ret < 3)
+		return -EINVAL;
+
+	if (path >= GET_HAL_RFPATH_NUM(padapter))
+		return -EINVAL;
+	if (addr > 0xFF)
+		return -EINVAL;
+	if (data > 0xFFFFF)
+		return -EINVAL;
+
+	_rtw_memset(extra, 0, wrqu->length);
+
+	write_rfreg(padapter, path, addr, data);
+
+	sprintf(extra, "write_rf completed\n");
+	wrqu->length = strlen(extra);
+
+	return 0;
+}
+
+
+/*
+ * Input Format: %d,%x
+ *	%d is RF path, should be smaller than MAX_RF_PATH_NUMS
+ *	%x is address(offset)
+ *
+ * Return:
+ *	%d for data readed
+ */
+int rtw_mp_read_rf(struct net_device *dev,
+		   struct iw_request_info *info,
+		   struct iw_point *wrqu, char *extra)
+{
+	char input[wrqu->length];
+	char *pch, *pnext;
+	char data[20], tmp[20];
+	u32 path, addr, strtou;
+	u32 ret, i = 0 , j = 0;
+	PADAPTER padapter = rtw_netdev_priv(dev);
+	char *pextra = extra;
+
+	if (wrqu->length > 128)
+		return -EFAULT;
+	_rtw_memset(input, 0, wrqu->length);
+	if (copy_from_user(input, wrqu->pointer, wrqu->length))
+		return -EFAULT;
+
+	ret = sscanf(input, "%d,%x", &path, &addr);
+	if (ret < 2)
+		return -EINVAL;
+
+	if (path >= GET_HAL_RFPATH_NUM(padapter))
+		return -EINVAL;
+	if (addr > 0xFF)
+		return -EINVAL;
+
+	_rtw_memset(extra, 0, wrqu->length);
+
+	sprintf(data, "%08x", read_rfreg(padapter, path, addr));
+	/*add read data format blank*/
+	for (i = 0 ; i <= strlen(data) ; i++) {
+		if (i % 2 == 0) {
+			tmp[j] = ' ';
+			j++;
+		}
+		tmp[j] = data[i];
+		j++;
+	}
+	pch = tmp;
+	RTW_INFO("pch=%s", pch);
+
+	while (*pch != '\0') {
+		pnext = strpbrk(pch, " ");
+		if (!pnext)
+			break;
+		pnext++;
+		if (*pnext != '\0') {
+			/*strtou =simple_strtoul(pnext , &ptmp, 16);*/
+			ret = sscanf(pnext, "%x", &strtou);
+			pextra += sprintf(pextra, " %d", strtou);
+		} else
+			break;
+		pch = pnext;
+	}
+	wrqu->length = strlen(extra);
+
+	return 0;
+}
+
+
+int rtw_mp_start(struct net_device *dev,
+		 struct iw_request_info *info,
+		 struct iw_point *wrqu, char *extra)
+{
+	int ret = 0;
+	PADAPTER padapter = rtw_netdev_priv(dev);
+
+	rtw_pm_set_ips(padapter, IPS_NONE);
+	LeaveAllPowerSaveMode(padapter);
+
+	if (rtw_mi_check_fwstate(padapter, _FW_UNDER_SURVEY))
+		rtw_mi_scan_abort(padapter, _FALSE);
+
+	if (rtw_mp_cmd(padapter, MP_START, RTW_CMDF_WAIT_ACK) != _SUCCESS)
+		ret = -EPERM;
+
+	_rtw_memset(extra, 0, wrqu->length);
+	sprintf(extra, "mp_start %s\n", ret == 0 ? "ok" : "fail");
+	wrqu->length = strlen(extra);
+
+	return ret;
+}
+
+
+
+int rtw_mp_stop(struct net_device *dev,
+		struct iw_request_info *info,
+		struct iw_point *wrqu, char *extra)
+{
+	int ret = 0;
+	PADAPTER padapter = rtw_netdev_priv(dev);
+
+	if (rtw_mp_cmd(padapter, MP_STOP, RTW_CMDF_WAIT_ACK) != _SUCCESS)
+		ret = -EPERM;
+
+	_rtw_memset(extra, 0, wrqu->length);
+	sprintf(extra, "mp_stop %s\n", ret == 0 ? "ok" : "fail");
+	wrqu->length = strlen(extra);
+
+	return ret;
+}
+
+
+int rtw_mp_rate(struct net_device *dev,
+		struct iw_request_info *info,
+		struct iw_point *wrqu, char *extra)
+{
+	u32 rate = MPT_RATE_1M;
+	u8		input[wrqu->length + 1];
+	PADAPTER padapter = rtw_netdev_priv(dev);
+	PMPT_CONTEXT		pMptCtx = &(padapter->mppriv.mpt_ctx);
+
+	_rtw_memset(input, 0, sizeof(input));
+	if (copy_from_user(input, wrqu->pointer, wrqu->length))
+		return -EFAULT;
+
+	input[wrqu->length] = '\0';
+	rate = rtw_mpRateParseFunc(padapter, input);
+	padapter->mppriv.rateidx = rate;
+
+	if (rate == 0 && strcmp(input, "1M") != 0) {
+		rate = rtw_atoi(input);
+		padapter->mppriv.rateidx = MRateToHwRate(rate);
+		/*if (rate <= 0x7f)
+			rate = wifirate2_ratetbl_inx((u8)rate);
+		else if (rate < 0xC8)
+			rate = (rate - 0x79 + MPT_RATE_MCS0);
+		HT  rate 0x80(MCS0)  ~ 0x8F(MCS15) ~ 0x9F(MCS31) 128~159
+		VHT1SS~2SS rate 0xA0 (VHT1SS_MCS0 44) ~ 0xB3 (VHT2SS_MCS9 #63) 160~179
+		VHT rate 0xB4 (VHT3SS_MCS0 64) ~ 0xC7 (VHT2SS_MCS9 #83) 180~199
+		else
+		VHT rate 0x90(VHT1SS_MCS0) ~ 0x99(VHT1SS_MCS9) 144~153
+		rate =(rate - MPT_RATE_VHT1SS_MCS0);
+		*/
+	}
+	_rtw_memset(extra, 0, wrqu->length);
+
+	sprintf(extra, "Set data rate to %s index %d" , input, padapter->mppriv.rateidx);
+	RTW_INFO("%s: %s rate index=%d\n", __func__, input, padapter->mppriv.rateidx);
+
+	if (padapter->mppriv.rateidx >= DESC_RATEVHTSS4MCS9)
+		return -EINVAL;
+
+	pMptCtx->mpt_rate_index = HwRateToMPTRate(padapter->mppriv.rateidx);
+	SetDataRate(padapter);
+
+	wrqu->length = strlen(extra);
+	return 0;
+}
+
+
+int rtw_mp_channel(struct net_device *dev,
+		   struct iw_request_info *info,
+		   struct iw_point *wrqu, char *extra)
+{
+
+	PADAPTER padapter = rtw_netdev_priv(dev);
+	HAL_DATA_TYPE	*pHalData	= GET_HAL_DATA(padapter);
+	u8		input[wrqu->length + 1];
+	u32	channel = 1;
+
+	_rtw_memset(input, 0, sizeof(input));
+	if (copy_from_user(input, wrqu->pointer, wrqu->length))
+		return -EFAULT;
+
+	input[wrqu->length] = '\0';
+	channel = rtw_atoi(input);
+	/*RTW_INFO("%s: channel=%d\n", __func__, channel);*/
+	_rtw_memset(extra, 0, wrqu->length);
+	sprintf(extra, "Change channel %d to channel %d", padapter->mppriv.channel , channel);
+	padapter->mppriv.channel = channel;
+	SetChannel(padapter);
+	pHalData->current_channel = channel;
+
+	wrqu->length = strlen(extra);
+	return 0;
+}
+
+
+int rtw_mp_ch_offset(struct net_device *dev,
+		   struct iw_request_info *info,
+		   struct iw_point *wrqu, char *extra)
+{
+
+	PADAPTER padapter = rtw_netdev_priv(dev);
+	u8		input[wrqu->length + 1];
+	u32	ch_offset = 0;
+
+	_rtw_memset(input, 0, sizeof(input));
+	if (copy_from_user(input, wrqu->pointer, wrqu->length))
+		return -EFAULT;
+
+	input[wrqu->length] = '\0';
+	ch_offset = rtw_atoi(input);
+	/*RTW_INFO("%s: channel=%d\n", __func__, channel);*/
+	_rtw_memset(extra, 0, wrqu->length);
+	sprintf(extra, "Change prime channel offset %d to %d", padapter->mppriv.prime_channel_offset , ch_offset);
+	padapter->mppriv.prime_channel_offset = ch_offset;
+	SetChannel(padapter);
+
+	wrqu->length = strlen(extra);
+	return 0;
+}
+
+
+int rtw_mp_bandwidth(struct net_device *dev,
+		     struct iw_request_info *info,
+		     struct iw_point *wrqu, char *extra)
+{
+	u32 bandwidth = 0, sg = 0;
+	PADAPTER padapter = rtw_netdev_priv(dev);
+	HAL_DATA_TYPE	*pHalData	= GET_HAL_DATA(padapter);
+	u8		input[wrqu->length];
+
+	if (copy_from_user(input, wrqu->pointer, wrqu->length))
+		return -EFAULT;
+
+	if (sscanf(input, "40M=%d,shortGI=%d", &bandwidth, &sg) > 0)
+		RTW_INFO("%s: bw=%d sg=%d\n", __func__, bandwidth , sg);
+
+	if (bandwidth == 1)
+		bandwidth = CHANNEL_WIDTH_40;
+	else if (bandwidth == 2)
+		bandwidth = CHANNEL_WIDTH_80;
+
+	padapter->mppriv.bandwidth = (u8)bandwidth;
+	padapter->mppriv.preamble = sg;
+	_rtw_memset(extra, 0, wrqu->length);
+	sprintf(extra, "Change BW %d to BW %d\n", pHalData->current_channel_bw , bandwidth);
+
+	SetBandwidth(padapter);
+	pHalData->current_channel_bw = bandwidth;
+
+	wrqu->length = strlen(extra);
+
+	return 0;
+}
+
+
+int rtw_mp_txpower_index(struct net_device *dev,
+			 struct iw_request_info *info,
+			 struct iw_point *wrqu, char *extra)
+{
+	PADAPTER padapter = rtw_netdev_priv(dev);
+ 	HAL_DATA_TYPE	*phal_data	= GET_HAL_DATA(padapter);
+	char input[wrqu->length + 1];
+	u32 rfpath;
+	u32 txpower_inx;
+
+	if (wrqu->length > 128)
+		return -EFAULT;
+
+	_rtw_memset(input, 0, sizeof(input));
+
+	if (copy_from_user(input, wrqu->pointer, wrqu->length))
+		return -EFAULT;
+
+	input[wrqu->length] = '\0';
+
+	if (wrqu->length == 2) {
+		rfpath = rtw_atoi(input);
+		txpower_inx = mpt_ProQueryCalTxPower(padapter, rfpath);
+		sprintf(extra, " %d", txpower_inx);
+	} else {
+		txpower_inx = mpt_ProQueryCalTxPower(padapter, 0);
+		sprintf(extra, "patha=%d", txpower_inx);
+		if (phal_data->rf_type > RF_1T2R) {
+			txpower_inx = mpt_ProQueryCalTxPower(padapter, 1);
+			sprintf(extra, "%s,pathb=%d", extra, txpower_inx);
+		}
+		if (phal_data->rf_type > RF_2T4R) {
+			txpower_inx = mpt_ProQueryCalTxPower(padapter, 2);
+			sprintf(extra, "%s,pathc=%d", extra, txpower_inx);
+		}
+		if (phal_data->rf_type > RF_3T4R) {
+			txpower_inx = mpt_ProQueryCalTxPower(padapter, 3);
+			sprintf(extra, "%s,pathd=%d", extra, txpower_inx);
+		}
+	}
+	wrqu->length = strlen(extra);
+
+	return 0;
+}
+
+
+int rtw_mp_txpower(struct net_device *dev,
+		   struct iw_request_info *info,
+		   struct iw_point *wrqu, char *extra)
+{
+	u32 idx_a = 0, idx_b = 0, idx_c = 0, idx_d = 0;
+	int MsetPower = 1;
+	u8		input[wrqu->length];
+
+	PADAPTER padapter = rtw_netdev_priv(dev);
+	PMPT_CONTEXT		pMptCtx = &(padapter->mppriv.mpt_ctx);
+
+	if (copy_from_user(input, wrqu->pointer, wrqu->length))
+		return -EFAULT;
+
+	MsetPower = strncmp(input, "off", 3);
+	if (MsetPower == 0) {
+		padapter->mppriv.bSetTxPower = 0;
+		sprintf(extra, "MP Set power off");
+	} else {
+		if (sscanf(input, "patha=%d,pathb=%d,pathc=%d,pathd=%d", &idx_a, &idx_b, &idx_c, &idx_d) < 3)
+			RTW_INFO("Invalid format on line %s ,patha=%d,pathb=%d,pathc=%d,pathd=%d\n", input , idx_a , idx_b , idx_c , idx_d);
+
+		sprintf(extra, "Set power level path_A:%d path_B:%d path_C:%d path_D:%d", idx_a , idx_b , idx_c , idx_d);
+		padapter->mppriv.txpoweridx = (u8)idx_a;
+
+		pMptCtx->TxPwrLevel[RF_PATH_A] = (u8)idx_a;
+		pMptCtx->TxPwrLevel[RF_PATH_B] = (u8)idx_b;
+		pMptCtx->TxPwrLevel[RF_PATH_C] = (u8)idx_c;
+		pMptCtx->TxPwrLevel[RF_PATH_D]  = (u8)idx_d;
+		padapter->mppriv.bSetTxPower = 1;
+
+		SetTxPower(padapter);
+	}
+
+	wrqu->length = strlen(extra);
+	return 0;
+}
+
+
+int rtw_mp_ant_tx(struct net_device *dev,
+		  struct iw_request_info *info,
+		  struct iw_point *wrqu, char *extra)
+{
+	u8 i;
+	u8		input[wrqu->length + 1];
+	u16 antenna = 0;
+	PADAPTER padapter = rtw_netdev_priv(dev);
+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(padapter);
+
+	_rtw_memset(input, 0, sizeof(input));
+	if (copy_from_user(input, wrqu->pointer, wrqu->length))
+		return -EFAULT;
+
+	input[wrqu->length] = '\0';
+	sprintf(extra, "switch Tx antenna to %s", input);
+
+	for (i = 0; i < strlen(input); i++) {
+		switch (input[i]) {
+		case 'a':
+			antenna |= ANTENNA_A;
+			break;
+		case 'b':
+			antenna |= ANTENNA_B;
+			break;
+		case 'c':
+			antenna |= ANTENNA_C;
+			break;
+		case 'd':
+			antenna |= ANTENNA_D;
+			break;
+		}
+	}
+	/*antenna |= BIT(extra[i]-'a');*/
+	RTW_INFO("%s: antenna=0x%x\n", __func__, antenna);
+	padapter->mppriv.antenna_tx = antenna;
+	padapter->mppriv.antenna_rx = antenna;
+	/*RTW_INFO("%s:mppriv.antenna_rx=%d\n", __func__, padapter->mppriv.antenna_tx);*/
+	pHalData->antenna_tx_path = antenna;
+
+	SetAntenna(padapter);
+
+	wrqu->length = strlen(extra);
+	return 0;
+}
+
+
+int rtw_mp_ant_rx(struct net_device *dev,
+		  struct iw_request_info *info,
+		  struct iw_point *wrqu, char *extra)
+{
+	u8 i;
+	u16 antenna = 0;
+	u8		input[wrqu->length + 1];
+	PADAPTER padapter = rtw_netdev_priv(dev);
+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(padapter);
+
+	_rtw_memset(input, 0, sizeof(input));
+	if (copy_from_user(input, wrqu->pointer, wrqu->length))
+		return -EFAULT;
+
+	input[wrqu->length] = '\0';
+	/*RTW_INFO("%s: input=%s\n", __func__, input);*/
+	_rtw_memset(extra, 0, wrqu->length);
+
+	sprintf(extra, "switch Rx antenna to %s", input);
+
+	for (i = 0; i < strlen(input); i++) {
+		switch (input[i]) {
+		case 'a':
+			antenna |= ANTENNA_A;
+			break;
+		case 'b':
+			antenna |= ANTENNA_B;
+			break;
+		case 'c':
+			antenna |= ANTENNA_C;
+			break;
+		case 'd':
+			antenna |= ANTENNA_D;
+			break;
+		}
+	}
+
+	RTW_INFO("%s: antenna=0x%x\n", __func__, antenna);
+	padapter->mppriv.antenna_tx = antenna;
+	padapter->mppriv.antenna_rx = antenna;
+	pHalData->AntennaRxPath = antenna;
+	/*RTW_INFO("%s:mppriv.antenna_rx=%d\n", __func__, padapter->mppriv.antenna_rx);*/
+	SetAntenna(padapter);
+	wrqu->length = strlen(extra);
+
+	return 0;
+}
+
+
+int rtw_set_ctx_destAddr(struct net_device *dev,
+			 struct iw_request_info *info,
+			 struct iw_point *wrqu, char *extra)
+{
+	int jj, kk = 0;
+
+	struct pkt_attrib *pattrib;
+	struct mp_priv *pmp_priv;
+	PADAPTER padapter = rtw_netdev_priv(dev);
+
+	pmp_priv = &padapter->mppriv;
+	pattrib = &pmp_priv->tx.attrib;
+
+	if (strlen(extra) < 5)
+		return _FAIL;
+
+	RTW_INFO("%s: in=%s\n", __func__, extra);
+	for (jj = 0, kk = 0; jj < ETH_ALEN; jj++, kk += 3)
+		pattrib->dst[jj] = key_2char2num(extra[kk], extra[kk + 1]);
+
+	RTW_INFO("pattrib->dst:%x %x %x %x %x %x\n", pattrib->dst[0], pattrib->dst[1], pattrib->dst[2], pattrib->dst[3], pattrib->dst[4], pattrib->dst[5]);
+	return 0;
+}
+
+
+
+int rtw_mp_ctx(struct net_device *dev,
+	       struct iw_request_info *info,
+	       struct iw_point *wrqu, char *extra)
+{
+	u32 pkTx = 1;
+	int countPkTx = 1, cotuTx = 1, CarrSprTx = 1, scTx = 1, sgleTx = 1, stop = 1;
+	u32 bStartTest = 1;
+	u32 count = 0, pktinterval = 0, pktlen = 0;
+	u8 status;
+	struct mp_priv *pmp_priv;
+	struct pkt_attrib *pattrib;
+	PADAPTER padapter = rtw_netdev_priv(dev);
+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(padapter);
+
+	pmp_priv = &padapter->mppriv;
+	pattrib = &pmp_priv->tx.attrib;
+
+	if (copy_from_user(extra, wrqu->pointer, wrqu->length))
+		return -EFAULT;
+
+	*(extra + wrqu->length) = '\0';
+	RTW_INFO("%s: in=%s\n", __func__, extra);
+#ifdef CONFIG_CONCURRENT_MODE
+	if (!is_primary_adapter(padapter)) {
+		sprintf(extra, "Error: MP mode can't support Virtual Adapter, Please to use main Adapter.\n");
+		wrqu->length = strlen(extra);
+		return 0;
+	}
+#endif
+	countPkTx = strncmp(extra, "count=", 5); /* strncmp TRUE is 0*/
+	cotuTx = strncmp(extra, "background", 20);
+	CarrSprTx = strncmp(extra, "background,cs", 20);
+	scTx = strncmp(extra, "background,sc", 20);
+	sgleTx = strncmp(extra, "background,stone", 20);
+	pkTx = strncmp(extra, "background,pkt", 20);
+	stop = strncmp(extra, "stop", 4);
+	if (sscanf(extra, "count=%d,pkt", &count) > 0)
+		RTW_INFO("count= %d\n", count);
+	if (sscanf(extra, "pktinterval=%d", &pktinterval) > 0)
+		RTW_INFO("pktinterval= %d\n", pktinterval);
+
+	if (sscanf(extra, "pktlen=%d", &pktlen) > 0)
+		RTW_INFO("pktlen= %d\n", pktlen);
+
+	if (_rtw_memcmp(extra, "destmac=", 8)) {
+		wrqu->length -= 8;
+		rtw_set_ctx_destAddr(dev, info, wrqu, &extra[8]);
+		sprintf(extra, "Set dest mac OK !\n");
+		return 0;
+	}
+
+	/*RTW_INFO("%s: count=%d countPkTx=%d cotuTx=%d CarrSprTx=%d scTx=%d sgleTx=%d pkTx=%d stop=%d\n", __func__, count, countPkTx, cotuTx, CarrSprTx, pkTx, sgleTx, scTx, stop);*/
+	_rtw_memset(extra, '\0', strlen(extra));
+
+	if (pktinterval != 0) {
+		sprintf(extra, "Pkt Interval = %d", pktinterval);
+		padapter->mppriv.pktInterval = pktinterval;
+		wrqu->length = strlen(extra);
+		return 0;
+	}
+	if (pktlen != 0) {
+		sprintf(extra, "Pkt len = %d", pktlen);
+		pattrib->pktlen = pktlen;
+		wrqu->length = strlen(extra);
+		return 0;
+	}
+	if (stop == 0) {
+		bStartTest = 0; /* To set Stop*/
+		pmp_priv->tx.stop = 1;
+		sprintf(extra, "Stop continuous Tx");
+		odm_write_dig(&pHalData->odmpriv, 0x20);
+	} else {
+		bStartTest = 1;
+		odm_write_dig(&pHalData->odmpriv, 0x7f);
+		if (pmp_priv->mode != MP_ON) {
+			if (pmp_priv->tx.stop != 1) {
+				RTW_INFO("%s: MP_MODE != ON %d\n", __func__, pmp_priv->mode);
+				return	-EFAULT;
+			}
+		}
+	}
+
+	pmp_priv->tx.count = count;
+
+	if (pkTx == 0 || countPkTx == 0)
+		pmp_priv->mode = MP_PACKET_TX;
+	if (sgleTx == 0)
+		pmp_priv->mode = MP_SINGLE_TONE_TX;
+	if (cotuTx == 0)
+		pmp_priv->mode = MP_CONTINUOUS_TX;
+	if (CarrSprTx == 0)
+		pmp_priv->mode = MP_CARRIER_SUPPRISSION_TX;
+	if (scTx == 0)
+		pmp_priv->mode = MP_SINGLE_CARRIER_TX;
+
+	status = rtw_mp_pretx_proc(padapter, bStartTest, extra);
+
+	wrqu->length = strlen(extra);
+	return status;
+}
+
+
+
+int rtw_mp_disable_bt_coexist(struct net_device *dev,
+			      struct iw_request_info *info,
+			      union iwreq_data *wrqu, char *extra)
+{
+#ifdef CONFIG_BT_COEXIST
+	PADAPTER padapter = (PADAPTER)rtw_netdev_priv(dev);
+
+#endif
+	u8 input[wrqu->data.length + 1];
+	u32 bt_coexist;
+
+	_rtw_memset(input, 0, sizeof(input));
+
+	if (copy_from_user(input, wrqu->data.pointer, wrqu->data.length))
+		return -EFAULT;
+
+	input[wrqu->data.length] = '\0';
+
+	bt_coexist = rtw_atoi(input);
+
+	if (bt_coexist == 0) {
+		RTW_INFO("Set OID_RT_SET_DISABLE_BT_COEXIST: disable BT_COEXIST\n");
+#ifdef CONFIG_BT_COEXIST
+		rtw_btcoex_HaltNotify(padapter);
+		rtw_btcoex_SetManualControl(padapter, _TRUE);
+		/* Force to switch Antenna to WiFi*/
+		rtw_write16(padapter, 0x870, 0x300);
+		rtw_write16(padapter, 0x860, 0x110);
+#endif
+		/* CONFIG_BT_COEXIST */
+	} else {
+#ifdef CONFIG_BT_COEXIST
+		rtw_btcoex_SetManualControl(padapter, _FALSE);
+#endif
+	}
+
+	return 0;
+}
+
+
+int rtw_mp_arx(struct net_device *dev,
+	       struct iw_request_info *info,
+	       struct iw_point *wrqu, char *extra)
+{
+	int bStartRx = 0, bStopRx = 0, bQueryPhy = 0, bQueryMac = 0, bSetBssid = 0, bSetRxframe = 0;
+	int bmac_filter = 0, bmon = 0, bSmpCfg = 0;
+	u8		input[wrqu->length];
+	char *pch, *token, *tmp[2] = {0x00, 0x00};
+	u32 i = 0, jj = 0, kk = 0, cnts = 0, ret;
+	PADAPTER padapter = rtw_netdev_priv(dev);
+	struct mp_priv *pmppriv = &padapter->mppriv;
+	struct dbg_rx_counter rx_counter;
+
+	if (copy_from_user(input, wrqu->pointer, wrqu->length))
+		return -EFAULT;
+
+	RTW_INFO("%s: %s\n", __func__, input);
+#ifdef CONFIG_CONCURRENT_MODE
+	if (!is_primary_adapter(padapter)) {
+		sprintf(extra, "Error: MP mode can't support Virtual Adapter, Please to use main Adapter.\n");
+		wrqu->length = strlen(extra);
+		return 0;
+	}
+#endif
+	bStartRx = (strncmp(input, "start", 5) == 0) ? 1 : 0; /* strncmp TRUE is 0*/
+	bStopRx = (strncmp(input, "stop", 5) == 0) ? 1 : 0; /* strncmp TRUE is 0*/
+	bQueryPhy = (strncmp(input, "phy", 3) == 0) ? 1 : 0; /* strncmp TRUE is 0*/
+	bQueryMac = (strncmp(input, "mac", 3) == 0) ? 1 : 0; /* strncmp TRUE is 0*/
+	bSetBssid = (strncmp(input, "setbssid=", 8) == 0) ? 1 : 0; /* strncmp TRUE is 0*/
+	bSetRxframe = (strncmp(input, "frametype", 9) == 0) ? 1 : 0;
+	/*bfilter_init = (strncmp(input, "filter_init",11)==0)?1:0;*/
+	bmac_filter = (strncmp(input, "accept_mac", 10) == 0) ? 1 : 0;
+	bmon = (strncmp(input, "mon=", 4) == 0) ? 1 : 0;
+	bSmpCfg = (strncmp(input , "smpcfg=" , 7) == 0) ? 1 : 0;
+	pmppriv->bloopback = (strncmp(input, "loopbk", 6) == 0) ? 1 : 0; /* strncmp TRUE is 0*/
+
+	if (bSetBssid == 1) {
+		pch = input;
+		while ((token = strsep(&pch, "=")) != NULL) {
+			if (i > 1)
+				break;
+			tmp[i] = token;
+			i++;
+		}
+		if ((tmp[0] != NULL) && (tmp[1] != NULL)) {
+			cnts = strlen(tmp[1]) / 2;
+			if (cnts < 1)
+				return -EFAULT;
+			RTW_INFO("%s: cnts=%d\n", __func__, cnts);
+			RTW_INFO("%s: data=%s\n", __func__, tmp[1]);
+			for (jj = 0, kk = 0; jj < cnts ; jj++, kk += 2) {
+				pmppriv->network_macaddr[jj] = key_2char2num(tmp[1][kk], tmp[1][kk + 1]);
+				RTW_INFO("network_macaddr[%d]=%x\n", jj, pmppriv->network_macaddr[jj]);
+			}
+		} else
+			return -EFAULT;
+
+		pmppriv->bSetRxBssid = _TRUE;
+	}
+	if (bSetRxframe) {
+		if (strncmp(input, "frametype beacon", 16) == 0)
+			pmppriv->brx_filter_beacon = _TRUE;
+		else
+			pmppriv->brx_filter_beacon = _FALSE;
+	}
+
+	if (bmac_filter) {
+		pmppriv->bmac_filter = bmac_filter;
+		pch = input;
+		while ((token = strsep(&pch, "=")) != NULL) {
+			if (i > 1)
+				break;
+			tmp[i] = token;
+			i++;
+		}
+		if ((tmp[0] != NULL) && (tmp[1] != NULL)) {
+			cnts = strlen(tmp[1]) / 2;
+			if (cnts < 1)
+				return -EFAULT;
+			RTW_INFO("%s: cnts=%d\n", __func__, cnts);
+			RTW_INFO("%s: data=%s\n", __func__, tmp[1]);
+			for (jj = 0, kk = 0; jj < cnts ; jj++, kk += 2) {
+				pmppriv->mac_filter[jj] = key_2char2num(tmp[1][kk], tmp[1][kk + 1]);
+				RTW_INFO("%s mac_filter[%d]=%x\n", __func__, jj, pmppriv->mac_filter[jj]);
+			}
+		} else
+			return -EFAULT;
+
+	}
+
+	if (bStartRx) {
+		sprintf(extra, "start");
+		SetPacketRx(padapter, bStartRx, _FALSE);
+	} else if (bStopRx) {
+		SetPacketRx(padapter, bStartRx, _FALSE);
+		pmppriv->bmac_filter = _FALSE;
+		pmppriv->bSetRxBssid = _FALSE;
+		sprintf(extra, "Received packet OK:%d CRC error:%d ,Filter out:%d", padapter->mppriv.rx_pktcount, padapter->mppriv.rx_crcerrpktcount, padapter->mppriv.rx_pktcount_filter_out);
+	} else if (bQueryPhy) {
+		_rtw_memset(&rx_counter, 0, sizeof(struct dbg_rx_counter));
+		rtw_dump_phy_rx_counters(padapter, &rx_counter);
+
+		RTW_INFO("%s: OFDM_FA =%d\n", __func__, rx_counter.rx_ofdm_fa);
+		RTW_INFO("%s: CCK_FA =%d\n", __func__, rx_counter.rx_cck_fa);
+		sprintf(extra, "Phy Received packet OK:%d CRC error:%d FA Counter: %d", rx_counter.rx_pkt_ok, rx_counter.rx_pkt_crc_error, rx_counter.rx_cck_fa + rx_counter.rx_ofdm_fa);
+
+
+	} else if (bQueryMac) {
+		_rtw_memset(&rx_counter, 0, sizeof(struct dbg_rx_counter));
+		rtw_dump_mac_rx_counters(padapter, &rx_counter);
+		sprintf(extra, "Mac Received packet OK: %d , CRC error: %d , Drop Packets: %d\n",
+			rx_counter.rx_pkt_ok, rx_counter.rx_pkt_crc_error, rx_counter.rx_pkt_drop);
+
+	}
+
+	if (bmon == 1) {
+		ret = sscanf(input, "mon=%d", &bmon);
+
+		if (bmon == 1) {
+			pmppriv->rx_bindicatePkt = _TRUE;
+			sprintf(extra, "Indicating Receive Packet to network start\n");
+		} else {
+			pmppriv->rx_bindicatePkt = _FALSE;
+			sprintf(extra, "Indicating Receive Packet to network Stop\n");
+		}
+	}
+	if (bSmpCfg == 1) {
+		ret = sscanf(input, "smpcfg=%d", &bSmpCfg);
+
+		if (bSmpCfg == 1) {
+			pmppriv->bRTWSmbCfg = _TRUE;
+			sprintf(extra , "Indicate By Simple Config Format\n");
+			SetPacketRx(padapter, _TRUE, _TRUE);
+		} else {
+			pmppriv->bRTWSmbCfg = _FALSE;
+			sprintf(extra , "Indicate By Normal Format\n");
+			SetPacketRx(padapter, _TRUE, _FALSE);
+		}
+	}
+
+	if (pmppriv->bloopback == _TRUE) {
+		sprintf(extra , "Enter MAC LoopBack mode\n");
+		_rtw_write32(padapter, 0x100, 0xB0106FF);
+		RTW_INFO("0x100 :0x%x" , _rtw_read32(padapter, 0x100));
+		_rtw_write16(padapter, 0x608, 0x30c);
+		RTW_INFO("0x100 :0x%x" , _rtw_read32(padapter, 0x608));
+	}
+
+	wrqu->length = strlen(extra) + 1;
+
+	return 0;
+}
+
+
+int rtw_mp_trx_query(struct net_device *dev,
+		     struct iw_request_info *info,
+		     struct iw_point *wrqu, char *extra)
+{
+	u32 txok, txfail, rxok, rxfail, rxfilterout;
+	PADAPTER padapter = rtw_netdev_priv(dev);
+	PMPT_CONTEXT	pMptCtx		=	&(padapter->mppriv.mpt_ctx);
+	RT_PMAC_TX_INFO	PMacTxInfo	=	pMptCtx->PMacTxInfo;
+
+	if (PMacTxInfo.bEnPMacTx == TRUE)
+		txok = hal_mpt_query_phytxok(padapter);
+	else
+		txok = padapter->mppriv.tx.sended;
+
+	txfail = 0;
+	rxok = padapter->mppriv.rx_pktcount;
+	rxfail = padapter->mppriv.rx_crcerrpktcount;
+	rxfilterout = padapter->mppriv.rx_pktcount_filter_out;
+
+	_rtw_memset(extra, '\0', 128);
+
+	sprintf(extra, "Tx OK:%d, Tx Fail:%d, Rx OK:%d, CRC error:%d ,Rx Filter out:%d\n", txok, txfail, rxok, rxfail, rxfilterout);
+
+	wrqu->length = strlen(extra) + 1;
+
+	return 0;
+}
+
+
+int rtw_mp_pwrtrk(struct net_device *dev,
+		  struct iw_request_info *info,
+		  struct iw_point *wrqu, char *extra)
+{
+	u8 enable;
+	u32 thermal;
+	s32 ret;
+	PADAPTER padapter = rtw_netdev_priv(dev);
+	u8		input[wrqu->length];
+
+	if (copy_from_user(input, wrqu->pointer, wrqu->length))
+		return -EFAULT;
+
+	_rtw_memset(extra, 0, wrqu->length);
+
+	enable = 1;
+	if (wrqu->length > 1) {
+		/* not empty string*/
+		if (strncmp(input, "stop", 4) == 0) {
+			enable = 0;
+			sprintf(extra, "mp tx power tracking stop");
+		} else if (sscanf(input, "ther=%d", &thermal) == 1) {
+			ret = SetThermalMeter(padapter, (u8)thermal);
+			if (ret == _FAIL)
+				return -EPERM;
+			sprintf(extra, "mp tx power tracking start,target value=%d ok", thermal);
+		} else
+			return -EINVAL;
+	}
+
+	ret = SetPowerTracking(padapter, enable);
+	if (ret == _FAIL)
+		return -EPERM;
+
+	wrqu->length = strlen(extra);
+
+	return 0;
+}
+
+
+
+int rtw_mp_psd(struct net_device *dev,
+	       struct iw_request_info *info,
+	       struct iw_point *wrqu, char *extra)
+{
+	PADAPTER padapter = rtw_netdev_priv(dev);
+	u8		input[wrqu->length + 1];
+
+	_rtw_memset(input, 0, sizeof(input));
+	if (copy_from_user(input, wrqu->pointer, wrqu->length))
+		return -EFAULT;
+
+	input[wrqu->length] = '\0';
+	strcpy(extra, input);
+
+	wrqu->length = mp_query_psd(padapter, extra);
+
+	return 0;
+}
+
+
+int rtw_mp_thermal(struct net_device *dev,
+		   struct iw_request_info *info,
+		   struct iw_point *wrqu, char *extra)
+{
+	u8 val;
+	int bwrite = 1;
+
+#ifdef CONFIG_RTL8188E
+	u16 addr = EEPROM_THERMAL_METER_88E;
+#endif
+#if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A) || defined(CONFIG_RTL8814A)
+	u16 addr = EEPROM_THERMAL_METER_8812;
+#endif
+#ifdef CONFIG_RTL8192E
+	u16 addr = EEPROM_THERMAL_METER_8192E;
+#endif
+#ifdef CONFIG_RTL8192F
+	u16 addr = EEPROM_THERMAL_METER_8192F;
+#endif
+#ifdef CONFIG_RTL8723B
+	u16 addr = EEPROM_THERMAL_METER_8723B;
+#endif
+#ifdef CONFIG_RTL8703B
+	u16 addr = EEPROM_THERMAL_METER_8703B;
+#endif
+#ifdef CONFIG_RTL8723D
+	u16 addr = EEPROM_THERMAL_METER_8723D;
+#endif
+#ifdef CONFIG_RTL8188F
+	u16 addr = EEPROM_THERMAL_METER_8188F;
+#endif
+#ifdef CONFIG_RTL8188GTV
+	u16 addr = EEPROM_THERMAL_METER_8188GTV;
+#endif
+#ifdef CONFIG_RTL8822B
+	u16 addr = EEPROM_THERMAL_METER_8822B;
+#endif
+#ifdef CONFIG_RTL8821C
+	u16 addr = EEPROM_THERMAL_METER_8821C;
+#endif
+#ifdef CONFIG_RTL8710B
+	u16 addr = EEPROM_THERMAL_METER_8710B;
+#endif
+	u16 cnt = 1;
+	u16 max_available_size = 0;
+	PADAPTER padapter = rtw_netdev_priv(dev);
+
+	if (copy_from_user(extra, wrqu->pointer, wrqu->length))
+		return -EFAULT;
+
+	bwrite = strncmp(extra, "write", 6);/* strncmp TRUE is 0*/
+
+	GetThermalMeter(padapter, &val);
+
+	if (bwrite == 0) {
+		/*RTW_INFO("to write val:%d",val);*/
+		EFUSE_GetEfuseDefinition(padapter, EFUSE_WIFI, TYPE_AVAILABLE_EFUSE_BYTES_TOTAL, (PVOID)&max_available_size, _FALSE);
+		if (2 > max_available_size) {
+			RTW_INFO("no available efuse!\n");
+			return -EFAULT;
+		}
+		if (rtw_efuse_map_write(padapter, addr, cnt, &val) == _FAIL) {
+			RTW_INFO("rtw_efuse_map_write error\n");
+			return -EFAULT;
+		}
+		sprintf(extra, " efuse write ok :%d", val);
+	} else
+		sprintf(extra, "%d", val);
+	wrqu->length = strlen(extra);
+
+	return 0;
+}
+
+
+
+int rtw_mp_reset_stats(struct net_device *dev,
+		       struct iw_request_info *info,
+		       struct iw_point *wrqu, char *extra)
+{
+	struct mp_priv *pmp_priv;
+	PADAPTER padapter = rtw_netdev_priv(dev);
+
+	pmp_priv = &padapter->mppriv;
+
+	pmp_priv->tx.sended = 0;
+	pmp_priv->tx_pktcount = 0;
+	pmp_priv->rx_pktcount = 0;
+	pmp_priv->rx_pktcount_filter_out = 0;
+	pmp_priv->rx_crcerrpktcount = 0;
+
+	rtw_reset_phy_rx_counters(padapter);
+	rtw_reset_mac_rx_counters(padapter);
+
+	_rtw_memset(extra, 0, wrqu->length);
+	sprintf(extra, "mp_reset_stats ok\n");
+	wrqu->length = strlen(extra);
+
+	return 0;
+}
+
+
+int rtw_mp_dump(struct net_device *dev,
+		struct iw_request_info *info,
+		struct iw_point *wrqu, char *extra)
+{
+	struct mp_priv *pmp_priv;
+	u8		input[wrqu->length];
+	PADAPTER padapter = rtw_netdev_priv(dev);
+
+	pmp_priv = &padapter->mppriv;
+
+	if (copy_from_user(input, wrqu->pointer, wrqu->length))
+		return -EFAULT;
+
+	if (strncmp(input, "all", 4) == 0) {
+		mac_reg_dump(RTW_DBGDUMP, padapter);
+		bb_reg_dump(RTW_DBGDUMP, padapter);
+		rf_reg_dump(RTW_DBGDUMP, padapter);
+	}
+	return 0;
+}
+
+
+int rtw_mp_phypara(struct net_device *dev,
+		   struct iw_request_info *info,
+		   struct iw_point *wrqu, char *extra)
+{
+
+	PADAPTER padapter = rtw_netdev_priv(dev);
+	HAL_DATA_TYPE	*pHalData	= GET_HAL_DATA(padapter);
+	char	input[wrqu->length];
+	u32		valxcap, ret;
+
+	if (copy_from_user(input, wrqu->pointer, wrqu->length))
+		return -EFAULT;
+
+	RTW_INFO("%s:iwpriv in=%s\n", __func__, input);
+
+	ret = sscanf(input, "xcap=%d", &valxcap);
+
+	pHalData->crystal_cap = (u8)valxcap;
+	hal_set_crystal_cap(padapter , valxcap);
+
+	sprintf(extra, "Set xcap=%d", valxcap);
+	wrqu->length = strlen(extra) + 1;
+
+	return 0;
+
+}
+
+
+int rtw_mp_SetRFPath(struct net_device *dev,
+		     struct iw_request_info *info,
+		     struct iw_point *wrqu, char *extra)
+{
+	PADAPTER padapter = rtw_netdev_priv(dev);
+	char	input[wrqu->length];
+	int		bMain = 1, bTurnoff = 1;
+#ifdef CONFIG_ANTENNA_DIVERSITY
+	u8 ret = _TRUE;
+#endif
+
+	RTW_INFO("%s:iwpriv in=%s\n", __func__, input);
+
+	if (copy_from_user(input, wrqu->pointer, wrqu->length))
+		return -EFAULT;
+
+	bMain = strncmp(input, "1", 2); /* strncmp TRUE is 0*/
+	bTurnoff = strncmp(input, "0", 3); /* strncmp TRUE is 0*/
+
+	_rtw_memset(extra, 0, wrqu->length);
+#ifdef CONFIG_ANTENNA_DIVERSITY
+	if (bMain == 0)
+		ret = rtw_mp_set_antdiv(padapter, _TRUE);
+	else
+		ret = rtw_mp_set_antdiv(padapter, _FALSE);
+	if (ret == _FALSE)
+		RTW_INFO("%s:ANTENNA_DIVERSITY FAIL\n", __func__);
+#endif
+
+	if (bMain == 0) {
+		MP_PHY_SetRFPathSwitch(padapter, _TRUE);
+		RTW_INFO("%s:PHY_SetRFPathSwitch=TRUE\n", __func__);
+		sprintf(extra, "mp_setrfpath Main\n");
+
+	} else if (bTurnoff == 0) {
+		MP_PHY_SetRFPathSwitch(padapter, _FALSE);
+		RTW_INFO("%s:PHY_SetRFPathSwitch=FALSE\n", __func__);
+		sprintf(extra, "mp_setrfpath Aux\n");
+	} else {
+		bMain = MP_PHY_QueryRFPathSwitch(padapter);
+		RTW_INFO("%s:PHY_SetRFPathSwitch = %s\n", __func__, (bMain ? "Main":"Aux"));
+		sprintf(extra, "mp_setrfpath %s\n" , (bMain ? "Main":"Aux"));
+	}
+
+	wrqu->length = strlen(extra);
+
+	return 0;
+}
+
+
+int rtw_mp_switch_rf_path(struct net_device *dev,
+			struct iw_request_info *info,
+			struct iw_point *wrqu, char *extra)
+{
+	PADAPTER padapter = rtw_netdev_priv(dev);
+	struct mp_priv *pmp_priv;
+	char	input[wrqu->length];
+	int		bwlg = 1, bwla = 1, btg = 1, bbt=1;
+	u8 ret = 0;
+
+
+	if (copy_from_user(input, wrqu->pointer, wrqu->length))
+		return -EFAULT;
+
+	pmp_priv = &padapter->mppriv;
+
+	RTW_INFO("%s: in=%s\n", __func__, input);
+
+	bwlg = strncmp(input, "WLG", 3); /* strncmp TRUE is 0*/
+	bwla = strncmp(input, "WLA", 3); /* strncmp TRUE is 0*/
+	btg = strncmp(input, "BTG", 3); /* strncmp TRUE is 0*/
+	bbt = strncmp(input, "BT", 3); /* strncmp TRUE is 0*/
+
+	_rtw_memset(extra, 0, wrqu->length);
+#ifdef CONFIG_RTL8821C /* only support for 8821c wlg/wla/btg/bt RF switch path */
+	if (bwlg == 0) {
+		pmp_priv->rf_path_cfg = SWITCH_TO_WLG;
+		sprintf(extra, "switch rf path WLG\n");
+	} else if (bwla == 0) {
+		pmp_priv->rf_path_cfg = SWITCH_TO_WLA;
+		sprintf(extra, "switch rf path WLA\n");
+	} else if (btg == 0) {
+		pmp_priv->rf_path_cfg = SWITCH_TO_BTG;
+		sprintf(extra, "switch rf path BTG\n");
+	} else if (bbt == 0) {
+		pmp_priv->rf_path_cfg = SWITCH_TO_BT;
+		sprintf(extra, "switch rf path BG\n");
+	} else {
+		sprintf(extra, "Error set %s\n", __func__);
+		return -EFAULT;
+	}
+
+	mp_phy_switch_rf_path_set(padapter, &pmp_priv->rf_path_cfg);
+#endif
+
+	wrqu->length = strlen(extra);
+
+	return ret;
+
+}
+int rtw_mp_QueryDrv(struct net_device *dev,
+		    struct iw_request_info *info,
+		    union iwreq_data *wrqu, char *extra)
+{
+	PADAPTER padapter = rtw_netdev_priv(dev);
+	char	input[wrqu->data.length];
+	int	qAutoLoad = 1;
+
+	PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter);
+
+	if (copy_from_user(input, wrqu->data.pointer, wrqu->data.length))
+		return -EFAULT;
+	RTW_INFO("%s:iwpriv in=%s\n", __func__, input);
+
+	qAutoLoad = strncmp(input, "autoload", 8); /* strncmp TRUE is 0*/
+
+	if (qAutoLoad == 0) {
+		RTW_INFO("%s:qAutoLoad\n", __func__);
+
+		if (pHalData->bautoload_fail_flag)
+			sprintf(extra, "fail");
+		else
+			sprintf(extra, "ok");
+	}
+	wrqu->data.length = strlen(extra) + 1;
+	return 0;
+}
+
+
+int rtw_mp_PwrCtlDM(struct net_device *dev,
+		    struct iw_request_info *info,
+		    struct iw_point *wrqu, char *extra)
+{
+	PADAPTER padapter = rtw_netdev_priv(dev);
+	u8		input[wrqu->length];
+	int		bstart = 1;
+
+	if (copy_from_user(input, wrqu->pointer, wrqu->length))
+		return -EFAULT;
+
+	bstart = strncmp(input, "start", 5); /* strncmp TRUE is 0*/
+	if (bstart == 0) {
+		sprintf(extra, "PwrCtlDM start\n");
+		MPT_PwrCtlDM(padapter, 1);
+	} else {
+		sprintf(extra, "PwrCtlDM stop\n");
+		MPT_PwrCtlDM(padapter, 0);
+	}
+	wrqu->length = strlen(extra);
+
+	return 0;
+}
+
+int rtw_mp_iqk(struct net_device *dev,
+		 struct iw_request_info *info,
+		 struct iw_point *wrqu, char *extra)
+{
+	PADAPTER padapter = rtw_netdev_priv(dev);
+
+	rtw_mp_trigger_iqk(padapter);
+
+	return 0;
+}
+
+int rtw_mp_lck(struct net_device *dev,
+		 struct iw_request_info *info,
+		 struct iw_point *wrqu, char *extra)
+{
+	PADAPTER padapter = rtw_netdev_priv(dev);
+
+	rtw_mp_trigger_lck(padapter);
+
+	return 0;
+}
+
+int rtw_mp_getver(struct net_device *dev,
+		  struct iw_request_info *info,
+		  union iwreq_data *wrqu, char *extra)
+{
+	PADAPTER padapter = rtw_netdev_priv(dev);
+	struct mp_priv *pmp_priv;
+
+	pmp_priv = &padapter->mppriv;
+
+	if (copy_from_user(extra, wrqu->data.pointer, wrqu->data.length))
+		return -EFAULT;
+
+	sprintf(extra, "rtwpriv=%d\n", RTWPRIV_VER_INFO);
+	wrqu->data.length = strlen(extra);
+	return 0;
+}
+
+
+int rtw_mp_mon(struct net_device *dev,
+	       struct iw_request_info *info,
+	       union iwreq_data *wrqu, char *extra)
+{
+	PADAPTER padapter = rtw_netdev_priv(dev);
+	struct mp_priv *pmp_priv = &padapter->mppriv;
+	struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
+	struct hal_ops *pHalFunc = &padapter->hal_func;
+	NDIS_802_11_NETWORK_INFRASTRUCTURE networkType;
+	int bstart = 1, bstop = 1;
+
+	networkType = Ndis802_11Infrastructure;
+	if (copy_from_user(extra, wrqu->data.pointer, wrqu->data.length))
+		return -EFAULT;
+
+	*(extra + wrqu->data.length) = '\0';
+	rtw_pm_set_ips(padapter, IPS_NONE);
+	LeaveAllPowerSaveMode(padapter);
+
+#ifdef CONFIG_MP_INCLUDED
+	if (init_mp_priv(padapter) == _FAIL)
+		RTW_INFO("%s: initialize MP private data Fail!\n", __func__);
+	padapter->mppriv.channel = 6;
+
+	bstart = strncmp(extra, "start", 5); /* strncmp TRUE is 0*/
+	bstop = strncmp(extra, "stop", 4); /* strncmp TRUE is 0*/
+	if (bstart == 0) {
+		mp_join(padapter, WIFI_FW_ADHOC_STATE);
+		SetPacketRx(padapter, _TRUE, _FALSE);
+		SetChannel(padapter);
+		pmp_priv->rx_bindicatePkt = _TRUE;
+		pmp_priv->bRTWSmbCfg = _TRUE;
+		sprintf(extra, "monitor mode start\n");
+	} else if (bstop == 0) {
+		SetPacketRx(padapter, _FALSE, _FALSE);
+		pmp_priv->rx_bindicatePkt = _FALSE;
+		pmp_priv->bRTWSmbCfg = _FALSE;
+		padapter->registrypriv.mp_mode = 1;
+		pHalFunc->hal_deinit(padapter);
+		padapter->registrypriv.mp_mode = 0;
+		pHalFunc->hal_init(padapter);
+		/*rtw_disassoc_cmd(padapter, 0, 0);*/
+		if (check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE) {
+			rtw_disassoc_cmd(padapter, 500, 0);
+			rtw_indicate_disconnect(padapter, 0, _FALSE);
+			/*rtw_free_assoc_resources_cmd(padapter, _TRUE, 0);*/
+		}
+		rtw_pm_set_ips(padapter, IPS_NORMAL);
+		sprintf(extra, "monitor mode Stop\n");
+	}
+#endif
+	wrqu->data.length = strlen(extra);
+	return 0;
+}
+
+int rtw_mp_pretx_proc(PADAPTER padapter, u8 bStartTest, char *extra)
+{
+	struct mp_priv *pmp_priv = &padapter->mppriv;
+	char *pextra = extra;
+
+	switch (pmp_priv->mode) {
+
+	case MP_PACKET_TX:
+		if (bStartTest == 0) {
+			pmp_priv->tx.stop = 1;
+			pmp_priv->mode = MP_ON;
+			sprintf(extra, "Stop continuous Tx");
+		} else if (pmp_priv->tx.stop == 1) {
+			pextra = extra + strlen(extra);
+			pextra += sprintf(pextra, "\nStart continuous DA=ffffffffffff len=1500 count=%u\n", pmp_priv->tx.count);
+			pmp_priv->tx.stop = 0;
+			SetPacketTx(padapter);
+		} else
+			return -EFAULT;
+		return 0;
+	case MP_SINGLE_TONE_TX:
+		if (bStartTest != 0)
+			strcat(extra, "\nStart continuous DA=ffffffffffff len=1500\n infinite=yes.");
+		SetSingleToneTx(padapter, (u8)bStartTest);
+		break;
+	case MP_CONTINUOUS_TX:
+		if (bStartTest != 0)
+			strcat(extra, "\nStart continuous DA=ffffffffffff len=1500\n infinite=yes.");
+		SetContinuousTx(padapter, (u8)bStartTest);
+		break;
+	case MP_CARRIER_SUPPRISSION_TX:
+		if (bStartTest != 0) {
+			if (HwRateToMPTRate(pmp_priv->rateidx) <= MPT_RATE_11M)
+				strcat(extra, "\nStart continuous DA=ffffffffffff len=1500\n infinite=yes.");
+			else
+				strcat(extra, "\nSpecify carrier suppression but not CCK rate");
+		}
+		SetCarrierSuppressionTx(padapter, (u8)bStartTest);
+		break;
+	case MP_SINGLE_CARRIER_TX:
+		if (bStartTest != 0)
+			strcat(extra, "\nStart continuous DA=ffffffffffff len=1500\n infinite=yes.");
+		SetSingleCarrierTx(padapter, (u8)bStartTest);
+		break;
+
+	default:
+		sprintf(extra, "Error! Continuous-Tx is not on-going.");
+		return -EFAULT;
+	}
+
+	if (bStartTest == 1 && pmp_priv->mode != MP_ON) {
+		struct mp_priv *pmp_priv = &padapter->mppriv;
+
+		if (pmp_priv->tx.stop == 0) {
+			pmp_priv->tx.stop = 1;
+			rtw_msleep_os(5);
+		}
+#ifdef CONFIG_80211N_HT
+		if(padapter->registrypriv.ht_enable &&
+			is_supported_ht(padapter->registrypriv.wireless_mode))
+			pmp_priv->tx.attrib.ht_en = 1;
+#endif
+		pmp_priv->tx.stop = 0;
+		pmp_priv->tx.count = 1;
+		SetPacketTx(padapter);
+	} else
+		pmp_priv->mode = MP_ON;
+
+#if defined(CONFIG_RTL8812A)
+	if (IS_HARDWARE_TYPE_8812AU(padapter)) {
+		/* <20130425, Kordan> Turn off OFDM Rx to prevent from CCA causing Tx hang.*/
+		if (pmp_priv->mode == MP_PACKET_TX)
+			phy_set_bb_reg(padapter, rCCAonSec_Jaguar, BIT3, 1);
+		else
+			phy_set_bb_reg(padapter, rCCAonSec_Jaguar, BIT3, 0);
+	}
+#endif
+
+	return 0;
+}
+
+
+int rtw_mp_tx(struct net_device *dev,
+	      struct iw_request_info *info,
+	      union iwreq_data *wrqu, char *extra)
+{
+	PADAPTER padapter = rtw_netdev_priv(dev);
+	HAL_DATA_TYPE	*pHalData	= GET_HAL_DATA(padapter);
+	struct mp_priv *pmp_priv = &padapter->mppriv;
+	PMPT_CONTEXT		pMptCtx = &(padapter->mppriv.mpt_ctx);
+	char *pextra = extra;
+	u32 bandwidth = 0, sg = 0, channel = 6, txpower = 40, rate = 108, ant = 0, txmode = 1, count = 0;
+	u8 bStartTest = 1, status = 0;
+#ifdef CONFIG_MP_VHT_HW_TX_MODE
+	u8 Idx = 0, tmpU1B;
+#endif
+	u16 antenna = 0;
+
+	if (copy_from_user(extra, wrqu->data.pointer, wrqu->data.length))
+		return -EFAULT;
+	RTW_INFO("extra = %s\n", extra);
+#ifdef CONFIG_CONCURRENT_MODE
+	if (!is_primary_adapter(padapter)) {
+		sprintf(extra, "Error: MP mode can't support Virtual Adapter, Please to use main Adapter.\n");
+		wrqu->data.length = strlen(extra);
+		return 0;
+	}
+#endif
+
+	if (strncmp(extra, "stop", 3) == 0) {
+		bStartTest = 0; /* To set Stop*/
+		pmp_priv->tx.stop = 1;
+		sprintf(extra, "Stop continuous Tx");
+		status = rtw_mp_pretx_proc(padapter, bStartTest, extra);
+		wrqu->data.length = strlen(extra);
+		return status;
+	} else if (strncmp(extra, "count", 5) == 0) {
+		if (sscanf(extra, "count=%d", &count) < 1)
+			RTW_INFO("Got Count=%d]\n", count);
+		pmp_priv->tx.count = count;
+		return 0;
+	} else if (strncmp(extra, "setting", 7) == 0) {
+		_rtw_memset(extra, 0, wrqu->data.length);
+		pextra += sprintf(pextra, "Current Setting :\n Channel:%d", pmp_priv->channel);
+		pextra += sprintf(pextra, "\n Bandwidth:%d", pmp_priv->bandwidth);
+		pextra += sprintf(pextra, "\n Rate index:%d", pmp_priv->rateidx);
+		pextra += sprintf(pextra, "\n TxPower index:%d", pmp_priv->txpoweridx);
+		pextra += sprintf(pextra, "\n Antenna TxPath:%d", pmp_priv->antenna_tx);
+		pextra += sprintf(pextra, "\n Antenna RxPath:%d", pmp_priv->antenna_rx);
+		pextra += sprintf(pextra, "\n MP Mode:%d", pmp_priv->mode);
+		wrqu->data.length = strlen(extra);
+		return 0;
+#ifdef CONFIG_MP_VHT_HW_TX_MODE
+	} else if (strncmp(extra, "pmact", 5) == 0) {
+		if (strncmp(extra, "pmact=", 6) == 0) {
+			_rtw_memset(&pMptCtx->PMacTxInfo, 0, sizeof(pMptCtx->PMacTxInfo));
+			if (strncmp(extra, "pmact=start", 11) == 0) {
+				pMptCtx->PMacTxInfo.bEnPMacTx = _TRUE;
+				sprintf(extra, "Set PMac Tx Mode start\n");
+			} else {
+				pMptCtx->PMacTxInfo.bEnPMacTx = _FALSE;
+				sprintf(extra, "Set PMac Tx Mode Stop\n");
+			}
+			if (pMptCtx->bldpc == TRUE)
+				pMptCtx->PMacTxInfo.bLDPC = _TRUE;
+
+			if (pMptCtx->bstbc == TRUE)
+				pMptCtx->PMacTxInfo.bSTBC = _TRUE;
+
+			pMptCtx->PMacTxInfo.bSPreamble = pmp_priv->preamble;
+			pMptCtx->PMacTxInfo.bSGI = pmp_priv->preamble;
+			pMptCtx->PMacTxInfo.BandWidth = pmp_priv->bandwidth;
+			pMptCtx->PMacTxInfo.TX_RATE = HwRateToMPTRate(pmp_priv->rateidx);
+
+			pMptCtx->PMacTxInfo.Mode = pMptCtx->HWTxmode;
+
+			pMptCtx->PMacTxInfo.NDP_sound = FALSE;/*(Adapter.PacketType == NDP_PKT)?TRUE:FALSE;*/
+
+			if (padapter->mppriv.pktInterval == 0)
+				pMptCtx->PMacTxInfo.PacketPeriod = 100;
+			else
+				pMptCtx->PMacTxInfo.PacketPeriod = padapter->mppriv.pktInterval;
+
+			if (padapter->mppriv.pktLength < 1000)
+				pMptCtx->PMacTxInfo.PacketLength = 1000;
+			else
+				pMptCtx->PMacTxInfo.PacketLength = padapter->mppriv.pktLength;
+
+			pMptCtx->PMacTxInfo.PacketPattern  = rtw_random32() % 0xFF;
+
+			if (padapter->mppriv.tx_pktcount != 0)
+				pMptCtx->PMacTxInfo.PacketCount = padapter->mppriv.tx_pktcount;
+
+			pMptCtx->PMacTxInfo.Ntx = 0;
+			for (Idx = 16; Idx < 20; Idx++) {
+				tmpU1B = (padapter->mppriv.antenna_tx >> Idx) & 1;
+				if (tmpU1B)
+					pMptCtx->PMacTxInfo.Ntx++;
+			}
+
+			_rtw_memset(pMptCtx->PMacTxInfo.MacAddress, 0xFF, ETH_ALEN);
+
+			PMAC_Get_Pkt_Param(&pMptCtx->PMacTxInfo, &pMptCtx->PMacPktInfo);
+
+			if (MPT_IS_CCK_RATE(pMptCtx->PMacTxInfo.TX_RATE))
+
+				CCK_generator(&pMptCtx->PMacTxInfo, &pMptCtx->PMacPktInfo);
+			else {
+				PMAC_Nsym_generator(&pMptCtx->PMacTxInfo, &pMptCtx->PMacPktInfo);
+				/* 24 BIT*/
+				L_SIG_generator(pMptCtx->PMacPktInfo.N_sym, &pMptCtx->PMacTxInfo, &pMptCtx->PMacPktInfo);
+			}
+			/*	48BIT*/
+			if (MPT_IS_HT_RATE(pMptCtx->PMacTxInfo.TX_RATE))
+				HT_SIG_generator(&pMptCtx->PMacTxInfo, &pMptCtx->PMacPktInfo);
+			else if (MPT_IS_VHT_RATE(pMptCtx->PMacTxInfo.TX_RATE)) {
+				/*	48BIT*/
+				VHT_SIG_A_generator(&pMptCtx->PMacTxInfo, &pMptCtx->PMacPktInfo);
+
+				/*	26/27/29 BIT  & CRC 8 BIT*/
+				VHT_SIG_B_generator(&pMptCtx->PMacTxInfo);
+
+				/* 32 BIT*/
+				VHT_Delimiter_generator(&pMptCtx->PMacTxInfo);
+			}
+
+			mpt_ProSetPMacTx(padapter);
+
+		} else if (strncmp(extra, "pmact,mode=", 11) == 0) {
+			int txmode = 0;
+
+			if (sscanf(extra, "pmact,mode=%d", &txmode) > 0) {
+				if (txmode == 1) {
+					pMptCtx->HWTxmode = CONTINUOUS_TX;
+					sprintf(extra, "\t Config HW Tx mode = CONTINUOUS_TX\n");
+				} else if (txmode == 2) {
+					pMptCtx->HWTxmode = OFDM_Single_Tone_TX;
+					sprintf(extra, "\t Config HW Tx mode = OFDM_Single_Tone_TX\n");
+				} else {
+					pMptCtx->HWTxmode = PACKETS_TX;
+					sprintf(extra, "\t Config HW Tx mode = PACKETS_TX\n");
+				}
+			} else {
+				pMptCtx->HWTxmode = PACKETS_TX;
+				sprintf(extra, "\t Config HW Tx mode=\n 0 = PACKETS_TX\n 1 = CONTINUOUS_TX\n 2 = OFDM_Single_Tone_TX");
+			}
+		} else if (strncmp(extra, "pmact,", 6) == 0) {
+			int PacketPeriod = 0, PacketLength = 0, PacketCout = 0;
+			int bldpc = 0, bstbc = 0;
+
+			if (sscanf(extra, "pmact,period=%d", &PacketPeriod) > 0) {
+				padapter->mppriv.pktInterval = PacketPeriod;
+				RTW_INFO("PacketPeriod=%d\n", padapter->mppriv.pktInterval);
+				sprintf(extra, "PacketPeriod [1~255]= %d\n", padapter->mppriv.pktInterval);
+
+			} else if (sscanf(extra, "pmact,length=%d", &PacketLength) > 0) {
+				padapter->mppriv.pktLength = PacketLength;
+				RTW_INFO("PacketPeriod=%d\n", padapter->mppriv.pktLength);
+				sprintf(extra, "PacketLength[~65535]=%d\n", padapter->mppriv.pktLength);
+
+			} else if (sscanf(extra, "pmact,count=%d", &PacketCout) > 0) {
+				padapter->mppriv.tx_pktcount = PacketCout;
+				RTW_INFO("Packet Cout =%d\n", padapter->mppriv.tx_pktcount);
+				sprintf(extra, "Packet Cout =%d\n", padapter->mppriv.tx_pktcount);
+
+			} else if (sscanf(extra, "pmact,ldpc=%d", &bldpc) > 0) {
+				pMptCtx->bldpc = bldpc;
+				RTW_INFO("Set LDPC =%d\n", pMptCtx->bldpc);
+				sprintf(extra, "Set LDPC =%d\n", pMptCtx->bldpc);
+
+			} else if (sscanf(extra, "pmact,stbc=%d", &bstbc) > 0) {
+				pMptCtx->bstbc = bstbc;
+				RTW_INFO("Set STBC =%d\n", pMptCtx->bstbc);
+				sprintf(extra, "Set STBC =%d\n", pMptCtx->bstbc);
+			} else
+				sprintf(extra, "\n period={1~255}\n length={1000~65535}\n count={0~}\n ldpc={0/1}\n stbc={0/1}");
+
+		}
+
+		wrqu->data.length = strlen(extra);
+		return 0;
+#endif
+	} else {
+
+		if (sscanf(extra, "ch=%d,bw=%d,rate=%d,pwr=%d,ant=%d,tx=%d", &channel, &bandwidth, &rate, &txpower, &ant, &txmode) < 6) {
+			RTW_INFO("Invalid format [ch=%d,bw=%d,rate=%d,pwr=%d,ant=%d,tx=%d]\n", channel, bandwidth, rate, txpower, ant, txmode);
+			_rtw_memset(extra, 0, wrqu->data.length);
+			pextra += sprintf(pextra, "\n Please input correct format as bleow:\n");
+			pextra += sprintf(pextra, "\t ch=%d,bw=%d,rate=%d,pwr=%d,ant=%d,tx=%d\n", channel, bandwidth, rate, txpower, ant, txmode);
+			pextra += sprintf(pextra, "\n [ ch : BGN = <1~14> , A or AC = <36~165> ]");
+			pextra += sprintf(pextra, "\n [ bw : Bandwidth: 0 = 20M, 1 = 40M, 2 = 80M ]");
+			pextra += sprintf(pextra, "\n [ rate :	CCK: 1 2 5.5 11M X 2 = < 2 4 11 22 >]");
+			pextra += sprintf(pextra, "\n [		OFDM: 6 9 12 18 24 36 48 54M X 2 = < 12 18 24 36 48 72 96 108>");
+			pextra += sprintf(pextra, "\n [		HT 1S2SS MCS0 ~ MCS15 : < [MCS0]=128 ~ [MCS7]=135 ~ [MCS15]=143 >");
+			pextra += sprintf(pextra, "\n [		HT 3SS MCS16 ~ MCS32 : < [MCS16]=144 ~ [MCS23]=151 ~ [MCS32]=159 >");
+			pextra += sprintf(pextra, "\n [		VHT 1SS MCS0 ~ MCS9 : < [MCS0]=160 ~ [MCS9]=169 >");
+			pextra += sprintf(pextra, "\n [ txpower : 1~63 power index");
+			pextra += sprintf(pextra, "\n [ ant : <A = 1, B = 2, C = 4, D = 8> ,2T ex: AB=3 BC=6 CD=12");
+			pextra += sprintf(pextra, "\n [ txmode : < 0 = CONTINUOUS_TX, 1 = PACKET_TX, 2 = SINGLE_TONE_TX, 3 = CARRIER_SUPPRISSION_TX, 4 = SINGLE_CARRIER_TX>\n");
+			wrqu->data.length = strlen(extra);
+			return status;
+
+		} else {
+			char *pextra = extra;
+			RTW_INFO("Got format [ch=%d,bw=%d,rate=%d,pwr=%d,ant=%d,tx=%d]\n", channel, bandwidth, rate, txpower, ant, txmode);
+			_rtw_memset(extra, 0, wrqu->data.length);
+			sprintf(extra, "Change Current channel %d to channel %d", padapter->mppriv.channel , channel);
+			padapter->mppriv.channel = channel;
+			SetChannel(padapter);
+			pHalData->current_channel = channel;
+
+			if (bandwidth == 1)
+				bandwidth = CHANNEL_WIDTH_40;
+			else if (bandwidth == 2)
+				bandwidth = CHANNEL_WIDTH_80;
+			pextra = extra + strlen(pextra);
+			pextra += sprintf(pextra, "\nChange Current Bandwidth %d to Bandwidth %d", padapter->mppriv.bandwidth, bandwidth);
+			padapter->mppriv.bandwidth = (u8)bandwidth;
+			padapter->mppriv.preamble = sg;
+			SetBandwidth(padapter);
+			pHalData->current_channel_bw = bandwidth;
+
+			pextra += sprintf(pextra, "\nSet power level :%d", txpower);
+			padapter->mppriv.txpoweridx = (u8)txpower;
+			pMptCtx->TxPwrLevel[RF_PATH_A] = (u8)txpower;
+			pMptCtx->TxPwrLevel[RF_PATH_B] = (u8)txpower;
+			pMptCtx->TxPwrLevel[RF_PATH_C] = (u8)txpower;
+			pMptCtx->TxPwrLevel[RF_PATH_D]  = (u8)txpower;
+			SetTxPower(padapter);
+
+			RTW_INFO("%s: bw=%d sg=%d\n", __func__, bandwidth, sg);
+
+			if (rate <= 0x7f)
+				rate = wifirate2_ratetbl_inx((u8)rate);
+			else if (rate < 0xC8)
+				rate = (rate - 0x80 + MPT_RATE_MCS0);
+			/*HT  rate 0x80(MCS0)  ~ 0x8F(MCS15) ~ 0x9F(MCS31) 128~159
+			VHT1SS~2SS rate 0xA0 (VHT1SS_MCS0 44) ~ 0xB3 (VHT2SS_MCS9 #63) 160~179
+			VHT rate 0xB4 (VHT3SS_MCS0 64) ~ 0xC7 (VHT2SS_MCS9 #83) 180~199
+			else
+			VHT rate 0x90(VHT1SS_MCS0) ~ 0x99(VHT1SS_MCS9) 144~153
+			rate =(rate - MPT_RATE_VHT1SS_MCS0);
+			*/
+			RTW_INFO("%s: rate index=%d\n", __func__, rate);
+			if (rate >= MPT_RATE_LAST)
+				return -EINVAL;
+			pextra += sprintf(pextra, "\nSet data rate to %d index %d", padapter->mppriv.rateidx, rate);
+
+			padapter->mppriv.rateidx = rate;
+			pMptCtx->mpt_rate_index = rate;
+			SetDataRate(padapter);
+
+			pextra += sprintf(pextra, "\nSet Antenna Path :%d", ant);
+			switch (ant) {
+			case 1:
+				antenna = ANTENNA_A;
+				break;
+			case 2:
+				antenna = ANTENNA_B;
+				break;
+			case 4:
+				antenna = ANTENNA_C;
+				break;
+			case 8:
+				antenna = ANTENNA_D;
+				break;
+			case 3:
+				antenna = ANTENNA_AB;
+				break;
+			case 5:
+				antenna = ANTENNA_AC;
+				break;
+			case 9:
+				antenna = ANTENNA_AD;
+				break;
+			case 6:
+				antenna = ANTENNA_BC;
+				break;
+			case 10:
+				antenna = ANTENNA_BD;
+				break;
+			case 12:
+				antenna = ANTENNA_CD;
+				break;
+			case 7:
+				antenna = ANTENNA_ABC;
+				break;
+			case 14:
+				antenna = ANTENNA_BCD;
+				break;
+			case 11:
+				antenna = ANTENNA_ABD;
+				break;
+			case 15:
+				antenna = ANTENNA_ABCD;
+				break;
+			}
+			RTW_INFO("%s: antenna=0x%x\n", __func__, antenna);
+			padapter->mppriv.antenna_tx = antenna;
+			padapter->mppriv.antenna_rx = antenna;
+			pHalData->antenna_tx_path = antenna;
+			SetAntenna(padapter);
+
+			if (txmode == 0)
+				pmp_priv->mode = MP_CONTINUOUS_TX;
+			else if (txmode == 1) {
+				pmp_priv->mode = MP_PACKET_TX;
+				pmp_priv->tx.count = count;
+			} else if (txmode == 2)
+				pmp_priv->mode = MP_SINGLE_TONE_TX;
+			else if (txmode == 3)
+				pmp_priv->mode = MP_CARRIER_SUPPRISSION_TX;
+			else if (txmode == 4)
+				pmp_priv->mode = MP_SINGLE_CARRIER_TX;
+
+			status = rtw_mp_pretx_proc(padapter, bStartTest, extra);
+		}
+
+	}
+
+	wrqu->data.length = strlen(extra);
+	return status;
+}
+
+
+int rtw_mp_rx(struct net_device *dev,
+	      struct iw_request_info *info,
+	      union iwreq_data *wrqu, char *extra)
+{
+	PADAPTER padapter = rtw_netdev_priv(dev);
+	HAL_DATA_TYPE	*pHalData	= GET_HAL_DATA(padapter);
+	struct mp_priv *pmp_priv = &padapter->mppriv;
+	char *pextra = extra;
+	u32 bandwidth = 0, sg = 0, channel = 6, ant = 0;
+	u16 antenna = 0;
+	u8 bStartRx = 0;
+
+	if (copy_from_user(extra, wrqu->data.pointer, wrqu->data.length))
+		return -EFAULT;
+
+#ifdef CONFIG_CONCURRENT_MODE
+	if (!is_primary_adapter(padapter)) {
+		sprintf(extra, "Error: MP mode can't support Virtual Adapter, Please to use main Adapter.\n");
+		wrqu->data.length = strlen(extra);
+		return 0;
+	}
+#endif
+
+	if (strncmp(extra, "stop", 4) == 0) {
+		_rtw_memset(extra, 0, wrqu->data.length);
+		SetPacketRx(padapter, bStartRx, _FALSE);
+		pmp_priv->bmac_filter = _FALSE;
+		sprintf(extra, "Received packet OK:%d CRC error:%d ,Filter out:%d", padapter->mppriv.rx_pktcount, padapter->mppriv.rx_crcerrpktcount, padapter->mppriv.rx_pktcount_filter_out);
+		wrqu->data.length = strlen(extra);
+		return 0;
+
+	} else if (sscanf(extra, "ch=%d,bw=%d,ant=%d", &channel, &bandwidth, &ant) < 3) {
+		RTW_INFO("Invalid format [ch=%d,bw=%d,ant=%d]\n", channel, bandwidth, ant);
+		_rtw_memset(extra, 0, wrqu->data.length);
+		pextra += sprintf(pextra, "\n Please input correct format as bleow:\n");
+		pextra += sprintf(pextra, "\t ch=%d,bw=%d,ant=%d\n", channel, bandwidth, ant);
+		pextra += sprintf(pextra, "\n [ ch : BGN = <1~14> , A or AC = <36~165> ]");
+		pextra += sprintf(pextra, "\n [ bw : Bandwidth: 0 = 20M, 1 = 40M, 2 = 80M ]");
+		pextra += sprintf(pextra, "\n [ ant : <A = 1, B = 2, C = 4, D = 8> ,2T ex: AB=3 BC=6 CD=12");
+		wrqu->data.length = strlen(extra);
+		return 0;
+
+	} else {
+		char *pextra = extra;
+		bStartRx = 1;
+		RTW_INFO("Got format [ch=%d,bw=%d,ant=%d]\n", channel, bandwidth, ant);
+		_rtw_memset(extra, 0, wrqu->data.length);
+		sprintf(extra, "Change Current channel %d to channel %d", padapter->mppriv.channel , channel);
+		padapter->mppriv.channel = channel;
+		SetChannel(padapter);
+		pHalData->current_channel = channel;
+
+		if (bandwidth == 1)
+			bandwidth = CHANNEL_WIDTH_40;
+		else if (bandwidth == 2)
+			bandwidth = CHANNEL_WIDTH_80;
+		pextra = extra + strlen(extra);
+		pextra += sprintf(pextra, "\nChange Current Bandwidth %d to Bandwidth %d", padapter->mppriv.bandwidth, bandwidth);
+		padapter->mppriv.bandwidth = (u8)bandwidth;
+		padapter->mppriv.preamble = sg;
+		SetBandwidth(padapter);
+		pHalData->current_channel_bw = bandwidth;
+
+		pextra += sprintf(pextra, "\nSet Antenna Path :%d", ant);
+		switch (ant) {
+		case 1:
+			antenna = ANTENNA_A;
+			break;
+		case 2:
+			antenna = ANTENNA_B;
+			break;
+		case 4:
+			antenna = ANTENNA_C;
+			break;
+		case 8:
+			antenna = ANTENNA_D;
+			break;
+		case 3:
+			antenna = ANTENNA_AB;
+			break;
+		case 5:
+			antenna = ANTENNA_AC;
+			break;
+		case 9:
+			antenna = ANTENNA_AD;
+			break;
+		case 6:
+			antenna = ANTENNA_BC;
+			break;
+		case 10:
+			antenna = ANTENNA_BD;
+			break;
+		case 12:
+			antenna = ANTENNA_CD;
+			break;
+		case 7:
+			antenna = ANTENNA_ABC;
+			break;
+		case 14:
+			antenna = ANTENNA_BCD;
+			break;
+		case 11:
+			antenna = ANTENNA_ABD;
+			break;
+		case 15:
+			antenna = ANTENNA_ABCD;
+			break;
+		}
+		RTW_INFO("%s: antenna=0x%x\n", __func__, antenna);
+		padapter->mppriv.antenna_tx = antenna;
+		padapter->mppriv.antenna_rx = antenna;
+		pHalData->antenna_tx_path = antenna;
+		SetAntenna(padapter);
+
+		strcat(extra, "\nstart Rx");
+		SetPacketRx(padapter, bStartRx, _FALSE);
+	}
+	wrqu->data.length = strlen(extra);
+	return 0;
+}
+
+
+int rtw_mp_hwtx(struct net_device *dev,
+		struct iw_request_info *info,
+		union iwreq_data *wrqu, char *extra)
+{
+	PADAPTER padapter = rtw_netdev_priv(dev);
+	struct mp_priv *pmp_priv = &padapter->mppriv;
+	PMPT_CONTEXT		pMptCtx = &(padapter->mppriv.mpt_ctx);
+
+#if defined(CONFIG_RTL8814A) || defined(CONFIG_RTL8821B) || defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C)
+	u8		input[wrqu->data.length];
+
+	if (copy_from_user(input, wrqu->data.pointer, wrqu->data.length))
+		return -EFAULT;
+
+	_rtw_memset(&pMptCtx->PMacTxInfo, 0, sizeof(RT_PMAC_TX_INFO));
+	_rtw_memcpy((void *)&pMptCtx->PMacTxInfo, (void *)input, sizeof(RT_PMAC_TX_INFO));
+	_rtw_memset(wrqu->data.pointer, 0, wrqu->data.length);
+
+	if (pMptCtx->PMacTxInfo.bEnPMacTx == 1 && pmp_priv->mode != MP_ON) {
+		sprintf(extra, "MP Tx Running, Please Set PMac Tx Mode Stop\n");
+		RTW_INFO("Error !!! MP Tx Running, Please Set PMac Tx Mode Stop\n");
+	} else {
+		RTW_INFO("To set MAC Tx mode\n");
+		mpt_ProSetPMacTx(padapter);
+		sprintf(extra, "Set PMac Tx Mode OK\n");
+	}
+	wrqu->data.length = strlen(extra);
+#endif
+	return 0;
+
+}
+
+int rtw_mp_pwrlmt(struct net_device *dev,
+			struct iw_request_info *info,
+			union iwreq_data *wrqu, char *extra)
+{
+	PADAPTER padapter = rtw_netdev_priv(dev);
+	struct registry_priv  *registry_par = &padapter->registrypriv;
+	u8 pwrlimtstat = 0;
+
+	if (copy_from_user(extra, wrqu->data.pointer, wrqu->data.length))
+		return -EFAULT;
+
+	*(extra + wrqu->data.length) = '\0';
+#ifdef CONFIG_TXPWR_LIMIT
+	pwrlimtstat = registry_par->RegEnableTxPowerLimit;
+	if (strncmp(extra, "off", 3) == 0 && strlen(extra) < 4) {
+		padapter->registrypriv.RegEnableTxPowerLimit = 0;
+		sprintf(extra, "Turn off Power Limit\n");
+
+	} else if (strncmp(extra, "on", 2) == 0 && strlen(extra) < 3) {
+		padapter->registrypriv.RegEnableTxPowerLimit = 1;
+		sprintf(extra, "Turn on Power Limit\n");
+
+	} else
+#endif
+		sprintf(extra, "Get Power Limit Status:%s\n", (pwrlimtstat == 1) ? "ON" : "OFF");
+
+
+	wrqu->data.length = strlen(extra);
+	return 0;
+}
+
+int rtw_mp_pwrbyrate(struct net_device *dev,
+			struct iw_request_info *info,
+			union iwreq_data *wrqu, char *extra)
+{
+	PADAPTER padapter = rtw_netdev_priv(dev);
+
+	if (copy_from_user(extra, wrqu->data.pointer, wrqu->data.length))
+		return -EFAULT;
+
+	*(extra + wrqu->data.length) = '\0';
+	if (strncmp(extra, "off", 3) == 0 && strlen(extra) < 4) {
+		padapter->registrypriv.RegEnableTxPowerByRate = 0;
+		sprintf(extra, "Turn off Tx Power by Rate\n");
+
+	} else if (strncmp(extra, "on", 2) == 0 && strlen(extra) < 3) {
+		padapter->registrypriv.RegEnableTxPowerByRate = 1;
+		sprintf(extra, "Turn On Tx Power by Rate\n");
+
+	} else {
+		sprintf(extra, "Get Power by Rate Status:%s\n", (padapter->registrypriv.RegEnableTxPowerByRate == 1) ? "ON" : "OFF");
+	}
+
+	wrqu->data.length = strlen(extra);
+	return 0;
+}
+
+int rtw_efuse_mask_file(struct net_device *dev,
+			struct iw_request_info *info,
+			union iwreq_data *wrqu, char *extra)
+{
+	char *rtw_efuse_mask_file_path;
+	u8 Status;
+	PADAPTER padapter = rtw_netdev_priv(dev);
+
+	_rtw_memset(maskfileBuffer, 0x00, sizeof(maskfileBuffer));
+
+	if (copy_from_user(extra, wrqu->data.pointer, wrqu->data.length))
+		return -EFAULT;
+
+	*(extra + wrqu->data.length) = '\0';
+	if (strncmp(extra, "off", 3) == 0 && strlen(extra) < 4) {
+		padapter->registrypriv.boffefusemask = 1;
+		sprintf(extra, "Turn off Efuse Mask\n");
+		wrqu->data.length = strlen(extra);
+		return 0;
+	}
+	if (strncmp(extra, "on", 2) == 0 && strlen(extra) < 3) {
+		padapter->registrypriv.boffefusemask = 0;
+		sprintf(extra, "Turn on Efuse Mask\n");
+		wrqu->data.length = strlen(extra);
+		return 0;
+	}
+	if (strncmp(extra, "data,", 5) == 0) {
+		u8	*pch;
+		char	*ptmp, tmp;
+		u8	count = 0;
+		u8	i = 0;
+
+		ptmp = extra;
+		pch = strsep(&ptmp, ",");
+
+		if ((pch == NULL) || (strlen(pch) == 0)) {
+			RTW_INFO("%s: parameter error(no cmd)!\n", __func__);
+			return -EFAULT;
+		}
+
+		do {
+			pch = strsep(&ptmp, ":");
+			if ((pch == NULL) || (strlen(pch) == 0))
+				break;
+			if (strlen(pch) != 2
+				|| IsHexDigit(*pch) == _FALSE
+				|| IsHexDigit(*(pch + 1)) == _FALSE
+				|| sscanf(pch, "%hhx", &tmp) != 1
+			) {
+				RTW_INFO("%s: invalid 8-bit hex! input format: data,01:23:45:67:89:ab:cd:ef...\n", __func__);
+				return -EFAULT;
+			}
+			maskfileBuffer[count++] = tmp;
+
+		 } while (count < 64);
+
+		for (i = 0; i < count; i++)
+			sprintf(extra, "%s:%02x", extra, maskfileBuffer[i]);
+
+		padapter->registrypriv.bFileMaskEfuse = _TRUE;
+
+		sprintf(extra, "%s\nLoad Efuse Mask data %d hex ok\n", extra, count);
+		wrqu->data.length = strlen(extra);
+		return 0;
+	}
+	rtw_efuse_mask_file_path = extra;
+
+	if (rtw_is_file_readable(rtw_efuse_mask_file_path) == _TRUE) {
+		RTW_INFO("%s do rtw_efuse_mask_file_read = %s! ,sizeof maskfileBuffer %zu\n", __func__, rtw_efuse_mask_file_path, sizeof(maskfileBuffer));
+		Status = rtw_efuse_file_read(padapter, rtw_efuse_mask_file_path, maskfileBuffer, sizeof(maskfileBuffer));
+		if (Status == _TRUE) {
+			padapter->registrypriv.bFileMaskEfuse = _TRUE;
+			sprintf(extra, "efuse mask file read OK\n");
+		} else {
+			padapter->registrypriv.bFileMaskEfuse = _FALSE;
+			sprintf(extra, "read efuse mask file FAIL\n");
+			RTW_INFO("%s rtw_efuse_file_read mask fail!\n", __func__);
+		}
+	} else {
+		padapter->registrypriv.bFileMaskEfuse = _FALSE;
+		sprintf(extra, "efuse mask file readable FAIL\n");
+		RTW_INFO("%s rtw_is_file_readable fail!\n", __func__);
+	}
+	wrqu->data.length = strlen(extra);
+	return 0;
+}
+
+
+int rtw_efuse_file_map(struct net_device *dev,
+		       struct iw_request_info *info,
+		       union iwreq_data *wrqu, char *extra)
+{
+	char *rtw_efuse_file_map_path;
+	u8 Status;
+	PEFUSE_HAL pEfuseHal;
+	PADAPTER padapter = rtw_netdev_priv(dev);
+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(padapter);
+	struct mp_priv *pmp_priv = &padapter->mppriv;
+
+	pEfuseHal = &pHalData->EfuseHal;
+	if (copy_from_user(extra, wrqu->data.pointer, wrqu->data.length))
+		return -EFAULT;
+
+	rtw_efuse_file_map_path = extra;
+
+	_rtw_memset(pEfuseHal->fakeEfuseModifiedMap, 0xFF, EFUSE_MAX_MAP_LEN);
+
+	if (rtw_is_file_readable(rtw_efuse_file_map_path) == _TRUE) {
+		RTW_INFO("%s do rtw_efuse_mask_file_read = %s!\n", __func__, rtw_efuse_file_map_path);
+		Status = rtw_efuse_file_read(padapter, rtw_efuse_file_map_path, pEfuseHal->fakeEfuseModifiedMap, sizeof(pEfuseHal->fakeEfuseModifiedMap));
+		if (Status == _TRUE) {
+			pmp_priv->bloadefusemap = _TRUE;
+			sprintf(extra, "efuse file file_read OK\n");
+		} else {
+			pmp_priv->bloadefusemap = _FALSE;
+			sprintf(extra, "efuse file file_read FAIL\n");
+		}
+	} else {
+		sprintf(extra, "efuse file readable FAIL\n");
+		RTW_INFO("%s rtw_is_file_readable fail!\n", __func__);
+	}
+	wrqu->data.length = strlen(extra);
+	return 0;
+}
+
+int rtw_bt_efuse_file_map(struct net_device *dev,
+				struct iw_request_info *info,
+				union iwreq_data *wrqu, char *extra)
+{
+	char *rtw_efuse_file_map_path;
+	u8 Status;
+	PEFUSE_HAL pEfuseHal;
+	PADAPTER padapter = rtw_netdev_priv(dev);
+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(padapter);
+	struct mp_priv *pmp_priv = &padapter->mppriv;
+
+	pEfuseHal = &pHalData->EfuseHal;
+	if (copy_from_user(extra, wrqu->data.pointer, wrqu->data.length))
+		return -EFAULT;
+
+	rtw_efuse_file_map_path = extra;
+
+	_rtw_memset(pEfuseHal->fakeBTEfuseModifiedMap, 0xFF, EFUSE_BT_MAX_MAP_LEN);
+
+	if (rtw_is_file_readable(rtw_efuse_file_map_path) == _TRUE) {
+		RTW_INFO("%s do rtw_efuse_mask_file_read = %s!\n", __func__, rtw_efuse_file_map_path);
+		Status = rtw_efuse_file_read(padapter, rtw_efuse_file_map_path, pEfuseHal->fakeBTEfuseModifiedMap, sizeof(pEfuseHal->fakeBTEfuseModifiedMap));
+		if (Status == _TRUE) {
+			pmp_priv->bloadBTefusemap = _TRUE;
+			sprintf(extra, "BT efuse file file_read OK\n");
+		} else {
+			pmp_priv->bloadBTefusemap = _FALSE;
+			sprintf(extra, "BT efuse file file_read FAIL\n");
+		}
+	} else {
+		sprintf(extra, "BT efuse file readable FAIL\n");
+		RTW_INFO("%s rtw_is_file_readable fail!\n", __func__);
+	}
+	wrqu->data.length = strlen(extra);
+	return 0;
+}
+
+#if defined(CONFIG_RTL8723B)
+int rtw_mp_SetBT(struct net_device *dev,
+		 struct iw_request_info *info,
+		 union iwreq_data *wrqu, char *extra)
+{
+	PADAPTER padapter = rtw_netdev_priv(dev);
+	struct hal_ops *pHalFunc = &padapter->hal_func;
+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(padapter);
+
+	BT_REQ_CMD	BtReq;
+	PMPT_CONTEXT	pMptCtx = &(padapter->mppriv.mpt_ctx);
+	PBT_RSP_CMD	pBtRsp = (PBT_RSP_CMD)&pMptCtx->mptOutBuf[0];
+	char	input[128];
+	char *pch, *ptmp, *token, *tmp[2] = {0x00, 0x00};
+	u8 setdata[100];
+	u8 resetbt = 0x00;
+	u8 tempval, BTStatus;
+	u8 H2cSetbtmac[6];
+	u8 u1H2CBtMpOperParm[4] = {0x01};
+	int testmode = 1, ready = 1, trxparam = 1, setgen = 1, getgen = 1, testctrl = 1, testbt = 1, readtherm = 1, setbtmac = 1;
+	u32 i = 0, ii = 0, jj = 0, kk = 0, cnts = 0, status = 0;
+	PRT_MP_FIRMWARE pBTFirmware = NULL;
+
+	if (copy_from_user(extra, wrqu->data.pointer, wrqu->data.length))
+		return -EFAULT;
+
+	*(extra + wrqu->data.length) = '\0';
+
+	if (strlen(extra) < 1)
+		return -EFAULT;
+
+	RTW_INFO("%s:iwpriv in=%s\n", __func__, extra);
+	ready = strncmp(extra, "ready", 5);
+	testmode = strncmp(extra, "testmode", 8); /* strncmp TRUE is 0*/
+	trxparam = strncmp(extra, "trxparam", 8);
+	setgen = strncmp(extra, "setgen", 6);
+	getgen = strncmp(extra, "getgen", 6);
+	testctrl = strncmp(extra, "testctrl", 8);
+	testbt = strncmp(extra, "testbt", 6);
+	readtherm = strncmp(extra, "readtherm", 9);
+	setbtmac = strncmp(extra, "setbtmac", 8);
+
+	if (strncmp(extra, "dlbt", 4) == 0) {
+		pHalData->LastHMEBoxNum = 0;
+		pHalData->bBTFWReady = _FALSE;
+		rtw_write8(padapter, 0xa3, 0x05);
+		BTStatus = rtw_read8(padapter, 0xa0);
+		RTW_INFO("%s: btwmap before read 0xa0 BT Status =0x%x\n", __func__, BTStatus);
+		if (BTStatus != 0x04) {
+			sprintf(extra, "BT Status not Active DLFW FAIL\n");
+			goto exit;
+		}
+
+		tempval = rtw_read8(padapter, 0x6B);
+		tempval |= BIT7;
+		rtw_write8(padapter, 0x6B, tempval);
+
+		/* Attention!! Between 0x6A[14] and 0x6A[15] setting need 100us delay*/
+		/* So don't write 0x6A[14]=1 and 0x6A[15]=0 together!*/
+		rtw_usleep_os(100);
+		/* disable BT power cut*/
+		/* 0x6A[14] = 0*/
+		tempval = rtw_read8(padapter, 0x6B);
+		tempval &= ~BIT6;
+		rtw_write8(padapter, 0x6B, tempval);
+		rtw_usleep_os(100);
+		MPT_PwrCtlDM(padapter, 0);
+		rtw_write32(padapter, 0xcc, (rtw_read32(padapter, 0xcc) | 0x00000004));
+		rtw_write32(padapter, 0x6b, (rtw_read32(padapter, 0x6b) & 0xFFFFFFEF));
+		rtw_msleep_os(600);
+		rtw_write32(padapter, 0x6b, (rtw_read32(padapter, 0x6b) | 0x00000010));
+		rtw_write32(padapter, 0xcc, (rtw_read32(padapter, 0xcc) & 0xFFFFFFFB));
+		rtw_msleep_os(1200);
+		pBTFirmware = (PRT_MP_FIRMWARE)rtw_zmalloc(sizeof(RT_MP_FIRMWARE));
+		if (pBTFirmware == NULL)
+			goto exit;
+		pHalData->bBTFWReady = _FALSE;
+		FirmwareDownloadBT(padapter, pBTFirmware);
+		if (pBTFirmware)
+			rtw_mfree((u8 *)pBTFirmware, sizeof(RT_MP_FIRMWARE));
+
+		RTW_INFO("Wait for FirmwareDownloadBT fw boot!\n");
+		rtw_msleep_os(2000);
+		_rtw_memset(extra, '\0', wrqu->data.length);
+		BtReq.opCodeVer = 1;
+		BtReq.OpCode = 0;
+		BtReq.paraLength = 0;
+		mptbt_BtControlProcess(padapter, &BtReq);
+		rtw_msleep_os(100);
+
+		RTW_INFO("FirmwareDownloadBT ready = 0x%x 0x%x", pMptCtx->mptOutBuf[4], pMptCtx->mptOutBuf[5]);
+		if ((pMptCtx->mptOutBuf[4] == 0x00) && (pMptCtx->mptOutBuf[5] == 0x00)) {
+
+			if (padapter->mppriv.bTxBufCkFail == _TRUE)
+				sprintf(extra, "check TxBuf Fail.\n");
+			else
+				sprintf(extra, "download FW Fail.\n");
+		} else {
+			sprintf(extra, "download FW OK.\n");
+			goto exit;
+		}
+		goto exit;
+	}
+	if (strncmp(extra, "dlfw", 4) == 0) {
+		pHalData->LastHMEBoxNum = 0;
+		pHalData->bBTFWReady = _FALSE;
+		rtw_write8(padapter, 0xa3, 0x05);
+		BTStatus = rtw_read8(padapter, 0xa0);
+		RTW_INFO("%s: btwmap before read 0xa0 BT Status =0x%x\n", __func__, BTStatus);
+		if (BTStatus != 0x04) {
+			sprintf(extra, "BT Status not Active DLFW FAIL\n");
+			goto exit;
+		}
+
+		tempval = rtw_read8(padapter, 0x6B);
+		tempval |= BIT7;
+		rtw_write8(padapter, 0x6B, tempval);
+
+		/* Attention!! Between 0x6A[14] and 0x6A[15] setting need 100us delay*/
+		/* So don't write 0x6A[14]=1 and 0x6A[15]=0 together!*/
+		rtw_usleep_os(100);
+		/* disable BT power cut*/
+		/* 0x6A[14] = 0*/
+		tempval = rtw_read8(padapter, 0x6B);
+		tempval &= ~BIT6;
+		rtw_write8(padapter, 0x6B, tempval);
+		rtw_usleep_os(100);
+
+		MPT_PwrCtlDM(padapter, 0);
+		rtw_write32(padapter, 0xcc, (rtw_read32(padapter, 0xcc) | 0x00000004));
+		rtw_write32(padapter, 0x6b, (rtw_read32(padapter, 0x6b) & 0xFFFFFFEF));
+		rtw_msleep_os(600);
+		rtw_write32(padapter, 0x6b, (rtw_read32(padapter, 0x6b) | 0x00000010));
+		rtw_write32(padapter, 0xcc, (rtw_read32(padapter, 0xcc) & 0xFFFFFFFB));
+		rtw_msleep_os(1200);
+
+#if defined(CONFIG_PLATFORM_SPRD) && (MP_DRIVER == 1)
+		/* Pull up BT reset pin.*/
+		RTW_INFO("%s: pull up BT reset pin when bt start mp test\n", __func__);
+		rtw_wifi_gpio_wlan_ctrl(WLAN_BT_PWDN_ON);
+#endif
+		RTW_INFO(" FirmwareDownload!\n");
+
+#if defined(CONFIG_RTL8723B)
+		status = rtl8723b_FirmwareDownload(padapter, _FALSE);
+#endif
+		RTW_INFO("Wait for FirmwareDownloadBT fw boot!\n");
+		rtw_msleep_os(1000);
+#ifdef CONFIG_BT_COEXIST
+		rtw_btcoex_HaltNotify(padapter);
+		RTW_INFO("SetBT btcoex HaltNotify !\n");
+		/*hal_btcoex1ant_SetAntPath(padapter);*/
+		rtw_btcoex_SetManualControl(padapter, _TRUE);
+#endif
+		_rtw_memset(extra, '\0', wrqu->data.length);
+		BtReq.opCodeVer = 1;
+		BtReq.OpCode = 0;
+		BtReq.paraLength = 0;
+		mptbt_BtControlProcess(padapter, &BtReq);
+		rtw_msleep_os(200);
+
+		RTW_INFO("FirmwareDownloadBT ready = 0x%x 0x%x", pMptCtx->mptOutBuf[4], pMptCtx->mptOutBuf[5]);
+		if ((pMptCtx->mptOutBuf[4] == 0x00) && (pMptCtx->mptOutBuf[5] == 0x00)) {
+			if (padapter->mppriv.bTxBufCkFail == _TRUE)
+				sprintf(extra, "check TxBuf Fail.\n");
+			else
+				sprintf(extra, "download FW Fail.\n");
+		} else {
+#ifdef CONFIG_BT_COEXIST
+			rtw_btcoex_SwitchBtTRxMask(padapter);
+#endif
+			rtw_msleep_os(200);
+			sprintf(extra, "download FW OK.\n");
+			goto exit;
+		}
+		goto exit;
+	}
+
+	if (strncmp(extra, "down", 4) == 0) {
+		RTW_INFO("SetBT down for to hal_init !\n");
+#ifdef CONFIG_BT_COEXIST
+		rtw_btcoex_SetManualControl(padapter, _FALSE);
+		rtw_btcoex_Initialize(padapter);
+#endif
+		pHalFunc->read_adapter_info(padapter);
+		pHalFunc->hal_deinit(padapter);
+		pHalFunc->hal_init(padapter);
+		rtw_pm_set_ips(padapter, IPS_NONE);
+		LeaveAllPowerSaveMode(padapter);
+		MPT_PwrCtlDM(padapter, 0);
+		rtw_write32(padapter, 0xcc, (rtw_read32(padapter, 0xcc) | 0x00000004));
+		rtw_write32(padapter, 0x6b, (rtw_read32(padapter, 0x6b) & 0xFFFFFFEF));
+		rtw_msleep_os(600);
+		/*rtw_write32(padapter, 0x6a, (rtw_read32(padapter, 0x6a)& 0xFFFFFFFE));*/
+		rtw_write32(padapter, 0x6b, (rtw_read32(padapter, 0x6b) | 0x00000010));
+		rtw_write32(padapter, 0xcc, (rtw_read32(padapter, 0xcc) & 0xFFFFFFFB));
+		rtw_msleep_os(1200);
+		goto exit;
+	}
+	if (strncmp(extra, "disable", 7) == 0) {
+		RTW_INFO("SetBT disable !\n");
+		rtw_write32(padapter, 0x6a, (rtw_read32(padapter, 0x6a) & 0xFFFFFFFB));
+		rtw_msleep_os(500);
+		goto exit;
+	}
+	if (strncmp(extra, "enable", 6) == 0) {
+		RTW_INFO("SetBT enable !\n");
+		rtw_write32(padapter, 0x6a, (rtw_read32(padapter, 0x6a) | 0x00000004));
+		rtw_msleep_os(500);
+		goto exit;
+	}
+	if (strncmp(extra, "h2c", 3) == 0) {
+		RTW_INFO("SetBT h2c !\n");
+		pHalData->bBTFWReady = _TRUE;
+		rtw_hal_fill_h2c_cmd(padapter, 0x63, 1, u1H2CBtMpOperParm);
+		goto exit;
+	}
+	if (strncmp(extra, "2ant", 4) == 0) {
+		RTW_INFO("Set BT 2ant use!\n");
+		phy_set_mac_reg(padapter, 0x67, BIT5, 0x1);
+		rtw_write32(padapter, 0x948, 0000);
+
+		goto exit;
+	}
+
+	if (ready != 0 && testmode != 0 && trxparam != 0 && setgen != 0 && getgen != 0 && testctrl != 0 && testbt != 0 && readtherm != 0 && setbtmac != 0)
+		return -EFAULT;
+
+	if (testbt == 0) {
+		BtReq.opCodeVer = 1;
+		BtReq.OpCode = 6;
+		BtReq.paraLength = cnts / 2;
+		goto todo;
+	}
+	if (ready == 0) {
+		BtReq.opCodeVer = 1;
+		BtReq.OpCode = 0;
+		BtReq.paraLength = 0;
+		goto todo;
+	}
+
+	pch = extra;
+	i = 0;
+	while ((token = strsep(&pch, ",")) != NULL) {
+		if (i > 1)
+			break;
+		tmp[i] = token;
+		i++;
+	}
+
+	if ((tmp[0] != NULL) && (tmp[1] != NULL)) {
+		cnts = strlen(tmp[1]);
+		if (cnts < 1)
+			return -EFAULT;
+
+		RTW_INFO("%s: cnts=%d\n", __func__, cnts);
+		RTW_INFO("%s: data=%s\n", __func__, tmp[1]);
+
+		for (jj = 0, kk = 0; jj < cnts; jj++, kk += 2) {
+			BtReq.pParamStart[jj] = key_2char2num(tmp[1][kk], tmp[1][kk + 1]);
+			/*			RTW_INFO("BtReq.pParamStart[%d]=0x%02x\n", jj, BtReq.pParamStart[jj]);*/
+		}
+	} else
+		return -EFAULT;
+
+	if (testmode == 0) {
+		BtReq.opCodeVer = 1;
+		BtReq.OpCode = 1;
+		BtReq.paraLength = 1;
+	}
+	if (trxparam == 0) {
+		BtReq.opCodeVer = 1;
+		BtReq.OpCode = 2;
+		BtReq.paraLength = cnts / 2;
+	}
+	if (setgen == 0) {
+		RTW_INFO("%s: BT_SET_GENERAL\n", __func__);
+		BtReq.opCodeVer = 1;
+		BtReq.OpCode = 3;/*BT_SET_GENERAL	3*/
+		BtReq.paraLength = cnts / 2;
+	}
+	if (getgen == 0) {
+		RTW_INFO("%s: BT_GET_GENERAL\n", __func__);
+		BtReq.opCodeVer = 1;
+		BtReq.OpCode = 4;/*BT_GET_GENERAL	4*/
+		BtReq.paraLength = cnts / 2;
+	}
+	if (readtherm == 0) {
+		RTW_INFO("%s: BT_GET_GENERAL\n", __func__);
+		BtReq.opCodeVer = 1;
+		BtReq.OpCode = 4;/*BT_GET_GENERAL	4*/
+		BtReq.paraLength = cnts / 2;
+	}
+
+	if (testctrl == 0) {
+		RTW_INFO("%s: BT_TEST_CTRL\n", __func__);
+		BtReq.opCodeVer = 1;
+		BtReq.OpCode = 5;/*BT_TEST_CTRL	5*/
+		BtReq.paraLength = cnts / 2;
+	}
+
+	RTW_INFO("%s: Req opCodeVer=%d OpCode=%d paraLength=%d\n",
+		 __func__, BtReq.opCodeVer, BtReq.OpCode, BtReq.paraLength);
+
+	if (BtReq.paraLength < 1)
+		goto todo;
+	for (i = 0; i < BtReq.paraLength; i++) {
+		RTW_INFO("%s: BtReq.pParamStart[%d] = 0x%02x\n",
+			 __func__, i, BtReq.pParamStart[i]);
+	}
+
+todo:
+	_rtw_memset(extra, '\0', wrqu->data.length);
+
+	if (pHalData->bBTFWReady == _FALSE) {
+		sprintf(extra, "BTFWReady = FALSE.\n");
+		goto exit;
+	}
+
+	mptbt_BtControlProcess(padapter, &BtReq);
+
+	if (readtherm == 0) {
+		sprintf(extra, "BT thermal=");
+		for (i = 4; i < pMptCtx->mptOutLen; i++) {
+			if ((pMptCtx->mptOutBuf[i] == 0x00) && (pMptCtx->mptOutBuf[i + 1] == 0x00))
+				goto exit;
+
+			sprintf(extra, "%s %d ", extra, (pMptCtx->mptOutBuf[i] & 0x1f));
+		}
+	} else {
+		for (i = 4; i < pMptCtx->mptOutLen; i++)
+			sprintf(extra, "%s 0x%x ", extra, pMptCtx->mptOutBuf[i]);
+	}
+
+exit:
+	wrqu->data.length = strlen(extra) + 1;
+	RTW_INFO("-%s: output len=%d data=%s\n", __func__, wrqu->data.length, extra);
+
+	return status;
+}
+
+#endif /*#ifdef CONFIG_RTL8723B*/
+
+#endif
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/os_dep/linux/mlme_linux.c linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/os_dep/linux/mlme_linux.c
--- linux-5.6.3/3rdparty/rtl8821ce/os_dep/linux/mlme_linux.c	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/os_dep/linux/mlme_linux.c	2020-04-10 16:35:06.855661888 +0300
@@ -0,0 +1,432 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+
+
+#define _MLME_OSDEP_C_
+
+#include <drv_types.h>
+
+
+#ifdef RTK_DMP_PLATFORM
+void Linkup_workitem_callback(struct work_struct *work)
+{
+	struct mlme_priv *pmlmepriv = container_of(work, struct mlme_priv, Linkup_workitem);
+	_adapter *padapter = container_of(pmlmepriv, _adapter, mlmepriv);
+
+
+
+#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 12))
+	kobject_uevent(&padapter->pnetdev->dev.kobj, KOBJ_LINKUP);
+#else
+	kobject_hotplug(&padapter->pnetdev->class_dev.kobj, KOBJ_LINKUP);
+#endif
+
+}
+
+void Linkdown_workitem_callback(struct work_struct *work)
+{
+	struct mlme_priv *pmlmepriv = container_of(work, struct mlme_priv, Linkdown_workitem);
+	_adapter *padapter = container_of(pmlmepriv, _adapter, mlmepriv);
+
+
+
+#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 12))
+	kobject_uevent(&padapter->pnetdev->dev.kobj, KOBJ_LINKDOWN);
+#else
+	kobject_hotplug(&padapter->pnetdev->class_dev.kobj, KOBJ_LINKDOWN);
+#endif
+
+}
+#endif
+
+extern void rtw_indicate_wx_assoc_event(_adapter *padapter);
+extern void rtw_indicate_wx_disassoc_event(_adapter *padapter);
+
+void rtw_os_indicate_connect(_adapter *adapter)
+{
+	struct mlme_priv *pmlmepriv = &(adapter->mlmepriv);
+
+#ifdef CONFIG_IOCTL_CFG80211
+	if ((check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE) == _TRUE) ||
+	    (check_fwstate(pmlmepriv, WIFI_ADHOC_STATE) == _TRUE))
+		rtw_cfg80211_ibss_indicate_connect(adapter);
+	else
+		rtw_cfg80211_indicate_connect(adapter);
+#endif /* CONFIG_IOCTL_CFG80211 */
+
+	rtw_indicate_wx_assoc_event(adapter);
+
+#ifdef CONFIG_RTW_MESH
+#if CONFIG_RTW_MESH_CTO_MGATE_CARRIER
+	if (!rtw_mesh_cto_mgate_required(adapter))
+#endif
+#endif
+		rtw_netif_carrier_on(adapter->pnetdev);
+
+	if (adapter->pid[2] != 0)
+		rtw_signal_process(adapter->pid[2], SIGALRM);
+
+#ifdef RTK_DMP_PLATFORM
+	_set_workitem(&adapter->mlmepriv.Linkup_workitem);
+#endif
+
+
+}
+
+extern void indicate_wx_scan_complete_event(_adapter *padapter);
+void rtw_os_indicate_scan_done(_adapter *padapter, bool aborted)
+{
+#ifdef CONFIG_IOCTL_CFG80211
+	rtw_cfg80211_indicate_scan_done(padapter, aborted);
+#endif
+	indicate_wx_scan_complete_event(padapter);
+}
+
+static RT_PMKID_LIST   backupPMKIDList[NUM_PMKID_CACHE];
+void rtw_reset_securitypriv(_adapter *adapter)
+{
+	u8	backupPMKIDIndex = 0;
+	u8	backupTKIPCountermeasure = 0x00;
+	u32	backupTKIPcountermeasure_time = 0;
+	/* add for CONFIG_IEEE80211W, none 11w also can use */
+	_irqL irqL;
+
+	_enter_critical_bh(&adapter->security_key_mutex, &irqL);
+
+	if (adapter->securitypriv.dot11AuthAlgrthm == dot11AuthAlgrthm_8021X) { /* 802.1x */
+		/* Added by Albert 2009/02/18 */
+		/* We have to backup the PMK information for WiFi PMK Caching test item. */
+		/*  */
+		/* Backup the btkip_countermeasure information. */
+		/* When the countermeasure is trigger, the driver have to disconnect with AP for 60 seconds. */
+
+		_rtw_memset(&backupPMKIDList[0], 0x00, sizeof(RT_PMKID_LIST) * NUM_PMKID_CACHE);
+
+		_rtw_memcpy(&backupPMKIDList[0], &adapter->securitypriv.PMKIDList[0], sizeof(RT_PMKID_LIST) * NUM_PMKID_CACHE);
+		backupPMKIDIndex = adapter->securitypriv.PMKIDIndex;
+		backupTKIPCountermeasure = adapter->securitypriv.btkip_countermeasure;
+		backupTKIPcountermeasure_time = adapter->securitypriv.btkip_countermeasure_time;
+		_rtw_memset((unsigned char *)&adapter->securitypriv, 0, sizeof(struct security_priv));
+
+		/* Added by Albert 2009/02/18 */
+		/* Restore the PMK information to securitypriv structure for the following connection. */
+		_rtw_memcpy(&adapter->securitypriv.PMKIDList[0], &backupPMKIDList[0], sizeof(RT_PMKID_LIST) * NUM_PMKID_CACHE);
+		adapter->securitypriv.PMKIDIndex = backupPMKIDIndex;
+		adapter->securitypriv.btkip_countermeasure = backupTKIPCountermeasure;
+		adapter->securitypriv.btkip_countermeasure_time = backupTKIPcountermeasure_time;
+
+		adapter->securitypriv.ndisauthtype = Ndis802_11AuthModeOpen;
+		adapter->securitypriv.ndisencryptstatus = Ndis802_11WEPDisabled;
+
+	} else { /* reset values in securitypriv */
+		/* if(adapter->mlmepriv.fw_state & WIFI_STATION_STATE) */
+		/* { */
+		struct security_priv *psec_priv = &adapter->securitypriv;
+
+		psec_priv->dot11AuthAlgrthm = dot11AuthAlgrthm_Open; /* open system */
+		psec_priv->dot11PrivacyAlgrthm = _NO_PRIVACY_;
+		psec_priv->dot11PrivacyKeyIndex = 0;
+
+		psec_priv->dot118021XGrpPrivacy = _NO_PRIVACY_;
+		psec_priv->dot118021XGrpKeyid = 1;
+
+		psec_priv->ndisauthtype = Ndis802_11AuthModeOpen;
+		psec_priv->ndisencryptstatus = Ndis802_11WEPDisabled;
+		/* } */
+	}
+	/* add for CONFIG_IEEE80211W, none 11w also can use */
+	_exit_critical_bh(&adapter->security_key_mutex, &irqL);
+
+	RTW_INFO(FUNC_ADPT_FMT" - End to Disconnect\n", FUNC_ADPT_ARG(adapter));
+}
+
+void rtw_os_indicate_disconnect(_adapter *adapter,  u16 reason, u8 locally_generated)
+{
+	/* RT_PMKID_LIST   backupPMKIDList[NUM_PMKID_CACHE]; */
+
+
+	rtw_netif_carrier_off(adapter->pnetdev); /* Do it first for tx broadcast pkt after disconnection issue! */
+
+#ifdef CONFIG_IOCTL_CFG80211
+	rtw_cfg80211_indicate_disconnect(adapter,  reason, locally_generated);
+#endif /* CONFIG_IOCTL_CFG80211 */
+
+	rtw_indicate_wx_disassoc_event(adapter);
+
+#ifdef RTK_DMP_PLATFORM
+	_set_workitem(&adapter->mlmepriv.Linkdown_workitem);
+#endif
+	/* modify for CONFIG_IEEE80211W, none 11w also can use the same command */
+	rtw_reset_securitypriv_cmd(adapter);
+
+
+}
+
+void rtw_report_sec_ie(_adapter *adapter, u8 authmode, u8 *sec_ie)
+{
+	uint	len;
+	u8	*buff, *p, i;
+	union iwreq_data wrqu;
+
+
+
+	buff = NULL;
+	if (authmode == _WPA_IE_ID_) {
+
+		buff = rtw_zmalloc(IW_CUSTOM_MAX);
+		if (NULL == buff) {
+			RTW_INFO(FUNC_ADPT_FMT ": alloc memory FAIL!!\n",
+				 FUNC_ADPT_ARG(adapter));
+			return;
+		}
+		p = buff;
+
+		p += sprintf(p, "ASSOCINFO(ReqIEs=");
+
+		len = sec_ie[1] + 2;
+		len = (len < IW_CUSTOM_MAX) ? len : IW_CUSTOM_MAX;
+
+		for (i = 0; i < len; i++)
+			p += sprintf(p, "%02x", sec_ie[i]);
+
+		p += sprintf(p, ")");
+
+		_rtw_memset(&wrqu, 0, sizeof(wrqu));
+
+		wrqu.data.length = p - buff;
+
+		wrqu.data.length = (wrqu.data.length < IW_CUSTOM_MAX) ? wrqu.data.length : IW_CUSTOM_MAX;
+
+#ifndef CONFIG_IOCTL_CFG80211
+		wireless_send_event(adapter->pnetdev, IWEVCUSTOM, &wrqu, buff);
+#endif
+
+		rtw_mfree(buff, IW_CUSTOM_MAX);
+	}
+
+
+}
+
+#ifdef CONFIG_AP_MODE
+
+void rtw_indicate_sta_assoc_event(_adapter *padapter, struct sta_info *psta)
+{
+	union iwreq_data wrqu;
+	struct sta_priv *pstapriv = &padapter->stapriv;
+
+	if (psta == NULL)
+		return;
+
+	if (psta->cmn.aid > pstapriv->max_aid)
+		return;
+
+	if (pstapriv->sta_aid[psta->cmn.aid - 1] != psta)
+		return;
+
+
+	wrqu.addr.sa_family = ARPHRD_ETHER;
+
+	_rtw_memcpy(wrqu.addr.sa_data, psta->cmn.mac_addr, ETH_ALEN);
+
+	RTW_INFO("+rtw_indicate_sta_assoc_event\n");
+
+#ifndef CONFIG_IOCTL_CFG80211
+	wireless_send_event(padapter->pnetdev, IWEVREGISTERED, &wrqu, NULL);
+#endif
+
+}
+
+void rtw_indicate_sta_disassoc_event(_adapter *padapter, struct sta_info *psta)
+{
+	union iwreq_data wrqu;
+	struct sta_priv *pstapriv = &padapter->stapriv;
+
+	if (psta == NULL)
+		return;
+
+	if (psta->cmn.aid > pstapriv->max_aid)
+		return;
+
+	if (pstapriv->sta_aid[psta->cmn.aid - 1] != psta)
+		return;
+
+
+	wrqu.addr.sa_family = ARPHRD_ETHER;
+
+	_rtw_memcpy(wrqu.addr.sa_data, psta->cmn.mac_addr, ETH_ALEN);
+
+	RTW_INFO("+rtw_indicate_sta_disassoc_event\n");
+
+#ifndef CONFIG_IOCTL_CFG80211
+	wireless_send_event(padapter->pnetdev, IWEVEXPIRED, &wrqu, NULL);
+#endif
+
+}
+
+
+#ifdef CONFIG_HOSTAPD_MLME
+
+static int mgnt_xmit_entry(struct sk_buff *skb, struct net_device *pnetdev)
+{
+	struct hostapd_priv *phostapdpriv = rtw_netdev_priv(pnetdev);
+	_adapter *padapter = (_adapter *)phostapdpriv->padapter;
+
+	/* RTW_INFO("%s\n", __FUNCTION__); */
+
+	return rtw_hal_hostap_mgnt_xmit_entry(padapter, skb);
+}
+
+static int mgnt_netdev_open(struct net_device *pnetdev)
+{
+	struct hostapd_priv *phostapdpriv = rtw_netdev_priv(pnetdev);
+
+	RTW_INFO("mgnt_netdev_open: MAC Address:" MAC_FMT "\n", MAC_ARG(pnetdev->dev_addr));
+
+
+	init_usb_anchor(&phostapdpriv->anchored);
+
+	rtw_netif_wake_queue(pnetdev);
+
+	rtw_netif_carrier_on(pnetdev);
+
+	/* rtw_write16(phostapdpriv->padapter, 0x0116, 0x0100); */ /* only excluding beacon */
+
+	return 0;
+}
+static int mgnt_netdev_close(struct net_device *pnetdev)
+{
+	struct hostapd_priv *phostapdpriv = rtw_netdev_priv(pnetdev);
+
+	RTW_INFO("%s\n", __FUNCTION__);
+
+	usb_kill_anchored_urbs(&phostapdpriv->anchored);
+
+	rtw_netif_carrier_off(pnetdev);
+
+	rtw_netif_stop_queue(pnetdev);
+
+	/* rtw_write16(phostapdpriv->padapter, 0x0116, 0x3f3f); */
+
+	return 0;
+}
+
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 29))
+static const struct net_device_ops rtl871x_mgnt_netdev_ops = {
+	.ndo_open = mgnt_netdev_open,
+	.ndo_stop = mgnt_netdev_close,
+	.ndo_start_xmit = mgnt_xmit_entry,
+	#if 0
+	.ndo_set_mac_address = r871x_net_set_mac_address,
+	.ndo_get_stats = r871x_net_get_stats,
+	.ndo_do_ioctl = r871x_mp_ioctl,
+	#endif
+};
+#endif
+
+int hostapd_mode_init(_adapter *padapter)
+{
+	unsigned char mac[ETH_ALEN];
+	struct hostapd_priv *phostapdpriv;
+	struct net_device *pnetdev;
+
+	pnetdev = rtw_alloc_etherdev(sizeof(struct hostapd_priv));
+	if (!pnetdev)
+		return -ENOMEM;
+
+	/* SET_MODULE_OWNER(pnetdev); */
+	ether_setup(pnetdev);
+
+	/* pnetdev->type = ARPHRD_IEEE80211; */
+
+	phostapdpriv = rtw_netdev_priv(pnetdev);
+	phostapdpriv->pmgnt_netdev = pnetdev;
+	phostapdpriv->padapter = padapter;
+	padapter->phostapdpriv = phostapdpriv;
+
+	/* pnetdev->init = NULL; */
+
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 29))
+
+	RTW_INFO("register rtl871x_mgnt_netdev_ops to netdev_ops\n");
+
+	pnetdev->netdev_ops = &rtl871x_mgnt_netdev_ops;
+
+#else
+
+	pnetdev->open = mgnt_netdev_open;
+
+	pnetdev->stop = mgnt_netdev_close;
+
+	pnetdev->hard_start_xmit = mgnt_xmit_entry;
+
+	/* pnetdev->set_mac_address = r871x_net_set_mac_address; */
+
+	/* pnetdev->get_stats = r871x_net_get_stats; */
+
+	/* pnetdev->do_ioctl = r871x_mp_ioctl; */
+
+#endif
+
+	pnetdev->watchdog_timeo = HZ; /* 1 second timeout */
+
+	/* pnetdev->wireless_handlers = NULL; */
+
+
+
+
+	if (dev_alloc_name(pnetdev, "mgnt.wlan%d") < 0)
+		RTW_INFO("hostapd_mode_init(): dev_alloc_name, fail!\n");
+
+
+	/* SET_NETDEV_DEV(pnetdev, pintfpriv->udev); */
+
+
+	mac[0] = 0x00;
+	mac[1] = 0xe0;
+	mac[2] = 0x4c;
+	mac[3] = 0x87;
+	mac[4] = 0x11;
+	mac[5] = 0x12;
+
+	_rtw_memcpy(pnetdev->dev_addr, mac, ETH_ALEN);
+
+
+	rtw_netif_carrier_off(pnetdev);
+
+
+	/* Tell the network stack we exist */
+	if (register_netdev(pnetdev) != 0) {
+		RTW_INFO("hostapd_mode_init(): register_netdev fail!\n");
+
+		if (pnetdev)
+			rtw_free_netdev(pnetdev);
+	}
+
+	return 0;
+
+}
+
+void hostapd_mode_unload(_adapter *padapter)
+{
+	struct hostapd_priv *phostapdpriv = padapter->phostapdpriv;
+	struct net_device *pnetdev = phostapdpriv->pmgnt_netdev;
+
+	unregister_netdev(pnetdev);
+	rtw_free_netdev(pnetdev);
+
+}
+
+#endif
+#endif
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/os_dep/linux/os_intfs.c linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/os_dep/linux/os_intfs.c
--- linux-5.6.3/3rdparty/rtl8821ce/os_dep/linux/os_intfs.c	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/os_dep/linux/os_intfs.c	2020-04-10 16:35:06.856661935 +0300
@@ -0,0 +1,5181 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#define _OS_INTFS_C_
+
+#include <drv_types.h>
+#include <hal_data.h>
+
+#if defined(PLATFORM_LINUX) && defined (PLATFORM_WINDOWS)
+
+	#error "Shall be Linux or Windows, but not both!\n"
+
+#endif
+
+
+MODULE_LICENSE("GPL");
+MODULE_DESCRIPTION("Realtek Wireless Lan Driver");
+MODULE_AUTHOR("Realtek Semiconductor Corp.");
+MODULE_VERSION(DRIVERVERSION);
+
+/* module param defaults */
+int rtw_chip_version = 0x00;
+int rtw_rfintfs = HWPI;
+int rtw_lbkmode = 0;/* RTL8712_AIR_TRX; */
+#ifdef DBG_LA_MODE
+int rtw_la_mode_en=1;
+module_param(rtw_la_mode_en, int, 0644);
+#endif
+int rtw_network_mode = Ndis802_11IBSS;/* Ndis802_11Infrastructure; */ /* infra, ad-hoc, auto */
+/* NDIS_802_11_SSID	ssid; */
+int rtw_channel = 1;/* ad-hoc support requirement */
+int rtw_wireless_mode = WIRELESS_MODE_MAX;
+module_param(rtw_wireless_mode, int, 0644);
+int rtw_vrtl_carrier_sense = AUTO_VCS;
+int rtw_vcs_type = RTS_CTS;
+int rtw_rts_thresh = 2347;
+int rtw_frag_thresh = 2346;
+int rtw_preamble = PREAMBLE_LONG;/* long, short, auto */
+int rtw_scan_mode = 1;/* active, passive */
+/* int smart_ps = 1; */
+#ifdef CONFIG_POWER_SAVING
+	int rtw_power_mgnt = PS_MODE_MAX;
+	#ifdef CONFIG_IPS_LEVEL_2
+		int rtw_ips_mode = IPS_LEVEL_2;
+	#else
+		int rtw_ips_mode = IPS_NORMAL;
+	#endif /*CONFIG_IPS_LEVEL_2*/
+
+	#ifdef CONFIG_USB_HCI
+		int rtw_lps_level = LPS_NORMAL; /*USB default LPS level*/
+	#else /*SDIO,PCIE*/
+		#if defined(CONFIG_LPS_PG)
+			/*int rtw_lps_level = LPS_PG;*//*FW not support yet*/
+			int rtw_lps_level = LPS_LCLK;
+		#elif defined(CONFIG_LPS_PG_DDMA)
+			int rtw_lps_level = LPS_PG;
+		#elif defined(CONFIG_LPS_LCLK)
+			int rtw_lps_level = LPS_LCLK;
+		#else
+			int rtw_lps_level = LPS_NORMAL;
+		#endif
+	#endif/*CONFIG_USB_HCI*/
+	int rtw_lps_chk_by_tp = 1;
+#else /* !CONFIG_POWER_SAVING */
+	int rtw_power_mgnt = PS_MODE_ACTIVE;
+	int rtw_ips_mode = IPS_NONE;
+	int rtw_lps_level = LPS_NORMAL;
+	int rtw_lps_chk_by_tp = 0;
+#endif /* CONFIG_POWER_SAVING */
+
+
+module_param(rtw_ips_mode, int, 0644);
+MODULE_PARM_DESC(rtw_ips_mode, "The default IPS mode");
+
+module_param(rtw_lps_level, int, 0644);
+MODULE_PARM_DESC(rtw_lps_level, "The default LPS level");
+
+module_param(rtw_lps_chk_by_tp, int, 0644);
+
+/* LPS:
+ * rtw_smart_ps = 0 => TX: pwr bit = 1, RX: PS_Poll
+ * rtw_smart_ps = 1 => TX: pwr bit = 0, RX: PS_Poll
+ * rtw_smart_ps = 2 => TX: pwr bit = 0, RX: NullData with pwr bit = 0
+*/
+int rtw_smart_ps = 2;
+
+int rtw_max_bss_cnt = 0;
+module_param(rtw_max_bss_cnt, int, 0644);
+#ifdef CONFIG_WMMPS_STA
+/* WMMPS:
+ * rtw_smart_ps = 0 => Only for fw test
+ * rtw_smart_ps = 1 => Refer to Beacon's TIM Bitmap
+ * rtw_smart_ps = 2 => Don't refer to Beacon's TIM Bitmap
+*/
+int rtw_wmm_smart_ps = 2;
+#endif /* CONFIG_WMMPS_STA */
+
+int rtw_check_fw_ps = 1;
+
+#ifdef CONFIG_TX_EARLY_MODE
+int rtw_early_mode = 1;
+#endif
+
+int rtw_usb_rxagg_mode = 2;/* RX_AGG_DMA=1, RX_AGG_USB=2 */
+module_param(rtw_usb_rxagg_mode, int, 0644);
+
+int rtw_dynamic_agg_enable = 1;
+module_param(rtw_dynamic_agg_enable, int, 0644);
+
+/* set log level when inserting driver module, default log level is _DRV_INFO_ = 4,
+* please refer to "How_to_set_driver_debug_log_level.doc" to set the available level.
+*/
+#ifdef CONFIG_RTW_DEBUG
+#ifdef RTW_LOG_LEVEL
+	uint rtw_drv_log_level = (uint)RTW_LOG_LEVEL; /* from Makefile */
+#else
+	uint rtw_drv_log_level = _DRV_INFO_;
+#endif
+module_param(rtw_drv_log_level, uint, 0644);
+MODULE_PARM_DESC(rtw_drv_log_level, "set log level when insert driver module, default log level is _DRV_INFO_ = 4");
+#endif
+int rtw_radio_enable = 1;
+int rtw_long_retry_lmt = 7;
+int rtw_short_retry_lmt = 7;
+int rtw_busy_thresh = 40;
+/* int qos_enable = 0; */ /* * */
+int rtw_ack_policy = NORMAL_ACK;
+
+int rtw_mp_mode = 0;
+
+#if defined(CONFIG_MP_INCLUDED) && defined(CONFIG_RTW_CUSTOMER_STR)
+uint rtw_mp_customer_str = 0;
+module_param(rtw_mp_customer_str, uint, 0644);
+MODULE_PARM_DESC(rtw_mp_customer_str, "Whether or not to enable customer str support on MP mode");
+#endif
+
+int rtw_software_encrypt = 0;
+int rtw_software_decrypt = 0;
+
+int rtw_acm_method = 0;/* 0:By SW 1:By HW. */
+
+int rtw_wmm_enable = 1;/* default is set to enable the wmm. */
+
+#ifdef CONFIG_WMMPS_STA
+/* uapsd (unscheduled automatic power-save delivery) = a kind of wmmps */
+/* 0: NO_LIMIT, 1: TWO_MSDU, 2: FOUR_MSDU, 3: SIX_MSDU */
+int rtw_uapsd_max_sp = NO_LIMIT;
+/* BIT0: AC_VO UAPSD, BIT1: AC_VI UAPSD, BIT2: AC_BK UAPSD, BIT3: AC_BE UAPSD */
+int rtw_uapsd_ac_enable = 0x0;
+#endif /* CONFIG_WMMPS_STA */
+
+#if defined(CONFIG_RTL8814A)
+	int rtw_pwrtrim_enable = 2; /* disable kfree , rename to power trim disable */
+#elif defined(CONFIG_RTL8821C) || defined(CONFIG_RTL8822B)
+	/*PHYDM API, must enable by default*/
+	int rtw_pwrtrim_enable = 1;
+#else
+	int rtw_pwrtrim_enable = 0; /* Default Enalbe  power trim by efuse config */
+#endif
+
+uint rtw_tx_bw_mode = 0x21;
+module_param(rtw_tx_bw_mode, uint, 0644);
+MODULE_PARM_DESC(rtw_tx_bw_mode, "The max tx bw for 2.4G and 5G. format is the same as rtw_bw_mode");
+
+#ifdef CONFIG_FW_HANDLE_TXBCN
+uint rtw_tbtt_rpt = 0;	/*ROOT AP - BIT0, VAP1 - BIT1, VAP2 - BIT2, VAP3 - VAP3, FW report TBTT INT by C2H*/
+module_param(rtw_tbtt_rpt, uint, 0644);
+#endif
+
+#ifdef CONFIG_80211N_HT
+int rtw_ht_enable = 1;
+/* 0: 20 MHz, 1: 40 MHz, 2: 80 MHz, 3: 160MHz, 4: 80+80MHz
+* 2.4G use bit 0 ~ 3, 5G use bit 4 ~ 7
+* 0x21 means enable 2.4G 40MHz & 5G 80MHz */
+#ifdef CONFIG_RTW_CUSTOMIZE_BWMODE
+int rtw_bw_mode = CONFIG_RTW_CUSTOMIZE_BWMODE;
+#else
+int rtw_bw_mode = 0x21;
+#endif
+int rtw_ampdu_enable = 1;/* for enable tx_ampdu , */ /* 0: disable, 0x1:enable */
+int rtw_rx_stbc = 1;/* 0: disable, bit(0):enable 2.4g, bit(1):enable 5g, default is set to enable 2.4GHZ for IOT issue with bufflao's AP at 5GHZ */
+#if (defined(CONFIG_RTL8814A) || defined(CONFIG_RTL8822B)) && defined(CONFIG_PCI_HCI)
+int rtw_rx_ampdu_amsdu = 2;/* 0: disabled, 1:enabled, 2:auto . There is an IOT issu with DLINK DIR-629 when the flag turn on */
+#else
+int rtw_rx_ampdu_amsdu;/* 0: disabled, 1:enabled, 2:auto . There is an IOT issu with DLINK DIR-629 when the flag turn on */
+#endif
+/*
+* 2: Follow the AMSDU filed in ADDBA Resp. (Deault)
+* 0: Force the AMSDU filed in ADDBA Resp. to be disabled.
+* 1: Force the AMSDU filed in ADDBA Resp. to be enabled.
+*/
+int rtw_tx_ampdu_amsdu = 2;
+
+static uint rtw_rx_ampdu_sz_limit_1ss[4] = CONFIG_RTW_RX_AMPDU_SZ_LIMIT_1SS;
+static uint rtw_rx_ampdu_sz_limit_1ss_num = 0;
+module_param_array(rtw_rx_ampdu_sz_limit_1ss, uint, &rtw_rx_ampdu_sz_limit_1ss_num, 0644);
+MODULE_PARM_DESC(rtw_rx_ampdu_sz_limit_1ss, "RX AMPDU size limit for 1SS link of each BW, 0xFF: no limitation");
+
+static uint rtw_rx_ampdu_sz_limit_2ss[4] = CONFIG_RTW_RX_AMPDU_SZ_LIMIT_2SS;
+static uint rtw_rx_ampdu_sz_limit_2ss_num = 0;
+module_param_array(rtw_rx_ampdu_sz_limit_2ss, uint, &rtw_rx_ampdu_sz_limit_2ss_num, 0644);
+MODULE_PARM_DESC(rtw_rx_ampdu_sz_limit_2ss, "RX AMPDU size limit for 2SS link of each BW, 0xFF: no limitation");
+
+static uint rtw_rx_ampdu_sz_limit_3ss[4] = CONFIG_RTW_RX_AMPDU_SZ_LIMIT_3SS;
+static uint rtw_rx_ampdu_sz_limit_3ss_num = 0;
+module_param_array(rtw_rx_ampdu_sz_limit_3ss, uint, &rtw_rx_ampdu_sz_limit_3ss_num, 0644);
+MODULE_PARM_DESC(rtw_rx_ampdu_sz_limit_3ss, "RX AMPDU size limit for 3SS link of each BW, 0xFF: no limitation");
+
+static uint rtw_rx_ampdu_sz_limit_4ss[4] = CONFIG_RTW_RX_AMPDU_SZ_LIMIT_4SS;
+static uint rtw_rx_ampdu_sz_limit_4ss_num = 0;
+module_param_array(rtw_rx_ampdu_sz_limit_4ss, uint, &rtw_rx_ampdu_sz_limit_4ss_num, 0644);
+MODULE_PARM_DESC(rtw_rx_ampdu_sz_limit_4ss, "RX AMPDU size limit for 4SS link of each BW, 0xFF: no limitation");
+
+/* Short GI support Bit Map
+* BIT0 - 20MHz, 0: non-support, 1: support
+* BIT1 - 40MHz, 0: non-support, 1: support
+* BIT2 - 80MHz, 0: non-support, 1: support
+* BIT3 - 160MHz, 0: non-support, 1: support */
+int rtw_short_gi = 0xf;
+/* BIT0: Enable VHT LDPC Rx, BIT1: Enable VHT LDPC Tx, BIT4: Enable HT LDPC Rx, BIT5: Enable HT LDPC Tx */
+int rtw_ldpc_cap = 0x33;
+/* BIT0: Enable VHT STBC Rx, BIT1: Enable VHT STBC Tx, BIT4: Enable HT STBC Rx, BIT5: Enable HT STBC Tx */
+int rtw_stbc_cap = 0x13;
+/*
+* BIT0: Enable VHT SU Beamformer
+* BIT1: Enable VHT SU Beamformee
+* BIT2: Enable VHT MU Beamformer, depend on VHT SU Beamformer
+* BIT3: Enable VHT MU Beamformee, depend on VHT SU Beamformee
+* BIT4: Enable HT Beamformer
+* BIT5: Enable HT Beamformee
+*/
+int rtw_beamform_cap = BIT(1) | BIT(3);
+int rtw_bfer_rf_number = 0; /*BeamformerCapRfNum Rf path number, 0 for auto, others for manual*/
+int rtw_bfee_rf_number = 0; /*BeamformeeCapRfNum  Rf path number, 0 for auto, others for manual*/
+
+#endif /* CONFIG_80211N_HT */
+
+#ifdef CONFIG_80211AC_VHT
+int rtw_vht_enable = 1; /* 0:disable, 1:enable, 2:force auto enable */
+module_param(rtw_vht_enable, int, 0644);
+
+int rtw_ampdu_factor = 7;
+
+uint rtw_vht_rx_mcs_map = 0xaaaa;
+module_param(rtw_vht_rx_mcs_map, uint, 0644);
+MODULE_PARM_DESC(rtw_vht_rx_mcs_map, "VHT RX MCS map");
+#endif /* CONFIG_80211AC_VHT */
+
+int rtw_lowrate_two_xmit = 1;/* Use 2 path Tx to transmit MCS0~7 and legacy mode */
+
+int rtw_rf_config = RF_TYPE_MAX;
+module_param(rtw_rf_config, int, 0644);
+
+/* 0: not check in watch dog, 1: check in watch dog  */
+int rtw_check_hw_status = 0;
+
+int rtw_low_power = 0;
+#ifdef CONFIG_WIFI_TEST
+	int rtw_wifi_spec = 1;/* for wifi test */
+#else
+	int rtw_wifi_spec = 0;
+#endif
+
+int rtw_special_rf_path = 0; /* 0: 2T2R ,1: only turn on path A 1T1R */
+
+char rtw_country_unspecified[] = {0xFF, 0xFF, 0x00};
+char *rtw_country_code = rtw_country_unspecified;
+module_param(rtw_country_code, charp, 0644);
+MODULE_PARM_DESC(rtw_country_code, "The default country code (in alpha2)");
+
+int rtw_channel_plan = CONFIG_RTW_CHPLAN;
+module_param(rtw_channel_plan, int, 0644);
+MODULE_PARM_DESC(rtw_channel_plan, "The default chplan ID when rtw_alpha2 is not specified or valid");
+
+static uint rtw_excl_chs[MAX_CHANNEL_NUM] = CONFIG_RTW_EXCL_CHS;
+static int rtw_excl_chs_num = 0;
+module_param_array(rtw_excl_chs, uint, &rtw_excl_chs_num, 0644);
+MODULE_PARM_DESC(rtw_excl_chs, "exclusive channel array");
+
+/*if concurrent softap + p2p(GO) is needed, this param lets p2p response full channel list.
+But Softap must be SHUT DOWN once P2P decide to set up connection and become a GO.*/
+#ifdef CONFIG_FULL_CH_IN_P2P_HANDSHAKE
+	int rtw_full_ch_in_p2p_handshake = 1; /* reply full channel list*/
+#else
+	int rtw_full_ch_in_p2p_handshake = 0; /* reply only softap channel*/
+#endif
+
+#ifdef CONFIG_BT_COEXIST
+int rtw_btcoex_enable = 2;
+module_param(rtw_btcoex_enable, int, 0644);
+MODULE_PARM_DESC(rtw_btcoex_enable, "BT co-existence on/off, 0:off, 1:on, 2:by efuse");
+
+int rtw_ant_num = 0;
+module_param(rtw_ant_num, int, 0644);
+MODULE_PARM_DESC(rtw_ant_num, "Antenna number setting, 0:by efuse");
+
+int rtw_bt_iso = 2;/* 0:Low, 1:High, 2:From Efuse */
+int rtw_bt_sco = 3;/* 0:Idle, 1:None-SCO, 2:SCO, 3:From Counter, 4.Busy, 5.OtherBusy */
+int rtw_bt_ampdu = 1 ; /* 0:Disable BT control A-MPDU, 1:Enable BT control A-MPDU. */
+#endif /* CONFIG_BT_COEXIST */
+
+int rtw_AcceptAddbaReq = _TRUE;/* 0:Reject AP's Add BA req, 1:Accept AP's Add BA req. */
+
+int rtw_antdiv_cfg = 2; /* 0:OFF , 1:ON, 2:decide by Efuse config */
+int rtw_antdiv_type = 0
+	; /* 0:decide by efuse  1: for 88EE, 1Tx and 1RxCG are diversity.(2 Ant with SPDT), 2:  for 88EE, 1Tx and 2Rx are diversity.( 2 Ant, Tx and RxCG are both on aux port, RxCS is on main port ), 3: for 88EE, 1Tx and 1RxCG are fixed.(1Ant, Tx and RxCG are both on aux port) */
+
+int rtw_drv_ant_band_switch = 1; /* 0:OFF , 1:ON, Driver control antenna band switch*/
+
+int rtw_single_ant_path; /*0:main ant , 1:aux ant , Fixed single antenna path, default main ant*/
+
+/* 0: doesn't switch, 1: switch from usb2.0 to usb 3.0 2: switch from usb3.0 to usb 2.0 */
+int rtw_switch_usb_mode = 0;
+
+#ifdef CONFIG_USB_AUTOSUSPEND
+int rtw_enusbss = 1;/* 0:disable,1:enable */
+#else
+int rtw_enusbss = 0;/* 0:disable,1:enable */
+#endif
+
+int rtw_hwpdn_mode = 2; /* 0:disable,1:enable,2: by EFUSE config */
+
+#ifdef CONFIG_HW_PWRP_DETECTION
+int rtw_hwpwrp_detect = 1;
+#else
+int rtw_hwpwrp_detect = 0; /* HW power  ping detect 0:disable , 1:enable */
+#endif
+
+#ifdef CONFIG_USB_HCI
+int rtw_hw_wps_pbc = 1;
+#else
+int rtw_hw_wps_pbc = 0;
+#endif
+
+#ifdef CONFIG_TX_MCAST2UNI
+int rtw_mc2u_disable = 0;
+#endif /* CONFIG_TX_MCAST2UNI */
+
+#ifdef CONFIG_80211D
+int rtw_80211d = 0;
+#endif
+
+#ifdef CONFIG_PCI_ASPM
+/* CLK_REQ:BIT0 L0s:BIT1 ASPM_L1:BIT2 L1Off:BIT3*/
+int	rtw_pci_aspm_enable = 0x5;
+#else
+int	rtw_pci_aspm_enable;
+#endif
+
+#ifdef CONFIG_QOS_OPTIMIZATION
+int rtw_qos_opt_enable = 1; /* 0: disable,1:enable */
+#else
+int rtw_qos_opt_enable = 0; /* 0: disable,1:enable */
+#endif
+module_param(rtw_qos_opt_enable, int, 0644);
+
+#ifdef CONFIG_RTW_ACS
+int rtw_acs_auto_scan = 0; /*0:disable, 1:enable*/
+module_param(rtw_acs_auto_scan, int, 0644);
+
+int rtw_acs = 1;
+module_param(rtw_acs, int, 0644);
+#endif
+
+#ifdef CONFIG_BACKGROUND_NOISE_MONITOR
+int rtw_nm = 1;/*noise monitor*/
+module_param(rtw_nm, int, 0644);
+#endif
+
+char *ifname = "wlan%d";
+module_param(ifname, charp, 0644);
+MODULE_PARM_DESC(ifname, "The default name to allocate for first interface");
+
+#ifdef CONFIG_PLATFORM_ANDROID
+	char *if2name = "p2p%d";
+#else /* CONFIG_PLATFORM_ANDROID */
+	char *if2name = "wlan%d";
+#endif /* CONFIG_PLATFORM_ANDROID */
+module_param(if2name, charp, 0644);
+MODULE_PARM_DESC(if2name, "The default name to allocate for second interface");
+
+char *rtw_initmac = 0;  /* temp mac address if users want to use instead of the mac address in Efuse */
+
+#ifdef CONFIG_CONCURRENT_MODE
+
+	#if (CONFIG_IFACE_NUMBER > 2)
+		int rtw_virtual_iface_num = CONFIG_IFACE_NUMBER - 1;
+		module_param(rtw_virtual_iface_num, int, 0644);
+	#else
+		int rtw_virtual_iface_num = 1;
+	#endif
+
+#endif
+#ifdef CONFIG_AP_MODE
+u8 rtw_bmc_tx_rate = MGN_UNKNOWN;
+#endif
+module_param(rtw_pwrtrim_enable, int, 0644);
+module_param(rtw_initmac, charp, 0644);
+module_param(rtw_special_rf_path, int, 0644);
+module_param(rtw_chip_version, int, 0644);
+module_param(rtw_rfintfs, int, 0644);
+module_param(rtw_lbkmode, int, 0644);
+module_param(rtw_network_mode, int, 0644);
+module_param(rtw_channel, int, 0644);
+module_param(rtw_mp_mode, int, 0644);
+module_param(rtw_wmm_enable, int, 0644);
+#ifdef CONFIG_WMMPS_STA
+module_param(rtw_uapsd_max_sp, int, 0644);
+module_param(rtw_uapsd_ac_enable, int, 0644);
+module_param(rtw_wmm_smart_ps, int, 0644);
+#endif /* CONFIG_WMMPS_STA */
+module_param(rtw_vrtl_carrier_sense, int, 0644);
+module_param(rtw_vcs_type, int, 0644);
+module_param(rtw_busy_thresh, int, 0644);
+
+#ifdef CONFIG_80211N_HT
+module_param(rtw_ht_enable, int, 0644);
+module_param(rtw_bw_mode, int, 0644);
+module_param(rtw_ampdu_enable, int, 0644);
+module_param(rtw_rx_stbc, int, 0644);
+module_param(rtw_rx_ampdu_amsdu, int, 0644);
+module_param(rtw_tx_ampdu_amsdu, int, 0644);
+#endif /* CONFIG_80211N_HT */
+
+#ifdef CONFIG_BEAMFORMING
+module_param(rtw_beamform_cap, int, 0644);
+#endif
+module_param(rtw_lowrate_two_xmit, int, 0644);
+
+module_param(rtw_power_mgnt, int, 0644);
+module_param(rtw_smart_ps, int, 0644);
+module_param(rtw_low_power, int, 0644);
+module_param(rtw_wifi_spec, int, 0644);
+
+module_param(rtw_full_ch_in_p2p_handshake, int, 0644);
+module_param(rtw_antdiv_cfg, int, 0644);
+module_param(rtw_antdiv_type, int, 0644);
+
+module_param(rtw_drv_ant_band_switch, int, 0644);
+module_param(rtw_single_ant_path, int, 0644);
+
+module_param(rtw_switch_usb_mode, int, 0644);
+
+module_param(rtw_enusbss, int, 0644);
+module_param(rtw_hwpdn_mode, int, 0644);
+module_param(rtw_hwpwrp_detect, int, 0644);
+
+module_param(rtw_hw_wps_pbc, int, 0644);
+module_param(rtw_check_hw_status, int, 0644);
+
+#ifdef CONFIG_PCI_HCI
+module_param(rtw_pci_aspm_enable, int, 0644);
+#endif
+
+#ifdef CONFIG_TX_EARLY_MODE
+module_param(rtw_early_mode, int, 0644);
+#endif
+#ifdef CONFIG_ADAPTOR_INFO_CACHING_FILE
+char *rtw_adaptor_info_caching_file_path = "/data/misc/wifi/rtw_cache";
+module_param(rtw_adaptor_info_caching_file_path, charp, 0644);
+MODULE_PARM_DESC(rtw_adaptor_info_caching_file_path, "The path of adapter info cache file");
+#endif /* CONFIG_ADAPTOR_INFO_CACHING_FILE */
+
+#ifdef CONFIG_LAYER2_ROAMING
+uint rtw_max_roaming_times = 2;
+module_param(rtw_max_roaming_times, uint, 0644);
+MODULE_PARM_DESC(rtw_max_roaming_times, "The max roaming times to try");
+#endif /* CONFIG_LAYER2_ROAMING */
+
+#ifdef CONFIG_IOL
+int rtw_fw_iol = 1;
+module_param(rtw_fw_iol, int, 0644);
+MODULE_PARM_DESC(rtw_fw_iol, "FW IOL. 0:Disable, 1:enable, 2:by usb speed");
+#endif /* CONFIG_IOL */
+
+#ifdef CONFIG_FILE_FWIMG
+char *rtw_fw_file_path = "/system/etc/firmware/rtlwifi/FW_NIC.BIN";
+module_param(rtw_fw_file_path, charp, 0644);
+MODULE_PARM_DESC(rtw_fw_file_path, "The path of fw image");
+
+char *rtw_fw_wow_file_path = "/system/etc/firmware/rtlwifi/FW_WoWLAN.BIN";
+module_param(rtw_fw_wow_file_path, charp, 0644);
+MODULE_PARM_DESC(rtw_fw_wow_file_path, "The path of fw for Wake on Wireless image");
+
+#ifdef CONFIG_MP_INCLUDED
+char *rtw_fw_mp_bt_file_path = "";
+module_param(rtw_fw_mp_bt_file_path, charp, 0644);
+MODULE_PARM_DESC(rtw_fw_mp_bt_file_path, "The path of fw for MP-BT image");
+#endif /* CONFIG_MP_INCLUDED */
+#endif /* CONFIG_FILE_FWIMG */
+
+#ifdef CONFIG_TX_MCAST2UNI
+module_param(rtw_mc2u_disable, int, 0644);
+#endif /* CONFIG_TX_MCAST2UNI */
+
+#ifdef CONFIG_80211D
+module_param(rtw_80211d, int, 0644);
+MODULE_PARM_DESC(rtw_80211d, "Enable 802.11d mechanism");
+#endif
+
+#ifdef CONFIG_ADVANCE_OTA
+/*	BIT(0): OTA continuous rotated test within low RSSI,1R CCA in path B
+	BIT(1) & BIT(2): OTA continuous rotated test with low high RSSI */
+/* Experimental environment: shielding room with half of absorber and 2~3 rotation per minute */
+int rtw_advnace_ota;
+module_param(rtw_advnace_ota, int, 0644);
+#endif
+
+uint rtw_notch_filter = RTW_NOTCH_FILTER;
+module_param(rtw_notch_filter, uint, 0644);
+MODULE_PARM_DESC(rtw_notch_filter, "0:Disable, 1:Enable, 2:Enable only for P2P");
+
+uint rtw_hiq_filter = CONFIG_RTW_HIQ_FILTER;
+module_param(rtw_hiq_filter, uint, 0644);
+MODULE_PARM_DESC(rtw_hiq_filter, "0:allow all, 1:allow special, 2:deny all");
+
+uint rtw_adaptivity_en = CONFIG_RTW_ADAPTIVITY_EN;
+module_param(rtw_adaptivity_en, uint, 0644);
+MODULE_PARM_DESC(rtw_adaptivity_en, "0:disable, 1:enable");
+
+uint rtw_adaptivity_mode = CONFIG_RTW_ADAPTIVITY_MODE;
+module_param(rtw_adaptivity_mode, uint, 0644);
+MODULE_PARM_DESC(rtw_adaptivity_mode, "0:normal, 1:carrier sense");
+
+int rtw_adaptivity_th_l2h_ini = CONFIG_RTW_ADAPTIVITY_TH_L2H_INI;
+module_param(rtw_adaptivity_th_l2h_ini, int, 0644);
+MODULE_PARM_DESC(rtw_adaptivity_th_l2h_ini, "th_l2h_ini for Adaptivity");
+
+int rtw_adaptivity_th_edcca_hl_diff = CONFIG_RTW_ADAPTIVITY_TH_EDCCA_HL_DIFF;
+module_param(rtw_adaptivity_th_edcca_hl_diff, int, 0644);
+MODULE_PARM_DESC(rtw_adaptivity_th_edcca_hl_diff, "th_edcca_hl_diff for Adaptivity");
+
+#ifdef CONFIG_DFS_MASTER
+uint rtw_dfs_region_domain = CONFIG_RTW_DFS_REGION_DOMAIN;
+module_param(rtw_dfs_region_domain, uint, 0644);
+MODULE_PARM_DESC(rtw_dfs_region_domain, "0:UNKNOWN, 1:FCC, 2:MKK, 3:ETSI");
+#endif
+
+uint rtw_amplifier_type_2g = CONFIG_RTW_AMPLIFIER_TYPE_2G;
+module_param(rtw_amplifier_type_2g, uint, 0644);
+MODULE_PARM_DESC(rtw_amplifier_type_2g, "BIT3:2G ext-PA, BIT4:2G ext-LNA");
+
+uint rtw_amplifier_type_5g = CONFIG_RTW_AMPLIFIER_TYPE_5G;
+module_param(rtw_amplifier_type_5g, uint, 0644);
+MODULE_PARM_DESC(rtw_amplifier_type_5g, "BIT6:5G ext-PA, BIT7:5G ext-LNA");
+
+uint rtw_RFE_type = CONFIG_RTW_RFE_TYPE;
+module_param(rtw_RFE_type, uint, 0644);
+MODULE_PARM_DESC(rtw_RFE_type, "default init value:64");
+
+uint rtw_powertracking_type = 64;
+module_param(rtw_powertracking_type, uint, 0644);
+MODULE_PARM_DESC(rtw_powertracking_type, "default init value:64");
+
+uint rtw_GLNA_type = CONFIG_RTW_GLNA_TYPE;
+module_param(rtw_GLNA_type, uint, 0644);
+MODULE_PARM_DESC(rtw_GLNA_type, "default init value:0");
+
+uint rtw_TxBBSwing_2G = 0xFF;
+module_param(rtw_TxBBSwing_2G, uint, 0644);
+MODULE_PARM_DESC(rtw_TxBBSwing_2G, "default init value:0xFF");
+
+uint rtw_TxBBSwing_5G = 0xFF;
+module_param(rtw_TxBBSwing_5G, uint, 0644);
+MODULE_PARM_DESC(rtw_TxBBSwing_5G, "default init value:0xFF");
+
+uint rtw_OffEfuseMask = 0;
+module_param(rtw_OffEfuseMask, uint, 0644);
+MODULE_PARM_DESC(rtw_OffEfuseMask, "default open Efuse Mask value:0");
+
+uint rtw_FileMaskEfuse = 0;
+module_param(rtw_FileMaskEfuse, uint, 0644);
+MODULE_PARM_DESC(rtw_FileMaskEfuse, "default drv Mask Efuse value:0");
+
+uint rtw_rxgain_offset_2g = 0;
+module_param(rtw_rxgain_offset_2g, uint, 0644);
+MODULE_PARM_DESC(rtw_rxgain_offset_2g, "default RF Gain 2G Offset value:0");
+
+uint rtw_rxgain_offset_5gl = 0;
+module_param(rtw_rxgain_offset_5gl, uint, 0644);
+MODULE_PARM_DESC(rtw_rxgain_offset_5gl, "default RF Gain 5GL Offset value:0");
+
+uint rtw_rxgain_offset_5gm = 0;
+module_param(rtw_rxgain_offset_5gm, uint, 0644);
+MODULE_PARM_DESC(rtw_rxgain_offset_5gm, "default RF Gain 5GM Offset value:0");
+
+uint rtw_rxgain_offset_5gh = 0;
+module_param(rtw_rxgain_offset_5gh, uint, 0644);
+MODULE_PARM_DESC(rtw_rxgain_offset_5gm, "default RF Gain 5GL Offset value:0");
+
+uint rtw_pll_ref_clk_sel = CONFIG_RTW_PLL_REF_CLK_SEL;
+module_param(rtw_pll_ref_clk_sel, uint, 0644);
+MODULE_PARM_DESC(rtw_pll_ref_clk_sel, "force pll_ref_clk_sel, 0xF:use autoload value");
+
+int rtw_tx_pwr_by_rate = CONFIG_TXPWR_BY_RATE_EN;
+module_param(rtw_tx_pwr_by_rate, int, 0644);
+MODULE_PARM_DESC(rtw_tx_pwr_by_rate, "0:Disable, 1:Enable, 2: Depend on efuse");
+
+#ifdef CONFIG_TXPWR_LIMIT
+int rtw_tx_pwr_lmt_enable = CONFIG_TXPWR_LIMIT_EN;
+module_param(rtw_tx_pwr_lmt_enable, int, 0644);
+MODULE_PARM_DESC(rtw_tx_pwr_lmt_enable, "0:Disable, 1:Enable, 2: Depend on efuse");
+#endif
+
+static int rtw_target_tx_pwr_2g_a[RATE_SECTION_NUM] = CONFIG_RTW_TARGET_TX_PWR_2G_A;
+static int rtw_target_tx_pwr_2g_a_num = 0;
+module_param_array(rtw_target_tx_pwr_2g_a, int, &rtw_target_tx_pwr_2g_a_num, 0644);
+MODULE_PARM_DESC(rtw_target_tx_pwr_2g_a, "2.4G target tx power (unit:dBm) of RF path A for each rate section, should match the real calibrate power, -1: undefined");
+
+static int rtw_target_tx_pwr_2g_b[RATE_SECTION_NUM] = CONFIG_RTW_TARGET_TX_PWR_2G_B;
+static int rtw_target_tx_pwr_2g_b_num = 0;
+module_param_array(rtw_target_tx_pwr_2g_b, int, &rtw_target_tx_pwr_2g_b_num, 0644);
+MODULE_PARM_DESC(rtw_target_tx_pwr_2g_b, "2.4G target tx power (unit:dBm) of RF path B for each rate section, should match the real calibrate power, -1: undefined");
+
+static int rtw_target_tx_pwr_2g_c[RATE_SECTION_NUM] = CONFIG_RTW_TARGET_TX_PWR_2G_C;
+static int rtw_target_tx_pwr_2g_c_num = 0;
+module_param_array(rtw_target_tx_pwr_2g_c, int, &rtw_target_tx_pwr_2g_c_num, 0644);
+MODULE_PARM_DESC(rtw_target_tx_pwr_2g_c, "2.4G target tx power (unit:dBm) of RF path C for each rate section, should match the real calibrate power, -1: undefined");
+
+static int rtw_target_tx_pwr_2g_d[RATE_SECTION_NUM] = CONFIG_RTW_TARGET_TX_PWR_2G_D;
+static int rtw_target_tx_pwr_2g_d_num = 0;
+module_param_array(rtw_target_tx_pwr_2g_d, int, &rtw_target_tx_pwr_2g_d_num, 0644);
+MODULE_PARM_DESC(rtw_target_tx_pwr_2g_d, "2.4G target tx power (unit:dBm) of RF path D for each rate section, should match the real calibrate power, -1: undefined");
+
+#ifdef CONFIG_IEEE80211_BAND_5GHZ
+static int rtw_target_tx_pwr_5g_a[RATE_SECTION_NUM - 1] = CONFIG_RTW_TARGET_TX_PWR_5G_A;
+static int rtw_target_tx_pwr_5g_a_num = 0;
+module_param_array(rtw_target_tx_pwr_5g_a, int, &rtw_target_tx_pwr_5g_a_num, 0644);
+MODULE_PARM_DESC(rtw_target_tx_pwr_5g_a, "5G target tx power (unit:dBm) of RF path A for each rate section, should match the real calibrate power, -1: undefined");
+
+static int rtw_target_tx_pwr_5g_b[RATE_SECTION_NUM - 1] = CONFIG_RTW_TARGET_TX_PWR_5G_B;
+static int rtw_target_tx_pwr_5g_b_num = 0;
+module_param_array(rtw_target_tx_pwr_5g_b, int, &rtw_target_tx_pwr_5g_b_num, 0644);
+MODULE_PARM_DESC(rtw_target_tx_pwr_5g_b, "5G target tx power (unit:dBm) of RF path B for each rate section, should match the real calibrate power, -1: undefined");
+
+static int rtw_target_tx_pwr_5g_c[RATE_SECTION_NUM - 1] = CONFIG_RTW_TARGET_TX_PWR_5G_C;
+static int rtw_target_tx_pwr_5g_c_num = 0;
+module_param_array(rtw_target_tx_pwr_5g_c, int, &rtw_target_tx_pwr_5g_c_num, 0644);
+MODULE_PARM_DESC(rtw_target_tx_pwr_5g_c, "5G target tx power (unit:dBm) of RF path C for each rate section, should match the real calibrate power, -1: undefined");
+
+static int rtw_target_tx_pwr_5g_d[RATE_SECTION_NUM - 1] = CONFIG_RTW_TARGET_TX_PWR_5G_D;
+static int rtw_target_tx_pwr_5g_d_num = 0;
+module_param_array(rtw_target_tx_pwr_5g_d, int, &rtw_target_tx_pwr_5g_d_num, 0644);
+MODULE_PARM_DESC(rtw_target_tx_pwr_5g_d, "5G target tx power (unit:dBm) of RF path D for each rate section, should match the real calibrate power, -1: undefined");
+#endif /* CONFIG_IEEE80211_BAND_5GHZ */
+
+int rtw_tsf_update_pause_factor = CONFIG_TSF_UPDATE_PAUSE_FACTOR;
+module_param(rtw_tsf_update_pause_factor, int, 0644);
+MODULE_PARM_DESC(rtw_tsf_update_pause_factor, "num of bcn intervals to stay TSF update pause status");
+
+int rtw_tsf_update_restore_factor = CONFIG_TSF_UPDATE_RESTORE_FACTOR;
+module_param(rtw_tsf_update_restore_factor, int, 0644);
+MODULE_PARM_DESC(rtw_tsf_update_restore_factor, "num of bcn intervals to stay TSF update restore status");
+
+#ifdef CONFIG_LOAD_PHY_PARA_FROM_FILE
+char *rtw_phy_file_path = REALTEK_CONFIG_PATH;
+module_param(rtw_phy_file_path, charp, 0644);
+MODULE_PARM_DESC(rtw_phy_file_path, "The path of phy parameter");
+/* PHY FILE Bit Map
+* BIT0 - MAC,				0: non-support, 1: support
+* BIT1 - BB,					0: non-support, 1: support
+* BIT2 - BB_PG,				0: non-support, 1: support
+* BIT3 - BB_MP,				0: non-support, 1: support
+* BIT4 - RF,					0: non-support, 1: support
+* BIT5 - RF_TXPWR_TRACK,	0: non-support, 1: support
+* BIT6 - RF_TXPWR_LMT,		0: non-support, 1: support */
+int rtw_load_phy_file = (BIT2 | BIT6);
+module_param(rtw_load_phy_file, int, 0644);
+MODULE_PARM_DESC(rtw_load_phy_file, "PHY File Bit Map");
+int rtw_decrypt_phy_file = 0;
+module_param(rtw_decrypt_phy_file, int, 0644);
+MODULE_PARM_DESC(rtw_decrypt_phy_file, "Enable Decrypt PHY File");
+#endif
+
+#ifdef CONFIG_SUPPORT_TRX_SHARED
+#ifdef DFT_TRX_SHARE_MODE
+int rtw_trx_share_mode = DFT_TRX_SHARE_MODE;
+#else
+int rtw_trx_share_mode = 0;
+#endif
+module_param(rtw_trx_share_mode, int, 0644);
+MODULE_PARM_DESC(rtw_trx_share_mode, "TRx FIFO Shared");
+#endif
+
+#ifdef CONFIG_DYNAMIC_SOML
+uint rtw_dynamic_soml_en = 1;
+module_param(rtw_dynamic_soml_en, int, 0644);
+MODULE_PARM_DESC(rtw_dynamic_soml_en, "0: disable, 1: enable with default param, 2: enable with specified param.");
+
+uint rtw_dynamic_soml_train_num = 0;
+module_param(rtw_dynamic_soml_train_num, int, 0644);
+MODULE_PARM_DESC(rtw_dynamic_soml_train_num, "SOML training number");
+
+uint rtw_dynamic_soml_interval = 0;
+module_param(rtw_dynamic_soml_interval, int, 0644);
+MODULE_PARM_DESC(rtw_dynamic_soml_interval, "SOML training interval");
+
+uint rtw_dynamic_soml_period = 0;
+module_param(rtw_dynamic_soml_period, int, 0644);
+MODULE_PARM_DESC(rtw_dynamic_soml_period, "SOML training period");
+
+uint rtw_dynamic_soml_delay = 0;
+module_param(rtw_dynamic_soml_delay, int, 0644);
+MODULE_PARM_DESC(rtw_dynamic_soml_delay, "SOML training delay");
+#endif
+
+
+int _netdev_open(struct net_device *pnetdev);
+int netdev_open(struct net_device *pnetdev);
+static int netdev_close(struct net_device *pnetdev);
+#ifdef CONFIG_PLATFORM_INTEL_BYT
+extern int rtw_sdio_set_power(int on);
+#endif /* CONFIG_PLATFORM_INTEL_BYT */
+
+#ifdef CONFIG_MCC_MODE
+/* enable MCC mode or not */
+int rtw_en_mcc = 1;
+/* can referece following value before insmod driver */
+int rtw_mcc_ap_bw20_target_tx_tp = MCC_AP_BW20_TARGET_TX_TP;
+int rtw_mcc_ap_bw40_target_tx_tp = MCC_AP_BW40_TARGET_TX_TP;
+int rtw_mcc_ap_bw80_target_tx_tp = MCC_AP_BW80_TARGET_TX_TP;
+int rtw_mcc_sta_bw20_target_tx_tp = MCC_STA_BW20_TARGET_TX_TP;
+int rtw_mcc_sta_bw40_target_tx_tp = MCC_STA_BW40_TARGET_TX_TP;
+int rtw_mcc_sta_bw80_target_tx_tp = MCC_STA_BW80_TARGET_TX_TP;
+int rtw_mcc_single_tx_cri = MCC_SINGLE_TX_CRITERIA;
+int rtw_mcc_policy_table_idx = 0;
+int rtw_mcc_duration = 0;
+int rtw_mcc_enable_runtime_duration = 1;
+module_param(rtw_en_mcc, int, 0644);
+module_param(rtw_mcc_single_tx_cri, int, 0644);
+module_param(rtw_mcc_ap_bw20_target_tx_tp, int, 0644);
+module_param(rtw_mcc_ap_bw40_target_tx_tp, int, 0644);
+module_param(rtw_mcc_ap_bw80_target_tx_tp, int, 0644);
+module_param(rtw_mcc_sta_bw20_target_tx_tp, int, 0644);
+module_param(rtw_mcc_sta_bw40_target_tx_tp, int, 0644);
+module_param(rtw_mcc_sta_bw80_target_tx_tp, int, 0644);
+module_param(rtw_mcc_policy_table_idx, int, 0644);
+module_param(rtw_mcc_duration, int, 0644);
+#endif /*CONFIG_MCC_MODE */
+
+#ifdef CONFIG_RTW_NAPI
+/*following setting should define NAPI in Makefile
+enable napi only = 1, disable napi = 0*/
+int rtw_en_napi = 1;
+module_param(rtw_en_napi, int, 0644);
+#ifdef CONFIG_RTW_NAPI_DYNAMIC
+int rtw_napi_threshold = 100; /* unit: Mbps */
+module_param(rtw_napi_threshold, int, 0644);
+#endif /* CONFIG_RTW_NAPI_DYNAMIC */
+#ifdef CONFIG_RTW_GRO
+/*following setting should define GRO in Makefile
+enable gro = 1, disable gro = 0*/
+int rtw_en_gro = 1;
+module_param(rtw_en_gro, int, 0644);
+#endif /* CONFIG_RTW_GRO */
+#endif /* CONFIG_RTW_NAPI */
+
+#ifdef RTW_IQK_FW_OFFLOAD
+int rtw_iqk_fw_offload = 1;
+#else
+int rtw_iqk_fw_offload;
+#endif /* RTW_IQK_FW_OFFLOAD */
+module_param(rtw_iqk_fw_offload, int, 0644);
+
+#ifdef RTW_CHANNEL_SWITCH_OFFLOAD
+int rtw_ch_switch_offload = 0;
+#else
+int rtw_ch_switch_offload;
+#endif /* RTW_CHANNEL_SWITCH_OFFLOAD */
+module_param(rtw_ch_switch_offload, int, 0644);
+
+#ifdef CONFIG_TDLS
+int rtw_en_tdls = 1;
+module_param(rtw_en_tdls, int, 0644);
+#endif
+
+#ifdef CONFIG_FW_OFFLOAD_PARAM_INIT
+int rtw_fw_param_init = 1;
+module_param(rtw_fw_param_init, int, 0644);
+#endif
+
+#ifdef CONFIG_WOWLAN
+/*
+ * bit[0]: magic packet wake up
+ * bit[1]: unucast packet(HW/FW unuicast)
+ * bit[2]: deauth wake up
+ */
+uint rtw_wakeup_event = RTW_WAKEUP_EVENT;
+module_param(rtw_wakeup_event, uint, 0644);
+#endif
+
+void rtw_regsty_load_target_tx_power(struct registry_priv *regsty)
+{
+	int path, rs;
+	int *target_tx_pwr;
+
+	for (path = RF_PATH_A; path < RF_PATH_MAX; path++) {
+		if (path == RF_PATH_A)
+			target_tx_pwr = rtw_target_tx_pwr_2g_a;
+		else if (path == RF_PATH_B)
+			target_tx_pwr = rtw_target_tx_pwr_2g_b;
+		else if (path == RF_PATH_C)
+			target_tx_pwr = rtw_target_tx_pwr_2g_c;
+		else if (path == RF_PATH_D)
+			target_tx_pwr = rtw_target_tx_pwr_2g_d;
+
+		for (rs = CCK; rs < RATE_SECTION_NUM; rs++)
+			regsty->target_tx_pwr_2g[path][rs] = target_tx_pwr[rs];
+	}
+
+#ifdef CONFIG_IEEE80211_BAND_5GHZ
+	for (path = RF_PATH_A; path < RF_PATH_MAX; path++) {
+		if (path == RF_PATH_A)
+			target_tx_pwr = rtw_target_tx_pwr_5g_a;
+		else if (path == RF_PATH_B)
+			target_tx_pwr = rtw_target_tx_pwr_5g_b;
+		else if (path == RF_PATH_C)
+			target_tx_pwr = rtw_target_tx_pwr_5g_c;
+		else if (path == RF_PATH_D)
+			target_tx_pwr = rtw_target_tx_pwr_5g_d;
+
+		for (rs = OFDM; rs < RATE_SECTION_NUM; rs++)
+			regsty->target_tx_pwr_5g[path][rs - 1] = target_tx_pwr[rs - 1];
+	}
+#endif /* CONFIG_IEEE80211_BAND_5GHZ */
+}
+
+inline void rtw_regsty_load_excl_chs(struct registry_priv *regsty)
+{
+	int i;
+	int ch_num = 0;
+
+	for (i = 0; i < MAX_CHANNEL_NUM; i++)
+		if (((u8)rtw_excl_chs[i]) != 0)
+			regsty->excl_chs[ch_num++] = (u8)rtw_excl_chs[i];
+
+	if (ch_num < MAX_CHANNEL_NUM)
+		regsty->excl_chs[ch_num] = 0;
+}
+
+#ifdef CONFIG_80211N_HT
+inline void rtw_regsty_init_rx_ampdu_sz_limit(struct registry_priv *regsty)
+{
+	int i, j;
+	uint *sz_limit;
+
+	for (i = 0; i < 4; i++) {
+		if (i == 0)
+			sz_limit = rtw_rx_ampdu_sz_limit_1ss;
+		else if (i == 1)
+			sz_limit = rtw_rx_ampdu_sz_limit_2ss;
+		else if (i == 2)
+			sz_limit = rtw_rx_ampdu_sz_limit_3ss;
+		else if (i == 3)
+			sz_limit = rtw_rx_ampdu_sz_limit_4ss;
+
+		for (j = 0; j < 4; j++)
+			regsty->rx_ampdu_sz_limit_by_nss_bw[i][j] = sz_limit[j];
+	}
+}
+#endif /* CONFIG_80211N_HT */
+
+uint loadparam(_adapter *padapter)
+{
+	uint status = _SUCCESS;
+	struct registry_priv  *registry_par = &padapter->registrypriv;
+
+
+#ifdef CONFIG_RTW_DEBUG
+	if (rtw_drv_log_level >= _DRV_MAX_)
+		rtw_drv_log_level = _DRV_DEBUG_;
+#endif
+
+	registry_par->chip_version = (u8)rtw_chip_version;
+	registry_par->rfintfs = (u8)rtw_rfintfs;
+	registry_par->lbkmode = (u8)rtw_lbkmode;
+	/* registry_par->hci = (u8)hci; */
+	registry_par->network_mode  = (u8)rtw_network_mode;
+
+	_rtw_memcpy(registry_par->ssid.Ssid, "ANY", 3);
+	registry_par->ssid.SsidLength = 3;
+
+	registry_par->channel = (u8)rtw_channel;
+	registry_par->wireless_mode = (u8)rtw_wireless_mode;
+
+	if (IsSupported24G(registry_par->wireless_mode) && (!is_supported_5g(registry_par->wireless_mode))
+	    && (registry_par->channel > 14))
+		registry_par->channel = 1;
+	else if (is_supported_5g(registry_par->wireless_mode) && (!IsSupported24G(registry_par->wireless_mode))
+		 && (registry_par->channel <= 14))
+		registry_par->channel = 36;
+
+	registry_par->vrtl_carrier_sense = (u8)rtw_vrtl_carrier_sense ;
+	registry_par->vcs_type = (u8)rtw_vcs_type;
+	registry_par->rts_thresh = (u16)rtw_rts_thresh;
+	registry_par->frag_thresh = (u16)rtw_frag_thresh;
+	registry_par->preamble = (u8)rtw_preamble;
+	registry_par->scan_mode = (u8)rtw_scan_mode;
+	registry_par->smart_ps = (u8)rtw_smart_ps;
+	registry_par->check_fw_ps = (u8)rtw_check_fw_ps;
+	registry_par->power_mgnt = (u8)rtw_power_mgnt;
+	registry_par->ips_mode = (u8)rtw_ips_mode;
+	registry_par->lps_level = (u8)rtw_lps_level;
+	registry_par->lps_chk_by_tp = (u8)rtw_lps_chk_by_tp;
+	registry_par->radio_enable = (u8)rtw_radio_enable;
+	registry_par->long_retry_lmt = (u8)rtw_long_retry_lmt;
+	registry_par->short_retry_lmt = (u8)rtw_short_retry_lmt;
+	registry_par->busy_thresh = (u16)rtw_busy_thresh;
+	registry_par->max_bss_cnt = (u16)rtw_max_bss_cnt;
+	/* registry_par->qos_enable = (u8)rtw_qos_enable; */
+	registry_par->ack_policy = (u8)rtw_ack_policy;
+	registry_par->mp_mode = (u8)rtw_mp_mode;
+#if defined(CONFIG_MP_INCLUDED) && defined(CONFIG_RTW_CUSTOMER_STR)
+	registry_par->mp_customer_str = (u8)rtw_mp_customer_str;
+#endif
+	registry_par->software_encrypt = (u8)rtw_software_encrypt;
+	registry_par->software_decrypt = (u8)rtw_software_decrypt;
+
+	registry_par->acm_method = (u8)rtw_acm_method;
+	registry_par->usb_rxagg_mode = (u8)rtw_usb_rxagg_mode;
+	registry_par->dynamic_agg_enable = (u8)rtw_dynamic_agg_enable;
+
+	/* WMM */
+	registry_par->wmm_enable = (u8)rtw_wmm_enable;
+
+#ifdef CONFIG_WMMPS_STA
+	/* UAPSD */
+	registry_par->uapsd_max_sp_len= (u8)rtw_uapsd_max_sp;
+	registry_par->uapsd_ac_enable = (u8)rtw_uapsd_ac_enable;
+	registry_par->wmm_smart_ps = (u8)rtw_wmm_smart_ps;
+#endif /* CONFIG_WMMPS_STA */
+
+	registry_par->RegPwrTrimEnable = (u8)rtw_pwrtrim_enable;
+
+	registry_par->tx_bw_mode = (u8)rtw_tx_bw_mode;
+
+#ifdef CONFIG_80211N_HT
+	registry_par->ht_enable = (u8)rtw_ht_enable;
+	if (registry_par->ht_enable && is_supported_ht(registry_par->wireless_mode)) {
+		registry_par->bw_mode = (u8)rtw_bw_mode;
+		registry_par->ampdu_enable = (u8)rtw_ampdu_enable;
+		registry_par->rx_stbc = (u8)rtw_rx_stbc;
+		registry_par->rx_ampdu_amsdu = (u8)rtw_rx_ampdu_amsdu;
+		registry_par->tx_ampdu_amsdu = (u8)rtw_tx_ampdu_amsdu;
+		registry_par->short_gi = (u8)rtw_short_gi;
+		registry_par->ldpc_cap = (u8)rtw_ldpc_cap;
+#if defined(CONFIG_CUSTOMER01_SMART_ANTENNA)
+		rtw_stbc_cap = 0x0;
+#elif defined(CONFIG_RTW_TX_2PATH_EN)
+		rtw_stbc_cap &= ~(BIT1|BIT5);
+#endif
+		registry_par->stbc_cap = (u8)rtw_stbc_cap;
+#if defined(CONFIG_RTW_TX_2PATH_EN)
+		rtw_beamform_cap &= ~(BIT0|BIT2|BIT4);
+#endif
+		registry_par->beamform_cap = (u8)rtw_beamform_cap;
+		registry_par->beamformer_rf_num = (u8)rtw_bfer_rf_number;
+		registry_par->beamformee_rf_num = (u8)rtw_bfee_rf_number;
+		rtw_regsty_init_rx_ampdu_sz_limit(registry_par);
+	}
+#endif
+#ifdef DBG_LA_MODE
+	registry_par->la_mode_en = (u8)rtw_la_mode_en;
+#endif
+#ifdef CONFIG_80211AC_VHT
+	registry_par->vht_enable = (u8)rtw_vht_enable;
+	registry_par->ampdu_factor = (u8)rtw_ampdu_factor;
+	registry_par->vht_rx_mcs_map[0] = (u8)(rtw_vht_rx_mcs_map & 0xFF);
+	registry_par->vht_rx_mcs_map[1] = (u8)((rtw_vht_rx_mcs_map & 0xFF00) >> 8);
+#endif
+
+#ifdef CONFIG_TX_EARLY_MODE
+	registry_par->early_mode = (u8)rtw_early_mode;
+#endif
+	registry_par->lowrate_two_xmit = (u8)rtw_lowrate_two_xmit;
+	registry_par->rf_config = (u8)rtw_rf_config;
+	registry_par->low_power = (u8)rtw_low_power;
+
+	registry_par->check_hw_status = (u8)rtw_check_hw_status;
+
+	registry_par->wifi_spec = (u8)rtw_wifi_spec;
+
+	if (strlen(rtw_country_code) != 2
+		|| is_alpha(rtw_country_code[0]) == _FALSE
+		|| is_alpha(rtw_country_code[1]) == _FALSE
+	) {
+		if (rtw_country_code != rtw_country_unspecified)
+			RTW_ERR("%s discard rtw_country_code not in alpha2\n", __func__);
+		_rtw_memset(registry_par->alpha2, 0xFF, 2);
+	} else
+		_rtw_memcpy(registry_par->alpha2, rtw_country_code, 2);
+
+	registry_par->channel_plan = (u8)rtw_channel_plan;
+	rtw_regsty_load_excl_chs(registry_par);
+
+	registry_par->special_rf_path = (u8)rtw_special_rf_path;
+
+	registry_par->full_ch_in_p2p_handshake = (u8)rtw_full_ch_in_p2p_handshake;
+#ifdef CONFIG_BT_COEXIST
+	registry_par->btcoex = (u8)rtw_btcoex_enable;
+	registry_par->bt_iso = (u8)rtw_bt_iso;
+	registry_par->bt_sco = (u8)rtw_bt_sco;
+	registry_par->bt_ampdu = (u8)rtw_bt_ampdu;
+	registry_par->ant_num = (u8)rtw_ant_num;
+	registry_par->single_ant_path = (u8) rtw_single_ant_path;
+#endif
+
+	registry_par->bAcceptAddbaReq = (u8)rtw_AcceptAddbaReq;
+
+	registry_par->antdiv_cfg = (u8)rtw_antdiv_cfg;
+	registry_par->antdiv_type = (u8)rtw_antdiv_type;
+
+	registry_par->drv_ant_band_switch = (u8) rtw_drv_ant_band_switch;
+
+	registry_par->switch_usb_mode = (u8)rtw_switch_usb_mode;
+
+#ifdef CONFIG_AUTOSUSPEND
+	registry_par->usbss_enable = (u8)rtw_enusbss;/* 0:disable,1:enable */
+#endif
+#ifdef SUPPORT_HW_RFOFF_DETECTED
+	registry_par->hwpdn_mode = (u8)rtw_hwpdn_mode;/* 0:disable,1:enable,2:by EFUSE config */
+	registry_par->hwpwrp_detect = (u8)rtw_hwpwrp_detect;/* 0:disable,1:enable */
+#endif
+
+	registry_par->hw_wps_pbc = (u8)rtw_hw_wps_pbc;
+
+#ifdef CONFIG_ADAPTOR_INFO_CACHING_FILE
+	snprintf(registry_par->adaptor_info_caching_file_path, PATH_LENGTH_MAX, "%s", rtw_adaptor_info_caching_file_path);
+	registry_par->adaptor_info_caching_file_path[PATH_LENGTH_MAX - 1] = 0;
+#endif
+
+#ifdef CONFIG_LAYER2_ROAMING
+	registry_par->max_roaming_times = (u8)rtw_max_roaming_times;
+#ifdef CONFIG_INTEL_WIDI
+	registry_par->max_roaming_times = (u8)rtw_max_roaming_times + 2;
+#endif /* CONFIG_INTEL_WIDI */
+#endif
+
+#ifdef CONFIG_IOL
+	registry_par->fw_iol = rtw_fw_iol;
+#endif
+
+#ifdef CONFIG_80211D
+	registry_par->enable80211d = (u8)rtw_80211d;
+#endif
+
+	snprintf(registry_par->ifname, 16, "%s", ifname);
+	snprintf(registry_par->if2name, 16, "%s", if2name);
+
+	registry_par->notch_filter = (u8)rtw_notch_filter;
+
+#ifdef CONFIG_CONCURRENT_MODE
+	registry_par->virtual_iface_num = (u8)rtw_virtual_iface_num;
+#endif
+	registry_par->pll_ref_clk_sel = (u8)rtw_pll_ref_clk_sel;
+
+#ifdef CONFIG_TXPWR_LIMIT
+	registry_par->RegEnableTxPowerLimit = (u8)rtw_tx_pwr_lmt_enable;
+#endif
+	registry_par->RegEnableTxPowerByRate = (u8)rtw_tx_pwr_by_rate;
+
+	rtw_regsty_load_target_tx_power(registry_par);
+
+	registry_par->tsf_update_pause_factor = (u8)rtw_tsf_update_pause_factor;
+	registry_par->tsf_update_restore_factor = (u8)rtw_tsf_update_restore_factor;
+
+	registry_par->TxBBSwing_2G = (s8)rtw_TxBBSwing_2G;
+	registry_par->TxBBSwing_5G = (s8)rtw_TxBBSwing_5G;
+	registry_par->bEn_RFE = 1;
+	registry_par->RFE_Type = (u8)rtw_RFE_type;
+	registry_par->PowerTracking_Type = (u8)rtw_powertracking_type;
+	registry_par->AmplifierType_2G = (u8)rtw_amplifier_type_2g;
+	registry_par->AmplifierType_5G = (u8)rtw_amplifier_type_5g;
+	registry_par->GLNA_Type = (u8)rtw_GLNA_type;
+#ifdef CONFIG_LOAD_PHY_PARA_FROM_FILE
+	registry_par->load_phy_file = (u8)rtw_load_phy_file;
+	registry_par->RegDecryptCustomFile = (u8)rtw_decrypt_phy_file;
+#endif
+	registry_par->qos_opt_enable = (u8)rtw_qos_opt_enable;
+
+	registry_par->hiq_filter = (u8)rtw_hiq_filter;
+
+	registry_par->adaptivity_en = (u8)rtw_adaptivity_en;
+	registry_par->adaptivity_mode = (u8)rtw_adaptivity_mode;
+	registry_par->adaptivity_th_l2h_ini = (s8)rtw_adaptivity_th_l2h_ini;
+	registry_par->adaptivity_th_edcca_hl_diff = (s8)rtw_adaptivity_th_edcca_hl_diff;
+
+#ifdef CONFIG_DYNAMIC_SOML
+	registry_par->dyn_soml_en = (u8)rtw_dynamic_soml_en;
+	registry_par->dyn_soml_train_num = (u8)rtw_dynamic_soml_train_num;
+	registry_par->dyn_soml_interval = (u8)rtw_dynamic_soml_interval;
+	registry_par->dyn_soml_period = (u8)rtw_dynamic_soml_period;
+	registry_par->dyn_soml_delay = (u8)rtw_dynamic_soml_delay;
+#endif
+
+	registry_par->boffefusemask = (u8)rtw_OffEfuseMask;
+	registry_par->bFileMaskEfuse = (u8)rtw_FileMaskEfuse;
+
+#ifdef CONFIG_RTW_ACS
+	registry_par->acs_mode = (u8)rtw_acs;
+	registry_par->acs_auto_scan = (u8)rtw_acs_auto_scan;
+#endif
+#ifdef CONFIG_BACKGROUND_NOISE_MONITOR
+	registry_par->nm_mode = (u8)rtw_nm;
+#endif
+	registry_par->reg_rxgain_offset_2g = (u32) rtw_rxgain_offset_2g;
+	registry_par->reg_rxgain_offset_5gl = (u32) rtw_rxgain_offset_5gl;
+	registry_par->reg_rxgain_offset_5gm = (u32) rtw_rxgain_offset_5gm;
+	registry_par->reg_rxgain_offset_5gh = (u32) rtw_rxgain_offset_5gh;
+
+#ifdef CONFIG_DFS_MASTER
+	registry_par->dfs_region_domain = (u8)rtw_dfs_region_domain;
+#endif
+
+#ifdef CONFIG_MCC_MODE
+	registry_par->en_mcc = (u8)rtw_en_mcc;
+	registry_par->rtw_mcc_ap_bw20_target_tx_tp = (u32)rtw_mcc_ap_bw20_target_tx_tp;
+	registry_par->rtw_mcc_ap_bw40_target_tx_tp = (u32)rtw_mcc_ap_bw40_target_tx_tp;
+	registry_par->rtw_mcc_ap_bw80_target_tx_tp = (u32)rtw_mcc_ap_bw80_target_tx_tp;
+	registry_par->rtw_mcc_sta_bw20_target_tx_tp = (u32)rtw_mcc_sta_bw20_target_tx_tp;
+	registry_par->rtw_mcc_sta_bw40_target_tx_tp = (u32)rtw_mcc_sta_bw40_target_tx_tp;
+	registry_par->rtw_mcc_sta_bw80_target_tx_tp = (u32)rtw_mcc_sta_bw80_target_tx_tp;
+	registry_par->rtw_mcc_single_tx_cri = (u32)rtw_mcc_single_tx_cri;
+	registry_par->rtw_mcc_policy_table_idx = rtw_mcc_policy_table_idx;
+	registry_par->rtw_mcc_duration = (u8)rtw_mcc_duration;
+	registry_par->rtw_mcc_enable_runtime_duration = rtw_mcc_enable_runtime_duration;
+#endif /*CONFIG_MCC_MODE */
+
+#ifdef CONFIG_WOWLAN
+	registry_par->wakeup_event = rtw_wakeup_event;
+#endif
+
+#ifdef CONFIG_SUPPORT_TRX_SHARED
+	registry_par->trx_share_mode = rtw_trx_share_mode;
+#endif
+
+#ifdef CONFIG_PCI_HCI
+	registry_par->pci_aspm_config = rtw_pci_aspm_enable;
+#endif
+
+#ifdef CONFIG_RTW_NAPI
+	registry_par->en_napi = (u8)rtw_en_napi;
+#ifdef CONFIG_RTW_NAPI_DYNAMIC
+	registry_par->napi_threshold = (u32)rtw_napi_threshold;
+#endif /* CONFIG_RTW_NAPI_DYNAMIC */
+#ifdef CONFIG_RTW_GRO
+	registry_par->en_gro = (u8)rtw_en_gro;
+	if (!registry_par->en_napi && registry_par->en_gro) {
+		registry_par->en_gro = 0;
+		RTW_WARN("Disable GRO because NAPI is not enabled\n");
+	}
+#endif /* CONFIG_RTW_GRO */
+#endif /* CONFIG_RTW_NAPI */
+
+	registry_par->iqk_fw_offload = (u8)rtw_iqk_fw_offload;
+	registry_par->ch_switch_offload = (u8)rtw_ch_switch_offload;
+
+#ifdef CONFIG_TDLS
+	registry_par->en_tdls = rtw_en_tdls;
+#endif
+
+#ifdef CONFIG_ADVANCE_OTA
+	registry_par->adv_ota = rtw_advnace_ota;
+#endif
+#ifdef CONFIG_FW_OFFLOAD_PARAM_INIT
+	registry_par->fw_param_init = rtw_fw_param_init;
+#endif
+#ifdef CONFIG_AP_MODE
+	registry_par->bmc_tx_rate = rtw_bmc_tx_rate;
+#endif
+#ifdef CONFIG_FW_HANDLE_TXBCN
+	registry_par->fw_tbtt_rpt = rtw_tbtt_rpt;
+#endif
+
+	return status;
+}
+
+/**
+ * rtw_net_set_mac_address
+ * This callback function is used for the Media Access Control address
+ * of each net_device needs to be changed.
+ *
+ * Arguments:
+ * @pnetdev: net_device pointer.
+ * @addr: new MAC address.
+ *
+ * Return:
+ * ret = 0: Permit to change net_device's MAC address.
+ * ret = -1 (Default): Operation not permitted.
+ *
+ * Auther: Arvin Liu
+ * Date: 2015/05/29
+ */
+static int rtw_net_set_mac_address(struct net_device *pnetdev, void *addr)
+{
+	_adapter *padapter = (_adapter *)rtw_netdev_priv(pnetdev);
+	struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
+	struct sockaddr *sa = (struct sockaddr *)addr;
+	int ret = -1;
+
+	/* only the net_device is in down state to permit modifying mac addr */
+	if ((pnetdev->flags & IFF_UP) == _TRUE) {
+		RTW_INFO(FUNC_ADPT_FMT": The net_device's is not in down state\n"
+			 , FUNC_ADPT_ARG(padapter));
+
+		return ret;
+	}
+
+	/* if the net_device is linked, it's not permit to modify mac addr */
+	if (check_fwstate(pmlmepriv, _FW_UNDER_LINKING) ||
+	    check_fwstate(pmlmepriv, _FW_LINKED) ||
+	    check_fwstate(pmlmepriv, _FW_UNDER_SURVEY)) {
+		RTW_INFO(FUNC_ADPT_FMT": The net_device's is not idle currently\n"
+			 , FUNC_ADPT_ARG(padapter));
+
+		return ret;
+	}
+
+	/* check whether the input mac address is valid to permit modifying mac addr */
+	if (rtw_check_invalid_mac_address(sa->sa_data, _FALSE) == _TRUE) {
+		RTW_INFO(FUNC_ADPT_FMT": Invalid Mac Addr for "MAC_FMT"\n"
+			 , FUNC_ADPT_ARG(padapter), MAC_ARG(sa->sa_data));
+
+		return ret;
+	}
+
+	_rtw_memcpy(adapter_mac_addr(padapter), sa->sa_data, ETH_ALEN); /* set mac addr to adapter */
+	_rtw_memcpy(pnetdev->dev_addr, sa->sa_data, ETH_ALEN); /* set mac addr to net_device */
+
+#if 0
+	if (rtw_is_hw_init_completed(padapter)) {
+		rtw_ps_deny(padapter, PS_DENY_IOCTL);
+		LeaveAllPowerSaveModeDirect(padapter); /* leave PS mode for guaranteeing to access hw register successfully */
+
+#ifdef CONFIG_MI_WITH_MBSSID_CAM
+		rtw_hal_change_macaddr_mbid(padapter, sa->sa_data);
+#else
+		rtw_hal_set_hwreg(padapter, HW_VAR_MAC_ADDR, sa->sa_data); /* set mac addr to mac register */
+#endif
+
+		rtw_ps_deny_cancel(padapter, PS_DENY_IOCTL);
+	}
+#else
+	rtw_ps_deny(padapter, PS_DENY_IOCTL);
+	LeaveAllPowerSaveModeDirect(padapter); /* leave PS mode for guaranteeing to access hw register successfully */
+#ifdef CONFIG_MI_WITH_MBSSID_CAM
+	rtw_hal_change_macaddr_mbid(padapter, sa->sa_data);
+#else
+	rtw_hal_set_hwreg(padapter, HW_VAR_MAC_ADDR, sa->sa_data); /* set mac addr to mac register */
+#endif
+	rtw_ps_deny_cancel(padapter, PS_DENY_IOCTL);
+#endif
+
+	RTW_INFO(FUNC_ADPT_FMT": Set Mac Addr to "MAC_FMT" Successfully\n"
+		 , FUNC_ADPT_ARG(padapter), MAC_ARG(sa->sa_data));
+
+	ret = 0;
+
+	return ret;
+}
+
+static struct net_device_stats *rtw_net_get_stats(struct net_device *pnetdev)
+{
+	_adapter *padapter = (_adapter *)rtw_netdev_priv(pnetdev);
+	struct xmit_priv *pxmitpriv = &(padapter->xmitpriv);
+	struct recv_priv *precvpriv = &(padapter->recvpriv);
+
+	padapter->stats.tx_packets = pxmitpriv->tx_pkts;/* pxmitpriv->tx_pkts++; */
+	padapter->stats.rx_packets = precvpriv->rx_pkts;/* precvpriv->rx_pkts++; */
+	padapter->stats.tx_dropped = pxmitpriv->tx_drop;
+	padapter->stats.rx_dropped = precvpriv->rx_drop;
+	padapter->stats.tx_bytes = pxmitpriv->tx_bytes;
+	padapter->stats.rx_bytes = precvpriv->rx_bytes;
+
+	return &padapter->stats;
+}
+
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 35))
+/*
+ * AC to queue mapping
+ *
+ * AC_VO -> queue 0
+ * AC_VI -> queue 1
+ * AC_BE -> queue 2
+ * AC_BK -> queue 3
+ */
+static const u16 rtw_1d_to_queue[8] = { 2, 3, 3, 2, 1, 1, 0, 0 };
+
+/* Given a data frame determine the 802.1p/1d tag to use. */
+unsigned int rtw_classify8021d(struct sk_buff *skb)
+{
+	unsigned int dscp;
+
+	/* skb->priority values from 256->263 are magic values to
+	 * directly indicate a specific 802.1d priority.  This is used
+	 * to allow 802.1d priority to be passed directly in from VLAN
+	 * tags, etc.
+	 */
+	if (skb->priority >= 256 && skb->priority <= 263)
+		return skb->priority - 256;
+
+	switch (skb->protocol) {
+	case htons(ETH_P_IP):
+		dscp = ip_hdr(skb)->tos & 0xfc;
+		break;
+	default:
+		return 0;
+	}
+
+	return dscp >> 5;
+}
+
+
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4,19,0))
+static u16 rtw_select_queue(struct net_device *dev, struct sk_buff *skb
+    , struct net_device *sb_dev
+    #if (LINUX_VERSION_CODE < KERNEL_VERSION(5,2,0))
+    , select_queue_fallback_t fallback
+    #endif
+)
+#else
+static u16 rtw_select_queue(struct net_device *dev, struct sk_buff *skb
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(3, 13, 0)
+	, void *accel_priv
+	#if LINUX_VERSION_CODE >= KERNEL_VERSION(3, 14, 0)
+	, select_queue_fallback_t fallback
+	#endif
+#endif
+)
+#endif
+{
+	_adapter	*padapter = rtw_netdev_priv(dev);
+	struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
+
+	skb->priority = rtw_classify8021d(skb);
+
+	if (pmlmepriv->acm_mask != 0)
+		skb->priority = qos_acm(pmlmepriv->acm_mask, skb->priority);
+
+	return rtw_1d_to_queue[skb->priority];
+}
+
+u16 rtw_recv_select_queue(struct sk_buff *skb)
+{
+	struct iphdr *piphdr;
+	unsigned int dscp;
+	u16	eth_type;
+	u32 priority;
+	u8 *pdata = skb->data;
+
+	_rtw_memcpy(&eth_type, pdata + (ETH_ALEN << 1), 2);
+
+	switch (eth_type) {
+	case htons(ETH_P_IP):
+
+		piphdr = (struct iphdr *)(pdata + ETH_HLEN);
+
+		dscp = piphdr->tos & 0xfc;
+
+		priority = dscp >> 5;
+
+		break;
+	default:
+		priority = 0;
+	}
+
+	return rtw_1d_to_queue[priority];
+
+}
+
+#endif
+
+static u8 is_rtw_ndev(struct net_device *ndev)
+{
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 29))
+	return ndev->netdev_ops
+		&& ndev->netdev_ops->ndo_do_ioctl
+		&& ndev->netdev_ops->ndo_do_ioctl == rtw_ioctl;
+#else
+	return ndev->do_ioctl
+		&& ndev->do_ioctl == rtw_ioctl;
+#endif
+}
+
+static int rtw_ndev_notifier_call(struct notifier_block *nb, unsigned long state, void *ptr)
+{
+	struct net_device *ndev;
+
+	if (ptr == NULL)
+		return NOTIFY_DONE;
+
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 11, 0))
+	ndev = netdev_notifier_info_to_dev(ptr);
+#else
+	ndev = ptr;
+#endif
+
+	if (ndev == NULL)
+		return NOTIFY_DONE;
+
+	if (!is_rtw_ndev(ndev))
+		return NOTIFY_DONE;
+
+	RTW_INFO(FUNC_NDEV_FMT" state:%lu\n", FUNC_NDEV_ARG(ndev), state);
+
+	switch (state) {
+	case NETDEV_CHANGENAME:
+		rtw_adapter_proc_replace(ndev);
+		break;
+	#ifdef CONFIG_NEW_NETDEV_HDL
+	case NETDEV_PRE_UP :
+		{
+			_adapter *adapter = rtw_netdev_priv(ndev);
+
+			rtw_pwr_wakeup(adapter);
+		}
+		break;
+	#endif
+	}
+
+	return NOTIFY_DONE;
+}
+
+static struct notifier_block rtw_ndev_notifier = {
+	.notifier_call = rtw_ndev_notifier_call,
+};
+
+int rtw_ndev_notifier_register(void)
+{
+	return register_netdevice_notifier(&rtw_ndev_notifier);
+}
+
+void rtw_ndev_notifier_unregister(void)
+{
+	unregister_netdevice_notifier(&rtw_ndev_notifier);
+}
+
+int rtw_ndev_init(struct net_device *dev)
+{
+	_adapter *adapter = rtw_netdev_priv(dev);
+
+	RTW_PRINT(FUNC_ADPT_FMT" if%d mac_addr="MAC_FMT"\n"
+		, FUNC_ADPT_ARG(adapter), (adapter->iface_id + 1), MAC_ARG(dev->dev_addr));
+	strncpy(adapter->old_ifname, dev->name, IFNAMSIZ);
+	adapter->old_ifname[IFNAMSIZ - 1] = '\0';
+	rtw_adapter_proc_init(dev);
+
+	return 0;
+}
+
+void rtw_ndev_uninit(struct net_device *dev)
+{
+	_adapter *adapter = rtw_netdev_priv(dev);
+
+	RTW_PRINT(FUNC_ADPT_FMT" if%d\n"
+		  , FUNC_ADPT_ARG(adapter), (adapter->iface_id + 1));
+	rtw_adapter_proc_deinit(dev);
+}
+
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 29))
+static const struct net_device_ops rtw_netdev_ops = {
+	.ndo_init = rtw_ndev_init,
+	.ndo_uninit = rtw_ndev_uninit,
+	.ndo_open = netdev_open,
+	.ndo_stop = netdev_close,
+	.ndo_start_xmit = rtw_xmit_entry,
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 35))
+	.ndo_select_queue	= rtw_select_queue,
+#endif
+	.ndo_set_mac_address = rtw_net_set_mac_address,
+	.ndo_get_stats = rtw_net_get_stats,
+	.ndo_do_ioctl = rtw_ioctl,
+};
+#endif
+
+int rtw_init_netdev_name(struct net_device *pnetdev, const char *ifname)
+{
+#ifdef CONFIG_EASY_REPLACEMENT
+	_adapter *padapter = rtw_netdev_priv(pnetdev);
+	struct net_device	*TargetNetdev = NULL;
+	_adapter			*TargetAdapter = NULL;
+	struct net		*devnet = NULL;
+
+	if (padapter->bDongle == 1) {
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 24))
+		TargetNetdev = dev_get_by_name("wlan0");
+#else
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 26))
+		devnet = pnetdev->nd_net;
+#else
+		devnet = dev_net(pnetdev);
+#endif
+		TargetNetdev = dev_get_by_name(devnet, "wlan0");
+#endif
+		if (TargetNetdev) {
+			RTW_INFO("Force onboard module driver disappear !!!\n");
+			TargetAdapter = rtw_netdev_priv(TargetNetdev);
+			TargetAdapter->DriverState = DRIVER_DISAPPEAR;
+
+			padapter->pid[0] = TargetAdapter->pid[0];
+			padapter->pid[1] = TargetAdapter->pid[1];
+			padapter->pid[2] = TargetAdapter->pid[2];
+
+			dev_put(TargetNetdev);
+			unregister_netdev(TargetNetdev);
+
+			padapter->DriverState = DRIVER_REPLACE_DONGLE;
+		}
+	}
+#endif /* CONFIG_EASY_REPLACEMENT */
+
+	if (dev_alloc_name(pnetdev, ifname) < 0)
+		RTW_ERR("dev_alloc_name, fail!\n");
+
+	rtw_netif_carrier_off(pnetdev);
+	/* rtw_netif_stop_queue(pnetdev); */
+
+	return 0;
+}
+
+void rtw_hook_if_ops(struct net_device *ndev)
+{
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 29))
+	ndev->netdev_ops = &rtw_netdev_ops;
+#else
+	ndev->init = rtw_ndev_init;
+	ndev->uninit = rtw_ndev_uninit;
+	ndev->open = netdev_open;
+	ndev->stop = netdev_close;
+	ndev->hard_start_xmit = rtw_xmit_entry;
+	ndev->set_mac_address = rtw_net_set_mac_address;
+	ndev->get_stats = rtw_net_get_stats;
+	ndev->do_ioctl = rtw_ioctl;
+#endif
+}
+
+#ifdef CONFIG_CONCURRENT_MODE
+static void rtw_hook_vir_if_ops(struct net_device *ndev);
+#endif
+struct net_device *rtw_init_netdev(_adapter *old_padapter)
+{
+	_adapter *padapter;
+	struct net_device *pnetdev;
+
+	if (old_padapter != NULL) {
+		rtw_os_ndev_free(old_padapter);
+		pnetdev = rtw_alloc_etherdev_with_old_priv(sizeof(_adapter), (void *)old_padapter);
+	} else
+		pnetdev = rtw_alloc_etherdev(sizeof(_adapter));
+
+	if (!pnetdev)
+		return NULL;
+
+	padapter = rtw_netdev_priv(pnetdev);
+	padapter->pnetdev = pnetdev;
+
+#if LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 24)
+	SET_MODULE_OWNER(pnetdev);
+#endif
+
+	rtw_hook_if_ops(pnetdev);
+#ifdef CONFIG_CONCURRENT_MODE
+	if (!is_primary_adapter(padapter))
+		rtw_hook_vir_if_ops(pnetdev);
+#endif /* CONFIG_CONCURRENT_MODE */
+
+
+#ifdef CONFIG_TX_CSUM_OFFLOAD
+        pnetdev->features |= (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM);
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 39)
+        pnetdev->hw_features |= (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM);
+#endif
+#endif
+
+#ifdef CONFIG_RTW_NETIF_SG
+        pnetdev->features |= NETIF_F_SG;
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 39)
+        pnetdev->hw_features |= NETIF_F_SG;
+#endif
+#endif
+
+	if ((pnetdev->features & NETIF_F_SG) && (pnetdev->features & NETIF_F_IP_CSUM)) {
+		pnetdev->features |= (NETIF_F_TSO | NETIF_F_GSO);
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 39)
+		pnetdev->hw_features |= (NETIF_F_TSO | NETIF_F_GSO);
+#endif
+	}
+	/* pnetdev->tx_timeout = NULL; */
+	pnetdev->watchdog_timeo = HZ * 3; /* 3 second timeout */
+
+#ifdef CONFIG_WIRELESS_EXT
+	pnetdev->wireless_handlers = (struct iw_handler_def *)&rtw_handlers_def;
+#endif
+
+#ifdef WIRELESS_SPY
+	/* priv->wireless_data.spy_data = &priv->spy_data; */
+	/* pnetdev->wireless_data = &priv->wireless_data; */
+#endif
+
+	return pnetdev;
+}
+
+int rtw_os_ndev_alloc(_adapter *adapter)
+{
+	int ret = _FAIL;
+	struct net_device *ndev = NULL;
+
+	ndev = rtw_init_netdev(adapter);
+	if (ndev == NULL) {
+		rtw_warn_on(1);
+		goto exit;
+	}
+#if LINUX_VERSION_CODE > KERNEL_VERSION(2, 5, 0)
+	SET_NETDEV_DEV(ndev, dvobj_to_dev(adapter_to_dvobj(adapter)));
+#endif
+
+#ifdef CONFIG_PCI_HCI
+	if (adapter_to_dvobj(adapter)->bdma64)
+		ndev->features |= NETIF_F_HIGHDMA;
+	ndev->irq = adapter_to_dvobj(adapter)->irq;
+#endif
+
+#if defined(CONFIG_IOCTL_CFG80211)
+	if (rtw_cfg80211_ndev_res_alloc(adapter) != _SUCCESS) {
+		rtw_warn_on(1);
+		goto free_ndev;
+	}
+#endif
+
+	ret = _SUCCESS;
+
+free_ndev:
+	if (ret != _SUCCESS && ndev)
+		rtw_free_netdev(ndev);
+exit:
+	return ret;
+}
+
+void rtw_os_ndev_free(_adapter *adapter)
+{
+#if defined(CONFIG_IOCTL_CFG80211)
+	rtw_cfg80211_ndev_res_free(adapter);
+#endif
+
+	/* free the old_pnetdev */
+	if (adapter->rereg_nd_name_priv.old_pnetdev) {
+		rtw_free_netdev(adapter->rereg_nd_name_priv.old_pnetdev);
+		adapter->rereg_nd_name_priv.old_pnetdev = NULL;
+	}
+
+	if (adapter->pnetdev) {
+		rtw_free_netdev(adapter->pnetdev);
+		adapter->pnetdev = NULL;
+	}
+}
+
+int rtw_os_ndev_register(_adapter *adapter, const char *name)
+{
+	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
+	int ret = _SUCCESS;
+	struct net_device *ndev = adapter->pnetdev;
+	u8 rtnl_lock_needed = rtw_rtnl_lock_needed(dvobj);
+
+#ifdef CONFIG_RTW_NAPI
+	netif_napi_add(ndev, &adapter->napi, rtw_recv_napi_poll, RTL_NAPI_WEIGHT);
+#endif /* CONFIG_RTW_NAPI */
+
+#if defined(CONFIG_IOCTL_CFG80211)
+	if (rtw_cfg80211_ndev_res_register(adapter) != _SUCCESS) {
+		rtw_warn_on(1);
+		ret = _FAIL;
+		goto exit;
+	}
+#endif
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 19, 0)) && defined(CONFIG_PCI_HCI)
+	ndev->gro_flush_timeout = 100000;
+#endif
+	/* alloc netdev name */
+	rtw_init_netdev_name(ndev, name);
+
+	_rtw_memcpy(ndev->dev_addr, adapter_mac_addr(adapter), ETH_ALEN);
+
+	/* Tell the network stack we exist */
+
+	if (rtnl_lock_needed)
+		ret = (register_netdev(ndev) == 0) ? _SUCCESS : _FAIL;
+	else
+		ret = (register_netdevice(ndev) == 0) ? _SUCCESS : _FAIL;
+
+	if (ret == _SUCCESS)
+		adapter->registered = 1;
+	else
+		RTW_INFO(FUNC_NDEV_FMT" if%d Failed!\n", FUNC_NDEV_ARG(ndev), (adapter->iface_id + 1));
+
+#if defined(CONFIG_IOCTL_CFG80211)
+	if (ret != _SUCCESS) {
+		rtw_cfg80211_ndev_res_unregister(adapter);
+		#if !defined(RTW_SINGLE_WIPHY)
+		rtw_wiphy_unregister(adapter_to_wiphy(adapter));
+		#endif
+	}
+#endif
+
+exit:
+#ifdef CONFIG_RTW_NAPI
+	if (ret != _SUCCESS)
+		netif_napi_del(&adapter->napi);
+#endif /* CONFIG_RTW_NAPI */
+
+	return ret;
+}
+
+void rtw_os_ndev_unregister(_adapter *adapter)
+{
+	struct net_device *netdev = NULL;
+
+	if (adapter == NULL || adapter->registered == 0)
+		return;
+
+	adapter->ndev_unregistering = 1;
+
+	netdev = adapter->pnetdev;
+
+#if defined(CONFIG_IOCTL_CFG80211)
+	rtw_cfg80211_ndev_res_unregister(adapter);
+#endif
+
+	if ((adapter->DriverState != DRIVER_DISAPPEAR) && netdev) {
+		struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
+		u8 rtnl_lock_needed = rtw_rtnl_lock_needed(dvobj);
+
+		if (rtnl_lock_needed)
+			unregister_netdev(netdev);
+		else
+			unregister_netdevice(netdev);
+	}
+
+#if defined(CONFIG_IOCTL_CFG80211) && !defined(RTW_SINGLE_WIPHY)
+#ifdef CONFIG_RFKILL_POLL
+	rtw_cfg80211_deinit_rfkill(adapter_to_wiphy(adapter));
+#endif
+	rtw_wiphy_unregister(adapter_to_wiphy(adapter));
+#endif
+
+#ifdef CONFIG_RTW_NAPI
+	if (adapter->napi_state == NAPI_ENABLE) {
+		napi_disable(&adapter->napi);
+		adapter->napi_state = NAPI_DISABLE;
+	}
+	netif_napi_del(&adapter->napi);
+#endif /* CONFIG_RTW_NAPI */
+
+	adapter->registered = 0;
+	adapter->ndev_unregistering = 0;
+}
+
+/**
+ * rtw_os_ndev_init - Allocate and register OS layer net device and relating structures for @adapter
+ * @adapter: the adapter on which this function applies
+ * @name: the requesting net device name
+ *
+ * Returns:
+ * _SUCCESS or _FAIL
+ */
+int rtw_os_ndev_init(_adapter *adapter, const char *name)
+{
+	int ret = _FAIL;
+
+	if (rtw_os_ndev_alloc(adapter) != _SUCCESS)
+		goto exit;
+
+	if (rtw_os_ndev_register(adapter, name) != _SUCCESS)
+		goto os_ndev_free;
+
+	ret = _SUCCESS;
+
+os_ndev_free:
+	if (ret != _SUCCESS)
+		rtw_os_ndev_free(adapter);
+exit:
+	return ret;
+}
+
+/**
+ * rtw_os_ndev_deinit - Unregister and free OS layer net device and relating structures for @adapter
+ * @adapter: the adapter on which this function applies
+ */
+void rtw_os_ndev_deinit(_adapter *adapter)
+{
+	rtw_os_ndev_unregister(adapter);
+	rtw_os_ndev_free(adapter);
+}
+
+int rtw_os_ndevs_alloc(struct dvobj_priv *dvobj)
+{
+	int i, status = _SUCCESS;
+	_adapter *adapter;
+
+#if defined(CONFIG_IOCTL_CFG80211)
+	if (rtw_cfg80211_dev_res_alloc(dvobj) != _SUCCESS) {
+		rtw_warn_on(1);
+		status = _FAIL;
+		goto exit;
+	}
+#endif
+
+	for (i = 0; i < dvobj->iface_nums; i++) {
+
+		if (i >= CONFIG_IFACE_NUMBER) {
+			RTW_ERR("%s %d >= CONFIG_IFACE_NUMBER(%d)\n", __func__, i, CONFIG_IFACE_NUMBER);
+			rtw_warn_on(1);
+			continue;
+		}
+
+		adapter = dvobj->padapters[i];
+		if (adapter && !adapter->pnetdev) {
+
+			#ifdef CONFIG_RTW_DYNAMIC_NDEV
+			if (!is_primary_adapter(adapter))
+				continue;
+			#endif
+
+			status = rtw_os_ndev_alloc(adapter);
+			if (status != _SUCCESS) {
+				rtw_warn_on(1);
+				break;
+			}
+		}
+	}
+
+	if (status != _SUCCESS) {
+		for (; i >= 0; i--) {
+			adapter = dvobj->padapters[i];
+			if (adapter && adapter->pnetdev)
+				rtw_os_ndev_free(adapter);
+		}
+	}
+
+#if defined(CONFIG_IOCTL_CFG80211)
+	if (status != _SUCCESS)
+		rtw_cfg80211_dev_res_free(dvobj);
+#endif
+exit:
+	return status;
+}
+
+void rtw_os_ndevs_free(struct dvobj_priv *dvobj)
+{
+	int i;
+	_adapter *adapter = NULL;
+
+	for (i = 0; i < dvobj->iface_nums; i++) {
+
+		if (i >= CONFIG_IFACE_NUMBER) {
+			RTW_ERR("%s %d >= CONFIG_IFACE_NUMBER(%d)\n", __func__, i, CONFIG_IFACE_NUMBER);
+			rtw_warn_on(1);
+			continue;
+		}
+
+		adapter = dvobj->padapters[i];
+
+		if (adapter == NULL)
+			continue;
+
+		rtw_os_ndev_free(adapter);
+	}
+
+#if defined(CONFIG_IOCTL_CFG80211)
+	rtw_cfg80211_dev_res_free(dvobj);
+#endif
+}
+
+u32 rtw_start_drv_threads(_adapter *padapter)
+{
+	u32 _status = _SUCCESS;
+
+	RTW_INFO(FUNC_ADPT_FMT" enter\n", FUNC_ADPT_ARG(padapter));
+
+#ifdef CONFIG_XMIT_THREAD_MODE
+#if defined(CONFIG_SDIO_HCI)
+	if (is_primary_adapter(padapter))
+#endif
+	{
+		if (padapter->xmitThread == NULL) {
+			RTW_INFO(FUNC_ADPT_FMT " start RTW_XMIT_THREAD\n", FUNC_ADPT_ARG(padapter));
+			padapter->xmitThread = kthread_run(rtw_xmit_thread, padapter, "RTW_XMIT_THREAD");
+			if (IS_ERR(padapter->xmitThread)) {
+				padapter->xmitThread = NULL;
+				_status = _FAIL;
+			}
+		}
+	}
+#endif /* #ifdef CONFIG_XMIT_THREAD_MODE */
+
+#ifdef CONFIG_RECV_THREAD_MODE
+	if (is_primary_adapter(padapter)) {
+		if (padapter->recvThread == NULL) {
+			RTW_INFO(FUNC_ADPT_FMT " start RTW_RECV_THREAD\n", FUNC_ADPT_ARG(padapter));
+			padapter->recvThread = kthread_run(rtw_recv_thread, padapter, "RTW_RECV_THREAD");
+			if (IS_ERR(padapter->recvThread)) {
+				padapter->recvThread = NULL;
+				_status = _FAIL;
+			}
+		}
+	}
+#endif
+
+	if (is_primary_adapter(padapter)) {
+		if (padapter->cmdThread == NULL) {
+			RTW_INFO(FUNC_ADPT_FMT " start RTW_CMD_THREAD\n", FUNC_ADPT_ARG(padapter));
+			padapter->cmdThread = kthread_run(rtw_cmd_thread, padapter, "RTW_CMD_THREAD");
+			if (IS_ERR(padapter->cmdThread)) {
+				padapter->cmdThread = NULL;
+				_status = _FAIL;
+			}
+			else
+				_rtw_down_sema(&padapter->cmdpriv.start_cmdthread_sema); /* wait for cmd_thread to run */
+		}
+	}
+
+
+#ifdef CONFIG_EVENT_THREAD_MODE
+	if (padapter->evtThread == NULL) {
+		RTW_INFO(FUNC_ADPT_FMT " start RTW_EVENT_THREAD\n", FUNC_ADPT_ARG(padapter));
+		padapter->evtThread = kthread_run(event_thread, padapter, "RTW_EVENT_THREAD");
+		if (IS_ERR(padapter->evtThread)) {
+			padapter->evtThread = NULL;
+			_status = _FAIL;
+		}
+	}
+#endif
+
+	rtw_hal_start_thread(padapter);
+	return _status;
+
+}
+
+void rtw_stop_drv_threads(_adapter *padapter)
+{
+	RTW_INFO(FUNC_ADPT_FMT" enter\n", FUNC_ADPT_ARG(padapter));
+	if (is_primary_adapter(padapter))
+		rtw_stop_cmd_thread(padapter);
+
+#ifdef CONFIG_EVENT_THREAD_MODE
+	if (padapter->evtThread) {
+		_rtw_up_sema(&padapter->evtpriv.evt_notify);
+		rtw_thread_stop(padapter->evtThread);
+		padapter->evtThread = NULL;
+	}
+#endif
+
+#ifdef CONFIG_XMIT_THREAD_MODE
+	/* Below is to termindate tx_thread... */
+#if defined(CONFIG_SDIO_HCI)
+	/* Only wake-up primary adapter */
+	if (is_primary_adapter(padapter))
+#endif  /*SDIO_HCI */
+	{
+		if (padapter->xmitThread) {
+			_rtw_up_sema(&padapter->xmitpriv.xmit_sema);
+			rtw_thread_stop(padapter->xmitThread);
+			padapter->xmitThread = NULL;
+		}
+	}
+#endif
+
+#ifdef CONFIG_RECV_THREAD_MODE
+	if (is_primary_adapter(padapter) && padapter->recvThread) {
+		/* Below is to termindate rx_thread... */
+		_rtw_up_sema(&padapter->recvpriv.recv_sema);
+		rtw_thread_stop(padapter->recvThread);
+		padapter->recvThread = NULL;
+	}
+#endif
+
+	rtw_hal_stop_thread(padapter);
+}
+
+u8 rtw_init_default_value(_adapter *padapter)
+{
+	u8 ret  = _SUCCESS;
+	struct registry_priv *pregistrypriv = &padapter->registrypriv;
+	struct xmit_priv	*pxmitpriv = &padapter->xmitpriv;
+	struct security_priv *psecuritypriv = &padapter->securitypriv;
+
+	/* xmit_priv */
+	pxmitpriv->vcs_setting = pregistrypriv->vrtl_carrier_sense;
+	pxmitpriv->vcs = pregistrypriv->vcs_type;
+	pxmitpriv->vcs_type = pregistrypriv->vcs_type;
+	/* pxmitpriv->rts_thresh = pregistrypriv->rts_thresh; */
+	pxmitpriv->frag_len = pregistrypriv->frag_thresh;
+
+	/* security_priv */
+	/* rtw_get_encrypt_decrypt_from_registrypriv(padapter); */
+	psecuritypriv->binstallGrpkey = _FAIL;
+#ifdef CONFIG_GTK_OL
+	psecuritypriv->binstallKCK_KEK = _FAIL;
+#endif /* CONFIG_GTK_OL */
+	psecuritypriv->sw_encrypt = pregistrypriv->software_encrypt;
+	psecuritypriv->sw_decrypt = pregistrypriv->software_decrypt;
+
+	psecuritypriv->dot11AuthAlgrthm = dot11AuthAlgrthm_Open; /* open system */
+	psecuritypriv->dot11PrivacyAlgrthm = _NO_PRIVACY_;
+
+	psecuritypriv->dot11PrivacyKeyIndex = 0;
+
+	psecuritypriv->dot118021XGrpPrivacy = _NO_PRIVACY_;
+	psecuritypriv->dot118021XGrpKeyid = 1;
+
+	psecuritypriv->ndisauthtype = Ndis802_11AuthModeOpen;
+	psecuritypriv->ndisencryptstatus = Ndis802_11WEPDisabled;
+#ifdef CONFIG_CONCURRENT_MODE
+	psecuritypriv->dot118021x_bmc_cam_id = INVALID_SEC_MAC_CAM_ID;
+#endif
+
+
+	/* pwrctrl_priv */
+
+
+	/* registry_priv */
+	rtw_init_registrypriv_dev_network(padapter);
+	rtw_update_registrypriv_dev_network(padapter);
+
+
+	/* hal_priv */
+	rtw_hal_def_value_init(padapter);
+
+#ifdef CONFIG_MCC_MODE
+	/* MCC parameter */
+	rtw_hal_mcc_parameter_init(padapter);
+#endif /* CONFIG_MCC_MODE */
+
+	/* misc. */
+	RTW_ENABLE_FUNC(padapter, DF_RX_BIT);
+	RTW_ENABLE_FUNC(padapter, DF_TX_BIT);
+	padapter->bLinkInfoDump = 0;
+	padapter->bNotifyChannelChange = _FALSE;
+#ifdef CONFIG_P2P
+	padapter->bShowGetP2PState = 1;
+#endif
+
+	/* for debug purpose */
+	padapter->fix_rate = 0xFF;
+	padapter->data_fb = 0;
+	padapter->fix_bw = 0xFF;
+	padapter->power_offset = 0;
+	padapter->rsvd_page_offset = 0;
+	padapter->rsvd_page_num = 0;
+#ifdef CONFIG_AP_MODE
+	padapter->bmc_tx_rate = pregistrypriv->bmc_tx_rate;
+#endif
+	padapter->driver_tx_bw_mode = pregistrypriv->tx_bw_mode;
+
+	padapter->driver_ampdu_spacing = 0xFF;
+	padapter->driver_rx_ampdu_factor =  0xFF;
+	padapter->driver_rx_ampdu_spacing = 0xFF;
+	padapter->fix_rx_ampdu_accept = RX_AMPDU_ACCEPT_INVALID;
+	padapter->fix_rx_ampdu_size = RX_AMPDU_SIZE_INVALID;
+#ifdef CONFIG_TX_AMSDU
+	padapter->tx_amsdu = 2;
+	padapter->tx_amsdu_rate = 400;
+#endif
+	padapter->driver_tx_max_agg_num = 0xFF;
+#ifdef DBG_RX_COUNTER_DUMP
+	padapter->dump_rx_cnt_mode = 0;
+	padapter->drv_rx_cnt_ok = 0;
+	padapter->drv_rx_cnt_crcerror = 0;
+	padapter->drv_rx_cnt_drop = 0;
+#endif
+#ifdef CONFIG_RTW_NAPI
+	padapter->napi_state = NAPI_DISABLE;
+#endif
+
+#ifdef CONFIG_RTW_ACS
+	if (pregistrypriv->acs_mode)
+		rtw_acs_start(padapter);
+	else
+		rtw_acs_stop(padapter);
+#endif
+#ifdef CONFIG_BACKGROUND_NOISE_MONITOR
+	if (pregistrypriv->nm_mode)
+		rtw_nm_enable(padapter);
+	else
+		rtw_nm_disable(padapter);
+#endif
+	return ret;
+}
+#ifdef CONFIG_CLIENT_PORT_CFG
+extern void rtw_clt_port_init(struct clt_port_t  *cltp);
+extern void rtw_clt_port_deinit(struct clt_port_t  *cltp);
+#endif
+
+struct dvobj_priv *devobj_init(void)
+{
+	struct dvobj_priv *pdvobj = NULL;
+
+	pdvobj = (struct dvobj_priv *)rtw_zmalloc(sizeof(*pdvobj));
+	if (pdvobj == NULL)
+		return NULL;
+
+	_rtw_mutex_init(&pdvobj->hw_init_mutex);
+	_rtw_mutex_init(&pdvobj->h2c_fwcmd_mutex);
+	_rtw_mutex_init(&pdvobj->setch_mutex);
+	_rtw_mutex_init(&pdvobj->setbw_mutex);
+	_rtw_mutex_init(&pdvobj->rf_read_reg_mutex);
+#ifdef CONFIG_SDIO_INDIRECT_ACCESS
+	_rtw_mutex_init(&pdvobj->sd_indirect_access_mutex);
+#endif
+#ifdef CONFIG_SYSON_INDIRECT_ACCESS
+	_rtw_mutex_init(&pdvobj->syson_indirect_access_mutex);
+#endif
+#ifdef CONFIG_RTW_CUSTOMER_STR
+	_rtw_mutex_init(&pdvobj->customer_str_mutex);
+	_rtw_memset(pdvobj->customer_str, 0xFF, RTW_CUSTOMER_STR_LEN);
+#endif
+
+	pdvobj->processing_dev_remove = _FALSE;
+
+	ATOMIC_SET(&pdvobj->disable_func, 0);
+
+	rtw_macid_ctl_init(&pdvobj->macid_ctl);
+#ifdef CONFIG_CLIENT_PORT_CFG
+	rtw_clt_port_init(&pdvobj->clt_port);
+#endif
+	_rtw_spinlock_init(&pdvobj->cam_ctl.lock);
+	_rtw_mutex_init(&pdvobj->cam_ctl.sec_cam_access_mutex);
+#if defined(RTK_129X_PLATFORM) && defined(CONFIG_PCI_HCI)
+	_rtw_spinlock_init(&pdvobj->io_reg_lock);
+#endif
+#ifdef CONFIG_MBSSID_CAM
+	rtw_mbid_cam_init(pdvobj);
+#endif
+
+#ifdef CONFIG_AP_MODE
+	#ifdef CONFIG_SUPPORT_MULTI_BCN
+	pdvobj->nr_ap_if = 0;
+	pdvobj->inter_bcn_space = DEFAULT_BCN_INTERVAL; /* default value is equal to the default beacon_interval (100ms) */
+	_rtw_init_queue(&pdvobj->ap_if_q);
+	pdvobj->vap_map = 0;
+	#endif /*CONFIG_SUPPORT_MULTI_BCN*/
+	#ifdef CONFIG_SWTIMER_BASED_TXBCN
+	rtw_init_timer(&(pdvobj->txbcn_timer), NULL, tx_beacon_timer_handlder, pdvobj);
+	#endif
+#endif
+
+	rtw_init_timer(&(pdvobj->dynamic_chk_timer), NULL, rtw_dynamic_check_timer_handlder, pdvobj);
+	rtw_init_timer(&(pdvobj->periodic_tsf_update_end_timer), NULL, rtw_hal_periodic_tsf_update_end_timer_hdl, pdvobj);
+
+#ifdef CONFIG_MCC_MODE
+	_rtw_mutex_init(&(pdvobj->mcc_objpriv.mcc_mutex));
+	_rtw_mutex_init(&(pdvobj->mcc_objpriv.mcc_tsf_req_mutex));
+	_rtw_spinlock_init(&pdvobj->mcc_objpriv.mcc_lock);
+#endif /* CONFIG_MCC_MODE */
+
+#ifdef CONFIG_RTW_NAPI_DYNAMIC
+	pdvobj->en_napi_dynamic = 0;
+#endif /* CONFIG_RTW_NAPI_DYNAMIC */
+
+
+	return pdvobj;
+
+}
+
+void devobj_deinit(struct dvobj_priv *pdvobj)
+{
+	if (!pdvobj)
+		return;
+
+	/* TODO: use rtw_os_ndevs_deinit instead at the first stage of driver's dev deinit function */
+#if defined(CONFIG_IOCTL_CFG80211)
+	rtw_cfg80211_dev_res_free(pdvobj);
+#endif
+
+#ifdef CONFIG_MCC_MODE
+	_rtw_mutex_free(&(pdvobj->mcc_objpriv.mcc_mutex));
+	_rtw_mutex_free(&(pdvobj->mcc_objpriv.mcc_tsf_req_mutex));
+	_rtw_spinlock_free(&pdvobj->mcc_objpriv.mcc_lock);
+#endif /* CONFIG_MCC_MODE */
+
+	_rtw_mutex_free(&pdvobj->hw_init_mutex);
+	_rtw_mutex_free(&pdvobj->h2c_fwcmd_mutex);
+
+#ifdef CONFIG_RTW_CUSTOMER_STR
+	_rtw_mutex_free(&pdvobj->customer_str_mutex);
+#endif
+
+	_rtw_mutex_free(&pdvobj->setch_mutex);
+	_rtw_mutex_free(&pdvobj->setbw_mutex);
+	_rtw_mutex_free(&pdvobj->rf_read_reg_mutex);
+#ifdef CONFIG_SDIO_INDIRECT_ACCESS
+	_rtw_mutex_free(&pdvobj->sd_indirect_access_mutex);
+#endif
+#ifdef CONFIG_SYSON_INDIRECT_ACCESS
+	_rtw_mutex_free(&pdvobj->syson_indirect_access_mutex);
+#endif
+
+	rtw_macid_ctl_deinit(&pdvobj->macid_ctl);
+#ifdef CONFIG_CLIENT_PORT_CFG
+	rtw_clt_port_deinit(&pdvobj->clt_port);
+#endif
+
+	_rtw_spinlock_free(&pdvobj->cam_ctl.lock);
+	_rtw_mutex_free(&pdvobj->cam_ctl.sec_cam_access_mutex);
+
+#if defined(RTK_129X_PLATFORM) && defined(CONFIG_PCI_HCI)
+	_rtw_spinlock_free(&pdvobj->io_reg_lock);
+#endif
+#ifdef CONFIG_MBSSID_CAM
+	rtw_mbid_cam_deinit(pdvobj);
+#endif
+#ifdef CONFIG_SUPPORT_MULTI_BCN
+	_rtw_spinlock_free(&(pdvobj->ap_if_q.lock));
+#endif
+	rtw_mfree((u8 *)pdvobj, sizeof(*pdvobj));
+}
+
+inline u8 rtw_rtnl_lock_needed(struct dvobj_priv *dvobj)
+{
+	if (dvobj->rtnl_lock_holder && dvobj->rtnl_lock_holder == current)
+		return 0;
+	return 1;
+}
+
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 26))
+static inline int rtnl_is_locked(void)
+{
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 17))
+	if (unlikely(rtnl_trylock())) {
+		rtnl_unlock();
+#else
+	if (unlikely(down_trylock(&rtnl_sem) == 0)) {
+		up(&rtnl_sem);
+#endif
+		return 0;
+	}
+	return 1;
+}
+#endif
+
+inline void rtw_set_rtnl_lock_holder(struct dvobj_priv *dvobj, _thread_hdl_ thd_hdl)
+{
+	rtw_warn_on(!rtnl_is_locked());
+
+	if (!thd_hdl || rtnl_is_locked())
+		dvobj->rtnl_lock_holder = thd_hdl;
+
+	if (dvobj->rtnl_lock_holder && 0)
+		RTW_INFO("rtnl_lock_holder: %s:%d\n", current->comm, current->pid);
+}
+
+u8 rtw_reset_drv_sw(_adapter *padapter)
+{
+	u8	ret8 = _SUCCESS;
+	struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
+	struct pwrctrl_priv *pwrctrlpriv = adapter_to_pwrctl(padapter);
+
+	/* hal_priv */
+	rtw_hal_def_value_init(padapter);
+
+	RTW_ENABLE_FUNC(padapter, DF_RX_BIT);
+	RTW_ENABLE_FUNC(padapter, DF_TX_BIT);
+
+	padapter->bLinkInfoDump = 0;
+
+	padapter->xmitpriv.tx_pkts = 0;
+	padapter->recvpriv.rx_pkts = 0;
+
+	pmlmepriv->LinkDetectInfo.bBusyTraffic = _FALSE;
+
+	/* pmlmepriv->LinkDetectInfo.TrafficBusyState = _FALSE; */
+	pmlmepriv->LinkDetectInfo.TrafficTransitionCount = 0;
+	pmlmepriv->LinkDetectInfo.LowPowerTransitionCount = 0;
+
+	_clr_fwstate_(pmlmepriv, _FW_UNDER_SURVEY | _FW_UNDER_LINKING);
+
+#ifdef CONFIG_AUTOSUSPEND
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 22) && LINUX_VERSION_CODE <= KERNEL_VERSION(2, 6, 34))
+	adapter_to_dvobj(padapter)->pusbdev->autosuspend_disabled = 1;/* autosuspend disabled by the user */
+#endif
+#endif
+
+#ifdef DBG_CONFIG_ERROR_DETECT
+	if (is_primary_adapter(padapter))
+		rtw_hal_sreset_reset_value(padapter);
+#endif
+	pwrctrlpriv->pwr_state_check_cnts = 0;
+
+	/* mlmeextpriv */
+	mlmeext_set_scan_state(&padapter->mlmeextpriv, SCAN_DISABLE);
+
+#ifdef CONFIG_NEW_SIGNAL_STAT_PROCESS
+	rtw_set_signal_stat_timer(&padapter->recvpriv);
+#endif
+
+	return ret8;
+}
+
+
+u8 rtw_init_drv_sw(_adapter *padapter)
+{
+	u8	ret8 = _SUCCESS;
+
+#ifdef CONFIG_RTW_CFGVENDOR_RANDOM_MAC_OUI
+	struct rtw_wdev_priv *pwdev_priv = adapter_wdev_data(padapter);
+#endif
+
+	#if defined(CONFIG_AP_MODE) && defined(CONFIG_SUPPORT_MULTI_BCN)
+	_rtw_init_listhead(&padapter->list);
+	#ifdef CONFIG_FW_HANDLE_TXBCN
+	padapter->vap_id = CONFIG_LIMITED_AP_NUM;
+	if (is_primary_adapter(padapter))
+		adapter_to_dvobj(padapter)->vap_tbtt_rpt_map = adapter_to_regsty(padapter)->fw_tbtt_rpt;
+	#endif
+	#endif
+
+	#ifdef CONFIG_CLIENT_PORT_CFG
+	padapter->client_id = MAX_CLIENT_PORT_NUM;
+	padapter->client_port = CLT_PORT_INVALID;
+	#endif
+
+	ret8 = rtw_init_default_value(padapter);
+
+	if ((rtw_init_cmd_priv(&padapter->cmdpriv)) == _FAIL) {
+		ret8 = _FAIL;
+		goto exit;
+	}
+
+	padapter->cmdpriv.padapter = padapter;
+
+	if ((rtw_init_evt_priv(&padapter->evtpriv)) == _FAIL) {
+		ret8 = _FAIL;
+		goto exit;
+	}
+
+	if (is_primary_adapter(padapter))
+		rtw_rfctl_init(padapter);
+
+	if (rtw_init_mlme_priv(padapter) == _FAIL) {
+		ret8 = _FAIL;
+		goto exit;
+	}
+
+#ifdef CONFIG_P2P
+	rtw_init_wifidirect_timers(padapter);
+	init_wifidirect_info(padapter, P2P_ROLE_DISABLE);
+	reset_global_wifidirect_info(padapter);
+	#ifdef CONFIG_IOCTL_CFG80211
+	rtw_init_cfg80211_wifidirect_info(padapter);
+	#endif
+#ifdef CONFIG_WFD
+	if (rtw_init_wifi_display_info(padapter) == _FAIL)
+		RTW_ERR("Can't init init_wifi_display_info\n");
+#endif
+#endif /* CONFIG_P2P */
+
+	if (init_mlme_ext_priv(padapter) == _FAIL) {
+		ret8 = _FAIL;
+		goto exit;
+	}
+
+#ifdef CONFIG_TDLS
+	if (rtw_init_tdls_info(padapter) == _FAIL) {
+		RTW_INFO("Can't rtw_init_tdls_info\n");
+		ret8 = _FAIL;
+		goto exit;
+	}
+#endif /* CONFIG_TDLS */
+
+#ifdef CONFIG_RTW_MESH
+	rtw_mesh_cfg_init(padapter);
+#endif
+
+	if (_rtw_init_xmit_priv(&padapter->xmitpriv, padapter) == _FAIL) {
+		RTW_INFO("Can't _rtw_init_xmit_priv\n");
+		ret8 = _FAIL;
+		goto exit;
+	}
+
+	if (_rtw_init_recv_priv(&padapter->recvpriv, padapter) == _FAIL) {
+		RTW_INFO("Can't _rtw_init_recv_priv\n");
+		ret8 = _FAIL;
+		goto exit;
+	}
+	/* add for CONFIG_IEEE80211W, none 11w also can use */
+	_rtw_spinlock_init(&padapter->security_key_mutex);
+
+	/* We don't need to memset padapter->XXX to zero, because adapter is allocated by rtw_zvmalloc(). */
+	/* _rtw_memset((unsigned char *)&padapter->securitypriv, 0, sizeof (struct security_priv)); */
+
+	if (_rtw_init_sta_priv(&padapter->stapriv) == _FAIL) {
+		RTW_INFO("Can't _rtw_init_sta_priv\n");
+		ret8 = _FAIL;
+		goto exit;
+	}
+
+	padapter->setband = WIFI_FREQUENCY_BAND_AUTO;
+	padapter->fix_rate = 0xFF;
+	padapter->power_offset = 0;
+	padapter->rsvd_page_offset = 0;
+	padapter->rsvd_page_num = 0;
+
+	padapter->data_fb = 0;
+	padapter->fix_rx_ampdu_accept = RX_AMPDU_ACCEPT_INVALID;
+	padapter->fix_rx_ampdu_size = RX_AMPDU_SIZE_INVALID;
+#ifdef DBG_RX_COUNTER_DUMP
+	padapter->dump_rx_cnt_mode = 0;
+	padapter->drv_rx_cnt_ok = 0;
+	padapter->drv_rx_cnt_crcerror = 0;
+	padapter->drv_rx_cnt_drop = 0;
+#endif
+	rtw_init_bcmc_stainfo(padapter);
+
+	rtw_init_pwrctrl_priv(padapter);
+
+	/* _rtw_memset((u8 *)&padapter->qospriv, 0, sizeof (struct qos_priv)); */ /* move to mlme_priv */
+
+#ifdef CONFIG_MP_INCLUDED
+	if (init_mp_priv(padapter) == _FAIL)
+		RTW_INFO("%s: initialize MP private data Fail!\n", __func__);
+#endif
+
+	rtw_hal_dm_init(padapter);
+#ifdef CONFIG_RTW_SW_LED
+	rtw_hal_sw_led_init(padapter);
+#endif
+#ifdef DBG_CONFIG_ERROR_DETECT
+	rtw_hal_sreset_init(padapter);
+#endif
+
+#ifdef CONFIG_INTEL_WIDI
+	if (rtw_init_intel_widi(padapter) == _FAIL) {
+		RTW_INFO("Can't rtw_init_intel_widi\n");
+		ret8 = _FAIL;
+		goto exit;
+	}
+#endif /* CONFIG_INTEL_WIDI */
+
+#ifdef CONFIG_WAPI_SUPPORT
+	padapter->WapiSupport = true; /* set true temp, will revise according to Efuse or Registry value later. */
+	rtw_wapi_init(padapter);
+#endif
+
+#ifdef CONFIG_BR_EXT
+	_rtw_spinlock_init(&padapter->br_ext_lock);
+#endif /* CONFIG_BR_EXT */
+
+#ifdef CONFIG_BEAMFORMING
+#ifdef RTW_BEAMFORMING_VERSION_2
+	rtw_bf_init(padapter);
+#endif /* RTW_BEAMFORMING_VERSION_2 */
+#endif /* CONFIG_BEAMFORMING */
+
+#ifdef CONFIG_RTW_REPEATER_SON
+	init_rtw_rson_data(adapter_to_dvobj(padapter));
+#endif
+
+#ifdef CONFIG_RTW_80211K
+	rtw_init_rm(padapter);
+#endif
+
+#ifdef CONFIG_RTW_CFGVENDOR_RANDOM_MAC_OUI
+	memset(pwdev_priv->pno_mac_addr, 0xFF, ETH_ALEN);
+#endif
+
+exit:
+
+
+
+	return ret8;
+
+}
+
+#ifdef CONFIG_WOWLAN
+void rtw_cancel_dynamic_chk_timer(_adapter *padapter)
+{
+	_cancel_timer_ex(&adapter_to_dvobj(padapter)->dynamic_chk_timer);
+}
+#endif
+
+void rtw_cancel_all_timer(_adapter *padapter)
+{
+
+	_cancel_timer_ex(&padapter->mlmepriv.assoc_timer);
+
+	_cancel_timer_ex(&padapter->mlmepriv.scan_to_timer);
+
+#ifdef CONFIG_DFS_MASTER
+	_cancel_timer_ex(&adapter_to_rfctl(padapter)->radar_detect_timer);
+#endif
+
+	_cancel_timer_ex(&adapter_to_dvobj(padapter)->dynamic_chk_timer);
+	_cancel_timer_ex(&adapter_to_dvobj(padapter)->periodic_tsf_update_end_timer);
+#ifdef CONFIG_RTW_SW_LED
+	/* cancel sw led timer */
+	rtw_hal_sw_led_deinit(padapter);
+#endif
+	_cancel_timer_ex(&(adapter_to_pwrctl(padapter)->pwr_state_check_timer));
+
+#ifdef CONFIG_TX_AMSDU
+	_cancel_timer_ex(&padapter->xmitpriv.amsdu_bk_timer);
+	_cancel_timer_ex(&padapter->xmitpriv.amsdu_be_timer);
+	_cancel_timer_ex(&padapter->xmitpriv.amsdu_vo_timer);
+	_cancel_timer_ex(&padapter->xmitpriv.amsdu_vi_timer);
+#endif
+
+#ifdef CONFIG_IOCTL_CFG80211
+#ifdef CONFIG_P2P
+	_cancel_timer_ex(&padapter->cfg80211_wdinfo.remain_on_ch_timer);
+#endif /* CONFIG_P2P */
+#endif /* CONFIG_IOCTL_CFG80211 */
+
+#ifdef CONFIG_SET_SCAN_DENY_TIMER
+	_cancel_timer_ex(&padapter->mlmepriv.set_scan_deny_timer);
+	rtw_clear_scan_deny(padapter);
+#endif
+
+#ifdef CONFIG_NEW_SIGNAL_STAT_PROCESS
+	_cancel_timer_ex(&padapter->recvpriv.signal_stat_timer);
+#endif
+
+#ifdef CONFIG_LPS_RPWM_TIMER
+	_cancel_timer_ex(&(adapter_to_pwrctl(padapter)->pwr_rpwm_timer));
+#endif /* CONFIG_LPS_RPWM_TIMER */
+
+	/* cancel dm timer */
+	rtw_hal_dm_deinit(padapter);
+
+#ifdef CONFIG_PLATFORM_FS_MX61
+	msleep(50);
+#endif
+}
+
+u8 rtw_free_drv_sw(_adapter *padapter)
+{
+
+#ifdef CONFIG_WAPI_SUPPORT
+	rtw_wapi_free(padapter);
+#endif
+
+	/* we can call rtw_p2p_enable here, but: */
+	/* 1. rtw_p2p_enable may have IO operation */
+	/* 2. rtw_p2p_enable is bundled with wext interface */
+	#ifdef CONFIG_P2P
+	{
+		struct wifidirect_info *pwdinfo = &padapter->wdinfo;
+		if (!rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE)) {
+			_cancel_timer_ex(&pwdinfo->find_phase_timer);
+			_cancel_timer_ex(&pwdinfo->restore_p2p_state_timer);
+			_cancel_timer_ex(&pwdinfo->pre_tx_scan_timer);
+			#ifdef CONFIG_CONCURRENT_MODE
+			_cancel_timer_ex(&pwdinfo->ap_p2p_switch_timer);
+			#endif /* CONFIG_CONCURRENT_MODE */
+			rtw_p2p_set_state(pwdinfo, P2P_STATE_NONE);
+		}
+	}
+	#endif
+	/* add for CONFIG_IEEE80211W, none 11w also can use */
+	_rtw_spinlock_free(&padapter->security_key_mutex);
+
+#ifdef CONFIG_BR_EXT
+	_rtw_spinlock_free(&padapter->br_ext_lock);
+#endif /* CONFIG_BR_EXT */
+
+#ifdef CONFIG_INTEL_WIDI
+	rtw_free_intel_widi(padapter);
+#endif /* CONFIG_INTEL_WIDI */
+
+	free_mlme_ext_priv(&padapter->mlmeextpriv);
+
+#ifdef CONFIG_TDLS
+	/* rtw_free_tdls_info(&padapter->tdlsinfo); */
+#endif /* CONFIG_TDLS */
+
+#ifdef CONFIG_RTW_80211K
+	rtw_free_rm_priv(padapter);
+#endif
+
+	rtw_free_cmd_priv(&padapter->cmdpriv);
+
+	rtw_free_evt_priv(&padapter->evtpriv);
+
+	rtw_free_mlme_priv(&padapter->mlmepriv);
+
+	if (is_primary_adapter(padapter))
+		rtw_rfctl_deinit(padapter);
+
+	/* free_io_queue(padapter); */
+
+	_rtw_free_xmit_priv(&padapter->xmitpriv);
+
+	_rtw_free_sta_priv(&padapter->stapriv); /* will free bcmc_stainfo here */
+
+	_rtw_free_recv_priv(&padapter->recvpriv);
+
+	rtw_free_pwrctrl_priv(padapter);
+
+	/* rtw_mfree((void *)padapter, sizeof (padapter)); */
+
+	rtw_hal_free_data(padapter);
+
+	return _SUCCESS;
+
+}
+void rtw_intf_start(_adapter *adapter)
+{
+	if (adapter->intf_start)
+		adapter->intf_start(adapter);
+}
+void rtw_intf_stop(_adapter *adapter)
+{
+	if (adapter->intf_stop)
+		adapter->intf_stop(adapter);
+}
+
+#ifdef CONFIG_CONCURRENT_MODE
+#ifndef CONFIG_NEW_NETDEV_HDL
+int _netdev_vir_if_open(struct net_device *pnetdev)
+{
+	_adapter *padapter = (_adapter *)rtw_netdev_priv(pnetdev);
+	_adapter *primary_padapter = GET_PRIMARY_ADAPTER(padapter);
+
+	RTW_INFO(FUNC_NDEV_FMT" , bup=%d\n", FUNC_NDEV_ARG(pnetdev), padapter->bup);
+
+	if (!primary_padapter)
+		goto _netdev_virtual_iface_open_error;
+
+#ifdef CONFIG_PLATFORM_INTEL_BYT
+	if (padapter->bup == _FALSE) {
+		u8 mac[ETH_ALEN];
+
+		/* get mac address from primary_padapter */
+		if (primary_padapter->bup == _FALSE)
+			rtw_macaddr_cfg(adapter_mac_addr(primary_padapter), get_hal_mac_addr(primary_padapter));
+
+		_rtw_memcpy(mac, adapter_mac_addr(primary_padapter), ETH_ALEN);
+
+		/*
+		* If the BIT1 is 0, the address is universally administered.
+		* If it is 1, the address is locally administered
+		*/
+		mac[0] |= BIT(1);
+
+		_rtw_memcpy(adapter_mac_addr(padapter), mac, ETH_ALEN);
+
+#ifdef CONFIG_MI_WITH_MBSSID_CAM
+		rtw_mbid_camid_alloc(padapter, adapter_mac_addr(padapter));
+#endif
+		rtw_init_wifidirect_addrs(padapter, adapter_mac_addr(padapter), adapter_mac_addr(padapter));
+		_rtw_memcpy(pnetdev->dev_addr, adapter_mac_addr(padapter), ETH_ALEN);
+	}
+#endif /*CONFIG_PLATFORM_INTEL_BYT*/
+
+	if (primary_padapter->bup == _FALSE || !rtw_is_hw_init_completed(primary_padapter))
+		_netdev_open(primary_padapter->pnetdev);
+
+	if (padapter->bup == _FALSE && primary_padapter->bup == _TRUE &&
+	    rtw_is_hw_init_completed(primary_padapter)) {
+#if 0 /*#ifdef CONFIG_MI_WITH_MBSSID_CAM*/
+		rtw_hal_set_hwreg(padapter, HW_VAR_MAC_ADDR, adapter_mac_addr(padapter)); /* set mac addr to mac register */
+#endif
+
+	}
+
+	if (padapter->bup == _FALSE) {
+		if (rtw_start_drv_threads(padapter) == _FAIL)
+			goto _netdev_virtual_iface_open_error;
+	}
+
+#ifdef CONFIG_RTW_NAPI
+	if (padapter->napi_state == NAPI_DISABLE) {
+		napi_enable(&padapter->napi);
+		padapter->napi_state = NAPI_ENABLE;
+	}
+#endif
+
+#ifdef CONFIG_IOCTL_CFG80211
+	rtw_cfg80211_init_wiphy(padapter);
+	rtw_cfg80211_init_wdev_data(padapter);
+#endif
+
+	padapter->bup = _TRUE;
+
+	padapter->net_closed = _FALSE;
+
+	rtw_netif_wake_queue(pnetdev);
+
+	RTW_INFO(FUNC_NDEV_FMT" (bup=%d) exit\n", FUNC_NDEV_ARG(pnetdev), padapter->bup);
+
+	return 0;
+
+_netdev_virtual_iface_open_error:
+
+	padapter->bup = _FALSE;
+
+#ifdef CONFIG_RTW_NAPI
+	if(padapter->napi_state == NAPI_ENABLE) {
+		napi_disable(&padapter->napi);
+		padapter->napi_state = NAPI_DISABLE;
+	}
+#endif
+
+	rtw_netif_carrier_off(pnetdev);
+	rtw_netif_stop_queue(pnetdev);
+
+	return -1;
+
+}
+
+int netdev_vir_if_open(struct net_device *pnetdev)
+{
+	int ret;
+	_adapter *padapter = (_adapter *)rtw_netdev_priv(pnetdev);
+
+	_enter_critical_mutex(&(adapter_to_dvobj(padapter)->hw_init_mutex), NULL);
+	ret = _netdev_vir_if_open(pnetdev);
+	_exit_critical_mutex(&(adapter_to_dvobj(padapter)->hw_init_mutex), NULL);
+
+#ifdef CONFIG_AUTO_AP_MODE
+	/* if(padapter->iface_id == 2) */
+	/*	rtw_start_auto_ap(padapter); */
+#endif
+
+	return ret;
+}
+
+static int netdev_vir_if_close(struct net_device *pnetdev)
+{
+	_adapter *padapter = (_adapter *)rtw_netdev_priv(pnetdev);
+	struct mlme_priv	*pmlmepriv = &padapter->mlmepriv;
+
+	RTW_INFO(FUNC_NDEV_FMT" , bup=%d\n", FUNC_NDEV_ARG(pnetdev), padapter->bup);
+	padapter->net_closed = _TRUE;
+	pmlmepriv->LinkDetectInfo.bBusyTraffic = _FALSE;
+
+	if (pnetdev)
+		rtw_netif_stop_queue(pnetdev);
+
+#ifdef CONFIG_P2P
+	if (!rtw_p2p_chk_role(&padapter->wdinfo, P2P_ROLE_DISABLE))
+		rtw_p2p_enable(padapter, P2P_ROLE_DISABLE);
+#endif
+
+#ifdef CONFIG_IOCTL_CFG80211
+	rtw_scan_abort(padapter);
+	rtw_cfg80211_wait_scan_req_empty(padapter, 200);
+	adapter_wdev_data(padapter)->bandroid_scan = _FALSE;
+#endif
+
+	return 0;
+}
+#endif /*#ifndef CONFIG_NEW_NETDEV_HDL*/
+
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 29))
+static const struct net_device_ops rtw_netdev_vir_if_ops = {
+	.ndo_init = rtw_ndev_init,
+	.ndo_uninit = rtw_ndev_uninit,
+	#ifdef CONFIG_NEW_NETDEV_HDL
+	.ndo_open = netdev_open,
+	.ndo_stop = netdev_close,
+	#else
+	.ndo_open = netdev_vir_if_open,
+	.ndo_stop = netdev_vir_if_close,
+	#endif
+	.ndo_start_xmit = rtw_xmit_entry,
+	.ndo_set_mac_address = rtw_net_set_mac_address,
+	.ndo_get_stats = rtw_net_get_stats,
+	.ndo_do_ioctl = rtw_ioctl,
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 35))
+	.ndo_select_queue	= rtw_select_queue,
+#endif
+};
+#endif
+
+static void rtw_hook_vir_if_ops(struct net_device *ndev)
+{
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 29))
+	ndev->netdev_ops = &rtw_netdev_vir_if_ops;
+#else
+	ndev->init = rtw_ndev_init;
+	ndev->uninit = rtw_ndev_uninit;
+	#ifdef CONFIG_NEW_NETDEV_HDL
+	ndev->open = netdev_open;
+	ndev->stop = netdev_close;
+	#else
+	ndev->open = netdev_vir_if_open;
+	ndev->stop = netdev_vir_if_close;
+	#endif
+
+	ndev->set_mac_address = rtw_net_set_mac_address;
+#endif
+}
+_adapter *rtw_drv_add_vir_if(_adapter *primary_padapter,
+	void (*set_intf_ops)(_adapter *primary_padapter, struct _io_ops *pops))
+{
+	int res = _FAIL;
+	_adapter *padapter = NULL;
+	struct dvobj_priv *pdvobjpriv;
+	u8 mac[ETH_ALEN];
+
+	/****** init adapter ******/
+	padapter = (_adapter *)rtw_zvmalloc(sizeof(*padapter));
+	if (padapter == NULL)
+		goto exit;
+
+	if (loadparam(padapter) != _SUCCESS)
+		goto free_adapter;
+
+	_rtw_memcpy(padapter, primary_padapter, sizeof(_adapter));
+
+	/*  */
+	padapter->bup = _FALSE;
+	padapter->net_closed = _TRUE;
+	padapter->dir_dev = NULL;
+	padapter->dir_odm = NULL;
+
+	/*set adapter_type/iface type*/
+	padapter->isprimary = _FALSE;
+	padapter->adapter_type = VIRTUAL_ADAPTER;
+
+#ifdef CONFIG_MI_WITH_MBSSID_CAM
+	padapter->hw_port = HW_PORT0;
+#else
+	padapter->hw_port = HW_PORT1;
+#endif
+
+
+	/****** hook vir if into dvobj ******/
+	pdvobjpriv = adapter_to_dvobj(padapter);
+	padapter->iface_id = pdvobjpriv->iface_nums;
+	pdvobjpriv->padapters[pdvobjpriv->iface_nums++] = padapter;
+
+	padapter->intf_start = primary_padapter->intf_start;
+	padapter->intf_stop = primary_padapter->intf_stop;
+
+	/* step init_io_priv */
+	if ((rtw_init_io_priv(padapter, set_intf_ops)) == _FAIL) {
+		goto free_adapter;
+	}
+
+	/*init drv data*/
+	if (rtw_init_drv_sw(padapter) != _SUCCESS)
+		goto free_drv_sw;
+
+
+	/*get mac address from primary_padapter*/
+	_rtw_memcpy(mac, adapter_mac_addr(primary_padapter), ETH_ALEN);
+
+	/*
+	* If the BIT1 is 0, the address is universally administered.
+	* If it is 1, the address is locally administered
+	*/
+	mac[0] |= BIT(1);
+	if (padapter->iface_id > IFACE_ID1)
+		mac[4] ^= BIT(padapter->iface_id);
+
+	_rtw_memcpy(adapter_mac_addr(padapter), mac, ETH_ALEN);
+	/* update mac-address to mbsid-cam cache*/
+#ifdef CONFIG_MI_WITH_MBSSID_CAM
+	rtw_mbid_camid_alloc(padapter, adapter_mac_addr(padapter));
+#endif
+	RTW_INFO("%s if%d mac_addr : "MAC_FMT"\n", __func__, padapter->iface_id + 1, MAC_ARG(adapter_mac_addr(padapter)));
+#ifdef CONFIG_P2P
+	rtw_init_wifidirect_addrs(padapter, adapter_mac_addr(padapter), adapter_mac_addr(padapter));
+#endif
+
+	rtw_led_set_ctl_en_mask_virtual(padapter);
+	rtw_led_set_iface_en(padapter, 1);
+
+	res = _SUCCESS;
+
+free_drv_sw:
+	if (res != _SUCCESS && padapter)
+		rtw_free_drv_sw(padapter);
+free_adapter:
+	if (res != _SUCCESS && padapter) {
+		rtw_vmfree((u8 *)padapter, sizeof(*padapter));
+		padapter = NULL;
+	}
+exit:
+	return padapter;
+}
+
+void rtw_drv_stop_vir_if(_adapter *padapter)
+{
+	struct net_device *pnetdev = NULL;
+	struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
+
+	if (padapter == NULL)
+		return;
+	RTW_INFO(FUNC_ADPT_FMT" enter\n", FUNC_ADPT_ARG(padapter));
+
+	pnetdev = padapter->pnetdev;
+
+	if (check_fwstate(pmlmepriv, _FW_LINKED))
+		rtw_disassoc_cmd(padapter, 0, RTW_CMDF_DIRECTLY);
+
+#ifdef CONFIG_AP_MODE
+	if (MLME_IS_AP(padapter) || MLME_IS_MESH(padapter)) {
+		free_mlme_ap_info(padapter);
+		#ifdef CONFIG_HOSTAPD_MLME
+		hostapd_mode_unload(padapter);
+		#endif
+	}
+#endif
+
+	if (padapter->bup == _TRUE) {
+		#ifdef CONFIG_XMIT_ACK
+		if (padapter->xmitpriv.ack_tx)
+			rtw_ack_tx_done(&padapter->xmitpriv, RTW_SCTX_DONE_DRV_STOP);
+		#endif
+
+		rtw_intf_stop(padapter);
+	#ifndef CONFIG_NEW_NETDEV_HDL
+		rtw_stop_drv_threads(padapter);
+	#endif
+		padapter->bup = _FALSE;
+	}
+	#ifdef CONFIG_NEW_NETDEV_HDL
+	rtw_stop_drv_threads(padapter);
+	#endif
+	/* cancel timer after thread stop */
+	rtw_cancel_all_timer(padapter);
+}
+
+void rtw_drv_free_vir_if(_adapter *padapter)
+{
+	if (padapter == NULL)
+		return;
+
+	RTW_INFO(FUNC_ADPT_FMT"\n", FUNC_ADPT_ARG(padapter));
+	rtw_free_drv_sw(padapter);
+
+	/* TODO: use rtw_os_ndevs_deinit instead at the first stage of driver's dev deinit function */
+	rtw_os_ndev_free(padapter);
+
+	rtw_vmfree((u8 *)padapter, sizeof(_adapter));
+}
+
+
+void rtw_drv_stop_vir_ifaces(struct dvobj_priv *dvobj)
+{
+	int i;
+
+	for (i = VIF_START_ID; i < dvobj->iface_nums; i++)
+		rtw_drv_stop_vir_if(dvobj->padapters[i]);
+}
+
+void rtw_drv_free_vir_ifaces(struct dvobj_priv *dvobj)
+{
+	int i;
+
+	for (i = VIF_START_ID; i < dvobj->iface_nums; i++)
+		rtw_drv_free_vir_if(dvobj->padapters[i]);
+}
+
+
+#endif /*end of CONFIG_CONCURRENT_MODE*/
+
+/* IPv4, IPv6 IP addr notifier */
+static int rtw_inetaddr_notifier_call(struct notifier_block *nb,
+				      unsigned long action, void *data)
+{
+	struct in_ifaddr *ifa = (struct in_ifaddr *)data;
+	struct net_device *ndev;
+	struct mlme_ext_priv *pmlmeext = NULL;
+	struct mlme_ext_info *pmlmeinfo = NULL;
+	_adapter *adapter = NULL;
+
+	if (!ifa || !ifa->ifa_dev || !ifa->ifa_dev->dev)
+		return NOTIFY_DONE;
+
+	ndev = ifa->ifa_dev->dev;
+
+	if (!is_rtw_ndev(ndev))
+		return NOTIFY_DONE;
+
+	adapter = (_adapter *)rtw_netdev_priv(ifa->ifa_dev->dev);
+
+	if (adapter == NULL)
+		return NOTIFY_DONE;
+
+	pmlmeext = &adapter->mlmeextpriv;
+	pmlmeinfo = &pmlmeext->mlmext_info;
+
+	switch (action) {
+	case NETDEV_UP:
+		_rtw_memcpy(pmlmeinfo->ip_addr, &ifa->ifa_address,
+					RTW_IP_ADDR_LEN);
+		RTW_DBG("%s[%s]: up IP: %pI4\n", __func__,
+					ifa->ifa_label, pmlmeinfo->ip_addr);
+	break;
+	case NETDEV_DOWN:
+		_rtw_memset(pmlmeinfo->ip_addr, 0, RTW_IP_ADDR_LEN);
+		RTW_DBG("%s[%s]: down IP: %pI4\n", __func__,
+					ifa->ifa_label, pmlmeinfo->ip_addr);
+	break;
+	default:
+		RTW_DBG("%s: default action\n", __func__);
+	break;
+	}
+	return NOTIFY_DONE;
+}
+
+#ifdef CONFIG_IPV6
+static int rtw_inet6addr_notifier_call(struct notifier_block *nb,
+				       unsigned long action, void *data)
+{
+	struct inet6_ifaddr *inet6_ifa = data;
+	struct net_device *ndev;
+	struct pwrctrl_priv *pwrctl = NULL;
+	struct mlme_ext_priv *pmlmeext = NULL;
+	struct mlme_ext_info *pmlmeinfo = NULL;
+	_adapter *adapter = NULL;
+
+	if (!inet6_ifa || !inet6_ifa->idev || !inet6_ifa->idev->dev)
+		return NOTIFY_DONE;
+
+	ndev = inet6_ifa->idev->dev;
+
+	if (!is_rtw_ndev(ndev))
+		return NOTIFY_DONE;
+
+	adapter = (_adapter *)rtw_netdev_priv(inet6_ifa->idev->dev);
+
+	if (adapter == NULL)
+		return NOTIFY_DONE;
+
+	pmlmeext =  &adapter->mlmeextpriv;
+	pmlmeinfo = &pmlmeext->mlmext_info;
+	pwrctl = adapter_to_pwrctl(adapter);
+
+	pmlmeext = &adapter->mlmeextpriv;
+	pmlmeinfo = &pmlmeext->mlmext_info;
+
+	switch (action) {
+	case NETDEV_UP:
+#ifdef CONFIG_WOWLAN
+		pwrctl->wowlan_ns_offload_en = _TRUE;
+#endif
+		_rtw_memcpy(pmlmeinfo->ip6_addr, &inet6_ifa->addr,
+					RTW_IPv6_ADDR_LEN);
+		RTW_DBG("%s: up IPv6 addrs: %pI6\n", __func__,
+					pmlmeinfo->ip6_addr);
+			break;
+	case NETDEV_DOWN:
+#ifdef CONFIG_WOWLAN
+		pwrctl->wowlan_ns_offload_en = _FALSE;
+#endif
+		_rtw_memset(pmlmeinfo->ip6_addr, 0, RTW_IPv6_ADDR_LEN);
+		RTW_DBG("%s: down IPv6 addrs: %pI6\n", __func__,
+					pmlmeinfo->ip6_addr);
+		break;
+	default:
+		RTW_DBG("%s: default action\n", __func__);
+		break;
+	}
+	return NOTIFY_DONE;
+}
+#endif
+
+static struct notifier_block rtw_inetaddr_notifier = {
+	.notifier_call = rtw_inetaddr_notifier_call
+};
+
+#ifdef CONFIG_IPV6
+static struct notifier_block rtw_inet6addr_notifier = {
+	.notifier_call = rtw_inet6addr_notifier_call
+};
+#endif
+
+void rtw_inetaddr_notifier_register(void)
+{
+	RTW_INFO("%s\n", __func__);
+	register_inetaddr_notifier(&rtw_inetaddr_notifier);
+#ifdef CONFIG_IPV6
+	register_inet6addr_notifier(&rtw_inet6addr_notifier);
+#endif
+}
+
+void rtw_inetaddr_notifier_unregister(void)
+{
+	RTW_INFO("%s\n", __func__);
+	unregister_inetaddr_notifier(&rtw_inetaddr_notifier);
+#ifdef CONFIG_IPV6
+	unregister_inet6addr_notifier(&rtw_inet6addr_notifier);
+#endif
+}
+
+int rtw_os_ndevs_register(struct dvobj_priv *dvobj)
+{
+	int i, status = _SUCCESS;
+	struct registry_priv *regsty = dvobj_to_regsty(dvobj);
+	_adapter *adapter;
+
+#if defined(CONFIG_IOCTL_CFG80211)
+	if (rtw_cfg80211_dev_res_register(dvobj) != _SUCCESS) {
+		rtw_warn_on(1);
+		status = _FAIL;
+		goto exit;
+	}
+#endif
+
+	for (i = 0; i < dvobj->iface_nums; i++) {
+
+		if (i >= CONFIG_IFACE_NUMBER) {
+			RTW_ERR("%s %d >= CONFIG_IFACE_NUMBER(%d)\n", __func__, i, CONFIG_IFACE_NUMBER);
+			rtw_warn_on(1);
+			continue;
+		}
+
+		adapter = dvobj->padapters[i];
+		if (adapter) {
+			char *name;
+
+			#ifdef CONFIG_RTW_DYNAMIC_NDEV
+			if (!is_primary_adapter(adapter))
+				continue;
+			#endif
+
+			if (adapter->iface_id == IFACE_ID0)
+				name = regsty->ifname;
+			else if (adapter->iface_id == IFACE_ID1)
+				name = regsty->if2name;
+			else
+				name = "wlan%d";
+
+			status = rtw_os_ndev_register(adapter, name);
+
+			if (status != _SUCCESS) {
+				rtw_warn_on(1);
+				break;
+			}
+		}
+	}
+
+	if (status != _SUCCESS) {
+		for (; i >= 0; i--) {
+			adapter = dvobj->padapters[i];
+			if (adapter)
+				rtw_os_ndev_unregister(adapter);
+		}
+	}
+
+#if defined(CONFIG_IOCTL_CFG80211)
+	if (status != _SUCCESS)
+		rtw_cfg80211_dev_res_unregister(dvobj);
+#endif
+exit:
+	return status;
+}
+
+void rtw_os_ndevs_unregister(struct dvobj_priv *dvobj)
+{
+	int i;
+	_adapter *adapter = NULL;
+
+	for (i = 0; i < dvobj->iface_nums; i++) {
+		adapter = dvobj->padapters[i];
+
+		if (adapter == NULL)
+			continue;
+
+		rtw_os_ndev_unregister(adapter);
+	}
+
+#if defined(CONFIG_IOCTL_CFG80211)
+	rtw_cfg80211_dev_res_unregister(dvobj);
+#endif
+}
+
+/**
+ * rtw_os_ndevs_init - Allocate and register OS layer net devices and relating structures for @dvobj
+ * @dvobj: the dvobj on which this function applies
+ *
+ * Returns:
+ * _SUCCESS or _FAIL
+ */
+int rtw_os_ndevs_init(struct dvobj_priv *dvobj)
+{
+	int ret = _FAIL;
+
+	if (rtw_os_ndevs_alloc(dvobj) != _SUCCESS)
+		goto exit;
+
+	if (rtw_os_ndevs_register(dvobj) != _SUCCESS)
+		goto os_ndevs_free;
+
+	ret = _SUCCESS;
+
+os_ndevs_free:
+	if (ret != _SUCCESS)
+		rtw_os_ndevs_free(dvobj);
+exit:
+	return ret;
+}
+
+/**
+ * rtw_os_ndevs_deinit - Unregister and free OS layer net devices and relating structures for @dvobj
+ * @dvobj: the dvobj on which this function applies
+ */
+void rtw_os_ndevs_deinit(struct dvobj_priv *dvobj)
+{
+	rtw_os_ndevs_unregister(dvobj);
+	rtw_os_ndevs_free(dvobj);
+}
+
+#ifdef CONFIG_BR_EXT
+void netdev_br_init(struct net_device *netdev)
+{
+	_adapter *adapter = (_adapter *)rtw_netdev_priv(netdev);
+
+#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 35))
+	rcu_read_lock();
+#endif /* (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 35)) */
+
+	/* if(check_fwstate(pmlmepriv, WIFI_STATION_STATE|WIFI_ADHOC_STATE) == _TRUE) */
+	{
+		/* struct net_bridge	*br = netdev->br_port->br; */ /* ->dev->dev_addr; */
+#if (LINUX_VERSION_CODE <= KERNEL_VERSION(2, 6, 35))
+		if (netdev->br_port)
+#else   /* (LINUX_VERSION_CODE <= KERNEL_VERSION(2, 6, 35)) */
+		if (rcu_dereference(adapter->pnetdev->rx_handler_data))
+#endif /* (LINUX_VERSION_CODE <= KERNEL_VERSION(2, 6, 35)) */
+		{
+			struct net_device *br_netdev;
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 24))
+			br_netdev = dev_get_by_name(CONFIG_BR_EXT_BRNAME);
+#else	/* (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 24)) */
+			struct net *devnet = NULL;
+
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 26))
+			devnet = netdev->nd_net;
+#else	/* (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 26)) */
+			devnet = dev_net(netdev);
+#endif /* (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 26)) */
+
+			br_netdev = dev_get_by_name(devnet, CONFIG_BR_EXT_BRNAME);
+#endif /* (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 24)) */
+
+			if (br_netdev) {
+				memcpy(adapter->br_mac, br_netdev->dev_addr, ETH_ALEN);
+				dev_put(br_netdev);
+			} else
+				printk("%s()-%d: dev_get_by_name(%s) failed!", __FUNCTION__, __LINE__, CONFIG_BR_EXT_BRNAME);
+		}
+
+		adapter->ethBrExtInfo.addPPPoETag = 1;
+	}
+
+#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 35))
+	rcu_read_unlock();
+#endif /* (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 35)) */
+}
+#endif /* CONFIG_BR_EXT */
+
+#ifdef CONFIG_NEW_NETDEV_HDL
+int _netdev_open(struct net_device *pnetdev)
+{
+	uint status;
+	_adapter *padapter = (_adapter *)rtw_netdev_priv(pnetdev);
+	struct pwrctrl_priv *pwrctrlpriv = adapter_to_pwrctl(padapter);
+
+	RTW_INFO(FUNC_NDEV_FMT" start\n", FUNC_NDEV_ARG(pnetdev));
+
+	#ifdef CONFIG_AUTOSUSPEND
+	if (pwrctrlpriv->ps_flag == _TRUE) {
+		padapter->net_closed = _FALSE;
+		goto netdev_open_normal_process;
+	}
+	#endif /*CONFIG_AUTOSUSPEND*/
+
+	if (!rtw_is_hw_init_completed(padapter)) { // ips
+		rtw_clr_surprise_removed(padapter);
+		rtw_clr_drv_stopped(padapter);
+		RTW_ENABLE_FUNC(padapter, DF_RX_BIT);
+		RTW_ENABLE_FUNC(padapter, DF_TX_BIT);
+		status = rtw_hal_init(padapter);
+		if (status == _FAIL)
+			goto netdev_open_error;
+		rtw_led_control(padapter, LED_CTL_NO_LINK);
+		#ifndef RTW_HALMAC
+		status = rtw_mi_start_drv_threads(padapter);
+		if (status == _FAIL) {
+			RTW_ERR(FUNC_NDEV_FMT "Initialize driver thread failed!\n", FUNC_NDEV_ARG(pnetdev));
+			goto netdev_open_error;
+		}
+
+		rtw_intf_start(GET_PRIMARY_ADAPTER(padapter));
+		#endif /* !RTW_HALMAC */
+
+		{
+	#ifdef CONFIG_BT_COEXIST_SOCKET_TRX
+			_adapter *prim_adpt = GET_PRIMARY_ADAPTER(padapter);
+
+			if (prim_adpt && (_TRUE == prim_adpt->EEPROMBluetoothCoexist)) {
+				rtw_btcoex_init_socket(prim_adpt);
+				prim_adpt->coex_info.BtMgnt.ExtConfig.HCIExtensionVer = 0x04;
+				rtw_btcoex_SetHciVersion(prim_adpt, 0x04);
+			}
+	#endif /* CONFIG_BT_COEXIST_SOCKET_TRX */
+
+			_set_timer(&adapter_to_dvobj(padapter)->dynamic_chk_timer, 2000);
+
+	#ifndef CONFIG_IPS_CHECK_IN_WD
+			rtw_set_pwr_state_check_timer(pwrctrlpriv);
+	#endif /*CONFIG_IPS_CHECK_IN_WD*/
+		}
+
+	}
+
+	/*if (padapter->bup == _FALSE) */
+	{
+		rtw_hal_iface_init(padapter);
+
+		#ifdef CONFIG_RTW_NAPI
+		if(padapter->napi_state == NAPI_DISABLE) {
+			napi_enable(&padapter->napi);
+			padapter->napi_state = NAPI_ENABLE;
+		}
+		#endif
+
+		#ifdef CONFIG_IOCTL_CFG80211
+		rtw_cfg80211_init_wiphy(padapter);
+		rtw_cfg80211_init_wdev_data(padapter);
+		#endif
+		/* rtw_netif_carrier_on(pnetdev); */ /* call this func when rtw_joinbss_event_callback return success */
+		rtw_netif_wake_queue(pnetdev);
+
+		#ifdef CONFIG_BR_EXT
+		if (is_primary_adapter(padapter))
+			netdev_br_init(pnetdev);
+		#endif /* CONFIG_BR_EXT */
+
+
+		padapter->bup = _TRUE;
+		padapter->net_closed = _FALSE;
+		padapter->netif_up = _TRUE;
+		pwrctrlpriv->bips_processing = _FALSE;
+	}
+
+
+netdev_open_normal_process:
+	RTW_INFO(FUNC_NDEV_FMT" Success (bup=%d)\n", FUNC_NDEV_ARG(pnetdev), padapter->bup);
+	return 0;
+
+netdev_open_error:
+	padapter->bup = _FALSE;
+
+	#ifdef CONFIG_RTW_NAPI
+	if(padapter->napi_state == NAPI_ENABLE) {
+		napi_disable(&padapter->napi);
+		padapter->napi_state = NAPI_DISABLE;
+	}
+	#endif
+
+	rtw_netif_carrier_off(pnetdev);
+	rtw_netif_stop_queue(pnetdev);
+
+	RTW_ERR(FUNC_NDEV_FMT" Failed!! (bup=%d)\n", FUNC_NDEV_ARG(pnetdev), padapter->bup);
+
+	return -1;
+
+}
+
+#else
+int _netdev_open(struct net_device *pnetdev)
+{
+	uint status;
+	_adapter *padapter = (_adapter *)rtw_netdev_priv(pnetdev);
+	struct pwrctrl_priv *pwrctrlpriv = adapter_to_pwrctl(padapter);
+#ifdef CONFIG_BT_COEXIST_SOCKET_TRX
+	HAL_DATA_TYPE		*pHalData = GET_HAL_DATA(padapter);
+#endif /* CONFIG_BT_COEXIST_SOCKET_TRX */
+
+
+	RTW_INFO(FUNC_NDEV_FMT" , bup=%d\n", FUNC_NDEV_ARG(pnetdev), padapter->bup);
+
+	padapter->netif_up = _TRUE;
+
+#ifdef CONFIG_PLATFORM_INTEL_BYT
+	rtw_sdio_set_power(1);
+#endif /* CONFIG_PLATFORM_INTEL_BYT */
+
+	#ifdef CONFIG_AUTOSUSPEND
+	if (pwrctrlpriv->ps_flag == _TRUE) {
+		padapter->net_closed = _FALSE;
+		goto netdev_open_normal_process;
+	}
+	#endif
+
+	if (padapter->bup == _FALSE) {
+#ifdef CONFIG_PLATFORM_INTEL_BYT
+		rtw_macaddr_cfg(adapter_mac_addr(padapter),  get_hal_mac_addr(padapter));
+#ifdef CONFIG_MI_WITH_MBSSID_CAM
+		rtw_mbid_camid_alloc(padapter, adapter_mac_addr(padapter));
+#endif
+		rtw_init_wifidirect_addrs(padapter, adapter_mac_addr(padapter), adapter_mac_addr(padapter));
+		_rtw_memcpy(pnetdev->dev_addr, adapter_mac_addr(padapter), ETH_ALEN);
+#endif /* CONFIG_PLATFORM_INTEL_BYT */
+
+		rtw_clr_surprise_removed(padapter);
+		rtw_clr_drv_stopped(padapter);
+
+		status = rtw_hal_init(padapter);
+		if (status == _FAIL) {
+			goto netdev_open_error;
+		}
+#if 0/*#ifdef CONFIG_MI_WITH_MBSSID_CAM*/
+		rtw_hal_set_hwreg(padapter, HW_VAR_MAC_ADDR, adapter_mac_addr(padapter)); /* set mac addr to mac register */
+#endif
+
+		RTW_INFO("MAC Address = "MAC_FMT"\n", MAC_ARG(pnetdev->dev_addr));
+
+#ifndef RTW_HALMAC
+		status = rtw_start_drv_threads(padapter);
+		if (status == _FAIL) {
+			RTW_INFO("Initialize driver software resource Failed!\n");
+			goto netdev_open_error;
+		}
+#endif /* !RTW_HALMAC */
+
+#ifdef CONFIG_RTW_NAPI
+		if(padapter->napi_state == NAPI_DISABLE) {
+			napi_enable(&padapter->napi);
+			padapter->napi_state = NAPI_ENABLE;
+		}
+#endif
+
+#ifndef RTW_HALMAC
+		rtw_intf_start(padapter);
+#endif /* !RTW_HALMAC */
+
+#ifdef CONFIG_IOCTL_CFG80211
+		rtw_cfg80211_init_wiphy(padapter);
+		rtw_cfg80211_init_wdev_data(padapter);
+#endif
+
+		rtw_led_control(padapter, LED_CTL_NO_LINK);
+
+		padapter->bup = _TRUE;
+		pwrctrlpriv->bips_processing = _FALSE;
+
+#ifdef CONFIG_PLATFORM_INTEL_BYT
+#ifdef CONFIG_BT_COEXIST
+		rtw_btcoex_IpsNotify(padapter, IPS_NONE);
+#endif /* CONFIG_BT_COEXIST */
+#endif /* CONFIG_PLATFORM_INTEL_BYT		 */
+	}
+	padapter->net_closed = _FALSE;
+
+	_set_timer(&adapter_to_dvobj(padapter)->dynamic_chk_timer, 2000);
+
+#ifndef CONFIG_IPS_CHECK_IN_WD
+	rtw_set_pwr_state_check_timer(pwrctrlpriv);
+#endif
+
+	/* rtw_netif_carrier_on(pnetdev); */ /* call this func when rtw_joinbss_event_callback return success */
+	rtw_netif_wake_queue(pnetdev);
+
+#ifdef CONFIG_BR_EXT
+	netdev_br_init(pnetdev);
+#endif /* CONFIG_BR_EXT */
+
+#ifdef CONFIG_BT_COEXIST_SOCKET_TRX
+	if (is_primary_adapter(padapter) && (_TRUE == pHalData->EEPROMBluetoothCoexist)) {
+		rtw_btcoex_init_socket(padapter);
+		padapter->coex_info.BtMgnt.ExtConfig.HCIExtensionVer = 0x04;
+		rtw_btcoex_SetHciVersion(padapter, 0x04);
+	} else
+		RTW_INFO("CONFIG_BT_COEXIST: VIRTUAL_ADAPTER\n");
+#endif /* CONFIG_BT_COEXIST_SOCKET_TRX */
+
+
+netdev_open_normal_process:
+
+#ifdef CONFIG_CONCURRENT_MODE
+	{
+		_adapter *sec_adapter = adapter_to_dvobj(padapter)->padapters[IFACE_ID1];
+
+		#ifndef CONFIG_RTW_DYNAMIC_NDEV
+		if (sec_adapter && (sec_adapter->bup == _FALSE))
+			_netdev_vir_if_open(sec_adapter->pnetdev);
+		#endif
+	}
+#endif
+
+#ifdef CONFIG_RTW_CFGVEDNOR_LLSTATS
+	pwrctrlpriv->radio_on_start_time = rtw_get_current_time();
+	pwrctrlpriv->pwr_saving_start_time = rtw_get_current_time();
+	pwrctrlpriv->pwr_saving_time = 0;
+	pwrctrlpriv->on_time = 0;
+	pwrctrlpriv->tx_time = 0;
+	pwrctrlpriv->rx_time = 0;
+#endif /* CONFIG_RTW_CFGVEDNOR_LLSTATS */
+
+	RTW_INFO("-871x_drv - drv_open, bup=%d\n", padapter->bup);
+
+	return 0;
+
+netdev_open_error:
+
+	padapter->bup = _FALSE;
+
+#ifdef CONFIG_RTW_NAPI
+	if(padapter->napi_state == NAPI_ENABLE) {
+		napi_disable(&padapter->napi);
+		padapter->napi_state = NAPI_DISABLE;
+	}
+#endif
+
+	rtw_netif_carrier_off(pnetdev);
+	rtw_netif_stop_queue(pnetdev);
+
+	RTW_INFO("-871x_drv - drv_open fail, bup=%d\n", padapter->bup);
+
+	return -1;
+
+}
+#endif
+int netdev_open(struct net_device *pnetdev)
+{
+	int ret = _FALSE;
+	_adapter *padapter = (_adapter *)rtw_netdev_priv(pnetdev);
+	struct pwrctrl_priv *pwrctrlpriv = adapter_to_pwrctl(padapter);
+
+	if (pwrctrlpriv->bInSuspend == _TRUE) {
+		RTW_INFO(" [WARN] "ADPT_FMT" %s  failed, bInSuspend=%d\n", ADPT_ARG(padapter), __func__, pwrctrlpriv->bInSuspend);
+		return 0;
+	}
+
+	_enter_critical_mutex(&(adapter_to_dvobj(padapter)->hw_init_mutex), NULL);
+#ifdef CONFIG_NEW_NETDEV_HDL
+	ret = _netdev_open(pnetdev);
+#else
+	if (is_primary_adapter(padapter))
+		ret = _netdev_open(pnetdev);
+#ifdef CONFIG_CONCURRENT_MODE
+	else
+		ret = _netdev_vir_if_open(pnetdev);
+#endif
+#endif
+	_exit_critical_mutex(&(adapter_to_dvobj(padapter)->hw_init_mutex), NULL);
+
+
+#ifdef CONFIG_AUTO_AP_MODE
+	if (padapter->iface_id == IFACE_ID2)
+		rtw_start_auto_ap(padapter);
+#endif
+
+	return ret;
+}
+
+#ifdef CONFIG_IPS
+int  ips_netdrv_open(_adapter *padapter)
+{
+	int status = _SUCCESS;
+	/* struct pwrctrl_priv	*pwrpriv = adapter_to_pwrctl(padapter); */
+
+	padapter->net_closed = _FALSE;
+
+	RTW_INFO("===> %s.........\n", __FUNCTION__);
+
+
+	rtw_clr_drv_stopped(padapter);
+	/* padapter->bup = _TRUE; */
+#ifdef CONFIG_NEW_NETDEV_HDL
+	if (!rtw_is_hw_init_completed(padapter)) {
+		status = rtw_hal_init(padapter);
+		if (status == _FAIL) {
+			goto netdev_open_error;
+		}
+		rtw_mi_hal_iface_init(padapter);
+	}
+#else
+	status = rtw_hal_init(padapter);
+	if (status == _FAIL) {
+		goto netdev_open_error;
+	}
+#endif
+#if 0
+	rtw_mi_set_mac_addr(padapter);
+#endif
+#ifndef RTW_HALMAC
+	rtw_intf_start(padapter);
+#endif /* !RTW_HALMAC */
+
+#ifndef CONFIG_IPS_CHECK_IN_WD
+	rtw_set_pwr_state_check_timer(adapter_to_pwrctl(padapter));
+#endif
+	_set_timer(&adapter_to_dvobj(padapter)->dynamic_chk_timer, 2000);
+
+	return _SUCCESS;
+
+netdev_open_error:
+	/* padapter->bup = _FALSE; */
+	RTW_INFO("-ips_netdrv_open - drv_open failure, bup=%d\n", padapter->bup);
+
+	return _FAIL;
+}
+
+int rtw_ips_pwr_up(_adapter *padapter)
+{
+	int result;
+#if defined(CONFIG_SWLPS_IN_IPS) || defined(CONFIG_FWLPS_IN_IPS)
+#ifdef DBG_CONFIG_ERROR_DETECT
+	PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter);
+	struct sreset_priv *psrtpriv = &pHalData->srestpriv;
+#endif/* #ifdef DBG_CONFIG_ERROR_DETECT */
+#endif /* defined(CONFIG_SWLPS_IN_IPS) || defined(CONFIG_FWLPS_IN_IPS) */
+	systime start_time = rtw_get_current_time();
+	RTW_INFO("===>  rtw_ips_pwr_up..............\n");
+
+#if defined(CONFIG_SWLPS_IN_IPS) || defined(CONFIG_FWLPS_IN_IPS)
+#ifdef DBG_CONFIG_ERROR_DETECT
+	if (psrtpriv->silent_reset_inprogress == _TRUE)
+#endif/* #ifdef DBG_CONFIG_ERROR_DETECT */
+#endif /* defined(CONFIG_SWLPS_IN_IPS) || defined(CONFIG_FWLPS_IN_IPS) */
+		rtw_reset_drv_sw(padapter);
+
+	result = ips_netdrv_open(padapter);
+
+	rtw_led_control(padapter, LED_CTL_NO_LINK);
+
+	RTW_INFO("<===  rtw_ips_pwr_up.............. in %dms\n", rtw_get_passing_time_ms(start_time));
+	return result;
+
+}
+
+void rtw_ips_pwr_down(_adapter *padapter)
+{
+	systime start_time = rtw_get_current_time();
+	RTW_INFO("===> rtw_ips_pwr_down...................\n");
+
+	padapter->net_closed = _TRUE;
+
+	rtw_ips_dev_unload(padapter);
+	RTW_INFO("<=== rtw_ips_pwr_down..................... in %dms\n", rtw_get_passing_time_ms(start_time));
+}
+#endif
+void rtw_ips_dev_unload(_adapter *padapter)
+{
+#if defined(CONFIG_SWLPS_IN_IPS) || defined(CONFIG_FWLPS_IN_IPS)
+#ifdef DBG_CONFIG_ERROR_DETECT
+	PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter);
+	struct sreset_priv *psrtpriv = &pHalData->srestpriv;
+#endif/* #ifdef DBG_CONFIG_ERROR_DETECT */
+#endif /* defined(CONFIG_SWLPS_IN_IPS) || defined(CONFIG_FWLPS_IN_IPS) */
+	RTW_INFO("====> %s...\n", __FUNCTION__);
+
+
+#if defined(CONFIG_SWLPS_IN_IPS) || defined(CONFIG_FWLPS_IN_IPS)
+#ifdef DBG_CONFIG_ERROR_DETECT
+	if (psrtpriv->silent_reset_inprogress == _TRUE)
+#endif /* #ifdef DBG_CONFIG_ERROR_DETECT */
+#endif /* defined(CONFIG_SWLPS_IN_IPS) || defined(CONFIG_FWLPS_IN_IPS) */
+	{
+		rtw_hal_set_hwreg(padapter, HW_VAR_FIFO_CLEARN_UP, 0);
+		rtw_intf_stop(padapter);
+	}
+
+	if (!rtw_is_surprise_removed(padapter))
+		rtw_hal_deinit(padapter);
+
+}
+#ifdef CONFIG_NEW_NETDEV_HDL
+int _pm_netdev_open(_adapter *padapter)
+{
+	uint status;
+	struct pwrctrl_priv *pwrctrlpriv = adapter_to_pwrctl(padapter);
+	struct net_device *pnetdev = padapter->pnetdev;
+
+	RTW_INFO(FUNC_NDEV_FMT" start\n", FUNC_NDEV_ARG(pnetdev));
+
+	#ifdef CONFIG_AUTOSUSPEND
+	if (pwrctrlpriv->ps_flag == _TRUE) {
+		padapter->net_closed = _FALSE;
+		goto netdev_open_normal_process;
+	}
+	#endif /*CONFIG_AUTOSUSPEND*/
+
+	if (!rtw_is_hw_init_completed(padapter)) { // ips
+		rtw_clr_surprise_removed(padapter);
+		rtw_clr_drv_stopped(padapter);
+		status = rtw_hal_init(padapter);
+		if (status == _FAIL)
+			goto netdev_open_error;
+		rtw_led_control(padapter, LED_CTL_NO_LINK);
+		#ifndef RTW_HALMAC
+		status = rtw_mi_start_drv_threads(padapter);
+		if (status == _FAIL) {
+			RTW_ERR(FUNC_NDEV_FMT "Initialize driver thread failed!\n", FUNC_NDEV_ARG(pnetdev));
+			goto netdev_open_error;
+		}
+
+		rtw_intf_start(GET_PRIMARY_ADAPTER(padapter));
+		#endif /* !RTW_HALMAC */
+
+		{
+			_set_timer(&adapter_to_dvobj(padapter)->dynamic_chk_timer, 2000);
+
+	#ifndef CONFIG_IPS_CHECK_IN_WD
+			rtw_set_pwr_state_check_timer(pwrctrlpriv);
+	#endif /*CONFIG_IPS_CHECK_IN_WD*/
+		}
+
+	}
+
+	/*if (padapter->bup == _FALSE) */
+	{
+		rtw_hal_iface_init(padapter);
+
+		padapter->bup = _TRUE;
+		padapter->net_closed = _FALSE;
+		padapter->netif_up = _TRUE;
+		pwrctrlpriv->bips_processing = _FALSE;
+	}
+
+
+netdev_open_normal_process:
+	RTW_INFO(FUNC_NDEV_FMT" Success (bup=%d)\n", FUNC_NDEV_ARG(pnetdev), padapter->bup);
+	return 0;
+
+netdev_open_error:
+	padapter->bup = _FALSE;
+
+	rtw_netif_carrier_off(pnetdev);
+	rtw_netif_stop_queue(pnetdev);
+
+	RTW_ERR(FUNC_NDEV_FMT" Failed!! (bup=%d)\n", FUNC_NDEV_ARG(pnetdev), padapter->bup);
+
+	return -1;
+
+}
+int _mi_pm_netdev_open(struct net_device *pnetdev)
+{
+	int i;
+	int status = 0;
+	_adapter *padapter = (_adapter *)rtw_netdev_priv(pnetdev);
+	_adapter *iface;
+	struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
+
+	for (i = 0; i < dvobj->iface_nums; i++) {
+		iface = dvobj->padapters[i];
+		if (iface->netif_up) {
+			status = _pm_netdev_open(iface);
+			if (status == -1) {
+				RTW_ERR("%s failled\n", __func__);
+				break;
+			}
+		}
+	}
+
+	return status;
+}
+#endif /*CONFIG_NEW_NETDEV_HDL*/
+int pm_netdev_open(struct net_device *pnetdev, u8 bnormal)
+{
+	int status = 0;
+
+	_adapter *padapter = (_adapter *)rtw_netdev_priv(pnetdev);
+
+	if (_TRUE == bnormal) {
+		_enter_critical_mutex(&(adapter_to_dvobj(padapter)->hw_init_mutex), NULL);
+		#ifdef CONFIG_NEW_NETDEV_HDL
+		status = _mi_pm_netdev_open(pnetdev);
+		#else
+		status = _netdev_open(pnetdev);
+		#endif
+		_exit_critical_mutex(&(adapter_to_dvobj(padapter)->hw_init_mutex), NULL);
+	}
+#ifdef CONFIG_IPS
+	else
+		status = (_SUCCESS == ips_netdrv_open(padapter)) ? (0) : (-1);
+#endif
+
+	return status;
+}
+#ifdef CONFIG_CLIENT_PORT_CFG
+extern void rtw_hw_client_port_release(_adapter *adapter);
+#endif
+static int netdev_close(struct net_device *pnetdev)
+{
+	_adapter *padapter = (_adapter *)rtw_netdev_priv(pnetdev);
+	struct pwrctrl_priv *pwrctl = adapter_to_pwrctl(padapter);
+	struct mlme_priv	*pmlmepriv = &padapter->mlmepriv;
+#ifdef CONFIG_BT_COEXIST_SOCKET_TRX
+	HAL_DATA_TYPE		*pHalData = GET_HAL_DATA(padapter);
+#endif /* CONFIG_BT_COEXIST_SOCKET_TRX */
+
+	RTW_INFO(FUNC_NDEV_FMT" , bup=%d\n", FUNC_NDEV_ARG(pnetdev), padapter->bup);
+#ifndef CONFIG_PLATFORM_INTEL_BYT
+	#ifdef CONFIG_AUTOSUSPEND
+	if (pwrctl->bInternalAutoSuspend == _TRUE) {
+		/* rtw_pwr_wakeup(padapter); */
+		if (pwrctl->rf_pwrstate == rf_off)
+			pwrctl->ps_flag = _TRUE;
+	}
+	#endif
+	padapter->net_closed = _TRUE;
+	padapter->netif_up = _FALSE;
+	pmlmepriv->LinkDetectInfo.bBusyTraffic = _FALSE;
+
+#ifdef CONFIG_CLIENT_PORT_CFG
+	if (MLME_IS_STA(padapter))
+		rtw_hw_client_port_release(padapter);
+#endif
+	/*	if (!rtw_is_hw_init_completed(padapter)) {
+			RTW_INFO("(1)871x_drv - drv_close, bup=%d, hw_init_completed=%s\n", padapter->bup, rtw_is_hw_init_completed(padapter)?"_TRUE":"_FALSE");
+
+			rtw_set_drv_stopped(padapter);
+
+			rtw_dev_unload(padapter);
+		}
+		else*/
+	if (pwrctl->rf_pwrstate == rf_on) {
+		RTW_INFO("(2)871x_drv - drv_close, bup=%d, hw_init_completed=%s\n", padapter->bup, rtw_is_hw_init_completed(padapter) ? "_TRUE" : "_FALSE");
+
+		/* s1. */
+		if (pnetdev)
+			rtw_netif_stop_queue(pnetdev);
+
+#ifndef CONFIG_ANDROID
+		/* s2. */
+		LeaveAllPowerSaveMode(padapter);
+		rtw_disassoc_cmd(padapter, 500, RTW_CMDF_WAIT_ACK);
+		/* s2-2.  indicate disconnect to os */
+		rtw_indicate_disconnect(padapter, 0, _FALSE);
+		/* s2-3. */
+		rtw_free_assoc_resources_cmd(padapter, _TRUE, RTW_CMDF_WAIT_ACK);
+		/* s2-4. */
+		rtw_free_network_queue(padapter, _TRUE);
+#endif
+	}
+
+#ifdef CONFIG_BR_EXT
+	/* if (OPMODE & (WIFI_STATION_STATE | WIFI_ADHOC_STATE)) */
+	{
+		/* void nat25_db_cleanup(_adapter *priv); */
+		nat25_db_cleanup(padapter);
+	}
+#endif /* CONFIG_BR_EXT */
+
+#ifdef CONFIG_P2P
+	if (!rtw_p2p_chk_role(&padapter->wdinfo, P2P_ROLE_DISABLE))
+		rtw_p2p_enable(padapter, P2P_ROLE_DISABLE);
+#endif /* CONFIG_P2P */
+
+	rtw_scan_abort(padapter); /* stop scanning process before wifi is going to down */
+#ifdef CONFIG_IOCTL_CFG80211
+	rtw_cfg80211_wait_scan_req_empty(padapter, 200);
+	adapter_wdev_data(padapter)->bandroid_scan = _FALSE;
+	/* padapter->rtw_wdev->iftype = NL80211_IFTYPE_MONITOR; */ /* set this at the end */
+#endif /* CONFIG_IOCTL_CFG80211 */
+
+#ifdef CONFIG_WAPI_SUPPORT
+	rtw_wapi_disable_tx(padapter);
+#endif
+#ifdef CONFIG_BT_COEXIST_SOCKET_TRX
+	if (is_primary_adapter(padapter) && (_TRUE == pHalData->EEPROMBluetoothCoexist))
+		rtw_btcoex_close_socket(padapter);
+	else
+		RTW_INFO("CONFIG_BT_COEXIST: VIRTUAL_ADAPTER\n");
+#endif /* CONFIG_BT_COEXIST_SOCKET_TRX */
+#else /* !CONFIG_PLATFORM_INTEL_BYT */
+
+	if (pwrctl->bInSuspend == _TRUE) {
+		RTW_INFO("+871x_drv - drv_close, bInSuspend=%d\n", pwrctl->bInSuspend);
+		return 0;
+	}
+
+	rtw_scan_abort(padapter); /* stop scanning process before wifi is going to down */
+#ifdef CONFIG_IOCTL_CFG80211
+	rtw_cfg80211_wait_scan_req_empty(padapter, 200);
+#endif
+
+	RTW_INFO("netdev_close, bips_processing=%d\n", pwrctl->bips_processing);
+	while (pwrctl->bips_processing == _TRUE) /* waiting for ips_processing done before call rtw_dev_unload() */
+		rtw_msleep_os(1);
+
+	rtw_dev_unload(padapter);
+	rtw_sdio_set_power(0);
+
+#endif /* !CONFIG_PLATFORM_INTEL_BYT */
+
+	RTW_INFO("-871x_drv - drv_close, bup=%d\n", padapter->bup);
+
+	return 0;
+
+}
+
+int pm_netdev_close(struct net_device *pnetdev, u8 bnormal)
+{
+	int status = 0;
+
+	status = netdev_close(pnetdev);
+
+	return status;
+}
+
+void rtw_ndev_destructor(struct net_device *ndev)
+{
+	RTW_INFO(FUNC_NDEV_FMT"\n", FUNC_NDEV_ARG(ndev));
+
+#ifdef CONFIG_IOCTL_CFG80211
+	if (ndev->ieee80211_ptr)
+		rtw_mfree((u8 *)ndev->ieee80211_ptr, sizeof(struct wireless_dev));
+#endif
+	free_netdev(ndev);
+}
+
+#ifdef CONFIG_ARP_KEEP_ALIVE
+struct route_info {
+	struct in_addr dst_addr;
+	struct in_addr src_addr;
+	struct in_addr gateway;
+	unsigned int dev_index;
+};
+
+static void parse_routes(struct nlmsghdr *nl_hdr, struct route_info *rt_info)
+{
+	struct rtmsg *rt_msg;
+	struct rtattr *rt_attr;
+	int rt_len;
+
+	rt_msg = (struct rtmsg *) NLMSG_DATA(nl_hdr);
+	if ((rt_msg->rtm_family != AF_INET) || (rt_msg->rtm_table != RT_TABLE_MAIN))
+		return;
+
+	rt_attr = (struct rtattr *) RTM_RTA(rt_msg);
+	rt_len = RTM_PAYLOAD(nl_hdr);
+
+	for (; RTA_OK(rt_attr, rt_len); rt_attr = RTA_NEXT(rt_attr, rt_len)) {
+		switch (rt_attr->rta_type) {
+		case RTA_OIF:
+			rt_info->dev_index = *(int *) RTA_DATA(rt_attr);
+			break;
+		case RTA_GATEWAY:
+			rt_info->gateway.s_addr = *(u_int *) RTA_DATA(rt_attr);
+			break;
+		case RTA_PREFSRC:
+			rt_info->src_addr.s_addr = *(u_int *) RTA_DATA(rt_attr);
+			break;
+		case RTA_DST:
+			rt_info->dst_addr.s_addr = *(u_int *) RTA_DATA(rt_attr);
+			break;
+		}
+	}
+}
+
+static int route_dump(u32 *gw_addr , int *gw_index)
+{
+	int err = 0;
+	struct socket *sock;
+	struct {
+		struct nlmsghdr nlh;
+		struct rtgenmsg g;
+	} req;
+	struct msghdr msg;
+	struct iovec iov;
+	struct sockaddr_nl nladdr;
+	mm_segment_t oldfs;
+	char *pg;
+	int size = 0;
+
+	err = sock_create(AF_NETLINK, SOCK_DGRAM, NETLINK_ROUTE, &sock);
+	if (err) {
+		printk(": Could not create a datagram socket, error = %d\n", -ENXIO);
+		return err;
+	}
+
+	memset(&nladdr, 0, sizeof(nladdr));
+	nladdr.nl_family = AF_NETLINK;
+
+	req.nlh.nlmsg_len = sizeof(req);
+	req.nlh.nlmsg_type = RTM_GETROUTE;
+	req.nlh.nlmsg_flags = NLM_F_ROOT | NLM_F_MATCH | NLM_F_REQUEST;
+	req.nlh.nlmsg_pid = 0;
+	req.g.rtgen_family = AF_INET;
+
+	iov.iov_base = &req;
+	iov.iov_len = sizeof(req);
+
+	msg.msg_name = &nladdr;
+	msg.msg_namelen = sizeof(nladdr);
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 19, 0))
+	/* referece:sock_xmit in kernel code
+	 * WRITE for sock_sendmsg, READ for sock_recvmsg
+	 * third parameter for msg_iovlen
+	 * last parameter for iov_len
+	 */
+	iov_iter_init(&msg.msg_iter, WRITE, &iov, 1, sizeof(req));
+#else
+	msg.msg_iov = &iov;
+	msg.msg_iovlen = 1;
+#endif
+	msg.msg_control = NULL;
+	msg.msg_controllen = 0;
+	msg.msg_flags = MSG_DONTWAIT;
+
+	oldfs = get_fs();
+	set_fs(KERNEL_DS);
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 1, 0))
+	err = sock_sendmsg(sock, &msg);
+#else
+	err = sock_sendmsg(sock, &msg, sizeof(req));
+#endif
+	set_fs(oldfs);
+
+	if (err < 0)
+		goto out_sock;
+
+	pg = (char *) __get_free_page(GFP_KERNEL);
+	if (pg == NULL) {
+		err = -ENOMEM;
+		goto out_sock;
+	}
+
+#if defined(CONFIG_IPV6) || defined(CONFIG_IPV6_MODULE)
+restart:
+#endif
+
+	for (;;) {
+		struct nlmsghdr *h;
+
+		iov.iov_base = pg;
+		iov.iov_len = PAGE_SIZE;
+
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 19, 0))
+		iov_iter_init(&msg.msg_iter, READ, &iov, 1, PAGE_SIZE);
+#endif
+
+		oldfs = get_fs();
+		set_fs(KERNEL_DS);
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 7, 0))
+		err = sock_recvmsg(sock, &msg, MSG_DONTWAIT);
+#else
+		err = sock_recvmsg(sock, &msg, PAGE_SIZE, MSG_DONTWAIT);
+#endif
+		set_fs(oldfs);
+
+		if (err < 0)
+			goto out_sock_pg;
+
+		if (msg.msg_flags & MSG_TRUNC) {
+			err = -ENOBUFS;
+			goto out_sock_pg;
+		}
+
+		h = (struct nlmsghdr *) pg;
+
+		while (NLMSG_OK(h, err)) {
+			struct route_info rt_info;
+			if (h->nlmsg_type == NLMSG_DONE) {
+				err = 0;
+				goto done;
+			}
+
+			if (h->nlmsg_type == NLMSG_ERROR) {
+				struct nlmsgerr *errm = (struct nlmsgerr *) NLMSG_DATA(h);
+				err = errm->error;
+				printk("NLMSG error: %d\n", errm->error);
+				goto done;
+			}
+
+			if (h->nlmsg_type == RTM_GETROUTE)
+				printk("RTM_GETROUTE: NLMSG: %d\n", h->nlmsg_type);
+			if (h->nlmsg_type != RTM_NEWROUTE) {
+				printk("NLMSG: %d\n", h->nlmsg_type);
+				err = -EINVAL;
+				goto done;
+			}
+
+			memset(&rt_info, 0, sizeof(struct route_info));
+			parse_routes(h, &rt_info);
+			if (!rt_info.dst_addr.s_addr && rt_info.gateway.s_addr && rt_info.dev_index) {
+				*gw_addr = rt_info.gateway.s_addr;
+				*gw_index = rt_info.dev_index;
+
+			}
+			h = NLMSG_NEXT(h, err);
+		}
+
+		if (err) {
+			printk("!!!Remnant of size %d %d %d\n", err, h->nlmsg_len, h->nlmsg_type);
+			err = -EINVAL;
+			break;
+		}
+	}
+
+done:
+#if defined(CONFIG_IPV6) || defined(CONFIG_IPV6_MODULE)
+	if (!err && req.g.rtgen_family == AF_INET) {
+		req.g.rtgen_family = AF_INET6;
+
+		iov.iov_base = &req;
+		iov.iov_len = sizeof(req);
+
+		msg.msg_name = &nladdr;
+		msg.msg_namelen = sizeof(nladdr);
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 19, 0))
+		iov_iter_init(&msg.msg_iter, WRITE, &iov, 1, sizeof(req));
+#else
+		msg.msg_iov = &iov;
+		msg.msg_iovlen = 1;
+#endif
+		msg.msg_control = NULL;
+		msg.msg_controllen = 0;
+		msg.msg_flags = MSG_DONTWAIT;
+
+		oldfs = get_fs();
+		set_fs(KERNEL_DS);
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 1, 0))
+		err = sock_sendmsg(sock, &msg);
+#else
+		err = sock_sendmsg(sock, &msg, sizeof(req));
+#endif
+		set_fs(oldfs);
+
+		if (err > 0)
+			goto restart;
+	}
+#endif
+
+out_sock_pg:
+	free_page((unsigned long) pg);
+
+out_sock:
+	sock_release(sock);
+	return err;
+}
+
+static int arp_query(unsigned char *haddr, u32 paddr,
+		     struct net_device *dev)
+{
+	struct neighbour *neighbor_entry;
+	int	ret = 0;
+
+	neighbor_entry = neigh_lookup(&arp_tbl, &paddr, dev);
+
+	if (neighbor_entry != NULL) {
+		neighbor_entry->used = jiffies;
+		if (neighbor_entry->nud_state & NUD_VALID) {
+			_rtw_memcpy(haddr, neighbor_entry->ha, dev->addr_len);
+			ret = 1;
+		}
+		neigh_release(neighbor_entry);
+	}
+	return ret;
+}
+
+static int get_defaultgw(u32 *ip_addr , char mac[])
+{
+	int gw_index = 0; /* oif device index */
+	struct net_device *gw_dev = NULL; /* oif device */
+
+	route_dump(ip_addr, &gw_index);
+
+	if (!(*ip_addr) || !gw_index) {
+		/* RTW_INFO("No default GW\n"); */
+		return -1;
+	}
+
+	gw_dev = dev_get_by_index(&init_net, gw_index);
+
+	if (gw_dev == NULL) {
+		/* RTW_INFO("get Oif Device Fail\n"); */
+		return -1;
+	}
+
+	if (!arp_query(mac, *ip_addr, gw_dev)) {
+		/* RTW_INFO( "arp query failed\n"); */
+		dev_put(gw_dev);
+		return -1;
+
+	}
+	dev_put(gw_dev);
+
+	return 0;
+}
+
+int	rtw_gw_addr_query(_adapter *padapter)
+{
+	struct mlme_priv	*pmlmepriv = &padapter->mlmepriv;
+	struct pwrctrl_priv *pwrctl = adapter_to_pwrctl(padapter);
+	u32 gw_addr = 0; /* default gw address */
+	unsigned char gw_mac[32] = {0}; /* default gw mac */
+	int i;
+	int res;
+
+	res = get_defaultgw(&gw_addr, gw_mac);
+	if (!res) {
+		pmlmepriv->gw_ip[0] = gw_addr & 0xff;
+		pmlmepriv->gw_ip[1] = (gw_addr & 0xff00) >> 8;
+		pmlmepriv->gw_ip[2] = (gw_addr & 0xff0000) >> 16;
+		pmlmepriv->gw_ip[3] = (gw_addr & 0xff000000) >> 24;
+		_rtw_memcpy(pmlmepriv->gw_mac_addr, gw_mac, ETH_ALEN);
+		RTW_INFO("%s Gateway Mac:\t" MAC_FMT "\n", __FUNCTION__, MAC_ARG(pmlmepriv->gw_mac_addr));
+		RTW_INFO("%s Gateway IP:\t" IP_FMT "\n", __FUNCTION__, IP_ARG(pmlmepriv->gw_ip));
+	} else
+		RTW_INFO("Get Gateway IP/MAC fail!\n");
+
+	return res;
+}
+#endif
+
+void rtw_dev_unload(PADAPTER padapter)
+{
+	struct pwrctrl_priv *pwrctl = adapter_to_pwrctl(padapter);
+	struct dvobj_priv *pobjpriv = padapter->dvobj;
+	struct debug_priv *pdbgpriv = &pobjpriv->drv_dbg;
+	struct cmd_priv *pcmdpriv = &padapter->cmdpriv;
+
+	if (padapter->bup == _TRUE) {
+		RTW_INFO("==> "FUNC_ADPT_FMT"\n", FUNC_ADPT_ARG(padapter));
+
+#ifdef CONFIG_WOWLAN
+#ifdef CONFIG_GPIO_WAKEUP
+		/*default wake up pin change to BT*/
+		RTW_INFO("%s:default wake up pin change to BT\n", __FUNCTION__);
+		rtw_hal_switch_gpio_wl_ctrl(padapter, WAKEUP_GPIO_IDX, _FALSE);
+#endif /* CONFIG_GPIO_WAKEUP */
+#endif /* CONFIG_WOWLAN */
+
+		rtw_set_drv_stopped(padapter);
+#ifdef CONFIG_XMIT_ACK
+		if (padapter->xmitpriv.ack_tx)
+			rtw_ack_tx_done(&padapter->xmitpriv, RTW_SCTX_DONE_DRV_STOP);
+#endif
+
+		rtw_intf_stop(padapter);
+
+		#ifdef CONFIG_AUTOSUSPEND
+		if (!pwrctl->bInternalAutoSuspend)
+		#endif
+		{
+			rtw_stop_drv_threads(padapter);
+
+			if (ATOMIC_READ(&(pcmdpriv->cmdthd_running)) == _TRUE) {
+				RTW_ERR("cmd_thread not stop !!\n");
+				rtw_warn_on(1);
+			}
+		}
+		/* check the status of IPS */
+		if (rtw_hal_check_ips_status(padapter) == _TRUE || pwrctl->rf_pwrstate == rf_off) { /* check HW status and SW state */
+			RTW_PRINT("%s: driver in IPS-FWLPS\n", __func__);
+			pdbgpriv->dbg_dev_unload_inIPS_cnt++;
+		} else
+			RTW_PRINT("%s: driver not in IPS\n", __func__);
+
+		if (!rtw_is_surprise_removed(padapter)) {
+#ifdef CONFIG_BT_COEXIST
+			rtw_btcoex_IpsNotify(padapter, pwrctl->ips_mode_req);
+#endif
+#ifdef CONFIG_WOWLAN
+			if (pwrctl->bSupportRemoteWakeup == _TRUE &&
+			    pwrctl->wowlan_mode == _TRUE)
+				RTW_PRINT("%s bSupportRemoteWakeup==_TRUE  do not run rtw_hal_deinit()\n", __FUNCTION__);
+			else
+#endif
+			{
+				/* amy modify 20120221 for power seq is different between driver open and ips */
+				rtw_hal_deinit(padapter);
+			}
+			rtw_set_surprise_removed(padapter);
+		}
+
+		padapter->bup = _FALSE;
+
+		RTW_INFO("<== "FUNC_ADPT_FMT"\n", FUNC_ADPT_ARG(padapter));
+	} else {
+		RTW_INFO("%s: bup==_FALSE\n", __FUNCTION__);
+	}
+	rtw_cancel_all_timer(padapter);
+}
+
+int rtw_suspend_free_assoc_resource(_adapter *padapter)
+{
+	struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
+#ifdef CONFIG_P2P
+	struct wifidirect_info	*pwdinfo = &padapter->wdinfo;
+#endif /* CONFIG_P2P */
+
+	RTW_INFO("==> "FUNC_ADPT_FMT" entry....\n", FUNC_ADPT_ARG(padapter));
+
+	if (rtw_chk_roam_flags(padapter, RTW_ROAM_ON_RESUME)) {
+		if (check_fwstate(pmlmepriv, WIFI_STATION_STATE)
+			&& check_fwstate(pmlmepriv, _FW_LINKED)
+			#ifdef CONFIG_P2P
+			&& (rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE)
+				#if defined(CONFIG_IOCTL_CFG80211) && RTW_P2P_GROUP_INTERFACE
+				|| rtw_p2p_chk_role(pwdinfo, P2P_ROLE_DEVICE)
+				#endif
+				)
+			#endif /* CONFIG_P2P */
+		) {
+			RTW_INFO("%s %s(" MAC_FMT "), length:%d assoc_ssid.length:%d\n", __FUNCTION__,
+				pmlmepriv->cur_network.network.Ssid.Ssid,
+				MAC_ARG(pmlmepriv->cur_network.network.MacAddress),
+				pmlmepriv->cur_network.network.Ssid.SsidLength,
+				pmlmepriv->assoc_ssid.SsidLength);
+			rtw_set_to_roam(padapter, 1);
+		}
+	}
+
+	if (check_fwstate(pmlmepriv, WIFI_STATION_STATE) && check_fwstate(pmlmepriv, _FW_LINKED)) {
+		rtw_disassoc_cmd(padapter, 0, RTW_CMDF_DIRECTLY);
+		/* s2-2.  indicate disconnect to os */
+		rtw_indicate_disconnect(padapter, 0, _FALSE);
+	}
+#ifdef CONFIG_AP_MODE
+	else if (MLME_IS_AP(padapter) || MLME_IS_MESH(padapter))
+		rtw_sta_flush(padapter, _TRUE);
+#endif
+
+	/* s2-3. */
+	rtw_free_assoc_resources(padapter, _TRUE);
+
+	/* s2-4. */
+#ifdef CONFIG_AUTOSUSPEND
+	if (is_primary_adapter(padapter) && (!adapter_to_pwrctl(padapter)->bInternalAutoSuspend))
+#endif
+		rtw_free_network_queue(padapter, _TRUE);
+
+	if (check_fwstate(pmlmepriv, _FW_UNDER_SURVEY)) {
+		RTW_PRINT("%s: fw_under_survey\n", __func__);
+		rtw_indicate_scan_done(padapter, 1);
+		clr_fwstate(pmlmepriv, _FW_UNDER_SURVEY);
+	}
+
+	if (check_fwstate(pmlmepriv, _FW_UNDER_LINKING) == _TRUE) {
+		RTW_PRINT("%s: fw_under_linking\n", __FUNCTION__);
+		rtw_indicate_disconnect(padapter, 0, _FALSE);
+	}
+
+	RTW_INFO("<== "FUNC_ADPT_FMT" exit....\n", FUNC_ADPT_ARG(padapter));
+	return _SUCCESS;
+}
+
+#ifdef CONFIG_WOWLAN
+int rtw_suspend_wow(_adapter *padapter)
+{
+	u8 ch, bw, offset;
+	struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
+	struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter);
+	struct wowlan_ioctl_param poidparam;
+	u8 ps_mode;
+	int ret = _SUCCESS;
+
+	RTW_INFO("==> "FUNC_ADPT_FMT" entry....\n", FUNC_ADPT_ARG(padapter));
+
+
+	RTW_INFO("wowlan_mode: %d\n", pwrpriv->wowlan_mode);
+	RTW_INFO("wowlan_pno_enable: %d\n", pwrpriv->wowlan_pno_enable);
+#ifdef CONFIG_P2P_WOWLAN
+	RTW_INFO("wowlan_p2p_enable: %d\n", pwrpriv->wowlan_p2p_enable);
+#endif
+
+	if (pwrpriv->wowlan_mode == _TRUE) {
+		rtw_mi_netif_stop_queue(padapter);
+		#ifdef CONFIG_CONCURRENT_MODE
+		rtw_mi_buddy_netif_carrier_off(padapter);
+		#endif
+
+		/* 0. Power off LED */
+		rtw_led_control(padapter, LED_CTL_POWER_OFF);
+
+#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
+		/* 2.only for SDIO disable interrupt */
+		rtw_intf_stop(padapter);
+
+		/* 2.1 clean interrupt */
+		rtw_hal_clear_interrupt(padapter);
+#endif /* CONFIG_SDIO_HCI */
+
+		/* 1. stop thread */
+		rtw_set_drv_stopped(padapter);	/*for stop thread*/
+		rtw_mi_stop_drv_threads(padapter);
+
+		rtw_clr_drv_stopped(padapter);	/*for 32k command*/
+
+		/* #ifdef CONFIG_LPS */
+		/* rtw_set_ps_mode(padapter, PS_MODE_ACTIVE, 0, 0, "WOWLAN"); */
+		/* #endif */
+
+		#ifdef CONFIG_SDIO_HCI
+		/* 2.2 free irq */
+		#if !(CONFIG_RTW_SDIO_KEEP_IRQ)
+		sdio_free_irq(adapter_to_dvobj(padapter));
+		#endif
+		#endif/*CONFIG_SDIO_HCI*/
+
+#ifdef CONFIG_RUNTIME_PORT_SWITCH
+		if (rtw_port_switch_chk(padapter)) {
+			RTW_INFO(" ### PORT SWITCH ###\n");
+			rtw_hal_set_hwreg(padapter, HW_VAR_PORT_SWITCH, NULL);
+		}
+#endif
+
+		poidparam.subcode = WOWLAN_ENABLE;
+		rtw_hal_set_hwreg(padapter, HW_VAR_WOWLAN, (u8 *)&poidparam);
+		if (rtw_chk_roam_flags(padapter, RTW_ROAM_ON_RESUME)) {
+			if (check_fwstate(pmlmepriv, WIFI_STATION_STATE)
+			    && check_fwstate(pmlmepriv, _FW_LINKED)) {
+				RTW_INFO("%s %s(" MAC_FMT "), length:%d assoc_ssid.length:%d\n", __FUNCTION__,
+					pmlmepriv->cur_network.network.Ssid.Ssid,
+					MAC_ARG(pmlmepriv->cur_network.network.MacAddress),
+					pmlmepriv->cur_network.network.Ssid.SsidLength,
+					 pmlmepriv->assoc_ssid.SsidLength);
+
+				rtw_set_to_roam(padapter, 0);
+			}
+		}
+
+		RTW_PRINT("%s: wowmode suspending\n", __func__);
+
+		if (check_fwstate(pmlmepriv, _FW_UNDER_SURVEY) == _TRUE) {
+			RTW_PRINT("%s: fw_under_survey\n", __func__);
+			rtw_indicate_scan_done(padapter, 1);
+			clr_fwstate(pmlmepriv, _FW_UNDER_SURVEY);
+		}
+
+#if 1
+		if (rtw_mi_check_status(padapter, MI_LINKED)) {
+			ch =  rtw_mi_get_union_chan(padapter);
+			bw = rtw_mi_get_union_bw(padapter);
+			offset = rtw_mi_get_union_offset(padapter);
+			RTW_INFO(FUNC_ADPT_FMT" back to linked/linking union - ch:%u, bw:%u, offset:%u\n",
+				 FUNC_ADPT_ARG(padapter), ch, bw, offset);
+			set_channel_bwmode(padapter, ch, offset, bw);
+		}
+#else
+		if (rtw_mi_get_ch_setting_union(padapter, &ch, &bw, &offset) != 0) {
+			RTW_INFO(FUNC_ADPT_FMT" back to linked/linking union - ch:%u, bw:%u, offset:%u\n",
+				 FUNC_ADPT_ARG(padapter), ch, bw, offset);
+			set_channel_bwmode(padapter, ch, offset, bw);
+			rtw_mi_update_union_chan_inf(padapter, ch, offset, bw);
+		}
+#endif
+#ifdef CONFIG_CONCURRENT_MODE
+		rtw_mi_buddy_suspend_free_assoc_resource(padapter);
+#endif
+
+#ifdef CONFIG_BT_COEXIST
+		rtw_btcoex_SuspendNotify(padapter, BTCOEX_SUSPEND_STATE_SUSPEND_KEEP_ANT);
+#endif
+
+		if (pwrpriv->wowlan_pno_enable) {
+			RTW_PRINT("%s: pno: %d\n", __func__,
+				  pwrpriv->wowlan_pno_enable);
+#ifdef CONFIG_FWLPS_IN_IPS
+			rtw_set_fw_in_ips_mode(padapter, _TRUE);
+#endif
+		}
+#ifdef CONFIG_LPS
+		else {
+			if (!(pwrpriv->wowlan_dis_lps)) {
+				rtw_wow_lps_level_decide(padapter, _TRUE);
+				rtw_set_ps_mode(padapter, PS_MODE_MAX, 0, 0, "WOWLAN");
+			}
+		}
+#endif /* #ifdef CONFIG_LPS */
+
+	} else
+		RTW_PRINT("%s: ### ERROR ### wowlan_mode=%d\n", __FUNCTION__, pwrpriv->wowlan_mode);
+	RTW_INFO("<== "FUNC_ADPT_FMT" exit....\n", FUNC_ADPT_ARG(padapter));
+	return ret;
+}
+#endif /* #ifdef CONFIG_WOWLAN */
+
+#ifdef CONFIG_AP_WOWLAN
+int rtw_suspend_ap_wow(_adapter *padapter)
+{
+	u8 ch, bw, offset;
+	struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
+	struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter);
+	struct wowlan_ioctl_param poidparam;
+	u8 ps_mode;
+	int ret = _SUCCESS;
+
+	RTW_INFO("==> "FUNC_ADPT_FMT" entry....\n", FUNC_ADPT_ARG(padapter));
+
+	pwrpriv->wowlan_ap_mode = _TRUE;
+
+	RTW_INFO("wowlan_ap_mode: %d\n", pwrpriv->wowlan_ap_mode);
+
+	rtw_mi_netif_stop_queue(padapter);
+
+	/* 0. Power off LED */
+	rtw_led_control(padapter, LED_CTL_POWER_OFF);
+#ifdef CONFIG_SDIO_HCI
+	/* 2.only for SDIO disable interrupt*/
+	rtw_intf_stop(padapter);
+
+	/* 2.1 clean interrupt */
+	rtw_hal_clear_interrupt(padapter);
+#endif /* CONFIG_SDIO_HCI */
+
+	/* 1. stop thread */
+	rtw_set_drv_stopped(padapter);	/*for stop thread*/
+	rtw_mi_stop_drv_threads(padapter);
+	rtw_clr_drv_stopped(padapter);	/*for 32k command*/
+
+	#ifdef CONFIG_SDIO_HCI
+	/* 2.2 free irq */
+	#if !(CONFIG_RTW_SDIO_KEEP_IRQ)
+	sdio_free_irq(adapter_to_dvobj(padapter));
+	#endif
+	#endif/*CONFIG_SDIO_HCI*/
+
+#ifdef CONFIG_RUNTIME_PORT_SWITCH
+	if (rtw_port_switch_chk(padapter)) {
+		RTW_INFO(" ### PORT SWITCH ###\n");
+		rtw_hal_set_hwreg(padapter, HW_VAR_PORT_SWITCH, NULL);
+	}
+#endif
+
+	poidparam.subcode = WOWLAN_AP_ENABLE;
+	rtw_hal_set_hwreg(padapter, HW_VAR_WOWLAN, (u8 *)&poidparam);
+
+	RTW_PRINT("%s: wowmode suspending\n", __func__);
+#if 1
+	if (rtw_mi_check_status(padapter, MI_LINKED)) {
+		ch =  rtw_mi_get_union_chan(padapter);
+		bw = rtw_mi_get_union_bw(padapter);
+		offset = rtw_mi_get_union_offset(padapter);
+		RTW_INFO("back to linked/linking union - ch:%u, bw:%u, offset:%u\n", ch, bw, offset);
+		set_channel_bwmode(padapter, ch, offset, bw);
+	}
+#else
+	if (rtw_mi_get_ch_setting_union(padapter, &ch, &bw, &offset) != 0) {
+		RTW_INFO("back to linked/linking union - ch:%u, bw:%u, offset:%u\n", ch, bw, offset);
+		set_channel_bwmode(padapter, ch, offset, bw);
+		rtw_mi_update_union_chan_inf(padapter, ch, offset, bw);
+	}
+#endif
+
+	/*FOR ONE AP - TODO :Multi-AP*/
+	{
+		int i;
+		_adapter *iface;
+		struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
+
+		for (i = 0; i < dvobj->iface_nums; i++) {
+			iface = dvobj->padapters[i];
+			if ((iface) && rtw_is_adapter_up(iface)) {
+				if (check_fwstate(&iface->mlmepriv, WIFI_AP_STATE | WIFI_MESH_STATE) == _FALSE)
+					rtw_suspend_free_assoc_resource(iface);
+			}
+		}
+
+	}
+
+#ifdef CONFIG_BT_COEXIST
+	rtw_btcoex_SuspendNotify(padapter, BTCOEX_SUSPEND_STATE_SUSPEND_KEEP_ANT);
+#endif
+
+#ifdef CONFIG_LPS
+	if (!(pwrpriv->wowlan_dis_lps)) {
+		rtw_wow_lps_level_decide(padapter, _TRUE);
+		rtw_set_ps_mode(padapter, PS_MODE_MIN, 0, 0, "AP-WOWLAN");
+	}
+#endif
+
+	RTW_INFO("<== "FUNC_ADPT_FMT" exit....\n", FUNC_ADPT_ARG(padapter));
+	return ret;
+}
+#endif /* #ifdef CONFIG_AP_WOWLAN */
+
+
+int rtw_suspend_normal(_adapter *padapter)
+{
+	int ret = _SUCCESS;
+
+	RTW_INFO("==> "FUNC_ADPT_FMT" entry....\n", FUNC_ADPT_ARG(padapter));
+
+#ifdef CONFIG_BT_COEXIST
+	rtw_btcoex_SuspendNotify(padapter, BTCOEX_SUSPEND_STATE_SUSPEND);
+#endif
+	rtw_mi_netif_caroff_qstop(padapter);
+
+	rtw_mi_suspend_free_assoc_resource(padapter);
+
+	rtw_led_control(padapter, LED_CTL_POWER_OFF);
+
+	if ((rtw_hal_check_ips_status(padapter) == _TRUE)
+	    || (adapter_to_pwrctl(padapter)->rf_pwrstate == rf_off))
+		RTW_PRINT("%s: ### ERROR #### driver in IPS ####ERROR###!!!\n", __FUNCTION__);
+
+
+#ifdef CONFIG_CONCURRENT_MODE
+	rtw_set_drv_stopped(padapter);	/*for stop thread*/
+	rtw_stop_cmd_thread(padapter);
+	rtw_drv_stop_vir_ifaces(adapter_to_dvobj(padapter));
+#endif
+	rtw_dev_unload(padapter);
+
+	#ifdef CONFIG_SDIO_HCI
+	sdio_deinit(adapter_to_dvobj(padapter));
+
+	#if !(CONFIG_RTW_SDIO_KEEP_IRQ)
+	sdio_free_irq(adapter_to_dvobj(padapter));
+	#endif
+	#endif /*CONFIG_SDIO_HCI*/
+
+	RTW_INFO("<== "FUNC_ADPT_FMT" exit....\n", FUNC_ADPT_ARG(padapter));
+	return ret;
+}
+
+int rtw_suspend_common(_adapter *padapter)
+{
+	struct dvobj_priv *dvobj = padapter->dvobj;
+	struct debug_priv *pdbgpriv = &dvobj->drv_dbg;
+	struct pwrctrl_priv *pwrpriv = dvobj_to_pwrctl(dvobj);
+#ifdef CONFIG_WOWLAN
+	struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
+#endif
+
+	int ret = 0;
+	systime start_time = rtw_get_current_time();
+
+	RTW_PRINT(" suspend start\n");
+	RTW_INFO("==> %s (%s:%d)\n", __FUNCTION__, current->comm, current->pid);
+
+	pdbgpriv->dbg_suspend_cnt++;
+
+	pwrpriv->bInSuspend = _TRUE;
+
+	while (pwrpriv->bips_processing == _TRUE)
+		rtw_msleep_os(1);
+
+#ifdef CONFIG_IOL_READ_EFUSE_MAP
+	if (!padapter->bup) {
+		u8 bMacPwrCtrlOn = _FALSE;
+		rtw_hal_get_hwreg(padapter, HW_VAR_APFM_ON_MAC, &bMacPwrCtrlOn);
+		if (bMacPwrCtrlOn)
+			rtw_hal_power_off(padapter);
+	}
+#endif
+
+	if ((!padapter->bup) || RTW_CANNOT_RUN(padapter)) {
+		RTW_INFO("%s bup=%d bDriverStopped=%s bSurpriseRemoved = %s\n", __func__
+			 , padapter->bup
+			 , rtw_is_drv_stopped(padapter) ? "True" : "False"
+			, rtw_is_surprise_removed(padapter) ? "True" : "False");
+		pdbgpriv->dbg_suspend_error_cnt++;
+		goto exit;
+	}
+	rtw_ps_deny(padapter, PS_DENY_SUSPEND);
+
+	rtw_mi_cancel_all_timer(padapter);
+	LeaveAllPowerSaveModeDirect(padapter);
+
+	rtw_ps_deny_cancel(padapter, PS_DENY_SUSPEND);
+
+	if (rtw_mi_check_status(padapter, MI_AP_MODE) == _FALSE) {
+#ifdef CONFIG_WOWLAN
+		if (check_fwstate(pmlmepriv, _FW_LINKED))
+			pwrpriv->wowlan_mode = _TRUE;
+		else if (pwrpriv->wowlan_pno_enable == _TRUE)
+			pwrpriv->wowlan_mode |= pwrpriv->wowlan_pno_enable;
+
+#ifdef CONFIG_P2P_WOWLAN
+		if (!rtw_p2p_chk_state(&padapter->wdinfo, P2P_STATE_NONE) || P2P_ROLE_DISABLE != padapter->wdinfo.role)
+			pwrpriv->wowlan_p2p_mode = _TRUE;
+		if (_TRUE == pwrpriv->wowlan_p2p_mode)
+			pwrpriv->wowlan_mode |= pwrpriv->wowlan_p2p_mode;
+#endif /* CONFIG_P2P_WOWLAN */
+
+		if (pwrpriv->wowlan_mode == _TRUE)
+			rtw_suspend_wow(padapter);
+		else
+#endif /* CONFIG_WOWLAN */
+			rtw_suspend_normal(padapter);
+	} else if (rtw_mi_check_status(padapter, MI_AP_MODE)) {
+#ifdef CONFIG_AP_WOWLAN
+		rtw_suspend_ap_wow(padapter);
+#else
+		rtw_suspend_normal(padapter);
+#endif /*CONFIG_AP_WOWLAN*/
+	}
+
+
+	RTW_PRINT("rtw suspend success in %d ms\n",
+		  rtw_get_passing_time_ms(start_time));
+
+exit:
+	RTW_INFO("<===  %s return %d.............. in %dms\n", __FUNCTION__
+		 , ret, rtw_get_passing_time_ms(start_time));
+
+	return ret;
+}
+
+#ifdef CONFIG_WOWLAN
+int rtw_resume_process_wow(_adapter *padapter)
+{
+	struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
+	struct mlme_ext_priv	*pmlmeext = &padapter->mlmeextpriv;
+	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
+	struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter);
+	struct dvobj_priv *psdpriv = padapter->dvobj;
+	struct debug_priv *pdbgpriv = &psdpriv->drv_dbg;
+	struct wowlan_ioctl_param poidparam;
+	struct sta_info	*psta = NULL;
+	int ret = _SUCCESS;
+
+	RTW_INFO("==> "FUNC_ADPT_FMT" entry....\n", FUNC_ADPT_ARG(padapter));
+
+	if (padapter) {
+		pwrpriv = adapter_to_pwrctl(padapter);
+	} else {
+		pdbgpriv->dbg_resume_error_cnt++;
+		ret = -1;
+		goto exit;
+	}
+
+	if (RTW_CANNOT_RUN(padapter)) {
+		RTW_INFO("%s pdapter %p bDriverStopped %s bSurpriseRemoved %s\n"
+			 , __func__, padapter
+			 , rtw_is_drv_stopped(padapter) ? "True" : "False"
+			, rtw_is_surprise_removed(padapter) ? "True" : "False");
+		goto exit;
+	}
+
+	pwrpriv->wowlan_in_resume = _TRUE;
+#ifdef CONFIG_PNO_SUPPORT
+#ifdef CONFIG_FWLPS_IN_IPS
+	if (pwrpriv->wowlan_pno_enable)
+		rtw_set_fw_in_ips_mode(padapter, _FALSE);
+#endif /* CONFIG_FWLPS_IN_IPS */
+#endif/* CONFIG_PNO_SUPPORT */
+
+	if (pwrpriv->wowlan_mode == _TRUE) {
+#ifdef CONFIG_LPS
+		if (!(pwrpriv->wowlan_dis_lps)) {
+			rtw_set_ps_mode(padapter, PS_MODE_ACTIVE, 0, 0, "WOWLAN");
+			rtw_wow_lps_level_decide(padapter, _FALSE);
+		}
+#endif /* CONFIG_LPS */
+
+		pwrpriv->bFwCurrentInPSMode = _FALSE;
+
+#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_PCI_HCI)
+		rtw_mi_intf_stop(padapter);
+		rtw_hal_clear_interrupt(padapter);
+#endif
+
+		#ifdef CONFIG_SDIO_HCI
+		#if !(CONFIG_RTW_SDIO_KEEP_IRQ)
+		if (sdio_alloc_irq(adapter_to_dvobj(padapter)) != _SUCCESS) {
+			ret = -1;
+			goto exit;
+		}
+		#endif
+		#endif/*CONFIG_SDIO_HCI*/
+
+		/* Disable WOW, set H2C command */
+		poidparam.subcode = WOWLAN_DISABLE;
+		rtw_hal_set_hwreg(padapter, HW_VAR_WOWLAN, (u8 *)&poidparam);
+
+#ifdef CONFIG_CONCURRENT_MODE
+		rtw_mi_buddy_reset_drv_sw(padapter);
+#endif
+
+		psta = rtw_get_stainfo(&padapter->stapriv, get_bssid(&padapter->mlmepriv));
+		if (psta)
+			set_sta_rate(padapter, psta);
+
+
+		rtw_clr_drv_stopped(padapter);
+		RTW_INFO("%s: wowmode resuming, DriverStopped:%s\n", __func__, rtw_is_drv_stopped(padapter) ? "True" : "False");
+
+		rtw_mi_start_drv_threads(padapter);
+
+		rtw_mi_intf_start(padapter);
+
+#ifdef CONFIG_CONCURRENT_MODE
+		rtw_mi_buddy_netif_carrier_on(padapter);
+#endif
+
+		/* start netif queue */
+		rtw_mi_netif_wake_queue(padapter);
+
+	} else
+
+		RTW_PRINT("%s: ### ERROR ### wowlan_mode=%d\n", __FUNCTION__, pwrpriv->wowlan_mode);
+
+	if (padapter->pid[1] != 0) {
+		RTW_INFO("pid[1]:%d\n", padapter->pid[1]);
+		rtw_signal_process(padapter->pid[1], SIGUSR2);
+	}
+
+	if (rtw_chk_roam_flags(padapter, RTW_ROAM_ON_RESUME)) {
+		if (pwrpriv->wowlan_wake_reason == FW_DECISION_DISCONNECT ||
+		    pwrpriv->wowlan_wake_reason == RX_DISASSOC||
+		    pwrpriv->wowlan_wake_reason == RX_DEAUTH) {
+
+			RTW_INFO("%s: disconnect reason: %02x\n", __func__,
+				 pwrpriv->wowlan_wake_reason);
+			rtw_indicate_disconnect(padapter, 0, _FALSE);
+
+			rtw_sta_media_status_rpt(padapter,
+					 rtw_get_stainfo(&padapter->stapriv,
+					 get_bssid(&padapter->mlmepriv)), 0);
+
+			rtw_free_assoc_resources(padapter, _TRUE);
+			pmlmeinfo->state = WIFI_FW_NULL_STATE;
+
+		} else {
+			RTW_INFO("%s: do roaming\n", __func__);
+			rtw_roaming(padapter, NULL);
+		}
+	}
+
+	if (pwrpriv->wowlan_mode == _TRUE) {
+		pwrpriv->bips_processing = _FALSE;
+		_set_timer(&adapter_to_dvobj(padapter)->dynamic_chk_timer, 2000);
+#ifndef CONFIG_IPS_CHECK_IN_WD
+		rtw_set_pwr_state_check_timer(pwrpriv);
+#endif
+	} else
+		RTW_PRINT("do not reset timer\n");
+
+	pwrpriv->wowlan_mode = _FALSE;
+
+	/* Power On LED */
+#ifdef CONFIG_RTW_SW_LED
+
+	if (pwrpriv->wowlan_wake_reason == RX_DISASSOC||
+	    pwrpriv->wowlan_wake_reason == RX_DEAUTH||
+	    pwrpriv->wowlan_wake_reason == FW_DECISION_DISCONNECT)
+		rtw_led_control(padapter, LED_CTL_NO_LINK);
+	else
+		rtw_led_control(padapter, LED_CTL_LINK);
+#endif
+	/* clean driver side wake up reason. */
+	pwrpriv->wowlan_last_wake_reason = pwrpriv->wowlan_wake_reason;
+	pwrpriv->wowlan_wake_reason = 0;
+
+#ifdef CONFIG_BT_COEXIST
+	rtw_btcoex_SuspendNotify(padapter, BTCOEX_SUSPEND_STATE_RESUME);
+#endif /* CONFIG_BT_COEXIST */
+
+exit:
+	RTW_INFO("<== "FUNC_ADPT_FMT" exit....\n", FUNC_ADPT_ARG(padapter));
+	return ret;
+}
+#endif /* #ifdef CONFIG_WOWLAN */
+
+#ifdef CONFIG_AP_WOWLAN
+int rtw_resume_process_ap_wow(_adapter *padapter)
+{
+	struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
+	struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter);
+	struct dvobj_priv *psdpriv = padapter->dvobj;
+	struct debug_priv *pdbgpriv = &psdpriv->drv_dbg;
+	struct wowlan_ioctl_param poidparam;
+	struct sta_info	*psta = NULL;
+	int ret = _SUCCESS;
+	u8 ch, bw, offset;
+
+	RTW_INFO("==> "FUNC_ADPT_FMT" entry....\n", FUNC_ADPT_ARG(padapter));
+
+	if (padapter) {
+		pwrpriv = adapter_to_pwrctl(padapter);
+	} else {
+		pdbgpriv->dbg_resume_error_cnt++;
+		ret = -1;
+		goto exit;
+	}
+
+
+#ifdef CONFIG_LPS
+	if (!(pwrpriv->wowlan_dis_lps)) {
+		rtw_set_ps_mode(padapter, PS_MODE_ACTIVE, 0, 0, "AP-WOWLAN");
+		rtw_wow_lps_level_decide(padapter, _FALSE);
+	}
+#endif /* CONFIG_LPS */
+
+	pwrpriv->bFwCurrentInPSMode = _FALSE;
+
+	rtw_hal_disable_interrupt(padapter);
+
+	rtw_hal_clear_interrupt(padapter);
+
+	#ifdef CONFIG_SDIO_HCI
+	#if !(CONFIG_RTW_SDIO_KEEP_IRQ)
+	if (sdio_alloc_irq(adapter_to_dvobj(padapter)) != _SUCCESS) {
+		ret = -1;
+		goto exit;
+	}
+	#endif
+	#endif/*CONFIG_SDIO_HCI*/
+	/* Disable WOW, set H2C command */
+	poidparam.subcode = WOWLAN_AP_DISABLE;
+	rtw_hal_set_hwreg(padapter, HW_VAR_WOWLAN, (u8 *)&poidparam);
+	pwrpriv->wowlan_ap_mode = _FALSE;
+
+	rtw_clr_drv_stopped(padapter);
+	RTW_INFO("%s: wowmode resuming, DriverStopped:%s\n", __func__, rtw_is_drv_stopped(padapter) ? "True" : "False");
+
+	rtw_mi_start_drv_threads(padapter);
+
+#if 1
+	if (rtw_mi_check_status(padapter, MI_LINKED)) {
+		ch =  rtw_mi_get_union_chan(padapter);
+		bw = rtw_mi_get_union_bw(padapter);
+		offset = rtw_mi_get_union_offset(padapter);
+		RTW_INFO(FUNC_ADPT_FMT" back to linked/linking union - ch:%u, bw:%u, offset:%u\n", FUNC_ADPT_ARG(padapter), ch, bw, offset);
+		set_channel_bwmode(padapter, ch, offset, bw);
+	}
+#else
+	if (rtw_mi_get_ch_setting_union(padapter, &ch, &bw, &offset) != 0) {
+		RTW_INFO(FUNC_ADPT_FMT" back to linked/linking union - ch:%u, bw:%u, offset:%u\n", FUNC_ADPT_ARG(padapter), ch, bw, offset);
+		set_channel_bwmode(padapter, ch, offset, bw);
+		rtw_mi_update_union_chan_inf(padapter, ch, offset, bw);
+	}
+#endif
+
+	/*FOR ONE AP - TODO :Multi-AP*/
+	{
+		int i;
+		_adapter *iface;
+		struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
+
+		for (i = 0; i < dvobj->iface_nums; i++) {
+			iface = dvobj->padapters[i];
+			if ((iface) && rtw_is_adapter_up(iface)) {
+				if (check_fwstate(&iface->mlmepriv, WIFI_AP_STATE | WIFI_MESH_STATE | _FW_LINKED))
+					rtw_reset_drv_sw(iface);
+			}
+		}
+
+	}
+	rtw_mi_intf_start(padapter);
+
+	/* start netif queue */
+	rtw_mi_netif_wake_queue(padapter);
+
+	if (padapter->pid[1] != 0) {
+		RTW_INFO("pid[1]:%d\n", padapter->pid[1]);
+		rtw_signal_process(padapter->pid[1], SIGUSR2);
+	}
+
+#ifdef CONFIG_RESUME_IN_WORKQUEUE
+	/* rtw_unlock_suspend(); */
+#endif /* CONFIG_RESUME_IN_WORKQUEUE */
+
+	pwrpriv->bips_processing = _FALSE;
+	_set_timer(&adapter_to_dvobj(padapter)->dynamic_chk_timer, 2000);
+#ifndef CONFIG_IPS_CHECK_IN_WD
+	rtw_set_pwr_state_check_timer(pwrpriv);
+#endif
+	/* clean driver side wake up reason. */
+	pwrpriv->wowlan_wake_reason = 0;
+
+#ifdef CONFIG_BT_COEXIST
+	rtw_btcoex_SuspendNotify(padapter, BTCOEX_SUSPEND_STATE_RESUME);
+#endif /* CONFIG_BT_COEXIST */
+
+	/* Power On LED */
+#ifdef CONFIG_RTW_SW_LED
+
+	rtw_led_control(padapter, LED_CTL_LINK);
+#endif
+exit:
+	RTW_INFO("<== "FUNC_ADPT_FMT" exit....\n", FUNC_ADPT_ARG(padapter));
+	return ret;
+}
+#endif /* #ifdef CONFIG_APWOWLAN */
+
+void rtw_mi_resume_process_normal(_adapter *padapter)
+{
+	int i;
+	_adapter *iface;
+	struct mlme_priv *pmlmepriv;
+	struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
+
+	for (i = 0; i < dvobj->iface_nums; i++) {
+		iface = dvobj->padapters[i];
+		if ((iface) && rtw_is_adapter_up(iface)) {
+			pmlmepriv = &iface->mlmepriv;
+
+			if (check_fwstate(pmlmepriv, WIFI_STATION_STATE)) {
+				RTW_INFO(FUNC_ADPT_FMT" fwstate:0x%08x - WIFI_STATION_STATE\n", FUNC_ADPT_ARG(iface), get_fwstate(pmlmepriv));
+
+				if (rtw_chk_roam_flags(iface, RTW_ROAM_ON_RESUME))
+					rtw_roaming(iface, NULL);
+
+			} else if (MLME_IS_AP(iface) || MLME_IS_MESH(iface)) {
+				RTW_INFO(FUNC_ADPT_FMT" %s\n", FUNC_ADPT_ARG(iface), MLME_IS_AP(iface) ? "AP" : "MESH");
+				rtw_ap_restore_network(iface);
+			} else if (check_fwstate(pmlmepriv, WIFI_ADHOC_STATE))
+				RTW_INFO(FUNC_ADPT_FMT" fwstate:0x%08x - WIFI_ADHOC_STATE\n", FUNC_ADPT_ARG(iface), get_fwstate(pmlmepriv));
+			else
+				RTW_INFO(FUNC_ADPT_FMT" fwstate:0x%08x - ???\n", FUNC_ADPT_ARG(iface), get_fwstate(pmlmepriv));
+		}
+	}
+}
+
+int rtw_resume_process_normal(_adapter *padapter)
+{
+	struct net_device *pnetdev;
+	struct pwrctrl_priv *pwrpriv;
+	struct dvobj_priv *psdpriv;
+	struct debug_priv *pdbgpriv;
+
+	int ret = _SUCCESS;
+
+	if (!padapter) {
+		ret = -1;
+		goto exit;
+	}
+
+	pnetdev = padapter->pnetdev;
+	pwrpriv = adapter_to_pwrctl(padapter);
+	psdpriv = padapter->dvobj;
+	pdbgpriv = &psdpriv->drv_dbg;
+
+	RTW_INFO("==> "FUNC_ADPT_FMT" entry....\n", FUNC_ADPT_ARG(padapter));
+
+	#ifdef CONFIG_SDIO_HCI
+	/* interface init */
+	if (sdio_init(adapter_to_dvobj(padapter)) != _SUCCESS) {
+		ret = -1;
+		goto exit;
+	}
+	#endif/*CONFIG_SDIO_HCI*/
+
+	rtw_clr_surprise_removed(padapter);
+	rtw_hal_disable_interrupt(padapter);
+
+	#ifdef CONFIG_SDIO_HCI
+	#if !(CONFIG_RTW_SDIO_KEEP_IRQ)
+	if (sdio_alloc_irq(adapter_to_dvobj(padapter)) != _SUCCESS) {
+		ret = -1;
+		goto exit;
+	}
+	#endif
+	#endif/*CONFIG_SDIO_HCI*/
+
+	rtw_mi_reset_drv_sw(padapter);
+
+	pwrpriv->bkeepfwalive = _FALSE;
+
+	RTW_INFO("bkeepfwalive(%x)\n", pwrpriv->bkeepfwalive);
+	if (pm_netdev_open(pnetdev, _TRUE) != 0) {
+		ret = -1;
+		pdbgpriv->dbg_resume_error_cnt++;
+		goto exit;
+	}
+
+	rtw_mi_netif_caron_qstart(padapter);
+
+	if (padapter->pid[1] != 0) {
+		RTW_INFO("pid[1]:%d\n", padapter->pid[1]);
+		rtw_signal_process(padapter->pid[1], SIGUSR2);
+	}
+
+#ifdef CONFIG_BT_COEXIST
+	rtw_btcoex_SuspendNotify(padapter, BTCOEX_SUSPEND_STATE_RESUME);
+#endif /* CONFIG_BT_COEXIST */
+
+	rtw_mi_resume_process_normal(padapter);
+
+#ifdef CONFIG_RESUME_IN_WORKQUEUE
+	/* rtw_unlock_suspend(); */
+#endif /* CONFIG_RESUME_IN_WORKQUEUE */
+	RTW_INFO("<== "FUNC_ADPT_FMT" exit....\n", FUNC_ADPT_ARG(padapter));
+
+exit:
+	return ret;
+}
+
+int rtw_resume_common(_adapter *padapter)
+{
+	int ret = 0;
+	systime start_time = rtw_get_current_time();
+	struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter);
+
+	if (pwrpriv->bInSuspend == _FALSE)
+		return 0;
+
+	RTW_PRINT("resume start\n");
+	RTW_INFO("==> %s (%s:%d)\n", __FUNCTION__, current->comm, current->pid);
+
+	if (rtw_mi_check_status(padapter, WIFI_AP_STATE) == _FALSE) {
+#ifdef CONFIG_WOWLAN
+		if (pwrpriv->wowlan_mode == _TRUE)
+			rtw_resume_process_wow(padapter);
+		else
+#endif
+			rtw_resume_process_normal(padapter);
+
+	} else if (rtw_mi_check_status(padapter, WIFI_AP_STATE)) {
+#ifdef CONFIG_AP_WOWLAN
+		rtw_resume_process_ap_wow(padapter);
+#else
+		rtw_resume_process_normal(padapter);
+#endif /* CONFIG_AP_WOWLAN */
+	}
+
+	if (pwrpriv) {
+		pwrpriv->bInSuspend = _FALSE;
+		pwrpriv->wowlan_in_resume = _FALSE;
+	}
+	RTW_PRINT("%s:%d in %d ms\n", __FUNCTION__ , ret,
+		  rtw_get_passing_time_ms(start_time));
+
+
+	return ret;
+}
+
+#ifdef CONFIG_GPIO_API
+u8 rtw_get_gpio(struct net_device *netdev, u8 gpio_num)
+{
+	_adapter *adapter = (_adapter *)rtw_netdev_priv(netdev);
+	return rtw_hal_get_gpio(adapter, gpio_num);
+}
+EXPORT_SYMBOL(rtw_get_gpio);
+
+int  rtw_set_gpio_output_value(struct net_device *netdev, u8 gpio_num, bool isHigh)
+{
+	u8 direction = 0;
+	u8 res = -1;
+	_adapter *adapter = (_adapter *)rtw_netdev_priv(netdev);
+	return rtw_hal_set_gpio_output_value(adapter, gpio_num, isHigh);
+}
+EXPORT_SYMBOL(rtw_set_gpio_output_value);
+
+int rtw_config_gpio(struct net_device *netdev, u8 gpio_num, bool isOutput)
+{
+	_adapter *adapter = (_adapter *)rtw_netdev_priv(netdev);
+	return rtw_hal_config_gpio(adapter, gpio_num, isOutput);
+}
+EXPORT_SYMBOL(rtw_config_gpio);
+int rtw_register_gpio_interrupt(struct net_device *netdev, int gpio_num, void(*callback)(u8 level))
+{
+	_adapter *adapter = (_adapter *)rtw_netdev_priv(netdev);
+	return rtw_hal_register_gpio_interrupt(adapter, gpio_num, callback);
+}
+EXPORT_SYMBOL(rtw_register_gpio_interrupt);
+
+int rtw_disable_gpio_interrupt(struct net_device *netdev, int gpio_num)
+{
+	_adapter *adapter = (_adapter *)rtw_netdev_priv(netdev);
+	return rtw_hal_disable_gpio_interrupt(adapter, gpio_num);
+}
+EXPORT_SYMBOL(rtw_disable_gpio_interrupt);
+
+#endif /* #ifdef CONFIG_GPIO_API */
+
+#ifdef CONFIG_APPEND_VENDOR_IE_ENABLE
+
+int rtw_vendor_ie_get_api(struct net_device *dev, int ie_num, char *extra,
+		u16 extra_len)
+{
+	int ret = 0;
+
+	ret = rtw_vendor_ie_get_raw_data(dev, ie_num, extra, extra_len);
+	return ret;
+}
+EXPORT_SYMBOL(rtw_vendor_ie_get_api);
+
+int rtw_vendor_ie_set_api(struct net_device *dev, char *extra)
+{
+	return rtw_vendor_ie_set(dev, NULL, NULL, extra);
+}
+EXPORT_SYMBOL(rtw_vendor_ie_set_api);
+
+#endif
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/os_dep/linux/pci_intf.c linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/os_dep/linux/pci_intf.c
--- linux-5.6.3/3rdparty/rtl8821ce/os_dep/linux/pci_intf.c	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/os_dep/linux/pci_intf.c	2020-04-10 16:35:06.856661935 +0300
@@ -0,0 +1,2081 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#define _HCI_INTF_C_
+
+#include <drv_types.h>
+#include <hal_data.h>
+
+#include <linux/pci_regs.h>
+
+#ifndef CONFIG_PCI_HCI
+
+	#error "CONFIG_PCI_HCI shall be on!\n"
+
+#endif
+
+
+#if defined(PLATFORM_LINUX) && defined(PLATFORM_WINDOWS)
+
+	#error "Shall be Linux or Windows, but not both!\n"
+
+#endif
+
+#ifdef CONFIG_80211N_HT
+	extern int rtw_ht_enable;
+	extern int rtw_bw_mode;
+	extern int rtw_ampdu_enable;/* for enable tx_ampdu */
+#endif
+
+#ifdef CONFIG_GLOBAL_UI_PID
+int ui_pid[3] = {0, 0, 0};
+#endif
+
+extern int pm_netdev_open(struct net_device *pnetdev, u8 bnormal);
+int rtw_resume_process(_adapter *padapter);
+
+#ifdef CONFIG_PM
+	static int rtw_pci_suspend(struct pci_dev *pdev, pm_message_t state);
+	static int rtw_pci_resume(struct pci_dev *pdev);
+#endif
+
+static int rtw_drv_init(struct pci_dev *pdev, const struct pci_device_id *pdid);
+static void rtw_dev_remove(struct pci_dev *pdev);
+static void rtw_dev_shutdown(struct pci_dev *pdev);
+
+static struct specific_device_id specific_device_id_tbl[] = {
+	{.idVendor = 0x0b05, .idProduct = 0x1791, .flags = SPEC_DEV_ID_DISABLE_HT},
+	{.idVendor = 0x13D3, .idProduct = 0x3311, .flags = SPEC_DEV_ID_DISABLE_HT},
+	{}
+};
+
+struct pci_device_id rtw_pci_id_tbl[] = {
+#ifdef CONFIG_RTL8188E
+	{PCI_DEVICE(PCI_VENDER_ID_REALTEK, 0x8179), .driver_data = RTL8188E},
+#endif
+#ifdef CONFIG_RTL8812A
+	{PCI_DEVICE(PCI_VENDER_ID_REALTEK, 0x8812), .driver_data = RTL8812},
+#endif
+#ifdef CONFIG_RTL8821A
+	{PCI_DEVICE(PCI_VENDER_ID_REALTEK, 0x8821), .driver_data = RTL8821},
+#endif
+#ifdef CONFIG_RTL8192E
+	{PCI_DEVICE(PCI_VENDER_ID_REALTEK, 0x818B), .driver_data = RTL8192E},
+#endif
+#ifdef CONFIG_RTL8192F
+	{PCI_DEVICE(PCI_VENDER_ID_REALTEK, 0xf192), .driver_data = RTL8192F},
+#endif
+#ifdef CONFIG_RTL8723B
+	{PCI_DEVICE(PCI_VENDER_ID_REALTEK, 0xb723), .driver_data = RTL8723B},
+#endif
+#ifdef CONFIG_RTL8723D
+	{PCI_DEVICE(PCI_VENDER_ID_REALTEK, 0xd723), .driver_data = RTL8723D},
+#endif
+#ifdef CONFIG_RTL8814A
+	{PCI_DEVICE(PCI_VENDER_ID_REALTEK, 0x8813), .driver_data = RTL8814A},
+#endif
+#ifdef CONFIG_RTL8822B
+	{PCI_DEVICE(PCI_VENDER_ID_REALTEK, 0xB822), .driver_data = RTL8822B},
+#endif
+#ifdef CONFIG_RTL8821C
+	{PCI_DEVICE(PCI_VENDER_ID_REALTEK, 0xC821), .driver_data = RTL8821C},
+	{PCI_DEVICE(PCI_VENDER_ID_REALTEK, 0xC82A), .driver_data = RTL8821C},
+	{PCI_DEVICE(PCI_VENDER_ID_REALTEK, 0xC82B), .driver_data = RTL8821C},
+#endif
+
+	{},
+};
+
+struct pci_drv_priv {
+	struct pci_driver rtw_pci_drv;
+	int drv_registered;
+};
+
+
+static struct pci_drv_priv pci_drvpriv = {
+	.rtw_pci_drv.name = (char *)DRV_NAME,
+	.rtw_pci_drv.probe = rtw_drv_init,
+	.rtw_pci_drv.remove = rtw_dev_remove,
+	.rtw_pci_drv.shutdown = rtw_dev_shutdown,
+	.rtw_pci_drv.id_table = rtw_pci_id_tbl,
+#ifdef CONFIG_PM
+	.rtw_pci_drv.suspend = rtw_pci_suspend,
+	.rtw_pci_drv.resume = rtw_pci_resume,
+#endif
+};
+
+
+MODULE_DEVICE_TABLE(pci, rtw_pci_id_tbl);
+
+
+static u16 pcibridge_vendors[PCI_BRIDGE_VENDOR_MAX] = {
+	INTEL_VENDOR_ID,
+	ATI_VENDOR_ID,
+	AMD_VENDOR_ID,
+	SIS_VENDOR_ID
+};
+
+#define PCI_PM_CAP_ID		0x01	/* The Capability ID for PME function */
+void	PlatformClearPciPMEStatus(PADAPTER Adapter)
+{
+	struct dvobj_priv	*pdvobjpriv = adapter_to_dvobj(Adapter);
+	struct pci_dev	*pdev = pdvobjpriv->ppcidev;
+	BOOLEAN		PCIClkReq = _FALSE;
+	u8	CapId = 0xff;
+	u8	CapPointer = 0;
+	/* u16	CapHdr; */
+	RT_PCI_CAPABILITIES_HEADER CapHdr;
+	u8	PMCSReg;
+	int	result;
+
+	/* Get the Capability pointer first, */
+	/* the Capability Pointer is located at offset 0x34 from the Function Header */
+
+	result = pci_read_config_byte(pdev, 0x34, &CapPointer);
+	if (result != 0)
+		RTW_INFO("%s() pci_read_config_byte 0x34 Failed!\n", __func__);
+	else {
+		RTW_INFO("PlatformClearPciPMEStatus(): PCI configration 0x34 = 0x%2x\n", CapPointer);
+		do {
+			/* end of pci capability */
+			if (CapPointer == 0x00) {
+				CapId = 0xff;
+				break;
+			}
+
+			/* result = pci_read_config_word(pdev, CapPointer, &CapHdr); */
+			result = pci_read_config_byte(pdev, CapPointer, &CapHdr.CapabilityID);
+			if (result != 0) {
+				RTW_INFO("%s() pci_read_config_byte %x Failed!\n", __func__, CapPointer);
+				CapId = 0xff;
+				break;
+			}
+
+			result = pci_read_config_byte(pdev, CapPointer + 1, &CapHdr.Next);
+			if (result != 0) {
+				RTW_INFO("%s() pci_read_config_byte %x Failed!\n", __func__, CapPointer);
+				CapId = 0xff;
+				break;
+			}
+
+			/* CapId = CapHdr & 0xFF; */
+			CapId = CapHdr.CapabilityID;
+
+			RTW_INFO("PlatformClearPciPMEStatus(): in pci configration1, CapPointer%x = %x\n", CapPointer, CapId);
+
+			if (CapId == PCI_PM_CAP_ID)
+				break;
+			else {
+				/* point to next Capability */
+				/* CapPointer = (CapHdr >> 8) & 0xFF; */
+				CapPointer = CapHdr.Next;
+			}
+		} while (_TRUE);
+
+		if (CapId == PCI_PM_CAP_ID) {
+			/* Get the PM CSR (Control/Status Register), */
+			/* The PME_Status is located at PM Capatibility offset 5, bit 7 */
+			result = pci_read_config_byte(pdev, CapPointer + 5, &PMCSReg);
+			if (PMCSReg & BIT7) {
+				/* PME event occured, clear the PM_Status by write 1 */
+				PMCSReg = PMCSReg | BIT7;
+
+				pci_write_config_byte(pdev, CapPointer + 5, PMCSReg);
+				PCIClkReq = _TRUE;
+				/* Read it back to check */
+				pci_read_config_byte(pdev, CapPointer + 5, &PMCSReg);
+				RTW_INFO("PlatformClearPciPMEStatus(): Clear PME status 0x%2x to 0x%2x\n", CapPointer + 5, PMCSReg);
+			} else
+				RTW_INFO("PlatformClearPciPMEStatus(): PME status(0x%2x) = 0x%2x\n", CapPointer + 5, PMCSReg);
+		} else
+			RTW_INFO("PlatformClearPciPMEStatus(): Cannot find PME Capability\n");
+	}
+
+	RTW_INFO("PME, value_offset = %x, PME EN = %x\n", CapPointer + 5, PCIClkReq);
+}
+
+void rtw_pci_aspm_config_clkreql0sl1(_adapter *padapter)
+{
+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(padapter);
+	u8 tmp8 = 0;
+	u16 tmp16 = 0;
+
+	/* 0x70f Bit7 for L0s */
+	tmp8 = rtw_hal_pci_dbi_read(padapter, 0x70f);
+
+	if (pHalData->pci_backdoor_ctrl & PCI_BC_ASPM_L0s)
+		tmp8 |= BIT7;
+	else
+		tmp8 &= (~BIT7);
+
+	/* Default set L1 entrance latency to 16us */
+	/* L0s: b[0-2], L1: b[3-5]*/
+	if (pHalData->pci_backdoor_ctrl & PCI_BC_ASPM_L1) {
+		tmp8 &= (~0x38);
+		tmp8 |= 0x20;
+#ifdef CONFIG_PCI_DYNAMIC_ASPM
+		pHalData->bAspmL1LastIdle = 1;
+#endif
+	}
+
+	rtw_hal_pci_dbi_write(padapter, 0x70f, tmp8);
+
+
+	/* 0x719 Bit 3 for L1 ,  Bit4 for clock req */
+	tmp8 = rtw_hal_pci_dbi_read(padapter, 0x719);
+
+	if (pHalData->pci_backdoor_ctrl & PCI_BC_ASPM_L1)
+		tmp8 |= BIT3;
+	else
+		tmp8 &= (~BIT3);
+
+	if (pHalData->pci_backdoor_ctrl & PCI_BC_CLK_REQ)
+		tmp8 |= BIT4;
+	else
+		tmp8 &= (~BIT4);
+
+	rtw_hal_pci_dbi_write(padapter, 0x719, tmp8);
+
+	if (pHalData->pci_backdoor_ctrl & PCI_BC_CLK_REQ) {
+		tmp16 = rtw_hal_pci_mdio_read(padapter, 0x10);
+		rtw_hal_pci_mdio_write(padapter, 0x10, (tmp16 | BIT2));
+	}
+}
+
+void rtw_pci_aspm_config_l1off(_adapter *padapter)
+{
+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(padapter);
+
+	u8 enable_l1off = _FALSE;
+
+	if (pHalData->pci_backdoor_ctrl & PCI_BC_ASPM_L1Off)
+		enable_l1off = rtw_hal_pci_l1off_nic_support(padapter);
+
+	padapter->hal_func.hal_set_l1ssbackdoor_handler(padapter, enable_l1off);
+
+}
+
+void rtw_pci_aspm_config_l1off_general(_adapter *padapter, u8 enablel1off)
+{
+
+	u8 tmp8;
+	u16 tmp16;
+
+	if (enablel1off) {
+		/* 0x718 Bit5 for L1SS */
+		tmp8 = rtw_hal_pci_dbi_read(padapter, 0x718);
+		rtw_hal_pci_dbi_write(padapter, 0x718, (tmp8 | BIT5));
+
+		tmp16 = rtw_hal_pci_mdio_read(padapter, 0x1b);
+		rtw_hal_pci_mdio_write(padapter, 0x1b, (tmp16 | BIT4));
+	} else {
+		tmp8 = rtw_hal_pci_dbi_read(padapter, 0x718);
+		rtw_hal_pci_dbi_write(padapter, 0x718, (tmp8 & (~BIT5)));
+	}
+
+}
+
+#ifdef CONFIG_PCI_DYNAMIC_ASPM
+void rtw_pci_aspm_config_dynamic_l1_ilde_time(_adapter *padapter)
+{
+	BOOLEAN	 bCurrentIdle = 1;	/* Default idle 4us (0x70F = 0x17)*/
+	HAL_DATA_TYPE *pHalData	= GET_HAL_DATA(padapter);
+	struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
+	struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(padapter);
+	int current_tx_tp = pdvobjpriv->traffic_stat.cur_tx_tp;
+	int current_rx_tp = pdvobjpriv->traffic_stat.cur_rx_tp;
+	int current_tp = current_tx_tp + current_rx_tp;
+	u8 tmp8 = 0;
+
+	if (padapter->registrypriv.wifi_spec)
+		return;
+
+	if (!(pHalData->pci_backdoor_ctrl & PCI_BC_ASPM_L1))
+		return;
+
+#if 0
+	RTW_INFO("current_tx_tp = %d\n", current_tx_tp);
+	RTW_INFO("current_rx_tp = %d\n", current_rx_tp);
+	RTW_INFO("current_tp = %d\n", current_tp);
+#endif
+
+	if ((rtw_linked_check(padapter) == _TRUE) && 
+		((current_tx_tp >= 50)||
+		(current_rx_tp >= 50)))
+		/*(current_rx_tp >= 10))*/
+		/*(current_tp >= 10))*/
+	{
+		bCurrentIdle = 0;
+	}	
+	else
+	{
+		bCurrentIdle = 1;
+	}
+
+	if(bCurrentIdle != pHalData->bAspmL1LastIdle)
+	{
+		pHalData->bAspmL1LastIdle = bCurrentIdle;
+
+		tmp8 = rtw_hal_pci_dbi_read(padapter, 0x70F);
+		tmp8 &= (~0x38);
+
+		if(bCurrentIdle) {
+			/*tmp8 |= 0x10; *//*L1 entrance latency: 4us*/
+			/*tmp8 |= 0x18; *//*L1 entrance latency: 8us*/
+			tmp8 |= 0x20; /*L1 entrance latency: 16us*/
+			rtw_hal_pci_dbi_write(padapter, 0x70F, tmp8 );
+		}
+		else {
+			tmp8 |= 0x28; /*L1 entrance latency: 32us*/
+			rtw_hal_pci_dbi_write(padapter, 0x70F, tmp8 );
+		}
+	}
+
+}
+#endif
+
+void rtw_pci_dump_aspm_info(_adapter *padapter)
+{
+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(padapter);
+	struct dvobj_priv	*pdvobjpriv = adapter_to_dvobj(padapter);
+	struct pci_priv	*pcipriv = &(pdvobjpriv->pcipriv);
+	u8 tmp8 = 0;
+	u16 tmp16 = 0;
+	u32 tmp32 = 0;
+	u8 l1_idle = 0;
+
+
+	RTW_INFO("***** ASPM Capability *****\n");
+
+	pci_read_config_dword(pdvobjpriv->ppcidev, pcipriv->pciehdr_offset + PCI_EXP_LNKCAP, &tmp32);
+
+	RTW_INFO("CLK REQ:	%s\n", (tmp32&PCI_EXP_LNKCAP_CLKPM) ? "Enable" : "Disable");
+
+	RTW_INFO("ASPM L0s:	%s\n", (tmp32&BIT10) ? "Enable" : "Disable");
+	RTW_INFO("ASPM L1:	%s\n", (tmp32&BIT11) ? "Enable" : "Disable");
+
+	tmp8 = rtw_hal_pci_l1off_capability(padapter);
+	RTW_INFO("ASPM L1OFF:%s\n", tmp8 ? "Enable" : "Disable");
+
+	RTW_INFO("***** ASPM CTRL Reg *****\n");
+
+	pci_read_config_word(pdvobjpriv->ppcidev, pcipriv->pciehdr_offset + PCI_EXP_LNKCTL, &tmp16);
+
+	RTW_INFO("CLK REQ:	%s\n", (tmp16&PCI_EXP_LNKCTL_CLKREQ_EN) ? "Enable" : "Disable");
+	RTW_INFO("ASPM L0s:	%s\n", (tmp16&BIT0) ? "Enable" : "Disable");
+	RTW_INFO("ASPM L1:	%s\n", (tmp16&BIT1) ? "Enable" : "Disable");
+
+	tmp8 = rtw_hal_pci_l1off_nic_support(padapter);
+	RTW_INFO("ASPM L1OFF:%s\n", tmp8 ? "Enable" : "Disable");
+
+	RTW_INFO("***** ASPM Backdoor *****\n");
+
+	tmp8 = rtw_hal_pci_dbi_read(padapter, 0x719);
+	RTW_INFO("CLK REQ:	%s\n", (tmp8 & BIT4) ? "Enable" : "Disable");
+
+	tmp8 = rtw_hal_pci_dbi_read(padapter, 0x70f);
+	l1_idle = tmp8 & 0x38;
+	RTW_INFO("ASPM L0s:	%s\n", (tmp8&BIT7) ? "Enable" : "Disable");
+
+	tmp8 = rtw_hal_pci_dbi_read(padapter, 0x719);
+	RTW_INFO("ASPM L1:	%s\n", (tmp8 & BIT3) ? "Enable" : "Disable");
+
+	tmp8 = rtw_hal_pci_dbi_read(padapter, 0x718);
+	RTW_INFO("ASPM L1OFF:%s\n", (tmp8 & BIT5) ? "Enable" : "Disable");
+	
+	RTW_INFO("********* MISC **********\n");
+	RTW_INFO("ASPM L1 Idel Time: 0x%x\n", l1_idle>>3);
+	RTW_INFO("*************************\n");
+}
+
+void rtw_pci_aspm_config(_adapter *padapter)
+{
+	rtw_pci_aspm_config_clkreql0sl1(padapter);
+	rtw_pci_aspm_config_l1off(padapter);
+	rtw_pci_dump_aspm_info(padapter);
+}
+
+static u8 rtw_pci_platform_switch_device_pci_aspm(_adapter *padapter, u8 value)
+{
+	struct dvobj_priv	*pdvobjpriv = adapter_to_dvobj(padapter);
+	struct pci_priv	*pcipriv = &(pdvobjpriv->pcipriv);
+	BOOLEAN		bResult = _FALSE;
+	int	Result = 0;
+	int	error;
+
+	Result = pci_write_config_byte(pdvobjpriv->ppcidev, pcipriv->pciehdr_offset + 0x10, value);	/* enable I/O space */
+	RTW_INFO("PlatformSwitchDevicePciASPM(0x%x) = 0x%x\n", pcipriv->pciehdr_offset + 0x10, value);
+	if (Result != 0) {
+		RTW_INFO("PlatformSwitchDevicePciASPM() Failed!\n");
+		bResult = _FALSE;
+	} else
+		bResult = _TRUE;
+
+	return bResult;
+}
+
+/*
+ * When we set 0x01 to enable clk request. Set 0x0 to disable clk req.
+ */
+static u8 rtw_pci_switch_clk_req(_adapter *padapter, u8 value)
+{
+	struct dvobj_priv	*pdvobjpriv = adapter_to_dvobj(padapter);
+	u8	buffer, bResult = _FALSE;
+	int	error;
+
+	buffer = value;
+
+	if (!rtw_is_hw_init_completed(padapter))
+		return bResult;
+
+	/* the clock request is located at offset 0x81, suppose the PCIE Capability register is located at offset 0x70 */
+	/* the correct code should be: search the PCIE capability register first and then the clock request is located offset 0x11 */
+	error = pci_write_config_byte(pdvobjpriv->ppcidev, 0x81, buffer);
+	if (error != 0)
+		RTW_INFO("rtw_pci_switch_clk_req error (%d)\n", error);
+	else
+		bResult = _TRUE;
+
+	return bResult;
+}
+
+/*Disable RTL8192SE ASPM & Disable Pci Bridge ASPM*/
+void rtw_pci_disable_aspm(_adapter *padapter)
+{
+	struct dvobj_priv	*pdvobjpriv = adapter_to_dvobj(padapter);
+	struct pwrctrl_priv	*pwrpriv = dvobj_to_pwrctl(pdvobjpriv);
+	struct pci_dev	*pdev = pdvobjpriv->ppcidev;
+	struct pci_dev	*bridge_pdev = pdev->bus->self;
+	struct pci_priv	*pcipriv = &(pdvobjpriv->pcipriv);
+	u8	linkctrl_reg;
+	u8	pcibridge_linkctrlreg, aspmlevel = 0;
+
+
+	/* We shall check RF Off Level for ASPM function instead of registry settings, revised by Roger, 2013.03.29. */
+	if (!(pwrpriv->reg_rfps_level & (RT_RF_LPS_LEVEL_ASPM | RT_RF_PS_LEVEL_ALWAYS_ASPM)))
+		return;
+
+	if (!rtw_is_hw_init_completed(padapter))
+		return;
+
+	if (pcipriv->pcibridge_vendor == PCI_BRIDGE_VENDOR_UNKNOWN)
+		return;
+
+	linkctrl_reg = pcipriv->linkctrl_reg;
+	pcibridge_linkctrlreg = pcipriv->pcibridge_linkctrlreg;
+
+	/* Set corresponding value. */
+	aspmlevel |= BIT(0) | BIT(1);
+	linkctrl_reg &= ~aspmlevel;
+	pcibridge_linkctrlreg &= ~aspmlevel;
+
+	/*  */
+	/* 09/08/21 MH From Sd1 suggestion. we need to adjust ASPM enable sequence */
+	/* CLK_REQ ==> delay 50us ==> Device ==> Host ==> delay 50us */
+	/*  */
+
+	if (pwrpriv->reg_rfps_level & RT_RF_OFF_LEVL_CLK_REQ) {
+		RT_CLEAR_PS_LEVEL(pwrpriv, RT_RF_OFF_LEVL_CLK_REQ);
+		rtw_pci_switch_clk_req(padapter, 0x0);
+	}
+
+	{
+		/*for promising device will in L0 state after an I/O.*/
+		u8 tmp_u1b;
+
+		pci_read_config_byte(pdev, (pcipriv->pciehdr_offset + 0x10), &tmp_u1b);
+	}
+
+	rtw_pci_platform_switch_device_pci_aspm(padapter, linkctrl_reg);
+
+	rtw_udelay_os(50);
+
+	/* When there exists anyone's BusNum, DevNum, and FuncNum that are set to 0xff, */
+	/* we do not execute any action and return. Added by tynli. */
+	if ((pcipriv->busnumber == 0xff && pcipriv->devnumber == 0xff && pcipriv->funcnumber == 0xff) ||
+	    (pcipriv->pcibridge_busnum == 0xff && pcipriv->pcibridge_devnum == 0xff && pcipriv->pcibridge_funcnum == 0xff)) {
+		/* Do Nothing!! */
+	} else {
+		/* 4  */ /* Disable Pci Bridge ASPM */
+		pci_write_config_byte(bridge_pdev, (pcipriv->pcibridge_pciehdr_offset + 0x10), pcibridge_linkctrlreg);
+		RTW_INFO("PlatformDisableASPM():PciBridge Write reg[%x] = %x\n",
+			(pcipriv->pcibridge_pciehdr_offset + 0x10), pcibridge_linkctrlreg);
+		rtw_udelay_os(50);
+	}
+
+}
+
+/*Enable RTL8192SE ASPM & Enable Pci Bridge ASPM for
+ * power saving We should follow the sequence to enable
+ * RTL8192SE first then enable Pci Bridge ASPM
+ * or the system will show bluescreen.
+*/
+void rtw_pci_enable_aspm(_adapter *padapter)
+{
+	struct dvobj_priv	*pdvobjpriv = adapter_to_dvobj(padapter);
+	struct pwrctrl_priv	*pwrpriv = dvobj_to_pwrctl(pdvobjpriv);
+	struct pci_dev	*pdev = pdvobjpriv->ppcidev;
+	struct pci_dev	*bridge_pdev = pdev->bus->self;
+	struct pci_priv	*pcipriv = &(pdvobjpriv->pcipriv);
+	u16	aspmlevel = 0;
+	u8	u_pcibridge_aspmsetting = 0;
+	u8	u_device_aspmsetting = 0;
+	u32	u_device_aspmsupportsetting = 0;
+
+
+	/* We shall check RF Off Level for ASPM function instead of registry settings, revised by Roger, 2013.03.29. */
+	if (!(pwrpriv->reg_rfps_level & (RT_RF_LPS_LEVEL_ASPM | RT_RF_PS_LEVEL_ALWAYS_ASPM)))
+		return;
+
+	/* When there exists anyone's BusNum, DevNum, and FuncNum that are set to 0xff, */
+	/* we do not execute any action and return. Added by tynli. */
+	if ((pcipriv->busnumber == 0xff && pcipriv->devnumber == 0xff && pcipriv->funcnumber == 0xff) ||
+	    (pcipriv->pcibridge_busnum == 0xff && pcipriv->pcibridge_devnum == 0xff && pcipriv->pcibridge_funcnum == 0xff)) {
+		RTW_INFO("rtw_pci_enable_aspm(): Fail to enable ASPM. Cannot find the Bus of PCI(Bridge).\n");
+		return;
+	}
+
+	/* Get Bridge ASPM Support
+	 * not to enable bridge aspm if bridge does not support
+	 * Added by sherry 20100803
+	*/
+	{
+		/* Get the Link Capability, it ls located at offset 0x0c from the PCIE Capability */
+		pci_read_config_dword(bridge_pdev, (pcipriv->pcibridge_pciehdr_offset + 0x0C), &u_device_aspmsupportsetting);
+
+		RTW_INFO("rtw_pci_enable_aspm(): Bridge ASPM support %x\n", u_device_aspmsupportsetting);
+		if (((u_device_aspmsupportsetting & BIT(11)) != BIT(11)) || ((u_device_aspmsupportsetting & BIT(10)) != BIT(10))) {
+			if (pdvobjpriv->const_devicepci_aspm_setting == 3) {
+				RTW_INFO("rtw_pci_enable_aspm(): Bridge not support L0S or L1\n");
+				return;
+			} else if (pdvobjpriv->const_devicepci_aspm_setting == 2) {
+				if ((u_device_aspmsupportsetting & BIT(11)) != BIT(11)) {
+					RTW_INFO("rtw_pci_enable_aspm(): Bridge not support L1\n");
+					return;
+				}
+			} else if (pdvobjpriv->const_devicepci_aspm_setting == 1) {
+				if ((u_device_aspmsupportsetting & BIT(10)) != BIT(10)) {
+					RTW_INFO("rtw_pci_enable_aspm(): Bridge not support L0s\n");
+					return;
+				}
+
+			}
+		} else
+			RTW_INFO("rtw_pci_enable_aspm(): Bridge support L0s and L1\n");
+	}
+
+	/*
+	* Skip following settings if ASPM has already enabled, added by Roger, 2013.03.15.
+	*/
+	if ((pcipriv->pcibridge_linkctrlreg & (BIT0 | BIT1)) &&
+	    (pcipriv->linkctrl_reg & (BIT0 | BIT1))) {
+		/* BIT0: L0S, BIT1:L1 */
+
+		RTW_INFO("PlatformEnableASPM(): ASPM is already enabled, skip incoming settings!!\n");
+		return;
+	}
+
+	/* 4 Enable Pci Bridge ASPM */
+	/* Write PCI bridge PCIE-capability Link Control Register */
+	/* Justin: Can we change the ASPM Control register ? */
+	/* The system BIOS should set this register with a correct value */
+	/* If we change the force enable the ASPM L1/L0s, this may cause the system hang */
+	u_pcibridge_aspmsetting = pcipriv->pcibridge_linkctrlreg;
+	u_pcibridge_aspmsetting |= pdvobjpriv->const_hostpci_aspm_setting;
+
+	if (pcipriv->pcibridge_vendor == PCI_BRIDGE_VENDOR_INTEL ||
+	    pcipriv->pcibridge_vendor == PCI_BRIDGE_VENDOR_SIS)
+		u_pcibridge_aspmsetting &= ~BIT(0); /* for intel host 42 device 43 */
+
+	pci_write_config_byte(bridge_pdev, (pcipriv->pcibridge_pciehdr_offset + 0x10), u_pcibridge_aspmsetting);
+	RTW_INFO("PlatformEnableASPM():PciBridge Write reg[%x] = %x\n",
+		 (pcipriv->pcibridge_pciehdr_offset + 0x10),
+		 u_pcibridge_aspmsetting);
+
+	rtw_udelay_os(50);
+
+	/*Get ASPM level (with/without Clock Req)*/
+	aspmlevel |= pdvobjpriv->const_devicepci_aspm_setting;
+	u_device_aspmsetting = pcipriv->linkctrl_reg;
+	u_device_aspmsetting |= aspmlevel; /* device 43 */
+
+	rtw_pci_platform_switch_device_pci_aspm(padapter, u_device_aspmsetting);
+
+	if (pwrpriv->reg_rfps_level & RT_RF_OFF_LEVL_CLK_REQ) {
+		rtw_pci_switch_clk_req(padapter, (pwrpriv->reg_rfps_level & RT_RF_OFF_LEVL_CLK_REQ) ? 1 : 0);
+		RT_SET_PS_LEVEL(pwrpriv, RT_RF_OFF_LEVL_CLK_REQ);
+	}
+
+	rtw_udelay_os(50);
+}
+
+static u8 rtw_pci_get_amd_l1_patch(struct dvobj_priv *pdvobjpriv, struct pci_dev *pdev)
+{
+	u8	status = _FALSE;
+	u8	offset_e0;
+	u32	offset_e4;
+
+	pci_write_config_byte(pdev, 0xE0, 0xA0);
+	pci_read_config_byte(pdev, 0xE0, &offset_e0);
+
+	if (offset_e0 == 0xA0) {
+		pci_read_config_dword(pdev, 0xE4, &offset_e4);
+		if (offset_e4 & BIT(23))
+			status = _TRUE;
+	}
+
+	return status;
+}
+
+static s32	rtw_pci_get_linkcontrol_reg(struct pci_dev *pdev, u8 *LinkCtrlReg, u8 *HdrOffset)
+{
+	u8 CapabilityPointer;
+	RT_PCI_CAPABILITIES_HEADER	CapabilityHdr;
+	s32 status = _FAIL;
+
+	/* get CapabilityOffset */
+	pci_read_config_byte(pdev, 0x34, &CapabilityPointer);	/* the capability pointer is located offset 0x34 */
+
+	/* Loop through the capabilities in search of the power management capability. */
+	/* The list is NULL-terminated, so the last offset will always be zero. */
+
+	while (CapabilityPointer != 0) {
+		/* Read the header of the capability at  this offset. If the retrieved capability is not */
+		/* the power management capability that we are looking for, follow the link to the  */
+		/* next capability and continue looping. */
+
+		/* 4 get CapabilityHdr */
+		/* pci_read_config_word(pdev, CapabilityPointer, (u16 *)&CapabilityHdr); */
+		pci_read_config_byte(pdev, CapabilityPointer, (u8 *)&CapabilityHdr.CapabilityID);
+		pci_read_config_byte(pdev, CapabilityPointer + 1, (u8 *)&CapabilityHdr.Next);
+
+		/* Found the PCI express capability */
+		if (CapabilityHdr.CapabilityID == PCI_CAPABILITY_ID_PCI_EXPRESS)
+			break;
+		else {
+			/* This is some other capability. Keep looking for the PCI express capability. */
+			CapabilityPointer = CapabilityHdr.Next;
+		}
+	}
+
+	/* Get the Link Control Register, it located at offset 0x10 from the Capability Header */
+	if (CapabilityHdr.CapabilityID == PCI_CAPABILITY_ID_PCI_EXPRESS) {
+		*HdrOffset = CapabilityPointer;
+		pci_read_config_byte(pdev, CapabilityPointer + 0x10, LinkCtrlReg);
+
+		status = _SUCCESS;
+	} else {
+		/* We didn't find a PCIe capability. */
+		RTW_INFO("GetPciLinkCtrlReg(): Cannot Find PCIe Capability\n");
+	}
+
+	return status;
+}
+
+static s32	rtw_set_pci_cache_line_size(struct pci_dev *pdev, u8 CacheLineSizeToSet)
+{
+	u8	ucPciCacheLineSize;
+	s32	Result;
+
+	/* ucPciCacheLineSize  = pPciConfig->CacheLineSize; */
+	pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &ucPciCacheLineSize);
+
+	if (ucPciCacheLineSize < 8 || ucPciCacheLineSize > 16) {
+		RTW_INFO("Driver Sets default Cache Line Size...\n");
+
+		ucPciCacheLineSize = CacheLineSizeToSet;
+
+		Result = pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, ucPciCacheLineSize);
+
+		if (Result != 0) {
+			RTW_INFO("pci_write_config_byte (CacheLineSize) Result=%d\n", Result);
+			goto _SET_CACHELINE_SIZE_FAIL;
+		}
+
+		Result = pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &ucPciCacheLineSize);
+		if (Result != 0) {
+			RTW_INFO("pci_read_config_byte (PciCacheLineSize) Result=%d\n", Result);
+			goto _SET_CACHELINE_SIZE_FAIL;
+		}
+
+		if (ucPciCacheLineSize != CacheLineSizeToSet) {
+			RTW_INFO("Failed to set Cache Line Size to 0x%x! ucPciCacheLineSize=%x\n", CacheLineSizeToSet, ucPciCacheLineSize);
+			goto _SET_CACHELINE_SIZE_FAIL;
+		}
+	}
+
+	return _SUCCESS;
+
+_SET_CACHELINE_SIZE_FAIL:
+
+	return _FAIL;
+}
+
+
+#define PCI_CMD_ENABLE_BUS_MASTER		BIT(2)
+#define PCI_CMD_DISABLE_INTERRUPT		BIT(10)
+#define CMD_BUS_MASTER				BIT(2)
+
+static s32 rtw_pci_parse_configuration(struct pci_dev *pdev, struct dvobj_priv *pdvobjpriv)
+{
+	struct pci_priv	*pcipriv = &(pdvobjpriv->pcipriv);
+	/* PPCI_COMMON_CONFIG pPciConfig = (PPCI_COMMON_CONFIG) pucBuffer; */
+	/* u16	usPciCommand = pPciConfig->Command; */
+	u16	usPciCommand = 0;
+	int	Result, ret = _FAIL;
+	u8	CapabilityOffset;
+	RT_PCI_CAPABILITIES_HEADER CapabilityHdr;
+	u8	PCIeCap;
+	u8	LinkCtrlReg;
+	u8	ClkReqReg;
+
+	/* RTW_INFO("%s==>\n", __func__); */
+
+	pci_read_config_word(pdev, PCI_COMMAND, &usPciCommand);
+
+	do {
+		/* 3 Enable bus matering if it isn't enabled by the BIOS */
+		if (!(usPciCommand & PCI_CMD_ENABLE_BUS_MASTER)) {
+			RTW_INFO("Bus master is not enabled by BIOS! usPciCommand=%x\n", usPciCommand);
+
+			usPciCommand |= CMD_BUS_MASTER;
+
+			Result = pci_write_config_word(pdev, PCI_COMMAND, usPciCommand);
+			if (Result != 0) {
+				RTW_INFO("pci_write_config_word (Command) Result=%d\n", Result);
+				ret = _FAIL;
+				break;
+			}
+
+			Result = pci_read_config_word(pdev, PCI_COMMAND, &usPciCommand);
+			if (Result != 0) {
+				RTW_INFO("pci_read_config_word (Command) Result=%d\n", Result);
+				ret = _FAIL;
+				break;
+			}
+
+			if (!(usPciCommand & PCI_CMD_ENABLE_BUS_MASTER)) {
+				RTW_INFO("Failed to enable bus master! usPciCommand=%x\n", usPciCommand);
+				ret = _FAIL;
+				break;
+			}
+		}
+		RTW_INFO("Bus master is enabled. usPciCommand=%x\n", usPciCommand);
+
+		/* 3 Enable interrupt */
+		if ((usPciCommand & PCI_CMD_DISABLE_INTERRUPT)) {
+			RTW_INFO("INTDIS==1 usPciCommand=%x\n", usPciCommand);
+
+			usPciCommand &= (~PCI_CMD_DISABLE_INTERRUPT);
+
+			Result = pci_write_config_word(pdev, PCI_COMMAND, usPciCommand);
+			if (Result != 0) {
+				RTW_INFO("pci_write_config_word (Command) Result=%d\n", Result);
+				ret = _FAIL;
+				break;
+			}
+
+			Result = pci_read_config_word(pdev, PCI_COMMAND, &usPciCommand);
+			if (Result != 0) {
+				RTW_INFO("pci_read_config_word (Command) Result=%d\n", Result);
+				ret = _FAIL;
+				break;
+			}
+
+			if ((usPciCommand & PCI_CMD_DISABLE_INTERRUPT)) {
+				RTW_INFO("Failed to set INTDIS to 0! usPciCommand=%x\n", usPciCommand);
+				ret = _FAIL;
+				break;
+			}
+		}
+
+		/*  */
+		/* Description: Find PCI express capability offset. Porting from 818xB by tynli 2008.12.19 */
+		/*  */
+		/* ------------------------------------------------------------- */
+
+		/* 3 PCIeCap */
+		/* The device supports capability lists. Find the capabilities. */
+
+		/* CapabilityOffset = pPciConfig->u.type0.CapabilitiesPtr; */
+		pci_read_config_byte(pdev, PCI_CAPABILITY_LIST, &CapabilityOffset);
+
+		/* Loop through the capabilities in search of the power management capability. */
+		/* The list is NULL-terminated, so the last offset will always be zero. */
+
+		while (CapabilityOffset != 0) {
+			/* Read the header of the capability at  this offset. If the retrieved capability is not */
+			/* the power management capability that we are looking for, follow the link to the */
+			/* next capability and continue looping. */
+
+			/* Result = pci_read_config_word(pdev, CapabilityOffset, (u16 *)&CapabilityHdr); */
+			Result = pci_read_config_byte(pdev, CapabilityOffset, (u8 *)&CapabilityHdr.CapabilityID);
+			if (Result != 0)
+				break;
+
+			Result = pci_read_config_byte(pdev, CapabilityOffset + 1, (u8 *)&CapabilityHdr.Next);
+			if (Result != 0)
+				break;
+
+			/* Found the PCI express capability */
+			if (CapabilityHdr.CapabilityID == PCI_CAPABILITY_ID_PCI_EXPRESS)
+				break;
+			else {
+				/* This is some other capability. Keep looking for the PCI express capability. */
+				CapabilityOffset = CapabilityHdr.Next;
+			}
+		}
+
+		if (Result != 0) {
+			RTW_INFO("pci_read_config_word (RT_PCI_CAPABILITIES_HEADER) Result=%d\n", Result);
+			break;
+		}
+
+		if (CapabilityHdr.CapabilityID == PCI_CAPABILITY_ID_PCI_EXPRESS) {
+			pcipriv->pciehdr_offset = CapabilityOffset;
+			RTW_INFO("PCIe Header Offset =%x\n", CapabilityOffset);
+
+			/* Skip past the capabilities header and read the PCI express capability */
+			/* Justin: The PCI-e capability size should be 2 bytes, why we just get 1 byte */
+			/* Beside, this PCIeCap seems no one reference it in the driver code */
+			Result = pci_read_config_byte(pdev, CapabilityOffset + 2, &PCIeCap);
+
+			if (Result != 0) {
+				RTW_INFO("pci_read_config_byte (PCIE Capability) Result=%d\n", Result);
+				break;
+			}
+
+			pcipriv->pcie_cap = PCIeCap;
+			RTW_INFO("PCIe Capability =%x\n", PCIeCap);
+
+			/* 3 Link Control Register */
+			/* Read "Link Control Register" Field (80h ~81h) */
+			Result = pci_read_config_byte(pdev, CapabilityOffset + 0x10, &LinkCtrlReg);
+			if (Result != 0) {
+				RTW_INFO("pci_read_config_byte (Link Control Register) Result=%d\n", Result);
+				break;
+			}
+
+			pcipriv->linkctrl_reg = LinkCtrlReg;
+			RTW_INFO("Link Control Register =%x\n", LinkCtrlReg);
+
+			/* 3 Get Capability of PCI Clock Request */
+			/* The clock request setting is located at 0x81[0] */
+			Result = pci_read_config_byte(pdev, CapabilityOffset + 0x11, &ClkReqReg);
+			if (Result != 0) {
+				pcipriv->pci_clk_req = _FALSE;
+				RTW_INFO("pci_read_config_byte (Clock Request Register) Result=%d\n", Result);
+				break;
+			}
+			if (ClkReqReg & BIT(0))
+				pcipriv->pci_clk_req = _TRUE;
+			else
+				pcipriv->pci_clk_req = _FALSE;
+			RTW_INFO("Clock Request =%x\n", pcipriv->pci_clk_req);
+		} else {
+			/* We didn't find a PCIe capability. */
+			RTW_INFO("Didn't Find PCIe Capability\n");
+			break;
+		}
+
+		/* 3 Fill Cacheline */
+		ret = rtw_set_pci_cache_line_size(pdev, 8);
+		if (ret != _SUCCESS) {
+			RTW_INFO("rtw_set_pci_cache_line_size fail\n");
+			break;
+		}
+
+		/* Include 92C suggested by SD1. Added by tynli. 2009.11.25.
+		 * Enable the Backdoor
+		 */
+		{
+			u8	tmp;
+
+			Result = pci_read_config_byte(pdev, 0x98, &tmp);
+
+			tmp |= BIT4;
+
+			Result = pci_write_config_byte(pdev, 0x98, tmp);
+
+		}
+		ret = _SUCCESS;
+	} while (_FALSE);
+
+	return ret;
+}
+
+/*
+ * Update PCI dependent default settings.
+ *
+ */
+static void rtw_pci_update_default_setting(_adapter *padapter)
+{
+	struct dvobj_priv	*pdvobjpriv = adapter_to_dvobj(padapter);
+	struct pci_priv	*pcipriv = &(pdvobjpriv->pcipriv);
+	struct pwrctrl_priv	*pwrpriv = dvobj_to_pwrctl(pdvobjpriv);
+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(padapter);
+
+	/* reset pPSC->reg_rfps_level & priv->b_support_aspm */
+	pwrpriv->reg_rfps_level = 0;
+
+	/* Update PCI ASPM setting */
+	/* pwrpriv->const_amdpci_aspm = pdvobjpriv->const_amdpci_aspm; */
+	switch (pdvobjpriv->const_pci_aspm) {
+	case 0:		/* No ASPM */
+		break;
+
+	case 1:		/* ASPM dynamically enabled/disable. */
+		pwrpriv->reg_rfps_level |= RT_RF_LPS_LEVEL_ASPM;
+		break;
+
+	case 2:		/* ASPM with Clock Req dynamically enabled/disable. */
+		pwrpriv->reg_rfps_level |= (RT_RF_LPS_LEVEL_ASPM | RT_RF_OFF_LEVL_CLK_REQ);
+		break;
+
+	case 3:		/* Always enable ASPM and Clock Req from initialization to halt. */
+		pwrpriv->reg_rfps_level &= ~(RT_RF_LPS_LEVEL_ASPM);
+		pwrpriv->reg_rfps_level |= (RT_RF_PS_LEVEL_ALWAYS_ASPM | RT_RF_OFF_LEVL_CLK_REQ);
+		break;
+
+	case 4:		/* Always enable ASPM without Clock Req from initialization to halt. */
+		pwrpriv->reg_rfps_level &= ~(RT_RF_LPS_LEVEL_ASPM | RT_RF_OFF_LEVL_CLK_REQ);
+		pwrpriv->reg_rfps_level |= RT_RF_PS_LEVEL_ALWAYS_ASPM;
+		break;
+
+	case 5: /* Linux do not support ASPM OSC, added by Roger, 2013.03.27.	 */
+		break;
+	}
+
+	pwrpriv->reg_rfps_level |= RT_RF_OFF_LEVL_HALT_NIC;
+
+	/* Update Radio OFF setting */
+	switch (pdvobjpriv->const_hwsw_rfoff_d3) {
+	case 1:
+		if (pwrpriv->reg_rfps_level & RT_RF_LPS_LEVEL_ASPM)
+			pwrpriv->reg_rfps_level |= RT_RF_OFF_LEVL_ASPM;
+		break;
+
+	case 2:
+		if (pwrpriv->reg_rfps_level & RT_RF_LPS_LEVEL_ASPM)
+			pwrpriv->reg_rfps_level |= RT_RF_OFF_LEVL_ASPM;
+		pwrpriv->reg_rfps_level |= RT_RF_OFF_LEVL_HALT_NIC;
+		break;
+
+	case 3:
+		pwrpriv->reg_rfps_level |= RT_RF_OFF_LEVL_PCI_D3;
+		break;
+	}
+
+	/* Update Rx 2R setting */
+	/* pPSC->reg_rfps_level |= ((pDevice->RegLPS2RDisable) ? RT_RF_LPS_DISALBE_2R : 0); */
+
+	/*  */
+	/* Set HW definition to determine if it supports ASPM. */
+	/*  */
+	switch (pdvobjpriv->const_support_pciaspm) {
+	case 1: {	/* Support ASPM. */
+		u8	b_support_backdoor = _TRUE;
+		u8	b_support_l1_on_amd = _FALSE;
+
+		rtw_hal_get_def_var(padapter, HAL_DEF_PCI_AMD_L1_SUPPORT, &b_support_l1_on_amd);
+
+		if (pHalData->CustomerID == RT_CID_TOSHIBA &&
+		    pcipriv->pcibridge_vendor == PCI_BRIDGE_VENDOR_AMD &&
+		    !pcipriv->amd_l1_patch && !b_support_l1_on_amd) {
+			RTW_INFO("%s(): Disable L1 Backdoor!!\n", __func__);
+			b_support_backdoor = _FALSE;
+		}
+		rtw_hal_set_def_var(padapter, HAL_DEF_PCI_SUUPORT_L1_BACKDOOR, &b_support_backdoor);
+	}
+	break;
+
+	default:
+		/* Do nothing. Set when finding the chipset. */
+		break;
+	}
+}
+
+static void rtw_pci_initialize_adapter_common(_adapter *padapter)
+{
+	struct pwrctrl_priv	*pwrpriv = adapter_to_pwrctl(padapter);
+
+	rtw_pci_update_default_setting(padapter);
+
+	if (pwrpriv->reg_rfps_level & RT_RF_PS_LEVEL_ALWAYS_ASPM) {
+		/* Always enable ASPM & Clock Req. */
+		rtw_pci_enable_aspm(padapter);
+		RT_SET_PS_LEVEL(pwrpriv, RT_RF_PS_LEVEL_ALWAYS_ASPM);
+	}
+
+}
+
+/*
+ * 2009/10/28 MH Enable rtl8192ce DMA64 function. We need to enable 0x719 BIT5
+ *   */
+#ifdef CONFIG_64BIT_DMA
+u8 PlatformEnableDMA64(PADAPTER Adapter)
+{
+	struct dvobj_priv	*pdvobjpriv = adapter_to_dvobj(Adapter);
+	struct pci_dev	*pdev = pdvobjpriv->ppcidev;
+	u8	bResult = _TRUE;
+	u8	value;
+
+	pci_read_config_byte(pdev, 0x719, &value);
+
+	/* 0x719 Bit5 is DMA64 bit fetch. */
+	value |= (BIT5);
+
+	pci_write_config_byte(pdev, 0x719, value);
+
+	return bResult;
+}
+#endif
+
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 5, 0)) || (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 18))
+	#define rtw_pci_interrupt(x, y, z) rtw_pci_interrupt(x, y)
+#endif
+
+static irqreturn_t rtw_pci_interrupt(int irq, void *priv, struct pt_regs *regs)
+{
+	struct dvobj_priv *dvobj = (struct dvobj_priv *)priv;
+	_adapter *adapter = dvobj_get_primary_adapter(dvobj);
+
+	if (dvobj->irq_enabled == 0)
+		return IRQ_HANDLED;
+
+	if (rtw_hal_interrupt_handler(adapter) == _FAIL)
+		return IRQ_HANDLED;
+	/* return IRQ_NONE; */
+
+	return IRQ_HANDLED;
+}
+
+#ifdef RTK_DMP_PLATFORM
+	#define pci_iounmap(x, y) iounmap(y)
+#endif
+
+int pci_alloc_irq(struct dvobj_priv *dvobj)
+{
+	int err;
+	struct pci_dev *pdev = dvobj->ppcidev;
+	int ret;
+
+	ret = pci_enable_msi(pdev);
+
+	RTW_INFO("pci_enable_msi ret=%d\n", ret);
+
+#if defined(IRQF_SHARED)
+	err = request_irq(pdev->irq, &rtw_pci_interrupt, IRQF_SHARED, DRV_NAME, dvobj);
+#else
+	err = request_irq(pdev->irq, &rtw_pci_interrupt, SA_SHIRQ, DRV_NAME, dvobj);
+#endif
+	if (err)
+		RTW_INFO("Error allocating IRQ %d", pdev->irq);
+	else {
+		dvobj->irq_alloc = 1;
+		dvobj->irq = pdev->irq;
+		RTW_INFO("Request_irq OK, IRQ %d\n", pdev->irq);
+	}
+
+	return err ? _FAIL : _SUCCESS;
+}
+
+static void rtw_decide_chip_type_by_pci_driver_data(struct dvobj_priv *pdvobj, const struct pci_device_id *pdid)
+{
+	pdvobj->chip_type = pdid->driver_data;
+
+#ifdef CONFIG_RTL8188E
+	if (pdvobj->chip_type == RTL8188E) {
+		pdvobj->HardwareType = HARDWARE_TYPE_RTL8188EE;
+		RTW_INFO("CHIP TYPE: RTL8188E\n");
+	}
+#endif
+
+#ifdef CONFIG_RTL8812A
+	if (pdvobj->chip_type == RTL8812) {
+		pdvobj->HardwareType = HARDWARE_TYPE_RTL8812E;
+		RTW_INFO("CHIP TYPE: RTL8812AE\n");
+	}
+#endif
+
+#ifdef CONFIG_RTL8821A
+	if (pdvobj->chip_type == RTL8821) {
+		pdvobj->HardwareType = HARDWARE_TYPE_RTL8821E;
+		RTW_INFO("CHIP TYPE: RTL8821AE\n");
+	}
+#endif
+
+#ifdef CONFIG_RTL8723B
+	if (pdvobj->chip_type == RTL8723B) {
+		pdvobj->HardwareType = HARDWARE_TYPE_RTL8723BE;
+		RTW_INFO("CHIP TYPE: RTL8723BE\n");
+	}
+#endif
+#ifdef CONFIG_RTL8723D
+	if (pdvobj->chip_type == RTL8723D) {
+		pdvobj->HardwareType = HARDWARE_TYPE_RTL8723DE;
+		RTW_INFO("CHIP TYPE: RTL8723DE\n");
+	}
+#endif
+#ifdef CONFIG_RTL8192E
+	if (pdvobj->chip_type == RTL8192E) {
+		pdvobj->HardwareType = HARDWARE_TYPE_RTL8192EE;
+		RTW_INFO("CHIP TYPE: RTL8192EE\n");
+	}
+#endif
+
+#ifdef CONFIG_RTL8192F
+	if (pdvobj->chip_type == RTL8192F) {
+		pdvobj->HardwareType = HARDWARE_TYPE_RTL8192FE;
+		RTW_INFO("CHIP TYPE: RTL8192FE\n");
+	}
+#endif
+#ifdef CONFIG_RTL8814A
+	if (pdvobj->chip_type == RTL8814A) {
+		pdvobj->HardwareType = HARDWARE_TYPE_RTL8814AE;
+		RTW_INFO("CHIP TYPE: RTL8814AE\n");
+	}
+#endif
+
+#if defined(CONFIG_RTL8822B)
+	if (pdvobj->chip_type == RTL8822B) {
+		pdvobj->HardwareType = HARDWARE_TYPE_RTL8822BE;
+		RTW_INFO("CHIP TYPE: RTL8822BE\n");
+	}
+#endif
+
+#if defined(CONFIG_RTL8821C)
+	if (pdvobj->chip_type == RTL8821C) {
+		pdvobj->HardwareType = HARDWARE_TYPE_RTL8821CE;
+		RTW_INFO("CHIP TYPE: RTL8821CE\n");
+	}
+#endif
+
+}
+
+static struct dvobj_priv	*pci_dvobj_init(struct pci_dev *pdev, const struct pci_device_id *pdid)
+{
+	int err;
+	u32	status = _FAIL;
+	struct dvobj_priv	*dvobj = NULL;
+	struct pci_priv	*pcipriv = NULL;
+	struct pci_dev	*bridge_pdev = pdev->bus->self;
+	/* u32	pci_cfg_space[16]; */
+	unsigned long pmem_start, pmem_len, pmem_flags;
+	u8	tmp;
+	u8	PciBgVIdIdx;
+	int	i;
+
+
+	dvobj = devobj_init();
+	if (dvobj == NULL)
+		goto exit;
+
+
+	dvobj->ppcidev = pdev;
+	pcipriv = &(dvobj->pcipriv);
+	pci_set_drvdata(pdev, dvobj);
+
+
+	err = pci_enable_device(pdev);
+	if (err != 0) {
+		RTW_ERR("%s : Cannot enable new PCI device\n", pci_name(pdev));
+		goto free_dvobj;
+	}
+
+#ifdef CONFIG_64BIT_DMA
+	if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
+		RTW_INFO("RTL819xCE: Using 64bit DMA\n");
+		err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
+		if (err != 0) {
+			RTW_ERR("Unable to obtain 64bit DMA for consistent allocations\n");
+			goto disable_picdev;
+		}
+		dvobj->bdma64 = _TRUE;
+	} else
+#endif
+	{
+		if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(32))) {
+			err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
+			if (err != 0) {
+				RTW_ERR("Unable to obtain 32bit DMA for consistent allocations\n");
+				goto disable_picdev;
+			}
+		}
+		dvobj->bdma64 = _FALSE;
+	}
+
+	pci_set_master(pdev);
+
+	err = pci_request_regions(pdev, DRV_NAME);
+	if (err != 0) {
+		RTW_ERR("Can't obtain PCI resources\n");
+		goto disable_picdev;
+	}
+
+#ifdef RTK_129X_PLATFORM
+	if (pdev->bus->number == 0x00) {
+		pmem_start = PCIE_SLOT1_MEM_START;
+		pmem_len   = PCIE_SLOT1_MEM_LEN;
+		pmem_flags = 0;
+		RTW_PRINT("RTD129X: PCIE SLOT1\n");
+	} else if (pdev->bus->number == 0x01) {
+		pmem_start = PCIE_SLOT2_MEM_START;
+		pmem_len   = PCIE_SLOT2_MEM_LEN;
+		pmem_flags = 0;
+		RTW_PRINT("RTD129X: PCIE SLOT2\n");
+	} else {
+		RTW_ERR(KERN_ERR "RTD129X: Wrong Slot Num\n");
+		goto release_regions;
+	}
+#else
+	/* Search for memory map resource (index 0~5) */
+	for (i = 0 ; i < 6 ; i++) {
+		pmem_start = pci_resource_start(pdev, i);
+		pmem_len = pci_resource_len(pdev, i);
+		pmem_flags = pci_resource_flags(pdev, i);
+
+		if (pmem_flags & IORESOURCE_MEM)
+			break;
+	}
+
+	if (i == 6) {
+		RTW_ERR("%s: No MMIO resource found, abort!\n", __func__);
+		goto release_regions;
+	}
+#endif /* RTK_DMP_PLATFORM */
+
+#ifdef RTK_DMP_PLATFORM
+	dvobj->pci_mem_start = (unsigned long)ioremap_nocache(pmem_start, pmem_len);
+#elif defined(RTK_129X_PLATFORM)
+	if (pdev->bus->number == 0x00)
+		dvobj->ctrl_start =
+			(unsigned long)ioremap(PCIE_SLOT1_CTRL_START, 0x200);
+	else if (pdev->bus->number == 0x01)
+		dvobj->ctrl_start =
+			(unsigned long)ioremap(PCIE_SLOT2_CTRL_START, 0x200);
+
+	if (dvobj->ctrl_start == 0) {
+		RTW_ERR("RTD129X: Can't map CTRL mem\n");
+		goto release_regions;
+	}
+
+	dvobj->mask_addr = dvobj->ctrl_start + PCIE_MASK_OFFSET;
+	dvobj->tran_addr = dvobj->ctrl_start + PCIE_TRANSLATE_OFFSET;
+
+	dvobj->pci_mem_start =
+		(unsigned long)ioremap_nocache(pmem_start, pmem_len);
+#else
+	/* shared mem start */
+	dvobj->pci_mem_start = (unsigned long)pci_iomap(pdev, i, pmem_len);
+#endif
+	if (dvobj->pci_mem_start == 0) {
+		RTW_ERR("Can't map PCI mem\n");
+		goto release_regions;
+	}
+
+	RTW_INFO("Memory mapped space start: 0x%08lx len:%08lx flags:%08lx, after map:0x%08lx\n",
+		 pmem_start, pmem_len, pmem_flags, dvobj->pci_mem_start);
+
+	/*find bus info*/
+	pcipriv->busnumber = pdev->bus->number;
+	pcipriv->devnumber = PCI_SLOT(pdev->devfn);
+	pcipriv->funcnumber = PCI_FUNC(pdev->devfn);
+
+	/*find bridge info*/
+	if (bridge_pdev) {
+		pcipriv->pcibridge_busnum = bridge_pdev->bus->number;
+		pcipriv->pcibridge_devnum = PCI_SLOT(bridge_pdev->devfn);
+		pcipriv->pcibridge_funcnum = PCI_FUNC(bridge_pdev->devfn);
+		pcipriv->pcibridge_vendor = PCI_BRIDGE_VENDOR_UNKNOWN;
+		pcipriv->pcibridge_vendorid = bridge_pdev->vendor;
+		pcipriv->pcibridge_deviceid = bridge_pdev->device;
+	}
+
+#if 0
+	/* Read PCI configuration Space Header */
+	for (i = 0; i < 16; i++)
+		pci_read_config_dword(pdev, (i << 2), &pci_cfg_space[i]);
+#endif
+
+	/*step 1-1., decide the chip_type via device info*/
+	dvobj->interface_type = RTW_PCIE;
+	rtw_decide_chip_type_by_pci_driver_data(dvobj, pdid);
+
+
+	/* rtw_pci_parse_configuration(pdev, dvobj, (u8 *)&pci_cfg_space); */
+	rtw_pci_parse_configuration(pdev, dvobj);
+
+	for (PciBgVIdIdx = 0; PciBgVIdIdx < PCI_BRIDGE_VENDOR_MAX; PciBgVIdIdx++) {
+		if (pcipriv->pcibridge_vendorid == pcibridge_vendors[PciBgVIdIdx]) {
+			pcipriv->pcibridge_vendor = PciBgVIdIdx;
+			RTW_INFO("Pci Bridge Vendor is found: VID=0x%x, VendorIdx=%d\n", pcipriv->pcibridge_vendorid, PciBgVIdIdx);
+			break;
+		}
+	}
+
+	if (pcipriv->pcibridge_vendor != PCI_BRIDGE_VENDOR_UNKNOWN) {
+		rtw_pci_get_linkcontrol_reg(bridge_pdev, &pcipriv->pcibridge_linkctrlreg, &pcipriv->pcibridge_pciehdr_offset);
+
+		if (pcipriv->pcibridge_vendor == PCI_BRIDGE_VENDOR_AMD)
+			pcipriv->amd_l1_patch = rtw_pci_get_amd_l1_patch(dvobj, bridge_pdev);
+	}
+
+	status = _SUCCESS;
+
+iounmap:
+	if (status != _SUCCESS && dvobj->pci_mem_start != 0) {
+#if 1/* def RTK_DMP_PLATFORM */
+		pci_iounmap(pdev, (void *)dvobj->pci_mem_start);
+#endif
+		dvobj->pci_mem_start = 0;
+	}
+
+#ifdef RTK_129X_PLATFORM
+	if (status != _SUCCESS && dvobj->ctrl_start != 0) {
+		pci_iounmap(pdev, (void *)dvobj->ctrl_start);
+		dvobj->ctrl_start = 0;
+	}
+#endif
+
+release_regions:
+	if (status != _SUCCESS)
+		pci_release_regions(pdev);
+disable_picdev:
+	if (status != _SUCCESS)
+		pci_disable_device(pdev);
+free_dvobj:
+	if (status != _SUCCESS && dvobj) {
+		pci_set_drvdata(pdev, NULL);
+		devobj_deinit(dvobj);
+		dvobj = NULL;
+	}
+exit:
+	return dvobj;
+}
+
+
+static void pci_dvobj_deinit(struct pci_dev *pdev)
+{
+	struct dvobj_priv *dvobj = pci_get_drvdata(pdev);
+
+	pci_set_drvdata(pdev, NULL);
+	if (dvobj) {
+		if (dvobj->irq_alloc) {
+			free_irq(pdev->irq, dvobj);
+			pci_disable_msi(pdev);
+			dvobj->irq_alloc = 0;
+		}
+
+		if (dvobj->pci_mem_start != 0) {
+#if 1/* def RTK_DMP_PLATFORM */
+			pci_iounmap(pdev, (void *)dvobj->pci_mem_start);
+#endif
+			dvobj->pci_mem_start = 0;
+		}
+
+#ifdef RTK_129X_PLATFORM
+		if (dvobj->ctrl_start != 0) {
+			pci_iounmap(pdev, (void *)dvobj->ctrl_start);
+			dvobj->ctrl_start = 0;
+		}
+#endif
+		devobj_deinit(dvobj);
+	}
+
+	pci_release_regions(pdev);
+	pci_disable_device(pdev);
+
+}
+
+
+u8 rtw_set_hal_ops(_adapter *padapter)
+{
+	/* alloc memory for HAL DATA */
+	if (rtw_hal_data_init(padapter) == _FAIL)
+		return _FAIL;
+
+#ifdef CONFIG_RTL8188E
+	if (rtw_get_chip_type(padapter) == RTL8188E)
+		rtl8188ee_set_hal_ops(padapter);
+#endif
+
+#if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A)
+	if ((rtw_get_chip_type(padapter) == RTL8812) || (rtw_get_chip_type(padapter) == RTL8821))
+		rtl8812ae_set_hal_ops(padapter);
+#endif
+
+#ifdef CONFIG_RTL8723B
+	if (rtw_get_chip_type(padapter) == RTL8723B)
+		rtl8723be_set_hal_ops(padapter);
+#endif
+
+#ifdef CONFIG_RTL8723D
+	if (rtw_get_chip_type(padapter) == RTL8723D)
+		rtl8723de_set_hal_ops(padapter);
+#endif
+
+#ifdef CONFIG_RTL8192E
+	if (rtw_get_chip_type(padapter) == RTL8192E)
+		rtl8192ee_set_hal_ops(padapter);
+#endif
+
+#ifdef CONFIG_RTL8192F
+	if (rtw_get_chip_type(padapter) == RTL8192F)
+		rtl8192fe_set_hal_ops(padapter);
+#endif
+
+#ifdef CONFIG_RTL8814A
+	if (rtw_get_chip_type(padapter) == RTL8814A)
+		rtl8814ae_set_hal_ops(padapter);
+#endif
+
+#if defined(CONFIG_RTL8822B)
+	if (rtw_get_chip_type(padapter) == RTL8822B)
+		rtl8822be_set_hal_ops(padapter);
+#endif
+#if defined(CONFIG_RTL8821C)
+	if (rtw_get_chip_type(padapter) == RTL8821C)
+		rtl8821ce_set_hal_ops(padapter);
+#endif
+
+	if (rtw_hal_ops_check(padapter) == _FAIL)
+		return _FAIL;
+
+	if (hal_spec_init(padapter) == _FAIL)
+		return _FAIL;
+
+	return _SUCCESS;
+}
+
+void pci_set_intf_ops(_adapter *padapter, struct _io_ops *pops)
+{
+#ifdef CONFIG_RTL8188E
+	if (rtw_get_chip_type(padapter) == RTL8188E)
+		rtl8188ee_set_intf_ops(pops);
+#endif
+
+#if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A)
+	if ((rtw_get_chip_type(padapter) == RTL8812) || (rtw_get_chip_type(padapter) == RTL8821))
+		rtl8812ae_set_intf_ops(pops);
+#endif
+
+#ifdef CONFIG_RTL8723B
+	if (rtw_get_chip_type(padapter) == RTL8723B)
+		rtl8723be_set_intf_ops(pops);
+#endif
+
+#ifdef CONFIG_RTL8723D
+	if (rtw_get_chip_type(padapter) == RTL8723D)
+		rtl8723de_set_intf_ops(pops);
+#endif
+
+#ifdef CONFIG_RTL8192E
+	if (rtw_get_chip_type(padapter) == RTL8192E)
+		rtl8192ee_set_intf_ops(pops);
+#endif
+
+#ifdef CONFIG_RTL8192F
+	if (rtw_get_chip_type(padapter) == RTL8192F)
+		rtl8192fe_set_intf_ops(pops);
+#endif
+
+#ifdef CONFIG_RTL8814A
+	if (rtw_get_chip_type(padapter) == RTL8814A)
+		rtl8814ae_set_intf_ops(pops);
+#endif
+
+#if defined(CONFIG_RTL8822B)
+	if (rtw_get_chip_type(padapter) == RTL8822B)
+		rtl8822be_set_intf_ops(pops);
+#endif
+
+#if defined(CONFIG_RTL8821C)
+	if (rtw_get_chip_type(padapter) == RTL8821C)
+		rtl8821ce_set_intf_ops(pops);
+#endif
+
+}
+
+static void pci_intf_start(_adapter *padapter)
+{
+
+	RTW_INFO("+pci_intf_start\n");
+
+	/* Enable hw interrupt */
+	rtw_hal_enable_interrupt(padapter);
+
+	RTW_INFO("-pci_intf_start\n");
+}
+static void rtw_mi_pci_tasklets_kill(_adapter *padapter)
+{
+	int i;
+	_adapter *iface;
+	struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
+
+	for (i = 0; i < dvobj->iface_nums; i++) {
+		iface = dvobj->padapters[i];
+		if ((iface) && rtw_is_adapter_up(iface)) {
+			tasklet_kill(&(padapter->recvpriv.recv_tasklet));
+			tasklet_kill(&(padapter->recvpriv.irq_prepare_beacon_tasklet));
+			tasklet_kill(&(padapter->xmitpriv.xmit_tasklet));
+		}
+	}
+}
+
+static void pci_intf_stop(_adapter *padapter)
+{
+
+
+	/* Disable hw interrupt */
+	if (!rtw_is_surprise_removed(padapter)) {
+		/* device still exists, so driver can do i/o operation */
+		rtw_hal_disable_interrupt(padapter);
+		rtw_mi_pci_tasklets_kill(padapter);
+
+		rtw_hal_set_hwreg(padapter, HW_VAR_PCIE_STOP_TX_DMA, 0);
+
+		rtw_hal_irp_reset(padapter);
+
+	} else {
+		/* Clear irq_enabled to prevent handle interrupt function. */
+		adapter_to_dvobj(padapter)->irq_enabled = 0;
+	}
+
+
+}
+
+static void disable_ht_for_spec_devid(const struct pci_device_id *pdid)
+{
+#ifdef CONFIG_80211N_HT
+	u16 vid, pid;
+	u32 flags;
+	int i;
+	int num = sizeof(specific_device_id_tbl) / sizeof(struct specific_device_id);
+
+	for (i = 0; i < num; i++) {
+		vid = specific_device_id_tbl[i].idVendor;
+		pid = specific_device_id_tbl[i].idProduct;
+		flags = specific_device_id_tbl[i].flags;
+
+		if ((pdid->vendor == vid) && (pdid->device == pid) && (flags & SPEC_DEV_ID_DISABLE_HT)) {
+			rtw_ht_enable = 0;
+			rtw_bw_mode = 0;
+			rtw_ampdu_enable = 0;
+		}
+
+	}
+#endif
+}
+
+#ifdef CONFIG_PM
+static int rtw_pci_suspend(struct pci_dev *pdev, pm_message_t state)
+{
+	int ret = 0;
+	struct dvobj_priv *dvobj = pci_get_drvdata(pdev);
+	_adapter *padapter = dvobj_get_primary_adapter(dvobj);
+
+	ret = rtw_suspend_common(padapter);
+	ret = pci_save_state(pdev);
+	if (ret != 0) {
+		RTW_INFO("%s Failed on pci_save_state (%d)\n", __func__, ret);
+		goto exit;
+	}
+
+#ifdef CONFIG_WOWLAN
+	device_set_wakeup_enable(&pdev->dev, true);
+#endif
+	pci_disable_device(pdev);
+
+#ifdef CONFIG_WOWLAN
+	ret = pci_enable_wake(pdev, pci_choose_state(pdev, state), true);
+	if (ret != 0)
+		RTW_INFO("%s Failed on pci_enable_wake (%d)\n", __func__, ret);
+#endif
+	ret = pci_set_power_state(pdev, pci_choose_state(pdev, state));
+	if (ret != 0)
+		RTW_INFO("%s Failed on pci_set_power_state (%d)\n", __func__, ret);
+
+exit:
+	return ret;
+
+}
+
+int rtw_resume_process(_adapter *padapter)
+{
+	return rtw_resume_common(padapter);
+}
+
+static int rtw_pci_resume(struct pci_dev *pdev)
+{
+	struct dvobj_priv *dvobj = pci_get_drvdata(pdev);
+	_adapter *padapter = dvobj_get_primary_adapter(dvobj);
+	struct net_device *pnetdev = padapter->pnetdev;
+	struct pwrctrl_priv *pwrpriv = dvobj_to_pwrctl(dvobj);
+	int	err = 0;
+
+	err = pci_set_power_state(pdev, PCI_D0);
+	if (err != 0) {
+		RTW_INFO("%s Failed on pci_set_power_state (%d)\n", __func__, err);
+		goto exit;
+	}
+
+	err = pci_enable_device(pdev);
+	if (err != 0) {
+		RTW_INFO("%s Failed on pci_enable_device (%d)\n", __func__, err);
+		goto exit;
+	}
+
+
+#ifdef CONFIG_WOWLAN
+	err =  pci_enable_wake(pdev, PCI_D0, 0);
+	if (err != 0) {
+		RTW_INFO("%s Failed on pci_enable_wake (%d)\n", __func__, err);
+		goto exit;
+	}
+#endif
+#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 37))
+	pci_restore_state(pdev);
+#else
+	err = pci_restore_state(pdev);
+	if (err != 0) {
+		RTW_INFO("%s Failed on pci_restore_state (%d)\n", __func__, err);
+		goto exit;
+	}
+#endif
+
+#ifdef CONFIG_WOWLAN
+	device_set_wakeup_enable(&pdev->dev, false);
+#endif
+
+	if (pwrpriv->wowlan_mode || pwrpriv->wowlan_ap_mode) {
+		rtw_resume_lock_suspend();
+		err = rtw_resume_process(padapter);
+		rtw_resume_unlock_suspend();
+	} else {
+#ifdef CONFIG_RESUME_IN_WORKQUEUE
+		rtw_resume_in_workqueue(pwrpriv);
+#else
+		if (rtw_is_earlysuspend_registered(pwrpriv)) {
+			/* jeff: bypass resume here, do in late_resume */
+			rtw_set_do_late_resume(pwrpriv, _TRUE);
+		} else {
+			rtw_resume_lock_suspend();
+			err = rtw_resume_process(padapter);
+			rtw_resume_unlock_suspend();
+		}
+#endif
+	}
+
+exit:
+
+	return err;
+}
+#endif/* CONFIG_PM */
+
+_adapter *rtw_pci_primary_adapter_init(struct dvobj_priv *dvobj, struct pci_dev *pdev)
+{
+	_adapter *padapter = NULL;
+	int status = _FAIL;
+
+	padapter = (_adapter *)rtw_zvmalloc(sizeof(*padapter));
+	if (padapter == NULL)
+		goto exit;
+
+	if (loadparam(padapter) != _SUCCESS)
+		goto free_adapter;
+
+	padapter->dvobj = dvobj;
+
+	rtw_set_drv_stopped(padapter);/*init*/
+
+	dvobj->padapters[dvobj->iface_nums++] = padapter;
+	padapter->iface_id = IFACE_ID0;
+
+	/* set adapter_type/iface type for primary padapter */
+	padapter->isprimary = _TRUE;
+	padapter->adapter_type = PRIMARY_ADAPTER;
+#ifdef CONFIG_MI_WITH_MBSSID_CAM
+	padapter->hw_port = HW_PORT0;
+#else
+	padapter->hw_port = HW_PORT0;
+#endif
+
+	if (rtw_init_io_priv(padapter, pci_set_intf_ops) == _FAIL)
+		goto free_adapter;
+
+	/* step 2.	hook HalFunc, allocate HalData */
+	/* hal_set_hal_ops(padapter); */
+	if (rtw_set_hal_ops(padapter) == _FAIL)
+		goto free_hal_data;
+
+	/* step 3. */
+	padapter->intf_start = &pci_intf_start;
+	padapter->intf_stop = &pci_intf_stop;
+
+	/* .3 */
+	rtw_hal_read_chip_version(padapter);
+
+	/* .4 */
+	rtw_hal_chip_configure(padapter);
+
+#ifdef CONFIG_BT_COEXIST
+	rtw_btcoex_Initialize(padapter);
+#endif
+	rtw_btcoex_wifionly_initialize(padapter);
+
+	/* step 4. read efuse/eeprom data and get mac_addr */
+	if (rtw_hal_read_chip_info(padapter) == _FAIL)
+		goto free_hal_data;
+
+	/* step 5. */
+	if (rtw_init_drv_sw(padapter) == _FAIL)
+		goto free_hal_data;
+
+	if (rtw_hal_inirp_init(padapter) == _FAIL)
+		goto free_hal_data;
+
+	rtw_macaddr_cfg(adapter_mac_addr(padapter),  get_hal_mac_addr(padapter));
+
+#ifdef CONFIG_MI_WITH_MBSSID_CAM
+	rtw_mbid_camid_alloc(padapter, adapter_mac_addr(padapter));
+#endif
+#ifdef CONFIG_P2P
+	rtw_init_wifidirect_addrs(padapter, adapter_mac_addr(padapter), adapter_mac_addr(padapter));
+#endif /* CONFIG_P2P */
+
+	rtw_hal_disable_interrupt(padapter);
+
+	/* step 6. Init pci related configuration */
+	rtw_pci_initialize_adapter_common(padapter);
+
+	RTW_INFO("bDriverStopped:%s, bSurpriseRemoved:%s, bup:%d, hw_init_completed:%s\n"
+		 , rtw_is_drv_stopped(padapter) ? "True" : "False"
+		 , rtw_is_surprise_removed(padapter) ? "True" : "False"
+		 , padapter->bup
+		 , rtw_is_hw_init_completed(padapter) ? "True" : "False"
+		);
+
+	status = _SUCCESS;
+
+free_hal_data:
+	if (status != _SUCCESS && padapter->HalData)
+		rtw_hal_free_data(padapter);
+
+free_adapter:
+	if (status != _SUCCESS && padapter) {
+		#ifdef RTW_HALMAC
+		rtw_halmac_deinit_adapter(dvobj);
+		#endif
+		rtw_vmfree((u8 *)padapter, sizeof(*padapter));
+		padapter = NULL;
+	}
+exit:
+	return padapter;
+}
+
+static void rtw_pci_primary_adapter_deinit(_adapter *padapter)
+{
+	struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
+
+	/*	padapter->intf_stop(padapter); */
+
+	if (check_fwstate(pmlmepriv, _FW_LINKED))
+		rtw_disassoc_cmd(padapter, 0, RTW_CMDF_DIRECTLY);
+
+#ifdef CONFIG_AP_MODE
+	if (MLME_IS_AP(padapter) || MLME_IS_MESH(padapter)) {
+		free_mlme_ap_info(padapter);
+#ifdef CONFIG_HOSTAPD_MLME
+		hostapd_mode_unload(padapter);
+#endif
+	}
+#endif
+
+	/*rtw_cancel_all_timer(padapte);*/
+#ifdef CONFIG_WOWLAN
+	adapter_to_pwrctl(padapter)->wowlan_mode = _FALSE;
+#endif /* CONFIG_WOWLAN */
+	rtw_dev_unload(padapter);
+
+	RTW_INFO("%s, hw_init_completed=%s\n", __func__, rtw_is_hw_init_completed(padapter) ? "_TRUE" : "_FALSE");
+
+	rtw_hal_inirp_deinit(padapter);
+	rtw_free_drv_sw(padapter);
+
+	/* TODO: use rtw_os_ndevs_deinit instead at the first stage of driver's dev deinit function */
+	rtw_os_ndev_free(padapter);
+
+#ifdef RTW_HALMAC
+	rtw_halmac_deinit_adapter(adapter_to_dvobj(padapter));
+#endif /* RTW_HALMAC */
+
+	rtw_vmfree((u8 *)padapter, sizeof(_adapter));
+
+#ifdef CONFIG_PLATFORM_RTD2880B
+	RTW_INFO("wlan link down\n");
+	rtd2885_wlan_netlink_sendMsg("linkdown", "8712");
+#endif
+}
+
+/*
+ * drv_init() - a device potentially for us
+ *
+ * notes: drv_init() is called when the bus driver has located a card for us to support.
+ *        We accept the new device by returning 0.
+*/
+static int rtw_drv_init(struct pci_dev *pdev, const struct pci_device_id *pdid)
+{
+	int i, err = -ENODEV;
+
+	int status = _FAIL;
+	_adapter *padapter = NULL;
+	struct dvobj_priv *dvobj;
+	struct net_device *pnetdev;
+
+	/* RTW_INFO("+rtw_drv_init\n"); */
+
+	/* step 0. */
+	disable_ht_for_spec_devid(pdid);
+
+	/* Initialize dvobj_priv */
+	dvobj = pci_dvobj_init(pdev, pdid);
+	if (dvobj == NULL)
+		goto exit;
+
+	/* Initialize primary adapter */
+	padapter = rtw_pci_primary_adapter_init(dvobj, pdev);
+	if (padapter == NULL) {
+		RTW_INFO("rtw_pci_primary_adapter_init Failed!\n");
+		goto free_dvobj;
+	}
+
+	/* Initialize virtual interface */
+#ifdef CONFIG_CONCURRENT_MODE
+	if (padapter->registrypriv.virtual_iface_num > (CONFIG_IFACE_NUMBER - 1))
+		padapter->registrypriv.virtual_iface_num = (CONFIG_IFACE_NUMBER - 1);
+
+	for (i = 0; i < padapter->registrypriv.virtual_iface_num; i++) {
+		if (rtw_drv_add_vir_if(padapter, pci_set_intf_ops) == NULL) {
+			RTW_INFO("rtw_drv_add_iface failed! (%d)\n", i);
+			goto free_if_vir;
+		}
+	}
+#endif
+
+#ifdef CONFIG_GLOBAL_UI_PID
+	if (ui_pid[1] != 0) {
+		RTW_INFO("ui_pid[1]:%d\n", ui_pid[1]);
+		rtw_signal_process(ui_pid[1], SIGUSR2);
+	}
+#endif
+
+	/* dev_alloc_name && register_netdev */
+	if (rtw_os_ndevs_init(dvobj) != _SUCCESS)
+		goto free_if_vir;
+
+#ifdef CONFIG_HOSTAPD_MLME
+	hostapd_mode_init(padapter);
+#endif
+
+#ifdef CONFIG_PLATFORM_RTD2880B
+	RTW_INFO("wlan link up\n");
+	rtd2885_wlan_netlink_sendMsg("linkup", "8712");
+#endif
+
+	/* alloc irq */
+	if (pci_alloc_irq(dvobj) != _SUCCESS)
+		goto os_ndevs_deinit;
+
+	/* RTW_INFO("-871x_drv - drv_init, success!\n"); */
+
+	status = _SUCCESS;
+
+os_ndevs_deinit:
+	if (status != _SUCCESS)
+		rtw_os_ndevs_deinit(dvobj);
+free_if_vir:
+	if (status != _SUCCESS) {
+#ifdef CONFIG_CONCURRENT_MODE
+		rtw_drv_stop_vir_ifaces(dvobj);
+		rtw_drv_free_vir_ifaces(dvobj);
+#endif
+	}
+
+	if (status != _SUCCESS && padapter)
+		rtw_pci_primary_adapter_deinit(padapter);
+
+free_dvobj:
+	if (status != _SUCCESS)
+		pci_dvobj_deinit(pdev);
+exit:
+	return status == _SUCCESS ? 0 : -ENODEV;
+}
+
+/*
+ * dev_remove() - our device is being removed
+*/
+/* rmmod module & unplug(SurpriseRemoved) will call r871xu_dev_remove() => how to recognize both */
+static void rtw_dev_remove(struct pci_dev *pdev)
+{
+	struct dvobj_priv *pdvobjpriv = pci_get_drvdata(pdev);
+	_adapter *padapter = dvobj_get_primary_adapter(pdvobjpriv);
+	struct net_device *pnetdev = padapter->pnetdev;
+
+	if (pdvobjpriv->processing_dev_remove == _TRUE) {
+		RTW_WARN("%s-line%d: Warning! device has been removed!\n", __func__, __LINE__);
+		return;
+	}
+
+	RTW_INFO("+rtw_dev_remove\n");
+
+	pdvobjpriv->processing_dev_remove = _TRUE;
+
+	if (unlikely(!padapter))
+		return;
+
+	/* TODO: use rtw_os_ndevs_deinit instead at the first stage of driver's dev deinit function */
+	rtw_os_ndevs_unregister(pdvobjpriv);
+
+#if 0
+#ifdef RTK_DMP_PLATFORM
+	rtw_clr_surprise_removed(padapter);	/* always trate as device exists*/
+	/* this will let the driver to disable it's interrupt */
+#else
+	if (pci_drvpriv.drv_registered == _TRUE) {
+		/* RTW_INFO("r871xu_dev_remove():padapter->bSurpriseRemoved == _TRUE\n"); */
+		rtw_set_surprise_removed(padapter);
+	}
+	/*else
+	{
+
+		rtw_set_hw_init_completed(padapter, _FALSE);
+
+	}*/
+#endif
+#endif
+
+#if defined(CONFIG_HAS_EARLYSUSPEND) || defined(CONFIG_ANDROID_POWER)
+	rtw_unregister_early_suspend(dvobj_to_pwrctl(pdvobjpriv));
+#endif
+
+	if (GET_HAL_DATA(padapter)->bFWReady == _TRUE) {
+		rtw_pm_set_ips(padapter, IPS_NONE);
+		rtw_pm_set_lps(padapter, PS_MODE_ACTIVE);
+
+		LeaveAllPowerSaveMode(padapter);
+	}
+
+	rtw_set_drv_stopped(padapter);	/*for stop thread*/
+	rtw_stop_cmd_thread(padapter);
+#ifdef CONFIG_CONCURRENT_MODE
+	rtw_drv_stop_vir_ifaces(pdvobjpriv);
+#endif
+
+#ifdef CONFIG_BT_COEXIST
+#ifdef CONFIG_BT_COEXIST_SOCKET_TRX
+	if (GET_HAL_DATA(padapter)->EEPROMBluetoothCoexist)
+		rtw_btcoex_close_socket(padapter);
+#endif
+	rtw_btcoex_HaltNotify(padapter);
+#endif
+
+	rtw_pci_primary_adapter_deinit(padapter);
+
+#ifdef CONFIG_CONCURRENT_MODE
+	rtw_drv_free_vir_ifaces(pdvobjpriv);
+#endif
+
+	pci_dvobj_deinit(pdev);
+
+	RTW_INFO("-r871xu_dev_remove, done\n");
+
+	return;
+}
+
+static void rtw_dev_shutdown(struct pci_dev *pdev)
+{
+	struct dvobj_priv *pdvobjpriv = pci_get_drvdata(pdev);
+	_adapter *padapter = dvobj_get_primary_adapter(pdvobjpriv);
+	struct net_device *pnetdev = padapter->pnetdev;
+
+#ifdef CONFIG_RTL8723D
+	if (IS_HARDWARE_TYPE_8723DE(padapter)) {
+		u1Byte u1Tmp;
+
+		u1Tmp = PlatformEFIORead1Byte(padapter, 0x75 /*REG_HCI_OPT_CTRL_8723D+1*/);
+		PlatformEFIOWrite1Byte(padapter, 0x75 /*REG_HCI_OPT_CTRL_8723D+1*/, (u1Tmp|BIT0));/*Disable USB Suspend Signal*/
+	}
+#endif
+
+	rtw_dev_remove(pdev);
+}
+
+static int __init rtw_drv_entry(void)
+{
+	int ret = 0;
+
+	RTW_PRINT("module init start\n");
+	dump_drv_version(RTW_DBGDUMP);
+#ifdef BTCOEXVERSION
+	RTW_PRINT(DRV_NAME" BT-Coex version = %s\n", BTCOEXVERSION);
+#endif /* BTCOEXVERSION */
+
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 24))
+	/* console_suspend_enabled=0; */
+#endif
+
+	pci_drvpriv.drv_registered = _TRUE;
+	rtw_suspend_lock_init();
+	rtw_drv_proc_init();
+	rtw_ndev_notifier_register();
+	rtw_inetaddr_notifier_register();
+
+	ret = pci_register_driver(&pci_drvpriv.rtw_pci_drv);
+
+	if (ret != 0) {
+		pci_drvpriv.drv_registered = _FALSE;
+		rtw_suspend_lock_uninit();
+		rtw_drv_proc_deinit();
+		rtw_ndev_notifier_unregister();
+		rtw_inetaddr_notifier_unregister();
+		goto exit;
+	}
+
+exit:
+	RTW_PRINT("module init ret=%d\n", ret);
+	return ret;
+}
+
+static void __exit rtw_drv_halt(void)
+{
+	RTW_PRINT("module exit start\n");
+
+	pci_drvpriv.drv_registered = _FALSE;
+
+	pci_unregister_driver(&pci_drvpriv.rtw_pci_drv);
+
+	rtw_suspend_lock_uninit();
+	rtw_drv_proc_deinit();
+	rtw_ndev_notifier_unregister();
+	rtw_inetaddr_notifier_unregister();
+
+	RTW_PRINT("module exit success\n");
+
+	rtw_mstat_dump(RTW_DBGDUMP);
+}
+
+
+module_init(rtw_drv_entry);
+module_exit(rtw_drv_halt);
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/os_dep/linux/pci_ops_linux.c linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/os_dep/linux/pci_ops_linux.c
--- linux-5.6.3/3rdparty/rtl8821ce/os_dep/linux/pci_ops_linux.c	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/os_dep/linux/pci_ops_linux.c	2020-04-10 16:35:06.856661935 +0300
@@ -0,0 +1,17 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#define _PCI_OPS_LINUX_C_
+
+#include <drv_types.h>
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/os_dep/linux/recv_linux.c linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/os_dep/linux/recv_linux.c
--- linux-5.6.3/3rdparty/rtl8821ce/os_dep/linux/recv_linux.c	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/os_dep/linux/recv_linux.c	2020-04-10 16:35:06.856661935 +0300
@@ -0,0 +1,734 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#define _RECV_OSDEP_C_
+
+#include <drv_types.h>
+
+int rtw_os_recvframe_duplicate_skb(_adapter *padapter, union recv_frame *pcloneframe, _pkt *pskb)
+{
+	int res = _SUCCESS;
+	_pkt	*pkt_copy = NULL;
+
+	if (pskb == NULL) {
+		RTW_INFO("%s [WARN] skb == NULL, drop frag frame\n", __func__);
+		return _FAIL;
+	}
+#if 1
+	pkt_copy = rtw_skb_copy(pskb);
+
+	if (pkt_copy == NULL) {
+		RTW_INFO("%s [WARN] rtw_skb_copy fail , drop frag frame\n", __func__);
+		return _FAIL;
+	}
+#else
+	pkt_copy = rtw_skb_clone(pskb);
+
+	if (pkt_copy == NULL) {
+		RTW_INFO("%s [WARN] rtw_skb_clone fail , drop frag frame\n", __func__);
+		return _FAIL;
+	}
+#endif
+	pkt_copy->dev = padapter->pnetdev;
+
+	pcloneframe->u.hdr.pkt = pkt_copy;
+	pcloneframe->u.hdr.rx_head = pkt_copy->head;
+	pcloneframe->u.hdr.rx_data = pkt_copy->data;
+	pcloneframe->u.hdr.rx_end = skb_end_pointer(pkt_copy);
+	pcloneframe->u.hdr.rx_tail = skb_tail_pointer(pkt_copy);
+	pcloneframe->u.hdr.len = pkt_copy->len;
+
+	return res;
+}
+
+int rtw_os_alloc_recvframe(_adapter *padapter, union recv_frame *precvframe, u8 *pdata, _pkt *pskb)
+{
+	int res = _SUCCESS;
+	u8	shift_sz = 0;
+	u32	skb_len, alloc_sz;
+	_pkt	*pkt_copy = NULL;
+	struct rx_pkt_attrib *pattrib = &precvframe->u.hdr.attrib;
+
+
+	if (pdata == NULL) {
+		precvframe->u.hdr.pkt = NULL;
+		res = _FAIL;
+		return res;
+	}
+
+
+	/*	Modified by Albert 20101213 */
+	/*	For 8 bytes IP header alignment. */
+	shift_sz = pattrib->qos ? 6 : 0; /*	Qos data, wireless lan header length is 26 */
+
+	skb_len = pattrib->pkt_len;
+
+	/* for first fragment packet, driver need allocate 1536+drvinfo_sz+RXDESC_SIZE to defrag packet. */
+	/* modify alloc_sz for recvive crc error packet by thomas 2011-06-02 */
+	if ((pattrib->mfrag == 1) && (pattrib->frag_num == 0)) {
+		/* alloc_sz = 1664;	 */ /* 1664 is 128 alignment. */
+		alloc_sz = (skb_len <= 1650) ? 1664 : (skb_len + 14);
+	} else {
+		alloc_sz = skb_len;
+		/*	6 is for IP header 8 bytes alignment in QoS packet case. */
+		/*	8 is for skb->data 4 bytes alignment. */
+		alloc_sz += 14;
+	}
+
+	pkt_copy = rtw_skb_alloc(alloc_sz);
+
+	if (pkt_copy) {
+		pkt_copy->dev = padapter->pnetdev;
+		pkt_copy->len = skb_len;
+		precvframe->u.hdr.pkt = pkt_copy;
+		precvframe->u.hdr.rx_head = pkt_copy->head;
+		precvframe->u.hdr.rx_end = pkt_copy->data + alloc_sz;
+		skb_reserve(pkt_copy, 8 - ((SIZE_PTR)(pkt_copy->data) & 7));  /* force pkt_copy->data at 8-byte alignment address */
+		skb_reserve(pkt_copy, shift_sz);/* force ip_hdr at 8-byte alignment address according to shift_sz. */
+		_rtw_memcpy(pkt_copy->data, pdata, skb_len);
+		precvframe->u.hdr.rx_data = precvframe->u.hdr.rx_tail = pkt_copy->data;
+	} else {
+#if 0
+		{
+			rtw_free_recvframe(precvframe_if2, &precvpriv->free_recv_queue);
+			rtw_enqueue_recvbuf_to_head(precvbuf, &precvpriv->recv_buf_pending_queue);
+
+			/* The case of can't allocate skb is serious and may never be recovered,
+			 once bDriverStopped is enable, this task should be stopped.*/
+			if (!rtw_is_drv_stopped(secondary_padapter))
+#ifdef PLATFORM_LINUX
+				tasklet_schedule(&precvpriv->recv_tasklet);
+#endif
+			return ret;
+		}
+
+#endif
+
+#ifdef CONFIG_USE_USB_BUFFER_ALLOC_RX
+		RTW_INFO("%s:can not allocate memory for skb copy\n", __func__);
+
+		precvframe->u.hdr.pkt = NULL;
+
+		/* rtw_free_recvframe(precvframe, pfree_recv_queue); */
+		/*exit_rtw_os_recv_resource_alloc;*/
+
+		res = _FAIL;
+#else
+		if ((pattrib->mfrag == 1) && (pattrib->frag_num == 0)) {
+			RTW_INFO("%s: alloc_skb fail , drop frag frame\n", __FUNCTION__);
+			/* rtw_free_recvframe(precvframe, pfree_recv_queue); */
+			res = _FAIL;
+			goto exit_rtw_os_recv_resource_alloc;
+		}
+
+		if (pskb == NULL) {
+			res = _FAIL;
+			goto exit_rtw_os_recv_resource_alloc;
+		}
+
+		precvframe->u.hdr.pkt = rtw_skb_clone(pskb);
+		if (precvframe->u.hdr.pkt) {
+			precvframe->u.hdr.pkt->dev = padapter->pnetdev;
+			precvframe->u.hdr.rx_head = precvframe->u.hdr.rx_data = precvframe->u.hdr.rx_tail = pdata;
+			precvframe->u.hdr.rx_end =  pdata + alloc_sz;
+		} else {
+			RTW_INFO("%s: rtw_skb_clone fail\n", __FUNCTION__);
+			/* rtw_free_recvframe(precvframe, pfree_recv_queue); */
+			/*exit_rtw_os_recv_resource_alloc;*/
+			res = _FAIL;
+		}
+#endif
+	}
+
+exit_rtw_os_recv_resource_alloc:
+
+	return res;
+
+}
+
+void rtw_os_free_recvframe(union recv_frame *precvframe)
+{
+	if (precvframe->u.hdr.pkt) {
+		rtw_os_pkt_free(precvframe->u.hdr.pkt);
+		precvframe->u.hdr.pkt = NULL;
+	}
+}
+
+/* init os related resource in struct recv_priv */
+int rtw_os_recv_resource_init(struct recv_priv *precvpriv, _adapter *padapter)
+{
+	int	res = _SUCCESS;
+
+
+#ifdef CONFIG_RTW_NAPI
+	skb_queue_head_init(&precvpriv->rx_napi_skb_queue);
+#endif /* CONFIG_RTW_NAPI */
+
+	return res;
+}
+
+/* alloc os related resource in union recv_frame */
+int rtw_os_recv_resource_alloc(_adapter *padapter, union recv_frame *precvframe)
+{
+	int	res = _SUCCESS;
+
+	precvframe->u.hdr.pkt = NULL;
+
+	return res;
+}
+
+/* free os related resource in union recv_frame */
+void rtw_os_recv_resource_free(struct recv_priv *precvpriv)
+{
+	sint i;
+	union recv_frame *precvframe;
+	precvframe = (union recv_frame *) precvpriv->precv_frame_buf;
+
+
+#ifdef CONFIG_RTW_NAPI
+	if (skb_queue_len(&precvpriv->rx_napi_skb_queue))
+		RTW_WARN("rx_napi_skb_queue not empty\n");
+	rtw_skb_queue_purge(&precvpriv->rx_napi_skb_queue);
+#endif /* CONFIG_RTW_NAPI */
+
+	for (i = 0; i < NR_RECVFRAME; i++) {
+		rtw_os_free_recvframe(precvframe);
+		precvframe++;
+	}
+}
+
+/* alloc os related resource in struct recv_buf */
+int rtw_os_recvbuf_resource_alloc(_adapter *padapter, struct recv_buf *precvbuf)
+{
+	int res = _SUCCESS;
+
+#ifdef CONFIG_USB_HCI
+#ifdef CONFIG_USE_USB_BUFFER_ALLOC_RX
+	struct dvobj_priv	*pdvobjpriv = adapter_to_dvobj(padapter);
+	struct usb_device	*pusbd = pdvobjpriv->pusbdev;
+#endif
+
+	precvbuf->irp_pending = _FALSE;
+	precvbuf->purb = usb_alloc_urb(0, GFP_KERNEL);
+	if (precvbuf->purb == NULL)
+		res = _FAIL;
+
+	precvbuf->pskb = NULL;
+
+	precvbuf->pallocated_buf  = precvbuf->pbuf = NULL;
+
+	precvbuf->pdata = precvbuf->phead = precvbuf->ptail = precvbuf->pend = NULL;
+
+	precvbuf->transfer_len = 0;
+
+	precvbuf->len = 0;
+
+#ifdef CONFIG_USE_USB_BUFFER_ALLOC_RX
+	precvbuf->pallocated_buf = rtw_usb_buffer_alloc(pusbd, (size_t)precvbuf->alloc_sz, &precvbuf->dma_transfer_addr);
+	precvbuf->pbuf = precvbuf->pallocated_buf;
+	if (precvbuf->pallocated_buf == NULL)
+		return _FAIL;
+#endif /* CONFIG_USE_USB_BUFFER_ALLOC_RX */
+
+#endif /* CONFIG_USB_HCI */
+
+	return res;
+}
+
+/* free os related resource in struct recv_buf */
+int rtw_os_recvbuf_resource_free(_adapter *padapter, struct recv_buf *precvbuf)
+{
+	int ret = _SUCCESS;
+
+#ifdef CONFIG_USB_HCI
+
+#ifdef CONFIG_USE_USB_BUFFER_ALLOC_RX
+
+	struct dvobj_priv	*pdvobjpriv = adapter_to_dvobj(padapter);
+	struct usb_device	*pusbd = pdvobjpriv->pusbdev;
+
+	rtw_usb_buffer_free(pusbd, (size_t)precvbuf->alloc_sz, precvbuf->pallocated_buf, precvbuf->dma_transfer_addr);
+	precvbuf->pallocated_buf =  NULL;
+	precvbuf->dma_transfer_addr = 0;
+
+#endif /* CONFIG_USE_USB_BUFFER_ALLOC_RX */
+
+	if (precvbuf->purb) {
+		/* usb_kill_urb(precvbuf->purb); */
+		usb_free_urb(precvbuf->purb);
+	}
+
+#endif /* CONFIG_USB_HCI */
+
+
+	if (precvbuf->pskb) {
+#ifdef CONFIG_PREALLOC_RX_SKB_BUFFER
+		if (rtw_free_skb_premem(precvbuf->pskb) != 0)
+#endif
+			rtw_skb_free(precvbuf->pskb);
+	}
+	return ret;
+
+}
+
+_pkt *rtw_os_alloc_msdu_pkt(union recv_frame *prframe, const u8 *da, const u8 *sa, u8 *msdu ,u16 msdu_len)
+{
+	u16	eth_type;
+	u8	*data_ptr;
+	_pkt *sub_skb;
+	struct rx_pkt_attrib *pattrib;
+
+	pattrib = &prframe->u.hdr.attrib;
+
+#ifdef CONFIG_SKB_COPY
+	sub_skb = rtw_skb_alloc(msdu_len + 14);
+	if (sub_skb) {
+		skb_reserve(sub_skb, 14);
+		data_ptr = (u8 *)skb_put(sub_skb, msdu_len);
+		_rtw_memcpy(data_ptr, msdu, msdu_len);
+	} else
+#endif /* CONFIG_SKB_COPY */
+	{
+		sub_skb = rtw_skb_clone(prframe->u.hdr.pkt);
+		if (sub_skb) {
+			sub_skb->data = msdu;
+			sub_skb->len = msdu_len;
+			skb_set_tail_pointer(sub_skb, msdu_len);
+		} else {
+			RTW_INFO("%s(): rtw_skb_clone() Fail!!!\n", __FUNCTION__);
+			return NULL;
+		}
+	}
+
+	eth_type = RTW_GET_BE16(&sub_skb->data[6]);
+
+	if (sub_skb->len >= 8
+		&& ((_rtw_memcmp(sub_skb->data, rtw_rfc1042_header, SNAP_SIZE)
+				&& eth_type != ETH_P_AARP && eth_type != ETH_P_IPX)
+			|| _rtw_memcmp(sub_skb->data, rtw_bridge_tunnel_header, SNAP_SIZE))
+	) {
+		/* remove RFC1042 or Bridge-Tunnel encapsulation and replace EtherType */
+		skb_pull(sub_skb, SNAP_SIZE);
+		_rtw_memcpy(skb_push(sub_skb, ETH_ALEN), sa, ETH_ALEN);
+		_rtw_memcpy(skb_push(sub_skb, ETH_ALEN), da, ETH_ALEN);
+	} else {
+		/* Leave Ethernet header part of hdr and full payload */
+		u16 len;
+
+		len = htons(sub_skb->len);
+		_rtw_memcpy(skb_push(sub_skb, 2), &len, 2);
+		_rtw_memcpy(skb_push(sub_skb, ETH_ALEN), sa, ETH_ALEN);
+		_rtw_memcpy(skb_push(sub_skb, ETH_ALEN), da, ETH_ALEN);
+	}
+
+	return sub_skb;
+}
+
+#ifdef CONFIG_RTW_NAPI
+static int napi_recv(_adapter *padapter, int budget)
+{
+	_pkt *pskb;
+	struct recv_priv *precvpriv = &padapter->recvpriv;
+	int work_done = 0;
+	struct registry_priv *pregistrypriv = &padapter->registrypriv;
+	u8 rx_ok;
+
+
+	while ((work_done < budget) &&
+	       (!skb_queue_empty(&precvpriv->rx_napi_skb_queue))) {
+		pskb = skb_dequeue(&precvpriv->rx_napi_skb_queue);
+		if (!pskb)
+			break;
+
+		rx_ok = _FALSE;
+
+#ifdef CONFIG_RTW_GRO
+		if (pregistrypriv->en_gro) {
+			if (rtw_napi_gro_receive(&padapter->napi, pskb) != GRO_DROP)
+				rx_ok = _TRUE;
+			goto next;
+		}
+#endif /* CONFIG_RTW_GRO */
+
+		if (rtw_netif_receive_skb(padapter->pnetdev, pskb) == NET_RX_SUCCESS)
+			rx_ok = _TRUE;
+
+next:
+		if (rx_ok == _TRUE) {
+			work_done++;
+			DBG_COUNTER(padapter->rx_logs.os_netif_ok);
+		} else {
+			DBG_COUNTER(padapter->rx_logs.os_netif_err);
+		}
+	}
+
+	return work_done;
+}
+
+int rtw_recv_napi_poll(struct napi_struct *napi, int budget)
+{
+	_adapter *padapter = container_of(napi, _adapter, napi);
+	int work_done = 0;
+	struct recv_priv *precvpriv = &padapter->recvpriv;
+
+
+	work_done = napi_recv(padapter, budget);
+	if (work_done < budget) {
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 19, 0)) && defined(CONFIG_PCI_HCI)
+		napi_complete_done(napi, work_done);
+#else
+		napi_complete(napi);
+#endif
+		if (!skb_queue_empty(&precvpriv->rx_napi_skb_queue))
+			napi_schedule(napi);
+	}
+
+	return work_done;
+}
+
+#ifdef CONFIG_RTW_NAPI_DYNAMIC
+void dynamic_napi_th_chk (_adapter *adapter)
+{
+
+	if (adapter->registrypriv.en_napi) {
+		struct dvobj_priv *dvobj;
+		struct registry_priv *registry;
+	
+		dvobj = adapter_to_dvobj(adapter);
+		registry = &adapter->registrypriv;
+		if (dvobj->traffic_stat.cur_rx_tp > registry->napi_threshold)
+			dvobj->en_napi_dynamic = 1;
+		else
+			dvobj->en_napi_dynamic = 0;
+	}
+
+}
+#endif /* CONFIG_RTW_NAPI_DYNAMIC */
+#endif /* CONFIG_RTW_NAPI */
+
+void rtw_os_recv_indicate_pkt(_adapter *padapter, _pkt *pkt, union recv_frame *rframe)
+{
+	struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
+	struct recv_priv *precvpriv = &(padapter->recvpriv);
+	struct registry_priv	*pregistrypriv = &padapter->registrypriv;
+#ifdef CONFIG_BR_EXT
+	void *br_port = NULL;
+#endif
+	int ret;
+
+	/* Indicat the packets to upper layer */
+	if (pkt) {
+		struct ethhdr *ehdr = (struct ethhdr *)pkt->data;
+
+		DBG_COUNTER(padapter->rx_logs.os_indicate);
+
+		if (MLME_IS_AP(padapter)) {
+			_pkt *pskb2 = NULL;
+			struct sta_info *psta = NULL;
+			struct sta_priv *pstapriv = &padapter->stapriv;
+			int bmcast = IS_MCAST(ehdr->h_dest);
+
+			/* RTW_INFO("bmcast=%d\n", bmcast); */
+
+			if (_rtw_memcmp(ehdr->h_dest, adapter_mac_addr(padapter), ETH_ALEN) == _FALSE) {
+				/* RTW_INFO("not ap psta=%p, addr=%pM\n", psta, ehdr->h_dest); */
+
+				if (bmcast) {
+					psta = rtw_get_bcmc_stainfo(padapter);
+					pskb2 = rtw_skb_clone(pkt);
+				} else
+					psta = rtw_get_stainfo(pstapriv, ehdr->h_dest);
+
+				if (psta) {
+					struct net_device *pnetdev = (struct net_device *)padapter->pnetdev;
+
+					/* RTW_INFO("directly forwarding to the rtw_xmit_entry\n"); */
+
+					/* skb->ip_summed = CHECKSUM_NONE; */
+					pkt->dev = pnetdev;
+					#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 35))
+					skb_set_queue_mapping(pkt, rtw_recv_select_queue(pkt));
+					#endif /* LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 35) */
+
+					_rtw_xmit_entry(pkt, pnetdev);
+
+					if (bmcast && (pskb2 != NULL)) {
+						pkt = pskb2;
+						DBG_COUNTER(padapter->rx_logs.os_indicate_ap_mcast);
+					} else {
+						DBG_COUNTER(padapter->rx_logs.os_indicate_ap_forward);
+						return;
+					}
+				}
+			} else { /* to APself */
+				/* RTW_INFO("to APSelf\n"); */
+				DBG_COUNTER(padapter->rx_logs.os_indicate_ap_self);
+			}
+		}
+
+#ifdef CONFIG_BR_EXT
+		if (check_fwstate(pmlmepriv, WIFI_STATION_STATE | WIFI_ADHOC_STATE) == _TRUE) {
+			/* Insert NAT2.5 RX here! */
+			#if (LINUX_VERSION_CODE <= KERNEL_VERSION(2, 6, 35))
+			br_port = padapter->pnetdev->br_port;
+			#else
+			rcu_read_lock();
+			br_port = rcu_dereference(padapter->pnetdev->rx_handler_data);
+			rcu_read_unlock();
+			#endif
+
+			if (br_port) {
+				int nat25_handle_frame(_adapter *priv, struct sk_buff *skb);
+
+				if (nat25_handle_frame(padapter, pkt) == -1) {
+					/* priv->ext_stats.rx_data_drops++; */
+					/* DEBUG_ERR("RX DROP: nat25_handle_frame fail!\n"); */
+					/* return FAIL; */
+
+					#if 1
+					/* bypass this frame to upper layer!! */
+					#else
+					rtw_skb_free(sub_skb);
+					continue;
+					#endif
+				}
+			}
+		}
+#endif /* CONFIG_BR_EXT */
+
+		/* After eth_type_trans process , pkt->data pointer will move from ethrnet header to ip header */
+		pkt->protocol = eth_type_trans(pkt, padapter->pnetdev);
+		pkt->dev = padapter->pnetdev;
+		pkt->ip_summed = CHECKSUM_NONE; /* CONFIG_TCP_CSUM_OFFLOAD_RX */
+
+#ifdef CONFIG_RTW_NAPI
+#ifdef CONFIG_RTW_NAPI_DYNAMIC
+		if (!skb_queue_empty(&precvpriv->rx_napi_skb_queue)
+			&& !adapter_to_dvobj(padapter)->en_napi_dynamic			
+			)
+			napi_recv(padapter, RTL_NAPI_WEIGHT);
+#endif
+
+		if (pregistrypriv->en_napi
+			#ifdef CONFIG_RTW_NAPI_DYNAMIC
+			&& adapter_to_dvobj(padapter)->en_napi_dynamic
+			#endif
+		) {
+			skb_queue_tail(&precvpriv->rx_napi_skb_queue, pkt);
+			#ifndef CONFIG_RTW_NAPI_V2
+			napi_schedule(&padapter->napi);
+			#endif
+			return;
+		}
+#endif /* CONFIG_RTW_NAPI */
+
+		ret = rtw_netif_rx(padapter->pnetdev, pkt);
+		if (ret == NET_RX_SUCCESS)
+			DBG_COUNTER(padapter->rx_logs.os_netif_ok);
+		else
+			DBG_COUNTER(padapter->rx_logs.os_netif_err);
+	}
+}
+
+void rtw_handle_tkip_mic_err(_adapter *padapter, struct sta_info *sta, u8 bgroup)
+{
+#ifdef CONFIG_IOCTL_CFG80211
+	enum nl80211_key_type key_type = 0;
+#endif
+	union iwreq_data wrqu;
+	struct iw_michaelmicfailure    ev;
+	struct security_priv	*psecuritypriv = &padapter->securitypriv;
+	systime cur_time = 0;
+
+	if (psecuritypriv->last_mic_err_time == 0)
+		psecuritypriv->last_mic_err_time = rtw_get_current_time();
+	else {
+		cur_time = rtw_get_current_time();
+
+		if (cur_time - psecuritypriv->last_mic_err_time < 60 * HZ) {
+			psecuritypriv->btkip_countermeasure = _TRUE;
+			psecuritypriv->last_mic_err_time = 0;
+			psecuritypriv->btkip_countermeasure_time = cur_time;
+		} else
+			psecuritypriv->last_mic_err_time = rtw_get_current_time();
+	}
+
+#ifdef CONFIG_IOCTL_CFG80211
+	if (bgroup)
+		key_type |= NL80211_KEYTYPE_GROUP;
+	else
+		key_type |= NL80211_KEYTYPE_PAIRWISE;
+
+	cfg80211_michael_mic_failure(padapter->pnetdev, sta->cmn.mac_addr, key_type, -1, NULL, GFP_ATOMIC);
+#endif
+
+	_rtw_memset(&ev, 0x00, sizeof(ev));
+	if (bgroup)
+		ev.flags |= IW_MICFAILURE_GROUP;
+	else
+		ev.flags |= IW_MICFAILURE_PAIRWISE;
+
+	ev.src_addr.sa_family = ARPHRD_ETHER;
+	_rtw_memcpy(ev.src_addr.sa_data, sta->cmn.mac_addr, ETH_ALEN);
+
+	_rtw_memset(&wrqu, 0x00, sizeof(wrqu));
+	wrqu.data.length = sizeof(ev);
+
+#ifndef CONFIG_IOCTL_CFG80211
+	wireless_send_event(padapter->pnetdev, IWEVMICHAELMICFAILURE, &wrqu, (char *) &ev);
+#endif
+}
+
+#ifdef CONFIG_HOSTAPD_MLME
+void rtw_hostapd_mlme_rx(_adapter *padapter, union recv_frame *precv_frame)
+{
+	_pkt *skb;
+	struct hostapd_priv *phostapdpriv  = padapter->phostapdpriv;
+	struct net_device *pmgnt_netdev = phostapdpriv->pmgnt_netdev;
+
+
+	skb = precv_frame->u.hdr.pkt;
+
+	if (skb == NULL)
+		return;
+
+	skb->data = precv_frame->u.hdr.rx_data;
+	skb->tail = precv_frame->u.hdr.rx_tail;
+	skb->len = precv_frame->u.hdr.len;
+
+	/* pskb_copy = rtw_skb_copy(skb);
+	*	if(skb == NULL) goto _exit; */
+
+	skb->dev = pmgnt_netdev;
+	skb->ip_summed = CHECKSUM_NONE;
+	skb->pkt_type = PACKET_OTHERHOST;
+	/* skb->protocol = __constant_htons(0x0019); ETH_P_80211_RAW */
+	skb->protocol = __constant_htons(0x0003); /*ETH_P_80211_RAW*/
+
+	/* RTW_INFO("(1)data=0x%x, head=0x%x, tail=0x%x, mac_header=0x%x, len=%d\n", skb->data, skb->head, skb->tail, skb->mac_header, skb->len); */
+
+	/* skb->mac.raw = skb->data; */
+	skb_reset_mac_header(skb);
+
+	/* skb_pull(skb, 24); */
+	_rtw_memset(skb->cb, 0, sizeof(skb->cb));
+
+	rtw_netif_rx(pmgnt_netdev, skb);
+
+	precv_frame->u.hdr.pkt = NULL; /* set pointer to NULL before rtw_free_recvframe() if call rtw_netif_rx() */
+}
+#endif /* CONFIG_HOSTAPD_MLME */
+
+int rtw_recv_monitor(_adapter *padapter, union recv_frame *precv_frame)
+{
+	int ret = _FAIL;
+	struct recv_priv *precvpriv;
+	_queue	*pfree_recv_queue;
+	_pkt *skb;
+	struct rx_pkt_attrib *pattrib;
+
+	if (NULL == precv_frame)
+		goto _recv_drop;
+
+	pattrib = &precv_frame->u.hdr.attrib;
+	precvpriv = &(padapter->recvpriv);
+	pfree_recv_queue = &(precvpriv->free_recv_queue);
+
+	skb = precv_frame->u.hdr.pkt;
+	if (skb == NULL) {
+		RTW_INFO("%s :skb==NULL something wrong!!!!\n", __func__);
+		goto _recv_drop;
+	}
+
+	skb->data = precv_frame->u.hdr.rx_data;
+	skb_set_tail_pointer(skb, precv_frame->u.hdr.len);
+	skb->len = precv_frame->u.hdr.len;
+	skb->ip_summed = CHECKSUM_NONE;
+	skb->pkt_type = PACKET_OTHERHOST;
+	skb->protocol = htons(0x0019); /* ETH_P_80211_RAW */
+
+	rtw_netif_rx(padapter->pnetdev, skb);
+
+	/* pointers to NULL before rtw_free_recvframe() */
+	precv_frame->u.hdr.pkt = NULL;
+
+	ret = _SUCCESS;
+
+_recv_drop:
+
+	/* enqueue back to free_recv_queue */
+	if (precv_frame)
+		rtw_free_recvframe(precv_frame, pfree_recv_queue);
+
+	return ret;
+
+}
+
+inline void rtw_rframe_set_os_pkt(union recv_frame *rframe)
+{
+	_pkt *skb = rframe->u.hdr.pkt;
+
+	skb->data = rframe->u.hdr.rx_data;
+	skb_set_tail_pointer(skb, rframe->u.hdr.len);
+	skb->len = rframe->u.hdr.len;
+}
+
+int rtw_recv_indicatepkt(_adapter *padapter, union recv_frame *precv_frame)
+{
+	struct recv_priv *precvpriv;
+	_queue	*pfree_recv_queue;
+
+	precvpriv = &(padapter->recvpriv);
+	pfree_recv_queue = &(precvpriv->free_recv_queue);
+
+	if (precv_frame->u.hdr.pkt == NULL)
+		goto _recv_indicatepkt_drop;
+
+	rtw_os_recv_indicate_pkt(padapter, precv_frame->u.hdr.pkt, precv_frame);
+
+_recv_indicatepkt_end:
+	precv_frame->u.hdr.pkt = NULL;
+	rtw_free_recvframe(precv_frame, pfree_recv_queue);
+	return _SUCCESS;
+
+_recv_indicatepkt_drop:
+	rtw_free_recvframe(precv_frame, pfree_recv_queue);
+	DBG_COUNTER(padapter->rx_logs.os_indicate_err);
+	return _FAIL;
+}
+
+void rtw_os_read_port(_adapter *padapter, struct recv_buf *precvbuf)
+{
+	struct recv_priv *precvpriv = &padapter->recvpriv;
+
+#ifdef CONFIG_USB_HCI
+
+	precvbuf->ref_cnt--;
+
+	/* free skb in recv_buf */
+	rtw_skb_free(precvbuf->pskb);
+
+	precvbuf->pskb = NULL;
+
+	if (precvbuf->irp_pending == _FALSE)
+		rtw_read_port(padapter, precvpriv->ff_hwaddr, 0, (unsigned char *)precvbuf);
+
+
+#endif
+#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
+	precvbuf->pskb = NULL;
+#endif
+
+}
+
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/os_dep/linux/rhashtable.c linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/os_dep/linux/rhashtable.c
--- linux-5.6.3/3rdparty/rtl8821ce/os_dep/linux/rhashtable.c	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/os_dep/linux/rhashtable.c	2020-04-10 16:35:06.856661935 +0300
@@ -0,0 +1,844 @@
+/*
+ * Resizable, Scalable, Concurrent Hash Table
+ *
+ * Copyright (c) 2015 Herbert Xu <herbert@gondor.apana.org.au>
+ * Copyright (c) 2014-2015 Thomas Graf <tgraf@suug.ch>
+ * Copyright (c) 2008-2014 Patrick McHardy <kaber@trash.net>
+ *
+ * Code partially derived from nft_hash
+ * Rewritten with rehash code from br_multicast plus single list
+ * pointer as suggested by Josh Triplett
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/atomic.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/log2.h>
+#include <linux/sched.h>
+#include <linux/slab.h>
+#include <linux/vmalloc.h>
+#include <linux/mm.h>
+#include <linux/jhash.h>
+#include <linux/random.h>
+#include <linux/err.h>
+#include <linux/export.h>
+
+#define HASH_DEFAULT_SIZE	64UL
+#define HASH_MIN_SIZE		4U
+#define BUCKET_LOCKS_PER_CPU   128UL
+
+static u32 head_hashfn(struct rhashtable *ht,
+		       const struct bucket_table *tbl,
+		       const struct rhash_head *he)
+{
+	return rht_head_hashfn(ht, tbl, he, ht->p);
+}
+
+#ifdef CONFIG_PROVE_LOCKING
+#define ASSERT_RHT_MUTEX(HT) BUG_ON(!lockdep_rht_mutex_is_held(HT))
+
+int lockdep_rht_mutex_is_held(struct rhashtable *ht)
+{
+	return (debug_locks) ? lockdep_is_held(&ht->mutex) : 1;
+}
+
+int lockdep_rht_bucket_is_held(const struct bucket_table *tbl, u32 hash)
+{
+	spinlock_t *lock = rht_bucket_lock(tbl, hash);
+
+	return (debug_locks) ? lockdep_is_held(lock) : 1;
+}
+#else
+#define ASSERT_RHT_MUTEX(HT)
+#endif
+
+
+static int alloc_bucket_locks(struct rhashtable *ht, struct bucket_table *tbl,
+			      gfp_t gfp)
+{
+	unsigned int i, size;
+#if defined(CONFIG_PROVE_LOCKING)
+	unsigned int nr_pcpus = 2;
+#else
+	unsigned int nr_pcpus = num_possible_cpus();
+#endif
+
+	nr_pcpus = min_t(unsigned int, nr_pcpus, 32UL);
+	size = roundup_pow_of_two(nr_pcpus * ht->p.locks_mul);
+
+	/* Never allocate more than 0.5 locks per bucket */
+	size = min_t(unsigned int, size, tbl->size >> 1);
+
+	if (sizeof(spinlock_t) != 0) {
+#ifdef CONFIG_NUMA
+		if (size * sizeof(spinlock_t) > PAGE_SIZE &&
+		    gfp == GFP_KERNEL)
+			tbl->locks = vmalloc(size * sizeof(spinlock_t));
+		else
+#endif
+		tbl->locks = kmalloc_array(size, sizeof(spinlock_t),
+					   gfp);
+		if (!tbl->locks)
+			return -ENOMEM;
+		for (i = 0; i < size; i++)
+			spin_lock_init(&tbl->locks[i]);
+	}
+	tbl->locks_mask = size - 1;
+
+	return 0;
+}
+
+static void bucket_table_free(const struct bucket_table *tbl)
+{
+	if (tbl)
+		kvfree(tbl->locks);
+
+	kvfree(tbl);
+}
+
+static void bucket_table_free_rcu(struct rcu_head *head)
+{
+	bucket_table_free(container_of(head, struct bucket_table, rcu));
+}
+
+static struct bucket_table *bucket_table_alloc(struct rhashtable *ht,
+					       size_t nbuckets,
+					       gfp_t gfp)
+{
+	struct bucket_table *tbl = NULL;
+	size_t size;
+	int i;
+
+	size = sizeof(*tbl) + nbuckets * sizeof(tbl->buckets[0]);
+	if (size <= (PAGE_SIZE << PAGE_ALLOC_COSTLY_ORDER) ||
+	    gfp != GFP_KERNEL)
+		tbl = kzalloc(size, gfp | __GFP_NOWARN | __GFP_NORETRY);
+	if (tbl == NULL && gfp == GFP_KERNEL)
+		tbl = vzalloc(size);
+	if (tbl == NULL)
+		return NULL;
+
+	tbl->size = nbuckets;
+
+	if (alloc_bucket_locks(ht, tbl, gfp) < 0) {
+		bucket_table_free(tbl);
+		return NULL;
+	}
+
+	INIT_LIST_HEAD(&tbl->walkers);
+
+	get_random_bytes(&tbl->hash_rnd, sizeof(tbl->hash_rnd));
+
+	for (i = 0; i < nbuckets; i++)
+		INIT_RHT_NULLS_HEAD(tbl->buckets[i], ht, i);
+
+	return tbl;
+}
+
+static struct bucket_table *rhashtable_last_table(struct rhashtable *ht,
+						  struct bucket_table *tbl)
+{
+	struct bucket_table *new_tbl;
+
+	do {
+		new_tbl = tbl;
+		tbl = rht_dereference_rcu(tbl->future_tbl, ht);
+	} while (tbl);
+
+	return new_tbl;
+}
+
+static int rhashtable_rehash_one(struct rhashtable *ht, unsigned int old_hash)
+{
+	struct bucket_table *old_tbl = rht_dereference(ht->tbl, ht);
+	struct bucket_table *new_tbl = rhashtable_last_table(ht,
+		rht_dereference_rcu(old_tbl->future_tbl, ht));
+	struct rhash_head __rcu **pprev = &old_tbl->buckets[old_hash];
+	int err = -ENOENT;
+	struct rhash_head *head, *next, *entry;
+	spinlock_t *new_bucket_lock;
+	unsigned int new_hash;
+
+	rht_for_each(entry, old_tbl, old_hash) {
+		err = 0;
+		next = rht_dereference_bucket(entry->next, old_tbl, old_hash);
+
+		if (rht_is_a_nulls(next))
+			break;
+
+		pprev = &entry->next;
+	}
+
+	if (err)
+		goto out;
+
+	new_hash = head_hashfn(ht, new_tbl, entry);
+
+	new_bucket_lock = rht_bucket_lock(new_tbl, new_hash);
+
+	spin_lock_nested(new_bucket_lock, SINGLE_DEPTH_NESTING);
+	head = rht_dereference_bucket(new_tbl->buckets[new_hash],
+				      new_tbl, new_hash);
+
+	RCU_INIT_POINTER(entry->next, head);
+
+	rcu_assign_pointer(new_tbl->buckets[new_hash], entry);
+	spin_unlock(new_bucket_lock);
+
+	rcu_assign_pointer(*pprev, next);
+
+out:
+	return err;
+}
+
+static void rhashtable_rehash_chain(struct rhashtable *ht,
+				    unsigned int old_hash)
+{
+	struct bucket_table *old_tbl = rht_dereference(ht->tbl, ht);
+	spinlock_t *old_bucket_lock;
+
+	old_bucket_lock = rht_bucket_lock(old_tbl, old_hash);
+
+	spin_lock_bh(old_bucket_lock);
+	while (!rhashtable_rehash_one(ht, old_hash))
+		;
+	old_tbl->rehash++;
+	spin_unlock_bh(old_bucket_lock);
+}
+
+static int rhashtable_rehash_attach(struct rhashtable *ht,
+				    struct bucket_table *old_tbl,
+				    struct bucket_table *new_tbl)
+{
+	/* Protect future_tbl using the first bucket lock. */
+	spin_lock_bh(old_tbl->locks);
+
+	/* Did somebody beat us to it? */
+	if (rcu_access_pointer(old_tbl->future_tbl)) {
+		spin_unlock_bh(old_tbl->locks);
+		return -EEXIST;
+	}
+
+	/* Make insertions go into the new, empty table right away. Deletions
+	 * and lookups will be attempted in both tables until we synchronize.
+	 */
+	rcu_assign_pointer(old_tbl->future_tbl, new_tbl);
+
+	/* Ensure the new table is visible to readers. */
+	smp_wmb();
+
+	spin_unlock_bh(old_tbl->locks);
+
+	return 0;
+}
+
+static int rhashtable_rehash_table(struct rhashtable *ht)
+{
+	struct bucket_table *old_tbl = rht_dereference(ht->tbl, ht);
+	struct bucket_table *new_tbl;
+	struct rhashtable_walker *walker;
+	unsigned int old_hash;
+
+	new_tbl = rht_dereference(old_tbl->future_tbl, ht);
+	if (!new_tbl)
+		return 0;
+
+	for (old_hash = 0; old_hash < old_tbl->size; old_hash++)
+		rhashtable_rehash_chain(ht, old_hash);
+
+	/* Publish the new table pointer. */
+	rcu_assign_pointer(ht->tbl, new_tbl);
+
+	spin_lock(&ht->lock);
+	list_for_each_entry(walker, &old_tbl->walkers, list)
+		walker->tbl = NULL;
+	spin_unlock(&ht->lock);
+
+	/* Wait for readers. All new readers will see the new
+	 * table, and thus no references to the old table will
+	 * remain.
+	 */
+	call_rcu(&old_tbl->rcu, bucket_table_free_rcu);
+
+	return rht_dereference(new_tbl->future_tbl, ht) ? -EAGAIN : 0;
+}
+
+/**
+ * rhashtable_expand - Expand hash table while allowing concurrent lookups
+ * @ht:		the hash table to expand
+ *
+ * A secondary bucket array is allocated and the hash entries are migrated.
+ *
+ * This function may only be called in a context where it is safe to call
+ * synchronize_rcu(), e.g. not within a rcu_read_lock() section.
+ *
+ * The caller must ensure that no concurrent resizing occurs by holding
+ * ht->mutex.
+ *
+ * It is valid to have concurrent insertions and deletions protected by per
+ * bucket locks or concurrent RCU protected lookups and traversals.
+ */
+static int rhashtable_expand(struct rhashtable *ht)
+{
+	struct bucket_table *new_tbl, *old_tbl = rht_dereference(ht->tbl, ht);
+	int err;
+
+	ASSERT_RHT_MUTEX(ht);
+
+	old_tbl = rhashtable_last_table(ht, old_tbl);
+
+	new_tbl = bucket_table_alloc(ht, old_tbl->size * 2, GFP_KERNEL);
+	if (new_tbl == NULL)
+		return -ENOMEM;
+
+	err = rhashtable_rehash_attach(ht, old_tbl, new_tbl);
+	if (err)
+		bucket_table_free(new_tbl);
+
+	return err;
+}
+
+/**
+ * rhashtable_shrink - Shrink hash table while allowing concurrent lookups
+ * @ht:		the hash table to shrink
+ *
+ * This function shrinks the hash table to fit, i.e., the smallest
+ * size would not cause it to expand right away automatically.
+ *
+ * The caller must ensure that no concurrent resizing occurs by holding
+ * ht->mutex.
+ *
+ * The caller must ensure that no concurrent table mutations take place.
+ * It is however valid to have concurrent lookups if they are RCU protected.
+ *
+ * It is valid to have concurrent insertions and deletions protected by per
+ * bucket locks or concurrent RCU protected lookups and traversals.
+ */
+static int rhashtable_shrink(struct rhashtable *ht)
+{
+	struct bucket_table *new_tbl, *old_tbl = rht_dereference(ht->tbl, ht);
+	unsigned int size;
+	int err;
+
+	ASSERT_RHT_MUTEX(ht);
+
+	size = roundup_pow_of_two(atomic_read(&ht->nelems) * 3 / 2);
+	if (size < ht->p.min_size)
+		size = ht->p.min_size;
+
+	if (old_tbl->size <= size)
+		return 0;
+
+	if (rht_dereference(old_tbl->future_tbl, ht))
+		return -EEXIST;
+
+	new_tbl = bucket_table_alloc(ht, size, GFP_KERNEL);
+	if (new_tbl == NULL)
+		return -ENOMEM;
+
+	err = rhashtable_rehash_attach(ht, old_tbl, new_tbl);
+	if (err)
+		bucket_table_free(new_tbl);
+
+	return err;
+}
+
+static void rht_deferred_worker(struct work_struct *work)
+{
+	struct rhashtable *ht;
+	struct bucket_table *tbl;
+	int err = 0;
+
+	ht = container_of(work, struct rhashtable, run_work);
+	mutex_lock(&ht->mutex);
+
+	tbl = rht_dereference(ht->tbl, ht);
+	tbl = rhashtable_last_table(ht, tbl);
+
+	if (rht_grow_above_75(ht, tbl))
+		rhashtable_expand(ht);
+	else if (ht->p.automatic_shrinking && rht_shrink_below_30(ht, tbl))
+		rhashtable_shrink(ht);
+
+	err = rhashtable_rehash_table(ht);
+
+	mutex_unlock(&ht->mutex);
+
+	if (err)
+		schedule_work(&ht->run_work);
+}
+
+static bool rhashtable_check_elasticity(struct rhashtable *ht,
+					struct bucket_table *tbl,
+					unsigned int hash)
+{
+	unsigned int elasticity = ht->elasticity;
+	struct rhash_head *head;
+
+	rht_for_each(head, tbl, hash)
+		if (!--elasticity)
+			return true;
+
+	return false;
+}
+
+int rhashtable_insert_rehash(struct rhashtable *ht,
+			     struct bucket_table *tbl)
+{
+	struct bucket_table *old_tbl;
+	struct bucket_table *new_tbl;
+	unsigned int size;
+	int err;
+
+	old_tbl = rht_dereference_rcu(ht->tbl, ht);
+
+	size = tbl->size;
+
+	err = -EBUSY;
+
+	if (rht_grow_above_75(ht, tbl))
+		size *= 2;
+	/* Do not schedule more than one rehash */
+	else if (old_tbl != tbl)
+		goto fail;
+
+	err = -ENOMEM;
+
+	new_tbl = bucket_table_alloc(ht, size, GFP_ATOMIC);
+	if (new_tbl == NULL)
+		goto fail;
+
+	err = rhashtable_rehash_attach(ht, tbl, new_tbl);
+	if (err) {
+		bucket_table_free(new_tbl);
+		if (err == -EEXIST)
+			err = 0;
+	} else
+		schedule_work(&ht->run_work);
+
+	return err;
+
+fail:
+	/* Do not fail the insert if someone else did a rehash. */
+	if (likely(rcu_dereference_raw(tbl->future_tbl)))
+		return 0;
+
+	/* Schedule async rehash to retry allocation in process context. */
+	if (err == -ENOMEM)
+		schedule_work(&ht->run_work);
+
+	return err;
+}
+
+struct bucket_table *rhashtable_insert_slow(struct rhashtable *ht,
+					    const void *key,
+					    struct rhash_head *obj,
+					    struct bucket_table *tbl)
+{
+	struct rhash_head *head;
+	unsigned int hash;
+	int err;
+
+	tbl = rhashtable_last_table(ht, tbl);
+	hash = head_hashfn(ht, tbl, obj);
+	spin_lock_nested(rht_bucket_lock(tbl, hash), SINGLE_DEPTH_NESTING);
+
+	err = -EEXIST;
+	if (key && rhashtable_lookup_fast(ht, key, ht->p))
+		goto exit;
+
+	err = -E2BIG;
+	if (unlikely(rht_grow_above_max(ht, tbl)))
+		goto exit;
+
+	err = -EAGAIN;
+	if (rhashtable_check_elasticity(ht, tbl, hash) ||
+	    rht_grow_above_100(ht, tbl))
+		goto exit;
+
+	err = 0;
+
+	head = rht_dereference_bucket(tbl->buckets[hash], tbl, hash);
+
+	RCU_INIT_POINTER(obj->next, head);
+
+	rcu_assign_pointer(tbl->buckets[hash], obj);
+
+	atomic_inc(&ht->nelems);
+
+exit:
+	spin_unlock(rht_bucket_lock(tbl, hash));
+
+	if (err == 0)
+		return NULL;
+	else if (err == -EAGAIN)
+		return tbl;
+	else
+		return ERR_PTR(err);
+}
+
+/**
+ * rhashtable_walk_init - Initialise an iterator
+ * @ht:		Table to walk over
+ * @iter:	Hash table Iterator
+ *
+ * This function prepares a hash table walk.
+ *
+ * Note that if you restart a walk after rhashtable_walk_stop you
+ * may see the same object twice.  Also, you may miss objects if
+ * there are removals in between rhashtable_walk_stop and the next
+ * call to rhashtable_walk_start.
+ *
+ * For a completely stable walk you should construct your own data
+ * structure outside the hash table.
+ *
+ * This function may sleep so you must not call it from interrupt
+ * context or with spin locks held.
+ *
+ * You must call rhashtable_walk_exit if this function returns
+ * successfully.
+ */
+int rhashtable_walk_init(struct rhashtable *ht, struct rhashtable_iter *iter)
+{
+	iter->ht = ht;
+	iter->p = NULL;
+	iter->slot = 0;
+	iter->skip = 0;
+
+	iter->walker = kmalloc(sizeof(*iter->walker), GFP_KERNEL);
+	if (!iter->walker)
+		return -ENOMEM;
+
+	spin_lock(&ht->lock);
+	iter->walker->tbl =
+		rcu_dereference_protected(ht->tbl, lockdep_is_held(&ht->lock));
+	list_add(&iter->walker->list, &iter->walker->tbl->walkers);
+	spin_unlock(&ht->lock);
+
+	return 0;
+}
+
+/**
+ * rhashtable_walk_exit - Free an iterator
+ * @iter:	Hash table Iterator
+ *
+ * This function frees resources allocated by rhashtable_walk_init.
+ */
+void rhashtable_walk_exit(struct rhashtable_iter *iter)
+{
+	spin_lock(&iter->ht->lock);
+	if (iter->walker->tbl)
+		list_del(&iter->walker->list);
+	spin_unlock(&iter->ht->lock);
+	kfree(iter->walker);
+}
+
+/**
+ * rhashtable_walk_start - Start a hash table walk
+ * @iter:	Hash table iterator
+ *
+ * Start a hash table walk.  Note that we take the RCU lock in all
+ * cases including when we return an error.  So you must always call
+ * rhashtable_walk_stop to clean up.
+ *
+ * Returns zero if successful.
+ *
+ * Returns -EAGAIN if resize event occured.  Note that the iterator
+ * will rewind back to the beginning and you may use it immediately
+ * by calling rhashtable_walk_next.
+ */
+int rhashtable_walk_start(struct rhashtable_iter *iter)
+	__acquires(RCU)
+{
+	struct rhashtable *ht = iter->ht;
+
+	rcu_read_lock();
+
+	spin_lock(&ht->lock);
+	if (iter->walker->tbl)
+		list_del(&iter->walker->list);
+	spin_unlock(&ht->lock);
+
+	if (!iter->walker->tbl) {
+		iter->walker->tbl = rht_dereference_rcu(ht->tbl, ht);
+		return -EAGAIN;
+	}
+
+	return 0;
+}
+
+/**
+ * rhashtable_walk_next - Return the next object and advance the iterator
+ * @iter:	Hash table iterator
+ *
+ * Note that you must call rhashtable_walk_stop when you are finished
+ * with the walk.
+ *
+ * Returns the next object or NULL when the end of the table is reached.
+ *
+ * Returns -EAGAIN if resize event occured.  Note that the iterator
+ * will rewind back to the beginning and you may continue to use it.
+ */
+void *rhashtable_walk_next(struct rhashtable_iter *iter)
+{
+	struct bucket_table *tbl = iter->walker->tbl;
+	struct rhashtable *ht = iter->ht;
+	struct rhash_head *p = iter->p;
+
+	if (p) {
+		p = rht_dereference_bucket_rcu(p->next, tbl, iter->slot);
+		goto next;
+	}
+
+	for (; iter->slot < tbl->size; iter->slot++) {
+		int skip = iter->skip;
+
+		rht_for_each_rcu(p, tbl, iter->slot) {
+			if (!skip)
+				break;
+			skip--;
+		}
+
+next:
+		if (!rht_is_a_nulls(p)) {
+			iter->skip++;
+			iter->p = p;
+			return rht_obj(ht, p);
+		}
+
+		iter->skip = 0;
+	}
+
+	iter->p = NULL;
+
+	/* Ensure we see any new tables. */
+	smp_rmb();
+
+	iter->walker->tbl = rht_dereference_rcu(tbl->future_tbl, ht);
+	if (iter->walker->tbl) {
+		iter->slot = 0;
+		iter->skip = 0;
+		return ERR_PTR(-EAGAIN);
+	}
+
+	return NULL;
+}
+
+/**
+ * rhashtable_walk_stop - Finish a hash table walk
+ * @iter:	Hash table iterator
+ *
+ * Finish a hash table walk.
+ */
+void rhashtable_walk_stop(struct rhashtable_iter *iter)
+	__releases(RCU)
+{
+	struct rhashtable *ht;
+	struct bucket_table *tbl = iter->walker->tbl;
+
+	if (!tbl)
+		goto out;
+
+	ht = iter->ht;
+
+	spin_lock(&ht->lock);
+	if (tbl->rehash < tbl->size)
+		list_add(&iter->walker->list, &tbl->walkers);
+	else
+		iter->walker->tbl = NULL;
+	spin_unlock(&ht->lock);
+
+	iter->p = NULL;
+
+out:
+	rcu_read_unlock();
+}
+
+static size_t rounded_hashtable_size(const struct rhashtable_params *params)
+{
+	return max(roundup_pow_of_two(params->nelem_hint * 4 / 3),
+		   (unsigned long)params->min_size);
+}
+
+static u32 rhashtable_jhash2(const void *key, u32 length, u32 seed)
+{
+	return jhash2(key, length, seed);
+}
+
+/**
+ * rhashtable_init - initialize a new hash table
+ * @ht:		hash table to be initialized
+ * @params:	configuration parameters
+ *
+ * Initializes a new hash table based on the provided configuration
+ * parameters. A table can be configured either with a variable or
+ * fixed length key:
+ *
+ * Configuration Example 1: Fixed length keys
+ * struct test_obj {
+ *	int			key;
+ *	void *			my_member;
+ *	struct rhash_head	node;
+ * };
+ *
+ * struct rhashtable_params params = {
+ *	.head_offset = offsetof(struct test_obj, node),
+ *	.key_offset = offsetof(struct test_obj, key),
+ *	.key_len = sizeof(int),
+ *	.hashfn = jhash,
+ *	.nulls_base = (1U << RHT_BASE_SHIFT),
+ * };
+ *
+ * Configuration Example 2: Variable length keys
+ * struct test_obj {
+ *	[...]
+ *	struct rhash_head	node;
+ * };
+ *
+ * u32 my_hash_fn(const void *data, u32 len, u32 seed)
+ * {
+ *	struct test_obj *obj = data;
+ *
+ *	return [... hash ...];
+ * }
+ *
+ * struct rhashtable_params params = {
+ *	.head_offset = offsetof(struct test_obj, node),
+ *	.hashfn = jhash,
+ *	.obj_hashfn = my_hash_fn,
+ * };
+ */
+int rhashtable_init(struct rhashtable *ht,
+		    const struct rhashtable_params *params)
+{
+	struct bucket_table *tbl;
+	size_t size;
+
+	size = HASH_DEFAULT_SIZE;
+
+	if ((!params->key_len && !params->obj_hashfn) ||
+	    (params->obj_hashfn && !params->obj_cmpfn))
+		return -EINVAL;
+
+	if (params->nulls_base && params->nulls_base < (1U << RHT_BASE_SHIFT))
+		return -EINVAL;
+
+	memset(ht, 0, sizeof(*ht));
+	mutex_init(&ht->mutex);
+	spin_lock_init(&ht->lock);
+	memcpy(&ht->p, params, sizeof(*params));
+
+	if (params->min_size)
+		ht->p.min_size = roundup_pow_of_two(params->min_size);
+
+	if (params->max_size)
+		ht->p.max_size = rounddown_pow_of_two(params->max_size);
+
+	if (params->insecure_max_entries)
+		ht->p.insecure_max_entries =
+			rounddown_pow_of_two(params->insecure_max_entries);
+	else
+		ht->p.insecure_max_entries = ht->p.max_size * 2;
+
+	ht->p.min_size = max(ht->p.min_size, HASH_MIN_SIZE);
+
+	if (params->nelem_hint)
+		size = rounded_hashtable_size(&ht->p);
+
+	/* The maximum (not average) chain length grows with the
+	 * size of the hash table, at a rate of (log N)/(log log N).
+	 * The value of 16 is selected so that even if the hash
+	 * table grew to 2^32 you would not expect the maximum
+	 * chain length to exceed it unless we are under attack
+	 * (or extremely unlucky).
+	 *
+	 * As this limit is only to detect attacks, we don't need
+	 * to set it to a lower value as you'd need the chain
+	 * length to vastly exceed 16 to have any real effect
+	 * on the system.
+	 */
+	if (!params->insecure_elasticity)
+		ht->elasticity = 16;
+
+	if (params->locks_mul)
+		ht->p.locks_mul = roundup_pow_of_two(params->locks_mul);
+	else
+		ht->p.locks_mul = BUCKET_LOCKS_PER_CPU;
+
+	ht->key_len = ht->p.key_len;
+	if (!params->hashfn) {
+		ht->p.hashfn = jhash;
+
+		if (!(ht->key_len & (sizeof(u32) - 1))) {
+			ht->key_len /= sizeof(u32);
+			ht->p.hashfn = rhashtable_jhash2;
+		}
+	}
+
+	tbl = bucket_table_alloc(ht, size, GFP_KERNEL);
+	if (tbl == NULL)
+		return -ENOMEM;
+
+	atomic_set(&ht->nelems, 0);
+
+	RCU_INIT_POINTER(ht->tbl, tbl);
+
+	INIT_WORK(&ht->run_work, rht_deferred_worker);
+
+	return 0;
+}
+
+/**
+ * rhashtable_free_and_destroy - free elements and destroy hash table
+ * @ht:		the hash table to destroy
+ * @free_fn:	callback to release resources of element
+ * @arg:	pointer passed to free_fn
+ *
+ * Stops an eventual async resize. If defined, invokes free_fn for each
+ * element to releasal resources. Please note that RCU protected
+ * readers may still be accessing the elements. Releasing of resources
+ * must occur in a compatible manner. Then frees the bucket array.
+ *
+ * This function will eventually sleep to wait for an async resize
+ * to complete. The caller is responsible that no further write operations
+ * occurs in parallel.
+ */
+void rhashtable_free_and_destroy(struct rhashtable *ht,
+				 void (*free_fn)(void *ptr, void *arg),
+				 void *arg)
+{
+	const struct bucket_table *tbl;
+	unsigned int i;
+
+	cancel_work_sync(&ht->run_work);
+
+	mutex_lock(&ht->mutex);
+	tbl = rht_dereference(ht->tbl, ht);
+	if (free_fn) {
+		for (i = 0; i < tbl->size; i++) {
+			struct rhash_head *pos, *next;
+
+			for (pos = rht_dereference(tbl->buckets[i], ht),
+			     next = !rht_is_a_nulls(pos) ?
+					rht_dereference(pos->next, ht) : NULL;
+			     !rht_is_a_nulls(pos);
+			     pos = next,
+			     next = !rht_is_a_nulls(pos) ?
+					rht_dereference(pos->next, ht) : NULL)
+				free_fn(rht_obj(ht, pos), arg);
+		}
+	}
+
+	bucket_table_free(tbl);
+	mutex_unlock(&ht->mutex);
+}
+
+void rhashtable_destroy(struct rhashtable *ht)
+{
+	return rhashtable_free_and_destroy(ht, NULL, NULL);
+}
+
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/os_dep/linux/rhashtable.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/os_dep/linux/rhashtable.h
--- linux-5.6.3/3rdparty/rtl8821ce/os_dep/linux/rhashtable.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/os_dep/linux/rhashtable.h	2020-04-10 16:35:06.856661935 +0300
@@ -0,0 +1,827 @@
+/*
+ * Resizable, Scalable, Concurrent Hash Table
+ *
+ * Copyright (c) 2015 Herbert Xu <herbert@gondor.apana.org.au>
+ * Copyright (c) 2014-2015 Thomas Graf <tgraf@suug.ch>
+ * Copyright (c) 2008-2014 Patrick McHardy <kaber@trash.net>
+ *
+ * Code partially derived from nft_hash
+ * Rewritten with rehash code from br_multicast plus single list
+ * pointer as suggested by Josh Triplett
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef _LINUX_RHASHTABLE_H
+#define _LINUX_RHASHTABLE_H
+
+#include <linux/atomic.h>
+#include <linux/compiler.h>
+#include <linux/err.h>
+#include <linux/errno.h>
+#include <linux/jhash.h>
+#include <linux/list_nulls.h>
+#include <linux/workqueue.h>
+#include <linux/mutex.h>
+#include <linux/rcupdate.h>
+
+/*
+ * The end of the chain is marked with a special nulls marks which has
+ * the following format:
+ *
+ * +-------+-----------------------------------------------------+-+
+ * | Base  |                      Hash                           |1|
+ * +-------+-----------------------------------------------------+-+
+ *
+ * Base (4 bits) : Reserved to distinguish between multiple tables.
+ *                 Specified via &struct rhashtable_params.nulls_base.
+ * Hash (27 bits): Full hash (unmasked) of first element added to bucket
+ * 1 (1 bit)     : Nulls marker (always set)
+ *
+ * The remaining bits of the next pointer remain unused for now.
+ */
+#define RHT_BASE_BITS		4
+#define RHT_HASH_BITS		27
+#define RHT_BASE_SHIFT		RHT_HASH_BITS
+
+/* Base bits plus 1 bit for nulls marker */
+#define RHT_HASH_RESERVED_SPACE	(RHT_BASE_BITS + 1)
+
+struct rhash_head {
+	struct rhash_head __rcu		*next;
+};
+
+/**
+ * struct bucket_table - Table of hash buckets
+ * @size: Number of hash buckets
+ * @rehash: Current bucket being rehashed
+ * @hash_rnd: Random seed to fold into hash
+ * @locks_mask: Mask to apply before accessing locks[]
+ * @locks: Array of spinlocks protecting individual buckets
+ * @walkers: List of active walkers
+ * @rcu: RCU structure for freeing the table
+ * @future_tbl: Table under construction during rehashing
+ * @buckets: size * hash buckets
+ */
+struct bucket_table {
+	unsigned int		size;
+	unsigned int		rehash;
+	u32			hash_rnd;
+	unsigned int		locks_mask;
+	spinlock_t		*locks;
+	struct list_head	walkers;
+	struct rcu_head		rcu;
+
+	struct bucket_table __rcu *future_tbl;
+
+	struct rhash_head __rcu	*buckets[] ____cacheline_aligned_in_smp;
+};
+
+/**
+ * struct rhashtable_compare_arg - Key for the function rhashtable_compare
+ * @ht: Hash table
+ * @key: Key to compare against
+ */
+struct rhashtable_compare_arg {
+	struct rhashtable *ht;
+	const void *key;
+};
+
+typedef u32 (*rht_hashfn_t)(const void *data, u32 len, u32 seed);
+typedef u32 (*rht_obj_hashfn_t)(const void *data, u32 len, u32 seed);
+typedef int (*rht_obj_cmpfn_t)(struct rhashtable_compare_arg *arg,
+			       const void *obj);
+
+struct rhashtable;
+
+/**
+ * struct rhashtable_params - Hash table construction parameters
+ * @nelem_hint: Hint on number of elements, should be 75% of desired size
+ * @key_len: Length of key
+ * @key_offset: Offset of key in struct to be hashed
+ * @head_offset: Offset of rhash_head in struct to be hashed
+ * @insecure_max_entries: Maximum number of entries (may be exceeded)
+ * @max_size: Maximum size while expanding
+ * @min_size: Minimum size while shrinking
+ * @nulls_base: Base value to generate nulls marker
+ * @insecure_elasticity: Set to true to disable chain length checks
+ * @automatic_shrinking: Enable automatic shrinking of tables
+ * @locks_mul: Number of bucket locks to allocate per cpu (default: 128)
+ * @hashfn: Hash function (default: jhash2 if !(key_len % 4), or jhash)
+ * @obj_hashfn: Function to hash object
+ * @obj_cmpfn: Function to compare key with object
+ */
+struct rhashtable_params {
+	size_t			nelem_hint;
+	size_t			key_len;
+	size_t			key_offset;
+	size_t			head_offset;
+	unsigned int		insecure_max_entries;
+	unsigned int		max_size;
+	unsigned int		min_size;
+	u32			nulls_base;
+	bool			insecure_elasticity;
+	bool			automatic_shrinking;
+	size_t			locks_mul;
+	rht_hashfn_t		hashfn;
+	rht_obj_hashfn_t	obj_hashfn;
+	rht_obj_cmpfn_t		obj_cmpfn;
+};
+
+/**
+ * struct rhashtable - Hash table handle
+ * @tbl: Bucket table
+ * @nelems: Number of elements in table
+ * @key_len: Key length for hashfn
+ * @elasticity: Maximum chain length before rehash
+ * @p: Configuration parameters
+ * @run_work: Deferred worker to expand/shrink asynchronously
+ * @mutex: Mutex to protect current/future table swapping
+ * @lock: Spin lock to protect walker list
+ */
+struct rhashtable {
+	struct bucket_table __rcu	*tbl;
+	atomic_t			nelems;
+	unsigned int			key_len;
+	unsigned int			elasticity;
+	struct rhashtable_params	p;
+	struct work_struct		run_work;
+	struct mutex                    mutex;
+	spinlock_t			lock;
+};
+
+/**
+ * struct rhashtable_walker - Hash table walker
+ * @list: List entry on list of walkers
+ * @tbl: The table that we were walking over
+ */
+struct rhashtable_walker {
+	struct list_head list;
+	struct bucket_table *tbl;
+};
+
+/**
+ * struct rhashtable_iter - Hash table iterator, fits into netlink cb
+ * @ht: Table to iterate through
+ * @p: Current pointer
+ * @walker: Associated rhashtable walker
+ * @slot: Current slot
+ * @skip: Number of entries to skip in slot
+ */
+struct rhashtable_iter {
+	struct rhashtable *ht;
+	struct rhash_head *p;
+	struct rhashtable_walker *walker;
+	unsigned int slot;
+	unsigned int skip;
+};
+
+static inline unsigned long rht_marker(const struct rhashtable *ht, u32 hash)
+{
+	return NULLS_MARKER(ht->p.nulls_base + hash);
+}
+
+#define INIT_RHT_NULLS_HEAD(ptr, ht, hash) \
+	((ptr) = (typeof(ptr)) rht_marker(ht, hash))
+
+static inline bool rht_is_a_nulls(const struct rhash_head *ptr)
+{
+	return ((unsigned long) ptr & 1);
+}
+
+static inline unsigned long rht_get_nulls_value(const struct rhash_head *ptr)
+{
+	return ((unsigned long) ptr) >> 1;
+}
+
+static inline void *rht_obj(const struct rhashtable *ht,
+			    const struct rhash_head *he)
+{
+	return (char *)he - ht->p.head_offset;
+}
+
+static inline unsigned int rht_bucket_index(const struct bucket_table *tbl,
+					    unsigned int hash)
+{
+	return (hash >> RHT_HASH_RESERVED_SPACE) & (tbl->size - 1);
+}
+
+static inline unsigned int rht_key_hashfn(
+	struct rhashtable *ht, const struct bucket_table *tbl,
+	const void *key, const struct rhashtable_params params)
+{
+	unsigned int hash;
+
+	/* params must be equal to ht->p if it isn't constant. */
+	if (!__builtin_constant_p(params.key_len))
+		hash = ht->p.hashfn(key, ht->key_len, tbl->hash_rnd);
+	else if (params.key_len) {
+		unsigned int key_len = params.key_len;
+
+		if (params.hashfn)
+			hash = params.hashfn(key, key_len, tbl->hash_rnd);
+		else if (key_len & (sizeof(u32) - 1))
+			hash = jhash(key, key_len, tbl->hash_rnd);
+		else
+			hash = jhash2(key, key_len / sizeof(u32),
+				      tbl->hash_rnd);
+	} else {
+		unsigned int key_len = ht->p.key_len;
+
+		if (params.hashfn)
+			hash = params.hashfn(key, key_len, tbl->hash_rnd);
+		else
+			hash = jhash(key, key_len, tbl->hash_rnd);
+	}
+
+	return rht_bucket_index(tbl, hash);
+}
+
+static inline unsigned int rht_head_hashfn(
+	struct rhashtable *ht, const struct bucket_table *tbl,
+	const struct rhash_head *he, const struct rhashtable_params params)
+{
+	const char *ptr = rht_obj(ht, he);
+
+	return likely(params.obj_hashfn) ?
+	       rht_bucket_index(tbl, params.obj_hashfn(ptr, params.key_len ?:
+							    ht->p.key_len,
+						       tbl->hash_rnd)) :
+	       rht_key_hashfn(ht, tbl, ptr + params.key_offset, params);
+}
+
+/**
+ * rht_grow_above_75 - returns true if nelems > 0.75 * table-size
+ * @ht:		hash table
+ * @tbl:	current table
+ */
+static inline bool rht_grow_above_75(const struct rhashtable *ht,
+				     const struct bucket_table *tbl)
+{
+	/* Expand table when exceeding 75% load */
+	return atomic_read(&ht->nelems) > (tbl->size / 4 * 3) &&
+	       (!ht->p.max_size || tbl->size < ht->p.max_size);
+}
+
+/**
+ * rht_shrink_below_30 - returns true if nelems < 0.3 * table-size
+ * @ht:		hash table
+ * @tbl:	current table
+ */
+static inline bool rht_shrink_below_30(const struct rhashtable *ht,
+				       const struct bucket_table *tbl)
+{
+	/* Shrink table beneath 30% load */
+	return atomic_read(&ht->nelems) < (tbl->size * 3 / 10) &&
+	       tbl->size > ht->p.min_size;
+}
+
+/**
+ * rht_grow_above_100 - returns true if nelems > table-size
+ * @ht:		hash table
+ * @tbl:	current table
+ */
+static inline bool rht_grow_above_100(const struct rhashtable *ht,
+				      const struct bucket_table *tbl)
+{
+	return atomic_read(&ht->nelems) > tbl->size &&
+		(!ht->p.max_size || tbl->size < ht->p.max_size);
+}
+
+/**
+ * rht_grow_above_max - returns true if table is above maximum
+ * @ht:		hash table
+ * @tbl:	current table
+ */
+static inline bool rht_grow_above_max(const struct rhashtable *ht,
+				      const struct bucket_table *tbl)
+{
+	return ht->p.insecure_max_entries &&
+	       atomic_read(&ht->nelems) >= ht->p.insecure_max_entries;
+}
+
+/* The bucket lock is selected based on the hash and protects mutations
+ * on a group of hash buckets.
+ *
+ * A maximum of tbl->size/2 bucket locks is allocated. This ensures that
+ * a single lock always covers both buckets which may both contains
+ * entries which link to the same bucket of the old table during resizing.
+ * This allows to simplify the locking as locking the bucket in both
+ * tables during resize always guarantee protection.
+ *
+ * IMPORTANT: When holding the bucket lock of both the old and new table
+ * during expansions and shrinking, the old bucket lock must always be
+ * acquired first.
+ */
+static inline spinlock_t *rht_bucket_lock(const struct bucket_table *tbl,
+					  unsigned int hash)
+{
+	return &tbl->locks[hash & tbl->locks_mask];
+}
+
+#ifdef CONFIG_PROVE_LOCKING
+int lockdep_rht_mutex_is_held(struct rhashtable *ht);
+int lockdep_rht_bucket_is_held(const struct bucket_table *tbl, u32 hash);
+#else
+static inline int lockdep_rht_mutex_is_held(struct rhashtable *ht)
+{
+	return 1;
+}
+
+static inline int lockdep_rht_bucket_is_held(const struct bucket_table *tbl,
+					     u32 hash)
+{
+	return 1;
+}
+#endif /* CONFIG_PROVE_LOCKING */
+
+int rhashtable_init(struct rhashtable *ht,
+		    const struct rhashtable_params *params);
+
+struct bucket_table *rhashtable_insert_slow(struct rhashtable *ht,
+					    const void *key,
+					    struct rhash_head *obj,
+					    struct bucket_table *old_tbl);
+int rhashtable_insert_rehash(struct rhashtable *ht, struct bucket_table *tbl);
+
+int rhashtable_walk_init(struct rhashtable *ht, struct rhashtable_iter *iter);
+void rhashtable_walk_exit(struct rhashtable_iter *iter);
+int rhashtable_walk_start(struct rhashtable_iter *iter) __acquires(RCU);
+void *rhashtable_walk_next(struct rhashtable_iter *iter);
+void rhashtable_walk_stop(struct rhashtable_iter *iter) __releases(RCU);
+
+void rhashtable_free_and_destroy(struct rhashtable *ht,
+				 void (*free_fn)(void *ptr, void *arg),
+				 void *arg);
+void rhashtable_destroy(struct rhashtable *ht);
+
+#define rht_dereference(p, ht) \
+	rcu_dereference_protected(p, lockdep_rht_mutex_is_held(ht))
+
+#define rht_dereference_rcu(p, ht) \
+	rcu_dereference_check(p, lockdep_rht_mutex_is_held(ht))
+
+#define rht_dereference_bucket(p, tbl, hash) \
+	rcu_dereference_protected(p, lockdep_rht_bucket_is_held(tbl, hash))
+
+#define rht_dereference_bucket_rcu(p, tbl, hash) \
+	rcu_dereference_check(p, lockdep_rht_bucket_is_held(tbl, hash))
+
+#define rht_entry(tpos, pos, member) \
+	({ tpos = container_of(pos, typeof(*tpos), member); 1; })
+
+/**
+ * rht_for_each_continue - continue iterating over hash chain
+ * @pos:	the &struct rhash_head to use as a loop cursor.
+ * @head:	the previous &struct rhash_head to continue from
+ * @tbl:	the &struct bucket_table
+ * @hash:	the hash value / bucket index
+ */
+#define rht_for_each_continue(pos, head, tbl, hash) \
+	for (pos = rht_dereference_bucket(head, tbl, hash); \
+	     !rht_is_a_nulls(pos); \
+	     pos = rht_dereference_bucket((pos)->next, tbl, hash))
+
+/**
+ * rht_for_each - iterate over hash chain
+ * @pos:	the &struct rhash_head to use as a loop cursor.
+ * @tbl:	the &struct bucket_table
+ * @hash:	the hash value / bucket index
+ */
+#define rht_for_each(pos, tbl, hash) \
+	rht_for_each_continue(pos, (tbl)->buckets[hash], tbl, hash)
+
+/**
+ * rht_for_each_entry_continue - continue iterating over hash chain
+ * @tpos:	the type * to use as a loop cursor.
+ * @pos:	the &struct rhash_head to use as a loop cursor.
+ * @head:	the previous &struct rhash_head to continue from
+ * @tbl:	the &struct bucket_table
+ * @hash:	the hash value / bucket index
+ * @member:	name of the &struct rhash_head within the hashable struct.
+ */
+#define rht_for_each_entry_continue(tpos, pos, head, tbl, hash, member)	\
+	for (pos = rht_dereference_bucket(head, tbl, hash);		\
+	     (!rht_is_a_nulls(pos)) && rht_entry(tpos, pos, member);	\
+	     pos = rht_dereference_bucket((pos)->next, tbl, hash))
+
+/**
+ * rht_for_each_entry - iterate over hash chain of given type
+ * @tpos:	the type * to use as a loop cursor.
+ * @pos:	the &struct rhash_head to use as a loop cursor.
+ * @tbl:	the &struct bucket_table
+ * @hash:	the hash value / bucket index
+ * @member:	name of the &struct rhash_head within the hashable struct.
+ */
+#define rht_for_each_entry(tpos, pos, tbl, hash, member)		\
+	rht_for_each_entry_continue(tpos, pos, (tbl)->buckets[hash],	\
+				    tbl, hash, member)
+
+/**
+ * rht_for_each_entry_safe - safely iterate over hash chain of given type
+ * @tpos:	the type * to use as a loop cursor.
+ * @pos:	the &struct rhash_head to use as a loop cursor.
+ * @next:	the &struct rhash_head to use as next in loop cursor.
+ * @tbl:	the &struct bucket_table
+ * @hash:	the hash value / bucket index
+ * @member:	name of the &struct rhash_head within the hashable struct.
+ *
+ * This hash chain list-traversal primitive allows for the looped code to
+ * remove the loop cursor from the list.
+ */
+#define rht_for_each_entry_safe(tpos, pos, next, tbl, hash, member)	    \
+	for (pos = rht_dereference_bucket((tbl)->buckets[hash], tbl, hash), \
+	     next = !rht_is_a_nulls(pos) ?				    \
+		       rht_dereference_bucket(pos->next, tbl, hash) : NULL; \
+	     (!rht_is_a_nulls(pos)) && rht_entry(tpos, pos, member);	    \
+	     pos = next,						    \
+	     next = !rht_is_a_nulls(pos) ?				    \
+		       rht_dereference_bucket(pos->next, tbl, hash) : NULL)
+
+/**
+ * rht_for_each_rcu_continue - continue iterating over rcu hash chain
+ * @pos:	the &struct rhash_head to use as a loop cursor.
+ * @head:	the previous &struct rhash_head to continue from
+ * @tbl:	the &struct bucket_table
+ * @hash:	the hash value / bucket index
+ *
+ * This hash chain list-traversal primitive may safely run concurrently with
+ * the _rcu mutation primitives such as rhashtable_insert() as long as the
+ * traversal is guarded by rcu_read_lock().
+ */
+#define rht_for_each_rcu_continue(pos, head, tbl, hash)			\
+	for (({barrier(); }),						\
+	     pos = rht_dereference_bucket_rcu(head, tbl, hash);		\
+	     !rht_is_a_nulls(pos);					\
+	     pos = rcu_dereference_raw(pos->next))
+
+/**
+ * rht_for_each_rcu - iterate over rcu hash chain
+ * @pos:	the &struct rhash_head to use as a loop cursor.
+ * @tbl:	the &struct bucket_table
+ * @hash:	the hash value / bucket index
+ *
+ * This hash chain list-traversal primitive may safely run concurrently with
+ * the _rcu mutation primitives such as rhashtable_insert() as long as the
+ * traversal is guarded by rcu_read_lock().
+ */
+#define rht_for_each_rcu(pos, tbl, hash)				\
+	rht_for_each_rcu_continue(pos, (tbl)->buckets[hash], tbl, hash)
+
+/**
+ * rht_for_each_entry_rcu_continue - continue iterating over rcu hash chain
+ * @tpos:	the type * to use as a loop cursor.
+ * @pos:	the &struct rhash_head to use as a loop cursor.
+ * @head:	the previous &struct rhash_head to continue from
+ * @tbl:	the &struct bucket_table
+ * @hash:	the hash value / bucket index
+ * @member:	name of the &struct rhash_head within the hashable struct.
+ *
+ * This hash chain list-traversal primitive may safely run concurrently with
+ * the _rcu mutation primitives such as rhashtable_insert() as long as the
+ * traversal is guarded by rcu_read_lock().
+ */
+#define rht_for_each_entry_rcu_continue(tpos, pos, head, tbl, hash, member) \
+	for (({barrier(); }),						    \
+	     pos = rht_dereference_bucket_rcu(head, tbl, hash);		    \
+	     (!rht_is_a_nulls(pos)) && rht_entry(tpos, pos, member);	    \
+	     pos = rht_dereference_bucket_rcu(pos->next, tbl, hash))
+
+/**
+ * rht_for_each_entry_rcu - iterate over rcu hash chain of given type
+ * @tpos:	the type * to use as a loop cursor.
+ * @pos:	the &struct rhash_head to use as a loop cursor.
+ * @tbl:	the &struct bucket_table
+ * @hash:	the hash value / bucket index
+ * @member:	name of the &struct rhash_head within the hashable struct.
+ *
+ * This hash chain list-traversal primitive may safely run concurrently with
+ * the _rcu mutation primitives such as rhashtable_insert() as long as the
+ * traversal is guarded by rcu_read_lock().
+ */
+#define rht_for_each_entry_rcu(tpos, pos, tbl, hash, member)		\
+	rht_for_each_entry_rcu_continue(tpos, pos, (tbl)->buckets[hash],\
+					tbl, hash, member)
+
+static inline int rhashtable_compare(struct rhashtable_compare_arg *arg,
+				     const void *obj)
+{
+	struct rhashtable *ht = arg->ht;
+	const char *ptr = obj;
+
+	return memcmp(ptr + ht->p.key_offset, arg->key, ht->p.key_len);
+}
+
+/**
+ * rhashtable_lookup_fast - search hash table, inlined version
+ * @ht:		hash table
+ * @key:	the pointer to the key
+ * @params:	hash table parameters
+ *
+ * Computes the hash value for the key and traverses the bucket chain looking
+ * for a entry with an identical key. The first matching entry is returned.
+ *
+ * Returns the first entry on which the compare function returned true.
+ */
+static inline void *rhashtable_lookup_fast(
+	struct rhashtable *ht, const void *key,
+	const struct rhashtable_params params)
+{
+	struct rhashtable_compare_arg arg = {
+		.ht = ht,
+		.key = key,
+	};
+	const struct bucket_table *tbl;
+	struct rhash_head *he;
+	unsigned int hash;
+
+	rcu_read_lock();
+
+	tbl = rht_dereference_rcu(ht->tbl, ht);
+restart:
+	hash = rht_key_hashfn(ht, tbl, key, params);
+	rht_for_each_rcu(he, tbl, hash) {
+		if (params.obj_cmpfn ?
+		    params.obj_cmpfn(&arg, rht_obj(ht, he)) :
+		    rhashtable_compare(&arg, rht_obj(ht, he)))
+			continue;
+		rcu_read_unlock();
+		return rht_obj(ht, he);
+	}
+
+	/* Ensure we see any new tables. */
+	smp_rmb();
+
+	tbl = rht_dereference_rcu(tbl->future_tbl, ht);
+	if (unlikely(tbl))
+		goto restart;
+	rcu_read_unlock();
+
+	return NULL;
+}
+
+/* Internal function, please use rhashtable_insert_fast() instead */
+static inline int __rhashtable_insert_fast(
+	struct rhashtable *ht, const void *key, struct rhash_head *obj,
+	const struct rhashtable_params params)
+{
+	struct rhashtable_compare_arg arg = {
+		.ht = ht,
+		.key = key,
+	};
+	struct bucket_table *tbl, *new_tbl;
+	struct rhash_head *head;
+	spinlock_t *lock;
+	unsigned int elasticity;
+	unsigned int hash;
+	int err;
+
+restart:
+	rcu_read_lock();
+
+	tbl = rht_dereference_rcu(ht->tbl, ht);
+
+	/* All insertions must grab the oldest table containing
+	 * the hashed bucket that is yet to be rehashed.
+	 */
+	for (;;) {
+		hash = rht_head_hashfn(ht, tbl, obj, params);
+		lock = rht_bucket_lock(tbl, hash);
+		spin_lock_bh(lock);
+
+		if (tbl->rehash <= hash)
+			break;
+
+		spin_unlock_bh(lock);
+		tbl = rht_dereference_rcu(tbl->future_tbl, ht);
+	}
+
+	new_tbl = rht_dereference_rcu(tbl->future_tbl, ht);
+	if (unlikely(new_tbl)) {
+		tbl = rhashtable_insert_slow(ht, key, obj, new_tbl);
+		if (!IS_ERR_OR_NULL(tbl))
+			goto slow_path;
+
+		err = PTR_ERR(tbl);
+		goto out;
+	}
+
+	err = -E2BIG;
+	if (unlikely(rht_grow_above_max(ht, tbl)))
+		goto out;
+
+	if (unlikely(rht_grow_above_100(ht, tbl))) {
+slow_path:
+		spin_unlock_bh(lock);
+		err = rhashtable_insert_rehash(ht, tbl);
+		rcu_read_unlock();
+		if (err)
+			return err;
+
+		goto restart;
+	}
+
+	err = -EEXIST;
+	elasticity = ht->elasticity;
+	rht_for_each(head, tbl, hash) {
+		if (key &&
+		    unlikely(!(params.obj_cmpfn ?
+			       params.obj_cmpfn(&arg, rht_obj(ht, head)) :
+			       rhashtable_compare(&arg, rht_obj(ht, head)))))
+			goto out;
+		if (!--elasticity)
+			goto slow_path;
+	}
+
+	err = 0;
+
+	head = rht_dereference_bucket(tbl->buckets[hash], tbl, hash);
+
+	RCU_INIT_POINTER(obj->next, head);
+
+	rcu_assign_pointer(tbl->buckets[hash], obj);
+
+	atomic_inc(&ht->nelems);
+	if (rht_grow_above_75(ht, tbl))
+		schedule_work(&ht->run_work);
+
+out:
+	spin_unlock_bh(lock);
+	rcu_read_unlock();
+
+	return err;
+}
+
+/**
+ * rhashtable_insert_fast - insert object into hash table
+ * @ht:		hash table
+ * @obj:	pointer to hash head inside object
+ * @params:	hash table parameters
+ *
+ * Will take a per bucket spinlock to protect against mutual mutations
+ * on the same bucket. Multiple insertions may occur in parallel unless
+ * they map to the same bucket lock.
+ *
+ * It is safe to call this function from atomic context.
+ *
+ * Will trigger an automatic deferred table resizing if the size grows
+ * beyond the watermark indicated by grow_decision() which can be passed
+ * to rhashtable_init().
+ */
+static inline int rhashtable_insert_fast(
+	struct rhashtable *ht, struct rhash_head *obj,
+	const struct rhashtable_params params)
+{
+	return __rhashtable_insert_fast(ht, NULL, obj, params);
+}
+
+/**
+ * rhashtable_lookup_insert_fast - lookup and insert object into hash table
+ * @ht:		hash table
+ * @obj:	pointer to hash head inside object
+ * @params:	hash table parameters
+ *
+ * Locks down the bucket chain in both the old and new table if a resize
+ * is in progress to ensure that writers can't remove from the old table
+ * and can't insert to the new table during the atomic operation of search
+ * and insertion. Searches for duplicates in both the old and new table if
+ * a resize is in progress.
+ *
+ * This lookup function may only be used for fixed key hash table (key_len
+ * parameter set). It will BUG() if used inappropriately.
+ *
+ * It is safe to call this function from atomic context.
+ *
+ * Will trigger an automatic deferred table resizing if the size grows
+ * beyond the watermark indicated by grow_decision() which can be passed
+ * to rhashtable_init().
+ */
+static inline int rhashtable_lookup_insert_fast(
+	struct rhashtable *ht, struct rhash_head *obj,
+	const struct rhashtable_params params)
+{
+	const char *key = rht_obj(ht, obj);
+
+	BUG_ON(ht->p.obj_hashfn);
+
+	return __rhashtable_insert_fast(ht, key + ht->p.key_offset, obj,
+					params);
+}
+
+/**
+ * rhashtable_lookup_insert_key - search and insert object to hash table
+ *				  with explicit key
+ * @ht:		hash table
+ * @key:	key
+ * @obj:	pointer to hash head inside object
+ * @params:	hash table parameters
+ *
+ * Locks down the bucket chain in both the old and new table if a resize
+ * is in progress to ensure that writers can't remove from the old table
+ * and can't insert to the new table during the atomic operation of search
+ * and insertion. Searches for duplicates in both the old and new table if
+ * a resize is in progress.
+ *
+ * Lookups may occur in parallel with hashtable mutations and resizing.
+ *
+ * Will trigger an automatic deferred table resizing if the size grows
+ * beyond the watermark indicated by grow_decision() which can be passed
+ * to rhashtable_init().
+ *
+ * Returns zero on success.
+ */
+static inline int rhashtable_lookup_insert_key(
+	struct rhashtable *ht, const void *key, struct rhash_head *obj,
+	const struct rhashtable_params params)
+{
+	BUG_ON(!ht->p.obj_hashfn || !key);
+
+	return __rhashtable_insert_fast(ht, key, obj, params);
+}
+
+/* Internal function, please use rhashtable_remove_fast() instead */
+static inline int __rhashtable_remove_fast(
+	struct rhashtable *ht, struct bucket_table *tbl,
+	struct rhash_head *obj, const struct rhashtable_params params)
+{
+	struct rhash_head __rcu **pprev;
+	struct rhash_head *he;
+	spinlock_t * lock;
+	unsigned int hash;
+	int err = -ENOENT;
+
+	hash = rht_head_hashfn(ht, tbl, obj, params);
+	lock = rht_bucket_lock(tbl, hash);
+
+	spin_lock_bh(lock);
+
+	pprev = &tbl->buckets[hash];
+	rht_for_each(he, tbl, hash) {
+		if (he != obj) {
+			pprev = &he->next;
+			continue;
+		}
+
+		rcu_assign_pointer(*pprev, obj->next);
+		err = 0;
+		break;
+	}
+
+	spin_unlock_bh(lock);
+
+	return err;
+}
+
+/**
+ * rhashtable_remove_fast - remove object from hash table
+ * @ht:		hash table
+ * @obj:	pointer to hash head inside object
+ * @params:	hash table parameters
+ *
+ * Since the hash chain is single linked, the removal operation needs to
+ * walk the bucket chain upon removal. The removal operation is thus
+ * considerable slow if the hash table is not correctly sized.
+ *
+ * Will automatically shrink the table via rhashtable_expand() if the
+ * shrink_decision function specified at rhashtable_init() returns true.
+ *
+ * Returns zero on success, -ENOENT if the entry could not be found.
+ */
+static inline int rhashtable_remove_fast(
+	struct rhashtable *ht, struct rhash_head *obj,
+	const struct rhashtable_params params)
+{
+	struct bucket_table *tbl;
+	int err;
+
+	rcu_read_lock();
+
+	tbl = rht_dereference_rcu(ht->tbl, ht);
+
+	/* Because we have already taken (and released) the bucket
+	 * lock in old_tbl, if we find that future_tbl is not yet
+	 * visible then that guarantees the entry to still be in
+	 * the old tbl if it exists.
+	 */
+	while ((err = __rhashtable_remove_fast(ht, tbl, obj, params)) &&
+	       (tbl = rht_dereference_rcu(tbl->future_tbl, ht)))
+		;
+
+	if (err)
+		goto out;
+
+	atomic_dec(&ht->nelems);
+	if (unlikely(ht->p.automatic_shrinking &&
+		     rht_shrink_below_30(ht, tbl)))
+		schedule_work(&ht->run_work);
+
+out:
+	rcu_read_unlock();
+
+	return err;
+}
+
+#endif /* _LINUX_RHASHTABLE_H */
+
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/os_dep/linux/rtw_android.c linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/os_dep/linux/rtw_android.c
--- linux-5.6.3/3rdparty/rtl8821ce/os_dep/linux/rtw_android.c	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/os_dep/linux/rtw_android.c	2020-04-10 16:35:06.856661935 +0300
@@ -0,0 +1,1325 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+
+#ifdef CONFIG_GPIO_WAKEUP
+#include <linux/gpio.h>
+#endif
+
+#include <drv_types.h>
+
+#if defined(RTW_ENABLE_WIFI_CONTROL_FUNC)
+#include <linux/platform_device.h>
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 35))
+	#include <linux/wlan_plat.h>
+#else
+	#include <linux/wifi_tiwlan.h>
+#endif
+#endif /* defined(RTW_ENABLE_WIFI_CONTROL_FUNC) */
+
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 0, 0))
+#define strnicmp	strncasecmp
+#endif /* Linux kernel >= 4.0.0 */
+
+#ifdef CONFIG_GPIO_WAKEUP
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#endif
+
+#include "rtw_version.h"
+
+extern void macstr2num(u8 *dst, u8 *src);
+
+const char *android_wifi_cmd_str[ANDROID_WIFI_CMD_MAX] = {
+	"START",
+	"STOP",
+	"SCAN-ACTIVE",
+	"SCAN-PASSIVE",
+	"RSSI",
+	"LINKSPEED",
+	"RXFILTER-START",
+	"RXFILTER-STOP",
+	"RXFILTER-ADD",
+	"RXFILTER-REMOVE",
+	"BTCOEXSCAN-START",
+	"BTCOEXSCAN-STOP",
+	"BTCOEXMODE",
+	"SETSUSPENDOPT",
+	"P2P_DEV_ADDR",
+	"SETFWPATH",
+	"SETBAND",
+	"GETBAND",
+	"COUNTRY",
+	"P2P_SET_NOA",
+	"P2P_GET_NOA",
+	"P2P_SET_PS",
+	"SET_AP_WPS_P2P_IE",
+
+	"MIRACAST",
+
+#ifdef CONFIG_PNO_SUPPORT
+	"PNOSSIDCLR",
+	"PNOSETUP",
+	"PNOFORCE",
+	"PNODEBUG",
+#endif
+
+	"MACADDR",
+
+	"BLOCK_SCAN",
+	"BLOCK",
+	"WFD-ENABLE",
+	"WFD-DISABLE",
+	"WFD-SET-TCPPORT",
+	"WFD-SET-MAXTPUT",
+	"WFD-SET-DEVTYPE",
+	"SET_DTIM",
+	"HOSTAPD_SET_MACADDR_ACL",
+	"HOSTAPD_ACL_ADD_STA",
+	"HOSTAPD_ACL_REMOVE_STA",
+#if defined(CONFIG_GTK_OL) && (LINUX_VERSION_CODE < KERNEL_VERSION(3, 1, 0))
+	"GTK_REKEY_OFFLOAD",
+#endif /* CONFIG_GTK_OL */
+/*	Private command for	P2P disable*/
+	"P2P_DISABLE",
+	"SET_AEK",
+	"DRIVER_VERSION"
+};
+
+#ifdef CONFIG_PNO_SUPPORT
+#define PNO_TLV_PREFIX			'S'
+#define PNO_TLV_VERSION			'1'
+#define PNO_TLV_SUBVERSION		'2'
+#define PNO_TLV_RESERVED		'0'
+#define PNO_TLV_TYPE_SSID_IE	'S'
+#define PNO_TLV_TYPE_TIME		'T'
+#define PNO_TLV_FREQ_REPEAT		'R'
+#define PNO_TLV_FREQ_EXPO_MAX	'M'
+
+typedef struct cmd_tlv {
+	char prefix;
+	char version;
+	char subver;
+	char reserved;
+} cmd_tlv_t;
+
+#ifdef CONFIG_PNO_SET_DEBUG
+char pno_in_example[] = {
+	'P', 'N', 'O', 'S', 'E', 'T', 'U', 'P', ' ',
+	'S', '1', '2', '0',
+	'S',	/* 1 */
+	0x05,
+	'd', 'l', 'i', 'n', 'k',
+	'S',	/* 2 */
+	0x06,
+	'B', 'U', 'F', 'B', 'U', 'F',
+	'S',	/* 3 */
+	0x20,
+	'a', 'b', 'c', 'd', 'e', 'f', 'g', 'h', 'i', 'j', 'k', 'l', 'm', 'n', 'o', 'p', 'q', 'r', 's', 't', 'u', 'v', 'w', 'x', 'y', 'z', '!', '@', '#', '$', '%', '^',
+	'S',	/* 4 */
+	0x0a,
+	'!', '@', '#', '$', '%', '^', '&', '*', '(', ')',
+	'T',
+	'0', '5',
+	'R',
+	'2',
+	'M',
+	'2',
+	0x00
+};
+#endif /* CONFIG_PNO_SET_DEBUG */
+#endif /* PNO_SUPPORT */
+
+typedef struct android_wifi_priv_cmd {
+	char *buf;
+	int used_len;
+	int total_len;
+} android_wifi_priv_cmd;
+
+#ifdef CONFIG_COMPAT
+typedef struct compat_android_wifi_priv_cmd {
+	compat_uptr_t buf;
+	int used_len;
+	int total_len;
+} compat_android_wifi_priv_cmd;
+#endif /* CONFIG_COMPAT */
+
+/**
+ * Local (static) functions and variables
+ */
+
+/* Initialize g_wifi_on to 1 so dhd_bus_start will be called for the first
+ * time (only) in dhd_open, subsequential wifi on will be handled by
+ * wl_android_wifi_on
+ */
+static int g_wifi_on = _TRUE;
+
+unsigned int oob_irq = 0;
+unsigned int oob_gpio = 0;
+
+#ifdef CONFIG_PNO_SUPPORT
+/*
+ * rtw_android_pno_setup
+ * Description:
+ * This is used for private command.
+ *
+ * Parameter:
+ * net: net_device
+ * command: parameters from private command
+ * total_len: the length of the command.
+ *
+ * */
+static int rtw_android_pno_setup(struct net_device *net, char *command, int total_len)
+{
+	pno_ssid_t pno_ssids_local[MAX_PNO_LIST_COUNT];
+	int res = -1;
+	int nssid = 0;
+	cmd_tlv_t *cmd_tlv_temp;
+	char *str_ptr;
+	int tlv_size_left;
+	int pno_time = 0;
+	int pno_repeat = 0;
+	int pno_freq_expo_max = 0;
+	int cmdlen = strlen(android_wifi_cmd_str[ANDROID_WIFI_CMD_PNOSETUP_SET]) + 1;
+
+#ifdef CONFIG_PNO_SET_DEBUG
+	int i;
+	char *p;
+	p = pno_in_example;
+
+	total_len = sizeof(pno_in_example);
+	str_ptr = p + cmdlen;
+#else
+	str_ptr = command + cmdlen;
+#endif
+
+	if (total_len < (cmdlen + sizeof(cmd_tlv_t))) {
+		RTW_INFO("%s argument=%d less min size\n", __func__, total_len);
+		goto exit_proc;
+	}
+
+	tlv_size_left = total_len - cmdlen;
+
+	cmd_tlv_temp = (cmd_tlv_t *)str_ptr;
+	memset(pno_ssids_local, 0, sizeof(pno_ssids_local));
+
+	if ((cmd_tlv_temp->prefix == PNO_TLV_PREFIX) &&
+	    (cmd_tlv_temp->version == PNO_TLV_VERSION) &&
+	    (cmd_tlv_temp->subver == PNO_TLV_SUBVERSION)) {
+
+		str_ptr += sizeof(cmd_tlv_t);
+		tlv_size_left -= sizeof(cmd_tlv_t);
+
+		nssid = rtw_parse_ssid_list_tlv(&str_ptr, pno_ssids_local,
+			     MAX_PNO_LIST_COUNT, &tlv_size_left);
+		if (nssid <= 0) {
+			RTW_INFO("SSID is not presented or corrupted ret=%d\n", nssid);
+			goto exit_proc;
+		} else {
+			if ((str_ptr[0] != PNO_TLV_TYPE_TIME) || (tlv_size_left <= 1)) {
+				RTW_INFO("%s scan duration corrupted field size %d\n",
+					 __func__, tlv_size_left);
+				goto exit_proc;
+			}
+			str_ptr++;
+			pno_time = simple_strtoul(str_ptr, &str_ptr, 16);
+			RTW_INFO("%s: pno_time=%d\n", __func__, pno_time);
+
+			if (str_ptr[0] != 0) {
+				if ((str_ptr[0] != PNO_TLV_FREQ_REPEAT)) {
+					RTW_INFO("%s pno repeat : corrupted field\n",
+						 __func__);
+					goto exit_proc;
+				}
+				str_ptr++;
+				pno_repeat = simple_strtoul(str_ptr, &str_ptr, 16);
+				RTW_INFO("%s :got pno_repeat=%d\n", __FUNCTION__, pno_repeat);
+				if (str_ptr[0] != PNO_TLV_FREQ_EXPO_MAX) {
+					RTW_INFO("%s FREQ_EXPO_MAX corrupted field size\n",
+						 __func__);
+					goto exit_proc;
+				}
+				str_ptr++;
+				pno_freq_expo_max = simple_strtoul(str_ptr, &str_ptr, 16);
+				RTW_INFO("%s: pno_freq_expo_max=%d\n",
+					 __func__, pno_freq_expo_max);
+			}
+		}
+	} else {
+		RTW_INFO("%s get wrong TLV command\n", __FUNCTION__);
+		goto exit_proc;
+	}
+
+	res = rtw_dev_pno_set(net, pno_ssids_local, nssid, pno_time, pno_repeat, pno_freq_expo_max);
+
+#ifdef CONFIG_PNO_SET_DEBUG
+	rtw_dev_pno_debug(net);
+#endif
+
+exit_proc:
+	return res;
+}
+
+/*
+ * rtw_android_cfg80211_pno_setup
+ * Description:
+ * This is used for cfg80211 sched_scan.
+ *
+ * Parameter:
+ * net: net_device
+ * request: cfg80211_request
+ * */
+
+int rtw_android_cfg80211_pno_setup(struct net_device *net,
+		   struct cfg80211_ssid *ssids, int n_ssids, int interval)
+{
+	int res = -1;
+	int nssid = 0;
+	int pno_time = 0;
+	int pno_repeat = 0;
+	int pno_freq_expo_max = 0;
+	int index = 0;
+	pno_ssid_t pno_ssids_local[MAX_PNO_LIST_COUNT];
+
+	if (n_ssids > MAX_PNO_LIST_COUNT || n_ssids < 0) {
+		RTW_INFO("%s: nssids(%d) is invalid.\n", __func__, n_ssids);
+		return -EINVAL;
+	}
+
+	memset(pno_ssids_local, 0, sizeof(pno_ssids_local));
+
+	nssid = n_ssids;
+
+	for (index = 0 ; index < nssid ; index++) {
+		pno_ssids_local[index].SSID_len = ssids[index].ssid_len;
+		memcpy(pno_ssids_local[index].SSID, ssids[index].ssid,
+		       ssids[index].ssid_len);
+	}
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(3, 2, 0)
+	if(ssids)
+		rtw_mfree((u8 *)ssids, (n_ssids * sizeof(struct cfg80211_ssid)));
+#endif
+	pno_time = (interval / 1000);
+
+	RTW_INFO("%s: nssids: %d, pno_time=%d\n", __func__, nssid, pno_time);
+
+	res = rtw_dev_pno_set(net, pno_ssids_local, nssid, pno_time,
+			      pno_repeat, pno_freq_expo_max);
+
+#ifdef CONFIG_PNO_SET_DEBUG
+	rtw_dev_pno_debug(net);
+#endif
+exit_proc:
+	return res;
+}
+
+int rtw_android_pno_enable(struct net_device *net, int pno_enable)
+{
+	_adapter *padapter = (_adapter *)rtw_netdev_priv(net);
+	struct pwrctrl_priv *pwrctl = adapter_to_pwrctl(padapter);
+
+	if (pwrctl) {
+		pwrctl->wowlan_pno_enable = pno_enable;
+		RTW_INFO("%s: wowlan_pno_enable: %d\n", __func__, pwrctl->wowlan_pno_enable);
+		if (pwrctl->wowlan_pno_enable == 0) {
+			if (pwrctl->pnlo_info != NULL) {
+				rtw_mfree((u8 *)pwrctl->pnlo_info, sizeof(pno_nlo_info_t));
+				pwrctl->pnlo_info = NULL;
+			}
+			if (pwrctl->pno_ssid_list != NULL) {
+				rtw_mfree((u8 *)pwrctl->pno_ssid_list, sizeof(pno_ssid_list_t));
+				pwrctl->pno_ssid_list = NULL;
+			}
+			if (pwrctl->pscan_info != NULL) {
+				rtw_mfree((u8 *)pwrctl->pscan_info, sizeof(pno_scan_info_t));
+				pwrctl->pscan_info = NULL;
+			}
+		}
+		return 0;
+	} else
+		return -1;
+}
+#endif /* CONFIG_PNO_SUPPORT */
+
+int rtw_android_cmdstr_to_num(char *cmdstr)
+{
+	int cmd_num;
+	for (cmd_num = 0 ; cmd_num < ANDROID_WIFI_CMD_MAX; cmd_num++)
+		if (0 == strnicmp(cmdstr , android_wifi_cmd_str[cmd_num], strlen(android_wifi_cmd_str[cmd_num])))
+			break;
+
+	return cmd_num;
+}
+
+int rtw_android_get_rssi(struct net_device *net, char *command, int total_len)
+{
+	_adapter *padapter = (_adapter *)rtw_netdev_priv(net);
+	struct	mlme_priv	*pmlmepriv = &(padapter->mlmepriv);
+	struct	wlan_network	*pcur_network = &pmlmepriv->cur_network;
+	int bytes_written = 0;
+
+	if (check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE) {
+		bytes_written += snprintf(&command[bytes_written], total_len, "%s rssi %d",
+			pcur_network->network.Ssid.Ssid, padapter->recvpriv.rssi);
+	}
+
+	return bytes_written;
+}
+
+int rtw_android_get_link_speed(struct net_device *net, char *command, int total_len)
+{
+	_adapter *padapter = (_adapter *)rtw_netdev_priv(net);
+	int bytes_written = 0;
+	u16 link_speed = 0;
+
+	link_speed = rtw_get_cur_max_rate(padapter) / 10;
+	bytes_written = snprintf(command, total_len, "LinkSpeed %d", link_speed);
+
+	return bytes_written;
+}
+
+int rtw_android_get_macaddr(struct net_device *net, char *command, int total_len)
+{
+	int bytes_written = 0;
+
+	bytes_written = snprintf(command, total_len, "Macaddr = "MAC_FMT, MAC_ARG(net->dev_addr));
+	return bytes_written;
+}
+
+int rtw_android_set_country(struct net_device *net, char *command, int total_len)
+{
+	_adapter *adapter = (_adapter *)rtw_netdev_priv(net);
+	char *country_code = command + strlen(android_wifi_cmd_str[ANDROID_WIFI_CMD_COUNTRY]) + 1;
+	int ret = _FAIL;
+
+	ret = rtw_set_country(adapter, country_code);
+
+	return (ret == _SUCCESS) ? 0 : -1;
+}
+
+int rtw_android_get_p2p_dev_addr(struct net_device *net, char *command, int total_len)
+{
+	int bytes_written = 0;
+
+	/* We use the same address as our HW MAC address */
+	_rtw_memcpy(command, net->dev_addr, ETH_ALEN);
+
+	bytes_written = ETH_ALEN;
+	return bytes_written;
+}
+
+int rtw_android_set_block_scan(struct net_device *net, char *command, int total_len)
+{
+	_adapter *adapter = (_adapter *)rtw_netdev_priv(net);
+	char *block_value = command + strlen(android_wifi_cmd_str[ANDROID_WIFI_CMD_BLOCK_SCAN]) + 1;
+
+#ifdef CONFIG_IOCTL_CFG80211
+	adapter_wdev_data(adapter)->block_scan = (*block_value == '0') ? _FALSE : _TRUE;
+#endif
+
+	return 0;
+}
+
+int rtw_android_set_block(struct net_device *net, char *command, int total_len)
+{
+	_adapter *adapter = (_adapter *)rtw_netdev_priv(net);
+	char *block_value = command + strlen(android_wifi_cmd_str[ANDROID_WIFI_CMD_BLOCK]) + 1;
+
+#ifdef CONFIG_IOCTL_CFG80211
+	adapter_wdev_data(adapter)->block = (*block_value == '0') ? _FALSE : _TRUE;
+#endif
+
+	return 0;
+}
+
+int rtw_android_setband(struct net_device *net, char *command, int total_len)
+{
+	_adapter *adapter = (_adapter *)rtw_netdev_priv(net);
+	char *arg = command + strlen(android_wifi_cmd_str[ANDROID_WIFI_CMD_SETBAND]) + 1;
+	u32 band = WIFI_FREQUENCY_BAND_AUTO;
+	int ret = _FAIL;
+
+	if (sscanf(arg, "%u", &band) >= 1)
+		ret = rtw_set_band(adapter, band);
+
+	return (ret == _SUCCESS) ? 0 : -1;
+}
+
+int rtw_android_getband(struct net_device *net, char *command, int total_len)
+{
+	_adapter *adapter = (_adapter *)rtw_netdev_priv(net);
+	int bytes_written = 0;
+
+	bytes_written = snprintf(command, total_len, "%u", adapter->setband);
+
+	return bytes_written;
+}
+
+#ifdef CONFIG_WFD
+int rtw_android_set_miracast_mode(struct net_device *net, char *command, int total_len)
+{
+	_adapter *adapter = (_adapter *)rtw_netdev_priv(net);
+	struct wifi_display_info *wfd_info = &adapter->wfd_info;
+	char *arg = command + strlen(android_wifi_cmd_str[ANDROID_WIFI_CMD_MIRACAST]) + 1;
+	u8 mode;
+	int num;
+	int ret = _FAIL;
+
+	num = sscanf(arg, "%hhu", &mode);
+
+	if (num < 1)
+		goto exit;
+
+	switch (mode) {
+	case 1: /* soruce */
+		mode = MIRACAST_SOURCE;
+		break;
+	case 2: /* sink */
+		mode = MIRACAST_SINK;
+		break;
+	case 0: /* disabled */
+	default:
+		mode = MIRACAST_DISABLED;
+		break;
+	}
+	wfd_info->stack_wfd_mode = mode;
+	RTW_INFO("stack miracast mode: %s\n", get_miracast_mode_str(wfd_info->stack_wfd_mode));
+
+	ret = _SUCCESS;
+
+exit:
+	return (ret == _SUCCESS) ? 0 : -1;
+}
+#endif /* CONFIG_WFD */
+
+int get_int_from_command(char *pcmd)
+{
+	int i = 0;
+
+	for (i = 0; i < strlen(pcmd); i++) {
+		if (pcmd[i] == '=') {
+			/*	Skip the '=' and space characters. */
+			i += 2;
+			break;
+		}
+	}
+	return rtw_atoi(pcmd + i) ;
+}
+
+#if defined(CONFIG_GTK_OL) && (LINUX_VERSION_CODE < KERNEL_VERSION(3, 1, 0))
+int rtw_gtk_offload(struct net_device *net, u8 *cmd_ptr)
+{
+	int i;
+	/* u8 *cmd_ptr = priv_cmd.buf; */
+	struct sta_info *psta;
+	_adapter *padapter = (_adapter *)rtw_netdev_priv(net);
+	struct mlme_priv	*pmlmepriv = &padapter->mlmepriv;
+	struct sta_priv *pstapriv = &padapter->stapriv;
+	struct security_priv *psecuritypriv = &(padapter->securitypriv);
+	psta = rtw_get_stainfo(pstapriv, get_bssid(pmlmepriv));
+
+
+	if (psta == NULL)
+		RTW_INFO("%s, : Obtain Sta_info fail\n", __func__);
+	else {
+		/* string command length of "GTK_REKEY_OFFLOAD" */
+		cmd_ptr += 18;
+
+		_rtw_memcpy(psta->kek, cmd_ptr, RTW_KEK_LEN);
+		cmd_ptr += RTW_KEK_LEN;
+		/*
+		printk("supplicant KEK: ");
+		for(i=0;i<RTW_KEK_LEN; i++)
+			printk(" %02x ", psta->kek[i]);
+		printk("\n supplicant KCK: ");
+		*/
+		_rtw_memcpy(psta->kck, cmd_ptr, RTW_KCK_LEN);
+		cmd_ptr += RTW_KCK_LEN;
+		/*
+		for(i=0;i<RTW_KEK_LEN; i++)
+			printk(" %02x ", psta->kck[i]);
+		*/
+		_rtw_memcpy(psta->replay_ctr, cmd_ptr, RTW_REPLAY_CTR_LEN);
+		psecuritypriv->binstallKCK_KEK = _TRUE;
+
+		/* printk("\nREPLAY_CTR: "); */
+		/* for(i=0;i<RTW_REPLAY_CTR_LEN; i++) */
+		/* printk(" %02x ", psta->replay_ctr[i]); */
+	}
+
+	return _SUCCESS;
+}
+#endif /* CONFIG_GTK_OL */
+
+#ifdef CONFIG_RTW_MESH_AEK
+static int rtw_android_set_aek(struct net_device *ndev, char *command, int total_len)
+{
+#define SET_AEK_DATA_LEN (ETH_ALEN + 32)
+
+	_adapter *adapter = (_adapter *)rtw_netdev_priv(ndev);
+	u8 *addr;
+	u8 *aek;
+	int err = 0;
+
+	if (total_len - strlen(android_wifi_cmd_str[ANDROID_WIFI_CMD_SET_AEK]) - 1 != SET_AEK_DATA_LEN) {
+		err = -EINVAL;
+		goto exit;
+	}
+
+	addr = command + strlen(android_wifi_cmd_str[ANDROID_WIFI_CMD_SET_AEK]) + 1;
+	aek = addr + ETH_ALEN;
+
+	RTW_PRINT(FUNC_NDEV_FMT" addr="MAC_FMT"\n"
+		, FUNC_NDEV_ARG(ndev), MAC_ARG(addr));
+	if (0)
+		RTW_PRINT(FUNC_NDEV_FMT" aek="KEY_FMT KEY_FMT"\n"
+			, FUNC_NDEV_ARG(ndev), KEY_ARG(aek), KEY_ARG(aek + 16));
+
+	if (rtw_mesh_plink_set_aek(adapter, addr, aek) != _SUCCESS)
+		err = -ENOENT;
+
+exit:
+	return err;
+}
+#endif /* CONFIG_RTW_MESH_AEK */
+
+int rtw_android_priv_cmd(struct net_device *net, struct ifreq *ifr, int cmd)
+{
+	#define PRIVATE_COMMAND_MAX_LEN        8192
+	int ret = 0;
+	char *command = NULL;
+	int cmd_num;
+	int bytes_written = 0;
+#ifdef CONFIG_PNO_SUPPORT
+	uint cmdlen = 0;
+	uint pno_enable = 0;
+#endif
+	android_wifi_priv_cmd priv_cmd;
+	_adapter	*padapter = (_adapter *) rtw_netdev_priv(net);
+#ifdef CONFIG_WFD
+	struct wifi_display_info		*pwfd_info;
+#endif
+
+	rtw_lock_suspend();
+
+	if (!ifr->ifr_data) {
+		ret = -EINVAL;
+		goto exit;
+	}
+	if (padapter->registrypriv.mp_mode == 1) {
+		ret = -EINVAL;
+		goto exit;
+	}
+#ifdef CONFIG_COMPAT
+#if (KERNEL_VERSION(4, 6, 0) > LINUX_VERSION_CODE)
+	if (is_compat_task()) {
+#else
+	if (in_compat_syscall()) {
+#endif
+		/* User space is 32-bit, use compat ioctl */
+		compat_android_wifi_priv_cmd compat_priv_cmd;
+
+		if (copy_from_user(&compat_priv_cmd, ifr->ifr_data, sizeof(compat_android_wifi_priv_cmd))) {
+			ret = -EFAULT;
+			goto exit;
+		}
+		priv_cmd.buf = compat_ptr(compat_priv_cmd.buf);
+		priv_cmd.used_len = compat_priv_cmd.used_len;
+		priv_cmd.total_len = compat_priv_cmd.total_len;
+	} else
+#endif /* CONFIG_COMPAT */
+		if (copy_from_user(&priv_cmd, ifr->ifr_data, sizeof(android_wifi_priv_cmd))) {
+			ret = -EFAULT;
+			goto exit;
+		}
+	if (padapter->registrypriv.mp_mode == 1) {
+		ret = -EFAULT;
+		goto exit;
+	}
+	/*RTW_INFO("%s priv_cmd.buf=%p priv_cmd.total_len=%d  priv_cmd.used_len=%d\n",__func__,priv_cmd.buf,priv_cmd.total_len,priv_cmd.used_len);*/
+	if (priv_cmd.total_len > PRIVATE_COMMAND_MAX_LEN || priv_cmd.total_len < 0) {
+		RTW_WARN("%s: invalid private command (%d)\n", __FUNCTION__,
+			priv_cmd.total_len);
+		ret = -EFAULT;
+		goto exit;
+	}
+	
+	command = rtw_zmalloc(priv_cmd.total_len+1);
+	if (!command) {
+		RTW_INFO("%s: failed to allocate memory\n", __FUNCTION__);
+		ret = -ENOMEM;
+		goto exit;
+	}
+
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5,0,0))
+	if (!access_ok(priv_cmd.buf, priv_cmd.total_len)) {
+#else
+	if (!access_ok(VERIFY_READ, priv_cmd.buf, priv_cmd.total_len)) {
+#endif
+		RTW_INFO("%s: failed to access memory\n", __FUNCTION__);
+		ret = -EFAULT;
+		goto exit;
+	}
+	if (copy_from_user(command, (void *)priv_cmd.buf, priv_cmd.total_len)) {
+		ret = -EFAULT;
+		goto exit;
+	}
+	command[priv_cmd.total_len] = '\0';
+	RTW_INFO("%s: Android private cmd \"%s\" on %s\n"
+		 , __FUNCTION__, command, ifr->ifr_name);
+
+	cmd_num = rtw_android_cmdstr_to_num(command);
+
+	switch (cmd_num) {
+	case ANDROID_WIFI_CMD_START:
+		/* bytes_written = wl_android_wifi_on(net); */
+		goto response;
+	case ANDROID_WIFI_CMD_SETFWPATH:
+		goto response;
+	}
+
+	if (!g_wifi_on) {
+		RTW_INFO("%s: Ignore private cmd \"%s\" - iface %s is down\n"
+			 , __FUNCTION__, command, ifr->ifr_name);
+		ret = 0;
+		goto exit;
+	}
+
+	if (!hal_chk_wl_func(padapter, WL_FUNC_MIRACAST)) {
+		switch (cmd_num) {
+		case ANDROID_WIFI_CMD_WFD_ENABLE:
+		case ANDROID_WIFI_CMD_WFD_DISABLE:
+		case ANDROID_WIFI_CMD_WFD_SET_TCPPORT:
+		case ANDROID_WIFI_CMD_WFD_SET_MAX_TPUT:
+		case ANDROID_WIFI_CMD_WFD_SET_DEVTYPE:
+			goto response;
+		}
+	}
+
+	switch (cmd_num) {
+
+	case ANDROID_WIFI_CMD_STOP:
+		/* bytes_written = wl_android_wifi_off(net); */
+		break;
+
+	case ANDROID_WIFI_CMD_SCAN_ACTIVE:
+		/* rtw_set_scan_mode((_adapter *)rtw_netdev_priv(net), SCAN_ACTIVE); */
+#ifdef CONFIG_PLATFORM_MSTAR
+#ifdef CONFIG_IOCTL_CFG80211
+		adapter_wdev_data((_adapter *)rtw_netdev_priv(net))->bandroid_scan = _TRUE;
+#endif /* CONFIG_IOCTL_CFG80211 */
+#endif /* CONFIG_PLATFORM_MSTAR */
+		break;
+	case ANDROID_WIFI_CMD_SCAN_PASSIVE:
+		/* rtw_set_scan_mode((_adapter *)rtw_netdev_priv(net), SCAN_PASSIVE); */
+		break;
+
+	case ANDROID_WIFI_CMD_RSSI:
+		bytes_written = rtw_android_get_rssi(net, command, priv_cmd.total_len);
+		break;
+	case ANDROID_WIFI_CMD_LINKSPEED:
+		bytes_written = rtw_android_get_link_speed(net, command, priv_cmd.total_len);
+		break;
+
+	case ANDROID_WIFI_CMD_MACADDR:
+		bytes_written = rtw_android_get_macaddr(net, command, priv_cmd.total_len);
+		break;
+
+	case ANDROID_WIFI_CMD_BLOCK_SCAN:
+		bytes_written = rtw_android_set_block_scan(net, command, priv_cmd.total_len);
+		break;
+
+	case ANDROID_WIFI_CMD_BLOCK:
+		bytes_written = rtw_android_set_block(net, command, priv_cmd.total_len);
+		break;
+
+	case ANDROID_WIFI_CMD_RXFILTER_START:
+		/* bytes_written = net_os_set_packet_filter(net, 1); */
+		break;
+	case ANDROID_WIFI_CMD_RXFILTER_STOP:
+		/* bytes_written = net_os_set_packet_filter(net, 0); */
+		break;
+	case ANDROID_WIFI_CMD_RXFILTER_ADD:
+		/* int filter_num = *(command + strlen(CMD_RXFILTER_ADD) + 1) - '0'; */
+		/* bytes_written = net_os_rxfilter_add_remove(net, TRUE, filter_num); */
+		break;
+	case ANDROID_WIFI_CMD_RXFILTER_REMOVE:
+		/* int filter_num = *(command + strlen(CMD_RXFILTER_REMOVE) + 1) - '0'; */
+		/* bytes_written = net_os_rxfilter_add_remove(net, FALSE, filter_num); */
+		break;
+
+	case ANDROID_WIFI_CMD_BTCOEXSCAN_START:
+		/* TBD: BTCOEXSCAN-START */
+		break;
+	case ANDROID_WIFI_CMD_BTCOEXSCAN_STOP:
+		/* TBD: BTCOEXSCAN-STOP */
+		break;
+	case ANDROID_WIFI_CMD_BTCOEXMODE:
+#if 0
+		uint mode = *(command + strlen(CMD_BTCOEXMODE) + 1) - '0';
+		if (mode == 1)
+			net_os_set_packet_filter(net, 0); /* DHCP starts */
+		else
+			net_os_set_packet_filter(net, 1); /* DHCP ends */
+#ifdef WL_CFG80211
+		bytes_written = wl_cfg80211_set_btcoex_dhcp(net, command);
+#endif
+#endif
+		break;
+
+	case ANDROID_WIFI_CMD_SETSUSPENDOPT:
+		/* bytes_written = wl_android_set_suspendopt(net, command, priv_cmd.total_len); */
+		break;
+
+	case ANDROID_WIFI_CMD_SETBAND:
+		bytes_written = rtw_android_setband(net, command, priv_cmd.total_len);
+		break;
+
+	case ANDROID_WIFI_CMD_GETBAND:
+		bytes_written = rtw_android_getband(net, command, priv_cmd.total_len);
+		break;
+
+	case ANDROID_WIFI_CMD_COUNTRY:
+		bytes_written = rtw_android_set_country(net, command, priv_cmd.total_len);
+		break;
+
+#ifdef CONFIG_PNO_SUPPORT
+	case ANDROID_WIFI_CMD_PNOSSIDCLR_SET:
+		/* bytes_written = dhd_dev_pno_reset(net); */
+		break;
+	case ANDROID_WIFI_CMD_PNOSETUP_SET:
+		bytes_written = rtw_android_pno_setup(net, command, priv_cmd.total_len);
+		break;
+	case ANDROID_WIFI_CMD_PNOENABLE_SET:
+		cmdlen = strlen(android_wifi_cmd_str[ANDROID_WIFI_CMD_PNOENABLE_SET]);
+		pno_enable = *(command + cmdlen + 1) - '0';
+		bytes_written = rtw_android_pno_enable(net, pno_enable);
+		break;
+#endif
+
+	case ANDROID_WIFI_CMD_P2P_DEV_ADDR:
+		bytes_written = rtw_android_get_p2p_dev_addr(net, command, priv_cmd.total_len);
+		break;
+	case ANDROID_WIFI_CMD_P2P_SET_NOA:
+		/* int skip = strlen(CMD_P2P_SET_NOA) + 1; */
+		/* bytes_written = wl_cfg80211_set_p2p_noa(net, command + skip, priv_cmd.total_len - skip); */
+		break;
+	case ANDROID_WIFI_CMD_P2P_GET_NOA:
+		/* bytes_written = wl_cfg80211_get_p2p_noa(net, command, priv_cmd.total_len); */
+		break;
+	case ANDROID_WIFI_CMD_P2P_SET_PS:
+		/* int skip = strlen(CMD_P2P_SET_PS) + 1; */
+		/* bytes_written = wl_cfg80211_set_p2p_ps(net, command + skip, priv_cmd.total_len - skip); */
+		break;
+
+#ifdef CONFIG_IOCTL_CFG80211
+	case ANDROID_WIFI_CMD_SET_AP_WPS_P2P_IE: {
+		int skip = strlen(android_wifi_cmd_str[ANDROID_WIFI_CMD_SET_AP_WPS_P2P_IE]) + 3;
+		bytes_written = rtw_cfg80211_set_mgnt_wpsp2pie(net, command + skip, priv_cmd.total_len - skip, *(command + skip - 2) - '0');
+		break;
+	}
+#endif /* CONFIG_IOCTL_CFG80211 */
+
+#ifdef CONFIG_WFD
+
+	case ANDROID_WIFI_CMD_MIRACAST:
+		bytes_written = rtw_android_set_miracast_mode(net, command, priv_cmd.total_len);
+		break;
+
+	case ANDROID_WIFI_CMD_WFD_ENABLE: {
+		/*	Commented by Albert 2012/07/24 */
+		/*	We can enable the WFD function by using the following command: */
+		/*	wpa_cli driver wfd-enable */
+
+		if (padapter->wdinfo.driver_interface == DRIVER_CFG80211)
+			rtw_wfd_enable(padapter, 1);
+		break;
+	}
+
+	case ANDROID_WIFI_CMD_WFD_DISABLE: {
+		/*	Commented by Albert 2012/07/24 */
+		/*	We can disable the WFD function by using the following command: */
+		/*	wpa_cli driver wfd-disable */
+
+		if (padapter->wdinfo.driver_interface == DRIVER_CFG80211)
+			rtw_wfd_enable(padapter, 0);
+		break;
+	}
+	case ANDROID_WIFI_CMD_WFD_SET_TCPPORT: {
+		/*	Commented by Albert 2012/07/24 */
+		/*	We can set the tcp port number by using the following command: */
+		/*	wpa_cli driver wfd-set-tcpport = 554 */
+
+		if (padapter->wdinfo.driver_interface == DRIVER_CFG80211)
+			rtw_wfd_set_ctrl_port(padapter, (u16)get_int_from_command(command));
+		break;
+	}
+	case ANDROID_WIFI_CMD_WFD_SET_MAX_TPUT: {
+		break;
+	}
+	case ANDROID_WIFI_CMD_WFD_SET_DEVTYPE: {
+		/*	Commented by Albert 2012/08/28 */
+		/*	Specify the WFD device type ( WFD source/primary sink ) */
+
+		pwfd_info = &padapter->wfd_info;
+		if (padapter->wdinfo.driver_interface == DRIVER_CFG80211) {
+			pwfd_info->wfd_device_type = (u8) get_int_from_command(command);
+			pwfd_info->wfd_device_type &= WFD_DEVINFO_DUAL;
+		}
+		break;
+	}
+#endif
+	case ANDROID_WIFI_CMD_CHANGE_DTIM: {
+#ifdef CONFIG_LPS
+		u8 dtim;
+		u8 *ptr = (u8 *) command;
+
+		ptr += 9;/* string command length of  "SET_DTIM"; */
+
+		dtim = rtw_atoi(ptr);
+
+		RTW_INFO("DTIM=%d\n", dtim);
+
+		rtw_lps_change_dtim_cmd(padapter, dtim);
+#endif
+	}
+	break;
+
+#if CONFIG_RTW_MACADDR_ACL
+	case ANDROID_WIFI_CMD_HOSTAPD_SET_MACADDR_ACL: {
+		rtw_set_macaddr_acl(padapter, RTW_ACL_PERIOD_BSS, get_int_from_command(command));
+		break;
+	}
+	case ANDROID_WIFI_CMD_HOSTAPD_ACL_ADD_STA: {
+		u8 addr[ETH_ALEN] = {0x00};
+		macstr2num(addr, command + strlen("HOSTAPD_ACL_ADD_STA") + 3);	/* 3 is space bar + "=" + space bar these 3 chars */
+		rtw_acl_add_sta(padapter, RTW_ACL_PERIOD_BSS, addr);
+		break;
+	}
+	case ANDROID_WIFI_CMD_HOSTAPD_ACL_REMOVE_STA: {
+		u8 addr[ETH_ALEN] = {0x00};
+		macstr2num(addr, command + strlen("HOSTAPD_ACL_REMOVE_STA") + 3);	/* 3 is space bar + "=" + space bar these 3 chars */
+		rtw_acl_remove_sta(padapter, RTW_ACL_PERIOD_BSS, addr);
+		break;
+	}
+#endif /* CONFIG_RTW_MACADDR_ACL */
+#if defined(CONFIG_GTK_OL) && (LINUX_VERSION_CODE < KERNEL_VERSION(3, 1, 0))
+	case ANDROID_WIFI_CMD_GTK_REKEY_OFFLOAD:
+		rtw_gtk_offload(net, (u8 *)command);
+		break;
+#endif /* CONFIG_GTK_OL		 */
+	case ANDROID_WIFI_CMD_P2P_DISABLE: {
+#ifdef CONFIG_P2P
+		rtw_p2p_enable(padapter, P2P_ROLE_DISABLE);
+#endif /* CONFIG_P2P */
+		break;
+	}
+
+#ifdef CONFIG_RTW_MESH_AEK
+	case ANDROID_WIFI_CMD_SET_AEK:
+		bytes_written = rtw_android_set_aek(net, command, priv_cmd.total_len);
+		break;
+#endif
+	
+	case ANDROID_WIFI_CMD_DRIVERVERSION: {
+		bytes_written = strlen(DRIVERVERSION);
+		snprintf(command, bytes_written + 1, DRIVERVERSION);
+		break;
+	}
+	default:
+		RTW_INFO("Unknown PRIVATE command %s - ignored\n", command);
+		snprintf(command, 3, "OK");
+		bytes_written = strlen("OK");
+	}
+
+response:
+	if (bytes_written >= 0) {
+		if ((bytes_written == 0) && (priv_cmd.total_len > 0))
+			command[0] = '\0';
+		if (bytes_written >= priv_cmd.total_len) {
+			RTW_INFO("%s: bytes_written = %d\n", __FUNCTION__, bytes_written);
+			bytes_written = priv_cmd.total_len;
+		} else
+			bytes_written++;
+		priv_cmd.used_len = bytes_written;
+		if (copy_to_user((void *)priv_cmd.buf, command, bytes_written)) {
+			RTW_INFO("%s: failed to copy data to user buffer\n", __FUNCTION__);
+			ret = -EFAULT;
+		}
+	} else
+		ret = bytes_written;
+
+exit:
+	rtw_unlock_suspend();
+	if (command)
+		rtw_mfree(command, priv_cmd.total_len);
+
+	return ret;
+}
+
+
+/**
+ * Functions for Android WiFi card detection
+ */
+#if defined(RTW_ENABLE_WIFI_CONTROL_FUNC)
+
+static int g_wifidev_registered = 0;
+static struct semaphore wifi_control_sem;
+static struct wifi_platform_data *wifi_control_data = NULL;
+static struct resource *wifi_irqres = NULL;
+
+static int wifi_add_dev(void);
+static void wifi_del_dev(void);
+
+int rtw_android_wifictrl_func_add(void)
+{
+	int ret = 0;
+	sema_init(&wifi_control_sem, 0);
+
+	ret = wifi_add_dev();
+	if (ret) {
+		RTW_INFO("%s: platform_driver_register failed\n", __FUNCTION__);
+		return ret;
+	}
+	g_wifidev_registered = 1;
+
+	/* Waiting callback after platform_driver_register is done or exit with error */
+	if (down_timeout(&wifi_control_sem,  msecs_to_jiffies(1000)) != 0) {
+		ret = -EINVAL;
+		RTW_INFO("%s: platform_driver_register timeout\n", __FUNCTION__);
+	}
+
+	return ret;
+}
+
+void rtw_android_wifictrl_func_del(void)
+{
+	if (g_wifidev_registered) {
+		wifi_del_dev();
+		g_wifidev_registered = 0;
+	}
+}
+
+void *wl_android_prealloc(int section, unsigned long size)
+{
+	void *alloc_ptr = NULL;
+	if (wifi_control_data && wifi_control_data->mem_prealloc) {
+		alloc_ptr = wifi_control_data->mem_prealloc(section, size);
+		if (alloc_ptr) {
+			RTW_INFO("success alloc section %d\n", section);
+			if (size != 0L)
+				memset(alloc_ptr, 0, size);
+			return alloc_ptr;
+		}
+	}
+
+	RTW_INFO("can't alloc section %d\n", section);
+	return NULL;
+}
+
+int wifi_get_irq_number(unsigned long *irq_flags_ptr)
+{
+	if (wifi_irqres) {
+		*irq_flags_ptr = wifi_irqres->flags & IRQF_TRIGGER_MASK;
+		return (int)wifi_irqres->start;
+	}
+#ifdef CUSTOM_OOB_GPIO_NUM
+	return CUSTOM_OOB_GPIO_NUM;
+#else
+	return -1;
+#endif
+}
+
+int wifi_set_power(int on, unsigned long msec)
+{
+	RTW_INFO("%s = %d\n", __FUNCTION__, on);
+	if (wifi_control_data && wifi_control_data->set_power)
+		wifi_control_data->set_power(on);
+	if (msec)
+		msleep(msec);
+	return 0;
+}
+
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 35))
+int wifi_get_mac_addr(unsigned char *buf)
+{
+	RTW_INFO("%s\n", __FUNCTION__);
+	if (!buf)
+		return -EINVAL;
+	if (wifi_control_data && wifi_control_data->get_mac_addr)
+		return wifi_control_data->get_mac_addr(buf);
+	return -EOPNOTSUPP;
+}
+#endif /* (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 35)) */
+
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 39)) || defined(COMPAT_KERNEL_RELEASE)
+void *wifi_get_country_code(char *ccode)
+{
+	RTW_INFO("%s\n", __FUNCTION__);
+	if (!ccode)
+		return NULL;
+	if (wifi_control_data && wifi_control_data->get_country_code)
+		return wifi_control_data->get_country_code(ccode);
+	return NULL;
+}
+#endif /* (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 39)) */
+
+static int wifi_set_carddetect(int on)
+{
+	RTW_INFO("%s = %d\n", __FUNCTION__, on);
+	if (wifi_control_data && wifi_control_data->set_carddetect)
+		wifi_control_data->set_carddetect(on);
+	return 0;
+}
+
+static int wifi_probe(struct platform_device *pdev)
+{
+	struct wifi_platform_data *wifi_ctrl =
+		(struct wifi_platform_data *)(pdev->dev.platform_data);
+	int wifi_wake_gpio = 0;
+
+	RTW_INFO("## %s\n", __FUNCTION__);
+	wifi_irqres = platform_get_resource_byname(pdev, IORESOURCE_IRQ, "bcmdhd_wlan_irq");
+
+	if (wifi_irqres == NULL)
+		wifi_irqres = platform_get_resource_byname(pdev,
+				IORESOURCE_IRQ, "bcm4329_wlan_irq");
+	else
+		wifi_wake_gpio = wifi_irqres->start;
+
+#ifdef CONFIG_GPIO_WAKEUP
+	RTW_INFO("%s: gpio:%d wifi_wake_gpio:%d\n", __func__,
+	       (int)wifi_irqres->start, wifi_wake_gpio);
+
+	if (wifi_wake_gpio > 0) {
+#ifdef CONFIG_PLATFORM_INTEL_BYT
+		wifi_configure_gpio();
+#else /* CONFIG_PLATFORM_INTEL_BYT */
+		gpio_request(wifi_wake_gpio, "oob_irq");
+		gpio_direction_input(wifi_wake_gpio);
+		oob_irq = gpio_to_irq(wifi_wake_gpio);
+#endif /* CONFIG_PLATFORM_INTEL_BYT */
+		RTW_INFO("%s oob_irq:%d\n", __func__, oob_irq);
+	} else if (wifi_irqres) {
+		oob_irq = wifi_irqres->start;
+		RTW_INFO("%s oob_irq:%d\n", __func__, oob_irq);
+	}
+#endif
+	wifi_control_data = wifi_ctrl;
+
+	wifi_set_power(1, 0);	/* Power On */
+	wifi_set_carddetect(1);	/* CardDetect (0->1) */
+
+	up(&wifi_control_sem);
+	return 0;
+}
+
+#ifdef RTW_SUPPORT_PLATFORM_SHUTDOWN
+extern PADAPTER g_test_adapter;
+
+static void shutdown_card(void)
+{
+	u32 addr;
+	u8 tmp8, cnt = 0;
+
+	if (NULL == g_test_adapter) {
+		RTW_INFO("%s: padapter==NULL\n", __FUNCTION__);
+		return;
+	}
+
+#ifdef CONFIG_FWLPS_IN_IPS
+	LeaveAllPowerSaveMode(g_test_adapter);
+#endif /* CONFIG_FWLPS_IN_IPS */
+
+#ifdef CONFIG_WOWLAN
+#ifdef CONFIG_GPIO_WAKEUP
+	/*default wake up pin change to BT*/
+	RTW_INFO("%s:default wake up pin change to BT\n", __FUNCTION__);
+	rtw_hal_switch_gpio_wl_ctrl(g_test_adapter, WAKEUP_GPIO_IDX, _FALSE);
+#endif /* CONFIG_GPIO_WAKEUP */
+#endif /* CONFIG_WOWLAN */
+
+	/* Leave SDIO HCI Suspend */
+	addr = 0x10250086;
+	rtw_write8(g_test_adapter, addr, 0);
+	do {
+		tmp8 = rtw_read8(g_test_adapter, addr);
+		cnt++;
+		RTW_INFO(FUNC_ADPT_FMT ": polling SDIO_HSUS_CTRL(0x%x)=0x%x, cnt=%d\n",
+			 FUNC_ADPT_ARG(g_test_adapter), addr, tmp8, cnt);
+
+		if (tmp8 & BIT(1))
+			break;
+
+		if (cnt >= 100) {
+			RTW_INFO(FUNC_ADPT_FMT ": polling 0x%x[1]==1 FAIL!!\n",
+				 FUNC_ADPT_ARG(g_test_adapter), addr);
+			break;
+		}
+
+		rtw_mdelay_os(10);
+	} while (1);
+
+	/* unlock register I/O */
+	rtw_write8(g_test_adapter, 0x1C, 0);
+
+	/* enable power down function */
+	/* 0x04[4] = 1 */
+	/* 0x05[7] = 1 */
+	addr = 0x04;
+	tmp8 = rtw_read8(g_test_adapter, addr);
+	tmp8 |= BIT(4);
+	rtw_write8(g_test_adapter, addr, tmp8);
+	RTW_INFO(FUNC_ADPT_FMT ": read after write 0x%x=0x%x\n",
+		FUNC_ADPT_ARG(g_test_adapter), addr, rtw_read8(g_test_adapter, addr));
+
+	addr = 0x05;
+	tmp8 = rtw_read8(g_test_adapter, addr);
+	tmp8 |= BIT(7);
+	rtw_write8(g_test_adapter, addr, tmp8);
+	RTW_INFO(FUNC_ADPT_FMT ": read after write 0x%x=0x%x\n",
+		FUNC_ADPT_ARG(g_test_adapter), addr, rtw_read8(g_test_adapter, addr));
+
+	/* lock register page0 0x0~0xB read/write */
+	rtw_write8(g_test_adapter, 0x1C, 0x0E);
+
+	rtw_set_surprise_removed(g_test_adapter);
+	RTW_INFO(FUNC_ADPT_FMT ": bSurpriseRemoved=%s\n",
+		FUNC_ADPT_ARG(g_test_adapter), rtw_is_surprise_removed(g_test_adapter) ? "True" : "False");
+}
+#endif /* RTW_SUPPORT_PLATFORM_SHUTDOWN */
+
+static int wifi_remove(struct platform_device *pdev)
+{
+	struct wifi_platform_data *wifi_ctrl =
+		(struct wifi_platform_data *)(pdev->dev.platform_data);
+
+	RTW_INFO("## %s\n", __FUNCTION__);
+	wifi_control_data = wifi_ctrl;
+
+	wifi_set_power(0, 0);	/* Power Off */
+	wifi_set_carddetect(0);	/* CardDetect (1->0) */
+
+	up(&wifi_control_sem);
+	return 0;
+}
+
+#ifdef RTW_SUPPORT_PLATFORM_SHUTDOWN
+static void wifi_shutdown(struct platform_device *pdev)
+{
+	struct wifi_platform_data *wifi_ctrl =
+		(struct wifi_platform_data *)(pdev->dev.platform_data);
+
+
+	RTW_INFO("## %s\n", __FUNCTION__);
+
+	wifi_control_data = wifi_ctrl;
+
+	shutdown_card();
+	wifi_set_power(0, 0);	/* Power Off */
+	wifi_set_carddetect(0);	/* CardDetect (1->0) */
+}
+#endif /* RTW_SUPPORT_PLATFORM_SHUTDOWN */
+
+static int wifi_suspend(struct platform_device *pdev, pm_message_t state)
+{
+	RTW_INFO("##> %s\n", __FUNCTION__);
+#if (LINUX_VERSION_CODE <= KERNEL_VERSION(2, 6, 39)) && defined(OOB_INTR_ONLY)
+	bcmsdh_oob_intr_set(0);
+#endif
+	return 0;
+}
+
+static int wifi_resume(struct platform_device *pdev)
+{
+	RTW_INFO("##> %s\n", __FUNCTION__);
+#if (LINUX_VERSION_CODE <= KERNEL_VERSION(2, 6, 39)) && defined(OOB_INTR_ONLY)
+	if (dhd_os_check_if_up(bcmsdh_get_drvdata()))
+		bcmsdh_oob_intr_set(1);
+#endif
+	return 0;
+}
+
+/* temporarily use these two */
+static struct platform_driver wifi_device = {
+	.probe          = wifi_probe,
+	.remove         = wifi_remove,
+	.suspend        = wifi_suspend,
+	.resume         = wifi_resume,
+#ifdef RTW_SUPPORT_PLATFORM_SHUTDOWN
+	.shutdown       = wifi_shutdown,
+#endif /* RTW_SUPPORT_PLATFORM_SHUTDOWN */
+	.driver         = {
+		.name   = "bcmdhd_wlan",
+	}
+};
+
+static struct platform_driver wifi_device_legacy = {
+	.probe          = wifi_probe,
+	.remove         = wifi_remove,
+	.suspend        = wifi_suspend,
+	.resume         = wifi_resume,
+	.driver         = {
+		.name   = "bcm4329_wlan",
+	}
+};
+
+static int wifi_add_dev(void)
+{
+	RTW_INFO("## Calling platform_driver_register\n");
+	platform_driver_register(&wifi_device);
+	platform_driver_register(&wifi_device_legacy);
+	return 0;
+}
+
+static void wifi_del_dev(void)
+{
+	RTW_INFO("## Unregister platform_driver_register\n");
+	platform_driver_unregister(&wifi_device);
+	platform_driver_unregister(&wifi_device_legacy);
+}
+#endif /* defined(RTW_ENABLE_WIFI_CONTROL_FUNC) */
+
+#ifdef CONFIG_GPIO_WAKEUP
+#ifdef CONFIG_PLATFORM_INTEL_BYT
+int wifi_configure_gpio(void)
+{
+	if (gpio_request(oob_gpio, "oob_irq")) {
+		RTW_INFO("## %s Cannot request GPIO\n", __FUNCTION__);
+		return -1;
+	}
+	gpio_export(oob_gpio, 0);
+	if (gpio_direction_input(oob_gpio)) {
+		RTW_INFO("## %s Cannot set GPIO direction input\n", __FUNCTION__);
+		return -1;
+	}
+	oob_irq = gpio_to_irq(oob_gpio);
+	if (oob_irq < 0) {
+		RTW_INFO("## %s Cannot convert GPIO to IRQ\n", __FUNCTION__);
+		return -1;
+	}
+
+	RTW_INFO("## %s OOB_IRQ=%d\n", __FUNCTION__, oob_irq);
+
+	return 0;
+}
+#endif /* CONFIG_PLATFORM_INTEL_BYT */
+void wifi_free_gpio(unsigned int gpio)
+{
+#ifdef CONFIG_PLATFORM_INTEL_BYT
+	if (gpio)
+		gpio_free(gpio);
+#endif /* CONFIG_PLATFORM_INTEL_BYT */
+}
+#endif /* CONFIG_GPIO_WAKEUP */
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/os_dep/linux/rtw_cfgvendor.c linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/os_dep/linux/rtw_cfgvendor.c
--- linux-5.6.3/3rdparty/rtl8821ce/os_dep/linux/rtw_cfgvendor.c	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/os_dep/linux/rtw_cfgvendor.c	2020-04-10 16:35:06.856661935 +0300
@@ -0,0 +1,2148 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+
+#include <drv_types.h>
+
+#ifdef CONFIG_IOCTL_CFG80211
+
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 14, 0)) || defined(RTW_VENDOR_EXT_SUPPORT)
+
+/*
+#include <linux/kernel.h>
+#include <linux/if_arp.h>
+#include <asm/uaccess.h>
+
+#include <linux/kernel.h>
+#include <linux/kthread.h>
+#include <linux/netdevice.h>
+#include <linux/sched.h>
+#include <linux/etherdevice.h>
+#include <linux/wireless.h>
+#include <linux/ieee80211.h>
+#include <linux/wait.h>
+#include <net/cfg80211.h>
+*/
+
+#include <net/rtnetlink.h>
+
+#ifdef DBG_MEM_ALLOC
+extern bool match_mstat_sniff_rules(const enum mstat_f flags, const size_t size);
+struct sk_buff *dbg_rtw_cfg80211_vendor_event_alloc(struct wiphy *wiphy, struct wireless_dev *wdev, int len, int event_id, gfp_t gfp
+		, const enum mstat_f flags, const char *func, const int line)
+{
+	struct sk_buff *skb;
+	unsigned int truesize = 0;
+
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 1, 0))
+	skb = cfg80211_vendor_event_alloc(wiphy, len, event_id, gfp);
+#else
+	skb = cfg80211_vendor_event_alloc(wiphy, wdev, len, event_id, gfp);
+#endif
+
+	if (skb)
+		truesize = skb->truesize;
+
+	if (!skb || truesize < len || match_mstat_sniff_rules(flags, truesize))
+		RTW_INFO("DBG_MEM_ALLOC %s:%d %s(%d), skb:%p, truesize=%u\n", func, line, __FUNCTION__, len, skb, truesize);
+
+	rtw_mstat_update(
+		flags
+		, skb ? MSTAT_ALLOC_SUCCESS : MSTAT_ALLOC_FAIL
+		, truesize
+	);
+
+	return skb;
+}
+
+void dbg_rtw_cfg80211_vendor_event(struct sk_buff *skb, gfp_t gfp
+		   , const enum mstat_f flags, const char *func, const int line)
+{
+	unsigned int truesize = skb->truesize;
+
+	if (match_mstat_sniff_rules(flags, truesize))
+		RTW_INFO("DBG_MEM_ALLOC %s:%d %s, truesize=%u\n", func, line, __FUNCTION__, truesize);
+
+	cfg80211_vendor_event(skb, gfp);
+
+	rtw_mstat_update(
+		flags
+		, MSTAT_FREE
+		, truesize
+	);
+}
+
+struct sk_buff *dbg_rtw_cfg80211_vendor_cmd_alloc_reply_skb(struct wiphy *wiphy, int len
+		, const enum mstat_f flags, const char *func, const int line)
+{
+	struct sk_buff *skb;
+	unsigned int truesize = 0;
+
+	skb = cfg80211_vendor_cmd_alloc_reply_skb(wiphy, len);
+
+	if (skb)
+		truesize = skb->truesize;
+
+	if (!skb || truesize < len || match_mstat_sniff_rules(flags, truesize))
+		RTW_INFO("DBG_MEM_ALLOC %s:%d %s(%d), skb:%p, truesize=%u\n", func, line, __FUNCTION__, len, skb, truesize);
+
+	rtw_mstat_update(
+		flags
+		, skb ? MSTAT_ALLOC_SUCCESS : MSTAT_ALLOC_FAIL
+		, truesize
+	);
+
+	return skb;
+}
+
+int dbg_rtw_cfg80211_vendor_cmd_reply(struct sk_buff *skb
+	      , const enum mstat_f flags, const char *func, const int line)
+{
+	unsigned int truesize = skb->truesize;
+	int ret;
+
+	if (match_mstat_sniff_rules(flags, truesize))
+		RTW_INFO("DBG_MEM_ALLOC %s:%d %s, truesize=%u\n", func, line, __FUNCTION__, truesize);
+
+	ret = cfg80211_vendor_cmd_reply(skb);
+
+	rtw_mstat_update(
+		flags
+		, MSTAT_FREE
+		, truesize
+	);
+
+	return ret;
+}
+
+#define rtw_cfg80211_vendor_event_alloc(wiphy, wdev, len, event_id, gfp) \
+	dbg_rtw_cfg80211_vendor_event_alloc(wiphy, wdev, len, event_id, gfp, MSTAT_FUNC_CFG_VENDOR | MSTAT_TYPE_SKB, __FUNCTION__, __LINE__)
+
+#define rtw_cfg80211_vendor_event(skb, gfp) \
+	dbg_rtw_cfg80211_vendor_event(skb, gfp, MSTAT_FUNC_CFG_VENDOR | MSTAT_TYPE_SKB, __FUNCTION__, __LINE__)
+
+#define rtw_cfg80211_vendor_cmd_alloc_reply_skb(wiphy, len) \
+	dbg_rtw_cfg80211_vendor_cmd_alloc_reply_skb(wiphy, len, MSTAT_FUNC_CFG_VENDOR | MSTAT_TYPE_SKB, __FUNCTION__, __LINE__)
+
+#define rtw_cfg80211_vendor_cmd_reply(skb) \
+	dbg_rtw_cfg80211_vendor_cmd_reply(skb, MSTAT_FUNC_CFG_VENDOR | MSTAT_TYPE_SKB, __FUNCTION__, __LINE__)
+#else
+
+struct sk_buff *rtw_cfg80211_vendor_event_alloc(
+	struct wiphy *wiphy, struct wireless_dev *wdev, int len, int event_id, gfp_t gfp)
+{
+	struct sk_buff *skb;
+
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 1, 0))
+	skb = cfg80211_vendor_event_alloc(wiphy, len, event_id, gfp);
+#else
+	skb = cfg80211_vendor_event_alloc(wiphy, wdev, len, event_id, gfp);
+#endif
+	return skb;
+}
+
+#define rtw_cfg80211_vendor_event(skb, gfp) \
+	cfg80211_vendor_event(skb, gfp)
+
+#define rtw_cfg80211_vendor_cmd_alloc_reply_skb(wiphy, len) \
+	cfg80211_vendor_cmd_alloc_reply_skb(wiphy, len)
+
+#define rtw_cfg80211_vendor_cmd_reply(skb) \
+	cfg80211_vendor_cmd_reply(skb)
+#endif /* DBG_MEM_ALLOC */
+
+/*
+ * This API is to be used for asynchronous vendor events. This
+ * shouldn't be used in response to a vendor command from its
+ * do_it handler context (instead rtw_cfgvendor_send_cmd_reply should
+ * be used).
+ */
+int rtw_cfgvendor_send_async_event(struct wiphy *wiphy,
+	   struct net_device *dev, int event_id, const void  *data, int len)
+{
+	u16 kflags;
+	struct sk_buff *skb;
+
+	kflags = in_atomic() ? GFP_ATOMIC : GFP_KERNEL;
+
+	/* Alloc the SKB for vendor_event */
+	skb = rtw_cfg80211_vendor_event_alloc(wiphy, ndev_to_wdev(dev), len, event_id, kflags);
+	if (!skb) {
+		RTW_ERR(FUNC_NDEV_FMT" skb alloc failed", FUNC_NDEV_ARG(dev));
+		return -ENOMEM;
+	}
+
+	/* Push the data to the skb */
+	nla_put_nohdr(skb, len, data);
+
+	rtw_cfg80211_vendor_event(skb, kflags);
+
+	return 0;
+}
+
+static int rtw_cfgvendor_send_cmd_reply(struct wiphy *wiphy,
+			struct net_device *dev, const void  *data, int len)
+{
+	struct sk_buff *skb;
+
+	/* Alloc the SKB for vendor_event */
+	skb = rtw_cfg80211_vendor_cmd_alloc_reply_skb(wiphy, len);
+	if (unlikely(!skb)) {
+		RTW_ERR(FUNC_NDEV_FMT" skb alloc failed", FUNC_NDEV_ARG(dev));
+		return -ENOMEM;
+	}
+
+	/* Push the data to the skb */
+	nla_put_nohdr(skb, len, data);
+
+	return rtw_cfg80211_vendor_cmd_reply(skb);
+}
+
+/* Feature enums */
+#define WIFI_FEATURE_INFRA              0x0001      // Basic infrastructure mode
+#define WIFI_FEATURE_INFRA_5G           0x0002      // Support for 5 GHz Band
+#define WIFI_FEATURE_HOTSPOT            0x0004      // Support for GAS/ANQP
+#define WIFI_FEATURE_P2P                0x0008      // Wifi-Direct
+#define WIFI_FEATURE_SOFT_AP            0x0010      // Soft AP
+#define WIFI_FEATURE_GSCAN              0x0020      // Google-Scan APIs
+#define WIFI_FEATURE_NAN                0x0040      // Neighbor Awareness Networking
+#define WIFI_FEATURE_D2D_RTT            0x0080      // Device-to-device RTT
+#define WIFI_FEATURE_D2AP_RTT           0x0100      // Device-to-AP RTT
+#define WIFI_FEATURE_BATCH_SCAN         0x0200      // Batched Scan (legacy)
+#define WIFI_FEATURE_PNO                0x0400      // Preferred network offload
+#define WIFI_FEATURE_ADDITIONAL_STA     0x0800      // Support for two STAs
+#define WIFI_FEATURE_TDLS               0x1000      // Tunnel directed link setup
+#define WIFI_FEATURE_TDLS_OFFCHANNEL    0x2000      // Support for TDLS off channel
+#define WIFI_FEATURE_EPR                0x4000      // Enhanced power reporting
+#define WIFI_FEATURE_AP_STA             0x8000      // Support for AP STA Concurrency
+#define WIFI_FEATURE_LINK_LAYER_STATS   0x10000     // Link layer stats collection
+#define WIFI_FEATURE_LOGGER             0x20000     // WiFi Logger
+#define WIFI_FEATURE_HAL_EPNO           0x40000     // WiFi PNO enhanced
+#define WIFI_FEATURE_RSSI_MONITOR       0x80000     // RSSI Monitor
+#define WIFI_FEATURE_MKEEP_ALIVE        0x100000    // WiFi mkeep_alive
+#define WIFI_FEATURE_CONFIG_NDO         0x200000    // ND offload configure
+#define WIFI_FEATURE_TX_TRANSMIT_POWER  0x400000    // Capture Tx transmit power levels
+#define WIFI_FEATURE_CONTROL_ROAMING    0x800000    // Enable/Disable firmware roaming
+#define WIFI_FEATURE_IE_WHITELIST       0x1000000   // Support Probe IE white listing
+#define WIFI_FEATURE_SCAN_RAND          0x2000000   // Support MAC & Probe Sequence Number randomization
+// Add more features here
+
+#define MAX_FEATURE_SET_CONCURRRENT_GROUPS  3
+
+#include <hal_data.h>
+int rtw_dev_get_feature_set(struct net_device *dev)
+{
+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
+	HAL_DATA_TYPE *HalData = GET_HAL_DATA(adapter);
+	HAL_VERSION *hal_ver = &HalData->version_id;
+
+	int feature_set = 0;
+
+	feature_set |= WIFI_FEATURE_INFRA;
+
+#ifdef CONFIG_IEEE80211_BAND_5GHZ
+	if (is_supported_5g(adapter_to_regsty(adapter)->wireless_mode))
+		feature_set |= WIFI_FEATURE_INFRA_5G;
+#endif
+
+	feature_set |= WIFI_FEATURE_P2P;
+	feature_set |= WIFI_FEATURE_SOFT_AP;
+
+	feature_set |= WIFI_FEATURE_ADDITIONAL_STA;
+#ifdef CONFIG_RTW_CFGVEDNOR_LLSTATS
+	feature_set |= WIFI_FEATURE_LINK_LAYER_STATS;
+#endif /* CONFIG_RTW_CFGVEDNOR_LLSTATS */
+
+#ifdef CONFIG_RTW_CFGVEDNOR_RSSIMONITOR
+        feature_set |= WIFI_FEATURE_RSSI_MONITOR;
+#endif
+
+#ifdef CONFIG_RTW_CFGVENDOR_WIFI_LOGGER
+	feature_set |= WIFI_FEATURE_LOGGER;
+#endif
+
+#ifdef CONFIG_RTW_WIFI_HAL
+	feature_set |= WIFI_FEATURE_CONFIG_NDO;
+	feature_set |= WIFI_FEATURE_SCAN_RAND;
+#endif
+
+	return feature_set;
+}
+
+int *rtw_dev_get_feature_set_matrix(struct net_device *dev, int *num)
+{
+	int feature_set_full, mem_needed;
+	int *ret;
+
+	*num = 0;
+	mem_needed = sizeof(int) * MAX_FEATURE_SET_CONCURRRENT_GROUPS;
+	ret = (int *)rtw_malloc(mem_needed);
+
+	if (!ret) {
+		RTW_ERR(FUNC_NDEV_FMT" failed to allocate %d bytes\n"
+			, FUNC_NDEV_ARG(dev), mem_needed);
+		return ret;
+	}
+
+	feature_set_full = rtw_dev_get_feature_set(dev);
+
+	ret[0] = (feature_set_full & WIFI_FEATURE_INFRA) |
+		 (feature_set_full & WIFI_FEATURE_INFRA_5G) |
+		 (feature_set_full & WIFI_FEATURE_NAN) |
+		 (feature_set_full & WIFI_FEATURE_D2D_RTT) |
+		 (feature_set_full & WIFI_FEATURE_D2AP_RTT) |
+		 (feature_set_full & WIFI_FEATURE_PNO) |
+		 (feature_set_full & WIFI_FEATURE_BATCH_SCAN) |
+		 (feature_set_full & WIFI_FEATURE_GSCAN) |
+		 (feature_set_full & WIFI_FEATURE_HOTSPOT) |
+		 (feature_set_full & WIFI_FEATURE_ADDITIONAL_STA) |
+		 (feature_set_full & WIFI_FEATURE_EPR);
+
+	ret[1] = (feature_set_full & WIFI_FEATURE_INFRA) |
+		 (feature_set_full & WIFI_FEATURE_INFRA_5G) |
+		 /* Not yet verified NAN with P2P */
+		 /* (feature_set_full & WIFI_FEATURE_NAN) | */
+		 (feature_set_full & WIFI_FEATURE_P2P) |
+		 (feature_set_full & WIFI_FEATURE_D2AP_RTT) |
+		 (feature_set_full & WIFI_FEATURE_D2D_RTT) |
+		 (feature_set_full & WIFI_FEATURE_EPR);
+
+	ret[2] = (feature_set_full & WIFI_FEATURE_INFRA) |
+		 (feature_set_full & WIFI_FEATURE_INFRA_5G) |
+		 (feature_set_full & WIFI_FEATURE_NAN) |
+		 (feature_set_full & WIFI_FEATURE_D2D_RTT) |
+		 (feature_set_full & WIFI_FEATURE_D2AP_RTT) |
+		 (feature_set_full & WIFI_FEATURE_TDLS) |
+		 (feature_set_full & WIFI_FEATURE_TDLS_OFFCHANNEL) |
+		 (feature_set_full & WIFI_FEATURE_EPR);
+	*num = MAX_FEATURE_SET_CONCURRRENT_GROUPS;
+
+	return ret;
+}
+
+static int rtw_cfgvendor_get_feature_set(struct wiphy *wiphy,
+		struct wireless_dev *wdev, const void  *data, int len)
+{
+	int err = 0;
+	int reply;
+
+	reply = rtw_dev_get_feature_set(wdev_to_ndev(wdev));
+
+	err =  rtw_cfgvendor_send_cmd_reply(wiphy, wdev_to_ndev(wdev), &reply, sizeof(int));
+
+	if (unlikely(err))
+		RTW_ERR(FUNC_NDEV_FMT" Vendor Command reply failed ret:%d\n"
+			, FUNC_NDEV_ARG(wdev_to_ndev(wdev)), err);
+
+	return err;
+}
+
+static int rtw_cfgvendor_get_feature_set_matrix(struct wiphy *wiphy,
+		struct wireless_dev *wdev, const void  *data, int len)
+{
+	int err = 0;
+	struct sk_buff *skb;
+	int *reply;
+	int num, mem_needed, i;
+
+	reply = rtw_dev_get_feature_set_matrix(wdev_to_ndev(wdev), &num);
+
+	if (!reply) {
+		RTW_ERR(FUNC_NDEV_FMT" Could not get feature list matrix\n"
+			, FUNC_NDEV_ARG(wdev_to_ndev(wdev)));
+		err = -EINVAL;
+		return err;
+	}
+
+	mem_needed = VENDOR_REPLY_OVERHEAD + (ATTRIBUTE_U32_LEN * num) +
+		     ATTRIBUTE_U32_LEN;
+
+	/* Alloc the SKB for vendor_event */
+	skb = rtw_cfg80211_vendor_cmd_alloc_reply_skb(wiphy, mem_needed);
+	if (unlikely(!skb)) {
+		RTW_ERR(FUNC_NDEV_FMT" skb alloc failed", FUNC_NDEV_ARG(wdev_to_ndev(wdev)));
+		err = -ENOMEM;
+		goto exit;
+	}
+
+	nla_put_u32(skb, ANDR_WIFI_ATTRIBUTE_NUM_FEATURE_SET, num);
+	for (i = 0; i < num; i++)
+		nla_put_u32(skb, ANDR_WIFI_ATTRIBUTE_FEATURE_SET, reply[i]);
+
+	err =  rtw_cfg80211_vendor_cmd_reply(skb);
+
+	if (unlikely(err))
+		RTW_ERR(FUNC_NDEV_FMT" Vendor Command reply failed ret:%d\n"
+			, FUNC_NDEV_ARG(wdev_to_ndev(wdev)), err);
+exit:
+	rtw_mfree((u8 *)reply, sizeof(int) * num);
+	return err;
+}
+
+#if defined(GSCAN_SUPPORT) && 0
+int rtw_cfgvendor_send_hotlist_event(struct wiphy *wiphy,
+	struct net_device *dev, void  *data, int len, rtw_vendor_event_t event)
+{
+	u16 kflags;
+	const void *ptr;
+	struct sk_buff *skb;
+	int malloc_len, total, iter_cnt_to_send, cnt;
+	gscan_results_cache_t *cache = (gscan_results_cache_t *)data;
+
+	total = len / sizeof(wifi_gscan_result_t);
+	while (total > 0) {
+		malloc_len = (total * sizeof(wifi_gscan_result_t)) + VENDOR_DATA_OVERHEAD;
+		if (malloc_len > NLMSG_DEFAULT_SIZE)
+			malloc_len = NLMSG_DEFAULT_SIZE;
+		iter_cnt_to_send =
+			(malloc_len - VENDOR_DATA_OVERHEAD) / sizeof(wifi_gscan_result_t);
+		total = total - iter_cnt_to_send;
+
+		kflags = in_atomic() ? GFP_ATOMIC : GFP_KERNEL;
+
+		/* Alloc the SKB for vendor_event */
+		skb = rtw_cfg80211_vendor_event_alloc(wiphy, ndev_to_wdev(dev), malloc_len, event, kflags);
+		if (!skb) {
+			WL_ERR(("skb alloc failed"));
+			return -ENOMEM;
+		}
+
+		while (cache && iter_cnt_to_send) {
+			ptr = (const void *) &cache->results[cache->tot_consumed];
+
+			if (iter_cnt_to_send < (cache->tot_count - cache->tot_consumed))
+				cnt = iter_cnt_to_send;
+			else
+				cnt = (cache->tot_count - cache->tot_consumed);
+
+			iter_cnt_to_send -= cnt;
+			cache->tot_consumed += cnt;
+			/* Push the data to the skb */
+			nla_append(skb, cnt * sizeof(wifi_gscan_result_t), ptr);
+			if (cache->tot_consumed == cache->tot_count)
+				cache = cache->next;
+
+		}
+
+		rtw_cfg80211_vendor_event(skb, kflags);
+	}
+
+	return 0;
+}
+
+
+static int rtw_cfgvendor_gscan_get_capabilities(struct wiphy *wiphy,
+		struct wireless_dev *wdev, const void  *data, int len)
+{
+	int err = 0;
+	struct bcm_cfg80211 *cfg = wiphy_priv(wiphy);
+	dhd_pno_gscan_capabilities_t *reply = NULL;
+	uint32 reply_len = 0;
+
+
+	reply = dhd_dev_pno_get_gscan(bcmcfg_to_prmry_ndev(cfg),
+			      DHD_PNO_GET_CAPABILITIES, NULL, &reply_len);
+	if (!reply) {
+		WL_ERR(("Could not get capabilities\n"));
+		err = -EINVAL;
+		return err;
+	}
+
+	err =  rtw_cfgvendor_send_cmd_reply(wiphy, bcmcfg_to_prmry_ndev(cfg),
+					    reply, reply_len);
+
+	if (unlikely(err))
+		WL_ERR(("Vendor Command reply failed ret:%d\n", err));
+
+	kfree(reply);
+	return err;
+}
+
+static int rtw_cfgvendor_gscan_get_channel_list(struct wiphy *wiphy,
+		struct wireless_dev *wdev, const void  *data, int len)
+{
+	int err = 0, type, band;
+	struct bcm_cfg80211 *cfg = wiphy_priv(wiphy);
+	uint16 *reply = NULL;
+	uint32 reply_len = 0, num_channels, mem_needed;
+	struct sk_buff *skb;
+
+	type = nla_type(data);
+
+	if (type == GSCAN_ATTRIBUTE_BAND)
+		band = nla_get_u32(data);
+	else
+		return -1;
+
+	reply = dhd_dev_pno_get_gscan(bcmcfg_to_prmry_ndev(cfg),
+			      DHD_PNO_GET_CHANNEL_LIST, &band, &reply_len);
+
+	if (!reply) {
+		WL_ERR(("Could not get channel list\n"));
+		err = -EINVAL;
+		return err;
+	}
+	num_channels =  reply_len / sizeof(uint32);
+	mem_needed = reply_len + VENDOR_REPLY_OVERHEAD + (ATTRIBUTE_U32_LEN * 2);
+
+	/* Alloc the SKB for vendor_event */
+	skb = rtw_cfg80211_vendor_cmd_alloc_reply_skb(wiphy, mem_needed);
+	if (unlikely(!skb)) {
+		WL_ERR(("skb alloc failed"));
+		err = -ENOMEM;
+		goto exit;
+	}
+
+	nla_put_u32(skb, GSCAN_ATTRIBUTE_NUM_CHANNELS, num_channels);
+	nla_put(skb, GSCAN_ATTRIBUTE_CHANNEL_LIST, reply_len, reply);
+
+	err =  rtw_cfg80211_vendor_cmd_reply(skb);
+
+	if (unlikely(err))
+		WL_ERR(("Vendor Command reply failed ret:%d\n", err));
+exit:
+	kfree(reply);
+	return err;
+}
+
+static int rtw_cfgvendor_gscan_get_batch_results(struct wiphy *wiphy,
+		struct wireless_dev *wdev, const void  *data, int len)
+{
+	int err = 0;
+	struct bcm_cfg80211 *cfg = wiphy_priv(wiphy);
+	gscan_results_cache_t *results, *iter;
+	uint32 reply_len, complete = 0, num_results_iter;
+	int32 mem_needed;
+	wifi_gscan_result_t *ptr;
+	uint16 num_scan_ids, num_results;
+	struct sk_buff *skb;
+	struct nlattr *scan_hdr;
+
+	dhd_dev_wait_batch_results_complete(bcmcfg_to_prmry_ndev(cfg));
+	dhd_dev_pno_lock_access_batch_results(bcmcfg_to_prmry_ndev(cfg));
+	results = dhd_dev_pno_get_gscan(bcmcfg_to_prmry_ndev(cfg),
+				DHD_PNO_GET_BATCH_RESULTS, NULL, &reply_len);
+
+	if (!results) {
+		WL_ERR(("No results to send %d\n", err));
+		err =  rtw_cfgvendor_send_cmd_reply(wiphy, bcmcfg_to_prmry_ndev(cfg),
+						    results, 0);
+
+		if (unlikely(err))
+			WL_ERR(("Vendor Command reply failed ret:%d\n", err));
+		dhd_dev_pno_unlock_access_batch_results(bcmcfg_to_prmry_ndev(cfg));
+		return err;
+	}
+	num_scan_ids = reply_len & 0xFFFF;
+	num_results = (reply_len & 0xFFFF0000) >> 16;
+	mem_needed = (num_results * sizeof(wifi_gscan_result_t)) +
+		     (num_scan_ids * GSCAN_BATCH_RESULT_HDR_LEN) +
+		     VENDOR_REPLY_OVERHEAD + SCAN_RESULTS_COMPLETE_FLAG_LEN;
+
+	if (mem_needed > (int32)NLMSG_DEFAULT_SIZE) {
+		mem_needed = (int32)NLMSG_DEFAULT_SIZE;
+		complete = 0;
+	} else
+		complete = 1;
+
+	WL_TRACE(("complete %d mem_needed %d max_mem %d\n", complete, mem_needed,
+		  (int)NLMSG_DEFAULT_SIZE));
+	/* Alloc the SKB for vendor_event */
+	skb = rtw_cfg80211_vendor_cmd_alloc_reply_skb(wiphy, mem_needed);
+	if (unlikely(!skb)) {
+		WL_ERR(("skb alloc failed"));
+		dhd_dev_pno_unlock_access_batch_results(bcmcfg_to_prmry_ndev(cfg));
+		return -ENOMEM;
+	}
+	iter = results;
+
+	nla_put_u32(skb, GSCAN_ATTRIBUTE_SCAN_RESULTS_COMPLETE, complete);
+
+	mem_needed = mem_needed - (SCAN_RESULTS_COMPLETE_FLAG_LEN + VENDOR_REPLY_OVERHEAD);
+
+	while (iter && ((mem_needed - GSCAN_BATCH_RESULT_HDR_LEN)  > 0)) {
+		scan_hdr = nla_nest_start(skb, GSCAN_ATTRIBUTE_SCAN_RESULTS);
+		nla_put_u32(skb, GSCAN_ATTRIBUTE_SCAN_ID, iter->scan_id);
+		nla_put_u8(skb, GSCAN_ATTRIBUTE_SCAN_FLAGS, iter->flag);
+		num_results_iter =
+			(mem_needed - GSCAN_BATCH_RESULT_HDR_LEN) / sizeof(wifi_gscan_result_t);
+
+		if ((iter->tot_count - iter->tot_consumed) < num_results_iter)
+			num_results_iter = iter->tot_count - iter->tot_consumed;
+
+		nla_put_u32(skb, GSCAN_ATTRIBUTE_NUM_OF_RESULTS, num_results_iter);
+		if (num_results_iter) {
+			ptr = &iter->results[iter->tot_consumed];
+			iter->tot_consumed += num_results_iter;
+			nla_put(skb, GSCAN_ATTRIBUTE_SCAN_RESULTS,
+				num_results_iter * sizeof(wifi_gscan_result_t), ptr);
+		}
+		nla_nest_end(skb, scan_hdr);
+		mem_needed -= GSCAN_BATCH_RESULT_HDR_LEN +
+			      (num_results_iter * sizeof(wifi_gscan_result_t));
+		iter = iter->next;
+	}
+
+	dhd_dev_gscan_batch_cache_cleanup(bcmcfg_to_prmry_ndev(cfg));
+	dhd_dev_pno_unlock_access_batch_results(bcmcfg_to_prmry_ndev(cfg));
+
+	return rtw_cfg80211_vendor_cmd_reply(skb);
+}
+
+static int rtw_cfgvendor_initiate_gscan(struct wiphy *wiphy,
+		       struct wireless_dev *wdev, const void  *data, int len)
+{
+	int err = 0;
+	struct bcm_cfg80211 *cfg = wiphy_priv(wiphy);
+	int type, tmp = len;
+	int run = 0xFF;
+	int flush = 0;
+	const struct nlattr *iter;
+
+	nla_for_each_attr(iter, data, len, tmp) {
+		type = nla_type(iter);
+		if (type == GSCAN_ATTRIBUTE_ENABLE_FEATURE)
+			run = nla_get_u32(iter);
+		else if (type == GSCAN_ATTRIBUTE_FLUSH_FEATURE)
+			flush = nla_get_u32(iter);
+	}
+
+	if (run != 0xFF) {
+		err = dhd_dev_pno_run_gscan(bcmcfg_to_prmry_ndev(cfg), run, flush);
+
+		if (unlikely(err))
+			WL_ERR(("Could not run gscan:%d\n", err));
+		return err;
+	} else
+		return -1;
+
+
+}
+
+static int rtw_cfgvendor_enable_full_scan_result(struct wiphy *wiphy,
+		struct wireless_dev *wdev, const void  *data, int len)
+{
+	int err = 0;
+	struct bcm_cfg80211 *cfg = wiphy_priv(wiphy);
+	int type;
+	bool real_time = FALSE;
+
+	type = nla_type(data);
+
+	if (type == GSCAN_ATTRIBUTE_ENABLE_FULL_SCAN_RESULTS) {
+		real_time = nla_get_u32(data);
+
+		err = dhd_dev_pno_enable_full_scan_result(bcmcfg_to_prmry_ndev(cfg), real_time);
+
+		if (unlikely(err))
+			WL_ERR(("Could not run gscan:%d\n", err));
+
+	} else
+		err = -1;
+
+	return err;
+}
+
+static int rtw_cfgvendor_set_scan_cfg(struct wiphy *wiphy,
+		     struct wireless_dev *wdev, const void  *data, int len)
+{
+	int err = 0;
+	struct bcm_cfg80211 *cfg = wiphy_priv(wiphy);
+	gscan_scan_params_t *scan_param;
+	int j = 0;
+	int type, tmp, tmp1, tmp2, k = 0;
+	const struct nlattr *iter, *iter1, *iter2;
+	struct dhd_pno_gscan_channel_bucket  *ch_bucket;
+
+	scan_param = kzalloc(sizeof(gscan_scan_params_t), GFP_KERNEL);
+	if (!scan_param) {
+		WL_ERR(("Could not set GSCAN scan cfg, mem alloc failure\n"));
+		err = -EINVAL;
+		return err;
+
+	}
+
+	scan_param->scan_fr = PNO_SCAN_MIN_FW_SEC;
+	nla_for_each_attr(iter, data, len, tmp) {
+		type = nla_type(iter);
+
+		if (j >= GSCAN_MAX_CH_BUCKETS)
+			break;
+
+		switch (type) {
+		case GSCAN_ATTRIBUTE_BASE_PERIOD:
+			scan_param->scan_fr = nla_get_u32(iter) / 1000;
+			break;
+		case GSCAN_ATTRIBUTE_NUM_BUCKETS:
+			scan_param->nchannel_buckets = nla_get_u32(iter);
+			break;
+		case GSCAN_ATTRIBUTE_CH_BUCKET_1:
+		case GSCAN_ATTRIBUTE_CH_BUCKET_2:
+		case GSCAN_ATTRIBUTE_CH_BUCKET_3:
+		case GSCAN_ATTRIBUTE_CH_BUCKET_4:
+		case GSCAN_ATTRIBUTE_CH_BUCKET_5:
+		case GSCAN_ATTRIBUTE_CH_BUCKET_6:
+		case GSCAN_ATTRIBUTE_CH_BUCKET_7:
+			nla_for_each_nested(iter1, iter, tmp1) {
+				type = nla_type(iter1);
+				ch_bucket =
+					scan_param->channel_bucket;
+
+				switch (type) {
+				case GSCAN_ATTRIBUTE_BUCKET_ID:
+					break;
+				case GSCAN_ATTRIBUTE_BUCKET_PERIOD:
+					ch_bucket[j].bucket_freq_multiple =
+						nla_get_u32(iter1) / 1000;
+					break;
+				case GSCAN_ATTRIBUTE_BUCKET_NUM_CHANNELS:
+					ch_bucket[j].num_channels =
+						nla_get_u32(iter1);
+					break;
+				case GSCAN_ATTRIBUTE_BUCKET_CHANNELS:
+					nla_for_each_nested(iter2, iter1, tmp2) {
+						if (k >= PFN_SWC_RSSI_WINDOW_MAX)
+							break;
+						ch_bucket[j].chan_list[k] =
+							nla_get_u32(iter2);
+						k++;
+					}
+					k = 0;
+					break;
+				case GSCAN_ATTRIBUTE_BUCKETS_BAND:
+					ch_bucket[j].band = (uint16)
+							    nla_get_u32(iter1);
+					break;
+				case GSCAN_ATTRIBUTE_REPORT_EVENTS:
+					ch_bucket[j].report_flag = (uint8)
+							   nla_get_u32(iter1);
+					break;
+				}
+			}
+			j++;
+			break;
+		}
+	}
+
+	if (dhd_dev_pno_set_cfg_gscan(bcmcfg_to_prmry_ndev(cfg),
+				      DHD_PNO_SCAN_CFG_ID, scan_param, 0) < 0) {
+		WL_ERR(("Could not set GSCAN scan cfg\n"));
+		err = -EINVAL;
+	}
+
+	kfree(scan_param);
+	return err;
+
+}
+
+static int rtw_cfgvendor_hotlist_cfg(struct wiphy *wiphy,
+		    struct wireless_dev *wdev, const void  *data, int len)
+{
+	int err = 0;
+	struct bcm_cfg80211 *cfg = wiphy_priv(wiphy);
+	gscan_hotlist_scan_params_t *hotlist_params;
+	int tmp, tmp1, tmp2, type, j = 0, dummy;
+	const struct nlattr *outer, *inner, *iter;
+	uint8 flush = 0;
+	struct bssid_t *pbssid;
+
+	hotlist_params = (gscan_hotlist_scan_params_t *)kzalloc(len, GFP_KERNEL);
+	if (!hotlist_params) {
+		WL_ERR(("Cannot Malloc mem to parse config commands size - %d bytes\n", len));
+		return -1;
+	}
+
+	hotlist_params->lost_ap_window = GSCAN_LOST_AP_WINDOW_DEFAULT;
+
+	nla_for_each_attr(iter, data, len, tmp2) {
+		type = nla_type(iter);
+		switch (type) {
+		case GSCAN_ATTRIBUTE_HOTLIST_BSSIDS:
+			pbssid = hotlist_params->bssid;
+			nla_for_each_nested(outer, iter, tmp) {
+				nla_for_each_nested(inner, outer, tmp1) {
+					type = nla_type(inner);
+
+					switch (type) {
+					case GSCAN_ATTRIBUTE_BSSID:
+						memcpy(&(pbssid[j].macaddr),
+						       nla_data(inner), ETHER_ADDR_LEN);
+						break;
+					case GSCAN_ATTRIBUTE_RSSI_LOW:
+						pbssid[j].rssi_reporting_threshold =
+							(int8) nla_get_u8(inner);
+						break;
+					case GSCAN_ATTRIBUTE_RSSI_HIGH:
+						dummy = (int8) nla_get_u8(inner);
+						break;
+					}
+				}
+				j++;
+			}
+			hotlist_params->nbssid = j;
+			break;
+		case GSCAN_ATTRIBUTE_HOTLIST_FLUSH:
+			flush = nla_get_u8(iter);
+			break;
+		case GSCAN_ATTRIBUTE_LOST_AP_SAMPLE_SIZE:
+			hotlist_params->lost_ap_window = nla_get_u32(iter);
+			break;
+		}
+
+	}
+
+	if (dhd_dev_pno_set_cfg_gscan(bcmcfg_to_prmry_ndev(cfg),
+		DHD_PNO_GEOFENCE_SCAN_CFG_ID, hotlist_params, flush) < 0) {
+		WL_ERR(("Could not set GSCAN HOTLIST cfg\n"));
+		err = -EINVAL;
+		goto exit;
+	}
+exit:
+	kfree(hotlist_params);
+	return err;
+}
+static int rtw_cfgvendor_set_batch_scan_cfg(struct wiphy *wiphy,
+		struct wireless_dev *wdev, const void  *data, int len)
+{
+	int err = 0, tmp, type;
+	struct bcm_cfg80211 *cfg = wiphy_priv(wiphy);
+	gscan_batch_params_t batch_param;
+	const struct nlattr *iter;
+
+	batch_param.mscan = batch_param.bestn = 0;
+	batch_param.buffer_threshold = GSCAN_BATCH_NO_THR_SET;
+
+	nla_for_each_attr(iter, data, len, tmp) {
+		type = nla_type(iter);
+
+		switch (type) {
+		case GSCAN_ATTRIBUTE_NUM_AP_PER_SCAN:
+			batch_param.bestn = nla_get_u32(iter);
+			break;
+		case GSCAN_ATTRIBUTE_NUM_SCANS_TO_CACHE:
+			batch_param.mscan = nla_get_u32(iter);
+			break;
+		case GSCAN_ATTRIBUTE_REPORT_THRESHOLD:
+			batch_param.buffer_threshold = nla_get_u32(iter);
+			break;
+		}
+	}
+
+	if (dhd_dev_pno_set_cfg_gscan(bcmcfg_to_prmry_ndev(cfg),
+			      DHD_PNO_BATCH_SCAN_CFG_ID, &batch_param, 0) < 0) {
+		WL_ERR(("Could not set batch cfg\n"));
+		err = -EINVAL;
+		return err;
+	}
+
+	return err;
+}
+
+static int rtw_cfgvendor_significant_change_cfg(struct wiphy *wiphy,
+		struct wireless_dev *wdev, const void  *data, int len)
+{
+	int err = 0;
+	struct bcm_cfg80211 *cfg = wiphy_priv(wiphy);
+	gscan_swc_params_t *significant_params;
+	int tmp, tmp1, tmp2, type, j = 0;
+	const struct nlattr *outer, *inner, *iter;
+	uint8 flush = 0;
+	wl_pfn_significant_bssid_t *pbssid;
+
+	significant_params = (gscan_swc_params_t *) kzalloc(len, GFP_KERNEL);
+	if (!significant_params) {
+		WL_ERR(("Cannot Malloc mem to parse config commands size - %d bytes\n", len));
+		return -1;
+	}
+
+
+	nla_for_each_attr(iter, data, len, tmp2) {
+		type = nla_type(iter);
+
+		switch (type) {
+		case GSCAN_ATTRIBUTE_SIGNIFICANT_CHANGE_FLUSH:
+			flush = nla_get_u8(iter);
+			break;
+		case GSCAN_ATTRIBUTE_RSSI_SAMPLE_SIZE:
+			significant_params->rssi_window = nla_get_u16(iter);
+			break;
+		case GSCAN_ATTRIBUTE_LOST_AP_SAMPLE_SIZE:
+			significant_params->lost_ap_window = nla_get_u16(iter);
+			break;
+		case GSCAN_ATTRIBUTE_MIN_BREACHING:
+			significant_params->swc_threshold = nla_get_u16(iter);
+			break;
+		case GSCAN_ATTRIBUTE_SIGNIFICANT_CHANGE_BSSIDS:
+			pbssid = significant_params->bssid_elem_list;
+			nla_for_each_nested(outer, iter, tmp) {
+				nla_for_each_nested(inner, outer, tmp1) {
+					switch (nla_type(inner)) {
+					case GSCAN_ATTRIBUTE_BSSID:
+						memcpy(&(pbssid[j].macaddr),
+						       nla_data(inner),
+						       ETHER_ADDR_LEN);
+						break;
+					case GSCAN_ATTRIBUTE_RSSI_HIGH:
+						pbssid[j].rssi_high_threshold =
+							(int8) nla_get_u8(inner);
+						break;
+					case GSCAN_ATTRIBUTE_RSSI_LOW:
+						pbssid[j].rssi_low_threshold =
+							(int8) nla_get_u8(inner);
+						break;
+					}
+				}
+				j++;
+			}
+			break;
+		}
+	}
+	significant_params->nbssid = j;
+
+	if (dhd_dev_pno_set_cfg_gscan(bcmcfg_to_prmry_ndev(cfg),
+		DHD_PNO_SIGNIFICANT_SCAN_CFG_ID, significant_params, flush) < 0) {
+		WL_ERR(("Could not set GSCAN significant cfg\n"));
+		err = -EINVAL;
+		goto exit;
+	}
+exit:
+	kfree(significant_params);
+	return err;
+}
+#endif /* GSCAN_SUPPORT */
+
+#if defined(RTT_SUPPORT) && 0
+void rtw_cfgvendor_rtt_evt(void *ctx, void *rtt_data)
+{
+	struct wireless_dev *wdev = (struct wireless_dev *)ctx;
+	struct wiphy *wiphy;
+	struct sk_buff *skb;
+	uint32 tot_len = NLMSG_DEFAULT_SIZE, entry_len = 0;
+	gfp_t kflags;
+	rtt_report_t *rtt_report = NULL;
+	rtt_result_t *rtt_result = NULL;
+	struct list_head *rtt_list;
+	wiphy = wdev->wiphy;
+
+	WL_DBG(("In\n"));
+	/* Push the data to the skb */
+	if (!rtt_data) {
+		WL_ERR(("rtt_data is NULL\n"));
+		goto exit;
+	}
+	rtt_list = (struct list_head *)rtt_data;
+	kflags = in_atomic() ? GFP_ATOMIC : GFP_KERNEL;
+	/* Alloc the SKB for vendor_event */
+	skb = rtw_cfg80211_vendor_event_alloc(wiphy, wdev, tot_len, GOOGLE_RTT_COMPLETE_EVENT, kflags);
+	if (!skb) {
+		WL_ERR(("skb alloc failed"));
+		goto exit;
+	}
+	/* fill in the rtt results on each entry */
+	list_for_each_entry(rtt_result, rtt_list, list) {
+		entry_len = 0;
+		if (rtt_result->TOF_type == TOF_TYPE_ONE_WAY) {
+			entry_len = sizeof(rtt_report_t);
+			rtt_report = kzalloc(entry_len, kflags);
+			if (!rtt_report) {
+				WL_ERR(("rtt_report alloc failed"));
+				goto exit;
+			}
+			rtt_report->addr = rtt_result->peer_mac;
+			rtt_report->num_measurement = 1; /* ONE SHOT */
+			rtt_report->status = rtt_result->err_code;
+			rtt_report->type = (rtt_result->TOF_type == TOF_TYPE_ONE_WAY) ? RTT_ONE_WAY : RTT_TWO_WAY;
+			rtt_report->peer = rtt_result->target_info->peer;
+			rtt_report->channel = rtt_result->target_info->channel;
+			rtt_report->rssi = rtt_result->avg_rssi;
+			/* tx_rate */
+			rtt_report->tx_rate = rtt_result->tx_rate;
+			/* RTT */
+			rtt_report->rtt = rtt_result->meanrtt;
+			rtt_report->rtt_sd = rtt_result->sdrtt;
+			/* convert to centi meter */
+			if (rtt_result->distance != 0xffffffff)
+				rtt_report->distance = (rtt_result->distance >> 2) * 25;
+			else /* invalid distance */
+				rtt_report->distance = -1;
+
+			rtt_report->ts = rtt_result->ts;
+			nla_append(skb, entry_len, rtt_report);
+			kfree(rtt_report);
+		}
+	}
+	rtw_cfg80211_vendor_event(skb, kflags);
+exit:
+	return;
+}
+
+static int rtw_cfgvendor_rtt_set_config(struct wiphy *wiphy, struct wireless_dev *wdev,
+				       const void *data, int len)
+{
+	int err = 0, rem, rem1, rem2, type;
+	rtt_config_params_t rtt_param;
+	rtt_target_info_t *rtt_target = NULL;
+	const struct nlattr *iter, *iter1, *iter2;
+	int8 eabuf[ETHER_ADDR_STR_LEN];
+	int8 chanbuf[CHANSPEC_STR_LEN];
+	struct bcm_cfg80211 *cfg = wiphy_priv(wiphy);
+
+	WL_DBG(("In\n"));
+	err = dhd_dev_rtt_register_noti_callback(wdev->netdev, wdev, wl_cfgvendor_rtt_evt);
+	if (err < 0) {
+		WL_ERR(("failed to register rtt_noti_callback\n"));
+		goto exit;
+	}
+	memset(&rtt_param, 0, sizeof(rtt_param));
+	nla_for_each_attr(iter, data, len, rem) {
+		type = nla_type(iter);
+		switch (type) {
+		case RTT_ATTRIBUTE_TARGET_CNT:
+			rtt_param.rtt_target_cnt = nla_get_u8(iter);
+			if (rtt_param.rtt_target_cnt > RTT_MAX_TARGET_CNT) {
+				WL_ERR(("exceed max target count : %d\n",
+					rtt_param.rtt_target_cnt));
+				err = BCME_RANGE;
+			}
+			break;
+		case RTT_ATTRIBUTE_TARGET_INFO:
+			rtt_target = rtt_param.target_info;
+			nla_for_each_nested(iter1, iter, rem1) {
+				nla_for_each_nested(iter2, iter1, rem2) {
+					type = nla_type(iter2);
+					switch (type) {
+					case RTT_ATTRIBUTE_TARGET_MAC:
+						memcpy(&rtt_target->addr, nla_data(iter2), ETHER_ADDR_LEN);
+						break;
+					case RTT_ATTRIBUTE_TARGET_TYPE:
+						rtt_target->type = nla_get_u8(iter2);
+						break;
+					case RTT_ATTRIBUTE_TARGET_PEER:
+						rtt_target->peer = nla_get_u8(iter2);
+						break;
+					case RTT_ATTRIBUTE_TARGET_CHAN:
+						memcpy(&rtt_target->channel, nla_data(iter2),
+						       sizeof(rtt_target->channel));
+						break;
+					case RTT_ATTRIBUTE_TARGET_MODE:
+						rtt_target->continuous = nla_get_u8(iter2);
+						break;
+					case RTT_ATTRIBUTE_TARGET_INTERVAL:
+						rtt_target->interval = nla_get_u32(iter2);
+						break;
+					case RTT_ATTRIBUTE_TARGET_NUM_MEASUREMENT:
+						rtt_target->measure_cnt = nla_get_u32(iter2);
+						break;
+					case RTT_ATTRIBUTE_TARGET_NUM_PKT:
+						rtt_target->ftm_cnt = nla_get_u32(iter2);
+						break;
+					case RTT_ATTRIBUTE_TARGET_NUM_RETRY:
+						rtt_target->retry_cnt = nla_get_u32(iter2);
+					}
+				}
+				/* convert to chanspec value */
+				rtt_target->chanspec = dhd_rtt_convert_to_chspec(rtt_target->channel);
+				if (rtt_target->chanspec == 0) {
+					WL_ERR(("Channel is not valid\n"));
+					goto exit;
+				}
+				WL_INFORM(("Target addr %s, Channel : %s for RTT\n",
+					bcm_ether_ntoa((const struct ether_addr *)&rtt_target->addr, eabuf),
+					wf_chspec_ntoa(rtt_target->chanspec, chanbuf)));
+				rtt_target++;
+			}
+			break;
+		}
+	}
+	WL_DBG(("leave :target_cnt : %d\n", rtt_param.rtt_target_cnt));
+	if (dhd_dev_rtt_set_cfg(bcmcfg_to_prmry_ndev(cfg), &rtt_param) < 0) {
+		WL_ERR(("Could not set RTT configuration\n"));
+		err = -EINVAL;
+	}
+exit:
+	return err;
+}
+
+static int rtw_cfgvendor_rtt_cancel_config(struct wiphy *wiphy, struct wireless_dev *wdev,
+		const void *data, int len)
+{
+	int err = 0, rem, type, target_cnt = 0;
+	const struct nlattr *iter;
+	struct ether_addr *mac_list = NULL, *mac_addr = NULL;
+	struct bcm_cfg80211 *cfg = wiphy_priv(wiphy);
+
+	nla_for_each_attr(iter, data, len, rem) {
+		type = nla_type(iter);
+		switch (type) {
+		case RTT_ATTRIBUTE_TARGET_CNT:
+			target_cnt = nla_get_u8(iter);
+			mac_list = (struct ether_addr *)kzalloc(target_cnt * ETHER_ADDR_LEN , GFP_KERNEL);
+			if (mac_list == NULL) {
+				WL_ERR(("failed to allocate mem for mac list\n"));
+				goto exit;
+			}
+			mac_addr = &mac_list[0];
+			break;
+		case RTT_ATTRIBUTE_TARGET_MAC:
+			if (mac_addr)
+				memcpy(mac_addr++, nla_data(iter), ETHER_ADDR_LEN);
+			else {
+				WL_ERR(("mac_list is NULL\n"));
+				goto exit;
+			}
+			break;
+		}
+		if (dhd_dev_rtt_cancel_cfg(bcmcfg_to_prmry_ndev(cfg), mac_list, target_cnt) < 0) {
+			WL_ERR(("Could not cancel RTT configuration\n"));
+			err = -EINVAL;
+			goto exit;
+		}
+	}
+exit:
+	if (mac_list)
+		kfree(mac_list);
+	return err;
+}
+static int rtw_cfgvendor_rtt_get_capability(struct wiphy *wiphy, struct wireless_dev *wdev,
+		const void *data, int len)
+{
+	int err = 0;
+	struct bcm_cfg80211 *cfg = wiphy_priv(wiphy);
+	rtt_capabilities_t capability;
+
+	err = dhd_dev_rtt_capability(bcmcfg_to_prmry_ndev(cfg), &capability);
+	if (unlikely(err)) {
+		WL_ERR(("Vendor Command reply failed ret:%d\n", err));
+		goto exit;
+	}
+	err =  rtw_cfgvendor_send_cmd_reply(wiphy, bcmcfg_to_prmry_ndev(cfg),
+					    &capability, sizeof(capability));
+
+	if (unlikely(err))
+		WL_ERR(("Vendor Command reply failed ret:%d\n", err));
+exit:
+	return err;
+}
+
+#endif /* RTT_SUPPORT */
+
+#ifdef CONFIG_RTW_CFGVEDNOR_LLSTATS
+enum {
+    LSTATS_SUBCMD_GET_INFO = ANDROID_NL80211_SUBCMD_LSTATS_RANGE_START,
+	LSTATS_SUBCMD_SET_INFO,
+	LSTATS_SUBCMD_CLEAR_INFO,
+};
+static void LinkLayerStats(_adapter *padapter)
+{
+	struct xmit_priv		*pxmitpriv = &(padapter->xmitpriv);
+	struct recv_priv		*precvpriv = &(padapter->recvpriv);
+	struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter);
+	struct dvobj_priv	*pdvobjpriv = adapter_to_dvobj(padapter);
+	u32 ps_time, trx_total_time;
+	u64 tx_bytes, rx_bytes, trx_total_bytes = 0;
+	u64 tmp = 0;
+	
+	RTW_DBG("%s adapter type : %u\n", __func__, padapter->adapter_type);
+
+	tx_bytes = 0;
+	rx_bytes = 0;
+	ps_time = 0;
+	trx_total_time = 0;
+
+	if ( padapter->netif_up == _TRUE ) {
+
+		pwrpriv->on_time = rtw_get_passing_time_ms(pwrpriv->radio_on_start_time);
+
+		if (rtw_mi_check_fwstate(padapter, _FW_LINKED)) {
+			if ( pwrpriv->bpower_saving == _TRUE ) {
+				pwrpriv->pwr_saving_time += rtw_get_passing_time_ms(pwrpriv->pwr_saving_start_time);
+				pwrpriv->pwr_saving_start_time = rtw_get_current_time();
+			}
+		} else {		
+#ifdef CONFIG_IPS
+			if ( pwrpriv->bpower_saving == _TRUE ) {
+				pwrpriv->pwr_saving_time += rtw_get_passing_time_ms(pwrpriv->pwr_saving_start_time);
+				pwrpriv->pwr_saving_start_time = rtw_get_current_time();
+			}
+#else
+			pwrpriv->pwr_saving_time = pwrpriv->on_time;
+#endif
+		}
+
+		ps_time = pwrpriv->pwr_saving_time;
+
+		/* Deviation caused by caculation start time */
+		if ( ps_time > pwrpriv->on_time )
+			ps_time = pwrpriv->on_time;
+
+		tx_bytes = pdvobjpriv->traffic_stat.last_tx_bytes;
+		rx_bytes = pdvobjpriv->traffic_stat.last_rx_bytes;		
+		trx_total_bytes = tx_bytes + rx_bytes;
+
+		trx_total_time = pwrpriv->on_time - ps_time;
+
+		if ( trx_total_bytes == 0) {
+			pwrpriv->tx_time = 0;
+			pwrpriv->rx_time = 0;
+		} else {
+
+			/* tx_time = (trx_total_time * tx_total_bytes) / trx_total_bytes; */
+			/* rx_time = (trx_total_time * rx_total_bytes) / trx_total_bytes; */
+
+			tmp = (tx_bytes * trx_total_time);
+			tmp = rtw_division64(tmp, trx_total_bytes);
+			pwrpriv->tx_time = tmp;
+
+			tmp = (rx_bytes * trx_total_time);
+			tmp = rtw_division64(tmp, trx_total_bytes);
+			pwrpriv->rx_time = tmp;		
+
+		}
+	
+	}
+	else {
+			pwrpriv->on_time = 0;
+			pwrpriv->tx_time = 0;
+			pwrpriv->rx_time = 0;	
+	}
+
+#ifdef CONFIG_RTW_WIFI_HAL_DEBUG
+	RTW_INFO("- tx_bytes : %llu rx_bytes : %llu total bytes : %llu\n", tx_bytes, rx_bytes, trx_total_bytes);
+	RTW_INFO("- netif_up = %s, on_time : %u ms\n", padapter->netif_up ? "1":"0", pwrpriv->on_time);
+	RTW_INFO("- pwr_saving_time : %u (%u) ms\n", pwrpriv->pwr_saving_time, ps_time);
+	RTW_INFO("- trx_total_time : %u ms\n", trx_total_time);		
+	RTW_INFO("- tx_time : %u ms\n", pwrpriv->tx_time);
+	RTW_INFO("- rx_time : %u ms\n", pwrpriv->rx_time);	
+#endif /* CONFIG_RTW_WIFI_HAL_DEBUG */
+
+}
+
+#define DUMMY_TIME_STATICS 99
+static int rtw_cfgvendor_lstats_get_info(struct wiphy *wiphy,	
+	struct wireless_dev *wdev, const void  *data, int len)
+{
+	int err = 0;
+	_adapter *padapter = GET_PRIMARY_ADAPTER(wiphy_to_adapter(wiphy));
+	struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter);
+	wifi_radio_stat_internal *radio;
+	wifi_iface_stat *iface;
+	char *output;
+
+	output = rtw_malloc(sizeof(wifi_radio_stat_internal) + sizeof(wifi_iface_stat));
+	if (output == NULL) {
+		RTW_DBG("Allocate lstats info buffer fail!\n");
+	}
+
+	radio = (wifi_radio_stat_internal *)output;
+
+	radio->num_channels = 0;
+	radio->radio = 1;
+
+	/* to get on_time, tx_time, rx_time */
+	LinkLayerStats(padapter); 
+	
+	radio->on_time = pwrpriv->on_time;
+	radio->tx_time = pwrpriv->tx_time;
+	radio->rx_time = pwrpriv->rx_time;
+	radio->on_time_scan = 0;
+	radio->on_time_nbd = 0;
+	radio->on_time_gscan = 0;
+	radio->on_time_pno_scan = 0;
+	radio->on_time_hs20 = 0;
+	#ifdef CONFIG_RTW_WIFI_HAL_DEBUG
+	RTW_INFO("==== %s ====\n", __func__);
+	RTW_INFO("radio->radio : %d\n", (radio->radio));
+	RTW_INFO("pwrpriv->on_time : %u ms\n", (pwrpriv->on_time));
+	RTW_INFO("pwrpriv->tx_time :  %u ms\n", (pwrpriv->tx_time));
+	RTW_INFO("pwrpriv->rx_time :  %u ms\n", (pwrpriv->rx_time));
+	RTW_INFO("radio->on_time :  %u ms\n", (radio->on_time));
+	RTW_INFO("radio->tx_time :  %u ms\n", (radio->tx_time));
+	RTW_INFO("radio->rx_time :  %u ms\n", (radio->rx_time));
+	#endif /* CONFIG_RTW_WIFI_HAL_DEBUG */
+	
+	RTW_DBG(FUNC_NDEV_FMT" %s\n", FUNC_NDEV_ARG(wdev_to_ndev(wdev)), (char*)data);
+	err =  rtw_cfgvendor_send_cmd_reply(wiphy, wdev_to_ndev(wdev), 
+		output, sizeof(wifi_iface_stat) + sizeof(wifi_radio_stat_internal));
+	if (unlikely(err))
+		RTW_ERR(FUNC_NDEV_FMT"Vendor Command reply failed ret:%d \n"
+			, FUNC_NDEV_ARG(wdev_to_ndev(wdev)), err);
+	rtw_mfree(output, sizeof(wifi_iface_stat) + sizeof(wifi_radio_stat_internal));
+	return err;
+}
+static int rtw_cfgvendor_lstats_set_info(struct wiphy *wiphy,	
+	struct wireless_dev *wdev, const void  *data, int len)
+{
+	int err = 0;
+	RTW_INFO("%s\n", __func__);
+	return err;
+}
+static int rtw_cfgvendor_lstats_clear_info(struct wiphy *wiphy,	
+	struct wireless_dev *wdev, const void  *data, int len)
+{
+	int err = 0;
+	RTW_INFO("%s\n", __func__);
+	return err;
+}
+#endif /* CONFIG_RTW_CFGVEDNOR_LLSTATS */
+#ifdef CONFIG_RTW_CFGVEDNOR_RSSIMONITOR
+static int rtw_cfgvendor_set_rssi_monitor(struct wiphy *wiphy,
+	struct wireless_dev *wdev, const void  *data, int len)
+{
+        _adapter *padapter = GET_PRIMARY_ADAPTER(wiphy_to_adapter(wiphy));
+        struct rtw_wdev_priv *pwdev_priv = adapter_wdev_data(padapter);
+
+        struct recv_priv *precvpriv = &padapter->recvpriv;
+	int err = 0, rem, type;
+        const struct nlattr *iter;
+
+        RTW_DBG(FUNC_NDEV_FMT" %s\n", FUNC_NDEV_ARG(wdev_to_ndev(wdev)), (char*)data);
+
+	nla_for_each_attr(iter, data, len, rem) {
+		type = nla_type(iter);
+
+		switch (type) {
+        		case RSSI_MONITOR_ATTRIBUTE_MAX_RSSI:
+                                pwdev_priv->rssi_monitor_max = (s8)nla_get_u32(iter);;
+	        		break;
+		        case RSSI_MONITOR_ATTRIBUTE_MIN_RSSI:
+                                pwdev_priv->rssi_monitor_min = (s8)nla_get_u32(iter);
+			        break;
+        		case RSSI_MONITOR_ATTRIBUTE_START:
+                                pwdev_priv->rssi_monitor_enable = (u8)nla_get_u32(iter);
+	        		break;
+		}
+	}
+
+	return err;
+}
+
+void rtw_cfgvendor_rssi_monitor_evt(_adapter *padapter) {
+	struct wireless_dev *wdev =  padapter->rtw_wdev;
+	struct wiphy *wiphy= wdev->wiphy;
+        struct recv_priv *precvpriv = &padapter->recvpriv;
+	struct	mlme_priv	*pmlmepriv = &(padapter->mlmepriv);
+	struct	wlan_network	*pcur_network = &pmlmepriv->cur_network;
+        struct rtw_wdev_priv *pwdev_priv = adapter_wdev_data(padapter);
+	struct sk_buff *skb;
+	u32 tot_len = NLMSG_DEFAULT_SIZE;
+	gfp_t kflags;
+        rssi_monitor_evt data ;
+        s8 rssi = precvpriv->rssi;
+
+        if (pwdev_priv->rssi_monitor_enable == 0 || check_fwstate(pmlmepriv, _FW_LINKED) != _TRUE)
+                return;
+
+        if (rssi < pwdev_priv->rssi_monitor_max || rssi > pwdev_priv->rssi_monitor_min)
+                return;
+
+	kflags = in_atomic() ? GFP_ATOMIC : GFP_KERNEL;
+
+	/* Alloc the SKB for vendor_event */
+	skb = rtw_cfg80211_vendor_event_alloc(wiphy, wdev, tot_len, GOOGLE_RSSI_MONITOR_EVENT, kflags);
+	if (!skb) {
+		goto exit;
+	}
+
+        _rtw_memset(&data, 0, sizeof(data));
+
+        data.version = RSSI_MONITOR_EVT_VERSION;
+        data.cur_rssi = rssi;
+        _rtw_memcpy(data.BSSID, pcur_network->network.MacAddress, sizeof(mac_addr));
+
+        nla_append(skb, sizeof(data), &data);
+
+	rtw_cfg80211_vendor_event(skb, kflags);
+exit:
+	return;
+}
+#endif /* CONFIG_RTW_CFGVEDNOR_RSSIMONITR */
+
+#ifdef CONFIG_RTW_CFGVENDOR_WIFI_LOGGER
+static int rtw_cfgvendor_logger_start_logging(struct wiphy *wiphy,
+	struct wireless_dev *wdev, const void  *data, int len)
+{
+	int ret = 0, rem, type;
+	char ring_name[32] = {0};
+	int log_level = 0, flags = 0, time_intval = 0, threshold = 0;
+	const struct nlattr *iter;
+
+	nla_for_each_attr(iter, data, len, rem) {
+		type = nla_type(iter);
+		switch (type) {
+			case LOGGER_ATTRIBUTE_RING_NAME:
+				strncpy(ring_name, nla_data(iter),
+					MIN(sizeof(ring_name) -1, nla_len(iter)));
+				break;
+			case LOGGER_ATTRIBUTE_LOG_LEVEL:
+				log_level = nla_get_u32(iter);
+				break;
+			case LOGGER_ATTRIBUTE_RING_FLAGS:
+				flags = nla_get_u32(iter);
+				break;
+			case LOGGER_ATTRIBUTE_LOG_TIME_INTVAL:
+				time_intval = nla_get_u32(iter);
+				break;
+			case LOGGER_ATTRIBUTE_LOG_MIN_DATA_SIZE:
+				threshold = nla_get_u32(iter);
+				break;
+			default:
+				RTW_ERR("Unknown type: %d\n", type);
+				ret = WIFI_ERROR_INVALID_ARGS;
+				goto exit;
+		}
+	}
+
+exit:
+	return ret;
+}
+static int rtw_cfgvendor_logger_get_feature(struct wiphy *wiphy,
+	struct wireless_dev *wdev, const void *data, int len)
+{
+	int err = 0;
+	u32 supported_features = 0;
+
+	err =  rtw_cfgvendor_send_cmd_reply(wiphy, wdev_to_ndev(wdev), &supported_features, sizeof(supported_features));
+
+	if (unlikely(err))
+		RTW_ERR(FUNC_NDEV_FMT" Vendor Command reply failed ret:%d\n"
+			, FUNC_NDEV_ARG(wdev_to_ndev(wdev)), err);
+
+	return err;
+}
+static int rtw_cfgvendor_logger_get_version(struct wiphy *wiphy,
+	struct wireless_dev *wdev, const void *data, int len)
+{
+	_adapter *padapter = GET_PRIMARY_ADAPTER(wiphy_to_adapter(wiphy));
+	HAL_DATA_TYPE *hal = GET_HAL_DATA(padapter);
+	int ret = 0, rem, type;
+	int buf_len = 1024;
+	char *buf_ptr;
+	const struct nlattr *iter;
+	gfp_t kflags;
+
+	kflags = in_atomic() ? GFP_ATOMIC : GFP_KERNEL;
+	buf_ptr = kzalloc(buf_len, kflags);
+	if (!buf_ptr) {
+		RTW_ERR("failed to allocate the buffer for version n");
+		ret = -ENOMEM;
+		goto exit;
+	}
+	nla_for_each_attr(iter, data, len, rem) {
+		type = nla_type(iter);
+		switch (type) {
+			case LOGGER_ATTRIBUTE_GET_DRIVER:
+				memcpy(buf_ptr, DRIVERVERSION, strlen(DRIVERVERSION)+1);
+				break;
+			case LOGGER_ATTRIBUTE_GET_FW:
+				sprintf(buf_ptr, "v%d.%d", hal->firmware_version, hal->firmware_sub_version);
+				break;
+			default:
+				RTW_ERR("Unknown type: %d\n", type);
+				ret = -EINVAL;
+				goto exit;
+		}
+	}
+	if (ret < 0) {
+		RTW_ERR("failed to get the version %d\n", ret);
+		goto exit;
+	}
+
+
+	ret =  rtw_cfgvendor_send_cmd_reply(wiphy, wdev_to_ndev(wdev), buf_ptr, strlen(buf_ptr));
+exit:
+	kfree(buf_ptr);
+	return ret;
+}
+
+static int rtw_cfgvendor_logger_get_ring_status(struct wiphy *wiphy,
+	struct wireless_dev *wdev, const void  *data, int len)
+{
+	int ret = 0;
+	int ring_id;
+	char ring_buf_name[] = "RTW_RING_BUFFER";
+
+	struct sk_buff *skb;
+	wifi_ring_buffer_status ring_status;
+
+
+	_rtw_memcpy(ring_status.name, ring_buf_name, strlen(ring_buf_name)+1);
+	ring_status.ring_id = 1;
+	/* Alloc the SKB for vendor_event */
+	skb = cfg80211_vendor_cmd_alloc_reply_skb(wiphy,
+		sizeof(wifi_ring_buffer_status));
+	if (!skb) {
+		RTW_ERR("skb allocation is failed\n");
+		ret = FAIL;
+		goto exit;
+	}
+
+	nla_put_u32(skb, LOGGER_ATTRIBUTE_RING_NUM, 1);
+	nla_put(skb, LOGGER_ATTRIBUTE_RING_STATUS, sizeof(wifi_ring_buffer_status),
+				&ring_status);
+	ret = cfg80211_vendor_cmd_reply(skb);
+
+	if (ret) {
+		RTW_ERR("Vendor Command reply failed ret:%d \n", ret);
+	}
+exit:
+	return ret;
+}
+
+static int rtw_cfgvendor_logger_get_ring_data(struct wiphy *wiphy,
+	struct wireless_dev *wdev, const void  *data, int len)
+{
+	int ret = 0, rem, type;
+	char ring_name[32] = {0};
+	const struct nlattr *iter;
+
+	nla_for_each_attr(iter, data, len, rem) {
+		type = nla_type(iter);
+		switch (type) {
+			case LOGGER_ATTRIBUTE_RING_NAME:
+				strncpy(ring_name, nla_data(iter),
+					MIN(sizeof(ring_name) -1, nla_len(iter)));
+				RTW_INFO(" %s LOGGER_ATTRIBUTE_RING_NAME : %s\n", __func__, ring_name);
+				break;
+			default:
+				RTW_ERR("Unknown type: %d\n", type);
+				return ret;
+		}
+	}
+
+
+	return ret;
+}
+
+static int rtw_cfgvendor_logger_get_firmware_memory_dump(struct wiphy *wiphy,
+	struct wireless_dev *wdev, const void  *data, int len)
+{
+	int ret = WIFI_ERROR_NOT_SUPPORTED;
+
+	return ret;
+}
+
+static int rtw_cfgvendor_logger_start_pkt_fate_monitoring(struct wiphy *wiphy,
+	struct wireless_dev *wdev, const void  *data, int len)
+{
+	int ret = WIFI_SUCCESS;
+
+	return ret;
+}
+
+static int rtw_cfgvendor_logger_get_tx_pkt_fates(struct wiphy *wiphy,
+	struct wireless_dev *wdev, const void  *data, int len)
+{
+	int ret = WIFI_SUCCESS;
+
+	return ret;
+}
+
+static int rtw_cfgvendor_logger_get_rx_pkt_fates(struct wiphy *wiphy,
+	struct wireless_dev *wdev, const void  *data, int len)
+{
+	int ret = WIFI_SUCCESS;
+
+	return ret;
+}
+
+#endif /* CONFIG_RTW_CFGVENDOR_WIFI_LOGGER */
+#ifdef CONFIG_RTW_WIFI_HAL
+#ifdef CONFIG_RTW_CFGVENDOR_RANDOM_MAC_OUI
+
+#ifndef ETHER_ISMULTI
+#define ETHER_ISMULTI(ea) (((const u8 *)(ea))[0] & 1)
+#endif
+
+
+static u8 null_addr[ETH_ALEN] = {0};
+static void rtw_hal_random_gen_mac_addr(u8 *mac_addr)
+{
+	do {
+		get_random_bytes(&mac_addr[3], ETH_ALEN-3);
+		if (memcmp(mac_addr, null_addr, ETH_ALEN) != 0)
+			break;
+	} while(1);
+}
+
+void rtw_hal_pno_random_gen_mac_addr(PADAPTER adapter)
+{
+	u8 mac_addr[ETH_ALEN];
+	struct rtw_wdev_priv *pwdev_priv = adapter_wdev_data(adapter);
+
+	memcpy(mac_addr, pwdev_priv->pno_mac_addr, ETH_ALEN);
+	if (mac_addr[0] == 0xFF) return;
+	rtw_hal_random_gen_mac_addr(mac_addr);
+	memcpy(pwdev_priv->pno_mac_addr, mac_addr, ETH_ALEN);
+#ifdef CONFIG_RTW_DEBUG
+	print_hex_dump(KERN_DEBUG, "pno_mac_addr: ",
+		       DUMP_PREFIX_OFFSET, 16, 1, pwdev_priv->pno_mac_addr,
+		       ETH_ALEN, 1);
+#endif
+}
+
+void rtw_hal_set_hw_mac_addr(PADAPTER adapter, u8 *mac_addr)
+{
+	rtw_ps_deny(adapter, PS_DENY_IOCTL);
+	LeaveAllPowerSaveModeDirect(adapter);
+
+	rtw_hal_set_hwreg(adapter, HW_VAR_MAC_ADDR, mac_addr);
+#ifdef CONFIG_RTW_DEBUG
+	rtw_hal_dump_macaddr(RTW_DBGDUMP, adapter);
+#endif
+	rtw_ps_deny_cancel(adapter, PS_DENY_IOCTL);
+}
+
+static int rtw_cfgvendor_set_rand_mac_oui(struct wiphy *wiphy,
+		struct wireless_dev *wdev, const void  *data, int len)
+{
+	int err = 0;
+	PADAPTER adapter;
+	void *devaddr;
+	struct net_device *netdev;
+	int type, mac_len;
+	u8 pno_random_mac_oui[3];
+	u8 mac_addr[ETH_ALEN] = {0};
+	struct pwrctrl_priv *pwrctl;
+	struct rtw_wdev_priv *pwdev_priv;
+
+	type = nla_type(data);
+	mac_len = nla_len(data);
+	if (mac_len != 3) {
+		RTW_ERR("%s oui len error %d != 3\n", __func__, mac_len);
+		return -1;
+	}
+
+	if (type == ANDR_WIFI_ATTRIBUTE_RANDOM_MAC_OUI) {
+		memcpy(pno_random_mac_oui, nla_data(data), 3);
+		print_hex_dump(KERN_DEBUG, "pno_random_mac_oui: ",
+			       DUMP_PREFIX_OFFSET, 16, 1, pno_random_mac_oui,
+			       3, 1);
+
+		if (ETHER_ISMULTI(pno_random_mac_oui)) {
+			pr_err("%s: oui is multicast address\n", __func__);
+			return -1;
+		}
+
+		adapter = wiphy_to_adapter(wiphy);
+		if (adapter == NULL) {
+			pr_err("%s: wiphy_to_adapter == NULL\n", __func__);
+			return -1;
+		}
+
+		pwdev_priv = adapter_wdev_data(adapter);
+
+		memcpy(mac_addr, pno_random_mac_oui, 3);
+		rtw_hal_random_gen_mac_addr(mac_addr);
+		memcpy(pwdev_priv->pno_mac_addr, mac_addr, ETH_ALEN);
+#ifdef CONFIG_RTW_DEBUG
+		print_hex_dump(KERN_DEBUG, "pno_mac_addr: ",
+			       DUMP_PREFIX_OFFSET, 16, 1, pwdev_priv->pno_mac_addr,
+			       ETH_ALEN, 1);
+#endif
+	} else {
+		RTW_ERR("%s oui type error %x != 0x2\n", __func__, type);
+		err = -1;
+	}
+
+
+	return err;
+}
+
+#endif
+
+
+static int rtw_cfgvendor_set_nodfs_flag(struct wiphy *wiphy,
+	struct wireless_dev *wdev, const void *data, int len)
+{
+	int err = 0;	
+	int type;
+	u32 nodfs = 0;
+	_adapter *padapter = GET_PRIMARY_ADAPTER(wiphy_to_adapter(wiphy));
+
+	RTW_DBG(FUNC_NDEV_FMT" %s\n", FUNC_NDEV_ARG(wdev_to_ndev(wdev)), (char*)data);
+
+	type = nla_type(data);
+	if (type == ANDR_WIFI_ATTRIBUTE_NODFS_SET) {
+		nodfs = nla_get_u32(data);
+		adapter_to_dvobj(padapter)->nodfs = nodfs;
+	} else {
+		err = -EINVAL;
+	}
+
+	RTW_INFO("%s nodfs=%d, err=%d\n", __func__, nodfs, err);
+	
+	return err;
+}
+
+static int rtw_cfgvendor_set_country(struct wiphy *wiphy,
+	struct wireless_dev *wdev, const void  *data, int len)
+{
+#define CNTRY_BUF_SZ	4	/* Country string is 3 bytes + NUL */
+	int err = 0, rem, type;
+	char country_code[CNTRY_BUF_SZ] = {0};
+	const struct nlattr *iter;
+	_adapter *padapter = GET_PRIMARY_ADAPTER(wiphy_to_adapter(wiphy));
+
+	RTW_DBG(FUNC_NDEV_FMT" %s\n", FUNC_NDEV_ARG(wdev_to_ndev(wdev)), (char*)data);
+
+	nla_for_each_attr(iter, data, len, rem) {
+		type = nla_type(iter);
+		switch (type) {
+			case ANDR_WIFI_ATTRIBUTE_COUNTRY:
+				_rtw_memcpy(country_code, nla_data(iter),
+					MIN(nla_len(iter), CNTRY_BUF_SZ));
+				break;
+			default:
+				RTW_ERR("Unknown type: %d\n", type);
+				return -EINVAL;
+		}
+	}
+
+	RTW_INFO("%s country_code:\"%c%c\" \n", __func__, country_code[0], country_code[1]);
+
+	rtw_set_country(padapter, country_code);
+
+	return err;
+}
+
+static int rtw_cfgvendor_set_nd_offload(struct wiphy *wiphy,
+	struct wireless_dev *wdev, const void *data, int len)
+{
+	int err = 0;	
+	int type;
+	u8 nd_en = 0;
+	_adapter *padapter = GET_PRIMARY_ADAPTER(wiphy_to_adapter(wiphy));
+
+	RTW_DBG(FUNC_NDEV_FMT" %s\n", FUNC_NDEV_ARG(wdev_to_ndev(wdev)), (char*)data);
+
+	type = nla_type(data);
+	if (type == ANDR_WIFI_ATTRIBUTE_ND_OFFLOAD_VALUE) {
+		nd_en = nla_get_u8(data);
+		/* ND has been enabled when wow is enabled */
+	} else {
+		err = -EINVAL;
+	}
+
+	RTW_INFO("%s nd_en=%d, err=%d\n", __func__, nd_en, err);
+	
+	return err;
+}
+#endif /* CONFIG_RTW_WIFI_HAL */
+
+static const struct wiphy_vendor_command rtw_vendor_cmds[] = {
+#if defined(GSCAN_SUPPORT) && 0
+	{
+		{
+			.vendor_id = OUI_GOOGLE,
+			.subcmd = GSCAN_SUBCMD_GET_CAPABILITIES
+		},
+		.flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(5,3,0)
+		.policy = VENDOR_CMD_RAW_DATA,
+#endif
+		.doit = rtw_cfgvendor_gscan_get_capabilities
+	},
+	{
+		{
+			.vendor_id = OUI_GOOGLE,
+			.subcmd = GSCAN_SUBCMD_SET_CONFIG
+		},
+		.flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(5,3,0)
+		.policy = VENDOR_CMD_RAW_DATA,
+#endif
+		.doit = rtw_cfgvendor_set_scan_cfg
+	},
+	{
+		{
+			.vendor_id = OUI_GOOGLE,
+			.subcmd = GSCAN_SUBCMD_SET_SCAN_CONFIG
+		},
+		.flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(5,3,0)
+		.policy = VENDOR_CMD_RAW_DATA,
+#endif
+		.doit = rtw_cfgvendor_set_batch_scan_cfg
+	},
+	{
+		{
+			.vendor_id = OUI_GOOGLE,
+			.subcmd = GSCAN_SUBCMD_ENABLE_GSCAN
+		},
+		.flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(5,3,0)
+		.policy = VENDOR_CMD_RAW_DATA,
+#endif
+		.doit = rtw_cfgvendor_initiate_gscan
+	},
+	{
+		{
+			.vendor_id = OUI_GOOGLE,
+			.subcmd = GSCAN_SUBCMD_ENABLE_FULL_SCAN_RESULTS
+		},
+		.flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(5,3,0)
+		.policy = VENDOR_CMD_RAW_DATA,
+#endif
+		.doit = rtw_cfgvendor_enable_full_scan_result
+	},
+	{
+		{
+			.vendor_id = OUI_GOOGLE,
+			.subcmd = GSCAN_SUBCMD_SET_HOTLIST
+		},
+		.flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(5,3,0)
+		.policy = VENDOR_CMD_RAW_DATA,
+#endif
+		.doit = rtw_cfgvendor_hotlist_cfg
+	},
+	{
+		{
+			.vendor_id = OUI_GOOGLE,
+			.subcmd = GSCAN_SUBCMD_SET_SIGNIFICANT_CHANGE_CONFIG
+		},
+		.flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(5,3,0)
+		.policy = VENDOR_CMD_RAW_DATA,
+#endif
+		.doit = rtw_cfgvendor_significant_change_cfg
+	},
+	{
+		{
+			.vendor_id = OUI_GOOGLE,
+			.subcmd = GSCAN_SUBCMD_GET_SCAN_RESULTS
+		},
+		.flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(5,3,0)
+		.policy = VENDOR_CMD_RAW_DATA,
+#endif
+		.doit = rtw_cfgvendor_gscan_get_batch_results
+	},
+	{
+		{
+			.vendor_id = OUI_GOOGLE,
+			.subcmd = GSCAN_SUBCMD_GET_CHANNEL_LIST
+		},
+		.flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(5,3,0)
+		.policy = VENDOR_CMD_RAW_DATA,
+#endif
+		.doit = rtw_cfgvendor_gscan_get_channel_list
+	},
+#endif /* GSCAN_SUPPORT */
+#if defined(RTT_SUPPORT) && 0
+	{
+		{
+			.vendor_id = OUI_GOOGLE,
+			.subcmd = RTT_SUBCMD_SET_CONFIG
+		},
+		.flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(5,3,0)
+		.policy = VENDOR_CMD_RAW_DATA,
+#endif
+		.doit = rtw_cfgvendor_rtt_set_config
+	},
+	{
+		{
+			.vendor_id = OUI_GOOGLE,
+			.subcmd = RTT_SUBCMD_CANCEL_CONFIG
+		},
+		.flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(5,3,0)
+		.policy = VENDOR_CMD_RAW_DATA,
+#endif
+		.doit = rtw_cfgvendor_rtt_cancel_config
+	},
+	{
+		{
+			.vendor_id = OUI_GOOGLE,
+			.subcmd = RTT_SUBCMD_GETCAPABILITY
+		},
+		.flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(5,3,0)
+		.policy = VENDOR_CMD_RAW_DATA,
+#endif
+		.doit = rtw_cfgvendor_rtt_get_capability
+	},
+#endif /* RTT_SUPPORT */
+#ifdef CONFIG_RTW_CFGVEDNOR_LLSTATS
+	{
+		{
+			.vendor_id = OUI_GOOGLE,
+			.subcmd = LSTATS_SUBCMD_GET_INFO
+		},
+		.flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(5,3,0)
+		.policy = VENDOR_CMD_RAW_DATA,
+#endif
+		.doit = rtw_cfgvendor_lstats_get_info
+	},
+	{
+		{
+			.vendor_id = OUI_GOOGLE,
+			.subcmd = LSTATS_SUBCMD_SET_INFO
+		},
+		.flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(5,3,0)
+		.policy = VENDOR_CMD_RAW_DATA,
+#endif
+		.doit = rtw_cfgvendor_lstats_set_info
+	},
+	{
+		{
+			.vendor_id = OUI_GOOGLE,
+			.subcmd = LSTATS_SUBCMD_CLEAR_INFO
+		},
+		.flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(5,3,0)
+		.policy = VENDOR_CMD_RAW_DATA,
+#endif
+		.doit = rtw_cfgvendor_lstats_clear_info
+	},
+#endif /* CONFIG_RTW_CFGVEDNOR_LLSTATS */
+#ifdef CONFIG_RTW_CFGVEDNOR_RSSIMONITOR
+        {
+                {
+                        .vendor_id = OUI_GOOGLE,
+                        .subcmd = WIFI_SUBCMD_SET_RSSI_MONITOR
+                },
+                .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(5,3,0)
+		.policy = VENDOR_CMD_RAW_DATA,
+#endif
+                .doit = rtw_cfgvendor_set_rssi_monitor
+        },
+#endif /* CONFIG_RTW_CFGVEDNOR_RSSIMONITOR */
+#ifdef CONFIG_RTW_CFGVENDOR_WIFI_LOGGER
+	{
+		{
+			.vendor_id = OUI_GOOGLE,
+			.subcmd = LOGGER_START_LOGGING
+		},
+		.flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(5,3,0)
+		.policy = VENDOR_CMD_RAW_DATA,
+#endif
+		.doit = rtw_cfgvendor_logger_start_logging
+	},
+	{
+		{
+			.vendor_id = OUI_GOOGLE,
+			.subcmd = LOGGER_GET_FEATURE
+		},
+		.flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(5,3,0)
+		.policy = VENDOR_CMD_RAW_DATA,
+#endif
+		.doit = rtw_cfgvendor_logger_get_feature
+	},
+	{
+		{
+			.vendor_id = OUI_GOOGLE,
+			.subcmd = LOGGER_GET_VER
+		},
+		.flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(5,3,0)
+		.policy = VENDOR_CMD_RAW_DATA,
+#endif
+		.doit = rtw_cfgvendor_logger_get_version
+	},
+	{
+		{
+			.vendor_id = OUI_GOOGLE,
+			.subcmd = LOGGER_GET_RING_STATUS
+		},
+		.flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(5,3,0)
+		.policy = VENDOR_CMD_RAW_DATA,
+#endif
+		.doit = rtw_cfgvendor_logger_get_ring_status
+	},
+	{
+		{
+			.vendor_id = OUI_GOOGLE,
+			.subcmd = LOGGER_GET_RING_DATA
+		},
+		.flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(5,3,0)
+		.policy = VENDOR_CMD_RAW_DATA,
+#endif
+		.doit = rtw_cfgvendor_logger_get_ring_data
+	},
+	{
+		{
+			.vendor_id = OUI_GOOGLE,
+			.subcmd = LOGGER_TRIGGER_MEM_DUMP
+		},
+		.flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(5,3,0)
+		.policy = VENDOR_CMD_RAW_DATA,
+#endif
+		.doit = rtw_cfgvendor_logger_get_firmware_memory_dump
+	},
+	{
+		{
+			.vendor_id = OUI_GOOGLE,
+			.subcmd = LOGGER_START_PKT_FATE_MONITORING
+		},
+		.flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(5,3,0)
+		.policy = VENDOR_CMD_RAW_DATA,
+#endif
+		.doit = rtw_cfgvendor_logger_start_pkt_fate_monitoring
+	},
+	{
+		{
+			.vendor_id = OUI_GOOGLE,
+			.subcmd = LOGGER_GET_TX_PKT_FATES
+		},
+		.flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(5,3,0)
+		.policy = VENDOR_CMD_RAW_DATA,
+#endif
+		.doit = rtw_cfgvendor_logger_get_tx_pkt_fates
+	},
+	{
+		{
+			.vendor_id = OUI_GOOGLE,
+			.subcmd = LOGGER_GET_RX_PKT_FATES
+		},
+		.flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(5,3,0)
+		.policy = VENDOR_CMD_RAW_DATA,
+#endif
+		.doit = rtw_cfgvendor_logger_get_rx_pkt_fates
+	},	
+#endif /* CONFIG_RTW_CFGVENDOR_WIFI_LOGGER */
+#ifdef CONFIG_RTW_WIFI_HAL
+#ifdef CONFIG_RTW_CFGVENDOR_RANDOM_MAC_OUI
+	{
+		{
+			.vendor_id = OUI_GOOGLE,
+			.subcmd = WIFI_SUBCMD_SET_PNO_RANDOM_MAC_OUI
+		},
+		.flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(5,3,0)
+		.policy = VENDOR_CMD_RAW_DATA,
+#endif
+		.doit = rtw_cfgvendor_set_rand_mac_oui
+	},
+#endif
+	{
+		{
+			.vendor_id = OUI_GOOGLE,
+			.subcmd = WIFI_SUBCMD_NODFS_SET
+		},
+		.flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(5,3,0)
+		.policy = VENDOR_CMD_RAW_DATA,
+#endif
+		.doit = rtw_cfgvendor_set_nodfs_flag
+	},
+	{
+		{
+			.vendor_id = OUI_GOOGLE,
+			.subcmd = WIFI_SUBCMD_SET_COUNTRY_CODE
+		},
+		.flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(5,3,0)
+		.policy = VENDOR_CMD_RAW_DATA,
+#endif
+		.doit = rtw_cfgvendor_set_country
+	},
+	{
+		{
+			.vendor_id = OUI_GOOGLE,
+			.subcmd = WIFI_SUBCMD_CONFIG_ND_OFFLOAD
+		},
+		.flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(5,3,0)
+		.policy = VENDOR_CMD_RAW_DATA,
+#endif
+		.doit = rtw_cfgvendor_set_nd_offload
+	},
+#endif /* CONFIG_RTW_WIFI_HAL */
+	{
+		{
+			.vendor_id = OUI_GOOGLE,
+			.subcmd = WIFI_SUBCMD_GET_FEATURE_SET
+		},
+		.flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(5,3,0)
+		.policy = VENDOR_CMD_RAW_DATA,
+#endif
+		.doit = rtw_cfgvendor_get_feature_set
+	},
+	{
+		{
+			.vendor_id = OUI_GOOGLE,
+			.subcmd = WIFI_SUBCMD_GET_FEATURE_SET_MATRIX
+		},
+		.flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(5,3,0)
+		.policy = VENDOR_CMD_RAW_DATA,
+#endif
+		.doit = rtw_cfgvendor_get_feature_set_matrix
+	}
+};
+
+static const struct  nl80211_vendor_cmd_info rtw_vendor_events[] = {
+#if defined(GSCAN_SUPPORT) && 0
+	{ OUI_GOOGLE, GSCAN_EVENT_SIGNIFICANT_CHANGE_RESULTS },
+	{ OUI_GOOGLE, GSCAN_EVENT_HOTLIST_RESULTS_FOUND },
+	{ OUI_GOOGLE, GSCAN_EVENT_SCAN_RESULTS_AVAILABLE },
+	{ OUI_GOOGLE, GSCAN_EVENT_FULL_SCAN_RESULTS },
+#endif /* GSCAN_SUPPORT */
+#if defined(RTT_SUPPORT) && 0
+	{ OUI_GOOGLE, RTT_EVENT_COMPLETE },
+#endif /* RTT_SUPPORT */
+
+#ifdef CONFIG_RTW_CFGVEDNOR_RSSIMONITOR
+	{ OUI_GOOGLE, GOOGLE_RSSI_MONITOR_EVENT },
+#endif /* RTW_CFGVEDNOR_RSSIMONITR */
+
+#if defined(GSCAN_SUPPORT) && 0
+	{ OUI_GOOGLE, GSCAN_EVENT_COMPLETE_SCAN },
+	{ OUI_GOOGLE, GSCAN_EVENT_HOTLIST_RESULTS_LOST }
+#endif /* GSCAN_SUPPORT */
+};
+
+int rtw_cfgvendor_attach(struct wiphy *wiphy)
+{
+
+	RTW_INFO("Register RTW cfg80211 vendor cmd(0x%x) interface\n", NL80211_CMD_VENDOR);
+
+	wiphy->vendor_commands	= rtw_vendor_cmds;
+	wiphy->n_vendor_commands = ARRAY_SIZE(rtw_vendor_cmds);
+	wiphy->vendor_events	= rtw_vendor_events;
+	wiphy->n_vendor_events	= ARRAY_SIZE(rtw_vendor_events);
+
+	return 0;
+}
+
+int rtw_cfgvendor_detach(struct wiphy *wiphy)
+{
+	RTW_INFO("Vendor: Unregister RTW cfg80211 vendor interface\n");
+
+	wiphy->vendor_commands  = NULL;
+	wiphy->vendor_events    = NULL;
+	wiphy->n_vendor_commands = 0;
+	wiphy->n_vendor_events  = 0;
+
+	return 0;
+}
+#endif /* (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 14, 0)) || defined(RTW_VENDOR_EXT_SUPPORT) */
+
+#endif /* CONFIG_IOCTL_CFG80211 */
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/os_dep/linux/rtw_cfgvendor.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/os_dep/linux/rtw_cfgvendor.h
--- linux-5.6.3/3rdparty/rtl8821ce/os_dep/linux/rtw_cfgvendor.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/os_dep/linux/rtw_cfgvendor.h	2020-04-10 16:35:06.856661935 +0300
@@ -0,0 +1,633 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+
+#ifndef _RTW_CFGVENDOR_H_
+#define _RTW_CFGVENDOR_H_
+
+#define OUI_GOOGLE  0x001A11
+#define ATTRIBUTE_U32_LEN                  (NLA_HDRLEN  + 4)
+#define VENDOR_ID_OVERHEAD                 ATTRIBUTE_U32_LEN
+#define VENDOR_SUBCMD_OVERHEAD             ATTRIBUTE_U32_LEN
+#define VENDOR_DATA_OVERHEAD               (NLA_HDRLEN)
+
+#define SCAN_RESULTS_COMPLETE_FLAG_LEN       ATTRIBUTE_U32_LEN
+#define SCAN_INDEX_HDR_LEN                   (NLA_HDRLEN)
+#define SCAN_ID_HDR_LEN                      ATTRIBUTE_U32_LEN
+#define SCAN_FLAGS_HDR_LEN                   ATTRIBUTE_U32_LEN
+#define GSCAN_NUM_RESULTS_HDR_LEN            ATTRIBUTE_U32_LEN
+#define GSCAN_RESULTS_HDR_LEN                (NLA_HDRLEN)
+#define GSCAN_BATCH_RESULT_HDR_LEN  (SCAN_INDEX_HDR_LEN + SCAN_ID_HDR_LEN + \
+				     SCAN_FLAGS_HDR_LEN + \
+				     GSCAN_NUM_RESULTS_HDR_LEN + \
+				     GSCAN_RESULTS_HDR_LEN)
+
+#define VENDOR_REPLY_OVERHEAD       (VENDOR_ID_OVERHEAD + \
+				     VENDOR_SUBCMD_OVERHEAD + \
+				     VENDOR_DATA_OVERHEAD)
+typedef enum {
+    /* don't use 0 as a valid subcommand */
+    VENDOR_NL80211_SUBCMD_UNSPECIFIED,
+
+    /* define all vendor startup commands between 0x0 and 0x0FFF */
+    VENDOR_NL80211_SUBCMD_RANGE_START = 0x0001,
+    VENDOR_NL80211_SUBCMD_RANGE_END   = 0x0FFF,
+
+    /* define all GScan related commands between 0x1000 and 0x10FF */
+    ANDROID_NL80211_SUBCMD_GSCAN_RANGE_START = 0x1000,
+    ANDROID_NL80211_SUBCMD_GSCAN_RANGE_END   = 0x10FF,
+
+    /* define all NearbyDiscovery related commands between 0x1100 and 0x11FF */
+    ANDROID_NL80211_SUBCMD_NBD_RANGE_START = 0x1100,
+    ANDROID_NL80211_SUBCMD_NBD_RANGE_END   = 0x11FF,
+
+    /* define all RTT related commands between 0x1100 and 0x11FF */
+    ANDROID_NL80211_SUBCMD_RTT_RANGE_START = 0x1100,
+    ANDROID_NL80211_SUBCMD_RTT_RANGE_END   = 0x11FF,
+
+    ANDROID_NL80211_SUBCMD_LSTATS_RANGE_START = 0x1200,
+    ANDROID_NL80211_SUBCMD_LSTATS_RANGE_END   = 0x12FF,
+
+    /* define all Logger related commands between 0x1400 and 0x14FF */
+    ANDROID_NL80211_SUBCMD_DEBUG_RANGE_START = 0x1400,
+    ANDROID_NL80211_SUBCMD_DEBUG_RANGE_END   = 0x14FF,
+
+    /* define all wifi offload related commands between 0x1600 and 0x16FF */
+    ANDROID_NL80211_SUBCMD_WIFI_OFFLOAD_RANGE_START = 0x1600,
+    ANDROID_NL80211_SUBCMD_WIFI_OFFLOAD_RANGE_END   = 0x16FF,
+
+    /* define all NAN related commands between 0x1700 and 0x17FF */
+    ANDROID_NL80211_SUBCMD_NAN_RANGE_START = 0x1700,
+    ANDROID_NL80211_SUBCMD_NAN_RANGE_END   = 0x17FF,
+
+    /* define all Android Packet Filter related commands between 0x1800 and 0x18FF */
+    ANDROID_NL80211_SUBCMD_PKT_FILTER_RANGE_START = 0x1800,
+    ANDROID_NL80211_SUBCMD_PKT_FILTER_RANGE_END   = 0x18FF,
+
+    /* This is reserved for future usage */
+
+} ANDROID_VENDOR_SUB_COMMAND;
+
+enum rtw_vendor_subcmd {
+    GSCAN_SUBCMD_GET_CAPABILITIES = ANDROID_NL80211_SUBCMD_GSCAN_RANGE_START,
+
+    GSCAN_SUBCMD_SET_CONFIG,                            /* 0x1001 */
+
+    GSCAN_SUBCMD_SET_SCAN_CONFIG,                       /* 0x1002 */
+    GSCAN_SUBCMD_ENABLE_GSCAN,                          /* 0x1003 */
+    GSCAN_SUBCMD_GET_SCAN_RESULTS,                      /* 0x1004 */
+    GSCAN_SUBCMD_SCAN_RESULTS,                          /* 0x1005 */
+
+    GSCAN_SUBCMD_SET_HOTLIST,                           /* 0x1006 */
+
+    GSCAN_SUBCMD_SET_SIGNIFICANT_CHANGE_CONFIG,         /* 0x1007 */
+    GSCAN_SUBCMD_ENABLE_FULL_SCAN_RESULTS,              /* 0x1008 */
+    GSCAN_SUBCMD_GET_CHANNEL_LIST,                       /* 0x1009 */
+
+    WIFI_SUBCMD_GET_FEATURE_SET,                         /* 0x100A */
+    WIFI_SUBCMD_GET_FEATURE_SET_MATRIX,                  /* 0x100B */
+    WIFI_SUBCMD_SET_PNO_RANDOM_MAC_OUI,                  /* 0x100C */
+    WIFI_SUBCMD_NODFS_SET,                               /* 0x100D */
+    WIFI_SUBCMD_SET_COUNTRY_CODE,                             /* 0x100E */
+    /* Add more sub commands here */
+    GSCAN_SUBCMD_SET_EPNO_SSID,                          /* 0x100F */
+
+    WIFI_SUBCMD_SET_SSID_WHITE_LIST,                    /* 0x1010 */
+    WIFI_SUBCMD_SET_ROAM_PARAMS,                        /* 0x1011 */
+    WIFI_SUBCMD_ENABLE_LAZY_ROAM,                       /* 0x1012 */
+    WIFI_SUBCMD_SET_BSSID_PREF,                         /* 0x1013 */
+    WIFI_SUBCMD_SET_BSSID_BLACKLIST,                     /* 0x1014 */
+
+    GSCAN_SUBCMD_ANQPO_CONFIG,                          /* 0x1015 */
+    WIFI_SUBCMD_SET_RSSI_MONITOR,                       /* 0x1016 */
+    WIFI_SUBCMD_CONFIG_ND_OFFLOAD,                      /* 0x1017 */
+    /* Add more sub commands here */
+
+    GSCAN_SUBCMD_MAX,
+
+	RTT_SUBCMD_SET_CONFIG = ANDROID_NL80211_SUBCMD_RTT_RANGE_START,
+	RTT_SUBCMD_CANCEL_CONFIG,
+	RTT_SUBCMD_GETCAPABILITY,
+
+    APF_SUBCMD_GET_CAPABILITIES = ANDROID_NL80211_SUBCMD_PKT_FILTER_RANGE_START,
+    APF_SUBCMD_SET_FILTER,
+    
+    LOGGER_START_LOGGING = ANDROID_NL80211_SUBCMD_DEBUG_RANGE_START,
+    LOGGER_TRIGGER_MEM_DUMP,
+    LOGGER_GET_MEM_DUMP,
+    LOGGER_GET_VER,
+    LOGGER_GET_RING_STATUS,
+    LOGGER_GET_RING_DATA,
+    LOGGER_GET_FEATURE,
+    LOGGER_RESET_LOGGING,
+    LOGGER_TRIGGER_DRIVER_MEM_DUMP,
+    LOGGER_GET_DRIVER_MEM_DUMP,
+    LOGGER_START_PKT_FATE_MONITORING,
+    LOGGER_GET_TX_PKT_FATES,
+    LOGGER_GET_RX_PKT_FATES,
+
+	VENDOR_SUBCMD_MAX
+};
+
+enum gscan_attributes {
+	GSCAN_ATTRIBUTE_NUM_BUCKETS = 10,
+	GSCAN_ATTRIBUTE_BASE_PERIOD,
+	GSCAN_ATTRIBUTE_BUCKETS_BAND,
+	GSCAN_ATTRIBUTE_BUCKET_ID,
+	GSCAN_ATTRIBUTE_BUCKET_PERIOD,
+	GSCAN_ATTRIBUTE_BUCKET_NUM_CHANNELS,
+	GSCAN_ATTRIBUTE_BUCKET_CHANNELS,
+	GSCAN_ATTRIBUTE_NUM_AP_PER_SCAN,
+	GSCAN_ATTRIBUTE_REPORT_THRESHOLD,
+	GSCAN_ATTRIBUTE_NUM_SCANS_TO_CACHE,
+	GSCAN_ATTRIBUTE_BAND = GSCAN_ATTRIBUTE_BUCKETS_BAND,
+
+	GSCAN_ATTRIBUTE_ENABLE_FEATURE = 20,
+	GSCAN_ATTRIBUTE_SCAN_RESULTS_COMPLETE,
+	GSCAN_ATTRIBUTE_FLUSH_FEATURE,
+	GSCAN_ATTRIBUTE_ENABLE_FULL_SCAN_RESULTS,
+	GSCAN_ATTRIBUTE_REPORT_EVENTS,
+	/* remaining reserved for additional attributes */
+	GSCAN_ATTRIBUTE_NUM_OF_RESULTS = 30,
+	GSCAN_ATTRIBUTE_FLUSH_RESULTS,
+	GSCAN_ATTRIBUTE_SCAN_RESULTS,                       /* flat array of wifi_scan_result */
+	GSCAN_ATTRIBUTE_SCAN_ID,                            /* indicates scan number */
+	GSCAN_ATTRIBUTE_SCAN_FLAGS,                         /* indicates if scan was aborted */
+	GSCAN_ATTRIBUTE_AP_FLAGS,                           /* flags on significant change event */
+	GSCAN_ATTRIBUTE_NUM_CHANNELS,
+	GSCAN_ATTRIBUTE_CHANNEL_LIST,
+
+	/* remaining reserved for additional attributes */
+
+	GSCAN_ATTRIBUTE_SSID = 40,
+	GSCAN_ATTRIBUTE_BSSID,
+	GSCAN_ATTRIBUTE_CHANNEL,
+	GSCAN_ATTRIBUTE_RSSI,
+	GSCAN_ATTRIBUTE_TIMESTAMP,
+	GSCAN_ATTRIBUTE_RTT,
+	GSCAN_ATTRIBUTE_RTTSD,
+
+	/* remaining reserved for additional attributes */
+
+	GSCAN_ATTRIBUTE_HOTLIST_BSSIDS = 50,
+	GSCAN_ATTRIBUTE_RSSI_LOW,
+	GSCAN_ATTRIBUTE_RSSI_HIGH,
+	GSCAN_ATTRIBUTE_HOSTLIST_BSSID_ELEM,
+	GSCAN_ATTRIBUTE_HOTLIST_FLUSH,
+
+	/* remaining reserved for additional attributes */
+	GSCAN_ATTRIBUTE_RSSI_SAMPLE_SIZE = 60,
+	GSCAN_ATTRIBUTE_LOST_AP_SAMPLE_SIZE,
+	GSCAN_ATTRIBUTE_MIN_BREACHING,
+	GSCAN_ATTRIBUTE_SIGNIFICANT_CHANGE_BSSIDS,
+	GSCAN_ATTRIBUTE_SIGNIFICANT_CHANGE_FLUSH,
+	GSCAN_ATTRIBUTE_MAX
+};
+
+enum gscan_bucket_attributes {
+	GSCAN_ATTRIBUTE_CH_BUCKET_1,
+	GSCAN_ATTRIBUTE_CH_BUCKET_2,
+	GSCAN_ATTRIBUTE_CH_BUCKET_3,
+	GSCAN_ATTRIBUTE_CH_BUCKET_4,
+	GSCAN_ATTRIBUTE_CH_BUCKET_5,
+	GSCAN_ATTRIBUTE_CH_BUCKET_6,
+	GSCAN_ATTRIBUTE_CH_BUCKET_7
+};
+
+enum gscan_ch_attributes {
+	GSCAN_ATTRIBUTE_CH_ID_1,
+	GSCAN_ATTRIBUTE_CH_ID_2,
+	GSCAN_ATTRIBUTE_CH_ID_3,
+	GSCAN_ATTRIBUTE_CH_ID_4,
+	GSCAN_ATTRIBUTE_CH_ID_5,
+	GSCAN_ATTRIBUTE_CH_ID_6,
+	GSCAN_ATTRIBUTE_CH_ID_7
+};
+
+enum wifi_rssi_monitor_attr {
+        RSSI_MONITOR_ATTRIBUTE_MAX_RSSI,
+        RSSI_MONITOR_ATTRIBUTE_MIN_RSSI,
+        RSSI_MONITOR_ATTRIBUTE_START,
+};
+
+
+enum rtt_attributes {
+	RTT_ATTRIBUTE_TARGET_CNT,
+	RTT_ATTRIBUTE_TARGET_INFO,
+	RTT_ATTRIBUTE_TARGET_MAC,
+	RTT_ATTRIBUTE_TARGET_TYPE,
+	RTT_ATTRIBUTE_TARGET_PEER,
+	RTT_ATTRIBUTE_TARGET_CHAN,
+	RTT_ATTRIBUTE_TARGET_MODE,
+	RTT_ATTRIBUTE_TARGET_INTERVAL,
+	RTT_ATTRIBUTE_TARGET_NUM_MEASUREMENT,
+	RTT_ATTRIBUTE_TARGET_NUM_PKT,
+	RTT_ATTRIBUTE_TARGET_NUM_RETRY
+};
+
+enum logger_attributes {
+	LOGGER_ATTRIBUTE_GET_DRIVER,
+	LOGGER_ATTRIBUTE_GET_FW,
+	LOGGER_ATTRIBUTE_RING_ID,
+	LOGGER_ATTRIBUTE_RING_NAME,
+	LOGGER_ATTRIBUTE_RING_FLAGS,
+	LOGGER_ATTRIBUTE_LOG_LEVEL,
+	LOGGER_ATTRIBUTE_LOG_TIME_INTVAL,
+	LOGGER_ATTRIBUTE_LOG_MIN_DATA_SIZE,
+	LOGGER_ATTRIBUTE_FW_DUMP_LEN,
+	LOGGER_ATTRIBUTE_FW_DUMP_DATA,
+	LOGGERG_ATTRIBUTE_RING_DATA,
+	LOGGER_ATTRIBUTE_RING_STATUS,
+	LOGGER_ATTRIBUTE_RING_NUM
+};
+typedef enum rtw_vendor_event {
+    RTK_RESERVED1,
+    RTK_RESERVED2,
+    GSCAN_EVENT_SIGNIFICANT_CHANGE_RESULTS ,
+    GSCAN_EVENT_HOTLIST_RESULTS_FOUND,
+    GSCAN_EVENT_SCAN_RESULTS_AVAILABLE,
+    GSCAN_EVENT_FULL_SCAN_RESULTS,
+    RTT_EVENT_COMPLETE,
+    GSCAN_EVENT_COMPLETE_SCAN,
+    GSCAN_EVENT_HOTLIST_RESULTS_LOST,
+    GSCAN_EVENT_EPNO_EVENT,
+    GOOGLE_DEBUG_RING_EVENT,
+    GOOGLE_DEBUG_MEM_DUMP_EVENT,
+    GSCAN_EVENT_ANQPO_HOTSPOT_MATCH,
+    GOOGLE_RSSI_MONITOR_EVENT
+} rtw_vendor_event_t;
+
+enum andr_wifi_feature_set_attr {
+	ANDR_WIFI_ATTRIBUTE_NUM_FEATURE_SET,
+	ANDR_WIFI_ATTRIBUTE_FEATURE_SET,
+	ANDR_WIFI_ATTRIBUTE_RANDOM_MAC_OUI,
+	ANDR_WIFI_ATTRIBUTE_NODFS_SET,
+	ANDR_WIFI_ATTRIBUTE_COUNTRY,
+	ANDR_WIFI_ATTRIBUTE_ND_OFFLOAD_VALUE
+	// Add more attribute here
+};
+
+typedef enum rtw_vendor_gscan_attribute {
+	ATTR_START_GSCAN,
+	ATTR_STOP_GSCAN,
+	ATTR_SET_SCAN_BATCH_CFG_ID, /* set batch scan params */
+	ATTR_SET_SCAN_GEOFENCE_CFG_ID, /* set list of bssids to track */
+	ATTR_SET_SCAN_SIGNIFICANT_CFG_ID, /* set list of bssids, rssi threshold etc.. */
+	ATTR_SET_SCAN_CFG_ID, /* set common scan config params here */
+	ATTR_GET_GSCAN_CAPABILITIES_ID,
+	/* Add more sub commands here */
+	ATTR_GSCAN_MAX
+} rtw_vendor_gscan_attribute_t;
+
+typedef enum gscan_batch_attribute {
+	ATTR_GSCAN_BATCH_BESTN,
+	ATTR_GSCAN_BATCH_MSCAN,
+	ATTR_GSCAN_BATCH_BUFFER_THRESHOLD
+} gscan_batch_attribute_t;
+
+typedef enum gscan_geofence_attribute {
+	ATTR_GSCAN_NUM_HOTLIST_BSSID,
+	ATTR_GSCAN_HOTLIST_BSSID
+} gscan_geofence_attribute_t;
+
+typedef enum gscan_complete_event {
+	WIFI_SCAN_BUFFER_FULL,
+	WIFI_SCAN_COMPLETE
+} gscan_complete_event_t;
+/* wifi_hal.h */
+/* WiFi Common definitions */
+typedef unsigned char byte;
+typedef int wifi_request_id;
+typedef int wifi_channel;                       // indicates channel frequency in MHz
+typedef int wifi_rssi;
+typedef byte mac_addr[6];
+typedef byte oui[3];
+typedef int64_t wifi_timestamp;                 // In microseconds (us)
+typedef int64_t wifi_timespan;                  // In picoseconds  (ps)
+
+struct wifi_info;
+struct wifi_interface_info;
+typedef struct wifi_info *wifi_handle;
+typedef struct wifi_interface_info *wifi_interface_handle;
+
+/* channel operating width */
+typedef enum {
+    WIFI_CHAN_WIDTH_20    = 0,
+    WIFI_CHAN_WIDTH_40    = 1,
+    WIFI_CHAN_WIDTH_80    = 2,
+    WIFI_CHAN_WIDTH_160   = 3,
+    WIFI_CHAN_WIDTH_80P80 = 4,
+    WIFI_CHAN_WIDTH_5     = 5,
+    WIFI_CHAN_WIDTH_10    = 6,
+    WIFI_CHAN_WIDTH_INVALID = -1
+} wifi_channel_width;
+
+typedef int wifi_radio;
+
+typedef struct {
+    wifi_channel_width width;
+    int center_frequency0;
+    int center_frequency1;
+    int primary_frequency;
+} wifi_channel_spec;
+
+typedef enum {
+    WIFI_SUCCESS = 0,
+    WIFI_ERROR_NONE = 0,
+    WIFI_ERROR_UNKNOWN = -1,
+    WIFI_ERROR_UNINITIALIZED = -2,
+    WIFI_ERROR_NOT_SUPPORTED = -3,
+    WIFI_ERROR_NOT_AVAILABLE = -4,              // Not available right now, but try later
+    WIFI_ERROR_INVALID_ARGS = -5,
+    WIFI_ERROR_INVALID_REQUEST_ID = -6,
+    WIFI_ERROR_TIMED_OUT = -7,
+    WIFI_ERROR_TOO_MANY_REQUESTS = -8,          // Too many instances of this request
+    WIFI_ERROR_OUT_OF_MEMORY = -9,
+    WIFI_ERROR_BUSY = -10,
+} wifi_error;
+
+typedef int wifi_ring_buffer_id;
+/* ring buffer params */
+/**
+ * written_bytes and read_bytes implement a producer consumer API
+ *     hence written_bytes >= read_bytes
+ * a modulo arithmetic of the buffer size has to be applied to those counters:
+ * actual offset into ring buffer = written_bytes % ring_buffer_byte_size
+ *
+ */
+typedef struct {
+    u8 name[32];
+    u32 flags;
+    wifi_ring_buffer_id ring_id; // unique integer representing the ring
+    u32 ring_buffer_byte_size;   // total memory size allocated for the buffer
+    u32 verbose_level;           // verbose level for ring buffer
+    u32 written_bytes;           // number of bytes that was written to the buffer by driver,
+                                 // monotonously increasing integer
+    u32 read_bytes;              // number of bytes that was read from the buffer by user land,
+                                 // monotonously increasing integer
+    u32 written_records;         // number of records that was written to the buffer by driver,
+                                 // monotonously increasing integer
+} wifi_ring_buffer_status;
+
+#ifdef CONFIG_RTW_CFGVEDNOR_LLSTATS
+#define STATS_MAJOR_VERSION      1
+#define STATS_MINOR_VERSION      0
+#define STATS_MICRO_VERSION      0
+
+typedef enum {
+    WIFI_DISCONNECTED = 0,
+    WIFI_AUTHENTICATING = 1,
+    WIFI_ASSOCIATING = 2,
+    WIFI_ASSOCIATED = 3,
+    WIFI_EAPOL_STARTED = 4,   // if done by firmware/driver
+    WIFI_EAPOL_COMPLETED = 5, // if done by firmware/driver
+} wifi_connection_state;
+
+typedef enum {
+    WIFI_ROAMING_IDLE = 0,
+    WIFI_ROAMING_ACTIVE = 1,
+} wifi_roam_state;
+
+typedef enum {
+    WIFI_INTERFACE_STA = 0,
+    WIFI_INTERFACE_SOFTAP = 1,
+    WIFI_INTERFACE_IBSS = 2,
+    WIFI_INTERFACE_P2P_CLIENT = 3,
+    WIFI_INTERFACE_P2P_GO = 4,
+    WIFI_INTERFACE_NAN = 5,
+    WIFI_INTERFACE_MESH = 6,
+    WIFI_INTERFACE_UNKNOWN = -1
+ } wifi_interface_mode;
+
+#define WIFI_CAPABILITY_QOS          0x00000001     // set for QOS association
+#define WIFI_CAPABILITY_PROTECTED    0x00000002     // set for protected association (802.11 beacon frame control protected bit set)
+#define WIFI_CAPABILITY_INTERWORKING 0x00000004     // set if 802.11 Extended Capabilities element interworking bit is set
+#define WIFI_CAPABILITY_HS20         0x00000008     // set for HS20 association
+#define WIFI_CAPABILITY_SSID_UTF8    0x00000010     // set is 802.11 Extended Capabilities element UTF-8 SSID bit is set
+#define WIFI_CAPABILITY_COUNTRY      0x00000020     // set is 802.11 Country Element is present
+
+typedef struct {
+   wifi_interface_mode mode;     // interface mode
+   u8 mac_addr[6];               // interface mac address (self)
+   wifi_connection_state state;  // connection state (valid for STA, CLI only)
+   wifi_roam_state roaming;      // roaming state
+   u32 capabilities;             // WIFI_CAPABILITY_XXX (self)
+   u8 ssid[33];                  // null terminated SSID
+   u8 bssid[6];                  // bssid
+   u8 ap_country_str[3];         // country string advertised by AP
+   u8 country_str[3];            // country string for this association
+} wifi_interface_link_layer_info;
+
+/* channel information */
+typedef struct {
+   wifi_channel_width width;   // channel width (20, 40, 80, 80+80, 160)
+   wifi_channel center_freq;   // primary 20 MHz channel
+   wifi_channel center_freq0;  // center frequency (MHz) first segment
+   wifi_channel center_freq1;  // center frequency (MHz) second segment
+} wifi_channel_info;
+
+/* wifi rate */
+typedef struct {
+   u32 preamble   :3;   // 0: OFDM, 1:CCK, 2:HT 3:VHT 4..7 reserved
+   u32 nss        :2;   // 0:1x1, 1:2x2, 3:3x3, 4:4x4
+   u32 bw         :3;   // 0:20MHz, 1:40Mhz, 2:80Mhz, 3:160Mhz
+   u32 rateMcsIdx :8;   // OFDM/CCK rate code would be as per ieee std in the units of 0.5mbps
+                        // HT/VHT it would be mcs index
+   u32 reserved  :16;   // reserved
+   u32 bitrate;         // units of 100 Kbps
+} wifi_rate;
+
+/* channel statistics */
+typedef struct {
+   wifi_channel_info channel;  // channel
+   u32 on_time;                // msecs the radio is awake (32 bits number accruing over time)
+   u32 cca_busy_time;          // msecs the CCA register is busy (32 bits number accruing over time)
+} wifi_channel_stat;
+
+// Max number of tx power levels. The actual number vary per device and is specified by |num_tx_levels|
+#define RADIO_STAT_MAX_TX_LEVELS 256
+
+/* Internal radio statistics structure in the driver */
+typedef struct {
+   wifi_radio radio;                      // wifi radio (if multiple radio supported)
+   u32 on_time;                           // msecs the radio is awake (32 bits number accruing over time)
+   u32 tx_time;                           // msecs the radio is transmitting (32 bits number accruing over time)
+   u32 rx_time;                           // msecs the radio is in active receive (32 bits number accruing over time)
+   u32 on_time_scan;                      // msecs the radio is awake due to all scan (32 bits number accruing over time)
+   u32 on_time_nbd;                       // msecs the radio is awake due to NAN (32 bits number accruing over time)
+   u32 on_time_gscan;                     // msecs the radio is awake due to G?scan (32 bits number accruing over time)
+   u32 on_time_roam_scan;                 // msecs the radio is awake due to roam?scan (32 bits number accruing over time)
+   u32 on_time_pno_scan;                  // msecs the radio is awake due to PNO scan (32 bits number accruing over time)
+   u32 on_time_hs20;                      // msecs the radio is awake due to HS2.0 scans and GAS exchange (32 bits number accruing over time)
+   u32 num_channels;                      // number of channels
+   wifi_channel_stat channels[];          // channel statistics
+} wifi_radio_stat_internal;
+
+/**
+ * Packet statistics reporting by firmware is performed on MPDU basi (i.e. counters increase by 1 for each MPDU)
+ * As well, "data packet" in associated comments, shall be interpreted as 802.11 data packet,
+ * that is, 802.11 frame control subtype == 2 and excluding management and control frames.
+ *
+ * As an example, in the case of transmission of an MSDU fragmented in 16 MPDUs which are transmitted
+ * OTA in a 16 units long a-mpdu, for which a block ack is received with 5 bits set:
+ *          tx_mpdu : shall increase by 5
+ *          retries : shall increase by 16
+ *          tx_ampdu : shall increase by 1
+ * data packet counters shall not increase regardless of the number of BAR potentially sent by device for this a-mpdu
+ * data packet counters shall not increase regardless of the number of BA received by device for this a-mpdu
+ *
+ * For each subsequent retransmission of the 11 remaining non ACK'ed mpdus
+ * (regardless of the fact that they are transmitted in a-mpdu or not)
+ *          retries : shall increase by 1
+ *
+ * If no subsequent BA or ACK are received from AP, until packet lifetime expires for those 11 packet that were not ACK'ed
+ *          mpdu_lost : shall increase by 11
+ */
+
+/* per rate statistics */
+typedef struct {
+   wifi_rate rate;     // rate information
+   u32 tx_mpdu;        // number of successfully transmitted data pkts (ACK rcvd)
+   u32 rx_mpdu;        // number of received data pkts
+   u32 mpdu_lost;      // number of data packet losses (no ACK)
+   u32 retries;        // total number of data pkt retries
+   u32 retries_short;  // number of short data pkt retries
+   u32 retries_long;   // number of long data pkt retries
+} wifi_rate_stat;
+
+/* access categories */
+typedef enum {
+   WIFI_AC_VO  = 0,
+   WIFI_AC_VI  = 1,
+   WIFI_AC_BE  = 2,
+   WIFI_AC_BK  = 3,
+   WIFI_AC_MAX = 4,
+} wifi_traffic_ac;
+
+/* wifi peer type */
+typedef enum
+{
+   WIFI_PEER_STA,
+   WIFI_PEER_AP,
+   WIFI_PEER_P2P_GO,
+   WIFI_PEER_P2P_CLIENT,
+   WIFI_PEER_NAN,
+   WIFI_PEER_TDLS,
+   WIFI_PEER_INVALID,
+} wifi_peer_type;
+
+/* per peer statistics */
+typedef struct {
+   wifi_peer_type type;           // peer type (AP, TDLS, GO etc.)
+   u8 peer_mac_address[6];        // mac address
+   u32 capabilities;              // peer WIFI_CAPABILITY_XXX
+   u32 num_rate;                  // number of rates
+   wifi_rate_stat rate_stats[];   // per rate statistics, number of entries  = num_rate
+} wifi_peer_info;
+
+/* Per access category statistics */
+typedef struct {
+   wifi_traffic_ac ac;             // access category (VI, VO, BE, BK)
+   u32 tx_mpdu;                    // number of successfully transmitted unicast data pkts (ACK rcvd)
+   u32 rx_mpdu;                    // number of received unicast data packets
+   u32 tx_mcast;                   // number of succesfully transmitted multicast data packets
+                                   // STA case: implies ACK received from AP for the unicast packet in which mcast pkt was sent
+   u32 rx_mcast;                   // number of received multicast data packets
+   u32 rx_ampdu;                   // number of received unicast a-mpdus; support of this counter is optional
+   u32 tx_ampdu;                   // number of transmitted unicast a-mpdus; support of this counter is optional
+   u32 mpdu_lost;                  // number of data pkt losses (no ACK)
+   u32 retries;                    // total number of data pkt retries
+   u32 retries_short;              // number of short data pkt retries
+   u32 retries_long;               // number of long data pkt retries
+   u32 contention_time_min;        // data pkt min contention time (usecs)
+   u32 contention_time_max;        // data pkt max contention time (usecs)
+   u32 contention_time_avg;        // data pkt avg contention time (usecs)
+   u32 contention_num_samples;     // num of data pkts used for contention statistics
+} wifi_wmm_ac_stat;
+
+/* interface statistics */
+typedef struct {
+   wifi_interface_handle iface;          // wifi interface
+   wifi_interface_link_layer_info info;  // current state of the interface
+   u32 beacon_rx;                        // access point beacon received count from connected AP
+   u64 average_tsf_offset;               // average beacon offset encountered (beacon_TSF - TBTT)
+                                         // The average_tsf_offset field is used so as to calculate the
+                                         // typical beacon contention time on the channel as well may be
+                                         // used to debug beacon synchronization and related power consumption issue
+   u32 leaky_ap_detected;                // indicate that this AP typically leaks packets beyond the driver guard time.
+   u32 leaky_ap_avg_num_frames_leaked;  // average number of frame leaked by AP after frame with PM bit set was ACK'ed by AP
+   u32 leaky_ap_guard_time;              // guard time currently in force (when implementing IEEE power management based on
+                                         // frame control PM bit), How long driver waits before shutting down the radio and
+                                         // after receiving an ACK for a data frame with PM bit set)
+   u32 mgmt_rx;                          // access point mgmt frames received count from connected AP (including Beacon)
+   u32 mgmt_action_rx;                   // action frames received count
+   u32 mgmt_action_tx;                   // action frames transmit count
+   wifi_rssi rssi_mgmt;                  // access Point Beacon and Management frames RSSI (averaged)
+   wifi_rssi rssi_data;                  // access Point Data Frames RSSI (averaged) from connected AP
+   wifi_rssi rssi_ack;                   // access Point ACK RSSI (averaged) from connected AP
+   wifi_wmm_ac_stat ac[WIFI_AC_MAX];     // per ac data packet statistics
+   u32 num_peers;                        // number of peers
+   wifi_peer_info peer_info[];           // per peer statistics
+} wifi_iface_stat;
+
+/* configuration params */
+typedef struct {
+   u32 mpdu_size_threshold;             // threshold to classify the pkts as short or long
+                                        // packet size < mpdu_size_threshold => short
+   u32 aggressive_statistics_gathering; // set for field debug mode. Driver should collect all statistics regardless of performance impact.
+} wifi_link_layer_params;
+
+#define RSSI_MONITOR_EVT_VERSION   1
+typedef struct {
+    u8 version;
+    s8 cur_rssi;
+    mac_addr BSSID;
+} rssi_monitor_evt;
+
+
+/* wifi statistics bitmap  */
+#define WIFI_STATS_RADIO              0x00000001      // all radio statistics
+#define WIFI_STATS_RADIO_CCA          0x00000002      // cca_busy_time (within radio statistics)
+#define WIFI_STATS_RADIO_CHANNELS     0x00000004      // all channel statistics (within radio statistics)
+#define WIFI_STATS_RADIO_SCAN         0x00000008      // all scan statistics (within radio statistics)
+#define WIFI_STATS_IFACE              0x00000010      // all interface statistics
+#define WIFI_STATS_IFACE_TXRATE       0x00000020      // all tx rate statistics (within interface statistics)
+#define WIFI_STATS_IFACE_AC           0x00000040      // all ac statistics (within interface statistics)
+#define WIFI_STATS_IFACE_CONTENTION   0x00000080      // all contention (min, max, avg) statistics (within ac statisctics)
+
+#endif /* CONFIG_RTW_CFGVEDNOR_LLSTATS */
+
+
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 14, 0)) || defined(RTW_VENDOR_EXT_SUPPORT)
+extern int rtw_cfgvendor_attach(struct wiphy *wiphy);
+extern int rtw_cfgvendor_detach(struct wiphy *wiphy);
+extern int rtw_cfgvendor_send_async_event(struct wiphy *wiphy,
+	struct net_device *dev, int event_id, const void  *data, int len);
+#if defined(GSCAN_SUPPORT) && 0
+extern int rtw_cfgvendor_send_hotlist_event(struct wiphy *wiphy,
+	struct net_device *dev, void  *data, int len, rtw_vendor_event_t event);
+#endif
+#endif /* (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 14, 0)) || defined(RTW_VENDOR_EXT_SUPPORT) */
+
+#ifdef CONFIG_RTW_CFGVEDNOR_RSSIMONITOR
+void rtw_cfgvendor_rssi_monitor_evt(_adapter *padapter);
+#endif
+
+#ifdef CONFIG_RTW_CFGVENDOR_RANDOM_MAC_OUI
+void rtw_hal_pno_random_gen_mac_addr(PADAPTER adapter);
+void rtw_hal_set_hw_mac_addr(PADAPTER adapter, u8 *mac_addr);
+#endif
+
+
+#endif /* _RTW_CFGVENDOR_H_ */
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/os_dep/linux/rtw_proc.c linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/os_dep/linux/rtw_proc.c
--- linux-5.6.3/3rdparty/rtl8821ce/os_dep/linux/rtw_proc.c	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/os_dep/linux/rtw_proc.c	2020-04-10 16:35:06.857661982 +0300
@@ -0,0 +1,4483 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+
+#include <linux/ctype.h>	/* tolower() */
+#include <drv_types.h>
+#include <hal_data.h>
+#include "rtw_proc.h"
+#include <rtw_btcoex.h>
+
+#ifdef CONFIG_PROC_DEBUG
+
+static struct proc_dir_entry *rtw_proc = NULL;
+
+inline struct proc_dir_entry *get_rtw_drv_proc(void)
+{
+	return rtw_proc;
+}
+
+#define RTW_PROC_NAME DRV_NAME
+
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 9, 0))
+#define file_inode(file) ((file)->f_dentry->d_inode)
+#endif
+
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 10, 0))
+#define PDE_DATA(inode) PDE((inode))->data
+#define proc_get_parent_data(inode) PDE((inode))->parent->data
+#endif
+
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 24))
+#define get_proc_net proc_net
+#else
+#define get_proc_net init_net.proc_net
+#endif
+
+inline struct proc_dir_entry *rtw_proc_create_dir(const char *name, struct proc_dir_entry *parent, void *data)
+{
+	struct proc_dir_entry *entry;
+
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 10, 0))
+	entry = proc_mkdir_data(name, S_IRUGO | S_IXUGO, parent, data);
+#else
+	/* entry = proc_mkdir_mode(name, S_IRUGO|S_IXUGO, parent); */
+	entry = proc_mkdir(name, parent);
+	if (entry)
+		entry->data = data;
+#endif
+
+	return entry;
+}
+
+inline struct proc_dir_entry *rtw_proc_create_entry(const char *name, struct proc_dir_entry *parent,
+	#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 6, 0))
+	const struct file_operations *fops,
+	#else
+	const struct proc_ops *fops,
+	#endif
+	void * data
+	)
+{
+	struct proc_dir_entry *entry;
+
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 26))
+	entry = proc_create_data(name,  S_IFREG | S_IRUGO | S_IWUGO, parent, fops, data);
+#else
+	entry = create_proc_entry(name, S_IFREG | S_IRUGO | S_IWUGO, parent);
+	if (entry) {
+		entry->data = data;
+		entry->proc_fops = fops;
+	}
+#endif
+
+	return entry;
+}
+
+static int proc_get_dummy(struct seq_file *m, void *v)
+{
+	return 0;
+}
+
+static int proc_get_drv_version(struct seq_file *m, void *v)
+{
+	dump_drv_version(m);
+	return 0;
+}
+
+static int proc_get_log_level(struct seq_file *m, void *v)
+{
+	dump_log_level(m);
+	return 0;
+}
+
+static int proc_get_drv_cfg(struct seq_file *m, void *v)
+{
+	dump_drv_cfg(m);
+	return 0;
+}
+
+static ssize_t proc_set_log_level(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
+{
+	char tmp[32];
+	int log_level;
+
+	if (count < 1)
+		return -EINVAL;
+
+	if (count > sizeof(tmp)) {
+		rtw_warn_on(1);
+		return -EFAULT;
+	}
+
+#ifdef CONFIG_RTW_DEBUG
+	if (buffer && !copy_from_user(tmp, buffer, count)) {
+
+		int num = sscanf(tmp, "%d ", &log_level);
+
+		if (num == 1 &&
+		    log_level >= _DRV_NONE_ && log_level <= _DRV_MAX_) {
+			rtw_drv_log_level = log_level;
+			printk("rtw_drv_log_level:%d\n", rtw_drv_log_level);
+		}
+	} else
+		return -EFAULT;
+#else
+	printk("CONFIG_RTW_DEBUG is disabled\n");
+#endif
+
+	return count;
+}
+
+#ifdef DBG_MEM_ALLOC
+static int proc_get_mstat(struct seq_file *m, void *v)
+{
+	rtw_mstat_dump(m);
+	return 0;
+}
+#endif /* DBG_MEM_ALLOC */
+
+static int proc_get_country_chplan_map(struct seq_file *m, void *v)
+{
+	dump_country_chplan_map(m);
+	return 0;
+}
+
+static int proc_get_chplan_id_list(struct seq_file *m, void *v)
+{
+	dump_chplan_id_list(m);
+	return 0;
+}
+
+static int proc_get_chplan_test(struct seq_file *m, void *v)
+{
+	dump_chplan_test(m);
+	return 0;
+}
+
+static int proc_get_chplan_ver(struct seq_file *m, void *v)
+{
+	dump_chplan_ver(m);
+	return 0;
+}
+
+#ifdef RTW_HALMAC
+extern void rtw_halmac_get_version(char *str, u32 len);
+
+static int proc_get_halmac_info(struct seq_file *m, void *v)
+{
+	char ver[30] = {0};
+
+
+	rtw_halmac_get_version(ver, 30);
+	RTW_PRINT_SEL(m, "version: %s\n", ver);
+
+	return 0;
+}
+#endif
+
+/*
+* rtw_drv_proc:
+* init/deinit when register/unregister driver
+*/
+const struct rtw_proc_hdl drv_proc_hdls[] = {
+	RTW_PROC_HDL_SSEQ("ver_info", proc_get_drv_version, NULL),
+	RTW_PROC_HDL_SSEQ("log_level", proc_get_log_level, proc_set_log_level),
+	RTW_PROC_HDL_SSEQ("drv_cfg", proc_get_drv_cfg, NULL),
+#ifdef DBG_MEM_ALLOC
+	RTW_PROC_HDL_SSEQ("mstat", proc_get_mstat, NULL),
+#endif /* DBG_MEM_ALLOC */
+	RTW_PROC_HDL_SSEQ("country_chplan_map", proc_get_country_chplan_map, NULL),
+	RTW_PROC_HDL_SSEQ("chplan_id_list", proc_get_chplan_id_list, NULL),
+	RTW_PROC_HDL_SSEQ("chplan_test", proc_get_chplan_test, NULL),
+	RTW_PROC_HDL_SSEQ("chplan_ver", proc_get_chplan_ver, NULL),
+#ifdef RTW_HALMAC
+	RTW_PROC_HDL_SSEQ("halmac_info", proc_get_halmac_info, NULL),
+#endif /* RTW_HALMAC */
+};
+
+const int drv_proc_hdls_num = sizeof(drv_proc_hdls) / sizeof(struct rtw_proc_hdl);
+
+static int rtw_drv_proc_open(struct inode *inode, struct file *file)
+{
+	/* struct net_device *dev = proc_get_parent_data(inode); */
+	ssize_t index = (ssize_t)PDE_DATA(inode);
+	const struct rtw_proc_hdl *hdl = drv_proc_hdls + index;
+	void *private = NULL;
+
+	if (hdl->type == RTW_PROC_HDL_TYPE_SEQ) {
+		int res = seq_open(file, hdl->u.seq_op);
+
+		if (res == 0)
+			((struct seq_file *)file->private_data)->private = private;
+
+		return res;
+	} else if (hdl->type == RTW_PROC_HDL_TYPE_SSEQ) {
+		int (*show)(struct seq_file *, void *) = hdl->u.show ? hdl->u.show : proc_get_dummy;
+
+		return single_open(file, show, private);
+	} else {
+		return -EROFS;
+	}
+}
+
+static ssize_t rtw_drv_proc_write(struct file *file, const char __user *buffer, size_t count, loff_t *pos)
+{
+	ssize_t index = (ssize_t)PDE_DATA(file_inode(file));
+	const struct rtw_proc_hdl *hdl = drv_proc_hdls + index;
+	ssize_t (*write)(struct file *, const char __user *, size_t, loff_t *, void *) = hdl->write;
+
+	if (write)
+		return write(file, buffer, count, pos, NULL);
+
+	return -EROFS;
+}
+
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 6, 0))
+static const struct file_operations rtw_drv_proc_seq_fops = {
+	.owner = THIS_MODULE,
+	.open = rtw_drv_proc_open,
+	.read = seq_read,
+	.llseek = seq_lseek,
+	.release = seq_release,
+	.write = rtw_drv_proc_write,
+};
+
+static const struct file_operations rtw_drv_proc_sseq_fops = {
+	.owner = THIS_MODULE,
+	.open = rtw_drv_proc_open,
+	.read = seq_read,
+	.llseek = seq_lseek,
+	.release = single_release,
+	.write = rtw_drv_proc_write,
+};
+#else
+static const struct proc_ops rtw_drv_proc_seq_fops = {
+	.proc_open = rtw_drv_proc_open,
+	.proc_read = seq_read,
+	.proc_lseek = seq_lseek,
+	.proc_release = seq_release,
+	.proc_write = rtw_drv_proc_write,
+};
+
+static const struct proc_ops rtw_drv_proc_sseq_fops = {
+	.proc_open = rtw_drv_proc_open,
+	.proc_read = seq_read,
+	.proc_lseek = seq_lseek,
+	.proc_release = single_release,
+	.proc_write = rtw_drv_proc_write,
+};
+#endif
+
+int rtw_drv_proc_init(void)
+{
+	int ret = _FAIL;
+	ssize_t i;
+	struct proc_dir_entry *entry = NULL;
+
+	if (rtw_proc != NULL) {
+		rtw_warn_on(1);
+		goto exit;
+	}
+
+	rtw_proc = rtw_proc_create_dir(RTW_PROC_NAME, get_proc_net, NULL);
+
+	if (rtw_proc == NULL) {
+		rtw_warn_on(1);
+		goto exit;
+	}
+
+	for (i = 0; i < drv_proc_hdls_num; i++) {
+		if (drv_proc_hdls[i].type == RTW_PROC_HDL_TYPE_SEQ)
+			entry = rtw_proc_create_entry(drv_proc_hdls[i].name, rtw_proc, &rtw_drv_proc_seq_fops, (void *)i);
+		else if (drv_proc_hdls[i].type == RTW_PROC_HDL_TYPE_SSEQ)
+			entry = rtw_proc_create_entry(drv_proc_hdls[i].name, rtw_proc, &rtw_drv_proc_sseq_fops, (void *)i);
+		else
+			entry = NULL;
+
+		if (!entry) {
+			rtw_warn_on(1);
+			goto exit;
+		}
+	}
+
+	ret = _SUCCESS;
+
+exit:
+	return ret;
+}
+
+void rtw_drv_proc_deinit(void)
+{
+	int i;
+
+	if (rtw_proc == NULL)
+		return;
+
+	for (i = 0; i < drv_proc_hdls_num; i++)
+		remove_proc_entry(drv_proc_hdls[i].name, rtw_proc);
+
+	remove_proc_entry(RTW_PROC_NAME, get_proc_net);
+	rtw_proc = NULL;
+}
+
+#ifndef RTW_SEQ_FILE_TEST
+#define RTW_SEQ_FILE_TEST 0
+#endif
+
+#if RTW_SEQ_FILE_TEST
+#define RTW_SEQ_FILE_TEST_SHOW_LIMIT 300
+static void *proc_start_seq_file_test(struct seq_file *m, loff_t *pos)
+{
+	struct net_device *dev = m->private;
+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
+
+	RTW_PRINT(FUNC_ADPT_FMT"\n", FUNC_ADPT_ARG(adapter));
+	if (*pos >= RTW_SEQ_FILE_TEST_SHOW_LIMIT) {
+		RTW_PRINT(FUNC_ADPT_FMT" pos:%llu, out of range return\n", FUNC_ADPT_ARG(adapter), *pos);
+		return NULL;
+	}
+
+	RTW_PRINT(FUNC_ADPT_FMT" return pos:%lld\n", FUNC_ADPT_ARG(adapter), *pos);
+	return pos;
+}
+void proc_stop_seq_file_test(struct seq_file *m, void *v)
+{
+	struct net_device *dev = m->private;
+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
+
+	RTW_PRINT(FUNC_ADPT_FMT"\n", FUNC_ADPT_ARG(adapter));
+}
+
+void *proc_next_seq_file_test(struct seq_file *m, void *v, loff_t *pos)
+{
+	struct net_device *dev = m->private;
+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
+
+	(*pos)++;
+	if (*pos >= RTW_SEQ_FILE_TEST_SHOW_LIMIT) {
+		RTW_PRINT(FUNC_ADPT_FMT" pos:%lld, out of range return\n", FUNC_ADPT_ARG(adapter), *pos);
+		return NULL;
+	}
+
+	RTW_PRINT(FUNC_ADPT_FMT" return pos:%lld\n", FUNC_ADPT_ARG(adapter), *pos);
+	return pos;
+}
+
+static int proc_get_seq_file_test(struct seq_file *m, void *v)
+{
+	struct net_device *dev = m->private;
+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
+
+	u32 pos = *((loff_t *)(v));
+	RTW_PRINT(FUNC_ADPT_FMT" pos:%d\n", FUNC_ADPT_ARG(adapter), pos);
+	RTW_PRINT_SEL(m, FUNC_ADPT_FMT" pos:%d\n", FUNC_ADPT_ARG(adapter), pos);
+	return 0;
+}
+
+struct seq_operations seq_file_test = {
+	.start = proc_start_seq_file_test,
+	.stop  = proc_stop_seq_file_test,
+	.next  = proc_next_seq_file_test,
+	.show  = proc_get_seq_file_test,
+};
+#endif /* RTW_SEQ_FILE_TEST */
+
+#ifdef CONFIG_SDIO_HCI
+static int proc_get_sd_f0_reg_dump(struct seq_file *m, void *v)
+{
+	struct net_device *dev = m->private;
+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
+
+	sd_f0_reg_dump(m, adapter);
+
+	return 0;
+}
+
+static int proc_get_sdio_local_reg_dump(struct seq_file *m, void *v)
+{
+	struct net_device *dev = m->private;
+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
+
+	sdio_local_reg_dump(m, adapter);
+
+	return 0;
+}
+static int proc_get_sdio_card_info(struct seq_file *m, void *v)
+{
+	struct net_device *dev = m->private;
+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
+
+	dump_sdio_card_info(m, adapter_to_dvobj(adapter));
+
+	return 0;
+}
+#endif /* CONFIG_SDIO_HCI */
+
+static int proc_get_fw_info(struct seq_file *m, void *v)
+{
+	struct net_device *dev = m->private;
+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
+
+	rtw_dump_fw_info(m, adapter);
+	return 0;
+}
+static int proc_get_mac_reg_dump(struct seq_file *m, void *v)
+{
+	struct net_device *dev = m->private;
+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
+
+	mac_reg_dump(m, adapter);
+
+	return 0;
+}
+
+static int proc_get_bb_reg_dump(struct seq_file *m, void *v)
+{
+	struct net_device *dev = m->private;
+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
+
+	bb_reg_dump(m, adapter);
+
+	return 0;
+}
+
+static int proc_get_bb_reg_dump_ex(struct seq_file *m, void *v)
+{
+	struct net_device *dev = m->private;
+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
+
+	bb_reg_dump_ex(m, adapter);
+
+	return 0;
+}
+
+static int proc_get_rf_reg_dump(struct seq_file *m, void *v)
+{
+	struct net_device *dev = m->private;
+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
+
+	rf_reg_dump(m, adapter);
+
+	return 0;
+}
+
+#ifdef CONFIG_RTW_LED
+int proc_get_led_config(struct seq_file *m, void *v)
+{
+	struct net_device *dev = m->private;
+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
+
+	dump_led_config(m, adapter);
+
+	return 0;
+}
+
+ssize_t proc_set_led_config(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
+{
+	struct net_device *dev = data;
+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
+
+	char tmp[32];
+	u8 strategy;
+	u8 iface_en_mask;
+
+	if (count < 1)
+		return -EFAULT;
+
+	if (count > sizeof(tmp)) {
+		rtw_warn_on(1);
+		return -EFAULT;
+	}
+
+	if (buffer && !copy_from_user(tmp, buffer, count)) {
+
+		int num = sscanf(tmp, "%hhu %hhx", &strategy, &iface_en_mask);
+
+		if (num >= 1)
+			rtw_led_set_strategy(adapter, strategy);
+		if (num >= 2)
+			rtw_led_set_iface_en_mask(adapter, iface_en_mask);
+	}
+
+	return count;
+}
+#endif /* CONFIG_RTW_LED */
+
+#ifdef CONFIG_AP_MODE
+int proc_get_aid_status(struct seq_file *m, void *v)
+{
+	struct net_device *dev = m->private;
+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
+
+	dump_aid_status(m, adapter);
+
+	return 0;
+}
+
+ssize_t proc_set_aid_status(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
+{
+	struct net_device *dev = data;
+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
+	struct sta_priv *stapriv = &adapter->stapriv;
+
+	char tmp[32];
+	u8 rr;
+	u16 started_aid;
+
+	if (count < 1)
+		return -EFAULT;
+
+	if (count > sizeof(tmp)) {
+		rtw_warn_on(1);
+		return -EFAULT;
+	}
+
+	if (buffer && !copy_from_user(tmp, buffer, count)) {
+
+		int num = sscanf(tmp, "%hhu %hu", &rr, &started_aid);
+
+		if (num >= 1)
+			stapriv->rr_aid = rr ? 1 : 0;
+		if (num >= 2) {
+			started_aid = started_aid % (stapriv->max_aid + 1);
+			stapriv->started_aid = started_aid ? started_aid : 1;
+		}
+	}
+
+	return count;
+}
+#endif /* CONFIG_AP_MODE */
+
+static int proc_get_dump_tx_rate_bmp(struct seq_file *m, void *v)
+{
+	struct net_device *dev = m->private;
+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
+
+	dump_tx_rate_bmp(m, adapter_to_dvobj(adapter));
+
+	return 0;
+}
+
+static int proc_get_dump_adapters_status(struct seq_file *m, void *v)
+{
+	struct net_device *dev = m->private;
+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
+
+	dump_adapters_status(m, adapter_to_dvobj(adapter));
+
+	return 0;
+}
+
+#ifdef CONFIG_RTW_CUSTOMER_STR
+static int proc_get_customer_str(struct seq_file *m, void *v)
+{
+	struct net_device *dev = m->private;
+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
+	u8 cstr[RTW_CUSTOMER_STR_LEN];
+
+	rtw_ps_deny(adapter, PS_DENY_IOCTL);
+	if (rtw_pwr_wakeup(adapter) == _FAIL)
+		goto exit;
+
+	if (rtw_hal_customer_str_read(adapter, cstr) != _SUCCESS)
+		goto exit;
+
+	RTW_PRINT_SEL(m, RTW_CUSTOMER_STR_FMT"\n", RTW_CUSTOMER_STR_ARG(cstr));
+
+exit:
+	rtw_ps_deny_cancel(adapter, PS_DENY_IOCTL);
+	return 0;
+}
+#endif /* CONFIG_RTW_CUSTOMER_STR */
+
+#ifdef CONFIG_SCAN_BACKOP
+static int proc_get_backop_flags_sta(struct seq_file *m, void *v)
+{
+	struct net_device *dev = m->private;
+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
+	struct mlme_ext_priv *mlmeext = &adapter->mlmeextpriv;
+
+	RTW_PRINT_SEL(m, "0x%02x\n", mlmeext_scan_backop_flags_sta(mlmeext));
+
+	return 0;
+}
+
+static ssize_t proc_set_backop_flags_sta(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
+{
+	struct net_device *dev = data;
+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
+	struct mlme_ext_priv *mlmeext = &adapter->mlmeextpriv;
+
+	char tmp[32];
+	u8 flags;
+
+	if (count < 1)
+		return -EFAULT;
+
+	if (count > sizeof(tmp)) {
+		rtw_warn_on(1);
+		return -EFAULT;
+	}
+
+	if (buffer && !copy_from_user(tmp, buffer, count)) {
+
+		int num = sscanf(tmp, "%hhx", &flags);
+
+		if (num == 1)
+			mlmeext_assign_scan_backop_flags_sta(mlmeext, flags);
+	}
+
+	return count;
+}
+
+#ifdef CONFIG_AP_MODE
+static int proc_get_backop_flags_ap(struct seq_file *m, void *v)
+{
+	struct net_device *dev = m->private;
+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
+	struct mlme_ext_priv *mlmeext = &adapter->mlmeextpriv;
+
+	RTW_PRINT_SEL(m, "0x%02x\n", mlmeext_scan_backop_flags_ap(mlmeext));
+
+	return 0;
+}
+
+static ssize_t proc_set_backop_flags_ap(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
+{
+	struct net_device *dev = data;
+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
+	struct mlme_ext_priv *mlmeext = &adapter->mlmeextpriv;
+
+	char tmp[32];
+	u8 flags;
+
+	if (count < 1)
+		return -EFAULT;
+
+	if (count > sizeof(tmp)) {
+		rtw_warn_on(1);
+		return -EFAULT;
+	}
+
+	if (buffer && !copy_from_user(tmp, buffer, count)) {
+
+		int num = sscanf(tmp, "%hhx", &flags);
+
+		if (num == 1)
+			mlmeext_assign_scan_backop_flags_ap(mlmeext, flags);
+	}
+
+	return count;
+}
+#endif /* CONFIG_AP_MODE */
+
+#ifdef CONFIG_RTW_MESH
+static int proc_get_backop_flags_mesh(struct seq_file *m, void *v)
+{
+	struct net_device *dev = m->private;
+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
+	struct mlme_ext_priv *mlmeext = &adapter->mlmeextpriv;
+
+	RTW_PRINT_SEL(m, "0x%02x\n", mlmeext_scan_backop_flags_mesh(mlmeext));
+
+	return 0;
+}
+
+static ssize_t proc_set_backop_flags_mesh(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
+{
+	struct net_device *dev = data;
+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
+	struct mlme_ext_priv *mlmeext = &adapter->mlmeextpriv;
+
+	char tmp[32];
+	u8 flags;
+
+	if (count < 1)
+		return -EFAULT;
+
+	if (count > sizeof(tmp)) {
+		rtw_warn_on(1);
+		return -EFAULT;
+	}
+
+	if (buffer && !copy_from_user(tmp, buffer, count)) {
+
+		int num = sscanf(tmp, "%hhx", &flags);
+
+		if (num == 1)
+			mlmeext_assign_scan_backop_flags_mesh(mlmeext, flags);
+	}
+
+	return count;
+}
+#endif /* CONFIG_RTW_MESH */
+
+#endif /* CONFIG_SCAN_BACKOP */
+
+/* gpio setting */
+#ifdef CONFIG_GPIO_API
+static ssize_t proc_set_config_gpio(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
+{
+	struct net_device *dev = data;
+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
+	char tmp[32] = {0};
+	int num = 0, gpio_pin = 0, gpio_mode = 0; /* gpio_mode:0 input  1:output; */
+
+	if (count < 2)
+		return -EFAULT;
+
+	if (count > sizeof(tmp)) {
+		rtw_warn_on(1);
+		return -EFAULT;
+	}
+
+	if (buffer && !copy_from_user(tmp, buffer, count)) {
+		num	= sscanf(tmp, "%d %d", &gpio_pin, &gpio_mode);
+		RTW_INFO("num=%d gpio_pin=%d mode=%d\n", num, gpio_pin, gpio_mode);
+		padapter->pre_gpio_pin = gpio_pin;
+
+		if (gpio_mode == 0 || gpio_mode == 1)
+			rtw_hal_config_gpio(padapter, gpio_pin, gpio_mode);
+	}
+	return count;
+
+}
+static ssize_t proc_set_gpio_output_value(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
+{
+	struct net_device *dev = data;
+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
+	char tmp[32] = {0};
+	int num = 0, gpio_pin = 0, pin_mode = 0; /* pin_mode: 1 high         0:low */
+
+	if (count < 2)
+		return -EFAULT;
+
+	if (count > sizeof(tmp)) {
+		rtw_warn_on(1);
+		return -EFAULT;
+	}
+
+	if (buffer && !copy_from_user(tmp, buffer, count)) {
+		num	= sscanf(tmp, "%d %d", &gpio_pin, &pin_mode);
+		RTW_INFO("num=%d gpio_pin=%d pin_high=%d\n", num, gpio_pin, pin_mode);
+		padapter->pre_gpio_pin = gpio_pin;
+
+		if (pin_mode == 0 || pin_mode == 1)
+			rtw_hal_set_gpio_output_value(padapter, gpio_pin, pin_mode);
+	}
+	return count;
+}
+static int proc_get_gpio(struct seq_file *m, void *v)
+{
+	u8 gpioreturnvalue = 0;
+	struct net_device *dev = m->private;
+
+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
+	if (!padapter)
+		return -EFAULT;
+	gpioreturnvalue = rtw_hal_get_gpio(padapter, padapter->pre_gpio_pin);
+	RTW_PRINT_SEL(m, "get_gpio %d:%d\n", padapter->pre_gpio_pin, gpioreturnvalue);
+
+	return 0;
+
+}
+static ssize_t proc_set_gpio(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
+{
+	struct net_device *dev = data;
+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
+	char tmp[32] = {0};
+	int num = 0, gpio_pin = 0;
+
+	if (count < 1)
+		return -EFAULT;
+
+	if (count > sizeof(tmp)) {
+		rtw_warn_on(1);
+		return -EFAULT;
+	}
+
+	if (buffer && !copy_from_user(tmp, buffer, count)) {
+		num	= sscanf(tmp, "%d", &gpio_pin);
+		RTW_INFO("num=%d gpio_pin=%d\n", num, gpio_pin);
+		padapter->pre_gpio_pin = gpio_pin;
+
+	}
+	return count;
+}
+#endif
+
+static ssize_t proc_set_rx_info_msg(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
+{
+
+	struct net_device *dev = data;
+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
+	struct recv_priv *precvpriv = &(padapter->recvpriv);
+	char tmp[32] = {0};
+	int phy_info_flag = 0;
+
+	if (!padapter)
+		return -EFAULT;
+
+	if (count < 1) {
+		RTW_INFO("argument size is less than 1\n");
+		return -EFAULT;
+	}
+
+	if (count > sizeof(tmp)) {
+		rtw_warn_on(1);
+		return -EFAULT;
+	}
+
+	if (buffer && !copy_from_user(tmp, buffer, count)) {
+		int num = sscanf(tmp, "%d", &phy_info_flag);
+
+		if (num == 1)
+			precvpriv->store_law_data_flag = (BOOLEAN) phy_info_flag;
+
+		/*RTW_INFO("precvpriv->store_law_data_flag = %d\n",( BOOLEAN )(precvpriv->store_law_data_flag));*/
+	}
+	return count;
+}
+static int proc_get_rx_info_msg(struct seq_file *m, void *v)
+{
+	struct net_device *dev = m->private;
+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
+
+	rtw_hal_set_odm_var(padapter, HAL_ODM_RX_Dframe_INFO, m, _FALSE);
+	return 0;
+}
+static int proc_get_tx_info_msg(struct seq_file *m, void *v)
+{
+	_irqL irqL;
+	struct net_device *dev = m->private;
+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
+	struct sta_info *psta;
+	u8 bc_addr[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
+	u8 null_addr[ETH_ALEN] = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00};
+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
+	struct sta_priv *pstapriv = &padapter->stapriv;
+	int i;
+	_list	*plist, *phead;
+	u8 current_rate_id = 0, current_sgi = 0;
+
+	char *BW, *status;
+
+	_enter_critical_bh(&pstapriv->sta_hash_lock, &irqL);
+
+	if (MLME_IS_STA(padapter))
+		status = "station mode";
+	else if (MLME_IS_AP(padapter))
+		status = "AP mode";
+	else if (MLME_IS_MESH(padapter))
+		status = "mesh mode";
+	else
+		status = " ";
+	_RTW_PRINT_SEL(m, "status=%s\n", status);
+	for (i = 0; i < NUM_STA; i++) {
+		phead = &(pstapriv->sta_hash[i]);
+		plist = get_next(phead);
+
+		while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) {
+
+			psta = LIST_CONTAINOR(plist, struct sta_info, hash_list);
+
+			plist = get_next(plist);
+
+			if ((_rtw_memcmp(psta->cmn.mac_addr, bc_addr, ETH_ALEN)  !=  _TRUE)
+				&& (_rtw_memcmp(psta->cmn.mac_addr, null_addr, ETH_ALEN) != _TRUE)
+				&& (_rtw_memcmp(psta->cmn.mac_addr, adapter_mac_addr(padapter), ETH_ALEN) != _TRUE)) {
+
+				switch (psta->cmn.bw_mode) {
+
+				case CHANNEL_WIDTH_20:
+					BW = "20M";
+					break;
+
+				case CHANNEL_WIDTH_40:
+					BW = "40M";
+					break;
+
+				case CHANNEL_WIDTH_80:
+					BW = "80M";
+					break;
+
+				case CHANNEL_WIDTH_160:
+					BW = "160M";
+					break;
+
+				default:
+					BW = "";
+					break;
+				}
+				current_rate_id = rtw_get_current_tx_rate(adapter, psta);
+				current_sgi = rtw_get_current_tx_sgi(adapter, psta);
+
+				RTW_PRINT_SEL(m, "==============================\n");
+				_RTW_PRINT_SEL(m, "macaddr=" MAC_FMT"\n", MAC_ARG(psta->cmn.mac_addr));
+				_RTW_PRINT_SEL(m, "Tx_Data_Rate=%s\n", HDATA_RATE(current_rate_id));
+				_RTW_PRINT_SEL(m, "BW=%s,sgi=%u\n", BW, current_sgi);
+
+			}
+		}
+	}
+
+	_exit_critical_bh(&pstapriv->sta_hash_lock, &irqL);
+
+	return 0;
+
+}
+
+
+static int proc_get_linked_info_dump(struct seq_file *m, void *v)
+{
+	struct net_device *dev = m->private;
+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
+	if (padapter)
+		RTW_PRINT_SEL(m, "linked_info_dump :%s\n", (padapter->bLinkInfoDump) ? "enable" : "disable");
+
+	return 0;
+}
+
+
+static ssize_t proc_set_linked_info_dump(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
+{
+	struct net_device *dev = data;
+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
+
+	char tmp[32] = {0};
+	int mode = 0, pre_mode = 0;
+	int num = 0;
+
+	if (count < 1)
+		return -EFAULT;
+
+	if (count > sizeof(tmp)) {
+		rtw_warn_on(1);
+		return -EFAULT;
+	}
+
+	pre_mode = padapter->bLinkInfoDump;
+	RTW_INFO("pre_mode=%d\n", pre_mode);
+
+	if (buffer && !copy_from_user(tmp, buffer, count)) {
+
+		num	= sscanf(tmp, "%d ", &mode);
+		RTW_INFO("num=%d mode=%d\n", num, mode);
+
+		if (num != 1) {
+			RTW_INFO("argument number is wrong\n");
+			return -EFAULT;
+		}
+
+		if (mode == 1 || (mode == 0 && pre_mode == 1)) /* not consider pwr_saving 0: */
+			padapter->bLinkInfoDump = mode;
+
+		else if ((mode == 2) || (mode == 0 && pre_mode == 2)) { /* consider power_saving */
+			/* RTW_INFO("linked_info_dump =%s\n", (padapter->bLinkInfoDump)?"enable":"disable") */
+			linked_info_dump(padapter, mode);
+		}
+	}
+	return count;
+}
+
+
+static int proc_get_sta_tp_dump(struct seq_file *m, void *v)
+{
+	struct net_device *dev = m->private;
+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
+
+	if (padapter)
+		RTW_PRINT_SEL(m, "sta_tp_dump :%s\n", (padapter->bsta_tp_dump) ? "enable" : "disable");
+
+	return 0;
+}
+
+static ssize_t proc_set_sta_tp_dump(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
+{
+	struct net_device *dev = data;
+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
+
+	char tmp[32] = {0};
+	int mode = 0;
+	int num = 0;
+
+	if (count < 1)
+		return -EFAULT;
+
+	if (count > sizeof(tmp)) {
+		rtw_warn_on(1);
+		return -EFAULT;
+	}
+
+	if (buffer && !copy_from_user(tmp, buffer, count)) {
+
+		num	= sscanf(tmp, "%d ", &mode);
+
+		if (num != 1) {
+			RTW_INFO("argument number is wrong\n");
+			return -EFAULT;
+		}
+		if (padapter)
+			padapter->bsta_tp_dump = mode;
+	}
+	return count;
+}
+
+static int proc_get_sta_tp_info(struct seq_file *m, void *v)
+{
+	struct net_device *dev = m->private;
+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
+
+	if (padapter)
+		rtw_sta_traffic_info(m, padapter);
+
+	return 0;
+}
+
+static int proc_get_turboedca_ctrl(struct seq_file *m, void *v)
+{
+	struct net_device *dev = m->private;
+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
+	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(padapter);
+
+	if (hal_data)
+		RTW_PRINT_SEL(m, "Turbo-EDCA :%s\n", (hal_data->dis_turboedca) ? "Disable" : "Enable");
+
+	return 0;
+}
+
+static ssize_t proc_set_turboedca_ctrl(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
+{
+	struct net_device *dev = data;
+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
+	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(padapter);
+
+	char tmp[32] = {0};
+	int mode = 0, num = 0;
+
+	if (count < 1)
+		return -EFAULT;
+
+	if (count > sizeof(tmp))
+		return -EFAULT;
+
+	if (buffer && !copy_from_user(tmp, buffer, count)) {
+
+		num	= sscanf(tmp, "%d ", &mode);
+
+		if (num != 1) {
+			RTW_INFO("argument number is wrong\n");
+			return -EFAULT;
+		}
+		hal_data->dis_turboedca = mode;
+	}
+	return count;
+}
+#ifdef CONFIG_WOWLAN
+static int proc_get_wow_lps_ctrl(struct seq_file *m, void *v)
+{
+	struct net_device *dev = m->private;
+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
+	struct pwrctrl_priv *pwrctl = adapter_to_pwrctl(padapter);
+
+	if (pwrctl)
+		RTW_PRINT_SEL(m, "WOW lps :%s\n", (pwrctl->wowlan_dis_lps) ? "Disable" : "Enable");
+
+	return 0;
+}
+
+static ssize_t proc_set_wow_lps_ctrl(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
+{
+	struct net_device *dev = data;
+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
+	struct pwrctrl_priv *pwrctl = adapter_to_pwrctl(padapter);
+
+	char tmp[32] = {0};
+	int mode = 0, num = 0;
+
+	if (count < 1)
+		return -EFAULT;
+
+	if (count > sizeof(tmp))
+		return -EFAULT;
+
+	if (buffer && !copy_from_user(tmp, buffer, count)) {
+
+		num	= sscanf(tmp, "%d ", &mode);
+
+		if (num != 1) {
+			RTW_INFO("argument number is wrong\n");
+			return -EFAULT;
+		}
+		pwrctl->wowlan_dis_lps = mode;
+		RTW_INFO("WOW lps :%s\n", (pwrctl->wowlan_dis_lps) ? "Disable" : "Enable");
+	}
+	return count;
+}
+#endif
+
+static int proc_get_mac_qinfo(struct seq_file *m, void *v)
+{
+	struct net_device *dev = m->private;
+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
+
+	rtw_hal_get_hwreg(adapter, HW_VAR_DUMP_MAC_QUEUE_INFO, (u8 *)m);
+
+	return 0;
+}
+
+int proc_get_wifi_spec(struct seq_file *m, void *v)
+{
+	struct net_device *dev = m->private;
+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
+	struct registry_priv	*pregpriv = &padapter->registrypriv;
+
+	RTW_PRINT_SEL(m, "wifi_spec=%d\n", pregpriv->wifi_spec);
+	return 0;
+}
+
+static int proc_get_chan_plan(struct seq_file *m, void *v)
+{
+	struct net_device *dev = m->private;
+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
+
+	dump_cur_chset(m, adapter_to_rfctl(adapter));
+
+	return 0;
+}
+
+static ssize_t proc_set_chan_plan(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
+{
+	struct net_device *dev = data;
+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
+	char tmp[32];
+	u8 chan_plan = RTW_CHPLAN_UNSPECIFIED;
+
+	if (!padapter)
+		return -EFAULT;
+
+	if (count < 1) {
+		RTW_INFO("argument size is less than 1\n");
+		return -EFAULT;
+	}
+
+	if (count > sizeof(tmp)) {
+		rtw_warn_on(1);
+		return -EFAULT;
+	}
+
+	if (buffer && !copy_from_user(tmp, buffer, count)) {
+		int num = sscanf(tmp, "%hhx", &chan_plan);
+		if (num !=  1)
+			return count;
+	}
+
+	rtw_set_channel_plan(padapter, chan_plan);
+
+	return count;
+}
+
+static int proc_get_country_code(struct seq_file *m, void *v)
+{
+	struct net_device *dev = m->private;
+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
+	struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter);
+
+	if (rfctl->country_ent)
+		dump_country_chplan(m, rfctl->country_ent);
+	else
+		RTW_PRINT_SEL(m, "unspecified\n");
+
+	return 0;
+}
+
+static ssize_t proc_set_country_code(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
+{
+	struct net_device *dev = data;
+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
+	char tmp[32];
+	char alpha2[2];
+	int num;
+
+	if (count < 1)
+		return -EFAULT;
+
+	if (count > sizeof(tmp)) {
+		rtw_warn_on(1);
+		return -EFAULT;
+	}
+
+	if (!buffer || copy_from_user(tmp, buffer, count))
+		goto exit;
+
+	num = sscanf(tmp, "%c%c", &alpha2[0], &alpha2[1]);
+	if (num !=	2)
+		return count;
+
+	rtw_set_country(padapter, alpha2);
+
+exit:
+	return count;
+}
+
+#if CONFIG_RTW_MACADDR_ACL
+static int proc_get_macaddr_acl(struct seq_file *m, void *v)
+{
+	struct net_device *dev = m->private;
+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
+
+	dump_macaddr_acl(m, adapter);
+	return 0;
+}
+
+ssize_t proc_set_macaddr_acl(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
+{
+	struct net_device *dev = data;
+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
+	char tmp[17 * NUM_ACL + 32] = {0};
+	u8 period;
+	char cmd[32];
+	u8 mode;
+	u8 addr[ETH_ALEN];
+
+#define MAC_ACL_CMD_MODE	0
+#define MAC_ACL_CMD_ADD		1
+#define MAC_ACL_CMD_DEL		2
+#define MAC_ACL_CMD_CLR		3
+#define MAC_ACL_CMD_NUM		4
+
+	static const char * const mac_acl_cmd_str[] = {
+		"mode",
+		"add",
+		"del",
+		"clr",
+	};
+	u8 cmd_id = MAC_ACL_CMD_NUM;
+
+	if (count < 1)
+		return -EFAULT;
+
+	if (count > sizeof(tmp)) {
+		rtw_warn_on(1);
+		return -EFAULT;
+	}
+
+	if (buffer && !copy_from_user(tmp, buffer, count)) {
+		/*
+		* <period> mode <mode> <macaddr> [<macaddr>]
+		* <period> mode <mode>
+		* <period> add <macaddr> [<macaddr>]
+		* <period> del <macaddr> [<macaddr>]
+		* <period> clr
+		*/
+		char *c, *next;
+		int i;
+		u8 is_bcast;
+
+		next = tmp;
+		c = strsep(&next, " \t");
+		if (!c || sscanf(c, "%hhu", &period) != 1)
+			goto exit;
+
+		if (period >= RTW_ACL_PERIOD_NUM) {
+			RTW_WARN(FUNC_ADPT_FMT" invalid period:%u", FUNC_ADPT_ARG(adapter), period);
+			goto exit;
+		}
+
+		c = strsep(&next, " \t");
+		if (!c || sscanf(c, "%s", cmd) != 1)
+			goto exit;
+
+		for (i = 0; i < MAC_ACL_CMD_NUM; i++)
+			if (strcmp(mac_acl_cmd_str[i], cmd) == 0)
+				cmd_id = i;
+
+		switch (cmd_id) {
+		case MAC_ACL_CMD_MODE:
+			c = strsep(&next, " \t");
+			if (!c || sscanf(c, "%hhu", &mode) != 1)
+				goto exit;
+
+			if (mode >= RTW_ACL_MODE_MAX) {
+				RTW_WARN(FUNC_ADPT_FMT" invalid mode:%u", FUNC_ADPT_ARG(adapter), mode);
+				goto exit;
+			}
+			break;
+
+		case MAC_ACL_CMD_ADD:
+		case MAC_ACL_CMD_DEL:
+			break;
+
+		case MAC_ACL_CMD_CLR:
+			/* clear settings */
+			rtw_macaddr_acl_clear(adapter, period);
+			goto exit;
+
+		default:
+			RTW_WARN(FUNC_ADPT_FMT" invalid cmd:\"%s\"", FUNC_ADPT_ARG(adapter), cmd);
+			goto exit;
+		}
+
+		/* check for macaddr list */
+		c = strsep(&next, " \t");
+		if (!c && cmd_id == MAC_ACL_CMD_MODE) {
+			/* set mode only  */
+			rtw_set_macaddr_acl(adapter, period, mode);
+			goto exit;
+		}
+
+		if (cmd_id == MAC_ACL_CMD_MODE) {
+			/* set mode and entire macaddr list */
+			rtw_macaddr_acl_clear(adapter, period);
+			rtw_set_macaddr_acl(adapter, period, mode);
+		}
+
+		while (c != NULL) {
+			if (sscanf(c, MAC_SFMT, MAC_SARG(addr)) != 6)
+				break;
+
+			is_bcast = is_broadcast_mac_addr(addr);
+			if (is_bcast
+				|| rtw_check_invalid_mac_address(addr, 0) == _FALSE
+			) {
+				if (cmd_id == MAC_ACL_CMD_DEL) {
+					rtw_acl_remove_sta(adapter, period, addr);
+					if (is_bcast)
+						break;
+				 } else if (!is_bcast)
+					rtw_acl_add_sta(adapter, period, addr);
+			}
+
+			c = strsep(&next, " \t");
+		}
+	}
+
+exit:
+	return count;
+}
+#endif /* CONFIG_RTW_MACADDR_ACL */
+
+#if CONFIG_RTW_PRE_LINK_STA
+static int proc_get_pre_link_sta(struct seq_file *m, void *v)
+{
+	struct net_device *dev = m->private;
+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
+
+	dump_pre_link_sta_ctl(m, &adapter->stapriv);
+	return 0;
+}
+
+ssize_t proc_set_pre_link_sta(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
+{
+	struct net_device *dev = data;
+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
+	struct mlme_priv *mlme = &adapter->mlmepriv;
+	struct mlme_ext_priv *mlmeext = &adapter->mlmeextpriv;
+	char tmp[17 * RTW_PRE_LINK_STA_NUM + 32] = {0};
+	char arg0[16] = {0};
+	u8 addr[ETH_ALEN];
+
+#define PRE_LINK_STA_CMD_RESET	0
+#define PRE_LINK_STA_CMD_ADD	1
+#define PRE_LINK_STA_CMD_DEL	2
+#define PRE_LINK_STA_CMD_NUM	3
+
+	static const char * const pre_link_sta_cmd_str[] = {
+		"reset",
+		"add",
+		"del"
+	};
+	u8 cmd_id = PRE_LINK_STA_CMD_NUM;
+
+	if (count < 1)
+		return -EFAULT;
+
+	if (count > sizeof(tmp)) {
+		rtw_warn_on(1);
+		return -EFAULT;
+	}
+
+	if (buffer && !copy_from_user(tmp, buffer, count)) {
+		/* cmd [<macaddr>] */
+		char *c, *next;
+		int i;
+
+		next = tmp;
+		c = strsep(&next, " \t");
+
+		if (sscanf(c, "%s", arg0) != 1)
+			goto exit;
+
+		for (i = 0; i < PRE_LINK_STA_CMD_NUM; i++)
+			if (strcmp(pre_link_sta_cmd_str[i], arg0) == 0)
+				cmd_id = i;
+
+		switch (cmd_id) {
+		case PRE_LINK_STA_CMD_RESET:
+			rtw_pre_link_sta_ctl_reset(&adapter->stapriv);
+			goto exit;
+		case PRE_LINK_STA_CMD_ADD:
+		case PRE_LINK_STA_CMD_DEL:
+			break;
+		default:
+			goto exit;
+		}
+
+		/* macaddr list */
+		c = strsep(&next, " \t");
+		while (c != NULL) {
+			if (sscanf(c, MAC_SFMT, MAC_SARG(addr)) != 6)
+				break;
+
+			if (rtw_check_invalid_mac_address(addr, 0) == _FALSE) {
+				if (cmd_id == PRE_LINK_STA_CMD_ADD)
+					rtw_pre_link_sta_add(&adapter->stapriv, addr);
+				else
+					rtw_pre_link_sta_del(&adapter->stapriv, addr);
+			}
+
+			c = strsep(&next, " \t");
+		}
+	}
+
+exit:
+	return count;
+}
+#endif /* CONFIG_RTW_PRE_LINK_STA */
+
+static int proc_get_ch_sel_policy(struct seq_file *m, void *v)
+{
+	struct net_device *dev = m->private;
+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
+	struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter);
+
+	RTW_PRINT_SEL(m, "%-16s\n", "same_band_prefer");
+
+	RTW_PRINT_SEL(m, "%16u\n", rfctl->ch_sel_same_band_prefer);
+
+	return 0;
+}
+
+static ssize_t proc_set_ch_sel_policy(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
+{
+	struct net_device *dev = data;
+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
+	struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter);
+	char tmp[32];
+	u8 sb_prefer;
+	int num;
+
+	if (count < 1)
+		return -EFAULT;
+
+	if (count > sizeof(tmp)) {
+		rtw_warn_on(1);
+		return -EFAULT;
+	}
+
+	if (!buffer || copy_from_user(tmp, buffer, count))
+		goto exit;
+
+	num = sscanf(tmp, "%hhu", &sb_prefer);
+	if (num >=	1)
+		rfctl->ch_sel_same_band_prefer = sb_prefer;
+
+exit:
+	return count;
+}
+
+#ifdef CONFIG_DFS_MASTER
+static int proc_get_dfs_test_case(struct seq_file *m, void *v)
+{
+	struct net_device *dev = m->private;
+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
+	struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter);
+
+	RTW_PRINT_SEL(m, "%-24s %-19s\n", "radar_detect_trigger_non", "choose_dfs_ch_first");
+	RTW_PRINT_SEL(m, "%24hhu %19hhu\n"
+		, rfctl->dbg_dfs_radar_detect_trigger_non
+		, rfctl->dbg_dfs_choose_dfs_ch_first
+	);
+
+	return 0;
+}
+
+static ssize_t proc_set_dfs_test_case(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
+{
+	struct net_device *dev = data;
+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
+	struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter);
+	char tmp[32];
+	u8 radar_detect_trigger_non;
+	u8 choose_dfs_ch_first;
+
+	if (count < 1)
+		return -EFAULT;
+
+	if (count > sizeof(tmp)) {
+		rtw_warn_on(1);
+		return -EFAULT;
+	}
+
+	if (buffer && !copy_from_user(tmp, buffer, count)) {
+		int num = sscanf(tmp, "%hhu %hhu", &radar_detect_trigger_non, &choose_dfs_ch_first);
+
+		if (num >= 1)
+			rfctl->dbg_dfs_radar_detect_trigger_non = radar_detect_trigger_non;
+		if (num >= 2)
+			rfctl->dbg_dfs_choose_dfs_ch_first = choose_dfs_ch_first;
+	}
+
+	return count;
+}
+
+ssize_t proc_set_update_non_ocp(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
+{
+	struct net_device *dev = data;
+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
+	struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter);
+	char tmp[32];
+	u8 ch, bw = CHANNEL_WIDTH_20, offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
+	int ms = -1;
+
+	if (count < 1)
+		return -EFAULT;
+
+	if (count > sizeof(tmp)) {
+		rtw_warn_on(1);
+		return -EFAULT;
+	}
+
+	if (buffer && !copy_from_user(tmp, buffer, count)) {
+
+		int num = sscanf(tmp, "%hhu %hhu %hhu %d", &ch, &bw, &offset, &ms);
+
+		if (num < 1 || (bw != CHANNEL_WIDTH_20 && num < 3))
+			goto exit;
+
+		if (bw == CHANNEL_WIDTH_20)
+			rtw_chset_update_non_ocp_ms(rfctl->channel_set
+				, ch, bw, HAL_PRIME_CHNL_OFFSET_DONT_CARE, ms);
+		else
+			rtw_chset_update_non_ocp_ms(rfctl->channel_set
+				, ch, bw, offset, ms);
+	}
+
+exit:
+	return count;
+}
+
+ssize_t proc_set_radar_detect(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
+{
+	struct net_device *dev = data;
+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
+	struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter);
+	char tmp[32];
+	u8 fake_radar_detect_cnt = 0;
+
+	if (count < 1)
+		return -EFAULT;
+
+	if (count > sizeof(tmp)) {
+		rtw_warn_on(1);
+		return -EFAULT;
+	}
+
+	if (buffer && !copy_from_user(tmp, buffer, count)) {
+
+		int num = sscanf(tmp, "%hhu", &fake_radar_detect_cnt);
+
+		if (num < 1)
+			goto exit;
+
+		rfctl->dbg_dfs_fake_radar_detect_cnt = fake_radar_detect_cnt;
+	}
+
+exit:
+	return count;
+}
+
+static int proc_get_dfs_ch_sel_d_flags(struct seq_file *m, void *v)
+{
+	struct net_device *dev = m->private;
+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
+	struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter);
+
+	RTW_PRINT_SEL(m, "0x%02x\n", rfctl->dfs_ch_sel_d_flags);
+
+	return 0;
+}
+
+static ssize_t proc_set_dfs_ch_sel_d_flags(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
+{
+	struct net_device *dev = data;
+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
+	struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter);
+	char tmp[32];
+	u8 d_flags;
+	int num;
+
+	if (count < 1)
+		return -EFAULT;
+
+	if (count > sizeof(tmp)) {
+		rtw_warn_on(1);
+		return -EFAULT;
+	}
+
+	if (!buffer || copy_from_user(tmp, buffer, count))
+		goto exit;
+
+	num = sscanf(tmp, "%hhx", &d_flags);
+	if (num != 1)
+		goto exit;
+
+	rfctl->dfs_ch_sel_d_flags = d_flags;
+
+exit:
+	return count;
+}
+
+#ifdef CONFIG_DFS_SLAVE_WITH_RADAR_DETECT
+static int proc_get_dfs_slave_with_rd(struct seq_file *m, void *v)
+{
+	struct net_device *dev = m->private;
+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
+	struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter);
+
+	RTW_PRINT_SEL(m, "%u\n", rfctl->dfs_slave_with_rd);
+
+	return 0;
+}
+
+static ssize_t proc_set_dfs_slave_with_rd(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
+{
+	struct net_device *dev = data;
+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
+	struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter);
+	char tmp[32];
+	u8 rd;
+	int num;
+
+	if (count < 1)
+		return -EFAULT;
+
+	if (count > sizeof(tmp)) {
+		rtw_warn_on(1);
+		return -EFAULT;
+	}
+
+	if (!buffer || copy_from_user(tmp, buffer, count))
+		goto exit;
+
+	num = sscanf(tmp, "%hhu", &rd);
+	if (num != 1)
+		goto exit;
+
+	rd = rd ? 1 : 0;
+
+	if (rfctl->dfs_slave_with_rd != rd) {
+		rfctl->dfs_slave_with_rd = rd;
+		rtw_dfs_rd_en_decision_cmd(adapter);
+	}
+
+exit:
+	return count;
+}
+#endif /* CONFIG_DFS_SLAVE_WITH_RADAR_DETECT */
+#endif /* CONFIG_DFS_MASTER */
+
+#ifdef CONFIG_80211N_HT
+int proc_get_rx_ampdu_size_limit(struct seq_file *m, void *v)
+{
+	struct net_device *dev = m->private;
+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
+
+	dump_regsty_rx_ampdu_size_limit(m, adapter);
+
+	return 0;
+}
+
+ssize_t proc_set_rx_ampdu_size_limit(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
+{
+	struct net_device *dev = data;
+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
+	struct registry_priv *regsty = adapter_to_regsty(adapter);
+	char tmp[32];
+	u8 nss;
+	u8 limit_by_bw[4] = {0xFF};
+
+	if (count < 1)
+		return -EFAULT;
+
+	if (count > sizeof(tmp)) {
+		rtw_warn_on(1);
+		return -EFAULT;
+	}
+
+	if (buffer && !copy_from_user(tmp, buffer, count)) {
+		int i;
+		int num = sscanf(tmp, "%hhu %hhu %hhu %hhu %hhu"
+			, &nss, &limit_by_bw[0], &limit_by_bw[1], &limit_by_bw[2], &limit_by_bw[3]);
+
+		if (num < 2)
+			goto exit;
+		if (nss == 0 || nss > 4)
+			goto exit;
+
+		for (i = 0; i < num - 1; i++)
+			regsty->rx_ampdu_sz_limit_by_nss_bw[nss - 1][i] = limit_by_bw[i];
+
+		rtw_rx_ampdu_apply(adapter);
+	}
+
+exit:
+	return count;
+}
+#endif /* CONFIG_80211N_HT */
+
+static int proc_get_udpport(struct seq_file *m, void *v)
+{
+	struct net_device *dev = m->private;
+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
+	struct recv_priv *precvpriv = &(padapter->recvpriv);
+
+	RTW_PRINT_SEL(m, "%d\n", precvpriv->sink_udpport);
+	return 0;
+}
+static ssize_t proc_set_udpport(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
+{
+	struct net_device *dev = data;
+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
+	struct recv_priv *precvpriv = &(padapter->recvpriv);
+	int sink_udpport = 0;
+	char tmp[32];
+
+
+	if (!padapter)
+		return -EFAULT;
+
+	if (count < 1) {
+		RTW_INFO("argument size is less than 1\n");
+		return -EFAULT;
+	}
+
+	if (count > sizeof(tmp)) {
+		rtw_warn_on(1);
+		return -EFAULT;
+	}
+
+	if (buffer && !copy_from_user(tmp, buffer, count)) {
+
+		int num = sscanf(tmp, "%d", &sink_udpport);
+
+		if (num !=  1) {
+			RTW_INFO("invalid input parameter number!\n");
+			return count;
+		}
+
+	}
+	precvpriv->sink_udpport = sink_udpport;
+
+	return count;
+
+}
+
+static int proc_get_mi_ap_bc_info(struct seq_file *m, void *v)
+{
+	struct net_device *dev = m->private;
+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
+	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
+	struct macid_ctl_t *macid_ctl = dvobj_to_macidctl(dvobj);
+	u8 i;
+
+	for (i = 0; i < dvobj->iface_nums; i++)
+		RTW_PRINT_SEL(m, "iface_id:%d, mac_id && sec_cam_id = %d\n", i, macid_ctl->iface_bmc[i]);
+
+	return 0;
+}
+static int proc_get_macid_info(struct seq_file *m, void *v)
+{
+	struct net_device *dev = m->private;
+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
+	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
+	struct macid_ctl_t *macid_ctl = dvobj_to_macidctl(dvobj);
+	struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter);
+	u8 i;
+	u8 null_addr[ETH_ALEN] = {0};
+	u8 *macaddr;
+
+	RTW_PRINT_SEL(m, "max_num:%u\n", macid_ctl->num);
+	RTW_PRINT_SEL(m, "\n");
+
+	RTW_PRINT_SEL(m, "used:\n");
+	dump_macid_map(m, &macid_ctl->used, macid_ctl->num);
+	RTW_PRINT_SEL(m, "\n");
+
+	RTW_PRINT_SEL(m, "%-3s %-3s %-5s %-4s %-17s %-6s %-3s"
+		, "id", "bmc", "ifbmp", "ch_g", "macaddr", "bw", "vht");
+
+	if (hal_spec->tx_nss_num > 2)
+		_RTW_PRINT_SEL(m, " %-10s", "rate_bmp1");
+
+	_RTW_PRINT_SEL(m, " %-10s %s\n", "rate_bmp0", "status");
+
+	for (i = 0; i < macid_ctl->num; i++) {
+		if (rtw_macid_is_used(macid_ctl, i)
+			|| macid_ctl->h2c_msr[i]
+		) {
+			if (macid_ctl->sta[i])
+				macaddr = macid_ctl->sta[i]->cmn.mac_addr;
+			else
+				macaddr = null_addr;
+
+			RTW_PRINT_SEL(m, "%3u %3u  0x%02x %4d "MAC_FMT" %6s %3u"
+				, i
+				, rtw_macid_is_bmc(macid_ctl, i)
+				, rtw_macid_get_iface_bmp(macid_ctl, i)
+				, rtw_macid_get_ch_g(macid_ctl, i)
+				, MAC_ARG(macaddr)
+				, ch_width_str(macid_ctl->bw[i])
+				, macid_ctl->vht_en[i]
+			);
+
+			if (hal_spec->tx_nss_num > 2)
+				_RTW_PRINT_SEL(m, " 0x%08X", macid_ctl->rate_bmp1[i]);
+
+			_RTW_PRINT_SEL(m, " 0x%08X "H2C_MSR_FMT" %s\n"
+				, macid_ctl->rate_bmp0[i]
+				, H2C_MSR_ARG(&macid_ctl->h2c_msr[i])
+				, rtw_macid_is_used(macid_ctl, i) ? "" : "[unused]"
+			);
+		}
+	}
+
+	return 0;
+}
+
+static int proc_get_sec_cam(struct seq_file *m, void *v)
+{
+	struct net_device *dev = m->private;
+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
+	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
+	struct cam_ctl_t *cam_ctl = &dvobj->cam_ctl;
+
+	RTW_PRINT_SEL(m, "sec_cap:0x%02x\n", cam_ctl->sec_cap);
+	RTW_PRINT_SEL(m, "flags:0x%08x\n", cam_ctl->flags);
+	RTW_PRINT_SEL(m, "\n");
+
+	RTW_PRINT_SEL(m, "max_num:%u\n", cam_ctl->num);
+	RTW_PRINT_SEL(m, "used:\n");
+	dump_sec_cam_map(m, &cam_ctl->used, cam_ctl->num);
+	RTW_PRINT_SEL(m, "\n");
+
+	RTW_PRINT_SEL(m, "reg_scr:0x%04x\n", rtw_read16(adapter, 0x680));
+	RTW_PRINT_SEL(m, "\n");
+
+	dump_sec_cam(m, adapter);
+
+	return 0;
+}
+
+static ssize_t proc_set_sec_cam(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
+{
+	struct net_device *dev = data;
+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
+	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
+	struct cam_ctl_t *cam_ctl = &dvobj->cam_ctl;
+	char tmp[32] = {0};
+	char cmd[4];
+	u8 id_1 = 0, id_2 = 0;
+
+	if (count > sizeof(tmp)) {
+		rtw_warn_on(1);
+		return -EFAULT;
+	}
+
+	if (buffer && !copy_from_user(tmp, buffer, count)) {
+
+		/* c <id_1>: clear specific cam entry */
+		/* wfc <id_1>: write specific cam entry from cam cache */
+		/* sw <id_1> <id_2>: sec_cam 1/2 swap */
+
+		int num = sscanf(tmp, "%s %hhu %hhu", cmd, &id_1, &id_2);
+
+		if (num < 2)
+			return count;
+
+		if ((id_1 >= cam_ctl->num) || (id_2 >= cam_ctl->num)) {
+			RTW_ERR(FUNC_ADPT_FMT" invalid id_1:%u id_2:%u\n", FUNC_ADPT_ARG(adapter), id_1, id_2);
+			return count;
+		}
+
+		if (strcmp("c", cmd) == 0) {
+			_clear_cam_entry(adapter, id_1);
+			adapter->securitypriv.hw_decrypted = _FALSE; /* temporarily set this for TX path to use SW enc */
+		} else if (strcmp("wfc", cmd) == 0)
+			write_cam_from_cache(adapter, id_1);
+		else if (strcmp("sw", cmd) == 0)
+			rtw_sec_cam_swap(adapter, id_1, id_2);
+		else if (strcmp("cdk", cmd) == 0)
+			rtw_clean_dk_section(adapter);
+#ifdef DBG_SEC_CAM_MOVE
+		else if (strcmp("sgd", cmd) == 0)
+			rtw_hal_move_sta_gk_to_dk(adapter);
+		else if (strcmp("rsd", cmd) == 0)
+			rtw_hal_read_sta_dk_key(adapter, id_1);
+#endif
+	}
+
+	return count;
+}
+
+static int proc_get_sec_cam_cache(struct seq_file *m, void *v)
+{
+	struct net_device *dev = m->private;
+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
+
+	dump_sec_cam_cache(m, adapter);
+	return 0;
+}
+
+static ssize_t proc_set_change_bss_chbw(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
+{
+	struct net_device *dev = data;
+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
+	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
+	int i;
+	char tmp[32];
+	s16 ch;
+	s8 bw = REQ_BW_NONE, offset = REQ_OFFSET_NONE;
+	u8 ifbmp = 0;
+
+	if (count < 1)
+		return -EFAULT;
+
+	if (count > sizeof(tmp)) {
+		rtw_warn_on(1);
+		return -EFAULT;
+	}
+
+	if (buffer && !copy_from_user(tmp, buffer, count)) {
+
+		int num = sscanf(tmp, "%hd %hhd %hhd %hhx", &ch, &bw, &offset, &ifbmp);
+
+		if (num < 1 || (bw != CHANNEL_WIDTH_20 && num < 3))
+			goto exit;
+
+		if (num < 4)
+			ifbmp = BIT(adapter->iface_id);
+		else
+			ifbmp &= (1 << dvobj->iface_nums) - 1;
+
+		for (i = 0; i < dvobj->iface_nums; i++) {
+			if (!(ifbmp & BIT(i)) || !dvobj->padapters[i])
+				continue;
+
+			if (!CHK_MLME_STATE(dvobj->padapters[i], WIFI_AP_STATE | WIFI_MESH_STATE)
+				|| !MLME_IS_ASOC(dvobj->padapters[i]))
+				ifbmp &= ~BIT(i);
+		}
+
+		if (ifbmp)
+			rtw_change_bss_chbw_cmd(adapter, RTW_CMDF_WAIT_ACK, ifbmp, 0, ch, bw, offset);
+	}
+
+exit:
+	return count;
+}
+
+static int proc_get_tx_bw_mode(struct seq_file *m, void *v)
+{
+	struct net_device *dev = m->private;
+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
+
+	RTW_PRINT_SEL(m, "0x%02x\n", adapter->driver_tx_bw_mode);
+	RTW_PRINT_SEL(m, "2.4G:%s\n", ch_width_str(ADAPTER_TX_BW_2G(adapter)));
+	RTW_PRINT_SEL(m, "5G:%s\n", ch_width_str(ADAPTER_TX_BW_5G(adapter)));
+
+	return 0;
+}
+
+static ssize_t proc_set_tx_bw_mode(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
+{
+	struct net_device *dev = data;
+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
+	struct macid_ctl_t *macid_ctl = &adapter->dvobj->macid_ctl;
+	struct mlme_ext_priv *mlmeext = &(adapter->mlmeextpriv);
+	char tmp[32];
+	u8 bw_mode;
+
+	if (count < 1)
+		return -EFAULT;
+
+	if (count > sizeof(tmp)) {
+		rtw_warn_on(1);
+		return -EFAULT;
+	}
+
+	if (buffer && !copy_from_user(tmp, buffer, count)) {
+
+		u8 update = _FALSE;
+		int num = sscanf(tmp, "%hhx", &bw_mode);
+
+		if (num < 1 || bw_mode == adapter->driver_tx_bw_mode)
+			goto exit;
+
+		if ((MLME_STATE(adapter) & WIFI_ASOC_STATE)
+			&& ((mlmeext->cur_channel <= 14 && BW_MODE_2G(bw_mode) != ADAPTER_TX_BW_2G(adapter))
+				|| (mlmeext->cur_channel >= 36 && BW_MODE_5G(bw_mode) != ADAPTER_TX_BW_5G(adapter)))
+		) {
+			/* RA mask update needed */
+			update = _TRUE;
+		}
+		adapter->driver_tx_bw_mode = bw_mode;
+
+		if (update == _TRUE) {
+			struct sta_info *sta;
+			int i;
+
+			for (i = 0; i < MACID_NUM_SW_LIMIT; i++) {
+				sta = macid_ctl->sta[i];
+				if (sta && !is_broadcast_mac_addr(sta->cmn.mac_addr))
+					rtw_dm_ra_mask_wk_cmd(adapter, (u8 *)sta);
+			}
+		}
+	}
+
+exit:
+	return count;
+}
+
+static int proc_get_hal_txpwr_info(struct seq_file *m, void *v)
+{
+	struct net_device *dev = m->private;
+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
+	struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter);
+
+	if (hal_is_band_support(adapter, BAND_ON_2_4G))
+		dump_hal_txpwr_info_2g(m, adapter, hal_spec->rfpath_num_2g, hal_spec->max_tx_cnt);
+
+#ifdef CONFIG_IEEE80211_BAND_5GHZ
+	if (hal_is_band_support(adapter, BAND_ON_5G))
+		dump_hal_txpwr_info_5g(m, adapter, hal_spec->rfpath_num_5g, hal_spec->max_tx_cnt);
+#endif
+
+	return 0;
+}
+
+static int proc_get_target_tx_power(struct seq_file *m, void *v)
+{
+	struct net_device *dev = m->private;
+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
+
+	dump_target_tx_power(m, adapter);
+
+	return 0;
+}
+
+static int proc_get_tx_power_by_rate(struct seq_file *m, void *v)
+{
+	struct net_device *dev = m->private;
+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
+
+	dump_tx_power_by_rate(m, adapter);
+
+	return 0;
+}
+
+#ifdef CONFIG_TXPWR_LIMIT
+static int proc_get_tx_power_limit(struct seq_file *m, void *v)
+{
+	struct net_device *dev = m->private;
+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
+
+	dump_txpwr_lmt(m, adapter);
+
+	return 0;
+}
+#endif /* CONFIG_TXPWR_LIMIT */
+
+static int proc_get_tx_power_ext_info(struct seq_file *m, void *v)
+{
+	struct net_device *dev = m->private;
+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
+
+	dump_tx_power_ext_info(m, adapter);
+
+	return 0;
+}
+
+static ssize_t proc_set_tx_power_ext_info(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
+{
+	struct net_device *dev = data;
+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
+
+	char tmp[32] = {0};
+	char cmd[16] = {0};
+
+	if (count > sizeof(tmp)) {
+		rtw_warn_on(1);
+		return -EFAULT;
+	}
+
+	if (buffer && !copy_from_user(tmp, buffer, count)) {
+
+		int num = sscanf(tmp, "%s", cmd);
+
+		if (num < 1)
+			return count;
+
+		#ifdef CONFIG_LOAD_PHY_PARA_FROM_FILE
+		phy_free_filebuf_mask(adapter, LOAD_BB_PG_PARA_FILE | LOAD_RF_TXPWR_LMT_PARA_FILE);
+		#endif
+
+		rtw_ps_deny(adapter, PS_DENY_IOCTL);
+		if (rtw_pwr_wakeup(adapter) == _FALSE)
+			goto clear_ps_deny;
+
+		if (strcmp("default", cmd) == 0)
+			rtw_run_in_thread_cmd(adapter, ((void *)(phy_reload_default_tx_power_ext_info)), adapter);
+		else
+			rtw_run_in_thread_cmd(adapter, ((void *)(phy_reload_tx_power_ext_info)), adapter);
+
+clear_ps_deny:
+		rtw_ps_deny_cancel(adapter, PS_DENY_IOCTL);
+	}
+
+	return count;
+}
+
+static void *proc_start_tx_power_idx(struct seq_file *m, loff_t *pos)
+{
+	u8 path = ((*pos) & 0xFF00) >> 8;
+
+	if (path >= RF_PATH_MAX)
+		return NULL;
+
+	return pos;
+}
+static void proc_stop_tx_power_idx(struct seq_file *m, void *v)
+{
+}
+
+static void *proc_next_tx_power_idx(struct seq_file *m, void *v, loff_t *pos)
+{
+	u8 path = ((*pos) & 0xFF00) >> 8;
+	u8 rs = *pos & 0xFF;
+
+	rs++;
+	if (rs >= RATE_SECTION_NUM) {
+		rs = 0;
+		path++;
+	}
+
+	if (path >= RF_PATH_MAX)
+		return NULL;
+
+	*pos = (path << 8) | rs;
+
+	return pos;
+}
+
+static int proc_get_tx_power_idx(struct seq_file *m, void *v)
+{
+	struct net_device *dev = m->private;
+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
+	u32 pos = *((loff_t *)(v));
+	u8 path = (pos & 0xFF00) >> 8;
+	u8 rs = pos & 0xFF;
+
+	if (0)
+		RTW_INFO("%s path=%u, rs=%u\n", __func__, path, rs);
+
+	if (path == RF_PATH_A && rs == CCK)
+		dump_tx_power_idx_title(m, adapter);
+	dump_tx_power_idx_by_path_rs(m, adapter, path, rs);
+
+	return 0;
+}
+
+static struct seq_operations seq_ops_tx_power_idx = {
+	.start = proc_start_tx_power_idx,
+	.stop  = proc_stop_tx_power_idx,
+	.next  = proc_next_tx_power_idx,
+	.show  = proc_get_tx_power_idx,
+};
+
+#ifdef CONFIG_RF_POWER_TRIM
+static int proc_get_kfree_flag(struct seq_file *m, void *v)
+{
+	struct net_device *dev = m->private;
+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
+	struct kfree_data_t *kfree_data = GET_KFREE_DATA(adapter);
+
+	RTW_PRINT_SEL(m, "0x%02x\n", kfree_data->flag);
+
+	return 0;
+}
+
+static ssize_t proc_set_kfree_flag(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
+{
+	struct net_device *dev = data;
+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
+	struct kfree_data_t *kfree_data = GET_KFREE_DATA(adapter);
+	char tmp[32] = {0};
+	u8 flag;
+
+	if (count > sizeof(tmp)) {
+		rtw_warn_on(1);
+		return -EFAULT;
+	}
+
+	if (buffer && !copy_from_user(tmp, buffer, count)) {
+
+		int num = sscanf(tmp, "%hhx", &flag);
+
+		if (num < 1)
+			return count;
+
+		kfree_data->flag = flag;
+	}
+
+	return count;
+}
+
+static int proc_get_kfree_bb_gain(struct seq_file *m, void *v)
+{
+	struct net_device *dev = m->private;
+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
+	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
+	struct kfree_data_t *kfree_data = GET_KFREE_DATA(adapter);
+	u8 i, j;
+
+	for (i = 0; i < BB_GAIN_NUM; i++) {
+		if (i == 0)
+			_RTW_PRINT_SEL(m, "2G: ");
+		else if (i == 1)
+			_RTW_PRINT_SEL(m, "5GLB1: ");
+		else if (i == 2)
+			_RTW_PRINT_SEL(m, "5GLB2: ");
+		else if (i == 3)
+			_RTW_PRINT_SEL(m, "5GMB1: ");
+		else if (i == 4)
+			_RTW_PRINT_SEL(m, "5GMB2: ");
+		else if (i == 5)
+			_RTW_PRINT_SEL(m, "5GHB: ");
+
+		for (j = 0; j < hal_data->NumTotalRFPath; j++)
+			_RTW_PRINT_SEL(m, "%d ", kfree_data->bb_gain[i][j]);
+		_RTW_PRINT_SEL(m, "\n");
+	}
+
+	return 0;
+}
+
+static ssize_t proc_set_kfree_bb_gain(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
+{
+	struct net_device *dev = data;
+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
+	struct kfree_data_t *kfree_data = GET_KFREE_DATA(adapter);
+	char tmp[BB_GAIN_NUM * RF_PATH_MAX] = {0};
+	u8 chidx;
+	s8 bb_gain[BB_GAIN_NUM];
+	char ch_band_Group[6];
+
+	if (count > sizeof(tmp)) {
+		rtw_warn_on(1);
+		return -EFAULT;
+	}
+
+	if (buffer && !copy_from_user(tmp, buffer, count)) {
+		char *c, *next;
+		int i = 0;
+
+		next = tmp;
+		c = strsep(&next, " \t");
+
+		if (sscanf(c, "%s", ch_band_Group) != 1) {
+			RTW_INFO("Error Head Format, channel Group select\n,Please input:\t 2G , 5GLB1 , 5GLB2 , 5GMB1 , 5GMB2 , 5GHB\n");
+			return count;
+		}
+		if (strcmp("2G", ch_band_Group) == 0)
+			chidx = BB_GAIN_2G;
+#ifdef CONFIG_IEEE80211_BAND_5GHZ
+		else if (strcmp("5GLB1", ch_band_Group) == 0)
+			chidx = BB_GAIN_5GLB1;
+		else if (strcmp("5GLB2", ch_band_Group) == 0)
+			chidx = BB_GAIN_5GLB2;
+		else if (strcmp("5GMB1", ch_band_Group) == 0)
+			chidx = BB_GAIN_5GMB1;
+		else if (strcmp("5GMB2", ch_band_Group) == 0)
+			chidx = BB_GAIN_5GMB2;
+		else if (strcmp("5GHB", ch_band_Group) == 0)
+			chidx = BB_GAIN_5GHB;
+#endif /*CONFIG_IEEE80211_BAND_5GHZ*/
+		else {
+			RTW_INFO("Error Head Format, channel Group select\n,Please input:\t 2G , 5GLB1 , 5GLB2 , 5GMB1 , 5GMB2 , 5GHB\n");
+			return count;
+		}
+		c = strsep(&next, " \t");
+
+		while (c != NULL) {
+			if (sscanf(c, "%hhx", &bb_gain[i]) != 1)
+				break;
+
+			kfree_data->bb_gain[chidx][i] = bb_gain[i];
+			RTW_INFO("%s,kfree_data->bb_gain[%d][%d]=%x\n", __func__, chidx, i, kfree_data->bb_gain[chidx][i]);
+
+			c = strsep(&next, " \t");
+			i++;
+		}
+
+	}
+
+	return count;
+
+}
+
+static int proc_get_kfree_thermal(struct seq_file *m, void *v)
+{
+	struct net_device *dev = m->private;
+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
+	struct kfree_data_t *kfree_data = GET_KFREE_DATA(adapter);
+
+	_RTW_PRINT_SEL(m, "%d\n", kfree_data->thermal);
+
+	return 0;
+}
+
+static ssize_t proc_set_kfree_thermal(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
+{
+	struct net_device *dev = data;
+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
+	struct kfree_data_t *kfree_data = GET_KFREE_DATA(adapter);
+	char tmp[32] = {0};
+	s8 thermal;
+
+	if (count > sizeof(tmp)) {
+		rtw_warn_on(1);
+		return -EFAULT;
+	}
+
+	if (buffer && !copy_from_user(tmp, buffer, count)) {
+
+		int num = sscanf(tmp, "%hhd", &thermal);
+
+		if (num < 1)
+			return count;
+
+		kfree_data->thermal = thermal;
+	}
+
+	return count;
+}
+
+static ssize_t proc_set_tx_gain_offset(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
+{
+	struct net_device *dev = data;
+	_adapter *adapter;
+	char tmp[32] = {0};
+	u8 rf_path;
+	s8 offset;
+
+	adapter = (_adapter *)rtw_netdev_priv(dev);
+	if (!adapter)
+		return -EFAULT;
+
+	if (count > sizeof(tmp)) {
+		rtw_warn_on(1);
+		return -EFAULT;
+	}
+
+	if (buffer && !copy_from_user(tmp, buffer, count)) {
+		int num = sscanf(tmp, "%hhu %hhd", &rf_path, &offset);
+
+		if (num < 2)
+			return count;
+
+		RTW_INFO("write rf_path:%u tx gain offset:%d\n", rf_path, offset);
+		rtw_rf_set_tx_gain_offset(adapter, rf_path, offset);
+	}
+
+	return count;
+}
+#endif /* CONFIG_RF_POWER_TRIM */
+
+#ifdef CONFIG_BT_COEXIST
+ssize_t proc_set_btinfo_evt(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
+{
+	struct net_device *dev = data;
+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
+	char tmp[32];
+	u8 btinfo[8];
+
+	if (count < 6)
+		return -EFAULT;
+
+	if (count > sizeof(tmp)) {
+		rtw_warn_on(1);
+		return -EFAULT;
+	}
+
+	if (buffer && !copy_from_user(tmp, buffer, count)) {
+		int num = 0;
+
+		_rtw_memset(btinfo, 0, 8);
+
+		num = sscanf(tmp, "%hhx %hhx %hhx %hhx %hhx %hhx %hhx %hhx"
+			, &btinfo[0], &btinfo[1], &btinfo[2], &btinfo[3]
+			, &btinfo[4], &btinfo[5], &btinfo[6], &btinfo[7]);
+
+		if (num < 6)
+			return -EINVAL;
+
+		btinfo[1] = num - 2;
+
+		rtw_btinfo_cmd(padapter, btinfo, btinfo[1] + 2);
+	}
+
+	return count;
+}
+
+static u8 btreg_read_type = 0;
+static u16 btreg_read_addr = 0;
+static int btreg_read_error = 0;
+static u8 btreg_write_type = 0;
+static u16 btreg_write_addr = 0;
+static int btreg_write_error = 0;
+
+static u8 *btreg_type[] = {
+	"rf",
+	"modem",
+	"bluewize",
+	"vendor",
+	"le"
+};
+
+static int btreg_parse_str(char const *input, u8 *type, u16 *addr, u16 *val)
+{
+	u32 num;
+	u8 str[80] = {0};
+	u8 t = 0;
+	u32 a, v;
+	u8 i, n;
+	u8 *p;
+
+
+	num = sscanf(input, "%s %x %x", str, &a, &v);
+	if (num < 2) {
+		RTW_INFO("%s: INVALID input!(%s)\n", __FUNCTION__, input);
+		return -EINVAL;
+	}
+	if ((num < 3) && val) {
+		RTW_INFO("%s: INVALID input!(%s)\n", __FUNCTION__, input);
+		return -EINVAL;
+	}
+
+	/* convert to lower case for following type compare */
+	p = str;
+	for (; *p; ++p)
+		*p = tolower(*p);
+	n = sizeof(btreg_type) / sizeof(btreg_type[0]);
+	for (i = 0; i < n; i++) {
+		if (!strcmp(str, btreg_type[i])) {
+			t = i;
+			break;
+		}
+	}
+	if (i == n) {
+		RTW_INFO("%s: unknown type(%s)!\n", __FUNCTION__, str);
+		return -EINVAL;
+	}
+
+	switch (t) {
+	case 0:
+		/* RF */
+		if (a & 0xFFFFFF80) {
+			RTW_INFO("%s: INVALID address(0x%X) for type %s(%d)!\n",
+				 __FUNCTION__, a, btreg_type[t], t);
+			return -EINVAL;
+		}
+		break;
+	case 1:
+		/* Modem */
+		if (a & 0xFFFFFE00) {
+			RTW_INFO("%s: INVALID address(0x%X) for type %s(%d)!\n",
+				 __FUNCTION__, a, btreg_type[t], t);
+			return -EINVAL;
+		}
+		break;
+	default:
+		/* Others(Bluewize, Vendor, LE) */
+		if (a & 0xFFFFF000) {
+			RTW_INFO("%s: INVALID address(0x%X) for type %s(%d)!\n",
+				 __FUNCTION__, a, btreg_type[t], t);
+			return -EINVAL;
+		}
+		break;
+	}
+
+	if (val) {
+		if (v & 0xFFFF0000) {
+			RTW_INFO("%s: INVALID value(0x%x)!\n", __FUNCTION__, v);
+			return -EINVAL;
+		}
+		*val = (u16)v;
+	}
+
+	*type = (u8)t;
+	*addr = (u16)a;
+
+	return 0;
+}
+
+int proc_get_btreg_read(struct seq_file *m, void *v)
+{
+	struct net_device *dev;
+	PADAPTER padapter;
+	u16 ret;
+	u32 data;
+
+
+	if (btreg_read_error)
+		return btreg_read_error;
+
+	dev = m->private;
+	padapter = (PADAPTER)rtw_netdev_priv(dev);
+
+	ret = rtw_btcoex_btreg_read(padapter, btreg_read_type, btreg_read_addr, &data);
+	if (CHECK_STATUS_CODE_FROM_BT_MP_OPER_RET(ret, BT_STATUS_BT_OP_SUCCESS))
+		RTW_PRINT_SEL(m, "BTREG read: (%s)0x%04X = 0x%08x\n", btreg_type[btreg_read_type], btreg_read_addr, data);
+	else
+		RTW_PRINT_SEL(m, "BTREG read: (%s)0x%04X read fail. error code = 0x%04x.\n", btreg_type[btreg_read_type], btreg_read_addr, ret);
+
+	return 0;
+}
+
+ssize_t proc_set_btreg_read(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
+{
+	struct net_device *dev = data;
+	PADAPTER padapter;
+	u8 tmp[80] = {0};
+	u32 num;
+	int err;
+
+
+	padapter = (PADAPTER)rtw_netdev_priv(dev);
+
+	if (NULL == buffer) {
+		RTW_INFO(FUNC_ADPT_FMT ": input buffer is NULL!\n",
+			 FUNC_ADPT_ARG(padapter));
+		err = -EFAULT;
+		goto exit;
+	}
+
+	if (count < 1) {
+		RTW_INFO(FUNC_ADPT_FMT ": input length is 0!\n",
+			 FUNC_ADPT_ARG(padapter));
+		err = -EFAULT;
+		goto exit;
+	}
+
+	num = count;
+	if (num > (sizeof(tmp) - 1))
+		num = (sizeof(tmp) - 1);
+
+	if (copy_from_user(tmp, buffer, num)) {
+		RTW_INFO(FUNC_ADPT_FMT ": copy buffer from user space FAIL!\n",
+			 FUNC_ADPT_ARG(padapter));
+		err = -EFAULT;
+		goto exit;
+	}
+	/* [Coverity] sure tmp end with '\0'(string terminal) */
+	tmp[sizeof(tmp) - 1] = 0;
+
+	err = btreg_parse_str(tmp, &btreg_read_type, &btreg_read_addr, NULL);
+	if (err)
+		goto exit;
+
+	RTW_INFO(FUNC_ADPT_FMT ": addr=(%s)0x%X\n",
+		FUNC_ADPT_ARG(padapter), btreg_type[btreg_read_type], btreg_read_addr);
+
+exit:
+	btreg_read_error = err;
+
+	return count;
+}
+
+int proc_get_btreg_write(struct seq_file *m, void *v)
+{
+	struct net_device *dev;
+	PADAPTER padapter;
+	u16 ret;
+	u32 data;
+
+
+	if (btreg_write_error < 0)
+		return btreg_write_error;
+	else if (btreg_write_error > 0) {
+		RTW_PRINT_SEL(m, "BTREG write: (%s)0x%04X write fail. error code = 0x%04x.\n", btreg_type[btreg_write_type], btreg_write_addr, btreg_write_error);
+		return 0;
+	}
+
+	dev = m->private;
+	padapter = (PADAPTER)rtw_netdev_priv(dev);
+
+	ret = rtw_btcoex_btreg_read(padapter, btreg_write_type, btreg_write_addr, &data);
+	if (CHECK_STATUS_CODE_FROM_BT_MP_OPER_RET(ret, BT_STATUS_BT_OP_SUCCESS))
+		RTW_PRINT_SEL(m, "BTREG read: (%s)0x%04X = 0x%08x\n", btreg_type[btreg_write_type], btreg_write_addr, data);
+	else
+		RTW_PRINT_SEL(m, "BTREG read: (%s)0x%04X read fail. error code = 0x%04x.\n", btreg_type[btreg_write_type], btreg_write_addr, ret);
+
+	return 0;
+}
+
+ssize_t proc_set_btreg_write(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
+{
+	struct net_device *dev = data;
+	PADAPTER padapter;
+	u8 tmp[80] = {0};
+	u32 num;
+	u16 val;
+	u16 ret;
+	int err;
+
+
+	padapter = (PADAPTER)rtw_netdev_priv(dev);
+
+	if (NULL == buffer) {
+		RTW_INFO(FUNC_ADPT_FMT ": input buffer is NULL!\n",
+			 FUNC_ADPT_ARG(padapter));
+		err = -EFAULT;
+		goto exit;
+	}
+
+	if (count < 1) {
+		RTW_INFO(FUNC_ADPT_FMT ": input length is 0!\n",
+			 FUNC_ADPT_ARG(padapter));
+		err = -EFAULT;
+		goto exit;
+	}
+
+	num = count;
+	if (num > (sizeof(tmp) - 1))
+		num = (sizeof(tmp) - 1);
+
+	if (copy_from_user(tmp, buffer, num)) {
+		RTW_INFO(FUNC_ADPT_FMT ": copy buffer from user space FAIL!\n",
+			 FUNC_ADPT_ARG(padapter));
+		err = -EFAULT;
+		goto exit;
+	}
+
+	err = btreg_parse_str(tmp, &btreg_write_type, &btreg_write_addr, &val);
+	if (err)
+		goto exit;
+
+	RTW_INFO(FUNC_ADPT_FMT ": Set (%s)0x%X = 0x%x\n",
+		FUNC_ADPT_ARG(padapter), btreg_type[btreg_write_type], btreg_write_addr, val);
+
+	ret = rtw_btcoex_btreg_write(padapter, btreg_write_type, btreg_write_addr, val);
+	if (!CHECK_STATUS_CODE_FROM_BT_MP_OPER_RET(ret, BT_STATUS_BT_OP_SUCCESS))
+		err = ret;
+
+exit:
+	btreg_write_error = err;
+
+	return count;
+}
+#endif /* CONFIG_BT_COEXIST */
+
+#ifdef CONFIG_MBSSID_CAM
+int proc_get_mbid_cam_cache(struct seq_file *m, void *v)
+{
+	struct net_device *dev = m->private;
+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
+
+	rtw_mbid_cam_cache_dump(m, __func__, adapter);
+	rtw_mbid_cam_dump(m, __func__, adapter);
+	return 0;
+}
+#endif /* CONFIG_MBSSID_CAM */
+
+int proc_get_mac_addr(struct seq_file *m, void *v)
+{
+	struct net_device *dev = m->private;
+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
+
+	rtw_hal_dump_macaddr(m, adapter);
+	return 0;
+}
+
+static int proc_get_skip_band(struct seq_file *m, void *v)
+{
+	struct net_device *dev = m->private;
+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
+	int bandskip;
+
+	bandskip = RTW_GET_SCAN_BAND_SKIP(adapter);
+	RTW_PRINT_SEL(m, "bandskip:0x%02x\n", bandskip);
+	return 0;
+}
+
+static ssize_t proc_set_skip_band(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
+{
+	struct net_device *dev = data;
+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
+	char tmp[6];
+	u8 skip_band;
+
+	if (count < 1)
+		return -EFAULT;
+
+	if (count > sizeof(tmp)) {
+		rtw_warn_on(1);
+		return -EFAULT;
+	}
+	if (buffer && !copy_from_user(tmp, buffer, count)) {
+
+		int num = sscanf(tmp, "%hhu", &skip_band);
+
+		if (num < 1)
+			return -EINVAL;
+
+		if (1 == skip_band)
+			RTW_SET_SCAN_BAND_SKIP(padapter, BAND_24G);
+		else if (2 == skip_band)
+			RTW_SET_SCAN_BAND_SKIP(padapter, BAND_5G);
+		else if (3 == skip_band)
+			RTW_CLR_SCAN_BAND_SKIP(padapter, BAND_24G);
+		else if (4 == skip_band)
+			RTW_CLR_SCAN_BAND_SKIP(padapter, BAND_5G);
+	}
+	return count;
+
+}
+
+#ifdef CONFIG_RTW_ACS
+static int proc_get_chan_info(struct seq_file *m, void *v)
+{
+	struct net_device *dev = m->private;
+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
+
+	rtw_acs_chan_info_dump(m, adapter);
+	return 0;
+}
+
+static int proc_get_best_chan(struct seq_file *m, void *v)
+{
+	struct net_device *dev = m->private;
+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
+
+	if (IS_ACS_ENABLE(adapter))
+		rtw_acs_info_dump(m, adapter);
+	else
+		_RTW_PRINT_SEL(m,"ACS disabled\n");
+	return 0;
+}
+
+static ssize_t proc_set_acs(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
+{
+#ifdef CONFIG_RTW_ACS_DBG
+	struct net_device *dev = data;
+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
+	char tmp[32];
+	u8 acs_state = 0;
+	u16 scan_ch_ms= 0, acs_scan_ch_ms = 0;
+	u8 scan_type = SCAN_ACTIVE, igi= 0, bw = 0;
+	u8 acs_scan_type = SCAN_ACTIVE, acs_igi= 0, acs_bw = 0;
+
+	if (count < 1)
+		return -EFAULT;
+
+	if (count > sizeof(tmp)) {
+		rtw_warn_on(1);
+		return -EFAULT;
+	}
+	if (buffer && !copy_from_user(tmp, buffer, count)) {
+
+		int num = sscanf(tmp, "%hhu %hhu %hu %hhx %hhu",
+			&acs_state, &scan_type, &scan_ch_ms, &igi, &bw);
+
+		if (num < 1)
+			return -EINVAL;
+
+		if (acs_state)
+			rtw_acs_start(padapter);
+		else
+			rtw_acs_stop(padapter);
+		num = num -1;
+
+		if(num) {
+			if (num-- > 0)
+				acs_scan_type = scan_type;
+			if (num-- > 0)
+				acs_scan_ch_ms = scan_ch_ms;
+			if (num-- > 0)
+				acs_igi = igi;
+			if (num-- > 0)
+				acs_bw = bw;
+			rtw_acs_adv_setting(padapter, acs_scan_type, acs_scan_ch_ms, acs_igi, acs_bw);
+		}
+	}
+#endif /*CONFIG_RTW_ACS_DBG*/
+	return count;
+}
+#endif /*CONFIG_RTW_ACS*/
+
+#ifdef CONFIG_BACKGROUND_NOISE_MONITOR
+static int proc_get_nm(struct seq_file *m, void *v)
+{
+	struct net_device *dev = m->private;
+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
+
+	rtw_noise_info_dump(m, adapter);
+	return 0;
+}
+
+static ssize_t proc_set_nm(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
+{
+	struct net_device *dev = data;
+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
+	char tmp[32];
+	u8 nm_state = 0;
+
+	if (count < 1)
+		return -EFAULT;
+
+	if (count > sizeof(tmp)) {
+		rtw_warn_on(1);
+		return -EFAULT;
+	}
+	if (buffer && !copy_from_user(tmp, buffer, count)) {
+
+		int num = sscanf(tmp, "%hhu", &nm_state);
+
+		if (num < 1)
+			return -EINVAL;
+
+		if (nm_state)
+			rtw_nm_enable(padapter);
+		else
+			rtw_nm_disable(padapter);
+
+	}
+	return count;
+}
+#endif /*CONFIG_RTW_ACS*/
+
+static int proc_get_hal_spec(struct seq_file *m, void *v)
+{
+	struct net_device *dev = m->private;
+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
+
+	dump_hal_spec(m, adapter);
+	return 0;
+}
+
+static int proc_get_phy_cap(struct seq_file *m, void *v)
+{
+	struct net_device *dev = m->private;
+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
+
+	rtw_dump_phy_cap(m, adapter);
+#ifdef CONFIG_80211N_HT
+	rtw_dump_drv_phy_cap(m, adapter);
+	rtw_get_dft_phy_cap(m, adapter);
+#endif /* CONFIG_80211N_HT */
+	return 0;
+}
+
+#ifdef CONFIG_SUPPORT_TRX_SHARED
+#include "../../hal/hal_halmac.h"
+static int proc_get_trx_share_mode(struct seq_file *m, void *v)
+{
+	struct net_device *dev = m->private;
+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
+
+	dump_trx_share_mode(m, adapter);
+	return 0;
+}
+#endif
+
+static int proc_dump_rsvd_page(struct seq_file *m, void *v)
+{
+	struct net_device *dev = m->private;
+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
+
+	rtw_dump_rsvd_page(m, adapter, adapter->rsvd_page_offset, adapter->rsvd_page_num);
+	return 0;
+}
+static ssize_t proc_set_rsvd_page_info(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
+{
+	struct net_device *dev = data;
+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
+	char tmp[32];
+	u8 page_offset, page_num;
+
+	if (count < 2)
+		return -EFAULT;
+
+	if (count > sizeof(tmp)) {
+		rtw_warn_on(1);
+		return -EFAULT;
+	}
+	if (buffer && !copy_from_user(tmp, buffer, count)) {
+
+		int num = sscanf(tmp, "%hhu %hhu", &page_offset, &page_num);
+
+		if (num < 2)
+			return -EINVAL;
+		padapter->rsvd_page_offset = page_offset;
+		padapter->rsvd_page_num = page_num;
+	}
+	return count;
+}
+
+#ifdef CONFIG_SUPPORT_FIFO_DUMP
+static int proc_dump_fifo(struct seq_file *m, void *v)
+{
+	struct net_device *dev = m->private;
+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
+
+	rtw_dump_fifo(m, adapter, adapter->fifo_sel, adapter->fifo_addr, adapter->fifo_size);
+	return 0;
+}
+static ssize_t proc_set_fifo_info(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
+{
+	struct net_device *dev = data;
+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
+	char tmp[32];
+	u8 fifo_sel = 0;
+	u32 fifo_addr = 0;
+	u32 fifo_size = 0;
+
+	if (count < 3)
+		return -EFAULT;
+
+	if (count > sizeof(tmp)) {
+		rtw_warn_on(1);
+		return -EFAULT;
+	}
+	if (buffer && !copy_from_user(tmp, buffer, count)) {
+
+		int num = sscanf(tmp, "%hhu %x %d", &fifo_sel, &fifo_addr, &fifo_size);
+
+		if (num < 3)
+			return -EINVAL;
+
+		padapter->fifo_sel = fifo_sel;
+		padapter->fifo_addr = fifo_addr;
+		padapter->fifo_size = fifo_size;
+	}
+	return count;
+}
+#endif
+
+#ifdef CONFIG_WOW_PATTERN_HW_CAM
+int proc_dump_pattern_cam(struct seq_file *m, void *v)
+{
+	struct net_device *dev = m->private;
+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
+	struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter);
+	int i;
+	struct  rtl_wow_pattern context;
+
+	for (i = 0 ; i < pwrpriv->wowlan_pattern_idx; i++) {
+		rtw_wow_pattern_read_cam_ent(padapter, i, &context);
+		rtw_dump_wow_pattern(m, &context, i);
+	}
+
+	return 0;
+}
+#endif
+
+static int proc_get_napi_info(struct seq_file *m, void *v)
+{
+	struct net_device *dev = m->private;
+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
+	struct registry_priv *pregistrypriv = &adapter->registrypriv;
+	u8 napi = 0, gro = 0;
+	u32 weight = 0;
+	struct dvobj_priv *d;
+	d = adapter_to_dvobj(adapter);
+
+
+#ifdef CONFIG_RTW_NAPI
+	if (pregistrypriv->en_napi) {
+		napi = 1;
+		weight = RTL_NAPI_WEIGHT;
+	}
+
+#ifdef CONFIG_RTW_GRO
+	if (pregistrypriv->en_gro)
+		gro = 1;
+#endif /* CONFIG_RTW_GRO */
+#endif /* CONFIG_RTW_NAPI */
+
+	if (napi) {
+		RTW_PRINT_SEL(m, "NAPI enable, weight=%d\n", weight);
+#ifdef CONFIG_RTW_NAPI_DYNAMIC
+		RTW_PRINT_SEL(m, "Dynamaic NAPI mechanism is on, current NAPI %s\n",
+			      d->en_napi_dynamic ? "enable" : "disable");
+		RTW_PRINT_SEL(m, "Dynamaic NAPI info:\n"
+				 "\ttcp_rx_threshold = %d Mbps\n"
+				 "\tcur_rx_tp = %d Mbps\n",
+			      pregistrypriv->napi_threshold,
+			      d->traffic_stat.cur_rx_tp);
+#endif /* CONFIG_RTW_NAPI_DYNAMIC */
+	} else {
+		RTW_PRINT_SEL(m, "NAPI disable\n");
+	}
+	RTW_PRINT_SEL(m, "GRO %s\n", gro?"enable":"disable");
+
+	return 0;
+
+}
+
+#ifdef CONFIG_RTW_NAPI_DYNAMIC
+static ssize_t proc_set_napi_th(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
+{
+	struct net_device *dev = data;
+	struct _ADAPTER *adapter = (struct _ADAPTER *)rtw_netdev_priv(dev);
+	struct registry_priv *registry = &adapter->registrypriv;
+	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
+	PADAPTER iface = NULL;
+	char tmp[32] = {0};
+	int thrshld = 0;
+	int num = 0, i = 0;
+
+
+	if (count < 1)
+		return -EFAULT;
+
+	if (count > sizeof(tmp)) {
+		rtw_warn_on(1);
+		return -EFAULT;
+	}
+
+	RTW_INFO("%s: Last threshold = %d Mbps\n", __FUNCTION__, registry->napi_threshold);
+
+
+	for (i = 0; i < dvobj->iface_nums; i++) {
+		iface = dvobj->padapters[i];
+		if (iface) {
+			if (buffer && !copy_from_user(tmp, buffer, count)) {
+				registry = &iface->registrypriv;
+				num = sscanf(tmp, "%d", &thrshld);
+				if (num > 0) {
+					if (thrshld > 0)
+						registry->napi_threshold = thrshld;
+				}
+			}
+		}
+	}
+	RTW_INFO("%s: New threshold = %d Mbps\n", __FUNCTION__, registry->napi_threshold);
+	RTW_INFO("%s: Current RX throughput = %d Mbps\n",
+		 __FUNCTION__, adapter_to_dvobj(adapter)->traffic_stat.cur_rx_tp);
+
+	return count;
+}
+#endif /* CONFIG_RTW_NAPI_DYNAMIC */
+
+
+ssize_t proc_set_dynamic_agg_enable(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
+{
+	struct net_device *dev = data;
+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
+	char tmp[32];
+	int enable = 0, i = 0;
+
+	if (count > sizeof(tmp)) {
+		rtw_warn_on(1);
+		return -EFAULT;
+	}
+
+	if (buffer && !copy_from_user(tmp, buffer, count)) {
+
+		struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
+		PADAPTER iface = NULL;
+		int num = sscanf(tmp, "%d", &enable);
+
+		if (num !=  1) {
+			RTW_INFO("invalid parameter!\n");
+			return count;
+		}
+
+		RTW_INFO("dynamic_agg_enable:%d\n", enable);
+
+		for (i = 0; i < dvobj->iface_nums; i++) {
+			iface = dvobj->padapters[i];
+			if (iface)
+				iface->registrypriv.dynamic_agg_enable = enable;
+		}
+
+	}
+
+	return count;
+
+}
+
+static int proc_get_dynamic_agg_enable(struct seq_file *m, void *v)
+{
+	struct net_device *dev = m->private;
+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
+	struct registry_priv *pregistrypriv = &adapter->registrypriv;
+
+	RTW_PRINT_SEL(m, "dynamic_agg_enable:%d\n", pregistrypriv->dynamic_agg_enable);
+
+	return 0;
+}
+
+#ifdef CONFIG_RTW_MESH
+static int proc_get_mesh_peer_sel_policy(struct seq_file *m, void *v)
+{
+	struct net_device *dev = m->private;
+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
+
+	dump_mesh_peer_sel_policy(m, adapter);
+
+	return 0;
+}
+
+#if CONFIG_RTW_MESH_ACNODE_PREVENT
+static int proc_get_mesh_acnode_prevent(struct seq_file *m, void *v)
+{
+	struct net_device *dev = m->private;
+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
+
+	if (MLME_IS_MESH(adapter))
+		dump_mesh_acnode_prevent_settings(m, adapter);
+
+	return 0;
+}
+
+static ssize_t proc_set_mesh_acnode_prevent(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
+{
+	struct net_device *dev = data;
+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
+	char tmp[32];
+
+	if (count < 1)
+		return -EFAULT;
+
+	if (count > sizeof(tmp)) {
+		rtw_warn_on(1);
+		return -EFAULT;
+	}
+
+	if (buffer && !copy_from_user(tmp, buffer, count)) {
+		struct mesh_peer_sel_policy *peer_sel_policy = &adapter->mesh_cfg.peer_sel_policy;
+		u8 enable;
+		u32 conf_timeout_ms;
+		u32 notify_timeout_ms;
+		int num = sscanf(tmp, "%hhu %u %u", &enable, &conf_timeout_ms, &notify_timeout_ms);
+
+		if (num >= 1)
+			peer_sel_policy->acnode_prevent = enable;
+		if (num >= 2)
+			peer_sel_policy->acnode_conf_timeout_ms = conf_timeout_ms;
+		if (num >= 3)
+			peer_sel_policy->acnode_notify_timeout_ms = notify_timeout_ms;
+	}
+
+exit:
+	return count;
+}
+#endif /* CONFIG_RTW_MESH_ACNODE_PREVENT */
+
+#if CONFIG_RTW_MESH_OFFCH_CAND
+static int proc_get_mesh_offch_cand(struct seq_file *m, void *v)
+{
+	struct net_device *dev = m->private;
+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
+
+	if (MLME_IS_MESH(adapter))
+		dump_mesh_offch_cand_settings(m, adapter);
+
+	return 0;
+}
+
+static ssize_t proc_set_mesh_offch_cand(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
+{
+	struct net_device *dev = data;
+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
+	char tmp[32];
+
+	if (count < 1)
+		return -EFAULT;
+
+	if (count > sizeof(tmp)) {
+		rtw_warn_on(1);
+		return -EFAULT;
+	}
+
+	if (buffer && !copy_from_user(tmp, buffer, count)) {
+		struct mesh_peer_sel_policy *peer_sel_policy = &adapter->mesh_cfg.peer_sel_policy;
+		u8 enable;
+		u32 find_int_ms;
+		int num = sscanf(tmp, "%hhu %u", &enable, &find_int_ms);
+
+		if (num >= 1)
+			peer_sel_policy->offch_cand = enable;
+		if (num >= 2)
+			peer_sel_policy->offch_find_int_ms = find_int_ms;
+	}
+
+exit:
+	return count;
+}
+#endif /* CONFIG_RTW_MESH_OFFCH_CAND */
+
+#if CONFIG_RTW_MESH_PEER_BLACKLIST
+static int proc_get_mesh_peer_blacklist(struct seq_file *m, void *v)
+{
+	struct net_device *dev = m->private;
+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
+
+	if (MLME_IS_MESH(adapter)) {
+		dump_mesh_peer_blacklist_settings(m, adapter);
+		if (MLME_IS_ASOC(adapter))
+			dump_mesh_peer_blacklist(m, adapter);
+	}
+
+	return 0;
+}
+
+static ssize_t proc_set_mesh_peer_blacklist(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
+{
+	struct net_device *dev = data;
+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
+	char tmp[32];
+
+	if (count < 1)
+		return -EFAULT;
+
+	if (count > sizeof(tmp)) {
+		rtw_warn_on(1);
+		return -EFAULT;
+	}
+
+	if (buffer && !copy_from_user(tmp, buffer, count)) {
+		struct mesh_peer_sel_policy *peer_sel_policy = &adapter->mesh_cfg.peer_sel_policy;
+		u32 conf_timeout_ms;
+		u32 blacklist_timeout_ms;
+		int num = sscanf(tmp, "%u %u", &conf_timeout_ms, &blacklist_timeout_ms);
+
+		if (num >= 1)
+			peer_sel_policy->peer_conf_timeout_ms = conf_timeout_ms;
+		if (num >= 2)
+			peer_sel_policy->peer_blacklist_timeout_ms = blacklist_timeout_ms;
+	}
+
+exit:
+	return count;
+}
+#endif /* CONFIG_RTW_MESH_PEER_BLACKLIST */
+
+#if CONFIG_RTW_MESH_CTO_MGATE_BLACKLIST
+static int proc_get_mesh_cto_mgate_require(struct seq_file *m, void *v)
+{
+	struct net_device *dev = m->private;
+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
+
+	if (MLME_IS_MESH(adapter))
+		RTW_PRINT_SEL(m, "%u\n", adapter->mesh_cfg.peer_sel_policy.cto_mgate_require);
+
+	return 0;
+}
+
+static ssize_t proc_set_mesh_cto_mgate_require(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
+{
+	struct net_device *dev = data;
+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
+	char tmp[32];
+
+	if (count < 1)
+		return -EFAULT;
+
+	if (count > sizeof(tmp)) {
+		rtw_warn_on(1);
+		return -EFAULT;
+	}
+
+	if (buffer && !copy_from_user(tmp, buffer, count)) {
+		struct mesh_peer_sel_policy *peer_sel_policy = &adapter->mesh_cfg.peer_sel_policy;
+		u8 require;
+		int num = sscanf(tmp, "%hhu", &require);
+
+		if (num >= 1) {
+			peer_sel_policy->cto_mgate_require = require;
+			#if CONFIG_RTW_MESH_CTO_MGATE_CARRIER
+			if (rtw_mesh_cto_mgate_required(adapter))
+				rtw_netif_carrier_off(adapter->pnetdev);
+			else
+				rtw_netif_carrier_on(adapter->pnetdev);
+			#endif
+		}
+	}
+
+exit:
+	return count;
+}
+
+static int proc_get_mesh_cto_mgate_blacklist(struct seq_file *m, void *v)
+{
+	struct net_device *dev = m->private;
+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
+
+	if (MLME_IS_MESH(adapter)) {
+		dump_mesh_cto_mgate_blacklist_settings(m, adapter);
+		if (MLME_IS_ASOC(adapter))
+			dump_mesh_cto_mgate_blacklist(m, adapter);
+	}
+
+	return 0;
+}
+
+static ssize_t proc_set_mesh_cto_mgate_blacklist(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
+{
+	struct net_device *dev = data;
+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
+	char tmp[32];
+
+	if (count < 1)
+		return -EFAULT;
+
+	if (count > sizeof(tmp)) {
+		rtw_warn_on(1);
+		return -EFAULT;
+	}
+
+	if (buffer && !copy_from_user(tmp, buffer, count)) {
+		struct mesh_peer_sel_policy *peer_sel_policy = &adapter->mesh_cfg.peer_sel_policy;
+		u32 conf_timeout_ms;
+		u32 blacklist_timeout_ms;
+		int num = sscanf(tmp, "%u %u", &conf_timeout_ms, &blacklist_timeout_ms);
+
+		if (num >= 1)
+			peer_sel_policy->cto_mgate_conf_timeout_ms = conf_timeout_ms;
+		if (num >= 2)
+			peer_sel_policy->cto_mgate_blacklist_timeout_ms = blacklist_timeout_ms;
+	}
+
+exit:
+	return count;
+}
+#endif /* CONFIG_RTW_MESH_CTO_MGATE_BLACKLIST */
+
+static int proc_get_mesh_networks(struct seq_file *m, void *v)
+{
+	struct net_device *dev = m->private;
+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
+
+	dump_mesh_networks(m, adapter);
+
+	return 0;
+}
+
+static int proc_get_mesh_plink_ctl(struct seq_file *m, void *v)
+{
+	struct net_device *dev = m->private;
+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
+
+	if (MLME_IS_MESH(adapter))
+		dump_mesh_plink_ctl(m, adapter);
+
+	return 0;
+}
+
+static int proc_get_mesh_mpp(struct seq_file *m, void *v)
+{
+	struct net_device *dev = m->private;
+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
+
+	if (MLME_IS_MESH(adapter) && MLME_IS_ASOC(adapter))
+		dump_mpp(m, adapter);
+
+	return 0;
+}
+
+static int proc_get_mesh_known_gates(struct seq_file *m, void *v)
+{
+	struct net_device *dev = m->private;
+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
+
+	if (MLME_IS_MESH(adapter))
+		dump_known_gates(m, adapter);
+
+	return 0;
+}
+
+#if CONFIG_RTW_MESH_DATA_BMC_TO_UC
+static int proc_get_mesh_b2u_flags(struct seq_file *m, void *v)
+{
+	struct net_device *dev = m->private;
+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
+
+	if (MLME_IS_MESH(adapter))
+		dump_mesh_b2u_flags(m, adapter);
+
+	return 0;
+}
+
+static ssize_t proc_set_mesh_b2u_flags(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
+{
+	struct net_device *dev = data;
+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
+	char tmp[32];
+
+	if (count < 1)
+		return -EFAULT;
+
+	if (count > sizeof(tmp)) {
+		rtw_warn_on(1);
+		return -EFAULT;
+	}
+
+	if (buffer && !copy_from_user(tmp, buffer, count)) {
+		struct rtw_mesh_cfg *mcfg = &adapter->mesh_cfg;
+		u8 msrc, mfwd;
+		int num = sscanf(tmp, "%hhx %hhx", &msrc, &mfwd);
+
+		if (num >= 1)
+			mcfg->b2u_flags_msrc = msrc;
+		if (num >= 2)
+			mcfg->b2u_flags_mfwd = mfwd;
+	}
+
+exit:
+	return count;
+}
+#endif /* CONFIG_RTW_MESH_DATA_BMC_TO_UC */
+
+static int proc_get_mesh_stats(struct seq_file *m, void *v)
+{
+	struct net_device *dev = m->private;
+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
+
+	if (MLME_IS_MESH(adapter))
+		dump_mesh_stats(m, adapter);
+
+	return 0;
+}
+
+static int proc_get_mesh_gate_timeout(struct seq_file *m, void *v)
+{
+	struct net_device *dev = m->private;
+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
+
+	if (MLME_IS_MESH(adapter))
+		RTW_PRINT_SEL(m, "%u factor\n",
+			       adapter->mesh_cfg.path_gate_timeout_factor);
+
+	return 0;
+}
+
+static ssize_t proc_set_mesh_gate_timeout(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
+{
+	struct net_device *dev = data;
+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
+	char tmp[32];
+
+	if (count < 1)
+		return -EFAULT;
+
+	if (count > sizeof(tmp)) {
+		rtw_warn_on(1);
+		return -EFAULT;
+	}
+
+	if (buffer && !copy_from_user(tmp, buffer, count)) {
+		struct rtw_mesh_cfg *mcfg = &adapter->mesh_cfg;
+		u32 timeout;
+		int num = sscanf(tmp, "%u", &timeout);
+
+		if (num < 1)
+			goto exit;
+
+		mcfg->path_gate_timeout_factor = timeout;
+	}
+
+exit:
+	return count;
+}
+
+static int proc_get_mesh_gate_state(struct seq_file *m, void *v)
+{
+	struct net_device *dev = m->private;
+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
+	struct rtw_mesh_cfg *mcfg = &adapter->mesh_cfg;
+	u8 cto_mgate = 0;
+
+	if (MLME_IS_MESH(adapter)) {
+		if (rtw_mesh_is_primary_gate(adapter))
+			RTW_PRINT_SEL(m, "PG\n");
+		else if (mcfg->dot11MeshGateAnnouncementProtocol)
+			RTW_PRINT_SEL(m, "G\n");
+		else if (rtw_mesh_gate_num(adapter))
+			RTW_PRINT_SEL(m, "C\n");
+		else
+			RTW_PRINT_SEL(m, "N\n");
+	}
+
+	return 0;
+}
+
+#endif /* CONFIG_RTW_MESH */
+
+/*
+* rtw_adapter_proc:
+* init/deinit when register/unregister net_device
+*/
+const struct rtw_proc_hdl adapter_proc_hdls[] = {
+#if RTW_SEQ_FILE_TEST
+	RTW_PROC_HDL_SEQ("seq_file_test", &seq_file_test, NULL),
+#endif
+	RTW_PROC_HDL_SSEQ("write_reg", NULL, proc_set_write_reg),
+	RTW_PROC_HDL_SSEQ("read_reg", proc_get_read_reg, proc_set_read_reg),
+	RTW_PROC_HDL_SSEQ("tx_rate_bmp", proc_get_dump_tx_rate_bmp, NULL),
+	RTW_PROC_HDL_SSEQ("adapters_status", proc_get_dump_adapters_status, NULL),
+#ifdef CONFIG_RTW_CUSTOMER_STR
+	RTW_PROC_HDL_SSEQ("customer_str", proc_get_customer_str, NULL),
+#endif
+	RTW_PROC_HDL_SSEQ("fwstate", proc_get_fwstate, NULL),
+	RTW_PROC_HDL_SSEQ("sec_info", proc_get_sec_info, NULL),
+	RTW_PROC_HDL_SSEQ("mlmext_state", proc_get_mlmext_state, NULL),
+	RTW_PROC_HDL_SSEQ("qos_option", proc_get_qos_option, NULL),
+	RTW_PROC_HDL_SSEQ("ht_option", proc_get_ht_option, NULL),
+	RTW_PROC_HDL_SSEQ("rf_info", proc_get_rf_info, NULL),
+	RTW_PROC_HDL_SSEQ("scan_param", proc_get_scan_param, proc_set_scan_param),
+	RTW_PROC_HDL_SSEQ("scan_abort", proc_get_scan_abort, NULL),
+#ifdef CONFIG_SCAN_BACKOP
+	RTW_PROC_HDL_SSEQ("backop_flags_sta", proc_get_backop_flags_sta, proc_set_backop_flags_sta),
+	#ifdef CONFIG_AP_MODE
+	RTW_PROC_HDL_SSEQ("backop_flags_ap", proc_get_backop_flags_ap, proc_set_backop_flags_ap),
+	#endif
+	#ifdef CONFIG_RTW_MESH
+	RTW_PROC_HDL_SSEQ("backop_flags_mesh", proc_get_backop_flags_mesh, proc_set_backop_flags_mesh),
+	#endif
+#endif
+#ifdef CONFIG_RTW_REPEATER_SON
+	RTW_PROC_HDL_SSEQ("rson_data", proc_get_rson_data, proc_set_rson_data),
+#endif
+	RTW_PROC_HDL_SSEQ("survey_info", proc_get_survey_info, proc_set_survey_info),
+	RTW_PROC_HDL_SSEQ("ap_info", proc_get_ap_info, NULL),
+#ifdef ROKU_PRIVATE
+	RTW_PROC_HDL_SSEQ("infra_ap", proc_get_infra_ap, NULL),
+#endif /* ROKU_PRIVATE */
+	RTW_PROC_HDL_SSEQ("trx_info", proc_get_trx_info, proc_reset_trx_info),
+	RTW_PROC_HDL_SSEQ("tx_power_offset", proc_get_tx_power_offset, proc_set_tx_power_offset),
+	RTW_PROC_HDL_SSEQ("rate_ctl", proc_get_rate_ctl, proc_set_rate_ctl),
+	RTW_PROC_HDL_SSEQ("bw_ctl", proc_get_bw_ctl, proc_set_bw_ctl),
+	RTW_PROC_HDL_SSEQ("mac_qinfo", proc_get_mac_qinfo, NULL),
+	RTW_PROC_HDL_SSEQ("macid_info", proc_get_macid_info, NULL),
+	RTW_PROC_HDL_SSEQ("bcmc_info", proc_get_mi_ap_bc_info, NULL),
+	RTW_PROC_HDL_SSEQ("sec_cam", proc_get_sec_cam, proc_set_sec_cam),
+	RTW_PROC_HDL_SSEQ("sec_cam_cache", proc_get_sec_cam_cache, NULL),
+	RTW_PROC_HDL_SSEQ("ps_dbg_info", proc_get_ps_dbg_info, proc_set_ps_dbg_info),
+	RTW_PROC_HDL_SSEQ("wifi_spec", proc_get_wifi_spec, NULL),
+#ifdef CONFIG_LAYER2_ROAMING
+	RTW_PROC_HDL_SSEQ("roam_flags", proc_get_roam_flags, proc_set_roam_flags),
+	RTW_PROC_HDL_SSEQ("roam_param", proc_get_roam_param, proc_set_roam_param),
+	RTW_PROC_HDL_SSEQ("roam_tgt_addr", NULL, proc_set_roam_tgt_addr),
+#endif /* CONFIG_LAYER2_ROAMING */
+
+#ifdef CONFIG_RTW_80211R
+	RTW_PROC_HDL_SSEQ("ft_flags", proc_get_ft_flags, proc_set_ft_flags),
+#endif
+
+#ifdef CONFIG_SDIO_HCI
+	RTW_PROC_HDL_SSEQ("sd_f0_reg_dump", proc_get_sd_f0_reg_dump, NULL),
+	RTW_PROC_HDL_SSEQ("sdio_local_reg_dump", proc_get_sdio_local_reg_dump, NULL),
+	RTW_PROC_HDL_SSEQ("sdio_card_info", proc_get_sdio_card_info, NULL),
+#endif /* CONFIG_SDIO_HCI */
+
+	RTW_PROC_HDL_SSEQ("fwdl_test_case", NULL, proc_set_fwdl_test_case),
+	RTW_PROC_HDL_SSEQ("del_rx_ampdu_test_case", NULL, proc_set_del_rx_ampdu_test_case),
+	RTW_PROC_HDL_SSEQ("wait_hiq_empty", NULL, proc_set_wait_hiq_empty),
+	RTW_PROC_HDL_SSEQ("sta_linking_test", NULL, proc_set_sta_linking_test),
+#ifdef CONFIG_AP_MODE
+	RTW_PROC_HDL_SSEQ("ap_linking_test", NULL, proc_set_ap_linking_test),
+#endif
+
+	RTW_PROC_HDL_SSEQ("mac_reg_dump", proc_get_mac_reg_dump, NULL),
+	RTW_PROC_HDL_SSEQ("bb_reg_dump", proc_get_bb_reg_dump, NULL),
+	RTW_PROC_HDL_SSEQ("bb_reg_dump_ex", proc_get_bb_reg_dump_ex, NULL),
+	RTW_PROC_HDL_SSEQ("rf_reg_dump", proc_get_rf_reg_dump, NULL),
+
+#ifdef CONFIG_RTW_LED
+	RTW_PROC_HDL_SSEQ("led_config", proc_get_led_config, proc_set_led_config),
+#endif
+
+#ifdef CONFIG_AP_MODE
+	RTW_PROC_HDL_SSEQ("aid_status", proc_get_aid_status, proc_set_aid_status),
+	RTW_PROC_HDL_SSEQ("all_sta_info", proc_get_all_sta_info, NULL),
+	RTW_PROC_HDL_SSEQ("bmc_tx_rate", proc_get_bmc_tx_rate, proc_set_bmc_tx_rate),
+#endif /* CONFIG_AP_MODE */
+
+#ifdef DBG_MEMORY_LEAK
+	RTW_PROC_HDL_SSEQ("_malloc_cnt", proc_get_malloc_cnt, NULL),
+#endif /* DBG_MEMORY_LEAK */
+
+#ifdef CONFIG_FIND_BEST_CHANNEL
+	RTW_PROC_HDL_SSEQ("best_channel", proc_get_best_channel, proc_set_best_channel),
+#endif
+
+	RTW_PROC_HDL_SSEQ("rx_signal", proc_get_rx_signal, proc_set_rx_signal),
+	RTW_PROC_HDL_SSEQ("hw_info", proc_get_hw_status, proc_set_hw_status),
+	RTW_PROC_HDL_SSEQ("mac_rptbuf", proc_get_mac_rptbuf, NULL),
+#ifdef CONFIG_80211N_HT
+	RTW_PROC_HDL_SSEQ("ht_enable", proc_get_ht_enable, proc_set_ht_enable),
+	RTW_PROC_HDL_SSEQ("bw_mode", proc_get_bw_mode, proc_set_bw_mode),
+	RTW_PROC_HDL_SSEQ("ampdu_enable", proc_get_ampdu_enable, proc_set_ampdu_enable),
+	RTW_PROC_HDL_SSEQ("rx_ampdu", proc_get_rx_ampdu, proc_set_rx_ampdu),
+	RTW_PROC_HDL_SSEQ("rx_ampdu_size_limit", proc_get_rx_ampdu_size_limit, proc_set_rx_ampdu_size_limit),
+	RTW_PROC_HDL_SSEQ("rx_ampdu_factor", proc_get_rx_ampdu_factor, proc_set_rx_ampdu_factor),
+	RTW_PROC_HDL_SSEQ("rx_ampdu_density", proc_get_rx_ampdu_density, proc_set_rx_ampdu_density),
+	RTW_PROC_HDL_SSEQ("tx_ampdu_density", proc_get_tx_ampdu_density, proc_set_tx_ampdu_density),
+	RTW_PROC_HDL_SSEQ("tx_max_agg_num", proc_get_tx_max_agg_num, proc_set_tx_max_agg_num),
+#ifdef CONFIG_TX_AMSDU
+	RTW_PROC_HDL_SSEQ("tx_amsdu", proc_get_tx_amsdu, proc_set_tx_amsdu),
+	RTW_PROC_HDL_SSEQ("tx_amsdu_rate", proc_get_tx_amsdu_rate, proc_set_tx_amsdu_rate),
+#endif
+#endif /* CONFIG_80211N_HT */
+
+	RTW_PROC_HDL_SSEQ("en_fwps", proc_get_en_fwps, proc_set_en_fwps),
+
+	/* RTW_PROC_HDL_SSEQ("path_rssi", proc_get_two_path_rssi, NULL),
+	* 	RTW_PROC_HDL_SSEQ("rssi_disp",proc_get_rssi_disp, proc_set_rssi_disp), */
+
+#ifdef CONFIG_BT_COEXIST
+	RTW_PROC_HDL_SSEQ("btcoex_dbg", proc_get_btcoex_dbg, proc_set_btcoex_dbg),
+	RTW_PROC_HDL_SSEQ("btcoex", proc_get_btcoex_info, NULL),
+	RTW_PROC_HDL_SSEQ("btinfo_evt", NULL, proc_set_btinfo_evt),
+	RTW_PROC_HDL_SSEQ("btreg_read", proc_get_btreg_read, proc_set_btreg_read),
+	RTW_PROC_HDL_SSEQ("btreg_write", proc_get_btreg_write, proc_set_btreg_write),
+#ifdef CONFIG_RF4CE_COEXIST
+	RTW_PROC_HDL_SSEQ("rf4ce_state", proc_get_rf4ce_state, proc_set_rf4ce_state),
+#endif
+#endif /* CONFIG_BT_COEXIST */
+
+#if defined(DBG_CONFIG_ERROR_DETECT)
+	RTW_PROC_HDL_SSEQ("sreset", proc_get_sreset, proc_set_sreset),
+#endif /* DBG_CONFIG_ERROR_DETECT */
+	RTW_PROC_HDL_SSEQ("trx_info_debug", proc_get_trx_info_debug, NULL),
+
+#ifdef CONFIG_HUAWEI_PROC
+	RTW_PROC_HDL_SSEQ("huawei_trx_info", proc_get_huawei_trx_info, NULL),
+#endif
+	RTW_PROC_HDL_SSEQ("linked_info_dump", proc_get_linked_info_dump, proc_set_linked_info_dump),
+	RTW_PROC_HDL_SSEQ("sta_tp_dump", proc_get_sta_tp_dump, proc_set_sta_tp_dump),
+	RTW_PROC_HDL_SSEQ("sta_tp_info", proc_get_sta_tp_info, NULL),
+	RTW_PROC_HDL_SSEQ("dis_turboedca", proc_get_turboedca_ctrl, proc_set_turboedca_ctrl),
+	RTW_PROC_HDL_SSEQ("tx_info_msg", proc_get_tx_info_msg, NULL),
+	RTW_PROC_HDL_SSEQ("rx_info_msg", proc_get_rx_info_msg, proc_set_rx_info_msg),
+
+#ifdef CONFIG_GPIO_API
+	RTW_PROC_HDL_SSEQ("gpio_info", proc_get_gpio, proc_set_gpio),
+	RTW_PROC_HDL_SSEQ("gpio_set_output_value", NULL, proc_set_gpio_output_value),
+	RTW_PROC_HDL_SSEQ("gpio_set_direction", NULL, proc_set_config_gpio),
+#endif
+
+#ifdef CONFIG_DBG_COUNTER
+	RTW_PROC_HDL_SSEQ("rx_logs", proc_get_rx_logs, NULL),
+	RTW_PROC_HDL_SSEQ("tx_logs", proc_get_tx_logs, NULL),
+	RTW_PROC_HDL_SSEQ("int_logs", proc_get_int_logs, NULL),
+#endif
+
+#ifdef CONFIG_DBG_RF_CAL
+	RTW_PROC_HDL_SSEQ("iqk", proc_get_iqk_info, proc_set_iqk),
+	RTW_PROC_HDL_SSEQ("lck", proc_get_lck_info, proc_set_lck),
+#endif
+
+#ifdef CONFIG_PCI_HCI
+	RTW_PROC_HDL_SSEQ("rx_ring", proc_get_rx_ring, NULL),
+	RTW_PROC_HDL_SSEQ("tx_ring", proc_get_tx_ring, NULL),
+#ifdef DBG_TXBD_DESC_DUMP
+	RTW_PROC_HDL_SSEQ("tx_ring_ext", proc_get_tx_ring_ext, proc_set_tx_ring_ext),
+#endif
+	RTW_PROC_HDL_SSEQ("pci_aspm", proc_get_pci_aspm, NULL),
+
+	RTW_PROC_HDL_SSEQ("pci_conf_space", proc_get_pci_conf_space, proc_set_pci_conf_space),
+
+	RTW_PROC_HDL_SSEQ("pci_bridge_conf_space", proc_get_pci_bridge_conf_space, proc_set_pci_bridge_conf_space),
+
+#endif
+
+#ifdef CONFIG_WOWLAN
+	RTW_PROC_HDL_SSEQ("wow_pattern_info", proc_get_pattern_info, proc_set_pattern_info),
+	RTW_PROC_HDL_SSEQ("wow_wakeup_event", proc_get_wakeup_event,
+			  proc_set_wakeup_event),
+	RTW_PROC_HDL_SSEQ("wowlan_last_wake_reason", proc_get_wakeup_reason, NULL),
+#ifdef CONFIG_WOW_PATTERN_HW_CAM
+	RTW_PROC_HDL_SSEQ("wow_pattern_cam", proc_dump_pattern_cam, NULL),
+#endif
+	RTW_PROC_HDL_SSEQ("dis_wow_lps", proc_get_wow_lps_ctrl, proc_set_wow_lps_ctrl),
+#endif
+
+#ifdef CONFIG_GPIO_WAKEUP
+	RTW_PROC_HDL_SSEQ("wowlan_gpio_info", proc_get_wowlan_gpio_info, proc_set_wowlan_gpio_info),
+#endif
+#ifdef CONFIG_P2P_WOWLAN
+	RTW_PROC_HDL_SSEQ("p2p_wowlan_info", proc_get_p2p_wowlan_info, NULL),
+#endif
+	RTW_PROC_HDL_SSEQ("country_code", proc_get_country_code, proc_set_country_code),
+	RTW_PROC_HDL_SSEQ("chan_plan", proc_get_chan_plan, proc_set_chan_plan),
+#if CONFIG_RTW_MACADDR_ACL
+	RTW_PROC_HDL_SSEQ("macaddr_acl", proc_get_macaddr_acl, proc_set_macaddr_acl),
+#endif
+#if CONFIG_RTW_PRE_LINK_STA
+	RTW_PROC_HDL_SSEQ("pre_link_sta", proc_get_pre_link_sta, proc_set_pre_link_sta),
+#endif
+	RTW_PROC_HDL_SSEQ("ch_sel_policy", proc_get_ch_sel_policy, proc_set_ch_sel_policy),
+#ifdef CONFIG_DFS_MASTER
+	RTW_PROC_HDL_SSEQ("dfs_test_case", proc_get_dfs_test_case, proc_set_dfs_test_case),
+	RTW_PROC_HDL_SSEQ("update_non_ocp", NULL, proc_set_update_non_ocp),
+	RTW_PROC_HDL_SSEQ("radar_detect", NULL, proc_set_radar_detect),
+	RTW_PROC_HDL_SSEQ("dfs_ch_sel_d_flags", proc_get_dfs_ch_sel_d_flags, proc_set_dfs_ch_sel_d_flags),
+	#ifdef CONFIG_DFS_SLAVE_WITH_RADAR_DETECT
+	RTW_PROC_HDL_SSEQ("dfs_slave_with_rd", proc_get_dfs_slave_with_rd, proc_set_dfs_slave_with_rd),
+	#endif
+#endif
+#ifdef CONFIG_BCN_CNT_CONFIRM_HDL
+	RTW_PROC_HDL_SSEQ("new_bcn_max", proc_get_new_bcn_max, proc_set_new_bcn_max),
+#endif
+	RTW_PROC_HDL_SSEQ("sink_udpport", proc_get_udpport, proc_set_udpport),
+#ifdef DBG_RX_COUNTER_DUMP
+	RTW_PROC_HDL_SSEQ("dump_rx_cnt_mode", proc_get_rx_cnt_dump, proc_set_rx_cnt_dump),
+#endif
+	RTW_PROC_HDL_SSEQ("change_bss_chbw", NULL, proc_set_change_bss_chbw),
+	RTW_PROC_HDL_SSEQ("tx_bw_mode", proc_get_tx_bw_mode, proc_set_tx_bw_mode),
+	RTW_PROC_HDL_SSEQ("hal_txpwr_info", proc_get_hal_txpwr_info, NULL),
+	RTW_PROC_HDL_SSEQ("target_tx_power", proc_get_target_tx_power, NULL),
+	RTW_PROC_HDL_SSEQ("tx_power_by_rate", proc_get_tx_power_by_rate, NULL),
+#ifdef CONFIG_TXPWR_LIMIT
+	RTW_PROC_HDL_SSEQ("tx_power_limit", proc_get_tx_power_limit, NULL),
+#endif
+	RTW_PROC_HDL_SSEQ("tx_power_ext_info", proc_get_tx_power_ext_info, proc_set_tx_power_ext_info),
+	RTW_PROC_HDL_SEQ("tx_power_idx", &seq_ops_tx_power_idx, NULL),
+#ifdef CONFIG_RF_POWER_TRIM
+	RTW_PROC_HDL_SSEQ("tx_gain_offset", NULL, proc_set_tx_gain_offset),
+	RTW_PROC_HDL_SSEQ("kfree_flag", proc_get_kfree_flag, proc_set_kfree_flag),
+	RTW_PROC_HDL_SSEQ("kfree_bb_gain", proc_get_kfree_bb_gain, proc_set_kfree_bb_gain),
+	RTW_PROC_HDL_SSEQ("kfree_thermal", proc_get_kfree_thermal, proc_set_kfree_thermal),
+#endif
+#ifdef CONFIG_POWER_SAVING
+	RTW_PROC_HDL_SSEQ("ps_info", proc_get_ps_info, NULL),
+#ifdef CONFIG_WMMPS_STA
+	RTW_PROC_HDL_SSEQ("wmmps_info", proc_get_wmmps_info, proc_set_wmmps_info),
+#endif /* CONFIG_WMMPS_STA */
+#endif
+#ifdef CONFIG_TDLS
+	RTW_PROC_HDL_SSEQ("tdls_info", proc_get_tdls_info, NULL),
+	RTW_PROC_HDL_SSEQ("tdls_enable", proc_get_tdls_enable, proc_set_tdls_enable),
+#endif
+	RTW_PROC_HDL_SSEQ("monitor", proc_get_monitor, proc_set_monitor),
+
+#ifdef CONFIG_RTW_ACS
+	RTW_PROC_HDL_SSEQ("acs", proc_get_best_chan, proc_set_acs),
+	RTW_PROC_HDL_SSEQ("chan_info", proc_get_chan_info, NULL),
+#endif
+
+#ifdef CONFIG_BACKGROUND_NOISE_MONITOR
+	RTW_PROC_HDL_SSEQ("noise_monitor", proc_get_nm, proc_set_nm),
+#endif
+
+#ifdef CONFIG_PREALLOC_RX_SKB_BUFFER
+	RTW_PROC_HDL_SSEQ("rtkm_info", proc_get_rtkm_info, NULL),
+#endif
+	RTW_PROC_HDL_SSEQ("efuse_map", proc_get_efuse_map, NULL),
+#ifdef CONFIG_IEEE80211W
+	RTW_PROC_HDL_SSEQ("11w_tx_sa_query", proc_get_tx_sa_query, proc_set_tx_sa_query),
+	RTW_PROC_HDL_SSEQ("11w_tx_deauth", proc_get_tx_deauth, proc_set_tx_deauth),
+	RTW_PROC_HDL_SSEQ("11w_tx_auth", proc_get_tx_auth, proc_set_tx_auth),
+#endif /* CONFIG_IEEE80211W */
+
+#ifdef CONFIG_MBSSID_CAM
+	RTW_PROC_HDL_SSEQ("mbid_cam", proc_get_mbid_cam_cache, NULL),
+#endif
+	RTW_PROC_HDL_SSEQ("mac_addr", proc_get_mac_addr, NULL),
+	RTW_PROC_HDL_SSEQ("skip_band", proc_get_skip_band, proc_set_skip_band),
+	RTW_PROC_HDL_SSEQ("hal_spec", proc_get_hal_spec, NULL),
+
+	RTW_PROC_HDL_SSEQ("rx_stat", proc_get_rx_stat, NULL),
+
+	RTW_PROC_HDL_SSEQ("tx_stat", proc_get_tx_stat, NULL),
+	/**** PHY Capability ****/
+	RTW_PROC_HDL_SSEQ("phy_cap", proc_get_phy_cap, NULL),
+#ifdef CONFIG_80211N_HT
+	RTW_PROC_HDL_SSEQ("rx_stbc", proc_get_rx_stbc, proc_set_rx_stbc),
+	RTW_PROC_HDL_SSEQ("stbc_cap", proc_get_stbc_cap, proc_set_stbc_cap),
+	RTW_PROC_HDL_SSEQ("ldpc_cap", proc_get_ldpc_cap, proc_set_ldpc_cap),
+#endif /* CONFIG_80211N_HT */
+#ifdef CONFIG_BEAMFORMING
+	RTW_PROC_HDL_SSEQ("txbf_cap", proc_get_txbf_cap, proc_set_txbf_cap),
+#endif
+
+#ifdef CONFIG_SUPPORT_TRX_SHARED
+	RTW_PROC_HDL_SSEQ("trx_share_mode", proc_get_trx_share_mode, NULL),
+#endif
+	RTW_PROC_HDL_SSEQ("napi_info", proc_get_napi_info, NULL),
+#ifdef CONFIG_RTW_NAPI_DYNAMIC
+	RTW_PROC_HDL_SSEQ("napi_th", proc_get_napi_info, proc_set_napi_th),
+#endif /* CONFIG_RTW_NAPI_DYNAMIC */
+
+	RTW_PROC_HDL_SSEQ("rsvd_page", proc_dump_rsvd_page, proc_set_rsvd_page_info),
+
+#ifdef CONFIG_SUPPORT_FIFO_DUMP
+	RTW_PROC_HDL_SSEQ("fifo_dump", proc_dump_fifo, proc_set_fifo_info),
+#endif
+	RTW_PROC_HDL_SSEQ("fw_info", proc_get_fw_info, NULL),
+
+#ifdef DBG_XMIT_BLOCK
+	RTW_PROC_HDL_SSEQ("xmit_block", proc_get_xmit_block, proc_set_xmit_block),
+#endif
+
+	RTW_PROC_HDL_SSEQ("ack_timeout", proc_get_ack_timeout, proc_set_ack_timeout),
+
+	RTW_PROC_HDL_SSEQ("dynamic_agg_enable", proc_get_dynamic_agg_enable, proc_set_dynamic_agg_enable),
+	RTW_PROC_HDL_SSEQ("fw_offload", proc_get_fw_offload, proc_set_fw_offload),
+
+#ifdef CONFIG_RTW_MESH
+	#if CONFIG_RTW_MESH_ACNODE_PREVENT
+	RTW_PROC_HDL_SSEQ("mesh_acnode_prevent", proc_get_mesh_acnode_prevent, proc_set_mesh_acnode_prevent),
+	#endif
+	#if CONFIG_RTW_MESH_OFFCH_CAND
+	RTW_PROC_HDL_SSEQ("mesh_offch_cand", proc_get_mesh_offch_cand, proc_set_mesh_offch_cand),
+	#endif
+	#if CONFIG_RTW_MESH_PEER_BLACKLIST
+	RTW_PROC_HDL_SSEQ("mesh_peer_blacklist", proc_get_mesh_peer_blacklist, proc_set_mesh_peer_blacklist),
+	#endif
+	#if CONFIG_RTW_MESH_CTO_MGATE_BLACKLIST
+	RTW_PROC_HDL_SSEQ("mesh_cto_mgate_require", proc_get_mesh_cto_mgate_require, proc_set_mesh_cto_mgate_require),
+	RTW_PROC_HDL_SSEQ("mesh_cto_mgate_blacklist", proc_get_mesh_cto_mgate_blacklist, proc_set_mesh_cto_mgate_blacklist),
+	#endif
+	RTW_PROC_HDL_SSEQ("mesh_peer_sel_policy", proc_get_mesh_peer_sel_policy, NULL),
+	RTW_PROC_HDL_SSEQ("mesh_networks", proc_get_mesh_networks, NULL),
+	RTW_PROC_HDL_SSEQ("mesh_plink_ctl", proc_get_mesh_plink_ctl, NULL),
+	RTW_PROC_HDL_SSEQ("mesh_mpp", proc_get_mesh_mpp, NULL),
+	RTW_PROC_HDL_SSEQ("mesh_known_gates", proc_get_mesh_known_gates, NULL),
+	#if CONFIG_RTW_MESH_DATA_BMC_TO_UC
+	RTW_PROC_HDL_SSEQ("mesh_b2u_flags", proc_get_mesh_b2u_flags, proc_set_mesh_b2u_flags),
+	#endif
+	RTW_PROC_HDL_SSEQ("mesh_stats", proc_get_mesh_stats, NULL),
+	RTW_PROC_HDL_SSEQ("mesh_gate_timeout_factor", proc_get_mesh_gate_timeout, proc_set_mesh_gate_timeout),
+	RTW_PROC_HDL_SSEQ("mesh_gate_state", proc_get_mesh_gate_state, NULL),
+#endif
+#ifdef CONFIG_FW_HANDLE_TXBCN
+	RTW_PROC_HDL_SSEQ("fw_tbtt_rpt", proc_get_fw_tbtt_rpt, proc_set_fw_tbtt_rpt),
+#endif
+#ifdef CONFIG_LPS_CHK_BY_TP
+	RTW_PROC_HDL_SSEQ("lps_chk_tp", proc_get_lps_chk_tp, proc_set_lps_chk_tp),
+#endif
+
+};
+
+const int adapter_proc_hdls_num = sizeof(adapter_proc_hdls) / sizeof(struct rtw_proc_hdl);
+
+static int rtw_adapter_proc_open(struct inode *inode, struct file *file)
+{
+	ssize_t index = (ssize_t)PDE_DATA(inode);
+	const struct rtw_proc_hdl *hdl = adapter_proc_hdls + index;
+	void *private = proc_get_parent_data(inode);
+
+	if (hdl->type == RTW_PROC_HDL_TYPE_SEQ) {
+		int res = seq_open(file, hdl->u.seq_op);
+
+		if (res == 0)
+			((struct seq_file *)file->private_data)->private = private;
+
+		return res;
+	} else if (hdl->type == RTW_PROC_HDL_TYPE_SSEQ) {
+		int (*show)(struct seq_file *, void *) = hdl->u.show ? hdl->u.show : proc_get_dummy;
+
+		return single_open(file, show, private);
+	} else {
+		return -EROFS;
+	}
+}
+
+static ssize_t rtw_adapter_proc_write(struct file *file, const char __user *buffer, size_t count, loff_t *pos)
+{
+	ssize_t index = (ssize_t)PDE_DATA(file_inode(file));
+	const struct rtw_proc_hdl *hdl = adapter_proc_hdls + index;
+	ssize_t (*write)(struct file *, const char __user *, size_t, loff_t *, void *) = hdl->write;
+
+	if (write)
+		return write(file, buffer, count, pos, ((struct seq_file *)file->private_data)->private);
+
+	return -EROFS;
+}
+
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 6, 0))
+static const struct file_operations rtw_adapter_proc_seq_fops = {
+	.owner = THIS_MODULE,
+	.open = rtw_adapter_proc_open,
+	.read = seq_read,
+	.llseek = seq_lseek,
+	.release = seq_release,
+	.write = rtw_adapter_proc_write,
+};
+
+static const struct file_operations rtw_adapter_proc_sseq_fops = {
+	.owner = THIS_MODULE,
+	.open = rtw_adapter_proc_open,
+	.read = seq_read,
+	.llseek = seq_lseek,
+	.release = single_release,
+	.write = rtw_adapter_proc_write,
+};
+#else
+static const struct proc_ops rtw_adapter_proc_seq_fops = {
+	.proc_open = rtw_adapter_proc_open,
+	.proc_read = seq_read,
+	.proc_lseek = seq_lseek,
+	.proc_release = seq_release,
+	.proc_write = rtw_adapter_proc_write,
+};
+
+static const struct proc_ops rtw_adapter_proc_sseq_fops = {
+	.proc_open = rtw_adapter_proc_open,
+	.proc_read = seq_read,
+	.proc_lseek = seq_lseek,
+	.proc_release = single_release,
+	.proc_write = rtw_adapter_proc_write,
+};
+#endif
+
+int proc_get_odm_adaptivity(struct seq_file *m, void *v)
+{
+	struct net_device *dev = m->private;
+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
+
+	rtw_odm_adaptivity_parm_msg(m, padapter);
+
+	return 0;
+}
+
+ssize_t proc_set_odm_adaptivity(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
+{
+	struct net_device *dev = data;
+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
+	char tmp[32];
+	u32 th_l2h_ini;
+	s8 th_edcca_hl_diff;
+
+	if (count < 1)
+		return -EFAULT;
+
+	if (count > sizeof(tmp)) {
+		rtw_warn_on(1);
+		return -EFAULT;
+	}
+
+	if (buffer && !copy_from_user(tmp, buffer, count)) {
+
+		int num = sscanf(tmp, "%x %hhd", &th_l2h_ini, &th_edcca_hl_diff);
+
+		if (num != 2)
+			return count;
+
+		rtw_odm_adaptivity_parm_set(padapter, (s8)th_l2h_ini, th_edcca_hl_diff);
+	}
+
+	return count;
+}
+
+static char *phydm_msg = NULL;
+#define PHYDM_MSG_LEN	80*24
+
+int proc_get_phydm_cmd(struct seq_file *m, void *v)
+{
+	struct net_device *netdev;
+	PADAPTER padapter;
+	struct dm_struct *phydm;
+
+
+	netdev = m->private;
+	padapter = (PADAPTER)rtw_netdev_priv(netdev);
+	phydm = adapter_to_phydm(padapter);
+
+	if (NULL == phydm_msg) {
+		phydm_msg = rtw_zmalloc(PHYDM_MSG_LEN);
+		if (NULL == phydm_msg)
+			return -ENOMEM;
+
+		phydm_cmd(phydm, NULL, 0, 0, phydm_msg, PHYDM_MSG_LEN);
+	}
+
+	_RTW_PRINT_SEL(m, "%s\n", phydm_msg);
+
+	rtw_mfree(phydm_msg, PHYDM_MSG_LEN);
+	phydm_msg = NULL;
+
+	return 0;
+}
+
+ssize_t proc_set_phydm_cmd(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
+{
+	struct net_device *netdev;
+	PADAPTER padapter;
+	struct dm_struct *phydm;
+	char tmp[64] = {0};
+
+
+	netdev = (struct net_device *)data;
+	padapter = (PADAPTER)rtw_netdev_priv(netdev);
+	phydm = adapter_to_phydm(padapter);
+
+	if (count < 1)
+		return -EFAULT;
+
+	if (count > sizeof(tmp))
+		return -EFAULT;
+
+	if (buffer && !copy_from_user(tmp, buffer, count)) {
+		if (NULL == phydm_msg) {
+			phydm_msg = rtw_zmalloc(PHYDM_MSG_LEN);
+			if (NULL == phydm_msg)
+				return -ENOMEM;
+		} else
+			_rtw_memset(phydm_msg, 0, PHYDM_MSG_LEN);
+
+		phydm_cmd(phydm, tmp, count, 1, phydm_msg, PHYDM_MSG_LEN);
+
+		if (strlen(phydm_msg) == 0) {
+			rtw_mfree(phydm_msg, PHYDM_MSG_LEN);
+			phydm_msg = NULL;
+		}
+	}
+
+	return count;
+}
+
+/*
+* rtw_odm_proc:
+* init/deinit when register/unregister net_device, along with rtw_adapter_proc
+*/
+const struct rtw_proc_hdl odm_proc_hdls[] = {
+	RTW_PROC_HDL_SSEQ("adaptivity", proc_get_odm_adaptivity, proc_set_odm_adaptivity),
+	RTW_PROC_HDL_SSEQ("cmd", proc_get_phydm_cmd, proc_set_phydm_cmd),
+};
+
+const int odm_proc_hdls_num = sizeof(odm_proc_hdls) / sizeof(struct rtw_proc_hdl);
+
+static int rtw_odm_proc_open(struct inode *inode, struct file *file)
+{
+	ssize_t index = (ssize_t)PDE_DATA(inode);
+	const struct rtw_proc_hdl *hdl = odm_proc_hdls + index;
+	void *private = proc_get_parent_data(inode);
+
+	if (hdl->type == RTW_PROC_HDL_TYPE_SEQ) {
+		int res = seq_open(file, hdl->u.seq_op);
+
+		if (res == 0)
+			((struct seq_file *)file->private_data)->private = private;
+
+		return res;
+	} else if (hdl->type == RTW_PROC_HDL_TYPE_SSEQ) {
+		int (*show)(struct seq_file *, void *) = hdl->u.show ? hdl->u.show : proc_get_dummy;
+
+		return single_open(file, show, private);
+	} else {
+		return -EROFS;
+	}
+}
+
+static ssize_t rtw_odm_proc_write(struct file *file, const char __user *buffer, size_t count, loff_t *pos)
+{
+	ssize_t index = (ssize_t)PDE_DATA(file_inode(file));
+	const struct rtw_proc_hdl *hdl = odm_proc_hdls + index;
+	ssize_t (*write)(struct file *, const char __user *, size_t, loff_t *, void *) = hdl->write;
+
+	if (write)
+		return write(file, buffer, count, pos, ((struct seq_file *)file->private_data)->private);
+
+	return -EROFS;
+}
+
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 6, 0))
+static const struct file_operations rtw_odm_proc_seq_fops = {
+	.owner = THIS_MODULE,
+	.open = rtw_odm_proc_open,
+	.read = seq_read,
+	.llseek = seq_lseek,
+	.release = seq_release,
+	.write = rtw_odm_proc_write,
+};
+
+static const struct file_operations rtw_odm_proc_sseq_fops = {
+	.owner = THIS_MODULE,
+	.open = rtw_odm_proc_open,
+	.read = seq_read,
+	.llseek = seq_lseek,
+	.release = single_release,
+	.write = rtw_odm_proc_write,
+};
+#else
+static const struct proc_ops rtw_odm_proc_seq_fops = {
+	.proc_open = rtw_odm_proc_open,
+	.proc_read = seq_read,
+	.proc_lseek = seq_lseek,
+	.proc_release = seq_release,
+	.proc_write = rtw_odm_proc_write,
+};
+
+static const struct proc_ops rtw_odm_proc_sseq_fops = {
+	.proc_open = rtw_odm_proc_open,
+	.proc_read = seq_read,
+	.proc_lseek = seq_lseek,
+	.proc_release = single_release,
+	.proc_write = rtw_odm_proc_write,
+};
+#endif
+
+struct proc_dir_entry *rtw_odm_proc_init(struct net_device *dev)
+{
+	struct proc_dir_entry *dir_odm = NULL;
+	struct proc_dir_entry *entry = NULL;
+	_adapter	*adapter = rtw_netdev_priv(dev);
+	ssize_t i;
+
+	if (adapter->dir_dev == NULL) {
+		rtw_warn_on(1);
+		goto exit;
+	}
+
+	if (adapter->dir_odm != NULL) {
+		rtw_warn_on(1);
+		goto exit;
+	}
+
+	dir_odm = rtw_proc_create_dir("odm", adapter->dir_dev, dev);
+	if (dir_odm == NULL) {
+		rtw_warn_on(1);
+		goto exit;
+	}
+
+	adapter->dir_odm = dir_odm;
+
+	for (i = 0; i < odm_proc_hdls_num; i++) {
+		if (odm_proc_hdls[i].type == RTW_PROC_HDL_TYPE_SEQ)
+			entry = rtw_proc_create_entry(odm_proc_hdls[i].name, dir_odm, &rtw_odm_proc_seq_fops, (void *)i);
+		else if (odm_proc_hdls[i].type == RTW_PROC_HDL_TYPE_SSEQ)
+			entry = rtw_proc_create_entry(odm_proc_hdls[i].name, dir_odm, &rtw_odm_proc_sseq_fops, (void *)i);
+		else
+			entry = NULL;
+
+		if (!entry) {
+			rtw_warn_on(1);
+			goto exit;
+		}
+	}
+
+exit:
+	return dir_odm;
+}
+
+void rtw_odm_proc_deinit(_adapter	*adapter)
+{
+	struct proc_dir_entry *dir_odm = NULL;
+	int i;
+
+	dir_odm = adapter->dir_odm;
+
+	if (dir_odm == NULL) {
+		rtw_warn_on(1);
+		return;
+	}
+
+	for (i = 0; i < odm_proc_hdls_num; i++)
+		remove_proc_entry(odm_proc_hdls[i].name, dir_odm);
+
+	remove_proc_entry("odm", adapter->dir_dev);
+
+	adapter->dir_odm = NULL;
+
+	if (phydm_msg) {
+		rtw_mfree(phydm_msg, PHYDM_MSG_LEN);
+		phydm_msg = NULL;
+	}
+}
+
+#ifdef CONFIG_MCC_MODE
+/*
+* rtw_mcc_proc:
+* init/deinit when register/unregister net_device, along with rtw_adapter_proc
+*/
+const struct rtw_proc_hdl mcc_proc_hdls[] = {
+	RTW_PROC_HDL_SSEQ("mcc_info", proc_get_mcc_info, NULL),
+	RTW_PROC_HDL_SSEQ("mcc_enable", proc_get_mcc_info, proc_set_mcc_enable),
+	RTW_PROC_HDL_SSEQ("mcc_duration", proc_get_mcc_info, proc_set_mcc_duration),
+	RTW_PROC_HDL_SSEQ("mcc_single_tx_criteria", proc_get_mcc_info, proc_set_mcc_single_tx_criteria),
+	RTW_PROC_HDL_SSEQ("mcc_ap_bw20_target_tp", proc_get_mcc_info, proc_set_mcc_ap_bw20_target_tp),
+	RTW_PROC_HDL_SSEQ("mcc_ap_bw40_target_tp", proc_get_mcc_info, proc_set_mcc_ap_bw40_target_tp),
+	RTW_PROC_HDL_SSEQ("mcc_ap_bw80_target_tp", proc_get_mcc_info, proc_set_mcc_ap_bw80_target_tp),
+	RTW_PROC_HDL_SSEQ("mcc_sta_bw20_target_tp", proc_get_mcc_info, proc_set_mcc_sta_bw20_target_tp),
+	RTW_PROC_HDL_SSEQ("mcc_sta_bw40_target_tp", proc_get_mcc_info, proc_set_mcc_sta_bw40_target_tp),
+	RTW_PROC_HDL_SSEQ("mcc_sta_bw80_target_tp", proc_get_mcc_info, proc_set_mcc_sta_bw80_target_tp),
+	RTW_PROC_HDL_SSEQ("mcc_policy_table", proc_get_mcc_policy_table, NULL),
+};
+
+const int mcc_proc_hdls_num = sizeof(mcc_proc_hdls) / sizeof(struct rtw_proc_hdl);
+
+static int rtw_mcc_proc_open(struct inode *inode, struct file *file)
+{
+	ssize_t index = (ssize_t)PDE_DATA(inode);
+	const struct rtw_proc_hdl *hdl = mcc_proc_hdls + index;
+	void *private = proc_get_parent_data(inode);
+
+	if (hdl->type == RTW_PROC_HDL_TYPE_SEQ) {
+		int res = seq_open(file, hdl->u.seq_op);
+
+		if (res == 0)
+			((struct seq_file *)file->private_data)->private = private;
+
+		return res;
+	} else if (hdl->type == RTW_PROC_HDL_TYPE_SSEQ) {
+		int (*show)(struct seq_file *, void *) = hdl->u.show ? hdl->u.show : proc_get_dummy;
+
+		return single_open(file, show, private);
+	} else {
+		return -EROFS;
+	}
+}
+
+static ssize_t rtw_mcc_proc_write(struct file *file, const char __user *buffer, size_t count, loff_t *pos)
+{
+	ssize_t index = (ssize_t)PDE_DATA(file_inode(file));
+	const struct rtw_proc_hdl *hdl = mcc_proc_hdls + index;
+	ssize_t (*write)(struct file *, const char __user *, size_t, loff_t *, void *) = hdl->write;
+
+	if (write)
+		return write(file, buffer, count, pos, ((struct seq_file *)file->private_data)->private);
+
+	return -EROFS;
+}
+
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 6, 0))
+static const struct file_operations rtw_mcc_proc_seq_fops = {
+	.owner = THIS_MODULE,
+	.open = rtw_mcc_proc_open,
+	.read = seq_read,
+	.llseek = seq_lseek,
+	.release = seq_release,
+	.write = rtw_mcc_proc_write,
+};
+
+static const struct file_operations rtw_mcc_proc_sseq_fops = {
+	.owner = THIS_MODULE,
+	.open = rtw_mcc_proc_open,
+	.read = seq_read,
+	.llseek = seq_lseek,
+	.release = single_release,
+	.write = rtw_mcc_proc_write,
+};
+#else
+static const struct proc_ops rtw_mcc_proc_seq_fops = {
+	.proc_owner = THIS_MODULE,
+	.proc_open = rtw_mcc_proc_open,
+	.proc_read = seq_read,
+	.proc_lseek = seq_lseek,
+	.proc_release = seq_release,
+	.proc_write = rtw_mcc_proc_write,
+};
+
+static const struct proc_ops rtw_mcc_proc_sseq_fops = {
+	.proc_owner = THIS_MODULE,
+	.proc_open = rtw_mcc_proc_open,
+	.proc_read = seq_read,
+	.proc_lseek = seq_lseek,
+	.proc_release = single_release,
+	.proc_write = rtw_mcc_proc_write,
+};
+#endif
+
+struct proc_dir_entry *rtw_mcc_proc_init(struct net_device *dev)
+{
+	struct proc_dir_entry *dir_mcc = NULL;
+	struct proc_dir_entry *entry = NULL;
+	_adapter	*adapter = rtw_netdev_priv(dev);
+	ssize_t i;
+
+	if (adapter->dir_dev == NULL) {
+		rtw_warn_on(1);
+		goto exit;
+	}
+
+	if (adapter->dir_mcc != NULL) {
+		rtw_warn_on(1);
+		goto exit;
+	}
+
+	dir_mcc = rtw_proc_create_dir("mcc", adapter->dir_dev, dev);
+	if (dir_mcc == NULL) {
+		rtw_warn_on(1);
+		goto exit;
+	}
+
+	adapter->dir_mcc = dir_mcc;
+
+	for (i = 0; i < mcc_proc_hdls_num; i++) {
+		if (mcc_proc_hdls[i].type == RTW_PROC_HDL_TYPE_SEQ)
+			entry = rtw_proc_create_entry(mcc_proc_hdls[i].name, dir_mcc, &rtw_mcc_proc_seq_fops, (void *)i);
+		else if (mcc_proc_hdls[i].type == RTW_PROC_HDL_TYPE_SSEQ)
+			entry = rtw_proc_create_entry(mcc_proc_hdls[i].name, dir_mcc, &rtw_mcc_proc_sseq_fops, (void *)i);
+		else
+			entry = NULL;
+
+		if (!entry) {
+			rtw_warn_on(1);
+			goto exit;
+		}
+	}
+
+exit:
+	return dir_mcc;
+}
+
+void rtw_mcc_proc_deinit(_adapter	*adapter)
+{
+	struct proc_dir_entry *dir_mcc = NULL;
+	int i;
+
+	dir_mcc = adapter->dir_mcc;
+
+	if (dir_mcc == NULL) {
+		rtw_warn_on(1);
+		return;
+	}
+
+	for (i = 0; i < mcc_proc_hdls_num; i++)
+		remove_proc_entry(mcc_proc_hdls[i].name, dir_mcc);
+
+	remove_proc_entry("mcc", adapter->dir_dev);
+
+	adapter->dir_mcc = NULL;
+}
+#endif /* CONFIG_MCC_MODE */
+
+struct proc_dir_entry *rtw_adapter_proc_init(struct net_device *dev)
+{
+	struct proc_dir_entry *drv_proc = get_rtw_drv_proc();
+	struct proc_dir_entry *dir_dev = NULL;
+	struct proc_dir_entry *entry = NULL;
+	_adapter *adapter = rtw_netdev_priv(dev);
+	ssize_t i;
+
+	if (drv_proc == NULL) {
+		rtw_warn_on(1);
+		goto exit;
+	}
+
+	if (adapter->dir_dev != NULL) {
+		rtw_warn_on(1);
+		goto exit;
+	}
+
+	dir_dev = rtw_proc_create_dir(dev->name, drv_proc, dev);
+	if (dir_dev == NULL) {
+		rtw_warn_on(1);
+		goto exit;
+	}
+
+	adapter->dir_dev = dir_dev;
+
+	for (i = 0; i < adapter_proc_hdls_num; i++) {
+		if (adapter_proc_hdls[i].type == RTW_PROC_HDL_TYPE_SEQ)
+			entry = rtw_proc_create_entry(adapter_proc_hdls[i].name, dir_dev, &rtw_adapter_proc_seq_fops, (void *)i);
+		else if (adapter_proc_hdls[i].type == RTW_PROC_HDL_TYPE_SSEQ)
+			entry = rtw_proc_create_entry(adapter_proc_hdls[i].name, dir_dev, &rtw_adapter_proc_sseq_fops, (void *)i);
+		else
+			entry = NULL;
+
+		if (!entry) {
+			rtw_warn_on(1);
+			goto exit;
+		}
+	}
+
+	rtw_odm_proc_init(dev);
+
+#ifdef CONFIG_MCC_MODE
+	rtw_mcc_proc_init(dev);
+#endif /* CONFIG_MCC_MODE */
+
+exit:
+	return dir_dev;
+}
+
+void rtw_adapter_proc_deinit(struct net_device *dev)
+{
+	struct proc_dir_entry *drv_proc = get_rtw_drv_proc();
+	struct proc_dir_entry *dir_dev = NULL;
+	_adapter *adapter = rtw_netdev_priv(dev);
+	int i;
+
+	dir_dev = adapter->dir_dev;
+
+	if (dir_dev == NULL) {
+		rtw_warn_on(1);
+		return;
+	}
+
+	for (i = 0; i < adapter_proc_hdls_num; i++)
+		remove_proc_entry(adapter_proc_hdls[i].name, dir_dev);
+
+	rtw_odm_proc_deinit(adapter);
+
+#ifdef CONFIG_MCC_MODE
+	rtw_mcc_proc_deinit(adapter);
+#endif /* CONFIG_MCC_MODE */
+
+	remove_proc_entry(dev->name, drv_proc);
+
+	adapter->dir_dev = NULL;
+}
+
+void rtw_adapter_proc_replace(struct net_device *dev)
+{
+	struct proc_dir_entry *drv_proc = get_rtw_drv_proc();
+	struct proc_dir_entry *dir_dev = NULL;
+	_adapter *adapter = rtw_netdev_priv(dev);
+	int i;
+
+	dir_dev = adapter->dir_dev;
+
+	if (dir_dev == NULL) {
+		rtw_warn_on(1);
+		return;
+	}
+
+	for (i = 0; i < adapter_proc_hdls_num; i++)
+		remove_proc_entry(adapter_proc_hdls[i].name, dir_dev);
+
+	rtw_odm_proc_deinit(adapter);
+
+#ifdef CONFIG_MCC_MODE
+	rtw_mcc_proc_deinit(adapter);
+#endif /* CONIG_MCC_MODE */
+
+	remove_proc_entry(adapter->old_ifname, drv_proc);
+
+	adapter->dir_dev = NULL;
+
+	rtw_adapter_proc_init(dev);
+
+}
+
+#endif /* CONFIG_PROC_DEBUG */
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/os_dep/linux/rtw_proc.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/os_dep/linux/rtw_proc.h
--- linux-5.6.3/3rdparty/rtl8821ce/os_dep/linux/rtw_proc.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/os_dep/linux/rtw_proc.h	2020-04-10 16:35:06.857661982 +0300
@@ -0,0 +1,60 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#ifndef __RTW_PROC_H__
+#define __RTW_PROC_H__
+
+#include <linux/proc_fs.h>
+#include <linux/seq_file.h>
+
+#define RTW_PROC_HDL_TYPE_SEQ	0
+#define RTW_PROC_HDL_TYPE_SSEQ	1
+
+struct rtw_proc_hdl {
+	char *name;
+	u8 type;
+	union {
+		int (*show)(struct seq_file *, void *);
+		struct seq_operations *seq_op;
+	} u;
+	ssize_t (*write)(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);
+};
+
+#define RTW_PROC_HDL_SEQ(_name, _seq_op, _write) \
+	{ .name = _name, .type = RTW_PROC_HDL_TYPE_SEQ, .u.seq_op = _seq_op, .write = _write}
+
+#define RTW_PROC_HDL_SSEQ(_name, _show, _write) \
+	{ .name = _name, .type = RTW_PROC_HDL_TYPE_SSEQ, .u.show = _show, .write = _write}
+
+#ifdef CONFIG_PROC_DEBUG
+
+struct proc_dir_entry *get_rtw_drv_proc(void);
+int rtw_drv_proc_init(void);
+void rtw_drv_proc_deinit(void);
+struct proc_dir_entry *rtw_adapter_proc_init(struct net_device *dev);
+void rtw_adapter_proc_deinit(struct net_device *dev);
+void rtw_adapter_proc_replace(struct net_device *dev);
+
+#else /* !CONFIG_PROC_DEBUG */
+
+#define get_rtw_drv_proc() NULL
+#define rtw_drv_proc_init() 0
+#define rtw_drv_proc_deinit() do {} while (0)
+#define rtw_adapter_proc_init(dev) NULL
+#define rtw_adapter_proc_deinit(dev) do {} while (0)
+#define rtw_adapter_proc_replace(dev) do {} while (0)
+
+#endif /* !CONFIG_PROC_DEBUG */
+
+#endif /* __RTW_PROC_H__ */
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/os_dep/linux/rtw_rhashtable.c linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/os_dep/linux/rtw_rhashtable.c
--- linux-5.6.3/3rdparty/rtl8821ce/os_dep/linux/rtw_rhashtable.c	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/os_dep/linux/rtw_rhashtable.c	2020-04-10 16:35:06.857661982 +0300
@@ -0,0 +1,74 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+
+#ifdef CONFIG_RTW_MESH /* for now, only promised for kernel versions we support mesh */
+
+#include <drv_types.h>
+
+int rtw_rhashtable_walk_enter(rtw_rhashtable *ht, rtw_rhashtable_iter *iter)
+{
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 7, 0))
+	return rhashtable_walk_init((ht), (iter), GFP_ATOMIC);
+#else
+	/* kernel >= 4.4.0 rhashtable_walk_init use GFP_KERNEL to alloc, spin_lock for assignment */
+	iter->ht = ht;
+	iter->p = NULL;
+	iter->slot = 0;
+	iter->skip = 0;
+
+	iter->walker = kmalloc(sizeof(*iter->walker), GFP_ATOMIC);
+	if (!iter->walker)
+		return -ENOMEM;
+
+	spin_lock(&ht->lock);
+	iter->walker->tbl =
+		rcu_dereference_protected(ht->tbl, lockdep_is_held(&ht->lock));
+	list_add(&iter->walker->list, &iter->walker->tbl->walkers);
+	spin_unlock(&ht->lock);
+
+	return 0;
+#endif
+}
+
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 4, 0))
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 15, 0))
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 25))
+static inline int is_vmalloc_addr(const void *x)
+{
+#ifdef CONFIG_MMU
+	unsigned long addr = (unsigned long)x;
+
+	return addr >= VMALLOC_START && addr < VMALLOC_END;
+#else
+	return 0;
+#endif
+}
+#endif /* (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 25)) */
+
+void kvfree(const void *addr)
+{
+	if (is_vmalloc_addr(addr))
+		vfree(addr);
+	else
+		kfree(addr);
+}
+#endif /* (LINUX_VERSION_CODE < KERNEL_VERSION(3, 15, 0)) */
+
+#include "rhashtable.c"
+
+#endif /* (LINUX_VERSION_CODE < KERNEL_VERSION(4, 4, 0)) */
+
+#endif /* CONFIG_RTW_MESH */
+
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/os_dep/linux/rtw_rhashtable.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/os_dep/linux/rtw_rhashtable.h
--- linux-5.6.3/3rdparty/rtl8821ce/os_dep/linux/rtw_rhashtable.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/os_dep/linux/rtw_rhashtable.h	2020-04-10 16:35:06.857661982 +0300
@@ -0,0 +1,55 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#ifndef __RTW_RHASHTABLE_H__
+#define __RTW_RHASHTABLE_H__
+
+#ifdef CONFIG_RTW_MESH /* for now, only promised for kernel versions we support mesh */
+
+/* directly reference rhashtable in kernel */
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 4, 0))
+#include <linux/rhashtable.h>
+#endif /* (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 4, 0)) */
+
+/* Use rhashtable from kernel 4.4 */
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 4, 0))
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 0, 0))
+#define NULLS_MARKER(value) (1UL | (((long)value) << 1))
+#endif
+#include "rhashtable.h"
+#endif /* (LINUX_VERSION_CODE < KERNEL_VERSION(4, 4, 0)) */
+
+typedef struct rhashtable rtw_rhashtable;
+typedef struct rhash_head rtw_rhash_head;
+typedef struct rhashtable_params rtw_rhashtable_params;
+
+#define rtw_rhashtable_init(ht, params) rhashtable_init(ht, params)
+
+typedef struct rhashtable_iter rtw_rhashtable_iter;
+
+int rtw_rhashtable_walk_enter(rtw_rhashtable *ht, rtw_rhashtable_iter *iter);
+#define rtw_rhashtable_walk_exit(iter) rhashtable_walk_exit(iter)
+#define rtw_rhashtable_walk_start(iter) rhashtable_walk_start(iter)
+#define rtw_rhashtable_walk_next(iter) rhashtable_walk_next(iter)
+#define rtw_rhashtable_walk_stop(iter) rhashtable_walk_stop(iter)
+
+#define rtw_rhashtable_free_and_destroy(ht, free_fn, arg) rhashtable_free_and_destroy((ht), (free_fn), (arg))
+#define rtw_rhashtable_lookup_fast(ht, key, params) rhashtable_lookup_fast((ht), (key), (params))
+#define rtw_rhashtable_lookup_insert_fast(ht, obj, params) rhashtable_lookup_insert_fast((ht), (obj), (params))
+#define rtw_rhashtable_remove_fast(ht, obj, params) rhashtable_remove_fast((ht), (obj), (params))
+
+#endif /* CONFIG_RTW_MESH */
+
+#endif /* __RTW_RHASHTABLE_H__ */
+
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/os_dep/linux/wifi_regd.c linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/os_dep/linux/wifi_regd.c
--- linux-5.6.3/3rdparty/rtl8821ce/os_dep/linux/wifi_regd.c	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/os_dep/linux/wifi_regd.c	2020-04-10 16:35:06.857661982 +0300
@@ -0,0 +1,424 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2009-2010 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+
+#include <drv_types.h>
+
+#ifdef CONFIG_IOCTL_CFG80211
+
+#include <rtw_wifi_regd.h>
+
+static struct country_code_to_enum_rd allCountries[] = {
+	{COUNTRY_CODE_USER, "RD"},
+};
+
+/*
+ * REG_RULE(freq start, freq end, bandwidth, max gain, eirp, reg_flags)
+ */
+
+/*
+ *Only these channels all allow active
+ *scan on all world regulatory domains
+ */
+
+/* 2G chan 01 - chan 11 */
+#define RTW_2GHZ_CH01_11	\
+	REG_RULE(2412-10, 2462+10, 40, 0, 20, 0)
+
+/*
+ *We enable active scan on these a case
+ *by case basis by regulatory domain
+ */
+
+/* 2G chan 12 - chan 13, PASSIV SCAN */
+#define RTW_2GHZ_CH12_13	\
+	REG_RULE(2467-10, 2472+10, 40, 0, 20,	\
+		 NL80211_RRF_PASSIVE_SCAN)
+
+/* 2G chan 14, PASSIVS SCAN, NO OFDM (B only) */
+#define RTW_2GHZ_CH14	\
+	REG_RULE(2484-10, 2484+10, 40, 0, 20,	\
+		 NL80211_RRF_PASSIVE_SCAN | NL80211_RRF_NO_OFDM)
+
+/* 5G chan 36 - chan 64 */
+#define RTW_5GHZ_5150_5350	\
+	REG_RULE(5150-10, 5350+10, 40, 0, 30,	\
+		 NL80211_RRF_PASSIVE_SCAN | NL80211_RRF_NO_IBSS)
+
+/* 5G chan 100 - chan 165 */
+#define RTW_5GHZ_5470_5850	\
+	REG_RULE(5470-10, 5850+10, 40, 0, 30, \
+		 NL80211_RRF_PASSIVE_SCAN | NL80211_RRF_NO_IBSS)
+
+/* 5G chan 149 - chan 165 */
+#define RTW_5GHZ_5725_5850	\
+	REG_RULE(5725-10, 5850+10, 40, 0, 30, \
+		 NL80211_RRF_PASSIVE_SCAN | NL80211_RRF_NO_IBSS)
+
+/* 5G chan 36 - chan 165 */
+#define RTW_5GHZ_5150_5850	\
+	REG_RULE(5150-10, 5850+10, 40, 0, 30,	\
+		 NL80211_RRF_PASSIVE_SCAN | NL80211_RRF_NO_IBSS)
+
+static const struct ieee80211_regdomain rtw_regdom_rd = {
+	.n_reg_rules = 3,
+	.alpha2 = "99",
+	.reg_rules = {
+		RTW_2GHZ_CH01_11,
+		RTW_2GHZ_CH12_13,
+		RTW_5GHZ_5150_5850,
+	}
+};
+
+static const struct ieee80211_regdomain rtw_regdom_11 = {
+	.n_reg_rules = 1,
+	.alpha2 = "99",
+	.reg_rules = {
+		RTW_2GHZ_CH01_11,
+	}
+};
+
+static const struct ieee80211_regdomain rtw_regdom_12_13 = {
+	.n_reg_rules = 2,
+	.alpha2 = "99",
+	.reg_rules = {
+		RTW_2GHZ_CH01_11,
+		RTW_2GHZ_CH12_13,
+	}
+};
+
+static const struct ieee80211_regdomain rtw_regdom_no_midband = {
+	.n_reg_rules = 3,
+	.alpha2 = "99",
+	.reg_rules = {
+		RTW_2GHZ_CH01_11,
+		RTW_5GHZ_5150_5350,
+		RTW_5GHZ_5725_5850,
+	}
+};
+
+static const struct ieee80211_regdomain rtw_regdom_60_64 = {
+	.n_reg_rules = 3,
+	.alpha2 = "99",
+	.reg_rules = {
+		RTW_2GHZ_CH01_11,
+		RTW_2GHZ_CH12_13,
+		RTW_5GHZ_5725_5850,
+	}
+};
+
+static const struct ieee80211_regdomain rtw_regdom_14_60_64 = {
+	.n_reg_rules = 4,
+	.alpha2 = "99",
+	.reg_rules = {
+		RTW_2GHZ_CH01_11,
+		RTW_2GHZ_CH12_13,
+		RTW_2GHZ_CH14,
+		RTW_5GHZ_5725_5850,
+	}
+};
+
+static const struct ieee80211_regdomain rtw_regdom_14 = {
+	.n_reg_rules = 3,
+	.alpha2 = "99",
+	.reg_rules = {
+		RTW_2GHZ_CH01_11,
+		RTW_2GHZ_CH12_13,
+		RTW_2GHZ_CH14,
+	}
+};
+
+#if 0
+static struct rtw_regulatory *rtw_regd;
+#endif
+
+#if 0 /* not_yet */
+static void _rtw_reg_apply_beaconing_flags(struct wiphy *wiphy,
+		enum nl80211_reg_initiator initiator)
+{
+	enum nl80211_band band;
+	struct ieee80211_supported_band *sband;
+	const struct ieee80211_reg_rule *reg_rule;
+	struct ieee80211_channel *ch;
+	unsigned int i;
+	u32 bandwidth = 0;
+	int r;
+
+	for (band = 0; band < NUM_NL80211_BANDS; band++) {
+
+		if (!wiphy->bands[band])
+			continue;
+
+		sband = wiphy->bands[band];
+
+		for (i = 0; i < sband->n_channels; i++) {
+			ch = &sband->channels[i];
+			if (rtw_is_dfs_ch(ch->hw_value) ||
+			    (ch->flags & IEEE80211_CHAN_RADAR))
+				continue;
+			if (initiator == NL80211_REGDOM_SET_BY_COUNTRY_IE) {
+				r = freq_reg_info(wiphy, ch->center_freq,
+						  bandwidth, &reg_rule);
+				if (r)
+					continue;
+
+				/*
+				 *If 11d had a rule for this channel ensure
+				 *we enable adhoc/beaconing if it allows us to
+				 *use it. Note that we would have disabled it
+				 *by applying our static world regdomain by
+				 *default during init, prior to calling our
+				 *regulatory_hint().
+				 */
+
+				if (!(reg_rule->flags & NL80211_RRF_NO_IBSS))
+					ch->flags &= ~IEEE80211_CHAN_NO_IBSS;
+				if (!
+				    (reg_rule->flags &
+				     NL80211_RRF_PASSIVE_SCAN))
+					ch->flags &=
+						~IEEE80211_CHAN_PASSIVE_SCAN;
+			} else {
+				if (ch->beacon_found)
+					ch->flags &= ~(IEEE80211_CHAN_NO_IBSS |
+						IEEE80211_CHAN_PASSIVE_SCAN);
+			}
+		}
+	}
+}
+
+/* Allows active scan scan on Ch 12 and 13 */
+static void _rtw_reg_apply_active_scan_flags(struct wiphy *wiphy,
+		enum nl80211_reg_initiator
+		initiator)
+{
+	struct ieee80211_supported_band *sband;
+	struct ieee80211_channel *ch;
+	const struct ieee80211_reg_rule *reg_rule;
+	u32 bandwidth = 0;
+	int r;
+
+	if (!wiphy->bands[NL80211_BAND_2GHZ])
+		return;
+	sband = wiphy->bands[NL80211_BAND_2GHZ];
+
+	/*
+	 * If no country IE has been received always enable active scan
+	 * on these channels. This is only done for specific regulatory SKUs
+	 */
+	if (initiator != NL80211_REGDOM_SET_BY_COUNTRY_IE) {
+		ch = &sband->channels[11];	/* CH 12 */
+		if (ch->flags & IEEE80211_CHAN_PASSIVE_SCAN)
+			ch->flags &= ~IEEE80211_CHAN_PASSIVE_SCAN;
+		ch = &sband->channels[12];	/* CH 13 */
+		if (ch->flags & IEEE80211_CHAN_PASSIVE_SCAN)
+			ch->flags &= ~IEEE80211_CHAN_PASSIVE_SCAN;
+		return;
+	}
+
+	/*
+	 * If a country IE has been received check its rule for this
+	 * channel first before enabling active scan. The passive scan
+	 * would have been enforced by the initial processing of our
+	 * custom regulatory domain.
+	 */
+
+	ch = &sband->channels[11];	/* CH 12 */
+	r = freq_reg_info(wiphy, ch->center_freq, bandwidth, &reg_rule);
+	if (!r) {
+		if (!(reg_rule->flags & NL80211_RRF_PASSIVE_SCAN))
+			if (ch->flags & IEEE80211_CHAN_PASSIVE_SCAN)
+				ch->flags &= ~IEEE80211_CHAN_PASSIVE_SCAN;
+	}
+
+	ch = &sband->channels[12];	/* CH 13 */
+	r = freq_reg_info(wiphy, ch->center_freq, bandwidth, &reg_rule);
+	if (!r) {
+		if (!(reg_rule->flags & NL80211_RRF_PASSIVE_SCAN))
+			if (ch->flags & IEEE80211_CHAN_PASSIVE_SCAN)
+				ch->flags &= ~IEEE80211_CHAN_PASSIVE_SCAN;
+	}
+}
+#endif
+
+void rtw_regd_apply_flags(struct wiphy *wiphy)
+{
+	struct dvobj_priv *dvobj = wiphy_to_dvobj(wiphy);
+	struct rf_ctl_t *rfctl = dvobj_to_rfctl(dvobj);
+	RT_CHANNEL_INFO *channel_set = rfctl->channel_set;
+	u8 max_chan_nums = rfctl->max_chan_nums;
+
+	struct ieee80211_supported_band *sband;
+	struct ieee80211_channel *ch;
+	unsigned int i, j;
+	u16 channel;
+	u32 freq;
+
+	/* all channels disable */
+	for (i = 0; i < NUM_NL80211_BANDS; i++) {
+		sband = wiphy->bands[i];
+
+		if (sband) {
+			for (j = 0; j < sband->n_channels; j++) {
+				ch = &sband->channels[j];
+
+				if (ch)
+					ch->flags = IEEE80211_CHAN_DISABLED;
+			}
+		}
+	}
+
+	/* channels apply by channel plans. */
+	for (i = 0; i < max_chan_nums; i++) {
+		channel = channel_set[i].ChannelNum;
+		freq = rtw_ch2freq(channel);
+
+		ch = ieee80211_get_channel(wiphy, freq);
+		if (!ch)
+			continue;
+
+		if (channel_set[i].ScanType == SCAN_PASSIVE
+			#if defined(CONFIG_DFS_MASTER)
+			&& rtw_odm_dfs_domain_unknown(dvobj)
+			#endif
+		) {
+			#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 14, 0))
+			ch->flags = (IEEE80211_CHAN_NO_IBSS | IEEE80211_CHAN_PASSIVE_SCAN);
+			#else
+			ch->flags = IEEE80211_CHAN_NO_IR;
+			#endif
+		} else
+			ch->flags = 0;
+
+		#ifdef CONFIG_DFS
+		if (rtw_is_dfs_ch(ch->hw_value)
+			#if defined(CONFIG_DFS_MASTER)
+			&& rtw_odm_dfs_domain_unknown(dvobj)
+			#endif
+		) {
+			ch->flags |= IEEE80211_CHAN_RADAR;
+			#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 14, 0))
+			ch->flags |= (IEEE80211_CHAN_NO_IBSS | IEEE80211_CHAN_PASSIVE_SCAN);
+			#else
+			ch->flags |= IEEE80211_CHAN_NO_IR;
+			#endif
+		}
+		#endif /* CONFIG_DFS */
+	}
+}
+
+static const struct ieee80211_regdomain *_rtw_regdomain_select(struct
+		rtw_regulatory
+		*reg)
+{
+#if 0
+	switch (reg->country_code) {
+	case COUNTRY_CODE_USER:
+	default:
+		return &rtw_regdom_rd;
+	}
+#else
+	return &rtw_regdom_rd;
+#endif
+}
+
+static void rtw_reg_notifier(struct wiphy *wiphy, struct regulatory_request *request)
+{
+	switch (request->initiator) {
+	case NL80211_REGDOM_SET_BY_DRIVER:
+		RTW_INFO("%s: %s\n", __func__, "NL80211_REGDOM_SET_BY_DRIVER");
+		break;
+	case NL80211_REGDOM_SET_BY_CORE:
+		RTW_INFO("%s: %s\n", __func__, "NL80211_REGDOM_SET_BY_CORE");
+		break;
+	case NL80211_REGDOM_SET_BY_USER:
+		RTW_INFO("%s: %s alpha2:%c%c\n", __func__, "NL80211_REGDOM_SET_BY_USER"
+			, request->alpha2[0], request->alpha2[1]);
+		rtw_set_country(wiphy_to_adapter(wiphy), request->alpha2);
+		break;
+	case NL80211_REGDOM_SET_BY_COUNTRY_IE:
+		RTW_INFO("%s: %s\n", __func__, "NL80211_REGDOM_SET_BY_COUNTRY_IE");
+		break;
+	}
+
+	rtw_regd_apply_flags(wiphy);
+}
+
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 9, 0))
+static int rtw_reg_notifier_return(struct wiphy *wiphy, struct regulatory_request *request)
+{
+	rtw_reg_notifier(wiphy, request);
+	return 0;
+}
+#endif
+
+static void _rtw_regd_init_wiphy(struct rtw_regulatory *reg, struct wiphy *wiphy)
+{
+	const struct ieee80211_regdomain *regd;
+
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 9, 0))
+	wiphy->reg_notifier = rtw_reg_notifier_return;
+#else
+	wiphy->reg_notifier = rtw_reg_notifier;
+#endif
+
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 14, 0))
+	wiphy->flags |= WIPHY_FLAG_CUSTOM_REGULATORY;
+	wiphy->flags &= ~WIPHY_FLAG_STRICT_REGULATORY;
+	wiphy->flags &= ~WIPHY_FLAG_DISABLE_BEACON_HINTS;
+#else
+	wiphy->regulatory_flags |= REGULATORY_CUSTOM_REG;
+	wiphy->regulatory_flags &= ~REGULATORY_STRICT_REG;
+	wiphy->regulatory_flags &= ~REGULATORY_DISABLE_BEACON_HINTS;
+#endif
+
+	regd = _rtw_regdomain_select(reg);
+	wiphy_apply_custom_regulatory(wiphy, regd);
+
+	rtw_regd_apply_flags(wiphy);
+}
+
+static struct country_code_to_enum_rd *_rtw_regd_find_country(u16 countrycode)
+{
+	int i;
+
+	for (i = 0; i < ARRAY_SIZE(allCountries); i++) {
+		if (allCountries[i].countrycode == countrycode)
+			return &allCountries[i];
+	}
+	return NULL;
+}
+
+int rtw_regd_init(struct wiphy *wiphy)
+{
+#if 0
+	if (rtw_regd == NULL) {
+		rtw_regd = (struct rtw_regulatory *)
+			   rtw_malloc(sizeof(struct rtw_regulatory));
+
+		rtw_regd->alpha2[0] = '9';
+		rtw_regd->alpha2[1] = '9';
+
+		rtw_regd->country_code = COUNTRY_CODE_USER;
+	}
+
+	RTW_INFO("%s: Country alpha2 being used: %c%c\n",
+		 __func__, rtw_regd->alpha2[0], rtw_regd->alpha2[1]);
+#endif
+
+	_rtw_regd_init_wiphy(NULL, wiphy);
+
+	return 0;
+}
+#endif /* CONFIG_IOCTL_CFG80211 */
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/os_dep/linux/xmit_linux.c linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/os_dep/linux/xmit_linux.c
--- linux-5.6.3/3rdparty/rtl8821ce/os_dep/linux/xmit_linux.c	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/os_dep/linux/xmit_linux.c	2020-04-10 16:35:06.857661982 +0300
@@ -0,0 +1,574 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#define _XMIT_OSDEP_C_
+
+#include <drv_types.h>
+
+#define DBG_DUMP_OS_QUEUE_CTL 0
+
+uint rtw_remainder_len(struct pkt_file *pfile)
+{
+	return pfile->buf_len - ((SIZE_PTR)(pfile->cur_addr) - (SIZE_PTR)(pfile->buf_start));
+}
+
+void _rtw_open_pktfile(_pkt *pktptr, struct pkt_file *pfile)
+{
+
+	pfile->pkt = pktptr;
+	pfile->cur_addr = pfile->buf_start = pktptr->data;
+	pfile->pkt_len = pfile->buf_len = pktptr->len;
+
+	pfile->cur_buffer = pfile->buf_start ;
+
+}
+
+uint _rtw_pktfile_read(struct pkt_file *pfile, u8 *rmem, uint rlen)
+{
+	uint	len = 0;
+
+
+	len =  rtw_remainder_len(pfile);
+	len = (rlen > len) ? len : rlen;
+
+	if (rmem)
+		skb_copy_bits(pfile->pkt, pfile->buf_len - pfile->pkt_len, rmem, len);
+
+	pfile->cur_addr += len;
+	pfile->pkt_len -= len;
+
+
+	return len;
+}
+
+sint rtw_endofpktfile(struct pkt_file *pfile)
+{
+
+	if (pfile->pkt_len == 0) {
+		return _TRUE;
+	}
+
+
+	return _FALSE;
+}
+
+void rtw_set_tx_chksum_offload(_pkt *pkt, struct pkt_attrib *pattrib)
+{
+#ifdef CONFIG_TX_CSUM_OFFLOAD	
+	struct sk_buff *skb = (struct sk_buff *)pkt;
+	struct iphdr *iph = NULL;
+	struct ipv6hdr *i6ph = NULL;
+	struct udphdr *uh = NULL;
+	struct tcphdr *th = NULL;
+	u8 	protocol = 0xFF;
+
+	if (skb->protocol == htons(ETH_P_IP)) {
+		iph = (struct iphdr *)skb_network_header(skb);
+		protocol = iph->protocol;
+	} else if (skb->protocol == htons(ETH_P_IPV6)) {
+		i6ph = (struct ipv6hdr *)skb_network_header(skb);
+		protocol = i6ph->nexthdr;
+	} else
+		{}
+
+	/*	HW unable to compute CSUM if header & payload was be encrypted by SW(cause TXDMA error) */
+	if (pattrib->bswenc == _TRUE) {
+		if (skb->ip_summed == CHECKSUM_PARTIAL)
+			skb_checksum_help(skb);
+		return;
+	}
+
+	/*	For HW rule, clear ipv4_csum & UDP/TCP_csum if it is UDP/TCP packet	*/
+	switch (protocol) {
+	case IPPROTO_UDP:
+		uh = (struct udphdr *)skb_transport_header(skb);
+		uh->check = 0;
+		if (iph)
+			iph->check = 0;
+		pattrib->hw_csum = _TRUE;
+		break;
+	case IPPROTO_TCP:
+		th = (struct tcphdr *)skb_transport_header(skb);
+		th->check = 0;
+		if (iph)
+			iph->check = 0;
+		pattrib->hw_csum = _TRUE;
+		break;
+	default:
+		break;
+	}
+#endif
+
+}
+
+int rtw_os_xmit_resource_alloc(_adapter *padapter, struct xmit_buf *pxmitbuf, u32 alloc_sz, u8 flag)
+{
+	if (alloc_sz > 0) {
+#ifdef CONFIG_USE_USB_BUFFER_ALLOC_TX
+		struct dvobj_priv	*pdvobjpriv = adapter_to_dvobj(padapter);
+		struct usb_device	*pusbd = pdvobjpriv->pusbdev;
+
+		pxmitbuf->pallocated_buf = rtw_usb_buffer_alloc(pusbd, (size_t)alloc_sz, &pxmitbuf->dma_transfer_addr);
+		pxmitbuf->pbuf = pxmitbuf->pallocated_buf;
+		if (pxmitbuf->pallocated_buf == NULL)
+			return _FAIL;
+#else /* CONFIG_USE_USB_BUFFER_ALLOC_TX */
+
+		pxmitbuf->pallocated_buf = rtw_zmalloc(alloc_sz);
+		if (pxmitbuf->pallocated_buf == NULL)
+			return _FAIL;
+
+		pxmitbuf->pbuf = (u8 *)N_BYTE_ALIGMENT((SIZE_PTR)(pxmitbuf->pallocated_buf), XMITBUF_ALIGN_SZ);
+
+#endif /* CONFIG_USE_USB_BUFFER_ALLOC_TX */
+	}
+
+	if (flag) {
+#ifdef CONFIG_USB_HCI
+		int i;
+		for (i = 0; i < 8; i++) {
+			pxmitbuf->pxmit_urb[i] = usb_alloc_urb(0, GFP_KERNEL);
+			if (pxmitbuf->pxmit_urb[i] == NULL) {
+				RTW_INFO("pxmitbuf->pxmit_urb[i]==NULL");
+				return _FAIL;
+			}
+		}
+#endif
+	}
+
+	return _SUCCESS;
+}
+
+void rtw_os_xmit_resource_free(_adapter *padapter, struct xmit_buf *pxmitbuf, u32 free_sz, u8 flag)
+{
+	if (flag) {
+#ifdef CONFIG_USB_HCI
+		int i;
+
+		for (i = 0; i < 8; i++) {
+			if (pxmitbuf->pxmit_urb[i]) {
+				/* usb_kill_urb(pxmitbuf->pxmit_urb[i]); */
+				usb_free_urb(pxmitbuf->pxmit_urb[i]);
+			}
+		}
+#endif
+	}
+
+	if (free_sz > 0) {
+#ifdef CONFIG_USE_USB_BUFFER_ALLOC_TX
+		struct dvobj_priv	*pdvobjpriv = adapter_to_dvobj(padapter);
+		struct usb_device	*pusbd = pdvobjpriv->pusbdev;
+
+		rtw_usb_buffer_free(pusbd, (size_t)free_sz, pxmitbuf->pallocated_buf, pxmitbuf->dma_transfer_addr);
+		pxmitbuf->pallocated_buf =  NULL;
+		pxmitbuf->dma_transfer_addr = 0;
+#else	/* CONFIG_USE_USB_BUFFER_ALLOC_TX */
+		if (pxmitbuf->pallocated_buf)
+			rtw_mfree(pxmitbuf->pallocated_buf, free_sz);
+#endif /* CONFIG_USE_USB_BUFFER_ALLOC_TX */
+	}
+}
+
+void dump_os_queue(void *sel, _adapter *padapter)
+{
+	struct net_device *ndev = padapter->pnetdev;
+
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 35))
+	int i;
+
+	for (i = 0; i < 4; i++) {
+		RTW_PRINT_SEL(sel, "os_queue[%d]:%s\n"
+			, i, __netif_subqueue_stopped(ndev, i) ? "stopped" : "waked");
+	}
+#else
+	RTW_PRINT_SEL(sel, "os_queue:%s\n"
+		      , netif_queue_stopped(ndev) ? "stopped" : "waked");
+#endif
+}
+
+#define WMM_XMIT_THRESHOLD	(NR_XMITFRAME*2/5)
+
+static inline bool rtw_os_need_wake_queue(_adapter *padapter, u16 qidx)
+{
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 35))
+	struct xmit_priv *pxmitpriv = &padapter->xmitpriv;
+
+	if (padapter->registrypriv.wifi_spec) {
+		if (pxmitpriv->hwxmits[qidx].accnt < WMM_XMIT_THRESHOLD)
+			return _TRUE;
+#ifdef DBG_CONFIG_ERROR_DETECT
+#ifdef DBG_CONFIG_ERROR_RESET
+	} else if (rtw_hal_sreset_inprogress(padapter) == _TRUE) {
+		return _FALSE;
+#endif/* #ifdef DBG_CONFIG_ERROR_RESET */
+#endif/* #ifdef DBG_CONFIG_ERROR_DETECT */
+	} else {
+#ifdef CONFIG_MCC_MODE
+		if (MCC_EN(padapter)) {
+			if (rtw_hal_check_mcc_status(padapter, MCC_STATUS_DOING_MCC)
+			    && MCC_STOP(padapter))
+				return _FALSE;
+		}
+#endif /* CONFIG_MCC_MODE */
+		return _TRUE;
+	}
+	return _FALSE;
+#else
+#ifdef CONFIG_MCC_MODE
+	if (MCC_EN(padapter)) {
+		if (rtw_hal_check_mcc_status(padapter, MCC_STATUS_DOING_MCC)
+		    && MCC_STOP(padapter))
+			return _FALSE;
+	}
+#endif /* CONFIG_MCC_MODE */
+	return _TRUE;
+#endif
+}
+
+static inline bool rtw_os_need_stop_queue(_adapter *padapter, u16 qidx)
+{
+	struct xmit_priv *pxmitpriv = &padapter->xmitpriv;
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 35))
+	if (padapter->registrypriv.wifi_spec) {
+		/* No free space for Tx, tx_worker is too slow */
+		if (pxmitpriv->hwxmits[qidx].accnt > WMM_XMIT_THRESHOLD)
+			return _TRUE;
+	} else {
+		if (pxmitpriv->free_xmitframe_cnt <= 4)
+			return _TRUE;
+	}
+#else
+	if (pxmitpriv->free_xmitframe_cnt <= 4)
+		return _TRUE;
+#endif
+	return _FALSE;
+}
+
+void rtw_os_pkt_complete(_adapter *padapter, _pkt *pkt)
+{
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 35))
+	u16	qidx;
+
+	qidx = skb_get_queue_mapping(pkt);
+	if (rtw_os_need_wake_queue(padapter, qidx)) {
+		if (DBG_DUMP_OS_QUEUE_CTL)
+			RTW_INFO(FUNC_ADPT_FMT": netif_wake_subqueue[%d]\n", FUNC_ADPT_ARG(padapter), qidx);
+		netif_wake_subqueue(padapter->pnetdev, qidx);
+	}
+#else
+	if (rtw_os_need_wake_queue(padapter, 0)) {
+		if (DBG_DUMP_OS_QUEUE_CTL)
+			RTW_INFO(FUNC_ADPT_FMT": netif_wake_queue\n", FUNC_ADPT_ARG(padapter));
+		netif_wake_queue(padapter->pnetdev);
+	}
+#endif
+
+	rtw_skb_free(pkt);
+}
+
+void rtw_os_xmit_complete(_adapter *padapter, struct xmit_frame *pxframe)
+{
+	if (pxframe->pkt)
+		rtw_os_pkt_complete(padapter, pxframe->pkt);
+
+	pxframe->pkt = NULL;
+}
+
+void rtw_os_xmit_schedule(_adapter *padapter)
+{
+#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
+	_adapter *pri_adapter = GET_PRIMARY_ADAPTER(padapter);
+
+	if (!padapter)
+		return;
+
+	if (_rtw_queue_empty(&padapter->xmitpriv.pending_xmitbuf_queue) == _FALSE)
+		_rtw_up_sema(&pri_adapter->xmitpriv.xmit_sema);
+
+
+#else
+	_irqL  irqL;
+	struct xmit_priv *pxmitpriv;
+
+	if (!padapter)
+		return;
+
+	pxmitpriv = &padapter->xmitpriv;
+
+	_enter_critical_bh(&pxmitpriv->lock, &irqL);
+
+	if (rtw_txframes_pending(padapter))
+		tasklet_hi_schedule(&pxmitpriv->xmit_tasklet);
+
+	_exit_critical_bh(&pxmitpriv->lock, &irqL);
+	
+#if defined(CONFIG_PCI_HCI) && defined(CONFIG_XMIT_THREAD_MODE)
+	if (_rtw_queue_empty(&padapter->xmitpriv.pending_xmitbuf_queue) == _FALSE)
+		_rtw_up_sema(&padapter->xmitpriv.xmit_sema);
+#endif
+	
+
+#endif
+}
+
+static bool rtw_check_xmit_resource(_adapter *padapter, _pkt *pkt)
+{
+	bool busy = _FALSE;
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 35))
+	u16	qidx;
+
+	qidx = skb_get_queue_mapping(pkt);
+	if (rtw_os_need_stop_queue(padapter, qidx)) {
+		if (DBG_DUMP_OS_QUEUE_CTL)
+			RTW_INFO(FUNC_ADPT_FMT": netif_stop_subqueue[%d]\n", FUNC_ADPT_ARG(padapter), qidx);
+		netif_stop_subqueue(padapter->pnetdev, qidx);
+		busy = _TRUE;
+	}
+#else
+	if (rtw_os_need_stop_queue(padapter, 0)) {
+		if (DBG_DUMP_OS_QUEUE_CTL)
+			RTW_INFO(FUNC_ADPT_FMT": netif_stop_queue\n", FUNC_ADPT_ARG(padapter));
+		rtw_netif_stop_queue(padapter->pnetdev);
+		busy = _TRUE;
+	}
+#endif
+	return busy;
+}
+
+void rtw_os_wake_queue_at_free_stainfo(_adapter *padapter, int *qcnt_freed)
+{
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 35))
+	int i;
+
+	for (i = 0; i < 4; i++) {
+		if (qcnt_freed[i] == 0)
+			continue;
+
+		if (rtw_os_need_wake_queue(padapter, i)) {
+			if (DBG_DUMP_OS_QUEUE_CTL)
+				RTW_INFO(FUNC_ADPT_FMT": netif_wake_subqueue[%d]\n", FUNC_ADPT_ARG(padapter), i);
+			netif_wake_subqueue(padapter->pnetdev, i);
+		}
+	}
+#else
+	if (qcnt_freed[0] || qcnt_freed[1] || qcnt_freed[2] || qcnt_freed[3]) {
+		if (rtw_os_need_wake_queue(padapter, 0)) {
+			if (DBG_DUMP_OS_QUEUE_CTL)
+				RTW_INFO(FUNC_ADPT_FMT": netif_wake_queue\n", FUNC_ADPT_ARG(padapter));
+			netif_wake_queue(padapter->pnetdev);
+		}
+	}
+#endif
+}
+
+#ifdef CONFIG_TX_MCAST2UNI
+int rtw_mlcst2unicst(_adapter *padapter, struct sk_buff *skb)
+{
+	struct	sta_priv *pstapriv = &padapter->stapriv;
+	struct xmit_priv *pxmitpriv = &padapter->xmitpriv;
+	_irqL	irqL;
+	_list	*phead, *plist;
+	struct sk_buff *newskb;
+	struct sta_info *psta = NULL;
+	u8 chk_alive_num = 0;
+	char chk_alive_list[NUM_STA];
+	u8 bc_addr[6] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
+	u8 null_addr[6] = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00};
+
+	int i;
+	s32	res;
+
+	DBG_COUNTER(padapter->tx_logs.os_tx_m2u);
+
+	_enter_critical_bh(&pstapriv->asoc_list_lock, &irqL);
+	phead = &pstapriv->asoc_list;
+	plist = get_next(phead);
+
+	/* free sta asoc_queue */
+	while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) {
+		int stainfo_offset;
+		psta = LIST_CONTAINOR(plist, struct sta_info, asoc_list);
+		plist = get_next(plist);
+
+		stainfo_offset = rtw_stainfo_offset(pstapriv, psta);
+		if (stainfo_offset_valid(stainfo_offset))
+			chk_alive_list[chk_alive_num++] = stainfo_offset;
+	}
+	_exit_critical_bh(&pstapriv->asoc_list_lock, &irqL);
+
+	for (i = 0; i < chk_alive_num; i++) {
+		psta = rtw_get_stainfo_by_offset(pstapriv, chk_alive_list[i]);
+		if (!(psta->state & _FW_LINKED)) {
+			DBG_COUNTER(padapter->tx_logs.os_tx_m2u_ignore_fw_linked);
+			continue;
+		}
+
+		/* avoid come from STA1 and send back STA1 */
+		if (_rtw_memcmp(psta->cmn.mac_addr, &skb->data[6], ETH_ALEN) == _TRUE
+			|| _rtw_memcmp(psta->cmn.mac_addr, null_addr, ETH_ALEN) == _TRUE
+			|| _rtw_memcmp(psta->cmn.mac_addr, bc_addr, ETH_ALEN) == _TRUE
+		) {
+			DBG_COUNTER(padapter->tx_logs.os_tx_m2u_ignore_self);
+			continue;
+		}
+
+		DBG_COUNTER(padapter->tx_logs.os_tx_m2u_entry);
+
+		newskb = rtw_skb_copy(skb);
+
+		if (newskb) {
+			_rtw_memcpy(newskb->data, psta->cmn.mac_addr, ETH_ALEN);
+			res = rtw_xmit(padapter, &newskb);
+			if (res < 0) {
+				DBG_COUNTER(padapter->tx_logs.os_tx_m2u_entry_err_xmit);
+				RTW_INFO("%s()-%d: rtw_xmit() return error! res=%d\n", __FUNCTION__, __LINE__, res);
+				pxmitpriv->tx_drop++;
+				rtw_skb_free(newskb);
+			}
+		} else {
+			DBG_COUNTER(padapter->tx_logs.os_tx_m2u_entry_err_skb);
+			RTW_INFO("%s-%d: rtw_skb_copy() failed!\n", __FUNCTION__, __LINE__);
+			pxmitpriv->tx_drop++;
+			/* rtw_skb_free(skb); */
+			return _FALSE;	/* Caller shall tx this multicast frame via normal way. */
+		}
+	}
+
+	rtw_skb_free(skb);
+	return _TRUE;
+}
+#endif /* CONFIG_TX_MCAST2UNI */
+
+
+int _rtw_xmit_entry(_pkt *pkt, _nic_hdl pnetdev)
+{
+	_adapter *padapter = (_adapter *)rtw_netdev_priv(pnetdev);
+	struct xmit_priv *pxmitpriv = &padapter->xmitpriv;
+#ifdef CONFIG_TX_MCAST2UNI
+	extern int rtw_mc2u_disable;
+#endif /* CONFIG_TX_MCAST2UNI	 */
+#ifdef CONFIG_TX_CSUM_OFFLOAD	
+	struct sk_buff *skb = pkt;
+	struct sk_buff *segs, *nskb;
+	netdev_features_t features = padapter->pnetdev->features;
+#endif
+	s32 res = 0;
+
+	if (padapter->registrypriv.mp_mode) {
+		RTW_INFO("MP_TX_DROP_OS_FRAME\n");
+		goto drop_packet;
+	}
+	DBG_COUNTER(padapter->tx_logs.os_tx);
+
+	if (rtw_if_up(padapter) == _FALSE) {
+		DBG_COUNTER(padapter->tx_logs.os_tx_err_up);
+		#ifdef DBG_TX_DROP_FRAME
+		RTW_INFO("DBG_TX_DROP_FRAME %s if_up fail\n", __FUNCTION__);
+		#endif
+		goto drop_packet;
+	}
+
+	rtw_check_xmit_resource(padapter, pkt);
+
+#ifdef CONFIG_TX_MCAST2UNI
+	if (!rtw_mc2u_disable
+		&& MLME_IS_AP(padapter)
+		&& (IP_MCAST_MAC(pkt->data)
+			|| ICMPV6_MCAST_MAC(pkt->data)
+			#ifdef CONFIG_TX_BCAST2UNI
+			|| is_broadcast_mac_addr(pkt->data)
+			#endif
+			)
+		&& (padapter->registrypriv.wifi_spec == 0)
+	) {
+		if (pxmitpriv->free_xmitframe_cnt > (NR_XMITFRAME / 4)) {
+			res = rtw_mlcst2unicst(padapter, pkt);
+			if (res == _TRUE)
+				goto exit;
+		} else {
+			/* RTW_INFO("Stop M2U(%d, %d)! ", pxmitpriv->free_xmitframe_cnt, pxmitpriv->free_xmitbuf_cnt); */
+			/* RTW_INFO("!m2u ); */
+			DBG_COUNTER(padapter->tx_logs.os_tx_m2u_stop);
+		}
+	}
+#endif /* CONFIG_TX_MCAST2UNI	 */
+
+#ifdef CONFIG_TX_CSUM_OFFLOAD
+	if (skb_shinfo(skb)->gso_size) {
+	/*	split a big(65k) skb into several small(1.5k) skbs */
+		features &= ~(NETIF_F_TSO | NETIF_F_TSO6);
+		segs = skb_gso_segment(skb, features);
+		if (IS_ERR(segs) || !segs)
+			goto drop_packet;
+
+		do {
+			nskb = segs;
+			segs = segs->next;
+			nskb->next = NULL;
+			rtw_mstat_update( MSTAT_TYPE_SKB, MSTAT_ALLOC_SUCCESS, nskb->truesize);
+			res = rtw_xmit(padapter, &nskb);
+			if (res < 0) {
+				#ifdef DBG_TX_DROP_FRAME
+				RTW_INFO("DBG_TX_DROP_FRAME %s rtw_xmit fail\n", __FUNCTION__);
+				#endif
+				pxmitpriv->tx_drop++;
+				rtw_os_pkt_complete(padapter, nskb);
+			}
+		} while (segs);
+		rtw_os_pkt_complete(padapter, skb);
+		goto exit;
+	}
+#endif
+
+	res = rtw_xmit(padapter, &pkt);
+	if (res < 0) {
+		#ifdef DBG_TX_DROP_FRAME
+		RTW_INFO("DBG_TX_DROP_FRAME %s rtw_xmit fail\n", __FUNCTION__);
+		#endif
+		goto drop_packet;
+	}
+
+	goto exit;
+
+drop_packet:
+	pxmitpriv->tx_drop++;
+	rtw_os_pkt_complete(padapter, pkt);
+
+exit:
+
+
+	return 0;
+}
+
+int rtw_xmit_entry(_pkt *pkt, _nic_hdl pnetdev)
+{
+	_adapter *padapter = (_adapter *)rtw_netdev_priv(pnetdev);
+	struct	mlme_priv	*pmlmepriv = &(padapter->mlmepriv);
+	int ret = 0;
+
+	if (pkt) {
+		if (check_fwstate(pmlmepriv, WIFI_MONITOR_STATE) == _TRUE) {
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 24))
+			rtw_monitor_xmit_entry((struct sk_buff *)pkt, pnetdev);
+#endif
+		}
+		else {
+			rtw_mstat_update(MSTAT_TYPE_SKB, MSTAT_ALLOC_SUCCESS, pkt->truesize);
+			ret = _rtw_xmit_entry(pkt, pnetdev);
+		}
+
+	}
+
+	return ret;
+}
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/os_dep/osdep_service.c linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/os_dep/osdep_service.c
--- linux-5.6.3/3rdparty/rtl8821ce/os_dep/osdep_service.c	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/os_dep/osdep_service.c	2020-04-10 16:35:06.857661982 +0300
@@ -0,0 +1,3136 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+
+
+#define _OSDEP_SERVICE_C_
+
+#include <drv_types.h>
+
+#define RT_TAG	'1178'
+
+#ifdef DBG_MEMORY_LEAK
+#ifdef PLATFORM_LINUX
+atomic_t _malloc_cnt = ATOMIC_INIT(0);
+atomic_t _malloc_size = ATOMIC_INIT(0);
+#endif
+#endif /* DBG_MEMORY_LEAK */
+
+
+#if defined(PLATFORM_LINUX)
+/*
+* Translate the OS dependent @param error_code to OS independent RTW_STATUS_CODE
+* @return: one of RTW_STATUS_CODE
+*/
+inline int RTW_STATUS_CODE(int error_code)
+{
+	if (error_code >= 0)
+		return _SUCCESS;
+
+	switch (error_code) {
+	/* case -ETIMEDOUT: */
+	/*	return RTW_STATUS_TIMEDOUT; */
+	default:
+		return _FAIL;
+	}
+}
+#else
+inline int RTW_STATUS_CODE(int error_code)
+{
+	return error_code;
+}
+#endif
+
+u32 rtw_atoi(u8 *s)
+{
+
+	int num = 0, flag = 0;
+	int i;
+	for (i = 0; i <= strlen(s); i++) {
+		if (s[i] >= '0' && s[i] <= '9')
+			num = num * 10 + s[i] - '0';
+		else if (s[0] == '-' && i == 0)
+			flag = 1;
+		else
+			break;
+	}
+
+	if (flag == 1)
+		num = num * -1;
+
+	return num;
+
+}
+
+inline void *_rtw_vmalloc(u32 sz)
+{
+	void *pbuf;
+#ifdef PLATFORM_LINUX
+	pbuf = vmalloc(sz);
+#endif
+#ifdef PLATFORM_FREEBSD
+	pbuf = malloc(sz, M_DEVBUF, M_NOWAIT);
+#endif
+
+#ifdef PLATFORM_WINDOWS
+	NdisAllocateMemoryWithTag(&pbuf, sz, RT_TAG);
+#endif
+
+#ifdef DBG_MEMORY_LEAK
+#ifdef PLATFORM_LINUX
+	if (pbuf != NULL) {
+		atomic_inc(&_malloc_cnt);
+		atomic_add(sz, &_malloc_size);
+	}
+#endif
+#endif /* DBG_MEMORY_LEAK */
+
+	return pbuf;
+}
+
+inline void *_rtw_zvmalloc(u32 sz)
+{
+	void *pbuf;
+#ifdef PLATFORM_LINUX
+	pbuf = _rtw_vmalloc(sz);
+	if (pbuf != NULL)
+		memset(pbuf, 0, sz);
+#endif
+#ifdef PLATFORM_FREEBSD
+	pbuf = malloc(sz, M_DEVBUF, M_ZERO | M_NOWAIT);
+#endif
+#ifdef PLATFORM_WINDOWS
+	NdisAllocateMemoryWithTag(&pbuf, sz, RT_TAG);
+	if (pbuf != NULL)
+		NdisFillMemory(pbuf, sz, 0);
+#endif
+
+	return pbuf;
+}
+
+inline void _rtw_vmfree(void *pbuf, u32 sz)
+{
+#ifdef PLATFORM_LINUX
+	vfree(pbuf);
+#endif
+#ifdef PLATFORM_FREEBSD
+	free(pbuf, M_DEVBUF);
+#endif
+#ifdef PLATFORM_WINDOWS
+	NdisFreeMemory(pbuf, sz, 0);
+#endif
+
+#ifdef DBG_MEMORY_LEAK
+#ifdef PLATFORM_LINUX
+	atomic_dec(&_malloc_cnt);
+	atomic_sub(sz, &_malloc_size);
+#endif
+#endif /* DBG_MEMORY_LEAK */
+}
+
+void *_rtw_malloc(u32 sz)
+{
+	void *pbuf = NULL;
+
+#ifdef PLATFORM_LINUX
+#ifdef RTK_DMP_PLATFORM
+	if (sz > 0x4000)
+		pbuf = dvr_malloc(sz);
+	else
+#endif
+		pbuf = kmalloc(sz, in_interrupt() ? GFP_ATOMIC : GFP_KERNEL);
+
+#endif
+#ifdef PLATFORM_FREEBSD
+	pbuf = malloc(sz, M_DEVBUF, M_NOWAIT);
+#endif
+#ifdef PLATFORM_WINDOWS
+
+	NdisAllocateMemoryWithTag(&pbuf, sz, RT_TAG);
+
+#endif
+
+#ifdef DBG_MEMORY_LEAK
+#ifdef PLATFORM_LINUX
+	if (pbuf != NULL) {
+		atomic_inc(&_malloc_cnt);
+		atomic_add(sz, &_malloc_size);
+	}
+#endif
+#endif /* DBG_MEMORY_LEAK */
+
+	return pbuf;
+
+}
+
+
+void *_rtw_zmalloc(u32 sz)
+{
+#ifdef PLATFORM_FREEBSD
+	return malloc(sz, M_DEVBUF, M_ZERO | M_NOWAIT);
+#else /* PLATFORM_FREEBSD */
+	void *pbuf = _rtw_malloc(sz);
+
+	if (pbuf != NULL) {
+
+#ifdef PLATFORM_LINUX
+		memset(pbuf, 0, sz);
+#endif
+
+#ifdef PLATFORM_WINDOWS
+		NdisFillMemory(pbuf, sz, 0);
+#endif
+
+	}
+
+	return pbuf;
+#endif /* PLATFORM_FREEBSD */
+}
+
+void _rtw_mfree(void *pbuf, u32 sz)
+{
+
+#ifdef PLATFORM_LINUX
+#ifdef RTK_DMP_PLATFORM
+	if (sz > 0x4000)
+		dvr_free(pbuf);
+	else
+#endif
+		kfree(pbuf);
+
+#endif
+#ifdef PLATFORM_FREEBSD
+	free(pbuf, M_DEVBUF);
+#endif
+#ifdef PLATFORM_WINDOWS
+
+	NdisFreeMemory(pbuf, sz, 0);
+
+#endif
+
+#ifdef DBG_MEMORY_LEAK
+#ifdef PLATFORM_LINUX
+	atomic_dec(&_malloc_cnt);
+	atomic_sub(sz, &_malloc_size);
+#endif
+#endif /* DBG_MEMORY_LEAK */
+
+}
+
+#ifdef PLATFORM_FREEBSD
+/* review again */
+struct sk_buff *dev_alloc_skb(unsigned int size)
+{
+	struct sk_buff *skb = NULL;
+	u8 *data = NULL;
+
+	/* skb = _rtw_zmalloc(sizeof(struct sk_buff)); */ /* for skb->len, etc. */
+	skb = _rtw_malloc(sizeof(struct sk_buff));
+	if (!skb)
+		goto out;
+	data = _rtw_malloc(size);
+	if (!data)
+		goto nodata;
+
+	skb->head = (unsigned char *)data;
+	skb->data = (unsigned char *)data;
+	skb->tail = (unsigned char *)data;
+	skb->end = (unsigned char *)data + size;
+	skb->len = 0;
+	/* printf("%s()-%d: skb=%p, skb->head = %p\n", __FUNCTION__, __LINE__, skb, skb->head); */
+
+out:
+	return skb;
+nodata:
+	_rtw_mfree(skb, sizeof(struct sk_buff));
+	skb = NULL;
+	goto out;
+
+}
+
+void dev_kfree_skb_any(struct sk_buff *skb)
+{
+	/* printf("%s()-%d: skb->head = %p\n", __FUNCTION__, __LINE__, skb->head); */
+	if (skb->head)
+		_rtw_mfree(skb->head, 0);
+	/* printf("%s()-%d: skb = %p\n", __FUNCTION__, __LINE__, skb); */
+	if (skb)
+		_rtw_mfree(skb, 0);
+}
+struct sk_buff *skb_clone(const struct sk_buff *skb)
+{
+	return NULL;
+}
+
+#endif /* PLATFORM_FREEBSD */
+
+inline struct sk_buff *_rtw_skb_alloc(u32 sz)
+{
+#ifdef PLATFORM_LINUX
+	return __dev_alloc_skb(sz, in_interrupt() ? GFP_ATOMIC : GFP_KERNEL);
+#endif /* PLATFORM_LINUX */
+
+#ifdef PLATFORM_FREEBSD
+	return dev_alloc_skb(sz);
+#endif /* PLATFORM_FREEBSD */
+}
+
+inline void _rtw_skb_free(struct sk_buff *skb)
+{
+	dev_kfree_skb_any(skb);
+}
+
+inline struct sk_buff *_rtw_skb_copy(const struct sk_buff *skb)
+{
+#ifdef PLATFORM_LINUX
+	return skb_copy(skb, in_interrupt() ? GFP_ATOMIC : GFP_KERNEL);
+#endif /* PLATFORM_LINUX */
+
+#ifdef PLATFORM_FREEBSD
+	return NULL;
+#endif /* PLATFORM_FREEBSD */
+}
+
+inline struct sk_buff *_rtw_skb_clone(struct sk_buff *skb)
+{
+#ifdef PLATFORM_LINUX
+	return skb_clone(skb, in_interrupt() ? GFP_ATOMIC : GFP_KERNEL);
+#endif /* PLATFORM_LINUX */
+
+#ifdef PLATFORM_FREEBSD
+	return skb_clone(skb);
+#endif /* PLATFORM_FREEBSD */
+}
+inline struct sk_buff *_rtw_pskb_copy(struct sk_buff *skb)
+{
+#ifdef PLATFORM_LINUX
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 36))
+	return pskb_copy(skb, in_interrupt() ? GFP_ATOMIC : GFP_KERNEL);
+#else
+	return skb_clone(skb, in_interrupt() ? GFP_ATOMIC : GFP_KERNEL);
+#endif
+#endif /* PLATFORM_LINUX */
+
+#ifdef PLATFORM_FREEBSD
+	return NULL;
+#endif /* PLATFORM_FREEBSD */
+}
+
+inline int _rtw_netif_rx(_nic_hdl ndev, struct sk_buff *skb)
+{
+#if defined(PLATFORM_LINUX)
+	skb->dev = ndev;
+	return netif_rx(skb);
+#elif defined(PLATFORM_FREEBSD)
+	return (*ndev->if_input)(ndev, skb);
+#else
+	rtw_warn_on(1);
+	return -1;
+#endif
+}
+
+#ifdef CONFIG_RTW_NAPI
+inline int _rtw_netif_receive_skb(_nic_hdl ndev, struct sk_buff *skb)
+{
+#if defined(PLATFORM_LINUX)
+	skb->dev = ndev;
+	return netif_receive_skb(skb);
+#else
+	rtw_warn_on(1);
+	return -1;
+#endif
+}
+
+#ifdef CONFIG_RTW_GRO
+inline gro_result_t _rtw_napi_gro_receive(struct napi_struct *napi, struct sk_buff *skb)
+{
+#if defined(PLATFORM_LINUX)
+	return napi_gro_receive(napi, skb);
+#else
+	rtw_warn_on(1);
+	return -1;
+#endif
+}
+#endif /* CONFIG_RTW_GRO */
+#endif /* CONFIG_RTW_NAPI */
+
+void _rtw_skb_queue_purge(struct sk_buff_head *list)
+{
+	struct sk_buff *skb;
+
+	while ((skb = skb_dequeue(list)) != NULL)
+		_rtw_skb_free(skb);
+}
+
+#ifdef CONFIG_USB_HCI
+inline void *_rtw_usb_buffer_alloc(struct usb_device *dev, size_t size, dma_addr_t *dma)
+{
+#ifdef PLATFORM_LINUX
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 35))
+	return usb_alloc_coherent(dev, size, (in_interrupt() ? GFP_ATOMIC : GFP_KERNEL), dma);
+#else
+	return usb_buffer_alloc(dev, size, (in_interrupt() ? GFP_ATOMIC : GFP_KERNEL), dma);
+#endif
+#endif /* PLATFORM_LINUX */
+
+#ifdef PLATFORM_FREEBSD
+	return malloc(size, M_USBDEV, M_NOWAIT | M_ZERO);
+#endif /* PLATFORM_FREEBSD */
+}
+inline void _rtw_usb_buffer_free(struct usb_device *dev, size_t size, void *addr, dma_addr_t dma)
+{
+#ifdef PLATFORM_LINUX
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 35))
+	usb_free_coherent(dev, size, addr, dma);
+#else
+	usb_buffer_free(dev, size, addr, dma);
+#endif
+#endif /* PLATFORM_LINUX */
+
+#ifdef PLATFORM_FREEBSD
+	free(addr, M_USBDEV);
+#endif /* PLATFORM_FREEBSD */
+}
+#endif /* CONFIG_USB_HCI */
+
+#if defined(DBG_MEM_ALLOC)
+
+struct rtw_mem_stat {
+	ATOMIC_T alloc; /* the memory bytes we allocate currently */
+	ATOMIC_T peak; /* the peak memory bytes we allocate */
+	ATOMIC_T alloc_cnt; /* the alloc count for alloc currently */
+	ATOMIC_T alloc_err_cnt; /* the error times we fail to allocate memory */
+};
+
+struct rtw_mem_stat rtw_mem_type_stat[mstat_tf_idx(MSTAT_TYPE_MAX)];
+#ifdef RTW_MEM_FUNC_STAT
+struct rtw_mem_stat rtw_mem_func_stat[mstat_ff_idx(MSTAT_FUNC_MAX)];
+#endif
+
+char *MSTAT_TYPE_str[] = {
+	"VIR",
+	"PHY",
+	"SKB",
+	"USB",
+};
+
+#ifdef RTW_MEM_FUNC_STAT
+char *MSTAT_FUNC_str[] = {
+	"UNSP",
+	"IO",
+	"TXIO",
+	"RXIO",
+	"TX",
+	"RX",
+};
+#endif
+
+void rtw_mstat_dump(void *sel)
+{
+	int i;
+	int value_t[4][mstat_tf_idx(MSTAT_TYPE_MAX)];
+#ifdef RTW_MEM_FUNC_STAT
+	int value_f[4][mstat_ff_idx(MSTAT_FUNC_MAX)];
+#endif
+
+	int vir_alloc, vir_peak, vir_alloc_err, phy_alloc, phy_peak, phy_alloc_err;
+	int tx_alloc, tx_peak, tx_alloc_err, rx_alloc, rx_peak, rx_alloc_err;
+
+	for (i = 0; i < mstat_tf_idx(MSTAT_TYPE_MAX); i++) {
+		value_t[0][i] = ATOMIC_READ(&(rtw_mem_type_stat[i].alloc));
+		value_t[1][i] = ATOMIC_READ(&(rtw_mem_type_stat[i].peak));
+		value_t[2][i] = ATOMIC_READ(&(rtw_mem_type_stat[i].alloc_cnt));
+		value_t[3][i] = ATOMIC_READ(&(rtw_mem_type_stat[i].alloc_err_cnt));
+	}
+
+#ifdef RTW_MEM_FUNC_STAT
+	for (i = 0; i < mstat_ff_idx(MSTAT_FUNC_MAX); i++) {
+		value_f[0][i] = ATOMIC_READ(&(rtw_mem_func_stat[i].alloc));
+		value_f[1][i] = ATOMIC_READ(&(rtw_mem_func_stat[i].peak));
+		value_f[2][i] = ATOMIC_READ(&(rtw_mem_func_stat[i].alloc_cnt));
+		value_f[3][i] = ATOMIC_READ(&(rtw_mem_func_stat[i].alloc_err_cnt));
+	}
+#endif
+
+	RTW_PRINT_SEL(sel, "===================== MSTAT =====================\n");
+	RTW_PRINT_SEL(sel, "%4s %10s %10s %10s %10s\n", "TAG", "alloc", "peak", "aloc_cnt", "err_cnt");
+	RTW_PRINT_SEL(sel, "-------------------------------------------------\n");
+	for (i = 0; i < mstat_tf_idx(MSTAT_TYPE_MAX); i++)
+		RTW_PRINT_SEL(sel, "%4s %10d %10d %10d %10d\n", MSTAT_TYPE_str[i], value_t[0][i], value_t[1][i], value_t[2][i], value_t[3][i]);
+#ifdef RTW_MEM_FUNC_STAT
+	RTW_PRINT_SEL(sel, "-------------------------------------------------\n");
+	for (i = 0; i < mstat_ff_idx(MSTAT_FUNC_MAX); i++)
+		RTW_PRINT_SEL(sel, "%4s %10d %10d %10d %10d\n", MSTAT_FUNC_str[i], value_f[0][i], value_f[1][i], value_f[2][i], value_f[3][i]);
+#endif
+}
+
+void rtw_mstat_update(const enum mstat_f flags, const MSTAT_STATUS status, u32 sz)
+{
+	static systime update_time = 0;
+	int peak, alloc;
+	int i;
+
+	/* initialization */
+	if (!update_time) {
+		for (i = 0; i < mstat_tf_idx(MSTAT_TYPE_MAX); i++) {
+			ATOMIC_SET(&(rtw_mem_type_stat[i].alloc), 0);
+			ATOMIC_SET(&(rtw_mem_type_stat[i].peak), 0);
+			ATOMIC_SET(&(rtw_mem_type_stat[i].alloc_cnt), 0);
+			ATOMIC_SET(&(rtw_mem_type_stat[i].alloc_err_cnt), 0);
+		}
+		#ifdef RTW_MEM_FUNC_STAT
+		for (i = 0; i < mstat_ff_idx(MSTAT_FUNC_MAX); i++) {
+			ATOMIC_SET(&(rtw_mem_func_stat[i].alloc), 0);
+			ATOMIC_SET(&(rtw_mem_func_stat[i].peak), 0);
+			ATOMIC_SET(&(rtw_mem_func_stat[i].alloc_cnt), 0);
+			ATOMIC_SET(&(rtw_mem_func_stat[i].alloc_err_cnt), 0);
+		}
+		#endif
+	}
+
+	switch (status) {
+	case MSTAT_ALLOC_SUCCESS:
+		ATOMIC_INC(&(rtw_mem_type_stat[mstat_tf_idx(flags)].alloc_cnt));
+		alloc = ATOMIC_ADD_RETURN(&(rtw_mem_type_stat[mstat_tf_idx(flags)].alloc), sz);
+		peak = ATOMIC_READ(&(rtw_mem_type_stat[mstat_tf_idx(flags)].peak));
+		if (peak < alloc)
+			ATOMIC_SET(&(rtw_mem_type_stat[mstat_tf_idx(flags)].peak), alloc);
+
+		#ifdef RTW_MEM_FUNC_STAT
+		ATOMIC_INC(&(rtw_mem_func_stat[mstat_ff_idx(flags)].alloc_cnt));
+		alloc = ATOMIC_ADD_RETURN(&(rtw_mem_func_stat[mstat_ff_idx(flags)].alloc), sz);
+		peak = ATOMIC_READ(&(rtw_mem_func_stat[mstat_ff_idx(flags)].peak));
+		if (peak < alloc)
+			ATOMIC_SET(&(rtw_mem_func_stat[mstat_ff_idx(flags)].peak), alloc);
+		#endif
+		break;
+
+	case MSTAT_ALLOC_FAIL:
+		ATOMIC_INC(&(rtw_mem_type_stat[mstat_tf_idx(flags)].alloc_err_cnt));
+		#ifdef RTW_MEM_FUNC_STAT
+		ATOMIC_INC(&(rtw_mem_func_stat[mstat_ff_idx(flags)].alloc_err_cnt));
+		#endif
+		break;
+
+	case MSTAT_FREE:
+		ATOMIC_DEC(&(rtw_mem_type_stat[mstat_tf_idx(flags)].alloc_cnt));
+		ATOMIC_SUB(&(rtw_mem_type_stat[mstat_tf_idx(flags)].alloc), sz);
+		#ifdef RTW_MEM_FUNC_STAT
+		ATOMIC_DEC(&(rtw_mem_func_stat[mstat_ff_idx(flags)].alloc_cnt));
+		ATOMIC_SUB(&(rtw_mem_func_stat[mstat_ff_idx(flags)].alloc), sz);
+		#endif
+		break;
+	};
+
+	/* if (rtw_get_passing_time_ms(update_time) > 5000) { */
+	/*	rtw_mstat_dump(RTW_DBGDUMP); */
+	update_time = rtw_get_current_time();
+	/* } */
+}
+
+#ifndef SIZE_MAX
+	#define SIZE_MAX (~(size_t)0)
+#endif
+
+struct mstat_sniff_rule {
+	enum mstat_f flags;
+	size_t lb;
+	size_t hb;
+};
+
+struct mstat_sniff_rule mstat_sniff_rules[] = {
+	{MSTAT_TYPE_PHY, 4097, SIZE_MAX},
+};
+
+int mstat_sniff_rule_num = sizeof(mstat_sniff_rules) / sizeof(struct mstat_sniff_rule);
+
+bool match_mstat_sniff_rules(const enum mstat_f flags, const size_t size)
+{
+	int i;
+	for (i = 0; i < mstat_sniff_rule_num; i++) {
+		if (mstat_sniff_rules[i].flags == flags
+			&& mstat_sniff_rules[i].lb <= size
+			&& mstat_sniff_rules[i].hb >= size)
+			return _TRUE;
+	}
+
+	return _FALSE;
+}
+
+inline void *dbg_rtw_vmalloc(u32 sz, const enum mstat_f flags, const char *func, const int line)
+{
+	void *p;
+
+	if (match_mstat_sniff_rules(flags, sz))
+		RTW_INFO("DBG_MEM_ALLOC %s:%d %s(%d)\n", func, line, __FUNCTION__, (sz));
+
+	p = _rtw_vmalloc((sz));
+
+	rtw_mstat_update(
+		flags
+		, p ? MSTAT_ALLOC_SUCCESS : MSTAT_ALLOC_FAIL
+		, sz
+	);
+
+	return p;
+}
+
+inline void *dbg_rtw_zvmalloc(u32 sz, const enum mstat_f flags, const char *func, const int line)
+{
+	void *p;
+
+	if (match_mstat_sniff_rules(flags, sz))
+		RTW_INFO("DBG_MEM_ALLOC %s:%d %s(%d)\n", func, line, __FUNCTION__, (sz));
+
+	p = _rtw_zvmalloc((sz));
+
+	rtw_mstat_update(
+		flags
+		, p ? MSTAT_ALLOC_SUCCESS : MSTAT_ALLOC_FAIL
+		, sz
+	);
+
+	return p;
+}
+
+inline void dbg_rtw_vmfree(void *pbuf, u32 sz, const enum mstat_f flags, const char *func, const int line)
+{
+
+	if (match_mstat_sniff_rules(flags, sz))
+		RTW_INFO("DBG_MEM_ALLOC %s:%d %s(%d)\n", func, line, __FUNCTION__, (sz));
+
+	_rtw_vmfree((pbuf), (sz));
+
+	rtw_mstat_update(
+		flags
+		, MSTAT_FREE
+		, sz
+	);
+}
+
+inline void *dbg_rtw_malloc(u32 sz, const enum mstat_f flags, const char *func, const int line)
+{
+	void *p;
+
+	if (match_mstat_sniff_rules(flags, sz))
+		RTW_INFO("DBG_MEM_ALLOC %s:%d %s(%d)\n", func, line, __FUNCTION__, (sz));
+
+	p = _rtw_malloc((sz));
+
+	rtw_mstat_update(
+		flags
+		, p ? MSTAT_ALLOC_SUCCESS : MSTAT_ALLOC_FAIL
+		, sz
+	);
+
+	return p;
+}
+
+inline void *dbg_rtw_zmalloc(u32 sz, const enum mstat_f flags, const char *func, const int line)
+{
+	void *p;
+
+	if (match_mstat_sniff_rules(flags, sz))
+		RTW_INFO("DBG_MEM_ALLOC %s:%d %s(%d)\n", func, line, __FUNCTION__, (sz));
+
+	p = _rtw_zmalloc((sz));
+
+	rtw_mstat_update(
+		flags
+		, p ? MSTAT_ALLOC_SUCCESS : MSTAT_ALLOC_FAIL
+		, sz
+	);
+
+	return p;
+}
+
+inline void dbg_rtw_mfree(void *pbuf, u32 sz, const enum mstat_f flags, const char *func, const int line)
+{
+	if (match_mstat_sniff_rules(flags, sz))
+		RTW_INFO("DBG_MEM_ALLOC %s:%d %s(%d)\n", func, line, __FUNCTION__, (sz));
+
+	_rtw_mfree((pbuf), (sz));
+
+	rtw_mstat_update(
+		flags
+		, MSTAT_FREE
+		, sz
+	);
+}
+
+inline struct sk_buff *dbg_rtw_skb_alloc(unsigned int size, const enum mstat_f flags, const char *func, int line)
+{
+	struct sk_buff *skb;
+	unsigned int truesize = 0;
+
+	skb = _rtw_skb_alloc(size);
+
+	if (skb)
+		truesize = skb->truesize;
+
+	if (!skb || truesize < size || match_mstat_sniff_rules(flags, truesize))
+		RTW_INFO("DBG_MEM_ALLOC %s:%d %s(%d), skb:%p, truesize=%u\n", func, line, __FUNCTION__, size, skb, truesize);
+
+	rtw_mstat_update(
+		flags
+		, skb ? MSTAT_ALLOC_SUCCESS : MSTAT_ALLOC_FAIL
+		, truesize
+	);
+
+	return skb;
+}
+
+inline void dbg_rtw_skb_free(struct sk_buff *skb, const enum mstat_f flags, const char *func, int line)
+{
+	unsigned int truesize = skb->truesize;
+
+	if (match_mstat_sniff_rules(flags, truesize))
+		RTW_INFO("DBG_MEM_ALLOC %s:%d %s, truesize=%u\n", func, line, __FUNCTION__, truesize);
+
+	_rtw_skb_free(skb);
+
+	rtw_mstat_update(
+		flags
+		, MSTAT_FREE
+		, truesize
+	);
+}
+
+inline struct sk_buff *dbg_rtw_skb_copy(const struct sk_buff *skb, const enum mstat_f flags, const char *func, const int line)
+{
+	struct sk_buff *skb_cp;
+	unsigned int truesize = skb->truesize;
+	unsigned int cp_truesize = 0;
+
+	skb_cp = _rtw_skb_copy(skb);
+	if (skb_cp)
+		cp_truesize = skb_cp->truesize;
+
+	if (!skb_cp || cp_truesize < truesize || match_mstat_sniff_rules(flags, cp_truesize))
+		RTW_INFO("DBG_MEM_ALLOC %s:%d %s(%u), skb_cp:%p, cp_truesize=%u\n", func, line, __FUNCTION__, truesize, skb_cp, cp_truesize);
+
+	rtw_mstat_update(
+		flags
+		, skb_cp ? MSTAT_ALLOC_SUCCESS : MSTAT_ALLOC_FAIL
+		, cp_truesize
+	);
+
+	return skb_cp;
+}
+
+inline struct sk_buff *dbg_rtw_skb_clone(struct sk_buff *skb, const enum mstat_f flags, const char *func, const int line)
+{
+	struct sk_buff *skb_cl;
+	unsigned int truesize = skb->truesize;
+	unsigned int cl_truesize = 0;
+
+	skb_cl = _rtw_skb_clone(skb);
+	if (skb_cl)
+		cl_truesize = skb_cl->truesize;
+
+	if (!skb_cl || cl_truesize < truesize || match_mstat_sniff_rules(flags, cl_truesize))
+		RTW_INFO("DBG_MEM_ALLOC %s:%d %s(%u), skb_cl:%p, cl_truesize=%u\n", func, line, __FUNCTION__, truesize, skb_cl, cl_truesize);
+
+	rtw_mstat_update(
+		flags
+		, skb_cl ? MSTAT_ALLOC_SUCCESS : MSTAT_ALLOC_FAIL
+		, cl_truesize
+	);
+
+	return skb_cl;
+}
+
+inline int dbg_rtw_netif_rx(_nic_hdl ndev, struct sk_buff *skb, const enum mstat_f flags, const char *func, int line)
+{
+	int ret;
+	unsigned int truesize = skb->truesize;
+
+	if (match_mstat_sniff_rules(flags, truesize))
+		RTW_INFO("DBG_MEM_ALLOC %s:%d %s, truesize=%u\n", func, line, __FUNCTION__, truesize);
+
+	ret = _rtw_netif_rx(ndev, skb);
+
+	rtw_mstat_update(
+		flags
+		, MSTAT_FREE
+		, truesize
+	);
+
+	return ret;
+}
+
+#ifdef CONFIG_RTW_NAPI
+inline int dbg_rtw_netif_receive_skb(_nic_hdl ndev, struct sk_buff *skb, const enum mstat_f flags, const char *func, int line)
+{
+	int ret;
+	unsigned int truesize = skb->truesize;
+
+	if (match_mstat_sniff_rules(flags, truesize))
+		RTW_INFO("DBG_MEM_ALLOC %s:%d %s, truesize=%u\n", func, line, __FUNCTION__, truesize);
+
+	ret = _rtw_netif_receive_skb(ndev, skb);
+
+	rtw_mstat_update(
+		flags
+		, MSTAT_FREE
+		, truesize
+	);
+
+	return ret;
+}
+
+#ifdef CONFIG_RTW_GRO
+inline gro_result_t dbg_rtw_napi_gro_receive(struct napi_struct *napi, struct sk_buff *skb, const enum mstat_f flags, const char *func, int line)
+{
+	int ret;
+	unsigned int truesize = skb->truesize;
+
+	if (match_mstat_sniff_rules(flags, truesize))
+		RTW_INFO("DBG_MEM_ALLOC %s:%d %s, truesize=%u\n", func, line, __FUNCTION__, truesize);
+
+	ret = _rtw_napi_gro_receive(napi, skb);
+
+	rtw_mstat_update(
+		flags
+		, MSTAT_FREE
+		, truesize
+	);
+
+	return ret;
+}
+#endif /* CONFIG_RTW_GRO */
+#endif /* CONFIG_RTW_NAPI */
+
+inline void dbg_rtw_skb_queue_purge(struct sk_buff_head *list, enum mstat_f flags, const char *func, int line)
+{
+	struct sk_buff *skb;
+
+	while ((skb = skb_dequeue(list)) != NULL)
+		dbg_rtw_skb_free(skb, flags, func, line);
+}
+
+#ifdef CONFIG_USB_HCI
+inline void *dbg_rtw_usb_buffer_alloc(struct usb_device *dev, size_t size, dma_addr_t *dma, const enum mstat_f flags, const char *func, int line)
+{
+	void *p;
+
+	if (match_mstat_sniff_rules(flags, size))
+		RTW_INFO("DBG_MEM_ALLOC %s:%d %s(%zu)\n", func, line, __FUNCTION__, size);
+
+	p = _rtw_usb_buffer_alloc(dev, size, dma);
+
+	rtw_mstat_update(
+		flags
+		, p ? MSTAT_ALLOC_SUCCESS : MSTAT_ALLOC_FAIL
+		, size
+	);
+
+	return p;
+}
+
+inline void dbg_rtw_usb_buffer_free(struct usb_device *dev, size_t size, void *addr, dma_addr_t dma, const enum mstat_f flags, const char *func, int line)
+{
+
+	if (match_mstat_sniff_rules(flags, size))
+		RTW_INFO("DBG_MEM_ALLOC %s:%d %s(%zu)\n", func, line, __FUNCTION__, size);
+
+	_rtw_usb_buffer_free(dev, size, addr, dma);
+
+	rtw_mstat_update(
+		flags
+		, MSTAT_FREE
+		, size
+	);
+}
+#endif /* CONFIG_USB_HCI */
+
+#endif /* defined(DBG_MEM_ALLOC) */
+
+void *rtw_malloc2d(int h, int w, size_t size)
+{
+	int j;
+
+	void **a = (void **) rtw_zmalloc(h * sizeof(void *) + h * w * size);
+	if (a == NULL) {
+		RTW_INFO("%s: alloc memory fail!\n", __FUNCTION__);
+		return NULL;
+	}
+
+	for (j = 0; j < h; j++)
+		a[j] = ((char *)(a + h)) + j * w * size;
+
+	return a;
+}
+
+void rtw_mfree2d(void *pbuf, int h, int w, int size)
+{
+	rtw_mfree((u8 *)pbuf, h * sizeof(void *) + w * h * size);
+}
+
+inline void rtw_os_pkt_free(_pkt *pkt)
+{
+#if defined(PLATFORM_LINUX)
+	rtw_skb_free(pkt);
+#elif defined(PLATFORM_FREEBSD)
+	m_freem(pkt);
+#else
+	#error "TBD\n"
+#endif
+}
+
+inline _pkt *rtw_os_pkt_copy(_pkt *pkt)
+{
+#if defined(PLATFORM_LINUX)
+	return rtw_skb_copy(pkt);
+#elif defined(PLATFORM_FREEBSD)
+	return m_dup(pkt, M_NOWAIT);
+#else
+	#error "TBD\n"
+#endif
+}
+
+inline void *rtw_os_pkt_data(_pkt *pkt)
+{
+#if defined(PLATFORM_LINUX)
+	return pkt->data;
+#elif defined(PLATFORM_FREEBSD)
+	return pkt->m_data;
+#else
+	#error "TBD\n"
+#endif
+}
+
+inline u32 rtw_os_pkt_len(_pkt *pkt)
+{
+#if defined(PLATFORM_LINUX)
+	return pkt->len;
+#elif defined(PLATFORM_FREEBSD)
+	return pkt->m_pkthdr.len;
+#else
+	#error "TBD\n"
+#endif
+}
+
+void _rtw_memcpy(void *dst, const void *src, u32 sz)
+{
+
+#if defined(PLATFORM_LINUX) || defined (PLATFORM_FREEBSD)
+
+	memcpy(dst, src, sz);
+
+#endif
+
+#ifdef PLATFORM_WINDOWS
+
+	NdisMoveMemory(dst, src, sz);
+
+#endif
+
+}
+
+inline void _rtw_memmove(void *dst, const void *src, u32 sz)
+{
+#if defined(PLATFORM_LINUX)
+	memmove(dst, src, sz);
+#else
+	#error "TBD\n"
+#endif
+}
+
+int	_rtw_memcmp(const void *dst, const void *src, u32 sz)
+{
+
+#if defined(PLATFORM_LINUX) || defined (PLATFORM_FREEBSD)
+	/* under Linux/GNU/GLibc, the return value of memcmp for two same mem. chunk is 0 */
+
+	if (!(memcmp(dst, src, sz)))
+		return _TRUE;
+	else
+		return _FALSE;
+#endif
+
+
+#ifdef PLATFORM_WINDOWS
+	/* under Windows, the return value of NdisEqualMemory for two same mem. chunk is 1 */
+
+	if (NdisEqualMemory(dst, src, sz))
+		return _TRUE;
+	else
+		return _FALSE;
+
+#endif
+
+
+
+}
+
+void _rtw_memset(void *pbuf, int c, u32 sz)
+{
+
+#if defined(PLATFORM_LINUX) || defined (PLATFORM_FREEBSD)
+
+	memset(pbuf, c, sz);
+
+#endif
+
+#ifdef PLATFORM_WINDOWS
+#if 0
+	NdisZeroMemory(pbuf, sz);
+	if (c != 0)
+		memset(pbuf, c, sz);
+#else
+	NdisFillMemory(pbuf, sz, c);
+#endif
+#endif
+
+}
+
+#ifdef PLATFORM_FREEBSD
+static inline void __list_add(_list *pnew, _list *pprev, _list *pnext)
+{
+	pnext->prev = pnew;
+	pnew->next = pnext;
+	pnew->prev = pprev;
+	pprev->next = pnew;
+}
+#endif /* PLATFORM_FREEBSD */
+
+
+void _rtw_init_listhead(_list *list)
+{
+
+#ifdef PLATFORM_LINUX
+
+	INIT_LIST_HEAD(list);
+
+#endif
+
+#ifdef PLATFORM_FREEBSD
+	list->next = list;
+	list->prev = list;
+#endif
+#ifdef PLATFORM_WINDOWS
+
+	NdisInitializeListHead(list);
+
+#endif
+
+}
+
+
+/*
+For the following list_xxx operations,
+caller must guarantee the atomic context.
+Otherwise, there will be racing condition.
+*/
+u32	rtw_is_list_empty(_list *phead)
+{
+
+#ifdef PLATFORM_LINUX
+
+	if (list_empty(phead))
+		return _TRUE;
+	else
+		return _FALSE;
+
+#endif
+#ifdef PLATFORM_FREEBSD
+
+	if (phead->next == phead)
+		return _TRUE;
+	else
+		return _FALSE;
+
+#endif
+
+
+#ifdef PLATFORM_WINDOWS
+
+	if (IsListEmpty(phead))
+		return _TRUE;
+	else
+		return _FALSE;
+
+#endif
+
+
+}
+
+void rtw_list_insert_head(_list *plist, _list *phead)
+{
+
+#ifdef PLATFORM_LINUX
+	list_add(plist, phead);
+#endif
+
+#ifdef PLATFORM_FREEBSD
+	__list_add(plist, phead, phead->next);
+#endif
+
+#ifdef PLATFORM_WINDOWS
+	InsertHeadList(phead, plist);
+#endif
+}
+
+void rtw_list_insert_tail(_list *plist, _list *phead)
+{
+
+#ifdef PLATFORM_LINUX
+
+	list_add_tail(plist, phead);
+
+#endif
+#ifdef PLATFORM_FREEBSD
+
+	__list_add(plist, phead->prev, phead);
+
+#endif
+#ifdef PLATFORM_WINDOWS
+
+	InsertTailList(phead, plist);
+
+#endif
+
+}
+
+inline void rtw_list_splice(_list *list, _list *head)
+{
+#ifdef PLATFORM_LINUX
+	list_splice(list, head);
+#else
+	#error "TBD\n"
+#endif
+}
+
+inline void rtw_list_splice_init(_list *list, _list *head)
+{
+#ifdef PLATFORM_LINUX
+	list_splice_init(list, head);
+#else
+	#error "TBD\n"
+#endif
+}
+
+inline void rtw_list_splice_tail(_list *list, _list *head)
+{
+#ifdef PLATFORM_LINUX
+	#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 27))
+	if (!list_empty(list))
+		__list_splice(list, head);
+	#else
+	list_splice_tail(list, head);
+	#endif
+#else
+	#error "TBD\n"
+#endif
+}
+
+inline void rtw_hlist_head_init(rtw_hlist_head *h)
+{
+#ifdef PLATFORM_LINUX
+	INIT_HLIST_HEAD(h);
+#else
+	#error "TBD\n"
+#endif
+}
+
+inline void rtw_hlist_add_head(rtw_hlist_node *n, rtw_hlist_head *h)
+{
+#ifdef PLATFORM_LINUX
+	hlist_add_head(n, h);
+#else
+	#error "TBD\n"
+#endif
+}
+
+inline void rtw_hlist_del(rtw_hlist_node *n)
+{
+#ifdef PLATFORM_LINUX
+	hlist_del(n);
+#else
+	#error "TBD\n"
+#endif
+}
+
+inline void rtw_hlist_add_head_rcu(rtw_hlist_node *n, rtw_hlist_head *h)
+{
+#ifdef PLATFORM_LINUX
+	hlist_add_head_rcu(n, h);
+#else
+	#error "TBD\n"
+#endif
+}
+
+inline void rtw_hlist_del_rcu(rtw_hlist_node *n)
+{
+#ifdef PLATFORM_LINUX
+	hlist_del_rcu(n);
+#else
+	#error "TBD\n"
+#endif
+}
+
+void rtw_init_timer(_timer *ptimer, void *padapter, void *pfunc, void *ctx)
+{
+	_adapter *adapter = (_adapter *)padapter;
+
+#ifdef PLATFORM_LINUX
+	_init_timer(ptimer, adapter->pnetdev, pfunc, ctx);
+#endif
+#ifdef PLATFORM_FREEBSD
+	_init_timer(ptimer, adapter->pifp, pfunc, ctx);
+#endif
+#ifdef PLATFORM_WINDOWS
+	_init_timer(ptimer, adapter->hndis_adapter, pfunc, ctx);
+#endif
+}
+
+/*
+
+Caller must check if the list is empty before calling rtw_list_delete
+
+*/
+
+
+void _rtw_init_sema(_sema	*sema, int init_val)
+{
+
+#ifdef PLATFORM_LINUX
+
+	sema_init(sema, init_val);
+
+#endif
+#ifdef PLATFORM_FREEBSD
+	sema_init(sema, init_val, "rtw_drv");
+#endif
+#ifdef PLATFORM_OS_XP
+
+	KeInitializeSemaphore(sema, init_val,  SEMA_UPBND); /* count=0; */
+
+#endif
+
+#ifdef PLATFORM_OS_CE
+	if (*sema == NULL)
+		*sema = CreateSemaphore(NULL, init_val, SEMA_UPBND, NULL);
+#endif
+
+}
+
+void _rtw_free_sema(_sema	*sema)
+{
+#ifdef PLATFORM_FREEBSD
+	sema_destroy(sema);
+#endif
+#ifdef PLATFORM_OS_CE
+	CloseHandle(*sema);
+#endif
+
+}
+
+void _rtw_up_sema(_sema	*sema)
+{
+
+#ifdef PLATFORM_LINUX
+
+	up(sema);
+
+#endif
+#ifdef PLATFORM_FREEBSD
+	sema_post(sema);
+#endif
+#ifdef PLATFORM_OS_XP
+
+	KeReleaseSemaphore(sema, IO_NETWORK_INCREMENT, 1,  FALSE);
+
+#endif
+
+#ifdef PLATFORM_OS_CE
+	ReleaseSemaphore(*sema,  1,  NULL);
+#endif
+}
+
+u32 _rtw_down_sema(_sema *sema)
+{
+
+#ifdef PLATFORM_LINUX
+
+	if (down_interruptible(sema))
+		return _FAIL;
+	else
+		return _SUCCESS;
+
+#endif
+#ifdef PLATFORM_FREEBSD
+	sema_wait(sema);
+	return  _SUCCESS;
+#endif
+#ifdef PLATFORM_OS_XP
+
+	if (STATUS_SUCCESS == KeWaitForSingleObject(sema, Executive, KernelMode, TRUE, NULL))
+		return  _SUCCESS;
+	else
+		return _FAIL;
+#endif
+
+#ifdef PLATFORM_OS_CE
+	if (WAIT_OBJECT_0 == WaitForSingleObject(*sema, INFINITE))
+		return _SUCCESS;
+	else
+		return _FAIL;
+#endif
+}
+
+inline void thread_exit(_completion *comp)
+{
+#ifdef PLATFORM_LINUX
+	complete_and_exit(comp, 0);
+#endif
+
+#ifdef PLATFORM_FREEBSD
+	printf("%s", "RTKTHREAD_exit");
+#endif
+
+#ifdef PLATFORM_OS_CE
+	ExitThread(STATUS_SUCCESS);
+#endif
+
+#ifdef PLATFORM_OS_XP
+	PsTerminateSystemThread(STATUS_SUCCESS);
+#endif
+}
+
+inline void _rtw_init_completion(_completion *comp)
+{
+#ifdef PLATFORM_LINUX
+	init_completion(comp);
+#endif
+}
+inline void _rtw_wait_for_comp_timeout(_completion *comp)
+{
+#ifdef PLATFORM_LINUX
+	wait_for_completion_timeout(comp, msecs_to_jiffies(3000));
+#endif
+}
+inline void _rtw_wait_for_comp(_completion *comp)
+{
+#ifdef PLATFORM_LINUX
+	wait_for_completion(comp);
+#endif
+}
+
+void	_rtw_mutex_init(_mutex *pmutex)
+{
+#ifdef PLATFORM_LINUX
+
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37))
+	mutex_init(pmutex);
+#else
+	init_MUTEX(pmutex);
+#endif
+
+#endif
+#ifdef PLATFORM_FREEBSD
+	mtx_init(pmutex, "", NULL, MTX_DEF | MTX_RECURSE);
+#endif
+#ifdef PLATFORM_OS_XP
+
+	KeInitializeMutex(pmutex, 0);
+
+#endif
+
+#ifdef PLATFORM_OS_CE
+	*pmutex =  CreateMutex(NULL, _FALSE, NULL);
+#endif
+}
+
+void	_rtw_mutex_free(_mutex *pmutex);
+void	_rtw_mutex_free(_mutex *pmutex)
+{
+#ifdef PLATFORM_LINUX
+
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37))
+	mutex_destroy(pmutex);
+#else
+#endif
+
+#ifdef PLATFORM_FREEBSD
+	sema_destroy(pmutex);
+#endif
+
+#endif
+
+#ifdef PLATFORM_OS_XP
+
+#endif
+
+#ifdef PLATFORM_OS_CE
+
+#endif
+}
+
+void	_rtw_spinlock_init(_lock *plock)
+{
+
+#ifdef PLATFORM_LINUX
+
+	spin_lock_init(plock);
+
+#endif
+#ifdef PLATFORM_FREEBSD
+	mtx_init(plock, "", NULL, MTX_DEF | MTX_RECURSE);
+#endif
+#ifdef PLATFORM_WINDOWS
+
+	NdisAllocateSpinLock(plock);
+
+#endif
+
+}
+
+void	_rtw_spinlock_free(_lock *plock)
+{
+#ifdef PLATFORM_FREEBSD
+	mtx_destroy(plock);
+#endif
+
+#ifdef PLATFORM_WINDOWS
+
+	NdisFreeSpinLock(plock);
+
+#endif
+
+}
+#ifdef PLATFORM_FREEBSD
+extern PADAPTER prtw_lock;
+
+void rtw_mtx_lock(_lock *plock)
+{
+	if (prtw_lock)
+		mtx_lock(&prtw_lock->glock);
+	else
+		printf("%s prtw_lock==NULL", __FUNCTION__);
+}
+void rtw_mtx_unlock(_lock *plock)
+{
+	if (prtw_lock)
+		mtx_unlock(&prtw_lock->glock);
+	else
+		printf("%s prtw_lock==NULL", __FUNCTION__);
+
+}
+#endif /* PLATFORM_FREEBSD */
+
+
+void	_rtw_spinlock(_lock	*plock)
+{
+
+#ifdef PLATFORM_LINUX
+
+	spin_lock(plock);
+
+#endif
+#ifdef PLATFORM_FREEBSD
+	mtx_lock(plock);
+#endif
+#ifdef PLATFORM_WINDOWS
+
+	NdisAcquireSpinLock(plock);
+
+#endif
+
+}
+
+void	_rtw_spinunlock(_lock *plock)
+{
+
+#ifdef PLATFORM_LINUX
+
+	spin_unlock(plock);
+
+#endif
+#ifdef PLATFORM_FREEBSD
+	mtx_unlock(plock);
+#endif
+#ifdef PLATFORM_WINDOWS
+
+	NdisReleaseSpinLock(plock);
+
+#endif
+}
+
+
+void	_rtw_spinlock_ex(_lock	*plock)
+{
+
+#ifdef PLATFORM_LINUX
+
+	spin_lock(plock);
+
+#endif
+#ifdef PLATFORM_FREEBSD
+	mtx_lock(plock);
+#endif
+#ifdef PLATFORM_WINDOWS
+
+	NdisDprAcquireSpinLock(plock);
+
+#endif
+
+}
+
+void	_rtw_spinunlock_ex(_lock *plock)
+{
+
+#ifdef PLATFORM_LINUX
+
+	spin_unlock(plock);
+
+#endif
+#ifdef PLATFORM_FREEBSD
+	mtx_unlock(plock);
+#endif
+#ifdef PLATFORM_WINDOWS
+
+	NdisDprReleaseSpinLock(plock);
+
+#endif
+}
+
+
+
+void _rtw_init_queue(_queue *pqueue)
+{
+	_rtw_init_listhead(&(pqueue->queue));
+	_rtw_spinlock_init(&(pqueue->lock));
+}
+
+void _rtw_deinit_queue(_queue *pqueue)
+{
+	_rtw_spinlock_free(&(pqueue->lock));
+}
+
+u32	  _rtw_queue_empty(_queue	*pqueue)
+{
+	return rtw_is_list_empty(&(pqueue->queue));
+}
+
+
+u32 rtw_end_of_queue_search(_list *head, _list *plist)
+{
+	if (head == plist)
+		return _TRUE;
+	else
+		return _FALSE;
+}
+
+
+systime _rtw_get_current_time(void)
+{
+
+#ifdef PLATFORM_LINUX
+	return jiffies;
+#endif
+#ifdef PLATFORM_FREEBSD
+	struct timeval tvp;
+	getmicrotime(&tvp);
+	return tvp.tv_sec;
+#endif
+#ifdef PLATFORM_WINDOWS
+	LARGE_INTEGER	SystemTime;
+	NdisGetCurrentSystemTime(&SystemTime);
+	return SystemTime.LowPart;/* count of 100-nanosecond intervals */
+#endif
+}
+
+inline u32 _rtw_systime_to_ms(systime stime)
+{
+#ifdef PLATFORM_LINUX
+	return jiffies_to_msecs(stime);
+#endif
+#ifdef PLATFORM_FREEBSD
+	return stime * 1000;
+#endif
+#ifdef PLATFORM_WINDOWS
+	return stime / 10000 ;
+#endif
+}
+
+inline systime _rtw_ms_to_systime(u32 ms)
+{
+#ifdef PLATFORM_LINUX
+	return msecs_to_jiffies(ms);
+#endif
+#ifdef PLATFORM_FREEBSD
+	return ms / 1000;
+#endif
+#ifdef PLATFORM_WINDOWS
+	return ms * 10000 ;
+#endif
+}
+
+inline systime _rtw_us_to_systime(u32 us)
+{
+#ifdef PLATFORM_LINUX
+	return usecs_to_jiffies(us);
+#else
+	#error "TBD\n"
+#endif
+}
+
+/* the input parameter start use the same unit as returned by rtw_get_current_time */
+inline s32 _rtw_get_passing_time_ms(systime start)
+{
+	return _rtw_systime_to_ms(_rtw_get_current_time() - start);
+}
+
+inline s32 _rtw_get_remaining_time_ms(systime end)
+{
+	return _rtw_systime_to_ms(end - _rtw_get_current_time());
+}
+
+inline s32 _rtw_get_time_interval_ms(systime start, systime end)
+{
+	return _rtw_systime_to_ms(end - start);
+}
+
+inline bool _rtw_time_after(systime a, systime b)
+{
+#ifdef PLATFORM_LINUX
+	return time_after(a, b);
+#else
+	#error "TBD\n"
+#endif
+}
+
+void rtw_sleep_schedulable(int ms)
+{
+
+#ifdef PLATFORM_LINUX
+
+	u32 delta;
+
+	delta = (ms * HZ) / 1000; /* (ms) */
+	if (delta == 0) {
+		delta = 1;/* 1 ms */
+	}
+	set_current_state(TASK_INTERRUPTIBLE);
+	if (schedule_timeout(delta) != 0)
+		return ;
+	return;
+
+#endif
+#ifdef PLATFORM_FREEBSD
+	DELAY(ms * 1000);
+	return ;
+#endif
+
+#ifdef PLATFORM_WINDOWS
+
+	NdisMSleep(ms * 1000); /* (us)*1000=(ms) */
+
+#endif
+
+}
+
+
+void rtw_msleep_os(int ms)
+{
+
+#ifdef PLATFORM_LINUX
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 36))
+	if (ms < 20) {
+		unsigned long us = ms * 1000UL;
+		usleep_range(us, us + 1000UL);
+	} else
+#endif
+		msleep((unsigned int)ms);
+
+#endif
+#ifdef PLATFORM_FREEBSD
+	/* Delay for delay microseconds */
+	DELAY(ms * 1000);
+	return ;
+#endif
+#ifdef PLATFORM_WINDOWS
+
+	NdisMSleep(ms * 1000); /* (us)*1000=(ms) */
+
+#endif
+
+
+}
+void rtw_usleep_os(int us)
+{
+#ifdef PLATFORM_LINUX
+
+	/* msleep((unsigned int)us); */
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 36))
+	usleep_range(us, us + 1);
+#else
+	if (1 < (us / 1000))
+		msleep(1);
+	else
+		msleep((us / 1000) + 1);
+#endif
+#endif
+
+#ifdef PLATFORM_FREEBSD
+	/* Delay for delay microseconds */
+	DELAY(us);
+
+	return ;
+#endif
+#ifdef PLATFORM_WINDOWS
+
+	NdisMSleep(us); /* (us) */
+
+#endif
+
+
+}
+
+
+#ifdef DBG_DELAY_OS
+void _rtw_mdelay_os(int ms, const char *func, const int line)
+{
+#if 0
+	if (ms > 10)
+		RTW_INFO("%s:%d %s(%d)\n", func, line, __FUNCTION__, ms);
+	rtw_msleep_os(ms);
+	return;
+#endif
+
+
+	RTW_INFO("%s:%d %s(%d)\n", func, line, __FUNCTION__, ms);
+
+#if defined(PLATFORM_LINUX)
+
+	mdelay((unsigned long)ms);
+
+#elif defined(PLATFORM_WINDOWS)
+
+	NdisStallExecution(ms * 1000); /* (us)*1000=(ms) */
+
+#endif
+
+
+}
+void _rtw_udelay_os(int us, const char *func, const int line)
+{
+
+#if 0
+	if (us > 1000) {
+		RTW_INFO("%s:%d %s(%d)\n", func, line, __FUNCTION__, us);
+		rtw_usleep_os(us);
+		return;
+	}
+#endif
+
+
+	RTW_INFO("%s:%d %s(%d)\n", func, line, __FUNCTION__, us);
+
+
+#if defined(PLATFORM_LINUX)
+
+	udelay((unsigned long)us);
+
+#elif defined(PLATFORM_WINDOWS)
+
+	NdisStallExecution(us); /* (us) */
+
+#endif
+
+}
+#else
+void rtw_mdelay_os(int ms)
+{
+
+#ifdef PLATFORM_LINUX
+
+	mdelay((unsigned long)ms);
+
+#endif
+#ifdef PLATFORM_FREEBSD
+	DELAY(ms * 1000);
+	return ;
+#endif
+#ifdef PLATFORM_WINDOWS
+
+	NdisStallExecution(ms * 1000); /* (us)*1000=(ms) */
+
+#endif
+
+
+}
+void rtw_udelay_os(int us)
+{
+
+#ifdef PLATFORM_LINUX
+
+	udelay((unsigned long)us);
+
+#endif
+#ifdef PLATFORM_FREEBSD
+	/* Delay for delay microseconds */
+	DELAY(us);
+	return ;
+#endif
+#ifdef PLATFORM_WINDOWS
+
+	NdisStallExecution(us); /* (us) */
+
+#endif
+
+}
+#endif
+
+void rtw_yield_os(void)
+{
+#ifdef PLATFORM_LINUX
+	yield();
+#endif
+#ifdef PLATFORM_FREEBSD
+	yield();
+#endif
+#ifdef PLATFORM_WINDOWS
+	SwitchToThread();
+#endif
+}
+
+bool rtw_macaddr_is_larger(const u8 *a, const u8 *b)
+{
+	u32 va, vb;
+
+	va = be32_to_cpu(*((u32 *)a));
+	vb = be32_to_cpu(*((u32 *)b));
+	if (va > vb)
+		return 1;
+	else if (va < vb)
+		return 0;
+
+	return be16_to_cpu(*((u16 *)(a + 4))) > be16_to_cpu(*((u16 *)(b + 4)));
+}
+
+#define RTW_SUSPEND_LOCK_NAME "rtw_wifi"
+#define RTW_SUSPEND_TRAFFIC_LOCK_NAME "rtw_wifi_traffic"
+#define RTW_SUSPEND_RESUME_LOCK_NAME "rtw_wifi_resume"
+#ifdef CONFIG_WAKELOCK
+static struct wake_lock rtw_suspend_lock;
+static struct wake_lock rtw_suspend_traffic_lock;
+static struct wake_lock rtw_suspend_resume_lock;
+#elif defined(CONFIG_ANDROID_POWER)
+static android_suspend_lock_t rtw_suspend_lock = {
+	.name = RTW_SUSPEND_LOCK_NAME
+};
+static android_suspend_lock_t rtw_suspend_traffic_lock = {
+	.name = RTW_SUSPEND_TRAFFIC_LOCK_NAME
+};
+static android_suspend_lock_t rtw_suspend_resume_lock = {
+	.name = RTW_SUSPEND_RESUME_LOCK_NAME
+};
+#endif
+
+inline void rtw_suspend_lock_init(void)
+{
+#ifdef CONFIG_WAKELOCK
+	wake_lock_init(&rtw_suspend_lock, WAKE_LOCK_SUSPEND, RTW_SUSPEND_LOCK_NAME);
+	wake_lock_init(&rtw_suspend_traffic_lock, WAKE_LOCK_SUSPEND, RTW_SUSPEND_TRAFFIC_LOCK_NAME);
+	wake_lock_init(&rtw_suspend_resume_lock, WAKE_LOCK_SUSPEND, RTW_SUSPEND_RESUME_LOCK_NAME);
+#elif defined(CONFIG_ANDROID_POWER)
+	android_init_suspend_lock(&rtw_suspend_lock);
+	android_init_suspend_lock(&rtw_suspend_traffic_lock);
+	android_init_suspend_lock(&rtw_suspend_resume_lock);
+#endif
+}
+
+inline void rtw_suspend_lock_uninit(void)
+{
+#ifdef CONFIG_WAKELOCK
+	wake_lock_destroy(&rtw_suspend_lock);
+	wake_lock_destroy(&rtw_suspend_traffic_lock);
+	wake_lock_destroy(&rtw_suspend_resume_lock);
+#elif defined(CONFIG_ANDROID_POWER)
+	android_uninit_suspend_lock(&rtw_suspend_lock);
+	android_uninit_suspend_lock(&rtw_suspend_traffic_lock);
+	android_uninit_suspend_lock(&rtw_suspend_resume_lock);
+#endif
+}
+
+inline void rtw_lock_suspend(void)
+{
+#ifdef CONFIG_WAKELOCK
+	wake_lock(&rtw_suspend_lock);
+#elif defined(CONFIG_ANDROID_POWER)
+	android_lock_suspend(&rtw_suspend_lock);
+#endif
+
+#if  defined(CONFIG_WAKELOCK) || defined(CONFIG_ANDROID_POWER)
+	/* RTW_INFO("####%s: suspend_lock_count:%d####\n", __FUNCTION__, rtw_suspend_lock.stat.count); */
+#endif
+}
+
+inline void rtw_unlock_suspend(void)
+{
+#ifdef CONFIG_WAKELOCK
+	wake_unlock(&rtw_suspend_lock);
+#elif defined(CONFIG_ANDROID_POWER)
+	android_unlock_suspend(&rtw_suspend_lock);
+#endif
+
+#if  defined(CONFIG_WAKELOCK) || defined(CONFIG_ANDROID_POWER)
+	/* RTW_INFO("####%s: suspend_lock_count:%d####\n", __FUNCTION__, rtw_suspend_lock.stat.count); */
+#endif
+}
+
+inline void rtw_resume_lock_suspend(void)
+{
+#ifdef CONFIG_WAKELOCK
+	wake_lock(&rtw_suspend_resume_lock);
+#elif defined(CONFIG_ANDROID_POWER)
+	android_lock_suspend(&rtw_suspend_resume_lock);
+#endif
+
+#if  defined(CONFIG_WAKELOCK) || defined(CONFIG_ANDROID_POWER)
+	/* RTW_INFO("####%s: suspend_lock_count:%d####\n", __FUNCTION__, rtw_suspend_lock.stat.count); */
+#endif
+}
+
+inline void rtw_resume_unlock_suspend(void)
+{
+#ifdef CONFIG_WAKELOCK
+	wake_unlock(&rtw_suspend_resume_lock);
+#elif defined(CONFIG_ANDROID_POWER)
+	android_unlock_suspend(&rtw_suspend_resume_lock);
+#endif
+
+#if  defined(CONFIG_WAKELOCK) || defined(CONFIG_ANDROID_POWER)
+	/* RTW_INFO("####%s: suspend_lock_count:%d####\n", __FUNCTION__, rtw_suspend_lock.stat.count); */
+#endif
+}
+
+inline void rtw_lock_suspend_timeout(u32 timeout_ms)
+{
+#ifdef CONFIG_WAKELOCK
+	wake_lock_timeout(&rtw_suspend_lock, rtw_ms_to_systime(timeout_ms));
+#elif defined(CONFIG_ANDROID_POWER)
+	android_lock_suspend_auto_expire(&rtw_suspend_lock, rtw_ms_to_systime(timeout_ms));
+#endif
+}
+
+
+inline void rtw_lock_traffic_suspend_timeout(u32 timeout_ms)
+{
+#ifdef CONFIG_WAKELOCK
+	wake_lock_timeout(&rtw_suspend_traffic_lock, rtw_ms_to_systime(timeout_ms));
+#elif defined(CONFIG_ANDROID_POWER)
+	android_lock_suspend_auto_expire(&rtw_suspend_traffic_lock, rtw_ms_to_systime(timeout_ms));
+#endif
+	/* RTW_INFO("traffic lock timeout:%d\n", timeout_ms); */
+}
+
+inline void rtw_set_bit(int nr, unsigned long *addr)
+{
+#ifdef PLATFORM_LINUX
+	set_bit(nr, addr);
+#else
+	#error "TBD\n";
+#endif
+}
+
+inline void rtw_clear_bit(int nr, unsigned long *addr)
+{
+#ifdef PLATFORM_LINUX
+	clear_bit(nr, addr);
+#else
+	#error "TBD\n";
+#endif
+}
+
+inline int rtw_test_and_clear_bit(int nr, unsigned long *addr)
+{
+#ifdef PLATFORM_LINUX
+	return test_and_clear_bit(nr, addr);
+#else
+	#error "TBD\n";
+#endif
+}
+
+inline void ATOMIC_SET(ATOMIC_T *v, int i)
+{
+#ifdef PLATFORM_LINUX
+	atomic_set(v, i);
+#elif defined(PLATFORM_WINDOWS)
+	*v = i; /* other choice???? */
+#elif defined(PLATFORM_FREEBSD)
+	atomic_set_int(v, i);
+#endif
+}
+
+inline int ATOMIC_READ(ATOMIC_T *v)
+{
+#ifdef PLATFORM_LINUX
+	return atomic_read(v);
+#elif defined(PLATFORM_WINDOWS)
+	return *v; /* other choice???? */
+#elif defined(PLATFORM_FREEBSD)
+	return atomic_load_acq_32(v);
+#endif
+}
+
+inline void ATOMIC_ADD(ATOMIC_T *v, int i)
+{
+#ifdef PLATFORM_LINUX
+	atomic_add(i, v);
+#elif defined(PLATFORM_WINDOWS)
+	InterlockedAdd(v, i);
+#elif defined(PLATFORM_FREEBSD)
+	atomic_add_int(v, i);
+#endif
+}
+inline void ATOMIC_SUB(ATOMIC_T *v, int i)
+{
+#ifdef PLATFORM_LINUX
+	atomic_sub(i, v);
+#elif defined(PLATFORM_WINDOWS)
+	InterlockedAdd(v, -i);
+#elif defined(PLATFORM_FREEBSD)
+	atomic_subtract_int(v, i);
+#endif
+}
+
+inline void ATOMIC_INC(ATOMIC_T *v)
+{
+#ifdef PLATFORM_LINUX
+	atomic_inc(v);
+#elif defined(PLATFORM_WINDOWS)
+	InterlockedIncrement(v);
+#elif defined(PLATFORM_FREEBSD)
+	atomic_add_int(v, 1);
+#endif
+}
+
+inline void ATOMIC_DEC(ATOMIC_T *v)
+{
+#ifdef PLATFORM_LINUX
+	atomic_dec(v);
+#elif defined(PLATFORM_WINDOWS)
+	InterlockedDecrement(v);
+#elif defined(PLATFORM_FREEBSD)
+	atomic_subtract_int(v, 1);
+#endif
+}
+
+inline int ATOMIC_ADD_RETURN(ATOMIC_T *v, int i)
+{
+#ifdef PLATFORM_LINUX
+	return atomic_add_return(i, v);
+#elif defined(PLATFORM_WINDOWS)
+	return InterlockedAdd(v, i);
+#elif defined(PLATFORM_FREEBSD)
+	atomic_add_int(v, i);
+	return atomic_load_acq_32(v);
+#endif
+}
+
+inline int ATOMIC_SUB_RETURN(ATOMIC_T *v, int i)
+{
+#ifdef PLATFORM_LINUX
+	return atomic_sub_return(i, v);
+#elif defined(PLATFORM_WINDOWS)
+	return InterlockedAdd(v, -i);
+#elif defined(PLATFORM_FREEBSD)
+	atomic_subtract_int(v, i);
+	return atomic_load_acq_32(v);
+#endif
+}
+
+inline int ATOMIC_INC_RETURN(ATOMIC_T *v)
+{
+#ifdef PLATFORM_LINUX
+	return atomic_inc_return(v);
+#elif defined(PLATFORM_WINDOWS)
+	return InterlockedIncrement(v);
+#elif defined(PLATFORM_FREEBSD)
+	atomic_add_int(v, 1);
+	return atomic_load_acq_32(v);
+#endif
+}
+
+inline int ATOMIC_DEC_RETURN(ATOMIC_T *v)
+{
+#ifdef PLATFORM_LINUX
+	return atomic_dec_return(v);
+#elif defined(PLATFORM_WINDOWS)
+	return InterlockedDecrement(v);
+#elif defined(PLATFORM_FREEBSD)
+	atomic_subtract_int(v, 1);
+	return atomic_load_acq_32(v);
+#endif
+}
+
+inline bool ATOMIC_INC_UNLESS(ATOMIC_T *v, int u)
+{
+#ifdef PLATFORM_LINUX
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 15))
+	return atomic_add_unless(v, 1, u);
+#else
+	/* only make sure not exceed after this function */
+	if (ATOMIC_INC_RETURN(v) > u) {
+		ATOMIC_DEC(v);
+		return 0;
+	}
+	return 1;
+#endif
+#else
+	#error "TBD\n"
+#endif
+}
+
+#ifdef PLATFORM_LINUX
+/*
+* Open a file with the specific @param path, @param flag, @param mode
+* @param fpp the pointer of struct file pointer to get struct file pointer while file opening is success
+* @param path the path of the file to open
+* @param flag file operation flags, please refer to linux document
+* @param mode please refer to linux document
+* @return Linux specific error code
+*/
+static int openFile(struct file **fpp, const char *path, int flag, int mode)
+{
+	struct file *fp;
+
+	fp = filp_open(path, flag, mode);
+	if (IS_ERR(fp)) {
+		*fpp = NULL;
+		return PTR_ERR(fp);
+	} else {
+		*fpp = fp;
+		return 0;
+	}
+}
+
+/*
+* Close the file with the specific @param fp
+* @param fp the pointer of struct file to close
+* @return always 0
+*/
+static int closeFile(struct file *fp)
+{
+	filp_close(fp, NULL);
+	return 0;
+}
+
+static int readFile(struct file *fp, char *buf, int len)
+{
+	int rlen = 0, sum = 0;
+
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 1, 0))
+	if (!(fp->f_mode & FMODE_CAN_READ))
+#else
+	if (!fp->f_op || !fp->f_op->read)
+#endif
+		return -EPERM;
+
+	while (sum < len) {
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 14, 0))
+		rlen = kernel_read(fp, buf + sum, len - sum, &fp->f_pos);
+#elif (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 1, 0))
+		rlen = __vfs_read(fp, buf + sum, len - sum, &fp->f_pos);
+#else
+		rlen = fp->f_op->read(fp, buf + sum, len - sum, &fp->f_pos);
+#endif
+		if (rlen > 0)
+			sum += rlen;
+		else if (0 != rlen)
+			return rlen;
+		else
+			break;
+	}
+
+	return  sum;
+
+}
+
+static int writeFile(struct file *fp, char *buf, int len)
+{
+	int wlen = 0, sum = 0;
+
+	if (!fp->f_op || !fp->f_op->write)
+		return -EPERM;
+
+	while (sum < len) {
+		wlen = fp->f_op->write(fp, buf + sum, len - sum, &fp->f_pos);
+		if (wlen > 0)
+			sum += wlen;
+		else if (0 != wlen)
+			return wlen;
+		else
+			break;
+	}
+
+	return sum;
+
+}
+
+/*
+* Test if the specifi @param path is a file and readable
+* If readable, @param sz is got
+* @param path the path of the file to test
+* @return Linux specific error code
+*/
+static int isFileReadable(const char *path, u32 *sz)
+{
+	struct file *fp;
+	int ret = 0;
+	mm_segment_t oldfs;
+	char buf;
+
+	fp = filp_open(path, O_RDONLY, 0);
+	if (IS_ERR(fp))
+		ret = PTR_ERR(fp);
+	else {
+		oldfs = get_fs();
+		set_fs(KERNEL_DS);
+
+		if (1 != readFile(fp, &buf, 1))
+			ret = PTR_ERR(fp);
+
+		if (ret == 0 && sz) {
+			#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 19, 0))
+			*sz = i_size_read(fp->f_path.dentry->d_inode);
+			#else
+			*sz = i_size_read(fp->f_dentry->d_inode);
+			#endif
+		}
+
+		set_fs(oldfs);
+		filp_close(fp, NULL);
+	}
+	return ret;
+}
+
+/*
+* Open the file with @param path and retrive the file content into memory starting from @param buf for @param sz at most
+* @param path the path of the file to open and read
+* @param buf the starting address of the buffer to store file content
+* @param sz how many bytes to read at most
+* @return the byte we've read, or Linux specific error code
+*/
+static int retriveFromFile(const char *path, u8 *buf, u32 sz)
+{
+	int ret = -1;
+	mm_segment_t oldfs;
+	struct file *fp;
+
+	if (path && buf) {
+		ret = openFile(&fp, path, O_RDONLY, 0);
+		if (0 == ret) {
+			RTW_INFO("%s openFile path:%s fp=%p\n", __FUNCTION__, path , fp);
+
+			oldfs = get_fs();
+			set_fs(KERNEL_DS);
+			ret = readFile(fp, buf, sz);
+			set_fs(oldfs);
+			closeFile(fp);
+
+			RTW_INFO("%s readFile, ret:%d\n", __FUNCTION__, ret);
+
+		} else
+			RTW_INFO("%s openFile path:%s Fail, ret:%d\n", __FUNCTION__, path, ret);
+	} else {
+		RTW_INFO("%s NULL pointer\n", __FUNCTION__);
+		ret =  -EINVAL;
+	}
+	return ret;
+}
+
+/*
+* Open the file with @param path and wirte @param sz byte of data starting from @param buf into the file
+* @param path the path of the file to open and write
+* @param buf the starting address of the data to write into file
+* @param sz how many bytes to write at most
+* @return the byte we've written, or Linux specific error code
+*/
+static int storeToFile(const char *path, u8 *buf, u32 sz)
+{
+	int ret = 0;
+	mm_segment_t oldfs;
+	struct file *fp;
+
+	if (path && buf) {
+		ret = openFile(&fp, path, O_CREAT | O_WRONLY, 0666);
+		if (0 == ret) {
+			RTW_INFO("%s openFile path:%s fp=%p\n", __FUNCTION__, path , fp);
+
+			oldfs = get_fs();
+			set_fs(KERNEL_DS);
+			ret = writeFile(fp, buf, sz);
+			set_fs(oldfs);
+			closeFile(fp);
+
+			RTW_INFO("%s writeFile, ret:%d\n", __FUNCTION__, ret);
+
+		} else
+			RTW_INFO("%s openFile path:%s Fail, ret:%d\n", __FUNCTION__, path, ret);
+	} else {
+		RTW_INFO("%s NULL pointer\n", __FUNCTION__);
+		ret =  -EINVAL;
+	}
+	return ret;
+}
+#endif /* PLATFORM_LINUX */
+
+/*
+* Test if the specifi @param path is a file and readable
+* @param path the path of the file to test
+* @return _TRUE or _FALSE
+*/
+int rtw_is_file_readable(const char *path)
+{
+#ifdef PLATFORM_LINUX
+	if (isFileReadable(path, NULL) == 0)
+		return _TRUE;
+	else
+		return _FALSE;
+#else
+	/* Todo... */
+	return _FALSE;
+#endif
+}
+
+/*
+* Test if the specifi @param path is a file and readable.
+* If readable, @param sz is got
+* @param path the path of the file to test
+* @return _TRUE or _FALSE
+*/
+int rtw_is_file_readable_with_size(const char *path, u32 *sz)
+{
+#ifdef PLATFORM_LINUX
+	if (isFileReadable(path, sz) == 0)
+		return _TRUE;
+	else
+		return _FALSE;
+#else
+	/* Todo... */
+	return _FALSE;
+#endif
+}
+
+/*
+* Open the file with @param path and retrive the file content into memory starting from @param buf for @param sz at most
+* @param path the path of the file to open and read
+* @param buf the starting address of the buffer to store file content
+* @param sz how many bytes to read at most
+* @return the byte we've read
+*/
+int rtw_retrieve_from_file(const char *path, u8 *buf, u32 sz)
+{
+#ifdef PLATFORM_LINUX
+	int ret = retriveFromFile(path, buf, sz);
+	return ret >= 0 ? ret : 0;
+#else
+	/* Todo... */
+	return 0;
+#endif
+}
+
+/*
+* Open the file with @param path and wirte @param sz byte of data starting from @param buf into the file
+* @param path the path of the file to open and write
+* @param buf the starting address of the data to write into file
+* @param sz how many bytes to write at most
+* @return the byte we've written
+*/
+int rtw_store_to_file(const char *path, u8 *buf, u32 sz)
+{
+#ifdef PLATFORM_LINUX
+	int ret = storeToFile(path, buf, sz);
+	return ret >= 0 ? ret : 0;
+#else
+	/* Todo... */
+	return 0;
+#endif
+}
+
+#ifdef PLATFORM_LINUX
+struct net_device *rtw_alloc_etherdev_with_old_priv(int sizeof_priv, void *old_priv)
+{
+	struct net_device *pnetdev;
+	struct rtw_netdev_priv_indicator *pnpi;
+
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 35))
+	pnetdev = alloc_etherdev_mq(sizeof(struct rtw_netdev_priv_indicator), 4);
+#else
+	pnetdev = alloc_etherdev(sizeof(struct rtw_netdev_priv_indicator));
+#endif
+	if (!pnetdev)
+		goto RETURN;
+
+	pnpi = netdev_priv(pnetdev);
+	pnpi->priv = old_priv;
+	pnpi->sizeof_priv = sizeof_priv;
+
+RETURN:
+	return pnetdev;
+}
+
+struct net_device *rtw_alloc_etherdev(int sizeof_priv)
+{
+	struct net_device *pnetdev;
+	struct rtw_netdev_priv_indicator *pnpi;
+
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 35))
+	pnetdev = alloc_etherdev_mq(sizeof(struct rtw_netdev_priv_indicator), 4);
+#else
+	pnetdev = alloc_etherdev(sizeof(struct rtw_netdev_priv_indicator));
+#endif
+	if (!pnetdev)
+		goto RETURN;
+
+	pnpi = netdev_priv(pnetdev);
+
+	pnpi->priv = rtw_zvmalloc(sizeof_priv);
+	if (!pnpi->priv) {
+		free_netdev(pnetdev);
+		pnetdev = NULL;
+		goto RETURN;
+	}
+
+	pnpi->sizeof_priv = sizeof_priv;
+RETURN:
+	return pnetdev;
+}
+
+void rtw_free_netdev(struct net_device *netdev)
+{
+	struct rtw_netdev_priv_indicator *pnpi;
+
+	if (!netdev)
+		goto RETURN;
+
+	pnpi = netdev_priv(netdev);
+
+	if (!pnpi->priv)
+		goto RETURN;
+
+	free_netdev(netdev);
+
+RETURN:
+	return;
+}
+
+int rtw_change_ifname(_adapter *padapter, const char *ifname)
+{
+	struct dvobj_priv *dvobj;
+	struct net_device *pnetdev;
+	struct net_device *cur_pnetdev;
+	struct rereg_nd_name_data *rereg_priv;
+	int ret;
+	u8 rtnl_lock_needed;
+
+	if (!padapter)
+		goto error;
+
+	dvobj = adapter_to_dvobj(padapter);
+	cur_pnetdev = padapter->pnetdev;
+	rereg_priv = &padapter->rereg_nd_name_priv;
+
+	/* free the old_pnetdev */
+	if (rereg_priv->old_pnetdev) {
+		free_netdev(rereg_priv->old_pnetdev);
+		rereg_priv->old_pnetdev = NULL;
+	}
+
+	rtnl_lock_needed = rtw_rtnl_lock_needed(dvobj);
+
+	if (rtnl_lock_needed)
+		unregister_netdev(cur_pnetdev);
+	else
+		unregister_netdevice(cur_pnetdev);
+
+	rereg_priv->old_pnetdev = cur_pnetdev;
+
+	pnetdev = rtw_init_netdev(padapter);
+	if (!pnetdev)  {
+		ret = -1;
+		goto error;
+	}
+
+	SET_NETDEV_DEV(pnetdev, dvobj_to_dev(adapter_to_dvobj(padapter)));
+
+	rtw_init_netdev_name(pnetdev, ifname);
+
+	_rtw_memcpy(pnetdev->dev_addr, adapter_mac_addr(padapter), ETH_ALEN);
+
+	if (rtnl_lock_needed)
+		ret = register_netdev(pnetdev);
+	else
+		ret = register_netdevice(pnetdev);
+
+	if (ret != 0) {
+		goto error;
+	}
+
+	return 0;
+
+error:
+
+	return -1;
+
+}
+#endif
+
+#ifdef PLATFORM_FREEBSD
+/*
+ * Copy a buffer from userspace and write into kernel address
+ * space.
+ *
+ * This emulation just calls the FreeBSD copyin function (to
+ * copy data from user space buffer into a kernel space buffer)
+ * and is designed to be used with the above io_write_wrapper.
+ *
+ * This function should return the number of bytes not copied.
+ * I.e. success results in a zero value.
+ * Negative error values are not returned.
+ */
+unsigned long
+copy_from_user(void *to, const void *from, unsigned long n)
+{
+	if (copyin(from, to, n) != 0) {
+		/* Any errors will be treated as a failure
+		   to copy any of the requested bytes */
+		return n;
+	}
+
+	return 0;
+}
+
+unsigned long
+copy_to_user(void *to, const void *from, unsigned long n)
+{
+	if (copyout(from, to, n) != 0) {
+		/* Any errors will be treated as a failure
+		   to copy any of the requested bytes */
+		return n;
+	}
+
+	return 0;
+}
+
+
+/*
+ * The usb_register and usb_deregister functions are used to register
+ * usb drivers with the usb subsystem. In this compatibility layer
+ * emulation a list of drivers (struct usb_driver) is maintained
+ * and is used for probing/attaching etc.
+ *
+ * usb_register and usb_deregister simply call these functions.
+ */
+int
+usb_register(struct usb_driver *driver)
+{
+	rtw_usb_linux_register(driver);
+	return 0;
+}
+
+
+int
+usb_deregister(struct usb_driver *driver)
+{
+	rtw_usb_linux_deregister(driver);
+	return 0;
+}
+
+void module_init_exit_wrapper(void *arg)
+{
+	int (*func)(void) = arg;
+	func();
+	return;
+}
+
+#endif /* PLATFORM_FREEBSD */
+
+#ifdef CONFIG_PLATFORM_SPRD
+	#ifdef do_div
+		#undef do_div
+	#endif
+	#include <asm-generic/div64.h>
+#endif
+
+u64 rtw_modular64(u64 x, u64 y)
+{
+#ifdef PLATFORM_LINUX
+	return do_div(x, y);
+#elif defined(PLATFORM_WINDOWS)
+	return x % y;
+#elif defined(PLATFORM_FREEBSD)
+	return x % y;
+#endif
+}
+
+u64 rtw_division64(u64 x, u64 y)
+{
+#ifdef PLATFORM_LINUX
+	do_div(x, y);
+	return x;
+#elif defined(PLATFORM_WINDOWS)
+	return x / y;
+#elif defined(PLATFORM_FREEBSD)
+	return x / y;
+#endif
+}
+
+inline u32 rtw_random32(void)
+{
+#ifdef PLATFORM_LINUX
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 8, 0))
+	return prandom_u32();
+#elif (LINUX_VERSION_CODE <= KERNEL_VERSION(2, 6, 18))
+	u32 random_int;
+	get_random_bytes(&random_int , 4);
+	return random_int;
+#else
+	return random32();
+#endif
+#elif defined(PLATFORM_WINDOWS)
+#error "to be implemented\n"
+#elif defined(PLATFORM_FREEBSD)
+#error "to be implemented\n"
+#endif
+}
+
+void rtw_buf_free(u8 **buf, u32 *buf_len)
+{
+	u32 ori_len;
+
+	if (!buf || !buf_len)
+		return;
+
+	ori_len = *buf_len;
+
+	if (*buf) {
+		u32 tmp_buf_len = *buf_len;
+		*buf_len = 0;
+		rtw_mfree(*buf, tmp_buf_len);
+		*buf = NULL;
+	}
+}
+
+void rtw_buf_update(u8 **buf, u32 *buf_len, u8 *src, u32 src_len)
+{
+	u32 ori_len = 0, dup_len = 0;
+	u8 *ori = NULL;
+	u8 *dup = NULL;
+
+	if (!buf || !buf_len)
+		return;
+
+	if (!src || !src_len)
+		goto keep_ori;
+
+	/* duplicate src */
+	dup = rtw_malloc(src_len);
+	if (dup) {
+		dup_len = src_len;
+		_rtw_memcpy(dup, src, dup_len);
+	}
+
+keep_ori:
+	ori = *buf;
+	ori_len = *buf_len;
+
+	/* replace buf with dup */
+	*buf_len = 0;
+	*buf = dup;
+	*buf_len = dup_len;
+
+	/* free ori */
+	if (ori && ori_len > 0)
+		rtw_mfree(ori, ori_len);
+}
+
+
+/**
+ * rtw_cbuf_full - test if cbuf is full
+ * @cbuf: pointer of struct rtw_cbuf
+ *
+ * Returns: _TRUE if cbuf is full
+ */
+inline bool rtw_cbuf_full(struct rtw_cbuf *cbuf)
+{
+	return (cbuf->write == cbuf->read - 1) ? _TRUE : _FALSE;
+}
+
+/**
+ * rtw_cbuf_empty - test if cbuf is empty
+ * @cbuf: pointer of struct rtw_cbuf
+ *
+ * Returns: _TRUE if cbuf is empty
+ */
+inline bool rtw_cbuf_empty(struct rtw_cbuf *cbuf)
+{
+	return (cbuf->write == cbuf->read) ? _TRUE : _FALSE;
+}
+
+/**
+ * rtw_cbuf_push - push a pointer into cbuf
+ * @cbuf: pointer of struct rtw_cbuf
+ * @buf: pointer to push in
+ *
+ * Lock free operation, be careful of the use scheme
+ * Returns: _TRUE push success
+ */
+bool rtw_cbuf_push(struct rtw_cbuf *cbuf, void *buf)
+{
+	if (rtw_cbuf_full(cbuf))
+		return _FAIL;
+
+	if (0)
+		RTW_INFO("%s on %u\n", __func__, cbuf->write);
+	cbuf->bufs[cbuf->write] = buf;
+	cbuf->write = (cbuf->write + 1) % cbuf->size;
+
+	return _SUCCESS;
+}
+
+/**
+ * rtw_cbuf_pop - pop a pointer from cbuf
+ * @cbuf: pointer of struct rtw_cbuf
+ *
+ * Lock free operation, be careful of the use scheme
+ * Returns: pointer popped out
+ */
+void *rtw_cbuf_pop(struct rtw_cbuf *cbuf)
+{
+	void *buf;
+	if (rtw_cbuf_empty(cbuf))
+		return NULL;
+
+	if (0)
+		RTW_INFO("%s on %u\n", __func__, cbuf->read);
+	buf = cbuf->bufs[cbuf->read];
+	cbuf->read = (cbuf->read + 1) % cbuf->size;
+
+	return buf;
+}
+
+/**
+ * rtw_cbuf_alloc - allocte a rtw_cbuf with given size and do initialization
+ * @size: size of pointer
+ *
+ * Returns: pointer of srtuct rtw_cbuf, NULL for allocation failure
+ */
+struct rtw_cbuf *rtw_cbuf_alloc(u32 size)
+{
+	struct rtw_cbuf *cbuf;
+
+	cbuf = (struct rtw_cbuf *)rtw_malloc(sizeof(*cbuf) + sizeof(void *) * size);
+
+	if (cbuf) {
+		cbuf->write = cbuf->read = 0;
+		cbuf->size = size;
+	}
+
+	return cbuf;
+}
+
+/**
+ * rtw_cbuf_free - free the given rtw_cbuf
+ * @cbuf: pointer of struct rtw_cbuf to free
+ */
+void rtw_cbuf_free(struct rtw_cbuf *cbuf)
+{
+	rtw_mfree((u8 *)cbuf, sizeof(*cbuf) + sizeof(void *) * cbuf->size);
+}
+
+/**
+ * map_readN - read a range of map data
+ * @map: map to read
+ * @offset: start address to read
+ * @len: length to read
+ * @buf: pointer of buffer to store data read
+ *
+ * Returns: _SUCCESS or _FAIL
+ */
+int map_readN(const struct map_t *map, u16 offset, u16 len, u8 *buf)
+{
+	const struct map_seg_t *seg;
+	int ret = _FAIL;
+	int i;
+
+	if (len == 0) {
+		rtw_warn_on(1);
+		goto exit;
+	}
+
+	if (offset + len > map->len) {
+		rtw_warn_on(1);
+		goto exit;
+	}
+
+	_rtw_memset(buf, map->init_value, len);
+
+	for (i = 0; i < map->seg_num; i++) {
+		u8 *c_dst, *c_src;
+		u16 c_len;
+
+		seg = map->segs + i;
+		if (seg->sa + seg->len <= offset || seg->sa >= offset + len)
+			continue;
+
+		if (seg->sa >= offset) {
+			c_dst = buf + (seg->sa - offset);
+			c_src = seg->c;
+			if (seg->sa + seg->len <= offset + len)
+				c_len = seg->len;
+			else
+				c_len = offset + len - seg->sa;
+		} else {
+			c_dst = buf;
+			c_src = seg->c + (offset - seg->sa);
+			if (seg->sa + seg->len >= offset + len)
+				c_len = len;
+			else
+				c_len = seg->sa + seg->len - offset;
+		}
+			
+		_rtw_memcpy(c_dst, c_src, c_len);
+	}
+
+exit:
+	return ret;
+}
+
+/**
+ * map_read8 - read 1 byte of map data
+ * @map: map to read
+ * @offset: address to read
+ *
+ * Returns: value of data of specified offset. map.init_value if offset is out of range
+ */
+u8 map_read8(const struct map_t *map, u16 offset)
+{
+	const struct map_seg_t *seg;
+	u8 val = map->init_value;
+	int i;
+
+	if (offset + 1 > map->len) {
+		rtw_warn_on(1);
+		goto exit;
+	}
+
+	for (i = 0; i < map->seg_num; i++) {
+		seg = map->segs + i;
+		if (seg->sa + seg->len <= offset || seg->sa >= offset + 1)
+			continue;
+
+		val = *(seg->c + offset - seg->sa);
+		break;
+	}
+
+exit:
+	return val;
+}
+
+int rtw_blacklist_add(_queue *blist, const u8 *addr, u32 timeout_ms)
+{
+	struct blacklist_ent *ent;
+	_list *list, *head;
+	u8 exist = _FALSE, timeout = _FALSE;
+
+	enter_critical_bh(&blist->lock);
+
+	head = &blist->queue;
+	list = get_next(head);
+	while (rtw_end_of_queue_search(head, list) == _FALSE) {
+		ent = LIST_CONTAINOR(list, struct blacklist_ent, list);
+		list = get_next(list);
+
+		if (_rtw_memcmp(ent->addr, addr, ETH_ALEN) == _TRUE) {
+			exist = _TRUE;
+			if (rtw_time_after(rtw_get_current_time(), ent->exp_time))
+				timeout = _TRUE;
+			ent->exp_time = rtw_get_current_time()
+				+ rtw_ms_to_systime(timeout_ms);
+			break;
+		}
+
+		if (rtw_time_after(rtw_get_current_time(), ent->exp_time)) {
+			rtw_list_delete(&ent->list);
+			rtw_mfree(ent, sizeof(struct blacklist_ent));
+		}
+	}
+
+	if (exist == _FALSE) {
+		ent = rtw_malloc(sizeof(struct blacklist_ent));
+		if (ent) {
+			_rtw_memcpy(ent->addr, addr, ETH_ALEN);
+			ent->exp_time = rtw_get_current_time()
+				+ rtw_ms_to_systime(timeout_ms);
+			rtw_list_insert_tail(&ent->list, head);
+		}
+	}
+
+	exit_critical_bh(&blist->lock);
+
+exit:
+	return (exist == _TRUE && timeout == _FALSE) ? RTW_ALREADY : (ent ? _SUCCESS : _FAIL);
+}
+
+int rtw_blacklist_del(_queue *blist, const u8 *addr)
+{
+	struct blacklist_ent *ent = NULL;
+	_list *list, *head;
+	u8 exist = _FALSE;
+
+	enter_critical_bh(&blist->lock);
+	head = &blist->queue;
+	list = get_next(head);
+	while (rtw_end_of_queue_search(head, list) == _FALSE) {
+		ent = LIST_CONTAINOR(list, struct blacklist_ent, list);
+		list = get_next(list);
+
+		if (_rtw_memcmp(ent->addr, addr, ETH_ALEN) == _TRUE) {
+			rtw_list_delete(&ent->list);
+			rtw_mfree(ent, sizeof(struct blacklist_ent));
+			exist = _TRUE;
+			break;
+		}
+
+		if (rtw_time_after(rtw_get_current_time(), ent->exp_time)) {
+			rtw_list_delete(&ent->list);
+			rtw_mfree(ent, sizeof(struct blacklist_ent));
+		}
+	}
+
+	exit_critical_bh(&blist->lock);
+
+exit:
+	return exist == _TRUE ? _SUCCESS : RTW_ALREADY;
+}
+
+int rtw_blacklist_search(_queue *blist, const u8 *addr)
+{
+	struct blacklist_ent *ent = NULL;
+	_list *list, *head;
+	u8 exist = _FALSE;
+
+	enter_critical_bh(&blist->lock);
+	head = &blist->queue;
+	list = get_next(head);
+	while (rtw_end_of_queue_search(head, list) == _FALSE) {
+		ent = LIST_CONTAINOR(list, struct blacklist_ent, list);
+		list = get_next(list);
+
+		if (_rtw_memcmp(ent->addr, addr, ETH_ALEN) == _TRUE) {
+			if (rtw_time_after(rtw_get_current_time(), ent->exp_time)) {
+				rtw_list_delete(&ent->list);
+				rtw_mfree(ent, sizeof(struct blacklist_ent));
+			} else
+				exist = _TRUE;
+			break;
+		}
+
+		if (rtw_time_after(rtw_get_current_time(), ent->exp_time)) {
+			rtw_list_delete(&ent->list);
+			rtw_mfree(ent, sizeof(struct blacklist_ent));
+		}
+	}
+
+	exit_critical_bh(&blist->lock);
+
+exit:
+	return exist;
+}
+
+void rtw_blacklist_flush(_queue *blist)
+{
+	struct blacklist_ent *ent;
+	_list *list, *head;
+	_list tmp;
+
+	_rtw_init_listhead(&tmp);
+
+	enter_critical_bh(&blist->lock);
+	rtw_list_splice_init(&blist->queue, &tmp);
+	exit_critical_bh(&blist->lock);
+
+	head = &tmp;
+	list = get_next(head);
+	while (rtw_end_of_queue_search(head, list) == _FALSE) {
+		ent = LIST_CONTAINOR(list, struct blacklist_ent, list);
+		list = get_next(list);
+		rtw_list_delete(&ent->list);
+		rtw_mfree(ent, sizeof(struct blacklist_ent));
+	}
+}
+
+void dump_blacklist(void *sel, _queue *blist, const char *title)
+{
+	struct blacklist_ent *ent = NULL;
+	_list *list, *head;
+
+	enter_critical_bh(&blist->lock);
+	head = &blist->queue;
+	list = get_next(head);
+
+	if (rtw_end_of_queue_search(head, list) == _FALSE) {
+		if (title)
+			RTW_PRINT_SEL(sel, "%s:\n", title);
+	
+		while (rtw_end_of_queue_search(head, list) == _FALSE) {
+			ent = LIST_CONTAINOR(list, struct blacklist_ent, list);
+			list = get_next(list);
+
+			if (rtw_time_after(rtw_get_current_time(), ent->exp_time))
+				RTW_PRINT_SEL(sel, MAC_FMT" expired\n", MAC_ARG(ent->addr));
+			else
+				RTW_PRINT_SEL(sel, MAC_FMT" %u\n", MAC_ARG(ent->addr)
+					, rtw_get_remaining_time_ms(ent->exp_time));
+		}
+
+	}
+	exit_critical_bh(&blist->lock);
+}
+
+/**
+* is_null -
+*
+* Return	TRUE if c is null character
+*		FALSE otherwise.
+*/
+inline BOOLEAN is_null(char c)
+{
+	if (c == '\0')
+		return _TRUE;
+	else
+		return _FALSE;
+}
+
+inline BOOLEAN is_all_null(char *c, int len)
+{
+	for (; len > 0; len--)
+		if (c[len - 1] != '\0')
+			return _FALSE;
+
+	return _TRUE;
+}
+
+/**
+* is_eol -
+*
+* Return	TRUE if c is represent for EOL (end of line)
+*		FALSE otherwise.
+*/
+inline BOOLEAN is_eol(char c)
+{
+	if (c == '\r' || c == '\n')
+		return _TRUE;
+	else
+		return _FALSE;
+}
+
+/**
+* is_space -
+*
+* Return	TRUE if c is represent for space
+*		FALSE otherwise.
+*/
+inline BOOLEAN is_space(char c)
+{
+	if (c == ' ' || c == '\t')
+		return _TRUE;
+	else
+		return _FALSE;
+}
+
+/**
+* IsHexDigit -
+*
+* Return	TRUE if chTmp is represent for hex digit
+*		FALSE otherwise.
+*/
+inline BOOLEAN IsHexDigit(char chTmp)
+{
+	if ((chTmp >= '0' && chTmp <= '9') ||
+		(chTmp >= 'a' && chTmp <= 'f') ||
+		(chTmp >= 'A' && chTmp <= 'F'))
+		return _TRUE;
+	else
+		return _FALSE;
+}
+
+/**
+* is_alpha -
+*
+* Return	TRUE if chTmp is represent for alphabet
+*		FALSE otherwise.
+*/
+inline BOOLEAN is_alpha(char chTmp)
+{
+	if ((chTmp >= 'a' && chTmp <= 'z') ||
+		(chTmp >= 'A' && chTmp <= 'Z'))
+		return _TRUE;
+	else
+		return _FALSE;
+}
+
+inline char alpha_to_upper(char c)
+{
+	if ((c >= 'a' && c <= 'z'))
+		c = 'A' + (c - 'a');
+	return c;
+}
+
+int hex2num_i(char c)
+{
+	if (c >= '0' && c <= '9')
+		return c - '0';
+	if (c >= 'a' && c <= 'f')
+		return c - 'a' + 10;
+	if (c >= 'A' && c <= 'F')
+		return c - 'A' + 10;
+	return -1;
+}
+
+int hex2byte_i(const char *hex)
+{
+	int a, b;
+	a = hex2num_i(*hex++);
+	if (a < 0)
+		return -1;
+	b = hex2num_i(*hex++);
+	if (b < 0)
+		return -1;
+	return (a << 4) | b;
+}
+
+int hexstr2bin(const char *hex, u8 *buf, size_t len)
+{
+	size_t i;
+	int a;
+	const char *ipos = hex;
+	u8 *opos = buf;
+
+	for (i = 0; i < len; i++) {
+		a = hex2byte_i(ipos);
+		if (a < 0)
+			return -1;
+		*opos++ = a;
+		ipos += 2;
+	}
+	return 0;
+}
+
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/platform/custom_country_chplan.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/platform/custom_country_chplan.h
--- linux-5.6.3/3rdparty/rtl8821ce/platform/custom_country_chplan.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/platform/custom_country_chplan.h	2020-04-10 16:35:06.857661982 +0300
@@ -0,0 +1,22 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2013 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+
+#error "You have defined CONFIG_CUSTOMIZED_COUNTRY_CHPLAN_MAP to use a customized map of your own instead of the default one"
+#error "Before removing these error notifications, please make sure regulatory certification requirements of your target markets"
+
+static const struct country_chplan CUSTOMIZED_country_chplan_map[] = {
+	COUNTRY_CHPLAN_ENT("TW", 0x76, 1, 0x3FF), /* Taiwan */
+};
+
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/platform/platform_aml_s905_sdio.c linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/platform/platform_aml_s905_sdio.c
--- linux-5.6.3/3rdparty/rtl8821ce/platform/platform_aml_s905_sdio.c	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/platform/platform_aml_s905_sdio.c	2020-04-10 16:35:06.857661982 +0300
@@ -0,0 +1,54 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2016 - 2018 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#include <linux/printk.h>		/* pr_info(() */
+#include <linux/delay.h>		/* msleep() */
+#include "platform_aml_s905_sdio.h"	/* sdio_reinit() and etc */
+
+
+/*
+ * Return:
+ *	0:	power on successfully
+ *	others:	power on failed
+ */
+int platform_wifi_power_on(void)
+{
+	int ret = 0;
+
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 14, 0))
+	ret = wifi_setup_dt();
+	if (ret) {
+		pr_err("%s: setup dt failed!!(%d)\n", __func__, ret);
+		return -1;
+	}
+#endif /* kernel < 3.14.0 */
+
+#if 0 /* Seems redundancy? Already done before insert driver */
+	pr_info("######%s:\n", __func__);
+	extern_wifi_set_enable(0);
+	msleep(500);
+	extern_wifi_set_enable(1);
+	msleep(500);
+	sdio_reinit();
+#endif
+
+	return ret;
+}
+
+void platform_wifi_power_off(void)
+{
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 14, 0))
+	wifi_teardown_dt();
+#endif /* kernel < 3.14.0 */
+}
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/platform/platform_aml_s905_sdio.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/platform/platform_aml_s905_sdio.h
--- linux-5.6.3/3rdparty/rtl8821ce/platform/platform_aml_s905_sdio.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/platform/platform_aml_s905_sdio.h	2020-04-10 16:35:06.857661982 +0300
@@ -0,0 +1,28 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2016 - 2018 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#ifndef __PLATFORM_AML_S905_SDIO_H__
+#define __PLATFORM_AML_S905_SDIO_H__
+
+#include <linux/version.h>	/* Linux vresion */
+
+extern void sdio_reinit(void);
+extern void extern_wifi_set_enable(int is_on);
+
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 14, 0))
+extern void wifi_teardown_dt(void);
+extern int wifi_setup_dt(void);
+#endif /* kernel < 3.14.0 */
+
+#endif /* __PLATFORM_AML_S905_SDIO_H__ */
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/platform/platform_arm_act_sdio.c linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/platform/platform_arm_act_sdio.c
--- linux-5.6.3/3rdparty/rtl8821ce/platform/platform_arm_act_sdio.c	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/platform/platform_arm_act_sdio.c	2020-04-10 16:35:06.857661982 +0300
@@ -0,0 +1,53 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2013 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+/*
+ * Description:
+ *	This file can be applied to following platforms:
+ *    CONFIG_PLATFORM_ACTIONS_ATM703X
+ */
+#include <drv_types.h>
+
+#ifdef CONFIG_PLATFORM_ACTIONS_ATM705X
+extern int acts_wifi_init(void);
+extern void acts_wifi_cleanup(void);
+#endif
+
+/*
+ * Return:
+ *	0:	power on successfully
+ *	others: power on failed
+ */
+int platform_wifi_power_on(void)
+{
+	int ret = 0;
+
+#ifdef CONFIG_PLATFORM_ACTIONS_ATM705X
+	ret = acts_wifi_init();
+	if (unlikely(ret < 0)) {
+		pr_err("%s Failed to register the power control driver.\n", __FUNCTION__);
+		goto exit;
+	}
+#endif
+
+exit:
+	return ret;
+}
+
+void platform_wifi_power_off(void)
+{
+#ifdef CONFIG_PLATFORM_ACTIONS_ATM705X
+	acts_wifi_cleanup();
+#endif
+}
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/platform/platform_ARM_SUN50IW1P1_sdio.c linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/platform/platform_ARM_SUN50IW1P1_sdio.c
--- linux-5.6.3/3rdparty/rtl8821ce/platform/platform_ARM_SUN50IW1P1_sdio.c	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/platform/platform_ARM_SUN50IW1P1_sdio.c	2020-04-10 16:35:06.857661982 +0300
@@ -0,0 +1,86 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2013 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+/*
+ * Description:
+ *	This file can be applied to following platforms:
+ *	CONFIG_PLATFORM_ARM_SUN50IW1P1
+ */
+#include <drv_types.h>
+#ifdef CONFIG_GPIO_WAKEUP
+#include <linux/gpio.h>
+#endif
+
+#ifdef CONFIG_MMC
+#if defined(CONFIG_PLATFORM_ARM_SUN50IW1P1)
+extern void sunxi_mmc_rescan_card(unsigned ids);
+extern void sunxi_wlan_set_power(int on);
+extern int sunxi_wlan_get_bus_index(void);
+extern int sunxi_wlan_get_oob_irq(void);
+extern int sunxi_wlan_get_oob_irq_flags(void);
+#endif
+#ifdef CONFIG_GPIO_WAKEUP
+extern unsigned int oob_irq;
+#endif
+#endif /* CONFIG_MMC */
+
+/*
+ * Return:
+ *	0:	power on successfully
+ *	others: power on failed
+ */
+int platform_wifi_power_on(void)
+{
+	int ret = 0;
+
+#ifdef CONFIG_MMC
+	{
+
+#if defined(CONFIG_PLATFORM_ARM_SUN50IW1P1)
+		int wlan_bus_index = sunxi_wlan_get_bus_index();
+		if (wlan_bus_index < 0)
+			return wlan_bus_index;
+
+		sunxi_wlan_set_power(1);
+		mdelay(100);
+		sunxi_mmc_rescan_card(wlan_bus_index);
+#endif
+		RTW_INFO("%s: power up, rescan card.\n", __FUNCTION__);
+
+#ifdef CONFIG_GPIO_WAKEUP
+#if defined(CONFIG_PLATFORM_ARM_SUN50IW1P1)
+		oob_irq = sunxi_wlan_get_oob_irq();
+#endif
+#endif /* CONFIG_GPIO_WAKEUP */
+	}
+#endif /* CONFIG_MMC */
+
+	return ret;
+}
+
+void platform_wifi_power_off(void)
+{
+#ifdef CONFIG_MMC
+#if defined(CONFIG_PLATFORM_ARM_SUN50IW1P1)
+	int wlan_bus_index = sunxi_wlan_get_bus_index();
+	if (wlan_bus_index < 0)
+		return;
+
+	sunxi_mmc_rescan_card(wlan_bus_index);
+	mdelay(100);
+	sunxi_wlan_set_power(0);
+#endif
+	RTW_INFO("%s: remove card, power off.\n", __FUNCTION__);
+#endif /* CONFIG_MMC */
+}
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/platform/platform_ARM_SUNnI_sdio.c linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/platform/platform_ARM_SUNnI_sdio.c
--- linux-5.6.3/3rdparty/rtl8821ce/platform/platform_ARM_SUNnI_sdio.c	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/platform/platform_ARM_SUNnI_sdio.c	2020-04-10 16:35:06.857661982 +0300
@@ -0,0 +1,130 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2013 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+/*
+ * Description:
+ *	This file can be applied to following platforms:
+ *	CONFIG_PLATFORM_ARM_SUN6I
+ *	CONFIG_PLATFORM_ARM_SUN7I
+ *	CONFIG_PLATFORM_ARM_SUN8I
+ */
+#include <drv_types.h>
+#include <mach/sys_config.h>
+#ifdef CONFIG_GPIO_WAKEUP
+#include <linux/gpio.h>
+#endif
+
+#ifdef CONFIG_MMC
+static int sdc_id = -1;
+static signed int gpio_eint_wlan = -1;
+static u32 eint_wlan_handle = 0;
+
+#if defined(CONFIG_PLATFORM_ARM_SUN6I) || defined(CONFIG_PLATFORM_ARM_SUN7I)
+extern void sw_mci_rescan_card(unsigned id, unsigned insert);
+#elif defined(CONFIG_PLATFORM_ARM_SUN8I)
+extern void sunxi_mci_rescan_card(unsigned id, unsigned insert);
+#endif
+
+#ifdef CONFIG_PLATFORM_ARM_SUN8I_W5P1
+extern int get_rf_mod_type(void);
+#else
+extern int wifi_pm_get_mod_type(void);
+#endif
+
+extern void wifi_pm_power(int on);
+#ifdef CONFIG_GPIO_WAKEUP
+extern unsigned int oob_irq;
+#endif
+#endif /* CONFIG_MMC */
+
+/*
+ * Return:
+ *	0:	power on successfully
+ *	others: power on failed
+ */
+int platform_wifi_power_on(void)
+{
+	int ret = 0;
+
+#ifdef CONFIG_MMC
+	{
+		script_item_u val;
+		script_item_value_type_e type;
+
+#ifdef CONFIG_PLATFORM_ARM_SUN8I_W5P1
+		unsigned int mod_sel = get_rf_mod_type();
+#else
+		unsigned int mod_sel = wifi_pm_get_mod_type();
+#endif
+
+		type = script_get_item("wifi_para", "wifi_sdc_id", &val);
+		if (SCIRPT_ITEM_VALUE_TYPE_INT != type) {
+			RTW_INFO("get wifi_sdc_id failed\n");
+			ret = -1;
+		} else {
+			sdc_id = val.val;
+			RTW_INFO("----- %s sdc_id: %d, mod_sel: %d\n", __FUNCTION__, sdc_id, mod_sel);
+
+#if defined(CONFIG_PLATFORM_ARM_SUN6I) || defined(CONFIG_PLATFORM_ARM_SUN7I)
+			sw_mci_rescan_card(sdc_id, 1);
+#elif defined(CONFIG_PLATFORM_ARM_SUN8I)
+			sunxi_mci_rescan_card(sdc_id, 1);
+#endif
+			mdelay(100);
+			wifi_pm_power(1);
+
+			RTW_INFO("%s: power up, rescan card.\n", __FUNCTION__);
+		}
+
+#ifdef CONFIG_GPIO_WAKEUP
+#ifdef CONFIG_PLATFORM_ARM_SUN8I_W5P1
+		type = script_get_item("wifi_para", "wl_host_wake", &val);
+#else
+#ifdef CONFIG_RTL8723B
+		type = script_get_item("wifi_para", "rtl8723bs_wl_host_wake", &val);
+#endif
+#ifdef CONFIG_RTL8188E
+		type = script_get_item("wifi_para", "rtl8189es_host_wake", &val);
+#endif
+#endif /* CONFIG_PLATFORM_ARM_SUN8I_W5P1 */
+		if (SCIRPT_ITEM_VALUE_TYPE_PIO != type) {
+			RTW_INFO("No definition of wake up host PIN\n");
+			ret = -1;
+		} else {
+			gpio_eint_wlan = val.gpio.gpio;
+#ifdef CONFIG_PLATFORM_ARM_SUN8I
+			oob_irq = gpio_to_irq(gpio_eint_wlan);
+#endif
+		}
+#endif /* CONFIG_GPIO_WAKEUP */
+	}
+#endif /* CONFIG_MMC */
+
+	return ret;
+}
+
+void platform_wifi_power_off(void)
+{
+#ifdef CONFIG_MMC
+#if defined(CONFIG_PLATFORM_ARM_SUN6I) || defined(CONFIG_PLATFORM_ARM_SUN7I)
+	sw_mci_rescan_card(sdc_id, 0);
+#elif defined(CONFIG_PLATFORM_ARM_SUN8I)
+	sunxi_mci_rescan_card(sdc_id, 0);
+#endif
+	mdelay(100);
+	wifi_pm_power(0);
+
+	RTW_INFO("%s: remove card, power off.\n", __FUNCTION__);
+#endif /* CONFIG_MMC */
+}
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/platform/platform_ARM_SUNxI_sdio.c linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/platform/platform_ARM_SUNxI_sdio.c
--- linux-5.6.3/3rdparty/rtl8821ce/platform/platform_ARM_SUNxI_sdio.c	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/platform/platform_ARM_SUNxI_sdio.c	2020-04-10 16:35:06.857661982 +0300
@@ -0,0 +1,90 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2013 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#include <drv_types.h>
+
+#ifdef CONFIG_MMC_SUNXI_POWER_CONTROL
+#ifdef CONFIG_WITS_EVB_V13
+	#define SDIOID	0
+#else /* !CONFIG_WITS_EVB_V13 */
+	#define SDIOID (CONFIG_CHIP_ID == 1123 ? 3 : 1)
+#endif /* !CONFIG_WITS_EVB_V13 */
+
+#define SUNXI_SDIO_WIFI_NUM_RTL8189ES  10
+extern void sunximmc_rescan_card(unsigned id, unsigned insert);
+extern int mmc_pm_get_mod_type(void);
+extern int mmc_pm_gpio_ctrl(char *name, int level);
+/*
+ *	rtl8189es_shdn	= port:PH09<1><default><default><0>
+ *	rtl8189es_wakeup	= port:PH10<1><default><default><1>
+ *	rtl8189es_vdd_en  = port:PH11<1><default><default><0>
+ *	rtl8189es_vcc_en  = port:PH12<1><default><default><0>
+ */
+
+int rtl8189es_sdio_powerup(void)
+{
+	mmc_pm_gpio_ctrl("rtl8189es_vdd_en", 1);
+	udelay(100);
+	mmc_pm_gpio_ctrl("rtl8189es_vcc_en", 1);
+	udelay(50);
+	mmc_pm_gpio_ctrl("rtl8189es_shdn", 1);
+	return 0;
+}
+
+int rtl8189es_sdio_poweroff(void)
+{
+	mmc_pm_gpio_ctrl("rtl8189es_shdn", 0);
+	mmc_pm_gpio_ctrl("rtl8189es_vcc_en", 0);
+	mmc_pm_gpio_ctrl("rtl8189es_vdd_en", 0);
+	return 0;
+}
+#endif /* CONFIG_MMC_SUNXI_POWER_CONTROL */
+
+/*
+ * Return:
+ *	0:	power on successfully
+ *	others:	power on failed
+ */
+int platform_wifi_power_on(void)
+{
+	int ret = 0;
+#ifdef CONFIG_MMC_SUNXI_POWER_CONTROL
+	unsigned int mod_sel = mmc_pm_get_mod_type();
+#endif /* CONFIG_MMC_SUNXI_POWER_CONTROL */
+
+
+#ifdef CONFIG_MMC_SUNXI_POWER_CONTROL
+	if (mod_sel == SUNXI_SDIO_WIFI_NUM_RTL8189ES) {
+		rtl8189es_sdio_powerup();
+		sunximmc_rescan_card(SDIOID, 1);
+		printk("[rtl8189es] %s: power up, rescan card.\n", __FUNCTION__);
+	} else {
+		ret = -1;
+		printk("[rtl8189es] %s: mod_sel = %d is incorrect.\n", __FUNCTION__, mod_sel);
+	}
+#endif /* CONFIG_MMC_SUNXI_POWER_CONTROL */
+
+	return ret;
+}
+
+void platform_wifi_power_off(void)
+{
+#ifdef CONFIG_MMC_SUNXI_POWER_CONTROL
+	sunximmc_rescan_card(SDIOID, 0);
+#ifdef CONFIG_RTL8188E
+	rtl8189es_sdio_poweroff();
+	printk("[rtl8189es] %s: remove card, power off.\n", __FUNCTION__);
+#endif /* CONFIG_RTL8188E */
+#endif /* CONFIG_MMC_SUNXI_POWER_CONTROL */
+}
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/platform/platform_ARM_SUNxI_usb.c linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/platform/platform_ARM_SUNxI_usb.c
--- linux-5.6.3/3rdparty/rtl8821ce/platform/platform_ARM_SUNxI_usb.c	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/platform/platform_ARM_SUNxI_usb.c	2020-04-10 16:35:06.857661982 +0300
@@ -0,0 +1,136 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2013 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+/*
+ * Description:
+ *	This file can be applied to following platforms:
+ *	CONFIG_PLATFORM_ARM_SUNXI Series platform
+ *
+ */
+
+#include <drv_types.h>
+#include <mach/sys_config.h>
+
+#ifdef CONFIG_PLATFORM_ARM_SUNxI
+extern int sw_usb_disable_hcd(__u32 usbc_no);
+extern int sw_usb_enable_hcd(__u32 usbc_no);
+static int usb_wifi_host = 2;
+#endif
+
+#if defined(CONFIG_PLATFORM_ARM_SUN6I) || defined(CONFIG_PLATFORM_ARM_SUN7I)
+extern int sw_usb_disable_hcd(__u32 usbc_no);
+extern int sw_usb_enable_hcd(__u32 usbc_no);
+extern void wifi_pm_power(int on);
+static script_item_u item;
+#endif
+
+#ifdef CONFIG_PLATFORM_ARM_SUN8I
+extern int sunxi_usb_disable_hcd(__u32 usbc_no);
+extern int sunxi_usb_enable_hcd(__u32 usbc_no);
+extern void wifi_pm_power(int on);
+static script_item_u item;
+#endif
+
+
+int platform_wifi_power_on(void)
+{
+	int ret = 0;
+
+#ifdef CONFIG_PLATFORM_ARM_SUNxI
+#ifndef CONFIG_RTL8723A
+	{
+		/* ----------get usb_wifi_usbc_num------------- */
+		ret = script_parser_fetch("usb_wifi_para", "usb_wifi_usbc_num", (int *)&usb_wifi_host, 64);
+		if (ret != 0) {
+			RTW_INFO("ERR: script_parser_fetch usb_wifi_usbc_num failed\n");
+			ret = -ENOMEM;
+			goto exit;
+		}
+		RTW_INFO("sw_usb_enable_hcd: usbc_num = %d\n", usb_wifi_host);
+		sw_usb_enable_hcd(usb_wifi_host);
+	}
+#endif /* CONFIG_RTL8723A */
+#endif /* CONFIG_PLATFORM_ARM_SUNxI */
+
+#if defined(CONFIG_PLATFORM_ARM_SUN6I) || defined(CONFIG_PLATFORM_ARM_SUN7I)
+	{
+		script_item_value_type_e type;
+
+		type = script_get_item("wifi_para", "wifi_usbc_id", &item);
+		if (SCIRPT_ITEM_VALUE_TYPE_INT != type) {
+			printk("ERR: script_get_item wifi_usbc_id failed\n");
+			ret = -ENOMEM;
+			goto exit;
+		}
+
+		printk("sw_usb_enable_hcd: usbc_num = %d\n", item.val);
+		wifi_pm_power(1);
+		mdelay(10);
+
+#if !(defined(CONFIG_RTL8723A)) && !(defined(CONFIG_RTL8723B))
+		sw_usb_enable_hcd(item.val);
+#endif
+	}
+#endif /* defined(CONFIG_PLATFORM_ARM_SUN6I) || defined(CONFIG_PLATFORM_ARM_SUN7I) */
+
+#if defined(CONFIG_PLATFORM_ARM_SUN8I)
+	{
+		script_item_value_type_e type;
+
+		type = script_get_item("wifi_para", "wifi_usbc_id", &item);
+		if (SCIRPT_ITEM_VALUE_TYPE_INT != type) {
+			printk("ERR: script_get_item wifi_usbc_id failed\n");
+			ret = -ENOMEM;
+			goto exit;
+		}
+
+		printk("sw_usb_enable_hcd: usbc_num = %d\n", item.val);
+		wifi_pm_power(1);
+		mdelay(10);
+
+#if !(defined(CONFIG_RTL8723A)) && !(defined(CONFIG_RTL8723B))
+		sunxi_usb_enable_hcd(item.val);
+#endif
+	}
+#endif /* CONFIG_PLATFORM_ARM_SUN8I */
+
+exit:
+	return ret;
+}
+
+void platform_wifi_power_off(void)
+{
+
+#ifdef CONFIG_PLATFORM_ARM_SUNxI
+#ifndef CONFIG_RTL8723A
+	RTW_INFO("sw_usb_disable_hcd: usbc_num = %d\n", usb_wifi_host);
+	sw_usb_disable_hcd(usb_wifi_host);
+#endif /* ifndef CONFIG_RTL8723A */
+#endif /* CONFIG_PLATFORM_ARM_SUNxI */
+
+#if defined(CONFIG_PLATFORM_ARM_SUN6I) || defined(CONFIG_PLATFORM_ARM_SUN7I)
+	#if !(defined(CONFIG_RTL8723A)) && !(defined(CONFIG_RTL8723B))
+	sw_usb_disable_hcd(item.val);
+	#endif
+	wifi_pm_power(0);
+#endif /* defined(CONFIG_PLATFORM_ARM_SUN6I) || defined(CONFIG_PLATFORM_ARM_SUN7I) */
+
+#if defined(CONFIG_PLATFORM_ARM_SUN8I)
+	#if !(defined(CONFIG_RTL8723A)) && !(defined(CONFIG_RTL8723B))
+	sunxi_usb_disable_hcd(item.val);
+	#endif
+	wifi_pm_power(0);
+#endif /* defined(CONFIG_PLATFORM_ARM_SUN8I) */
+
+}
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/platform/platform_ARM_WMT_sdio.c linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/platform/platform_ARM_WMT_sdio.c
--- linux-5.6.3/3rdparty/rtl8821ce/platform/platform_ARM_WMT_sdio.c	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/platform/platform_ARM_WMT_sdio.c	2020-04-10 16:35:06.857661982 +0300
@@ -0,0 +1,46 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2013 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#include <drv_types.h>
+#include <mach/wmt_iomux.h>
+#include <linux/gpio.h>
+
+extern void wmt_detect_sdio2(void);
+extern void force_remove_sdio2(void);
+
+int platform_wifi_power_on(void)
+{
+	int err = 0;
+	err = gpio_request(WMT_PIN_GP62_SUSGPIO1, "wifi_chip_en");
+	if (err < 0) {
+		printk("request gpio for rtl8188eu failed!\n");
+		return err;
+	}
+	gpio_direction_output(WMT_PIN_GP62_SUSGPIO1, 0);/* pull sus_gpio1 to 0 to open vcc_wifi. */
+	printk("power on rtl8189.\n");
+	msleep(500);
+	wmt_detect_sdio2();
+	printk("[rtl8189es] %s: new card, power on.\n", __FUNCTION__);
+	return err;
+}
+
+void platform_wifi_power_off(void)
+{
+	force_remove_sdio2();
+
+	gpio_direction_output(WMT_PIN_GP62_SUSGPIO1, 1);/* pull sus_gpio1 to 1 to close vcc_wifi. */
+	printk("power off rtl8189.\n");
+	gpio_free(WMT_PIN_GP62_SUSGPIO1);
+	printk("[rtl8189es] %s: remove card, power off.\n", __FUNCTION__);
+}
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/platform/platform_hisilicon_hi3798_sdio.c linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/platform/platform_hisilicon_hi3798_sdio.c
--- linux-5.6.3/3rdparty/rtl8821ce/platform/platform_hisilicon_hi3798_sdio.c	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/platform/platform_hisilicon_hi3798_sdio.c	2020-04-10 16:35:06.857661982 +0300
@@ -0,0 +1,110 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2017 - 2018 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#include <linux/delay.h>		/* mdelay() */
+#include <mach/hardware.h>		/* __io_address(), readl(), writel() */
+#include "platform_hisilicon_hi3798_sdio.h"	/* HI_S32() and etc. */
+
+typedef enum hi_GPIO_DIR_E {
+	HI_DIR_OUT = 0,
+	HI_DIR_IN  = 1,
+} HI_GPIO_DIR_E;
+
+#define RTL_REG_ON_GPIO		(4*8 + 3)
+
+#define REG_BASE_CTRL		__io_address(0xf8a20008)
+
+int gpio_wlan_reg_on = RTL_REG_ON_GPIO;
+#if 0
+module_param(gpio_wlan_reg_on, uint, 0644);
+MODULE_PARM_DESC(gpio_wlan_reg_on, "wlan reg_on gpio num (default:gpio4_3)");
+#endif
+
+static int hi_gpio_set_value(u32 gpio, u32 value)
+{
+	HI_S32 s32Status;
+
+	s32Status = HI_DRV_GPIO_SetDirBit(gpio, HI_DIR_OUT);
+	if (s32Status != HI_SUCCESS) {
+		pr_err("gpio(%d) HI_DRV_GPIO_SetDirBit HI_DIR_OUT failed\n",
+			gpio);
+		return -1;
+	}
+
+	s32Status = HI_DRV_GPIO_WriteBit(gpio, value);
+	if (s32Status != HI_SUCCESS) {
+		pr_err("gpio(%d) HI_DRV_GPIO_WriteBit value(%d) failed\n",
+			gpio, value);
+		return -1;
+	}
+
+	return 0;
+}
+
+static int hisi_wlan_set_carddetect(bool present)
+{
+	u32 regval;
+	u32 mask;
+
+
+#ifndef CONFIG_HISI_SDIO_ID
+	return;
+#endif
+	pr_info("SDIO ID=%d\n", CONFIG_HISI_SDIO_ID);
+#if (CONFIG_HISI_SDIO_ID == 1)
+	mask = 1;
+#elif (CONFIG_HISI_SDIO_ID == 0)
+	mask = 2;
+#endif
+
+	regval = readl(REG_BASE_CTRL);
+	if (present) {
+		pr_info("====== Card detection to detect SDIO card! ======\n");
+		/* set card_detect low to detect card */
+		regval |= mask;
+	} else {
+		pr_info("====== Card detection to remove SDIO card! ======\n");
+		/* set card_detect high to remove card */
+		regval &= ~(mask);
+	}
+	writel(regval, REG_BASE_CTRL);
+
+	return 0;
+}
+
+/*
+ * Return:
+ *	0:	power on successfully
+ *	others: power on failed
+ */
+int platform_wifi_power_on(void)
+{
+	int ret = 0;
+
+
+	hi_gpio_set_value(gpio_wlan_reg_on, 1);
+	mdelay(100);
+	hisi_wlan_set_carddetect(1);
+	mdelay(2000);
+	pr_info("======== set_carddetect delay 2s! ========\n");
+
+	return ret;
+}
+
+void platform_wifi_power_off(void)
+{
+	hisi_wlan_set_carddetect(0);
+	mdelay(100);
+	hi_gpio_set_value(gpio_wlan_reg_on, 0);
+}
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/platform/platform_hisilicon_hi3798_sdio.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/platform/platform_hisilicon_hi3798_sdio.h
--- linux-5.6.3/3rdparty/rtl8821ce/platform/platform_hisilicon_hi3798_sdio.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/platform/platform_hisilicon_hi3798_sdio.h	2020-04-10 16:35:06.857661982 +0300
@@ -0,0 +1,28 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2017 - 2018 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#ifndef __PLATFORM_HISILICON_HI3798_SDIO_H__
+#define __PLATFORM_HISILICON_HI3798_SDIO_H__
+
+typedef unsigned int	HI_U32;
+
+typedef int		HI_S32;
+
+#define HI_SUCCESS	0
+#define HI_FAILURE	(-1)
+
+extern HI_S32 HI_DRV_GPIO_SetDirBit(HI_U32 u32GpioNo, HI_U32 u32DirBit);
+extern HI_S32 HI_DRV_GPIO_WriteBit(HI_U32 u32GpioNo, HI_U32 u32BitValue);
+
+#endif /* __PLATFORM_HISILICON_HI3798_SDIO_H__ */
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/platform/platform_ops.c linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/platform/platform_ops.c
--- linux-5.6.3/3rdparty/rtl8821ce/platform/platform_ops.c	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/platform/platform_ops.c	2020-04-10 16:35:06.857661982 +0300
@@ -0,0 +1,32 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2013 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#ifndef CONFIG_PLATFORM_OPS
+/*
+ * Return:
+ *	0:	power on successfully
+ *	others: power on failed
+ */
+int platform_wifi_power_on(void)
+{
+	int ret = 0;
+
+
+	return ret;
+}
+
+void platform_wifi_power_off(void)
+{
+}
+#endif /* !CONFIG_PLATFORM_OPS */
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/platform/platform_ops.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/platform/platform_ops.h
--- linux-5.6.3/3rdparty/rtl8821ce/platform/platform_ops.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/platform/platform_ops.h	2020-04-10 16:35:06.857661982 +0300
@@ -0,0 +1,26 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2013 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#ifndef __PLATFORM_OPS_H__
+#define __PLATFORM_OPS_H__
+
+/*
+ * Return:
+ *	0:	power on successfully
+ *	others: power on failed
+ */
+int platform_wifi_power_on(void);
+void platform_wifi_power_off(void);
+
+#endif /* __PLATFORM_OPS_H__ */
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/platform/platform_RTK_DMP_usb.c linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/platform/platform_RTK_DMP_usb.c
--- linux-5.6.3/3rdparty/rtl8821ce/platform/platform_RTK_DMP_usb.c	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/platform/platform_RTK_DMP_usb.c	2020-04-10 16:35:06.857661982 +0300
@@ -0,0 +1,30 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2013 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#include <drv_types.h>
+
+int platform_wifi_power_on(void)
+{
+	int ret = 0;
+	u32 tmp;
+	tmp = readl((volatile unsigned int *)0xb801a608);
+	tmp &= 0xffffff00;
+	tmp |= 0x55;
+	writel(tmp, (volatile unsigned int *)0xb801a608); /* write dummy register for 1055 */
+	return ret;
+}
+
+void platform_wifi_power_off(void)
+{
+}
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/platform/platform_sprd_sdio.c linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/platform/platform_sprd_sdio.c
--- linux-5.6.3/3rdparty/rtl8821ce/platform/platform_sprd_sdio.c	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/platform/platform_sprd_sdio.c	2020-04-10 16:35:06.857661982 +0300
@@ -0,0 +1,84 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2013 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#include <drv_types.h>
+
+extern void sdhci_bus_scan(void);
+#ifndef ANDROID_2X
+extern int sdhci_device_attached(void);
+#endif
+
+/*
+ * Return:
+ *	0:	power on successfully
+ *	others:	power on failed
+ */
+int platform_wifi_power_on(void)
+{
+	int ret = 0;
+
+
+#ifdef CONFIG_RTL8188E
+	rtw_wifi_gpio_wlan_ctrl(WLAN_POWER_ON);
+#endif /* CONFIG_RTL8188E */
+
+	/* Pull up pwd pin, make wifi leave power down mode. */
+	rtw_wifi_gpio_init();
+	rtw_wifi_gpio_wlan_ctrl(WLAN_PWDN_ON);
+
+#if (MP_DRIVER == 1) && (defined(CONFIG_RTL8723A) || defined(CONFIG_RTL8723B))
+	/* Pull up BT reset pin. */
+	rtw_wifi_gpio_wlan_ctrl(WLAN_BT_PWDN_ON);
+#endif
+	rtw_mdelay_os(5);
+
+	sdhci_bus_scan();
+#ifdef CONFIG_RTL8723B
+	/* YJ,test,130305 */
+	rtw_mdelay_os(1000);
+#endif
+#ifdef ANDROID_2X
+	rtw_mdelay_os(200);
+#else /* !ANDROID_2X */
+	if (1) {
+		int i = 0;
+
+		for (i = 0; i <= 50; i++) {
+			msleep(10);
+			if (sdhci_device_attached())
+				break;
+			printk("%s delay times:%d\n", __func__, i);
+		}
+	}
+#endif /* !ANDROID_2X */
+
+	return ret;
+}
+
+void platform_wifi_power_off(void)
+{
+	/* Pull down pwd pin, make wifi enter power down mode. */
+	rtw_wifi_gpio_wlan_ctrl(WLAN_PWDN_OFF);
+	rtw_mdelay_os(5);
+	rtw_wifi_gpio_deinit();
+
+#ifdef CONFIG_RTL8188E
+	rtw_wifi_gpio_wlan_ctrl(WLAN_POWER_OFF);
+#endif /* CONFIG_RTL8188E */
+
+#ifdef CONFIG_WOWLAN
+	if (mmc_host)
+		mmc_host->pm_flags &= ~MMC_PM_KEEP_POWER;
+#endif /* CONFIG_WOWLAN */
+}
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/platform/platform_zte_zx296716_sdio.c linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/platform/platform_zte_zx296716_sdio.c
--- linux-5.6.3/3rdparty/rtl8821ce/platform/platform_zte_zx296716_sdio.c	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/platform/platform_zte_zx296716_sdio.c	2020-04-10 16:35:06.857661982 +0300
@@ -0,0 +1,53 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2016 - 2018 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#include <linux/printk.h>		/* pr_info(() */
+#include <linux/delay.h>		/* msleep() */
+#include "platform_zte_zx296716_sdio.h"	/* sdio_reinit() and etc */
+
+
+/*
+ * Return:
+ *	0:	power on successfully
+ *	others:	power on failed
+ */
+int platform_wifi_power_on(void)
+{
+	int ret = 0;
+
+	pr_info("######%s: disable--1--\n", __func__);
+	extern_wifi_set_enable(0);
+	/*msleep(500);*/ /* add in function:extern_wifi_set_enable */
+	pr_info("######%s: enable--2---\n", __func__);
+	extern_wifi_set_enable(1);
+	/*msleep(500);*/
+	sdio_reinit();
+
+	return ret;
+}
+
+void platform_wifi_power_off(void)
+{
+	int card_val;
+
+	pr_info("######%s:\n", __func__);
+#ifdef CONFIG_A16T03_BOARD
+	card_val = sdio_host_is_null();
+	if (card_val)
+		remove_card();
+#endif /* CONFIG_A16T03_BOARD */
+	extern_wifi_set_enable(0);
+
+	/*msleep(500);*/
+}
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/platform/platform_zte_zx296716_sdio.h linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/platform/platform_zte_zx296716_sdio.h
--- linux-5.6.3/3rdparty/rtl8821ce/platform/platform_zte_zx296716_sdio.h	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/platform/platform_zte_zx296716_sdio.h	2020-04-10 16:35:06.857661982 +0300
@@ -0,0 +1,25 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2016 - 2018 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#ifndef __PLATFORM_ZTE_ZX296716_SDIO_H__
+#define __PLATFORM_ZTE_ZX296716_SDIO_H__
+
+extern void sdio_reinit(void);
+extern void extern_wifi_set_enable(int val);
+#ifdef CONFIG_A16T03_BOARD
+extern int sdio_host_is_null(void);
+extern void remove_card(void);
+#endif /* CONFIG_A16T03_BOARD */
+
+#endif /* __PLATFORM_ZTE_ZX296716_SDIO_H__ */
diff -Nurp linux-5.6.3/3rdparty/rtl8821ce/rtl8821c.mk linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/rtl8821c.mk
--- linux-5.6.3/3rdparty/rtl8821ce/rtl8821c.mk	1970-01-01 02:00:00.000000000 +0200
+++ linux-5.6.3-rtl8821ce/3rdparty/rtl8821ce/rtl8821c.mk	2020-04-10 16:35:06.857661982 +0300
@@ -0,0 +1,45 @@
+EXTRA_CFLAGS += -DCONFIG_RTL8821C
+
+ifeq ($(CONFIG_USB_HCI), y)
+FILE_NAME = 8821cu
+endif
+ifeq ($(CONFIG_PCI_HCI), y)
+FILE_NAME = 8821ce
+endif
+ifeq ($(CONFIG_SDIO_HCI), y)
+FILE_NAME = 8821cs
+endif
+
+_HAL_INTFS_FILES +=	hal/rtl8821c/rtl8821c_halinit.o \
+			hal/rtl8821c/rtl8821c_mac.o \
+			hal/rtl8821c/rtl8821c_cmd.o \
+			hal/rtl8821c/rtl8821c_phy.o \
+			hal/rtl8821c/rtl8821c_dm.o \
+			hal/rtl8821c/rtl8821c_ops.o \
+			hal/rtl8821c/hal8821c_fw.o
+
+_HAL_INTFS_FILES +=	hal/rtl8821c/$(HCI_NAME)/rtl$(FILE_NAME)_halinit.o \
+			hal/rtl8821c/$(HCI_NAME)/rtl$(FILE_NAME)_halmac.o \
+			hal/rtl8821c/$(HCI_NAME)/rtl$(FILE_NAME)_io.o \
+			hal/rtl8821c/$(HCI_NAME)/rtl$(FILE_NAME)_xmit.o \
+			hal/rtl8821c/$(HCI_NAME)/rtl$(FILE_NAME)_recv.o \
+			hal/rtl8821c/$(HCI_NAME)/rtl$(FILE_NAME)_led.o \
+			hal/rtl8821c/$(HCI_NAME)/rtl$(FILE_NAME)_ops.o
+
+ifeq ($(CONFIG_SDIO_HCI), y)
+_HAL_INTFS_FILES +=hal/efuse/$(RTL871X)/HalEfuseMask8821C_SDIO.o
+endif
+ifeq ($(CONFIG_USB_HCI), y)
+_HAL_INTFS_FILES +=hal/efuse/$(RTL871X)/HalEfuseMask8821C_USB.o
+endif
+ifeq ($(CONFIG_PCI_HCI), y)
+_HAL_INTFS_FILES +=hal/efuse/$(RTL871X)/HalEfuseMask8821C_PCIE.o
+endif
+
+include $(TopDIR)/halmac.mk
+
+_BTC_FILES += hal/btc/halbtc8821cwifionly.o
+ifeq ($(CONFIG_BT_COEXIST), y)
+_BTC_FILES += hal/btc/halbtc8821c1ant.o \
+				hal/btc/halbtc8821c2ant.o
+endif
